diff --git a/.clang-format b/.clang-format
new file mode 100644
index 00000000000..8f47348794d
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,246 @@
+# Clang format version: 18.1.3
+---
+BasedOnStyle: LLVM
+AccessModifierOffset: -2
+AlignAfterOpenBracket: BlockIndent
+AlignArrayOfStructures: None
+AlignConsecutiveAssignments:
+  Enabled: false
+  AcrossEmptyLines: false
+  AcrossComments: false
+  AlignCompound: false
+  AlignFunctionPointers: false
+  PadOperators: true
+AlignConsecutiveBitFields:
+  Enabled: true
+  AcrossEmptyLines: false
+  AcrossComments: false
+  AlignCompound: false
+  AlignFunctionPointers: false
+  PadOperators: false
+AlignConsecutiveDeclarations:
+  Enabled: false
+  AcrossEmptyLines: false
+  AcrossComments: false
+  AlignCompound: false
+  AlignFunctionPointers: false
+  PadOperators: false
+AlignConsecutiveMacros:
+  Enabled: true
+  AcrossEmptyLines: false
+  AcrossComments: false
+  AlignCompound: false
+  AlignFunctionPointers: false
+  PadOperators: false
+AlignConsecutiveShortCaseStatements:
+  Enabled: true
+  AcrossEmptyLines: false
+  AcrossComments: false
+  AlignCaseColons: false
+AlignEscapedNewlines: Left
+AlignOperands: Align
+AlignTrailingComments:
+  Kind: Always
+  OverEmptyLines: 0
+AllowAllArgumentsOnNextLine: true
+AllowAllParametersOfDeclarationOnNextLine: true
+AllowBreakBeforeNoexceptSpecifier: Never
+AllowShortBlocksOnASingleLine: Empty
+AllowShortCaseLabelsOnASingleLine: true
+AllowShortCompoundRequirementOnASingleLine: true
+AllowShortEnumsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: Empty
+AllowShortIfStatementsOnASingleLine: Never
+AllowShortLambdasOnASingleLine: Empty
+AllowShortLoopsOnASingleLine: true
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AlwaysBreakTemplateDeclarations: MultiLine
+AttributeMacros:
+  - __capability
+BinPackArguments: true
+BinPackParameters: true
+BitFieldColonSpacing: Both
+BraceWrapping:
+  AfterCaseLabel: true
+  AfterClass: false
+  AfterControlStatement: Never
+  AfterEnum: false
+  AfterFunction: false
+  AfterNamespace: false
+  AfterObjCDeclaration: false
+  AfterStruct: false
+  AfterUnion: false
+  AfterExternBlock: false
+  BeforeCatch: false
+  BeforeElse: false
+  BeforeLambdaBody: false
+  BeforeWhile: false
+  IndentBraces: false
+  SplitEmptyFunction: false
+  SplitEmptyRecord: true
+  SplitEmptyNamespace: true
+BreakAdjacentStringLiterals: true
+BreakAfterAttributes: Always
+BreakAfterJavaFieldAnnotations: false
+BreakArrays: false
+BreakBeforeBinaryOperators: NonAssignment
+BreakBeforeBraces: Custom
+BreakBeforeConceptDeclarations: Always
+BreakBeforeInlineASMColon: OnlyMultiline
+BreakBeforeTernaryOperators: true
+BreakConstructorInitializers: BeforeColon
+BreakInheritanceList: BeforeColon
+BreakStringLiterals: true
+ColumnLimit: 160
+CommentPragmas: ""
+CompactNamespaces: false
+ConstructorInitializerIndentWidth: 2
+ContinuationIndentWidth: 2
+Cpp11BracedListStyle: true
+DerivePointerAlignment: false
+DisableFormat: false
+EmptyLineAfterAccessModifier: Never
+EmptyLineBeforeAccessModifier: LogicalBlock
+ExperimentalAutoDetectBinPacking: false
+FixNamespaceComments: true
+ForEachMacros:
+  - foreach
+  - Q_FOREACH
+  - BOOST_FOREACH
+IfMacros:
+  - KJ_IF_MAYBE
+IncludeBlocks: Preserve
+IncludeCategories:
+  - Regex: ^"(llvm|llvm-c|clang|clang-c)/
+    Priority: 2
+    SortPriority: 0
+    CaseSensitive: false
+  - Regex: ^(<|"(gtest|gmock|isl|json)/)
+    Priority: 3
+    SortPriority: 0
+    CaseSensitive: false
+  - Regex: .*
+    Priority: 1
+    SortPriority: 0
+    CaseSensitive: false
+IncludeIsMainRegex: ""
+IncludeIsMainSourceRegex: ""
+IndentAccessModifiers: false
+IndentCaseBlocks: false
+IndentCaseLabels: true
+IndentExternBlock: NoIndent
+IndentGotoLabels: false
+IndentPPDirectives: None
+IndentRequiresClause: false
+IndentWidth: 2
+IndentWrappedFunctionNames: true
+InsertBraces: true
+InsertNewlineAtEOF: true
+InsertTrailingCommas: None
+IntegerLiteralSeparator:
+  Binary: 0
+  BinaryMinDigits: 0
+  Decimal: 0
+  DecimalMinDigits: 0
+  Hex: 0
+  HexMinDigits: 0
+JavaScriptQuotes: Leave
+JavaScriptWrapImports: true
+KeepEmptyLinesAtEOF: false
+KeepEmptyLinesAtTheStartOfBlocks: true
+LambdaBodyIndentation: Signature
+Language: Cpp
+LineEnding: LF
+MacroBlockBegin: ""
+MacroBlockEnd: ""
+MaxEmptyLinesToKeep: 1
+NamespaceIndentation: None
+ObjCBinPackProtocolList: Auto
+ObjCBlockIndentWidth: 2
+ObjCBreakBeforeNestedBlockParam: true
+ObjCSpaceAfterProperty: false
+ObjCSpaceBeforeProtocolList: true
+PPIndentWidth: -1
+PackConstructorInitializers: BinPack
+PenaltyBreakAssignment: 2
+PenaltyBreakBeforeFirstCallParameter: 19
+PenaltyBreakComment: 300
+PenaltyBreakFirstLessLess: 120
+PenaltyBreakOpenParenthesis: 0
+PenaltyBreakScopeResolution: 500
+PenaltyBreakString: 1000
+PenaltyBreakTemplateDeclaration: 10
+PenaltyExcessCharacter: 1000000
+PenaltyIndentedWhitespace: 0
+PenaltyReturnTypeOnItsOwnLine: 60
+PointerAlignment: Right
+QualifierAlignment: Leave
+ReferenceAlignment: Pointer
+ReflowComments: false
+RemoveBracesLLVM: false
+RemoveParentheses: Leave
+RemoveSemicolon: false
+RequiresClausePosition: OwnLine
+RequiresExpressionIndentation: OuterScope
+SeparateDefinitionBlocks: Leave
+ShortNamespaceLines: 1
+SkipMacroDefinitionBody: false
+SortIncludes: Never
+SortJavaStaticImport: Before
+SortUsingDeclarations: LexicographicNumeric
+SpaceAfterCStyleCast: false
+SpaceAfterLogicalNot: false
+SpaceAfterTemplateKeyword: false
+SpaceAroundPointerQualifiers: Default
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCaseColon: false
+SpaceBeforeCpp11BracedList: false
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeJsonColon: false
+SpaceBeforeParens: ControlStatements
+SpaceBeforeParensOptions:
+  AfterControlStatements: true
+  AfterForeachMacros: true
+  AfterFunctionDeclarationName: false
+  AfterFunctionDefinitionName: false
+  AfterIfMacros: true
+  AfterOverloadedOperator: true
+  AfterPlacementOperator: true
+  AfterRequiresInClause: false
+  AfterRequiresInExpression: false
+  BeforeNonEmptyParentheses: false
+SpaceBeforeRangeBasedForLoopColon: true
+SpaceBeforeSquareBrackets: false
+SpaceInEmptyBlock: false
+SpacesBeforeTrailingComments: 2
+SpacesInAngles: Never
+SpacesInContainerLiterals: false
+SpacesInLineCommentPrefix:
+  Minimum: 1
+  Maximum: -1
+SpacesInParens: Never
+SpacesInParensOptions:
+  InConditionalStatements: false
+  InCStyleCasts: false
+  InEmptyParentheses: false
+  Other: false
+SpacesInSquareBrackets: false
+Standard: Auto
+StatementAttributeLikeMacros:
+  - Q_EMIT
+StatementMacros:
+  - Q_UNUSED
+  - QT_REQUIRE_VERSION
+TabWidth: 2
+UseTab: Never
+VerilogBreakBetweenInstancePorts: true
+WhitespaceSensitiveMacros:
+  - BOOST_PP_STRINGIZE
+  - CF_SWIFT_NAME
+  - NS_SWIFT_NAME
+  - PP_STRINGIZE
+  - STRINGIZE
+BracedInitializerIndentWidth: 2
diff --git a/.codespellrc b/.codespellrc
new file mode 100644
index 00000000000..d3b9b45cb1e
--- /dev/null
+++ b/.codespellrc
@@ -0,0 +1,8 @@
+[codespell]
+# Source: https://github.com/arduino/tooling-project-assets/blob/main/workflow-templates/assets/spell-check/.codespellrc
+# In the event of a false positive, add the problematic word, in all lowercase, to a comma-separated list here:
+ignore-words-list = ba,licence,ot,dout,als,exten,emac
+skip = ./.git,./.licenses,__pycache__,.clang-format,.codespellrc,.editorconfig,.flake8,.prettierignore,.yamllint.yml,.gitignore,boards.txt,platform.txt,programmers.txt
+builtin = clear,informal,en-GB_to_en-US
+check-filenames =
+check-hidden =
diff --git a/.editorconfig b/.editorconfig
new file mode 100644
index 00000000000..e22936cb1fe
--- /dev/null
+++ b/.editorconfig
@@ -0,0 +1,60 @@
+# Source: https://github.com/arduino/tooling-project-assets/blob/main/workflow-templates/assets/general/.editorconfig
+# See: https://editorconfig.org/
+# The formatting style defined in this file is the official standardized style to be used in all Arduino Tooling
+# projects and should not be modified.
+# Note: indent style for each file type is defined even when it matches the universal config in order to make it clear
+# that this type has an official style.
+
+[*]
+charset = utf-8
+end_of_line = lf
+indent_size = 2
+indent_style = space
+insert_final_newline = true
+trim_trailing_whitespace = true
+
+[*.{adoc,asc,asciidoc}]
+indent_size = 2
+indent_style = space
+
+[*.{bash,sh}]
+indent_size = 4
+indent_style = space
+
+[*.{c,cc,cp,cpp,cxx,h,hh,hpp,hxx,ii,inl,ino,ixx,pde,tpl,tpp,txx}]
+indent_size = 2
+indent_style = space
+
+[*.{go,mod}]
+indent_style = tab
+
+[*.java]
+indent_size = 2
+indent_style = space
+
+[*.{js,jsx,json,jsonc,json5,ts,tsx}]
+indent_size = 2
+indent_style = space
+
+[*.{md,mdx,mkdn,mdown,markdown}]
+indent_size = unset
+indent_style = space
+
+[*.proto]
+indent_size = 2
+indent_style = space
+
+[*.py]
+indent_size = 4
+indent_style = space
+
+[*.svg]
+indent_size = 2
+indent_style = space
+
+[*.{yaml,yml}]
+indent_size = 2
+indent_style = space
+
+[{.gitconfig,.gitmodules}]
+indent_style = tab
diff --git a/.flake8 b/.flake8
new file mode 100644
index 00000000000..5a2ed0b5b7f
--- /dev/null
+++ b/.flake8
@@ -0,0 +1,10 @@
+# Source: https://github.com/arduino/tooling-project-assets/blob/main/workflow-templates/assets/check-python/.flake8
+# See: https://flake8.pycqa.org/en/latest/user/configuration.html
+
+[flake8]
+doctests = True
+# W503 and W504 are mutually exclusive. PEP 8 recommends line break before.
+ignore = W503,E203
+max-complexity = 20
+max-line-length = 120
+select = E,W,F,C,N
diff --git a/.github/ISSUE_TEMPLATE/Feature-request.yml b/.github/ISSUE_TEMPLATE/Feature-request.yml
new file mode 100644
index 00000000000..8849a407a39
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/Feature-request.yml
@@ -0,0 +1,63 @@
+name: Feature request
+description: Suggest an idea for this project
+labels: ["Type: Feature request"]
+body:
+  - type: markdown
+    attributes:
+      value: |
+        * Please note that we can only process feature requests reported in English to ensure effective communication and support. Feature requests written in other languages will be closed, with a request to rewrite them in English.
+        * We welcome any ideas or feature requests! It is helpful if you can explain exactly why the feature would be useful.
+        * There are usually some outstanding feature requests in the [existing issues list](https://github.com/espressif/arduino-esp32/issues?q=is%3Aopen+is%3Aissue+label%3A%22Type%3A+Feature+request%22), feel free to add comments to them.
+        * If you would like to contribute, please read the [contributions guide](https://docs.espressif.com/projects/arduino-esp32/en/latest/contributing.html).
+  - type: input
+    id: Area
+    attributes:
+      label: Related area
+      description: Please briefly explain the area of your Feature Request.
+      placeholder: eg. Board support, specific Peripheral, BT, Wifi...
+    validations:
+      required: true
+  - type: input
+    id: HW
+    attributes:
+      label: Hardware specification
+      description: Please provide if your proposal depends on specific Hardware.
+      placeholder: eg. Support for ESP32 DevKitC, ESP32-C3 DevKitM...
+    validations:
+      required: true
+  - type: textarea
+    id: problem-related
+    attributes:
+      label: Is your feature request related to a problem?
+      description: Please provide a clear and concise description of what the problem is. Add relevant issue link.
+      placeholder: ex. I'm facing the issue/missing function...
+    validations:
+      required: true
+  - type: textarea
+    id: solution
+    attributes:
+      label: Describe the solution you'd like
+      description: Please provide a clear and concise description of what you want to happen.
+      placeholder: ex. When using this function...
+    validations:
+      required: true
+  - type: textarea
+    id: alternatives
+    attributes:
+      label: Describe alternatives you've considered
+      description: Please provide a clear and concise description of any alternative solutions or features you've considered.
+      placeholder: ex. Choosing other approach wouldn't work, because...
+  - type: textarea
+    id: context
+    attributes:
+      label: Additional context
+      description: Please add any other context or screenshots about the feature request here.
+      placeholder: ex. This would work only when ...
+  - type: checkboxes
+    id: confirmation
+    attributes:
+      label: I have checked existing list of Feature requests and the Contribution Guide
+      description: You agree to check all the resources above before opening a new Feature request.
+      options:
+        - label: I confirm I have checked existing list of Feature requests and Contribution Guide.
+          required: true
diff --git a/.github/ISSUE_TEMPLATE/Issue-report.yml b/.github/ISSUE_TEMPLATE/Issue-report.yml
new file mode 100644
index 00000000000..9dba5e0ca8f
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/Issue-report.yml
@@ -0,0 +1,162 @@
+name: Issue report
+description: Report any problem here
+labels: ["Status: Awaiting triage"]
+body:
+  - type: markdown
+    attributes:
+      value: |
+        * Please note that we can only process issues reported in English to ensure effective communication and support. Issues written in other languages will be closed, with a request to rewrite them in English.
+        * Before reporting a new issue please check and search in [List of existing issues](https://github.com/espressif/arduino-esp32/issues?q=is%3Aissue)
+        * Please check [Online Documentation](https://docs.espressif.com/projects/arduino-esp32/en/latest/index.html)
+        * Take a look on [Troubleshooting guide](https://docs.espressif.com/projects/arduino-esp32/en/latest/troubleshooting.html)
+        * If still experiencing the issue, please provide as many details as possible below about your hardware, computer setup and code.
+  - type: input
+    id: Board
+    attributes:
+      label: Board
+      description: On which Board does this issue occur?
+      placeholder: eg. ESP32 Dev Module, ESP32-S2, LilyGo TTGO LoRa32...
+    validations:
+      required: true
+  - type: textarea
+    id: devboard
+    attributes:
+      label: Device Description
+      description: What development board or other hardware is the chip attached to?
+      placeholder: ex. DevKitC, plain module on breadboard, etc. If your hardware is custom or unusual, please attach a photo.
+    validations:
+      required: true
+  - type: textarea
+    id: other-hw
+    attributes:
+      label: Hardware Configuration
+      description: Is anything else attached to the development board?
+      placeholder: ex. GPIO 18 & 19 are connected to I2C devices.
+    validations:
+      required: true
+  - type: dropdown
+    id: version
+    attributes:
+      label: Version
+      description: What version of Arduino ESP32 are you running? If possible, consider updating to the latest version.
+      options:
+        - latest stable Release (if not listed below)
+        - latest development Release Candidate (RC-X)
+        - latest master (checkout manually)
+        - v3.2.0
+        - v3.1.3
+        - v3.1.2
+        - v3.1.1
+        - v3.1.0
+        - v3.0.7
+        - v3.0.6
+        - v3.0.5
+        - v3.0.4
+        - v3.0.3
+        - v3.0.2
+        - v3.0.1
+        - v3.0.0
+        - v2.0.17
+        - v2.0.16
+        - v2.0.15
+        - v2.0.14
+        - v2.0.13
+        - v2.0.12
+        - v2.0.11
+        - v2.0.10
+        - v2.0.9
+        - v2.0.8
+        - v2.0.7
+        - v2.0.6
+        - v2.0.5
+        - v2.0.4
+        - v2.0.3
+        - v2.0.2
+        - v2.0.1
+        - v2.0.0
+        - v1.0.6
+        - other
+    validations:
+      required: true
+  - type: input
+    id: IDE
+    attributes:
+     label: IDE Name
+     description: What IDE are you using?
+     placeholder: eg. Arduino IDE, VSCode, Sloeber...
+    validations:
+      required: true
+  - type: input
+    id: os
+    attributes:
+      label: Operating System
+      description: On which OS does this issue occur?
+      placeholder: ex. macOS 12.1, Windows 10...
+    validations:
+      required: true
+  - type: input
+    id: Flash
+    attributes:
+      label: Flash frequency
+      description: What flash frequency is used?
+      placeholder: eg. 40Mhz
+    validations:
+      required: true
+  - type: dropdown
+    id: PSRAM
+    attributes:
+      label: PSRAM enabled
+      description: Is PSRAM enabled?
+      options:
+        - "yes"
+        - "no"
+    validations:
+      required: true
+  - type: input
+    id: Upload
+    attributes:
+      label: Upload speed
+      description: What upload speed is used?
+      placeholder: eg. 115200
+    validations:
+      required: true
+  - type: textarea
+    id: Description
+    attributes:
+      label: Description
+      description: Please describe your problem here and expected behavior
+      placeholder: ex. Can't connect/weird behavior/wrong function/missing parameter..
+    validations:
+      required: true
+  - type: textarea
+    id: sketch
+    attributes:
+      label: Sketch
+      description: Please provide full minimal sketch/code which can be run to reproduce your issue
+      placeholder: ex. Related part of the code to replicate the issue
+      render: cpp
+    validations:
+      required: true
+  - type: textarea
+    id: Debug
+    attributes:
+      label: Debug Message
+      description: Please provide a debug message or error message. If you have a Guru Meditation Error or Backtrace, please decode it with [ExceptionDecoder](https://github.com/me-no-dev/EspExceptionDecoder)
+      placeholder: Enable Core debug level - Debug on tools menu of Arduino IDE, then put the serial output here.
+      render: plain
+    validations:
+      required: true
+  - type: textarea
+    id: other-remarks
+    attributes:
+      label: Other Steps to Reproduce
+      description: Is there any other information you can think of which will help us reproduce this problem? Any additional info can be added as well.
+      placeholder: ex. I also tried on other OS, HW...it works correctly on that setup.
+  - type: checkboxes
+    id: confirmation
+    attributes:
+      label: I have checked existing issues, online documentation and the Troubleshooting Guide
+      description: You agree to check all the resources above before opening a new issue.
+      options:
+        - label: I confirm I have checked existing issues, online documentation and Troubleshooting guide.
+          required: true
diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md
deleted file mode 100644
index 63d88b10f38..00000000000
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ /dev/null
@@ -1,54 +0,0 @@
----
-name: Bug report
-about: Please fill in the bug report carefully
-title: ''
-labels: ''
-assignees: ''
-
----
-
-Make your question, not a Statement, inclusive. Include all pertinent information:
-
-What you are trying to do?
-Describe your system( Hardware, computer, O/S, core version, environment).
-Describe what is failing.
-Show the shortest possible code that will duplicate the error.
-Show the EXACT error message(it doesn't work is not enough).
-All of this work on your part shows us that you have worked to solve YOUR problem. The more complete your issue posting is, the more likely someone will volunteer their time to help you.
-
-If you have a Guru Meditation Error or Backtrace, ***please decode it***:
-https://github.com/me-no-dev/EspExceptionDecoder
-
------------------------------ Remove above -----------------------------
-
-
-### Hardware:
-Board:							?ESP32 Dev Module? ?node32? ?ttgo_lora?
-Core Installation version:			?1.0.0? ?1.0.1-rc4? ?1.0.1? ?1.0.1-git? ?1.0.2? ?1.0.3?
-IDE name:						?Arduino IDE? ?Platform.io? ?IDF component?
-Flash Frequency:					?40Mhz?
-PSRAM enabled:                                    ?no? ?yes?
-Upload Speed:					?115200?
-Computer OS:                                        ?Windows 10? ?Mac OSX? ?Ubuntu?
-
-### Description:
-Describe your problem here
-
-
-### Sketch:  (leave the backquotes for [code formatting](https://help.github.com/articles/creating-and-highlighting-code-blocks/))
-```cpp
-
-//Change the code below by your sketch
-#include <Arduino.h>
-
-void setup() {
-}
-
-void loop() {
-}
-```
-
-### Debug Messages:
-```
-Enable Core debug level: Debug on tools menu of Arduino IDE, then put the serial output here 
-```
diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml
new file mode 100644
index 00000000000..e879b09bec2
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/config.yml
@@ -0,0 +1,8 @@
+blank_issues_enabled: false
+contact_links:
+  - name: Arduino Core for Espressif Discord Server
+    url: https://discord.gg/8xY6e9crwv
+    about: Community Discord server for questions and help
+  - name: ESP32 Forum - Arduino
+    url: https://esp32.com/viewforum.php?f=19
+    about: Official Forum for questions
diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md
new file mode 100644
index 00000000000..5e0d99c0457
--- /dev/null
+++ b/.github/PULL_REQUEST_TEMPLATE.md
@@ -0,0 +1,24 @@
+*By completing this PR sufficiently, you help us to review this Pull Request quicker and also help improve the quality of Release Notes*
+
+### Checklist
+1. [ ] Please provide specific title of the PR describing the change, including the component name (*eg. „Update of Documentation link on Readme.md“*)
+2. [ ] Please provide related links (*eg. Issue which will be closed by this Pull Request*)
+3. [ ] Please **update relevant Documentation** if applicable
+4. [ ] Please check [Contributing guide](https://docs.espressif.com/projects/arduino-esp32/en/latest/contributing.html)
+5. [ ] Please **confirm option to "Allow edits and access to secrets by maintainers"** when opening a Pull Request
+
+*This entire section above can be deleted if all items are checked.*
+
+-----------
+## Description of Change
+Please describe your proposed Pull Request and it's impact.
+
+## Tests scenarios
+Please describe on what Hardware and Software combinations you have tested this Pull Request and how.
+
+(*eg. I have tested my Pull Request on Arduino-esp32 core v2.0.2 with ESP32 and ESP32-S2 Board with this scenario*)
+
+## Related links
+Please provide links to related issue, PRs etc.
+
+(*eg. Closes #number of issue*)
diff --git a/.github/pytools/Sign-File.ps1 b/.github/pytools/Sign-File.ps1
new file mode 100755
index 00000000000..09094096ac7
--- /dev/null
+++ b/.github/pytools/Sign-File.ps1
@@ -0,0 +1,78 @@
+[CmdletBinding()]
+param (
+    [Parameter()]
+    [String]
+    $Path
+)
+
+
+function FindSignTool {
+    $SignTool = "signtool.exe"
+    if (Get-Command $SignTool -ErrorAction SilentlyContinue) {
+        return $SignTool
+    }
+    $SignTool = "${env:ProgramFiles(x86)}\Windows Kits\10\bin\x64\signtool.exe"
+    if (Test-Path -Path $SignTool -PathType Leaf) {
+        return $SignTool
+    }
+    $SignTool = "${env:ProgramFiles(x86)}\Windows Kits\10\bin\x86\signtool.exe"
+    if (Test-Path -Path $SignTool -PathType Leaf) {
+        return $SignTool
+    }
+    $sdkVers = "10.0.22000.0", "10.0.20348.0", "10.0.19041.0", "10.0.17763.0"
+    Foreach ($ver in $sdkVers)
+    {
+        $SignTool = "${env:ProgramFiles(x86)}\Windows Kits\10\bin\${ver}\x64\signtool.exe"
+        if (Test-Path -Path $SignTool -PathType Leaf) {
+            return $SignTool
+        }
+    }
+    "signtool.exe not found"
+    Exit 1
+}
+
+function SignEsptool {
+    param(
+        [Parameter()]
+        [String]
+        $Path
+    )
+
+    $SignTool = FindSignTool
+    "Using: $SignTool"
+    $CertificateFile = [system.io.path]::GetTempPath() + "certificate.pfx"
+
+    if ($null -eq $env:CERTIFICATE) {
+        "CERTIFICATE variable not set, unable to sign the file"
+        Exit 1
+    }
+
+    if ("" -eq $env:CERTIFICATE) {
+        "CERTIFICATE variable is empty, unable to sign the file"
+        Exit 1
+    }
+
+    $SignParameters = @("sign", "/tr", 'http://timestamp.digicert.com', "/td", "SHA256", "/f", $CertificateFile, "/fd", "SHA256")
+    if ($env:CERTIFICATE_PASSWORD) {
+        "CERTIFICATE_PASSWORD detected, using the password"
+        $SignParameters += "/p"
+        $SignParameters += $env:CERTIFICATE_PASSWORD
+    }
+    $SignParameters += $Path
+
+    [byte[]]$CertificateBytes = [convert]::FromBase64String($env:CERTIFICATE)
+    [IO.File]::WriteAllBytes($CertificateFile, $CertificateBytes)
+
+    &$SignTool $SignParameters
+
+    if (0 -eq $LASTEXITCODE) {
+        Remove-Item $CertificateFile
+    } else {
+        Remove-Item $CertificateFile
+        "Signing failed"
+        Exit 1
+    }
+
+}
+
+SignEsptool ${Path}
diff --git a/.github/pytools/espressif.ico b/.github/pytools/espressif.ico
new file mode 100644
index 00000000000..c5550f148cf
Binary files /dev/null and b/.github/pytools/espressif.ico differ
diff --git a/.github/scripts/check-cmakelists.sh b/.github/scripts/check-cmakelists.sh
index 88eb3dfbc4b..7d4f6b4e2d9 100755
--- a/.github/scripts/check-cmakelists.sh
+++ b/.github/scripts/check-cmakelists.sh
@@ -1,6 +1,7 @@
 #!/bin/bash
+
 #
-# This script is for Travis. It checks all non-examples source files in libraries/ and cores/ are listed in
+# This script is used in the CI workflow. It checks all non-examples source files in libraries/ and cores/ are listed in
 # CMakeLists.txt for the cmake-based IDF component
 #
 # If you see an error running this script, edit CMakeLists.txt and add any new source files into your PR
@@ -12,12 +13,12 @@ set -e
 git submodule update --init --recursive
 
 # find all source files in repo
-REPO_SRCS=`find cores/esp32/ libraries/ -name 'examples' -prune -o -name '*.c' -print -o -name '*.cpp' -print | sort`
+REPO_SRCS=$(find cores/esp32/ libraries/ -name 'examples' -prune -o -name '*.c' -print -o -name '*.cpp' -print | sort)
 
 # find all source files named in CMakeLists.txt COMPONENT_SRCS
-CMAKE_SRCS=`cmake --trace-expand -C CMakeLists.txt 2>&1 | grep COMPONENT_SRCS | sed 's/.\+COMPONENT_SRCS //' | sed 's/ )//' | tr ' ;' '\n' | sort`
+CMAKE_SRCS=$(cmake --trace-expand -P CMakeLists.txt 2>&1 | grep set\(srcs | cut -d'(' -f3 | sed 's/ )//' | sed 's/srcs //' | tr ' ;' '\n' | sort)
 
-if ! diff -u0 --label "Repo Files" --label "COMPONENT_SRCS" <(echo "$REPO_SRCS") <(echo "$CMAKE_SRCS"); then
+if ! diff -u0 --label "Repo Files" --label "srcs" <(echo "$REPO_SRCS") <(echo "$CMAKE_SRCS"); then
     echo "Source files in repo (-) and source files in CMakeLists.txt (+) don't match"
     echo "Edit CMakeLists.txt as appropriate to add/remove source files from COMPONENT_SRCS"
     exit 1
diff --git a/.github/scripts/find_all_boards.sh b/.github/scripts/find_all_boards.sh
new file mode 100755
index 00000000000..67b46661ca5
--- /dev/null
+++ b/.github/scripts/find_all_boards.sh
@@ -0,0 +1,39 @@
+#!/bin/bash
+
+# Get all boards
+boards_array=()
+
+boards_list=$(grep '.tarch=' boards.txt)
+
+while read -r line; do
+    board_name=$(echo "$line" | cut -d '.' -f1 | cut -d '#' -f1)
+    # skip esp32c2 as we dont build libs for it
+    if [ "$board_name" == "esp32c2" ]; then
+        echo "Skipping 'espressif:esp32:$board_name'"
+        continue
+    fi
+    boards_array+=("espressif:esp32:$board_name")
+    echo "Added 'espressif:esp32:$board_name' to array"
+done <<< "$boards_list"
+
+# Create JSON like string with all boards found and pass it to env variable
+board_count=${#boards_array[@]}
+echo "Boards found: $board_count"
+echo "BOARD-COUNT=$board_count" >> "$GITHUB_ENV"
+
+if [ "$board_count" -gt 0 ]; then
+    json_matrix='['
+    for board in "${boards_array[@]}"; do
+        json_matrix+='"'$board'"'
+        if [ "$board_count" -gt 1 ]; then
+            json_matrix+=","
+        fi
+        board_count=$((board_count - 1))
+    done
+    json_matrix+=']'
+
+    echo "$json_matrix"
+    echo "FQBNS=${json_matrix}" >> "$GITHUB_ENV"
+else
+    echo "FQBNS=" >> "$GITHUB_ENV"
+fi
diff --git a/.github/scripts/find_new_boards.sh b/.github/scripts/find_new_boards.sh
new file mode 100755
index 00000000000..4482aa2b1da
--- /dev/null
+++ b/.github/scripts/find_new_boards.sh
@@ -0,0 +1,62 @@
+#!/bin/bash
+
+# Get inputs from command
+owner_repository=$1
+base_ref=$2
+
+# Download the boards.txt file from the base branch
+curl -L -o boards_base.txt https://raw.githubusercontent.com/"$owner_repository"/"$base_ref"/boards.txt
+
+# Compare boards.txt file in the repo with the modified file from PR
+diff=$(diff -u boards_base.txt boards.txt)
+
+# Check if the diff is empty
+if [ -z "$diff" ]; then
+    echo "No changes in boards.txt file"
+    echo "FQBNS="
+    exit 0
+fi
+
+# Extract added or modified lines (lines starting with '+' or '-')
+modified_lines=$(echo "$diff" | grep -E '^[+-][^+-]')
+
+# Print the modified lines for debugging
+echo "Modified lines:"
+echo "$modified_lines"
+
+boards_array=()
+previous_board=""
+
+# Extract board names from the modified lines, and add them to the boards_array
+while read -r line; do
+    board_name=$(echo "$line" | cut -d '.' -f1 | cut -d '#' -f1)
+    # remove + or - from the board name at the beginning
+    board_name=${board_name#[-+]}
+    if [ "$board_name" != "" ] && [ "$board_name" != "+" ] && [ "$board_name" != "-" ] && [ "$board_name" != "esp32_family" ]; then
+        if [ "$board_name" != "$previous_board" ]; then
+            boards_array+=("espressif:esp32:$board_name")
+            previous_board="$board_name"
+            echo "Added 'espressif:esp32:$board_name' to array"
+        fi
+    fi
+done <<< "$modified_lines"
+
+# Create JSON like string with all boards found and pass it to env variable
+board_count=${#boards_array[@]}
+
+if [ "$board_count" -gt 0 ]; then
+    json_matrix='{"fqbn": ['
+    for board in "${boards_array[@]}"; do
+        json_matrix+='"'$board'"'
+        if [ "$board_count" -gt 1 ]; then
+            json_matrix+=","
+        fi
+        board_count=$((board_count - 1))
+    done
+    json_matrix+=']}'
+
+    echo "$json_matrix"
+    echo "FQBNS=${json_matrix}" >> "$GITHUB_ENV"
+else
+    echo "FQBNS=" >> "$GITHUB_ENV"
+fi
diff --git a/.github/scripts/install-arduino-cli.sh b/.github/scripts/install-arduino-cli.sh
new file mode 100755
index 00000000000..bb7f544e752
--- /dev/null
+++ b/.github/scripts/install-arduino-cli.sh
@@ -0,0 +1,51 @@
+#!/bin/bash
+
+OSBITS=$(uname -m)
+if [[ "$OSTYPE" == "linux"* ]]; then
+    export OS_IS_LINUX="1"
+    if [[ "$OSBITS" == "i686" ]]; then
+        OS_NAME="linux32"
+    elif [[ "$OSBITS" == "x86_64" ]]; then
+        OS_NAME="linux64"
+    elif [[ "$OSBITS" == "armv7l" || "$OSBITS" == "aarch64" ]]; then
+        OS_NAME="linuxarm"
+    else
+        OS_NAME="$OSTYPE-$OSBITS"
+        echo "Unknown OS '$OS_NAME'"
+        exit 1
+    fi
+elif [[ "$OSTYPE" == "darwin"* ]]; then
+    export OS_IS_MACOS="1"
+    OS_NAME="macosx"
+elif [[ "$OSTYPE" == "cygwin" ]] || [[ "$OSTYPE" == "msys" ]] || [[ "$OSTYPE" == "win32" ]]; then
+    export OS_IS_WINDOWS="1"
+    OS_NAME="windows"
+else
+    OS_NAME="$OSTYPE-$OSBITS"
+    echo "Unknown OS '$OS_NAME'"
+    exit 1
+fi
+export OS_NAME
+
+if [ "$OS_IS_MACOS" == "1" ]; then
+    export ARDUINO_IDE_PATH="$HOME/bin"
+    export ARDUINO_USR_PATH="$HOME/Documents/Arduino"
+elif [ "$OS_IS_WINDOWS" == "1" ]; then
+    export ARDUINO_IDE_PATH="$HOME/bin"
+    export ARDUINO_USR_PATH="$HOME/Documents/Arduino"
+else
+    export ARDUINO_IDE_PATH="$HOME/bin"
+    export ARDUINO_USR_PATH="$HOME/Arduino"
+fi
+
+if [ ! -d "$ARDUINO_IDE_PATH" ] || [ ! -f "$ARDUINO_IDE_PATH/arduino-cli" ]; then
+    echo "Installing Arduino CLI on $OS_NAME ..."
+    mkdir -p "$ARDUINO_IDE_PATH"
+    if [ "$OS_IS_WINDOWS" == "1" ]; then
+        curl -fsSL https://downloads.arduino.cc/arduino-cli/arduino-cli_latest_Windows_64bit.zip -o arduino-cli.zip
+        unzip -q arduino-cli.zip -d "$ARDUINO_IDE_PATH"
+        rm arduino-cli.zip
+    else
+        curl -fsSL https://raw.githubusercontent.com/arduino/arduino-cli/master/install.sh | BINDIR="$ARDUINO_IDE_PATH" sh
+    fi
+fi
diff --git a/.github/scripts/install-arduino-core-esp32.sh b/.github/scripts/install-arduino-core-esp32.sh
index cf1026d6a71..e0071a0eb83 100755
--- a/.github/scripts/install-arduino-core-esp32.sh
+++ b/.github/scripts/install-arduino-core-esp32.sh
@@ -2,35 +2,39 @@
 
 export ARDUINO_ESP32_PATH="$ARDUINO_USR_PATH/hardware/espressif/esp32"
 if [ ! -d "$ARDUINO_ESP32_PATH" ]; then
-	echo "Installing ESP32 Arduino Core ..."
-	script_init_path="$PWD"
-	mkdir -p "$ARDUINO_USR_PATH/hardware/espressif"
-	cd "$ARDUINO_USR_PATH/hardware/espressif"
+    echo "Installing ESP32 Arduino Core ..."
+    script_init_path="$PWD"
+    mkdir -p "$ARDUINO_USR_PATH/hardware/espressif"
+    cd "$ARDUINO_USR_PATH/hardware/espressif" || exit
 
-	echo "Installing Python Serial ..."
-	pip install pyserial > /dev/null
+    echo "Installing Python Serial ..."
+    pip install pyserial > /dev/null
 
-	if [ "$OS_IS_WINDOWS" == "1" ]; then
-		echo "Installing Python Requests ..."
-		pip install requests > /dev/null
-	fi
+    if [ "$OS_IS_WINDOWS" == "1" ]; then
+        echo "Installing Python Requests ..."
+        pip install requests > /dev/null
+    fi
 
-	if [ "$GITHUB_REPOSITORY" == "espressif/arduino-esp32" ];  then
-		echo "Linking Core..."
-		ln -s $GITHUB_WORKSPACE esp32
-	else
-		echo "Cloning Core Repository..."
-		git clone https://github.com/espressif/arduino-esp32.git esp32 > /dev/null 2>&1
-	fi
+    if [ -n "$GITHUB_REPOSITORY" ];  then
+        echo "Linking Core..."
+        ln -s "$GITHUB_WORKSPACE" esp32
+    else
+        echo "Cloning Core Repository..."
+        git clone https://github.com/espressif/arduino-esp32.git esp32 > /dev/null 2>&1
+    fi
 
-	echo "Updating Submodules ..."
-	cd esp32
-	git submodule update --init --recursive > /dev/null 2>&1
+    #echo "Updating Submodules ..."
+    cd esp32 || exit
+    #git submodule update --init --recursive > /dev/null 2>&1
 
-	echo "Installing Platform Tools ..."
-	cd tools && python get.py
-	cd $script_init_path
+    echo "Installing Platform Tools ..."
+    if [ "$OS_IS_WINDOWS" == "1" ]; then
+        cd tools && ./get.exe
+    else
+        cd tools && python get.py
+    fi
+    cd "$script_init_path" || exit
 
-	echo "ESP32 Arduino has been installed in '$ARDUINO_ESP32_PATH'"
-	echo ""
+    echo "ESP32 Arduino has been installed in '$ARDUINO_ESP32_PATH'"
+    echo ""
 fi
diff --git a/.github/scripts/install-arduino-ide.sh b/.github/scripts/install-arduino-ide.sh
index e0c5b78b794..5b3bcb1791e 100755
--- a/.github/scripts/install-arduino-ide.sh
+++ b/.github/scripts/install-arduino-ide.sh
@@ -4,48 +4,45 @@
 #OSTYPE: 'msys', ARCH: 'x86_64' => win32
 #OSTYPE: 'darwin18', ARCH: 'i386' => macos
 
-OSBITS=`arch`
+OSBITS=$(uname -m)
 if [[ "$OSTYPE" == "linux"* ]]; then
-	export OS_IS_LINUX="1"
-	ARCHIVE_FORMAT="tar.xz"
-	if [[ "$OSBITS" == "i686" ]]; then
-		OS_NAME="linux32"
-	elif [[ "$OSBITS" == "x86_64" ]]; then
-		OS_NAME="linux64"
-	elif [[ "$OSBITS" == "armv7l" || "$OSBITS" == "aarch64" ]]; then
-		OS_NAME="linuxarm"
-	else
-		OS_NAME="$OSTYPE-$OSBITS"
-		echo "Unknown OS '$OS_NAME'"
-		exit 1
-	fi
+    export OS_IS_LINUX="1"
+    ARCHIVE_FORMAT="tar.xz"
+    if [[ "$OSBITS" == "i686" ]]; then
+        OS_NAME="linux32"
+    elif [[ "$OSBITS" == "x86_64" ]]; then
+        OS_NAME="linux64"
+    elif [[ "$OSBITS" == "armv7l" || "$OSBITS" == "aarch64" ]]; then
+        OS_NAME="linuxarm"
+    else
+        OS_NAME="$OSTYPE-$OSBITS"
+        echo "Unknown OS '$OS_NAME'"
+        exit 1
+    fi
 elif [[ "$OSTYPE" == "darwin"* ]]; then
-	export OS_IS_MACOS="1"
-	ARCHIVE_FORMAT="zip"
-	OS_NAME="macosx"
+    export OS_IS_MACOS="1"
+    ARCHIVE_FORMAT="zip"
+    OS_NAME="macosx"
 elif [[ "$OSTYPE" == "cygwin" ]] || [[ "$OSTYPE" == "msys" ]] || [[ "$OSTYPE" == "win32" ]]; then
-	export OS_IS_WINDOWS="1"
-	ARCHIVE_FORMAT="zip"
-	OS_NAME="windows"
+    export OS_IS_WINDOWS="1"
+    ARCHIVE_FORMAT="zip"
+    OS_NAME="windows"
 else
-	OS_NAME="$OSTYPE-$OSBITS"
-	echo "Unknown OS '$OS_NAME'"
-	exit 1
+    OS_NAME="$OSTYPE-$OSBITS"
+    echo "Unknown OS '$OS_NAME'"
+    exit 1
 fi
 export OS_NAME
 
-ARDUINO_BUILD_DIR="$HOME/.arduino/build.tmp"
-ARDUINO_CACHE_DIR="$HOME/.arduino/cache.tmp"
-
 if [ "$OS_IS_MACOS" == "1" ]; then
-	export ARDUINO_IDE_PATH="/Applications/Arduino.app/Contents/Java"
-	export ARDUINO_USR_PATH="$HOME/Documents/Arduino"
+    export ARDUINO_IDE_PATH="/Applications/Arduino.app/Contents/Java"
+    export ARDUINO_USR_PATH="$HOME/Documents/Arduino"
 elif [ "$OS_IS_WINDOWS" == "1" ]; then
-	export ARDUINO_IDE_PATH="$HOME/arduino_ide"
-	export ARDUINO_USR_PATH="$HOME/Documents/Arduino"
+    export ARDUINO_IDE_PATH="$HOME/arduino_ide"
+    export ARDUINO_USR_PATH="$HOME/Documents/Arduino"
 else
-	export ARDUINO_IDE_PATH="$HOME/arduino_ide"
-	export ARDUINO_USR_PATH="$HOME/Arduino"
+    export ARDUINO_IDE_PATH="$HOME/arduino_ide"
+    export ARDUINO_USR_PATH="$HOME/Arduino"
 fi
 
 # Updated as of Nov 3rd 2020
@@ -55,172 +52,28 @@ ARDUINO_IDE_URL="https://github.com/espressif/arduino-esp32/releases/download/1.
 #ARDUINO_IDE_URL="https://www.arduino.cc/download.php?f=/arduino-nightly-"
 
 if [ ! -d "$ARDUINO_IDE_PATH" ]; then
-	echo "Installing Arduino IDE on $OS_NAME ..."
-	echo "Downloading '$ARDUINO_IDE_URL$OS_NAME.$ARCHIVE_FORMAT' to 'arduino.$ARCHIVE_FORMAT' ..."
-	if [ "$OS_IS_LINUX" == "1" ]; then
-		wget -O "arduino.$ARCHIVE_FORMAT" "$ARDUINO_IDE_URL$OS_NAME.$ARCHIVE_FORMAT" > /dev/null 2>&1
-		echo "Extracting 'arduino.$ARCHIVE_FORMAT' ..."
-		tar xf "arduino.$ARCHIVE_FORMAT" > /dev/null
-		mv arduino-nightly "$ARDUINO_IDE_PATH"
-	else
-		curl -o "arduino.$ARCHIVE_FORMAT" -L "$ARDUINO_IDE_URL$OS_NAME.$ARCHIVE_FORMAT" > /dev/null 2>&1
-		echo "Extracting 'arduino.$ARCHIVE_FORMAT' ..."
-		unzip "arduino.$ARCHIVE_FORMAT" > /dev/null
-		if [ "$OS_IS_MACOS" == "1" ]; then
-			mv "Arduino.app" "/Applications/Arduino.app"
-		else
-			mv arduino-nightly "$ARDUINO_IDE_PATH"
-		fi
-	fi
-	rm -rf "arduino.$ARCHIVE_FORMAT"
-
-	mkdir -p "$ARDUINO_USR_PATH/libraries"
-	mkdir -p "$ARDUINO_USR_PATH/hardware"
-
-	echo "Arduino IDE Installed in '$ARDUINO_IDE_PATH'"
-	echo ""
-fi
-
-function build_sketch(){ # build_sketch <fqbn> <path-to-ino> [extra-options]
-    if [ "$#" -lt 2 ]; then
-		echo "ERROR: Illegal number of parameters"
-		echo "USAGE: build_sketch <fqbn> <path-to-ino> [extra-options]"
-		return 1
-	fi
-
-	local fqbn="$1"
-	local sketch="$2"
-	local xtra_opts="$3"
-	local win_opts=""
-	if [ "$OS_IS_WINDOWS" == "1" ]; then
-		local ctags_version=`ls "$ARDUINO_IDE_PATH/tools-builder/ctags/"`
-		local preprocessor_version=`ls "$ARDUINO_IDE_PATH/tools-builder/arduino-preprocessor/"`
-		win_opts="-prefs=runtime.tools.ctags.path=$ARDUINO_IDE_PATH/tools-builder/ctags/$ctags_version -prefs=runtime.tools.arduino-preprocessor.path=$ARDUINO_IDE_PATH/tools-builder/arduino-preprocessor/$preprocessor_version"
-	fi
-
-	echo ""
-	echo "Compiling '"$(basename "$sketch")"' ..."
-	mkdir -p "$ARDUINO_BUILD_DIR"
-	mkdir -p "$ARDUINO_CACHE_DIR"
-	$ARDUINO_IDE_PATH/arduino-builder -compile -logger=human -core-api-version=10810 \
-		-fqbn=$fqbn \
-		-warnings="all" \
-		-tools "$ARDUINO_IDE_PATH/tools-builder" \
-		-tools "$ARDUINO_IDE_PATH/tools" \
-		-built-in-libraries "$ARDUINO_IDE_PATH/libraries" \
-		-hardware "$ARDUINO_IDE_PATH/hardware" \
-		-hardware "$ARDUINO_USR_PATH/hardware" \
-		-libraries "$ARDUINO_USR_PATH/libraries" \
-		-build-cache "$ARDUINO_CACHE_DIR" \
-		-build-path "$ARDUINO_BUILD_DIR" \
-		$win_opts $xtra_opts "$sketch"
-}
-
-function count_sketches() # count_sketches <examples-path>
-{
-	local examples="$1"
-    rm -rf sketches.txt
-	if [ ! -d "$examples" ]; then
-		touch sketches.txt
-		return 0
-	fi
-    local sketches=$(find $examples -name *.ino)
-    local sketchnum=0
-    for sketch in $sketches; do
-        local sketchdir=$(dirname $sketch)
-        local sketchdirname=$(basename $sketchdir)
-        local sketchname=$(basename $sketch)
-        if [[ "${sketchdirname}.ino" != "$sketchname" ]]; then
-            continue
-        fi;
-        if [[ -f "$sketchdir/.test.skip" ]]; then
-            continue
+    echo "Installing Arduino IDE on $OS_NAME ..."
+    echo "Downloading '$ARDUINO_IDE_URL$OS_NAME.$ARCHIVE_FORMAT' to 'arduino.$ARCHIVE_FORMAT' ..."
+    if [ "$OS_IS_LINUX" == "1" ]; then
+        wget -O "arduino.$ARCHIVE_FORMAT" "$ARDUINO_IDE_URL$OS_NAME.$ARCHIVE_FORMAT" > /dev/null 2>&1
+        echo "Extracting 'arduino.$ARCHIVE_FORMAT' ..."
+        tar xf "arduino.$ARCHIVE_FORMAT" > /dev/null
+        mv arduino-nightly "$ARDUINO_IDE_PATH"
+    else
+        curl -o "arduino.$ARCHIVE_FORMAT" -L "$ARDUINO_IDE_URL$OS_NAME.$ARCHIVE_FORMAT" > /dev/null 2>&1
+        echo "Extracting 'arduino.$ARCHIVE_FORMAT' ..."
+        unzip "arduino.$ARCHIVE_FORMAT" > /dev/null
+        if [ "$OS_IS_MACOS" == "1" ]; then
+            mv "Arduino.app" "/Applications/Arduino.app"
+        else
+            mv arduino-nightly "$ARDUINO_IDE_PATH"
         fi
-        echo $sketch >> sketches.txt
-        sketchnum=$(($sketchnum + 1))
-    done
-    return $sketchnum
-}
-
-function build_sketches() # build_sketches <fqbn> <examples-path> <chunk> <total-chunks> [extra-options]
-{
-    local fqbn=$1
-    local examples=$2
-    local chunk_idex=$3
-    local chunks_num=$4
-    local xtra_opts=$5
-
-    if [ "$#" -lt 2 ]; then
-		echo "ERROR: Illegal number of parameters"
-		echo "USAGE: build_sketches <fqbn> <examples-path> [<chunk> <total-chunks>] [extra-options]"
-		return 1
-	fi
-
-    if [ "$#" -lt 4 ]; then
-		chunk_idex="0"
-		chunks_num="1"
-		xtra_opts=$3
-	fi
-
-	if [ "$chunks_num" -le 0 ]; then
-		echo "ERROR: Chunks count must be positive number"
-		return 1
-	fi
-	if [ "$chunk_idex" -ge "$chunks_num" ]; then
-		echo "ERROR: Chunk index must be less than chunks count"
-		return 1
-	fi
-
-	set +e
-    count_sketches "$examples"
-    local sketchcount=$?
-	set -e
-    local sketches=$(cat sketches.txt)
-    rm -rf sketches.txt
-
-    local chunk_size=$(( $sketchcount / $chunks_num ))
-    local all_chunks=$(( $chunks_num * $chunk_size ))
-    if [ "$all_chunks" -lt "$sketchcount" ]; then
-    	chunk_size=$(( $chunk_size + 1 ))
     fi
+    rm -rf "arduino.$ARCHIVE_FORMAT"
 
-    local start_index=$(( $chunk_idex * $chunk_size ))
-    if [ "$sketchcount" -le "$start_index" ]; then
-    	echo "Skipping job"
-    	return 0
-    fi
-
-    local end_index=$(( $(( $chunk_idex + 1 )) * $chunk_size ))
-    if [ "$end_index" -gt "$sketchcount" ]; then
-    	end_index=$sketchcount
-    fi
+    mkdir -p "$ARDUINO_USR_PATH/libraries"
+    mkdir -p "$ARDUINO_USR_PATH/hardware"
 
-    local start_num=$(( $start_index + 1 ))
-    echo "Found $sketchcount Sketches";
-    echo "Chunk Count : $chunks_num"
-    echo "Chunk Size  : $chunk_size"
-    echo "Start Sketch: $start_num"
-    echo "End Sketch  : $end_index"
-
-    local sketchnum=0
-    for sketch in $sketches; do
-        local sketchdir=$(dirname $sketch)
-        local sketchdirname=$(basename $sketchdir)
-        local sketchname=$(basename $sketch)
-        if [ "${sketchdirname}.ino" != "$sketchname" ] \
-        || [ -f "$sketchdir/.test.skip" ]; then
-            continue
-        fi
-        sketchnum=$(($sketchnum + 1))
-        if [ "$sketchnum" -le "$start_index" ] \
-        || [ "$sketchnum" -gt "$end_index" ]; then
-        	continue
-        fi
-        build_sketch "$fqbn" "$sketch" "$xtra_opts"
-        local result=$?
-        if [ $result -ne 0 ]; then
-            return $result
-        fi
-    done
-    return 0
-}
+    echo "Arduino IDE Installed in '$ARDUINO_IDE_PATH'"
+    echo ""
+fi
diff --git a/.github/scripts/install-platformio-esp32.sh b/.github/scripts/install-platformio-esp32.sh
deleted file mode 100755
index c065b0a029c..00000000000
--- a/.github/scripts/install-platformio-esp32.sh
+++ /dev/null
@@ -1,148 +0,0 @@
-#!/bin/bash
-
-export PLATFORMIO_ESP32_PATH="$HOME/.platformio/packages/framework-arduinoespressif32"
-
-echo "Installing Python Wheel ..."
-pip install wheel > /dev/null 2>&1
-
-echo "Installing PlatformIO ..."
-pip install -U https://github.com/platformio/platformio/archive/develop.zip > /dev/null 2>&1
-
-echo "Installing Platform ESP32 ..."
-python -m platformio platform install https://github.com/platformio/platform-espressif32.git > /dev/null 2>&1
-
-echo "Replacing the framework version ..."
-python -c "import json; import os; fp=open(os.path.expanduser('~/.platformio/platforms/espressif32/platform.json'), 'r+'); data=json.load(fp); data['packages']['framework-arduinoespressif32']['version'] = '*'; del data['packages']['framework-arduinoespressif32']['owner']; fp.seek(0); fp.truncate(); json.dump(data, fp); fp.close()"
-
-if [ "$GITHUB_REPOSITORY" == "espressif/arduino-esp32" ];  then
-	echo "Linking Core..."
-	ln -s $GITHUB_WORKSPACE "$PLATFORMIO_ESP32_PATH"
-else
-	echo "Cloning Core Repository ..."
-	git clone --recursive https://github.com/espressif/arduino-esp32.git "$PLATFORMIO_ESP32_PATH" > /dev/null 2>&1
-fi
-
-echo "PlatformIO for ESP32 has been installed"
-echo ""
-
-function build_pio_sketch(){ # build_pio_sketch <board> <path-to-ino>
-    if [ "$#" -lt 2 ]; then
-        echo "ERROR: Illegal number of parameters"
-        echo "USAGE: build_pio_sketch <board> <path-to-ino>"
-        return 1
-    fi
-
-    local board="$1"
-    local sketch="$2"
-    local sketch_dir=$(dirname "$sketch")
-    echo ""
-    echo "Compiling '"$(basename "$sketch")"' ..."
-    python -m platformio ci --board "$board" "$sketch_dir" --project-option="board_build.partitions = huge_app.csv"
-}
-
-function count_sketches() # count_sketches <examples-path>
-{
-    local examples="$1"
-    rm -rf sketches.txt
-    if [ ! -d "$examples" ]; then
-        touch sketches.txt
-        return 0
-    fi
-    local sketches=$(find $examples -name *.ino)
-    local sketchnum=0
-    for sketch in $sketches; do
-        local sketchdir=$(dirname $sketch)
-        local sketchdirname=$(basename $sketchdir)
-        local sketchname=$(basename $sketch)
-        if [[ "${sketchdirname}.ino" != "$sketchname" ]]; then
-            continue
-        fi;
-        if [[ -f "$sketchdir/.test.skip" ]]; then
-            continue
-        fi
-        echo $sketch >> sketches.txt
-        sketchnum=$(($sketchnum + 1))
-    done
-    return $sketchnum
-}
-
-function build_pio_sketches() # build_pio_sketches <board> <examples-path> <chunk> <total-chunks>
-{
-    if [ "$#" -lt 2 ]; then
-        echo "ERROR: Illegal number of parameters"
-        echo "USAGE: build_pio_sketches <board> <examples-path> [<chunk> <total-chunks>]"
-        return 1
-    fi
-
-    local board=$1
-    local examples=$2
-    local chunk_idex=$3
-    local chunks_num=$4
-
-    if [ "$#" -lt 4 ]; then
-        chunk_idex="0"
-        chunks_num="1"
-    fi
-
-    if [ "$chunks_num" -le 0 ]; then
-        echo "ERROR: Chunks count must be positive number"
-        return 1
-    fi
-    if [ "$chunk_idex" -ge "$chunks_num" ]; then
-        echo "ERROR: Chunk index must be less than chunks count"
-        return 1
-    fi
-
-    set +e
-    count_sketches "$examples"
-    local sketchcount=$?
-    set -e
-    local sketches=$(cat sketches.txt)
-    rm -rf sketches.txt
-
-    local chunk_size=$(( $sketchcount / $chunks_num ))
-    local all_chunks=$(( $chunks_num * $chunk_size ))
-    if [ "$all_chunks" -lt "$sketchcount" ]; then
-        chunk_size=$(( $chunk_size + 1 ))
-    fi
-
-    local start_index=$(( $chunk_idex * $chunk_size ))
-    if [ "$sketchcount" -le "$start_index" ]; then
-        echo "Skipping job"
-        return 0
-    fi
-
-    local end_index=$(( $(( $chunk_idex + 1 )) * $chunk_size ))
-    if [ "$end_index" -gt "$sketchcount" ]; then
-        end_index=$sketchcount
-    fi
-
-    local start_num=$(( $start_index + 1 ))
-    echo "Found $sketchcount Sketches";
-    echo "Chunk Count : $chunks_num"
-    echo "Chunk Size  : $chunk_size"
-    echo "Start Sketch: $start_num"
-    echo "End Sketch  : $end_index"
-
-    local sketchnum=0
-    for sketch in $sketches; do
-        local sketchdir=$(dirname $sketch)
-        local sketchdirname=$(basename $sketchdir)
-        local sketchname=$(basename $sketch)
-        if [ "${sketchdirname}.ino" != "$sketchname" ] \
-        || [ -f "$sketchdir/.test.skip" ]; then
-            continue
-        fi
-        sketchnum=$(($sketchnum + 1))
-        if [ "$sketchnum" -le "$start_index" ] \
-        || [ "$sketchnum" -gt "$end_index" ]; then
-            continue
-        fi
-        build_pio_sketch "$board" "$sketch"
-        local result=$?
-        if [ $result -ne 0 ]; then
-            return $result
-        fi
-    done
-    return 0
-}
diff --git a/.github/scripts/merge_packages.py b/.github/scripts/merge_packages.py
index 53fbbd9b0a9..7e4f47ca8b3 100755
--- a/.github/scripts/merge_packages.py
+++ b/.github/scripts/merge_packages.py
@@ -1,49 +1,58 @@
 #!/usr/bin/env python
+
 # This script merges two Arduino Board Manager package json files.
 # Usage:
 #   python merge_packages.py package_esp8266com_index.json version/new/package_esp8266com_index.json
 # Written by Ivan Grokhotkov, 2015
 #
+
 from __future__ import print_function
-from distutils.version import LooseVersion
+
+# from distutils.version import LooseVersion
+from packaging.version import Version
 import re
 import json
 import sys
 
+
 def load_package(filename):
-    pkg = json.load(open(filename))['packages'][0]
-    print("Loaded package {0} from {1}".format(pkg['name'], filename), file=sys.stderr)
-    print("{0} platform(s), {1} tools".format(len(pkg['platforms']), len(pkg['tools'])), file=sys.stderr)
+    pkg = json.load(open(filename))["packages"][0]
+    print("Loaded package {0} from {1}".format(pkg["name"], filename), file=sys.stderr)
+    print("{0} platform(s), {1} tools".format(len(pkg["platforms"]), len(pkg["tools"])), file=sys.stderr)
     return pkg
 
+
 def merge_objects(versions, obj):
     for o in obj:
-        name = o['name'].encode('ascii')
-        ver = o['version'].encode('ascii')
-        if not name in versions:
+        name = o["name"].encode("ascii")
+        ver = o["version"].encode("ascii")
+        if name not in versions:
             print("found new object, {0}".format(name), file=sys.stderr)
             versions[name] = {}
-        if not ver in versions[name]:
+        if ver not in versions[name]:
             print("found new version {0} for object {1}".format(ver, name), file=sys.stderr)
             versions[name][ver] = o
     return versions
 
-# Normalize ESP release version string (x.x.x) by adding '-rc<MAXINT>' (x.x.x-rc9223372036854775807) to ensure having REL above any RC
-# Dummy approach, functional anyway for current ESP package versioning (unlike NormalizedVersion/LooseVersion/StrictVersion & similar crap)
+
+# Normalize ESP release version string (x.x.x) by adding '-rc<MAXINT>' (x.x.x-rc9223372036854775807)
+# to ensure having REL above any RC
+# Dummy approach, functional anyway for current ESP package versioning
+# (unlike NormalizedVersion/LooseVersion/StrictVersion & similar crap)
 def pkgVersionNormalized(versionString):
 
     verStr = str(versionString)
-    verParts = re.split('\.|-rc', verStr, flags=re.IGNORECASE)
-    
+    verParts = re.split(r"\.|-rc|-alpha", verStr, flags=re.IGNORECASE)
+
     if len(verParts) == 3:
-        if (sys.version_info > (3, 0)): # Python 3
-            verStr = str(versionString) + '-rc' + str(sys.maxsize)
-        else: # Python 2
-            verStr = str(versionString) + '-rc' + str(sys.maxint)
-        
+        if sys.version_info > (3, 0):  # Python 3
+            verStr = str(versionString) + "-rc" + str(sys.maxsize)
+        else:  # Python 2
+            verStr = str(versionString) + "-rc" + str(sys.maxint)
+
     elif len(verParts) != 4:
         print("pkgVersionNormalized WARNING: unexpected version format: {0})".format(verStr), file=sys.stderr)
-        
+
     return verStr
 
 
@@ -53,30 +62,37 @@ def main(args):
         return 1
 
     tools = {}
-    platforms = {} 
+    platforms = {}
     pkg1 = load_package(args[1])
-    tools = merge_objects(tools, pkg1['tools']);
-    platforms = merge_objects(platforms, pkg1['platforms']);
+    tools = merge_objects(tools, pkg1["tools"])
+    platforms = merge_objects(platforms, pkg1["platforms"])
     pkg2 = load_package(args[2])
-    tools = merge_objects(tools, pkg2['tools']);
-    platforms = merge_objects(platforms, pkg2['platforms']);
+    tools = merge_objects(tools, pkg2["tools"])
+    platforms = merge_objects(platforms, pkg2["platforms"])
 
-    pkg1['tools'] = []
-    pkg1['platforms'] = []
+    pkg1["tools"] = []
+    pkg1["platforms"] = []
 
     for name in tools:
         for version in tools[name]:
             print("Adding tool {0}-{1}".format(name, version), file=sys.stderr)
-            pkg1['tools'].append(tools[name][version])
+            pkg1["tools"].append(tools[name][version])
 
     for name in platforms:
         for version in platforms[name]:
             print("Adding platform {0}-{1}".format(name, version), file=sys.stderr)
-            pkg1['platforms'].append(platforms[name][version])
-                
-    pkg1['platforms'] = sorted(pkg1['platforms'], key=lambda k: LooseVersion(pkgVersionNormalized(k['version'])), reverse=True)
+            pkg1["platforms"].append(platforms[name][version])
+
+    # pkg1["platforms"] = sorted(
+    #     pkg1["platforms"], key=lambda k: LooseVersion(pkgVersionNormalized(k["version"])), reverse=True
+    # )
+
+    pkg1["platforms"] = sorted(
+        pkg1["platforms"], key=lambda k: Version(pkgVersionNormalized(k["version"])), reverse=True
+    )
+
+    json.dump({"packages": [pkg1]}, sys.stdout, indent=2)
 
-    json.dump({'packages':[pkg1]}, sys.stdout, indent=2)
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     sys.exit(main(sys.argv))
diff --git a/.github/scripts/on-pages.sh b/.github/scripts/on-pages.sh
old mode 100644
new mode 100755
index 1b265f91adb..877d036106b
--- a/.github/scripts/on-pages.sh
+++ b/.github/scripts/on-pages.sh
@@ -1,12 +1,13 @@
-#/bin/bash
+#!/bin/bash
+
 set -e
 
-function get_file_size(){
+function get_file_size {
     local file="$1"
     if [[ "$OSTYPE" == "darwin"* ]]; then
-        eval `stat -s "$file"`
+        eval "$(stat -s "$file")"
         local res="$?"
-        echo "$st_size"
+        echo "${st_size:?}"
         return $res
     else
         stat --printf="%s" "$file"
@@ -15,25 +16,32 @@ function get_file_size(){
 }
 
 #git_remove_from_pages <file>
-function git_remove_from_pages(){
+function git_remove_from_pages {
     local path=$1
-    local info=`curl -s -k -H "Authorization: token $GITHUB_TOKEN" -H "Accept: application/vnd.github.v3.object+json" -X GET "https://api.github.com/repos/$GITHUB_REPOSITORY/contents/$path?ref=gh-pages"`
-    local type=`echo "$info" | jq -r '.type'`
-    if [ ! $type == "file" ]; then
-        if [ ! $type == "null" ]; then
+    local info
+    local type
+    local sha
+    local message
+
+    info=$(curl -s -k -H "Authorization: token $GITHUB_TOKEN" -H "Accept: application/vnd.github.v3.object+json" -X GET "https://api.github.com/repos/$GITHUB_REPOSITORY/contents/$path?ref=gh-pages")
+    type=$(echo "$info" | jq -r '.type')
+
+    if [ ! "$type" == "file" ]; then
+        if [ ! "$type" == "null" ]; then
             echo "Wrong type '$type'"
         else
             echo "File is not on Pages"
         fi
         return 0
     fi
-    local sha=`echo "$info" | jq -r '.sha'`
-    local message="Deleting "$(basename $path)
+
+    sha=$(echo "$info" | jq -r '.sha')
+    message="Deleting "$(basename "$path")
     local json="{\"branch\":\"gh-pages\",\"message\":\"$message\",\"sha\":\"$sha\"}"
     echo "$json" | curl -s -k -H "Authorization: token $GITHUB_TOKEN" -H "Accept: application/vnd.github.v3.raw+json" -X DELETE --data @- "https://api.github.com/repos/$GITHUB_REPOSITORY/contents/$path"
 }
 
-function git_upload_to_pages(){
+function git_upload_to_pages {
     local path=$1
     local src=$2
 
@@ -42,41 +50,50 @@ function git_upload_to_pages(){
         return 1
     fi
 
-    local info=`curl -s -k -H "Authorization: token $GITHUB_TOKEN" -H "Accept: application/vnd.github.v3.object+json" -X GET "https://api.github.com/repos/$GITHUB_REPOSITORY/contents/$path?ref=gh-pages"`
-    local type=`echo "$info" | jq -r '.type'`
-    local message=$(basename $path)
+    local info
+    local type
+    local message
     local sha=""
     local content=""
 
-    if [ $type == "file" ]; then
-        sha=`echo "$info" | jq -r '.sha'`
+    info=$(curl -s -k -H "Authorization: token $GITHUB_TOKEN" -H "Accept: application/vnd.github.v3.object+json" -X GET "https://api.github.com/repos/$GITHUB_REPOSITORY/contents/$path?ref=gh-pages")
+    type=$(echo "$info" | jq -r '.type')
+    message=$(basename "$path")
+
+    if [ "$type" == "file" ]; then
+        sha=$(echo "$info" | jq -r '.sha')
         sha=",\"sha\":\"$sha\""
         message="Updating $message"
-    elif [ ! $type == "null" ]; then
+    elif [ ! "$type" == "null" ]; then
         >&2 echo "Wrong type '$type'"
         return 1
     else
         message="Creating $message"
     fi
 
-    content=`base64 -i "$src"`
+    content=$(base64 -i "$src")
     data="{\"branch\":\"gh-pages\",\"message\":\"$message\",\"content\":\"$content\"$sha}"
 
     echo "$data" | curl -s -k -H "Authorization: token $GITHUB_TOKEN" -H "Accept: application/vnd.github.v3.raw+json" -X PUT --data @- "https://api.github.com/repos/$GITHUB_REPOSITORY/contents/$path"
 }
 
-function git_safe_upload_to_pages(){
+function git_safe_upload_to_pages {
     local path=$1
     local file="$2"
-    local name=$(basename "$file")
-    local size=`get_file_size "$file"`
-    local upload_res=`git_upload_to_pages "$path" "$file"`
-    if [ $? -ne 0 ]; then 
+    local name
+    local size
+    local upload_res
+
+    name=$(basename "$file")
+    size=$(get_file_size "$file")
+
+    if ! upload_res=$(git_upload_to_pages "$path" "$file"); then
         >&2 echo "ERROR: Failed to upload '$name' ($?)"
         return 1
     fi
-    up_size=`echo "$upload_res" | jq -r '.content.size'`
-    if [ $up_size -ne $size ]; then
+
+    up_size=$(echo "$upload_res" | jq -r '.content.size')
+    if [ "$up_size" -ne "$size" ]; then
         >&2 echo "ERROR: Uploaded size does not match! $up_size != $size"
         #git_delete_asset
         return 1
@@ -85,47 +102,59 @@ function git_safe_upload_to_pages(){
     return $?
 }
 
-EVENT_JSON=`cat $GITHUB_EVENT_PATH`
+git_safe_upload_to_pages "index.md" "README.md"
 
-pages_added=`echo "$EVENT_JSON" | jq -r '.commits[].added[]'`
-pages_modified=`echo "$EVENT_JSON" | jq -r '.commits[].modified[]'`
-pages_removed=`echo "$EVENT_JSON" | jq -r '.commits[].removed[]'`
+# At some point github stopped providing a list of edited file
+# but we also stopped havong documentation in md format,
+# so we can skip this portion safely and update just the index
 
-for page in $pages_added; do
-    if [[ $page != "README.md" && $page != "docs/"* ]]; then
-        continue
-    fi
-    echo "Adding '$page' to pages ..."
-    if [[ $page == "README.md" ]]; then
-        git_safe_upload_to_pages "index.md" "README.md"
-    else
-        git_safe_upload_to_pages "$page" "$page"
-    fi
-done
+# EVENT_JSON=`cat $GITHUB_EVENT_PATH`
 
-for page in $pages_modified; do
-    if [[ $page != "README.md" && $page != "docs/"* ]]; then
-        continue
-    fi
-    echo "Modifying '$page' ..."
-    if [[ $page == "README.md" ]]; then
-        git_safe_upload_to_pages "index.md" "README.md"
-    else
-        git_safe_upload_to_pages "$page" "$page"
-    fi
-done
+# echo "GITHUB_EVENT_PATH: $GITHUB_EVENT_PATH"
+# echo "EVENT_JSON: $EVENT_JSON"
 
-for page in $pages_removed; do
-    if [[ $page != "README.md" && $page != "docs/"* ]]; then
-        continue
-    fi
-    echo "Removing '$page' from pages ..."
-    if [[ $page == "README.md" ]]; then
-        git_remove_from_pages "README.md" > /dev/null
-    else
-        git_remove_from_pages "$page" > /dev/null
-    fi
-done
+# pages_added=`echo "$EVENT_JSON" | jq -r '.commits[].added[]'`
+# echo "added: $pages_added"
+# pages_modified=`echo "$EVENT_JSON" | jq -r '.commits[].modified[]'`
+# echo "modified: $pages_modified"
+# pages_removed=`echo "$EVENT_JSON" | jq -r '.commits[].removed[]'`
+# echo "removed: $pages_removed"
+
+# for page in $pages_added; do
+#     if [[ $page != "README.md" && $page != "docs/"* ]]; then
+#         continue
+#     fi
+#     echo "Adding '$page' to pages ..."
+#     if [[ $page == "README.md" ]]; then
+#         git_safe_upload_to_pages "index.md" "README.md"
+#     else
+#         git_safe_upload_to_pages "$page" "$page"
+#     fi
+# done
+
+# for page in $pages_modified; do
+#     if [[ $page != "README.md" && $page != "docs/"* ]]; then
+#         continue
+#     fi
+#     echo "Modifying '$page' ..."
+#     if [[ $page == "README.md" ]]; then
+#         git_safe_upload_to_pages "index.md" "README.md"
+#     else
+#         git_safe_upload_to_pages "$page" "$page"
+#     fi
+# done
+
+# for page in $pages_removed; do
+#     if [[ $page != "README.md" && $page != "docs/"* ]]; then
+#         continue
+#     fi
+#     echo "Removing '$page' from pages ..."
+#     if [[ $page == "README.md" ]]; then
+#         git_remove_from_pages "README.md" > /dev/null
+#     else
+#         git_remove_from_pages "$page" > /dev/null
+#     fi
+# done
 
 echo
 echo "DONE!"
diff --git a/.github/scripts/on-push.sh b/.github/scripts/on-push.sh
index e0e14ec2b26..6095f88e727 100755
--- a/.github/scripts/on-push.sh
+++ b/.github/scripts/on-push.sh
@@ -2,70 +2,105 @@
 
 set -e
 
-if [ ! -z "$TRAVIS_TAG" ]; then
-	echo "Skipping Test: Tagged build"
-	exit 0
-fi
+export ARDUINO_BUILD_DIR="$HOME/.arduino/build.tmp"
+
+function build {
+    local target=$1
+    local chunk_index=$2
+    local chunks_cnt=$3
+    local build_log=$4
+    local log_level=${5:-none}
+    local sketches_file=$6
+    shift 6
+    local sketches=("$@")
+
+    local BUILD_SKETCH="${SCRIPTS_DIR}/sketch_utils.sh build"
+    local BUILD_SKETCHES="${SCRIPTS_DIR}/sketch_utils.sh chunk_build"
 
-if [ ! -z "$GITHUB_WORKSPACE" ]; then
-	export TRAVIS_BUILD_DIR="$GITHUB_WORKSPACE"
-	export TRAVIS_REPO_SLUG="$GITHUB_REPOSITORY"
-elif [ ! -z "$TRAVIS_BUILD_DIR" ]; then
-	export GITHUB_WORKSPACE="$TRAVIS_BUILD_DIR"
-	export GITHUB_REPOSITORY="$TRAVIS_REPO_SLUG"
-else
-	export GITHUB_WORKSPACE="$PWD"
-	export GITHUB_REPOSITORY="espressif/arduino-esp32"
+    local args=("-ai" "$ARDUINO_IDE_PATH" "-au" "$ARDUINO_USR_PATH" "-t" "$target")
+
+    if [ "$OS_IS_LINUX" == "1" ]; then
+        args+=("-p" "$ARDUINO_ESP32_PATH/libraries" "-i" "$chunk_index" "-m" "$chunks_cnt" "-d" "$log_level")
+        if [ -n "$sketches_file" ]; then
+            args+=("-f" "$sketches_file")
+        fi
+        if [ "$build_log" -eq 1 ]; then
+            args+=("-l" "$build_log")
+        fi
+        ${BUILD_SKETCHES} "${args[@]}"
+    else
+        for sketch in "${sketches[@]}"; do
+            local sargs=("${args[@]}")
+            local ctags_version
+            local preprocessor_version
+            sargs+=("-s" "$(dirname "$sketch")")
+            if [ "$OS_IS_WINDOWS" == "1" ] && [ -d "$ARDUINO_IDE_PATH/tools-builder" ]; then
+                ctags_version=$(ls "$ARDUINO_IDE_PATH/tools-builder/ctags/")
+                preprocessor_version=$(ls "$ARDUINO_IDE_PATH/tools-builder/arduino-preprocessor/")
+                sargs+=(
+                    "-prefs=runtime.tools.ctags.path=$ARDUINO_IDE_PATH/tools-builder/ctags/$ctags_version"
+                    "-prefs=runtime.tools.arduino-preprocessor.path=$ARDUINO_IDE_PATH/tools-builder/arduino-preprocessor/$preprocessor_version"
+                )
+            fi
+            ${BUILD_SKETCH} "${sargs[@]}"
+        done
+    fi
+}
+
+if [ -z "$GITHUB_WORKSPACE" ]; then
+    export GITHUB_WORKSPACE="$PWD"
+    export GITHUB_REPOSITORY="espressif/arduino-esp32"
 fi
 
 CHUNK_INDEX=$1
 CHUNKS_CNT=$2
-BUILD_PIO=0
+BUILD_LOG=$3
+LOG_LEVEL=$4
+SKETCHES_FILE=$5
 if [ "$#" -lt 2 ] || [ "$CHUNKS_CNT" -le 0 ]; then
-	CHUNK_INDEX=0
-	CHUNKS_CNT=1
-elif [ "$CHUNK_INDEX" -gt "$CHUNKS_CNT" ]; then
-	CHUNK_INDEX=$CHUNKS_CNT
-elif [ "$CHUNK_INDEX" -eq "$CHUNKS_CNT" ]; then
-	BUILD_PIO=1
+    CHUNK_INDEX=0
+    CHUNKS_CNT=1
+elif [ "$CHUNK_INDEX" -gt "$CHUNKS_CNT" ] &&  [ "$CHUNKS_CNT" -ge 2 ]; then
+    CHUNK_INDEX=$CHUNKS_CNT
+fi
+
+if [ -z "$BUILD_LOG" ] || [ "$BUILD_LOG" -le 0 ]; then
+    BUILD_LOG=0
+fi
+
+#echo "Updating submodules ..."
+#git -C "$GITHUB_WORKSPACE" submodule update --init --recursive > /dev/null 2>&1
+
+SCRIPTS_DIR="./.github/scripts"
+source "${SCRIPTS_DIR}/install-arduino-cli.sh"
+source "${SCRIPTS_DIR}/install-arduino-core-esp32.sh"
+
+SKETCHES_ESP32=(
+    "$ARDUINO_ESP32_PATH/libraries/NetworkClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino"
+    "$ARDUINO_ESP32_PATH/libraries/BLE/examples/Server/Server.ino"
+    "$ARDUINO_ESP32_PATH/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino"
+    "$ARDUINO_ESP32_PATH/libraries/Insights/examples/MinimalDiagnostics/MinimalDiagnostics.ino"
+)
+#create sizes_file
+sizes_file="$GITHUB_WORKSPACE/cli_compile_$CHUNK_INDEX.json"
+
+if [ "$BUILD_LOG" -eq 1 ]; then
+    #create sizes_file and echo start of JSON array with "boards" key
+    echo "{\"boards\": [" > "$sizes_file"
 fi
 
-echo "Updating submodules ..."
-git -C "$GITHUB_WORKSPACE" submodule update --init --recursive > /dev/null 2>&1
+#build sketches for different targets
+build "esp32p4" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
+build "esp32s3" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
+build "esp32s2" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
+build "esp32c3" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
+build "esp32c6" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
+build "esp32h2" "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
+build "esp32"   "$CHUNK_INDEX" "$CHUNKS_CNT" "$BUILD_LOG" "$LOG_LEVEL" "$SKETCHES_FILE" "${SKETCHES_ESP32[@]}"
 
-if [ "$BUILD_PIO" -eq 0 ]; then
-	# ArduinoIDE Test
-	FQBN="espressif:esp32:esp32:PSRAM=enabled,PartitionScheme=huge_app"
-	source ./.github/scripts/install-arduino-ide.sh
-	source ./.github/scripts/install-arduino-core-esp32.sh
-	if [ "$OS_IS_WINDOWS" == "1" ]; then
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/WiFiClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino" && \
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/BLE/examples/BLE_server/BLE_server.ino" && \
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/AzureIoT/examples/GetStarted/GetStarted.ino" && \
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino"
-	elif [ "$OS_IS_MACOS" == "1" ]; then
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/WiFi/examples/WiFiClient/WiFiClient.ino" && \
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/WiFiClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino" && \
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino" && \
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/BLE/examples/BLE_server/BLE_server.ino" && \
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/AzureIoT/examples/GetStarted/GetStarted.ino" && \
-		build_sketch "$FQBN" "$ARDUINO_ESP32_PATH/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino"
-	else
-		# CMake Test
-		if [ "$CHUNK_INDEX" -eq 0 ]; then
-			bash "$ARDUINO_ESP32_PATH/.github/scripts/check-cmakelists.sh"
-		fi
-		build_sketches "$FQBN" "$ARDUINO_ESP32_PATH/libraries" "$CHUNK_INDEX" "$CHUNKS_CNT"
-	fi
-else
-	# PlatformIO Test
-	source ./.github/scripts/install-platformio-esp32.sh
-	BOARD="esp32dev"
-	build_pio_sketch "$BOARD" "$PLATFORMIO_ESP32_PATH/libraries/WiFi/examples/WiFiClient/WiFiClient.ino" && \
-	build_pio_sketch "$BOARD" "$PLATFORMIO_ESP32_PATH/libraries/WiFiClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino" && \
-	build_pio_sketch "$BOARD" "$PLATFORMIO_ESP32_PATH/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino" && \
-	build_pio_sketch "$BOARD" "$PLATFORMIO_ESP32_PATH/libraries/BLE/examples/BLE_server/BLE_server.ino" && \
-	build_pio_sketch "$BOARD" "$PLATFORMIO_ESP32_PATH/libraries/AzureIoT/examples/GetStarted/GetStarted.ino" && \
-	build_pio_sketch "$BOARD" "$PLATFORMIO_ESP32_PATH/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino"
-	#build_pio_sketches esp32dev "$PLATFORMIO_ESP32_PATH/libraries"
+if [ "$BUILD_LOG" -eq 1 ]; then
+    #remove last comma from the last JSON object
+    sed -i '$ s/,$//' "$sizes_file"
+    #echo end of JSON array
+    echo "]}" >> "$sizes_file"
 fi
diff --git a/.github/scripts/on-release.sh b/.github/scripts/on-release.sh
index 7b32d9cc544..242cee93d0b 100755
--- a/.github/scripts/on-release.sh
+++ b/.github/scripts/on-release.sh
@@ -1,30 +1,34 @@
 #!/bin/bash
+# Disable shellcheck warning about using 'cat' to read a file.
+# Disable shellcheck warning about using individual redirections for each command.
+# Disable shellcheck warning about $? uses.
+# shellcheck disable=SC2002,SC2129,SC2181,SC2319
 
-if [ ! $GITHUB_EVENT_NAME == "release" ]; then
+if [ ! "$GITHUB_EVENT_NAME" == "release" ]; then
     echo "Wrong event '$GITHUB_EVENT_NAME'!"
     exit 1
 fi
 
-EVENT_JSON=`cat $GITHUB_EVENT_PATH`
+EVENT_JSON=$(cat "$GITHUB_EVENT_PATH")
 
-action=`echo $EVENT_JSON | jq -r '.action'`
-if [ ! $action == "published" ]; then
+action=$(echo "$EVENT_JSON" | jq -r '.action')
+if [ ! "$action" == "published" ]; then
     echo "Wrong action '$action'. Exiting now..."
     exit 0
 fi
 
-draft=`echo $EVENT_JSON | jq -r '.release.draft'`
-if [ $draft == "true" ]; then
+draft=$(echo "$EVENT_JSON" | jq -r '.release.draft')
+if [ "$draft" == "true" ]; then
     echo "It's a draft release. Exiting now..."
     exit 0
 fi
 
-RELEASE_PRE=`echo $EVENT_JSON | jq -r '.release.prerelease'`
-RELEASE_TAG=`echo $EVENT_JSON | jq -r '.release.tag_name'`
-RELEASE_BRANCH=`echo $EVENT_JSON | jq -r '.release.target_commitish'`
-RELEASE_ID=`echo $EVENT_JSON | jq -r '.release.id'`
-RELEASE_BODY=`echo $EVENT_JSON | jq -r '.release.body'`
+RELEASE_PRE=$(echo "$EVENT_JSON" | jq -r '.release.prerelease')
+RELEASE_TAG=$(echo "$EVENT_JSON" | jq -r '.release.tag_name')
+RELEASE_BRANCH=$(echo "$EVENT_JSON" | jq -r '.release.target_commitish')
+RELEASE_ID=$(echo "$EVENT_JSON" | jq -r '.release.id')
 
+SCRIPTS_DIR="./.github/scripts"
 OUTPUT_DIR="$GITHUB_WORKSPACE/build"
 PACKAGE_NAME="esp32-$RELEASE_TAG"
 PACKAGE_JSON_MERGE="$GITHUB_WORKSPACE/.github/scripts/merge_packages.py"
@@ -33,15 +37,27 @@ PACKAGE_JSON_DEV="package_esp32_dev_index.json"
 PACKAGE_JSON_REL="package_esp32_index.json"
 
 echo "Event: $GITHUB_EVENT_NAME, Repo: $GITHUB_REPOSITORY, Path: $GITHUB_WORKSPACE, Ref: $GITHUB_REF"
-echo "Action: $action, Branch: $RELEASE_BRANCH, ID: $RELEASE_ID" 
+echo "Action: $action, Branch: $RELEASE_BRANCH, ID: $RELEASE_ID"
 echo "Tag: $RELEASE_TAG, Draft: $draft, Pre-Release: $RELEASE_PRE"
 
-function get_file_size(){
+# Try extracting something like a JSON with a "boards" array/element and "vendor" fields
+BOARDS=$(echo "$RELEASE_BODY" | grep -Pzo '(?s){.*}' | jq -r '.boards[]? // .boards? // empty' | xargs echo -n 2>/dev/null)
+VENDOR=$(echo "$RELEASE_BODY" | grep -Pzo '(?s){.*}' | jq -r '.vendor? // empty' | xargs echo -n 2>/dev/null)
+
+if [ -n "${BOARDS}" ]; then
+    echo "Releasing board(s): $BOARDS"
+fi
+
+if [ -n "${VENDOR}" ]; then
+    echo "Setting packager: $VENDOR"
+fi
+
+function get_file_size {
     local file="$1"
     if [[ "$OSTYPE" == "darwin"* ]]; then
-        eval `stat -s "$file"`
+        eval "$(stat -s "$file")"
         local res="$?"
-        echo "$st_size"
+        echo "${st_size:?}"
         return $res
     else
         stat --printf="%s" "$file"
@@ -49,23 +65,29 @@ function get_file_size(){
     fi
 }
 
-function git_upload_asset(){
-    local name=$(basename "$1")
+function git_upload_asset {
+    local name
+    name=$(basename "$1")
     # local mime=$(file -b --mime-type "$1")
     curl -k -X POST -sH "Authorization: token $GITHUB_TOKEN" -H "Content-Type: application/octet-stream" --data-binary @"$1" "https://uploads.github.com/repos/$GITHUB_REPOSITORY/releases/$RELEASE_ID/assets?name=$name"
 }
 
-function git_safe_upload_asset(){
+function git_safe_upload_asset {
     local file="$1"
-    local name=$(basename "$file")
-    local size=`get_file_size "$file"`
-    local upload_res=`git_upload_asset "$file"`
-    if [ $? -ne 0 ]; then 
+    local name
+    local size
+    local upload_res
+
+    name=$(basename "$file")
+    size=$(get_file_size "$file")
+
+    if ! upload_res=$(git_upload_asset "$file"); then
         >&2 echo "ERROR: Failed to upload '$name' ($?)"
         return 1
     fi
-    up_size=`echo "$upload_res" | jq -r '.size'`
-    if [ $up_size -ne $size ]; then
+
+    up_size=$(echo "$upload_res" | jq -r '.size')
+    if [ "$up_size" -ne "$size" ]; then
         >&2 echo "ERROR: Uploaded size does not match! $up_size != $size"
         #git_delete_asset
         return 1
@@ -74,7 +96,7 @@ function git_safe_upload_asset(){
     return $?
 }
 
-function git_upload_to_pages(){
+function git_upload_to_pages {
     local path=$1
     local src=$2
 
@@ -83,41 +105,50 @@ function git_upload_to_pages(){
         return 1
     fi
 
-    local info=`curl -s -k -H "Authorization: token $GITHUB_TOKEN" -H "Accept: application/vnd.github.v3.object+json" -X GET "https://api.github.com/repos/$GITHUB_REPOSITORY/contents/$path?ref=gh-pages"`
-    local type=`echo "$info" | jq -r '.type'`
-    local message=$(basename $path)
+    local info
+    local type
+    local message
     local sha=""
     local content=""
 
-    if [ $type == "file" ]; then
-        sha=`echo "$info" | jq -r '.sha'`
+    info=$(curl -s -k -H "Authorization: token $GITHUB_TOKEN" -H "Accept: application/vnd.github.v3.object+json" -X GET "https://api.github.com/repos/$GITHUB_REPOSITORY/contents/$path?ref=gh-pages")
+    type=$(echo "$info" | jq -r '.type')
+    message=$(basename "$path")
+
+    if [ "$type" == "file" ]; then
+        sha=$(echo "$info" | jq -r '.sha')
         sha=",\"sha\":\"$sha\""
         message="Updating $message"
-    elif [ ! $type == "null" ]; then
+    elif [ ! "$type" == "null" ]; then
         >&2 echo "Wrong type '$type'"
         return 1
     else
         message="Creating $message"
     fi
 
-    content=`base64 -i "$src"`
+    content=$(base64 -i "$src")
     data="{\"branch\":\"gh-pages\",\"message\":\"$message\",\"content\":\"$content\"$sha}"
 
     echo "$data" | curl -s -k -H "Authorization: token $GITHUB_TOKEN" -H "Accept: application/vnd.github.v3.raw+json" -X PUT --data @- "https://api.github.com/repos/$GITHUB_REPOSITORY/contents/$path"
 }
 
-function git_safe_upload_to_pages(){
+function git_safe_upload_to_pages {
     local path=$1
     local file="$2"
-    local name=$(basename "$file")
-    local size=`get_file_size "$file"`
-    local upload_res=`git_upload_to_pages "$path" "$file"`
-    if [ $? -ne 0 ]; then 
+    local name
+    local size
+    local upload_res
+
+    name=$(basename "$file")
+    size=$(get_file_size "$file")
+
+    if ! upload_res=$(git_upload_to_pages "$path" "$file"); then
         >&2 echo "ERROR: Failed to upload '$name' ($?)"
         return 1
     fi
-    up_size=`echo "$upload_res" | jq -r '.content.size'`
-    if [ $up_size -ne $size ]; then
+
+    up_size=$(echo "$upload_res" | jq -r '.content.size')
+    if [ "$up_size" -ne "$size" ]; then
         >&2 echo "ERROR: Uploaded size does not match! $up_size != $size"
         #git_delete_asset
         return 1
@@ -126,23 +157,28 @@ function git_safe_upload_to_pages(){
     return $?
 }
 
-function merge_package_json(){
+function merge_package_json {
     local jsonLink=$1
     local jsonOut=$2
     local old_json=$OUTPUT_DIR/oldJson.json
     local merged_json=$OUTPUT_DIR/mergedJson.json
-    
+    local error_code=0
+
     echo "Downloading previous JSON $jsonLink ..."
     curl -L -o "$old_json" "https://github.com/$GITHUB_REPOSITORY/releases/download/$jsonLink?access_token=$GITHUB_TOKEN" 2>/dev/null
-    if [ $? -ne 0 ]; then echo "ERROR: Download Failed! $?"; exit 1; fi
+    error_code=$?
+    if [ $error_code -ne 0 ]; then
+        echo "ERROR: Download Failed! $error_code"
+        exit 1
+    fi
 
     echo "Creating new JSON ..."
     set +e
     stdbuf -oL python "$PACKAGE_JSON_MERGE" "$jsonOut" "$old_json" > "$merged_json"
     set -e
-    
+
     set -v
-    if [ ! -s $merged_json ]; then
+    if [ ! -s "$merged_json" ]; then
         rm -f "$merged_json"
         echo "Nothing to merge"
     else
@@ -171,52 +207,94 @@ mkdir -p "$PKG_DIR/tools"
 
 # Copy all core files to the package folder
 echo "Copying files for packaging ..."
-cp -f  "$GITHUB_WORKSPACE/boards.txt"              "$PKG_DIR/"
-cp -f  "$GITHUB_WORKSPACE/programmers.txt"         "$PKG_DIR/"
-cp -Rf "$GITHUB_WORKSPACE/cores"                   "$PKG_DIR/"
-cp -Rf "$GITHUB_WORKSPACE/libraries"               "$PKG_DIR/"
-cp -Rf "$GITHUB_WORKSPACE/variants"                "$PKG_DIR/"
-cp -f  "$GITHUB_WORKSPACE/tools/espota.exe"        "$PKG_DIR/tools/"
-cp -f  "$GITHUB_WORKSPACE/tools/espota.py"         "$PKG_DIR/tools/"
-cp -f  "$GITHUB_WORKSPACE/tools/esptool.py"        "$PKG_DIR/tools/"
-cp -f  "$GITHUB_WORKSPACE/tools/gen_esp32part.py"  "$PKG_DIR/tools/"
-cp -f  "$GITHUB_WORKSPACE/tools/gen_esp32part.exe" "$PKG_DIR/tools/"
-cp -Rf "$GITHUB_WORKSPACE/tools/partitions"        "$PKG_DIR/tools/"
-cp -Rf "$GITHUB_WORKSPACE/tools/sdk"               "$PKG_DIR/tools/"
+if [ -z "${BOARDS}" ]; then
+    # Copy all variants
+    cp -f  "$GITHUB_WORKSPACE/boards.txt"                   "$PKG_DIR/"
+    cp -Rf "$GITHUB_WORKSPACE/variants"                     "$PKG_DIR/"
+else
+    # Remove all entries not starting with any board code or "menu." from boards.txt
+    cat "$GITHUB_WORKSPACE/boards.txt" | grep "^menu\."         >  "$PKG_DIR/boards.txt"
+    for board in ${BOARDS} ; do
+        cat "$GITHUB_WORKSPACE/boards.txt" | grep "^${board}\." >> "$PKG_DIR/boards.txt"
+    done
+    # Copy only relevant variant files
+    mkdir "$PKG_DIR/variants/"
+    board_list=$(cat "${PKG_DIR}"/boards.txt | grep "\.variant=" | cut -d= -f2)
+    while IFS= read -r variant; do
+        cp -Rf "$GITHUB_WORKSPACE/variants/${variant}"      "$PKG_DIR/variants/"
+    done <<< "$board_list"
+fi
+cp -f  "$GITHUB_WORKSPACE/CMakeLists.txt"                   "$PKG_DIR/"
+cp -f  "$GITHUB_WORKSPACE/idf_component.yml"                "$PKG_DIR/"
+cp -f  "$GITHUB_WORKSPACE/Kconfig.projbuild"                "$PKG_DIR/"
+cp -f  "$GITHUB_WORKSPACE/package.json"                     "$PKG_DIR/"
+cp -f  "$GITHUB_WORKSPACE/programmers.txt"                  "$PKG_DIR/"
+cp -Rf "$GITHUB_WORKSPACE/cores"                            "$PKG_DIR/"
+cp -Rf "$GITHUB_WORKSPACE/libraries"                        "$PKG_DIR/"
+cp -f  "$GITHUB_WORKSPACE/tools/espota.exe"                 "$PKG_DIR/tools/"
+cp -f  "$GITHUB_WORKSPACE/tools/espota.py"                  "$PKG_DIR/tools/"
+cp -f  "$GITHUB_WORKSPACE/tools/gen_esp32part.py"           "$PKG_DIR/tools/"
+cp -f  "$GITHUB_WORKSPACE/tools/gen_esp32part.exe"          "$PKG_DIR/tools/"
+cp -f  "$GITHUB_WORKSPACE/tools/gen_insights_package.py"    "$PKG_DIR/tools/"
+cp -f  "$GITHUB_WORKSPACE/tools/gen_insights_package.exe"   "$PKG_DIR/tools/"
+cp -Rf "$GITHUB_WORKSPACE/tools/partitions"                 "$PKG_DIR/tools/"
+cp -Rf "$GITHUB_WORKSPACE/tools/ide-debug"                  "$PKG_DIR/tools/"
+cp -f  "$GITHUB_WORKSPACE/tools/pioarduino-build.py"        "$PKG_DIR/tools/"
 
 # Remove unnecessary files in the package folder
 echo "Cleaning up folders ..."
 find "$PKG_DIR" -name '*.DS_Store' -exec rm -f {} \;
 find "$PKG_DIR" -name '*.git*' -type f -delete
 
+##
+## TEMP WORKAROUND FOR RV32 LONG PATH ON WINDOWS
+##
+RVTC_NAME="riscv32-esp-elf-gcc"
+RVTC_NEW_NAME="esp-rv32"
+X32TC_NAME="xtensa-esp-elf-gcc"
+X32TC_NEW_NAME="esp-x32"
+
 # Replace tools locations in platform.txt
 echo "Generating platform.txt..."
 cat "$GITHUB_WORKSPACE/platform.txt" | \
-sed "s/version=.*/version=$ver$extent/g" | \
-sed 's/runtime.tools.xtensa-esp32-elf-gcc.path={runtime.platform.path}\/tools\/xtensa-esp32-elf//g' | \
-sed 's/tools.esptool_py.path={runtime.platform.path}\/tools\/esptool/tools.esptool_py.path=\{runtime.tools.esptool_py.path\}/g' \
- > "$PKG_DIR/platform.txt"
+sed "s/version=.*/version=$RELEASE_TAG/g" | \
+sed 's/tools\.esp32-arduino-libs\.path\.windows=.*//g' | \
+sed 's/{runtime\.platform\.path}.tools.esp32-arduino-libs/\{runtime.tools.esp32-arduino-libs.path\}/g' | \
+sed 's/{runtime\.platform\.path}.tools.xtensa-esp-elf-gdb/\{runtime.tools.xtensa-esp-elf-gdb.path\}/g' | \
+sed "s/{runtime\.platform\.path}.tools.xtensa-esp-elf/\\{runtime.tools.$X32TC_NEW_NAME.path\\}/g" | \
+sed 's/{runtime\.platform\.path}.tools.riscv32-esp-elf-gdb/\{runtime.tools.riscv32-esp-elf-gdb.path\}/g' | \
+sed "s/{runtime\.platform\.path}.tools.riscv32-esp-elf/\\{runtime.tools.$RVTC_NEW_NAME.path\\}/g" | \
+sed 's/{runtime\.platform\.path}.tools.esptool/\{runtime.tools.esptool_py.path\}/g' | \
+sed 's/{runtime\.platform\.path}.tools.openocd-esp32/\{runtime.tools.openocd-esp32.path\}/g' > "$PKG_DIR/platform.txt"
+
+if [ -n "${VENDOR}" ]; then
+    # Append vendor name to platform.txt to create a separate section
+    sed -i  "/^name=.*/s/$/ ($VENDOR)/" "$PKG_DIR/platform.txt"
+fi
 
 # Add header with version information
 echo "Generating core_version.h ..."
-ver_define=`echo $RELEASE_TAG | tr "[:lower:].\055" "[:upper:]_"`
-ver_hex=`git -C "$GITHUB_WORKSPACE" rev-parse --short=8 HEAD 2>/dev/null`
-echo \#define ARDUINO_ESP32_GIT_VER 0x$ver_hex > "$PKG_DIR/cores/esp32/core_version.h"
-echo \#define ARDUINO_ESP32_GIT_DESC `git -C "$GITHUB_WORKSPACE" describe --tags 2>/dev/null` >> "$PKG_DIR/cores/esp32/core_version.h"
-echo \#define ARDUINO_ESP32_RELEASE_$ver_define >> "$PKG_DIR/cores/esp32/core_version.h"
-echo \#define ARDUINO_ESP32_RELEASE \"$ver_define\" >> "$PKG_DIR/cores/esp32/core_version.h"
+ver_define=$(echo "$RELEASE_TAG" | tr "[:lower:].\055" "[:upper:]_")
+ver_hex=$(git -C "$GITHUB_WORKSPACE" rev-parse --short=8 HEAD 2>/dev/null)
+echo \#define ARDUINO_ESP32_GIT_VER 0x"$ver_hex" > "$PKG_DIR/cores/esp32/core_version.h"
+echo \#define ARDUINO_ESP32_GIT_DESC "$(git -C "$GITHUB_WORKSPACE" describe --tags 2>/dev/null)" >> "$PKG_DIR/cores/esp32/core_version.h"
+echo \#define ARDUINO_ESP32_RELEASE_"$ver_define" >> "$PKG_DIR/cores/esp32/core_version.h"
+echo \#define ARDUINO_ESP32_RELEASE \""$ver_define"\" >> "$PKG_DIR/cores/esp32/core_version.h"
 
 # Compress package folder
 echo "Creating ZIP ..."
 pushd "$OUTPUT_DIR" >/dev/null
 zip -qr "$PACKAGE_ZIP" "$PACKAGE_NAME"
-if [ $? -ne 0 ]; then echo "ERROR: Failed to create $PACKAGE_ZIP ($?)"; exit 1; fi
+if [ $? -ne 0 ]; then
+    echo "ERROR: Failed to create $PACKAGE_ZIP ($?)"
+    exit 1
+fi
 
 # Calculate SHA-256
 echo "Calculating SHA sum ..."
 PACKAGE_PATH="$OUTPUT_DIR/$PACKAGE_ZIP"
-PACKAGE_SHA=`shasum -a 256 "$PACKAGE_ZIP" | cut -f 1 -d ' '`
-PACKAGE_SIZE=`get_file_size "$PACKAGE_ZIP"`
+PACKAGE_SHA=$(shasum -a 256 "$PACKAGE_ZIP" | cut -f 1 -d ' ')
+PACKAGE_SIZE=$(get_file_size "$PACKAGE_ZIP")
 popd >/dev/null
 rm -rf "$PKG_DIR"
 echo "'$PACKAGE_ZIP' Created! Size: $PACKAGE_SIZE, SHA-256: $PACKAGE_SHA"
@@ -224,11 +302,29 @@ echo
 
 # Upload package to release page
 echo "Uploading package to release page ..."
-PACKAGE_URL=`git_safe_upload_asset "$PACKAGE_PATH"`
+PACKAGE_URL=$(git_safe_upload_asset "$PACKAGE_PATH")
 echo "Package Uploaded"
 echo "Download URL: $PACKAGE_URL"
 echo
 
+##
+## TEMP WORKAROUND FOR RV32 LONG PATH ON WINDOWS
+##
+RVTC_VERSION=$(cat "$PACKAGE_JSON_TEMPLATE" | jq -r ".packages[0].platforms[0].toolsDependencies[] | select(.name == \"$RVTC_NAME\") | .version" | cut -d '_' -f 2)
+# RVTC_VERSION=`date -j -f '%Y%m%d' "$RVTC_VERSION" '+%y%m'` # MacOS
+RVTC_VERSION=$(date -d "$RVTC_VERSION" '+%y%m')
+rvtc_jq_arg="\
+    (.packages[0].platforms[0].toolsDependencies[] | select(.name==\"$RVTC_NAME\")).version = \"$RVTC_VERSION\" |\
+    (.packages[0].platforms[0].toolsDependencies[] | select(.name==\"$RVTC_NAME\")).name = \"$RVTC_NEW_NAME\" |\
+    (.packages[0].tools[] | select(.name==\"$RVTC_NAME\")).version = \"$RVTC_VERSION\" |\
+    (.packages[0].tools[] | select(.name==\"$RVTC_NAME\")).name = \"$RVTC_NEW_NAME\" |\
+    (.packages[0].platforms[0].toolsDependencies[] | select(.name==\"$X32TC_NAME\")).version = \"$RVTC_VERSION\" |\
+    (.packages[0].platforms[0].toolsDependencies[] | select(.name==\"$X32TC_NAME\")).name = \"$X32TC_NEW_NAME\" |\
+    (.packages[0].tools[] | select(.name==\"$X32TC_NAME\")).version = \"$RVTC_VERSION\" |\
+    (.packages[0].tools[] | select(.name==\"$X32TC_NAME\")).name = \"$X32TC_NEW_NAME\""
+cat "$PACKAGE_JSON_TEMPLATE" | jq "$rvtc_jq_arg" > "$OUTPUT_DIR/package-rvfix.json"
+PACKAGE_JSON_TEMPLATE="$OUTPUT_DIR/package-rvfix.json"
+
 ##
 ## PACKAGE JSON
 ##
@@ -241,137 +337,122 @@ jq_arg=".packages[0].platforms[0].version = \"$RELEASE_TAG\" | \
     .packages[0].platforms[0].checksum = \"SHA-256:$PACKAGE_SHA\""
 
 # Generate package JSONs
-echo "Genarating $PACKAGE_JSON_DEV ..."
+echo "Generating $PACKAGE_JSON_DEV ..."
 cat "$PACKAGE_JSON_TEMPLATE" | jq "$jq_arg" > "$OUTPUT_DIR/$PACKAGE_JSON_DEV"
 if [ "$RELEASE_PRE" == "false" ]; then
-    echo "Genarating $PACKAGE_JSON_REL ..."
+    echo "Generating $PACKAGE_JSON_REL ..."
     cat "$PACKAGE_JSON_TEMPLATE" | jq "$jq_arg" > "$OUTPUT_DIR/$PACKAGE_JSON_REL"
 fi
 
 # Figure out the last release or pre-release
 echo "Getting previous releases ..."
-releasesJson=`curl -sH "Authorization: token $GITHUB_TOKEN" "https://api.github.com/repos/$GITHUB_REPOSITORY/releases" 2>/dev/null`
-if [ $? -ne 0 ]; then echo "ERROR: Get Releases Failed! ($?)"; exit 1; fi
+releasesJson=$(curl -sH "Authorization: token $GITHUB_TOKEN" "https://api.github.com/repos/$GITHUB_REPOSITORY/releases" 2>/dev/null)
+if [ $? -ne 0 ]; then
+    echo "ERROR: Get Releases Failed! ($?)"
+    exit 1
+fi
 
 set +e
-prev_release=$(echo "$releasesJson" | jq -e -r '. | map(select(.draft == false and .prerelease == false)) | sort_by(.created_at | - fromdateiso8601) | .[0].tag_name')
-prev_any_release=$(echo "$releasesJson" | jq -e -r '. | map(select(.draft == false)) | sort_by(.created_at | - fromdateiso8601)  | .[0].tag_name')
+prev_release=$(echo "$releasesJson" | jq -e -r ". | map(select(.draft == false and .prerelease == false)) | sort_by(.published_at | - fromdateiso8601) | .[0].tag_name")
+prev_any_release=$(echo "$releasesJson" | jq -e -r ". | map(select(.draft == false)) | sort_by(.published_at | - fromdateiso8601)  | .[0].tag_name")
 shopt -s nocasematch
+if [ "$prev_release" == "$RELEASE_TAG" ]; then
+    prev_release=$(echo "$releasesJson" | jq -e -r ". | map(select(.draft == false and .prerelease == false)) | sort_by(.published_at | - fromdateiso8601) | .[1].tag_name")
+fi
 if [ "$prev_any_release" == "$RELEASE_TAG" ]; then
-    prev_release=$(echo "$releasesJson" | jq -e -r '. | map(select(.draft == false and .prerelease == false)) | sort_by(.created_at | - fromdateiso8601) | .[1].tag_name')
-    prev_any_release=$(echo "$releasesJson" | jq -e -r '. | map(select(.draft == false)) | sort_by(.created_at | - fromdateiso8601)  | .[1].tag_name')
+    prev_any_release=$(echo "$releasesJson" | jq -e -r ". | map(select(.draft == false)) | sort_by(.published_at | - fromdateiso8601)  | .[1].tag_name")
 fi
-COMMITS_SINCE_RELEASE="$prev_any_release"
 shopt -u nocasematch
 set -e
 
+echo "Previous Release: $prev_release"
+echo "Previous (any)release: $prev_any_release"
+echo
+
 # Merge package JSONs with previous releases
-if [ ! -z "$prev_any_release" ] && [ "$prev_any_release" != "null" ]; then
+if [ -n "$prev_any_release" ] && [ "$prev_any_release" != "null" ]; then
     echo "Merging with JSON from $prev_any_release ..."
     merge_package_json "$prev_any_release/$PACKAGE_JSON_DEV" "$OUTPUT_DIR/$PACKAGE_JSON_DEV"
 fi
 
 if [ "$RELEASE_PRE" == "false" ]; then
-    COMMITS_SINCE_RELEASE="$prev_release"
-    if [ ! -z "$prev_release" ] && [ "$prev_release" != "null" ]; then
+    if [ -n "$prev_release" ] && [ "$prev_release" != "null" ]; then
         echo "Merging with JSON from $prev_release ..."
         merge_package_json "$prev_release/$PACKAGE_JSON_REL" "$OUTPUT_DIR/$PACKAGE_JSON_REL"
     fi
 fi
 
-echo "Previous Release: $prev_release"
-echo "Previous (any)release: $prev_any_release"
-echo
+# Test the package JSONs
 
-# Upload package JSONs
-echo "Uploading $PACKAGE_JSON_DEV ..."
-echo "Download URL: "`git_safe_upload_asset "$OUTPUT_DIR/$PACKAGE_JSON_DEV"`
-echo "Pages URL: "`git_safe_upload_to_pages "$PACKAGE_JSON_DEV" "$OUTPUT_DIR/$PACKAGE_JSON_DEV"`
-echo
-if [ "$RELEASE_PRE" == "false" ]; then
-    echo "Uploading $PACKAGE_JSON_REL ..."
-    echo "Download URL: "`git_safe_upload_asset "$OUTPUT_DIR/$PACKAGE_JSON_REL"`
-    echo "Pages URL: "`git_safe_upload_to_pages "$PACKAGE_JSON_REL" "$OUTPUT_DIR/$PACKAGE_JSON_REL"`
-    echo
-fi
+echo "Installing arduino-cli ..."
+export PATH="/home/runner/bin:$PATH"
+source "${SCRIPTS_DIR}/install-arduino-cli.sh"
 
-##
-## RELEASE NOTES
-##
+echo "Testing $PACKAGE_JSON_DEV install ..."
 
-# Create release notes
-echo "Preparing release notes ..."
-releaseNotes=""
-
-# Process annotated tags
-relNotesRaw=`git -C "$GITHUB_WORKSPACE" show -s --format=%b $RELEASE_TAG`
-readarray -t msgArray <<<"$relNotesRaw"
-arrLen=${#msgArray[@]}
-if [ $arrLen > 3 ] && [ "${msgArray[0]:0:3}" == "tag" ]; then 
-    ind=3
-    while [ $ind -lt $arrLen ]; do
-        if [ $ind -eq 3 ]; then
-            releaseNotes="#### ${msgArray[ind]}"
-            releaseNotes+=$'\r\n'
-        else
-            oneLine="$(echo -e "${msgArray[ind]}" | sed -e 's/^[[:space:]]*//')"
-            if [ ${#oneLine} -gt 0 ]; then
-                if [ "${oneLine:0:2}" == "* " ]; then oneLine=$(echo ${oneLine/\*/-}); fi
-                if [ "${oneLine:0:2}" != "- " ]; then releaseNotes+="- "; fi        
-                releaseNotes+="$oneLine"
-                releaseNotes+=$'\r\n'
-            fi
-        fi
-        let ind=$ind+1
-    done
+echo "Installing esp32 ..."
+arduino-cli core install esp32:esp32 --additional-urls "file://$OUTPUT_DIR/$PACKAGE_JSON_DEV"
+if [ $? -ne 0 ]; then
+    echo "ERROR: Failed to install esp32 ($?)"
+    exit 1
 fi
 
-# Append Commit Messages
-if [ ! -z "$COMMITS_SINCE_RELEASE" ] && [ "$COMMITS_SINCE_RELEASE" != "null" ]; then
-    echo "Getting commits since $COMMITS_SINCE_RELEASE ..."
-    commitFile=$OUTPUT_DIR/commits.txt
-    git -C "$GITHUB_WORKSPACE" log --oneline "$COMMITS_SINCE_RELEASE..HEAD" > "$OUTPUT_DIR/commits.txt"
-    releaseNotes+=$'\r\n##### Commits\r\n'
-    IFS=$'\n'
-    for next in `cat $commitFile`
-    do
-        IFS=' ' read -r commitId commitMsg <<< "$next"
-        commitLine="- [$commitId](https://github.com/$GITHUB_REPOSITORY/commit/$commitId) $commitMsg"
-        releaseNotes+="$commitLine"
-        releaseNotes+=$'\r\n'
-    done
-    rm -f $commitFile
+echo "Compiling example ..."
+arduino-cli compile --fqbn esp32:esp32:esp32 "$GITHUB_WORKSPACE"/libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino
+if [ $? -ne 0 ]; then
+    echo "ERROR: Failed to compile example ($?)"
+    exit 1
 fi
 
-# Prepend the original release body
-if [ "${RELEASE_BODY: -1}" == $'\r' ]; then         
-    RELEASE_BODY="${RELEASE_BODY:0:-1}"
-else 
-    RELEASE_BODY="$RELEASE_BODY"
+echo "Uninstalling esp32 ..."
+arduino-cli core uninstall esp32:esp32
+if [ $? -ne 0 ]; then
+    echo "ERROR: Failed to uninstall esp32 ($?)"
+    exit 1
 fi
-RELEASE_BODY+=$'\r\n'
-releaseNotes="$RELEASE_BODY$releaseNotes"
-
-# Update release page
-echo "Updating release notes ..."
-releaseNotes=$(printf '%s' "$releaseNotes" | python -c 'import json,sys; print(json.dumps(sys.stdin.read()))')
-releaseNotes=${releaseNotes:1:-1}
-curlData="{\"body\": \"$releaseNotes\"}"
-releaseData=`curl --data "$curlData" "https://api.github.com/repos/$GITHUB_REPOSITORY/releases/$RELEASE_ID?access_token=$GITHUB_TOKEN" 2>/dev/null`
-if [ $? -ne 0 ]; then echo "ERROR: Updating Release Failed: $?"; exit 1; fi
-echo "Release notes successfully updated"
-echo
 
-##
-## SUBMODULE VERSIONS
-##
+echo "Test successful!"
+
+if [ "$RELEASE_PRE" == "false" ]; then
+    echo "Testing $PACKAGE_JSON_REL install ..."
+
+    echo "Installing esp32 ..."
+    arduino-cli core install esp32:esp32 --additional-urls "file://$OUTPUT_DIR/$PACKAGE_JSON_REL"
+    if [ $? -ne 0 ]; then
+        echo "ERROR: Failed to install esp32 ($?)"
+        exit 1
+    fi
+
+    echo "Compiling example ..."
+    arduino-cli compile --fqbn esp32:esp32:esp32 "$GITHUB_WORKSPACE"/libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino
+    if [ $? -ne 0 ]; then
+        echo "ERROR: Failed to compile example ($?)"
+        exit 1
+    fi
+
+    echo "Uninstalling esp32 ..."
+    arduino-cli core uninstall esp32:esp32
+    if [ $? -ne 0 ]; then
+        echo "ERROR: Failed to uninstall esp32 ($?)"
+        exit 1
+    fi
+
+    echo "Test successful!"
+fi
+
+# Upload package JSONs
+
+echo "Uploading $PACKAGE_JSON_DEV ..."
+echo "Download URL: $(git_safe_upload_asset "$OUTPUT_DIR/$PACKAGE_JSON_DEV")"
+echo "Pages URL: $(git_safe_upload_to_pages "$PACKAGE_JSON_DEV" "$OUTPUT_DIR/$PACKAGE_JSON_DEV")"
+echo
+if [ "$RELEASE_PRE" == "false" ]; then
+    echo "Uploading $PACKAGE_JSON_REL ..."
+    echo "Download URL: $(git_safe_upload_asset "$OUTPUT_DIR/$PACKAGE_JSON_REL")"
+    echo "Pages URL: $(git_safe_upload_to_pages "$PACKAGE_JSON_REL" "$OUTPUT_DIR/$PACKAGE_JSON_REL")"
+    echo
+fi
 
-# Upload submodules versions
-echo "Generating submodules.txt ..."
-git -C "$GITHUB_WORKSPACE" submodule status > "$OUTPUT_DIR/submodules.txt"
-echo "Uploading submodules.txt ..."
-echo "Download URL: "`git_safe_upload_asset "$OUTPUT_DIR/submodules.txt"`
-echo ""
 set +e
 
 ##
diff --git a/.github/scripts/set_push_chunks.sh b/.github/scripts/set_push_chunks.sh
new file mode 100644
index 00000000000..ff0af7da6e8
--- /dev/null
+++ b/.github/scripts/set_push_chunks.sh
@@ -0,0 +1,84 @@
+#!/bin/bash
+
+build_all=false
+chunks_count=0
+
+if [[ $CORE_CHANGED == 'true' ]] || [[ $IS_PR != 'true' ]]; then
+    echo "Core files changed or not a PR. Building all."
+    build_all=true
+    chunks_count=$MAX_CHUNKS
+elif [[ $LIB_CHANGED == 'true' ]]; then
+    echo "Libraries changed. Building only affected sketches."
+    if [[ $NETWORKING_CHANGED == 'true' ]]; then
+        echo "Networking libraries changed. Building networking related sketches."
+        networking_sketches="$(find libraries/WiFi -name '*.ino') "
+        networking_sketches+="$(find libraries/Ethernet -name '*.ino') "
+        networking_sketches+="$(find libraries/PPP -name '*.ino') "
+        networking_sketches+="$(find libraries/NetworkClientSecure -name '*.ino') "
+        networking_sketches+="$(find libraries/WebServer -name '*.ino') "
+    fi
+    if [[ $FS_CHANGED == 'true' ]]; then
+        echo "FS libraries changed. Building FS related sketches."
+        fs_sketches="$(find libraries/SD -name '*.ino') "
+        fs_sketches+="$(find libraries/SD_MMC -name '*.ino') "
+        fs_sketches+="$(find libraries/SPIFFS -name '*.ino') "
+        fs_sketches+="$(find libraries/LittleFS -name '*.ino') "
+        fs_sketches+="$(find libraries/FFat -name '*.ino') "
+    fi
+    sketches="$networking_sketches $fs_sketches"
+    for file in $LIB_FILES; do
+        lib=$(echo "$file" | awk -F "/" '{print $1"/"$2}')
+        if [[ "$file" == *.ino ]]; then
+            # If file ends with .ino, add it to the list of sketches
+            echo "Sketch found: $file"
+            sketches+="$file "
+        elif [[ "$file" == "$lib/src/"* ]]; then
+            # If file is inside the src directory, find all sketches in the lib/examples directory
+            echo "Library src file found: $file"
+            if [[ -d $lib/examples ]]; then
+                lib_sketches=$(find "$lib"/examples -name '*.ino')
+                sketches+="$lib_sketches "
+                echo "Library sketches: $lib_sketches"
+            fi
+        else
+            # If file is in a example folder but it is not a sketch, find all sketches in the current directory
+            echo "File in example folder found: $file"
+            sketch=$(find "$(dirname "$file")" -name '*.ino')
+            sketches+="$sketch "
+            echo "Sketch in example folder: $sketch"
+        fi
+        echo ""
+    done
+fi
+
+if [[ -n $sketches ]]; then
+    # Remove duplicates
+    sketches=$(echo "$sketches" | tr ' ' '\n' | sort | uniq)
+    for sketch in $sketches; do
+        echo "$sketch" >> sketches_found.txt
+        chunks_count=$((chunks_count+1))
+    done
+    echo "Number of sketches found: $chunks_count"
+    echo "Sketches:"
+    echo "$sketches"
+
+    if [[ $chunks_count -gt $MAX_CHUNKS ]]; then
+        echo "More sketches than the allowed number of chunks found. Limiting to $MAX_CHUNKS chunks."
+        chunks_count=$MAX_CHUNKS
+    fi
+fi
+
+chunks='["0"'
+for i in $(seq 1 $(( chunks_count - 1 )) ); do
+    chunks+=",\"$i\""
+done
+chunks+="]"
+
+{
+    echo "build_all=$build_all"
+    echo "build_libraries=$BUILD_LIBRARIES"
+    echo "build_static_sketches=$BUILD_STATIC_SKETCHES"
+    echo "build_idf=$BUILD_IDF"
+    echo "chunk_count=$chunks_count"
+    echo "chunks=$chunks"
+} >> "$GITHUB_OUTPUT"
diff --git a/.github/scripts/sketch_utils.sh b/.github/scripts/sketch_utils.sh
new file mode 100755
index 00000000000..e536da50111
--- /dev/null
+++ b/.github/scripts/sketch_utils.sh
@@ -0,0 +1,608 @@
+#!/bin/bash
+
+if [ -d "$ARDUINO_ESP32_PATH/tools/esp32-arduino-libs" ]; then
+    SDKCONFIG_DIR="$ARDUINO_ESP32_PATH/tools/esp32-arduino-libs"
+elif [ -d "$GITHUB_WORKSPACE/tools/esp32-arduino-libs" ]; then
+    SDKCONFIG_DIR="$GITHUB_WORKSPACE/tools/esp32-arduino-libs"
+else
+    SDKCONFIG_DIR="tools/esp32-arduino-libs"
+fi
+
+function check_requirements { # check_requirements <sketchdir> <sdkconfig_path>
+    local sketchdir=$1
+    local sdkconfig_path=$2
+    local has_requirements=1
+    local requirements
+    local requirements_or
+
+    if [ ! -f "$sdkconfig_path" ] || [ ! -f "$sketchdir/ci.json" ]; then
+        echo "ERROR: sdkconfig or ci.json not found" 1>&2
+        # Return 1 on error to force the sketch to be built and fail. This way the
+        # CI will fail and the user will know that the sketch has a problem.
+    else
+        # Check if the sketch requires any configuration options (AND)
+        requirements=$(jq -r '.requires[]? // empty' "$sketchdir/ci.json")
+        if [[ "$requirements" != "null" && "$requirements" != "" ]]; then
+            for requirement in $requirements; do
+                requirement=$(echo "$requirement" | xargs)
+                found_line=$(grep -E "^$requirement" "$sdkconfig_path")
+                if [[ "$found_line" == "" ]]; then
+                    has_requirements=0
+                fi
+            done
+        fi
+
+        # Check if the sketch requires any configuration options (OR)
+        requirements_or=$(jq -r '.requires_any[]? // empty' "$sketchdir/ci.json")
+        if [[ "$requirements_or" != "null" && "$requirements_or" != "" ]]; then
+            local found=false
+            for requirement in $requirements_or; do
+                requirement=$(echo "$requirement" | xargs)
+                found_line=$(grep -E "^$requirement" "$sdkconfig_path")
+                if [[ "$found_line" != "" ]]; then
+                    found=true
+                    break
+                fi
+            done
+            if [[ "$found" == "false" ]]; then
+                has_requirements=0
+            fi
+        fi
+    fi
+
+    echo $has_requirements
+}
+
+function build_sketch { # build_sketch <ide_path> <user_path> <path-to-ino> [extra-options]
+    while [ -n "$1" ]; do
+        case "$1" in
+        -ai )
+            shift
+            ide_path=$1
+            ;;
+        -au )
+            shift
+            user_path=$1
+            ;;
+        -t )
+            shift
+            target=$1
+            ;;
+        -fqbn )
+            shift
+            fqbn=$1
+            ;;
+        -o )
+            shift
+            options=$1
+            ;;
+        -s )
+            shift
+            sketchdir=$1
+            ;;
+        -i )
+            shift
+            chunk_index=$1
+            ;;
+        -l )
+            shift
+            log_compilation=$1
+            ;;
+        -d )
+            shift
+            debug_level="DebugLevel=$1"
+            ;;
+        * )
+            break
+            ;;
+        esac
+        shift
+    done
+
+    xtra_opts=("$@")
+    len=0
+
+    if [ -z "$sketchdir" ]; then
+        echo "ERROR: Sketch directory not provided"
+        echo "$USAGE"
+        exit 1
+    fi
+
+    # No FQBN was passed, try to get it from other options
+
+    if [ -z "$fqbn" ]; then
+        if [ -z "$target" ]; then
+            echo "ERROR: Unspecified chip"
+            echo "$USAGE"
+            exit 1
+        fi
+
+        # The options are either stored in the test directory, for a per test
+        # customization or passed as parameters.  Command line options take
+        # precedence.  Note that the following logic also falls to the default
+        # parameters if no arguments were passed and no file was found.
+
+        if [ -z "$options" ] && [ -f "$sketchdir"/ci.json ]; then
+            # The config file could contain multiple FQBNs for one chip.  If
+            # that's the case we build one time for every FQBN.
+
+            len=$(jq -r --arg target "$target" '.fqbn[$target] | length' "$sketchdir"/ci.json)
+            if [ "$len" -gt 0 ]; then
+                fqbn=$(jq -r --arg target "$target" '.fqbn[$target] | sort' "$sketchdir"/ci.json)
+            fi
+        fi
+
+        if [ -n "$options" ] || [ "$len" -eq 0 ]; then
+            # Since we are passing options, we will end up with only one FQBN to
+            # build.
+
+            len=1
+
+            if [ -f "$sketchdir"/ci.json ]; then
+                fqbn_append=$(jq -r '.fqbn_append' "$sketchdir"/ci.json)
+                if [ "$fqbn_append" == "null" ]; then
+                    fqbn_append=""
+                fi
+            fi
+
+            # Default FQBN options if none were passed in the command line.
+            # Replace any double commas with a single one and strip leading and
+            # trailing commas.
+
+            esp32_opts=$(echo "PSRAM=enabled,$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
+            esp32s2_opts=$(echo "PSRAM=enabled,$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
+            esp32s3_opts=$(echo "PSRAM=opi,USBMode=default,$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
+            esp32c3_opts=$(echo "$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
+            esp32c6_opts=$(echo "$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
+            esp32h2_opts=$(echo "$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
+            esp32p4_opts=$(echo "PSRAM=enabled,USBMode=default,$debug_level,$fqbn_append" | sed 's/^,*//;s/,*$//;s/,\{2,\}/,/g')
+
+            # Select the common part of the FQBN based on the target.  The rest will be
+            # appended depending on the passed options.
+
+            opt=""
+
+            case "$target" in
+                "esp32")
+                    [ -n "${options:-$esp32_opts}" ] && opt=":${options:-$esp32_opts}"
+                    fqbn="espressif:esp32:esp32$opt"
+                ;;
+                "esp32s2")
+                    [ -n "${options:-$esp32s2_opts}" ] && opt=":${options:-$esp32s2_opts}"
+                    fqbn="espressif:esp32:esp32s2$opt"
+                ;;
+                "esp32c3")
+                    [ -n "${options:-$esp32c3_opts}" ] && opt=":${options:-$esp32c3_opts}"
+                    fqbn="espressif:esp32:esp32c3$opt"
+                ;;
+                "esp32s3")
+                    [ -n "${options:-$esp32s3_opts}" ] && opt=":${options:-$esp32s3_opts}"
+                    fqbn="espressif:esp32:esp32s3$opt"
+                ;;
+                "esp32c6")
+                    [ -n "${options:-$esp32c6_opts}" ] && opt=":${options:-$esp32c6_opts}"
+                    fqbn="espressif:esp32:esp32c6$opt"
+                ;;
+                "esp32h2")
+                    [ -n "${options:-$esp32h2_opts}" ] && opt=":${options:-$esp32h2_opts}"
+                    fqbn="espressif:esp32:esp32h2$opt"
+                ;;
+                "esp32p4")
+                    [ -n "${options:-$esp32p4_opts}" ] && opt=":${options:-$esp32p4_opts}"
+                    fqbn="espressif:esp32:esp32p4$opt"
+                ;;
+                *)
+                    echo "ERROR: Invalid chip: $target"
+                    exit 1
+                ;;
+            esac
+
+            # Make it look like a JSON array.
+
+            fqbn="[\"$fqbn\"]"
+        fi
+    else
+        # An FQBN was passed.  Make it look like a JSON array.
+
+        len=1
+        fqbn="[\"$fqbn\"]"
+    fi
+
+    if [ -z "$fqbn" ]; then
+        echo "No FQBN passed or invalid chip: $target"
+        exit 1
+    fi
+
+    # The directory that will hold all the artifacts (the build directory) is
+    # provided through:
+    #  1. An env variable called ARDUINO_BUILD_DIR.
+    #  2. Created at the sketch level as "build" in the case of a single
+    #     configuration test.
+    #  3. Created at the sketch level as "buildX" where X is the number
+    #     of configuration built in case of a multiconfiguration test.
+
+    sketchname=$(basename "$sketchdir")
+    local has_requirements
+
+    if [ -f "$sketchdir"/ci.json ]; then
+        # If the target is listed as false, skip the sketch. Otherwise, include it.
+        is_target=$(jq -r --arg target "$target" '.targets[$target]' "$sketchdir"/ci.json)
+        if [[ "$is_target" == "false" ]]; then
+            echo "Skipping $sketchname for target $target"
+            exit 0
+        fi
+
+        has_requirements=$(check_requirements "$sketchdir" "$SDKCONFIG_DIR/$target/sdkconfig")
+        if [ "$has_requirements" == "0" ]; then
+            echo "Target $target does not meet the requirements for $sketchname. Skipping."
+            exit 0
+        fi
+    fi
+
+    ARDUINO_CACHE_DIR="$HOME/.arduino/cache.tmp"
+    if [ -n "$ARDUINO_BUILD_DIR" ]; then
+        build_dir="$ARDUINO_BUILD_DIR"
+    elif [ "$len" -eq 1 ]; then
+        # build_dir="$sketchdir/build"
+        build_dir="$HOME/.arduino/tests/$target/$sketchname/build.tmp"
+    fi
+
+    output_file="$HOME/.arduino/cli_compile_output.txt"
+    sizes_file="$GITHUB_WORKSPACE/cli_compile_$chunk_index.json"
+
+    mkdir -p "$ARDUINO_CACHE_DIR"
+    for i in $(seq 0 $((len - 1))); do
+        if [ "$len" -ne 1 ]; then
+            # build_dir="$sketchdir/build$i"
+            build_dir="$HOME/.arduino/tests/$target/$sketchname/build$i.tmp"
+        fi
+        rm -rf "$build_dir"
+        mkdir -p "$build_dir"
+
+        currfqbn=$(echo "$fqbn" | jq -r --argjson i "$i" '.[$i]')
+
+        if [ -f "$ide_path/arduino-cli" ]; then
+            echo "Building $sketchname with arduino-cli and FQBN=$currfqbn"
+
+            curroptions=$(echo "$currfqbn" | cut -d':' -f4)
+            currfqbn=$(echo "$currfqbn" | cut -d':' -f1-3)
+            "$ide_path"/arduino-cli compile \
+                --fqbn "$currfqbn" \
+                --board-options "$curroptions" \
+                --warnings "all" \
+                --build-property "compiler.warning_flags.all=-Wall -Werror=all -Wextra" \
+                --build-path "$build_dir" \
+                "${xtra_opts[@]}" "${sketchdir}" \
+                2>&1 | tee "$output_file"
+
+            exit_status=${PIPESTATUS[0]}
+            if [ "$exit_status" -ne 0 ]; then
+                echo "ERROR: Compilation failed with error code $exit_status"
+                exit "$exit_status"
+            fi
+
+            if [ -n "$log_compilation" ]; then
+                #Extract the program storage space and dynamic memory usage in bytes and percentage in separate variables from the output, just the value without the string
+                flash_bytes=$(grep -oE 'Sketch uses ([0-9]+) bytes' "$output_file" | awk '{print $3}')
+                flash_percentage=$(grep -oE 'Sketch uses ([0-9]+) bytes \(([0-9]+)%\)' "$output_file" | awk '{print $5}' | tr -d '(%)')
+                ram_bytes=$(grep -oE 'Global variables use ([0-9]+) bytes' "$output_file" | awk '{print $4}')
+                ram_percentage=$(grep -oE 'Global variables use ([0-9]+) bytes \(([0-9]+)%\)' "$output_file" | awk '{print $6}' | tr -d '(%)')
+
+                # Extract the directory path excluding the filename
+                directory_path=$(dirname "$sketch")
+                # Define the constant part
+                constant_part="/home/runner/Arduino/hardware/espressif/esp32/libraries/"
+                # Extract the desired substring
+                lib_sketch_name="${directory_path#"$constant_part"}"
+                #append json file where key is fqbn, sketch name, sizes -> extracted values
+                echo "{\"name\": \"$lib_sketch_name\",
+                    \"sizes\": [{
+                            \"flash_bytes\": $flash_bytes,
+                            \"flash_percentage\": $flash_percentage,
+                            \"ram_bytes\": $ram_bytes,
+                            \"ram_percentage\": $ram_percentage
+                            }]
+                    }," >> "$sizes_file"
+            fi
+
+        elif [ -f "$ide_path/arduino-builder" ]; then
+            echo "Building $sketchname with arduino-builder and FQBN=$currfqbn"
+            echo "Build path = $build_dir"
+
+            "$ide_path"/arduino-builder -compile -logger=human -core-api-version=10810 \
+                -fqbn=\""$currfqbn"\" \
+                -warnings="all" \
+                -tools "$ide_path/tools-builder" \
+                -hardware "$user_path/hardware" \
+                -libraries "$user_path/libraries" \
+                -build-cache "$ARDUINO_CACHE_DIR" \
+                -build-path "$build_dir" \
+                "${xtra_opts[@]}" "${sketchdir}/${sketchname}.ino"
+
+            exit_status=$?
+            if [ $exit_status -ne 0 ]; then
+                echo "ERROR: Compilation failed with error code $exit_status"
+                exit $exit_status
+            fi
+            # $ide_path/arduino-builder -compile -logger=human -core-api-version=10810 \
+            #     -fqbn=\"$currfqbn\" \
+            #     -warnings="all" \
+            #     -tools "$ide_path/tools-builder" \
+            #     -tools "$ide_path/tools" \
+            #     -built-in-libraries "$ide_path/libraries" \
+            #     -hardware "$ide_path/hardware" \
+            #     -hardware "$user_path/hardware" \
+            #     -libraries "$user_path/libraries" \
+            #     -build-cache "$ARDUINO_CACHE_DIR" \
+            #     -build-path "$build_dir" \
+            #     $xtra_opts "${sketchdir}/${sketchname}.ino"
+        fi
+    done
+
+    unset fqbn
+    unset xtra_opts
+    unset options
+}
+
+function count_sketches { # count_sketches <path> [target] [file] [ignore-requirements]
+    local path=$1
+    local target=$2
+    local ignore_requirements=$3
+    local file=$4
+    local sketches
+
+    if [ $# -lt 1 ]; then
+        echo "ERROR: Illegal number of parameters"
+        echo "USAGE: ${0} count <path> [target]"
+    fi
+
+    rm -rf sketches.txt
+    touch sketches.txt
+    if [ ! -d "$path" ]; then
+        return 0
+    fi
+
+    if [ -f "$file" ]; then
+        sketches=$(cat "$file")
+    else
+        sketches=$(find "$path" -name '*.ino' | sort)
+    fi
+
+    local sketchnum=0
+    for sketch in $sketches; do
+        local sketchdir
+        local sketchdirname
+        local sketchname
+        local has_requirements
+
+        sketchdir=$(dirname "$sketch")
+        sketchdirname=$(basename "$sketchdir")
+        sketchname=$(basename "$sketch")
+
+        if [[ "$sketchdirname.ino" != "$sketchname" ]]; then
+            continue
+        elif [[ -n $target ]] && [[ -f $sketchdir/ci.json ]]; then
+            # If the target is listed as false, skip the sketch. Otherwise, include it.
+            is_target=$(jq -r --arg target "$target" '.targets[$target]' "$sketchdir"/ci.json)
+            if [[ "$is_target" == "false" ]]; then
+                continue
+            fi
+
+            if [ "$ignore_requirements" != "1" ]; then
+                has_requirements=$(check_requirements "$sketchdir" "$SDKCONFIG_DIR/$target/sdkconfig")
+                if [ "$has_requirements" == "0" ]; then
+                    continue
+                fi
+            fi
+        fi
+        echo "$sketch" >> sketches.txt
+        sketchnum=$((sketchnum + 1))
+    done
+    return $sketchnum
+}
+
+function build_sketches { # build_sketches <ide_path> <user_path> <target> <path> <chunk> <total-chunks> [extra-options]
+    local args=()
+    while [ -n "$1" ]; do
+        case $1 in
+        -ai )
+            shift
+            ide_path=$1
+            ;;
+        -au )
+            shift
+            user_path=$1
+            ;;
+        -t )
+            shift
+            target=$1
+            args+=("-t" "$target")
+            ;;
+        -fqbn )
+            shift
+            fqbn=$1
+            args+=("-fqbn" "$fqbn")
+            ;;
+        -p )
+            shift
+            path=$1
+            ;;
+        -i )
+            shift
+            chunk_index=$1
+            ;;
+        -m )
+            shift
+            chunk_max=$1
+            ;;
+        -l )
+            shift
+            log_compilation=$1
+            ;;
+        -f )
+            shift
+            sketches_file=$1
+            ;;
+        -d )
+            shift
+            debug_level="$1"
+            args+=("-d" "$debug_level")
+            ;;
+        * )
+            break
+            ;;
+        esac
+        shift
+    done
+
+    local xtra_opts=("$@")
+
+    if [ -z "$chunk_index" ] || [ -z "$chunk_max" ]; then
+        echo "ERROR: Invalid chunk parameters"
+        echo "$USAGE"
+        exit 1
+    fi
+
+    if [ "$chunk_max" -le 0 ]; then
+        echo "ERROR: Chunks count must be positive number"
+        return 1
+    fi
+
+    if [ "$chunk_index" -gt "$chunk_max" ] && [ "$chunk_max" -ge 2 ]; then
+        chunk_index=$chunk_max
+    fi
+
+    set +e
+    if [ -n "$sketches_file" ]; then
+        count_sketches "$path" "$target" "0" "$sketches_file"
+        local sketchcount=$?
+    else
+        count_sketches "$path" "$target"
+        local sketchcount=$?
+    fi
+    set -e
+    local sketches
+    sketches=$(cat sketches.txt)
+    rm -rf sketches.txt
+
+    local chunk_size
+    local all_chunks
+    chunk_size=$(( sketchcount / chunk_max ))
+    all_chunks=$(( chunk_max * chunk_size ))
+    if [ "$all_chunks" -lt "$sketchcount" ]; then
+        chunk_size=$(( chunk_size + 1 ))
+    fi
+
+    local start_index=0
+    local end_index=0
+    if [ "$chunk_index" -ge "$chunk_max" ]; then
+        start_index=$chunk_index
+        end_index=$sketchcount
+    else
+        start_index=$(( chunk_index * chunk_size ))
+        if [ "$sketchcount" -le "$start_index" ]; then
+            echo "No sketches to build for $target in this chunk"
+            return 0
+        fi
+
+        end_index=$(( $(( chunk_index + 1 )) * chunk_size ))
+        if [ "$end_index" -gt "$sketchcount" ]; then
+            end_index=$sketchcount
+        fi
+    fi
+
+    local start_num
+    start_num=$(( start_index + 1 ))
+    echo "Found $sketchcount Sketches for target '$target'";
+    echo "Chunk Index : $chunk_index"
+    echo "Chunk Count : $chunk_max"
+    echo "Chunk Size  : $chunk_size"
+    echo "Start Sketch: $start_num"
+    echo "End Sketch  : $end_index"
+
+    #if fqbn is not passed then set it to default for compilation log
+    if [ -z "$fqbn" ]; then
+        log_fqbn="espressif:esp32:$target"
+    else
+        log_fqbn=$fqbn
+    fi
+
+    sizes_file="$GITHUB_WORKSPACE/cli_compile_$chunk_index.json"
+    if [ -n "$log_compilation" ]; then
+        #echo board,target and start of sketches to sizes_file json
+        echo "{ \"board\": \"$log_fqbn\",
+                \"target\": \"$target\",
+                \"sketches\": [" >> "$sizes_file"
+    fi
+
+    local sketchnum=0
+    args+=("-ai" "$ide_path" "-au" "$user_path" "-i" "$chunk_index")
+    if [ -n "$log_compilation" ]; then
+        args+=("-l" "$log_compilation")
+    fi
+    for sketch in $sketches; do
+        local sketchdir
+        local sketchdirname
+
+        sketchdir=$(dirname "$sketch")
+        sketchdirname=$(basename "$sketchdir")
+        sketchnum=$((sketchnum + 1))
+
+        if [ "$sketchnum" -le "$start_index" ] \
+        || [ "$sketchnum" -gt "$end_index" ]; then
+            continue
+        fi
+        echo ""
+        echo "Building Sketch Index $sketchnum - $sketchdirname"
+        build_sketch "${args[@]}" -s "$sketchdir" "${xtra_opts[@]}"
+        local result=$?
+        if [ $result -ne 0 ]; then
+            return $result
+        fi
+    done
+
+    if [ -n "$log_compilation" ]; then
+        #remove last comma from json
+        if [ "$i" -eq $((len - 1)) ]; then
+            sed -i '$ s/.$//' "$sizes_file"
+        fi
+        #echo end of sketches sizes_file json
+        echo "]" >> "$sizes_file"
+        #echo end of board sizes_file json
+        echo "}," >> "$sizes_file"
+    fi
+
+    return 0
+}
+
+USAGE="
+USAGE: ${0} [command] [options]
+Available commands:
+    count: Count sketches.
+    build: Build a sketch.
+    chunk_build: Build a chunk of sketches.
+    check_requirements: Check if target meets sketch requirements.
+"
+
+cmd=$1
+shift
+if [ -z "$cmd" ]; then
+    echo "ERROR: No command supplied"
+    echo "$USAGE"
+    exit 2
+fi
+
+case "$cmd" in
+    "count") count_sketches "$@"
+    ;;
+    "build") build_sketch "$@"
+    ;;
+    "chunk_build") build_sketches "$@"
+    ;;
+    "check_requirements") check_requirements "$@"
+    ;;
+    *)
+        echo "ERROR: Unrecognized command"
+        echo "$USAGE"
+        exit 2
+esac
diff --git a/.github/scripts/tests_build.sh b/.github/scripts/tests_build.sh
new file mode 100755
index 00000000000..93342c83299
--- /dev/null
+++ b/.github/scripts/tests_build.sh
@@ -0,0 +1,80 @@
+#!/bin/bash
+
+USAGE="
+USAGE:
+    ${0} -c -type <test_type> <chunk_build_opts>
+        Example: ${0} -c -type validation -t esp32 -i 0 -m 15
+    ${0} -s sketch_name <build_opts>
+        Example: ${0} -s hello_world -t esp32
+    ${0} -clean
+        Remove build and test generated files
+"
+
+function clean {
+    rm -rf tests/.pytest_cache
+    find tests/ -type d -name 'build*' -exec rm -rf "{}" \+
+    find tests/ -type d -name '__pycache__' -exec rm -rf "{}" \+
+    find tests/ -name '*.xml' -exec rm -rf "{}" \+
+    find tests/ -name 'result_*.json' -exec rm -rf "{}" \+
+}
+
+SCRIPTS_DIR="./.github/scripts"
+BUILD_CMD=""
+
+chunk_build=0
+
+while [ -n "$1" ]; do
+    case $1 in
+    -c )
+        chunk_build=1
+        ;;
+    -s )
+        shift
+        sketch=$1
+        ;;
+    -h )
+        echo "$USAGE"
+        exit 0
+        ;;
+    -type )
+        shift
+        test_type=$1
+        ;;
+    -clean )
+        clean
+        exit 0
+        ;;
+    * )
+        break
+        ;;
+    esac
+    shift
+done
+
+source "${SCRIPTS_DIR}/install-arduino-cli.sh"
+source "${SCRIPTS_DIR}/install-arduino-core-esp32.sh"
+
+args=("-ai" "$ARDUINO_IDE_PATH" "-au" "$ARDUINO_USR_PATH")
+
+if [[ $test_type == "all" ]] || [[ -z $test_type ]]; then
+    if [ -n "$sketch" ]; then
+        tmp_sketch_path=$(find tests -name "$sketch".ino)
+        test_type=$(basename "$(dirname "$(dirname "$tmp_sketch_path")")")
+        echo "Sketch $sketch test type: $test_type"
+        test_folder="$PWD/tests/$test_type"
+    else
+        test_folder="$PWD/tests"
+    fi
+else
+    test_folder="$PWD/tests/$test_type"
+fi
+
+if [ $chunk_build -eq 1 ]; then
+    BUILD_CMD="${SCRIPTS_DIR}/sketch_utils.sh chunk_build"
+    args+=("-p" "$test_folder" "-i" "0" "-m" "1")
+else
+    BUILD_CMD="${SCRIPTS_DIR}/sketch_utils.sh build"
+    args+=("-s" "$test_folder/$sketch")
+fi
+
+${BUILD_CMD} "${args[@]}" "$@"
diff --git a/.github/scripts/tests_matrix.sh b/.github/scripts/tests_matrix.sh
new file mode 100644
index 00000000000..a8baf2ce275
--- /dev/null
+++ b/.github/scripts/tests_matrix.sh
@@ -0,0 +1,28 @@
+#!/bin/bash
+
+build_types="'validation'"
+hw_types="'validation'"
+wokwi_types="'validation'"
+qemu_types="'validation'"
+
+if [[ $IS_PR != 'true' ]] || [[ $PERFORMANCE_ENABLED == 'true' ]]; then
+    build_types+=",'performance'"
+    hw_types+=",'performance'"
+    #wokwi_types+=",'performance'"
+    #qemu_types+=",'performance'"
+fi
+
+targets="'esp32','esp32s2','esp32s3','esp32c3','esp32c6','esp32h2','esp32p4'"
+
+mkdir -p info
+
+echo "[$wokwi_types]" > info/wokwi_types.txt
+echo "[$targets]" > info/targets.txt
+
+{
+    echo "build-types=[$build_types]"
+    echo "hw-types=[$hw_types]"
+    echo "wokwi-types=[$wokwi_types]"
+    echo "qemu-types=[$qemu_types]"
+    echo "targets=[$targets]"
+} >> "$GITHUB_OUTPUT"
diff --git a/.github/scripts/tests_run.sh b/.github/scripts/tests_run.sh
new file mode 100755
index 00000000000..1c4bee79742
--- /dev/null
+++ b/.github/scripts/tests_run.sh
@@ -0,0 +1,290 @@
+#!/bin/bash
+
+function run_test {
+    local target=$1
+    local sketch=$2
+    local options=$3
+    local erase_flash=$4
+    local sketchdir
+    local sketchname
+    local result=0
+    local error=0
+    local sdkconfig_path
+    local extra_args
+    local test_type
+
+    sketchdir=$(dirname "$sketch")
+    sketchname=$(basename "$sketchdir")
+    test_type=$(basename "$(dirname "$sketchdir")")
+
+    if [ "$options" -eq 0 ] && [ -f "$sketchdir"/ci.json ]; then
+        len=$(jq -r --arg target "$target" '.fqbn[$target] | length' "$sketchdir"/ci.json)
+        if [ "$len" -eq 0 ]; then
+            len=1
+        fi
+    else
+        len=1
+    fi
+
+    if [ "$len" -eq 1 ]; then
+        sdkconfig_path="$HOME/.arduino/tests/$target/$sketchname/build.tmp/sdkconfig"
+    else
+        sdkconfig_path="$HOME/.arduino/tests/$target/$sketchname/build0.tmp/sdkconfig"
+    fi
+
+    if [ -f "$sketchdir"/ci.json ]; then
+        # If the target or platform is listed as false, skip the sketch. Otherwise, include it.
+        is_target=$(jq -r --arg target "$target" '.targets[$target]' "$sketchdir"/ci.json)
+        selected_platform=$(jq -r --arg platform "$platform" '.platforms[$platform]' "$sketchdir"/ci.json)
+
+        if [[ $is_target == "false" ]] || [[ $selected_platform == "false" ]]; then
+            printf "\033[93mSkipping %s test for %s, platform: %s\033[0m\n" "$sketchname" "$target" "$platform"
+            printf "\n\n\n"
+            return 0
+        fi
+    fi
+
+    if [ ! -f "$sdkconfig_path" ]; then
+        printf "\033[93mSketch %s build not found in %s\nMight be due to missing target requirements or build failure\033[0m\n" "$(dirname "$sdkconfig_path")" "$sketchname"
+        printf "\n\n\n"
+        return 0
+    fi
+
+    local compiled_target
+    compiled_target=$(grep -E "CONFIG_IDF_TARGET=" "$sdkconfig_path" | cut -d'"' -f2)
+    if [ "$compiled_target" != "$target" ]; then
+        printf "\033[91mError: Sketch %s compiled for %s, expected %s\033[0m\n" "$sketchname" "$compiled_target" "$target"
+        printf "\n\n\n"
+        return 1
+    fi
+
+    if [ "$len" -eq 1 ]; then
+        # build_dir="$sketchdir/build"
+        build_dir="$HOME/.arduino/tests/$target/$sketchname/build.tmp"
+        report_file="$sketchdir/$target/$sketchname.xml"
+    fi
+
+    for i in $(seq 0 $((len - 1))); do
+        fqbn="Default"
+
+        if [ "$len" -ne 1 ]; then
+            fqbn=$(jq -r --arg target "$target" --argjson i "$i" '.fqbn[$target] | sort | .[$i]' "$sketchdir"/ci.json)
+        elif [ -f "$sketchdir"/ci.json ]; then
+            has_fqbn=$(jq -r --arg target "$target" '.fqbn[$target]' "$sketchdir"/ci.json)
+            if [ "$has_fqbn" != "null" ]; then
+                fqbn=$(jq -r --arg target "$target" '.fqbn[$target] | .[0]' "$sketchdir"/ci.json)
+            fi
+        fi
+
+        printf "\033[95mRunning test: %s -- Config: %s\033[0m\n" "$sketchname" "$fqbn"
+        if [ "$erase_flash" -eq 1 ]; then
+            esptool.py -c "$target" erase_flash
+        fi
+
+        if [ "$len" -ne 1 ]; then
+            # build_dir="$sketchdir/build$i"
+            build_dir="$HOME/.arduino/tests/$target/$sketchname/build$i.tmp"
+            report_file="$sketchdir/$target/$sketchname$i.xml"
+        fi
+
+        if [ $platform == "wokwi" ]; then
+            extra_args=("--target" "$target" "--embedded-services" "arduino,wokwi" "--wokwi-timeout=$wokwi_timeout")
+            if [[ -f "$sketchdir/scenario.yaml" ]]; then
+                extra_args+=("--wokwi-scenario" "$sketchdir/scenario.yaml")
+            fi
+            if [[ -f "$sketchdir/diagram.$target.json" ]]; then
+                extra_args+=("--wokwi-diagram" "$sketchdir/diagram.$target.json")
+            fi
+
+        elif [ $platform == "qemu" ]; then
+            PATH=$HOME/qemu/bin:$PATH
+            extra_args=("--embedded-services" "qemu" "--qemu-image-path" "$build_dir/$sketchname.ino.merged.bin")
+
+            if [ "$target" == "esp32" ] || [ "$target" == "esp32s3" ]; then
+                extra_args+=("--qemu-prog-path" "qemu-system-xtensa" "--qemu-cli-args=\"-machine $target -m 4M -nographic\"")
+            elif [ "$target" == "esp32c3" ]; then
+                extra_args+=("--qemu-prog-path" "qemu-system-riscv32" "--qemu-cli-args=\"-machine $target -icount 3 -nographic\"")
+            else
+                printf "\033[91mUnsupported QEMU target: %s\033[0m\n" "$target"
+                exit 1
+            fi
+        else
+            extra_args=("--embedded-services" "esp,arduino")
+        fi
+
+        rm "$sketchdir"/diagram.json 2>/dev/null || true
+
+        result=0
+        printf "\033[95mpytest \"%s/test_%s.py\" --build-dir \"%s\" --junit-xml=\"%s\" -o junit_suite_name=%s_%s_%s_%s%s %s\033[0m\n" "$sketchdir" "$sketchname" "$build_dir" "$report_file" "$test_type" "$platform" "$target" "$sketchname" "$i" "${extra_args[*]@Q}"
+        bash -c "set +e; pytest \"$sketchdir/test_$sketchname.py\" --build-dir \"$build_dir\" --junit-xml=\"$report_file\" -o junit_suite_name=${test_type}_${platform}_${target}_${sketchname}${i} ${extra_args[*]@Q}; exit \$?" || result=$?
+        printf "\n"
+        if [ $result -ne 0 ]; then
+            result=0
+            printf "\033[95mRetrying test: %s -- Config: %s\033[0m\n" "$sketchname" "$i"
+            printf "\033[95mpytest \"%s/test_%s.py\" --build-dir \"%s\" --junit-xml=\"%s\" -o junit_suite_name=%s_%s_%s_%s%s %s\033[0m\n" "$sketchdir" "$sketchname" "$build_dir" "$report_file" "$test_type" "$platform" "$target" "$sketchname" "$i" "${extra_args[*]@Q}"
+            bash -c "set +e; pytest \"$sketchdir/test_$sketchname.py\" --build-dir \"$build_dir\" --junit-xml=\"$report_file\" -o junit_suite_name=${test_type}_${platform}_${target}_${sketchname}${i} ${extra_args[*]@Q}; exit \$?" || result=$?
+            printf "\n"
+            if [ $result -ne 0 ]; then
+                printf "\033[91mFailed test: %s -- Config: %s\033[0m\n\n" "$sketchname" "$i"
+                error=$result
+            fi
+        fi
+    done
+    return $error
+}
+
+SCRIPTS_DIR="./.github/scripts"
+COUNT_SKETCHES="${SCRIPTS_DIR}/sketch_utils.sh count"
+
+platform="hardware"
+wokwi_timeout=60000
+chunk_run=0
+options=0
+erase=0
+
+while [ -n "$1" ]; do
+    case $1 in
+    -c )
+        chunk_run=1
+        ;;
+    -Q )
+        if [ ! -d "$QEMU_PATH" ]; then
+            echo "QEMU path $QEMU_PATH does not exist"
+            exit 1
+        fi
+        platform="qemu"
+        ;;
+    -W )
+        shift
+        wokwi_timeout=$1
+        if [[ -z $WOKWI_CLI_TOKEN ]]; then
+            echo "Wokwi CLI token is not set"
+            exit 1
+        fi
+        platform="wokwi"
+        ;;
+    -o )
+        options=1
+        ;;
+    -s )
+        shift
+        sketch=$1
+        ;;
+    -t )
+        shift
+        target=$1
+        ;;
+    -i )
+        shift
+        chunk_index=$1
+        ;;
+    -m )
+        shift
+        chunk_max=$1
+        ;;
+    -e )
+        erase=1
+        ;;
+    -h )
+        echo "$USAGE"
+        exit 0
+        ;;
+    -type )
+        shift
+        test_type=$1
+        ;;
+    * )
+        break
+        ;;
+    esac
+    shift
+done
+
+if [ ! $platform == "qemu" ]; then
+    source "${SCRIPTS_DIR}/install-arduino-ide.sh"
+fi
+
+# If sketch is provided and test type is not, test type is inferred from the sketch path
+if [[ $test_type == "all" ]] || [[ -z $test_type ]]; then
+    if [ -n "$sketch" ]; then
+        tmp_sketch_path=$(find tests -name "$sketch".ino)
+        test_type=$(basename "$(dirname "$(dirname "$tmp_sketch_path")")")
+        echo "Sketch $sketch test type: $test_type"
+        test_folder="$PWD/tests/$test_type"
+    else
+        test_folder="$PWD/tests"
+    fi
+else
+    test_folder="$PWD/tests/$test_type"
+fi
+
+if [ $chunk_run -eq 0 ]; then
+    if [ -z "$sketch" ]; then
+        echo "ERROR: Sketch name is required for single test run"
+        exit 1
+    fi
+    run_test "$target" "$test_folder"/"$sketch"/"$sketch".ino $options $erase
+    exit $?
+else
+    if [ "$chunk_max" -le 0 ]; then
+        echo "ERROR: Chunks count must be positive number"
+        exit 1
+    fi
+
+    if [ "$chunk_index" -ge "$chunk_max" ] && [ "$chunk_max" -ge 2 ]; then
+        echo "ERROR: Chunk index must be less than chunks count"
+        exit 1
+    fi
+
+    set +e
+    # Ignore requirements as we don't have the libs. The requirements will be checked in the run_test function
+    ${COUNT_SKETCHES} "$test_folder" "$target" "1"
+    sketchcount=$?
+    set -e
+    sketches=$(cat sketches.txt)
+    rm -rf sketches.txt
+
+    chunk_size=$(( sketchcount / chunk_max ))
+    all_chunks=$(( chunk_max * chunk_size ))
+    if [ "$all_chunks" -lt "$sketchcount" ]; then
+        chunk_size=$(( chunk_size + 1 ))
+    fi
+
+    start_index=0
+    end_index=0
+    if [ "$chunk_index" -ge "$chunk_max" ]; then
+        start_index=$chunk_index
+        end_index=$sketchcount
+    else
+        start_index=$(( chunk_index * chunk_size ))
+        if [ "$sketchcount" -le "$start_index" ]; then
+            exit 0
+        fi
+
+        end_index=$(( $(( chunk_index + 1 )) * chunk_size ))
+        if [ "$end_index" -gt "$sketchcount" ]; then
+            end_index=$sketchcount
+        fi
+    fi
+
+    sketchnum=0
+    error=0
+
+    for sketch in $sketches; do
+
+        sketchnum=$((sketchnum + 1))
+        if [ "$sketchnum" -le "$start_index" ] \
+        || [ "$sketchnum" -gt "$end_index" ]; then
+            continue
+        fi
+
+        printf "\033[95mSketch Index %s\033[0m\n" "$((sketchnum - 1))"
+
+        exit_code=0
+        run_test "$target" "$sketch" $options $erase || exit_code=$?
+        if [ $exit_code -ne 0 ]; then
+            error=$exit_code
+        fi
+    done
+    exit $error
+fi
diff --git a/.github/scripts/update-version.sh b/.github/scripts/update-version.sh
new file mode 100755
index 00000000000..9a38b27a57a
--- /dev/null
+++ b/.github/scripts/update-version.sh
@@ -0,0 +1,48 @@
+#!/bin/bash
+# shellcheck disable=SC2002
+
+# For reference: add tools for all boards by replacing one line in each board
+# "[board].upload.tool=esptool_py" to "[board].upload.tool=esptool_py\n[board].upload.tool.default=esptool_py\n[board].upload.tool.network=esp_ota"
+#cat boards.txt | sed "s/\([a-zA-Z0-9_\-]*\)\.upload\.tool\=esptool_py/\1\.upload\.tool\=esptool_py\\n\1\.upload\.tool\.default\=esptool_py\\n\1\.upload\.tool\.network\=esp_ota/"
+
+if [ ! $# -eq 3 ]; then
+    echo "Bad number of arguments: $#" >&2
+    echo "usage: $0 <major> <minor> <patch>" >&2
+    exit 1
+fi
+
+re='^[0-9]+$'
+if [[ ! $1 =~ $re ]] || [[ ! $2 =~ $re ]] || [[ ! $3 =~ $re ]] ; then
+    echo "error: Not a valid version: $1.$2.$3" >&2
+    echo "usage: $0 <major> <minor> <patch>" >&2
+    exit 1
+fi
+
+ESP_ARDUINO_VERSION_MAJOR="$1"
+ESP_ARDUINO_VERSION_MINOR="$2"
+ESP_ARDUINO_VERSION_PATCH="$3"
+ESP_ARDUINO_VERSION="$ESP_ARDUINO_VERSION_MAJOR.$ESP_ARDUINO_VERSION_MINOR.$ESP_ARDUINO_VERSION_PATCH"
+
+echo "New Arduino Version: $ESP_ARDUINO_VERSION"
+
+echo "Updating platform.txt..."
+cat platform.txt | sed "s/version=.*/version=$ESP_ARDUINO_VERSION/g" > __platform.txt && mv __platform.txt platform.txt
+
+echo "Updating package.json..."
+cat package.json | sed "s/.*\"version\":.*/  \"version\": \"$ESP_ARDUINO_VERSION\",/g" > __package.json && mv __package.json package.json
+
+echo "Updating cores/esp32/esp_arduino_version.h..."
+cat cores/esp32/esp_arduino_version.h | \
+sed "s/#define ESP_ARDUINO_VERSION_MAJOR.*/#define ESP_ARDUINO_VERSION_MAJOR $ESP_ARDUINO_VERSION_MAJOR/g" | \
+sed "s/#define ESP_ARDUINO_VERSION_MINOR.*/#define ESP_ARDUINO_VERSION_MINOR $ESP_ARDUINO_VERSION_MINOR/g" | \
+sed "s/#define ESP_ARDUINO_VERSION_PATCH.*/#define ESP_ARDUINO_VERSION_PATCH $ESP_ARDUINO_VERSION_PATCH/g" > __esp_arduino_version.h && mv __esp_arduino_version.h cores/esp32/esp_arduino_version.h
+
+libraries=$(find libraries -maxdepth 1 -mindepth 1 -type d -exec basename {} \;)
+for lib in $libraries; do
+    if [ -f "libraries/$lib/library.properties" ]; then
+        echo "Updating Library $lib..."
+        cat "libraries/$lib/library.properties" | sed "s/version=.*/version=$ESP_ARDUINO_VERSION/g" > "libraries/$lib/__library.properties" && mv "libraries/$lib/__library.properties" "libraries/$lib/library.properties"
+    fi
+done
+
+exit 0
diff --git a/.github/scripts/upload_py_tools.sh b/.github/scripts/upload_py_tools.sh
new file mode 100755
index 00000000000..abe18a50c6e
--- /dev/null
+++ b/.github/scripts/upload_py_tools.sh
@@ -0,0 +1,12 @@
+#!/bin/bash
+
+CHANGED_FILES=$1
+echo "Pushing '$CHANGED_FILES' as github-actions[bot]"
+git config --global github.user "github-actions[bot]"
+git config --global user.name "github-actions[bot]"
+git config --global user.email "41898282+github-actions[bot]@users.noreply.github.com"
+for tool in $CHANGED_FILES; do
+    git add tools/"$tool".exe
+done
+git commit -m "change(tools): Push generated binaries to PR"
+git push
diff --git a/.github/stale.yml b/.github/stale.yml
deleted file mode 100644
index e969fcba5b1..00000000000
--- a/.github/stale.yml
+++ /dev/null
@@ -1,64 +0,0 @@
-# Configuration for probot-stale - https://github.com/probot/stale
-
-# Number of days of inactivity before an Issue or Pull Request becomes stale
-daysUntilStale: 60
-
-# Number of days of inactivity before an Issue or Pull Request with the stale label is closed.
-# Set to false to disable. If disabled, issues still need to be closed manually, but will remain marked as stale.
-daysUntilClose: 14
-
-# Only issues or pull requests with all of these labels are check if stale. Defaults to `[]` (disabled)
-onlyLabels: []
-
-# Issues or Pull Requests with these labels will never be considered stale. Set to `[]` to disable
-exemptLabels:
-  - pinned
-  - security
-  - "to be implemented"
-  - "for reference"
-  - "move to PR"
-  - "enhancement"
-
-# Set to true to ignore issues in a project (defaults to false)
-exemptProjects: false
-
-# Set to true to ignore issues in a milestone (defaults to false)
-exemptMilestones: false
-
-# Set to true to ignore issues with an assignee (defaults to false)
-exemptAssignees: false
-
-# Label to use when marking as stale
-staleLabel: stale
-
-# Comment to post when marking as stale. Set to `false` to disable
-markComment: >
-  [STALE_SET] This issue has been automatically marked as stale because it has not had
-  recent activity. It will be closed in 14 days if no further activity occurs. Thank you
-  for your contributions.
-
-# Comment to post when removing the stale label.
-unmarkComment: >
-  [STALE_CLR] This issue has been removed from the stale queue. Please ensure activity to keep it openin the future.
-
-# Comment to post when closing a stale Issue or Pull Request.
-closeComment: >
-  [STALE_DEL] This stale issue has been automatically closed. Thank you for your contributions.
-
-# Limit the number of actions per hour, from 1-30. Default is 30
-limitPerRun: 30
-
-# Limit to only `issues` or `pulls`
-only: issues
-
-# Optionally, specify configuration settings that are specific to just 'issues' or 'pulls':
-# pulls:
-#   daysUntilStale: 30
-#   markComment: >
-#     This pull request has been automatically marked as stale because it has not had
-#     recent activity. It will be closed if no further activity occurs. Thank you
-#     for your contributions.
-
-# issues:
-#   exemptLabels:
-#     - confirmed
diff --git a/.github/workflows/allboards.yml b/.github/workflows/allboards.yml
new file mode 100644
index 00000000000..6910ad05d3f
--- /dev/null
+++ b/.github/workflows/allboards.yml
@@ -0,0 +1,88 @@
+name: Boards Test - Remote trigger
+
+# The workflow will run on remote dispatch with event-type set to "test-boards"
+on:
+  repository_dispatch:
+    types: [test-boards]
+
+jobs:
+  find-boards:
+    runs-on: ubuntu-latest
+
+    outputs:
+      fqbns: ${{ env.FQBNS }}
+      board-count: ${{ env.BOARD-COUNT }}
+
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: ${{ github.event.client_payload.branch }}
+
+      - name: Get boards fqbns
+        run: bash .github/scripts/find_all_boards.sh
+
+  setup-chunks:
+    needs: find-boards
+    runs-on: ubuntu-latest
+    if: needs.find-boards.outputs.fqbns != ''
+
+    outputs:
+      test-chunks: ${{ steps['set-test-chunks'].outputs['test-chunks'] }}
+
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: ${{ github.event.client_payload.branch }}
+
+      - run: npm install
+      - name: Setup jq
+        uses: dcarbone/install-jq-action@e397bd87438d72198f81efd21f876461183d383a # v3.0.1
+
+      - id: set-test-chunks
+        name: Set Chunks
+        run: echo "test-chunks<<EOF" >> $GITHUB_OUTPUT
+
+          echo "$( jq -nc '${{ needs.find-boards.outputs.fqbns }} | [_nwise( ${{ needs.find-boards.outputs.board-count }}/15 | ceil)]')" >> $GITHUB_OUTPUT
+
+          echo "EOF" >> $GITHUB_OUTPUT
+
+  test-boards:
+    needs: setup-chunks
+    runs-on: ubuntu-latest
+
+    env:
+      REPOSITORY: |
+        - source-path: '.'
+          name: "espressif:esp32"
+
+    strategy:
+      fail-fast: false
+      matrix:
+        chunk: ${{ fromJSON(needs.setup-chunks.outputs['test-chunks']) }}
+
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: ${{ github.event.client_payload.branch }}
+
+      - name: Echo FQBNS to file
+        run: echo "$FQBN" > fqbns.json
+        env:
+          FQBN: ${{ toJSON(matrix.chunk) }}
+
+      - name: Compile sketch
+        uses: P-R-O-C-H-Y/compile-sketches@a62f069b92dc8f5053da4ac439ea6d1950cf6379 # main
+        with:
+          platforms: |
+            ${{ env.REPOSITORY }}
+          multiple-fqbn: true
+          multiple-fqbn-path: "fqbns.json"
+          use-json-file: false
+          enable-deltas-report: false
+          enable-warnings-report: false
+          cli-compile-flags: |
+            - --warnings="all"
+          sketch-paths: "- ./libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino"
diff --git a/.github/workflows/boards.yml b/.github/workflows/boards.yml
new file mode 100644
index 00000000000..287e97219c4
--- /dev/null
+++ b/.github/workflows/boards.yml
@@ -0,0 +1,88 @@
+name: Boards Test
+
+# The workflow will run on schedule and labeled pull requests
+on:
+  pull_request:
+    paths:
+      - "boards.txt"
+      - "libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino"
+      - ".github/workflows/boards.yml"
+
+env:
+  # It's convenient to set variables for values used multiple times in the workflow
+  GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+
+jobs:
+  find-boards:
+    runs-on: ubuntu-latest
+
+    outputs:
+      fqbns: ${{ env.FQBNS }}
+
+    steps:
+      # This step makes the contents of the repository available to the workflow
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+      - name: Setup jq
+        uses: dcarbone/install-jq-action@e397bd87438d72198f81efd21f876461183d383a # v3.0.1
+
+      - name: Get board name
+        run: bash .github/scripts/find_new_boards.sh ${{ github.repository }} ${{github.base_ref}}
+
+  test-boards:
+    needs: find-boards
+    runs-on: ubuntu-latest
+    if: needs.find-boards.outputs.fqbns != ''
+
+    env:
+      REPOSITORY: |
+        - source-path: '.'
+          name: "espressif:esp32"
+
+    strategy:
+      fail-fast: false
+      matrix: ${{ fromJson(needs.find-boards.outputs.fqbns) }}
+
+    steps:
+      # This step makes the contents of the repository available to the workflow
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+      - name: Check if build.board is uppercase
+        run: |
+          board_name=$(echo ${{ matrix.fqbn }} | awk -F':' '{print $NF}')
+          if grep -q "^$board_name.build.board=[A-Z0-9_]*$" boards.txt; then
+            echo "$board_name.build.board is valid.";
+          else
+            echo "Error: $board_name.build.board is not uppercase!";
+            exit 1;
+          fi
+
+      - name: Get libs cache
+        uses: actions/cache@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        with:
+          key: libs-${{ runner.os }}-${{ runner.arch }}-${{ hashFiles('package/package_esp32_index.template.json', 'tools/get.py') }}
+          path: |
+            ./tools/dist
+            ./tools/esp32-arduino-libs
+            ./tools/esptool
+            ./tools/mk*
+            ./tools/openocd-esp32
+            ./tools/riscv32-*
+            ./tools/xtensa-*
+
+      - name: Compile sketch
+        uses: P-R-O-C-H-Y/compile-sketches@a62f069b92dc8f5053da4ac439ea6d1950cf6379 # main
+        with:
+          platforms: |
+            ${{ env.REPOSITORY }}
+          fqbn: ${{ matrix.fqbn }}
+          use-json-file: false
+          enable-deltas-report: false
+          enable-warnings-report: false
+          cli-compile-flags: |
+            - --warnings="all"
+          exit-on-fail: true
+          sketch-paths: "- ./libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino"
+          verbose: true
diff --git a/.github/workflows/build_py_tools.yml b/.github/workflows/build_py_tools.yml
new file mode 100644
index 00000000000..bbb36589c84
--- /dev/null
+++ b/.github/workflows/build_py_tools.yml
@@ -0,0 +1,151 @@
+name: Build Python Tools
+
+on:
+  pull_request:
+    paths:
+      - ".github/workflows/build_py_tools.yml"
+      - "tools/get.py"
+      - "tools/espota.py"
+      - "tools/gen_esp32part.py"
+      - "tools/gen_insights_package.py"
+
+jobs:
+  find-changed-tools:
+    name: Check if tools have been changed
+    runs-on: ubuntu-latest
+    outputs:
+      any_changed: ${{ steps.verify-changed-files.outputs.any_changed }}
+      all_changed_files: ${{ steps.verify-changed-files.outputs.all_changed_files }}
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          fetch-depth: 2
+          ref: ${{ github.event.pull_request.head.ref }}
+
+      - name: Check if checkout failed
+        if: failure()
+        run: |
+          echo "Checkout failed."
+          echo "Make sure you are using a branch inside the repository and not a fork."
+
+      - name: Verify Python Tools Changed
+        uses: tj-actions/changed-files@2f7c5bfce28377bc069a65ba478de0a74aa0ca32 # v46.0.1
+        id: verify-changed-files
+        with:
+          fetch_depth: "2"
+          since_last_remote_commit: "true"
+          files: |
+            tools/get.py
+            tools/espota.py
+            tools/gen_esp32part.py
+            tools/gen_insights_package.py
+
+      - name: List all changed files
+        shell: bash
+        run: |
+          for file in ${{ steps.verify-changed-files.outputs.all_changed_files }}; do
+            echo "$file was changed"
+          done
+
+  build-pytools-binaries:
+    name: Build python tools binaries for ${{ matrix.os }}
+    runs-on: ${{ matrix.os }}
+    needs: find-changed-tools
+    if: needs.find-changed-tools.outputs.any_changed == 'true'
+    strategy:
+      fail-fast: false
+      matrix:
+        os: [windows-latest, macos-latest, ubuntu-latest, ubuntu-24.04-arm]
+        include:
+          - os: windows-latest
+            TARGET: win64
+            EXTEN: .exe
+            SEPARATOR: ";"
+          - os: macos-latest
+            TARGET: macos
+            SEPARATOR: ":"
+          - os: ubuntu-latest
+            TARGET: linux-amd64
+            SEPARATOR: ":"
+          - os: ubuntu-24.04-arm
+            TARGET: arm
+            SEPARATOR: ":"
+    env:
+      DISTPATH: pytools-${{ matrix.TARGET }}
+      PIP_EXTRA_INDEX_URL: "https://dl.espressif.com/pypi"
+    steps:
+      - name: List changed tools
+        shell: bash
+        run: |
+          CHANGED_FILES=()
+          for file in ${{ needs.find-changed-tools.outputs.all_changed_files }}; do
+              file="${file#*\/}"
+              file="${file%\.*}"
+              CHANGED_FILES+=("$file")
+          done
+          CHANGED_FILES="${CHANGED_FILES[@]}"
+          echo "CHANGED_TOOLS=$CHANGED_FILES" >> "$GITHUB_ENV"
+          for tool in ${{ env.CHANGED_TOOLS }}; do
+            echo "tool $tool was changed"
+          done
+
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          token: ${{ secrets.TOOLS_UPLOAD_PAT }}
+          ref: ${{ github.event.pull_request.head.ref }}
+
+      - name: Set up Python 3.8
+        uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+        with:
+          python-version: 3.8
+
+      - name: Install dependencies
+        run: |
+          python -m pip install --upgrade pip
+          pip install pyinstaller requests
+
+      - name: Build with PyInstaller
+        shell: bash
+        run: |
+          for tool in ${{ env.CHANGED_TOOLS }}; do
+            pyinstaller --distpath ./${{ env.DISTPATH }} -F --icon=.github/pytools/espressif.ico tools/$tool.py
+          done
+
+      - name: Sign binaries
+        if: matrix.os == 'windows-latest'
+        env:
+          CERTIFICATE: ${{ secrets.CERTIFICATE }}
+          CERTIFICATE_PASSWORD: ${{ secrets.CERTIFICATE_PASSWORD }}
+        shell: pwsh
+        run: |
+          $data = Write-Output ${{ env.CHANGED_TOOLS }}
+          foreach ( $node in $data )
+          {
+            ./.github/pytools/Sign-File.ps1 -Path ./${{ env.DISTPATH }}/$node.exe
+          }
+
+      - name: Test binaries
+        shell: bash
+        run: |
+          for tool in ${{ env.CHANGED_TOOLS }}; do
+            ./${{ env.DISTPATH }}/$tool${{ matrix.EXTEN }} -h
+          done
+
+      - name: Push binary to tools
+        if: matrix.os == 'windows-latest'
+        env:
+          GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+        shell: bash
+        run: |
+          for tool in ${{ env.CHANGED_TOOLS }}; do
+            cp -f ./${{ env.DISTPATH }}/$tool.exe tools/$tool.exe
+          done
+          bash .github/scripts/upload_py_tools.sh "${{ env.CHANGED_TOOLS }}"
+
+      - name: Archive artifact
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: ${{ env.DISTPATH }}
+          path: ${{ env.DISTPATH }}
diff --git a/.github/workflows/dangerjs.yml b/.github/workflows/dangerjs.yml
new file mode 100644
index 00000000000..13bc907566b
--- /dev/null
+++ b/.github/workflows/dangerjs.yml
@@ -0,0 +1,27 @@
+name: DangerJS Pull Request linter
+on:
+  pull_request_target:
+    types: [opened, edited, reopened, synchronize]
+
+permissions:
+  pull-requests: write
+  contents: write
+
+jobs:
+  pull-request-style-linter:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check out PR head
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: ${{ github.event.pull_request.head.sha }}
+
+      - name: DangerJS pull request linter
+        uses: espressif/shared-github-dangerjs@fb17367fd3e8ff7412603b8e946d9b19ffdb2d7f # v1
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          instructions-cla-link: "https://cla-assistant.io/espressif/arduino-esp32"
+          instructions-contributions-file: "docs/en/contributing.rst"
+          rule-max-commits: "false"
+          commit-messages-min-summary-length: "10"
diff --git a/.github/workflows/docs_build.yml b/.github/workflows/docs_build.yml
new file mode 100644
index 00000000000..d9b9f160228
--- /dev/null
+++ b/.github/workflows/docs_build.yml
@@ -0,0 +1,48 @@
+name: Documentation Build and Deploy CI
+
+on:
+  push:
+    branches:
+      - master
+      - release/v2.x
+    paths:
+      - "docs/**"
+      - ".github/workflows/docs_build.yml"
+  pull_request:
+    paths:
+      - "docs/**"
+      - ".github/workflows/docs_build.yml"
+
+jobs:
+  build-docs:
+    name: Build ESP-Docs
+    runs-on: ubuntu-22.04
+    defaults:
+      run:
+        shell: bash
+    steps:
+      - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          submodules: true
+
+      - uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+        with:
+          cache-dependency-path: docs/requirements.txt
+          cache: "pip"
+          python-version: "3.10"
+
+      - name: Build
+        run: |
+          sudo apt update
+          sudo apt install python3-pip python3-setuptools
+          # GitHub CI installs pip3 and setuptools outside the path.
+          # Update the path to include them and run.
+          cd ./docs
+          PATH=/home/runner/.local/bin:$PATH pip3 install -r requirements.txt --prefer-binary
+          PATH=/home/runner/.local/bin:$PATH SPHINXOPTS="-W" build-docs -l en
+
+      - name: Archive Docs
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: docs
+          path: docs
diff --git a/.github/workflows/docs_deploy.yml b/.github/workflows/docs_deploy.yml
new file mode 100644
index 00000000000..9f45e35aef8
--- /dev/null
+++ b/.github/workflows/docs_deploy.yml
@@ -0,0 +1,62 @@
+name: Documentation Build and Production Deploy CI
+
+on:
+  workflow_run:
+    workflows: ["ESP32 Arduino Release"]
+    types:
+      - completed
+  push:
+    branches:
+      - release/v2.x
+      - master
+    paths:
+      - "docs/**"
+      - ".github/workflows/docs_deploy.yml"
+
+jobs:
+  deploy-prod-docs:
+    name: Deploy Documentation on Production
+    runs-on: ubuntu-22.04
+    defaults:
+      run:
+        shell: bash
+    steps:
+      - name: Check if release workflow is successful
+        if: ${{ github.event_name == 'workflow_run' && github.event.workflow_run.conclusion != 'success' }}
+        run: |
+          echo "Release workflow failed. Exiting..."
+          exit 1
+
+      - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          submodules: true
+
+      - uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+        with:
+          cache-dependency-path: docs/requirements.txt
+          cache: "pip"
+          python-version: "3.10"
+
+      - name: Deploy Documentation
+        env:
+          # Deploy to production server
+          # DOCS_BUILD_DIR: "./docs/_build/"
+          DOCS_DEPLOY_PRIVATEKEY: ${{ secrets.DOCS_KEY }}
+          DOCS_DEPLOY_PATH: ${{ secrets.DOCS_PATH }}
+          DOCS_DEPLOY_SERVER: ${{ secrets.DOCS_SERVER }}
+          DOCS_DEPLOY_SERVER_USER: ${{ secrets.DOCS_USER }}
+          DOCS_DEPLOY_URL_BASE: ${{ secrets.DOCS_URL }}
+        run: |
+          sudo apt update
+          sudo apt install python3-pip python3-setuptools
+          source ./docs/utils.sh
+          add_doc_server_ssh_keys $DOCS_DEPLOY_PRIVATEKEY $DOCS_DEPLOY_SERVER $DOCS_DEPLOY_SERVER_USER
+          export GIT_VER=$(git describe --always)
+          echo "PIP install requirements..."
+          pip3 install --user -r ./docs/requirements.txt
+          echo "Building the Docs..."
+          cd ./docs && build-docs -l en
+          echo "Deploy the Docs..."
+          export DOCS_BUILD_DIR=$GITHUB_WORKSPACE/docs/
+          cd $GITHUB_WORKSPACE/docs
+          deploy-docs
diff --git a/.github/workflows/gh-pages.yml b/.github/workflows/gh-pages.yml
index f111f3aa254..60795229eff 100644
--- a/.github/workflows/gh-pages.yml
+++ b/.github/workflows/gh-pages.yml
@@ -3,19 +3,22 @@ name: GitHub Pages CI
 on:
   push:
     branches:
-    - master
+      - master
+      - pages
     paths:
-    - 'README.md'
-    - 'docs/**'
+      - "README.md"
+      - ".github/scripts/on-pages.sh"
+      - ".github/workflows/gh-pages.yml"
 
 jobs:
-
   build-pages:
     name: Build GitHub Pages
     runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v1
-    - name: Copy Files
-      env:
-        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-      run: bash ./.github/scripts/on-pages.sh
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+      - name: Copy Files
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        run: bash ./.github/scripts/on-pages.sh
diff --git a/.github/workflows/lib.json b/.github/workflows/lib.json
new file mode 100644
index 00000000000..5b93d6689ef
--- /dev/null
+++ b/.github/workflows/lib.json
@@ -0,0 +1,110 @@
+[
+    {
+        "name": "Adafruit NeoPixel",
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/Adafruit_NeoPixel/examples/strandtest/strandtest.ino"
+        ]
+    },
+    {
+        "name": "ArduinoBLE",
+        "exclude_targets": [
+            "esp32s2"
+        ],
+        "sketch_path": [
+            "~/Arduino/libraries/ArduinoBLE/examples/Central/Scan/Scan.ino"
+        ]
+    },
+    {
+        "name": "ESP32Servo",
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/ESP32Servo/examples/Multiple-Servo-Example-Arduino/Multiple-Servo-Example-Arduino.ino"
+        ]
+    },
+    {
+        "source-url": "https://github.com/ESP32Async/ESPAsyncWebServer.git",
+        "required-libs": [
+            {"source-url": "https://github.com/ESP32Async/AsyncTCP.git"}
+        ],
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Auth/Auth.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/CORS/CORS.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/CaptivePortal/CaptivePortal.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/CatchAllHandler/CatchAllHandler.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/ChunkResponse/ChunkResponse.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/ChunkRetryResponse/ChunkRetryResponse.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/EndBegin/EndBegin.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Filters/Filters.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/FlashResponse/FlashResponse.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/HeaderManipulation/HeaderManipulation.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Headers/Headers.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Json/Json.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Logging/Logging.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/MessagePack/MessagePack.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Middleware/Middleware.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Params/Params.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/PartitionDownloader/PartitionDownloader.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/PerfTests/PerfTests.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/RateLimit/RateLimit.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Redirect/Redirect.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/RequestContinuation/RequestContinuation.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/RequestContinuationComplete/RequestContinuationComplete.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/ResumableDownload/ResumableDownload.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Rewrite/Rewrite.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/ServerSentEvents/ServerSentEvents.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/ServerState/ServerState.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/SkipServerMiddleware/SkipServerMiddleware.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/SlowChunkResponse/SlowChunkResponse.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/StaticFile/StaticFile.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Templates/Templates.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/Upload/Upload.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/WebSocket/WebSocket.ino"
+        ]
+    },
+    {
+        "name": "EthernetESP32",
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/EthernetESP32/examples/LegacyEthernetTest/LegacyEthernetTest.ino",
+            "~/Arduino/libraries/EthernetESP32/examples/TwoEthernets/TwoEthernets.ino"
+        ]
+    },
+    {
+        "name": "FastLED",
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/FastLED/examples/Blink/Blink.ino"
+        ]
+    },
+    {
+        "name": "IRremote",
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/IRremote/examples/SendDemo/SendDemo.ino"
+        ]
+    },
+    {
+        "name": "MFRC522",
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/MFRC522/examples/ReadUidMultiReader/ReadUidMultiReader.ino"
+        ]
+    },
+    {
+        "name": "WS2812FX",
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/WS2812FX/examples/ws2812fx_spi/ws2812fx_spi.ino"
+        ]
+    },
+    {
+        "name": "ZACwire for TSic",
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/ZACwire_for_TSic/examples/ReadingTwoTSICs/ReadingTwoTSICs.ino",
+            "~/Arduino/libraries/ZACwire_for_TSic/examples/ReadSingleTSIC206/ReadSingleTSIC206.ino"
+        ]
+    }
+]
diff --git a/.github/workflows/lib.yml b/.github/workflows/lib.yml
new file mode 100644
index 00000000000..0cb50842e5d
--- /dev/null
+++ b/.github/workflows/lib.yml
@@ -0,0 +1,145 @@
+name: External Libraries Test
+
+# The workflow will run on schedule and labeled pull requests
+on:
+  pull_request:
+    types: [opened, reopened, synchronize, labeled]
+
+  # Schedule weekly builds on every Sunday at 4 am
+  schedule:
+    - cron: "0 4 * * SUN"
+
+concurrency:
+  group: libs-${{ github.event.pull_request.number || github.ref }}
+  cancel-in-progress: true
+
+env:
+  # It's convenient to set variables for values used multiple times in the workflow
+  SKETCHES_REPORTS_PATH: libraries-report
+  SKETCHES_REPORTS_ARTIFACT_NAME: libraries-report
+  RESULT_LIBRARY_TEST_FILE: LIBRARIES_TEST.md
+  JSON_LIBRARY_LIST_FILE: .github/workflows/lib.json
+  GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+
+jobs:
+  compile-sketch:
+    if: |
+      contains(github.event.pull_request.labels.*.name, 'lib_test') ||
+      (github.event_name == 'schedule' && github.repository == 'espressif/arduino-esp32')
+    runs-on: ubuntu-latest
+    env:
+      REPOSITORY: |
+        - source-path: '.'
+          name: "espressif:esp32"
+
+    strategy:
+      matrix:
+        target:
+          - esp32
+          - esp32s2
+          - esp32c3
+          - esp32s3
+          - esp32c6
+          - esp32h2
+          - esp32p4
+
+        include:
+          - target: esp32
+            fqbn: espressif:esp32:esp32
+          - target: esp32s2
+            fqbn: espressif:esp32:esp32s2
+          - target: esp32c3
+            fqbn: espressif:esp32:esp32c3
+          - target: esp32s3
+            fqbn: espressif:esp32:esp32s3
+          - target: esp32c6
+            fqbn: espressif:esp32:esp32c6
+          - target: esp32h2
+            fqbn: espressif:esp32:esp32h2
+          - target: esp32p4
+            fqbn: espressif:esp32:esp32p4
+
+    steps:
+      # This step makes the contents of the repository available to the workflow
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+      - name: Compile sketch
+        uses: P-R-O-C-H-Y/compile-sketches@a62f069b92dc8f5053da4ac439ea6d1950cf6379 # main
+        with:
+          platforms: |
+            ${{ env.REPOSITORY }}
+          target: ${{ matrix.target }}
+          fqbn: ${{ matrix.fqbn }}
+          use-json-file: true
+          json-path: ${{ env.JSON_LIBRARY_LIST_FILE }}
+          enable-deltas-report: true
+          sketches-report-path: ${{ env.SKETCHES_REPORTS_PATH }}
+          enable-warnings-report: true
+          cli-compile-flags: |
+            - --warnings="all"
+
+      - name: Upload artifact
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: ${{ env.SKETCHES_REPORTS_ARTIFACT_NAME }}-${{ matrix.target }}
+          path: ${{ env.SKETCHES_REPORTS_PATH }}
+
+  report-to-file:
+    needs: compile-sketch # Wait for the compile job to finish to get the data for the report
+    if: github.event_name == 'schedule' # Only run the job when the workflow is triggered by a schedule
+    runs-on: ubuntu-latest
+    steps:
+      # Check out repository
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          token: ${{ env.GITHUB_TOKEN }}
+          fetch-depth: "0"
+
+      - name: Switch branch
+        run: git checkout remotes/origin/gh-pages
+
+      # This step is needed to get the size data produced by the compile jobs
+      - name: Download sketches reports artifact
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        with:
+          pattern: ${{ env.SKETCHES_REPORTS_ARTIFACT_NAME }}-*
+          merge-multiple: true
+          path: ${{ env.SKETCHES_REPORTS_PATH }}
+
+      - name: Report results
+        uses: P-R-O-C-H-Y/report-size-deltas@4a79caa6dcc3579024293638b97156106edc588e # main
+        with:
+          sketches-reports-source: ${{ env.SKETCHES_REPORTS_PATH }}
+          destination-file: ${{ env.RESULT_LIBRARY_TEST_FILE }}
+
+      - name: Append file with action URL
+        run: echo "/ [GitHub Action Link](https://github.com/${{github.repository}}/actions/runs/${{github.run_id}})" >> ${{ env.RESULT_LIBRARY_TEST_FILE }}
+
+      - name: Push to github repo
+        run: |
+          git config user.name "github-actions[bot]"
+          git config user.email "41898282+github-actions[bot]@users.noreply.github.com"
+          git add ${{ env.RESULT_LIBRARY_TEST_FILE }}
+          git commit -m "Generated External Libraries Test Results"
+          git push origin HEAD:gh-pages
+
+  #Upload PR number as artifact
+  upload-pr-number:
+    name: Upload PR number
+    if: (github.event_name == 'pull_request' && contains(github.event.pull_request.labels.*.name, 'lib_test'))
+    runs-on: ubuntu-latest
+    steps:
+      - name: Save the PR number in an artifact
+        shell: bash
+        env:
+          PR_NUM: ${{ github.event.number }}
+        run: echo $PR_NUM > pr_num.txt
+
+      - name: Upload PR number
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: pr_number
+          path: ./pr_num.txt
+          overwrite: true
diff --git a/.github/workflows/pre-commit-status.yml b/.github/workflows/pre-commit-status.yml
new file mode 100644
index 00000000000..c7be9f8d352
--- /dev/null
+++ b/.github/workflows/pre-commit-status.yml
@@ -0,0 +1,64 @@
+# This needs to be in a separate workflow because it requires higher permissions than the calling workflow
+name: Report Pre-commit Check Status
+
+on:
+  workflow_run:
+    workflows: [Pre-commit hooks]
+    types:
+      - completed
+
+permissions:
+  statuses: write
+
+jobs:
+  report-success:
+    name: Report pre-commit success
+    if: github.event.workflow_run.conclusion == 'success'
+    runs-on: ubuntu-latest
+    steps:
+      - name: Report success
+        uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1
+        with:
+          script: |
+            const owner = '${{ github.repository_owner }}';
+            const repo = '${{ github.repository }}'.split('/')[1];
+            const sha = '${{ github.event.workflow_run.head_sha }}';
+            core.debug(`owner: ${owner}`);
+            core.debug(`repo: ${repo}`);
+            core.debug(`sha: ${sha}`);
+            const { context: name, state } = (await github.rest.repos.createCommitStatus({
+              context: 'Pre-commit checks',
+              description: 'Pre-commit checks successful',
+              owner: owner,
+              repo: repo,
+              sha: sha,
+              state: 'success',
+              target_url: 'https://github.com/${{ github.repository }}/actions/runs/${{ github.event.workflow_run.id }}'
+            })).data;
+            core.info(`${name} is ${state}`);
+
+  report-pending:
+    name: Report pre-commit pending
+    if: github.event.workflow_run.conclusion != 'success'
+    runs-on: ubuntu-latest
+    steps:
+      - name: Report pending
+        uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1
+        with:
+          script: |
+            const owner = '${{ github.repository_owner }}';
+            const repo = '${{ github.repository }}'.split('/')[1];
+            const sha = '${{ github.event.workflow_run.head_sha }}';
+            core.debug(`owner: ${owner}`);
+            core.debug(`repo: ${repo}`);
+            core.debug(`sha: ${sha}`);
+            const { context: name, state } = (await github.rest.repos.createCommitStatus({
+              context: 'Pre-commit checks',
+              description: 'The pre-commit checks need to be successful before merging',
+              owner: owner,
+              repo: repo,
+              sha: sha,
+              state: 'pending',
+              target_url: 'https://github.com/${{ github.repository }}/actions/runs/${{ github.event.workflow_run.id }}'
+            })).data;
+            core.info(`${name} is ${state}`);
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
new file mode 100644
index 00000000000..a3b858dd0fb
--- /dev/null
+++ b/.github/workflows/pre-commit.yml
@@ -0,0 +1,80 @@
+name: Pre-commit hooks
+
+on:
+  workflow_dispatch:
+  push:
+    branches:
+      - master
+  pull_request:
+    types: [opened, reopened, synchronize, labeled]
+
+concurrency:
+  group: pre-commit-${{github.event.pull_request.number || github.ref}}
+  cancel-in-progress: true
+
+jobs:
+  lint:
+    if: |
+      github.event_name != 'pull_request' ||
+      contains(github.event.pull_request.labels.*.name, 'Status: Pending Merge') ||
+      contains(github.event.pull_request.labels.*.name, 'Re-trigger Pre-commit Hooks')
+
+    name: Check if fixes are needed
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout latest commit
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          fetch-depth: 2
+
+      - name: Remove Label
+        if: contains(github.event.pull_request.labels.*.name, 'Re-trigger Pre-commit Hooks')
+        run: gh pr edit ${{ github.event.number }} --remove-label 'Re-trigger Pre-commit Hooks'
+        env:
+          GH_TOKEN: ${{ github.token }}
+
+      - name: Set up Python 3
+        uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+        with:
+          cache-dependency-path: tools/pre-commit/requirements.txt
+          cache: "pip"
+          python-version: "3.x"
+
+      - name: Get Python version hash
+        run: |
+          echo "Using $(python -VV)"
+          echo "PY_HASH=$(python -VV | sha256sum | cut -d' ' -f1)" >> $GITHUB_ENV
+
+      - name: Restore pre-commit cache
+        uses: actions/cache/restore@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        id: restore-cache
+        with:
+          path: |
+            ~/.cache/pre-commit
+          key: pre-commit-${{ env.PY_HASH }}-${{ hashFiles('.pre-commit-config.yaml', '.github/workflows/pre-commit.yml', 'tools/pre-commit/requirements.txt') }}
+
+      - name: Install python dependencies
+        run: python -m pip install -r tools/pre-commit/requirements.txt
+
+      - name: Get changed files
+        id: changed-files
+        uses: tj-actions/changed-files@2f7c5bfce28377bc069a65ba478de0a74aa0ca32 # v46.0.1
+
+      - name: Run pre-commit hooks in changed files
+        run: pre-commit run --color=always --show-diff-on-failure --files ${{ steps.changed-files.outputs.all_changed_files }}
+
+      - name: Save pre-commit cache
+        uses: actions/cache/save@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        if: ${{ always() && steps.restore-cache.outputs.cache-hit != 'true' }}
+        continue-on-error: true
+        with:
+          path: |
+            ~/.cache/pre-commit
+          key: ${{ steps.restore-cache.outputs.cache-primary-key }}
+
+      - name: Push changes using pre-commit-ci-lite
+        uses: pre-commit-ci/lite-action@5d6cc0eb514c891a40562a58a8e71576c5c7fb43 # v1.1.0
+        # Only push changes in PRs
+        if: ${{ always() && github.event_name == 'pull_request' }}
+        with:
+          msg: "ci(pre-commit): Apply automatic fixes"
diff --git a/.github/workflows/publishlib.yml b/.github/workflows/publishlib.yml
new file mode 100644
index 00000000000..0e1c3f64afd
--- /dev/null
+++ b/.github/workflows/publishlib.yml
@@ -0,0 +1,56 @@
+name: External Libraries Results
+
+on:
+  workflow_run:
+    workflows: [External Libraries Test]
+    types:
+      - completed
+
+  workflow_dispatch:
+env:
+  # It's convenient to set variables for values used multiple times in the workflow
+  SKETCHES_REPORTS_PATH: artifacts/libraries-report
+  GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+
+jobs:
+  lib-test-results:
+    name: External Libraries Test Results
+    runs-on: ubuntu-latest
+    if: |
+      github.event.workflow_run.event == 'pull_request' &&
+      github.event.workflow_run.conclusion == 'success'
+
+    steps:
+      - name: Download and Extract Artifacts
+        run: |
+          mkdir -p artifacts && cd artifacts
+          mkdir -p libraries-report
+          mkdir -p workflows
+          artifacts_url=${{ github.event.workflow_run.artifacts_url }}
+          gh api "$artifacts_url" -q '.artifacts[] | [.name, .archive_download_url] | @tsv' | while read artifact
+          do
+            IFS=$'\t' read name url <<< "$artifact"
+            gh api $url > "$name.zip"
+            unzip -j "$name.zip" -d "temp_$name"
+            if [[ "$name" == "pr_number" ]]; then
+              mv "temp_$name"/* workflows
+            else
+              mv "temp_$name"/* libraries-report
+            fi
+            rm -r "temp_$name"
+          done
+          echo "Contents of parent directory:"
+          ls -R ..
+
+      - name: Read the pr_num file
+        id: pr_num_reader
+        uses: juliangruber/read-file-action@b549046febe0fe86f8cb4f93c24e284433f9ab58 # v1.1.7
+        with:
+          path: ./artifacts/workflows/pr_num.txt
+
+      - name: Report results
+        uses: P-R-O-C-H-Y/report-size-deltas@256d1f13e4195cd7fd436d2f959e6dc4d5e4b406 # libs
+        with:
+          sketches-reports-source: ${{ env.SKETCHES_REPORTS_PATH }}
+          github-token: ${{ env.GITHUB_TOKEN }}
+          pr-number: "${{ steps.pr_num_reader.outputs.content }}"
diff --git a/.github/workflows/publishsizes-2.x.yml b/.github/workflows/publishsizes-2.x.yml
new file mode 100644
index 00000000000..738e215bc3f
--- /dev/null
+++ b/.github/workflows/publishsizes-2.x.yml
@@ -0,0 +1,52 @@
+name: Sizes Results (master-v2.x)
+
+on:
+  workflow_dispatch:
+
+env:
+  # It's convenient to set variables for values used multiple times in the workflow
+  SKETCHES_REPORTS_PATH: artifacts/sizes-report
+  RESULT_SIZES_TEST_FILE: SIZES_TEST.md
+  GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+
+jobs:
+  sizes-test-results:
+    name: Sizes Comparison Results
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout gh-pages branch
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: gh-pages
+
+      - name: Create folder structure
+        run: |
+          mkdir -p artifacts && cd artifacts
+          mkdir -p sizes-report
+          mkdir -p sizes-report/master
+          mkdir -p sizes-report/pr
+
+      # master folder is a base for comparison
+      # pr folder is for comparison with master
+      - name: Download JSON file
+        run: |
+          mv master_cli_compile/*.json artifacts/sizes-report/pr/
+          mv v2.x_cli_compile/*.json artifacts/sizes-report/master/
+
+      - name: Report results
+        uses: P-R-O-C-H-Y/report-size-deltas@2043188c68f483a7b50527c4eacf609d05bb67a5 # sizes_v2
+        with:
+          sketches-reports-source: ${{ env.SKETCHES_REPORTS_PATH }}
+          github-token: ${{ env.GITHUB_TOKEN }}
+          destination-file: ${{ env.RESULT_SIZES_TEST_FILE }}
+
+      - name: Append file with action URL
+        run: echo "/ [GitHub Action Link](https://github.com/${{github.repository}}/actions/runs/${{github.run_id}})" >> ${{ env.RESULT_SIZES_TEST_FILE }}
+
+      - name: Push to github repo
+        run: |
+          git config user.name "github-actions[bot]"
+          git config user.email "41898282+github-actions[bot]@users.noreply.github.com"
+          git add ${{ env.RESULT_SIZES_TEST_FILE }}
+          git commit -m "Generated Sizes Results (master-v2.x)"
+          git push origin HEAD:gh-pages
diff --git a/.github/workflows/publishsizes.yml b/.github/workflows/publishsizes.yml
new file mode 100644
index 00000000000..69c18cf1835
--- /dev/null
+++ b/.github/workflows/publishsizes.yml
@@ -0,0 +1,72 @@
+name: Sizes Results
+
+on:
+  workflow_run:
+    workflows: [Compilation Tests]
+    types:
+      - completed
+
+  workflow_dispatch:
+env:
+  # It's convenient to set variables for values used multiple times in the workflow
+  SKETCHES_REPORTS_PATH: artifacts/sizes-report
+  GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}
+
+jobs:
+  sizes-test-results:
+    name: Sizes Comparison Results
+    runs-on: ubuntu-latest
+    if: |
+      github.event.workflow_run.event == 'pull_request' &&
+      github.event.workflow_run.conclusion == 'success'
+
+    steps:
+      - name: Checkout gh-pages branch
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: gh-pages
+
+      - name: Create folder structure
+        run: |
+          mkdir -p artifacts && cd artifacts
+          mkdir -p sizes-report
+          mkdir -p sizes-report/master
+          mkdir -p sizes-report/pr
+
+      - name: Download JSON file
+        run: |
+          mv master_cli_compile/*.json artifacts/sizes-report/master/
+
+      - name: Download and Extract Artifacts
+        run: |
+          cd artifacts
+          artifacts_url=${{ github.event.workflow_run.artifacts_url }}
+          gh api "$artifacts_url" -q '.artifacts[] | [.name, .archive_download_url] | @tsv' | while read artifact
+          do
+            IFS=$'\t' read name url <<< "$artifact"
+            gh api $url > "$name.zip"
+            unzip -j "$name.zip" -d "temp_$name"
+            if [[ "$name" == "pr_number" ]]; then
+              mv "temp_$name"/* sizes-report
+            elif [[ "$name" == "pr_cli"* ]]; then
+              mv "temp_$name"/* sizes-report/pr
+            else
+              mv "temp_$name"/* sizes-report
+            fi
+            rm -r "temp_$name"
+          done
+          echo "Contents of parent directory:"
+          ls -R ..
+
+      - name: Read the pr_num file
+        id: pr_num_reader
+        uses: juliangruber/read-file-action@b549046febe0fe86f8cb4f93c24e284433f9ab58 # v1.1.7
+        with:
+          path: ./artifacts/sizes-report/pr_num.txt
+
+      - name: Report results
+        uses: P-R-O-C-H-Y/report-size-deltas@2043188c68f483a7b50527c4eacf609d05bb67a5 # sizes_v2
+        with:
+          sketches-reports-source: ${{ env.SKETCHES_REPORTS_PATH }}
+          github-token: ${{ env.GITHUB_TOKEN }}
+          pr-number: "${{ steps.pr_num_reader.outputs.content }}"
diff --git a/.github/workflows/push.yml b/.github/workflows/push.yml
index e8aec98166c..d98da24fc07 100644
--- a/.github/workflows/push.yml
+++ b/.github/workflows/push.yml
@@ -1,58 +1,334 @@
-name: ESP32 Arduino CI
+name: Compilation Tests
 
 on:
+  workflow_dispatch:
+    inputs:
+      log_level:
+        description: "Log level"
+        default: "none"
+        type: "choice"
+        required: true
+        options:
+          - "none"
+          - "error"
+          - "warn"
+          - "info"
+          - "debug"
+          - "verbose"
+  schedule:
+    # Every Sunday at 2:00 UTC run a build with verbose log level
+    - cron: "0 2 * * SUN"
   push:
     branches:
-    - master
-    - release/*
+      - master
+      - release/*
   pull_request:
+    paths:
+      - "cores/**"
+      - "libraries/**"
+      - "!libraries/**.md"
+      - "!libraries/**.txt"
+      - "!libraries/**.properties"
+      - "!libraries/**.py"
+      - "package/**"
+      - "tools/**.py"
+      - "platform.txt"
+      - "programmers.txt"
+      - "idf_component.yml"
+      - "Kconfig.projbuild"
+      - "package.json"
+      - "CMakeLists.txt"
+      - ".github/workflows/push.yml"
+      - ".github/scripts/**"
+      - "!.github/scripts/find_*"
+      - "!.github/scripts/on-release.sh"
+      - "!.github/scripts/tests_*"
+      - "!.github/scripts/upload_*"
+      - "variants/esp32/**/*"
+      - "variants/esp32c2/**/*"
+      - "variants/esp32c3/**/*"
+      - "variants/esp32c6/**/*"
+      - "variants/esp32h2/**/*"
+      - "variants/esp32p4/**/*"
+      - "variants/esp32s2/**/*"
+      - "variants/esp32s3/**/*"
+
+concurrency:
+  group: build-${{github.event.pull_request.number || github.ref}}
+  cancel-in-progress: true
+
+env:
+  MAX_CHUNKS: 15
 
 jobs:
-  
+  cmake-check:
+    name: Check cmake file
+    runs-on: ubuntu-latest
+    if: ${{ !(github.event_name == 'pull_request' && startsWith(github.head_ref, 'release/')) }}
+    steps:
+      - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+      - run: bash ./.github/scripts/check-cmakelists.sh
+
+  gen-chunks:
+    name: Generate chunks
+    runs-on: ubuntu-latest
+    if: ${{ !(github.event_name == 'pull_request' && startsWith(github.head_ref, 'release/')) }}
+    outputs:
+      build_all: ${{ steps.set-chunks.outputs.build_all }}
+      build_libraries: ${{ steps.set-chunks.outputs.build_libraries }}
+      build_static_sketches: ${{ steps.set-chunks.outputs.build_static_sketches }}
+      build_idf: ${{ steps.set-chunks.outputs.build_idf }}
+      chunk_count: ${{ steps.set-chunks.outputs.chunk_count }}
+      chunks: ${{ steps.set-chunks.outputs.chunks }}
+    steps:
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          fetch-depth: 2
+
+      - name: Get changed files
+        id: changed-files
+        uses: tj-actions/changed-files@2f7c5bfce28377bc069a65ba478de0a74aa0ca32 # v46.0.1
+        with:
+          files_yaml: |
+            core:
+              - '.github/**'
+              - 'cores/**'
+              - 'package/**'
+              - 'tools/**'
+              - 'platform.txt'
+              - 'programmers.txt'
+              - "variants/esp32/**/*"
+              - "variants/esp32c3/**/*"
+              - "variants/esp32c6/**/*"
+              - "variants/esp32h2/**/*"
+              - "variants/esp32p4/**/*"
+              - "variants/esp32s2/**/*"
+              - "variants/esp32s3/**/*"
+            libraries:
+              - 'libraries/**/examples/**'
+              - 'libraries/**/src/**'
+            networking:
+              - 'libraries/Network/src/**'
+            fs:
+              - 'libraries/FS/src/**'
+            static_sketeches:
+              - 'libraries/NetworkClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino'
+              - 'libraries/BLE/examples/Server/Server.ino'
+              - 'libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino'
+              - 'libraries/Insights/examples/MinimalDiagnostics/MinimalDiagnostics.ino'
+              - 'libraries/NetworkClientSecure/src/**'
+              - 'libraries/BLE/src/**'
+              - 'libraries/Insights/src/**'
+            idf:
+              - 'idf_component.yml'
+              - 'Kconfig.projbuild'
+              - 'CMakeLists.txt'
+              - "variants/esp32c2/**/*"
+
+      - name: Set chunks
+        id: set-chunks
+        env:
+          LIB_FILES: ${{ steps.changed-files.outputs.libraries_all_changed_files }}
+          IS_PR: ${{ github.event_name == 'pull_request' }}
+          MAX_CHUNKS: ${{ env.MAX_CHUNKS }}
+          BUILD_IDF: ${{ steps.changed-files.outputs.idf_any_changed == 'true' }}
+          BUILD_LIBRARIES: ${{ steps.changed-files.outputs.libraries_any_changed == 'true' }}
+          BUILD_STATIC_SKETCHES: ${{ steps.changed-files.outputs.static_sketeches_any_changed == 'true' }}
+          FS_CHANGED: ${{ steps.changed-files.outputs.fs_any_changed == 'true' }}
+          NETWORKING_CHANGED: ${{ steps.changed-files.outputs.networking_any_changed == 'true' }}
+          CORE_CHANGED: ${{ steps.changed-files.outputs.core_any_changed == 'true' }}
+          LIB_CHANGED: ${{ steps.changed-files.outputs.libraries_any_changed == 'true' }}
+        run: |
+          bash ./.github/scripts/set_push_chunks.sh
+
+      - name: Upload sketches found
+        if: ${{ steps.set-chunks.outputs.build_all == 'false' && steps.set-chunks.outputs.build_libraries == 'true' }}
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: sketches_found
+          path: sketches_found.txt
+          overwrite: true
+          if-no-files-found: error
+
   # Ubuntu
   build-arduino-linux:
     name: Arduino ${{ matrix.chunk }} on ubuntu-latest
+    if: ${{ needs.gen-chunks.outputs.build_all == 'true' || needs.gen-chunks.outputs.build_libraries == 'true' }}
+    needs: gen-chunks
     runs-on: ubuntu-latest
     strategy:
+      fail-fast: false
       matrix:
-        chunk: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14]
-    
+        chunk: ${{ fromJson(needs.gen-chunks.outputs.chunks) }}
+
     steps:
-    - uses: actions/checkout@v1
-    - uses: actions/setup-python@v1
-      with:
-        python-version: '3.x'
-    - name: Build Sketches
-      run: bash ./.github/scripts/on-push.sh ${{ matrix.chunk }} 15
+      - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+      - uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+        with:
+          python-version: "3.x"
+
+      - name: Get libs cache
+        uses: actions/cache@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        with:
+          key: libs-${{ runner.os }}-${{ runner.arch }}-${{ hashFiles('package/package_esp32_index.template.json', 'tools/get.py') }}
+          path: |
+            ./tools/dist
+            ./tools/esp32-arduino-libs
+            ./tools/esptool
+            ./tools/mk*
+            ./tools/openocd-esp32
+            ./tools/riscv32-*
+            ./tools/xtensa-*
+
+      - name: Set Log Level
+        run: |
+          if [ "${{ github.event_name }}" == "workflow_dispatch" ]; then
+            echo "LOG_LEVEL=${{ github.event.inputs.log_level }}" >> $GITHUB_ENV
+          elif [ "${{ github.event_name }}" == "schedule" ]; then
+            echo "LOG_LEVEL=verbose" >> $GITHUB_ENV
+          else
+            echo "LOG_LEVEL=none" >> $GITHUB_ENV
+          fi
+
+      - name: Build all sketches
+        if: ${{ needs.gen-chunks.outputs.build_all == 'true' }}
+        run: bash ./.github/scripts/on-push.sh ${{ matrix.chunk }} ${{ env.MAX_CHUNKS }} 1 ${{ env.LOG_LEVEL }}
+
+      - name: Download sketches found
+        if: ${{ needs.gen-chunks.outputs.build_all == 'false' && needs.gen-chunks.outputs.build_libraries == 'true' }}
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        with:
+          name: sketches_found
+
+      - name: Build selected sketches
+        if: ${{ needs.gen-chunks.outputs.build_all == 'false' && needs.gen-chunks.outputs.build_libraries == 'true' }}
+        run: bash ./.github/scripts/on-push.sh ${{ matrix.chunk }} ${{ needs.gen-chunks.outputs.chunk_count }} 1 ${{ env.LOG_LEVEL }} sketches_found.txt
+
+      #Upload cli compile json as artifact
+      - name: Upload cli compile json
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: pr_cli_compile_${{ matrix.chunk }}
+          path: cli_compile_${{ matrix.chunk }}.json
+          overwrite: true
 
   # Windows and MacOS
   build-arduino-win-mac:
     name: Arduino on ${{ matrix.os }}
+    needs: gen-chunks
+    if: ${{ needs.gen-chunks.outputs.build_all == 'true' || needs.gen-chunks.outputs.build_static_sketches == 'true' }}
     runs-on: ${{ matrix.os }}
     strategy:
+      fail-fast: false
       matrix:
         os: [windows-latest, macOS-latest]
-    
+
     steps:
-    - uses: actions/checkout@v1
-    - uses: actions/setup-python@v1
-      with:
-        python-version: '3.x'
-    - name: Build Sketches
-      run: bash ./.github/scripts/on-push.sh
-
-  # PlatformIO on Windows, Ubuntu and Mac
-  build-platformio:
-    name: PlatformIO on ${{ matrix.os }}
-    runs-on: ${{ matrix.os }}
+      - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+      - uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+        with:
+          python-version: "3.x"
+      - name: Build Sketches
+        run: bash ./.github/scripts/on-push.sh
+
+  build-esp-idf-component:
+    name: Build with ESP-IDF ${{ matrix.idf_ver }} for ${{ matrix.idf_target }}
+    needs: gen-chunks
+    if: |
+      needs.gen-chunks.outputs.build_all == 'true' ||
+      needs.gen-chunks.outputs.build_libraries == 'true' ||
+      needs.gen-chunks.outputs.build_idf == 'true'
+    runs-on: ubuntu-latest
     strategy:
+      fail-fast: false
       matrix:
-        os: [ubuntu-latest, windows-latest, macOS-latest]
-    
+        # The version names here correspond to the versions of espressif/idf Docker image.
+        # See https://hub.docker.com/r/espressif/idf/tags and
+        # https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/tools/idf-docker-image.html
+        # for details.
+        idf_ver: ["release-v5.4"]
+        idf_target:
+          [
+            "esp32",
+            "esp32s2",
+            "esp32s3",
+            "esp32c2",
+            "esp32c3",
+            "esp32c6",
+            "esp32h2",
+            "esp32p4"
+          ]
+    container: espressif/idf:${{ matrix.idf_ver }}
+    steps:
+      - name: Check out arduino-esp32 as a component
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          submodules: recursive
+          path: components/arduino-esp32
+
+      - name: Build
+        env:
+          IDF_TARGET: ${{ matrix.idf_target }}
+        shell: bash
+        run: |
+          . ${IDF_PATH}/export.sh
+          idf.py create-project test
+          echo CONFIG_FREERTOS_HZ=1000 > test/sdkconfig.defaults
+          idf.py -C test -DEXTRA_COMPONENT_DIRS=$PWD/components build
+
+  # Save artifacts to gh-pages
+  save-master-artifacts:
+    name: Save master artifacts
+    needs: build-arduino-linux
+    if: github.event_name == 'push' && github.ref == 'refs/heads/master'
+    runs-on: ubuntu-latest
     steps:
-    - uses: actions/checkout@v1
-    - uses: actions/setup-python@v1
-      with:
-        python-version: '3.x'
-    - name: Build Sketches
-      run: bash ./.github/scripts/on-push.sh 1 1 #equal and non-zero to trigger PIO
+      # Check out repository
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          token: ${{secrets.GITHUB_TOKEN}}
+          fetch-depth: "0"
+
+      - name: Switch branch
+        run: git checkout remotes/origin/gh-pages
+
+      - name: Download sketches reports artifact
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        with:
+          pattern: pr_cli_compile_*
+          merge-multiple: true
+          path: master_cli_compile
+
+      - name: List files in the directory
+        run: ls -R
+
+      - name: Commit json files to gh-pages if on master
+        if: github.event_name == 'push' && github.ref == 'refs/heads/master'
+        continue-on-error: true
+        run: |
+          git config user.name "github-actions[bot]"
+          git config user.email "41898282+github-actions[bot]@users.noreply.github.com"
+          git add --all
+          git commit -m "Updated cli compile json files"
+          git push origin HEAD:gh-pages
+
+  #Upload PR number as artifact
+  upload-pr-number:
+    name: Upload PR number
+    if: ${{ github.event_name == 'pull_request' && !startsWith(github.head_ref, 'release/') }}
+    runs-on: ubuntu-latest
+    steps:
+      - name: Save the PR number in an artifact
+        shell: bash
+        env:
+          PR_NUM: ${{ github.event.number }}
+        run: echo $PR_NUM > pr_num.txt
+
+      - name: Upload PR number
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: pr_number
+          path: ./pr_num.txt
+          overwrite: true
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml
index 6f63870e81c..7b23c80c49a 100644
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -10,11 +10,23 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-    - uses: actions/checkout@master
-    - uses: actions/setup-python@v1
-      with:
-        python-version: '3.x'
-    - name: Build Release
-      env:
-        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
-      run: bash ./.github/scripts/on-release.sh
+      - name: Checkout repository
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          fetch-depth: 0
+
+      - name: Set up Python
+        uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+        with:
+          python-version: "3.x"
+
+      - name: Install packaging
+        run: pip install packaging
+
+      - name: Install pyserial
+        run: pip install pyserial
+
+      - name: Build Release
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        run: bash ./.github/scripts/on-release.sh
diff --git a/.github/workflows/tests.yml b/.github/workflows/tests.yml
new file mode 100644
index 00000000000..ddc9b64aace
--- /dev/null
+++ b/.github/workflows/tests.yml
@@ -0,0 +1,123 @@
+# This file is used to run the runtime tests for the Arduino core for ESP32.
+# The tests are run on the hardware, Wokwi and QEMU emulators.
+# The QEMU tests are disabled for now as they are redundant with most of the Wokwi tests.
+# As the Wokwi tests require access to secrets, they are run in a separate workflow.
+# We need to ensure that the artifacts from previous tests in the chain are propagated for publishing the results.
+# This is the current trigger sequence for the tests:
+#  tests.yml -> tests_wokwi.yml -> tests_results.yml
+#   ⌙> tests_build.yml
+#   ⌙> tests_hw.yml
+#   ⌙> tests_qemu.yml
+
+name: Runtime Tests
+
+on:
+  workflow_dispatch:
+  pull_request:
+    types: [opened, reopened, closed, synchronize, labeled, unlabeled]
+    paths:
+      - ".github/workflows/tests*"
+      - ".github/scripts/*.sh"
+      - "!.github/scripts/check-cmakelists.sh"
+      - "!.github/scripts/find_*"
+      - "!.github/scripts/on-*.sh"
+      - "!.github/scripts/set_push_chunks.sh"
+      - "!.github/scripts/update-version.sh"
+      - "!.github/scripts/upload_py_tools.sh"
+      - "tests/**"
+      - "cores/**"
+      - "libraries/*/src/**.cpp"
+      - "libraries/*/src/**.h"
+      - "libraries/*/src/**.c"
+      - "package/**"
+  schedule:
+    - cron: "0 2 * * *"
+
+concurrency:
+  group: tests-${{ github.event.pull_request.number || github.ref }}
+  cancel-in-progress: true
+
+jobs:
+  push-event-file:
+    name: Push event file
+    runs-on: ubuntu-latest
+    steps:
+      - name: Upload
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: event_file
+          path: ${{ github.event_path }}
+
+  gen-matrix:
+    name: Generate matrix
+    runs-on: ubuntu-latest
+    outputs:
+      build-types: ${{ steps.set-matrix.outputs.build-types }}
+      hw-types: ${{ steps.set-matrix.outputs.hw-types }}
+      wokwi-types: ${{ steps.set-matrix.outputs.wokwi-types }}
+      qemu-types: ${{ steps.set-matrix.outputs.qemu-types }}
+      targets: ${{ steps.set-matrix.outputs.targets }}
+    env:
+      IS_PR: ${{ github.event.pull_request.number != null }}
+      PERFORMANCE_ENABLED: ${{ contains(github.event.pull_request.labels.*.name, 'perf_test') }}
+    steps:
+      - name: Checkout
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          sparse-checkout: .github/scripts/tests_matrix.sh
+
+      - name: Set matrix
+        id: set-matrix
+        run: bash .github/scripts/tests_matrix.sh
+
+      - name: Upload
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: matrix_info
+          path: info/*
+
+  call-build-tests:
+    name: Build
+    uses: ./.github/workflows/tests_build.yml
+    needs: gen-matrix
+    strategy:
+      matrix:
+        type: ${{ fromJson(needs.gen-matrix.outputs.build-types) }}
+        chip: ${{ fromJson(needs.gen-matrix.outputs.targets) }}
+    with:
+      type: ${{ matrix.type }}
+      chip: ${{ matrix.chip }}
+
+  call-hardware-tests:
+    name: Hardware
+    uses: ./.github/workflows/tests_hw.yml
+    needs: [gen-matrix, call-build-tests]
+    if: |
+      github.repository == 'espressif/arduino-esp32' &&
+      (github.event_name != 'pull_request' ||
+      contains(github.event.pull_request.labels.*.name, 'hil_test'))
+    strategy:
+      fail-fast: false
+      matrix:
+        type: ${{ fromJson(needs.gen-matrix.outputs.hw-types) }}
+        chip: ${{ fromJson(needs.gen-matrix.outputs.targets) }}
+    with:
+      type: ${{ matrix.type }}
+      chip: ${{ matrix.chip }}
+
+  # This job is disabled for now
+  call-qemu-tests:
+    name: QEMU
+    uses: ./.github/workflows/tests_qemu.yml
+    needs: [gen-matrix, call-build-tests]
+    if: false
+    strategy:
+      fail-fast: false
+      matrix:
+        type: ${{ fromJson(needs.gen-matrix.outputs.qemu-types) }}
+        chip: ["esp32", "esp32c3"]
+    with:
+      type: ${{ matrix.type }}
+      chip: ${{ matrix.chip }}
+
+  # Wokwi tests are run after this workflow as it needs access to secrets
diff --git a/.github/workflows/tests_build.yml b/.github/workflows/tests_build.yml
new file mode 100644
index 00000000000..ac1f40644ed
--- /dev/null
+++ b/.github/workflows/tests_build.yml
@@ -0,0 +1,90 @@
+name: Build tests
+
+on:
+  workflow_call:
+    inputs:
+      type:
+        type: string
+        description: "Type of tests to build"
+        required: true
+      chip:
+        type: string
+        description: "Chip to build tests for"
+        required: true
+
+jobs:
+  build-tests:
+    name: Build ${{ inputs.type }} tests for ${{ inputs.chip }}
+    runs-on: ubuntu-latest
+    env:
+      id: ${{ github.event.pull_request.number || github.ref }}-${{ github.event.pull_request.head.sha || github.sha }}-${{ inputs.chip }}-${{ inputs.type }}
+    steps:
+      - name: Check if already built
+        id: cache-build-binaries
+        if: github.event.pull_request.number != null
+        uses: actions/cache/restore@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        with:
+          key: tests-${{ env.id }}-bin
+          path: |
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/*.bin
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/*.elf
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/*.json
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/sdkconfig
+
+      - name: Evaluate if tests should be built
+        id: check-build
+        run: |
+          cache_exists=${{ steps.cache-build-binaries.outputs.cache-hit == 'true' }}
+          enabled=true
+
+          if [[ $cache_exists == 'true' ]]; then
+            echo "Already built, skipping"
+            enabled=false
+          fi
+
+          echo "enabled=$enabled" >> $GITHUB_OUTPUT
+
+      - name: Checkout user repository
+        if: ${{ steps.check-build.outputs.enabled == 'true' }}
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+      - name: Get libs cache
+        uses: actions/cache@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        if: ${{ steps.check-build.outputs.enabled == 'true' }}
+        with:
+          key: libs-${{ runner.os }}-${{ runner.arch }}-${{ hashFiles('package/package_esp32_index.template.json', 'tools/get.py') }}
+          path: |
+            ./tools/dist
+            ./tools/esp32-arduino-libs
+            ./tools/esptool
+            ./tools/mk*
+            ./tools/openocd-esp32
+            ./tools/riscv32-*
+            ./tools/xtensa-*
+
+      - name: Build sketches
+        if: ${{ steps.check-build.outputs.enabled == 'true' }}
+        run: |
+          bash .github/scripts/tests_build.sh -c -type ${{ inputs.type }} -t ${{ inputs.chip }}
+
+      - name: Upload ${{ inputs.chip }} ${{ inputs.type }} binaries as cache
+        uses: actions/cache/save@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        if: steps.check-build.outputs.enabled == 'true' && github.event.pull_request.number != null
+        with:
+          key: tests-${{ env.id }}-bin
+          path: |
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/*.bin
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/*.elf
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/*.json
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/sdkconfig
+
+      - name: Upload ${{ inputs.chip }} ${{ inputs.type }} binaries as artifacts
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: tests-bin-${{ inputs.chip }}-${{ inputs.type }}
+          overwrite: true
+          path: |
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/*.bin
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/*.elf
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/*.json
+            ~/.arduino/tests/${{ inputs.chip }}/**/build*.tmp/sdkconfig
diff --git a/.github/workflows/tests_hw.yml b/.github/workflows/tests_hw.yml
new file mode 100644
index 00000000000..6f5fc67f7b9
--- /dev/null
+++ b/.github/workflows/tests_hw.yml
@@ -0,0 +1,118 @@
+name: Hardware tests
+
+on:
+  workflow_call:
+    inputs:
+      type:
+        type: string
+        description: "Type of tests to run"
+        required: true
+      chip:
+        type: string
+        description: "Chip to run tests for"
+        required: true
+
+env:
+  DEBIAN_FRONTEND: noninteractive
+
+defaults:
+  run:
+    shell: bash
+
+jobs:
+  hardware-test:
+    name: Hardware ${{ inputs.chip }} ${{ inputs.type }} tests
+    runs-on: ["arduino", "${{ inputs.chip }}"]
+    env:
+      id: ${{ github.event.pull_request.number || github.ref }}-${{ github.event.pull_request.head.sha || github.sha }}-${{ inputs.chip }}-${{ inputs.type }}
+    container:
+      image: python:3.10.1-bullseye
+      options: --privileged --device-cgroup-rule="c 188:* rmw" --device-cgroup-rule="c 166:* rmw"
+    steps:
+      - name: Clean workspace
+        run: |
+          rm -rf ./*
+          rm -rf ~/.arduino/tests
+
+      - name: Check if already passed
+        id: cache-results
+        if: github.event.pull_request.number != null
+        uses: actions/cache/restore@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        with:
+          key: tests-${{ env.id }}-results-hw
+          path: |
+            tests/**/*.xml
+            tests/**/result_*.json
+
+      - name: Evaluate if tests should be run
+        id: check-tests
+        run: |
+          cache_exists=${{ steps.cache-results.outputs.cache-hit == 'true' }}
+          enabled=true
+
+          if [[ $cache_exists == 'true' ]]; then
+            echo "Already ran, skipping"
+            enabled=false
+          fi
+
+          echo "enabled=$enabled" >> $GITHUB_OUTPUT
+
+      - name: Checkout user repository
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          sparse-checkout: |
+            *
+
+      # setup-python currently only works on ubuntu images
+      # - uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+      #   if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+      #   with:
+      #     cache-dependency-path: tests/requirements.txt
+      #     cache: 'pip'
+      #     python-version: '3.10.1'
+
+      - name: Install dependencies
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        run: |
+          pip install -U pip
+          pip install -r tests/requirements.txt --extra-index-url https://dl.espressif.com/pypi
+          apt update
+          apt install -y jq
+
+      - name: Get binaries
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        with:
+          name: tests-bin-${{ inputs.chip }}-${{ inputs.type }}
+          path: |
+            ~/.arduino/tests/${{ inputs.chip }}
+
+      - name: List binaries
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        run: |
+          ls -laR ~/.arduino/tests
+
+      - name: Run Tests
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        run: |
+          bash .github/scripts/tests_run.sh -c -type ${{ inputs.type }} -t ${{ inputs.chip }} -i 0 -m 1 -e
+
+      - name: Upload ${{ inputs.chip }} ${{ inputs.type }} hardware results as cache
+        uses: actions/cache/save@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        if: steps.check-tests.outputs.enabled == 'true' && github.event.pull_request.number != null
+        with:
+          key: tests-${{ env.id }}-results-hw
+          path: |
+            tests/**/*.xml
+            tests/**/result_*.json
+
+      - name: Upload ${{ inputs.chip }} ${{ inputs.type }} hardware results as artifacts
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        if: always()
+        with:
+          name: tests-results-hw-${{ inputs.chip }}-${{ inputs.type }}
+          overwrite: true
+          path: |
+            tests/**/*.xml
+            tests/**/result_*.json
diff --git a/.github/workflows/tests_qemu.yml b/.github/workflows/tests_qemu.yml
new file mode 100644
index 00000000000..fa3f874cbbb
--- /dev/null
+++ b/.github/workflows/tests_qemu.yml
@@ -0,0 +1,143 @@
+name: QEMU tests
+
+on:
+  workflow_call:
+    inputs:
+      chip:
+        required: true
+        type: string
+      type:
+        required: true
+        type: string
+
+jobs:
+  qemu-test:
+    name: QEMU ${{ inputs.chip }} ${{ inputs.type }} tests
+    env:
+      id: ${{ github.event.pull_request.number || github.ref }}-${{ github.event.pull_request.head.sha || github.sha }}-${{ inputs.chip }}-${{ inputs.type }}
+      QEMU_INSTALL_PATH: "$HOME"
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check if already passed
+        id: get-cache-results
+        if: github.event.pull_request.number != null
+        uses: actions/cache/restore@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        with:
+          key: tests-${{ env.id }}-results-qemu
+          path: |
+            tests/**/*.xml
+            tests/**/result_*.json
+
+      - name: Evaluate if tests should be run
+        id: check-tests
+        run: |
+          cache_exists=${{ steps.get-cache-results.outputs.cache-hit == 'true' }}
+          enabled=true
+
+          if [[ $cache_exists == 'true' ]]; then
+            echo "Already ran, skipping"
+            enabled=false
+          fi
+
+          echo "enabled=$enabled" >> $GITHUB_OUTPUT
+
+      - name: Checkout user repository
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: ${{ github.event.pull_request.head.sha || github.sha }}
+          persist-credentials: false
+          sparse-checkout-cone-mode: false
+          sparse-checkout: |
+            /*
+            !.github
+
+      # To avoid giving unknown scripts elevated permissions, download them from the master branch
+      - name: Get CI scripts from master
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        run: |
+          mkdir -p .github
+          cd .github
+          curl https://codeload.github.com/${{ github.repository }}/tar.gz/master | tar -xz --strip=2 arduino-esp32-master/.github
+
+      - uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        with:
+          cache-dependency-path: tests/requirements.txt
+          cache: "pip"
+          python-version: "3.x"
+
+      - name: Install Python dependencies
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        run: |
+          pip install -U pip
+          pip install -r tests/requirements.txt --extra-index-url https://dl.espressif.com/pypi
+
+      - name: Install APT dependencies
+        uses: awalsh128/cache-apt-pkgs-action@5902b33ae29014e6ca012c5d8025d4346556bd40 # v1.4.3
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        with:
+          packages: libpixman-1-0 libnuma1 libglib2.0-0 libslirp0 libsdl2-2.0-0
+          version: 1.0
+
+      - name: Get QEMU version
+        uses: pozetroninc/github-action-get-latest-release@2a61c339ea7ef0a336d1daa35ef0cb1418e7676c # v0.8.0
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        id: get-qemu-version
+        with:
+          token: ${{secrets.GITHUB_TOKEN}}
+          owner: espressif
+          repo: qemu
+          excludes: prerelease, draft
+
+      - name: Cache QEMU
+        id: cache-qemu
+        uses: actions/cache@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        with:
+          path: |
+            ~/qemu
+          key: qemu-${{ steps.get-qemu-version.outputs.release }}-${{ hashFiles('.github/workflows/tests_qemu.yml') }}
+
+      - name: Download QEMU
+        if: ${{ steps.cache-qemu.outputs.cache-hit != 'true' && steps.check-tests.outputs.enabled == 'true' }}
+        run: |
+          cd ${{ env.QEMU_INSTALL_PATH }}
+          underscore_release=$(echo ${{ steps.get-qemu-version.outputs.release }} | sed 's/\-/_/g')
+          curl -L https://github.com/espressif/qemu/releases/download/${{ steps.get-qemu-version.outputs.release }}/qemu-riscv32-softmmu-${underscore_release}-x86_64-linux-gnu.tar.xz > qemu-riscv32.tar.xz
+          curl -L https://github.com/espressif/qemu/releases/download/${{ steps.get-qemu-version.outputs.release }}/qemu-xtensa-softmmu-${underscore_release}-x86_64-linux-gnu.tar.xz > qemu-xtensa.tar.xz
+          tar -xf qemu-riscv32.tar.xz
+          tar -xf qemu-xtensa.tar.xz
+          rm qemu-*
+          echo "QEMU_PATH=${{ env.QEMU_INSTALL_PATH }}/qemu" >> $GITHUB_ENV
+
+      - name: Get binaries
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        with:
+          name: tests-bin-${{ inputs.chip }}-${{ inputs.type }}
+          path: |
+            ~/.arduino/tests/${{ inputs.chip }}
+
+      - name: Run Tests
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        run: QEMU_PATH="${{ env.QEMU_INSTALL_PATH }}" bash .github/scripts/tests_run.sh -c -type ${{inputs.type}} -t ${{inputs.chip}} -i 0 -m 1 -Q
+
+      - name: Upload ${{ inputs.chip }} ${{ inputs.type }} QEMU results as cache
+        uses: actions/cache/save@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        if: steps.check-tests.outputs.enabled == 'true' && github.event.pull_request.number != null
+        with:
+          key: tests-${{ env.id }}-results-qemu
+          path: |
+            tests/**/*.xml
+            tests/**/result_*.json
+
+      - name: Upload ${{ inputs.chip }} ${{ inputs.type }} QEMU results as artifacts
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        if: always()
+        with:
+          name: tests-results-qemu-${{ inputs.chip }}-${{ inputs.type }}
+          overwrite: true
+          path: |
+            tests/**/*.xml
+            tests/**/result_*.json
diff --git a/.github/workflows/tests_results.yml b/.github/workflows/tests_results.yml
new file mode 100644
index 00000000000..ebba2a3aa08
--- /dev/null
+++ b/.github/workflows/tests_results.yml
@@ -0,0 +1,195 @@
+name: Publish and clean test results
+
+on:
+  workflow_run:
+    workflows: ["Wokwi tests"]
+    types:
+      - completed
+
+# No permissions by default
+permissions: { contents: read }
+
+jobs:
+  unit-test-results:
+    name: Unit Test Results
+    if: |
+      github.event.workflow_run.conclusion == 'success' ||
+      github.event.workflow_run.conclusion == 'failure' ||
+      github.event.workflow_run.conclusion == 'timed_out'
+    runs-on: ubuntu-latest
+    permissions:
+      actions: write
+      statuses: write
+      checks: write
+      pull-requests: write
+      contents: write
+    steps:
+      - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: gh-pages
+
+      - name: Download and Extract Artifacts
+        uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9
+        with:
+          run_id: ${{ github.event.workflow_run.id }}
+          path: ./artifacts
+
+      - name: Get original info
+        run: |
+          original_event=$(cat ./artifacts/parent-artifacts/event.txt)
+          original_action=$(cat ./artifacts/parent-artifacts/action.txt)
+          original_sha=$(cat ./artifacts/parent-artifacts/sha.txt)
+          original_ref=$(cat ./artifacts/parent-artifacts/ref.txt)
+          original_conclusion=$(cat ./artifacts/parent-artifacts/conclusion.txt)
+          original_run_id=$(cat ./artifacts/parent-artifacts/run_id.txt)
+
+          # Sanitize the values to avoid security issues
+
+          # Event: Allow alphabetical characters and underscores
+          original_event=$(echo "$original_event" | tr -cd '[:alpha:]_')
+
+          # Action: Allow alphabetical characters and underscores
+          original_action=$(echo "$original_action" | tr -cd '[:alpha:]_')
+
+          # SHA: Allow alphanumeric characters
+          original_sha=$(echo "$original_sha" | tr -cd '[:alnum:]')
+
+          # Ref: Allow alphanumeric characters, slashes, underscores, dots, and dashes
+          original_ref=$(echo "$original_ref" | tr -cd '[:alnum:]/_.-')
+
+          # Conclusion: Allow alphabetical characters and underscores
+          original_conclusion=$(echo "$original_conclusion" | tr -cd '[:alpha:]_')
+
+          # Run ID: Allow numeric characters
+          original_run_id=$(echo "$original_run_id" | tr -cd '[:digit:]')
+
+          echo "original_event=$original_event" >> $GITHUB_ENV
+          echo "original_action=$original_action" >> $GITHUB_ENV
+          echo "original_sha=$original_sha" >> $GITHUB_ENV
+          echo "original_ref=$original_ref" >> $GITHUB_ENV
+          echo "original_conclusion=$original_conclusion" >> $GITHUB_ENV
+          echo "original_run_id=$original_run_id" >> $GITHUB_ENV
+
+          echo "original_event = $original_event"
+          echo "original_action = $original_action"
+          echo "original_sha = $original_sha"
+          echo "original_ref = $original_ref"
+          echo "original_conclusion = $original_conclusion"
+          echo "original_run_id = $original_run_id"
+
+      - name: Print links to other runs
+        run: |
+          echo "Build, Hardware and QEMU tests: https://github.com/${{ github.repository }}/actions/runs/${{ env.original_run_id }}"
+          echo "Wokwi tests: https://github.com/${{ github.repository }}/actions/runs/${{ github.event.workflow_run.id }}"
+
+      - name: Publish Unit Test Results
+        uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0
+        with:
+          commit: ${{ env.original_sha }}
+          event_file: ./artifacts/parent-artifacts/event_file/event.json
+          event_name: ${{ env.original_event }}
+          files: ./artifacts/**/*.xml
+          action_fail: true
+          compare_to_earlier_commit: false
+          json_file: ./unity_results.json
+          json_suite_details: true
+
+      - name: Upload JSON
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        if: ${{ always() }}
+        with:
+          name: unity_results
+          overwrite: true
+          path: |
+            ./unity_results.json
+
+      - name: Fail if tests failed
+        if: ${{ env.original_conclusion == 'failure' || env.original_conclusion == 'timed_out' || github.event.workflow_run.conclusion == 'failure' || github.event.workflow_run.conclusion == 'timed_out' }}
+        run: exit 1
+
+      - name: Clean up caches
+        if: always()
+        uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1
+        with:
+          script: |
+            const ref = process.env.original_ref;
+            const key_prefix = 'tests-' + ref + '-';
+
+            if (process.env.original_event == 'pull_request' && process.env.original_action != 'closed') {
+              console.log('Skipping cache cleanup for open PR');
+              return;
+            }
+
+            await github.paginate(github.rest.actions.getActionsCacheList, {
+              owner: context.repo.owner,
+              repo: context.repo.repo,
+              per_page: 100,
+              key: key_prefix
+            }).then(caches => {
+              if (caches) {
+                for (const cache of caches) {
+                  console.log(`Deleting cache: ${cache.key}`);
+                  github.rest.actions.deleteActionsCacheById({
+                    owner: context.repo.owner,
+                    repo: context.repo.repo,
+                    cache_id: cache.id
+                  });
+                }
+              }
+            });
+
+      - name: Report conclusion
+        uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1
+        if: always()
+        with:
+          script: |
+            const owner = '${{ github.repository_owner }}';
+            const repo = '${{ github.repository }}'.split('/')[1];
+            const sha = process.env.original_sha;
+            core.debug(`owner: ${owner}`);
+            core.debug(`repo: ${repo}`);
+            core.debug(`sha: ${sha}`);
+            const { context: name, state } = (await github.rest.repos.createCommitStatus({
+              context: `Runtime Tests / Report results (${process.env.original_event} -> workflow_run -> workflow_run)`,
+              owner: owner,
+              repo: repo,
+              sha: sha,
+              state: '${{ job.status }}',
+              description: '${{ job.status }}' == 'success' ? 'Runtime tests successful' : 'Runtime tests failed',
+              target_url: 'https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }}'
+            })).data;
+            core.info(`${name} is ${state}`);
+
+      - name: Generate report
+        if: ${{ !cancelled() && (env.original_event == 'schedule' || env.original_event == 'workflow_dispatch') }} # codespell:ignore cancelled
+        env:
+          REPORT_FILE: ./runtime-tests-results/RUNTIME_TESTS_REPORT.md
+          WOKWI_RUN_ID: ${{ github.event.workflow_run.id }}
+          BUILD_RUN_ID: ${{ env.original_run_id }}
+          IS_FAILING: ${{ env.original_conclusion == 'failure' || env.original_conclusion == 'timed_out' || github.event.workflow_run.conclusion == 'failure' || github.event.workflow_run.conclusion == 'timed_out' || job.status == 'failure' }}
+        run: |
+          rm -rf artifacts $REPORT_FILE
+          mv -f ./unity_results.json ./runtime-tests-results/unity_results.json
+          touch $REPORT_FILE
+          python3 ./runtime-tests-results/table_generator.py ./runtime-tests-results/unity_results.json >> $REPORT_FILE
+
+      - name: Generate badge
+        if: ${{ !cancelled() && (env.original_event == 'schedule' || env.original_event == 'workflow_dispatch') }} # codespell:ignore cancelled
+        uses: jaywcjlove/generated-badges@0e078ae4d4bab3777ea4f137de496ab44688f5ad # v1.0.13
+        with:
+          label: Runtime Tests
+          status: ${{ job.status == 'success' && 'passing' || 'failing' }}
+          output: runtime-tests-results/badge.svg
+          color: ${{ job.status == 'success' && 'green' || 'red' }}
+          style: flat
+
+      - name: Push badge
+        if: ${{ !cancelled() && (env.original_event == 'schedule' || env.original_event == 'workflow_dispatch') }} # codespell:ignore cancelled
+        run: |
+          git config user.name "github-actions[bot]"
+          git config user.email "41898282+github-actions[bot]@users.noreply.github.com"
+          if [[ `git status --porcelain` ]]; then
+            git add --all
+            git commit -m "Updated runtime tests report"
+            git push origin HEAD:gh-pages
+          fi
diff --git a/.github/workflows/tests_wokwi.yml b/.github/workflows/tests_wokwi.yml
new file mode 100644
index 00000000000..03dd64fc0fb
--- /dev/null
+++ b/.github/workflows/tests_wokwi.yml
@@ -0,0 +1,326 @@
+name: Wokwi tests
+
+on:
+  workflow_run:
+    workflows: ["Runtime Tests"]
+    types:
+      - completed
+
+# No permissions by default
+permissions: { contents: read }
+
+env:
+  WOKWI_TIMEOUT: 600000 # Milliseconds
+
+jobs:
+  get-artifacts:
+    name: Get required artifacts
+    runs-on: ubuntu-latest
+    permissions:
+      actions: read
+      statuses: write
+    outputs:
+      pr_num: ${{ steps.set-ref.outputs.pr_num }}
+      ref: ${{ steps.set-ref.outputs.ref }}
+      base: ${{ steps.set-ref.outputs.base }}
+      targets: ${{ steps.set-ref.outputs.targets }}
+      types: ${{ steps.set-ref.outputs.types }}
+    steps:
+      - name: Report pending
+        uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1
+        with:
+          script: |
+            const owner = '${{ github.repository_owner }}';
+            const repo = '${{ github.repository }}'.split('/')[1];
+            const sha = '${{ github.event.workflow_run.head_sha }}';
+            core.debug(`owner: ${owner}`);
+            core.debug(`repo: ${repo}`);
+            core.debug(`sha: ${sha}`);
+            const { context: name, state } = (await github.rest.repos.createCommitStatus({
+              context: 'Runtime Tests / Wokwi (Get artifacts) (${{ github.event.workflow_run.event }} -> workflow_run)',
+              owner: owner,
+              repo: repo,
+              sha: sha,
+              state: 'pending',
+              target_url: 'https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }}'
+            })).data;
+            core.info(`${name} is ${state}`);
+
+      - name: Download and extract event file
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        with:
+          github-token: ${{ secrets.GITHUB_TOKEN }}
+          run-id: ${{ github.event.workflow_run.id }}
+          name: event_file
+          path: artifacts/event_file
+
+      - name: Download and extract matrix info
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        with:
+          github-token: ${{ secrets.GITHUB_TOKEN }}
+          run-id: ${{ github.event.workflow_run.id }}
+          name: matrix_info
+          path: artifacts/matrix_info
+
+      - name: Try to read PR number
+        id: set-ref
+        run: |
+          pr_num=$(jq -r '.pull_request.number' artifacts/event_file/event.json | tr -cd "[:digit:]")
+          if [ -z "$pr_num" ] || [ "$pr_num" == "null" ]; then
+            pr_num=""
+          fi
+
+          ref=$pr_num
+          if [ -z "$ref" ] || [ "$ref" == "null" ]; then
+            ref=${{ github.ref }}
+          fi
+
+          action=$(jq -r '.action' artifacts/event_file/event.json | tr -cd "[:alpha:]_")
+          if [ "$action" == "null" ]; then
+            action=""
+          fi
+
+          base=$(jq -r '.pull_request.base.ref' artifacts/event_file/event.json | tr -cd "[:alnum:]/_.-")
+          if [ -z "$base" ] || [ "$base" == "null" ]; then
+            base=${{ github.ref }}
+          fi
+
+          types=$(cat artifacts/matrix_info/wokwi_types.txt | tr -cd "[:alpha:],[]'")
+          targets=$(cat artifacts/matrix_info/targets.txt | tr -cd "[:alnum:],[]'")
+
+          echo "base = $base"
+          echo "targets = $targets"
+          echo "types = $types"
+          echo "pr_num = $pr_num"
+
+          printf "$ref" >> artifacts/ref.txt
+          printf "Ref = "
+          cat artifacts/ref.txt
+
+          printf "${{ github.event.workflow_run.event }}" >> artifacts/event.txt
+          printf "\nEvent name = "
+          cat artifacts/event.txt
+
+          printf "${{ github.event.workflow_run.head_sha || github.sha }}" >> artifacts/sha.txt
+          printf "\nHead SHA = "
+          cat artifacts/sha.txt
+
+          printf "$action" >> artifacts/action.txt
+          printf "\nAction = "
+          cat artifacts/action.txt
+
+          printf "${{ github.event.workflow_run.id }}" >> artifacts/run_id.txt
+          printf "\nRun ID = "
+          cat artifacts/run_id.txt
+
+          if [ -z "$ref" ] || [ "$ref" == "null" ]; then
+            echo "Failed to get PR number or ref"
+            exit 1
+          fi
+
+          conclusion="${{ github.event.workflow_run.conclusion }}"
+          printf "$conclusion" >> artifacts/conclusion.txt
+          printf "\nConclusion = "
+          cat artifacts/conclusion.txt
+
+          echo "pr_num=$pr_num" >> $GITHUB_OUTPUT
+          echo "base=$base" >> $GITHUB_OUTPUT
+          echo "targets=$targets" >> $GITHUB_OUTPUT
+          echo "types=$types" >> $GITHUB_OUTPUT
+          echo "ref=$ref" >> $GITHUB_OUTPUT
+
+      - name: Download and extract parent hardware results
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        continue-on-error: true
+        with:
+          github-token: ${{ secrets.GITHUB_TOKEN }}
+          run-id: ${{ github.event.workflow_run.id }}
+          pattern: tests-results-hw-*
+          merge-multiple: true
+          path: artifacts/results/hw
+
+      - name: Download and extract parent QEMU results
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        continue-on-error: true
+        with:
+          github-token: ${{ secrets.GITHUB_TOKEN }}
+          run-id: ${{ github.event.workflow_run.id }}
+          pattern: tests-results-qemu-*
+          merge-multiple: true
+          path: artifacts/results/qemu
+
+      - name: Upload parent artifacts
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: parent-artifacts
+          path: artifacts
+          if-no-files-found: error
+
+      - name: Report conclusion
+        uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1
+        if: always()
+        with:
+          script: |
+            const owner = '${{ github.repository_owner }}';
+            const repo = '${{ github.repository }}'.split('/')[1];
+            const sha = '${{ github.event.workflow_run.head_sha }}';
+            core.debug(`owner: ${owner}`);
+            core.debug(`repo: ${repo}`);
+            core.debug(`sha: ${sha}`);
+            const { context: name, state } = (await github.rest.repos.createCommitStatus({
+              context: 'Runtime Tests / Wokwi (Get artifacts) (${{ github.event.workflow_run.event }} -> workflow_run)',
+              owner: owner,
+              repo: repo,
+              sha: sha,
+              state: '${{ job.status }}',
+              target_url: 'https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }}'
+            })).data;
+            core.info(`${name} is ${state}`);
+
+  wokwi-test:
+    name: Wokwi ${{ matrix.chip }} ${{ matrix.type }} tests
+    if: |
+      github.event.workflow_run.conclusion == 'success' ||
+      github.event.workflow_run.conclusion == 'failure' ||
+      github.event.workflow_run.conclusion == 'timed_out'
+    runs-on: ubuntu-latest
+    needs: get-artifacts
+    env:
+      id: ${{ needs.get-artifacts.outputs.ref }}-${{ github.event.workflow_run.head_sha || github.sha }}-${{ matrix.chip }}-${{ matrix.type }}
+    permissions:
+      actions: read
+      statuses: write
+    strategy:
+      fail-fast: false
+      matrix:
+        type: ${{ fromJson(needs.get-artifacts.outputs.types) }}
+        chip: ${{ fromJson(needs.get-artifacts.outputs.targets) }}
+    steps:
+      - name: Report pending
+        uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1
+        with:
+          script: |
+            const owner = '${{ github.repository_owner }}';
+            const repo = '${{ github.repository }}'.split('/')[1];
+            const sha = '${{ github.event.workflow_run.head_sha }}';
+            core.debug(`owner: ${owner}`);
+            core.debug(`repo: ${repo}`);
+            core.debug(`sha: ${sha}`);
+            const { context: name, state } = (await github.rest.repos.createCommitStatus({
+              context: 'Runtime Tests / Wokwi (${{ matrix.type }}, ${{ matrix.chip }}) / Wokwi ${{ matrix.chip }} ${{ matrix.type }} tests (${{ github.event.workflow_run.event }} -> workflow_run)',
+              owner: owner,
+              repo: repo,
+              sha: sha,
+              state: 'pending',
+              target_url: 'https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }}'
+            })).data;
+            core.info(`${name} is ${state}`);
+
+      - name: Check if already passed
+        id: get-cache-results
+        if: needs.get-artifacts.outputs.pr_num
+        uses: actions/cache/restore@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        with:
+          key: tests-${{ env.id }}-results-wokwi
+          path: |
+            tests/**/*.xml
+            tests/**/result_*.json
+
+      - name: Evaluate if tests should be run
+        id: check-tests
+        run: |
+          cache_exists=${{ steps.get-cache-results.outputs.cache-hit == 'true' }}
+          enabled=true
+
+          if [[ $cache_exists == 'true' ]]; then
+            echo "Already ran, skipping"
+            enabled=false
+          fi
+
+          echo "enabled=$enabled" >> $GITHUB_OUTPUT
+
+      # Note that changes to the workflows and tests will only be picked up after the PR is merged
+      # DO NOT CHECKOUT THE USER'S REPOSITORY IN THIS WORKFLOW. IT HAS HIGH SECURITY RISKS.
+      - name: Checkout repository
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: ${{ needs.get-artifacts.outputs.base || github.ref }}
+
+      - uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.0.4
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        with:
+          cache-dependency-path: tests/requirements.txt
+          cache: "pip"
+          python-version: "3.x"
+
+      - name: Install dependencies
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        run: |
+          pip install -U pip
+          pip install -r tests/requirements.txt --extra-index-url https://dl.espressif.com/pypi
+
+      - name: Install Wokwi CLI
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        run: curl -L https://wokwi.com/ci/install.sh | sh
+
+      - name: Wokwi CI Server
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        uses: wokwi/wokwi-ci-server-action@a6fabb5a49e080158c7a1d121ea5b789536a82c3 # v1
+
+      - name: Get binaries
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
+        with:
+          github-token: ${{ secrets.GITHUB_TOKEN }}
+          run-id: ${{ github.event.workflow_run.id }}
+          name: tests-bin-${{ matrix.chip }}-${{ matrix.type }}
+          path: |
+            ~/.arduino/tests/${{ matrix.chip }}
+
+      - name: Run Tests
+        if: ${{ steps.check-tests.outputs.enabled == 'true' }}
+        env:
+          WOKWI_CLI_TOKEN: ${{ secrets.WOKWI_CLI_TOKEN }}
+        run: |
+          bash .github/scripts/tests_run.sh -c -type ${{ matrix.type }} -t ${{ matrix.chip }} -i 0 -m 1 -W ${{ env.WOKWI_TIMEOUT }}
+
+      - name: Upload ${{ matrix.chip }} ${{ matrix.type }} Wokwi results as cache
+        uses: actions/cache/save@5a3ec84eff668545956fd18022155c47e93e2684 # v4.2.3
+        if: steps.check-tests.outputs.enabled == 'true' && needs.get-artifacts.outputs.pr_num
+        with:
+          key: tests-${{ env.id }}-results-wokwi
+          path: |
+            tests/**/*.xml
+            tests/**/result_*.json
+
+      - name: Upload ${{ matrix.chip }} ${{ matrix.type }} Wokwi results as artifacts
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        if: always()
+        with:
+          name: tests-results-wokwi-${{ matrix.chip }}-${{ matrix.type }}
+          overwrite: true
+          path: |
+            tests/**/*.xml
+            tests/**/result_*.json
+
+      - name: Report conclusion
+        uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1
+        if: always()
+        with:
+          script: |
+            const owner = '${{ github.repository_owner }}';
+            const repo = '${{ github.repository }}'.split('/')[1];
+            const sha = '${{ github.event.workflow_run.head_sha }}';
+            core.debug(`owner: ${owner}`);
+            core.debug(`repo: ${repo}`);
+            core.debug(`sha: ${sha}`);
+            const { context: name, state } = (await github.rest.repos.createCommitStatus({
+              context: 'Runtime Tests / Wokwi (${{ matrix.type }}, ${{ matrix.chip }}) / Wokwi ${{ matrix.chip }} ${{ matrix.type }} tests (${{ github.event.workflow_run.event }} -> workflow_run)',
+              owner: owner,
+              repo: repo,
+              sha: sha,
+              state: '${{ job.status }}',
+              target_url: 'https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }}'
+            })).data;
+            core.info(`${name} is ${state}`);
diff --git a/.github/workflows/upload-idf-component.yml b/.github/workflows/upload-idf-component.yml
new file mode 100644
index 00000000000..687e721fbc2
--- /dev/null
+++ b/.github/workflows/upload-idf-component.yml
@@ -0,0 +1,59 @@
+name: Push components to https://components.espressif.com
+
+on:
+  workflow_dispatch:
+    inputs:
+      tag:
+        description: 'Version to push to the component registry'
+        required: true
+      git_ref:
+        description: 'Git ref with the source to push to the component registry'
+        required: true
+  workflow_run:
+    workflows: ["ESP32 Arduino Release"]
+    types:
+      - completed
+
+permissions:
+  contents: read
+
+jobs:
+  upload_components:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Get the release tag
+        env:
+          head_branch: ${{ inputs.tag || github.event.workflow_run.head_branch }}
+        run: |
+          if [ "${{ github.event.workflow_run.conclusion }}" != "success" ] && [ "${{ github.event_name }}" == "workflow_run" ]; then
+            echo "Release workflow failed. Exiting..."
+            exit 1
+          fi
+
+          # Read and sanitize the branch/tag name
+          branch=$(echo "$head_branch" | tr -cd '[:alnum:]/_.-')
+
+          if [[ $branch == refs/tags/* ]]; then
+            tag="${branch#refs/tags/}"
+          elif [[ $branch =~ ^[0-9]+\.[0-9]+\.[0-9]+.*$ ]]; then
+            tag=$branch
+          else
+            echo "Tag not found in $branch. Exiting..."
+            exit 1
+          fi
+
+          echo "Tag: $tag"
+          echo "RELEASE_TAG=$tag" >> $GITHUB_ENV
+
+      - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: ${{ inputs.git_ref || env.RELEASE_TAG }}
+          submodules: "recursive"
+
+      - name: Upload components to the component registry
+        uses: espressif/upload-components-ci-action@b78a19fa5424714997596d3ecffa634aef8ae20b # v1.0.5
+        with:
+          name: arduino-esp32
+          version: ${{ env.RELEASE_TAG }}
+          namespace: espressif
+          api_token: ${{ secrets.IDF_COMPONENT_API_TOKEN }}
diff --git a/.gitignore b/.gitignore
index e1a9aa2f31b..d254d439834 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,15 +1,57 @@
+tools/esp32-arduino-libs
+tools/xtensa-esp-elf
 tools/xtensa-esp32-elf
+tools/xtensa-esp32s2-elf
+tools/xtensa-esp32s3-elf
+tools/xtensa-esp-elf-gdb
+tools/riscv32-esp-elf
+tools/riscv32-esp-elf-gdb
 tools/dist
 tools/esptool
 tools/esptool.exe
-tools/mkspiffs/mkspiffs
-tools/mkspiffs/mkspiffs.exe
+tools/mkspiffs
+tools/mklittlefs
+tools/mkfatfs.exe
+tools/openocd-esp32
+
+# Ignore editor backup files and macOS system metadata
 .DS_Store
- 
-#Ignore files built by Visual Studio/Visual Micro
-[Dd]ebug*/
-[Rr]elease*/
+.*.swp
+.*.swo
+*~
+
+# Ignore build folder
+/build
+
+# Ignore files built by Visual Studio/Visual Micro
+[Dd]ebug/
+[Rr]elease/
 .vs/
 __vm/
 *.vcxproj*
 .vscode/
+platform.sloeber.txt
+boards.sloeber.txt
+
+# Ignore docs build (Sphinx)
+docs/build
+docs/source/_build
+__pycache__/
+_build/
+
+# Test log files
+*.log
+debug.cfg
+debug.svd
+debug_custom.json
+libraries/Insights/examples/*/*.ino.zip
+
+# Vale Style
+.vale/styles/*
+!.vale/styles/Vocab/
+.vale/styles/Vocab/*
+!.vale/styles/Vocab/Espressif/
+
+# Ignore Lib Builder Docker run scripts
+/run.sh
+/run.ps1
diff --git a/.gitmodules b/.gitmodules
index c9e5e6fd92e..e69de29bb2d 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +0,0 @@
-[submodule "libraries/AzureIoT"]
-	path = libraries/AzureIoT
-	url = https://github.com/VSChina/ESP32_AzureIoT_Arduino
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
new file mode 100644
index 00000000000..0d425c46eae
--- /dev/null
+++ b/.pre-commit-config.yaml
@@ -0,0 +1,110 @@
+exclude: |
+  (?x)(
+      ^\.github\/|
+      ^tests\/performance\/coremark\/.*\.[ch]$|
+      ^tests\/performance\/superpi\/.*\.(cpp|h)$|
+      LICENSE\.md$
+  )
+
+default_language_version:
+  # force all unspecified python hooks to run python3
+  python: python3
+
+repos:
+  - repo: https://github.com/pre-commit/pre-commit-hooks
+    rev: "cef0300fd0fc4d2a87a85fa2093c6b283ea36f4b" # v5.0.0
+    hooks:
+      # Generic checks
+      - id: check-case-conflict
+      - id: check-symlinks
+      - id: debug-statements
+      - id: destroyed-symlinks
+      - id: detect-private-key
+      - id: end-of-file-fixer
+        exclude: ^.*\.(bin|BIN)$
+      - id: mixed-line-ending
+        args: [--fix=lf]
+      - id: trailing-whitespace
+        args: [--markdown-linebreak-ext=md]
+
+      # JSON formatting
+      - id: pretty-format-json
+        stages: [manual]
+        args: [--autofix]
+        types_or: [json]
+        exclude: |
+          (?x)(
+              diagram\..*\.json$|
+              package\.json$|
+              ^package\/.*$
+          )
+
+  - repo: https://github.com/pre-commit/mirrors-clang-format
+    rev: "f6446549e5e97ec9665b9b03e75b87b445857f9a" # v18.1.3
+    hooks:
+      # C/C++ formatting
+      - id: clang-format
+        types_or: [c, c++]
+        exclude: ^.*\/build_opt\.h$
+
+  - repo: https://github.com/psf/black-pre-commit-mirror
+    rev: "a4920527036bb9a3f3e6055d595849d67d0da066" # 25.1.0
+    hooks:
+      # Python formatting
+      - id: black
+        types_or: [python]
+        args: [--line-length=120] #From the arduino code style. Add as argument rather than creating a new config file.
+
+  - repo: https://github.com/PyCQA/flake8
+    rev: "16f5f28a384f0781bebb37a08aa45e65b9526c50" # 7.2.0
+    hooks:
+      # Python linting
+      - id: flake8
+        types_or: [python]
+        additional_dependencies:
+          - flake8-bugbear
+          - flake8-comprehensions
+          - flake8-simplify
+
+  - repo: https://github.com/pre-commit/mirrors-prettier
+    rev: "ffb6a759a979008c0e6dff86e39f4745a2d9eac4" # v3.1.0
+    hooks:
+      # YAML formatting
+      - id: prettier
+        types_or: [yaml]
+
+  - repo: https://github.com/codespell-project/codespell
+    rev: "63c8f8312b7559622c0d82815639671ae42132ac" # v2.4.1
+    hooks:
+      # Spell checking
+      - id: codespell
+        exclude: ^.*\.(svd|SVD)$
+
+  - repo: https://github.com/shellcheck-py/shellcheck-py
+    rev: "a23f6b85d0fdd5bb9d564e2579e678033debbdff" # v0.10.0.1
+    hooks:
+      # Bash linting
+      - id: shellcheck
+        types: [shell]
+
+  - repo: https://github.com/openstack/bashate
+    rev: "fbd7c2534c2701351c603ff700ddf08202430a31" # 2.1.1
+    hooks:
+      # Bash formatting
+      - id: bashate
+        types: [shell]
+        args: ["-i", "E006"] # Ignore E006: Line too long
+
+  - repo: https://github.com/errata-ai/vale
+    rev: "dc4c47923788a413fb5677de6e3370d514aecb78" # v3.11.2
+    hooks:
+      # Sync vale styles and lint markdown and reStructuredText
+      - id: vale
+        name: vale-sync
+        language_version: "1.23.2"
+        pass_filenames: false
+        args: [sync]
+        types_or: [markdown, rst]
+      - id: vale
+        language_version: "1.23.2"
+        types_or: [markdown, rst]
diff --git a/.prettierignore b/.prettierignore
new file mode 100644
index 00000000000..58b8966740f
--- /dev/null
+++ b/.prettierignore
@@ -0,0 +1,4 @@
+__pycache__/
+.clang-format
+.licenses/
+/.git/
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
new file mode 100644
index 00000000000..115b9e7122a
--- /dev/null
+++ b/.readthedocs.yaml
@@ -0,0 +1,20 @@
+# .readthedocs.yaml
+# Read the Docs configuration file
+# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
+
+# Required
+version: 2
+
+# Set the version of Python and other tools you might need
+build:
+  os: ubuntu-22.04
+  tools:
+    python: "3.12"
+
+# Build documentation in the docs/ directory with Sphinx
+sphinx:
+  configuration: docs/source/conf.py
+
+python:
+  install:
+    - requirements: docs/requirements.txt
diff --git a/.shellcheckrc b/.shellcheckrc
new file mode 100644
index 00000000000..a7612e611a2
--- /dev/null
+++ b/.shellcheckrc
@@ -0,0 +1,11 @@
+# Shellcheck configuration file for ESP32 Arduino core
+
+# Optional checks. https://github.com/koalaman/shellcheck/wiki/optional
+enable=add-default-case,deprecate-which,avoid-nullary-conditions
+
+# Enable search for external sources
+external-sources=true
+
+# Search folder for sourced files.
+# Set to the folder where the original script is located.
+source-path=SCRIPTDIR
diff --git a/.travis.yml b/.travis.yml
deleted file mode 100644
index 2fb1dc44dc9..00000000000
--- a/.travis.yml
+++ /dev/null
@@ -1,55 +0,0 @@
-sudo: false
-
-language: python
-
-os:
-  - linux
-
-git:
-  depth: false
-
-before_install:
-  - git submodule update --init --recursive
-
-stages:
-  - build
-  - deploy
-
-jobs:
-  include:
-
-    - name: "Build Arduino 0"
-      if: tag IS blank AND (type = pull_request OR (type = push AND branch = master))
-      stage: build
-      script: $TRAVIS_BUILD_DIR/.github/scripts/on-push.sh 0 10
-
-    - name: "Build Arduino 1"
-      if: tag IS blank AND (type = pull_request OR (type = push AND branch = master))
-      stage: build
-      script: $TRAVIS_BUILD_DIR/.github/scripts/on-push.sh 1 10
-
-    - name: "Build Arduino 2"
-      if: tag IS blank AND (type = pull_request OR (type = push AND branch = master))
-      stage: build
-      script: $TRAVIS_BUILD_DIR/.github/scripts/on-push.sh 2 10
-
-    - name: "Build Arduino 3"
-      if: tag IS blank AND (type = pull_request OR (type = push AND branch = master))
-      stage: build
-      script: $TRAVIS_BUILD_DIR/.github/scripts/on-push.sh 3 10
-
-    - name: "Build PlatformIO"
-      if: tag IS blank AND (type = pull_request OR (type = push AND branch = master))
-      stage: build
-      script: $TRAVIS_BUILD_DIR/.github/scripts/on-push.sh 1 1
-
-notifications:
-  email:
-    on_success: change
-    on_failure: change
-  webhooks:
-    urls:
-        - https://webhooks.gitter.im/e/cb057279c430d91a47a8
-    on_success: change  # options: [always|never|change] default: always
-    on_failure: always  # options: [always|never|change] default: always
-    on_start: never     # options: [always|never|change] default: always
\ No newline at end of file
diff --git a/.vale.ini b/.vale.ini
new file mode 100644
index 00000000000..f04df30f840
--- /dev/null
+++ b/.vale.ini
@@ -0,0 +1,118 @@
+###################
+### Vale Config ###
+###################
+
+# This is a Vale linter configuration file.
+# - Repo: arduino-esp32
+# - Based on Default config: v0-1-1
+# It lists all necessary parameters to configure Vale for your project.
+# For official documentation on all config settings, see
+# https://vale.sh/docs/topics/config
+
+
+##############
+### Global ###
+##############
+
+# This section lists core settings applying to Vale itself.
+
+
+# Specify path to external resources (e.g., styles and vocab files).
+# The path value may be absolute or relative to this configuration file.
+StylesPath = .vale/styles
+
+
+# Specify the minimum alert severity that Vale will report.
+MinAlertLevel = error # "suggestion", "warning", or "error"
+
+
+# Specify vocabulary for special treatment.
+# Create a folder in <StylesPath>/Vocab/<name>/and add its name here
+# The folder should contain two files:
+# - accept.txt -- lists words with accepted case-sensitive spelling
+# - reject.txt -- lists words whose occurrences throw an error
+# Vocab = Espressif
+
+
+# Specify the packages to import into your project.
+# A package is a zip file containing a number of rules (style) written in YAML.
+# For a list of official packages, see Package Hub at https://vale.sh/hub/
+# For official documentation on packages, see
+# https://vale.sh/docs/topics/packages/
+# Before linting, navigate to your project and run `vale sync` to download
+# the official packages specified below.
+# Packages = Package1, Package2, \
+# https://example.com/path/to/package/Package.zip
+Packages = Google, Microsoft, RedHat, \
+https://dl.espressif.com/dl/esp-vale-config/Espressif-latest.zip
+
+
+###############
+### Formats ###
+###############
+
+# This section enables association of "unknown" formats with the ones
+# supported by Vale. For official documentation on supported formats, see
+# https://vale.sh/docs/topics/scoping/
+[formats]
+
+# For example, treat MDX files as Markdown files.
+# mdx = md
+
+
+################################
+### Format-specific settings ###
+################################
+
+# This section lists the settings that apply to specific file formats
+# based on their glob pattern.
+# Settings provided under a more specific glob pattern,
+# such as [*.{md,txt}] will override those in [*].
+[*.{md,rst}]
+
+
+# Enable styles to activate all rules included in them.
+# BasedOnStyles = Style1, Style2
+BasedOnStyles = Vale, Espressif-latest
+
+
+### Deactivate individual rules ###
+### in enabled styles.
+# Style1.Rule1 = NO
+Vale.Repetition = NO
+Vale.Spelling = NO
+Espressif-latest.Admonitions = NO
+Espressif-latest.Contractions = NO
+Espressif-latest.Monospace = NO
+
+
+### Change default severity level ###
+### of an activated rule.
+# Choose between "suggestion", "warning", or "error".
+# Style1.Rule2 = error
+
+
+### Activate individual rules ###
+### in non-enabled styles stored in <StylesPath>.
+# Style1.Rule = YES
+Google.Gender = YES
+Google.GenderBias = YES
+Google.Slang = YES
+Google.Spacing = YES
+Microsoft.DateNumbers = YES
+Microsoft.Ellipses = YES
+Microsoft.FirstPerson = YES
+Microsoft.Hyphens = YES
+Microsoft.Ordinal = YES
+Microsoft.OxfordComma = YES
+Microsoft.Percentages = YES
+Microsoft.RangeTime = YES
+Microsoft.Semicolon = YES
+Microsoft.SentenceLength = YES
+Microsoft.Suspended = YES
+Microsoft.Units = YES
+Microsoft.URLFormat = YES
+Microsoft.We = YES
+Microsoft.Wordiness = YES
+RedHat.Contractions = YES
+RedHat.RepeatedWords = YES
diff --git a/CMakeLists.txt b/CMakeLists.txt
index e7c6ac4fc6b..14fcb19b6da 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,146 +1,310 @@
+# Check ESP-IDF version and error out if it is not in the supported range.
+#
+# Note for arduino-esp32 developers: to bypass the version check locally,
+# set ARDUINO_SKIP_IDF_VERSION_CHECK environment variable to 1. For example:
+#   export ARDUINO_SKIP_IDF_VERSION_CHECK=1
+#   idf.py build
+
+set(min_supported_idf_version "5.3.0")
+set(max_supported_idf_version "5.4.99")
+set(idf_version "${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}.${IDF_VERSION_PATCH}")
+
+if ("${idf_version}" AND NOT "$ENV{ARDUINO_SKIP_IDF_VERSION_CHECK}")
+  if (idf_version VERSION_LESS min_supported_idf_version)
+    message(FATAL_ERROR "Arduino-esp32 can be used with ESP-IDF versions "
+                        "between ${min_supported_idf_version} and ${max_supported_idf_version}, "
+                        "but an older version is detected: ${idf_version}.")
+  endif()
+  if (idf_version VERSION_GREATER max_supported_idf_version)
+    message(FATAL_ERROR "Arduino-esp32 can be used with ESP-IDF versions "
+                        "between ${min_supported_idf_version} and ${max_supported_idf_version}, "
+                        "but a newer version is detected: ${idf_version}.")
+  endif()
+endif()
+
 set(CORE_SRCS
   cores/esp32/base64.cpp
   cores/esp32/cbuf.cpp
+  cores/esp32/ColorFormat.c
+  cores/esp32/chip-debug-report.cpp
   cores/esp32/esp32-hal-adc.c
   cores/esp32/esp32-hal-bt.c
   cores/esp32/esp32-hal-cpu.c
   cores/esp32/esp32-hal-dac.c
   cores/esp32/esp32-hal-gpio.c
   cores/esp32/esp32-hal-i2c.c
+  cores/esp32/esp32-hal-i2c-ng.c
+  cores/esp32/esp32-hal-i2c-slave.c
   cores/esp32/esp32-hal-ledc.c
   cores/esp32/esp32-hal-matrix.c
   cores/esp32/esp32-hal-misc.c
+  cores/esp32/esp32-hal-periman.c
   cores/esp32/esp32-hal-psram.c
+  cores/esp32/esp32-hal-rgb-led.c
   cores/esp32/esp32-hal-sigmadelta.c
   cores/esp32/esp32-hal-spi.c
   cores/esp32/esp32-hal-time.c
   cores/esp32/esp32-hal-timer.c
+  cores/esp32/esp32-hal-tinyusb.c
   cores/esp32/esp32-hal-touch.c
+  cores/esp32/esp32-hal-touch-ng.c
   cores/esp32/esp32-hal-uart.c
   cores/esp32/esp32-hal-rmt.c
   cores/esp32/Esp.cpp
+  cores/esp32/freertos_stats.cpp
   cores/esp32/FunctionalInterrupt.cpp
   cores/esp32/HardwareSerial.cpp
+  cores/esp32/HEXBuilder.cpp
   cores/esp32/IPAddress.cpp
-  cores/esp32/IPv6Address.cpp
   cores/esp32/libb64/cdecode.c
   cores/esp32/libb64/cencode.c
+  cores/esp32/MacAddress.cpp
   cores/esp32/main.cpp
   cores/esp32/MD5Builder.cpp
   cores/esp32/Print.cpp
+  cores/esp32/SHA1Builder.cpp
   cores/esp32/stdlib_noniso.c
   cores/esp32/Stream.cpp
   cores/esp32/StreamString.cpp
+  cores/esp32/Tone.cpp
+  cores/esp32/HWCDC.cpp
+  cores/esp32/USB.cpp
+  cores/esp32/USBCDC.cpp
+  cores/esp32/USBMSC.cpp
+  cores/esp32/FirmwareMSC.cpp
+  cores/esp32/firmware_msc_fat.c
   cores/esp32/wiring_pulse.c
   cores/esp32/wiring_shift.c
   cores/esp32/WMath.cpp
   cores/esp32/WString.cpp
   )
 
-set(LIBRARY_SRCS
-  libraries/ArduinoOTA/src/ArduinoOTA.cpp
-  libraries/AsyncUDP/src/AsyncUDP.cpp
+set(ARDUINO_ALL_LIBRARIES
+  ArduinoOTA
+  AsyncUDP
+  BLE
+  BluetoothSerial
+  DNSServer
+  EEPROM
+  ESP_I2S
+  ESP_NOW
+  ESP_SR
+  ESPmDNS
+  Ethernet
+  FFat
+  FS
+  HTTPClient
+  HTTPUpdate
+  Insights
+  LittleFS
+  Matter
+  NetBIOS
+  Network
+  OpenThread
+  PPP
+  Preferences
+  RainMaker
+  SD_MMC
+  SD
+  SimpleBLE
+  SPIFFS
+  SPI
+  Ticker
+  Update
+  USB
+  WebServer
+  NetworkClientSecure
+  WiFi
+  WiFiProv
+  Wire
+  Zigbee
+  )
+
+set(ARDUINO_LIBRARY_ArduinoOTA_SRCS libraries/ArduinoOTA/src/ArduinoOTA.cpp)
+
+set(ARDUINO_LIBRARY_AsyncUDP_SRCS libraries/AsyncUDP/src/AsyncUDP.cpp)
+
+set(ARDUINO_LIBRARY_BluetoothSerial_SRCS
   libraries/BluetoothSerial/src/BluetoothSerial.cpp
-  libraries/DNSServer/src/DNSServer.cpp
-  libraries/EEPROM/src/EEPROM.cpp
-  libraries/ESPmDNS/src/ESPmDNS.cpp
-  libraries/FFat/src/FFat.cpp
+  libraries/BluetoothSerial/src/BTAddress.cpp
+  libraries/BluetoothSerial/src/BTAdvertisedDeviceSet.cpp
+  libraries/BluetoothSerial/src/BTScanResultsSet.cpp)
+
+set(ARDUINO_LIBRARY_DNSServer_SRCS libraries/DNSServer/src/DNSServer.cpp)
+
+set(ARDUINO_LIBRARY_EEPROM_SRCS libraries/EEPROM/src/EEPROM.cpp)
+
+set(ARDUINO_LIBRARY_ESP_I2S_SRCS libraries/ESP_I2S/src/ESP_I2S.cpp)
+
+set(ARDUINO_LIBRARY_ESP_NOW_SRCS
+  libraries/ESP_NOW/src/ESP32_NOW.cpp
+  libraries/ESP_NOW/src/ESP32_NOW_Serial.cpp)
+
+set(ARDUINO_LIBRARY_ESP_SR_SRCS
+  libraries/ESP_SR/src/ESP_SR.cpp
+  libraries/ESP_SR/src/esp32-hal-sr.c)
+
+set(ARDUINO_LIBRARY_ESPmDNS_SRCS libraries/ESPmDNS/src/ESPmDNS.cpp)
+
+set(ARDUINO_LIBRARY_Ethernet_SRCS libraries/Ethernet/src/ETH.cpp)
+
+set(ARDUINO_LIBRARY_FFat_SRCS libraries/FFat/src/FFat.cpp)
+
+set(ARDUINO_LIBRARY_FS_SRCS
   libraries/FS/src/FS.cpp
-  libraries/FS/src/vfs_api.cpp
-  libraries/HTTPClient/src/HTTPClient.cpp
-  libraries/HTTPUpdate/src/HTTPUpdate.cpp
-  libraries/NetBIOS/src/NetBIOS.cpp
-  libraries/Preferences/src/Preferences.cpp
-  libraries/SD_MMC/src/SD_MMC.cpp
+  libraries/FS/src/vfs_api.cpp)
+
+set(ARDUINO_LIBRARY_HTTPClient_SRCS libraries/HTTPClient/src/HTTPClient.cpp)
+
+set(ARDUINO_LIBRARY_HTTPUpdate_SRCS libraries/HTTPUpdate/src/HTTPUpdate.cpp)
+
+set(ARDUINO_LIBRARY_Insights_SRCS libraries/Insights/src/Insights.cpp)
+
+set(ARDUINO_LIBRARY_LittleFS_SRCS libraries/LittleFS/src/LittleFS.cpp)
+
+set(ARDUINO_LIBRARY_NetBIOS_SRCS libraries/NetBIOS/src/NetBIOS.cpp)
+
+set(ARDUINO_LIBRARY_OpenThread_SRCS
+  libraries/OpenThread/src/OThreadCLI.cpp
+  libraries/OpenThread/src/OThreadCLI_Util.cpp)
+
+set(ARDUINO_LIBRARY_Matter_SRCS
+  libraries/Matter/src/MatterEndpoints/MatterGenericSwitch.cpp
+  libraries/Matter/src/MatterEndpoints/MatterOnOffLight.cpp
+  libraries/Matter/src/MatterEndpoints/MatterDimmableLight.cpp
+  libraries/Matter/src/MatterEndpoints/MatterColorTemperatureLight.cpp
+  libraries/Matter/src/MatterEndpoints/MatterColorLight.cpp
+  libraries/Matter/src/MatterEndpoints/MatterEnhancedColorLight.cpp
+  libraries/Matter/src/MatterEndpoints/MatterFan.cpp
+  libraries/Matter/src/MatterEndpoints/MatterTemperatureSensor.cpp
+  libraries/Matter/src/MatterEndpoints/MatterHumiditySensor.cpp
+  libraries/Matter/src/MatterEndpoints/MatterContactSensor.cpp
+  libraries/Matter/src/MatterEndpoints/MatterPressureSensor.cpp
+  libraries/Matter/src/MatterEndpoints/MatterOccupancySensor.cpp
+  libraries/Matter/src/MatterEndpoints/MatterOnOffPlugin.cpp
+  libraries/Matter/src/MatterEndpoints/MatterThermostat.cpp
+  libraries/Matter/src/Matter.cpp)
+
+set(ARDUINO_LIBRARY_PPP_SRCS
+  libraries/PPP/src/PPP.cpp
+  libraries/PPP/src/ppp.c)
+
+set(ARDUINO_LIBRARY_Preferences_SRCS libraries/Preferences/src/Preferences.cpp)
+
+set(ARDUINO_LIBRARY_RainMaker_SRCS
+  libraries/RainMaker/src/RMaker.cpp
+  libraries/RainMaker/src/RMakerNode.cpp
+  libraries/RainMaker/src/RMakerParam.cpp
+  libraries/RainMaker/src/RMakerDevice.cpp
+  libraries/RainMaker/src/RMakerType.cpp
+  libraries/RainMaker/src/RMakerQR.cpp
+  libraries/RainMaker/src/RMakerUtils.cpp
+  libraries/RainMaker/src/AppInsights.cpp)
+
+set(ARDUINO_LIBRARY_SD_MMC_SRCS libraries/SD_MMC/src/SD_MMC.cpp)
+
+set(ARDUINO_LIBRARY_SD_SRCS
   libraries/SD/src/SD.cpp
   libraries/SD/src/sd_diskio.cpp
-  libraries/SD/src/sd_diskio_crc.c
-  libraries/SimpleBLE/src/SimpleBLE.cpp
-  libraries/SPIFFS/src/SPIFFS.cpp
-  libraries/SPI/src/SPI.cpp
-  libraries/Ticker/src/Ticker.cpp
+  libraries/SD/src/sd_diskio_crc.c)
+
+set(ARDUINO_LIBRARY_SimpleBLE_SRCS libraries/SimpleBLE/src/SimpleBLE.cpp)
+
+set(ARDUINO_LIBRARY_SPIFFS_SRCS libraries/SPIFFS/src/SPIFFS.cpp)
+
+set(ARDUINO_LIBRARY_SPI_SRCS libraries/SPI/src/SPI.cpp)
+
+set(ARDUINO_LIBRARY_Ticker_SRCS libraries/Ticker/src/Ticker.cpp)
+
+set(ARDUINO_LIBRARY_Update_SRCS
   libraries/Update/src/Updater.cpp
-  libraries/Update/src/HttpsOTAUpdate.cpp
+  libraries/Update/src/HttpsOTAUpdate.cpp)
+
+set(ARDUINO_LIBRARY_USB_SRCS
+  libraries/USB/src/USBHID.cpp
+  libraries/USB/src/USBMIDI.cpp
+  libraries/USB/src/USBHIDMouse.cpp
+  libraries/USB/src/USBHIDKeyboard.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_da_DK.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_de_DE.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_en_US.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_es_ES.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_fr_FR.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_hu_HU.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_it_IT.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_pt_BR.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_pt_PT.cpp
+  libraries/USB/src/keyboardLayout/KeyboardLayout_sv_SE.cpp
+  libraries/USB/src/USBHIDGamepad.cpp
+  libraries/USB/src/USBHIDConsumerControl.cpp
+  libraries/USB/src/USBHIDSystemControl.cpp
+  libraries/USB/src/USBHIDVendor.cpp
+  libraries/USB/src/USBVendor.cpp)
+
+set(ARDUINO_LIBRARY_WebServer_SRCS
   libraries/WebServer/src/WebServer.cpp
   libraries/WebServer/src/Parsing.cpp
   libraries/WebServer/src/detail/mimetable.cpp
-  libraries/WiFiClientSecure/src/ssl_client.cpp
-  libraries/WiFiClientSecure/src/WiFiClientSecure.cpp
-  libraries/WiFi/src/ETH.cpp
+  libraries/WebServer/src/middleware/MiddlewareChain.cpp
+  libraries/WebServer/src/middleware/AuthenticationMiddleware.cpp
+  libraries/WebServer/src/middleware/CorsMiddleware.cpp
+  libraries/WebServer/src/middleware/LoggingMiddleware.cpp)
+
+set(ARDUINO_LIBRARY_NetworkClientSecure_SRCS
+  libraries/NetworkClientSecure/src/ssl_client.cpp
+  libraries/NetworkClientSecure/src/NetworkClientSecure.cpp)
+
+set(ARDUINO_LIBRARY_Network_SRCS
+  libraries/Network/src/NetworkInterface.cpp
+  libraries/Network/src/NetworkEvents.cpp
+  libraries/Network/src/NetworkManager.cpp
+  libraries/Network/src/NetworkClient.cpp
+  libraries/Network/src/NetworkServer.cpp
+  libraries/Network/src/NetworkUdp.cpp)
+
+set(ARDUINO_LIBRARY_WiFi_SRCS
   libraries/WiFi/src/WiFiAP.cpp
-  libraries/WiFi/src/WiFiClient.cpp
   libraries/WiFi/src/WiFi.cpp
   libraries/WiFi/src/WiFiGeneric.cpp
   libraries/WiFi/src/WiFiMulti.cpp
   libraries/WiFi/src/WiFiScan.cpp
-  libraries/WiFi/src/WiFiServer.cpp
   libraries/WiFi/src/WiFiSTA.cpp
-  libraries/WiFi/src/WiFiUdp.cpp
-  libraries/WiFiProv/src/WiFiProv.cpp
-  libraries/Wire/src/Wire.cpp
-  )
+  libraries/WiFi/src/STA.cpp
+  libraries/WiFi/src/AP.cpp)
 
-set(AZURE_SRCS
-  libraries/AzureIoT/src/az_iot/azureiotcerts.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/agenttime.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/dns_async.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/freertos/lock.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/freertos/threadapi.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/freertos/tickcounter.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/lwip/sntp_lwip.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/socket_async.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/src/platform_openssl_compact.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/src/tlsio_openssl_compact.c
-  libraries/AzureIoT/src/az_iot/c-utility/pal/tlsio_options.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/base64.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/buffer.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/connection_string_parser.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/consolelogger.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/constbuffer.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/constmap.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/crt_abstractions.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/doublylinkedlist.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/gballoc.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/gb_stdio.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/gb_time.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/hmac.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/hmacsha256.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/httpapiex.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/httpapiexsas.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/httpheaders.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/http_proxy_io.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/map.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/optionhandler.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/sastoken.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/sha1.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/sha224.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/sha384-512.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/singlylinkedlist.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/strings.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/string_tokenizer.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/urlencode.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/usha.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/vector.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/xio.c
-  libraries/AzureIoT/src/az_iot/c-utility/src/xlogging.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/blob.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/iothub_client_authorization.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/iothub_client.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/iothub_client_ll.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/iothub_client_retry_control.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/iothub_message.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/iothubtransport.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/iothubtransportmqtt.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/iothubtransport_mqtt_common.c
-  libraries/AzureIoT/src/az_iot/iothub_client/src/version.c
-  libraries/AzureIoT/src/az_iot/umqtt/src/mqtt_client.c
-  libraries/AzureIoT/src/az_iot/umqtt/src/mqtt_codec.c
-  libraries/AzureIoT/src/az_iot/umqtt/src/mqtt_message.c
-  libraries/AzureIoT/src/AzureIotHub.cpp
-  libraries/AzureIoT/src/Esp32MQTTClient.cpp
+set(ARDUINO_LIBRARY_WiFiProv_SRCS libraries/WiFiProv/src/WiFiProv.cpp)
+
+set(ARDUINO_LIBRARY_Wire_SRCS libraries/Wire/src/Wire.cpp)
+
+set(ARDUINO_LIBRARY_Zigbee_SRCS
+  libraries/Zigbee/src/ZigbeeCore.cpp
+  libraries/Zigbee/src/ZigbeeEP.cpp
+  libraries/Zigbee/src/ZigbeeHandlers.cpp
+  libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.cpp
+  libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.cpp
+  libraries/Zigbee/src/ep/ZigbeeDimmableLight.cpp
+  libraries/Zigbee/src/ep/ZigbeeLight.cpp
+  libraries/Zigbee/src/ep/ZigbeeSwitch.cpp
+  libraries/Zigbee/src/ep/ZigbeeTempSensor.cpp
+  libraries/Zigbee/src/ep/ZigbeeThermostat.cpp
+  libraries/Zigbee/src/ep/ZigbeeFlowSensor.cpp
+  libraries/Zigbee/src/ep/ZigbeePressureSensor.cpp
+  libraries/Zigbee/src/ep/ZigbeeOccupancySensor.cpp
+  libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.cpp
+  libraries/Zigbee/src/ep/ZigbeeContactSwitch.cpp
+  libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.cpp
+  libraries/Zigbee/src/ep/ZigbeeWindowCovering.cpp
+  libraries/Zigbee/src/ep/ZigbeeVibrationSensor.cpp
+  libraries/Zigbee/src/ep/ZigbeeAnalog.cpp
+  libraries/Zigbee/src/ep/ZigbeeRangeExtender.cpp
+  libraries/Zigbee/src/ep/ZigbeeGateway.cpp
+  libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.cpp
+  libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.cpp
+  libraries/Zigbee/src/ep/ZigbeePM25Sensor.cpp
   )
 
-set(BLE_SRCS
+set(ARDUINO_LIBRARY_BLE_SRCS
+  libraries/BLE/src/BLE2901.cpp
   libraries/BLE/src/BLE2902.cpp
   libraries/BLE/src/BLE2904.cpp
   libraries/BLE/src/BLEAddress.cpp
@@ -172,48 +336,95 @@ set(BLE_SRCS
   libraries/BLE/src/GeneralUtils.cpp
   )
 
-set(COMPONENT_SRCS ${CORE_SRCS} ${LIBRARY_SRCS} ${AZURE_SRCS} ${BLE_SRCS})
-
-set(COMPONENT_ADD_INCLUDEDIRS
-  variants/esp32/
-  cores/esp32/
-  libraries/ArduinoOTA/src
-  libraries/AsyncUDP/src
-  libraries/AzureIoT/src
-  libraries/BLE/src
-  libraries/BluetoothSerial/src
-  libraries/DNSServer/src
-  libraries/EEPROM/src
-  libraries/ESP32/src
-  libraries/ESPmDNS/src
-  libraries/FFat/src
-  libraries/FS/src
-  libraries/HTTPClient/src
-  libraries/HTTPUpdate/src
-  libraries/NetBIOS/src
-  libraries/Preferences/src
-  libraries/SD_MMC/src
-  libraries/SD/src
-  libraries/SimpleBLE/src
-  libraries/SPIFFS/src
-  libraries/SPI/src
-  libraries/Ticker/src
-  libraries/Update/src
-  libraries/WebServer/src
-  libraries/WiFiClientSecure/src
-  libraries/WiFi/src
-  libraries/WiFiProv/src
-  libraries/Wire/src
-  )
+set(ARDUINO_LIBRARIES_SRCS)
+set(ARDUINO_LIBRARIES_REQUIRES)
+set(ARDUINO_LIBRARIES_INCLUDEDIRS)
+foreach(libname IN LISTS ARDUINO_ALL_LIBRARIES)
+  if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_${libname})
+    if(ARDUINO_LIBRARY_${libname}_SRCS)
+      list(APPEND ARDUINO_LIBRARIES_SRCS ${ARDUINO_LIBRARY_${libname}_SRCS})
+    endif()
+    if(ARDUINO_LIBRARY_${libname}_REQUIRES)
+      list(APPEND ARDUINO_LIBRARIES_REQUIRES ${ARDUINO_LIBRARY_${libname}_REQUIRES})
+    endif()
+    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/libraries/${libname}/src)
+      list(APPEND ARDUINO_LIBRARIES_INCLUDEDIRS libraries/${libname}/src)
+    endif()
+  endif()
+endforeach()
+
+set(includedirs variants/${CONFIG_ARDUINO_VARIANT}/ cores/esp32/ ${ARDUINO_LIBRARIES_INCLUDEDIRS})
+set(srcs ${CORE_SRCS} ${ARDUINO_LIBRARIES_SRCS})
+set(priv_includes cores/esp32/libb64)
+set(requires spi_flash esp_partition mbedtls wpa_supplicant esp_adc esp_eth http_parser esp_ringbuf esp_driver_gptimer esp_driver_usb_serial_jtag driver)
+set(priv_requires fatfs nvs_flash app_update spiffs bootloader_support bt esp_hid usb esp_psram ${ARDUINO_LIBRARIES_REQUIRES})
+
+if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_OpenThread)
+  #if(CONFIG_SOC_IEEE802154_SUPPORTED) # Does not work!
+  #if(CONFIG_OPENTHREAD_ENABLED) # Does not work!
+  if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2") # Sadly only this works
+    list(APPEND requires openthread)
+  endif()
+endif()
+
+if(IDF_TARGET STREQUAL "esp32p4")
+  list(APPEND requires esp_driver_touch_sens)
+endif()
+
+idf_component_register(INCLUDE_DIRS ${includedirs} PRIV_INCLUDE_DIRS ${priv_includes} SRCS ${srcs} REQUIRES ${requires} PRIV_REQUIRES ${priv_requires})
+
+if(NOT CONFIG_FREERTOS_HZ EQUAL 1000 AND NOT "$ENV{ARDUINO_SKIP_TICK_CHECK}")
+    # See delay() in cores/esp32/esp32-hal-misc.c.
+    message(FATAL_ERROR "esp32-arduino requires CONFIG_FREERTOS_HZ=1000 "
+                        "(currently ${CONFIG_FREERTOS_HZ})")
+endif()
 
-set(COMPONENT_PRIV_INCLUDEDIRS cores/esp32/libb64)
+string(TOUPPER ${CONFIG_ARDUINO_VARIANT} idf_target_caps)
+string(REPLACE "-" "_" idf_target_for_macro "${idf_target_caps}")
+target_compile_options(${COMPONENT_TARGET} PUBLIC
+    -DARDUINO=10812
+    -DARDUINO_${idf_target_for_macro}_DEV
+    -DARDUINO_ARCH_ESP32
+    -DARDUINO_BOARD="${idf_target_caps}_DEV"
+    -DARDUINO_VARIANT="${CONFIG_ARDUINO_VARIANT}"
+    -DESP32=ESP32)
 
-set(COMPONENT_REQUIRES spi_flash mbedtls mdns ethernet esp_adc_cal wifi_provisioning)
-set(COMPONENT_PRIV_REQUIRES fatfs nvs_flash app_update spiffs bootloader_support openssl bt esp_http_client esp_https_ota)
+if(CONFIG_AUTOSTART_ARDUINO)
+    # in autostart mode, arduino-esp32 contains app_main() function and needs to
+    # reference setup() and loop() in the main component. If we add main
+    # component to priv_requires then we create a large circular dependency
+    # (arduino-esp32 -> main -> arduino-esp32) and can get linker errors, so
+    # instead we add setup() and loop() to the undefined symbols list so the
+    # linker will always include them.
+    #
+    # (As they are C++ symbol, we need to add the C++ mangled names.)
+    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u _Z5setupv -u _Z4loopv")
+endif()
 
-register_component()
+# This function adds a dependency on the given component if the component is included into the build.
+function(maybe_add_component component_name)
+    idf_build_get_property(components BUILD_COMPONENTS)
+    if (${component_name} IN_LIST components)
+        idf_component_get_property(lib_name ${component_name} COMPONENT_LIB)
+        target_link_libraries(${COMPONENT_LIB} PUBLIC ${lib_name})
+    endif()
+endfunction()
 
-set_source_files_properties(libraries/AzureIoT/src/az_iot/iothub_client/src/iothubtransport_mqtt_common.c
-    PROPERTIES COMPILE_FLAGS
-    -Wno-maybe-uninitialized
-)
+if(IDF_TARGET MATCHES "esp32s2|esp32s3|esp32p4" AND CONFIG_TINYUSB_ENABLED)
+    maybe_add_component(arduino_tinyusb)
+endif()
+if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_ArduinoOTA)
+    maybe_add_component(esp_https_ota)
+endif()
+if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_ESP_SR)
+    maybe_add_component(espressif__esp_sr)
+endif()
+if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_Matter)
+    maybe_add_component(espressif__esp_matter)
+endif()
+if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_LittleFS)
+    maybe_add_component(joltwallet__littlefs)
+endif()
+if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_WiFiProv)
+    maybe_add_component(espressif__network_provisioning)
+endif()
diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md
new file mode 100644
index 00000000000..0c90775c760
--- /dev/null
+++ b/CODE_OF_CONDUCT.md
@@ -0,0 +1,128 @@
+# Contributor Covenant Code of Conduct
+
+## Our Pledge
+
+We as members, contributors, and leaders pledge to make participation in our
+community a harassment-free experience for everyone, regardless of age, body
+size, visible or invisible disability, ethnicity, sex characteristics, gender
+identity and expression, level of experience, education, socioeconomic status,
+nationality, personal appearance, race, religion, or sexual identity
+and orientation.
+
+We pledge to act and interact in ways that contribute to an open, welcoming,
+diverse, inclusive, and healthy community.
+
+## Our Standards
+
+Examples of behavior that contributes to a positive environment for our
+community include:
+
+* Demonstrating empathy and kindness toward other people
+* Being respectful of differing opinions, viewpoints, and experiences
+* Giving and gracefully accepting constructive feedback
+* Accepting responsibility and apologizing to those affected by our mistakes,
+  and learning from the experience
+* Focusing on what is best not just for us as individuals, but for the
+  overall community
+
+Examples of unacceptable behavior include:
+
+* The use of sexualized language or imagery, and sexual attention or
+  advances of any kind
+* Trolling, insulting or derogatory comments, and personal or political attacks
+* Public or private harassment
+* Publishing others' private information, such as a physical or email
+  address, without their explicit permission
+* Other conduct which could reasonably be considered inappropriate in a
+  professional setting
+
+## Enforcement Responsibilities
+
+Community leaders are responsible for clarifying and enforcing our standards of
+acceptable behavior and will take appropriate and fair corrective action in
+response to any behavior that they deem inappropriate, threatening, offensive,
+or harmful.
+
+Community leaders have the right and responsibility to remove, edit, or reject
+comments, commits, code, wiki edits, issues, and other contributions that are
+not aligned to this Code of Conduct, and will communicate reasons for moderation
+decisions when appropriate.
+
+## Scope
+
+This Code of Conduct applies within all community spaces, and also applies when
+an individual is officially representing the community in public spaces.
+Examples of representing our community include using an official e-mail address,
+posting via an official social media account, or acting as an appointed
+representative at an online or offline event.
+
+## Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be
+reported to the community leaders responsible for enforcement at
+vojtech.bartoska@espressif.com.
+All complaints will be reviewed and investigated promptly and fairly.
+
+All community leaders are obligated to respect the privacy and security of the
+reporter of any incident.
+
+## Enforcement Guidelines
+
+Community leaders will follow these Community Impact Guidelines in determining
+the consequences for any action they deem in violation of this Code of Conduct:
+
+### 1. Correction
+
+**Community Impact**: Use of inappropriate language or other behavior deemed
+unprofessional or unwelcome in the community.
+
+**Consequence**: A private, written warning from community leaders, providing
+clarity around the nature of the violation and an explanation of why the
+behavior was inappropriate. A public apology may be requested.
+
+### 2. Warning
+
+**Community Impact**: A violation through a single incident or series
+of actions.
+
+**Consequence**: A warning with consequences for continued behavior. No
+interaction with the people involved, including unsolicited interaction with
+those enforcing the Code of Conduct, for a specified period of time. This
+includes avoiding interactions in community spaces as well as external channels
+like social media. Violating these terms may lead to a temporary or
+permanent ban.
+
+### 3. Temporary Ban
+
+**Community Impact**: A serious violation of community standards, including
+sustained inappropriate behavior.
+
+**Consequence**: A temporary ban from any sort of interaction or public
+communication with the community for a specified period of time. No public or
+private interaction with the people involved, including unsolicited interaction
+with those enforcing the Code of Conduct, is allowed during this period.
+Violating these terms may lead to a permanent ban.
+
+### 4. Permanent Ban
+
+**Community Impact**: Demonstrating a pattern of violation of community
+standards, including sustained inappropriate behavior,  harassment of an
+individual, or aggression toward or disparagement of classes of individuals.
+
+**Consequence**: A permanent ban from any sort of public interaction within
+the community.
+
+## Attribution
+
+This Code of Conduct is adapted from the [Contributor Covenant][homepage],
+version 2.0, available at
+https://www.contributor-covenant.org/version/2/0/code_of_conduct.html.
+
+Community Impact Guidelines were inspired by [Mozilla's code of conduct
+enforcement ladder](https://github.com/mozilla/diversity).
+
+[homepage]: https://www.contributor-covenant.org
+
+For answers to common questions about this code of conduct, see the FAQ at
+https://www.contributor-covenant.org/faq. Translations are available at
+https://www.contributor-covenant.org/translations.
diff --git a/Kconfig.projbuild b/Kconfig.projbuild
index 740f077c5fc..9966463f8c1 100644
--- a/Kconfig.projbuild
+++ b/Kconfig.projbuild
@@ -1,11 +1,20 @@
 menu "Arduino Configuration"
 
+config ARDUINO_VARIANT
+    string "Arduino target variant (board)"
+    default IDF_TARGET
+    help
+        The name of a target variant (e.g., a specific board) in the variants/
+        folder, e.g.  "heltec_wifi_lora_32_V2". The name is case sensitive.
+        Specifying a variant name different from the target enables additional
+        customization, for example the definition of GPIO pins.
+
 config ENABLE_ARDUINO_DEPENDS
     bool
     select LWIP_SO_RCVBUF
     select ETHERNET
     select WIFI_ENABLED
-    select ESP32_PHY_CALIBRATION_AND_DATA_STORAGE
+    select ESP32_PHY_CALIBRATION_AND_DATA_STORAGE if IDF_TARGET_ESP32
     select MEMMAP_SMP
     default "y"
 
@@ -21,7 +30,8 @@ config AUTOSTART_ARDUINO
 
 choice ARDUINO_RUNNING_CORE
     bool "Core on which Arduino's setup() and loop() are running"
-    default ARDUINO_RUN_CORE1
+    default ARDUINO_RUN_CORE0 if FREERTOS_UNICORE
+    default ARDUINO_RUN_CORE1 if !FREERTOS_UNICORE
     help
         Select on which core Arduino's setup() and loop() functions run
 
@@ -29,8 +39,10 @@ choice ARDUINO_RUNNING_CORE
         bool "CORE 0"
     config ARDUINO_RUN_CORE1
         bool "CORE 1"
+        depends on !FREERTOS_UNICORE
     config ARDUINO_RUN_NO_AFFINITY
         bool "BOTH"
+        depends on !FREERTOS_UNICORE
 
 endchoice
 
@@ -40,9 +52,16 @@ config ARDUINO_RUNNING_CORE
     default 1 if ARDUINO_RUN_CORE1
     default -1 if ARDUINO_RUN_NO_AFFINITY
 
+config ARDUINO_LOOP_STACK_SIZE
+    int "Loop thread stack size"
+    default 8192
+    help
+        Amount of stack available for the Arduino task.
+
 choice ARDUINO_EVENT_RUNNING_CORE
     bool "Core on which Arduino's event handler is running"
-    default ARDUINO_EVENT_RUN_CORE1
+    default ARDUINO_EVENT_RUN_CORE0 if FREERTOS_UNICORE
+    default ARDUINO_EVENT_RUN_CORE1 if !FREERTOS_UNICORE
     help
         Select on which core Arduino's WiFi.onEvent() run
 
@@ -50,8 +69,10 @@ choice ARDUINO_EVENT_RUNNING_CORE
         bool "CORE 0"
     config ARDUINO_EVENT_RUN_CORE1
         bool "CORE 1"
+        depends on !FREERTOS_UNICORE
     config ARDUINO_EVENT_RUN_NO_AFFINITY
         bool "BOTH"
+        depends on !FREERTOS_UNICORE
 
 endchoice
 
@@ -61,9 +82,45 @@ config ARDUINO_EVENT_RUNNING_CORE
     default 1 if ARDUINO_EVENT_RUN_CORE1
     default -1 if ARDUINO_EVENT_RUN_NO_AFFINITY
 
+choice ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE
+    bool "Core on which Arduino's Serial Event task is running"
+    default ARDUINO_SERIAL_EVENT_RUN_CORE0 if FREERTOS_UNICORE
+    default ARDUINO_SERIAL_EVENT_RUN_NO_AFFINITY if !FREERTOS_UNICORE
+    help
+        Select on which core Arduino's Serial Event task run
+
+    config ARDUINO_SERIAL_EVENT_RUN_CORE0
+        bool "CORE 0"
+    config ARDUINO_SERIAL_EVENT_RUN_CORE1
+        bool "CORE 1"
+        depends on !FREERTOS_UNICORE
+    config ARDUINO_SERIAL_EVENT_RUN_NO_AFFINITY
+        bool "BOTH"
+        depends on !FREERTOS_UNICORE
+
+endchoice
+
+config ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE
+    int
+    default 0 if ARDUINO_SERIAL_EVENT_RUN_CORE0
+    default 1 if ARDUINO_SERIAL_EVENT_RUN_CORE1
+    default -1 if ARDUINO_SERIAL_EVENT_RUN_NO_AFFINITY
+
+config ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
+    int "Serial Event task stack size"
+    default 2048
+    help
+        Amount of stack available for the Serial Event task.
+
+config ARDUINO_SERIAL_EVENT_TASK_PRIORITY
+    int "Priority of the Serial Event task"
+    default 24
+    help
+        Select at what priority you want the Serial Event task to run.
+
 choice ARDUINO_UDP_RUNNING_CORE
     bool "Core on which Arduino's UDP is running"
-    default ARDUINO_UDP_RUN_CORE1
+    default ARDUINO_UDP_RUN_CORE0
     help
         Select on which core Arduino's UDP run
 
@@ -71,22 +128,34 @@ choice ARDUINO_UDP_RUNNING_CORE
         bool "CORE 0"
     config ARDUINO_UDP_RUN_CORE1
         bool "CORE 1"
+        depends on !FREERTOS_UNICORE
     config ARDUINO_UDP_RUN_NO_AFFINITY
         bool "BOTH"
+        depends on !FREERTOS_UNICORE
 
 endchoice
 
+config ARDUINO_UDP_RUNNING_CORE
+    int
+    default 0 if ARDUINO_UDP_RUN_CORE0
+    default 1 if ARDUINO_UDP_RUN_CORE1
+    default -1 if ARDUINO_UDP_RUN_NO_AFFINITY
+
 config ARDUINO_UDP_TASK_PRIORITY
     int "Priority of the UDP task"
     default 3
     help
         Select at what priority you want the UDP task to run.
 
-config ARDUINO_UDP_RUNNING_CORE
-    int
-    default 0 if ARDUINO_UDP_RUN_CORE0
-    default 1 if ARDUINO_UDP_RUN_CORE1
-    default -1 if ARDUINO_UDP_RUN_NO_AFFINITY
+config ARDUINO_ISR_IRAM
+    bool "Run interrupts in IRAM"
+    default "n"
+    help
+        Enabling this option will Attach all interrupts with the IRAm flag.
+        It will also make some HAL function, like, digitalRead/Write and more
+				be loaded into IRAM for access inside ISRs.
+				Beware that this is a very dangerous setting. Enable it only if you
+				are fully aware of the consequences.
 
 config DISABLE_HAL_LOCKS
     bool "Disable mutex locks for HAL"
@@ -140,7 +209,7 @@ config ARDUHAL_ESP_LOG
     default "n"
     help
         This option will redefine the ESP_LOGx macros to Arduino's log_x macros.
-        To enable for your application, add the follwing after your includes:
+        To enable for your application, add the following after your includes:
         #ifdef ARDUINO_ARCH_ESP32
         #include "esp32-hal-log.h"
         #endif
@@ -187,144 +256,177 @@ config ARDUINO_SELECTIVE_COMPILATION
     bool "Include only specific Arduino libraries"
     default n
 
-config ARDUINO_SELECTIVE_ArduinoOTA
-    bool "Enable ArduinoOTA"
+config ARDUINO_SELECTIVE_SPI
+    bool "Enable SPI"
     depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_WiFi
-    select ARDUINO_SELECTIVE_ESPmDNS
     default y
 
-config ARDUINO_SELECTIVE_AsyncUDP
-    bool "Enable AsyncUDP"
+config ARDUINO_SELECTIVE_Wire
+    bool "Enable Wire"
     depends on ARDUINO_SELECTIVE_COMPILATION
     default y
 
-config ARDUINO_SELECTIVE_AzureIoT
-    bool "Enable AzureIoT"
+config ARDUINO_SELECTIVE_ESP_SR
+    bool "Enable ESP-SR"
     depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_HTTPClient
     default y
 
-config ARDUINO_SELECTIVE_BLE
-    bool "Enable BLE"
+config ARDUINO_SELECTIVE_EEPROM
+    bool "Enable EEPROM"
     depends on ARDUINO_SELECTIVE_COMPILATION
     default y
 
-config ARDUINO_SELECTIVE_BluetoothSerial
-    bool "Enable BluetoothSerial"
+config ARDUINO_SELECTIVE_Preferences
+    bool "Enable Preferences"
     depends on ARDUINO_SELECTIVE_COMPILATION
     default y
 
-config ARDUINO_SELECTIVE_DNSServer
-    bool "Enable DNSServer"
+config ARDUINO_SELECTIVE_Ticker
+    bool "Enable Ticker"
     depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_WiFi
     default y
 
-config ARDUINO_SELECTIVE_EEPROM
-    bool "Enable EEPROM"
+config ARDUINO_SELECTIVE_Update
+    bool "Enable Update"
     depends on ARDUINO_SELECTIVE_COMPILATION
     default y
 
-config ARDUINO_SELECTIVE_ESP32
-    bool "Enable ESP32"
+config ARDUINO_SELECTIVE_Zigbee
+    bool "Enable Zigbee"
     depends on ARDUINO_SELECTIVE_COMPILATION
     default y
 
-config ARDUINO_SELECTIVE_ESPmDNS
-    bool "Enable ESPmDNS"
+config ARDUINO_SELECTIVE_FS
+    bool "Enable FS"
     depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_WiFi
+    default y
+
+config ARDUINO_SELECTIVE_SD
+    bool "Enable SD"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS
+    default y
+
+config ARDUINO_SELECTIVE_SD_MMC
+    bool "Enable SD_MMC"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS
+    default y
+
+config ARDUINO_SELECTIVE_SPIFFS
+    bool "Enable SPIFFS"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS
     default y
 
 config ARDUINO_SELECTIVE_FFat
     bool "Enable FFat"
-    depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_FS
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS
     default y
 
-config ARDUINO_SELECTIVE_FS
-    bool "Enable FS"
-    depends on ARDUINO_SELECTIVE_COMPILATION
+config ARDUINO_SELECTIVE_LittleFS
+    bool "Enable LittleFS"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_FS
     default y
 
-config ARDUINO_SELECTIVE_HTTPClient
-    bool "Enable HTTPClient"
+config ARDUINO_SELECTIVE_Network
+    bool "Enable Networking"
     depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_WiFi
-    select ARDUINO_SELECTIVE_WiFiClientSecure
     default y
 
-config ARDUINO_SELECTIVE_NetBIOS
-    bool "Enable NetBIOS"
+config ARDUINO_SELECTIVE_Ethernet
+    bool "Enable Ethernet"
     depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_WiFi
     default y
 
-config ARDUINO_SELECTIVE_Preferences
-    bool "Enable Preferences"
+config ARDUINO_SELECTIVE_PPP
+    bool "Enable PPP"
     depends on ARDUINO_SELECTIVE_COMPILATION
     default y
 
-config ARDUINO_SELECTIVE_SD
-    bool "Enable SD"
-    depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_FS
+config ARDUINO_SELECTIVE_ArduinoOTA
+    bool "Enable ArduinoOTA"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
+    select ARDUINO_SELECTIVE_ESPmDNS
     default y
 
-config ARDUINO_SELECTIVE_SD_MMC
-    bool "Enable SD_MMC"
-    depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_FS
+config ARDUINO_SELECTIVE_AsyncUDP
+    bool "Enable AsyncUDP"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
     default y
 
-config ARDUINO_SELECTIVE_SimpleBLE
-    bool "Enable SimpleBLE"
-    depends on ARDUINO_SELECTIVE_COMPILATION
+config ARDUINO_SELECTIVE_DNSServer
+    bool "Enable DNSServer"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
     default y
 
-config ARDUINO_SELECTIVE_SPI
-    bool "Enable SPI"
-    depends on ARDUINO_SELECTIVE_COMPILATION
+config ARDUINO_SELECTIVE_ESPmDNS
+    bool "Enable ESPmDNS"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
     default y
 
-config ARDUINO_SELECTIVE_SPIFFS
-    bool "Enable SPIFFS"
-    depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_FS
+config ARDUINO_SELECTIVE_HTTPClient
+    bool "Enable HTTPClient"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
+    select ARDUINO_SELECTIVE_NetworkClientSecure
     default y
 
-config ARDUINO_SELECTIVE_Ticker
-    bool "Enable Ticker"
-    depends on ARDUINO_SELECTIVE_COMPILATION
+config ARDUINO_SELECTIVE_Matter
+    bool "Enable Matter"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
     default y
 
-config ARDUINO_SELECTIVE_Update
-    bool "Enable Update"
-    depends on ARDUINO_SELECTIVE_COMPILATION
+config ARDUINO_SELECTIVE_NetBIOS
+    bool "Enable NetBIOS"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
     default y
 
 config ARDUINO_SELECTIVE_WebServer
     bool "Enable WebServer"
-    depends on ARDUINO_SELECTIVE_COMPILATION
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
     default y
     select ARDUINO_SELECTIVE_FS
 
 config ARDUINO_SELECTIVE_WiFi
     bool "Enable WiFi"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
+    default y
+
+config ARDUINO_SELECTIVE_NetworkClientSecure
+    bool "Enable NetworkClientSecure"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network
+    default y
+
+config ARDUINO_SELECTIVE_WiFiProv
+    bool "Enable WiFiProv"
+    depends on ARDUINO_SELECTIVE_COMPILATION && ARDUINO_SELECTIVE_Network && ARDUINO_SELECTIVE_WiFi
+    default y
+
+config ARDUINO_SELECTIVE_BLE
+    bool "Enable BLE"
     depends on ARDUINO_SELECTIVE_COMPILATION
     default y
 
-config ARDUINO_SELECTIVE_WiFiClientSecure
-    bool "Enable WiFiClientSecure"
+config ARDUINO_SELECTIVE_BluetoothSerial
+    bool "Enable BluetoothSerial"
     depends on ARDUINO_SELECTIVE_COMPILATION
-    select ARDUINO_SELECTIVE_WiFi
     default y
 
-config ARDUINO_SELECTIVE_Wire
-    bool "Enable Wire"
+config ARDUINO_SELECTIVE_SimpleBLE
+    bool "Enable SimpleBLE"
     depends on ARDUINO_SELECTIVE_COMPILATION
     default y
 
+config ARDUINO_SELECTIVE_RainMaker
+    bool "Enable RainMaker"
+    depends on ARDUINO_SELECTIVE_COMPILATION
+    default y
+
+config ARDUINO_SELECTIVE_OpenThread
+    bool "Enable OpenThread"
+    depends on ARDUINO_SELECTIVE_COMPILATION
+    default y
+
+config ARDUINO_SELECTIVE_Insights
+    bool "Enable Insights"
+    depends on ARDUINO_SELECTIVE_COMPILATION
+    default y
 
 endmenu
diff --git a/LICENSE.md b/LICENSE.md
index d55f6088e5e..b14d908353d 100644
--- a/LICENSE.md
+++ b/LICENSE.md
@@ -4,7 +4,7 @@ Version 2.1, February 1999
 
     Copyright (C) 1991, 1999 Free Software Foundation, Inc.
     51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-    
+
     Everyone is permitted to copy and distribute verbatim copies
     of this license document, but changing it is not allowed.
 
@@ -500,4 +500,4 @@ if necessary. Here is a sample; alter the names:
     signature of Ty Coon, 1 April 1990
     Ty Coon, President of Vice
 
-That's all there is to it!
\ No newline at end of file
+That's all there is to it!
diff --git a/Makefile.projbuild b/Makefile.projbuild
deleted file mode 100644
index 26b43787a6f..00000000000
--- a/Makefile.projbuild
+++ /dev/null
@@ -1,7 +0,0 @@
-BOOT_APP_BIN_ROOT := $(call dequote,$(COMPONENT_PATH))
-
-ifndef CONFIG_PARTITION_TABLE_CUSTOM
-PARTITION_TABLE_CSV_PATH = $(call dequote,$(abspath $(BOOT_APP_BIN_ROOT)/$(subst $(quote),,tools/partitions/$(CONFIG_ARDUHAL_PARTITION_SCHEME).csv)))
-endif
-
-CPPFLAGS += -DARDUINO=10800 -DESP32=1 -DARDUINO_ARCH_ESP32=1 -DBOARD_HAS_PSRAM
diff --git a/README.md b/README.md
index 8817f8ada66..f40315c03cc 100644
--- a/README.md
+++ b/README.md
@@ -1,49 +1,105 @@
-# Arduino core for the ESP32
-[![Build Status](https://travis-ci.org/espressif/arduino-esp32.svg?branch=master)](https://travis-ci.org/espressif/arduino-esp32) ![](https://github.com/espressif/arduino-esp32/workflows/ESP32%20Arduino%20CI/badge.svg)
+# Arduino core for the ESP32, ESP32-C3, ESP32-C6, ESP32-H2, ESP32-P4, ESP32-S2 and ESP32-S3.
 
-### Need help or have a question? Join the chat at [![https://gitter.im/espressif/arduino-esp32](https://badges.gitter.im/espressif/arduino-esp32.svg)](https://gitter.im/espressif/arduino-esp32?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
+[![Build Status](https://img.shields.io/github/actions/workflow/status/espressif/arduino-esp32/push.yml?branch=master&event=push&label=Compilation%20Tests)](https://github.com/espressif/arduino-esp32/actions/workflows/push.yml?query=branch%3Amaster+event%3Apush)
+[![Verbose Build Status](https://img.shields.io/github/actions/workflow/status/espressif/arduino-esp32/push.yml?branch=master&event=schedule&label=Compilation%20Tests%20(Verbose))](https://github.com/espressif/arduino-esp32/actions/workflows/push.yml?query=branch%3Amaster+event%3Aschedule)
+[![External Libraries Test](https://img.shields.io/github/actions/workflow/status/espressif/arduino-esp32/lib.yml?branch=master&event=schedule&label=External%20Libraries%20Test)](https://github.com/espressif/arduino-esp32/blob/gh-pages/LIBRARIES_TEST.md)
+[![Runtime Tests](https://github.com/espressif/arduino-esp32/blob/gh-pages/runtime-tests-results/badge.svg)](https://github.com/espressif/arduino-esp32/blob/gh-pages/runtime-tests-results/RUNTIME_TESTS_REPORT.md)
+
+### Need help or have a question? Join the chat at [Discord](https://discord.gg/8xY6e9crwv) or [open a new Discussion](https://github.com/espressif/arduino-esp32/discussions)
+
+[![Discord invite](https://img.shields.io/discord/1327272229427216425?logo=discord&logoColor=white&logoSize=auto&label=Discord)](https://discord.gg/8xY6e9crwv)
 
 ## Contents
-- [Development Status](#development-status)
-- [Installation Instructions](#installation-instructions)
-- [Decoding Exceptions](#decoding-exceptions)
-- [Issue/Bug report template](#issuebug-report-template)
-- [ESP32Dev Board PINMAP](#esp32dev-board-pinmap)
+
+  - [Development Status](#development-status)
+  - [Development Planning](#development-planning)
+  - [Documentation](#documentation)
+  - [Supported Chips](#supported-chips)
+  - [Decoding exceptions](#decoding-exceptions)
+  - [Issue/Bug report template](#issuebug-report-template)
+  - [Contributing](#contributing)
 
 ### Development Status
 
-Latest Stable Release  [![Release Version](https://img.shields.io/github/release/espressif/arduino-esp32.svg?style=plastic)](https://github.com/espressif/arduino-esp32/releases/latest/) [![Release Date](https://img.shields.io/github/release-date/espressif/arduino-esp32.svg?style=plastic)](https://github.com/espressif/arduino-esp32/releases/latest/) [![Downloads](https://img.shields.io/github/downloads/espressif/arduino-esp32/latest/total.svg?style=plastic)](https://github.com/espressif/arduino-esp32/releases/latest/)
+#### Latest Stable Release
+
+[![Release Version](https://img.shields.io/github/release/espressif/arduino-esp32.svg)](https://github.com/espressif/arduino-esp32/releases/latest/)
+[![Release Date](https://img.shields.io/github/release-date/espressif/arduino-esp32.svg)](https://github.com/espressif/arduino-esp32/releases/latest/)
+[![Downloads](https://img.shields.io/github/downloads/espressif/arduino-esp32/latest/total.svg)](https://github.com/espressif/arduino-esp32/releases/latest/)
+
+#### Latest Development Release
+
+[![Release Version](https://img.shields.io/github/release/espressif/arduino-esp32/all.svg)](https://github.com/espressif/arduino-esp32/releases/)
+[![Release Date](https://img.shields.io/github/release-date-pre/espressif/arduino-esp32.svg)](https://github.com/espressif/arduino-esp32/releases/)
+[![Downloads](https://img.shields.io/github/downloads-pre/espressif/arduino-esp32/latest/total.svg)](https://github.com/espressif/arduino-esp32/releases/)
+
+### Development Planning
+
+Our Development is fully tracked on this public **[Roadmap 🎉](https://github.com/orgs/espressif/projects/3)**
+
+For even more information you can join our **[Monthly Community Meetings 🔔](https://github.com/espressif/arduino-esp32/discussions/categories/monthly-community-meetings).**
+
+### Documentation
+
+You can use the [Arduino-ESP32 Online Documentation](https://docs.espressif.com/projects/arduino-esp32/en/latest/) to get all information about this project.
 
-Latest Development Release  [![Release Version](https://img.shields.io/github/release/espressif/arduino-esp32/all.svg?style=plastic)](https://github.com/espressif/arduino-esp32/releases/latest/) [![Release Date](https://img.shields.io/github/release-date-pre/espressif/arduino-esp32.svg?style=plastic)](https://github.com/espressif/arduino-esp32/releases/latest/) [![Downloads](https://img.shields.io/github/downloads-pre/espressif/arduino-esp32/latest/total.svg?style=plastic)](https://github.com/espressif/arduino-esp32/releases/latest/)
+---
 
+**Migration guide from version 2.x to 3.x is available [here](https://docs.espressif.com/projects/arduino-esp32/en/latest/migration_guides/2.x_to_3.0.html).**
 
-### Installation Instructions
-- Using Arduino IDE Boards Manager (preferred)
-  + [Instructions for Boards Manager](docs/arduino-ide/boards_manager.md)
-- Using Arduino IDE with the development repository
-  + [Instructions for Windows](docs/arduino-ide/windows.md)
-  + [Instructions for Mac](docs/arduino-ide/mac.md)
-  + [Instructions for Debian/Ubuntu Linux](docs/arduino-ide/debian_ubuntu.md)
-  + [Instructions for Fedora](docs/arduino-ide/fedora.md)
-  + [Instructions for openSUSE](docs/arduino-ide/opensuse.md)
-- [Using PlatformIO](docs/platformio.md)
-- [Building with make](docs/make.md)
-- [Using as ESP-IDF component](docs/esp-idf_component.md)
-- [Using OTAWebUpdater](docs/OTAWebUpdate/OTAWebUpdate.md)
+---
+
+**APIs compatibility with ESP8266 and Arduino-CORE (Arduino.cc) is explained [here](https://docs.espressif.com/projects/arduino-esp32/en/latest/libraries.html#apis).**
+
+---
+
+* [Getting Started](https://docs.espressif.com/projects/arduino-esp32/en/latest/getting_started.html)
+* [Installing (Windows, Linux and macOS)](https://docs.espressif.com/projects/arduino-esp32/en/latest/installing.html)
+* [Libraries](https://docs.espressif.com/projects/arduino-esp32/en/latest/libraries.html)
+* [Arduino as an ESP-IDF component](https://docs.espressif.com/projects/arduino-esp32/en/latest/esp-idf_component.html)
+* [FAQ](https://docs.espressif.com/projects/arduino-esp32/en/latest/faq.html)
+* [Troubleshooting](https://docs.espressif.com/projects/arduino-esp32/en/latest/troubleshooting.html)
+
+### Supported Chips
+
+Here are the ESP32 series supported by the Arduino-ESP32 project:
+
+| **SoC**  | **Stable** | **Development** |                                           **Datasheet**                                           |
+|----------|:----------:|:---------------:|:-------------------------------------------------------------------------------------------------:|
+| ESP32    |     Yes    |       Yes       |    [ESP32](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)    |
+| ESP32-C3 |     Yes    |       Yes       | [ESP32-C3](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf) |
+| ESP32-C6 |     Yes    |       Yes       | [ESP32-C6](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf) |
+| ESP32-H2 |     Yes    |       Yes       | [ESP32-H2](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf) |
+| ESP32-P4 |     Yes    |       Yes       | [ESP32-P4](https://www.espressif.com/sites/default/files/documentation/esp32-p4_datasheet_en.pdf) |
+| ESP32-S2 |     Yes    |       Yes       | [ESP32-S2](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf) |
+| ESP32-S3 |     Yes    |       Yes       | [ESP32-S3](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) |
+
+> [!NOTE]
+> ESP32-C2 is also supported by Arduino-ESP32 but requires using Arduino as an ESP-IDF component or rebuilding the static libraries.
+> For more information, see the [Arduino as an ESP-IDF component documentation](https://docs.espressif.com/projects/arduino-esp32/en/latest/esp-idf_component.html) or the
+> [Lib Builder documentation](https://docs.espressif.com/projects/arduino-esp32/en/latest/lib_builder.html), respectively.
+
+For more details visit the [supported chips](https://docs.espressif.com/projects/arduino-esp32/en/latest/getting_started.html#supported-soc-s) documentation page.
 
 ### Decoding exceptions
 
 You can use [EspExceptionDecoder](https://github.com/me-no-dev/EspExceptionDecoder) to get meaningful call trace.
 
 ### Issue/Bug report template
-Before reporting an issue, make sure you've searched for similar one that was already created. Also make sure to go through all the issues labelled as [for reference](https://github.com/espressif/arduino-esp32/issues?utf8=%E2%9C%93&q=is%3Aissue%20label%3A%22for%20reference%22%20).
 
-Finally, if you are sure no one else had the issue, follow the [ISSUE_TEMPLATE](docs/ISSUE_TEMPLATE.md) while reporting any issue.
+Before reporting an issue, make sure you've searched for similar one that was already created. Also make sure to go through all the issues labeled as [Type: For reference](https://github.com/espressif/arduino-esp32/issues?q=is%3Aissue+label%3A%22Type%3A+For+reference%22+).
+
+Finally, if you are sure no one else had the issue, follow the **Issue template** or **Feature request template** while reporting any [new Issue](https://github.com/espressif/arduino-esp32/issues/new/choose).
+
+### External libraries compilation test
+
+We have set-up CI testing for external libraries for ESP32 Arduino core. You can check test results in the file [LIBRARIES_TEST](https://github.com/espressif/arduino-esp32/blob/gh-pages/LIBRARIES_TEST.md).
+For more information and how to add your library to the test see [external library testing](https://docs.espressif.com/projects/arduino-esp32/en/latest/external_libraries_test.html) in the documentation.
 
-### ESP32Dev Board PINMAP
+### Contributing
 
-![Pin Functions](docs/esp32_pinmap.png)
+We welcome contributions to the Arduino ESP32 project!
 
-### Tip
+See [contributing](https://docs.espressif.com/projects/arduino-esp32/en/latest/contributing.html) in the documentation for more information on how to contribute to the project.
 
-Sometimes to program ESP32 via serial you must keep GPIO0 LOW during the programming process
+> We would like to have this repository in a polite and friendly atmosphere, so please be kind and respectful to others. For more details, look at [Code of Conduct](https://github.com/espressif/arduino-esp32/blob/master/CODE_OF_CONDUCT.md).
diff --git a/boards.txt b/boards.txt
index 67862f551d7..f0df27762c2 100644
--- a/boards.txt
+++ b/boards.txt
@@ -1,4 +1,10 @@
+# Official Espressif options
 menu.UploadSpeed=Upload Speed
+menu.USBMode=USB Mode
+menu.CDCOnBoot=USB CDC On Boot
+menu.MSCOnBoot=USB Firmware MSC On Boot
+menu.DFUOnBoot=USB DFU On Boot
+menu.UploadMode=Upload Mode
 menu.CPUFreq=CPU Frequency
 menu.FlashFreq=Flash Frequency
 menu.FlashMode=Flash Mode
@@ -6,22 +12,1419 @@ menu.FlashSize=Flash Size
 menu.PartitionScheme=Partition Scheme
 menu.DebugLevel=Core Debug Level
 menu.PSRAM=PSRAM
+menu.LoopCore=Arduino Runs On
+menu.EventsCore=Events Run On
+menu.MemoryType=Memory Type
+menu.EraseFlash=Erase All Flash Before Sketch Upload
+menu.JTAGAdapter=JTAG Adapter
+menu.ZigbeeMode=Zigbee Mode
+menu.PinNumbers=Pin Numbering
+
+# Custom options
 menu.Revision=Board Revision
-
+menu.LORAWAN_REGION=LoRaWan Region
+menu.LoRaWanDebugLevel=LoRaWan Debug Level
+menu.LORAWAN_DEVEUI=LoRaWan DevEUI
+menu.LORAWAN_PREAMBLE_LENGTH=LoRaWan Preamble Length
+menu.SLOW_CLK_TPYE=Slow Clk Type(only for LoRaWAN)
+menu.einksize=E-Ink Display Size
+menu.NetworkLogLevel=Network Log Level
 ##############################################################
 ### DO NOT PUT BOARDS ABOVE THE OFFICIAL ESPRESSIF BOARDS! ###
 ##############################################################
 
+# Generic definition to be used for USB discovery of CDC/JTAG
+esp32_family.name=ESP32 Family Device
+esp32_family.hide=true
+esp32_family.vid.0=0x303a
+esp32_family.pid.0=0x1001
+esp32_family.upload_port.0.vid=0x303a
+esp32_family.upload_port.0.pid=0x1001
+esp32_family.build.board=ESP32_FAMILY
+
+##############################################################
+
+esp32c2.name=ESP32C2 Dev Module
+esp32c2.hide=true
+
+esp32c2.bootloader.tool=esptool_py
+esp32c2.bootloader.tool.default=esptool_py
+
+esp32c2.upload.tool=esptool_py
+esp32c2.upload.tool.default=esptool_py
+esp32c2.upload.tool.network=esp_ota
+
+esp32c2.upload.maximum_size=1310720
+esp32c2.upload.maximum_data_size=327680
+esp32c2.upload.flags=
+esp32c2.upload.extra_flags=
+esp32c2.upload.use_1200bps_touch=false
+esp32c2.upload.wait_for_upload_port=false
+
+esp32c2.serial.disableDTR=false
+esp32c2.serial.disableRTS=false
+
+esp32c2.build.tarch=riscv32
+esp32c2.build.target=esp
+esp32c2.build.mcu=esp32c2
+esp32c2.build.core=esp32
+esp32c2.build.variant=esp32c2
+esp32c2.build.board=ESP32C2_DEV
+esp32c2.build.bootloader_addr=0x0
+
+esp32c2.build.cdc_on_boot=0
+esp32c2.build.f_cpu=120000000L
+esp32c2.build.flash_size=2MB
+esp32c2.build.flash_freq=60m
+esp32c2.build.flash_mode=qio
+esp32c2.build.boot=qio
+esp32c2.build.partitions=minimal
+esp32c2.build.defines=
+
+esp32c2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32c2.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32c2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32c2.menu.PartitionScheme.default.build.partitions=default
+esp32c2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32c2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32c2.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32c2.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32c2.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32c2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32c2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32c2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32c2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32c2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32c2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32c2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32c2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32c2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32c2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32c2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32c2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32c2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32c2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32c2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32c2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32c2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32c2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+esp32c2.menu.FlashMode.qio=QIO
+esp32c2.menu.FlashMode.qio.build.flash_mode=dio
+esp32c2.menu.FlashMode.qio.build.boot=qio
+esp32c2.menu.FlashMode.dio=DIO
+esp32c2.menu.FlashMode.dio.build.flash_mode=dio
+esp32c2.menu.FlashMode.dio.build.boot=dio
+
+esp32c2.menu.FlashFreq.60=60MHz
+esp32c2.menu.FlashFreq.60.build.flash_freq=60m
+esp32c2.menu.FlashFreq.30=30MHz
+esp32c2.menu.FlashFreq.30.build.flash_freq=30m
+
+esp32c2.menu.FlashSize.2M=2MB (16Mb)
+esp32c2.menu.FlashSize.2M.build.flash_size=2MB
+esp32c2.menu.FlashSize.4M=4MB (32Mb)
+esp32c2.menu.FlashSize.4M.build.flash_size=4MB
+
+esp32c2.menu.UploadSpeed.921600=921600
+esp32c2.menu.UploadSpeed.921600.upload.speed=921600
+esp32c2.menu.UploadSpeed.115200=115200
+esp32c2.menu.UploadSpeed.115200.upload.speed=115200
+esp32c2.menu.UploadSpeed.256000.windows=256000
+esp32c2.menu.UploadSpeed.256000.upload.speed=256000
+esp32c2.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32c2.menu.UploadSpeed.230400=230400
+esp32c2.menu.UploadSpeed.230400.upload.speed=230400
+esp32c2.menu.UploadSpeed.460800.linux=460800
+esp32c2.menu.UploadSpeed.460800.macosx=460800
+esp32c2.menu.UploadSpeed.460800.upload.speed=460800
+esp32c2.menu.UploadSpeed.512000.windows=512000
+esp32c2.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32c2.menu.DebugLevel.none=None
+esp32c2.menu.DebugLevel.none.build.code_debug=0
+esp32c2.menu.DebugLevel.error=Error
+esp32c2.menu.DebugLevel.error.build.code_debug=1
+esp32c2.menu.DebugLevel.warn=Warn
+esp32c2.menu.DebugLevel.warn.build.code_debug=2
+esp32c2.menu.DebugLevel.info=Info
+esp32c2.menu.DebugLevel.info.build.code_debug=3
+esp32c2.menu.DebugLevel.debug=Debug
+esp32c2.menu.DebugLevel.debug.build.code_debug=4
+esp32c2.menu.DebugLevel.verbose=Verbose
+esp32c2.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32c2.menu.EraseFlash.none=Disabled
+esp32c2.menu.EraseFlash.none.upload.erase_cmd=
+esp32c2.menu.EraseFlash.all=Enabled
+esp32c2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32p4.name=ESP32P4 Dev Module
+
+esp32p4.bootloader.tool=esptool_py
+esp32p4.bootloader.tool.default=esptool_py
+
+esp32p4.upload.tool=esptool_py
+esp32p4.upload.tool.default=esptool_py
+esp32p4.upload.tool.network=esp_ota
+
+esp32p4.upload.maximum_size=1310720
+esp32p4.upload.maximum_data_size=327680
+esp32p4.upload.flags=
+esp32p4.upload.extra_flags=
+esp32p4.upload.use_1200bps_touch=false
+esp32p4.upload.wait_for_upload_port=false
+
+esp32p4.serial.disableDTR=false
+esp32p4.serial.disableRTS=false
+
+esp32p4.build.tarch=riscv32
+esp32p4.build.target=esp
+esp32p4.build.mcu=esp32p4
+esp32p4.build.core=esp32
+esp32p4.build.variant=esp32p4
+esp32p4.build.board=ESP32P4_DEV
+esp32p4.build.bootloader_addr=0x2000
+
+esp32p4.build.usb_mode=0
+esp32p4.build.cdc_on_boot=0
+esp32p4.build.msc_on_boot=0
+esp32p4.build.dfu_on_boot=0
+esp32p4.build.f_cpu=360000000L
+esp32p4.build.flash_size=4MB
+esp32p4.build.flash_freq=80m
+esp32p4.build.img_freq=80m
+esp32p4.build.flash_mode=qio
+esp32p4.build.boot=qio
+esp32p4.build.partitions=default
+esp32p4.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32p4.menu.JTAGAdapter.default=Disabled
+esp32p4.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32p4.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32p4.menu.JTAGAdapter.builtin.build.openocdscript=esp32p4-builtin.cfg
+esp32p4.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32p4.menu.JTAGAdapter.external=FTDI Adapter
+esp32p4.menu.JTAGAdapter.external.build.openocdscript=esp32p4-ftdi.cfg
+esp32p4.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32p4.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32p4.menu.JTAGAdapter.bridge.build.openocdscript=esp32p4-bridge.cfg
+esp32p4.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32p4.menu.PSRAM.disabled=Disabled
+esp32p4.menu.PSRAM.disabled.build.defines=
+esp32p4.menu.PSRAM.enabled=Enabled
+esp32p4.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+esp32p4.menu.USBMode.default=USB-OTG (TinyUSB)
+esp32p4.menu.USBMode.default.build.usb_mode=0
+esp32p4.menu.USBMode.hwcdc=Hardware CDC and JTAG
+esp32p4.menu.USBMode.hwcdc.build.usb_mode=1
+
+esp32p4.menu.CDCOnBoot.default=Disabled
+esp32p4.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32p4.menu.CDCOnBoot.cdc=Enabled
+esp32p4.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32p4.menu.MSCOnBoot.default=Disabled
+esp32p4.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32p4.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+esp32p4.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32p4.menu.DFUOnBoot.default=Disabled
+esp32p4.menu.DFUOnBoot.default.build.dfu_on_boot=0
+esp32p4.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+esp32p4.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+esp32p4.menu.UploadMode.default=UART0 / Hardware CDC
+esp32p4.menu.UploadMode.default.upload.use_1200bps_touch=false
+esp32p4.menu.UploadMode.default.upload.wait_for_upload_port=false
+esp32p4.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+esp32p4.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+esp32p4.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+esp32p4.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32p4.menu.PartitionScheme.default.build.partitions=default
+esp32p4.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32p4.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32p4.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32p4.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32p4.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32p4.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32p4.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32p4.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32p4.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32p4.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32p4.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32p4.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32p4.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32p4.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32p4.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32p4.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32p4.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32p4.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32p4.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32p4.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32p4.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32p4.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32p4.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32p4.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32p4.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32p4.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32p4.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32p4.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32p4.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32p4.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32p4.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32p4.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32p4.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32p4.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32p4.menu.PartitionScheme.custom=Custom
+esp32p4.menu.PartitionScheme.custom.build.partitions=
+esp32p4.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+## From https://docs.espressif.com/projects/esp-idf/en/latest/esp32p4/api-reference/kconfig.html#config-esp-default-cpu-freq-mhz
+esp32p4.menu.CPUFreq.360=360MHz
+esp32p4.menu.CPUFreq.360.build.f_cpu=360000000L
+esp32p4.menu.CPUFreq.40=40MHz
+esp32p4.menu.CPUFreq.40.build.f_cpu=40000000L
+
+esp32p4.menu.FlashMode.qio=QIO
+esp32p4.menu.FlashMode.qio.build.flash_mode=dio
+esp32p4.menu.FlashMode.qio.build.boot=qio
+esp32p4.menu.FlashMode.dio=DIO
+esp32p4.menu.FlashMode.dio.build.flash_mode=dio
+esp32p4.menu.FlashMode.dio.build.boot=dio
+
+esp32p4.menu.FlashFreq.80=80MHz
+esp32p4.menu.FlashFreq.80.build.flash_freq=80m
+esp32p4.menu.FlashFreq.40=40MHz
+esp32p4.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32p4.menu.FlashSize.4M=4MB (32Mb)
+esp32p4.menu.FlashSize.4M.build.flash_size=4MB
+esp32p4.menu.FlashSize.8M=8MB (64Mb)
+esp32p4.menu.FlashSize.8M.build.flash_size=8MB
+esp32p4.menu.FlashSize.8M.build.partitions=default_8MB
+esp32p4.menu.FlashSize.2M=2MB (16Mb)
+esp32p4.menu.FlashSize.2M.build.flash_size=2MB
+esp32p4.menu.FlashSize.2M.build.partitions=minimal
+esp32p4.menu.FlashSize.16M=16MB (128Mb)
+esp32p4.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32p4.menu.UploadSpeed.921600=921600
+esp32p4.menu.UploadSpeed.921600.upload.speed=921600
+esp32p4.menu.UploadSpeed.115200=115200
+esp32p4.menu.UploadSpeed.115200.upload.speed=115200
+esp32p4.menu.UploadSpeed.256000.windows=256000
+esp32p4.menu.UploadSpeed.256000.upload.speed=256000
+esp32p4.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32p4.menu.UploadSpeed.230400=230400
+esp32p4.menu.UploadSpeed.230400.upload.speed=230400
+esp32p4.menu.UploadSpeed.460800.linux=460800
+esp32p4.menu.UploadSpeed.460800.macosx=460800
+esp32p4.menu.UploadSpeed.460800.upload.speed=460800
+esp32p4.menu.UploadSpeed.512000.windows=512000
+esp32p4.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32p4.menu.DebugLevel.none=None
+esp32p4.menu.DebugLevel.none.build.code_debug=0
+esp32p4.menu.DebugLevel.error=Error
+esp32p4.menu.DebugLevel.error.build.code_debug=1
+esp32p4.menu.DebugLevel.warn=Warn
+esp32p4.menu.DebugLevel.warn.build.code_debug=2
+esp32p4.menu.DebugLevel.info=Info
+esp32p4.menu.DebugLevel.info.build.code_debug=3
+esp32p4.menu.DebugLevel.debug=Debug
+esp32p4.menu.DebugLevel.debug.build.code_debug=4
+esp32p4.menu.DebugLevel.verbose=Verbose
+esp32p4.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32p4.menu.EraseFlash.none=Disabled
+esp32p4.menu.EraseFlash.none.upload.erase_cmd=
+esp32p4.menu.EraseFlash.all=Enabled
+esp32p4.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32h2.name=ESP32H2 Dev Module
+
+esp32h2.bootloader.tool=esptool_py
+esp32h2.bootloader.tool.default=esptool_py
+
+esp32h2.upload.tool=esptool_py
+esp32h2.upload.tool.default=esptool_py
+esp32h2.upload.tool.network=esp_ota
+
+esp32h2.upload.maximum_size=1310720
+esp32h2.upload.maximum_data_size=327680
+esp32h2.upload.flags=
+esp32h2.upload.extra_flags=
+esp32h2.upload.use_1200bps_touch=false
+esp32h2.upload.wait_for_upload_port=false
+
+esp32h2.serial.disableDTR=false
+esp32h2.serial.disableRTS=false
+
+esp32h2.build.tarch=riscv32
+esp32h2.build.target=esp
+esp32h2.build.mcu=esp32h2
+esp32h2.build.core=esp32
+esp32h2.build.variant=esp32h2
+esp32h2.build.board=ESP32H2_DEV
+esp32h2.build.bootloader_addr=0x0
+
+esp32h2.build.cdc_on_boot=0
+esp32h2.build.f_cpu=96000000L
+esp32h2.build.flash_size=4MB
+esp32h2.build.flash_freq=64m
+esp32h2.build.img_freq=48m
+esp32h2.build.flash_mode=qio
+esp32h2.build.boot=qio
+esp32h2.build.partitions=default
+esp32h2.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32h2.menu.JTAGAdapter.default=Disabled
+esp32h2.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32h2.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32h2.menu.JTAGAdapter.builtin.build.openocdscript=esp32h2-builtin.cfg
+esp32h2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32h2.menu.JTAGAdapter.external=FTDI Adapter
+esp32h2.menu.JTAGAdapter.external.build.openocdscript=esp32h2-ftdi.cfg
+esp32h2.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32h2.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32h2.menu.JTAGAdapter.bridge.build.openocdscript=esp32h2-bridge.cfg
+esp32h2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32h2.menu.CDCOnBoot.default=Disabled
+esp32h2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32h2.menu.CDCOnBoot.cdc=Enabled
+esp32h2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32h2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32h2.menu.PartitionScheme.default.build.partitions=default
+esp32h2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32h2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32h2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32h2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32h2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32h2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32h2.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32h2.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32h2.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32h2.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32h2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32h2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32h2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32h2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32h2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32h2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32h2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32h2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32h2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32h2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32h2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32h2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32h2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32h2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32h2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32h2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32h2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32h2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32h2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32h2.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32h2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32h2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32h2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32h2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+#esp32h2.menu.PartitionScheme.rainmaker=RainMaker 4MB
+#esp32h2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+#esp32h2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+#esp32h2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+#esp32h2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+#esp32h2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+#esp32h2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+#esp32h2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+#esp32h2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32h2.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs
+esp32h2.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB
+esp32h2.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720
+esp32h2.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+esp32h2.menu.PartitionScheme.zigbee.build.partitions=zigbee
+esp32h2.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+esp32h2.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs
+esp32h2.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB
+esp32h2.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872
+esp32h2.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs
+esp32h2.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB
+esp32h2.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720
+esp32h2.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32h2.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32h2.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32h2.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
+esp32h2.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
+esp32h2.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
+esp32h2.menu.PartitionScheme.custom=Custom
+esp32h2.menu.PartitionScheme.custom.build.partitions=
+esp32h2.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32h2.menu.FlashMode.qio=QIO
+esp32h2.menu.FlashMode.qio.build.flash_mode=dio
+esp32h2.menu.FlashMode.qio.build.boot=qio
+esp32h2.menu.FlashMode.dio=DIO
+esp32h2.menu.FlashMode.dio.build.flash_mode=dio
+esp32h2.menu.FlashMode.dio.build.boot=dio
+
+esp32h2.menu.FlashFreq.64=64MHz
+esp32h2.menu.FlashFreq.64.build.flash_freq=64m
+esp32h2.menu.FlashFreq.64.build.img_freq=48m
+#esp32h2.menu.FlashFreq.32=32MHz
+#esp32h2.menu.FlashFreq.32.build.flash_freq=32m
+#esp32h2.menu.FlashFreq.32.build.img_freq=24m
+esp32h2.menu.FlashFreq.16=16MHz
+esp32h2.menu.FlashFreq.16.build.flash_freq=16m
+esp32h2.menu.FlashFreq.16.build.img_freq=12m
+
+esp32h2.menu.FlashSize.4M=4MB (32Mb)
+esp32h2.menu.FlashSize.4M.build.flash_size=4MB
+esp32h2.menu.FlashSize.8M=8MB (64Mb)
+esp32h2.menu.FlashSize.8M.build.flash_size=8MB
+esp32h2.menu.FlashSize.2M=2MB (16Mb)
+esp32h2.menu.FlashSize.2M.build.flash_size=2MB
+esp32h2.menu.FlashSize.16M=16MB (128Mb)
+esp32h2.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32h2.menu.UploadSpeed.921600=921600
+esp32h2.menu.UploadSpeed.921600.upload.speed=921600
+esp32h2.menu.UploadSpeed.115200=115200
+esp32h2.menu.UploadSpeed.115200.upload.speed=115200
+esp32h2.menu.UploadSpeed.256000.windows=256000
+esp32h2.menu.UploadSpeed.256000.upload.speed=256000
+esp32h2.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32h2.menu.UploadSpeed.230400=230400
+esp32h2.menu.UploadSpeed.230400.upload.speed=230400
+esp32h2.menu.UploadSpeed.460800.linux=460800
+esp32h2.menu.UploadSpeed.460800.macosx=460800
+esp32h2.menu.UploadSpeed.460800.upload.speed=460800
+esp32h2.menu.UploadSpeed.512000.windows=512000
+esp32h2.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32h2.menu.DebugLevel.none=None
+esp32h2.menu.DebugLevel.none.build.code_debug=0
+esp32h2.menu.DebugLevel.error=Error
+esp32h2.menu.DebugLevel.error.build.code_debug=1
+esp32h2.menu.DebugLevel.warn=Warn
+esp32h2.menu.DebugLevel.warn.build.code_debug=2
+esp32h2.menu.DebugLevel.info=Info
+esp32h2.menu.DebugLevel.info.build.code_debug=3
+esp32h2.menu.DebugLevel.debug=Debug
+esp32h2.menu.DebugLevel.debug.build.code_debug=4
+esp32h2.menu.DebugLevel.verbose=Verbose
+esp32h2.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32h2.menu.EraseFlash.none=Disabled
+esp32h2.menu.EraseFlash.none.upload.erase_cmd=
+esp32h2.menu.EraseFlash.all=Enabled
+esp32h2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32h2.menu.ZigbeeMode.default=Disabled
+esp32h2.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32h2.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32h2.menu.ZigbeeMode.ed=Zigbee ED (end device)
+esp32h2.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+esp32h2.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+esp32h2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32h2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32h2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+esp32h2.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug
+esp32h2.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED
+esp32h2.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug
+esp32h2.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug
+esp32h2.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32h2.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug
+
+##############################################################
+
+esp32c6.name=ESP32C6 Dev Module
+
+esp32c6.bootloader.tool=esptool_py
+esp32c6.bootloader.tool.default=esptool_py
+
+esp32c6.upload.tool=esptool_py
+esp32c6.upload.tool.default=esptool_py
+esp32c6.upload.tool.network=esp_ota
+
+esp32c6.upload.maximum_size=1310720
+esp32c6.upload.maximum_data_size=327680
+esp32c6.upload.flags=
+esp32c6.upload.extra_flags=
+esp32c6.upload.use_1200bps_touch=false
+esp32c6.upload.wait_for_upload_port=false
+
+esp32c6.serial.disableDTR=false
+esp32c6.serial.disableRTS=false
+
+esp32c6.build.tarch=riscv32
+esp32c6.build.target=esp
+esp32c6.build.mcu=esp32c6
+esp32c6.build.core=esp32
+esp32c6.build.variant=esp32c6
+esp32c6.build.board=ESP32C6_DEV
+esp32c6.build.bootloader_addr=0x0
+
+esp32c6.build.cdc_on_boot=0
+esp32c6.build.f_cpu=160000000L
+esp32c6.build.flash_size=4MB
+esp32c6.build.flash_freq=80m
+esp32c6.build.flash_mode=qio
+esp32c6.build.boot=qio
+esp32c6.build.partitions=default
+esp32c6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32c6.menu.JTAGAdapter.default=Disabled
+esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32c6.menu.JTAGAdapter.external=FTDI Adapter
+esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32c6.menu.CDCOnBoot.default=Disabled
+esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32c6.menu.CDCOnBoot.cdc=Enabled
+esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32c6.menu.PartitionScheme.default.build.partitions=default
+esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32c6.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32c6.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32c6.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32c6.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32c6.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32c6.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32c6.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32c6.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32c6.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32c6.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32c6.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32c6.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32c6.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32c6.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32c6.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32c6.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs
+esp32c6.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB
+esp32c6.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720
+esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+esp32c6.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs
+esp32c6.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB
+esp32c6.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872
+esp32c6.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs
+esp32c6.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB
+esp32c6.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720
+esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32c6.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
+esp32c6.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
+esp32c6.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
+esp32c6.menu.PartitionScheme.custom=Custom
+esp32c6.menu.PartitionScheme.custom.build.partitions=
+esp32c6.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32c6.menu.CPUFreq.160=160MHz (WiFi)
+esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32c6.menu.CPUFreq.120=120MHz (WiFi)
+esp32c6.menu.CPUFreq.120.build.f_cpu=120000000L
+esp32c6.menu.CPUFreq.80=80MHz (WiFi)
+esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32c6.menu.CPUFreq.40=40MHz
+esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32c6.menu.CPUFreq.20=20MHz
+esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32c6.menu.CPUFreq.10=10MHz
+esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32c6.menu.FlashMode.qio=QIO
+esp32c6.menu.FlashMode.qio.build.flash_mode=dio
+esp32c6.menu.FlashMode.qio.build.boot=qio
+esp32c6.menu.FlashMode.dio=DIO
+esp32c6.menu.FlashMode.dio.build.flash_mode=dio
+esp32c6.menu.FlashMode.dio.build.boot=dio
+
+esp32c6.menu.FlashFreq.80=80MHz
+esp32c6.menu.FlashFreq.80.build.flash_freq=80m
+esp32c6.menu.FlashFreq.40=40MHz
+esp32c6.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32c6.menu.FlashSize.4M=4MB (32Mb)
+esp32c6.menu.FlashSize.4M.build.flash_size=4MB
+esp32c6.menu.FlashSize.8M=8MB (64Mb)
+esp32c6.menu.FlashSize.8M.build.flash_size=8MB
+esp32c6.menu.FlashSize.2M=2MB (16Mb)
+esp32c6.menu.FlashSize.2M.build.flash_size=2MB
+esp32c6.menu.FlashSize.16M=16MB (128Mb)
+esp32c6.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32c6.menu.UploadSpeed.921600=921600
+esp32c6.menu.UploadSpeed.921600.upload.speed=921600
+esp32c6.menu.UploadSpeed.115200=115200
+esp32c6.menu.UploadSpeed.115200.upload.speed=115200
+esp32c6.menu.UploadSpeed.256000.windows=256000
+esp32c6.menu.UploadSpeed.256000.upload.speed=256000
+esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32c6.menu.UploadSpeed.230400=230400
+esp32c6.menu.UploadSpeed.230400.upload.speed=230400
+esp32c6.menu.UploadSpeed.460800.linux=460800
+esp32c6.menu.UploadSpeed.460800.macosx=460800
+esp32c6.menu.UploadSpeed.460800.upload.speed=460800
+esp32c6.menu.UploadSpeed.512000.windows=512000
+esp32c6.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32c6.menu.DebugLevel.none=None
+esp32c6.menu.DebugLevel.none.build.code_debug=0
+esp32c6.menu.DebugLevel.error=Error
+esp32c6.menu.DebugLevel.error.build.code_debug=1
+esp32c6.menu.DebugLevel.warn=Warn
+esp32c6.menu.DebugLevel.warn.build.code_debug=2
+esp32c6.menu.DebugLevel.info=Info
+esp32c6.menu.DebugLevel.info.build.code_debug=3
+esp32c6.menu.DebugLevel.debug=Debug
+esp32c6.menu.DebugLevel.debug.build.code_debug=4
+esp32c6.menu.DebugLevel.verbose=Verbose
+esp32c6.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32c6.menu.EraseFlash.none=Disabled
+esp32c6.menu.EraseFlash.none.upload.erase_cmd=
+esp32c6.menu.EraseFlash.all=Enabled
+esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32c6.menu.ZigbeeMode.default=Disabled
+esp32c6.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32c6.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+esp32c6.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug
+esp32c6.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED
+esp32c6.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api.ed.debug -lzboss_stack.ed.debug -lzboss_port.native.debug
+esp32c6.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug
+esp32c6.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32c6.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lzboss_stack.zczr.debug -lzboss_port.native.debug
+
+##############################################################
+
+esp32s3.name=ESP32S3 Dev Module
+
+esp32s3.bootloader.tool=esptool_py
+esp32s3.bootloader.tool.default=esptool_py
+
+esp32s3.upload.tool=esptool_py
+esp32s3.upload.tool.default=esptool_py
+esp32s3.upload.tool.network=esp_ota
+
+esp32s3.upload.maximum_size=1310720
+esp32s3.upload.maximum_data_size=327680
+esp32s3.upload.flags=
+esp32s3.upload.extra_flags=
+esp32s3.upload.use_1200bps_touch=false
+esp32s3.upload.wait_for_upload_port=false
+
+esp32s3.serial.disableDTR=false
+esp32s3.serial.disableRTS=false
+
+esp32s3.build.tarch=xtensa
+esp32s3.build.bootloader_addr=0x0
+esp32s3.build.target=esp32s3
+esp32s3.build.mcu=esp32s3
+esp32s3.build.core=esp32
+esp32s3.build.variant=esp32s3
+esp32s3.build.board=ESP32S3_DEV
+
+esp32s3.build.usb_mode=1
+esp32s3.build.cdc_on_boot=0
+esp32s3.build.msc_on_boot=0
+esp32s3.build.dfu_on_boot=0
+esp32s3.build.f_cpu=240000000L
+esp32s3.build.flash_size=4MB
+esp32s3.build.flash_freq=80m
+esp32s3.build.flash_mode=dio
+esp32s3.build.boot=qio
+esp32s3.build.boot_freq=80m
+esp32s3.build.partitions=default
+esp32s3.build.defines=
+esp32s3.build.loop_core=
+esp32s3.build.event_core=
+esp32s3.build.psram_type=qspi
+esp32s3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+esp32s3.menu.JTAGAdapter.default=Disabled
+esp32s3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32s3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+esp32s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32s3.menu.JTAGAdapter.external=FTDI Adapter
+esp32s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+esp32s3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32s3.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+esp32s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32s3.menu.PSRAM.disabled=Disabled
+esp32s3.menu.PSRAM.disabled.build.defines=
+esp32s3.menu.PSRAM.disabled.build.psram_type=qspi
+esp32s3.menu.PSRAM.enabled=QSPI PSRAM
+esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+esp32s3.menu.PSRAM.enabled.build.psram_type=qspi
+esp32s3.menu.PSRAM.opi=OPI PSRAM
+esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+esp32s3.menu.PSRAM.opi.build.psram_type=opi
+
+esp32s3.menu.FlashMode.qio=QIO 80MHz
+esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+esp32s3.menu.FlashMode.qio.build.boot=qio
+esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+esp32s3.menu.FlashMode.qio120=QIO 120MHz
+esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+esp32s3.menu.FlashMode.qio120.build.boot=qio
+esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+esp32s3.menu.FlashMode.dio=DIO 80MHz
+esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+esp32s3.menu.FlashMode.dio.build.boot=dio
+esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+esp32s3.menu.FlashMode.opi=OPI 80MHz
+esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+esp32s3.menu.FlashMode.opi.build.boot=opi
+esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+
+esp32s3.menu.FlashSize.4M=4MB (32Mb)
+esp32s3.menu.FlashSize.4M.build.flash_size=4MB
+esp32s3.menu.FlashSize.8M=8MB (64Mb)
+esp32s3.menu.FlashSize.8M.build.flash_size=8MB
+esp32s3.menu.FlashSize.16M=16MB (128Mb)
+esp32s3.menu.FlashSize.16M.build.flash_size=16MB
+esp32s3.menu.FlashSize.32M=32MB (256Mb)
+esp32s3.menu.FlashSize.32M.build.flash_size=32MB
+
+esp32s3.menu.LoopCore.1=Core 1
+esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32s3.menu.LoopCore.0=Core 0
+esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+esp32s3.menu.EventsCore.1=Core 1
+esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+esp32s3.menu.EventsCore.0=Core 0
+esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+esp32s3.menu.USBMode.default.build.usb_mode=0
+
+esp32s3.menu.CDCOnBoot.default=Disabled
+esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32s3.menu.CDCOnBoot.cdc=Enabled
+esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32s3.menu.MSCOnBoot.default=Disabled
+esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32s3.menu.DFUOnBoot.default=Disabled
+esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s3.menu.PartitionScheme.default.build.partitions=default
+esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32s3.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32s3.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32s3.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32s3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+esp32s3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+esp32s3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+esp32s3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+esp32s3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+esp32s3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+esp32s3.menu.PartitionScheme.app13M_data7M_32MB=32M Flash (13MB APP/6.75MB SPIFFS)
+esp32s3.menu.PartitionScheme.app13M_data7M_32MB.build.partitions=default_32MB
+esp32s3.menu.PartitionScheme.app13M_data7M_32MB.upload.maximum_size=13107200
+esp32s3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+esp32s3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+esp32s3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+esp32s3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+esp32s3.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32s3.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32s3.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32s3.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
+esp32s3.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
+esp32s3.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
+esp32s3.menu.PartitionScheme.custom=Custom
+esp32s3.menu.PartitionScheme.custom.build.partitions=
+esp32s3.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32s3.menu.CPUFreq.40=40MHz
+esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32s3.menu.CPUFreq.20=20MHz
+esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32s3.menu.CPUFreq.10=10MHz
+esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32s3.menu.UploadSpeed.921600=921600
+esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+esp32s3.menu.UploadSpeed.115200=115200
+esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+esp32s3.menu.UploadSpeed.256000.windows=256000
+esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32s3.menu.UploadSpeed.230400=230400
+esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+esp32s3.menu.UploadSpeed.460800.linux=460800
+esp32s3.menu.UploadSpeed.460800.macosx=460800
+esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+esp32s3.menu.UploadSpeed.512000.windows=512000
+esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32s3.menu.DebugLevel.none=None
+esp32s3.menu.DebugLevel.none.build.code_debug=0
+esp32s3.menu.DebugLevel.error=Error
+esp32s3.menu.DebugLevel.error.build.code_debug=1
+esp32s3.menu.DebugLevel.warn=Warn
+esp32s3.menu.DebugLevel.warn.build.code_debug=2
+esp32s3.menu.DebugLevel.info=Info
+esp32s3.menu.DebugLevel.info.build.code_debug=3
+esp32s3.menu.DebugLevel.debug=Debug
+esp32s3.menu.DebugLevel.debug.build.code_debug=4
+esp32s3.menu.DebugLevel.verbose=Verbose
+esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s3.menu.EraseFlash.none=Disabled
+esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+esp32s3.menu.EraseFlash.all=Enabled
+esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32s3.menu.ZigbeeMode.default=Disabled
+esp32s3.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32s3.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+esp32c3.name=ESP32C3 Dev Module
+
+esp32c3.bootloader.tool=esptool_py
+esp32c3.bootloader.tool.default=esptool_py
+
+esp32c3.upload.tool=esptool_py
+esp32c3.upload.tool.default=esptool_py
+esp32c3.upload.tool.network=esp_ota
+
+esp32c3.upload.maximum_size=1310720
+esp32c3.upload.maximum_data_size=327680
+esp32c3.upload.flags=
+esp32c3.upload.extra_flags=
+esp32c3.upload.use_1200bps_touch=false
+esp32c3.upload.wait_for_upload_port=false
+
+esp32c3.serial.disableDTR=false
+esp32c3.serial.disableRTS=false
+
+esp32c3.build.tarch=riscv32
+esp32c3.build.target=esp
+esp32c3.build.mcu=esp32c3
+esp32c3.build.core=esp32
+esp32c3.build.variant=esp32c3
+esp32c3.build.board=ESP32C3_DEV
+esp32c3.build.bootloader_addr=0x0
+
+esp32c3.build.cdc_on_boot=0
+esp32c3.build.f_cpu=160000000L
+esp32c3.build.flash_size=4MB
+esp32c3.build.flash_freq=80m
+esp32c3.build.flash_mode=qio
+esp32c3.build.boot=qio
+esp32c3.build.partitions=default
+esp32c3.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32c3.menu.JTAGAdapter.default=Disabled
+esp32c3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32c3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32c3.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg
+esp32c3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32c3.menu.JTAGAdapter.external=FTDI Adapter
+esp32c3.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg
+esp32c3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32c3.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32c3.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg
+esp32c3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32c3.menu.CDCOnBoot.default=Disabled
+esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32c3.menu.CDCOnBoot.cdc=Enabled
+esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32c3.menu.PartitionScheme.default.build.partitions=default
+esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32c3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32c3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32c3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32c3.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32c3.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32c3.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32c3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32c3.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32c3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32c3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32c3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32c3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32c3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32c3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32c3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32c3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32c3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32c3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32c3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32c3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32c3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32c3.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32c3.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32c3.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32c3.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
+esp32c3.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
+esp32c3.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
+esp32c3.menu.PartitionScheme.custom=Custom
+esp32c3.menu.PartitionScheme.custom.build.partitions=
+esp32c3.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32c3.menu.CPUFreq.160=160MHz (WiFi)
+esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32c3.menu.CPUFreq.80=80MHz (WiFi)
+esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32c3.menu.CPUFreq.40=40MHz
+esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32c3.menu.CPUFreq.20=20MHz
+esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32c3.menu.CPUFreq.10=10MHz
+esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32c3.menu.FlashMode.qio=QIO
+esp32c3.menu.FlashMode.qio.build.flash_mode=dio
+esp32c3.menu.FlashMode.qio.build.boot=qio
+esp32c3.menu.FlashMode.dio=DIO
+esp32c3.menu.FlashMode.dio.build.flash_mode=dio
+esp32c3.menu.FlashMode.dio.build.boot=dio
+
+esp32c3.menu.FlashFreq.80=80MHz
+esp32c3.menu.FlashFreq.80.build.flash_freq=80m
+esp32c3.menu.FlashFreq.40=40MHz
+esp32c3.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32c3.menu.FlashSize.4M=4MB (32Mb)
+esp32c3.menu.FlashSize.4M.build.flash_size=4MB
+esp32c3.menu.FlashSize.8M=8MB (64Mb)
+esp32c3.menu.FlashSize.8M.build.flash_size=8MB
+esp32c3.menu.FlashSize.2M=2MB (16Mb)
+esp32c3.menu.FlashSize.2M.build.flash_size=2MB
+esp32c3.menu.FlashSize.16M=16MB (128Mb)
+esp32c3.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32c3.menu.UploadSpeed.921600=921600
+esp32c3.menu.UploadSpeed.921600.upload.speed=921600
+esp32c3.menu.UploadSpeed.115200=115200
+esp32c3.menu.UploadSpeed.115200.upload.speed=115200
+esp32c3.menu.UploadSpeed.256000.windows=256000
+esp32c3.menu.UploadSpeed.256000.upload.speed=256000
+esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32c3.menu.UploadSpeed.230400=230400
+esp32c3.menu.UploadSpeed.230400.upload.speed=230400
+esp32c3.menu.UploadSpeed.460800.linux=460800
+esp32c3.menu.UploadSpeed.460800.macosx=460800
+esp32c3.menu.UploadSpeed.460800.upload.speed=460800
+esp32c3.menu.UploadSpeed.512000.windows=512000
+esp32c3.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32c3.menu.DebugLevel.none=None
+esp32c3.menu.DebugLevel.none.build.code_debug=0
+esp32c3.menu.DebugLevel.error=Error
+esp32c3.menu.DebugLevel.error.build.code_debug=1
+esp32c3.menu.DebugLevel.warn=Warn
+esp32c3.menu.DebugLevel.warn.build.code_debug=2
+esp32c3.menu.DebugLevel.info=Info
+esp32c3.menu.DebugLevel.info.build.code_debug=3
+esp32c3.menu.DebugLevel.debug=Debug
+esp32c3.menu.DebugLevel.debug.build.code_debug=4
+esp32c3.menu.DebugLevel.verbose=Verbose
+esp32c3.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32c3.menu.EraseFlash.none=Disabled
+esp32c3.menu.EraseFlash.none.upload.erase_cmd=
+esp32c3.menu.EraseFlash.all=Enabled
+esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32c3.menu.ZigbeeMode.default=Disabled
+esp32c3.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32c3.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32c3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32c3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32c3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+esp32s2.name=ESP32S2 Dev Module
+esp32s2.vid.0=0x303a
+esp32s2.pid.0=0x0002
+esp32s2.upload_port.vid.0=0x303a
+esp32s2.upload_port.pid.0=0x0002
+
+esp32s2.bootloader.tool=esptool_py
+esp32s2.bootloader.tool.default=esptool_py
+
+esp32s2.upload.tool=esptool_py
+esp32s2.upload.tool.default=esptool_py
+esp32s2.upload.tool.network=esp_ota
+
+esp32s2.upload.maximum_size=1310720
+esp32s2.upload.maximum_data_size=327680
+esp32s2.upload.flags=
+esp32s2.upload.extra_flags=
+esp32s2.upload.use_1200bps_touch=false
+esp32s2.upload.wait_for_upload_port=false
+
+esp32s2.serial.disableDTR=false
+esp32s2.serial.disableRTS=false
+
+esp32s2.build.tarch=xtensa
+esp32s2.build.bootloader_addr=0x1000
+esp32s2.build.target=esp32s2
+esp32s2.build.mcu=esp32s2
+esp32s2.build.core=esp32
+esp32s2.build.variant=esp32s2
+esp32s2.build.board=ESP32S2_DEV
+
+esp32s2.build.cdc_on_boot=0
+esp32s2.build.msc_on_boot=0
+esp32s2.build.dfu_on_boot=0
+esp32s2.build.f_cpu=240000000L
+esp32s2.build.flash_size=4MB
+esp32s2.build.flash_freq=80m
+esp32s2.build.flash_mode=dio
+esp32s2.build.boot=qio
+esp32s2.build.partitions=default
+esp32s2.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32s2.menu.JTAGAdapter.default=Disabled
+esp32s2.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32s2.menu.JTAGAdapter.external=FTDI Adapter
+esp32s2.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg
+esp32s2.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32s2.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32s2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg
+esp32s2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32s2.menu.CDCOnBoot.default=Disabled
+esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32s2.menu.CDCOnBoot.cdc=Enabled
+esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32s2.menu.MSCOnBoot.default=Disabled
+esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32s2.menu.MSCOnBoot.msc=Enabled
+esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32s2.menu.DFUOnBoot.default=Disabled
+esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+esp32s2.menu.DFUOnBoot.dfu=Enabled
+esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+esp32s2.menu.UploadMode.default=UART0
+esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false
+esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false
+esp32s2.menu.UploadMode.cdc=Internal USB
+esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+esp32s2.menu.PSRAM.disabled=Disabled
+esp32s2.menu.PSRAM.disabled.build.defines=
+esp32s2.menu.PSRAM.enabled=Enabled
+esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s2.menu.PartitionScheme.default.build.partitions=default
+esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32s2.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32s2.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32s2.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32s2.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32s2.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32s2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32s2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32s2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32s2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32s2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32s2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32s2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32s2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32s2.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32s2.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32s2.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32s2.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
+esp32s2.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
+esp32s2.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
+esp32s2.menu.PartitionScheme.custom=Custom
+esp32s2.menu.PartitionScheme.custom.build.partitions=
+esp32s2.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32s2.menu.CPUFreq.240=240MHz (WiFi)
+esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32s2.menu.CPUFreq.160=160MHz (WiFi)
+esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32s2.menu.CPUFreq.80=80MHz (WiFi)
+esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32s2.menu.CPUFreq.40=40MHz
+esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32s2.menu.CPUFreq.20=20MHz
+esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32s2.menu.CPUFreq.10=10MHz
+esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32s2.menu.FlashMode.qio=QIO
+esp32s2.menu.FlashMode.qio.build.flash_mode=dio
+esp32s2.menu.FlashMode.qio.build.boot=qio
+esp32s2.menu.FlashMode.dio=DIO
+esp32s2.menu.FlashMode.dio.build.flash_mode=dio
+esp32s2.menu.FlashMode.dio.build.boot=dio
+
+esp32s2.menu.FlashFreq.80=80MHz
+esp32s2.menu.FlashFreq.80.build.flash_freq=80m
+esp32s2.menu.FlashFreq.40=40MHz
+esp32s2.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32s2.menu.FlashSize.4M=4MB (32Mb)
+esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+esp32s2.menu.FlashSize.8M=8MB (64Mb)
+esp32s2.menu.FlashSize.8M.build.flash_size=8MB
+esp32s2.menu.FlashSize.2M=2MB (16Mb)
+esp32s2.menu.FlashSize.2M.build.flash_size=2MB
+esp32s2.menu.FlashSize.16M=16MB (128Mb)
+esp32s2.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32s2.menu.UploadSpeed.921600=921600
+esp32s2.menu.UploadSpeed.921600.upload.speed=921600
+esp32s2.menu.UploadSpeed.115200=115200
+esp32s2.menu.UploadSpeed.115200.upload.speed=115200
+esp32s2.menu.UploadSpeed.256000.windows=256000
+esp32s2.menu.UploadSpeed.256000.upload.speed=256000
+esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32s2.menu.UploadSpeed.230400=230400
+esp32s2.menu.UploadSpeed.230400.upload.speed=230400
+esp32s2.menu.UploadSpeed.460800.linux=460800
+esp32s2.menu.UploadSpeed.460800.macosx=460800
+esp32s2.menu.UploadSpeed.460800.upload.speed=460800
+esp32s2.menu.UploadSpeed.512000.windows=512000
+esp32s2.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32s2.menu.DebugLevel.none=None
+esp32s2.menu.DebugLevel.none.build.code_debug=0
+esp32s2.menu.DebugLevel.error=Error
+esp32s2.menu.DebugLevel.error.build.code_debug=1
+esp32s2.menu.DebugLevel.warn=Warn
+esp32s2.menu.DebugLevel.warn.build.code_debug=2
+esp32s2.menu.DebugLevel.info=Info
+esp32s2.menu.DebugLevel.info.build.code_debug=3
+esp32s2.menu.DebugLevel.debug=Debug
+esp32s2.menu.DebugLevel.debug.build.code_debug=4
+esp32s2.menu.DebugLevel.verbose=Verbose
+esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s2.menu.EraseFlash.none=Disabled
+esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+esp32s2.menu.EraseFlash.all=Enabled
+esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32s2.menu.ZigbeeMode.default=Disabled
+esp32s2.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32s2.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
 esp32.name=ESP32 Dev Module
 
+esp32.bootloader.tool=esptool_py
+esp32.bootloader.tool.default=esptool_py
+
 esp32.upload.tool=esptool_py
+esp32.upload.tool.default=esptool_py
+esp32.upload.tool.network=esp_ota
+
 esp32.upload.maximum_size=1310720
 esp32.upload.maximum_data_size=327680
-esp32.upload.wait_for_upload_port=true
+esp32.upload.flags=
+esp32.upload.extra_flags=
 
 esp32.serial.disableDTR=true
 esp32.serial.disableRTS=true
 
+esp32.build.tarch=xtensa
+esp32.build.bootloader_addr=0x1000
+esp32.build.target=esp32
 esp32.build.mcu=esp32
 esp32.build.core=esp32
 esp32.build.variant=esp32
@@ -34,21 +1437,38 @@ esp32.build.flash_mode=dio
 esp32.build.boot=dio
 esp32.build.partitions=default
 esp32.build.defines=
+esp32.build.loop_core=
+esp32.build.event_core=
+
+## IDE 2.0 Seems to not update the value
+esp32.menu.JTAGAdapter.default=Disabled
+esp32.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32.menu.JTAGAdapter.external=FTDI Adapter
+esp32.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg
+esp32.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg
+esp32.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
 
 esp32.menu.PSRAM.disabled=Disabled
 esp32.menu.PSRAM.disabled.build.defines=
+esp32.menu.PSRAM.disabled.build.extra_libs=
 esp32.menu.PSRAM.enabled=Enabled
-esp32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+esp32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+esp32.menu.PSRAM.enabled.build.extra_libs=
 
 esp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
 esp32.menu.PartitionScheme.default.build.partitions=default
 esp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
 esp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
-esp32.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+esp32.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
 esp32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
 esp32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
 esp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
 esp32.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
 esp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
 esp32.menu.PartitionScheme.no_ota.build.partitions=no_ota
 esp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
@@ -67,12 +1487,30 @@ esp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
 esp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
 esp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 esp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-esp32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+esp32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
 esp32.menu.PartitionScheme.fatflash.build.partitions=ffat
 esp32.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
-esp32.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+esp32.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
 esp32.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
 esp32.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
+esp32.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
+esp32.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
+esp32.menu.PartitionScheme.custom=Custom
+esp32.menu.PartitionScheme.custom.build.partitions=
+esp32.menu.PartitionScheme.custom.upload.maximum_size=16777216
 
 esp32.menu.CPUFreq.240=240MHz (WiFi/BT)
 esp32.menu.CPUFreq.240.build.f_cpu=240000000L
@@ -97,12 +1535,6 @@ esp32.menu.FlashMode.qio.build.boot=qio
 esp32.menu.FlashMode.dio=DIO
 esp32.menu.FlashMode.dio.build.flash_mode=dio
 esp32.menu.FlashMode.dio.build.boot=dio
-esp32.menu.FlashMode.qout=QOUT
-esp32.menu.FlashMode.qout.build.flash_mode=dout
-esp32.menu.FlashMode.qout.build.boot=qout
-esp32.menu.FlashMode.dout=DOUT
-esp32.menu.FlashMode.dout.build.flash_mode=dout
-esp32.menu.FlashMode.dout.build.boot=dout
 
 esp32.menu.FlashFreq.80=80MHz
 esp32.menu.FlashFreq.80.build.flash_freq=80m
@@ -113,10 +1545,8 @@ esp32.menu.FlashSize.4M=4MB (32Mb)
 esp32.menu.FlashSize.4M.build.flash_size=4MB
 esp32.menu.FlashSize.8M=8MB (64Mb)
 esp32.menu.FlashSize.8M.build.flash_size=8MB
-esp32.menu.FlashSize.8M.build.partitions=default_8MB
 esp32.menu.FlashSize.2M=2MB (16Mb)
 esp32.menu.FlashSize.2M.build.flash_size=2MB
-esp32.menu.FlashSize.2M.build.partitions=minimal
 esp32.menu.FlashSize.16M=16MB (128Mb)
 esp32.menu.FlashSize.16M.build.flash_size=16MB
 
@@ -135,6 +1565,16 @@ esp32.menu.UploadSpeed.460800.upload.speed=460800
 esp32.menu.UploadSpeed.512000.windows=512000
 esp32.menu.UploadSpeed.512000.upload.speed=512000
 
+esp32.menu.LoopCore.1=Core 1
+esp32.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32.menu.LoopCore.0=Core 0
+esp32.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+esp32.menu.EventsCore.1=Core 1
+esp32.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+esp32.menu.EventsCore.0=Core 0
+esp32.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
 esp32.menu.DebugLevel.none=None
 esp32.menu.DebugLevel.none.build.code_debug=0
 esp32.menu.DebugLevel.error=Error
@@ -148,18 +1588,205 @@ esp32.menu.DebugLevel.debug.build.code_debug=4
 esp32.menu.DebugLevel.verbose=Verbose
 esp32.menu.DebugLevel.verbose.build.code_debug=5
 
+esp32.menu.EraseFlash.none=Disabled
+esp32.menu.EraseFlash.none.upload.erase_cmd=
+esp32.menu.EraseFlash.all=Enabled
+esp32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32.menu.ZigbeeMode.default=Disabled
+esp32.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+esp32da.name=ESP32-WROOM-DA Module
+
+esp32da.bootloader.tool=esptool_py
+esp32da.bootloader.tool.default=esptool_py
+
+esp32da.upload.tool=esptool_py
+esp32da.upload.tool.default=esptool_py
+esp32da.upload.tool.network=esp_ota
+
+esp32da.upload.maximum_size=1310720
+esp32da.upload.maximum_data_size=327680
+esp32da.upload.flags=
+esp32da.upload.extra_flags=
+
+esp32da.serial.disableDTR=true
+esp32da.serial.disableRTS=true
+
+esp32da.build.tarch=xtensa
+esp32da.build.bootloader_addr=0x1000
+esp32da.build.target=esp32
+esp32da.build.mcu=esp32
+esp32da.build.core=esp32
+esp32da.build.variant=esp32da
+esp32da.build.board=ESP32_WROOM_DA
+
+esp32da.build.f_cpu=240000000L
+esp32da.build.flash_size=4MB
+esp32da.build.flash_freq=40m
+esp32da.build.flash_mode=dio
+esp32da.build.boot=dio
+esp32da.build.partitions=default
+esp32da.build.defines=
+esp32da.build.loop_core=
+esp32da.build.event_core=
+
+esp32da.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32da.menu.PartitionScheme.default.build.partitions=default
+esp32da.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32da.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32da.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32da.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32da.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32da.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32da.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32da.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+esp32da.menu.PartitionScheme.no_fs.build.partitions=no_fs
+esp32da.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+esp32da.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32da.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32da.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32da.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32da.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32da.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32da.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32da.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32da.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32da.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32da.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32da.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32da.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32da.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32da.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32da.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32da.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32da.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32da.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32da.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32da.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32da.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32da.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32da.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32da.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32da.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32da.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32da.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32da.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32da.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32da.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32da.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32da.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32da.menu.PartitionScheme.custom=Custom
+esp32da.menu.PartitionScheme.custom.build.partitions=
+esp32da.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32da.menu.CPUFreq.240=240MHz (WiFi/BT)
+esp32da.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32da.menu.CPUFreq.160=160MHz (WiFi/BT)
+esp32da.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32da.menu.CPUFreq.80=80MHz (WiFi/BT)
+esp32da.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32da.menu.CPUFreq.40=40MHz (40MHz XTAL)
+esp32da.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32da.menu.CPUFreq.26=26MHz (26MHz XTAL)
+esp32da.menu.CPUFreq.26.build.f_cpu=26000000L
+esp32da.menu.CPUFreq.20=20MHz (40MHz XTAL)
+esp32da.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32da.menu.CPUFreq.13=13MHz (26MHz XTAL)
+esp32da.menu.CPUFreq.13.build.f_cpu=13000000L
+esp32da.menu.CPUFreq.10=10MHz (40MHz XTAL)
+esp32da.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32da.menu.FlashMode.qio=QIO
+esp32da.menu.FlashMode.qio.build.flash_mode=dio
+esp32da.menu.FlashMode.qio.build.boot=qio
+esp32da.menu.FlashMode.dio=DIO
+esp32da.menu.FlashMode.dio.build.flash_mode=dio
+esp32da.menu.FlashMode.dio.build.boot=dio
+
+esp32da.menu.FlashFreq.80=80MHz
+esp32da.menu.FlashFreq.80.build.flash_freq=80m
+esp32da.menu.FlashFreq.40=40MHz
+esp32da.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32da.menu.FlashSize.4M=4MB (32Mb)
+esp32da.menu.FlashSize.4M.build.flash_size=4MB
+esp32da.menu.FlashSize.8M=8MB (64Mb)
+esp32da.menu.FlashSize.8M.build.flash_size=8MB
+esp32da.menu.FlashSize.16M=16MB (128Mb)
+esp32da.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32da.menu.UploadSpeed.921600=921600
+esp32da.menu.UploadSpeed.921600.upload.speed=921600
+esp32da.menu.UploadSpeed.115200=115200
+esp32da.menu.UploadSpeed.115200.upload.speed=115200
+esp32da.menu.UploadSpeed.256000.windows=256000
+esp32da.menu.UploadSpeed.256000.upload.speed=256000
+esp32da.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32da.menu.UploadSpeed.230400=230400
+esp32da.menu.UploadSpeed.230400.upload.speed=230400
+esp32da.menu.UploadSpeed.460800.linux=460800
+esp32da.menu.UploadSpeed.460800.macosx=460800
+esp32da.menu.UploadSpeed.460800.upload.speed=460800
+esp32da.menu.UploadSpeed.512000.windows=512000
+esp32da.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32da.menu.LoopCore.1=Core 1
+esp32da.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32da.menu.LoopCore.0=Core 0
+esp32da.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+esp32da.menu.EventsCore.1=Core 1
+esp32da.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+esp32da.menu.EventsCore.0=Core 0
+esp32da.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+esp32da.menu.DebugLevel.none=None
+esp32da.menu.DebugLevel.none.build.code_debug=0
+esp32da.menu.DebugLevel.error=Error
+esp32da.menu.DebugLevel.error.build.code_debug=1
+esp32da.menu.DebugLevel.warn=Warn
+esp32da.menu.DebugLevel.warn.build.code_debug=2
+esp32da.menu.DebugLevel.info=Info
+esp32da.menu.DebugLevel.info.build.code_debug=3
+esp32da.menu.DebugLevel.debug=Debug
+esp32da.menu.DebugLevel.debug.build.code_debug=4
+esp32da.menu.DebugLevel.verbose=Verbose
+esp32da.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32da.menu.EraseFlash.none=Disabled
+esp32da.menu.EraseFlash.none.upload.erase_cmd=
+esp32da.menu.EraseFlash.all=Enabled
+esp32da.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 esp32wrover.name=ESP32 Wrover Module
 
+esp32wrover.bootloader.tool=esptool_py
+esp32wrover.bootloader.tool.default=esptool_py
+
 esp32wrover.upload.tool=esptool_py
+esp32wrover.upload.tool.default=esptool_py
+esp32wrover.upload.tool.network=esp_ota
+
 esp32wrover.upload.maximum_size=1310720
 esp32wrover.upload.maximum_data_size=327680
-esp32wrover.upload.wait_for_upload_port=true
+esp32wrover.upload.flags=
+esp32wrover.upload.extra_flags=
 
 esp32wrover.serial.disableDTR=true
 esp32wrover.serial.disableRTS=true
 
+esp32wrover.build.tarch=xtensa
+esp32wrover.build.bootloader_addr=0x1000
+esp32wrover.build.target=esp32
 esp32wrover.build.mcu=esp32
 esp32wrover.build.core=esp32
 esp32wrover.build.variant=esp32
@@ -171,14 +1798,16 @@ esp32wrover.build.flash_freq=40m
 esp32wrover.build.flash_mode=dio
 esp32wrover.build.boot=dio
 esp32wrover.build.partitions=default
-esp32wrover.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+esp32wrover.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+esp32wrover.build.extra_libs=
 
 esp32wrover.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
 esp32wrover.menu.PartitionScheme.default.build.partitions=default
 esp32wrover.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
 esp32wrover.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
-esp32wrover.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+esp32wrover.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
 esp32wrover.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32wrover.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
 esp32wrover.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
 esp32wrover.menu.PartitionScheme.minimal.build.partitions=minimal
 esp32wrover.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
@@ -199,8 +1828,18 @@ esp32wrover.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
 esp32wrover.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
 esp32wrover.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 esp32wrover.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-esp32wrover.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+esp32wrover.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
 esp32wrover.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32wrover.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32wrover.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32wrover.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32wrover.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32wrover.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32wrover.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32wrover.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32wrover.menu.PartitionScheme.custom=Custom
+esp32wrover.menu.PartitionScheme.custom.build.partitions=
+esp32wrover.menu.PartitionScheme.custom.upload.maximum_size=16777216
 
 esp32wrover.menu.FlashMode.qio=QIO
 esp32wrover.menu.FlashMode.qio.build.flash_mode=dio
@@ -208,12 +1847,6 @@ esp32wrover.menu.FlashMode.qio.build.boot=qio
 esp32wrover.menu.FlashMode.dio=DIO
 esp32wrover.menu.FlashMode.dio.build.flash_mode=dio
 esp32wrover.menu.FlashMode.dio.build.boot=dio
-esp32wrover.menu.FlashMode.qout=QOUT
-esp32wrover.menu.FlashMode.qout.build.flash_mode=dout
-esp32wrover.menu.FlashMode.qout.build.boot=qout
-esp32wrover.menu.FlashMode.dout=DOUT
-esp32wrover.menu.FlashMode.dout.build.flash_mode=dout
-esp32wrover.menu.FlashMode.dout.build.boot=dout
 
 esp32wrover.menu.FlashFreq.80=80MHz
 esp32wrover.menu.FlashFreq.80.build.flash_freq=80m
@@ -248,17 +1881,33 @@ esp32wrover.menu.DebugLevel.debug.build.code_debug=4
 esp32wrover.menu.DebugLevel.verbose=Verbose
 esp32wrover.menu.DebugLevel.verbose.build.code_debug=5
 
+esp32wrover.menu.EraseFlash.none=Disabled
+esp32wrover.menu.EraseFlash.none.upload.erase_cmd=
+esp32wrover.menu.EraseFlash.all=Enabled
+esp32wrover.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
-pico32.name=ESP32 Pico Kit
+
+pico32.name=ESP32 PICO-D4
+
+pico32.bootloader.tool=esptool_py
+pico32.bootloader.tool.default=esptool_py
 
 pico32.upload.tool=esptool_py
+pico32.upload.tool.default=esptool_py
+pico32.upload.tool.network=esp_ota
+
 pico32.upload.maximum_size=1310720
 pico32.upload.maximum_data_size=327680
-pico32.upload.wait_for_upload_port=true
+pico32.upload.flags=
+pico32.upload.extra_flags=
 
 pico32.serial.disableDTR=true
 pico32.serial.disableRTS=true
 
+pico32.build.tarch=xtensa
+pico32.build.bootloader_addr=0x1000
+pico32.build.target=esp32
 pico32.build.mcu=esp32
 pico32.build.core=esp32
 pico32.build.variant=pico32
@@ -280,6 +1929,9 @@ pico32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
 pico32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
 pico32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 pico32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+pico32.menu.PartitionScheme.custom=Custom
+pico32.menu.PartitionScheme.custom.build.partitions=
+pico32.menu.PartitionScheme.custom.upload.maximum_size=16777216
 
 pico32.menu.UploadSpeed.921600=921600
 pico32.menu.UploadSpeed.921600.upload.speed=921600
@@ -309,95 +1961,3336 @@ pico32.menu.DebugLevel.debug.build.code_debug=4
 pico32.menu.DebugLevel.verbose=Verbose
 pico32.menu.DebugLevel.verbose.build.code_debug=5
 
+pico32.menu.EraseFlash.none=Disabled
+pico32.menu.EraseFlash.none.upload.erase_cmd=
+pico32.menu.EraseFlash.all=Enabled
+pico32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32s3-octal.name=ESP32S3 Dev Module Octal (WROOM2)
+
+esp32s3-octal.bootloader.tool=esptool_py
+esp32s3-octal.bootloader.tool.default=esptool_py
+
+esp32s3-octal.upload.tool=esptool_py
+esp32s3-octal.upload.tool.default=esptool_py
+esp32s3-octal.upload.tool.network=esp_ota
+esp32s3-octal.upload.maximum_size=1310720
+esp32s3-octal.upload.maximum_data_size=327680
+esp32s3-octal.upload.flags=
+esp32s3-octal.upload.extra_flags=
+esp32s3-octal.upload.use_1200bps_touch=false
+esp32s3-octal.upload.wait_for_upload_port=false
+
+esp32s3-octal.serial.disableDTR=false
+esp32s3-octal.serial.disableRTS=false
+
+esp32s3-octal.build.tarch=xtensa
+esp32s3-octal.build.bootloader_addr=0x0
+esp32s3-octal.build.target=esp32s3
+esp32s3-octal.build.mcu=esp32s3
+esp32s3-octal.build.core=esp32
+esp32s3-octal.build.variant=esp32s3
+esp32s3-octal.build.board=ESP32S3_DEV
+
+esp32s3-octal.build.usb_mode=1
+esp32s3-octal.build.cdc_on_boot=0
+esp32s3-octal.build.msc_on_boot=0
+esp32s3-octal.build.dfu_on_boot=0
+esp32s3-octal.build.f_cpu=240000000L
+esp32s3-octal.build.flash_size=4MB
+esp32s3-octal.build.flash_freq=80m
+esp32s3-octal.build.flash_mode=dio
+
+esp32s3-octal.build.boot=opi
+esp32s3-octal.build.boot_freq=80m
+esp32s3-octal.build.partitions=default
+esp32s3-octal.build.defines=
+esp32s3-octal.build.loop_core=
+esp32s3-octal.build.event_core=
+esp32s3-octal.build.psram_type=opi
+esp32s3-octal.build.memory_type={build.boot}_{build.psram_type}
+
+esp32s3-octal.menu.JTAGAdapter.default=Disabled
+esp32s3-octal.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32s3-octal.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32s3-octal.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+esp32s3-octal.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32s3-octal.menu.JTAGAdapter.external=FTDI Adapter
+esp32s3-octal.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+esp32s3-octal.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32s3-octal.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32s3-octal.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+esp32s3-octal.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32s3-octal.menu.PSRAM.opi=OPI PSRAM
+esp32s3-octal.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+esp32s3-octal.menu.PSRAM.opi.build.psram_type=opi
+esp32s3-octal.menu.PSRAM.enabled=QSPI PSRAM
+esp32s3-octal.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+esp32s3-octal.menu.PSRAM.enabled.build.psram_type=qspi
+esp32s3-octal.menu.PSRAM.disabled=Disabled
+esp32s3-octal.menu.PSRAM.disabled.build.defines=
+esp32s3-octal.menu.PSRAM.disabled.build.psram_type=qspi
+
+esp32s3-octal.menu.FlashMode.opi=OPI 80MHz
+esp32s3-octal.menu.FlashMode.opi.build.flash_mode=dout
+esp32s3-octal.menu.FlashMode.opi.build.boot=opi
+esp32s3-octal.menu.FlashMode.opi.build.boot_freq=80m
+esp32s3-octal.menu.FlashMode.opi.build.flash_freq=80m
+esp32s3-octal.menu.FlashMode.qio=QIO 80MHz
+esp32s3-octal.menu.FlashMode.qio.build.flash_mode=dio
+esp32s3-octal.menu.FlashMode.qio.build.boot=qio
+esp32s3-octal.menu.FlashMode.qio.build.boot_freq=80m
+esp32s3-octal.menu.FlashMode.qio.build.flash_freq=80m
+esp32s3-octal.menu.FlashMode.qio120=QIO 120MHz
+esp32s3-octal.menu.FlashMode.qio120.build.flash_mode=dio
+esp32s3-octal.menu.FlashMode.qio120.build.boot=qio
+esp32s3-octal.menu.FlashMode.qio120.build.boot_freq=120m
+esp32s3-octal.menu.FlashMode.qio120.build.flash_freq=80m
+esp32s3-octal.menu.FlashMode.dio=DIO 80MHz
+esp32s3-octal.menu.FlashMode.dio.build.flash_mode=dio
+esp32s3-octal.menu.FlashMode.dio.build.boot=dio
+esp32s3-octal.menu.FlashMode.dio.build.boot_freq=80m
+esp32s3-octal.menu.FlashMode.dio.build.flash_freq=80m
+
+esp32s3-octal.menu.FlashSize.16M=16MB (128Mb)
+esp32s3-octal.menu.FlashSize.4M=4MB (32Mb)
+esp32s3-octal.menu.FlashSize.4M.build.flash_size=4MB
+esp32s3-octal.menu.FlashSize.8M=8MB (64Mb)
+esp32s3-octal.menu.FlashSize.8M.build.flash_size=8MB
+esp32s3-octal.menu.FlashSize.16M=16MB (128Mb)
+esp32s3-octal.menu.FlashSize.16M.build.flash_size=16MB
+esp32s3-octal.menu.FlashSize.32M=32MB (256Mb)
+esp32s3-octal.menu.FlashSize.32M.build.flash_size=32MB
+
+esp32s3-octal.menu.LoopCore.1=Core 1
+esp32s3-octal.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32s3-octal.menu.LoopCore.0=Core 0
+esp32s3-octal.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+esp32s3-octal.menu.EventsCore.1=Core 1
+esp32s3-octal.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+esp32s3-octal.menu.EventsCore.0=Core 0
+esp32s3-octal.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+esp32s3-octal.menu.USBMode.hwcdc=Hardware CDC and JTAG
+esp32s3-octal.menu.USBMode.hwcdc.build.usb_mode=1
+esp32s3-octal.menu.USBMode.default=USB-OTG (TinyUSB)
+esp32s3-octal.menu.USBMode.default.build.usb_mode=0
+
+esp32s3-octal.menu.CDCOnBoot.default=Disabled
+esp32s3-octal.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32s3-octal.menu.CDCOnBoot.cdc=Enabled
+esp32s3-octal.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32s3-octal.menu.MSCOnBoot.default=Disabled
+esp32s3-octal.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32s3-octal.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+esp32s3-octal.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32s3-octal.menu.DFUOnBoot.default=Disabled
+esp32s3-octal.menu.DFUOnBoot.default.build.dfu_on_boot=0
+esp32s3-octal.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+esp32s3-octal.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+esp32s3-octal.menu.UploadMode.default=UART0 / Hardware CDC
+esp32s3-octal.menu.UploadMode.default.upload.use_1200bps_touch=false
+esp32s3-octal.menu.UploadMode.default.upload.wait_for_upload_port=false
+esp32s3-octal.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+esp32s3-octal.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+esp32s3-octal.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+esp32s3-octal.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s3-octal.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s3-octal.menu.PartitionScheme.default.build.partitions=default
+esp32s3-octal.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s3-octal.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s3-octal.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s3-octal.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s3-octal.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s3-octal.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32s3-octal.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32s3-octal.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s3-octal.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s3-octal.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s3-octal.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s3-octal.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s3-octal.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s3-octal.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s3-octal.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s3-octal.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s3-octal.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s3-octal.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s3-octal.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s3-octal.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s3-octal.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s3-octal.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s3-octal.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s3-octal.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s3-octal.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s3-octal.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32s3-octal.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s3-octal.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s3-octal.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s3-octal.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s3-octal.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32s3-octal.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32s3-octal.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32s3-octal.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32s3-octal.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32s3-octal.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32s3-octal.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32s3-octal.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32s3-octal.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32s3-octal.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32s3-octal.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+esp32s3-octal.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+esp32s3-octal.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+esp32s3-octal.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+esp32s3-octal.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+esp32s3-octal.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+esp32s3-octal.menu.PartitionScheme.app13M_data7M_32MB=32M Flash (13MB APP/6.75MB SPIFFS)
+esp32s3-octal.menu.PartitionScheme.app13M_data7M_32MB.build.partitions=default_32MB
+esp32s3-octal.menu.PartitionScheme.app13M_data7M_32MB.upload.maximum_size=13107200
+
+esp32s3-octal.menu.CPUFreq.240=240MHz (WiFi)
+esp32s3-octal.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32s3-octal.menu.CPUFreq.160=160MHz (WiFi)
+esp32s3-octal.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32s3-octal.menu.CPUFreq.80=80MHz (WiFi)
+esp32s3-octal.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32s3-octal.menu.CPUFreq.40=40MHz
+esp32s3-octal.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32s3-octal.menu.CPUFreq.20=20MHz
+esp32s3-octal.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32s3-octal.menu.CPUFreq.10=10MHz
+esp32s3-octal.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32s3-octal.menu.UploadSpeed.921600=921600
+esp32s3-octal.menu.UploadSpeed.921600.upload.speed=921600
+esp32s3-octal.menu.UploadSpeed.115200=115200
+esp32s3-octal.menu.UploadSpeed.115200.upload.speed=115200
+esp32s3-octal.menu.UploadSpeed.256000.windows=256000
+esp32s3-octal.menu.UploadSpeed.256000.upload.speed=256000
+esp32s3-octal.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32s3-octal.menu.UploadSpeed.230400=230400
+esp32s3-octal.menu.UploadSpeed.230400.upload.speed=230400
+esp32s3-octal.menu.UploadSpeed.460800.linux=460800
+esp32s3-octal.menu.UploadSpeed.460800.macosx=460800
+esp32s3-octal.menu.UploadSpeed.460800.upload.speed=460800
+esp32s3-octal.menu.UploadSpeed.512000.windows=512000
+esp32s3-octal.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32s3-octal.menu.DebugLevel.none=None
+esp32s3-octal.menu.DebugLevel.none.build.code_debug=0
+esp32s3-octal.menu.DebugLevel.error=Error
+esp32s3-octal.menu.DebugLevel.error.build.code_debug=1
+esp32s3-octal.menu.DebugLevel.warn=Warn
+esp32s3-octal.menu.DebugLevel.warn.build.code_debug=2
+esp32s3-octal.menu.DebugLevel.info=Info
+esp32s3-octal.menu.DebugLevel.info.build.code_debug=3
+esp32s3-octal.menu.DebugLevel.debug=Debug
+esp32s3-octal.menu.DebugLevel.debug.build.code_debug=4
+esp32s3-octal.menu.DebugLevel.verbose=Verbose
+esp32s3-octal.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s3-octal.menu.EraseFlash.none=Disabled
+esp32s3-octal.menu.EraseFlash.none.upload.erase_cmd=
+esp32s3-octal.menu.EraseFlash.all=Enabled
+esp32s3-octal.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32s3box.name=ESP32-S3-Box
+
+esp32s3box.bootloader.tool=esptool_py
+esp32s3box.bootloader.tool.default=esptool_py
+
+esp32s3box.upload.tool=esptool_py
+esp32s3box.upload.tool.default=esptool_py
+esp32s3box.upload.tool.network=esp_ota
+
+esp32s3box.upload.maximum_size=3145728
+esp32s3box.upload.maximum_data_size=327680
+esp32s3box.upload.speed=921600
+esp32s3box.upload.flags=
+esp32s3box.upload.extra_flags=
+esp32s3box.upload.use_1200bps_touch=false
+esp32s3box.upload.wait_for_upload_port=false
+
+esp32s3box.serial.disableDTR=false
+esp32s3box.serial.disableRTS=false
+
+esp32s3box.build.tarch=xtensa
+esp32s3box.build.bootloader_addr=0x0
+esp32s3box.build.target=esp32s3
+esp32s3box.build.mcu=esp32s3
+esp32s3box.build.core=esp32
+esp32s3box.build.variant=esp32s3box
+esp32s3box.build.board=ESP32_S3_BOX
+
+esp32s3box.build.usb_mode=1
+esp32s3box.build.cdc_on_boot=1
+esp32s3box.build.msc_on_boot=0
+esp32s3box.build.dfu_on_boot=0
+esp32s3box.build.f_cpu=240000000L
+esp32s3box.build.flash_size=16MB
+esp32s3box.build.flash_freq=80m
+esp32s3box.build.flash_mode=dio
+esp32s3box.build.boot=qio
+esp32s3box.build.partitions=default
+esp32s3box.build.defines=-DBOARD_HAS_PSRAM
+esp32s3box.build.memory_type=qio_opi
+esp32s3box.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32s3box.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+esp32s3box.menu.USBMode.hwcdc=Hardware CDC and JTAG
+esp32s3box.menu.USBMode.hwcdc.build.usb_mode=1
+esp32s3box.menu.USBMode.hwcdc.upload.use_1200bps_touch=false
+esp32s3box.menu.USBMode.hwcdc.upload.wait_for_upload_port=false
+esp32s3box.menu.USBMode.default=USB-OTG
+esp32s3box.menu.USBMode.default.build.usb_mode=0
+esp32s3box.menu.USBMode.default.upload.use_1200bps_touch=true
+esp32s3box.menu.USBMode.default.upload.wait_for_upload_port=true
+
+esp32s3box.menu.MSCOnBoot.default=Disabled
+esp32s3box.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32s3box.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+esp32s3box.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32s3box.menu.DFUOnBoot.default=Disabled
+esp32s3box.menu.DFUOnBoot.default.build.dfu_on_boot=0
+esp32s3box.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+esp32s3box.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+esp32s3box.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s3box.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s3box.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32s3box.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32s3box.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32s3box.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32s3box.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32s3box.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32s3box.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32s3box.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+esp32s3box.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+esp32s3box.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+esp32s3box.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+esp32s3box.menu.PartitionScheme.custom=Custom
+esp32s3box.menu.PartitionScheme.custom.build.partitions=
+esp32s3box.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32s3box.menu.DebugLevel.none=None
+esp32s3box.menu.DebugLevel.none.build.code_debug=0
+esp32s3box.menu.DebugLevel.error=Error
+esp32s3box.menu.DebugLevel.error.build.code_debug=1
+esp32s3box.menu.DebugLevel.warn=Warn
+esp32s3box.menu.DebugLevel.warn.build.code_debug=2
+esp32s3box.menu.DebugLevel.info=Info
+esp32s3box.menu.DebugLevel.info.build.code_debug=3
+esp32s3box.menu.DebugLevel.debug=Debug
+esp32s3box.menu.DebugLevel.debug.build.code_debug=4
+esp32s3box.menu.DebugLevel.verbose=Verbose
+esp32s3box.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s3box.menu.EraseFlash.none=Disabled
+esp32s3box.menu.EraseFlash.none.upload.erase_cmd=
+esp32s3box.menu.EraseFlash.all=Enabled
+esp32s3box.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32s3usbotg.name=ESP32-S3-USB-OTG
+
+esp32s3usbotg.bootloader.tool=esptool_py
+esp32s3usbotg.bootloader.tool.default=esptool_py
+
+esp32s3usbotg.upload.tool=esptool_py
+esp32s3usbotg.upload.tool.default=esptool_py
+esp32s3usbotg.upload.tool.network=esp_ota
+
+esp32s3usbotg.upload.maximum_size=1310720
+esp32s3usbotg.upload.maximum_data_size=327680
+esp32s3usbotg.upload.speed=921600
+esp32s3usbotg.upload.flags=
+esp32s3usbotg.upload.extra_flags=
+esp32s3usbotg.upload.use_1200bps_touch=false
+esp32s3usbotg.upload.wait_for_upload_port=false
+
+esp32s3usbotg.serial.disableDTR=false
+esp32s3usbotg.serial.disableRTS=false
+
+esp32s3usbotg.build.tarch=xtensa
+esp32s3usbotg.build.bootloader_addr=0x0
+esp32s3usbotg.build.target=esp32s3
+esp32s3usbotg.build.mcu=esp32s3
+esp32s3usbotg.build.core=esp32
+esp32s3usbotg.build.variant=esp32s3usbotg
+esp32s3usbotg.build.board=ESP32_S3_USB_OTG
+
+esp32s3usbotg.build.usb_mode=0
+esp32s3usbotg.build.cdc_on_boot=0
+esp32s3usbotg.build.msc_on_boot=0
+esp32s3usbotg.build.dfu_on_boot=0
+esp32s3usbotg.build.f_cpu=240000000L
+esp32s3usbotg.build.flash_size=8MB
+esp32s3usbotg.build.flash_freq=80m
+esp32s3usbotg.build.flash_mode=dio
+esp32s3usbotg.build.boot=qio
+esp32s3usbotg.build.partitions=default
+esp32s3usbotg.build.defines=
+esp32s3usbotg.build.memory_type=qio_qspi
+esp32s3usbotg.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32s3usbotg.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+esp32s3usbotg.menu.USBMode.default=USB-OTG
+esp32s3usbotg.menu.USBMode.default.build.usb_mode=0
+esp32s3usbotg.menu.USBMode.default.build.cdc_on_boot=0
+esp32s3usbotg.menu.USBMode.hwcdc=Hardware CDC and JTAG
+esp32s3usbotg.menu.USBMode.hwcdc.build.usb_mode=1
+esp32s3usbotg.menu.USBMode.hwcdc.build.cdc_on_boot=1
+
+esp32s3usbotg.menu.UploadMode.default=UART0 / Hardware CDC
+esp32s3usbotg.menu.UploadMode.default.upload.use_1200bps_touch=false
+esp32s3usbotg.menu.UploadMode.default.upload.wait_for_upload_port=false
+esp32s3usbotg.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+esp32s3usbotg.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+esp32s3usbotg.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+esp32s3usbotg.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s3usbotg.menu.PartitionScheme.default.build.partitions=default
+esp32s3usbotg.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s3usbotg.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s3usbotg.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s3usbotg.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s3usbotg.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s3usbotg.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s3usbotg.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s3usbotg.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s3usbotg.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s3usbotg.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s3usbotg.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s3usbotg.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s3usbotg.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s3usbotg.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s3usbotg.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s3usbotg.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s3usbotg.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s3usbotg.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s3usbotg.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s3usbotg.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s3usbotg.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s3usbotg.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s3usbotg.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s3usbotg.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32s3usbotg.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s3usbotg.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s3usbotg.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s3usbotg.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s3usbotg.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32s3usbotg.menu.PartitionScheme.custom=Custom
+esp32s3usbotg.menu.PartitionScheme.custom.build.partitions=
+esp32s3usbotg.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32s3usbotg.menu.DebugLevel.none=None
+esp32s3usbotg.menu.DebugLevel.none.build.code_debug=0
+esp32s3usbotg.menu.DebugLevel.error=Error
+esp32s3usbotg.menu.DebugLevel.error.build.code_debug=1
+esp32s3usbotg.menu.DebugLevel.warn=Warn
+esp32s3usbotg.menu.DebugLevel.warn.build.code_debug=2
+esp32s3usbotg.menu.DebugLevel.info=Info
+esp32s3usbotg.menu.DebugLevel.info.build.code_debug=3
+esp32s3usbotg.menu.DebugLevel.debug=Debug
+esp32s3usbotg.menu.DebugLevel.debug.build.code_debug=4
+esp32s3usbotg.menu.DebugLevel.verbose=Verbose
+esp32s3usbotg.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s3usbotg.menu.EraseFlash.none=Disabled
+esp32s3usbotg.menu.EraseFlash.none.upload.erase_cmd=
+esp32s3usbotg.menu.EraseFlash.all=Enabled
+esp32s3usbotg.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32s3camlcd.name=ESP32S3 CAM LCD
+
+esp32s3camlcd.bootloader.tool=esptool_py
+esp32s3camlcd.bootloader.tool.default=esptool_py
+
+esp32s3camlcd.upload.tool=esptool_py
+esp32s3camlcd.upload.tool.default=esptool_py
+esp32s3camlcd.upload.tool.network=esp_ota
+
+esp32s3camlcd.upload.maximum_size=1310720
+esp32s3camlcd.upload.maximum_data_size=327680
+esp32s3camlcd.upload.flags=
+esp32s3camlcd.upload.extra_flags=
+esp32s3camlcd.upload.use_1200bps_touch=false
+esp32s3camlcd.upload.wait_for_upload_port=false
+
+esp32s3camlcd.serial.disableDTR=false
+esp32s3camlcd.serial.disableRTS=false
+
+esp32s3camlcd.build.tarch=xtensa
+esp32s3camlcd.build.bootloader_addr=0x0
+esp32s3camlcd.build.target=esp32s3
+esp32s3camlcd.build.mcu=esp32s3
+esp32s3camlcd.build.core=esp32
+esp32s3camlcd.build.variant=esp32s3camlcd
+esp32s3camlcd.build.board=ESP32S3_CAM_LCD
+
+esp32s3camlcd.build.usb_mode=1
+esp32s3camlcd.build.cdc_on_boot=0
+esp32s3camlcd.build.msc_on_boot=0
+esp32s3camlcd.build.dfu_on_boot=0
+esp32s3camlcd.build.f_cpu=240000000L
+esp32s3camlcd.build.flash_size=4MB
+esp32s3camlcd.build.flash_freq=80m
+esp32s3camlcd.build.flash_mode=dout
+esp32s3camlcd.build.boot=opi
+esp32s3camlcd.build.partitions=default
+esp32s3camlcd.build.defines=-DBOARD_HAS_PSRAM
+esp32s3camlcd.build.memory_type=opi_opi
+esp32s3camlcd.build.loop_core=
+esp32s3camlcd.build.event_core=
+
+esp32s3camlcd.menu.LoopCore.1=Core 1
+esp32s3camlcd.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32s3camlcd.menu.LoopCore.0=Core 0
+esp32s3camlcd.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+esp32s3camlcd.menu.EventsCore.1=Core 1
+esp32s3camlcd.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+esp32s3camlcd.menu.EventsCore.0=Core 0
+esp32s3camlcd.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+esp32s3camlcd.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s3camlcd.menu.PartitionScheme.default.build.partitions=default
+esp32s3camlcd.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s3camlcd.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s3camlcd.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s3camlcd.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s3camlcd.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s3camlcd.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32s3camlcd.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32s3camlcd.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s3camlcd.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s3camlcd.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s3camlcd.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s3camlcd.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s3camlcd.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s3camlcd.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s3camlcd.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s3camlcd.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s3camlcd.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s3camlcd.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s3camlcd.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s3camlcd.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s3camlcd.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s3camlcd.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s3camlcd.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s3camlcd.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s3camlcd.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s3camlcd.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32s3camlcd.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s3camlcd.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s3camlcd.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s3camlcd.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s3camlcd.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+esp32s3camlcd.menu.UploadSpeed.921600=921600
+esp32s3camlcd.menu.UploadSpeed.921600.upload.speed=921600
+esp32s3camlcd.menu.UploadSpeed.115200=115200
+esp32s3camlcd.menu.UploadSpeed.115200.upload.speed=115200
+esp32s3camlcd.menu.UploadSpeed.256000.windows=256000
+esp32s3camlcd.menu.UploadSpeed.256000.upload.speed=256000
+esp32s3camlcd.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32s3camlcd.menu.UploadSpeed.230400=230400
+esp32s3camlcd.menu.UploadSpeed.230400.upload.speed=230400
+esp32s3camlcd.menu.UploadSpeed.460800.linux=460800
+esp32s3camlcd.menu.UploadSpeed.460800.macosx=460800
+esp32s3camlcd.menu.UploadSpeed.460800.upload.speed=460800
+esp32s3camlcd.menu.UploadSpeed.512000.windows=512000
+esp32s3camlcd.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32s3camlcd.menu.DebugLevel.none=None
+esp32s3camlcd.menu.DebugLevel.none.build.code_debug=0
+esp32s3camlcd.menu.DebugLevel.error=Error
+esp32s3camlcd.menu.DebugLevel.error.build.code_debug=1
+esp32s3camlcd.menu.DebugLevel.warn=Warn
+esp32s3camlcd.menu.DebugLevel.warn.build.code_debug=2
+esp32s3camlcd.menu.DebugLevel.info=Info
+esp32s3camlcd.menu.DebugLevel.info.build.code_debug=3
+esp32s3camlcd.menu.DebugLevel.debug=Debug
+esp32s3camlcd.menu.DebugLevel.debug.build.code_debug=4
+esp32s3camlcd.menu.DebugLevel.verbose=Verbose
+esp32s3camlcd.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s3camlcd.menu.EraseFlash.none=Disabled
+esp32s3camlcd.menu.EraseFlash.none.upload.erase_cmd=
+esp32s3camlcd.menu.EraseFlash.all=Enabled
+esp32s3camlcd.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32s2usb.name=ESP32S2 Native USB
+esp32s2usb.vid.0=0x303a
+esp32s2usb.pid.0=0x0003
+esp32s2usb.upload_port.vid.0=0x303a
+esp32s2usb.upload_port.pid.0=0x0003
+
+esp32s2usb.bootloader.tool=esptool_py
+esp32s2usb.bootloader.tool.default=esptool_py
+
+esp32s2usb.upload.tool=esptool_py
+esp32s2usb.upload.tool.default=esptool_py
+esp32s2usb.upload.tool.network=esp_ota
+
+esp32s2usb.upload.maximum_size=1310720
+esp32s2usb.upload.maximum_data_size=327680
+esp32s2usb.upload.flags=
+esp32s2usb.upload.extra_flags=
+esp32s2usb.upload.use_1200bps_touch=true
+esp32s2usb.upload.wait_for_upload_port=true
+esp32s2usb.upload.speed=921600
+
+esp32s2usb.serial.disableDTR=false
+esp32s2usb.serial.disableRTS=false
+
+esp32s2usb.build.tarch=xtensa
+esp32s2usb.build.bootloader_addr=0x1000
+esp32s2usb.build.target=esp32s2
+esp32s2usb.build.mcu=esp32s2
+esp32s2usb.build.core=esp32
+esp32s2usb.build.variant=esp32s2usb
+esp32s2usb.build.board=ESP32S2_USB
+
+esp32s2usb.build.cdc_on_boot=1
+esp32s2usb.build.msc_on_boot=1
+esp32s2usb.build.dfu_on_boot=1
+esp32s2usb.build.f_cpu=240000000L
+esp32s2usb.build.flash_size=4MB
+esp32s2usb.build.flash_freq=80m
+esp32s2usb.build.flash_mode=dio
+esp32s2usb.build.boot=qio
+esp32s2usb.build.partitions=default
+esp32s2usb.build.defines=
+
+esp32s2usb.menu.PSRAM.disabled=Disabled
+esp32s2usb.menu.PSRAM.disabled.build.defines=
+esp32s2usb.menu.PSRAM.enabled=Enabled
+esp32s2usb.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+esp32s2usb.menu.FlashSize.4M=4MB (32Mb)
+esp32s2usb.menu.FlashSize.4M.build.flash_size=4MB
+esp32s2usb.menu.FlashSize.8M=8MB (64Mb)
+esp32s2usb.menu.FlashSize.8M.build.flash_size=8MB
+esp32s2usb.menu.FlashSize.16M=16MB (128Mb)
+esp32s2usb.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32s2usb.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s2usb.menu.PartitionScheme.default.build.partitions=default
+esp32s2usb.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s2usb.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s2usb.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s2usb.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s2usb.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s2usb.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32s2usb.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32s2usb.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s2usb.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s2usb.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s2usb.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s2usb.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s2usb.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s2usb.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s2usb.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s2usb.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s2usb.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s2usb.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s2usb.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s2usb.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s2usb.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s2usb.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s2usb.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s2usb.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s2usb.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s2usb.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32s2usb.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s2usb.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s2usb.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s2usb.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s2usb.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+esp32s2usb.menu.DebugLevel.none=None
+esp32s2usb.menu.DebugLevel.none.build.code_debug=0
+esp32s2usb.menu.DebugLevel.error=Error
+esp32s2usb.menu.DebugLevel.error.build.code_debug=1
+esp32s2usb.menu.DebugLevel.warn=Warn
+esp32s2usb.menu.DebugLevel.warn.build.code_debug=2
+esp32s2usb.menu.DebugLevel.info=Info
+esp32s2usb.menu.DebugLevel.info.build.code_debug=3
+esp32s2usb.menu.DebugLevel.debug=Debug
+esp32s2usb.menu.DebugLevel.debug.build.code_debug=4
+esp32s2usb.menu.DebugLevel.verbose=Verbose
+esp32s2usb.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s2usb.menu.EraseFlash.none=Disabled
+esp32s2usb.menu.EraseFlash.none.upload.erase_cmd=
+esp32s2usb.menu.EraseFlash.all=Enabled
+esp32s2usb.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32wroverkit.name=ESP32 Wrover Kit (all versions)
+
+esp32wroverkit.bootloader.tool=esptool_py
+esp32wroverkit.bootloader.tool.default=esptool_py
+
+esp32wroverkit.upload.tool=esptool_py
+esp32wroverkit.upload.tool.default=esptool_py
+esp32wroverkit.upload.tool.network=esp_ota
+
+esp32wroverkit.upload.maximum_size=1310720
+esp32wroverkit.upload.maximum_data_size=327680
+esp32wroverkit.upload.flags=
+esp32wroverkit.upload.extra_flags=
+
+esp32wroverkit.serial.disableDTR=true
+esp32wroverkit.serial.disableRTS=true
+
+esp32wroverkit.build.tarch=xtensa
+esp32wroverkit.build.bootloader_addr=0x1000
+esp32wroverkit.build.target=esp32
+esp32wroverkit.build.mcu=esp32
+esp32wroverkit.build.core=esp32
+esp32wroverkit.build.variant=esp32
+esp32wroverkit.build.board=ESP32_WROVER_KIT
+
+esp32wroverkit.build.f_cpu=240000000L
+esp32wroverkit.build.flash_size=4MB
+esp32wroverkit.build.flash_freq=40m
+esp32wroverkit.build.flash_mode=dio
+esp32wroverkit.build.boot=dio
+esp32wroverkit.build.partitions=default
+
+esp32wroverkit.menu.FlashSize.4M=4MB (32Mb)
+esp32wroverkit.menu.FlashSize.4M.build.flash_size=4MB
+esp32wroverkit.menu.FlashSize.8M=8MB (64Mb)
+esp32wroverkit.menu.FlashSize.8M.build.flash_size=8MB
+esp32wroverkit.menu.FlashSize.2M=2MB (16Mb)
+esp32wroverkit.menu.FlashSize.2M.build.flash_size=2MB
+esp32wroverkit.menu.FlashSize.16M=16MB (128Mb)
+esp32wroverkit.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32wroverkit.menu.PSRAM.enabled=Enabled
+esp32wroverkit.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+esp32wroverkit.menu.PSRAM.disabled=Disabled
+esp32wroverkit.menu.PSRAM.disabled.build.defines=
+
+esp32wroverkit.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32wroverkit.menu.PartitionScheme.default.build.partitions=default
+esp32wroverkit.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32wroverkit.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32wroverkit.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32wroverkit.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32wroverkit.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32wroverkit.menu.PartitionScheme.default_16MB=16M with spiffs (6.25MB APP/3.43MB SPIFFS)
+esp32wroverkit.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
+esp32wroverkit.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
+esp32wroverkit.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32wroverkit.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32wroverkit.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32wroverkit.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32wroverkit.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32wroverkit.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32wroverkit.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32wroverkit.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32wroverkit.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32wroverkit.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32wroverkit.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32wroverkit.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32wroverkit.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32wroverkit.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32wroverkit.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32wroverkit.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32wroverkit.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32wroverkit.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32wroverkit.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32wroverkit.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32wroverkit.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32wroverkit.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32wroverkit.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32wroverkit.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32wroverkit.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32wroverkit.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32wroverkit.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32wroverkit.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32wroverkit.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32wroverkit.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32wroverkit.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32wroverkit.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+esp32wroverkit.menu.CPUFreq.240=240MHz (WiFi/BT)
+esp32wroverkit.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32wroverkit.menu.CPUFreq.160=160MHz (WiFi/BT)
+esp32wroverkit.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32wroverkit.menu.CPUFreq.80=80MHz (WiFi/BT)
+esp32wroverkit.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32wroverkit.menu.CPUFreq.40=40MHz (40MHz XTAL)
+esp32wroverkit.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32wroverkit.menu.CPUFreq.26=26MHz (26MHz XTAL)
+esp32wroverkit.menu.CPUFreq.26.build.f_cpu=26000000L
+esp32wroverkit.menu.CPUFreq.20=20MHz (40MHz XTAL)
+esp32wroverkit.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32wroverkit.menu.CPUFreq.13=13MHz (26MHz XTAL)
+esp32wroverkit.menu.CPUFreq.13.build.f_cpu=13000000L
+esp32wroverkit.menu.CPUFreq.10=10MHz (40MHz XTAL)
+esp32wroverkit.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32wroverkit.menu.FlashMode.qio=QIO
+esp32wroverkit.menu.FlashMode.qio.build.flash_mode=dio
+esp32wroverkit.menu.FlashMode.qio.build.boot=qio
+esp32wroverkit.menu.FlashMode.dio=DIO
+esp32wroverkit.menu.FlashMode.dio.build.flash_mode=dio
+esp32wroverkit.menu.FlashMode.dio.build.boot=dio
+esp32wroverkit.menu.FlashFreq.80=80MHz
+esp32wroverkit.menu.FlashFreq.80.build.flash_freq=80m
+esp32wroverkit.menu.FlashFreq.40=40MHz
+esp32wroverkit.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32wroverkit.menu.UploadSpeed.921600=921600
+esp32wroverkit.menu.UploadSpeed.921600.upload.speed=921600
+esp32wroverkit.menu.UploadSpeed.115200=115200
+esp32wroverkit.menu.UploadSpeed.115200.upload.speed=115200
+esp32wroverkit.menu.UploadSpeed.256000.windows=256000
+esp32wroverkit.menu.UploadSpeed.256000.upload.speed=256000
+esp32wroverkit.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32wroverkit.menu.UploadSpeed.230400=230400
+esp32wroverkit.menu.UploadSpeed.230400.upload.speed=230400
+esp32wroverkit.menu.UploadSpeed.460800.linux=460800
+esp32wroverkit.menu.UploadSpeed.460800.macosx=460800
+esp32wroverkit.menu.UploadSpeed.460800.upload.speed=460800
+esp32wroverkit.menu.UploadSpeed.512000.windows=512000
+esp32wroverkit.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32wroverkit.menu.DebugLevel.none=None
+esp32wroverkit.menu.DebugLevel.none.build.code_debug=0
+esp32wroverkit.menu.DebugLevel.error=Error
+esp32wroverkit.menu.DebugLevel.error.build.code_debug=1
+esp32wroverkit.menu.DebugLevel.warn=Warn
+esp32wroverkit.menu.DebugLevel.warn.build.code_debug=2
+esp32wroverkit.menu.DebugLevel.info=Info
+esp32wroverkit.menu.DebugLevel.info.build.code_debug=3
+esp32wroverkit.menu.DebugLevel.debug=Debug
+esp32wroverkit.menu.DebugLevel.debug.build.code_debug=4
+esp32wroverkit.menu.DebugLevel.verbose=Verbose
+esp32wroverkit.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32wroverkit.menu.EraseFlash.none=Disabled
+esp32wroverkit.menu.EraseFlash.none.upload.erase_cmd=
+esp32wroverkit.menu.EraseFlash.all=Enabled
+esp32wroverkit.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+aventen_s3_sync.name=Aventen S3 Sync
+## Based upon ESP32-S3 Dev Board
+
+aventen_s3_sync.bootloader.tool=esptool_py
+aventen_s3_sync.bootloader.tool.default=esptool_py
+
+aventen_s3_sync.upload.tool=esptool_py
+aventen_s3_sync.upload.tool.default=esptool_py
+aventen_s3_sync.upload.tool.network=esp_ota
+
+aventen_s3_sync.upload.maximum_size=1310720
+aventen_s3_sync.upload.maximum_data_size=327680
+aventen_s3_sync.upload.flags=
+aventen_s3_sync.upload.extra_flags=
+aventen_s3_sync.upload.use_1200bps_touch=false
+aventen_s3_sync.upload.wait_for_upload_port=false
+
+aventen_s3_sync.serial.disableDTR=false
+aventen_s3_sync.serial.disableRTS=false
+
+aventen_s3_sync.build.tarch=xtensa
+aventen_s3_sync.build.bootloader_addr=0x0
+aventen_s3_sync.build.target=esp32s3
+aventen_s3_sync.build.mcu=esp32s3
+aventen_s3_sync.build.core=esp32
+aventen_s3_sync.build.variant=Aventen_S3_Sync
+aventen_s3_sync.build.board=AVENTEN_S3_SYNC
+
+aventen_s3_sync.build.usb_mode=1
+aventen_s3_sync.build.cdc_on_boot=0
+aventen_s3_sync.build.msc_on_boot=0
+aventen_s3_sync.build.dfu_on_boot=0
+aventen_s3_sync.build.f_cpu=240000000L
+aventen_s3_sync.build.flash_size=16MB
+aventen_s3_sync.build.flash_freq=80m
+aventen_s3_sync.build.flash_mode=dio
+aventen_s3_sync.build.boot=qio
+aventen_s3_sync.build.boot_freq=80m
+aventen_s3_sync.build.partitions=default
+aventen_s3_sync.build.defines=
+aventen_s3_sync.build.loop_core=
+aventen_s3_sync.build.event_core=
+aventen_s3_sync.build.psram_type=qspi
+aventen_s3_sync.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0
+aventen_s3_sync.menu.JTAGAdapter.default=Disabled
+aventen_s3_sync.menu.JTAGAdapter.default.build.copy_jtag_files=0
+aventen_s3_sync.menu.JTAGAdapter.builtin=Integrated USB JTAG
+aventen_s3_sync.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+aventen_s3_sync.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+aventen_s3_sync.menu.JTAGAdapter.external=FTDI Adapter
+aventen_s3_sync.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+aventen_s3_sync.menu.JTAGAdapter.external.build.copy_jtag_files=1
+aventen_s3_sync.menu.JTAGAdapter.bridge=ESP USB Bridge
+aventen_s3_sync.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+aventen_s3_sync.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+aventen_s3_sync.menu.PSRAM.disabled=Disabled
+aventen_s3_sync.menu.PSRAM.disabled.build.defines=
+aventen_s3_sync.menu.PSRAM.disabled.build.psram_type=qspi
+aventen_s3_sync.menu.PSRAM.enabled=QSPI PSRAM
+aventen_s3_sync.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+aventen_s3_sync.menu.PSRAM.enabled.build.psram_type=qspi
+aventen_s3_sync.menu.PSRAM.opi=OPI PSRAM
+aventen_s3_sync.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+aventen_s3_sync.menu.PSRAM.opi.build.psram_type=opi
+
+aventen_s3_sync.menu.FlashMode.qio=QIO 80MHz
+aventen_s3_sync.menu.FlashMode.qio.build.flash_mode=dio
+aventen_s3_sync.menu.FlashMode.qio.build.boot=qio
+aventen_s3_sync.menu.FlashMode.qio.build.boot_freq=80m
+aventen_s3_sync.menu.FlashMode.qio.build.flash_freq=80m
+aventen_s3_sync.menu.FlashMode.qio120=QIO 120MHz
+aventen_s3_sync.menu.FlashMode.qio120.build.flash_mode=dio
+aventen_s3_sync.menu.FlashMode.qio120.build.boot=qio
+aventen_s3_sync.menu.FlashMode.qio120.build.boot_freq=120m
+aventen_s3_sync.menu.FlashMode.qio120.build.flash_freq=80m
+aventen_s3_sync.menu.FlashMode.dio=DIO 80MHz
+aventen_s3_sync.menu.FlashMode.dio.build.flash_mode=dio
+aventen_s3_sync.menu.FlashMode.dio.build.boot=dio
+aventen_s3_sync.menu.FlashMode.dio.build.boot_freq=80m
+aventen_s3_sync.menu.FlashMode.dio.build.flash_freq=80m
+aventen_s3_sync.menu.FlashMode.opi=OPI 80MHz
+aventen_s3_sync.menu.FlashMode.opi.build.flash_mode=dout
+aventen_s3_sync.menu.FlashMode.opi.build.boot=opi
+aventen_s3_sync.menu.FlashMode.opi.build.boot_freq=80m
+aventen_s3_sync.menu.FlashMode.opi.build.flash_freq=80m
+
+aventen_s3_sync.menu.FlashSize.16M=16MB (128Mb)
+aventen_s3_sync.menu.FlashSize.16M.build.flash_size=16MB
+
+aventen_s3_sync.menu.LoopCore.1=Core 1
+aventen_s3_sync.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+aventen_s3_sync.menu.LoopCore.0=Core 0
+aventen_s3_sync.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+aventen_s3_sync.menu.EventsCore.1=Core 1
+aventen_s3_sync.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+aventen_s3_sync.menu.EventsCore.0=Core 0
+aventen_s3_sync.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+aventen_s3_sync.menu.USBMode.hwcdc=Hardware CDC and JTAG
+aventen_s3_sync.menu.USBMode.hwcdc.build.usb_mode=1
+aventen_s3_sync.menu.USBMode.default=USB-OTG (TinyUSB)
+aventen_s3_sync.menu.USBMode.default.build.usb_mode=0
+
+aventen_s3_sync.menu.CDCOnBoot.default=Disabled
+aventen_s3_sync.menu.CDCOnBoot.default.build.cdc_on_boot=0
+aventen_s3_sync.menu.CDCOnBoot.cdc=Enabled
+aventen_s3_sync.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+aventen_s3_sync.menu.MSCOnBoot.default=Disabled
+aventen_s3_sync.menu.MSCOnBoot.default.build.msc_on_boot=0
+aventen_s3_sync.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+aventen_s3_sync.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+aventen_s3_sync.menu.DFUOnBoot.default=Disabled
+aventen_s3_sync.menu.DFUOnBoot.default.build.dfu_on_boot=0
+aventen_s3_sync.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+aventen_s3_sync.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+aventen_s3_sync.menu.UploadMode.default=UART0 / Hardware CDC
+aventen_s3_sync.menu.UploadMode.default.upload.use_1200bps_touch=false
+aventen_s3_sync.menu.UploadMode.default.upload.wait_for_upload_port=false
+aventen_s3_sync.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+aventen_s3_sync.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+aventen_s3_sync.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+aventen_s3_sync.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+aventen_s3_sync.menu.PartitionScheme.default.build.partitions=default
+aventen_s3_sync.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+aventen_s3_sync.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+aventen_s3_sync.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+aventen_s3_sync.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+aventen_s3_sync.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+aventen_s3_sync.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+aventen_s3_sync.menu.PartitionScheme.minimal.build.partitions=minimal
+aventen_s3_sync.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+aventen_s3_sync.menu.PartitionScheme.no_ota.build.partitions=no_ota
+aventen_s3_sync.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+aventen_s3_sync.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+aventen_s3_sync.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+aventen_s3_sync.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+aventen_s3_sync.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+aventen_s3_sync.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+aventen_s3_sync.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+aventen_s3_sync.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+aventen_s3_sync.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+aventen_s3_sync.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+aventen_s3_sync.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+aventen_s3_sync.menu.PartitionScheme.huge_app.build.partitions=huge_app
+aventen_s3_sync.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+aventen_s3_sync.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+aventen_s3_sync.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+aventen_s3_sync.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+aventen_s3_sync.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+aventen_s3_sync.menu.PartitionScheme.fatflash.build.partitions=ffat
+aventen_s3_sync.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+aventen_s3_sync.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+aventen_s3_sync.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+aventen_s3_sync.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+aventen_s3_sync.menu.PartitionScheme.rainmaker=RainMaker 4MB
+aventen_s3_sync.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+aventen_s3_sync.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+aventen_s3_sync.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+aventen_s3_sync.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+aventen_s3_sync.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+aventen_s3_sync.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+aventen_s3_sync.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+aventen_s3_sync.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+aventen_s3_sync.menu.CPUFreq.240=240MHz (WiFi)
+aventen_s3_sync.menu.CPUFreq.240.build.f_cpu=240000000L
+aventen_s3_sync.menu.CPUFreq.160=160MHz (WiFi)
+aventen_s3_sync.menu.CPUFreq.160.build.f_cpu=160000000L
+aventen_s3_sync.menu.CPUFreq.80=80MHz (WiFi)
+aventen_s3_sync.menu.CPUFreq.80.build.f_cpu=80000000L
+aventen_s3_sync.menu.CPUFreq.40=40MHz
+aventen_s3_sync.menu.CPUFreq.40.build.f_cpu=40000000L
+aventen_s3_sync.menu.CPUFreq.20=20MHz
+aventen_s3_sync.menu.CPUFreq.20.build.f_cpu=20000000L
+aventen_s3_sync.menu.CPUFreq.10=10MHz
+aventen_s3_sync.menu.CPUFreq.10.build.f_cpu=10000000L
+
+aventen_s3_sync.menu.UploadSpeed.921600=921600
+aventen_s3_sync.menu.UploadSpeed.921600.upload.speed=921600
+aventen_s3_sync.menu.UploadSpeed.115200=115200
+aventen_s3_sync.menu.UploadSpeed.115200.upload.speed=115200
+aventen_s3_sync.menu.UploadSpeed.256000.windows=256000
+aventen_s3_sync.menu.UploadSpeed.256000.upload.speed=256000
+aventen_s3_sync.menu.UploadSpeed.230400.windows.upload.speed=256000
+aventen_s3_sync.menu.UploadSpeed.230400=230400
+aventen_s3_sync.menu.UploadSpeed.230400.upload.speed=230400
+aventen_s3_sync.menu.UploadSpeed.460800.linux=460800
+aventen_s3_sync.menu.UploadSpeed.460800.macosx=460800
+aventen_s3_sync.menu.UploadSpeed.460800.upload.speed=460800
+aventen_s3_sync.menu.UploadSpeed.512000.windows=512000
+aventen_s3_sync.menu.UploadSpeed.512000.upload.speed=512000
+
+aventen_s3_sync.menu.DebugLevel.none=None
+aventen_s3_sync.menu.DebugLevel.none.build.code_debug=0
+aventen_s3_sync.menu.DebugLevel.error=Error
+aventen_s3_sync.menu.DebugLevel.error.build.code_debug=1
+aventen_s3_sync.menu.DebugLevel.warn=Warn
+aventen_s3_sync.menu.DebugLevel.warn.build.code_debug=2
+aventen_s3_sync.menu.DebugLevel.info=Info
+aventen_s3_sync.menu.DebugLevel.info.build.code_debug=3
+aventen_s3_sync.menu.DebugLevel.debug=Debug
+aventen_s3_sync.menu.DebugLevel.debug.build.code_debug=4
+aventen_s3_sync.menu.DebugLevel.verbose=Verbose
+aventen_s3_sync.menu.DebugLevel.verbose.build.code_debug=5
+
+aventen_s3_sync.menu.EraseFlash.none=Disabled
+aventen_s3_sync.menu.EraseFlash.none.upload.erase_cmd=
+aventen_s3_sync.menu.EraseFlash.all=Enabled
+aventen_s3_sync.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+BharatPi-Node-Wifi.name=BharatPi Node Wifi Module
+
+BharatPi-Node-Wifi.bootloader.tool=esptool_py
+BharatPi-Node-Wifi.bootloader.tool.default=esptool_py
+
+BharatPi-Node-Wifi.upload.tool=esptool_py
+BharatPi-Node-Wifi.upload.tool.default=esptool_py
+BharatPi-Node-Wifi.upload.tool.network=esp_ota
+
+BharatPi-Node-Wifi.upload.maximum_size=1310720
+BharatPi-Node-Wifi.upload.maximum_data_size=327680
+BharatPi-Node-Wifi.upload.flags=
+BharatPi-Node-Wifi.upload.extra_flags=
+
+BharatPi-Node-Wifi.serial.disableDTR=true
+BharatPi-Node-Wifi.serial.disableRTS=true
+
+BharatPi-Node-Wifi.build.tarch=xtensa
+BharatPi-Node-Wifi.build.bootloader_addr=0x1000
+BharatPi-Node-Wifi.build.target=esp32
+BharatPi-Node-Wifi.build.mcu=esp32
+BharatPi-Node-Wifi.build.core=esp32
+BharatPi-Node-Wifi.build.variant=BharatPi-Node-Wifi
+BharatPi-Node-Wifi.build.board=BHARATPI_NODE_WIFI
+
+BharatPi-Node-Wifi.build.f_cpu=240000000L
+BharatPi-Node-Wifi.build.flash_size=4MB
+BharatPi-Node-Wifi.build.flash_freq=40m
+BharatPi-Node-Wifi.build.flash_mode=dio
+BharatPi-Node-Wifi.build.boot=dio
+BharatPi-Node-Wifi.build.partitions=default
+BharatPi-Node-Wifi.build.defines=
+BharatPi-Node-Wifi.build.loop_core=
+BharatPi-Node-Wifi.build.event_core=
+
+BharatPi-Node-Wifi.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.default.build.partitions=default
+BharatPi-Node-Wifi.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+BharatPi-Node-Wifi.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+BharatPi-Node-Wifi.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+BharatPi-Node-Wifi.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.minimal.build.partitions=minimal
+BharatPi-Node-Wifi.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.no_ota.build.partitions=no_ota
+BharatPi-Node-Wifi.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+BharatPi-Node-Wifi.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+BharatPi-Node-Wifi.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+BharatPi-Node-Wifi.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+BharatPi-Node-Wifi.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+BharatPi-Node-Wifi.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+BharatPi-Node-Wifi.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+BharatPi-Node-Wifi.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.huge_app.build.partitions=huge_app
+BharatPi-Node-Wifi.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+BharatPi-Node-Wifi.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+BharatPi-Node-Wifi.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+BharatPi-Node-Wifi.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.fatflash.build.partitions=ffat
+BharatPi-Node-Wifi.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+BharatPi-Node-Wifi.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+BharatPi-Node-Wifi.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+BharatPi-Node-Wifi.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+BharatPi-Node-Wifi.menu.PartitionScheme.rainmaker=RainMaker
+BharatPi-Node-Wifi.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+BharatPi-Node-Wifi.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728
+BharatPi-Node-Wifi.menu.PartitionScheme.custom=Custom
+BharatPi-Node-Wifi.menu.PartitionScheme.custom.build.partitions=
+BharatPi-Node-Wifi.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+BharatPi-Node-Wifi.menu.CPUFreq.240=240MHz (WiFi/BT)
+BharatPi-Node-Wifi.menu.CPUFreq.240.build.f_cpu=240000000L
+BharatPi-Node-Wifi.menu.CPUFreq.160=160MHz (WiFi/BT)
+BharatPi-Node-Wifi.menu.CPUFreq.160.build.f_cpu=160000000L
+BharatPi-Node-Wifi.menu.CPUFreq.80=80MHz (WiFi/BT)
+BharatPi-Node-Wifi.menu.CPUFreq.80.build.f_cpu=80000000L
+BharatPi-Node-Wifi.menu.CPUFreq.40=40MHz (40MHz XTAL)
+BharatPi-Node-Wifi.menu.CPUFreq.40.build.f_cpu=40000000L
+BharatPi-Node-Wifi.menu.CPUFreq.26=26MHz (26MHz XTAL)
+BharatPi-Node-Wifi.menu.CPUFreq.26.build.f_cpu=26000000L
+BharatPi-Node-Wifi.menu.CPUFreq.20=20MHz (40MHz XTAL)
+BharatPi-Node-Wifi.menu.CPUFreq.20.build.f_cpu=20000000L
+BharatPi-Node-Wifi.menu.CPUFreq.13=13MHz (26MHz XTAL)
+BharatPi-Node-Wifi.menu.CPUFreq.13.build.f_cpu=13000000L
+BharatPi-Node-Wifi.menu.CPUFreq.10=10MHz (40MHz XTAL)
+BharatPi-Node-Wifi.menu.CPUFreq.10.build.f_cpu=10000000L
+
+BharatPi-Node-Wifi.menu.FlashMode.qio=QIO
+BharatPi-Node-Wifi.menu.FlashMode.qio.build.flash_mode=dio
+BharatPi-Node-Wifi.menu.FlashMode.qio.build.boot=qio
+BharatPi-Node-Wifi.menu.FlashMode.dio=DIO
+BharatPi-Node-Wifi.menu.FlashMode.dio.build.flash_mode=dio
+BharatPi-Node-Wifi.menu.FlashMode.dio.build.boot=dio
+
+BharatPi-Node-Wifi.menu.FlashFreq.80=80MHz
+BharatPi-Node-Wifi.menu.FlashFreq.80.build.flash_freq=80m
+BharatPi-Node-Wifi.menu.FlashFreq.40=40MHz
+BharatPi-Node-Wifi.menu.FlashFreq.40.build.flash_freq=40m
+
+BharatPi-Node-Wifi.menu.FlashSize.4M=4MB (32Mb)
+BharatPi-Node-Wifi.menu.FlashSize.4M.build.flash_size=4MB
+BharatPi-Node-Wifi.menu.FlashSize.8M=8MB (64Mb)
+BharatPi-Node-Wifi.menu.FlashSize.8M.build.flash_size=8MB
+BharatPi-Node-Wifi.menu.FlashSize.8M.build.partitions=default_8MB
+BharatPi-Node-Wifi.menu.FlashSize.16M=16MB (128Mb)
+BharatPi-Node-Wifi.menu.FlashSize.16M.build.flash_size=16MB
+
+BharatPi-Node-Wifi.menu.UploadSpeed.921600=921600
+BharatPi-Node-Wifi.menu.UploadSpeed.921600.upload.speed=921600
+BharatPi-Node-Wifi.menu.UploadSpeed.115200=115200
+BharatPi-Node-Wifi.menu.UploadSpeed.115200.upload.speed=115200
+BharatPi-Node-Wifi.menu.UploadSpeed.256000.windows=256000
+BharatPi-Node-Wifi.menu.UploadSpeed.256000.upload.speed=256000
+BharatPi-Node-Wifi.menu.UploadSpeed.230400.windows.upload.speed=256000
+BharatPi-Node-Wifi.menu.UploadSpeed.230400=230400
+BharatPi-Node-Wifi.menu.UploadSpeed.230400.upload.speed=230400
+BharatPi-Node-Wifi.menu.UploadSpeed.460800.linux=460800
+BharatPi-Node-Wifi.menu.UploadSpeed.460800.macosx=460800
+BharatPi-Node-Wifi.menu.UploadSpeed.460800.upload.speed=460800
+BharatPi-Node-Wifi.menu.UploadSpeed.512000.windows=512000
+BharatPi-Node-Wifi.menu.UploadSpeed.512000.upload.speed=512000
+
+BharatPi-Node-Wifi.menu.LoopCore.1=Core 1
+BharatPi-Node-Wifi.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+BharatPi-Node-Wifi.menu.LoopCore.0=Core 0
+BharatPi-Node-Wifi.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+BharatPi-Node-Wifi.menu.EventsCore.1=Core 1
+BharatPi-Node-Wifi.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+BharatPi-Node-Wifi.menu.EventsCore.0=Core 0
+BharatPi-Node-Wifi.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+BharatPi-Node-Wifi.menu.DebugLevel.none=None
+BharatPi-Node-Wifi.menu.DebugLevel.none.build.code_debug=0
+BharatPi-Node-Wifi.menu.DebugLevel.error=Error
+BharatPi-Node-Wifi.menu.DebugLevel.error.build.code_debug=1
+BharatPi-Node-Wifi.menu.DebugLevel.warn=Warn
+BharatPi-Node-Wifi.menu.DebugLevel.warn.build.code_debug=2
+BharatPi-Node-Wifi.menu.DebugLevel.info=Info
+BharatPi-Node-Wifi.menu.DebugLevel.info.build.code_debug=3
+BharatPi-Node-Wifi.menu.DebugLevel.debug=Debug
+BharatPi-Node-Wifi.menu.DebugLevel.debug.build.code_debug=4
+BharatPi-Node-Wifi.menu.DebugLevel.verbose=Verbose
+BharatPi-Node-Wifi.menu.DebugLevel.verbose.build.code_debug=5
+
+BharatPi-Node-Wifi.menu.EraseFlash.none=Disabled
+BharatPi-Node-Wifi.menu.EraseFlash.none.upload.erase_cmd=
+BharatPi-Node-Wifi.menu.EraseFlash.all=Enabled
+BharatPi-Node-Wifi.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+
+BharatPi-A7672S-4G.name=BharatPi A7672S 4G Module
+
+BharatPi-A7672S-4G.bootloader.tool=esptool_py
+BharatPi-A7672S-4G.bootloader.tool.default=esptool_py
+
+BharatPi-A7672S-4G.upload.tool=esptool_py
+BharatPi-A7672S-4G.upload.tool.default=esptool_py
+BharatPi-A7672S-4G.upload.tool.network=esp_ota
+
+BharatPi-A7672S-4G.upload.maximum_size=1310720
+BharatPi-A7672S-4G.upload.maximum_data_size=327680
+BharatPi-A7672S-4G.upload.flags=
+BharatPi-A7672S-4G.upload.extra_flags=
+
+BharatPi-A7672S-4G.serial.disableDTR=true
+BharatPi-A7672S-4G.serial.disableRTS=true
+
+BharatPi-A7672S-4G.build.tarch=xtensa
+BharatPi-A7672S-4G.build.bootloader_addr=0x1000
+BharatPi-A7672S-4G.build.target=esp32
+BharatPi-A7672S-4G.build.mcu=esp32
+BharatPi-A7672S-4G.build.core=esp32
+BharatPi-A7672S-4G.build.variant=BharatPi-A7672S-4G
+BharatPi-A7672S-4G.build.board=BHARATPI_A7672S_4G
+
+BharatPi-A7672S-4G.build.f_cpu=240000000L
+BharatPi-A7672S-4G.build.flash_size=4MB
+BharatPi-A7672S-4G.build.flash_freq=40m
+BharatPi-A7672S-4G.build.flash_mode=dio
+BharatPi-A7672S-4G.build.boot=dio
+BharatPi-A7672S-4G.build.partitions=default
+BharatPi-A7672S-4G.build.defines=
+BharatPi-A7672S-4G.build.loop_core=
+BharatPi-A7672S-4G.build.event_core=
+
+BharatPi-A7672S-4G.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.default.build.partitions=default
+BharatPi-A7672S-4G.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+BharatPi-A7672S-4G.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+BharatPi-A7672S-4G.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+BharatPi-A7672S-4G.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.minimal.build.partitions=minimal
+BharatPi-A7672S-4G.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.no_ota.build.partitions=no_ota
+BharatPi-A7672S-4G.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+BharatPi-A7672S-4G.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+BharatPi-A7672S-4G.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+BharatPi-A7672S-4G.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+BharatPi-A7672S-4G.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+BharatPi-A7672S-4G.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+BharatPi-A7672S-4G.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+BharatPi-A7672S-4G.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.huge_app.build.partitions=huge_app
+BharatPi-A7672S-4G.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+BharatPi-A7672S-4G.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+BharatPi-A7672S-4G.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+BharatPi-A7672S-4G.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.fatflash.build.partitions=ffat
+BharatPi-A7672S-4G.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+BharatPi-A7672S-4G.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+BharatPi-A7672S-4G.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+BharatPi-A7672S-4G.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+BharatPi-A7672S-4G.menu.PartitionScheme.rainmaker=RainMaker
+BharatPi-A7672S-4G.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+BharatPi-A7672S-4G.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728
+BharatPi-A7672S-4G.menu.PartitionScheme.custom=Custom
+BharatPi-A7672S-4G.menu.PartitionScheme.custom.build.partitions=
+BharatPi-A7672S-4G.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+BharatPi-A7672S-4G.menu.CPUFreq.240=240MHz (WiFi/BT)
+BharatPi-A7672S-4G.menu.CPUFreq.240.build.f_cpu=240000000L
+BharatPi-A7672S-4G.menu.CPUFreq.160=160MHz (WiFi/BT)
+BharatPi-A7672S-4G.menu.CPUFreq.160.build.f_cpu=160000000L
+BharatPi-A7672S-4G.menu.CPUFreq.80=80MHz (WiFi/BT)
+BharatPi-A7672S-4G.menu.CPUFreq.80.build.f_cpu=80000000L
+BharatPi-A7672S-4G.menu.CPUFreq.40=40MHz (40MHz XTAL)
+BharatPi-A7672S-4G.menu.CPUFreq.40.build.f_cpu=40000000L
+BharatPi-A7672S-4G.menu.CPUFreq.26=26MHz (26MHz XTAL)
+BharatPi-A7672S-4G.menu.CPUFreq.26.build.f_cpu=26000000L
+BharatPi-A7672S-4G.menu.CPUFreq.20=20MHz (40MHz XTAL)
+BharatPi-A7672S-4G.menu.CPUFreq.20.build.f_cpu=20000000L
+BharatPi-A7672S-4G.menu.CPUFreq.13=13MHz (26MHz XTAL)
+BharatPi-A7672S-4G.menu.CPUFreq.13.build.f_cpu=13000000L
+BharatPi-A7672S-4G.menu.CPUFreq.10=10MHz (40MHz XTAL)
+BharatPi-A7672S-4G.menu.CPUFreq.10.build.f_cpu=10000000L
+
+BharatPi-A7672S-4G.menu.FlashMode.qio=QIO
+BharatPi-A7672S-4G.menu.FlashMode.qio.build.flash_mode=dio
+BharatPi-A7672S-4G.menu.FlashMode.qio.build.boot=qio
+BharatPi-A7672S-4G.menu.FlashMode.dio=DIO
+BharatPi-A7672S-4G.menu.FlashMode.dio.build.flash_mode=dio
+BharatPi-A7672S-4G.menu.FlashMode.dio.build.boot=dio
+
+BharatPi-A7672S-4G.menu.FlashFreq.80=80MHz
+BharatPi-A7672S-4G.menu.FlashFreq.80.build.flash_freq=80m
+BharatPi-A7672S-4G.menu.FlashFreq.40=40MHz
+BharatPi-A7672S-4G.menu.FlashFreq.40.build.flash_freq=40m
+
+BharatPi-A7672S-4G.menu.FlashSize.4M=4MB (32Mb)
+BharatPi-A7672S-4G.menu.FlashSize.4M.build.flash_size=4MB
+BharatPi-A7672S-4G.menu.FlashSize.8M=8MB (64Mb)
+BharatPi-A7672S-4G.menu.FlashSize.8M.build.flash_size=8MB
+BharatPi-A7672S-4G.menu.FlashSize.8M.build.partitions=default_8MB
+BharatPi-A7672S-4G.menu.FlashSize.16M=16MB (128Mb)
+BharatPi-A7672S-4G.menu.FlashSize.16M.build.flash_size=16MB
+
+BharatPi-A7672S-4G.menu.UploadSpeed.921600=921600
+BharatPi-A7672S-4G.menu.UploadSpeed.921600.upload.speed=921600
+BharatPi-A7672S-4G.menu.UploadSpeed.115200=115200
+BharatPi-A7672S-4G.menu.UploadSpeed.115200.upload.speed=115200
+BharatPi-A7672S-4G.menu.UploadSpeed.256000.windows=256000
+BharatPi-A7672S-4G.menu.UploadSpeed.256000.upload.speed=256000
+BharatPi-A7672S-4G.menu.UploadSpeed.230400.windows.upload.speed=256000
+BharatPi-A7672S-4G.menu.UploadSpeed.230400=230400
+BharatPi-A7672S-4G.menu.UploadSpeed.230400.upload.speed=230400
+BharatPi-A7672S-4G.menu.UploadSpeed.460800.linux=460800
+BharatPi-A7672S-4G.menu.UploadSpeed.460800.macosx=460800
+BharatPi-A7672S-4G.menu.UploadSpeed.460800.upload.speed=460800
+BharatPi-A7672S-4G.menu.UploadSpeed.512000.windows=512000
+BharatPi-A7672S-4G.menu.UploadSpeed.512000.upload.speed=512000
+
+BharatPi-A7672S-4G.menu.LoopCore.1=Core 1
+BharatPi-A7672S-4G.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+BharatPi-A7672S-4G.menu.LoopCore.0=Core 0
+BharatPi-A7672S-4G.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+BharatPi-A7672S-4G.menu.EventsCore.1=Core 1
+BharatPi-A7672S-4G.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+BharatPi-A7672S-4G.menu.EventsCore.0=Core 0
+BharatPi-A7672S-4G.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+BharatPi-A7672S-4G.menu.DebugLevel.none=None
+BharatPi-A7672S-4G.menu.DebugLevel.none.build.code_debug=0
+BharatPi-A7672S-4G.menu.DebugLevel.error=Error
+BharatPi-A7672S-4G.menu.DebugLevel.error.build.code_debug=1
+BharatPi-A7672S-4G.menu.DebugLevel.warn=Warn
+BharatPi-A7672S-4G.menu.DebugLevel.warn.build.code_debug=2
+BharatPi-A7672S-4G.menu.DebugLevel.info=Info
+BharatPi-A7672S-4G.menu.DebugLevel.info.build.code_debug=3
+BharatPi-A7672S-4G.menu.DebugLevel.debug=Debug
+BharatPi-A7672S-4G.menu.DebugLevel.debug.build.code_debug=4
+BharatPi-A7672S-4G.menu.DebugLevel.verbose=Verbose
+BharatPi-A7672S-4G.menu.DebugLevel.verbose.build.code_debug=5
+
+BharatPi-A7672S-4G.menu.EraseFlash.none=Disabled
+BharatPi-A7672S-4G.menu.EraseFlash.none.upload.erase_cmd=
+BharatPi-A7672S-4G.menu.EraseFlash.all=Enabled
+BharatPi-A7672S-4G.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+
+BharatPi-LoRa.name=BharatPi LoRa Module
+
+BharatPi-LoRa.bootloader.tool=esptool_py
+BharatPi-LoRa.bootloader.tool.default=esptool_py
+
+BharatPi-LoRa.upload.tool=esptool_py
+BharatPi-LoRa.upload.tool.default=esptool_py
+BharatPi-LoRa.upload.tool.network=esp_ota
+
+BharatPi-LoRa.upload.maximum_size=1310720
+BharatPi-LoRa.upload.maximum_data_size=327680
+BharatPi-LoRa.upload.flags=
+BharatPi-LoRa.upload.extra_flags=
+
+BharatPi-LoRa.serial.disableDTR=true
+BharatPi-LoRa.serial.disableRTS=true
+
+BharatPi-LoRa.build.tarch=xtensa
+BharatPi-LoRa.build.bootloader_addr=0x1000
+BharatPi-LoRa.build.target=esp32
+BharatPi-LoRa.build.mcu=esp32
+BharatPi-LoRa.build.core=esp32
+BharatPi-LoRa.build.variant=BharatPi-LoRa
+BharatPi-LoRa.build.board=BHARATPI_LORA
+
+BharatPi-LoRa.build.f_cpu=240000000L
+BharatPi-LoRa.build.flash_size=4MB
+BharatPi-LoRa.build.flash_freq=40m
+BharatPi-LoRa.build.flash_mode=dio
+BharatPi-LoRa.build.boot=dio
+BharatPi-LoRa.build.partitions=default
+BharatPi-LoRa.build.defines=
+BharatPi-LoRa.build.loop_core=
+BharatPi-LoRa.build.event_core=
+
+BharatPi-LoRa.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+BharatPi-LoRa.menu.PartitionScheme.default.build.partitions=default
+BharatPi-LoRa.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+BharatPi-LoRa.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+BharatPi-LoRa.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+BharatPi-LoRa.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+BharatPi-LoRa.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+BharatPi-LoRa.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+BharatPi-LoRa.menu.PartitionScheme.minimal.build.partitions=minimal
+BharatPi-LoRa.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+BharatPi-LoRa.menu.PartitionScheme.no_ota.build.partitions=no_ota
+BharatPi-LoRa.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+BharatPi-LoRa.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+BharatPi-LoRa.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+BharatPi-LoRa.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+BharatPi-LoRa.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+BharatPi-LoRa.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+BharatPi-LoRa.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+BharatPi-LoRa.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+BharatPi-LoRa.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+BharatPi-LoRa.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+BharatPi-LoRa.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+BharatPi-LoRa.menu.PartitionScheme.huge_app.build.partitions=huge_app
+BharatPi-LoRa.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+BharatPi-LoRa.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+BharatPi-LoRa.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+BharatPi-LoRa.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+BharatPi-LoRa.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+BharatPi-LoRa.menu.PartitionScheme.fatflash.build.partitions=ffat
+BharatPi-LoRa.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+BharatPi-LoRa.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+BharatPi-LoRa.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+BharatPi-LoRa.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+BharatPi-LoRa.menu.PartitionScheme.rainmaker=RainMaker
+BharatPi-LoRa.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+BharatPi-LoRa.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728
+BharatPi-LoRa.menu.PartitionScheme.custom=Custom
+BharatPi-LoRa.menu.PartitionScheme.custom.build.partitions=
+BharatPi-LoRa.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+BharatPi-LoRa.menu.CPUFreq.240=240MHz (WiFi/BT)
+BharatPi-LoRa.menu.CPUFreq.240.build.f_cpu=240000000L
+BharatPi-LoRa.menu.CPUFreq.160=160MHz (WiFi/BT)
+BharatPi-LoRa.menu.CPUFreq.160.build.f_cpu=160000000L
+BharatPi-LoRa.menu.CPUFreq.80=80MHz (WiFi/BT)
+BharatPi-LoRa.menu.CPUFreq.80.build.f_cpu=80000000L
+BharatPi-LoRa.menu.CPUFreq.40=40MHz (40MHz XTAL)
+BharatPi-LoRa.menu.CPUFreq.40.build.f_cpu=40000000L
+BharatPi-LoRa.menu.CPUFreq.26=26MHz (26MHz XTAL)
+BharatPi-LoRa.menu.CPUFreq.26.build.f_cpu=26000000L
+BharatPi-LoRa.menu.CPUFreq.20=20MHz (40MHz XTAL)
+BharatPi-LoRa.menu.CPUFreq.20.build.f_cpu=20000000L
+BharatPi-LoRa.menu.CPUFreq.13=13MHz (26MHz XTAL)
+BharatPi-LoRa.menu.CPUFreq.13.build.f_cpu=13000000L
+BharatPi-LoRa.menu.CPUFreq.10=10MHz (40MHz XTAL)
+BharatPi-LoRa.menu.CPUFreq.10.build.f_cpu=10000000L
+
+BharatPi-LoRa.menu.FlashMode.qio=QIO
+BharatPi-LoRa.menu.FlashMode.qio.build.flash_mode=dio
+BharatPi-LoRa.menu.FlashMode.qio.build.boot=qio
+BharatPi-LoRa.menu.FlashMode.dio=DIO
+BharatPi-LoRa.menu.FlashMode.dio.build.flash_mode=dio
+BharatPi-LoRa.menu.FlashMode.dio.build.boot=dio
+
+BharatPi-LoRa.menu.FlashFreq.80=80MHz
+BharatPi-LoRa.menu.FlashFreq.80.build.flash_freq=80m
+BharatPi-LoRa.menu.FlashFreq.40=40MHz
+BharatPi-LoRa.menu.FlashFreq.40.build.flash_freq=40m
+
+BharatPi-LoRa.menu.FlashSize.4M=4MB (32Mb)
+BharatPi-LoRa.menu.FlashSize.4M.build.flash_size=4MB
+BharatPi-LoRa.menu.FlashSize.8M=8MB (64Mb)
+BharatPi-LoRa.menu.FlashSize.8M.build.flash_size=8MB
+BharatPi-LoRa.menu.FlashSize.8M.build.partitions=default_8MB
+BharatPi-LoRa.menu.FlashSize.16M=16MB (128Mb)
+BharatPi-LoRa.menu.FlashSize.16M.build.flash_size=16MB
+
+BharatPi-LoRa.menu.UploadSpeed.921600=921600
+BharatPi-LoRa.menu.UploadSpeed.921600.upload.speed=921600
+BharatPi-LoRa.menu.UploadSpeed.115200=115200
+BharatPi-LoRa.menu.UploadSpeed.115200.upload.speed=115200
+BharatPi-LoRa.menu.UploadSpeed.256000.windows=256000
+BharatPi-LoRa.menu.UploadSpeed.256000.upload.speed=256000
+BharatPi-LoRa.menu.UploadSpeed.230400.windows.upload.speed=256000
+BharatPi-LoRa.menu.UploadSpeed.230400=230400
+BharatPi-LoRa.menu.UploadSpeed.230400.upload.speed=230400
+BharatPi-LoRa.menu.UploadSpeed.460800.linux=460800
+BharatPi-LoRa.menu.UploadSpeed.460800.macosx=460800
+BharatPi-LoRa.menu.UploadSpeed.460800.upload.speed=460800
+BharatPi-LoRa.menu.UploadSpeed.512000.windows=512000
+BharatPi-LoRa.menu.UploadSpeed.512000.upload.speed=512000
+
+BharatPi-LoRa.menu.LoopCore.1=Core 1
+BharatPi-LoRa.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+BharatPi-LoRa.menu.LoopCore.0=Core 0
+BharatPi-LoRa.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+BharatPi-LoRa.menu.EventsCore.1=Core 1
+BharatPi-LoRa.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+BharatPi-LoRa.menu.EventsCore.0=Core 0
+BharatPi-LoRa.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+BharatPi-LoRa.menu.DebugLevel.none=None
+BharatPi-LoRa.menu.DebugLevel.none.build.code_debug=0
+BharatPi-LoRa.menu.DebugLevel.error=Error
+BharatPi-LoRa.menu.DebugLevel.error.build.code_debug=1
+BharatPi-LoRa.menu.DebugLevel.warn=Warn
+BharatPi-LoRa.menu.DebugLevel.warn.build.code_debug=2
+BharatPi-LoRa.menu.DebugLevel.info=Info
+BharatPi-LoRa.menu.DebugLevel.info.build.code_debug=3
+BharatPi-LoRa.menu.DebugLevel.debug=Debug
+BharatPi-LoRa.menu.DebugLevel.debug.build.code_debug=4
+BharatPi-LoRa.menu.DebugLevel.verbose=Verbose
+BharatPi-LoRa.menu.DebugLevel.verbose.build.code_debug=5
+
+BharatPi-LoRa.menu.EraseFlash.none=Disabled
+BharatPi-LoRa.menu.EraseFlash.none.upload.erase_cmd=
+BharatPi-LoRa.menu.EraseFlash.all=Enabled
+BharatPi-LoRa.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_bling.name=UM BLING
+um_bling.vid.0=0x303a
+um_bling.pid.0=0x817F
+um_bling.upload_port.0.vid=0x303a
+um_bling.upload_port.0.pid=0x817F
+
+um_bling.bootloader.tool=esptool_py
+um_bling.bootloader.tool.default=esptool_py
+
+um_bling.upload.tool=esptool_py
+um_bling.upload.tool.default=esptool_py
+um_bling.upload.tool.network=esp_ota
+
+um_bling.upload.maximum_size=1310720
+um_bling.upload.maximum_data_size=327680
+um_bling.upload.flags=
+um_bling.upload.extra_flags=
+um_bling.upload.use_1200bps_touch=false
+um_bling.upload.wait_for_upload_port=false
+
+um_bling.serial.disableDTR=false
+um_bling.serial.disableRTS=false
+
+um_bling.build.tarch=xtensa
+um_bling.build.bootloader_addr=0x0
+um_bling.build.target=esp32s3
+um_bling.build.mcu=esp32s3
+um_bling.build.core=esp32
+um_bling.build.variant=um_bling
+um_bling.build.board=BLING
+
+um_bling.build.usb_mode=1
+um_bling.build.cdc_on_boot=0
+um_bling.build.msc_on_boot=0
+um_bling.build.dfu_on_boot=0
+um_bling.build.f_cpu=240000000L
+um_bling.build.flash_size=8MB
+um_bling.build.flash_freq=80m
+um_bling.build.flash_mode=dio
+um_bling.build.boot=qio
+um_bling.build.partitions=default
+um_bling.build.defines=
+um_bling.build.loop_core=
+um_bling.build.event_core=
+um_bling.build.flash_type=qio
+um_bling.build.psram_type=qspi
+um_bling.build.memory_type=qio_qspi
+
+um_bling.menu.LoopCore.1=Core 1
+um_bling.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+um_bling.menu.LoopCore.0=Core 0
+um_bling.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+um_bling.menu.EventsCore.1=Core 1
+um_bling.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+um_bling.menu.EventsCore.0=Core 0
+um_bling.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+um_bling.menu.USBMode.hwcdc=Hardware CDC and JTAG
+um_bling.menu.USBMode.hwcdc.build.usb_mode=1
+um_bling.menu.USBMode.default=USB-OTG (TinyUSB)
+um_bling.menu.USBMode.default.build.usb_mode=0
+
+um_bling.menu.CDCOnBoot.cdc=Enabled
+um_bling.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_bling.menu.CDCOnBoot.default=Disabled
+um_bling.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_bling.menu.MSCOnBoot.default=Disabled
+um_bling.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_bling.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+um_bling.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_bling.menu.DFUOnBoot.default=Disabled
+um_bling.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_bling.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+um_bling.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_bling.menu.UploadMode.default=UART0 / Hardware CDC
+um_bling.menu.UploadMode.default.upload.use_1200bps_touch=false
+um_bling.menu.UploadMode.default.upload.wait_for_upload_port=false
+um_bling.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+um_bling.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+um_bling.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+um_bling.menu.PSRAM.enabled=Enabled
+um_bling.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_bling.menu.PSRAM.disabled=Disabled
+um_bling.menu.PSRAM.disabled.build.defines=
+
+um_bling.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+um_bling.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+um_bling.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+um_bling.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT)
+um_bling.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
+um_bling.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
+um_bling.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+um_bling.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+
+um_bling.menu.CPUFreq.240=240MHz (WiFi)
+um_bling.menu.CPUFreq.240.build.f_cpu=240000000L
+um_bling.menu.CPUFreq.160=160MHz (WiFi)
+um_bling.menu.CPUFreq.160.build.f_cpu=160000000L
+um_bling.menu.CPUFreq.80=80MHz (WiFi)
+um_bling.menu.CPUFreq.80.build.f_cpu=80000000L
+um_bling.menu.CPUFreq.40=40MHz
+um_bling.menu.CPUFreq.40.build.f_cpu=40000000L
+um_bling.menu.CPUFreq.20=20MHz
+um_bling.menu.CPUFreq.20.build.f_cpu=20000000L
+um_bling.menu.CPUFreq.10=10MHz
+um_bling.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_bling.menu.FlashMode.qio=QIO
+um_bling.menu.FlashMode.qio.build.flash_mode=dio
+um_bling.menu.FlashMode.qio.build.boot=qio
+um_bling.menu.FlashMode.dio=DIO
+um_bling.menu.FlashMode.dio.build.flash_mode=dio
+um_bling.menu.FlashMode.dio.build.boot=dio
+
+um_bling.menu.UploadSpeed.921600=921600
+um_bling.menu.UploadSpeed.921600.upload.speed=921600
+um_bling.menu.UploadSpeed.115200=115200
+um_bling.menu.UploadSpeed.115200.upload.speed=115200
+um_bling.menu.UploadSpeed.256000.windows=256000
+um_bling.menu.UploadSpeed.256000.upload.speed=256000
+um_bling.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_bling.menu.UploadSpeed.230400=230400
+um_bling.menu.UploadSpeed.230400.upload.speed=230400
+um_bling.menu.UploadSpeed.460800.linux=460800
+um_bling.menu.UploadSpeed.460800.macosx=460800
+um_bling.menu.UploadSpeed.460800.upload.speed=460800
+um_bling.menu.UploadSpeed.512000.windows=512000
+um_bling.menu.UploadSpeed.512000.upload.speed=512000
+
+um_bling.menu.DebugLevel.none=None
+um_bling.menu.DebugLevel.none.build.code_debug=0
+um_bling.menu.DebugLevel.error=Error
+um_bling.menu.DebugLevel.error.build.code_debug=1
+um_bling.menu.DebugLevel.warn=Warn
+um_bling.menu.DebugLevel.warn.build.code_debug=2
+um_bling.menu.DebugLevel.info=Info
+um_bling.menu.DebugLevel.info.build.code_debug=3
+um_bling.menu.DebugLevel.debug=Debug
+um_bling.menu.DebugLevel.debug.build.code_debug=4
+um_bling.menu.DebugLevel.verbose=Verbose
+um_bling.menu.DebugLevel.verbose.build.code_debug=5
+
+um_bling.menu.EraseFlash.none=Disabled
+um_bling.menu.EraseFlash.none.upload.erase_cmd=
+um_bling.menu.EraseFlash.all=Enabled
+um_bling.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_feathers2.name=UM FeatherS2
+um_feathers2.vid.0=0x239A
+um_feathers2.pid.0=0x80AB
+um_feathers2.upload_port.0.vid=0x239A
+um_feathers2.upload_port.0.pid=0x80AB
+
+um_feathers2.bootloader.tool=esptool_py
+um_feathers2.bootloader.tool.default=esptool_py
+
+um_feathers2.upload.tool=esptool_py
+um_feathers2.upload.tool.default=esptool_py
+um_feathers2.upload.tool.network=esp_ota
+
+um_feathers2.upload.maximum_size=1310720
+um_feathers2.upload.maximum_data_size=327680
+um_feathers2.upload.flags=
+um_feathers2.upload.extra_flags=
+um_feathers2.upload.use_1200bps_touch=true
+um_feathers2.upload.wait_for_upload_port=true
+
+um_feathers2.serial.disableDTR=false
+um_feathers2.serial.disableRTS=false
+
+um_feathers2.build.tarch=xtensa
+um_feathers2.build.bootloader_addr=0x1000
+um_feathers2.build.target=esp32s2
+um_feathers2.build.mcu=esp32s2
+um_feathers2.build.core=esp32
+um_feathers2.build.variant=um_feathers2
+um_feathers2.build.board=FEATHERS2
+
+um_feathers2.build.cdc_on_boot=1
+um_feathers2.build.msc_on_boot=0
+um_feathers2.build.dfu_on_boot=0
+um_feathers2.build.f_cpu=240000000L
+um_feathers2.build.flash_size=16MB
+um_feathers2.build.flash_freq=80m
+um_feathers2.build.flash_mode=dio
+um_feathers2.build.boot=qio
+um_feathers2.build.partitions=fatflash
+um_feathers2.build.defines=
+
+um_feathers2.menu.CDCOnBoot.cdc=Enabled
+um_feathers2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_feathers2.menu.CDCOnBoot.default=Disabled
+um_feathers2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_feathers2.menu.MSCOnBoot.default=Disabled
+um_feathers2.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_feathers2.menu.MSCOnBoot.msc=Enabled
+um_feathers2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_feathers2.menu.DFUOnBoot.default=Disabled
+um_feathers2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_feathers2.menu.DFUOnBoot.dfu=Enabled
+um_feathers2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_feathers2.menu.PSRAM.enabled=Enabled
+um_feathers2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_feathers2.menu.PSRAM.disabled=Disabled
+um_feathers2.menu.PSRAM.disabled.build.defines=
+
+um_feathers2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+um_feathers2.menu.PartitionScheme.fatflash.build.partitions=ffat
+um_feathers2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+um_feathers2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+um_feathers2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+um_feathers2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+um_feathers2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+um_feathers2.menu.PartitionScheme.default.build.partitions=default
+um_feathers2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+um_feathers2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+um_feathers2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+um_feathers2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+um_feathers2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+um_feathers2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+um_feathers2.menu.PartitionScheme.minimal.build.partitions=minimal
+um_feathers2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+um_feathers2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+um_feathers2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+um_feathers2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+um_feathers2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+um_feathers2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+um_feathers2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+um_feathers2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+um_feathers2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+um_feathers2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+um_feathers2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+um_feathers2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+um_feathers2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+um_feathers2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+um_feathers2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+um_feathers2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+um_feathers2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+um_feathers2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+um_feathers2.menu.CPUFreq.240=240MHz (WiFi)
+um_feathers2.menu.CPUFreq.240.build.f_cpu=240000000L
+um_feathers2.menu.CPUFreq.160=160MHz (WiFi)
+um_feathers2.menu.CPUFreq.160.build.f_cpu=160000000L
+um_feathers2.menu.CPUFreq.80=80MHz (WiFi)
+um_feathers2.menu.CPUFreq.80.build.f_cpu=80000000L
+um_feathers2.menu.CPUFreq.40=40MHz
+um_feathers2.menu.CPUFreq.40.build.f_cpu=40000000L
+um_feathers2.menu.CPUFreq.20=20MHz
+um_feathers2.menu.CPUFreq.20.build.f_cpu=20000000L
+um_feathers2.menu.CPUFreq.10=10MHz
+um_feathers2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_feathers2.menu.FlashSize.16M=16MB (128Mb)
+um_feathers2.menu.FlashSize.16M.build.flash_size=16MB
+um_feathers2.menu.FlashSize.4M=4MB (32Mb)
+um_feathers2.menu.FlashSize.4M.build.flash_size=4MB
+um_feathers2.menu.FlashSize.8M=8MB (64Mb)
+um_feathers2.menu.FlashSize.8M.build.flash_size=8MB
+um_feathers2.menu.FlashSize.2M=2MB (16Mb)
+um_feathers2.menu.FlashSize.2M.build.flash_size=2MB
+
+um_feathers2.menu.UploadSpeed.921600=921600
+um_feathers2.menu.UploadSpeed.921600.upload.speed=921600
+um_feathers2.menu.UploadSpeed.115200=115200
+um_feathers2.menu.UploadSpeed.115200.upload.speed=115200
+um_feathers2.menu.UploadSpeed.256000.windows=256000
+um_feathers2.menu.UploadSpeed.256000.upload.speed=256000
+um_feathers2.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_feathers2.menu.UploadSpeed.230400=230400
+um_feathers2.menu.UploadSpeed.230400.upload.speed=230400
+um_feathers2.menu.UploadSpeed.460800.linux=460800
+um_feathers2.menu.UploadSpeed.460800.macosx=460800
+um_feathers2.menu.UploadSpeed.460800.upload.speed=460800
+
+um_feathers2.menu.DebugLevel.none=None
+um_feathers2.menu.DebugLevel.none.build.code_debug=0
+um_feathers2.menu.DebugLevel.error=Error
+um_feathers2.menu.DebugLevel.error.build.code_debug=1
+um_feathers2.menu.DebugLevel.warn=Warn
+um_feathers2.menu.DebugLevel.warn.build.code_debug=2
+um_feathers2.menu.DebugLevel.info=Info
+um_feathers2.menu.DebugLevel.info.build.code_debug=3
+um_feathers2.menu.DebugLevel.debug=Debug
+um_feathers2.menu.DebugLevel.debug.build.code_debug=4
+um_feathers2.menu.DebugLevel.verbose=Verbose
+um_feathers2.menu.DebugLevel.verbose.build.code_debug=5
+
+um_feathers2.menu.EraseFlash.none=Disabled
+um_feathers2.menu.EraseFlash.none.upload.erase_cmd=
+um_feathers2.menu.EraseFlash.all=Enabled
+um_feathers2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_feathers2neo.name=UM FeatherS2 Neo
+um_feathers2neo.vid.0=0x303a
+um_feathers2neo.pid.0=0x80B4
+um_feathers2neo.upload_port.0.vid=0x303a
+um_feathers2neo.upload_port.0.pid=0x80B4
+
+um_feathers2neo.bootloader.tool=esptool_py
+um_feathers2neo.bootloader.tool.default=esptool_py
+
+um_feathers2neo.upload.tool=esptool_py
+um_feathers2neo.upload.tool.default=esptool_py
+um_feathers2neo.upload.tool.network=esp_ota
+
+um_feathers2neo.upload.maximum_size=1310720
+um_feathers2neo.upload.maximum_data_size=327680
+um_feathers2neo.upload.flags=
+um_feathers2neo.upload.extra_flags=
+um_feathers2neo.upload.use_1200bps_touch=true
+um_feathers2neo.upload.wait_for_upload_port=true
+
+um_feathers2neo.serial.disableDTR=false
+um_feathers2neo.serial.disableRTS=false
+
+um_feathers2neo.build.tarch=xtensa
+um_feathers2neo.build.bootloader_addr=0x1000
+um_feathers2neo.build.target=esp32s2
+um_feathers2neo.build.mcu=esp32s2
+um_feathers2neo.build.core=esp32
+um_feathers2neo.build.variant=um_feathers2neo
+um_feathers2neo.build.board=FEATHERS2NEO
+
+um_feathers2neo.build.cdc_on_boot=1
+um_feathers2neo.build.msc_on_boot=0
+um_feathers2neo.build.dfu_on_boot=0
+um_feathers2neo.build.f_cpu=240000000L
+um_feathers2neo.build.flash_size=4MB
+um_feathers2neo.build.flash_freq=80m
+um_feathers2neo.build.flash_mode=dio
+um_feathers2neo.build.boot=qio
+um_feathers2neo.build.partitions=default
+um_feathers2neo.build.defines=
+
+um_feathers2neo.menu.CDCOnBoot.cdc=Enabled
+um_feathers2neo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_feathers2neo.menu.CDCOnBoot.default=Disabled
+um_feathers2neo.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_feathers2neo.menu.MSCOnBoot.default=Disabled
+um_feathers2neo.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_feathers2neo.menu.MSCOnBoot.msc=Enabled
+um_feathers2neo.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_feathers2neo.menu.DFUOnBoot.default=Disabled
+um_feathers2neo.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_feathers2neo.menu.DFUOnBoot.dfu=Enabled
+um_feathers2neo.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_feathers2neo.menu.PSRAM.enabled=Enabled
+um_feathers2neo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_feathers2neo.menu.PSRAM.disabled=Disabled
+um_feathers2neo.menu.PSRAM.disabled.build.defines=
+
+um_feathers2neo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+um_feathers2neo.menu.PartitionScheme.default.build.partitions=default
+um_feathers2neo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+um_feathers2neo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+um_feathers2neo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+um_feathers2neo.menu.PartitionScheme.minimal.build.partitions=minimal
+um_feathers2neo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+um_feathers2neo.menu.PartitionScheme.no_ota.build.partitions=no_ota
+um_feathers2neo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+um_feathers2neo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+um_feathers2neo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+um_feathers2neo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+um_feathers2neo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+um_feathers2neo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+um_feathers2neo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+um_feathers2neo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+um_feathers2neo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+um_feathers2neo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+um_feathers2neo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+um_feathers2neo.menu.PartitionScheme.huge_app.build.partitions=huge_app
+um_feathers2neo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+um_feathers2neo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+um_feathers2neo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+um_feathers2neo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+um_feathers2neo.menu.CPUFreq.240=240MHz (WiFi)
+um_feathers2neo.menu.CPUFreq.240.build.f_cpu=240000000L
+um_feathers2neo.menu.CPUFreq.160=160MHz (WiFi)
+um_feathers2neo.menu.CPUFreq.160.build.f_cpu=160000000L
+um_feathers2neo.menu.CPUFreq.80=80MHz (WiFi)
+um_feathers2neo.menu.CPUFreq.80.build.f_cpu=80000000L
+um_feathers2neo.menu.CPUFreq.40=40MHz
+um_feathers2neo.menu.CPUFreq.40.build.f_cpu=40000000L
+um_feathers2neo.menu.CPUFreq.20=20MHz
+um_feathers2neo.menu.CPUFreq.20.build.f_cpu=20000000L
+um_feathers2neo.menu.CPUFreq.10=10MHz
+um_feathers2neo.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_feathers2neo.menu.FlashSize.4M=4MB (32Mb)
+um_feathers2neo.menu.FlashSize.4M.build.flash_size=4MB
+um_feathers2neo.menu.FlashSize.2M=2MB (16Mb)
+um_feathers2neo.menu.FlashSize.2M.build.flash_size=2MB
+
+um_feathers2neo.menu.UploadSpeed.921600=921600
+um_feathers2neo.menu.UploadSpeed.921600.upload.speed=921600
+um_feathers2neo.menu.UploadSpeed.115200=115200
+um_feathers2neo.menu.UploadSpeed.115200.upload.speed=115200
+um_feathers2neo.menu.UploadSpeed.256000.windows=256000
+um_feathers2neo.menu.UploadSpeed.256000.upload.speed=256000
+um_feathers2neo.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_feathers2neo.menu.UploadSpeed.230400=230400
+um_feathers2neo.menu.UploadSpeed.230400.upload.speed=230400
+um_feathers2neo.menu.UploadSpeed.460800.linux=460800
+um_feathers2neo.menu.UploadSpeed.460800.macosx=460800
+um_feathers2neo.menu.UploadSpeed.460800.upload.speed=460800
+
+um_feathers2neo.menu.DebugLevel.none=None
+um_feathers2neo.menu.DebugLevel.none.build.code_debug=0
+um_feathers2neo.menu.DebugLevel.error=Error
+um_feathers2neo.menu.DebugLevel.error.build.code_debug=1
+um_feathers2neo.menu.DebugLevel.warn=Warn
+um_feathers2neo.menu.DebugLevel.warn.build.code_debug=2
+um_feathers2neo.menu.DebugLevel.info=Info
+um_feathers2neo.menu.DebugLevel.info.build.code_debug=3
+um_feathers2neo.menu.DebugLevel.debug=Debug
+um_feathers2neo.menu.DebugLevel.debug.build.code_debug=4
+um_feathers2neo.menu.DebugLevel.verbose=Verbose
+um_feathers2neo.menu.DebugLevel.verbose.build.code_debug=5
+
+um_feathers2neo.menu.EraseFlash.none=Disabled
+um_feathers2neo.menu.EraseFlash.none.upload.erase_cmd=
+um_feathers2neo.menu.EraseFlash.all=Enabled
+um_feathers2neo.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_feathers3.name=UM FeatherS3
+um_feathers3.vid.0=0x303a
+um_feathers3.pid.0=0x80D6
+um_feathers3.upload_port.0.vid=0x303a
+um_feathers3.upload_port.0.pid=0x80D6
+
+um_feathers3.bootloader.tool=esptool_py
+um_feathers3.bootloader.tool.default=esptool_py
+
+um_feathers3.upload.tool=esptool_py
+um_feathers3.upload.tool.default=esptool_py
+um_feathers3.upload.tool.network=esp_ota
+
+um_feathers3.upload.maximum_size=1310720
+um_feathers3.upload.maximum_data_size=327680
+um_feathers3.upload.flags=
+um_feathers3.upload.extra_flags=
+um_feathers3.upload.use_1200bps_touch=false
+um_feathers3.upload.wait_for_upload_port=false
+
+um_feathers3.serial.disableDTR=false
+um_feathers3.serial.disableRTS=false
+
+um_feathers3.build.tarch=xtensa
+um_feathers3.build.bootloader_addr=0x0
+um_feathers3.build.target=esp32s3
+um_feathers3.build.mcu=esp32s3
+um_feathers3.build.core=esp32
+um_feathers3.build.variant=um_feathers3
+um_feathers3.build.board=FEATHERS3
+
+um_feathers3.build.usb_mode=1
+um_feathers3.build.cdc_on_boot=1
+um_feathers3.build.msc_on_boot=0
+um_feathers3.build.dfu_on_boot=0
+um_feathers3.build.f_cpu=240000000L
+um_feathers3.build.flash_size=16MB
+um_feathers3.build.flash_freq=80m
+um_feathers3.build.flash_mode=dio
+um_feathers3.build.boot=qio
+um_feathers3.build.partitions=default
+um_feathers3.build.defines=
+um_feathers3.build.loop_core=
+um_feathers3.build.event_core=
+um_feathers3.build.flash_type=qio
+um_feathers3.build.psram_type=qspi
+um_feathers3.build.memory_type=qio_qspi
+
+um_feathers3.menu.LoopCore.1=Core 1
+um_feathers3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+um_feathers3.menu.LoopCore.0=Core 0
+um_feathers3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+um_feathers3.menu.EventsCore.1=Core 1
+um_feathers3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+um_feathers3.menu.EventsCore.0=Core 0
+um_feathers3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+um_feathers3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+um_feathers3.menu.USBMode.hwcdc.build.usb_mode=1
+um_feathers3.menu.USBMode.default=USB-OTG (TinyUSB)
+um_feathers3.menu.USBMode.default.build.usb_mode=0
+
+um_feathers3.menu.CDCOnBoot.cdc=Enabled
+um_feathers3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_feathers3.menu.CDCOnBoot.default=Disabled
+um_feathers3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_feathers3.menu.MSCOnBoot.default=Disabled
+um_feathers3.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_feathers3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+um_feathers3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_feathers3.menu.DFUOnBoot.default=Disabled
+um_feathers3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_feathers3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+um_feathers3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_feathers3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+um_feathers3.menu.UploadMode.default=UART0 / Hardware CDC
+um_feathers3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+um_feathers3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+um_feathers3.menu.UploadMode.default.upload.use_1200bps_touch=false
+um_feathers3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+um_feathers3.menu.PSRAM.enabled=Enabled
+um_feathers3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_feathers3.menu.PSRAM.disabled=Disabled
+um_feathers3.menu.PSRAM.disabled.build.defines=
+
+um_feathers3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS)
+um_feathers3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
+um_feathers3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
+um_feathers3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/12MB FFAT)
+um_feathers3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
+um_feathers3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
+um_feathers3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+um_feathers3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+um_feathers3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS)
+um_feathers3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
+um_feathers3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592
+um_feathers3.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS)
+um_feathers3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+um_feathers3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+um_feathers3.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS)
+um_feathers3.menu.PartitionScheme.fatflash.build.partitions=ffat
+um_feathers3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+
+um_feathers3.menu.CPUFreq.240=240MHz (WiFi)
+um_feathers3.menu.CPUFreq.240.build.f_cpu=240000000L
+um_feathers3.menu.CPUFreq.160=160MHz (WiFi)
+um_feathers3.menu.CPUFreq.160.build.f_cpu=160000000L
+um_feathers3.menu.CPUFreq.80=80MHz (WiFi)
+um_feathers3.menu.CPUFreq.80.build.f_cpu=80000000L
+um_feathers3.menu.CPUFreq.40=40MHz
+um_feathers3.menu.CPUFreq.40.build.f_cpu=40000000L
+um_feathers3.menu.CPUFreq.20=20MHz
+um_feathers3.menu.CPUFreq.20.build.f_cpu=20000000L
+um_feathers3.menu.CPUFreq.10=10MHz
+um_feathers3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_feathers3.menu.FlashMode.qio=QIO
+um_feathers3.menu.FlashMode.qio.build.flash_mode=dio
+um_feathers3.menu.FlashMode.qio.build.boot=qio
+um_feathers3.menu.FlashMode.dio=DIO
+um_feathers3.menu.FlashMode.dio.build.flash_mode=dio
+um_feathers3.menu.FlashMode.dio.build.boot=dio
+
+um_feathers3.menu.UploadSpeed.921600=921600
+um_feathers3.menu.UploadSpeed.921600.upload.speed=921600
+um_feathers3.menu.UploadSpeed.115200=115200
+um_feathers3.menu.UploadSpeed.115200.upload.speed=115200
+um_feathers3.menu.UploadSpeed.256000.windows=256000
+um_feathers3.menu.UploadSpeed.256000.upload.speed=256000
+um_feathers3.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_feathers3.menu.UploadSpeed.230400=230400
+um_feathers3.menu.UploadSpeed.230400.upload.speed=230400
+um_feathers3.menu.UploadSpeed.460800.linux=460800
+um_feathers3.menu.UploadSpeed.460800.macosx=460800
+um_feathers3.menu.UploadSpeed.460800.upload.speed=460800
+um_feathers3.menu.UploadSpeed.512000.windows=512000
+um_feathers3.menu.UploadSpeed.512000.upload.speed=512000
+
+um_feathers3.menu.DebugLevel.none=None
+um_feathers3.menu.DebugLevel.none.build.code_debug=0
+um_feathers3.menu.DebugLevel.error=Error
+um_feathers3.menu.DebugLevel.error.build.code_debug=1
+um_feathers3.menu.DebugLevel.warn=Warn
+um_feathers3.menu.DebugLevel.warn.build.code_debug=2
+um_feathers3.menu.DebugLevel.info=Info
+um_feathers3.menu.DebugLevel.info.build.code_debug=3
+um_feathers3.menu.DebugLevel.debug=Debug
+um_feathers3.menu.DebugLevel.debug.build.code_debug=4
+um_feathers3.menu.DebugLevel.verbose=Verbose
+um_feathers3.menu.DebugLevel.verbose.build.code_debug=5
+
+um_feathers3.menu.EraseFlash.none=Disabled
+um_feathers3.menu.EraseFlash.none.upload.erase_cmd=
+um_feathers3.menu.EraseFlash.all=Enabled
+um_feathers3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_feathers3neo.name=UM FeatherS3 Neo
+um_feathers3neo.vid.0=0x303a
+um_feathers3neo.pid.0=0x81FB
+um_feathers3neo.upload_port.0.vid=0x303a
+um_feathers3neo.upload_port.0.pid=0x81FB
+
+um_feathers3neo.bootloader.tool=esptool_py
+um_feathers3neo.bootloader.tool.default=esptool_py
+
+um_feathers3neo.upload.tool=esptool_py
+um_feathers3neo.upload.tool.default=esptool_py
+um_feathers3neo.upload.tool.network=esp_ota
+
+um_feathers3neo.upload.maximum_size=1310720
+um_feathers3neo.upload.maximum_data_size=327680
+um_feathers3neo.upload.flags=
+um_feathers3neo.upload.extra_flags=
+um_feathers3neo.upload.use_1200bps_touch=false
+um_feathers3neo.upload.wait_for_upload_port=false
+
+um_feathers3neo.serial.disableDTR=false
+um_feathers3neo.serial.disableRTS=false
+
+um_feathers3neo.build.tarch=xtensa
+um_feathers3neo.build.bootloader_addr=0x0
+um_feathers3neo.build.target=esp32s3
+um_feathers3neo.build.mcu=esp32s3
+um_feathers3neo.build.core=esp32
+um_feathers3neo.build.variant=um_feathers3neo
+um_feathers3neo.build.board=FEATHERS3NEO
+
+um_feathers3neo.build.usb_mode=1
+um_feathers3neo.build.cdc_on_boot=1
+um_feathers3neo.build.msc_on_boot=0
+um_feathers3neo.build.dfu_on_boot=0
+um_feathers3neo.build.f_cpu=240000000L
+um_feathers3neo.build.flash_size=8MB
+um_feathers3neo.build.flash_freq=80m
+um_feathers3neo.build.flash_mode=dio
+um_feathers3neo.build.boot=qio
+um_feathers3neo.build.partitions=default
+um_feathers3neo.build.defines=
+um_feathers3neo.build.loop_core=
+um_feathers3neo.build.event_core=
+um_feathers3neo.build.flash_type=qio
+um_feathers3neo.build.psram_type=qspi
+um_feathers3neo.build.memory_type=qio_qspi
+
+um_feathers3neo.menu.LoopCore.1=Core 1
+um_feathers3neo.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+um_feathers3neo.menu.LoopCore.0=Core 0
+um_feathers3neo.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+um_feathers3neo.menu.EventsCore.1=Core 1
+um_feathers3neo.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+um_feathers3neo.menu.EventsCore.0=Core 0
+um_feathers3neo.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+um_feathers3neo.menu.USBMode.hwcdc=Hardware CDC and JTAG
+um_feathers3neo.menu.USBMode.hwcdc.build.usb_mode=1
+um_feathers3neo.menu.USBMode.default=USB-OTG (TinyUSB)
+um_feathers3neo.menu.USBMode.default.build.usb_mode=0
+
+um_feathers3neo.menu.CDCOnBoot.cdc=Enabled
+um_feathers3neo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_feathers3neo.menu.CDCOnBoot.default=Disabled
+um_feathers3neo.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_feathers3neo.menu.MSCOnBoot.default=Disabled
+um_feathers3neo.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_feathers3neo.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+um_feathers3neo.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_feathers3neo.menu.DFUOnBoot.default=Disabled
+um_feathers3neo.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_feathers3neo.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+um_feathers3neo.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_feathers3neo.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+um_feathers3neo.menu.UploadMode.default=UART0 / Hardware CDC
+um_feathers3neo.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+um_feathers3neo.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+um_feathers3neo.menu.UploadMode.default.upload.use_1200bps_touch=false
+um_feathers3neo.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+um_feathers3neo.menu.PSRAM.enabled=Enabled
+um_feathers3neo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_feathers3neo.menu.PSRAM.disabled=Disabled
+um_feathers3neo.menu.PSRAM.disabled.build.defines=
+
+um_feathers3neo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+um_feathers3neo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+um_feathers3neo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+um_feathers3neo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+um_feathers3neo.menu.PartitionScheme.minimal.build.partitions=minimal
+um_feathers3neo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+um_feathers3neo.menu.PartitionScheme.no_ota.build.partitions=no_ota
+um_feathers3neo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+um_feathers3neo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+um_feathers3neo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+um_feathers3neo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+um_feathers3neo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+um_feathers3neo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+um_feathers3neo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+um_feathers3neo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+um_feathers3neo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+um_feathers3neo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+um_feathers3neo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+um_feathers3neo.menu.PartitionScheme.huge_app.build.partitions=huge_app
+um_feathers3neo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+um_feathers3neo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+um_feathers3neo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+um_feathers3neo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+um_feathers3neo.menu.CPUFreq.240=240MHz (WiFi)
+um_feathers3neo.menu.CPUFreq.240.build.f_cpu=240000000L
+um_feathers3neo.menu.CPUFreq.160=160MHz (WiFi)
+um_feathers3neo.menu.CPUFreq.160.build.f_cpu=160000000L
+um_feathers3neo.menu.CPUFreq.80=80MHz (WiFi)
+um_feathers3neo.menu.CPUFreq.80.build.f_cpu=80000000L
+um_feathers3neo.menu.CPUFreq.40=40MHz
+um_feathers3neo.menu.CPUFreq.40.build.f_cpu=40000000L
+um_feathers3neo.menu.CPUFreq.20=20MHz
+um_feathers3neo.menu.CPUFreq.20.build.f_cpu=20000000L
+um_feathers3neo.menu.CPUFreq.10=10MHz
+um_feathers3neo.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_feathers3neo.menu.FlashMode.qio=QIO
+um_feathers3neo.menu.FlashMode.qio.build.flash_mode=dio
+um_feathers3neo.menu.FlashMode.qio.build.boot=qio
+um_feathers3neo.menu.FlashMode.dio=DIO
+um_feathers3neo.menu.FlashMode.dio.build.flash_mode=dio
+um_feathers3neo.menu.FlashMode.dio.build.boot=dio
+
+um_feathers3neo.menu.UploadSpeed.921600=921600
+um_feathers3neo.menu.UploadSpeed.921600.upload.speed=921600
+um_feathers3neo.menu.UploadSpeed.115200=115200
+um_feathers3neo.menu.UploadSpeed.115200.upload.speed=115200
+um_feathers3neo.menu.UploadSpeed.256000.windows=256000
+um_feathers3neo.menu.UploadSpeed.256000.upload.speed=256000
+um_feathers3neo.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_feathers3neo.menu.UploadSpeed.230400=230400
+um_feathers3neo.menu.UploadSpeed.230400.upload.speed=230400
+um_feathers3neo.menu.UploadSpeed.460800.linux=460800
+um_feathers3neo.menu.UploadSpeed.460800.macosx=460800
+um_feathers3neo.menu.UploadSpeed.460800.upload.speed=460800
+um_feathers3neo.menu.UploadSpeed.512000.windows=512000
+um_feathers3neo.menu.UploadSpeed.512000.upload.speed=512000
+
+um_feathers3neo.menu.DebugLevel.none=None
+um_feathers3neo.menu.DebugLevel.none.build.code_debug=0
+um_feathers3neo.menu.DebugLevel.error=Error
+um_feathers3neo.menu.DebugLevel.error.build.code_debug=1
+um_feathers3neo.menu.DebugLevel.warn=Warn
+um_feathers3neo.menu.DebugLevel.warn.build.code_debug=2
+um_feathers3neo.menu.DebugLevel.info=Info
+um_feathers3neo.menu.DebugLevel.info.build.code_debug=3
+um_feathers3neo.menu.DebugLevel.debug=Debug
+um_feathers3neo.menu.DebugLevel.debug.build.code_debug=4
+um_feathers3neo.menu.DebugLevel.verbose=Verbose
+um_feathers3neo.menu.DebugLevel.verbose.build.code_debug=5
+
+um_feathers3neo.menu.EraseFlash.none=Disabled
+um_feathers3neo.menu.EraseFlash.none.upload.erase_cmd=
+um_feathers3neo.menu.EraseFlash.all=Enabled
+um_feathers3neo.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_nanos3.name=UM NanoS3
+um_nanos3.vid.0=0x303a
+um_nanos3.pid.0=0x8179
+um_nanos3.upload_port.0.vid=0x303a
+um_nanos3.upload_port.0.pid=0x8179
+
+um_nanos3.bootloader.tool=esptool_py
+um_nanos3.bootloader.tool.default=esptool_py
+
+um_nanos3.upload.tool=esptool_py
+um_nanos3.upload.tool.default=esptool_py
+um_nanos3.upload.tool.network=esp_ota
+
+um_nanos3.upload.maximum_size=1310720
+um_nanos3.upload.maximum_data_size=327680
+um_nanos3.upload.flags=
+um_nanos3.upload.extra_flags=
+um_nanos3.upload.use_1200bps_touch=false
+um_nanos3.upload.wait_for_upload_port=false
+
+um_nanos3.serial.disableDTR=false
+um_nanos3.serial.disableRTS=false
+
+um_nanos3.build.tarch=xtensa
+um_nanos3.build.bootloader_addr=0x0
+um_nanos3.build.target=esp32s3
+um_nanos3.build.mcu=esp32s3
+um_nanos3.build.core=esp32
+um_nanos3.build.variant=um_nanos3
+um_nanos3.build.board=NANOS3
+
+um_nanos3.build.usb_mode=1
+um_nanos3.build.cdc_on_boot=1
+um_nanos3.build.msc_on_boot=0
+um_nanos3.build.dfu_on_boot=0
+um_nanos3.build.f_cpu=240000000L
+um_nanos3.build.flash_size=8MB
+um_nanos3.build.flash_freq=80m
+um_nanos3.build.flash_mode=dio
+um_nanos3.build.boot=qio
+um_nanos3.build.partitions=default
+um_nanos3.build.defines=
+um_nanos3.build.loop_core=
+um_nanos3.build.event_core=
+um_nanos3.build.flash_type=qio
+um_nanos3.build.psram_type=qspi
+um_nanos3.build.memory_type=qio_qspi
+
+um_nanos3.menu.LoopCore.1=Core 1
+um_nanos3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+um_nanos3.menu.LoopCore.0=Core 0
+um_nanos3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+um_nanos3.menu.EventsCore.1=Core 1
+um_nanos3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+um_nanos3.menu.EventsCore.0=Core 0
+um_nanos3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+um_nanos3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+um_nanos3.menu.USBMode.hwcdc.build.usb_mode=1
+um_nanos3.menu.USBMode.default=USB-OTG (TinyUSB)
+um_nanos3.menu.USBMode.default.build.usb_mode=0
+
+um_nanos3.menu.CDCOnBoot.cdc=Enabled
+um_nanos3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_nanos3.menu.CDCOnBoot.default=Disabled
+um_nanos3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_nanos3.menu.MSCOnBoot.default=Disabled
+um_nanos3.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_nanos3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+um_nanos3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_nanos3.menu.DFUOnBoot.default=Disabled
+um_nanos3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_nanos3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+um_nanos3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_nanos3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+um_nanos3.menu.UploadMode.default=UART0 / Hardware CDC
+um_nanos3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+um_nanos3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+um_nanos3.menu.UploadMode.default.upload.use_1200bps_touch=false
+um_nanos3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+um_nanos3.menu.PSRAM.enabled=Enabled
+um_nanos3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_nanos3.menu.PSRAM.disabled=Disabled
+um_nanos3.menu.PSRAM.disabled.build.defines=
+
+um_nanos3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+um_nanos3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+um_nanos3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+um_nanos3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT)
+um_nanos3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
+um_nanos3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
+um_nanos3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+um_nanos3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+
+um_nanos3.menu.CPUFreq.240=240MHz (WiFi)
+um_nanos3.menu.CPUFreq.240.build.f_cpu=240000000L
+um_nanos3.menu.CPUFreq.160=160MHz (WiFi)
+um_nanos3.menu.CPUFreq.160.build.f_cpu=160000000L
+um_nanos3.menu.CPUFreq.80=80MHz (WiFi)
+um_nanos3.menu.CPUFreq.80.build.f_cpu=80000000L
+um_nanos3.menu.CPUFreq.40=40MHz
+um_nanos3.menu.CPUFreq.40.build.f_cpu=40000000L
+um_nanos3.menu.CPUFreq.20=20MHz
+um_nanos3.menu.CPUFreq.20.build.f_cpu=20000000L
+um_nanos3.menu.CPUFreq.10=10MHz
+um_nanos3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_nanos3.menu.FlashMode.qio=QIO
+um_nanos3.menu.FlashMode.qio.build.flash_mode=dio
+um_nanos3.menu.FlashMode.qio.build.boot=qio
+um_nanos3.menu.FlashMode.dio=DIO
+um_nanos3.menu.FlashMode.dio.build.flash_mode=dio
+um_nanos3.menu.FlashMode.dio.build.boot=dio
+
+um_nanos3.menu.UploadSpeed.921600=921600
+um_nanos3.menu.UploadSpeed.921600.upload.speed=921600
+um_nanos3.menu.UploadSpeed.115200=115200
+um_nanos3.menu.UploadSpeed.115200.upload.speed=115200
+um_nanos3.menu.UploadSpeed.256000.windows=256000
+um_nanos3.menu.UploadSpeed.256000.upload.speed=256000
+um_nanos3.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_nanos3.menu.UploadSpeed.230400=230400
+um_nanos3.menu.UploadSpeed.230400.upload.speed=230400
+um_nanos3.menu.UploadSpeed.460800.linux=460800
+um_nanos3.menu.UploadSpeed.460800.macosx=460800
+um_nanos3.menu.UploadSpeed.460800.upload.speed=460800
+um_nanos3.menu.UploadSpeed.512000.windows=512000
+um_nanos3.menu.UploadSpeed.512000.upload.speed=512000
+
+um_nanos3.menu.DebugLevel.none=None
+um_nanos3.menu.DebugLevel.none.build.code_debug=0
+um_nanos3.menu.DebugLevel.error=Error
+um_nanos3.menu.DebugLevel.error.build.code_debug=1
+um_nanos3.menu.DebugLevel.warn=Warn
+um_nanos3.menu.DebugLevel.warn.build.code_debug=2
+um_nanos3.menu.DebugLevel.info=Info
+um_nanos3.menu.DebugLevel.info.build.code_debug=3
+um_nanos3.menu.DebugLevel.debug=Debug
+um_nanos3.menu.DebugLevel.debug.build.code_debug=4
+um_nanos3.menu.DebugLevel.verbose=Verbose
+um_nanos3.menu.DebugLevel.verbose.build.code_debug=5
+
+um_nanos3.menu.EraseFlash.none=Disabled
+um_nanos3.menu.EraseFlash.none.upload.erase_cmd=
+um_nanos3.menu.EraseFlash.all=Enabled
+um_nanos3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_omgs3.name=UM OMGS3
+um_omgs3.vid.0=0x303a
+um_omgs3.pid.0=0x8224
+um_omgs3.upload_port.0.vid=0x303a
+um_omgs3.upload_port.0.pid=0x8224
+
+um_omgs3.bootloader.tool=esptool_py
+um_omgs3.bootloader.tool.default=esptool_py
+
+um_omgs3.upload.tool=esptool_py
+um_omgs3.upload.tool.default=esptool_py
+um_omgs3.upload.tool.network=esp_ota
+
+um_omgs3.upload.maximum_size=1310720
+um_omgs3.upload.maximum_data_size=327680
+um_omgs3.upload.flags=
+um_omgs3.upload.extra_flags=
+um_omgs3.upload.use_1200bps_touch=false
+um_omgs3.upload.wait_for_upload_port=false
+
+um_omgs3.serial.disableDTR=false
+um_omgs3.serial.disableRTS=false
+
+um_omgs3.build.tarch=xtensa
+um_omgs3.build.bootloader_addr=0x0
+um_omgs3.build.target=esp32s3
+um_omgs3.build.mcu=esp32s3
+um_omgs3.build.core=esp32
+um_omgs3.build.variant=um_omgs3
+um_omgs3.build.board=OMGS3
+
+um_omgs3.build.usb_mode=1
+um_omgs3.build.cdc_on_boot=1
+um_omgs3.build.msc_on_boot=0
+um_omgs3.build.dfu_on_boot=0
+um_omgs3.build.f_cpu=240000000L
+um_omgs3.build.flash_size=8MB
+um_omgs3.build.flash_freq=80m
+um_omgs3.build.flash_mode=dio
+um_omgs3.build.boot=qio
+um_omgs3.build.partitions=default
+um_omgs3.build.defines=
+um_omgs3.build.loop_core=
+um_omgs3.build.event_core=
+um_omgs3.build.flash_type=qio
+um_omgs3.build.psram_type=qspi
+um_omgs3.build.memory_type=qio_qspi
+
+um_omgs3.menu.LoopCore.1=Core 1
+um_omgs3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+um_omgs3.menu.LoopCore.0=Core 0
+um_omgs3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+um_omgs3.menu.EventsCore.1=Core 1
+um_omgs3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+um_omgs3.menu.EventsCore.0=Core 0
+um_omgs3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+um_omgs3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+um_omgs3.menu.USBMode.hwcdc.build.usb_mode=1
+um_omgs3.menu.USBMode.default=USB-OTG (TinyUSB)
+um_omgs3.menu.USBMode.default.build.usb_mode=0
+
+um_omgs3.menu.CDCOnBoot.cdc=Enabled
+um_omgs3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_omgs3.menu.CDCOnBoot.default=Disabled
+um_omgs3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_omgs3.menu.MSCOnBoot.default=Disabled
+um_omgs3.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_omgs3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+um_omgs3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_omgs3.menu.DFUOnBoot.default=Disabled
+um_omgs3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_omgs3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+um_omgs3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_omgs3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+um_omgs3.menu.UploadMode.default=UART0 / Hardware CDC
+um_omgs3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+um_omgs3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+um_omgs3.menu.UploadMode.default.upload.use_1200bps_touch=false
+um_omgs3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+um_omgs3.menu.PSRAM.enabled=Enabled
+um_omgs3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_omgs3.menu.PSRAM.disabled=Disabled
+um_omgs3.menu.PSRAM.disabled.build.defines=
+
+um_omgs3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+um_omgs3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+um_omgs3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+um_omgs3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT)
+um_omgs3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
+um_omgs3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
+um_omgs3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+um_omgs3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+
+um_omgs3.menu.CPUFreq.240=240MHz (WiFi)
+um_omgs3.menu.CPUFreq.240.build.f_cpu=240000000L
+um_omgs3.menu.CPUFreq.160=160MHz (WiFi)
+um_omgs3.menu.CPUFreq.160.build.f_cpu=160000000L
+um_omgs3.menu.CPUFreq.80=80MHz (WiFi)
+um_omgs3.menu.CPUFreq.80.build.f_cpu=80000000L
+um_omgs3.menu.CPUFreq.40=40MHz
+um_omgs3.menu.CPUFreq.40.build.f_cpu=40000000L
+um_omgs3.menu.CPUFreq.20=20MHz
+um_omgs3.menu.CPUFreq.20.build.f_cpu=20000000L
+um_omgs3.menu.CPUFreq.10=10MHz
+um_omgs3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_omgs3.menu.FlashMode.qio=QIO
+um_omgs3.menu.FlashMode.qio.build.flash_mode=dio
+um_omgs3.menu.FlashMode.qio.build.boot=qio
+um_omgs3.menu.FlashMode.dio=DIO
+um_omgs3.menu.FlashMode.dio.build.flash_mode=dio
+um_omgs3.menu.FlashMode.dio.build.boot=dio
+
+um_omgs3.menu.UploadSpeed.921600=921600
+um_omgs3.menu.UploadSpeed.921600.upload.speed=921600
+um_omgs3.menu.UploadSpeed.115200=115200
+um_omgs3.menu.UploadSpeed.115200.upload.speed=115200
+um_omgs3.menu.UploadSpeed.256000.windows=256000
+um_omgs3.menu.UploadSpeed.256000.upload.speed=256000
+um_omgs3.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_omgs3.menu.UploadSpeed.230400=230400
+um_omgs3.menu.UploadSpeed.230400.upload.speed=230400
+um_omgs3.menu.UploadSpeed.460800.linux=460800
+um_omgs3.menu.UploadSpeed.460800.macosx=460800
+um_omgs3.menu.UploadSpeed.460800.upload.speed=460800
+um_omgs3.menu.UploadSpeed.512000.windows=512000
+um_omgs3.menu.UploadSpeed.512000.upload.speed=512000
+
+um_omgs3.menu.DebugLevel.none=None
+um_omgs3.menu.DebugLevel.none.build.code_debug=0
+um_omgs3.menu.DebugLevel.error=Error
+um_omgs3.menu.DebugLevel.error.build.code_debug=1
+um_omgs3.menu.DebugLevel.warn=Warn
+um_omgs3.menu.DebugLevel.warn.build.code_debug=2
+um_omgs3.menu.DebugLevel.info=Info
+um_omgs3.menu.DebugLevel.info.build.code_debug=3
+um_omgs3.menu.DebugLevel.debug=Debug
+um_omgs3.menu.DebugLevel.debug.build.code_debug=4
+um_omgs3.menu.DebugLevel.verbose=Verbose
+um_omgs3.menu.DebugLevel.verbose.build.code_debug=5
+
+um_omgs3.menu.EraseFlash.none=Disabled
+um_omgs3.menu.EraseFlash.none.upload.erase_cmd=
+um_omgs3.menu.EraseFlash.all=Enabled
+um_omgs3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_pros3.name=UM PROS3
+um_pros3.vid.0=0x303a
+um_pros3.pid.0=0x80D3
+um_pros3.upload_port.0.vid=0x303a
+um_pros3.upload_port.0.pid=0x80D3
+
+um_pros3.bootloader.tool=esptool_py
+um_pros3.bootloader.tool.default=esptool_py
+
+um_pros3.upload.tool=esptool_py
+um_pros3.upload.tool.default=esptool_py
+um_pros3.upload.tool.network=esp_ota
+
+um_pros3.upload.maximum_size=1310720
+um_pros3.upload.maximum_data_size=327680
+um_pros3.upload.flags=
+um_pros3.upload.extra_flags=
+um_pros3.upload.use_1200bps_touch=false
+um_pros3.upload.wait_for_upload_port=false
+
+um_pros3.serial.disableDTR=false
+um_pros3.serial.disableRTS=false
+
+um_pros3.build.tarch=xtensa
+um_pros3.build.bootloader_addr=0x0
+um_pros3.build.target=esp32s3
+um_pros3.build.mcu=esp32s3
+um_pros3.build.core=esp32
+um_pros3.build.variant=um_pros3
+um_pros3.build.board=PROS3
+
+um_pros3.build.usb_mode=1
+um_pros3.build.cdc_on_boot=1
+um_pros3.build.msc_on_boot=0
+um_pros3.build.dfu_on_boot=0
+um_pros3.build.f_cpu=240000000L
+um_pros3.build.flash_size=16MB
+um_pros3.build.flash_freq=80m
+um_pros3.build.flash_mode=dio
+um_pros3.build.boot=qio
+um_pros3.build.partitions=default
+um_pros3.build.defines=
+um_pros3.build.loop_core=
+um_pros3.build.event_core=
+um_pros3.build.flash_type=qio
+um_pros3.build.psram_type=qspi
+um_pros3.build.memory_type=qio_qspi
+
+um_pros3.menu.LoopCore.1=Core 1
+um_pros3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+um_pros3.menu.LoopCore.0=Core 0
+um_pros3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+um_pros3.menu.EventsCore.1=Core 1
+um_pros3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+um_pros3.menu.EventsCore.0=Core 0
+um_pros3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+um_pros3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+um_pros3.menu.USBMode.hwcdc.build.usb_mode=1
+um_pros3.menu.USBMode.default=USB-OTG (TinyUSB)
+um_pros3.menu.USBMode.default.build.usb_mode=0
+
+um_pros3.menu.CDCOnBoot.cdc=Enabled
+um_pros3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_pros3.menu.CDCOnBoot.default=Disabled
+um_pros3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_pros3.menu.MSCOnBoot.default=Disabled
+um_pros3.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_pros3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+um_pros3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_pros3.menu.DFUOnBoot.default=Disabled
+um_pros3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_pros3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+um_pros3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_pros3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+um_pros3.menu.UploadMode.default=UART0 / Hardware CDC
+um_pros3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+um_pros3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+um_pros3.menu.UploadMode.default.upload.use_1200bps_touch=false
+um_pros3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+um_pros3.menu.PSRAM.enabled=Enabled
+um_pros3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_pros3.menu.PSRAM.disabled=Disabled
+um_pros3.menu.PSRAM.disabled.build.defines=
+
+um_pros3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS)
+um_pros3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
+um_pros3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
+um_pros3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/12MB FFAT)
+um_pros3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
+um_pros3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
+um_pros3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+um_pros3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+um_pros3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS)
+um_pros3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
+um_pros3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592
+um_pros3.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS)
+um_pros3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+um_pros3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+um_pros3.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS)
+um_pros3.menu.PartitionScheme.fatflash.build.partitions=ffat
+um_pros3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+
+um_pros3.menu.CPUFreq.240=240MHz (WiFi)
+um_pros3.menu.CPUFreq.240.build.f_cpu=240000000L
+um_pros3.menu.CPUFreq.160=160MHz (WiFi)
+um_pros3.menu.CPUFreq.160.build.f_cpu=160000000L
+um_pros3.menu.CPUFreq.80=80MHz (WiFi)
+um_pros3.menu.CPUFreq.80.build.f_cpu=80000000L
+um_pros3.menu.CPUFreq.40=40MHz
+um_pros3.menu.CPUFreq.40.build.f_cpu=40000000L
+um_pros3.menu.CPUFreq.20=20MHz
+um_pros3.menu.CPUFreq.20.build.f_cpu=20000000L
+um_pros3.menu.CPUFreq.10=10MHz
+um_pros3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_pros3.menu.FlashMode.qio=QIO
+um_pros3.menu.FlashMode.qio.build.flash_mode=dio
+um_pros3.menu.FlashMode.qio.build.boot=qio
+um_pros3.menu.FlashMode.dio=DIO
+um_pros3.menu.FlashMode.dio.build.flash_mode=dio
+um_pros3.menu.FlashMode.dio.build.boot=dio
+
+um_pros3.menu.UploadSpeed.921600=921600
+um_pros3.menu.UploadSpeed.921600.upload.speed=921600
+um_pros3.menu.UploadSpeed.115200=115200
+um_pros3.menu.UploadSpeed.115200.upload.speed=115200
+um_pros3.menu.UploadSpeed.256000.windows=256000
+um_pros3.menu.UploadSpeed.256000.upload.speed=256000
+um_pros3.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_pros3.menu.UploadSpeed.230400=230400
+um_pros3.menu.UploadSpeed.230400.upload.speed=230400
+um_pros3.menu.UploadSpeed.460800.linux=460800
+um_pros3.menu.UploadSpeed.460800.macosx=460800
+um_pros3.menu.UploadSpeed.460800.upload.speed=460800
+um_pros3.menu.UploadSpeed.512000.windows=512000
+um_pros3.menu.UploadSpeed.512000.upload.speed=512000
+
+um_pros3.menu.DebugLevel.none=None
+um_pros3.menu.DebugLevel.none.build.code_debug=0
+um_pros3.menu.DebugLevel.error=Error
+um_pros3.menu.DebugLevel.error.build.code_debug=1
+um_pros3.menu.DebugLevel.warn=Warn
+um_pros3.menu.DebugLevel.warn.build.code_debug=2
+um_pros3.menu.DebugLevel.info=Info
+um_pros3.menu.DebugLevel.info.build.code_debug=3
+um_pros3.menu.DebugLevel.debug=Debug
+um_pros3.menu.DebugLevel.debug.build.code_debug=4
+um_pros3.menu.DebugLevel.verbose=Verbose
+um_pros3.menu.DebugLevel.verbose.build.code_debug=5
+
+um_pros3.menu.EraseFlash.none=Disabled
+um_pros3.menu.EraseFlash.none.upload.erase_cmd=
+um_pros3.menu.EraseFlash.all=Enabled
+um_pros3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_tinypico.name=UM TinyPICO
+
+um_tinypico.bootloader.tool=esptool_py
+um_tinypico.bootloader.tool.default=esptool_py
+
+um_tinypico.upload.tool=esptool_py
+um_tinypico.upload.tool.default=esptool_py
+um_tinypico.upload.tool.network=esp_ota
+
+um_tinypico.upload.maximum_size=1310720
+um_tinypico.upload.maximum_data_size=327680
+um_tinypico.upload.flags=
+um_tinypico.upload.extra_flags=
+
+um_tinypico.serial.disableDTR=true
+um_tinypico.serial.disableRTS=true
+
+um_tinypico.build.tarch=xtensa
+um_tinypico.build.bootloader_addr=0x1000
+um_tinypico.build.target=esp32
+um_tinypico.build.mcu=esp32
+um_tinypico.build.core=esp32
+um_tinypico.build.variant=um_tinypico
+um_tinypico.build.board=TINYPICO
+
+um_tinypico.build.f_cpu=240000000L
+um_tinypico.build.flash_size=4MB
+um_tinypico.build.flash_freq=80m
+um_tinypico.build.flash_mode=dio
+um_tinypico.build.boot=dio
+um_tinypico.build.partitions=default
+um_tinypico.build.defines=
+
+um_tinypico.menu.PartitionScheme.default=Default
+um_tinypico.menu.PartitionScheme.default.build.partitions=default
+um_tinypico.menu.PartitionScheme.no_ota=No OTA (Large APP)
+um_tinypico.menu.PartitionScheme.no_ota.build.partitions=no_ota
+um_tinypico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+um_tinypico.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+um_tinypico.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+um_tinypico.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+um_tinypico.menu.UploadSpeed.921600=921600
+um_tinypico.menu.UploadSpeed.921600.upload.speed=921600
+um_tinypico.menu.UploadSpeed.115200=115200
+um_tinypico.menu.UploadSpeed.115200.upload.speed=115200
+um_tinypico.menu.UploadSpeed.256000.windows=256000
+um_tinypico.menu.UploadSpeed.256000.upload.speed=256000
+um_tinypico.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_tinypico.menu.UploadSpeed.230400=230400
+um_tinypico.menu.UploadSpeed.230400.upload.speed=230400
+um_tinypico.menu.UploadSpeed.460800.linux=460800
+um_tinypico.menu.UploadSpeed.460800.macosx=460800
+um_tinypico.menu.UploadSpeed.460800.upload.speed=460800
+um_tinypico.menu.UploadSpeed.512000.windows=512000
+um_tinypico.menu.UploadSpeed.512000.upload.speed=512000
+
+um_tinypico.menu.FlashMode.qio=QIO
+um_tinypico.menu.FlashMode.qio.build.flash_mode=dio
+um_tinypico.menu.FlashMode.qio.build.boot=qio
+um_tinypico.menu.FlashMode.dio=DIO
+um_tinypico.menu.FlashMode.dio.build.flash_mode=dio
+um_tinypico.menu.FlashMode.dio.build.boot=dio
+
+um_tinypico.menu.FlashFreq.80=80MHz
+um_tinypico.menu.FlashFreq.80.build.flash_freq=80m
+um_tinypico.menu.FlashFreq.40=40MHz
+um_tinypico.menu.FlashFreq.40.build.flash_freq=40m
+
+um_tinypico.menu.PSRAM.enabled=Enabled
+um_tinypico.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+um_tinypico.menu.PSRAM.enabled.build.extra_libs=
+um_tinypico.menu.PSRAM.disabled=Disabled
+um_tinypico.menu.PSRAM.disabled.build.defines=
+um_tinypico.menu.PSRAM.disabled.build.extra_libs=
+
+um_tinypico.menu.DebugLevel.none=None
+um_tinypico.menu.DebugLevel.none.build.code_debug=0
+um_tinypico.menu.DebugLevel.error=Error
+um_tinypico.menu.DebugLevel.error.build.code_debug=1
+um_tinypico.menu.DebugLevel.warn=Warn
+um_tinypico.menu.DebugLevel.warn.build.code_debug=2
+um_tinypico.menu.DebugLevel.info=Info
+um_tinypico.menu.DebugLevel.info.build.code_debug=3
+um_tinypico.menu.DebugLevel.debug=Debug
+um_tinypico.menu.DebugLevel.debug.build.code_debug=4
+um_tinypico.menu.DebugLevel.verbose=Verbose
+um_tinypico.menu.DebugLevel.verbose.build.code_debug=5
+
+um_tinypico.menu.EraseFlash.none=Disabled
+um_tinypico.menu.EraseFlash.none.upload.erase_cmd=
+um_tinypico.menu.EraseFlash.all=Enabled
+um_tinypico.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+um_tinyc6.name=UM TinyC6
+
+um_tinyc6.bootloader.tool=esptool_py
+um_tinyc6.bootloader.tool.default=esptool_py
+
+um_tinyc6.upload.tool=esptool_py
+um_tinyc6.upload.tool.default=esptool_py
+um_tinyc6.upload.tool.network=esp_ota
+
+um_tinyc6.upload.maximum_size=1310720
+um_tinyc6.upload.maximum_data_size=327680
+um_tinyc6.upload.flags=
+um_tinyc6.upload.extra_flags=
+um_tinyc6.upload.use_1200bps_touch=false
+um_tinyc6.upload.wait_for_upload_port=false
+
+um_tinyc6.serial.disableDTR=false
+um_tinyc6.serial.disableRTS=false
+
+um_tinyc6.build.tarch=riscv32
+um_tinyc6.build.target=esp
+um_tinyc6.build.mcu=esp32c6
+um_tinyc6.build.core=esp32
+um_tinyc6.build.variant=um_tinyc6
+um_tinyc6.build.board=TINYC6
+um_tinyc6.build.bootloader_addr=0x0
+
+um_tinyc6.build.cdc_on_boot=1
+um_tinyc6.build.f_cpu=160000000L
+um_tinyc6.build.flash_size=4MB
+um_tinyc6.build.flash_freq=80m
+um_tinyc6.build.flash_mode=qio
+um_tinyc6.build.boot=qio
+um_tinyc6.build.partitions=default
+um_tinyc6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+um_tinyc6.menu.JTAGAdapter.default=Disabled
+um_tinyc6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+um_tinyc6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+um_tinyc6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+um_tinyc6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+um_tinyc6.menu.JTAGAdapter.external=FTDI Adapter
+um_tinyc6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+um_tinyc6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+um_tinyc6.menu.JTAGAdapter.bridge=ESP USB Bridge
+um_tinyc6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+um_tinyc6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+um_tinyc6.menu.CDCOnBoot.cdc=Enabled
+um_tinyc6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_tinyc6.menu.CDCOnBoot.default=Disabled
+um_tinyc6.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_tinyc6.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+um_tinyc6.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+um_tinyc6.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+um_tinyc6.menu.PartitionScheme.rainmaker=RainMaker 4MB
+um_tinyc6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+um_tinyc6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+um_tinyc6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+um_tinyc6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+um_tinyc6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+um_tinyc6.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+um_tinyc6.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+um_tinyc6.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+um_tinyc6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+um_tinyc6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+um_tinyc6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+um_tinyc6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+um_tinyc6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+um_tinyc6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+um_tinyc6.menu.PartitionScheme.custom=Custom
+um_tinyc6.menu.PartitionScheme.custom.build.partitions=
+um_tinyc6.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+um_tinyc6.menu.CPUFreq.160=160MHz (WiFi)
+um_tinyc6.menu.CPUFreq.160.build.f_cpu=160000000L
+um_tinyc6.menu.CPUFreq.80=80MHz (WiFi)
+um_tinyc6.menu.CPUFreq.80.build.f_cpu=80000000L
+um_tinyc6.menu.CPUFreq.40=40MHz
+um_tinyc6.menu.CPUFreq.40.build.f_cpu=40000000L
+um_tinyc6.menu.CPUFreq.20=20MHz
+um_tinyc6.menu.CPUFreq.20.build.f_cpu=20000000L
+um_tinyc6.menu.CPUFreq.10=10MHz
+um_tinyc6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_tinyc6.menu.FlashMode.qio=QIO
+um_tinyc6.menu.FlashMode.qio.build.flash_mode=dio
+um_tinyc6.menu.FlashMode.qio.build.boot=qio
+um_tinyc6.menu.FlashMode.dio=DIO
+um_tinyc6.menu.FlashMode.dio.build.flash_mode=dio
+um_tinyc6.menu.FlashMode.dio.build.boot=dio
+
+um_tinyc6.menu.FlashFreq.80=80MHz
+um_tinyc6.menu.FlashFreq.80.build.flash_freq=80m
+um_tinyc6.menu.FlashFreq.40=40MHz
+um_tinyc6.menu.FlashFreq.40.build.flash_freq=40m
+
+um_tinyc6.menu.FlashSize.8M=8MB (64Mb)
+um_tinyc6.menu.FlashSize.8M.build.flash_size=8MB
+
+um_tinyc6.menu.UploadSpeed.921600=921600
+um_tinyc6.menu.UploadSpeed.921600.upload.speed=921600
+um_tinyc6.menu.UploadSpeed.115200=115200
+um_tinyc6.menu.UploadSpeed.115200.upload.speed=115200
+um_tinyc6.menu.UploadSpeed.256000.windows=256000
+um_tinyc6.menu.UploadSpeed.256000.upload.speed=256000
+um_tinyc6.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_tinyc6.menu.UploadSpeed.230400=230400
+um_tinyc6.menu.UploadSpeed.230400.upload.speed=230400
+um_tinyc6.menu.UploadSpeed.460800.linux=460800
+um_tinyc6.menu.UploadSpeed.460800.macosx=460800
+um_tinyc6.menu.UploadSpeed.460800.upload.speed=460800
+um_tinyc6.menu.UploadSpeed.512000.windows=512000
+um_tinyc6.menu.UploadSpeed.512000.upload.speed=512000
+
+um_tinyc6.menu.DebugLevel.none=None
+um_tinyc6.menu.DebugLevel.none.build.code_debug=0
+um_tinyc6.menu.DebugLevel.error=Error
+um_tinyc6.menu.DebugLevel.error.build.code_debug=1
+um_tinyc6.menu.DebugLevel.warn=Warn
+um_tinyc6.menu.DebugLevel.warn.build.code_debug=2
+um_tinyc6.menu.DebugLevel.info=Info
+um_tinyc6.menu.DebugLevel.info.build.code_debug=3
+um_tinyc6.menu.DebugLevel.debug=Debug
+um_tinyc6.menu.DebugLevel.debug.build.code_debug=4
+um_tinyc6.menu.DebugLevel.verbose=Verbose
+um_tinyc6.menu.DebugLevel.verbose.build.code_debug=5
+
+um_tinyc6.menu.EraseFlash.none=Disabled
+um_tinyc6.menu.EraseFlash.none.upload.erase_cmd=
+um_tinyc6.menu.EraseFlash.all=Enabled
+um_tinyc6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+um_tinyc6.menu.ZigbeeMode.default=Disabled
+um_tinyc6.menu.ZigbeeMode.default.build.zigbee_mode=
+um_tinyc6.menu.ZigbeeMode.default.build.zigbee_libs=
+um_tinyc6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+um_tinyc6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+um_tinyc6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+um_tinyc6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+um_tinyc6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+um_tinyc6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+um_tinys2.name=UM TinyS2
+um_tinys2.vid.0=0x303a
+um_tinys2.pid.0=0x8001
+um_tinys2.upload_port.0.vid=0x303a
+um_tinys2.upload_port.0.pid=0x8001
+
+um_tinys2.bootloader.tool=esptool_py
+um_tinys2.bootloader.tool.default=esptool_py
+
+um_tinys2.upload.tool=esptool_py
+um_tinys2.upload.tool.default=esptool_py
+um_tinys2.upload.tool.network=esp_ota
+
+um_tinys2.upload.maximum_size=1310720
+um_tinys2.upload.maximum_data_size=327680
+um_tinys2.upload.flags=
+um_tinys2.upload.extra_flags=
+um_tinys2.upload.use_1200bps_touch=true
+um_tinys2.upload.wait_for_upload_port=true
+
+um_tinys2.serial.disableDTR=false
+um_tinys2.serial.disableRTS=false
+
+um_tinys2.build.tarch=xtensa
+um_tinys2.build.bootloader_addr=0x1000
+um_tinys2.build.target=esp32s2
+um_tinys2.build.mcu=esp32s2
+um_tinys2.build.core=esp32
+um_tinys2.build.variant=um_tinys2
+um_tinys2.build.board=TINYS2
+
+um_tinys2.build.cdc_on_boot=1
+um_tinys2.build.msc_on_boot=0
+um_tinys2.build.dfu_on_boot=0
+um_tinys2.build.f_cpu=240000000L
+um_tinys2.build.flash_size=4MB
+um_tinys2.build.flash_freq=80m
+um_tinys2.build.flash_mode=dio
+um_tinys2.build.boot=qio
+um_tinys2.build.partitions=default
+um_tinys2.build.defines=
+
+um_tinys2.menu.CDCOnBoot.cdc=Enabled
+um_tinys2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_tinys2.menu.CDCOnBoot.default=Disabled
+um_tinys2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_tinys2.menu.MSCOnBoot.default=Disabled
+um_tinys2.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_tinys2.menu.MSCOnBoot.msc=Enabled
+um_tinys2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_tinys2.menu.DFUOnBoot.default=Disabled
+um_tinys2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_tinys2.menu.DFUOnBoot.dfu=Enabled
+um_tinys2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_tinys2.menu.PSRAM.enabled=Enabled
+um_tinys2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_tinys2.menu.PSRAM.disabled=Disabled
+um_tinys2.menu.PSRAM.disabled.build.defines=
+
+um_tinys2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+um_tinys2.menu.PartitionScheme.default.build.partitions=default
+um_tinys2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+um_tinys2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+um_tinys2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+um_tinys2.menu.PartitionScheme.minimal.build.partitions=minimal
+um_tinys2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+um_tinys2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+um_tinys2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+um_tinys2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+um_tinys2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+um_tinys2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+um_tinys2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+um_tinys2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+um_tinys2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+um_tinys2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+um_tinys2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+um_tinys2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+um_tinys2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+um_tinys2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+um_tinys2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+um_tinys2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+um_tinys2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+um_tinys2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+um_tinys2.menu.CPUFreq.240=240MHz (WiFi)
+um_tinys2.menu.CPUFreq.240.build.f_cpu=240000000L
+um_tinys2.menu.CPUFreq.160=160MHz (WiFi)
+um_tinys2.menu.CPUFreq.160.build.f_cpu=160000000L
+um_tinys2.menu.CPUFreq.80=80MHz (WiFi)
+um_tinys2.menu.CPUFreq.80.build.f_cpu=80000000L
+um_tinys2.menu.CPUFreq.40=40MHz
+um_tinys2.menu.CPUFreq.40.build.f_cpu=40000000L
+um_tinys2.menu.CPUFreq.20=20MHz
+um_tinys2.menu.CPUFreq.20.build.f_cpu=20000000L
+um_tinys2.menu.CPUFreq.10=10MHz
+um_tinys2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_tinys2.menu.FlashSize.4M=4MB (32Mb)
+um_tinys2.menu.FlashSize.4M.build.flash_size=4MB
+um_tinys2.menu.FlashSize.2M=2MB (16Mb)
+um_tinys2.menu.FlashSize.2M.build.flash_size=2MB
+
+um_tinys2.menu.UploadSpeed.921600=921600
+um_tinys2.menu.UploadSpeed.921600.upload.speed=921600
+um_tinys2.menu.UploadSpeed.115200=115200
+um_tinys2.menu.UploadSpeed.115200.upload.speed=115200
+um_tinys2.menu.UploadSpeed.256000.windows=256000
+um_tinys2.menu.UploadSpeed.256000.upload.speed=256000
+um_tinys2.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_tinys2.menu.UploadSpeed.230400=230400
+um_tinys2.menu.UploadSpeed.230400.upload.speed=230400
+um_tinys2.menu.UploadSpeed.460800.linux=460800
+um_tinys2.menu.UploadSpeed.460800.macosx=460800
+um_tinys2.menu.UploadSpeed.460800.upload.speed=460800
+
+um_tinys2.menu.DebugLevel.none=None
+um_tinys2.menu.DebugLevel.none.build.code_debug=0
+um_tinys2.menu.DebugLevel.error=Error
+um_tinys2.menu.DebugLevel.error.build.code_debug=1
+um_tinys2.menu.DebugLevel.warn=Warn
+um_tinys2.menu.DebugLevel.warn.build.code_debug=2
+um_tinys2.menu.DebugLevel.info=Info
+um_tinys2.menu.DebugLevel.info.build.code_debug=3
+um_tinys2.menu.DebugLevel.debug=Debug
+um_tinys2.menu.DebugLevel.debug.build.code_debug=4
+um_tinys2.menu.DebugLevel.verbose=Verbose
+um_tinys2.menu.DebugLevel.verbose.build.code_debug=5
+
+um_tinys2.menu.EraseFlash.none=Disabled
+um_tinys2.menu.EraseFlash.none.upload.erase_cmd=
+um_tinys2.menu.EraseFlash.all=Enabled
+um_tinys2.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
-tinypico.name=TinyPICO
-
-tinypico.upload.tool=esptool_py
-tinypico.upload.maximum_size=1310720
-tinypico.upload.maximum_data_size=327680
-tinypico.upload.wait_for_upload_port=true
-
-tinypico.serial.disableDTR=true
-tinypico.serial.disableRTS=true
-
-tinypico.build.mcu=esp32
-tinypico.build.core=esp32
-tinypico.build.variant=pico32
-tinypico.build.board=TINYPICO
-
-tinypico.build.f_cpu=240000000L
-tinypico.build.flash_size=4MB
-tinypico.build.flash_freq=80m
-tinypico.build.flash_mode=dio
-tinypico.build.boot=dio
-tinypico.build.partitions=default
-tinypico.build.defines=
-
-tinypico.menu.PartitionScheme.default=Default
-tinypico.menu.PartitionScheme.default.build.partitions=default
-tinypico.menu.PartitionScheme.no_ota=No OTA (Large APP)
-tinypico.menu.PartitionScheme.no_ota.build.partitions=no_ota
-tinypico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-tinypico.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-tinypico.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-tinypico.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-
-tinypico.menu.UploadSpeed.921600=921600
-tinypico.menu.UploadSpeed.921600.upload.speed=921600
-tinypico.menu.UploadSpeed.115200=115200
-tinypico.menu.UploadSpeed.115200.upload.speed=115200
-tinypico.menu.UploadSpeed.256000.windows=256000
-tinypico.menu.UploadSpeed.256000.upload.speed=256000
-tinypico.menu.UploadSpeed.230400.windows.upload.speed=256000
-tinypico.menu.UploadSpeed.230400=230400
-tinypico.menu.UploadSpeed.230400.upload.speed=230400
-tinypico.menu.UploadSpeed.460800.linux=460800
-tinypico.menu.UploadSpeed.460800.macosx=460800
-tinypico.menu.UploadSpeed.460800.upload.speed=460800
-tinypico.menu.UploadSpeed.512000.windows=512000
-tinypico.menu.UploadSpeed.512000.upload.speed=512000
-
-tinypico.menu.FlashMode.qio=QIO
-tinypico.menu.FlashMode.qio.build.flash_mode=dio
-tinypico.menu.FlashMode.qio.build.boot=qio
-tinypico.menu.FlashMode.dio=DIO
-tinypico.menu.FlashMode.dio.build.flash_mode=dio
-tinypico.menu.FlashMode.dio.build.boot=dio
-
-tinypico.menu.FlashFreq.80=80MHz
-tinypico.menu.FlashFreq.80.build.flash_freq=80m
-tinypico.menu.FlashFreq.40=40MHz
-tinypico.menu.FlashFreq.40.build.flash_freq=40m
-
-tinypico.menu.PSRAM.enabled=Enabled
-tinypico.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
-tinypico.menu.PSRAM.disabled=Disabled
-tinypico.menu.PSRAM.disabled.build.defines=
-
-tinypico.menu.DebugLevel.none=None
-tinypico.menu.DebugLevel.none.build.code_debug=0
-tinypico.menu.DebugLevel.error=Error
-tinypico.menu.DebugLevel.error.build.code_debug=1
-tinypico.menu.DebugLevel.warn=Warn
-tinypico.menu.DebugLevel.warn.build.code_debug=2
-tinypico.menu.DebugLevel.info=Info
-tinypico.menu.DebugLevel.info.build.code_debug=3
-tinypico.menu.DebugLevel.debug=Debug
-tinypico.menu.DebugLevel.debug.build.code_debug=4
-tinypico.menu.DebugLevel.verbose=Verbose
-tinypico.menu.DebugLevel.verbose.build.code_debug=5
+
+um_tinys3.name=UM TinyS3
+um_tinys3.vid.0=0x303a
+um_tinys3.pid.0=0x80D0
+um_tinys3.upload_port.0.vid=0x303a
+um_tinys3.upload_port.0.pid=0x80D0
+
+um_tinys3.bootloader.tool=esptool_py
+um_tinys3.bootloader.tool.default=esptool_py
+
+um_tinys3.upload.tool=esptool_py
+um_tinys3.upload.tool.default=esptool_py
+um_tinys3.upload.tool.network=esp_ota
+
+um_tinys3.upload.maximum_size=1310720
+um_tinys3.upload.maximum_data_size=327680
+um_tinys3.upload.flags=
+um_tinys3.upload.extra_flags=
+um_tinys3.upload.use_1200bps_touch=false
+um_tinys3.upload.wait_for_upload_port=false
+
+um_tinys3.serial.disableDTR=false
+um_tinys3.serial.disableRTS=false
+
+um_tinys3.build.tarch=xtensa
+um_tinys3.build.bootloader_addr=0x0
+um_tinys3.build.target=esp32s3
+um_tinys3.build.mcu=esp32s3
+um_tinys3.build.core=esp32
+um_tinys3.build.variant=um_tinys3
+um_tinys3.build.board=TINYS3
+
+um_tinys3.build.usb_mode=1
+um_tinys3.build.cdc_on_boot=1
+um_tinys3.build.msc_on_boot=0
+um_tinys3.build.dfu_on_boot=0
+um_tinys3.build.f_cpu=240000000L
+um_tinys3.build.flash_size=8MB
+um_tinys3.build.flash_freq=80m
+um_tinys3.build.flash_mode=dio
+um_tinys3.build.boot=qio
+um_tinys3.build.partitions=default
+um_tinys3.build.defines=
+um_tinys3.build.loop_core=
+um_tinys3.build.event_core=
+um_tinys3.build.flash_type=qio
+um_tinys3.build.psram_type=qspi
+um_tinys3.build.memory_type=qio_qspi
+
+um_tinys3.menu.LoopCore.1=Core 1
+um_tinys3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+um_tinys3.menu.LoopCore.0=Core 0
+um_tinys3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+um_tinys3.menu.EventsCore.1=Core 1
+um_tinys3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+um_tinys3.menu.EventsCore.0=Core 0
+um_tinys3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+um_tinys3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+um_tinys3.menu.USBMode.hwcdc.build.usb_mode=1
+um_tinys3.menu.USBMode.default=USB-OTG (TinyUSB)
+um_tinys3.menu.USBMode.default.build.usb_mode=0
+
+um_tinys3.menu.CDCOnBoot.cdc=Enabled
+um_tinys3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+um_tinys3.menu.CDCOnBoot.default=Disabled
+um_tinys3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+um_tinys3.menu.MSCOnBoot.default=Disabled
+um_tinys3.menu.MSCOnBoot.default.build.msc_on_boot=0
+um_tinys3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+um_tinys3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+um_tinys3.menu.DFUOnBoot.default=Disabled
+um_tinys3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+um_tinys3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+um_tinys3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+um_tinys3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+um_tinys3.menu.UploadMode.default=UART0 / Hardware CDC
+um_tinys3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+um_tinys3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+um_tinys3.menu.UploadMode.default.upload.use_1200bps_touch=false
+um_tinys3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+um_tinys3.menu.PSRAM.enabled=Enabled
+um_tinys3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+um_tinys3.menu.PSRAM.disabled=Disabled
+um_tinys3.menu.PSRAM.disabled.build.defines=
+
+um_tinys3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+um_tinys3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+um_tinys3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+um_tinys3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT)
+um_tinys3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
+um_tinys3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
+um_tinys3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+um_tinys3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+
+um_tinys3.menu.CPUFreq.240=240MHz (WiFi)
+um_tinys3.menu.CPUFreq.240.build.f_cpu=240000000L
+um_tinys3.menu.CPUFreq.160=160MHz (WiFi)
+um_tinys3.menu.CPUFreq.160.build.f_cpu=160000000L
+um_tinys3.menu.CPUFreq.80=80MHz (WiFi)
+um_tinys3.menu.CPUFreq.80.build.f_cpu=80000000L
+um_tinys3.menu.CPUFreq.40=40MHz
+um_tinys3.menu.CPUFreq.40.build.f_cpu=40000000L
+um_tinys3.menu.CPUFreq.20=20MHz
+um_tinys3.menu.CPUFreq.20.build.f_cpu=20000000L
+um_tinys3.menu.CPUFreq.10=10MHz
+um_tinys3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+um_tinys3.menu.FlashMode.qio=QIO
+um_tinys3.menu.FlashMode.qio.build.flash_mode=dio
+um_tinys3.menu.FlashMode.qio.build.boot=qio
+um_tinys3.menu.FlashMode.dio=DIO
+um_tinys3.menu.FlashMode.dio.build.flash_mode=dio
+um_tinys3.menu.FlashMode.dio.build.boot=dio
+
+um_tinys3.menu.UploadSpeed.921600=921600
+um_tinys3.menu.UploadSpeed.921600.upload.speed=921600
+um_tinys3.menu.UploadSpeed.115200=115200
+um_tinys3.menu.UploadSpeed.115200.upload.speed=115200
+um_tinys3.menu.UploadSpeed.256000.windows=256000
+um_tinys3.menu.UploadSpeed.256000.upload.speed=256000
+um_tinys3.menu.UploadSpeed.230400.windows.upload.speed=256000
+um_tinys3.menu.UploadSpeed.230400=230400
+um_tinys3.menu.UploadSpeed.230400.upload.speed=230400
+um_tinys3.menu.UploadSpeed.460800.linux=460800
+um_tinys3.menu.UploadSpeed.460800.macosx=460800
+um_tinys3.menu.UploadSpeed.460800.upload.speed=460800
+um_tinys3.menu.UploadSpeed.512000.windows=512000
+um_tinys3.menu.UploadSpeed.512000.upload.speed=512000
+
+um_tinys3.menu.DebugLevel.none=None
+um_tinys3.menu.DebugLevel.none.build.code_debug=0
+um_tinys3.menu.DebugLevel.error=Error
+um_tinys3.menu.DebugLevel.error.build.code_debug=1
+um_tinys3.menu.DebugLevel.warn=Warn
+um_tinys3.menu.DebugLevel.warn.build.code_debug=2
+um_tinys3.menu.DebugLevel.info=Info
+um_tinys3.menu.DebugLevel.info.build.code_debug=3
+um_tinys3.menu.DebugLevel.debug=Debug
+um_tinys3.menu.DebugLevel.debug.build.code_debug=4
+um_tinys3.menu.DebugLevel.verbose=Verbose
+um_tinys3.menu.DebugLevel.verbose.build.code_debug=5
+
+um_tinys3.menu.EraseFlash.none=Disabled
+um_tinys3.menu.EraseFlash.none.upload.erase_cmd=
+um_tinys3.menu.EraseFlash.all=Enabled
+um_tinys3.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
+
 S_ODI_Ultra.name=S.ODI Ultra v1
 
+S_ODI_Ultra.bootloader.tool=esptool_py
+S_ODI_Ultra.bootloader.tool.default=esptool_py
+
 S_ODI_Ultra.upload.tool=esptool_py
+S_ODI_Ultra.upload.tool.default=esptool_py
+S_ODI_Ultra.upload.tool.network=esp_ota
+
 S_ODI_Ultra.upload.maximum_size=1310720
 S_ODI_Ultra.upload.maximum_data_size=327680
 S_ODI_Ultra.upload.wait_for_upload_port=true
+S_ODI_Ultra.upload.flags=
+S_ODI_Ultra.upload.extra_flags=
 
 S_ODI_Ultra.serial.disableDTR=true
 S_ODI_Ultra.serial.disableRTS=true
 
+S_ODI_Ultra.build.tarch=xtensa
+S_ODI_Ultra.build.bootloader_addr=0x1000
+S_ODI_Ultra.build.target=esp32
 S_ODI_Ultra.build.mcu=esp32
 S_ODI_Ultra.build.core=esp32
 S_ODI_Ultra.build.variant=S_ODI_Ultra_v1
@@ -441,17 +5334,1243 @@ S_ODI_Ultra.menu.DebugLevel.info.build.code_debug=3
 S_ODI_Ultra.menu.DebugLevel.debug=Debug
 S_ODI_Ultra.menu.DebugLevel.debug.build.code_debug=4
 
+S_ODI_Ultra.menu.EraseFlash.none=Disabled
+S_ODI_Ultra.menu.EraseFlash.none.upload.erase_cmd=
+S_ODI_Ultra.menu.EraseFlash.all=Enabled
+S_ODI_Ultra.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lilygo_t_display.name=LilyGo T-Display
+
+lilygo_t_display.upload.tool=esptool_py
+lilygo_t_display.upload.tool.default=esptool_py
+lilygo_t_display.upload.tool.network=esp_ota
+lilygo_t_display.upload.maximum_size=1310720
+lilygo_t_display.upload.maximum_data_size=327680
+lilygo_t_display.upload.wait_for_upload_port=true
+lilygo_t_display.upload.speed=460800
+lilygo_t_display.upload.flags=
+lilygo_t_display.upload.extra_flags=
+
+lilygo_t_display.bootloader.tool=esptool_py
+lilygo_t_display.bootloader.tool.default=esptool_py
+
+lilygo_t_display.serial.disableDTR=true
+lilygo_t_display.serial.disableRTS=true
+
+lilygo_t_display.build.tarch=xtensa
+lilygo_t_display.build.bootloader_addr=0x1000
+lilygo_t_display.build.mcu=esp32
+lilygo_t_display.build.core=esp32
+lilygo_t_display.build.target=esp32
+lilygo_t_display.build.variant=lilygo_t_display
+lilygo_t_display.build.board=LILYGO_T_DISPLAY
+
+lilygo_t_display.build.f_cpu=240000000L
+lilygo_t_display.build.flash_size=4MB
+lilygo_t_display.build.flash_freq=80m
+lilygo_t_display.build.flash_mode=dio
+lilygo_t_display.build.boot=dio
+lilygo_t_display.build.partitions=default
+
+lilygo_t_display.menu.PSRAM.disabled=Disabled
+lilygo_t_display.menu.PSRAM.disabled.build.defines=
+lilygo_t_display.menu.PSRAM.enabled=Enabled
+lilygo_t_display.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+lilygo_t_display.menu.PSRAM.enabled.build.extra_libs=
+
+lilygo_t_display.menu.LoopCore.1=Core 1
+lilygo_t_display.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lilygo_t_display.menu.LoopCore.0=Core 0
+lilygo_t_display.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lilygo_t_display.menu.EventsCore.1=Core 1
+lilygo_t_display.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lilygo_t_display.menu.EventsCore.0=Core 0
+lilygo_t_display.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lilygo_t_display.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lilygo_t_display.menu.PartitionScheme.default.build.partitions=default
+lilygo_t_display.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lilygo_t_display.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lilygo_t_display.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+lilygo_t_display.menu.PartitionScheme.minimal.build.partitions=minimal
+lilygo_t_display.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lilygo_t_display.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lilygo_t_display.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lilygo_t_display.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lilygo_t_display.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lilygo_t_display.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lilygo_t_display.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lilygo_t_display.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lilygo_t_display.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lilygo_t_display.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lilygo_t_display.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lilygo_t_display.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lilygo_t_display.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lilygo_t_display.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lilygo_t_display.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+lilygo_t_display.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+lilygo_t_display.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+lilygo_t_display.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+lilygo_t_display.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+lilygo_t_display.menu.PartitionScheme.fatflash.build.partitions=ffat
+lilygo_t_display.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+lilygo_t_display.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+lilygo_t_display.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+lilygo_t_display.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+lilygo_t_display.menu.CPUFreq.240=240MHz (WiFi/BT)
+lilygo_t_display.menu.CPUFreq.240.build.f_cpu=240000000L
+lilygo_t_display.menu.CPUFreq.160=160MHz (WiFi/BT)
+lilygo_t_display.menu.CPUFreq.160.build.f_cpu=160000000L
+lilygo_t_display.menu.CPUFreq.80=80MHz (WiFi/BT)
+lilygo_t_display.menu.CPUFreq.80.build.f_cpu=80000000L
+lilygo_t_display.menu.CPUFreq.40=40MHz (40MHz XTAL)
+lilygo_t_display.menu.CPUFreq.40.build.f_cpu=40000000L
+lilygo_t_display.menu.CPUFreq.26=26MHz (26MHz XTAL)
+lilygo_t_display.menu.CPUFreq.26.build.f_cpu=26000000L
+lilygo_t_display.menu.CPUFreq.20=20MHz (40MHz XTAL)
+lilygo_t_display.menu.CPUFreq.20.build.f_cpu=20000000L
+lilygo_t_display.menu.CPUFreq.13=13MHz (26MHz XTAL)
+lilygo_t_display.menu.CPUFreq.13.build.f_cpu=13000000L
+lilygo_t_display.menu.CPUFreq.10=10MHz (40MHz XTAL)
+lilygo_t_display.menu.CPUFreq.10.build.f_cpu=10000000L
+
+lilygo_t_display.menu.FlashMode.qio=QIO
+lilygo_t_display.menu.FlashMode.qio.build.flash_mode=dio
+lilygo_t_display.menu.FlashMode.qio.build.boot=qio
+lilygo_t_display.menu.FlashMode.dio=DIO
+lilygo_t_display.menu.FlashMode.dio.build.flash_mode=dio
+lilygo_t_display.menu.FlashMode.dio.build.boot=dio
+
+lilygo_t_display.menu.FlashFreq.80=80MHz
+lilygo_t_display.menu.FlashFreq.80.build.flash_freq=80m
+lilygo_t_display.menu.FlashFreq.40=40MHz
+lilygo_t_display.menu.FlashFreq.40.build.flash_freq=40m
+
+lilygo_t_display.menu.FlashSize.4M=4MB (32Mb)
+lilygo_t_display.menu.FlashSize.4M.build.flash_size=4MB
+lilygo_t_display.menu.FlashSize.16M=16MB (128Mb)
+lilygo_t_display.menu.FlashSize.16M.build.flash_size=16MB
+
+lilygo_t_display.menu.UploadSpeed.921600=921600
+lilygo_t_display.menu.UploadSpeed.921600.upload.speed=921600
+lilygo_t_display.menu.UploadSpeed.115200=115200
+lilygo_t_display.menu.UploadSpeed.115200.upload.speed=115200
+lilygo_t_display.menu.UploadSpeed.256000.windows=256000
+lilygo_t_display.menu.UploadSpeed.256000.upload.speed=256000
+lilygo_t_display.menu.UploadSpeed.230400.windows.upload.speed=256000
+lilygo_t_display.menu.UploadSpeed.230400=230400
+lilygo_t_display.menu.UploadSpeed.230400.upload.speed=230400
+lilygo_t_display.menu.UploadSpeed.460800.linux=460800
+lilygo_t_display.menu.UploadSpeed.460800.macosx=460800
+lilygo_t_display.menu.UploadSpeed.460800.upload.speed=460800
+lilygo_t_display.menu.UploadSpeed.512000.windows=512000
+lilygo_t_display.menu.UploadSpeed.512000.upload.speed=512000
+
+lilygo_t_display.menu.DebugLevel.none=None
+lilygo_t_display.menu.DebugLevel.none.build.code_debug=0
+lilygo_t_display.menu.DebugLevel.error=Error
+lilygo_t_display.menu.DebugLevel.error.build.code_debug=1
+lilygo_t_display.menu.DebugLevel.warn=Warn
+lilygo_t_display.menu.DebugLevel.warn.build.code_debug=2
+lilygo_t_display.menu.DebugLevel.info=Info
+lilygo_t_display.menu.DebugLevel.info.build.code_debug=3
+lilygo_t_display.menu.DebugLevel.debug=Debug
+lilygo_t_display.menu.DebugLevel.debug.build.code_debug=4
+lilygo_t_display.menu.DebugLevel.verbose=Verbose
+lilygo_t_display.menu.DebugLevel.verbose.build.code_debug=5
+
+lilygo_t_display.menu.EraseFlash.none=Disabled
+lilygo_t_display.menu.EraseFlash.none.upload.erase_cmd=
+lilygo_t_display.menu.EraseFlash.all=Enabled
+lilygo_t_display.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lilygo_t_display_s3.name=LilyGo T-Display-S3
+
+lilygo_t_display_s3.bootloader.tool=esptool_py
+lilygo_t_display_s3.bootloader.tool.default=esptool_py
+
+lilygo_t_display_s3.upload.tool=esptool_py
+lilygo_t_display_s3.upload.tool.default=esptool_py
+lilygo_t_display_s3.upload.tool.network=esp_ota
+
+lilygo_t_display_s3.upload.maximum_size=3145728
+lilygo_t_display_s3.upload.maximum_data_size=327680
+lilygo_t_display_s3.upload.speed=921600
+lilygo_t_display_s3.upload.flags=
+lilygo_t_display_s3.upload.extra_flags=
+lilygo_t_display_s3.upload.use_1200bps_touch=false
+lilygo_t_display_s3.upload.wait_for_upload_port=false
+
+lilygo_t_display_s3.serial.disableDTR=false
+lilygo_t_display_s3.serial.disableRTS=false
+
+lilygo_t_display_s3.build.tarch=xtensa
+lilygo_t_display_s3.build.bootloader_addr=0x0
+lilygo_t_display_s3.build.target=esp32s3
+lilygo_t_display_s3.build.mcu=esp32s3
+lilygo_t_display_s3.build.core=esp32
+lilygo_t_display_s3.build.variant=lilygo_t_display_s3
+lilygo_t_display_s3.build.board=LILYGO_T_DISPLAY_S3
+
+lilygo_t_display_s3.build.usb_mode=1
+lilygo_t_display_s3.build.cdc_on_boot=1
+lilygo_t_display_s3.build.msc_on_boot=0
+lilygo_t_display_s3.build.dfu_on_boot=0
+lilygo_t_display_s3.build.f_cpu=240000000L
+lilygo_t_display_s3.build.flash_size=16MB
+lilygo_t_display_s3.build.flash_freq=80m
+lilygo_t_display_s3.build.flash_mode=dio
+lilygo_t_display_s3.build.boot=qio
+lilygo_t_display_s3.build.boot_freq=80m
+lilygo_t_display_s3.build.partitions=app3M_fat9M_16MB
+lilygo_t_display_s3.build.defines=
+lilygo_t_display_s3.build.loop_core=
+lilygo_t_display_s3.build.event_core=
+lilygo_t_display_s3.build.psram_type=opi
+lilygo_t_display_s3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+lilygo_t_display_s3.menu.JTAGAdapter.default=Disabled
+lilygo_t_display_s3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+lilygo_t_display_s3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+lilygo_t_display_s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+lilygo_t_display_s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+
+lilygo_t_display_s3.menu.LoopCore.1=Core 1
+lilygo_t_display_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lilygo_t_display_s3.menu.LoopCore.0=Core 0
+lilygo_t_display_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lilygo_t_display_s3.menu.EventsCore.1=Core 1
+lilygo_t_display_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lilygo_t_display_s3.menu.EventsCore.0=Core 0
+lilygo_t_display_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lilygo_t_display_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+lilygo_t_display_s3.menu.USBMode.hwcdc.build.usb_mode=1
+lilygo_t_display_s3.menu.USBMode.default=USB-OTG (TinyUSB)
+lilygo_t_display_s3.menu.USBMode.default.build.usb_mode=0
+
+lilygo_t_display_s3.menu.CDCOnBoot.cdc=Enabled
+lilygo_t_display_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+lilygo_t_display_s3.menu.CDCOnBoot.default=Disabled
+lilygo_t_display_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+lilygo_t_display_s3.menu.MSCOnBoot.default=Disabled
+lilygo_t_display_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+lilygo_t_display_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+lilygo_t_display_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lilygo_t_display_s3.menu.DFUOnBoot.default=Disabled
+lilygo_t_display_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lilygo_t_display_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+lilygo_t_display_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lilygo_t_display_s3.menu.UploadMode.default=UART0 / Hardware CDC
+lilygo_t_display_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+lilygo_t_display_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+lilygo_t_display_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+lilygo_t_display_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+lilygo_t_display_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+lilygo_t_display_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+lilygo_t_display_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+lilygo_t_display_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+lilygo_t_display_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+lilygo_t_display_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+lilygo_t_display_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+lilygo_t_display_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+lilygo_t_display_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+lilygo_t_display_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+lilygo_t_display_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+lilygo_t_display_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+lilygo_t_display_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+lilygo_t_display_s3.menu.DebugLevel.none=None
+lilygo_t_display_s3.menu.DebugLevel.none.build.code_debug=0
+lilygo_t_display_s3.menu.DebugLevel.error=Error
+lilygo_t_display_s3.menu.DebugLevel.error.build.code_debug=1
+lilygo_t_display_s3.menu.DebugLevel.warn=Warn
+lilygo_t_display_s3.menu.DebugLevel.warn.build.code_debug=2
+lilygo_t_display_s3.menu.DebugLevel.info=Info
+lilygo_t_display_s3.menu.DebugLevel.info.build.code_debug=3
+lilygo_t_display_s3.menu.DebugLevel.debug=Debug
+lilygo_t_display_s3.menu.DebugLevel.debug.build.code_debug=4
+lilygo_t_display_s3.menu.DebugLevel.verbose=Verbose
+lilygo_t_display_s3.menu.DebugLevel.verbose.build.code_debug=5
+
+lilygo_t_display_s3.menu.EraseFlash.none=Disabled
+lilygo_t_display_s3.menu.EraseFlash.none.upload.erase_cmd=
+lilygo_t_display_s3.menu.EraseFlash.all=Enabled
+lilygo_t_display_s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lilygo_t_eth_lite.name=LilyGo T-ETH-Lite
+
+lilygo_t_eth_lite.bootloader.tool=esptool_py
+lilygo_t_eth_lite.bootloader.tool.default=esptool_py
+
+lilygo_t_eth_lite.upload.tool=esptool_py
+lilygo_t_eth_lite.upload.tool.default=esptool_py
+lilygo_t_eth_lite.upload.tool.network=esp_ota
+
+lilygo_t_eth_lite.upload.maximum_size=3145728
+lilygo_t_eth_lite.upload.maximum_data_size=327680
+lilygo_t_eth_lite.upload.speed=921600
+lilygo_t_eth_lite.upload.flags=
+lilygo_t_eth_lite.upload.extra_flags=
+lilygo_t_eth_lite.upload.use_1200bps_touch=false
+lilygo_t_eth_lite.upload.wait_for_upload_port=false
+
+lilygo_t_eth_lite.serial.disableDTR=false
+lilygo_t_eth_lite.serial.disableRTS=false
+
+lilygo_t_eth_lite.build.tarch=xtensa
+lilygo_t_eth_lite.build.bootloader_addr=0x0
+lilygo_t_eth_lite.build.target=esp32s3
+lilygo_t_eth_lite.build.mcu=esp32s3
+lilygo_t_eth_lite.build.core=esp32
+lilygo_t_eth_lite.build.variant=lilygo_t_eth_lite
+lilygo_t_eth_lite.build.board=LILYGO_T_ETH_LITE
+
+lilygo_t_eth_lite.build.usb_mode=1
+lilygo_t_eth_lite.build.cdc_on_boot=0
+lilygo_t_eth_lite.build.msc_on_boot=0
+lilygo_t_eth_lite.build.dfu_on_boot=0
+lilygo_t_eth_lite.build.f_cpu=240000000L
+lilygo_t_eth_lite.build.flash_size=16MB
+lilygo_t_eth_lite.build.flash_freq=80m
+lilygo_t_eth_lite.build.flash_mode=dio
+lilygo_t_eth_lite.build.boot=qio
+lilygo_t_eth_lite.build.boot_freq=80m
+lilygo_t_eth_lite.build.partitions=app3M_fat9M_16MB
+lilygo_t_eth_lite.build.defines=
+lilygo_t_eth_lite.build.loop_core=
+lilygo_t_eth_lite.build.event_core=
+lilygo_t_eth_lite.build.psram_type=opi
+lilygo_t_eth_lite.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+lilygo_t_eth_lite.menu.JTAGAdapter.default=Disabled
+lilygo_t_eth_lite.menu.JTAGAdapter.default.build.copy_jtag_files=0
+lilygo_t_eth_lite.menu.JTAGAdapter.builtin=Integrated USB JTAG
+lilygo_t_eth_lite.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+lilygo_t_eth_lite.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+
+lilygo_t_eth_lite.menu.LoopCore.1=Core 1
+lilygo_t_eth_lite.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lilygo_t_eth_lite.menu.LoopCore.0=Core 0
+lilygo_t_eth_lite.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lilygo_t_eth_lite.menu.EventsCore.1=Core 1
+lilygo_t_eth_lite.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lilygo_t_eth_lite.menu.EventsCore.0=Core 0
+lilygo_t_eth_lite.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lilygo_t_eth_lite.menu.USBMode.hwcdc=Hardware CDC and JTAG
+lilygo_t_eth_lite.menu.USBMode.hwcdc.build.usb_mode=1
+lilygo_t_eth_lite.menu.USBMode.default=USB-OTG (TinyUSB)
+lilygo_t_eth_lite.menu.USBMode.default.build.usb_mode=0
+
+lilygo_t_eth_lite.menu.CDCOnBoot.default=Disabled
+lilygo_t_eth_lite.menu.CDCOnBoot.default.build.cdc_on_boot=0
+lilygo_t_eth_lite.menu.CDCOnBoot.cdc=Enabled
+lilygo_t_eth_lite.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+lilygo_t_eth_lite.menu.MSCOnBoot.default=Disabled
+lilygo_t_eth_lite.menu.MSCOnBoot.default.build.msc_on_boot=0
+lilygo_t_eth_lite.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+lilygo_t_eth_lite.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lilygo_t_eth_lite.menu.DFUOnBoot.default=Disabled
+lilygo_t_eth_lite.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lilygo_t_eth_lite.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+lilygo_t_eth_lite.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lilygo_t_eth_lite.menu.UploadMode.default=UART0 / Hardware CDC
+lilygo_t_eth_lite.menu.UploadMode.default.upload.use_1200bps_touch=false
+lilygo_t_eth_lite.menu.UploadMode.default.upload.wait_for_upload_port=false
+lilygo_t_eth_lite.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+lilygo_t_eth_lite.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+lilygo_t_eth_lite.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+lilygo_t_eth_lite.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+lilygo_t_eth_lite.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+lilygo_t_eth_lite.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+lilygo_t_eth_lite.menu.PartitionScheme.rainmaker=RainMaker 4MB
+lilygo_t_eth_lite.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+lilygo_t_eth_lite.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+lilygo_t_eth_lite.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+lilygo_t_eth_lite.menu.DebugLevel.none=None
+lilygo_t_eth_lite.menu.DebugLevel.none.build.code_debug=0
+lilygo_t_eth_lite.menu.DebugLevel.error=Error
+lilygo_t_eth_lite.menu.DebugLevel.error.build.code_debug=1
+lilygo_t_eth_lite.menu.DebugLevel.warn=Warn
+lilygo_t_eth_lite.menu.DebugLevel.warn.build.code_debug=2
+lilygo_t_eth_lite.menu.DebugLevel.info=Info
+lilygo_t_eth_lite.menu.DebugLevel.info.build.code_debug=3
+lilygo_t_eth_lite.menu.DebugLevel.debug=Debug
+lilygo_t_eth_lite.menu.DebugLevel.debug.build.code_debug=4
+lilygo_t_eth_lite.menu.DebugLevel.verbose=Verbose
+lilygo_t_eth_lite.menu.DebugLevel.verbose.build.code_debug=5
+
+lilygo_t_eth_lite.menu.EraseFlash.none=Disabled
+lilygo_t_eth_lite.menu.EraseFlash.none.upload.erase_cmd=
+lilygo_t_eth_lite.menu.EraseFlash.all=Enabled
+lilygo_t_eth_lite.menu.EraseFlash.all.upload.erase_cmd=-e
+
+
+##############################################################
+
+lilygo_t3s3.name=LilyGo T3-S3
+
+lilygo_t3s3.upload.tool=esptool_py
+lilygo_t3s3.upload.tool.default=esptool_py
+lilygo_t3s3.upload.tool.network=esp_ota
+lilygo_t3s3.upload.maximum_size=1310720
+lilygo_t3s3.upload.maximum_data_size=327680
+lilygo_t3s3.upload.wait_for_upload_port=false
+lilygo_t3s3.upload.speed=460800
+lilygo_t3s3.upload.flags=
+lilygo_t3s3.upload.extra_flags=
+
+lilygo_t3s3.bootloader.tool=esptool_py
+lilygo_t3s3.bootloader.tool.default=esptool_py
+
+lilygo_t3s3.serial.disableDTR=true
+lilygo_t3s3.serial.disableRTS=true
+
+lilygo_t3s3.build.tarch=xtensa
+lilygo_t3s3.build.bootloader_addr=0x0
+lilygo_t3s3.build.mcu=esp32s3
+lilygo_t3s3.build.core=esp32
+lilygo_t3s3.build.target=esp32s3
+lilygo_t3s3.build.board=LILYGO_T3_S3
+
+lilygo_t3s3.build.usb_mode=1
+lilygo_t3s3.build.cdc_on_boot=1
+lilygo_t3s3.build.msc_on_boot=0
+lilygo_t3s3.build.dfu_on_boot=0
+
+lilygo_t3s3.build.f_cpu=240000000L
+lilygo_t3s3.build.flash_size=4MB
+lilygo_t3s3.build.flash_freq=80m
+lilygo_t3s3.build.flash_mode=dio
+lilygo_t3s3.build.boot=dio
+lilygo_t3s3.build.partitions=default
+lilygo_t3s3.build.defines=
+
+lilygo_t3s3.menu.PSRAM.disabled=Disabled
+lilygo_t3s3.menu.PSRAM.disabled.build.defines=
+lilygo_t3s3.menu.PSRAM.enabled=Enabled
+lilygo_t3s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+lilygo_t3s3.menu.PSRAM.enabled.build.psram_type=qspi
+
+lilygo_t3s3.menu.LoopCore.1=Core 1
+lilygo_t3s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lilygo_t3s3.menu.LoopCore.0=Core 0
+lilygo_t3s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lilygo_t3s3.menu.EventsCore.1=Core 1
+lilygo_t3s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lilygo_t3s3.menu.EventsCore.0=Core 0
+lilygo_t3s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lilygo_t3s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+lilygo_t3s3.menu.USBMode.hwcdc.build.usb_mode=1
+lilygo_t3s3.menu.USBMode.default=USB-OTG (TinyUSB)
+lilygo_t3s3.menu.USBMode.default.build.usb_mode=0
+
+lilygo_t3s3.menu.CDCOnBoot.default=Disabled
+lilygo_t3s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+lilygo_t3s3.menu.CDCOnBoot.cdc=Enabled
+lilygo_t3s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+lilygo_t3s3.menu.MSCOnBoot.default=Disabled
+lilygo_t3s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+lilygo_t3s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+lilygo_t3s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lilygo_t3s3.menu.DFUOnBoot.default=Disabled
+lilygo_t3s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lilygo_t3s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+lilygo_t3s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lilygo_t3s3.menu.UploadMode.default=UART0 / Hardware CDC
+lilygo_t3s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+lilygo_t3s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+lilygo_t3s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+lilygo_t3s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+lilygo_t3s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+lilygo_t3s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lilygo_t3s3.menu.PartitionScheme.default.build.partitions=default
+lilygo_t3s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lilygo_t3s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lilygo_t3s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+lilygo_t3s3.menu.PartitionScheme.minimal.build.partitions=minimal
+lilygo_t3s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lilygo_t3s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lilygo_t3s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lilygo_t3s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lilygo_t3s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lilygo_t3s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lilygo_t3s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lilygo_t3s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lilygo_t3s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lilygo_t3s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lilygo_t3s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lilygo_t3s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lilygo_t3s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lilygo_t3s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lilygo_t3s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+lilygo_t3s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+lilygo_t3s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+lilygo_t3s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+lilygo_t3s3.menu.CPUFreq.240=240MHz (WiFi/BT)
+lilygo_t3s3.menu.CPUFreq.240.build.f_cpu=240000000L
+lilygo_t3s3.menu.CPUFreq.160=160MHz (WiFi/BT)
+lilygo_t3s3.menu.CPUFreq.160.build.f_cpu=160000000L
+lilygo_t3s3.menu.CPUFreq.80=80MHz (WiFi/BT)
+lilygo_t3s3.menu.CPUFreq.80.build.f_cpu=80000000L
+
+lilygo_t3s3.menu.FlashMode.qio=QIO
+lilygo_t3s3.menu.FlashMode.qio.build.flash_mode=dio
+lilygo_t3s3.menu.FlashMode.qio.build.boot=qio
+lilygo_t3s3.menu.FlashMode.dio=DIO
+lilygo_t3s3.menu.FlashMode.dio.build.flash_mode=dio
+lilygo_t3s3.menu.FlashMode.dio.build.boot=dio
+
+lilygo_t3s3.menu.FlashFreq.80=80MHz
+lilygo_t3s3.menu.FlashFreq.80.build.flash_freq=80m
+lilygo_t3s3.menu.FlashFreq.40=40MHz
+lilygo_t3s3.menu.FlashFreq.40.build.flash_freq=40m
+
+lilygo_t3s3.menu.UploadSpeed.921600=921600
+lilygo_t3s3.menu.UploadSpeed.921600.upload.speed=921600
+lilygo_t3s3.menu.UploadSpeed.115200=115200
+lilygo_t3s3.menu.UploadSpeed.115200.upload.speed=115200
+lilygo_t3s3.menu.UploadSpeed.256000.windows=256000
+lilygo_t3s3.menu.UploadSpeed.256000.upload.speed=256000
+lilygo_t3s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+lilygo_t3s3.menu.UploadSpeed.230400=230400
+lilygo_t3s3.menu.UploadSpeed.230400.upload.speed=230400
+lilygo_t3s3.menu.UploadSpeed.460800.linux=460800
+lilygo_t3s3.menu.UploadSpeed.460800.macosx=460800
+lilygo_t3s3.menu.UploadSpeed.460800.upload.speed=460800
+lilygo_t3s3.menu.UploadSpeed.512000.windows=512000
+lilygo_t3s3.menu.UploadSpeed.512000.upload.speed=512000
+
+lilygo_t3s3.menu.DebugLevel.none=None
+lilygo_t3s3.menu.DebugLevel.none.build.code_debug=0
+lilygo_t3s3.menu.DebugLevel.error=Error
+lilygo_t3s3.menu.DebugLevel.error.build.code_debug=1
+lilygo_t3s3.menu.DebugLevel.warn=Warn
+lilygo_t3s3.menu.DebugLevel.warn.build.code_debug=2
+lilygo_t3s3.menu.DebugLevel.info=Info
+lilygo_t3s3.menu.DebugLevel.info.build.code_debug=3
+lilygo_t3s3.menu.DebugLevel.debug=Debug
+lilygo_t3s3.menu.DebugLevel.debug.build.code_debug=4
+lilygo_t3s3.menu.DebugLevel.verbose=Verbose
+lilygo_t3s3.menu.DebugLevel.verbose.build.code_debug=5
+
+lilygo_t3s3.menu.EraseFlash.none=Disabled
+lilygo_t3s3.menu.EraseFlash.none.upload.erase_cmd=
+lilygo_t3s3.menu.EraseFlash.all=Enabled
+lilygo_t3s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+lilygo_t3s3.menu.Revision.Radio_SX1262=Radio-SX1262
+lilygo_t3s3.menu.Revision.Radio_SX1262.build.board=LILYGO_T3S3_SX1262
+lilygo_t3s3.menu.Revision.Radio_SX1262.build.variant=lilygo_t3_s3_sx1262
+
+lilygo_t3s3.menu.Revision.Radio_SX1276=Radio-SX1276
+lilygo_t3s3.menu.Revision.Radio_SX1276.build.board=LILYGO_T3S3_SX1276
+lilygo_t3s3.menu.Revision.Radio_SX1276.build.variant=lilygo_t3_s3_sx127x
+
+lilygo_t3s3.menu.Revision.Radio_SX1278=Radio-SX1278
+lilygo_t3s3.menu.Revision.Radio_SX1278.build.board=LILYGO_T3S3_SX1278
+lilygo_t3s3.menu.Revision.Radio_SX1278.build.variant=lilygo_t3_s3_sx127x
+
+lilygo_t3s3.menu.Revision.Radio_SX1280=Radio-SX1280
+lilygo_t3s3.menu.Revision.Radio_SX1280.build.board=LILYGO_T3S3_SX1280
+lilygo_t3s3.menu.Revision.Radio_SX1280.build.variant=lilygo_t3_s3_sx1280
+
+lilygo_t3s3.menu.Revision.Radio_SX1280PA=Radio-SX1280PA
+lilygo_t3s3.menu.Revision.Radio_SX1280PA.build.board=LILYGO_T3S3_SX1280PA
+lilygo_t3s3.menu.Revision.Radio_SX1280PA.build.variant=lilygo_t3_s3_sx1280pa
+
+lilygo_t3s3.menu.Revision.Radio_LR1121=Radio-LR1121
+lilygo_t3s3.menu.Revision.Radio_LR1121.build.board=LILYGO_T3S3_LR1121
+lilygo_t3s3.menu.Revision.Radio_LR1121.build.variant=lilygo_t3_s3_lr1121
+
+##############################################################
+
+twatchs3.name=LilyGo T-Watch-S3
+
+twatchs3.bootloader.tool=esptool_py
+twatchs3.bootloader.tool.default=esptool_py
+
+twatchs3.upload.tool=esptool_py
+twatchs3.upload.tool.default=esptool_py
+twatchs3.upload.tool.network=esp_ota
+
+twatchs3.upload.maximum_size=1310720
+twatchs3.upload.maximum_data_size=327680
+twatchs3.upload.flags=
+twatchs3.upload.extra_flags=
+twatchs3.upload.use_1200bps_touch=false
+twatchs3.upload.wait_for_upload_port=false
+
+twatchs3.serial.disableDTR=false
+twatchs3.serial.disableRTS=false
+
+twatchs3.build.tarch=xtensa
+twatchs3.build.bootloader_addr=0x0
+twatchs3.build.target=esp32s3
+twatchs3.build.mcu=esp32s3
+twatchs3.build.core=esp32
+twatchs3.build.variant=lilygo_twatch_s3
+twatchs3.build.board=T_WATCH_S3
+
+twatchs3.build.usb_mode=1
+twatchs3.build.cdc_on_boot=0
+twatchs3.build.msc_on_boot=0
+twatchs3.build.dfu_on_boot=0
+twatchs3.build.f_cpu=240000000L
+twatchs3.build.flash_size=16MB
+twatchs3.build.flash_freq=80m
+twatchs3.build.flash_mode=dio
+twatchs3.build.boot=qio
+twatchs3.build.boot_freq=80m
+twatchs3.build.partitions=app3M_fat9M_16MB
+twatchs3.build.defines=-DBOARD_HAS_PSRAM -DARDUINO_T_WATCH_S3
+twatchs3.build.loop_core=
+twatchs3.build.event_core=
+twatchs3.build.psram_type=opi
+twatchs3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+twatchs3.menu.JTAGAdapter.default=Disabled
+twatchs3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+twatchs3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+twatchs3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+twatchs3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+
+twatchs3.menu.LoopCore.1=Core 1
+twatchs3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+twatchs3.menu.LoopCore.0=Core 0
+twatchs3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+twatchs3.menu.EventsCore.1=Core 1
+twatchs3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+twatchs3.menu.EventsCore.0=Core 0
+twatchs3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+twatchs3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+twatchs3.menu.USBMode.hwcdc.build.usb_mode=1
+twatchs3.menu.USBMode.default=USB-OTG (TinyUSB)
+twatchs3.menu.USBMode.default.build.usb_mode=0
+
+twatchs3.menu.CDCOnBoot.default=Enabled
+twatchs3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+twatchs3.menu.CDCOnBoot.cdc=Disabled
+twatchs3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+twatchs3.menu.MSCOnBoot.default=Disabled
+twatchs3.menu.MSCOnBoot.default.build.msc_on_boot=0
+twatchs3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+twatchs3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+twatchs3.menu.DFUOnBoot.default=Disabled
+twatchs3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+twatchs3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+twatchs3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+twatchs3.menu.UploadMode.default=UART0 / Hardware CDC
+twatchs3.menu.UploadMode.default.upload.use_1200bps_touch=false
+twatchs3.menu.UploadMode.default.upload.wait_for_upload_port=false
+twatchs3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+twatchs3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+twatchs3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+twatchs3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+twatchs3.menu.PartitionScheme.fatflash.build.partitions=ffat
+twatchs3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+twatchs3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+twatchs3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+twatchs3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+twatchs3.menu.PartitionScheme.rainmaker=RainMaker
+twatchs3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+twatchs3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+twatchs3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+twatchs3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+twatchs3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+twatchs3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+twatchs3.menu.PartitionScheme.custom=Custom
+twatchs3.menu.PartitionScheme.custom.build.partitions=
+twatchs3.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+twatchs3.menu.CPUFreq.240=240MHz (WiFi)
+twatchs3.menu.CPUFreq.240.build.f_cpu=240000000L
+twatchs3.menu.CPUFreq.160=160MHz (WiFi)
+twatchs3.menu.CPUFreq.160.build.f_cpu=160000000L
+twatchs3.menu.CPUFreq.80=80MHz (WiFi)
+twatchs3.menu.CPUFreq.80.build.f_cpu=80000000L
+twatchs3.menu.CPUFreq.40=40MHz
+twatchs3.menu.CPUFreq.40.build.f_cpu=40000000L
+twatchs3.menu.CPUFreq.20=20MHz
+twatchs3.menu.CPUFreq.20.build.f_cpu=20000000L
+twatchs3.menu.CPUFreq.10=10MHz
+twatchs3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+twatchs3.menu.UploadSpeed.921600=921600
+twatchs3.menu.UploadSpeed.921600.upload.speed=921600
+twatchs3.menu.UploadSpeed.115200=115200
+twatchs3.menu.UploadSpeed.115200.upload.speed=115200
+twatchs3.menu.UploadSpeed.256000.windows=256000
+twatchs3.menu.UploadSpeed.256000.upload.speed=256000
+twatchs3.menu.UploadSpeed.230400.windows.upload.speed=256000
+twatchs3.menu.UploadSpeed.230400=230400
+twatchs3.menu.UploadSpeed.230400.upload.speed=230400
+twatchs3.menu.UploadSpeed.460800.linux=460800
+twatchs3.menu.UploadSpeed.460800.macosx=460800
+twatchs3.menu.UploadSpeed.460800.upload.speed=460800
+twatchs3.menu.UploadSpeed.512000.windows=512000
+twatchs3.menu.UploadSpeed.512000.upload.speed=512000
+
+twatchs3.menu.DebugLevel.none=None
+twatchs3.menu.DebugLevel.none.build.code_debug=0
+twatchs3.menu.DebugLevel.error=Error
+twatchs3.menu.DebugLevel.error.build.code_debug=1
+twatchs3.menu.DebugLevel.warn=Warn
+twatchs3.menu.DebugLevel.warn.build.code_debug=2
+twatchs3.menu.DebugLevel.info=Info
+twatchs3.menu.DebugLevel.info.build.code_debug=3
+twatchs3.menu.DebugLevel.debug=Debug
+twatchs3.menu.DebugLevel.debug.build.code_debug=4
+twatchs3.menu.DebugLevel.verbose=Verbose
+twatchs3.menu.DebugLevel.verbose.build.code_debug=5
+
+twatchs3.menu.EraseFlash.none=Disabled
+twatchs3.menu.EraseFlash.none.upload.erase_cmd=
+twatchs3.menu.EraseFlash.all=Enabled
+twatchs3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+twatchs3.menu.Revision.Radio_SX1262=Radio-SX1262
+twatchs3.menu.Revision.Radio_SX1262.build.board=LILYGO_LORA_SX1262
+twatchs3.menu.Revision.Radio_SX1280=Radio-SX1280
+twatchs3.menu.Revision.Radio_SX1280.build.board=LILYGO_LORA_SX1280
+twatchs3.menu.Revision.Radio_CC1101=Radio-CC1101
+twatchs3.menu.Revision.Radio_CC1101.build.board=LILYGO_LORA_CC1101
+
+##############################################################
+
+
+twatch_ultra.name=LilyGo T-Watch-Ultra
+
+twatch_ultra.bootloader.tool=esptool_py
+twatch_ultra.bootloader.tool.default=esptool_py
+
+twatch_ultra.upload.tool=esptool_py
+twatch_ultra.upload.tool.default=esptool_py
+twatch_ultra.upload.tool.network=esp_ota
+
+twatch_ultra.upload.maximum_size=1310720
+twatch_ultra.upload.maximum_data_size=327680
+twatch_ultra.upload.flags=
+twatch_ultra.upload.extra_flags=
+twatch_ultra.upload.use_1200bps_touch=false
+twatch_ultra.upload.wait_for_upload_port=false
+
+twatch_ultra.serial.disableDTR=false
+twatch_ultra.serial.disableRTS=false
+
+twatch_ultra.build.tarch=xtensa
+twatch_ultra.build.bootloader_addr=0x0
+twatch_ultra.build.target=esp32s3
+twatch_ultra.build.mcu=esp32s3
+twatch_ultra.build.core=esp32
+twatch_ultra.build.variant=lilygo_twatch_ultra
+twatch_ultra.build.board=T_WATCH_S3_ULTRA
+
+twatch_ultra.build.usb_mode=1
+twatch_ultra.build.cdc_on_boot=1
+twatch_ultra.build.msc_on_boot=0
+twatch_ultra.build.dfu_on_boot=0
+twatch_ultra.build.f_cpu=240000000L
+twatch_ultra.build.flash_size=16MB
+twatch_ultra.build.flash_freq=80m
+twatch_ultra.build.flash_mode=dio
+twatch_ultra.build.boot=qio
+twatch_ultra.build.boot_freq=80m
+twatch_ultra.build.partitions=app3M_fat9M_16MB
+twatch_ultra.build.defines=-DBOARD_HAS_PSRAM -DARDUINO_T_WATCH_S3_ULTRA
+twatch_ultra.build.loop_core=
+twatch_ultra.build.event_core=
+twatch_ultra.build.psram_type=qspi
+twatch_ultra.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+twatch_ultra.menu.JTAGAdapter.default=Disabled
+twatch_ultra.menu.JTAGAdapter.default.build.copy_jtag_files=0
+twatch_ultra.menu.JTAGAdapter.builtin=Integrated USB JTAG
+twatch_ultra.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+twatch_ultra.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+
+twatch_ultra.menu.LoopCore.1=Core 1
+twatch_ultra.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+twatch_ultra.menu.LoopCore.0=Core 0
+twatch_ultra.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+twatch_ultra.menu.EventsCore.1=Core 1
+twatch_ultra.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+twatch_ultra.menu.EventsCore.0=Core 0
+twatch_ultra.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+twatch_ultra.menu.USBMode.hwcdc=Hardware CDC and JTAG
+twatch_ultra.menu.USBMode.hwcdc.build.usb_mode=1
+twatch_ultra.menu.USBMode.default=USB-OTG (TinyUSB)
+twatch_ultra.menu.USBMode.default.build.usb_mode=0
+
+twatch_ultra.menu.CDCOnBoot.default=Enabled
+twatch_ultra.menu.CDCOnBoot.default.build.cdc_on_boot=1
+twatch_ultra.menu.CDCOnBoot.cdc=Disabled
+twatch_ultra.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+twatch_ultra.menu.MSCOnBoot.default=Disabled
+twatch_ultra.menu.MSCOnBoot.default.build.msc_on_boot=0
+twatch_ultra.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+twatch_ultra.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+twatch_ultra.menu.DFUOnBoot.default=Disabled
+twatch_ultra.menu.DFUOnBoot.default.build.dfu_on_boot=0
+twatch_ultra.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+twatch_ultra.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+twatch_ultra.menu.UploadMode.default=UART0 / Hardware CDC
+twatch_ultra.menu.UploadMode.default.upload.use_1200bps_touch=false
+twatch_ultra.menu.UploadMode.default.upload.wait_for_upload_port=false
+twatch_ultra.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+twatch_ultra.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+twatch_ultra.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+twatch_ultra.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+twatch_ultra.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+twatch_ultra.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+twatch_ultra.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+twatch_ultra.menu.PartitionScheme.fatflash.build.partitions=ffat
+twatch_ultra.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+twatch_ultra.menu.PartitionScheme.rainmaker=RainMaker
+twatch_ultra.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+twatch_ultra.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+twatch_ultra.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+twatch_ultra.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+twatch_ultra.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+twatch_ultra.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+twatch_ultra.menu.PartitionScheme.custom=Custom
+twatch_ultra.menu.PartitionScheme.custom.build.partitions=
+twatch_ultra.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+twatch_ultra.menu.CPUFreq.240=240MHz (WiFi)
+twatch_ultra.menu.CPUFreq.240.build.f_cpu=240000000L
+twatch_ultra.menu.CPUFreq.160=160MHz (WiFi)
+twatch_ultra.menu.CPUFreq.160.build.f_cpu=160000000L
+twatch_ultra.menu.CPUFreq.80=80MHz (WiFi)
+twatch_ultra.menu.CPUFreq.80.build.f_cpu=80000000L
+twatch_ultra.menu.CPUFreq.40=40MHz
+twatch_ultra.menu.CPUFreq.40.build.f_cpu=40000000L
+twatch_ultra.menu.CPUFreq.20=20MHz
+twatch_ultra.menu.CPUFreq.20.build.f_cpu=20000000L
+twatch_ultra.menu.CPUFreq.10=10MHz
+twatch_ultra.menu.CPUFreq.10.build.f_cpu=10000000L
+
+twatch_ultra.menu.UploadSpeed.921600=921600
+twatch_ultra.menu.UploadSpeed.921600.upload.speed=921600
+twatch_ultra.menu.UploadSpeed.115200=115200
+twatch_ultra.menu.UploadSpeed.115200.upload.speed=115200
+twatch_ultra.menu.UploadSpeed.256000.windows=256000
+twatch_ultra.menu.UploadSpeed.256000.upload.speed=256000
+twatch_ultra.menu.UploadSpeed.230400.windows.upload.speed=256000
+twatch_ultra.menu.UploadSpeed.230400=230400
+twatch_ultra.menu.UploadSpeed.230400.upload.speed=230400
+twatch_ultra.menu.UploadSpeed.460800.linux=460800
+twatch_ultra.menu.UploadSpeed.460800.macosx=460800
+twatch_ultra.menu.UploadSpeed.460800.upload.speed=460800
+twatch_ultra.menu.UploadSpeed.512000.windows=512000
+twatch_ultra.menu.UploadSpeed.512000.upload.speed=512000
+
+twatch_ultra.menu.DebugLevel.none=None
+twatch_ultra.menu.DebugLevel.none.build.code_debug=0
+twatch_ultra.menu.DebugLevel.error=Error
+twatch_ultra.menu.DebugLevel.error.build.code_debug=1
+twatch_ultra.menu.DebugLevel.warn=Warn
+twatch_ultra.menu.DebugLevel.warn.build.code_debug=2
+twatch_ultra.menu.DebugLevel.info=Info
+twatch_ultra.menu.DebugLevel.info.build.code_debug=3
+twatch_ultra.menu.DebugLevel.debug=Debug
+twatch_ultra.menu.DebugLevel.debug.build.code_debug=4
+twatch_ultra.menu.DebugLevel.verbose=Verbose
+twatch_ultra.menu.DebugLevel.verbose.build.code_debug=5
+
+twatch_ultra.menu.EraseFlash.none=Disabled
+twatch_ultra.menu.EraseFlash.none.upload.erase_cmd=
+twatch_ultra.menu.EraseFlash.all=Enabled
+twatch_ultra.menu.EraseFlash.all.upload.erase_cmd=-e
+
+twatch_ultra.menu.Revision.Radio_SX1280=Radio-SX1280
+twatch_ultra.menu.Revision.Radio_SX1280.build.board=LILYGO_LORA_SX1280
+twatch_ultra.menu.Revision.Radio_SX1262=Radio-SX1262
+twatch_ultra.menu.Revision.Radio_SX1262.build.board=LILYGO_LORA_SX1262
+twatch_ultra.menu.Revision.Radio_CC1101=Radio-CC1101
+twatch_ultra.menu.Revision.Radio_CC1101.build.board=LILYGO_LORA_CC1101
+
+
+##############################################################
+
+tlora_pager.name=LilyGo-T-LoRa-Pager
+
+tlora_pager.bootloader.tool=esptool_py
+tlora_pager.bootloader.tool.default=esptool_py
+
+tlora_pager.upload.tool=esptool_py
+tlora_pager.upload.tool.default=esptool_py
+tlora_pager.upload.tool.network=esp_ota
+
+tlora_pager.upload.maximum_size=1310720
+tlora_pager.upload.maximum_data_size=327680
+tlora_pager.upload.flags=
+tlora_pager.upload.extra_flags=
+tlora_pager.upload.use_1200bps_touch=false
+tlora_pager.upload.wait_for_upload_port=false
+
+tlora_pager.serial.disableDTR=false
+tlora_pager.serial.disableRTS=false
+
+tlora_pager.build.tarch=xtensa
+tlora_pager.build.bootloader_addr=0x0
+tlora_pager.build.target=esp32s3
+tlora_pager.build.mcu=esp32s3
+tlora_pager.build.core=esp32
+tlora_pager.build.variant=lilygo_tlora_pager
+tlora_pager.build.board=T_LORA_PAGER
+
+tlora_pager.build.usb_mode=1
+tlora_pager.build.cdc_on_boot=1
+tlora_pager.build.msc_on_boot=0
+tlora_pager.build.dfu_on_boot=0
+tlora_pager.build.f_cpu=240000000L
+tlora_pager.build.flash_size=16MB
+tlora_pager.build.flash_freq=80m
+tlora_pager.build.flash_mode=dio
+tlora_pager.build.boot=qio
+tlora_pager.build.boot_freq=80m
+tlora_pager.build.partitions=app3M_fat9M_16MB
+tlora_pager.build.defines=-DBOARD_HAS_PSRAM -DARDUINO_T_LORA_PAGER
+tlora_pager.build.loop_core=
+tlora_pager.build.event_core=
+tlora_pager.build.psram_type=qspi
+tlora_pager.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+tlora_pager.menu.JTAGAdapter.default=Disabled
+tlora_pager.menu.JTAGAdapter.default.build.copy_jtag_files=0
+tlora_pager.menu.JTAGAdapter.builtin=Integrated USB JTAG
+tlora_pager.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+tlora_pager.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+
+tlora_pager.menu.LoopCore.1=Core 1
+tlora_pager.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+tlora_pager.menu.LoopCore.0=Core 0
+tlora_pager.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+tlora_pager.menu.EventsCore.1=Core 1
+tlora_pager.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+tlora_pager.menu.EventsCore.0=Core 0
+tlora_pager.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+tlora_pager.menu.USBMode.hwcdc=Hardware CDC and JTAG
+tlora_pager.menu.USBMode.hwcdc.build.usb_mode=1
+tlora_pager.menu.USBMode.default=USB-OTG (TinyUSB)
+tlora_pager.menu.USBMode.default.build.usb_mode=0
+
+tlora_pager.menu.CDCOnBoot.default=Enabled
+tlora_pager.menu.CDCOnBoot.default.build.cdc_on_boot=1
+tlora_pager.menu.CDCOnBoot.cdc=Disabled
+tlora_pager.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+tlora_pager.menu.MSCOnBoot.default=Disabled
+tlora_pager.menu.MSCOnBoot.default.build.msc_on_boot=0
+tlora_pager.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+tlora_pager.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+tlora_pager.menu.DFUOnBoot.default=Disabled
+tlora_pager.menu.DFUOnBoot.default.build.dfu_on_boot=0
+tlora_pager.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+tlora_pager.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+tlora_pager.menu.UploadMode.default=UART0 / Hardware CDC
+tlora_pager.menu.UploadMode.default.upload.use_1200bps_touch=false
+tlora_pager.menu.UploadMode.default.upload.wait_for_upload_port=false
+tlora_pager.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+tlora_pager.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+tlora_pager.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+tlora_pager.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+tlora_pager.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+tlora_pager.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+tlora_pager.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+tlora_pager.menu.PartitionScheme.fatflash.build.partitions=ffat
+tlora_pager.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+tlora_pager.menu.PartitionScheme.rainmaker=RainMaker
+tlora_pager.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+tlora_pager.menu.PartitionScheme.rainmaker.upload.maximum_size=3145728
+tlora_pager.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+tlora_pager.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+tlora_pager.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+tlora_pager.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+tlora_pager.menu.PartitionScheme.custom=Custom
+tlora_pager.menu.PartitionScheme.custom.build.partitions=
+tlora_pager.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+tlora_pager.menu.CPUFreq.240=240MHz (WiFi)
+tlora_pager.menu.CPUFreq.240.build.f_cpu=240000000L
+tlora_pager.menu.CPUFreq.160=160MHz (WiFi)
+tlora_pager.menu.CPUFreq.160.build.f_cpu=160000000L
+tlora_pager.menu.CPUFreq.80=80MHz (WiFi)
+tlora_pager.menu.CPUFreq.80.build.f_cpu=80000000L
+tlora_pager.menu.CPUFreq.40=40MHz
+tlora_pager.menu.CPUFreq.40.build.f_cpu=40000000L
+tlora_pager.menu.CPUFreq.20=20MHz
+tlora_pager.menu.CPUFreq.20.build.f_cpu=20000000L
+tlora_pager.menu.CPUFreq.10=10MHz
+tlora_pager.menu.CPUFreq.10.build.f_cpu=10000000L
+
+tlora_pager.menu.UploadSpeed.921600=921600
+tlora_pager.menu.UploadSpeed.921600.upload.speed=921600
+tlora_pager.menu.UploadSpeed.115200=115200
+tlora_pager.menu.UploadSpeed.115200.upload.speed=115200
+tlora_pager.menu.UploadSpeed.256000.windows=256000
+tlora_pager.menu.UploadSpeed.256000.upload.speed=256000
+tlora_pager.menu.UploadSpeed.230400.windows.upload.speed=256000
+tlora_pager.menu.UploadSpeed.230400=230400
+tlora_pager.menu.UploadSpeed.230400.upload.speed=230400
+tlora_pager.menu.UploadSpeed.460800.linux=460800
+tlora_pager.menu.UploadSpeed.460800.macosx=460800
+tlora_pager.menu.UploadSpeed.460800.upload.speed=460800
+tlora_pager.menu.UploadSpeed.512000.windows=512000
+tlora_pager.menu.UploadSpeed.512000.upload.speed=512000
+
+tlora_pager.menu.DebugLevel.none=None
+tlora_pager.menu.DebugLevel.none.build.code_debug=0
+tlora_pager.menu.DebugLevel.error=Error
+tlora_pager.menu.DebugLevel.error.build.code_debug=1
+tlora_pager.menu.DebugLevel.warn=Warn
+tlora_pager.menu.DebugLevel.warn.build.code_debug=2
+tlora_pager.menu.DebugLevel.info=Info
+tlora_pager.menu.DebugLevel.info.build.code_debug=3
+tlora_pager.menu.DebugLevel.debug=Debug
+tlora_pager.menu.DebugLevel.debug.build.code_debug=4
+tlora_pager.menu.DebugLevel.verbose=Verbose
+tlora_pager.menu.DebugLevel.verbose.build.code_debug=5
+
+tlora_pager.menu.EraseFlash.none=Disabled
+tlora_pager.menu.EraseFlash.none.upload.erase_cmd=
+tlora_pager.menu.EraseFlash.all=Enabled
+tlora_pager.menu.EraseFlash.all.upload.erase_cmd=-e
+
+
+tlora_pager.menu.Revision.Radio_SX1280=Radio-SX1280
+tlora_pager.menu.Revision.Radio_SX1280.build.board=LILYGO_LORA_SX1280
+tlora_pager.menu.Revision.Radio_SX1262=Radio-SX1262
+tlora_pager.menu.Revision.Radio_SX1262.build.board=LILYGO_LORA_SX1262
+tlora_pager.menu.Revision.Radio_CC1101=Radio-CC1101
+tlora_pager.menu.Revision.Radio_CC1101.build.board=LILYGO_LORA_CC1101
+
+##############################################################
+
+micros2.name=microS2
+micros2.vid.0=0x239A
+micros2.pid.0=0x80C5
+
+micros2.bootloader.tool=esptool_py
+micros2.bootloader.tool.default=esptool_py
+
+micros2.upload.tool=esptool_py
+micros2.upload.tool.default=esptool_py
+micros2.upload.tool.network=esp_ota
+
+micros2.upload.maximum_size=1310720
+micros2.upload.maximum_data_size=327680
+micros2.upload.flags=
+micros2.upload.extra_flags=
+micros2.upload.use_1200bps_touch=true
+micros2.upload.wait_for_upload_port=true
+
+micros2.serial.disableDTR=false
+micros2.serial.disableRTS=false
+
+micros2.build.tarch=xtensa
+micros2.build.bootloader_addr=0x1000
+micros2.build.target=esp32s2
+micros2.build.mcu=esp32s2
+micros2.build.core=esp32
+micros2.build.variant=micro_s2
+micros2.build.board=MICROS2
+
+micros2.build.cdc_on_boot=1
+micros2.build.msc_on_boot=1
+micros2.build.dfu_on_boot=0
+micros2.build.f_cpu=240000000L
+micros2.build.flash_size=16MB
+micros2.build.flash_freq=80m
+micros2.build.flash_mode=dio
+micros2.build.boot=qio
+micros2.build.partitions=fatflash
+micros2.build.defines=
+
+micros2.menu.CDCOnBoot.cdc=Enabled
+micros2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+micros2.menu.CDCOnBoot.default=Disabled
+micros2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+micros2.menu.MSCOnBoot.msc=Enabled
+micros2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+micros2.menu.MSCOnBoot.default=Disabled
+micros2.menu.MSCOnBoot.default.build.msc_on_boot=0
+
+micros2.menu.DFUOnBoot.default=Disabled
+micros2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+micros2.menu.DFUOnBoot.dfu=Enabled
+micros2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+micros2.menu.PSRAM.enabled=Enabled
+micros2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+micros2.menu.PSRAM.disabled=Disabled
+micros2.menu.PSRAM.disabled.build.defines=
+
+micros2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+micros2.menu.PartitionScheme.fatflash.build.partitions=ffat
+micros2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+micros2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+micros2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+micros2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+micros2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+micros2.menu.PartitionScheme.default.build.partitions=default
+micros2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+micros2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+micros2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+micros2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+micros2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+micros2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+micros2.menu.PartitionScheme.minimal.build.partitions=minimal
+micros2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+micros2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+micros2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+micros2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+micros2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+micros2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+micros2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+micros2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+micros2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+micros2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+micros2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+micros2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+micros2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+micros2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+micros2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+micros2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+micros2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+micros2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+micros2.menu.CPUFreq.240=240MHz (WiFi)
+micros2.menu.CPUFreq.240.build.f_cpu=240000000L
+micros2.menu.CPUFreq.160=160MHz (WiFi)
+micros2.menu.CPUFreq.160.build.f_cpu=160000000L
+micros2.menu.CPUFreq.80=80MHz (WiFi)
+micros2.menu.CPUFreq.80.build.f_cpu=80000000L
+micros2.menu.CPUFreq.40=40MHz
+micros2.menu.CPUFreq.40.build.f_cpu=40000000L
+micros2.menu.CPUFreq.20=20MHz
+micros2.menu.CPUFreq.20.build.f_cpu=20000000L
+micros2.menu.CPUFreq.10=10MHz
+micros2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+micros2.menu.FlashSize.16M=16MB (128Mb)
+micros2.menu.FlashSize.16M.build.flash_size=16MB
+micros2.menu.FlashSize.4M=4MB (32Mb)
+micros2.menu.FlashSize.4M.build.flash_size=4MB
+micros2.menu.FlashSize.8M=8MB (64Mb)
+micros2.menu.FlashSize.8M.build.flash_size=8MB
+micros2.menu.FlashSize.2M=2MB (16Mb)
+micros2.menu.FlashSize.2M.build.flash_size=2MB
+
+micros2.menu.UploadSpeed.921600=921600
+micros2.menu.UploadSpeed.921600.upload.speed=921600
+micros2.menu.UploadSpeed.115200=115200
+micros2.menu.UploadSpeed.115200.upload.speed=115200
+micros2.menu.UploadSpeed.256000.windows=256000
+micros2.menu.UploadSpeed.256000.upload.speed=256000
+micros2.menu.UploadSpeed.230400.windows.upload.speed=256000
+micros2.menu.UploadSpeed.230400=230400
+micros2.menu.UploadSpeed.230400.upload.speed=230400
+micros2.menu.UploadSpeed.460800.linux=460800
+micros2.menu.UploadSpeed.460800.macosx=460800
+micros2.menu.UploadSpeed.460800.upload.speed=460800
+
+micros2.menu.DebugLevel.none=None
+micros2.menu.DebugLevel.none.build.code_debug=0
+micros2.menu.DebugLevel.error=Error
+micros2.menu.DebugLevel.error.build.code_debug=1
+micros2.menu.DebugLevel.warn=Warn
+micros2.menu.DebugLevel.warn.build.code_debug=2
+micros2.menu.DebugLevel.info=Info
+micros2.menu.DebugLevel.info.build.code_debug=3
+micros2.menu.DebugLevel.debug=Debug
+micros2.menu.DebugLevel.debug.build.code_debug=4
+micros2.menu.DebugLevel.verbose=Verbose
+micros2.menu.DebugLevel.verbose.build.code_debug=5
+
+micros2.menu.EraseFlash.none=Disabled
+micros2.menu.EraseFlash.none.upload.erase_cmd=
+micros2.menu.EraseFlash.all=Enabled
+micros2.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
+
 magicbit.name=MagicBit
 
+magicbit.bootloader.tool=esptool_py
+magicbit.bootloader.tool.default=esptool_py
+
 magicbit.upload.tool=esptool_py
+magicbit.upload.tool.default=esptool_py
+magicbit.upload.tool.network=esp_ota
+
 magicbit.upload.maximum_size=1310720
 magicbit.upload.maximum_data_size=327680
-magicbit.upload.wait_for_upload_port=true
+magicbit.upload.flags=
+magicbit.upload.extra_flags=
 
 magicbit.serial.disableDTR=true
 magicbit.serial.disableRTS=true
 
+magicbit.build.tarch=xtensa
+magicbit.build.bootloader_addr=0x1000
+magicbit.build.target=esp32
 magicbit.build.mcu=esp32
 magicbit.build.core=esp32
 magicbit.build.variant=magicbit
@@ -476,17 +6595,47 @@ magicbit.menu.UploadSpeed.921600=921600
 magicbit.menu.UploadSpeed.921600.upload.speed=921600
 magicbit.menu.UploadSpeed.115200=115200
 magicbit.menu.UploadSpeed.115200.upload.speed=115200
+
+magicbit.menu.DebugLevel.none=None
+magicbit.menu.DebugLevel.none.build.code_debug=0
+magicbit.menu.DebugLevel.error=Error
+magicbit.menu.DebugLevel.error.build.code_debug=1
+magicbit.menu.DebugLevel.warn=Warn
+magicbit.menu.DebugLevel.warn.build.code_debug=2
+magicbit.menu.DebugLevel.info=Info
+magicbit.menu.DebugLevel.info.build.code_debug=3
+magicbit.menu.DebugLevel.debug=Debug
+magicbit.menu.DebugLevel.debug.build.code_debug=4
+magicbit.menu.DebugLevel.verbose=Verbose
+magicbit.menu.DebugLevel.verbose.build.code_debug=5
+
+magicbit.menu.EraseFlash.none=Disabled
+magicbit.menu.EraseFlash.none.upload.erase_cmd=
+magicbit.menu.EraseFlash.all=Enabled
+magicbit.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
+
 turta_iot_node.name=Turta IoT Node
 
+turta_iot_node.bootloader.tool=esptool_py
+turta_iot_node.bootloader.tool.default=esptool_py
+
 turta_iot_node.upload.tool=esptool_py
+turta_iot_node.upload.tool.default=esptool_py
+turta_iot_node.upload.tool.network=esp_ota
+
 turta_iot_node.upload.maximum_size=1310720
 turta_iot_node.upload.maximum_data_size=327680
-turta_iot_node.upload.wait_for_upload_port=true
+turta_iot_node.upload.flags=
+turta_iot_node.upload.extra_flags=
 
 turta_iot_node.serial.disableDTR=true
 turta_iot_node.serial.disableRTS=true
 
+turta_iot_node.build.tarch=xtensa
+turta_iot_node.build.bootloader_addr=0x1000
+turta_iot_node.build.target=esp32
 turta_iot_node.build.mcu=esp32
 turta_iot_node.build.core=esp32
 turta_iot_node.build.variant=pico32
@@ -518,74 +6667,115 @@ turta_iot_node.menu.DebugLevel.debug.build.code_debug=4
 turta_iot_node.menu.DebugLevel.verbose=Verbose
 turta_iot_node.menu.DebugLevel.verbose.build.code_debug=5
 
+turta_iot_node.menu.EraseFlash.none=Disabled
+turta_iot_node.menu.EraseFlash.none.upload.erase_cmd=
+turta_iot_node.menu.EraseFlash.all=Enabled
+turta_iot_node.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
-ttgo-lora32-v1.name=TTGO LoRa32-OLED V1
-
-ttgo-lora32-v1.upload.tool=esptool_py
-ttgo-lora32-v1.upload.maximum_size=1310720
-ttgo-lora32-v1.upload.maximum_data_size=294912
-ttgo-lora32-v1.upload.wait_for_upload_port=true
-
-ttgo-lora32-v1.serial.disableDTR=true
-ttgo-lora32-v1.serial.disableRTS=true
-
-ttgo-lora32-v1.build.mcu=esp32
-ttgo-lora32-v1.build.core=esp32
-ttgo-lora32-v1.build.variant=ttgo-lora32-v1
-ttgo-lora32-v1.build.board=TTGO_LoRa32_V1
-
-ttgo-lora32-v1.build.f_cpu=240000000L
-ttgo-lora32-v1.build.flash_mode=dio
-ttgo-lora32-v1.build.flash_size=4MB
-ttgo-lora32-v1.build.boot=dio
-ttgo-lora32-v1.build.partitions=default
-
-ttgo-lora32-v1.menu.FlashFreq.80=80MHz
-ttgo-lora32-v1.menu.FlashFreq.80.build.flash_freq=80m
-ttgo-lora32-v1.menu.FlashFreq.40=40MHz
-ttgo-lora32-v1.menu.FlashFreq.40.build.flash_freq=40m
-
-ttgo-lora32-v1.menu.UploadSpeed.921600=921600
-ttgo-lora32-v1.menu.UploadSpeed.921600.upload.speed=921600
-ttgo-lora32-v1.menu.UploadSpeed.115200=115200
-ttgo-lora32-v1.menu.UploadSpeed.115200.upload.speed=115200
-ttgo-lora32-v1.menu.UploadSpeed.256000.windows=256000
-ttgo-lora32-v1.menu.UploadSpeed.256000.upload.speed=256000
-ttgo-lora32-v1.menu.UploadSpeed.230400.windows.upload.speed=256000
-ttgo-lora32-v1.menu.UploadSpeed.230400=230400
-ttgo-lora32-v1.menu.UploadSpeed.230400.upload.speed=230400
-ttgo-lora32-v1.menu.UploadSpeed.460800.linux=460800
-ttgo-lora32-v1.menu.UploadSpeed.460800.macosx=460800
-ttgo-lora32-v1.menu.UploadSpeed.460800.upload.speed=460800
-ttgo-lora32-v1.menu.UploadSpeed.512000.windows=512000
-ttgo-lora32-v1.menu.UploadSpeed.512000.upload.speed=512000
-
-ttgo-lora32-v1.menu.DebugLevel.none=None
-ttgo-lora32-v1.menu.DebugLevel.none.build.code_debug=0
-ttgo-lora32-v1.menu.DebugLevel.error=Error
-ttgo-lora32-v1.menu.DebugLevel.error.build.code_debug=1
-ttgo-lora32-v1.menu.DebugLevel.warn=Warn
-ttgo-lora32-v1.menu.DebugLevel.warn.build.code_debug=2
-ttgo-lora32-v1.menu.DebugLevel.info=Info
-ttgo-lora32-v1.menu.DebugLevel.info.build.code_debug=3
-ttgo-lora32-v1.menu.DebugLevel.debug=Debug
-ttgo-lora32-v1.menu.DebugLevel.debug.build.code_debug=4
-ttgo-lora32-v1.menu.DebugLevel.verbose=Verbose
-ttgo-lora32-v1.menu.DebugLevel.verbose.build.code_debug=5
+ttgo-lora32.name=TTGO LoRa32-OLED
+
+ttgo-lora32.bootloader.tool=esptool_py
+ttgo-lora32.bootloader.tool.default=esptool_py
+
+ttgo-lora32.upload.tool=esptool_py
+ttgo-lora32.upload.tool.default=esptool_py
+ttgo-lora32.upload.tool.network=esp_ota
+
+ttgo-lora32.upload.maximum_size=1310720
+ttgo-lora32.upload.maximum_data_size=294912
+ttgo-lora32.upload.flags=
+ttgo-lora32.upload.extra_flags=
+
+ttgo-lora32.serial.disableDTR=true
+ttgo-lora32.serial.disableRTS=true
+
+ttgo-lora32.build.tarch=xtensa
+ttgo-lora32.build.bootloader_addr=0x1000
+ttgo-lora32.build.target=esp32
+ttgo-lora32.build.mcu=esp32
+ttgo-lora32.build.core=esp32
+ttgo-lora32.build.board=TTGO_LoRa32
+
+ttgo-lora32.menu.Revision.TTGO_LoRa32_V1=TTGO LoRa32 V1 (No TFCard)
+ttgo-lora32.menu.Revision.TTGO_LoRa32_V1.build.board=TTGO_LoRa32_V1
+ttgo-lora32.menu.Revision.TTGO_LoRa32_V1.build.variant=ttgo-lora32-v1
+
+ttgo-lora32.menu.Revision.TTGO_LoRa32_V2=TTGO LoRa32 V2
+ttgo-lora32.menu.Revision.TTGO_LoRa32_V2.build.board=TTGO_LoRa32_V2
+ttgo-lora32.menu.Revision.TTGO_LoRa32_V2.build.variant=ttgo-lora32-v2
+
+ttgo-lora32.menu.Revision.TTGO_LoRa32_v21new=TTGO LoRa32 V2.1 (1.6.1)
+ttgo-lora32.menu.Revision.TTGO_LoRa32_v21new.build.board=TTGO_LoRa32_v21new
+ttgo-lora32.menu.Revision.TTGO_LoRa32_v21new.build.variant=ttgo-lora32-v21new
+
+ttgo-lora32.build.f_cpu=240000000L
+ttgo-lora32.build.flash_mode=dio
+ttgo-lora32.build.flash_size=4MB
+ttgo-lora32.build.boot=dio
+ttgo-lora32.build.partitions=default
+
+ttgo-lora32.menu.FlashFreq.80=80MHz
+ttgo-lora32.menu.FlashFreq.80.build.flash_freq=80m
+ttgo-lora32.menu.FlashFreq.40=40MHz
+ttgo-lora32.menu.FlashFreq.40.build.flash_freq=40m
+
+ttgo-lora32.menu.UploadSpeed.921600=921600
+ttgo-lora32.menu.UploadSpeed.921600.upload.speed=921600
+ttgo-lora32.menu.UploadSpeed.115200=115200
+ttgo-lora32.menu.UploadSpeed.115200.upload.speed=115200
+ttgo-lora32.menu.UploadSpeed.256000.windows=256000
+ttgo-lora32.menu.UploadSpeed.256000.upload.speed=256000
+ttgo-lora32.menu.UploadSpeed.230400.windows.upload.speed=256000
+ttgo-lora32.menu.UploadSpeed.230400=230400
+ttgo-lora32.menu.UploadSpeed.230400.upload.speed=230400
+ttgo-lora32.menu.UploadSpeed.460800.linux=460800
+ttgo-lora32.menu.UploadSpeed.460800.macosx=460800
+ttgo-lora32.menu.UploadSpeed.460800.upload.speed=460800
+ttgo-lora32.menu.UploadSpeed.512000.windows=512000
+ttgo-lora32.menu.UploadSpeed.512000.upload.speed=512000
+
+ttgo-lora32.menu.DebugLevel.none=None
+ttgo-lora32.menu.DebugLevel.none.build.code_debug=0
+ttgo-lora32.menu.DebugLevel.error=Error
+ttgo-lora32.menu.DebugLevel.error.build.code_debug=1
+ttgo-lora32.menu.DebugLevel.warn=Warn
+ttgo-lora32.menu.DebugLevel.warn.build.code_debug=2
+ttgo-lora32.menu.DebugLevel.info=Info
+ttgo-lora32.menu.DebugLevel.info.build.code_debug=3
+ttgo-lora32.menu.DebugLevel.debug=Debug
+ttgo-lora32.menu.DebugLevel.debug.build.code_debug=4
+ttgo-lora32.menu.DebugLevel.verbose=Verbose
+ttgo-lora32.menu.DebugLevel.verbose.build.code_debug=5
+
+ttgo-lora32.menu.EraseFlash.none=Disabled
+ttgo-lora32.menu.EraseFlash.none.upload.erase_cmd=
+ttgo-lora32.menu.EraseFlash.all=Enabled
+ttgo-lora32.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
 
 ttgo-t1.name=TTGO T1
 
+ttgo-t1.bootloader.tool=esptool_py
+ttgo-t1.bootloader.tool.default=esptool_py
+
 ttgo-t1.upload.tool=esptool_py
+ttgo-t1.upload.tool.default=esptool_py
+ttgo-t1.upload.tool.network=esp_ota
+
 ttgo-t1.upload.maximum_size=1310720
 ttgo-t1.upload.maximum_data_size=327680
-ttgo-t1.upload.wait_for_upload_port=true
+ttgo-t1.upload.flags=
+ttgo-t1.upload.extra_flags=
 
 ttgo-t1.serial.disableDTR=true
 ttgo-t1.serial.disableRTS=true
 
+ttgo-t1.build.tarch=xtensa
+ttgo-t1.build.bootloader_addr=0x1000
+ttgo-t1.build.target=esp32
 ttgo-t1.build.mcu=esp32
 ttgo-t1.build.core=esp32
 ttgo-t1.build.variant=ttgo-t1
@@ -647,12 +6837,6 @@ ttgo-t1.menu.FlashMode.qio.build.boot=qio
 ttgo-t1.menu.FlashMode.dio=DIO
 ttgo-t1.menu.FlashMode.dio.build.flash_mode=dio
 ttgo-t1.menu.FlashMode.dio.build.boot=dio
-ttgo-t1.menu.FlashMode.qout=QOUT
-ttgo-t1.menu.FlashMode.qout.build.flash_mode=dout
-ttgo-t1.menu.FlashMode.qout.build.boot=qout
-ttgo-t1.menu.FlashMode.dout=DOUT
-ttgo-t1.menu.FlashMode.dout.build.flash_mode=dout
-ttgo-t1.menu.FlashMode.dout.build.boot=dout
 
 ttgo-t1.menu.FlashFreq.80=80MHz
 ttgo-t1.menu.FlashFreq.80.build.flash_freq=80m
@@ -663,10 +6847,8 @@ ttgo-t1.menu.FlashSize.4M=4MB (32Mb)
 ttgo-t1.menu.FlashSize.4M.build.flash_size=4MB
 ttgo-t1.menu.FlashSize.2M=2MB (16Mb)
 ttgo-t1.menu.FlashSize.2M.build.flash_size=2MB
-ttgo-t1.menu.FlashSize.2M.build.partitions=minimal
 ttgo-t1.menu.FlashSize.16M=16MB (128Mb)
 ttgo-t1.menu.FlashSize.16M.build.flash_size=16MB
-ttgo-t1.menu.FlashSize.16M.build.partitions=ffat
 
 ttgo-t1.menu.UploadSpeed.921600=921600
 ttgo-t1.menu.UploadSpeed.921600.upload.speed=921600
@@ -696,18 +6878,405 @@ ttgo-t1.menu.DebugLevel.debug.build.code_debug=4
 ttgo-t1.menu.DebugLevel.verbose=Verbose
 ttgo-t1.menu.DebugLevel.verbose.build.code_debug=5
 
+ttgo-t1.menu.EraseFlash.none=Disabled
+ttgo-t1.menu.EraseFlash.none.upload.erase_cmd=
+ttgo-t1.menu.EraseFlash.all=Enabled
+ttgo-t1.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+ttgo-t7-v13-mini32.name=TTGO T7 V1.3 Mini32
+
+ttgo-t7-v13-mini32.bootloader.tool=esptool_py
+ttgo-t7-v13-mini32.bootloader.tool.default=esptool_py
+
+ttgo-t7-v13-mini32.upload.tool=esptool_py
+ttgo-t7-v13-mini32.upload.tool.default=esptool_py
+ttgo-t7-v13-mini32.upload.tool.network=esp_ota
+
+ttgo-t7-v13-mini32.upload.maximum_size=1310720
+ttgo-t7-v13-mini32.upload.maximum_data_size=327680
+ttgo-t7-v13-mini32.upload.wait_for_upload_port=true
+ttgo-t7-v13-mini32.upload.flags=
+ttgo-t7-v13-mini32.upload.extra_flags=
+
+ttgo-t7-v13-mini32.serial.disableDTR=true
+ttgo-t7-v13-mini32.serial.disableRTS=true
+
+ttgo-t7-v13-mini32.build.tarch=xtensa
+ttgo-t7-v13-mini32.build.bootloader_addr=0x1000
+ttgo-t7-v13-mini32.build.target=esp32
+ttgo-t7-v13-mini32.build.mcu=esp32
+ttgo-t7-v13-mini32.build.core=esp32
+ttgo-t7-v13-mini32.build.variant=ttgo-t7-v13-mini32
+ttgo-t7-v13-mini32.build.board=TTGO_T7_V13_Mini32
+
+ttgo-t7-v13-mini32.build.f_cpu=240000000L
+ttgo-t7-v13-mini32.build.flash_size=4MB
+ttgo-t7-v13-mini32.build.flash_freq=40m
+ttgo-t7-v13-mini32.build.flash_mode=dio
+ttgo-t7-v13-mini32.build.boot=dio
+ttgo-t7-v13-mini32.build.partitions=default
+ttgo-t7-v13-mini32.build.defines=
+
+ttgo-t7-v13-mini32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+ttgo-t7-v13-mini32.menu.PartitionScheme.default.build.partitions=default
+ttgo-t7-v13-mini32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+ttgo-t7-v13-mini32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+ttgo-t7-v13-mini32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+ttgo-t7-v13-mini32.menu.PartitionScheme.minimal.build.partitions=minimal
+ttgo-t7-v13-mini32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+ttgo-t7-v13-mini32.menu.PartitionScheme.no_ota.build.partitions=no_ota
+ttgo-t7-v13-mini32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+ttgo-t7-v13-mini32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+ttgo-t7-v13-mini32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+ttgo-t7-v13-mini32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+ttgo-t7-v13-mini32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+ttgo-t7-v13-mini32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+ttgo-t7-v13-mini32.menu.PartitionScheme.huge_app.build.partitions=huge_app
+ttgo-t7-v13-mini32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+ttgo-t7-v13-mini32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+ttgo-t7-v13-mini32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+ttgo-t7-v13-mini32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+ttgo-t7-v13-mini32.menu.CPUFreq.240=240MHz (WiFi/BT)
+ttgo-t7-v13-mini32.menu.CPUFreq.240.build.f_cpu=240000000L
+ttgo-t7-v13-mini32.menu.CPUFreq.160=160MHz (WiFi/BT)
+ttgo-t7-v13-mini32.menu.CPUFreq.160.build.f_cpu=160000000L
+ttgo-t7-v13-mini32.menu.CPUFreq.80=80MHz (WiFi/BT)
+ttgo-t7-v13-mini32.menu.CPUFreq.80.build.f_cpu=80000000L
+ttgo-t7-v13-mini32.menu.CPUFreq.40=40MHz (40MHz XTAL)
+ttgo-t7-v13-mini32.menu.CPUFreq.40.build.f_cpu=40000000L
+ttgo-t7-v13-mini32.menu.CPUFreq.26=26MHz (26MHz XTAL)
+ttgo-t7-v13-mini32.menu.CPUFreq.26.build.f_cpu=26000000L
+ttgo-t7-v13-mini32.menu.CPUFreq.20=20MHz (40MHz XTAL)
+ttgo-t7-v13-mini32.menu.CPUFreq.20.build.f_cpu=20000000L
+ttgo-t7-v13-mini32.menu.CPUFreq.13=13MHz (26MHz XTAL)
+ttgo-t7-v13-mini32.menu.CPUFreq.13.build.f_cpu=13000000L
+ttgo-t7-v13-mini32.menu.CPUFreq.10=10MHz (40MHz XTAL)
+ttgo-t7-v13-mini32.menu.CPUFreq.10.build.f_cpu=10000000L
+
+ttgo-t7-v13-mini32.menu.FlashMode.qio=QIO
+ttgo-t7-v13-mini32.menu.FlashMode.qio.build.flash_mode=dio
+ttgo-t7-v13-mini32.menu.FlashMode.qio.build.boot=qio
+ttgo-t7-v13-mini32.menu.FlashMode.dio=DIO
+ttgo-t7-v13-mini32.menu.FlashMode.dio.build.flash_mode=dio
+ttgo-t7-v13-mini32.menu.FlashMode.dio.build.boot=dio
+
+ttgo-t7-v13-mini32.menu.FlashFreq.80=80MHz
+ttgo-t7-v13-mini32.menu.FlashFreq.80.build.flash_freq=80m
+ttgo-t7-v13-mini32.menu.FlashFreq.40=40MHz
+ttgo-t7-v13-mini32.menu.FlashFreq.40.build.flash_freq=40m
+
+ttgo-t7-v13-mini32.menu.FlashSize.4M=4MB (32Mb)
+ttgo-t7-v13-mini32.menu.FlashSize.4M.build.flash_size=4MB
+
+ttgo-t7-v13-mini32.menu.UploadSpeed.921600=921600
+ttgo-t7-v13-mini32.menu.UploadSpeed.921600.upload.speed=921600
+ttgo-t7-v13-mini32.menu.UploadSpeed.115200=115200
+ttgo-t7-v13-mini32.menu.UploadSpeed.115200.upload.speed=115200
+ttgo-t7-v13-mini32.menu.UploadSpeed.256000.windows=256000
+ttgo-t7-v13-mini32.menu.UploadSpeed.256000.upload.speed=256000
+ttgo-t7-v13-mini32.menu.UploadSpeed.230400.windows.upload.speed=256000
+ttgo-t7-v13-mini32.menu.UploadSpeed.230400=230400
+ttgo-t7-v13-mini32.menu.UploadSpeed.230400.upload.speed=230400
+ttgo-t7-v13-mini32.menu.UploadSpeed.460800.linux=460800
+ttgo-t7-v13-mini32.menu.UploadSpeed.460800.macosx=460800
+ttgo-t7-v13-mini32.menu.UploadSpeed.460800.upload.speed=460800
+ttgo-t7-v13-mini32.menu.UploadSpeed.512000.windows=512000
+ttgo-t7-v13-mini32.menu.UploadSpeed.512000.upload.speed=512000
+
+ttgo-t7-v13-mini32.menu.DebugLevel.none=None
+ttgo-t7-v13-mini32.menu.DebugLevel.none.build.code_debug=0
+ttgo-t7-v13-mini32.menu.DebugLevel.error=Error
+ttgo-t7-v13-mini32.menu.DebugLevel.error.build.code_debug=1
+ttgo-t7-v13-mini32.menu.DebugLevel.warn=Warn
+ttgo-t7-v13-mini32.menu.DebugLevel.warn.build.code_debug=2
+ttgo-t7-v13-mini32.menu.DebugLevel.info=Info
+ttgo-t7-v13-mini32.menu.DebugLevel.info.build.code_debug=3
+ttgo-t7-v13-mini32.menu.DebugLevel.debug=Debug
+ttgo-t7-v13-mini32.menu.DebugLevel.debug.build.code_debug=4
+ttgo-t7-v13-mini32.menu.DebugLevel.verbose=Verbose
+ttgo-t7-v13-mini32.menu.DebugLevel.verbose.build.code_debug=5
+
+ttgo-t7-v13-mini32.menu.EraseFlash.none=Disabled
+ttgo-t7-v13-mini32.menu.EraseFlash.none.upload.erase_cmd=
+ttgo-t7-v13-mini32.menu.EraseFlash.all=Enabled
+ttgo-t7-v13-mini32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+ttgo-t7-v14-mini32.name=TTGO T7 V1.4 Mini32
+
+ttgo-t7-v14-mini32.bootloader.tool=esptool_py
+ttgo-t7-v14-mini32.bootloader.tool.default=esptool_py
+
+ttgo-t7-v14-mini32.upload.tool=esptool_py
+ttgo-t7-v14-mini32.upload.tool.default=esptool_py
+ttgo-t7-v14-mini32.upload.tool.network=esp_ota
+
+ttgo-t7-v14-mini32.upload.maximum_size=1310720
+ttgo-t7-v14-mini32.upload.maximum_data_size=327680
+ttgo-t7-v14-mini32.upload.wait_for_upload_port=true
+ttgo-t7-v14-mini32.upload.flags=
+ttgo-t7-v14-mini32.upload.extra_flags=
+
+ttgo-t7-v14-mini32.serial.disableDTR=true
+ttgo-t7-v14-mini32.serial.disableRTS=true
+
+ttgo-t7-v14-mini32.build.tarch=xtensa
+ttgo-t7-v14-mini32.build.bootloader_addr=0x1000
+ttgo-t7-v14-mini32.build.target=esp32
+ttgo-t7-v14-mini32.build.mcu=esp32
+ttgo-t7-v14-mini32.build.core=esp32
+ttgo-t7-v14-mini32.build.variant=ttgo-t7-v14-mini32
+ttgo-t7-v14-mini32.build.board=TTGO_T7_V14_Mini32
+
+ttgo-t7-v14-mini32.build.f_cpu=240000000L
+ttgo-t7-v14-mini32.build.flash_size=4MB
+ttgo-t7-v14-mini32.build.flash_freq=40m
+ttgo-t7-v14-mini32.build.flash_mode=dio
+ttgo-t7-v14-mini32.build.boot=dio
+ttgo-t7-v14-mini32.build.partitions=default
+ttgo-t7-v14-mini32.build.defines=
+
+ttgo-t7-v14-mini32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+ttgo-t7-v14-mini32.menu.PartitionScheme.default.build.partitions=default
+ttgo-t7-v14-mini32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+ttgo-t7-v14-mini32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+ttgo-t7-v14-mini32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+ttgo-t7-v14-mini32.menu.PartitionScheme.minimal.build.partitions=minimal
+ttgo-t7-v14-mini32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+ttgo-t7-v14-mini32.menu.PartitionScheme.no_ota.build.partitions=no_ota
+ttgo-t7-v14-mini32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+ttgo-t7-v14-mini32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+ttgo-t7-v14-mini32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+ttgo-t7-v14-mini32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+ttgo-t7-v14-mini32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+ttgo-t7-v14-mini32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+ttgo-t7-v14-mini32.menu.PartitionScheme.huge_app.build.partitions=huge_app
+ttgo-t7-v14-mini32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+ttgo-t7-v14-mini32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+ttgo-t7-v14-mini32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+ttgo-t7-v14-mini32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+ttgo-t7-v14-mini32.menu.CPUFreq.240=240MHz (WiFi/BT)
+ttgo-t7-v14-mini32.menu.CPUFreq.240.build.f_cpu=240000000L
+ttgo-t7-v14-mini32.menu.CPUFreq.160=160MHz (WiFi/BT)
+ttgo-t7-v14-mini32.menu.CPUFreq.160.build.f_cpu=160000000L
+ttgo-t7-v14-mini32.menu.CPUFreq.80=80MHz (WiFi/BT)
+ttgo-t7-v14-mini32.menu.CPUFreq.80.build.f_cpu=80000000L
+ttgo-t7-v14-mini32.menu.CPUFreq.40=40MHz (40MHz XTAL)
+ttgo-t7-v14-mini32.menu.CPUFreq.40.build.f_cpu=40000000L
+ttgo-t7-v14-mini32.menu.CPUFreq.26=26MHz (26MHz XTAL)
+ttgo-t7-v14-mini32.menu.CPUFreq.26.build.f_cpu=26000000L
+ttgo-t7-v14-mini32.menu.CPUFreq.20=20MHz (40MHz XTAL)
+ttgo-t7-v14-mini32.menu.CPUFreq.20.build.f_cpu=20000000L
+ttgo-t7-v14-mini32.menu.CPUFreq.13=13MHz (26MHz XTAL)
+ttgo-t7-v14-mini32.menu.CPUFreq.13.build.f_cpu=13000000L
+ttgo-t7-v14-mini32.menu.CPUFreq.10=10MHz (40MHz XTAL)
+ttgo-t7-v14-mini32.menu.CPUFreq.10.build.f_cpu=10000000L
+
+ttgo-t7-v14-mini32.menu.FlashMode.qio=QIO
+ttgo-t7-v14-mini32.menu.FlashMode.qio.build.flash_mode=dio
+ttgo-t7-v14-mini32.menu.FlashMode.qio.build.boot=qio
+ttgo-t7-v14-mini32.menu.FlashMode.dio=DIO
+ttgo-t7-v14-mini32.menu.FlashMode.dio.build.flash_mode=dio
+ttgo-t7-v14-mini32.menu.FlashMode.dio.build.boot=dio
+
+ttgo-t7-v14-mini32.menu.FlashFreq.80=80MHz
+ttgo-t7-v14-mini32.menu.FlashFreq.80.build.flash_freq=80m
+ttgo-t7-v14-mini32.menu.FlashFreq.40=40MHz
+ttgo-t7-v14-mini32.menu.FlashFreq.40.build.flash_freq=40m
+
+ttgo-t7-v14-mini32.menu.FlashSize.4M=4MB (32Mb)
+ttgo-t7-v14-mini32.menu.FlashSize.4M.build.flash_size=4MB
+
+ttgo-t7-v14-mini32.menu.UploadSpeed.921600=921600
+ttgo-t7-v14-mini32.menu.UploadSpeed.921600.upload.speed=921600
+ttgo-t7-v14-mini32.menu.UploadSpeed.115200=115200
+ttgo-t7-v14-mini32.menu.UploadSpeed.115200.upload.speed=115200
+ttgo-t7-v14-mini32.menu.UploadSpeed.256000.windows=256000
+ttgo-t7-v14-mini32.menu.UploadSpeed.256000.upload.speed=256000
+ttgo-t7-v14-mini32.menu.UploadSpeed.230400.windows.upload.speed=256000
+ttgo-t7-v14-mini32.menu.UploadSpeed.230400=230400
+ttgo-t7-v14-mini32.menu.UploadSpeed.230400.upload.speed=230400
+ttgo-t7-v14-mini32.menu.UploadSpeed.460800.linux=460800
+ttgo-t7-v14-mini32.menu.UploadSpeed.460800.macosx=460800
+ttgo-t7-v14-mini32.menu.UploadSpeed.460800.upload.speed=460800
+ttgo-t7-v14-mini32.menu.UploadSpeed.512000.windows=512000
+ttgo-t7-v14-mini32.menu.UploadSpeed.512000.upload.speed=512000
+
+ttgo-t7-v14-mini32.menu.DebugLevel.none=None
+ttgo-t7-v14-mini32.menu.DebugLevel.none.build.code_debug=0
+ttgo-t7-v14-mini32.menu.DebugLevel.error=Error
+ttgo-t7-v14-mini32.menu.DebugLevel.error.build.code_debug=1
+ttgo-t7-v14-mini32.menu.DebugLevel.warn=Warn
+ttgo-t7-v14-mini32.menu.DebugLevel.warn.build.code_debug=2
+ttgo-t7-v14-mini32.menu.DebugLevel.info=Info
+ttgo-t7-v14-mini32.menu.DebugLevel.info.build.code_debug=3
+ttgo-t7-v14-mini32.menu.DebugLevel.debug=Debug
+ttgo-t7-v14-mini32.menu.DebugLevel.debug.build.code_debug=4
+ttgo-t7-v14-mini32.menu.DebugLevel.verbose=Verbose
+ttgo-t7-v14-mini32.menu.DebugLevel.verbose.build.code_debug=5
+
+ttgo-t7-v14-mini32.menu.EraseFlash.none=Disabled
+ttgo-t7-v14-mini32.menu.EraseFlash.none.upload.erase_cmd=
+ttgo-t7-v14-mini32.menu.EraseFlash.all=Enabled
+ttgo-t7-v14-mini32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+ttgo-t-oi-plus.name=TTGO T-OI PLUS RISC-V ESP32-C3
+
+ttgo-t-oi-plus.bootloader.tool=esptool_py
+ttgo-t-oi-plus.bootloader.tool.default=esptool_py
+
+ttgo-t-oi-plus.upload.tool=esptool_py
+ttgo-t-oi-plus.upload.tool.default=esptool_py
+ttgo-t-oi-plus.upload.tool.network=esp_ota
+
+ttgo-t-oi-plus.upload.maximum_size=1310720
+ttgo-t-oi-plus.upload.maximum_data_size=327680
+ttgo-t-oi-plus.upload.flags=
+ttgo-t-oi-plus.upload.extra_flags=
+
+ttgo-t-oi-plus.serial.disableDTR=false
+ttgo-t-oi-plus.serial.disableRTS=false
+
+ttgo-t-oi-plus.build.tarch=riscv32
+ttgo-t-oi-plus.build.target=esp
+ttgo-t-oi-plus.build.mcu=esp32c3
+ttgo-t-oi-plus.build.core=esp32
+ttgo-t-oi-plus.build.variant=ttgo-t-oi-plus
+ttgo-t-oi-plus.build.board=TTGO-T-OI-PLUS_DEV
+ttgo-t-oi-plus.build.bootloader_addr=0x0
+
+ttgo-t-oi-plus.build.cdc_on_boot=0
+ttgo-t-oi-plus.build.f_cpu=160000000L
+ttgo-t-oi-plus.build.flash_size=4MB
+ttgo-t-oi-plus.build.flash_freq=80m
+ttgo-t-oi-plus.build.flash_mode=qio
+ttgo-t-oi-plus.build.boot=qio
+ttgo-t-oi-plus.build.partitions=default
+ttgo-t-oi-plus.build.defines=
+
+ttgo-t-oi-plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+ttgo-t-oi-plus.menu.PartitionScheme.default.build.partitions=default
+ttgo-t-oi-plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+ttgo-t-oi-plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+ttgo-t-oi-plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+ttgo-t-oi-plus.menu.PartitionScheme.minimal.build.partitions=minimal
+ttgo-t-oi-plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+ttgo-t-oi-plus.menu.PartitionScheme.no_ota.build.partitions=no_ota
+ttgo-t-oi-plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+ttgo-t-oi-plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+ttgo-t-oi-plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+ttgo-t-oi-plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+ttgo-t-oi-plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+ttgo-t-oi-plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+ttgo-t-oi-plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+ttgo-t-oi-plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+ttgo-t-oi-plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+ttgo-t-oi-plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+ttgo-t-oi-plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+ttgo-t-oi-plus.menu.PartitionScheme.huge_app.build.partitions=huge_app
+ttgo-t-oi-plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+ttgo-t-oi-plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+ttgo-t-oi-plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+ttgo-t-oi-plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+ttgo-t-oi-plus.menu.CPUFreq.160=160MHz (WiFi)
+ttgo-t-oi-plus.menu.CPUFreq.160.build.f_cpu=160000000L
+ttgo-t-oi-plus.menu.CPUFreq.80=80MHz (WiFi)
+ttgo-t-oi-plus.menu.CPUFreq.80.build.f_cpu=80000000L
+ttgo-t-oi-plus.menu.CPUFreq.40=40MHz
+ttgo-t-oi-plus.menu.CPUFreq.40.build.f_cpu=40000000L
+ttgo-t-oi-plus.menu.CPUFreq.20=20MHz
+ttgo-t-oi-plus.menu.CPUFreq.20.build.f_cpu=20000000L
+ttgo-t-oi-plus.menu.CPUFreq.10=10MHz
+ttgo-t-oi-plus.menu.CPUFreq.10.build.f_cpu=10000000L
+
+ttgo-t-oi-plus.menu.FlashMode.qio=QIO
+ttgo-t-oi-plus.menu.FlashMode.qio.build.flash_mode=dio
+ttgo-t-oi-plus.menu.FlashMode.qio.build.boot=qio
+ttgo-t-oi-plus.menu.FlashMode.dio=DIO
+ttgo-t-oi-plus.menu.FlashMode.dio.build.flash_mode=dio
+ttgo-t-oi-plus.menu.FlashMode.dio.build.boot=dio
+
+ttgo-t-oi-plus.menu.FlashFreq.80=80MHz
+ttgo-t-oi-plus.menu.FlashFreq.80.build.flash_freq=80m
+ttgo-t-oi-plus.menu.FlashFreq.40=40MHz
+ttgo-t-oi-plus.menu.FlashFreq.40.build.flash_freq=40m
+
+ttgo-t-oi-plus.menu.FlashSize.4M=4MB (32Mb)
+ttgo-t-oi-plus.menu.FlashSize.4M.build.flash_size=4MB
+
+ttgo-t-oi-plus.menu.UploadSpeed.921600=921600
+ttgo-t-oi-plus.menu.UploadSpeed.921600.upload.speed=921600
+ttgo-t-oi-plus.menu.UploadSpeed.115200=115200
+ttgo-t-oi-plus.menu.UploadSpeed.115200.upload.speed=115200
+ttgo-t-oi-plus.menu.UploadSpeed.256000.windows=256000
+ttgo-t-oi-plus.menu.UploadSpeed.256000.upload.speed=256000
+ttgo-t-oi-plus.menu.UploadSpeed.230400.windows.upload.speed=256000
+ttgo-t-oi-plus.menu.UploadSpeed.230400=230400
+ttgo-t-oi-plus.menu.UploadSpeed.230400.upload.speed=230400
+ttgo-t-oi-plus.menu.UploadSpeed.460800.linux=460800
+ttgo-t-oi-plus.menu.UploadSpeed.460800.macosx=460800
+ttgo-t-oi-plus.menu.UploadSpeed.460800.upload.speed=460800
+ttgo-t-oi-plus.menu.UploadSpeed.512000.windows=512000
+ttgo-t-oi-plus.menu.UploadSpeed.512000.upload.speed=512000
+
+ttgo-t-oi-plus.menu.DebugLevel.none=None
+ttgo-t-oi-plus.menu.DebugLevel.none.build.code_debug=0
+ttgo-t-oi-plus.menu.DebugLevel.error=Error
+ttgo-t-oi-plus.menu.DebugLevel.error.build.code_debug=1
+ttgo-t-oi-plus.menu.DebugLevel.warn=Warn
+ttgo-t-oi-plus.menu.DebugLevel.warn.build.code_debug=2
+ttgo-t-oi-plus.menu.DebugLevel.info=Info
+ttgo-t-oi-plus.menu.DebugLevel.info.build.code_debug=3
+ttgo-t-oi-plus.menu.DebugLevel.debug=Debug
+ttgo-t-oi-plus.menu.DebugLevel.debug.build.code_debug=4
+ttgo-t-oi-plus.menu.DebugLevel.verbose=Verbose
+ttgo-t-oi-plus.menu.DebugLevel.verbose.build.code_debug=5
+
+ttgo-t-oi-plus.menu.EraseFlash.none=Disabled
+ttgo-t-oi-plus.menu.EraseFlash.none.upload.erase_cmd=
+ttgo-t-oi-plus.menu.EraseFlash.all=Enabled
+ttgo-t-oi-plus.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 cw02.name=XinaBox CW02
 
+cw02.bootloader.tool=esptool_py
+cw02.bootloader.tool.default=esptool_py
+
 cw02.upload.tool=esptool_py
+cw02.upload.tool.default=esptool_py
+cw02.upload.tool.network=esp_ota
+
 cw02.upload.maximum_size=1310720
 cw02.upload.maximum_data_size=294912
-cw02.upload.wait_for_upload_port=true
+cw02.upload.flags=
+cw02.upload.extra_flags=
 
 cw02.serial.disableDTR=true
 cw02.serial.disableRTS=true
 
+cw02.build.tarch=xtensa
+cw02.build.bootloader_addr=0x1000
+cw02.build.target=esp32
 cw02.build.mcu=esp32
 cw02.build.core=esp32
 cw02.build.variant=xinabox
@@ -726,12 +7295,6 @@ cw02.menu.FlashMode.qio.build.boot=qio
 cw02.menu.FlashMode.dio=DIO
 cw02.menu.FlashMode.dio.build.flash_mode=dio
 cw02.menu.FlashMode.dio.build.boot=dio
-cw02.menu.FlashMode.qout=QOUT
-cw02.menu.FlashMode.qout.build.flash_mode=dout
-cw02.menu.FlashMode.qout.build.boot=qout
-cw02.menu.FlashMode.dout=DOUT
-cw02.menu.FlashMode.dout.build.flash_mode=dout
-cw02.menu.FlashMode.dout.build.boot=dout
 
 cw02.menu.FlashFreq.80=80MHz
 cw02.menu.FlashFreq.80.build.flash_freq=80m
@@ -742,7 +7305,6 @@ cw02.menu.FlashSize.4M=4MB (32Mb)
 cw02.menu.FlashSize.4M.build.flash_size=4MB
 cw02.menu.FlashSize.2M=2MB (16Mb)
 cw02.menu.FlashSize.2M.build.flash_size=2MB
-cw02.menu.FlashSize.2M.build.partitions=minimal
 
 cw02.menu.UploadSpeed.921600=921600
 cw02.menu.UploadSpeed.921600.upload.speed=921600
@@ -772,18 +7334,33 @@ cw02.menu.DebugLevel.debug.build.code_debug=4
 cw02.menu.DebugLevel.verbose=Verbose
 cw02.menu.DebugLevel.verbose.build.code_debug=5
 
+cw02.menu.EraseFlash.none=Disabled
+cw02.menu.EraseFlash.none.upload.erase_cmd=
+cw02.menu.EraseFlash.all=Enabled
+cw02.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 esp32thing.name=SparkFun ESP32 Thing
 
+esp32thing.bootloader.tool=esptool_py
+esp32thing.bootloader.tool.default=esptool_py
+
 esp32thing.upload.tool=esptool_py
+esp32thing.upload.tool.default=esptool_py
+esp32thing.upload.tool.network=esp_ota
+
 esp32thing.upload.maximum_size=1310720
 esp32thing.upload.maximum_data_size=327680
-esp32thing.upload.wait_for_upload_port=true
+esp32thing.upload.flags=
+esp32thing.upload.extra_flags=
 
 esp32thing.serial.disableDTR=true
 esp32thing.serial.disableRTS=true
 
+esp32thing.build.tarch=xtensa
+esp32thing.build.bootloader_addr=0x1000
+esp32thing.build.target=esp32
 esp32thing.build.mcu=esp32
 esp32thing.build.core=esp32
 esp32thing.build.variant=esp32thing
@@ -838,18 +7415,34 @@ esp32thing.menu.DebugLevel.debug.build.code_debug=4
 esp32thing.menu.DebugLevel.verbose=Verbose
 esp32thing.menu.DebugLevel.verbose.build.code_debug=5
 
+esp32thing.menu.EraseFlash.none=Disabled
+esp32thing.menu.EraseFlash.none.upload.erase_cmd=
+esp32thing.menu.EraseFlash.all=Enabled
+esp32thing.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 esp32thing_plus.name=SparkFun ESP32 Thing Plus
 
+esp32thing_plus.bootloader.tool=esptool_py
+esp32thing_plus.bootloader.tool.default=esptool_py
+
 esp32thing_plus.upload.tool=esptool_py
+esp32thing_plus.upload.tool.default=esptool_py
+esp32thing_plus.upload.tool.network=esp_ota
+
 esp32thing_plus.upload.maximum_size=1310720
 esp32thing_plus.upload.maximum_data_size=327680
 esp32thing_plus.upload.wait_for_upload_port=true
+esp32thing_plus.upload.flags=
+esp32thing_plus.upload.extra_flags=
 
 esp32thing_plus.serial.disableDTR=true
 esp32thing_plus.serial.disableRTS=true
 
+esp32thing_plus.build.tarch=xtensa
+esp32thing_plus.build.bootloader_addr=0x1000
+esp32thing_plus.build.target=esp32
 esp32thing_plus.build.mcu=esp32
 esp32thing_plus.build.core=esp32
 esp32thing_plus.build.variant=esp32thing_plus
@@ -902,103 +7495,1846 @@ esp32thing_plus.menu.DebugLevel.debug.build.code_debug=4
 esp32thing_plus.menu.DebugLevel.verbose=Verbose
 esp32thing_plus.menu.DebugLevel.verbose.build.code_debug=5
 
+esp32thing_plus.menu.EraseFlash.none=Disabled
+esp32thing_plus.menu.EraseFlash.none.upload.erase_cmd=
+esp32thing_plus.menu.EraseFlash.all=Enabled
+esp32thing_plus.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
 
-nina_w10.name=u-blox NINA-W10 series (ESP32)
-
-nina_w10.upload.tool=esptool_py
-nina_w10.upload.maximum_size=1310720
-nina_w10.upload.maximum_data_size=327680
-nina_w10.upload.wait_for_upload_port=true
-
-nina_w10.serial.disableDTR=true
-nina_w10.serial.disableRTS=true
+esp32thing_plus_c.name=SparkFun ESP32 Thing Plus C
+
+esp32thing_plus_c.bootloader.tool=esptool_py
+esp32thing_plus_c.bootloader.tool.default=esptool_py
+
+esp32thing_plus_c.upload.tool=esptool_py
+esp32thing_plus_c.upload.tool.default=esptool_py
+esp32thing_plus_c.upload.tool.network=esp_ota
+
+esp32thing_plus_c.upload.maximum_size=1310720
+esp32thing_plus_c.upload.maximum_data_size=327680
+esp32thing_plus_c.upload.wait_for_upload_port=true
+esp32thing_plus_c.upload.flags=
+esp32thing_plus_c.upload.extra_flags=
+
+esp32thing_plus_c.serial.disableDTR=true
+esp32thing_plus_c.serial.disableRTS=true
+
+esp32thing_plus_c.build.tarch=xtensa
+esp32thing_plus_c.build.bootloader_addr=0x1000
+esp32thing_plus_c.build.target=esp32
+esp32thing_plus_c.build.mcu=esp32
+esp32thing_plus_c.build.core=esp32
+esp32thing_plus_c.build.variant=esp32thing_plus_c
+esp32thing_plus_c.build.board=ESP32_THING_PLUS_C
+
+esp32thing_plus_c.build.f_cpu=240000000L
+esp32thing_plus_c.build.flash_mode=dio
+esp32thing_plus_c.build.flash_size=16MB
+esp32thing_plus_c.build.boot=dio
+esp32thing_plus_c.build.partitions=default
+esp32thing_plus_c.build.defines=
+
+esp32thing_plus_c.menu.FlashFreq.80=80MHz
+esp32thing_plus_c.menu.FlashFreq.80.build.flash_freq=80m
+esp32thing_plus_c.menu.FlashFreq.40=40MHz
+esp32thing_plus_c.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32thing_plus_c.menu.PartitionScheme.default=Default (6.25MB APP/OTA/3.43MB SPIFFS)
+esp32thing_plus_c.menu.PartitionScheme.default.build.partitions=default_16MB
+esp32thing_plus_c.menu.PartitionScheme.default.upload.maximum_size=6553600
+esp32thing_plus_c.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/OTA/6.93MB SPIFFS)
+esp32thing_plus_c.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
+esp32thing_plus_c.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592
+
+esp32thing_plus_c.menu.UploadSpeed.921600=921600
+esp32thing_plus_c.menu.UploadSpeed.921600.upload.speed=921600
+esp32thing_plus_c.menu.UploadSpeed.115200=115200
+esp32thing_plus_c.menu.UploadSpeed.115200.upload.speed=115200
+esp32thing_plus_c.menu.UploadSpeed.256000.windows=256000
+esp32thing_plus_c.menu.UploadSpeed.256000.upload.speed=256000
+esp32thing_plus_c.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32thing_plus_c.menu.UploadSpeed.230400=230400
+esp32thing_plus_c.menu.UploadSpeed.230400.upload.speed=230400
+esp32thing_plus_c.menu.UploadSpeed.460800.linux=460800
+esp32thing_plus_c.menu.UploadSpeed.460800.macosx=460800
+esp32thing_plus_c.menu.UploadSpeed.460800.upload.speed=460800
+esp32thing_plus_c.menu.UploadSpeed.512000.windows=512000
+esp32thing_plus_c.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32thing_plus_c.menu.DebugLevel.none=None
+esp32thing_plus_c.menu.DebugLevel.none.build.code_debug=0
+esp32thing_plus_c.menu.DebugLevel.error=Error
+esp32thing_plus_c.menu.DebugLevel.error.build.code_debug=1
+esp32thing_plus_c.menu.DebugLevel.warn=Warn
+esp32thing_plus_c.menu.DebugLevel.warn.build.code_debug=2
+esp32thing_plus_c.menu.DebugLevel.info=Info
+esp32thing_plus_c.menu.DebugLevel.info.build.code_debug=3
+esp32thing_plus_c.menu.DebugLevel.debug=Debug
+esp32thing_plus_c.menu.DebugLevel.debug.build.code_debug=4
+esp32thing_plus_c.menu.DebugLevel.verbose=Verbose
+esp32thing_plus_c.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32thing_plus_c.menu.EraseFlash.none=Disabled
+esp32thing_plus_c.menu.EraseFlash.none.upload.erase_cmd=
+esp32thing_plus_c.menu.EraseFlash.all=Enabled
+esp32thing_plus_c.menu.EraseFlash.all.upload.erase_cmd=-e
 
-nina_w10.build.mcu=esp32
-nina_w10.build.core=esp32
-nina_w10.build.variant=nina_w10
-nina_w10.build.board=UBLOX_NINA_W10
-nina_w10.build.f_cpu=240000000L
-nina_w10.build.boot=dio
-nina_w10.build.partitions=minimal
-nina_w10.build.flash_mode=dio
-nina_w10.build.flash_size=2MB
-nina_w10.build.flash_freq=40m
-nina_w10.build.defines=
+##############################################################
 
-nina_w10.menu.UploadSpeed.921600=921600
-nina_w10.menu.UploadSpeed.921600.upload.speed=921600
-nina_w10.menu.UploadSpeed.115200=115200
-nina_w10.menu.UploadSpeed.115200.upload.speed=115200
-nina_w10.menu.UploadSpeed.256000.windows=256000
-nina_w10.menu.UploadSpeed.256000.upload.speed=256000
-nina_w10.menu.UploadSpeed.230400.windows.upload.speed=256000
-nina_w10.menu.UploadSpeed.230400=230400
-nina_w10.menu.UploadSpeed.230400.upload.speed=230400
-nina_w10.menu.UploadSpeed.460800.linux=460800
-nina_w10.menu.UploadSpeed.460800.macosx=460800
-nina_w10.menu.UploadSpeed.460800.upload.speed=460800
-nina_w10.menu.UploadSpeed.512000.windows=512000
-nina_w10.menu.UploadSpeed.512000.upload.speed=512000
+sparkfun_esp32s2_thing_plus.name=SparkFun ESP32-S2 Thing Plus
+sparkfun_esp32s2_thing_plus.vid.0=0x1B4F
+sparkfun_esp32s2_thing_plus.pid.0=0x0027
+
+sparkfun_esp32s2_thing_plus.bootloader.tool=esptool_py
+sparkfun_esp32s2_thing_plus.bootloader.tool.default=esptool_py
+
+sparkfun_esp32s2_thing_plus.upload.tool=esptool_py
+sparkfun_esp32s2_thing_plus.upload.tool.default=esptool_py
+sparkfun_esp32s2_thing_plus.upload.tool.network=esp_ota
+
+sparkfun_esp32s2_thing_plus.upload.maximum_size=1310720
+sparkfun_esp32s2_thing_plus.upload.maximum_data_size=327680
+sparkfun_esp32s2_thing_plus.upload.flags=
+sparkfun_esp32s2_thing_plus.upload.extra_flags=
+sparkfun_esp32s2_thing_plus.upload.use_1200bps_touch=true
+sparkfun_esp32s2_thing_plus.upload.wait_for_upload_port=true
+
+sparkfun_esp32s2_thing_plus.serial.disableDTR=false
+sparkfun_esp32s2_thing_plus.serial.disableRTS=false
+
+sparkfun_esp32s2_thing_plus.build.tarch=xtensa
+sparkfun_esp32s2_thing_plus.build.bootloader_addr=0x1000
+sparkfun_esp32s2_thing_plus.build.target=esp32s2
+sparkfun_esp32s2_thing_plus.build.mcu=esp32s2
+sparkfun_esp32s2_thing_plus.build.core=esp32
+sparkfun_esp32s2_thing_plus.build.variant=esp32s2thing_plus
+sparkfun_esp32s2_thing_plus.build.board=ESP32S2_THING_PLUS
+
+sparkfun_esp32s2_thing_plus.build.cdc_on_boot=0
+sparkfun_esp32s2_thing_plus.build.msc_on_boot=0
+sparkfun_esp32s2_thing_plus.build.dfu_on_boot=0
+sparkfun_esp32s2_thing_plus.build.f_cpu=240000000L
+sparkfun_esp32s2_thing_plus.build.flash_size=4MB
+sparkfun_esp32s2_thing_plus.build.flash_freq=80m
+sparkfun_esp32s2_thing_plus.build.flash_mode=qio
+sparkfun_esp32s2_thing_plus.build.boot=qio
+sparkfun_esp32s2_thing_plus.build.partitions=default
+sparkfun_esp32s2_thing_plus.build.defines=
+
+sparkfun_esp32s2_thing_plus.menu.CDCOnBoot.default=Disabled
+sparkfun_esp32s2_thing_plus.menu.CDCOnBoot.default.build.cdc_on_boot=0
+sparkfun_esp32s2_thing_plus.menu.CDCOnBoot.cdc=Enabled
+sparkfun_esp32s2_thing_plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+sparkfun_esp32s2_thing_plus.menu.MSCOnBoot.default=Disabled
+sparkfun_esp32s2_thing_plus.menu.MSCOnBoot.default.build.msc_on_boot=0
+sparkfun_esp32s2_thing_plus.menu.MSCOnBoot.msc=Enabled
+sparkfun_esp32s2_thing_plus.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+sparkfun_esp32s2_thing_plus.menu.DFUOnBoot.default=Disabled
+sparkfun_esp32s2_thing_plus.menu.DFUOnBoot.default.build.dfu_on_boot=0
+sparkfun_esp32s2_thing_plus.menu.DFUOnBoot.dfu=Enabled
+sparkfun_esp32s2_thing_plus.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+sparkfun_esp32s2_thing_plus.menu.PSRAM.disabled=Disabled
+sparkfun_esp32s2_thing_plus.menu.PSRAM.disabled.build.defines=
+sparkfun_esp32s2_thing_plus.menu.PSRAM.enabled=Enabled
+sparkfun_esp32s2_thing_plus.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default.build.partitions=default
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.minimal.build.partitions=minimal
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.huge_app.build.partitions=huge_app
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.fatflash.build.partitions=ffat
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+sparkfun_esp32s2_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.240=240MHz (WiFi)
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.240.build.f_cpu=240000000L
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.160=160MHz (WiFi)
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.160.build.f_cpu=160000000L
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.80=80MHz (WiFi)
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.80.build.f_cpu=80000000L
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.40=40MHz
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.40.build.f_cpu=40000000L
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.20=20MHz
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.20.build.f_cpu=20000000L
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.10=10MHz
+sparkfun_esp32s2_thing_plus.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sparkfun_esp32s2_thing_plus.menu.FlashMode.qio=QIO
+sparkfun_esp32s2_thing_plus.menu.FlashMode.qio.build.flash_mode=dio
+sparkfun_esp32s2_thing_plus.menu.FlashMode.qio.build.boot=qio
+sparkfun_esp32s2_thing_plus.menu.FlashMode.dio=DIO
+sparkfun_esp32s2_thing_plus.menu.FlashMode.dio.build.flash_mode=dio
+sparkfun_esp32s2_thing_plus.menu.FlashMode.dio.build.boot=dio
+
+sparkfun_esp32s2_thing_plus.menu.FlashFreq.80=80MHz
+sparkfun_esp32s2_thing_plus.menu.FlashFreq.80.build.flash_freq=80m
+sparkfun_esp32s2_thing_plus.menu.FlashFreq.40=40MHz
+sparkfun_esp32s2_thing_plus.menu.FlashFreq.40.build.flash_freq=40m
+
+sparkfun_esp32s2_thing_plus.menu.FlashSize.4M=4MB (32Mb)
+sparkfun_esp32s2_thing_plus.menu.FlashSize.4M.build.flash_size=4MB
+sparkfun_esp32s2_thing_plus.menu.FlashSize.8M=8MB (64Mb)
+sparkfun_esp32s2_thing_plus.menu.FlashSize.8M.build.flash_size=8MB
+sparkfun_esp32s2_thing_plus.menu.FlashSize.2M=2MB (16Mb)
+sparkfun_esp32s2_thing_plus.menu.FlashSize.2M.build.flash_size=2MB
+sparkfun_esp32s2_thing_plus.menu.FlashSize.16M=16MB (128Mb)
+sparkfun_esp32s2_thing_plus.menu.FlashSize.16M.build.flash_size=16MB
+
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.921600=921600
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.921600.upload.speed=921600
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.115200=115200
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.115200.upload.speed=115200
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.256000.windows=256000
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.256000.upload.speed=256000
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.230400.windows.upload.speed=256000
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.230400=230400
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.230400.upload.speed=230400
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.460800.linux=460800
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.460800.macosx=460800
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.460800.upload.speed=460800
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.512000.windows=512000
+sparkfun_esp32s2_thing_plus.menu.UploadSpeed.512000.upload.speed=512000
+
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.none=None
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.none.build.code_debug=0
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.error=Error
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.error.build.code_debug=1
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.warn=Warn
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.warn.build.code_debug=2
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.info=Info
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.info.build.code_debug=3
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.debug=Debug
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.debug.build.code_debug=4
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.verbose=Verbose
+sparkfun_esp32s2_thing_plus.menu.DebugLevel.verbose.build.code_debug=5
+
+sparkfun_esp32s2_thing_plus.menu.EraseFlash.none=Disabled
+sparkfun_esp32s2_thing_plus.menu.EraseFlash.none.upload.erase_cmd=
+sparkfun_esp32s2_thing_plus.menu.EraseFlash.all=Enabled
+sparkfun_esp32s2_thing_plus.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
+# Sparkfun ESP32S3 Thing Plus
+
+sparkfun_esp32s3_thing_plus.name=SparkFun ESP32-S3 Thing Plus
+sparkfun_esp32s3_thing_plus.bootloader.tool=esptool_py
+sparkfun_esp32s3_thing_plus.bootloader.tool.default=esptool_py
+
+sparkfun_esp32s3_thing_plus.upload.tool=esptool_py
+sparkfun_esp32s3_thing_plus.upload.tool.default=esptool_py
+sparkfun_esp32s3_thing_plus.upload.tool.network=esp_ota
+
+sparkfun_esp32s3_thing_plus.upload.maximum_size=1310720
+sparkfun_esp32s3_thing_plus.upload.maximum_data_size=327680
+sparkfun_esp32s3_thing_plus.upload.flags=
+sparkfun_esp32s3_thing_plus.upload.extra_flags=
+sparkfun_esp32s3_thing_plus.upload.use_1200bps_touch=false
+sparkfun_esp32s3_thing_plus.upload.wait_for_upload_port=false
+
+sparkfun_esp32s3_thing_plus.serial.disableDTR=false
+sparkfun_esp32s3_thing_plus.serial.disableRTS=false
+
+sparkfun_esp32s3_thing_plus.build.tarch=xtensa
+sparkfun_esp32s3_thing_plus.build.bootloader_addr=0x0
+sparkfun_esp32s3_thing_plus.build.target=esp32s3
+sparkfun_esp32s3_thing_plus.build.mcu=esp32s3
+sparkfun_esp32s3_thing_plus.build.core=esp32
+sparkfun_esp32s3_thing_plus.build.variant=sparkfun_esp32s3_thing_plus
+sparkfun_esp32s3_thing_plus.build.board=SPARKFUN_ESP32S3_THING_PLUS
+
+sparkfun_esp32s3_thing_plus.build.usb_mode=1
+sparkfun_esp32s3_thing_plus.build.cdc_on_boot=0
+sparkfun_esp32s3_thing_plus.build.msc_on_boot=0
+sparkfun_esp32s3_thing_plus.build.dfu_on_boot=0
+sparkfun_esp32s3_thing_plus.build.f_cpu=240000000L
+sparkfun_esp32s3_thing_plus.build.flash_size=4MB
+sparkfun_esp32s3_thing_plus.build.flash_freq=80m
+sparkfun_esp32s3_thing_plus.build.flash_mode=dio
+sparkfun_esp32s3_thing_plus.build.boot=qio
+sparkfun_esp32s3_thing_plus.build.boot_freq=80m
+sparkfun_esp32s3_thing_plus.build.partitions=default
+sparkfun_esp32s3_thing_plus.build.defines=
+sparkfun_esp32s3_thing_plus.build.loop_core=
+sparkfun_esp32s3_thing_plus.build.event_core=
+sparkfun_esp32s3_thing_plus.build.psram_type=qspi
+sparkfun_esp32s3_thing_plus.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.default=Disabled
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.default.build.copy_jtag_files=0
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.builtin=Integrated USB JTAG
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.external=FTDI Adapter
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.external.build.copy_jtag_files=1
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.bridge=ESP USB Bridge
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+sparkfun_esp32s3_thing_plus.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+sparkfun_esp32s3_thing_plus.menu.PSRAM.enabled=QSPI PSRAM
+sparkfun_esp32s3_thing_plus.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+sparkfun_esp32s3_thing_plus.menu.PSRAM.enabled.build.psram_type=qspi
+
+sparkfun_esp32s3_thing_plus.menu.PSRAM.disabled=Disabled
+sparkfun_esp32s3_thing_plus.menu.PSRAM.disabled.build.defines=
+sparkfun_esp32s3_thing_plus.menu.PSRAM.disabled.build.psram_type=qspi
+sparkfun_esp32s3_thing_plus.menu.PSRAM.opi=OPI PSRAM
+sparkfun_esp32s3_thing_plus.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+sparkfun_esp32s3_thing_plus.menu.PSRAM.opi.build.psram_type=opi
+
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio=QIO 80MHz
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio.build.flash_mode=dio
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio.build.boot=qio
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio.build.boot_freq=80m
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio.build.flash_freq=80m
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120=QIO 120MHz
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120.build.flash_mode=dio
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120.build.boot=qio
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120.build.boot_freq=120m
+sparkfun_esp32s3_thing_plus.menu.FlashMode.qio120.build.flash_freq=80m
+sparkfun_esp32s3_thing_plus.menu.FlashMode.dio=DIO 80MHz
+sparkfun_esp32s3_thing_plus.menu.FlashMode.dio.build.flash_mode=dio
+sparkfun_esp32s3_thing_plus.menu.FlashMode.dio.build.boot=dio
+sparkfun_esp32s3_thing_plus.menu.FlashMode.dio.build.boot_freq=80m
+sparkfun_esp32s3_thing_plus.menu.FlashMode.dio.build.flash_freq=80m
+
+sparkfun_esp32s3_thing_plus.menu.LoopCore.1=Core 1
+sparkfun_esp32s3_thing_plus.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+sparkfun_esp32s3_thing_plus.menu.LoopCore.0=Core 0
+sparkfun_esp32s3_thing_plus.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+sparkfun_esp32s3_thing_plus.menu.EventsCore.1=Core 1
+sparkfun_esp32s3_thing_plus.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+sparkfun_esp32s3_thing_plus.menu.EventsCore.0=Core 0
+sparkfun_esp32s3_thing_plus.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+sparkfun_esp32s3_thing_plus.menu.USBMode.default=Hardware CDC and JTAG
+sparkfun_esp32s3_thing_plus.menu.USBMode.default.build.usb_mode=1
+sparkfun_esp32s3_thing_plus.menu.USBMode.hwcdc=USB-OTG (TinyUSB)
+sparkfun_esp32s3_thing_plus.menu.USBMode.hwcdc.build.usb_mode=0
+
+# sparkfun says to put that to Enabled but it fails
+sparkfun_esp32s3_thing_plus.menu.CDCOnBoot.default=Disabled
+sparkfun_esp32s3_thing_plus.menu.CDCOnBoot.default.build.cdc_on_boot=0
+sparkfun_esp32s3_thing_plus.menu.CDCOnBoot.cdc=Enabled
+sparkfun_esp32s3_thing_plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+sparkfun_esp32s3_thing_plus.menu.MSCOnBoot.default=Disabled
+sparkfun_esp32s3_thing_plus.menu.MSCOnBoot.default.build.msc_on_boot=0
+sparkfun_esp32s3_thing_plus.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+sparkfun_esp32s3_thing_plus.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+sparkfun_esp32s3_thing_plus.menu.DFUOnBoot.default=Disabled
+sparkfun_esp32s3_thing_plus.menu.DFUOnBoot.default.build.dfu_on_boot=0
+sparkfun_esp32s3_thing_plus.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+sparkfun_esp32s3_thing_plus.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+sparkfun_esp32s3_thing_plus.menu.UploadMode.default=UART0 / Hardware CDC
+sparkfun_esp32s3_thing_plus.menu.UploadMode.default.upload.use_1200bps_touch=false
+sparkfun_esp32s3_thing_plus.menu.UploadMode.default.upload.wait_for_upload_port=false
+sparkfun_esp32s3_thing_plus.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+sparkfun_esp32s3_thing_plus.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+sparkfun_esp32s3_thing_plus.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.default.build.partitions=default
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.minimal.build.partitions=minimal
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_fs.build.partitions=no_fs
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.huge_app.build.partitions=huge_app
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker=RainMaker 4MB
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.custom=Custom
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.custom.build.partitions=
+sparkfun_esp32s3_thing_plus.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.240=240MHz (WiFi)
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.240.build.f_cpu=240000000L
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.160=160MHz (WiFi)
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.160.build.f_cpu=160000000L
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.80=80MHz (WiFi)
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.80.build.f_cpu=80000000L
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.40=40MHz
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.40.build.f_cpu=40000000L
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.20=20MHz
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.20.build.f_cpu=20000000L
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.10=10MHz
+sparkfun_esp32s3_thing_plus.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.921600=921600
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.921600.upload.speed=921600
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.115200=115200
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.115200.upload.speed=115200
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.256000.windows=256000
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.256000.upload.speed=256000
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.230400.windows.upload.speed=256000
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.230400=230400
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.230400.upload.speed=230400
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.460800.linux=460800
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.460800.macosx=460800
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.460800.upload.speed=460800
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.512000.windows=512000
+sparkfun_esp32s3_thing_plus.menu.UploadSpeed.512000.upload.speed=512000
+
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.none=None
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.none.build.code_debug=0
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.error=Error
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.error.build.code_debug=1
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.warn=Warn
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.warn.build.code_debug=2
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.info=Info
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.info.build.code_debug=3
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.debug=Debug
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.debug.build.code_debug=4
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.verbose=Verbose
+sparkfun_esp32s3_thing_plus.menu.DebugLevel.verbose.build.code_debug=5
+
+sparkfun_esp32s3_thing_plus.menu.EraseFlash.none=Disabled
+sparkfun_esp32s3_thing_plus.menu.EraseFlash.none.upload.erase_cmd=
+sparkfun_esp32s3_thing_plus.menu.EraseFlash.all=Enabled
+sparkfun_esp32s3_thing_plus.menu.EraseFlash.all.upload.erase_cmd=-e
+
+sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.default=Disabled
+sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.default.build.zigbee_mode=
+sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.default.build.zigbee_libs=
+sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator)
+sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+sparkfun_esp32s3_thing_plus.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
 
-widora-air.name=Widora AIR
+##############################################################
 
-widora-air.upload.tool=esptool_py
-widora-air.upload.maximum_size=1310720
-widora-air.upload.maximum_data_size=327680
-widora-air.upload.wait_for_upload_port=true
+sparkfun_esp32c6_thing_plus.name=SparkFun ESP32-C6 Thing Plus
+
+sparkfun_esp32c6_thing_plus.bootloader.tool=esptool_py
+sparkfun_esp32c6_thing_plus.bootloader.tool.default=esptool_py
+
+sparkfun_esp32c6_thing_plus.upload.tool=esptool_py
+sparkfun_esp32c6_thing_plus.upload.tool.default=esptool_py
+sparkfun_esp32c6_thing_plus.upload.tool.network=esp_ota
+
+sparkfun_esp32c6_thing_plus.upload.maximum_size=1310720
+sparkfun_esp32c6_thing_plus.upload.maximum_data_size=327680
+sparkfun_esp32c6_thing_plus.upload.flags=
+sparkfun_esp32c6_thing_plus.upload.extra_flags=
+sparkfun_esp32c6_thing_plus.upload.use_1200bps_touch=false
+sparkfun_esp32c6_thing_plus.upload.wait_for_upload_port=false
+
+sparkfun_esp32c6_thing_plus.serial.disableDTR=false
+sparkfun_esp32c6_thing_plus.serial.disableRTS=false
+
+sparkfun_esp32c6_thing_plus.build.tarch=riscv32
+sparkfun_esp32c6_thing_plus.build.target=esp
+sparkfun_esp32c6_thing_plus.build.mcu=esp32c6
+sparkfun_esp32c6_thing_plus.build.core=esp32
+sparkfun_esp32c6_thing_plus.build.variant=sparkfun_esp32c6_thing_plus
+sparkfun_esp32c6_thing_plus.build.board=ESP32C6_THING_PLUS
+sparkfun_esp32c6_thing_plus.build.bootloader_addr=0x0
+
+sparkfun_esp32c6_thing_plus.build.cdc_on_boot=0
+sparkfun_esp32c6_thing_plus.build.f_cpu=160000000L
+sparkfun_esp32c6_thing_plus.build.flash_size=4MB
+sparkfun_esp32c6_thing_plus.build.flash_freq=80m
+sparkfun_esp32c6_thing_plus.build.flash_mode=qio
+sparkfun_esp32c6_thing_plus.build.boot=qio
+sparkfun_esp32c6_thing_plus.build.partitions=default
+sparkfun_esp32c6_thing_plus.build.defines=
+
+## IDE 2.0 Seems to not update the value
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.default=Disabled
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.default.build.copy_jtag_files=0
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.builtin=Integrated USB JTAG
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.external=FTDI Adapter
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.external.build.copy_jtag_files=1
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.bridge=ESP USB Bridge
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+sparkfun_esp32c6_thing_plus.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+sparkfun_esp32c6_thing_plus.menu.CDCOnBoot.default=Enabled
+sparkfun_esp32c6_thing_plus.menu.CDCOnBoot.default.build.cdc_on_boot=1
+sparkfun_esp32c6_thing_plus.menu.CDCOnBoot.cdc=Disabled
+sparkfun_esp32c6_thing_plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default.build.partitions=default
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.minimal.build.partitions=minimal
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.huge_app.build.partitions=huge_app
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.fatflash.build.partitions=ffat
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker=RainMaker 4MB
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee.build.partitions=zigbee
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.custom=Custom
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.custom.build.partitions=
+sparkfun_esp32c6_thing_plus.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.160=160MHz (WiFi)
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.160.build.f_cpu=160000000L
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.80=80MHz (WiFi)
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.80.build.f_cpu=80000000L
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.40=40MHz
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.40.build.f_cpu=40000000L
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.20=20MHz
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.20.build.f_cpu=20000000L
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.10=10MHz
+sparkfun_esp32c6_thing_plus.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sparkfun_esp32c6_thing_plus.menu.FlashMode.qio=QIO
+sparkfun_esp32c6_thing_plus.menu.FlashMode.qio.build.flash_mode=dio
+sparkfun_esp32c6_thing_plus.menu.FlashMode.qio.build.boot=qio
+sparkfun_esp32c6_thing_plus.menu.FlashMode.dio=DIO
+sparkfun_esp32c6_thing_plus.menu.FlashMode.dio.build.flash_mode=dio
+sparkfun_esp32c6_thing_plus.menu.FlashMode.dio.build.boot=dio
+
+sparkfun_esp32c6_thing_plus.menu.FlashFreq.80=80MHz
+sparkfun_esp32c6_thing_plus.menu.FlashFreq.80.build.flash_freq=80m
+sparkfun_esp32c6_thing_plus.menu.FlashFreq.40=40MHz
+sparkfun_esp32c6_thing_plus.menu.FlashFreq.40.build.flash_freq=40m
+
+sparkfun_esp32c6_thing_plus.menu.FlashSize.4M=4MB (32Mb)
+sparkfun_esp32c6_thing_plus.menu.FlashSize.4M.build.flash_size=4MB
+sparkfun_esp32c6_thing_plus.menu.FlashSize.8M=8MB (64Mb)
+sparkfun_esp32c6_thing_plus.menu.FlashSize.8M.build.flash_size=8MB
+sparkfun_esp32c6_thing_plus.menu.FlashSize.2M=2MB (16Mb)
+sparkfun_esp32c6_thing_plus.menu.FlashSize.2M.build.flash_size=2MB
+sparkfun_esp32c6_thing_plus.menu.FlashSize.16M=16MB (128Mb)
+sparkfun_esp32c6_thing_plus.menu.FlashSize.16M.build.flash_size=16MB
+
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.921600=921600
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.921600.upload.speed=921600
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.115200=115200
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.115200.upload.speed=115200
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.256000.windows=256000
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.256000.upload.speed=256000
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.230400.windows.upload.speed=256000
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.230400=230400
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.230400.upload.speed=230400
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.460800.linux=460800
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.460800.macosx=460800
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.460800.upload.speed=460800
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.512000.windows=512000
+sparkfun_esp32c6_thing_plus.menu.UploadSpeed.512000.upload.speed=512000
+
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.none=None
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.none.build.code_debug=0
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.error=Error
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.error.build.code_debug=1
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.warn=Warn
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.warn.build.code_debug=2
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.info=Info
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.info.build.code_debug=3
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.debug=Debug
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.debug.build.code_debug=4
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.verbose=Verbose
+sparkfun_esp32c6_thing_plus.menu.DebugLevel.verbose.build.code_debug=5
+
+sparkfun_esp32c6_thing_plus.menu.EraseFlash.none=Disabled
+sparkfun_esp32c6_thing_plus.menu.EraseFlash.none.upload.erase_cmd=
+sparkfun_esp32c6_thing_plus.menu.EraseFlash.all=Enabled
+sparkfun_esp32c6_thing_plus.menu.EraseFlash.all.upload.erase_cmd=-e
+
+sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.default=Disabled
+sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.default.build.zigbee_mode=
+sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.default.build.zigbee_libs=
+sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.ed=Zigbee ED (end device)
+sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+sparkfun_esp32c6_thing_plus.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
 
-widora-air.serial.disableDTR=true
-widora-air.serial.disableRTS=true
+##############################################################
 
-widora-air.build.mcu=esp32
-widora-air.build.core=esp32
-widora-air.build.variant=widora-air
-widora-air.build.board=WIDORA_AIR
+esp32micromod.name=SparkFun ESP32 MicroMod
+
+esp32micromod.bootloader.tool=esptool_py
+esp32micromod.bootloader.tool.default=esptool_py
+
+esp32micromod.upload.tool=esptool_py
+esp32micromod.upload.tool.default=esptool_py
+esp32micromod.upload.tool.network=esp_ota
+
+esp32micromod.upload.maximum_size=1310720
+esp32micromod.upload.maximum_data_size=327680
+esp32micromod.upload.wait_for_upload_port=true
+esp32micromod.upload.flags=
+esp32micromod.upload.extra_flags=
+
+esp32micromod.serial.disableDTR=true
+esp32micromod.serial.disableRTS=true
+
+esp32micromod.build.tarch=xtensa
+esp32micromod.build.bootloader_addr=0x1000
+esp32micromod.build.target=esp32
+esp32micromod.build.mcu=esp32
+esp32micromod.build.core=esp32
+esp32micromod.build.variant=esp32micromod
+esp32micromod.build.board=ESP32_MICROMOD
+
+esp32micromod.build.f_cpu=240000000L
+esp32micromod.build.flash_size=4MB
+esp32micromod.build.flash_freq=40m
+esp32micromod.build.flash_mode=dio
+esp32micromod.build.boot=dio
+esp32micromod.build.partitions=default
+esp32micromod.build.defines=
+
+esp32micromod.menu.PSRAM.disabled=Disabled
+esp32micromod.menu.PSRAM.disabled.build.defines=
+esp32micromod.menu.PSRAM.enabled=Enabled
+esp32micromod.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+
+esp32micromod.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32micromod.menu.PartitionScheme.default.build.partitions=default
+esp32micromod.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32micromod.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32micromod.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32micromod.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32micromod.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32micromod.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32micromod.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32micromod.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32micromod.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32micromod.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32micromod.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32micromod.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32micromod.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32micromod.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32micromod.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32micromod.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32micromod.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32micromod.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32micromod.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32micromod.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32micromod.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32micromod.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32micromod.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32micromod.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32micromod.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32micromod.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32micromod.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32micromod.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32micromod.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32micromod.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32micromod.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+esp32micromod.menu.CPUFreq.240=240MHz (WiFi/BT)
+esp32micromod.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32micromod.menu.CPUFreq.160=160MHz (WiFi/BT)
+esp32micromod.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32micromod.menu.CPUFreq.80=80MHz (WiFi/BT)
+esp32micromod.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32micromod.menu.CPUFreq.40=40MHz (40MHz XTAL)
+esp32micromod.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32micromod.menu.CPUFreq.26=26MHz (26MHz XTAL)
+esp32micromod.menu.CPUFreq.26.build.f_cpu=26000000L
+esp32micromod.menu.CPUFreq.20=20MHz (40MHz XTAL)
+esp32micromod.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32micromod.menu.CPUFreq.13=13MHz (26MHz XTAL)
+esp32micromod.menu.CPUFreq.13.build.f_cpu=13000000L
+esp32micromod.menu.CPUFreq.10=10MHz (40MHz XTAL)
+esp32micromod.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32micromod.menu.FlashMode.qio=QIO
+esp32micromod.menu.FlashMode.qio.build.flash_mode=dio
+esp32micromod.menu.FlashMode.qio.build.boot=qio
+esp32micromod.menu.FlashMode.dio=DIO
+esp32micromod.menu.FlashMode.dio.build.flash_mode=dio
+esp32micromod.menu.FlashMode.dio.build.boot=dio
+
+esp32micromod.menu.FlashFreq.80=80MHz
+esp32micromod.menu.FlashFreq.80.build.flash_freq=80m
+esp32micromod.menu.FlashFreq.40=40MHz
+esp32micromod.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32micromod.menu.FlashSize.4M=4MB (32Mb)
+esp32micromod.menu.FlashSize.4M.build.flash_size=4MB
+esp32micromod.menu.FlashSize.8M=8MB (64Mb)
+esp32micromod.menu.FlashSize.8M.build.flash_size=8MB
+esp32micromod.menu.FlashSize.2M=2MB (16Mb)
+esp32micromod.menu.FlashSize.2M.build.flash_size=2MB
+esp32micromod.menu.FlashSize.16M=16MB (128Mb)
+esp32micromod.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32micromod.menu.UploadSpeed.921600=921600
+esp32micromod.menu.UploadSpeed.921600.upload.speed=921600
+esp32micromod.menu.UploadSpeed.115200=115200
+esp32micromod.menu.UploadSpeed.115200.upload.speed=115200
+esp32micromod.menu.UploadSpeed.256000.windows=256000
+esp32micromod.menu.UploadSpeed.256000.upload.speed=256000
+esp32micromod.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32micromod.menu.UploadSpeed.230400=230400
+esp32micromod.menu.UploadSpeed.230400.upload.speed=230400
+esp32micromod.menu.UploadSpeed.460800.linux=460800
+esp32micromod.menu.UploadSpeed.460800.macosx=460800
+esp32micromod.menu.UploadSpeed.460800.upload.speed=460800
+esp32micromod.menu.UploadSpeed.512000.windows=512000
+esp32micromod.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32micromod.menu.DebugLevel.none=None
+esp32micromod.menu.DebugLevel.none.build.code_debug=0
+esp32micromod.menu.DebugLevel.error=Error
+esp32micromod.menu.DebugLevel.error.build.code_debug=1
+esp32micromod.menu.DebugLevel.warn=Warn
+esp32micromod.menu.DebugLevel.warn.build.code_debug=2
+esp32micromod.menu.DebugLevel.info=Info
+esp32micromod.menu.DebugLevel.info.build.code_debug=3
+esp32micromod.menu.DebugLevel.debug=Debug
+esp32micromod.menu.DebugLevel.debug.build.code_debug=4
+esp32micromod.menu.DebugLevel.verbose=Verbose
+esp32micromod.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32micromod.menu.EraseFlash.none=Disabled
+esp32micromod.menu.EraseFlash.none.upload.erase_cmd=
+esp32micromod.menu.EraseFlash.all=Enabled
+esp32micromod.menu.EraseFlash.all.upload.erase_cmd=-e
 
-widora-air.build.f_cpu=240000000L
-widora-air.build.flash_mode=dio
-widora-air.build.flash_size=16MB
-widora-air.build.boot=dio
-widora-air.build.partitions=default
-widora-air.build.defines=
+##############################################################
 
-widora-air.menu.FlashFreq.80=80MHz
-widora-air.menu.FlashFreq.80.build.flash_freq=80m
-widora-air.menu.FlashFreq.40=40MHz
-widora-air.menu.FlashFreq.40.build.flash_freq=40m
+sparkfun_lora_gateway_1-channel.name=SparkFun LoRa Gateway 1-Channel
 
-widora-air.menu.UploadSpeed.921600=921600
-widora-air.menu.UploadSpeed.921600.upload.speed=921600
-widora-air.menu.UploadSpeed.115200=115200
-widora-air.menu.UploadSpeed.115200.upload.speed=115200
-widora-air.menu.UploadSpeed.256000.windows=256000
-widora-air.menu.UploadSpeed.256000.upload.speed=256000
-widora-air.menu.UploadSpeed.230400.windows.upload.speed=256000
-widora-air.menu.UploadSpeed.230400=230400
-widora-air.menu.UploadSpeed.230400.upload.speed=230400
-widora-air.menu.UploadSpeed.460800.linux=460800
-widora-air.menu.UploadSpeed.460800.macosx=460800
-widora-air.menu.UploadSpeed.460800.upload.speed=460800
-widora-air.menu.UploadSpeed.512000.windows=512000
-widora-air.menu.UploadSpeed.512000.upload.speed=512000
+sparkfun_lora_gateway_1-channel.bootloader.tool=esptool_py
+sparkfun_lora_gateway_1-channel.bootloader.tool.default=esptool_py
 
-##############################################################
+sparkfun_lora_gateway_1-channel.upload.tool=esptool_py
+sparkfun_lora_gateway_1-channel.upload.tool.default=esptool_py
+sparkfun_lora_gateway_1-channel.upload.tool.network=esp_ota
 
-esp320.name=Electronic SweetPeas - ESP320
+sparkfun_lora_gateway_1-channel.upload.maximum_size=1310720
+sparkfun_lora_gateway_1-channel.upload.maximum_data_size=294912
+sparkfun_lora_gateway_1-channel.upload.flags=
+sparkfun_lora_gateway_1-channel.upload.extra_flags=
 
-esp320.upload.tool=esptool_py
-esp320.upload.maximum_size=1310720
-esp320.upload.maximum_data_size=327680
-esp320.upload.wait_for_upload_port=true
+sparkfun_lora_gateway_1-channel.serial.disableDTR=true
+sparkfun_lora_gateway_1-channel.serial.disableRTS=true
 
-esp320.serial.disableDTR=true
-esp320.serial.disableRTS=true
+sparkfun_lora_gateway_1-channel.build.tarch=xtensa
+sparkfun_lora_gateway_1-channel.build.bootloader_addr=0x1000
+sparkfun_lora_gateway_1-channel.build.target=esp32
+sparkfun_lora_gateway_1-channel.build.mcu=esp32
+sparkfun_lora_gateway_1-channel.build.core=esp32
+sparkfun_lora_gateway_1-channel.build.variant=sparkfun_lora_gateway_1-channel
+sparkfun_lora_gateway_1-channel.build.board=ESP32_DEV
 
-esp320.build.mcu=esp32
+sparkfun_lora_gateway_1-channel.build.f_cpu=240000000L
+sparkfun_lora_gateway_1-channel.build.flash_size=4MB
+sparkfun_lora_gateway_1-channel.build.flash_freq=40m
+sparkfun_lora_gateway_1-channel.build.flash_mode=dio
+sparkfun_lora_gateway_1-channel.build.boot=dio
+sparkfun_lora_gateway_1-channel.build.partitions=default
+
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.default=Default
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.default.build.partitions=default
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.minimal=Minimal (2MB FLASH)
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.minimal.build.partitions=minimal
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.no_ota=No OTA (Large APP)
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sparkfun_lora_gateway_1-channel.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+sparkfun_lora_gateway_1-channel.menu.FlashMode.qio=QIO
+sparkfun_lora_gateway_1-channel.menu.FlashMode.qio.build.flash_mode=dio
+sparkfun_lora_gateway_1-channel.menu.FlashMode.qio.build.boot=qio
+sparkfun_lora_gateway_1-channel.menu.FlashMode.dio=DIO
+sparkfun_lora_gateway_1-channel.menu.FlashMode.dio.build.flash_mode=dio
+sparkfun_lora_gateway_1-channel.menu.FlashMode.dio.build.boot=dio
+
+sparkfun_lora_gateway_1-channel.menu.FlashFreq.80=80MHz
+sparkfun_lora_gateway_1-channel.menu.FlashFreq.80.build.flash_freq=80m
+sparkfun_lora_gateway_1-channel.menu.FlashFreq.40=40MHz
+sparkfun_lora_gateway_1-channel.menu.FlashFreq.40.build.flash_freq=40m
+
+sparkfun_lora_gateway_1-channel.menu.FlashSize.4M=4MB (32Mb)
+sparkfun_lora_gateway_1-channel.menu.FlashSize.4M.build.flash_size=4MB
+
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.921600=921600
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.921600.upload.speed=921600
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.115200=115200
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.115200.upload.speed=115200
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.256000.windows=256000
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.256000.upload.speed=256000
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.230400.windows.upload.speed=256000
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.230400=230400
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.230400.upload.speed=230400
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.460800.linux=460800
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.460800.macosx=460800
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.460800.upload.speed=460800
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.512000.windows=512000
+sparkfun_lora_gateway_1-channel.menu.UploadSpeed.512000.upload.speed=512000
+
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.none=None
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.none.build.code_debug=0
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.error=Error
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.error.build.code_debug=1
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.warn=Warn
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.warn.build.code_debug=2
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.info=Info
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.info.build.code_debug=3
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.debug=Debug
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.debug.build.code_debug=4
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.verbose=Verbose
+sparkfun_lora_gateway_1-channel.menu.DebugLevel.verbose.build.code_debug=5
+
+sparkfun_lora_gateway_1-channel.menu.EraseFlash.none=Disabled
+sparkfun_lora_gateway_1-channel.menu.EraseFlash.none.upload.erase_cmd=
+sparkfun_lora_gateway_1-channel.menu.EraseFlash.all=Enabled
+sparkfun_lora_gateway_1-channel.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+sparkfun_esp32_iot_redboard.name=SparkFun ESP32 IoT RedBoard
+
+sparkfun_esp32_iot_redboard.bootloader.tool=esptool_py
+sparkfun_esp32_iot_redboard.bootloader.tool.default=esptool_py
+
+sparkfun_esp32_iot_redboard.upload.tool=esptool_py
+sparkfun_esp32_iot_redboard.upload.tool.default=esptool_py
+sparkfun_esp32_iot_redboard.upload.tool.network=esp_ota
+
+sparkfun_esp32_iot_redboard.upload.maximum_size=1310720
+sparkfun_esp32_iot_redboard.upload.maximum_data_size=327680
+sparkfun_esp32_iot_redboard.upload.flags=
+sparkfun_esp32_iot_redboard.upload.extra_flags=
+
+sparkfun_esp32_iot_redboard.serial.disableDTR=true
+sparkfun_esp32_iot_redboard.serial.disableRTS=true
+
+sparkfun_esp32_iot_redboard.build.tarch=xtensa
+sparkfun_esp32_iot_redboard.build.bootloader_addr=0x1000
+sparkfun_esp32_iot_redboard.build.target=esp32
+sparkfun_esp32_iot_redboard.build.mcu=esp32
+sparkfun_esp32_iot_redboard.build.core=esp32
+sparkfun_esp32_iot_redboard.build.variant=sparkfun_esp32_iot_redboard
+sparkfun_esp32_iot_redboard.build.board=ESP32_IOT_REDBOARD
+
+sparkfun_esp32_iot_redboard.build.f_cpu=240000000L
+sparkfun_esp32_iot_redboard.build.flash_size=4MB
+sparkfun_esp32_iot_redboard.build.flash_freq=40m
+sparkfun_esp32_iot_redboard.build.flash_mode=dio
+sparkfun_esp32_iot_redboard.build.boot=dio
+sparkfun_esp32_iot_redboard.build.partitions=default
+sparkfun_esp32_iot_redboard.build.defines=
+sparkfun_esp32_iot_redboard.build.loop_core=
+sparkfun_esp32_iot_redboard.build.event_core=
+
+sparkfun_esp32_iot_redboard.menu.PSRAM.disabled=Disabled
+sparkfun_esp32_iot_redboard.menu.PSRAM.disabled.build.defines=
+sparkfun_esp32_iot_redboard.menu.PSRAM.disabled.build.extra_libs=
+sparkfun_esp32_iot_redboard.menu.PSRAM.enabled=Enabled
+sparkfun_esp32_iot_redboard.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+sparkfun_esp32_iot_redboard.menu.PSRAM.enabled.build.extra_libs=
+
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.default.build.partitions=default
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.minimal.build.partitions=minimal
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.huge_app.build.partitions=huge_app
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.fatflash.build.partitions=ffat
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker=RainMaker 4MB
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+sparkfun_esp32_iot_redboard.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+sparkfun_esp32_iot_redboard.menu.CPUFreq.240=240MHz (WiFi/BT)
+sparkfun_esp32_iot_redboard.menu.CPUFreq.240.build.f_cpu=240000000L
+sparkfun_esp32_iot_redboard.menu.CPUFreq.160=160MHz (WiFi/BT)
+sparkfun_esp32_iot_redboard.menu.CPUFreq.160.build.f_cpu=160000000L
+sparkfun_esp32_iot_redboard.menu.CPUFreq.80=80MHz (WiFi/BT)
+sparkfun_esp32_iot_redboard.menu.CPUFreq.80.build.f_cpu=80000000L
+sparkfun_esp32_iot_redboard.menu.CPUFreq.40=40MHz (40MHz XTAL)
+sparkfun_esp32_iot_redboard.menu.CPUFreq.40.build.f_cpu=40000000L
+sparkfun_esp32_iot_redboard.menu.CPUFreq.26=26MHz (26MHz XTAL)
+sparkfun_esp32_iot_redboard.menu.CPUFreq.26.build.f_cpu=26000000L
+sparkfun_esp32_iot_redboard.menu.CPUFreq.20=20MHz (40MHz XTAL)
+sparkfun_esp32_iot_redboard.menu.CPUFreq.20.build.f_cpu=20000000L
+sparkfun_esp32_iot_redboard.menu.CPUFreq.13=13MHz (26MHz XTAL)
+sparkfun_esp32_iot_redboard.menu.CPUFreq.13.build.f_cpu=13000000L
+sparkfun_esp32_iot_redboard.menu.CPUFreq.10=10MHz (40MHz XTAL)
+sparkfun_esp32_iot_redboard.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sparkfun_esp32_iot_redboard.menu.FlashMode.qio=QIO
+sparkfun_esp32_iot_redboard.menu.FlashMode.qio.build.flash_mode=dio
+sparkfun_esp32_iot_redboard.menu.FlashMode.qio.build.boot=qio
+sparkfun_esp32_iot_redboard.menu.FlashMode.dio=DIO
+sparkfun_esp32_iot_redboard.menu.FlashMode.dio.build.flash_mode=dio
+sparkfun_esp32_iot_redboard.menu.FlashMode.dio.build.boot=dio
+
+sparkfun_esp32_iot_redboard.menu.FlashFreq.80=80MHz
+sparkfun_esp32_iot_redboard.menu.FlashFreq.80.build.flash_freq=80m
+sparkfun_esp32_iot_redboard.menu.FlashFreq.40=40MHz
+sparkfun_esp32_iot_redboard.menu.FlashFreq.40.build.flash_freq=40m
+
+sparkfun_esp32_iot_redboard.menu.FlashSize.4M=4MB (32Mb)
+sparkfun_esp32_iot_redboard.menu.FlashSize.4M.build.flash_size=4MB
+sparkfun_esp32_iot_redboard.menu.FlashSize.8M=8MB (64Mb)
+sparkfun_esp32_iot_redboard.menu.FlashSize.8M.build.flash_size=8MB
+sparkfun_esp32_iot_redboard.menu.FlashSize.2M=2MB (16Mb)
+sparkfun_esp32_iot_redboard.menu.FlashSize.2M.build.flash_size=2MB
+sparkfun_esp32_iot_redboard.menu.FlashSize.16M=16MB (128Mb)
+sparkfun_esp32_iot_redboard.menu.FlashSize.16M.build.flash_size=16MB
+
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.921600=921600
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.921600.upload.speed=921600
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.115200=115200
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.115200.upload.speed=115200
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.256000.windows=256000
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.256000.upload.speed=256000
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.230400.windows.upload.speed=256000
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.230400=230400
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.230400.upload.speed=230400
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.460800.linux=460800
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.460800.macosx=460800
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.460800.upload.speed=460800
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.512000.windows=512000
+sparkfun_esp32_iot_redboard.menu.UploadSpeed.512000.upload.speed=512000
+
+sparkfun_esp32_iot_redboard.menu.LoopCore.1=Core 1
+sparkfun_esp32_iot_redboard.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+sparkfun_esp32_iot_redboard.menu.LoopCore.0=Core 0
+sparkfun_esp32_iot_redboard.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+sparkfun_esp32_iot_redboard.menu.EventsCore.1=Core 1
+sparkfun_esp32_iot_redboard.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+sparkfun_esp32_iot_redboard.menu.EventsCore.0=Core 0
+sparkfun_esp32_iot_redboard.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+sparkfun_esp32_iot_redboard.menu.DebugLevel.none=None
+sparkfun_esp32_iot_redboard.menu.DebugLevel.none.build.code_debug=0
+sparkfun_esp32_iot_redboard.menu.DebugLevel.error=Error
+sparkfun_esp32_iot_redboard.menu.DebugLevel.error.build.code_debug=1
+sparkfun_esp32_iot_redboard.menu.DebugLevel.warn=Warn
+sparkfun_esp32_iot_redboard.menu.DebugLevel.warn.build.code_debug=2
+sparkfun_esp32_iot_redboard.menu.DebugLevel.info=Info
+sparkfun_esp32_iot_redboard.menu.DebugLevel.info.build.code_debug=3
+sparkfun_esp32_iot_redboard.menu.DebugLevel.debug=Debug
+sparkfun_esp32_iot_redboard.menu.DebugLevel.debug.build.code_debug=4
+sparkfun_esp32_iot_redboard.menu.DebugLevel.verbose=Verbose
+sparkfun_esp32_iot_redboard.menu.DebugLevel.verbose.build.code_debug=5
+
+sparkfun_esp32_iot_redboard.menu.EraseFlash.none=Disabled
+sparkfun_esp32_iot_redboard.menu.EraseFlash.none.upload.erase_cmd=
+sparkfun_esp32_iot_redboard.menu.EraseFlash.all=Enabled
+sparkfun_esp32_iot_redboard.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+sparkfun_esp32c6_qwiic_pocket.name=SparkFun ESP32-C6 Qwiic Pocket
+
+sparkfun_esp32c6_qwiic_pocket.bootloader.tool=esptool_py
+sparkfun_esp32c6_qwiic_pocket.bootloader.tool.default=esptool_py
+
+sparkfun_esp32c6_qwiic_pocket.upload.tool=esptool_py
+sparkfun_esp32c6_qwiic_pocket.upload.tool.default=esptool_py
+sparkfun_esp32c6_qwiic_pocket.upload.tool.network=esp_ota
+
+sparkfun_esp32c6_qwiic_pocket.upload.maximum_size=1310720
+sparkfun_esp32c6_qwiic_pocket.upload.maximum_data_size=327680
+sparkfun_esp32c6_qwiic_pocket.upload.flags=
+sparkfun_esp32c6_qwiic_pocket.upload.extra_flags=
+sparkfun_esp32c6_qwiic_pocket.upload.use_1200bps_touch=false
+sparkfun_esp32c6_qwiic_pocket.upload.wait_for_upload_port=false
+
+sparkfun_esp32c6_qwiic_pocket.serial.disableDTR=false
+sparkfun_esp32c6_qwiic_pocket.serial.disableRTS=false
+
+sparkfun_esp32c6_qwiic_pocket.build.tarch=riscv32
+sparkfun_esp32c6_qwiic_pocket.build.target=esp
+sparkfun_esp32c6_qwiic_pocket.build.mcu=esp32c6
+sparkfun_esp32c6_qwiic_pocket.build.core=esp32
+sparkfun_esp32c6_qwiic_pocket.build.variant=sparkfun_esp32c6_qwiic_pocket
+sparkfun_esp32c6_qwiic_pocket.build.board=ESP32C6_QWIIC_POCKET
+sparkfun_esp32c6_qwiic_pocket.build.bootloader_addr=0x0
+
+sparkfun_esp32c6_qwiic_pocket.build.cdc_on_boot=0
+sparkfun_esp32c6_qwiic_pocket.build.f_cpu=160000000L
+sparkfun_esp32c6_qwiic_pocket.build.flash_size=4MB
+sparkfun_esp32c6_qwiic_pocket.build.flash_freq=80m
+sparkfun_esp32c6_qwiic_pocket.build.flash_mode=qio
+sparkfun_esp32c6_qwiic_pocket.build.boot=qio
+sparkfun_esp32c6_qwiic_pocket.build.partitions=default
+sparkfun_esp32c6_qwiic_pocket.build.defines=
+
+## IDE 2.0 Seems to not update the value
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.default=Disabled
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.default.build.copy_jtag_files=0
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.builtin=Integrated USB JTAG
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.external=FTDI Adapter
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.external.build.copy_jtag_files=1
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.bridge=ESP USB Bridge
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+sparkfun_esp32c6_qwiic_pocket.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+sparkfun_esp32c6_qwiic_pocket.menu.CDCOnBoot.default=Enabled
+sparkfun_esp32c6_qwiic_pocket.menu.CDCOnBoot.default.build.cdc_on_boot=1
+sparkfun_esp32c6_qwiic_pocket.menu.CDCOnBoot.cdc=Disabled
+sparkfun_esp32c6_qwiic_pocket.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default.build.partitions=default
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.minimal.build.partitions=minimal
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.huge_app.build.partitions=huge_app
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.fatflash.build.partitions=ffat
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker=RainMaker 4MB
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee.build.partitions=zigbee
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.custom=Custom
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.custom.build.partitions=
+sparkfun_esp32c6_qwiic_pocket.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.160=160MHz (WiFi)
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.160.build.f_cpu=160000000L
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.80=80MHz (WiFi)
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.80.build.f_cpu=80000000L
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.40=40MHz
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.40.build.f_cpu=40000000L
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.20=20MHz
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.20.build.f_cpu=20000000L
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.10=10MHz
+sparkfun_esp32c6_qwiic_pocket.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.qio=QIO
+sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.qio.build.flash_mode=dio
+sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.qio.build.boot=qio
+sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.dio=DIO
+sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.dio.build.flash_mode=dio
+sparkfun_esp32c6_qwiic_pocket.menu.FlashMode.dio.build.boot=dio
+
+sparkfun_esp32c6_qwiic_pocket.menu.FlashFreq.80=80MHz
+sparkfun_esp32c6_qwiic_pocket.menu.FlashFreq.80.build.flash_freq=80m
+sparkfun_esp32c6_qwiic_pocket.menu.FlashFreq.40=40MHz
+sparkfun_esp32c6_qwiic_pocket.menu.FlashFreq.40.build.flash_freq=40m
+
+sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.4M=4MB (32Mb)
+sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.4M.build.flash_size=4MB
+sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.8M=8MB (64Mb)
+sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.8M.build.flash_size=8MB
+sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.2M=2MB (16Mb)
+sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.2M.build.flash_size=2MB
+sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.16M=16MB (128Mb)
+sparkfun_esp32c6_qwiic_pocket.menu.FlashSize.16M.build.flash_size=16MB
+
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.921600=921600
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.921600.upload.speed=921600
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.115200=115200
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.115200.upload.speed=115200
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.256000.windows=256000
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.256000.upload.speed=256000
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.230400.windows.upload.speed=256000
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.230400=230400
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.230400.upload.speed=230400
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.460800.linux=460800
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.460800.macosx=460800
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.460800.upload.speed=460800
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.512000.windows=512000
+sparkfun_esp32c6_qwiic_pocket.menu.UploadSpeed.512000.upload.speed=512000
+
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.none=None
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.none.build.code_debug=0
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.error=Error
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.error.build.code_debug=1
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.warn=Warn
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.warn.build.code_debug=2
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.info=Info
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.info.build.code_debug=3
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.debug=Debug
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.debug.build.code_debug=4
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.verbose=Verbose
+sparkfun_esp32c6_qwiic_pocket.menu.DebugLevel.verbose.build.code_debug=5
+
+sparkfun_esp32c6_qwiic_pocket.menu.EraseFlash.none=Disabled
+sparkfun_esp32c6_qwiic_pocket.menu.EraseFlash.none.upload.erase_cmd=
+sparkfun_esp32c6_qwiic_pocket.menu.EraseFlash.all=Enabled
+sparkfun_esp32c6_qwiic_pocket.menu.EraseFlash.all.upload.erase_cmd=-e
+
+sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.default=Disabled
+sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.default.build.zigbee_mode=
+sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.default.build.zigbee_libs=
+sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.ed=Zigbee ED (end device)
+sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+sparkfun_esp32c6_qwiic_pocket.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+# SparkFun Pro Micro ESP32C3
+
+sparkfun_pro_micro_esp32c3.name=SparkFun Pro Micro - ESP32C3
+sparkfun_pro_micro_esp32c3.vid.0=0x1B4F
+sparkfun_pro_micro_esp32c3.pid.0=0x0035
+
+sparkfun_pro_micro_esp32c3.bootloader.tool=esptool_py
+sparkfun_pro_micro_esp32c3.bootloader.tool.default=esptool_py
+
+sparkfun_pro_micro_esp32c3.upload.tool=esptool_py
+sparkfun_pro_micro_esp32c3.upload.tool.default=esptool_py
+sparkfun_pro_micro_esp32c3.upload.tool.network=esp_ota
+
+sparkfun_pro_micro_esp32c3.upload.maximum_size=1310720
+sparkfun_pro_micro_esp32c3.upload.maximum_data_size=327680
+sparkfun_pro_micro_esp32c3.upload.flags=
+sparkfun_pro_micro_esp32c3.upload.extra_flags=
+sparkfun_pro_micro_esp32c3.upload.use_1200bps_touch=false
+sparkfun_pro_micro_esp32c3.upload.wait_for_upload_port=false
+
+sparkfun_pro_micro_esp32c3.serial.disableDTR=false
+sparkfun_pro_micro_esp32c3.serial.disableRTS=false
+
+sparkfun_pro_micro_esp32c3.build.tarch=riscv32
+sparkfun_pro_micro_esp32c3.build.bootloader_addr=0x0
+sparkfun_pro_micro_esp32c3.build.target=esp
+sparkfun_pro_micro_esp32c3.build.mcu=esp32c3
+sparkfun_pro_micro_esp32c3.build.core=esp32
+sparkfun_pro_micro_esp32c3.build.variant=sparkfun_pro_micro_esp32c3
+sparkfun_pro_micro_esp32c3.build.board=SPARKFUN_PRO_MICRO_ESP32C3
+
+sparkfun_pro_micro_esp32c3.build.cdc_on_boot=1
+sparkfun_pro_micro_esp32c3.build.f_cpu=160000000L
+sparkfun_pro_micro_esp32c3.build.flash_size=4MB
+sparkfun_pro_micro_esp32c3.build.flash_freq=80m
+sparkfun_pro_micro_esp32c3.build.flash_mode=dio
+sparkfun_pro_micro_esp32c3.build.boot=qio
+sparkfun_pro_micro_esp32c3.build.partitions=default
+sparkfun_pro_micro_esp32c3.build.defines=
+
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.default=Disabled
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.external=FTDI Adapter
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.bridge=ESP USB Bridge
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg
+sparkfun_pro_micro_esp32c3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+sparkfun_pro_micro_esp32c3.menu.CDCOnBoot.cdc=Enabled
+sparkfun_pro_micro_esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+sparkfun_pro_micro_esp32c3.menu.CDCOnBoot.default=Enabled
+sparkfun_pro_micro_esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.default.build.partitions=default
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sparkfun_pro_micro_esp32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.160=160MHz (WiFi)
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.80=80MHz (WiFi)
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.40=40MHz
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.20=20MHz
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.10=10MHz
+sparkfun_pro_micro_esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sparkfun_pro_micro_esp32c3.menu.FlashMode.qio=QIO
+sparkfun_pro_micro_esp32c3.menu.FlashMode.qio.build.flash_mode=dio
+sparkfun_pro_micro_esp32c3.menu.FlashMode.qio.build.boot=qio
+sparkfun_pro_micro_esp32c3.menu.FlashMode.dio=DIO
+sparkfun_pro_micro_esp32c3.menu.FlashMode.dio.build.flash_mode=dio
+sparkfun_pro_micro_esp32c3.menu.FlashMode.dio.build.boot=dio
+sparkfun_pro_micro_esp32c3.menu.FlashMode.qout=QOUT
+sparkfun_pro_micro_esp32c3.menu.FlashMode.qout.build.flash_mode=dout
+sparkfun_pro_micro_esp32c3.menu.FlashMode.qout.build.boot=qout
+sparkfun_pro_micro_esp32c3.menu.FlashMode.dout=DOUT
+sparkfun_pro_micro_esp32c3.menu.FlashMode.dout.build.flash_mode=dout
+sparkfun_pro_micro_esp32c3.menu.FlashMode.dout.build.boot=dout
+
+sparkfun_pro_micro_esp32c3.menu.FlashFreq.80=80MHz
+sparkfun_pro_micro_esp32c3.menu.FlashFreq.80.build.flash_freq=80m
+sparkfun_pro_micro_esp32c3.menu.FlashFreq.40=40MHz
+sparkfun_pro_micro_esp32c3.menu.FlashFreq.40.build.flash_freq=40m
+
+sparkfun_pro_micro_esp32c3.menu.FlashSize.4M=4MB (32Mb)
+sparkfun_pro_micro_esp32c3.menu.FlashSize.4M.build.flash_size=4MB
+
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.921600=921600
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.921600.upload.speed=921600
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.115200=115200
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.115200.upload.speed=115200
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.256000.windows=256000
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.256000.upload.speed=256000
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.230400=230400
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.230400.upload.speed=230400
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.460800.linux=460800
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.460800.macosx=460800
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.460800.upload.speed=460800
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.512000.windows=512000
+sparkfun_pro_micro_esp32c3.menu.UploadSpeed.512000.upload.speed=512000
+
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.none=None
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.none.build.code_debug=0
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.error=Error
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.error.build.code_debug=1
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.warn=Warn
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.warn.build.code_debug=2
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.info=Info
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.info.build.code_debug=3
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.debug=Debug
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.debug.build.code_debug=4
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.verbose=Verbose
+sparkfun_pro_micro_esp32c3.menu.DebugLevel.verbose.build.code_debug=5
+
+sparkfun_pro_micro_esp32c3.menu.EraseFlash.none=Disabled
+sparkfun_pro_micro_esp32c3.menu.EraseFlash.none.upload.erase_cmd=
+sparkfun_pro_micro_esp32c3.menu.EraseFlash.all=Enabled
+sparkfun_pro_micro_esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+nina_w10.name=u-blox NINA-W10 series (ESP32)
+
+nina_w10.bootloader.tool=esptool_py
+nina_w10.bootloader.tool.default=esptool_py
+
+nina_w10.upload.tool=esptool_py
+nina_w10.upload.tool.default=esptool_py
+nina_w10.upload.tool.network=esp_ota
+
+nina_w10.upload.maximum_size=1310720
+nina_w10.upload.maximum_data_size=327680
+nina_w10.upload.flags=
+nina_w10.upload.extra_flags=
+
+nina_w10.serial.disableDTR=true
+nina_w10.serial.disableRTS=true
+
+nina_w10.build.tarch=xtensa
+nina_w10.build.bootloader_addr=0x1000
+nina_w10.build.target=esp32
+nina_w10.build.mcu=esp32
+nina_w10.build.core=esp32
+nina_w10.build.variant=nina_w10
+nina_w10.build.board=UBLOX_NINA_W10
+nina_w10.build.f_cpu=240000000L
+nina_w10.build.boot=dio
+nina_w10.build.partitions=minimal
+nina_w10.build.flash_mode=dio
+nina_w10.build.flash_size=2MB
+nina_w10.build.flash_freq=40m
+nina_w10.build.defines=
+nina_w10.build.extra_libs=
+nina_w10.build.loop_core=
+nina_w10.build.event_core=
+
+nina_w10.menu.UploadSpeed.921600=921600
+nina_w10.menu.UploadSpeed.921600.upload.speed=921600
+nina_w10.menu.UploadSpeed.115200=115200
+nina_w10.menu.UploadSpeed.115200.upload.speed=115200
+nina_w10.menu.UploadSpeed.256000.windows=256000
+nina_w10.menu.UploadSpeed.256000.upload.speed=256000
+nina_w10.menu.UploadSpeed.230400.windows.upload.speed=256000
+nina_w10.menu.UploadSpeed.230400=230400
+nina_w10.menu.UploadSpeed.230400.upload.speed=230400
+nina_w10.menu.UploadSpeed.460800.linux=460800
+nina_w10.menu.UploadSpeed.460800.macosx=460800
+nina_w10.menu.UploadSpeed.460800.upload.speed=460800
+nina_w10.menu.UploadSpeed.512000.windows=512000
+nina_w10.menu.UploadSpeed.512000.upload.speed=512000
+
+nina_w10.menu.FlashSize.2M=2MB (16Mb, NINA-W101/W102)
+nina_w10.menu.FlashSize.2M.build.flash_size=2MB
+nina_w10.menu.FlashSize.4M=4MB (32Mb, NINA-W106-00B)
+nina_w10.menu.FlashSize.4M.build.flash_size=4MB
+nina_w10.menu.FlashSize.8M=8MB (64Mb, NINA-W106-10B)
+nina_w10.menu.FlashSize.8M.build.flash_size=8MB
+
+nina_w10.menu.FlashFreq.80=80MHz
+nina_w10.menu.FlashFreq.80.build.flash_freq=80m
+nina_w10.menu.FlashFreq.40=40MHz
+nina_w10.menu.FlashFreq.40.build.flash_freq=40m
+
+nina_w10.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+nina_w10.menu.PartitionScheme.minimal.build.partitions=minimal
+nina_w10.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+nina_w10.menu.PartitionScheme.default.build.partitions=default
+nina_w10.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+nina_w10.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+nina_w10.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+nina_w10.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+nina_w10.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+nina_w10.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+nina_w10.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+nina_w10.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+nina_w10.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+nina_w10.menu.PartitionScheme.no_ota.build.partitions=no_ota
+nina_w10.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+nina_w10.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+nina_w10.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+nina_w10.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+nina_w10.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+nina_w10.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+nina_w10.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+nina_w10.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+nina_w10.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+nina_w10.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+nina_w10.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+nina_w10.menu.PartitionScheme.huge_app.build.partitions=huge_app
+nina_w10.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+nina_w10.menu.PartitionScheme.rainmaker=RainMaker 4MB
+nina_w10.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+nina_w10.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+nina_w10.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+nina_w10.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+nina_w10.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+nina_w10.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+nina_w10.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+nina_w10.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+nina_w10.menu.CPUFreq.240=240MHz (WiFi/BT)
+nina_w10.menu.CPUFreq.240.build.f_cpu=240000000L
+nina_w10.menu.CPUFreq.160=160MHz (WiFi/BT)
+nina_w10.menu.CPUFreq.160.build.f_cpu=160000000L
+nina_w10.menu.CPUFreq.80=80MHz (WiFi/BT)
+nina_w10.menu.CPUFreq.80.build.f_cpu=80000000L
+nina_w10.menu.CPUFreq.40=40MHz (40MHz XTAL)
+nina_w10.menu.CPUFreq.40.build.f_cpu=40000000L
+nina_w10.menu.CPUFreq.26=26MHz (26MHz XTAL)
+nina_w10.menu.CPUFreq.26.build.f_cpu=26000000L
+nina_w10.menu.CPUFreq.20=20MHz (40MHz XTAL)
+nina_w10.menu.CPUFreq.20.build.f_cpu=20000000L
+nina_w10.menu.CPUFreq.13=13MHz (26MHz XTAL)
+nina_w10.menu.CPUFreq.13.build.f_cpu=13000000L
+nina_w10.menu.CPUFreq.10=10MHz (40MHz XTAL)
+nina_w10.menu.CPUFreq.10.build.f_cpu=10000000L
+
+nina_w10.menu.LoopCore.1=Core 1
+nina_w10.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+nina_w10.menu.LoopCore.0=Core 0
+nina_w10.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+nina_w10.menu.EventsCore.1=Core 1
+nina_w10.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+nina_w10.menu.EventsCore.0=Core 0
+nina_w10.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+nina_w10.menu.DebugLevel.none=None
+nina_w10.menu.DebugLevel.none.build.code_debug=0
+nina_w10.menu.DebugLevel.error=Error
+nina_w10.menu.DebugLevel.error.build.code_debug=1
+nina_w10.menu.DebugLevel.warn=Warn
+nina_w10.menu.DebugLevel.warn.build.code_debug=2
+nina_w10.menu.DebugLevel.info=Info
+nina_w10.menu.DebugLevel.info.build.code_debug=3
+nina_w10.menu.DebugLevel.debug=Debug
+nina_w10.menu.DebugLevel.debug.build.code_debug=4
+nina_w10.menu.DebugLevel.verbose=Verbose
+nina_w10.menu.DebugLevel.verbose.build.code_debug=5
+
+nina_w10.menu.EraseFlash.none=Disabled
+nina_w10.menu.EraseFlash.none.upload.erase_cmd=
+nina_w10.menu.EraseFlash.all=Enabled
+nina_w10.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+nora_w10.name=u-blox NORA-W10 series (ESP32-S3)
+
+nora_w10.bootloader.tool=esptool_py
+nora_w10.bootloader.tool.default=esptool_py
+
+nora_w10.upload.tool=esptool_py
+nora_w10.upload.tool.default=esptool_py
+nora_w10.upload.tool.network=esp_ota
+
+nora_w10.upload.maximum_size=1310720
+nora_w10.upload.maximum_data_size=327680
+nora_w10.upload.flags=
+nora_w10.upload.extra_flags=
+nora_w10.upload.use_1200bps_touch=false
+nora_w10.upload.wait_for_upload_port=false
+
+nora_w10.serial.disableDTR=false
+nora_w10.serial.disableRTS=false
+
+nora_w10.build.tarch=xtensa
+nora_w10.build.bootloader_addr=0x0
+nora_w10.build.target=esp32s3
+nora_w10.build.mcu=esp32s3
+nora_w10.build.core=esp32
+nora_w10.build.variant=nora_w10
+nora_w10.build.board=UBLOX_NORA_W10
+
+nora_w10.build.usb_mode=1
+nora_w10.build.cdc_on_boot=0
+nora_w10.build.msc_on_boot=0
+nora_w10.build.dfu_on_boot=0
+nora_w10.build.f_cpu=240000000L
+nora_w10.build.flash_size=4MB
+nora_w10.build.flash_freq=80m
+nora_w10.build.flash_mode=dio
+nora_w10.build.boot=qio
+nora_w10.build.boot_freq=80m
+nora_w10.build.partitions=default
+nora_w10.build.defines=
+nora_w10.build.loop_core=
+nora_w10.build.event_core=
+nora_w10.build.psram_type=qspi
+nora_w10.build.memory_type={build.boot}_{build.psram_type}
+
+nora_w10.menu.PSRAM.disabled=Disabled
+nora_w10.menu.PSRAM.disabled.build.defines=
+nora_w10.menu.PSRAM.disabled.build.psram_type=qspi
+nora_w10.menu.PSRAM.enabled=QSPI PSRAM
+nora_w10.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+nora_w10.menu.PSRAM.enabled.build.psram_type=qspi
+nora_w10.menu.PSRAM.opi=OPI PSRAM
+nora_w10.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+nora_w10.menu.PSRAM.opi.build.psram_type=opi
+
+nora_w10.menu.FlashMode.qio=QIO 80MHz
+nora_w10.menu.FlashMode.qio.build.flash_mode=dio
+nora_w10.menu.FlashMode.qio.build.boot=qio
+nora_w10.menu.FlashMode.qio.build.boot_freq=80m
+nora_w10.menu.FlashMode.qio.build.flash_freq=80m
+nora_w10.menu.FlashMode.qio120=QIO 120MHz
+nora_w10.menu.FlashMode.qio120.build.flash_mode=dio
+nora_w10.menu.FlashMode.qio120.build.boot=qio
+nora_w10.menu.FlashMode.qio120.build.boot_freq=120m
+nora_w10.menu.FlashMode.qio120.build.flash_freq=80m
+nora_w10.menu.FlashMode.dio=DIO 80MHz
+nora_w10.menu.FlashMode.dio.build.flash_mode=dio
+nora_w10.menu.FlashMode.dio.build.boot=dio
+nora_w10.menu.FlashMode.dio.build.boot_freq=80m
+nora_w10.menu.FlashMode.dio.build.flash_freq=80m
+nora_w10.menu.FlashMode.opi=OPI 80MHz
+nora_w10.menu.FlashMode.opi.build.flash_mode=dout
+nora_w10.menu.FlashMode.opi.build.boot=opi
+nora_w10.menu.FlashMode.opi.build.boot_freq=80m
+nora_w10.menu.FlashMode.opi.build.flash_freq=80m
+
+nora_w10.menu.FlashSize.4M=4MB (32Mb)
+nora_w10.menu.FlashSize.4M.build.flash_size=4MB
+nora_w10.menu.FlashSize.8M=8MB (64Mb)
+nora_w10.menu.FlashSize.8M.build.flash_size=8MB
+#nora_w10.menu.FlashSize.16M=16MB (128Mb)
+#nora_w10.menu.FlashSize.16M.build.flash_size=16MB
+#nora_w10.menu.FlashSize.32M=32MB (256Mb)
+#nora_w10.menu.FlashSize.32M.build.flash_size=32MB
+
+nora_w10.menu.LoopCore.1=Core 1
+nora_w10.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+nora_w10.menu.LoopCore.0=Core 0
+nora_w10.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+nora_w10.menu.EventsCore.1=Core 1
+nora_w10.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+nora_w10.menu.EventsCore.0=Core 0
+nora_w10.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+nora_w10.menu.USBMode.hwcdc=Hardware CDC and JTAG
+nora_w10.menu.USBMode.hwcdc.build.usb_mode=1
+nora_w10.menu.USBMode.default=USB-OTG (TinyUSB)
+nora_w10.menu.USBMode.default.build.usb_mode=0
+
+nora_w10.menu.CDCOnBoot.default=Disabled
+nora_w10.menu.CDCOnBoot.default.build.cdc_on_boot=0
+nora_w10.menu.CDCOnBoot.cdc=Enabled
+nora_w10.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+nora_w10.menu.MSCOnBoot.default=Disabled
+nora_w10.menu.MSCOnBoot.default.build.msc_on_boot=0
+nora_w10.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+nora_w10.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+nora_w10.menu.DFUOnBoot.default=Disabled
+nora_w10.menu.DFUOnBoot.default.build.dfu_on_boot=0
+nora_w10.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+nora_w10.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+nora_w10.menu.UploadMode.default=UART0 / Hardware CDC
+nora_w10.menu.UploadMode.default.upload.use_1200bps_touch=false
+nora_w10.menu.UploadMode.default.upload.wait_for_upload_port=false
+nora_w10.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+nora_w10.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+nora_w10.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+nora_w10.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+nora_w10.menu.PartitionScheme.default.build.partitions=default
+nora_w10.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+nora_w10.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+nora_w10.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+nora_w10.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+nora_w10.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+nora_w10.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+nora_w10.menu.PartitionScheme.minimal.build.partitions=minimal
+nora_w10.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+nora_w10.menu.PartitionScheme.no_ota.build.partitions=no_ota
+nora_w10.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+nora_w10.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+nora_w10.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+nora_w10.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+nora_w10.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+nora_w10.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+nora_w10.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+nora_w10.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+nora_w10.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+nora_w10.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+nora_w10.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+nora_w10.menu.PartitionScheme.huge_app.build.partitions=huge_app
+nora_w10.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+nora_w10.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+nora_w10.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+nora_w10.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+#nora_w10.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+#nora_w10.menu.PartitionScheme.fatflash.build.partitions=ffat
+#nora_w10.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+#nora_w10.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+#nora_w10.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+#nora_w10.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+nora_w10.menu.PartitionScheme.rainmaker=RainMaker 4MB
+nora_w10.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+nora_w10.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+nora_w10.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+nora_w10.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+nora_w10.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+nora_w10.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+nora_w10.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+nora_w10.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+nora_w10.menu.CPUFreq.240=240MHz (WiFi)
+nora_w10.menu.CPUFreq.240.build.f_cpu=240000000L
+nora_w10.menu.CPUFreq.160=160MHz (WiFi)
+nora_w10.menu.CPUFreq.160.build.f_cpu=160000000L
+nora_w10.menu.CPUFreq.80=80MHz (WiFi)
+nora_w10.menu.CPUFreq.80.build.f_cpu=80000000L
+nora_w10.menu.CPUFreq.40=40MHz
+nora_w10.menu.CPUFreq.40.build.f_cpu=40000000L
+nora_w10.menu.CPUFreq.20=20MHz
+nora_w10.menu.CPUFreq.20.build.f_cpu=20000000L
+nora_w10.menu.CPUFreq.10=10MHz
+nora_w10.menu.CPUFreq.10.build.f_cpu=10000000L
+
+nora_w10.menu.UploadSpeed.921600=921600
+nora_w10.menu.UploadSpeed.921600.upload.speed=921600
+nora_w10.menu.UploadSpeed.115200=115200
+nora_w10.menu.UploadSpeed.115200.upload.speed=115200
+nora_w10.menu.UploadSpeed.256000.windows=256000
+nora_w10.menu.UploadSpeed.256000.upload.speed=256000
+nora_w10.menu.UploadSpeed.230400.windows.upload.speed=256000
+nora_w10.menu.UploadSpeed.230400=230400
+nora_w10.menu.UploadSpeed.230400.upload.speed=230400
+nora_w10.menu.UploadSpeed.460800.linux=460800
+nora_w10.menu.UploadSpeed.460800.macosx=460800
+nora_w10.menu.UploadSpeed.460800.upload.speed=460800
+nora_w10.menu.UploadSpeed.512000.windows=512000
+nora_w10.menu.UploadSpeed.512000.upload.speed=512000
+
+nora_w10.menu.DebugLevel.none=None
+nora_w10.menu.DebugLevel.none.build.code_debug=0
+nora_w10.menu.DebugLevel.error=Error
+nora_w10.menu.DebugLevel.error.build.code_debug=1
+nora_w10.menu.DebugLevel.warn=Warn
+nora_w10.menu.DebugLevel.warn.build.code_debug=2
+nora_w10.menu.DebugLevel.info=Info
+nora_w10.menu.DebugLevel.info.build.code_debug=3
+nora_w10.menu.DebugLevel.debug=Debug
+nora_w10.menu.DebugLevel.debug.build.code_debug=4
+nora_w10.menu.DebugLevel.verbose=Verbose
+nora_w10.menu.DebugLevel.verbose.build.code_debug=5
+
+nora_w10.menu.EraseFlash.none=Disabled
+nora_w10.menu.EraseFlash.none.upload.erase_cmd=
+nora_w10.menu.EraseFlash.all=Enabled
+nora_w10.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+widora-air.name=Widora AIR
+
+widora-air.bootloader.tool=esptool_py
+widora-air.bootloader.tool.default=esptool_py
+
+widora-air.upload.tool=esptool_py
+widora-air.upload.tool.default=esptool_py
+widora-air.upload.tool.network=esp_ota
+
+widora-air.upload.maximum_size=1310720
+widora-air.upload.maximum_data_size=327680
+widora-air.upload.flags=
+widora-air.upload.extra_flags=
+
+widora-air.serial.disableDTR=true
+widora-air.serial.disableRTS=true
+
+widora-air.build.tarch=xtensa
+widora-air.build.bootloader_addr=0x1000
+widora-air.build.target=esp32
+widora-air.build.mcu=esp32
+widora-air.build.core=esp32
+widora-air.build.variant=widora-air
+widora-air.build.board=WIDORA_AIR
+
+widora-air.build.f_cpu=240000000L
+widora-air.build.flash_mode=dio
+widora-air.build.flash_size=16MB
+widora-air.build.boot=dio
+widora-air.build.partitions=default
+widora-air.build.defines=
+
+widora-air.menu.FlashFreq.80=80MHz
+widora-air.menu.FlashFreq.80.build.flash_freq=80m
+widora-air.menu.FlashFreq.40=40MHz
+widora-air.menu.FlashFreq.40.build.flash_freq=40m
+
+widora-air.menu.UploadSpeed.921600=921600
+widora-air.menu.UploadSpeed.921600.upload.speed=921600
+widora-air.menu.UploadSpeed.115200=115200
+widora-air.menu.UploadSpeed.115200.upload.speed=115200
+widora-air.menu.UploadSpeed.256000.windows=256000
+widora-air.menu.UploadSpeed.256000.upload.speed=256000
+widora-air.menu.UploadSpeed.230400.windows.upload.speed=256000
+widora-air.menu.UploadSpeed.230400=230400
+widora-air.menu.UploadSpeed.230400.upload.speed=230400
+widora-air.menu.UploadSpeed.460800.linux=460800
+widora-air.menu.UploadSpeed.460800.macosx=460800
+widora-air.menu.UploadSpeed.460800.upload.speed=460800
+widora-air.menu.UploadSpeed.512000.windows=512000
+widora-air.menu.UploadSpeed.512000.upload.speed=512000
+
+widora-air.menu.DebugLevel.none=None
+widora-air.menu.DebugLevel.none.build.code_debug=0
+widora-air.menu.DebugLevel.error=Error
+widora-air.menu.DebugLevel.error.build.code_debug=1
+widora-air.menu.DebugLevel.warn=Warn
+widora-air.menu.DebugLevel.warn.build.code_debug=2
+widora-air.menu.DebugLevel.info=Info
+widora-air.menu.DebugLevel.info.build.code_debug=3
+widora-air.menu.DebugLevel.debug=Debug
+widora-air.menu.DebugLevel.debug.build.code_debug=4
+widora-air.menu.DebugLevel.verbose=Verbose
+widora-air.menu.DebugLevel.verbose.build.code_debug=5
+
+widora-air.menu.EraseFlash.none=Disabled
+widora-air.menu.EraseFlash.none.upload.erase_cmd=
+widora-air.menu.EraseFlash.all=Enabled
+widora-air.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp320.name=Electronic SweetPeas - ESP320
+
+esp320.bootloader.tool=esptool_py
+esp320.bootloader.tool.default=esptool_py
+
+esp320.upload.tool=esptool_py
+esp320.upload.tool.default=esptool_py
+esp320.upload.tool.network=esp_ota
+
+esp320.upload.maximum_size=1310720
+esp320.upload.maximum_data_size=327680
+esp320.upload.flags=
+esp320.upload.extra_flags=
+
+esp320.serial.disableDTR=true
+esp320.serial.disableRTS=true
+
+esp320.build.tarch=xtensa
+esp320.build.bootloader_addr=0x1000
+esp320.build.target=esp32
+esp320.build.mcu=esp32
 esp320.build.core=esp32
 esp320.build.variant=esp320
 esp320.build.board=ESP320
@@ -1030,18 +9366,46 @@ esp320.menu.UploadSpeed.460800.upload.speed=460800
 esp320.menu.UploadSpeed.512000.windows=512000
 esp320.menu.UploadSpeed.512000.upload.speed=512000
 
+esp320.menu.DebugLevel.none=None
+esp320.menu.DebugLevel.none.build.code_debug=0
+esp320.menu.DebugLevel.error=Error
+esp320.menu.DebugLevel.error.build.code_debug=1
+esp320.menu.DebugLevel.warn=Warn
+esp320.menu.DebugLevel.warn.build.code_debug=2
+esp320.menu.DebugLevel.info=Info
+esp320.menu.DebugLevel.info.build.code_debug=3
+esp320.menu.DebugLevel.debug=Debug
+esp320.menu.DebugLevel.debug.build.code_debug=4
+esp320.menu.DebugLevel.verbose=Verbose
+esp320.menu.DebugLevel.verbose.build.code_debug=5
+
+esp320.menu.EraseFlash.none=Disabled
+esp320.menu.EraseFlash.none.upload.erase_cmd=
+esp320.menu.EraseFlash.all=Enabled
+esp320.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 nano32.name=Nano32
 
+nano32.bootloader.tool=esptool_py
+nano32.bootloader.tool.default=esptool_py
+
 nano32.upload.tool=esptool_py
+nano32.upload.tool.default=esptool_py
+nano32.upload.tool.network=esp_ota
+
 nano32.upload.maximum_size=1310720
 nano32.upload.maximum_data_size=327680
-nano32.upload.wait_for_upload_port=true
+nano32.upload.flags=
+nano32.upload.extra_flags=
 
 nano32.serial.disableDTR=true
 nano32.serial.disableRTS=true
 
+nano32.build.tarch=xtensa
+nano32.build.bootloader_addr=0x1000
+nano32.build.target=esp32
 nano32.build.mcu=esp32
 nano32.build.core=esp32
 nano32.build.variant=nano32
@@ -1074,18 +9438,46 @@ nano32.menu.UploadSpeed.460800.upload.speed=460800
 nano32.menu.UploadSpeed.512000.windows=512000
 nano32.menu.UploadSpeed.512000.upload.speed=512000
 
+nano32.menu.DebugLevel.none=None
+nano32.menu.DebugLevel.none.build.code_debug=0
+nano32.menu.DebugLevel.error=Error
+nano32.menu.DebugLevel.error.build.code_debug=1
+nano32.menu.DebugLevel.warn=Warn
+nano32.menu.DebugLevel.warn.build.code_debug=2
+nano32.menu.DebugLevel.info=Info
+nano32.menu.DebugLevel.info.build.code_debug=3
+nano32.menu.DebugLevel.debug=Debug
+nano32.menu.DebugLevel.debug.build.code_debug=4
+nano32.menu.DebugLevel.verbose=Verbose
+nano32.menu.DebugLevel.verbose.build.code_debug=5
+
+nano32.menu.EraseFlash.none=Disabled
+nano32.menu.EraseFlash.none.upload.erase_cmd=
+nano32.menu.EraseFlash.all=Enabled
+nano32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 d32.name=LOLIN D32
 
+d32.bootloader.tool=esptool_py
+d32.bootloader.tool.default=esptool_py
+
 d32.upload.tool=esptool_py
+d32.upload.tool.default=esptool_py
+d32.upload.tool.network=esp_ota
+
 d32.upload.maximum_size=1310720
 d32.upload.maximum_data_size=327680
-d32.upload.wait_for_upload_port=true
+d32.upload.flags=
+d32.upload.extra_flags=
 
 d32.serial.disableDTR=true
 d32.serial.disableRTS=true
 
+d32.build.tarch=xtensa
+d32.build.bootloader_addr=0x1000
+d32.build.target=esp32
 d32.build.mcu=esp32
 d32.build.core=esp32
 d32.build.variant=d32
@@ -1110,15 +9502,11 @@ d32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
 d32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 d32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
 
-
-
 d32.menu.FlashFreq.80=80MHz
 d32.menu.FlashFreq.80.build.flash_freq=80m
 d32.menu.FlashFreq.40=40MHz
 d32.menu.FlashFreq.40.build.flash_freq=40m
 
-
-
 d32.menu.UploadSpeed.921600=921600
 d32.menu.UploadSpeed.921600.upload.speed=921600
 d32.menu.UploadSpeed.115200=115200
@@ -1147,18 +9535,33 @@ d32.menu.DebugLevel.debug.build.code_debug=4
 d32.menu.DebugLevel.verbose=Verbose
 d32.menu.DebugLevel.verbose.build.code_debug=5
 
+d32.menu.EraseFlash.none=Disabled
+d32.menu.EraseFlash.none.upload.erase_cmd=
+d32.menu.EraseFlash.all=Enabled
+d32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 d32_pro.name=LOLIN D32 PRO
 
+d32_pro.bootloader.tool=esptool_py
+d32_pro.bootloader.tool.default=esptool_py
+
 d32_pro.upload.tool=esptool_py
+d32_pro.upload.tool.default=esptool_py
+d32_pro.upload.tool.network=esp_ota
+
 d32_pro.upload.maximum_size=1310720
 d32_pro.upload.maximum_data_size=327680
-d32_pro.upload.wait_for_upload_port=true
+d32_pro.upload.flags=
+d32_pro.upload.extra_flags=
 
 d32_pro.serial.disableDTR=true
 d32_pro.serial.disableRTS=true
 
+d32_pro.build.tarch=xtensa
+d32_pro.build.bootloader_addr=0x1000
+d32_pro.build.target=esp32
 d32_pro.build.mcu=esp32
 d32_pro.build.core=esp32
 d32_pro.build.variant=d32_pro
@@ -1174,8 +9577,10 @@ d32_pro.build.defines=
 
 d32_pro.menu.PSRAM.disabled=Disabled
 d32_pro.menu.PSRAM.disabled.build.defines=
+d32_pro.menu.PSRAM.disabled.build.extra_libs=
 d32_pro.menu.PSRAM.enabled=Enabled
-d32_pro.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+d32_pro.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+d32_pro.menu.PSRAM.enabled.build.extra_libs=
 
 d32_pro.menu.PartitionScheme.default=Default
 d32_pro.menu.PartitionScheme.default.build.partitions=default
@@ -1188,15 +9593,11 @@ d32_pro.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
 d32_pro.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 d32_pro.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
 
-
-
 d32_pro.menu.FlashFreq.80=80MHz
 d32_pro.menu.FlashFreq.80.build.flash_freq=80m
 d32_pro.menu.FlashFreq.40=40MHz
 d32_pro.menu.FlashFreq.40.build.flash_freq=40m
 
-
-
 d32_pro.menu.UploadSpeed.921600=921600
 d32_pro.menu.UploadSpeed.921600.upload.speed=921600
 d32_pro.menu.UploadSpeed.115200=115200
@@ -1211,6 +9612,8 @@ d32_pro.menu.UploadSpeed.460800.macosx=460800
 d32_pro.menu.UploadSpeed.460800.upload.speed=460800
 d32_pro.menu.UploadSpeed.512000.windows=512000
 d32_pro.menu.UploadSpeed.512000.upload.speed=512000
+d32_pro.menu.UploadSpeed.1500000=1500000
+d32_pro.menu.UploadSpeed.1500000.upload.speed=1500000
 
 d32_pro.menu.DebugLevel.none=None
 d32_pro.menu.DebugLevel.none.build.code_debug=0
@@ -1225,18 +9628,1112 @@ d32_pro.menu.DebugLevel.debug.build.code_debug=4
 d32_pro.menu.DebugLevel.verbose=Verbose
 d32_pro.menu.DebugLevel.verbose.build.code_debug=5
 
+d32_pro.menu.EraseFlash.none=Disabled
+d32_pro.menu.EraseFlash.none.upload.erase_cmd=
+d32_pro.menu.EraseFlash.all=Enabled
+d32_pro.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lolin_c3_mini.name=LOLIN C3 Mini
+
+lolin_c3_mini.bootloader.tool=esptool_py
+lolin_c3_mini.bootloader.tool.default=esptool_py
+
+lolin_c3_mini.upload.tool=esptool_py
+lolin_c3_mini.upload.tool.default=esptool_py
+lolin_c3_mini.upload.tool.network=esp_ota
+
+lolin_c3_mini.upload.maximum_size=1310720
+lolin_c3_mini.upload.maximum_data_size=327680
+lolin_c3_mini.upload.flags=
+lolin_c3_mini.upload.extra_flags=
+lolin_c3_mini.upload.use_1200bps_touch=false
+lolin_c3_mini.upload.wait_for_upload_port=false
+
+lolin_c3_mini.serial.disableDTR=true
+lolin_c3_mini.serial.disableRTS=true
+
+lolin_c3_mini.build.tarch=riscv32
+lolin_c3_mini.build.target=esp
+lolin_c3_mini.build.mcu=esp32c3
+lolin_c3_mini.build.core=esp32
+lolin_c3_mini.build.variant=lolin_c3_mini
+lolin_c3_mini.build.board=LOLIN_C3_MINI
+lolin_c3_mini.build.bootloader_addr=0x0
+
+lolin_c3_mini.build.cdc_on_boot=1
+lolin_c3_mini.build.f_cpu=160000000L
+lolin_c3_mini.build.flash_size=4MB
+lolin_c3_mini.build.flash_freq=80m
+lolin_c3_mini.build.flash_mode=dio
+lolin_c3_mini.build.boot=qio
+lolin_c3_mini.build.partitions=default
+lolin_c3_mini.build.defines=
+
+lolin_c3_mini.menu.CDCOnBoot.default=Enabled
+lolin_c3_mini.menu.CDCOnBoot.default.build.cdc_on_boot=1
+lolin_c3_mini.menu.CDCOnBoot.dis_cdc=Disabled
+lolin_c3_mini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+lolin_c3_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lolin_c3_mini.menu.PartitionScheme.default.build.partitions=default
+lolin_c3_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lolin_c3_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lolin_c3_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lolin_c3_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lolin_c3_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lolin_c3_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lolin_c3_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lolin_c3_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lolin_c3_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lolin_c3_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lolin_c3_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lolin_c3_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lolin_c3_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lolin_c3_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lolin_c3_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lolin_c3_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lolin_c3_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+
+lolin_c3_mini.menu.CPUFreq.160=160MHz (WiFi)
+lolin_c3_mini.menu.CPUFreq.160.build.f_cpu=160000000L
+lolin_c3_mini.menu.CPUFreq.80=80MHz (WiFi)
+lolin_c3_mini.menu.CPUFreq.80.build.f_cpu=80000000L
+lolin_c3_mini.menu.CPUFreq.40=40MHz
+lolin_c3_mini.menu.CPUFreq.40.build.f_cpu=40000000L
+lolin_c3_mini.menu.CPUFreq.20=20MHz
+lolin_c3_mini.menu.CPUFreq.20.build.f_cpu=20000000L
+lolin_c3_mini.menu.CPUFreq.10=10MHz
+lolin_c3_mini.menu.CPUFreq.10.build.f_cpu=10000000L
+
+
+
+lolin_c3_mini.menu.FlashFreq.80=80MHz
+lolin_c3_mini.menu.FlashFreq.80.build.flash_freq=80m
+lolin_c3_mini.menu.FlashFreq.40=40MHz
+lolin_c3_mini.menu.FlashFreq.40.build.flash_freq=40m
+
+lolin_c3_mini.menu.UploadSpeed.921600=921600
+lolin_c3_mini.menu.UploadSpeed.921600.upload.speed=921600
+lolin_c3_mini.menu.UploadSpeed.115200=115200
+lolin_c3_mini.menu.UploadSpeed.115200.upload.speed=115200
+lolin_c3_mini.menu.UploadSpeed.256000.windows=256000
+lolin_c3_mini.menu.UploadSpeed.256000.upload.speed=256000
+lolin_c3_mini.menu.UploadSpeed.230400.windows.upload.speed=256000
+lolin_c3_mini.menu.UploadSpeed.230400=230400
+lolin_c3_mini.menu.UploadSpeed.230400.upload.speed=230400
+lolin_c3_mini.menu.UploadSpeed.460800.linux=460800
+lolin_c3_mini.menu.UploadSpeed.460800.macosx=460800
+lolin_c3_mini.menu.UploadSpeed.460800.upload.speed=460800
+lolin_c3_mini.menu.UploadSpeed.512000.windows=512000
+lolin_c3_mini.menu.UploadSpeed.512000.upload.speed=512000
+
+lolin_c3_mini.menu.DebugLevel.none=None
+lolin_c3_mini.menu.DebugLevel.none.build.code_debug=0
+lolin_c3_mini.menu.DebugLevel.error=Error
+lolin_c3_mini.menu.DebugLevel.error.build.code_debug=1
+lolin_c3_mini.menu.DebugLevel.warn=Warn
+lolin_c3_mini.menu.DebugLevel.warn.build.code_debug=2
+lolin_c3_mini.menu.DebugLevel.info=Info
+lolin_c3_mini.menu.DebugLevel.info.build.code_debug=3
+lolin_c3_mini.menu.DebugLevel.debug=Debug
+lolin_c3_mini.menu.DebugLevel.debug.build.code_debug=4
+lolin_c3_mini.menu.DebugLevel.verbose=Verbose
+lolin_c3_mini.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin_c3_mini.menu.EraseFlash.none=Disabled
+lolin_c3_mini.menu.EraseFlash.none.upload.erase_cmd=
+lolin_c3_mini.menu.EraseFlash.all=Enabled
+lolin_c3_mini.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lolin_c3_pico.name=LOLIN C3 Pico
+
+lolin_c3_pico.bootloader.tool=esptool_py
+lolin_c3_pico.bootloader.tool.default=esptool_py
+
+lolin_c3_pico.upload.tool=esptool_py
+lolin_c3_pico.upload.tool.default=esptool_py
+lolin_c3_pico.upload.tool.network=esp_ota
+
+lolin_c3_pico.upload.maximum_size=1310720
+lolin_c3_pico.upload.maximum_data_size=327680
+lolin_c3_pico.upload.flags=
+lolin_c3_pico.upload.extra_flags=
+lolin_c3_pico.upload.use_1200bps_touch=false
+lolin_c3_pico.upload.wait_for_upload_port=false
+
+lolin_c3_pico.serial.disableDTR=true
+lolin_c3_pico.serial.disableRTS=true
+
+lolin_c3_pico.build.tarch=riscv32
+lolin_c3_pico.build.target=esp
+lolin_c3_pico.build.mcu=esp32c3
+lolin_c3_pico.build.core=esp32
+lolin_c3_pico.build.variant=lolin_c3_pico
+lolin_c3_pico.build.board=LOLIN_C3_PICO
+lolin_c3_pico.build.bootloader_addr=0x0
+
+lolin_c3_pico.build.cdc_on_boot=1
+lolin_c3_pico.build.f_cpu=160000000L
+lolin_c3_pico.build.flash_size=4MB
+lolin_c3_pico.build.flash_freq=80m
+lolin_c3_pico.build.flash_mode=dio
+lolin_c3_pico.build.boot=qio
+lolin_c3_pico.build.partitions=default
+lolin_c3_pico.build.defines=
+
+lolin_c3_pico.menu.CDCOnBoot.default=Enabled
+lolin_c3_pico.menu.CDCOnBoot.default.build.cdc_on_boot=1
+lolin_c3_pico.menu.CDCOnBoot.dis_cdc=Disabled
+lolin_c3_pico.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+lolin_c3_pico.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lolin_c3_pico.menu.PartitionScheme.default.build.partitions=default
+lolin_c3_pico.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lolin_c3_pico.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lolin_c3_pico.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lolin_c3_pico.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lolin_c3_pico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lolin_c3_pico.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lolin_c3_pico.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lolin_c3_pico.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lolin_c3_pico.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lolin_c3_pico.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lolin_c3_pico.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lolin_c3_pico.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lolin_c3_pico.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lolin_c3_pico.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lolin_c3_pico.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lolin_c3_pico.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lolin_c3_pico.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+lolin_c3_pico.menu.CPUFreq.160=160MHz (WiFi)
+lolin_c3_pico.menu.CPUFreq.160.build.f_cpu=160000000L
+lolin_c3_pico.menu.CPUFreq.80=80MHz (WiFi)
+lolin_c3_pico.menu.CPUFreq.80.build.f_cpu=80000000L
+lolin_c3_pico.menu.CPUFreq.40=40MHz
+lolin_c3_pico.menu.CPUFreq.40.build.f_cpu=40000000L
+lolin_c3_pico.menu.CPUFreq.20=20MHz
+lolin_c3_pico.menu.CPUFreq.20.build.f_cpu=20000000L
+lolin_c3_pico.menu.CPUFreq.10=10MHz
+lolin_c3_pico.menu.CPUFreq.10.build.f_cpu=10000000L
+
+lolin_c3_pico.menu.FlashFreq.80=80MHz
+lolin_c3_pico.menu.FlashFreq.80.build.flash_freq=80m
+lolin_c3_pico.menu.FlashFreq.40=40MHz
+lolin_c3_pico.menu.FlashFreq.40.build.flash_freq=40m
+
+lolin_c3_pico.menu.UploadSpeed.921600=921600
+lolin_c3_pico.menu.UploadSpeed.921600.upload.speed=921600
+lolin_c3_pico.menu.UploadSpeed.115200=115200
+lolin_c3_pico.menu.UploadSpeed.115200.upload.speed=115200
+lolin_c3_pico.menu.UploadSpeed.256000.windows=256000
+lolin_c3_pico.menu.UploadSpeed.256000.upload.speed=256000
+lolin_c3_pico.menu.UploadSpeed.230400.windows.upload.speed=256000
+lolin_c3_pico.menu.UploadSpeed.230400=230400
+lolin_c3_pico.menu.UploadSpeed.230400.upload.speed=230400
+lolin_c3_pico.menu.UploadSpeed.460800.linux=460800
+lolin_c3_pico.menu.UploadSpeed.460800.macosx=460800
+lolin_c3_pico.menu.UploadSpeed.460800.upload.speed=460800
+lolin_c3_pico.menu.UploadSpeed.512000.windows=512000
+lolin_c3_pico.menu.UploadSpeed.512000.upload.speed=512000
+
+lolin_c3_pico.menu.DebugLevel.none=None
+lolin_c3_pico.menu.DebugLevel.none.build.code_debug=0
+lolin_c3_pico.menu.DebugLevel.error=Error
+lolin_c3_pico.menu.DebugLevel.error.build.code_debug=1
+lolin_c3_pico.menu.DebugLevel.warn=Warn
+lolin_c3_pico.menu.DebugLevel.warn.build.code_debug=2
+lolin_c3_pico.menu.DebugLevel.info=Info
+lolin_c3_pico.menu.DebugLevel.info.build.code_debug=3
+lolin_c3_pico.menu.DebugLevel.debug=Debug
+lolin_c3_pico.menu.DebugLevel.debug.build.code_debug=4
+lolin_c3_pico.menu.DebugLevel.verbose=Verbose
+lolin_c3_pico.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin_c3_pico.menu.EraseFlash.none=Disabled
+lolin_c3_pico.menu.EraseFlash.none.upload.erase_cmd=
+lolin_c3_pico.menu.EraseFlash.all=Enabled
+lolin_c3_pico.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lolin_s2_mini.name=LOLIN S2 Mini
+lolin_s2_mini.vid.0=0x303a
+lolin_s2_mini.pid.0=0x80C2
+
+lolin_s2_mini.bootloader.tool=esptool_py
+lolin_s2_mini.bootloader.tool.default=esptool_py
+
+lolin_s2_mini.upload.tool=esptool_py
+lolin_s2_mini.upload.tool.default=esptool_py
+lolin_s2_mini.upload.tool.network=esp_ota
+
+lolin_s2_mini.upload.maximum_size=1310720
+lolin_s2_mini.upload.maximum_data_size=327680
+lolin_s2_mini.upload.flags=
+lolin_s2_mini.upload.extra_flags=
+lolin_s2_mini.upload.use_1200bps_touch=true
+lolin_s2_mini.upload.wait_for_upload_port=true
+lolin_s2_mini.upload.speed=921600
+
+lolin_s2_mini.serial.disableDTR=false
+lolin_s2_mini.serial.disableRTS=false
+
+lolin_s2_mini.build.tarch=xtensa
+lolin_s2_mini.build.bootloader_addr=0x1000
+lolin_s2_mini.build.target=esp32s2
+lolin_s2_mini.build.mcu=esp32s2
+lolin_s2_mini.build.core=esp32
+lolin_s2_mini.build.variant=lolin_s2_mini
+lolin_s2_mini.build.board=LOLIN_S2_MINI
+
+lolin_s2_mini.build.cdc_on_boot=1
+lolin_s2_mini.build.msc_on_boot=1
+lolin_s2_mini.build.dfu_on_boot=1
+lolin_s2_mini.build.f_cpu=240000000L
+lolin_s2_mini.build.flash_size=4MB
+lolin_s2_mini.build.flash_freq=80m
+lolin_s2_mini.build.flash_mode=dio
+lolin_s2_mini.build.boot=qio
+lolin_s2_mini.build.partitions=default
+lolin_s2_mini.build.defines=
+
+lolin_s2_mini.build.defines=-DBOARD_HAS_PSRAM
+
+lolin_s2_mini.menu.CDCOnBoot.default=Enabled
+lolin_s2_mini.menu.CDCOnBoot.default.build.cdc_on_boot=1
+lolin_s2_mini.menu.CDCOnBoot.dis_cdc=Disabled
+lolin_s2_mini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+lolin_s2_mini.menu.MSCOnBoot.default=Disabled
+lolin_s2_mini.menu.MSCOnBoot.default.build.msc_on_boot=0
+lolin_s2_mini.menu.MSCOnBoot.msc=Enabled
+lolin_s2_mini.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lolin_s2_mini.menu.DFUOnBoot.default=Disabled
+lolin_s2_mini.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lolin_s2_mini.menu.DFUOnBoot.dfu=Enabled
+lolin_s2_mini.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lolin_s2_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lolin_s2_mini.menu.PartitionScheme.default.build.partitions=default
+lolin_s2_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lolin_s2_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lolin_s2_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lolin_s2_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lolin_s2_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lolin_s2_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lolin_s2_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lolin_s2_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lolin_s2_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lolin_s2_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lolin_s2_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lolin_s2_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lolin_s2_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lolin_s2_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lolin_s2_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lolin_s2_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lolin_s2_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+lolin_s2_mini.menu.DebugLevel.none=None
+lolin_s2_mini.menu.DebugLevel.none.build.code_debug=0
+lolin_s2_mini.menu.DebugLevel.error=Error
+lolin_s2_mini.menu.DebugLevel.error.build.code_debug=1
+lolin_s2_mini.menu.DebugLevel.warn=Warn
+lolin_s2_mini.menu.DebugLevel.warn.build.code_debug=2
+lolin_s2_mini.menu.DebugLevel.info=Info
+lolin_s2_mini.menu.DebugLevel.info.build.code_debug=3
+lolin_s2_mini.menu.DebugLevel.debug=Debug
+lolin_s2_mini.menu.DebugLevel.debug.build.code_debug=4
+lolin_s2_mini.menu.DebugLevel.verbose=Verbose
+lolin_s2_mini.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin_s2_mini.menu.EraseFlash.none=Disabled
+lolin_s2_mini.menu.EraseFlash.none.upload.erase_cmd=
+lolin_s2_mini.menu.EraseFlash.all=Enabled
+lolin_s2_mini.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lolin_s2_pico.name=LOLIN S2 PICO
+lolin_s2_pico.vid.0=0x303a
+lolin_s2_pico.pid.0=0x80C5
+
+lolin_s2_pico.bootloader.tool=esptool_py
+lolin_s2_pico.bootloader.tool.default=esptool_py
+
+lolin_s2_pico.upload.tool=esptool_py
+lolin_s2_pico.upload.tool.default=esptool_py
+lolin_s2_pico.upload.tool.network=esp_ota
+
+lolin_s2_pico.upload.maximum_size=1310720
+lolin_s2_pico.upload.maximum_data_size=327680
+lolin_s2_pico.upload.flags=
+lolin_s2_pico.upload.extra_flags=
+lolin_s2_pico.upload.use_1200bps_touch=true
+lolin_s2_pico.upload.wait_for_upload_port=true
+lolin_s2_pico.upload.speed=921600
+
+lolin_s2_pico.serial.disableDTR=false
+lolin_s2_pico.serial.disableRTS=false
+
+lolin_s2_pico.build.tarch=xtensa
+lolin_s2_pico.build.bootloader_addr=0x1000
+lolin_s2_pico.build.target=esp32s2
+lolin_s2_pico.build.mcu=esp32s2
+lolin_s2_pico.build.core=esp32
+lolin_s2_pico.build.variant=lolin_s2_pico
+lolin_s2_pico.build.board=LOLIN_S2_PICO
+
+lolin_s2_pico.build.cdc_on_boot=1
+lolin_s2_pico.build.msc_on_boot=1
+lolin_s2_pico.build.dfu_on_boot=1
+lolin_s2_pico.build.f_cpu=240000000L
+lolin_s2_pico.build.flash_size=4MB
+lolin_s2_pico.build.flash_freq=80m
+lolin_s2_pico.build.flash_mode=dio
+lolin_s2_pico.build.boot=qio
+lolin_s2_pico.build.partitions=default
+lolin_s2_pico.build.defines=
+
+lolin_s2_pico.build.defines=-DBOARD_HAS_PSRAM
+
+lolin_s2_pico.menu.CDCOnBoot.default=Enabled
+lolin_s2_pico.menu.CDCOnBoot.default.build.cdc_on_boot=1
+lolin_s2_pico.menu.CDCOnBoot.dis_cdc=Disabled
+lolin_s2_pico.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+lolin_s2_pico.menu.MSCOnBoot.default=Disabled
+lolin_s2_pico.menu.MSCOnBoot.default.build.msc_on_boot=0
+lolin_s2_pico.menu.MSCOnBoot.msc=Enabled
+lolin_s2_pico.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lolin_s2_pico.menu.DFUOnBoot.default=Disabled
+lolin_s2_pico.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lolin_s2_pico.menu.DFUOnBoot.dfu=Enabled
+lolin_s2_pico.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lolin_s2_pico.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lolin_s2_pico.menu.PartitionScheme.default.build.partitions=default
+lolin_s2_pico.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lolin_s2_pico.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lolin_s2_pico.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lolin_s2_pico.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lolin_s2_pico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lolin_s2_pico.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lolin_s2_pico.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lolin_s2_pico.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lolin_s2_pico.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lolin_s2_pico.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lolin_s2_pico.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lolin_s2_pico.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lolin_s2_pico.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lolin_s2_pico.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lolin_s2_pico.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lolin_s2_pico.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lolin_s2_pico.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+lolin_s2_pico.menu.DebugLevel.none=None
+lolin_s2_pico.menu.DebugLevel.none.build.code_debug=0
+lolin_s2_pico.menu.DebugLevel.error=Error
+lolin_s2_pico.menu.DebugLevel.error.build.code_debug=1
+lolin_s2_pico.menu.DebugLevel.warn=Warn
+lolin_s2_pico.menu.DebugLevel.warn.build.code_debug=2
+lolin_s2_pico.menu.DebugLevel.info=Info
+lolin_s2_pico.menu.DebugLevel.info.build.code_debug=3
+lolin_s2_pico.menu.DebugLevel.debug=Debug
+lolin_s2_pico.menu.DebugLevel.debug.build.code_debug=4
+lolin_s2_pico.menu.DebugLevel.verbose=Verbose
+lolin_s2_pico.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin_s2_pico.menu.EraseFlash.none=Disabled
+lolin_s2_pico.menu.EraseFlash.none.upload.erase_cmd=
+lolin_s2_pico.menu.EraseFlash.all=Enabled
+lolin_s2_pico.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lolin_s3.name=LOLIN S3
+
+lolin_s3.bootloader.tool=esptool_py
+lolin_s3.bootloader.tool.default=esptool_py
+
+lolin_s3.upload.tool=esptool_py
+lolin_s3.upload.tool.default=esptool_py
+lolin_s3.upload.tool.network=esp_ota
+
+lolin_s3.upload.maximum_size=1310720
+lolin_s3.upload.maximum_data_size=327680
+lolin_s3.upload.flags=
+lolin_s3.upload.extra_flags=
+lolin_s3.upload.use_1200bps_touch=false
+lolin_s3.upload.wait_for_upload_port=false
+
+lolin_s3.serial.disableDTR=false
+lolin_s3.serial.disableRTS=false
+
+lolin_s3.build.tarch=xtensa
+lolin_s3.build.bootloader_addr=0x0
+lolin_s3.build.target=esp32s3
+lolin_s3.build.mcu=esp32s3
+lolin_s3.build.core=esp32
+lolin_s3.build.variant=lolin_s3
+lolin_s3.build.board=LOLIN_S3
+
+lolin_s3.build.usb_mode=1
+lolin_s3.build.cdc_on_boot=0
+lolin_s3.build.msc_on_boot=0
+lolin_s3.build.dfu_on_boot=0
+lolin_s3.build.f_cpu=240000000L
+lolin_s3.build.flash_size=16MB
+lolin_s3.build.flash_freq=80m
+lolin_s3.build.flash_mode=dio
+lolin_s3.build.boot=qio
+lolin_s3.build.boot_freq=80m
+lolin_s3.build.partitions=default
+lolin_s3.build.defines=-DBOARD_HAS_PSRAM
+lolin_s3.build.loop_core=
+lolin_s3.build.event_core=
+lolin_s3.build.psram_type=opi
+lolin_s3.build.memory_type={build.boot}_{build.psram_type}
+
+lolin_s3.menu.FlashMode.qio=QIO 80MHz
+lolin_s3.menu.FlashMode.qio.build.flash_mode=dio
+lolin_s3.menu.FlashMode.qio.build.boot=qio
+lolin_s3.menu.FlashMode.qio.build.boot_freq=80m
+lolin_s3.menu.FlashMode.qio.build.flash_freq=80m
+lolin_s3.menu.FlashMode.qio120=QIO 120MHz
+lolin_s3.menu.FlashMode.qio120.build.flash_mode=dio
+lolin_s3.menu.FlashMode.qio120.build.boot=qio
+lolin_s3.menu.FlashMode.qio120.build.boot_freq=120m
+lolin_s3.menu.FlashMode.qio120.build.flash_freq=80m
+
+lolin_s3.menu.LoopCore.1=Core 1
+lolin_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lolin_s3.menu.LoopCore.0=Core 0
+lolin_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lolin_s3.menu.EventsCore.1=Core 1
+lolin_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lolin_s3.menu.EventsCore.0=Core 0
+lolin_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lolin_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+lolin_s3.menu.USBMode.hwcdc.build.usb_mode=1
+lolin_s3.menu.USBMode.default=USB-OTG (TinyUSB)
+lolin_s3.menu.USBMode.default.build.usb_mode=0
+
+lolin_s3.menu.CDCOnBoot.default=Disabled
+lolin_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+lolin_s3.menu.CDCOnBoot.cdc=Enabled
+lolin_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+lolin_s3.menu.MSCOnBoot.default=Disabled
+lolin_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+lolin_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+lolin_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lolin_s3.menu.DFUOnBoot.default=Disabled
+lolin_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lolin_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+lolin_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lolin_s3.menu.UploadMode.default=UART0 / Hardware CDC
+lolin_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+lolin_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+lolin_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+lolin_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+lolin_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+lolin_s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+lolin_s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+lolin_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+lolin_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+lolin_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+lolin_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+lolin_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+lolin_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+lolin_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+lolin_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+lolin_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+lolin_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+lolin_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+lolin_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+lolin_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+lolin_s3.menu.CPUFreq.240=240MHz (WiFi)
+lolin_s3.menu.CPUFreq.240.build.f_cpu=240000000L
+lolin_s3.menu.CPUFreq.160=160MHz (WiFi)
+lolin_s3.menu.CPUFreq.160.build.f_cpu=160000000L
+lolin_s3.menu.CPUFreq.80=80MHz (WiFi)
+lolin_s3.menu.CPUFreq.80.build.f_cpu=80000000L
+lolin_s3.menu.CPUFreq.40=40MHz
+lolin_s3.menu.CPUFreq.40.build.f_cpu=40000000L
+lolin_s3.menu.CPUFreq.20=20MHz
+lolin_s3.menu.CPUFreq.20.build.f_cpu=20000000L
+lolin_s3.menu.CPUFreq.10=10MHz
+lolin_s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+lolin_s3.menu.UploadSpeed.921600=921600
+lolin_s3.menu.UploadSpeed.921600.upload.speed=921600
+lolin_s3.menu.UploadSpeed.115200=115200
+lolin_s3.menu.UploadSpeed.115200.upload.speed=115200
+lolin_s3.menu.UploadSpeed.256000.windows=256000
+lolin_s3.menu.UploadSpeed.256000.upload.speed=256000
+lolin_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+lolin_s3.menu.UploadSpeed.230400=230400
+lolin_s3.menu.UploadSpeed.230400.upload.speed=230400
+lolin_s3.menu.UploadSpeed.460800.linux=460800
+lolin_s3.menu.UploadSpeed.460800.macosx=460800
+lolin_s3.menu.UploadSpeed.460800.upload.speed=460800
+lolin_s3.menu.UploadSpeed.512000.windows=512000
+lolin_s3.menu.UploadSpeed.512000.upload.speed=512000
+
+lolin_s3.menu.DebugLevel.none=None
+lolin_s3.menu.DebugLevel.none.build.code_debug=0
+lolin_s3.menu.DebugLevel.error=Error
+lolin_s3.menu.DebugLevel.error.build.code_debug=1
+lolin_s3.menu.DebugLevel.warn=Warn
+lolin_s3.menu.DebugLevel.warn.build.code_debug=2
+lolin_s3.menu.DebugLevel.info=Info
+lolin_s3.menu.DebugLevel.info.build.code_debug=3
+lolin_s3.menu.DebugLevel.debug=Debug
+lolin_s3.menu.DebugLevel.debug.build.code_debug=4
+lolin_s3.menu.DebugLevel.verbose=Verbose
+lolin_s3.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin_s3.menu.EraseFlash.none=Disabled
+lolin_s3.menu.EraseFlash.none.upload.erase_cmd=
+lolin_s3.menu.EraseFlash.all=Enabled
+lolin_s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lolin_s3_mini.name=LOLIN S3 Mini
+lolin_s3_mini.vid.0=0x303a
+lolin_s3_mini.pid.0=0x8167
+
+lolin_s3_mini.bootloader.tool=esptool_py
+lolin_s3_mini.bootloader.tool.default=esptool_py
+
+lolin_s3_mini.upload.tool=esptool_py
+lolin_s3_mini.upload.tool.default=esptool_py
+lolin_s3_mini.upload.tool.network=esp_ota
+
+lolin_s3_mini.upload.maximum_size=1310720
+lolin_s3_mini.upload.maximum_data_size=327680
+lolin_s3_mini.upload.flags=
+lolin_s3_mini.upload.extra_flags=
+lolin_s3_mini.upload.use_1200bps_touch=false
+lolin_s3_mini.upload.wait_for_upload_port=false
+
+lolin_s3_mini.serial.disableDTR=false
+lolin_s3_mini.serial.disableRTS=false
+
+lolin_s3_mini.build.tarch=xtensa
+lolin_s3_mini.build.bootloader_addr=0x0
+lolin_s3_mini.build.target=esp32s3
+lolin_s3_mini.build.mcu=esp32s3
+lolin_s3_mini.build.core=esp32
+lolin_s3_mini.build.variant=lolin_s3_mini
+lolin_s3_mini.build.board=LOLIN_S3_MINI
+
+lolin_s3_mini.build.usb_mode=1
+lolin_s3_mini.build.cdc_on_boot=0
+lolin_s3_mini.build.msc_on_boot=0
+lolin_s3_mini.build.dfu_on_boot=0
+lolin_s3_mini.build.f_cpu=240000000L
+lolin_s3_mini.build.flash_size=4MB
+lolin_s3_mini.build.flash_freq=80m
+lolin_s3_mini.build.flash_mode=dio
+lolin_s3_mini.build.boot=qio
+lolin_s3_mini.build.boot_freq=80m
+lolin_s3_mini.build.partitions=default
+lolin_s3_mini.build.defines=-DBOARD_HAS_PSRAM
+lolin_s3_mini.build.loop_core=
+lolin_s3_mini.build.event_core=
+lolin_s3_mini.build.psram_type=qspi
+lolin_s3_mini.build.memory_type={build.boot}_{build.psram_type}
+
+lolin_s3_mini.menu.FlashMode.qio=QIO 80MHz
+lolin_s3_mini.menu.FlashMode.qio.build.flash_mode=dio
+lolin_s3_mini.menu.FlashMode.qio.build.boot=qio
+lolin_s3_mini.menu.FlashMode.qio.build.boot_freq=80m
+lolin_s3_mini.menu.FlashMode.qio.build.flash_freq=80m
+lolin_s3_mini.menu.FlashMode.qio120=QIO 120MHz
+lolin_s3_mini.menu.FlashMode.qio120.build.flash_mode=dio
+lolin_s3_mini.menu.FlashMode.qio120.build.boot=qio
+lolin_s3_mini.menu.FlashMode.qio120.build.boot_freq=120m
+lolin_s3_mini.menu.FlashMode.qio120.build.flash_freq=80m
+
+lolin_s3_mini.menu.LoopCore.1=Core 1
+lolin_s3_mini.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lolin_s3_mini.menu.LoopCore.0=Core 0
+lolin_s3_mini.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lolin_s3_mini.menu.EventsCore.1=Core 1
+lolin_s3_mini.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lolin_s3_mini.menu.EventsCore.0=Core 0
+lolin_s3_mini.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lolin_s3_mini.menu.USBMode.hwcdc=Hardware CDC and JTAG
+lolin_s3_mini.menu.USBMode.hwcdc.build.usb_mode=1
+lolin_s3_mini.menu.USBMode.default=USB-OTG (TinyUSB)
+lolin_s3_mini.menu.USBMode.default.build.usb_mode=0
+
+lolin_s3_mini.menu.CDCOnBoot.default=Disabled
+lolin_s3_mini.menu.CDCOnBoot.default.build.cdc_on_boot=0
+lolin_s3_mini.menu.CDCOnBoot.cdc=Enabled
+lolin_s3_mini.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+lolin_s3_mini.menu.MSCOnBoot.default=Disabled
+lolin_s3_mini.menu.MSCOnBoot.default.build.msc_on_boot=0
+lolin_s3_mini.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+lolin_s3_mini.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lolin_s3_mini.menu.DFUOnBoot.default=Disabled
+lolin_s3_mini.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lolin_s3_mini.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+lolin_s3_mini.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lolin_s3_mini.menu.UploadMode.default=UART0 / Hardware CDC
+lolin_s3_mini.menu.UploadMode.default.upload.use_1200bps_touch=false
+lolin_s3_mini.menu.UploadMode.default.upload.wait_for_upload_port=false
+lolin_s3_mini.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+lolin_s3_mini.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+lolin_s3_mini.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+lolin_s3_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lolin_s3_mini.menu.PartitionScheme.default.build.partitions=default
+lolin_s3_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lolin_s3_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lolin_s3_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lolin_s3_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lolin_s3_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lolin_s3_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lolin_s3_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lolin_s3_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lolin_s3_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lolin_s3_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lolin_s3_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lolin_s3_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lolin_s3_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lolin_s3_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lolin_s3_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lolin_s3_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lolin_s3_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+lolin_s3_mini.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+lolin_s3_mini.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+lolin_s3_mini.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+lolin_s3_mini.menu.PartitionScheme.rainmaker=RainMaker 4MB
+lolin_s3_mini.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+lolin_s3_mini.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+lolin_s3_mini.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+lolin_s3_mini.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+lolin_s3_mini.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+lolin_s3_mini.menu.CPUFreq.240=240MHz (WiFi)
+lolin_s3_mini.menu.CPUFreq.240.build.f_cpu=240000000L
+lolin_s3_mini.menu.CPUFreq.160=160MHz (WiFi)
+lolin_s3_mini.menu.CPUFreq.160.build.f_cpu=160000000L
+lolin_s3_mini.menu.CPUFreq.80=80MHz (WiFi)
+lolin_s3_mini.menu.CPUFreq.80.build.f_cpu=80000000L
+lolin_s3_mini.menu.CPUFreq.40=40MHz
+lolin_s3_mini.menu.CPUFreq.40.build.f_cpu=40000000L
+lolin_s3_mini.menu.CPUFreq.20=20MHz
+lolin_s3_mini.menu.CPUFreq.20.build.f_cpu=20000000L
+lolin_s3_mini.menu.CPUFreq.10=10MHz
+lolin_s3_mini.menu.CPUFreq.10.build.f_cpu=10000000L
+
+lolin_s3_mini.menu.UploadSpeed.921600=921600
+lolin_s3_mini.menu.UploadSpeed.921600.upload.speed=921600
+lolin_s3_mini.menu.UploadSpeed.115200=115200
+lolin_s3_mini.menu.UploadSpeed.115200.upload.speed=115200
+lolin_s3_mini.menu.UploadSpeed.256000.windows=256000
+lolin_s3_mini.menu.UploadSpeed.256000.upload.speed=256000
+lolin_s3_mini.menu.UploadSpeed.230400.windows.upload.speed=256000
+lolin_s3_mini.menu.UploadSpeed.230400=230400
+lolin_s3_mini.menu.UploadSpeed.230400.upload.speed=230400
+lolin_s3_mini.menu.UploadSpeed.460800.linux=460800
+lolin_s3_mini.menu.UploadSpeed.460800.macosx=460800
+lolin_s3_mini.menu.UploadSpeed.460800.upload.speed=460800
+lolin_s3_mini.menu.UploadSpeed.512000.windows=512000
+lolin_s3_mini.menu.UploadSpeed.512000.upload.speed=512000
+
+lolin_s3_mini.menu.DebugLevel.none=None
+lolin_s3_mini.menu.DebugLevel.none.build.code_debug=0
+lolin_s3_mini.menu.DebugLevel.error=Error
+lolin_s3_mini.menu.DebugLevel.error.build.code_debug=1
+lolin_s3_mini.menu.DebugLevel.warn=Warn
+lolin_s3_mini.menu.DebugLevel.warn.build.code_debug=2
+lolin_s3_mini.menu.DebugLevel.info=Info
+lolin_s3_mini.menu.DebugLevel.info.build.code_debug=3
+lolin_s3_mini.menu.DebugLevel.debug=Debug
+lolin_s3_mini.menu.DebugLevel.debug.build.code_debug=4
+lolin_s3_mini.menu.DebugLevel.verbose=Verbose
+lolin_s3_mini.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin_s3_mini.menu.EraseFlash.none=Disabled
+lolin_s3_mini.menu.EraseFlash.none.upload.erase_cmd=
+lolin_s3_mini.menu.EraseFlash.all=Enabled
+lolin_s3_mini.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lolin_s3_mini_pro.name=LOLIN S3 Mini Pro
+lolin_s3_mini_pro.vid.0=0x303a
+lolin_s3_mini_pro.pid.0=0x8216
+
+lolin_s3_mini_pro.bootloader.tool=esptool_py
+lolin_s3_mini_pro.bootloader.tool.default=esptool_py
+
+lolin_s3_mini_pro.upload.tool=esptool_py
+lolin_s3_mini_pro.upload.tool.default=esptool_py
+lolin_s3_mini_pro.upload.tool.network=esp_ota
+
+lolin_s3_mini_pro.upload.maximum_size=1310720
+lolin_s3_mini_pro.upload.maximum_data_size=327680
+lolin_s3_mini_pro.upload.flags=
+lolin_s3_mini_pro.upload.extra_flags=
+lolin_s3_mini_pro.upload.use_1200bps_touch=false
+lolin_s3_mini_pro.upload.wait_for_upload_port=false
+
+lolin_s3_mini_pro.serial.disableDTR=false
+lolin_s3_mini_pro.serial.disableRTS=false
+
+lolin_s3_mini_pro.build.tarch=xtensa
+lolin_s3_mini_pro.build.bootloader_addr=0x0
+lolin_s3_mini_pro.build.target=esp32s3
+lolin_s3_mini_pro.build.mcu=esp32s3
+lolin_s3_mini_pro.build.core=esp32
+lolin_s3_mini_pro.build.variant=lolin_s3_mini_pro
+lolin_s3_mini_pro.build.board=LOLIN_S3_MINI_PRO
+
+lolin_s3_mini_pro.build.usb_mode=1
+lolin_s3_mini_pro.build.cdc_on_boot=0
+lolin_s3_mini_pro.build.msc_on_boot=0
+lolin_s3_mini_pro.build.dfu_on_boot=0
+lolin_s3_mini_pro.build.f_cpu=240000000L
+lolin_s3_mini_pro.build.flash_size=4MB
+lolin_s3_mini_pro.build.flash_freq=80m
+lolin_s3_mini_pro.build.flash_mode=dio
+lolin_s3_mini_pro.build.boot=qio
+lolin_s3_mini_pro.build.boot_freq=80m
+lolin_s3_mini_pro.build.partitions=default
+lolin_s3_mini_pro.build.defines=-DBOARD_HAS_PSRAM
+lolin_s3_mini_pro.build.loop_core=
+lolin_s3_mini_pro.build.event_core=
+lolin_s3_mini_pro.build.psram_type=qspi
+lolin_s3_mini_pro.build.memory_type={build.boot}_{build.psram_type}
+
+lolin_s3_mini_pro.menu.FlashMode.qio=QIO 80MHz
+lolin_s3_mini_pro.menu.FlashMode.qio.build.flash_mode=dio
+lolin_s3_mini_pro.menu.FlashMode.qio.build.boot=qio
+lolin_s3_mini_pro.menu.FlashMode.qio.build.boot_freq=80m
+lolin_s3_mini_pro.menu.FlashMode.qio.build.flash_freq=80m
+lolin_s3_mini_pro.menu.FlashMode.qio120=QIO 120MHz
+lolin_s3_mini_pro.menu.FlashMode.qio120.build.flash_mode=dio
+lolin_s3_mini_pro.menu.FlashMode.qio120.build.boot=qio
+lolin_s3_mini_pro.menu.FlashMode.qio120.build.boot_freq=120m
+lolin_s3_mini_pro.menu.FlashMode.qio120.build.flash_freq=80m
+
+lolin_s3_mini_pro.menu.LoopCore.1=Core 1
+lolin_s3_mini_pro.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lolin_s3_mini_pro.menu.LoopCore.0=Core 0
+lolin_s3_mini_pro.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lolin_s3_mini_pro.menu.EventsCore.1=Core 1
+lolin_s3_mini_pro.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lolin_s3_mini_pro.menu.EventsCore.0=Core 0
+lolin_s3_mini_pro.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lolin_s3_mini_pro.menu.USBMode.hwcdc=Hardware CDC and JTAG
+lolin_s3_mini_pro.menu.USBMode.hwcdc.build.usb_mode=1
+lolin_s3_mini_pro.menu.USBMode.default=USB-OTG (TinyUSB)
+lolin_s3_mini_pro.menu.USBMode.default.build.usb_mode=0
+
+lolin_s3_mini_pro.menu.CDCOnBoot.default=Disabled
+lolin_s3_mini_pro.menu.CDCOnBoot.default.build.cdc_on_boot=0
+lolin_s3_mini_pro.menu.CDCOnBoot.cdc=Enabled
+lolin_s3_mini_pro.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+lolin_s3_mini_pro.menu.MSCOnBoot.default=Disabled
+lolin_s3_mini_pro.menu.MSCOnBoot.default.build.msc_on_boot=0
+lolin_s3_mini_pro.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+lolin_s3_mini_pro.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lolin_s3_mini_pro.menu.DFUOnBoot.default=Disabled
+lolin_s3_mini_pro.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lolin_s3_mini_pro.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+lolin_s3_mini_pro.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lolin_s3_mini_pro.menu.UploadMode.default=UART0 / Hardware CDC
+lolin_s3_mini_pro.menu.UploadMode.default.upload.use_1200bps_touch=false
+lolin_s3_mini_pro.menu.UploadMode.default.upload.wait_for_upload_port=false
+lolin_s3_mini_pro.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+lolin_s3_mini_pro.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+lolin_s3_mini_pro.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+lolin_s3_mini_pro.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lolin_s3_mini_pro.menu.PartitionScheme.default.build.partitions=default
+lolin_s3_mini_pro.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lolin_s3_mini_pro.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lolin_s3_mini_pro.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lolin_s3_mini_pro.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lolin_s3_mini_pro.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lolin_s3_mini_pro.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lolin_s3_mini_pro.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lolin_s3_mini_pro.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lolin_s3_mini_pro.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lolin_s3_mini_pro.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lolin_s3_mini_pro.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lolin_s3_mini_pro.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lolin_s3_mini_pro.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lolin_s3_mini_pro.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lolin_s3_mini_pro.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lolin_s3_mini_pro.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lolin_s3_mini_pro.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+lolin_s3_mini_pro.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+lolin_s3_mini_pro.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+lolin_s3_mini_pro.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+lolin_s3_mini_pro.menu.PartitionScheme.rainmaker=RainMaker 4MB
+lolin_s3_mini_pro.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+lolin_s3_mini_pro.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+lolin_s3_mini_pro.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+lolin_s3_mini_pro.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+lolin_s3_mini_pro.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+lolin_s3_mini_pro.menu.CPUFreq.240=240MHz (WiFi)
+lolin_s3_mini_pro.menu.CPUFreq.240.build.f_cpu=240000000L
+lolin_s3_mini_pro.menu.CPUFreq.160=160MHz (WiFi)
+lolin_s3_mini_pro.menu.CPUFreq.160.build.f_cpu=160000000L
+lolin_s3_mini_pro.menu.CPUFreq.80=80MHz (WiFi)
+lolin_s3_mini_pro.menu.CPUFreq.80.build.f_cpu=80000000L
+lolin_s3_mini_pro.menu.CPUFreq.40=40MHz
+lolin_s3_mini_pro.menu.CPUFreq.40.build.f_cpu=40000000L
+lolin_s3_mini_pro.menu.CPUFreq.20=20MHz
+lolin_s3_mini_pro.menu.CPUFreq.20.build.f_cpu=20000000L
+lolin_s3_mini_pro.menu.CPUFreq.10=10MHz
+lolin_s3_mini_pro.menu.CPUFreq.10.build.f_cpu=10000000L
+
+lolin_s3_mini_pro.menu.UploadSpeed.921600=921600
+lolin_s3_mini_pro.menu.UploadSpeed.921600.upload.speed=921600
+lolin_s3_mini_pro.menu.UploadSpeed.115200=115200
+lolin_s3_mini_pro.menu.UploadSpeed.115200.upload.speed=115200
+lolin_s3_mini_pro.menu.UploadSpeed.256000.windows=256000
+lolin_s3_mini_pro.menu.UploadSpeed.256000.upload.speed=256000
+lolin_s3_mini_pro.menu.UploadSpeed.230400.windows.upload.speed=256000
+lolin_s3_mini_pro.menu.UploadSpeed.230400=230400
+lolin_s3_mini_pro.menu.UploadSpeed.230400.upload.speed=230400
+lolin_s3_mini_pro.menu.UploadSpeed.460800.linux=460800
+lolin_s3_mini_pro.menu.UploadSpeed.460800.macosx=460800
+lolin_s3_mini_pro.menu.UploadSpeed.460800.upload.speed=460800
+lolin_s3_mini_pro.menu.UploadSpeed.512000.windows=512000
+lolin_s3_mini_pro.menu.UploadSpeed.512000.upload.speed=512000
+
+lolin_s3_mini_pro.menu.DebugLevel.none=None
+lolin_s3_mini_pro.menu.DebugLevel.none.build.code_debug=0
+lolin_s3_mini_pro.menu.DebugLevel.error=Error
+lolin_s3_mini_pro.menu.DebugLevel.error.build.code_debug=1
+lolin_s3_mini_pro.menu.DebugLevel.warn=Warn
+lolin_s3_mini_pro.menu.DebugLevel.warn.build.code_debug=2
+lolin_s3_mini_pro.menu.DebugLevel.info=Info
+lolin_s3_mini_pro.menu.DebugLevel.info.build.code_debug=3
+lolin_s3_mini_pro.menu.DebugLevel.debug=Debug
+lolin_s3_mini_pro.menu.DebugLevel.debug.build.code_debug=4
+lolin_s3_mini_pro.menu.DebugLevel.verbose=Verbose
+lolin_s3_mini_pro.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin_s3_mini_pro.menu.EraseFlash.none=Disabled
+lolin_s3_mini_pro.menu.EraseFlash.none.upload.erase_cmd=
+lolin_s3_mini_pro.menu.EraseFlash.all=Enabled
+lolin_s3_mini_pro.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lolin_s3_pro.name=LOLIN S3 Pro
+lolin_s3_pro.vid.0=0x303a
+lolin_s3_pro.pid.0=0x8161
+
+lolin_s3_pro.bootloader.tool=esptool_py
+lolin_s3_pro.bootloader.tool.default=esptool_py
+
+lolin_s3_pro.upload.tool=esptool_py
+lolin_s3_pro.upload.tool.default=esptool_py
+lolin_s3_pro.upload.tool.network=esp_ota
+
+lolin_s3_pro.upload.maximum_size=1310720
+lolin_s3_pro.upload.maximum_data_size=327680
+lolin_s3_pro.upload.flags=
+lolin_s3_pro.upload.extra_flags=
+lolin_s3_pro.upload.use_1200bps_touch=false
+lolin_s3_pro.upload.wait_for_upload_port=false
+
+lolin_s3_pro.serial.disableDTR=false
+lolin_s3_pro.serial.disableRTS=false
+
+lolin_s3_pro.build.tarch=xtensa
+lolin_s3_pro.build.bootloader_addr=0x0
+lolin_s3_pro.build.target=esp32s3
+lolin_s3_pro.build.mcu=esp32s3
+lolin_s3_pro.build.core=esp32
+lolin_s3_pro.build.variant=lolin_s3_pro
+lolin_s3_pro.build.board=LOLIN_S3_PRO
+
+lolin_s3_pro.build.usb_mode=1
+lolin_s3_pro.build.cdc_on_boot=0
+lolin_s3_pro.build.msc_on_boot=0
+lolin_s3_pro.build.dfu_on_boot=0
+lolin_s3_pro.build.f_cpu=240000000L
+lolin_s3_pro.build.flash_size=16MB
+lolin_s3_pro.build.flash_freq=80m
+lolin_s3_pro.build.flash_mode=dio
+lolin_s3_pro.build.boot=qio
+lolin_s3_pro.build.boot_freq=80m
+lolin_s3_pro.build.partitions=default
+lolin_s3_pro.build.defines=-DBOARD_HAS_PSRAM
+lolin_s3_pro.build.loop_core=
+lolin_s3_pro.build.event_core=
+lolin_s3_pro.build.psram_type=opi
+lolin_s3_pro.build.memory_type={build.boot}_{build.psram_type}
+
+lolin_s3_pro.menu.FlashMode.qio=QIO 80MHz
+lolin_s3_pro.menu.FlashMode.qio.build.flash_mode=dio
+lolin_s3_pro.menu.FlashMode.qio.build.boot=qio
+lolin_s3_pro.menu.FlashMode.qio.build.boot_freq=80m
+lolin_s3_pro.menu.FlashMode.qio.build.flash_freq=80m
+lolin_s3_pro.menu.FlashMode.qio120=QIO 120MHz
+lolin_s3_pro.menu.FlashMode.qio120.build.flash_mode=dio
+lolin_s3_pro.menu.FlashMode.qio120.build.boot=qio
+lolin_s3_pro.menu.FlashMode.qio120.build.boot_freq=120m
+lolin_s3_pro.menu.FlashMode.qio120.build.flash_freq=80m
+
+lolin_s3_pro.menu.LoopCore.1=Core 1
+lolin_s3_pro.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lolin_s3_pro.menu.LoopCore.0=Core 0
+lolin_s3_pro.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lolin_s3_pro.menu.EventsCore.1=Core 1
+lolin_s3_pro.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lolin_s3_pro.menu.EventsCore.0=Core 0
+lolin_s3_pro.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lolin_s3_pro.menu.USBMode.hwcdc=Hardware CDC and JTAG
+lolin_s3_pro.menu.USBMode.hwcdc.build.usb_mode=1
+lolin_s3_pro.menu.USBMode.default=USB-OTG (TinyUSB)
+lolin_s3_pro.menu.USBMode.default.build.usb_mode=0
+
+lolin_s3_pro.menu.CDCOnBoot.default=Disabled
+lolin_s3_pro.menu.CDCOnBoot.default.build.cdc_on_boot=0
+lolin_s3_pro.menu.CDCOnBoot.cdc=Enabled
+lolin_s3_pro.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+lolin_s3_pro.menu.MSCOnBoot.default=Disabled
+lolin_s3_pro.menu.MSCOnBoot.default.build.msc_on_boot=0
+lolin_s3_pro.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+lolin_s3_pro.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lolin_s3_pro.menu.DFUOnBoot.default=Disabled
+lolin_s3_pro.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lolin_s3_pro.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+lolin_s3_pro.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lolin_s3_pro.menu.UploadMode.default=UART0 / Hardware CDC
+lolin_s3_pro.menu.UploadMode.default.upload.use_1200bps_touch=false
+lolin_s3_pro.menu.UploadMode.default.upload.wait_for_upload_port=false
+lolin_s3_pro.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+lolin_s3_pro.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+lolin_s3_pro.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+lolin_s3_pro.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+lolin_s3_pro.menu.PartitionScheme.fatflash.build.partitions=ffat
+lolin_s3_pro.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+lolin_s3_pro.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+lolin_s3_pro.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+lolin_s3_pro.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+lolin_s3_pro.menu.PartitionScheme.rainmaker=RainMaker 4MB
+lolin_s3_pro.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+lolin_s3_pro.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+lolin_s3_pro.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+lolin_s3_pro.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+lolin_s3_pro.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+lolin_s3_pro.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+lolin_s3_pro.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+lolin_s3_pro.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+lolin_s3_pro.menu.CPUFreq.240=240MHz (WiFi)
+lolin_s3_pro.menu.CPUFreq.240.build.f_cpu=240000000L
+lolin_s3_pro.menu.CPUFreq.160=160MHz (WiFi)
+lolin_s3_pro.menu.CPUFreq.160.build.f_cpu=160000000L
+lolin_s3_pro.menu.CPUFreq.80=80MHz (WiFi)
+lolin_s3_pro.menu.CPUFreq.80.build.f_cpu=80000000L
+lolin_s3_pro.menu.CPUFreq.40=40MHz
+lolin_s3_pro.menu.CPUFreq.40.build.f_cpu=40000000L
+lolin_s3_pro.menu.CPUFreq.20=20MHz
+lolin_s3_pro.menu.CPUFreq.20.build.f_cpu=20000000L
+lolin_s3_pro.menu.CPUFreq.10=10MHz
+lolin_s3_pro.menu.CPUFreq.10.build.f_cpu=10000000L
+
+lolin_s3_pro.menu.UploadSpeed.921600=921600
+lolin_s3_pro.menu.UploadSpeed.921600.upload.speed=921600
+lolin_s3_pro.menu.UploadSpeed.115200=115200
+lolin_s3_pro.menu.UploadSpeed.115200.upload.speed=115200
+lolin_s3_pro.menu.UploadSpeed.256000.windows=256000
+lolin_s3_pro.menu.UploadSpeed.256000.upload.speed=256000
+lolin_s3_pro.menu.UploadSpeed.230400.windows.upload.speed=256000
+lolin_s3_pro.menu.UploadSpeed.230400=230400
+lolin_s3_pro.menu.UploadSpeed.230400.upload.speed=230400
+lolin_s3_pro.menu.UploadSpeed.460800.linux=460800
+lolin_s3_pro.menu.UploadSpeed.460800.macosx=460800
+lolin_s3_pro.menu.UploadSpeed.460800.upload.speed=460800
+lolin_s3_pro.menu.UploadSpeed.512000.windows=512000
+lolin_s3_pro.menu.UploadSpeed.512000.upload.speed=512000
+
+lolin_s3_pro.menu.DebugLevel.none=None
+lolin_s3_pro.menu.DebugLevel.none.build.code_debug=0
+lolin_s3_pro.menu.DebugLevel.error=Error
+lolin_s3_pro.menu.DebugLevel.error.build.code_debug=1
+lolin_s3_pro.menu.DebugLevel.warn=Warn
+lolin_s3_pro.menu.DebugLevel.warn.build.code_debug=2
+lolin_s3_pro.menu.DebugLevel.info=Info
+lolin_s3_pro.menu.DebugLevel.info.build.code_debug=3
+lolin_s3_pro.menu.DebugLevel.debug=Debug
+lolin_s3_pro.menu.DebugLevel.debug.build.code_debug=4
+lolin_s3_pro.menu.DebugLevel.verbose=Verbose
+lolin_s3_pro.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin_s3_pro.menu.EraseFlash.none=Disabled
+lolin_s3_pro.menu.EraseFlash.none.upload.erase_cmd=
+lolin_s3_pro.menu.EraseFlash.all=Enabled
+lolin_s3_pro.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 lolin32.name=WEMOS LOLIN32
 
+lolin32.bootloader.tool=esptool_py
+lolin32.bootloader.tool.default=esptool_py
+
 lolin32.upload.tool=esptool_py
+lolin32.upload.tool.default=esptool_py
+lolin32.upload.tool.network=esp_ota
+
 lolin32.upload.maximum_size=1310720
 lolin32.upload.maximum_data_size=327680
-lolin32.upload.wait_for_upload_port=true
+lolin32.upload.flags=
+lolin32.upload.extra_flags=
 
 lolin32.serial.disableDTR=true
 lolin32.serial.disableRTS=true
 
+lolin32.build.tarch=xtensa
+lolin32.build.bootloader_addr=0x1000
+lolin32.build.target=esp32
 lolin32.build.mcu=esp32
 lolin32.build.core=esp32
 lolin32.build.variant=lolin32
@@ -1295,18 +10792,341 @@ lolin32.menu.UploadSpeed.460800.upload.speed=460800
 lolin32.menu.UploadSpeed.512000.windows=512000
 lolin32.menu.UploadSpeed.512000.upload.speed=512000
 
+lolin32.menu.DebugLevel.none=None
+lolin32.menu.DebugLevel.none.build.code_debug=0
+lolin32.menu.DebugLevel.error=Error
+lolin32.menu.DebugLevel.error.build.code_debug=1
+lolin32.menu.DebugLevel.warn=Warn
+lolin32.menu.DebugLevel.warn.build.code_debug=2
+lolin32.menu.DebugLevel.info=Info
+lolin32.menu.DebugLevel.info.build.code_debug=3
+lolin32.menu.DebugLevel.debug=Debug
+lolin32.menu.DebugLevel.debug.build.code_debug=4
+lolin32.menu.DebugLevel.verbose=Verbose
+lolin32.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin32.menu.EraseFlash.none=Disabled
+lolin32.menu.EraseFlash.none.upload.erase_cmd=
+lolin32.menu.EraseFlash.all=Enabled
+lolin32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+viralink32g01.name=ViraLink Gate32-0.1
+
+viralink32g01.bootloader.tool=esptool_py
+viralink32g01.bootloader.tool.default=esptool_py
+
+viralink32g01.upload.tool=esptool_py
+viralink32g01.upload.tool.default=esptool_py
+viralink32g01.upload.tool.network=esp_ota
+
+viralink32g01.upload.maximum_size=1310720
+viralink32g01.upload.maximum_data_size=327680
+viralink32g01.upload.flags=
+viralink32g01.upload.extra_flags=
+
+viralink32g01.serial.disableDTR=true
+viralink32g01.serial.disableRTS=true
+
+viralink32g01.build.tarch=xtensa
+viralink32g01.build.bootloader_addr=0x1000
+viralink32g01.build.target=esp32
+viralink32g01.build.mcu=esp32
+viralink32g01.build.core=esp32
+viralink32g01.build.variant=ViraLink-G0.1
+viralink32g01.build.board=VIRALINK_GATE32_01
+
+viralink32g01.build.f_cpu=240000000L
+viralink32g01.build.flash_mode=dio
+viralink32g01.build.flash_size=4MB
+viralink32g01.build.boot=dio
+viralink32g01.build.partitions=default
+viralink32g01.build.defines=
+
+viralink32g01.menu.FlashFreq.80=80MHz
+viralink32g01.menu.FlashFreq.80.build.flash_freq=80m
+viralink32g01.menu.FlashFreq.40=40MHz
+viralink32g01.menu.FlashFreq.40.build.flash_freq=40m
+
+viralink32g01.menu.PartitionScheme.default=Default
+viralink32g01.menu.PartitionScheme.default.build.partitions=default
+viralink32g01.menu.PartitionScheme.no_ota=No OTA (Large APP)
+viralink32g01.menu.PartitionScheme.no_ota.build.partitions=no_ota
+viralink32g01.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+viralink32g01.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+viralink32g01.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+viralink32g01.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+viralink32g01.menu.CPUFreq.240=240MHz (WiFi/BT)
+viralink32g01.menu.CPUFreq.240.build.f_cpu=240000000L
+viralink32g01.menu.CPUFreq.160=160MHz (WiFi/BT)
+viralink32g01.menu.CPUFreq.160.build.f_cpu=160000000L
+viralink32g01.menu.CPUFreq.80=80MHz (WiFi/BT)
+viralink32g01.menu.CPUFreq.80.build.f_cpu=80000000L
+viralink32g01.menu.CPUFreq.40=40MHz (40MHz XTAL)
+viralink32g01.menu.CPUFreq.40.build.f_cpu=40000000L
+viralink32g01.menu.CPUFreq.26=26MHz (26MHz XTAL)
+viralink32g01.menu.CPUFreq.26.build.f_cpu=26000000L
+viralink32g01.menu.CPUFreq.20=20MHz (40MHz XTAL)
+viralink32g01.menu.CPUFreq.20.build.f_cpu=20000000L
+viralink32g01.menu.CPUFreq.13=13MHz (26MHz XTAL)
+viralink32g01.menu.CPUFreq.13.build.f_cpu=13000000L
+viralink32g01.menu.CPUFreq.10=10MHz (40MHz XTAL)
+viralink32g01.menu.CPUFreq.10.build.f_cpu=10000000L
+
+viralink32g01.menu.UploadSpeed.921600=921600
+viralink32g01.menu.UploadSpeed.921600.upload.speed=921600
+viralink32g01.menu.UploadSpeed.115200=115200
+viralink32g01.menu.UploadSpeed.115200.upload.speed=115200
+viralink32g01.menu.UploadSpeed.256000.windows=256000
+viralink32g01.menu.UploadSpeed.256000.upload.speed=256000
+viralink32g01.menu.UploadSpeed.230400.windows.upload.speed=256000
+viralink32g01.menu.UploadSpeed.230400=230400
+viralink32g01.menu.UploadSpeed.230400.upload.speed=230400
+viralink32g01.menu.UploadSpeed.460800.linux=460800
+viralink32g01.menu.UploadSpeed.460800.macosx=460800
+viralink32g01.menu.UploadSpeed.460800.upload.speed=460800
+viralink32g01.menu.UploadSpeed.512000.windows=512000
+viralink32g01.menu.UploadSpeed.512000.upload.speed=512000
+
+viralink32g01.menu.DebugLevel.none=None
+viralink32g01.menu.DebugLevel.none.build.code_debug=0
+viralink32g01.menu.DebugLevel.error=Error
+viralink32g01.menu.DebugLevel.error.build.code_debug=1
+viralink32g01.menu.DebugLevel.warn=Warn
+viralink32g01.menu.DebugLevel.warn.build.code_debug=2
+viralink32g01.menu.DebugLevel.info=Info
+viralink32g01.menu.DebugLevel.info.build.code_debug=3
+viralink32g01.menu.DebugLevel.debug=Debug
+viralink32g01.menu.DebugLevel.debug.build.code_debug=4
+viralink32g01.menu.DebugLevel.verbose=Verbose
+viralink32g01.menu.DebugLevel.verbose.build.code_debug=5
+
+viralink32g01.menu.EraseFlash.none=Disabled
+viralink32g01.menu.EraseFlash.none.upload.erase_cmd=
+viralink32g01.menu.EraseFlash.all=Enabled
+viralink32g01.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+viralink32g11.name=ViraLink Gate32-1.1
+
+viralink32g11.bootloader.tool=esptool_py
+viralink32g11.bootloader.tool.default=esptool_py
+
+viralink32g11.upload.tool=esptool_py
+viralink32g11.upload.tool.default=esptool_py
+viralink32g11.upload.tool.network=esp_ota
+
+viralink32g11.upload.maximum_size=1310720
+viralink32g11.upload.maximum_data_size=327680
+viralink32g11.upload.flags=
+viralink32g11.upload.extra_flags=
+
+viralink32g11.serial.disableDTR=true
+viralink32g11.serial.disableRTS=true
+
+viralink32g11.build.tarch=xtensa
+viralink32g11.build.bootloader_addr=0x1000
+viralink32g11.build.target=esp32
+viralink32g11.build.mcu=esp32
+viralink32g11.build.core=esp32
+viralink32g11.build.variant=ViraLink-G1.1
+viralink32g11.build.board=VIRALINK_GATE32_11
+
+viralink32g11.build.f_cpu=240000000L
+viralink32g11.build.flash_mode=dio
+viralink32g11.build.flash_size=4MB
+viralink32g11.build.boot=dio
+viralink32g11.build.partitions=default
+viralink32g11.build.defines=
+
+viralink32g11.menu.FlashFreq.80=80MHz
+viralink32g11.menu.FlashFreq.80.build.flash_freq=80m
+viralink32g11.menu.FlashFreq.40=40MHz
+viralink32g11.menu.FlashFreq.40.build.flash_freq=40m
+
+viralink32g11.menu.PartitionScheme.default=Default
+viralink32g11.menu.PartitionScheme.default.build.partitions=default
+viralink32g11.menu.PartitionScheme.no_ota=No OTA (Large APP)
+viralink32g11.menu.PartitionScheme.no_ota.build.partitions=no_ota
+viralink32g11.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+viralink32g11.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+viralink32g11.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+viralink32g11.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+viralink32g11.menu.CPUFreq.240=240MHz (WiFi/BT)
+viralink32g11.menu.CPUFreq.240.build.f_cpu=240000000L
+viralink32g11.menu.CPUFreq.160=160MHz (WiFi/BT)
+viralink32g11.menu.CPUFreq.160.build.f_cpu=160000000L
+viralink32g11.menu.CPUFreq.80=80MHz (WiFi/BT)
+viralink32g11.menu.CPUFreq.80.build.f_cpu=80000000L
+viralink32g11.menu.CPUFreq.40=40MHz (40MHz XTAL)
+viralink32g11.menu.CPUFreq.40.build.f_cpu=40000000L
+viralink32g11.menu.CPUFreq.26=26MHz (26MHz XTAL)
+viralink32g11.menu.CPUFreq.26.build.f_cpu=26000000L
+viralink32g11.menu.CPUFreq.20=20MHz (40MHz XTAL)
+viralink32g11.menu.CPUFreq.20.build.f_cpu=20000000L
+viralink32g11.menu.CPUFreq.13=13MHz (26MHz XTAL)
+viralink32g11.menu.CPUFreq.13.build.f_cpu=13000000L
+viralink32g11.menu.CPUFreq.10=10MHz (40MHz XTAL)
+viralink32g11.menu.CPUFreq.10.build.f_cpu=10000000L
+
+viralink32g11.menu.UploadSpeed.921600=921600
+viralink32g11.menu.UploadSpeed.921600.upload.speed=921600
+viralink32g11.menu.UploadSpeed.115200=115200
+viralink32g11.menu.UploadSpeed.115200.upload.speed=115200
+viralink32g11.menu.UploadSpeed.256000.windows=256000
+viralink32g11.menu.UploadSpeed.256000.upload.speed=256000
+viralink32g11.menu.UploadSpeed.230400.windows.upload.speed=256000
+viralink32g11.menu.UploadSpeed.230400=230400
+viralink32g11.menu.UploadSpeed.230400.upload.speed=230400
+viralink32g11.menu.UploadSpeed.460800.linux=460800
+viralink32g11.menu.UploadSpeed.460800.macosx=460800
+viralink32g11.menu.UploadSpeed.460800.upload.speed=460800
+viralink32g11.menu.UploadSpeed.512000.windows=512000
+viralink32g11.menu.UploadSpeed.512000.upload.speed=512000
+
+viralink32g11.menu.DebugLevel.none=None
+viralink32g11.menu.DebugLevel.none.build.code_debug=0
+viralink32g11.menu.DebugLevel.error=Error
+viralink32g11.menu.DebugLevel.error.build.code_debug=1
+viralink32g11.menu.DebugLevel.warn=Warn
+viralink32g11.menu.DebugLevel.warn.build.code_debug=2
+viralink32g11.menu.DebugLevel.info=Info
+viralink32g11.menu.DebugLevel.info.build.code_debug=3
+viralink32g11.menu.DebugLevel.debug=Debug
+viralink32g11.menu.DebugLevel.debug.build.code_debug=4
+viralink32g11.menu.DebugLevel.verbose=Verbose
+viralink32g11.menu.DebugLevel.verbose.build.code_debug=5
+
+viralink32g11.menu.EraseFlash.none=Disabled
+viralink32g11.menu.EraseFlash.none.upload.erase_cmd=
+viralink32g11.menu.EraseFlash.all=Enabled
+viralink32g11.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lolin32-lite.name=WEMOS LOLIN32 Lite
+
+lolin32-lite.bootloader.tool=esptool_py
+lolin32-lite.bootloader.tool.default=esptool_py
+
+lolin32-lite.upload.tool=esptool_py
+lolin32-lite.upload.tool.default=esptool_py
+lolin32-lite.upload.tool.network=esp_ota
+
+lolin32-lite.upload.maximum_size=1310720
+lolin32-lite.upload.maximum_data_size=327680
+lolin32-lite.upload.wait_for_upload_port=true
+lolin32-lite.upload.flags=
+lolin32-lite.upload.extra_flags=
+
+lolin32-lite.serial.disableDTR=true
+lolin32-lite.serial.disableRTS=true
+
+lolin32-lite.build.tarch=xtensa
+lolin32-lite.build.bootloader_addr=0x1000
+lolin32-lite.build.target=esp32
+lolin32-lite.build.mcu=esp32
+lolin32-lite.build.core=esp32
+lolin32-lite.build.variant=lolin32-lite
+lolin32-lite.build.board=LOLIN32_LITE
+
+lolin32-lite.build.f_cpu=240000000L
+lolin32-lite.build.flash_mode=dio
+lolin32-lite.build.flash_size=4MB
+lolin32-lite.build.boot=dio
+lolin32-lite.build.partitions=default
+lolin32-lite.build.defines=
+
+lolin32-lite.menu.FlashFreq.80=80MHz
+lolin32-lite.menu.FlashFreq.80.build.flash_freq=80m
+lolin32-lite.menu.FlashFreq.40=40MHz
+lolin32-lite.menu.FlashFreq.40.build.flash_freq=40m
+
+lolin32-lite.menu.PartitionScheme.default=Default
+lolin32-lite.menu.PartitionScheme.default.build.partitions=default
+lolin32-lite.menu.PartitionScheme.no_ota=No OTA (Large APP)
+lolin32-lite.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lolin32-lite.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lolin32-lite.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+lolin32-lite.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+lolin32-lite.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+lolin32-lite.menu.CPUFreq.240=240MHz (WiFi/BT)
+lolin32-lite.menu.CPUFreq.240.build.f_cpu=240000000L
+lolin32-lite.menu.CPUFreq.160=160MHz (WiFi/BT)
+lolin32-lite.menu.CPUFreq.160.build.f_cpu=160000000L
+lolin32-lite.menu.CPUFreq.80=80MHz (WiFi/BT)
+lolin32-lite.menu.CPUFreq.80.build.f_cpu=80000000L
+lolin32-lite.menu.CPUFreq.40=40MHz (40MHz XTAL)
+lolin32-lite.menu.CPUFreq.40.build.f_cpu=40000000L
+lolin32-lite.menu.CPUFreq.26=26MHz (26MHz XTAL)
+lolin32-lite.menu.CPUFreq.26.build.f_cpu=26000000L
+lolin32-lite.menu.CPUFreq.20=20MHz (40MHz XTAL)
+lolin32-lite.menu.CPUFreq.20.build.f_cpu=20000000L
+lolin32-lite.menu.CPUFreq.13=13MHz (26MHz XTAL)
+lolin32-lite.menu.CPUFreq.13.build.f_cpu=13000000L
+lolin32-lite.menu.CPUFreq.10=10MHz (40MHz XTAL)
+lolin32-lite.menu.CPUFreq.10.build.f_cpu=10000000L
+
+lolin32-lite.menu.UploadSpeed.921600=921600
+lolin32-lite.menu.UploadSpeed.921600.upload.speed=921600
+lolin32-lite.menu.UploadSpeed.115200=115200
+lolin32-lite.menu.UploadSpeed.115200.upload.speed=115200
+lolin32-lite.menu.UploadSpeed.256000.windows=256000
+lolin32-lite.menu.UploadSpeed.256000.upload.speed=256000
+lolin32-lite.menu.UploadSpeed.230400.windows.upload.speed=256000
+lolin32-lite.menu.UploadSpeed.230400=230400
+lolin32-lite.menu.UploadSpeed.230400.upload.speed=230400
+lolin32-lite.menu.UploadSpeed.460800.linux=460800
+lolin32-lite.menu.UploadSpeed.460800.macosx=460800
+lolin32-lite.menu.UploadSpeed.460800.upload.speed=460800
+lolin32-lite.menu.UploadSpeed.512000.windows=512000
+lolin32-lite.menu.UploadSpeed.512000.upload.speed=512000
+
+lolin32-lite.menu.DebugLevel.none=None
+lolin32-lite.menu.DebugLevel.none.build.code_debug=0
+lolin32-lite.menu.DebugLevel.error=Error
+lolin32-lite.menu.DebugLevel.error.build.code_debug=1
+lolin32-lite.menu.DebugLevel.warn=Warn
+lolin32-lite.menu.DebugLevel.warn.build.code_debug=2
+lolin32-lite.menu.DebugLevel.info=Info
+lolin32-lite.menu.DebugLevel.info.build.code_debug=3
+lolin32-lite.menu.DebugLevel.debug=Debug
+lolin32-lite.menu.DebugLevel.debug.build.code_debug=4
+lolin32-lite.menu.DebugLevel.verbose=Verbose
+lolin32-lite.menu.DebugLevel.verbose.build.code_debug=5
+
+lolin32-lite.menu.EraseFlash.none=Disabled
+lolin32-lite.menu.EraseFlash.none.upload.erase_cmd=
+lolin32-lite.menu.EraseFlash.all=Enabled
+lolin32-lite.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 pocket_32.name=Dongsen Tech Pocket 32
 
+pocket_32.bootloader.tool=esptool_py
+pocket_32.bootloader.tool.default=esptool_py
+
 pocket_32.upload.tool=esptool_py
+pocket_32.upload.tool.default=esptool_py
+pocket_32.upload.tool.network=esp_ota
+
 pocket_32.upload.maximum_size=1310720
 pocket_32.upload.maximum_data_size=327680
-pocket_32.upload.wait_for_upload_port=true
+pocket_32.upload.flags=
+pocket_32.upload.extra_flags=
 
 pocket_32.serial.disableDTR=true
 pocket_32.serial.disableRTS=true
 
+pocket_32.build.tarch=xtensa
+pocket_32.build.bootloader_addr=0x1000
+pocket_32.build.target=esp32
 pocket_32.build.mcu=esp32
 pocket_32.build.core=esp32
 pocket_32.build.variant=pocket_32
@@ -1339,18 +11159,46 @@ pocket_32.menu.UploadSpeed.460800.upload.speed=460800
 pocket_32.menu.UploadSpeed.512000.windows=512000
 pocket_32.menu.UploadSpeed.512000.upload.speed=512000
 
+pocket_32.menu.DebugLevel.none=None
+pocket_32.menu.DebugLevel.none.build.code_debug=0
+pocket_32.menu.DebugLevel.error=Error
+pocket_32.menu.DebugLevel.error.build.code_debug=1
+pocket_32.menu.DebugLevel.warn=Warn
+pocket_32.menu.DebugLevel.warn.build.code_debug=2
+pocket_32.menu.DebugLevel.info=Info
+pocket_32.menu.DebugLevel.info.build.code_debug=3
+pocket_32.menu.DebugLevel.debug=Debug
+pocket_32.menu.DebugLevel.debug.build.code_debug=4
+pocket_32.menu.DebugLevel.verbose=Verbose
+pocket_32.menu.DebugLevel.verbose.build.code_debug=5
+
+pocket_32.menu.EraseFlash.none=Disabled
+pocket_32.menu.EraseFlash.none.upload.erase_cmd=
+pocket_32.menu.EraseFlash.all=Enabled
+pocket_32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 WeMosBat.name=WeMos WiFi&Bluetooth Battery
 
+WeMosBat.bootloader.tool=esptool_py
+WeMosBat.bootloader.tool.default=esptool_py
+
 WeMosBat.upload.tool=esptool_py
+WeMosBat.upload.tool.default=esptool_py
+WeMosBat.upload.tool.network=esp_ota
+
 WeMosBat.upload.maximum_size=1310720
 WeMosBat.upload.maximum_data_size=327680
-WeMosBat.upload.wait_for_upload_port=true
+WeMosBat.upload.flags=
+WeMosBat.upload.extra_flags=
 
 WeMosBat.serial.disableDTR=true
 WeMosBat.serial.disableRTS=true
 
+WeMosBat.build.tarch=xtensa
+WeMosBat.build.bootloader_addr=0x1000
+WeMosBat.build.target=esp32
 WeMosBat.build.mcu=esp32
 WeMosBat.build.core=esp32
 WeMosBat.build.variant=pocket_32
@@ -1363,6 +11211,46 @@ WeMosBat.build.boot=dio
 WeMosBat.build.partitions=default
 WeMosBat.build.defines=
 
+WeMosBat.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+WeMosBat.menu.PartitionScheme.default.build.partitions=default
+WeMosBat.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+WeMosBat.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+WeMosBat.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+WeMosBat.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+WeMosBat.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+WeMosBat.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+WeMosBat.menu.PartitionScheme.minimal.build.partitions=minimal
+WeMosBat.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+WeMosBat.menu.PartitionScheme.no_ota.build.partitions=no_ota
+WeMosBat.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+WeMosBat.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+WeMosBat.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+WeMosBat.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+WeMosBat.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+WeMosBat.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+WeMosBat.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+WeMosBat.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+WeMosBat.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+WeMosBat.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+WeMosBat.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+WeMosBat.menu.PartitionScheme.huge_app.build.partitions=huge_app
+WeMosBat.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+WeMosBat.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+WeMosBat.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+WeMosBat.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+WeMosBat.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+WeMosBat.menu.PartitionScheme.fatflash.build.partitions=ffat
+WeMosBat.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+WeMosBat.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+WeMosBat.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+WeMosBat.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+WeMosBat.menu.PartitionScheme.rainmaker=RainMaker 4MB
+WeMosBat.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+WeMosBat.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+WeMosBat.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+WeMosBat.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+WeMosBat.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
 WeMosBat.menu.FlashFreq.80=80MHz
 WeMosBat.menu.FlashFreq.80.build.flash_freq=80m
 WeMosBat.menu.FlashFreq.40=40MHz
@@ -1396,18 +11284,33 @@ WeMosBat.menu.DebugLevel.debug.build.code_debug=4
 WeMosBat.menu.DebugLevel.verbose=Verbose
 WeMosBat.menu.DebugLevel.verbose.build.code_debug=5
 
+WeMosBat.menu.EraseFlash.none=Disabled
+WeMosBat.menu.EraseFlash.none.upload.erase_cmd=
+WeMosBat.menu.EraseFlash.all=Enabled
+WeMosBat.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 espea32.name=ESPea32
 
+espea32.bootloader.tool=esptool_py
+espea32.bootloader.tool.default=esptool_py
+
 espea32.upload.tool=esptool_py
+espea32.upload.tool.default=esptool_py
+espea32.upload.tool.network=esp_ota
+
 espea32.upload.maximum_size=1310720
 espea32.upload.maximum_data_size=327680
-espea32.upload.wait_for_upload_port=true
+espea32.upload.flags=
+espea32.upload.extra_flags=
 
 espea32.serial.disableDTR=true
 espea32.serial.disableRTS=true
 
+espea32.build.tarch=xtensa
+espea32.build.bootloader_addr=0x1000
+espea32.build.target=esp32
 espea32.build.mcu=esp32
 espea32.build.core=esp32
 espea32.build.variant=espea32
@@ -1440,18 +11343,46 @@ espea32.menu.UploadSpeed.460800.upload.speed=460800
 espea32.menu.UploadSpeed.512000.windows=512000
 espea32.menu.UploadSpeed.512000.upload.speed=512000
 
+espea32.menu.DebugLevel.none=None
+espea32.menu.DebugLevel.none.build.code_debug=0
+espea32.menu.DebugLevel.error=Error
+espea32.menu.DebugLevel.error.build.code_debug=1
+espea32.menu.DebugLevel.warn=Warn
+espea32.menu.DebugLevel.warn.build.code_debug=2
+espea32.menu.DebugLevel.info=Info
+espea32.menu.DebugLevel.info.build.code_debug=3
+espea32.menu.DebugLevel.debug=Debug
+espea32.menu.DebugLevel.debug.build.code_debug=4
+espea32.menu.DebugLevel.verbose=Verbose
+espea32.menu.DebugLevel.verbose.build.code_debug=5
+
+espea32.menu.EraseFlash.none=Disabled
+espea32.menu.EraseFlash.none.upload.erase_cmd=
+espea32.menu.EraseFlash.all=Enabled
+espea32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 quantum.name=Noduino Quantum
 
+quantum.bootloader.tool=esptool_py
+quantum.bootloader.tool.default=esptool_py
+
 quantum.upload.tool=esptool_py
+quantum.upload.tool.default=esptool_py
+quantum.upload.tool.network=esp_ota
+
 quantum.upload.maximum_size=1310720
 quantum.upload.maximum_data_size=327680
-quantum.upload.wait_for_upload_port=true
+quantum.upload.flags=
+quantum.upload.extra_flags=
 
 quantum.serial.disableDTR=true
 quantum.serial.disableRTS=true
 
+quantum.build.tarch=xtensa
+quantum.build.bootloader_addr=0x1000
+quantum.build.target=esp32
 quantum.build.mcu=esp32
 quantum.build.core=esp32
 quantum.build.variant=quantum
@@ -1484,18 +11415,46 @@ quantum.menu.UploadSpeed.460800.upload.speed=460800
 quantum.menu.UploadSpeed.512000.windows=512000
 quantum.menu.UploadSpeed.512000.upload.speed=512000
 
+quantum.menu.DebugLevel.none=None
+quantum.menu.DebugLevel.none.build.code_debug=0
+quantum.menu.DebugLevel.error=Error
+quantum.menu.DebugLevel.error.build.code_debug=1
+quantum.menu.DebugLevel.warn=Warn
+quantum.menu.DebugLevel.warn.build.code_debug=2
+quantum.menu.DebugLevel.info=Info
+quantum.menu.DebugLevel.info.build.code_debug=3
+quantum.menu.DebugLevel.debug=Debug
+quantum.menu.DebugLevel.debug.build.code_debug=4
+quantum.menu.DebugLevel.verbose=Verbose
+quantum.menu.DebugLevel.verbose.build.code_debug=5
+
+quantum.menu.EraseFlash.none=Disabled
+quantum.menu.EraseFlash.none.upload.erase_cmd=
+quantum.menu.EraseFlash.all=Enabled
+quantum.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 node32s.name=Node32s
 
+node32s.bootloader.tool=esptool_py
+node32s.bootloader.tool.default=esptool_py
+
 node32s.upload.tool=esptool_py
+node32s.upload.tool.default=esptool_py
+node32s.upload.tool.network=esp_ota
+
 node32s.upload.maximum_size=1310720
 node32s.upload.maximum_data_size=327680
-node32s.upload.wait_for_upload_port=true
+node32s.upload.flags=
+node32s.upload.extra_flags=
 
 node32s.serial.disableDTR=true
 node32s.serial.disableRTS=true
 
+node32s.build.tarch=xtensa
+node32s.build.bootloader_addr=0x1000
+node32s.build.target=esp32
 node32s.build.mcu=esp32
 node32s.build.core=esp32
 node32s.build.variant=node32s
@@ -1550,18 +11509,33 @@ node32s.menu.DebugLevel.debug.build.code_debug=4
 node32s.menu.DebugLevel.verbose=Verbose
 node32s.menu.DebugLevel.verbose.build.code_debug=5
 
+node32s.menu.EraseFlash.none=Disabled
+node32s.menu.EraseFlash.none.upload.erase_cmd=
+node32s.menu.EraseFlash.all=Enabled
+node32s.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 hornbill32dev.name=Hornbill ESP32 Dev
 
+hornbill32dev.bootloader.tool=esptool_py
+hornbill32dev.bootloader.tool.default=esptool_py
+
 hornbill32dev.upload.tool=esptool_py
+hornbill32dev.upload.tool.default=esptool_py
+hornbill32dev.upload.tool.network=esp_ota
+
 hornbill32dev.upload.maximum_size=1310720
 hornbill32dev.upload.maximum_data_size=327680
-hornbill32dev.upload.wait_for_upload_port=true
+hornbill32dev.upload.flags=
+hornbill32dev.upload.extra_flags=
 
 hornbill32dev.serial.disableDTR=true
 hornbill32dev.serial.disableRTS=true
 
+hornbill32dev.build.tarch=xtensa
+hornbill32dev.build.bootloader_addr=0x1000
+hornbill32dev.build.target=esp32
 hornbill32dev.build.mcu=esp32
 hornbill32dev.build.core=esp32
 hornbill32dev.build.variant=hornbill32dev
@@ -1594,18 +11568,46 @@ hornbill32dev.menu.UploadSpeed.460800.upload.speed=460800
 hornbill32dev.menu.UploadSpeed.512000.windows=512000
 hornbill32dev.menu.UploadSpeed.512000.upload.speed=512000
 
+hornbill32dev.menu.DebugLevel.none=None
+hornbill32dev.menu.DebugLevel.none.build.code_debug=0
+hornbill32dev.menu.DebugLevel.error=Error
+hornbill32dev.menu.DebugLevel.error.build.code_debug=1
+hornbill32dev.menu.DebugLevel.warn=Warn
+hornbill32dev.menu.DebugLevel.warn.build.code_debug=2
+hornbill32dev.menu.DebugLevel.info=Info
+hornbill32dev.menu.DebugLevel.info.build.code_debug=3
+hornbill32dev.menu.DebugLevel.debug=Debug
+hornbill32dev.menu.DebugLevel.debug.build.code_debug=4
+hornbill32dev.menu.DebugLevel.verbose=Verbose
+hornbill32dev.menu.DebugLevel.verbose.build.code_debug=5
+
+hornbill32dev.menu.EraseFlash.none=Disabled
+hornbill32dev.menu.EraseFlash.none.upload.erase_cmd=
+hornbill32dev.menu.EraseFlash.all=Enabled
+hornbill32dev.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 hornbill32minima.name=Hornbill ESP32 Minima
 
+hornbill32minima.bootloader.tool=esptool_py
+hornbill32minima.bootloader.tool.default=esptool_py
+
 hornbill32minima.upload.tool=esptool_py
+hornbill32minima.upload.tool.default=esptool_py
+hornbill32minima.upload.tool.network=esp_ota
+
 hornbill32minima.upload.maximum_size=1310720
 hornbill32minima.upload.maximum_data_size=327680
-hornbill32minima.upload.wait_for_upload_port=true
+hornbill32minima.upload.flags=
+hornbill32minima.upload.extra_flags=
 
 hornbill32minima.serial.disableDTR=true
 hornbill32minima.serial.disableRTS=true
 
+hornbill32minima.build.tarch=xtensa
+hornbill32minima.build.bootloader_addr=0x1000
+hornbill32minima.build.target=esp32
 hornbill32minima.build.mcu=esp32
 hornbill32minima.build.core=esp32
 hornbill32minima.build.variant=hornbill32minima
@@ -1637,22 +11639,1099 @@ hornbill32minima.menu.UploadSpeed.460800.upload.speed=460800
 hornbill32minima.menu.UploadSpeed.512000.windows=512000
 hornbill32minima.menu.UploadSpeed.512000.upload.speed=512000
 
+hornbill32minima.menu.DebugLevel.none=None
+hornbill32minima.menu.DebugLevel.none.build.code_debug=0
+hornbill32minima.menu.DebugLevel.error=Error
+hornbill32minima.menu.DebugLevel.error.build.code_debug=1
+hornbill32minima.menu.DebugLevel.warn=Warn
+hornbill32minima.menu.DebugLevel.warn.build.code_debug=2
+hornbill32minima.menu.DebugLevel.info=Info
+hornbill32minima.menu.DebugLevel.info.build.code_debug=3
+hornbill32minima.menu.DebugLevel.debug=Debug
+hornbill32minima.menu.DebugLevel.debug.build.code_debug=4
+hornbill32minima.menu.DebugLevel.verbose=Verbose
+hornbill32minima.menu.DebugLevel.verbose.build.code_debug=5
+
+hornbill32minima.menu.EraseFlash.none=Disabled
+hornbill32minima.menu.EraseFlash.none.upload.erase_cmd=
+hornbill32minima.menu.EraseFlash.all=Enabled
+hornbill32minima.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+dfrobot_beetle_esp32c3.name=DFRobot Beetle ESP32-C3
+
+dfrobot_beetle_esp32c3.bootloader.tool=esptool_py
+dfrobot_beetle_esp32c3.bootloader.tool.default=esptool_py
+
+dfrobot_beetle_esp32c3.upload.tool=esptool_py
+dfrobot_beetle_esp32c3.upload.tool.default=esptool_py
+dfrobot_beetle_esp32c3.upload.tool.network=esp_ota
+
+dfrobot_beetle_esp32c3.upload.maximum_size=1310720
+dfrobot_beetle_esp32c3.upload.maximum_data_size=327680
+dfrobot_beetle_esp32c3.upload.flags=
+dfrobot_beetle_esp32c3.upload.extra_flags=
+dfrobot_beetle_esp32c3.upload.use_1200bps_touch=false
+dfrobot_beetle_esp32c3.upload.wait_for_upload_port=false
+
+dfrobot_beetle_esp32c3.serial.disableDTR=false
+dfrobot_beetle_esp32c3.serial.disableRTS=false
+
+dfrobot_beetle_esp32c3.build.tarch=riscv32
+dfrobot_beetle_esp32c3.build.target=esp
+dfrobot_beetle_esp32c3.build.mcu=esp32c3
+dfrobot_beetle_esp32c3.build.core=esp32
+dfrobot_beetle_esp32c3.build.variant=dfrobot_beetle_esp32c3
+#dfrobot_beetle_esp32c3.build.board=DFROBOT_BEETLE_ESP32_C3
+dfrobot_beetle_esp32c3.build.board=ESP32C3_DEV
+dfrobot_beetle_esp32c3.build.bootloader_addr=0x0
+
+dfrobot_beetle_esp32c3.build.cdc_on_boot=0
+dfrobot_beetle_esp32c3.build.f_cpu=160000000L
+dfrobot_beetle_esp32c3.build.flash_size=4MB
+dfrobot_beetle_esp32c3.build.flash_freq=80m
+dfrobot_beetle_esp32c3.build.flash_mode=qio
+dfrobot_beetle_esp32c3.build.boot=qio
+dfrobot_beetle_esp32c3.build.partitions=default
+dfrobot_beetle_esp32c3.build.defines=
+
+dfrobot_beetle_esp32c3.menu.CDCOnBoot.default=Disabled
+dfrobot_beetle_esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+dfrobot_beetle_esp32c3.menu.CDCOnBoot.cdc=Enabled
+dfrobot_beetle_esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+dfrobot_beetle_esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.default.build.partitions=default
+dfrobot_beetle_esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+dfrobot_beetle_esp32c3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+dfrobot_beetle_esp32c3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+dfrobot_beetle_esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal
+dfrobot_beetle_esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+dfrobot_beetle_esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+dfrobot_beetle_esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+dfrobot_beetle_esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+dfrobot_beetle_esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+dfrobot_beetle_esp32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+dfrobot_beetle_esp32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+dfrobot_beetle_esp32c3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.fatflash.build.partitions=ffat
+dfrobot_beetle_esp32c3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+dfrobot_beetle_esp32c3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+dfrobot_beetle_esp32c3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+dfrobot_beetle_esp32c3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+dfrobot_beetle_esp32c3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+dfrobot_beetle_esp32c3.menu.CPUFreq.160=160MHz (WiFi)
+dfrobot_beetle_esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L
+dfrobot_beetle_esp32c3.menu.CPUFreq.80=80MHz (WiFi)
+dfrobot_beetle_esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L
+dfrobot_beetle_esp32c3.menu.CPUFreq.40=40MHz
+dfrobot_beetle_esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L
+dfrobot_beetle_esp32c3.menu.CPUFreq.20=20MHz
+dfrobot_beetle_esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L
+dfrobot_beetle_esp32c3.menu.CPUFreq.10=10MHz
+dfrobot_beetle_esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+dfrobot_beetle_esp32c3.menu.FlashMode.qio=QIO
+dfrobot_beetle_esp32c3.menu.FlashMode.qio.build.flash_mode=dio
+dfrobot_beetle_esp32c3.menu.FlashMode.qio.build.boot=qio
+dfrobot_beetle_esp32c3.menu.FlashMode.dio=DIO
+dfrobot_beetle_esp32c3.menu.FlashMode.dio.build.flash_mode=dio
+dfrobot_beetle_esp32c3.menu.FlashMode.dio.build.boot=dio
+
+dfrobot_beetle_esp32c3.menu.FlashFreq.80=80MHz
+dfrobot_beetle_esp32c3.menu.FlashFreq.80.build.flash_freq=80m
+dfrobot_beetle_esp32c3.menu.FlashFreq.40=40MHz
+dfrobot_beetle_esp32c3.menu.FlashFreq.40.build.flash_freq=40m
+
+dfrobot_beetle_esp32c3.menu.FlashSize.4M=4MB (32Mb)
+dfrobot_beetle_esp32c3.menu.FlashSize.4M.build.flash_size=4MB
+
+dfrobot_beetle_esp32c3.menu.UploadSpeed.921600=921600
+dfrobot_beetle_esp32c3.menu.UploadSpeed.921600.upload.speed=921600
+dfrobot_beetle_esp32c3.menu.UploadSpeed.115200=115200
+dfrobot_beetle_esp32c3.menu.UploadSpeed.115200.upload.speed=115200
+dfrobot_beetle_esp32c3.menu.UploadSpeed.256000.windows=256000
+dfrobot_beetle_esp32c3.menu.UploadSpeed.256000.upload.speed=256000
+dfrobot_beetle_esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000
+dfrobot_beetle_esp32c3.menu.UploadSpeed.230400=230400
+dfrobot_beetle_esp32c3.menu.UploadSpeed.230400.upload.speed=230400
+dfrobot_beetle_esp32c3.menu.UploadSpeed.460800.linux=460800
+dfrobot_beetle_esp32c3.menu.UploadSpeed.460800.macosx=460800
+dfrobot_beetle_esp32c3.menu.UploadSpeed.460800.upload.speed=460800
+dfrobot_beetle_esp32c3.menu.UploadSpeed.512000.windows=512000
+dfrobot_beetle_esp32c3.menu.UploadSpeed.512000.upload.speed=512000
+
+dfrobot_beetle_esp32c3.menu.DebugLevel.none=None
+dfrobot_beetle_esp32c3.menu.DebugLevel.none.build.code_debug=0
+dfrobot_beetle_esp32c3.menu.DebugLevel.error=Error
+dfrobot_beetle_esp32c3.menu.DebugLevel.error.build.code_debug=1
+dfrobot_beetle_esp32c3.menu.DebugLevel.warn=Warn
+dfrobot_beetle_esp32c3.menu.DebugLevel.warn.build.code_debug=2
+dfrobot_beetle_esp32c3.menu.DebugLevel.info=Info
+dfrobot_beetle_esp32c3.menu.DebugLevel.info.build.code_debug=3
+dfrobot_beetle_esp32c3.menu.DebugLevel.debug=Debug
+dfrobot_beetle_esp32c3.menu.DebugLevel.debug.build.code_debug=4
+dfrobot_beetle_esp32c3.menu.DebugLevel.verbose=Verbose
+dfrobot_beetle_esp32c3.menu.DebugLevel.verbose.build.code_debug=5
+
+dfrobot_beetle_esp32c3.menu.EraseFlash.none=Disabled
+dfrobot_beetle_esp32c3.menu.EraseFlash.none.upload.erase_cmd=
+dfrobot_beetle_esp32c3.menu.EraseFlash.all=Enabled
+dfrobot_beetle_esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+dfrobot_beetle_esp32c6.name=DFRobot Beetle ESP32-C6
+
+dfrobot_beetle_esp32c6.bootloader.tool=esptool_py
+dfrobot_beetle_esp32c6.bootloader.tool.default=esptool_py
+
+dfrobot_beetle_esp32c6.upload.tool=esptool_py
+dfrobot_beetle_esp32c6.upload.tool.default=esptool_py
+dfrobot_beetle_esp32c6.upload.tool.network=esp_ota
+
+dfrobot_beetle_esp32c6.upload.maximum_size=1310720
+dfrobot_beetle_esp32c6.upload.maximum_data_size=327680
+dfrobot_beetle_esp32c6.upload.flags=
+dfrobot_beetle_esp32c6.upload.extra_flags=
+dfrobot_beetle_esp32c6.upload.use_1200bps_touch=false
+dfrobot_beetle_esp32c6.upload.wait_for_upload_port=false
+
+dfrobot_beetle_esp32c6.serial.disableDTR=false
+dfrobot_beetle_esp32c6.serial.disableRTS=false
+
+dfrobot_beetle_esp32c6.build.tarch=riscv32
+dfrobot_beetle_esp32c6.build.target=esp
+dfrobot_beetle_esp32c6.build.mcu=esp32c6
+dfrobot_beetle_esp32c6.build.core=esp32
+dfrobot_beetle_esp32c6.build.variant=dfrobot_beetle_esp32c6
+dfrobot_beetle_esp32c6.build.board=DFROBOT_BEETLE_ESP32C6
+dfrobot_beetle_esp32c6.build.bootloader_addr=0x0
+
+dfrobot_beetle_esp32c6.build.cdc_on_boot=0
+dfrobot_beetle_esp32c6.build.f_cpu=160000000L
+dfrobot_beetle_esp32c6.build.flash_size=4MB
+dfrobot_beetle_esp32c6.build.flash_freq=80m
+dfrobot_beetle_esp32c6.build.flash_mode=qio
+dfrobot_beetle_esp32c6.build.boot=qio
+dfrobot_beetle_esp32c6.build.partitions=default
+dfrobot_beetle_esp32c6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.default=Disabled
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.external=FTDI Adapter
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+dfrobot_beetle_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+dfrobot_beetle_esp32c6.menu.CDCOnBoot.default=Disabled
+dfrobot_beetle_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0
+dfrobot_beetle_esp32c6.menu.CDCOnBoot.cdc=Enabled
+dfrobot_beetle_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+dfrobot_beetle_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+dfrobot_beetle_esp32c6.menu.PartitionScheme.default.build.partitions=default
+dfrobot_beetle_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+dfrobot_beetle_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+dfrobot_beetle_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+dfrobot_beetle_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal
+dfrobot_beetle_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+dfrobot_beetle_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+dfrobot_beetle_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+dfrobot_beetle_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+dfrobot_beetle_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+dfrobot_beetle_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+dfrobot_beetle_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+dfrobot_beetle_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+dfrobot_beetle_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+dfrobot_beetle_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB
+dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+dfrobot_beetle_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+dfrobot_beetle_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+dfrobot_beetle_esp32c6.menu.PartitionScheme.custom=Custom
+dfrobot_beetle_esp32c6.menu.PartitionScheme.custom.build.partitions=
+dfrobot_beetle_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+dfrobot_beetle_esp32c6.menu.CPUFreq.160=160MHz (WiFi)
+dfrobot_beetle_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L
+dfrobot_beetle_esp32c6.menu.CPUFreq.80=80MHz (WiFi)
+dfrobot_beetle_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L
+dfrobot_beetle_esp32c6.menu.CPUFreq.40=40MHz
+dfrobot_beetle_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L
+dfrobot_beetle_esp32c6.menu.CPUFreq.20=20MHz
+dfrobot_beetle_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L
+dfrobot_beetle_esp32c6.menu.CPUFreq.10=10MHz
+dfrobot_beetle_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+dfrobot_beetle_esp32c6.menu.FlashMode.qio=QIO
+dfrobot_beetle_esp32c6.menu.FlashMode.qio.build.flash_mode=dio
+dfrobot_beetle_esp32c6.menu.FlashMode.qio.build.boot=qio
+dfrobot_beetle_esp32c6.menu.FlashMode.dio=DIO
+dfrobot_beetle_esp32c6.menu.FlashMode.dio.build.flash_mode=dio
+dfrobot_beetle_esp32c6.menu.FlashMode.dio.build.boot=dio
+
+dfrobot_beetle_esp32c6.menu.FlashFreq.80=80MHz
+dfrobot_beetle_esp32c6.menu.FlashFreq.80.build.flash_freq=80m
+dfrobot_beetle_esp32c6.menu.FlashFreq.40=40MHz
+dfrobot_beetle_esp32c6.menu.FlashFreq.40.build.flash_freq=40m
+
+dfrobot_beetle_esp32c6.menu.FlashSize.4M=4MB (32Mb)
+dfrobot_beetle_esp32c6.menu.FlashSize.4M.build.flash_size=4MB
+
+dfrobot_beetle_esp32c6.menu.UploadSpeed.921600=921600
+dfrobot_beetle_esp32c6.menu.UploadSpeed.921600.upload.speed=921600
+dfrobot_beetle_esp32c6.menu.UploadSpeed.115200=115200
+dfrobot_beetle_esp32c6.menu.UploadSpeed.115200.upload.speed=115200
+dfrobot_beetle_esp32c6.menu.UploadSpeed.256000.windows=256000
+dfrobot_beetle_esp32c6.menu.UploadSpeed.256000.upload.speed=256000
+dfrobot_beetle_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000
+dfrobot_beetle_esp32c6.menu.UploadSpeed.230400=230400
+dfrobot_beetle_esp32c6.menu.UploadSpeed.230400.upload.speed=230400
+dfrobot_beetle_esp32c6.menu.UploadSpeed.460800.linux=460800
+dfrobot_beetle_esp32c6.menu.UploadSpeed.460800.macosx=460800
+dfrobot_beetle_esp32c6.menu.UploadSpeed.460800.upload.speed=460800
+dfrobot_beetle_esp32c6.menu.UploadSpeed.512000.windows=512000
+dfrobot_beetle_esp32c6.menu.UploadSpeed.512000.upload.speed=512000
+
+dfrobot_beetle_esp32c6.menu.DebugLevel.none=None
+dfrobot_beetle_esp32c6.menu.DebugLevel.none.build.code_debug=0
+dfrobot_beetle_esp32c6.menu.DebugLevel.error=Error
+dfrobot_beetle_esp32c6.menu.DebugLevel.error.build.code_debug=1
+dfrobot_beetle_esp32c6.menu.DebugLevel.warn=Warn
+dfrobot_beetle_esp32c6.menu.DebugLevel.warn.build.code_debug=2
+dfrobot_beetle_esp32c6.menu.DebugLevel.info=Info
+dfrobot_beetle_esp32c6.menu.DebugLevel.info.build.code_debug=3
+dfrobot_beetle_esp32c6.menu.DebugLevel.debug=Debug
+dfrobot_beetle_esp32c6.menu.DebugLevel.debug.build.code_debug=4
+dfrobot_beetle_esp32c6.menu.DebugLevel.verbose=Verbose
+dfrobot_beetle_esp32c6.menu.DebugLevel.verbose.build.code_debug=5
+
+dfrobot_beetle_esp32c6.menu.EraseFlash.none=Disabled
+dfrobot_beetle_esp32c6.menu.EraseFlash.none.upload.erase_cmd=
+dfrobot_beetle_esp32c6.menu.EraseFlash.all=Enabled
+dfrobot_beetle_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+dfrobot_beetle_esp32c6.menu.ZigbeeMode.default=Disabled
+dfrobot_beetle_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode=
+dfrobot_beetle_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs=
+dfrobot_beetle_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+dfrobot_beetle_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+dfrobot_beetle_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+dfrobot_beetle_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+dfrobot_beetle_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+dfrobot_beetle_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+dfrobot_firebeetle2_esp32e.name=FireBeetle 2 ESP32-E
+
+dfrobot_firebeetle2_esp32e.upload.tool=esptool_py
+dfrobot_firebeetle2_esp32e.upload.tool.default=esptool_py
+dfrobot_firebeetle2_esp32e.upload.maximum_size=1310720
+dfrobot_firebeetle2_esp32e.upload.maximum_data_size=327680
+dfrobot_firebeetle2_esp32e.upload.flags=
+dfrobot_firebeetle2_esp32e.upload.extra_flags=
+
+dfrobot_firebeetle2_esp32e.serial.disableDTR=true
+dfrobot_firebeetle2_esp32e.serial.disableRTS=true
+
+dfrobot_firebeetle2_esp32e.build.tarch=xtensa
+dfrobot_firebeetle2_esp32e.build.bootloader_addr=0x1000
+dfrobot_firebeetle2_esp32e.build.target=esp32
+dfrobot_firebeetle2_esp32e.build.mcu=esp32
+dfrobot_firebeetle2_esp32e.build.core=esp32
+dfrobot_firebeetle2_esp32e.build.variant=dfrobot_firebeetle2_esp32e
+dfrobot_firebeetle2_esp32e.build.board=DFROBOT_FIREBEETLE_2_ESP32E
+
+dfrobot_firebeetle2_esp32e.build.f_cpu=240000000L
+dfrobot_firebeetle2_esp32e.build.flash_size=4MB
+dfrobot_firebeetle2_esp32e.build.flash_freq=40m
+dfrobot_firebeetle2_esp32e.build.flash_mode=dio
+dfrobot_firebeetle2_esp32e.build.boot=dio
+dfrobot_firebeetle2_esp32e.build.partitions=default
+dfrobot_firebeetle2_esp32e.build.defines=
+dfrobot_firebeetle2_esp32e.build.loop_core=
+dfrobot_firebeetle2_esp32e.build.event_core=
+
+dfrobot_firebeetle2_esp32e.menu.PSRAM.disabled=Disabled
+dfrobot_firebeetle2_esp32e.menu.PSRAM.disabled.build.defines=
+dfrobot_firebeetle2_esp32e.menu.PSRAM.disabled.build.extra_libs=
+dfrobot_firebeetle2_esp32e.menu.PSRAM.enabled=Enabled
+dfrobot_firebeetle2_esp32e.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+dfrobot_firebeetle2_esp32e.menu.PSRAM.enabled.build.extra_libs=
+
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default.build.partitions=default
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.minimal.build.partitions=minimal
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.no_ota.build.partitions=no_ota
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.huge_app.build.partitions=huge_app
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.fatflash.build.partitions=ffat
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker=RainMaker 4MB
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+dfrobot_firebeetle2_esp32e.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.240=240MHz (WiFi/BT)
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.240.build.f_cpu=240000000L
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.160=160MHz (WiFi/BT)
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.160.build.f_cpu=160000000L
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.80=80MHz (WiFi/BT)
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.80.build.f_cpu=80000000L
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.40=40MHz (40MHz XTAL)
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.40.build.f_cpu=40000000L
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.26=26MHz (26MHz XTAL)
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.26.build.f_cpu=26000000L
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.20=20MHz (40MHz XTAL)
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.20.build.f_cpu=20000000L
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.13=13MHz (26MHz XTAL)
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.13.build.f_cpu=13000000L
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.10=10MHz (40MHz XTAL)
+dfrobot_firebeetle2_esp32e.menu.CPUFreq.10.build.f_cpu=10000000L
+
+dfrobot_firebeetle2_esp32e.menu.FlashMode.qio=QIO
+dfrobot_firebeetle2_esp32e.menu.FlashMode.qio.build.flash_mode=dio
+dfrobot_firebeetle2_esp32e.menu.FlashMode.qio.build.boot=qio
+dfrobot_firebeetle2_esp32e.menu.FlashMode.dio=DIO
+dfrobot_firebeetle2_esp32e.menu.FlashMode.dio.build.flash_mode=dio
+dfrobot_firebeetle2_esp32e.menu.FlashMode.dio.build.boot=dio
+
+dfrobot_firebeetle2_esp32e.menu.FlashFreq.80=80MHz
+dfrobot_firebeetle2_esp32e.menu.FlashFreq.80.build.flash_freq=80m
+dfrobot_firebeetle2_esp32e.menu.FlashFreq.40=40MHz
+dfrobot_firebeetle2_esp32e.menu.FlashFreq.40.build.flash_freq=40m
+
+dfrobot_firebeetle2_esp32e.menu.FlashSize.4M=4MB (32Mb)
+dfrobot_firebeetle2_esp32e.menu.FlashSize.4M.build.flash_size=4MB
+dfrobot_firebeetle2_esp32e.menu.FlashSize.8M=8MB (64Mb)
+dfrobot_firebeetle2_esp32e.menu.FlashSize.8M.build.flash_size=8MB
+dfrobot_firebeetle2_esp32e.menu.FlashSize.2M=2MB (16Mb)
+dfrobot_firebeetle2_esp32e.menu.FlashSize.2M.build.flash_size=2MB
+dfrobot_firebeetle2_esp32e.menu.FlashSize.16M=16MB (128Mb)
+dfrobot_firebeetle2_esp32e.menu.FlashSize.16M.build.flash_size=16MB
+
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.921600=921600
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.921600.upload.speed=921600
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.115200=115200
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.115200.upload.speed=115200
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.256000.windows=256000
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.256000.upload.speed=256000
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.230400.windows.upload.speed=256000
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.230400=230400
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.230400.upload.speed=230400
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.460800.linux=460800
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.460800.macosx=460800
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.460800.upload.speed=460800
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.512000.windows=512000
+dfrobot_firebeetle2_esp32e.menu.UploadSpeed.512000.upload.speed=512000
+
+dfrobot_firebeetle2_esp32e.menu.LoopCore.1=Core 1
+dfrobot_firebeetle2_esp32e.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+dfrobot_firebeetle2_esp32e.menu.LoopCore.0=Core 0
+dfrobot_firebeetle2_esp32e.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+dfrobot_firebeetle2_esp32e.menu.EventsCore.1=Core 1
+dfrobot_firebeetle2_esp32e.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+dfrobot_firebeetle2_esp32e.menu.EventsCore.0=Core 0
+dfrobot_firebeetle2_esp32e.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.none=None
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.none.build.code_debug=0
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.error=Error
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.error.build.code_debug=1
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.warn=Warn
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.warn.build.code_debug=2
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.info=Info
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.info.build.code_debug=3
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.debug=Debug
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.debug.build.code_debug=4
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.verbose=Verbose
+dfrobot_firebeetle2_esp32e.menu.DebugLevel.verbose.build.code_debug=5
+
+dfrobot_firebeetle2_esp32e.menu.EraseFlash.none=Disabled
+dfrobot_firebeetle2_esp32e.menu.EraseFlash.none.upload.erase_cmd=
+dfrobot_firebeetle2_esp32e.menu.EraseFlash.all=Enabled
+dfrobot_firebeetle2_esp32e.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+dfrobot_firebeetle2_esp32s3.name=DFRobot Firebeetle 2 ESP32-S3
+
+dfrobot_firebeetle2_esp32s3.bootloader.tool=esptool_py
+dfrobot_firebeetle2_esp32s3.bootloader.tool.default=esptool_py
+
+dfrobot_firebeetle2_esp32s3.upload.tool=esptool_py
+dfrobot_firebeetle2_esp32s3.upload.tool.default=esptool_py
+dfrobot_firebeetle2_esp32s3.upload.tool.network=esp_ota
+
+dfrobot_firebeetle2_esp32s3.upload.maximum_size=1310720
+dfrobot_firebeetle2_esp32s3.upload.maximum_data_size=327680
+dfrobot_firebeetle2_esp32s3.upload.flags=
+dfrobot_firebeetle2_esp32s3.upload.extra_flags=
+dfrobot_firebeetle2_esp32s3.upload.use_1200bps_touch=false
+dfrobot_firebeetle2_esp32s3.upload.wait_for_upload_port=false
+
+dfrobot_firebeetle2_esp32s3.serial.disableDTR=false
+dfrobot_firebeetle2_esp32s3.serial.disableRTS=false
+
+dfrobot_firebeetle2_esp32s3.build.tarch=xtensa
+dfrobot_firebeetle2_esp32s3.build.bootloader_addr=0x0
+dfrobot_firebeetle2_esp32s3.build.target=esp32s3
+dfrobot_firebeetle2_esp32s3.build.mcu=esp32s3
+dfrobot_firebeetle2_esp32s3.build.core=esp32
+dfrobot_firebeetle2_esp32s3.build.variant=dfrobot_firebeetle2_esp32s3
+dfrobot_firebeetle2_esp32s3.build.board=ESP32S3_DEV
+#dfrobot_firebeetle2_esp32s3.build.board=DFROBOT_FIREBEETLE_2_ESP32S3
+
+dfrobot_firebeetle2_esp32s3.build.usb_mode=1
+dfrobot_firebeetle2_esp32s3.build.cdc_on_boot=0
+dfrobot_firebeetle2_esp32s3.build.msc_on_boot=0
+dfrobot_firebeetle2_esp32s3.build.dfu_on_boot=0
+dfrobot_firebeetle2_esp32s3.build.f_cpu=240000000L
+dfrobot_firebeetle2_esp32s3.build.flash_size=4MB
+dfrobot_firebeetle2_esp32s3.build.flash_freq=80m
+dfrobot_firebeetle2_esp32s3.build.flash_mode=dio
+dfrobot_firebeetle2_esp32s3.build.boot=qio
+dfrobot_firebeetle2_esp32s3.build.boot_freq=80m
+dfrobot_firebeetle2_esp32s3.build.partitions=default
+dfrobot_firebeetle2_esp32s3.build.defines=
+dfrobot_firebeetle2_esp32s3.build.loop_core=
+dfrobot_firebeetle2_esp32s3.build.event_core=
+dfrobot_firebeetle2_esp32s3.build.flash_type=qio
+dfrobot_firebeetle2_esp32s3.build.psram_type=qspi
+dfrobot_firebeetle2_esp32s3.build.memory_type={build.flash_type}_{build.psram_type}
+
+dfrobot_firebeetle2_esp32s3.menu.PSRAM.disabled=Disabled
+dfrobot_firebeetle2_esp32s3.menu.PSRAM.disabled.build.defines=
+dfrobot_firebeetle2_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi
+dfrobot_firebeetle2_esp32s3.menu.PSRAM.enabled=QSPI PSRAM
+dfrobot_firebeetle2_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+dfrobot_firebeetle2_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi
+dfrobot_firebeetle2_esp32s3.menu.PSRAM.opi=OPI PSRAM
+dfrobot_firebeetle2_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+dfrobot_firebeetle2_esp32s3.menu.PSRAM.opi.build.psram_type=opi
+
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio=QIO 80MHz
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.boot=qio
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio.build.flash_type=qio
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120=QIO 120MHz
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.boot=qio
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.qio120.build.flash_type=qio
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio=DIO 80MHz
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.boot=dio
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.dio.build.flash_type=qio
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi=OPI 80MHz
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.boot=opi
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+dfrobot_firebeetle2_esp32s3.menu.FlashMode.opi.build.flash_type=opi
+
+dfrobot_firebeetle2_esp32s3.menu.FlashSize.4M=4MB (32Mb)
+dfrobot_firebeetle2_esp32s3.menu.FlashSize.4M.build.flash_size=4MB
+dfrobot_firebeetle2_esp32s3.menu.FlashSize.8M=8MB (64Mb)
+dfrobot_firebeetle2_esp32s3.menu.FlashSize.8M.build.flash_size=8MB
+dfrobot_firebeetle2_esp32s3.menu.FlashSize.16M=16MB (128Mb)
+dfrobot_firebeetle2_esp32s3.menu.FlashSize.16M.build.flash_size=16MB
+#dfrobot_firebeetle2_esp32s3.menu.FlashSize.32M=32MB (256Mb)
+#dfrobot_firebeetle2_esp32s3.menu.FlashSize.32M.build.flash_size=32MB
+
+dfrobot_firebeetle2_esp32s3.menu.LoopCore.1=Core 1
+dfrobot_firebeetle2_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+dfrobot_firebeetle2_esp32s3.menu.LoopCore.0=Core 0
+dfrobot_firebeetle2_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+dfrobot_firebeetle2_esp32s3.menu.EventsCore.1=Core 1
+dfrobot_firebeetle2_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+dfrobot_firebeetle2_esp32s3.menu.EventsCore.0=Core 0
+dfrobot_firebeetle2_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+dfrobot_firebeetle2_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+dfrobot_firebeetle2_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+dfrobot_firebeetle2_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+dfrobot_firebeetle2_esp32s3.menu.USBMode.default.build.usb_mode=0
+
+dfrobot_firebeetle2_esp32s3.menu.CDCOnBoot.default=Disabled
+dfrobot_firebeetle2_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+dfrobot_firebeetle2_esp32s3.menu.CDCOnBoot.cdc=Enabled
+dfrobot_firebeetle2_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+dfrobot_firebeetle2_esp32s3.menu.MSCOnBoot.default=Disabled
+dfrobot_firebeetle2_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+dfrobot_firebeetle2_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+dfrobot_firebeetle2_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+dfrobot_firebeetle2_esp32s3.menu.DFUOnBoot.default=Disabled
+dfrobot_firebeetle2_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+dfrobot_firebeetle2_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+dfrobot_firebeetle2_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+dfrobot_firebeetle2_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+dfrobot_firebeetle2_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+dfrobot_firebeetle2_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+dfrobot_firebeetle2_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+dfrobot_firebeetle2_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+dfrobot_firebeetle2_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default.build.partitions=default
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+dfrobot_firebeetle2_esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.40=40MHz
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.20=20MHz
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.10=10MHz
+dfrobot_firebeetle2_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.921600=921600
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.115200=115200
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.256000.windows=256000
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.230400=230400
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.460800.linux=460800
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.460800.macosx=460800
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.512000.windows=512000
+dfrobot_firebeetle2_esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.none=None
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.none.build.code_debug=0
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.error=Error
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.error.build.code_debug=1
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.warn=Warn
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.warn.build.code_debug=2
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.info=Info
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.info.build.code_debug=3
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.debug=Debug
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.debug.build.code_debug=4
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.verbose=Verbose
+dfrobot_firebeetle2_esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+dfrobot_firebeetle2_esp32s3.menu.EraseFlash.none=Disabled
+dfrobot_firebeetle2_esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+dfrobot_firebeetle2_esp32s3.menu.EraseFlash.all=Enabled
+dfrobot_firebeetle2_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+dfrobot_firebeetle2_esp32c6.name=DFRobot FireBeetle 2 ESP32-C6
+
+dfrobot_firebeetle2_esp32c6.bootloader.tool=esptool_py
+dfrobot_firebeetle2_esp32c6.bootloader.tool.default=esptool_py
+
+dfrobot_firebeetle2_esp32c6.upload.tool=esptool_py
+dfrobot_firebeetle2_esp32c6.upload.tool.default=esptool_py
+dfrobot_firebeetle2_esp32c6.upload.tool.network=esp_ota
+
+dfrobot_firebeetle2_esp32c6.upload.maximum_size=1310720
+dfrobot_firebeetle2_esp32c6.upload.maximum_data_size=327680
+dfrobot_firebeetle2_esp32c6.upload.flags=
+dfrobot_firebeetle2_esp32c6.upload.extra_flags=
+dfrobot_firebeetle2_esp32c6.upload.use_1200bps_touch=false
+dfrobot_firebeetle2_esp32c6.upload.wait_for_upload_port=false
+
+dfrobot_firebeetle2_esp32c6.serial.disableDTR=false
+dfrobot_firebeetle2_esp32c6.serial.disableRTS=false
+
+dfrobot_firebeetle2_esp32c6.build.tarch=riscv32
+dfrobot_firebeetle2_esp32c6.build.target=esp
+dfrobot_firebeetle2_esp32c6.build.mcu=esp32c6
+dfrobot_firebeetle2_esp32c6.build.core=esp32
+dfrobot_firebeetle2_esp32c6.build.variant=dfrobot_firebeetle2_esp32c6
+dfrobot_firebeetle2_esp32c6.build.board=DFROBOT_FIREBEETLE_2_ESP32C6
+dfrobot_firebeetle2_esp32c6.build.bootloader_addr=0x0
+
+dfrobot_firebeetle2_esp32c6.build.cdc_on_boot=0
+dfrobot_firebeetle2_esp32c6.build.f_cpu=160000000L
+dfrobot_firebeetle2_esp32c6.build.flash_size=4MB
+dfrobot_firebeetle2_esp32c6.build.flash_freq=80m
+dfrobot_firebeetle2_esp32c6.build.flash_mode=qio
+dfrobot_firebeetle2_esp32c6.build.boot=qio
+dfrobot_firebeetle2_esp32c6.build.partitions=default
+dfrobot_firebeetle2_esp32c6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.default=Disabled
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.external=FTDI Adapter
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+dfrobot_firebeetle2_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+dfrobot_firebeetle2_esp32c6.menu.CDCOnBoot.default=Disabled
+dfrobot_firebeetle2_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0
+dfrobot_firebeetle2_esp32c6.menu.CDCOnBoot.cdc=Enabled
+dfrobot_firebeetle2_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.default.build.partitions=default
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.custom=Custom
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.custom.build.partitions=
+dfrobot_firebeetle2_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.160=160MHz (WiFi)
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.80=80MHz (WiFi)
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.40=40MHz
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.20=20MHz
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.10=10MHz
+dfrobot_firebeetle2_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+dfrobot_firebeetle2_esp32c6.menu.FlashMode.qio=QIO
+dfrobot_firebeetle2_esp32c6.menu.FlashMode.qio.build.flash_mode=dio
+dfrobot_firebeetle2_esp32c6.menu.FlashMode.qio.build.boot=qio
+dfrobot_firebeetle2_esp32c6.menu.FlashMode.dio=DIO
+dfrobot_firebeetle2_esp32c6.menu.FlashMode.dio.build.flash_mode=dio
+dfrobot_firebeetle2_esp32c6.menu.FlashMode.dio.build.boot=dio
+
+dfrobot_firebeetle2_esp32c6.menu.FlashFreq.80=80MHz
+dfrobot_firebeetle2_esp32c6.menu.FlashFreq.80.build.flash_freq=80m
+dfrobot_firebeetle2_esp32c6.menu.FlashFreq.40=40MHz
+dfrobot_firebeetle2_esp32c6.menu.FlashFreq.40.build.flash_freq=40m
+
+dfrobot_firebeetle2_esp32c6.menu.FlashSize.4M=4MB (32Mb)
+dfrobot_firebeetle2_esp32c6.menu.FlashSize.4M.build.flash_size=4MB
+
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.921600=921600
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.921600.upload.speed=921600
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.115200=115200
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.115200.upload.speed=115200
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.256000.windows=256000
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.256000.upload.speed=256000
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.230400=230400
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.230400.upload.speed=230400
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.460800.linux=460800
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.460800.macosx=460800
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.460800.upload.speed=460800
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.512000.windows=512000
+dfrobot_firebeetle2_esp32c6.menu.UploadSpeed.512000.upload.speed=512000
+
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.none=None
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.none.build.code_debug=0
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.error=Error
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.error.build.code_debug=1
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.warn=Warn
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.warn.build.code_debug=2
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.info=Info
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.info.build.code_debug=3
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.debug=Debug
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.debug.build.code_debug=4
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.verbose=Verbose
+dfrobot_firebeetle2_esp32c6.menu.DebugLevel.verbose.build.code_debug=5
+
+dfrobot_firebeetle2_esp32c6.menu.EraseFlash.none=Disabled
+dfrobot_firebeetle2_esp32c6.menu.EraseFlash.none.upload.erase_cmd=
+dfrobot_firebeetle2_esp32c6.menu.EraseFlash.all=Enabled
+dfrobot_firebeetle2_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.default=Disabled
+dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode=
+dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs=
+dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+dfrobot_firebeetle2_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+##############################################################
+
+# dfrobot Romeo ESP32-S3
+dfrobot_romeo_esp32s3.name=DFRobot Romeo ESP32-S3
+
+dfrobot_romeo_esp32s3.bootloader.tool=esptool_py
+dfrobot_romeo_esp32s3.bootloader.tool.default=esptool_py
+
+dfrobot_romeo_esp32s3.upload.tool=esptool_py
+dfrobot_romeo_esp32s3.upload.tool.default=esptool_py
+dfrobot_romeo_esp32s3.upload.tool.network=esp_ota
+
+dfrobot_romeo_esp32s3.upload.maximum_size=1310720
+dfrobot_romeo_esp32s3.upload.maximum_data_size=327680
+dfrobot_romeo_esp32s3.upload.flags=
+dfrobot_romeo_esp32s3.upload.extra_flags=
+dfrobot_romeo_esp32s3.upload.use_1200bps_touch=false
+dfrobot_romeo_esp32s3.upload.wait_for_upload_port=false
+
+dfrobot_romeo_esp32s3.serial.disableDTR=false
+dfrobot_romeo_esp32s3.serial.disableRTS=false
+
+dfrobot_romeo_esp32s3.build.tarch=xtensa
+dfrobot_romeo_esp32s3.build.bootloader_addr=0x0
+dfrobot_romeo_esp32s3.build.target=esp32s3
+dfrobot_romeo_esp32s3.build.mcu=esp32s3
+dfrobot_romeo_esp32s3.build.core=esp32
+dfrobot_romeo_esp32s3.build.variant=dfrobot_romeo_esp32s3
+dfrobot_romeo_esp32s3.build.board=DFROBOT_ROMEO_ESP32S3
+
+
+dfrobot_romeo_esp32s3.build.usb_mode=1
+dfrobot_romeo_esp32s3.build.cdc_on_boot=0
+dfrobot_romeo_esp32s3.build.msc_on_boot=0
+dfrobot_romeo_esp32s3.build.dfu_on_boot=0
+dfrobot_romeo_esp32s3.build.f_cpu=240000000L
+dfrobot_romeo_esp32s3.build.flash_size=16MB
+dfrobot_romeo_esp32s3.build.flash_freq=80m
+dfrobot_romeo_esp32s3.build.flash_mode=qio
+dfrobot_romeo_esp32s3.build.boot=qio
+dfrobot_romeo_esp32s3.build.boot_freq=80m
+dfrobot_romeo_esp32s3.build.partitions=default
+dfrobot_romeo_esp32s3.build.defines=
+dfrobot_romeo_esp32s3.build.loop_core=
+dfrobot_romeo_esp32s3.build.event_core=
+dfrobot_romeo_esp32s3.build.flash_type=qio
+dfrobot_romeo_esp32s3.build.psram_type=qspi
+dfrobot_romeo_esp32s3.build.memory_type={build.flash_type}_{build.psram_type}
+
+dfrobot_romeo_esp32s3.menu.PSRAM.opi=OPI PSRAM
+dfrobot_romeo_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+dfrobot_romeo_esp32s3.menu.PSRAM.opi.build.psram_type=opi
+dfrobot_romeo_esp32s3.menu.PSRAM.disabled=Disabled
+dfrobot_romeo_esp32s3.menu.PSRAM.disabled.build.defines=
+dfrobot_romeo_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi
+dfrobot_romeo_esp32s3.menu.PSRAM.enabled=QSPI PSRAM
+dfrobot_romeo_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+dfrobot_romeo_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi
+
+
+dfrobot_romeo_esp32s3.menu.FlashMode.qio=QIO 80MHz
+dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.boot=qio
+dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+dfrobot_romeo_esp32s3.menu.FlashMode.qio.build.flash_type=qio
+dfrobot_romeo_esp32s3.menu.FlashMode.qio120=QIO 120MHz
+dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.boot=qio
+dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+dfrobot_romeo_esp32s3.menu.FlashMode.qio120.build.flash_type=qio
+dfrobot_romeo_esp32s3.menu.FlashMode.dio=DIO 80MHz
+dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.boot=dio
+dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+dfrobot_romeo_esp32s3.menu.FlashMode.dio.build.flash_type=qio
+dfrobot_romeo_esp32s3.menu.FlashMode.opi=OPI 80MHz
+dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.boot=opi
+dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+dfrobot_romeo_esp32s3.menu.FlashMode.opi.build.flash_type=opi
+
+dfrobot_romeo_esp32s3.menu.FlashSize.16M=16MB (128Mb)
+dfrobot_romeo_esp32s3.menu.FlashSize.16M.build.flash_size=16MB
+
+
+dfrobot_romeo_esp32s3.menu.LoopCore.1=Core 1
+dfrobot_romeo_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+dfrobot_romeo_esp32s3.menu.LoopCore.0=Core 0
+dfrobot_romeo_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+dfrobot_romeo_esp32s3.menu.EventsCore.1=Core 1
+dfrobot_romeo_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+dfrobot_romeo_esp32s3.menu.EventsCore.0=Core 0
+dfrobot_romeo_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+dfrobot_romeo_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+dfrobot_romeo_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+dfrobot_romeo_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+dfrobot_romeo_esp32s3.menu.USBMode.default.build.usb_mode=0
+
+dfrobot_romeo_esp32s3.menu.CDCOnBoot.cdc=Enabled
+dfrobot_romeo_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+dfrobot_romeo_esp32s3.menu.CDCOnBoot.default=Disabled
+dfrobot_romeo_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+
+dfrobot_romeo_esp32s3.menu.MSCOnBoot.default=Disabled
+dfrobot_romeo_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+dfrobot_romeo_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+dfrobot_romeo_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+dfrobot_romeo_esp32s3.menu.DFUOnBoot.default=Disabled
+dfrobot_romeo_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+dfrobot_romeo_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+dfrobot_romeo_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+dfrobot_romeo_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+dfrobot_romeo_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+dfrobot_romeo_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+dfrobot_romeo_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+dfrobot_romeo_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+dfrobot_romeo_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+dfrobot_romeo_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+dfrobot_romeo_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+dfrobot_romeo_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+dfrobot_romeo_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+dfrobot_romeo_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+dfrobot_romeo_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+dfrobot_romeo_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+dfrobot_romeo_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal
+dfrobot_romeo_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+dfrobot_romeo_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+dfrobot_romeo_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+dfrobot_romeo_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+dfrobot_romeo_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+dfrobot_romeo_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+dfrobot_romeo_esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+dfrobot_romeo_esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+dfrobot_romeo_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+dfrobot_romeo_esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+dfrobot_romeo_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+dfrobot_romeo_esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+dfrobot_romeo_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+dfrobot_romeo_esp32s3.menu.CPUFreq.40=40MHz
+dfrobot_romeo_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+dfrobot_romeo_esp32s3.menu.CPUFreq.20=20MHz
+dfrobot_romeo_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+dfrobot_romeo_esp32s3.menu.CPUFreq.10=10MHz
+dfrobot_romeo_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+dfrobot_romeo_esp32s3.menu.UploadSpeed.921600=921600
+dfrobot_romeo_esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+dfrobot_romeo_esp32s3.menu.UploadSpeed.115200=115200
+dfrobot_romeo_esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+dfrobot_romeo_esp32s3.menu.UploadSpeed.256000.windows=256000
+dfrobot_romeo_esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+dfrobot_romeo_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+dfrobot_romeo_esp32s3.menu.UploadSpeed.230400=230400
+dfrobot_romeo_esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+dfrobot_romeo_esp32s3.menu.UploadSpeed.460800.linux=460800
+dfrobot_romeo_esp32s3.menu.UploadSpeed.460800.macosx=460800
+dfrobot_romeo_esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+dfrobot_romeo_esp32s3.menu.UploadSpeed.512000.windows=512000
+dfrobot_romeo_esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+dfrobot_romeo_esp32s3.menu.DebugLevel.none=None
+dfrobot_romeo_esp32s3.menu.DebugLevel.none.build.code_debug=0
+dfrobot_romeo_esp32s3.menu.DebugLevel.error=Error
+dfrobot_romeo_esp32s3.menu.DebugLevel.error.build.code_debug=1
+dfrobot_romeo_esp32s3.menu.DebugLevel.warn=Warn
+dfrobot_romeo_esp32s3.menu.DebugLevel.warn.build.code_debug=2
+dfrobot_romeo_esp32s3.menu.DebugLevel.info=Info
+dfrobot_romeo_esp32s3.menu.DebugLevel.info.build.code_debug=3
+dfrobot_romeo_esp32s3.menu.DebugLevel.debug=Debug
+dfrobot_romeo_esp32s3.menu.DebugLevel.debug.build.code_debug=4
+dfrobot_romeo_esp32s3.menu.DebugLevel.verbose=Verbose
+dfrobot_romeo_esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+dfrobot_romeo_esp32s3.menu.EraseFlash.none=Disabled
+dfrobot_romeo_esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+dfrobot_romeo_esp32s3.menu.EraseFlash.all=Enabled
+dfrobot_romeo_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 firebeetle32.name=FireBeetle-ESP32
 
+firebeetle32.bootloader.tool=esptool_py
+firebeetle32.bootloader.tool.default=esptool_py
+
 firebeetle32.upload.tool=esptool_py
+firebeetle32.upload.tool.default=esptool_py
+firebeetle32.upload.tool.network=esp_ota
+
 firebeetle32.upload.maximum_size=1310720
 firebeetle32.upload.maximum_data_size=327680
-firebeetle32.upload.wait_for_upload_port=true
+firebeetle32.upload.flags=
+firebeetle32.upload.extra_flags=
 
 firebeetle32.serial.disableDTR=true
 firebeetle32.serial.disableRTS=true
 
+firebeetle32.build.tarch=xtensa
+firebeetle32.build.bootloader_addr=0x1000
+firebeetle32.build.target=esp32
 firebeetle32.build.mcu=esp32
 firebeetle32.build.core=esp32
 firebeetle32.build.variant=firebeetle32
-firebeetle32.build.board=ESP32_DEV
+firebeetle32.build.board=DFROBOT_FIREBEETLE_ESP32
 
 firebeetle32.build.f_cpu=240000000L
 firebeetle32.build.flash_mode=dio
@@ -1681,18 +12760,46 @@ firebeetle32.menu.UploadSpeed.460800.upload.speed=460800
 firebeetle32.menu.UploadSpeed.512000.windows=512000
 firebeetle32.menu.UploadSpeed.512000.upload.speed=512000
 
+firebeetle32.menu.DebugLevel.none=None
+firebeetle32.menu.DebugLevel.none.build.code_debug=0
+firebeetle32.menu.DebugLevel.error=Error
+firebeetle32.menu.DebugLevel.error.build.code_debug=1
+firebeetle32.menu.DebugLevel.warn=Warn
+firebeetle32.menu.DebugLevel.warn.build.code_debug=2
+firebeetle32.menu.DebugLevel.info=Info
+firebeetle32.menu.DebugLevel.info.build.code_debug=3
+firebeetle32.menu.DebugLevel.debug=Debug
+firebeetle32.menu.DebugLevel.debug.build.code_debug=4
+firebeetle32.menu.DebugLevel.verbose=Verbose
+firebeetle32.menu.DebugLevel.verbose.build.code_debug=5
+
+firebeetle32.menu.EraseFlash.none=Disabled
+firebeetle32.menu.EraseFlash.none.upload.erase_cmd=
+firebeetle32.menu.EraseFlash.all=Enabled
+firebeetle32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 intorobot-fig.name=IntoRobot Fig
 
+intorobot-fig.bootloader.tool=esptool_py
+intorobot-fig.bootloader.tool.default=esptool_py
+
 intorobot-fig.upload.tool=esptool_py
+intorobot-fig.upload.tool.default=esptool_py
+intorobot-fig.upload.tool.network=esp_ota
+
 intorobot-fig.upload.maximum_size=1310720
 intorobot-fig.upload.maximum_data_size=327680
-intorobot-fig.upload.wait_for_upload_port=true
+intorobot-fig.upload.flags=
+intorobot-fig.upload.extra_flags=
 
 intorobot-fig.serial.disableDTR=true
 intorobot-fig.serial.disableRTS=true
 
+intorobot-fig.build.tarch=xtensa
+intorobot-fig.build.bootloader_addr=0x1000
+intorobot-fig.build.target=esp32
 intorobot-fig.build.mcu=esp32
 intorobot-fig.build.core=esp32
 intorobot-fig.build.variant=intorobot-fig
@@ -1725,18 +12832,46 @@ intorobot-fig.menu.UploadSpeed.460800.upload.speed=460800
 intorobot-fig.menu.UploadSpeed.512000.windows=512000
 intorobot-fig.menu.UploadSpeed.512000.upload.speed=512000
 
+intorobot-fig.menu.DebugLevel.none=None
+intorobot-fig.menu.DebugLevel.none.build.code_debug=0
+intorobot-fig.menu.DebugLevel.error=Error
+intorobot-fig.menu.DebugLevel.error.build.code_debug=1
+intorobot-fig.menu.DebugLevel.warn=Warn
+intorobot-fig.menu.DebugLevel.warn.build.code_debug=2
+intorobot-fig.menu.DebugLevel.info=Info
+intorobot-fig.menu.DebugLevel.info.build.code_debug=3
+intorobot-fig.menu.DebugLevel.debug=Debug
+intorobot-fig.menu.DebugLevel.debug.build.code_debug=4
+intorobot-fig.menu.DebugLevel.verbose=Verbose
+intorobot-fig.menu.DebugLevel.verbose.build.code_debug=5
+
+intorobot-fig.menu.EraseFlash.none=Disabled
+intorobot-fig.menu.EraseFlash.none.upload.erase_cmd=
+intorobot-fig.menu.EraseFlash.all=Enabled
+intorobot-fig.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 onehorse32dev.name=Onehorse ESP32 Dev Module
 
+onehorse32dev.bootloader.tool=esptool_py
+onehorse32dev.bootloader.tool.default=esptool_py
+
 onehorse32dev.upload.tool=esptool_py
+onehorse32dev.upload.tool.default=esptool_py
+onehorse32dev.upload.tool.network=esp_ota
+
 onehorse32dev.upload.maximum_size=1310720
 onehorse32dev.upload.maximum_data_size=327680
-onehorse32dev.upload.wait_for_upload_port=true
+onehorse32dev.upload.flags=
+onehorse32dev.upload.extra_flags=
 
 onehorse32dev.serial.disableDTR=true
 onehorse32dev.serial.disableRTS=true
 
+onehorse32dev.build.tarch=xtensa
+onehorse32dev.build.bootloader_addr=0x1000
+onehorse32dev.build.target=esp32
 onehorse32dev.build.mcu=esp32
 onehorse32dev.build.core=esp32
 onehorse32dev.build.variant=onehorse32dev
@@ -1769,35 +12904,870 @@ onehorse32dev.menu.UploadSpeed.460800.upload.speed=460800
 onehorse32dev.menu.UploadSpeed.512000.windows=512000
 onehorse32dev.menu.UploadSpeed.512000.upload.speed=512000
 
+onehorse32dev.menu.DebugLevel.none=None
+onehorse32dev.menu.DebugLevel.none.build.code_debug=0
+onehorse32dev.menu.DebugLevel.error=Error
+onehorse32dev.menu.DebugLevel.error.build.code_debug=1
+onehorse32dev.menu.DebugLevel.warn=Warn
+onehorse32dev.menu.DebugLevel.warn.build.code_debug=2
+onehorse32dev.menu.DebugLevel.info=Info
+onehorse32dev.menu.DebugLevel.info.build.code_debug=3
+onehorse32dev.menu.DebugLevel.debug=Debug
+onehorse32dev.menu.DebugLevel.debug.build.code_debug=4
+onehorse32dev.menu.DebugLevel.verbose=Verbose
+onehorse32dev.menu.DebugLevel.verbose.build.code_debug=5
+
+onehorse32dev.menu.EraseFlash.none=Disabled
+onehorse32dev.menu.EraseFlash.none.upload.erase_cmd=
+onehorse32dev.menu.EraseFlash.all=Enabled
+onehorse32dev.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# Adafruit Metro ESP32-S2
+
+adafruit_metro_esp32s2.name=Adafruit Metro ESP32-S2
+adafruit_metro_esp32s2.vid.0=0x239A
+adafruit_metro_esp32s2.pid.0=0x80DF
+adafruit_metro_esp32s2.vid.1=0x239A
+adafruit_metro_esp32s2.pid.1=0x00DF
+adafruit_metro_esp32s2.vid.2=0x239A
+adafruit_metro_esp32s2.pid.2=0x80E0
+adafruit_metro_esp32s2.upload_port.0.vid=0x239A
+adafruit_metro_esp32s2.upload_port.0.pid=0x80DF
+adafruit_metro_esp32s2.upload_port.1.vid=0x239A
+adafruit_metro_esp32s2.upload_port.1.pid=0x00DF
+adafruit_metro_esp32s2.upload_port.2.vid=0x239A
+adafruit_metro_esp32s2.upload_port.2.pid=0x80E0
+
+adafruit_metro_esp32s2.bootloader.tool=esptool_py
+adafruit_metro_esp32s2.bootloader.tool.default=esptool_py
+
+adafruit_metro_esp32s2.upload.tool=esptool_py
+adafruit_metro_esp32s2.upload.tool.default=esptool_py
+adafruit_metro_esp32s2.upload.tool.network=esp_ota
+
+adafruit_metro_esp32s2.upload.maximum_size=1310720
+adafruit_metro_esp32s2.upload.maximum_data_size=327680
+adafruit_metro_esp32s2.upload.flags=
+adafruit_metro_esp32s2.upload.extra_flags=
+adafruit_metro_esp32s2.upload.use_1200bps_touch=true
+adafruit_metro_esp32s2.upload.wait_for_upload_port=true
+
+adafruit_metro_esp32s2.serial.disableDTR=false
+adafruit_metro_esp32s2.serial.disableRTS=false
+
+adafruit_metro_esp32s2.build.tarch=xtensa
+adafruit_metro_esp32s2.build.bootloader_addr=0x1000
+adafruit_metro_esp32s2.build.target=esp32s2
+adafruit_metro_esp32s2.build.mcu=esp32s2
+adafruit_metro_esp32s2.build.core=esp32
+adafruit_metro_esp32s2.build.variant=adafruit_metro_esp32s2
+adafruit_metro_esp32s2.build.board=METRO_ESP32S2
+
+adafruit_metro_esp32s2.build.cdc_on_boot=1
+adafruit_metro_esp32s2.build.msc_on_boot=0
+adafruit_metro_esp32s2.build.dfu_on_boot=0
+adafruit_metro_esp32s2.build.f_cpu=240000000L
+adafruit_metro_esp32s2.build.flash_size=4MB
+adafruit_metro_esp32s2.build.flash_freq=80m
+adafruit_metro_esp32s2.build.flash_mode=dio
+adafruit_metro_esp32s2.build.boot=qio
+adafruit_metro_esp32s2.build.partitions=default
+adafruit_metro_esp32s2.build.defines=
+
+adafruit_metro_esp32s2.menu.CDCOnBoot.cdc=Enabled
+adafruit_metro_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_metro_esp32s2.menu.CDCOnBoot.default=Disabled
+adafruit_metro_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_metro_esp32s2.menu.MSCOnBoot.default=Disabled
+adafruit_metro_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_metro_esp32s2.menu.MSCOnBoot.msc=Enabled
+adafruit_metro_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_metro_esp32s2.menu.DFUOnBoot.default=Disabled
+adafruit_metro_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_metro_esp32s2.menu.DFUOnBoot.dfu=Enabled
+adafruit_metro_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_metro_esp32s2.menu.UploadMode.cdc=Internal USB
+adafruit_metro_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_metro_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_metro_esp32s2.menu.UploadMode.default=UART0
+adafruit_metro_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_metro_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_metro_esp32s2.menu.PSRAM.enabled=Enabled
+adafruit_metro_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_metro_esp32s2.menu.PSRAM.disabled=Disabled
+adafruit_metro_esp32s2.menu.PSRAM.disabled.build.defines=
+
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_metro_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_metro_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.default.build.partitions=default
+adafruit_metro_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_metro_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_metro_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_metro_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_metro_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_metro_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_metro_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_metro_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_metro_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_metro_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_metro_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_metro_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_metro_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_metro_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_metro_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_metro_esp32s2.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_metro_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_metro_esp32s2.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_metro_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_metro_esp32s2.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_metro_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_metro_esp32s2.menu.CPUFreq.40=40MHz
+adafruit_metro_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_metro_esp32s2.menu.CPUFreq.20=20MHz
+adafruit_metro_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_metro_esp32s2.menu.CPUFreq.10=10MHz
+adafruit_metro_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_metro_esp32s2.menu.FlashMode.qio=QIO
+adafruit_metro_esp32s2.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_metro_esp32s2.menu.FlashMode.qio.build.boot=qio
+adafruit_metro_esp32s2.menu.FlashMode.dio=DIO
+adafruit_metro_esp32s2.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_metro_esp32s2.menu.FlashMode.dio.build.boot=dio
+
+adafruit_metro_esp32s2.menu.FlashFreq.80=80MHz
+adafruit_metro_esp32s2.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_metro_esp32s2.menu.FlashFreq.40=40MHz
+adafruit_metro_esp32s2.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_metro_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+adafruit_metro_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_metro_esp32s2.menu.UploadSpeed.921600=921600
+adafruit_metro_esp32s2.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_metro_esp32s2.menu.UploadSpeed.115200=115200
+adafruit_metro_esp32s2.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_metro_esp32s2.menu.UploadSpeed.256000.windows=256000
+adafruit_metro_esp32s2.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_metro_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_metro_esp32s2.menu.UploadSpeed.230400=230400
+adafruit_metro_esp32s2.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_metro_esp32s2.menu.UploadSpeed.460800.linux=460800
+adafruit_metro_esp32s2.menu.UploadSpeed.460800.macosx=460800
+adafruit_metro_esp32s2.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_metro_esp32s2.menu.UploadSpeed.512000.windows=512000
+adafruit_metro_esp32s2.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_metro_esp32s2.menu.DebugLevel.none=None
+adafruit_metro_esp32s2.menu.DebugLevel.none.build.code_debug=0
+adafruit_metro_esp32s2.menu.DebugLevel.error=Error
+adafruit_metro_esp32s2.menu.DebugLevel.error.build.code_debug=1
+adafruit_metro_esp32s2.menu.DebugLevel.warn=Warn
+adafruit_metro_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+adafruit_metro_esp32s2.menu.DebugLevel.info=Info
+adafruit_metro_esp32s2.menu.DebugLevel.info.build.code_debug=3
+adafruit_metro_esp32s2.menu.DebugLevel.debug=Debug
+adafruit_metro_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+adafruit_metro_esp32s2.menu.DebugLevel.verbose=Verbose
+adafruit_metro_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_metro_esp32s2.menu.EraseFlash.none=Disabled
+adafruit_metro_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_metro_esp32s2.menu.EraseFlash.all=Enabled
+adafruit_metro_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_metro_esp32s2.menu.ZigbeeMode.default=Disabled
+adafruit_metro_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_metro_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_metro_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_metro_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_metro_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Metro ESP32-S3
+
+adafruit_metro_esp32s3.name=Adafruit Metro ESP32-S3
+adafruit_metro_esp32s3.vid.0=0x239A
+adafruit_metro_esp32s3.pid.0=0x8145
+adafruit_metro_esp32s3.vid.1=0x239A
+adafruit_metro_esp32s3.pid.1=0x0145
+adafruit_metro_esp32s3.vid.2=0x239A
+adafruit_metro_esp32s3.pid.2=0x8146
+adafruit_metro_esp32s3.upload_port.0.vid=0x239A
+adafruit_metro_esp32s3.upload_port.0.pid=0x8145
+adafruit_metro_esp32s3.upload_port.1.vid=0x239A
+adafruit_metro_esp32s3.upload_port.1.pid=0x0145
+adafruit_metro_esp32s3.upload_port.2.vid=0x239A
+adafruit_metro_esp32s3.upload_port.2.pid=0x8146
+
+adafruit_metro_esp32s3.bootloader.tool=esptool_py
+adafruit_metro_esp32s3.bootloader.tool.default=esptool_py
+
+adafruit_metro_esp32s3.upload.tool=esptool_py
+adafruit_metro_esp32s3.upload.tool.default=esptool_py
+adafruit_metro_esp32s3.upload.tool.network=esp_ota
+
+adafruit_metro_esp32s3.upload.maximum_size=1310720
+adafruit_metro_esp32s3.upload.maximum_data_size=327680
+adafruit_metro_esp32s3.upload.flags=
+adafruit_metro_esp32s3.upload.extra_flags=
+adafruit_metro_esp32s3.upload.use_1200bps_touch=true
+adafruit_metro_esp32s3.upload.wait_for_upload_port=true
+
+adafruit_metro_esp32s3.serial.disableDTR=false
+adafruit_metro_esp32s3.serial.disableRTS=false
+
+adafruit_metro_esp32s3.build.tarch=xtensa
+adafruit_metro_esp32s3.build.bootloader_addr=0x0
+adafruit_metro_esp32s3.build.target=esp32s3
+adafruit_metro_esp32s3.build.mcu=esp32s3
+adafruit_metro_esp32s3.build.core=esp32
+adafruit_metro_esp32s3.build.variant=adafruit_metro_esp32s3
+adafruit_metro_esp32s3.build.board=METRO_ESP32S3
+
+adafruit_metro_esp32s3.build.usb_mode=0
+adafruit_metro_esp32s3.build.cdc_on_boot=1
+adafruit_metro_esp32s3.build.msc_on_boot=0
+adafruit_metro_esp32s3.build.dfu_on_boot=0
+adafruit_metro_esp32s3.build.f_cpu=240000000L
+adafruit_metro_esp32s3.build.flash_size=16MB
+adafruit_metro_esp32s3.build.flash_freq=80m
+adafruit_metro_esp32s3.build.flash_mode=dio
+adafruit_metro_esp32s3.build.boot=qio
+adafruit_metro_esp32s3.build.partitions=default
+adafruit_metro_esp32s3.build.defines=
+adafruit_metro_esp32s3.build.loop_core=
+adafruit_metro_esp32s3.build.event_core=
+adafruit_metro_esp32s3.build.flash_type=qio
+adafruit_metro_esp32s3.build.psram_type=opi
+adafruit_metro_esp32s3.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_metro_esp32s3.menu.LoopCore.1=Core 1
+adafruit_metro_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_metro_esp32s3.menu.LoopCore.0=Core 0
+adafruit_metro_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_metro_esp32s3.menu.EventsCore.1=Core 1
+adafruit_metro_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_metro_esp32s3.menu.EventsCore.0=Core 0
+adafruit_metro_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_metro_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_metro_esp32s3.menu.USBMode.default.build.usb_mode=0
+adafruit_metro_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_metro_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_metro_esp32s3.menu.CDCOnBoot.cdc=Enabled
+adafruit_metro_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_metro_esp32s3.menu.CDCOnBoot.default=Disabled
+adafruit_metro_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_metro_esp32s3.menu.MSCOnBoot.default=Disabled
+adafruit_metro_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_metro_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_metro_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_metro_esp32s3.menu.DFUOnBoot.default=Disabled
+adafruit_metro_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_metro_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_metro_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_metro_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_metro_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_metro_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_metro_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_metro_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_metro_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_metro_esp32s3.menu.PSRAM.opi=OPI PSRAM
+adafruit_metro_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+adafruit_metro_esp32s3.menu.PSRAM.opi.build.psram_type=opi
+adafruit_metro_esp32s3.menu.PSRAM.disabled=Disabled
+adafruit_metro_esp32s3.menu.PSRAM.disabled.build.defines=
+adafruit_metro_esp32s3.menu.PSRAM.disabled.build.psram_type=opi
+
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 16MB (2MB APP/11.6MB FATFS)
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-16MB
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota=TinyUF2 16MB No OTA(4MB APP/11.6MB FATFS)
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-16MB-noota
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304
+adafruit_metro_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_metro_esp32s3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS)
+adafruit_metro_esp32s3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
+adafruit_metro_esp32s3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
+adafruit_metro_esp32s3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS)
+adafruit_metro_esp32s3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
+adafruit_metro_esp32s3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592
+adafruit_metro_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+adafruit_metro_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+adafruit_metro_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+adafruit_metro_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+adafruit_metro_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+adafruit_metro_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+
+adafruit_metro_esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_metro_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_metro_esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_metro_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_metro_esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_metro_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_metro_esp32s3.menu.CPUFreq.40=40MHz
+adafruit_metro_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_metro_esp32s3.menu.CPUFreq.20=20MHz
+adafruit_metro_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_metro_esp32s3.menu.CPUFreq.10=10MHz
+adafruit_metro_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_metro_esp32s3.menu.FlashMode.qio=QIO 80MHz
+adafruit_metro_esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_metro_esp32s3.menu.FlashMode.qio.build.boot=qio
+adafruit_metro_esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_metro_esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_metro_esp32s3.menu.FlashMode.qio120=QIO 120MHz
+adafruit_metro_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_metro_esp32s3.menu.FlashMode.qio120.build.boot=qio
+adafruit_metro_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_metro_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_metro_esp32s3.menu.FlashMode.dio=DIO 80MHz
+adafruit_metro_esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_metro_esp32s3.menu.FlashMode.dio.build.boot=dio
+adafruit_metro_esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_metro_esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_metro_esp32s3.menu.FlashMode.opi=OPI 80MHz
+adafruit_metro_esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_metro_esp32s3.menu.FlashMode.opi.build.boot=opi
+adafruit_metro_esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_metro_esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_metro_esp32s3.menu.FlashSize.16M=16MB (128Mb)
+adafruit_metro_esp32s3.menu.FlashSize.16M.build.flash_size=16MB
+
+adafruit_metro_esp32s3.menu.UploadSpeed.921600=921600
+adafruit_metro_esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_metro_esp32s3.menu.UploadSpeed.115200=115200
+adafruit_metro_esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_metro_esp32s3.menu.UploadSpeed.256000.windows=256000
+adafruit_metro_esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_metro_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_metro_esp32s3.menu.UploadSpeed.230400=230400
+adafruit_metro_esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_metro_esp32s3.menu.UploadSpeed.460800.linux=460800
+adafruit_metro_esp32s3.menu.UploadSpeed.460800.macosx=460800
+adafruit_metro_esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_metro_esp32s3.menu.UploadSpeed.512000.windows=512000
+adafruit_metro_esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_metro_esp32s3.menu.DebugLevel.none=None
+adafruit_metro_esp32s3.menu.DebugLevel.none.build.code_debug=0
+adafruit_metro_esp32s3.menu.DebugLevel.error=Error
+adafruit_metro_esp32s3.menu.DebugLevel.error.build.code_debug=1
+adafruit_metro_esp32s3.menu.DebugLevel.warn=Warn
+adafruit_metro_esp32s3.menu.DebugLevel.warn.build.code_debug=2
+adafruit_metro_esp32s3.menu.DebugLevel.info=Info
+adafruit_metro_esp32s3.menu.DebugLevel.info.build.code_debug=3
+adafruit_metro_esp32s3.menu.DebugLevel.debug=Debug
+adafruit_metro_esp32s3.menu.DebugLevel.debug.build.code_debug=4
+adafruit_metro_esp32s3.menu.DebugLevel.verbose=Verbose
+adafruit_metro_esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_metro_esp32s3.menu.EraseFlash.none=Disabled
+adafruit_metro_esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_metro_esp32s3.menu.EraseFlash.all=Enabled
+adafruit_metro_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_metro_esp32s3.menu.ZigbeeMode.default=Disabled
+adafruit_metro_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_metro_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_metro_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_metro_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_metro_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit MagTag 2.9"
+
+adafruit_magtag29_esp32s2.name=Adafruit MagTag 2.9"
+adafruit_magtag29_esp32s2.vid.0=0x239A
+adafruit_magtag29_esp32s2.pid.0=0x80E5
+adafruit_magtag29_esp32s2.vid.1=0x239A
+adafruit_magtag29_esp32s2.pid.1=0x00E5
+adafruit_magtag29_esp32s2.vid.2=0x239A
+adafruit_magtag29_esp32s2.pid.2=0x80E6
+adafruit_magtag29_esp32s2.upload_port.0.vid=0x239A
+adafruit_magtag29_esp32s2.upload_port.0.pid=0x80E5
+adafruit_magtag29_esp32s2.upload_port.1.vid=0x239A
+adafruit_magtag29_esp32s2.upload_port.1.pid=0x00E5
+adafruit_magtag29_esp32s2.upload_port.2.vid=0x239A
+adafruit_magtag29_esp32s2.upload_port.2.pid=0x80E6
+
+adafruit_magtag29_esp32s2.bootloader.tool=esptool_py
+adafruit_magtag29_esp32s2.bootloader.tool.default=esptool_py
+
+adafruit_magtag29_esp32s2.upload.tool=esptool_py
+adafruit_magtag29_esp32s2.upload.tool.default=esptool_py
+adafruit_magtag29_esp32s2.upload.tool.network=esp_ota
+
+adafruit_magtag29_esp32s2.upload.maximum_size=1310720
+adafruit_magtag29_esp32s2.upload.maximum_data_size=327680
+adafruit_magtag29_esp32s2.upload.flags=
+adafruit_magtag29_esp32s2.upload.extra_flags=
+adafruit_magtag29_esp32s2.upload.use_1200bps_touch=true
+adafruit_magtag29_esp32s2.upload.wait_for_upload_port=true
+
+adafruit_magtag29_esp32s2.serial.disableDTR=false
+adafruit_magtag29_esp32s2.serial.disableRTS=false
+
+adafruit_magtag29_esp32s2.build.tarch=xtensa
+adafruit_magtag29_esp32s2.build.bootloader_addr=0x1000
+adafruit_magtag29_esp32s2.build.target=esp32s2
+adafruit_magtag29_esp32s2.build.mcu=esp32s2
+adafruit_magtag29_esp32s2.build.core=esp32
+adafruit_magtag29_esp32s2.build.variant=adafruit_magtag29_esp32s2
+adafruit_magtag29_esp32s2.build.board=MAGTAG29_ESP32S2
+
+adafruit_magtag29_esp32s2.build.cdc_on_boot=1
+adafruit_magtag29_esp32s2.build.msc_on_boot=0
+adafruit_magtag29_esp32s2.build.dfu_on_boot=0
+adafruit_magtag29_esp32s2.build.f_cpu=240000000L
+adafruit_magtag29_esp32s2.build.flash_size=4MB
+adafruit_magtag29_esp32s2.build.flash_freq=80m
+adafruit_magtag29_esp32s2.build.flash_mode=dio
+adafruit_magtag29_esp32s2.build.boot=qio
+adafruit_magtag29_esp32s2.build.partitions=default
+adafruit_magtag29_esp32s2.build.defines=
+
+adafruit_magtag29_esp32s2.menu.CDCOnBoot.cdc=Enabled
+adafruit_magtag29_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_magtag29_esp32s2.menu.CDCOnBoot.default=Disabled
+adafruit_magtag29_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_magtag29_esp32s2.menu.MSCOnBoot.default=Disabled
+adafruit_magtag29_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_magtag29_esp32s2.menu.MSCOnBoot.msc=Enabled
+adafruit_magtag29_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_magtag29_esp32s2.menu.DFUOnBoot.default=Disabled
+adafruit_magtag29_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_magtag29_esp32s2.menu.DFUOnBoot.dfu=Enabled
+adafruit_magtag29_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_magtag29_esp32s2.menu.UploadMode.cdc=Internal USB
+adafruit_magtag29_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_magtag29_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_magtag29_esp32s2.menu.UploadMode.default=UART0
+adafruit_magtag29_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_magtag29_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_magtag29_esp32s2.menu.PSRAM.enabled=Enabled
+adafruit_magtag29_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_magtag29_esp32s2.menu.PSRAM.disabled=Disabled
+adafruit_magtag29_esp32s2.menu.PSRAM.disabled.build.defines=
+
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_magtag29_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_magtag29_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.default.build.partitions=default
+adafruit_magtag29_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_magtag29_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_magtag29_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_magtag29_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_magtag29_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_magtag29_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_magtag29_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_magtag29_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_magtag29_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_magtag29_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_magtag29_esp32s2.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_magtag29_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_magtag29_esp32s2.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_magtag29_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_magtag29_esp32s2.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_magtag29_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_magtag29_esp32s2.menu.CPUFreq.40=40MHz
+adafruit_magtag29_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_magtag29_esp32s2.menu.CPUFreq.20=20MHz
+adafruit_magtag29_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_magtag29_esp32s2.menu.CPUFreq.10=10MHz
+adafruit_magtag29_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_magtag29_esp32s2.menu.FlashMode.qio=QIO
+adafruit_magtag29_esp32s2.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_magtag29_esp32s2.menu.FlashMode.qio.build.boot=qio
+adafruit_magtag29_esp32s2.menu.FlashMode.dio=DIO
+adafruit_magtag29_esp32s2.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_magtag29_esp32s2.menu.FlashMode.dio.build.boot=dio
+
+adafruit_magtag29_esp32s2.menu.FlashFreq.80=80MHz
+adafruit_magtag29_esp32s2.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_magtag29_esp32s2.menu.FlashFreq.40=40MHz
+adafruit_magtag29_esp32s2.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_magtag29_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+adafruit_magtag29_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_magtag29_esp32s2.menu.UploadSpeed.921600=921600
+adafruit_magtag29_esp32s2.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_magtag29_esp32s2.menu.UploadSpeed.115200=115200
+adafruit_magtag29_esp32s2.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_magtag29_esp32s2.menu.UploadSpeed.256000.windows=256000
+adafruit_magtag29_esp32s2.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_magtag29_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_magtag29_esp32s2.menu.UploadSpeed.230400=230400
+adafruit_magtag29_esp32s2.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_magtag29_esp32s2.menu.UploadSpeed.460800.linux=460800
+adafruit_magtag29_esp32s2.menu.UploadSpeed.460800.macosx=460800
+adafruit_magtag29_esp32s2.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_magtag29_esp32s2.menu.UploadSpeed.512000.windows=512000
+adafruit_magtag29_esp32s2.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_magtag29_esp32s2.menu.DebugLevel.none=None
+adafruit_magtag29_esp32s2.menu.DebugLevel.none.build.code_debug=0
+adafruit_magtag29_esp32s2.menu.DebugLevel.error=Error
+adafruit_magtag29_esp32s2.menu.DebugLevel.error.build.code_debug=1
+adafruit_magtag29_esp32s2.menu.DebugLevel.warn=Warn
+adafruit_magtag29_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+adafruit_magtag29_esp32s2.menu.DebugLevel.info=Info
+adafruit_magtag29_esp32s2.menu.DebugLevel.info.build.code_debug=3
+adafruit_magtag29_esp32s2.menu.DebugLevel.debug=Debug
+adafruit_magtag29_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+adafruit_magtag29_esp32s2.menu.DebugLevel.verbose=Verbose
+adafruit_magtag29_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_magtag29_esp32s2.menu.EraseFlash.none=Disabled
+adafruit_magtag29_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_magtag29_esp32s2.menu.EraseFlash.all=Enabled
+adafruit_magtag29_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_magtag29_esp32s2.menu.ZigbeeMode.default=Disabled
+adafruit_magtag29_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_magtag29_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_magtag29_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_magtag29_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_magtag29_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit FunHouse
+
+adafruit_funhouse_esp32s2.name=Adafruit FunHouse
+adafruit_funhouse_esp32s2.vid.0=0x239A
+adafruit_funhouse_esp32s2.pid.0=0x80F9
+adafruit_funhouse_esp32s2.vid.1=0x239A
+adafruit_funhouse_esp32s2.pid.1=0x00F9
+adafruit_funhouse_esp32s2.vid.2=0x239A
+adafruit_funhouse_esp32s2.pid.2=0x80FA
+adafruit_funhouse_esp32s2.upload_port.0.vid=0x239A
+adafruit_funhouse_esp32s2.upload_port.0.pid=0x80F9
+adafruit_funhouse_esp32s2.upload_port.1.vid=0x239A
+adafruit_funhouse_esp32s2.upload_port.1.pid=0x00F9
+adafruit_funhouse_esp32s2.upload_port.2.vid=0x239A
+adafruit_funhouse_esp32s2.upload_port.2.pid=0x80FA
+
+adafruit_funhouse_esp32s2.bootloader.tool=esptool_py
+adafruit_funhouse_esp32s2.bootloader.tool.default=esptool_py
+
+adafruit_funhouse_esp32s2.upload.tool=esptool_py
+adafruit_funhouse_esp32s2.upload.tool.default=esptool_py
+adafruit_funhouse_esp32s2.upload.tool.network=esp_ota
+
+adafruit_funhouse_esp32s2.upload.maximum_size=1310720
+adafruit_funhouse_esp32s2.upload.maximum_data_size=327680
+adafruit_funhouse_esp32s2.upload.flags=
+adafruit_funhouse_esp32s2.upload.extra_flags=
+adafruit_funhouse_esp32s2.upload.use_1200bps_touch=true
+adafruit_funhouse_esp32s2.upload.wait_for_upload_port=true
+
+adafruit_funhouse_esp32s2.serial.disableDTR=false
+adafruit_funhouse_esp32s2.serial.disableRTS=false
+
+adafruit_funhouse_esp32s2.build.tarch=xtensa
+adafruit_funhouse_esp32s2.build.bootloader_addr=0x1000
+adafruit_funhouse_esp32s2.build.target=esp32s2
+adafruit_funhouse_esp32s2.build.mcu=esp32s2
+adafruit_funhouse_esp32s2.build.core=esp32
+adafruit_funhouse_esp32s2.build.variant=adafruit_funhouse_esp32s2
+adafruit_funhouse_esp32s2.build.board=FUNHOUSE_ESP32S2
+
+adafruit_funhouse_esp32s2.build.cdc_on_boot=1
+adafruit_funhouse_esp32s2.build.msc_on_boot=0
+adafruit_funhouse_esp32s2.build.dfu_on_boot=0
+adafruit_funhouse_esp32s2.build.f_cpu=240000000L
+adafruit_funhouse_esp32s2.build.flash_size=4MB
+adafruit_funhouse_esp32s2.build.flash_freq=80m
+adafruit_funhouse_esp32s2.build.flash_mode=dio
+adafruit_funhouse_esp32s2.build.boot=qio
+adafruit_funhouse_esp32s2.build.partitions=default
+adafruit_funhouse_esp32s2.build.defines=
+
+adafruit_funhouse_esp32s2.menu.CDCOnBoot.cdc=Enabled
+adafruit_funhouse_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_funhouse_esp32s2.menu.CDCOnBoot.default=Disabled
+adafruit_funhouse_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_funhouse_esp32s2.menu.MSCOnBoot.default=Disabled
+adafruit_funhouse_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_funhouse_esp32s2.menu.MSCOnBoot.msc=Enabled
+adafruit_funhouse_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_funhouse_esp32s2.menu.DFUOnBoot.default=Disabled
+adafruit_funhouse_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_funhouse_esp32s2.menu.DFUOnBoot.dfu=Enabled
+adafruit_funhouse_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_funhouse_esp32s2.menu.UploadMode.cdc=Internal USB
+adafruit_funhouse_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_funhouse_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_funhouse_esp32s2.menu.UploadMode.default=UART0
+adafruit_funhouse_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_funhouse_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_funhouse_esp32s2.menu.PSRAM.enabled=Enabled
+adafruit_funhouse_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_funhouse_esp32s2.menu.PSRAM.disabled=Disabled
+adafruit_funhouse_esp32s2.menu.PSRAM.disabled.build.defines=
+
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_funhouse_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_funhouse_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.default.build.partitions=default
+adafruit_funhouse_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_funhouse_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_funhouse_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_funhouse_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_funhouse_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_funhouse_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_funhouse_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_funhouse_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_funhouse_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_funhouse_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_funhouse_esp32s2.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_funhouse_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_funhouse_esp32s2.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_funhouse_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_funhouse_esp32s2.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_funhouse_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_funhouse_esp32s2.menu.CPUFreq.40=40MHz
+adafruit_funhouse_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_funhouse_esp32s2.menu.CPUFreq.20=20MHz
+adafruit_funhouse_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_funhouse_esp32s2.menu.CPUFreq.10=10MHz
+adafruit_funhouse_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_funhouse_esp32s2.menu.FlashMode.qio=QIO
+adafruit_funhouse_esp32s2.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_funhouse_esp32s2.menu.FlashMode.qio.build.boot=qio
+adafruit_funhouse_esp32s2.menu.FlashMode.dio=DIO
+adafruit_funhouse_esp32s2.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_funhouse_esp32s2.menu.FlashMode.dio.build.boot=dio
+
+adafruit_funhouse_esp32s2.menu.FlashFreq.80=80MHz
+adafruit_funhouse_esp32s2.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_funhouse_esp32s2.menu.FlashFreq.40=40MHz
+adafruit_funhouse_esp32s2.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_funhouse_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+adafruit_funhouse_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_funhouse_esp32s2.menu.UploadSpeed.921600=921600
+adafruit_funhouse_esp32s2.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_funhouse_esp32s2.menu.UploadSpeed.115200=115200
+adafruit_funhouse_esp32s2.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_funhouse_esp32s2.menu.UploadSpeed.256000.windows=256000
+adafruit_funhouse_esp32s2.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_funhouse_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_funhouse_esp32s2.menu.UploadSpeed.230400=230400
+adafruit_funhouse_esp32s2.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_funhouse_esp32s2.menu.UploadSpeed.460800.linux=460800
+adafruit_funhouse_esp32s2.menu.UploadSpeed.460800.macosx=460800
+adafruit_funhouse_esp32s2.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_funhouse_esp32s2.menu.UploadSpeed.512000.windows=512000
+adafruit_funhouse_esp32s2.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_funhouse_esp32s2.menu.DebugLevel.none=None
+adafruit_funhouse_esp32s2.menu.DebugLevel.none.build.code_debug=0
+adafruit_funhouse_esp32s2.menu.DebugLevel.error=Error
+adafruit_funhouse_esp32s2.menu.DebugLevel.error.build.code_debug=1
+adafruit_funhouse_esp32s2.menu.DebugLevel.warn=Warn
+adafruit_funhouse_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+adafruit_funhouse_esp32s2.menu.DebugLevel.info=Info
+adafruit_funhouse_esp32s2.menu.DebugLevel.info.build.code_debug=3
+adafruit_funhouse_esp32s2.menu.DebugLevel.debug=Debug
+adafruit_funhouse_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+adafruit_funhouse_esp32s2.menu.DebugLevel.verbose=Verbose
+adafruit_funhouse_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_funhouse_esp32s2.menu.EraseFlash.none=Disabled
+adafruit_funhouse_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_funhouse_esp32s2.menu.EraseFlash.all=Enabled
+adafruit_funhouse_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_funhouse_esp32s2.menu.ZigbeeMode.default=Disabled
+adafruit_funhouse_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_funhouse_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_funhouse_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_funhouse_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_funhouse_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
 ##############################################################
+# Adafruit ESP32 Feather
 
 featheresp32.name=Adafruit ESP32 Feather
 
+featheresp32.bootloader.tool=esptool_py
+featheresp32.bootloader.tool.default=esptool_py
+
 featheresp32.upload.tool=esptool_py
+featheresp32.upload.tool.default=esptool_py
+featheresp32.upload.tool.network=esp_ota
+
 featheresp32.upload.maximum_size=1310720
 featheresp32.upload.maximum_data_size=327680
-featheresp32.upload.wait_for_upload_port=true
+featheresp32.upload.flags=
+featheresp32.upload.extra_flags=
 
 featheresp32.serial.disableDTR=true
 featheresp32.serial.disableRTS=true
 
+featheresp32.build.tarch=xtensa
+featheresp32.build.bootloader_addr=0x1000
+featheresp32.build.target=esp32
 featheresp32.build.mcu=esp32
 featheresp32.build.core=esp32
 featheresp32.build.variant=feather_esp32
 featheresp32.build.board=FEATHER_ESP32
 
 featheresp32.build.f_cpu=240000000L
-featheresp32.build.flash_mode=dio
 featheresp32.build.flash_size=4MB
+featheresp32.build.flash_freq=80m
+featheresp32.build.flash_mode=dio
 featheresp32.build.boot=dio
 featheresp32.build.partitions=default
 featheresp32.build.defines=
+featheresp32.build.loop_core=
+featheresp32.build.event_core=
+
+featheresp32.menu.LoopCore.1=Core 1
+featheresp32.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+featheresp32.menu.LoopCore.0=Core 0
+featheresp32.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+featheresp32.menu.EventsCore.1=Core 1
+featheresp32.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+featheresp32.menu.EventsCore.0=Core 0
+featheresp32.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+featheresp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+featheresp32.menu.PartitionScheme.default.build.partitions=default
+featheresp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+featheresp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+featheresp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+featheresp32.menu.PartitionScheme.minimal.build.partitions=minimal
+featheresp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+featheresp32.menu.PartitionScheme.no_ota.build.partitions=no_ota
+featheresp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+featheresp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+featheresp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+featheresp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+featheresp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+featheresp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+featheresp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+featheresp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+featheresp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+featheresp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+featheresp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+featheresp32.menu.PartitionScheme.huge_app.build.partitions=huge_app
+featheresp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+featheresp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+featheresp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+featheresp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+featheresp32.menu.CPUFreq.240=240MHz (WiFi/BT)
+featheresp32.menu.CPUFreq.240.build.f_cpu=240000000L
+featheresp32.menu.CPUFreq.160=160MHz (WiFi/BT)
+featheresp32.menu.CPUFreq.160.build.f_cpu=160000000L
+featheresp32.menu.CPUFreq.80=80MHz (WiFi/BT)
+featheresp32.menu.CPUFreq.80.build.f_cpu=80000000L
+featheresp32.menu.CPUFreq.40=40MHz
+featheresp32.menu.CPUFreq.40.build.f_cpu=40000000L
+featheresp32.menu.CPUFreq.20=20MHz
+featheresp32.menu.CPUFreq.20.build.f_cpu=20000000L
+featheresp32.menu.CPUFreq.10=10MHz
+featheresp32.menu.CPUFreq.10.build.f_cpu=10000000L
 
 featheresp32.menu.FlashFreq.80=80MHz
 featheresp32.menu.FlashFreq.80.build.flash_freq=80m
 featheresp32.menu.FlashFreq.40=40MHz
 featheresp32.menu.FlashFreq.40.build.flash_freq=40m
 
+featheresp32.menu.FlashSize.4M=4MB (32Mb)
+featheresp32.menu.FlashSize.4M.build.flash_size=4MB
+
 featheresp32.menu.UploadSpeed.921600=921600
 featheresp32.menu.UploadSpeed.921600.upload.speed=921600
 featheresp32.menu.UploadSpeed.115200=115200
@@ -1826,31 +13796,3578 @@ featheresp32.menu.DebugLevel.debug.build.code_debug=4
 featheresp32.menu.DebugLevel.verbose=Verbose
 featheresp32.menu.DebugLevel.verbose.build.code_debug=5
 
-featheresp32.menu.PartitionScheme.default=Default
-featheresp32.menu.PartitionScheme.default.build.partitions=default
-featheresp32.menu.PartitionScheme.no_ota=No OTA (Large APP)
-featheresp32.menu.PartitionScheme.no_ota.build.partitions=no_ota
-featheresp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-featheresp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-featheresp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-featheresp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+featheresp32.menu.EraseFlash.none=Disabled
+featheresp32.menu.EraseFlash.none.upload.erase_cmd=
+featheresp32.menu.EraseFlash.all=Enabled
+featheresp32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+featheresp32.menu.ZigbeeMode.default=Disabled
+featheresp32.menu.ZigbeeMode.default.build.zigbee_mode=
+featheresp32.menu.ZigbeeMode.default.build.zigbee_libs=
+featheresp32.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+featheresp32.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+featheresp32.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Feather ESP32 V2
+
+adafruit_feather_esp32_v2.name=Adafruit Feather ESP32 V2
+
+adafruit_feather_esp32_v2.bootloader.tool=esptool_py
+adafruit_feather_esp32_v2.bootloader.tool.default=esptool_py
+
+adafruit_feather_esp32_v2.upload.tool=esptool_py
+adafruit_feather_esp32_v2.upload.tool.default=esptool_py
+adafruit_feather_esp32_v2.upload.tool.network=esp_ota
+
+adafruit_feather_esp32_v2.upload.maximum_size=1310720
+adafruit_feather_esp32_v2.upload.maximum_data_size=327680
+adafruit_feather_esp32_v2.upload.flags=
+adafruit_feather_esp32_v2.upload.extra_flags=
+
+adafruit_feather_esp32_v2.serial.disableDTR=true
+adafruit_feather_esp32_v2.serial.disableRTS=true
+
+adafruit_feather_esp32_v2.build.tarch=xtensa
+adafruit_feather_esp32_v2.build.bootloader_addr=0x1000
+adafruit_feather_esp32_v2.build.target=esp32
+adafruit_feather_esp32_v2.build.mcu=esp32
+adafruit_feather_esp32_v2.build.core=esp32
+adafruit_feather_esp32_v2.build.variant=adafruit_feather_esp32_v2
+adafruit_feather_esp32_v2.build.board=ADAFRUIT_FEATHER_ESP32_V2
+
+adafruit_feather_esp32_v2.build.f_cpu=240000000L
+adafruit_feather_esp32_v2.build.flash_size=8MB
+adafruit_feather_esp32_v2.build.flash_freq=80m
+adafruit_feather_esp32_v2.build.flash_mode=dio
+adafruit_feather_esp32_v2.build.boot=dio
+adafruit_feather_esp32_v2.build.partitions=default
+adafruit_feather_esp32_v2.build.defines=
+adafruit_feather_esp32_v2.build.loop_core=
+adafruit_feather_esp32_v2.build.event_core=
+
+adafruit_feather_esp32_v2.menu.LoopCore.1=Core 1
+adafruit_feather_esp32_v2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_feather_esp32_v2.menu.LoopCore.0=Core 0
+adafruit_feather_esp32_v2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_feather_esp32_v2.menu.EventsCore.1=Core 1
+adafruit_feather_esp32_v2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_feather_esp32_v2.menu.EventsCore.0=Core 0
+adafruit_feather_esp32_v2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_feather_esp32_v2.menu.PSRAM.enabled=Enabled
+adafruit_feather_esp32_v2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+adafruit_feather_esp32_v2.menu.PSRAM.disabled=Disabled
+adafruit_feather_esp32_v2.menu.PSRAM.disabled.build.defines=
+
+adafruit_feather_esp32_v2.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32_v2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+adafruit_feather_esp32_v2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+adafruit_feather_esp32_v2.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.2MB APP / 5.3MB SPIFFS)
+adafruit_feather_esp32_v2.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB
+adafruit_feather_esp32_v2.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720
+
+adafruit_feather_esp32_v2.menu.CPUFreq.240=240MHz (WiFi/BT)
+adafruit_feather_esp32_v2.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_feather_esp32_v2.menu.CPUFreq.160=160MHz (WiFi/BT)
+adafruit_feather_esp32_v2.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_feather_esp32_v2.menu.CPUFreq.80=80MHz (WiFi/BT)
+adafruit_feather_esp32_v2.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_feather_esp32_v2.menu.CPUFreq.40=40MHz
+adafruit_feather_esp32_v2.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_feather_esp32_v2.menu.CPUFreq.20=20MHz
+adafruit_feather_esp32_v2.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_feather_esp32_v2.menu.CPUFreq.10=10MHz
+adafruit_feather_esp32_v2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_feather_esp32_v2.menu.FlashFreq.80=80MHz
+adafruit_feather_esp32_v2.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_feather_esp32_v2.menu.FlashFreq.40=40MHz
+adafruit_feather_esp32_v2.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_feather_esp32_v2.menu.FlashSize.8M=8MB (64Mb)
+adafruit_feather_esp32_v2.menu.FlashSize.8M.build.flash_size=8MB
+
+adafruit_feather_esp32_v2.menu.UploadSpeed.921600=921600
+adafruit_feather_esp32_v2.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_feather_esp32_v2.menu.UploadSpeed.115200=115200
+adafruit_feather_esp32_v2.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_feather_esp32_v2.menu.UploadSpeed.256000.windows=256000
+adafruit_feather_esp32_v2.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_feather_esp32_v2.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_feather_esp32_v2.menu.UploadSpeed.230400=230400
+adafruit_feather_esp32_v2.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_feather_esp32_v2.menu.UploadSpeed.460800.linux=460800
+adafruit_feather_esp32_v2.menu.UploadSpeed.460800.macosx=460800
+adafruit_feather_esp32_v2.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_feather_esp32_v2.menu.UploadSpeed.512000.windows=512000
+adafruit_feather_esp32_v2.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_feather_esp32_v2.menu.DebugLevel.none=None
+adafruit_feather_esp32_v2.menu.DebugLevel.none.build.code_debug=0
+adafruit_feather_esp32_v2.menu.DebugLevel.error=Error
+adafruit_feather_esp32_v2.menu.DebugLevel.error.build.code_debug=1
+adafruit_feather_esp32_v2.menu.DebugLevel.warn=Warn
+adafruit_feather_esp32_v2.menu.DebugLevel.warn.build.code_debug=2
+adafruit_feather_esp32_v2.menu.DebugLevel.info=Info
+adafruit_feather_esp32_v2.menu.DebugLevel.info.build.code_debug=3
+adafruit_feather_esp32_v2.menu.DebugLevel.debug=Debug
+adafruit_feather_esp32_v2.menu.DebugLevel.debug.build.code_debug=4
+adafruit_feather_esp32_v2.menu.DebugLevel.verbose=Verbose
+adafruit_feather_esp32_v2.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_feather_esp32_v2.menu.EraseFlash.none=Disabled
+adafruit_feather_esp32_v2.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_feather_esp32_v2.menu.EraseFlash.all=Enabled
+adafruit_feather_esp32_v2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_feather_esp32_v2.menu.ZigbeeMode.default=Disabled
+adafruit_feather_esp32_v2.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_feather_esp32_v2.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_feather_esp32_v2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_feather_esp32_v2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_feather_esp32_v2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Feather ESP32-S2
+
+adafruit_feather_esp32s2.name=Adafruit Feather ESP32-S2
+adafruit_feather_esp32s2.vid.0=0x239A
+adafruit_feather_esp32s2.pid.0=0x80EB
+adafruit_feather_esp32s2.vid.1=0x239A
+adafruit_feather_esp32s2.pid.1=0x00EB
+adafruit_feather_esp32s2.vid.2=0x239A
+adafruit_feather_esp32s2.pid.2=0x80EC
+adafruit_feather_esp32s2.upload_port.0.vid=0x239A
+adafruit_feather_esp32s2.upload_port.0.pid=0x80EB
+adafruit_feather_esp32s2.upload_port.1.vid=0x239A
+adafruit_feather_esp32s2.upload_port.1.pid=0x00EB
+adafruit_feather_esp32s2.upload_port.2.vid=0x239A
+adafruit_feather_esp32s2.upload_port.2.pid=0x80EC
+
+adafruit_feather_esp32s2.bootloader.tool=esptool_py
+adafruit_feather_esp32s2.bootloader.tool.default=esptool_py
+
+adafruit_feather_esp32s2.upload.tool=esptool_py
+adafruit_feather_esp32s2.upload.tool.default=esptool_py
+adafruit_feather_esp32s2.upload.tool.network=esp_ota
+
+adafruit_feather_esp32s2.upload.maximum_size=1310720
+adafruit_feather_esp32s2.upload.maximum_data_size=327680
+adafruit_feather_esp32s2.upload.flags=
+adafruit_feather_esp32s2.upload.extra_flags=
+adafruit_feather_esp32s2.upload.use_1200bps_touch=true
+adafruit_feather_esp32s2.upload.wait_for_upload_port=true
+
+adafruit_feather_esp32s2.serial.disableDTR=false
+adafruit_feather_esp32s2.serial.disableRTS=false
+
+adafruit_feather_esp32s2.build.tarch=xtensa
+adafruit_feather_esp32s2.build.bootloader_addr=0x1000
+adafruit_feather_esp32s2.build.target=esp32s2
+adafruit_feather_esp32s2.build.mcu=esp32s2
+adafruit_feather_esp32s2.build.core=esp32
+adafruit_feather_esp32s2.build.variant=adafruit_feather_esp32s2
+adafruit_feather_esp32s2.build.board=ADAFRUIT_FEATHER_ESP32S2
+
+adafruit_feather_esp32s2.build.cdc_on_boot=1
+adafruit_feather_esp32s2.build.msc_on_boot=0
+adafruit_feather_esp32s2.build.dfu_on_boot=0
+adafruit_feather_esp32s2.build.f_cpu=240000000L
+adafruit_feather_esp32s2.build.flash_size=4MB
+adafruit_feather_esp32s2.build.flash_freq=80m
+adafruit_feather_esp32s2.build.flash_mode=dio
+adafruit_feather_esp32s2.build.boot=qio
+adafruit_feather_esp32s2.build.partitions=default
+adafruit_feather_esp32s2.build.defines=
+
+adafruit_feather_esp32s2.menu.CDCOnBoot.cdc=Enabled
+adafruit_feather_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_feather_esp32s2.menu.CDCOnBoot.default=Disabled
+adafruit_feather_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_feather_esp32s2.menu.MSCOnBoot.default=Disabled
+adafruit_feather_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_feather_esp32s2.menu.MSCOnBoot.msc=Enabled
+adafruit_feather_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_feather_esp32s2.menu.DFUOnBoot.default=Disabled
+adafruit_feather_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_feather_esp32s2.menu.DFUOnBoot.dfu=Enabled
+adafruit_feather_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_feather_esp32s2.menu.UploadMode.cdc=Internal USB
+adafruit_feather_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_feather_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_feather_esp32s2.menu.UploadMode.default=UART0
+adafruit_feather_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_feather_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_feather_esp32s2.menu.PSRAM.enabled=Enabled
+adafruit_feather_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_feather_esp32s2.menu.PSRAM.disabled=Disabled
+adafruit_feather_esp32s2.menu.PSRAM.disabled.build.defines=
+
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_feather_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.default.build.partitions=default
+adafruit_feather_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_feather_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_feather_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_feather_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_feather_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_feather_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_feather_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_feather_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_feather_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_feather_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_feather_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_feather_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_feather_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_feather_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_feather_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_feather_esp32s2.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_feather_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_feather_esp32s2.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_feather_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_feather_esp32s2.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_feather_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_feather_esp32s2.menu.CPUFreq.40=40MHz
+adafruit_feather_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_feather_esp32s2.menu.CPUFreq.20=20MHz
+adafruit_feather_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_feather_esp32s2.menu.CPUFreq.10=10MHz
+adafruit_feather_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_feather_esp32s2.menu.FlashMode.qio=QIO
+adafruit_feather_esp32s2.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_feather_esp32s2.menu.FlashMode.qio.build.boot=qio
+adafruit_feather_esp32s2.menu.FlashMode.dio=DIO
+adafruit_feather_esp32s2.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_feather_esp32s2.menu.FlashMode.dio.build.boot=dio
+
+adafruit_feather_esp32s2.menu.FlashFreq.80=80MHz
+adafruit_feather_esp32s2.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_feather_esp32s2.menu.FlashFreq.40=40MHz
+adafruit_feather_esp32s2.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_feather_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+adafruit_feather_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_feather_esp32s2.menu.UploadSpeed.921600=921600
+adafruit_feather_esp32s2.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_feather_esp32s2.menu.UploadSpeed.115200=115200
+adafruit_feather_esp32s2.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_feather_esp32s2.menu.UploadSpeed.256000.windows=256000
+adafruit_feather_esp32s2.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_feather_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_feather_esp32s2.menu.UploadSpeed.230400=230400
+adafruit_feather_esp32s2.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_feather_esp32s2.menu.UploadSpeed.460800.linux=460800
+adafruit_feather_esp32s2.menu.UploadSpeed.460800.macosx=460800
+adafruit_feather_esp32s2.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_feather_esp32s2.menu.UploadSpeed.512000.windows=512000
+adafruit_feather_esp32s2.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_feather_esp32s2.menu.DebugLevel.none=None
+adafruit_feather_esp32s2.menu.DebugLevel.none.build.code_debug=0
+adafruit_feather_esp32s2.menu.DebugLevel.error=Error
+adafruit_feather_esp32s2.menu.DebugLevel.error.build.code_debug=1
+adafruit_feather_esp32s2.menu.DebugLevel.warn=Warn
+adafruit_feather_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+adafruit_feather_esp32s2.menu.DebugLevel.info=Info
+adafruit_feather_esp32s2.menu.DebugLevel.info.build.code_debug=3
+adafruit_feather_esp32s2.menu.DebugLevel.debug=Debug
+adafruit_feather_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+adafruit_feather_esp32s2.menu.DebugLevel.verbose=Verbose
+adafruit_feather_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_feather_esp32s2.menu.EraseFlash.none=Disabled
+adafruit_feather_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_feather_esp32s2.menu.EraseFlash.all=Enabled
+adafruit_feather_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_feather_esp32s2.menu.ZigbeeMode.default=Disabled
+adafruit_feather_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_feather_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_feather_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_feather_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_feather_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Feather ESP32-S2 TFT
+
+adafruit_feather_esp32s2_tft.name=Adafruit Feather ESP32-S2 TFT
+adafruit_feather_esp32s2_tft.vid.0=0x239A
+adafruit_feather_esp32s2_tft.pid.0=0x810F
+adafruit_feather_esp32s2_tft.vid.1=0x239A
+adafruit_feather_esp32s2_tft.pid.1=0x010F
+adafruit_feather_esp32s2_tft.vid.2=0x239A
+adafruit_feather_esp32s2_tft.pid.2=0x8110
+adafruit_feather_esp32s2_tft.upload_port.0.vid=0x239A
+adafruit_feather_esp32s2_tft.upload_port.0.pid=0x810F
+adafruit_feather_esp32s2_tft.upload_port.1.vid=0x239A
+adafruit_feather_esp32s2_tft.upload_port.1.pid=0x010F
+adafruit_feather_esp32s2_tft.upload_port.2.vid=0x239A
+adafruit_feather_esp32s2_tft.upload_port.2.pid=0x8110
+
+adafruit_feather_esp32s2_tft.bootloader.tool=esptool_py
+adafruit_feather_esp32s2_tft.bootloader.tool.default=esptool_py
+
+adafruit_feather_esp32s2_tft.upload.tool=esptool_py
+adafruit_feather_esp32s2_tft.upload.tool.default=esptool_py
+adafruit_feather_esp32s2_tft.upload.tool.network=esp_ota
+
+adafruit_feather_esp32s2_tft.upload.maximum_size=1310720
+adafruit_feather_esp32s2_tft.upload.maximum_data_size=327680
+adafruit_feather_esp32s2_tft.upload.flags=
+adafruit_feather_esp32s2_tft.upload.extra_flags=
+adafruit_feather_esp32s2_tft.upload.use_1200bps_touch=true
+adafruit_feather_esp32s2_tft.upload.wait_for_upload_port=true
+
+adafruit_feather_esp32s2_tft.serial.disableDTR=false
+adafruit_feather_esp32s2_tft.serial.disableRTS=false
+
+adafruit_feather_esp32s2_tft.build.tarch=xtensa
+adafruit_feather_esp32s2_tft.build.bootloader_addr=0x1000
+adafruit_feather_esp32s2_tft.build.target=esp32s2
+adafruit_feather_esp32s2_tft.build.mcu=esp32s2
+adafruit_feather_esp32s2_tft.build.core=esp32
+adafruit_feather_esp32s2_tft.build.variant=adafruit_feather_esp32s2_tft
+adafruit_feather_esp32s2_tft.build.board=ADAFRUIT_FEATHER_ESP32S2_TFT
+
+adafruit_feather_esp32s2_tft.build.cdc_on_boot=1
+adafruit_feather_esp32s2_tft.build.msc_on_boot=0
+adafruit_feather_esp32s2_tft.build.dfu_on_boot=0
+adafruit_feather_esp32s2_tft.build.f_cpu=240000000L
+adafruit_feather_esp32s2_tft.build.flash_size=4MB
+adafruit_feather_esp32s2_tft.build.flash_freq=80m
+adafruit_feather_esp32s2_tft.build.flash_mode=dio
+adafruit_feather_esp32s2_tft.build.boot=qio
+adafruit_feather_esp32s2_tft.build.partitions=default
+adafruit_feather_esp32s2_tft.build.defines=
+
+adafruit_feather_esp32s2_tft.menu.CDCOnBoot.cdc=Enabled
+adafruit_feather_esp32s2_tft.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_feather_esp32s2_tft.menu.CDCOnBoot.default=Disabled
+adafruit_feather_esp32s2_tft.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_feather_esp32s2_tft.menu.MSCOnBoot.default=Disabled
+adafruit_feather_esp32s2_tft.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_feather_esp32s2_tft.menu.MSCOnBoot.msc=Enabled
+adafruit_feather_esp32s2_tft.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_feather_esp32s2_tft.menu.DFUOnBoot.default=Disabled
+adafruit_feather_esp32s2_tft.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_feather_esp32s2_tft.menu.DFUOnBoot.dfu=Enabled
+adafruit_feather_esp32s2_tft.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_feather_esp32s2_tft.menu.UploadMode.cdc=Internal USB
+adafruit_feather_esp32s2_tft.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_feather_esp32s2_tft.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_feather_esp32s2_tft.menu.UploadMode.default=UART0
+adafruit_feather_esp32s2_tft.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_feather_esp32s2_tft.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_feather_esp32s2_tft.menu.PSRAM.enabled=Enabled
+adafruit_feather_esp32s2_tft.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_feather_esp32s2_tft.menu.PSRAM.disabled=Disabled
+adafruit_feather_esp32s2_tft.menu.PSRAM.disabled.build.defines=
+
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.default.build.partitions=default
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_feather_esp32s2_tft.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_feather_esp32s2_tft.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_feather_esp32s2_tft.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_feather_esp32s2_tft.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_feather_esp32s2_tft.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_feather_esp32s2_tft.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_feather_esp32s2_tft.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_feather_esp32s2_tft.menu.CPUFreq.40=40MHz
+adafruit_feather_esp32s2_tft.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_feather_esp32s2_tft.menu.CPUFreq.20=20MHz
+adafruit_feather_esp32s2_tft.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_feather_esp32s2_tft.menu.CPUFreq.10=10MHz
+adafruit_feather_esp32s2_tft.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_feather_esp32s2_tft.menu.FlashMode.qio=QIO
+adafruit_feather_esp32s2_tft.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_feather_esp32s2_tft.menu.FlashMode.qio.build.boot=qio
+adafruit_feather_esp32s2_tft.menu.FlashMode.dio=DIO
+adafruit_feather_esp32s2_tft.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_feather_esp32s2_tft.menu.FlashMode.dio.build.boot=dio
+
+adafruit_feather_esp32s2_tft.menu.FlashFreq.80=80MHz
+adafruit_feather_esp32s2_tft.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_feather_esp32s2_tft.menu.FlashFreq.40=40MHz
+adafruit_feather_esp32s2_tft.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_feather_esp32s2_tft.menu.FlashSize.4M=4MB (32Mb)
+adafruit_feather_esp32s2_tft.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.921600=921600
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.115200=115200
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.256000.windows=256000
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.230400=230400
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.460800.linux=460800
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.460800.macosx=460800
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.512000.windows=512000
+adafruit_feather_esp32s2_tft.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_feather_esp32s2_tft.menu.DebugLevel.none=None
+adafruit_feather_esp32s2_tft.menu.DebugLevel.none.build.code_debug=0
+adafruit_feather_esp32s2_tft.menu.DebugLevel.error=Error
+adafruit_feather_esp32s2_tft.menu.DebugLevel.error.build.code_debug=1
+adafruit_feather_esp32s2_tft.menu.DebugLevel.warn=Warn
+adafruit_feather_esp32s2_tft.menu.DebugLevel.warn.build.code_debug=2
+adafruit_feather_esp32s2_tft.menu.DebugLevel.info=Info
+adafruit_feather_esp32s2_tft.menu.DebugLevel.info.build.code_debug=3
+adafruit_feather_esp32s2_tft.menu.DebugLevel.debug=Debug
+adafruit_feather_esp32s2_tft.menu.DebugLevel.debug.build.code_debug=4
+adafruit_feather_esp32s2_tft.menu.DebugLevel.verbose=Verbose
+adafruit_feather_esp32s2_tft.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_feather_esp32s2_tft.menu.EraseFlash.none=Disabled
+adafruit_feather_esp32s2_tft.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_feather_esp32s2_tft.menu.EraseFlash.all=Enabled
+adafruit_feather_esp32s2_tft.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_feather_esp32s2_tft.menu.ZigbeeMode.default=Disabled
+adafruit_feather_esp32s2_tft.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_feather_esp32s2_tft.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_feather_esp32s2_tft.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_feather_esp32s2_tft.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_feather_esp32s2_tft.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Feather ESP32-S2 Reverse TFT
+
+adafruit_feather_esp32s2_reversetft.name=Adafruit Feather ESP32-S2 Reverse TFT
+adafruit_feather_esp32s2_reversetft.vid.0=0x239A
+adafruit_feather_esp32s2_reversetft.pid.0=0x80ED
+adafruit_feather_esp32s2_reversetft.vid.1=0x239A
+adafruit_feather_esp32s2_reversetft.pid.1=0x00ED
+adafruit_feather_esp32s2_reversetft.vid.2=0x239A
+adafruit_feather_esp32s2_reversetft.pid.2=0x80EE
+adafruit_feather_esp32s2_reversetft.upload_port.0.vid=0x239A
+adafruit_feather_esp32s2_reversetft.upload_port.0.pid=0x80ED
+adafruit_feather_esp32s2_reversetft.upload_port.1.vid=0x239A
+adafruit_feather_esp32s2_reversetft.upload_port.1.pid=0x00ED
+adafruit_feather_esp32s2_reversetft.upload_port.2.vid=0x239A
+adafruit_feather_esp32s2_reversetft.upload_port.2.pid=0x80EE
+
+adafruit_feather_esp32s2_reversetft.bootloader.tool=esptool_py
+adafruit_feather_esp32s2_reversetft.bootloader.tool.default=esptool_py
+
+adafruit_feather_esp32s2_reversetft.upload.tool=esptool_py
+adafruit_feather_esp32s2_reversetft.upload.tool.default=esptool_py
+adafruit_feather_esp32s2_reversetft.upload.tool.network=esp_ota
+
+adafruit_feather_esp32s2_reversetft.upload.maximum_size=1310720
+adafruit_feather_esp32s2_reversetft.upload.maximum_data_size=327680
+adafruit_feather_esp32s2_reversetft.upload.flags=
+adafruit_feather_esp32s2_reversetft.upload.extra_flags=
+adafruit_feather_esp32s2_reversetft.upload.use_1200bps_touch=true
+adafruit_feather_esp32s2_reversetft.upload.wait_for_upload_port=true
+
+adafruit_feather_esp32s2_reversetft.serial.disableDTR=false
+adafruit_feather_esp32s2_reversetft.serial.disableRTS=false
+
+adafruit_feather_esp32s2_reversetft.build.tarch=xtensa
+adafruit_feather_esp32s2_reversetft.build.bootloader_addr=0x1000
+adafruit_feather_esp32s2_reversetft.build.target=esp32s2
+adafruit_feather_esp32s2_reversetft.build.mcu=esp32s2
+adafruit_feather_esp32s2_reversetft.build.core=esp32
+adafruit_feather_esp32s2_reversetft.build.variant=adafruit_feather_esp32s2_reversetft
+adafruit_feather_esp32s2_reversetft.build.board=ADAFRUIT_FEATHER_ESP32S2_REVTFT
+
+adafruit_feather_esp32s2_reversetft.build.cdc_on_boot=1
+adafruit_feather_esp32s2_reversetft.build.msc_on_boot=0
+adafruit_feather_esp32s2_reversetft.build.dfu_on_boot=0
+adafruit_feather_esp32s2_reversetft.build.f_cpu=240000000L
+adafruit_feather_esp32s2_reversetft.build.flash_size=4MB
+adafruit_feather_esp32s2_reversetft.build.flash_freq=80m
+adafruit_feather_esp32s2_reversetft.build.flash_mode=dio
+adafruit_feather_esp32s2_reversetft.build.boot=qio
+adafruit_feather_esp32s2_reversetft.build.partitions=default
+adafruit_feather_esp32s2_reversetft.build.defines=
+
+adafruit_feather_esp32s2_reversetft.menu.CDCOnBoot.cdc=Enabled
+adafruit_feather_esp32s2_reversetft.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_feather_esp32s2_reversetft.menu.CDCOnBoot.default=Disabled
+adafruit_feather_esp32s2_reversetft.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_feather_esp32s2_reversetft.menu.MSCOnBoot.default=Disabled
+adafruit_feather_esp32s2_reversetft.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_feather_esp32s2_reversetft.menu.MSCOnBoot.msc=Enabled
+adafruit_feather_esp32s2_reversetft.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_feather_esp32s2_reversetft.menu.DFUOnBoot.default=Disabled
+adafruit_feather_esp32s2_reversetft.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_feather_esp32s2_reversetft.menu.DFUOnBoot.dfu=Enabled
+adafruit_feather_esp32s2_reversetft.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_feather_esp32s2_reversetft.menu.UploadMode.cdc=Internal USB
+adafruit_feather_esp32s2_reversetft.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_feather_esp32s2_reversetft.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_feather_esp32s2_reversetft.menu.UploadMode.default=UART0
+adafruit_feather_esp32s2_reversetft.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_feather_esp32s2_reversetft.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_feather_esp32s2_reversetft.menu.PSRAM.enabled=Enabled
+adafruit_feather_esp32s2_reversetft.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_feather_esp32s2_reversetft.menu.PSRAM.disabled=Disabled
+adafruit_feather_esp32s2_reversetft.menu.PSRAM.disabled.build.defines=
+
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.default.build.partitions=default
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_feather_esp32s2_reversetft.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.40=40MHz
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.20=20MHz
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.10=10MHz
+adafruit_feather_esp32s2_reversetft.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_feather_esp32s2_reversetft.menu.FlashMode.qio=QIO
+adafruit_feather_esp32s2_reversetft.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_feather_esp32s2_reversetft.menu.FlashMode.qio.build.boot=qio
+adafruit_feather_esp32s2_reversetft.menu.FlashMode.dio=DIO
+adafruit_feather_esp32s2_reversetft.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_feather_esp32s2_reversetft.menu.FlashMode.dio.build.boot=dio
+
+adafruit_feather_esp32s2_reversetft.menu.FlashFreq.80=80MHz
+adafruit_feather_esp32s2_reversetft.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_feather_esp32s2_reversetft.menu.FlashFreq.40=40MHz
+adafruit_feather_esp32s2_reversetft.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_feather_esp32s2_reversetft.menu.FlashSize.4M=4MB (32Mb)
+adafruit_feather_esp32s2_reversetft.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.921600=921600
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.115200=115200
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.256000.windows=256000
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.230400=230400
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.460800.linux=460800
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.460800.macosx=460800
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.512000.windows=512000
+adafruit_feather_esp32s2_reversetft.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.none=None
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.none.build.code_debug=0
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.error=Error
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.error.build.code_debug=1
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.warn=Warn
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.warn.build.code_debug=2
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.info=Info
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.info.build.code_debug=3
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.debug=Debug
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.debug.build.code_debug=4
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.verbose=Verbose
+adafruit_feather_esp32s2_reversetft.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_feather_esp32s2_reversetft.menu.EraseFlash.none=Disabled
+adafruit_feather_esp32s2_reversetft.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_feather_esp32s2_reversetft.menu.EraseFlash.all=Enabled
+adafruit_feather_esp32s2_reversetft.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.default=Disabled
+adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_feather_esp32s2_reversetft.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Feather ESP32-S3 2MB PSRAM
+
+adafruit_feather_esp32s3.name=Adafruit Feather ESP32-S3 2MB PSRAM
+adafruit_feather_esp32s3.vid.0=0x239A
+adafruit_feather_esp32s3.pid.0=0x811B
+adafruit_feather_esp32s3.vid.1=0x239A
+adafruit_feather_esp32s3.pid.1=0x011B
+adafruit_feather_esp32s3.vid.2=0x239A
+adafruit_feather_esp32s3.pid.2=0x811C
+adafruit_feather_esp32s3.upload_port.0.vid=0x239A
+adafruit_feather_esp32s3.upload_port.0.pid=0x811B
+adafruit_feather_esp32s3.upload_port.1.vid=0x239A
+adafruit_feather_esp32s3.upload_port.1.pid=0x011B
+adafruit_feather_esp32s3.upload_port.2.vid=0x239A
+adafruit_feather_esp32s3.upload_port.2.pid=0x811C
+
+adafruit_feather_esp32s3.bootloader.tool=esptool_py
+adafruit_feather_esp32s3.bootloader.tool.default=esptool_py
+
+adafruit_feather_esp32s3.upload.tool=esptool_py
+adafruit_feather_esp32s3.upload.tool.default=esptool_py
+adafruit_feather_esp32s3.upload.tool.network=esp_ota
+
+adafruit_feather_esp32s3.upload.maximum_size=1310720
+adafruit_feather_esp32s3.upload.maximum_data_size=327680
+adafruit_feather_esp32s3.upload.flags=
+adafruit_feather_esp32s3.upload.extra_flags=
+adafruit_feather_esp32s3.upload.use_1200bps_touch=true
+adafruit_feather_esp32s3.upload.wait_for_upload_port=true
+
+adafruit_feather_esp32s3.serial.disableDTR=false
+adafruit_feather_esp32s3.serial.disableRTS=false
+
+adafruit_feather_esp32s3.build.tarch=xtensa
+adafruit_feather_esp32s3.build.bootloader_addr=0x0
+adafruit_feather_esp32s3.build.target=esp32s3
+adafruit_feather_esp32s3.build.mcu=esp32s3
+adafruit_feather_esp32s3.build.core=esp32
+adafruit_feather_esp32s3.build.variant=adafruit_feather_esp32s3
+adafruit_feather_esp32s3.build.board=ADAFRUIT_FEATHER_ESP32S3
+
+adafruit_feather_esp32s3.build.usb_mode=0
+adafruit_feather_esp32s3.build.cdc_on_boot=1
+adafruit_feather_esp32s3.build.msc_on_boot=0
+adafruit_feather_esp32s3.build.dfu_on_boot=0
+adafruit_feather_esp32s3.build.f_cpu=240000000L
+adafruit_feather_esp32s3.build.flash_size=4MB
+adafruit_feather_esp32s3.build.flash_freq=80m
+adafruit_feather_esp32s3.build.flash_mode=dio
+adafruit_feather_esp32s3.build.boot=qio
+adafruit_feather_esp32s3.build.partitions=default
+adafruit_feather_esp32s3.build.defines=
+adafruit_feather_esp32s3.build.loop_core=
+adafruit_feather_esp32s3.build.event_core=
+adafruit_feather_esp32s3.build.flash_type=qio
+adafruit_feather_esp32s3.build.psram_type=qspi
+adafruit_feather_esp32s3.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_feather_esp32s3.menu.LoopCore.1=Core 1
+adafruit_feather_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_feather_esp32s3.menu.LoopCore.0=Core 0
+adafruit_feather_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_feather_esp32s3.menu.EventsCore.1=Core 1
+adafruit_feather_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_feather_esp32s3.menu.EventsCore.0=Core 0
+adafruit_feather_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_feather_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_feather_esp32s3.menu.USBMode.default.build.usb_mode=0
+adafruit_feather_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_feather_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_feather_esp32s3.menu.CDCOnBoot.cdc=Enabled
+adafruit_feather_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_feather_esp32s3.menu.CDCOnBoot.default=Disabled
+adafruit_feather_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_feather_esp32s3.menu.MSCOnBoot.default=Disabled
+adafruit_feather_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_feather_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_feather_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_feather_esp32s3.menu.DFUOnBoot.default=Disabled
+adafruit_feather_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_feather_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_feather_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_feather_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_feather_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_feather_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_feather_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_feather_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_feather_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_feather_esp32s3.menu.PSRAM.enabled=QSPI PSRAM
+adafruit_feather_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_feather_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi
+adafruit_feather_esp32s3.menu.PSRAM.disabled=Disabled
+adafruit_feather_esp32s3.menu.PSRAM.disabled.build.defines=
+adafruit_feather_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi
+adafruit_feather_esp32s3.menu.PSRAM.opi=OPI PSRAM
+adafruit_feather_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+adafruit_feather_esp32s3.menu.PSRAM.opi.build.psram_type=opi
+
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_feather_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.default.build.partitions=default
+adafruit_feather_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_feather_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_feather_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_feather_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_feather_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_feather_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_feather_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_feather_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_feather_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_feather_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_feather_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_feather_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_feather_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_feather_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_feather_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_feather_esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_feather_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_feather_esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_feather_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_feather_esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_feather_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_feather_esp32s3.menu.CPUFreq.40=40MHz
+adafruit_feather_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_feather_esp32s3.menu.CPUFreq.20=20MHz
+adafruit_feather_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_feather_esp32s3.menu.CPUFreq.10=10MHz
+adafruit_feather_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_feather_esp32s3.menu.FlashMode.qio=QIO 80MHz
+adafruit_feather_esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_feather_esp32s3.menu.FlashMode.qio.build.boot=qio
+adafruit_feather_esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_feather_esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_feather_esp32s3.menu.FlashMode.qio120=QIO 120MHz
+adafruit_feather_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_feather_esp32s3.menu.FlashMode.qio120.build.boot=qio
+adafruit_feather_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_feather_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_feather_esp32s3.menu.FlashMode.dio=DIO 80MHz
+adafruit_feather_esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_feather_esp32s3.menu.FlashMode.dio.build.boot=dio
+adafruit_feather_esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_feather_esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_feather_esp32s3.menu.FlashMode.opi=OPI 80MHz
+adafruit_feather_esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_feather_esp32s3.menu.FlashMode.opi.build.boot=opi
+adafruit_feather_esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_feather_esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_feather_esp32s3.menu.FlashSize.4M=4MB (32Mb)
+adafruit_feather_esp32s3.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_feather_esp32s3.menu.UploadSpeed.921600=921600
+adafruit_feather_esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_feather_esp32s3.menu.UploadSpeed.115200=115200
+adafruit_feather_esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_feather_esp32s3.menu.UploadSpeed.256000.windows=256000
+adafruit_feather_esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_feather_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_feather_esp32s3.menu.UploadSpeed.230400=230400
+adafruit_feather_esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_feather_esp32s3.menu.UploadSpeed.460800.linux=460800
+adafruit_feather_esp32s3.menu.UploadSpeed.460800.macosx=460800
+adafruit_feather_esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_feather_esp32s3.menu.UploadSpeed.512000.windows=512000
+adafruit_feather_esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_feather_esp32s3.menu.DebugLevel.none=None
+adafruit_feather_esp32s3.menu.DebugLevel.none.build.code_debug=0
+adafruit_feather_esp32s3.menu.DebugLevel.error=Error
+adafruit_feather_esp32s3.menu.DebugLevel.error.build.code_debug=1
+adafruit_feather_esp32s3.menu.DebugLevel.warn=Warn
+adafruit_feather_esp32s3.menu.DebugLevel.warn.build.code_debug=2
+adafruit_feather_esp32s3.menu.DebugLevel.info=Info
+adafruit_feather_esp32s3.menu.DebugLevel.info.build.code_debug=3
+adafruit_feather_esp32s3.menu.DebugLevel.debug=Debug
+adafruit_feather_esp32s3.menu.DebugLevel.debug.build.code_debug=4
+adafruit_feather_esp32s3.menu.DebugLevel.verbose=Verbose
+adafruit_feather_esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_feather_esp32s3.menu.EraseFlash.none=Disabled
+adafruit_feather_esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_feather_esp32s3.menu.EraseFlash.all=Enabled
+adafruit_feather_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_feather_esp32s3.menu.ZigbeeMode.default=Disabled
+adafruit_feather_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_feather_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_feather_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_feather_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_feather_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Feather ESP32-S3 No PSRAM
+
+adafruit_feather_esp32s3_nopsram.name=Adafruit Feather ESP32-S3 No PSRAM
+adafruit_feather_esp32s3_nopsram.vid.0=0x239A
+adafruit_feather_esp32s3_nopsram.pid.0=0x8113
+adafruit_feather_esp32s3_nopsram.vid.1=0x239A
+adafruit_feather_esp32s3_nopsram.pid.1=0x0113
+adafruit_feather_esp32s3_nopsram.vid.2=0x239A
+adafruit_feather_esp32s3_nopsram.pid.2=0x8114
+adafruit_feather_esp32s3_nopsram.upload_port.0.vid=0x239A
+adafruit_feather_esp32s3_nopsram.upload_port.0.pid=0x8113
+adafruit_feather_esp32s3_nopsram.upload_port.1.vid=0x239A
+adafruit_feather_esp32s3_nopsram.upload_port.1.pid=0x0113
+adafruit_feather_esp32s3_nopsram.upload_port.2.vid=0x239A
+adafruit_feather_esp32s3_nopsram.upload_port.2.pid=0x8114
+
+adafruit_feather_esp32s3_nopsram.bootloader.tool=esptool_py
+adafruit_feather_esp32s3_nopsram.bootloader.tool.default=esptool_py
+
+adafruit_feather_esp32s3_nopsram.upload.tool=esptool_py
+adafruit_feather_esp32s3_nopsram.upload.tool.default=esptool_py
+adafruit_feather_esp32s3_nopsram.upload.tool.network=esp_ota
+
+adafruit_feather_esp32s3_nopsram.upload.maximum_size=1310720
+adafruit_feather_esp32s3_nopsram.upload.maximum_data_size=327680
+adafruit_feather_esp32s3_nopsram.upload.flags=
+adafruit_feather_esp32s3_nopsram.upload.extra_flags=
+adafruit_feather_esp32s3_nopsram.upload.use_1200bps_touch=true
+adafruit_feather_esp32s3_nopsram.upload.wait_for_upload_port=true
+
+adafruit_feather_esp32s3_nopsram.serial.disableDTR=false
+adafruit_feather_esp32s3_nopsram.serial.disableRTS=false
+
+adafruit_feather_esp32s3_nopsram.build.tarch=xtensa
+adafruit_feather_esp32s3_nopsram.build.bootloader_addr=0x0
+adafruit_feather_esp32s3_nopsram.build.target=esp32s3
+adafruit_feather_esp32s3_nopsram.build.mcu=esp32s3
+adafruit_feather_esp32s3_nopsram.build.core=esp32
+adafruit_feather_esp32s3_nopsram.build.variant=adafruit_feather_esp32s3_nopsram
+adafruit_feather_esp32s3_nopsram.build.board=ADAFRUIT_FEATHER_ESP32S3_NOPSRAM
+
+adafruit_feather_esp32s3_nopsram.build.usb_mode=0
+adafruit_feather_esp32s3_nopsram.build.cdc_on_boot=1
+adafruit_feather_esp32s3_nopsram.build.msc_on_boot=0
+adafruit_feather_esp32s3_nopsram.build.dfu_on_boot=0
+adafruit_feather_esp32s3_nopsram.build.f_cpu=240000000L
+adafruit_feather_esp32s3_nopsram.build.flash_size=8MB
+adafruit_feather_esp32s3_nopsram.build.flash_freq=80m
+adafruit_feather_esp32s3_nopsram.build.flash_mode=dio
+adafruit_feather_esp32s3_nopsram.build.boot=qio
+adafruit_feather_esp32s3_nopsram.build.partitions=default
+adafruit_feather_esp32s3_nopsram.build.defines=
+adafruit_feather_esp32s3_nopsram.build.loop_core=
+adafruit_feather_esp32s3_nopsram.build.event_core=
+adafruit_feather_esp32s3_nopsram.build.flash_type=qio
+adafruit_feather_esp32s3_nopsram.build.psram_type=qspi
+adafruit_feather_esp32s3_nopsram.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_feather_esp32s3_nopsram.menu.LoopCore.1=Core 1
+adafruit_feather_esp32s3_nopsram.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_feather_esp32s3_nopsram.menu.LoopCore.0=Core 0
+adafruit_feather_esp32s3_nopsram.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_feather_esp32s3_nopsram.menu.EventsCore.1=Core 1
+adafruit_feather_esp32s3_nopsram.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_feather_esp32s3_nopsram.menu.EventsCore.0=Core 0
+adafruit_feather_esp32s3_nopsram.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_feather_esp32s3_nopsram.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_feather_esp32s3_nopsram.menu.USBMode.default.build.usb_mode=0
+adafruit_feather_esp32s3_nopsram.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_feather_esp32s3_nopsram.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_feather_esp32s3_nopsram.menu.CDCOnBoot.cdc=Enabled
+adafruit_feather_esp32s3_nopsram.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_feather_esp32s3_nopsram.menu.CDCOnBoot.default=Disabled
+adafruit_feather_esp32s3_nopsram.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_feather_esp32s3_nopsram.menu.MSCOnBoot.default=Disabled
+adafruit_feather_esp32s3_nopsram.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_feather_esp32s3_nopsram.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_feather_esp32s3_nopsram.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_feather_esp32s3_nopsram.menu.DFUOnBoot.default=Disabled
+adafruit_feather_esp32s3_nopsram.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_feather_esp32s3_nopsram.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_feather_esp32s3_nopsram.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_feather_esp32s3_nopsram.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_feather_esp32s3_nopsram.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_feather_esp32s3_nopsram.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_feather_esp32s3_nopsram.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_feather_esp32s3_nopsram.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_feather_esp32s3_nopsram.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FATFS)
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-8MB
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota=TinyUF2 8MB No OTA (4MB APP/3.7MB FATFS)
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-8MB-noota
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+adafruit_feather_esp32s3_nopsram.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.40=40MHz
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.20=20MHz
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.10=10MHz
+adafruit_feather_esp32s3_nopsram.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio=QIO 80MHz
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio.build.boot=qio
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120=QIO 120MHz
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120.build.boot=qio
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio=DIO 80MHz
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio.build.boot=dio
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi=OPI 80MHz
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi.build.boot=opi
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_feather_esp32s3_nopsram.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_feather_esp32s3_nopsram.menu.FlashSize.8M=8MB (64Mb)
+adafruit_feather_esp32s3_nopsram.menu.FlashSize.8M.build.flash_size=8MB
+
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.921600=921600
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.115200=115200
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.256000.windows=256000
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.230400=230400
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.460800.linux=460800
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.460800.macosx=460800
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.512000.windows=512000
+adafruit_feather_esp32s3_nopsram.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.none=None
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.none.build.code_debug=0
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.error=Error
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.error.build.code_debug=1
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.warn=Warn
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.warn.build.code_debug=2
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.info=Info
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.info.build.code_debug=3
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.debug=Debug
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.debug.build.code_debug=4
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.verbose=Verbose
+adafruit_feather_esp32s3_nopsram.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_feather_esp32s3_nopsram.menu.EraseFlash.none=Disabled
+adafruit_feather_esp32s3_nopsram.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_feather_esp32s3_nopsram.menu.EraseFlash.all=Enabled
+adafruit_feather_esp32s3_nopsram.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.default=Disabled
+adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_feather_esp32s3_nopsram.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Feather ESP32-S3 TFT
+
+adafruit_feather_esp32s3_tft.name=Adafruit Feather ESP32-S3 TFT
+adafruit_feather_esp32s3_tft.vid.0=0x239A
+adafruit_feather_esp32s3_tft.pid.0=0x811D
+adafruit_feather_esp32s3_tft.vid.1=0x239A
+adafruit_feather_esp32s3_tft.pid.1=0x011D
+adafruit_feather_esp32s3_tft.vid.2=0x239A
+adafruit_feather_esp32s3_tft.pid.2=0x811E
+adafruit_feather_esp32s3_tft.upload_port.0.vid=0x239A
+adafruit_feather_esp32s3_tft.upload_port.0.pid=0x811D
+adafruit_feather_esp32s3_tft.upload_port.1.vid=0x239A
+adafruit_feather_esp32s3_tft.upload_port.1.pid=0x011D
+adafruit_feather_esp32s3_tft.upload_port.2.vid=0x239A
+adafruit_feather_esp32s3_tft.upload_port.2.pid=0x811E
+
+adafruit_feather_esp32s3_tft.bootloader.tool=esptool_py
+adafruit_feather_esp32s3_tft.bootloader.tool.default=esptool_py
+
+adafruit_feather_esp32s3_tft.upload.tool=esptool_py
+adafruit_feather_esp32s3_tft.upload.tool.default=esptool_py
+adafruit_feather_esp32s3_tft.upload.tool.network=esp_ota
+
+adafruit_feather_esp32s3_tft.upload.maximum_size=1310720
+adafruit_feather_esp32s3_tft.upload.maximum_data_size=327680
+adafruit_feather_esp32s3_tft.upload.flags=
+adafruit_feather_esp32s3_tft.upload.extra_flags=
+adafruit_feather_esp32s3_tft.upload.use_1200bps_touch=true
+adafruit_feather_esp32s3_tft.upload.wait_for_upload_port=true
+
+adafruit_feather_esp32s3_tft.serial.disableDTR=false
+adafruit_feather_esp32s3_tft.serial.disableRTS=false
+
+adafruit_feather_esp32s3_tft.build.tarch=xtensa
+adafruit_feather_esp32s3_tft.build.bootloader_addr=0x0
+adafruit_feather_esp32s3_tft.build.target=esp32s3
+adafruit_feather_esp32s3_tft.build.mcu=esp32s3
+adafruit_feather_esp32s3_tft.build.core=esp32
+adafruit_feather_esp32s3_tft.build.variant=adafruit_feather_esp32s3_tft
+adafruit_feather_esp32s3_tft.build.board=ADAFRUIT_FEATHER_ESP32S3_TFT
+
+adafruit_feather_esp32s3_tft.build.usb_mode=0
+adafruit_feather_esp32s3_tft.build.cdc_on_boot=1
+adafruit_feather_esp32s3_tft.build.msc_on_boot=0
+adafruit_feather_esp32s3_tft.build.dfu_on_boot=0
+adafruit_feather_esp32s3_tft.build.f_cpu=240000000L
+adafruit_feather_esp32s3_tft.build.flash_size=4MB
+adafruit_feather_esp32s3_tft.build.flash_freq=80m
+adafruit_feather_esp32s3_tft.build.flash_mode=dio
+adafruit_feather_esp32s3_tft.build.boot=qio
+adafruit_feather_esp32s3_tft.build.partitions=default
+adafruit_feather_esp32s3_tft.build.defines=
+adafruit_feather_esp32s3_tft.build.loop_core=
+adafruit_feather_esp32s3_tft.build.event_core=
+adafruit_feather_esp32s3_tft.build.flash_type=qio
+adafruit_feather_esp32s3_tft.build.psram_type=qspi
+adafruit_feather_esp32s3_tft.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_feather_esp32s3_tft.menu.LoopCore.1=Core 1
+adafruit_feather_esp32s3_tft.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_feather_esp32s3_tft.menu.LoopCore.0=Core 0
+adafruit_feather_esp32s3_tft.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_feather_esp32s3_tft.menu.EventsCore.1=Core 1
+adafruit_feather_esp32s3_tft.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_feather_esp32s3_tft.menu.EventsCore.0=Core 0
+adafruit_feather_esp32s3_tft.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_feather_esp32s3_tft.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_feather_esp32s3_tft.menu.USBMode.default.build.usb_mode=0
+adafruit_feather_esp32s3_tft.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_feather_esp32s3_tft.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_feather_esp32s3_tft.menu.CDCOnBoot.cdc=Enabled
+adafruit_feather_esp32s3_tft.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_feather_esp32s3_tft.menu.CDCOnBoot.default=Disabled
+adafruit_feather_esp32s3_tft.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_feather_esp32s3_tft.menu.MSCOnBoot.default=Disabled
+adafruit_feather_esp32s3_tft.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_feather_esp32s3_tft.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_feather_esp32s3_tft.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_feather_esp32s3_tft.menu.DFUOnBoot.default=Disabled
+adafruit_feather_esp32s3_tft.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_feather_esp32s3_tft.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_feather_esp32s3_tft.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_feather_esp32s3_tft.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_feather_esp32s3_tft.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_feather_esp32s3_tft.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_feather_esp32s3_tft.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_feather_esp32s3_tft.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_feather_esp32s3_tft.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_feather_esp32s3_tft.menu.PSRAM.enabled=QSPI PSRAM
+adafruit_feather_esp32s3_tft.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_feather_esp32s3_tft.menu.PSRAM.enabled.build.psram_type=qspi
+adafruit_feather_esp32s3_tft.menu.PSRAM.disabled=Disabled
+adafruit_feather_esp32s3_tft.menu.PSRAM.disabled.build.defines=
+adafruit_feather_esp32s3_tft.menu.PSRAM.disabled.build.psram_type=qspi
+adafruit_feather_esp32s3_tft.menu.PSRAM.opi=OPI PSRAM
+adafruit_feather_esp32s3_tft.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+adafruit_feather_esp32s3_tft.menu.PSRAM.opi.build.psram_type=opi
+
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.default.build.partitions=default
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_feather_esp32s3_tft.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_feather_esp32s3_tft.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_feather_esp32s3_tft.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_feather_esp32s3_tft.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_feather_esp32s3_tft.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_feather_esp32s3_tft.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_feather_esp32s3_tft.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_feather_esp32s3_tft.menu.CPUFreq.40=40MHz
+adafruit_feather_esp32s3_tft.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_feather_esp32s3_tft.menu.CPUFreq.20=20MHz
+adafruit_feather_esp32s3_tft.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_feather_esp32s3_tft.menu.CPUFreq.10=10MHz
+adafruit_feather_esp32s3_tft.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio=QIO 80MHz
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio.build.boot=qio
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio120=QIO 120MHz
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio120.build.boot=qio
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_feather_esp32s3_tft.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_feather_esp32s3_tft.menu.FlashMode.dio=DIO 80MHz
+adafruit_feather_esp32s3_tft.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_feather_esp32s3_tft.menu.FlashMode.dio.build.boot=dio
+adafruit_feather_esp32s3_tft.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_feather_esp32s3_tft.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_feather_esp32s3_tft.menu.FlashMode.opi=OPI 80MHz
+adafruit_feather_esp32s3_tft.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_feather_esp32s3_tft.menu.FlashMode.opi.build.boot=opi
+adafruit_feather_esp32s3_tft.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_feather_esp32s3_tft.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_feather_esp32s3_tft.menu.FlashSize.4M=4MB (32Mb)
+adafruit_feather_esp32s3_tft.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.921600=921600
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.115200=115200
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.256000.windows=256000
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.230400=230400
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.460800.linux=460800
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.460800.macosx=460800
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.512000.windows=512000
+adafruit_feather_esp32s3_tft.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_feather_esp32s3_tft.menu.DebugLevel.none=None
+adafruit_feather_esp32s3_tft.menu.DebugLevel.none.build.code_debug=0
+adafruit_feather_esp32s3_tft.menu.DebugLevel.error=Error
+adafruit_feather_esp32s3_tft.menu.DebugLevel.error.build.code_debug=1
+adafruit_feather_esp32s3_tft.menu.DebugLevel.warn=Warn
+adafruit_feather_esp32s3_tft.menu.DebugLevel.warn.build.code_debug=2
+adafruit_feather_esp32s3_tft.menu.DebugLevel.info=Info
+adafruit_feather_esp32s3_tft.menu.DebugLevel.info.build.code_debug=3
+adafruit_feather_esp32s3_tft.menu.DebugLevel.debug=Debug
+adafruit_feather_esp32s3_tft.menu.DebugLevel.debug.build.code_debug=4
+adafruit_feather_esp32s3_tft.menu.DebugLevel.verbose=Verbose
+adafruit_feather_esp32s3_tft.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_feather_esp32s3_tft.menu.EraseFlash.none=Disabled
+adafruit_feather_esp32s3_tft.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_feather_esp32s3_tft.menu.EraseFlash.all=Enabled
+adafruit_feather_esp32s3_tft.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_feather_esp32s3_tft.menu.ZigbeeMode.default=Disabled
+adafruit_feather_esp32s3_tft.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_feather_esp32s3_tft.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_feather_esp32s3_tft.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_feather_esp32s3_tft.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_feather_esp32s3_tft.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Feather ESP32-S3 Reverse TFT
+
+adafruit_feather_esp32s3_reversetft.name=Adafruit Feather ESP32-S3 Reverse TFT
+adafruit_feather_esp32s3_reversetft.vid.0=0x239A
+adafruit_feather_esp32s3_reversetft.pid.0=0x8123
+adafruit_feather_esp32s3_reversetft.vid.1=0x239A
+adafruit_feather_esp32s3_reversetft.pid.1=0x0123
+adafruit_feather_esp32s3_reversetft.vid.2=0x239A
+adafruit_feather_esp32s3_reversetft.pid.2=0x8124
+adafruit_feather_esp32s3_reversetft.upload_port.0.vid=0x239A
+adafruit_feather_esp32s3_reversetft.upload_port.0.pid=0x8123
+adafruit_feather_esp32s3_reversetft.upload_port.1.vid=0x239A
+adafruit_feather_esp32s3_reversetft.upload_port.1.pid=0x0123
+adafruit_feather_esp32s3_reversetft.upload_port.2.vid=0x239A
+adafruit_feather_esp32s3_reversetft.upload_port.2.pid=0x8124
+
+adafruit_feather_esp32s3_reversetft.bootloader.tool=esptool_py
+adafruit_feather_esp32s3_reversetft.bootloader.tool.default=esptool_py
+
+adafruit_feather_esp32s3_reversetft.upload.tool=esptool_py
+adafruit_feather_esp32s3_reversetft.upload.tool.default=esptool_py
+adafruit_feather_esp32s3_reversetft.upload.tool.network=esp_ota
+
+adafruit_feather_esp32s3_reversetft.upload.maximum_size=1310720
+adafruit_feather_esp32s3_reversetft.upload.maximum_data_size=327680
+adafruit_feather_esp32s3_reversetft.upload.flags=
+adafruit_feather_esp32s3_reversetft.upload.extra_flags=
+adafruit_feather_esp32s3_reversetft.upload.use_1200bps_touch=true
+adafruit_feather_esp32s3_reversetft.upload.wait_for_upload_port=true
+
+adafruit_feather_esp32s3_reversetft.serial.disableDTR=false
+adafruit_feather_esp32s3_reversetft.serial.disableRTS=false
+
+adafruit_feather_esp32s3_reversetft.build.tarch=xtensa
+adafruit_feather_esp32s3_reversetft.build.bootloader_addr=0x0
+adafruit_feather_esp32s3_reversetft.build.target=esp32s3
+adafruit_feather_esp32s3_reversetft.build.mcu=esp32s3
+adafruit_feather_esp32s3_reversetft.build.core=esp32
+adafruit_feather_esp32s3_reversetft.build.variant=adafruit_feather_esp32s3_reversetft
+adafruit_feather_esp32s3_reversetft.build.board=ADAFRUIT_FEATHER_ESP32S3_REVTFT
+
+adafruit_feather_esp32s3_reversetft.build.usb_mode=0
+adafruit_feather_esp32s3_reversetft.build.cdc_on_boot=1
+adafruit_feather_esp32s3_reversetft.build.msc_on_boot=0
+adafruit_feather_esp32s3_reversetft.build.dfu_on_boot=0
+adafruit_feather_esp32s3_reversetft.build.f_cpu=240000000L
+adafruit_feather_esp32s3_reversetft.build.flash_size=4MB
+adafruit_feather_esp32s3_reversetft.build.flash_freq=80m
+adafruit_feather_esp32s3_reversetft.build.flash_mode=dio
+adafruit_feather_esp32s3_reversetft.build.boot=qio
+adafruit_feather_esp32s3_reversetft.build.partitions=default
+adafruit_feather_esp32s3_reversetft.build.defines=
+adafruit_feather_esp32s3_reversetft.build.loop_core=
+adafruit_feather_esp32s3_reversetft.build.event_core=
+adafruit_feather_esp32s3_reversetft.build.flash_type=qio
+adafruit_feather_esp32s3_reversetft.build.psram_type=qspi
+adafruit_feather_esp32s3_reversetft.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_feather_esp32s3_reversetft.menu.LoopCore.1=Core 1
+adafruit_feather_esp32s3_reversetft.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_feather_esp32s3_reversetft.menu.LoopCore.0=Core 0
+adafruit_feather_esp32s3_reversetft.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_feather_esp32s3_reversetft.menu.EventsCore.1=Core 1
+adafruit_feather_esp32s3_reversetft.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_feather_esp32s3_reversetft.menu.EventsCore.0=Core 0
+adafruit_feather_esp32s3_reversetft.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_feather_esp32s3_reversetft.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_feather_esp32s3_reversetft.menu.USBMode.default.build.usb_mode=0
+adafruit_feather_esp32s3_reversetft.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_feather_esp32s3_reversetft.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_feather_esp32s3_reversetft.menu.CDCOnBoot.cdc=Enabled
+adafruit_feather_esp32s3_reversetft.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_feather_esp32s3_reversetft.menu.CDCOnBoot.default=Disabled
+adafruit_feather_esp32s3_reversetft.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_feather_esp32s3_reversetft.menu.MSCOnBoot.default=Disabled
+adafruit_feather_esp32s3_reversetft.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_feather_esp32s3_reversetft.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_feather_esp32s3_reversetft.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_feather_esp32s3_reversetft.menu.DFUOnBoot.default=Disabled
+adafruit_feather_esp32s3_reversetft.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_feather_esp32s3_reversetft.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_feather_esp32s3_reversetft.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_feather_esp32s3_reversetft.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_feather_esp32s3_reversetft.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_feather_esp32s3_reversetft.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_feather_esp32s3_reversetft.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_feather_esp32s3_reversetft.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_feather_esp32s3_reversetft.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_feather_esp32s3_reversetft.menu.PSRAM.enabled=QSPI PSRAM
+adafruit_feather_esp32s3_reversetft.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_feather_esp32s3_reversetft.menu.PSRAM.enabled.build.psram_type=qspi
+adafruit_feather_esp32s3_reversetft.menu.PSRAM.disabled=Disabled
+adafruit_feather_esp32s3_reversetft.menu.PSRAM.disabled.build.defines=
+adafruit_feather_esp32s3_reversetft.menu.PSRAM.disabled.build.psram_type=qspi
+adafruit_feather_esp32s3_reversetft.menu.PSRAM.opi=OPI PSRAM
+adafruit_feather_esp32s3_reversetft.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+adafruit_feather_esp32s3_reversetft.menu.PSRAM.opi.build.psram_type=opi
+
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.default.build.partitions=default
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_feather_esp32s3_reversetft.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.40=40MHz
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.20=20MHz
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.10=10MHz
+adafruit_feather_esp32s3_reversetft.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio=QIO 80MHz
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio.build.boot=qio
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120=QIO 120MHz
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120.build.boot=qio
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio=DIO 80MHz
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio.build.boot=dio
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi=OPI 80MHz
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi.build.boot=opi
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_feather_esp32s3_reversetft.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_feather_esp32s3_reversetft.menu.FlashSize.4M=4MB (32Mb)
+adafruit_feather_esp32s3_reversetft.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.921600=921600
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.115200=115200
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.256000.windows=256000
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.230400=230400
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.460800.linux=460800
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.460800.macosx=460800
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.512000.windows=512000
+adafruit_feather_esp32s3_reversetft.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.none=None
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.none.build.code_debug=0
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.error=Error
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.error.build.code_debug=1
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.warn=Warn
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.warn.build.code_debug=2
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.info=Info
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.info.build.code_debug=3
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.debug=Debug
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.debug.build.code_debug=4
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.verbose=Verbose
+adafruit_feather_esp32s3_reversetft.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_feather_esp32s3_reversetft.menu.EraseFlash.none=Disabled
+adafruit_feather_esp32s3_reversetft.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_feather_esp32s3_reversetft.menu.EraseFlash.all=Enabled
+adafruit_feather_esp32s3_reversetft.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.default=Disabled
+adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_feather_esp32s3_reversetft.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+#############################
+# Feather C6
+
+
+adafruit_feather_esp32c6.name=Adafruit Feather ESP32-C6
+
+adafruit_feather_esp32c6.bootloader.tool=esptool_py
+adafruit_feather_esp32c6.bootloader.tool.default=esptool_py
+
+adafruit_feather_esp32c6.upload.tool=esptool_py
+adafruit_feather_esp32c6.upload.tool.default=esptool_py
+adafruit_feather_esp32c6.upload.tool.network=esp_ota
+
+adafruit_feather_esp32c6.upload.maximum_size=1310720
+adafruit_feather_esp32c6.upload.maximum_data_size=327680
+adafruit_feather_esp32c6.upload.flags=
+adafruit_feather_esp32c6.upload.extra_flags=
+adafruit_feather_esp32c6.upload.use_1200bps_touch=false
+adafruit_feather_esp32c6.upload.wait_for_upload_port=false
+
+adafruit_feather_esp32c6.serial.disableDTR=false
+adafruit_feather_esp32c6.serial.disableRTS=false
+
+adafruit_feather_esp32c6.build.tarch=riscv32
+adafruit_feather_esp32c6.build.target=esp
+adafruit_feather_esp32c6.build.mcu=esp32c6
+adafruit_feather_esp32c6.build.core=esp32
+adafruit_feather_esp32c6.build.variant=adafruit_feather_esp32c6
+adafruit_feather_esp32c6.build.board=ADAFRUIT_FEATHER_ESP32C6
+adafruit_feather_esp32c6.build.bootloader_addr=0x0
+
+adafruit_feather_esp32c6.build.cdc_on_boot=0
+adafruit_feather_esp32c6.build.f_cpu=160000000L
+adafruit_feather_esp32c6.build.flash_size=4MB
+adafruit_feather_esp32c6.build.flash_freq=80m
+adafruit_feather_esp32c6.build.flash_mode=qio
+adafruit_feather_esp32c6.build.boot=qio
+adafruit_feather_esp32c6.build.partitions=default
+adafruit_feather_esp32c6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+adafruit_feather_esp32c6.menu.JTAGAdapter.default=Disabled
+adafruit_feather_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+adafruit_feather_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+adafruit_feather_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+adafruit_feather_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+adafruit_feather_esp32c6.menu.JTAGAdapter.external=FTDI Adapter
+adafruit_feather_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+adafruit_feather_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+adafruit_feather_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge
+adafruit_feather_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+adafruit_feather_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+adafruit_feather_esp32c6.menu.CDCOnBoot.default=Disabled
+adafruit_feather_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0
+adafruit_feather_esp32c6.menu.CDCOnBoot.cdc=Enabled
+adafruit_feather_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+adafruit_feather_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.default.build.partitions=default
+adafruit_feather_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_feather_esp32c6.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+adafruit_feather_esp32c6.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+adafruit_feather_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_feather_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_feather_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_feather_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_feather_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_feather_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_feather_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_feather_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_feather_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_feather_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_feather_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_feather_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_feather_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+adafruit_feather_esp32c6.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.fatflash.build.partitions=ffat
+adafruit_feather_esp32c6.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+adafruit_feather_esp32c6.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+adafruit_feather_esp32c6.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+adafruit_feather_esp32c6.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB
+adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+adafruit_feather_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+adafruit_feather_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+adafruit_feather_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+adafruit_feather_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+adafruit_feather_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+adafruit_feather_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+adafruit_feather_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+adafruit_feather_esp32c6.menu.PartitionScheme.custom=Custom
+adafruit_feather_esp32c6.menu.PartitionScheme.custom.build.partitions=
+adafruit_feather_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+adafruit_feather_esp32c6.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_feather_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_feather_esp32c6.menu.CPUFreq.120=120MHz (WiFi)
+adafruit_feather_esp32c6.menu.CPUFreq.120.build.f_cpu=120000000L
+adafruit_feather_esp32c6.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_feather_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_feather_esp32c6.menu.CPUFreq.40=40MHz
+adafruit_feather_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_feather_esp32c6.menu.CPUFreq.20=20MHz
+adafruit_feather_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_feather_esp32c6.menu.CPUFreq.10=10MHz
+adafruit_feather_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_feather_esp32c6.menu.FlashMode.qio=QIO
+adafruit_feather_esp32c6.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_feather_esp32c6.menu.FlashMode.qio.build.boot=qio
+adafruit_feather_esp32c6.menu.FlashMode.dio=DIO
+adafruit_feather_esp32c6.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_feather_esp32c6.menu.FlashMode.dio.build.boot=dio
+
+adafruit_feather_esp32c6.menu.FlashFreq.80=80MHz
+adafruit_feather_esp32c6.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_feather_esp32c6.menu.FlashFreq.40=40MHz
+adafruit_feather_esp32c6.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_feather_esp32c6.menu.UploadSpeed.921600=921600
+adafruit_feather_esp32c6.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_feather_esp32c6.menu.UploadSpeed.115200=115200
+adafruit_feather_esp32c6.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_feather_esp32c6.menu.UploadSpeed.256000.windows=256000
+adafruit_feather_esp32c6.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_feather_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_feather_esp32c6.menu.UploadSpeed.230400=230400
+adafruit_feather_esp32c6.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_feather_esp32c6.menu.UploadSpeed.460800.linux=460800
+adafruit_feather_esp32c6.menu.UploadSpeed.460800.macosx=460800
+adafruit_feather_esp32c6.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_feather_esp32c6.menu.UploadSpeed.512000.windows=512000
+adafruit_feather_esp32c6.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_feather_esp32c6.menu.DebugLevel.none=None
+adafruit_feather_esp32c6.menu.DebugLevel.none.build.code_debug=0
+adafruit_feather_esp32c6.menu.DebugLevel.error=Error
+adafruit_feather_esp32c6.menu.DebugLevel.error.build.code_debug=1
+adafruit_feather_esp32c6.menu.DebugLevel.warn=Warn
+adafruit_feather_esp32c6.menu.DebugLevel.warn.build.code_debug=2
+adafruit_feather_esp32c6.menu.DebugLevel.info=Info
+adafruit_feather_esp32c6.menu.DebugLevel.info.build.code_debug=3
+adafruit_feather_esp32c6.menu.DebugLevel.debug=Debug
+adafruit_feather_esp32c6.menu.DebugLevel.debug.build.code_debug=4
+adafruit_feather_esp32c6.menu.DebugLevel.verbose=Verbose
+adafruit_feather_esp32c6.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_feather_esp32c6.menu.EraseFlash.none=Disabled
+adafruit_feather_esp32c6.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_feather_esp32c6.menu.EraseFlash.all=Enabled
+adafruit_feather_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_feather_esp32c6.menu.ZigbeeMode.default=Disabled
+adafruit_feather_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_feather_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_feather_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+adafruit_feather_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+adafruit_feather_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+adafruit_feather_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_feather_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_feather_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+# Adafruit QT Py ESP32
+
+adafruit_qtpy_esp32_pico.name=Adafruit QT Py ESP32
+
+adafruit_qtpy_esp32_pico.bootloader.tool=esptool_py
+adafruit_qtpy_esp32_pico.bootloader.tool.default=esptool_py
+
+adafruit_qtpy_esp32_pico.upload.tool=esptool_py
+adafruit_qtpy_esp32_pico.upload.tool.default=esptool_py
+adafruit_qtpy_esp32_pico.upload.tool.network=esp_ota
+
+adafruit_qtpy_esp32_pico.upload.maximum_size=1310720
+adafruit_qtpy_esp32_pico.upload.maximum_data_size=327680
+adafruit_qtpy_esp32_pico.upload.flags=
+adafruit_qtpy_esp32_pico.upload.extra_flags=
+
+adafruit_qtpy_esp32_pico.serial.disableDTR=true
+adafruit_qtpy_esp32_pico.serial.disableRTS=true
+
+adafruit_qtpy_esp32_pico.build.tarch=xtensa
+adafruit_qtpy_esp32_pico.build.bootloader_addr=0x1000
+adafruit_qtpy_esp32_pico.build.target=esp32
+adafruit_qtpy_esp32_pico.build.mcu=esp32
+adafruit_qtpy_esp32_pico.build.core=esp32
+adafruit_qtpy_esp32_pico.build.variant=adafruit_qtpy_esp32
+adafruit_qtpy_esp32_pico.build.board=ADAFRUIT_QTPY_ESP32_PICO
+
+adafruit_qtpy_esp32_pico.build.f_cpu=240000000L
+adafruit_qtpy_esp32_pico.build.flash_size=8MB
+adafruit_qtpy_esp32_pico.build.flash_freq=80m
+adafruit_qtpy_esp32_pico.build.flash_mode=dio
+adafruit_qtpy_esp32_pico.build.boot=dio
+adafruit_qtpy_esp32_pico.build.partitions=default
+adafruit_qtpy_esp32_pico.build.defines=
+adafruit_qtpy_esp32_pico.build.loop_core=
+adafruit_qtpy_esp32_pico.build.event_core=
+
+adafruit_qtpy_esp32_pico.menu.LoopCore.1=Core 1
+adafruit_qtpy_esp32_pico.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_qtpy_esp32_pico.menu.LoopCore.0=Core 0
+adafruit_qtpy_esp32_pico.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_qtpy_esp32_pico.menu.EventsCore.1=Core 1
+adafruit_qtpy_esp32_pico.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_qtpy_esp32_pico.menu.EventsCore.0=Core 0
+adafruit_qtpy_esp32_pico.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_qtpy_esp32_pico.menu.PSRAM.enabled=Enabled
+adafruit_qtpy_esp32_pico.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+adafruit_qtpy_esp32_pico.menu.PSRAM.disabled=Disabled
+adafruit_qtpy_esp32_pico.menu.PSRAM.disabled.build.defines=
+
+adafruit_qtpy_esp32_pico.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+adafruit_qtpy_esp32_pico.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+adafruit_qtpy_esp32_pico.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+adafruit_qtpy_esp32_pico.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.2MB APP / 5.3MB SPIFFS)
+adafruit_qtpy_esp32_pico.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB
+adafruit_qtpy_esp32_pico.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720
+
+adafruit_qtpy_esp32_pico.menu.CPUFreq.240=240MHz (WiFi/BT)
+adafruit_qtpy_esp32_pico.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_qtpy_esp32_pico.menu.CPUFreq.160=160MHz (WiFi/BT)
+adafruit_qtpy_esp32_pico.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_qtpy_esp32_pico.menu.CPUFreq.80=80MHz (WiFi/BT)
+adafruit_qtpy_esp32_pico.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_qtpy_esp32_pico.menu.CPUFreq.40=40MHz
+adafruit_qtpy_esp32_pico.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_qtpy_esp32_pico.menu.CPUFreq.20=20MHz
+adafruit_qtpy_esp32_pico.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_qtpy_esp32_pico.menu.CPUFreq.10=10MHz
+adafruit_qtpy_esp32_pico.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_qtpy_esp32_pico.menu.FlashFreq.80=80MHz
+adafruit_qtpy_esp32_pico.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_qtpy_esp32_pico.menu.FlashFreq.40=40MHz
+adafruit_qtpy_esp32_pico.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_qtpy_esp32_pico.menu.FlashSize.8M=8MB (64Mb)
+adafruit_qtpy_esp32_pico.menu.FlashSize.8M.build.flash_size=8MB
+
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.921600=921600
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.115200=115200
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.256000.windows=256000
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.230400=230400
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.460800.linux=460800
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.460800.macosx=460800
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.512000.windows=512000
+adafruit_qtpy_esp32_pico.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_qtpy_esp32_pico.menu.DebugLevel.none=None
+adafruit_qtpy_esp32_pico.menu.DebugLevel.none.build.code_debug=0
+adafruit_qtpy_esp32_pico.menu.DebugLevel.error=Error
+adafruit_qtpy_esp32_pico.menu.DebugLevel.error.build.code_debug=1
+adafruit_qtpy_esp32_pico.menu.DebugLevel.warn=Warn
+adafruit_qtpy_esp32_pico.menu.DebugLevel.warn.build.code_debug=2
+adafruit_qtpy_esp32_pico.menu.DebugLevel.info=Info
+adafruit_qtpy_esp32_pico.menu.DebugLevel.info.build.code_debug=3
+adafruit_qtpy_esp32_pico.menu.DebugLevel.debug=Debug
+adafruit_qtpy_esp32_pico.menu.DebugLevel.debug.build.code_debug=4
+adafruit_qtpy_esp32_pico.menu.DebugLevel.verbose=Verbose
+adafruit_qtpy_esp32_pico.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_qtpy_esp32_pico.menu.EraseFlash.none=Disabled
+adafruit_qtpy_esp32_pico.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_qtpy_esp32_pico.menu.EraseFlash.all=Enabled
+adafruit_qtpy_esp32_pico.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_qtpy_esp32_pico.menu.ZigbeeMode.default=Disabled
+adafruit_qtpy_esp32_pico.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_qtpy_esp32_pico.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_qtpy_esp32_pico.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_qtpy_esp32_pico.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_qtpy_esp32_pico.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit QT Py ESP32-C3
+
+adafruit_qtpy_esp32c3.name=Adafruit QT Py ESP32-C3
+
+adafruit_qtpy_esp32c3.bootloader.tool=esptool_py
+adafruit_qtpy_esp32c3.bootloader.tool.default=esptool_py
+
+adafruit_qtpy_esp32c3.upload.tool=esptool_py
+adafruit_qtpy_esp32c3.upload.tool.default=esptool_py
+adafruit_qtpy_esp32c3.upload.tool.network=esp_ota
+
+adafruit_qtpy_esp32c3.upload.maximum_size=1310720
+adafruit_qtpy_esp32c3.upload.maximum_data_size=327680
+adafruit_qtpy_esp32c3.upload.flags=
+adafruit_qtpy_esp32c3.upload.extra_flags=
+adafruit_qtpy_esp32c3.upload.use_1200bps_touch=false
+adafruit_qtpy_esp32c3.upload.wait_for_upload_port=false
+
+adafruit_qtpy_esp32c3.serial.disableDTR=false
+adafruit_qtpy_esp32c3.serial.disableRTS=false
+
+adafruit_qtpy_esp32c3.build.tarch=riscv32
+adafruit_qtpy_esp32c3.build.bootloader_addr=0x0
+adafruit_qtpy_esp32c3.build.target=esp
+adafruit_qtpy_esp32c3.build.mcu=esp32c3
+adafruit_qtpy_esp32c3.build.core=esp32
+adafruit_qtpy_esp32c3.build.variant=adafruit_qtpy_esp32c3
+adafruit_qtpy_esp32c3.build.board=ADAFRUIT_QTPY_ESP32C3
+
+adafruit_qtpy_esp32c3.build.cdc_on_boot=1
+adafruit_qtpy_esp32c3.build.f_cpu=160000000L
+adafruit_qtpy_esp32c3.build.flash_size=4MB
+adafruit_qtpy_esp32c3.build.flash_freq=80m
+adafruit_qtpy_esp32c3.build.flash_mode=dio
+adafruit_qtpy_esp32c3.build.boot=qio
+adafruit_qtpy_esp32c3.build.partitions=default
+adafruit_qtpy_esp32c3.build.defines=
+
+adafruit_qtpy_esp32c3.menu.CDCOnBoot.cdc=Enabled
+adafruit_qtpy_esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_qtpy_esp32c3.menu.CDCOnBoot.default=Disabled
+adafruit_qtpy_esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_qtpy_esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_qtpy_esp32c3.menu.PartitionScheme.default.build.partitions=default
+adafruit_qtpy_esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_qtpy_esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_qtpy_esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_qtpy_esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_qtpy_esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_qtpy_esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_qtpy_esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_qtpy_esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_qtpy_esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_qtpy_esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_qtpy_esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_qtpy_esp32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_qtpy_esp32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_qtpy_esp32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_qtpy_esp32c3.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_qtpy_esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_qtpy_esp32c3.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_qtpy_esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_qtpy_esp32c3.menu.CPUFreq.40=40MHz
+adafruit_qtpy_esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_qtpy_esp32c3.menu.CPUFreq.20=20MHz
+adafruit_qtpy_esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_qtpy_esp32c3.menu.CPUFreq.10=10MHz
+adafruit_qtpy_esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_qtpy_esp32c3.menu.FlashMode.qio=QIO
+adafruit_qtpy_esp32c3.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_qtpy_esp32c3.menu.FlashMode.qio.build.boot=qio
+adafruit_qtpy_esp32c3.menu.FlashMode.dio=DIO
+adafruit_qtpy_esp32c3.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_qtpy_esp32c3.menu.FlashMode.dio.build.boot=dio
+
+adafruit_qtpy_esp32c3.menu.FlashFreq.80=80MHz
+adafruit_qtpy_esp32c3.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_qtpy_esp32c3.menu.FlashFreq.40=40MHz
+adafruit_qtpy_esp32c3.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_qtpy_esp32c3.menu.FlashSize.4M=4MB (32Mb)
+adafruit_qtpy_esp32c3.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_qtpy_esp32c3.menu.UploadSpeed.921600=921600
+adafruit_qtpy_esp32c3.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_qtpy_esp32c3.menu.UploadSpeed.115200=115200
+adafruit_qtpy_esp32c3.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_qtpy_esp32c3.menu.UploadSpeed.256000.windows=256000
+adafruit_qtpy_esp32c3.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_qtpy_esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_qtpy_esp32c3.menu.UploadSpeed.230400=230400
+adafruit_qtpy_esp32c3.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_qtpy_esp32c3.menu.UploadSpeed.460800.linux=460800
+adafruit_qtpy_esp32c3.menu.UploadSpeed.460800.macosx=460800
+adafruit_qtpy_esp32c3.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_qtpy_esp32c3.menu.UploadSpeed.512000.windows=512000
+adafruit_qtpy_esp32c3.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_qtpy_esp32c3.menu.DebugLevel.none=None
+adafruit_qtpy_esp32c3.menu.DebugLevel.none.build.code_debug=0
+adafruit_qtpy_esp32c3.menu.DebugLevel.error=Error
+adafruit_qtpy_esp32c3.menu.DebugLevel.error.build.code_debug=1
+adafruit_qtpy_esp32c3.menu.DebugLevel.warn=Warn
+adafruit_qtpy_esp32c3.menu.DebugLevel.warn.build.code_debug=2
+adafruit_qtpy_esp32c3.menu.DebugLevel.info=Info
+adafruit_qtpy_esp32c3.menu.DebugLevel.info.build.code_debug=3
+adafruit_qtpy_esp32c3.menu.DebugLevel.debug=Debug
+adafruit_qtpy_esp32c3.menu.DebugLevel.debug.build.code_debug=4
+adafruit_qtpy_esp32c3.menu.DebugLevel.verbose=Verbose
+adafruit_qtpy_esp32c3.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_qtpy_esp32c3.menu.EraseFlash.none=Disabled
+adafruit_qtpy_esp32c3.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_qtpy_esp32c3.menu.EraseFlash.all=Enabled
+adafruit_qtpy_esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_qtpy_esp32c3.menu.ZigbeeMode.default=Disabled
+adafruit_qtpy_esp32c3.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_qtpy_esp32c3.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_qtpy_esp32c3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_qtpy_esp32c3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_qtpy_esp32c3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit QT Py ESP32-S2
+
+adafruit_qtpy_esp32s2.name=Adafruit QT Py ESP32-S2
+adafruit_qtpy_esp32s2.vid.0=0x239A
+adafruit_qtpy_esp32s2.pid.0=0x8111
+adafruit_qtpy_esp32s2.vid.1=0x239A
+adafruit_qtpy_esp32s2.pid.1=0x0111
+adafruit_qtpy_esp32s2.vid.2=0x239A
+adafruit_qtpy_esp32s2.pid.2=0x8112
+adafruit_qtpy_esp32s2.upload_port.0.vid=0x239A
+adafruit_qtpy_esp32s2.upload_port.0.pid=0x8111
+adafruit_qtpy_esp32s2.upload_port.1.vid=0x239A
+adafruit_qtpy_esp32s2.upload_port.1.pid=0x0111
+adafruit_qtpy_esp32s2.upload_port.2.vid=0x239A
+adafruit_qtpy_esp32s2.upload_port.2.pid=0x8112
+
+adafruit_qtpy_esp32s2.bootloader.tool=esptool_py
+adafruit_qtpy_esp32s2.bootloader.tool.default=esptool_py
+
+adafruit_qtpy_esp32s2.upload.tool=esptool_py
+adafruit_qtpy_esp32s2.upload.tool.default=esptool_py
+adafruit_qtpy_esp32s2.upload.tool.network=esp_ota
+
+adafruit_qtpy_esp32s2.upload.maximum_size=1310720
+adafruit_qtpy_esp32s2.upload.maximum_data_size=327680
+adafruit_qtpy_esp32s2.upload.flags=
+adafruit_qtpy_esp32s2.upload.extra_flags=
+adafruit_qtpy_esp32s2.upload.use_1200bps_touch=true
+adafruit_qtpy_esp32s2.upload.wait_for_upload_port=true
+
+adafruit_qtpy_esp32s2.serial.disableDTR=false
+adafruit_qtpy_esp32s2.serial.disableRTS=false
+
+adafruit_qtpy_esp32s2.build.tarch=xtensa
+adafruit_qtpy_esp32s2.build.bootloader_addr=0x1000
+adafruit_qtpy_esp32s2.build.target=esp32s2
+adafruit_qtpy_esp32s2.build.mcu=esp32s2
+adafruit_qtpy_esp32s2.build.core=esp32
+adafruit_qtpy_esp32s2.build.variant=adafruit_qtpy_esp32s2
+adafruit_qtpy_esp32s2.build.board=ADAFRUIT_QTPY_ESP32S2
+
+adafruit_qtpy_esp32s2.build.cdc_on_boot=1
+adafruit_qtpy_esp32s2.build.msc_on_boot=0
+adafruit_qtpy_esp32s2.build.dfu_on_boot=0
+adafruit_qtpy_esp32s2.build.f_cpu=240000000L
+adafruit_qtpy_esp32s2.build.flash_size=4MB
+adafruit_qtpy_esp32s2.build.flash_freq=80m
+adafruit_qtpy_esp32s2.build.flash_mode=dio
+adafruit_qtpy_esp32s2.build.boot=qio
+adafruit_qtpy_esp32s2.build.partitions=default
+adafruit_qtpy_esp32s2.build.defines=
+
+adafruit_qtpy_esp32s2.menu.CDCOnBoot.cdc=Enabled
+adafruit_qtpy_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_qtpy_esp32s2.menu.CDCOnBoot.default=Disabled
+adafruit_qtpy_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_qtpy_esp32s2.menu.MSCOnBoot.default=Disabled
+adafruit_qtpy_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_qtpy_esp32s2.menu.MSCOnBoot.msc=Enabled
+adafruit_qtpy_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_qtpy_esp32s2.menu.DFUOnBoot.default=Disabled
+adafruit_qtpy_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_qtpy_esp32s2.menu.DFUOnBoot.dfu=Enabled
+adafruit_qtpy_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_qtpy_esp32s2.menu.UploadMode.cdc=Internal USB
+adafruit_qtpy_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_qtpy_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_qtpy_esp32s2.menu.UploadMode.default=UART0
+adafruit_qtpy_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_qtpy_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_qtpy_esp32s2.menu.PSRAM.enabled=Enabled
+adafruit_qtpy_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_qtpy_esp32s2.menu.PSRAM.disabled=Disabled
+adafruit_qtpy_esp32s2.menu.PSRAM.disabled.build.defines=
+
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_qtpy_esp32s2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_qtpy_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.default.build.partitions=default
+adafruit_qtpy_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_qtpy_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_qtpy_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_qtpy_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_qtpy_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_qtpy_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_qtpy_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_qtpy_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_qtpy_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_qtpy_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_qtpy_esp32s2.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_qtpy_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_qtpy_esp32s2.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_qtpy_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_qtpy_esp32s2.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_qtpy_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_qtpy_esp32s2.menu.CPUFreq.40=40MHz
+adafruit_qtpy_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_qtpy_esp32s2.menu.CPUFreq.20=20MHz
+adafruit_qtpy_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_qtpy_esp32s2.menu.CPUFreq.10=10MHz
+adafruit_qtpy_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_qtpy_esp32s2.menu.FlashMode.qio=QIO
+adafruit_qtpy_esp32s2.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_qtpy_esp32s2.menu.FlashMode.qio.build.boot=qio
+adafruit_qtpy_esp32s2.menu.FlashMode.dio=DIO
+adafruit_qtpy_esp32s2.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_qtpy_esp32s2.menu.FlashMode.dio.build.boot=dio
+
+adafruit_qtpy_esp32s2.menu.FlashFreq.80=80MHz
+adafruit_qtpy_esp32s2.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_qtpy_esp32s2.menu.FlashFreq.40=40MHz
+adafruit_qtpy_esp32s2.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_qtpy_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+adafruit_qtpy_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_qtpy_esp32s2.menu.UploadSpeed.921600=921600
+adafruit_qtpy_esp32s2.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_qtpy_esp32s2.menu.UploadSpeed.115200=115200
+adafruit_qtpy_esp32s2.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_qtpy_esp32s2.menu.UploadSpeed.256000.windows=256000
+adafruit_qtpy_esp32s2.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_qtpy_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_qtpy_esp32s2.menu.UploadSpeed.230400=230400
+adafruit_qtpy_esp32s2.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_qtpy_esp32s2.menu.UploadSpeed.460800.linux=460800
+adafruit_qtpy_esp32s2.menu.UploadSpeed.460800.macosx=460800
+adafruit_qtpy_esp32s2.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_qtpy_esp32s2.menu.UploadSpeed.512000.windows=512000
+adafruit_qtpy_esp32s2.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_qtpy_esp32s2.menu.DebugLevel.none=None
+adafruit_qtpy_esp32s2.menu.DebugLevel.none.build.code_debug=0
+adafruit_qtpy_esp32s2.menu.DebugLevel.error=Error
+adafruit_qtpy_esp32s2.menu.DebugLevel.error.build.code_debug=1
+adafruit_qtpy_esp32s2.menu.DebugLevel.warn=Warn
+adafruit_qtpy_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+adafruit_qtpy_esp32s2.menu.DebugLevel.info=Info
+adafruit_qtpy_esp32s2.menu.DebugLevel.info.build.code_debug=3
+adafruit_qtpy_esp32s2.menu.DebugLevel.debug=Debug
+adafruit_qtpy_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+adafruit_qtpy_esp32s2.menu.DebugLevel.verbose=Verbose
+adafruit_qtpy_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_qtpy_esp32s2.menu.EraseFlash.none=Disabled
+adafruit_qtpy_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_qtpy_esp32s2.menu.EraseFlash.all=Enabled
+adafruit_qtpy_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_qtpy_esp32s2.menu.ZigbeeMode.default=Disabled
+adafruit_qtpy_esp32s2.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_qtpy_esp32s2.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_qtpy_esp32s2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_qtpy_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_qtpy_esp32s2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit QT Py ESP32-S3 No PSRAM
+
+adafruit_qtpy_esp32s3_nopsram.name=Adafruit QT Py ESP32-S3 No PSRAM
+adafruit_qtpy_esp32s3_nopsram.vid.0=0x239A
+adafruit_qtpy_esp32s3_nopsram.pid.0=0x8119
+adafruit_qtpy_esp32s3_nopsram.vid.1=0x239A
+adafruit_qtpy_esp32s3_nopsram.pid.1=0x0119
+adafruit_qtpy_esp32s3_nopsram.vid.2=0x239A
+adafruit_qtpy_esp32s3_nopsram.pid.2=0x811A
+adafruit_qtpy_esp32s3_nopsram.upload_port.0.vid=0x239A
+adafruit_qtpy_esp32s3_nopsram.upload_port.0.pid=0x8119
+adafruit_qtpy_esp32s3_nopsram.upload_port.1.vid=0x239A
+adafruit_qtpy_esp32s3_nopsram.upload_port.1.pid=0x0119
+adafruit_qtpy_esp32s3_nopsram.upload_port.2.vid=0x239A
+adafruit_qtpy_esp32s3_nopsram.upload_port.2.pid=0x811A
+
+adafruit_qtpy_esp32s3_nopsram.bootloader.tool=esptool_py
+adafruit_qtpy_esp32s3_nopsram.bootloader.tool.default=esptool_py
+
+adafruit_qtpy_esp32s3_nopsram.upload.tool=esptool_py
+adafruit_qtpy_esp32s3_nopsram.upload.tool.default=esptool_py
+adafruit_qtpy_esp32s3_nopsram.upload.tool.network=esp_ota
+
+adafruit_qtpy_esp32s3_nopsram.upload.maximum_size=1310720
+adafruit_qtpy_esp32s3_nopsram.upload.maximum_data_size=327680
+adafruit_qtpy_esp32s3_nopsram.upload.flags=
+adafruit_qtpy_esp32s3_nopsram.upload.extra_flags=
+adafruit_qtpy_esp32s3_nopsram.upload.use_1200bps_touch=true
+adafruit_qtpy_esp32s3_nopsram.upload.wait_for_upload_port=true
+
+adafruit_qtpy_esp32s3_nopsram.serial.disableDTR=false
+adafruit_qtpy_esp32s3_nopsram.serial.disableRTS=false
+
+adafruit_qtpy_esp32s3_nopsram.build.tarch=xtensa
+adafruit_qtpy_esp32s3_nopsram.build.bootloader_addr=0x0
+adafruit_qtpy_esp32s3_nopsram.build.target=esp32s3
+adafruit_qtpy_esp32s3_nopsram.build.mcu=esp32s3
+adafruit_qtpy_esp32s3_nopsram.build.core=esp32
+adafruit_qtpy_esp32s3_nopsram.build.variant=adafruit_qtpy_esp32s3_nopsram
+adafruit_qtpy_esp32s3_nopsram.build.board=ADAFRUIT_QTPY_ESP32S3_NOPSRAM
+
+adafruit_qtpy_esp32s3_nopsram.build.usb_mode=0
+adafruit_qtpy_esp32s3_nopsram.build.cdc_on_boot=1
+adafruit_qtpy_esp32s3_nopsram.build.msc_on_boot=0
+adafruit_qtpy_esp32s3_nopsram.build.dfu_on_boot=0
+adafruit_qtpy_esp32s3_nopsram.build.f_cpu=240000000L
+adafruit_qtpy_esp32s3_nopsram.build.flash_size=8MB
+adafruit_qtpy_esp32s3_nopsram.build.flash_freq=80m
+adafruit_qtpy_esp32s3_nopsram.build.flash_mode=dio
+adafruit_qtpy_esp32s3_nopsram.build.boot=qio
+adafruit_qtpy_esp32s3_nopsram.build.partitions=default
+adafruit_qtpy_esp32s3_nopsram.build.defines=
+adafruit_qtpy_esp32s3_nopsram.build.loop_core=
+adafruit_qtpy_esp32s3_nopsram.build.event_core=
+adafruit_qtpy_esp32s3_nopsram.build.flash_type=qio
+adafruit_qtpy_esp32s3_nopsram.build.psram_type=qspi
+adafruit_qtpy_esp32s3_nopsram.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_qtpy_esp32s3_nopsram.menu.LoopCore.1=Core 1
+adafruit_qtpy_esp32s3_nopsram.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_qtpy_esp32s3_nopsram.menu.LoopCore.0=Core 0
+adafruit_qtpy_esp32s3_nopsram.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_qtpy_esp32s3_nopsram.menu.EventsCore.1=Core 1
+adafruit_qtpy_esp32s3_nopsram.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_qtpy_esp32s3_nopsram.menu.EventsCore.0=Core 0
+adafruit_qtpy_esp32s3_nopsram.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_qtpy_esp32s3_nopsram.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_qtpy_esp32s3_nopsram.menu.USBMode.default.build.usb_mode=0
+adafruit_qtpy_esp32s3_nopsram.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_qtpy_esp32s3_nopsram.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_qtpy_esp32s3_nopsram.menu.CDCOnBoot.cdc=Enabled
+adafruit_qtpy_esp32s3_nopsram.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_qtpy_esp32s3_nopsram.menu.CDCOnBoot.default=Disabled
+adafruit_qtpy_esp32s3_nopsram.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_qtpy_esp32s3_nopsram.menu.MSCOnBoot.default=Disabled
+adafruit_qtpy_esp32s3_nopsram.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_qtpy_esp32s3_nopsram.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_qtpy_esp32s3_nopsram.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_qtpy_esp32s3_nopsram.menu.DFUOnBoot.default=Disabled
+adafruit_qtpy_esp32s3_nopsram.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_qtpy_esp32s3_nopsram.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_qtpy_esp32s3_nopsram.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_qtpy_esp32s3_nopsram.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FATFS)
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-8MB
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota=TinyUF2 8MB No OTA (4MB APP/3.7MB FATFS)
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-8MB-noota
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+adafruit_qtpy_esp32s3_nopsram.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.40=40MHz
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.20=20MHz
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.10=10MHz
+adafruit_qtpy_esp32s3_nopsram.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio=QIO 80MHz
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio.build.boot=qio
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120=QIO 120MHz
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120.build.boot=qio
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio=DIO 80MHz
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio.build.boot=dio
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi=OPI 80MHz
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi.build.boot=opi
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_qtpy_esp32s3_nopsram.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_qtpy_esp32s3_nopsram.menu.FlashSize.8M=8MB (64Mb)
+adafruit_qtpy_esp32s3_nopsram.menu.FlashSize.8M.build.flash_size=8MB
+
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.921600=921600
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.115200=115200
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.256000.windows=256000
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.230400=230400
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.460800.linux=460800
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.460800.macosx=460800
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.512000.windows=512000
+adafruit_qtpy_esp32s3_nopsram.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.none=None
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.none.build.code_debug=0
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.error=Error
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.error.build.code_debug=1
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.warn=Warn
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.warn.build.code_debug=2
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.info=Info
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.info.build.code_debug=3
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.debug=Debug
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.debug.build.code_debug=4
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.verbose=Verbose
+adafruit_qtpy_esp32s3_nopsram.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_qtpy_esp32s3_nopsram.menu.EraseFlash.none=Disabled
+adafruit_qtpy_esp32s3_nopsram.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_qtpy_esp32s3_nopsram.menu.EraseFlash.all=Enabled
+adafruit_qtpy_esp32s3_nopsram.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.default=Disabled
+adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_qtpy_esp32s3_nopsram.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit QT Py ESP32-S3 (4M Flash 2M PSRAM)
+
+adafruit_qtpy_esp32s3_n4r2.name=Adafruit QT Py ESP32-S3 (4M Flash 2M PSRAM)
+adafruit_qtpy_esp32s3_n4r2.vid.0=0x239A
+adafruit_qtpy_esp32s3_n4r2.pid.0=0x8143
+adafruit_qtpy_esp32s3_n4r2.vid.1=0x239A
+adafruit_qtpy_esp32s3_n4r2.pid.1=0x0143
+adafruit_qtpy_esp32s3_n4r2.vid.2=0x239A
+adafruit_qtpy_esp32s3_n4r2.pid.2=0x8144
+adafruit_qtpy_esp32s3_n4r2.upload_port.0.vid=0x239A
+adafruit_qtpy_esp32s3_n4r2.upload_port.0.pid=0x8143
+adafruit_qtpy_esp32s3_n4r2.upload_port.1.vid=0x239A
+adafruit_qtpy_esp32s3_n4r2.upload_port.1.pid=0x0143
+adafruit_qtpy_esp32s3_n4r2.upload_port.2.vid=0x239A
+adafruit_qtpy_esp32s3_n4r2.upload_port.2.pid=0x8144
+
+adafruit_qtpy_esp32s3_n4r2.bootloader.tool=esptool_py
+adafruit_qtpy_esp32s3_n4r2.bootloader.tool.default=esptool_py
+
+adafruit_qtpy_esp32s3_n4r2.upload.tool=esptool_py
+adafruit_qtpy_esp32s3_n4r2.upload.tool.default=esptool_py
+adafruit_qtpy_esp32s3_n4r2.upload.tool.network=esp_ota
+
+adafruit_qtpy_esp32s3_n4r2.upload.maximum_size=1310720
+adafruit_qtpy_esp32s3_n4r2.upload.maximum_data_size=327680
+adafruit_qtpy_esp32s3_n4r2.upload.flags=
+adafruit_qtpy_esp32s3_n4r2.upload.extra_flags=
+adafruit_qtpy_esp32s3_n4r2.upload.use_1200bps_touch=true
+adafruit_qtpy_esp32s3_n4r2.upload.wait_for_upload_port=true
+
+adafruit_qtpy_esp32s3_n4r2.serial.disableDTR=false
+adafruit_qtpy_esp32s3_n4r2.serial.disableRTS=false
+
+adafruit_qtpy_esp32s3_n4r2.build.tarch=xtensa
+adafruit_qtpy_esp32s3_n4r2.build.bootloader_addr=0x0
+adafruit_qtpy_esp32s3_n4r2.build.target=esp32s3
+adafruit_qtpy_esp32s3_n4r2.build.mcu=esp32s3
+adafruit_qtpy_esp32s3_n4r2.build.core=esp32
+adafruit_qtpy_esp32s3_n4r2.build.variant=adafruit_qtpy_esp32s3_n4r2
+adafruit_qtpy_esp32s3_n4r2.build.board=ADAFRUIT_QTPY_ESP32S3_N4R2
+
+adafruit_qtpy_esp32s3_n4r2.build.usb_mode=0
+adafruit_qtpy_esp32s3_n4r2.build.cdc_on_boot=1
+adafruit_qtpy_esp32s3_n4r2.build.msc_on_boot=0
+adafruit_qtpy_esp32s3_n4r2.build.dfu_on_boot=0
+adafruit_qtpy_esp32s3_n4r2.build.f_cpu=240000000L
+adafruit_qtpy_esp32s3_n4r2.build.flash_size=4MB
+adafruit_qtpy_esp32s3_n4r2.build.flash_freq=80m
+adafruit_qtpy_esp32s3_n4r2.build.flash_mode=dio
+adafruit_qtpy_esp32s3_n4r2.build.boot=qio
+adafruit_qtpy_esp32s3_n4r2.build.partitions=default
+adafruit_qtpy_esp32s3_n4r2.build.defines=
+adafruit_qtpy_esp32s3_n4r2.build.loop_core=
+adafruit_qtpy_esp32s3_n4r2.build.event_core=
+adafruit_qtpy_esp32s3_n4r2.build.flash_type=qio
+adafruit_qtpy_esp32s3_n4r2.build.psram_type=qspi
+adafruit_qtpy_esp32s3_n4r2.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_qtpy_esp32s3_n4r2.menu.LoopCore.1=Core 1
+adafruit_qtpy_esp32s3_n4r2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_qtpy_esp32s3_n4r2.menu.LoopCore.0=Core 0
+adafruit_qtpy_esp32s3_n4r2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_qtpy_esp32s3_n4r2.menu.EventsCore.1=Core 1
+adafruit_qtpy_esp32s3_n4r2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_qtpy_esp32s3_n4r2.menu.EventsCore.0=Core 0
+adafruit_qtpy_esp32s3_n4r2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_qtpy_esp32s3_n4r2.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_qtpy_esp32s3_n4r2.menu.USBMode.default.build.usb_mode=0
+adafruit_qtpy_esp32s3_n4r2.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_qtpy_esp32s3_n4r2.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_qtpy_esp32s3_n4r2.menu.CDCOnBoot.cdc=Enabled
+adafruit_qtpy_esp32s3_n4r2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_qtpy_esp32s3_n4r2.menu.CDCOnBoot.default=Disabled
+adafruit_qtpy_esp32s3_n4r2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_qtpy_esp32s3_n4r2.menu.MSCOnBoot.default=Disabled
+adafruit_qtpy_esp32s3_n4r2.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_qtpy_esp32s3_n4r2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_qtpy_esp32s3_n4r2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_qtpy_esp32s3_n4r2.menu.DFUOnBoot.default=Disabled
+adafruit_qtpy_esp32s3_n4r2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_qtpy_esp32s3_n4r2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_qtpy_esp32s3_n4r2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_qtpy_esp32s3_n4r2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.enabled=QSPI PSRAM
+adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.enabled.build.psram_type=qspi
+adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.disabled=Disabled
+adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.disabled.build.defines=
+adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.disabled.build.psram_type=qspi
+adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.opi=OPI PSRAM
+adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+adafruit_qtpy_esp32s3_n4r2.menu.PSRAM.opi.build.psram_type=opi
+
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.default.build.partitions=default
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_qtpy_esp32s3_n4r2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.40=40MHz
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.20=20MHz
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.10=10MHz
+adafruit_qtpy_esp32s3_n4r2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio=QIO 80MHz
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio.build.boot=qio
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120=QIO 120MHz
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120.build.boot=qio
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio=DIO 80MHz
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio.build.boot=dio
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi=OPI 80MHz
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi.build.boot=opi
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_qtpy_esp32s3_n4r2.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_qtpy_esp32s3_n4r2.menu.FlashSize.4M=4MB (32Mb)
+adafruit_qtpy_esp32s3_n4r2.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.921600=921600
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.115200=115200
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.256000.windows=256000
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.230400=230400
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.460800.linux=460800
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.460800.macosx=460800
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.512000.windows=512000
+adafruit_qtpy_esp32s3_n4r2.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.none=None
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.none.build.code_debug=0
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.error=Error
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.error.build.code_debug=1
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.warn=Warn
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.warn.build.code_debug=2
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.info=Info
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.info.build.code_debug=3
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.debug=Debug
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.debug.build.code_debug=4
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.verbose=Verbose
+adafruit_qtpy_esp32s3_n4r2.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_qtpy_esp32s3_n4r2.menu.EraseFlash.none=Disabled
+adafruit_qtpy_esp32s3_n4r2.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_qtpy_esp32s3_n4r2.menu.EraseFlash.all=Enabled
+adafruit_qtpy_esp32s3_n4r2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.default=Disabled
+adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_qtpy_esp32s3_n4r2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit ItsyBitsy ESP32
+
+adafruit_itsybitsy_esp32.name=Adafruit ItsyBitsy ESP32
+
+adafruit_itsybitsy_esp32.bootloader.tool=esptool_py
+adafruit_itsybitsy_esp32.bootloader.tool.default=esptool_py
+
+adafruit_itsybitsy_esp32.upload.tool=esptool_py
+adafruit_itsybitsy_esp32.upload.tool.default=esptool_py
+adafruit_itsybitsy_esp32.upload.tool.network=esp_ota
+
+adafruit_itsybitsy_esp32.upload.maximum_size=1310720
+adafruit_itsybitsy_esp32.upload.maximum_data_size=327680
+adafruit_itsybitsy_esp32.upload.flags=
+adafruit_itsybitsy_esp32.upload.extra_flags=
+
+adafruit_itsybitsy_esp32.serial.disableDTR=true
+adafruit_itsybitsy_esp32.serial.disableRTS=true
+
+adafruit_itsybitsy_esp32.build.tarch=xtensa
+adafruit_itsybitsy_esp32.build.bootloader_addr=0x1000
+adafruit_itsybitsy_esp32.build.target=esp32
+adafruit_itsybitsy_esp32.build.mcu=esp32
+adafruit_itsybitsy_esp32.build.core=esp32
+adafruit_itsybitsy_esp32.build.variant=adafruit_itsybitsy_esp32
+adafruit_itsybitsy_esp32.build.board=ADAFRUIT_ITSYBITSY_ESP32
+
+adafruit_itsybitsy_esp32.build.f_cpu=240000000L
+adafruit_itsybitsy_esp32.build.flash_size=8MB
+adafruit_itsybitsy_esp32.build.flash_freq=80m
+adafruit_itsybitsy_esp32.build.flash_mode=dio
+adafruit_itsybitsy_esp32.build.boot=dio
+adafruit_itsybitsy_esp32.build.partitions=default
+adafruit_itsybitsy_esp32.build.defines=
+adafruit_itsybitsy_esp32.build.loop_core=
+adafruit_itsybitsy_esp32.build.event_core=
+
+adafruit_itsybitsy_esp32.menu.LoopCore.1=Core 1
+adafruit_itsybitsy_esp32.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_itsybitsy_esp32.menu.LoopCore.0=Core 0
+adafruit_itsybitsy_esp32.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_itsybitsy_esp32.menu.EventsCore.1=Core 1
+adafruit_itsybitsy_esp32.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_itsybitsy_esp32.menu.EventsCore.0=Core 0
+adafruit_itsybitsy_esp32.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_itsybitsy_esp32.menu.PSRAM.enabled=Enabled
+adafruit_itsybitsy_esp32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+adafruit_itsybitsy_esp32.menu.PSRAM.disabled=Disabled
+adafruit_itsybitsy_esp32.menu.PSRAM.disabled.build.defines=
+
+adafruit_itsybitsy_esp32.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+adafruit_itsybitsy_esp32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+adafruit_itsybitsy_esp32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+
+adafruit_itsybitsy_esp32.menu.CPUFreq.240=240MHz (WiFi/BT)
+adafruit_itsybitsy_esp32.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_itsybitsy_esp32.menu.CPUFreq.160=160MHz (WiFi/BT)
+adafruit_itsybitsy_esp32.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_itsybitsy_esp32.menu.CPUFreq.80=80MHz (WiFi/BT)
+adafruit_itsybitsy_esp32.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_itsybitsy_esp32.menu.CPUFreq.40=40MHz
+adafruit_itsybitsy_esp32.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_itsybitsy_esp32.menu.CPUFreq.20=20MHz
+adafruit_itsybitsy_esp32.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_itsybitsy_esp32.menu.CPUFreq.10=10MHz
+adafruit_itsybitsy_esp32.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_itsybitsy_esp32.menu.FlashFreq.80=80MHz
+adafruit_itsybitsy_esp32.menu.FlashFreq.80.build.flash_freq=80m
+adafruit_itsybitsy_esp32.menu.FlashFreq.40=40MHz
+adafruit_itsybitsy_esp32.menu.FlashFreq.40.build.flash_freq=40m
+
+adafruit_itsybitsy_esp32.menu.FlashSize.8M=8MB (64Mb)
+adafruit_itsybitsy_esp32.menu.FlashSize.8M.build.flash_size=8MB
+
+adafruit_itsybitsy_esp32.menu.UploadSpeed.921600=921600
+adafruit_itsybitsy_esp32.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_itsybitsy_esp32.menu.UploadSpeed.115200=115200
+adafruit_itsybitsy_esp32.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_itsybitsy_esp32.menu.UploadSpeed.256000.windows=256000
+adafruit_itsybitsy_esp32.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_itsybitsy_esp32.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_itsybitsy_esp32.menu.UploadSpeed.230400=230400
+adafruit_itsybitsy_esp32.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_itsybitsy_esp32.menu.UploadSpeed.460800.linux=460800
+adafruit_itsybitsy_esp32.menu.UploadSpeed.460800.macosx=460800
+adafruit_itsybitsy_esp32.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_itsybitsy_esp32.menu.UploadSpeed.512000.windows=512000
+adafruit_itsybitsy_esp32.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_itsybitsy_esp32.menu.DebugLevel.none=None
+adafruit_itsybitsy_esp32.menu.DebugLevel.none.build.code_debug=0
+adafruit_itsybitsy_esp32.menu.DebugLevel.error=Error
+adafruit_itsybitsy_esp32.menu.DebugLevel.error.build.code_debug=1
+adafruit_itsybitsy_esp32.menu.DebugLevel.warn=Warn
+adafruit_itsybitsy_esp32.menu.DebugLevel.warn.build.code_debug=2
+adafruit_itsybitsy_esp32.menu.DebugLevel.info=Info
+adafruit_itsybitsy_esp32.menu.DebugLevel.info.build.code_debug=3
+adafruit_itsybitsy_esp32.menu.DebugLevel.debug=Debug
+adafruit_itsybitsy_esp32.menu.DebugLevel.debug.build.code_debug=4
+adafruit_itsybitsy_esp32.menu.DebugLevel.verbose=Verbose
+adafruit_itsybitsy_esp32.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_itsybitsy_esp32.menu.EraseFlash.none=Disabled
+adafruit_itsybitsy_esp32.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_itsybitsy_esp32.menu.EraseFlash.all=Enabled
+adafruit_itsybitsy_esp32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_itsybitsy_esp32.menu.ZigbeeMode.default=Disabled
+adafruit_itsybitsy_esp32.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_itsybitsy_esp32.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_itsybitsy_esp32.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_itsybitsy_esp32.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_itsybitsy_esp32.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit MatrixPortal ESP32-S3
+
+adafruit_matrixportal_esp32s3.name=Adafruit MatrixPortal ESP32-S3
+adafruit_matrixportal_esp32s3.vid.0=0x239A
+adafruit_matrixportal_esp32s3.pid.0=0x8125
+adafruit_matrixportal_esp32s3.vid.1=0x239A
+adafruit_matrixportal_esp32s3.pid.1=0x0125
+adafruit_matrixportal_esp32s3.vid.2=0x239A
+adafruit_matrixportal_esp32s3.pid.2=0x8126
+adafruit_matrixportal_esp32s3.upload_port.0.vid=0x239A
+adafruit_matrixportal_esp32s3.upload_port.0.pid=0x8125
+adafruit_matrixportal_esp32s3.upload_port.1.vid=0x239A
+adafruit_matrixportal_esp32s3.upload_port.1.pid=0x0125
+adafruit_matrixportal_esp32s3.upload_port.2.vid=0x239A
+adafruit_matrixportal_esp32s3.upload_port.2.pid=0x8126
+
+adafruit_matrixportal_esp32s3.bootloader.tool=esptool_py
+adafruit_matrixportal_esp32s3.bootloader.tool.default=esptool_py
+
+adafruit_matrixportal_esp32s3.upload.tool=esptool_py
+adafruit_matrixportal_esp32s3.upload.tool.default=esptool_py
+adafruit_matrixportal_esp32s3.upload.tool.network=esp_ota
+
+adafruit_matrixportal_esp32s3.upload.maximum_size=1310720
+adafruit_matrixportal_esp32s3.upload.maximum_data_size=327680
+adafruit_matrixportal_esp32s3.upload.flags=
+adafruit_matrixportal_esp32s3.upload.extra_flags=
+adafruit_matrixportal_esp32s3.upload.use_1200bps_touch=true
+adafruit_matrixportal_esp32s3.upload.wait_for_upload_port=true
+
+adafruit_matrixportal_esp32s3.serial.disableDTR=false
+adafruit_matrixportal_esp32s3.serial.disableRTS=false
+
+adafruit_matrixportal_esp32s3.build.tarch=xtensa
+adafruit_matrixportal_esp32s3.build.bootloader_addr=0x0
+adafruit_matrixportal_esp32s3.build.target=esp32s3
+adafruit_matrixportal_esp32s3.build.mcu=esp32s3
+adafruit_matrixportal_esp32s3.build.core=esp32
+adafruit_matrixportal_esp32s3.build.variant=adafruit_matrixportal_esp32s3
+adafruit_matrixportal_esp32s3.build.board=ADAFRUIT_MATRIXPORTAL_ESP32S3
+
+adafruit_matrixportal_esp32s3.build.usb_mode=0
+adafruit_matrixportal_esp32s3.build.cdc_on_boot=1
+adafruit_matrixportal_esp32s3.build.msc_on_boot=0
+adafruit_matrixportal_esp32s3.build.dfu_on_boot=0
+adafruit_matrixportal_esp32s3.build.f_cpu=240000000L
+adafruit_matrixportal_esp32s3.build.flash_size=8MB
+adafruit_matrixportal_esp32s3.build.flash_freq=80m
+adafruit_matrixportal_esp32s3.build.flash_mode=dio
+adafruit_matrixportal_esp32s3.build.boot=qio
+adafruit_matrixportal_esp32s3.build.partitions=default
+adafruit_matrixportal_esp32s3.build.defines=
+adafruit_matrixportal_esp32s3.build.loop_core=
+adafruit_matrixportal_esp32s3.build.event_core=
+adafruit_matrixportal_esp32s3.build.flash_type=qio
+adafruit_matrixportal_esp32s3.build.psram_type=qspi
+adafruit_matrixportal_esp32s3.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_matrixportal_esp32s3.menu.LoopCore.1=Core 1
+adafruit_matrixportal_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_matrixportal_esp32s3.menu.LoopCore.0=Core 0
+adafruit_matrixportal_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_matrixportal_esp32s3.menu.EventsCore.1=Core 1
+adafruit_matrixportal_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_matrixportal_esp32s3.menu.EventsCore.0=Core 0
+adafruit_matrixportal_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_matrixportal_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_matrixportal_esp32s3.menu.USBMode.default.build.usb_mode=0
+adafruit_matrixportal_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_matrixportal_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_matrixportal_esp32s3.menu.CDCOnBoot.cdc=Enabled
+adafruit_matrixportal_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_matrixportal_esp32s3.menu.CDCOnBoot.default=Disabled
+adafruit_matrixportal_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_matrixportal_esp32s3.menu.MSCOnBoot.default=Disabled
+adafruit_matrixportal_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_matrixportal_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_matrixportal_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_matrixportal_esp32s3.menu.DFUOnBoot.default=Disabled
+adafruit_matrixportal_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_matrixportal_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_matrixportal_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_matrixportal_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_matrixportal_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_matrixportal_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_matrixportal_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_matrixportal_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_matrixportal_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_matrixportal_esp32s3.menu.PSRAM.enabled=QSPI PSRAM
+adafruit_matrixportal_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_matrixportal_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi
+adafruit_matrixportal_esp32s3.menu.PSRAM.disabled=Disabled
+adafruit_matrixportal_esp32s3.menu.PSRAM.disabled.build.defines=
+adafruit_matrixportal_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi
+adafruit_matrixportal_esp32s3.menu.PSRAM.opi=OPI PSRAM
+adafruit_matrixportal_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+adafruit_matrixportal_esp32s3.menu.PSRAM.opi.build.psram_type=opi
+
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FATFS)
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-8MB
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota=TinyUF2 8MB No OTA (4MB APP/3.7MB FATFS)
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-8MB-noota
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+adafruit_matrixportal_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+
+adafruit_matrixportal_esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_matrixportal_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_matrixportal_esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_matrixportal_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_matrixportal_esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_matrixportal_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_matrixportal_esp32s3.menu.CPUFreq.40=40MHz
+adafruit_matrixportal_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_matrixportal_esp32s3.menu.CPUFreq.20=20MHz
+adafruit_matrixportal_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_matrixportal_esp32s3.menu.CPUFreq.10=10MHz
+adafruit_matrixportal_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio=QIO 80MHz
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio.build.boot=qio
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio120=QIO 120MHz
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio120.build.boot=qio
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_matrixportal_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_matrixportal_esp32s3.menu.FlashMode.dio=DIO 80MHz
+adafruit_matrixportal_esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_matrixportal_esp32s3.menu.FlashMode.dio.build.boot=dio
+adafruit_matrixportal_esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_matrixportal_esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_matrixportal_esp32s3.menu.FlashMode.opi=OPI 80MHz
+adafruit_matrixportal_esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_matrixportal_esp32s3.menu.FlashMode.opi.build.boot=opi
+adafruit_matrixportal_esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_matrixportal_esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_matrixportal_esp32s3.menu.FlashSize.8M=8MB (64Mb)
+adafruit_matrixportal_esp32s3.menu.FlashSize.8M.build.flash_size=8MB
+
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.921600=921600
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.115200=115200
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.256000.windows=256000
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.230400=230400
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.460800.linux=460800
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.460800.macosx=460800
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.512000.windows=512000
+adafruit_matrixportal_esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_matrixportal_esp32s3.menu.DebugLevel.none=None
+adafruit_matrixportal_esp32s3.menu.DebugLevel.none.build.code_debug=0
+adafruit_matrixportal_esp32s3.menu.DebugLevel.error=Error
+adafruit_matrixportal_esp32s3.menu.DebugLevel.error.build.code_debug=1
+adafruit_matrixportal_esp32s3.menu.DebugLevel.warn=Warn
+adafruit_matrixportal_esp32s3.menu.DebugLevel.warn.build.code_debug=2
+adafruit_matrixportal_esp32s3.menu.DebugLevel.info=Info
+adafruit_matrixportal_esp32s3.menu.DebugLevel.info.build.code_debug=3
+adafruit_matrixportal_esp32s3.menu.DebugLevel.debug=Debug
+adafruit_matrixportal_esp32s3.menu.DebugLevel.debug.build.code_debug=4
+adafruit_matrixportal_esp32s3.menu.DebugLevel.verbose=Verbose
+adafruit_matrixportal_esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_matrixportal_esp32s3.menu.EraseFlash.none=Disabled
+adafruit_matrixportal_esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_matrixportal_esp32s3.menu.EraseFlash.all=Enabled
+adafruit_matrixportal_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_matrixportal_esp32s3.menu.ZigbeeMode.default=Disabled
+adafruit_matrixportal_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_matrixportal_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_matrixportal_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_matrixportal_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_matrixportal_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit pyCamera S3
+
+adafruit_camera_esp32s3.name=Adafruit pyCamera S3
+adafruit_camera_esp32s3.vid.0=0x239A
+adafruit_camera_esp32s3.pid.0=0x0117
+adafruit_camera_esp32s3.vid.1=0x239A
+adafruit_camera_esp32s3.pid.1=0x8117
+adafruit_camera_esp32s3.vid.2=0x239A
+adafruit_camera_esp32s3.pid.2=0x8118
+adafruit_camera_esp32s3.upload_port.0.vid=0x239A
+adafruit_camera_esp32s3.upload_port.0.pid=0x0117
+adafruit_camera_esp32s3.upload_port.1.vid=0x239A
+adafruit_camera_esp32s3.upload_port.1.pid=0x8117
+adafruit_camera_esp32s3.upload_port.2.vid=0x239A
+adafruit_camera_esp32s3.upload_port.2.pid=0x8118
+
+adafruit_camera_esp32s3.bootloader.tool=esptool_py
+adafruit_camera_esp32s3.bootloader.tool.default=esptool_py
+
+adafruit_camera_esp32s3.upload.tool=esptool_py
+adafruit_camera_esp32s3.upload.tool.default=esptool_py
+adafruit_camera_esp32s3.upload.tool.network=esp_ota
+
+adafruit_camera_esp32s3.upload.maximum_size=1310720
+adafruit_camera_esp32s3.upload.maximum_data_size=327680
+adafruit_camera_esp32s3.upload.flags=
+adafruit_camera_esp32s3.upload.extra_flags=
+adafruit_camera_esp32s3.upload.use_1200bps_touch=true
+adafruit_camera_esp32s3.upload.wait_for_upload_port=true
+
+adafruit_camera_esp32s3.serial.disableDTR=false
+adafruit_camera_esp32s3.serial.disableRTS=false
+
+adafruit_camera_esp32s3.build.tarch=xtensa
+adafruit_camera_esp32s3.build.bootloader_addr=0x0
+adafruit_camera_esp32s3.build.target=esp32s3
+adafruit_camera_esp32s3.build.mcu=esp32s3
+adafruit_camera_esp32s3.build.core=esp32
+adafruit_camera_esp32s3.build.variant=adafruit_camera_esp32s3
+adafruit_camera_esp32s3.build.board=ADAFRUIT_CAMERA_ESP32S3
+
+adafruit_camera_esp32s3.build.usb_mode=0
+adafruit_camera_esp32s3.build.cdc_on_boot=1
+adafruit_camera_esp32s3.build.msc_on_boot=0
+adafruit_camera_esp32s3.build.dfu_on_boot=0
+adafruit_camera_esp32s3.build.f_cpu=240000000L
+adafruit_camera_esp32s3.build.flash_size=4MB
+adafruit_camera_esp32s3.build.flash_freq=80m
+adafruit_camera_esp32s3.build.flash_mode=dio
+adafruit_camera_esp32s3.build.boot=qio
+adafruit_camera_esp32s3.build.partitions=default
+adafruit_camera_esp32s3.build.defines=
+adafruit_camera_esp32s3.build.loop_core=
+adafruit_camera_esp32s3.build.event_core=
+adafruit_camera_esp32s3.build.flash_type=qio
+adafruit_camera_esp32s3.build.psram_type=qspi
+adafruit_camera_esp32s3.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_camera_esp32s3.menu.LoopCore.1=Core 1
+adafruit_camera_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_camera_esp32s3.menu.LoopCore.0=Core 0
+adafruit_camera_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_camera_esp32s3.menu.EventsCore.1=Core 1
+adafruit_camera_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_camera_esp32s3.menu.EventsCore.0=Core 0
+adafruit_camera_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_camera_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_camera_esp32s3.menu.USBMode.default.build.usb_mode=0
+adafruit_camera_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_camera_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_camera_esp32s3.menu.CDCOnBoot.cdc=Enabled
+adafruit_camera_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_camera_esp32s3.menu.CDCOnBoot.default=Disabled
+adafruit_camera_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_camera_esp32s3.menu.MSCOnBoot.default=Disabled
+adafruit_camera_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_camera_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_camera_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_camera_esp32s3.menu.DFUOnBoot.default=Disabled
+adafruit_camera_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_camera_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_camera_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_camera_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_camera_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_camera_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_camera_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_camera_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_camera_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_camera_esp32s3.menu.PSRAM.enabled=QSPI PSRAM
+adafruit_camera_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+adafruit_camera_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi
+adafruit_camera_esp32s3.menu.PSRAM.disabled=Disabled
+adafruit_camera_esp32s3.menu.PSRAM.disabled.build.defines=
+adafruit_camera_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi
+adafruit_camera_esp32s3.menu.PSRAM.opi=OPI PSRAM
+adafruit_camera_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+adafruit_camera_esp32s3.menu.PSRAM.opi.build.psram_type=opi
+
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota=TinyUF2 4MB No OTA (2.7MB APP/960KB FATFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-4MB-noota
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=2883584
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-4MB
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+adafruit_camera_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_camera_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.default.build.partitions=default
+adafruit_camera_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+adafruit_camera_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal
+adafruit_camera_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+adafruit_camera_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+adafruit_camera_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+adafruit_camera_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+adafruit_camera_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+adafruit_camera_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+adafruit_camera_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+adafruit_camera_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+adafruit_camera_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+adafruit_camera_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+adafruit_camera_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+adafruit_camera_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+adafruit_camera_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+adafruit_camera_esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_camera_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_camera_esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_camera_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_camera_esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_camera_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_camera_esp32s3.menu.CPUFreq.40=40MHz
+adafruit_camera_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_camera_esp32s3.menu.CPUFreq.20=20MHz
+adafruit_camera_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_camera_esp32s3.menu.CPUFreq.10=10MHz
+adafruit_camera_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_camera_esp32s3.menu.FlashMode.qio=QIO 80MHz
+adafruit_camera_esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_camera_esp32s3.menu.FlashMode.qio.build.boot=qio
+adafruit_camera_esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_camera_esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_camera_esp32s3.menu.FlashMode.qio120=QIO 120MHz
+adafruit_camera_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_camera_esp32s3.menu.FlashMode.qio120.build.boot=qio
+adafruit_camera_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_camera_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_camera_esp32s3.menu.FlashMode.dio=DIO 80MHz
+adafruit_camera_esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_camera_esp32s3.menu.FlashMode.dio.build.boot=dio
+adafruit_camera_esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_camera_esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_camera_esp32s3.menu.FlashMode.opi=OPI 80MHz
+adafruit_camera_esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_camera_esp32s3.menu.FlashMode.opi.build.boot=opi
+adafruit_camera_esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_camera_esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_camera_esp32s3.menu.FlashSize.4M=4MB (32Mb)
+adafruit_camera_esp32s3.menu.FlashSize.4M.build.flash_size=4MB
+
+adafruit_camera_esp32s3.menu.UploadSpeed.921600=921600
+adafruit_camera_esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_camera_esp32s3.menu.UploadSpeed.115200=115200
+adafruit_camera_esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_camera_esp32s3.menu.UploadSpeed.256000.windows=256000
+adafruit_camera_esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_camera_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_camera_esp32s3.menu.UploadSpeed.230400=230400
+adafruit_camera_esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_camera_esp32s3.menu.UploadSpeed.460800.linux=460800
+adafruit_camera_esp32s3.menu.UploadSpeed.460800.macosx=460800
+adafruit_camera_esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_camera_esp32s3.menu.UploadSpeed.512000.windows=512000
+adafruit_camera_esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_camera_esp32s3.menu.DebugLevel.none=None
+adafruit_camera_esp32s3.menu.DebugLevel.none.build.code_debug=0
+adafruit_camera_esp32s3.menu.DebugLevel.error=Error
+adafruit_camera_esp32s3.menu.DebugLevel.error.build.code_debug=1
+adafruit_camera_esp32s3.menu.DebugLevel.warn=Warn
+adafruit_camera_esp32s3.menu.DebugLevel.warn.build.code_debug=2
+adafruit_camera_esp32s3.menu.DebugLevel.info=Info
+adafruit_camera_esp32s3.menu.DebugLevel.info.build.code_debug=3
+adafruit_camera_esp32s3.menu.DebugLevel.debug=Debug
+adafruit_camera_esp32s3.menu.DebugLevel.debug.build.code_debug=4
+adafruit_camera_esp32s3.menu.DebugLevel.verbose=Verbose
+adafruit_camera_esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_camera_esp32s3.menu.EraseFlash.none=Disabled
+adafruit_camera_esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_camera_esp32s3.menu.EraseFlash.all=Enabled
+adafruit_camera_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_camera_esp32s3.menu.ZigbeeMode.default=Disabled
+adafruit_camera_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_camera_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_camera_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_camera_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_camera_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Qualia ESP32-S3 RGB666
+
+adafruit_qualia_s3_rgb666.name=Adafruit Qualia ESP32-S3 RGB666
+adafruit_qualia_s3_rgb666.vid.0=0x239A
+adafruit_qualia_s3_rgb666.pid.0=0x8147
+adafruit_qualia_s3_rgb666.vid.1=0x239A
+adafruit_qualia_s3_rgb666.pid.1=0x0147
+adafruit_qualia_s3_rgb666.vid.2=0x239A
+adafruit_qualia_s3_rgb666.pid.2=0x8148
+adafruit_qualia_s3_rgb666.upload_port.0.vid=0x239A
+adafruit_qualia_s3_rgb666.upload_port.0.pid=0x8147
+adafruit_qualia_s3_rgb666.upload_port.1.vid=0x239A
+adafruit_qualia_s3_rgb666.upload_port.1.pid=0x0147
+adafruit_qualia_s3_rgb666.upload_port.2.vid=0x239A
+adafruit_qualia_s3_rgb666.upload_port.2.pid=0x8148
+
+adafruit_qualia_s3_rgb666.bootloader.tool=esptool_py
+adafruit_qualia_s3_rgb666.bootloader.tool.default=esptool_py
+
+adafruit_qualia_s3_rgb666.upload.tool=esptool_py
+adafruit_qualia_s3_rgb666.upload.tool.default=esptool_py
+adafruit_qualia_s3_rgb666.upload.tool.network=esp_ota
+
+adafruit_qualia_s3_rgb666.upload.maximum_size=1310720
+adafruit_qualia_s3_rgb666.upload.maximum_data_size=327680
+adafruit_qualia_s3_rgb666.upload.flags=
+adafruit_qualia_s3_rgb666.upload.extra_flags=
+adafruit_qualia_s3_rgb666.upload.use_1200bps_touch=true
+adafruit_qualia_s3_rgb666.upload.wait_for_upload_port=true
+
+adafruit_qualia_s3_rgb666.serial.disableDTR=false
+adafruit_qualia_s3_rgb666.serial.disableRTS=false
+
+adafruit_qualia_s3_rgb666.build.tarch=xtensa
+adafruit_qualia_s3_rgb666.build.bootloader_addr=0x0
+adafruit_qualia_s3_rgb666.build.target=esp32s3
+adafruit_qualia_s3_rgb666.build.mcu=esp32s3
+adafruit_qualia_s3_rgb666.build.core=esp32
+adafruit_qualia_s3_rgb666.build.variant=adafruit_qualia_s3_rgb666
+adafruit_qualia_s3_rgb666.build.board=QUALIA_S3_RGB666
+
+adafruit_qualia_s3_rgb666.build.usb_mode=0
+adafruit_qualia_s3_rgb666.build.cdc_on_boot=1
+adafruit_qualia_s3_rgb666.build.msc_on_boot=0
+adafruit_qualia_s3_rgb666.build.dfu_on_boot=0
+adafruit_qualia_s3_rgb666.build.f_cpu=240000000L
+adafruit_qualia_s3_rgb666.build.flash_size=16MB
+adafruit_qualia_s3_rgb666.build.flash_freq=80m
+adafruit_qualia_s3_rgb666.build.flash_mode=dio
+adafruit_qualia_s3_rgb666.build.boot=qio
+adafruit_qualia_s3_rgb666.build.partitions=default
+adafruit_qualia_s3_rgb666.build.defines=
+adafruit_qualia_s3_rgb666.build.loop_core=
+adafruit_qualia_s3_rgb666.build.event_core=
+adafruit_qualia_s3_rgb666.build.flash_type=qio
+adafruit_qualia_s3_rgb666.build.psram_type=opi
+adafruit_qualia_s3_rgb666.build.memory_type={build.flash_type}_{build.psram_type}
+
+adafruit_qualia_s3_rgb666.menu.LoopCore.1=Core 1
+adafruit_qualia_s3_rgb666.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+adafruit_qualia_s3_rgb666.menu.LoopCore.0=Core 0
+adafruit_qualia_s3_rgb666.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+adafruit_qualia_s3_rgb666.menu.EventsCore.1=Core 1
+adafruit_qualia_s3_rgb666.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+adafruit_qualia_s3_rgb666.menu.EventsCore.0=Core 0
+adafruit_qualia_s3_rgb666.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+adafruit_qualia_s3_rgb666.menu.USBMode.default=USB-OTG (TinyUSB)
+adafruit_qualia_s3_rgb666.menu.USBMode.default.build.usb_mode=0
+adafruit_qualia_s3_rgb666.menu.USBMode.hwcdc=Hardware CDC and JTAG
+adafruit_qualia_s3_rgb666.menu.USBMode.hwcdc.build.usb_mode=1
+
+adafruit_qualia_s3_rgb666.menu.CDCOnBoot.cdc=Enabled
+adafruit_qualia_s3_rgb666.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+adafruit_qualia_s3_rgb666.menu.CDCOnBoot.default=Disabled
+adafruit_qualia_s3_rgb666.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+adafruit_qualia_s3_rgb666.menu.MSCOnBoot.default=Disabled
+adafruit_qualia_s3_rgb666.menu.MSCOnBoot.default.build.msc_on_boot=0
+adafruit_qualia_s3_rgb666.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+adafruit_qualia_s3_rgb666.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+adafruit_qualia_s3_rgb666.menu.DFUOnBoot.default=Disabled
+adafruit_qualia_s3_rgb666.menu.DFUOnBoot.default.build.dfu_on_boot=0
+adafruit_qualia_s3_rgb666.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+adafruit_qualia_s3_rgb666.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+adafruit_qualia_s3_rgb666.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+adafruit_qualia_s3_rgb666.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+adafruit_qualia_s3_rgb666.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+adafruit_qualia_s3_rgb666.menu.UploadMode.default=UART0 / Hardware CDC
+adafruit_qualia_s3_rgb666.menu.UploadMode.default.upload.use_1200bps_touch=false
+adafruit_qualia_s3_rgb666.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+adafruit_qualia_s3_rgb666.menu.PSRAM.opi=OPI PSRAM
+adafruit_qualia_s3_rgb666.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+adafruit_qualia_s3_rgb666.menu.PSRAM.opi.build.psram_type=opi
+adafruit_qualia_s3_rgb666.menu.PSRAM.disabled=Disabled
+adafruit_qualia_s3_rgb666.menu.PSRAM.disabled.build.defines=
+adafruit_qualia_s3_rgb666.menu.PSRAM.disabled.build.psram_type=opi
+
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2=TinyUF2 16MB (2MB APP/11.6MB FATFS)
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2.build.partitions=tinyuf2-partitions-16MB
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota=TinyUF2 16MB No OTA(4MB APP/11.6MB FATFS)
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota.build.custom_bootloader=bootloader-tinyuf2
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota.build.partitions=tinyuf2-partitions-16MB-noota
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota.upload.maximum_size=4194304
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.tinyuf2_noota.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS)
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS)
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.fatflash.build.partitions=ffat
+adafruit_qualia_s3_rgb666.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+
+adafruit_qualia_s3_rgb666.menu.CPUFreq.240=240MHz (WiFi)
+adafruit_qualia_s3_rgb666.menu.CPUFreq.240.build.f_cpu=240000000L
+adafruit_qualia_s3_rgb666.menu.CPUFreq.160=160MHz (WiFi)
+adafruit_qualia_s3_rgb666.menu.CPUFreq.160.build.f_cpu=160000000L
+adafruit_qualia_s3_rgb666.menu.CPUFreq.80=80MHz (WiFi)
+adafruit_qualia_s3_rgb666.menu.CPUFreq.80.build.f_cpu=80000000L
+adafruit_qualia_s3_rgb666.menu.CPUFreq.40=40MHz
+adafruit_qualia_s3_rgb666.menu.CPUFreq.40.build.f_cpu=40000000L
+adafruit_qualia_s3_rgb666.menu.CPUFreq.20=20MHz
+adafruit_qualia_s3_rgb666.menu.CPUFreq.20.build.f_cpu=20000000L
+adafruit_qualia_s3_rgb666.menu.CPUFreq.10=10MHz
+adafruit_qualia_s3_rgb666.menu.CPUFreq.10.build.f_cpu=10000000L
+
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio=QIO 80MHz
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio.build.flash_mode=dio
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio.build.boot=qio
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio.build.boot_freq=80m
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio.build.flash_freq=80m
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio120=QIO 120MHz
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio120.build.flash_mode=dio
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio120.build.boot=qio
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio120.build.boot_freq=120m
+adafruit_qualia_s3_rgb666.menu.FlashMode.qio120.build.flash_freq=80m
+adafruit_qualia_s3_rgb666.menu.FlashMode.dio=DIO 80MHz
+adafruit_qualia_s3_rgb666.menu.FlashMode.dio.build.flash_mode=dio
+adafruit_qualia_s3_rgb666.menu.FlashMode.dio.build.boot=dio
+adafruit_qualia_s3_rgb666.menu.FlashMode.dio.build.boot_freq=80m
+adafruit_qualia_s3_rgb666.menu.FlashMode.dio.build.flash_freq=80m
+adafruit_qualia_s3_rgb666.menu.FlashMode.opi=OPI 80MHz
+adafruit_qualia_s3_rgb666.menu.FlashMode.opi.build.flash_mode=dout
+adafruit_qualia_s3_rgb666.menu.FlashMode.opi.build.boot=opi
+adafruit_qualia_s3_rgb666.menu.FlashMode.opi.build.boot_freq=80m
+adafruit_qualia_s3_rgb666.menu.FlashMode.opi.build.flash_freq=80m
+
+adafruit_qualia_s3_rgb666.menu.FlashSize.16M=16MB (128Mb)
+adafruit_qualia_s3_rgb666.menu.FlashSize.16M.build.flash_size=16MB
+
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.921600=921600
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.921600.upload.speed=921600
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.115200=115200
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.115200.upload.speed=115200
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.256000.windows=256000
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.256000.upload.speed=256000
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.230400.windows.upload.speed=256000
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.230400=230400
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.230400.upload.speed=230400
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.460800.linux=460800
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.460800.macosx=460800
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.460800.upload.speed=460800
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.512000.windows=512000
+adafruit_qualia_s3_rgb666.menu.UploadSpeed.512000.upload.speed=512000
+
+adafruit_qualia_s3_rgb666.menu.DebugLevel.none=None
+adafruit_qualia_s3_rgb666.menu.DebugLevel.none.build.code_debug=0
+adafruit_qualia_s3_rgb666.menu.DebugLevel.error=Error
+adafruit_qualia_s3_rgb666.menu.DebugLevel.error.build.code_debug=1
+adafruit_qualia_s3_rgb666.menu.DebugLevel.warn=Warn
+adafruit_qualia_s3_rgb666.menu.DebugLevel.warn.build.code_debug=2
+adafruit_qualia_s3_rgb666.menu.DebugLevel.info=Info
+adafruit_qualia_s3_rgb666.menu.DebugLevel.info.build.code_debug=3
+adafruit_qualia_s3_rgb666.menu.DebugLevel.debug=Debug
+adafruit_qualia_s3_rgb666.menu.DebugLevel.debug.build.code_debug=4
+adafruit_qualia_s3_rgb666.menu.DebugLevel.verbose=Verbose
+adafruit_qualia_s3_rgb666.menu.DebugLevel.verbose.build.code_debug=5
+
+adafruit_qualia_s3_rgb666.menu.EraseFlash.none=Disabled
+adafruit_qualia_s3_rgb666.menu.EraseFlash.none.upload.erase_cmd=
+adafruit_qualia_s3_rgb666.menu.EraseFlash.all=Enabled
+adafruit_qualia_s3_rgb666.menu.EraseFlash.all.upload.erase_cmd=-e
+
+adafruit_qualia_s3_rgb666.menu.ZigbeeMode.default=Disabled
+adafruit_qualia_s3_rgb666.menu.ZigbeeMode.default.build.zigbee_mode=
+adafruit_qualia_s3_rgb666.menu.ZigbeeMode.default.build.zigbee_libs=
+adafruit_qualia_s3_rgb666.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+adafruit_qualia_s3_rgb666.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+adafruit_qualia_s3_rgb666.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Sparkle Motion w/ESP32
+
+sparklemotion.name=Adafruit Sparkle Motion (ESP32)
+
+sparklemotion.bootloader.tool=esptool_py
+sparklemotion.bootloader.tool.default=esptool_py
+
+sparklemotion.upload.tool=esptool_py
+sparklemotion.upload.tool.default=esptool_py
+sparklemotion.upload.tool.network=esp_ota
+
+sparklemotion.upload.maximum_size=1310720
+sparklemotion.upload.maximum_data_size=327680
+sparklemotion.upload.flags=
+sparklemotion.upload.extra_flags=
+
+sparklemotion.serial.disableDTR=true
+sparklemotion.serial.disableRTS=true
+
+sparklemotion.build.tarch=xtensa
+sparklemotion.build.bootloader_addr=0x1000
+sparklemotion.build.target=esp32
+sparklemotion.build.mcu=esp32
+sparklemotion.build.core=esp32
+sparklemotion.build.variant=adafruit_sparklemotion_esp32
+sparklemotion.build.board=SPARKLEMOTION_ESP32
+
+sparklemotion.build.f_cpu=240000000L
+sparklemotion.build.flash_size=4MB
+sparklemotion.build.flash_freq=80m
+sparklemotion.build.flash_mode=dio
+sparklemotion.build.boot=dio
+sparklemotion.build.partitions=default
+sparklemotion.build.defines=
+sparklemotion.build.loop_core=
+sparklemotion.build.event_core=
+
+sparklemotion.menu.LoopCore.1=Core 1
+sparklemotion.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+sparklemotion.menu.LoopCore.0=Core 0
+sparklemotion.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+sparklemotion.menu.EventsCore.1=Core 1
+sparklemotion.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+sparklemotion.menu.EventsCore.0=Core 0
+sparklemotion.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+sparklemotion.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+sparklemotion.menu.PartitionScheme.default.build.partitions=default
+sparklemotion.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+sparklemotion.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+sparklemotion.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+sparklemotion.menu.PartitionScheme.minimal.build.partitions=minimal
+sparklemotion.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+sparklemotion.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sparklemotion.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sparklemotion.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+sparklemotion.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+sparklemotion.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+sparklemotion.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+sparklemotion.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+sparklemotion.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+sparklemotion.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+sparklemotion.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+sparklemotion.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+sparklemotion.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+sparklemotion.menu.PartitionScheme.huge_app.build.partitions=huge_app
+sparklemotion.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+sparklemotion.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+sparklemotion.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sparklemotion.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+sparklemotion.menu.CPUFreq.240=240MHz (WiFi/BT)
+sparklemotion.menu.CPUFreq.240.build.f_cpu=240000000L
+sparklemotion.menu.CPUFreq.160=160MHz (WiFi/BT)
+sparklemotion.menu.CPUFreq.160.build.f_cpu=160000000L
+sparklemotion.menu.CPUFreq.80=80MHz (WiFi/BT)
+sparklemotion.menu.CPUFreq.80.build.f_cpu=80000000L
+sparklemotion.menu.CPUFreq.40=40MHz
+sparklemotion.menu.CPUFreq.40.build.f_cpu=40000000L
+sparklemotion.menu.CPUFreq.20=20MHz
+sparklemotion.menu.CPUFreq.20.build.f_cpu=20000000L
+sparklemotion.menu.CPUFreq.10=10MHz
+sparklemotion.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sparklemotion.menu.FlashFreq.80=80MHz
+sparklemotion.menu.FlashFreq.80.build.flash_freq=80m
+sparklemotion.menu.FlashFreq.40=40MHz
+sparklemotion.menu.FlashFreq.40.build.flash_freq=40m
+
+sparklemotion.menu.FlashSize.4M=4MB (32Mb)
+sparklemotion.menu.FlashSize.4M.build.flash_size=4MB
+
+sparklemotion.menu.UploadSpeed.921600=921600
+sparklemotion.menu.UploadSpeed.921600.upload.speed=921600
+sparklemotion.menu.UploadSpeed.115200=115200
+sparklemotion.menu.UploadSpeed.115200.upload.speed=115200
+sparklemotion.menu.UploadSpeed.256000.windows=256000
+sparklemotion.menu.UploadSpeed.256000.upload.speed=256000
+sparklemotion.menu.UploadSpeed.230400.windows.upload.speed=256000
+sparklemotion.menu.UploadSpeed.230400=230400
+sparklemotion.menu.UploadSpeed.230400.upload.speed=230400
+sparklemotion.menu.UploadSpeed.460800.linux=460800
+sparklemotion.menu.UploadSpeed.460800.macosx=460800
+sparklemotion.menu.UploadSpeed.460800.upload.speed=460800
+sparklemotion.menu.UploadSpeed.512000.windows=512000
+sparklemotion.menu.UploadSpeed.512000.upload.speed=512000
+
+sparklemotion.menu.DebugLevel.none=None
+sparklemotion.menu.DebugLevel.none.build.code_debug=0
+sparklemotion.menu.DebugLevel.error=Error
+sparklemotion.menu.DebugLevel.error.build.code_debug=1
+sparklemotion.menu.DebugLevel.warn=Warn
+sparklemotion.menu.DebugLevel.warn.build.code_debug=2
+sparklemotion.menu.DebugLevel.info=Info
+sparklemotion.menu.DebugLevel.info.build.code_debug=3
+sparklemotion.menu.DebugLevel.debug=Debug
+sparklemotion.menu.DebugLevel.debug.build.code_debug=4
+sparklemotion.menu.DebugLevel.verbose=Verbose
+sparklemotion.menu.DebugLevel.verbose.build.code_debug=5
+
+sparklemotion.menu.EraseFlash.none=Disabled
+sparklemotion.menu.EraseFlash.none.upload.erase_cmd=
+sparklemotion.menu.EraseFlash.all=Enabled
+sparklemotion.menu.EraseFlash.all.upload.erase_cmd=-e
+
+sparklemotion.menu.ZigbeeMode.default=Disabled
+sparklemotion.menu.ZigbeeMode.default.build.zigbee_mode=
+sparklemotion.menu.ZigbeeMode.default.build.zigbee_libs=
+sparklemotion.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+sparklemotion.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+sparklemotion.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+# Adafruit Sparkle Motion Mini w/ESP32
+
+sparklemotionmini.name=Adafruit Sparkle Motion Mini (ESP32)
+
+sparklemotionmini.bootloader.tool=esptool_py
+sparklemotionmini.bootloader.tool.default=esptool_py
+
+sparklemotionmini.upload.tool=esptool_py
+sparklemotionmini.upload.tool.default=esptool_py
+sparklemotionmini.upload.tool.network=esp_ota
+
+sparklemotionmini.upload.maximum_size=1310720
+sparklemotionmini.upload.maximum_data_size=327680
+sparklemotionmini.upload.flags=
+sparklemotionmini.upload.extra_flags=
+
+sparklemotionmini.serial.disableDTR=true
+sparklemotionmini.serial.disableRTS=true
+
+sparklemotionmini.build.tarch=xtensa
+sparklemotionmini.build.bootloader_addr=0x1000
+sparklemotionmini.build.target=esp32
+sparklemotionmini.build.mcu=esp32
+sparklemotionmini.build.core=esp32
+sparklemotionmini.build.variant=adafruit_sparklemotionmini_esp32
+sparklemotionmini.build.board=SPARKLEMOTIONMINI_ESP32
+
+sparklemotionmini.build.f_cpu=240000000L
+sparklemotionmini.build.flash_size=4MB
+sparklemotionmini.build.flash_freq=80m
+sparklemotionmini.build.flash_mode=dio
+sparklemotionmini.build.boot=dio
+sparklemotionmini.build.partitions=default
+sparklemotionmini.build.defines=
+sparklemotionmini.build.loop_core=
+sparklemotionmini.build.event_core=
+
+sparklemotionmini.menu.LoopCore.1=Core 1
+sparklemotionmini.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+sparklemotionmini.menu.LoopCore.0=Core 0
+sparklemotionmini.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+sparklemotionmini.menu.EventsCore.1=Core 1
+sparklemotionmini.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+sparklemotionmini.menu.EventsCore.0=Core 0
+sparklemotionmini.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+sparklemotionmini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+sparklemotionmini.menu.PartitionScheme.default.build.partitions=default
+sparklemotionmini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+sparklemotionmini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+sparklemotionmini.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+sparklemotionmini.menu.PartitionScheme.minimal.build.partitions=minimal
+sparklemotionmini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+sparklemotionmini.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sparklemotionmini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sparklemotionmini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+sparklemotionmini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+sparklemotionmini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+sparklemotionmini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+sparklemotionmini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+sparklemotionmini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+sparklemotionmini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+sparklemotionmini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+sparklemotionmini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+sparklemotionmini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+sparklemotionmini.menu.PartitionScheme.huge_app.build.partitions=huge_app
+sparklemotionmini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+sparklemotionmini.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+sparklemotionmini.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sparklemotionmini.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+sparklemotionmini.menu.CPUFreq.240=240MHz (WiFi/BT)
+sparklemotionmini.menu.CPUFreq.240.build.f_cpu=240000000L
+sparklemotionmini.menu.CPUFreq.160=160MHz (WiFi/BT)
+sparklemotionmini.menu.CPUFreq.160.build.f_cpu=160000000L
+sparklemotionmini.menu.CPUFreq.80=80MHz (WiFi/BT)
+sparklemotionmini.menu.CPUFreq.80.build.f_cpu=80000000L
+sparklemotionmini.menu.CPUFreq.40=40MHz
+sparklemotionmini.menu.CPUFreq.40.build.f_cpu=40000000L
+sparklemotionmini.menu.CPUFreq.20=20MHz
+sparklemotionmini.menu.CPUFreq.20.build.f_cpu=20000000L
+sparklemotionmini.menu.CPUFreq.10=10MHz
+sparklemotionmini.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sparklemotionmini.menu.FlashFreq.80=80MHz
+sparklemotionmini.menu.FlashFreq.80.build.flash_freq=80m
+sparklemotionmini.menu.FlashFreq.40=40MHz
+sparklemotionmini.menu.FlashFreq.40.build.flash_freq=40m
+
+sparklemotionmini.menu.FlashSize.4M=4MB (32Mb)
+sparklemotionmini.menu.FlashSize.4M.build.flash_size=4MB
+
+sparklemotionmini.menu.UploadSpeed.921600=921600
+sparklemotionmini.menu.UploadSpeed.921600.upload.speed=921600
+sparklemotionmini.menu.UploadSpeed.115200=115200
+sparklemotionmini.menu.UploadSpeed.115200.upload.speed=115200
+sparklemotionmini.menu.UploadSpeed.256000.windows=256000
+sparklemotionmini.menu.UploadSpeed.256000.upload.speed=256000
+sparklemotionmini.menu.UploadSpeed.230400.windows.upload.speed=256000
+sparklemotionmini.menu.UploadSpeed.230400=230400
+sparklemotionmini.menu.UploadSpeed.230400.upload.speed=230400
+sparklemotionmini.menu.UploadSpeed.460800.linux=460800
+sparklemotionmini.menu.UploadSpeed.460800.macosx=460800
+sparklemotionmini.menu.UploadSpeed.460800.upload.speed=460800
+sparklemotionmini.menu.UploadSpeed.512000.windows=512000
+sparklemotionmini.menu.UploadSpeed.512000.upload.speed=512000
+
+sparklemotionmini.menu.DebugLevel.none=None
+sparklemotionmini.menu.DebugLevel.none.build.code_debug=0
+sparklemotionmini.menu.DebugLevel.error=Error
+sparklemotionmini.menu.DebugLevel.error.build.code_debug=1
+sparklemotionmini.menu.DebugLevel.warn=Warn
+sparklemotionmini.menu.DebugLevel.warn.build.code_debug=2
+sparklemotionmini.menu.DebugLevel.info=Info
+sparklemotionmini.menu.DebugLevel.info.build.code_debug=3
+sparklemotionmini.menu.DebugLevel.debug=Debug
+sparklemotionmini.menu.DebugLevel.debug.build.code_debug=4
+sparklemotionmini.menu.DebugLevel.verbose=Verbose
+sparklemotionmini.menu.DebugLevel.verbose.build.code_debug=5
+
+sparklemotionmini.menu.EraseFlash.none=Disabled
+sparklemotionmini.menu.EraseFlash.none.upload.erase_cmd=
+sparklemotionmini.menu.EraseFlash.all=Enabled
+sparklemotionmini.menu.EraseFlash.all.upload.erase_cmd=-e
+
+sparklemotionmini.menu.ZigbeeMode.default=Disabled
+sparklemotionmini.menu.ZigbeeMode.default.build.zigbee_mode=
+sparklemotionmini.menu.ZigbeeMode.default.build.zigbee_libs=
+sparklemotionmini.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+sparklemotionmini.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+sparklemotionmini.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
 
 ##############################################################
 
 nodemcu-32s.name=NodeMCU-32S
 
+nodemcu-32s.bootloader.tool=esptool_py
+nodemcu-32s.bootloader.tool.default=esptool_py
+
 nodemcu-32s.upload.tool=esptool_py
+nodemcu-32s.upload.tool.default=esptool_py
+nodemcu-32s.upload.tool.network=esp_ota
+
 nodemcu-32s.upload.maximum_size=1310720
 nodemcu-32s.upload.maximum_data_size=327680
-nodemcu-32s.upload.wait_for_upload_port=true
+nodemcu-32s.upload.flags=
+nodemcu-32s.upload.extra_flags=
 
 nodemcu-32s.serial.disableDTR=true
 nodemcu-32s.serial.disableRTS=true
 
+nodemcu-32s.build.tarch=xtensa
+nodemcu-32s.build.bootloader_addr=0x1000
+nodemcu-32s.build.target=esp32
 nodemcu-32s.build.mcu=esp32
 nodemcu-32s.build.core=esp32
 nodemcu-32s.build.variant=nodemcu-32s
-nodemcu-32s.build.board=NodeMCU_32S
+nodemcu-32s.build.board=NODEMCU_32S
 
 nodemcu-32s.build.f_cpu=240000000L
 nodemcu-32s.build.flash_mode=dio
@@ -1864,8 +17381,6 @@ nodemcu-32s.menu.FlashFreq.80.build.flash_freq=80m
 nodemcu-32s.menu.FlashFreq.40=40MHz
 nodemcu-32s.menu.FlashFreq.40.build.flash_freq=40m
 
-nodemcu-32s.menu.UploadSpeed.921600=921600
-nodemcu-32s.menu.UploadSpeed.921600.upload.speed=921600
 nodemcu-32s.menu.UploadSpeed.115200=115200
 nodemcu-32s.menu.UploadSpeed.115200.upload.speed=115200
 nodemcu-32s.menu.UploadSpeed.256000.windows=256000
@@ -1873,24 +17388,436 @@ nodemcu-32s.menu.UploadSpeed.256000.upload.speed=256000
 nodemcu-32s.menu.UploadSpeed.230400.windows.upload.speed=256000
 nodemcu-32s.menu.UploadSpeed.230400=230400
 nodemcu-32s.menu.UploadSpeed.230400.upload.speed=230400
+nodemcu-32s.menu.UploadSpeed.512000.windows=512000
+nodemcu-32s.menu.UploadSpeed.512000.upload.speed=512000
 nodemcu-32s.menu.UploadSpeed.460800.linux=460800
 nodemcu-32s.menu.UploadSpeed.460800.macosx=460800
 nodemcu-32s.menu.UploadSpeed.460800.upload.speed=460800
-nodemcu-32s.menu.UploadSpeed.512000.windows=512000
-nodemcu-32s.menu.UploadSpeed.512000.upload.speed=512000
+nodemcu-32s.menu.UploadSpeed.921600=921600
+nodemcu-32s.menu.UploadSpeed.921600.upload.speed=921600
+
+nodemcu-32s.menu.DebugLevel.none=None
+nodemcu-32s.menu.DebugLevel.none.build.code_debug=0
+nodemcu-32s.menu.DebugLevel.error=Error
+nodemcu-32s.menu.DebugLevel.error.build.code_debug=1
+nodemcu-32s.menu.DebugLevel.warn=Warn
+nodemcu-32s.menu.DebugLevel.warn.build.code_debug=2
+nodemcu-32s.menu.DebugLevel.info=Info
+nodemcu-32s.menu.DebugLevel.info.build.code_debug=3
+nodemcu-32s.menu.DebugLevel.debug=Debug
+nodemcu-32s.menu.DebugLevel.debug.build.code_debug=4
+nodemcu-32s.menu.DebugLevel.verbose=Verbose
+nodemcu-32s.menu.DebugLevel.verbose.build.code_debug=5
+
+nodemcu-32s.menu.EraseFlash.none=Disabled
+nodemcu-32s.menu.EraseFlash.none.upload.erase_cmd=
+nodemcu-32s.menu.EraseFlash.all=Enabled
+nodemcu-32s.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+nologo_esp32c3_super_mini.name=Nologo ESP32C3 Super Mini
+
+nologo_esp32c3_super_mini.upload.tool=esptool_py
+nologo_esp32c3_super_mini.upload.tool.default=esptool_py
+nologo_esp32c3_super_mini.upload.tool.network=esp_ota
+nologo_esp32c3_super_mini.upload.maximum_size=1310720
+nologo_esp32c3_super_mini.upload.maximum_data_size=327680
+nologo_esp32c3_super_mini.upload.flags=
+nologo_esp32c3_super_mini.upload.extra_flags=
+nologo_esp32c3_super_mini.upload.use_1200bps_touch=false
+nologo_esp32c3_super_mini.upload.wait_for_upload_port=false
+
+nologo_esp32c3_super_mini.serial.disableDTR=false
+nologo_esp32c3_super_mini.serial.disableRTS=false
+
+nologo_esp32c3_super_mini.build.tarch=riscv32
+nologo_esp32c3_super_mini.build.target=esp
+nologo_esp32c3_super_mini.build.mcu=esp32c3
+nologo_esp32c3_super_mini.build.core=esp32
+nologo_esp32c3_super_mini.build.variant=nologo_esp32c3_super_mini
+nologo_esp32c3_super_mini.build.board=NOLOGO_ESP32C3_SUPER_MINI
+nologo_esp32c3_super_mini.build.bootloader_addr=0x0
+
+nologo_esp32c3_super_mini.build.usb_mode=1
+nologo_esp32c3_super_mini.build.cdc_on_boot=1
+nologo_esp32c3_super_mini.build.f_cpu=160000000L
+nologo_esp32c3_super_mini.build.flash_size=4MB
+nologo_esp32c3_super_mini.build.flash_freq=80m
+nologo_esp32c3_super_mini.build.flash_mode=qio
+nologo_esp32c3_super_mini.build.boot=qio
+nologo_esp32c3_super_mini.build.partitions=default
+nologo_esp32c3_super_mini.build.defines=
+
+nologo_esp32c3_super_mini.menu.USBMode.hwcdc=Hardware CDC and JTAG
+nologo_esp32c3_super_mini.menu.USBMode.hwcdc.build.usb_mode=1
+nologo_esp32c3_super_mini.menu.USBMode.default=USB-OTG
+nologo_esp32c3_super_mini.menu.USBMode.default.build.usb_mode=0
+
+nologo_esp32c3_super_mini.menu.JTAGAdapter.default=Disabled
+nologo_esp32c3_super_mini.menu.JTAGAdapter.default.build.copy_jtag_files=0
+nologo_esp32c3_super_mini.menu.JTAGAdapter.builtin=Integrated USB JTAG
+nologo_esp32c3_super_mini.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg
+nologo_esp32c3_super_mini.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+nologo_esp32c3_super_mini.menu.JTAGAdapter.external=FTDI Adapter
+nologo_esp32c3_super_mini.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg
+nologo_esp32c3_super_mini.menu.JTAGAdapter.external.build.copy_jtag_files=1
+nologo_esp32c3_super_mini.menu.JTAGAdapter.bridge=ESP USB Bridge
+nologo_esp32c3_super_mini.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg
+nologo_esp32c3_super_mini.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+nologo_esp32c3_super_mini.menu.CDCOnBoot.default=Enabled
+nologo_esp32c3_super_mini.menu.CDCOnBoot.default.build.cdc_on_boot=1
+nologo_esp32c3_super_mini.menu.CDCOnBoot.cdc=Enabled
+nologo_esp32c3_super_mini.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+nologo_esp32c3_super_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+nologo_esp32c3_super_mini.menu.PartitionScheme.default.build.partitions=default
+nologo_esp32c3_super_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+nologo_esp32c3_super_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+nologo_esp32c3_super_mini.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+nologo_esp32c3_super_mini.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+nologo_esp32c3_super_mini.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+nologo_esp32c3_super_mini.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+nologo_esp32c3_super_mini.menu.PartitionScheme.minimal.build.partitions=minimal
+nologo_esp32c3_super_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+nologo_esp32c3_super_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota
+nologo_esp32c3_super_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+nologo_esp32c3_super_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+nologo_esp32c3_super_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+nologo_esp32c3_super_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+nologo_esp32c3_super_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+nologo_esp32c3_super_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+nologo_esp32c3_super_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app
+nologo_esp32c3_super_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+nologo_esp32c3_super_mini.menu.CPUFreq.160=160MHz (WiFi)
+nologo_esp32c3_super_mini.menu.CPUFreq.160.build.f_cpu=160000000L
+nologo_esp32c3_super_mini.menu.CPUFreq.80=80MHz (WiFi)
+nologo_esp32c3_super_mini.menu.CPUFreq.80.build.f_cpu=80000000L
+nologo_esp32c3_super_mini.menu.CPUFreq.40=40MHz
+nologo_esp32c3_super_mini.menu.CPUFreq.40.build.f_cpu=40000000L
+nologo_esp32c3_super_mini.menu.CPUFreq.20=20MHz
+nologo_esp32c3_super_mini.menu.CPUFreq.20.build.f_cpu=20000000L
+nologo_esp32c3_super_mini.menu.CPUFreq.10=10MHz
+nologo_esp32c3_super_mini.menu.CPUFreq.10.build.f_cpu=10000000L
+
+nologo_esp32c3_super_mini.menu.FlashMode.qio=QIO
+nologo_esp32c3_super_mini.menu.FlashMode.qio.build.flash_mode=dio
+nologo_esp32c3_super_mini.menu.FlashMode.qio.build.boot=qio
+nologo_esp32c3_super_mini.menu.FlashMode.dio=DIO
+nologo_esp32c3_super_mini.menu.FlashMode.dio.build.flash_mode=dio
+nologo_esp32c3_super_mini.menu.FlashMode.dio.build.boot=dio
+
+nologo_esp32c3_super_mini.menu.FlashFreq.80=80MHz
+nologo_esp32c3_super_mini.menu.FlashFreq.80.build.flash_freq=80m
+nologo_esp32c3_super_mini.menu.FlashFreq.40=40MHz
+nologo_esp32c3_super_mini.menu.FlashFreq.40.build.flash_freq=40m
+
+nologo_esp32c3_super_mini.menu.UploadSpeed.921600=921600
+nologo_esp32c3_super_mini.menu.UploadSpeed.921600.upload.speed=921600
+nologo_esp32c3_super_mini.menu.UploadSpeed.115200=115200
+nologo_esp32c3_super_mini.menu.UploadSpeed.115200.upload.speed=115200
+nologo_esp32c3_super_mini.menu.UploadSpeed.256000.windows=256000
+nologo_esp32c3_super_mini.menu.UploadSpeed.256000.upload.speed=256000
+nologo_esp32c3_super_mini.menu.UploadSpeed.230400.windows.upload.speed=256000
+nologo_esp32c3_super_mini.menu.UploadSpeed.230400=230400
+nologo_esp32c3_super_mini.menu.UploadSpeed.230400.upload.speed=230400
+nologo_esp32c3_super_mini.menu.UploadSpeed.460800.linux=460800
+nologo_esp32c3_super_mini.menu.UploadSpeed.460800.macosx=460800
+nologo_esp32c3_super_mini.menu.UploadSpeed.460800.upload.speed=460800
+nologo_esp32c3_super_mini.menu.UploadSpeed.512000.windows=512000
+nologo_esp32c3_super_mini.menu.UploadSpeed.512000.upload.speed=512000
+
+nologo_esp32c3_super_mini.menu.DebugLevel.none=None
+nologo_esp32c3_super_mini.menu.DebugLevel.none.build.code_debug=0
+nologo_esp32c3_super_mini.menu.DebugLevel.error=Error
+nologo_esp32c3_super_mini.menu.DebugLevel.error.build.code_debug=1
+nologo_esp32c3_super_mini.menu.DebugLevel.warn=Warn
+nologo_esp32c3_super_mini.menu.DebugLevel.warn.build.code_debug=2
+nologo_esp32c3_super_mini.menu.DebugLevel.info=Info
+nologo_esp32c3_super_mini.menu.DebugLevel.info.build.code_debug=3
+nologo_esp32c3_super_mini.menu.DebugLevel.debug=Debug
+nologo_esp32c3_super_mini.menu.DebugLevel.debug.build.code_debug=4
+nologo_esp32c3_super_mini.menu.DebugLevel.verbose=Verbose
+nologo_esp32c3_super_mini.menu.DebugLevel.verbose.build.code_debug=5
+
+nologo_esp32c3_super_mini.menu.EraseFlash.none=Disabled
+nologo_esp32c3_super_mini.menu.EraseFlash.none.upload.erase_cmd=
+nologo_esp32c3_super_mini.menu.EraseFlash.all=Enabled
+nologo_esp32c3_super_mini.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+nologo_esp32s3_pico.name=Nologo ESP32S3 Pico
+
+nologo_esp32s3_pico.bootloader.tool=esptool_py
+nologo_esp32s3_pico.bootloader.tool.default=esptool_py
+
+nologo_esp32s3_pico.upload.tool=esptool_py
+nologo_esp32s3_pico.upload.tool.default=esptool_py
+nologo_esp32s3_pico.upload.tool.network=esp_ota
+
+nologo_esp32s3_pico.upload.maximum_size=1310720
+nologo_esp32s3_pico.upload.maximum_data_size=327680
+nologo_esp32s3_pico.upload.flags=
+nologo_esp32s3_pico.upload.extra_flags=
+nologo_esp32s3_pico.upload.use_1200bps_touch=false
+nologo_esp32s3_pico.upload.wait_for_upload_port=false
+
+nologo_esp32s3_pico.serial.disableDTR=false
+nologo_esp32s3_pico.serial.disableRTS=false
+
+nologo_esp32s3_pico.build.tarch=xtensa
+nologo_esp32s3_pico.build.bootloader_addr=0x0
+nologo_esp32s3_pico.build.target=esp32s3
+nologo_esp32s3_pico.build.mcu=esp32s3
+nologo_esp32s3_pico.build.core=esp32
+nologo_esp32s3_pico.build.variant=nologo_esp32s3_pico
+nologo_esp32s3_pico.build.board=NOLOGO_ESP32S3_PICO
+
+nologo_esp32s3_pico.build.usb_mode=1
+nologo_esp32s3_pico.build.cdc_on_boot=1
+nologo_esp32s3_pico.build.msc_on_boot=0
+nologo_esp32s3_pico.build.dfu_on_boot=0
+nologo_esp32s3_pico.build.f_cpu=240000000L
+nologo_esp32s3_pico.build.flash_size=8MB
+nologo_esp32s3_pico.build.flash_freq=80m
+nologo_esp32s3_pico.build.flash_mode=dio
+nologo_esp32s3_pico.build.boot=qio
+nologo_esp32s3_pico.build.boot_freq=80m
+nologo_esp32s3_pico.build.partitions=default
+nologo_esp32s3_pico.build.defines=
+nologo_esp32s3_pico.build.loop_core=
+nologo_esp32s3_pico.build.event_core=
+nologo_esp32s3_pico.build.psram_type=qspi
+nologo_esp32s3_pico.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+nologo_esp32s3_pico.menu.JTAGAdapter.default=Disabled
+nologo_esp32s3_pico.menu.JTAGAdapter.default.build.copy_jtag_files=0
+nologo_esp32s3_pico.menu.JTAGAdapter.builtin=Integrated USB JTAG
+nologo_esp32s3_pico.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+nologo_esp32s3_pico.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+nologo_esp32s3_pico.menu.JTAGAdapter.external=FTDI Adapter
+nologo_esp32s3_pico.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+nologo_esp32s3_pico.menu.JTAGAdapter.external.build.copy_jtag_files=1
+nologo_esp32s3_pico.menu.JTAGAdapter.bridge=ESP USB Bridge
+nologo_esp32s3_pico.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+nologo_esp32s3_pico.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+nologo_esp32s3_pico.menu.PSRAM.disabled=Disabled
+nologo_esp32s3_pico.menu.PSRAM.disabled.build.defines=
+nologo_esp32s3_pico.menu.PSRAM.disabled.build.psram_type=qspi
+nologo_esp32s3_pico.menu.PSRAM.enabled=QSPI PSRAM
+nologo_esp32s3_pico.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+nologo_esp32s3_pico.menu.PSRAM.enabled.build.psram_type=qspi
+nologo_esp32s3_pico.menu.PSRAM.opi=OPI PSRAM
+nologo_esp32s3_pico.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+nologo_esp32s3_pico.menu.PSRAM.opi.build.psram_type=opi
+
+nologo_esp32s3_pico.menu.FlashMode.qio=QIO 80MHz
+nologo_esp32s3_pico.menu.FlashMode.qio.build.flash_mode=dio
+nologo_esp32s3_pico.menu.FlashMode.qio.build.boot=qio
+nologo_esp32s3_pico.menu.FlashMode.qio.build.boot_freq=80m
+nologo_esp32s3_pico.menu.FlashMode.qio.build.flash_freq=80m
+nologo_esp32s3_pico.menu.FlashMode.qio120=QIO 120MHz
+nologo_esp32s3_pico.menu.FlashMode.qio120.build.flash_mode=dio
+nologo_esp32s3_pico.menu.FlashMode.qio120.build.boot=qio
+nologo_esp32s3_pico.menu.FlashMode.qio120.build.boot_freq=120m
+nologo_esp32s3_pico.menu.FlashMode.qio120.build.flash_freq=80m
+nologo_esp32s3_pico.menu.FlashMode.dio=DIO 80MHz
+nologo_esp32s3_pico.menu.FlashMode.dio.build.flash_mode=dio
+nologo_esp32s3_pico.menu.FlashMode.dio.build.boot=dio
+nologo_esp32s3_pico.menu.FlashMode.dio.build.boot_freq=80m
+nologo_esp32s3_pico.menu.FlashMode.dio.build.flash_freq=80m
+nologo_esp32s3_pico.menu.FlashMode.opi=OPI 80MHz
+nologo_esp32s3_pico.menu.FlashMode.opi.build.flash_mode=dout
+nologo_esp32s3_pico.menu.FlashMode.opi.build.boot=opi
+nologo_esp32s3_pico.menu.FlashMode.opi.build.boot_freq=80m
+nologo_esp32s3_pico.menu.FlashMode.opi.build.flash_freq=80m
+
+nologo_esp32s3_pico.menu.FlashSize.8M=8MB (64Mb)
+nologo_esp32s3_pico.menu.FlashSize.8M.build.flash_size=8MB
+nologo_esp32s3_pico.menu.FlashSize.16M=16MB (128Mb)
+nologo_esp32s3_pico.menu.FlashSize.16M.build.flash_size=16MB
+
+nologo_esp32s3_pico.menu.LoopCore.1=Core 1
+nologo_esp32s3_pico.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+nologo_esp32s3_pico.menu.LoopCore.0=Core 0
+nologo_esp32s3_pico.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+nologo_esp32s3_pico.menu.EventsCore.1=Core 1
+nologo_esp32s3_pico.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+nologo_esp32s3_pico.menu.EventsCore.0=Core 0
+nologo_esp32s3_pico.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+nologo_esp32s3_pico.menu.USBMode.hwcdc=Hardware CDC and JTAG
+nologo_esp32s3_pico.menu.USBMode.hwcdc.build.usb_mode=1
+nologo_esp32s3_pico.menu.USBMode.default=USB-OTG (TinyUSB)
+nologo_esp32s3_pico.menu.USBMode.default.build.usb_mode=0
+
+nologo_esp32s3_pico.menu.CDCOnBoot.default=Enabled
+nologo_esp32s3_pico.menu.CDCOnBoot.default.build.cdc_on_boot=1
+nologo_esp32s3_pico.menu.CDCOnBoot.cdc=Enabled
+nologo_esp32s3_pico.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+nologo_esp32s3_pico.menu.MSCOnBoot.default=Disabled
+nologo_esp32s3_pico.menu.MSCOnBoot.default.build.msc_on_boot=0
+nologo_esp32s3_pico.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+nologo_esp32s3_pico.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+nologo_esp32s3_pico.menu.DFUOnBoot.default=Disabled
+nologo_esp32s3_pico.menu.DFUOnBoot.default.build.dfu_on_boot=0
+nologo_esp32s3_pico.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+nologo_esp32s3_pico.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+nologo_esp32s3_pico.menu.UploadMode.default=UART0 / Hardware CDC
+nologo_esp32s3_pico.menu.UploadMode.default.upload.use_1200bps_touch=false
+nologo_esp32s3_pico.menu.UploadMode.default.upload.wait_for_upload_port=false
+nologo_esp32s3_pico.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+nologo_esp32s3_pico.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+nologo_esp32s3_pico.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+nologo_esp32s3_pico.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+nologo_esp32s3_pico.menu.PartitionScheme.default.build.partitions=default
+nologo_esp32s3_pico.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+nologo_esp32s3_pico.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+nologo_esp32s3_pico.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+nologo_esp32s3_pico.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+nologo_esp32s3_pico.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+nologo_esp32s3_pico.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+nologo_esp32s3_pico.menu.PartitionScheme.minimal.build.partitions=minimal
+nologo_esp32s3_pico.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+nologo_esp32s3_pico.menu.PartitionScheme.no_ota.build.partitions=no_ota
+nologo_esp32s3_pico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+nologo_esp32s3_pico.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+nologo_esp32s3_pico.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+nologo_esp32s3_pico.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+nologo_esp32s3_pico.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+nologo_esp32s3_pico.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+nologo_esp32s3_pico.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+nologo_esp32s3_pico.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+nologo_esp32s3_pico.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+nologo_esp32s3_pico.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+nologo_esp32s3_pico.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+nologo_esp32s3_pico.menu.PartitionScheme.huge_app.build.partitions=huge_app
+nologo_esp32s3_pico.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+nologo_esp32s3_pico.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+nologo_esp32s3_pico.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+nologo_esp32s3_pico.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+nologo_esp32s3_pico.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+nologo_esp32s3_pico.menu.PartitionScheme.fatflash.build.partitions=ffat
+nologo_esp32s3_pico.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+nologo_esp32s3_pico.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+nologo_esp32s3_pico.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+nologo_esp32s3_pico.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+nologo_esp32s3_pico.menu.PartitionScheme.rainmaker=RainMaker 4MB
+nologo_esp32s3_pico.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+nologo_esp32s3_pico.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+nologo_esp32s3_pico.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+nologo_esp32s3_pico.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+nologo_esp32s3_pico.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+nologo_esp32s3_pico.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+nologo_esp32s3_pico.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+nologo_esp32s3_pico.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+nologo_esp32s3_pico.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+nologo_esp32s3_pico.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+nologo_esp32s3_pico.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+nologo_esp32s3_pico.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+nologo_esp32s3_pico.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+nologo_esp32s3_pico.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+nologo_esp32s3_pico.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+nologo_esp32s3_pico.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+nologo_esp32s3_pico.menu.PartitionScheme.custom=Custom
+nologo_esp32s3_pico.menu.PartitionScheme.custom.build.partitions=
+nologo_esp32s3_pico.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+nologo_esp32s3_pico.menu.CPUFreq.240=240MHz (WiFi)
+nologo_esp32s3_pico.menu.CPUFreq.240.build.f_cpu=240000000L
+nologo_esp32s3_pico.menu.CPUFreq.160=160MHz (WiFi)
+nologo_esp32s3_pico.menu.CPUFreq.160.build.f_cpu=160000000L
+nologo_esp32s3_pico.menu.CPUFreq.80=80MHz (WiFi)
+nologo_esp32s3_pico.menu.CPUFreq.80.build.f_cpu=80000000L
+nologo_esp32s3_pico.menu.CPUFreq.40=40MHz
+nologo_esp32s3_pico.menu.CPUFreq.40.build.f_cpu=40000000L
+nologo_esp32s3_pico.menu.CPUFreq.20=20MHz
+nologo_esp32s3_pico.menu.CPUFreq.20.build.f_cpu=20000000L
+nologo_esp32s3_pico.menu.CPUFreq.10=10MHz
+nologo_esp32s3_pico.menu.CPUFreq.10.build.f_cpu=10000000L
+
+nologo_esp32s3_pico.menu.UploadSpeed.921600=921600
+nologo_esp32s3_pico.menu.UploadSpeed.921600.upload.speed=921600
+nologo_esp32s3_pico.menu.UploadSpeed.115200=115200
+nologo_esp32s3_pico.menu.UploadSpeed.115200.upload.speed=115200
+nologo_esp32s3_pico.menu.UploadSpeed.256000.windows=256000
+nologo_esp32s3_pico.menu.UploadSpeed.256000.upload.speed=256000
+nologo_esp32s3_pico.menu.UploadSpeed.230400.windows.upload.speed=256000
+nologo_esp32s3_pico.menu.UploadSpeed.230400=230400
+nologo_esp32s3_pico.menu.UploadSpeed.230400.upload.speed=230400
+nologo_esp32s3_pico.menu.UploadSpeed.460800.linux=460800
+nologo_esp32s3_pico.menu.UploadSpeed.460800.macosx=460800
+nologo_esp32s3_pico.menu.UploadSpeed.460800.upload.speed=460800
+nologo_esp32s3_pico.menu.UploadSpeed.512000.windows=512000
+nologo_esp32s3_pico.menu.UploadSpeed.512000.upload.speed=512000
+
+nologo_esp32s3_pico.menu.DebugLevel.none=None
+nologo_esp32s3_pico.menu.DebugLevel.none.build.code_debug=0
+nologo_esp32s3_pico.menu.DebugLevel.error=Error
+nologo_esp32s3_pico.menu.DebugLevel.error.build.code_debug=1
+nologo_esp32s3_pico.menu.DebugLevel.warn=Warn
+nologo_esp32s3_pico.menu.DebugLevel.warn.build.code_debug=2
+nologo_esp32s3_pico.menu.DebugLevel.info=Info
+nologo_esp32s3_pico.menu.DebugLevel.info.build.code_debug=3
+nologo_esp32s3_pico.menu.DebugLevel.debug=Debug
+nologo_esp32s3_pico.menu.DebugLevel.debug.build.code_debug=4
+nologo_esp32s3_pico.menu.DebugLevel.verbose=Verbose
+nologo_esp32s3_pico.menu.DebugLevel.verbose.build.code_debug=5
+
+nologo_esp32s3_pico.menu.EraseFlash.none=Disabled
+nologo_esp32s3_pico.menu.EraseFlash.none.upload.erase_cmd=
+nologo_esp32s3_pico.menu.EraseFlash.all=Enabled
+nologo_esp32s3_pico.menu.EraseFlash.all.upload.erase_cmd=-e
+
+nologo_esp32s3_pico.menu.ZigbeeMode.default=Disabled
+nologo_esp32s3_pico.menu.ZigbeeMode.default.build.zigbee_mode=
+nologo_esp32s3_pico.menu.ZigbeeMode.default.build.zigbee_libs=
+nologo_esp32s3_pico.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+nologo_esp32s3_pico.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+nologo_esp32s3_pico.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
 
 ##############################################################
 
 mhetesp32devkit.name=MH ET LIVE ESP32DevKIT
 
+mhetesp32devkit.bootloader.tool=esptool_py
+mhetesp32devkit.bootloader.tool.default=esptool_py
+
 mhetesp32devkit.upload.tool=esptool_py
+mhetesp32devkit.upload.tool.default=esptool_py
+mhetesp32devkit.upload.tool.network=esp_ota
+
 mhetesp32devkit.upload.maximum_size=1310720
 mhetesp32devkit.upload.maximum_data_size=327680
-mhetesp32devkit.upload.wait_for_upload_port=true
+mhetesp32devkit.upload.flags=
+mhetesp32devkit.upload.extra_flags=
 
 mhetesp32devkit.serial.disableDTR=true
 mhetesp32devkit.serial.disableRTS=true
 
+mhetesp32devkit.build.tarch=xtensa
+mhetesp32devkit.build.bootloader_addr=0x1000
+mhetesp32devkit.build.target=esp32
 mhetesp32devkit.build.mcu=esp32
 mhetesp32devkit.build.core=esp32
 mhetesp32devkit.build.variant=mhetesp32devkit
@@ -1945,18 +17872,33 @@ mhetesp32devkit.menu.DebugLevel.debug.build.code_debug=4
 mhetesp32devkit.menu.DebugLevel.verbose=Verbose
 mhetesp32devkit.menu.DebugLevel.verbose.build.code_debug=5
 
+mhetesp32devkit.menu.EraseFlash.none=Disabled
+mhetesp32devkit.menu.EraseFlash.none.upload.erase_cmd=
+mhetesp32devkit.menu.EraseFlash.all=Enabled
+mhetesp32devkit.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 mhetesp32minikit.name=MH ET LIVE ESP32MiniKit
 
+mhetesp32minikit.bootloader.tool=esptool_py
+mhetesp32minikit.bootloader.tool.default=esptool_py
+
 mhetesp32minikit.upload.tool=esptool_py
+mhetesp32minikit.upload.tool.default=esptool_py
+mhetesp32minikit.upload.tool.network=esp_ota
+
 mhetesp32minikit.upload.maximum_size=1310720
 mhetesp32minikit.upload.maximum_data_size=327680
-mhetesp32minikit.upload.wait_for_upload_port=true
+mhetesp32minikit.upload.flags=
+mhetesp32minikit.upload.extra_flags=
 
 mhetesp32minikit.serial.disableDTR=true
 mhetesp32minikit.serial.disableRTS=true
 
+mhetesp32minikit.build.tarch=xtensa
+mhetesp32minikit.build.bootloader_addr=0x1000
+mhetesp32minikit.build.target=esp32
 mhetesp32minikit.build.mcu=esp32
 mhetesp32minikit.build.core=esp32
 mhetesp32minikit.build.variant=mhetesp32minikit
@@ -2013,18 +17955,33 @@ mhetesp32minikit.menu.DebugLevel.debug.build.code_debug=4
 mhetesp32minikit.menu.DebugLevel.verbose=Verbose
 mhetesp32minikit.menu.DebugLevel.verbose.build.code_debug=5
 
-#################################################################
+mhetesp32minikit.menu.EraseFlash.none=Disabled
+mhetesp32minikit.menu.EraseFlash.none.upload.erase_cmd=
+mhetesp32minikit.menu.EraseFlash.all=Enabled
+mhetesp32minikit.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
 
 esp32vn-iot-uno.name=ESP32vn IoT Uno
 
+esp32vn-iot-uno.bootloader.tool=esptool_py
+esp32vn-iot-uno.bootloader.tool.default=esptool_py
+
 esp32vn-iot-uno.upload.tool=esptool_py
+esp32vn-iot-uno.upload.tool.default=esptool_py
+esp32vn-iot-uno.upload.tool.network=esp_ota
+
 esp32vn-iot-uno.upload.maximum_size=1310720
 esp32vn-iot-uno.upload.maximum_data_size=327680
-esp32vn-iot-uno.upload.wait_for_upload_port=true
+esp32vn-iot-uno.upload.flags=
+esp32vn-iot-uno.upload.extra_flags=
 
 esp32vn-iot-uno.serial.disableDTR=true
 esp32vn-iot-uno.serial.disableRTS=true
 
+esp32vn-iot-uno.build.tarch=xtensa
+esp32vn-iot-uno.build.bootloader_addr=0x1000
+esp32vn-iot-uno.build.target=esp32
 esp32vn-iot-uno.build.mcu=esp32
 esp32vn-iot-uno.build.core=esp32
 esp32vn-iot-uno.build.variant=esp32vn-iot-uno
@@ -2057,18 +18014,46 @@ esp32vn-iot-uno.menu.UploadSpeed.460800.upload.speed=460800
 esp32vn-iot-uno.menu.UploadSpeed.512000.windows=512000
 esp32vn-iot-uno.menu.UploadSpeed.512000.upload.speed=512000
 
+esp32vn-iot-uno.menu.DebugLevel.none=None
+esp32vn-iot-uno.menu.DebugLevel.none.build.code_debug=0
+esp32vn-iot-uno.menu.DebugLevel.error=Error
+esp32vn-iot-uno.menu.DebugLevel.error.build.code_debug=1
+esp32vn-iot-uno.menu.DebugLevel.warn=Warn
+esp32vn-iot-uno.menu.DebugLevel.warn.build.code_debug=2
+esp32vn-iot-uno.menu.DebugLevel.info=Info
+esp32vn-iot-uno.menu.DebugLevel.info.build.code_debug=3
+esp32vn-iot-uno.menu.DebugLevel.debug=Debug
+esp32vn-iot-uno.menu.DebugLevel.debug.build.code_debug=4
+esp32vn-iot-uno.menu.DebugLevel.verbose=Verbose
+esp32vn-iot-uno.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32vn-iot-uno.menu.EraseFlash.none=Disabled
+esp32vn-iot-uno.menu.EraseFlash.none.upload.erase_cmd=
+esp32vn-iot-uno.menu.EraseFlash.all=Enabled
+esp32vn-iot-uno.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 esp32doit-devkit-v1.name=DOIT ESP32 DEVKIT V1
 
+esp32doit-devkit-v1.bootloader.tool=esptool_py
+esp32doit-devkit-v1.bootloader.tool.default=esptool_py
+
 esp32doit-devkit-v1.upload.tool=esptool_py
+esp32doit-devkit-v1.upload.tool.default=esptool_py
+esp32doit-devkit-v1.upload.tool.network=esp_ota
+
 esp32doit-devkit-v1.upload.maximum_size=1310720
 esp32doit-devkit-v1.upload.maximum_data_size=327680
-esp32doit-devkit-v1.upload.wait_for_upload_port=true
+esp32doit-devkit-v1.upload.flags=
+esp32doit-devkit-v1.upload.extra_flags=
 
 esp32doit-devkit-v1.serial.disableDTR=true
 esp32doit-devkit-v1.serial.disableRTS=true
 
+esp32doit-devkit-v1.build.tarch=xtensa
+esp32doit-devkit-v1.build.bootloader_addr=0x1000
+esp32doit-devkit-v1.build.target=esp32
 esp32doit-devkit-v1.build.mcu=esp32
 esp32doit-devkit-v1.build.core=esp32
 esp32doit-devkit-v1.build.variant=doitESP32devkitV1
@@ -2112,18 +18097,34 @@ esp32doit-devkit-v1.menu.DebugLevel.info.build.code_debug=3
 esp32doit-devkit-v1.menu.DebugLevel.debug=Debug
 esp32doit-devkit-v1.menu.DebugLevel.debug.build.code_debug=4
 
+esp32doit-devkit-v1.menu.EraseFlash.none=Disabled
+esp32doit-devkit-v1.menu.EraseFlash.none.upload.erase_cmd=
+esp32doit-devkit-v1.menu.EraseFlash.all=Enabled
+esp32doit-devkit-v1.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 esp32doit-espduino.name=DOIT ESPduino32
 
-esp32doit-espduino.upload.tool=esptool
+esp32doit-espduino.bootloader.tool=esptool_py
+esp32doit-espduino.bootloader.tool.default=esptool_py
+
+esp32doit-espduino.upload.tool=esptool_py
+esp32doit-espduino.upload.tool.default=esptool_py
+esp32doit-espduino.upload.tool.network=esp_ota
+
 esp32doit-espduino.upload.maximum_size=1310720
 esp32doit-espduino.upload.maximum_data_size=327680
 esp32doit-espduino.upload.wait_for_upload_port=true
+esp32doit-espduino.upload.flags=
+esp32doit-espduino.upload.extra_flags=
 
 esp32doit-espduino.serial.disableDTR=true
 esp32doit-espduino.serial.disableRTS=true
 
+esp32doit-espduino.build.tarch=xtensa
+esp32doit-espduino.build.bootloader_addr=0x1000
+esp32doit-espduino.build.target=esp32
 esp32doit-espduino.build.mcu=esp32
 esp32doit-espduino.build.core=esp32
 esp32doit-espduino.build.variant=doitESPduino32
@@ -2141,6 +18142,32 @@ esp32doit-espduino.menu.FlashFreq.80.build.flash_freq=80m
 esp32doit-espduino.menu.FlashFreq.40=40MHz
 esp32doit-espduino.menu.FlashFreq.40.build.flash_freq=40m
 
+esp32doit-espduino.menu.PartitionScheme.default=Default
+esp32doit-espduino.menu.PartitionScheme.default.build.partitions=default
+esp32doit-espduino.menu.PartitionScheme.no_ota=No OTA (Large APP)
+esp32doit-espduino.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32doit-espduino.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32doit-espduino.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+esp32doit-espduino.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32doit-espduino.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+esp32doit-espduino.menu.CPUFreq.240=240MHz (WiFi/BT)
+esp32doit-espduino.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32doit-espduino.menu.CPUFreq.160=160MHz (WiFi/BT)
+esp32doit-espduino.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32doit-espduino.menu.CPUFreq.80=80MHz (WiFi/BT)
+esp32doit-espduino.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32doit-espduino.menu.CPUFreq.40=40MHz (40MHz XTAL)
+esp32doit-espduino.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32doit-espduino.menu.CPUFreq.26=26MHz (26MHz XTAL)
+esp32doit-espduino.menu.CPUFreq.26.build.f_cpu=26000000L
+esp32doit-espduino.menu.CPUFreq.20=20MHz (40MHz XTAL)
+esp32doit-espduino.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32doit-espduino.menu.CPUFreq.13=13MHz (26MHz XTAL)
+esp32doit-espduino.menu.CPUFreq.13.build.f_cpu=13000000L
+esp32doit-espduino.menu.CPUFreq.10=10MHz (40MHz XTAL)
+esp32doit-espduino.menu.CPUFreq.10.build.f_cpu=10000000L
+
 esp32doit-espduino.menu.UploadSpeed.921600=921600
 esp32doit-espduino.menu.UploadSpeed.921600.upload.speed=921600
 esp32doit-espduino.menu.UploadSpeed.115200=115200
@@ -2166,19 +18193,36 @@ esp32doit-espduino.menu.DebugLevel.info=Info
 esp32doit-espduino.menu.DebugLevel.info.build.code_debug=3
 esp32doit-espduino.menu.DebugLevel.debug=Debug
 esp32doit-espduino.menu.DebugLevel.debug.build.code_debug=4
+esp32doit-espduino.menu.DebugLevel.verbose=Verbose
+esp32doit-espduino.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32doit-espduino.menu.EraseFlash.none=Disabled
+esp32doit-espduino.menu.EraseFlash.none.upload.erase_cmd=
+esp32doit-espduino.menu.EraseFlash.all=Enabled
+esp32doit-espduino.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
 
 esp32-evb.name=OLIMEX ESP32-EVB
 
+esp32-evb.bootloader.tool=esptool_py
+esp32-evb.bootloader.tool.default=esptool_py
+
 esp32-evb.upload.tool=esptool_py
+esp32-evb.upload.tool.default=esptool_py
+esp32-evb.upload.tool.network=esp_ota
+
 esp32-evb.upload.maximum_size=1310720
 esp32-evb.upload.maximum_data_size=327680
-esp32-evb.upload.wait_for_upload_port=true
+esp32-evb.upload.flags=
+esp32-evb.upload.extra_flags=
 
 esp32-evb.serial.disableDTR=true
 esp32-evb.serial.disableRTS=true
 
+esp32-evb.build.tarch=xtensa
+esp32-evb.build.bootloader_addr=0x1000
+esp32-evb.build.target=esp32
 esp32-evb.build.mcu=esp32
 esp32-evb.build.core=esp32
 esp32-evb.build.variant=esp32-evb
@@ -2196,9 +18240,20 @@ esp32-evb.menu.FlashFreq.80.build.flash_freq=80m
 esp32-evb.menu.FlashFreq.40=40MHz
 esp32-evb.menu.FlashFreq.40.build.flash_freq=40m
 
-
+esp32-evb.menu.UploadSpeed.921600=921600
+esp32-evb.menu.UploadSpeed.921600.upload.speed=921600
 esp32-evb.menu.UploadSpeed.115200=115200
 esp32-evb.menu.UploadSpeed.115200.upload.speed=115200
+esp32-evb.menu.UploadSpeed.256000.windows=256000
+esp32-evb.menu.UploadSpeed.256000.upload.speed=256000
+esp32-evb.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32-evb.menu.UploadSpeed.230400=230400
+esp32-evb.menu.UploadSpeed.230400.upload.speed=230400
+esp32-evb.menu.UploadSpeed.460800.linux=460800
+esp32-evb.menu.UploadSpeed.460800.macosx=460800
+esp32-evb.menu.UploadSpeed.460800.upload.speed=460800
+esp32-evb.menu.UploadSpeed.512000.windows=512000
+esp32-evb.menu.UploadSpeed.512000.upload.speed=512000
 
 esp32-evb.menu.PartitionScheme.default=Default
 esp32-evb.menu.PartitionScheme.default.build.partitions=default
@@ -2209,28 +18264,56 @@ esp32-evb.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
 esp32-evb.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 esp32-evb.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
 
+esp32-evb.menu.DebugLevel.none=None
+esp32-evb.menu.DebugLevel.none.build.code_debug=0
+esp32-evb.menu.DebugLevel.error=Error
+esp32-evb.menu.DebugLevel.error.build.code_debug=1
+esp32-evb.menu.DebugLevel.warn=Warn
+esp32-evb.menu.DebugLevel.warn.build.code_debug=2
+esp32-evb.menu.DebugLevel.info=Info
+esp32-evb.menu.DebugLevel.info.build.code_debug=3
+esp32-evb.menu.DebugLevel.debug=Debug
+esp32-evb.menu.DebugLevel.debug.build.code_debug=4
+esp32-evb.menu.DebugLevel.verbose=Verbose
+esp32-evb.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32-evb.menu.EraseFlash.none=Disabled
+esp32-evb.menu.EraseFlash.none.upload.erase_cmd=
+esp32-evb.menu.EraseFlash.all=Enabled
+esp32-evb.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 esp32-gateway.name=OLIMEX ESP32-GATEWAY
 
+esp32-gateway.bootloader.tool=esptool_py
+esp32-gateway.bootloader.tool.default=esptool_py
+
 esp32-gateway.upload.tool=esptool_py
+esp32-gateway.upload.tool.default=esptool_py
+esp32-gateway.upload.tool.network=esp_ota
+
 esp32-gateway.upload.maximum_size=1310720
 esp32-gateway.upload.maximum_data_size=327680
-esp32-gateway.upload.wait_for_upload_port=true
+esp32-gateway.upload.flags=
+esp32-gateway.upload.extra_flags=
 
 esp32-gateway.serial.disableDTR=true
 esp32-gateway.serial.disableRTS=true
 
+esp32-gateway.build.tarch=xtensa
+esp32-gateway.build.bootloader_addr=0x1000
+esp32-gateway.build.target=esp32
 esp32-gateway.build.mcu=esp32
 esp32-gateway.build.core=esp32
 esp32-gateway.build.variant=esp32-gateway
 esp32-gateway.build.board=ESP32_GATEWAY
 esp32-gateway.menu.Revision.RevC=Revision C or older
-esp32-gateway.menu.Revision.RevC.build.board=ESP32_GATEWAY='C'
+esp32-gateway.menu.Revision.RevC.build.board=ESP32_GATEWAY_C
 esp32-gateway.menu.Revision.RevE=Revision E
-esp32-gateway.menu.Revision.RevE.build.board=ESP32_GATEWAY='E'
-esp32-gateway.menu.Revision.RevF=Revision F
-esp32-gateway.menu.Revision.RevF.build.board=ESP32_GATEWAY='F'
+esp32-gateway.menu.Revision.RevE.build.board=ESP32_GATEWAY_E
+esp32-gateway.menu.Revision.RevF=Revision F or newer
+esp32-gateway.menu.Revision.RevF.build.board=ESP32_GATEWAY_F
 
 esp32-gateway.build.f_cpu=240000000L
 esp32-gateway.build.flash_mode=dio
@@ -2244,7 +18327,8 @@ esp32-gateway.menu.FlashFreq.80.build.flash_freq=80m
 esp32-gateway.menu.FlashFreq.40=40MHz
 esp32-gateway.menu.FlashFreq.40.build.flash_freq=40m
 
-
+esp32-gateway.menu.UploadSpeed.921600=921600
+esp32-gateway.menu.UploadSpeed.921600.upload.speed=921600
 esp32-gateway.menu.UploadSpeed.115200=115200
 esp32-gateway.menu.UploadSpeed.115200.upload.speed=115200
 
@@ -2257,175 +18341,1787 @@ esp32-gateway.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OT
 esp32-gateway.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 esp32-gateway.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
 
+esp32-gateway.menu.DebugLevel.none=None
+esp32-gateway.menu.DebugLevel.none.build.code_debug=0
+esp32-gateway.menu.DebugLevel.error=Error
+esp32-gateway.menu.DebugLevel.error.build.code_debug=1
+esp32-gateway.menu.DebugLevel.warn=Warn
+esp32-gateway.menu.DebugLevel.warn.build.code_debug=2
+esp32-gateway.menu.DebugLevel.info=Info
+esp32-gateway.menu.DebugLevel.info.build.code_debug=3
+esp32-gateway.menu.DebugLevel.debug=Debug
+esp32-gateway.menu.DebugLevel.debug.build.code_debug=4
+esp32-gateway.menu.DebugLevel.verbose=Verbose
+esp32-gateway.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32-gateway.menu.EraseFlash.none=Disabled
+esp32-gateway.menu.EraseFlash.none.upload.erase_cmd=
+esp32-gateway.menu.EraseFlash.all=Enabled
+esp32-gateway.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
-esp32-poe.name=OLIMEX ESP32-PoE
+esp32-poe.name=OLIMEX ESP32-POE
+
+esp32-poe.bootloader.tool=esptool_py
+esp32-poe.bootloader.tool.default=esptool_py
 
 esp32-poe.upload.tool=esptool_py
+esp32-poe.upload.tool.default=esptool_py
+esp32-poe.upload.tool.network=esp_ota
+
 esp32-poe.upload.maximum_size=1310720
 esp32-poe.upload.maximum_data_size=327680
-esp32-poe.upload.wait_for_upload_port=true
+esp32-poe.upload.flags=
+esp32-poe.upload.extra_flags=
 
 esp32-poe.serial.disableDTR=true
 esp32-poe.serial.disableRTS=true
 
+esp32-poe.build.tarch=xtensa
+esp32-poe.build.bootloader_addr=0x1000
+esp32-poe.build.target=esp32
 esp32-poe.build.mcu=esp32
 esp32-poe.build.core=esp32
 esp32-poe.build.variant=esp32-poe
 esp32-poe.build.board=ESP32_POE
 
 esp32-poe.build.f_cpu=240000000L
-esp32-poe.build.flash_mode=dio
 esp32-poe.build.flash_size=4MB
+esp32-poe.build.flash_freq=40m
+esp32-poe.build.flash_mode=dio
 esp32-poe.build.boot=dio
 esp32-poe.build.partitions=default
 esp32-poe.build.defines=
+esp32-poe.build.loop_core=
+esp32-poe.build.event_core=
+
+esp32-poe.menu.PSRAM.disabled=Disabled (WROOM)
+esp32-poe.menu.PSRAM.disabled.build.defines=
+esp32-poe.menu.PSRAM.disabled.build.extra_libs=
+esp32-poe.menu.PSRAM.enabled=Enabled (WROVER)
+esp32-poe.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+esp32-poe.menu.PSRAM.enabled.build.extra_libs=
+
+esp32-poe.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32-poe.menu.PartitionScheme.default.build.partitions=default
+esp32-poe.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32-poe.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32-poe.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32-poe.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32-poe.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32-poe.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32-poe.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32-poe.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32-poe.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32-poe.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32-poe.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32-poe.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32-poe.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32-poe.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32-poe.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32-poe.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32-poe.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32-poe.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32-poe.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32-poe.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32-poe.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32-poe.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32-poe.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32-poe.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32-poe.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32-poe.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32-poe.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32-poe.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32-poe.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32-poe.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32-poe.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32-poe.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32-poe.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32-poe.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32-poe.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32-poe.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32-poe.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32-poe.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32-poe.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32-poe.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32-poe.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32-poe.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32-poe.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32-poe.menu.PartitionScheme.custom=Custom
+esp32-poe.menu.PartitionScheme.custom.build.partitions=
+esp32-poe.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32-poe.menu.FlashMode.qio=QIO
+esp32-poe.menu.FlashMode.qio.build.flash_mode=dio
+esp32-poe.menu.FlashMode.qio.build.boot=qio
+esp32-poe.menu.FlashMode.dio=DIO
+esp32-poe.menu.FlashMode.dio.build.flash_mode=dio
+esp32-poe.menu.FlashMode.dio.build.boot=dio
 
 esp32-poe.menu.FlashFreq.80=80MHz
 esp32-poe.menu.FlashFreq.80.build.flash_freq=80m
 esp32-poe.menu.FlashFreq.40=40MHz
 esp32-poe.menu.FlashFreq.40.build.flash_freq=40m
 
+esp32-poe.menu.FlashSize.4M=4MB (32Mb)
+esp32-poe.menu.FlashSize.4M.build.flash_size=4MB
+esp32-poe.menu.FlashSize.16M=16MB (128Mb)
+esp32-poe.menu.FlashSize.16M.build.flash_size=16MB
 
+esp32-poe.menu.UploadSpeed.921600=921600
+esp32-poe.menu.UploadSpeed.921600.upload.speed=921600
 esp32-poe.menu.UploadSpeed.115200=115200
 esp32-poe.menu.UploadSpeed.115200.upload.speed=115200
-
-esp32-poe.menu.PartitionScheme.default=Default
-esp32-poe.menu.PartitionScheme.default.build.partitions=default
-esp32-poe.menu.PartitionScheme.no_ota=No OTA (Large APP)
-esp32-poe.menu.PartitionScheme.no_ota.build.partitions=no_ota
-esp32-poe.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-esp32-poe.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-esp32-poe.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-esp32-poe.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32-poe.menu.UploadSpeed.256000.windows=256000
+esp32-poe.menu.UploadSpeed.256000.upload.speed=256000
+esp32-poe.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32-poe.menu.UploadSpeed.230400=230400
+esp32-poe.menu.UploadSpeed.230400.upload.speed=230400
+esp32-poe.menu.UploadSpeed.460800.linux=460800
+esp32-poe.menu.UploadSpeed.460800.macosx=460800
+esp32-poe.menu.UploadSpeed.460800.upload.speed=460800
+esp32-poe.menu.UploadSpeed.512000.windows=512000
+esp32-poe.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32-poe.menu.DebugLevel.none=None
+esp32-poe.menu.DebugLevel.none.build.code_debug=0
+esp32-poe.menu.DebugLevel.error=Error
+esp32-poe.menu.DebugLevel.error.build.code_debug=1
+esp32-poe.menu.DebugLevel.warn=Warn
+esp32-poe.menu.DebugLevel.warn.build.code_debug=2
+esp32-poe.menu.DebugLevel.info=Info
+esp32-poe.menu.DebugLevel.info.build.code_debug=3
+esp32-poe.menu.DebugLevel.debug=Debug
+esp32-poe.menu.DebugLevel.debug.build.code_debug=4
+esp32-poe.menu.DebugLevel.verbose=Verbose
+esp32-poe.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32-poe.menu.EraseFlash.none=Disabled
+esp32-poe.menu.EraseFlash.none.upload.erase_cmd=
+esp32-poe.menu.EraseFlash.all=Enabled
+esp32-poe.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
 
-esp32-poe-iso.name=OLIMEX ESP32-PoE-ISO
+esp32-poe-iso.name=OLIMEX ESP32-POE-ISO
+
+esp32-poe-iso.bootloader.tool=esptool_py
+esp32-poe-iso.bootloader.tool.default=esptool_py
 
 esp32-poe-iso.upload.tool=esptool_py
+esp32-poe-iso.upload.tool.default=esptool_py
+esp32-poe-iso.upload.tool.network=esp_ota
+
 esp32-poe-iso.upload.maximum_size=1310720
 esp32-poe-iso.upload.maximum_data_size=327680
-esp32-poe-iso.upload.wait_for_upload_port=true
+esp32-poe-iso.upload.flags=
+esp32-poe-iso.upload.extra_flags=
 
 esp32-poe-iso.serial.disableDTR=true
 esp32-poe-iso.serial.disableRTS=true
 
+esp32-poe-iso.build.tarch=xtensa
+esp32-poe-iso.build.bootloader_addr=0x1000
+esp32-poe-iso.build.target=esp32
 esp32-poe-iso.build.mcu=esp32
 esp32-poe-iso.build.core=esp32
 esp32-poe-iso.build.variant=esp32-poe-iso
 esp32-poe-iso.build.board=ESP32_POE_ISO
 
 esp32-poe-iso.build.f_cpu=240000000L
-esp32-poe-iso.build.flash_mode=dio
 esp32-poe-iso.build.flash_size=4MB
+esp32-poe-iso.build.flash_freq=40m
+esp32-poe-iso.build.flash_mode=dio
 esp32-poe-iso.build.boot=dio
 esp32-poe-iso.build.partitions=default
 esp32-poe-iso.build.defines=
+esp32-poe-iso.build.loop_core=
+esp32-poe-iso.build.event_core=
+
+esp32-poe-iso.menu.PSRAM.disabled=Disabled (WROOM)
+esp32-poe-iso.menu.PSRAM.disabled.build.defines=
+esp32-poe-iso.menu.PSRAM.disabled.build.extra_libs=
+esp32-poe-iso.menu.PSRAM.enabled=Enabled (WROVER)
+esp32-poe-iso.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+esp32-poe-iso.menu.PSRAM.enabled.build.extra_libs=
+
+esp32-poe-iso.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32-poe-iso.menu.PartitionScheme.default.build.partitions=default
+esp32-poe-iso.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32-poe-iso.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32-poe-iso.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32-poe-iso.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32-poe-iso.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32-poe-iso.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32-poe-iso.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32-poe-iso.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32-poe-iso.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32-poe-iso.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32-poe-iso.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32-poe-iso.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32-poe-iso.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32-poe-iso.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32-poe-iso.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32-poe-iso.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32-poe-iso.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32-poe-iso.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32-poe-iso.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32-poe-iso.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32-poe-iso.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32-poe-iso.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32-poe-iso.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32-poe-iso.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32-poe-iso.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32-poe-iso.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32-poe-iso.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32-poe-iso.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32-poe-iso.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32-poe-iso.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32-poe-iso.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32-poe-iso.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32-poe-iso.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32-poe-iso.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32-poe-iso.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32-poe-iso.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32-poe-iso.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32-poe-iso.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32-poe-iso.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32-poe-iso.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32-poe-iso.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32-poe-iso.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32-poe-iso.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32-poe-iso.menu.PartitionScheme.custom=Custom
+esp32-poe-iso.menu.PartitionScheme.custom.build.partitions=
+esp32-poe-iso.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32-poe-iso.menu.FlashMode.qio=QIO
+esp32-poe-iso.menu.FlashMode.qio.build.flash_mode=dio
+esp32-poe-iso.menu.FlashMode.qio.build.boot=qio
+esp32-poe-iso.menu.FlashMode.dio=DIO
+esp32-poe-iso.menu.FlashMode.dio.build.flash_mode=dio
+esp32-poe-iso.menu.FlashMode.dio.build.boot=dio
 
 esp32-poe-iso.menu.FlashFreq.80=80MHz
 esp32-poe-iso.menu.FlashFreq.80.build.flash_freq=80m
 esp32-poe-iso.menu.FlashFreq.40=40MHz
 esp32-poe-iso.menu.FlashFreq.40.build.flash_freq=40m
 
+esp32-poe-iso.menu.FlashSize.4M=4MB (32Mb)
+esp32-poe-iso.menu.FlashSize.4M.build.flash_size=4MB
+esp32-poe-iso.menu.FlashSize.16M=16MB (128Mb)
+esp32-poe-iso.menu.FlashSize.16M.build.flash_size=16MB
 
+esp32-poe-iso.menu.UploadSpeed.921600=921600
+esp32-poe-iso.menu.UploadSpeed.921600.upload.speed=921600
 esp32-poe-iso.menu.UploadSpeed.115200=115200
 esp32-poe-iso.menu.UploadSpeed.115200.upload.speed=115200
+esp32-poe-iso.menu.UploadSpeed.256000.windows=256000
+esp32-poe-iso.menu.UploadSpeed.256000.upload.speed=256000
+esp32-poe-iso.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32-poe-iso.menu.UploadSpeed.230400=230400
+esp32-poe-iso.menu.UploadSpeed.230400.upload.speed=230400
+esp32-poe-iso.menu.UploadSpeed.460800.linux=460800
+esp32-poe-iso.menu.UploadSpeed.460800.macosx=460800
+esp32-poe-iso.menu.UploadSpeed.460800.upload.speed=460800
+esp32-poe-iso.menu.UploadSpeed.512000.windows=512000
+esp32-poe-iso.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32-poe-iso.menu.DebugLevel.none=None
+esp32-poe-iso.menu.DebugLevel.none.build.code_debug=0
+esp32-poe-iso.menu.DebugLevel.error=Error
+esp32-poe-iso.menu.DebugLevel.error.build.code_debug=1
+esp32-poe-iso.menu.DebugLevel.warn=Warn
+esp32-poe-iso.menu.DebugLevel.warn.build.code_debug=2
+esp32-poe-iso.menu.DebugLevel.info=Info
+esp32-poe-iso.menu.DebugLevel.info.build.code_debug=3
+esp32-poe-iso.menu.DebugLevel.debug=Debug
+esp32-poe-iso.menu.DebugLevel.debug.build.code_debug=4
+esp32-poe-iso.menu.DebugLevel.verbose=Verbose
+esp32-poe-iso.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32-poe-iso.menu.EraseFlash.none=Disabled
+esp32-poe-iso.menu.EraseFlash.none.upload.erase_cmd=
+esp32-poe-iso.menu.EraseFlash.all=Enabled
+esp32-poe-iso.menu.EraseFlash.all.upload.erase_cmd=-e
 
-esp32-poe-iso.menu.PartitionScheme.default=Default
-esp32-poe-iso.menu.PartitionScheme.default.build.partitions=default
-esp32-poe-iso.menu.PartitionScheme.no_ota=No OTA (Large APP)
-esp32-poe-iso.menu.PartitionScheme.no_ota.build.partitions=no_ota
-esp32-poe-iso.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-esp32-poe-iso.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-esp32-poe-iso.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-esp32-poe-iso.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+##############################################################
+
+esp32-devkitlipo.name=OLIMEX ESP32-DevKit-LiPo
+
+esp32-devkitlipo.bootloader.tool=esptool_py
+esp32-devkitlipo.bootloader.tool.default=esptool_py
+
+esp32-devkitlipo.upload.tool=esptool_py
+esp32-devkitlipo.upload.tool.default=esptool_py
+esp32-devkitlipo.upload.tool.network=esp_ota
+
+esp32-devkitlipo.upload.maximum_size=1310720
+esp32-devkitlipo.upload.maximum_data_size=327680
+esp32-devkitlipo.upload.flags=
+esp32-devkitlipo.upload.extra_flags=
+
+esp32-devkitlipo.serial.disableDTR=true
+esp32-devkitlipo.serial.disableRTS=true
+
+esp32-devkitlipo.build.tarch=xtensa
+esp32-devkitlipo.build.bootloader_addr=0x1000
+esp32-devkitlipo.build.target=esp32
+esp32-devkitlipo.build.mcu=esp32
+esp32-devkitlipo.build.core=esp32
+esp32-devkitlipo.build.variant=esp32-devkit-lipo
+esp32-devkitlipo.build.board=ESP32_DEVKIT_LIPO
+
+esp32-devkitlipo.build.f_cpu=240000000L
+esp32-devkitlipo.build.flash_size=4MB
+esp32-devkitlipo.build.flash_freq=40m
+esp32-devkitlipo.build.flash_mode=dio
+esp32-devkitlipo.build.boot=dio
+esp32-devkitlipo.build.partitions=default
+esp32-devkitlipo.build.defines=
+
+esp32-devkitlipo.menu.PSRAM.disabled=Disabled (WROOM)
+esp32-devkitlipo.menu.PSRAM.disabled.build.defines=
+esp32-devkitlipo.menu.PSRAM.disabled.build.extra_libs=
+esp32-devkitlipo.menu.PSRAM.enabled=Enabled (WROVER)
+esp32-devkitlipo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+esp32-devkitlipo.menu.PSRAM.enabled.build.extra_libs=
+
+esp32-devkitlipo.menu.PartitionScheme.default=Default
+esp32-devkitlipo.menu.PartitionScheme.default.build.partitions=default
+esp32-devkitlipo.menu.PartitionScheme.minimal=Minimal (2MB FLASH)
+esp32-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32-devkitlipo.menu.PartitionScheme.no_ota=No OTA (Large APP)
+esp32-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA)
+esp32-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+esp32-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32-devkitlipo.menu.PartitionScheme.fatflash=16M Fat
+esp32-devkitlipo.menu.PartitionScheme.fatflash.build.partitions=ffat
+
+esp32-devkitlipo.menu.FlashMode.qio=QIO
+esp32-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio
+esp32-devkitlipo.menu.FlashMode.qio.build.boot=qio
+esp32-devkitlipo.menu.FlashMode.dio=DIO
+esp32-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio
+esp32-devkitlipo.menu.FlashMode.dio.build.boot=dio
+
+esp32-devkitlipo.menu.FlashFreq.80=80MHz
+esp32-devkitlipo.menu.FlashFreq.80.build.flash_freq=80m
+esp32-devkitlipo.menu.FlashFreq.40=40MHz
+esp32-devkitlipo.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32-devkitlipo.menu.UploadSpeed.921600=921600
+esp32-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600
+esp32-devkitlipo.menu.UploadSpeed.115200=115200
+esp32-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200
+esp32-devkitlipo.menu.UploadSpeed.256000.windows=256000
+esp32-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000
+esp32-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32-devkitlipo.menu.UploadSpeed.230400=230400
+esp32-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400
+esp32-devkitlipo.menu.UploadSpeed.460800.linux=460800
+esp32-devkitlipo.menu.UploadSpeed.460800.macosx=460800
+esp32-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800
+esp32-devkitlipo.menu.UploadSpeed.512000.windows=512000
+esp32-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32-devkitlipo.menu.DebugLevel.none=None
+esp32-devkitlipo.menu.DebugLevel.none.build.code_debug=0
+esp32-devkitlipo.menu.DebugLevel.error=Error
+esp32-devkitlipo.menu.DebugLevel.error.build.code_debug=1
+esp32-devkitlipo.menu.DebugLevel.warn=Warn
+esp32-devkitlipo.menu.DebugLevel.warn.build.code_debug=2
+esp32-devkitlipo.menu.DebugLevel.info=Info
+esp32-devkitlipo.menu.DebugLevel.info.build.code_debug=3
+esp32-devkitlipo.menu.DebugLevel.debug=Debug
+esp32-devkitlipo.menu.DebugLevel.debug.build.code_debug=4
+esp32-devkitlipo.menu.DebugLevel.verbose=Verbose
+esp32-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32-devkitlipo.menu.EraseFlash.none=Disabled
+esp32-devkitlipo.menu.EraseFlash.none.upload.erase_cmd=
+esp32-devkitlipo.menu.EraseFlash.all=Enabled
+esp32-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32s2-devkitlipo.name=OLIMEX ESP32-S2-DevKit-Lipo
+
+esp32s2-devkitlipo.bootloader.tool=esptool_py
+esp32s2-devkitlipo.bootloader.tool.default=esptool_py
+
+esp32s2-devkitlipo.upload.tool=esptool_py
+esp32s2-devkitlipo.upload.tool.default=esptool_py
+esp32s2-devkitlipo.upload.tool.network=esp_ota
+
+esp32s2-devkitlipo.upload.maximum_size=1310720
+esp32s2-devkitlipo.upload.maximum_data_size=327680
+esp32s2-devkitlipo.upload.flags=
+esp32s2-devkitlipo.upload.extra_flags=
+esp32s2-devkitlipo.upload.use_1200bps_touch=false
+esp32s2-devkitlipo.upload.wait_for_upload_port=false
+
+esp32s2-devkitlipo.serial.disableDTR=false
+esp32s2-devkitlipo.serial.disableRTS=false
+
+esp32s2-devkitlipo.build.tarch=xtensa
+esp32s2-devkitlipo.build.bootloader_addr=0x1000
+esp32s2-devkitlipo.build.target=esp32s2
+esp32s2-devkitlipo.build.mcu=esp32s2
+esp32s2-devkitlipo.build.core=esp32
+esp32s2-devkitlipo.build.variant=esp32s2-devkit-lipo
+esp32s2-devkitlipo.build.board=ESP32S2_DEVKIT_LIPO
+
+esp32s2-devkitlipo.build.cdc_on_boot=0
+esp32s2-devkitlipo.build.msc_on_boot=0
+esp32s2-devkitlipo.build.dfu_on_boot=0
+esp32s2-devkitlipo.build.f_cpu=240000000L
+esp32s2-devkitlipo.build.flash_size=4MB
+esp32s2-devkitlipo.build.flash_freq=80m
+esp32s2-devkitlipo.build.flash_mode=dio
+esp32s2-devkitlipo.build.boot=qio
+esp32s2-devkitlipo.build.partitions=default
+esp32s2-devkitlipo.build.defines=
+
+esp32s2-devkitlipo.menu.JTAGAdapter.default=Disabled
+esp32s2-devkitlipo.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32s2-devkitlipo.menu.JTAGAdapter.external=FTDI Adapter
+esp32s2-devkitlipo.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg
+esp32s2-devkitlipo.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32s2-devkitlipo.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32s2-devkitlipo.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg
+esp32s2-devkitlipo.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32s2-devkitlipo.menu.CDCOnBoot.default=Disabled
+esp32s2-devkitlipo.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32s2-devkitlipo.menu.CDCOnBoot.cdc=Enabled
+esp32s2-devkitlipo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32s2-devkitlipo.menu.MSCOnBoot.default=Disabled
+esp32s2-devkitlipo.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32s2-devkitlipo.menu.MSCOnBoot.msc=Enabled
+esp32s2-devkitlipo.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32s2-devkitlipo.menu.DFUOnBoot.default=Disabled
+esp32s2-devkitlipo.menu.DFUOnBoot.default.build.dfu_on_boot=0
+esp32s2-devkitlipo.menu.DFUOnBoot.dfu=Enabled
+esp32s2-devkitlipo.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+esp32s2-devkitlipo.menu.UploadMode.default=UART0
+esp32s2-devkitlipo.menu.UploadMode.default.upload.use_1200bps_touch=false
+esp32s2-devkitlipo.menu.UploadMode.default.upload.wait_for_upload_port=false
+esp32s2-devkitlipo.menu.UploadMode.cdc=Internal USB
+esp32s2-devkitlipo.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+esp32s2-devkitlipo.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+esp32s2-devkitlipo.menu.PSRAM.disabled=Disabled (WROOM)
+esp32s2-devkitlipo.menu.PSRAM.disabled.build.defines=
+esp32s2-devkitlipo.menu.PSRAM.enabled=Enabled (WROVER)
+esp32s2-devkitlipo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+esp32s2-devkitlipo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s2-devkitlipo.menu.PartitionScheme.default.build.partitions=default
+esp32s2-devkitlipo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s2-devkitlipo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s2-devkitlipo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s2-devkitlipo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s2-devkitlipo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s2-devkitlipo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32s2-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32s2-devkitlipo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s2-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s2-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s2-devkitlipo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s2-devkitlipo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s2-devkitlipo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s2-devkitlipo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s2-devkitlipo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s2-devkitlipo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s2-devkitlipo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s2-devkitlipo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s2-devkitlipo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s2-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s2-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s2-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s2-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s2-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s2-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s2-devkitlipo.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32s2-devkitlipo.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s2-devkitlipo.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32s2-devkitlipo.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32s2-devkitlipo.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32s2-devkitlipo.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32s2-devkitlipo.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32s2-devkitlipo.menu.PartitionScheme.custom=Custom
+esp32s2-devkitlipo.menu.PartitionScheme.custom.build.partitions=
+esp32s2-devkitlipo.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32s2-devkitlipo.menu.CPUFreq.240=240MHz (WiFi)
+esp32s2-devkitlipo.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32s2-devkitlipo.menu.CPUFreq.160=160MHz (WiFi)
+esp32s2-devkitlipo.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32s2-devkitlipo.menu.CPUFreq.80=80MHz (WiFi)
+esp32s2-devkitlipo.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32s2-devkitlipo.menu.CPUFreq.40=40MHz
+esp32s2-devkitlipo.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32s2-devkitlipo.menu.CPUFreq.20=20MHz
+esp32s2-devkitlipo.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32s2-devkitlipo.menu.CPUFreq.10=10MHz
+esp32s2-devkitlipo.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32s2-devkitlipo.menu.FlashMode.qio=QIO
+esp32s2-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio
+esp32s2-devkitlipo.menu.FlashMode.qio.build.boot=qio
+esp32s2-devkitlipo.menu.FlashMode.dio=DIO
+esp32s2-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio
+esp32s2-devkitlipo.menu.FlashMode.dio.build.boot=dio
+esp32s2-devkitlipo.menu.FlashMode.qout=QOUT
+esp32s2-devkitlipo.menu.FlashMode.qout.build.flash_mode=dout
+esp32s2-devkitlipo.menu.FlashMode.qout.build.boot=qout
+esp32s2-devkitlipo.menu.FlashMode.dout=DOUT
+esp32s2-devkitlipo.menu.FlashMode.dout.build.flash_mode=dout
+esp32s2-devkitlipo.menu.FlashMode.dout.build.boot=dout
+
+esp32s2-devkitlipo.menu.FlashFreq.80=80MHz
+esp32s2-devkitlipo.menu.FlashFreq.80.build.flash_freq=80m
+esp32s2-devkitlipo.menu.FlashFreq.40=40MHz
+esp32s2-devkitlipo.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32s2-devkitlipo.menu.FlashSize.4M=4MB (32Mb)
+esp32s2-devkitlipo.menu.FlashSize.4M.build.flash_size=4MB
+esp32s2-devkitlipo.menu.FlashSize.8M=8MB (64Mb)
+esp32s2-devkitlipo.menu.FlashSize.8M.build.flash_size=8MB
+esp32s2-devkitlipo.menu.FlashSize.2M=2MB (16Mb)
+esp32s2-devkitlipo.menu.FlashSize.2M.build.flash_size=2MB
+esp32s2-devkitlipo.menu.FlashSize.16M=16MB (128Mb)
+esp32s2-devkitlipo.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32s2-devkitlipo.menu.UploadSpeed.921600=921600
+esp32s2-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600
+esp32s2-devkitlipo.menu.UploadSpeed.115200=115200
+esp32s2-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200
+esp32s2-devkitlipo.menu.UploadSpeed.256000.windows=256000
+esp32s2-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000
+esp32s2-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32s2-devkitlipo.menu.UploadSpeed.230400=230400
+esp32s2-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400
+esp32s2-devkitlipo.menu.UploadSpeed.460800.linux=460800
+esp32s2-devkitlipo.menu.UploadSpeed.460800.macosx=460800
+esp32s2-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800
+esp32s2-devkitlipo.menu.UploadSpeed.512000.windows=512000
+esp32s2-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32s2-devkitlipo.menu.DebugLevel.none=None
+esp32s2-devkitlipo.menu.DebugLevel.none.build.code_debug=0
+esp32s2-devkitlipo.menu.DebugLevel.error=Error
+esp32s2-devkitlipo.menu.DebugLevel.error.build.code_debug=1
+esp32s2-devkitlipo.menu.DebugLevel.warn=Warn
+esp32s2-devkitlipo.menu.DebugLevel.warn.build.code_debug=2
+esp32s2-devkitlipo.menu.DebugLevel.info=Info
+esp32s2-devkitlipo.menu.DebugLevel.info.build.code_debug=3
+esp32s2-devkitlipo.menu.DebugLevel.debug=Debug
+esp32s2-devkitlipo.menu.DebugLevel.debug.build.code_debug=4
+esp32s2-devkitlipo.menu.DebugLevel.verbose=Verbose
+esp32s2-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s2-devkitlipo.menu.EraseFlash.none=Disabled
+esp32s2-devkitlipo.menu.EraseFlash.none.upload.erase_cmd=
+esp32s2-devkitlipo.menu.EraseFlash.all=Enabled
+esp32s2-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32s2-devkitlipo-usb.name=OLIMEX ESP32-S2-DevKit-Lipo-USB
+
+esp32s2-devkitlipo-usb.bootloader.tool=esptool_py
+esp32s2-devkitlipo-usb.bootloader.tool.default=esptool_py
+
+esp32s2-devkitlipo-usb.upload.tool=esptool_py
+esp32s2-devkitlipo-usb.upload.tool.default=esptool_py
+esp32s2-devkitlipo-usb.upload.tool.network=esp_ota
+
+esp32s2-devkitlipo-usb.upload.maximum_size=1310720
+esp32s2-devkitlipo-usb.upload.maximum_data_size=327680
+esp32s2-devkitlipo-usb.upload.flags=
+esp32s2-devkitlipo-usb.upload.extra_flags=
+esp32s2-devkitlipo-usb.upload.use_1200bps_touch=false
+esp32s2-devkitlipo-usb.upload.wait_for_upload_port=false
+
+esp32s2-devkitlipo-usb.serial.disableDTR=false
+esp32s2-devkitlipo-usb.serial.disableRTS=false
+
+esp32s2-devkitlipo-usb.build.tarch=xtensa
+esp32s2-devkitlipo-usb.build.bootloader_addr=0x1000
+esp32s2-devkitlipo-usb.build.target=esp32s2
+esp32s2-devkitlipo-usb.build.mcu=esp32s2
+esp32s2-devkitlipo-usb.build.core=esp32
+esp32s2-devkitlipo-usb.build.variant=esp32s2-devkit-lipo-usb
+esp32s2-devkitlipo-usb.build.board=ESP32S2_DEVKIT_LIPO_USB
+
+esp32s2-devkitlipo-usb.build.cdc_on_boot=0
+esp32s2-devkitlipo-usb.build.msc_on_boot=0
+esp32s2-devkitlipo-usb.build.dfu_on_boot=0
+esp32s2-devkitlipo-usb.build.f_cpu=240000000L
+esp32s2-devkitlipo-usb.build.flash_size=4MB
+esp32s2-devkitlipo-usb.build.flash_freq=80m
+esp32s2-devkitlipo-usb.build.flash_mode=dio
+esp32s2-devkitlipo-usb.build.boot=qio
+esp32s2-devkitlipo-usb.build.partitions=default
+esp32s2-devkitlipo-usb.build.defines=
+
+esp32s2-devkitlipo-usb.menu.JTAGAdapter.default=Disabled
+esp32s2-devkitlipo-usb.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32s2-devkitlipo-usb.menu.JTAGAdapter.external=FTDI Adapter
+esp32s2-devkitlipo-usb.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg
+esp32s2-devkitlipo-usb.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32s2-devkitlipo-usb.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32s2-devkitlipo-usb.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg
+esp32s2-devkitlipo-usb.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32s2-devkitlipo-usb.menu.CDCOnBoot.default=Enabled
+esp32s2-devkitlipo-usb.menu.CDCOnBoot.default.build.cdc_on_boot=1
+esp32s2-devkitlipo-usb.menu.CDCOnBoot.cdc=Disabled
+esp32s2-devkitlipo-usb.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+esp32s2-devkitlipo-usb.menu.MSCOnBoot.default=Disabled
+esp32s2-devkitlipo-usb.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32s2-devkitlipo-usb.menu.MSCOnBoot.msc=Enabled
+esp32s2-devkitlipo-usb.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32s2-devkitlipo-usb.menu.DFUOnBoot.default=Enabled
+esp32s2-devkitlipo-usb.menu.DFUOnBoot.default.build.dfu_on_boot=1
+esp32s2-devkitlipo-usb.menu.DFUOnBoot.dfu=Disabled
+esp32s2-devkitlipo-usb.menu.DFUOnBoot.dfu.build.dfu_on_boot=0
+
+esp32s2-devkitlipo-usb.menu.UploadMode.default=Internal USB
+esp32s2-devkitlipo-usb.menu.UploadMode.default.upload.use_1200bps_touch=true
+esp32s2-devkitlipo-usb.menu.UploadMode.default.upload.wait_for_upload_port=true
+esp32s2-devkitlipo-usb.menu.UploadMode.UART0=UART0
+esp32s2-devkitlipo-usb.menu.UploadMode.UART0.upload.use_1200bps_touch=false
+esp32s2-devkitlipo-usb.menu.UploadMode.UART0.upload.wait_for_upload_port=false
+
+esp32s2-devkitlipo-usb.menu.PSRAM.disabled=Disabled (WROOM)
+esp32s2-devkitlipo-usb.menu.PSRAM.disabled.build.defines=
+esp32s2-devkitlipo-usb.menu.PSRAM.enabled=Enabled (WROVER)
+esp32s2-devkitlipo-usb.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+esp32s2-devkitlipo-usb.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.default.build.partitions=default
+esp32s2-devkitlipo-usb.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s2-devkitlipo-usb.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s2-devkitlipo-usb.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s2-devkitlipo-usb.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32s2-devkitlipo-usb.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s2-devkitlipo-usb.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s2-devkitlipo-usb.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s2-devkitlipo-usb.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s2-devkitlipo-usb.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s2-devkitlipo-usb.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s2-devkitlipo-usb.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s2-devkitlipo-usb.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s2-devkitlipo-usb.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s2-devkitlipo-usb.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s2-devkitlipo-usb.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s2-devkitlipo-usb.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32s2-devkitlipo-usb.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32s2-devkitlipo-usb.menu.PartitionScheme.custom=Custom
+esp32s2-devkitlipo-usb.menu.PartitionScheme.custom.build.partitions=
+esp32s2-devkitlipo-usb.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32s2-devkitlipo-usb.menu.CPUFreq.240=240MHz (WiFi)
+esp32s2-devkitlipo-usb.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32s2-devkitlipo-usb.menu.CPUFreq.160=160MHz (WiFi)
+esp32s2-devkitlipo-usb.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32s2-devkitlipo-usb.menu.CPUFreq.80=80MHz (WiFi)
+esp32s2-devkitlipo-usb.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32s2-devkitlipo-usb.menu.CPUFreq.40=40MHz
+esp32s2-devkitlipo-usb.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32s2-devkitlipo-usb.menu.CPUFreq.20=20MHz
+esp32s2-devkitlipo-usb.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32s2-devkitlipo-usb.menu.CPUFreq.10=10MHz
+esp32s2-devkitlipo-usb.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32s2-devkitlipo-usb.menu.FlashMode.qio=QIO
+esp32s2-devkitlipo-usb.menu.FlashMode.qio.build.flash_mode=dio
+esp32s2-devkitlipo-usb.menu.FlashMode.qio.build.boot=qio
+esp32s2-devkitlipo-usb.menu.FlashMode.dio=DIO
+esp32s2-devkitlipo-usb.menu.FlashMode.dio.build.flash_mode=dio
+esp32s2-devkitlipo-usb.menu.FlashMode.dio.build.boot=dio
+esp32s2-devkitlipo-usb.menu.FlashMode.qout=QOUT
+esp32s2-devkitlipo-usb.menu.FlashMode.qout.build.flash_mode=dout
+esp32s2-devkitlipo-usb.menu.FlashMode.qout.build.boot=qout
+esp32s2-devkitlipo-usb.menu.FlashMode.dout=DOUT
+esp32s2-devkitlipo-usb.menu.FlashMode.dout.build.flash_mode=dout
+esp32s2-devkitlipo-usb.menu.FlashMode.dout.build.boot=dout
+
+esp32s2-devkitlipo-usb.menu.FlashFreq.80=80MHz
+esp32s2-devkitlipo-usb.menu.FlashFreq.80.build.flash_freq=80m
+esp32s2-devkitlipo-usb.menu.FlashFreq.40=40MHz
+esp32s2-devkitlipo-usb.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32s2-devkitlipo-usb.menu.FlashSize.4M=4MB (32Mb)
+esp32s2-devkitlipo-usb.menu.FlashSize.4M.build.flash_size=4MB
+esp32s2-devkitlipo-usb.menu.FlashSize.8M=8MB (64Mb)
+esp32s2-devkitlipo-usb.menu.FlashSize.8M.build.flash_size=8MB
+esp32s2-devkitlipo-usb.menu.FlashSize.2M=2MB (16Mb)
+esp32s2-devkitlipo-usb.menu.FlashSize.2M.build.flash_size=2MB
+esp32s2-devkitlipo-usb.menu.FlashSize.16M=16MB (128Mb)
+esp32s2-devkitlipo-usb.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32s2-devkitlipo-usb.menu.UploadSpeed.921600=921600
+esp32s2-devkitlipo-usb.menu.UploadSpeed.921600.upload.speed=921600
+esp32s2-devkitlipo-usb.menu.UploadSpeed.115200=115200
+esp32s2-devkitlipo-usb.menu.UploadSpeed.115200.upload.speed=115200
+esp32s2-devkitlipo-usb.menu.UploadSpeed.256000.windows=256000
+esp32s2-devkitlipo-usb.menu.UploadSpeed.256000.upload.speed=256000
+esp32s2-devkitlipo-usb.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32s2-devkitlipo-usb.menu.UploadSpeed.230400=230400
+esp32s2-devkitlipo-usb.menu.UploadSpeed.230400.upload.speed=230400
+esp32s2-devkitlipo-usb.menu.UploadSpeed.460800.linux=460800
+esp32s2-devkitlipo-usb.menu.UploadSpeed.460800.macosx=460800
+esp32s2-devkitlipo-usb.menu.UploadSpeed.460800.upload.speed=460800
+esp32s2-devkitlipo-usb.menu.UploadSpeed.512000.windows=512000
+esp32s2-devkitlipo-usb.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32s2-devkitlipo-usb.menu.DebugLevel.none=None
+esp32s2-devkitlipo-usb.menu.DebugLevel.none.build.code_debug=0
+esp32s2-devkitlipo-usb.menu.DebugLevel.error=Error
+esp32s2-devkitlipo-usb.menu.DebugLevel.error.build.code_debug=1
+esp32s2-devkitlipo-usb.menu.DebugLevel.warn=Warn
+esp32s2-devkitlipo-usb.menu.DebugLevel.warn.build.code_debug=2
+esp32s2-devkitlipo-usb.menu.DebugLevel.info=Info
+esp32s2-devkitlipo-usb.menu.DebugLevel.info.build.code_debug=3
+esp32s2-devkitlipo-usb.menu.DebugLevel.debug=Debug
+esp32s2-devkitlipo-usb.menu.DebugLevel.debug.build.code_debug=4
+esp32s2-devkitlipo-usb.menu.DebugLevel.verbose=Verbose
+esp32s2-devkitlipo-usb.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s2-devkitlipo-usb.menu.EraseFlash.none=Disabled
+esp32s2-devkitlipo-usb.menu.EraseFlash.none.upload.erase_cmd=
+esp32s2-devkitlipo-usb.menu.EraseFlash.all=Enabled
+esp32s2-devkitlipo-usb.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32s3-devkitlipo.name=OLIMEX ESP32-S3-DevKit-Lipo
+
+esp32s3-devkitlipo.bootloader.tool=esptool_py
+esp32s3-devkitlipo.bootloader.tool.default=esptool_py
+
+esp32s3-devkitlipo.upload.tool=esptool_py
+esp32s3-devkitlipo.upload.tool.default=esptool_py
+esp32s3-devkitlipo.upload.tool.network=esp_ota
+
+esp32s3-devkitlipo.upload.maximum_size=1310720
+esp32s3-devkitlipo.upload.maximum_data_size=327680
+esp32s3-devkitlipo.upload.flags=
+esp32s3-devkitlipo.upload.extra_flags=
+esp32s3-devkitlipo.upload.use_1200bps_touch=false
+esp32s3-devkitlipo.upload.wait_for_upload_port=false
+
+esp32s3-devkitlipo.serial.disableDTR=false
+esp32s3-devkitlipo.serial.disableRTS=false
+
+esp32s3-devkitlipo.build.tarch=xtensa
+esp32s3-devkitlipo.build.bootloader_addr=0x0
+esp32s3-devkitlipo.build.target=esp32s3
+esp32s3-devkitlipo.build.mcu=esp32s3
+esp32s3-devkitlipo.build.core=esp32
+esp32s3-devkitlipo.build.variant=esp32s3-devkit-lipo
+esp32s3-devkitlipo.build.board=ESP32S3_DEVKIT_LIPO
+
+esp32s3-devkitlipo.build.usb_mode=1
+esp32s3-devkitlipo.build.cdc_on_boot=0
+esp32s3-devkitlipo.build.msc_on_boot=0
+esp32s3-devkitlipo.build.dfu_on_boot=0
+esp32s3-devkitlipo.build.f_cpu=240000000L
+esp32s3-devkitlipo.build.flash_size=4MB
+esp32s3-devkitlipo.build.flash_freq=80m
+esp32s3-devkitlipo.build.flash_mode=dio
+esp32s3-devkitlipo.build.boot=qio
+esp32s3-devkitlipo.build.boot_freq=80m
+esp32s3-devkitlipo.build.partitions=default
+esp32s3-devkitlipo.build.defines=
+esp32s3-devkitlipo.build.loop_core=
+esp32s3-devkitlipo.build.event_core=
+esp32s3-devkitlipo.build.psram_type=qspi
+esp32s3-devkitlipo.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+esp32s3-devkitlipo.menu.JTAGAdapter.default=Disabled
+esp32s3-devkitlipo.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32s3-devkitlipo.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32s3-devkitlipo.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+esp32s3-devkitlipo.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32s3-devkitlipo.menu.JTAGAdapter.external=FTDI Adapter
+esp32s3-devkitlipo.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+esp32s3-devkitlipo.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32s3-devkitlipo.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32s3-devkitlipo.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+esp32s3-devkitlipo.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32s3-devkitlipo.menu.PSRAM.disabled=Disabled
+esp32s3-devkitlipo.menu.PSRAM.disabled.build.defines=
+esp32s3-devkitlipo.menu.PSRAM.disabled.build.psram_type=qspi
+esp32s3-devkitlipo.menu.PSRAM.enabled=QSPI PSRAM
+esp32s3-devkitlipo.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+esp32s3-devkitlipo.menu.PSRAM.enabled.build.psram_type=qspi
+esp32s3-devkitlipo.menu.PSRAM.opi=OPI PSRAM
+esp32s3-devkitlipo.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+esp32s3-devkitlipo.menu.PSRAM.opi.build.psram_type=opi
+
+esp32s3-devkitlipo.menu.FlashMode.qio=QIO 80MHz
+esp32s3-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio
+esp32s3-devkitlipo.menu.FlashMode.qio.build.boot=qio
+esp32s3-devkitlipo.menu.FlashMode.qio.build.boot_freq=80m
+esp32s3-devkitlipo.menu.FlashMode.qio.build.flash_freq=80m
+esp32s3-devkitlipo.menu.FlashMode.qio120=QIO 120MHz
+esp32s3-devkitlipo.menu.FlashMode.qio120.build.flash_mode=dio
+esp32s3-devkitlipo.menu.FlashMode.qio120.build.boot=qio
+esp32s3-devkitlipo.menu.FlashMode.qio120.build.boot_freq=120m
+esp32s3-devkitlipo.menu.FlashMode.qio120.build.flash_freq=80m
+esp32s3-devkitlipo.menu.FlashMode.dio=DIO 80MHz
+esp32s3-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio
+esp32s3-devkitlipo.menu.FlashMode.dio.build.boot=dio
+esp32s3-devkitlipo.menu.FlashMode.dio.build.boot_freq=80m
+esp32s3-devkitlipo.menu.FlashMode.dio.build.flash_freq=80m
+esp32s3-devkitlipo.menu.FlashMode.opi=OPI 80MHz
+esp32s3-devkitlipo.menu.FlashMode.opi.build.flash_mode=dout
+esp32s3-devkitlipo.menu.FlashMode.opi.build.boot=opi
+esp32s3-devkitlipo.menu.FlashMode.opi.build.boot_freq=80m
+esp32s3-devkitlipo.menu.FlashMode.opi.build.flash_freq=80m
+
+esp32s3-devkitlipo.menu.FlashSize.4M=4MB (32Mb)
+esp32s3-devkitlipo.menu.FlashSize.4M.build.flash_size=4MB
+esp32s3-devkitlipo.menu.FlashSize.8M=8MB (64Mb)
+esp32s3-devkitlipo.menu.FlashSize.8M.build.flash_size=8MB
+esp32s3-devkitlipo.menu.FlashSize.16M=16MB (128Mb)
+esp32s3-devkitlipo.menu.FlashSize.16M.build.flash_size=16MB
+esp32s3-devkitlipo.menu.FlashSize.32M=32MB (256Mb)
+esp32s3-devkitlipo.menu.FlashSize.32M.build.flash_size=32MB
+
+esp32s3-devkitlipo.menu.LoopCore.1=Core 1
+esp32s3-devkitlipo.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32s3-devkitlipo.menu.LoopCore.0=Core 0
+esp32s3-devkitlipo.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+esp32s3-devkitlipo.menu.EventsCore.1=Core 1
+esp32s3-devkitlipo.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+esp32s3-devkitlipo.menu.EventsCore.0=Core 0
+esp32s3-devkitlipo.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+esp32s3-devkitlipo.menu.USBMode.hwcdc=Hardware CDC and JTAG
+esp32s3-devkitlipo.menu.USBMode.hwcdc.build.usb_mode=1
+esp32s3-devkitlipo.menu.USBMode.default=USB-OTG (TinyUSB)
+esp32s3-devkitlipo.menu.USBMode.default.build.usb_mode=0
+
+esp32s3-devkitlipo.menu.CDCOnBoot.default=Disabled
+esp32s3-devkitlipo.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32s3-devkitlipo.menu.CDCOnBoot.cdc=Enabled
+esp32s3-devkitlipo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32s3-devkitlipo.menu.MSCOnBoot.default=Disabled
+esp32s3-devkitlipo.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32s3-devkitlipo.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+esp32s3-devkitlipo.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32s3-devkitlipo.menu.DFUOnBoot.default=Disabled
+esp32s3-devkitlipo.menu.DFUOnBoot.default.build.dfu_on_boot=0
+esp32s3-devkitlipo.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+esp32s3-devkitlipo.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+esp32s3-devkitlipo.menu.UploadMode.default=UART0 / Hardware CDC
+esp32s3-devkitlipo.menu.UploadMode.default.upload.use_1200bps_touch=false
+esp32s3-devkitlipo.menu.UploadMode.default.upload.wait_for_upload_port=false
+esp32s3-devkitlipo.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+esp32s3-devkitlipo.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+esp32s3-devkitlipo.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+esp32s3-devkitlipo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32s3-devkitlipo.menu.PartitionScheme.default.build.partitions=default
+esp32s3-devkitlipo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32s3-devkitlipo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32s3-devkitlipo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s3-devkitlipo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s3-devkitlipo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s3-devkitlipo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32s3-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32s3-devkitlipo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32s3-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32s3-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32s3-devkitlipo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32s3-devkitlipo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32s3-devkitlipo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32s3-devkitlipo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32s3-devkitlipo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32s3-devkitlipo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32s3-devkitlipo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32s3-devkitlipo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32s3-devkitlipo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32s3-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32s3-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32s3-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32s3-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32s3-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32s3-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32s3-devkitlipo.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32s3-devkitlipo.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32s3-devkitlipo.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32s3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32s3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32s3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32s3-devkitlipo.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32s3-devkitlipo.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32s3-devkitlipo.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32s3-devkitlipo.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32s3-devkitlipo.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+esp32s3-devkitlipo.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+esp32s3-devkitlipo.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+esp32s3-devkitlipo.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+esp32s3-devkitlipo.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+esp32s3-devkitlipo.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+esp32s3-devkitlipo.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+esp32s3-devkitlipo.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+esp32s3-devkitlipo.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+esp32s3-devkitlipo.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+esp32s3-devkitlipo.menu.PartitionScheme.custom=Custom
+esp32s3-devkitlipo.menu.PartitionScheme.custom.build.partitions=
+esp32s3-devkitlipo.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32s3-devkitlipo.menu.CPUFreq.240=240MHz (WiFi)
+esp32s3-devkitlipo.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32s3-devkitlipo.menu.CPUFreq.160=160MHz (WiFi)
+esp32s3-devkitlipo.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32s3-devkitlipo.menu.CPUFreq.80=80MHz (WiFi)
+esp32s3-devkitlipo.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32s3-devkitlipo.menu.CPUFreq.40=40MHz
+esp32s3-devkitlipo.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32s3-devkitlipo.menu.CPUFreq.20=20MHz
+esp32s3-devkitlipo.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32s3-devkitlipo.menu.CPUFreq.10=10MHz
+esp32s3-devkitlipo.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32s3-devkitlipo.menu.UploadSpeed.921600=921600
+esp32s3-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600
+esp32s3-devkitlipo.menu.UploadSpeed.115200=115200
+esp32s3-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200
+esp32s3-devkitlipo.menu.UploadSpeed.256000.windows=256000
+esp32s3-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000
+esp32s3-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32s3-devkitlipo.menu.UploadSpeed.230400=230400
+esp32s3-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400
+esp32s3-devkitlipo.menu.UploadSpeed.460800.linux=460800
+esp32s3-devkitlipo.menu.UploadSpeed.460800.macosx=460800
+esp32s3-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800
+esp32s3-devkitlipo.menu.UploadSpeed.512000.windows=512000
+esp32s3-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32s3-devkitlipo.menu.DebugLevel.none=None
+esp32s3-devkitlipo.menu.DebugLevel.none.build.code_debug=0
+esp32s3-devkitlipo.menu.DebugLevel.error=Error
+esp32s3-devkitlipo.menu.DebugLevel.error.build.code_debug=1
+esp32s3-devkitlipo.menu.DebugLevel.warn=Warn
+esp32s3-devkitlipo.menu.DebugLevel.warn.build.code_debug=2
+esp32s3-devkitlipo.menu.DebugLevel.info=Info
+esp32s3-devkitlipo.menu.DebugLevel.info.build.code_debug=3
+esp32s3-devkitlipo.menu.DebugLevel.debug=Debug
+esp32s3-devkitlipo.menu.DebugLevel.debug.build.code_debug=4
+esp32s3-devkitlipo.menu.DebugLevel.verbose=Verbose
+esp32s3-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s3-devkitlipo.menu.EraseFlash.none=Disabled
+esp32s3-devkitlipo.menu.EraseFlash.none.upload.erase_cmd=
+esp32s3-devkitlipo.menu.EraseFlash.all=Enabled
+esp32s3-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32c3-devkitlipo.name=OLIMEX ESP32-C3-DevKit-Lipo
+
+esp32c3-devkitlipo.bootloader.tool=esptool_py
+esp32c3-devkitlipo.bootloader.tool.default=esptool_py
+
+esp32c3-devkitlipo.upload.tool=esptool_py
+esp32c3-devkitlipo.upload.tool.default=esptool_py
+esp32c3-devkitlipo.upload.tool.network=esp_ota
+
+esp32c3-devkitlipo.upload.maximum_size=1310720
+esp32c3-devkitlipo.upload.maximum_data_size=327680
+esp32c3-devkitlipo.upload.flags=
+esp32c3-devkitlipo.upload.extra_flags=
+esp32c3-devkitlipo.upload.use_1200bps_touch=false
+esp32c3-devkitlipo.upload.wait_for_upload_port=false
+
+esp32c3-devkitlipo.serial.disableDTR=false
+esp32c3-devkitlipo.serial.disableRTS=false
+
+esp32c3-devkitlipo.build.tarch=riscv32
+esp32c3-devkitlipo.build.target=esp
+esp32c3-devkitlipo.build.mcu=esp32c3
+esp32c3-devkitlipo.build.core=esp32
+esp32c3-devkitlipo.build.variant=esp32c3-devkit-lipo
+esp32c3-devkitlipo.build.board=ESP32C3_DEVKIT_LIPO
+esp32c3-devkitlipo.build.bootloader_addr=0x0
+
+esp32c3-devkitlipo.build.cdc_on_boot=0
+esp32c3-devkitlipo.build.f_cpu=160000000L
+esp32c3-devkitlipo.build.flash_size=4MB
+esp32c3-devkitlipo.build.flash_freq=80m
+esp32c3-devkitlipo.build.flash_mode=qio
+esp32c3-devkitlipo.build.boot=qio
+esp32c3-devkitlipo.build.partitions=default
+esp32c3-devkitlipo.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32c3-devkitlipo.menu.JTAGAdapter.default=Disabled
+esp32c3-devkitlipo.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32c3-devkitlipo.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32c3-devkitlipo.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg
+esp32c3-devkitlipo.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32c3-devkitlipo.menu.JTAGAdapter.external=FTDI Adapter
+esp32c3-devkitlipo.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg
+esp32c3-devkitlipo.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32c3-devkitlipo.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32c3-devkitlipo.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg
+esp32c3-devkitlipo.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32c3-devkitlipo.menu.CDCOnBoot.default=Disabled
+esp32c3-devkitlipo.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32c3-devkitlipo.menu.CDCOnBoot.cdc=Enabled
+esp32c3-devkitlipo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32c3-devkitlipo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32c3-devkitlipo.menu.PartitionScheme.default.build.partitions=default
+esp32c3-devkitlipo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32c3-devkitlipo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32c3-devkitlipo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32c3-devkitlipo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32c3-devkitlipo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32c3-devkitlipo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32c3-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32c3-devkitlipo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32c3-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32c3-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32c3-devkitlipo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32c3-devkitlipo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32c3-devkitlipo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32c3-devkitlipo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32c3-devkitlipo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32c3-devkitlipo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32c3-devkitlipo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32c3-devkitlipo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32c3-devkitlipo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32c3-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32c3-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32c3-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32c3-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32c3-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32c3-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32c3-devkitlipo.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32c3-devkitlipo.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32c3-devkitlipo.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32c3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32c3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32c3-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32c3-devkitlipo.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32c3-devkitlipo.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32c3-devkitlipo.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32c3-devkitlipo.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32c3-devkitlipo.menu.PartitionScheme.custom=Custom
+esp32c3-devkitlipo.menu.PartitionScheme.custom.build.partitions=
+esp32c3-devkitlipo.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32c3-devkitlipo.menu.CPUFreq.160=160MHz (WiFi)
+esp32c3-devkitlipo.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32c3-devkitlipo.menu.CPUFreq.80=80MHz (WiFi)
+esp32c3-devkitlipo.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32c3-devkitlipo.menu.CPUFreq.40=40MHz
+esp32c3-devkitlipo.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32c3-devkitlipo.menu.CPUFreq.20=20MHz
+esp32c3-devkitlipo.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32c3-devkitlipo.menu.CPUFreq.10=10MHz
+esp32c3-devkitlipo.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32c3-devkitlipo.menu.FlashMode.qio=QIO
+esp32c3-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio
+esp32c3-devkitlipo.menu.FlashMode.qio.build.boot=qio
+esp32c3-devkitlipo.menu.FlashMode.dio=DIO
+esp32c3-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio
+esp32c3-devkitlipo.menu.FlashMode.dio.build.boot=dio
+esp32c3-devkitlipo.menu.FlashMode.qout=QOUT
+esp32c3-devkitlipo.menu.FlashMode.qout.build.flash_mode=dout
+esp32c3-devkitlipo.menu.FlashMode.qout.build.boot=qout
+esp32c3-devkitlipo.menu.FlashMode.dout=DOUT
+esp32c3-devkitlipo.menu.FlashMode.dout.build.flash_mode=dout
+esp32c3-devkitlipo.menu.FlashMode.dout.build.boot=dout
+
+esp32c3-devkitlipo.menu.FlashFreq.80=80MHz
+esp32c3-devkitlipo.menu.FlashFreq.80.build.flash_freq=80m
+esp32c3-devkitlipo.menu.FlashFreq.40=40MHz
+esp32c3-devkitlipo.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32c3-devkitlipo.menu.FlashSize.4M=4MB (32Mb)
+esp32c3-devkitlipo.menu.FlashSize.4M.build.flash_size=4MB
+esp32c3-devkitlipo.menu.FlashSize.8M=8MB (64Mb)
+esp32c3-devkitlipo.menu.FlashSize.8M.build.flash_size=8MB
+esp32c3-devkitlipo.menu.FlashSize.2M=2MB (16Mb)
+esp32c3-devkitlipo.menu.FlashSize.2M.build.flash_size=2MB
+esp32c3-devkitlipo.menu.FlashSize.16M=16MB (128Mb)
+esp32c3-devkitlipo.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32c3-devkitlipo.menu.UploadSpeed.921600=921600
+esp32c3-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600
+esp32c3-devkitlipo.menu.UploadSpeed.115200=115200
+esp32c3-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200
+esp32c3-devkitlipo.menu.UploadSpeed.256000.windows=256000
+esp32c3-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000
+esp32c3-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32c3-devkitlipo.menu.UploadSpeed.230400=230400
+esp32c3-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400
+esp32c3-devkitlipo.menu.UploadSpeed.460800.linux=460800
+esp32c3-devkitlipo.menu.UploadSpeed.460800.macosx=460800
+esp32c3-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800
+esp32c3-devkitlipo.menu.UploadSpeed.512000.windows=512000
+esp32c3-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32c3-devkitlipo.menu.DebugLevel.none=None
+esp32c3-devkitlipo.menu.DebugLevel.none.build.code_debug=0
+esp32c3-devkitlipo.menu.DebugLevel.error=Error
+esp32c3-devkitlipo.menu.DebugLevel.error.build.code_debug=1
+esp32c3-devkitlipo.menu.DebugLevel.warn=Warn
+esp32c3-devkitlipo.menu.DebugLevel.warn.build.code_debug=2
+esp32c3-devkitlipo.menu.DebugLevel.info=Info
+esp32c3-devkitlipo.menu.DebugLevel.info.build.code_debug=3
+esp32c3-devkitlipo.menu.DebugLevel.debug=Debug
+esp32c3-devkitlipo.menu.DebugLevel.debug.build.code_debug=4
+esp32c3-devkitlipo.menu.DebugLevel.verbose=Verbose
+esp32c3-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32c3-devkitlipo.menu.EraseFlash.none=Disabled
+esp32c3-devkitlipo.menu.EraseFlash.none.upload.erase_cmd=
+esp32c3-devkitlipo.menu.EraseFlash.all=Enabled
+esp32c3-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32c6-evb.name=OLIMEX ESP32-C6-EVB
+
+esp32c6-evb.bootloader.tool=esptool_py
+esp32c6-evb.bootloader.tool.default=esptool_py
+
+esp32c6-evb.upload.tool=esptool_py
+esp32c6-evb.upload.tool.default=esptool_py
+esp32c6-evb.upload.tool.network=esp_ota
+
+esp32c6-evb.upload.maximum_size=1310720
+esp32c6-evb.upload.maximum_data_size=327680
+esp32c6-evb.upload.flags=
+esp32c6-evb.upload.extra_flags=
+esp32c6-evb.upload.use_1200bps_touch=false
+esp32c6-evb.upload.wait_for_upload_port=false
+
+esp32c6-evb.serial.disableDTR=false
+esp32c6-evb.serial.disableRTS=false
+
+esp32c6-evb.build.tarch=riscv32
+esp32c6-evb.build.target=esp
+esp32c6-evb.build.mcu=esp32c6
+esp32c6-evb.build.core=esp32
+esp32c6-evb.build.variant=esp32c6-evb
+esp32c6-evb.build.board=ESP32C6_EVB
+esp32c6-evb.build.bootloader_addr=0x0
+
+esp32c6-evb.build.cdc_on_boot=0
+esp32c6-evb.build.f_cpu=160000000L
+esp32c6-evb.build.flash_size=4MB
+esp32c6-evb.build.flash_freq=80m
+esp32c6-evb.build.flash_mode=qio
+esp32c6-evb.build.boot=qio
+esp32c6-evb.build.partitions=default
+esp32c6-evb.build.defines=
+
+## IDE 2.0 Seems to not update the value
+esp32c6-evb.menu.JTAGAdapter.default=Disabled
+esp32c6-evb.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32c6-evb.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32c6-evb.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+esp32c6-evb.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32c6-evb.menu.JTAGAdapter.external=FTDI Adapter
+esp32c6-evb.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+esp32c6-evb.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32c6-evb.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32c6-evb.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+esp32c6-evb.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32c6-evb.menu.CDCOnBoot.default=Disabled
+esp32c6-evb.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32c6-evb.menu.CDCOnBoot.cdc=Enabled
+esp32c6-evb.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32c6-evb.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32c6-evb.menu.PartitionScheme.default.build.partitions=default
+esp32c6-evb.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32c6-evb.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32c6-evb.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32c6-evb.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32c6-evb.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32c6-evb.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32c6-evb.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32c6-evb.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32c6-evb.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32c6-evb.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32c6-evb.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32c6-evb.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32c6-evb.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32c6-evb.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32c6-evb.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32c6-evb.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32c6-evb.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32c6-evb.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32c6-evb.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32c6-evb.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32c6-evb.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32c6-evb.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32c6-evb.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32c6-evb.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32c6-evb.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32c6-evb.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32c6-evb.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32c6-evb.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32c6-evb.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32c6-evb.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32c6-evb.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32c6-evb.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32c6-evb.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32c6-evb.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32c6-evb.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32c6-evb.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32c6-evb.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32c6-evb.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32c6-evb.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32c6-evb.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32c6-evb.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+esp32c6-evb.menu.PartitionScheme.zigbee.build.partitions=zigbee
+esp32c6-evb.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+esp32c6-evb.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32c6-evb.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32c6-evb.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32c6-evb.menu.PartitionScheme.custom=Custom
+esp32c6-evb.menu.PartitionScheme.custom.build.partitions=
+esp32c6-evb.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32c6-evb.menu.CPUFreq.160=160MHz (WiFi)
+esp32c6-evb.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32c6-evb.menu.CPUFreq.80=80MHz (WiFi)
+esp32c6-evb.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32c6-evb.menu.CPUFreq.40=40MHz
+esp32c6-evb.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32c6-evb.menu.CPUFreq.20=20MHz
+esp32c6-evb.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32c6-evb.menu.CPUFreq.10=10MHz
+esp32c6-evb.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32c6-evb.menu.FlashMode.qio=QIO
+esp32c6-evb.menu.FlashMode.qio.build.flash_mode=dio
+esp32c6-evb.menu.FlashMode.qio.build.boot=qio
+esp32c6-evb.menu.FlashMode.dio=DIO
+esp32c6-evb.menu.FlashMode.dio.build.flash_mode=dio
+esp32c6-evb.menu.FlashMode.dio.build.boot=dio
+
+esp32c6-evb.menu.FlashFreq.80=80MHz
+esp32c6-evb.menu.FlashFreq.80.build.flash_freq=80m
+esp32c6-evb.menu.FlashFreq.40=40MHz
+esp32c6-evb.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32c6-evb.menu.FlashSize.4M=4MB (32Mb)
+esp32c6-evb.menu.FlashSize.4M.build.flash_size=4MB
+esp32c6-evb.menu.FlashSize.8M=8MB (64Mb)
+esp32c6-evb.menu.FlashSize.8M.build.flash_size=8MB
+esp32c6-evb.menu.FlashSize.2M=2MB (16Mb)
+esp32c6-evb.menu.FlashSize.2M.build.flash_size=2MB
+esp32c6-evb.menu.FlashSize.16M=16MB (128Mb)
+esp32c6-evb.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32c6-evb.menu.UploadSpeed.921600=921600
+esp32c6-evb.menu.UploadSpeed.921600.upload.speed=921600
+esp32c6-evb.menu.UploadSpeed.115200=115200
+esp32c6-evb.menu.UploadSpeed.115200.upload.speed=115200
+esp32c6-evb.menu.UploadSpeed.256000.windows=256000
+esp32c6-evb.menu.UploadSpeed.256000.upload.speed=256000
+esp32c6-evb.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32c6-evb.menu.UploadSpeed.230400=230400
+esp32c6-evb.menu.UploadSpeed.230400.upload.speed=230400
+esp32c6-evb.menu.UploadSpeed.460800.linux=460800
+esp32c6-evb.menu.UploadSpeed.460800.macosx=460800
+esp32c6-evb.menu.UploadSpeed.460800.upload.speed=460800
+esp32c6-evb.menu.UploadSpeed.512000.windows=512000
+esp32c6-evb.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32c6-evb.menu.DebugLevel.none=None
+esp32c6-evb.menu.DebugLevel.none.build.code_debug=0
+esp32c6-evb.menu.DebugLevel.error=Error
+esp32c6-evb.menu.DebugLevel.error.build.code_debug=1
+esp32c6-evb.menu.DebugLevel.warn=Warn
+esp32c6-evb.menu.DebugLevel.warn.build.code_debug=2
+esp32c6-evb.menu.DebugLevel.info=Info
+esp32c6-evb.menu.DebugLevel.info.build.code_debug=3
+esp32c6-evb.menu.DebugLevel.debug=Debug
+esp32c6-evb.menu.DebugLevel.debug.build.code_debug=4
+esp32c6-evb.menu.DebugLevel.verbose=Verbose
+esp32c6-evb.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32c6-evb.menu.EraseFlash.none=Disabled
+esp32c6-evb.menu.EraseFlash.none.upload.erase_cmd=
+esp32c6-evb.menu.EraseFlash.all=Enabled
+esp32c6-evb.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32c6-evb.menu.ZigbeeMode.default=Disabled
+esp32c6-evb.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32c6-evb.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32c6-evb.menu.ZigbeeMode.ed=Zigbee ED (end device)
+esp32c6-evb.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+esp32c6-evb.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+esp32c6-evb.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32c6-evb.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32c6-evb.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+esp32h2-devkitlipo.name=OLIMEX ESP32-H2-DevKit-LiPo
+
+esp32h2-devkitlipo.bootloader.tool=esptool_py
+esp32h2-devkitlipo.bootloader.tool.default=esptool_py
+
+esp32h2-devkitlipo.upload.tool=esptool_py
+esp32h2-devkitlipo.upload.tool.default=esptool_py
+esp32h2-devkitlipo.upload.tool.network=esp_ota
+
+esp32h2-devkitlipo.upload.maximum_size=1310720
+esp32h2-devkitlipo.upload.maximum_data_size=327680
+esp32h2-devkitlipo.upload.flags=
+esp32h2-devkitlipo.upload.extra_flags=
+esp32h2-devkitlipo.upload.use_1200bps_touch=false
+esp32h2-devkitlipo.upload.wait_for_upload_port=false
+
+esp32h2-devkitlipo.serial.disableDTR=false
+esp32h2-devkitlipo.serial.disableRTS=false
+
+esp32h2-devkitlipo.build.tarch=riscv32
+esp32h2-devkitlipo.build.target=esp
+esp32h2-devkitlipo.build.mcu=esp32h2
+esp32h2-devkitlipo.build.core=esp32
+esp32h2-devkitlipo.build.variant=esp32h2-devkit-lipo
+esp32h2-devkitlipo.build.board=ESP32H2_DEVKIT_LIPO
+esp32h2-devkitlipo.build.bootloader_addr=0x0
+
+esp32h2-devkitlipo.build.cdc_on_boot=0
+esp32h2-devkitlipo.build.f_cpu=96000000L
+esp32h2-devkitlipo.build.flash_size=4MB
+esp32h2-devkitlipo.build.flash_freq=64m
+esp32h2-devkitlipo.build.img_freq=48m
+esp32h2-devkitlipo.build.flash_mode=qio
+esp32h2-devkitlipo.build.boot=qio
+esp32h2-devkitlipo.build.partitions=default
+esp32h2-devkitlipo.build.defines=
+
+esp32h2-devkitlipo.menu.JTAGAdapter.default=Disabled
+esp32h2-devkitlipo.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32h2-devkitlipo.menu.JTAGAdapter.builtin=Integrated USB JTAG
+esp32h2-devkitlipo.menu.JTAGAdapter.builtin.build.openocdscript=esp32h2-builtin.cfg
+esp32h2-devkitlipo.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+esp32h2-devkitlipo.menu.JTAGAdapter.external=FTDI Adapter
+esp32h2-devkitlipo.menu.JTAGAdapter.external.build.openocdscript=esp32h2-ftdi.cfg
+esp32h2-devkitlipo.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32h2-devkitlipo.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32h2-devkitlipo.menu.JTAGAdapter.bridge.build.openocdscript=esp32h2-bridge.cfg
+esp32h2-devkitlipo.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32h2-devkitlipo.menu.CDCOnBoot.default=Disabled
+esp32h2-devkitlipo.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32h2-devkitlipo.menu.CDCOnBoot.cdc=Enabled
+esp32h2-devkitlipo.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32h2-devkitlipo.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32h2-devkitlipo.menu.PartitionScheme.default.build.partitions=default
+esp32h2-devkitlipo.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32h2-devkitlipo.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32h2-devkitlipo.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32h2-devkitlipo.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32h2-devkitlipo.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32h2-devkitlipo.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32h2-devkitlipo.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32h2-devkitlipo.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32h2-devkitlipo.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32h2-devkitlipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32h2-devkitlipo.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32h2-devkitlipo.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32h2-devkitlipo.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32h2-devkitlipo.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32h2-devkitlipo.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32h2-devkitlipo.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32h2-devkitlipo.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32h2-devkitlipo.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32h2-devkitlipo.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32h2-devkitlipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32h2-devkitlipo.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32h2-devkitlipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32h2-devkitlipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32h2-devkitlipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32h2-devkitlipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32h2-devkitlipo.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32h2-devkitlipo.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32h2-devkitlipo.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32h2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32h2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32h2-devkitlipo.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker=RainMaker 4MB
+#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+#esp32h2-devkitlipo.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32h2-devkitlipo.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+esp32h2-devkitlipo.menu.PartitionScheme.zigbee.build.partitions=zigbee
+esp32h2-devkitlipo.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+esp32h2-devkitlipo.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32h2-devkitlipo.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32h2-devkitlipo.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32h2-devkitlipo.menu.PartitionScheme.custom=Custom
+esp32h2-devkitlipo.menu.PartitionScheme.custom.build.partitions=
+esp32h2-devkitlipo.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32h2-devkitlipo.menu.FlashMode.qio=QIO
+esp32h2-devkitlipo.menu.FlashMode.qio.build.flash_mode=dio
+esp32h2-devkitlipo.menu.FlashMode.qio.build.boot=qio
+esp32h2-devkitlipo.menu.FlashMode.dio=DIO
+esp32h2-devkitlipo.menu.FlashMode.dio.build.flash_mode=dio
+esp32h2-devkitlipo.menu.FlashMode.dio.build.boot=dio
+
+esp32h2-devkitlipo.menu.FlashFreq.64=64MHz
+esp32h2-devkitlipo.menu.FlashFreq.64.build.flash_freq=64m
+esp32h2-devkitlipo.menu.FlashFreq.64.build.img_freq=48m
+#esp32h-devkitlipo2.menu.FlashFreq.32=32MHz
+#esp32h-devkitlipo2.menu.FlashFreq.32.build.flash_freq=32m
+#esp32h-devkitlipo2.menu.FlashFreq.32.build.img_freq=24m
+esp32h2-devkitlipo.menu.FlashFreq.16=16MHz
+esp32h2-devkitlipo.menu.FlashFreq.16.build.flash_freq=16m
+esp32h2-devkitlipo.menu.FlashFreq.16.build.img_freq=12m
+
+esp32h2-devkitlipo.menu.FlashSize.4M=4MB (32Mb)
+esp32h2-devkitlipo.menu.FlashSize.4M.build.flash_size=4MB
+esp32h2-devkitlipo.menu.FlashSize.8M=8MB (64Mb)
+esp32h2-devkitlipo.menu.FlashSize.8M.build.flash_size=8MB
+esp32h2-devkitlipo.menu.FlashSize.2M=2MB (16Mb)
+esp32h2-devkitlipo.menu.FlashSize.2M.build.flash_size=2MB
+esp32h2-devkitlipo.menu.FlashSize.16M=16MB (128Mb)
+esp32h2-devkitlipo.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32h2-devkitlipo.menu.UploadSpeed.921600=921600
+esp32h2-devkitlipo.menu.UploadSpeed.921600.upload.speed=921600
+esp32h2-devkitlipo.menu.UploadSpeed.115200=115200
+esp32h2-devkitlipo.menu.UploadSpeed.115200.upload.speed=115200
+esp32h2-devkitlipo.menu.UploadSpeed.256000.windows=256000
+esp32h2-devkitlipo.menu.UploadSpeed.256000.upload.speed=256000
+esp32h2-devkitlipo.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32h2-devkitlipo.menu.UploadSpeed.230400=230400
+esp32h2-devkitlipo.menu.UploadSpeed.230400.upload.speed=230400
+esp32h2-devkitlipo.menu.UploadSpeed.460800.linux=460800
+esp32h2-devkitlipo.menu.UploadSpeed.460800.macosx=460800
+esp32h2-devkitlipo.menu.UploadSpeed.460800.upload.speed=460800
+esp32h2-devkitlipo.menu.UploadSpeed.512000.windows=512000
+esp32h2-devkitlipo.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32h2-devkitlipo.menu.DebugLevel.none=None
+esp32h2-devkitlipo.menu.DebugLevel.none.build.code_debug=0
+esp32h2-devkitlipo.menu.DebugLevel.error=Error
+esp32h2-devkitlipo.menu.DebugLevel.error.build.code_debug=1
+esp32h2-devkitlipo.menu.DebugLevel.warn=Warn
+esp32h2-devkitlipo.menu.DebugLevel.warn.build.code_debug=2
+esp32h2-devkitlipo.menu.DebugLevel.info=Info
+esp32h2-devkitlipo.menu.DebugLevel.info.build.code_debug=3
+esp32h2-devkitlipo.menu.DebugLevel.debug=Debug
+esp32h2-devkitlipo.menu.DebugLevel.debug.build.code_debug=4
+esp32h2-devkitlipo.menu.DebugLevel.verbose=Verbose
+esp32h2-devkitlipo.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32h2-devkitlipo.menu.EraseFlash.none=Disabled
+esp32h2-devkitlipo.menu.EraseFlash.none.upload.erase_cmd=
+esp32h2-devkitlipo.menu.EraseFlash.all=Enabled
+esp32h2-devkitlipo.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32h2-devkitlipo.menu.ZigbeeMode.default=Disabled
+esp32h2-devkitlipo.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32h2-devkitlipo.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32h2-devkitlipo.menu.ZigbeeMode.ed=Zigbee ED (end device)
+esp32h2-devkitlipo.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+esp32h2-devkitlipo.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+esp32h2-devkitlipo.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32h2-devkitlipo.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32h2-devkitlipo.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
 
 ##############################################################
 
-esp32-DevKitLipo.name=OLIMEX ESP32-DevKit-LiPo
-
-esp32-DevKitLipo.upload.tool=esptool_py
-esp32-DevKitLipo.upload.maximum_size=1310720
-esp32-DevKitLipo.upload.maximum_data_size=327680
-esp32-DevKitLipo.upload.wait_for_upload_port=true
-
-esp32-DevKitLipo.serial.disableDTR=true
-esp32-DevKitLipo.serial.disableRTS=true
-
-esp32-DevKitLipo.build.mcu=esp32
-esp32-DevKitLipo.build.core=esp32
-esp32-DevKitLipo.build.variant=esp32-devkit-lipo
-esp32-DevKitLipo.build.board=ESP32_DEVKIT_LIPO
-
-esp32-DevKitLipo.build.f_cpu=240000000L
-esp32-DevKitLipo.build.flash_size=4MB
-esp32-DevKitLipo.build.flash_freq=40m
-esp32-DevKitLipo.build.flash_mode=dio
-esp32-DevKitLipo.build.boot=dio
-esp32-DevKitLipo.build.partitions=default
-esp32-DevKitLipo.build.defines=
-
-esp32-DevKitLipo.menu.PartitionScheme.default=Default
-esp32-DevKitLipo.menu.PartitionScheme.default.build.partitions=default
-esp32-DevKitLipo.menu.PartitionScheme.minimal=Minimal (2MB FLASH)
-esp32-DevKitLipo.menu.PartitionScheme.minimal.build.partitions=minimal
-esp32-DevKitLipo.menu.PartitionScheme.no_ota=No OTA (Large APP)
-esp32-DevKitLipo.menu.PartitionScheme.no_ota.build.partitions=no_ota
-esp32-DevKitLipo.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-esp32-DevKitLipo.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA)
-esp32-DevKitLipo.menu.PartitionScheme.huge_app.build.partitions=huge_app
-esp32-DevKitLipo.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
-esp32-DevKitLipo.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-esp32-DevKitLipo.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-esp32-DevKitLipo.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-esp32-DevKitLipo.menu.PartitionScheme.fatflash=16M Fat
-esp32-DevKitLipo.menu.PartitionScheme.fatflash.build.partitions=ffat
-
-esp32-DevKitLipo.menu.FlashMode.qio=QIO
-esp32-DevKitLipo.menu.FlashMode.qio.build.flash_mode=dio
-esp32-DevKitLipo.menu.FlashMode.qio.build.boot=qio
-esp32-DevKitLipo.menu.FlashMode.dio=DIO
-esp32-DevKitLipo.menu.FlashMode.dio.build.flash_mode=dio
-esp32-DevKitLipo.menu.FlashMode.dio.build.boot=dio
-esp32-DevKitLipo.menu.FlashMode.qout=QOUT
-esp32-DevKitLipo.menu.FlashMode.qout.build.flash_mode=dout
-esp32-DevKitLipo.menu.FlashMode.qout.build.boot=qout
-esp32-DevKitLipo.menu.FlashMode.dout=DOUT
-esp32-DevKitLipo.menu.FlashMode.dout.build.flash_mode=dout
-esp32-DevKitLipo.menu.FlashMode.dout.build.boot=dout
-
-esp32-DevKitLipo.menu.FlashFreq.80=80MHz
-esp32-DevKitLipo.menu.FlashFreq.80.build.flash_freq=80m
-esp32-DevKitLipo.menu.FlashFreq.40=40MHz
-esp32-DevKitLipo.menu.FlashFreq.40.build.flash_freq=40m
-
-esp32-DevKitLipo.menu.UploadSpeed.921600=921600
-esp32-DevKitLipo.menu.UploadSpeed.921600.upload.speed=921600
-esp32-DevKitLipo.menu.UploadSpeed.115200=115200
-esp32-DevKitLipo.menu.UploadSpeed.115200.upload.speed=115200
-esp32-DevKitLipo.menu.UploadSpeed.256000.windows=256000
-esp32-DevKitLipo.menu.UploadSpeed.256000.upload.speed=256000
-esp32-DevKitLipo.menu.UploadSpeed.230400.windows.upload.speed=256000
-esp32-DevKitLipo.menu.UploadSpeed.230400=230400
-esp32-DevKitLipo.menu.UploadSpeed.230400.upload.speed=230400
-esp32-DevKitLipo.menu.UploadSpeed.460800.linux=460800
-esp32-DevKitLipo.menu.UploadSpeed.460800.macosx=460800
-esp32-DevKitLipo.menu.UploadSpeed.460800.upload.speed=460800
-esp32-DevKitLipo.menu.UploadSpeed.512000.windows=512000
-esp32-DevKitLipo.menu.UploadSpeed.512000.upload.speed=512000
+esp32-sbc-fabgl.name=OLIMEX ESP32-SBC-FABGL
+
+esp32-sbc-fabgl.bootloader.tool=esptool_py
+esp32-sbc-fabgl.bootloader.tool.default=esptool_py
+
+esp32-sbc-fabgl.upload.tool=esptool_py
+esp32-sbc-fabgl.upload.tool.default=esptool_py
+esp32-sbc-fabgl.upload.tool.network=esp_ota
+
+esp32-sbc-fabgl.upload.maximum_size=1310720
+esp32-sbc-fabgl.upload.maximum_data_size=327680
+esp32-sbc-fabgl.upload.flags=
+esp32-sbc-fabgl.upload.extra_flags=
+
+esp32-sbc-fabgl.serial.disableDTR=true
+esp32-sbc-fabgl.serial.disableRTS=true
+
+esp32-sbc-fabgl.build.tarch=xtensa
+esp32-sbc-fabgl.build.bootloader_addr=0x1000
+esp32-sbc-fabgl.build.target=esp32
+esp32-sbc-fabgl.build.mcu=esp32
+esp32-sbc-fabgl.build.core=esp32
+esp32-sbc-fabgl.build.variant=esp32-sbc-fabgl
+esp32-sbc-fabgl.build.board=ESP32_SBC_FABGL
+
+esp32-sbc-fabgl.build.f_cpu=240000000L
+esp32-sbc-fabgl.build.flash_size=4MB
+esp32-sbc-fabgl.build.flash_freq=40m
+esp32-sbc-fabgl.build.flash_mode=dio
+esp32-sbc-fabgl.build.boot=dio
+esp32-sbc-fabgl.build.partitions=default
+esp32-sbc-fabgl.build.defines=
+esp32-sbc-fabgl.build.loop_core=
+esp32-sbc-fabgl.build.event_core=
+
+## IDE 2.0 Seems to not update the value
+esp32-sbc-fabgl.menu.JTAGAdapter.default=Disabled
+esp32-sbc-fabgl.menu.JTAGAdapter.default.build.copy_jtag_files=0
+esp32-sbc-fabgl.menu.JTAGAdapter.external=FTDI Adapter
+esp32-sbc-fabgl.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg
+esp32-sbc-fabgl.menu.JTAGAdapter.external.build.copy_jtag_files=1
+esp32-sbc-fabgl.menu.JTAGAdapter.bridge=ESP USB Bridge
+esp32-sbc-fabgl.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg
+esp32-sbc-fabgl.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+esp32-sbc-fabgl.menu.PSRAM.enabled=Enabled
+esp32-sbc-fabgl.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+esp32-sbc-fabgl.menu.PSRAM.enabled.build.extra_libs=
+esp32-sbc-fabgl.menu.PSRAM.disabled=Disabled
+esp32-sbc-fabgl.menu.PSRAM.disabled.build.defines=
+esp32-sbc-fabgl.menu.PSRAM.disabled.build.extra_libs=
+
+esp32-sbc-fabgl.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32-sbc-fabgl.menu.PartitionScheme.default.build.partitions=default
+esp32-sbc-fabgl.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32-sbc-fabgl.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32-sbc-fabgl.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32-sbc-fabgl.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32-sbc-fabgl.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32-sbc-fabgl.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32-sbc-fabgl.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32-sbc-fabgl.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32-sbc-fabgl.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32-sbc-fabgl.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32-sbc-fabgl.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32-sbc-fabgl.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32-sbc-fabgl.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32-sbc-fabgl.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32-sbc-fabgl.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32-sbc-fabgl.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32-sbc-fabgl.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32-sbc-fabgl.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32-sbc-fabgl.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32-sbc-fabgl.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32-sbc-fabgl.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32-sbc-fabgl.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32-sbc-fabgl.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32-sbc-fabgl.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32-sbc-fabgl.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32-sbc-fabgl.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+esp32-sbc-fabgl.menu.PartitionScheme.fatflash.build.partitions=ffat
+esp32-sbc-fabgl.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+esp32-sbc-fabgl.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+esp32-sbc-fabgl.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+esp32-sbc-fabgl.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+esp32-sbc-fabgl.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32-sbc-fabgl.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32-sbc-fabgl.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+esp32-sbc-fabgl.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+esp32-sbc-fabgl.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+esp32-sbc-fabgl.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+esp32-sbc-fabgl.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+esp32-sbc-fabgl.menu.PartitionScheme.custom=Custom
+esp32-sbc-fabgl.menu.PartitionScheme.custom.build.partitions=
+esp32-sbc-fabgl.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+esp32-sbc-fabgl.menu.CPUFreq.240=240MHz (WiFi/BT)
+esp32-sbc-fabgl.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32-sbc-fabgl.menu.CPUFreq.160=160MHz (WiFi/BT)
+esp32-sbc-fabgl.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32-sbc-fabgl.menu.CPUFreq.80=80MHz (WiFi/BT)
+esp32-sbc-fabgl.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32-sbc-fabgl.menu.CPUFreq.40=40MHz (40MHz XTAL)
+esp32-sbc-fabgl.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32-sbc-fabgl.menu.CPUFreq.26=26MHz (26MHz XTAL)
+esp32-sbc-fabgl.menu.CPUFreq.26.build.f_cpu=26000000L
+esp32-sbc-fabgl.menu.CPUFreq.20=20MHz (40MHz XTAL)
+esp32-sbc-fabgl.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32-sbc-fabgl.menu.CPUFreq.13=13MHz (26MHz XTAL)
+esp32-sbc-fabgl.menu.CPUFreq.13.build.f_cpu=13000000L
+esp32-sbc-fabgl.menu.CPUFreq.10=10MHz (40MHz XTAL)
+esp32-sbc-fabgl.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32-sbc-fabgl.menu.FlashMode.qio=QIO
+esp32-sbc-fabgl.menu.FlashMode.qio.build.flash_mode=dio
+esp32-sbc-fabgl.menu.FlashMode.qio.build.boot=qio
+esp32-sbc-fabgl.menu.FlashMode.dio=DIO
+esp32-sbc-fabgl.menu.FlashMode.dio.build.flash_mode=dio
+esp32-sbc-fabgl.menu.FlashMode.dio.build.boot=dio
+
+esp32-sbc-fabgl.menu.FlashFreq.80=80MHz
+esp32-sbc-fabgl.menu.FlashFreq.80.build.flash_freq=80m
+esp32-sbc-fabgl.menu.FlashFreq.40=40MHz
+esp32-sbc-fabgl.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32-sbc-fabgl.menu.FlashSize.4M=4MB (32Mb)
+esp32-sbc-fabgl.menu.FlashSize.4M.build.flash_size=4MB
+esp32-sbc-fabgl.menu.FlashSize.8M=8MB (64Mb)
+esp32-sbc-fabgl.menu.FlashSize.8M.build.flash_size=8MB
+esp32-sbc-fabgl.menu.FlashSize.2M=2MB (16Mb)
+esp32-sbc-fabgl.menu.FlashSize.2M.build.flash_size=2MB
+esp32-sbc-fabgl.menu.FlashSize.16M=16MB (128Mb)
+esp32-sbc-fabgl.menu.FlashSize.16M.build.flash_size=16MB
+
+esp32-sbc-fabgl.menu.UploadSpeed.921600=921600
+esp32-sbc-fabgl.menu.UploadSpeed.921600.upload.speed=921600
+esp32-sbc-fabgl.menu.UploadSpeed.115200=115200
+esp32-sbc-fabgl.menu.UploadSpeed.115200.upload.speed=115200
+esp32-sbc-fabgl.menu.UploadSpeed.256000.windows=256000
+esp32-sbc-fabgl.menu.UploadSpeed.256000.upload.speed=256000
+esp32-sbc-fabgl.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32-sbc-fabgl.menu.UploadSpeed.230400=230400
+esp32-sbc-fabgl.menu.UploadSpeed.230400.upload.speed=230400
+esp32-sbc-fabgl.menu.UploadSpeed.460800.linux=460800
+esp32-sbc-fabgl.menu.UploadSpeed.460800.macosx=460800
+esp32-sbc-fabgl.menu.UploadSpeed.460800.upload.speed=460800
+esp32-sbc-fabgl.menu.UploadSpeed.512000.windows=512000
+esp32-sbc-fabgl.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32-sbc-fabgl.menu.LoopCore.1=Core 1
+esp32-sbc-fabgl.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32-sbc-fabgl.menu.LoopCore.0=Core 0
+esp32-sbc-fabgl.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+esp32-sbc-fabgl.menu.EventsCore.1=Core 1
+esp32-sbc-fabgl.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+esp32-sbc-fabgl.menu.EventsCore.0=Core 0
+esp32-sbc-fabgl.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+esp32-sbc-fabgl.menu.DebugLevel.none=None
+esp32-sbc-fabgl.menu.DebugLevel.none.build.code_debug=0
+esp32-sbc-fabgl.menu.DebugLevel.error=Error
+esp32-sbc-fabgl.menu.DebugLevel.error.build.code_debug=1
+esp32-sbc-fabgl.menu.DebugLevel.warn=Warn
+esp32-sbc-fabgl.menu.DebugLevel.warn.build.code_debug=2
+esp32-sbc-fabgl.menu.DebugLevel.info=Info
+esp32-sbc-fabgl.menu.DebugLevel.info.build.code_debug=3
+esp32-sbc-fabgl.menu.DebugLevel.debug=Debug
+esp32-sbc-fabgl.menu.DebugLevel.debug.build.code_debug=4
+esp32-sbc-fabgl.menu.DebugLevel.verbose=Verbose
+esp32-sbc-fabgl.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32-sbc-fabgl.menu.EraseFlash.none=Disabled
+esp32-sbc-fabgl.menu.EraseFlash.none.upload.erase_cmd=
+esp32-sbc-fabgl.menu.EraseFlash.all=Enabled
+esp32-sbc-fabgl.menu.EraseFlash.all.upload.erase_cmd=-e
+
+esp32-sbc-fabgl.menu.ZigbeeMode.default=Disabled
+esp32-sbc-fabgl.menu.ZigbeeMode.default.build.zigbee_mode=
+esp32-sbc-fabgl.menu.ZigbeeMode.default.build.zigbee_libs=
+esp32-sbc-fabgl.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+esp32-sbc-fabgl.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+esp32-sbc-fabgl.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
 ##############################################################
 
 espino32.name=ThaiEasyElec's ESPino32
 
+espino32.bootloader.tool=esptool_py
+espino32.bootloader.tool.default=esptool_py
+
 espino32.upload.tool=esptool_py
+espino32.upload.tool.default=esptool_py
+espino32.upload.tool.network=esp_ota
+
 espino32.upload.maximum_size=1310720
 espino32.upload.maximum_data_size=327680
-espino32.upload.wait_for_upload_port=true
+espino32.upload.flags=
+espino32.upload.extra_flags=
 
 espino32.serial.disableDTR=true
 espino32.serial.disableRTS=true
 
+espino32.build.tarch=xtensa
+espino32.build.bootloader_addr=0x1000
+espino32.build.target=esp32
 espino32.build.mcu=esp32
 espino32.build.core=esp32
 espino32.build.variant=espino32
@@ -2458,539 +20154,4651 @@ espino32.menu.UploadSpeed.460800.upload.speed=460800
 espino32.menu.UploadSpeed.512000.windows=512000
 espino32.menu.UploadSpeed.512000.upload.speed=512000
 
+espino32.menu.DebugLevel.none=None
+espino32.menu.DebugLevel.none.build.code_debug=0
+espino32.menu.DebugLevel.error=Error
+espino32.menu.DebugLevel.error.build.code_debug=1
+espino32.menu.DebugLevel.warn=Warn
+espino32.menu.DebugLevel.warn.build.code_debug=2
+espino32.menu.DebugLevel.info=Info
+espino32.menu.DebugLevel.info.build.code_debug=3
+espino32.menu.DebugLevel.debug=Debug
+espino32.menu.DebugLevel.debug.build.code_debug=4
+espino32.menu.DebugLevel.verbose=Verbose
+espino32.menu.DebugLevel.verbose.build.code_debug=5
+
+espino32.menu.EraseFlash.none=Disabled
+espino32.menu.EraseFlash.none.upload.erase_cmd=
+espino32.menu.EraseFlash.all=Enabled
+espino32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_core.name=M5Core
+
+m5stack_core.bootloader.tool=esptool_py
+m5stack_core.bootloader.tool.default=esptool_py
+
+m5stack_core.upload.tool=esptool_py
+m5stack_core.upload.tool.default=esptool_py
+m5stack_core.upload.tool.network=esp_ota
+
+m5stack_core.upload.maximum_size=1310720
+m5stack_core.upload.maximum_data_size=327680
+m5stack_core.upload.flags=
+m5stack_core.upload.extra_flags=
+
+m5stack_core.serial.disableDTR=true
+m5stack_core.serial.disableRTS=true
+
+m5stack_core.build.tarch=xtensa
+m5stack_core.build.bootloader_addr=0x1000
+m5stack_core.build.target=esp32
+m5stack_core.build.mcu=esp32
+m5stack_core.build.core=esp32
+m5stack_core.build.variant=m5stack_core
+m5stack_core.build.board=M5STACK_CORE
+
+m5stack_core.build.f_cpu=240000000L
+m5stack_core.build.flash_size=4MB
+m5stack_core.build.flash_freq=80m
+m5stack_core.build.flash_mode=dio
+m5stack_core.build.boot=dio
+m5stack_core.build.partitions=default
+m5stack_core.build.defines=
+m5stack_core.build.loop_core=
+m5stack_core.build.event_core=
+
+m5stack_core.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_core.menu.PartitionScheme.default.build.partitions=default
+m5stack_core.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_core.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_core.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_core.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_core.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_core.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_core.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_core.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_core.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_core.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_core.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_core.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_core.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_core.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_core.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_core.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_core.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_core.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_core.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_core.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_core.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_core.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_core.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_core.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_core.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_core.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_core.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_core.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_core.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_core.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_core.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_core.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_core.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_core.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_core.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_core.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_core.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_core.menu.PartitionScheme.custom=Custom
+m5stack_core.menu.PartitionScheme.custom.build.partitions=
+m5stack_core.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_core.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_core.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_core.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_core.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_core.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_core.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_core.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_core.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_core.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_core.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_core.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_core.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_core.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_core.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_core.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_core.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_core.menu.FlashMode.qio=QIO
+m5stack_core.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_core.menu.FlashMode.qio.build.boot=qio
+m5stack_core.menu.FlashMode.dio=DIO
+m5stack_core.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_core.menu.FlashMode.dio.build.boot=dio
+m5stack_core.menu.FlashMode.qout=QOUT
+m5stack_core.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_core.menu.FlashMode.qout.build.boot=qout
+m5stack_core.menu.FlashMode.dout=DOUT
+m5stack_core.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_core.menu.FlashMode.dout.build.boot=dout
+
+m5stack_core.menu.FlashFreq.80=80MHz
+m5stack_core.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_core.menu.FlashFreq.40=40MHz
+m5stack_core.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_core.menu.FlashSize.4M=4MB (32Mb)
+m5stack_core.menu.FlashSize.4M.build.flash_size=4MB
+m5stack_core.menu.FlashSize.16M=16MB (128Mb)
+m5stack_core.menu.FlashSize.16M.build.flash_size=16MB
+
+m5stack_core.menu.UploadSpeed.1500000=1500000
+m5stack_core.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_core.menu.UploadSpeed.921600=921600
+m5stack_core.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_core.menu.UploadSpeed.115200=115200
+m5stack_core.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_core.menu.UploadSpeed.256000.windows=256000
+m5stack_core.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_core.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_core.menu.UploadSpeed.230400=230400
+m5stack_core.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_core.menu.UploadSpeed.460800.linux=460800
+m5stack_core.menu.UploadSpeed.460800.macosx=460800
+m5stack_core.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_core.menu.UploadSpeed.512000.windows=512000
+m5stack_core.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_core.menu.LoopCore.1=Core 1
+m5stack_core.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_core.menu.LoopCore.0=Core 0
+m5stack_core.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_core.menu.EventsCore.1=Core 1
+m5stack_core.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_core.menu.EventsCore.0=Core 0
+m5stack_core.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_core.menu.DebugLevel.none=None
+m5stack_core.menu.DebugLevel.none.build.code_debug=0
+m5stack_core.menu.DebugLevel.error=Error
+m5stack_core.menu.DebugLevel.error.build.code_debug=1
+m5stack_core.menu.DebugLevel.warn=Warn
+m5stack_core.menu.DebugLevel.warn.build.code_debug=2
+m5stack_core.menu.DebugLevel.info=Info
+m5stack_core.menu.DebugLevel.info.build.code_debug=3
+m5stack_core.menu.DebugLevel.debug=Debug
+m5stack_core.menu.DebugLevel.debug.build.code_debug=4
+m5stack_core.menu.DebugLevel.verbose=Verbose
+m5stack_core.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_core.menu.EraseFlash.none=Disabled
+m5stack_core.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_core.menu.EraseFlash.all=Enabled
+m5stack_core.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_fire.name=M5Fire
+
+m5stack_fire.bootloader.tool=esptool_py
+m5stack_fire.bootloader.tool.default=esptool_py
+
+m5stack_fire.upload.tool=esptool_py
+m5stack_fire.upload.tool.default=esptool_py
+m5stack_fire.upload.tool.network=esp_ota
+
+m5stack_fire.upload.maximum_size=6553600
+m5stack_fire.upload.maximum_data_size=4521984
+m5stack_fire.upload.flags=
+m5stack_fire.upload.extra_flags=
+
+m5stack_fire.serial.disableDTR=true
+m5stack_fire.serial.disableRTS=true
+
+m5stack_fire.build.tarch=xtensa
+m5stack_fire.build.bootloader_addr=0x1000
+m5stack_fire.build.target=esp32
+m5stack_fire.build.mcu=esp32
+m5stack_fire.build.core=esp32
+m5stack_fire.build.variant=m5stack_fire
+m5stack_fire.build.board=M5STACK_FIRE
+
+m5stack_fire.build.f_cpu=240000000L
+m5stack_fire.build.flash_size=16MB
+m5stack_fire.build.flash_freq=80m
+m5stack_fire.build.flash_mode=dio
+m5stack_fire.build.boot=dio
+m5stack_fire.build.partitions=default
+m5stack_fire.build.defines=
+m5stack_fire.build.loop_core=
+m5stack_fire.build.event_core=
+
+m5stack_fire.menu.PSRAM.enabled=Enabled
+m5stack_fire.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+m5stack_fire.menu.PSRAM.enabled.build.extra_libs=
+m5stack_fire.menu.PSRAM.disabled=Disabled
+m5stack_fire.menu.PSRAM.disabled.build.defines=
+m5stack_fire.menu.PSRAM.disabled.build.extra_libs=
+
+m5stack_fire.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS)
+m5stack_fire.menu.PartitionScheme.default.build.partitions=default_16MB
+m5stack_fire.menu.PartitionScheme.default.upload.maximum_size=6553600
+m5stack_fire.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_fire.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_fire.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_fire.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_fire.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_fire.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_fire.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_fire.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_fire.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_fire.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_fire.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_fire.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_fire.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_fire.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_fire.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_fire.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_fire.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_fire.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_fire.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_fire.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_fire.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_fire.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_fire.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_fire.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_fire.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_fire.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_fire.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_fire.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_fire.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_fire.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_fire.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_fire.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_fire.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_fire.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_fire.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_fire.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_fire.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_fire.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_fire.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_fire.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_fire.menu.PartitionScheme.custom=Custom
+m5stack_fire.menu.PartitionScheme.custom.build.partitions=
+m5stack_fire.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_fire.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_fire.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_fire.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_fire.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_fire.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_fire.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_fire.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_fire.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_fire.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_fire.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_fire.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_fire.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_fire.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_fire.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_fire.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_fire.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_fire.menu.FlashMode.qio=QIO
+m5stack_fire.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_fire.menu.FlashMode.qio.build.boot=qio
+m5stack_fire.menu.FlashMode.dio=DIO
+m5stack_fire.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_fire.menu.FlashMode.dio.build.boot=dio
+m5stack_fire.menu.FlashMode.qout=QOUT
+m5stack_fire.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_fire.menu.FlashMode.qout.build.boot=qout
+m5stack_fire.menu.FlashMode.dout=DOUT
+m5stack_fire.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_fire.menu.FlashMode.dout.build.boot=dout
+
+m5stack_fire.menu.FlashFreq.80=80MHz
+m5stack_fire.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_fire.menu.FlashFreq.40=40MHz
+m5stack_fire.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_fire.menu.FlashSize.16M=16MB (128Mb)
+m5stack_fire.menu.FlashSize.16M.build.flash_size=16MB
+
+m5stack_fire.menu.UploadSpeed.1500000=1500000
+m5stack_fire.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_fire.menu.UploadSpeed.921600=921600
+m5stack_fire.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_fire.menu.UploadSpeed.115200=115200
+m5stack_fire.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_fire.menu.UploadSpeed.256000.windows=256000
+m5stack_fire.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_fire.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_fire.menu.UploadSpeed.230400=230400
+m5stack_fire.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_fire.menu.UploadSpeed.460800.linux=460800
+m5stack_fire.menu.UploadSpeed.460800.macosx=460800
+m5stack_fire.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_fire.menu.UploadSpeed.512000.windows=512000
+m5stack_fire.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_fire.menu.LoopCore.1=Core 1
+m5stack_fire.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_fire.menu.LoopCore.0=Core 0
+m5stack_fire.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_fire.menu.EventsCore.1=Core 1
+m5stack_fire.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_fire.menu.EventsCore.0=Core 0
+m5stack_fire.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_fire.menu.DebugLevel.none=None
+m5stack_fire.menu.DebugLevel.none.build.code_debug=0
+m5stack_fire.menu.DebugLevel.error=Error
+m5stack_fire.menu.DebugLevel.error.build.code_debug=1
+m5stack_fire.menu.DebugLevel.warn=Warn
+m5stack_fire.menu.DebugLevel.warn.build.code_debug=2
+m5stack_fire.menu.DebugLevel.info=Info
+m5stack_fire.menu.DebugLevel.info.build.code_debug=3
+m5stack_fire.menu.DebugLevel.debug=Debug
+m5stack_fire.menu.DebugLevel.debug.build.code_debug=4
+m5stack_fire.menu.DebugLevel.verbose=Verbose
+m5stack_fire.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_fire.menu.EraseFlash.none=Disabled
+m5stack_fire.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_fire.menu.EraseFlash.all=Enabled
+m5stack_fire.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_core2.name=M5Core2
+
+m5stack_core2.bootloader.tool=esptool_py
+m5stack_core2.bootloader.tool.default=esptool_py
+
+m5stack_core2.upload.tool=esptool_py
+m5stack_core2.upload.tool.default=esptool_py
+m5stack_core2.upload.tool.network=esp_ota
+
+m5stack_core2.upload.maximum_size=6553600
+m5stack_core2.upload.maximum_data_size=4521984
+m5stack_core2.upload.flags=
+m5stack_core2.upload.extra_flags=
+
+m5stack_core2.serial.disableDTR=true
+m5stack_core2.serial.disableRTS=true
+
+m5stack_core2.build.tarch=xtensa
+m5stack_core2.build.bootloader_addr=0x1000
+m5stack_core2.build.target=esp32
+m5stack_core2.build.mcu=esp32
+m5stack_core2.build.core=esp32
+m5stack_core2.build.variant=m5stack_core2
+m5stack_core2.build.board=M5STACK_CORE2
+
+m5stack_core2.build.f_cpu=240000000L
+m5stack_core2.build.flash_size=16MB
+m5stack_core2.build.flash_freq=80m
+m5stack_core2.build.flash_mode=dio
+m5stack_core2.build.boot=dio
+m5stack_core2.build.partitions=default
+m5stack_core2.build.defines=
+m5stack_core2.build.loop_core=
+m5stack_core2.build.event_core=
+
+m5stack_core2.menu.PSRAM.enabled=Enabled
+m5stack_core2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+m5stack_core2.menu.PSRAM.enabled.build.extra_libs=
+m5stack_core2.menu.PSRAM.disabled=Disabled
+m5stack_core2.menu.PSRAM.disabled.build.defines=
+m5stack_core2.menu.PSRAM.disabled.build.extra_libs=
+
+m5stack_core2.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS)
+m5stack_core2.menu.PartitionScheme.default.build.partitions=default_16MB
+m5stack_core2.menu.PartitionScheme.default.upload.maximum_size=6553600
+m5stack_core2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_core2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_core2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_core2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_core2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_core2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_core2.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_core2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_core2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_core2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_core2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_core2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_core2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_core2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_core2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_core2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_core2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_core2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_core2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_core2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_core2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_core2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_core2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_core2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_core2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_core2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_core2.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_core2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_core2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_core2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_core2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_core2.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_core2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_core2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_core2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_core2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_core2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_core2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_core2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_core2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_core2.menu.PartitionScheme.custom=Custom
+m5stack_core2.menu.PartitionScheme.custom.build.partitions=
+m5stack_core2.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_core2.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_core2.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_core2.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_core2.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_core2.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_core2.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_core2.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_core2.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_core2.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_core2.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_core2.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_core2.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_core2.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_core2.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_core2.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_core2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_core2.menu.FlashMode.qio=QIO
+m5stack_core2.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_core2.menu.FlashMode.qio.build.boot=qio
+m5stack_core2.menu.FlashMode.dio=DIO
+m5stack_core2.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_core2.menu.FlashMode.dio.build.boot=dio
+m5stack_core2.menu.FlashMode.qout=QOUT
+m5stack_core2.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_core2.menu.FlashMode.qout.build.boot=qout
+m5stack_core2.menu.FlashMode.dout=DOUT
+m5stack_core2.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_core2.menu.FlashMode.dout.build.boot=dout
+
+m5stack_core2.menu.FlashFreq.80=80MHz
+m5stack_core2.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_core2.menu.FlashFreq.40=40MHz
+m5stack_core2.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_core2.menu.FlashSize.16M=16MB (128Mb)
+m5stack_core2.menu.FlashSize.16M.build.flash_size=16MB
+
+m5stack_core2.menu.UploadSpeed.1500000=1500000
+m5stack_core2.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_core2.menu.UploadSpeed.921600=921600
+m5stack_core2.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_core2.menu.UploadSpeed.115200=115200
+m5stack_core2.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_core2.menu.UploadSpeed.256000.windows=256000
+m5stack_core2.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_core2.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_core2.menu.UploadSpeed.230400=230400
+m5stack_core2.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_core2.menu.UploadSpeed.460800.linux=460800
+m5stack_core2.menu.UploadSpeed.460800.macosx=460800
+m5stack_core2.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_core2.menu.UploadSpeed.512000.windows=512000
+m5stack_core2.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_core2.menu.LoopCore.1=Core 1
+m5stack_core2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_core2.menu.LoopCore.0=Core 0
+m5stack_core2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_core2.menu.EventsCore.1=Core 1
+m5stack_core2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_core2.menu.EventsCore.0=Core 0
+m5stack_core2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_core2.menu.DebugLevel.none=None
+m5stack_core2.menu.DebugLevel.none.build.code_debug=0
+m5stack_core2.menu.DebugLevel.error=Error
+m5stack_core2.menu.DebugLevel.error.build.code_debug=1
+m5stack_core2.menu.DebugLevel.warn=Warn
+m5stack_core2.menu.DebugLevel.warn.build.code_debug=2
+m5stack_core2.menu.DebugLevel.info=Info
+m5stack_core2.menu.DebugLevel.info.build.code_debug=3
+m5stack_core2.menu.DebugLevel.debug=Debug
+m5stack_core2.menu.DebugLevel.debug.build.code_debug=4
+m5stack_core2.menu.DebugLevel.verbose=Verbose
+m5stack_core2.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_core2.menu.EraseFlash.none=Disabled
+m5stack_core2.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_core2.menu.EraseFlash.all=Enabled
+m5stack_core2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_tough.name=M5Tough
+
+m5stack_tough.bootloader.tool=esptool_py
+m5stack_tough.bootloader.tool.default=esptool_py
+
+m5stack_tough.upload.tool=esptool_py
+m5stack_tough.upload.tool.default=esptool_py
+m5stack_tough.upload.tool.network=esp_ota
+
+m5stack_tough.upload.maximum_size=6553600
+m5stack_tough.upload.maximum_data_size=4521984
+m5stack_tough.upload.flags=
+m5stack_tough.upload.extra_flags=
+
+m5stack_tough.serial.disableDTR=true
+m5stack_tough.serial.disableRTS=true
+
+m5stack_tough.build.tarch=xtensa
+m5stack_tough.build.bootloader_addr=0x1000
+m5stack_tough.build.target=esp32
+m5stack_tough.build.mcu=esp32
+m5stack_tough.build.core=esp32
+m5stack_tough.build.variant=m5stack_tough
+m5stack_tough.build.board=M5STACK_TOUGH
+
+m5stack_tough.build.f_cpu=240000000L
+m5stack_tough.build.flash_size=16MB
+m5stack_tough.build.flash_freq=80m
+m5stack_tough.build.flash_mode=dio
+m5stack_tough.build.boot=dio
+m5stack_tough.build.partitions=default
+m5stack_tough.build.defines=
+m5stack_tough.build.loop_core=
+m5stack_tough.build.event_core=
+
+m5stack_tough.menu.PSRAM.enabled=Enabled
+m5stack_tough.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+m5stack_tough.menu.PSRAM.enabled.build.extra_libs=
+m5stack_tough.menu.PSRAM.disabled=Disabled
+m5stack_tough.menu.PSRAM.disabled.build.defines=
+m5stack_tough.menu.PSRAM.disabled.build.extra_libs=
+
+m5stack_tough.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS)
+m5stack_tough.menu.PartitionScheme.default.build.partitions=default_16MB
+m5stack_tough.menu.PartitionScheme.default.upload.maximum_size=6553600
+m5stack_tough.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_tough.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_tough.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_tough.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_tough.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_tough.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_tough.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_tough.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_tough.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_tough.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_tough.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_tough.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_tough.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_tough.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_tough.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_tough.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_tough.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_tough.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_tough.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_tough.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_tough.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_tough.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_tough.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_tough.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_tough.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_tough.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_tough.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_tough.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_tough.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_tough.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_tough.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_tough.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_tough.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_tough.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_tough.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_tough.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_tough.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_tough.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_tough.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_tough.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_tough.menu.PartitionScheme.custom=Custom
+m5stack_tough.menu.PartitionScheme.custom.build.partitions=
+m5stack_tough.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_tough.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_tough.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_tough.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_tough.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_tough.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_tough.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_tough.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_tough.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_tough.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_tough.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_tough.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_tough.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_tough.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_tough.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_tough.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_tough.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_tough.menu.FlashMode.qio=QIO
+m5stack_tough.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_tough.menu.FlashMode.qio.build.boot=qio
+m5stack_tough.menu.FlashMode.dio=DIO
+m5stack_tough.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_tough.menu.FlashMode.dio.build.boot=dio
+m5stack_tough.menu.FlashMode.qout=QOUT
+m5stack_tough.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_tough.menu.FlashMode.qout.build.boot=qout
+m5stack_tough.menu.FlashMode.dout=DOUT
+m5stack_tough.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_tough.menu.FlashMode.dout.build.boot=dout
+
+m5stack_tough.menu.FlashFreq.80=80MHz
+m5stack_tough.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_tough.menu.FlashFreq.40=40MHz
+m5stack_tough.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_tough.menu.FlashSize.16M=16MB (128Mb)
+m5stack_tough.menu.FlashSize.16M.build.flash_size=16MB
+
+m5stack_tough.menu.UploadSpeed.1500000=1500000
+m5stack_tough.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_tough.menu.UploadSpeed.921600=921600
+m5stack_tough.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_tough.menu.UploadSpeed.115200=115200
+m5stack_tough.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_tough.menu.UploadSpeed.256000.windows=256000
+m5stack_tough.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_tough.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_tough.menu.UploadSpeed.230400=230400
+m5stack_tough.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_tough.menu.UploadSpeed.460800.linux=460800
+m5stack_tough.menu.UploadSpeed.460800.macosx=460800
+m5stack_tough.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_tough.menu.UploadSpeed.512000.windows=512000
+m5stack_tough.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_tough.menu.LoopCore.1=Core 1
+m5stack_tough.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_tough.menu.LoopCore.0=Core 0
+m5stack_tough.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_tough.menu.EventsCore.1=Core 1
+m5stack_tough.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_tough.menu.EventsCore.0=Core 0
+m5stack_tough.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_tough.menu.DebugLevel.none=None
+m5stack_tough.menu.DebugLevel.none.build.code_debug=0
+m5stack_tough.menu.DebugLevel.error=Error
+m5stack_tough.menu.DebugLevel.error.build.code_debug=1
+m5stack_tough.menu.DebugLevel.warn=Warn
+m5stack_tough.menu.DebugLevel.warn.build.code_debug=2
+m5stack_tough.menu.DebugLevel.info=Info
+m5stack_tough.menu.DebugLevel.info.build.code_debug=3
+m5stack_tough.menu.DebugLevel.debug=Debug
+m5stack_tough.menu.DebugLevel.debug.build.code_debug=4
+m5stack_tough.menu.DebugLevel.verbose=Verbose
+m5stack_tough.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_tough.menu.EraseFlash.none=Disabled
+m5stack_tough.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_tough.menu.EraseFlash.all=Enabled
+m5stack_tough.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_station.name=M5Station
+
+m5stack_station.bootloader.tool=esptool_py
+m5stack_station.bootloader.tool.default=esptool_py
+
+m5stack_station.upload.tool=esptool_py
+m5stack_station.upload.tool.default=esptool_py
+m5stack_station.upload.tool.network=esp_ota
+
+m5stack_station.upload.maximum_size=6553600
+m5stack_station.upload.maximum_data_size=4521984
+m5stack_station.upload.flags=
+m5stack_station.upload.extra_flags=
+
+m5stack_station.serial.disableDTR=true
+m5stack_station.serial.disableRTS=true
+
+m5stack_station.build.tarch=xtensa
+m5stack_station.build.bootloader_addr=0x1000
+m5stack_station.build.target=esp32
+m5stack_station.build.mcu=esp32
+m5stack_station.build.core=esp32
+m5stack_station.build.variant=m5stack_station
+m5stack_station.build.board=M5STACK_STATION
+
+m5stack_station.build.f_cpu=240000000L
+m5stack_station.build.flash_size=16MB
+m5stack_station.build.flash_freq=80m
+m5stack_station.build.flash_mode=dio
+m5stack_station.build.boot=dio
+m5stack_station.build.partitions=default
+m5stack_station.build.defines=
+m5stack_station.build.loop_core=
+m5stack_station.build.event_core=
+
+m5stack_station.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS)
+m5stack_station.menu.PartitionScheme.default.build.partitions=default_16MB
+m5stack_station.menu.PartitionScheme.default.upload.maximum_size=6553600
+m5stack_station.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_station.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_station.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_station.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_station.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_station.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_station.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_station.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_station.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_station.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_station.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_station.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_station.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_station.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_station.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_station.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_station.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_station.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_station.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_station.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_station.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_station.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_station.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_station.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_station.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_station.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_station.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_station.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_station.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_station.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_station.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_station.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_station.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_station.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_station.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_station.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_station.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_station.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_station.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_station.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_station.menu.PartitionScheme.custom=Custom
+m5stack_station.menu.PartitionScheme.custom.build.partitions=
+m5stack_station.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_station.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_station.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_station.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_station.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_station.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_station.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_station.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_station.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_station.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_station.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_station.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_station.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_station.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_station.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_station.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_station.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_station.menu.FlashMode.qio=QIO
+m5stack_station.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_station.menu.FlashMode.qio.build.boot=qio
+m5stack_station.menu.FlashMode.dio=DIO
+m5stack_station.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_station.menu.FlashMode.dio.build.boot=dio
+m5stack_station.menu.FlashMode.qout=QOUT
+m5stack_station.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_station.menu.FlashMode.qout.build.boot=qout
+m5stack_station.menu.FlashMode.dout=DOUT
+m5stack_station.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_station.menu.FlashMode.dout.build.boot=dout
+
+m5stack_station.menu.FlashFreq.80=80MHz
+m5stack_station.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_station.menu.FlashFreq.40=40MHz
+m5stack_station.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_station.menu.FlashSize.16M=16MB (128Mb)
+m5stack_station.menu.FlashSize.16M.build.flash_size=16MB
+
+m5stack_station.menu.UploadSpeed.1500000=1500000
+m5stack_station.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_station.menu.UploadSpeed.921600=921600
+m5stack_station.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_station.menu.UploadSpeed.115200=115200
+m5stack_station.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_station.menu.UploadSpeed.256000.windows=256000
+m5stack_station.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_station.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_station.menu.UploadSpeed.230400=230400
+m5stack_station.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_station.menu.UploadSpeed.460800.linux=460800
+m5stack_station.menu.UploadSpeed.460800.macosx=460800
+m5stack_station.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_station.menu.UploadSpeed.512000.windows=512000
+m5stack_station.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_station.menu.LoopCore.1=Core 1
+m5stack_station.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_station.menu.LoopCore.0=Core 0
+m5stack_station.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_station.menu.EventsCore.1=Core 1
+m5stack_station.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_station.menu.EventsCore.0=Core 0
+m5stack_station.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_station.menu.DebugLevel.none=None
+m5stack_station.menu.DebugLevel.none.build.code_debug=0
+m5stack_station.menu.DebugLevel.error=Error
+m5stack_station.menu.DebugLevel.error.build.code_debug=1
+m5stack_station.menu.DebugLevel.warn=Warn
+m5stack_station.menu.DebugLevel.warn.build.code_debug=2
+m5stack_station.menu.DebugLevel.info=Info
+m5stack_station.menu.DebugLevel.info.build.code_debug=3
+m5stack_station.menu.DebugLevel.debug=Debug
+m5stack_station.menu.DebugLevel.debug.build.code_debug=4
+m5stack_station.menu.DebugLevel.verbose=Verbose
+m5stack_station.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_station.menu.EraseFlash.none=Disabled
+m5stack_station.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_station.menu.EraseFlash.all=Enabled
+m5stack_station.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_stickc.name=M5StickC
+
+m5stack_stickc.bootloader.tool=esptool_py
+m5stack_stickc.bootloader.tool.default=esptool_py
+
+m5stack_stickc.upload.tool=esptool_py
+m5stack_stickc.upload.tool.default=esptool_py
+m5stack_stickc.upload.tool.network=esp_ota
+
+m5stack_stickc.upload.maximum_size=1310720
+m5stack_stickc.upload.maximum_data_size=327680
+m5stack_stickc.upload.flags=
+m5stack_stickc.upload.extra_flags=
+
+m5stack_stickc.serial.disableDTR=true
+m5stack_stickc.serial.disableRTS=true
+
+m5stack_stickc.build.tarch=xtensa
+m5stack_stickc.build.bootloader_addr=0x1000
+m5stack_stickc.build.target=esp32
+m5stack_stickc.build.mcu=esp32
+m5stack_stickc.build.core=esp32
+m5stack_stickc.build.variant=m5stack_stickc
+m5stack_stickc.build.board=M5STACK_STICKC
+
+m5stack_stickc.build.f_cpu=240000000L
+m5stack_stickc.build.flash_size=4MB
+m5stack_stickc.build.flash_freq=80m
+m5stack_stickc.build.flash_mode=dio
+m5stack_stickc.build.boot=dio
+m5stack_stickc.build.partitions=huge_app
+m5stack_stickc.build.defines=
+m5stack_stickc.build.loop_core=
+m5stack_stickc.build.event_core=
+
+m5stack_stickc.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_stickc.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_stickc.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_stickc.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_stickc.menu.PartitionScheme.default.build.partitions=default
+m5stack_stickc.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_stickc.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_stickc.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_stickc.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_stickc.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_stickc.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_stickc.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_stickc.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_stickc.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_stickc.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_stickc.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_stickc.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_stickc.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_stickc.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_stickc.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_stickc.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_stickc.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_stickc.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_stickc.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_stickc.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_stickc.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_stickc.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_stickc.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_stickc.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_stickc.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_stickc.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_stickc.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_stickc.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_stickc.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_stickc.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_stickc.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_stickc.menu.PartitionScheme.custom=Custom
+m5stack_stickc.menu.PartitionScheme.custom.build.partitions=
+m5stack_stickc.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_stickc.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_stickc.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_stickc.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_stickc.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_stickc.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_stickc.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_stickc.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_stickc.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_stickc.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_stickc.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_stickc.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_stickc.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_stickc.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_stickc.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_stickc.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_stickc.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_stickc.menu.FlashMode.qio=QIO
+m5stack_stickc.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_stickc.menu.FlashMode.qio.build.boot=qio
+m5stack_stickc.menu.FlashMode.dio=DIO
+m5stack_stickc.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_stickc.menu.FlashMode.dio.build.boot=dio
+m5stack_stickc.menu.FlashMode.qout=QOUT
+m5stack_stickc.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_stickc.menu.FlashMode.qout.build.boot=qout
+m5stack_stickc.menu.FlashMode.dout=DOUT
+m5stack_stickc.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_stickc.menu.FlashMode.dout.build.boot=dout
+
+m5stack_stickc.menu.FlashFreq.80=80MHz
+m5stack_stickc.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_stickc.menu.FlashFreq.40=40MHz
+m5stack_stickc.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_stickc.menu.FlashSize.4M=4MB (32Mb)
+m5stack_stickc.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_stickc.menu.UploadSpeed.1500000=1500000
+m5stack_stickc.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_stickc.menu.UploadSpeed.750000=750000
+m5stack_stickc.menu.UploadSpeed.750000.upload.speed=750000
+m5stack_stickc.menu.UploadSpeed.500000=500000
+m5stack_stickc.menu.UploadSpeed.500000.upload.speed=500000
+m5stack_stickc.menu.UploadSpeed.250000=250000
+m5stack_stickc.menu.UploadSpeed.250000.upload.speed=250000
+m5stack_stickc.menu.UploadSpeed.115200=115200
+m5stack_stickc.menu.UploadSpeed.115200.upload.speed=115200
+
+m5stack_stickc.menu.LoopCore.1=Core 1
+m5stack_stickc.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_stickc.menu.LoopCore.0=Core 0
+m5stack_stickc.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_stickc.menu.EventsCore.1=Core 1
+m5stack_stickc.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_stickc.menu.EventsCore.0=Core 0
+m5stack_stickc.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_stickc.menu.DebugLevel.none=None
+m5stack_stickc.menu.DebugLevel.none.build.code_debug=0
+m5stack_stickc.menu.DebugLevel.error=Error
+m5stack_stickc.menu.DebugLevel.error.build.code_debug=1
+m5stack_stickc.menu.DebugLevel.warn=Warn
+m5stack_stickc.menu.DebugLevel.warn.build.code_debug=2
+m5stack_stickc.menu.DebugLevel.info=Info
+m5stack_stickc.menu.DebugLevel.info.build.code_debug=3
+m5stack_stickc.menu.DebugLevel.debug=Debug
+m5stack_stickc.menu.DebugLevel.debug.build.code_debug=4
+m5stack_stickc.menu.DebugLevel.verbose=Verbose
+m5stack_stickc.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_stickc.menu.EraseFlash.none=Disabled
+m5stack_stickc.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_stickc.menu.EraseFlash.all=Enabled
+m5stack_stickc.menu.EraseFlash.all.upload.erase_cmd=-e
+
+
+##############################################################
+
+m5stack_stickc_plus.name=M5StickCPlus
+
+m5stack_stickc_plus.bootloader.tool=esptool_py
+m5stack_stickc_plus.bootloader.tool.default=esptool_py
+
+m5stack_stickc_plus.upload.tool=esptool_py
+m5stack_stickc_plus.upload.tool.default=esptool_py
+m5stack_stickc_plus.upload.tool.network=esp_ota
+
+m5stack_stickc_plus.upload.maximum_size=1310720
+m5stack_stickc_plus.upload.maximum_data_size=327680
+m5stack_stickc_plus.upload.flags=
+m5stack_stickc_plus.upload.extra_flags=
+
+m5stack_stickc_plus.serial.disableDTR=true
+m5stack_stickc_plus.serial.disableRTS=true
+
+m5stack_stickc_plus.build.tarch=xtensa
+m5stack_stickc_plus.build.bootloader_addr=0x1000
+m5stack_stickc_plus.build.target=esp32
+m5stack_stickc_plus.build.mcu=esp32
+m5stack_stickc_plus.build.core=esp32
+m5stack_stickc_plus.build.variant=m5stack_stickc_plus
+m5stack_stickc_plus.build.board=M5STACK_STICKC_PLUS
+
+m5stack_stickc_plus.build.f_cpu=240000000L
+m5stack_stickc_plus.build.flash_size=4MB
+m5stack_stickc_plus.build.flash_freq=80m
+m5stack_stickc_plus.build.flash_mode=dio
+m5stack_stickc_plus.build.boot=dio
+m5stack_stickc_plus.build.partitions=huge_app
+m5stack_stickc_plus.build.defines=
+m5stack_stickc_plus.build.loop_core=
+m5stack_stickc_plus.build.event_core=
+
+m5stack_stickc_plus.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_stickc_plus.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_stickc_plus.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_stickc_plus.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_stickc_plus.menu.PartitionScheme.default.build.partitions=default
+m5stack_stickc_plus.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_stickc_plus.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_stickc_plus.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_stickc_plus.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_stickc_plus.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_stickc_plus.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_stickc_plus.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_stickc_plus.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_stickc_plus.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_stickc_plus.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_stickc_plus.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_stickc_plus.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_stickc_plus.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_stickc_plus.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_stickc_plus.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_stickc_plus.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_stickc_plus.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_stickc_plus.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_stickc_plus.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_stickc_plus.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_stickc_plus.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_stickc_plus.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_stickc_plus.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_stickc_plus.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_stickc_plus.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_stickc_plus.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_stickc_plus.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_stickc_plus.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_stickc_plus.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_stickc_plus.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_stickc_plus.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_stickc_plus.menu.PartitionScheme.custom=Custom
+m5stack_stickc_plus.menu.PartitionScheme.custom.build.partitions=
+m5stack_stickc_plus.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_stickc_plus.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_stickc_plus.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_stickc_plus.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_stickc_plus.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_stickc_plus.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_stickc_plus.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_stickc_plus.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_stickc_plus.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_stickc_plus.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_stickc_plus.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_stickc_plus.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_stickc_plus.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_stickc_plus.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_stickc_plus.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_stickc_plus.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_stickc_plus.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_stickc_plus.menu.FlashMode.qio=QIO
+m5stack_stickc_plus.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_stickc_plus.menu.FlashMode.qio.build.boot=qio
+m5stack_stickc_plus.menu.FlashMode.dio=DIO
+m5stack_stickc_plus.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_stickc_plus.menu.FlashMode.dio.build.boot=dio
+m5stack_stickc_plus.menu.FlashMode.qout=QOUT
+m5stack_stickc_plus.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_stickc_plus.menu.FlashMode.qout.build.boot=qout
+m5stack_stickc_plus.menu.FlashMode.dout=DOUT
+m5stack_stickc_plus.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_stickc_plus.menu.FlashMode.dout.build.boot=dout
+
+m5stack_stickc_plus.menu.FlashFreq.80=80MHz
+m5stack_stickc_plus.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_stickc_plus.menu.FlashFreq.40=40MHz
+m5stack_stickc_plus.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_stickc_plus.menu.FlashSize.4M=4MB (32Mb)
+m5stack_stickc_plus.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_stickc_plus.menu.UploadSpeed.1500000=1500000
+m5stack_stickc_plus.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_stickc_plus.menu.UploadSpeed.750000=750000
+m5stack_stickc_plus.menu.UploadSpeed.750000.upload.speed=750000
+m5stack_stickc_plus.menu.UploadSpeed.500000=500000
+m5stack_stickc_plus.menu.UploadSpeed.500000.upload.speed=500000
+m5stack_stickc_plus.menu.UploadSpeed.250000=250000
+m5stack_stickc_plus.menu.UploadSpeed.250000.upload.speed=250000
+m5stack_stickc_plus.menu.UploadSpeed.115200=115200
+m5stack_stickc_plus.menu.UploadSpeed.115200.upload.speed=115200
+
+m5stack_stickc_plus.menu.LoopCore.1=Core 1
+m5stack_stickc_plus.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_stickc_plus.menu.LoopCore.0=Core 0
+m5stack_stickc_plus.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_stickc_plus.menu.EventsCore.1=Core 1
+m5stack_stickc_plus.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_stickc_plus.menu.EventsCore.0=Core 0
+m5stack_stickc_plus.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_stickc_plus.menu.DebugLevel.none=None
+m5stack_stickc_plus.menu.DebugLevel.none.build.code_debug=0
+m5stack_stickc_plus.menu.DebugLevel.error=Error
+m5stack_stickc_plus.menu.DebugLevel.error.build.code_debug=1
+m5stack_stickc_plus.menu.DebugLevel.warn=Warn
+m5stack_stickc_plus.menu.DebugLevel.warn.build.code_debug=2
+m5stack_stickc_plus.menu.DebugLevel.info=Info
+m5stack_stickc_plus.menu.DebugLevel.info.build.code_debug=3
+m5stack_stickc_plus.menu.DebugLevel.debug=Debug
+m5stack_stickc_plus.menu.DebugLevel.debug.build.code_debug=4
+m5stack_stickc_plus.menu.DebugLevel.verbose=Verbose
+m5stack_stickc_plus.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_stickc_plus.menu.EraseFlash.none=Disabled
+m5stack_stickc_plus.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_stickc_plus.menu.EraseFlash.all=Enabled
+m5stack_stickc_plus.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_stickc_plus2.name=M5StickCPlus2
+
+m5stack_stickc_plus2.bootloader.tool=esptool_py
+m5stack_stickc_plus2.bootloader.tool.default=esptool_py
+
+m5stack_stickc_plus2.upload.tool=esptool_py
+m5stack_stickc_plus2.upload.tool.default=esptool_py
+m5stack_stickc_plus2.upload.tool.network=esp_ota
+
+m5stack_stickc_plus2.upload.maximum_size=3342336
+m5stack_stickc_plus2.upload.maximum_data_size=327680
+m5stack_stickc_plus2.upload.flags=
+m5stack_stickc_plus2.upload.extra_flags=
+
+m5stack_stickc_plus2.serial.disableDTR=true
+m5stack_stickc_plus2.serial.disableRTS=true
+
+m5stack_stickc_plus2.build.tarch=xtensa
+m5stack_stickc_plus2.build.bootloader_addr=0x1000
+m5stack_stickc_plus2.build.target=esp32
+m5stack_stickc_plus2.build.mcu=esp32
+m5stack_stickc_plus2.build.core=esp32
+m5stack_stickc_plus2.build.variant=m5stack_stickc_plus2
+m5stack_stickc_plus2.build.board=M5STACK_STICKC_PLUS2
+
+m5stack_stickc_plus2.build.f_cpu=240000000L
+m5stack_stickc_plus2.build.flash_size=8MB
+m5stack_stickc_plus2.build.flash_freq=80m
+m5stack_stickc_plus2.build.flash_mode=dio
+m5stack_stickc_plus2.build.boot=dio
+m5stack_stickc_plus2.build.partitions=default_8MB
+m5stack_stickc_plus2.build.defines=
+m5stack_stickc_plus2.build.loop_core=
+m5stack_stickc_plus2.build.event_core=
+
+m5stack_stickc_plus2.menu.PSRAM.enabled=Enabled
+m5stack_stickc_plus2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+m5stack_stickc_plus2.menu.PSRAM.enabled.build.extra_libs=
+m5stack_stickc_plus2.menu.PSRAM.disabled=Disabled
+m5stack_stickc_plus2.menu.PSRAM.disabled.build.defines=
+m5stack_stickc_plus2.menu.PSRAM.disabled.build.extra_libs=
+
+m5stack_stickc_plus2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_stickc_plus2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_stickc_plus2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_stickc_plus2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_stickc_plus2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_stickc_plus2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_stickc_plus2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_stickc_plus2.menu.PartitionScheme.default.build.partitions=default
+m5stack_stickc_plus2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_stickc_plus2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_stickc_plus2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_stickc_plus2.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_stickc_plus2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_stickc_plus2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_stickc_plus2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_stickc_plus2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_stickc_plus2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_stickc_plus2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_stickc_plus2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_stickc_plus2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_stickc_plus2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_stickc_plus2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_stickc_plus2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_stickc_plus2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_stickc_plus2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_stickc_plus2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_stickc_plus2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_stickc_plus2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_stickc_plus2.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_stickc_plus2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_stickc_plus2.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_stickc_plus2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_stickc_plus2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_stickc_plus2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_stickc_plus2.menu.PartitionScheme.custom=Custom
+m5stack_stickc_plus2.menu.PartitionScheme.custom.build.partitions=
+m5stack_stickc_plus2.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_stickc_plus2.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_stickc_plus2.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_stickc_plus2.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_stickc_plus2.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_stickc_plus2.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_stickc_plus2.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_stickc_plus2.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_stickc_plus2.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_stickc_plus2.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_stickc_plus2.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_stickc_plus2.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_stickc_plus2.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_stickc_plus2.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_stickc_plus2.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_stickc_plus2.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_stickc_plus2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_stickc_plus2.menu.FlashMode.qio=QIO
+m5stack_stickc_plus2.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_stickc_plus2.menu.FlashMode.qio.build.boot=qio
+m5stack_stickc_plus2.menu.FlashMode.dio=DIO
+m5stack_stickc_plus2.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_stickc_plus2.menu.FlashMode.dio.build.boot=dio
+m5stack_stickc_plus2.menu.FlashMode.qout=QOUT
+m5stack_stickc_plus2.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_stickc_plus2.menu.FlashMode.qout.build.boot=qout
+m5stack_stickc_plus2.menu.FlashMode.dout=DOUT
+m5stack_stickc_plus2.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_stickc_plus2.menu.FlashMode.dout.build.boot=dout
+
+m5stack_stickc_plus2.menu.FlashFreq.80=80MHz
+m5stack_stickc_plus2.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_stickc_plus2.menu.FlashFreq.40=40MHz
+m5stack_stickc_plus2.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_stickc_plus2.menu.FlashSize.8M=8MB (64Mb)
+m5stack_stickc_plus2.menu.FlashSize.8M.build.flash_size=8MB
+
+m5stack_stickc_plus2.menu.UploadSpeed.1500000=1500000
+m5stack_stickc_plus2.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_stickc_plus2.menu.UploadSpeed.750000=750000
+m5stack_stickc_plus2.menu.UploadSpeed.750000.upload.speed=750000
+m5stack_stickc_plus2.menu.UploadSpeed.500000=500000
+m5stack_stickc_plus2.menu.UploadSpeed.500000.upload.speed=500000
+m5stack_stickc_plus2.menu.UploadSpeed.250000=250000
+m5stack_stickc_plus2.menu.UploadSpeed.250000.upload.speed=250000
+m5stack_stickc_plus2.menu.UploadSpeed.115200=115200
+m5stack_stickc_plus2.menu.UploadSpeed.115200.upload.speed=115200
+
+m5stack_stickc_plus2.menu.LoopCore.1=Core 1
+m5stack_stickc_plus2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_stickc_plus2.menu.LoopCore.0=Core 0
+m5stack_stickc_plus2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_stickc_plus2.menu.EventsCore.1=Core 1
+m5stack_stickc_plus2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_stickc_plus2.menu.EventsCore.0=Core 0
+m5stack_stickc_plus2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_stickc_plus2.menu.DebugLevel.none=None
+m5stack_stickc_plus2.menu.DebugLevel.none.build.code_debug=0
+m5stack_stickc_plus2.menu.DebugLevel.error=Error
+m5stack_stickc_plus2.menu.DebugLevel.error.build.code_debug=1
+m5stack_stickc_plus2.menu.DebugLevel.warn=Warn
+m5stack_stickc_plus2.menu.DebugLevel.warn.build.code_debug=2
+m5stack_stickc_plus2.menu.DebugLevel.info=Info
+m5stack_stickc_plus2.menu.DebugLevel.info.build.code_debug=3
+m5stack_stickc_plus2.menu.DebugLevel.debug=Debug
+m5stack_stickc_plus2.menu.DebugLevel.debug.build.code_debug=4
+m5stack_stickc_plus2.menu.DebugLevel.verbose=Verbose
+m5stack_stickc_plus2.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_stickc_plus2.menu.EraseFlash.none=Disabled
+m5stack_stickc_plus2.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_stickc_plus2.menu.EraseFlash.all=Enabled
+m5stack_stickc_plus2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_atom.name=M5Atom
+
+m5stack_atom.bootloader.tool=esptool_py
+m5stack_atom.bootloader.tool.default=esptool_py
+
+m5stack_atom.upload.tool=esptool_py
+m5stack_atom.upload.tool.default=esptool_py
+m5stack_atom.upload.tool.network=esp_ota
+
+m5stack_atom.upload.maximum_size=1310720
+m5stack_atom.upload.maximum_data_size=327680
+m5stack_atom.upload.flags=
+m5stack_atom.upload.extra_flags=
+
+m5stack_atom.serial.disableDTR=true
+m5stack_atom.serial.disableRTS=true
+
+m5stack_atom.build.tarch=xtensa
+m5stack_atom.build.bootloader_addr=0x1000
+m5stack_atom.build.target=esp32
+m5stack_atom.build.mcu=esp32
+m5stack_atom.build.core=esp32
+m5stack_atom.build.variant=m5stack_atom
+m5stack_atom.build.board=M5STACK_ATOM
+
+m5stack_atom.build.f_cpu=240000000L
+m5stack_atom.build.flash_size=4MB
+m5stack_atom.build.flash_freq=80m
+m5stack_atom.build.flash_mode=dio
+m5stack_atom.build.boot=dio
+m5stack_atom.build.partitions=huge_app
+m5stack_atom.build.defines=
+m5stack_atom.build.loop_core=
+m5stack_atom.build.event_core=
+
+m5stack_atom.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_atom.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_atom.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_atom.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_atom.menu.PartitionScheme.default.build.partitions=default
+m5stack_atom.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_atom.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_atom.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_atom.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_atom.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_atom.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_atom.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_atom.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_atom.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_atom.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_atom.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_atom.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_atom.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_atom.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_atom.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_atom.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_atom.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_atom.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_atom.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_atom.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_atom.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_atom.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_atom.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_atom.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_atom.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_atom.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_atom.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_atom.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_atom.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_atom.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_atom.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_atom.menu.PartitionScheme.custom=Custom
+m5stack_atom.menu.PartitionScheme.custom.build.partitions=
+m5stack_atom.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_atom.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_atom.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_atom.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_atom.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_atom.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_atom.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_atom.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_atom.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_atom.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_atom.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_atom.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_atom.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_atom.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_atom.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_atom.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_atom.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_atom.menu.FlashMode.qio=QIO
+m5stack_atom.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_atom.menu.FlashMode.qio.build.boot=qio
+m5stack_atom.menu.FlashMode.dio=DIO
+m5stack_atom.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_atom.menu.FlashMode.dio.build.boot=dio
+m5stack_atom.menu.FlashMode.qout=QOUT
+m5stack_atom.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_atom.menu.FlashMode.qout.build.boot=qout
+m5stack_atom.menu.FlashMode.dout=DOUT
+m5stack_atom.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_atom.menu.FlashMode.dout.build.boot=dout
+
+m5stack_atom.menu.FlashFreq.80=80MHz
+m5stack_atom.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_atom.menu.FlashFreq.40=40MHz
+m5stack_atom.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_atom.menu.FlashSize.4M=4MB (32Mb)
+m5stack_atom.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_atom.menu.UploadSpeed.1500000=1500000
+m5stack_atom.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_atom.menu.UploadSpeed.750000=750000
+m5stack_atom.menu.UploadSpeed.750000.upload.speed=750000
+m5stack_atom.menu.UploadSpeed.500000=500000
+m5stack_atom.menu.UploadSpeed.500000.upload.speed=500000
+m5stack_atom.menu.UploadSpeed.250000=250000
+m5stack_atom.menu.UploadSpeed.250000.upload.speed=250000
+m5stack_atom.menu.UploadSpeed.115200=115200
+m5stack_atom.menu.UploadSpeed.115200.upload.speed=115200
+
+m5stack_atom.menu.LoopCore.1=Core 1
+m5stack_atom.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_atom.menu.LoopCore.0=Core 0
+m5stack_atom.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_atom.menu.EventsCore.1=Core 1
+m5stack_atom.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_atom.menu.EventsCore.0=Core 0
+m5stack_atom.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_atom.menu.DebugLevel.none=None
+m5stack_atom.menu.DebugLevel.none.build.code_debug=0
+m5stack_atom.menu.DebugLevel.error=Error
+m5stack_atom.menu.DebugLevel.error.build.code_debug=1
+m5stack_atom.menu.DebugLevel.warn=Warn
+m5stack_atom.menu.DebugLevel.warn.build.code_debug=2
+m5stack_atom.menu.DebugLevel.info=Info
+m5stack_atom.menu.DebugLevel.info.build.code_debug=3
+m5stack_atom.menu.DebugLevel.debug=Debug
+m5stack_atom.menu.DebugLevel.debug.build.code_debug=4
+m5stack_atom.menu.DebugLevel.verbose=Verbose
+m5stack_atom.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_atom.menu.EraseFlash.none=Disabled
+m5stack_atom.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_atom.menu.EraseFlash.all=Enabled
+m5stack_atom.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_atoms3.name=M5AtomS3
+m5stack_atoms3.bootloader.tool=esptool_py
+m5stack_atoms3.bootloader.tool.default=esptool_py
+
+m5stack_atoms3.upload.tool=esptool_py
+m5stack_atoms3.upload.tool.default=esptool_py
+m5stack_atoms3.upload.tool.network=esp_ota
+
+m5stack_atoms3.upload.maximum_size=1310720
+m5stack_atoms3.upload.maximum_data_size=327680
+m5stack_atoms3.upload.flags=
+m5stack_atoms3.upload.extra_flags=
+m5stack_atoms3.upload.use_1200bps_touch=false
+m5stack_atoms3.upload.wait_for_upload_port=false
+
+m5stack_atoms3.serial.disableDTR=false
+m5stack_atoms3.serial.disableRTS=false
+
+m5stack_atoms3.build.tarch=xtensa
+m5stack_atoms3.build.bootloader_addr=0x0
+m5stack_atoms3.build.target=esp32s3
+m5stack_atoms3.build.mcu=esp32s3
+m5stack_atoms3.build.core=esp32
+m5stack_atoms3.build.variant=m5stack_atoms3
+m5stack_atoms3.build.board=M5STACK_ATOMS3
+
+m5stack_atoms3.build.usb_mode=1
+m5stack_atoms3.build.cdc_on_boot=1
+m5stack_atoms3.build.msc_on_boot=0
+m5stack_atoms3.build.dfu_on_boot=0
+m5stack_atoms3.build.f_cpu=240000000L
+m5stack_atoms3.build.flash_size=8MB
+m5stack_atoms3.build.flash_freq=80m
+m5stack_atoms3.build.flash_mode=dio
+m5stack_atoms3.build.boot=qio
+m5stack_atoms3.build.boot_freq=80m
+m5stack_atoms3.build.partitions=default
+m5stack_atoms3.build.defines=
+m5stack_atoms3.build.loop_core=
+m5stack_atoms3.build.event_core=
+m5stack_atoms3.build.psram_type=qspi
+m5stack_atoms3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+m5stack_atoms3.menu.JTAGAdapter.default=Disabled
+m5stack_atoms3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_atoms3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_atoms3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+m5stack_atoms3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_atoms3.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_atoms3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+m5stack_atoms3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_atoms3.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_atoms3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+m5stack_atoms3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_atoms3.menu.PSRAM.disabled=Disabled
+m5stack_atoms3.menu.PSRAM.disabled.build.defines=
+m5stack_atoms3.menu.PSRAM.disabled.build.psram_type=qspi
+m5stack_atoms3.menu.PSRAM.enabled=QSPI PSRAM
+m5stack_atoms3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+m5stack_atoms3.menu.PSRAM.enabled.build.psram_type=qspi
+m5stack_atoms3.menu.PSRAM.opi=OPI PSRAM
+m5stack_atoms3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+m5stack_atoms3.menu.PSRAM.opi.build.psram_type=opi
+
+m5stack_atoms3.menu.FlashMode.qio=QIO 80MHz
+m5stack_atoms3.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_atoms3.menu.FlashMode.qio.build.boot=qio
+m5stack_atoms3.menu.FlashMode.qio.build.boot_freq=80m
+m5stack_atoms3.menu.FlashMode.qio.build.flash_freq=80m
+m5stack_atoms3.menu.FlashMode.qio120=QIO 120MHz
+m5stack_atoms3.menu.FlashMode.qio120.build.flash_mode=dio
+m5stack_atoms3.menu.FlashMode.qio120.build.boot=qio
+m5stack_atoms3.menu.FlashMode.qio120.build.boot_freq=120m
+m5stack_atoms3.menu.FlashMode.qio120.build.flash_freq=80m
+m5stack_atoms3.menu.FlashMode.dio=DIO 80MHz
+m5stack_atoms3.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_atoms3.menu.FlashMode.dio.build.boot=dio
+m5stack_atoms3.menu.FlashMode.dio.build.boot_freq=80m
+m5stack_atoms3.menu.FlashMode.dio.build.flash_freq=80m
+m5stack_atoms3.menu.FlashMode.opi=OPI 80MHz
+m5stack_atoms3.menu.FlashMode.opi.build.flash_mode=dout
+m5stack_atoms3.menu.FlashMode.opi.build.boot=opi
+m5stack_atoms3.menu.FlashMode.opi.build.boot_freq=80m
+m5stack_atoms3.menu.FlashMode.opi.build.flash_freq=80m
+
+
+m5stack_atoms3.menu.FlashSize.8M=8MB (64Mb)
+m5stack_atoms3.menu.FlashSize.8M.build.flash_size=8MB
+
+m5stack_atoms3.menu.LoopCore.1=Core 1
+m5stack_atoms3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_atoms3.menu.LoopCore.0=Core 0
+m5stack_atoms3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_atoms3.menu.EventsCore.1=Core 1
+m5stack_atoms3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_atoms3.menu.EventsCore.0=Core 0
+m5stack_atoms3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_atoms3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+m5stack_atoms3.menu.USBMode.hwcdc.build.usb_mode=1
+m5stack_atoms3.menu.USBMode.default=USB-OTG (TinyUSB)
+m5stack_atoms3.menu.USBMode.default.build.usb_mode=0
+
+m5stack_atoms3.menu.CDCOnBoot.cdc=Enabled
+m5stack_atoms3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_atoms3.menu.CDCOnBoot.default=Disabled
+m5stack_atoms3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+m5stack_atoms3.menu.MSCOnBoot.default=Disabled
+m5stack_atoms3.menu.MSCOnBoot.default.build.msc_on_boot=0
+m5stack_atoms3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+m5stack_atoms3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+m5stack_atoms3.menu.DFUOnBoot.default=Disabled
+m5stack_atoms3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+m5stack_atoms3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+m5stack_atoms3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+m5stack_atoms3.menu.UploadMode.default=UART0 / Hardware CDC
+m5stack_atoms3.menu.UploadMode.default.upload.use_1200bps_touch=false
+m5stack_atoms3.menu.UploadMode.default.upload.wait_for_upload_port=false
+m5stack_atoms3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+m5stack_atoms3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+m5stack_atoms3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+m5stack_atoms3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_atoms3.menu.PartitionScheme.default.build.partitions=default
+m5stack_atoms3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_atoms3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_atoms3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_atoms3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_atoms3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_atoms3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_atoms3.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_atoms3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_atoms3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_atoms3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_atoms3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_atoms3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_atoms3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_atoms3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_atoms3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_atoms3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_atoms3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_atoms3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_atoms3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_atoms3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_atoms3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_atoms3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_atoms3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_atoms3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_atoms3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_atoms3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_atoms3.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_atoms3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_atoms3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_atoms3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_atoms3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_atoms3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_atoms3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_atoms3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_atoms3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_atoms3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_atoms3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_atoms3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_atoms3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_atoms3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_atoms3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+m5stack_atoms3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+m5stack_atoms3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+m5stack_atoms3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+m5stack_atoms3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+m5stack_atoms3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+m5stack_atoms3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+m5stack_atoms3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+m5stack_atoms3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+m5stack_atoms3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+m5stack_atoms3.menu.PartitionScheme.custom=Custom
+m5stack_atoms3.menu.PartitionScheme.custom.build.partitions=
+m5stack_atoms3.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_atoms3.menu.CPUFreq.240=240MHz (WiFi)
+m5stack_atoms3.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_atoms3.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_atoms3.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_atoms3.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_atoms3.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_atoms3.menu.CPUFreq.40=40MHz
+m5stack_atoms3.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_atoms3.menu.CPUFreq.20=20MHz
+m5stack_atoms3.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_atoms3.menu.CPUFreq.10=10MHz
+m5stack_atoms3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_atoms3.menu.UploadSpeed.921600=921600
+m5stack_atoms3.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_atoms3.menu.UploadSpeed.115200=115200
+m5stack_atoms3.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_atoms3.menu.UploadSpeed.256000.windows=256000
+m5stack_atoms3.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_atoms3.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_atoms3.menu.UploadSpeed.230400=230400
+m5stack_atoms3.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_atoms3.menu.UploadSpeed.460800.linux=460800
+m5stack_atoms3.menu.UploadSpeed.460800.macosx=460800
+m5stack_atoms3.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_atoms3.menu.UploadSpeed.512000.windows=512000
+m5stack_atoms3.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_atoms3.menu.DebugLevel.none=None
+m5stack_atoms3.menu.DebugLevel.none.build.code_debug=0
+m5stack_atoms3.menu.DebugLevel.error=Error
+m5stack_atoms3.menu.DebugLevel.error.build.code_debug=1
+m5stack_atoms3.menu.DebugLevel.warn=Warn
+m5stack_atoms3.menu.DebugLevel.warn.build.code_debug=2
+m5stack_atoms3.menu.DebugLevel.info=Info
+m5stack_atoms3.menu.DebugLevel.info.build.code_debug=3
+m5stack_atoms3.menu.DebugLevel.debug=Debug
+m5stack_atoms3.menu.DebugLevel.debug.build.code_debug=4
+m5stack_atoms3.menu.DebugLevel.verbose=Verbose
+m5stack_atoms3.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_atoms3.menu.EraseFlash.none=Disabled
+m5stack_atoms3.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_atoms3.menu.EraseFlash.all=Enabled
+m5stack_atoms3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_cores3.name=M5CoreS3
+m5stack_cores3.bootloader.tool=esptool_py
+m5stack_cores3.bootloader.tool.default=esptool_py
+
+m5stack_cores3.upload.tool=esptool_py
+m5stack_cores3.upload.tool.default=esptool_py
+m5stack_cores3.upload.tool.network=esp_ota
+
+m5stack_cores3.upload.maximum_size=1310720
+m5stack_cores3.upload.maximum_data_size=327680
+m5stack_cores3.upload.flags=
+m5stack_cores3.upload.extra_flags=
+m5stack_cores3.upload.use_1200bps_touch=false
+m5stack_cores3.upload.wait_for_upload_port=false
+
+m5stack_cores3.serial.disableDTR=false
+m5stack_cores3.serial.disableRTS=false
+
+m5stack_cores3.build.tarch=xtensa
+m5stack_cores3.build.bootloader_addr=0x0
+m5stack_cores3.build.target=esp32s3
+m5stack_cores3.build.mcu=esp32s3
+m5stack_cores3.build.core=esp32
+m5stack_cores3.build.variant=m5stack_cores3
+m5stack_cores3.build.board=M5STACK_CORES3
+
+m5stack_cores3.build.usb_mode=1
+m5stack_cores3.build.cdc_on_boot=1
+m5stack_cores3.build.msc_on_boot=0
+m5stack_cores3.build.dfu_on_boot=0
+m5stack_cores3.build.f_cpu=240000000L
+m5stack_cores3.build.flash_size=16MB
+m5stack_cores3.build.flash_freq=80m
+m5stack_cores3.build.flash_mode=dio
+m5stack_cores3.build.boot=qio
+m5stack_cores3.build.boot_freq=80m
+m5stack_cores3.build.partitions=default
+m5stack_cores3.build.defines=
+m5stack_cores3.build.loop_core=
+m5stack_cores3.build.event_core=
+m5stack_cores3.build.psram_type=qspi
+m5stack_cores3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+m5stack_cores3.menu.JTAGAdapter.default=Disabled
+m5stack_cores3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_cores3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_cores3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+m5stack_cores3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_cores3.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_cores3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+m5stack_cores3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_cores3.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_cores3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+m5stack_cores3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_cores3.menu.PSRAM.enabled=QSPI PSRAM
+m5stack_cores3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+m5stack_cores3.menu.PSRAM.enabled.build.psram_type=qspi
+m5stack_cores3.menu.PSRAM.disabled=Disabled
+m5stack_cores3.menu.PSRAM.disabled.build.defines=
+m5stack_cores3.menu.PSRAM.disabled.build.psram_type=qspi
+m5stack_cores3.menu.PSRAM.opi=OPI PSRAM
+m5stack_cores3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+m5stack_cores3.menu.PSRAM.opi.build.psram_type=opi
+
+m5stack_cores3.menu.FlashMode.qio=QIO 80MHz
+m5stack_cores3.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_cores3.menu.FlashMode.qio.build.boot=qio
+m5stack_cores3.menu.FlashMode.qio.build.boot_freq=80m
+m5stack_cores3.menu.FlashMode.qio.build.flash_freq=80m
+m5stack_cores3.menu.FlashMode.qio120=QIO 120MHz
+m5stack_cores3.menu.FlashMode.qio120.build.flash_mode=dio
+m5stack_cores3.menu.FlashMode.qio120.build.boot=qio
+m5stack_cores3.menu.FlashMode.qio120.build.boot_freq=120m
+m5stack_cores3.menu.FlashMode.qio120.build.flash_freq=80m
+m5stack_cores3.menu.FlashMode.dio=DIO 80MHz
+m5stack_cores3.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_cores3.menu.FlashMode.dio.build.boot=dio
+m5stack_cores3.menu.FlashMode.dio.build.boot_freq=80m
+m5stack_cores3.menu.FlashMode.dio.build.flash_freq=80m
+m5stack_cores3.menu.FlashMode.opi=OPI 80MHz
+m5stack_cores3.menu.FlashMode.opi.build.flash_mode=dout
+m5stack_cores3.menu.FlashMode.opi.build.boot=opi
+m5stack_cores3.menu.FlashMode.opi.build.boot_freq=80m
+m5stack_cores3.menu.FlashMode.opi.build.flash_freq=80m
+
+m5stack_cores3.menu.FlashSize.16M=16MB (128Mb)
+m5stack_cores3.menu.FlashSize.16M.build.flash_size=16MB
+m5stack_cores3.menu.FlashSize.32M=32MB (256Mb)
+m5stack_cores3.menu.FlashSize.32M.build.flash_size=32MB
+
+m5stack_cores3.menu.LoopCore.1=Core 1
+m5stack_cores3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_cores3.menu.LoopCore.0=Core 0
+m5stack_cores3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_cores3.menu.EventsCore.1=Core 1
+m5stack_cores3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_cores3.menu.EventsCore.0=Core 0
+m5stack_cores3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_cores3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+m5stack_cores3.menu.USBMode.hwcdc.build.usb_mode=1
+m5stack_cores3.menu.USBMode.default=USB-OTG (TinyUSB)
+m5stack_cores3.menu.USBMode.default.build.usb_mode=0
+
+m5stack_cores3.menu.CDCOnBoot.cdc=Enabled
+m5stack_cores3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_cores3.menu.CDCOnBoot.default=Disabled
+m5stack_cores3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+m5stack_cores3.menu.MSCOnBoot.default=Disabled
+m5stack_cores3.menu.MSCOnBoot.default.build.msc_on_boot=0
+m5stack_cores3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+m5stack_cores3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+m5stack_cores3.menu.DFUOnBoot.default=Disabled
+m5stack_cores3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+m5stack_cores3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+m5stack_cores3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+m5stack_cores3.menu.UploadMode.default=UART0 / Hardware CDC
+m5stack_cores3.menu.UploadMode.default.upload.use_1200bps_touch=false
+m5stack_cores3.menu.UploadMode.default.upload.wait_for_upload_port=false
+m5stack_cores3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+m5stack_cores3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+m5stack_cores3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+m5stack_cores3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_cores3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_cores3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_cores3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_cores3.menu.PartitionScheme.default.build.partitions=default
+m5stack_cores3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_cores3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_cores3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_cores3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_cores3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_cores3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_cores3.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_cores3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_cores3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_cores3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_cores3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_cores3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_cores3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_cores3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_cores3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_cores3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_cores3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_cores3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_cores3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_cores3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_cores3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_cores3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_cores3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_cores3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_cores3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_cores3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_cores3.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_cores3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_cores3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_cores3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_cores3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_cores3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_cores3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_cores3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_cores3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_cores3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_cores3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_cores3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+m5stack_cores3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+m5stack_cores3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+m5stack_cores3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+m5stack_cores3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+m5stack_cores3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+m5stack_cores3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+m5stack_cores3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+m5stack_cores3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+m5stack_cores3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+m5stack_cores3.menu.PartitionScheme.custom=Custom
+m5stack_cores3.menu.PartitionScheme.custom.build.partitions=
+m5stack_cores3.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_cores3.menu.PartitionScheme.factory_4apps=16MB+Factory (4x 3MB APP/2MB SPIFFS)
+m5stack_cores3.menu.PartitionScheme.factory_4apps.build.custom_partitions=m5stack_partitions_16MB_factory_4_apps
+m5stack_cores3.menu.PartitionScheme.factory_4apps.upload.maximum_size=3145728
+m5stack_cores3.menu.PartitionScheme.factory_6apps=16MB+Factory (6x 2MB APP/2MB SPIFFS)
+m5stack_cores3.menu.PartitionScheme.factory_6apps.build.custom_partitions=m5stack_partitions_16MB_factory_6_apps
+m5stack_cores3.menu.PartitionScheme.factory_6apps.upload.maximum_size=2097152
+
+m5stack_cores3.menu.CPUFreq.240=240MHz (WiFi)
+m5stack_cores3.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_cores3.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_cores3.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_cores3.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_cores3.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_cores3.menu.CPUFreq.40=40MHz
+m5stack_cores3.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_cores3.menu.CPUFreq.20=20MHz
+m5stack_cores3.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_cores3.menu.CPUFreq.10=10MHz
+m5stack_cores3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_cores3.menu.UploadSpeed.921600=921600
+m5stack_cores3.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_cores3.menu.UploadSpeed.115200=115200
+m5stack_cores3.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_cores3.menu.UploadSpeed.256000.windows=256000
+m5stack_cores3.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_cores3.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_cores3.menu.UploadSpeed.230400=230400
+m5stack_cores3.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_cores3.menu.UploadSpeed.460800.linux=460800
+m5stack_cores3.menu.UploadSpeed.460800.macosx=460800
+m5stack_cores3.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_cores3.menu.UploadSpeed.512000.windows=512000
+m5stack_cores3.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_cores3.menu.DebugLevel.none=None
+m5stack_cores3.menu.DebugLevel.none.build.code_debug=0
+m5stack_cores3.menu.DebugLevel.error=Error
+m5stack_cores3.menu.DebugLevel.error.build.code_debug=1
+m5stack_cores3.menu.DebugLevel.warn=Warn
+m5stack_cores3.menu.DebugLevel.warn.build.code_debug=2
+m5stack_cores3.menu.DebugLevel.info=Info
+m5stack_cores3.menu.DebugLevel.info.build.code_debug=3
+m5stack_cores3.menu.DebugLevel.debug=Debug
+m5stack_cores3.menu.DebugLevel.debug.build.code_debug=4
+m5stack_cores3.menu.DebugLevel.verbose=Verbose
+m5stack_cores3.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_cores3.menu.EraseFlash.none=Disabled
+m5stack_cores3.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_cores3.menu.EraseFlash.all=Enabled
+m5stack_cores3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_timer_cam.name=M5TimerCAM
+
+m5stack_timer_cam.bootloader.tool=esptool_py
+m5stack_timer_cam.bootloader.tool.default=esptool_py
+
+m5stack_timer_cam.upload.tool=esptool_py
+m5stack_timer_cam.upload.tool.default=esptool_py
+m5stack_timer_cam.upload.tool.network=esp_ota
+
+m5stack_timer_cam.upload.maximum_size=1310720
+m5stack_timer_cam.upload.maximum_data_size=327680
+
+m5stack_timer_cam.upload.flags=
+m5stack_timer_cam.upload.extra_flags=
+
+m5stack_timer_cam.serial.disableDTR=true
+m5stack_timer_cam.serial.disableRTS=true
+
+m5stack_timer_cam.build.tarch=xtensa
+m5stack_timer_cam.build.bootloader_addr=0x1000
+m5stack_timer_cam.build.target=esp32
+m5stack_timer_cam.build.mcu=esp32
+m5stack_timer_cam.build.core=esp32
+m5stack_timer_cam.build.variant=m5stack_timer_cam
+m5stack_timer_cam.build.board=M5STACK_TIMER_CAM
+
+m5stack_timer_cam.build.f_cpu=240000000L
+m5stack_timer_cam.build.flash_size=4MB
+m5stack_timer_cam.build.flash_freq=80m
+m5stack_timer_cam.build.flash_mode=dio
+m5stack_timer_cam.build.boot=dio
+m5stack_timer_cam.build.partitions=default
+m5stack_timer_cam.build.defines=
+m5stack_timer_cam.build.loop_core=
+m5stack_timer_cam.build.event_core=
+
+m5stack_timer_cam.menu.PSRAM.enabled=Enabled
+m5stack_timer_cam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+m5stack_timer_cam.menu.PSRAM.enabled.build.extra_libs=
+m5stack_timer_cam.menu.PSRAM.disabled=Disabled
+m5stack_timer_cam.menu.PSRAM.disabled.build.defines=
+m5stack_timer_cam.menu.PSRAM.disabled.build.extra_libs=
+
+m5stack_timer_cam.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_timer_cam.menu.PartitionScheme.default.build.partitions=default
+m5stack_timer_cam.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_timer_cam.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_timer_cam.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_timer_cam.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_timer_cam.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_timer_cam.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_timer_cam.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_timer_cam.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_timer_cam.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_timer_cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_timer_cam.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_timer_cam.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_timer_cam.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_timer_cam.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_timer_cam.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_timer_cam.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_timer_cam.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_timer_cam.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_timer_cam.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_timer_cam.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_timer_cam.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_timer_cam.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_timer_cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_timer_cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_timer_cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+m5stack_timer_cam.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_timer_cam.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_timer_cam.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_timer_cam.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_timer_cam.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_timer_cam.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_timer_cam.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_timer_cam.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_timer_cam.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_timer_cam.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_timer_cam.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_timer_cam.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_timer_cam.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_timer_cam.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_timer_cam.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_timer_cam.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_timer_cam.menu.FlashMode.qio=QIO
+m5stack_timer_cam.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_timer_cam.menu.FlashMode.qio.build.boot=qio
+m5stack_timer_cam.menu.FlashMode.dio=DIO
+m5stack_timer_cam.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_timer_cam.menu.FlashMode.dio.build.boot=dio
+m5stack_timer_cam.menu.FlashMode.qout=QOUT
+m5stack_timer_cam.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_timer_cam.menu.FlashMode.qout.build.boot=qout
+m5stack_timer_cam.menu.FlashMode.dout=DOUT
+m5stack_timer_cam.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_timer_cam.menu.FlashMode.dout.build.boot=dout
+
+m5stack_timer_cam.menu.FlashFreq.80=80MHz
+m5stack_timer_cam.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_timer_cam.menu.FlashFreq.40=40MHz
+m5stack_timer_cam.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_timer_cam.menu.FlashSize.4M=4MB (32Mb)
+m5stack_timer_cam.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_timer_cam.menu.UploadSpeed.1500000=1500000
+m5stack_timer_cam.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_timer_cam.menu.UploadSpeed.750000=750000
+m5stack_timer_cam.menu.UploadSpeed.750000.upload.speed=750000
+m5stack_timer_cam.menu.UploadSpeed.500000=500000
+m5stack_timer_cam.menu.UploadSpeed.500000.upload.speed=500000
+m5stack_timer_cam.menu.UploadSpeed.250000=250000
+m5stack_timer_cam.menu.UploadSpeed.250000.upload.speed=250000
+m5stack_timer_cam.menu.UploadSpeed.115200=115200
+m5stack_timer_cam.menu.UploadSpeed.115200.upload.speed=115200
+
+m5stack_timer_cam.menu.LoopCore.1=Core 1
+m5stack_timer_cam.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_timer_cam.menu.LoopCore.0=Core 0
+m5stack_timer_cam.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_timer_cam.menu.EventsCore.1=Core 1
+m5stack_timer_cam.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_timer_cam.menu.EventsCore.0=Core 0
+m5stack_timer_cam.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_timer_cam.menu.DebugLevel.none=None
+m5stack_timer_cam.menu.DebugLevel.none.build.code_debug=0
+m5stack_timer_cam.menu.DebugLevel.error=Error
+m5stack_timer_cam.menu.DebugLevel.error.build.code_debug=1
+m5stack_timer_cam.menu.DebugLevel.warn=Warn
+m5stack_timer_cam.menu.DebugLevel.warn.build.code_debug=2
+m5stack_timer_cam.menu.DebugLevel.info=Info
+m5stack_timer_cam.menu.DebugLevel.info.build.code_debug=3
+m5stack_timer_cam.menu.DebugLevel.debug=Debug
+m5stack_timer_cam.menu.DebugLevel.debug.build.code_debug=4
+m5stack_timer_cam.menu.DebugLevel.verbose=Verbose
+m5stack_timer_cam.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_timer_cam.menu.EraseFlash.none=Disabled
+m5stack_timer_cam.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_timer_cam.menu.EraseFlash.all=Enabled
+m5stack_timer_cam.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+
+m5stack_unit_cam.name=M5UnitCAM
+
+m5stack_unit_cam.bootloader.tool=esptool_py
+m5stack_unit_cam.bootloader.tool.default=esptool_py
+
+m5stack_unit_cam.upload.tool=esptool_py
+m5stack_unit_cam.upload.tool.default=esptool_py
+m5stack_unit_cam.upload.tool.network=esp_ota
+
+m5stack_unit_cam.upload.maximum_size=1310720
+m5stack_unit_cam.upload.maximum_data_size=327680
+
+m5stack_unit_cam.upload.flags=
+m5stack_unit_cam.upload.extra_flags=
+
+m5stack_unit_cam.serial.disableDTR=true
+m5stack_unit_cam.serial.disableRTS=true
+
+m5stack_unit_cam.build.tarch=xtensa
+m5stack_unit_cam.build.bootloader_addr=0x1000
+m5stack_unit_cam.build.target=esp32
+m5stack_unit_cam.build.mcu=esp32
+m5stack_unit_cam.build.core=esp32
+m5stack_unit_cam.build.variant=m5stack_unit_cam
+m5stack_unit_cam.build.board=M5STACK_UNIT_CAM
+
+m5stack_unit_cam.build.f_cpu=240000000L
+m5stack_unit_cam.build.flash_size=4MB
+m5stack_unit_cam.build.flash_freq=80m
+m5stack_unit_cam.build.flash_mode=dio
+m5stack_unit_cam.build.boot=dio
+m5stack_unit_cam.build.partitions=default
+m5stack_unit_cam.build.defines=
+m5stack_unit_cam.build.loop_core=
+m5stack_unit_cam.build.event_core=
+
+m5stack_unit_cam.menu.PSRAM.enabled=Enabled
+m5stack_unit_cam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+m5stack_unit_cam.menu.PSRAM.enabled.build.extra_libs=
+m5stack_unit_cam.menu.PSRAM.disabled=Disabled
+m5stack_unit_cam.menu.PSRAM.disabled.build.defines=
+m5stack_unit_cam.menu.PSRAM.disabled.build.extra_libs=
+
+m5stack_unit_cam.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_unit_cam.menu.PartitionScheme.default.build.partitions=default
+m5stack_unit_cam.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_unit_cam.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_unit_cam.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_unit_cam.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_unit_cam.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_unit_cam.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_unit_cam.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_unit_cam.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_unit_cam.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_unit_cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_unit_cam.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_unit_cam.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_unit_cam.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_unit_cam.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_unit_cam.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_unit_cam.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_unit_cam.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_unit_cam.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_unit_cam.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_unit_cam.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_unit_cam.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_unit_cam.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_unit_cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_unit_cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_unit_cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+m5stack_unit_cam.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_unit_cam.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_unit_cam.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_unit_cam.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_unit_cam.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_unit_cam.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_unit_cam.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_unit_cam.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_unit_cam.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_unit_cam.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_unit_cam.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_unit_cam.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_unit_cam.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_unit_cam.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_unit_cam.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_unit_cam.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_unit_cam.menu.FlashMode.qio=QIO
+m5stack_unit_cam.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_unit_cam.menu.FlashMode.qio.build.boot=qio
+m5stack_unit_cam.menu.FlashMode.dio=DIO
+m5stack_unit_cam.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_unit_cam.menu.FlashMode.dio.build.boot=dio
+m5stack_unit_cam.menu.FlashMode.qout=QOUT
+m5stack_unit_cam.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_unit_cam.menu.FlashMode.qout.build.boot=qout
+m5stack_unit_cam.menu.FlashMode.dout=DOUT
+m5stack_unit_cam.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_unit_cam.menu.FlashMode.dout.build.boot=dout
+
+m5stack_unit_cam.menu.FlashFreq.80=80MHz
+m5stack_unit_cam.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_unit_cam.menu.FlashFreq.40=40MHz
+m5stack_unit_cam.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_unit_cam.menu.FlashSize.4M=4MB (32Mb)
+m5stack_unit_cam.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_unit_cam.menu.UploadSpeed.1500000=1500000
+m5stack_unit_cam.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_unit_cam.menu.UploadSpeed.750000=750000
+m5stack_unit_cam.menu.UploadSpeed.750000.upload.speed=750000
+m5stack_unit_cam.menu.UploadSpeed.500000=500000
+m5stack_unit_cam.menu.UploadSpeed.500000.upload.speed=500000
+m5stack_unit_cam.menu.UploadSpeed.250000=250000
+m5stack_unit_cam.menu.UploadSpeed.250000.upload.speed=250000
+m5stack_unit_cam.menu.UploadSpeed.115200=115200
+m5stack_unit_cam.menu.UploadSpeed.115200.upload.speed=115200
+
+m5stack_unit_cam.menu.LoopCore.1=Core 1
+m5stack_unit_cam.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_unit_cam.menu.LoopCore.0=Core 0
+m5stack_unit_cam.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_unit_cam.menu.EventsCore.1=Core 1
+m5stack_unit_cam.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_unit_cam.menu.EventsCore.0=Core 0
+m5stack_unit_cam.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_unit_cam.menu.DebugLevel.none=None
+m5stack_unit_cam.menu.DebugLevel.none.build.code_debug=0
+m5stack_unit_cam.menu.DebugLevel.error=Error
+m5stack_unit_cam.menu.DebugLevel.error.build.code_debug=1
+m5stack_unit_cam.menu.DebugLevel.warn=Warn
+m5stack_unit_cam.menu.DebugLevel.warn.build.code_debug=2
+m5stack_unit_cam.menu.DebugLevel.info=Info
+m5stack_unit_cam.menu.DebugLevel.info.build.code_debug=3
+m5stack_unit_cam.menu.DebugLevel.debug=Debug
+m5stack_unit_cam.menu.DebugLevel.debug.build.code_debug=4
+m5stack_unit_cam.menu.DebugLevel.verbose=Verbose
+m5stack_unit_cam.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_unit_cam.menu.EraseFlash.none=Disabled
+m5stack_unit_cam.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_unit_cam.menu.EraseFlash.all=Enabled
+m5stack_unit_cam.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+
+m5stack_unit_cams3.name=M5UnitCAMS3
+m5stack_unit_cams3.bootloader.tool=esptool_py
+m5stack_unit_cams3.bootloader.tool.default=esptool_py
+
+m5stack_unit_cams3.upload.tool=esptool_py
+m5stack_unit_cams3.upload.tool.default=esptool_py
+m5stack_unit_cams3.upload.tool.network=esp_ota
+
+m5stack_unit_cams3.upload.maximum_size=1310720
+m5stack_unit_cams3.upload.maximum_data_size=327680
+m5stack_unit_cams3.upload.flags=
+m5stack_unit_cams3.upload.extra_flags=
+m5stack_unit_cams3.upload.use_1200bps_touch=false
+m5stack_unit_cams3.upload.wait_for_upload_port=false
+
+m5stack_unit_cams3.serial.disableDTR=false
+m5stack_unit_cams3.serial.disableRTS=false
+
+m5stack_unit_cams3.build.tarch=xtensa
+m5stack_unit_cams3.build.bootloader_addr=0x0
+m5stack_unit_cams3.build.target=esp32s3
+m5stack_unit_cams3.build.mcu=esp32s3
+m5stack_unit_cams3.build.core=esp32
+m5stack_unit_cams3.build.variant=m5stack_unit_cams3
+m5stack_unit_cams3.build.board=M5STACK_UNIT_CAMS3
+
+m5stack_unit_cams3.build.usb_mode=1
+m5stack_unit_cams3.build.cdc_on_boot=1
+m5stack_unit_cams3.build.msc_on_boot=0
+m5stack_unit_cams3.build.dfu_on_boot=0
+m5stack_unit_cams3.build.f_cpu=240000000L
+m5stack_unit_cams3.build.flash_size=16MB
+m5stack_unit_cams3.build.flash_freq=80m
+m5stack_unit_cams3.build.flash_mode=dio
+m5stack_unit_cams3.build.boot=qio
+m5stack_unit_cams3.build.boot_freq=80m
+m5stack_unit_cams3.build.partitions=default
+m5stack_unit_cams3.build.defines=
+m5stack_unit_cams3.build.loop_core=
+m5stack_unit_cams3.build.event_core=
+m5stack_unit_cams3.build.psram_type=qspi
+m5stack_unit_cams3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+m5stack_unit_cams3.menu.JTAGAdapter.default=Disabled
+m5stack_unit_cams3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_unit_cams3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_unit_cams3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+m5stack_unit_cams3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_unit_cams3.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_unit_cams3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+m5stack_unit_cams3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_unit_cams3.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_unit_cams3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+m5stack_unit_cams3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_unit_cams3.menu.PSRAM.enabled=QSPI PSRAM
+m5stack_unit_cams3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+m5stack_unit_cams3.menu.PSRAM.enabled.build.psram_type=qspi
+m5stack_unit_cams3.menu.PSRAM.disabled=Disabled
+m5stack_unit_cams3.menu.PSRAM.disabled.build.defines=
+m5stack_unit_cams3.menu.PSRAM.disabled.build.psram_type=qspi
+m5stack_unit_cams3.menu.PSRAM.opi=OPI PSRAM
+m5stack_unit_cams3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+m5stack_unit_cams3.menu.PSRAM.opi.build.psram_type=opi
+
+m5stack_unit_cams3.menu.FlashMode.qio=QIO 80MHz
+m5stack_unit_cams3.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_unit_cams3.menu.FlashMode.qio.build.boot=qio
+m5stack_unit_cams3.menu.FlashMode.qio.build.boot_freq=80m
+m5stack_unit_cams3.menu.FlashMode.qio.build.flash_freq=80m
+m5stack_unit_cams3.menu.FlashMode.qio120=QIO 120MHz
+m5stack_unit_cams3.menu.FlashMode.qio120.build.flash_mode=dio
+m5stack_unit_cams3.menu.FlashMode.qio120.build.boot=qio
+m5stack_unit_cams3.menu.FlashMode.qio120.build.boot_freq=120m
+m5stack_unit_cams3.menu.FlashMode.qio120.build.flash_freq=80m
+m5stack_unit_cams3.menu.FlashMode.dio=DIO 80MHz
+m5stack_unit_cams3.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_unit_cams3.menu.FlashMode.dio.build.boot=dio
+m5stack_unit_cams3.menu.FlashMode.dio.build.boot_freq=80m
+m5stack_unit_cams3.menu.FlashMode.dio.build.flash_freq=80m
+m5stack_unit_cams3.menu.FlashMode.opi=OPI 80MHz
+m5stack_unit_cams3.menu.FlashMode.opi.build.flash_mode=dout
+m5stack_unit_cams3.menu.FlashMode.opi.build.boot=opi
+m5stack_unit_cams3.menu.FlashMode.opi.build.boot_freq=80m
+m5stack_unit_cams3.menu.FlashMode.opi.build.flash_freq=80m
+
+m5stack_unit_cams3.menu.FlashSize.16M=16MB (128Mb)
+m5stack_unit_cams3.menu.FlashSize.16M.build.flash_size=16MB
+m5stack_unit_cams3.menu.FlashSize.32M=32MB (256Mb)
+m5stack_unit_cams3.menu.FlashSize.32M.build.flash_size=32MB
+
+m5stack_unit_cams3.menu.LoopCore.1=Core 1
+m5stack_unit_cams3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_unit_cams3.menu.LoopCore.0=Core 0
+m5stack_unit_cams3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_unit_cams3.menu.EventsCore.1=Core 1
+m5stack_unit_cams3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_unit_cams3.menu.EventsCore.0=Core 0
+m5stack_unit_cams3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_unit_cams3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+m5stack_unit_cams3.menu.USBMode.hwcdc.build.usb_mode=1
+m5stack_unit_cams3.menu.USBMode.default=USB-OTG (TinyUSB)
+m5stack_unit_cams3.menu.USBMode.default.build.usb_mode=0
+
+m5stack_unit_cams3.menu.CDCOnBoot.cdc=Enabled
+m5stack_unit_cams3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_unit_cams3.menu.CDCOnBoot.default=Disabled
+m5stack_unit_cams3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+m5stack_unit_cams3.menu.MSCOnBoot.default=Disabled
+m5stack_unit_cams3.menu.MSCOnBoot.default.build.msc_on_boot=0
+m5stack_unit_cams3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+m5stack_unit_cams3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+m5stack_unit_cams3.menu.DFUOnBoot.default=Disabled
+m5stack_unit_cams3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+m5stack_unit_cams3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+m5stack_unit_cams3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+m5stack_unit_cams3.menu.UploadMode.default=UART0 / Hardware CDC
+m5stack_unit_cams3.menu.UploadMode.default.upload.use_1200bps_touch=false
+m5stack_unit_cams3.menu.UploadMode.default.upload.wait_for_upload_port=false
+m5stack_unit_cams3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+m5stack_unit_cams3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+m5stack_unit_cams3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+m5stack_unit_cams3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_unit_cams3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_unit_cams3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_unit_cams3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_unit_cams3.menu.PartitionScheme.default.build.partitions=default
+m5stack_unit_cams3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_unit_cams3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_unit_cams3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_unit_cams3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_unit_cams3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_unit_cams3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_unit_cams3.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_unit_cams3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_unit_cams3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_unit_cams3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_unit_cams3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_unit_cams3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_unit_cams3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_unit_cams3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_unit_cams3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_unit_cams3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_unit_cams3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_unit_cams3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_unit_cams3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_unit_cams3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_unit_cams3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_unit_cams3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_unit_cams3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_unit_cams3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_unit_cams3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_unit_cams3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_unit_cams3.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_unit_cams3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_unit_cams3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_unit_cams3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_unit_cams3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_unit_cams3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_unit_cams3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_unit_cams3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_unit_cams3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_unit_cams3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_unit_cams3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_unit_cams3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+m5stack_unit_cams3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+m5stack_unit_cams3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+m5stack_unit_cams3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+m5stack_unit_cams3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+m5stack_unit_cams3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+m5stack_unit_cams3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+m5stack_unit_cams3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+m5stack_unit_cams3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+m5stack_unit_cams3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+m5stack_unit_cams3.menu.PartitionScheme.custom=Custom
+m5stack_unit_cams3.menu.PartitionScheme.custom.build.partitions=
+m5stack_unit_cams3.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_unit_cams3.menu.CPUFreq.240=240MHz (WiFi)
+m5stack_unit_cams3.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_unit_cams3.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_unit_cams3.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_unit_cams3.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_unit_cams3.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_unit_cams3.menu.CPUFreq.40=40MHz
+m5stack_unit_cams3.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_unit_cams3.menu.CPUFreq.20=20MHz
+m5stack_unit_cams3.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_unit_cams3.menu.CPUFreq.10=10MHz
+m5stack_unit_cams3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_unit_cams3.menu.UploadSpeed.921600=921600
+m5stack_unit_cams3.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_unit_cams3.menu.UploadSpeed.115200=115200
+m5stack_unit_cams3.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_unit_cams3.menu.UploadSpeed.256000.windows=256000
+m5stack_unit_cams3.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_unit_cams3.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_unit_cams3.menu.UploadSpeed.230400=230400
+m5stack_unit_cams3.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_unit_cams3.menu.UploadSpeed.460800.linux=460800
+m5stack_unit_cams3.menu.UploadSpeed.460800.macosx=460800
+m5stack_unit_cams3.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_unit_cams3.menu.UploadSpeed.512000.windows=512000
+m5stack_unit_cams3.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_unit_cams3.menu.DebugLevel.none=None
+m5stack_unit_cams3.menu.DebugLevel.none.build.code_debug=0
+m5stack_unit_cams3.menu.DebugLevel.error=Error
+m5stack_unit_cams3.menu.DebugLevel.error.build.code_debug=1
+m5stack_unit_cams3.menu.DebugLevel.warn=Warn
+m5stack_unit_cams3.menu.DebugLevel.warn.build.code_debug=2
+m5stack_unit_cams3.menu.DebugLevel.info=Info
+m5stack_unit_cams3.menu.DebugLevel.info.build.code_debug=3
+m5stack_unit_cams3.menu.DebugLevel.debug=Debug
+m5stack_unit_cams3.menu.DebugLevel.debug.build.code_debug=4
+m5stack_unit_cams3.menu.DebugLevel.verbose=Verbose
+m5stack_unit_cams3.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_unit_cams3.menu.EraseFlash.none=Disabled
+m5stack_unit_cams3.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_unit_cams3.menu.EraseFlash.all=Enabled
+m5stack_unit_cams3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_poe_cam.name=M5PoECAM
+
+m5stack_poe_cam.bootloader.tool=esptool_py
+m5stack_poe_cam.bootloader.tool.default=esptool_py
+
+m5stack_poe_cam.upload.tool=esptool_py
+m5stack_poe_cam.upload.tool.default=esptool_py
+m5stack_poe_cam.upload.tool.network=esp_ota
+
+m5stack_poe_cam.upload.maximum_size=1310720
+m5stack_poe_cam.upload.maximum_data_size=327680
+
+m5stack_poe_cam.upload.flags=
+m5stack_poe_cam.upload.extra_flags=
+
+m5stack_poe_cam.serial.disableDTR=true
+m5stack_poe_cam.serial.disableRTS=true
+
+m5stack_poe_cam.build.tarch=xtensa
+m5stack_poe_cam.build.bootloader_addr=0x1000
+m5stack_poe_cam.build.target=esp32
+m5stack_poe_cam.build.mcu=esp32
+m5stack_poe_cam.build.core=esp32
+m5stack_poe_cam.build.variant=m5stack_poe_cam
+m5stack_poe_cam.build.board=M5STACK_POE_CAM
+
+m5stack_poe_cam.build.f_cpu=240000000L
+m5stack_poe_cam.build.flash_size=4MB
+m5stack_poe_cam.build.flash_freq=80m
+m5stack_poe_cam.build.flash_mode=dio
+m5stack_poe_cam.build.boot=dio
+m5stack_poe_cam.build.partitions=default
+m5stack_poe_cam.build.defines=
+m5stack_poe_cam.build.loop_core=
+m5stack_poe_cam.build.event_core=
+
+m5stack_poe_cam.menu.PSRAM.enabled=Enabled
+m5stack_poe_cam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+m5stack_poe_cam.menu.PSRAM.enabled.build.extra_libs=
+m5stack_poe_cam.menu.PSRAM.disabled=Disabled
+m5stack_poe_cam.menu.PSRAM.disabled.build.defines=
+m5stack_poe_cam.menu.PSRAM.disabled.build.extra_libs=
+
+m5stack_poe_cam.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_poe_cam.menu.PartitionScheme.default.build.partitions=default
+m5stack_poe_cam.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_poe_cam.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_poe_cam.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_poe_cam.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_poe_cam.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_poe_cam.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_poe_cam.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_poe_cam.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_poe_cam.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_poe_cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_poe_cam.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_poe_cam.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_poe_cam.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_poe_cam.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_poe_cam.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_poe_cam.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_poe_cam.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_poe_cam.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_poe_cam.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_poe_cam.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_poe_cam.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_poe_cam.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_poe_cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_poe_cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_poe_cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+m5stack_poe_cam.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_poe_cam.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_poe_cam.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_poe_cam.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_poe_cam.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_poe_cam.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_poe_cam.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_poe_cam.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_poe_cam.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_poe_cam.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_poe_cam.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_poe_cam.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_poe_cam.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_poe_cam.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_poe_cam.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_poe_cam.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_poe_cam.menu.FlashMode.qio=QIO
+m5stack_poe_cam.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_poe_cam.menu.FlashMode.qio.build.boot=qio
+m5stack_poe_cam.menu.FlashMode.dio=DIO
+m5stack_poe_cam.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_poe_cam.menu.FlashMode.dio.build.boot=dio
+m5stack_poe_cam.menu.FlashMode.qout=QOUT
+m5stack_poe_cam.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_poe_cam.menu.FlashMode.qout.build.boot=qout
+m5stack_poe_cam.menu.FlashMode.dout=DOUT
+m5stack_poe_cam.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_poe_cam.menu.FlashMode.dout.build.boot=dout
+
+m5stack_poe_cam.menu.FlashFreq.80=80MHz
+m5stack_poe_cam.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_poe_cam.menu.FlashFreq.40=40MHz
+m5stack_poe_cam.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_poe_cam.menu.FlashSize.4M=4MB (32Mb)
+m5stack_poe_cam.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_poe_cam.menu.UploadSpeed.1500000=1500000
+m5stack_poe_cam.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_poe_cam.menu.UploadSpeed.750000=750000
+m5stack_poe_cam.menu.UploadSpeed.750000.upload.speed=750000
+m5stack_poe_cam.menu.UploadSpeed.500000=500000
+m5stack_poe_cam.menu.UploadSpeed.500000.upload.speed=500000
+m5stack_poe_cam.menu.UploadSpeed.250000=250000
+m5stack_poe_cam.menu.UploadSpeed.250000.upload.speed=250000
+m5stack_poe_cam.menu.UploadSpeed.115200=115200
+m5stack_poe_cam.menu.UploadSpeed.115200.upload.speed=115200
+
+m5stack_poe_cam.menu.LoopCore.1=Core 1
+m5stack_poe_cam.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_poe_cam.menu.LoopCore.0=Core 0
+m5stack_poe_cam.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_poe_cam.menu.EventsCore.1=Core 1
+m5stack_poe_cam.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_poe_cam.menu.EventsCore.0=Core 0
+m5stack_poe_cam.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_poe_cam.menu.DebugLevel.none=None
+m5stack_poe_cam.menu.DebugLevel.none.build.code_debug=0
+m5stack_poe_cam.menu.DebugLevel.error=Error
+m5stack_poe_cam.menu.DebugLevel.error.build.code_debug=1
+m5stack_poe_cam.menu.DebugLevel.warn=Warn
+m5stack_poe_cam.menu.DebugLevel.warn.build.code_debug=2
+m5stack_poe_cam.menu.DebugLevel.info=Info
+m5stack_poe_cam.menu.DebugLevel.info.build.code_debug=3
+m5stack_poe_cam.menu.DebugLevel.debug=Debug
+m5stack_poe_cam.menu.DebugLevel.debug.build.code_debug=4
+m5stack_poe_cam.menu.DebugLevel.verbose=Verbose
+m5stack_poe_cam.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_poe_cam.menu.EraseFlash.none=Disabled
+m5stack_poe_cam.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_poe_cam.menu.EraseFlash.all=Enabled
+m5stack_poe_cam.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_paper.name=M5Paper
+
+m5stack_paper.bootloader.tool=esptool_py
+m5stack_paper.bootloader.tool.default=esptool_py
+
+m5stack_paper.upload.tool=esptool_py
+m5stack_paper.upload.tool.default=esptool_py
+m5stack_paper.upload.tool.network=esp_ota
+
+m5stack_paper.upload.maximum_size=6553600
+m5stack_paper.upload.maximum_data_size=4521984
+m5stack_paper.upload.flags=
+m5stack_paper.upload.extra_flags=
+
+m5stack_paper.serial.disableDTR=true
+m5stack_paper.serial.disableRTS=true
+
+m5stack_paper.build.tarch=xtensa
+m5stack_paper.build.bootloader_addr=0x1000
+m5stack_paper.build.target=esp32
+m5stack_paper.build.mcu=esp32
+m5stack_paper.build.core=esp32
+m5stack_paper.build.variant=m5stack_paper
+m5stack_paper.build.board=M5STACK_PAPER
+
+m5stack_paper.build.f_cpu=240000000L
+m5stack_paper.build.flash_size=16MB
+m5stack_paper.build.flash_freq=80m
+m5stack_paper.build.flash_mode=dio
+m5stack_paper.build.boot=dio
+m5stack_paper.build.partitions=default
+m5stack_paper.build.defines=
+m5stack_paper.build.loop_core=
+m5stack_paper.build.event_core=
+
+m5stack_paper.menu.PSRAM.enabled=Enabled
+m5stack_paper.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+m5stack_paper.menu.PSRAM.enabled.build.extra_libs=
+m5stack_paper.menu.PSRAM.disabled=Disabled
+m5stack_paper.menu.PSRAM.disabled.build.defines=
+m5stack_paper.menu.PSRAM.disabled.build.extra_libs=
+
+m5stack_paper.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS)
+m5stack_paper.menu.PartitionScheme.default.build.partitions=default_16MB
+m5stack_paper.menu.PartitionScheme.default.upload.maximum_size=6553600
+m5stack_paper.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_paper.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_paper.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_paper.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_paper.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_paper.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_paper.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_paper.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_paper.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_paper.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_paper.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_paper.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_paper.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_paper.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_paper.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_paper.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_paper.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_paper.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_paper.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_paper.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_paper.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_paper.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_paper.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_paper.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_paper.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_paper.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_paper.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_paper.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_paper.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_paper.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_paper.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_paper.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_paper.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_paper.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_paper.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_paper.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_paper.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_paper.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_paper.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_paper.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_paper.menu.PartitionScheme.custom=Custom
+m5stack_paper.menu.PartitionScheme.custom.build.partitions=
+m5stack_paper.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_paper.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_paper.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_paper.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_paper.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_paper.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_paper.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_paper.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_paper.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_paper.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_paper.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_paper.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_paper.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_paper.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_paper.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_paper.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_paper.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_paper.menu.FlashMode.qio=QIO
+m5stack_paper.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_paper.menu.FlashMode.qio.build.boot=qio
+m5stack_paper.menu.FlashMode.dio=DIO
+m5stack_paper.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_paper.menu.FlashMode.dio.build.boot=dio
+m5stack_paper.menu.FlashMode.qout=QOUT
+m5stack_paper.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_paper.menu.FlashMode.qout.build.boot=qout
+m5stack_paper.menu.FlashMode.dout=DOUT
+m5stack_paper.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_paper.menu.FlashMode.dout.build.boot=dout
+
+m5stack_paper.menu.FlashFreq.80=80MHz
+m5stack_paper.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_paper.menu.FlashFreq.40=40MHz
+m5stack_paper.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_paper.menu.FlashSize.16M=16MB (128Mb)
+m5stack_paper.menu.FlashSize.16M.build.flash_size=16MB
+
+m5stack_paper.menu.UploadSpeed.1500000=1500000
+m5stack_paper.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_paper.menu.UploadSpeed.921600=921600
+m5stack_paper.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_paper.menu.UploadSpeed.115200=115200
+m5stack_paper.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_paper.menu.UploadSpeed.256000.windows=256000
+m5stack_paper.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_paper.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_paper.menu.UploadSpeed.230400=230400
+m5stack_paper.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_paper.menu.UploadSpeed.460800.linux=460800
+m5stack_paper.menu.UploadSpeed.460800.macosx=460800
+m5stack_paper.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_paper.menu.UploadSpeed.512000.windows=512000
+m5stack_paper.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_paper.menu.LoopCore.1=Core 1
+m5stack_paper.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_paper.menu.LoopCore.0=Core 0
+m5stack_paper.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_paper.menu.EventsCore.1=Core 1
+m5stack_paper.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_paper.menu.EventsCore.0=Core 0
+m5stack_paper.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_paper.menu.DebugLevel.none=None
+m5stack_paper.menu.DebugLevel.none.build.code_debug=0
+m5stack_paper.menu.DebugLevel.error=Error
+m5stack_paper.menu.DebugLevel.error.build.code_debug=1
+m5stack_paper.menu.DebugLevel.warn=Warn
+m5stack_paper.menu.DebugLevel.warn.build.code_debug=2
+m5stack_paper.menu.DebugLevel.info=Info
+m5stack_paper.menu.DebugLevel.info.build.code_debug=3
+m5stack_paper.menu.DebugLevel.debug=Debug
+m5stack_paper.menu.DebugLevel.debug.build.code_debug=4
+m5stack_paper.menu.DebugLevel.verbose=Verbose
+m5stack_paper.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_paper.menu.EraseFlash.none=Disabled
+m5stack_paper.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_paper.menu.EraseFlash.all=Enabled
+m5stack_paper.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_coreink.name=M5CoreInk
+
+m5stack_coreink.bootloader.tool=esptool_py
+m5stack_coreink.bootloader.tool.default=esptool_py
+
+m5stack_coreink.upload.tool=esptool_py
+m5stack_coreink.upload.tool.default=esptool_py
+m5stack_coreink.upload.tool.network=esp_ota
+
+m5stack_coreink.upload.maximum_size=1310720
+m5stack_coreink.upload.maximum_data_size=327680
+m5stack_coreink.upload.flags=
+m5stack_coreink.upload.extra_flags=
+
+m5stack_coreink.serial.disableDTR=true
+m5stack_coreink.serial.disableRTS=true
+
+m5stack_coreink.build.tarch=xtensa
+m5stack_coreink.build.bootloader_addr=0x1000
+m5stack_coreink.build.target=esp32
+m5stack_coreink.build.mcu=esp32
+m5stack_coreink.build.core=esp32
+m5stack_coreink.build.variant=m5stack_coreink
+m5stack_coreink.build.board=M5STACK_COREINK
+
+m5stack_coreink.build.f_cpu=240000000L
+m5stack_coreink.build.flash_size=4MB
+m5stack_coreink.build.flash_freq=80m
+m5stack_coreink.build.flash_mode=dio
+m5stack_coreink.build.boot=dio
+m5stack_coreink.build.partitions=default
+m5stack_coreink.build.defines=
+m5stack_coreink.build.loop_core=
+m5stack_coreink.build.event_core=
+
+m5stack_coreink.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_coreink.menu.PartitionScheme.default.build.partitions=default
+m5stack_coreink.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_coreink.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_coreink.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_coreink.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_coreink.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_coreink.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_coreink.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_coreink.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_coreink.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_coreink.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_coreink.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_coreink.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_coreink.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_coreink.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_coreink.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_coreink.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_coreink.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_coreink.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_coreink.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_coreink.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_coreink.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_coreink.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_coreink.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_coreink.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_coreink.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_coreink.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_coreink.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_coreink.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_coreink.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_coreink.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_coreink.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_coreink.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_coreink.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_coreink.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_coreink.menu.PartitionScheme.custom=Custom
+m5stack_coreink.menu.PartitionScheme.custom.build.partitions=
+m5stack_coreink.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_coreink.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_coreink.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_coreink.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_coreink.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_coreink.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_coreink.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_coreink.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_coreink.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_coreink.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_coreink.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_coreink.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_coreink.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_coreink.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_coreink.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_coreink.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_coreink.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_coreink.menu.FlashMode.qio=QIO
+m5stack_coreink.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_coreink.menu.FlashMode.qio.build.boot=qio
+m5stack_coreink.menu.FlashMode.dio=DIO
+m5stack_coreink.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_coreink.menu.FlashMode.dio.build.boot=dio
+m5stack_coreink.menu.FlashMode.qout=QOUT
+m5stack_coreink.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_coreink.menu.FlashMode.qout.build.boot=qout
+m5stack_coreink.menu.FlashMode.dout=DOUT
+m5stack_coreink.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_coreink.menu.FlashMode.dout.build.boot=dout
+
+m5stack_coreink.menu.FlashFreq.80=80MHz
+m5stack_coreink.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_coreink.menu.FlashFreq.40=40MHz
+m5stack_coreink.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_coreink.menu.FlashSize.4M=4MB (32Mb)
+m5stack_coreink.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_coreink.menu.UploadSpeed.1500000=1500000
+m5stack_coreink.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_coreink.menu.UploadSpeed.750000=750000
+m5stack_coreink.menu.UploadSpeed.750000.upload.speed=750000
+m5stack_coreink.menu.UploadSpeed.500000=500000
+m5stack_coreink.menu.UploadSpeed.500000.upload.speed=500000
+m5stack_coreink.menu.UploadSpeed.250000=250000
+m5stack_coreink.menu.UploadSpeed.250000.upload.speed=250000
+m5stack_coreink.menu.UploadSpeed.115200=115200
+m5stack_coreink.menu.UploadSpeed.115200.upload.speed=115200
+
+m5stack_coreink.menu.LoopCore.1=Core 1
+m5stack_coreink.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_coreink.menu.LoopCore.0=Core 0
+m5stack_coreink.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_coreink.menu.EventsCore.1=Core 1
+m5stack_coreink.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_coreink.menu.EventsCore.0=Core 0
+m5stack_coreink.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_coreink.menu.DebugLevel.none=None
+m5stack_coreink.menu.DebugLevel.none.build.code_debug=0
+m5stack_coreink.menu.DebugLevel.error=Error
+m5stack_coreink.menu.DebugLevel.error.build.code_debug=1
+m5stack_coreink.menu.DebugLevel.warn=Warn
+m5stack_coreink.menu.DebugLevel.warn.build.code_debug=2
+m5stack_coreink.menu.DebugLevel.info=Info
+m5stack_coreink.menu.DebugLevel.info.build.code_debug=3
+m5stack_coreink.menu.DebugLevel.debug=Debug
+m5stack_coreink.menu.DebugLevel.debug.build.code_debug=4
+m5stack_coreink.menu.DebugLevel.verbose=Verbose
+m5stack_coreink.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_coreink.menu.EraseFlash.none=Disabled
+m5stack_coreink.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_coreink.menu.EraseFlash.all=Enabled
+m5stack_coreink.menu.EraseFlash.all.upload.erase_cmd=-e
+
+###############################################################
+
+m5stack_stamp_pico.name=M5StampPico
+
+m5stack_stamp_pico.bootloader.tool=esptool_py
+m5stack_stamp_pico.bootloader.tool.default=esptool_py
+
+m5stack_stamp_pico.upload.tool=esptool_py
+m5stack_stamp_pico.upload.tool.default=esptool_py
+m5stack_stamp_pico.upload.tool.network=esp_ota
+
+m5stack_stamp_pico.upload.maximum_size=1310720
+m5stack_stamp_pico.upload.maximum_data_size=327680
+m5stack_stamp_pico.upload.flags=
+m5stack_stamp_pico.upload.extra_flags=
+
+m5stack_stamp_pico.serial.disableDTR=true
+m5stack_stamp_pico.serial.disableRTS=true
+
+m5stack_stamp_pico.build.tarch=xtensa
+m5stack_stamp_pico.build.bootloader_addr=0x1000
+m5stack_stamp_pico.build.target=esp32
+m5stack_stamp_pico.build.mcu=esp32
+m5stack_stamp_pico.build.core=esp32
+m5stack_stamp_pico.build.variant=m5stack_stamp_pico
+m5stack_stamp_pico.build.board=M5STACK_STAMP_PICO
+
+m5stack_stamp_pico.build.f_cpu=240000000L
+m5stack_stamp_pico.build.flash_size=4MB
+m5stack_stamp_pico.build.flash_freq=80m
+m5stack_stamp_pico.build.flash_mode=dio
+m5stack_stamp_pico.build.boot=dio
+m5stack_stamp_pico.build.partitions=default
+m5stack_stamp_pico.build.defines=
+m5stack_stamp_pico.build.loop_core=
+m5stack_stamp_pico.build.event_core=
+
+m5stack_stamp_pico.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_stamp_pico.menu.PartitionScheme.default.build.partitions=default
+m5stack_stamp_pico.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_stamp_pico.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_stamp_pico.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_stamp_pico.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_stamp_pico.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_stamp_pico.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_stamp_pico.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_stamp_pico.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_stamp_pico.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_stamp_pico.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_stamp_pico.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_stamp_pico.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_stamp_pico.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_stamp_pico.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_stamp_pico.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_stamp_pico.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_stamp_pico.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_stamp_pico.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_stamp_pico.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_stamp_pico.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_stamp_pico.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_stamp_pico.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_stamp_pico.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_stamp_pico.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_stamp_pico.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_stamp_pico.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_stamp_pico.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_stamp_pico.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_stamp_pico.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_stamp_pico.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_stamp_pico.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_stamp_pico.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_stamp_pico.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_stamp_pico.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_stamp_pico.menu.PartitionScheme.custom=Custom
+m5stack_stamp_pico.menu.PartitionScheme.custom.build.partitions=
+m5stack_stamp_pico.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_stamp_pico.menu.CPUFreq.240=240MHz (WiFi/BT)
+m5stack_stamp_pico.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_stamp_pico.menu.CPUFreq.160=160MHz (WiFi/BT)
+m5stack_stamp_pico.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_stamp_pico.menu.CPUFreq.80=80MHz (WiFi/BT)
+m5stack_stamp_pico.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_stamp_pico.menu.CPUFreq.40=40MHz (40MHz XTAL)
+m5stack_stamp_pico.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_stamp_pico.menu.CPUFreq.26=26MHz (26MHz XTAL)
+m5stack_stamp_pico.menu.CPUFreq.26.build.f_cpu=26000000L
+m5stack_stamp_pico.menu.CPUFreq.20=20MHz (40MHz XTAL)
+m5stack_stamp_pico.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_stamp_pico.menu.CPUFreq.13=13MHz (26MHz XTAL)
+m5stack_stamp_pico.menu.CPUFreq.13.build.f_cpu=13000000L
+m5stack_stamp_pico.menu.CPUFreq.10=10MHz (40MHz XTAL)
+m5stack_stamp_pico.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_stamp_pico.menu.FlashMode.qio=QIO
+m5stack_stamp_pico.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_stamp_pico.menu.FlashMode.qio.build.boot=qio
+m5stack_stamp_pico.menu.FlashMode.dio=DIO
+m5stack_stamp_pico.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_stamp_pico.menu.FlashMode.dio.build.boot=dio
+m5stack_stamp_pico.menu.FlashMode.qout=QOUT
+m5stack_stamp_pico.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_stamp_pico.menu.FlashMode.qout.build.boot=qout
+m5stack_stamp_pico.menu.FlashMode.dout=DOUT
+m5stack_stamp_pico.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_stamp_pico.menu.FlashMode.dout.build.boot=dout
+
+m5stack_stamp_pico.menu.FlashFreq.80=80MHz
+m5stack_stamp_pico.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_stamp_pico.menu.FlashFreq.40=40MHz
+m5stack_stamp_pico.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_stamp_pico.menu.FlashSize.4M=4MB (32Mb)
+m5stack_stamp_pico.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_stamp_pico.menu.UploadSpeed.1500000=1500000
+m5stack_stamp_pico.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_stamp_pico.menu.UploadSpeed.750000=750000
+m5stack_stamp_pico.menu.UploadSpeed.750000.upload.speed=750000
+m5stack_stamp_pico.menu.UploadSpeed.500000=500000
+m5stack_stamp_pico.menu.UploadSpeed.500000.upload.speed=500000
+m5stack_stamp_pico.menu.UploadSpeed.250000=250000
+m5stack_stamp_pico.menu.UploadSpeed.250000.upload.speed=250000
+m5stack_stamp_pico.menu.UploadSpeed.115200=115200
+m5stack_stamp_pico.menu.UploadSpeed.115200.upload.speed=115200
+
+m5stack_stamp_pico.menu.LoopCore.1=Core 1
+m5stack_stamp_pico.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_stamp_pico.menu.LoopCore.0=Core 0
+m5stack_stamp_pico.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_stamp_pico.menu.EventsCore.1=Core 1
+m5stack_stamp_pico.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_stamp_pico.menu.EventsCore.0=Core 0
+m5stack_stamp_pico.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_stamp_pico.menu.DebugLevel.none=None
+m5stack_stamp_pico.menu.DebugLevel.none.build.code_debug=0
+m5stack_stamp_pico.menu.DebugLevel.error=Error
+m5stack_stamp_pico.menu.DebugLevel.error.build.code_debug=1
+m5stack_stamp_pico.menu.DebugLevel.warn=Warn
+m5stack_stamp_pico.menu.DebugLevel.warn.build.code_debug=2
+m5stack_stamp_pico.menu.DebugLevel.info=Info
+m5stack_stamp_pico.menu.DebugLevel.info.build.code_debug=3
+m5stack_stamp_pico.menu.DebugLevel.debug=Debug
+m5stack_stamp_pico.menu.DebugLevel.debug.build.code_debug=4
+m5stack_stamp_pico.menu.DebugLevel.verbose=Verbose
+m5stack_stamp_pico.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_stamp_pico.menu.EraseFlash.none=Disabled
+m5stack_stamp_pico.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_stamp_pico.menu.EraseFlash.all=Enabled
+m5stack_stamp_pico.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_stamp_c3.name=M5StampC3
+
+m5stack_stamp_c3.bootloader.tool=esptool_py
+m5stack_stamp_c3.bootloader.tool.default=esptool_py
+
+m5stack_stamp_c3.upload.tool=esptool_py
+m5stack_stamp_c3.upload.tool.default=esptool_py
+m5stack_stamp_c3.upload.tool.network=esp_ota
+
+m5stack_stamp_c3.upload.maximum_size=1310720
+m5stack_stamp_c3.upload.maximum_data_size=327680
+m5stack_stamp_c3.upload.wait_for_upload_port=false
+m5stack_stamp_c3.upload.flags=
+m5stack_stamp_c3.upload.extra_flags=
+
+m5stack_stamp_c3.serial.disableDTR=false
+m5stack_stamp_c3.serial.disableRTS=false
+
+m5stack_stamp_c3.build.tarch=riscv32
+m5stack_stamp_c3.build.target=esp
+m5stack_stamp_c3.build.mcu=esp32c3
+m5stack_stamp_c3.build.core=esp32
+m5stack_stamp_c3.build.variant=m5stack_stamp_c3
+m5stack_stamp_c3.build.board=M5STACK_STAMP_C3
+m5stack_stamp_c3.build.bootloader_addr=0x0
+
+m5stack_stamp_c3.build.cdc_on_boot=1
+m5stack_stamp_c3.build.f_cpu=160000000L
+m5stack_stamp_c3.build.flash_size=4MB
+m5stack_stamp_c3.build.flash_freq=80m
+m5stack_stamp_c3.build.flash_mode=qio
+m5stack_stamp_c3.build.boot=qio
+m5stack_stamp_c3.build.partitions=default
+m5stack_stamp_c3.build.defines=
+
+## IDE 2.0 Seems to not update the value
+m5stack_stamp_c3.menu.JTAGAdapter.default=Disabled
+m5stack_stamp_c3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_stamp_c3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_stamp_c3.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg
+m5stack_stamp_c3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_stamp_c3.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_stamp_c3.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg
+m5stack_stamp_c3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_stamp_c3.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_stamp_c3.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg
+m5stack_stamp_c3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_stamp_c3.menu.CDCOnBoot.cdc=Enabled
+m5stack_stamp_c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_stamp_c3.menu.CDCOnBoot.default=Disabled
+m5stack_stamp_c3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+m5stack_stamp_c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_stamp_c3.menu.PartitionScheme.default.build.partitions=default
+m5stack_stamp_c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_stamp_c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_stamp_c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_stamp_c3.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_stamp_c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_stamp_c3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_stamp_c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_stamp_c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_stamp_c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_stamp_c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_stamp_c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_stamp_c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_stamp_c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_stamp_c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_stamp_c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_stamp_c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_stamp_c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_stamp_c3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_stamp_c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_stamp_c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_stamp_c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_stamp_c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+
+m5stack_stamp_c3.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_stamp_c3.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_stamp_c3.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_stamp_c3.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_stamp_c3.menu.CPUFreq.40=40MHz
+m5stack_stamp_c3.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_stamp_c3.menu.CPUFreq.20=20MHz
+m5stack_stamp_c3.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_stamp_c3.menu.CPUFreq.10=10MHz
+m5stack_stamp_c3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_stamp_c3.menu.FlashMode.qio=QIO
+m5stack_stamp_c3.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_stamp_c3.menu.FlashMode.qio.build.boot=qio
+m5stack_stamp_c3.menu.FlashMode.dio=DIO
+m5stack_stamp_c3.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_stamp_c3.menu.FlashMode.dio.build.boot=dio
+m5stack_stamp_c3.menu.FlashMode.qout=QOUT
+m5stack_stamp_c3.menu.FlashMode.qout.build.flash_mode=dout
+m5stack_stamp_c3.menu.FlashMode.qout.build.boot=qout
+m5stack_stamp_c3.menu.FlashMode.dout=DOUT
+m5stack_stamp_c3.menu.FlashMode.dout.build.flash_mode=dout
+m5stack_stamp_c3.menu.FlashMode.dout.build.boot=dout
+
+m5stack_stamp_c3.menu.FlashFreq.80=80MHz
+m5stack_stamp_c3.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_stamp_c3.menu.FlashFreq.40=40MHz
+m5stack_stamp_c3.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_stamp_c3.menu.FlashSize.4M=4MB (32Mb)
+m5stack_stamp_c3.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_stamp_c3.menu.UploadSpeed.921600=921600
+m5stack_stamp_c3.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_stamp_c3.menu.UploadSpeed.115200=115200
+m5stack_stamp_c3.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_stamp_c3.menu.UploadSpeed.256000.windows=256000
+m5stack_stamp_c3.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_stamp_c3.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_stamp_c3.menu.UploadSpeed.230400=230400
+m5stack_stamp_c3.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_stamp_c3.menu.UploadSpeed.460800.linux=460800
+m5stack_stamp_c3.menu.UploadSpeed.460800.macosx=460800
+m5stack_stamp_c3.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_stamp_c3.menu.UploadSpeed.512000.windows=512000
+m5stack_stamp_c3.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_stamp_c3.menu.DebugLevel.none=None
+m5stack_stamp_c3.menu.DebugLevel.none.build.code_debug=0
+m5stack_stamp_c3.menu.DebugLevel.error=Error
+m5stack_stamp_c3.menu.DebugLevel.error.build.code_debug=1
+m5stack_stamp_c3.menu.DebugLevel.warn=Warn
+m5stack_stamp_c3.menu.DebugLevel.warn.build.code_debug=2
+m5stack_stamp_c3.menu.DebugLevel.info=Info
+m5stack_stamp_c3.menu.DebugLevel.info.build.code_debug=3
+m5stack_stamp_c3.menu.DebugLevel.debug=Debug
+m5stack_stamp_c3.menu.DebugLevel.debug.build.code_debug=4
+m5stack_stamp_c3.menu.DebugLevel.verbose=Verbose
+m5stack_stamp_c3.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_stamp_c3.menu.EraseFlash.none=Disabled
+m5stack_stamp_c3.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_stamp_c3.menu.EraseFlash.all=Enabled
+m5stack_stamp_c3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+###############################################################
+
+m5stack_stamp_s3.name=M5StampS3
+m5stack_stamp_s3.bootloader.tool=esptool_py
+m5stack_stamp_s3.bootloader.tool.default=esptool_py
+
+m5stack_stamp_s3.upload.tool=esptool_py
+m5stack_stamp_s3.upload.tool.default=esptool_py
+m5stack_stamp_s3.upload.tool.network=esp_ota
+
+m5stack_stamp_s3.upload.maximum_size=1310720
+m5stack_stamp_s3.upload.maximum_data_size=327680
+m5stack_stamp_s3.upload.flags=
+m5stack_stamp_s3.upload.extra_flags=
+m5stack_stamp_s3.upload.use_1200bps_touch=false
+m5stack_stamp_s3.upload.wait_for_upload_port=false
+
+m5stack_stamp_s3.serial.disableDTR=false
+m5stack_stamp_s3.serial.disableRTS=false
+
+m5stack_stamp_s3.build.tarch=xtensa
+m5stack_stamp_s3.build.bootloader_addr=0x0
+m5stack_stamp_s3.build.target=esp32s3
+m5stack_stamp_s3.build.mcu=esp32s3
+m5stack_stamp_s3.build.core=esp32
+m5stack_stamp_s3.build.variant=m5stack_stamp_s3
+m5stack_stamp_s3.build.board=M5STACK_STAMP_S3
+
+m5stack_stamp_s3.build.usb_mode=1
+m5stack_stamp_s3.build.cdc_on_boot=1
+m5stack_stamp_s3.build.msc_on_boot=0
+m5stack_stamp_s3.build.dfu_on_boot=0
+m5stack_stamp_s3.build.f_cpu=240000000L
+m5stack_stamp_s3.build.flash_size=8MB
+m5stack_stamp_s3.build.flash_freq=80m
+m5stack_stamp_s3.build.flash_mode=dio
+m5stack_stamp_s3.build.boot=qio
+m5stack_stamp_s3.build.boot_freq=80m
+m5stack_stamp_s3.build.partitions=default_8MB
+m5stack_stamp_s3.build.defines=
+m5stack_stamp_s3.build.loop_core=
+m5stack_stamp_s3.build.event_core=
+m5stack_stamp_s3.build.psram_type=qspi
+m5stack_stamp_s3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+m5stack_stamp_s3.menu.JTAGAdapter.default=Disabled
+m5stack_stamp_s3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_stamp_s3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_stamp_s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+m5stack_stamp_s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_stamp_s3.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_stamp_s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+m5stack_stamp_s3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_stamp_s3.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_stamp_s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+m5stack_stamp_s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_stamp_s3.menu.PSRAM.disabled=Disabled
+m5stack_stamp_s3.menu.PSRAM.disabled.build.defines=
+m5stack_stamp_s3.menu.PSRAM.disabled.build.psram_type=qspi
+m5stack_stamp_s3.menu.PSRAM.enabled=QSPI PSRAM
+m5stack_stamp_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+m5stack_stamp_s3.menu.PSRAM.enabled.build.psram_type=qspi
+m5stack_stamp_s3.menu.PSRAM.opi=OPI PSRAM
+m5stack_stamp_s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+m5stack_stamp_s3.menu.PSRAM.opi.build.psram_type=opi
+
+m5stack_stamp_s3.menu.FlashMode.qio=QIO 80MHz
+m5stack_stamp_s3.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_stamp_s3.menu.FlashMode.qio.build.boot=qio
+m5stack_stamp_s3.menu.FlashMode.qio.build.boot_freq=80m
+m5stack_stamp_s3.menu.FlashMode.qio.build.flash_freq=80m
+m5stack_stamp_s3.menu.FlashMode.qio120=QIO 120MHz
+m5stack_stamp_s3.menu.FlashMode.qio120.build.flash_mode=dio
+m5stack_stamp_s3.menu.FlashMode.qio120.build.boot=qio
+m5stack_stamp_s3.menu.FlashMode.qio120.build.boot_freq=120m
+m5stack_stamp_s3.menu.FlashMode.qio120.build.flash_freq=80m
+m5stack_stamp_s3.menu.FlashMode.dio=DIO 80MHz
+m5stack_stamp_s3.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_stamp_s3.menu.FlashMode.dio.build.boot=dio
+m5stack_stamp_s3.menu.FlashMode.dio.build.boot_freq=80m
+m5stack_stamp_s3.menu.FlashMode.dio.build.flash_freq=80m
+m5stack_stamp_s3.menu.FlashMode.opi=OPI 80MHz
+m5stack_stamp_s3.menu.FlashMode.opi.build.flash_mode=dout
+m5stack_stamp_s3.menu.FlashMode.opi.build.boot=opi
+m5stack_stamp_s3.menu.FlashMode.opi.build.boot_freq=80m
+m5stack_stamp_s3.menu.FlashMode.opi.build.flash_freq=80m
+
+m5stack_stamp_s3.menu.FlashSize.4M=4MB (32Mb)
+m5stack_stamp_s3.menu.FlashSize.4M.build.flash_size=4MB
+m5stack_stamp_s3.menu.FlashSize.8M=8MB (64Mb)
+m5stack_stamp_s3.menu.FlashSize.8M.build.flash_size=8MB
+m5stack_stamp_s3.menu.FlashSize.16M=16MB (128Mb)
+m5stack_stamp_s3.menu.FlashSize.16M.build.flash_size=16MB
+m5stack_stamp_s3.menu.FlashSize.32M=32MB (256Mb)
+m5stack_stamp_s3.menu.FlashSize.32M.build.flash_size=32MB
+
+m5stack_stamp_s3.menu.LoopCore.1=Core 1
+m5stack_stamp_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_stamp_s3.menu.LoopCore.0=Core 0
+m5stack_stamp_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_stamp_s3.menu.EventsCore.1=Core 1
+m5stack_stamp_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_stamp_s3.menu.EventsCore.0=Core 0
+m5stack_stamp_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_stamp_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+m5stack_stamp_s3.menu.USBMode.hwcdc.build.usb_mode=1
+m5stack_stamp_s3.menu.USBMode.default=USB-OTG (TinyUSB)
+m5stack_stamp_s3.menu.USBMode.default.build.usb_mode=0
+
+m5stack_stamp_s3.menu.CDCOnBoot.cdc=Enabled
+m5stack_stamp_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_stamp_s3.menu.CDCOnBoot.default=Disabled
+m5stack_stamp_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+m5stack_stamp_s3.menu.MSCOnBoot.default=Disabled
+m5stack_stamp_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+m5stack_stamp_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+m5stack_stamp_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+m5stack_stamp_s3.menu.DFUOnBoot.default=Disabled
+m5stack_stamp_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+m5stack_stamp_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+m5stack_stamp_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+m5stack_stamp_s3.menu.UploadMode.default=UART0 / Hardware CDC
+m5stack_stamp_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+m5stack_stamp_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+m5stack_stamp_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+m5stack_stamp_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+m5stack_stamp_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+m5stack_stamp_s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_stamp_s3.menu.PartitionScheme.default.build.partitions=default
+m5stack_stamp_s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_stamp_s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_stamp_s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_stamp_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_stamp_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_stamp_s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_stamp_s3.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_stamp_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_stamp_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_stamp_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_stamp_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_stamp_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_stamp_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_stamp_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_stamp_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_stamp_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_stamp_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_stamp_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_stamp_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_stamp_s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_stamp_s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_stamp_s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_stamp_s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_stamp_s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_stamp_s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_stamp_s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_stamp_s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_stamp_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_stamp_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_stamp_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_stamp_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_stamp_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_stamp_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_stamp_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_stamp_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_stamp_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_stamp_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_stamp_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_stamp_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_stamp_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_stamp_s3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+m5stack_stamp_s3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+m5stack_stamp_s3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+m5stack_stamp_s3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+m5stack_stamp_s3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+m5stack_stamp_s3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+m5stack_stamp_s3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+m5stack_stamp_s3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+m5stack_stamp_s3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+m5stack_stamp_s3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+m5stack_stamp_s3.menu.PartitionScheme.custom=Custom
+m5stack_stamp_s3.menu.PartitionScheme.custom.build.partitions=
+m5stack_stamp_s3.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_stamp_s3.menu.CPUFreq.240=240MHz (WiFi)
+m5stack_stamp_s3.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_stamp_s3.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_stamp_s3.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_stamp_s3.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_stamp_s3.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_stamp_s3.menu.CPUFreq.40=40MHz
+m5stack_stamp_s3.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_stamp_s3.menu.CPUFreq.20=20MHz
+m5stack_stamp_s3.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_stamp_s3.menu.CPUFreq.10=10MHz
+m5stack_stamp_s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_stamp_s3.menu.UploadSpeed.921600=921600
+m5stack_stamp_s3.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_stamp_s3.menu.UploadSpeed.115200=115200
+m5stack_stamp_s3.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_stamp_s3.menu.UploadSpeed.256000.windows=256000
+m5stack_stamp_s3.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_stamp_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_stamp_s3.menu.UploadSpeed.230400=230400
+m5stack_stamp_s3.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_stamp_s3.menu.UploadSpeed.460800.linux=460800
+m5stack_stamp_s3.menu.UploadSpeed.460800.macosx=460800
+m5stack_stamp_s3.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_stamp_s3.menu.UploadSpeed.512000.windows=512000
+m5stack_stamp_s3.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_stamp_s3.menu.DebugLevel.none=None
+m5stack_stamp_s3.menu.DebugLevel.none.build.code_debug=0
+m5stack_stamp_s3.menu.DebugLevel.error=Error
+m5stack_stamp_s3.menu.DebugLevel.error.build.code_debug=1
+m5stack_stamp_s3.menu.DebugLevel.warn=Warn
+m5stack_stamp_s3.menu.DebugLevel.warn.build.code_debug=2
+m5stack_stamp_s3.menu.DebugLevel.info=Info
+m5stack_stamp_s3.menu.DebugLevel.info.build.code_debug=3
+m5stack_stamp_s3.menu.DebugLevel.debug=Debug
+m5stack_stamp_s3.menu.DebugLevel.debug.build.code_debug=4
+m5stack_stamp_s3.menu.DebugLevel.verbose=Verbose
+m5stack_stamp_s3.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_stamp_s3.menu.EraseFlash.none=Disabled
+m5stack_stamp_s3.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_stamp_s3.menu.EraseFlash.all=Enabled
+m5stack_stamp_s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_capsule.name=M5Capsule
+m5stack_capsule.bootloader.tool=esptool_py
+m5stack_capsule.bootloader.tool.default=esptool_py
+
+m5stack_capsule.upload.tool=esptool_py
+m5stack_capsule.upload.tool.default=esptool_py
+m5stack_capsule.upload.tool.network=esp_ota
+
+m5stack_capsule.upload.maximum_size=1310720
+m5stack_capsule.upload.maximum_data_size=327680
+m5stack_capsule.upload.flags=
+m5stack_capsule.upload.extra_flags=
+m5stack_capsule.upload.use_1200bps_touch=false
+m5stack_capsule.upload.wait_for_upload_port=false
+
+m5stack_capsule.serial.disableDTR=false
+m5stack_capsule.serial.disableRTS=false
+
+m5stack_capsule.build.tarch=xtensa
+m5stack_capsule.build.bootloader_addr=0x0
+m5stack_capsule.build.target=esp32s3
+m5stack_capsule.build.mcu=esp32s3
+m5stack_capsule.build.core=esp32
+m5stack_capsule.build.variant=m5stack_capsule
+m5stack_capsule.build.board=M5STACK_CAPSULE
+
+m5stack_capsule.build.usb_mode=1
+m5stack_capsule.build.cdc_on_boot=1
+m5stack_capsule.build.msc_on_boot=0
+m5stack_capsule.build.dfu_on_boot=0
+m5stack_capsule.build.f_cpu=240000000L
+m5stack_capsule.build.flash_size=8MB
+m5stack_capsule.build.flash_freq=80m
+m5stack_capsule.build.flash_mode=dio
+m5stack_capsule.build.boot=qio
+m5stack_capsule.build.boot_freq=80m
+m5stack_capsule.build.partitions=default
+m5stack_capsule.build.defines=
+m5stack_capsule.build.loop_core=
+m5stack_capsule.build.event_core=
+m5stack_capsule.build.psram_type=qspi
+m5stack_capsule.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+m5stack_capsule.menu.JTAGAdapter.default=Disabled
+m5stack_capsule.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_capsule.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_capsule.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+m5stack_capsule.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_capsule.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_capsule.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+m5stack_capsule.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_capsule.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_capsule.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+m5stack_capsule.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_capsule.menu.PSRAM.disabled=Disabled
+m5stack_capsule.menu.PSRAM.disabled.build.defines=
+m5stack_capsule.menu.PSRAM.disabled.build.psram_type=qspi
+m5stack_capsule.menu.PSRAM.enabled=QSPI PSRAM
+m5stack_capsule.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+m5stack_capsule.menu.PSRAM.enabled.build.psram_type=qspi
+m5stack_capsule.menu.PSRAM.opi=OPI PSRAM
+m5stack_capsule.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+m5stack_capsule.menu.PSRAM.opi.build.psram_type=opi
+
+m5stack_capsule.menu.FlashMode.qio=QIO 80MHz
+m5stack_capsule.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_capsule.menu.FlashMode.qio.build.boot=qio
+m5stack_capsule.menu.FlashMode.qio.build.boot_freq=80m
+m5stack_capsule.menu.FlashMode.qio.build.flash_freq=80m
+m5stack_capsule.menu.FlashMode.qio120=QIO 120MHz
+m5stack_capsule.menu.FlashMode.qio120.build.flash_mode=dio
+m5stack_capsule.menu.FlashMode.qio120.build.boot=qio
+m5stack_capsule.menu.FlashMode.qio120.build.boot_freq=120m
+m5stack_capsule.menu.FlashMode.qio120.build.flash_freq=80m
+m5stack_capsule.menu.FlashMode.dio=DIO 80MHz
+m5stack_capsule.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_capsule.menu.FlashMode.dio.build.boot=dio
+m5stack_capsule.menu.FlashMode.dio.build.boot_freq=80m
+m5stack_capsule.menu.FlashMode.dio.build.flash_freq=80m
+m5stack_capsule.menu.FlashMode.opi=OPI 80MHz
+m5stack_capsule.menu.FlashMode.opi.build.flash_mode=dout
+m5stack_capsule.menu.FlashMode.opi.build.boot=opi
+m5stack_capsule.menu.FlashMode.opi.build.boot_freq=80m
+m5stack_capsule.menu.FlashMode.opi.build.flash_freq=80m
+
+m5stack_capsule.menu.FlashSize.4M=4MB (32Mb)
+m5stack_capsule.menu.FlashSize.4M.build.flash_size=4MB
+m5stack_capsule.menu.FlashSize.8M=8MB (64Mb)
+m5stack_capsule.menu.FlashSize.8M.build.flash_size=8MB
+m5stack_capsule.menu.FlashSize.16M=16MB (128Mb)
+m5stack_capsule.menu.FlashSize.16M.build.flash_size=16MB
+m5stack_capsule.menu.FlashSize.32M=32MB (256Mb)
+m5stack_capsule.menu.FlashSize.32M.build.flash_size=32MB
+
+m5stack_capsule.menu.LoopCore.1=Core 1
+m5stack_capsule.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_capsule.menu.LoopCore.0=Core 0
+m5stack_capsule.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_capsule.menu.EventsCore.1=Core 1
+m5stack_capsule.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_capsule.menu.EventsCore.0=Core 0
+m5stack_capsule.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_capsule.menu.USBMode.hwcdc=Hardware CDC and JTAG
+m5stack_capsule.menu.USBMode.hwcdc.build.usb_mode=1
+m5stack_capsule.menu.USBMode.default=USB-OTG (TinyUSB)
+m5stack_capsule.menu.USBMode.default.build.usb_mode=0
+
+m5stack_capsule.menu.CDCOnBoot.cdc=Enabled
+m5stack_capsule.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_capsule.menu.CDCOnBoot.default=Disabled
+m5stack_capsule.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+m5stack_capsule.menu.MSCOnBoot.default=Disabled
+m5stack_capsule.menu.MSCOnBoot.default.build.msc_on_boot=0
+m5stack_capsule.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+m5stack_capsule.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+m5stack_capsule.menu.DFUOnBoot.default=Disabled
+m5stack_capsule.menu.DFUOnBoot.default.build.dfu_on_boot=0
+m5stack_capsule.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+m5stack_capsule.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+m5stack_capsule.menu.UploadMode.default=UART0 / Hardware CDC
+m5stack_capsule.menu.UploadMode.default.upload.use_1200bps_touch=false
+m5stack_capsule.menu.UploadMode.default.upload.wait_for_upload_port=false
+m5stack_capsule.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+m5stack_capsule.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+m5stack_capsule.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+m5stack_capsule.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_capsule.menu.PartitionScheme.default.build.partitions=default
+m5stack_capsule.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_capsule.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_capsule.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_capsule.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_capsule.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_capsule.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_capsule.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_capsule.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_capsule.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_capsule.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_capsule.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_capsule.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_capsule.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_capsule.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_capsule.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_capsule.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_capsule.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_capsule.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_capsule.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_capsule.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_capsule.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_capsule.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_capsule.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_capsule.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_capsule.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_capsule.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_capsule.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_capsule.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_capsule.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_capsule.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_capsule.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_capsule.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_capsule.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_capsule.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_capsule.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_capsule.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_capsule.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_capsule.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_capsule.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_capsule.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_capsule.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+m5stack_capsule.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+m5stack_capsule.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+m5stack_capsule.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+m5stack_capsule.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+m5stack_capsule.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+m5stack_capsule.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+m5stack_capsule.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+m5stack_capsule.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+m5stack_capsule.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+m5stack_capsule.menu.PartitionScheme.custom=Custom
+m5stack_capsule.menu.PartitionScheme.custom.build.partitions=
+m5stack_capsule.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_capsule.menu.CPUFreq.240=240MHz (WiFi)
+m5stack_capsule.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_capsule.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_capsule.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_capsule.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_capsule.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_capsule.menu.CPUFreq.40=40MHz
+m5stack_capsule.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_capsule.menu.CPUFreq.20=20MHz
+m5stack_capsule.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_capsule.menu.CPUFreq.10=10MHz
+m5stack_capsule.menu.CPUFreq.10.build.f_cpu=10000000L
+
+
+m5stack_capsule.menu.UploadSpeed.1500000=1500000
+m5stack_capsule.menu.UploadSpeed.1500000.upload.speed=1500000
+m5stack_capsule.menu.UploadSpeed.921600=921600
+m5stack_capsule.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_capsule.menu.UploadSpeed.115200=115200
+m5stack_capsule.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_capsule.menu.UploadSpeed.256000.windows=256000
+m5stack_capsule.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_capsule.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_capsule.menu.UploadSpeed.230400=230400
+m5stack_capsule.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_capsule.menu.UploadSpeed.460800.linux=460800
+m5stack_capsule.menu.UploadSpeed.460800.macosx=460800
+m5stack_capsule.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_capsule.menu.UploadSpeed.512000.windows=512000
+m5stack_capsule.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_capsule.menu.DebugLevel.none=None
+m5stack_capsule.menu.DebugLevel.none.build.code_debug=0
+m5stack_capsule.menu.DebugLevel.error=Error
+m5stack_capsule.menu.DebugLevel.error.build.code_debug=1
+m5stack_capsule.menu.DebugLevel.warn=Warn
+m5stack_capsule.menu.DebugLevel.warn.build.code_debug=2
+m5stack_capsule.menu.DebugLevel.info=Info
+m5stack_capsule.menu.DebugLevel.info.build.code_debug=3
+m5stack_capsule.menu.DebugLevel.debug=Debug
+m5stack_capsule.menu.DebugLevel.debug.build.code_debug=4
+m5stack_capsule.menu.DebugLevel.verbose=Verbose
+m5stack_capsule.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_capsule.menu.EraseFlash.none=Disabled
+m5stack_capsule.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_capsule.menu.EraseFlash.all=Enabled
+m5stack_capsule.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_cardputer.name=M5Cardputer
+m5stack_cardputer.bootloader.tool=esptool_py
+m5stack_cardputer.bootloader.tool.default=esptool_py
+
+m5stack_cardputer.upload.tool=esptool_py
+m5stack_cardputer.upload.tool.default=esptool_py
+m5stack_cardputer.upload.tool.network=esp_ota
+
+m5stack_cardputer.upload.maximum_size=1310720
+m5stack_cardputer.upload.maximum_data_size=327680
+m5stack_cardputer.upload.flags=
+m5stack_cardputer.upload.extra_flags=
+m5stack_cardputer.upload.use_1200bps_touch=false
+m5stack_cardputer.upload.wait_for_upload_port=false
+
+m5stack_cardputer.serial.disableDTR=false
+m5stack_cardputer.serial.disableRTS=false
+
+m5stack_cardputer.build.tarch=xtensa
+m5stack_cardputer.build.bootloader_addr=0x0
+m5stack_cardputer.build.target=esp32s3
+m5stack_cardputer.build.mcu=esp32s3
+m5stack_cardputer.build.core=esp32
+m5stack_cardputer.build.variant=m5stack_cardputer
+m5stack_cardputer.build.board=M5STACK_CARDPUTER
+
+m5stack_cardputer.build.usb_mode=1
+m5stack_cardputer.build.cdc_on_boot=1
+m5stack_cardputer.build.msc_on_boot=0
+m5stack_cardputer.build.dfu_on_boot=0
+m5stack_cardputer.build.f_cpu=240000000L
+m5stack_cardputer.build.flash_size=8MB
+m5stack_cardputer.build.flash_freq=80m
+m5stack_cardputer.build.flash_mode=dio
+m5stack_cardputer.build.boot=qio
+m5stack_cardputer.build.boot_freq=80m
+m5stack_cardputer.build.partitions=default
+m5stack_cardputer.build.defines=
+m5stack_cardputer.build.loop_core=
+m5stack_cardputer.build.event_core=
+m5stack_cardputer.build.psram_type=qspi
+m5stack_cardputer.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+m5stack_cardputer.menu.JTAGAdapter.default=Disabled
+m5stack_cardputer.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_cardputer.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_cardputer.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+m5stack_cardputer.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_cardputer.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_cardputer.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+m5stack_cardputer.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_cardputer.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_cardputer.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+m5stack_cardputer.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_cardputer.menu.PSRAM.disabled=Disabled
+m5stack_cardputer.menu.PSRAM.disabled.build.defines=
+m5stack_cardputer.menu.PSRAM.disabled.build.psram_type=qspi
+m5stack_cardputer.menu.PSRAM.enabled=QSPI PSRAM
+m5stack_cardputer.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+m5stack_cardputer.menu.PSRAM.enabled.build.psram_type=qspi
+m5stack_cardputer.menu.PSRAM.opi=OPI PSRAM
+m5stack_cardputer.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+m5stack_cardputer.menu.PSRAM.opi.build.psram_type=opi
+
+m5stack_cardputer.menu.FlashMode.qio=QIO 80MHz
+m5stack_cardputer.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_cardputer.menu.FlashMode.qio.build.boot=qio
+m5stack_cardputer.menu.FlashMode.qio.build.boot_freq=80m
+m5stack_cardputer.menu.FlashMode.qio.build.flash_freq=80m
+m5stack_cardputer.menu.FlashMode.qio120=QIO 120MHz
+m5stack_cardputer.menu.FlashMode.qio120.build.flash_mode=dio
+m5stack_cardputer.menu.FlashMode.qio120.build.boot=qio
+m5stack_cardputer.menu.FlashMode.qio120.build.boot_freq=120m
+m5stack_cardputer.menu.FlashMode.qio120.build.flash_freq=80m
+m5stack_cardputer.menu.FlashMode.dio=DIO 80MHz
+m5stack_cardputer.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_cardputer.menu.FlashMode.dio.build.boot=dio
+m5stack_cardputer.menu.FlashMode.dio.build.boot_freq=80m
+m5stack_cardputer.menu.FlashMode.dio.build.flash_freq=80m
+m5stack_cardputer.menu.FlashMode.opi=OPI 80MHz
+m5stack_cardputer.menu.FlashMode.opi.build.flash_mode=dout
+m5stack_cardputer.menu.FlashMode.opi.build.boot=opi
+m5stack_cardputer.menu.FlashMode.opi.build.boot_freq=80m
+m5stack_cardputer.menu.FlashMode.opi.build.flash_freq=80m
+
+m5stack_cardputer.menu.FlashSize.4M=4MB (32Mb)
+m5stack_cardputer.menu.FlashSize.4M.build.flash_size=4MB
+m5stack_cardputer.menu.FlashSize.8M=8MB (64Mb)
+m5stack_cardputer.menu.FlashSize.8M.build.flash_size=8MB
+m5stack_cardputer.menu.FlashSize.16M=16MB (128Mb)
+m5stack_cardputer.menu.FlashSize.16M.build.flash_size=16MB
+m5stack_cardputer.menu.FlashSize.32M=32MB (256Mb)
+m5stack_cardputer.menu.FlashSize.32M.build.flash_size=32MB
+
+m5stack_cardputer.menu.LoopCore.1=Core 1
+m5stack_cardputer.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_cardputer.menu.LoopCore.0=Core 0
+m5stack_cardputer.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_cardputer.menu.EventsCore.1=Core 1
+m5stack_cardputer.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_cardputer.menu.EventsCore.0=Core 0
+m5stack_cardputer.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_cardputer.menu.USBMode.hwcdc=Hardware CDC and JTAG
+m5stack_cardputer.menu.USBMode.hwcdc.build.usb_mode=1
+m5stack_cardputer.menu.USBMode.default=USB-OTG (TinyUSB)
+m5stack_cardputer.menu.USBMode.default.build.usb_mode=0
+
+m5stack_cardputer.menu.CDCOnBoot.cdc=Enabled
+m5stack_cardputer.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_cardputer.menu.CDCOnBoot.default=Disabled
+m5stack_cardputer.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+m5stack_cardputer.menu.MSCOnBoot.default=Disabled
+m5stack_cardputer.menu.MSCOnBoot.default.build.msc_on_boot=0
+m5stack_cardputer.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+m5stack_cardputer.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+m5stack_cardputer.menu.DFUOnBoot.default=Disabled
+m5stack_cardputer.menu.DFUOnBoot.default.build.dfu_on_boot=0
+m5stack_cardputer.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+m5stack_cardputer.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+m5stack_cardputer.menu.UploadMode.default=UART0 / Hardware CDC
+m5stack_cardputer.menu.UploadMode.default.upload.use_1200bps_touch=false
+m5stack_cardputer.menu.UploadMode.default.upload.wait_for_upload_port=false
+m5stack_cardputer.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+m5stack_cardputer.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+m5stack_cardputer.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+m5stack_cardputer.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_cardputer.menu.PartitionScheme.default.build.partitions=default
+m5stack_cardputer.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_cardputer.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_cardputer.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_cardputer.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_cardputer.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_cardputer.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_cardputer.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_cardputer.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_cardputer.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_cardputer.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_cardputer.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_cardputer.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_cardputer.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_cardputer.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_cardputer.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_cardputer.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_cardputer.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_cardputer.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_cardputer.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_cardputer.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_cardputer.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_cardputer.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_cardputer.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_cardputer.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_cardputer.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_cardputer.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_cardputer.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_cardputer.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_cardputer.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_cardputer.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_cardputer.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_cardputer.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_cardputer.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_cardputer.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_cardputer.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_cardputer.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_cardputer.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_cardputer.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_cardputer.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_cardputer.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_cardputer.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+m5stack_cardputer.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+m5stack_cardputer.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+m5stack_cardputer.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+m5stack_cardputer.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+m5stack_cardputer.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+m5stack_cardputer.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+m5stack_cardputer.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+m5stack_cardputer.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+m5stack_cardputer.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+m5stack_cardputer.menu.PartitionScheme.custom=Custom
+m5stack_cardputer.menu.PartitionScheme.custom.build.partitions=
+m5stack_cardputer.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_cardputer.menu.CPUFreq.240=240MHz (WiFi)
+m5stack_cardputer.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_cardputer.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_cardputer.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_cardputer.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_cardputer.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_cardputer.menu.CPUFreq.40=40MHz
+m5stack_cardputer.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_cardputer.menu.CPUFreq.20=20MHz
+m5stack_cardputer.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_cardputer.menu.CPUFreq.10=10MHz
+m5stack_cardputer.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_cardputer.menu.UploadSpeed.921600=921600
+m5stack_cardputer.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_cardputer.menu.UploadSpeed.115200=115200
+m5stack_cardputer.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_cardputer.menu.UploadSpeed.256000.windows=256000
+m5stack_cardputer.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_cardputer.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_cardputer.menu.UploadSpeed.230400=230400
+m5stack_cardputer.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_cardputer.menu.UploadSpeed.460800.linux=460800
+m5stack_cardputer.menu.UploadSpeed.460800.macosx=460800
+m5stack_cardputer.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_cardputer.menu.UploadSpeed.512000.windows=512000
+m5stack_cardputer.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_cardputer.menu.DebugLevel.none=None
+m5stack_cardputer.menu.DebugLevel.none.build.code_debug=0
+m5stack_cardputer.menu.DebugLevel.error=Error
+m5stack_cardputer.menu.DebugLevel.error.build.code_debug=1
+m5stack_cardputer.menu.DebugLevel.warn=Warn
+m5stack_cardputer.menu.DebugLevel.warn.build.code_debug=2
+m5stack_cardputer.menu.DebugLevel.info=Info
+m5stack_cardputer.menu.DebugLevel.info.build.code_debug=3
+m5stack_cardputer.menu.DebugLevel.debug=Debug
+m5stack_cardputer.menu.DebugLevel.debug.build.code_debug=4
+m5stack_cardputer.menu.DebugLevel.verbose=Verbose
+m5stack_cardputer.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_cardputer.menu.EraseFlash.none=Disabled
+m5stack_cardputer.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_cardputer.menu.EraseFlash.all=Enabled
+m5stack_cardputer.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_dial.name=M5Dial
+m5stack_dial.bootloader.tool=esptool_py
+m5stack_dial.bootloader.tool.default=esptool_py
+
+m5stack_dial.upload.tool=esptool_py
+m5stack_dial.upload.tool.default=esptool_py
+m5stack_dial.upload.tool.network=esp_ota
+
+m5stack_dial.upload.maximum_size=1310720
+m5stack_dial.upload.maximum_data_size=327680
+m5stack_dial.upload.flags=
+m5stack_dial.upload.extra_flags=
+m5stack_dial.upload.use_1200bps_touch=false
+m5stack_dial.upload.wait_for_upload_port=false
+
+m5stack_dial.serial.disableDTR=false
+m5stack_dial.serial.disableRTS=false
+
+m5stack_dial.build.tarch=xtensa
+m5stack_dial.build.bootloader_addr=0x0
+m5stack_dial.build.target=esp32s3
+m5stack_dial.build.mcu=esp32s3
+m5stack_dial.build.core=esp32
+m5stack_dial.build.variant=m5stack_dial
+m5stack_dial.build.board=M5STACK_DIAL
+
+m5stack_dial.build.usb_mode=1
+m5stack_dial.build.cdc_on_boot=1
+m5stack_dial.build.msc_on_boot=0
+m5stack_dial.build.dfu_on_boot=0
+m5stack_dial.build.f_cpu=240000000L
+m5stack_dial.build.flash_size=8MB
+m5stack_dial.build.flash_freq=80m
+m5stack_dial.build.flash_mode=dio
+m5stack_dial.build.boot=qio
+m5stack_dial.build.boot_freq=80m
+m5stack_dial.build.partitions=default_8MB
+m5stack_dial.build.defines=
+m5stack_dial.build.loop_core=
+m5stack_dial.build.event_core=
+m5stack_dial.build.psram_type=qspi
+m5stack_dial.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+m5stack_dial.menu.JTAGAdapter.default=Disabled
+m5stack_dial.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_dial.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_dial.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+m5stack_dial.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_dial.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_dial.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+m5stack_dial.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_dial.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_dial.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+m5stack_dial.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_dial.menu.PSRAM.disabled=Disabled
+m5stack_dial.menu.PSRAM.disabled.build.defines=
+m5stack_dial.menu.PSRAM.disabled.build.psram_type=qspi
+m5stack_dial.menu.PSRAM.enabled=QSPI PSRAM
+m5stack_dial.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+m5stack_dial.menu.PSRAM.enabled.build.psram_type=qspi
+m5stack_dial.menu.PSRAM.opi=OPI PSRAM
+m5stack_dial.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+m5stack_dial.menu.PSRAM.opi.build.psram_type=opi
+
+m5stack_dial.menu.FlashMode.qio=QIO 80MHz
+m5stack_dial.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_dial.menu.FlashMode.qio.build.boot=qio
+m5stack_dial.menu.FlashMode.qio.build.boot_freq=80m
+m5stack_dial.menu.FlashMode.qio.build.flash_freq=80m
+m5stack_dial.menu.FlashMode.qio120=QIO 120MHz
+m5stack_dial.menu.FlashMode.qio120.build.flash_mode=dio
+m5stack_dial.menu.FlashMode.qio120.build.boot=qio
+m5stack_dial.menu.FlashMode.qio120.build.boot_freq=120m
+m5stack_dial.menu.FlashMode.qio120.build.flash_freq=80m
+m5stack_dial.menu.FlashMode.dio=DIO 80MHz
+m5stack_dial.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_dial.menu.FlashMode.dio.build.boot=dio
+m5stack_dial.menu.FlashMode.dio.build.boot_freq=80m
+m5stack_dial.menu.FlashMode.dio.build.flash_freq=80m
+m5stack_dial.menu.FlashMode.opi=OPI 80MHz
+m5stack_dial.menu.FlashMode.opi.build.flash_mode=dout
+m5stack_dial.menu.FlashMode.opi.build.boot=opi
+m5stack_dial.menu.FlashMode.opi.build.boot_freq=80m
+m5stack_dial.menu.FlashMode.opi.build.flash_freq=80m
+
+m5stack_dial.menu.FlashSize.4M=4MB (32Mb)
+m5stack_dial.menu.FlashSize.4M.build.flash_size=4MB
+m5stack_dial.menu.FlashSize.8M=8MB (64Mb)
+m5stack_dial.menu.FlashSize.8M.build.flash_size=8MB
+m5stack_dial.menu.FlashSize.16M=16MB (128Mb)
+m5stack_dial.menu.FlashSize.16M.build.flash_size=16MB
+m5stack_dial.menu.FlashSize.32M=32MB (256Mb)
+m5stack_dial.menu.FlashSize.32M.build.flash_size=32MB
+
+m5stack_dial.menu.LoopCore.1=Core 1
+m5stack_dial.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_dial.menu.LoopCore.0=Core 0
+m5stack_dial.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_dial.menu.EventsCore.1=Core 1
+m5stack_dial.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_dial.menu.EventsCore.0=Core 0
+m5stack_dial.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_dial.menu.USBMode.hwcdc=Hardware CDC and JTAG
+m5stack_dial.menu.USBMode.hwcdc.build.usb_mode=1
+m5stack_dial.menu.USBMode.default=USB-OTG (TinyUSB)
+m5stack_dial.menu.USBMode.default.build.usb_mode=0
+
+m5stack_dial.menu.CDCOnBoot.cdc=Enabled
+m5stack_dial.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_dial.menu.CDCOnBoot.default=Disabled
+m5stack_dial.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+m5stack_dial.menu.MSCOnBoot.default=Disabled
+m5stack_dial.menu.MSCOnBoot.default.build.msc_on_boot=0
+m5stack_dial.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+m5stack_dial.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+m5stack_dial.menu.DFUOnBoot.default=Disabled
+m5stack_dial.menu.DFUOnBoot.default.build.dfu_on_boot=0
+m5stack_dial.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+m5stack_dial.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+m5stack_dial.menu.UploadMode.default=UART0 / Hardware CDC
+m5stack_dial.menu.UploadMode.default.upload.use_1200bps_touch=false
+m5stack_dial.menu.UploadMode.default.upload.wait_for_upload_port=false
+m5stack_dial.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+m5stack_dial.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+m5stack_dial.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+m5stack_dial.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_dial.menu.PartitionScheme.default.build.partitions=default
+m5stack_dial.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_dial.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_dial.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_dial.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_dial.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_dial.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_dial.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_dial.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_dial.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_dial.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_dial.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_dial.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_dial.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_dial.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_dial.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_dial.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_dial.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_dial.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_dial.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_dial.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_dial.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_dial.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_dial.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_dial.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_dial.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_dial.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_dial.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_dial.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_dial.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_dial.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_dial.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_dial.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_dial.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_dial.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_dial.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_dial.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_dial.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_dial.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_dial.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_dial.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_dial.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+m5stack_dial.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+m5stack_dial.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+m5stack_dial.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+m5stack_dial.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+m5stack_dial.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+m5stack_dial.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+m5stack_dial.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+m5stack_dial.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+m5stack_dial.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+m5stack_dial.menu.PartitionScheme.custom=Custom
+m5stack_dial.menu.PartitionScheme.custom.build.partitions=
+m5stack_dial.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_dial.menu.CPUFreq.240=240MHz (WiFi)
+m5stack_dial.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_dial.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_dial.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_dial.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_dial.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_dial.menu.CPUFreq.40=40MHz
+m5stack_dial.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_dial.menu.CPUFreq.20=20MHz
+m5stack_dial.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_dial.menu.CPUFreq.10=10MHz
+m5stack_dial.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_dial.menu.UploadSpeed.921600=921600
+m5stack_dial.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_dial.menu.UploadSpeed.115200=115200
+m5stack_dial.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_dial.menu.UploadSpeed.256000.windows=256000
+m5stack_dial.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_dial.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_dial.menu.UploadSpeed.230400=230400
+m5stack_dial.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_dial.menu.UploadSpeed.460800.linux=460800
+m5stack_dial.menu.UploadSpeed.460800.macosx=460800
+m5stack_dial.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_dial.menu.UploadSpeed.512000.windows=512000
+m5stack_dial.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_dial.menu.DebugLevel.none=None
+m5stack_dial.menu.DebugLevel.none.build.code_debug=0
+m5stack_dial.menu.DebugLevel.error=Error
+m5stack_dial.menu.DebugLevel.error.build.code_debug=1
+m5stack_dial.menu.DebugLevel.warn=Warn
+m5stack_dial.menu.DebugLevel.warn.build.code_debug=2
+m5stack_dial.menu.DebugLevel.info=Info
+m5stack_dial.menu.DebugLevel.info.build.code_debug=3
+m5stack_dial.menu.DebugLevel.debug=Debug
+m5stack_dial.menu.DebugLevel.debug.build.code_debug=4
+m5stack_dial.menu.DebugLevel.verbose=Verbose
+m5stack_dial.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_dial.menu.EraseFlash.none=Disabled
+m5stack_dial.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_dial.menu.EraseFlash.all=Enabled
+m5stack_dial.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+m5stack_dinmeter.name=M5DinMeter
+m5stack_dinmeter.bootloader.tool=esptool_py
+m5stack_dinmeter.bootloader.tool.default=esptool_py
+
+m5stack_dinmeter.upload.tool=esptool_py
+m5stack_dinmeter.upload.tool.default=esptool_py
+m5stack_dinmeter.upload.tool.network=esp_ota
+
+m5stack_dinmeter.upload.maximum_size=1310720
+m5stack_dinmeter.upload.maximum_data_size=327680
+m5stack_dinmeter.upload.flags=
+m5stack_dinmeter.upload.extra_flags=
+m5stack_dinmeter.upload.use_1200bps_touch=false
+m5stack_dinmeter.upload.wait_for_upload_port=false
+
+m5stack_dinmeter.serial.disableDTR=false
+m5stack_dinmeter.serial.disableRTS=false
+
+m5stack_dinmeter.build.tarch=xtensa
+m5stack_dinmeter.build.bootloader_addr=0x0
+m5stack_dinmeter.build.target=esp32s3
+m5stack_dinmeter.build.mcu=esp32s3
+m5stack_dinmeter.build.core=esp32
+m5stack_dinmeter.build.variant=m5stack_dinmeter
+m5stack_dinmeter.build.board=M5STACK_DINMETER
+
+m5stack_dinmeter.build.usb_mode=1
+m5stack_dinmeter.build.cdc_on_boot=1
+m5stack_dinmeter.build.msc_on_boot=0
+m5stack_dinmeter.build.dfu_on_boot=0
+m5stack_dinmeter.build.f_cpu=240000000L
+m5stack_dinmeter.build.flash_size=8MB
+m5stack_dinmeter.build.flash_freq=80m
+m5stack_dinmeter.build.flash_mode=dio
+m5stack_dinmeter.build.boot=qio
+m5stack_dinmeter.build.boot_freq=80m
+m5stack_dinmeter.build.partitions=default
+m5stack_dinmeter.build.defines=
+m5stack_dinmeter.build.loop_core=
+m5stack_dinmeter.build.event_core=
+m5stack_dinmeter.build.psram_type=qspi
+m5stack_dinmeter.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+m5stack_dinmeter.menu.JTAGAdapter.default=Disabled
+m5stack_dinmeter.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_dinmeter.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_dinmeter.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+m5stack_dinmeter.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_dinmeter.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_dinmeter.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+m5stack_dinmeter.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_dinmeter.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_dinmeter.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+m5stack_dinmeter.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_dinmeter.menu.PSRAM.disabled=Disabled
+m5stack_dinmeter.menu.PSRAM.disabled.build.defines=
+m5stack_dinmeter.menu.PSRAM.disabled.build.psram_type=qspi
+m5stack_dinmeter.menu.PSRAM.enabled=QSPI PSRAM
+m5stack_dinmeter.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+m5stack_dinmeter.menu.PSRAM.enabled.build.psram_type=qspi
+m5stack_dinmeter.menu.PSRAM.opi=OPI PSRAM
+m5stack_dinmeter.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+m5stack_dinmeter.menu.PSRAM.opi.build.psram_type=opi
+
+m5stack_dinmeter.menu.FlashMode.qio=QIO 80MHz
+m5stack_dinmeter.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_dinmeter.menu.FlashMode.qio.build.boot=qio
+m5stack_dinmeter.menu.FlashMode.qio.build.boot_freq=80m
+m5stack_dinmeter.menu.FlashMode.qio.build.flash_freq=80m
+m5stack_dinmeter.menu.FlashMode.qio120=QIO 120MHz
+m5stack_dinmeter.menu.FlashMode.qio120.build.flash_mode=dio
+m5stack_dinmeter.menu.FlashMode.qio120.build.boot=qio
+m5stack_dinmeter.menu.FlashMode.qio120.build.boot_freq=120m
+m5stack_dinmeter.menu.FlashMode.qio120.build.flash_freq=80m
+m5stack_dinmeter.menu.FlashMode.dio=DIO 80MHz
+m5stack_dinmeter.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_dinmeter.menu.FlashMode.dio.build.boot=dio
+m5stack_dinmeter.menu.FlashMode.dio.build.boot_freq=80m
+m5stack_dinmeter.menu.FlashMode.dio.build.flash_freq=80m
+m5stack_dinmeter.menu.FlashMode.opi=OPI 80MHz
+m5stack_dinmeter.menu.FlashMode.opi.build.flash_mode=dout
+m5stack_dinmeter.menu.FlashMode.opi.build.boot=opi
+m5stack_dinmeter.menu.FlashMode.opi.build.boot_freq=80m
+m5stack_dinmeter.menu.FlashMode.opi.build.flash_freq=80m
+
+m5stack_dinmeter.menu.FlashSize.4M=4MB (32Mb)
+m5stack_dinmeter.menu.FlashSize.4M.build.flash_size=4MB
+m5stack_dinmeter.menu.FlashSize.8M=8MB (64Mb)
+m5stack_dinmeter.menu.FlashSize.8M.build.flash_size=8MB
+m5stack_dinmeter.menu.FlashSize.16M=16MB (128Mb)
+m5stack_dinmeter.menu.FlashSize.16M.build.flash_size=16MB
+m5stack_dinmeter.menu.FlashSize.32M=32MB (256Mb)
+m5stack_dinmeter.menu.FlashSize.32M.build.flash_size=32MB
+
+m5stack_dinmeter.menu.LoopCore.1=Core 1
+m5stack_dinmeter.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+m5stack_dinmeter.menu.LoopCore.0=Core 0
+m5stack_dinmeter.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+m5stack_dinmeter.menu.EventsCore.1=Core 1
+m5stack_dinmeter.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+m5stack_dinmeter.menu.EventsCore.0=Core 0
+m5stack_dinmeter.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+m5stack_dinmeter.menu.USBMode.hwcdc=Hardware CDC and JTAG
+m5stack_dinmeter.menu.USBMode.hwcdc.build.usb_mode=1
+m5stack_dinmeter.menu.USBMode.default=USB-OTG (TinyUSB)
+m5stack_dinmeter.menu.USBMode.default.build.usb_mode=0
+
+m5stack_dinmeter.menu.CDCOnBoot.cdc=Enabled
+m5stack_dinmeter.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_dinmeter.menu.CDCOnBoot.default=Disabled
+m5stack_dinmeter.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+m5stack_dinmeter.menu.MSCOnBoot.default=Disabled
+m5stack_dinmeter.menu.MSCOnBoot.default.build.msc_on_boot=0
+m5stack_dinmeter.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+m5stack_dinmeter.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+m5stack_dinmeter.menu.DFUOnBoot.default=Disabled
+m5stack_dinmeter.menu.DFUOnBoot.default.build.dfu_on_boot=0
+m5stack_dinmeter.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+m5stack_dinmeter.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+m5stack_dinmeter.menu.UploadMode.default=UART0 / Hardware CDC
+m5stack_dinmeter.menu.UploadMode.default.upload.use_1200bps_touch=false
+m5stack_dinmeter.menu.UploadMode.default.upload.wait_for_upload_port=false
+m5stack_dinmeter.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+m5stack_dinmeter.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+m5stack_dinmeter.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+m5stack_dinmeter.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_dinmeter.menu.PartitionScheme.default.build.partitions=default
+m5stack_dinmeter.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_dinmeter.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_dinmeter.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+m5stack_dinmeter.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+m5stack_dinmeter.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+m5stack_dinmeter.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+m5stack_dinmeter.menu.PartitionScheme.minimal.build.partitions=minimal
+m5stack_dinmeter.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_dinmeter.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_dinmeter.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_dinmeter.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_dinmeter.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_dinmeter.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_dinmeter.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_dinmeter.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_dinmeter.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_dinmeter.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_dinmeter.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_dinmeter.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_dinmeter.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_dinmeter.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_dinmeter.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_dinmeter.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+m5stack_dinmeter.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+m5stack_dinmeter.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+m5stack_dinmeter.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+m5stack_dinmeter.menu.PartitionScheme.fatflash.build.partitions=ffat
+m5stack_dinmeter.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+m5stack_dinmeter.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+m5stack_dinmeter.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+m5stack_dinmeter.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+m5stack_dinmeter.menu.PartitionScheme.rainmaker=RainMaker 4MB
+m5stack_dinmeter.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+m5stack_dinmeter.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+m5stack_dinmeter.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+m5stack_dinmeter.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+m5stack_dinmeter.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+m5stack_dinmeter.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+m5stack_dinmeter.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+m5stack_dinmeter.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+m5stack_dinmeter.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+m5stack_dinmeter.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+m5stack_dinmeter.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+m5stack_dinmeter.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+m5stack_dinmeter.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+m5stack_dinmeter.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+m5stack_dinmeter.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+m5stack_dinmeter.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+m5stack_dinmeter.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+m5stack_dinmeter.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+m5stack_dinmeter.menu.PartitionScheme.custom=Custom
+m5stack_dinmeter.menu.PartitionScheme.custom.build.partitions=
+m5stack_dinmeter.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+m5stack_dinmeter.menu.CPUFreq.240=240MHz (WiFi)
+m5stack_dinmeter.menu.CPUFreq.240.build.f_cpu=240000000L
+m5stack_dinmeter.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_dinmeter.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_dinmeter.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_dinmeter.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_dinmeter.menu.CPUFreq.40=40MHz
+m5stack_dinmeter.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_dinmeter.menu.CPUFreq.20=20MHz
+m5stack_dinmeter.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_dinmeter.menu.CPUFreq.10=10MHz
+m5stack_dinmeter.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_dinmeter.menu.UploadSpeed.921600=921600
+m5stack_dinmeter.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_dinmeter.menu.UploadSpeed.115200=115200
+m5stack_dinmeter.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_dinmeter.menu.UploadSpeed.256000.windows=256000
+m5stack_dinmeter.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_dinmeter.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_dinmeter.menu.UploadSpeed.230400=230400
+m5stack_dinmeter.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_dinmeter.menu.UploadSpeed.460800.linux=460800
+m5stack_dinmeter.menu.UploadSpeed.460800.macosx=460800
+m5stack_dinmeter.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_dinmeter.menu.UploadSpeed.512000.windows=512000
+m5stack_dinmeter.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_dinmeter.menu.DebugLevel.none=None
+m5stack_dinmeter.menu.DebugLevel.none.build.code_debug=0
+m5stack_dinmeter.menu.DebugLevel.error=Error
+m5stack_dinmeter.menu.DebugLevel.error.build.code_debug=1
+m5stack_dinmeter.menu.DebugLevel.warn=Warn
+m5stack_dinmeter.menu.DebugLevel.warn.build.code_debug=2
+m5stack_dinmeter.menu.DebugLevel.info=Info
+m5stack_dinmeter.menu.DebugLevel.info.build.code_debug=3
+m5stack_dinmeter.menu.DebugLevel.debug=Debug
+m5stack_dinmeter.menu.DebugLevel.debug.build.code_debug=4
+m5stack_dinmeter.menu.DebugLevel.verbose=Verbose
+m5stack_dinmeter.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_dinmeter.menu.EraseFlash.none=Disabled
+m5stack_dinmeter.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_dinmeter.menu.EraseFlash.all=Enabled
+m5stack_dinmeter.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
-m5stack-core-esp32.name=M5Stack-Core-ESP32
-
-m5stack-core-esp32.upload.tool=esptool_py
-m5stack-core-esp32.upload.maximum_size=1310720
-m5stack-core-esp32.upload.maximum_data_size=327680
-m5stack-core-esp32.upload.wait_for_upload_port=true
-
-m5stack-core-esp32.serial.disableDTR=true
-m5stack-core-esp32.serial.disableRTS=true
-
-m5stack-core-esp32.build.mcu=esp32
-m5stack-core-esp32.build.core=esp32
-m5stack-core-esp32.build.variant=m5stack_core_esp32
-m5stack-core-esp32.build.board=M5Stack_Core_ESP32
-
-m5stack-core-esp32.build.f_cpu=240000000L
-m5stack-core-esp32.build.flash_size=4MB
-m5stack-core-esp32.build.flash_mode=dio
-m5stack-core-esp32.build.boot=dio
-m5stack-core-esp32.build.partitions=default
-m5stack-core-esp32.build.defines=
-
-m5stack-core-esp32.menu.FlashMode.qio=QIO
-m5stack-core-esp32.menu.FlashMode.qio.build.flash_mode=dio
-m5stack-core-esp32.menu.FlashMode.qio.build.boot=qio
-m5stack-core-esp32.menu.FlashMode.dio=DIO
-m5stack-core-esp32.menu.FlashMode.dio.build.flash_mode=dio
-m5stack-core-esp32.menu.FlashMode.dio.build.boot=dio
-m5stack-core-esp32.menu.FlashMode.qout=QOUT
-m5stack-core-esp32.menu.FlashMode.qout.build.flash_mode=dout
-m5stack-core-esp32.menu.FlashMode.qout.build.boot=qout
-m5stack-core-esp32.menu.FlashMode.dout=DOUT
-m5stack-core-esp32.menu.FlashMode.dout.build.flash_mode=dout
-m5stack-core-esp32.menu.FlashMode.dout.build.boot=dout
-
-m5stack-core-esp32.menu.FlashFreq.80=80MHz
-m5stack-core-esp32.menu.FlashFreq.80.build.flash_freq=80m
-m5stack-core-esp32.menu.FlashFreq.40=40MHz
-m5stack-core-esp32.menu.FlashFreq.40.build.flash_freq=40m
-
-m5stack-core-esp32.menu.PartitionScheme.default=Default
-m5stack-core-esp32.menu.PartitionScheme.default.build.partitions=default
-m5stack-core-esp32.menu.PartitionScheme.no_ota=No OTA (Large APP)
-m5stack-core-esp32.menu.PartitionScheme.no_ota.build.partitions=no_ota
-m5stack-core-esp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-m5stack-core-esp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-m5stack-core-esp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-m5stack-core-esp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-
-m5stack-core-esp32.menu.UploadSpeed.921600=921600
-m5stack-core-esp32.menu.UploadSpeed.921600.upload.speed=921600
-m5stack-core-esp32.menu.UploadSpeed.115200=115200
-m5stack-core-esp32.menu.UploadSpeed.115200.upload.speed=115200
-m5stack-core-esp32.menu.UploadSpeed.256000.windows=256000
-m5stack-core-esp32.menu.UploadSpeed.256000.upload.speed=256000
-m5stack-core-esp32.menu.UploadSpeed.230400.windows.upload.speed=256000
-m5stack-core-esp32.menu.UploadSpeed.230400=230400
-m5stack-core-esp32.menu.UploadSpeed.230400.upload.speed=230400
-m5stack-core-esp32.menu.UploadSpeed.460800.linux=460800
-m5stack-core-esp32.menu.UploadSpeed.460800.macosx=460800
-m5stack-core-esp32.menu.UploadSpeed.460800.upload.speed=460800
-m5stack-core-esp32.menu.UploadSpeed.512000.windows=512000
-m5stack-core-esp32.menu.UploadSpeed.512000.upload.speed=512000
-
-m5stack-core-esp32.menu.DebugLevel.none=None
-m5stack-core-esp32.menu.DebugLevel.none.build.code_debug=0
-m5stack-core-esp32.menu.DebugLevel.error=Error
-m5stack-core-esp32.menu.DebugLevel.error.build.code_debug=1
-m5stack-core-esp32.menu.DebugLevel.warn=Warn
-m5stack-core-esp32.menu.DebugLevel.warn.build.code_debug=2
-m5stack-core-esp32.menu.DebugLevel.info=Info
-m5stack-core-esp32.menu.DebugLevel.info.build.code_debug=3
-m5stack-core-esp32.menu.DebugLevel.debug=Debug
-m5stack-core-esp32.menu.DebugLevel.debug.build.code_debug=4
-m5stack-core-esp32.menu.DebugLevel.verbose=Verbose
-m5stack-core-esp32.menu.DebugLevel.verbose.build.code_debug=5
-
-##############################################################
-
-m5stack-fire.name=M5Stack-FIRE
-
-m5stack-fire.upload.tool=esptool_py
-m5stack-fire.upload.maximum_size=6553600
-m5stack-fire.upload.maximum_data_size=4521984
-m5stack-fire.upload.wait_for_upload_port=true
-
-m5stack-fire.serial.disableDTR=true
-m5stack-fire.serial.disableRTS=true
-
-m5stack-fire.build.mcu=esp32
-m5stack-fire.build.core=esp32
-m5stack-fire.build.variant=m5stack_fire
-m5stack-fire.build.board=M5STACK_FIRE
-
-m5stack-fire.build.f_cpu=240000000L
-m5stack-fire.build.flash_size=16MB
-m5stack-fire.build.flash_freq=80m
-m5stack-fire.build.flash_mode=dio
-m5stack-fire.build.boot=dio
-m5stack-fire.build.partitions=default_16MB
-m5stack-fire.build.defines=
-
-m5stack-fire.menu.PSRAM.enabled=Enabled
-m5stack-fire.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
-m5stack-fire.menu.PSRAM.disabled=Disabled
-m5stack-fire.menu.PSRAM.disabled.build.defines=
-
-m5stack-fire.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS)
-m5stack-fire.menu.PartitionScheme.default.build.partitions=default_16MB
-m5stack-fire.menu.PartitionScheme.default.upload.maximum_size=6553600
-m5stack-fire.menu.PartitionScheme.large_spiffs=Large SPIFFS (7 MB)
-m5stack-fire.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
-m5stack-fire.menu.PartitionScheme.large_spiffs.upload.maximum_size=4685824
-
-m5stack-fire.menu.UploadSpeed.921600=921600
-m5stack-fire.menu.UploadSpeed.921600.upload.speed=921600
-m5stack-fire.menu.UploadSpeed.115200=115200
-m5stack-fire.menu.UploadSpeed.115200.upload.speed=115200
-m5stack-fire.menu.UploadSpeed.256000.windows=256000
-m5stack-fire.menu.UploadSpeed.256000.upload.speed=256000
-m5stack-fire.menu.UploadSpeed.230400.windows.upload.speed=256000
-m5stack-fire.menu.UploadSpeed.230400=230400
-m5stack-fire.menu.UploadSpeed.230400.upload.speed=230400
-m5stack-fire.menu.UploadSpeed.460800.linux=460800
-m5stack-fire.menu.UploadSpeed.460800.macosx=460800
-m5stack-fire.menu.UploadSpeed.460800.upload.speed=460800
-m5stack-fire.menu.UploadSpeed.512000.windows=512000
-m5stack-fire.menu.UploadSpeed.512000.upload.speed=512000
-
-m5stack-fire.menu.DebugLevel.none=None
-m5stack-fire.menu.DebugLevel.none.build.code_debug=0
-m5stack-fire.menu.DebugLevel.error=Error
-m5stack-fire.menu.DebugLevel.error.build.code_debug=1
-m5stack-fire.menu.DebugLevel.warn=Warn
-m5stack-fire.menu.DebugLevel.warn.build.code_debug=2
-m5stack-fire.menu.DebugLevel.info=Info
-m5stack-fire.menu.DebugLevel.info.build.code_debug=3
-m5stack-fire.menu.DebugLevel.debug=Debug
-m5stack-fire.menu.DebugLevel.debug.build.code_debug=4
-m5stack-fire.menu.DebugLevel.verbose=Verbose
-m5stack-fire.menu.DebugLevel.verbose.build.code_debug=5
-
-##############################################################
-
-m5stick-c.name=M5Stick-C
-
-m5stick-c.upload.tool=esptool_py
-m5stick-c.upload.maximum_size=1310720
-m5stick-c.upload.maximum_data_size=327680
-m5stick-c.upload.wait_for_upload_port=true
-
-m5stick-c.serial.disableDTR=true
-m5stick-c.serial.disableRTS=true
-
-m5stick-c.build.mcu=esp32
-m5stick-c.build.core=esp32
-m5stick-c.build.variant=m5stick_c
-m5stick-c.build.board=M5Stick_C
-
-m5stick-c.build.f_cpu=240000000L
-m5stick-c.build.flash_size=4MB
-m5stick-c.build.flash_freq=80m
-m5stick-c.build.flash_mode=dio
-m5stick-c.build.boot=dio
-m5stick-c.build.partitions=default
-m5stick-c.build.defines=
-
-m5stick-c.menu.PartitionScheme.default=Default
-m5stick-c.menu.PartitionScheme.default.build.partitions=default
-m5stick-c.menu.PartitionScheme.no_ota=No OTA (Large APP)
-m5stick-c.menu.PartitionScheme.no_ota.build.partitions=no_ota
-m5stick-c.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-m5stick-c.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-m5stick-c.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-m5stick-c.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-
-
-m5stick-c.menu.UploadSpeed.1500000=1500000
-m5stick-c.menu.UploadSpeed.1500000.upload.speed=1500000
-m5stick-c.menu.UploadSpeed.750000=750000
-m5stick-c.menu.UploadSpeed.750000.upload.speed=750000
-m5stick-c.menu.UploadSpeed.500000=500000
-m5stick-c.menu.UploadSpeed.500000.upload.speed=500000
-m5stick-c.menu.UploadSpeed.250000=250000
-m5stick-c.menu.UploadSpeed.250000.upload.speed=250000
-m5stick-c.menu.UploadSpeed.115200=115200
-m5stick-c.menu.UploadSpeed.115200.upload.speed=115200
-
-
-
-m5stick-c.menu.DebugLevel.none=None
-m5stick-c.menu.DebugLevel.none.build.code_debug=0
-m5stick-c.menu.DebugLevel.error=Error
-m5stick-c.menu.DebugLevel.error.build.code_debug=1
-m5stick-c.menu.DebugLevel.warn=Warn
-m5stick-c.menu.DebugLevel.warn.build.code_debug=2
-m5stick-c.menu.DebugLevel.info=Info
-m5stick-c.menu.DebugLevel.info.build.code_debug=3
-m5stick-c.menu.DebugLevel.debug=Debug
-m5stick-c.menu.DebugLevel.debug.build.code_debug=4
-m5stick-c.menu.DebugLevel.verbose=Verbose
-m5stick-c.menu.DebugLevel.verbose.build.code_debug=5
-
-##############################################################
-
-m5stack-atom.name=M5Stack-ATOM
-
-m5stack-atom.upload.tool=esptool_py
-m5stack-atom.upload.maximum_size=1310720
-m5stack-atom.upload.maximum_data_size=327680
-m5stack-atom.upload.wait_for_upload_port=true
-
-m5stack-atom.serial.disableDTR=true
-m5stack-atom.serial.disableRTS=true
-
-m5stack-atom.build.mcu=esp32
-m5stack-atom.build.core=esp32
-m5stack-atom.build.variant=m5stack_atom
-m5stack-atom.build.board=M5Stack_ATOM
-
-m5stack-atom.build.f_cpu=240000000L
-m5stack-atom.build.flash_size=4MB
-m5stack-atom.build.flash_freq=80m
-m5stack-atom.build.flash_mode=dio
-m5stack-atom.build.boot=dio
-m5stack-atom.build.partitions=default
-m5stack-atom.build.defines=
-
-m5stack-atom.menu.PartitionScheme.default=Default
-m5stack-atom.menu.PartitionScheme.default.build.partitions=default
-m5stack-atom.menu.PartitionScheme.no_ota=No OTA (Large APP)
-m5stack-atom.menu.PartitionScheme.no_ota.build.partitions=no_ota
-m5stack-atom.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-m5stack-atom.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-m5stack-atom.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-m5stack-atom.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-
-
-m5stack-atom.menu.UploadSpeed.1500000=1500000
-m5stack-atom.menu.UploadSpeed.1500000.upload.speed=1500000
-m5stack-atom.menu.UploadSpeed.750000=750000
-m5stack-atom.menu.UploadSpeed.750000.upload.speed=750000
-m5stack-atom.menu.UploadSpeed.500000=500000
-m5stack-atom.menu.UploadSpeed.500000.upload.speed=500000
-m5stack-atom.menu.UploadSpeed.250000=250000
-m5stack-atom.menu.UploadSpeed.250000.upload.speed=250000
-m5stack-atom.menu.UploadSpeed.115200=115200
-m5stack-atom.menu.UploadSpeed.115200.upload.speed=115200
-
-
-
-m5stack-atom.menu.DebugLevel.none=None
-m5stack-atom.menu.DebugLevel.none.build.code_debug=0
-m5stack-atom.menu.DebugLevel.error=Error
-m5stack-atom.menu.DebugLevel.error.build.code_debug=1
-m5stack-atom.menu.DebugLevel.warn=Warn
-m5stack-atom.menu.DebugLevel.warn.build.code_debug=2
-m5stack-atom.menu.DebugLevel.info=Info
-m5stack-atom.menu.DebugLevel.info.build.code_debug=3
-m5stack-atom.menu.DebugLevel.debug=Debug
-m5stack-atom.menu.DebugLevel.debug.build.code_debug=4
-m5stack-atom.menu.DebugLevel.verbose=Verbose
-m5stack-atom.menu.DebugLevel.verbose.build.code_debug=5
-
-
-##############################################################
-
-m5stack-core2.name=M5Stack-Core2
-
-m5stack-core2.upload.tool=esptool_py
-m5stack-core2.upload.maximum_size=6553600
-m5stack-core2.upload.maximum_data_size=4521984
-m5stack-core2.upload.wait_for_upload_port=true
-
-m5stack-core2.serial.disableDTR=true
-m5stack-core2.serial.disableRTS=true
-
-m5stack-core2.build.mcu=esp32
-m5stack-core2.build.core=esp32
-m5stack-core2.build.variant=m5stack_core2
-m5stack-core2.build.board=M5STACK_Core2
-
-m5stack-core2.build.f_cpu=240000000L
-m5stack-core2.build.flash_size=16MB
-m5stack-core2.build.flash_freq=80m
-m5stack-core2.build.flash_mode=dio
-m5stack-core2.build.boot=dio
-m5stack-core2.build.partitions=default_16MB
-m5stack-core2.build.defines=
-
-m5stack-core2.menu.PSRAM.enabled=Enabled
-m5stack-core2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
-m5stack-core2.menu.PSRAM.disabled=Disabled
-m5stack-core2.menu.PSRAM.disabled.build.defines=
-
-m5stack-core2.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS)
-m5stack-core2.menu.PartitionScheme.default.build.partitions=default_16MB
-m5stack-core2.menu.PartitionScheme.default.upload.maximum_size=6553600
-m5stack-core2.menu.PartitionScheme.large_spiffs=Large SPIFFS (7 MB)
-m5stack-core2.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
-m5stack-core2.menu.PartitionScheme.large_spiffs.upload.maximum_size=4685824
-
-m5stack-core2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
-m5stack-core2.menu.PartitionScheme.minimal.build.partitions=minimal
-m5stack-core2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
-m5stack-core2.menu.PartitionScheme.no_ota.build.partitions=no_ota
-m5stack-core2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-m5stack-core2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
-m5stack-core2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
-m5stack-core2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
-m5stack-core2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
-m5stack-core2.menu.PartitionScheme.huge_app.build.partitions=huge_app
-m5stack-core2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
-m5stack-core2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
-m5stack-core2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-m5stack-core2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-
-m5stack-core2.menu.CPUFreq.240=240MHz (WiFi/BT)
-m5stack-core2.menu.CPUFreq.240.build.f_cpu=240000000L
-m5stack-core2.menu.CPUFreq.160=160MHz (WiFi/BT)
-m5stack-core2.menu.CPUFreq.160.build.f_cpu=160000000L
-m5stack-core2.menu.CPUFreq.80=80MHz (WiFi/BT)
-m5stack-core2.menu.CPUFreq.80.build.f_cpu=80000000L
-m5stack-core2.menu.CPUFreq.40=40MHz (40MHz XTAL)
-m5stack-core2.menu.CPUFreq.40.build.f_cpu=40000000L
-m5stack-core2.menu.CPUFreq.26=26MHz (26MHz XTAL)
-m5stack-core2.menu.CPUFreq.26.build.f_cpu=26000000L
-m5stack-core2.menu.CPUFreq.20=20MHz (40MHz XTAL)
-m5stack-core2.menu.CPUFreq.20.build.f_cpu=20000000L
-m5stack-core2.menu.CPUFreq.13=13MHz (26MHz XTAL)
-m5stack-core2.menu.CPUFreq.13.build.f_cpu=13000000L
-m5stack-core2.menu.CPUFreq.10=10MHz (40MHz XTAL)
-m5stack-core2.menu.CPUFreq.10.build.f_cpu=10000000L
-
-m5stack-core2.menu.UploadSpeed.921600=921600
-m5stack-core2.menu.UploadSpeed.921600.upload.speed=921600
-m5stack-core2.menu.UploadSpeed.115200=115200
-m5stack-core2.menu.UploadSpeed.115200.upload.speed=115200
-m5stack-core2.menu.UploadSpeed.256000.windows=256000
-m5stack-core2.menu.UploadSpeed.256000.upload.speed=256000
-m5stack-core2.menu.UploadSpeed.230400.windows.upload.speed=256000
-m5stack-core2.menu.UploadSpeed.230400=230400
-m5stack-core2.menu.UploadSpeed.230400.upload.speed=230400
-m5stack-core2.menu.UploadSpeed.460800.linux=460800
-m5stack-core2.menu.UploadSpeed.460800.macosx=460800
-m5stack-core2.menu.UploadSpeed.460800.upload.speed=460800
-m5stack-core2.menu.UploadSpeed.512000.windows=512000
-m5stack-core2.menu.UploadSpeed.512000.upload.speed=512000
-m5stack-core2.menu.UploadSpeed.1500000=1500000
-m5stack-core2.menu.UploadSpeed.1500000.upload.speed=1500000
-
-m5stack-core2.menu.DebugLevel.none=None
-m5stack-core2.menu.DebugLevel.none.build.code_debug=0
-m5stack-core2.menu.DebugLevel.error=Error
-m5stack-core2.menu.DebugLevel.error.build.code_debug=1
-m5stack-core2.menu.DebugLevel.warn=Warn
-m5stack-core2.menu.DebugLevel.warn.build.code_debug=2
-m5stack-core2.menu.DebugLevel.info=Info
-m5stack-core2.menu.DebugLevel.info.build.code_debug=3
-m5stack-core2.menu.DebugLevel.debug=Debug
-m5stack-core2.menu.DebugLevel.debug.build.code_debug=4
-m5stack-core2.menu.DebugLevel.verbose=Verbose
-m5stack-core2.menu.DebugLevel.verbose.build.code_debug=5
-
-##############################################################
-
-m5stack-timer-cam.name=M5Stack-Timer-CAM
-
-m5stack-timer-cam.upload.tool=esptool_py
-m5stack-timer-cam.upload.maximum_size=1310720
-m5stack-timer-cam.upload.maximum_data_size=327680
-m5stack-timer-cam.upload.wait_for_upload_port=true
-
-m5stack-timer-cam.serial.disableDTR=true
-m5stack-timer-cam.serial.disableRTS=true
-
-m5stack-timer-cam.build.mcu=esp32
-m5stack-timer-cam.build.core=esp32
-m5stack-timer-cam.build.variant=m5stack_timer_cam
-m5stack-timer-cam.build.board=M5Stack-Timer-CAM
-
-m5stack-timer-cam.build.f_cpu=240000000L
-m5stack-timer-cam.build.flash_size=4MB
-m5stack-timer-cam.build.flash_freq=80m
-m5stack-timer-cam.build.flash_mode=dio
-m5stack-timer-cam.build.boot=dio
-m5stack-timer-cam.build.partitions=default
-m5stack-timer-cam.build.defines=
-
-m5stack-timer-cam.menu.PSRAM.enabled=Enabled
-m5stack-timer-cam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
-m5stack-timer-cam.menu.PSRAM.disabled=Disabled
-m5stack-timer-cam.menu.PSRAM.disabled.build.defines=
-
-m5stack-timer-cam.menu.PartitionScheme.default=Default(3MB No OTA/1MB SPIFFS)
-m5stack-timer-cam.menu.PartitionScheme.default.build.partitions=huge_app
-m5stack-timer-cam.menu.PartitionScheme.default.upload.maximum_size=3145728
-
-m5stack-timer-cam.menu.PartitionScheme.no_ota=No OTA (Large APP)
-m5stack-timer-cam.menu.PartitionScheme.no_ota.build.partitions=no_ota
-m5stack-timer-cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-
-m5stack-timer-cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-m5stack-timer-cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-m5stack-timer-cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-
-m5stack-timer-cam.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
-m5stack-timer-cam.menu.PartitionScheme.no_ota.build.partitions=no_ota
-m5stack-timer-cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-
-m5stack-timer-cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
-m5stack-timer-cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-m5stack-timer-cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-
-m5stack-timer-cam.menu.CPUFreq.240=240MHz (WiFi/BT)
-m5stack-timer-cam.menu.CPUFreq.240.build.f_cpu=240000000L
-m5stack-timer-cam.menu.CPUFreq.160=160MHz (WiFi/BT)
-m5stack-timer-cam.menu.CPUFreq.160.build.f_cpu=160000000L
-m5stack-timer-cam.menu.CPUFreq.80=80MHz (WiFi/BT)
-m5stack-timer-cam.menu.CPUFreq.80.build.f_cpu=80000000L
-m5stack-timer-cam.menu.CPUFreq.40=40MHz (40MHz XTAL)
-m5stack-timer-cam.menu.CPUFreq.40.build.f_cpu=40000000L
-m5stack-timer-cam.menu.CPUFreq.26=26MHz (26MHz XTAL)
-m5stack-timer-cam.menu.CPUFreq.26.build.f_cpu=26000000L
-m5stack-timer-cam.menu.CPUFreq.20=20MHz (40MHz XTAL)
-m5stack-timer-cam.menu.CPUFreq.20.build.f_cpu=20000000L
-m5stack-timer-cam.menu.CPUFreq.13=13MHz (26MHz XTAL)
-m5stack-timer-cam.menu.CPUFreq.13.build.f_cpu=13000000L
-m5stack-timer-cam.menu.CPUFreq.10=10MHz (40MHz XTAL)
-m5stack-timer-cam.menu.CPUFreq.10.build.f_cpu=10000000L
-
-m5stack-timer-cam.menu.UploadSpeed.1500000=1500000
-m5stack-timer-cam.menu.UploadSpeed.1500000.upload.speed=1500000
-m5stack-timer-cam.menu.UploadSpeed.750000=750000
-m5stack-timer-cam.menu.UploadSpeed.750000.upload.speed=750000
-m5stack-timer-cam.menu.UploadSpeed.500000=500000
-m5stack-timer-cam.menu.UploadSpeed.500000.upload.speed=500000
-m5stack-timer-cam.menu.UploadSpeed.250000=250000
-m5stack-timer-cam.menu.UploadSpeed.250000.upload.speed=250000
-m5stack-timer-cam.menu.UploadSpeed.115200=115200
-m5stack-timer-cam.menu.UploadSpeed.115200.upload.speed=115200
-
-m5stack-timer-cam.menu.DebugLevel.none=None
-m5stack-timer-cam.menu.DebugLevel.none.build.code_debug=0
-m5stack-timer-cam.menu.DebugLevel.error=Error
-m5stack-timer-cam.menu.DebugLevel.error.build.code_debug=1
-m5stack-timer-cam.menu.DebugLevel.warn=Warn
-m5stack-timer-cam.menu.DebugLevel.warn.build.code_debug=2
-m5stack-timer-cam.menu.DebugLevel.info=Info
-m5stack-timer-cam.menu.DebugLevel.info.build.code_debug=3
-m5stack-timer-cam.menu.DebugLevel.debug=Debug
-m5stack-timer-cam.menu.DebugLevel.debug.build.code_debug=4
-m5stack-timer-cam.menu.DebugLevel.verbose=Verbose
-m5stack-timer-cam.menu.DebugLevel.verbose.build.code_debug=5
-
-##############################################################
-
-m5stack-coreink.name=M5Stack-CoreInk
-
-m5stack-coreink.upload.tool=esptool_py
-m5stack-coreink.upload.maximum_size=1310720
-m5stack-coreink.upload.maximum_data_size=327680
-m5stack-coreink.upload.wait_for_upload_port=true
-
-m5stack-coreink.serial.disableDTR=true
-m5stack-coreink.serial.disableRTS=true
-
-m5stack-coreink.build.mcu=esp32
-m5stack-coreink.build.core=esp32
-m5stack-coreink.build.variant=m5stack_coreink
-m5stack-coreink.build.board=M5Stack_CoreInk
-
-m5stack-coreink.build.f_cpu=240000000L
-m5stack-coreink.build.flash_size=4MB
-m5stack-coreink.build.flash_freq=80m
-m5stack-coreink.build.flash_mode=dio
-m5stack-coreink.build.boot=dio
-m5stack-coreink.build.partitions=default
-m5stack-coreink.build.defines=
-
-m5stack-coreink.menu.PartitionScheme.default=Default
-m5stack-coreink.menu.PartitionScheme.default.build.partitions=default
-m5stack-coreink.menu.PartitionScheme.no_ota=No OTA (Large APP)
-m5stack-coreink.menu.PartitionScheme.no_ota.build.partitions=no_ota
-m5stack-coreink.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-m5stack-coreink.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-m5stack-coreink.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-m5stack-coreink.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-
-m5stack-coreink.menu.UploadSpeed.921600=921600
-m5stack-coreink.menu.UploadSpeed.921600.upload.speed=921600
-m5stack-coreink.menu.UploadSpeed.115200=115200
-m5stack-coreink.menu.UploadSpeed.115200.upload.speed=115200
-m5stack-coreink.menu.UploadSpeed.256000.windows=256000
-m5stack-coreink.menu.UploadSpeed.256000.upload.speed=256000
-m5stack-coreink.menu.UploadSpeed.230400.windows.upload.speed=256000
-m5stack-coreink.menu.UploadSpeed.230400=230400
-m5stack-coreink.menu.UploadSpeed.230400.upload.speed=230400
-m5stack-coreink.menu.UploadSpeed.460800.linux=460800
-m5stack-coreink.menu.UploadSpeed.460800.macosx=460800
-m5stack-coreink.menu.UploadSpeed.460800.upload.speed=460800
-m5stack-coreink.menu.UploadSpeed.512000.windows=512000
-m5stack-coreink.menu.UploadSpeed.512000.upload.speed=512000
-m5stack-coreink.menu.UploadSpeed.1500000=1500000
-m5stack-coreink.menu.UploadSpeed.1500000.upload.speed=1500000
-
-m5stack-coreink.menu.DebugLevel.none=None
-m5stack-coreink.menu.DebugLevel.none.build.code_debug=0
-m5stack-coreink.menu.DebugLevel.error=Error
-m5stack-coreink.menu.DebugLevel.error.build.code_debug=1
-m5stack-coreink.menu.DebugLevel.warn=Warn
-m5stack-coreink.menu.DebugLevel.warn.build.code_debug=2
-m5stack-coreink.menu.DebugLevel.info=Info
-m5stack-coreink.menu.DebugLevel.info.build.code_debug=3
-m5stack-coreink.menu.DebugLevel.debug=Debug
-m5stack-coreink.menu.DebugLevel.debug.build.code_debug=4
-m5stack-coreink.menu.DebugLevel.verbose=Verbose
-m5stack-coreink.menu.DebugLevel.verbose.build.code_debug=5
+m5stack_nanoc6.name=M5NanoC6
+
+m5stack_nanoc6.bootloader.tool=esptool_py
+m5stack_nanoc6.bootloader.tool.default=esptool_py
+
+m5stack_nanoc6.upload.tool=esptool_py
+m5stack_nanoc6.upload.tool.default=esptool_py
+m5stack_nanoc6.upload.tool.network=esp_ota
+
+m5stack_nanoc6.upload.maximum_size=1310720
+m5stack_nanoc6.upload.maximum_data_size=327680
+m5stack_nanoc6.upload.flags=
+m5stack_nanoc6.upload.extra_flags=
+m5stack_nanoc6.upload.use_1200bps_touch=false
+m5stack_nanoc6.upload.wait_for_upload_port=false
+
+m5stack_nanoc6.serial.disableDTR=false
+m5stack_nanoc6.serial.disableRTS=false
+
+m5stack_nanoc6.build.tarch=riscv32
+m5stack_nanoc6.build.target=esp
+m5stack_nanoc6.build.mcu=esp32c6
+m5stack_nanoc6.build.core=esp32
+m5stack_nanoc6.build.variant=m5stack_nanoc6
+m5stack_nanoc6.build.board=M5STACK_NANOC6
+m5stack_nanoc6.build.bootloader_addr=0x0
+
+m5stack_nanoc6.build.cdc_on_boot=1
+m5stack_nanoc6.build.f_cpu=160000000L
+m5stack_nanoc6.build.flash_size=4MB
+m5stack_nanoc6.build.flash_freq=80m
+m5stack_nanoc6.build.flash_mode=qio
+m5stack_nanoc6.build.boot=qio
+m5stack_nanoc6.build.partitions=default
+m5stack_nanoc6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+m5stack_nanoc6.menu.JTAGAdapter.default=Disabled
+m5stack_nanoc6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+m5stack_nanoc6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+m5stack_nanoc6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+m5stack_nanoc6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+m5stack_nanoc6.menu.JTAGAdapter.external=FTDI Adapter
+m5stack_nanoc6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+m5stack_nanoc6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+m5stack_nanoc6.menu.JTAGAdapter.bridge=ESP USB Bridge
+m5stack_nanoc6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+m5stack_nanoc6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+m5stack_nanoc6.menu.CDCOnBoot.cdc=Enabled
+m5stack_nanoc6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+m5stack_nanoc6.menu.CDCOnBoot.default=Enabled
+m5stack_nanoc6.menu.CDCOnBoot.default.build.cdc_on_boot=1
+
+m5stack_nanoc6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+m5stack_nanoc6.menu.PartitionScheme.default.build.partitions=default
+m5stack_nanoc6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+m5stack_nanoc6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+m5stack_nanoc6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+m5stack_nanoc6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+m5stack_nanoc6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+m5stack_nanoc6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+m5stack_nanoc6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+m5stack_nanoc6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+m5stack_nanoc6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+m5stack_nanoc6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+m5stack_nanoc6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+m5stack_nanoc6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+m5stack_nanoc6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+m5stack_nanoc6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+m5stack_nanoc6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+m5stack_nanoc6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+m5stack_nanoc6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+m5stack_nanoc6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+m5stack_nanoc6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+m5stack_nanoc6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+m5stack_nanoc6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+m5stack_nanoc6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+m5stack_nanoc6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+
+m5stack_nanoc6.menu.CPUFreq.160=160MHz (WiFi)
+m5stack_nanoc6.menu.CPUFreq.160.build.f_cpu=160000000L
+m5stack_nanoc6.menu.CPUFreq.80=80MHz (WiFi)
+m5stack_nanoc6.menu.CPUFreq.80.build.f_cpu=80000000L
+m5stack_nanoc6.menu.CPUFreq.40=40MHz
+m5stack_nanoc6.menu.CPUFreq.40.build.f_cpu=40000000L
+m5stack_nanoc6.menu.CPUFreq.20=20MHz
+m5stack_nanoc6.menu.CPUFreq.20.build.f_cpu=20000000L
+m5stack_nanoc6.menu.CPUFreq.10=10MHz
+m5stack_nanoc6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+m5stack_nanoc6.menu.FlashMode.qio=QIO
+m5stack_nanoc6.menu.FlashMode.qio.build.flash_mode=dio
+m5stack_nanoc6.menu.FlashMode.qio.build.boot=qio
+m5stack_nanoc6.menu.FlashMode.dio=DIO
+m5stack_nanoc6.menu.FlashMode.dio.build.flash_mode=dio
+m5stack_nanoc6.menu.FlashMode.dio.build.boot=dio
+
+m5stack_nanoc6.menu.FlashFreq.80=80MHz
+m5stack_nanoc6.menu.FlashFreq.80.build.flash_freq=80m
+m5stack_nanoc6.menu.FlashFreq.40=40MHz
+m5stack_nanoc6.menu.FlashFreq.40.build.flash_freq=40m
+
+m5stack_nanoc6.menu.FlashSize.4M=4MB (32Mb)
+m5stack_nanoc6.menu.FlashSize.4M.build.flash_size=4MB
+
+m5stack_nanoc6.menu.UploadSpeed.921600=921600
+m5stack_nanoc6.menu.UploadSpeed.921600.upload.speed=921600
+m5stack_nanoc6.menu.UploadSpeed.115200=115200
+m5stack_nanoc6.menu.UploadSpeed.115200.upload.speed=115200
+m5stack_nanoc6.menu.UploadSpeed.256000.windows=256000
+m5stack_nanoc6.menu.UploadSpeed.256000.upload.speed=256000
+m5stack_nanoc6.menu.UploadSpeed.230400.windows.upload.speed=256000
+m5stack_nanoc6.menu.UploadSpeed.230400=230400
+m5stack_nanoc6.menu.UploadSpeed.230400.upload.speed=230400
+m5stack_nanoc6.menu.UploadSpeed.460800.linux=460800
+m5stack_nanoc6.menu.UploadSpeed.460800.macosx=460800
+m5stack_nanoc6.menu.UploadSpeed.460800.upload.speed=460800
+m5stack_nanoc6.menu.UploadSpeed.512000.windows=512000
+m5stack_nanoc6.menu.UploadSpeed.512000.upload.speed=512000
+
+m5stack_nanoc6.menu.DebugLevel.none=None
+m5stack_nanoc6.menu.DebugLevel.none.build.code_debug=0
+m5stack_nanoc6.menu.DebugLevel.error=Error
+m5stack_nanoc6.menu.DebugLevel.error.build.code_debug=1
+m5stack_nanoc6.menu.DebugLevel.warn=Warn
+m5stack_nanoc6.menu.DebugLevel.warn.build.code_debug=2
+m5stack_nanoc6.menu.DebugLevel.info=Info
+m5stack_nanoc6.menu.DebugLevel.info.build.code_debug=3
+m5stack_nanoc6.menu.DebugLevel.debug=Debug
+m5stack_nanoc6.menu.DebugLevel.debug.build.code_debug=4
+m5stack_nanoc6.menu.DebugLevel.verbose=Verbose
+m5stack_nanoc6.menu.DebugLevel.verbose.build.code_debug=5
+
+m5stack_nanoc6.menu.EraseFlash.none=Disabled
+m5stack_nanoc6.menu.EraseFlash.none.upload.erase_cmd=
+m5stack_nanoc6.menu.EraseFlash.all=Enabled
+m5stack_nanoc6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+m5stack_nanoc6.menu.ZigbeeMode.default=Disabled
+m5stack_nanoc6.menu.ZigbeeMode.default.build.zigbee_mode=
+m5stack_nanoc6.menu.ZigbeeMode.default.build.zigbee_libs=
+m5stack_nanoc6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+m5stack_nanoc6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+m5stack_nanoc6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+m5stack_nanoc6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+m5stack_nanoc6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+m5stack_nanoc6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
 
 ##############################################################
 
 odroid_esp32.name=ODROID ESP32
 
+odroid_esp32.bootloader.tool=esptool_py
+odroid_esp32.bootloader.tool.default=esptool_py
+
 odroid_esp32.upload.tool=esptool_py
+odroid_esp32.upload.tool.default=esptool_py
+odroid_esp32.upload.tool.network=esp_ota
+
 odroid_esp32.upload.maximum_size=1310720
 odroid_esp32.upload.maximum_data_size=327680
-odroid_esp32.upload.wait_for_upload_port=true
+odroid_esp32.upload.flags=
+odroid_esp32.upload.extra_flags=
 
 odroid_esp32.serial.disableDTR=true
 odroid_esp32.serial.disableRTS=true
 
+odroid_esp32.build.tarch=xtensa
+odroid_esp32.build.bootloader_addr=0x1000
+odroid_esp32.build.target=esp32
 odroid_esp32.build.mcu=esp32
 odroid_esp32.build.core=esp32
 odroid_esp32.build.variant=odroid_esp32
@@ -3001,7 +24809,8 @@ odroid_esp32.build.flash_size=16MB
 odroid_esp32.build.flash_mode=dio
 odroid_esp32.build.boot=dio
 odroid_esp32.build.partitions=default
-odroid_esp32.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+odroid_esp32.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+odroid_esp32.build.extra_libs=
 
 odroid_esp32.menu.FlashMode.qio=QIO
 odroid_esp32.menu.FlashMode.qio.build.flash_mode=dio
@@ -3009,12 +24818,6 @@ odroid_esp32.menu.FlashMode.qio.build.boot=qio
 odroid_esp32.menu.FlashMode.dio=DIO
 odroid_esp32.menu.FlashMode.dio.build.flash_mode=dio
 odroid_esp32.menu.FlashMode.dio.build.boot=dio
-odroid_esp32.menu.FlashMode.qout=QOUT
-odroid_esp32.menu.FlashMode.qout.build.flash_mode=dout
-odroid_esp32.menu.FlashMode.qout.build.boot=qout
-odroid_esp32.menu.FlashMode.dout=DOUT
-odroid_esp32.menu.FlashMode.dout.build.flash_mode=dout
-odroid_esp32.menu.FlashMode.dout.build.boot=dout
 
 odroid_esp32.menu.FlashFreq.80=80MHz
 odroid_esp32.menu.FlashFreq.80.build.flash_freq=80m
@@ -3058,18 +24861,33 @@ odroid_esp32.menu.DebugLevel.debug.build.code_debug=4
 odroid_esp32.menu.DebugLevel.verbose=Verbose
 odroid_esp32.menu.DebugLevel.verbose.build.code_debug=5
 
+odroid_esp32.menu.EraseFlash.none=Disabled
+odroid_esp32.menu.EraseFlash.none.upload.erase_cmd=
+odroid_esp32.menu.EraseFlash.all=Enabled
+odroid_esp32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 heltec_wifi_kit_32.name=Heltec WiFi Kit 32
 
+heltec_wifi_kit_32.bootloader.tool=esptool_py
+heltec_wifi_kit_32.bootloader.tool.default=esptool_py
+
 heltec_wifi_kit_32.upload.tool=esptool_py
+heltec_wifi_kit_32.upload.tool.default=esptool_py
+heltec_wifi_kit_32.upload.tool.network=esp_ota
+
 heltec_wifi_kit_32.upload.maximum_size=1310720
 heltec_wifi_kit_32.upload.maximum_data_size=327680
-heltec_wifi_kit_32.upload.wait_for_upload_port=true
+heltec_wifi_kit_32.upload.flags=
+heltec_wifi_kit_32.upload.extra_flags=
 
 heltec_wifi_kit_32.serial.disableDTR=true
 heltec_wifi_kit_32.serial.disableRTS=true
 
+heltec_wifi_kit_32.build.tarch=xtensa
+heltec_wifi_kit_32.build.bootloader_addr=0x1000
+heltec_wifi_kit_32.build.target=esp32
 heltec_wifi_kit_32.build.mcu=esp32
 heltec_wifi_kit_32.build.core=esp32
 heltec_wifi_kit_32.build.variant=heltec_wifi_kit_32
@@ -3077,32 +24895,33 @@ heltec_wifi_kit_32.build.board=HELTEC_WIFI_KIT_32
 
 heltec_wifi_kit_32.build.f_cpu=240000000L
 heltec_wifi_kit_32.build.flash_size=4MB
-heltec_wifi_kit_32.build.flash_freq=40m
+heltec_wifi_kit_32.build.flash_freq=80m
 heltec_wifi_kit_32.build.flash_mode=dio
 heltec_wifi_kit_32.build.boot=dio
 heltec_wifi_kit_32.build.partitions=default
 heltec_wifi_kit_32.build.defines=
+heltec_wifi_kit_32.build.band=LoRaWAN_NONE
+heltec_wifi_kit_32.build.LoRaWanDebugLevel=0
 
-heltec_wifi_kit_32.menu.PSRAM.disabled=Disabled
-heltec_wifi_kit_32.menu.PSRAM.disabled.build.defines=
-heltec_wifi_kit_32.menu.PSRAM.enabled=Enabled
-heltec_wifi_kit_32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
-
-heltec_wifi_kit_32.menu.PartitionScheme.default=Default
+heltec_wifi_kit_32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
 heltec_wifi_kit_32.menu.PartitionScheme.default.build.partitions=default
-heltec_wifi_kit_32.menu.PartitionScheme.minimal=Minimal (2MB FLASH)
-heltec_wifi_kit_32.menu.PartitionScheme.minimal.build.partitions=minimal
-heltec_wifi_kit_32.menu.PartitionScheme.no_ota=No OTA (Large APP)
+heltec_wifi_kit_32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+heltec_wifi_kit_32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+heltec_wifi_kit_32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
 heltec_wifi_kit_32.menu.PartitionScheme.no_ota.build.partitions=no_ota
 heltec_wifi_kit_32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-heltec_wifi_kit_32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA)
+heltec_wifi_kit_32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+heltec_wifi_kit_32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+heltec_wifi_kit_32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+heltec_wifi_kit_32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+heltec_wifi_kit_32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+heltec_wifi_kit_32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+heltec_wifi_kit_32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+heltec_wifi_kit_32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+heltec_wifi_kit_32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+heltec_wifi_kit_32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
 heltec_wifi_kit_32.menu.PartitionScheme.huge_app.build.partitions=huge_app
 heltec_wifi_kit_32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
-heltec_wifi_kit_32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-heltec_wifi_kit_32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-heltec_wifi_kit_32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-heltec_wifi_kit_32.menu.PartitionScheme.fatflash=16M Fat
-heltec_wifi_kit_32.menu.PartitionScheme.fatflash.build.partitions=ffat
 
 heltec_wifi_kit_32.menu.CPUFreq.240=240MHz (WiFi/BT)
 heltec_wifi_kit_32.menu.CPUFreq.240.build.f_cpu=240000000L
@@ -3110,37 +24929,6 @@ heltec_wifi_kit_32.menu.CPUFreq.160=160MHz (WiFi/BT)
 heltec_wifi_kit_32.menu.CPUFreq.160.build.f_cpu=160000000L
 heltec_wifi_kit_32.menu.CPUFreq.80=80MHz (WiFi/BT)
 heltec_wifi_kit_32.menu.CPUFreq.80.build.f_cpu=80000000L
-heltec_wifi_kit_32.menu.CPUFreq.26=26MHz (26MHz XTAL)
-heltec_wifi_kit_32.menu.CPUFreq.26.build.f_cpu=26000000L
-heltec_wifi_kit_32.menu.CPUFreq.13=13MHz (26MHz XTAL)
-heltec_wifi_kit_32.menu.CPUFreq.13.build.f_cpu=13000000L
-
-heltec_wifi_kit_32.menu.FlashMode.qio=QIO
-heltec_wifi_kit_32.menu.FlashMode.qio.build.flash_mode=dio
-heltec_wifi_kit_32.menu.FlashMode.qio.build.boot=qio
-heltec_wifi_kit_32.menu.FlashMode.dio=DIO
-heltec_wifi_kit_32.menu.FlashMode.dio.build.flash_mode=dio
-heltec_wifi_kit_32.menu.FlashMode.dio.build.boot=dio
-heltec_wifi_kit_32.menu.FlashMode.qout=QOUT
-heltec_wifi_kit_32.menu.FlashMode.qout.build.flash_mode=dout
-heltec_wifi_kit_32.menu.FlashMode.qout.build.boot=qout
-heltec_wifi_kit_32.menu.FlashMode.dout=DOUT
-heltec_wifi_kit_32.menu.FlashMode.dout.build.flash_mode=dout
-heltec_wifi_kit_32.menu.FlashMode.dout.build.boot=dout
-
-heltec_wifi_kit_32.menu.FlashFreq.40=40MHz
-heltec_wifi_kit_32.menu.FlashFreq.40.build.flash_freq=40m
-heltec_wifi_kit_32.menu.FlashFreq.80=80MHz
-heltec_wifi_kit_32.menu.FlashFreq.80.build.flash_freq=80m
-
-heltec_wifi_kit_32.menu.FlashSize.4M=4MB (32Mb)
-heltec_wifi_kit_32.menu.FlashSize.4M.build.flash_size=4MB
-heltec_wifi_kit_32.menu.FlashSize.2M=2MB (16Mb)
-heltec_wifi_kit_32.menu.FlashSize.2M.build.flash_size=2MB
-heltec_wifi_kit_32.menu.FlashSize.2M.build.partitions=minimal
-heltec_wifi_kit_32.menu.FlashSize.16M=16MB (128Mb)
-heltec_wifi_kit_32.menu.FlashSize.16M.build.flash_size=16MB
-heltec_wifi_kit_32.menu.FlashSize.16M.build.partitions=ffat
 
 heltec_wifi_kit_32.menu.UploadSpeed.921600=921600
 heltec_wifi_kit_32.menu.UploadSpeed.921600.upload.speed=921600
@@ -3170,18 +24958,134 @@ heltec_wifi_kit_32.menu.DebugLevel.debug.build.code_debug=4
 heltec_wifi_kit_32.menu.DebugLevel.verbose=Verbose
 heltec_wifi_kit_32.menu.DebugLevel.verbose.build.code_debug=5
 
+heltec_wifi_kit_32.menu.EraseFlash.none=Disabled
+heltec_wifi_kit_32.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wifi_kit_32.menu.EraseFlash.all=Enabled
+heltec_wifi_kit_32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_wifi_kit_32_V3.name=Heltec WiFi Kit 32(V3)
+
+heltec_wifi_kit_32_V3.bootloader.tool=esptool_py
+heltec_wifi_kit_32_V3.bootloader.tool.default=esptool_py
+
+heltec_wifi_kit_32_V3.upload.tool=esptool_py
+heltec_wifi_kit_32_V3.upload.tool.default=esptool_py
+heltec_wifi_kit_32_V3.upload.tool.network=esp_ota
+
+heltec_wifi_kit_32_V3.upload.maximum_size=3342336
+heltec_wifi_kit_32_V3.upload.maximum_data_size=327680
+heltec_wifi_kit_32_V3.upload.flags=
+heltec_wifi_kit_32_V3.upload.extra_flags=
+heltec_wifi_kit_32_V3.upload.use_1200bps_touch=false
+heltec_wifi_kit_32_V3.upload.wait_for_upload_port=false
+
+heltec_wifi_kit_32_V3.serial.disableDTR=false
+heltec_wifi_kit_32_V3.serial.disableRTS=false
+
+heltec_wifi_kit_32_V3.build.tarch=xtensa
+heltec_wifi_kit_32_V3.build.bootloader_addr=0x0
+heltec_wifi_kit_32_V3.build.target=esp32s3
+heltec_wifi_kit_32_V3.build.mcu=esp32s3
+heltec_wifi_kit_32_V3.build.core=esp32
+heltec_wifi_kit_32_V3.build.variant=heltec_wifi_kit_32_V3
+heltec_wifi_kit_32_V3.build.board=HELTEC_WIFI_KIT_32_V3
+
+heltec_wifi_kit_32_V3.build.usb_mode=1
+heltec_wifi_kit_32_V3.build.cdc_on_boot=0
+heltec_wifi_kit_32_V3.build.msc_on_boot=0
+heltec_wifi_kit_32_V3.build.dfu_on_boot=0
+heltec_wifi_kit_32_V3.build.f_cpu=240000000L
+heltec_wifi_kit_32_V3.build.flash_size=8MB
+heltec_wifi_kit_32_V3.build.flash_freq=80m
+heltec_wifi_kit_32_V3.build.flash_mode=dio
+heltec_wifi_kit_32_V3.build.boot=qio
+heltec_wifi_kit_32_V3.build.boot_freq=80m
+heltec_wifi_kit_32_V3.build.partitions=default_8MB
+heltec_wifi_kit_32_V3.build.loop_core=
+heltec_wifi_kit_32_V3.build.event_core=
+heltec_wifi_kit_32_V3.build.psram_type=qspi
+heltec_wifi_kit_32_V3.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_wifi_kit_32_V3.menu.LoopCore.1=Core 1
+heltec_wifi_kit_32_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_wifi_kit_32_V3.menu.LoopCore.0=Core 0
+heltec_wifi_kit_32_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_wifi_kit_32_V3.menu.EventsCore.1=Core 1
+heltec_wifi_kit_32_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_wifi_kit_32_V3.menu.EventsCore.0=Core 0
+heltec_wifi_kit_32_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_wifi_kit_32_V3.menu.CPUFreq.240=240MHz (WiFi)
+heltec_wifi_kit_32_V3.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_wifi_kit_32_V3.menu.CPUFreq.160=160MHz (WiFi)
+heltec_wifi_kit_32_V3.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wifi_kit_32_V3.menu.CPUFreq.80=80MHz (WiFi)
+heltec_wifi_kit_32_V3.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_wifi_kit_32_V3.menu.CPUFreq.40=40MHz
+heltec_wifi_kit_32_V3.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_wifi_kit_32_V3.menu.CPUFreq.20=20MHz
+heltec_wifi_kit_32_V3.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_wifi_kit_32_V3.menu.CPUFreq.10=10MHz
+heltec_wifi_kit_32_V3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_wifi_kit_32_V3.menu.UploadSpeed.921600=921600
+heltec_wifi_kit_32_V3.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wifi_kit_32_V3.menu.UploadSpeed.115200=115200
+heltec_wifi_kit_32_V3.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wifi_kit_32_V3.menu.UploadSpeed.256000.windows=256000
+heltec_wifi_kit_32_V3.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wifi_kit_32_V3.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wifi_kit_32_V3.menu.UploadSpeed.230400=230400
+heltec_wifi_kit_32_V3.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wifi_kit_32_V3.menu.UploadSpeed.460800.linux=460800
+heltec_wifi_kit_32_V3.menu.UploadSpeed.460800.macosx=460800
+heltec_wifi_kit_32_V3.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wifi_kit_32_V3.menu.UploadSpeed.512000.windows=512000
+heltec_wifi_kit_32_V3.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_wifi_kit_32_V3.menu.DebugLevel.none=None
+heltec_wifi_kit_32_V3.menu.DebugLevel.none.build.code_debug=0
+heltec_wifi_kit_32_V3.menu.DebugLevel.error=Error
+heltec_wifi_kit_32_V3.menu.DebugLevel.error.build.code_debug=1
+heltec_wifi_kit_32_V3.menu.DebugLevel.warn=Warn
+heltec_wifi_kit_32_V3.menu.DebugLevel.warn.build.code_debug=2
+heltec_wifi_kit_32_V3.menu.DebugLevel.info=Info
+heltec_wifi_kit_32_V3.menu.DebugLevel.info.build.code_debug=3
+heltec_wifi_kit_32_V3.menu.DebugLevel.debug=Debug
+heltec_wifi_kit_32_V3.menu.DebugLevel.debug.build.code_debug=4
+heltec_wifi_kit_32_V3.menu.DebugLevel.verbose=Verbose
+heltec_wifi_kit_32_V3.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wifi_kit_32_V3.menu.EraseFlash.none=Disabled
+heltec_wifi_kit_32_V3.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wifi_kit_32_V3.menu.EraseFlash.all=Enabled
+heltec_wifi_kit_32_V3.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 heltec_wifi_lora_32.name=Heltec WiFi LoRa 32
 
+heltec_wifi_lora_32.bootloader.tool=esptool_py
+heltec_wifi_lora_32.bootloader.tool.default=esptool_py
+
 heltec_wifi_lora_32.upload.tool=esptool_py
+heltec_wifi_lora_32.upload.tool.default=esptool_py
+heltec_wifi_lora_32.upload.tool.network=esp_ota
+
 heltec_wifi_lora_32.upload.maximum_size=1310720
 heltec_wifi_lora_32.upload.maximum_data_size=327680
-heltec_wifi_lora_32.upload.wait_for_upload_port=true
+heltec_wifi_lora_32.upload.flags=
+heltec_wifi_lora_32.upload.extra_flags=
 
 heltec_wifi_lora_32.serial.disableDTR=true
 heltec_wifi_lora_32.serial.disableRTS=true
 
+heltec_wifi_lora_32.build.tarch=xtensa
+heltec_wifi_lora_32.build.bootloader_addr=0x1000
+heltec_wifi_lora_32.build.target=esp32
 heltec_wifi_lora_32.build.mcu=esp32
 heltec_wifi_lora_32.build.core=esp32
 heltec_wifi_lora_32.build.variant=heltec_wifi_lora_32
@@ -3189,70 +25093,39 @@ heltec_wifi_lora_32.build.board=HELTEC_WIFI_LORA_32
 
 heltec_wifi_lora_32.build.f_cpu=240000000L
 heltec_wifi_lora_32.build.flash_size=4MB
-heltec_wifi_lora_32.build.flash_freq=40m
+heltec_wifi_lora_32.build.flash_freq=80m
 heltec_wifi_lora_32.build.flash_mode=dio
-heltec_wifi_lora_32.build.boot=dio
+heltec_wifi_lora_32.build.boot=qio
 heltec_wifi_lora_32.build.partitions=default
-heltec_wifi_lora_32.build.defines=
-
-heltec_wifi_lora_32.menu.PSRAM.disabled=Disabled
-heltec_wifi_lora_32.menu.PSRAM.disabled.build.defines=
-heltec_wifi_lora_32.menu.PSRAM.enabled=Enabled
-heltec_wifi_lora_32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+heltec_wifi_lora_32.build.psram=
+heltec_wifi_lora_32.build.defines=-D{build.band} -DMCU_ESP32_D0 -DWIFI_LORA_32 -DHELTEC_BOARD=1 -DRADIO_CHIP_SX127X -DSLOW_CLK_TPYE=0 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH}  -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO}  {build.psram}
 
-heltec_wifi_lora_32.menu.PartitionScheme.default=Default
+heltec_wifi_lora_32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
 heltec_wifi_lora_32.menu.PartitionScheme.default.build.partitions=default
-heltec_wifi_lora_32.menu.PartitionScheme.minimal=Minimal (2MB FLASH)
-heltec_wifi_lora_32.menu.PartitionScheme.minimal.build.partitions=minimal
-heltec_wifi_lora_32.menu.PartitionScheme.no_ota=No OTA (Large APP)
+heltec_wifi_lora_32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+heltec_wifi_lora_32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+heltec_wifi_lora_32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
 heltec_wifi_lora_32.menu.PartitionScheme.no_ota.build.partitions=no_ota
 heltec_wifi_lora_32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-heltec_wifi_lora_32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA)
+heltec_wifi_lora_32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+heltec_wifi_lora_32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+heltec_wifi_lora_32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+heltec_wifi_lora_32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+heltec_wifi_lora_32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+heltec_wifi_lora_32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+heltec_wifi_lora_32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+heltec_wifi_lora_32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+heltec_wifi_lora_32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+heltec_wifi_lora_32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
 heltec_wifi_lora_32.menu.PartitionScheme.huge_app.build.partitions=huge_app
 heltec_wifi_lora_32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
-heltec_wifi_lora_32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-heltec_wifi_lora_32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-heltec_wifi_lora_32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-heltec_wifi_lora_32.menu.PartitionScheme.fatflash=16M Fat
-heltec_wifi_lora_32.menu.PartitionScheme.fatflash.build.partitions=ffat
 
 heltec_wifi_lora_32.menu.CPUFreq.240=240MHz (WiFi/BT)
 heltec_wifi_lora_32.menu.CPUFreq.240.build.f_cpu=240000000L
 heltec_wifi_lora_32.menu.CPUFreq.160=160MHz (WiFi/BT)
 heltec_wifi_lora_32.menu.CPUFreq.160.build.f_cpu=160000000L
 heltec_wifi_lora_32.menu.CPUFreq.80=80MHz (WiFi/BT)
-heltec_wifi_lora_32.menu.CPUFreq.80.build.f_cpu=80000000L
-heltec_wifi_lora_32.menu.CPUFreq.26=26MHz (26MHz XTAL)
-heltec_wifi_lora_32.menu.CPUFreq.26.build.f_cpu=26000000L
-heltec_wifi_lora_32.menu.CPUFreq.13=13MHz (26MHz XTAL)
-heltec_wifi_lora_32.menu.CPUFreq.13.build.f_cpu=13000000L
-
-heltec_wifi_lora_32.menu.FlashMode.qio=QIO
-heltec_wifi_lora_32.menu.FlashMode.qio.build.flash_mode=dio
-heltec_wifi_lora_32.menu.FlashMode.qio.build.boot=qio
-heltec_wifi_lora_32.menu.FlashMode.dio=DIO
-heltec_wifi_lora_32.menu.FlashMode.dio.build.flash_mode=dio
-heltec_wifi_lora_32.menu.FlashMode.dio.build.boot=dio
-heltec_wifi_lora_32.menu.FlashMode.qout=QOUT
-heltec_wifi_lora_32.menu.FlashMode.qout.build.flash_mode=dout
-heltec_wifi_lora_32.menu.FlashMode.qout.build.boot=qout
-heltec_wifi_lora_32.menu.FlashMode.dout=DOUT
-heltec_wifi_lora_32.menu.FlashMode.dout.build.flash_mode=dout
-heltec_wifi_lora_32.menu.FlashMode.dout.build.boot=dout
-
-heltec_wifi_lora_32.menu.FlashFreq.40=40MHz
-heltec_wifi_lora_32.menu.FlashFreq.40.build.flash_freq=40m
-heltec_wifi_lora_32.menu.FlashFreq.80=80MHz
-heltec_wifi_lora_32.menu.FlashFreq.80.build.flash_freq=80m
-
-heltec_wifi_lora_32.menu.FlashSize.4M=4MB (32Mb)
-heltec_wifi_lora_32.menu.FlashSize.4M.build.flash_size=4MB
-heltec_wifi_lora_32.menu.FlashSize.2M=2MB (16Mb)
-heltec_wifi_lora_32.menu.FlashSize.2M.build.flash_size=2MB
-heltec_wifi_lora_32.menu.FlashSize.2M.build.partitions=minimal
-heltec_wifi_lora_32.menu.FlashSize.16M=16MB (128Mb)
-heltec_wifi_lora_32.menu.FlashSize.16M.build.flash_size=16MB
-heltec_wifi_lora_32.menu.FlashSize.16M.build.partitions=ffat
+heltec_wifi_lora_32.menu.CPUFreq.160.build.f_cpu=80000000L
 
 heltec_wifi_lora_32.menu.UploadSpeed.921600=921600
 heltec_wifi_lora_32.menu.UploadSpeed.921600.upload.speed=921600
@@ -3282,18 +25155,74 @@ heltec_wifi_lora_32.menu.DebugLevel.debug.build.code_debug=4
 heltec_wifi_lora_32.menu.DebugLevel.verbose=Verbose
 heltec_wifi_lora_32.menu.DebugLevel.verbose.build.code_debug=5
 
+heltec_wifi_lora_32.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wifi_lora_32.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wifi_lora_32.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wifi_lora_32.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wifi_lora_32.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wifi_lora_32.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wifi_lora_32.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wifi_lora_32.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wifi_lora_32.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wifi_lora_32.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wifi_lora_32.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wifi_lora_32.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wifi_lora_32.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wifi_lora_32.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wifi_lora_32.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wifi_lora_32.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wifi_lora_32.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wifi_lora_32.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wifi_lora_32.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wifi_lora_32.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wifi_lora_32.menu.LoRaWanDebugLevel.0=None
+heltec_wifi_lora_32.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wifi_lora_32.menu.LoRaWanDebugLevel.1=Freq
+heltec_wifi_lora_32.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wifi_lora_32.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wifi_lora_32.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wifi_lora_32.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wifi_lora_32.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wifi_lora_32.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wifi_lora_32.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wifi_lora_32.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wifi_lora_32.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wifi_lora_32.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wifi_lora_32.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wifi_lora_32.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wifi_lora_32.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+
+heltec_wifi_lora_32.menu.EraseFlash.none=Disabled
+heltec_wifi_lora_32.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wifi_lora_32.menu.EraseFlash.all=Enabled
+heltec_wifi_lora_32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 heltec_wifi_lora_32_V2.name=Heltec WiFi LoRa 32(V2)
 
+heltec_wifi_lora_32_V2.bootloader.tool=esptool_py
+heltec_wifi_lora_32_V2.bootloader.tool.default=esptool_py
+
 heltec_wifi_lora_32_V2.upload.tool=esptool_py
-heltec_wifi_lora_32_V2.upload.maximum_size=1310720
+heltec_wifi_lora_32_V2.upload.tool.default=esptool_py
+heltec_wifi_lora_32_V2.upload.tool.network=esp_ota
+
+heltec_wifi_lora_32_V2.upload.maximum_size=3342336
 heltec_wifi_lora_32_V2.upload.maximum_data_size=327680
-heltec_wifi_lora_32_V2.upload.wait_for_upload_port=true
+heltec_wifi_lora_32_V2.upload.flags=
+heltec_wifi_lora_32_V2.upload.extra_flags=
 
 heltec_wifi_lora_32_V2.serial.disableDTR=true
 heltec_wifi_lora_32_V2.serial.disableRTS=true
 
+heltec_wifi_lora_32_V2.build.tarch=xtensa
+heltec_wifi_lora_32_V2.build.bootloader_addr=0x1000
+heltec_wifi_lora_32_V2.build.target=esp32
 heltec_wifi_lora_32_V2.build.mcu=esp32
 heltec_wifi_lora_32_V2.build.core=esp32
 heltec_wifi_lora_32_V2.build.variant=heltec_wifi_lora_32_V2
@@ -3301,33 +25230,12 @@ heltec_wifi_lora_32_V2.build.board=HELTEC_WIFI_LORA_32_V2
 
 heltec_wifi_lora_32_V2.build.f_cpu=240000000L
 heltec_wifi_lora_32_V2.build.flash_size=8MB
-heltec_wifi_lora_32_V2.build.flash_freq=40m
+heltec_wifi_lora_32_V2.build.flash_freq=80m
 heltec_wifi_lora_32_V2.build.flash_mode=dio
-heltec_wifi_lora_32_V2.build.boot=dio
+heltec_wifi_lora_32_V2.build.boot=qio
 heltec_wifi_lora_32_V2.build.partitions=default_8MB
-heltec_wifi_lora_32_V2.build.defines=
-
-heltec_wifi_lora_32_V2.menu.PSRAM.disabled=Disabled
-heltec_wifi_lora_32_V2.menu.PSRAM.disabled.build.defines=
-heltec_wifi_lora_32_V2.menu.PSRAM.enabled=Enabled
-heltec_wifi_lora_32_V2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
-
-heltec_wifi_lora_32_V2.menu.PartitionScheme.default=default_8MB
-heltec_wifi_lora_32_V2.menu.PartitionScheme.default.build.partitions=default_8MB
-heltec_wifi_lora_32_V2.menu.PartitionScheme.default.upload.maximum_size=3342336
-heltec_wifi_lora_32_V2.menu.PartitionScheme.minimal=Minimal (2MB FLASH)
-heltec_wifi_lora_32_V2.menu.PartitionScheme.minimal.build.partitions=minimal
-heltec_wifi_lora_32_V2.menu.PartitionScheme.no_ota=No OTA (Large APP)
-heltec_wifi_lora_32_V2.menu.PartitionScheme.no_ota.build.partitions=no_ota
-heltec_wifi_lora_32_V2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-heltec_wifi_lora_32_V2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA)
-heltec_wifi_lora_32_V2.menu.PartitionScheme.huge_app.build.partitions=huge_app
-heltec_wifi_lora_32_V2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
-heltec_wifi_lora_32_V2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-heltec_wifi_lora_32_V2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-heltec_wifi_lora_32_V2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-heltec_wifi_lora_32_V2.menu.PartitionScheme.fatflash=16M Fat
-heltec_wifi_lora_32_V2.menu.PartitionScheme.fatflash.build.partitions=ffat
+heltec_wifi_lora_32_V2.build.psram=
+heltec_wifi_lora_32_V2.build.defines=-D{build.band} -DMCU_ESP32_D0 -DWIFI_LORA_32_V2 -DHELTEC_BOARD=0 -DRADIO_CHIP_SX127X -DSLOW_CLK_TPYE=0 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH}  -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO}  {build.psram}
 
 heltec_wifi_lora_32_V2.menu.CPUFreq.240=240MHz (WiFi/BT)
 heltec_wifi_lora_32_V2.menu.CPUFreq.240.build.f_cpu=240000000L
@@ -3335,42 +25243,6 @@ heltec_wifi_lora_32_V2.menu.CPUFreq.160=160MHz (WiFi/BT)
 heltec_wifi_lora_32_V2.menu.CPUFreq.160.build.f_cpu=160000000L
 heltec_wifi_lora_32_V2.menu.CPUFreq.80=80MHz (WiFi/BT)
 heltec_wifi_lora_32_V2.menu.CPUFreq.80.build.f_cpu=80000000L
-heltec_wifi_lora_32_V2.menu.CPUFreq.40=40MHz (40MHz XTAL)
-heltec_wifi_lora_32_V2.menu.CPUFreq.40.build.f_cpu=40000000L
-heltec_wifi_lora_32_V2.menu.CPUFreq.20=20MHz (40MHz XTAL)
-heltec_wifi_lora_32_V2.menu.CPUFreq.20.build.f_cpu=20000000L
-heltec_wifi_lora_32_V2.menu.CPUFreq.10=10MHz (40MHz XTAL)
-heltec_wifi_lora_32_V2.menu.CPUFreq.10.build.f_cpu=10000000L
-
-heltec_wifi_lora_32_V2.menu.FlashMode.qio=QIO
-heltec_wifi_lora_32_V2.menu.FlashMode.qio.build.flash_mode=dio
-heltec_wifi_lora_32_V2.menu.FlashMode.qio.build.boot=qio
-heltec_wifi_lora_32_V2.menu.FlashMode.dio=DIO
-heltec_wifi_lora_32_V2.menu.FlashMode.dio.build.flash_mode=dio
-heltec_wifi_lora_32_V2.menu.FlashMode.dio.build.boot=dio
-heltec_wifi_lora_32_V2.menu.FlashMode.qout=QOUT
-heltec_wifi_lora_32_V2.menu.FlashMode.qout.build.flash_mode=dout
-heltec_wifi_lora_32_V2.menu.FlashMode.qout.build.boot=qout
-heltec_wifi_lora_32_V2.menu.FlashMode.dout=DOUT
-heltec_wifi_lora_32_V2.menu.FlashMode.dout.build.flash_mode=dout
-heltec_wifi_lora_32_V2.menu.FlashMode.dout.build.boot=dout
-
-heltec_wifi_lora_32_V2.menu.FlashFreq.80=80MHz
-heltec_wifi_lora_32_V2.menu.FlashFreq.80.build.flash_freq=80m
-heltec_wifi_lora_32_V2.menu.FlashFreq.40=40MHz
-heltec_wifi_lora_32_V2.menu.FlashFreq.40.build.flash_freq=40m
-
-heltec_wifi_lora_32_V2.menu.FlashSize.8M=8MB (64Mb)
-heltec_wifi_lora_32_V2.menu.FlashSize.8M.build.flash_size=8MB
-heltec_wifi_lora_32_V2.menu.FlashSize.8M.build.partitions=default_8MB
-heltec_wifi_lora_32_V2.menu.FlashSize.4M=4MB (32Mb)
-heltec_wifi_lora_32_V2.menu.FlashSize.4M.build.flash_size=4MB
-heltec_wifi_lora_32_V2.menu.FlashSize.2M=2MB (16Mb)
-heltec_wifi_lora_32_V2.menu.FlashSize.2M.build.flash_size=2MB
-heltec_wifi_lora_32_V2.menu.FlashSize.2M.build.partitions=minimal
-heltec_wifi_lora_32_V2.menu.FlashSize.16M=16MB (128Mb)
-heltec_wifi_lora_32_V2.menu.FlashSize.16M.build.flash_size=16MB
-heltec_wifi_lora_32_V2.menu.FlashSize.16M.build.partitions=ffat
 
 heltec_wifi_lora_32_V2.menu.UploadSpeed.921600=921600
 heltec_wifi_lora_32_V2.menu.UploadSpeed.921600.upload.speed=921600
@@ -3400,18 +25272,1269 @@ heltec_wifi_lora_32_V2.menu.DebugLevel.debug.build.code_debug=4
 heltec_wifi_lora_32_V2.menu.DebugLevel.verbose=Verbose
 heltec_wifi_lora_32_V2.menu.DebugLevel.verbose.build.code_debug=5
 
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wifi_lora_32_V2.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.0=None
+heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.1=Freq
+heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wifi_lora_32_V2.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wifi_lora_32_V2.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wifi_lora_32_V2.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wifi_lora_32_V2.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wifi_lora_32_V2.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wifi_lora_32_V2.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wifi_lora_32_V2.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wifi_lora_32_V2.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wifi_lora_32_V2.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wifi_lora_32_V2.menu.EraseFlash.none=Disabled
+heltec_wifi_lora_32_V2.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wifi_lora_32_V2.menu.EraseFlash.all=Enabled
+heltec_wifi_lora_32_V2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_wifi_lora_32_V3.name=Heltec WiFi LoRa 32(V3)
+
+heltec_wifi_lora_32_V3.bootloader.tool=esptool_py
+heltec_wifi_lora_32_V3.bootloader.tool.default=esptool_py
+
+heltec_wifi_lora_32_V3.upload.tool=esptool_py
+heltec_wifi_lora_32_V3.upload.tool.default=esptool_py
+heltec_wifi_lora_32_V3.upload.tool.network=esp_ota
+
+heltec_wifi_lora_32_V3.upload.maximum_size=3342336
+heltec_wifi_lora_32_V3.upload.maximum_data_size=327680
+heltec_wifi_lora_32_V3.upload.flags=
+heltec_wifi_lora_32_V3.upload.extra_flags=
+heltec_wifi_lora_32_V3.upload.use_1200bps_touch=false
+heltec_wifi_lora_32_V3.upload.wait_for_upload_port=false
+
+heltec_wifi_lora_32_V3.serial.disableDTR=false
+heltec_wifi_lora_32_V3.serial.disableRTS=false
+
+heltec_wifi_lora_32_V3.build.tarch=xtensa
+heltec_wifi_lora_32_V3.build.bootloader_addr=0x0
+heltec_wifi_lora_32_V3.build.target=esp32s3
+heltec_wifi_lora_32_V3.build.mcu=esp32s3
+heltec_wifi_lora_32_V3.build.core=esp32
+heltec_wifi_lora_32_V3.build.variant=heltec_wifi_lora_32_V3
+heltec_wifi_lora_32_V3.build.board=HELTEC_WIFI_LORA_32_V3
+
+heltec_wifi_lora_32_V3.build.usb_mode=1
+heltec_wifi_lora_32_V3.build.cdc_on_boot=0
+heltec_wifi_lora_32_V3.build.msc_on_boot=0
+heltec_wifi_lora_32_V3.build.dfu_on_boot=0
+heltec_wifi_lora_32_V3.build.f_cpu=240000000L
+heltec_wifi_lora_32_V3.build.flash_size=8MB
+heltec_wifi_lora_32_V3.build.flash_freq=80m
+heltec_wifi_lora_32_V3.build.flash_mode=dio
+heltec_wifi_lora_32_V3.build.boot=qio
+heltec_wifi_lora_32_V3.build.boot_freq=80m
+heltec_wifi_lora_32_V3.build.partitions=default_8MB
+heltec_wifi_lora_32_V3.build.loop_core=
+heltec_wifi_lora_32_V3.build.event_core=
+heltec_wifi_lora_32_V3.build.psram_type=qspi
+heltec_wifi_lora_32_V3.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_wifi_lora_32_V3.menu.LoopCore.1=Core 1
+heltec_wifi_lora_32_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_wifi_lora_32_V3.menu.LoopCore.0=Core 0
+heltec_wifi_lora_32_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_wifi_lora_32_V3.menu.EventsCore.1=Core 1
+heltec_wifi_lora_32_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_wifi_lora_32_V3.menu.EventsCore.0=Core 0
+heltec_wifi_lora_32_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_wifi_lora_32_V3.menu.CPUFreq.240=240MHz (WiFi)
+heltec_wifi_lora_32_V3.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_wifi_lora_32_V3.menu.CPUFreq.160=160MHz (WiFi)
+heltec_wifi_lora_32_V3.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wifi_lora_32_V3.menu.CPUFreq.80=80MHz (WiFi)
+heltec_wifi_lora_32_V3.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_wifi_lora_32_V3.menu.CPUFreq.40=40MHz
+heltec_wifi_lora_32_V3.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_wifi_lora_32_V3.menu.CPUFreq.20=20MHz
+heltec_wifi_lora_32_V3.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_wifi_lora_32_V3.menu.CPUFreq.10=10MHz
+heltec_wifi_lora_32_V3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_wifi_lora_32_V3.menu.UploadSpeed.921600=921600
+heltec_wifi_lora_32_V3.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wifi_lora_32_V3.menu.UploadSpeed.115200=115200
+heltec_wifi_lora_32_V3.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wifi_lora_32_V3.menu.UploadSpeed.256000.windows=256000
+heltec_wifi_lora_32_V3.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wifi_lora_32_V3.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wifi_lora_32_V3.menu.UploadSpeed.230400=230400
+heltec_wifi_lora_32_V3.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wifi_lora_32_V3.menu.UploadSpeed.460800.linux=460800
+heltec_wifi_lora_32_V3.menu.UploadSpeed.460800.macosx=460800
+heltec_wifi_lora_32_V3.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wifi_lora_32_V3.menu.UploadSpeed.512000.windows=512000
+heltec_wifi_lora_32_V3.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_wifi_lora_32_V3.menu.DebugLevel.none=None
+heltec_wifi_lora_32_V3.menu.DebugLevel.none.build.code_debug=0
+heltec_wifi_lora_32_V3.menu.DebugLevel.error=Error
+heltec_wifi_lora_32_V3.menu.DebugLevel.error.build.code_debug=1
+heltec_wifi_lora_32_V3.menu.DebugLevel.warn=Warn
+heltec_wifi_lora_32_V3.menu.DebugLevel.warn.build.code_debug=2
+heltec_wifi_lora_32_V3.menu.DebugLevel.info=Info
+heltec_wifi_lora_32_V3.menu.DebugLevel.info.build.code_debug=3
+heltec_wifi_lora_32_V3.menu.DebugLevel.debug=Debug
+heltec_wifi_lora_32_V3.menu.DebugLevel.debug.build.code_debug=4
+heltec_wifi_lora_32_V3.menu.DebugLevel.verbose=Verbose
+heltec_wifi_lora_32_V3.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wifi_lora_32_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.0=None
+heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.1=Freq
+heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wifi_lora_32_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wifi_lora_32_V3.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wifi_lora_32_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wifi_lora_32_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wifi_lora_32_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wifi_lora_32_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wifi_lora_32_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wifi_lora_32_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wifi_lora_32_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wifi_lora_32_V3.menu.SLOW_CLK_TPYE.0=Internal (default)
+heltec_wifi_lora_32_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0
+heltec_wifi_lora_32_V3.menu.SLOW_CLK_TPYE.1=External 32K
+heltec_wifi_lora_32_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1
+
+heltec_wifi_lora_32_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=30 -DWIFI_LORA_32_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_wifi_lora_32_V3.menu.EraseFlash.none=Disabled
+heltec_wifi_lora_32_V3.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wifi_lora_32_V3.menu.EraseFlash.all=Enabled
+heltec_wifi_lora_32_V3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_wireless_stick_V3.name=Heltec Wireless Stick(V3)
+
+heltec_wireless_stick_V3.bootloader.tool=esptool_py
+heltec_wireless_stick_V3.bootloader.tool.default=esptool_py
+
+heltec_wireless_stick_V3.upload.tool=esptool_py
+heltec_wireless_stick_V3.upload.tool.default=esptool_py
+heltec_wireless_stick_V3.upload.tool.network=esp_ota
+
+heltec_wireless_stick_V3.upload.maximum_size=3342336
+heltec_wireless_stick_V3.upload.maximum_data_size=327680
+heltec_wireless_stick_V3.upload.flags=
+heltec_wireless_stick_V3.upload.extra_flags=
+heltec_wireless_stick_V3.upload.use_1200bps_touch=false
+heltec_wireless_stick_V3.upload.wait_for_upload_port=false
+
+heltec_wireless_stick_V3.serial.disableDTR=false
+heltec_wireless_stick_V3.serial.disableRTS=false
+
+heltec_wireless_stick_V3.build.tarch=xtensa
+heltec_wireless_stick_V3.build.bootloader_addr=0x0
+heltec_wireless_stick_V3.build.target=esp32s3
+heltec_wireless_stick_V3.build.mcu=esp32s3
+heltec_wireless_stick_V3.build.core=esp32
+heltec_wireless_stick_V3.build.variant=heltec_wireless_stick_v3
+heltec_wireless_stick_V3.build.board=HELTEC_WIRELESS_STICK_V3
+
+heltec_wireless_stick_V3.build.usb_mode=1
+heltec_wireless_stick_V3.build.cdc_on_boot=0
+heltec_wireless_stick_V3.build.msc_on_boot=0
+heltec_wireless_stick_V3.build.dfu_on_boot=0
+heltec_wireless_stick_V3.build.f_cpu=240000000L
+heltec_wireless_stick_V3.build.flash_size=8MB
+heltec_wireless_stick_V3.build.flash_freq=80m
+heltec_wireless_stick_V3.build.flash_mode=dio
+heltec_wireless_stick_V3.build.boot=qio
+heltec_wireless_stick_V3.build.boot_freq=80m
+heltec_wireless_stick_V3.build.partitions=default_8MB
+heltec_wireless_stick_V3.build.loop_core=
+heltec_wireless_stick_V3.build.event_core=
+heltec_wireless_stick_V3.build.psram_type=qspi
+heltec_wireless_stick_V3.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_wireless_stick_V3.menu.LoopCore.1=Core 1
+heltec_wireless_stick_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_wireless_stick_V3.menu.LoopCore.0=Core 0
+heltec_wireless_stick_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_wireless_stick_V3.menu.EventsCore.1=Core 1
+heltec_wireless_stick_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_wireless_stick_V3.menu.EventsCore.0=Core 0
+heltec_wireless_stick_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_wireless_stick_V3.menu.CPUFreq.240=240MHz (WiFi)
+heltec_wireless_stick_V3.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_wireless_stick_V3.menu.CPUFreq.160=160MHz (WiFi)
+heltec_wireless_stick_V3.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wireless_stick_V3.menu.CPUFreq.80=80MHz (WiFi)
+heltec_wireless_stick_V3.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_wireless_stick_V3.menu.CPUFreq.40=40MHz
+heltec_wireless_stick_V3.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_wireless_stick_V3.menu.CPUFreq.20=20MHz
+heltec_wireless_stick_V3.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_wireless_stick_V3.menu.CPUFreq.10=10MHz
+heltec_wireless_stick_V3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_wireless_stick_V3.menu.UploadSpeed.921600=921600
+heltec_wireless_stick_V3.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wireless_stick_V3.menu.UploadSpeed.115200=115200
+heltec_wireless_stick_V3.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wireless_stick_V3.menu.UploadSpeed.256000.windows=256000
+heltec_wireless_stick_V3.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wireless_stick_V3.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wireless_stick_V3.menu.UploadSpeed.230400=230400
+heltec_wireless_stick_V3.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wireless_stick_V3.menu.UploadSpeed.460800.linux=460800
+heltec_wireless_stick_V3.menu.UploadSpeed.460800.macosx=460800
+heltec_wireless_stick_V3.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wireless_stick_V3.menu.UploadSpeed.512000.windows=512000
+heltec_wireless_stick_V3.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_wireless_stick_V3.menu.DebugLevel.none=None
+heltec_wireless_stick_V3.menu.DebugLevel.none.build.code_debug=0
+heltec_wireless_stick_V3.menu.DebugLevel.error=Error
+heltec_wireless_stick_V3.menu.DebugLevel.error.build.code_debug=1
+heltec_wireless_stick_V3.menu.DebugLevel.warn=Warn
+heltec_wireless_stick_V3.menu.DebugLevel.warn.build.code_debug=2
+heltec_wireless_stick_V3.menu.DebugLevel.info=Info
+heltec_wireless_stick_V3.menu.DebugLevel.info.build.code_debug=3
+heltec_wireless_stick_V3.menu.DebugLevel.debug=Debug
+heltec_wireless_stick_V3.menu.DebugLevel.debug.build.code_debug=4
+heltec_wireless_stick_V3.menu.DebugLevel.verbose=Verbose
+heltec_wireless_stick_V3.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wireless_stick_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.0=None
+heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.1=Freq
+heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wireless_stick_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wireless_stick_V3.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wireless_stick_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wireless_stick_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wireless_stick_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wireless_stick_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wireless_stick_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wireless_stick_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wireless_stick_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wireless_stick_V3.menu.SLOW_CLK_TPYE.0=Internal (default)
+heltec_wireless_stick_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0
+heltec_wireless_stick_V3.menu.SLOW_CLK_TPYE.1=External 32K
+heltec_wireless_stick_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1
+
+heltec_wireless_stick_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=31 -DWIRELESS_STICK_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_wireless_stick_V3.menu.EraseFlash.none=Disabled
+heltec_wireless_stick_V3.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wireless_stick_V3.menu.EraseFlash.all=Enabled
+heltec_wireless_stick_V3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_wireless_stick_lite_V3.name=Heltec Wireless Stick Lite(V3)
+
+heltec_wireless_stick_lite_V3.bootloader.tool=esptool_py
+heltec_wireless_stick_lite_V3.bootloader.tool.default=esptool_py
+
+heltec_wireless_stick_lite_V3.upload.tool=esptool_py
+heltec_wireless_stick_lite_V3.upload.tool.default=esptool_py
+heltec_wireless_stick_lite_V3.upload.tool.network=esp_ota
+
+heltec_wireless_stick_lite_V3.upload.maximum_size=3342336
+heltec_wireless_stick_lite_V3.upload.maximum_data_size=327680
+heltec_wireless_stick_lite_V3.upload.flags=
+heltec_wireless_stick_lite_V3.upload.extra_flags=
+heltec_wireless_stick_lite_V3.upload.use_1200bps_touch=false
+heltec_wireless_stick_lite_V3.upload.wait_for_upload_port=false
+
+heltec_wireless_stick_lite_V3.serial.disableDTR=false
+heltec_wireless_stick_lite_V3.serial.disableRTS=false
+
+heltec_wireless_stick_lite_V3.build.tarch=xtensa
+heltec_wireless_stick_lite_V3.build.bootloader_addr=0x0
+heltec_wireless_stick_lite_V3.build.target=esp32s3
+heltec_wireless_stick_lite_V3.build.mcu=esp32s3
+heltec_wireless_stick_lite_V3.build.core=esp32
+heltec_wireless_stick_lite_V3.build.variant=heltec_wireless_stick_lite_v3
+heltec_wireless_stick_lite_V3.build.board=HELTEC_WIRELESS_STICK_LITE_V3
+
+heltec_wireless_stick_lite_V3.build.usb_mode=1
+heltec_wireless_stick_lite_V3.build.cdc_on_boot=0
+heltec_wireless_stick_lite_V3.build.msc_on_boot=0
+heltec_wireless_stick_lite_V3.build.dfu_on_boot=0
+heltec_wireless_stick_lite_V3.build.f_cpu=240000000L
+heltec_wireless_stick_lite_V3.build.flash_size=8MB
+heltec_wireless_stick_lite_V3.build.flash_freq=80m
+heltec_wireless_stick_lite_V3.build.flash_mode=dio
+heltec_wireless_stick_lite_V3.build.boot=qio
+heltec_wireless_stick_lite_V3.build.boot_freq=80m
+heltec_wireless_stick_lite_V3.build.partitions=default_8MB
+heltec_wireless_stick_lite_V3.build.loop_core=
+heltec_wireless_stick_lite_V3.build.event_core=
+heltec_wireless_stick_lite_V3.build.psram_type=qspi
+heltec_wireless_stick_lite_V3.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_wireless_stick_lite_V3.menu.LoopCore.1=Core 1
+heltec_wireless_stick_lite_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_wireless_stick_lite_V3.menu.LoopCore.0=Core 0
+heltec_wireless_stick_lite_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_wireless_stick_lite_V3.menu.EventsCore.1=Core 1
+heltec_wireless_stick_lite_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_wireless_stick_lite_V3.menu.EventsCore.0=Core 0
+heltec_wireless_stick_lite_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_wireless_stick_lite_V3.menu.CPUFreq.240=240MHz (WiFi)
+heltec_wireless_stick_lite_V3.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_wireless_stick_lite_V3.menu.CPUFreq.160=160MHz (WiFi)
+heltec_wireless_stick_lite_V3.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wireless_stick_lite_V3.menu.CPUFreq.80=80MHz (WiFi)
+heltec_wireless_stick_lite_V3.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_wireless_stick_lite_V3.menu.CPUFreq.40=40MHz
+heltec_wireless_stick_lite_V3.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_wireless_stick_lite_V3.menu.CPUFreq.20=20MHz
+heltec_wireless_stick_lite_V3.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_wireless_stick_lite_V3.menu.CPUFreq.10=10MHz
+heltec_wireless_stick_lite_V3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.921600=921600
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.115200=115200
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.256000.windows=256000
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.230400=230400
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.460800.linux=460800
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.460800.macosx=460800
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.512000.windows=512000
+heltec_wireless_stick_lite_V3.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_wireless_stick_lite_V3.menu.DebugLevel.none=None
+heltec_wireless_stick_lite_V3.menu.DebugLevel.none.build.code_debug=0
+heltec_wireless_stick_lite_V3.menu.DebugLevel.error=Error
+heltec_wireless_stick_lite_V3.menu.DebugLevel.error.build.code_debug=1
+heltec_wireless_stick_lite_V3.menu.DebugLevel.warn=Warn
+heltec_wireless_stick_lite_V3.menu.DebugLevel.warn.build.code_debug=2
+heltec_wireless_stick_lite_V3.menu.DebugLevel.info=Info
+heltec_wireless_stick_lite_V3.menu.DebugLevel.info.build.code_debug=3
+heltec_wireless_stick_lite_V3.menu.DebugLevel.debug=Debug
+heltec_wireless_stick_lite_V3.menu.DebugLevel.debug.build.code_debug=4
+heltec_wireless_stick_lite_V3.menu.DebugLevel.verbose=Verbose
+heltec_wireless_stick_lite_V3.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wireless_stick_lite_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.0=None
+heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.1=Freq
+heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wireless_stick_lite_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wireless_stick_lite_V3.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wireless_stick_lite_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wireless_stick_lite_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wireless_stick_lite_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wireless_stick_lite_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wireless_stick_lite_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wireless_stick_lite_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wireless_stick_lite_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wireless_stick_lite_V3.menu.SLOW_CLK_TPYE.0=Internal (default)
+heltec_wireless_stick_lite_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0
+heltec_wireless_stick_lite_V3.menu.SLOW_CLK_TPYE.1=External 32K
+heltec_wireless_stick_lite_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1
+
+heltec_wireless_stick_lite_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=32 -DWIRELESS_STICK_LITE_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_wireless_stick_lite_V3.menu.EraseFlash.none=Disabled
+heltec_wireless_stick_lite_V3.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wireless_stick_lite_V3.menu.EraseFlash.all=Enabled
+heltec_wireless_stick_lite_V3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_wireless_shell_V3.name=Heltec Wireless Shell (V3)
+
+heltec_wireless_shell_V3.bootloader.tool=esptool_py
+heltec_wireless_shell_V3.bootloader.tool.default=esptool_py
+
+heltec_wireless_shell_V3.upload.tool=esptool_py
+heltec_wireless_shell_V3.upload.tool.default=esptool_py
+heltec_wireless_shell_V3.upload.tool.network=esp_ota
+
+heltec_wireless_shell_V3.upload.maximum_size=3342336
+heltec_wireless_shell_V3.upload.maximum_data_size=327680
+heltec_wireless_shell_V3.upload.flags=
+heltec_wireless_shell_V3.upload.extra_flags=
+heltec_wireless_shell_V3.upload.use_1200bps_touch=false
+heltec_wireless_shell_V3.upload.wait_for_upload_port=false
+
+heltec_wireless_shell_V3.serial.disableDTR=false
+heltec_wireless_shell_V3.serial.disableRTS=false
+
+heltec_wireless_shell_V3.build.tarch=xtensa
+heltec_wireless_shell_V3.build.bootloader_addr=0x0
+heltec_wireless_shell_V3.build.target=esp32s3
+heltec_wireless_shell_V3.build.mcu=esp32s3
+heltec_wireless_shell_V3.build.core=esp32
+heltec_wireless_shell_V3.build.variant=heltec_wireless_shell_v3
+heltec_wireless_shell_V3.build.board=HELTEC_WIRELESS_SHELL_V3
+
+heltec_wireless_shell_V3.build.usb_mode=1
+heltec_wireless_shell_V3.build.cdc_on_boot=0
+heltec_wireless_shell_V3.build.msc_on_boot=0
+heltec_wireless_shell_V3.build.dfu_on_boot=0
+heltec_wireless_shell_V3.build.f_cpu=240000000L
+heltec_wireless_shell_V3.build.flash_size=8MB
+heltec_wireless_shell_V3.build.flash_freq=80m
+heltec_wireless_shell_V3.build.flash_mode=dio
+heltec_wireless_shell_V3.build.boot=qio
+heltec_wireless_shell_V3.build.boot_freq=80m
+heltec_wireless_shell_V3.build.partitions=default_8MB
+heltec_wireless_shell_V3.build.loop_core=
+heltec_wireless_shell_V3.build.event_core=
+heltec_wireless_shell_V3.build.psram_type=qspi
+heltec_wireless_shell_V3.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_wireless_shell_V3.menu.LoopCore.1=Core 1
+heltec_wireless_shell_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_wireless_shell_V3.menu.LoopCore.0=Core 0
+heltec_wireless_shell_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_wireless_shell_V3.menu.EventsCore.1=Core 1
+heltec_wireless_shell_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_wireless_shell_V3.menu.EventsCore.0=Core 0
+heltec_wireless_shell_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_wireless_shell_V3.menu.CPUFreq.240=240MHz (WiFi)
+heltec_wireless_shell_V3.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_wireless_shell_V3.menu.CPUFreq.160=160MHz (WiFi)
+heltec_wireless_shell_V3.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wireless_shell_V3.menu.CPUFreq.80=80MHz (WiFi)
+heltec_wireless_shell_V3.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_wireless_shell_V3.menu.CPUFreq.40=40MHz
+heltec_wireless_shell_V3.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_wireless_shell_V3.menu.CPUFreq.20=20MHz
+heltec_wireless_shell_V3.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_wireless_shell_V3.menu.CPUFreq.10=10MHz
+heltec_wireless_shell_V3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_wireless_shell_V3.menu.UploadSpeed.921600=921600
+heltec_wireless_shell_V3.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wireless_shell_V3.menu.UploadSpeed.115200=115200
+heltec_wireless_shell_V3.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wireless_shell_V3.menu.UploadSpeed.256000.windows=256000
+heltec_wireless_shell_V3.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wireless_shell_V3.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wireless_shell_V3.menu.UploadSpeed.230400=230400
+heltec_wireless_shell_V3.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wireless_shell_V3.menu.UploadSpeed.460800.linux=460800
+heltec_wireless_shell_V3.menu.UploadSpeed.460800.macosx=460800
+heltec_wireless_shell_V3.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wireless_shell_V3.menu.UploadSpeed.512000.windows=512000
+heltec_wireless_shell_V3.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_wireless_shell_V3.menu.DebugLevel.none=None
+heltec_wireless_shell_V3.menu.DebugLevel.none.build.code_debug=0
+heltec_wireless_shell_V3.menu.DebugLevel.error=Error
+heltec_wireless_shell_V3.menu.DebugLevel.error.build.code_debug=1
+heltec_wireless_shell_V3.menu.DebugLevel.warn=Warn
+heltec_wireless_shell_V3.menu.DebugLevel.warn.build.code_debug=2
+heltec_wireless_shell_V3.menu.DebugLevel.info=Info
+heltec_wireless_shell_V3.menu.DebugLevel.info.build.code_debug=3
+heltec_wireless_shell_V3.menu.DebugLevel.debug=Debug
+heltec_wireless_shell_V3.menu.DebugLevel.debug.build.code_debug=4
+heltec_wireless_shell_V3.menu.DebugLevel.verbose=Verbose
+heltec_wireless_shell_V3.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wireless_shell_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.0=None
+heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.1=Freq
+heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wireless_shell_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wireless_shell_V3.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wireless_shell_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wireless_shell_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wireless_shell_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wireless_shell_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wireless_shell_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wireless_shell_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wireless_shell_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wireless_shell_V3.menu.SLOW_CLK_TPYE.0=Internal (default)
+heltec_wireless_shell_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0
+heltec_wireless_shell_V3.menu.SLOW_CLK_TPYE.1=External 32K
+heltec_wireless_shell_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1
+
+heltec_wireless_shell_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=33 -DWIRELESS_SHELL_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_wireless_shell_V3.menu.EraseFlash.none=Disabled
+heltec_wireless_shell_V3.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wireless_shell_V3.menu.EraseFlash.all=Enabled
+heltec_wireless_shell_V3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_capsule_sensor_V3.name=Heltec Capsule Sensor (V3)
+
+heltec_capsule_sensor_V3.bootloader.tool=esptool_py
+heltec_capsule_sensor_V3.bootloader.tool.default=esptool_py
+
+heltec_capsule_sensor_V3.upload.tool=esptool_py
+heltec_capsule_sensor_V3.upload.tool.default=esptool_py
+heltec_capsule_sensor_V3.upload.tool.network=esp_ota
+
+heltec_capsule_sensor_V3.upload.maximum_size=3342336
+heltec_capsule_sensor_V3.upload.maximum_data_size=327680
+heltec_capsule_sensor_V3.upload.flags=
+heltec_capsule_sensor_V3.upload.extra_flags=
+heltec_capsule_sensor_V3.upload.use_1200bps_touch=false
+heltec_capsule_sensor_V3.upload.wait_for_upload_port=false
+
+heltec_capsule_sensor_V3.serial.disableDTR=false
+heltec_capsule_sensor_V3.serial.disableRTS=false
+
+heltec_capsule_sensor_V3.build.tarch=xtensa
+heltec_capsule_sensor_V3.build.bootloader_addr=0x0
+heltec_capsule_sensor_V3.build.target=esp32s3
+heltec_capsule_sensor_V3.build.mcu=esp32s3
+heltec_capsule_sensor_V3.build.core=esp32
+heltec_capsule_sensor_V3.build.variant=heltec_capsule_sensor_v3
+heltec_capsule_sensor_V3.build.board=HELTEC_CAPSULE_SENSOR_V3
+
+heltec_capsule_sensor_V3.build.usb_mode=1
+heltec_capsule_sensor_V3.build.cdc_on_boot=0
+heltec_capsule_sensor_V3.build.msc_on_boot=0
+heltec_capsule_sensor_V3.build.dfu_on_boot=0
+heltec_capsule_sensor_V3.build.f_cpu=240000000L
+heltec_capsule_sensor_V3.build.flash_size=8MB
+heltec_capsule_sensor_V3.build.flash_freq=80m
+heltec_capsule_sensor_V3.build.flash_mode=dio
+heltec_capsule_sensor_V3.build.boot=qio
+heltec_capsule_sensor_V3.build.boot_freq=80m
+heltec_capsule_sensor_V3.build.partitions=partitions
+heltec_capsule_sensor_V3.build.loop_core=
+heltec_capsule_sensor_V3.build.event_core=
+heltec_capsule_sensor_V3.build.psram_type=qspi
+heltec_capsule_sensor_V3.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_capsule_sensor_V3.menu.LoopCore.1=Core 1
+heltec_capsule_sensor_V3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_capsule_sensor_V3.menu.LoopCore.0=Core 0
+heltec_capsule_sensor_V3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_capsule_sensor_V3.menu.EventsCore.1=Core 1
+heltec_capsule_sensor_V3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_capsule_sensor_V3.menu.EventsCore.0=Core 0
+heltec_capsule_sensor_V3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_capsule_sensor_V3.menu.CPUFreq.240=240MHz (WiFi)
+heltec_capsule_sensor_V3.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_capsule_sensor_V3.menu.CPUFreq.160=160MHz (WiFi)
+heltec_capsule_sensor_V3.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_capsule_sensor_V3.menu.CPUFreq.80=80MHz (WiFi)
+heltec_capsule_sensor_V3.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_capsule_sensor_V3.menu.CPUFreq.40=40MHz
+heltec_capsule_sensor_V3.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_capsule_sensor_V3.menu.CPUFreq.20=20MHz
+heltec_capsule_sensor_V3.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_capsule_sensor_V3.menu.CPUFreq.10=10MHz
+heltec_capsule_sensor_V3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_capsule_sensor_V3.menu.UploadSpeed.921600=921600
+heltec_capsule_sensor_V3.menu.UploadSpeed.921600.upload.speed=921600
+heltec_capsule_sensor_V3.menu.UploadSpeed.115200=115200
+heltec_capsule_sensor_V3.menu.UploadSpeed.115200.upload.speed=115200
+heltec_capsule_sensor_V3.menu.UploadSpeed.256000.windows=256000
+heltec_capsule_sensor_V3.menu.UploadSpeed.256000.upload.speed=256000
+heltec_capsule_sensor_V3.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_capsule_sensor_V3.menu.UploadSpeed.230400=230400
+heltec_capsule_sensor_V3.menu.UploadSpeed.230400.upload.speed=230400
+heltec_capsule_sensor_V3.menu.UploadSpeed.460800.linux=460800
+heltec_capsule_sensor_V3.menu.UploadSpeed.460800.macosx=460800
+heltec_capsule_sensor_V3.menu.UploadSpeed.460800.upload.speed=460800
+heltec_capsule_sensor_V3.menu.UploadSpeed.512000.windows=512000
+heltec_capsule_sensor_V3.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_capsule_sensor_V3.menu.DebugLevel.none=None
+heltec_capsule_sensor_V3.menu.DebugLevel.none.build.code_debug=0
+heltec_capsule_sensor_V3.menu.DebugLevel.error=Error
+heltec_capsule_sensor_V3.menu.DebugLevel.error.build.code_debug=1
+heltec_capsule_sensor_V3.menu.DebugLevel.warn=Warn
+heltec_capsule_sensor_V3.menu.DebugLevel.warn.build.code_debug=2
+heltec_capsule_sensor_V3.menu.DebugLevel.info=Info
+heltec_capsule_sensor_V3.menu.DebugLevel.info.build.code_debug=3
+heltec_capsule_sensor_V3.menu.DebugLevel.debug=Debug
+heltec_capsule_sensor_V3.menu.DebugLevel.debug.build.code_debug=4
+heltec_capsule_sensor_V3.menu.DebugLevel.verbose=Verbose
+heltec_capsule_sensor_V3.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.3=REGION_US915
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_capsule_sensor_V3.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.0=None
+heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.1=Freq
+heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_capsule_sensor_V3.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_capsule_sensor_V3.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_capsule_sensor_V3.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_capsule_sensor_V3.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_capsule_sensor_V3.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_capsule_sensor_V3.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_capsule_sensor_V3.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_capsule_sensor_V3.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_capsule_sensor_V3.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+
+heltec_capsule_sensor_V3.menu.SLOW_CLK_TPYE.0=External 32K (default)
+heltec_capsule_sensor_V3.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=1
+heltec_capsule_sensor_V3.menu.SLOW_CLK_TPYE.1=Internal
+heltec_capsule_sensor_V3.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=0
+
+heltec_capsule_sensor_V3.menu.NetworkLogLevel.0=NONE
+heltec_capsule_sensor_V3.menu.NetworkLogLevel.0.build.NetworkLogLevel=0
+heltec_capsule_sensor_V3.menu.NetworkLogLevel.1=ERROR
+heltec_capsule_sensor_V3.menu.NetworkLogLevel.1.build.NetworkLogLevel=1
+heltec_capsule_sensor_V3.menu.NetworkLogLevel.2=WARN
+heltec_capsule_sensor_V3.menu.NetworkLogLevel.2.build.NetworkLogLevel=2
+heltec_capsule_sensor_V3.menu.NetworkLogLevel.3=INFO
+heltec_capsule_sensor_V3.menu.NetworkLogLevel.3.build.NetworkLogLevel=3
+
+heltec_capsule_sensor_V3.build.defines=-D{build.band} -DMCU_ESP32_S3 -DHELTEC_BOARD=50 -DCAPSULE_SENSOR_V3 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board} -DNLOG_LOCAL_LEVEL={build.NetworkLogLevel}
+
+heltec_capsule_sensor_V3.menu.EraseFlash.none=Disabled
+heltec_capsule_sensor_V3.menu.EraseFlash.none.upload.erase_cmd=
+heltec_capsule_sensor_V3.menu.EraseFlash.all=Enabled
+heltec_capsule_sensor_V3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+#############################################################
+
+heltec_wireless_paper.name=Heltec Wireless Paper
+
+heltec_wireless_paper.bootloader.tool=esptool_py
+heltec_wireless_paper.bootloader.tool.default=esptool_py
+
+heltec_wireless_paper.upload.tool=esptool_py
+heltec_wireless_paper.upload.tool.default=esptool_py
+heltec_wireless_paper.upload.tool.network=esp_ota
+
+heltec_wireless_paper.upload.maximum_size=4026368
+heltec_wireless_paper.upload.maximum_data_size=327680
+heltec_wireless_paper.upload.flags=
+heltec_wireless_paper.upload.extra_flags=
+heltec_wireless_paper.upload.use_1200bps_touch=false
+heltec_wireless_paper.upload.wait_for_upload_port=false
+
+heltec_wireless_paper.serial.disableDTR=false
+heltec_wireless_paper.serial.disableRTS=false
+
+heltec_wireless_paper.build.tarch=xtensa
+heltec_wireless_paper.build.bootloader_addr=0x0
+heltec_wireless_paper.build.target=esp32s3
+heltec_wireless_paper.build.mcu=esp32s3
+heltec_wireless_paper.build.core=esp32
+heltec_wireless_paper.build.variant=heltec_wireless_paper
+heltec_wireless_paper.build.board=HELTEC_WIRELESS_PAPER
+
+heltec_wireless_paper.build.usb_mode=1
+heltec_wireless_paper.build.cdc_on_boot=0
+heltec_wireless_paper.build.msc_on_boot=0
+heltec_wireless_paper.build.dfu_on_boot=0
+heltec_wireless_paper.build.f_cpu=240000000L
+heltec_wireless_paper.build.flash_size=8MB
+heltec_wireless_paper.build.flash_freq=80m
+heltec_wireless_paper.build.flash_mode=dio
+heltec_wireless_paper.build.boot=qio
+heltec_wireless_paper.build.boot_freq=80m
+heltec_wireless_paper.build.partitions=default_8MB
+heltec_wireless_paper.build.loop_core=
+heltec_wireless_paper.build.event_core=
+heltec_wireless_paper.build.psram_type=qspi
+heltec_wireless_paper.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_wireless_paper.menu.LoopCore.1=Core 1
+heltec_wireless_paper.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_wireless_paper.menu.LoopCore.0=Core 0
+heltec_wireless_paper.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_wireless_paper.menu.EventsCore.1=Core 1
+heltec_wireless_paper.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_wireless_paper.menu.EventsCore.0=Core 0
+heltec_wireless_paper.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_wireless_paper.menu.CPUFreq.240=240MHz (WiFi)
+heltec_wireless_paper.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_wireless_paper.menu.CPUFreq.160=160MHz (WiFi)
+heltec_wireless_paper.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wireless_paper.menu.CPUFreq.80=80MHz (WiFi)
+heltec_wireless_paper.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_wireless_paper.menu.CPUFreq.40=40MHz
+heltec_wireless_paper.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_wireless_paper.menu.CPUFreq.20=20MHz
+heltec_wireless_paper.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_wireless_paper.menu.CPUFreq.10=10MHz
+heltec_wireless_paper.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_wireless_paper.menu.UploadSpeed.921600=921600
+heltec_wireless_paper.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wireless_paper.menu.UploadSpeed.115200=115200
+heltec_wireless_paper.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wireless_paper.menu.UploadSpeed.256000.windows=256000
+heltec_wireless_paper.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wireless_paper.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wireless_paper.menu.UploadSpeed.230400=230400
+heltec_wireless_paper.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wireless_paper.menu.UploadSpeed.460800.linux=460800
+heltec_wireless_paper.menu.UploadSpeed.460800.macosx=460800
+heltec_wireless_paper.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wireless_paper.menu.UploadSpeed.512000.windows=512000
+heltec_wireless_paper.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_wireless_paper.menu.DebugLevel.none=None
+heltec_wireless_paper.menu.DebugLevel.none.build.code_debug=0
+heltec_wireless_paper.menu.DebugLevel.error=Error
+heltec_wireless_paper.menu.DebugLevel.error.build.code_debug=1
+heltec_wireless_paper.menu.DebugLevel.warn=Warn
+heltec_wireless_paper.menu.DebugLevel.warn.build.code_debug=2
+heltec_wireless_paper.menu.DebugLevel.info=Info
+heltec_wireless_paper.menu.DebugLevel.info.build.code_debug=3
+heltec_wireless_paper.menu.DebugLevel.debug=Debug
+heltec_wireless_paper.menu.DebugLevel.debug.build.code_debug=4
+heltec_wireless_paper.menu.DebugLevel.verbose=Verbose
+heltec_wireless_paper.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wireless_paper.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wireless_paper.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wireless_paper.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wireless_paper.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wireless_paper.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wireless_paper.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wireless_paper.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wireless_paper.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wireless_paper.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wireless_paper.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wireless_paper.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wireless_paper.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wireless_paper.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wireless_paper.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wireless_paper.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wireless_paper.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wireless_paper.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wireless_paper.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wireless_paper.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wireless_paper.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wireless_paper.menu.LoRaWanDebugLevel.0=None
+heltec_wireless_paper.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wireless_paper.menu.LoRaWanDebugLevel.1=Freq
+heltec_wireless_paper.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wireless_paper.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wireless_paper.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wireless_paper.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wireless_paper.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wireless_paper.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wireless_paper.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wireless_paper.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wireless_paper.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wireless_paper.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wireless_paper.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wireless_paper.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wireless_paper.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wireless_paper.menu.SLOW_CLK_TPYE.0=Internal (default)
+heltec_wireless_paper.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0
+heltec_wireless_paper.menu.SLOW_CLK_TPYE.1=External 32K
+heltec_wireless_paper.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1
+
+heltec_wireless_paper.build.defines=-D{build.band}  -DMCU_ESP32_S3 -DHELTEC_BOARD=60 -DWIRELESS_PAPER -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_wireless_paper.menu.EraseFlash.none=Disabled
+heltec_wireless_paper.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wireless_paper.menu.EraseFlash.all=Enabled
+heltec_wireless_paper.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_wireless_tracker.name=Heltec Wireless Tracker
+
+heltec_wireless_tracker.bootloader.tool=esptool_py
+heltec_wireless_tracker.bootloader.tool.default=esptool_py
+
+heltec_wireless_tracker.upload.tool=esptool_py
+heltec_wireless_tracker.upload.tool.default=esptool_py
+heltec_wireless_tracker.upload.tool.network=esp_ota
+
+heltec_wireless_tracker.upload.maximum_size=3342336
+heltec_wireless_tracker.upload.maximum_data_size=327680
+heltec_wireless_tracker.upload.flags=
+heltec_wireless_tracker.upload.extra_flags=
+heltec_wireless_tracker.upload.use_1200bps_touch=false
+heltec_wireless_tracker.upload.wait_for_upload_port=false
+
+heltec_wireless_tracker.serial.disableDTR=false
+heltec_wireless_tracker.serial.disableRTS=false
+
+heltec_wireless_tracker.build.tarch=xtensa
+heltec_wireless_tracker.build.bootloader_addr=0x0
+heltec_wireless_tracker.build.target=esp32s3
+heltec_wireless_tracker.build.mcu=esp32s3
+heltec_wireless_tracker.build.core=esp32
+heltec_wireless_tracker.build.variant=heltec_wireless_tracker
+heltec_wireless_tracker.build.board=HELTEC_WIRELESS_TRACKER
+
+heltec_wireless_tracker.build.usb_mode=1
+heltec_wireless_tracker.build.cdc_on_boot=0
+heltec_wireless_tracker.build.msc_on_boot=0
+heltec_wireless_tracker.build.dfu_on_boot=0
+heltec_wireless_tracker.build.f_cpu=240000000L
+heltec_wireless_tracker.build.flash_size=8MB
+heltec_wireless_tracker.build.flash_freq=80m
+heltec_wireless_tracker.build.flash_mode=dio
+heltec_wireless_tracker.build.boot=qio
+heltec_wireless_tracker.build.boot_freq=80m
+heltec_wireless_tracker.build.partitions=default_8MB
+heltec_wireless_tracker.build.loop_core=
+heltec_wireless_tracker.build.event_core=
+heltec_wireless_tracker.build.psram_type=qspi
+heltec_wireless_tracker.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_wireless_tracker.menu.LoopCore.1=Core 1
+heltec_wireless_tracker.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_wireless_tracker.menu.LoopCore.0=Core 0
+heltec_wireless_tracker.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_wireless_tracker.menu.EventsCore.1=Core 1
+heltec_wireless_tracker.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_wireless_tracker.menu.EventsCore.0=Core 0
+heltec_wireless_tracker.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_wireless_tracker.menu.USBMode.hwcdc=Hardware CDC and JTAG
+heltec_wireless_tracker.menu.USBMode.hwcdc.build.usb_mode=1
+heltec_wireless_tracker.menu.USBMode.default=USB-OTG (TinyUSB)
+heltec_wireless_tracker.menu.USBMode.default.build.usb_mode=0
+
+heltec_wireless_tracker.menu.CDCOnBoot.default=Enabled
+heltec_wireless_tracker.menu.CDCOnBoot.default.build.cdc_on_boot=1
+heltec_wireless_tracker.menu.CDCOnBoot.cdc=Disabled
+heltec_wireless_tracker.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+heltec_wireless_tracker.menu.MSCOnBoot.default=Disabled
+heltec_wireless_tracker.menu.MSCOnBoot.default.build.msc_on_boot=0
+heltec_wireless_tracker.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+heltec_wireless_tracker.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+heltec_wireless_tracker.menu.DFUOnBoot.default=Disabled
+heltec_wireless_tracker.menu.DFUOnBoot.default.build.dfu_on_boot=0
+heltec_wireless_tracker.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+heltec_wireless_tracker.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+heltec_wireless_tracker.menu.UploadMode.default=UART0 / Hardware CDC
+heltec_wireless_tracker.menu.UploadMode.default.upload.use_1200bps_touch=false
+heltec_wireless_tracker.menu.UploadMode.default.upload.wait_for_upload_port=false
+heltec_wireless_tracker.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+heltec_wireless_tracker.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+heltec_wireless_tracker.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+heltec_wireless_tracker.menu.CPUFreq.240=240MHz (WiFi)
+heltec_wireless_tracker.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_wireless_tracker.menu.CPUFreq.160=160MHz (WiFi)
+heltec_wireless_tracker.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wireless_tracker.menu.CPUFreq.80=80MHz (WiFi)
+heltec_wireless_tracker.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_wireless_tracker.menu.CPUFreq.40=40MHz
+heltec_wireless_tracker.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_wireless_tracker.menu.CPUFreq.20=20MHz
+heltec_wireless_tracker.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_wireless_tracker.menu.CPUFreq.10=10MHz
+heltec_wireless_tracker.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_wireless_tracker.menu.UploadSpeed.921600=921600
+heltec_wireless_tracker.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wireless_tracker.menu.UploadSpeed.115200=115200
+heltec_wireless_tracker.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wireless_tracker.menu.UploadSpeed.256000.windows=256000
+heltec_wireless_tracker.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wireless_tracker.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wireless_tracker.menu.UploadSpeed.230400=230400
+heltec_wireless_tracker.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wireless_tracker.menu.UploadSpeed.460800.linux=460800
+heltec_wireless_tracker.menu.UploadSpeed.460800.macosx=460800
+heltec_wireless_tracker.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wireless_tracker.menu.UploadSpeed.512000.windows=512000
+heltec_wireless_tracker.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_wireless_tracker.menu.DebugLevel.none=None
+heltec_wireless_tracker.menu.DebugLevel.none.build.code_debug=0
+heltec_wireless_tracker.menu.DebugLevel.error=Error
+heltec_wireless_tracker.menu.DebugLevel.error.build.code_debug=1
+heltec_wireless_tracker.menu.DebugLevel.warn=Warn
+heltec_wireless_tracker.menu.DebugLevel.warn.build.code_debug=2
+heltec_wireless_tracker.menu.DebugLevel.info=Info
+heltec_wireless_tracker.menu.DebugLevel.info.build.code_debug=3
+heltec_wireless_tracker.menu.DebugLevel.debug=Debug
+heltec_wireless_tracker.menu.DebugLevel.debug.build.code_debug=4
+heltec_wireless_tracker.menu.DebugLevel.verbose=Verbose
+heltec_wireless_tracker.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wireless_tracker.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wireless_tracker.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wireless_tracker.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wireless_tracker.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wireless_tracker.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wireless_tracker.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wireless_tracker.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wireless_tracker.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wireless_tracker.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wireless_tracker.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wireless_tracker.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wireless_tracker.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wireless_tracker.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wireless_tracker.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wireless_tracker.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wireless_tracker.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wireless_tracker.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wireless_tracker.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wireless_tracker.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wireless_tracker.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wireless_tracker.menu.LoRaWanDebugLevel.0=None
+heltec_wireless_tracker.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wireless_tracker.menu.LoRaWanDebugLevel.1=Freq
+heltec_wireless_tracker.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wireless_tracker.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wireless_tracker.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wireless_tracker.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wireless_tracker.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wireless_tracker.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wireless_tracker.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wireless_tracker.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wireless_tracker.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wireless_tracker.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wireless_tracker.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wireless_tracker.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wireless_tracker.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wireless_tracker.menu.SLOW_CLK_TPYE.0=Internal (default)
+heltec_wireless_tracker.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0
+heltec_wireless_tracker.menu.SLOW_CLK_TPYE.1=External 32K
+heltec_wireless_tracker.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1
+
+heltec_wireless_tracker.build.defines=-D{build.band}  -DMCU_ESP32_S3 -DHELTEC_BOARD=34 -DWIRELESS_TRACKER -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_wireless_tracker.menu.EraseFlash.none=Disabled
+heltec_wireless_tracker.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wireless_tracker.menu.EraseFlash.all=Enabled
+heltec_wireless_tracker.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_wireless_mini_shell.name=Heltec Wireless Mini Shell
+
+heltec_wireless_mini_shell.bootloader.tool=esptool_py
+heltec_wireless_mini_shell.bootloader.tool.default=esptool_py
+
+heltec_wireless_mini_shell.upload.tool=esptool_py
+heltec_wireless_mini_shell.upload.tool.default=esptool_py
+heltec_wireless_mini_shell.upload.tool.network=esp_ota
+
+heltec_wireless_mini_shell.upload.maximum_size=1310720
+heltec_wireless_mini_shell.upload.maximum_data_size=327680
+heltec_wireless_mini_shell.upload.flags=
+heltec_wireless_mini_shell.upload.extra_flags=
+heltec_wireless_mini_shell.upload.use_1200bps_touch=false
+heltec_wireless_mini_shell.upload.wait_for_upload_port=false
+
+heltec_wireless_mini_shell.serial.disableDTR=false
+heltec_wireless_mini_shell.serial.disableRTS=false
+
+heltec_wireless_mini_shell.build.tarch=riscv32
+heltec_wireless_mini_shell.build.target=esp
+heltec_wireless_mini_shell.build.mcu=esp32c3
+heltec_wireless_mini_shell.build.core=esp32
+heltec_wireless_mini_shell.build.variant=heltec_wireless_mini_shell
+heltec_wireless_mini_shell.build.board=HELTEC_WIRELESS_MINI_SHELL
+heltec_wireless_mini_shell.build.bootloader_addr=0x0
+
+heltec_wireless_mini_shell.build.cdc_on_boot=0
+heltec_wireless_mini_shell.build.f_cpu=160000000L
+heltec_wireless_mini_shell.build.flash_size=4MB
+heltec_wireless_mini_shell.build.flash_freq=80m
+heltec_wireless_mini_shell.build.flash_mode=dio
+heltec_wireless_mini_shell.build.boot=qio
+heltec_wireless_mini_shell.build.partitions=default
+
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wireless_mini_shell.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wireless_mini_shell.menu.CPUFreq.160=160MHz (WiFi)
+heltec_wireless_mini_shell.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wireless_mini_shell.menu.CPUFreq.80=80MHz (WiFi)
+heltec_wireless_mini_shell.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_wireless_mini_shell.menu.CPUFreq.40=40MHz
+heltec_wireless_mini_shell.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_wireless_mini_shell.menu.CPUFreq.20=20MHz
+heltec_wireless_mini_shell.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_wireless_mini_shell.menu.CPUFreq.10=10MHz
+heltec_wireless_mini_shell.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_wireless_mini_shell.menu.UploadSpeed.921600=921600
+heltec_wireless_mini_shell.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wireless_mini_shell.menu.UploadSpeed.115200=115200
+heltec_wireless_mini_shell.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wireless_mini_shell.menu.UploadSpeed.256000.windows=256000
+heltec_wireless_mini_shell.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wireless_mini_shell.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wireless_mini_shell.menu.UploadSpeed.230400=230400
+heltec_wireless_mini_shell.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wireless_mini_shell.menu.UploadSpeed.460800.linux=460800
+heltec_wireless_mini_shell.menu.UploadSpeed.460800.macosx=460800
+heltec_wireless_mini_shell.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wireless_mini_shell.menu.UploadSpeed.512000.windows=512000
+heltec_wireless_mini_shell.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_wireless_mini_shell.menu.DebugLevel.none=None
+heltec_wireless_mini_shell.menu.DebugLevel.none.build.code_debug=0
+heltec_wireless_mini_shell.menu.DebugLevel.error=Error
+heltec_wireless_mini_shell.menu.DebugLevel.error.build.code_debug=1
+heltec_wireless_mini_shell.menu.DebugLevel.warn=Warn
+heltec_wireless_mini_shell.menu.DebugLevel.warn.build.code_debug=2
+heltec_wireless_mini_shell.menu.DebugLevel.info=Info
+heltec_wireless_mini_shell.menu.DebugLevel.info.build.code_debug=3
+heltec_wireless_mini_shell.menu.DebugLevel.debug=Debug
+heltec_wireless_mini_shell.menu.DebugLevel.debug.build.code_debug=4
+heltec_wireless_mini_shell.menu.DebugLevel.verbose=Verbose
+heltec_wireless_mini_shell.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.0=None
+heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.1=Freq
+heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wireless_mini_shell.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+
+heltec_wireless_mini_shell.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wireless_mini_shell.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wireless_mini_shell.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wireless_mini_shell.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wireless_mini_shell.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wireless_mini_shell.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wireless_mini_shell.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wireless_mini_shell.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wireless_mini_shell.build.defines=-D{build.band}  -DMCU_ESP32_C3 -DHELTEC_BOARD=70 -DWIRELESS_MINI_SHELL -DSLOW_CLK_TPYE=0 -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+heltec_wireless_mini_shell.menu.EraseFlash.none=Disabled
+heltec_wireless_mini_shell.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wireless_mini_shell.menu.EraseFlash.all=Enabled
+heltec_wireless_mini_shell.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 heltec_wireless_stick.name=Heltec Wireless Stick
 
+heltec_wireless_stick.bootloader.tool=esptool_py
+heltec_wireless_stick.bootloader.tool.default=esptool_py
+
 heltec_wireless_stick.upload.tool=esptool_py
-heltec_wireless_stick.upload.maximum_size=1310720
+heltec_wireless_stick.upload.tool.default=esptool_py
+heltec_wireless_stick.upload.tool.network=esp_ota
+
+heltec_wireless_stick.upload.maximum_size=3342336
 heltec_wireless_stick.upload.maximum_data_size=327680
-heltec_wireless_stick.upload.wait_for_upload_port=true
+heltec_wireless_stick.upload.flags=
+heltec_wireless_stick.upload.extra_flags=
 
 heltec_wireless_stick.serial.disableDTR=true
 heltec_wireless_stick.serial.disableRTS=true
 
+heltec_wireless_stick.build.tarch=xtensa
+heltec_wireless_stick.build.bootloader_addr=0x1000
+heltec_wireless_stick.build.target=esp32
 heltec_wireless_stick.build.mcu=esp32
 heltec_wireless_stick.build.core=esp32
 heltec_wireless_stick.build.variant=heltec_wireless_stick
@@ -3419,33 +26542,12 @@ heltec_wireless_stick.build.board=HELTEC_WIRELESS_STICK
 
 heltec_wireless_stick.build.f_cpu=240000000L
 heltec_wireless_stick.build.flash_size=8MB
-heltec_wireless_stick.build.flash_freq=40m
+heltec_wireless_stick.build.flash_freq=80m
 heltec_wireless_stick.build.flash_mode=dio
 heltec_wireless_stick.build.boot=dio
 heltec_wireless_stick.build.partitions=default_8MB
-heltec_wireless_stick.build.defines=
-
-heltec_wireless_stick.menu.PSRAM.disabled=Disabled
-heltec_wireless_stick.menu.PSRAM.disabled.build.defines=
-heltec_wireless_stick.menu.PSRAM.enabled=Enabled
-heltec_wireless_stick.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
-
-heltec_wireless_stick.menu.PartitionScheme.default=default_8MB
-heltec_wireless_stick.menu.PartitionScheme.default.build.partitions=default_8MB
-heltec_wireless_stick.menu.PartitionScheme.default.upload.maximum_size=3342336
-heltec_wireless_stick.menu.PartitionScheme.minimal=Minimal (2MB FLASH)
-heltec_wireless_stick.menu.PartitionScheme.minimal.build.partitions=minimal
-heltec_wireless_stick.menu.PartitionScheme.no_ota=No OTA (Large APP)
-heltec_wireless_stick.menu.PartitionScheme.no_ota.build.partitions=no_ota
-heltec_wireless_stick.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-heltec_wireless_stick.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA)
-heltec_wireless_stick.menu.PartitionScheme.huge_app.build.partitions=huge_app
-heltec_wireless_stick.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
-heltec_wireless_stick.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-heltec_wireless_stick.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-heltec_wireless_stick.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-heltec_wireless_stick.menu.PartitionScheme.fatflash=16M Fat
-heltec_wireless_stick.menu.PartitionScheme.fatflash.build.partitions=ffat
+heltec_wireless_stick.build.build.psram=
+heltec_wireless_stick.build.defines=-D{build.band}  -DMCU_ESP32_D0 -DHELTEC_BOARD=2 -DWIRELESS_STICK -DSLOW_CLK_TPYE=0 -DRADIO_CHIP_SX127X  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
 
 heltec_wireless_stick.menu.CPUFreq.240=240MHz (WiFi/BT)
 heltec_wireless_stick.menu.CPUFreq.240.build.f_cpu=240000000L
@@ -3453,42 +26555,6 @@ heltec_wireless_stick.menu.CPUFreq.160=160MHz (WiFi/BT)
 heltec_wireless_stick.menu.CPUFreq.160.build.f_cpu=160000000L
 heltec_wireless_stick.menu.CPUFreq.80=80MHz (WiFi/BT)
 heltec_wireless_stick.menu.CPUFreq.80.build.f_cpu=80000000L
-heltec_wireless_stick.menu.CPUFreq.40=40MHz (40MHz XTAL)
-heltec_wireless_stick.menu.CPUFreq.40.build.f_cpu=40000000L
-heltec_wireless_stick.menu.CPUFreq.20=20MHz (40MHz XTAL)
-heltec_wireless_stick.menu.CPUFreq.20.build.f_cpu=20000000L
-heltec_wireless_stick.menu.CPUFreq.10=10MHz (40MHz XTAL)
-heltec_wireless_stick.menu.CPUFreq.10.build.f_cpu=10000000L
-
-heltec_wireless_stick.menu.FlashMode.qio=QIO
-heltec_wireless_stick.menu.FlashMode.qio.build.flash_mode=dio
-heltec_wireless_stick.menu.FlashMode.qio.build.boot=qio
-heltec_wireless_stick.menu.FlashMode.dio=DIO
-heltec_wireless_stick.menu.FlashMode.dio.build.flash_mode=dio
-heltec_wireless_stick.menu.FlashMode.dio.build.boot=dio
-heltec_wireless_stick.menu.FlashMode.qout=QOUT
-heltec_wireless_stick.menu.FlashMode.qout.build.flash_mode=dout
-heltec_wireless_stick.menu.FlashMode.qout.build.boot=qout
-heltec_wireless_stick.menu.FlashMode.dout=DOUT
-heltec_wireless_stick.menu.FlashMode.dout.build.flash_mode=dout
-heltec_wireless_stick.menu.FlashMode.dout.build.boot=dout
-
-heltec_wireless_stick.menu.FlashFreq.80=80MHz
-heltec_wireless_stick.menu.FlashFreq.80.build.flash_freq=80m
-heltec_wireless_stick.menu.FlashFreq.40=40MHz
-heltec_wireless_stick.menu.FlashFreq.40.build.flash_freq=40m
-
-heltec_wireless_stick.menu.FlashSize.8M=8MB (64Mb)
-heltec_wireless_stick.menu.FlashSize.8M.build.flash_size=8MB
-heltec_wireless_stick.menu.FlashSize.2M.build.partitions=default_8MB
-heltec_wireless_stick.menu.FlashSize.4M=4MB (32Mb)
-heltec_wireless_stick.menu.FlashSize.4M.build.flash_size=4MB
-heltec_wireless_stick.menu.FlashSize.2M=2MB (16Mb)
-heltec_wireless_stick.menu.FlashSize.2M.build.flash_size=2MB
-heltec_wireless_stick.menu.FlashSize.2M.build.partitions=minimal
-heltec_wireless_stick.menu.FlashSize.16M=16MB (128Mb)
-heltec_wireless_stick.menu.FlashSize.16M.build.flash_size=16MB
-heltec_wireless_stick.menu.FlashSize.16M.build.partitions=ffat
 
 heltec_wireless_stick.menu.UploadSpeed.921600=921600
 heltec_wireless_stick.menu.UploadSpeed.921600.upload.speed=921600
@@ -3518,18 +26584,953 @@ heltec_wireless_stick.menu.DebugLevel.debug.build.code_debug=4
 heltec_wireless_stick.menu.DebugLevel.verbose=Verbose
 heltec_wireless_stick.menu.DebugLevel.verbose.build.code_debug=5
 
+heltec_wireless_stick.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wireless_stick.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wireless_stick.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wireless_stick.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wireless_stick.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wireless_stick.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wireless_stick.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wireless_stick.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wireless_stick.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wireless_stick.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wireless_stick.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wireless_stick.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wireless_stick.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wireless_stick.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wireless_stick.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wireless_stick.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wireless_stick.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wireless_stick.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wireless_stick.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wireless_stick.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wireless_stick.menu.LoRaWanDebugLevel.0=None
+heltec_wireless_stick.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wireless_stick.menu.LoRaWanDebugLevel.1=Freq
+heltec_wireless_stick.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wireless_stick.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wireless_stick.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wireless_stick.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wireless_stick.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wireless_stick.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wireless_stick.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wireless_stick.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wireless_stick.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wireless_stick.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wireless_stick.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wireless_stick.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wireless_stick.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wireless_stick.menu.EraseFlash.none=Disabled
+heltec_wireless_stick.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wireless_stick.menu.EraseFlash.all=Enabled
+heltec_wireless_stick.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_wireless_stick_lite.name=Heltec Wireless Stick Lite / Wireless Shell
+
+heltec_wireless_stick_lite.bootloader.tool=esptool_py
+heltec_wireless_stick_lite.bootloader.tool.default=esptool_py
+
+heltec_wireless_stick_lite.upload.tool=esptool_py
+heltec_wireless_stick_lite.upload.tool.default=esptool_py
+heltec_wireless_stick_lite.upload.tool.network=esp_ota
+
+heltec_wireless_stick_lite.upload.maximum_size=1310720
+heltec_wireless_stick_lite.upload.maximum_data_size=327680
+heltec_wireless_stick_lite.upload.flags=
+heltec_wireless_stick_lite.upload.extra_flags=
+
+heltec_wireless_stick_lite.serial.disableDTR=true
+heltec_wireless_stick_lite.serial.disableRTS=true
+
+heltec_wireless_stick_lite.build.tarch=xtensa
+heltec_wireless_stick_lite.build.bootloader_addr=0x1000
+heltec_wireless_stick_lite.build.target=esp32
+heltec_wireless_stick_lite.build.mcu=esp32
+heltec_wireless_stick_lite.build.core=esp32
+heltec_wireless_stick_lite.build.variant=heltec_wireless_stick_lite
+heltec_wireless_stick_lite.build.board=HELTEC_WIRELESS_STICK_LITE
+
+heltec_wireless_stick_lite.build.f_cpu=240000000L
+heltec_wireless_stick_lite.build.flash_size=4MB
+heltec_wireless_stick_lite.build.flash_freq=80m
+heltec_wireless_stick_lite.build.flash_mode=dio
+heltec_wireless_stick_lite.build.boot=dio
+heltec_wireless_stick_lite.build.partitions=default
+heltec_wireless_stick_lite.build.psram=
+heltec_wireless_stick_lite.build.defines=-D{build.band}  -DMCU_ESP32_D0 -DHELTEC_BOARD=3 -DWIRELESS_STICK_LITE -DSLOW_CLK_TPYE=0 -DRADIO_CHIP_SX127X -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_wireless_stick_lite.menu.CPUFreq.240=240MHz (WiFi/BT)
+heltec_wireless_stick_lite.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_wireless_stick_lite.menu.CPUFreq.160=160MHz (WiFi/BT)
+heltec_wireless_stick_lite.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wireless_stick_lite.menu.CPUFreq.80=80MHz (WiFi/BT)
+heltec_wireless_stick_lite.menu.CPUFreq.80.build.f_cpu=80000000L
+
+heltec_wireless_stick_lite.menu.UploadSpeed.921600=921600
+heltec_wireless_stick_lite.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wireless_stick_lite.menu.UploadSpeed.115200=115200
+heltec_wireless_stick_lite.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wireless_stick_lite.menu.UploadSpeed.256000.windows=256000
+heltec_wireless_stick_lite.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wireless_stick_lite.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wireless_stick_lite.menu.UploadSpeed.230400=230400
+heltec_wireless_stick_lite.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wireless_stick_lite.menu.UploadSpeed.460800.linux=460800
+heltec_wireless_stick_lite.menu.UploadSpeed.460800.macosx=460800
+heltec_wireless_stick_lite.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wireless_stick_lite.menu.UploadSpeed.512000.windows=512000
+heltec_wireless_stick_lite.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_wireless_stick_lite.menu.DebugLevel.none=None
+heltec_wireless_stick_lite.menu.DebugLevel.none.build.code_debug=0
+heltec_wireless_stick_lite.menu.DebugLevel.error=Error
+heltec_wireless_stick_lite.menu.DebugLevel.error.build.code_debug=1
+heltec_wireless_stick_lite.menu.DebugLevel.warn=Warn
+heltec_wireless_stick_lite.menu.DebugLevel.warn.build.code_debug=2
+heltec_wireless_stick_lite.menu.DebugLevel.info=Info
+heltec_wireless_stick_lite.menu.DebugLevel.info.build.code_debug=3
+heltec_wireless_stick_lite.menu.DebugLevel.debug=Debug
+heltec_wireless_stick_lite.menu.DebugLevel.debug.build.code_debug=4
+heltec_wireless_stick_lite.menu.DebugLevel.verbose=Verbose
+heltec_wireless_stick_lite.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wireless_stick_lite.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.0=None
+heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.1=Freq
+heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wireless_stick_lite.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wireless_stick_lite.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wireless_stick_lite.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wireless_stick_lite.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wireless_stick_lite.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wireless_stick_lite.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wireless_stick_lite.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wireless_stick_lite.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wireless_stick_lite.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wireless_stick_lite.menu.EraseFlash.none=Disabled
+heltec_wireless_stick_lite.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wireless_stick_lite.menu.EraseFlash.all=Enabled
+heltec_wireless_stick_lite.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_wireless_bridge.name=Heltec Wireless Bridge
+
+heltec_wireless_bridge.bootloader.tool=esptool_py
+heltec_wireless_bridge.bootloader.tool.default=esptool_py
+
+heltec_wireless_bridge.upload.tool=esptool_py
+heltec_wireless_bridge.upload.tool.default=esptool_py
+heltec_wireless_bridge.upload.tool.network=esp_ota
+
+heltec_wireless_bridge.upload.maximum_size=3342336
+heltec_wireless_bridge.upload.maximum_data_size=327680
+heltec_wireless_bridge.upload.wait_for_upload_port=true
+heltec_wireless_bridge.upload.flags=
+heltec_wireless_bridge.upload.extra_flags=
+
+heltec_wireless_bridge.serial.disableDTR=true
+heltec_wireless_bridge.serial.disableRTS=true
+
+heltec_wireless_bridge.build.tarch=xtensa
+heltec_wireless_bridge.build.bootloader_addr=0x1000
+heltec_wireless_bridge.build.target=esp32
+heltec_wireless_bridge.build.mcu=esp32
+heltec_wireless_bridge.build.core=esp32
+heltec_wireless_bridge.build.variant=heltec_wireless_bridge
+heltec_wireless_bridge.build.board=HELTEC_WIRELESS_BRIDGE
+
+heltec_wireless_bridge.build.f_cpu=240000000L
+heltec_wireless_bridge.build.flash_size=8MB
+heltec_wireless_bridge.build.flash_freq=80m
+heltec_wireless_bridge.build.flash_mode=dio
+heltec_wireless_bridge.build.boot=dio
+heltec_wireless_bridge.build.partitions=default_8MB
+heltec_wireless_bridge.build.psram=
+heltec_wireless_bridge.build.psram_type=qspi
+heltec_wireless_bridge.build.memory_type={build.boot}_{build.psram_type}
+heltec_wireless_bridge.build.defines=-D{build.band} {build.psram_val} -DMCU_ESP32_D0 -DWIRELESS_BRIDGE -DHELTEC_BOARD=4 -DRADIO_CHIP_SX127X -DSLOW_CLK_TPYE=0 -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH}  -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO}  {build.psram}
+
+heltec_wireless_bridge.menu.CPUFreq.240=240MHz (WiFi/BT)
+heltec_wireless_bridge.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_wireless_bridge.menu.CPUFreq.160=160MHz (WiFi/BT)
+heltec_wireless_bridge.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_wireless_bridge.menu.CPUFreq.80=80MHz (WiFi/BT)
+heltec_wireless_bridge.menu.CPUFreq.80.build.f_cpu=80000000L
+
+heltec_wireless_bridge.menu.UploadSpeed.921600=921600
+heltec_wireless_bridge.menu.UploadSpeed.921600.upload.speed=921600
+heltec_wireless_bridge.menu.UploadSpeed.115200=115200
+heltec_wireless_bridge.menu.UploadSpeed.115200.upload.speed=115200
+heltec_wireless_bridge.menu.UploadSpeed.256000.windows=256000
+heltec_wireless_bridge.menu.UploadSpeed.256000.upload.speed=256000
+heltec_wireless_bridge.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_wireless_bridge.menu.UploadSpeed.230400=230400
+heltec_wireless_bridge.menu.UploadSpeed.230400.upload.speed=230400
+heltec_wireless_bridge.menu.UploadSpeed.460800.linux=460800
+heltec_wireless_bridge.menu.UploadSpeed.460800.macosx=460800
+heltec_wireless_bridge.menu.UploadSpeed.460800.upload.speed=460800
+heltec_wireless_bridge.menu.UploadSpeed.512000.windows=512000
+heltec_wireless_bridge.menu.UploadSpeed.512000.upload.speed=512000
+
+
+heltec_wireless_bridge.menu.PSRAM.disabled=Disabled
+heltec_wireless_bridge.menu.PSRAM.disabled.build.psram_val=
+heltec_wireless_bridge.menu.PSRAM.disabled.build.psram_type=qspi
+heltec_wireless_bridge.menu.PSRAM.enabled=QSPI PSRAM
+heltec_wireless_bridge.menu.PSRAM.enabled.build.psram_val=-DBOARD_HAS_PSRAM
+heltec_wireless_bridge.menu.PSRAM.enabled.build.psram_type=qspi
+
+heltec_wireless_bridge.menu.DebugLevel.none=None
+heltec_wireless_bridge.menu.DebugLevel.none.build.code_debug=0
+heltec_wireless_bridge.menu.DebugLevel.error=Error
+heltec_wireless_bridge.menu.DebugLevel.error.build.code_debug=1
+heltec_wireless_bridge.menu.DebugLevel.warn=Warn
+heltec_wireless_bridge.menu.DebugLevel.warn.build.code_debug=2
+heltec_wireless_bridge.menu.DebugLevel.info=Info
+heltec_wireless_bridge.menu.DebugLevel.info.build.code_debug=3
+heltec_wireless_bridge.menu.DebugLevel.debug=Debug
+heltec_wireless_bridge.menu.DebugLevel.debug.build.code_debug=4
+heltec_wireless_bridge.menu.DebugLevel.verbose=Verbose
+heltec_wireless_bridge.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_wireless_bridge.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_wireless_bridge.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_wireless_bridge.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_wireless_bridge.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_wireless_bridge.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_wireless_bridge.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_wireless_bridge.menu.LORAWAN_REGION.3=REGION_US915
+heltec_wireless_bridge.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_wireless_bridge.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_wireless_bridge.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_wireless_bridge.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_wireless_bridge.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_wireless_bridge.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_wireless_bridge.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_wireless_bridge.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_wireless_bridge.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_wireless_bridge.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_wireless_bridge.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_wireless_bridge.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_wireless_bridge.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_wireless_bridge.menu.LoRaWanDebugLevel.0=None
+heltec_wireless_bridge.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_wireless_bridge.menu.LoRaWanDebugLevel.1=Freq
+heltec_wireless_bridge.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_wireless_bridge.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_wireless_bridge.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_wireless_bridge.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_wireless_bridge.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_wireless_bridge.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_wireless_bridge.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_wireless_bridge.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_wireless_bridge.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_wireless_bridge.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_wireless_bridge.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_wireless_bridge.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_wireless_bridge.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_wireless_bridge.menu.EraseFlash.none=Disabled
+heltec_wireless_bridge.menu.EraseFlash.none.upload.erase_cmd=
+heltec_wireless_bridge.menu.EraseFlash.all=Enabled
+heltec_wireless_bridge.menu.EraseFlash.all.upload.erase_cmd=-e
+
+#############################################################
+
+heltec_ht_de01.name=Heltec E-Ink Driver
+
+heltec_ht_de01.bootloader.tool=esptool_py
+heltec_ht_de01.bootloader.tool.default=esptool_py
+
+heltec_ht_de01.upload.tool=esptool_py
+heltec_ht_de01.upload.tool.default=esptool_py
+heltec_ht_de01.upload.tool.network=esp_ota
+
+heltec_ht_de01.upload.maximum_size=4026368
+heltec_ht_de01.upload.maximum_data_size=327680
+heltec_ht_de01.upload.flags=
+heltec_ht_de01.upload.extra_flags=
+heltec_ht_de01.upload.use_1200bps_touch=false
+heltec_ht_de01.upload.wait_for_upload_port=false
+
+heltec_ht_de01.serial.disableDTR=false
+heltec_ht_de01.serial.disableRTS=false
+
+heltec_ht_de01.build.tarch=xtensa
+heltec_ht_de01.build.bootloader_addr=0x0
+heltec_ht_de01.build.target=esp32s3
+heltec_ht_de01.build.mcu=esp32s3
+heltec_ht_de01.build.core=esp32
+heltec_ht_de01.build.variant=heltec_ht_de01
+heltec_ht_de01.build.board=HT_DE01
+
+heltec_ht_de01.build.usb_mode=1
+heltec_ht_de01.build.cdc_on_boot=0
+heltec_ht_de01.build.msc_on_boot=0
+heltec_ht_de01.build.dfu_on_boot=0
+heltec_ht_de01.build.f_cpu=240000000L
+heltec_ht_de01.build.flash_size=8MB
+heltec_ht_de01.build.flash_freq=80m
+heltec_ht_de01.build.flash_mode=dio
+heltec_ht_de01.build.boot=qio
+heltec_ht_de01.build.boot_freq=80m
+heltec_ht_de01.build.partitions=default_8MB
+heltec_ht_de01.build.loop_core=
+heltec_ht_de01.build.event_core=
+heltec_ht_de01.build.psram_type=qspi
+heltec_ht_de01.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_ht_de01.menu.LoopCore.1=Core 1
+heltec_ht_de01.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_ht_de01.menu.LoopCore.0=Core 0
+heltec_ht_de01.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_ht_de01.menu.EventsCore.1=Core 1
+heltec_ht_de01.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_ht_de01.menu.EventsCore.0=Core 0
+heltec_ht_de01.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_ht_de01.menu.CPUFreq.240=240MHz (WiFi)
+heltec_ht_de01.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_ht_de01.menu.CPUFreq.160=160MHz (WiFi)
+heltec_ht_de01.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_ht_de01.menu.CPUFreq.80=80MHz (WiFi)
+heltec_ht_de01.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_ht_de01.menu.CPUFreq.40=40MHz
+heltec_ht_de01.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_ht_de01.menu.CPUFreq.20=20MHz
+heltec_ht_de01.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_ht_de01.menu.CPUFreq.10=10MHz
+heltec_ht_de01.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_ht_de01.menu.UploadSpeed.921600=921600
+heltec_ht_de01.menu.UploadSpeed.921600.upload.speed=921600
+heltec_ht_de01.menu.UploadSpeed.115200=115200
+heltec_ht_de01.menu.UploadSpeed.115200.upload.speed=115200
+heltec_ht_de01.menu.UploadSpeed.256000.windows=256000
+heltec_ht_de01.menu.UploadSpeed.256000.upload.speed=256000
+heltec_ht_de01.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_ht_de01.menu.UploadSpeed.230400=230400
+heltec_ht_de01.menu.UploadSpeed.230400.upload.speed=230400
+heltec_ht_de01.menu.UploadSpeed.460800.linux=460800
+heltec_ht_de01.menu.UploadSpeed.460800.macosx=460800
+heltec_ht_de01.menu.UploadSpeed.460800.upload.speed=460800
+heltec_ht_de01.menu.UploadSpeed.512000.windows=512000
+heltec_ht_de01.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_ht_de01.menu.DebugLevel.none=None
+heltec_ht_de01.menu.DebugLevel.none.build.code_debug=0
+heltec_ht_de01.menu.DebugLevel.error=Error
+heltec_ht_de01.menu.DebugLevel.error.build.code_debug=1
+heltec_ht_de01.menu.DebugLevel.warn=Warn
+heltec_ht_de01.menu.DebugLevel.warn.build.code_debug=2
+heltec_ht_de01.menu.DebugLevel.info=Info
+heltec_ht_de01.menu.DebugLevel.info.build.code_debug=3
+heltec_ht_de01.menu.DebugLevel.debug=Debug
+heltec_ht_de01.menu.DebugLevel.debug.build.code_debug=4
+heltec_ht_de01.menu.DebugLevel.verbose=Verbose
+heltec_ht_de01.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_ht_de01.menu.einksize.0=eink_150
+heltec_ht_de01.menu.einksize.0.build.einksize=150;
+heltec_ht_de01.menu.einksize.1=eink_154
+heltec_ht_de01.menu.einksize.1.build.einksize=154;
+heltec_ht_de01.menu.einksize.2=eink_213
+heltec_ht_de01.menu.einksize.2.build.einksize=213;
+heltec_ht_de01.menu.einksize.3=eink_290
+heltec_ht_de01.menu.einksize.3.build.einksize=290;
+
+heltec_ht_de01.build.defines=   -DEINK={build.einksize}   -D{build.board}
+
+heltec_ht_de01.menu.EraseFlash.none=Disabled
+heltec_ht_de01.menu.EraseFlash.none.upload.erase_cmd=
+heltec_ht_de01.menu.EraseFlash.all=Enabled
+heltec_ht_de01.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_vision_master_e290.name=Heltec Vision Master E290
+
+heltec_vision_master_e290.bootloader.tool=esptool_py
+heltec_vision_master_e290.bootloader.tool.default=esptool_py
+
+heltec_vision_master_e290.upload.tool=esptool_py
+heltec_vision_master_e290.upload.tool.default=esptool_py
+heltec_vision_master_e290.upload.tool.network=esp_ota
+
+heltec_vision_master_e290.upload.maximum_size=3342336
+heltec_vision_master_e290.upload.maximum_data_size=327680
+heltec_vision_master_e290.upload.flags=
+heltec_vision_master_e290.upload.extra_flags=
+heltec_vision_master_e290.upload.use_1200bps_touch=false
+heltec_vision_master_e290.upload.wait_for_upload_port=false
+
+heltec_vision_master_e290.serial.disableDTR=false
+heltec_vision_master_e290.serial.disableRTS=false
+
+heltec_vision_master_e290.build.tarch=xtensa
+heltec_vision_master_e290.build.bootloader_addr=0x0
+heltec_vision_master_e290.build.target=esp32s3
+heltec_vision_master_e290.build.mcu=esp32s3
+heltec_vision_master_e290.build.core=esp32
+heltec_vision_master_e290.build.variant=heltec_vision_master_e290
+heltec_vision_master_e290.build.board=HELTEC_VISION_MASTER_E290
+
+heltec_vision_master_e290.build.usb_mode=1
+heltec_vision_master_e290.build.cdc_on_boot=0
+heltec_vision_master_e290.build.msc_on_boot=0
+heltec_vision_master_e290.build.dfu_on_boot=0
+heltec_vision_master_e290.build.f_cpu=240000000L
+heltec_vision_master_e290.build.flash_size=8MB
+heltec_vision_master_e290.build.flash_freq=80m
+heltec_vision_master_e290.build.flash_mode=dio
+heltec_vision_master_e290.build.boot=qio
+heltec_vision_master_e290.build.boot_freq=80m
+heltec_vision_master_e290.build.partitions=default_8MB
+heltec_vision_master_e290.build.loop_core=
+heltec_vision_master_e290.build.event_core=
+heltec_vision_master_e290.build.psram_type=qspi
+heltec_vision_master_e290.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_vision_master_e290.menu.LoopCore.1=Core 1
+heltec_vision_master_e290.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_vision_master_e290.menu.LoopCore.0=Core 0
+heltec_vision_master_e290.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_vision_master_e290.menu.EventsCore.1=Core 1
+heltec_vision_master_e290.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_vision_master_e290.menu.EventsCore.0=Core 0
+heltec_vision_master_e290.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_vision_master_e290.menu.USBMode.hwcdc=Hardware CDC and JTAG
+heltec_vision_master_e290.menu.USBMode.hwcdc.build.usb_mode=1
+heltec_vision_master_e290.menu.USBMode.default=USB-OTG (TinyUSB)
+heltec_vision_master_e290.menu.USBMode.default.build.usb_mode=0
+
+heltec_vision_master_e290.menu.CDCOnBoot.default=Enabled
+heltec_vision_master_e290.menu.CDCOnBoot.default.build.cdc_on_boot=1
+heltec_vision_master_e290.menu.CDCOnBoot.cdc=Disabled
+heltec_vision_master_e290.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+heltec_vision_master_e290.menu.MSCOnBoot.default=Disabled
+heltec_vision_master_e290.menu.MSCOnBoot.default.build.msc_on_boot=0
+heltec_vision_master_e290.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+heltec_vision_master_e290.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+heltec_vision_master_e290.menu.DFUOnBoot.default=Disabled
+heltec_vision_master_e290.menu.DFUOnBoot.default.build.dfu_on_boot=0
+heltec_vision_master_e290.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+heltec_vision_master_e290.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+heltec_vision_master_e290.menu.UploadMode.default=UART0 / Hardware CDC
+heltec_vision_master_e290.menu.UploadMode.default.upload.use_1200bps_touch=false
+heltec_vision_master_e290.menu.UploadMode.default.upload.wait_for_upload_port=false
+heltec_vision_master_e290.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+heltec_vision_master_e290.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+heltec_vision_master_e290.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+heltec_vision_master_e290.menu.CPUFreq.240=240MHz (WiFi)
+heltec_vision_master_e290.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_vision_master_e290.menu.CPUFreq.160=160MHz (WiFi)
+heltec_vision_master_e290.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_vision_master_e290.menu.CPUFreq.80=80MHz (WiFi)
+heltec_vision_master_e290.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_vision_master_e290.menu.CPUFreq.40=40MHz
+heltec_vision_master_e290.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_vision_master_e290.menu.CPUFreq.20=20MHz
+heltec_vision_master_e290.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_vision_master_e290.menu.CPUFreq.10=10MHz
+heltec_vision_master_e290.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_vision_master_e290.menu.UploadSpeed.921600=921600
+heltec_vision_master_e290.menu.UploadSpeed.921600.upload.speed=921600
+heltec_vision_master_e290.menu.UploadSpeed.115200=115200
+heltec_vision_master_e290.menu.UploadSpeed.115200.upload.speed=115200
+heltec_vision_master_e290.menu.UploadSpeed.256000.windows=256000
+heltec_vision_master_e290.menu.UploadSpeed.256000.upload.speed=256000
+heltec_vision_master_e290.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_vision_master_e290.menu.UploadSpeed.230400=230400
+heltec_vision_master_e290.menu.UploadSpeed.230400.upload.speed=230400
+heltec_vision_master_e290.menu.UploadSpeed.460800.linux=460800
+heltec_vision_master_e290.menu.UploadSpeed.460800.macosx=460800
+heltec_vision_master_e290.menu.UploadSpeed.460800.upload.speed=460800
+heltec_vision_master_e290.menu.UploadSpeed.512000.windows=512000
+heltec_vision_master_e290.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_vision_master_e290.menu.DebugLevel.none=None
+heltec_vision_master_e290.menu.DebugLevel.none.build.code_debug=0
+heltec_vision_master_e290.menu.DebugLevel.error=Error
+heltec_vision_master_e290.menu.DebugLevel.error.build.code_debug=1
+heltec_vision_master_e290.menu.DebugLevel.warn=Warn
+heltec_vision_master_e290.menu.DebugLevel.warn.build.code_debug=2
+heltec_vision_master_e290.menu.DebugLevel.info=Info
+heltec_vision_master_e290.menu.DebugLevel.info.build.code_debug=3
+heltec_vision_master_e290.menu.DebugLevel.debug=Debug
+heltec_vision_master_e290.menu.DebugLevel.debug.build.code_debug=4
+heltec_vision_master_e290.menu.DebugLevel.verbose=Verbose
+heltec_vision_master_e290.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_vision_master_e290.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_vision_master_e290.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_vision_master_e290.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_vision_master_e290.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_vision_master_e290.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_vision_master_e290.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_vision_master_e290.menu.LORAWAN_REGION.3=REGION_US915
+heltec_vision_master_e290.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_vision_master_e290.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_vision_master_e290.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_vision_master_e290.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_vision_master_e290.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_vision_master_e290.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_vision_master_e290.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_vision_master_e290.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_vision_master_e290.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_vision_master_e290.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_vision_master_e290.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_vision_master_e290.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_vision_master_e290.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_vision_master_e290.menu.LoRaWanDebugLevel.0=None
+heltec_vision_master_e290.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_vision_master_e290.menu.LoRaWanDebugLevel.1=Freq
+heltec_vision_master_e290.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_vision_master_e290.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_vision_master_e290.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_vision_master_e290.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_vision_master_e290.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_vision_master_e290.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_vision_master_e290.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_vision_master_e290.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_vision_master_e290.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_vision_master_e290.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_vision_master_e290.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_vision_master_e290.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_vision_master_e290.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_vision_master_e290.menu.SLOW_CLK_TPYE.0=Internal (default)
+heltec_vision_master_e290.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0
+heltec_vision_master_e290.menu.SLOW_CLK_TPYE.1=External 32K
+heltec_vision_master_e290.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1
+
+heltec_vision_master_e290.build.defines=-D{build.band}  -DMCU_ESP32_S3 -DHELTEC_BOARD=37 -DHELTEC_VISION_MASTER_E290 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_vision_master_e290.menu.EraseFlash.none=Disabled
+heltec_vision_master_e290.menu.EraseFlash.none.upload.erase_cmd=
+heltec_vision_master_e290.menu.EraseFlash.all=Enabled
+heltec_vision_master_e290.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_vision_master_t190.name=Heltec Vision Master T190
+
+heltec_vision_master_t190.bootloader.tool=esptool_py
+heltec_vision_master_t190.bootloader.tool.default=esptool_py
+
+heltec_vision_master_t190.upload.tool=esptool_py
+heltec_vision_master_t190.upload.tool.default=esptool_py
+heltec_vision_master_t190.upload.tool.network=esp_ota
+
+heltec_vision_master_t190.upload.maximum_size=3342336
+heltec_vision_master_t190.upload.maximum_data_size=327680
+heltec_vision_master_t190.upload.flags=
+heltec_vision_master_t190.upload.extra_flags=
+heltec_vision_master_t190.upload.use_1200bps_touch=false
+heltec_vision_master_t190.upload.wait_for_upload_port=false
+
+heltec_vision_master_t190.serial.disableDTR=false
+heltec_vision_master_t190.serial.disableRTS=false
+
+heltec_vision_master_t190.build.tarch=xtensa
+heltec_vision_master_t190.build.bootloader_addr=0x0
+heltec_vision_master_t190.build.target=esp32s3
+heltec_vision_master_t190.build.mcu=esp32s3
+heltec_vision_master_t190.build.core=esp32
+heltec_vision_master_t190.build.variant=heltec_vision_master_t190
+heltec_vision_master_t190.build.board=HELTEC_VISION_MASTER_T190
+
+heltec_vision_master_t190.build.usb_mode=1
+heltec_vision_master_t190.build.cdc_on_boot=0
+heltec_vision_master_t190.build.msc_on_boot=0
+heltec_vision_master_t190.build.dfu_on_boot=0
+heltec_vision_master_t190.build.f_cpu=240000000L
+heltec_vision_master_t190.build.flash_size=8MB
+heltec_vision_master_t190.build.flash_freq=80m
+heltec_vision_master_t190.build.flash_mode=dio
+heltec_vision_master_t190.build.boot=qio
+heltec_vision_master_t190.build.boot_freq=80m
+heltec_vision_master_t190.build.partitions=default_8MB
+heltec_vision_master_t190.build.loop_core=
+heltec_vision_master_t190.build.event_core=
+heltec_vision_master_t190.build.psram_type=qspi
+heltec_vision_master_t190.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_vision_master_t190.menu.LoopCore.1=Core 1
+heltec_vision_master_t190.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_vision_master_t190.menu.LoopCore.0=Core 0
+heltec_vision_master_t190.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_vision_master_t190.menu.EventsCore.1=Core 1
+heltec_vision_master_t190.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_vision_master_t190.menu.EventsCore.0=Core 0
+heltec_vision_master_t190.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_vision_master_t190.menu.USBMode.hwcdc=Hardware CDC and JTAG
+heltec_vision_master_t190.menu.USBMode.hwcdc.build.usb_mode=1
+heltec_vision_master_t190.menu.USBMode.default=USB-OTG (TinyUSB)
+heltec_vision_master_t190.menu.USBMode.default.build.usb_mode=0
+
+heltec_vision_master_t190.menu.CDCOnBoot.default=Enabled
+heltec_vision_master_t190.menu.CDCOnBoot.default.build.cdc_on_boot=1
+heltec_vision_master_t190.menu.CDCOnBoot.cdc=Disabled
+heltec_vision_master_t190.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+heltec_vision_master_t190.menu.MSCOnBoot.default=Disabled
+heltec_vision_master_t190.menu.MSCOnBoot.default.build.msc_on_boot=0
+heltec_vision_master_t190.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+heltec_vision_master_t190.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+heltec_vision_master_t190.menu.DFUOnBoot.default=Disabled
+heltec_vision_master_t190.menu.DFUOnBoot.default.build.dfu_on_boot=0
+heltec_vision_master_t190.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+heltec_vision_master_t190.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+heltec_vision_master_t190.menu.UploadMode.default=UART0 / Hardware CDC
+heltec_vision_master_t190.menu.UploadMode.default.upload.use_1200bps_touch=false
+heltec_vision_master_t190.menu.UploadMode.default.upload.wait_for_upload_port=false
+heltec_vision_master_t190.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+heltec_vision_master_t190.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+heltec_vision_master_t190.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+heltec_vision_master_t190.menu.CPUFreq.240=240MHz (WiFi)
+heltec_vision_master_t190.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_vision_master_t190.menu.CPUFreq.160=160MHz (WiFi)
+heltec_vision_master_t190.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_vision_master_t190.menu.CPUFreq.80=80MHz (WiFi)
+heltec_vision_master_t190.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_vision_master_t190.menu.CPUFreq.40=40MHz
+heltec_vision_master_t190.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_vision_master_t190.menu.CPUFreq.20=20MHz
+heltec_vision_master_t190.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_vision_master_t190.menu.CPUFreq.10=10MHz
+heltec_vision_master_t190.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_vision_master_t190.menu.UploadSpeed.921600=921600
+heltec_vision_master_t190.menu.UploadSpeed.921600.upload.speed=921600
+heltec_vision_master_t190.menu.UploadSpeed.115200=115200
+heltec_vision_master_t190.menu.UploadSpeed.115200.upload.speed=115200
+heltec_vision_master_t190.menu.UploadSpeed.256000.windows=256000
+heltec_vision_master_t190.menu.UploadSpeed.256000.upload.speed=256000
+heltec_vision_master_t190.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_vision_master_t190.menu.UploadSpeed.230400=230400
+heltec_vision_master_t190.menu.UploadSpeed.230400.upload.speed=230400
+heltec_vision_master_t190.menu.UploadSpeed.460800.linux=460800
+heltec_vision_master_t190.menu.UploadSpeed.460800.macosx=460800
+heltec_vision_master_t190.menu.UploadSpeed.460800.upload.speed=460800
+heltec_vision_master_t190.menu.UploadSpeed.512000.windows=512000
+heltec_vision_master_t190.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_vision_master_t190.menu.DebugLevel.none=None
+heltec_vision_master_t190.menu.DebugLevel.none.build.code_debug=0
+heltec_vision_master_t190.menu.DebugLevel.error=Error
+heltec_vision_master_t190.menu.DebugLevel.error.build.code_debug=1
+heltec_vision_master_t190.menu.DebugLevel.warn=Warn
+heltec_vision_master_t190.menu.DebugLevel.warn.build.code_debug=2
+heltec_vision_master_t190.menu.DebugLevel.info=Info
+heltec_vision_master_t190.menu.DebugLevel.info.build.code_debug=3
+heltec_vision_master_t190.menu.DebugLevel.debug=Debug
+heltec_vision_master_t190.menu.DebugLevel.debug.build.code_debug=4
+heltec_vision_master_t190.menu.DebugLevel.verbose=Verbose
+heltec_vision_master_t190.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_vision_master_t190.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_vision_master_t190.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_vision_master_t190.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_vision_master_t190.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_vision_master_t190.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_vision_master_t190.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_vision_master_t190.menu.LORAWAN_REGION.3=REGION_US915
+heltec_vision_master_t190.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_vision_master_t190.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_vision_master_t190.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_vision_master_t190.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_vision_master_t190.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_vision_master_t190.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_vision_master_t190.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_vision_master_t190.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_vision_master_t190.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_vision_master_t190.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_vision_master_t190.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_vision_master_t190.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_vision_master_t190.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_vision_master_t190.menu.LoRaWanDebugLevel.0=None
+heltec_vision_master_t190.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_vision_master_t190.menu.LoRaWanDebugLevel.1=Freq
+heltec_vision_master_t190.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_vision_master_t190.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_vision_master_t190.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_vision_master_t190.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_vision_master_t190.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_vision_master_t190.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_vision_master_t190.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_vision_master_t190.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_vision_master_t190.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_vision_master_t190.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_vision_master_t190.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_vision_master_t190.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_vision_master_t190.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_vision_master_t190.menu.SLOW_CLK_TPYE.0=Internal (default)
+heltec_vision_master_t190.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0
+heltec_vision_master_t190.menu.SLOW_CLK_TPYE.1=External 32K
+heltec_vision_master_t190.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1
+
+heltec_vision_master_t190.build.defines=-D{build.band}  -DMCU_ESP32_S3 -DHELTEC_BOARD=38 -DHELTEC_VISION_MASTER_T190 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_vision_master_t190.menu.EraseFlash.none=Disabled
+heltec_vision_master_t190.menu.EraseFlash.none.upload.erase_cmd=
+heltec_vision_master_t190.menu.EraseFlash.all=Enabled
+heltec_vision_master_t190.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+heltec_vision_master_e_213.name=Heltec Vision Master E213
+
+heltec_vision_master_e_213.bootloader.tool=esptool_py
+heltec_vision_master_e_213.bootloader.tool.default=esptool_py
+
+heltec_vision_master_e_213.upload.tool=esptool_py
+heltec_vision_master_e_213.upload.tool.default=esptool_py
+heltec_vision_master_e_213.upload.tool.network=esp_ota
+
+heltec_vision_master_e_213.upload.maximum_size=3342336
+heltec_vision_master_e_213.upload.maximum_data_size=327680
+heltec_vision_master_e_213.upload.flags=
+heltec_vision_master_e_213.upload.extra_flags=
+heltec_vision_master_e_213.upload.use_1200bps_touch=false
+heltec_vision_master_e_213.upload.wait_for_upload_port=false
+
+heltec_vision_master_e_213.serial.disableDTR=false
+heltec_vision_master_e_213.serial.disableRTS=false
+
+heltec_vision_master_e_213.build.tarch=xtensa
+heltec_vision_master_e_213.build.bootloader_addr=0x0
+heltec_vision_master_e_213.build.target=esp32s3
+heltec_vision_master_e_213.build.mcu=esp32s3
+heltec_vision_master_e_213.build.core=esp32
+heltec_vision_master_e_213.build.variant=heltec_vision_master_e_213
+heltec_vision_master_e_213.build.board=HELTEC_VISION_MASTER_E_213
+
+heltec_vision_master_e_213.build.usb_mode=1
+heltec_vision_master_e_213.build.cdc_on_boot=0
+heltec_vision_master_e_213.build.msc_on_boot=0
+heltec_vision_master_e_213.build.dfu_on_boot=0
+heltec_vision_master_e_213.build.f_cpu=240000000L
+heltec_vision_master_e_213.build.flash_size=8MB
+heltec_vision_master_e_213.build.flash_freq=80m
+heltec_vision_master_e_213.build.flash_mode=dio
+heltec_vision_master_e_213.build.boot=qio
+heltec_vision_master_e_213.build.boot_freq=80m
+heltec_vision_master_e_213.build.partitions=default_8MB
+heltec_vision_master_e_213.build.loop_core=
+heltec_vision_master_e_213.build.event_core=
+heltec_vision_master_e_213.build.psram_type=qspi
+heltec_vision_master_e_213.build.memory_type={build.boot}_{build.psram_type}
+
+heltec_vision_master_e_213.menu.LoopCore.1=Core 1
+heltec_vision_master_e_213.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+heltec_vision_master_e_213.menu.LoopCore.0=Core 0
+heltec_vision_master_e_213.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+heltec_vision_master_e_213.menu.EventsCore.1=Core 1
+heltec_vision_master_e_213.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+heltec_vision_master_e_213.menu.EventsCore.0=Core 0
+heltec_vision_master_e_213.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+heltec_vision_master_e_213.menu.USBMode.hwcdc=Hardware CDC and JTAG
+heltec_vision_master_e_213.menu.USBMode.hwcdc.build.usb_mode=1
+heltec_vision_master_e_213.menu.USBMode.default=USB-OTG (TinyUSB)
+heltec_vision_master_e_213.menu.USBMode.default.build.usb_mode=0
+
+heltec_vision_master_e_213.menu.CDCOnBoot.default=Enabled
+heltec_vision_master_e_213.menu.CDCOnBoot.default.build.cdc_on_boot=1
+heltec_vision_master_e_213.menu.CDCOnBoot.cdc=Disabled
+heltec_vision_master_e_213.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+heltec_vision_master_e_213.menu.MSCOnBoot.default=Disabled
+heltec_vision_master_e_213.menu.MSCOnBoot.default.build.msc_on_boot=0
+heltec_vision_master_e_213.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+heltec_vision_master_e_213.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+heltec_vision_master_e_213.menu.DFUOnBoot.default=Disabled
+heltec_vision_master_e_213.menu.DFUOnBoot.default.build.dfu_on_boot=0
+heltec_vision_master_e_213.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+heltec_vision_master_e_213.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+heltec_vision_master_e_213.menu.UploadMode.default=UART0 / Hardware CDC
+heltec_vision_master_e_213.menu.UploadMode.default.upload.use_1200bps_touch=false
+heltec_vision_master_e_213.menu.UploadMode.default.upload.wait_for_upload_port=false
+heltec_vision_master_e_213.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+heltec_vision_master_e_213.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+heltec_vision_master_e_213.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+heltec_vision_master_e_213.menu.CPUFreq.240=240MHz (WiFi)
+heltec_vision_master_e_213.menu.CPUFreq.240.build.f_cpu=240000000L
+heltec_vision_master_e_213.menu.CPUFreq.160=160MHz (WiFi)
+heltec_vision_master_e_213.menu.CPUFreq.160.build.f_cpu=160000000L
+heltec_vision_master_e_213.menu.CPUFreq.80=80MHz (WiFi)
+heltec_vision_master_e_213.menu.CPUFreq.80.build.f_cpu=80000000L
+heltec_vision_master_e_213.menu.CPUFreq.40=40MHz
+heltec_vision_master_e_213.menu.CPUFreq.40.build.f_cpu=40000000L
+heltec_vision_master_e_213.menu.CPUFreq.20=20MHz
+heltec_vision_master_e_213.menu.CPUFreq.20.build.f_cpu=20000000L
+heltec_vision_master_e_213.menu.CPUFreq.10=10MHz
+heltec_vision_master_e_213.menu.CPUFreq.10.build.f_cpu=10000000L
+
+heltec_vision_master_e_213.menu.UploadSpeed.921600=921600
+heltec_vision_master_e_213.menu.UploadSpeed.921600.upload.speed=921600
+heltec_vision_master_e_213.menu.UploadSpeed.115200=115200
+heltec_vision_master_e_213.menu.UploadSpeed.115200.upload.speed=115200
+heltec_vision_master_e_213.menu.UploadSpeed.256000.windows=256000
+heltec_vision_master_e_213.menu.UploadSpeed.256000.upload.speed=256000
+heltec_vision_master_e_213.menu.UploadSpeed.230400.windows.upload.speed=256000
+heltec_vision_master_e_213.menu.UploadSpeed.230400=230400
+heltec_vision_master_e_213.menu.UploadSpeed.230400.upload.speed=230400
+heltec_vision_master_e_213.menu.UploadSpeed.460800.linux=460800
+heltec_vision_master_e_213.menu.UploadSpeed.460800.macosx=460800
+heltec_vision_master_e_213.menu.UploadSpeed.460800.upload.speed=460800
+heltec_vision_master_e_213.menu.UploadSpeed.512000.windows=512000
+heltec_vision_master_e_213.menu.UploadSpeed.512000.upload.speed=512000
+
+heltec_vision_master_e_213.menu.DebugLevel.none=None
+heltec_vision_master_e_213.menu.DebugLevel.none.build.code_debug=0
+heltec_vision_master_e_213.menu.DebugLevel.error=Error
+heltec_vision_master_e_213.menu.DebugLevel.error.build.code_debug=1
+heltec_vision_master_e_213.menu.DebugLevel.warn=Warn
+heltec_vision_master_e_213.menu.DebugLevel.warn.build.code_debug=2
+heltec_vision_master_e_213.menu.DebugLevel.info=Info
+heltec_vision_master_e_213.menu.DebugLevel.info.build.code_debug=3
+heltec_vision_master_e_213.menu.DebugLevel.debug=Debug
+heltec_vision_master_e_213.menu.DebugLevel.debug.build.code_debug=4
+heltec_vision_master_e_213.menu.DebugLevel.verbose=Verbose
+heltec_vision_master_e_213.menu.DebugLevel.verbose.build.code_debug=5
+
+heltec_vision_master_e_213.menu.LORAWAN_REGION.0=REGION_EU868
+heltec_vision_master_e_213.menu.LORAWAN_REGION.0.build.band=REGION_EU868
+heltec_vision_master_e_213.menu.LORAWAN_REGION.1=REGION_EU433
+heltec_vision_master_e_213.menu.LORAWAN_REGION.1.build.band=REGION_EU433
+heltec_vision_master_e_213.menu.LORAWAN_REGION.2=REGION_CN470
+heltec_vision_master_e_213.menu.LORAWAN_REGION.2.build.band=REGION_CN470
+heltec_vision_master_e_213.menu.LORAWAN_REGION.3=REGION_US915
+heltec_vision_master_e_213.menu.LORAWAN_REGION.3.build.band=REGION_US915
+heltec_vision_master_e_213.menu.LORAWAN_REGION.4=REGION_AU915
+heltec_vision_master_e_213.menu.LORAWAN_REGION.4.build.band=REGION_AU915
+heltec_vision_master_e_213.menu.LORAWAN_REGION.5=REGION_CN779
+heltec_vision_master_e_213.menu.LORAWAN_REGION.5.build.band=REGION_CN779
+heltec_vision_master_e_213.menu.LORAWAN_REGION.6=REGION_AS923
+heltec_vision_master_e_213.menu.LORAWAN_REGION.6.build.band=REGION_AS923
+heltec_vision_master_e_213.menu.LORAWAN_REGION.7=REGION_KR920
+heltec_vision_master_e_213.menu.LORAWAN_REGION.7.build.band=REGION_KR920
+heltec_vision_master_e_213.menu.LORAWAN_REGION.8=REGION_IN865
+heltec_vision_master_e_213.menu.LORAWAN_REGION.8.build.band=REGION_IN865
+heltec_vision_master_e_213.menu.LORAWAN_REGION.9=REGION_US915_HYBRID
+heltec_vision_master_e_213.menu.LORAWAN_REGION.9.build.band=REGION_US915_HYBRID
+
+heltec_vision_master_e_213.menu.LoRaWanDebugLevel.0=None
+heltec_vision_master_e_213.menu.LoRaWanDebugLevel.0.build.LoRaWanDebugLevel=0
+heltec_vision_master_e_213.menu.LoRaWanDebugLevel.1=Freq
+heltec_vision_master_e_213.menu.LoRaWanDebugLevel.1.build.LoRaWanDebugLevel=1
+heltec_vision_master_e_213.menu.LoRaWanDebugLevel.2=Freq && DIO
+heltec_vision_master_e_213.menu.LoRaWanDebugLevel.2.build.LoRaWanDebugLevel=2
+heltec_vision_master_e_213.menu.LoRaWanDebugLevel.3=Freq && DIO && PW
+heltec_vision_master_e_213.menu.LoRaWanDebugLevel.3.build.LoRaWanDebugLevel=3
+
+heltec_vision_master_e_213.menu.LORAWAN_DEVEUI.0=CUSTOM
+heltec_vision_master_e_213.menu.LORAWAN_DEVEUI.0.build.LORAWAN_DEVEUI_AUTO=0
+heltec_vision_master_e_213.menu.LORAWAN_DEVEUI.1=Generate By ChipID
+heltec_vision_master_e_213.menu.LORAWAN_DEVEUI.1.build.LORAWAN_DEVEUI_AUTO=1
+
+heltec_vision_master_e_213.menu.LORAWAN_PREAMBLE_LENGTH.0=8(default)
+heltec_vision_master_e_213.menu.LORAWAN_PREAMBLE_LENGTH.0.build.LORAWAN_PREAMBLE_LENGTH=8
+heltec_vision_master_e_213.menu.LORAWAN_PREAMBLE_LENGTH.1=16(For M00 and M00L)
+heltec_vision_master_e_213.menu.LORAWAN_PREAMBLE_LENGTH.1.build.LORAWAN_PREAMBLE_LENGTH=16
+
+heltec_vision_master_e_213.menu.SLOW_CLK_TPYE.0=Internal (default)
+heltec_vision_master_e_213.menu.SLOW_CLK_TPYE.0.build.SLOW_CLK_TPYE=0
+heltec_vision_master_e_213.menu.SLOW_CLK_TPYE.1=External 32K
+heltec_vision_master_e_213.menu.SLOW_CLK_TPYE.1.build.SLOW_CLK_TPYE=1
+
+heltec_vision_master_e_213.build.defines=-D{build.band}  -DMCU_ESP32_S3 -DHELTEC_BOARD=36 -DHELTEC_VISION_MASTER_E_213 -DSLOW_CLK_TPYE={build.SLOW_CLK_TPYE} -DRADIO_CHIP_SX1262  -DLoRaWAN_DEBUG_LEVEL={build.LoRaWanDebugLevel} -DACTIVE_REGION=LORAMAC_{build.band} -DLORAWAN_PREAMBLE_LENGTH={build.LORAWAN_PREAMBLE_LENGTH} -DLORAWAN_DEVEUI_AUTO={build.LORAWAN_DEVEUI_AUTO} -D{build.board}
+
+heltec_vision_master_e_213.menu.EraseFlash.none=Disabled
+heltec_vision_master_e_213.menu.EraseFlash.none.upload.erase_cmd=
+heltec_vision_master_e_213.menu.EraseFlash.all=Enabled
+heltec_vision_master_e_213.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 espectro32.name=ESPectro32
 
+espectro32.bootloader.tool=esptool_py
+espectro32.bootloader.tool.default=esptool_py
+
 espectro32.upload.tool=esptool_py
+espectro32.upload.tool.default=esptool_py
+espectro32.upload.tool.network=esp_ota
+
 espectro32.upload.maximum_size=1310720
 espectro32.upload.maximum_data_size=327680
-espectro32.upload.wait_for_upload_port=true
+espectro32.upload.flags=
+espectro32.upload.extra_flags=
 
 espectro32.serial.disableDTR=true
 espectro32.serial.disableRTS=true
 
+espectro32.build.tarch=xtensa
+espectro32.build.bootloader_addr=0x1000
+espectro32.build.target=esp32
 espectro32.build.mcu=esp32
 espectro32.build.core=esp32
 espectro32.build.variant=espectro32
@@ -3548,12 +27549,6 @@ espectro32.menu.FlashMode.qio.build.boot=qio
 espectro32.menu.FlashMode.dio=DIO
 espectro32.menu.FlashMode.dio.build.flash_mode=dio
 espectro32.menu.FlashMode.dio.build.boot=dio
-espectro32.menu.FlashMode.qout=QOUT
-espectro32.menu.FlashMode.qout.build.flash_mode=dout
-espectro32.menu.FlashMode.qout.build.boot=qout
-espectro32.menu.FlashMode.dout=DOUT
-espectro32.menu.FlashMode.dout.build.flash_mode=dout
-espectro32.menu.FlashMode.dout.build.boot=dout
 
 espectro32.menu.FlashFreq.80=80MHz
 espectro32.menu.FlashFreq.80.build.flash_freq=80m
@@ -3564,7 +27559,6 @@ espectro32.menu.FlashSize.4M=4MB (32Mb)
 espectro32.menu.FlashSize.4M.build.flash_size=4MB
 espectro32.menu.FlashSize.2M=2MB (16Mb)
 espectro32.menu.FlashSize.2M.build.flash_size=2MB
-espectro32.menu.FlashSize.2M.build.partitions=minimal
 
 espectro32.menu.UploadSpeed.921600=921600
 espectro32.menu.UploadSpeed.921600.upload.speed=921600
@@ -3594,18 +27588,33 @@ espectro32.menu.DebugLevel.debug.build.code_debug=4
 espectro32.menu.DebugLevel.verbose=Verbose
 espectro32.menu.DebugLevel.verbose.build.code_debug=5
 
+espectro32.menu.EraseFlash.none=Disabled
+espectro32.menu.EraseFlash.none.upload.erase_cmd=
+espectro32.menu.EraseFlash.all=Enabled
+espectro32.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
+
 CoreESP32.name=Microduino-CoreESP32
 
+CoreESP32.bootloader.tool=esptool_py
+CoreESP32.bootloader.tool.default=esptool_py
+
 CoreESP32.upload.tool=esptool_py
+CoreESP32.upload.tool.default=esptool_py
+CoreESP32.upload.tool.network=esp_ota
+
 CoreESP32.upload.maximum_size=1310720
 CoreESP32.upload.maximum_data_size=327680
-CoreESP32.upload.wait_for_upload_port=true
+CoreESP32.upload.flags=
+CoreESP32.upload.extra_flags=
 
 CoreESP32.serial.disableDTR=false
 CoreESP32.serial.disableRTS=false
 
+CoreESP32.build.tarch=xtensa
+CoreESP32.build.bootloader_addr=0x1000
+CoreESP32.build.target=esp32
 CoreESP32.build.mcu=esp32
 CoreESP32.build.core=esp32
 CoreESP32.build.variant=Microduino-esp32
@@ -3620,8 +27629,10 @@ CoreESP32.build.defines=
 
 CoreESP32.menu.PSRAM.disabled=Disabled
 CoreESP32.menu.PSRAM.disabled.build.defines=
+CoreESP32.menu.PSRAM.disabled.build.extra_libs=
 CoreESP32.menu.PSRAM.enabled=Enabled
-CoreESP32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+CoreESP32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+CoreESP32.menu.PSRAM.enabled.build.extra_libs=
 
 CoreESP32.menu.PartitionScheme.default=Default
 CoreESP32.menu.PartitionScheme.default.build.partitions=default
@@ -3669,19 +27680,33 @@ CoreESP32.menu.DebugLevel.debug.build.code_debug=4
 CoreESP32.menu.DebugLevel.verbose=Verbose
 CoreESP32.menu.DebugLevel.verbose.build.code_debug=5
 
-##############################################################
+CoreESP32.menu.EraseFlash.none=Disabled
+CoreESP32.menu.EraseFlash.none.upload.erase_cmd=
+CoreESP32.menu.EraseFlash.all=Enabled
+CoreESP32.menu.EraseFlash.all.upload.erase_cmd=-e
 
+##############################################################
 
 alksesp32.name=ALKS ESP32
 
+alksesp32.bootloader.tool=esptool_py
+alksesp32.bootloader.tool.default=esptool_py
+
 alksesp32.upload.tool=esptool_py
+alksesp32.upload.tool.default=esptool_py
+alksesp32.upload.tool.network=esp_ota
+
 alksesp32.upload.maximum_size=1310720
 alksesp32.upload.maximum_data_size=327680
-alksesp32.upload.wait_for_upload_port=true
+alksesp32.upload.flags=
+alksesp32.upload.extra_flags=
 
 alksesp32.serial.disableDTR=true
 alksesp32.serial.disableRTS=true
 
+alksesp32.build.tarch=xtensa
+alksesp32.build.bootloader_addr=0x1000
+alksesp32.build.target=esp32
 alksesp32.build.mcu=esp32
 alksesp32.build.core=esp32
 alksesp32.build.variant=alksesp32
@@ -3697,8 +27722,10 @@ alksesp32.build.defines=
 
 alksesp32.menu.PSRAM.disabled=Disabled
 alksesp32.menu.PSRAM.disabled.build.defines=
+alksesp32.menu.PSRAM.disabled.build.extra_libs=
 alksesp32.menu.PSRAM.enabled=Enabled
-alksesp32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+alksesp32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+alksesp32.menu.PSRAM.enabled.build.extra_libs=
 
 alksesp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
 alksesp32.menu.PartitionScheme.default.build.partitions=default
@@ -3724,7 +27751,7 @@ alksesp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
 alksesp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
 alksesp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 alksesp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-alksesp32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+alksesp32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
 alksesp32.menu.PartitionScheme.fatflash.build.partitions=ffat
 
 alksesp32.menu.CPUFreq.240=240MHz (WiFi/BT)
@@ -3750,12 +27777,6 @@ alksesp32.menu.FlashMode.qio.build.boot=qio
 alksesp32.menu.FlashMode.dio=DIO
 alksesp32.menu.FlashMode.dio.build.flash_mode=dio
 alksesp32.menu.FlashMode.dio.build.boot=dio
-alksesp32.menu.FlashMode.qout=QOUT
-alksesp32.menu.FlashMode.qout.build.flash_mode=dout
-alksesp32.menu.FlashMode.qout.build.boot=qout
-alksesp32.menu.FlashMode.dout=DOUT
-alksesp32.menu.FlashMode.dout.build.flash_mode=dout
-alksesp32.menu.FlashMode.dout.build.boot=dout
 
 alksesp32.menu.FlashFreq.80=80MHz
 alksesp32.menu.FlashFreq.80.build.flash_freq=80m
@@ -3766,10 +27787,8 @@ alksesp32.menu.FlashSize.4M=4MB (32Mb)
 alksesp32.menu.FlashSize.4M.build.flash_size=4MB
 alksesp32.menu.FlashSize.2M=2MB (16Mb)
 alksesp32.menu.FlashSize.2M.build.flash_size=2MB
-alksesp32.menu.FlashSize.2M.build.partitions=minimal
 alksesp32.menu.FlashSize.16M=16MB (128Mb)
 alksesp32.menu.FlashSize.16M.build.flash_size=16MB
-alksesp32.menu.FlashSize.16M.build.partitions=ffat
 
 alksesp32.menu.UploadSpeed.921600=921600
 alksesp32.menu.UploadSpeed.921600.upload.speed=921600
@@ -3799,19 +27818,33 @@ alksesp32.menu.DebugLevel.debug.build.code_debug=4
 alksesp32.menu.DebugLevel.verbose=Verbose
 alksesp32.menu.DebugLevel.verbose.build.code_debug=5
 
-##############################################################
+alksesp32.menu.EraseFlash.none=Disabled
+alksesp32.menu.EraseFlash.none.upload.erase_cmd=
+alksesp32.menu.EraseFlash.all=Enabled
+alksesp32.menu.EraseFlash.all.upload.erase_cmd=-e
 
+##############################################################
 
 wipy3.name=WiPy 3.0
 
+wipy3.bootloader.tool=esptool_py
+wipy3.bootloader.tool.default=esptool_py
+
 wipy3.upload.tool=esptool_py
+wipy3.upload.tool.default=esptool_py
+wipy3.upload.tool.network=esp_ota
+
 wipy3.upload.maximum_size=1310720
 wipy3.upload.maximum_data_size=294912
-wipy3.upload.wait_for_upload_port=true
+wipy3.upload.flags=
+wipy3.upload.extra_flags=
 
 wipy3.serial.disableDTR=true
 wipy3.serial.disableRTS=true
 
+wipy3.build.tarch=xtensa
+wipy3.build.bootloader_addr=0x1000
+wipy3.build.target=esp32
 wipy3.build.mcu=esp32
 wipy3.build.core=esp32
 wipy3.build.variant=wipy3
@@ -3857,22 +27890,295 @@ wipy3.menu.DebugLevel.debug.build.code_debug=4
 wipy3.menu.DebugLevel.verbose=Verbose
 wipy3.menu.DebugLevel.verbose.build.code_debug=5
 
+wipy3.menu.EraseFlash.none=Disabled
+wipy3.menu.EraseFlash.none.upload.erase_cmd=
+wipy3.menu.EraseFlash.all=Enabled
+wipy3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+wt32-eth01.name=WT32-ETH01 Ethernet Module
+
+wt32-eth01.bootloader.tool=esptool_py
+wt32-eth01.bootloader.tool.default=esptool_py
+
+wt32-eth01.upload.tool=esptool_py
+wt32-eth01.upload.tool.default=esptool_py
+wt32-eth01.upload.tool.network=esp_ota
+
+wt32-eth01.upload.maximum_size=8388608
+wt32-eth01.upload.maximum_data_size=327680
+wt32-eth01.upload.flags=
+wt32-eth01.upload.extra_flags=
+
+wt32-eth01.serial.disableDTR=true
+wt32-eth01.serial.disableRTS=true
+
+wt32-eth01.build.tarch=xtensa
+wt32-eth01.build.bootloader_addr=0x1000
+wt32-eth01.build.target=esp32
+wt32-eth01.build.mcu=esp32
+wt32-eth01.build.core=esp32
+wt32-eth01.build.variant=wt32-eth01
+wt32-eth01.build.board=WT32_ETH01
+
+wt32-eth01.build.f_cpu=240000000L
+wt32-eth01.build.flash_size=4MB
+wt32-eth01.build.flash_freq=40m
+wt32-eth01.build.flash_mode=dio
+wt32-eth01.build.boot=dio
+wt32-eth01.build.partitions=default
+wt32-eth01.build.defines=
+wt32-eth01.build.extra_libs=
+
+wt32-eth01.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+wt32-eth01.menu.PartitionScheme.default.build.partitions=default
+wt32-eth01.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+wt32-eth01.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+wt32-eth01.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+wt32-eth01.menu.PartitionScheme.minimal.build.partitions=minimal
+wt32-eth01.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+wt32-eth01.menu.PartitionScheme.no_ota.build.partitions=no_ota
+wt32-eth01.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+wt32-eth01.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+wt32-eth01.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+wt32-eth01.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+wt32-eth01.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+wt32-eth01.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+wt32-eth01.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+wt32-eth01.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+wt32-eth01.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+wt32-eth01.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+wt32-eth01.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+wt32-eth01.menu.PartitionScheme.huge_app.build.partitions=huge_app
+wt32-eth01.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+wt32-eth01.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+wt32-eth01.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+wt32-eth01.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+wt32-eth01.menu.FlashMode.qio=QIO
+wt32-eth01.menu.FlashMode.qio.build.flash_mode=dio
+wt32-eth01.menu.FlashMode.qio.build.boot=qio
+wt32-eth01.menu.FlashMode.dio=DIO
+wt32-eth01.menu.FlashMode.dio.build.flash_mode=dio
+wt32-eth01.menu.FlashMode.dio.build.boot=dio
+
+wt32-eth01.menu.FlashFreq.80=80MHz
+wt32-eth01.menu.FlashFreq.80.build.flash_freq=80m
+wt32-eth01.menu.FlashFreq.40=40MHz
+wt32-eth01.menu.FlashFreq.40.build.flash_freq=40m
+
+wt32-eth01.menu.UploadSpeed.921600=921600
+wt32-eth01.menu.UploadSpeed.921600.upload.speed=921600
+wt32-eth01.menu.UploadSpeed.115200=115200
+wt32-eth01.menu.UploadSpeed.115200.upload.speed=115200
+wt32-eth01.menu.UploadSpeed.256000.windows=256000
+wt32-eth01.menu.UploadSpeed.256000.upload.speed=256000
+wt32-eth01.menu.UploadSpeed.230400.windows.upload.speed=256000
+wt32-eth01.menu.UploadSpeed.230400=230400
+wt32-eth01.menu.UploadSpeed.230400.upload.speed=230400
+wt32-eth01.menu.UploadSpeed.460800.linux=460800
+wt32-eth01.menu.UploadSpeed.460800.macosx=460800
+wt32-eth01.menu.UploadSpeed.460800.upload.speed=460800
+wt32-eth01.menu.UploadSpeed.512000.windows=512000
+wt32-eth01.menu.UploadSpeed.512000.upload.speed=512000
+
+wt32-eth01.menu.DebugLevel.none=None
+wt32-eth01.menu.DebugLevel.none.build.code_debug=0
+wt32-eth01.menu.DebugLevel.error=Error
+wt32-eth01.menu.DebugLevel.error.build.code_debug=1
+wt32-eth01.menu.DebugLevel.warn=Warn
+wt32-eth01.menu.DebugLevel.warn.build.code_debug=2
+wt32-eth01.menu.DebugLevel.info=Info
+wt32-eth01.menu.DebugLevel.info.build.code_debug=3
+wt32-eth01.menu.DebugLevel.debug=Debug
+wt32-eth01.menu.DebugLevel.debug.build.code_debug=4
+wt32-eth01.menu.DebugLevel.verbose=Verbose
+wt32-eth01.menu.DebugLevel.verbose.build.code_debug=5
+
+wt32-eth01.menu.EraseFlash.none=Disabled
+wt32-eth01.menu.EraseFlash.none.upload.erase_cmd=
+wt32-eth01.menu.EraseFlash.all=Enabled
+wt32-eth01.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+wt32-sc01-plus.name=WT32-SC01 PLUS
+wt32-sc01-plus.vid.0=0x303a
+wt32-sc01-plus.pid.0=0x80D0
+
+wt32-sc01-plus.bootloader.tool=esptool_py
+wt32-sc01-plus.bootloader.tool.default=esptool_py
+
+wt32-sc01-plus.upload.tool=esptool_py
+wt32-sc01-plus.upload.tool.default=esptool_py
+wt32-sc01-plus.upload.tool.network=esp_ota
+
+wt32-sc01-plus.upload.maximum_size=1310720
+wt32-sc01-plus.upload.maximum_data_size=327680
+wt32-sc01-plus.upload.flags=
+wt32-sc01-plus.upload.extra_flags=
+wt32-sc01-plus.upload.use_1200bps_touch=false
+wt32-sc01-plus.upload.wait_for_upload_port=false
+
+wt32-sc01-plus.serial.disableDTR=false
+wt32-sc01-plus.serial.disableRTS=false
+
+wt32-sc01-plus.build.tarch=xtensa
+wt32-sc01-plus.build.bootloader_addr=0x0
+wt32-sc01-plus.build.target=esp32s3
+wt32-sc01-plus.build.mcu=esp32s3
+wt32-sc01-plus.build.core=esp32
+wt32-sc01-plus.build.variant=wt32-sc01-plus
+wt32-sc01-plus.build.board=WT32_SC01_PLUS
+
+wt32-sc01-plus.build.usb_mode=1
+wt32-sc01-plus.build.cdc_on_boot=1
+wt32-sc01-plus.build.msc_on_boot=0
+wt32-sc01-plus.build.dfu_on_boot=0
+wt32-sc01-plus.build.f_cpu=240000000L
+wt32-sc01-plus.build.flash_size=16MB
+wt32-sc01-plus.build.flash_freq=80m
+wt32-sc01-plus.build.flash_mode=dio
+wt32-sc01-plus.build.boot=qio
+wt32-sc01-plus.build.partitions=default
+wt32-sc01-plus.build.defines=
+wt32-sc01-plus.build.loop_core=
+wt32-sc01-plus.build.event_core=
+wt32-sc01-plus.build.flash_type=qio
+wt32-sc01-plus.build.psram_type=qspi
+wt32-sc01-plus.build.memory_type=qio_qspi
+
+wt32-sc01-plus.menu.LoopCore.1=Core 1
+wt32-sc01-plus.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+wt32-sc01-plus.menu.LoopCore.0=Core 0
+wt32-sc01-plus.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+wt32-sc01-plus.menu.EventsCore.1=Core 1
+wt32-sc01-plus.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+wt32-sc01-plus.menu.EventsCore.0=Core 0
+wt32-sc01-plus.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+wt32-sc01-plus.menu.USBMode.hwcdc=Hardware CDC and JTAG
+wt32-sc01-plus.menu.USBMode.hwcdc.build.usb_mode=1
+wt32-sc01-plus.menu.USBMode.default=USB-OTG (TinyUSB)
+wt32-sc01-plus.menu.USBMode.default.build.usb_mode=0
+
+wt32-sc01-plus.menu.CDCOnBoot.cdc=Enabled
+wt32-sc01-plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+wt32-sc01-plus.menu.CDCOnBoot.default=Disabled
+wt32-sc01-plus.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+wt32-sc01-plus.menu.MSCOnBoot.default=Disabled
+wt32-sc01-plus.menu.MSCOnBoot.default.build.msc_on_boot=0
+wt32-sc01-plus.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+wt32-sc01-plus.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+wt32-sc01-plus.menu.DFUOnBoot.default=Disabled
+wt32-sc01-plus.menu.DFUOnBoot.default.build.dfu_on_boot=0
+wt32-sc01-plus.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+wt32-sc01-plus.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+wt32-sc01-plus.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+wt32-sc01-plus.menu.UploadMode.default=UART0 / Hardware CDC
+wt32-sc01-plus.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+wt32-sc01-plus.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+wt32-sc01-plus.menu.UploadMode.default.upload.use_1200bps_touch=false
+wt32-sc01-plus.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+wt32-sc01-plus.menu.PSRAM.enabled=Enabled
+wt32-sc01-plus.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+wt32-sc01-plus.menu.PSRAM.disabled=Disabled
+wt32-sc01-plus.menu.PSRAM.disabled.build.defines=
+
+wt32-sc01-plus.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+wt32-sc01-plus.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+wt32-sc01-plus.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+wt32-sc01-plus.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/3.7MB FFAT)
+wt32-sc01-plus.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
+wt32-sc01-plus.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
+wt32-sc01-plus.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+wt32-sc01-plus.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+
+wt32-sc01-plus.menu.CPUFreq.240=240MHz (WiFi)
+wt32-sc01-plus.menu.CPUFreq.240.build.f_cpu=240000000L
+wt32-sc01-plus.menu.CPUFreq.160=160MHz (WiFi)
+wt32-sc01-plus.menu.CPUFreq.160.build.f_cpu=160000000L
+wt32-sc01-plus.menu.CPUFreq.80=80MHz (WiFi)
+wt32-sc01-plus.menu.CPUFreq.80.build.f_cpu=80000000L
+wt32-sc01-plus.menu.CPUFreq.40=40MHz
+wt32-sc01-plus.menu.CPUFreq.40.build.f_cpu=40000000L
+wt32-sc01-plus.menu.CPUFreq.20=20MHz
+wt32-sc01-plus.menu.CPUFreq.20.build.f_cpu=20000000L
+wt32-sc01-plus.menu.CPUFreq.10=10MHz
+wt32-sc01-plus.menu.CPUFreq.10.build.f_cpu=10000000L
+
+wt32-sc01-plus.menu.FlashMode.qio=QIO
+wt32-sc01-plus.menu.FlashMode.qio.build.flash_mode=dio
+wt32-sc01-plus.menu.FlashMode.qio.build.boot=qio
+wt32-sc01-plus.menu.FlashMode.dio=DIO
+wt32-sc01-plus.menu.FlashMode.dio.build.flash_mode=dio
+wt32-sc01-plus.menu.FlashMode.dio.build.boot=dio
+
+wt32-sc01-plus.menu.UploadSpeed.921600=921600
+wt32-sc01-plus.menu.UploadSpeed.921600.upload.speed=921600
+wt32-sc01-plus.menu.UploadSpeed.115200=115200
+wt32-sc01-plus.menu.UploadSpeed.115200.upload.speed=115200
+wt32-sc01-plus.menu.UploadSpeed.256000.windows=256000
+wt32-sc01-plus.menu.UploadSpeed.256000.upload.speed=256000
+wt32-sc01-plus.menu.UploadSpeed.230400.windows.upload.speed=256000
+wt32-sc01-plus.menu.UploadSpeed.230400=230400
+wt32-sc01-plus.menu.UploadSpeed.230400.upload.speed=230400
+wt32-sc01-plus.menu.UploadSpeed.460800.linux=460800
+wt32-sc01-plus.menu.UploadSpeed.460800.macosx=460800
+wt32-sc01-plus.menu.UploadSpeed.460800.upload.speed=460800
+wt32-sc01-plus.menu.UploadSpeed.512000.windows=512000
+wt32-sc01-plus.menu.UploadSpeed.512000.upload.speed=512000
+
+wt32-sc01-plus.menu.DebugLevel.none=None
+wt32-sc01-plus.menu.DebugLevel.none.build.code_debug=0
+wt32-sc01-plus.menu.DebugLevel.error=Error
+wt32-sc01-plus.menu.DebugLevel.error.build.code_debug=1
+wt32-sc01-plus.menu.DebugLevel.warn=Warn
+wt32-sc01-plus.menu.DebugLevel.warn.build.code_debug=2
+wt32-sc01-plus.menu.DebugLevel.info=Info
+wt32-sc01-plus.menu.DebugLevel.info.build.code_debug=3
+wt32-sc01-plus.menu.DebugLevel.debug=Debug
+wt32-sc01-plus.menu.DebugLevel.debug.build.code_debug=4
+wt32-sc01-plus.menu.DebugLevel.verbose=Verbose
+wt32-sc01-plus.menu.DebugLevel.verbose.build.code_debug=5
+
+wt32-sc01-plus.menu.EraseFlash.none=Disabled
+wt32-sc01-plus.menu.EraseFlash.none.upload.erase_cmd=
+wt32-sc01-plus.menu.EraseFlash.all=Enabled
+wt32-sc01-plus.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 bpi-bit.name=BPI-BIT
 
+bpi-bit.bootloader.tool=esptool_py
+bpi-bit.bootloader.tool.default=esptool_py
+
 bpi-bit.upload.tool=esptool_py
+bpi-bit.upload.tool.default=esptool_py
+bpi-bit.upload.tool.network=esp_ota
+
 bpi-bit.upload.maximum_size=1310720
 bpi-bit.upload.maximum_data_size=294912
-bpi-bit.upload.wait_for_upload_port=true
+bpi-bit.upload.flags=
+bpi-bit.upload.extra_flags=
 
 bpi-bit.serial.disableDTR=true
 bpi-bit.serial.disableRTS=true
 
+bpi-bit.build.tarch=xtensa
+bpi-bit.build.bootloader_addr=0x1000
+bpi-bit.build.target=esp32
 bpi-bit.build.mcu=esp32
 bpi-bit.build.core=esp32
 bpi-bit.build.variant=bpi-bit
-bpi-bit.build.board=BPI-BIT
+bpi-bit.build.board=BPI_BIT
 
 bpi-bit.build.f_cpu=160000000L
 bpi-bit.build.flash_mode=dio
@@ -3900,18 +28206,260 @@ bpi-bit.menu.UploadSpeed.460800.upload.speed=460800
 bpi-bit.menu.UploadSpeed.512000.windows=512000
 bpi-bit.menu.UploadSpeed.512000.upload.speed=512000
 
+bpi-bit.menu.DebugLevel.none=None
+bpi-bit.menu.DebugLevel.none.build.code_debug=0
+bpi-bit.menu.DebugLevel.error=Error
+bpi-bit.menu.DebugLevel.error.build.code_debug=1
+bpi-bit.menu.DebugLevel.warn=Warn
+bpi-bit.menu.DebugLevel.warn.build.code_debug=2
+bpi-bit.menu.DebugLevel.info=Info
+bpi-bit.menu.DebugLevel.info.build.code_debug=3
+bpi-bit.menu.DebugLevel.debug=Debug
+bpi-bit.menu.DebugLevel.debug.build.code_debug=4
+bpi-bit.menu.DebugLevel.verbose=Verbose
+bpi-bit.menu.DebugLevel.verbose.build.code_debug=5
+
+bpi-bit.menu.EraseFlash.none=Disabled
+bpi-bit.menu.EraseFlash.none.upload.erase_cmd=
+bpi-bit.menu.EraseFlash.all=Enabled
+bpi-bit.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+bpi_leaf_s3.name=BPI-Leaf-S3
+bpi_leaf_s3.vid.0=0x303a
+bpi_leaf_s3.pid.0=0x80df
+
+bpi_leaf_s3.bootloader.tool=esptool_py
+bpi_leaf_s3.bootloader.tool.default=esptool_py
+
+bpi_leaf_s3.upload.tool=esptool_py
+bpi_leaf_s3.upload.tool.default=esptool_py
+bpi_leaf_s3.upload.tool.network=esp_ota
+
+bpi_leaf_s3.upload.maximum_size=1310720
+bpi_leaf_s3.upload.maximum_data_size=327680
+bpi_leaf_s3.upload.flags=
+bpi_leaf_s3.upload.extra_flags=
+bpi_leaf_s3.upload.use_1200bps_touch=false
+bpi_leaf_s3.upload.wait_for_upload_port=false
+
+bpi_leaf_s3.serial.disableDTR=false
+bpi_leaf_s3.serial.disableRTS=false
+
+bpi_leaf_s3.build.tarch=xtensa
+bpi_leaf_s3.build.bootloader_addr=0x0
+bpi_leaf_s3.build.target=esp32s3
+bpi_leaf_s3.build.mcu=esp32s3
+bpi_leaf_s3.build.core=esp32
+bpi_leaf_s3.build.variant=bpi_leaf_s3
+bpi_leaf_s3.build.board=BPI_LEAF_S3
+
+bpi_leaf_s3.build.usb_mode=1
+bpi_leaf_s3.build.cdc_on_boot=0
+bpi_leaf_s3.build.msc_on_boot=0
+bpi_leaf_s3.build.dfu_on_boot=0
+bpi_leaf_s3.build.f_cpu=240000000L
+bpi_leaf_s3.build.flash_size=8MB
+bpi_leaf_s3.build.flash_freq=80m
+bpi_leaf_s3.build.flash_mode=dio
+bpi_leaf_s3.build.boot=qio
+bpi_leaf_s3.build.boot_freq=80m
+bpi_leaf_s3.build.partitions=default
+bpi_leaf_s3.build.defines=
+bpi_leaf_s3.build.loop_core=
+bpi_leaf_s3.build.event_core=
+bpi_leaf_s3.build.psram_type=qspi
+bpi_leaf_s3.build.memory_type={build.boot}_{build.psram_type}
+
+bpi_leaf_s3.menu.PSRAM.enabled=QSPI PSRAM
+bpi_leaf_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+bpi_leaf_s3.menu.PSRAM.enabled.build.psram_type=qspi
+bpi_leaf_s3.menu.PSRAM.disabled=Disabled
+bpi_leaf_s3.menu.PSRAM.disabled.build.defines=
+bpi_leaf_s3.menu.PSRAM.disabled.build.psram_type=qspi
+bpi_leaf_s3.menu.PSRAM.opi=OPI PSRAM
+bpi_leaf_s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+bpi_leaf_s3.menu.PSRAM.opi.build.psram_type=opi
+
+bpi_leaf_s3.menu.FlashMode.qio=QIO 80MHz
+bpi_leaf_s3.menu.FlashMode.qio.build.flash_mode=dio
+bpi_leaf_s3.menu.FlashMode.qio.build.boot=qio
+bpi_leaf_s3.menu.FlashMode.qio.build.boot_freq=80m
+bpi_leaf_s3.menu.FlashMode.qio.build.flash_freq=80m
+bpi_leaf_s3.menu.FlashMode.qio120=QIO 120MHz
+bpi_leaf_s3.menu.FlashMode.qio120.build.flash_mode=dio
+bpi_leaf_s3.menu.FlashMode.qio120.build.boot=qio
+bpi_leaf_s3.menu.FlashMode.qio120.build.boot_freq=120m
+bpi_leaf_s3.menu.FlashMode.qio120.build.flash_freq=80m
+bpi_leaf_s3.menu.FlashMode.dio=DIO 80MHz
+bpi_leaf_s3.menu.FlashMode.dio.build.flash_mode=dio
+bpi_leaf_s3.menu.FlashMode.dio.build.boot=dio
+bpi_leaf_s3.menu.FlashMode.dio.build.boot_freq=80m
+bpi_leaf_s3.menu.FlashMode.dio.build.flash_freq=80m
+bpi_leaf_s3.menu.FlashMode.opi=OPI 80MHz
+bpi_leaf_s3.menu.FlashMode.opi.build.flash_mode=dout
+bpi_leaf_s3.menu.FlashMode.opi.build.boot=opi
+bpi_leaf_s3.menu.FlashMode.opi.build.boot_freq=80m
+bpi_leaf_s3.menu.FlashMode.opi.build.flash_freq=80m
+
+bpi_leaf_s3.menu.FlashSize.8M=8MB (64Mb)
+bpi_leaf_s3.menu.FlashSize.8M.build.flash_size=8MB
+bpi_leaf_s3.menu.FlashSize.4M=4MB (32Mb)
+bpi_leaf_s3.menu.FlashSize.4M.build.flash_size=4MB
+bpi_leaf_s3.menu.FlashSize.16M=16MB (128Mb)
+bpi_leaf_s3.menu.FlashSize.16M.build.flash_size=16MB
+#bpi_leaf_s3.menu.FlashSize.32M=32MB (256Mb)
+#bpi_leaf_s3.menu.FlashSize.32M.build.flash_size=32MB
+
+bpi_leaf_s3.menu.LoopCore.1=Core 1
+bpi_leaf_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+bpi_leaf_s3.menu.LoopCore.0=Core 0
+bpi_leaf_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+bpi_leaf_s3.menu.EventsCore.1=Core 1
+bpi_leaf_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+bpi_leaf_s3.menu.EventsCore.0=Core 0
+bpi_leaf_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+bpi_leaf_s3.menu.USBMode.default=USB-OTG (TinyUSB)
+bpi_leaf_s3.menu.USBMode.default.build.usb_mode=0
+bpi_leaf_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+bpi_leaf_s3.menu.USBMode.hwcdc.build.usb_mode=1
+
+bpi_leaf_s3.menu.CDCOnBoot.cdc=Enabled
+bpi_leaf_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+bpi_leaf_s3.menu.CDCOnBoot.default=Disabled
+bpi_leaf_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+bpi_leaf_s3.menu.MSCOnBoot.default=Disabled
+bpi_leaf_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+bpi_leaf_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+bpi_leaf_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+bpi_leaf_s3.menu.DFUOnBoot.default=Disabled
+bpi_leaf_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+bpi_leaf_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+bpi_leaf_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+bpi_leaf_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+bpi_leaf_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+bpi_leaf_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+bpi_leaf_s3.menu.UploadMode.default=UART0 / Hardware CDC
+bpi_leaf_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+bpi_leaf_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+bpi_leaf_s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+bpi_leaf_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+bpi_leaf_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+bpi_leaf_s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+bpi_leaf_s3.menu.PartitionScheme.default.build.partitions=default
+bpi_leaf_s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+bpi_leaf_s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+bpi_leaf_s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+bpi_leaf_s3.menu.PartitionScheme.minimal.build.partitions=minimal
+bpi_leaf_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+bpi_leaf_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+bpi_leaf_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+bpi_leaf_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+bpi_leaf_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+bpi_leaf_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+bpi_leaf_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+bpi_leaf_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+bpi_leaf_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+bpi_leaf_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+bpi_leaf_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+bpi_leaf_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+bpi_leaf_s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+bpi_leaf_s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+bpi_leaf_s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+bpi_leaf_s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+bpi_leaf_s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+bpi_leaf_s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+bpi_leaf_s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+bpi_leaf_s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+bpi_leaf_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+bpi_leaf_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+bpi_leaf_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+bpi_leaf_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+bpi_leaf_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+bpi_leaf_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+bpi_leaf_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+bpi_leaf_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+bpi_leaf_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+bpi_leaf_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+bpi_leaf_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+bpi_leaf_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+bpi_leaf_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+bpi_leaf_s3.menu.CPUFreq.240=240MHz (WiFi)
+bpi_leaf_s3.menu.CPUFreq.240.build.f_cpu=240000000L
+bpi_leaf_s3.menu.CPUFreq.160=160MHz (WiFi)
+bpi_leaf_s3.menu.CPUFreq.160.build.f_cpu=160000000L
+bpi_leaf_s3.menu.CPUFreq.80=80MHz (WiFi)
+bpi_leaf_s3.menu.CPUFreq.80.build.f_cpu=80000000L
+bpi_leaf_s3.menu.CPUFreq.40=40MHz
+bpi_leaf_s3.menu.CPUFreq.40.build.f_cpu=40000000L
+bpi_leaf_s3.menu.CPUFreq.20=20MHz
+bpi_leaf_s3.menu.CPUFreq.20.build.f_cpu=20000000L
+bpi_leaf_s3.menu.CPUFreq.10=10MHz
+bpi_leaf_s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+bpi_leaf_s3.menu.UploadSpeed.921600=921600
+bpi_leaf_s3.menu.UploadSpeed.921600.upload.speed=921600
+bpi_leaf_s3.menu.UploadSpeed.115200=115200
+bpi_leaf_s3.menu.UploadSpeed.115200.upload.speed=115200
+bpi_leaf_s3.menu.UploadSpeed.256000.windows=256000
+bpi_leaf_s3.menu.UploadSpeed.256000.upload.speed=256000
+bpi_leaf_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+bpi_leaf_s3.menu.UploadSpeed.230400=230400
+bpi_leaf_s3.menu.UploadSpeed.230400.upload.speed=230400
+bpi_leaf_s3.menu.UploadSpeed.460800.linux=460800
+bpi_leaf_s3.menu.UploadSpeed.460800.macosx=460800
+bpi_leaf_s3.menu.UploadSpeed.460800.upload.speed=460800
+bpi_leaf_s3.menu.UploadSpeed.512000.windows=512000
+bpi_leaf_s3.menu.UploadSpeed.512000.upload.speed=512000
+
+bpi_leaf_s3.menu.DebugLevel.none=None
+bpi_leaf_s3.menu.DebugLevel.none.build.code_debug=0
+bpi_leaf_s3.menu.DebugLevel.error=Error
+bpi_leaf_s3.menu.DebugLevel.error.build.code_debug=1
+bpi_leaf_s3.menu.DebugLevel.warn=Warn
+bpi_leaf_s3.menu.DebugLevel.warn.build.code_debug=2
+bpi_leaf_s3.menu.DebugLevel.info=Info
+bpi_leaf_s3.menu.DebugLevel.info.build.code_debug=3
+bpi_leaf_s3.menu.DebugLevel.debug=Debug
+bpi_leaf_s3.menu.DebugLevel.debug.build.code_debug=4
+bpi_leaf_s3.menu.DebugLevel.verbose=Verbose
+bpi_leaf_s3.menu.DebugLevel.verbose.build.code_debug=5
+
+bpi_leaf_s3.menu.EraseFlash.none=Disabled
+bpi_leaf_s3.menu.EraseFlash.none.upload.erase_cmd=
+bpi_leaf_s3.menu.EraseFlash.all=Enabled
+bpi_leaf_s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 wesp32.name=Silicognition wESP32
 
+wesp32.bootloader.tool=esptool_py
+wesp32.bootloader.tool.default=esptool_py
+
 wesp32.upload.tool=esptool_py
+wesp32.upload.tool.default=esptool_py
+wesp32.upload.tool.network=esp_ota
+
 wesp32.upload.maximum_size=1310720
 wesp32.upload.maximum_data_size=327680
-wesp32.upload.wait_for_upload_port=true
+wesp32.upload.flags=
+wesp32.upload.extra_flags=
 
 wesp32.serial.disableDTR=true
 wesp32.serial.disableRTS=true
 
+wesp32.build.tarch=xtensa
+wesp32.build.bootloader_addr=0x1000
+wesp32.build.target=esp32
 wesp32.build.mcu=esp32
 wesp32.build.core=esp32
 wesp32.build.variant=wesp32
@@ -3957,23 +28505,49 @@ wesp32.menu.DebugLevel.debug.build.code_debug=4
 wesp32.menu.DebugLevel.verbose=Verbose
 wesp32.menu.DebugLevel.verbose.build.code_debug=5
 
+wesp32.menu.EraseFlash.none=Disabled
+wesp32.menu.EraseFlash.none.upload.erase_cmd=
+wesp32.menu.EraseFlash.all=Enabled
+wesp32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 t-beam.name=T-Beam
 
+t-beam.bootloader.tool=esptool_py
+t-beam.bootloader.tool.default=esptool_py
+
 t-beam.upload.tool=esptool_py
+t-beam.upload.tool.default=esptool_py
+t-beam.upload.tool.network=esp_ota
+
 t-beam.upload.maximum_size=1310720
 t-beam.upload.maximum_data_size=327680
-t-beam.upload.wait_for_upload_port=true
+t-beam.upload.flags=
+t-beam.upload.extra_flags=
 
 t-beam.serial.disableDTR=true
 t-beam.serial.disableRTS=true
 
+t-beam.build.tarch=xtensa
+t-beam.build.bootloader_addr=0x1000
+t-beam.build.target=esp32
 t-beam.build.mcu=esp32
 t-beam.build.core=esp32
 t-beam.build.variant=tbeam
 t-beam.build.board=TBeam
 
+t-beam.menu.Revision.Radio_SX1262=Radio-SX1262
+t-beam.menu.Revision.Radio_SX1262.build.board=TBEAM_USE_RADIO_SX1262
+t-beam.menu.Revision.Radio_SX1276=Radio-SX1276
+t-beam.menu.Revision.Radio_SX1276.build.board=TBEAM_USE_RADIO_SX1276
+t-beam.menu.Revision.Radio_SX1278=Radio-SX1278
+t-beam.menu.Revision.Radio_SX1278.build.board=TBEAM_USE_RADIO_SX1278
+t-beam.menu.Revision.Radio_SX1280=Radio-SX1280
+t-beam.menu.Revision.Radio_SX1280.build.board=TBEAM_USE_RADIO_SX1280
+t-beam.menu.Revision.Radio_SX1268=Radio-SX1268
+t-beam.menu.Revision.Radio_SX1268.build.board=TBEAM_USE_RADIO_SX1268
+
 t-beam.build.f_cpu=240000000L
 t-beam.build.flash_mode=dio
 t-beam.build.flash_size=4MB
@@ -3982,8 +28556,10 @@ t-beam.build.partitions=default
 
 t-beam.menu.PSRAM.disabled=Disabled
 t-beam.menu.PSRAM.disabled.build.defines=
+t-beam.menu.PSRAM.disabled.build.extra_libs=
 t-beam.menu.PSRAM.enabled=Enabled
-t-beam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+t-beam.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+t-beam.menu.PSRAM.enabled.build.extra_libs=
 
 t-beam.menu.FlashFreq.80=80MHz
 t-beam.menu.FlashFreq.80.build.flash_freq=80m
@@ -4018,22 +28594,37 @@ t-beam.menu.DebugLevel.debug.build.code_debug=4
 t-beam.menu.DebugLevel.verbose=Verbose
 t-beam.menu.DebugLevel.verbose.build.code_debug=5
 
+t-beam.menu.EraseFlash.none=Disabled
+t-beam.menu.EraseFlash.none.upload.erase_cmd=
+t-beam.menu.EraseFlash.all=Enabled
+t-beam.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 d-duino-32.name=D-duino-32
 
+d-duino-32.bootloader.tool=esptool_py
+d-duino-32.bootloader.tool.default=esptool_py
+
 d-duino-32.upload.tool=esptool_py
+d-duino-32.upload.tool.default=esptool_py
+d-duino-32.upload.tool.network=esp_ota
+
 d-duino-32.upload.maximum_size=1310720
 d-duino-32.upload.maximum_data_size=327680
-d-duino-32.upload.wait_for_upload_port=true
+d-duino-32.upload.flags=
+d-duino-32.upload.extra_flags=
 
 d-duino-32.serial.disableDTR=true
 d-duino-32.serial.disableRTS=true
 
+d-duino-32.build.tarch=xtensa
+d-duino-32.build.bootloader_addr=0x1000
+d-duino-32.build.target=esp32
 d-duino-32.build.mcu=esp32
 d-duino-32.build.core=esp32
 d-duino-32.build.variant=d-duino-32
-d-duino-32.build.board=D-duino-32
+d-duino-32.build.board=D_Duino_32
 
 d-duino-32.build.f_cpu=240000000L
 d-duino-32.build.flash_size=4MB
@@ -4089,18 +28680,33 @@ d-duino-32.menu.DebugLevel.debug.build.code_debug=4
 d-duino-32.menu.DebugLevel.verbose=Verbose
 d-duino-32.menu.DebugLevel.verbose.build.code_debug=5
 
+d-duino-32.menu.EraseFlash.none=Disabled
+d-duino-32.menu.EraseFlash.none.upload.erase_cmd=
+d-duino-32.menu.EraseFlash.all=Enabled
+d-duino-32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 lopy.name=LoPy
 
+lopy.bootloader.tool=esptool_py
+lopy.bootloader.tool.default=esptool_py
+
 lopy.upload.tool=esptool_py
+lopy.upload.tool.default=esptool_py
+lopy.upload.tool.network=esp_ota
+
 lopy.upload.maximum_size=1310720
 lopy.upload.maximum_data_size=327680
-lopy.upload.wait_for_upload_port=true
+lopy.upload.flags=
+lopy.upload.extra_flags=
 
 lopy.serial.disableDTR=true
 lopy.serial.disableRTS=true
 
+lopy.build.tarch=xtensa
+lopy.build.bootloader_addr=0x1000
+lopy.build.target=esp32
 lopy.build.mcu=esp32
 lopy.build.core=esp32
 lopy.build.variant=lopy
@@ -4145,18 +28751,33 @@ lopy.menu.DebugLevel.debug.build.code_debug=4
 lopy.menu.DebugLevel.verbose=Verbose
 lopy.menu.DebugLevel.verbose.build.code_debug=5
 
+lopy.menu.EraseFlash.none=Disabled
+lopy.menu.EraseFlash.none.upload.erase_cmd=
+lopy.menu.EraseFlash.all=Enabled
+lopy.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 lopy4.name=LoPy4
 
+lopy4.bootloader.tool=esptool_py
+lopy4.bootloader.tool.default=esptool_py
+
 lopy4.upload.tool=esptool_py
+lopy4.upload.tool.default=esptool_py
+lopy4.upload.tool.network=esp_ota
+
 lopy4.upload.maximum_size=1310720
 lopy4.upload.maximum_data_size=327680
-lopy4.upload.wait_for_upload_port=true
+lopy4.upload.flags=
+lopy4.upload.extra_flags=
 
 lopy4.serial.disableDTR=true
 lopy4.serial.disableRTS=true
 
+lopy4.build.tarch=xtensa
+lopy4.build.bootloader_addr=0x1000
+lopy4.build.target=esp32
 lopy4.build.mcu=esp32
 lopy4.build.core=esp32
 lopy4.build.variant=lopy4
@@ -4170,8 +28791,10 @@ lopy4.build.partitions=default
 
 lopy4.menu.PSRAM.disabled=Disabled
 lopy4.menu.PSRAM.disabled.build.defines=
+lopy4.menu.PSRAM.disabled.build.extra_libs=
 lopy4.menu.PSRAM.enabled=Enabled
-lopy4.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+lopy4.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+lopy4.menu.PSRAM.enabled.build.extra_libs=
 
 lopy4.menu.FlashFreq.80=80MHz
 lopy4.menu.FlashFreq.80.build.flash_freq=80m
@@ -4206,18 +28829,33 @@ lopy4.menu.DebugLevel.debug.build.code_debug=4
 lopy4.menu.DebugLevel.verbose=Verbose
 lopy4.menu.DebugLevel.verbose.build.code_debug=5
 
+lopy4.menu.EraseFlash.none=Disabled
+lopy4.menu.EraseFlash.none.upload.erase_cmd=
+lopy4.menu.EraseFlash.all=Enabled
+lopy4.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 oroca_edubot.name=OROCA EduBot
 
+oroca_edubot.bootloader.tool=esptool_py
+oroca_edubot.bootloader.tool.default=esptool_py
+
 oroca_edubot.upload.tool=esptool_py
+oroca_edubot.upload.tool.default=esptool_py
+oroca_edubot.upload.tool.network=esp_ota
+
 oroca_edubot.upload.maximum_size=3145728
 oroca_edubot.upload.maximum_data_size=327680
-oroca_edubot.upload.wait_for_upload_port=true
+oroca_edubot.upload.flags=
+oroca_edubot.upload.extra_flags=
 
 oroca_edubot.serial.disableDTR=true
 oroca_edubot.serial.disableRTS=true
 
+oroca_edubot.build.tarch=xtensa
+oroca_edubot.build.bootloader_addr=0x1000
+oroca_edubot.build.target=esp32
 oroca_edubot.build.mcu=esp32
 oroca_edubot.build.core=esp32
 oroca_edubot.build.variant=oroca_edubot
@@ -4270,24 +28908,34 @@ oroca_edubot.menu.DebugLevel.debug.build.code_debug=4
 oroca_edubot.menu.DebugLevel.verbose=Verbose
 oroca_edubot.menu.DebugLevel.verbose.build.code_debug=5
 
-
+oroca_edubot.menu.EraseFlash.none=Disabled
+oroca_edubot.menu.EraseFlash.none.upload.erase_cmd=
+oroca_edubot.menu.EraseFlash.all=Enabled
+oroca_edubot.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
 
 fm-devkit.name=ESP32 FM DevKit
 
-fm-devkit.upload.tool=esptool
+fm-devkit.upload.tool=esptool_py
+fm-devkit.upload.tool.default=esptool_py
+fm-devkit.upload.tool.network=esp_ota
+
 fm-devkit.upload.maximum_size=1310720
 fm-devkit.upload.maximum_data_size=327680
-fm-devkit.upload.wait_for_upload_port=true
+fm-devkit.upload.flags=
+fm-devkit.upload.extra_flags=
 
 fm-devkit.serial.disableDTR=true
 fm-devkit.serial.disableRTS=true
 
+fm-devkit.build.tarch=xtensa
+fm-devkit.build.bootloader_addr=0x1000
+fm-devkit.build.target=esp32
 fm-devkit.build.mcu=esp32
 fm-devkit.build.core=esp32
 fm-devkit.build.variant=fm-devkit
-fm-devkit.build.board=fm-devkit
+fm-devkit.build.board=fm_devkit
 
 fm-devkit.build.f_cpu=240000000L
 fm-devkit.build.flash_size=4MB
@@ -4325,18 +28973,250 @@ fm-devkit.menu.DebugLevel.debug.build.code_debug=4
 fm-devkit.menu.DebugLevel.verbose=Verbose
 fm-devkit.menu.DebugLevel.verbose.build.code_debug=5
 
+fm-devkit.menu.EraseFlash.none=Disabled
+fm-devkit.menu.EraseFlash.none.upload.erase_cmd=
+fm-devkit.menu.EraseFlash.all=Enabled
+fm-devkit.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+### Fri3d Badge 2024 (ESP32-S3-WROOM-1)
+
+fri3d_2024_esp32s3.name=Fri3d Badge 2024 (ESP32-S3-WROOM-1)
+
+fri3d_2024_esp32s3.bootloader.tool=esptool_py
+fri3d_2024_esp32s3.bootloader.tool.default=esptool_py
+
+fri3d_2024_esp32s3.upload.tool=esptool_py
+fri3d_2024_esp32s3.upload.tool.default=esptool_py
+fri3d_2024_esp32s3.upload.tool.network=esp_ota
+
+fri3d_2024_esp32s3.upload.maximum_size=1310720
+fri3d_2024_esp32s3.upload.maximum_data_size=327680
+fri3d_2024_esp32s3.upload.flags=
+fri3d_2024_esp32s3.upload.extra_flags=
+fri3d_2024_esp32s3.upload.use_1200bps_touch=false
+fri3d_2024_esp32s3.upload.wait_for_upload_port=false
+
+fri3d_2024_esp32s3.serial.disableDTR=false
+fri3d_2024_esp32s3.serial.disableRTS=false
+
+fri3d_2024_esp32s3.build.tarch=xtensa
+fri3d_2024_esp32s3.build.bootloader_addr=0x0
+fri3d_2024_esp32s3.build.target=esp32s3
+fri3d_2024_esp32s3.build.mcu=esp32s3
+fri3d_2024_esp32s3.build.core=esp32
+fri3d_2024_esp32s3.build.variant=fri3d_2024_esp32s3
+fri3d_2024_esp32s3.build.board=FRI3D_2024_ESP32S3
+
+fri3d_2024_esp32s3.build.usb_mode=1
+fri3d_2024_esp32s3.build.cdc_on_boot=0
+fri3d_2024_esp32s3.build.msc_on_boot=0
+fri3d_2024_esp32s3.build.dfu_on_boot=0
+fri3d_2024_esp32s3.build.f_cpu=240000000L
+fri3d_2024_esp32s3.build.flash_size=16MB
+fri3d_2024_esp32s3.build.flash_freq=80m
+fri3d_2024_esp32s3.build.flash_mode=dio
+fri3d_2024_esp32s3.build.boot=qio
+fri3d_2024_esp32s3.build.boot_freq=80m
+fri3d_2024_esp32s3.build.partitions=default
+fri3d_2024_esp32s3.build.defines=
+fri3d_2024_esp32s3.build.loop_core=
+fri3d_2024_esp32s3.build.event_core=
+fri3d_2024_esp32s3.build.psram_type=opi
+fri3d_2024_esp32s3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+fri3d_2024_esp32s3.menu.JTAGAdapter.default=Disabled
+fri3d_2024_esp32s3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+fri3d_2024_esp32s3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+fri3d_2024_esp32s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+fri3d_2024_esp32s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+fri3d_2024_esp32s3.menu.JTAGAdapter.external=FTDI Adapter
+fri3d_2024_esp32s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+fri3d_2024_esp32s3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+fri3d_2024_esp32s3.menu.JTAGAdapter.bridge=ESP USB Bridge
+fri3d_2024_esp32s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+fri3d_2024_esp32s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+fri3d_2024_esp32s3.menu.PSRAM.default=OPI PSRAM
+fri3d_2024_esp32s3.menu.PSRAM.default.build.defines=-DBOARD_HAS_PSRAM
+fri3d_2024_esp32s3.menu.PSRAM.default.build.psram_type=opi
+fri3d_2024_esp32s3.menu.PSRAM.disabled=Disabled
+fri3d_2024_esp32s3.menu.PSRAM.disabled.build.defines=
+fri3d_2024_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi
+
+fri3d_2024_esp32s3.menu.FlashMode.qio=QIO 80MHz
+fri3d_2024_esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+fri3d_2024_esp32s3.menu.FlashMode.qio.build.boot=qio
+fri3d_2024_esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+fri3d_2024_esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+fri3d_2024_esp32s3.menu.FlashMode.qio120=QIO 120MHz
+fri3d_2024_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+fri3d_2024_esp32s3.menu.FlashMode.qio120.build.boot=qio
+fri3d_2024_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+fri3d_2024_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+fri3d_2024_esp32s3.menu.FlashMode.dio=DIO 80MHz
+fri3d_2024_esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+fri3d_2024_esp32s3.menu.FlashMode.dio.build.boot=dio
+fri3d_2024_esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+fri3d_2024_esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+fri3d_2024_esp32s3.menu.FlashMode.opi=OPI 80MHz
+fri3d_2024_esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+fri3d_2024_esp32s3.menu.FlashMode.opi.build.boot=opi
+fri3d_2024_esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+fri3d_2024_esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+
+fri3d_2024_esp32s3.menu.FlashSize.default=16MB (128Mb)
+fri3d_2024_esp32s3.menu.FlashSize.default.build.flash_size=16MB
+
+fri3d_2024_esp32s3.menu.LoopCore.1=Core 1
+fri3d_2024_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+fri3d_2024_esp32s3.menu.LoopCore.0=Core 0
+fri3d_2024_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+fri3d_2024_esp32s3.menu.EventsCore.1=Core 1
+fri3d_2024_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+fri3d_2024_esp32s3.menu.EventsCore.0=Core 0
+fri3d_2024_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+fri3d_2024_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+fri3d_2024_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+fri3d_2024_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+fri3d_2024_esp32s3.menu.USBMode.default.build.usb_mode=0
+
+fri3d_2024_esp32s3.menu.CDCOnBoot.default=Enabled
+fri3d_2024_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+fri3d_2024_esp32s3.menu.CDCOnBoot.disabled=Disabled
+fri3d_2024_esp32s3.menu.CDCOnBoot.disabled.build.cdc_on_boot=0
+
+fri3d_2024_esp32s3.menu.MSCOnBoot.default=Disabled
+fri3d_2024_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+fri3d_2024_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+fri3d_2024_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+fri3d_2024_esp32s3.menu.DFUOnBoot.default=Disabled
+fri3d_2024_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+fri3d_2024_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+fri3d_2024_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+fri3d_2024_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+fri3d_2024_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+fri3d_2024_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+fri3d_2024_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+fri3d_2024_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+fri3d_2024_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+fri3d_2024_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.default.build.partitions=default
+fri3d_2024_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+fri3d_2024_esp32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+fri3d_2024_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+fri3d_2024_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal
+fri3d_2024_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+fri3d_2024_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+fri3d_2024_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+fri3d_2024_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+fri3d_2024_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+fri3d_2024_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+fri3d_2024_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+fri3d_2024_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+fri3d_2024_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+fri3d_2024_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+fri3d_2024_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+fri3d_2024_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+fri3d_2024_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+fri3d_2024_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+fri3d_2024_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+fri3d_2024_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+fri3d_2024_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker=RainMaker
+fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+fri3d_2024_esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+fri3d_2024_esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+fri3d_2024_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+fri3d_2024_esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+fri3d_2024_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+fri3d_2024_esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+fri3d_2024_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+fri3d_2024_esp32s3.menu.CPUFreq.40=40MHz
+fri3d_2024_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+fri3d_2024_esp32s3.menu.CPUFreq.20=20MHz
+fri3d_2024_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+fri3d_2024_esp32s3.menu.CPUFreq.10=10MHz
+fri3d_2024_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+fri3d_2024_esp32s3.menu.UploadSpeed.921600=921600
+fri3d_2024_esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+fri3d_2024_esp32s3.menu.UploadSpeed.115200=115200
+fri3d_2024_esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+fri3d_2024_esp32s3.menu.UploadSpeed.256000.windows=256000
+fri3d_2024_esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+fri3d_2024_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+fri3d_2024_esp32s3.menu.UploadSpeed.230400=230400
+fri3d_2024_esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+fri3d_2024_esp32s3.menu.UploadSpeed.460800.linux=460800
+fri3d_2024_esp32s3.menu.UploadSpeed.460800.macosx=460800
+fri3d_2024_esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+fri3d_2024_esp32s3.menu.UploadSpeed.512000.windows=512000
+fri3d_2024_esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+fri3d_2024_esp32s3.menu.DebugLevel.none=None
+fri3d_2024_esp32s3.menu.DebugLevel.none.build.code_debug=0
+fri3d_2024_esp32s3.menu.DebugLevel.error=Error
+fri3d_2024_esp32s3.menu.DebugLevel.error.build.code_debug=1
+fri3d_2024_esp32s3.menu.DebugLevel.warn=Warn
+fri3d_2024_esp32s3.menu.DebugLevel.warn.build.code_debug=2
+fri3d_2024_esp32s3.menu.DebugLevel.info=Info
+fri3d_2024_esp32s3.menu.DebugLevel.info.build.code_debug=3
+fri3d_2024_esp32s3.menu.DebugLevel.debug=Debug
+fri3d_2024_esp32s3.menu.DebugLevel.debug.build.code_debug=4
+fri3d_2024_esp32s3.menu.DebugLevel.verbose=Verbose
+fri3d_2024_esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+fri3d_2024_esp32s3.menu.EraseFlash.none=Disabled
+fri3d_2024_esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+fri3d_2024_esp32s3.menu.EraseFlash.all=Enabled
+fri3d_2024_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 frogboard.name=Frog Board ESP32
 
+frogboard.bootloader.tool=esptool_py
+frogboard.bootloader.tool.default=esptool_py
+
 frogboard.upload.tool=esptool_py
+frogboard.upload.tool.default=esptool_py
+frogboard.upload.tool.network=esp_ota
+
 frogboard.upload.maximum_size=1310720
 frogboard.upload.maximum_data_size=327680
-frogboard.upload.wait_for_upload_port=true
+frogboard.upload.flags=
+frogboard.upload.extra_flags=
 
 frogboard.serial.disableDTR=true
 frogboard.serial.disableRTS=true
 
+frogboard.build.tarch=xtensa
+frogboard.build.bootloader_addr=0x1000
+frogboard.build.target=esp32
 frogboard.build.mcu=esp32
 frogboard.build.core=esp32
 frogboard.build.variant=frog32
@@ -4351,8 +29231,10 @@ frogboard.build.defines=
 
 frogboard.menu.PSRAM.disabled=Disabled
 frogboard.menu.PSRAM.disabled.build.defines=
+frogboard.menu.PSRAM.disabled.build.extra_libs=
 frogboard.menu.PSRAM.enabled=Enabled
-frogboard.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+frogboard.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+frogboard.menu.PSRAM.enabled.build.extra_libs=
 
 frogboard.menu.PartitionScheme.default=Default
 frogboard.menu.PartitionScheme.default.build.partitions=default
@@ -4371,12 +29253,6 @@ frogboard.menu.FlashMode.qio.build.boot=qio
 frogboard.menu.FlashMode.dio=DIO
 frogboard.menu.FlashMode.dio.build.flash_mode=dio
 frogboard.menu.FlashMode.dio.build.boot=dio
-frogboard.menu.FlashMode.qout=QOUT
-frogboard.menu.FlashMode.qout.build.flash_mode=dout
-frogboard.menu.FlashMode.qout.build.boot=qout
-frogboard.menu.FlashMode.dout=DOUT
-frogboard.menu.FlashMode.dout.build.flash_mode=dout
-frogboard.menu.FlashMode.dout.build.boot=dout
 frogboard.menu.FlashFreq.80=80MHz
 frogboard.menu.FlashFreq.80.build.flash_freq=80m
 frogboard.menu.FlashFreq.40=40MHz
@@ -4385,7 +29261,6 @@ frogboard.menu.FlashSize.4M=4MB (32Mb)
 frogboard.menu.FlashSize.4M.build.flash_size=4MB
 frogboard.menu.FlashSize.2M=2MB (16Mb)
 frogboard.menu.FlashSize.2M.build.flash_size=2MB
-frogboard.menu.FlashSize.2M.build.partitions=minimal
 
 frogboard.menu.UploadSpeed.921600=921600
 frogboard.menu.UploadSpeed.921600.upload.speed=921600
@@ -4415,26 +29290,42 @@ frogboard.menu.DebugLevel.debug.build.code_debug=4
 frogboard.menu.DebugLevel.verbose=Verbose
 frogboard.menu.DebugLevel.verbose.build.code_debug=5
 
+frogboard.menu.EraseFlash.none=Disabled
+frogboard.menu.EraseFlash.none.upload.erase_cmd=
+frogboard.menu.EraseFlash.all=Enabled
+frogboard.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 esp32cam.name=AI Thinker ESP32-CAM
 
+esp32cam.bootloader.tool=esptool_py
+esp32cam.bootloader.tool.default=esptool_py
+
 esp32cam.upload.tool=esptool_py
+esp32cam.upload.tool.default=esptool_py
+esp32cam.upload.tool.network=esp_ota
+
 esp32cam.upload.maximum_size=3145728
 esp32cam.upload.maximum_data_size=327680
-esp32cam.upload.wait_for_upload_port=true
+esp32cam.upload.flags=
+esp32cam.upload.extra_flags=
 esp32cam.upload.speed=460800
 
 esp32cam.serial.disableDTR=true
 esp32cam.serial.disableRTS=true
 
+esp32cam.build.tarch=xtensa
+esp32cam.build.bootloader_addr=0x1000
+esp32cam.build.target=esp32
 esp32cam.build.mcu=esp32
 esp32cam.build.core=esp32
 esp32cam.build.variant=esp32
 esp32cam.build.board=ESP32_DEV
 esp32cam.build.flash_size=4MB
 esp32cam.build.partitions=huge_app
-esp32cam.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+esp32cam.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+esp32cam.build.extra_libs=
 esp32cam.build.code_debug=0
 
 esp32cam.menu.CPUFreq.240=240MHz (WiFi/BT)
@@ -4460,101 +29351,78 @@ esp32cam.menu.FlashMode.qio.build.boot=qio
 esp32cam.menu.FlashMode.dio=DIO
 esp32cam.menu.FlashMode.dio.build.flash_mode=dio
 esp32cam.menu.FlashMode.dio.build.boot=dio
-esp32cam.menu.FlashMode.qout=QOUT
-esp32cam.menu.FlashMode.qout.build.flash_mode=dout
-esp32cam.menu.FlashMode.qout.build.boot=qout
-esp32cam.menu.FlashMode.dout=DOUT
-esp32cam.menu.FlashMode.dout.build.flash_mode=dout
-esp32cam.menu.FlashMode.dout.build.boot=dout
+
+esp32cam.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32cam.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32cam.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32cam.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32cam.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32cam.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32cam.menu.PartitionScheme.default=Regular 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32cam.menu.PartitionScheme.default.build.partitions=default
+esp32cam.menu.PartitionScheme.defaultffat=Regular 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32cam.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32cam.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32cam.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32cam.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32cam.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32cam.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32cam.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32cam.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32cam.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32cam.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32cam.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32cam.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32cam.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32cam.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32cam.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
 
 esp32cam.menu.FlashFreq.80=80MHz
 esp32cam.menu.FlashFreq.80.build.flash_freq=80m
 esp32cam.menu.FlashFreq.40=40MHz
 esp32cam.menu.FlashFreq.40.build.flash_freq=40m
 
-##############################################################
-
-sparkfun_lora_gateway_1-channel.name=SparkFun LoRa Gateway 1-Channel
-
-sparkfun_lora_gateway_1-channel.upload.tool=esptool_py
-sparkfun_lora_gateway_1-channel.upload.maximum_size=1310720
-sparkfun_lora_gateway_1-channel.upload.maximum_data_size=294912
-sparkfun_lora_gateway_1-channel.upload.wait_for_upload_port=true
-
-sparkfun_lora_gateway_1-channel.serial.disableDTR=true
-sparkfun_lora_gateway_1-channel.serial.disableRTS=true
-
-sparkfun_lora_gateway_1-channel.build.mcu=esp32
-sparkfun_lora_gateway_1-channel.build.core=esp32
-sparkfun_lora_gateway_1-channel.build.variant=sparkfun_lora_gateway_1-channel
-sparkfun_lora_gateway_1-channel.build.board=ESP32_DEV
-
-sparkfun_lora_gateway_1-channel.build.f_cpu=240000000L
-sparkfun_lora_gateway_1-channel.build.flash_size=4MB
-sparkfun_lora_gateway_1-channel.build.flash_freq=40m
-sparkfun_lora_gateway_1-channel.build.flash_mode=dio
-sparkfun_lora_gateway_1-channel.build.boot=dio
-sparkfun_lora_gateway_1-channel.build.partitions=default
-
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.default=Default
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.default.build.partitions=default
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.minimal=Minimal (2MB FLASH)
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.minimal.build.partitions=minimal
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.no_ota=No OTA (Large APP)
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.no_ota.build.partitions=no_ota
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
-sparkfun_lora_gateway_1-channel.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-
-sparkfun_lora_gateway_1-channel.menu.FlashMode.qio=QIO
-sparkfun_lora_gateway_1-channel.menu.FlashMode.qio.build.flash_mode=dio
-sparkfun_lora_gateway_1-channel.menu.FlashMode.qio.build.boot=qio
-sparkfun_lora_gateway_1-channel.menu.FlashMode.dio=DIO
-sparkfun_lora_gateway_1-channel.menu.FlashMode.dio.build.flash_mode=dio
-sparkfun_lora_gateway_1-channel.menu.FlashMode.dio.build.boot=dio
-sparkfun_lora_gateway_1-channel.menu.FlashMode.qout=QOUT
-sparkfun_lora_gateway_1-channel.menu.FlashMode.qout.build.flash_mode=dout
-sparkfun_lora_gateway_1-channel.menu.FlashMode.qout.build.boot=qout
-sparkfun_lora_gateway_1-channel.menu.FlashMode.dout=DOUT
-sparkfun_lora_gateway_1-channel.menu.FlashMode.dout.build.flash_mode=dout
-sparkfun_lora_gateway_1-channel.menu.FlashMode.dout.build.boot=dout
-
-sparkfun_lora_gateway_1-channel.menu.FlashFreq.80=80MHz
-sparkfun_lora_gateway_1-channel.menu.FlashFreq.80.build.flash_freq=80m
-sparkfun_lora_gateway_1-channel.menu.FlashFreq.40=40MHz
-sparkfun_lora_gateway_1-channel.menu.FlashFreq.40.build.flash_freq=40m
-
-sparkfun_lora_gateway_1-channel.menu.FlashSize.4M=4MB (32Mb)
-sparkfun_lora_gateway_1-channel.menu.FlashSize.4M.build.flash_size=4MB
-
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.921600=921600
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.921600.upload.speed=921600
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.115200=115200
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.115200.upload.speed=115200
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.256000.windows=256000
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.256000.upload.speed=256000
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.230400.windows.upload.speed=256000
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.230400=230400
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.230400.upload.speed=230400
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.460800.linux=460800
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.460800.macosx=460800
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.460800.upload.speed=460800
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.512000.windows=512000
-sparkfun_lora_gateway_1-channel.menu.UploadSpeed.512000.upload.speed=512000
+esp32cam.menu.DebugLevel.none=None
+esp32cam.menu.DebugLevel.none.build.code_debug=0
+esp32cam.menu.DebugLevel.error=Error
+esp32cam.menu.DebugLevel.error.build.code_debug=1
+esp32cam.menu.DebugLevel.warn=Warn
+esp32cam.menu.DebugLevel.warn.build.code_debug=2
+esp32cam.menu.DebugLevel.info=Info
+esp32cam.menu.DebugLevel.info.build.code_debug=3
+esp32cam.menu.DebugLevel.debug=Debug
+esp32cam.menu.DebugLevel.debug.build.code_debug=4
+esp32cam.menu.DebugLevel.verbose=Verbose
+esp32cam.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32cam.menu.EraseFlash.none=Disabled
+esp32cam.menu.EraseFlash.none.upload.erase_cmd=
+esp32cam.menu.EraseFlash.all=Enabled
+esp32cam.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
 
 twatch.name=TTGO T-Watch
 
+twatch.bootloader.tool=esptool_py
+twatch.bootloader.tool.default=esptool_py
+
 twatch.upload.tool=esptool_py
+twatch.upload.tool.default=esptool_py
+twatch.upload.tool.network=esp_ota
+
 twatch.upload.maximum_size=6553600
 twatch.upload.maximum_data_size=4521984
 twatch.upload.wait_for_upload_port=true
+twatch.upload.flags=
+twatch.upload.extra_flags=
 
 twatch.serial.disableDTR=true
 twatch.serial.disableRTS=true
 
+twatch.build.tarch=xtensa
+twatch.build.bootloader_addr=0x1000
+twatch.build.target=esp32
 twatch.build.mcu=esp32
 twatch.build.core=esp32
 twatch.build.variant=twatch
@@ -4566,6 +29434,8 @@ twatch.menu.Revision.TWATCH_2020_V1=T-Watch-2020-V1
 twatch.menu.Revision.TWATCH_2020_V1.build.board=TWATCH_2020_V1
 twatch.menu.Revision.TWATCH_2020_V2=T-Watch-2020-V2
 twatch.menu.Revision.TWATCH_2020_V2.build.board=TWATCH_2020_V2
+twatch.menu.Revision.TWATCH_2020_V3=T-Watch-2020-V3
+twatch.menu.Revision.TWATCH_2020_V3.build.board=TWATCH_2020_V3
 
 twatch.build.f_cpu=240000000L
 twatch.build.flash_size=16MB
@@ -4576,9 +29446,11 @@ twatch.build.partitions=default_16MB
 twatch.build.defines=
 
 twatch.menu.PSRAM.enabled=Enabled
-twatch.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+twatch.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+twatch.menu.PSRAM.enabled.build.extra_libs=
 twatch.menu.PSRAM.disabled=Disabled
 twatch.menu.PSRAM.disabled.build.defines=
+twatch.menu.PSRAM.disabled.build.extra_libs=
 
 twatch.menu.PartitionScheme.default=Default (2 x 6.5 MB app, 3.6 MB SPIFFS)
 twatch.menu.PartitionScheme.default.build.partitions=default_16MB
@@ -4619,18 +29491,33 @@ twatch.menu.DebugLevel.debug.build.code_debug=4
 twatch.menu.DebugLevel.verbose=Verbose
 twatch.menu.DebugLevel.verbose.build.code_debug=5
 
+twatch.menu.EraseFlash.none=Disabled
+twatch.menu.EraseFlash.none.upload.erase_cmd=
+twatch.menu.EraseFlash.all=Enabled
+twatch.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 d1_mini32.name=WEMOS D1 MINI ESP32
 
+d1_mini32.bootloader.tool=esptool_py
+d1_mini32.bootloader.tool.default=esptool_py
+
 d1_mini32.upload.tool=esptool_py
+d1_mini32.upload.tool.default=esptool_py
+d1_mini32.upload.tool.network=esp_ota
+
 d1_mini32.upload.maximum_size=1310720
 d1_mini32.upload.maximum_data_size=327680
-d1_mini32.upload.wait_for_upload_port=true
+d1_mini32.upload.flags=
+d1_mini32.upload.extra_flags=
 
 d1_mini32.serial.disableDTR=true
 d1_mini32.serial.disableRTS=true
 
+d1_mini32.build.tarch=xtensa
+d1_mini32.build.bootloader_addr=0x1000
+d1_mini32.build.target=esp32
 d1_mini32.build.mcu=esp32
 d1_mini32.build.core=esp32
 d1_mini32.build.variant=d1_mini32
@@ -4689,18 +29576,144 @@ d1_mini32.menu.UploadSpeed.460800.upload.speed=460800
 d1_mini32.menu.UploadSpeed.512000.windows=512000
 d1_mini32.menu.UploadSpeed.512000.upload.speed=512000
 
+d1_mini32.menu.DebugLevel.none=None
+d1_mini32.menu.DebugLevel.none.build.code_debug=0
+d1_mini32.menu.DebugLevel.error=Error
+d1_mini32.menu.DebugLevel.error.build.code_debug=1
+d1_mini32.menu.DebugLevel.warn=Warn
+d1_mini32.menu.DebugLevel.warn.build.code_debug=2
+d1_mini32.menu.DebugLevel.info=Info
+d1_mini32.menu.DebugLevel.info.build.code_debug=3
+d1_mini32.menu.DebugLevel.debug=Debug
+d1_mini32.menu.DebugLevel.debug.build.code_debug=4
+d1_mini32.menu.DebugLevel.verbose=Verbose
+d1_mini32.menu.DebugLevel.verbose.build.code_debug=5
+
+d1_mini32.menu.EraseFlash.none=Disabled
+d1_mini32.menu.EraseFlash.none.upload.erase_cmd=
+d1_mini32.menu.EraseFlash.all=Enabled
+d1_mini32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+d1_uno32.name=WEMOS D1 R32
+
+d1_uno32.bootloader.tool=esptool_py
+d1_uno32.bootloader.tool.default=esptool_py
+
+d1_uno32.upload.tool=esptool_py
+d1_uno32.upload.tool.default=esptool_py
+d1_uno32.upload.tool.network=esp_ota
+
+d1_uno32.upload.maximum_size=1310720
+d1_uno32.upload.maximum_data_size=327680
+d1_uno32.upload.flags=
+d1_uno32.upload.extra_flags=
+
+d1_uno32.serial.disableDTR=true
+d1_uno32.serial.disableRTS=true
+
+d1_uno32.build.tarch=xtensa
+d1_uno32.build.bootloader_addr=0x1000
+d1_uno32.build.target=esp32
+d1_uno32.build.mcu=esp32
+d1_uno32.build.core=esp32
+d1_uno32.build.variant=d1_uno32
+d1_uno32.build.board=D1_UNO32
+
+d1_uno32.build.f_cpu=240000000L
+d1_uno32.build.flash_mode=dio
+d1_uno32.build.flash_size=4MB
+d1_uno32.build.boot=dio
+d1_uno32.build.partitions=default
+d1_uno32.build.defines=
+
+d1_uno32.menu.FlashFreq.80=80MHz
+d1_uno32.menu.FlashFreq.80.build.flash_freq=80m
+d1_uno32.menu.FlashFreq.40=40MHz
+d1_uno32.menu.FlashFreq.40.build.flash_freq=40m
+
+d1_uno32.menu.PartitionScheme.default=Default
+d1_uno32.menu.PartitionScheme.default.build.partitions=default
+d1_uno32.menu.PartitionScheme.no_ota=No OTA (Large APP)
+d1_uno32.menu.PartitionScheme.no_ota.build.partitions=no_ota
+d1_uno32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+d1_uno32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+d1_uno32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+d1_uno32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+d1_uno32.menu.CPUFreq.240=240MHz (WiFi/BT)
+d1_uno32.menu.CPUFreq.240.build.f_cpu=240000000L
+d1_uno32.menu.CPUFreq.160=160MHz (WiFi/BT)
+d1_uno32.menu.CPUFreq.160.build.f_cpu=160000000L
+d1_uno32.menu.CPUFreq.80=80MHz (WiFi/BT)
+d1_uno32.menu.CPUFreq.80.build.f_cpu=80000000L
+d1_uno32.menu.CPUFreq.40=40MHz (40MHz XTAL)
+d1_uno32.menu.CPUFreq.40.build.f_cpu=40000000L
+d1_uno32.menu.CPUFreq.26=26MHz (26MHz XTAL)
+d1_uno32.menu.CPUFreq.26.build.f_cpu=26000000L
+d1_uno32.menu.CPUFreq.20=20MHz (40MHz XTAL)
+d1_uno32.menu.CPUFreq.20.build.f_cpu=20000000L
+d1_uno32.menu.CPUFreq.13=13MHz (26MHz XTAL)
+d1_uno32.menu.CPUFreq.13.build.f_cpu=13000000L
+d1_uno32.menu.CPUFreq.10=10MHz (40MHz XTAL)
+d1_uno32.menu.CPUFreq.10.build.f_cpu=10000000L
+
+d1_uno32.menu.UploadSpeed.921600=921600
+d1_uno32.menu.UploadSpeed.921600.upload.speed=921600
+d1_uno32.menu.UploadSpeed.115200=115200
+d1_uno32.menu.UploadSpeed.115200.upload.speed=115200
+d1_uno32.menu.UploadSpeed.256000.windows=256000
+d1_uno32.menu.UploadSpeed.256000.upload.speed=256000
+d1_uno32.menu.UploadSpeed.230400.windows.upload.speed=256000
+d1_uno32.menu.UploadSpeed.230400=230400
+d1_uno32.menu.UploadSpeed.230400.upload.speed=230400
+d1_uno32.menu.UploadSpeed.460800.linux=460800
+d1_uno32.menu.UploadSpeed.460800.macosx=460800
+d1_uno32.menu.UploadSpeed.460800.upload.speed=460800
+d1_uno32.menu.UploadSpeed.512000.windows=512000
+d1_uno32.menu.UploadSpeed.512000.upload.speed=512000
+
+d1_uno32.menu.DebugLevel.none=None
+d1_uno32.menu.DebugLevel.none.build.code_debug=0
+d1_uno32.menu.DebugLevel.error=Error
+d1_uno32.menu.DebugLevel.error.build.code_debug=1
+d1_uno32.menu.DebugLevel.warn=Warn
+d1_uno32.menu.DebugLevel.warn.build.code_debug=2
+d1_uno32.menu.DebugLevel.info=Info
+d1_uno32.menu.DebugLevel.info.build.code_debug=3
+d1_uno32.menu.DebugLevel.debug=Debug
+d1_uno32.menu.DebugLevel.debug.build.code_debug=4
+d1_uno32.menu.DebugLevel.verbose=Verbose
+d1_uno32.menu.DebugLevel.verbose.build.code_debug=5
+
+d1_uno32.menu.EraseFlash.none=Disabled
+d1_uno32.menu.EraseFlash.none.upload.erase_cmd=
+d1_uno32.menu.EraseFlash.all=Enabled
+d1_uno32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 gpy.name=Pycom GPy
 
+gpy.bootloader.tool=esptool_py
+gpy.bootloader.tool.default=esptool_py
+
 gpy.upload.tool=esptool_py
+gpy.upload.tool.default=esptool_py
+gpy.upload.tool.network=esp_ota
+
 gpy.upload.maximum_size=1310720
 gpy.upload.maximum_data_size=327680
-gpy.upload.wait_for_upload_port=true
+gpy.upload.flags=
+gpy.upload.extra_flags=
 
 gpy.serial.disableDTR=true
 gpy.serial.disableRTS=true
 
+gpy.build.tarch=xtensa
+gpy.build.bootloader_addr=0x1000
+gpy.build.target=esp32
 gpy.build.mcu=esp32
 gpy.build.core=esp32
 gpy.build.variant=gpy
@@ -4745,18 +29758,33 @@ gpy.menu.DebugLevel.debug.build.code_debug=4
 gpy.menu.DebugLevel.verbose=Verbose
 gpy.menu.DebugLevel.verbose.build.code_debug=5
 
+gpy.menu.EraseFlash.none=Disabled
+gpy.menu.EraseFlash.none.upload.erase_cmd=
+gpy.menu.EraseFlash.all=Enabled
+gpy.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 vintlabs-devkit-v1.name=VintLabs ESP32 Devkit
 
+vintlabs-devkit-v1.bootloader.tool=esptool_py
+vintlabs-devkit-v1.bootloader.tool.default=esptool_py
+
 vintlabs-devkit-v1.upload.tool=esptool_py
+vintlabs-devkit-v1.upload.tool.default=esptool_py
+vintlabs-devkit-v1.upload.tool.network=esp_ota
+
 vintlabs-devkit-v1.upload.maximum_size=1310720
 vintlabs-devkit-v1.upload.maximum_data_size=327680
-vintlabs-devkit-v1.upload.wait_for_upload_port=true
+vintlabs-devkit-v1.upload.flags=
+vintlabs-devkit-v1.upload.extra_flags=
 
 vintlabs-devkit-v1.serial.disableDTR=true
 vintlabs-devkit-v1.serial.disableRTS=true
 
+vintlabs-devkit-v1.build.tarch=xtensa
+vintlabs-devkit-v1.build.bootloader_addr=0x1000
+vintlabs-devkit-v1.build.target=esp32
 vintlabs-devkit-v1.build.mcu=esp32
 vintlabs-devkit-v1.build.core=esp32
 vintlabs-devkit-v1.build.variant=vintlabsdevkitv1
@@ -4795,7 +29823,7 @@ vintlabs-devkit-v1.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB A
 vintlabs-devkit-v1.menu.PartitionScheme.default.build.partitions=default
 vintlabs-devkit-v1.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
 vintlabs-devkit-v1.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
-vintlabs-devkit-v1.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+vintlabs-devkit-v1.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
 vintlabs-devkit-v1.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
 vintlabs-devkit-v1.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
 vintlabs-devkit-v1.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
@@ -4818,10 +29846,10 @@ vintlabs-devkit-v1.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
 vintlabs-devkit-v1.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
 vintlabs-devkit-v1.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 vintlabs-devkit-v1.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-vintlabs-devkit-v1.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+vintlabs-devkit-v1.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
 vintlabs-devkit-v1.menu.PartitionScheme.fatflash.build.partitions=ffat
 vintlabs-devkit-v1.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
-vintlabs-devkit-v1.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+vintlabs-devkit-v1.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
 vintlabs-devkit-v1.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
 vintlabs-devkit-v1.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
 
@@ -4829,10 +29857,8 @@ vintlabs-devkit-v1.menu.FlashSize.4M=4MB (32Mb)
 vintlabs-devkit-v1.menu.FlashSize.4M.build.flash_size=4MB
 vintlabs-devkit-v1.menu.FlashSize.8M=8MB (64Mb)
 vintlabs-devkit-v1.menu.FlashSize.8M.build.flash_size=8MB
-vintlabs-devkit-v1.menu.FlashSize.8M.build.partitions=default_8MB
 vintlabs-devkit-v1.menu.FlashSize.2M=2MB (16Mb)
 vintlabs-devkit-v1.menu.FlashSize.2M.build.flash_size=2MB
-vintlabs-devkit-v1.menu.FlashSize.2M.build.partitions=minimal
 vintlabs-devkit-v1.menu.FlashSize.16M=16MB (128Mb)
 vintlabs-devkit-v1.menu.FlashSize.16M.build.flash_size=16MB
 
@@ -4847,18 +29873,33 @@ vintlabs-devkit-v1.menu.DebugLevel.info.build.code_debug=3
 vintlabs-devkit-v1.menu.DebugLevel.debug=Debug
 vintlabs-devkit-v1.menu.DebugLevel.debug.build.code_debug=4
 
+vintlabs-devkit-v1.menu.EraseFlash.none=Disabled
+vintlabs-devkit-v1.menu.EraseFlash.none.upload.erase_cmd=
+vintlabs-devkit-v1.menu.EraseFlash.all=Enabled
+vintlabs-devkit-v1.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 honeylemon.name=HONEYLemon
 
+honeylemon.bootloader.tool=esptool_py
+honeylemon.bootloader.tool.default=esptool_py
+
 honeylemon.upload.tool=esptool_py
+honeylemon.upload.tool.default=esptool_py
+honeylemon.upload.tool.network=esp_ota
+
 honeylemon.upload.maximum_size=1310720
 honeylemon.upload.maximum_data_size=327680
-honeylemon.upload.wait_for_upload_port=true
+honeylemon.upload.flags=
+honeylemon.upload.extra_flags=
 
 honeylemon.serial.disableDTR=true
 honeylemon.serial.disableRTS=true
 
+honeylemon.build.tarch=xtensa
+honeylemon.build.bootloader_addr=0x1000
+honeylemon.build.target=esp32
 honeylemon.build.mcu=esp32
 honeylemon.build.core=esp32
 honeylemon.build.variant=honeylemon
@@ -4891,18 +29932,46 @@ honeylemon.menu.UploadSpeed.460800.upload.speed=460800
 honeylemon.menu.UploadSpeed.512000.windows=512000
 honeylemon.menu.UploadSpeed.512000.upload.speed=512000
 
+honeylemon.menu.DebugLevel.none=None
+honeylemon.menu.DebugLevel.none.build.code_debug=0
+honeylemon.menu.DebugLevel.error=Error
+honeylemon.menu.DebugLevel.error.build.code_debug=1
+honeylemon.menu.DebugLevel.warn=Warn
+honeylemon.menu.DebugLevel.warn.build.code_debug=2
+honeylemon.menu.DebugLevel.info=Info
+honeylemon.menu.DebugLevel.info.build.code_debug=3
+honeylemon.menu.DebugLevel.debug=Debug
+honeylemon.menu.DebugLevel.debug.build.code_debug=4
+honeylemon.menu.DebugLevel.verbose=Verbose
+honeylemon.menu.DebugLevel.verbose.build.code_debug=5
+
+honeylemon.menu.EraseFlash.none=Disabled
+honeylemon.menu.EraseFlash.none.upload.erase_cmd=
+honeylemon.menu.EraseFlash.all=Enabled
+honeylemon.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 mgbot-iotik32a.name=MGBOT IOTIK 32A
 
+mgbot-iotik32a.bootloader.tool=esptool_py
+mgbot-iotik32a.bootloader.tool.default=esptool_py
+
 mgbot-iotik32a.upload.tool=esptool_py
+mgbot-iotik32a.upload.tool.default=esptool_py
+mgbot-iotik32a.upload.tool.network=esp_ota
+
 mgbot-iotik32a.upload.maximum_size=1310720
 mgbot-iotik32a.upload.maximum_data_size=327680
-mgbot-iotik32a.upload.wait_for_upload_port=true
+mgbot-iotik32a.upload.flags=
+mgbot-iotik32a.upload.extra_flags=
 
 mgbot-iotik32a.serial.disableDTR=true
 mgbot-iotik32a.serial.disableRTS=true
 
+mgbot-iotik32a.build.tarch=xtensa
+mgbot-iotik32a.build.bootloader_addr=0x1000
+mgbot-iotik32a.build.target=esp32
 mgbot-iotik32a.build.mcu=esp32
 mgbot-iotik32a.build.core=esp32
 mgbot-iotik32a.build.variant=mgbot-iotik32a
@@ -4918,14 +29987,16 @@ mgbot-iotik32a.build.defines=
 
 mgbot-iotik32a.menu.PSRAM.disabled=Disabled
 mgbot-iotik32a.menu.PSRAM.disabled.build.defines=
+mgbot-iotik32a.menu.PSRAM.disabled.build.extra_libs=
 mgbot-iotik32a.menu.PSRAM.enabled=Enabled
-mgbot-iotik32a.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+mgbot-iotik32a.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+mgbot-iotik32a.menu.PSRAM.enabled.build.extra_libs=
 
 mgbot-iotik32a.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
 mgbot-iotik32a.menu.PartitionScheme.default.build.partitions=default
 mgbot-iotik32a.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
 mgbot-iotik32a.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
-mgbot-iotik32a.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+mgbot-iotik32a.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
 mgbot-iotik32a.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
 mgbot-iotik32a.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
 mgbot-iotik32a.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
@@ -4948,10 +30019,10 @@ mgbot-iotik32a.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
 mgbot-iotik32a.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
 mgbot-iotik32a.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 mgbot-iotik32a.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-mgbot-iotik32a.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+mgbot-iotik32a.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
 mgbot-iotik32a.menu.PartitionScheme.fatflash.build.partitions=ffat
 mgbot-iotik32a.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
-mgbot-iotik32a.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+mgbot-iotik32a.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
 mgbot-iotik32a.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
 mgbot-iotik32a.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
 
@@ -4978,12 +30049,6 @@ mgbot-iotik32a.menu.FlashMode.qio.build.boot=qio
 mgbot-iotik32a.menu.FlashMode.dio=DIO
 mgbot-iotik32a.menu.FlashMode.dio.build.flash_mode=dio
 mgbot-iotik32a.menu.FlashMode.dio.build.boot=dio
-mgbot-iotik32a.menu.FlashMode.qout=QOUT
-mgbot-iotik32a.menu.FlashMode.qout.build.flash_mode=dout
-mgbot-iotik32a.menu.FlashMode.qout.build.boot=qout
-mgbot-iotik32a.menu.FlashMode.dout=DOUT
-mgbot-iotik32a.menu.FlashMode.dout.build.flash_mode=dout
-mgbot-iotik32a.menu.FlashMode.dout.build.boot=dout
 
 mgbot-iotik32a.menu.FlashFreq.80=80MHz
 mgbot-iotik32a.menu.FlashFreq.80.build.flash_freq=80m
@@ -4994,10 +30059,8 @@ mgbot-iotik32a.menu.FlashSize.4M=4MB (32Mb)
 mgbot-iotik32a.menu.FlashSize.4M.build.flash_size=4MB
 mgbot-iotik32a.menu.FlashSize.8M=8MB (64Mb)
 mgbot-iotik32a.menu.FlashSize.8M.build.flash_size=8MB
-mgbot-iotik32a.menu.FlashSize.8M.build.partitions=default_8MB
 mgbot-iotik32a.menu.FlashSize.2M=2MB (16Mb)
 mgbot-iotik32a.menu.FlashSize.2M.build.flash_size=2MB
-mgbot-iotik32a.menu.FlashSize.2M.build.partitions=minimal
 mgbot-iotik32a.menu.FlashSize.16M=16MB (128Mb)
 mgbot-iotik32a.menu.FlashSize.16M.build.flash_size=16MB
 
@@ -5029,18 +30092,33 @@ mgbot-iotik32a.menu.DebugLevel.debug.build.code_debug=4
 mgbot-iotik32a.menu.DebugLevel.verbose=Verbose
 mgbot-iotik32a.menu.DebugLevel.verbose.build.code_debug=5
 
+mgbot-iotik32a.menu.EraseFlash.none=Disabled
+mgbot-iotik32a.menu.EraseFlash.none.upload.erase_cmd=
+mgbot-iotik32a.menu.EraseFlash.all=Enabled
+mgbot-iotik32a.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 mgbot-iotik32b.name=MGBOT IOTIK 32B
 
+mgbot-iotik32b.bootloader.tool=esptool_py
+mgbot-iotik32b.bootloader.tool.default=esptool_py
+
 mgbot-iotik32b.upload.tool=esptool_py
+mgbot-iotik32b.upload.tool.default=esptool_py
+mgbot-iotik32b.upload.tool.network=esp_ota
+
 mgbot-iotik32b.upload.maximum_size=1310720
 mgbot-iotik32b.upload.maximum_data_size=327680
-mgbot-iotik32b.upload.wait_for_upload_port=true
+mgbot-iotik32b.upload.flags=
+mgbot-iotik32b.upload.extra_flags=
 
 mgbot-iotik32b.serial.disableDTR=true
 mgbot-iotik32b.serial.disableRTS=true
 
+mgbot-iotik32b.build.tarch=xtensa
+mgbot-iotik32b.build.bootloader_addr=0x1000
+mgbot-iotik32b.build.target=esp32
 mgbot-iotik32b.build.mcu=esp32
 mgbot-iotik32b.build.core=esp32
 mgbot-iotik32b.build.variant=mgbot-iotik32b
@@ -5056,14 +30134,16 @@ mgbot-iotik32b.build.defines=
 
 mgbot-iotik32b.menu.PSRAM.disabled=Disabled
 mgbot-iotik32b.menu.PSRAM.disabled.build.defines=
+mgbot-iotik32b.menu.PSRAM.disabled.build.extra_libs=
 mgbot-iotik32b.menu.PSRAM.enabled=Enabled
-mgbot-iotik32b.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+mgbot-iotik32b.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+mgbot-iotik32b.menu.PSRAM.enabled.build.extra_libs=
 
 mgbot-iotik32b.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
 mgbot-iotik32b.menu.PartitionScheme.default.build.partitions=default
 mgbot-iotik32b.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
 mgbot-iotik32b.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
-mgbot-iotik32b.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+mgbot-iotik32b.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
 mgbot-iotik32b.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
 mgbot-iotik32b.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
 mgbot-iotik32b.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
@@ -5086,10 +30166,10 @@ mgbot-iotik32b.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
 mgbot-iotik32b.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
 mgbot-iotik32b.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 mgbot-iotik32b.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-mgbot-iotik32b.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+mgbot-iotik32b.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
 mgbot-iotik32b.menu.PartitionScheme.fatflash.build.partitions=ffat
 mgbot-iotik32b.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
-mgbot-iotik32b.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+mgbot-iotik32b.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
 mgbot-iotik32b.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
 mgbot-iotik32b.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
 
@@ -5116,12 +30196,6 @@ mgbot-iotik32b.menu.FlashMode.qio.build.boot=qio
 mgbot-iotik32b.menu.FlashMode.dio=DIO
 mgbot-iotik32b.menu.FlashMode.dio.build.flash_mode=dio
 mgbot-iotik32b.menu.FlashMode.dio.build.boot=dio
-mgbot-iotik32b.menu.FlashMode.qout=QOUT
-mgbot-iotik32b.menu.FlashMode.qout.build.flash_mode=dout
-mgbot-iotik32b.menu.FlashMode.qout.build.boot=qout
-mgbot-iotik32b.menu.FlashMode.dout=DOUT
-mgbot-iotik32b.menu.FlashMode.dout.build.flash_mode=dout
-mgbot-iotik32b.menu.FlashMode.dout.build.boot=dout
 
 mgbot-iotik32b.menu.FlashFreq.80=80MHz
 mgbot-iotik32b.menu.FlashFreq.80.build.flash_freq=80m
@@ -5132,10 +30206,8 @@ mgbot-iotik32b.menu.FlashSize.4M=4MB (32Mb)
 mgbot-iotik32b.menu.FlashSize.4M.build.flash_size=4MB
 mgbot-iotik32b.menu.FlashSize.8M=8MB (64Mb)
 mgbot-iotik32b.menu.FlashSize.8M.build.flash_size=8MB
-mgbot-iotik32b.menu.FlashSize.8M.build.partitions=default_8MB
 mgbot-iotik32b.menu.FlashSize.2M=2MB (16Mb)
 mgbot-iotik32b.menu.FlashSize.2M.build.flash_size=2MB
-mgbot-iotik32b.menu.FlashSize.2M.build.partitions=minimal
 mgbot-iotik32b.menu.FlashSize.16M=16MB (128Mb)
 mgbot-iotik32b.menu.FlashSize.16M.build.flash_size=16MB
 
@@ -5167,17 +30239,33 @@ mgbot-iotik32b.menu.DebugLevel.debug.build.code_debug=4
 mgbot-iotik32b.menu.DebugLevel.verbose=Verbose
 mgbot-iotik32b.menu.DebugLevel.verbose.build.code_debug=5
 
+mgbot-iotik32b.menu.EraseFlash.none=Disabled
+mgbot-iotik32b.menu.EraseFlash.none.upload.erase_cmd=
+mgbot-iotik32b.menu.EraseFlash.all=Enabled
+mgbot-iotik32b.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
+
 piranha_esp-32.name=Piranha ESP-32
 
+piranha_esp-32.bootloader.tool=esptool_py
+piranha_esp-32.bootloader.tool.default=esptool_py
+
 piranha_esp-32.upload.tool=esptool_py
+piranha_esp-32.upload.tool.default=esptool_py
+piranha_esp-32.upload.tool.network=esp_ota
+
 piranha_esp-32.upload.maximum_size=1310720
 piranha_esp-32.upload.maximum_data_size=327680
-piranha_esp-32.upload.wait_for_upload_port=true
+piranha_esp-32.upload.flags=
+piranha_esp-32.upload.extra_flags=
 
 piranha_esp-32.serial.disableDTR=true
 piranha_esp-32.serial.disableRTS=true
 
+piranha_esp-32.build.tarch=xtensa
+piranha_esp-32.build.bootloader_addr=0x1000
+piranha_esp-32.build.target=esp32
 piranha_esp-32.build.mcu=esp32
 piranha_esp-32.build.core=esp32
 piranha_esp-32.build.variant=piranha_esp-32
@@ -5232,18 +30320,33 @@ piranha_esp-32.menu.DebugLevel.debug.build.code_debug=4
 piranha_esp-32.menu.DebugLevel.verbose=Verbose
 piranha_esp-32.menu.DebugLevel.verbose.build.code_debug=5
 
+piranha_esp-32.menu.EraseFlash.none=Disabled
+piranha_esp-32.menu.EraseFlash.none.upload.erase_cmd=
+piranha_esp-32.menu.EraseFlash.all=Enabled
+piranha_esp-32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 metro_esp-32.name=Metro ESP-32
 
+metro_esp-32.bootloader.tool=esptool_py
+metro_esp-32.bootloader.tool.default=esptool_py
+
 metro_esp-32.upload.tool=esptool_py
+metro_esp-32.upload.tool.default=esptool_py
+metro_esp-32.upload.tool.network=esp_ota
+
 metro_esp-32.upload.maximum_size=1310720
 metro_esp-32.upload.maximum_data_size=327680
-metro_esp-32.upload.wait_for_upload_port=true
+metro_esp-32.upload.flags=
+metro_esp-32.upload.extra_flags=
 
 metro_esp-32.serial.disableDTR=true
 metro_esp-32.serial.disableRTS=true
 
+metro_esp-32.build.tarch=xtensa
+metro_esp-32.build.bootloader_addr=0x1000
+metro_esp-32.build.target=esp32
 metro_esp-32.build.mcu=esp32
 metro_esp-32.build.core=esp32
 metro_esp-32.build.variant=metro_esp-32
@@ -5298,17 +30401,33 @@ metro_esp-32.menu.DebugLevel.debug.build.code_debug=4
 metro_esp-32.menu.DebugLevel.verbose=Verbose
 metro_esp-32.menu.DebugLevel.verbose.build.code_debug=5
 
+metro_esp-32.menu.EraseFlash.none=Disabled
+metro_esp-32.menu.EraseFlash.none.upload.erase_cmd=
+metro_esp-32.menu.EraseFlash.all=Enabled
+metro_esp-32.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
+
 sensesiot_weizen.name=Senses's WEIZEN
 
+sensesiot_weizen.bootloader.tool=esptool_py
+sensesiot_weizen.bootloader.tool.default=esptool_py
+
 sensesiot_weizen.upload.tool=esptool_py
+sensesiot_weizen.upload.tool.default=esptool_py
+sensesiot_weizen.upload.tool.network=esp_ota
+
 sensesiot_weizen.upload.maximum_size=1310720
 sensesiot_weizen.upload.maximum_data_size=327680
-sensesiot_weizen.upload.wait_for_upload_port=true
+sensesiot_weizen.upload.flags=
+sensesiot_weizen.upload.extra_flags=
 
 sensesiot_weizen.serial.disableDTR=true
 sensesiot_weizen.serial.disableRTS=true
 
+sensesiot_weizen.build.tarch=xtensa
+sensesiot_weizen.build.bootloader_addr=0x1000
+sensesiot_weizen.build.target=esp32
 sensesiot_weizen.build.mcu=esp32
 sensesiot_weizen.build.core=esp32
 sensesiot_weizen.build.variant=esp32
@@ -5341,17 +30460,47 @@ sensesiot_weizen.menu.UploadSpeed.460800.upload.speed=460800
 sensesiot_weizen.menu.UploadSpeed.512000.windows=512000
 sensesiot_weizen.menu.UploadSpeed.512000.upload.speed=512000
 
+sensesiot_weizen.menu.DebugLevel.none=None
+sensesiot_weizen.menu.DebugLevel.none.build.code_debug=0
+sensesiot_weizen.menu.DebugLevel.error=Error
+sensesiot_weizen.menu.DebugLevel.error.build.code_debug=1
+sensesiot_weizen.menu.DebugLevel.warn=Warn
+sensesiot_weizen.menu.DebugLevel.warn.build.code_debug=2
+sensesiot_weizen.menu.DebugLevel.info=Info
+sensesiot_weizen.menu.DebugLevel.info.build.code_debug=3
+sensesiot_weizen.menu.DebugLevel.debug=Debug
+sensesiot_weizen.menu.DebugLevel.debug.build.code_debug=4
+sensesiot_weizen.menu.DebugLevel.verbose=Verbose
+sensesiot_weizen.menu.DebugLevel.verbose.build.code_debug=5
+
+sensesiot_weizen.menu.EraseFlash.none=Disabled
+sensesiot_weizen.menu.EraseFlash.none.upload.erase_cmd=
+sensesiot_weizen.menu.EraseFlash.all=Enabled
+sensesiot_weizen.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
+
 kits-edu.name=KITS ESP32 EDU
 
+kits-edu.bootloader.tool=esptool_py
+kits-edu.bootloader.tool.default=esptool_py
+
 kits-edu.upload.tool=esptool_py
+kits-edu.upload.tool.default=esptool_py
+kits-edu.upload.tool.network=esp_ota
+
 kits-edu.upload.maximum_size=1310720
 kits-edu.upload.maximum_data_size=327680
 kits-edu.upload.wait_for_upload_port=true
+kits-edu.upload.flags=
+kits-edu.upload.extra_flags=
 
 kits-edu.serial.disableDTR=true
 kits-edu.serial.disableRTS=true
 
+kits-edu.build.tarch=xtensa
+kits-edu.build.bootloader_addr=0x1000
+kits-edu.build.target=esp32
 kits-edu.build.mcu=esp32
 kits-edu.build.core=esp32
 kits-edu.build.variant=pico32
@@ -5402,17 +30551,32 @@ kits-edu.menu.DebugLevel.debug.build.code_debug=4
 kits-edu.menu.DebugLevel.verbose=Verbose
 kits-edu.menu.DebugLevel.verbose.build.code_debug=5
 
+kits-edu.menu.EraseFlash.none=Disabled
+kits-edu.menu.EraseFlash.none.upload.erase_cmd=
+kits-edu.menu.EraseFlash.all=Enabled
+kits-edu.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 mPython.name=Labplus mPython
+mPython.bootloader.tool=esptool_py
+mPython.bootloader.tool.default=esptool_py
+
 mPython.upload.tool=esptool_py
+mPython.upload.tool.default=esptool_py
+mPython.upload.tool.network=esp_ota
+
 mPython.upload.maximum_size=1310720
 mPython.upload.maximum_data_size=327680
-mPython.upload.wait_for_upload_port=true
+mPython.upload.flags=
+mPython.upload.extra_flags=
 
 mPython.serial.disableDTR=true
 mPython.serial.disableRTS=true
 
+mPython.build.tarch=xtensa
+mPython.build.bootloader_addr=0x1000
+mPython.build.target=esp32
 mPython.build.mcu=esp32
 mPython.build.core=esp32
 mPython.build.variant=mpython
@@ -5428,8 +30592,10 @@ mPython.build.defines=
 
 mPython.menu.PSRAM.disabled=Disabled
 mPython.menu.PSRAM.disabled.build.defines=
+mPython.menu.PSRAM.disabled.build.extra_libs=
 mPython.menu.PSRAM.enabled=Enabled
-mPython.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue
+mPython.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+mPython.menu.PSRAM.enabled.build.extra_libs=
 
 mPython.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
 mPython.menu.PartitionScheme.huge_app.build.partitions=huge_app
@@ -5455,25 +30621,18 @@ mPython.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
 mPython.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
 mPython.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
 mPython.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
-mPython.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+mPython.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
 mPython.menu.PartitionScheme.fatflash.build.partitions=ffat
 
 mPython.menu.CPUFreq.240=240MHz (WiFi/BT)
 mPython.menu.CPUFreq.240.build.f_cpu=240000000L
 
-
 mPython.menu.FlashMode.qio=QIO
 mPython.menu.FlashMode.qio.build.flash_mode=dio
 mPython.menu.FlashMode.qio.build.boot=qio
 mPython.menu.FlashMode.dio=DIO
 mPython.menu.FlashMode.dio.build.flash_mode=dio
 mPython.menu.FlashMode.dio.build.boot=dio
-mPython.menu.FlashMode.qout=QOUT
-mPython.menu.FlashMode.qout.build.flash_mode=dout
-mPython.menu.FlashMode.qout.build.boot=qout
-mPython.menu.FlashMode.dout=DOUT
-mPython.menu.FlashMode.dout.build.flash_mode=dout
-mPython.menu.FlashMode.dout.build.boot=dout
 
 mPython.menu.FlashFreq.80=80MHz
 mPython.menu.FlashFreq.80.build.flash_freq=80m
@@ -5483,7 +30642,6 @@ mPython.menu.FlashFreq.40.build.flash_freq=40m
 mPython.menu.FlashSize.8M=8MB (64Mb)
 mPython.menu.FlashSize.8M.build.flash_size=8MB
 
-
 mPython.menu.UploadSpeed.921600=921600
 mPython.menu.UploadSpeed.921600.upload.speed=921600
 mPython.menu.UploadSpeed.115200=115200
@@ -5512,18 +30670,34 @@ mPython.menu.DebugLevel.debug.build.code_debug=4
 mPython.menu.DebugLevel.verbose=Verbose
 mPython.menu.DebugLevel.verbose.build.code_debug=5
 
+mPython.menu.EraseFlash.none=Disabled
+mPython.menu.EraseFlash.none.upload.erase_cmd=
+mPython.menu.EraseFlash.all=Enabled
+mPython.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 OpenKB.name=INEX OpenKB
 
+OpenKB.bootloader.tool=esptool_py
+OpenKB.bootloader.tool.default=esptool_py
+
 OpenKB.upload.tool=esptool_py
+OpenKB.upload.tool.default=esptool_py
+OpenKB.upload.tool.network=esp_ota
+
 OpenKB.upload.maximum_size=1310720
 OpenKB.upload.maximum_data_size=327680
 OpenKB.upload.wait_for_upload_port=true
+OpenKB.upload.flags=
+OpenKB.upload.extra_flags=
 
 OpenKB.serial.disableDTR=true
 OpenKB.serial.disableRTS=true
 
+OpenKB.build.tarch=xtensa
+OpenKB.build.bootloader_addr=0x1000
+OpenKB.build.target=esp32
 OpenKB.build.mcu=esp32
 OpenKB.build.core=esp32
 OpenKB.build.variant=openkb
@@ -5556,18 +30730,47 @@ OpenKB.menu.UploadSpeed.460800.upload.speed=460800
 OpenKB.menu.UploadSpeed.512000.windows=512000
 OpenKB.menu.UploadSpeed.512000.upload.speed=512000
 
+OpenKB.menu.DebugLevel.none=None
+OpenKB.menu.DebugLevel.none.build.code_debug=0
+OpenKB.menu.DebugLevel.error=Error
+OpenKB.menu.DebugLevel.error.build.code_debug=1
+OpenKB.menu.DebugLevel.warn=Warn
+OpenKB.menu.DebugLevel.warn.build.code_debug=2
+OpenKB.menu.DebugLevel.info=Info
+OpenKB.menu.DebugLevel.info.build.code_debug=3
+OpenKB.menu.DebugLevel.debug=Debug
+OpenKB.menu.DebugLevel.debug.build.code_debug=4
+OpenKB.menu.DebugLevel.verbose=Verbose
+OpenKB.menu.DebugLevel.verbose.build.code_debug=5
+
+OpenKB.menu.EraseFlash.none=Disabled
+OpenKB.menu.EraseFlash.none.upload.erase_cmd=
+OpenKB.menu.EraseFlash.all=Enabled
+OpenKB.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 wifiduino32.name=WiFiduino32
 
+wifiduino32.bootloader.tool=esptool_py
+wifiduino32.bootloader.tool.default=esptool_py
+
 wifiduino32.upload.tool=esptool_py
+wifiduino32.upload.tool.default=esptool_py
+wifiduino32.upload.tool.network=esp_ota
+
 wifiduino32.upload.maximum_size=1310720
 wifiduino32.upload.maximum_data_size=327680
 wifiduino32.upload.wait_for_upload_port=true
+wifiduino32.upload.flags=
+wifiduino32.upload.extra_flags=
 
 wifiduino32.serial.disableDTR=true
 wifiduino32.serial.disableRTS=true
 
+wifiduino32.build.tarch=xtensa
+wifiduino32.build.bootloader_addr=0x1000
+wifiduino32.build.target=esp32
 wifiduino32.build.mcu=esp32
 wifiduino32.build.core=esp32
 wifiduino32.build.variant=wifiduino32
@@ -5622,126 +30825,397 @@ wifiduino32.menu.DebugLevel.debug.build.code_debug=4
 wifiduino32.menu.DebugLevel.verbose=Verbose
 wifiduino32.menu.DebugLevel.verbose.build.code_debug=5
 
+wifiduino32.menu.EraseFlash.none=Disabled
+wifiduino32.menu.EraseFlash.none.upload.erase_cmd=
+wifiduino32.menu.EraseFlash.all=Enabled
+wifiduino32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+wifiduino32c3.name=WiFiduinoV2
+
+wifiduino32c3.bootloader.tool=esptool_py
+wifiduino32c3.bootloader.tool.default=esptool_py
+
+wifiduino32c3.upload.tool=esptool_py
+wifiduino32c3.upload.tool.default=esptool_py
+wifiduino32c3.upload.tool.network=esp_ota
+
+wifiduino32c3.upload.maximum_size=1310720
+wifiduino32c3.upload.maximum_data_size=327680
+wifiduino32c3.upload.flags=
+wifiduino32c3.upload.extra_flags=
+wifiduino32c3.upload.use_1200bps_touch=false
+wifiduino32c3.upload.wait_for_upload_port=false
+
+wifiduino32c3.serial.disableDTR=false
+wifiduino32c3.serial.disableRTS=false
+
+wifiduino32c3.build.tarch=riscv32
+wifiduino32c3.build.target=esp
+wifiduino32c3.build.mcu=esp32c3
+wifiduino32c3.build.core=esp32
+wifiduino32c3.build.variant=wifiduinov2
+wifiduino32c3.build.board=WiFiduinoV2
+wifiduino32c3.build.bootloader_addr=0x0
+
+wifiduino32c3.build.cdc_on_boot=0
+wifiduino32c3.build.f_cpu=160000000L
+wifiduino32c3.build.flash_size=4MB
+wifiduino32c3.build.flash_freq=80m
+wifiduino32c3.build.flash_mode=qio
+wifiduino32c3.build.boot=qio
+wifiduino32c3.build.partitions=default
+wifiduino32c3.build.defines=
+
+wifiduino32c3.menu.CDCOnBoot.default=Disabled
+wifiduino32c3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+wifiduino32c3.menu.CDCOnBoot.cdc=Enabled
+wifiduino32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+wifiduino32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+wifiduino32c3.menu.PartitionScheme.default.build.partitions=default
+wifiduino32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+wifiduino32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+wifiduino32c3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+wifiduino32c3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+wifiduino32c3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+wifiduino32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+wifiduino32c3.menu.PartitionScheme.minimal.build.partitions=minimal
+wifiduino32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+wifiduino32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+wifiduino32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+wifiduino32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+wifiduino32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+wifiduino32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+wifiduino32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+wifiduino32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+wifiduino32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+wifiduino32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+wifiduino32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+wifiduino32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+wifiduino32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+wifiduino32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+wifiduino32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+wifiduino32c3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+wifiduino32c3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+wifiduino32c3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+wifiduino32c3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+wifiduino32c3.menu.PartitionScheme.fatflash.build.partitions=ffat
+wifiduino32c3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+wifiduino32c3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+wifiduino32c3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+wifiduino32c3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+wifiduino32c3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+wifiduino32c3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+wifiduino32c3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+wifiduino32c3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+wifiduino32c3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+wifiduino32c3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+wifiduino32c3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+wifiduino32c3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+wifiduino32c3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+wifiduino32c3.menu.CPUFreq.160=160MHz (WiFi)
+wifiduino32c3.menu.CPUFreq.160.build.f_cpu=160000000L
+wifiduino32c3.menu.CPUFreq.80=80MHz (WiFi)
+wifiduino32c3.menu.CPUFreq.80.build.f_cpu=80000000L
+wifiduino32c3.menu.CPUFreq.40=40MHz
+wifiduino32c3.menu.CPUFreq.40.build.f_cpu=40000000L
+wifiduino32c3.menu.CPUFreq.20=20MHz
+wifiduino32c3.menu.CPUFreq.20.build.f_cpu=20000000L
+wifiduino32c3.menu.CPUFreq.10=10MHz
+wifiduino32c3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+wifiduino32c3.menu.FlashMode.qio=QIO
+wifiduino32c3.menu.FlashMode.qio.build.flash_mode=dio
+wifiduino32c3.menu.FlashMode.qio.build.boot=qio
+wifiduino32c3.menu.FlashMode.dio=DIO
+wifiduino32c3.menu.FlashMode.dio.build.flash_mode=dio
+wifiduino32c3.menu.FlashMode.dio.build.boot=dio
+
+wifiduino32c3.menu.FlashFreq.80=80MHz
+wifiduino32c3.menu.FlashFreq.80.build.flash_freq=80m
+wifiduino32c3.menu.FlashFreq.40=40MHz
+wifiduino32c3.menu.FlashFreq.40.build.flash_freq=40m
+
+wifiduino32c3.menu.FlashSize.4M=4MB (32Mb)
+wifiduino32c3.menu.FlashSize.4M.build.flash_size=4MB
+wifiduino32c3.menu.FlashSize.8M=8MB (64Mb)
+wifiduino32c3.menu.FlashSize.8M.build.flash_size=8MB
+wifiduino32c3.menu.FlashSize.2M=2MB (16Mb)
+wifiduino32c3.menu.FlashSize.2M.build.flash_size=2MB
+wifiduino32c3.menu.FlashSize.16M=16MB (128Mb)
+wifiduino32c3.menu.FlashSize.16M.build.flash_size=16MB
+
+wifiduino32c3.menu.UploadSpeed.921600=921600
+wifiduino32c3.menu.UploadSpeed.921600.upload.speed=921600
+wifiduino32c3.menu.UploadSpeed.115200=115200
+wifiduino32c3.menu.UploadSpeed.115200.upload.speed=115200
+wifiduino32c3.menu.UploadSpeed.256000.windows=256000
+wifiduino32c3.menu.UploadSpeed.256000.upload.speed=256000
+wifiduino32c3.menu.UploadSpeed.230400.windows.upload.speed=256000
+wifiduino32c3.menu.UploadSpeed.230400=230400
+wifiduino32c3.menu.UploadSpeed.230400.upload.speed=230400
+wifiduino32c3.menu.UploadSpeed.460800.linux=460800
+wifiduino32c3.menu.UploadSpeed.460800.macosx=460800
+wifiduino32c3.menu.UploadSpeed.460800.upload.speed=460800
+wifiduino32c3.menu.UploadSpeed.512000.windows=512000
+wifiduino32c3.menu.UploadSpeed.512000.upload.speed=512000
+
+wifiduino32c3.menu.DebugLevel.none=None
+wifiduino32c3.menu.DebugLevel.none.build.code_debug=0
+wifiduino32c3.menu.DebugLevel.error=Error
+wifiduino32c3.menu.DebugLevel.error.build.code_debug=1
+wifiduino32c3.menu.DebugLevel.warn=Warn
+wifiduino32c3.menu.DebugLevel.warn.build.code_debug=2
+wifiduino32c3.menu.DebugLevel.info=Info
+wifiduino32c3.menu.DebugLevel.info.build.code_debug=3
+wifiduino32c3.menu.DebugLevel.debug=Debug
+wifiduino32c3.menu.DebugLevel.debug.build.code_debug=4
+wifiduino32c3.menu.DebugLevel.verbose=Verbose
+wifiduino32c3.menu.DebugLevel.verbose.build.code_debug=5
+
+wifiduino32c3.menu.EraseFlash.none=Disabled
+wifiduino32c3.menu.EraseFlash.none.upload.erase_cmd=
+wifiduino32c3.menu.EraseFlash.all=Enabled
+wifiduino32c3.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
-ttgo-lora32-v21new.name=TTGO LoRa32-OLED v2.1.6
-
-ttgo-lora32-v21new.upload.tool=esptool_py
-ttgo-lora32-v21new.upload.maximum_size=1310720
-ttgo-lora32-v21new.upload.maximum_data_size=294912
-ttgo-lora32-v21new.upload.wait_for_upload_port=true
-
-ttgo-lora32-v21new.serial.disableDTR=true
-ttgo-lora32-v21new.serial.disableRTS=true
-
-ttgo-lora32-v21new.build.mcu=esp32
-ttgo-lora32-v21new.build.core=esp32
-ttgo-lora32-v21new.build.variant=ttgo-lora32-v21new
-ttgo-lora32-v21new.build.board=TTGO_LoRa32_v21new
-
-ttgo-lora32-v21new.build.f_cpu=240000000L
-ttgo-lora32-v21new.build.flash_mode=dio
-ttgo-lora32-v21new.build.flash_size=4MB
-ttgo-lora32-v21new.build.boot=dio
-ttgo-lora32-v21new.build.partitions=default
-
-ttgo-lora32-v21new.menu.FlashFreq.80=80MHz
-ttgo-lora32-v21new.menu.FlashFreq.80.build.flash_freq=80m
-ttgo-lora32-v21new.menu.FlashFreq.40=40MHz
-ttgo-lora32-v21new.menu.FlashFreq.40.build.flash_freq=40m
-
-ttgo-lora32-v21new.menu.UploadSpeed.921600=921600
-ttgo-lora32-v21new.menu.UploadSpeed.921600.upload.speed=921600
-ttgo-lora32-v21new.menu.UploadSpeed.115200=115200
-ttgo-lora32-v21new.name=TTGO LoRa32-OLED v2.1.6
-
-ttgo-lora32-v21new.upload.tool=esptool_py
-ttgo-lora32-v21new.upload.maximum_size=1310720
-ttgo-lora32-v21new.upload.maximum_data_size=294912
-ttgo-lora32-v21new.upload.wait_for_upload_port=true
-
-ttgo-lora32-v21new.serial.disableDTR=true
-ttgo-lora32-v21new.serial.disableRTS=true
-
-ttgo-lora32-v21new.build.mcu=esp32
-ttgo-lora32-v21new.build.core=esp32
-ttgo-lora32-v21new.build.variant=ttgo-lora32-v21new
-ttgo-lora32-v21new.build.board=TTGO_LoRa32_v21new
-
-ttgo-lora32-v21new.build.f_cpu=240000000L
-ttgo-lora32-v21new.build.flash_mode=dio
-ttgo-lora32-v21new.build.flash_size=4MB
-ttgo-lora32-v21new.build.boot=dio
-ttgo-lora32-v21new.build.partitions=default
-
-ttgo-lora32-v21new.menu.FlashFreq.80=80MHz
-ttgo-lora32-v21new.menu.FlashFreq.80.build.flash_freq=80m
-ttgo-lora32-v21new.menu.FlashFreq.40=40MHz
-ttgo-lora32-v21new.menu.FlashFreq.40.build.flash_freq=40m
-
-ttgo-lora32-v21new.menu.UploadSpeed.921600=921600
-ttgo-lora32-v21new.menu.UploadSpeed.921600.upload.speed=921600
-ttgo-lora32-v21new.menu.UploadSpeed.115200=115200
-ttgo-lora32-v21new.menu.UploadSpeed.115200.upload.speed=115200
-ttgo-lora32-v21new.menu.UploadSpeed.256000.windows=256000
-ttgo-lora32-v21new.menu.UploadSpeed.256000.upload.speed=256000
-ttgo-lora32-v21new.menu.UploadSpeed.230400.windows.upload.speed=256000
-ttgo-lora32-v21new.menu.UploadSpeed.230400=230400
-ttgo-lora32-v21new.menu.UploadSpeed.230400.upload.speed=230400
-ttgo-lora32-v21new.menu.UploadSpeed.460800.linux=460800
-ttgo-lora32-v21new.menu.UploadSpeed.460800.macosx=460800
-ttgo-lora32-v21new.menu.UploadSpeed.460800.upload.speed=460800
-ttgo-lora32-v21new.menu.UploadSpeed.512000.windows=512000
-ttgo-lora32-v21new.menu.UploadSpeed.512000.upload.speed=512000
-
-ttgo-lora32-v21new.menu.DebugLevel.none=None
-ttgo-lora32-v21new.menu.DebugLevel.none.build.code_debug=0
-ttgo-lora32-v21new.menu.DebugLevel.error=Error
-ttgo-lora32-v21new.menu.DebugLevel.error.build.code_debug=1
-ttgo-lora32-v21new.menu.DebugLevel.warn=Warn
-ttgo-lora32-v21new.menu.DebugLevel.warn.build.code_debug=2
-ttgo-lora32-v21new.menu.DebugLevel.info=Info
-ttgo-lora32-v21new.menu.DebugLevel.info.build.code_debug=3
-ttgo-lora32-v21new.menu.DebugLevel.debug=Debug
-ttgo-lora32-v21new.menu.DebugLevel.debug.build.code_debug=4
-ttgo-lora32-v21new.menu.DebugLevel.verbose=Verbose
-ttgo-lora32-v21new.menu.DebugLevel.verbose.build.code_debug=5w.menu.UploadSpeed.115200.upload.speed=115200
-ttgo-lora32-v21new.menu.UploadSpeed.256000.windows=256000
-ttgo-lora32-v21new.menu.UploadSpeed.256000.upload.speed=256000
-ttgo-lora32-v21new.menu.UploadSpeed.230400.windows.upload.speed=256000
-ttgo-lora32-v21new.menu.UploadSpeed.230400=230400
-ttgo-lora32-v21new.menu.UploadSpeed.230400.upload.speed=230400
-ttgo-lora32-v21new.menu.UploadSpeed.460800.linux=460800
-ttgo-lora32-v21new.menu.UploadSpeed.460800.macosx=460800
-ttgo-lora32-v21new.menu.UploadSpeed.460800.upload.speed=460800
-ttgo-lora32-v21new.menu.UploadSpeed.512000.windows=512000
-ttgo-lora32-v21new.menu.UploadSpeed.512000.upload.speed=512000
-
-ttgo-lora32-v21new.menu.DebugLevel.none=None
-ttgo-lora32-v21new.menu.DebugLevel.none.build.code_debug=0
-ttgo-lora32-v21new.menu.DebugLevel.error=Error
-ttgo-lora32-v21new.menu.DebugLevel.error.build.code_debug=1
-ttgo-lora32-v21new.menu.DebugLevel.warn=Warn
-ttgo-lora32-v21new.menu.DebugLevel.warn.build.code_debug=2
-ttgo-lora32-v21new.menu.DebugLevel.info=Info
-ttgo-lora32-v21new.menu.DebugLevel.info.build.code_debug=3
-ttgo-lora32-v21new.menu.DebugLevel.debug=Debug
-ttgo-lora32-v21new.menu.DebugLevel.debug.build.code_debug=4
-ttgo-lora32-v21new.menu.DebugLevel.verbose=Verbose
-ttgo-lora32-v21new.menu.DebugLevel.verbose.build.code_debug=5
+wifiduino32s3.name=WiFiduino32S3
+
+wifiduino32s3.bootloader.tool=esptool_py
+wifiduino32s3.bootloader.tool.default=esptool_py
+
+wifiduino32s3.upload.tool=esptool_py
+wifiduino32s3.upload.tool.default=esptool_py
+wifiduino32s3.upload.tool.network=esp_ota
+
+wifiduino32s3.upload.maximum_size=1310720
+wifiduino32s3.upload.maximum_data_size=327680
+wifiduino32s3.upload.flags=
+wifiduino32s3.upload.extra_flags=
+wifiduino32s3.upload.use_1200bps_touch=false
+wifiduino32s3.upload.wait_for_upload_port=false
+
+wifiduino32s3.serial.disableDTR=false
+wifiduino32s3.serial.disableRTS=false
+
+wifiduino32s3.build.tarch=xtensa
+wifiduino32s3.build.bootloader_addr=0x0
+wifiduino32s3.build.target=esp32s3
+wifiduino32s3.build.mcu=esp32s3
+wifiduino32s3.build.core=esp32
+wifiduino32s3.build.variant=wifiduino32s3
+wifiduino32s3.build.board=WiFiduino32S3
+
+wifiduino32s3.build.usb_mode=1
+wifiduino32s3.build.cdc_on_boot=0
+wifiduino32s3.build.msc_on_boot=0
+wifiduino32s3.build.dfu_on_boot=0
+wifiduino32s3.build.f_cpu=240000000L
+wifiduino32s3.build.flash_size=4MB
+wifiduino32s3.build.flash_freq=80m
+wifiduino32s3.build.flash_mode=dio
+wifiduino32s3.build.boot=qio
+wifiduino32s3.build.boot_freq=80m
+wifiduino32s3.build.partitions=default
+wifiduino32s3.build.defines=
+wifiduino32s3.build.loop_core=
+wifiduino32s3.build.event_core=
+wifiduino32s3.build.psram_type=qspi
+wifiduino32s3.build.memory_type={build.boot}_{build.psram_type}
+
+wifiduino32s3.menu.PSRAM.disabled=Disabled
+wifiduino32s3.menu.PSRAM.disabled.build.defines=
+wifiduino32s3.menu.PSRAM.disabled.build.psram_type=qspi
+wifiduino32s3.menu.PSRAM.enabled=QSPI PSRAM
+wifiduino32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+wifiduino32s3.menu.PSRAM.enabled.build.psram_type=qspi
+wifiduino32s3.menu.PSRAM.opi=OPI PSRAM
+wifiduino32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+wifiduino32s3.menu.PSRAM.opi.build.psram_type=opi
+
+wifiduino32s3.menu.FlashMode.qio=QIO 80MHz
+wifiduino32s3.menu.FlashMode.qio.build.flash_mode=dio
+wifiduino32s3.menu.FlashMode.qio.build.boot=qio
+wifiduino32s3.menu.FlashMode.qio.build.boot_freq=80m
+wifiduino32s3.menu.FlashMode.qio.build.flash_freq=80m
+wifiduino32s3.menu.FlashMode.qio120=QIO 120MHz
+wifiduino32s3.menu.FlashMode.qio120.build.flash_mode=dio
+wifiduino32s3.menu.FlashMode.qio120.build.boot=qio
+wifiduino32s3.menu.FlashMode.qio120.build.boot_freq=120m
+wifiduino32s3.menu.FlashMode.qio120.build.flash_freq=80m
+wifiduino32s3.menu.FlashMode.dio=DIO 80MHz
+wifiduino32s3.menu.FlashMode.dio.build.flash_mode=dio
+wifiduino32s3.menu.FlashMode.dio.build.boot=dio
+wifiduino32s3.menu.FlashMode.dio.build.boot_freq=80m
+wifiduino32s3.menu.FlashMode.dio.build.flash_freq=80m
+wifiduino32s3.menu.FlashMode.opi=OPI 80MHz
+wifiduino32s3.menu.FlashMode.opi.build.flash_mode=dout
+wifiduino32s3.menu.FlashMode.opi.build.boot=opi
+wifiduino32s3.menu.FlashMode.opi.build.boot_freq=80m
+wifiduino32s3.menu.FlashMode.opi.build.flash_freq=80m
+
+wifiduino32s3.menu.FlashSize.4M=4MB (32Mb)
+wifiduino32s3.menu.FlashSize.4M.build.flash_size=4MB
+wifiduino32s3.menu.FlashSize.8M=8MB (64Mb)
+wifiduino32s3.menu.FlashSize.8M.build.flash_size=8MB
+wifiduino32s3.menu.FlashSize.16M=16MB (128Mb)
+wifiduino32s3.menu.FlashSize.16M.build.flash_size=16MB
+#wifiduino32s3.menu.FlashSize.32M=32MB (256Mb)
+#wifiduino32s3.menu.FlashSize.32M.build.flash_size=32MB
+
+wifiduino32s3.menu.LoopCore.1=Core 1
+wifiduino32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+wifiduino32s3.menu.LoopCore.0=Core 0
+wifiduino32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+wifiduino32s3.menu.EventsCore.1=Core 1
+wifiduino32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+wifiduino32s3.menu.EventsCore.0=Core 0
+wifiduino32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+wifiduino32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+wifiduino32s3.menu.USBMode.hwcdc.build.usb_mode=1
+wifiduino32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+wifiduino32s3.menu.USBMode.default.build.usb_mode=0
+
+wifiduino32s3.menu.CDCOnBoot.default=Disabled
+wifiduino32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+wifiduino32s3.menu.CDCOnBoot.cdc=Enabled
+wifiduino32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+wifiduino32s3.menu.MSCOnBoot.default=Disabled
+wifiduino32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+wifiduino32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+wifiduino32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+wifiduino32s3.menu.DFUOnBoot.default=Disabled
+wifiduino32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+wifiduino32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+wifiduino32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+wifiduino32s3.menu.UploadMode.default=UART0 / Hardware CDC
+wifiduino32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+wifiduino32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+wifiduino32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+wifiduino32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+wifiduino32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+wifiduino32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+wifiduino32s3.menu.PartitionScheme.default.build.partitions=default
+wifiduino32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+wifiduino32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+wifiduino32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+wifiduino32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+wifiduino32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+wifiduino32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+wifiduino32s3.menu.PartitionScheme.minimal.build.partitions=minimal
+wifiduino32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+wifiduino32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+wifiduino32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+wifiduino32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+wifiduino32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+wifiduino32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+wifiduino32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+wifiduino32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+wifiduino32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+wifiduino32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+wifiduino32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+wifiduino32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+wifiduino32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+wifiduino32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+wifiduino32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+wifiduino32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+wifiduino32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+wifiduino32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+wifiduino32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+wifiduino32s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+wifiduino32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+wifiduino32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+wifiduino32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+wifiduino32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+wifiduino32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+wifiduino32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+wifiduino32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+wifiduino32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+wifiduino32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+wifiduino32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+wifiduino32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+wifiduino32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+wifiduino32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+wifiduino32s3.menu.CPUFreq.240=240MHz (WiFi)
+wifiduino32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+wifiduino32s3.menu.CPUFreq.160=160MHz (WiFi)
+wifiduino32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+wifiduino32s3.menu.CPUFreq.80=80MHz (WiFi)
+wifiduino32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+wifiduino32s3.menu.CPUFreq.40=40MHz
+wifiduino32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+wifiduino32s3.menu.CPUFreq.20=20MHz
+wifiduino32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+wifiduino32s3.menu.CPUFreq.10=10MHz
+wifiduino32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+wifiduino32s3.menu.UploadSpeed.921600=921600
+wifiduino32s3.menu.UploadSpeed.921600.upload.speed=921600
+wifiduino32s3.menu.UploadSpeed.115200=115200
+wifiduino32s3.menu.UploadSpeed.115200.upload.speed=115200
+wifiduino32s3.menu.UploadSpeed.256000.windows=256000
+wifiduino32s3.menu.UploadSpeed.256000.upload.speed=256000
+wifiduino32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+wifiduino32s3.menu.UploadSpeed.230400=230400
+wifiduino32s3.menu.UploadSpeed.230400.upload.speed=230400
+wifiduino32s3.menu.UploadSpeed.460800.linux=460800
+wifiduino32s3.menu.UploadSpeed.460800.macosx=460800
+wifiduino32s3.menu.UploadSpeed.460800.upload.speed=460800
+wifiduino32s3.menu.UploadSpeed.512000.windows=512000
+wifiduino32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+wifiduino32s3.menu.DebugLevel.none=None
+wifiduino32s3.menu.DebugLevel.none.build.code_debug=0
+wifiduino32s3.menu.DebugLevel.error=Error
+wifiduino32s3.menu.DebugLevel.error.build.code_debug=1
+wifiduino32s3.menu.DebugLevel.warn=Warn
+wifiduino32s3.menu.DebugLevel.warn.build.code_debug=2
+wifiduino32s3.menu.DebugLevel.info=Info
+wifiduino32s3.menu.DebugLevel.info.build.code_debug=3
+wifiduino32s3.menu.DebugLevel.debug=Debug
+wifiduino32s3.menu.DebugLevel.debug.build.code_debug=4
+wifiduino32s3.menu.DebugLevel.verbose=Verbose
+wifiduino32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+wifiduino32s3.menu.EraseFlash.none=Disabled
+wifiduino32s3.menu.EraseFlash.none.upload.erase_cmd=
+wifiduino32s3.menu.EraseFlash.all=Enabled
+wifiduino32s3.menu.EraseFlash.all.upload.erase_cmd=-e
 
 ##############################################################
 
 imbrios-logsens-v1p1.name=IMBRIOS LOGSENS_V1P1
 
+imbrios-logsens-v1p1.bootloader.tool=esptool_py
+imbrios-logsens-v1p1.bootloader.tool.default=esptool_py
+
 imbrios-logsens-v1p1.upload.tool=esptool_py
+imbrios-logsens-v1p1.upload.tool.default=esptool_py
+imbrios-logsens-v1p1.upload.tool.network=esp_ota
+
 imbrios-logsens-v1p1.upload.maximum_size=1310720
 imbrios-logsens-v1p1.upload.maximum_data_size=327680
 imbrios-logsens-v1p1.upload.wait_for_upload_port=true
+imbrios-logsens-v1p1.upload.flags=
+imbrios-logsens-v1p1.upload.extra_flags=
 
 imbrios-logsens-v1p1.serial.disableDTR=true
 imbrios-logsens-v1p1.serial.disableRTS=true
 
+imbrios-logsens-v1p1.build.tarch=xtensa
+imbrios-logsens-v1p1.build.bootloader_addr=0x1000
+imbrios-logsens-v1p1.build.target=esp32
 imbrios-logsens-v1p1.build.mcu=esp32
 imbrios-logsens-v1p1.build.core=esp32
 imbrios-logsens-v1p1.build.variant=imbrios-logsens-v1p1
@@ -5800,18 +31274,47 @@ imbrios-logsens-v1p1.menu.UploadSpeed.460800.upload.speed=460800
 imbrios-logsens-v1p1.menu.UploadSpeed.512000.windows=512000
 imbrios-logsens-v1p1.menu.UploadSpeed.512000.upload.speed=512000
 
+imbrios-logsens-v1p1.menu.DebugLevel.none=None
+imbrios-logsens-v1p1.menu.DebugLevel.none.build.code_debug=0
+imbrios-logsens-v1p1.menu.DebugLevel.error=Error
+imbrios-logsens-v1p1.menu.DebugLevel.error.build.code_debug=1
+imbrios-logsens-v1p1.menu.DebugLevel.warn=Warn
+imbrios-logsens-v1p1.menu.DebugLevel.warn.build.code_debug=2
+imbrios-logsens-v1p1.menu.DebugLevel.info=Info
+imbrios-logsens-v1p1.menu.DebugLevel.info.build.code_debug=3
+imbrios-logsens-v1p1.menu.DebugLevel.debug=Debug
+imbrios-logsens-v1p1.menu.DebugLevel.debug.build.code_debug=4
+imbrios-logsens-v1p1.menu.DebugLevel.verbose=Verbose
+imbrios-logsens-v1p1.menu.DebugLevel.verbose.build.code_debug=5
+
+imbrios-logsens-v1p1.menu.EraseFlash.none=Disabled
+imbrios-logsens-v1p1.menu.EraseFlash.none.upload.erase_cmd=
+imbrios-logsens-v1p1.menu.EraseFlash.all=Enabled
+imbrios-logsens-v1p1.menu.EraseFlash.all.upload.erase_cmd=-e
+
 ##############################################################
 
 healthypi4.name=ProtoCentral HealthyPi 4
 
+healthypi4.bootloader.tool=esptool_py
+healthypi4.bootloader.tool.default=esptool_py
+
 healthypi4.upload.tool=esptool_py
+healthypi4.upload.tool.default=esptool_py
+healthypi4.upload.tool.network=esp_ota
+
 healthypi4.upload.maximum_size=1310720
 healthypi4.upload.maximum_data_size=327680
 healthypi4.upload.wait_for_upload_port=true
+healthypi4.upload.flags=
+healthypi4.upload.extra_flags=
 
 healthypi4.serial.disableDTR=true
 healthypi4.serial.disableRTS=true
 
+healthypi4.build.tarch=xtensa
+healthypi4.build.bootloader_addr=0x1000
+healthypi4.build.target=esp32
 healthypi4.build.mcu=esp32
 healthypi4.build.core=esp32
 healthypi4.build.variant=healthypi4
@@ -5865,3 +31368,18225 @@ healthypi4.menu.DebugLevel.debug=Debug
 healthypi4.menu.DebugLevel.debug.build.code_debug=4
 healthypi4.menu.DebugLevel.verbose=Verbose
 healthypi4.menu.DebugLevel.verbose.build.code_debug=5
+
+healthypi4.menu.EraseFlash.none=Disabled
+healthypi4.menu.EraseFlash.none.upload.erase_cmd=
+healthypi4.menu.EraseFlash.all=Enabled
+healthypi4.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+ET-Board.name=ET-Board
+
+ET-Board.bootloader.tool=esptool_py
+ET-Board.bootloader.tool.default=esptool_py
+
+ET-Board.upload.tool=esptool_py
+ET-Board.upload.tool.default=esptool_py
+ET-Board.upload.tool.network=esp_ota
+
+ET-Board.upload.maximum_size=1310720
+ET-Board.upload.maximum_data_size=327680
+ET-Board.upload.wait_for_upload_port=true
+ET-Board.upload.flags=
+ET-Board.upload.extra_flags=
+
+ET-Board.serial.disableDTR=true
+ET-Board.serial.disableRTS=true
+
+ET-Board.build.tarch=xtensa
+ET-Board.build.bootloader_addr=0x1000
+ET-Board.build.target=esp32
+ET-Board.build.mcu=esp32
+ET-Board.build.core=esp32
+ET-Board.build.variant=ET-Board
+ET-Board.build.board=ET-Board
+ET-Board.build.f_cpu=240000000L
+ET-Board.build.flash_mode=dio
+ET-Board.build.flash_size=4MB
+ET-Board.build.boot=dio
+ET-Board.build.partitions=default
+ET-Board.build.defines=
+
+ET-Board.menu.PartitionScheme.default=Default
+ET-Board.menu.PartitionScheme.default.build.partitions=default
+ET-Board.menu.PartitionScheme.no_ota=No OTA (Large APP)
+ET-Board.menu.PartitionScheme.no_ota.build.partitions=no_ota
+ET-Board.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+ET-Board.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+ET-Board.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+ET-Board.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+ET-Board.menu.FlashFreq.80=80MHz
+ET-Board.menu.FlashFreq.80.build.flash_freq=80m
+ET-Board.menu.FlashFreq.40=40MHz
+ET-Board.menu.FlashFreq.40.build.flash_freq=40m
+
+ET-Board.menu.UploadSpeed.921600=921600
+ET-Board.menu.UploadSpeed.921600.upload.speed=921600
+ET-Board.menu.UploadSpeed.115200=115200
+ET-Board.menu.UploadSpeed.115200.upload.speed=115200
+ET-Board.menu.UploadSpeed.256000.windows=256000
+ET-Board.menu.UploadSpeed.256000.upload.speed=256000
+ET-Board.menu.UploadSpeed.230400.windows.upload.speed=256000
+ET-Board.menu.UploadSpeed.230400=230400
+ET-Board.menu.UploadSpeed.230400.upload.speed=230400
+ET-Board.menu.UploadSpeed.460800.linux=460800
+ET-Board.menu.UploadSpeed.460800.macosx=460800
+ET-Board.menu.UploadSpeed.460800.upload.speed=460800
+ET-Board.menu.UploadSpeed.512000.windows=512000
+ET-Board.menu.UploadSpeed.512000.upload.speed=512000
+
+ET-Board.menu.DebugLevel.none=None
+ET-Board.menu.DebugLevel.none.build.code_debug=0
+ET-Board.menu.DebugLevel.error=Error
+ET-Board.menu.DebugLevel.error.build.code_debug=1
+ET-Board.menu.DebugLevel.warn=Warn
+ET-Board.menu.DebugLevel.warn.build.code_debug=2
+ET-Board.menu.DebugLevel.info=Info
+ET-Board.menu.DebugLevel.info.build.code_debug=3
+ET-Board.menu.DebugLevel.debug=Debug
+ET-Board.menu.DebugLevel.debug.build.code_debug=4
+ET-Board.menu.DebugLevel.verbose=Verbose
+ET-Board.menu.DebugLevel.verbose.build.code_debug=5
+
+ET-Board.menu.EraseFlash.none=Disabled
+ET-Board.menu.EraseFlash.none.upload.erase_cmd=
+ET-Board.menu.EraseFlash.all=Enabled
+ET-Board.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+ch_denky.name=Denky
+
+ch_denky.bootloader.tool=esptool_py
+ch_denky.bootloader.tool.default=esptool_py
+
+ch_denky.upload.tool=esptool_py
+ch_denky.upload.tool.default=esptool_py
+ch_denky.upload.tool.network=esp_ota
+
+ch_denky.upload.maximum_size=1310720
+ch_denky.upload.maximum_data_size=327680
+ch_denky.upload.flags=
+ch_denky.upload.extra_flags=
+
+ch_denky.serial.disableDTR=true
+ch_denky.serial.disableRTS=true
+
+ch_denky.build.tarch=xtensa
+ch_denky.build.bootloader_addr=0x1000
+ch_denky.build.target=esp32
+ch_denky.build.mcu=esp32
+ch_denky.build.core=esp32
+ch_denky.build.variant=ch_denky
+ch_denky.build.board=DENKY
+
+ch_denky.build.f_cpu=240000000L
+ch_denky.build.flash_size=4MB
+ch_denky.build.flash_freq=80m
+ch_denky.build.flash_mode=dio
+ch_denky.build.boot=dio
+ch_denky.build.partitions=default
+ch_denky.build.defines=
+
+ch_denky.menu.Revision.denkyd4=PICO-V3-02
+ch_denky.menu.Revision.denkyd4.build.board=DENKY_PICOV3
+ch_denky.menu.Revision.denkyd4.build.flash_size=8MB
+ch_denky.menu.Revision.denky32=WROOM32
+ch_denky.menu.Revision.denky32.build.board=DENKY_WROOM32
+ch_denky.menu.Revision.denkyd4.build.flash_size=4MB
+
+ch_denky.menu.PartitionScheme.default=Default
+ch_denky.menu.PartitionScheme.default.build.partitions=default
+ch_denky.menu.PartitionScheme.no_ota=No OTA (Large APP)
+ch_denky.menu.PartitionScheme.no_ota.build.partitions=no_ota
+ch_denky.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+ch_denky.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+ch_denky.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+ch_denky.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+ch_denky.menu.UploadSpeed.921600=921600
+ch_denky.menu.UploadSpeed.921600.upload.speed=921600
+ch_denky.menu.UploadSpeed.115200=115200
+ch_denky.menu.UploadSpeed.115200.upload.speed=115200
+ch_denky.menu.UploadSpeed.256000.windows=256000
+ch_denky.menu.UploadSpeed.256000.upload.speed=256000
+ch_denky.menu.UploadSpeed.230400.windows.upload.speed=256000
+ch_denky.menu.UploadSpeed.230400=230400
+ch_denky.menu.UploadSpeed.230400.upload.speed=230400
+ch_denky.menu.UploadSpeed.460800.linux=460800
+ch_denky.menu.UploadSpeed.460800.macosx=460800
+ch_denky.menu.UploadSpeed.460800.upload.speed=460800
+ch_denky.menu.UploadSpeed.512000.windows=512000
+ch_denky.menu.UploadSpeed.512000.upload.speed=512000
+
+ch_denky.menu.PSRAM.enabled=Enabled
+ch_denky.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+ch_denky.menu.PSRAM.enabled.build.extra_libs=
+ch_denky.menu.PSRAM.disabled=Disabled
+ch_denky.menu.PSRAM.disabled.build.defines=
+ch_denky.menu.PSRAM.disabled.build.extra_libs=
+
+ch_denky.menu.DebugLevel.none=None
+ch_denky.menu.DebugLevel.none.build.code_debug=0
+ch_denky.menu.DebugLevel.error=Error
+ch_denky.menu.DebugLevel.error.build.code_debug=1
+ch_denky.menu.DebugLevel.warn=Warn
+ch_denky.menu.DebugLevel.warn.build.code_debug=2
+ch_denky.menu.DebugLevel.info=Info
+ch_denky.menu.DebugLevel.info.build.code_debug=3
+ch_denky.menu.DebugLevel.debug=Debug
+ch_denky.menu.DebugLevel.debug.build.code_debug=4
+ch_denky.menu.DebugLevel.verbose=Verbose
+ch_denky.menu.DebugLevel.verbose.build.code_debug=5
+
+ch_denky.menu.EraseFlash.none=Disabled
+ch_denky.menu.EraseFlash.none.upload.erase_cmd=
+ch_denky.menu.EraseFlash.all=Enabled
+ch_denky.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+uPesy_wrover.name=uPesy ESP32 Wrover DevKit
+
+uPesy_wrover.bootloader.tool=esptool_py
+uPesy_wrover.bootloader.tool.default=esptool_py
+
+uPesy_wrover.upload.tool=esptool_py
+uPesy_wrover.upload.tool.default=esptool_py
+uPesy_wrover.upload.tool.network=esp_ota
+
+uPesy_wrover.upload.maximum_size=1310720
+uPesy_wrover.upload.maximum_data_size=327680
+uPesy_wrover.upload.flags=
+uPesy_wrover.upload.extra_flags=
+
+uPesy_wrover.serial.disableDTR=true
+uPesy_wrover.serial.disableRTS=true
+
+uPesy_wrover.build.tarch=xtensa
+uPesy_wrover.build.bootloader_addr=0x1000
+uPesy_wrover.build.target=esp32
+uPesy_wrover.build.mcu=esp32
+uPesy_wrover.build.core=esp32
+uPesy_wrover.build.variant=uPesy_esp32_wrover_devkit
+uPesy_wrover.build.board=UPESY_WROVER
+
+uPesy_wrover.build.f_cpu=240000000L
+uPesy_wrover.build.flash_size=4MB
+uPesy_wrover.build.flash_freq=80m
+uPesy_wrover.build.flash_mode=dio
+uPesy_wrover.build.boot=dio
+uPesy_wrover.build.partitions=default
+uPesy_wrover.build.defines=
+
+uPesy_wrover.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+uPesy_wrover.menu.PartitionScheme.default.build.partitions=default
+uPesy_wrover.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+uPesy_wrover.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+uPesy_wrover.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+uPesy_wrover.menu.PartitionScheme.minimal.build.partitions=minimal
+uPesy_wrover.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+uPesy_wrover.menu.PartitionScheme.no_ota.build.partitions=no_ota
+uPesy_wrover.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+uPesy_wrover.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+uPesy_wrover.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+uPesy_wrover.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+uPesy_wrover.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+uPesy_wrover.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+uPesy_wrover.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+uPesy_wrover.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+uPesy_wrover.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+uPesy_wrover.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+uPesy_wrover.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+uPesy_wrover.menu.PartitionScheme.huge_app.build.partitions=huge_app
+uPesy_wrover.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+uPesy_wrover.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+uPesy_wrover.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+uPesy_wrover.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+uPesy_wrover.menu.CPUFreq.240=240MHz
+uPesy_wrover.menu.CPUFreq.240.build.f_cpu=240000000L
+uPesy_wrover.menu.CPUFreq.160=160MHz
+uPesy_wrover.menu.CPUFreq.160.build.f_cpu=160000000L
+
+uPesy_wrover.menu.UploadSpeed.921600=921600
+uPesy_wrover.menu.UploadSpeed.921600.upload.speed=921600
+uPesy_wrover.menu.UploadSpeed.512000.windows=512000
+uPesy_wrover.menu.UploadSpeed.512000.upload.speed=512000
+uPesy_wrover.menu.UploadSpeed.460800.linux=460800
+uPesy_wrover.menu.UploadSpeed.460800.macosx=460800
+uPesy_wrover.menu.UploadSpeed.460800.upload.speed=460800
+uPesy_wrover.menu.UploadSpeed.256000.windows=256000
+uPesy_wrover.menu.UploadSpeed.256000.upload.speed=256000
+uPesy_wrover.menu.UploadSpeed.230400.windows.upload.speed=256000
+uPesy_wrover.menu.UploadSpeed.230400=230400
+uPesy_wrover.menu.UploadSpeed.230400.upload.speed=230400
+uPesy_wrover.menu.UploadSpeed.115200=115200
+uPesy_wrover.menu.UploadSpeed.115200.upload.speed=115200
+
+uPesy_wrover.menu.FlashMode.qio=QIO
+uPesy_wrover.menu.FlashMode.qio.build.flash_mode=dio
+uPesy_wrover.menu.FlashMode.qio.build.boot=qio
+uPesy_wrover.menu.FlashMode.dio=DIO
+uPesy_wrover.menu.FlashMode.dio.build.flash_mode=dio
+uPesy_wrover.menu.FlashMode.dio.build.boot=dio
+
+uPesy_wrover.menu.FlashFreq.80=80MHz
+uPesy_wrover.menu.FlashFreq.80.build.flash_freq=80m
+uPesy_wrover.menu.FlashFreq.40=40MHz
+uPesy_wrover.menu.FlashFreq.40.build.flash_freq=40m
+
+uPesy_wrover.menu.PSRAM.enabled=Enabled
+uPesy_wrover.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+uPesy_wrover.menu.PSRAM.enabled.build.extra_libs=
+uPesy_wrover.menu.PSRAM.disabled=Disabled
+uPesy_wrover.menu.PSRAM.disabled.build.defines=
+uPesy_wrover.menu.PSRAM.disabled.build.extra_libs=
+
+uPesy_wrover.menu.DebugLevel.none=None
+uPesy_wrover.menu.DebugLevel.none.build.code_debug=0
+uPesy_wrover.menu.DebugLevel.error=Error
+uPesy_wrover.menu.DebugLevel.error.build.code_debug=1
+uPesy_wrover.menu.DebugLevel.warn=Warn
+uPesy_wrover.menu.DebugLevel.warn.build.code_debug=2
+uPesy_wrover.menu.DebugLevel.info=Info
+uPesy_wrover.menu.DebugLevel.info.build.code_debug=3
+uPesy_wrover.menu.DebugLevel.debug=Debug
+uPesy_wrover.menu.DebugLevel.debug.build.code_debug=4
+uPesy_wrover.menu.DebugLevel.verbose=Verbose
+uPesy_wrover.menu.DebugLevel.verbose.build.code_debug=5
+
+uPesy_wrover.menu.EraseFlash.none=Disabled
+uPesy_wrover.menu.EraseFlash.none.upload.erase_cmd=
+uPesy_wrover.menu.EraseFlash.all=Enabled
+uPesy_wrover.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+uPesy_wroom.name=uPesy ESP32 Wroom DevKit
+
+uPesy_wroom.bootloader.tool=esptool_py
+uPesy_wroom.bootloader.tool.default=esptool_py
+
+uPesy_wroom.upload.tool=esptool_py
+uPesy_wroom.upload.tool.default=esptool_py
+uPesy_wroom.upload.tool.network=esp_ota
+
+uPesy_wroom.upload.maximum_size=1310720
+uPesy_wroom.upload.maximum_data_size=327680
+uPesy_wroom.upload.flags=
+uPesy_wroom.upload.extra_flags=
+
+uPesy_wroom.serial.disableDTR=true
+uPesy_wroom.serial.disableRTS=true
+
+uPesy_wroom.build.tarch=xtensa
+uPesy_wroom.build.bootloader_addr=0x1000
+uPesy_wroom.build.target=esp32
+uPesy_wroom.build.mcu=esp32
+uPesy_wroom.build.core=esp32
+uPesy_wroom.build.variant=uPesy_esp32_wroom_devkit
+uPesy_wroom.build.board=UPESY_WROOM
+
+uPesy_wroom.build.f_cpu=240000000L
+uPesy_wroom.build.flash_size=4MB
+uPesy_wroom.build.flash_freq=80m
+uPesy_wroom.build.flash_mode=dio
+uPesy_wroom.build.boot=dio
+uPesy_wroom.build.partitions=default
+uPesy_wroom.build.defines=
+
+uPesy_wroom.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+uPesy_wroom.menu.PartitionScheme.default.build.partitions=default
+uPesy_wroom.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+uPesy_wroom.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+uPesy_wroom.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+uPesy_wroom.menu.PartitionScheme.minimal.build.partitions=minimal
+uPesy_wroom.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+uPesy_wroom.menu.PartitionScheme.no_ota.build.partitions=no_ota
+uPesy_wroom.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+uPesy_wroom.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+uPesy_wroom.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+uPesy_wroom.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+uPesy_wroom.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+uPesy_wroom.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+uPesy_wroom.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+uPesy_wroom.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+uPesy_wroom.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+uPesy_wroom.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+uPesy_wroom.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+uPesy_wroom.menu.PartitionScheme.huge_app.build.partitions=huge_app
+uPesy_wroom.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+uPesy_wroom.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+uPesy_wroom.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+uPesy_wroom.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+uPesy_wroom.menu.CPUFreq.240=240MHz
+uPesy_wroom.menu.CPUFreq.240.build.f_cpu=240000000L
+uPesy_wroom.menu.CPUFreq.160=160MHz
+uPesy_wroom.menu.CPUFreq.160.build.f_cpu=160000000L
+
+uPesy_wroom.menu.UploadSpeed.921600=921600
+uPesy_wroom.menu.UploadSpeed.921600.upload.speed=921600
+uPesy_wroom.menu.UploadSpeed.512000.windows=512000
+uPesy_wroom.menu.UploadSpeed.512000.upload.speed=512000
+uPesy_wroom.menu.UploadSpeed.460800.linux=460800
+uPesy_wroom.menu.UploadSpeed.460800.macosx=460800
+uPesy_wroom.menu.UploadSpeed.460800.upload.speed=460800
+uPesy_wroom.menu.UploadSpeed.256000.windows=256000
+uPesy_wroom.menu.UploadSpeed.256000.upload.speed=256000
+uPesy_wroom.menu.UploadSpeed.230400.windows.upload.speed=256000
+uPesy_wroom.menu.UploadSpeed.230400=230400
+uPesy_wroom.menu.UploadSpeed.230400.upload.speed=230400
+uPesy_wroom.menu.UploadSpeed.115200=115200
+uPesy_wroom.menu.UploadSpeed.115200.upload.speed=115200
+
+uPesy_wroom.menu.FlashMode.qio=QIO
+uPesy_wroom.menu.FlashMode.qio.build.flash_mode=dio
+uPesy_wroom.menu.FlashMode.qio.build.boot=qio
+uPesy_wroom.menu.FlashMode.dio=DIO
+uPesy_wroom.menu.FlashMode.dio.build.flash_mode=dio
+uPesy_wroom.menu.FlashMode.dio.build.boot=dio
+
+uPesy_wroom.menu.FlashFreq.80=80MHz
+uPesy_wroom.menu.FlashFreq.80.build.flash_freq=80m
+uPesy_wroom.menu.FlashFreq.40=40MHz
+uPesy_wroom.menu.FlashFreq.40.build.flash_freq=40m
+
+uPesy_wroom.menu.DebugLevel.none=None
+uPesy_wroom.menu.DebugLevel.none.build.code_debug=0
+uPesy_wroom.menu.DebugLevel.error=Error
+uPesy_wroom.menu.DebugLevel.error.build.code_debug=1
+uPesy_wroom.menu.DebugLevel.warn=Warn
+uPesy_wroom.menu.DebugLevel.warn.build.code_debug=2
+uPesy_wroom.menu.DebugLevel.info=Info
+uPesy_wroom.menu.DebugLevel.info.build.code_debug=3
+uPesy_wroom.menu.DebugLevel.debug=Debug
+uPesy_wroom.menu.DebugLevel.debug.build.code_debug=4
+uPesy_wroom.menu.DebugLevel.verbose=Verbose
+uPesy_wroom.menu.DebugLevel.verbose.build.code_debug=5
+
+uPesy_wroom.menu.EraseFlash.none=Disabled
+uPesy_wroom.menu.EraseFlash.none.upload.erase_cmd=
+uPesy_wroom.menu.EraseFlash.all=Enabled
+uPesy_wroom.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+uPesy_edu_esp32.name=uPesy EDU ESP32
+
+uPesy_edu_esp32.bootloader.tool=esptool_py
+uPesy_edu_esp32.bootloader.tool.default=esptool_py
+
+uPesy_edu_esp32.upload.tool=esptool_py
+uPesy_edu_esp32.upload.tool.default=esptool_py
+uPesy_edu_esp32.upload.tool.network=esp_ota
+
+uPesy_edu_esp32.upload.maximum_size=1310720
+uPesy_edu_esp32.upload.maximum_data_size=327680
+uPesy_edu_esp32.upload.flags=
+uPesy_edu_esp32.upload.extra_flags=
+
+uPesy_edu_esp32.serial.disableDTR=true
+uPesy_edu_esp32.serial.disableRTS=true
+
+uPesy_edu_esp32.build.tarch=xtensa
+uPesy_edu_esp32.build.bootloader_addr=0x1000
+uPesy_edu_esp32.build.target=esp32
+uPesy_edu_esp32.build.mcu=esp32
+uPesy_edu_esp32.build.core=esp32
+uPesy_edu_esp32.build.variant=uPesy_edu_esp32
+uPesy_edu_esp32.build.board=UPESY_EDU_ESP32
+
+uPesy_edu_esp32.build.f_cpu=240000000L
+uPesy_edu_esp32.build.flash_size=4MB
+uPesy_edu_esp32.build.flash_freq=80m
+uPesy_edu_esp32.build.flash_mode=dio
+uPesy_edu_esp32.build.boot=dio
+uPesy_edu_esp32.build.partitions=default
+uPesy_edu_esp32.build.defines=
+
+uPesy_edu_esp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+uPesy_edu_esp32.menu.PartitionScheme.default.build.partitions=default
+uPesy_edu_esp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+uPesy_edu_esp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+uPesy_edu_esp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+uPesy_edu_esp32.menu.PartitionScheme.minimal.build.partitions=minimal
+uPesy_edu_esp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+uPesy_edu_esp32.menu.PartitionScheme.no_ota.build.partitions=no_ota
+uPesy_edu_esp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+uPesy_edu_esp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+uPesy_edu_esp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+uPesy_edu_esp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+uPesy_edu_esp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+uPesy_edu_esp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+uPesy_edu_esp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+uPesy_edu_esp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+uPesy_edu_esp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+uPesy_edu_esp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+uPesy_edu_esp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+uPesy_edu_esp32.menu.PartitionScheme.huge_app.build.partitions=huge_app
+uPesy_edu_esp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+uPesy_edu_esp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+uPesy_edu_esp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+uPesy_edu_esp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+uPesy_edu_esp32.menu.CPUFreq.240=240MHz
+uPesy_edu_esp32.menu.CPUFreq.240.build.f_cpu=240000000L
+uPesy_edu_esp32.menu.CPUFreq.160=160MHz
+uPesy_edu_esp32.menu.CPUFreq.160.build.f_cpu=160000000L
+
+uPesy_edu_esp32.menu.UploadSpeed.921600=921600
+uPesy_edu_esp32.menu.UploadSpeed.921600.upload.speed=921600
+uPesy_edu_esp32.menu.UploadSpeed.512000.windows=512000
+uPesy_edu_esp32.menu.UploadSpeed.512000.upload.speed=512000
+uPesy_edu_esp32.menu.UploadSpeed.460800.linux=460800
+uPesy_edu_esp32.menu.UploadSpeed.460800.macosx=460800
+uPesy_edu_esp32.menu.UploadSpeed.460800.upload.speed=460800
+uPesy_edu_esp32.menu.UploadSpeed.256000.windows=256000
+uPesy_edu_esp32.menu.UploadSpeed.256000.upload.speed=256000
+uPesy_edu_esp32.menu.UploadSpeed.230400.windows.upload.speed=256000
+uPesy_edu_esp32.menu.UploadSpeed.230400=230400
+uPesy_edu_esp32.menu.UploadSpeed.230400.upload.speed=230400
+uPesy_edu_esp32.menu.UploadSpeed.115200=115200
+uPesy_edu_esp32.menu.UploadSpeed.115200.upload.speed=115200
+
+uPesy_edu_esp32.menu.FlashMode.qio=QIO
+uPesy_edu_esp32.menu.FlashMode.qio.build.flash_mode=dio
+uPesy_edu_esp32.menu.FlashMode.qio.build.boot=qio
+uPesy_edu_esp32.menu.FlashMode.dio=DIO
+uPesy_edu_esp32.menu.FlashMode.dio.build.flash_mode=dio
+uPesy_edu_esp32.menu.FlashMode.dio.build.boot=dio
+
+uPesy_edu_esp32.menu.FlashFreq.80=80MHz
+uPesy_edu_esp32.menu.FlashFreq.80.build.flash_freq=80m
+uPesy_edu_esp32.menu.FlashFreq.40=40MHz
+uPesy_edu_esp32.menu.FlashFreq.40.build.flash_freq=40m
+
+uPesy_edu_esp32.menu.DebugLevel.none=None
+uPesy_edu_esp32.menu.DebugLevel.none.build.code_debug=0
+uPesy_edu_esp32.menu.DebugLevel.error=Error
+uPesy_edu_esp32.menu.DebugLevel.error.build.code_debug=1
+uPesy_edu_esp32.menu.DebugLevel.warn=Warn
+uPesy_edu_esp32.menu.DebugLevel.warn.build.code_debug=2
+uPesy_edu_esp32.menu.DebugLevel.info=Info
+uPesy_edu_esp32.menu.DebugLevel.info.build.code_debug=3
+uPesy_edu_esp32.menu.DebugLevel.debug=Debug
+uPesy_edu_esp32.menu.DebugLevel.debug.build.code_debug=4
+uPesy_edu_esp32.menu.DebugLevel.verbose=Verbose
+uPesy_edu_esp32.menu.DebugLevel.verbose.build.code_debug=5
+
+uPesy_edu_esp32.menu.EraseFlash.none=Disabled
+uPesy_edu_esp32.menu.EraseFlash.none.upload.erase_cmd=
+uPesy_edu_esp32.menu.EraseFlash.all=Enabled
+uPesy_edu_esp32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+upesy_esp32c3_basic.name=uPesy ESP32C3 Basic
+upesy_esp32c3_basic.vid.0=0x303a
+upesy_esp32c3_basic.pid.0=0x8195
+
+upesy_esp32c3_basic.bootloader.tool=esptool_py
+upesy_esp32c3_basic.bootloader.tool.default=esptool_py
+
+upesy_esp32c3_basic.upload.tool=esptool_py
+upesy_esp32c3_basic.upload.tool.default=esptool_py
+upesy_esp32c3_basic.upload.tool.network=esp_ota
+
+upesy_esp32c3_basic.upload.maximum_size=1310720
+upesy_esp32c3_basic.upload.maximum_data_size=327680
+upesy_esp32c3_basic.upload.flags=
+upesy_esp32c3_basic.upload.extra_flags=
+upesy_esp32c3_basic.upload.use_1200bps_touch=false
+upesy_esp32c3_basic.upload.wait_for_upload_port=false
+
+upesy_esp32c3_basic.serial.disableDTR=true
+upesy_esp32c3_basic.serial.disableRTS=true
+
+upesy_esp32c3_basic.build.tarch=riscv32
+upesy_esp32c3_basic.build.target=esp
+upesy_esp32c3_basic.build.mcu=esp32c3
+upesy_esp32c3_basic.build.core=esp32
+upesy_esp32c3_basic.build.variant=uPesy_esp32c3_basic
+upesy_esp32c3_basic.build.board=UPESY_ESP32C3_BASIC
+upesy_esp32c3_basic.build.bootloader_addr=0x0
+
+upesy_esp32c3_basic.build.cdc_on_boot=1
+upesy_esp32c3_basic.build.f_cpu=160000000L
+upesy_esp32c3_basic.build.flash_size=4MB
+upesy_esp32c3_basic.build.flash_freq=80m
+upesy_esp32c3_basic.build.flash_mode=dio
+upesy_esp32c3_basic.build.boot=qio
+upesy_esp32c3_basic.build.partitions=default
+upesy_esp32c3_basic.build.defines=
+
+upesy_esp32c3_basic.menu.CDCOnBoot.default=Enabled
+upesy_esp32c3_basic.menu.CDCOnBoot.default.build.cdc_on_boot=1
+upesy_esp32c3_basic.menu.CDCOnBoot.dis_cdc=Disabled
+upesy_esp32c3_basic.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+upesy_esp32c3_basic.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+upesy_esp32c3_basic.menu.PartitionScheme.default.build.partitions=default
+upesy_esp32c3_basic.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+upesy_esp32c3_basic.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+upesy_esp32c3_basic.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+upesy_esp32c3_basic.menu.PartitionScheme.no_ota.build.partitions=no_ota
+upesy_esp32c3_basic.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+upesy_esp32c3_basic.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+upesy_esp32c3_basic.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+upesy_esp32c3_basic.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+upesy_esp32c3_basic.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+upesy_esp32c3_basic.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+upesy_esp32c3_basic.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+upesy_esp32c3_basic.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+upesy_esp32c3_basic.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+upesy_esp32c3_basic.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+upesy_esp32c3_basic.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+upesy_esp32c3_basic.menu.PartitionScheme.huge_app.build.partitions=huge_app
+upesy_esp32c3_basic.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+upesy_esp32c3_basic.menu.CPUFreq.160=160MHz (WiFi)
+upesy_esp32c3_basic.menu.CPUFreq.160.build.f_cpu=160000000L
+upesy_esp32c3_basic.menu.CPUFreq.80=80MHz (WiFi)
+upesy_esp32c3_basic.menu.CPUFreq.80.build.f_cpu=80000000L
+upesy_esp32c3_basic.menu.CPUFreq.40=40MHz
+upesy_esp32c3_basic.menu.CPUFreq.40.build.f_cpu=40000000L
+upesy_esp32c3_basic.menu.CPUFreq.20=20MHz
+upesy_esp32c3_basic.menu.CPUFreq.20.build.f_cpu=20000000L
+upesy_esp32c3_basic.menu.CPUFreq.10=10MHz
+upesy_esp32c3_basic.menu.CPUFreq.10.build.f_cpu=10000000L
+
+upesy_esp32c3_basic.menu.FlashFreq.80=80MHz
+upesy_esp32c3_basic.menu.FlashFreq.80.build.flash_freq=80m
+upesy_esp32c3_basic.menu.FlashFreq.40=40MHz
+upesy_esp32c3_basic.menu.FlashFreq.40.build.flash_freq=40m
+
+upesy_esp32c3_basic.menu.UploadSpeed.921600=921600
+upesy_esp32c3_basic.menu.UploadSpeed.921600.upload.speed=921600
+upesy_esp32c3_basic.menu.UploadSpeed.115200=115200
+upesy_esp32c3_basic.menu.UploadSpeed.115200.upload.speed=115200
+upesy_esp32c3_basic.menu.UploadSpeed.256000.windows=256000
+upesy_esp32c3_basic.menu.UploadSpeed.256000.upload.speed=256000
+upesy_esp32c3_basic.menu.UploadSpeed.230400.windows.upload.speed=256000
+upesy_esp32c3_basic.menu.UploadSpeed.230400=230400
+upesy_esp32c3_basic.menu.UploadSpeed.230400.upload.speed=230400
+upesy_esp32c3_basic.menu.UploadSpeed.460800.linux=460800
+upesy_esp32c3_basic.menu.UploadSpeed.460800.macosx=460800
+upesy_esp32c3_basic.menu.UploadSpeed.460800.upload.speed=460800
+upesy_esp32c3_basic.menu.UploadSpeed.512000.windows=512000
+upesy_esp32c3_basic.menu.UploadSpeed.512000.upload.speed=512000
+
+upesy_esp32c3_basic.menu.DebugLevel.none=None
+upesy_esp32c3_basic.menu.DebugLevel.none.build.code_debug=0
+upesy_esp32c3_basic.menu.DebugLevel.error=Error
+upesy_esp32c3_basic.menu.DebugLevel.error.build.code_debug=1
+upesy_esp32c3_basic.menu.DebugLevel.warn=Warn
+upesy_esp32c3_basic.menu.DebugLevel.warn.build.code_debug=2
+upesy_esp32c3_basic.menu.DebugLevel.info=Info
+upesy_esp32c3_basic.menu.DebugLevel.info.build.code_debug=3
+upesy_esp32c3_basic.menu.DebugLevel.debug=Debug
+upesy_esp32c3_basic.menu.DebugLevel.debug.build.code_debug=4
+upesy_esp32c3_basic.menu.DebugLevel.verbose=Verbose
+upesy_esp32c3_basic.menu.DebugLevel.verbose.build.code_debug=5
+
+upesy_esp32c3_basic.menu.EraseFlash.none=Disabled
+upesy_esp32c3_basic.menu.EraseFlash.none.upload.erase_cmd=
+upesy_esp32c3_basic.menu.EraseFlash.all=Enabled
+upesy_esp32c3_basic.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+upesy_esp32c3_mini.name=uPesy ESP32C3 Mini
+upesy_esp32c3_mini.vid.0=0x303a
+upesy_esp32c3_mini.pid.0=0x819B
+
+upesy_esp32c3_mini.bootloader.tool=esptool_py
+upesy_esp32c3_mini.bootloader.tool.default=esptool_py
+
+upesy_esp32c3_mini.upload.tool=esptool_py
+upesy_esp32c3_mini.upload.tool.default=esptool_py
+upesy_esp32c3_mini.upload.tool.network=esp_ota
+
+upesy_esp32c3_mini.upload.maximum_size=1310720
+upesy_esp32c3_mini.upload.maximum_data_size=327680
+upesy_esp32c3_mini.upload.flags=
+upesy_esp32c3_mini.upload.extra_flags=
+upesy_esp32c3_mini.upload.use_1200bps_touch=false
+upesy_esp32c3_mini.upload.wait_for_upload_port=false
+
+upesy_esp32c3_mini.serial.disableDTR=true
+upesy_esp32c3_mini.serial.disableRTS=true
+
+upesy_esp32c3_mini.build.tarch=riscv32
+upesy_esp32c3_mini.build.target=esp
+upesy_esp32c3_mini.build.mcu=esp32c3
+upesy_esp32c3_mini.build.core=esp32
+upesy_esp32c3_mini.build.variant=uPesy_esp32c3_mini
+upesy_esp32c3_mini.build.board=UPESY_ESP32C3_MINI
+upesy_esp32c3_mini.build.bootloader_addr=0x0
+
+upesy_esp32c3_mini.build.cdc_on_boot=1
+upesy_esp32c3_mini.build.f_cpu=160000000L
+upesy_esp32c3_mini.build.flash_size=4MB
+upesy_esp32c3_mini.build.flash_freq=80m
+upesy_esp32c3_mini.build.flash_mode=dio
+upesy_esp32c3_mini.build.boot=qio
+upesy_esp32c3_mini.build.partitions=default
+upesy_esp32c3_mini.build.defines=
+
+upesy_esp32c3_mini.menu.CDCOnBoot.default=Enabled
+upesy_esp32c3_mini.menu.CDCOnBoot.default.build.cdc_on_boot=1
+upesy_esp32c3_mini.menu.CDCOnBoot.dis_cdc=Disabled
+upesy_esp32c3_mini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+upesy_esp32c3_mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+upesy_esp32c3_mini.menu.PartitionScheme.default.build.partitions=default
+upesy_esp32c3_mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+upesy_esp32c3_mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+upesy_esp32c3_mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+upesy_esp32c3_mini.menu.PartitionScheme.no_ota.build.partitions=no_ota
+upesy_esp32c3_mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+upesy_esp32c3_mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+upesy_esp32c3_mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+upesy_esp32c3_mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+upesy_esp32c3_mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+upesy_esp32c3_mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+upesy_esp32c3_mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+upesy_esp32c3_mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+upesy_esp32c3_mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+upesy_esp32c3_mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+upesy_esp32c3_mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+upesy_esp32c3_mini.menu.PartitionScheme.huge_app.build.partitions=huge_app
+upesy_esp32c3_mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+upesy_esp32c3_mini.menu.CPUFreq.160=160MHz (WiFi)
+upesy_esp32c3_mini.menu.CPUFreq.160.build.f_cpu=160000000L
+upesy_esp32c3_mini.menu.CPUFreq.80=80MHz (WiFi)
+upesy_esp32c3_mini.menu.CPUFreq.80.build.f_cpu=80000000L
+upesy_esp32c3_mini.menu.CPUFreq.40=40MHz
+upesy_esp32c3_mini.menu.CPUFreq.40.build.f_cpu=40000000L
+upesy_esp32c3_mini.menu.CPUFreq.20=20MHz
+upesy_esp32c3_mini.menu.CPUFreq.20.build.f_cpu=20000000L
+upesy_esp32c3_mini.menu.CPUFreq.10=10MHz
+upesy_esp32c3_mini.menu.CPUFreq.10.build.f_cpu=10000000L
+
+upesy_esp32c3_mini.menu.FlashFreq.80=80MHz
+upesy_esp32c3_mini.menu.FlashFreq.80.build.flash_freq=80m
+upesy_esp32c3_mini.menu.FlashFreq.40=40MHz
+upesy_esp32c3_mini.menu.FlashFreq.40.build.flash_freq=40m
+
+upesy_esp32c3_mini.menu.UploadSpeed.921600=921600
+upesy_esp32c3_mini.menu.UploadSpeed.921600.upload.speed=921600
+upesy_esp32c3_mini.menu.UploadSpeed.115200=115200
+upesy_esp32c3_mini.menu.UploadSpeed.115200.upload.speed=115200
+upesy_esp32c3_mini.menu.UploadSpeed.256000.windows=256000
+upesy_esp32c3_mini.menu.UploadSpeed.256000.upload.speed=256000
+upesy_esp32c3_mini.menu.UploadSpeed.230400.windows.upload.speed=256000
+upesy_esp32c3_mini.menu.UploadSpeed.230400=230400
+upesy_esp32c3_mini.menu.UploadSpeed.230400.upload.speed=230400
+upesy_esp32c3_mini.menu.UploadSpeed.460800.linux=460800
+upesy_esp32c3_mini.menu.UploadSpeed.460800.macosx=460800
+upesy_esp32c3_mini.menu.UploadSpeed.460800.upload.speed=460800
+upesy_esp32c3_mini.menu.UploadSpeed.512000.windows=512000
+upesy_esp32c3_mini.menu.UploadSpeed.512000.upload.speed=512000
+
+upesy_esp32c3_mini.menu.DebugLevel.none=None
+upesy_esp32c3_mini.menu.DebugLevel.none.build.code_debug=0
+upesy_esp32c3_mini.menu.DebugLevel.error=Error
+upesy_esp32c3_mini.menu.DebugLevel.error.build.code_debug=1
+upesy_esp32c3_mini.menu.DebugLevel.warn=Warn
+upesy_esp32c3_mini.menu.DebugLevel.warn.build.code_debug=2
+upesy_esp32c3_mini.menu.DebugLevel.info=Info
+upesy_esp32c3_mini.menu.DebugLevel.info.build.code_debug=3
+upesy_esp32c3_mini.menu.DebugLevel.debug=Debug
+upesy_esp32c3_mini.menu.DebugLevel.debug.build.code_debug=4
+upesy_esp32c3_mini.menu.DebugLevel.verbose=Verbose
+upesy_esp32c3_mini.menu.DebugLevel.verbose.build.code_debug=5
+
+upesy_esp32c3_mini.menu.EraseFlash.none=Disabled
+upesy_esp32c3_mini.menu.EraseFlash.none.upload.erase_cmd=
+upesy_esp32c3_mini.menu.EraseFlash.all=Enabled
+upesy_esp32c3_mini.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+upesy_esp32s3_basic.name=uPesy ESP32S3 Basic
+upesy_esp32s3_basic.vid.0=0x303a
+upesy_esp32s3_basic.pid.0=0x8192
+
+upesy_esp32s3_basic.bootloader.tool=esptool_py
+upesy_esp32s3_basic.bootloader.tool.default=esptool_py
+
+upesy_esp32s3_basic.upload.tool=esptool_py
+upesy_esp32s3_basic.upload.tool.default=esptool_py
+upesy_esp32s3_basic.upload.tool.network=esp_ota
+
+upesy_esp32s3_basic.upload.maximum_size=1310720
+upesy_esp32s3_basic.upload.maximum_data_size=327680
+upesy_esp32s3_basic.upload.flags=
+upesy_esp32s3_basic.upload.extra_flags=
+upesy_esp32s3_basic.upload.use_1200bps_touch=false
+upesy_esp32s3_basic.upload.wait_for_upload_port=false
+
+upesy_esp32s3_basic.serial.disableDTR=false
+upesy_esp32s3_basic.serial.disableRTS=false
+
+upesy_esp32s3_basic.build.tarch=xtensa
+upesy_esp32s3_basic.build.bootloader_addr=0x0
+upesy_esp32s3_basic.build.target=esp32s3
+upesy_esp32s3_basic.build.mcu=esp32s3
+upesy_esp32s3_basic.build.core=esp32
+upesy_esp32s3_basic.build.variant=uPesy_esp32s3_basic
+upesy_esp32s3_basic.build.board=UPESY_ESP32S3_BASIC
+
+upesy_esp32s3_basic.build.usb_mode=1
+upesy_esp32s3_basic.build.cdc_on_boot=0
+upesy_esp32s3_basic.build.msc_on_boot=0
+upesy_esp32s3_basic.build.dfu_on_boot=0
+upesy_esp32s3_basic.build.f_cpu=240000000L
+upesy_esp32s3_basic.build.flash_size=16MB
+upesy_esp32s3_basic.build.flash_freq=80m
+upesy_esp32s3_basic.build.flash_mode=dio
+upesy_esp32s3_basic.build.boot=qio
+upesy_esp32s3_basic.build.boot_freq=80m
+upesy_esp32s3_basic.build.partitions=default
+upesy_esp32s3_basic.build.defines=-DBOARD_HAS_PSRAM
+upesy_esp32s3_basic.build.loop_core=
+upesy_esp32s3_basic.build.event_core=
+upesy_esp32s3_basic.build.psram_type=opi
+upesy_esp32s3_basic.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+upesy_esp32s3_basic.menu.JTAGAdapter.default=Disabled
+upesy_esp32s3_basic.menu.JTAGAdapter.default.build.copy_jtag_files=0
+upesy_esp32s3_basic.menu.JTAGAdapter.builtin=Integrated USB JTAG
+upesy_esp32s3_basic.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+upesy_esp32s3_basic.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+upesy_esp32s3_basic.menu.JTAGAdapter.external=FTDI Adapter
+upesy_esp32s3_basic.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+upesy_esp32s3_basic.menu.JTAGAdapter.external.build.copy_jtag_files=1
+upesy_esp32s3_basic.menu.JTAGAdapter.bridge=ESP USB Bridge
+upesy_esp32s3_basic.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+upesy_esp32s3_basic.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+upesy_esp32s3_basic.menu.FlashMode.qio=QIO 80MHz
+upesy_esp32s3_basic.menu.FlashMode.qio.build.flash_mode=dio
+upesy_esp32s3_basic.menu.FlashMode.qio.build.boot=qio
+upesy_esp32s3_basic.menu.FlashMode.qio.build.boot_freq=80m
+upesy_esp32s3_basic.menu.FlashMode.qio.build.flash_freq=80m
+upesy_esp32s3_basic.menu.FlashMode.qio120=QIO 120MHz
+upesy_esp32s3_basic.menu.FlashMode.qio120.build.flash_mode=dio
+upesy_esp32s3_basic.menu.FlashMode.qio120.build.boot=qio
+upesy_esp32s3_basic.menu.FlashMode.qio120.build.boot_freq=120m
+upesy_esp32s3_basic.menu.FlashMode.qio120.build.flash_freq=80m
+
+upesy_esp32s3_basic.menu.LoopCore.1=Core 1
+upesy_esp32s3_basic.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+upesy_esp32s3_basic.menu.LoopCore.0=Core 0
+upesy_esp32s3_basic.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+upesy_esp32s3_basic.menu.EventsCore.1=Core 1
+upesy_esp32s3_basic.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+upesy_esp32s3_basic.menu.EventsCore.0=Core 0
+upesy_esp32s3_basic.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+upesy_esp32s3_basic.menu.USBMode.hwcdc=Hardware CDC and JTAG
+upesy_esp32s3_basic.menu.USBMode.hwcdc.build.usb_mode=1
+upesy_esp32s3_basic.menu.USBMode.default=USB-OTG (TinyUSB)
+upesy_esp32s3_basic.menu.USBMode.default.build.usb_mode=0
+
+upesy_esp32s3_basic.menu.CDCOnBoot.default=Disabled
+upesy_esp32s3_basic.menu.CDCOnBoot.default.build.cdc_on_boot=0
+upesy_esp32s3_basic.menu.CDCOnBoot.cdc=Enabled
+upesy_esp32s3_basic.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+upesy_esp32s3_basic.menu.MSCOnBoot.default=Disabled
+upesy_esp32s3_basic.menu.MSCOnBoot.default.build.msc_on_boot=0
+upesy_esp32s3_basic.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+upesy_esp32s3_basic.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+upesy_esp32s3_basic.menu.DFUOnBoot.default=Disabled
+upesy_esp32s3_basic.menu.DFUOnBoot.default.build.dfu_on_boot=0
+upesy_esp32s3_basic.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+upesy_esp32s3_basic.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+upesy_esp32s3_basic.menu.UploadMode.default=UART0 / Hardware CDC
+upesy_esp32s3_basic.menu.UploadMode.default.upload.use_1200bps_touch=false
+upesy_esp32s3_basic.menu.UploadMode.default.upload.wait_for_upload_port=false
+upesy_esp32s3_basic.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+upesy_esp32s3_basic.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+upesy_esp32s3_basic.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+upesy_esp32s3_basic.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+upesy_esp32s3_basic.menu.PartitionScheme.fatflash.build.partitions=ffat
+upesy_esp32s3_basic.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+upesy_esp32s3_basic.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+upesy_esp32s3_basic.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+upesy_esp32s3_basic.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+upesy_esp32s3_basic.menu.CPUFreq.240=240MHz (WiFi)
+upesy_esp32s3_basic.menu.CPUFreq.240.build.f_cpu=240000000L
+upesy_esp32s3_basic.menu.CPUFreq.160=160MHz (WiFi)
+upesy_esp32s3_basic.menu.CPUFreq.160.build.f_cpu=160000000L
+upesy_esp32s3_basic.menu.CPUFreq.80=80MHz (WiFi)
+upesy_esp32s3_basic.menu.CPUFreq.80.build.f_cpu=80000000L
+upesy_esp32s3_basic.menu.CPUFreq.40=40MHz
+upesy_esp32s3_basic.menu.CPUFreq.40.build.f_cpu=40000000L
+upesy_esp32s3_basic.menu.CPUFreq.20=20MHz
+upesy_esp32s3_basic.menu.CPUFreq.20.build.f_cpu=20000000L
+upesy_esp32s3_basic.menu.CPUFreq.10=10MHz
+upesy_esp32s3_basic.menu.CPUFreq.10.build.f_cpu=10000000L
+
+upesy_esp32s3_basic.menu.UploadSpeed.921600=921600
+upesy_esp32s3_basic.menu.UploadSpeed.921600.upload.speed=921600
+upesy_esp32s3_basic.menu.UploadSpeed.115200=115200
+upesy_esp32s3_basic.menu.UploadSpeed.115200.upload.speed=115200
+upesy_esp32s3_basic.menu.UploadSpeed.256000.windows=256000
+upesy_esp32s3_basic.menu.UploadSpeed.256000.upload.speed=256000
+upesy_esp32s3_basic.menu.UploadSpeed.230400.windows.upload.speed=256000
+upesy_esp32s3_basic.menu.UploadSpeed.230400=230400
+upesy_esp32s3_basic.menu.UploadSpeed.230400.upload.speed=230400
+upesy_esp32s3_basic.menu.UploadSpeed.460800.linux=460800
+upesy_esp32s3_basic.menu.UploadSpeed.460800.macosx=460800
+upesy_esp32s3_basic.menu.UploadSpeed.460800.upload.speed=460800
+upesy_esp32s3_basic.menu.UploadSpeed.512000.windows=512000
+upesy_esp32s3_basic.menu.UploadSpeed.512000.upload.speed=512000
+
+upesy_esp32s3_basic.menu.DebugLevel.none=None
+upesy_esp32s3_basic.menu.DebugLevel.none.build.code_debug=0
+upesy_esp32s3_basic.menu.DebugLevel.error=Error
+upesy_esp32s3_basic.menu.DebugLevel.error.build.code_debug=1
+upesy_esp32s3_basic.menu.DebugLevel.warn=Warn
+upesy_esp32s3_basic.menu.DebugLevel.warn.build.code_debug=2
+upesy_esp32s3_basic.menu.DebugLevel.info=Info
+upesy_esp32s3_basic.menu.DebugLevel.info.build.code_debug=3
+upesy_esp32s3_basic.menu.DebugLevel.debug=Debug
+upesy_esp32s3_basic.menu.DebugLevel.debug.build.code_debug=4
+upesy_esp32s3_basic.menu.DebugLevel.verbose=Verbose
+upesy_esp32s3_basic.menu.DebugLevel.verbose.build.code_debug=5
+
+upesy_esp32s3_basic.menu.EraseFlash.none=Disabled
+upesy_esp32s3_basic.menu.EraseFlash.none.upload.erase_cmd=
+upesy_esp32s3_basic.menu.EraseFlash.all=Enabled
+upesy_esp32s3_basic.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+kb32.name=KB32-FT
+
+kb32.bootloader.tool=esptool_py
+kb32.bootloader.tool.default=esptool_py
+
+kb32.upload.tool=esptool_py
+kb32.upload.tool.default=esptool_py
+kb32.upload.tool.network=esp_ota
+
+kb32.upload.maximum_size=1310720
+kb32.upload.maximum_data_size=327680
+kb32.upload.flags=
+kb32.upload.extra_flags=
+
+kb32.serial.disableDTR=true
+kb32.serial.disableRTS=true
+
+kb32.build.tarch=xtensa
+kb32.build.bootloader_addr=0x1000
+kb32.build.target=esp32
+kb32.build.mcu=esp32
+kb32.build.core=esp32
+kb32.build.variant=esp32
+kb32.build.board=ESP32_DEV
+
+kb32.build.f_cpu=240000000L
+kb32.build.flash_size=4MB
+kb32.build.flash_freq=40m
+kb32.build.flash_mode=dio
+kb32.build.boot=dio
+kb32.build.partitions=default
+kb32.build.defines=
+kb32.build.loop_core=
+kb32.build.event_core=
+
+kb32.menu.PSRAM.disabled=Disabled
+kb32.menu.PSRAM.disabled.build.defines=
+kb32.menu.PSRAM.disabled.build.extra_libs=
+kb32.menu.PSRAM.enabled=Enabled
+kb32.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+kb32.menu.PSRAM.enabled.build.extra_libs=
+
+kb32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+kb32.menu.PartitionScheme.default.build.partitions=default
+kb32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+kb32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+kb32.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+kb32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+kb32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+kb32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+kb32.menu.PartitionScheme.minimal.build.partitions=minimal
+kb32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+kb32.menu.PartitionScheme.no_ota.build.partitions=no_ota
+kb32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+kb32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+kb32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+kb32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+kb32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+kb32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+kb32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+kb32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+kb32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+kb32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+kb32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+kb32.menu.PartitionScheme.huge_app.build.partitions=huge_app
+kb32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+kb32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+kb32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+kb32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+kb32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+kb32.menu.PartitionScheme.fatflash.build.partitions=ffat
+kb32.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+kb32.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+kb32.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+kb32.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+kb32.menu.PartitionScheme.rainmaker=RainMaker 4MB
+kb32.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+kb32.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+kb32.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+kb32.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+kb32.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+kb32.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+kb32.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+kb32.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+kb32.menu.CPUFreq.240=240MHz (WiFi/BT)
+kb32.menu.CPUFreq.240.build.f_cpu=240000000L
+kb32.menu.CPUFreq.160=160MHz (WiFi/BT)
+kb32.menu.CPUFreq.160.build.f_cpu=160000000L
+kb32.menu.CPUFreq.80=80MHz (WiFi/BT)
+kb32.menu.CPUFreq.80.build.f_cpu=80000000L
+kb32.menu.CPUFreq.40=40MHz (40MHz XTAL)
+kb32.menu.CPUFreq.40.build.f_cpu=40000000L
+kb32.menu.CPUFreq.26=26MHz (26MHz XTAL)
+kb32.menu.CPUFreq.26.build.f_cpu=26000000L
+kb32.menu.CPUFreq.20=20MHz (40MHz XTAL)
+kb32.menu.CPUFreq.20.build.f_cpu=20000000L
+kb32.menu.CPUFreq.13=13MHz (26MHz XTAL)
+kb32.menu.CPUFreq.13.build.f_cpu=13000000L
+kb32.menu.CPUFreq.10=10MHz (40MHz XTAL)
+kb32.menu.CPUFreq.10.build.f_cpu=10000000L
+
+kb32.menu.FlashMode.qio=QIO
+kb32.menu.FlashMode.qio.build.flash_mode=dio
+kb32.menu.FlashMode.qio.build.boot=qio
+kb32.menu.FlashMode.dio=DIO
+kb32.menu.FlashMode.dio.build.flash_mode=dio
+kb32.menu.FlashMode.dio.build.boot=dio
+
+kb32.menu.FlashFreq.80=80MHz
+kb32.menu.FlashFreq.80.build.flash_freq=80m
+kb32.menu.FlashFreq.40=40MHz
+kb32.menu.FlashFreq.40.build.flash_freq=40m
+
+kb32.menu.FlashSize.4M=4MB (32Mb)
+kb32.menu.FlashSize.4M.build.flash_size=4MB
+kb32.menu.FlashSize.8M=8MB (64Mb)
+kb32.menu.FlashSize.8M.build.flash_size=8MB
+kb32.menu.FlashSize.2M=2MB (16Mb)
+kb32.menu.FlashSize.2M.build.flash_size=2MB
+kb32.menu.FlashSize.16M=16MB (128Mb)
+kb32.menu.FlashSize.16M.build.flash_size=16MB
+
+kb32.menu.UploadSpeed.921600=921600
+kb32.menu.UploadSpeed.921600.upload.speed=921600
+kb32.menu.UploadSpeed.115200=115200
+kb32.menu.UploadSpeed.115200.upload.speed=115200
+kb32.menu.UploadSpeed.256000.windows=256000
+kb32.menu.UploadSpeed.256000.upload.speed=256000
+kb32.menu.UploadSpeed.230400.windows.upload.speed=256000
+kb32.menu.UploadSpeed.230400=230400
+kb32.menu.UploadSpeed.230400.upload.speed=230400
+kb32.menu.UploadSpeed.460800.linux=460800
+kb32.menu.UploadSpeed.460800.macosx=460800
+kb32.menu.UploadSpeed.460800.upload.speed=460800
+kb32.menu.UploadSpeed.512000.windows=512000
+kb32.menu.UploadSpeed.512000.upload.speed=512000
+
+kb32.menu.LoopCore.1=Core 1
+kb32.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+kb32.menu.LoopCore.0=Core 0
+kb32.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+kb32.menu.EventsCore.1=Core 1
+kb32.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+kb32.menu.EventsCore.0=Core 0
+kb32.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+kb32.menu.DebugLevel.none=None
+kb32.menu.DebugLevel.none.build.code_debug=0
+kb32.menu.DebugLevel.error=Error
+kb32.menu.DebugLevel.error.build.code_debug=1
+kb32.menu.DebugLevel.warn=Warn
+kb32.menu.DebugLevel.warn.build.code_debug=2
+kb32.menu.DebugLevel.info=Info
+kb32.menu.DebugLevel.info.build.code_debug=3
+kb32.menu.DebugLevel.debug=Debug
+kb32.menu.DebugLevel.debug.build.code_debug=4
+kb32.menu.DebugLevel.verbose=Verbose
+kb32.menu.DebugLevel.verbose.build.code_debug=5
+
+kb32.menu.EraseFlash.none=Disabled
+kb32.menu.EraseFlash.none.upload.erase_cmd=
+kb32.menu.EraseFlash.all=Enabled
+kb32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+deneyapkart.name=Deneyap Kart
+
+deneyapkart.bootloader.tool=esptool_py
+deneyapkart.bootloader.tool.default=esptool_py
+
+deneyapkart.upload.tool=esptool_py
+deneyapkart.upload.tool.default=esptool_py
+deneyapkart.upload.tool.network=esp_ota
+
+deneyapkart.upload.maximum_size=1310720
+deneyapkart.upload.maximum_data_size=327680
+deneyapkart.upload.flags=
+deneyapkart.upload.extra_flags=
+
+deneyapkart.serial.disableDTR=true
+deneyapkart.serial.disableRTS=true
+
+deneyapkart.build.tarch=xtensa
+deneyapkart.build.bootloader_addr=0x1000
+deneyapkart.build.target=esp32
+deneyapkart.build.mcu=esp32
+deneyapkart.build.core=esp32
+deneyapkart.build.variant=deneyapkart
+deneyapkart.build.board=DYDK
+
+deneyapkart.build.f_cpu=240000000L
+deneyapkart.build.flash_size=4MB
+deneyapkart.build.flash_freq=80m
+deneyapkart.build.flash_mode=dio
+deneyapkart.build.boot=qio
+deneyapkart.build.partitions=default
+deneyapkart.build.defines=
+deneyapkart.build.loop_core=
+deneyapkart.build.event_core=
+
+## IDE 2.0 Seems to not update the value
+deneyapkart.menu.JTAGAdapter.default=Disabled
+deneyapkart.menu.JTAGAdapter.default.build.copy_jtag_files=0
+deneyapkart.menu.JTAGAdapter.external=FTDI Adapter
+deneyapkart.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg
+deneyapkart.menu.JTAGAdapter.external.build.copy_jtag_files=1
+deneyapkart.menu.JTAGAdapter.bridge=ESP USB Bridge
+deneyapkart.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg
+deneyapkart.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+deneyapkart.menu.PSRAM.enabled=Enabled
+deneyapkart.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+deneyapkart.menu.PSRAM.enabled.build.extra_libs=
+deneyapkart.menu.PSRAM.disabled=Disabled
+deneyapkart.menu.PSRAM.disabled.build.defines=
+deneyapkart.menu.PSRAM.disabled.build.extra_libs=
+
+deneyapkart.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+deneyapkart.menu.PartitionScheme.default.build.partitions=default
+deneyapkart.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+deneyapkart.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+deneyapkart.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+deneyapkart.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+deneyapkart.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+deneyapkart.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+deneyapkart.menu.PartitionScheme.minimal.build.partitions=minimal
+deneyapkart.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+deneyapkart.menu.PartitionScheme.no_ota.build.partitions=no_ota
+deneyapkart.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+deneyapkart.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+deneyapkart.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+deneyapkart.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+deneyapkart.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+deneyapkart.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+deneyapkart.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+deneyapkart.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+deneyapkart.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+deneyapkart.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+deneyapkart.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+deneyapkart.menu.PartitionScheme.huge_app.build.partitions=huge_app
+deneyapkart.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+deneyapkart.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+deneyapkart.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+deneyapkart.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+deneyapkart.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+deneyapkart.menu.PartitionScheme.fatflash.build.partitions=ffat
+deneyapkart.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+deneyapkart.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+deneyapkart.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+deneyapkart.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+deneyapkart.menu.PartitionScheme.rainmaker=RainMaker 4MB
+deneyapkart.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+deneyapkart.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+deneyapkart.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+deneyapkart.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+deneyapkart.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+deneyapkart.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+deneyapkart.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+deneyapkart.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+deneyapkart.menu.CPUFreq.240=240MHz (WiFi/BT)
+deneyapkart.menu.CPUFreq.240.build.f_cpu=240000000L
+deneyapkart.menu.CPUFreq.160=160MHz (WiFi/BT)
+deneyapkart.menu.CPUFreq.160.build.f_cpu=160000000L
+deneyapkart.menu.CPUFreq.80=80MHz (WiFi/BT)
+deneyapkart.menu.CPUFreq.80.build.f_cpu=80000000L
+deneyapkart.menu.CPUFreq.40=40MHz (40MHz XTAL)
+deneyapkart.menu.CPUFreq.40.build.f_cpu=40000000L
+deneyapkart.menu.CPUFreq.26=26MHz (26MHz XTAL)
+deneyapkart.menu.CPUFreq.26.build.f_cpu=26000000L
+deneyapkart.menu.CPUFreq.20=20MHz (40MHz XTAL)
+deneyapkart.menu.CPUFreq.20.build.f_cpu=20000000L
+deneyapkart.menu.CPUFreq.13=13MHz (26MHz XTAL)
+deneyapkart.menu.CPUFreq.13.build.f_cpu=13000000L
+deneyapkart.menu.CPUFreq.10=10MHz (40MHz XTAL)
+deneyapkart.menu.CPUFreq.10.build.f_cpu=10000000L
+
+deneyapkart.menu.FlashMode.qio=QIO
+deneyapkart.menu.FlashMode.qio.build.flash_mode=dio
+deneyapkart.menu.FlashMode.qio.build.boot=qio
+deneyapkart.menu.FlashMode.dio=DIO
+deneyapkart.menu.FlashMode.dio.build.flash_mode=dio
+deneyapkart.menu.FlashMode.dio.build.boot=dio
+
+deneyapkart.menu.FlashFreq.80=80MHz
+deneyapkart.menu.FlashFreq.80.build.flash_freq=80m
+deneyapkart.menu.FlashFreq.40=40MHz
+deneyapkart.menu.FlashFreq.40.build.flash_freq=40m
+
+deneyapkart.menu.FlashSize.4M=4MB (32Mb)
+deneyapkart.menu.FlashSize.4M.build.flash_size=4MB
+deneyapkart.menu.FlashSize.8M=8MB (64Mb)
+deneyapkart.menu.FlashSize.8M.build.flash_size=8MB
+deneyapkart.menu.FlashSize.2M=2MB (16Mb)
+deneyapkart.menu.FlashSize.2M.build.flash_size=2MB
+deneyapkart.menu.FlashSize.16M=16MB (128Mb)
+deneyapkart.menu.FlashSize.16M.build.flash_size=16MB
+
+deneyapkart.menu.UploadSpeed.921600=921600
+deneyapkart.menu.UploadSpeed.921600.upload.speed=921600
+deneyapkart.menu.UploadSpeed.115200=115200
+deneyapkart.menu.UploadSpeed.115200.upload.speed=115200
+deneyapkart.menu.UploadSpeed.256000.windows=256000
+deneyapkart.menu.UploadSpeed.256000.upload.speed=256000
+deneyapkart.menu.UploadSpeed.230400.windows.upload.speed=256000
+deneyapkart.menu.UploadSpeed.230400=230400
+deneyapkart.menu.UploadSpeed.230400.upload.speed=230400
+deneyapkart.menu.UploadSpeed.460800.linux=460800
+deneyapkart.menu.UploadSpeed.460800.macosx=460800
+deneyapkart.menu.UploadSpeed.460800.upload.speed=460800
+deneyapkart.menu.UploadSpeed.512000.windows=512000
+deneyapkart.menu.UploadSpeed.512000.upload.speed=512000
+
+deneyapkart.menu.LoopCore.1=Core 1
+deneyapkart.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+deneyapkart.menu.LoopCore.0=Core 0
+deneyapkart.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+deneyapkart.menu.EventsCore.1=Core 1
+deneyapkart.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+deneyapkart.menu.EventsCore.0=Core 0
+deneyapkart.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+deneyapkart.menu.DebugLevel.none=None
+deneyapkart.menu.DebugLevel.none.build.code_debug=0
+deneyapkart.menu.DebugLevel.error=Error
+deneyapkart.menu.DebugLevel.error.build.code_debug=1
+deneyapkart.menu.DebugLevel.warn=Warn
+deneyapkart.menu.DebugLevel.warn.build.code_debug=2
+deneyapkart.menu.DebugLevel.info=Info
+deneyapkart.menu.DebugLevel.info.build.code_debug=3
+deneyapkart.menu.DebugLevel.debug=Debug
+deneyapkart.menu.DebugLevel.debug.build.code_debug=4
+deneyapkart.menu.DebugLevel.verbose=Verbose
+deneyapkart.menu.DebugLevel.verbose.build.code_debug=5
+
+deneyapkart.menu.EraseFlash.none=Disabled
+deneyapkart.menu.EraseFlash.none.upload.erase_cmd=
+deneyapkart.menu.EraseFlash.all=Enabled
+deneyapkart.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+deneyapkart1A.name=Deneyap Kart 1A
+
+deneyapkart1A.bootloader.tool=esptool_py
+deneyapkart1A.bootloader.tool.default=esptool_py
+
+deneyapkart1A.upload.tool=esptool_py
+deneyapkart1A.upload.tool.default=esptool_py
+deneyapkart1A.upload.tool.network=esp_ota
+
+deneyapkart1A.upload.maximum_size=1310720
+deneyapkart1A.upload.maximum_data_size=327680
+deneyapkart1A.upload.flags=
+deneyapkart1A.upload.extra_flags=
+
+deneyapkart1A.serial.disableDTR=true
+deneyapkart1A.serial.disableRTS=true
+
+deneyapkart1A.build.tarch=xtensa
+deneyapkart1A.build.bootloader_addr=0x1000
+deneyapkart1A.build.target=esp32
+deneyapkart1A.build.mcu=esp32
+deneyapkart1A.build.core=esp32
+deneyapkart1A.build.variant=deneyapkart1A
+deneyapkart1A.build.board=DYDK1A
+
+deneyapkart1A.build.f_cpu=240000000L
+deneyapkart1A.build.flash_size=4MB
+deneyapkart1A.build.flash_freq=80m
+deneyapkart1A.build.flash_mode=dio
+deneyapkart1A.build.boot=qio
+deneyapkart1A.build.partitions=default
+deneyapkart1A.build.defines=
+deneyapkart1A.build.loop_core=
+deneyapkart1A.build.event_core=
+
+## IDE 2.0 Seems to not update the value
+deneyapkart1A.menu.JTAGAdapter.default=Disabled
+deneyapkart1A.menu.JTAGAdapter.default.build.copy_jtag_files=0
+deneyapkart1A.menu.JTAGAdapter.external=FTDI Adapter
+deneyapkart1A.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg
+deneyapkart1A.menu.JTAGAdapter.external.build.copy_jtag_files=1
+deneyapkart1A.menu.JTAGAdapter.bridge=ESP USB Bridge
+deneyapkart1A.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg
+deneyapkart1A.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+deneyapkart1A.menu.PSRAM.enabled=Enabled
+deneyapkart1A.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+deneyapkart1A.menu.PSRAM.enabled.build.extra_libs=
+deneyapkart1A.menu.PSRAM.disabled=Disabled
+deneyapkart1A.menu.PSRAM.disabled.build.defines=
+deneyapkart1A.menu.PSRAM.disabled.build.extra_libs=
+
+deneyapkart1A.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+deneyapkart1A.menu.PartitionScheme.default.build.partitions=default
+deneyapkart1A.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+deneyapkart1A.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+deneyapkart1A.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+deneyapkart1A.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+deneyapkart1A.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+deneyapkart1A.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+deneyapkart1A.menu.PartitionScheme.minimal.build.partitions=minimal
+deneyapkart1A.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+deneyapkart1A.menu.PartitionScheme.no_ota.build.partitions=no_ota
+deneyapkart1A.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+deneyapkart1A.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+deneyapkart1A.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+deneyapkart1A.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+deneyapkart1A.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+deneyapkart1A.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+deneyapkart1A.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+deneyapkart1A.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+deneyapkart1A.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+deneyapkart1A.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+deneyapkart1A.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+deneyapkart1A.menu.PartitionScheme.huge_app.build.partitions=huge_app
+deneyapkart1A.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+deneyapkart1A.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+deneyapkart1A.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+deneyapkart1A.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+deneyapkart1A.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+deneyapkart1A.menu.PartitionScheme.fatflash.build.partitions=ffat
+deneyapkart1A.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+deneyapkart1A.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+deneyapkart1A.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+deneyapkart1A.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+deneyapkart1A.menu.PartitionScheme.rainmaker=RainMaker 4MB
+deneyapkart1A.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+deneyapkart1A.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+deneyapkart1A.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+deneyapkart1A.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+deneyapkart1A.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+deneyapkart1A.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+deneyapkart1A.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+deneyapkart1A.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+deneyapkart1A.menu.CPUFreq.240=240MHz (WiFi/BT)
+deneyapkart1A.menu.CPUFreq.240.build.f_cpu=240000000L
+deneyapkart1A.menu.CPUFreq.160=160MHz (WiFi/BT)
+deneyapkart1A.menu.CPUFreq.160.build.f_cpu=160000000L
+deneyapkart1A.menu.CPUFreq.80=80MHz (WiFi/BT)
+deneyapkart1A.menu.CPUFreq.80.build.f_cpu=80000000L
+deneyapkart1A.menu.CPUFreq.40=40MHz (40MHz XTAL)
+deneyapkart1A.menu.CPUFreq.40.build.f_cpu=40000000L
+deneyapkart1A.menu.CPUFreq.26=26MHz (26MHz XTAL)
+deneyapkart1A.menu.CPUFreq.26.build.f_cpu=26000000L
+deneyapkart1A.menu.CPUFreq.20=20MHz (40MHz XTAL)
+deneyapkart1A.menu.CPUFreq.20.build.f_cpu=20000000L
+deneyapkart1A.menu.CPUFreq.13=13MHz (26MHz XTAL)
+deneyapkart1A.menu.CPUFreq.13.build.f_cpu=13000000L
+deneyapkart1A.menu.CPUFreq.10=10MHz (40MHz XTAL)
+deneyapkart1A.menu.CPUFreq.10.build.f_cpu=10000000L
+
+deneyapkart1A.menu.FlashMode.qio=QIO
+deneyapkart1A.menu.FlashMode.qio.build.flash_mode=dio
+deneyapkart1A.menu.FlashMode.qio.build.boot=qio
+deneyapkart1A.menu.FlashMode.dio=DIO
+deneyapkart1A.menu.FlashMode.dio.build.flash_mode=dio
+deneyapkart1A.menu.FlashMode.dio.build.boot=dio
+
+deneyapkart1A.menu.FlashFreq.80=80MHz
+deneyapkart1A.menu.FlashFreq.80.build.flash_freq=80m
+deneyapkart1A.menu.FlashFreq.40=40MHz
+deneyapkart1A.menu.FlashFreq.40.build.flash_freq=40m
+
+deneyapkart1A.menu.FlashSize.4M=4MB (32Mb)
+deneyapkart1A.menu.FlashSize.4M.build.flash_size=4MB
+deneyapkart1A.menu.FlashSize.8M=8MB (64Mb)
+deneyapkart1A.menu.FlashSize.8M.build.flash_size=8MB
+deneyapkart1A.menu.FlashSize.2M=2MB (16Mb)
+deneyapkart1A.menu.FlashSize.2M.build.flash_size=2MB
+deneyapkart1A.menu.FlashSize.16M=16MB (128Mb)
+deneyapkart1A.menu.FlashSize.16M.build.flash_size=16MB
+
+deneyapkart1A.menu.UploadSpeed.921600=921600
+deneyapkart1A.menu.UploadSpeed.921600.upload.speed=921600
+deneyapkart1A.menu.UploadSpeed.115200=115200
+deneyapkart1A.menu.UploadSpeed.115200.upload.speed=115200
+deneyapkart1A.menu.UploadSpeed.256000.windows=256000
+deneyapkart1A.menu.UploadSpeed.256000.upload.speed=256000
+deneyapkart1A.menu.UploadSpeed.230400.windows.upload.speed=256000
+deneyapkart1A.menu.UploadSpeed.230400=230400
+deneyapkart1A.menu.UploadSpeed.230400.upload.speed=230400
+deneyapkart1A.menu.UploadSpeed.460800.linux=460800
+deneyapkart1A.menu.UploadSpeed.460800.macosx=460800
+deneyapkart1A.menu.UploadSpeed.460800.upload.speed=460800
+deneyapkart1A.menu.UploadSpeed.512000.windows=512000
+deneyapkart1A.menu.UploadSpeed.512000.upload.speed=512000
+
+deneyapkart1A.menu.LoopCore.1=Core 1
+deneyapkart1A.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+deneyapkart1A.menu.LoopCore.0=Core 0
+deneyapkart1A.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+deneyapkart1A.menu.EventsCore.1=Core 1
+deneyapkart1A.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+deneyapkart1A.menu.EventsCore.0=Core 0
+deneyapkart1A.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+deneyapkart1A.menu.DebugLevel.none=None
+deneyapkart1A.menu.DebugLevel.none.build.code_debug=0
+deneyapkart1A.menu.DebugLevel.error=Error
+deneyapkart1A.menu.DebugLevel.error.build.code_debug=1
+deneyapkart1A.menu.DebugLevel.warn=Warn
+deneyapkart1A.menu.DebugLevel.warn.build.code_debug=2
+deneyapkart1A.menu.DebugLevel.info=Info
+deneyapkart1A.menu.DebugLevel.info.build.code_debug=3
+deneyapkart1A.menu.DebugLevel.debug=Debug
+deneyapkart1A.menu.DebugLevel.debug.build.code_debug=4
+deneyapkart1A.menu.DebugLevel.verbose=Verbose
+deneyapkart1A.menu.DebugLevel.verbose.build.code_debug=5
+
+deneyapkart1A.menu.EraseFlash.none=Disabled
+deneyapkart1A.menu.EraseFlash.none.upload.erase_cmd=
+deneyapkart1A.menu.EraseFlash.all=Enabled
+deneyapkart1A.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+deneyapkart1Av2.name=Deneyap Kart 1A v2
+
+deneyapkart1Av2.vid.0=0x303a
+deneyapkart1Av2.pid.0=0x8147
+
+deneyapkart1Av2.bootloader.tool=esptool_py
+deneyapkart1Av2.bootloader.tool.default=esptool_py
+
+deneyapkart1Av2.upload.tool=esptool_py
+deneyapkart1Av2.upload.tool.default=esptool_py
+deneyapkart1Av2.upload.tool.network=esp_ota
+
+deneyapkart1Av2.upload.maximum_size=1310720
+deneyapkart1Av2.upload.maximum_data_size=327680
+deneyapkart1Av2.upload.flags=
+deneyapkart1Av2.upload.extra_flags=
+deneyapkart1Av2.upload.use_1200bps_touch=false
+deneyapkart1Av2.upload.wait_for_upload_port=false
+
+deneyapkart1Av2.serial.disableDTR=false
+deneyapkart1Av2.serial.disableRTS=false
+
+deneyapkart1Av2.build.tarch=xtensa
+deneyapkart1Av2.build.bootloader_addr=0x0
+deneyapkart1Av2.build.target=esp32s3
+deneyapkart1Av2.build.mcu=esp32s3
+deneyapkart1Av2.build.core=esp32
+deneyapkart1Av2.build.variant=deneyapkart1Av2
+deneyapkart1Av2.build.board=DYDK1Av2
+
+deneyapkart1Av2.build.usb_mode=1
+deneyapkart1Av2.build.cdc_on_boot=1
+deneyapkart1Av2.build.msc_on_boot=0
+deneyapkart1Av2.build.dfu_on_boot=0
+deneyapkart1Av2.build.f_cpu=240000000L
+deneyapkart1Av2.build.flash_size=4MB
+deneyapkart1Av2.build.flash_freq=80m
+deneyapkart1Av2.build.flash_mode=dio
+deneyapkart1Av2.build.boot=qio
+deneyapkart1Av2.build.boot_freq=80m
+deneyapkart1Av2.build.partitions=default
+deneyapkart1Av2.build.defines=-DBOARD_HAS_PSRAM
+deneyapkart1Av2.build.loop_core=
+deneyapkart1Av2.build.event_core=
+deneyapkart1Av2.build.psram_type=opi
+deneyapkart1Av2.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+deneyapkart1Av2.menu.JTAGAdapter.default=Disabled
+deneyapkart1Av2.menu.JTAGAdapter.default.build.copy_jtag_files=0
+deneyapkart1Av2.menu.JTAGAdapter.builtin=Integrated USB JTAG
+deneyapkart1Av2.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+deneyapkart1Av2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+deneyapkart1Av2.menu.JTAGAdapter.external=FTDI Adapter
+deneyapkart1Av2.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+deneyapkart1Av2.menu.JTAGAdapter.external.build.copy_jtag_files=1
+deneyapkart1Av2.menu.JTAGAdapter.bridge=ESP USB Bridge
+deneyapkart1Av2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+deneyapkart1Av2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+deneyapkart1Av2.menu.PSRAM.opi=OPI PSRAM
+deneyapkart1Av2.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+deneyapkart1Av2.menu.PSRAM.opi.build.psram_type=opi
+deneyapkart1Av2.menu.PSRAM.disabled=Disabled
+deneyapkart1Av2.menu.PSRAM.disabled.build.defines=
+deneyapkart1Av2.menu.PSRAM.disabled.build.psram_type=qspi
+deneyapkart1Av2.menu.PSRAM.enabled=QSPI PSRAM
+deneyapkart1Av2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+deneyapkart1Av2.menu.PSRAM.enabled.build.psram_type=qspi
+
+deneyapkart1Av2.menu.FlashMode.qio=QIO 80MHz
+deneyapkart1Av2.menu.FlashMode.qio.build.flash_mode=dio
+deneyapkart1Av2.menu.FlashMode.qio.build.boot=qio
+deneyapkart1Av2.menu.FlashMode.qio.build.boot_freq=80m
+deneyapkart1Av2.menu.FlashMode.qio.build.flash_freq=80m
+deneyapkart1Av2.menu.FlashMode.qio120=QIO 120MHz
+deneyapkart1Av2.menu.FlashMode.qio120.build.flash_mode=dio
+deneyapkart1Av2.menu.FlashMode.qio120.build.boot=qio
+deneyapkart1Av2.menu.FlashMode.qio120.build.boot_freq=120m
+deneyapkart1Av2.menu.FlashMode.qio120.build.flash_freq=80m
+deneyapkart1Av2.menu.FlashMode.dio=DIO 80MHz
+deneyapkart1Av2.menu.FlashMode.dio.build.flash_mode=dio
+deneyapkart1Av2.menu.FlashMode.dio.build.boot=dio
+deneyapkart1Av2.menu.FlashMode.dio.build.boot_freq=80m
+deneyapkart1Av2.menu.FlashMode.dio.build.flash_freq=80m
+deneyapkart1Av2.menu.FlashMode.opi=OPI 80MHz
+deneyapkart1Av2.menu.FlashMode.opi.build.flash_mode=dout
+deneyapkart1Av2.menu.FlashMode.opi.build.boot=opi
+deneyapkart1Av2.menu.FlashMode.opi.build.boot_freq=80m
+deneyapkart1Av2.menu.FlashMode.opi.build.flash_freq=80m
+
+deneyapkart1Av2.menu.FlashSize.4M=4MB (32Mb)
+deneyapkart1Av2.menu.FlashSize.4M.build.flash_size=4MB
+deneyapkart1Av2.menu.FlashSize.8M=8MB (64Mb)
+deneyapkart1Av2.menu.FlashSize.8M.build.flash_size=8MB
+deneyapkart1Av2.menu.FlashSize.16M=16MB (128Mb)
+deneyapkart1Av2.menu.FlashSize.16M.build.flash_size=16MB
+#deneyapkart1Av2.menu.FlashSize.32M=32MB (256Mb)
+#deneyapkart1Av2.menu.FlashSize.32M.build.flash_size=32MB
+
+deneyapkart1Av2.menu.LoopCore.1=Core 1
+deneyapkart1Av2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+deneyapkart1Av2.menu.LoopCore.0=Core 0
+deneyapkart1Av2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+deneyapkart1Av2.menu.EventsCore.1=Core 1
+deneyapkart1Av2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+deneyapkart1Av2.menu.EventsCore.0=Core 0
+deneyapkart1Av2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+deneyapkart1Av2.menu.USBMode.hwcdc=Hardware CDC and JTAG
+deneyapkart1Av2.menu.USBMode.hwcdc.build.usb_mode=1
+deneyapkart1Av2.menu.USBMode.default=USB-OTG (TinyUSB)
+deneyapkart1Av2.menu.USBMode.default.build.usb_mode=0
+
+deneyapkart1Av2.menu.CDCOnBoot.cdc=Enabled
+deneyapkart1Av2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+deneyapkart1Av2.menu.CDCOnBoot.default=Disabled
+deneyapkart1Av2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+deneyapkart1Av2.menu.MSCOnBoot.default=Disabled
+deneyapkart1Av2.menu.MSCOnBoot.default.build.msc_on_boot=0
+deneyapkart1Av2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+deneyapkart1Av2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+deneyapkart1Av2.menu.DFUOnBoot.default=Disabled
+deneyapkart1Av2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+deneyapkart1Av2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+deneyapkart1Av2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+deneyapkart1Av2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+deneyapkart1Av2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+deneyapkart1Av2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+deneyapkart1Av2.menu.UploadMode.default=UART0 / Hardware CDC
+deneyapkart1Av2.menu.UploadMode.default.upload.use_1200bps_touch=false
+deneyapkart1Av2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+deneyapkart1Av2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+deneyapkart1Av2.menu.PartitionScheme.default.build.partitions=default
+deneyapkart1Av2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+deneyapkart1Av2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+deneyapkart1Av2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+deneyapkart1Av2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+deneyapkart1Av2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+deneyapkart1Av2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+deneyapkart1Av2.menu.PartitionScheme.minimal.build.partitions=minimal
+deneyapkart1Av2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+deneyapkart1Av2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+deneyapkart1Av2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+deneyapkart1Av2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+deneyapkart1Av2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+deneyapkart1Av2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+deneyapkart1Av2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+deneyapkart1Av2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+deneyapkart1Av2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+deneyapkart1Av2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+deneyapkart1Av2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+deneyapkart1Av2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+deneyapkart1Av2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+deneyapkart1Av2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+deneyapkart1Av2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+deneyapkart1Av2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+deneyapkart1Av2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+deneyapkart1Av2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+deneyapkart1Av2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+deneyapkart1Av2.menu.PartitionScheme.fatflash.build.partitions=ffat
+deneyapkart1Av2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+deneyapkart1Av2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+deneyapkart1Av2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+deneyapkart1Av2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+deneyapkart1Av2.menu.PartitionScheme.rainmaker=RainMaker 4MB
+deneyapkart1Av2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+deneyapkart1Av2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+deneyapkart1Av2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+deneyapkart1Av2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+deneyapkart1Av2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+deneyapkart1Av2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+deneyapkart1Av2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+deneyapkart1Av2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+deneyapkart1Av2.menu.CPUFreq.240=240MHz (WiFi)
+deneyapkart1Av2.menu.CPUFreq.240.build.f_cpu=240000000L
+deneyapkart1Av2.menu.CPUFreq.160=160MHz (WiFi)
+deneyapkart1Av2.menu.CPUFreq.160.build.f_cpu=160000000L
+deneyapkart1Av2.menu.CPUFreq.80=80MHz (WiFi)
+deneyapkart1Av2.menu.CPUFreq.80.build.f_cpu=80000000L
+deneyapkart1Av2.menu.CPUFreq.40=40MHz
+deneyapkart1Av2.menu.CPUFreq.40.build.f_cpu=40000000L
+deneyapkart1Av2.menu.CPUFreq.20=20MHz
+deneyapkart1Av2.menu.CPUFreq.20.build.f_cpu=20000000L
+deneyapkart1Av2.menu.CPUFreq.10=10MHz
+deneyapkart1Av2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+deneyapkart1Av2.menu.UploadSpeed.921600=921600
+deneyapkart1Av2.menu.UploadSpeed.921600.upload.speed=921600
+deneyapkart1Av2.menu.UploadSpeed.115200=115200
+deneyapkart1Av2.menu.UploadSpeed.115200.upload.speed=115200
+deneyapkart1Av2.menu.UploadSpeed.256000.windows=256000
+deneyapkart1Av2.menu.UploadSpeed.256000.upload.speed=256000
+deneyapkart1Av2.menu.UploadSpeed.230400.windows.upload.speed=256000
+deneyapkart1Av2.menu.UploadSpeed.230400=230400
+deneyapkart1Av2.menu.UploadSpeed.230400.upload.speed=230400
+deneyapkart1Av2.menu.UploadSpeed.460800.linux=460800
+deneyapkart1Av2.menu.UploadSpeed.460800.macosx=460800
+deneyapkart1Av2.menu.UploadSpeed.460800.upload.speed=460800
+deneyapkart1Av2.menu.UploadSpeed.512000.windows=512000
+deneyapkart1Av2.menu.UploadSpeed.512000.upload.speed=512000
+
+deneyapkart1Av2.menu.DebugLevel.none=None
+deneyapkart1Av2.menu.DebugLevel.none.build.code_debug=0
+deneyapkart1Av2.menu.DebugLevel.error=Error
+deneyapkart1Av2.menu.DebugLevel.error.build.code_debug=1
+deneyapkart1Av2.menu.DebugLevel.warn=Warn
+deneyapkart1Av2.menu.DebugLevel.warn.build.code_debug=2
+deneyapkart1Av2.menu.DebugLevel.info=Info
+deneyapkart1Av2.menu.DebugLevel.info.build.code_debug=3
+deneyapkart1Av2.menu.DebugLevel.debug=Debug
+deneyapkart1Av2.menu.DebugLevel.debug.build.code_debug=4
+deneyapkart1Av2.menu.DebugLevel.verbose=Verbose
+deneyapkart1Av2.menu.DebugLevel.verbose.build.code_debug=5
+
+deneyapkart1Av2.menu.EraseFlash.none=Disabled
+deneyapkart1Av2.menu.EraseFlash.none.upload.erase_cmd=
+deneyapkart1Av2.menu.EraseFlash.all=Enabled
+deneyapkart1Av2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+deneyapmini.name=Deneyap Mini
+
+deneyapmini.vid.0=0x303a
+deneyapmini.pid.0=0x8141
+
+deneyapmini.bootloader.tool=esptool_py
+deneyapmini.bootloader.tool.default=esptool_py
+
+deneyapmini.upload.tool=esptool_py
+deneyapmini.upload.tool.default=esptool_py
+deneyapmini.upload.tool.network=esp_ota
+
+deneyapmini.upload.maximum_size=1310720
+deneyapmini.upload.maximum_data_size=327680
+deneyapmini.upload.flags=
+deneyapmini.upload.extra_flags=
+deneyapmini.upload.use_1200bps_touch=false
+deneyapmini.upload.wait_for_upload_port=false
+
+deneyapmini.serial.disableDTR=false
+deneyapmini.serial.disableRTS=false
+
+deneyapmini.build.tarch=xtensa
+deneyapmini.build.bootloader_addr=0x1000
+deneyapmini.build.target=esp32s2
+deneyapmini.build.mcu=esp32s2
+deneyapmini.build.core=esp32
+deneyapmini.build.variant=deneyapmini
+deneyapmini.build.board=DYM
+
+deneyapmini.build.cdc_on_boot=1
+deneyapmini.build.msc_on_boot=0
+deneyapmini.build.dfu_on_boot=0
+deneyapmini.build.f_cpu=240000000L
+deneyapmini.build.flash_size=4MB
+deneyapmini.build.flash_freq=80m
+deneyapmini.build.flash_mode=dio
+deneyapmini.build.boot=qio
+deneyapmini.build.partitions=default
+deneyapmini.build.defines=
+
+## IDE 2.0 Seems to not update the value
+deneyapmini.menu.JTAGAdapter.default=Disabled
+deneyapmini.menu.JTAGAdapter.default.build.copy_jtag_files=0
+deneyapmini.menu.JTAGAdapter.external=FTDI Adapter
+deneyapmini.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg
+deneyapmini.menu.JTAGAdapter.external.build.copy_jtag_files=1
+deneyapmini.menu.JTAGAdapter.bridge=ESP USB Bridge
+deneyapmini.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg
+deneyapmini.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+deneyapmini.menu.CDCOnBoot.cdc=Enabled
+deneyapmini.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+deneyapmini.menu.CDCOnBoot.default=Disabled
+deneyapmini.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+deneyapmini.menu.MSCOnBoot.default=Disabled
+deneyapmini.menu.MSCOnBoot.default.build.msc_on_boot=0
+deneyapmini.menu.MSCOnBoot.msc=Enabled
+deneyapmini.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+deneyapmini.menu.DFUOnBoot.default=Disabled
+deneyapmini.menu.DFUOnBoot.default.build.dfu_on_boot=0
+deneyapmini.menu.DFUOnBoot.dfu=Enabled
+deneyapmini.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+deneyapmini.menu.UploadMode.cdc=Internal USB
+deneyapmini.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+deneyapmini.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+deneyapmini.menu.UploadMode.default=UART0
+deneyapmini.menu.UploadMode.default.upload.use_1200bps_touch=false
+deneyapmini.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+deneyapmini.menu.PSRAM.disabled=Disabled
+deneyapmini.menu.PSRAM.disabled.build.defines=
+deneyapmini.menu.PSRAM.enabled=Enabled
+deneyapmini.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+deneyapmini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+deneyapmini.menu.PartitionScheme.default.build.partitions=default
+deneyapmini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+deneyapmini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+deneyapmini.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+deneyapmini.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+deneyapmini.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+deneyapmini.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+deneyapmini.menu.PartitionScheme.minimal.build.partitions=minimal
+deneyapmini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+deneyapmini.menu.PartitionScheme.no_ota.build.partitions=no_ota
+deneyapmini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+deneyapmini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+deneyapmini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+deneyapmini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+deneyapmini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+deneyapmini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+deneyapmini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+deneyapmini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+deneyapmini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+deneyapmini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+deneyapmini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+deneyapmini.menu.PartitionScheme.huge_app.build.partitions=huge_app
+deneyapmini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+deneyapmini.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+deneyapmini.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+deneyapmini.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+deneyapmini.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+deneyapmini.menu.PartitionScheme.fatflash.build.partitions=ffat
+deneyapmini.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+deneyapmini.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+deneyapmini.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+deneyapmini.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+deneyapmini.menu.PartitionScheme.rainmaker=RainMaker 4MB
+deneyapmini.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+deneyapmini.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+deneyapmini.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+deneyapmini.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+deneyapmini.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+deneyapmini.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+deneyapmini.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+deneyapmini.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+deneyapmini.menu.CPUFreq.240=240MHz (WiFi)
+deneyapmini.menu.CPUFreq.240.build.f_cpu=240000000L
+deneyapmini.menu.CPUFreq.160=160MHz (WiFi)
+deneyapmini.menu.CPUFreq.160.build.f_cpu=160000000L
+deneyapmini.menu.CPUFreq.80=80MHz (WiFi)
+deneyapmini.menu.CPUFreq.80.build.f_cpu=80000000L
+deneyapmini.menu.CPUFreq.40=40MHz
+deneyapmini.menu.CPUFreq.40.build.f_cpu=40000000L
+deneyapmini.menu.CPUFreq.20=20MHz
+deneyapmini.menu.CPUFreq.20.build.f_cpu=20000000L
+deneyapmini.menu.CPUFreq.10=10MHz
+deneyapmini.menu.CPUFreq.10.build.f_cpu=10000000L
+
+deneyapmini.menu.FlashMode.qio=QIO
+deneyapmini.menu.FlashMode.qio.build.flash_mode=dio
+deneyapmini.menu.FlashMode.qio.build.boot=qio
+deneyapmini.menu.FlashMode.dio=DIO
+deneyapmini.menu.FlashMode.dio.build.flash_mode=dio
+deneyapmini.menu.FlashMode.dio.build.boot=dio
+
+deneyapmini.menu.FlashFreq.80=80MHz
+deneyapmini.menu.FlashFreq.80.build.flash_freq=80m
+deneyapmini.menu.FlashFreq.40=40MHz
+deneyapmini.menu.FlashFreq.40.build.flash_freq=40m
+
+deneyapmini.menu.FlashSize.4M=4MB (32Mb)
+deneyapmini.menu.FlashSize.4M.build.flash_size=4MB
+deneyapmini.menu.FlashSize.8M=8MB (64Mb)
+deneyapmini.menu.FlashSize.8M.build.flash_size=8MB
+deneyapmini.menu.FlashSize.2M=2MB (16Mb)
+deneyapmini.menu.FlashSize.2M.build.flash_size=2MB
+deneyapmini.menu.FlashSize.16M=16MB (128Mb)
+deneyapmini.menu.FlashSize.16M.build.flash_size=16MB
+
+deneyapmini.menu.UploadSpeed.921600=921600
+deneyapmini.menu.UploadSpeed.921600.upload.speed=921600
+deneyapmini.menu.UploadSpeed.115200=115200
+deneyapmini.menu.UploadSpeed.115200.upload.speed=115200
+deneyapmini.menu.UploadSpeed.256000.windows=256000
+deneyapmini.menu.UploadSpeed.256000.upload.speed=256000
+deneyapmini.menu.UploadSpeed.230400.windows.upload.speed=256000
+deneyapmini.menu.UploadSpeed.230400=230400
+deneyapmini.menu.UploadSpeed.230400.upload.speed=230400
+deneyapmini.menu.UploadSpeed.460800.linux=460800
+deneyapmini.menu.UploadSpeed.460800.macosx=460800
+deneyapmini.menu.UploadSpeed.460800.upload.speed=460800
+deneyapmini.menu.UploadSpeed.512000.windows=512000
+deneyapmini.menu.UploadSpeed.512000.upload.speed=512000
+
+deneyapmini.menu.DebugLevel.none=None
+deneyapmini.menu.DebugLevel.none.build.code_debug=0
+deneyapmini.menu.DebugLevel.error=Error
+deneyapmini.menu.DebugLevel.error.build.code_debug=1
+deneyapmini.menu.DebugLevel.warn=Warn
+deneyapmini.menu.DebugLevel.warn.build.code_debug=2
+deneyapmini.menu.DebugLevel.info=Info
+deneyapmini.menu.DebugLevel.info.build.code_debug=3
+deneyapmini.menu.DebugLevel.debug=Debug
+deneyapmini.menu.DebugLevel.debug.build.code_debug=4
+deneyapmini.menu.DebugLevel.verbose=Verbose
+deneyapmini.menu.DebugLevel.verbose.build.code_debug=5
+
+deneyapmini.menu.EraseFlash.none=Disabled
+deneyapmini.menu.EraseFlash.none.upload.erase_cmd=
+deneyapmini.menu.EraseFlash.all=Enabled
+deneyapmini.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+deneyapminiv2.name=Deneyap Mini v2
+
+deneyapminiv2.vid.0=0x303a
+deneyapminiv2.pid.0=0x8144
+
+deneyapminiv2.bootloader.tool=esptool_py
+deneyapminiv2.bootloader.tool.default=esptool_py
+
+deneyapminiv2.upload.tool=esptool_py
+deneyapminiv2.upload.tool.default=esptool_py
+deneyapminiv2.upload.tool.network=esp_ota
+
+deneyapminiv2.upload.maximum_size=1310720
+deneyapminiv2.upload.maximum_data_size=327680
+deneyapminiv2.upload.flags=
+deneyapminiv2.upload.extra_flags=
+deneyapminiv2.upload.use_1200bps_touch=false
+deneyapminiv2.upload.wait_for_upload_port=false
+
+deneyapminiv2.serial.disableDTR=false
+deneyapminiv2.serial.disableRTS=false
+
+deneyapminiv2.build.tarch=xtensa
+deneyapminiv2.build.bootloader_addr=0x1000
+deneyapminiv2.build.target=esp32s2
+deneyapminiv2.build.mcu=esp32s2
+deneyapminiv2.build.core=esp32
+deneyapminiv2.build.variant=deneyapminiv2
+deneyapminiv2.build.board=DYMv2
+
+deneyapminiv2.build.cdc_on_boot=1
+deneyapminiv2.build.msc_on_boot=0
+deneyapminiv2.build.dfu_on_boot=0
+deneyapminiv2.build.f_cpu=240000000L
+deneyapminiv2.build.flash_size=4MB
+deneyapminiv2.build.flash_freq=80m
+deneyapminiv2.build.flash_mode=dio
+deneyapminiv2.build.boot=qio
+deneyapminiv2.build.partitions=default
+deneyapminiv2.build.defines=-DBOARD_HAS_PSRAM
+
+## IDE 2.0 Seems to not update the value
+deneyapminiv2.menu.JTAGAdapter.default=Disabled
+deneyapminiv2.menu.JTAGAdapter.default.build.copy_jtag_files=0
+deneyapminiv2.menu.JTAGAdapter.external=FTDI Adapter
+deneyapminiv2.menu.JTAGAdapter.external.build.openocdscript=esp32s2-kaluga-1.cfg
+deneyapminiv2.menu.JTAGAdapter.external.build.copy_jtag_files=1
+deneyapminiv2.menu.JTAGAdapter.bridge=ESP USB Bridge
+deneyapminiv2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s2-bridge.cfg
+deneyapminiv2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+deneyapminiv2.menu.CDCOnBoot.cdc=Enabled
+deneyapminiv2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+deneyapminiv2.menu.CDCOnBoot.default=Disabled
+deneyapminiv2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+deneyapminiv2.menu.MSCOnBoot.default=Disabled
+deneyapminiv2.menu.MSCOnBoot.default.build.msc_on_boot=0
+deneyapminiv2.menu.MSCOnBoot.msc=Enabled
+deneyapminiv2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+deneyapminiv2.menu.DFUOnBoot.default=Disabled
+deneyapminiv2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+deneyapminiv2.menu.DFUOnBoot.dfu=Enabled
+deneyapminiv2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+deneyapminiv2.menu.UploadMode.cdc=Internal USB
+deneyapminiv2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+deneyapminiv2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+deneyapminiv2.menu.UploadMode.default=UART0
+deneyapminiv2.menu.UploadMode.default.upload.use_1200bps_touch=false
+deneyapminiv2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+deneyapminiv2.menu.PSRAM.enabled=Enabled
+deneyapminiv2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+deneyapminiv2.menu.PSRAM.disabled=Disabled
+deneyapminiv2.menu.PSRAM.disabled.build.defines=
+
+deneyapminiv2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+deneyapminiv2.menu.PartitionScheme.default.build.partitions=default
+deneyapminiv2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+deneyapminiv2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+deneyapminiv2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+deneyapminiv2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+deneyapminiv2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+deneyapminiv2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+deneyapminiv2.menu.PartitionScheme.minimal.build.partitions=minimal
+deneyapminiv2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+deneyapminiv2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+deneyapminiv2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+deneyapminiv2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+deneyapminiv2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+deneyapminiv2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+deneyapminiv2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+deneyapminiv2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+deneyapminiv2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+deneyapminiv2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+deneyapminiv2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+deneyapminiv2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+deneyapminiv2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+deneyapminiv2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+deneyapminiv2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+deneyapminiv2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+deneyapminiv2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+deneyapminiv2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+deneyapminiv2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+deneyapminiv2.menu.PartitionScheme.fatflash.build.partitions=ffat
+deneyapminiv2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+deneyapminiv2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+deneyapminiv2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+deneyapminiv2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+deneyapminiv2.menu.PartitionScheme.rainmaker=RainMaker 4MB
+deneyapminiv2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+deneyapminiv2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+deneyapminiv2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+deneyapminiv2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+deneyapminiv2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+deneyapminiv2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+deneyapminiv2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+deneyapminiv2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+deneyapminiv2.menu.CPUFreq.240=240MHz (WiFi)
+deneyapminiv2.menu.CPUFreq.240.build.f_cpu=240000000L
+deneyapminiv2.menu.CPUFreq.160=160MHz (WiFi)
+deneyapminiv2.menu.CPUFreq.160.build.f_cpu=160000000L
+deneyapminiv2.menu.CPUFreq.80=80MHz (WiFi)
+deneyapminiv2.menu.CPUFreq.80.build.f_cpu=80000000L
+deneyapminiv2.menu.CPUFreq.40=40MHz
+deneyapminiv2.menu.CPUFreq.40.build.f_cpu=40000000L
+deneyapminiv2.menu.CPUFreq.20=20MHz
+deneyapminiv2.menu.CPUFreq.20.build.f_cpu=20000000L
+deneyapminiv2.menu.CPUFreq.10=10MHz
+deneyapminiv2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+deneyapminiv2.menu.FlashMode.qio=QIO
+deneyapminiv2.menu.FlashMode.qio.build.flash_mode=dio
+deneyapminiv2.menu.FlashMode.qio.build.boot=qio
+deneyapminiv2.menu.FlashMode.dio=DIO
+deneyapminiv2.menu.FlashMode.dio.build.flash_mode=dio
+deneyapminiv2.menu.FlashMode.dio.build.boot=dio
+
+deneyapminiv2.menu.FlashFreq.80=80MHz
+deneyapminiv2.menu.FlashFreq.80.build.flash_freq=80m
+deneyapminiv2.menu.FlashFreq.40=40MHz
+deneyapminiv2.menu.FlashFreq.40.build.flash_freq=40m
+
+deneyapminiv2.menu.FlashSize.4M=4MB (32Mb)
+deneyapminiv2.menu.FlashSize.4M.build.flash_size=4MB
+deneyapminiv2.menu.FlashSize.8M=8MB (64Mb)
+deneyapminiv2.menu.FlashSize.8M.build.flash_size=8MB
+deneyapminiv2.menu.FlashSize.2M=2MB (16Mb)
+deneyapminiv2.menu.FlashSize.2M.build.flash_size=2MB
+deneyapminiv2.menu.FlashSize.16M=16MB (128Mb)
+deneyapminiv2.menu.FlashSize.16M.build.flash_size=16MB
+
+deneyapminiv2.menu.UploadSpeed.921600=921600
+deneyapminiv2.menu.UploadSpeed.921600.upload.speed=921600
+deneyapminiv2.menu.UploadSpeed.115200=115200
+deneyapminiv2.menu.UploadSpeed.115200.upload.speed=115200
+deneyapminiv2.menu.UploadSpeed.256000.windows=256000
+deneyapminiv2.menu.UploadSpeed.256000.upload.speed=256000
+deneyapminiv2.menu.UploadSpeed.230400.windows.upload.speed=256000
+deneyapminiv2.menu.UploadSpeed.230400=230400
+deneyapminiv2.menu.UploadSpeed.230400.upload.speed=230400
+deneyapminiv2.menu.UploadSpeed.460800.linux=460800
+deneyapminiv2.menu.UploadSpeed.460800.macosx=460800
+deneyapminiv2.menu.UploadSpeed.460800.upload.speed=460800
+deneyapminiv2.menu.UploadSpeed.512000.windows=512000
+deneyapminiv2.menu.UploadSpeed.512000.upload.speed=512000
+
+deneyapminiv2.menu.DebugLevel.none=None
+deneyapminiv2.menu.DebugLevel.none.build.code_debug=0
+deneyapminiv2.menu.DebugLevel.error=Error
+deneyapminiv2.menu.DebugLevel.error.build.code_debug=1
+deneyapminiv2.menu.DebugLevel.warn=Warn
+deneyapminiv2.menu.DebugLevel.warn.build.code_debug=2
+deneyapminiv2.menu.DebugLevel.info=Info
+deneyapminiv2.menu.DebugLevel.info.build.code_debug=3
+deneyapminiv2.menu.DebugLevel.debug=Debug
+deneyapminiv2.menu.DebugLevel.debug.build.code_debug=4
+deneyapminiv2.menu.DebugLevel.verbose=Verbose
+deneyapminiv2.menu.DebugLevel.verbose.build.code_debug=5
+
+deneyapminiv2.menu.EraseFlash.none=Disabled
+deneyapminiv2.menu.EraseFlash.none.upload.erase_cmd=
+deneyapminiv2.menu.EraseFlash.all=Enabled
+deneyapminiv2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+deneyapkartg.name=Deneyap Kart G
+
+deneyapkartg.vid.0=0x303a
+deneyapkartg.pid.0=0x814A
+
+deneyapkartg.bootloader.tool=esptool_py
+deneyapkartg.bootloader.tool.default=esptool_py
+
+deneyapkartg.upload.tool=esptool_py
+deneyapkartg.upload.tool.default=esptool_py
+deneyapkartg.upload.tool.network=esp_ota
+
+deneyapkartg.upload.maximum_size=1310720
+deneyapkartg.upload.maximum_data_size=327680
+deneyapkartg.upload.flags=
+deneyapkartg.upload.extra_flags=
+deneyapkartg.upload.use_1200bps_touch=false
+deneyapkartg.upload.wait_for_upload_port=false
+
+deneyapkartg.serial.disableDTR=false
+deneyapkartg.serial.disableRTS=false
+
+deneyapkartg.build.tarch=riscv32
+deneyapkartg.build.target=esp
+deneyapkartg.build.mcu=esp32c3
+deneyapkartg.build.core=esp32
+deneyapkartg.build.variant=deneyapkartg
+deneyapkartg.build.board=DYG
+deneyapkartg.build.bootloader_addr=0x0
+
+deneyapkartg.build.cdc_on_boot=1
+deneyapkartg.build.f_cpu=160000000L
+deneyapkartg.build.flash_size=4MB
+deneyapkartg.build.flash_freq=80m
+deneyapkartg.build.flash_mode=dio
+deneyapkartg.build.boot=qio
+deneyapkartg.build.partitions=default
+deneyapkartg.build.defines=
+
+## IDE 2.0 Seems to not update the value
+deneyapkartg.menu.JTAGAdapter.default=Disabled
+deneyapkartg.menu.JTAGAdapter.default.build.copy_jtag_files=0
+deneyapkartg.menu.JTAGAdapter.builtin=Integrated USB JTAG
+deneyapkartg.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg
+deneyapkartg.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+deneyapkartg.menu.JTAGAdapter.external=FTDI Adapter
+deneyapkartg.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg
+deneyapkartg.menu.JTAGAdapter.external.build.copy_jtag_files=1
+deneyapkartg.menu.JTAGAdapter.bridge=ESP USB Bridge
+deneyapkartg.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg
+deneyapkartg.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+deneyapkartg.menu.CDCOnBoot.cdc=Enabled
+deneyapkartg.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+deneyapkartg.menu.CDCOnBoot.default=Disabled
+deneyapkartg.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+deneyapkartg.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+deneyapkartg.menu.PartitionScheme.default.build.partitions=default
+deneyapkartg.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+deneyapkartg.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+deneyapkartg.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+deneyapkartg.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+deneyapkartg.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+deneyapkartg.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+deneyapkartg.menu.PartitionScheme.minimal.build.partitions=minimal
+deneyapkartg.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+deneyapkartg.menu.PartitionScheme.no_ota.build.partitions=no_ota
+deneyapkartg.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+deneyapkartg.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+deneyapkartg.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+deneyapkartg.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+deneyapkartg.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+deneyapkartg.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+deneyapkartg.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+deneyapkartg.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+deneyapkartg.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+deneyapkartg.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+deneyapkartg.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+deneyapkartg.menu.PartitionScheme.huge_app.build.partitions=huge_app
+deneyapkartg.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+deneyapkartg.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+deneyapkartg.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+deneyapkartg.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+deneyapkartg.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+deneyapkartg.menu.PartitionScheme.fatflash.build.partitions=ffat
+deneyapkartg.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+deneyapkartg.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+deneyapkartg.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+deneyapkartg.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+deneyapkartg.menu.PartitionScheme.rainmaker=RainMaker 4MB
+deneyapkartg.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+deneyapkartg.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+deneyapkartg.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+deneyapkartg.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+deneyapkartg.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+deneyapkartg.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+deneyapkartg.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+deneyapkartg.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+deneyapkartg.menu.CPUFreq.160=160MHz (WiFi)
+deneyapkartg.menu.CPUFreq.160.build.f_cpu=160000000L
+deneyapkartg.menu.CPUFreq.80=80MHz (WiFi)
+deneyapkartg.menu.CPUFreq.80.build.f_cpu=80000000L
+deneyapkartg.menu.CPUFreq.40=40MHz
+deneyapkartg.menu.CPUFreq.40.build.f_cpu=40000000L
+deneyapkartg.menu.CPUFreq.20=20MHz
+deneyapkartg.menu.CPUFreq.20.build.f_cpu=20000000L
+deneyapkartg.menu.CPUFreq.10=10MHz
+deneyapkartg.menu.CPUFreq.10.build.f_cpu=10000000L
+
+deneyapkartg.menu.FlashMode.qio=QIO
+deneyapkartg.menu.FlashMode.qio.build.flash_mode=dio
+deneyapkartg.menu.FlashMode.qio.build.boot=qio
+deneyapkartg.menu.FlashMode.dio=DIO
+deneyapkartg.menu.FlashMode.dio.build.flash_mode=dio
+deneyapkartg.menu.FlashMode.dio.build.boot=dio
+
+deneyapkartg.menu.FlashFreq.80=80MHz
+deneyapkartg.menu.FlashFreq.80.build.flash_freq=80m
+deneyapkartg.menu.FlashFreq.40=40MHz
+deneyapkartg.menu.FlashFreq.40.build.flash_freq=40m
+
+deneyapkartg.menu.FlashSize.4M=4MB (32Mb)
+deneyapkartg.menu.FlashSize.4M.build.flash_size=4MB
+deneyapkartg.menu.FlashSize.8M=8MB (64Mb)
+deneyapkartg.menu.FlashSize.8M.build.flash_size=8MB
+deneyapkartg.menu.FlashSize.2M=2MB (16Mb)
+deneyapkartg.menu.FlashSize.2M.build.flash_size=2MB
+deneyapkartg.menu.FlashSize.16M=16MB (128Mb)
+deneyapkartg.menu.FlashSize.16M.build.flash_size=16MB
+
+deneyapkartg.menu.UploadSpeed.921600=921600
+deneyapkartg.menu.UploadSpeed.921600.upload.speed=921600
+deneyapkartg.menu.UploadSpeed.115200=115200
+deneyapkartg.menu.UploadSpeed.115200.upload.speed=115200
+deneyapkartg.menu.UploadSpeed.256000.windows=256000
+deneyapkartg.menu.UploadSpeed.256000.upload.speed=256000
+deneyapkartg.menu.UploadSpeed.230400.windows.upload.speed=256000
+deneyapkartg.menu.UploadSpeed.230400=230400
+deneyapkartg.menu.UploadSpeed.230400.upload.speed=230400
+deneyapkartg.menu.UploadSpeed.460800.linux=460800
+deneyapkartg.menu.UploadSpeed.460800.macosx=460800
+deneyapkartg.menu.UploadSpeed.460800.upload.speed=460800
+deneyapkartg.menu.UploadSpeed.512000.windows=512000
+deneyapkartg.menu.UploadSpeed.512000.upload.speed=512000
+
+deneyapkartg.menu.DebugLevel.none=None
+deneyapkartg.menu.DebugLevel.none.build.code_debug=0
+deneyapkartg.menu.DebugLevel.error=Error
+deneyapkartg.menu.DebugLevel.error.build.code_debug=1
+deneyapkartg.menu.DebugLevel.warn=Warn
+deneyapkartg.menu.DebugLevel.warn.build.code_debug=2
+deneyapkartg.menu.DebugLevel.info=Info
+deneyapkartg.menu.DebugLevel.info.build.code_debug=3
+deneyapkartg.menu.DebugLevel.debug=Debug
+deneyapkartg.menu.DebugLevel.debug.build.code_debug=4
+deneyapkartg.menu.DebugLevel.verbose=Verbose
+deneyapkartg.menu.DebugLevel.verbose.build.code_debug=5
+
+deneyapkartg.menu.EraseFlash.none=Disabled
+deneyapkartg.menu.EraseFlash.none.upload.erase_cmd=
+deneyapkartg.menu.EraseFlash.all=Enabled
+deneyapkartg.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32-trueverit-iot-driver.name=Trueverit ESP32 Universal IoT Driver
+
+esp32-trueverit-iot-driver.bootloader.tool=esptool_py
+esp32-trueverit-iot-driver.bootloader.tool.default=esptool_py
+
+esp32-trueverit-iot-driver.upload.tool=esptool_py
+esp32-trueverit-iot-driver.upload.tool.default=esptool_py
+esp32-trueverit-iot-driver.upload.tool.network=esp_ota
+
+esp32-trueverit-iot-driver.upload.maximum_size=1310720
+esp32-trueverit-iot-driver.upload.maximum_data_size=327680
+esp32-trueverit-iot-driver.upload.flags=
+esp32-trueverit-iot-driver.upload.extra_flags=
+
+esp32-trueverit-iot-driver.serial.disableDTR=true
+esp32-trueverit-iot-driver.serial.disableRTS=true
+
+esp32-trueverit-iot-driver.build.tarch=xtensa
+esp32-trueverit-iot-driver.build.bootloader_addr=0x1000
+esp32-trueverit-iot-driver.build.target=esp32
+esp32-trueverit-iot-driver.build.mcu=esp32
+esp32-trueverit-iot-driver.build.core=esp32
+esp32-trueverit-iot-driver.build.variant=esp32-trueverit-iot-driver
+esp32-trueverit-iot-driver.build.board=Trueverit_ESP32_Universal_IoT_Driver
+
+esp32-trueverit-iot-driver.build.f_cpu=240000000L
+esp32-trueverit-iot-driver.build.flash_mode=dio
+esp32-trueverit-iot-driver.build.flash_size=4MB
+esp32-trueverit-iot-driver.build.boot=dio
+esp32-trueverit-iot-driver.build.partitions=default
+esp32-trueverit-iot-driver.build.defines=
+
+esp32-trueverit-iot-driver.menu.FlashFreq.80=80MHz
+esp32-trueverit-iot-driver.menu.FlashFreq.80.build.flash_freq=80m
+esp32-trueverit-iot-driver.menu.FlashFreq.40=40MHz
+esp32-trueverit-iot-driver.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32-trueverit-iot-driver.menu.UploadSpeed.115200=115200
+esp32-trueverit-iot-driver.menu.UploadSpeed.115200.upload.speed=115200
+esp32-trueverit-iot-driver.menu.UploadSpeed.256000.windows=256000
+esp32-trueverit-iot-driver.menu.UploadSpeed.256000.upload.speed=256000
+esp32-trueverit-iot-driver.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32-trueverit-iot-driver.menu.UploadSpeed.230400=230400
+esp32-trueverit-iot-driver.menu.UploadSpeed.230400.upload.speed=230400
+esp32-trueverit-iot-driver.menu.UploadSpeed.460800.linux=460800
+esp32-trueverit-iot-driver.menu.UploadSpeed.460800.macosx=460800
+esp32-trueverit-iot-driver.menu.UploadSpeed.460800.upload.speed=460800
+
+esp32-trueverit-iot-driver.menu.DebugLevel.none=None
+esp32-trueverit-iot-driver.menu.DebugLevel.none.build.code_debug=0
+esp32-trueverit-iot-driver.menu.DebugLevel.error=Error
+esp32-trueverit-iot-driver.menu.DebugLevel.error.build.code_debug=1
+esp32-trueverit-iot-driver.menu.DebugLevel.warn=Warn
+esp32-trueverit-iot-driver.menu.DebugLevel.warn.build.code_debug=2
+esp32-trueverit-iot-driver.menu.DebugLevel.info=Info
+esp32-trueverit-iot-driver.menu.DebugLevel.info.build.code_debug=3
+esp32-trueverit-iot-driver.menu.DebugLevel.debug=Debug
+esp32-trueverit-iot-driver.menu.DebugLevel.debug.build.code_debug=4
+esp32-trueverit-iot-driver.menu.DebugLevel.verbose=Verbose
+esp32-trueverit-iot-driver.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32-trueverit-iot-driver.menu.EraseFlash.none=Disabled
+esp32-trueverit-iot-driver.menu.EraseFlash.none.upload.erase_cmd=
+esp32-trueverit-iot-driver.menu.EraseFlash.all=Enabled
+esp32-trueverit-iot-driver.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32-trueverit-iot-driver-mkii.name=Trueverit ESP32 Universal IoT Driver MK II
+
+esp32-trueverit-iot-driver-mkii.bootloader.tool=esptool_py
+esp32-trueverit-iot-driver-mkii.bootloader.tool.default=esptool_py
+
+esp32-trueverit-iot-driver-mkii.upload.tool=esptool_py
+esp32-trueverit-iot-driver-mkii.upload.tool.default=esptool_py
+esp32-trueverit-iot-driver-mkii.upload.tool.network=esp_ota
+
+esp32-trueverit-iot-driver-mkii.upload.maximum_size=1310720
+esp32-trueverit-iot-driver-mkii.upload.maximum_data_size=327680
+esp32-trueverit-iot-driver-mkii.upload.flags=
+esp32-trueverit-iot-driver-mkii.upload.extra_flags=
+
+esp32-trueverit-iot-driver-mkii.serial.disableDTR=true
+esp32-trueverit-iot-driver-mkii.serial.disableRTS=true
+
+esp32-trueverit-iot-driver-mkii.build.tarch=xtensa
+esp32-trueverit-iot-driver-mkii.build.bootloader_addr=0x1000
+esp32-trueverit-iot-driver-mkii.build.target=esp32
+esp32-trueverit-iot-driver-mkii.build.mcu=esp32
+esp32-trueverit-iot-driver-mkii.build.core=esp32
+esp32-trueverit-iot-driver-mkii.build.variant=esp32-trueverit-iot-driver-mkii
+esp32-trueverit-iot-driver-mkii.build.board=Trueverit_ESP32_Universal_IoT_Driver_MK_II
+
+esp32-trueverit-iot-driver-mkii.build.f_cpu=240000000L
+esp32-trueverit-iot-driver-mkii.build.flash_mode=dio
+esp32-trueverit-iot-driver-mkii.build.flash_size=4MB
+esp32-trueverit-iot-driver-mkii.build.boot=dio
+esp32-trueverit-iot-driver-mkii.build.partitions=default
+esp32-trueverit-iot-driver-mkii.build.defines=
+
+esp32-trueverit-iot-driver-mkii.menu.FlashFreq.80=80MHz
+esp32-trueverit-iot-driver-mkii.menu.FlashFreq.80.build.flash_freq=80m
+esp32-trueverit-iot-driver-mkii.menu.FlashFreq.40=40MHz
+esp32-trueverit-iot-driver-mkii.menu.FlashFreq.40.build.flash_freq=40m
+
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.115200=115200
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.115200.upload.speed=115200
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.256000.windows=256000
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.256000.upload.speed=256000
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.230400=230400
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.230400.upload.speed=230400
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.460800.linux=460800
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.460800.macosx=460800
+esp32-trueverit-iot-driver-mkii.menu.UploadSpeed.460800.upload.speed=460800
+
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.none=None
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.none.build.code_debug=0
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.error=Error
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.error.build.code_debug=1
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.warn=Warn
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.warn.build.code_debug=2
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.info=Info
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.info.build.code_debug=3
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.debug=Debug
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.debug.build.code_debug=4
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.verbose=Verbose
+esp32-trueverit-iot-driver-mkii.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32-trueverit-iot-driver-mkii.menu.EraseFlash.none=Disabled
+esp32-trueverit-iot-driver-mkii.menu.EraseFlash.none.upload.erase_cmd=
+esp32-trueverit-iot-driver-mkii.menu.EraseFlash.all=Enabled
+esp32-trueverit-iot-driver-mkii.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+atmegazero_esp32s2.name=ATMegaZero ESP32-S2
+atmegazero_esp32s2.vid.0=0x239A
+atmegazero_esp32s2.pid.0=0x800A
+
+atmegazero_esp32s2.bootloader.tool=esptool_py
+atmegazero_esp32s2.bootloader.tool.default=esptool_py
+
+atmegazero_esp32s2.upload.tool=esptool_py
+atmegazero_esp32s2.upload.tool.default=esptool_py
+atmegazero_esp32s2.upload.tool.network=esp_ota
+
+atmegazero_esp32s2.upload.maximum_size=1310720
+atmegazero_esp32s2.upload.maximum_data_size=327680
+atmegazero_esp32s2.upload.flags=
+atmegazero_esp32s2.upload.extra_flags=
+atmegazero_esp32s2.upload.use_1200bps_touch=true
+atmegazero_esp32s2.upload.wait_for_upload_port=true
+
+atmegazero_esp32s2.serial.disableDTR=false
+atmegazero_esp32s2.serial.disableRTS=false
+
+atmegazero_esp32s2.build.tarch=xtensa
+atmegazero_esp32s2.build.bootloader_addr=0x1000
+atmegazero_esp32s2.build.target=esp32s2
+atmegazero_esp32s2.build.mcu=esp32s2
+atmegazero_esp32s2.build.core=esp32
+atmegazero_esp32s2.build.variant=atmegazero_esp32s2
+atmegazero_esp32s2.build.board=atmegazero_esp32s2
+
+atmegazero_esp32s2.build.cdc_on_boot=1
+atmegazero_esp32s2.build.msc_on_boot=0
+atmegazero_esp32s2.build.dfu_on_boot=0
+atmegazero_esp32s2.build.serial=0
+atmegazero_esp32s2.build.f_cpu=240000000L
+atmegazero_esp32s2.build.flash_size=16MB
+atmegazero_esp32s2.build.flash_freq=40m
+atmegazero_esp32s2.build.flash_mode=qio
+atmegazero_esp32s2.build.boot=qio
+atmegazero_esp32s2.build.partitions=default
+atmegazero_esp32s2.build.defines=
+
+atmegazero_esp32s2.menu.CDCOnBoot.cdc=Enabled
+atmegazero_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+atmegazero_esp32s2.menu.CDCOnBoot.default=Disabled
+atmegazero_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+atmegazero_esp32s2.menu.MSCOnBoot.default=Disabled
+atmegazero_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0
+atmegazero_esp32s2.menu.MSCOnBoot.msc=Enabled
+atmegazero_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+atmegazero_esp32s2.menu.DFUOnBoot.default=Disabled
+atmegazero_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+atmegazero_esp32s2.menu.DFUOnBoot.dfu=Enabled
+atmegazero_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+atmegazero_esp32s2.menu.PSRAM.disabled=Disabled
+atmegazero_esp32s2.menu.PSRAM.disabled.build.defines=
+atmegazero_esp32s2.menu.PSRAM.enabled=Enabled
+atmegazero_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+atmegazero_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 16MB (2MB APP/11.6MB FFAT)
+atmegazero_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+atmegazero_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-16MB-tinyuf2
+atmegazero_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+atmegazero_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+atmegazero_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+atmegazero_esp32s2.menu.PartitionScheme.default.build.partitions=default
+atmegazero_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+atmegazero_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+atmegazero_esp32s2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+atmegazero_esp32s2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+atmegazero_esp32s2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+atmegazero_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+atmegazero_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+atmegazero_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+atmegazero_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+atmegazero_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+atmegazero_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+atmegazero_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+atmegazero_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+atmegazero_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+atmegazero_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+atmegazero_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+atmegazero_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+atmegazero_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+atmegazero_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+atmegazero_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+atmegazero_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+atmegazero_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+atmegazero_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+atmegazero_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+atmegazero_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+atmegazero_esp32s2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+atmegazero_esp32s2.menu.PartitionScheme.fatflash.build.partitions=ffat
+atmegazero_esp32s2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+atmegazero_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+atmegazero_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+atmegazero_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+atmegazero_esp32s2.menu.CPUFreq.240=240MHz (WiFi)
+atmegazero_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L
+atmegazero_esp32s2.menu.CPUFreq.160=160MHz (WiFi)
+atmegazero_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L
+atmegazero_esp32s2.menu.CPUFreq.80=80MHz (WiFi)
+atmegazero_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L
+atmegazero_esp32s2.menu.CPUFreq.40=40MHz
+atmegazero_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L
+atmegazero_esp32s2.menu.CPUFreq.20=20MHz
+atmegazero_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L
+atmegazero_esp32s2.menu.CPUFreq.10=10MHz
+atmegazero_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+atmegazero_esp32s2.menu.FlashMode.qio=QIO
+atmegazero_esp32s2.menu.FlashMode.qio.build.flash_mode=dio
+atmegazero_esp32s2.menu.FlashMode.qio.build.boot=qio
+atmegazero_esp32s2.menu.FlashMode.dio=DIO
+atmegazero_esp32s2.menu.FlashMode.dio.build.flash_mode=dio
+atmegazero_esp32s2.menu.FlashMode.dio.build.boot=dio
+
+atmegazero_esp32s2.menu.FlashFreq.80=80MHz
+atmegazero_esp32s2.menu.FlashFreq.80.build.flash_freq=80m
+atmegazero_esp32s2.menu.FlashFreq.40=40MHz
+atmegazero_esp32s2.menu.FlashFreq.40.build.flash_freq=40m
+
+atmegazero_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+atmegazero_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+atmegazero_esp32s2.menu.FlashSize.8M=8MB (64Mb)
+atmegazero_esp32s2.menu.FlashSize.8M.build.flash_size=8MB
+atmegazero_esp32s2.menu.FlashSize.2M=2MB (16Mb)
+atmegazero_esp32s2.menu.FlashSize.2M.build.flash_size=2MB
+atmegazero_esp32s2.menu.FlashSize.16M=16MB (128Mb)
+atmegazero_esp32s2.menu.FlashSize.16M.build.flash_size=16MB
+
+atmegazero_esp32s2.menu.UploadSpeed.921600=921600
+atmegazero_esp32s2.menu.UploadSpeed.921600.upload.speed=921600
+atmegazero_esp32s2.menu.UploadSpeed.115200=115200
+atmegazero_esp32s2.menu.UploadSpeed.115200.upload.speed=115200
+atmegazero_esp32s2.menu.UploadSpeed.256000.windows=256000
+atmegazero_esp32s2.menu.UploadSpeed.256000.upload.speed=256000
+atmegazero_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000
+atmegazero_esp32s2.menu.UploadSpeed.230400=230400
+atmegazero_esp32s2.menu.UploadSpeed.230400.upload.speed=230400
+atmegazero_esp32s2.menu.UploadSpeed.460800.linux=460800
+atmegazero_esp32s2.menu.UploadSpeed.460800.macosx=460800
+atmegazero_esp32s2.menu.UploadSpeed.460800.upload.speed=460800
+atmegazero_esp32s2.menu.UploadSpeed.512000.windows=512000
+atmegazero_esp32s2.menu.UploadSpeed.512000.upload.speed=512000
+
+atmegazero_esp32s2.menu.DebugLevel.none=None
+atmegazero_esp32s2.menu.DebugLevel.none.build.code_debug=0
+atmegazero_esp32s2.menu.DebugLevel.error=Error
+atmegazero_esp32s2.menu.DebugLevel.error.build.code_debug=1
+atmegazero_esp32s2.menu.DebugLevel.warn=Warn
+atmegazero_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+atmegazero_esp32s2.menu.DebugLevel.info=Info
+atmegazero_esp32s2.menu.DebugLevel.info.build.code_debug=3
+atmegazero_esp32s2.menu.DebugLevel.debug=Debug
+atmegazero_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+atmegazero_esp32s2.menu.DebugLevel.verbose=Verbose
+atmegazero_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+atmegazero_esp32s2.menu.EraseFlash.none=Disabled
+atmegazero_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+atmegazero_esp32s2.menu.EraseFlash.all=Enabled
+atmegazero_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+franzininho_wifi_esp32s2.name=Franzininho WiFi
+franzininho_wifi_esp32s2.vid.0=0x303A
+franzininho_wifi_esp32s2.pid.0=0x80A9
+
+franzininho_wifi_esp32s2.bootloader.tool=esptool_py
+franzininho_wifi_esp32s2.bootloader.tool.default=esptool_py
+
+franzininho_wifi_esp32s2.upload.tool=esptool_py
+franzininho_wifi_esp32s2.upload.tool.default=esptool_py
+franzininho_wifi_esp32s2.upload.tool.network=esp_ota
+
+franzininho_wifi_esp32s2.upload.maximum_size=1310720
+franzininho_wifi_esp32s2.upload.maximum_data_size=327680
+franzininho_wifi_esp32s2.upload.flags=
+franzininho_wifi_esp32s2.upload.extra_flags=
+franzininho_wifi_esp32s2.upload.use_1200bps_touch=true
+franzininho_wifi_esp32s2.upload.wait_for_upload_port=true
+franzininho_wifi_esp32s2.upload.speed=921600
+
+franzininho_wifi_esp32s2.serial.disableDTR=false
+franzininho_wifi_esp32s2.serial.disableRTS=false
+
+franzininho_wifi_esp32s2.build.tarch=xtensa
+franzininho_wifi_esp32s2.build.bootloader_addr=0x1000
+franzininho_wifi_esp32s2.build.target=esp32s2
+franzininho_wifi_esp32s2.build.mcu=esp32s2
+franzininho_wifi_esp32s2.build.core=esp32
+franzininho_wifi_esp32s2.build.variant=franzininho_wifi_esp32s2
+franzininho_wifi_esp32s2.build.board=FRANZININHO_WIFI
+
+franzininho_wifi_esp32s2.build.cdc_on_boot=1
+franzininho_wifi_esp32s2.build.msc_on_boot=0
+franzininho_wifi_esp32s2.build.dfu_on_boot=0
+franzininho_wifi_esp32s2.build.f_cpu=240000000L
+franzininho_wifi_esp32s2.build.flash_size=4MB
+franzininho_wifi_esp32s2.build.flash_freq=80m
+franzininho_wifi_esp32s2.build.flash_mode=dio
+franzininho_wifi_esp32s2.build.boot=qio
+franzininho_wifi_esp32s2.build.partitions=default
+franzininho_wifi_esp32s2.build.defines=
+
+franzininho_wifi_esp32s2.menu.PSRAM.disabled=Disabled
+franzininho_wifi_esp32s2.menu.PSRAM.disabled.build.defines=
+franzininho_wifi_esp32s2.menu.PSRAM.enabled=Enabled
+franzininho_wifi_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+franzininho_wifi_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+franzininho_wifi_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+franzininho_wifi_esp32s2.menu.FlashSize.8M=8MB (64Mb)
+franzininho_wifi_esp32s2.menu.FlashSize.8M.build.flash_size=8MB
+franzininho_wifi_esp32s2.menu.FlashSize.16M=16MB (128Mb)
+franzininho_wifi_esp32s2.menu.FlashSize.16M.build.flash_size=16MB
+
+franzininho_wifi_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.default.build.partitions=default
+franzininho_wifi_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+franzininho_wifi_esp32s2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+franzininho_wifi_esp32s2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+franzininho_wifi_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+franzininho_wifi_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+franzininho_wifi_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+franzininho_wifi_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+franzininho_wifi_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+franzininho_wifi_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+franzininho_wifi_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+franzininho_wifi_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+franzininho_wifi_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+franzininho_wifi_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+franzininho_wifi_esp32s2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.fatflash.build.partitions=ffat
+franzininho_wifi_esp32s2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+franzininho_wifi_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+franzininho_wifi_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+franzininho_wifi_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+franzininho_wifi_esp32s2.menu.DebugLevel.none=None
+franzininho_wifi_esp32s2.menu.DebugLevel.none.build.code_debug=0
+franzininho_wifi_esp32s2.menu.DebugLevel.error=Error
+franzininho_wifi_esp32s2.menu.DebugLevel.error.build.code_debug=1
+franzininho_wifi_esp32s2.menu.DebugLevel.warn=Warn
+franzininho_wifi_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+franzininho_wifi_esp32s2.menu.DebugLevel.info=Info
+franzininho_wifi_esp32s2.menu.DebugLevel.info.build.code_debug=3
+franzininho_wifi_esp32s2.menu.DebugLevel.debug=Debug
+franzininho_wifi_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+franzininho_wifi_esp32s2.menu.DebugLevel.verbose=Verbose
+franzininho_wifi_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+franzininho_wifi_esp32s2.menu.EraseFlash.none=Disabled
+franzininho_wifi_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+franzininho_wifi_esp32s2.menu.EraseFlash.all=Enabled
+franzininho_wifi_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+franzininho_wifi_msc_esp32s2.name=Franzininho WiFi MSC
+franzininho_wifi_msc_esp32s2.vid.0=0x303A
+franzininho_wifi_msc_esp32s2.pid.0=0x80A9
+
+franzininho_wifi_msc_esp32s2.bootloader.tool=esptool_py
+franzininho_wifi_msc_esp32s2.bootloader.tool.default=esptool_py
+
+franzininho_wifi_msc_esp32s2.upload.tool=esptool_py
+franzininho_wifi_msc_esp32s2.upload.tool.default=esptool_py
+franzininho_wifi_msc_esp32s2.upload.tool.network=esp_ota
+
+franzininho_wifi_msc_esp32s2.upload.maximum_size=1310720
+franzininho_wifi_msc_esp32s2.upload.maximum_data_size=327680
+franzininho_wifi_msc_esp32s2.upload.flags=
+franzininho_wifi_msc_esp32s2.upload.extra_flags=
+franzininho_wifi_msc_esp32s2.upload.use_1200bps_touch=true
+franzininho_wifi_msc_esp32s2.upload.wait_for_upload_port=true
+franzininho_wifi_msc_esp32s2.upload.speed=921600
+
+franzininho_wifi_msc_esp32s2.serial.disableDTR=false
+franzininho_wifi_msc_esp32s2.serial.disableRTS=false
+
+franzininho_wifi_msc_esp32s2.build.tarch=xtensa
+franzininho_wifi_msc_esp32s2.build.bootloader_addr=0x1000
+franzininho_wifi_msc_esp32s2.build.target=esp32s2
+franzininho_wifi_msc_esp32s2.build.mcu=esp32s2
+franzininho_wifi_msc_esp32s2.build.core=esp32
+franzininho_wifi_msc_esp32s2.build.variant=franzininho_wifi_msc_esp32s2
+franzininho_wifi_msc_esp32s2.build.board=FRANZININHO_WIFI_MSC
+
+franzininho_wifi_msc_esp32s2.build.cdc_on_boot=1
+franzininho_wifi_msc_esp32s2.build.msc_on_boot=1
+franzininho_wifi_msc_esp32s2.build.dfu_on_boot=1
+franzininho_wifi_msc_esp32s2.build.f_cpu=240000000L
+franzininho_wifi_msc_esp32s2.build.flash_size=4MB
+franzininho_wifi_msc_esp32s2.build.flash_freq=80m
+franzininho_wifi_msc_esp32s2.build.flash_mode=dio
+franzininho_wifi_msc_esp32s2.build.boot=qio
+franzininho_wifi_msc_esp32s2.build.partitions=default
+franzininho_wifi_msc_esp32s2.build.defines=
+
+franzininho_wifi_msc_esp32s2.menu.PSRAM.disabled=Disabled
+franzininho_wifi_msc_esp32s2.menu.PSRAM.disabled.build.defines=
+franzininho_wifi_msc_esp32s2.menu.PSRAM.enabled=Enabled
+franzininho_wifi_msc_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+
+franzininho_wifi_msc_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+franzininho_wifi_msc_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+franzininho_wifi_msc_esp32s2.menu.FlashSize.8M=8MB (64Mb)
+franzininho_wifi_msc_esp32s2.menu.FlashSize.8M.build.flash_size=8MB
+franzininho_wifi_msc_esp32s2.menu.FlashSize.16M=16MB (128Mb)
+franzininho_wifi_msc_esp32s2.menu.FlashSize.16M.build.flash_size=16MB
+
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default.build.partitions=default
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.fatflash.build.partitions=ffat
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+franzininho_wifi_msc_esp32s2.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.none=None
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.none.build.code_debug=0
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.error=Error
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.error.build.code_debug=1
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.warn=Warn
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.info=Info
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.info.build.code_debug=3
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.debug=Debug
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.verbose=Verbose
+franzininho_wifi_msc_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+franzininho_wifi_msc_esp32s2.menu.EraseFlash.none=Disabled
+franzininho_wifi_msc_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+franzininho_wifi_msc_esp32s2.menu.EraseFlash.all=Enabled
+franzininho_wifi_msc_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+tamc_termod_s3.name=TAMC Termod S3
+
+tamc_termod_s3.bootloader.tool=esptool_py
+tamc_termod_s3.bootloader.tool.default=esptool_py
+
+tamc_termod_s3.upload.tool=esptool_py
+tamc_termod_s3.upload.tool.default=esptool_py
+tamc_termod_s3.upload.tool.network=esp_ota
+
+tamc_termod_s3.upload.maximum_size=1310720
+tamc_termod_s3.upload.maximum_data_size=327680
+tamc_termod_s3.upload.flags=
+tamc_termod_s3.upload.extra_flags=
+tamc_termod_s3.upload.use_1200bps_touch=false
+tamc_termod_s3.upload.wait_for_upload_port=false
+
+tamc_termod_s3.serial.disableDTR=false
+tamc_termod_s3.serial.disableRTS=false
+
+tamc_termod_s3.build.tarch=xtensa
+tamc_termod_s3.build.bootloader_addr=0x0
+tamc_termod_s3.build.target=esp32s3
+tamc_termod_s3.build.mcu=esp32s3
+tamc_termod_s3.build.core=esp32
+tamc_termod_s3.build.variant=tamc_termod_s3
+tamc_termod_s3.build.board=TAMC_TERMOD_S3
+
+tamc_termod_s3.build.usb_mode=1
+tamc_termod_s3.build.cdc_on_boot=1
+tamc_termod_s3.build.msc_on_boot=0
+tamc_termod_s3.build.dfu_on_boot=0
+tamc_termod_s3.build.f_cpu=240000000L
+tamc_termod_s3.build.flash_size=8MB
+tamc_termod_s3.build.flash_freq=80m
+tamc_termod_s3.build.flash_mode=dio
+tamc_termod_s3.build.boot=qio
+tamc_termod_s3.build.boot_freq=80m
+tamc_termod_s3.build.partitions=default
+tamc_termod_s3.build.defines=
+tamc_termod_s3.build.loop_core=
+tamc_termod_s3.build.event_core=
+tamc_termod_s3.build.psram_type=qspi
+tamc_termod_s3.build.memory_type={build.boot}_{build.psram_type}
+
+tamc_termod_s3.menu.PSRAM.enabled=QSPI PSRAM
+tamc_termod_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+tamc_termod_s3.menu.PSRAM.enabled.build.psram_type=qspi
+tamc_termod_s3.menu.PSRAM.disabled=Disabled
+tamc_termod_s3.menu.PSRAM.disabled.build.defines=
+tamc_termod_s3.menu.PSRAM.disabled.build.psram_type=qspi
+tamc_termod_s3.menu.PSRAM.opi=OPI PSRAM
+tamc_termod_s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+tamc_termod_s3.menu.PSRAM.opi.build.psram_type=opi
+
+tamc_termod_s3.menu.FlashMode.qio=QIO 80MHz
+tamc_termod_s3.menu.FlashMode.qio.build.flash_mode=dio
+tamc_termod_s3.menu.FlashMode.qio.build.boot=qio
+tamc_termod_s3.menu.FlashMode.qio.build.boot_freq=80m
+tamc_termod_s3.menu.FlashMode.qio.build.flash_freq=80m
+tamc_termod_s3.menu.FlashMode.qio120=QIO 120MHz
+tamc_termod_s3.menu.FlashMode.qio120.build.flash_mode=dio
+tamc_termod_s3.menu.FlashMode.qio120.build.boot=qio
+tamc_termod_s3.menu.FlashMode.qio120.build.boot_freq=120m
+tamc_termod_s3.menu.FlashMode.qio120.build.flash_freq=80m
+tamc_termod_s3.menu.FlashMode.dio=DIO 80MHz
+tamc_termod_s3.menu.FlashMode.dio.build.flash_mode=dio
+tamc_termod_s3.menu.FlashMode.dio.build.boot=dio
+tamc_termod_s3.menu.FlashMode.dio.build.boot_freq=80m
+tamc_termod_s3.menu.FlashMode.dio.build.flash_freq=80m
+tamc_termod_s3.menu.FlashMode.opi=OPI 80MHz
+tamc_termod_s3.menu.FlashMode.opi.build.flash_mode=dout
+tamc_termod_s3.menu.FlashMode.opi.build.boot=opi
+tamc_termod_s3.menu.FlashMode.opi.build.boot_freq=80m
+tamc_termod_s3.menu.FlashMode.opi.build.flash_freq=80m
+
+tamc_termod_s3.menu.FlashSize.4M=4MB (32Mb)
+tamc_termod_s3.menu.FlashSize.4M.build.flash_size=4MB
+tamc_termod_s3.menu.FlashSize.8M=8MB (64Mb)
+tamc_termod_s3.menu.FlashSize.8M.build.flash_size=8MB
+tamc_termod_s3.menu.FlashSize.16M=16MB (128Mb)
+tamc_termod_s3.menu.FlashSize.16M.build.flash_size=16MB
+
+tamc_termod_s3.menu.LoopCore.1=Core 1
+tamc_termod_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+tamc_termod_s3.menu.LoopCore.0=Core 0
+tamc_termod_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+tamc_termod_s3.menu.EventsCore.1=Core 1
+tamc_termod_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+tamc_termod_s3.menu.EventsCore.0=Core 0
+tamc_termod_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+tamc_termod_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+tamc_termod_s3.menu.USBMode.hwcdc.build.usb_mode=1
+tamc_termod_s3.menu.USBMode.default=USB-OTG (TinyUSB)
+tamc_termod_s3.menu.USBMode.default.build.usb_mode=0
+
+tamc_termod_s3.menu.CDCOnBoot.cdc=Enabled
+tamc_termod_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+tamc_termod_s3.menu.CDCOnBoot.default=Disabled
+tamc_termod_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+tamc_termod_s3.menu.MSCOnBoot.default=Disabled
+tamc_termod_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+tamc_termod_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+tamc_termod_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+tamc_termod_s3.menu.DFUOnBoot.default=Disabled
+tamc_termod_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+tamc_termod_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+tamc_termod_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+tamc_termod_s3.menu.UploadMode.default=UART0 / Hardware CDC
+tamc_termod_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+tamc_termod_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+tamc_termod_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+tamc_termod_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+tamc_termod_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+tamc_termod_s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+tamc_termod_s3.menu.PartitionScheme.default.build.partitions=default
+tamc_termod_s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+tamc_termod_s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+tamc_termod_s3.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+tamc_termod_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+tamc_termod_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+tamc_termod_s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+tamc_termod_s3.menu.PartitionScheme.minimal.build.partitions=minimal
+tamc_termod_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+tamc_termod_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+tamc_termod_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+tamc_termod_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+tamc_termod_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+tamc_termod_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+tamc_termod_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+tamc_termod_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+tamc_termod_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+tamc_termod_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+tamc_termod_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+tamc_termod_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+tamc_termod_s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+tamc_termod_s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+tamc_termod_s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+tamc_termod_s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+tamc_termod_s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+tamc_termod_s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+tamc_termod_s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+tamc_termod_s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+tamc_termod_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+tamc_termod_s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+tamc_termod_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+tamc_termod_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+tamc_termod_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+tamc_termod_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+tamc_termod_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+tamc_termod_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+tamc_termod_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+tamc_termod_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+tamc_termod_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+tamc_termod_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+tamc_termod_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+tamc_termod_s3.menu.CPUFreq.240=240MHz (WiFi)
+tamc_termod_s3.menu.CPUFreq.240.build.f_cpu=240000000L
+tamc_termod_s3.menu.CPUFreq.160=160MHz (WiFi)
+tamc_termod_s3.menu.CPUFreq.160.build.f_cpu=160000000L
+tamc_termod_s3.menu.CPUFreq.80=80MHz (WiFi)
+tamc_termod_s3.menu.CPUFreq.80.build.f_cpu=80000000L
+tamc_termod_s3.menu.CPUFreq.40=40MHz
+tamc_termod_s3.menu.CPUFreq.40.build.f_cpu=40000000L
+tamc_termod_s3.menu.CPUFreq.20=20MHz
+tamc_termod_s3.menu.CPUFreq.20.build.f_cpu=20000000L
+tamc_termod_s3.menu.CPUFreq.10=10MHz
+tamc_termod_s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+tamc_termod_s3.menu.UploadSpeed.921600=921600
+tamc_termod_s3.menu.UploadSpeed.921600.upload.speed=921600
+tamc_termod_s3.menu.UploadSpeed.115200=115200
+tamc_termod_s3.menu.UploadSpeed.115200.upload.speed=115200
+tamc_termod_s3.menu.UploadSpeed.256000.windows=256000
+tamc_termod_s3.menu.UploadSpeed.256000.upload.speed=256000
+tamc_termod_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+tamc_termod_s3.menu.UploadSpeed.230400=230400
+tamc_termod_s3.menu.UploadSpeed.230400.upload.speed=230400
+tamc_termod_s3.menu.UploadSpeed.460800.linux=460800
+tamc_termod_s3.menu.UploadSpeed.460800.macosx=460800
+tamc_termod_s3.menu.UploadSpeed.460800.upload.speed=460800
+tamc_termod_s3.menu.UploadSpeed.512000.windows=512000
+tamc_termod_s3.menu.UploadSpeed.512000.upload.speed=512000
+
+tamc_termod_s3.menu.DebugLevel.none=None
+tamc_termod_s3.menu.DebugLevel.none.build.code_debug=0
+tamc_termod_s3.menu.DebugLevel.error=Error
+tamc_termod_s3.menu.DebugLevel.error.build.code_debug=1
+tamc_termod_s3.menu.DebugLevel.warn=Warn
+tamc_termod_s3.menu.DebugLevel.warn.build.code_debug=2
+tamc_termod_s3.menu.DebugLevel.info=Info
+tamc_termod_s3.menu.DebugLevel.info.build.code_debug=3
+tamc_termod_s3.menu.DebugLevel.debug=Debug
+tamc_termod_s3.menu.DebugLevel.debug.build.code_debug=4
+tamc_termod_s3.menu.DebugLevel.verbose=Verbose
+tamc_termod_s3.menu.DebugLevel.verbose.build.code_debug=5
+
+tamc_termod_s3.menu.EraseFlash.none=Disabled
+tamc_termod_s3.menu.EraseFlash.none.upload.erase_cmd=
+tamc_termod_s3.menu.EraseFlash.all=Enabled
+tamc_termod_s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+dpu_esp32.name=DPU ESP32
+
+dpu_esp32.bootloader.tool=esptool_py
+dpu_esp32.bootloader.tool.default=esptool_py
+
+dpu_esp32.upload.tool=esptool_py
+dpu_esp32.upload.tool.default=esptool_py
+dpu_esp32.upload.tool.network=esp_ota
+
+dpu_esp32.upload.maximum_size=3342336
+dpu_esp32.upload.maximum_data_size=327680
+dpu_esp32.upload.flags=
+dpu_esp32.upload.extra_flags=
+
+dpu_esp32.serial.disableDTR=true
+dpu_esp32.serial.disableRTS=true
+
+dpu_esp32.build.tarch=xtensa
+dpu_esp32.build.bootloader_addr=0x1000
+dpu_esp32.build.target=esp32
+dpu_esp32.build.mcu=esp32
+dpu_esp32.build.core=esp32
+dpu_esp32.build.variant=dpu_esp32
+dpu_esp32.build.board=DPU_ESP32
+
+dpu_esp32.build.f_cpu=240000000L
+dpu_esp32.build.flash_size=8MB
+dpu_esp32.build.flash_freq=40m
+dpu_esp32.build.flash_mode=dio
+dpu_esp32.build.boot=dio
+dpu_esp32.build.partitions=default_8MB
+dpu_esp32.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+dpu_esp32.build.extra_libs=
+
+dpu_esp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+dpu_esp32.menu.PartitionScheme.default.build.partitions=default
+dpu_esp32.menu.PartitionScheme.default.upload.maximum_size=1310720
+dpu_esp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+dpu_esp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+dpu_esp32.menu.PartitionScheme.defaultffat.upload.maximum_size=1310720
+dpu_esp32.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+dpu_esp32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+dpu_esp32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+dpu_esp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+dpu_esp32.menu.PartitionScheme.minimal.build.partitions=minimal
+dpu_esp32.menu.PartitionScheme.minimal.upload.maximum_size=1310720
+dpu_esp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+dpu_esp32.menu.PartitionScheme.no_ota.build.partitions=no_ota
+dpu_esp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+dpu_esp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+dpu_esp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+dpu_esp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+dpu_esp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+dpu_esp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+dpu_esp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+dpu_esp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+dpu_esp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+dpu_esp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+dpu_esp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+dpu_esp32.menu.PartitionScheme.huge_app.build.partitions=huge_app
+dpu_esp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+dpu_esp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+dpu_esp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+dpu_esp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+dpu_esp32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+dpu_esp32.menu.PartitionScheme.fatflash.build.partitions=ffat
+
+dpu_esp32.menu.FlashMode.qio=QIO
+dpu_esp32.menu.FlashMode.qio.build.flash_mode=dio
+dpu_esp32.menu.FlashMode.qio.build.boot=qio
+dpu_esp32.menu.FlashMode.dio=DIO
+dpu_esp32.menu.FlashMode.dio.build.flash_mode=dio
+dpu_esp32.menu.FlashMode.dio.build.boot=dio
+
+dpu_esp32.menu.FlashFreq.80=80MHz
+dpu_esp32.menu.FlashFreq.80.build.flash_freq=80m
+dpu_esp32.menu.FlashFreq.40=40MHz
+dpu_esp32.menu.FlashFreq.40.build.flash_freq=40m
+
+dpu_esp32.menu.UploadSpeed.921600=921600
+dpu_esp32.menu.UploadSpeed.921600.upload.speed=921600
+dpu_esp32.menu.UploadSpeed.115200=115200
+dpu_esp32.menu.UploadSpeed.115200.upload.speed=115200
+dpu_esp32.menu.UploadSpeed.256000.windows=256000
+dpu_esp32.menu.UploadSpeed.256000.upload.speed=256000
+dpu_esp32.menu.UploadSpeed.230400.windows.upload.speed=256000
+dpu_esp32.menu.UploadSpeed.230400=230400
+dpu_esp32.menu.UploadSpeed.230400.upload.speed=230400
+dpu_esp32.menu.UploadSpeed.460800.linux=460800
+dpu_esp32.menu.UploadSpeed.460800.macosx=460800
+dpu_esp32.menu.UploadSpeed.460800.upload.speed=460800
+dpu_esp32.menu.UploadSpeed.512000.windows=512000
+dpu_esp32.menu.UploadSpeed.512000.upload.speed=512000
+
+dpu_esp32.menu.DebugLevel.none=None
+dpu_esp32.menu.DebugLevel.none.build.code_debug=0
+dpu_esp32.menu.DebugLevel.error=Error
+dpu_esp32.menu.DebugLevel.error.build.code_debug=1
+dpu_esp32.menu.DebugLevel.warn=Warn
+dpu_esp32.menu.DebugLevel.warn.build.code_debug=2
+dpu_esp32.menu.DebugLevel.info=Info
+dpu_esp32.menu.DebugLevel.info.build.code_debug=3
+dpu_esp32.menu.DebugLevel.debug=Debug
+dpu_esp32.menu.DebugLevel.debug.build.code_debug=4
+dpu_esp32.menu.DebugLevel.verbose=Verbose
+dpu_esp32.menu.DebugLevel.verbose.build.code_debug=5
+
+dpu_esp32.menu.EraseFlash.none=Disabled
+dpu_esp32.menu.EraseFlash.none.upload.erase_cmd=
+dpu_esp32.menu.EraseFlash.all=Enabled
+dpu_esp32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+sonoff_dualr3.name=Sonoff DUALR3
+
+sonoff_dualr3.bootloader.tool=esptool_py
+sonoff_dualr3.bootloader.tool.default=esptool_py
+
+sonoff_dualr3.upload.tool=esptool_py
+sonoff_dualr3.upload.tool.default=esptool_py
+sonoff_dualr3.upload.tool.network=esp_ota
+
+sonoff_dualr3.upload.maximum_size=1310720
+sonoff_dualr3.upload.maximum_data_size=327680
+sonoff_dualr3.upload.flags=
+sonoff_dualr3.upload.extra_flags=
+
+sonoff_dualr3.serial.disableDTR=true
+sonoff_dualr3.serial.disableRTS=true
+
+sonoff_dualr3.build.tarch=xtensa
+sonoff_dualr3.build.bootloader_addr=0x1000
+sonoff_dualr3.build.target=esp32
+sonoff_dualr3.build.mcu=esp32
+sonoff_dualr3.build.core=esp32
+sonoff_dualr3.build.variant=esp32
+sonoff_dualr3.build.board=SONOFF_DUALR3
+
+sonoff_dualr3.build.f_cpu=240000000L
+sonoff_dualr3.build.flash_size=4MB
+sonoff_dualr3.build.flash_freq=40m
+sonoff_dualr3.build.flash_mode=dio
+sonoff_dualr3.build.boot=dio
+sonoff_dualr3.build.partitions=rainmaker
+sonoff_dualr3.build.defines=
+sonoff_dualr3.build.loop_core=
+sonoff_dualr3.build.event_core=
+
+sonoff_dualr3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+sonoff_dualr3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+sonoff_dualr3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+sonoff_dualr3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+sonoff_dualr3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+sonoff_dualr3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+sonoff_dualr3.menu.CPUFreq.240=240MHz (WiFi/BT)
+sonoff_dualr3.menu.CPUFreq.240.build.f_cpu=240000000L
+sonoff_dualr3.menu.CPUFreq.160=160MHz (WiFi/BT)
+sonoff_dualr3.menu.CPUFreq.160.build.f_cpu=160000000L
+sonoff_dualr3.menu.CPUFreq.80=80MHz (WiFi/BT)
+sonoff_dualr3.menu.CPUFreq.80.build.f_cpu=80000000L
+sonoff_dualr3.menu.CPUFreq.40=40MHz (40MHz XTAL)
+sonoff_dualr3.menu.CPUFreq.40.build.f_cpu=40000000L
+sonoff_dualr3.menu.CPUFreq.26=26MHz (26MHz XTAL)
+sonoff_dualr3.menu.CPUFreq.26.build.f_cpu=26000000L
+sonoff_dualr3.menu.CPUFreq.20=20MHz (40MHz XTAL)
+sonoff_dualr3.menu.CPUFreq.20.build.f_cpu=20000000L
+sonoff_dualr3.menu.CPUFreq.13=13MHz (26MHz XTAL)
+sonoff_dualr3.menu.CPUFreq.13.build.f_cpu=13000000L
+sonoff_dualr3.menu.CPUFreq.10=10MHz (40MHz XTAL)
+sonoff_dualr3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sonoff_dualr3.menu.FlashMode.qio=QIO
+sonoff_dualr3.menu.FlashMode.qio.build.flash_mode=dio
+sonoff_dualr3.menu.FlashMode.qio.build.boot=qio
+sonoff_dualr3.menu.FlashMode.dio=DIO
+sonoff_dualr3.menu.FlashMode.dio.build.flash_mode=dio
+sonoff_dualr3.menu.FlashMode.dio.build.boot=dio
+
+sonoff_dualr3.menu.FlashFreq.80=80MHz
+sonoff_dualr3.menu.FlashFreq.80.build.flash_freq=80m
+sonoff_dualr3.menu.FlashFreq.40=40MHz
+sonoff_dualr3.menu.FlashFreq.40.build.flash_freq=40m
+
+sonoff_dualr3.menu.FlashSize.4M=4MB (32Mb)
+sonoff_dualr3.menu.FlashSize.4M.build.flash_size=4MB
+
+sonoff_dualr3.menu.UploadSpeed.921600=921600
+sonoff_dualr3.menu.UploadSpeed.921600.upload.speed=921600
+sonoff_dualr3.menu.UploadSpeed.115200=115200
+sonoff_dualr3.menu.UploadSpeed.115200.upload.speed=115200
+sonoff_dualr3.menu.UploadSpeed.256000.windows=256000
+sonoff_dualr3.menu.UploadSpeed.256000.upload.speed=256000
+sonoff_dualr3.menu.UploadSpeed.230400.windows.upload.speed=256000
+sonoff_dualr3.menu.UploadSpeed.230400=230400
+sonoff_dualr3.menu.UploadSpeed.230400.upload.speed=230400
+sonoff_dualr3.menu.UploadSpeed.460800.linux=460800
+sonoff_dualr3.menu.UploadSpeed.460800.macosx=460800
+sonoff_dualr3.menu.UploadSpeed.460800.upload.speed=460800
+sonoff_dualr3.menu.UploadSpeed.512000.windows=512000
+sonoff_dualr3.menu.UploadSpeed.512000.upload.speed=512000
+
+sonoff_dualr3.menu.DebugLevel.none=None
+sonoff_dualr3.menu.DebugLevel.none.build.code_debug=0
+sonoff_dualr3.menu.DebugLevel.error=Error
+sonoff_dualr3.menu.DebugLevel.error.build.code_debug=1
+sonoff_dualr3.menu.DebugLevel.warn=Warn
+sonoff_dualr3.menu.DebugLevel.warn.build.code_debug=2
+sonoff_dualr3.menu.DebugLevel.info=Info
+sonoff_dualr3.menu.DebugLevel.info.build.code_debug=3
+sonoff_dualr3.menu.DebugLevel.debug=Debug
+sonoff_dualr3.menu.DebugLevel.debug.build.code_debug=4
+sonoff_dualr3.menu.DebugLevel.verbose=Verbose
+sonoff_dualr3.menu.DebugLevel.verbose.build.code_debug=5
+
+sonoff_dualr3.menu.EraseFlash.none=Disabled
+sonoff_dualr3.menu.EraseFlash.none.upload.erase_cmd=
+sonoff_dualr3.menu.EraseFlash.all=Enabled
+sonoff_dualr3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+lionbit.name=Lion:Bit Dev Board
+
+lionbit.bootloader.tool=esptool_py
+lionbit.bootloader.tool.default=esptool_py
+
+lionbit.upload.tool=esptool_py
+lionbit.upload.tool.default=esptool_py
+lionbit.upload.tool.network=esp_ota
+
+lionbit.upload.maximum_size=1310720
+lionbit.upload.maximum_data_size=327680
+lionbit.upload.flags=
+lionbit.upload.extra_flags=
+
+lionbit.serial.disableDTR=true
+lionbit.serial.disableRTS=true
+
+lionbit.build.tarch=xtensa
+lionbit.build.bootloader_addr=0x1000
+lionbit.build.target=esp32
+lionbit.build.mcu=esp32
+lionbit.build.core=esp32
+lionbit.build.variant=lionbit
+lionbit.build.board=Lion:Bit_Dev_Board
+
+lionbit.build.f_cpu=240000000L
+lionbit.build.flash_size=4MB
+lionbit.build.flash_freq=80m
+lionbit.build.flash_mode=dio
+lionbit.build.boot=dio
+lionbit.build.partitions=default
+lionbit.build.defines=
+lionbit.build.loop_core=
+lionbit.build.event_core=
+
+
+lionbit.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lionbit.menu.PartitionScheme.default.build.partitions=default
+lionbit.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lionbit.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lionbit.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+lionbit.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+lionbit.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+lionbit.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+lionbit.menu.PartitionScheme.minimal.build.partitions=minimal
+lionbit.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lionbit.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lionbit.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lionbit.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lionbit.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lionbit.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lionbit.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lionbit.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lionbit.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lionbit.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lionbit.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lionbit.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lionbit.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lionbit.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lionbit.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+lionbit.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+lionbit.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+lionbit.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+lionbit.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+lionbit.menu.PartitionScheme.fatflash.build.partitions=ffat
+lionbit.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+lionbit.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+lionbit.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+lionbit.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+lionbit.menu.PartitionScheme.rainmaker=RainMaker 4MB
+lionbit.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+lionbit.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+lionbit.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+lionbit.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+lionbit.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+lionbit.menu.CPUFreq.240=240MHz (WiFi/BT)
+lionbit.menu.CPUFreq.240.build.f_cpu=240000000L
+lionbit.menu.CPUFreq.160=160MHz (WiFi/BT)
+lionbit.menu.CPUFreq.160.build.f_cpu=160000000L
+lionbit.menu.CPUFreq.80=80MHz (WiFi/BT)
+lionbit.menu.CPUFreq.80.build.f_cpu=80000000L
+lionbit.menu.CPUFreq.40=40MHz (40MHz XTAL)
+lionbit.menu.CPUFreq.40.build.f_cpu=40000000L
+lionbit.menu.CPUFreq.26=26MHz (26MHz XTAL)
+lionbit.menu.CPUFreq.26.build.f_cpu=26000000L
+lionbit.menu.CPUFreq.20=20MHz (40MHz XTAL)
+lionbit.menu.CPUFreq.20.build.f_cpu=20000000L
+lionbit.menu.CPUFreq.13=13MHz (26MHz XTAL)
+lionbit.menu.CPUFreq.13.build.f_cpu=13000000L
+lionbit.menu.CPUFreq.10=10MHz (40MHz XTAL)
+lionbit.menu.CPUFreq.10.build.f_cpu=10000000L
+
+
+lionbit.menu.FlashMode.dio=DIO
+lionbit.menu.FlashMode.dio.build.flash_mode=dio
+lionbit.menu.FlashMode.dio.build.boot=dio
+lionbit.menu.FlashMode.qio=QIO
+lionbit.menu.FlashMode.qio.build.flash_mode=dio
+lionbit.menu.FlashMode.qio.build.boot=qio
+
+lionbit.menu.FlashFreq.80=80MHz
+lionbit.menu.FlashFreq.80.build.flash_freq=80m
+lionbit.menu.FlashFreq.40=40MHz
+lionbit.menu.FlashFreq.40.build.flash_freq=40m
+
+lionbit.menu.FlashSize.4M=4MB (32Mb)
+lionbit.menu.FlashSize.4M.build.flash_size=4MB
+
+
+
+lionbit.menu.UploadSpeed.115200=115200
+lionbit.menu.UploadSpeed.115200.upload.speed=115200
+lionbit.menu.UploadSpeed.256000.windows=256000
+lionbit.menu.UploadSpeed.256000.upload.speed=256000
+lionbit.menu.UploadSpeed.230400.windows.upload.speed=256000
+lionbit.menu.UploadSpeed.230400=230400
+lionbit.menu.UploadSpeed.230400.upload.speed=230400
+lionbit.menu.UploadSpeed.460800.linux=460800
+lionbit.menu.UploadSpeed.460800.macosx=460800
+lionbit.menu.UploadSpeed.460800.upload.speed=460800
+
+
+lionbit.menu.LoopCore.1=Core 1
+lionbit.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lionbit.menu.LoopCore.0=Core 0
+lionbit.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lionbit.menu.EventsCore.1=Core 1
+lionbit.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lionbit.menu.EventsCore.0=Core 0
+lionbit.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lionbit.menu.DebugLevel.none=None
+lionbit.menu.DebugLevel.none.build.code_debug=0
+lionbit.menu.DebugLevel.error=Error
+lionbit.menu.DebugLevel.error.build.code_debug=1
+lionbit.menu.DebugLevel.warn=Warn
+lionbit.menu.DebugLevel.warn.build.code_debug=2
+lionbit.menu.DebugLevel.info=Info
+lionbit.menu.DebugLevel.info.build.code_debug=3
+lionbit.menu.DebugLevel.debug=Debug
+lionbit.menu.DebugLevel.debug.build.code_debug=4
+lionbit.menu.DebugLevel.verbose=Verbose
+lionbit.menu.DebugLevel.verbose.build.code_debug=5
+
+lionbit.menu.EraseFlash.none=Disabled
+lionbit.menu.EraseFlash.none.upload.erase_cmd=
+lionbit.menu.EraseFlash.all=Enabled
+lionbit.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+watchy.name=Watchy
+
+watchy.bootloader.tool=esptool_py
+watchy.bootloader.tool.default=esptool_py
+
+watchy.upload.tool=esptool_py
+watchy.upload.tool.default=esptool_py
+watchy.upload.tool.network=esp_ota
+
+watchy.upload.maximum_size=1310720
+watchy.upload.maximum_data_size=327680
+watchy.upload.flags=
+watchy.upload.extra_flags=
+
+watchy.serial.disableDTR=true
+watchy.serial.disableRTS=true
+
+watchy.build.tarch=xtensa
+watchy.build.bootloader_addr=0x1000
+watchy.build.target=esp32
+watchy.build.mcu=esp32
+watchy.build.core=esp32
+watchy.build.variant=watchy
+watchy.build.board=WATCHY
+
+watchy.build.f_cpu=240000000L
+watchy.build.flash_size=4MB
+watchy.build.flash_freq=80m
+watchy.build.flash_mode=dio
+watchy.build.boot=qio
+watchy.build.partitions=min_spiffs
+watchy.build.defines=
+
+watchy.menu.Revision.v10=Watchy v1.0
+watchy.menu.Revision.v10.build.board=WATCHY_V10
+watchy.menu.Revision.v15=Watchy v1.5
+watchy.menu.Revision.v15.build.board=WATCHY_V15
+watchy.menu.Revision.v20=Watchy v2.0
+watchy.menu.Revision.v20.build.board=WATCHY_V20
+
+watchy.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+watchy.menu.PartitionScheme.huge_app.build.partitions=huge_app
+watchy.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+watchy.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+watchy.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+watchy.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+watchy.menu.UploadSpeed.921600=921600
+watchy.menu.UploadSpeed.921600.upload.speed=921600
+watchy.menu.UploadSpeed.115200=115200
+watchy.menu.UploadSpeed.115200.upload.speed=115200
+watchy.menu.UploadSpeed.256000.windows=256000
+watchy.menu.UploadSpeed.256000.upload.speed=256000
+watchy.menu.UploadSpeed.230400.windows.upload.speed=256000
+watchy.menu.UploadSpeed.230400=230400
+watchy.menu.UploadSpeed.230400.upload.speed=230400
+watchy.menu.UploadSpeed.460800.linux=460800
+watchy.menu.UploadSpeed.460800.macosx=460800
+watchy.menu.UploadSpeed.460800.upload.speed=460800
+watchy.menu.UploadSpeed.512000.windows=512000
+watchy.menu.UploadSpeed.512000.upload.speed=512000
+
+watchy.menu.DebugLevel.none=None
+watchy.menu.DebugLevel.none.build.code_debug=0
+watchy.menu.DebugLevel.error=Error
+watchy.menu.DebugLevel.error.build.code_debug=1
+watchy.menu.DebugLevel.warn=Warn
+watchy.menu.DebugLevel.warn.build.code_debug=2
+watchy.menu.DebugLevel.info=Info
+watchy.menu.DebugLevel.info.build.code_debug=3
+watchy.menu.DebugLevel.debug=Debug
+watchy.menu.DebugLevel.debug.build.code_debug=4
+watchy.menu.DebugLevel.verbose=Verbose
+watchy.menu.DebugLevel.verbose.build.code_debug=5
+
+watchy.menu.EraseFlash.none=Disabled
+watchy.menu.EraseFlash.none.upload.erase_cmd=
+watchy.menu.EraseFlash.all=Enabled
+watchy.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+AirM2M_CORE_ESP32C3.name=AirM2M_CORE_ESP32C3
+
+AirM2M_CORE_ESP32C3.upload.tool=esptool_py
+AirM2M_CORE_ESP32C3.upload.tool.default=esptool_py
+AirM2M_CORE_ESP32C3.upload.tool.network=esp_ota
+AirM2M_CORE_ESP32C3.upload.maximum_size=1310720
+AirM2M_CORE_ESP32C3.upload.maximum_data_size=327680
+AirM2M_CORE_ESP32C3.upload.flags=
+AirM2M_CORE_ESP32C3.upload.extra_flags=
+AirM2M_CORE_ESP32C3.upload.use_1200bps_touch=false
+AirM2M_CORE_ESP32C3.upload.wait_for_upload_port=false
+
+AirM2M_CORE_ESP32C3.serial.disableDTR=false
+AirM2M_CORE_ESP32C3.serial.disableRTS=false
+
+AirM2M_CORE_ESP32C3.build.tarch=riscv32
+AirM2M_CORE_ESP32C3.build.target=esp
+AirM2M_CORE_ESP32C3.build.mcu=esp32c3
+AirM2M_CORE_ESP32C3.build.core=esp32
+AirM2M_CORE_ESP32C3.build.variant=AirM2M_CORE_ESP32C3
+AirM2M_CORE_ESP32C3.build.board=AirM2M_CORE_ESP32C3
+AirM2M_CORE_ESP32C3.build.bootloader_addr=0x0
+
+AirM2M_CORE_ESP32C3.build.cdc_on_boot=0
+AirM2M_CORE_ESP32C3.build.f_cpu=160000000L
+AirM2M_CORE_ESP32C3.build.flash_size=4MB
+AirM2M_CORE_ESP32C3.build.flash_freq=80m
+AirM2M_CORE_ESP32C3.build.flash_mode=dio
+AirM2M_CORE_ESP32C3.build.boot=dio
+AirM2M_CORE_ESP32C3.build.partitions=default
+AirM2M_CORE_ESP32C3.build.defines=
+
+AirM2M_CORE_ESP32C3.menu.CDCOnBoot.default=Disabled
+AirM2M_CORE_ESP32C3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+AirM2M_CORE_ESP32C3.menu.CDCOnBoot.cdc=Enabled
+AirM2M_CORE_ESP32C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.default.build.partitions=default
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.minimal.build.partitions=minimal
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+AirM2M_CORE_ESP32C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+AirM2M_CORE_ESP32C3.menu.CPUFreq.160=160MHz (WiFi)
+AirM2M_CORE_ESP32C3.menu.CPUFreq.160.build.f_cpu=160000000L
+AirM2M_CORE_ESP32C3.menu.CPUFreq.80=80MHz (WiFi)
+AirM2M_CORE_ESP32C3.menu.CPUFreq.80.build.f_cpu=80000000L
+AirM2M_CORE_ESP32C3.menu.CPUFreq.40=40MHz
+AirM2M_CORE_ESP32C3.menu.CPUFreq.40.build.f_cpu=40000000L
+AirM2M_CORE_ESP32C3.menu.CPUFreq.20=20MHz
+AirM2M_CORE_ESP32C3.menu.CPUFreq.20.build.f_cpu=20000000L
+AirM2M_CORE_ESP32C3.menu.CPUFreq.10=10MHz
+AirM2M_CORE_ESP32C3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+AirM2M_CORE_ESP32C3.menu.FlashFreq.80=80MHz
+AirM2M_CORE_ESP32C3.menu.FlashFreq.80.build.flash_freq=80m
+AirM2M_CORE_ESP32C3.menu.FlashFreq.40=40MHz
+AirM2M_CORE_ESP32C3.menu.FlashFreq.40.build.flash_freq=40m
+
+AirM2M_CORE_ESP32C3.menu.UploadSpeed.921600=921600
+AirM2M_CORE_ESP32C3.menu.UploadSpeed.921600.upload.speed=921600
+AirM2M_CORE_ESP32C3.menu.UploadSpeed.115200=115200
+AirM2M_CORE_ESP32C3.menu.UploadSpeed.115200.upload.speed=115200
+AirM2M_CORE_ESP32C3.menu.UploadSpeed.1152000=1152000
+AirM2M_CORE_ESP32C3.menu.UploadSpeed.1152000.upload.speed=1152000
+
+
+AirM2M_CORE_ESP32C3.menu.DebugLevel.none=None
+AirM2M_CORE_ESP32C3.menu.DebugLevel.none.build.code_debug=0
+AirM2M_CORE_ESP32C3.menu.DebugLevel.error=Error
+AirM2M_CORE_ESP32C3.menu.DebugLevel.error.build.code_debug=1
+AirM2M_CORE_ESP32C3.menu.DebugLevel.warn=Warn
+AirM2M_CORE_ESP32C3.menu.DebugLevel.warn.build.code_debug=2
+AirM2M_CORE_ESP32C3.menu.DebugLevel.info=Info
+AirM2M_CORE_ESP32C3.menu.DebugLevel.info.build.code_debug=3
+AirM2M_CORE_ESP32C3.menu.DebugLevel.debug=Debug
+AirM2M_CORE_ESP32C3.menu.DebugLevel.debug.build.code_debug=4
+AirM2M_CORE_ESP32C3.menu.DebugLevel.verbose=Verbose
+AirM2M_CORE_ESP32C3.menu.DebugLevel.verbose.build.code_debug=5
+
+AirM2M_CORE_ESP32C3.menu.EraseFlash.none=Disabled
+AirM2M_CORE_ESP32C3.menu.EraseFlash.none.upload.erase_cmd=
+AirM2M_CORE_ESP32C3.menu.EraseFlash.all=Enabled
+AirM2M_CORE_ESP32C3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+#############################################################
+
+
+XIAO_ESP32C3.name=XIAO_ESP32C3
+XIAO_ESP32C3.vid.0=0x2886
+XIAO_ESP32C3.pid.0=0x0046
+
+XIAO_ESP32C3.bootloader.tool=esptool_py
+XIAO_ESP32C3.bootloader.tool.default=esptool_py
+
+XIAO_ESP32C3.upload.tool=esptool_py
+XIAO_ESP32C3.upload.tool.default=esptool_py
+XIAO_ESP32C3.upload.tool.network=esp_ota
+
+XIAO_ESP32C3.upload.maximum_size=1310720
+XIAO_ESP32C3.upload.maximum_data_size=327680
+XIAO_ESP32C3.upload.flags=
+XIAO_ESP32C3.upload.extra_flags=
+XIAO_ESP32C3.upload.use_1200bps_touch=false
+XIAO_ESP32C3.upload.wait_for_upload_port=false
+
+XIAO_ESP32C3.serial.disableDTR=false
+XIAO_ESP32C3.serial.disableRTS=false
+
+XIAO_ESP32C3.build.tarch=riscv32
+XIAO_ESP32C3.build.target=esp
+XIAO_ESP32C3.build.mcu=esp32c3
+XIAO_ESP32C3.build.core=esp32
+XIAO_ESP32C3.build.variant=XIAO_ESP32C3
+XIAO_ESP32C3.build.board=XIAO_ESP32C3
+XIAO_ESP32C3.build.bootloader_addr=0x0
+
+XIAO_ESP32C3.build.cdc_on_boot=1
+XIAO_ESP32C3.build.f_cpu=160000000L
+XIAO_ESP32C3.build.flash_size=4MB
+XIAO_ESP32C3.build.flash_freq=80m
+XIAO_ESP32C3.build.flash_mode=qio
+XIAO_ESP32C3.build.boot=qio
+XIAO_ESP32C3.build.partitions=default
+XIAO_ESP32C3.build.defines=
+
+XIAO_ESP32C3.menu.CDCOnBoot.default=Enabled
+XIAO_ESP32C3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+XIAO_ESP32C3.menu.CDCOnBoot.cdc=Disabled
+XIAO_ESP32C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+XIAO_ESP32C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+XIAO_ESP32C3.menu.PartitionScheme.default.build.partitions=default
+XIAO_ESP32C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+XIAO_ESP32C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+XIAO_ESP32C3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+XIAO_ESP32C3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+XIAO_ESP32C3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+XIAO_ESP32C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+XIAO_ESP32C3.menu.PartitionScheme.minimal.build.partitions=minimal
+XIAO_ESP32C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+XIAO_ESP32C3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+XIAO_ESP32C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+XIAO_ESP32C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+XIAO_ESP32C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+XIAO_ESP32C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+XIAO_ESP32C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+XIAO_ESP32C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+XIAO_ESP32C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+XIAO_ESP32C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+XIAO_ESP32C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+XIAO_ESP32C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+XIAO_ESP32C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+XIAO_ESP32C3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+XIAO_ESP32C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+XIAO_ESP32C3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+XIAO_ESP32C3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+XIAO_ESP32C3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+XIAO_ESP32C3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+XIAO_ESP32C3.menu.PartitionScheme.fatflash.build.partitions=ffat
+XIAO_ESP32C3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+XIAO_ESP32C3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+XIAO_ESP32C3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+XIAO_ESP32C3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+XIAO_ESP32C3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+XIAO_ESP32C3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+XIAO_ESP32C3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+XIAO_ESP32C3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+XIAO_ESP32C3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+XIAO_ESP32C3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+XIAO_ESP32C3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+XIAO_ESP32C3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+XIAO_ESP32C3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+XIAO_ESP32C3.menu.CPUFreq.160=160MHz (WiFi)
+XIAO_ESP32C3.menu.CPUFreq.160.build.f_cpu=160000000L
+XIAO_ESP32C3.menu.CPUFreq.80=80MHz (WiFi)
+XIAO_ESP32C3.menu.CPUFreq.80.build.f_cpu=80000000L
+XIAO_ESP32C3.menu.CPUFreq.40=40MHz
+XIAO_ESP32C3.menu.CPUFreq.40.build.f_cpu=40000000L
+XIAO_ESP32C3.menu.CPUFreq.20=20MHz
+XIAO_ESP32C3.menu.CPUFreq.20.build.f_cpu=20000000L
+XIAO_ESP32C3.menu.CPUFreq.10=10MHz
+XIAO_ESP32C3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+XIAO_ESP32C3.menu.FlashMode.qio=QIO
+XIAO_ESP32C3.menu.FlashMode.qio.build.flash_mode=dio
+XIAO_ESP32C3.menu.FlashMode.qio.build.boot=qio
+XIAO_ESP32C3.menu.FlashMode.dio=DIO
+XIAO_ESP32C3.menu.FlashMode.dio.build.flash_mode=dio
+XIAO_ESP32C3.menu.FlashMode.dio.build.boot=dio
+
+XIAO_ESP32C3.menu.FlashFreq.80=80MHz
+XIAO_ESP32C3.menu.FlashFreq.80.build.flash_freq=80m
+XIAO_ESP32C3.menu.FlashFreq.40=40MHz
+XIAO_ESP32C3.menu.FlashFreq.40.build.flash_freq=40m
+
+XIAO_ESP32C3.menu.FlashSize.4M=4MB (32Mb)
+XIAO_ESP32C3.menu.FlashSize.4M.build.flash_size=4MB
+XIAO_ESP32C3.menu.FlashSize.8M=8MB (64Mb)
+XIAO_ESP32C3.menu.FlashSize.8M.build.flash_size=8MB
+XIAO_ESP32C3.menu.FlashSize.2M=2MB (16Mb)
+XIAO_ESP32C3.menu.FlashSize.2M.build.flash_size=2MB
+XIAO_ESP32C3.menu.FlashSize.16M=16MB (128Mb)
+XIAO_ESP32C3.menu.FlashSize.16M.build.flash_size=16MB
+
+XIAO_ESP32C3.menu.UploadSpeed.921600=921600
+XIAO_ESP32C3.menu.UploadSpeed.921600.upload.speed=921600
+XIAO_ESP32C3.menu.UploadSpeed.115200=115200
+XIAO_ESP32C3.menu.UploadSpeed.115200.upload.speed=115200
+XIAO_ESP32C3.menu.UploadSpeed.256000.windows=256000
+XIAO_ESP32C3.menu.UploadSpeed.256000.upload.speed=256000
+XIAO_ESP32C3.menu.UploadSpeed.230400.windows.upload.speed=256000
+XIAO_ESP32C3.menu.UploadSpeed.230400=230400
+XIAO_ESP32C3.menu.UploadSpeed.230400.upload.speed=230400
+XIAO_ESP32C3.menu.UploadSpeed.460800.linux=460800
+XIAO_ESP32C3.menu.UploadSpeed.460800.macosx=460800
+XIAO_ESP32C3.menu.UploadSpeed.460800.upload.speed=460800
+XIAO_ESP32C3.menu.UploadSpeed.512000.windows=512000
+XIAO_ESP32C3.menu.UploadSpeed.512000.upload.speed=512000
+
+XIAO_ESP32C3.menu.DebugLevel.none=None
+XIAO_ESP32C3.menu.DebugLevel.none.build.code_debug=0
+XIAO_ESP32C3.menu.DebugLevel.error=Error
+XIAO_ESP32C3.menu.DebugLevel.error.build.code_debug=1
+XIAO_ESP32C3.menu.DebugLevel.warn=Warn
+XIAO_ESP32C3.menu.DebugLevel.warn.build.code_debug=2
+XIAO_ESP32C3.menu.DebugLevel.info=Info
+XIAO_ESP32C3.menu.DebugLevel.info.build.code_debug=3
+XIAO_ESP32C3.menu.DebugLevel.debug=Debug
+XIAO_ESP32C3.menu.DebugLevel.debug.build.code_debug=4
+XIAO_ESP32C3.menu.DebugLevel.verbose=Verbose
+XIAO_ESP32C3.menu.DebugLevel.verbose.build.code_debug=5
+
+XIAO_ESP32C3.menu.EraseFlash.none=Disabled
+XIAO_ESP32C3.menu.EraseFlash.none.upload.erase_cmd=
+XIAO_ESP32C3.menu.EraseFlash.all=Enabled
+XIAO_ESP32C3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+XIAO_ESP32C6.name=XIAO_ESP32C6
+
+XIAO_ESP32C6.bootloader.tool=esptool_py
+XIAO_ESP32C6.bootloader.tool.default=esptool_py
+
+XIAO_ESP32C6.upload.tool=esptool_py
+XIAO_ESP32C6.upload.tool.default=esptool_py
+XIAO_ESP32C6.upload.tool.network=esp_ota
+
+XIAO_ESP32C6.upload.maximum_size=1310720
+XIAO_ESP32C6.upload.maximum_data_size=327680
+XIAO_ESP32C6.upload.flags=
+XIAO_ESP32C6.upload.extra_flags=
+XIAO_ESP32C6.upload.use_1200bps_touch=false
+XIAO_ESP32C6.upload.wait_for_upload_port=false
+
+XIAO_ESP32C6.serial.disableDTR=false
+XIAO_ESP32C6.serial.disableRTS=false
+
+XIAO_ESP32C6.build.tarch=riscv32
+XIAO_ESP32C6.build.target=esp
+XIAO_ESP32C6.build.mcu=esp32c6
+XIAO_ESP32C6.build.core=esp32
+XIAO_ESP32C6.build.variant=XIAO_ESP32C6
+XIAO_ESP32C6.build.board=XIAO_ESP32C6
+XIAO_ESP32C6.build.bootloader_addr=0x0
+
+XIAO_ESP32C6.build.cdc_on_boot=1
+XIAO_ESP32C6.build.f_cpu=160000000L
+XIAO_ESP32C6.build.flash_size=4MB
+XIAO_ESP32C6.build.flash_freq=80m
+XIAO_ESP32C6.build.flash_mode=qio
+XIAO_ESP32C6.build.boot=qio
+XIAO_ESP32C6.build.partitions=default
+XIAO_ESP32C6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+XIAO_ESP32C6.menu.JTAGAdapter.default=Disabled
+XIAO_ESP32C6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+XIAO_ESP32C6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+XIAO_ESP32C6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+XIAO_ESP32C6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+XIAO_ESP32C6.menu.JTAGAdapter.external=FTDI Adapter
+XIAO_ESP32C6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+XIAO_ESP32C6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+XIAO_ESP32C6.menu.JTAGAdapter.bridge=ESP USB Bridge
+XIAO_ESP32C6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+XIAO_ESP32C6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+XIAO_ESP32C6.menu.CDCOnBoot.cdc=Enabled
+XIAO_ESP32C6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+XIAO_ESP32C6.menu.CDCOnBoot.default=Disabled
+XIAO_ESP32C6.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+XIAO_ESP32C6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+XIAO_ESP32C6.menu.PartitionScheme.default.build.partitions=default
+XIAO_ESP32C6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+XIAO_ESP32C6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+XIAO_ESP32C6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+XIAO_ESP32C6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+XIAO_ESP32C6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+XIAO_ESP32C6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+XIAO_ESP32C6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+XIAO_ESP32C6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+XIAO_ESP32C6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+XIAO_ESP32C6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+XIAO_ESP32C6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+XIAO_ESP32C6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+XIAO_ESP32C6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+XIAO_ESP32C6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+XIAO_ESP32C6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+XIAO_ESP32C6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+XIAO_ESP32C6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+XIAO_ESP32C6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+XIAO_ESP32C6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+XIAO_ESP32C6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+XIAO_ESP32C6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+XIAO_ESP32C6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+XIAO_ESP32C6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+
+XIAO_ESP32C6.menu.CPUFreq.160=160MHz (WiFi)
+XIAO_ESP32C6.menu.CPUFreq.160.build.f_cpu=160000000L
+XIAO_ESP32C6.menu.CPUFreq.80=80MHz (WiFi)
+XIAO_ESP32C6.menu.CPUFreq.80.build.f_cpu=80000000L
+XIAO_ESP32C6.menu.CPUFreq.40=40MHz
+XIAO_ESP32C6.menu.CPUFreq.40.build.f_cpu=40000000L
+XIAO_ESP32C6.menu.CPUFreq.20=20MHz
+XIAO_ESP32C6.menu.CPUFreq.20.build.f_cpu=20000000L
+XIAO_ESP32C6.menu.CPUFreq.10=10MHz
+XIAO_ESP32C6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+XIAO_ESP32C6.menu.FlashMode.qio=QIO
+XIAO_ESP32C6.menu.FlashMode.qio.build.flash_mode=dio
+XIAO_ESP32C6.menu.FlashMode.qio.build.boot=qio
+XIAO_ESP32C6.menu.FlashMode.dio=DIO
+XIAO_ESP32C6.menu.FlashMode.dio.build.flash_mode=dio
+XIAO_ESP32C6.menu.FlashMode.dio.build.boot=dio
+
+XIAO_ESP32C6.menu.FlashFreq.80=80MHz
+XIAO_ESP32C6.menu.FlashFreq.80.build.flash_freq=80m
+XIAO_ESP32C6.menu.FlashFreq.40=40MHz
+XIAO_ESP32C6.menu.FlashFreq.40.build.flash_freq=40m
+
+XIAO_ESP32C6.menu.FlashSize.4M=4MB (32Mb)
+XIAO_ESP32C6.menu.FlashSize.4M.build.flash_size=4MB
+
+XIAO_ESP32C6.menu.UploadSpeed.921600=921600
+XIAO_ESP32C6.menu.UploadSpeed.921600.upload.speed=921600
+XIAO_ESP32C6.menu.UploadSpeed.115200=115200
+XIAO_ESP32C6.menu.UploadSpeed.115200.upload.speed=115200
+XIAO_ESP32C6.menu.UploadSpeed.256000.windows=256000
+XIAO_ESP32C6.menu.UploadSpeed.256000.upload.speed=256000
+XIAO_ESP32C6.menu.UploadSpeed.230400.windows.upload.speed=256000
+XIAO_ESP32C6.menu.UploadSpeed.230400=230400
+XIAO_ESP32C6.menu.UploadSpeed.230400.upload.speed=230400
+XIAO_ESP32C6.menu.UploadSpeed.460800.linux=460800
+XIAO_ESP32C6.menu.UploadSpeed.460800.macosx=460800
+XIAO_ESP32C6.menu.UploadSpeed.460800.upload.speed=460800
+XIAO_ESP32C6.menu.UploadSpeed.512000.windows=512000
+XIAO_ESP32C6.menu.UploadSpeed.512000.upload.speed=512000
+
+XIAO_ESP32C6.menu.DebugLevel.none=None
+XIAO_ESP32C6.menu.DebugLevel.none.build.code_debug=0
+XIAO_ESP32C6.menu.DebugLevel.error=Error
+XIAO_ESP32C6.menu.DebugLevel.error.build.code_debug=1
+XIAO_ESP32C6.menu.DebugLevel.warn=Warn
+XIAO_ESP32C6.menu.DebugLevel.warn.build.code_debug=2
+XIAO_ESP32C6.menu.DebugLevel.info=Info
+XIAO_ESP32C6.menu.DebugLevel.info.build.code_debug=3
+XIAO_ESP32C6.menu.DebugLevel.debug=Debug
+XIAO_ESP32C6.menu.DebugLevel.debug.build.code_debug=4
+XIAO_ESP32C6.menu.DebugLevel.verbose=Verbose
+XIAO_ESP32C6.menu.DebugLevel.verbose.build.code_debug=5
+
+XIAO_ESP32C6.menu.EraseFlash.none=Disabled
+XIAO_ESP32C6.menu.EraseFlash.none.upload.erase_cmd=
+XIAO_ESP32C6.menu.EraseFlash.all=Enabled
+XIAO_ESP32C6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+XIAO_ESP32C6.menu.ZigbeeMode.default=Disabled
+XIAO_ESP32C6.menu.ZigbeeMode.default.build.zigbee_mode=
+XIAO_ESP32C6.menu.ZigbeeMode.default.build.zigbee_libs=
+XIAO_ESP32C6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+XIAO_ESP32C6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+XIAO_ESP32C6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+XIAO_ESP32C6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+XIAO_ESP32C6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+XIAO_ESP32C6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+XIAO_ESP32S3.name=XIAO_ESP32S3
+XIAO_ESP32S3.vid.0=0x2886
+XIAO_ESP32S3.pid.0=0x0056
+XIAO_ESP32S3.vid.1=0x2886
+XIAO_ESP32S3.pid.1=0x8056
+
+XIAO_ESP32S3.bootloader.tool=esptool_py
+XIAO_ESP32S3.bootloader.tool.default=esptool_py
+
+XIAO_ESP32S3.upload.tool=esptool_py
+XIAO_ESP32S3.upload.tool.default=esptool_py
+XIAO_ESP32S3.upload.tool.network=esp_ota
+
+XIAO_ESP32S3.upload.maximum_size=1310720
+XIAO_ESP32S3.upload.maximum_data_size=327680
+XIAO_ESP32S3.upload.flags=
+XIAO_ESP32S3.upload.extra_flags=
+XIAO_ESP32S3.upload.use_1200bps_touch=false
+XIAO_ESP32S3.upload.wait_for_upload_port=false
+
+XIAO_ESP32S3.serial.disableDTR=false
+XIAO_ESP32S3.serial.disableRTS=false
+
+XIAO_ESP32S3.build.tarch=xtensa
+XIAO_ESP32S3.build.bootloader_addr=0x0
+XIAO_ESP32S3.build.target=esp32s3
+XIAO_ESP32S3.build.mcu=esp32s3
+XIAO_ESP32S3.build.core=esp32
+XIAO_ESP32S3.build.variant=XIAO_ESP32S3
+XIAO_ESP32S3.build.board=XIAO_ESP32S3
+
+XIAO_ESP32S3.build.usb_mode=0
+XIAO_ESP32S3.build.cdc_on_boot=1
+XIAO_ESP32S3.build.msc_on_boot=0
+XIAO_ESP32S3.build.dfu_on_boot=0
+XIAO_ESP32S3.build.f_cpu=240000000L
+XIAO_ESP32S3.build.flash_size=8MB
+XIAO_ESP32S3.build.flash_freq=80m
+XIAO_ESP32S3.build.flash_mode=dio
+XIAO_ESP32S3.build.boot=qio
+XIAO_ESP32S3.build.boot_freq=80m
+XIAO_ESP32S3.build.partitions=default_8MB
+XIAO_ESP32S3.build.defines=
+XIAO_ESP32S3.build.loop_core=
+XIAO_ESP32S3.build.event_core=
+XIAO_ESP32S3.build.psram_type=qspi
+XIAO_ESP32S3.build.memory_type={build.boot}_{build.psram_type}
+
+XIAO_ESP32S3.menu.JTAGAdapter.default=Disabled
+XIAO_ESP32S3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+XIAO_ESP32S3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+XIAO_ESP32S3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+XIAO_ESP32S3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+XIAO_ESP32S3.menu.JTAGAdapter.external=FTDI Adapter
+XIAO_ESP32S3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+XIAO_ESP32S3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+XIAO_ESP32S3.menu.JTAGAdapter.bridge=ESP USB Bridge
+XIAO_ESP32S3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+XIAO_ESP32S3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+XIAO_ESP32S3.menu.PSRAM.disabled=Disabled
+XIAO_ESP32S3.menu.PSRAM.disabled.build.defines=
+XIAO_ESP32S3.menu.PSRAM.disabled.build.psram_type=qspi
+XIAO_ESP32S3.menu.PSRAM.opi=OPI PSRAM
+XIAO_ESP32S3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+XIAO_ESP32S3.menu.PSRAM.opi.build.psram_type=opi
+
+XIAO_ESP32S3.menu.FlashMode.qio=QIO 80MHz
+XIAO_ESP32S3.menu.FlashMode.qio.build.flash_mode=dio
+XIAO_ESP32S3.menu.FlashMode.qio.build.boot=qio
+XIAO_ESP32S3.menu.FlashMode.qio.build.boot_freq=80m
+XIAO_ESP32S3.menu.FlashMode.qio.build.flash_freq=80m
+XIAO_ESP32S3.menu.FlashMode.dio=DIO 80MHz
+XIAO_ESP32S3.menu.FlashMode.dio.build.flash_mode=dio
+XIAO_ESP32S3.menu.FlashMode.dio.build.boot=dio
+XIAO_ESP32S3.menu.FlashMode.dio.build.boot_freq=80m
+XIAO_ESP32S3.menu.FlashMode.dio.build.flash_freq=80m
+
+XIAO_ESP32S3.menu.FlashSize.8M=8MB (64Mb)
+XIAO_ESP32S3.menu.FlashSize.8M.build.flash_size=8MB
+
+XIAO_ESP32S3.menu.LoopCore.1=Core 1
+XIAO_ESP32S3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+XIAO_ESP32S3.menu.LoopCore.0=Core 0
+XIAO_ESP32S3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+XIAO_ESP32S3.menu.EventsCore.1=Core 1
+XIAO_ESP32S3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+XIAO_ESP32S3.menu.EventsCore.0=Core 0
+XIAO_ESP32S3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+XIAO_ESP32S3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+XIAO_ESP32S3.menu.USBMode.hwcdc.build.usb_mode=1
+XIAO_ESP32S3.menu.USBMode.default=USB-OTG (TinyUSB)
+XIAO_ESP32S3.menu.USBMode.default.build.usb_mode=0
+
+XIAO_ESP32S3.menu.CDCOnBoot.default=Enabled
+XIAO_ESP32S3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+XIAO_ESP32S3.menu.CDCOnBoot.cdc=Disabled
+XIAO_ESP32S3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+XIAO_ESP32S3.menu.MSCOnBoot.default=Disabled
+XIAO_ESP32S3.menu.MSCOnBoot.default.build.msc_on_boot=0
+XIAO_ESP32S3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+XIAO_ESP32S3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+XIAO_ESP32S3.menu.DFUOnBoot.default=Disabled
+XIAO_ESP32S3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+XIAO_ESP32S3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+XIAO_ESP32S3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+XIAO_ESP32S3.menu.UploadMode.default=UART0 / Hardware CDC
+XIAO_ESP32S3.menu.UploadMode.default.upload.use_1200bps_touch=false
+XIAO_ESP32S3.menu.UploadMode.default.upload.wait_for_upload_port=false
+XIAO_ESP32S3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+XIAO_ESP32S3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+XIAO_ESP32S3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+XIAO_ESP32S3.menu.PartitionScheme.default_8MB=Default with spiffs (3MB APP/1.5MB SPIFFS)
+XIAO_ESP32S3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+XIAO_ESP32S3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+XIAO_ESP32S3.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS)
+XIAO_ESP32S3.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB
+XIAO_ESP32S3.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536
+XIAO_ESP32S3.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FFAT)
+XIAO_ESP32S3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+XIAO_ESP32S3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-8MB-tinyuf2
+XIAO_ESP32S3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+XIAO_ESP32S3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+
+XIAO_ESP32S3.menu.CPUFreq.240=240MHz (WiFi)
+XIAO_ESP32S3.menu.CPUFreq.240.build.f_cpu=240000000L
+XIAO_ESP32S3.menu.CPUFreq.160=160MHz (WiFi)
+XIAO_ESP32S3.menu.CPUFreq.160.build.f_cpu=160000000L
+XIAO_ESP32S3.menu.CPUFreq.80=80MHz (WiFi)
+XIAO_ESP32S3.menu.CPUFreq.80.build.f_cpu=80000000L
+XIAO_ESP32S3.menu.CPUFreq.40=40MHz
+XIAO_ESP32S3.menu.CPUFreq.40.build.f_cpu=40000000L
+XIAO_ESP32S3.menu.CPUFreq.20=20MHz
+XIAO_ESP32S3.menu.CPUFreq.20.build.f_cpu=20000000L
+XIAO_ESP32S3.menu.CPUFreq.10=10MHz
+XIAO_ESP32S3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+XIAO_ESP32S3.menu.UploadSpeed.921600=921600
+XIAO_ESP32S3.menu.UploadSpeed.921600.upload.speed=921600
+XIAO_ESP32S3.menu.UploadSpeed.115200=115200
+XIAO_ESP32S3.menu.UploadSpeed.115200.upload.speed=115200
+XIAO_ESP32S3.menu.UploadSpeed.256000.windows=256000
+XIAO_ESP32S3.menu.UploadSpeed.256000.upload.speed=256000
+XIAO_ESP32S3.menu.UploadSpeed.230400.windows.upload.speed=256000
+XIAO_ESP32S3.menu.UploadSpeed.230400=230400
+XIAO_ESP32S3.menu.UploadSpeed.230400.upload.speed=230400
+XIAO_ESP32S3.menu.UploadSpeed.460800.linux=460800
+XIAO_ESP32S3.menu.UploadSpeed.460800.macosx=460800
+XIAO_ESP32S3.menu.UploadSpeed.460800.upload.speed=460800
+XIAO_ESP32S3.menu.UploadSpeed.512000.windows=512000
+XIAO_ESP32S3.menu.UploadSpeed.512000.upload.speed=512000
+
+XIAO_ESP32S3.menu.DebugLevel.none=None
+XIAO_ESP32S3.menu.DebugLevel.none.build.code_debug=0
+XIAO_ESP32S3.menu.DebugLevel.error=Error
+XIAO_ESP32S3.menu.DebugLevel.error.build.code_debug=1
+XIAO_ESP32S3.menu.DebugLevel.warn=Warn
+XIAO_ESP32S3.menu.DebugLevel.warn.build.code_debug=2
+XIAO_ESP32S3.menu.DebugLevel.info=Info
+XIAO_ESP32S3.menu.DebugLevel.info.build.code_debug=3
+XIAO_ESP32S3.menu.DebugLevel.debug=Debug
+XIAO_ESP32S3.menu.DebugLevel.debug.build.code_debug=4
+XIAO_ESP32S3.menu.DebugLevel.verbose=Verbose
+XIAO_ESP32S3.menu.DebugLevel.verbose.build.code_debug=5
+
+XIAO_ESP32S3.menu.EraseFlash.none=Disabled
+XIAO_ESP32S3.menu.EraseFlash.none.upload.erase_cmd=
+XIAO_ESP32S3.menu.EraseFlash.all=Enabled
+XIAO_ESP32S3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+XIAO_ESP32S3_Plus.name=XIAO_ESP32S3_PLUS
+XIAO_ESP32S3_Plus.vid.0=0x2886
+XIAO_ESP32S3_Plus.pid.0=0x0063
+XIAO_ESP32S3_Plus.vid.1=0x2886
+XIAO_ESP32S3_Plus.pid.1=0x8063
+
+XIAO_ESP32S3_Plus.bootloader.tool=esptool_py
+XIAO_ESP32S3_Plus.bootloader.tool.default=esptool_py
+
+XIAO_ESP32S3_Plus.upload.tool=esptool_py
+XIAO_ESP32S3_Plus.upload.tool.default=esptool_py
+XIAO_ESP32S3_Plus.upload.tool.network=esp_ota
+
+XIAO_ESP32S3_Plus.upload.maximum_size=1310720
+XIAO_ESP32S3_Plus.upload.maximum_data_size=327680
+XIAO_ESP32S3_Plus.upload.flags=
+XIAO_ESP32S3_Plus.upload.extra_flags=
+XIAO_ESP32S3_Plus.upload.use_1200bps_touch=false
+XIAO_ESP32S3_Plus.upload.wait_for_upload_port=false
+
+XIAO_ESP32S3_Plus.serial.disableDTR=false
+XIAO_ESP32S3_Plus.serial.disableRTS=false
+
+XIAO_ESP32S3_Plus.build.tarch=xtensa
+XIAO_ESP32S3_Plus.build.bootloader_addr=0x0
+XIAO_ESP32S3_Plus.build.target=esp32s3
+XIAO_ESP32S3_Plus.build.mcu=esp32s3
+XIAO_ESP32S3_Plus.build.core=esp32
+XIAO_ESP32S3_Plus.build.variant=XIAO_ESP32S3_Plus
+XIAO_ESP32S3_Plus.build.board=XIAO_ESP32S3_PLUS
+
+XIAO_ESP32S3_Plus.build.usb_mode=0
+XIAO_ESP32S3_Plus.build.cdc_on_boot=1
+XIAO_ESP32S3_Plus.build.msc_on_boot=0
+XIAO_ESP32S3_Plus.build.dfu_on_boot=0
+XIAO_ESP32S3_Plus.build.f_cpu=240000000L
+XIAO_ESP32S3_Plus.build.flash_size=8MB
+XIAO_ESP32S3_Plus.build.flash_freq=80m
+XIAO_ESP32S3_Plus.build.flash_mode=dio
+XIAO_ESP32S3_Plus.build.boot=qio
+XIAO_ESP32S3_Plus.build.boot_freq=80m
+XIAO_ESP32S3_Plus.build.partitions=default_8MB
+XIAO_ESP32S3_Plus.build.defines=
+XIAO_ESP32S3_Plus.build.loop_core=
+XIAO_ESP32S3_Plus.build.event_core=
+XIAO_ESP32S3_Plus.build.psram_type=qspi
+XIAO_ESP32S3_Plus.build.memory_type={build.boot}_{build.psram_type}
+
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.default=Disabled
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.default.build.copy_jtag_files=0
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.builtin=Integrated USB JTAG
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.external=FTDI Adapter
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.external.build.copy_jtag_files=1
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.bridge=ESP USB Bridge
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+XIAO_ESP32S3_Plus.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+XIAO_ESP32S3_Plus.menu.PSRAM.disabled=Disabled
+XIAO_ESP32S3_Plus.menu.PSRAM.disabled.build.defines=
+XIAO_ESP32S3_Plus.menu.PSRAM.disabled.build.psram_type=qspi
+XIAO_ESP32S3_Plus.menu.PSRAM.opi=OPI PSRAM
+XIAO_ESP32S3_Plus.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+XIAO_ESP32S3_Plus.menu.PSRAM.opi.build.psram_type=opi
+
+XIAO_ESP32S3_Plus.menu.FlashMode.qio=QIO 80MHz
+XIAO_ESP32S3_Plus.menu.FlashMode.qio.build.flash_mode=dio
+XIAO_ESP32S3_Plus.menu.FlashMode.qio.build.boot=qio
+XIAO_ESP32S3_Plus.menu.FlashMode.qio.build.boot_freq=80m
+XIAO_ESP32S3_Plus.menu.FlashMode.qio.build.flash_freq=80m
+XIAO_ESP32S3_Plus.menu.FlashMode.dio=DIO 80MHz
+XIAO_ESP32S3_Plus.menu.FlashMode.dio.build.flash_mode=dio
+XIAO_ESP32S3_Plus.menu.FlashMode.dio.build.boot=dio
+XIAO_ESP32S3_Plus.menu.FlashMode.dio.build.boot_freq=80m
+XIAO_ESP32S3_Plus.menu.FlashMode.dio.build.flash_freq=80m
+
+XIAO_ESP32S3_Plus.menu.FlashSize.8M=8MB (64Mb)
+XIAO_ESP32S3_Plus.menu.FlashSize.8M.build.flash_size=8MB
+XIAO_ESP32S3_Plus.menu.FlashSize.16M=16MB (128Mb)
+XIAO_ESP32S3_Plus.menu.FlashSize.16M.build.flash_size=16MB
+
+XIAO_ESP32S3_Plus.menu.LoopCore.1=Core 1
+XIAO_ESP32S3_Plus.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+XIAO_ESP32S3_Plus.menu.LoopCore.0=Core 0
+XIAO_ESP32S3_Plus.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+XIAO_ESP32S3_Plus.menu.EventsCore.1=Core 1
+XIAO_ESP32S3_Plus.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+XIAO_ESP32S3_Plus.menu.EventsCore.0=Core 0
+XIAO_ESP32S3_Plus.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+XIAO_ESP32S3_Plus.menu.USBMode.hwcdc=Hardware CDC and JTAG
+XIAO_ESP32S3_Plus.menu.USBMode.hwcdc.build.usb_mode=1
+XIAO_ESP32S3_Plus.menu.USBMode.default=USB-OTG (TinyUSB)
+XIAO_ESP32S3_Plus.menu.USBMode.default.build.usb_mode=0
+
+XIAO_ESP32S3_Plus.menu.CDCOnBoot.default=Enabled
+XIAO_ESP32S3_Plus.menu.CDCOnBoot.default.build.cdc_on_boot=1
+XIAO_ESP32S3_Plus.menu.CDCOnBoot.cdc=Disabled
+XIAO_ESP32S3_Plus.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+XIAO_ESP32S3_Plus.menu.MSCOnBoot.default=Disabled
+XIAO_ESP32S3_Plus.menu.MSCOnBoot.default.build.msc_on_boot=0
+XIAO_ESP32S3_Plus.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+XIAO_ESP32S3_Plus.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+XIAO_ESP32S3_Plus.menu.DFUOnBoot.default=Disabled
+XIAO_ESP32S3_Plus.menu.DFUOnBoot.default.build.dfu_on_boot=0
+XIAO_ESP32S3_Plus.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+XIAO_ESP32S3_Plus.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+XIAO_ESP32S3_Plus.menu.UploadMode.default=UART0 / Hardware CDC
+XIAO_ESP32S3_Plus.menu.UploadMode.default.upload.use_1200bps_touch=false
+XIAO_ESP32S3_Plus.menu.UploadMode.default.upload.wait_for_upload_port=false
+XIAO_ESP32S3_Plus.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+XIAO_ESP32S3_Plus.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+XIAO_ESP32S3_Plus.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+XIAO_ESP32S3_Plus.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+XIAO_ESP32S3_Plus.menu.PartitionScheme.fatflash.build.partitions=ffat
+XIAO_ESP32S3_Plus.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+XIAO_ESP32S3_Plus.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+XIAO_ESP32S3_Plus.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+XIAO_ESP32S3_Plus.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+XIAO_ESP32S3_Plus.menu.PartitionScheme.default_8MB=Default with spiffs (3MB APP/1.5MB SPIFFS)
+XIAO_ESP32S3_Plus.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+XIAO_ESP32S3_Plus.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+XIAO_ESP32S3_Plus.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS)
+XIAO_ESP32S3_Plus.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB
+XIAO_ESP32S3_Plus.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536
+XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FFAT)
+XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-8MB
+XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+XIAO_ESP32S3_Plus.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+
+XIAO_ESP32S3_Plus.menu.CPUFreq.240=240MHz (WiFi)
+XIAO_ESP32S3_Plus.menu.CPUFreq.240.build.f_cpu=240000000L
+XIAO_ESP32S3_Plus.menu.CPUFreq.160=160MHz (WiFi)
+XIAO_ESP32S3_Plus.menu.CPUFreq.160.build.f_cpu=160000000L
+XIAO_ESP32S3_Plus.menu.CPUFreq.80=80MHz (WiFi)
+XIAO_ESP32S3_Plus.menu.CPUFreq.80.build.f_cpu=80000000L
+XIAO_ESP32S3_Plus.menu.CPUFreq.40=40MHz
+XIAO_ESP32S3_Plus.menu.CPUFreq.40.build.f_cpu=40000000L
+XIAO_ESP32S3_Plus.menu.CPUFreq.20=20MHz
+XIAO_ESP32S3_Plus.menu.CPUFreq.20.build.f_cpu=20000000L
+XIAO_ESP32S3_Plus.menu.CPUFreq.10=10MHz
+XIAO_ESP32S3_Plus.menu.CPUFreq.10.build.f_cpu=10000000L
+
+XIAO_ESP32S3_Plus.menu.UploadSpeed.921600=921600
+XIAO_ESP32S3_Plus.menu.UploadSpeed.921600.upload.speed=921600
+XIAO_ESP32S3_Plus.menu.UploadSpeed.115200=115200
+XIAO_ESP32S3_Plus.menu.UploadSpeed.115200.upload.speed=115200
+XIAO_ESP32S3_Plus.menu.UploadSpeed.256000.windows=256000
+XIAO_ESP32S3_Plus.menu.UploadSpeed.256000.upload.speed=256000
+XIAO_ESP32S3_Plus.menu.UploadSpeed.230400.windows.upload.speed=256000
+XIAO_ESP32S3_Plus.menu.UploadSpeed.230400=230400
+XIAO_ESP32S3_Plus.menu.UploadSpeed.230400.upload.speed=230400
+XIAO_ESP32S3_Plus.menu.UploadSpeed.460800.linux=460800
+XIAO_ESP32S3_Plus.menu.UploadSpeed.460800.macosx=460800
+XIAO_ESP32S3_Plus.menu.UploadSpeed.460800.upload.speed=460800
+XIAO_ESP32S3_Plus.menu.UploadSpeed.512000.windows=512000
+XIAO_ESP32S3_Plus.menu.UploadSpeed.512000.upload.speed=512000
+
+XIAO_ESP32S3_Plus.menu.DebugLevel.none=None
+XIAO_ESP32S3_Plus.menu.DebugLevel.none.build.code_debug=0
+XIAO_ESP32S3_Plus.menu.DebugLevel.error=Error
+XIAO_ESP32S3_Plus.menu.DebugLevel.error.build.code_debug=1
+XIAO_ESP32S3_Plus.menu.DebugLevel.warn=Warn
+XIAO_ESP32S3_Plus.menu.DebugLevel.warn.build.code_debug=2
+XIAO_ESP32S3_Plus.menu.DebugLevel.info=Info
+XIAO_ESP32S3_Plus.menu.DebugLevel.info.build.code_debug=3
+XIAO_ESP32S3_Plus.menu.DebugLevel.debug=Debug
+XIAO_ESP32S3_Plus.menu.DebugLevel.debug.build.code_debug=4
+XIAO_ESP32S3_Plus.menu.DebugLevel.verbose=Verbose
+XIAO_ESP32S3_Plus.menu.DebugLevel.verbose.build.code_debug=5
+
+XIAO_ESP32S3_Plus.menu.EraseFlash.none=Disabled
+XIAO_ESP32S3_Plus.menu.EraseFlash.none.upload.erase_cmd=
+XIAO_ESP32S3_Plus.menu.EraseFlash.all=Enabled
+XIAO_ESP32S3_Plus.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+connaxio_espoir.name=Connaxio's Espoir
+connaxio_espoir.vid.0=0x10C4
+connaxio_espoir.pid.0=0x8D9A
+
+connaxio_espoir.bootloader.tool=esptool_py
+connaxio_espoir.bootloader.tool.default=esptool_py
+
+connaxio_espoir.upload.tool=esptool_py
+connaxio_espoir.upload.tool.default=esptool_py
+connaxio_espoir.upload.tool.network=esp_ota
+
+connaxio_espoir.upload.maximum_size=1310720
+connaxio_espoir.upload.maximum_data_size=327680
+connaxio_espoir.upload.flags=
+connaxio_espoir.upload.extra_flags=
+
+connaxio_espoir.serial.disableDTR=true
+connaxio_espoir.serial.disableRTS=true
+
+connaxio_espoir.build.tarch=xtensa
+connaxio_espoir.build.bootloader_addr=0x1000
+connaxio_espoir.build.target=esp32
+connaxio_espoir.build.mcu=esp32
+connaxio_espoir.build.core=esp32
+connaxio_espoir.build.variant=connaxio_espoir
+connaxio_espoir.build.board=connaxio_espoir
+
+connaxio_espoir.build.f_cpu=240000000L
+connaxio_espoir.build.flash_size=4MB
+connaxio_espoir.build.flash_freq=80m
+connaxio_espoir.build.flash_mode=dio
+connaxio_espoir.build.boot=dio
+connaxio_espoir.build.partitions=default
+connaxio_espoir.build.defines=
+connaxio_espoir.build.loop_core=
+connaxio_espoir.build.event_core=
+
+connaxio_espoir.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+connaxio_espoir.menu.PartitionScheme.default.build.partitions=default
+connaxio_espoir.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+connaxio_espoir.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+connaxio_espoir.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+connaxio_espoir.menu.PartitionScheme.minimal.build.partitions=minimal
+connaxio_espoir.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+connaxio_espoir.menu.PartitionScheme.no_ota.build.partitions=no_ota
+connaxio_espoir.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+connaxio_espoir.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+connaxio_espoir.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+connaxio_espoir.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+connaxio_espoir.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+connaxio_espoir.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+connaxio_espoir.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+connaxio_espoir.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+connaxio_espoir.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+connaxio_espoir.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+connaxio_espoir.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+connaxio_espoir.menu.PartitionScheme.huge_app.build.partitions=huge_app
+connaxio_espoir.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+connaxio_espoir.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+connaxio_espoir.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+connaxio_espoir.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+connaxio_espoir.menu.PartitionScheme.rainmaker=RainMaker 4MB
+connaxio_espoir.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+connaxio_espoir.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+connaxio_espoir.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+connaxio_espoir.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+connaxio_espoir.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+connaxio_espoir.menu.CPUFreq.240=240MHz (WiFi/BT)
+connaxio_espoir.menu.CPUFreq.240.build.f_cpu=240000000L
+connaxio_espoir.menu.CPUFreq.160=160MHz (WiFi/BT)
+connaxio_espoir.menu.CPUFreq.160.build.f_cpu=160000000L
+connaxio_espoir.menu.CPUFreq.80=80MHz (WiFi/BT)
+connaxio_espoir.menu.CPUFreq.80.build.f_cpu=80000000L
+connaxio_espoir.menu.CPUFreq.40=40MHz
+connaxio_espoir.menu.CPUFreq.40.build.f_cpu=40000000L
+connaxio_espoir.menu.CPUFreq.20=20MHz
+connaxio_espoir.menu.CPUFreq.20.build.f_cpu=20000000L
+connaxio_espoir.menu.CPUFreq.10=10MHz
+connaxio_espoir.menu.CPUFreq.10.build.f_cpu=10000000L
+
+connaxio_espoir.menu.FlashFreq.80=80MHz
+connaxio_espoir.menu.FlashFreq.80.build.flash_freq=80m
+connaxio_espoir.menu.FlashFreq.40=40MHz
+connaxio_espoir.menu.FlashFreq.40.build.flash_freq=40m
+
+connaxio_espoir.menu.UploadSpeed.921600=921600
+connaxio_espoir.menu.UploadSpeed.921600.upload.speed=921600
+connaxio_espoir.menu.UploadSpeed.512000.windows=512000
+connaxio_espoir.menu.UploadSpeed.512000.upload.speed=512000
+connaxio_espoir.menu.UploadSpeed.460800.linux=460800
+connaxio_espoir.menu.UploadSpeed.460800.macosx=460800
+connaxio_espoir.menu.UploadSpeed.460800.upload.speed=460800
+connaxio_espoir.menu.UploadSpeed.256000.windows=256000
+connaxio_espoir.menu.UploadSpeed.256000.upload.speed=256000
+connaxio_espoir.menu.UploadSpeed.230400.windows.upload.speed=256000
+connaxio_espoir.menu.UploadSpeed.230400=230400
+connaxio_espoir.menu.UploadSpeed.230400.upload.speed=230400
+connaxio_espoir.menu.UploadSpeed.115200=115200
+connaxio_espoir.menu.UploadSpeed.115200.upload.speed=115200
+
+connaxio_espoir.menu.DebugLevel.none=None
+connaxio_espoir.menu.DebugLevel.none.build.code_debug=0
+connaxio_espoir.menu.DebugLevel.error=Error
+connaxio_espoir.menu.DebugLevel.error.build.code_debug=1
+connaxio_espoir.menu.DebugLevel.warn=Warn
+connaxio_espoir.menu.DebugLevel.warn.build.code_debug=2
+connaxio_espoir.menu.DebugLevel.info=Info
+connaxio_espoir.menu.DebugLevel.info.build.code_debug=3
+connaxio_espoir.menu.DebugLevel.debug=Debug
+connaxio_espoir.menu.DebugLevel.debug.build.code_debug=4
+connaxio_espoir.menu.DebugLevel.verbose=Verbose
+connaxio_espoir.menu.DebugLevel.verbose.build.code_debug=5
+
+connaxio_espoir.menu.EraseFlash.none=Disabled
+connaxio_espoir.menu.EraseFlash.none.upload.erase_cmd=
+connaxio_espoir.menu.EraseFlash.all=Enabled
+connaxio_espoir.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+aw2eth.name=CNRS AW2ETH
+
+aw2eth.bootloader.tool=esptool_py
+aw2eth.bootloader.tool.default=esptool_py
+
+aw2eth.upload.tool=esptool_py
+aw2eth.upload.tool.default=esptool_py
+aw2eth.upload.tool.network=esp_ota
+
+aw2eth.upload.maximum_size=1310720
+aw2eth.upload.maximum_data_size=327680
+aw2eth.upload.flags=
+aw2eth.upload.extra_flags=
+
+aw2eth.serial.disableDTR=true
+aw2eth.serial.disableRTS=true
+
+aw2eth.build.tarch=xtensa
+aw2eth.build.bootloader_addr=0x1000
+aw2eth.build.target=esp32
+aw2eth.build.mcu=esp32
+aw2eth.build.core=esp32
+aw2eth.build.variant=cnrs_aw2eth
+aw2eth.build.board=ESP32_PICO
+
+aw2eth.build.f_cpu=240000000L
+aw2eth.build.flash_size=4MB
+aw2eth.build.flash_freq=80m
+aw2eth.build.flash_mode=dio
+aw2eth.build.boot=dio
+aw2eth.build.partitions=default
+aw2eth.build.defines=
+
+aw2eth.menu.PartitionScheme.default=Default
+aw2eth.menu.PartitionScheme.default.build.partitions=default
+aw2eth.menu.PartitionScheme.no_ota=No OTA (Large APP)
+aw2eth.menu.PartitionScheme.no_ota.build.partitions=no_ota
+aw2eth.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+aw2eth.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+aw2eth.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+aw2eth.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+aw2eth.menu.UploadSpeed.921600=921600
+aw2eth.menu.UploadSpeed.921600.upload.speed=921600
+aw2eth.menu.UploadSpeed.115200=115200
+aw2eth.menu.UploadSpeed.115200.upload.speed=115200
+aw2eth.menu.UploadSpeed.256000.windows=256000
+aw2eth.menu.UploadSpeed.256000.upload.speed=256000
+aw2eth.menu.UploadSpeed.230400.windows.upload.speed=256000
+aw2eth.menu.UploadSpeed.230400=230400
+aw2eth.menu.UploadSpeed.230400.upload.speed=230400
+aw2eth.menu.UploadSpeed.460800.linux=460800
+aw2eth.menu.UploadSpeed.460800.macosx=460800
+aw2eth.menu.UploadSpeed.460800.upload.speed=460800
+aw2eth.menu.UploadSpeed.512000.windows=512000
+aw2eth.menu.UploadSpeed.512000.upload.speed=512000
+
+aw2eth.menu.DebugLevel.none=None
+aw2eth.menu.DebugLevel.none.build.code_debug=0
+aw2eth.menu.DebugLevel.error=Error
+aw2eth.menu.DebugLevel.error.build.code_debug=1
+aw2eth.menu.DebugLevel.warn=Warn
+aw2eth.menu.DebugLevel.warn.build.code_debug=2
+aw2eth.menu.DebugLevel.info=Info
+aw2eth.menu.DebugLevel.info.build.code_debug=3
+aw2eth.menu.DebugLevel.debug=Debug
+aw2eth.menu.DebugLevel.debug.build.code_debug=4
+aw2eth.menu.DebugLevel.verbose=Verbose
+aw2eth.menu.DebugLevel.verbose.build.code_debug=5
+
+aw2eth.menu.EraseFlash.none=Disabled
+aw2eth.menu.EraseFlash.none.upload.erase_cmd=
+aw2eth.menu.EraseFlash.all=Enabled
+aw2eth.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+department_of_alchemy_minimain_esp32s2.name=Department of Alchemy MiniMain ESP32-S2
+department_of_alchemy_minimain_esp32s2.vid.0=0x303A
+department_of_alchemy_minimain_esp32s2.pid.0=0x80FF
+
+department_of_alchemy_minimain_esp32s2.bootloader.tool=esptool_py
+department_of_alchemy_minimain_esp32s2.bootloader.tool.default=esptool_py
+
+department_of_alchemy_minimain_esp32s2.upload.tool=esptool_py
+department_of_alchemy_minimain_esp32s2.upload.tool.default=esptool_py
+department_of_alchemy_minimain_esp32s2.upload.tool.network=esp_ota
+
+department_of_alchemy_minimain_esp32s2.upload.maximum_size=1310720
+department_of_alchemy_minimain_esp32s2.upload.maximum_data_size=327680
+department_of_alchemy_minimain_esp32s2.upload.flags=
+department_of_alchemy_minimain_esp32s2.upload.extra_flags=
+department_of_alchemy_minimain_esp32s2.upload.use_1200bps_touch=true
+department_of_alchemy_minimain_esp32s2.upload.wait_for_upload_port=true
+
+department_of_alchemy_minimain_esp32s2.serial.disableDTR=false
+department_of_alchemy_minimain_esp32s2.serial.disableRTS=false
+
+department_of_alchemy_minimain_esp32s2.build.tarch=xtensa
+department_of_alchemy_minimain_esp32s2.build.bootloader_addr=0x1000
+department_of_alchemy_minimain_esp32s2.build.target=esp32s2
+department_of_alchemy_minimain_esp32s2.build.mcu=esp32s2
+department_of_alchemy_minimain_esp32s2.build.core=esp32
+department_of_alchemy_minimain_esp32s2.build.variant=department_of_alchemy_minimain_esp32s2
+department_of_alchemy_minimain_esp32s2.build.board=DEPARTMENT_OF_ALCHEMY_MINIMAIN_ESP32S2
+
+department_of_alchemy_minimain_esp32s2.build.cdc_on_boot=1
+department_of_alchemy_minimain_esp32s2.build.msc_on_boot=0
+department_of_alchemy_minimain_esp32s2.build.dfu_on_boot=0
+department_of_alchemy_minimain_esp32s2.build.f_cpu=240000000L
+department_of_alchemy_minimain_esp32s2.build.flash_size=4MB
+department_of_alchemy_minimain_esp32s2.build.flash_freq=80m
+department_of_alchemy_minimain_esp32s2.build.flash_mode=qio
+department_of_alchemy_minimain_esp32s2.build.boot=qio
+department_of_alchemy_minimain_esp32s2.build.partitions=default
+department_of_alchemy_minimain_esp32s2.build.defines=
+
+department_of_alchemy_minimain_esp32s2.menu.CDCOnBoot.cdc=Enabled
+department_of_alchemy_minimain_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+department_of_alchemy_minimain_esp32s2.menu.CDCOnBoot.default=Disabled
+department_of_alchemy_minimain_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+department_of_alchemy_minimain_esp32s2.menu.MSCOnBoot.default=Disabled
+department_of_alchemy_minimain_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0
+department_of_alchemy_minimain_esp32s2.menu.MSCOnBoot.msc=Enabled
+department_of_alchemy_minimain_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+department_of_alchemy_minimain_esp32s2.menu.DFUOnBoot.default=Disabled
+department_of_alchemy_minimain_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+department_of_alchemy_minimain_esp32s2.menu.DFUOnBoot.dfu=Enabled
+department_of_alchemy_minimain_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+department_of_alchemy_minimain_esp32s2.menu.UploadMode.cdc=Internal USB
+department_of_alchemy_minimain_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+department_of_alchemy_minimain_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+department_of_alchemy_minimain_esp32s2.menu.UploadMode.default=UART0
+department_of_alchemy_minimain_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false
+department_of_alchemy_minimain_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+department_of_alchemy_minimain_esp32s2.menu.PSRAM.enabled=Enabled
+department_of_alchemy_minimain_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+department_of_alchemy_minimain_esp32s2.menu.PSRAM.disabled=Disabled
+department_of_alchemy_minimain_esp32s2.menu.PSRAM.disabled.build.defines=
+
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FFAT)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-4MB-tinyuf2
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.default.build.partitions=default
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+department_of_alchemy_minimain_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.240=240MHz (WiFi)
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.160=160MHz (WiFi)
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.80=80MHz (WiFi)
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.40=40MHz
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.20=20MHz
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.10=10MHz
+department_of_alchemy_minimain_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+department_of_alchemy_minimain_esp32s2.menu.FlashMode.qio=QIO
+department_of_alchemy_minimain_esp32s2.menu.FlashMode.qio.build.flash_mode=dio
+department_of_alchemy_minimain_esp32s2.menu.FlashMode.qio.build.boot=qio
+department_of_alchemy_minimain_esp32s2.menu.FlashMode.dio=DIO
+department_of_alchemy_minimain_esp32s2.menu.FlashMode.dio.build.flash_mode=dio
+department_of_alchemy_minimain_esp32s2.menu.FlashMode.dio.build.boot=dio
+
+department_of_alchemy_minimain_esp32s2.menu.FlashFreq.80=80MHz
+department_of_alchemy_minimain_esp32s2.menu.FlashFreq.80.build.flash_freq=80m
+department_of_alchemy_minimain_esp32s2.menu.FlashFreq.40=40MHz
+department_of_alchemy_minimain_esp32s2.menu.FlashFreq.40.build.flash_freq=40m
+
+department_of_alchemy_minimain_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+department_of_alchemy_minimain_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+department_of_alchemy_minimain_esp32s2.menu.FlashSize.8M=8MB (64Mb)
+department_of_alchemy_minimain_esp32s2.menu.FlashSize.8M.build.flash_size=8MB
+department_of_alchemy_minimain_esp32s2.menu.FlashSize.2M=2MB (16Mb)
+department_of_alchemy_minimain_esp32s2.menu.FlashSize.2M.build.flash_size=2MB
+department_of_alchemy_minimain_esp32s2.menu.FlashSize.16M=16MB (128Mb)
+department_of_alchemy_minimain_esp32s2.menu.FlashSize.16M.build.flash_size=16MB
+
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.921600=921600
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.921600.upload.speed=921600
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.115200=115200
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.115200.upload.speed=115200
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.256000.windows=256000
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.256000.upload.speed=256000
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.230400=230400
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.230400.upload.speed=230400
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.460800.linux=460800
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.460800.macosx=460800
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.460800.upload.speed=460800
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.512000.windows=512000
+department_of_alchemy_minimain_esp32s2.menu.UploadSpeed.512000.upload.speed=512000
+
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.none=None
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.none.build.code_debug=0
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.error=Error
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.error.build.code_debug=1
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.warn=Warn
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.info=Info
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.info.build.code_debug=3
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.debug=Debug
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.verbose=Verbose
+department_of_alchemy_minimain_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+department_of_alchemy_minimain_esp32s2.menu.EraseFlash.none=Disabled
+department_of_alchemy_minimain_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+department_of_alchemy_minimain_esp32s2.menu.EraseFlash.all=Enabled
+department_of_alchemy_minimain_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+
+Bee_Data_Logger.name=Bee Data Logger
+Bee_Data_Logger.vid.0=0x303a
+Bee_Data_Logger.pid.0=0x815C
+Bee_Data_Logger.upload_port.0.vid=0x303a
+Bee_Data_Logger.upload_port.0.pid=0x815C
+
+Bee_Data_Logger.bootloader.tool=esptool_py
+Bee_Data_Logger.bootloader.tool.default=esptool_py
+
+Bee_Data_Logger.upload.tool=esptool_py
+Bee_Data_Logger.upload.tool.default=esptool_py
+Bee_Data_Logger.upload.tool.network=esp_ota
+
+Bee_Data_Logger.upload.maximum_size=1310720
+Bee_Data_Logger.upload.maximum_data_size=327680
+Bee_Data_Logger.upload.flags=
+Bee_Data_Logger.upload.extra_flags=
+Bee_Data_Logger.upload.use_1200bps_touch=true
+Bee_Data_Logger.upload.wait_for_upload_port=true
+Bee_Data_Logger.upload.speed=921600
+
+Bee_Data_Logger.serial.disableDTR=false
+Bee_Data_Logger.serial.disableRTS=false
+
+Bee_Data_Logger.build.tarch=xtensa
+Bee_Data_Logger.build.bootloader_addr=0x0
+Bee_Data_Logger.build.target=esp32s3
+Bee_Data_Logger.build.mcu=esp32s3
+Bee_Data_Logger.build.core=esp32
+Bee_Data_Logger.build.variant=Bee_Data_Logger
+Bee_Data_Logger.build.board=BEE_DATA_LOGGER
+
+Bee_Data_Logger.build.cdc_on_boot=1
+Bee_Data_Logger.build.msc_on_boot=1
+Bee_Data_Logger.build.dfu_on_boot=1
+Bee_Data_Logger.build.f_cpu=240000000L
+Bee_Data_Logger.build.flash_size=8MB
+Bee_Data_Logger.build.flash_freq=80m
+Bee_Data_Logger.build.flash_mode=dio
+Bee_Data_Logger.build.partitions=default_8MB
+Bee_Data_Logger.build.defines=
+Bee_Data_Logger.build.loop_core=-DARDUINO_RUNNING_CORE=1
+Bee_Data_Logger.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+Bee_Data_Logger.build.boot=qio
+Bee_Data_Logger.build.partitions=default
+Bee_Data_Logger.build.defines=
+
+Bee_Data_Logger.menu.CDCOnBoot.default=Enabled
+Bee_Data_Logger.menu.CDCOnBoot.default.build.cdc_on_boot=1
+Bee_Data_Logger.menu.CDCOnBoot.dis_cdc=Disabled
+Bee_Data_Logger.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+Bee_Data_Logger.menu.MSCOnBoot.default=Disabled
+Bee_Data_Logger.menu.MSCOnBoot.default.build.msc_on_boot=0
+Bee_Data_Logger.menu.MSCOnBoot.msc=Enabled
+Bee_Data_Logger.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+Bee_Data_Logger.menu.DFUOnBoot.default=Disabled
+Bee_Data_Logger.menu.DFUOnBoot.default.build.dfu_on_boot=0
+Bee_Data_Logger.menu.DFUOnBoot.dfu=Enabled
+Bee_Data_Logger.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+Bee_Data_Logger.menu.USBMode.default=USB-OTG
+Bee_Data_Logger.menu.USBMode.default.build.usb_mode=0
+Bee_Data_Logger.menu.USBMode.default.upload.use_1200bps_touch=true
+Bee_Data_Logger.menu.USBMode.default.upload.wait_for_upload_port=true
+Bee_Data_Logger.menu.USBMode.hwcdc=Hardware CDC and JTAG
+Bee_Data_Logger.menu.USBMode.hwcdc.build.usb_mode=1
+Bee_Data_Logger.menu.USBMode.hwcdc.upload.use_1200bps_touch=false
+Bee_Data_Logger.menu.USBMode.hwcdc.upload.wait_for_upload_port=false
+
+Bee_Data_Logger.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Bee_Data_Logger.menu.PartitionScheme.default.build.partitions=default
+Bee_Data_Logger.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Bee_Data_Logger.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Bee_Data_Logger.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Bee_Data_Logger.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Bee_Data_Logger.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Bee_Data_Logger.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Bee_Data_Logger.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Bee_Data_Logger.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Bee_Data_Logger.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Bee_Data_Logger.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Bee_Data_Logger.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Bee_Data_Logger.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Bee_Data_Logger.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Bee_Data_Logger.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Bee_Data_Logger.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Bee_Data_Logger.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Bee_Data_Logger.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+Bee_Data_Logger.menu.DebugLevel.none=None
+Bee_Data_Logger.menu.DebugLevel.none.build.code_debug=0
+Bee_Data_Logger.menu.DebugLevel.error=Error
+Bee_Data_Logger.menu.DebugLevel.error.build.code_debug=1
+Bee_Data_Logger.menu.DebugLevel.warn=Warn
+Bee_Data_Logger.menu.DebugLevel.warn.build.code_debug=2
+Bee_Data_Logger.menu.DebugLevel.info=Info
+Bee_Data_Logger.menu.DebugLevel.info.build.code_debug=3
+Bee_Data_Logger.menu.DebugLevel.debug=Debug
+Bee_Data_Logger.menu.DebugLevel.debug.build.code_debug=4
+Bee_Data_Logger.menu.DebugLevel.verbose=Verbose
+Bee_Data_Logger.menu.DebugLevel.verbose.build.code_debug=5
+
+Bee_Data_Logger.menu.EraseFlash.none=Disabled
+Bee_Data_Logger.menu.EraseFlash.none.upload.erase_cmd=
+Bee_Data_Logger.menu.EraseFlash.all=Enabled
+Bee_Data_Logger.menu.EraseFlash.all.upload.erase_cmd=-e
+
+############################################################
+
+Bee_Motion_S3.name=Bee Motion S3
+Bee_Motion_S3.vid.0=0x303a
+Bee_Motion_S3.pid.0=0x8113
+Bee_Motion_S3.upload_port.0.vid=0x303a
+Bee_Motion_S3.upload_port.0.pid=0x8113
+
+Bee_Motion_S3.bootloader.tool=esptool_py
+Bee_Motion_S3.bootloader.tool.default=esptool_py
+
+Bee_Motion_S3.upload.tool=esptool_py
+Bee_Motion_S3.upload.tool.default=esptool_py
+Bee_Motion_S3.upload.tool.network=esp_ota
+
+Bee_Motion_S3.upload.maximum_size=1310720
+Bee_Motion_S3.upload.maximum_data_size=327680
+Bee_Motion_S3.upload.flags=
+Bee_Motion_S3.upload.extra_flags=
+Bee_Motion_S3.upload.use_1200bps_touch=true
+Bee_Motion_S3.upload.wait_for_upload_port=true
+Bee_Motion_S3.upload.speed=921600
+
+Bee_Motion_S3.serial.disableDTR=false
+Bee_Motion_S3.serial.disableRTS=false
+
+Bee_Motion_S3.build.tarch=xtensa
+Bee_Motion_S3.build.bootloader_addr=0x0
+Bee_Motion_S3.build.target=esp32s3
+Bee_Motion_S3.build.mcu=esp32s3
+Bee_Motion_S3.build.core=esp32
+Bee_Motion_S3.build.variant=Bee_Motion_S3
+Bee_Motion_S3.build.board=BeeMotionS3
+
+Bee_Motion_S3.build.cdc_on_boot=1
+Bee_Motion_S3.build.msc_on_boot=1
+Bee_Motion_S3.build.dfu_on_boot=1
+Bee_Motion_S3.build.f_cpu=240000000L
+Bee_Motion_S3.build.flash_size=8MB
+Bee_Motion_S3.build.flash_freq=80m
+Bee_Motion_S3.build.flash_mode=dio
+Bee_Motion_S3.build.partitions=default_8MB
+Bee_Motion_S3.build.defines=
+Bee_Motion_S3.build.loop_core=-DARDUINO_RUNNING_CORE=1
+Bee_Motion_S3.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+Bee_Motion_S3.build.boot=qio
+Bee_Motion_S3.build.partitions=default
+Bee_Motion_S3.build.defines=
+
+Bee_Motion_S3.menu.CDCOnBoot.default=Enabled
+Bee_Motion_S3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+Bee_Motion_S3.menu.CDCOnBoot.dis_cdc=Disabled
+Bee_Motion_S3.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+Bee_Motion_S3.menu.MSCOnBoot.default=Disabled
+Bee_Motion_S3.menu.MSCOnBoot.default.build.msc_on_boot=0
+Bee_Motion_S3.menu.MSCOnBoot.msc=Enabled
+Bee_Motion_S3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+Bee_Motion_S3.menu.DFUOnBoot.default=Disabled
+Bee_Motion_S3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+Bee_Motion_S3.menu.DFUOnBoot.dfu=Enabled
+Bee_Motion_S3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+Bee_Motion_S3.menu.USBMode.default=USB-OTG
+Bee_Motion_S3.menu.USBMode.default.build.usb_mode=0
+Bee_Motion_S3.menu.USBMode.default.upload.use_1200bps_touch=true
+Bee_Motion_S3.menu.USBMode.default.upload.wait_for_upload_port=true
+Bee_Motion_S3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+Bee_Motion_S3.menu.USBMode.hwcdc.build.usb_mode=1
+Bee_Motion_S3.menu.USBMode.hwcdc.upload.use_1200bps_touch=false
+Bee_Motion_S3.menu.USBMode.hwcdc.upload.wait_for_upload_port=false
+
+Bee_Motion_S3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Bee_Motion_S3.menu.PartitionScheme.default.build.partitions=default
+Bee_Motion_S3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Bee_Motion_S3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Bee_Motion_S3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Bee_Motion_S3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Bee_Motion_S3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Bee_Motion_S3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Bee_Motion_S3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Bee_Motion_S3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Bee_Motion_S3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Bee_Motion_S3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Bee_Motion_S3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Bee_Motion_S3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Bee_Motion_S3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Bee_Motion_S3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Bee_Motion_S3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Bee_Motion_S3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Bee_Motion_S3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+Bee_Motion_S3.menu.DebugLevel.none=None
+Bee_Motion_S3.menu.DebugLevel.none.build.code_debug=0
+Bee_Motion_S3.menu.DebugLevel.error=Error
+Bee_Motion_S3.menu.DebugLevel.error.build.code_debug=1
+Bee_Motion_S3.menu.DebugLevel.warn=Warn
+Bee_Motion_S3.menu.DebugLevel.warn.build.code_debug=2
+Bee_Motion_S3.menu.DebugLevel.info=Info
+Bee_Motion_S3.menu.DebugLevel.info.build.code_debug=3
+Bee_Motion_S3.menu.DebugLevel.debug=Debug
+Bee_Motion_S3.menu.DebugLevel.debug.build.code_debug=4
+Bee_Motion_S3.menu.DebugLevel.verbose=Verbose
+Bee_Motion_S3.menu.DebugLevel.verbose.build.code_debug=5
+
+Bee_Motion_S3.menu.EraseFlash.none=Disabled
+Bee_Motion_S3.menu.EraseFlash.none.upload.erase_cmd=
+Bee_Motion_S3.menu.EraseFlash.all=Enabled
+Bee_Motion_S3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+########################################################################
+
+Bee_Motion.name=Bee Motion
+Bee_Motion.vid.0=0x303a
+Bee_Motion.pid.0=0x810D
+Bee_Motion.vid.upload_port.0.vid=0x303a
+Bee_Motion.pid.upload_port.0.pid=0x810D
+
+Bee_Motion.bootloader.tool=esptool_py
+Bee_Motion.bootloader.tool.default=esptool_py
+
+Bee_Motion.upload.tool=esptool_py
+Bee_Motion.upload.tool.default=esptool_py
+Bee_Motion.upload.tool.network=esp_ota
+
+Bee_Motion.upload.maximum_size=1310720
+Bee_Motion.upload.maximum_data_size=327680
+Bee_Motion.upload.flags=
+Bee_Motion.upload.extra_flags=
+Bee_Motion.upload.use_1200bps_touch=true
+Bee_Motion.upload.wait_for_upload_port=true
+Bee_Motion.upload.speed=921600
+
+Bee_Motion.serial.disableDTR=false
+Bee_Motion.serial.disableRTS=false
+
+Bee_Motion.build.tarch=xtensa
+Bee_Motion.build.bootloader_addr=0x1000
+Bee_Motion.build.target=esp32s2
+Bee_Motion.build.mcu=esp32s2
+Bee_Motion.build.core=esp32
+Bee_Motion.build.variant=Bee_Motion
+Bee_Motion.build.board=Bee_Motion
+
+Bee_Motion.build.cdc_on_boot=1
+Bee_Motion.build.msc_on_boot=1
+Bee_Motion.build.dfu_on_boot=1
+Bee_Motion.build.f_cpu=240000000L
+Bee_Motion.build.flash_size=4MB
+Bee_Motion.build.flash_freq=80m
+Bee_Motion.build.flash_mode=dio
+Bee_Motion.build.boot=qio
+Bee_Motion.build.partitions=default
+Bee_Motion.build.defines=
+
+Bee_Motion.menu.CDCOnBoot.default=Enabled
+Bee_Motion.menu.CDCOnBoot.default.build.cdc_on_boot=1
+Bee_Motion.menu.CDCOnBoot.dis_cdc=Disabled
+Bee_Motion.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+Bee_Motion.menu.MSCOnBoot.default=Disabled
+Bee_Motion.menu.MSCOnBoot.default.build.msc_on_boot=0
+Bee_Motion.menu.MSCOnBoot.msc=Enabled
+Bee_Motion.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+Bee_Motion.menu.DFUOnBoot.default=Disabled
+Bee_Motion.menu.DFUOnBoot.default.build.dfu_on_boot=0
+Bee_Motion.menu.DFUOnBoot.dfu=Enabled
+Bee_Motion.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+Bee_Motion.menu.USBMode.default=USB-OTG
+Bee_Motion.menu.USBMode.default.build.usb_mode=0
+Bee_Motion.menu.USBMode.default.upload.use_1200bps_touch=true
+Bee_Motion.menu.USBMode.default.upload.wait_for_upload_port=true
+Bee_Motion.menu.USBMode.hwcdc=Hardware CDC and JTAG
+Bee_Motion.menu.USBMode.hwcdc.build.usb_mode=1
+Bee_Motion.menu.USBMode.hwcdc.upload.use_1200bps_touch=false
+Bee_Motion.menu.USBMode.hwcdc.upload.wait_for_upload_port=false
+
+Bee_Motion.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Bee_Motion.menu.PartitionScheme.default.build.partitions=default
+Bee_Motion.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Bee_Motion.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Bee_Motion.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Bee_Motion.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Bee_Motion.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Bee_Motion.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Bee_Motion.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Bee_Motion.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Bee_Motion.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Bee_Motion.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Bee_Motion.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Bee_Motion.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Bee_Motion.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Bee_Motion.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Bee_Motion.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Bee_Motion.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Bee_Motion.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+Bee_Motion.menu.DebugLevel.none=None
+Bee_Motion.menu.DebugLevel.none.build.code_debug=0
+Bee_Motion.menu.DebugLevel.error=Error
+Bee_Motion.menu.DebugLevel.error.build.code_debug=1
+Bee_Motion.menu.DebugLevel.warn=Warn
+Bee_Motion.menu.DebugLevel.warn.build.code_debug=2
+Bee_Motion.menu.DebugLevel.info=Info
+Bee_Motion.menu.DebugLevel.info.build.code_debug=3
+Bee_Motion.menu.DebugLevel.debug=Debug
+Bee_Motion.menu.DebugLevel.debug.build.code_debug=4
+Bee_Motion.menu.DebugLevel.verbose=Verbose
+Bee_Motion.menu.DebugLevel.verbose.build.code_debug=5
+
+Bee_Motion.menu.EraseFlash.none=Disabled
+Bee_Motion.menu.EraseFlash.none.upload.erase_cmd=
+Bee_Motion.menu.EraseFlash.all=Enabled
+Bee_Motion.menu.EraseFlash.all.upload.erase_cmd=-e
+
+#####################################################################
+
+Bee_Motion_Mini.name=Bee Motion Mini
+
+Bee_Motion_Mini.bootloader.tool=esptool_py
+Bee_Motion_Mini.bootloader.tool.default=esptool_py
+
+Bee_Motion_Mini.upload.tool=esptool_py
+Bee_Motion_Mini.upload.tool.default=esptool_py
+Bee_Motion_Mini.upload.tool.network=esp_ota
+
+Bee_Motion_Mini.upload.maximum_size=1310720
+Bee_Motion_Mini.upload.maximum_data_size=327680
+Bee_Motion_Mini.upload.flags=
+Bee_Motion_Mini.upload.extra_flags=
+Bee_Motion_Mini.upload.use_1200bps_touch=false
+Bee_Motion_Mini.upload.wait_for_upload_port=false
+
+Bee_Motion_Mini.serial.disableDTR=true
+Bee_Motion_Mini.serial.disableRTS=true
+
+Bee_Motion_Mini.build.tarch=riscv32
+Bee_Motion_Mini.build.target=esp
+Bee_Motion_Mini.build.mcu=esp32c3
+Bee_Motion_Mini.build.core=esp32
+Bee_Motion_Mini.build.variant=Bee_Motion_Mini
+Bee_Motion_Mini.build.board=Bee_Motion_Mini
+Bee_Motion_Mini.build.bootloader_addr=0x0
+
+Bee_Motion_Mini.build.cdc_on_boot=1
+Bee_Motion_Mini.build.f_cpu=160000000L
+Bee_Motion_Mini.build.flash_size=4MB
+Bee_Motion_Mini.build.flash_freq=80m
+Bee_Motion_Mini.build.flash_mode=dio
+Bee_Motion_Mini.build.boot=qio
+Bee_Motion_Mini.build.partitions=default
+Bee_Motion_Mini.build.defines=
+
+Bee_Motion_Mini.menu.CDCOnBoot.default=Enabled
+Bee_Motion_Mini.menu.CDCOnBoot.default.build.cdc_on_boot=1
+Bee_Motion_Mini.menu.CDCOnBoot.dis_cdc=Disabled
+Bee_Motion_Mini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+Bee_Motion_Mini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Bee_Motion_Mini.menu.PartitionScheme.default.build.partitions=default
+Bee_Motion_Mini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Bee_Motion_Mini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Bee_Motion_Mini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Bee_Motion_Mini.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Bee_Motion_Mini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Bee_Motion_Mini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Bee_Motion_Mini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Bee_Motion_Mini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Bee_Motion_Mini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Bee_Motion_Mini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Bee_Motion_Mini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Bee_Motion_Mini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Bee_Motion_Mini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Bee_Motion_Mini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Bee_Motion_Mini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Bee_Motion_Mini.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Bee_Motion_Mini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+Bee_Motion_Mini.menu.CPUFreq.160=160MHz (WiFi)
+Bee_Motion_Mini.menu.CPUFreq.160.build.f_cpu=160000000L
+Bee_Motion_Mini.menu.CPUFreq.80=80MHz (WiFi)
+Bee_Motion_Mini.menu.CPUFreq.80.build.f_cpu=80000000L
+Bee_Motion_Mini.menu.CPUFreq.40=40MHz
+Bee_Motion_Mini.menu.CPUFreq.40.build.f_cpu=40000000L
+Bee_Motion_Mini.menu.CPUFreq.20=20MHz
+Bee_Motion_Mini.menu.CPUFreq.20.build.f_cpu=20000000L
+Bee_Motion_Mini.menu.CPUFreq.10=10MHz
+Bee_Motion_Mini.menu.CPUFreq.10.build.f_cpu=10000000L
+
+Bee_Motion_Mini.menu.FlashFreq.80=80MHz
+Bee_Motion_Mini.menu.FlashFreq.80.build.flash_freq=80m
+Bee_Motion_Mini.menu.FlashFreq.40=40MHz
+Bee_Motion_Mini.menu.FlashFreq.40.build.flash_freq=40m
+
+Bee_Motion_Mini.menu.UploadSpeed.921600=921600
+Bee_Motion_Mini.menu.UploadSpeed.921600.upload.speed=921600
+Bee_Motion_Mini.menu.UploadSpeed.115200=115200
+Bee_Motion_Mini.menu.UploadSpeed.115200.upload.speed=115200
+Bee_Motion_Mini.menu.UploadSpeed.256000.windows=256000
+Bee_Motion_Mini.menu.UploadSpeed.256000.upload.speed=256000
+Bee_Motion_Mini.menu.UploadSpeed.230400.windows.upload.speed=256000
+Bee_Motion_Mini.menu.UploadSpeed.230400=230400
+Bee_Motion_Mini.menu.UploadSpeed.230400.upload.speed=230400
+Bee_Motion_Mini.menu.UploadSpeed.460800.linux=460800
+Bee_Motion_Mini.menu.UploadSpeed.460800.macosx=460800
+Bee_Motion_Mini.menu.UploadSpeed.460800.upload.speed=460800
+Bee_Motion_Mini.menu.UploadSpeed.512000.windows=512000
+Bee_Motion_Mini.menu.UploadSpeed.512000.upload.speed=512000
+
+Bee_Motion_Mini.menu.DebugLevel.none=None
+Bee_Motion_Mini.menu.DebugLevel.none.build.code_debug=0
+Bee_Motion_Mini.menu.DebugLevel.error=Error
+Bee_Motion_Mini.menu.DebugLevel.error.build.code_debug=1
+Bee_Motion_Mini.menu.DebugLevel.warn=Warn
+Bee_Motion_Mini.menu.DebugLevel.warn.build.code_debug=2
+Bee_Motion_Mini.menu.DebugLevel.info=Info
+Bee_Motion_Mini.menu.DebugLevel.info.build.code_debug=3
+Bee_Motion_Mini.menu.DebugLevel.debug=Debug
+Bee_Motion_Mini.menu.DebugLevel.debug.build.code_debug=4
+Bee_Motion_Mini.menu.DebugLevel.verbose=Verbose
+Bee_Motion_Mini.menu.DebugLevel.verbose.build.code_debug=5
+
+Bee_Motion_Mini.menu.EraseFlash.none=Disabled
+Bee_Motion_Mini.menu.EraseFlash.none.upload.erase_cmd=
+Bee_Motion_Mini.menu.EraseFlash.all=Enabled
+Bee_Motion_Mini.menu.EraseFlash.all.upload.erase_cmd=-e
+
+###############################################################
+
+Bee_S3.name=Bee S3
+Bee_S3.vid.0=0x303a
+Bee_S3.pid.0=0x8110
+Bee_S3.vid.upload_port.0.vid=0x303a
+Bee_S3.pid.upload_port.0.pid=0x8110
+
+Bee_S3.bootloader.tool=esptool_py
+Bee_S3.bootloader.tool.default=esptool_py
+
+Bee_S3.upload.tool=esptool_py
+Bee_S3.upload.tool.default=esptool_py
+Bee_S3.upload.tool.network=esp_ota
+
+Bee_S3.upload.maximum_size=1310720
+Bee_S3.upload.maximum_data_size=327680
+Bee_S3.upload.flags=
+Bee_S3.upload.extra_flags=
+Bee_S3.upload.use_1200bps_touch=false
+Bee_S3.upload.wait_for_upload_port=false
+
+Bee_S3.serial.disableDTR=false
+Bee_S3.serial.disableRTS=false
+
+Bee_S3.build.tarch=xtensa
+Bee_S3.build.bootloader_addr=0x0
+Bee_S3.build.target=esp32s3
+Bee_S3.build.mcu=esp32s3
+Bee_S3.build.core=esp32
+Bee_S3.build.variant=Bee_S3
+Bee_S3.build.board=Bee_S3
+
+Bee_S3.build.usb_mode=1
+Bee_S3.build.cdc_on_boot=1
+Bee_S3.build.msc_on_boot=0
+Bee_S3.build.dfu_on_boot=0
+Bee_S3.build.f_cpu=240000000L
+Bee_S3.build.flash_size=8MB
+Bee_S3.build.flash_freq=80m
+Bee_S3.build.flash_mode=dio
+Bee_S3.build.boot=qio
+Bee_S3.build.partitions=default_8MB
+Bee_S3.build.defines=
+Bee_S3.build.loop_core=-DARDUINO_RUNNING_CORE=1
+Bee_S3.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+Bee_S3.menu.USBMode.default=USB-OTG
+Bee_S3.menu.USBMode.default.build.usb_mode=0
+Bee_S3.menu.USBMode.default.upload.use_1200bps_touch=true
+Bee_S3.menu.USBMode.default.upload.wait_for_upload_port=true
+Bee_S3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+Bee_S3.menu.USBMode.hwcdc.build.usb_mode=1
+Bee_S3.menu.USBMode.hwcdc.upload.use_1200bps_touch=false
+Bee_S3.menu.USBMode.hwcdc.upload.wait_for_upload_port=false
+
+Bee_S3.menu.CDCOnBoot.cdc=Enabled
+Bee_S3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+Bee_S3.menu.CDCOnBoot.default=Disabled
+Bee_S3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+Bee_S3.menu.MSCOnBoot.default=Disabled
+Bee_S3.menu.MSCOnBoot.default.build.msc_on_boot=0
+Bee_S3.menu.MSCOnBoot.msc=Enabled
+Bee_S3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+Bee_S3.menu.DFUOnBoot.default=Disabled
+Bee_S3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+Bee_S3.menu.DFUOnBoot.dfu=Enabled
+Bee_S3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+Bee_S3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Bee_S3.menu.PartitionScheme.default.build.partitions=default
+Bee_S3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Bee_S3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Bee_S3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+Bee_S3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+Bee_S3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+Bee_S3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+Bee_S3.menu.PartitionScheme.minimal.build.partitions=minimal
+Bee_S3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Bee_S3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Bee_S3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Bee_S3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Bee_S3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Bee_S3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Bee_S3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Bee_S3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Bee_S3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Bee_S3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Bee_S3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Bee_S3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Bee_S3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Bee_S3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Bee_S3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+Bee_S3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+Bee_S3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+Bee_S3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+Bee_S3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+Bee_S3.menu.PartitionScheme.fatflash.build.partitions=ffat
+Bee_S3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+Bee_S3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+Bee_S3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+Bee_S3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+Bee_S3.menu.CPUFreq.240=240MHz (WiFi)
+Bee_S3.menu.CPUFreq.240.build.f_cpu=240000000L
+Bee_S3.menu.CPUFreq.160=160MHz (WiFi)
+Bee_S3.menu.CPUFreq.160.build.f_cpu=160000000L
+Bee_S3.menu.CPUFreq.80=80MHz (WiFi)
+Bee_S3.menu.CPUFreq.80.build.f_cpu=80000000L
+Bee_S3.menu.CPUFreq.40=40MHz
+Bee_S3.menu.CPUFreq.40.build.f_cpu=40000000L
+Bee_S3.menu.CPUFreq.20=20MHz
+Bee_S3.menu.CPUFreq.20.build.f_cpu=20000000L
+Bee_S3.menu.CPUFreq.10=10MHz
+Bee_S3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+Bee_S3.menu.FlashFreq.80=80MHz
+Bee_S3.menu.FlashFreq.80.build.flash_freq=80m
+Bee_S3.menu.FlashFreq.40=40MHz
+Bee_S3.menu.FlashFreq.40.build.flash_freq=40m
+
+Bee_S3.menu.UploadSpeed.921600=921600
+Bee_S3.menu.UploadSpeed.921600.upload.speed=921600
+Bee_S3.menu.UploadSpeed.115200=115200
+Bee_S3.menu.UploadSpeed.115200.upload.speed=115200
+Bee_S3.menu.UploadSpeed.256000.windows=256000
+Bee_S3.menu.UploadSpeed.256000.upload.speed=256000
+Bee_S3.menu.UploadSpeed.230400.windows.upload.speed=256000
+Bee_S3.menu.UploadSpeed.230400=230400
+Bee_S3.menu.UploadSpeed.230400.upload.speed=230400
+Bee_S3.menu.UploadSpeed.460800.linux=460800
+Bee_S3.menu.UploadSpeed.460800.macosx=460800
+Bee_S3.menu.UploadSpeed.460800.upload.speed=460800
+Bee_S3.menu.UploadSpeed.512000.windows=512000
+Bee_S3.menu.UploadSpeed.512000.upload.speed=512000
+
+Bee_S3.menu.DebugLevel.none=None
+Bee_S3.menu.DebugLevel.none.build.code_debug=0
+Bee_S3.menu.DebugLevel.error=Error
+Bee_S3.menu.DebugLevel.error.build.code_debug=1
+Bee_S3.menu.DebugLevel.warn=Warn
+Bee_S3.menu.DebugLevel.warn.build.code_debug=2
+Bee_S3.menu.DebugLevel.info=Info
+Bee_S3.menu.DebugLevel.info.build.code_debug=3
+Bee_S3.menu.DebugLevel.debug=Debug
+Bee_S3.menu.DebugLevel.debug.build.code_debug=4
+Bee_S3.menu.DebugLevel.verbose=Verbose
+Bee_S3.menu.DebugLevel.verbose.build.code_debug=5
+
+Bee_S3.menu.EraseFlash.none=Disabled
+Bee_S3.menu.EraseFlash.none.upload.erase_cmd=
+Bee_S3.menu.EraseFlash.all=Enabled
+Bee_S3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+unphone7.name=unPhone 7
+
+unphone7.bootloader.tool=esptool_py
+unphone7.bootloader.tool.default=esptool_py
+
+unphone7.upload.tool=esptool_py
+unphone7.upload.tool.default=esptool_py
+unphone7.upload.tool.network=esp_ota
+
+unphone7.upload.maximum_size=1310720
+unphone7.upload.maximum_data_size=327680
+unphone7.upload.flags=
+unphone7.upload.extra_flags=
+
+unphone7.serial.disableDTR=true
+unphone7.serial.disableRTS=true
+
+unphone7.build.tarch=xtensa
+unphone7.build.bootloader_addr=0x1000
+unphone7.build.target=esp32
+unphone7.build.mcu=esp32
+unphone7.build.core=esp32
+unphone7.build.variant=feather_esp32
+unphone7.build.board=FEATHER_ESP32
+
+unphone7.build.f_cpu=240000000L
+unphone7.build.flash_mode=dio
+unphone7.build.flash_size=4MB
+unphone7.build.boot=dio
+unphone7.build.partitions=default
+unphone7.build.defines=-DUNPHONE_SPIN=7
+
+unphone7.menu.FlashFreq.80=80MHz
+unphone7.menu.FlashFreq.80.build.flash_freq=80m
+unphone7.menu.FlashFreq.40=40MHz
+unphone7.menu.FlashFreq.40.build.flash_freq=40m
+
+unphone7.menu.UploadSpeed.921600=921600
+unphone7.menu.UploadSpeed.921600.upload.speed=921600
+unphone7.menu.UploadSpeed.115200=115200
+unphone7.menu.UploadSpeed.115200.upload.speed=115200
+unphone7.menu.UploadSpeed.256000.windows=256000
+unphone7.menu.UploadSpeed.256000.upload.speed=256000
+unphone7.menu.UploadSpeed.230400.windows.upload.speed=256000
+unphone7.menu.UploadSpeed.230400=230400
+unphone7.menu.UploadSpeed.230400.upload.speed=230400
+unphone7.menu.UploadSpeed.460800.linux=460800
+unphone7.menu.UploadSpeed.460800.macosx=460800
+unphone7.menu.UploadSpeed.460800.upload.speed=460800
+unphone7.menu.UploadSpeed.512000.windows=512000
+unphone7.menu.UploadSpeed.512000.upload.speed=512000
+
+unphone7.menu.DebugLevel.none=None
+unphone7.menu.DebugLevel.none.build.code_debug=0
+unphone7.menu.DebugLevel.error=Error
+unphone7.menu.DebugLevel.error.build.code_debug=1
+unphone7.menu.DebugLevel.warn=Warn
+unphone7.menu.DebugLevel.warn.build.code_debug=2
+unphone7.menu.DebugLevel.info=Info
+unphone7.menu.DebugLevel.info.build.code_debug=3
+unphone7.menu.DebugLevel.debug=Debug
+unphone7.menu.DebugLevel.debug.build.code_debug=4
+unphone7.menu.DebugLevel.verbose=Verbose
+unphone7.menu.DebugLevel.verbose.build.code_debug=5
+
+unphone7.menu.PartitionScheme.default=Default
+unphone7.menu.PartitionScheme.default.build.partitions=default
+unphone7.menu.PartitionScheme.no_ota=No OTA (Large APP)
+unphone7.menu.PartitionScheme.no_ota.build.partitions=no_ota
+unphone7.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+unphone7.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (Large APPS with OTA)
+unphone7.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+unphone7.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+unphone7.menu.EraseFlash.none=Disabled
+unphone7.menu.EraseFlash.none.upload.erase_cmd=
+unphone7.menu.EraseFlash.all=Enabled
+unphone7.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+unphone8.name=unPhone 8
+unphone8.vid.0=0x16D0
+unphone8.pid.0=0x1178
+
+unphone8.bootloader.tool=esptool_py
+unphone8.bootloader.tool.default=esptool_py
+
+unphone8.upload.tool=esptool_py
+unphone8.upload.tool.default=esptool_py
+unphone8.upload.tool.network=esp_ota
+
+unphone8.upload.maximum_size=8323072
+unphone8.upload.maximum_data_size=2424832
+unphone8.upload.flags=
+unphone8.upload.extra_flags=
+unphone8.upload.use_1200bps_touch=false
+unphone8.upload.wait_for_upload_port=false
+
+unphone8.serial.disableDTR=false
+unphone8.serial.disableRTS=false
+
+unphone8.build.tarch=xtensa
+unphone8.build.bootloader_addr=0x0
+unphone8.build.target=esp32s3
+unphone8.build.mcu=esp32s3
+unphone8.build.core=esp32
+unphone8.build.variant=unphone8
+unphone8.build.board=unphone8
+
+unphone8.build.usb_mode=1
+unphone8.build.cdc_on_boot=0
+unphone8.build.msc_on_boot=0
+unphone8.build.dfu_on_boot=0
+unphone8.build.f_cpu=240000000L
+unphone8.build.flash_size=8MB
+unphone8.build.flash_freq=80m
+unphone8.build.flash_mode=dio
+unphone8.build.boot=qio
+unphone8.build.boot_freq=80m
+unphone8.build.partitions=default_8MB
+unphone8.build.defines=-DBOARD_HAS_PSRAM -DUNPHONE_SPIN=8
+unphone8.build.loop_core=-DARDUINO_RUNNING_CORE=1
+unphone8.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+unphone8.build.flash_type=qio
+unphone8.build.psram_type=qspi
+unphone8.build.memory_type={build.flash_type}_{build.psram_type}
+
+unphone8.menu.USBMode.default=Hardware CDC and JTAG
+unphone8.menu.USBMode.default.build.usb_mode=1
+unphone8.menu.USBMode.hwcdc=USB-OTG (TinyUSB)
+unphone8.menu.USBMode.hwcdc.build.usb_mode=0
+
+unphone8.menu.CDCOnBoot.default=Disabled
+unphone8.menu.CDCOnBoot.default.build.cdc_on_boot=0
+unphone8.menu.CDCOnBoot.cdc=Enabled
+unphone8.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+unphone8.menu.MSCOnBoot.default=Disabled
+unphone8.menu.MSCOnBoot.default.build.msc_on_boot=0
+unphone8.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+unphone8.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+unphone8.menu.DFUOnBoot.default=Disabled
+unphone8.menu.DFUOnBoot.default.build.dfu_on_boot=0
+unphone8.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+unphone8.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+unphone8.menu.UploadMode.default=UART0 / Hardware CDC
+unphone8.menu.UploadMode.default.upload.use_1200bps_touch=false
+unphone8.menu.UploadMode.default.upload.wait_for_upload_port=false
+unphone8.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+unphone8.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+unphone8.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+unphone8.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+unphone8.menu.PartitionScheme.default.build.partitions=default
+unphone8.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+unphone8.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+unphone8.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+unphone8.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+unphone8.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+unphone8.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+unphone8.menu.PartitionScheme.minimal.build.partitions=minimal
+unphone8.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+unphone8.menu.PartitionScheme.no_ota.build.partitions=no_ota
+unphone8.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+unphone8.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+unphone8.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+unphone8.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+unphone8.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+unphone8.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+unphone8.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+unphone8.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+unphone8.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+unphone8.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+unphone8.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+unphone8.menu.PartitionScheme.huge_app.build.partitions=huge_app
+unphone8.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+unphone8.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+unphone8.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+unphone8.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+unphone8.menu.PartitionScheme.rainmaker=RainMaker 4MB
+unphone8.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+unphone8.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+unphone8.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+unphone8.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+unphone8.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+unphone8.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+unphone8.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+unphone8.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+unphone8.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS)
+unphone8.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB
+
+unphone8.menu.CPUFreq.240=240MHz (WiFi)
+unphone8.menu.CPUFreq.240.build.f_cpu=240000000L
+unphone8.menu.CPUFreq.160=160MHz (WiFi)
+unphone8.menu.CPUFreq.160.build.f_cpu=160000000L
+unphone8.menu.CPUFreq.80=80MHz (WiFi)
+unphone8.menu.CPUFreq.80.build.f_cpu=80000000L
+unphone8.menu.CPUFreq.40=40MHz
+unphone8.menu.CPUFreq.40.build.f_cpu=40000000L
+unphone8.menu.CPUFreq.20=20MHz
+unphone8.menu.CPUFreq.20.build.f_cpu=20000000L
+unphone8.menu.CPUFreq.10=10MHz
+unphone8.menu.CPUFreq.10.build.f_cpu=10000000L
+
+unphone8.menu.UploadSpeed.921600=921600
+unphone8.menu.UploadSpeed.921600.upload.speed=921600
+unphone8.menu.UploadSpeed.115200=115200
+unphone8.menu.UploadSpeed.115200.upload.speed=115200
+unphone8.menu.UploadSpeed.256000.windows=256000
+unphone8.menu.UploadSpeed.256000.upload.speed=256000
+unphone8.menu.UploadSpeed.230400.windows.upload.speed=256000
+unphone8.menu.UploadSpeed.230400=230400
+unphone8.menu.UploadSpeed.230400.upload.speed=230400
+unphone8.menu.UploadSpeed.460800.linux=460800
+unphone8.menu.UploadSpeed.460800.macosx=460800
+unphone8.menu.UploadSpeed.460800.upload.speed=460800
+unphone8.menu.UploadSpeed.512000.windows=512000
+unphone8.menu.UploadSpeed.512000.upload.speed=512000
+
+unphone8.menu.DebugLevel.none=None
+unphone8.menu.DebugLevel.none.build.code_debug=0
+unphone8.menu.DebugLevel.error=Error
+unphone8.menu.DebugLevel.error.build.code_debug=1
+unphone8.menu.DebugLevel.warn=Warn
+unphone8.menu.DebugLevel.warn.build.code_debug=2
+unphone8.menu.DebugLevel.info=Info
+unphone8.menu.DebugLevel.info.build.code_debug=3
+unphone8.menu.DebugLevel.debug=Debug
+unphone8.menu.DebugLevel.debug.build.code_debug=4
+unphone8.menu.DebugLevel.verbose=Verbose
+unphone8.menu.DebugLevel.verbose.build.code_debug=5
+
+#############################################################
+
+unphone9.name=unPhone 9
+unphone9.vid.0=0x16D0
+unphone9.pid.0=0x1178
+
+unphone9.bootloader.tool=esptool_py
+unphone9.bootloader.tool.default=esptool_py
+
+unphone9.upload.tool=esptool_py
+unphone9.upload.tool.default=esptool_py
+unphone9.upload.tool.network=esp_ota
+
+unphone9.upload.maximum_size=8323072
+unphone9.upload.maximum_data_size=8716288
+unphone9.upload.flags=
+unphone9.upload.extra_flags=
+unphone9.upload.use_1200bps_touch=false
+unphone9.upload.wait_for_upload_port=false
+
+unphone9.serial.disableDTR=false
+unphone9.serial.disableRTS=false
+
+unphone9.build.tarch=xtensa
+unphone9.build.bootloader_addr=0x0
+unphone9.build.target=esp32s3
+unphone9.build.mcu=esp32s3
+unphone9.build.core=esp32
+unphone9.build.variant=unphone9
+unphone9.build.board=unphone9
+
+unphone9.build.usb_mode=1
+unphone9.build.cdc_on_boot=1
+unphone9.build.msc_on_boot=0
+unphone9.build.dfu_on_boot=0
+unphone9.build.f_cpu=240000000L
+unphone9.build.flash_size=8MB
+unphone9.build.flash_freq=80m
+unphone9.build.flash_mode=dio
+unphone9.build.boot=qio
+unphone9.build.boot_freq=80m
+unphone9.build.partitions=default_8MB
+unphone9.build.defines=-DBOARD_HAS_PSRAM -DUNPHONE_SPIN=9
+unphone9.build.loop_core=-DARDUINO_RUNNING_CORE=1
+unphone9.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+unphone9.build.flash_type=qio
+unphone9.build.psram_type=qspi
+unphone9.build.memory_type={build.flash_type}_{build.psram_type}
+
+unphone9.menu.USBMode.default=Hardware CDC and JTAG
+unphone9.menu.USBMode.default.build.usb_mode=1
+unphone9.menu.USBMode.hwcdc=USB-OTG (TinyUSB)
+unphone9.menu.USBMode.hwcdc.build.usb_mode=0
+
+unphone9.menu.CDCOnBoot.default=Enabled
+unphone9.menu.CDCOnBoot.default.build.cdc_on_boot=1
+unphone9.menu.CDCOnBoot.cdc=Disabled
+unphone9.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+unphone9.menu.MSCOnBoot.default=Disabled
+unphone9.menu.MSCOnBoot.default.build.msc_on_boot=0
+unphone9.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+unphone9.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+unphone9.menu.DFUOnBoot.default=Disabled
+unphone9.menu.DFUOnBoot.default.build.dfu_on_boot=0
+unphone9.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+unphone9.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+unphone9.menu.UploadMode.default=UART0 / Hardware CDC
+unphone9.menu.UploadMode.default.upload.use_1200bps_touch=false
+unphone9.menu.UploadMode.default.upload.wait_for_upload_port=false
+unphone9.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+unphone9.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+unphone9.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+unphone9.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+unphone9.menu.PartitionScheme.default.build.partitions=default
+unphone9.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+unphone9.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+unphone9.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+unphone9.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+unphone9.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+unphone9.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+unphone9.menu.PartitionScheme.minimal.build.partitions=minimal
+unphone9.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+unphone9.menu.PartitionScheme.no_ota.build.partitions=no_ota
+unphone9.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+unphone9.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+unphone9.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+unphone9.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+unphone9.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+unphone9.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+unphone9.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+unphone9.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+unphone9.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+unphone9.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+unphone9.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+unphone9.menu.PartitionScheme.huge_app.build.partitions=huge_app
+unphone9.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+unphone9.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+unphone9.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+unphone9.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+unphone9.menu.PartitionScheme.rainmaker=RainMaker 4MB
+unphone9.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+unphone9.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+unphone9.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+unphone9.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+unphone9.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+unphone9.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+unphone9.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+unphone9.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+unphone9.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS)
+unphone9.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB
+
+unphone9.menu.CPUFreq.240=240MHz (WiFi)
+unphone9.menu.CPUFreq.240.build.f_cpu=240000000L
+unphone9.menu.CPUFreq.160=160MHz (WiFi)
+unphone9.menu.CPUFreq.160.build.f_cpu=160000000L
+unphone9.menu.CPUFreq.80=80MHz (WiFi)
+unphone9.menu.CPUFreq.80.build.f_cpu=80000000L
+unphone9.menu.CPUFreq.40=40MHz
+unphone9.menu.CPUFreq.40.build.f_cpu=40000000L
+unphone9.menu.CPUFreq.20=20MHz
+unphone9.menu.CPUFreq.20.build.f_cpu=20000000L
+unphone9.menu.CPUFreq.10=10MHz
+unphone9.menu.CPUFreq.10.build.f_cpu=10000000L
+
+unphone9.menu.UploadSpeed.921600=921600
+unphone9.menu.UploadSpeed.921600.upload.speed=921600
+unphone9.menu.UploadSpeed.115200=115200
+unphone9.menu.UploadSpeed.115200.upload.speed=115200
+unphone9.menu.UploadSpeed.256000.windows=256000
+unphone9.menu.UploadSpeed.256000.upload.speed=256000
+unphone9.menu.UploadSpeed.230400.windows.upload.speed=256000
+unphone9.menu.UploadSpeed.230400=230400
+unphone9.menu.UploadSpeed.230400.upload.speed=230400
+unphone9.menu.UploadSpeed.460800.linux=460800
+unphone9.menu.UploadSpeed.460800.macosx=460800
+unphone9.menu.UploadSpeed.460800.upload.speed=460800
+unphone9.menu.UploadSpeed.512000.windows=512000
+unphone9.menu.UploadSpeed.512000.upload.speed=512000
+
+unphone9.menu.DebugLevel.none=None
+unphone9.menu.DebugLevel.none.build.code_debug=0
+unphone9.menu.DebugLevel.error=Error
+unphone9.menu.DebugLevel.error.build.code_debug=1
+unphone9.menu.DebugLevel.warn=Warn
+unphone9.menu.DebugLevel.warn.build.code_debug=2
+unphone9.menu.DebugLevel.info=Info
+unphone9.menu.DebugLevel.info.build.code_debug=3
+unphone9.menu.DebugLevel.debug=Debug
+unphone9.menu.DebugLevel.debug.build.code_debug=4
+unphone9.menu.DebugLevel.verbose=Verbose
+unphone9.menu.DebugLevel.verbose.build.code_debug=5
+
+unphone9.menu.EraseFlash.none=Disabled
+unphone9.menu.EraseFlash.none.upload.erase_cmd=
+unphone9.menu.EraseFlash.all=Enabled
+unphone9.menu.EraseFlash.all.upload.erase_cmd=-e
+
+###############################################################
+# Cytron Maker Feather AIoT S3
+
+cytron_maker_feather_aiot_s3.name=Cytron Maker Feather AIoT S3
+cytron_maker_feather_aiot_s3.vid.0=0x303a
+cytron_maker_feather_aiot_s3.pid.0=0x80f8
+
+cytron_maker_feather_aiot_s3.bootloader.tool=esptool_py
+cytron_maker_feather_aiot_s3.bootloader.tool.default=esptool_py
+
+cytron_maker_feather_aiot_s3.upload.tool=esptool_py
+cytron_maker_feather_aiot_s3.upload.tool.default=esptool_py
+cytron_maker_feather_aiot_s3.upload.tool.network=esp_ota
+
+cytron_maker_feather_aiot_s3.upload.maximum_size=1310720
+cytron_maker_feather_aiot_s3.upload.maximum_data_size=327680
+cytron_maker_feather_aiot_s3.upload.flags=
+cytron_maker_feather_aiot_s3.upload.extra_flags=
+cytron_maker_feather_aiot_s3.upload.use_1200bps_touch=true
+cytron_maker_feather_aiot_s3.upload.wait_for_upload_port=true
+
+cytron_maker_feather_aiot_s3.serial.disableDTR=false
+cytron_maker_feather_aiot_s3.serial.disableRTS=false
+
+cytron_maker_feather_aiot_s3.build.tarch=xtensa
+cytron_maker_feather_aiot_s3.build.bootloader_addr=0x0
+cytron_maker_feather_aiot_s3.build.target=esp32s3
+cytron_maker_feather_aiot_s3.build.mcu=esp32s3
+cytron_maker_feather_aiot_s3.build.core=esp32
+cytron_maker_feather_aiot_s3.build.variant=cytron_maker_feather_aiot_s3
+cytron_maker_feather_aiot_s3.build.board=CYTRON_MAKER_FEATHER_AIOT_S3
+
+cytron_maker_feather_aiot_s3.build.usb_mode=0
+cytron_maker_feather_aiot_s3.build.cdc_on_boot=1
+cytron_maker_feather_aiot_s3.build.msc_on_boot=0
+cytron_maker_feather_aiot_s3.build.dfu_on_boot=0
+cytron_maker_feather_aiot_s3.build.f_cpu=240000000L
+cytron_maker_feather_aiot_s3.build.flash_size=8MB
+cytron_maker_feather_aiot_s3.build.flash_freq=80m
+cytron_maker_feather_aiot_s3.build.flash_mode=dio
+cytron_maker_feather_aiot_s3.build.boot=qio
+cytron_maker_feather_aiot_s3.build.partitions=default
+cytron_maker_feather_aiot_s3.build.defines=
+cytron_maker_feather_aiot_s3.build.loop_core=
+cytron_maker_feather_aiot_s3.build.event_core=
+cytron_maker_feather_aiot_s3.build.flash_type=qio
+cytron_maker_feather_aiot_s3.build.psram_type=opi
+cytron_maker_feather_aiot_s3.build.memory_type={build.flash_type}_{build.psram_type}
+
+cytron_maker_feather_aiot_s3.menu.LoopCore.1=Core 1
+cytron_maker_feather_aiot_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+cytron_maker_feather_aiot_s3.menu.LoopCore.0=Core 0
+cytron_maker_feather_aiot_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+cytron_maker_feather_aiot_s3.menu.EventsCore.1=Core 1
+cytron_maker_feather_aiot_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+cytron_maker_feather_aiot_s3.menu.EventsCore.0=Core 0
+cytron_maker_feather_aiot_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+cytron_maker_feather_aiot_s3.menu.USBMode.default=USB-OTG (TinyUSB)
+cytron_maker_feather_aiot_s3.menu.USBMode.default.build.usb_mode=0
+cytron_maker_feather_aiot_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+cytron_maker_feather_aiot_s3.menu.USBMode.hwcdc.build.usb_mode=1
+
+cytron_maker_feather_aiot_s3.menu.CDCOnBoot.cdc=Enabled
+cytron_maker_feather_aiot_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+cytron_maker_feather_aiot_s3.menu.CDCOnBoot.default=Disabled
+cytron_maker_feather_aiot_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+cytron_maker_feather_aiot_s3.menu.MSCOnBoot.default=Disabled
+cytron_maker_feather_aiot_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+cytron_maker_feather_aiot_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+cytron_maker_feather_aiot_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+cytron_maker_feather_aiot_s3.menu.DFUOnBoot.default=Disabled
+cytron_maker_feather_aiot_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+cytron_maker_feather_aiot_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+cytron_maker_feather_aiot_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+cytron_maker_feather_aiot_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+cytron_maker_feather_aiot_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+cytron_maker_feather_aiot_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+cytron_maker_feather_aiot_s3.menu.UploadMode.default=UART0 / Hardware CDC
+cytron_maker_feather_aiot_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+cytron_maker_feather_aiot_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+cytron_maker_feather_aiot_s3.menu.PSRAM.opi=OPI PSRAM
+cytron_maker_feather_aiot_s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+cytron_maker_feather_aiot_s3.menu.PSRAM.opi.build.psram_type=opi
+cytron_maker_feather_aiot_s3.menu.PSRAM.enabled=QSPI PSRAM
+cytron_maker_feather_aiot_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+cytron_maker_feather_aiot_s3.menu.PSRAM.enabled.build.psram_type=qspi
+cytron_maker_feather_aiot_s3.menu.PSRAM.disabled=Disabled
+cytron_maker_feather_aiot_s3.menu.PSRAM.disabled.build.defines=
+cytron_maker_feather_aiot_s3.menu.PSRAM.disabled.build.psram_type=qspi
+
+cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FFAT)
+cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-8MB-tinyuf2
+cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+cytron_maker_feather_aiot_s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+cytron_maker_feather_aiot_s3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+cytron_maker_feather_aiot_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+cytron_maker_feather_aiot_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+
+cytron_maker_feather_aiot_s3.menu.CPUFreq.240=240MHz (WiFi)
+cytron_maker_feather_aiot_s3.menu.CPUFreq.240.build.f_cpu=240000000L
+cytron_maker_feather_aiot_s3.menu.CPUFreq.160=160MHz (WiFi)
+cytron_maker_feather_aiot_s3.menu.CPUFreq.160.build.f_cpu=160000000L
+cytron_maker_feather_aiot_s3.menu.CPUFreq.80=80MHz (WiFi)
+cytron_maker_feather_aiot_s3.menu.CPUFreq.80.build.f_cpu=80000000L
+cytron_maker_feather_aiot_s3.menu.CPUFreq.40=40MHz
+cytron_maker_feather_aiot_s3.menu.CPUFreq.40.build.f_cpu=40000000L
+cytron_maker_feather_aiot_s3.menu.CPUFreq.20=20MHz
+cytron_maker_feather_aiot_s3.menu.CPUFreq.20.build.f_cpu=20000000L
+cytron_maker_feather_aiot_s3.menu.CPUFreq.10=10MHz
+cytron_maker_feather_aiot_s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio=QIO 80MHz
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio.build.flash_mode=dio
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio.build.boot=qio
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio.build.boot_freq=80m
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio.build.flash_freq=80m
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio120=QIO 120MHz
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio120.build.flash_mode=dio
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio120.build.boot=qio
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio120.build.boot_freq=120m
+cytron_maker_feather_aiot_s3.menu.FlashMode.qio120.build.flash_freq=80m
+cytron_maker_feather_aiot_s3.menu.FlashMode.dio=DIO 80MHz
+cytron_maker_feather_aiot_s3.menu.FlashMode.dio.build.flash_mode=dio
+cytron_maker_feather_aiot_s3.menu.FlashMode.dio.build.boot=dio
+cytron_maker_feather_aiot_s3.menu.FlashMode.dio.build.boot_freq=80m
+cytron_maker_feather_aiot_s3.menu.FlashMode.dio.build.flash_freq=80m
+cytron_maker_feather_aiot_s3.menu.FlashMode.opi=OPI 80MHz
+cytron_maker_feather_aiot_s3.menu.FlashMode.opi.build.flash_mode=dout
+cytron_maker_feather_aiot_s3.menu.FlashMode.opi.build.boot=opi
+cytron_maker_feather_aiot_s3.menu.FlashMode.opi.build.boot_freq=80m
+cytron_maker_feather_aiot_s3.menu.FlashMode.opi.build.flash_freq=80m
+
+cytron_maker_feather_aiot_s3.menu.FlashSize.8M=8MB (64Mb)
+cytron_maker_feather_aiot_s3.menu.FlashSize.8M.build.flash_size=8MB
+
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.921600=921600
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.921600.upload.speed=921600
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.115200=115200
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.115200.upload.speed=115200
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.256000.windows=256000
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.256000.upload.speed=256000
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.230400=230400
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.230400.upload.speed=230400
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.460800.linux=460800
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.460800.macosx=460800
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.460800.upload.speed=460800
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.512000.windows=512000
+cytron_maker_feather_aiot_s3.menu.UploadSpeed.512000.upload.speed=512000
+
+cytron_maker_feather_aiot_s3.menu.DebugLevel.none=None
+cytron_maker_feather_aiot_s3.menu.DebugLevel.none.build.code_debug=0
+cytron_maker_feather_aiot_s3.menu.DebugLevel.error=Error
+cytron_maker_feather_aiot_s3.menu.DebugLevel.error.build.code_debug=1
+cytron_maker_feather_aiot_s3.menu.DebugLevel.warn=Warn
+cytron_maker_feather_aiot_s3.menu.DebugLevel.warn.build.code_debug=2
+cytron_maker_feather_aiot_s3.menu.DebugLevel.info=Info
+cytron_maker_feather_aiot_s3.menu.DebugLevel.info.build.code_debug=3
+cytron_maker_feather_aiot_s3.menu.DebugLevel.debug=Debug
+cytron_maker_feather_aiot_s3.menu.DebugLevel.debug.build.code_debug=4
+cytron_maker_feather_aiot_s3.menu.DebugLevel.verbose=Verbose
+cytron_maker_feather_aiot_s3.menu.DebugLevel.verbose.build.code_debug=5
+
+cytron_maker_feather_aiot_s3.menu.EraseFlash.none=Disabled
+cytron_maker_feather_aiot_s3.menu.EraseFlash.none.upload.erase_cmd=
+cytron_maker_feather_aiot_s3.menu.EraseFlash.all=Enabled
+cytron_maker_feather_aiot_s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# RedPill(+) ESP32-S3
+
+redpill_esp32s3.name=RedPill(+) ESP32-S3
+
+redpill_esp32s3.bootloader.tool=esptool_py
+redpill_esp32s3.bootloader.tool.default=esptool_py
+
+redpill_esp32s3.upload.tool=esptool_py
+redpill_esp32s3.upload.tool.default=esptool_py
+redpill_esp32s3.upload.tool.network=esp_ota
+
+redpill_esp32s3.upload.maximum_size=1310720
+redpill_esp32s3.upload.maximum_data_size=327680
+redpill_esp32s3.upload.flags=
+redpill_esp32s3.upload.extra_flags=
+redpill_esp32s3.upload.use_1200bps_touch=true
+redpill_esp32s3.upload.wait_for_upload_port=true
+
+redpill_esp32s3.serial.disableDTR=false
+redpill_esp32s3.serial.disableRTS=false
+
+redpill_esp32s3.build.tarch=xtensa
+redpill_esp32s3.build.bootloader_addr=0x0
+redpill_esp32s3.build.target=esp32s3
+redpill_esp32s3.build.mcu=esp32s3
+redpill_esp32s3.build.core=esp32
+redpill_esp32s3.build.variant=redpill_esp32s3
+redpill_esp32s3.build.board=REDPILL_ESP32S3
+
+redpill_esp32s3.build.usb_mode=0
+redpill_esp32s3.build.cdc_on_boot=1
+redpill_esp32s3.build.msc_on_boot=0
+redpill_esp32s3.build.dfu_on_boot=0
+redpill_esp32s3.build.f_cpu=240000000L
+redpill_esp32s3.build.flash_size=8MB
+redpill_esp32s3.build.flash_freq=80m
+redpill_esp32s3.build.flash_mode=dio
+redpill_esp32s3.build.boot=qio
+redpill_esp32s3.build.partitions=default
+redpill_esp32s3.build.defines=
+redpill_esp32s3.build.loop_core=
+redpill_esp32s3.build.event_core=
+redpill_esp32s3.build.flash_type=qio
+redpill_esp32s3.build.psram_type=qspi
+redpill_esp32s3.build.memory_type={build.flash_type}_{build.psram_type}
+
+redpill_esp32s3.menu.LoopCore.1=Core 1
+redpill_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+redpill_esp32s3.menu.LoopCore.0=Core 0
+redpill_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+redpill_esp32s3.menu.EventsCore.1=Core 1
+redpill_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+redpill_esp32s3.menu.EventsCore.0=Core 0
+redpill_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+redpill_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+redpill_esp32s3.menu.USBMode.default.build.usb_mode=0
+redpill_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+redpill_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+
+redpill_esp32s3.menu.CDCOnBoot.cdc=Enabled
+redpill_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+redpill_esp32s3.menu.CDCOnBoot.default=Disabled
+redpill_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+redpill_esp32s3.menu.MSCOnBoot.default=Disabled
+redpill_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+redpill_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+redpill_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+redpill_esp32s3.menu.DFUOnBoot.default=Disabled
+redpill_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+redpill_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+redpill_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+redpill_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+redpill_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+redpill_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+redpill_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+redpill_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+redpill_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+redpill_esp32s3.menu.PSRAM.enabled=QSPI PSRAM
+redpill_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+redpill_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi
+redpill_esp32s3.menu.PSRAM.disabled=Disabled
+redpill_esp32s3.menu.PSRAM.disabled.build.defines=
+redpill_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi
+redpill_esp32s3.menu.PSRAM.opi=OPI PSRAM
+redpill_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+redpill_esp32s3.menu.PSRAM.opi.build.psram_type=opi
+
+redpill_esp32s3.menu.PartitionScheme.tinyuf2=TinyUF2 8MB (2MB APP/3.7MB FFAT)
+redpill_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+redpill_esp32s3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-8MB-tinyuf2
+redpill_esp32s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+redpill_esp32s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+redpill_esp32s3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+redpill_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+redpill_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+
+redpill_esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+redpill_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+redpill_esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+redpill_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+redpill_esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+redpill_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+redpill_esp32s3.menu.CPUFreq.40=40MHz
+redpill_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+redpill_esp32s3.menu.CPUFreq.20=20MHz
+redpill_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+redpill_esp32s3.menu.CPUFreq.10=10MHz
+redpill_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+redpill_esp32s3.menu.FlashMode.qio=QIO 80MHz
+redpill_esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+redpill_esp32s3.menu.FlashMode.qio.build.boot=qio
+redpill_esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+redpill_esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+redpill_esp32s3.menu.FlashMode.qio120=QIO 120MHz
+redpill_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+redpill_esp32s3.menu.FlashMode.qio120.build.boot=qio
+redpill_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+redpill_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+redpill_esp32s3.menu.FlashMode.dio=DIO 80MHz
+redpill_esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+redpill_esp32s3.menu.FlashMode.dio.build.boot=dio
+redpill_esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+redpill_esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+redpill_esp32s3.menu.FlashMode.opi=OPI 80MHz
+redpill_esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+redpill_esp32s3.menu.FlashMode.opi.build.boot=opi
+redpill_esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+redpill_esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+
+redpill_esp32s3.menu.FlashSize.8M=8MB (64Mb)
+redpill_esp32s3.menu.FlashSize.8M.build.flash_size=8MB
+
+redpill_esp32s3.menu.UploadSpeed.921600=921600
+redpill_esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+redpill_esp32s3.menu.UploadSpeed.115200=115200
+redpill_esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+redpill_esp32s3.menu.UploadSpeed.256000.windows=256000
+redpill_esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+redpill_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+redpill_esp32s3.menu.UploadSpeed.230400=230400
+redpill_esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+redpill_esp32s3.menu.UploadSpeed.460800.linux=460800
+redpill_esp32s3.menu.UploadSpeed.460800.macosx=460800
+redpill_esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+redpill_esp32s3.menu.UploadSpeed.512000.windows=512000
+redpill_esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+redpill_esp32s3.menu.DebugLevel.none=None
+redpill_esp32s3.menu.DebugLevel.none.build.code_debug=0
+redpill_esp32s3.menu.DebugLevel.error=Error
+redpill_esp32s3.menu.DebugLevel.error.build.code_debug=1
+redpill_esp32s3.menu.DebugLevel.warn=Warn
+redpill_esp32s3.menu.DebugLevel.warn.build.code_debug=2
+redpill_esp32s3.menu.DebugLevel.info=Info
+redpill_esp32s3.menu.DebugLevel.info.build.code_debug=3
+redpill_esp32s3.menu.DebugLevel.debug=Debug
+redpill_esp32s3.menu.DebugLevel.debug.build.code_debug=4
+redpill_esp32s3.menu.DebugLevel.verbose=Verbose
+redpill_esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+redpill_esp32s3.menu.EraseFlash.none=Disabled
+redpill_esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+redpill_esp32s3.menu.EraseFlash.all=Enabled
+redpill_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+esp32c3m1IKit.name=ESP-C3-M1-I-Kit
+
+esp32c3m1IKit.bootloader.tool=esptool_py
+esp32c3m1IKit.bootloader.tool.default=esptool_py
+
+esp32c3m1IKit.upload.tool=esptool_py
+esp32c3m1IKit.upload.tool.default=esptool_py
+esp32c3m1IKit.upload.tool.network=esp_ota
+
+esp32c3m1IKit.upload.maximum_size=1310720
+esp32c3m1IKit.upload.maximum_data_size=327680
+esp32c3m1IKit.upload.flags=
+esp32c3m1IKit.upload.extra_flags=
+esp32c3m1IKit.upload.use_1200bps_touch=false
+esp32c3m1IKit.upload.wait_for_upload_port=false
+
+esp32c3m1IKit.serial.disableDTR=false
+esp32c3m1IKit.serial.disableRTS=false
+
+esp32c3m1IKit.build.tarch=riscv32
+esp32c3m1IKit.build.target=esp
+esp32c3m1IKit.build.mcu=esp32c3
+esp32c3m1IKit.build.core=esp32
+esp32c3m1IKit.build.variant=esp_c3_m1_i_kit
+esp32c3m1IKit.build.board=ESP32C3_M1_I_KIT
+esp32c3m1IKit.build.bootloader_addr=0x0
+
+esp32c3m1IKit.build.cdc_on_boot=0
+esp32c3m1IKit.build.f_cpu=160000000L
+esp32c3m1IKit.build.flash_size=4MB
+esp32c3m1IKit.build.flash_freq=80m
+esp32c3m1IKit.build.flash_mode=qio
+esp32c3m1IKit.build.boot=qio
+esp32c3m1IKit.build.partitions=default
+esp32c3m1IKit.build.defines=
+
+esp32c3m1IKit.menu.CDCOnBoot.default=Disabled
+esp32c3m1IKit.menu.CDCOnBoot.default.build.cdc_on_boot=0
+esp32c3m1IKit.menu.CDCOnBoot.cdc=Enabled
+esp32c3m1IKit.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+esp32c3m1IKit.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+esp32c3m1IKit.menu.PartitionScheme.default.build.partitions=default
+esp32c3m1IKit.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+esp32c3m1IKit.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+esp32c3m1IKit.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+esp32c3m1IKit.menu.PartitionScheme.minimal.build.partitions=minimal
+esp32c3m1IKit.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+esp32c3m1IKit.menu.PartitionScheme.no_ota.build.partitions=no_ota
+esp32c3m1IKit.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+esp32c3m1IKit.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+esp32c3m1IKit.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+esp32c3m1IKit.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+esp32c3m1IKit.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+esp32c3m1IKit.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+esp32c3m1IKit.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+esp32c3m1IKit.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+esp32c3m1IKit.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+esp32c3m1IKit.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+esp32c3m1IKit.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+esp32c3m1IKit.menu.PartitionScheme.huge_app.build.partitions=huge_app
+esp32c3m1IKit.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+esp32c3m1IKit.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+esp32c3m1IKit.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+esp32c3m1IKit.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+esp32c3m1IKit.menu.PartitionScheme.rainmaker=RainMaker 4MB
+esp32c3m1IKit.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+esp32c3m1IKit.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+esp32c3m1IKit.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+esp32c3m1IKit.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+esp32c3m1IKit.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+esp32c3m1IKit.menu.CPUFreq.160=160MHz (WiFi)
+esp32c3m1IKit.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32c3m1IKit.menu.CPUFreq.80=80MHz (WiFi)
+esp32c3m1IKit.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32c3m1IKit.menu.CPUFreq.40=40MHz
+esp32c3m1IKit.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32c3m1IKit.menu.CPUFreq.20=20MHz
+esp32c3m1IKit.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32c3m1IKit.menu.CPUFreq.10=10MHz
+esp32c3m1IKit.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32c3m1IKit.menu.UploadSpeed.921600=921600
+esp32c3m1IKit.menu.UploadSpeed.921600.upload.speed=921600
+esp32c3m1IKit.menu.UploadSpeed.115200=115200
+esp32c3m1IKit.menu.UploadSpeed.115200.upload.speed=115200
+esp32c3m1IKit.menu.UploadSpeed.256000.windows=256000
+esp32c3m1IKit.menu.UploadSpeed.256000.upload.speed=256000
+esp32c3m1IKit.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32c3m1IKit.menu.UploadSpeed.230400=230400
+esp32c3m1IKit.menu.UploadSpeed.230400.upload.speed=230400
+esp32c3m1IKit.menu.UploadSpeed.460800.linux=460800
+esp32c3m1IKit.menu.UploadSpeed.460800.macosx=460800
+esp32c3m1IKit.menu.UploadSpeed.460800.upload.speed=460800
+esp32c3m1IKit.menu.UploadSpeed.512000.windows=512000
+esp32c3m1IKit.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32c3m1IKit.menu.DebugLevel.none=None
+esp32c3m1IKit.menu.DebugLevel.none.build.code_debug=0
+esp32c3m1IKit.menu.DebugLevel.error=Error
+esp32c3m1IKit.menu.DebugLevel.error.build.code_debug=1
+esp32c3m1IKit.menu.DebugLevel.warn=Warn
+esp32c3m1IKit.menu.DebugLevel.warn.build.code_debug=2
+esp32c3m1IKit.menu.DebugLevel.info=Info
+esp32c3m1IKit.menu.DebugLevel.info.build.code_debug=3
+esp32c3m1IKit.menu.DebugLevel.debug=Debug
+esp32c3m1IKit.menu.DebugLevel.debug.build.code_debug=4
+esp32c3m1IKit.menu.DebugLevel.verbose=Verbose
+esp32c3m1IKit.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32c3m1IKit.menu.EraseFlash.none=Disabled
+esp32c3m1IKit.menu.EraseFlash.none.upload.erase_cmd=
+esp32c3m1IKit.menu.EraseFlash.all=Enabled
+esp32c3m1IKit.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+roboheart_hercules.name=RoboHeart Hercules
+
+roboheart_hercules.upload.tool=esptool_py
+roboheart_hercules.upload.tool.default=esptool_py
+roboheart_hercules.upload.maximum_size=1310720
+roboheart_hercules.upload.maximum_data_size=327680
+roboheart_hercules.upload.wait_for_upload_port=true
+roboheart_hercules.upload.flags=
+roboheart_hercules.upload.extra_flags=
+
+roboheart_hercules.serial.disableDTR=true
+roboheart_hercules.serial.disableRTS=true
+
+roboheart_hercules.build.tarch=xtensa
+roboheart_hercules.build.bootloader_addr=0x1000
+roboheart_hercules.build.target=esp32
+roboheart_hercules.build.mcu=esp32
+roboheart_hercules.build.core=esp32
+roboheart_hercules.build.variant=roboheart_hercules
+roboheart_hercules.build.board=roboheart_hercules
+
+roboheart_hercules.build.f_cpu=240000000L
+roboheart_hercules.build.flash_size=4MB
+roboheart_hercules.build.flash_freq=40m
+roboheart_hercules.build.flash_mode=dio
+roboheart_hercules.build.boot=dio
+roboheart_hercules.build.partitions=default
+roboheart_hercules.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+roboheart_hercules.build.extra_libs=
+
+roboheart_hercules.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+roboheart_hercules.menu.PartitionScheme.default.build.partitions=default
+roboheart_hercules.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+roboheart_hercules.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+roboheart_hercules.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
+roboheart_hercules.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+roboheart_hercules.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+roboheart_hercules.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+roboheart_hercules.menu.PartitionScheme.minimal.build.partitions=minimal
+roboheart_hercules.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+roboheart_hercules.menu.PartitionScheme.no_ota.build.partitions=no_ota
+roboheart_hercules.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+roboheart_hercules.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+roboheart_hercules.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+roboheart_hercules.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+roboheart_hercules.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+roboheart_hercules.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+roboheart_hercules.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+roboheart_hercules.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+roboheart_hercules.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+roboheart_hercules.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+roboheart_hercules.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+roboheart_hercules.menu.PartitionScheme.huge_app.build.partitions=huge_app
+roboheart_hercules.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+roboheart_hercules.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+roboheart_hercules.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+roboheart_hercules.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+roboheart_hercules.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+roboheart_hercules.menu.PartitionScheme.fatflash.build.partitions=ffat
+roboheart_hercules.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+roboheart_hercules.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+roboheart_hercules.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+roboheart_hercules.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+roboheart_hercules.menu.PartitionScheme.rainmaker=RainMaker 4MB
+roboheart_hercules.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+roboheart_hercules.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+roboheart_hercules.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+roboheart_hercules.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+roboheart_hercules.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+roboheart_hercules.menu.CPUFreq.240=240MHz (WiFi/BT)
+roboheart_hercules.menu.CPUFreq.240.build.f_cpu=240000000L
+roboheart_hercules.menu.CPUFreq.160=160MHz (WiFi/BT)
+roboheart_hercules.menu.CPUFreq.160.build.f_cpu=160000000L
+roboheart_hercules.menu.CPUFreq.80=80MHz (WiFi/BT)
+roboheart_hercules.menu.CPUFreq.80.build.f_cpu=80000000L
+roboheart_hercules.menu.CPUFreq.40=40MHz
+roboheart_hercules.menu.CPUFreq.40.build.f_cpu=40000000L
+roboheart_hercules.menu.CPUFreq.20=20MHz
+roboheart_hercules.menu.CPUFreq.20.build.f_cpu=20000000L
+roboheart_hercules.menu.CPUFreq.10=10MHz
+roboheart_hercules.menu.CPUFreq.10.build.f_cpu=10000000L
+
+roboheart_hercules.menu.FlashMode.qio=QIO
+roboheart_hercules.menu.FlashMode.qio.build.flash_mode=dio
+roboheart_hercules.menu.FlashMode.qio.build.boot=qio
+roboheart_hercules.menu.FlashMode.dio=DIO
+roboheart_hercules.menu.FlashMode.dio.build.flash_mode=dio
+roboheart_hercules.menu.FlashMode.dio.build.boot=dio
+
+roboheart_hercules.menu.FlashFreq.80=80MHz
+roboheart_hercules.menu.FlashFreq.80.build.flash_freq=80m
+roboheart_hercules.menu.FlashFreq.40=40MHz
+roboheart_hercules.menu.FlashFreq.40.build.flash_freq=40m
+
+roboheart_hercules.menu.UploadSpeed.921600=921600
+roboheart_hercules.menu.UploadSpeed.921600.upload.speed=921600
+roboheart_hercules.menu.UploadSpeed.115200=115200
+roboheart_hercules.menu.UploadSpeed.115200.upload.speed=115200
+roboheart_hercules.menu.UploadSpeed.256000.windows=256000
+roboheart_hercules.menu.UploadSpeed.256000.upload.speed=256000
+roboheart_hercules.menu.UploadSpeed.230400.windows.upload.speed=256000
+roboheart_hercules.menu.UploadSpeed.230400=230400
+roboheart_hercules.menu.UploadSpeed.230400.upload.speed=230400
+roboheart_hercules.menu.UploadSpeed.460800.linux=460800
+roboheart_hercules.menu.UploadSpeed.460800.macosx=460800
+roboheart_hercules.menu.UploadSpeed.460800.upload.speed=460800
+roboheart_hercules.menu.UploadSpeed.512000.windows=512000
+roboheart_hercules.menu.UploadSpeed.512000.upload.speed=512000
+
+roboheart_hercules.menu.DebugLevel.none=None
+roboheart_hercules.menu.DebugLevel.none.build.code_debug=0
+roboheart_hercules.menu.DebugLevel.error=Error
+roboheart_hercules.menu.DebugLevel.error.build.code_debug=1
+roboheart_hercules.menu.DebugLevel.warn=Warn
+roboheart_hercules.menu.DebugLevel.warn.build.code_debug=2
+roboheart_hercules.menu.DebugLevel.info=Info
+roboheart_hercules.menu.DebugLevel.info.build.code_debug=3
+roboheart_hercules.menu.DebugLevel.debug=Debug
+roboheart_hercules.menu.DebugLevel.debug.build.code_debug=4
+roboheart_hercules.menu.DebugLevel.verbose=Verbose
+roboheart_hercules.menu.DebugLevel.verbose.build.code_debug=5
+
+roboheart_hercules.menu.EraseFlash.none=Disabled
+roboheart_hercules.menu.EraseFlash.none.upload.erase_cmd=
+roboheart_hercules.menu.EraseFlash.all=Enabled
+roboheart_hercules.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+VALTRACK_V4_VTS_ESP32_C3.name=VALTRACK_V4_VTS_ESP32_C3
+
+VALTRACK_V4_VTS_ESP32_C3.bootloader.tool=esptool_py
+VALTRACK_V4_VTS_ESP32_C3.bootloader.tool.default=esptool_py
+
+VALTRACK_V4_VTS_ESP32_C3.upload.tool=esptool_py
+VALTRACK_V4_VTS_ESP32_C3.upload.tool.default=esptool_py
+VALTRACK_V4_VTS_ESP32_C3.upload.tool.network=esp_ota
+
+VALTRACK_V4_VTS_ESP32_C3.upload.maximum_size=1310720
+VALTRACK_V4_VTS_ESP32_C3.upload.maximum_data_size=327680
+VALTRACK_V4_VTS_ESP32_C3.upload.flags=
+VALTRACK_V4_VTS_ESP32_C3.upload.extra_flags=
+VALTRACK_V4_VTS_ESP32_C3.upload.use_1200bps_touch=false
+VALTRACK_V4_VTS_ESP32_C3.upload.wait_for_upload_port=false
+
+VALTRACK_V4_VTS_ESP32_C3.serial.disableDTR=false
+VALTRACK_V4_VTS_ESP32_C3.serial.disableRTS=false
+
+VALTRACK_V4_VTS_ESP32_C3.build.tarch=riscv32
+VALTRACK_V4_VTS_ESP32_C3.build.target=esp
+VALTRACK_V4_VTS_ESP32_C3.build.mcu=esp32c3
+VALTRACK_V4_VTS_ESP32_C3.build.core=esp32
+VALTRACK_V4_VTS_ESP32_C3.build.variant=VALTRACK_V4_VTS_ESP32_C3
+VALTRACK_V4_VTS_ESP32_C3.build.board=VALTRACK_V4_VTS_ESP32_C3
+VALTRACK_V4_VTS_ESP32_C3.build.bootloader_addr=0x0
+
+VALTRACK_V4_VTS_ESP32_C3.build.cdc_on_boot=1
+VALTRACK_V4_VTS_ESP32_C3.build.f_cpu=160000000L
+VALTRACK_V4_VTS_ESP32_C3.build.flash_size=4MB
+VALTRACK_V4_VTS_ESP32_C3.build.flash_freq=80m
+VALTRACK_V4_VTS_ESP32_C3.build.flash_mode=qio
+VALTRACK_V4_VTS_ESP32_C3.build.boot=qio
+VALTRACK_V4_VTS_ESP32_C3.build.partitions=default
+VALTRACK_V4_VTS_ESP32_C3.build.defines=
+
+VALTRACK_V4_VTS_ESP32_C3.menu.CDCOnBoot.default=Enabled
+VALTRACK_V4_VTS_ESP32_C3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+VALTRACK_V4_VTS_ESP32_C3.menu.CDCOnBoot.cdc=Disabled
+VALTRACK_V4_VTS_ESP32_C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default.build.partitions=default
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.minimal.build.partitions=minimal
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.fatflash.build.partitions=ffat
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+VALTRACK_V4_VTS_ESP32_C3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.160=160MHz (WiFi)
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.160.build.f_cpu=160000000L
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.80=80MHz (WiFi)
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.80.build.f_cpu=80000000L
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.40=40MHz
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.40.build.f_cpu=40000000L
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.20=20MHz
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.20.build.f_cpu=20000000L
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.10=10MHz
+VALTRACK_V4_VTS_ESP32_C3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.qio=QIO
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.qio.build.flash_mode=dio
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.qio.build.boot=qio
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.dio=DIO
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.dio.build.flash_mode=dio
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashMode.dio.build.boot=dio
+
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashFreq.80=80MHz
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashFreq.80.build.flash_freq=80m
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashFreq.40=40MHz
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashFreq.40.build.flash_freq=40m
+
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.4M=4MB (32Mb)
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.4M.build.flash_size=4MB
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.8M=8MB (64Mb)
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.8M.build.flash_size=8MB
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.2M=2MB (16Mb)
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.2M.build.flash_size=2MB
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.16M=16MB (128Mb)
+VALTRACK_V4_VTS_ESP32_C3.menu.FlashSize.16M.build.flash_size=16MB
+
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.921600=921600
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.921600.upload.speed=921600
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.115200=115200
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.115200.upload.speed=115200
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.256000.windows=256000
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.256000.upload.speed=256000
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.230400.windows.upload.speed=256000
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.230400=230400
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.230400.upload.speed=230400
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.460800.linux=460800
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.460800.macosx=460800
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.460800.upload.speed=460800
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.512000.windows=512000
+VALTRACK_V4_VTS_ESP32_C3.menu.UploadSpeed.512000.upload.speed=512000
+
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.none=None
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.none.build.code_debug=0
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.error=Error
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.error.build.code_debug=1
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.warn=Warn
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.warn.build.code_debug=2
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.info=Info
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.info.build.code_debug=3
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.debug=Debug
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.debug.build.code_debug=4
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.verbose=Verbose
+VALTRACK_V4_VTS_ESP32_C3.menu.DebugLevel.verbose.build.code_debug=5
+
+VALTRACK_V4_VTS_ESP32_C3.menu.EraseFlash.none=Disabled
+VALTRACK_V4_VTS_ESP32_C3.menu.EraseFlash.none.upload.erase_cmd=
+VALTRACK_V4_VTS_ESP32_C3.menu.EraseFlash.all=Enabled
+VALTRACK_V4_VTS_ESP32_C3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+VALTRACK_V4_MFW_ESP32_C3.name=VALTRACK_V4_MFW_ESP32_C3
+
+VALTRACK_V4_MFW_ESP32_C3.bootloader.tool=esptool_py
+VALTRACK_V4_MFW_ESP32_C3.bootloader.tool.default=esptool_py
+
+VALTRACK_V4_MFW_ESP32_C3.upload.tool=esptool_py
+VALTRACK_V4_MFW_ESP32_C3.upload.tool.default=esptool_py
+VALTRACK_V4_MFW_ESP32_C3.upload.tool.network=esp_ota
+
+VALTRACK_V4_MFW_ESP32_C3.upload.maximum_size=1310720
+VALTRACK_V4_MFW_ESP32_C3.upload.maximum_data_size=327680
+VALTRACK_V4_MFW_ESP32_C3.upload.flags=
+VALTRACK_V4_MFW_ESP32_C3.upload.extra_flags=
+VALTRACK_V4_MFW_ESP32_C3.upload.use_1200bps_touch=false
+VALTRACK_V4_MFW_ESP32_C3.upload.wait_for_upload_port=false
+
+VALTRACK_V4_MFW_ESP32_C3.serial.disableDTR=false
+VALTRACK_V4_MFW_ESP32_C3.serial.disableRTS=false
+
+VALTRACK_V4_MFW_ESP32_C3.build.tarch=riscv32
+VALTRACK_V4_MFW_ESP32_C3.build.target=esp
+VALTRACK_V4_MFW_ESP32_C3.build.mcu=esp32c3
+VALTRACK_V4_MFW_ESP32_C3.build.core=esp32
+VALTRACK_V4_MFW_ESP32_C3.build.variant=VALTRACK_V4_MFW_ESP32_C3
+VALTRACK_V4_MFW_ESP32_C3.build.board=VALTRACK_V4_MFW_ESP32_C3
+VALTRACK_V4_MFW_ESP32_C3.build.bootloader_addr=0x0
+
+VALTRACK_V4_MFW_ESP32_C3.build.cdc_on_boot=1
+VALTRACK_V4_MFW_ESP32_C3.build.f_cpu=160000000L
+VALTRACK_V4_MFW_ESP32_C3.build.flash_size=4MB
+VALTRACK_V4_MFW_ESP32_C3.build.flash_freq=80m
+VALTRACK_V4_MFW_ESP32_C3.build.flash_mode=qio
+VALTRACK_V4_MFW_ESP32_C3.build.boot=qio
+VALTRACK_V4_MFW_ESP32_C3.build.partitions=default
+VALTRACK_V4_MFW_ESP32_C3.build.defines=
+
+VALTRACK_V4_MFW_ESP32_C3.menu.CDCOnBoot.default=Enabled
+VALTRACK_V4_MFW_ESP32_C3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+VALTRACK_V4_MFW_ESP32_C3.menu.CDCOnBoot.cdc=Disabled
+VALTRACK_V4_MFW_ESP32_C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default.build.partitions=default
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.minimal.build.partitions=minimal
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.fatflash.build.partitions=ffat
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+VALTRACK_V4_MFW_ESP32_C3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.160=160MHz (WiFi)
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.160.build.f_cpu=160000000L
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.80=80MHz (WiFi)
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.80.build.f_cpu=80000000L
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.40=40MHz
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.40.build.f_cpu=40000000L
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.20=20MHz
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.20.build.f_cpu=20000000L
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.10=10MHz
+VALTRACK_V4_MFW_ESP32_C3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.qio=QIO
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.qio.build.flash_mode=dio
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.qio.build.boot=qio
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.dio=DIO
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.dio.build.flash_mode=dio
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashMode.dio.build.boot=dio
+
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashFreq.80=80MHz
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashFreq.80.build.flash_freq=80m
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashFreq.40=40MHz
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashFreq.40.build.flash_freq=40m
+
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.4M=4MB (32Mb)
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.4M.build.flash_size=4MB
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.8M=8MB (64Mb)
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.8M.build.flash_size=8MB
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.2M=2MB (16Mb)
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.2M.build.flash_size=2MB
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.16M=16MB (128Mb)
+VALTRACK_V4_MFW_ESP32_C3.menu.FlashSize.16M.build.flash_size=16MB
+
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.921600=921600
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.921600.upload.speed=921600
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.115200=115200
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.115200.upload.speed=115200
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.256000.windows=256000
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.256000.upload.speed=256000
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.230400.windows.upload.speed=256000
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.230400=230400
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.230400.upload.speed=230400
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.460800.linux=460800
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.460800.macosx=460800
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.460800.upload.speed=460800
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.512000.windows=512000
+VALTRACK_V4_MFW_ESP32_C3.menu.UploadSpeed.512000.upload.speed=512000
+
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.none=None
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.none.build.code_debug=0
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.error=Error
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.error.build.code_debug=1
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.warn=Warn
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.warn.build.code_debug=2
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.info=Info
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.info.build.code_debug=3
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.debug=Debug
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.debug.build.code_debug=4
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.verbose=Verbose
+VALTRACK_V4_MFW_ESP32_C3.menu.DebugLevel.verbose.build.code_debug=5
+
+VALTRACK_V4_MFW_ESP32_C3.menu.EraseFlash.none=Disabled
+VALTRACK_V4_MFW_ESP32_C3.menu.EraseFlash.none.upload.erase_cmd=
+VALTRACK_V4_MFW_ESP32_C3.menu.EraseFlash.all=Enabled
+VALTRACK_V4_MFW_ESP32_C3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+Edgebox-ESP-100.name=Edgebox-ESP-100
+
+Edgebox-ESP-100.bootloader.tool=esptool_py
+Edgebox-ESP-100.bootloader.tool.default=esptool_py
+
+Edgebox-ESP-100.upload.tool=esptool_py
+Edgebox-ESP-100.upload.tool.default=esptool_py
+Edgebox-ESP-100.upload.tool.network=esp_ota
+
+Edgebox-ESP-100.upload.maximum_size=1310720
+Edgebox-ESP-100.upload.maximum_data_size=327680
+Edgebox-ESP-100.upload.flags=
+Edgebox-ESP-100.upload.extra_flags=
+Edgebox-ESP-100.upload.use_1200bps_touch=false
+Edgebox-ESP-100.upload.wait_for_upload_port=false
+
+Edgebox-ESP-100.serial.disableDTR=false
+Edgebox-ESP-100.serial.disableRTS=false
+
+Edgebox-ESP-100.build.tarch=xtensa
+Edgebox-ESP-100.build.bootloader_addr=0x0
+Edgebox-ESP-100.build.target=esp32s3
+Edgebox-ESP-100.build.mcu=esp32s3
+Edgebox-ESP-100.build.core=esp32
+Edgebox-ESP-100.build.variant=Edgebox-ESP-100
+Edgebox-ESP-100.build.board=Edgebox-ESP-100
+
+Edgebox-ESP-100.build.usb_mode=1
+Edgebox-ESP-100.build.cdc_on_boot=0
+Edgebox-ESP-100.build.msc_on_boot=0
+Edgebox-ESP-100.build.dfu_on_boot=0
+Edgebox-ESP-100.build.f_cpu=240000000L
+Edgebox-ESP-100.build.flash_size=4MB
+Edgebox-ESP-100.build.flash_freq=80m
+Edgebox-ESP-100.build.flash_mode=dio
+Edgebox-ESP-100.build.boot=qio
+Edgebox-ESP-100.build.boot_freq=80m
+Edgebox-ESP-100.build.partitions=default
+Edgebox-ESP-100.build.defines=
+Edgebox-ESP-100.build.loop_core=
+Edgebox-ESP-100.build.event_core=
+Edgebox-ESP-100.build.psram_type=qspi
+Edgebox-ESP-100.build.memory_type={build.boot}_{build.psram_type}
+
+Edgebox-ESP-100.menu.PSRAM.disabled=Disabled
+Edgebox-ESP-100.menu.PSRAM.disabled.build.defines=
+Edgebox-ESP-100.menu.PSRAM.disabled.build.psram_type=qspi
+Edgebox-ESP-100.menu.PSRAM.enabled=QSPI PSRAM
+Edgebox-ESP-100.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+Edgebox-ESP-100.menu.PSRAM.enabled.build.psram_type=qspi
+Edgebox-ESP-100.menu.PSRAM.opi=OPI PSRAM
+Edgebox-ESP-100.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+Edgebox-ESP-100.menu.PSRAM.opi.build.psram_type=opi
+
+Edgebox-ESP-100.menu.FlashMode.qio=QIO 80MHz
+Edgebox-ESP-100.menu.FlashMode.qio.build.flash_mode=dio
+Edgebox-ESP-100.menu.FlashMode.qio.build.boot=qio
+Edgebox-ESP-100.menu.FlashMode.qio.build.boot_freq=80m
+Edgebox-ESP-100.menu.FlashMode.qio.build.flash_freq=80m
+Edgebox-ESP-100.menu.FlashMode.qio120=QIO 120MHz
+Edgebox-ESP-100.menu.FlashMode.qio120.build.flash_mode=dio
+Edgebox-ESP-100.menu.FlashMode.qio120.build.boot=qio
+Edgebox-ESP-100.menu.FlashMode.qio120.build.boot_freq=120m
+Edgebox-ESP-100.menu.FlashMode.qio120.build.flash_freq=80m
+Edgebox-ESP-100.menu.FlashMode.dio=DIO 80MHz
+Edgebox-ESP-100.menu.FlashMode.dio.build.flash_mode=dio
+Edgebox-ESP-100.menu.FlashMode.dio.build.boot=dio
+Edgebox-ESP-100.menu.FlashMode.dio.build.boot_freq=80m
+Edgebox-ESP-100.menu.FlashMode.dio.build.flash_freq=80m
+Edgebox-ESP-100.menu.FlashMode.opi=OPI 80MHz
+Edgebox-ESP-100.menu.FlashMode.opi.build.flash_mode=dout
+Edgebox-ESP-100.menu.FlashMode.opi.build.boot=opi
+Edgebox-ESP-100.menu.FlashMode.opi.build.boot_freq=80m
+Edgebox-ESP-100.menu.FlashMode.opi.build.flash_freq=80m
+
+Edgebox-ESP-100.menu.FlashSize.4M=4MB (32Mb)
+Edgebox-ESP-100.menu.FlashSize.4M.build.flash_size=4MB
+Edgebox-ESP-100.menu.FlashSize.8M=8MB (64Mb)
+Edgebox-ESP-100.menu.FlashSize.8M.build.flash_size=8MB
+Edgebox-ESP-100.menu.FlashSize.16M=16MB (128Mb)
+Edgebox-ESP-100.menu.FlashSize.16M.build.flash_size=16MB
+#Edgebox-ESP-100.menu.FlashSize.32M=32MB (256Mb)
+#Edgebox-ESP-100.menu.FlashSize.32M.build.flash_size=32MB
+
+Edgebox-ESP-100.menu.LoopCore.1=Core 1
+Edgebox-ESP-100.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+Edgebox-ESP-100.menu.LoopCore.0=Core 0
+Edgebox-ESP-100.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+Edgebox-ESP-100.menu.EventsCore.1=Core 1
+Edgebox-ESP-100.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+Edgebox-ESP-100.menu.EventsCore.0=Core 0
+Edgebox-ESP-100.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+Edgebox-ESP-100.menu.USBMode.default=Hardware CDC and JTAG
+Edgebox-ESP-100.menu.USBMode.default.build.usb_mode=1
+Edgebox-ESP-100.menu.USBMode.hwcdc=USB-OTG (TinyUSB)
+Edgebox-ESP-100.menu.USBMode.hwcdc.build.usb_mode=0
+
+Edgebox-ESP-100.menu.CDCOnBoot.default=Disabled
+Edgebox-ESP-100.menu.CDCOnBoot.default.build.cdc_on_boot=0
+Edgebox-ESP-100.menu.CDCOnBoot.cdc=Enabled
+Edgebox-ESP-100.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+Edgebox-ESP-100.menu.MSCOnBoot.default=Disabled
+Edgebox-ESP-100.menu.MSCOnBoot.default.build.msc_on_boot=0
+Edgebox-ESP-100.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+Edgebox-ESP-100.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+Edgebox-ESP-100.menu.DFUOnBoot.default=Disabled
+Edgebox-ESP-100.menu.DFUOnBoot.default.build.dfu_on_boot=0
+Edgebox-ESP-100.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+Edgebox-ESP-100.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+Edgebox-ESP-100.menu.UploadMode.default=UART0 / Hardware CDC
+Edgebox-ESP-100.menu.UploadMode.default.upload.use_1200bps_touch=false
+Edgebox-ESP-100.menu.UploadMode.default.upload.wait_for_upload_port=false
+Edgebox-ESP-100.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+Edgebox-ESP-100.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+Edgebox-ESP-100.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+Edgebox-ESP-100.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Edgebox-ESP-100.menu.PartitionScheme.default.build.partitions=default
+Edgebox-ESP-100.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Edgebox-ESP-100.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Edgebox-ESP-100.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+Edgebox-ESP-100.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+Edgebox-ESP-100.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+Edgebox-ESP-100.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+Edgebox-ESP-100.menu.PartitionScheme.minimal.build.partitions=minimal
+Edgebox-ESP-100.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Edgebox-ESP-100.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Edgebox-ESP-100.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Edgebox-ESP-100.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Edgebox-ESP-100.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Edgebox-ESP-100.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Edgebox-ESP-100.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Edgebox-ESP-100.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Edgebox-ESP-100.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Edgebox-ESP-100.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Edgebox-ESP-100.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Edgebox-ESP-100.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Edgebox-ESP-100.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Edgebox-ESP-100.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Edgebox-ESP-100.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+Edgebox-ESP-100.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+Edgebox-ESP-100.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+Edgebox-ESP-100.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+Edgebox-ESP-100.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+Edgebox-ESP-100.menu.PartitionScheme.fatflash.build.partitions=ffat
+Edgebox-ESP-100.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+Edgebox-ESP-100.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+Edgebox-ESP-100.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+Edgebox-ESP-100.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+Edgebox-ESP-100.menu.PartitionScheme.rainmaker=RainMaker 4MB
+Edgebox-ESP-100.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+Edgebox-ESP-100.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+Edgebox-ESP-100.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+Edgebox-ESP-100.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+Edgebox-ESP-100.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+Edgebox-ESP-100.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+Edgebox-ESP-100.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+Edgebox-ESP-100.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+Edgebox-ESP-100.menu.CPUFreq.240=240MHz (WiFi)
+Edgebox-ESP-100.menu.CPUFreq.240.build.f_cpu=240000000L
+Edgebox-ESP-100.menu.CPUFreq.160=160MHz (WiFi)
+Edgebox-ESP-100.menu.CPUFreq.160.build.f_cpu=160000000L
+Edgebox-ESP-100.menu.CPUFreq.80=80MHz (WiFi)
+Edgebox-ESP-100.menu.CPUFreq.80.build.f_cpu=80000000L
+Edgebox-ESP-100.menu.CPUFreq.40=40MHz
+Edgebox-ESP-100.menu.CPUFreq.40.build.f_cpu=40000000L
+Edgebox-ESP-100.menu.CPUFreq.20=20MHz
+Edgebox-ESP-100.menu.CPUFreq.20.build.f_cpu=20000000L
+Edgebox-ESP-100.menu.CPUFreq.10=10MHz
+Edgebox-ESP-100.menu.CPUFreq.10.build.f_cpu=10000000L
+
+Edgebox-ESP-100.menu.UploadSpeed.921600=921600
+Edgebox-ESP-100.menu.UploadSpeed.921600.upload.speed=921600
+Edgebox-ESP-100.menu.UploadSpeed.115200=115200
+Edgebox-ESP-100.menu.UploadSpeed.115200.upload.speed=115200
+Edgebox-ESP-100.menu.UploadSpeed.256000.windows=256000
+Edgebox-ESP-100.menu.UploadSpeed.256000.upload.speed=256000
+Edgebox-ESP-100.menu.UploadSpeed.230400.windows.upload.speed=256000
+Edgebox-ESP-100.menu.UploadSpeed.230400=230400
+Edgebox-ESP-100.menu.UploadSpeed.230400.upload.speed=230400
+Edgebox-ESP-100.menu.UploadSpeed.460800.linux=460800
+Edgebox-ESP-100.menu.UploadSpeed.460800.macosx=460800
+Edgebox-ESP-100.menu.UploadSpeed.460800.upload.speed=460800
+Edgebox-ESP-100.menu.UploadSpeed.512000.windows=512000
+Edgebox-ESP-100.menu.UploadSpeed.512000.upload.speed=512000
+
+Edgebox-ESP-100.menu.DebugLevel.none=None
+Edgebox-ESP-100.menu.DebugLevel.none.build.code_debug=0
+Edgebox-ESP-100.menu.DebugLevel.error=Error
+Edgebox-ESP-100.menu.DebugLevel.error.build.code_debug=1
+Edgebox-ESP-100.menu.DebugLevel.warn=Warn
+Edgebox-ESP-100.menu.DebugLevel.warn.build.code_debug=2
+Edgebox-ESP-100.menu.DebugLevel.info=Info
+Edgebox-ESP-100.menu.DebugLevel.info.build.code_debug=3
+Edgebox-ESP-100.menu.DebugLevel.debug=Debug
+Edgebox-ESP-100.menu.DebugLevel.debug.build.code_debug=4
+Edgebox-ESP-100.menu.DebugLevel.verbose=Verbose
+Edgebox-ESP-100.menu.DebugLevel.verbose.build.code_debug=5
+
+Edgebox-ESP-100.menu.EraseFlash.none=Disabled
+Edgebox-ESP-100.menu.EraseFlash.none.upload.erase_cmd=
+Edgebox-ESP-100.menu.EraseFlash.all=Enabled
+Edgebox-ESP-100.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+crabik_slot_esp32_s3.name=Crabik Slot ESP32-S3
+
+crabik_slot_esp32_s3.bootloader.tool=esptool_py
+crabik_slot_esp32_s3.bootloader.tool.default=esptool_py
+
+crabik_slot_esp32_s3.upload.tool=esptool_py
+crabik_slot_esp32_s3.upload.tool.default=esptool_py
+crabik_slot_esp32_s3.upload.tool.network=esp_ota
+
+crabik_slot_esp32_s3.upload.maximum_size=1310720
+crabik_slot_esp32_s3.upload.maximum_data_size=327680
+crabik_slot_esp32_s3.upload.speed=921600
+crabik_slot_esp32_s3.upload.flags=
+crabik_slot_esp32_s3.upload.extra_flags=
+crabik_slot_esp32_s3.upload.use_1200bps_touch=false
+crabik_slot_esp32_s3.upload.wait_for_upload_port=false
+
+crabik_slot_esp32_s3.serial.disableDTR=false
+crabik_slot_esp32_s3.serial.disableRTS=false
+
+crabik_slot_esp32_s3.build.tarch=xtensa
+crabik_slot_esp32_s3.build.bootloader_addr=0x0
+crabik_slot_esp32_s3.build.target=esp32s3
+crabik_slot_esp32_s3.build.mcu=esp32s3
+crabik_slot_esp32_s3.build.core=esp32
+crabik_slot_esp32_s3.build.variant=crabik_slot_esp32_s3
+crabik_slot_esp32_s3.build.board=CRABIK_SLOT_ESP32_S3
+
+crabik_slot_esp32_s3.build.usb_mode=0
+crabik_slot_esp32_s3.build.cdc_on_boot=0
+crabik_slot_esp32_s3.build.msc_on_boot=0
+crabik_slot_esp32_s3.build.dfu_on_boot=0
+crabik_slot_esp32_s3.build.f_cpu=240000000L
+crabik_slot_esp32_s3.build.flash_size=8MB
+crabik_slot_esp32_s3.build.flash_freq=80m
+crabik_slot_esp32_s3.build.flash_mode=dio
+crabik_slot_esp32_s3.build.boot=qio
+crabik_slot_esp32_s3.build.partitions=default
+crabik_slot_esp32_s3.build.defines=
+crabik_slot_esp32_s3.build.memory_type=qio_qspi
+crabik_slot_esp32_s3.build.loop_core=
+crabik_slot_esp32_s3.build.event_core=
+
+## IDE 2.0 Seems to not update the value
+crabik_slot_esp32_s3.menu.JTAGAdapter.default=Disabled
+crabik_slot_esp32_s3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+crabik_slot_esp32_s3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+crabik_slot_esp32_s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+crabik_slot_esp32_s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+
+crabik_slot_esp32_s3.menu.LoopCore.1=Core 1
+crabik_slot_esp32_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+crabik_slot_esp32_s3.menu.LoopCore.0=Core 0
+crabik_slot_esp32_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+crabik_slot_esp32_s3.menu.EventsCore.1=Core 1
+crabik_slot_esp32_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+crabik_slot_esp32_s3.menu.EventsCore.0=Core 0
+crabik_slot_esp32_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+crabik_slot_esp32_s3.menu.CDCOnBoot.default=Enabled (Requires Hardware CDC and JTAG Mode)
+crabik_slot_esp32_s3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+crabik_slot_esp32_s3.menu.CDCOnBoot.discdc=Disabled
+crabik_slot_esp32_s3.menu.CDCOnBoot.discdc.build.cdc_on_boot=0
+
+crabik_slot_esp32_s3.menu.MSCOnBoot.default=Disabled
+crabik_slot_esp32_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+crabik_slot_esp32_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+crabik_slot_esp32_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+crabik_slot_esp32_s3.menu.USBMode.default=Hardware CDC and JTAG
+crabik_slot_esp32_s3.menu.USBMode.default.build.usb_mode=1
+crabik_slot_esp32_s3.menu.USBMode.default.build.cdc_on_boot=1
+crabik_slot_esp32_s3.menu.USBMode.usbotg=USB-OTG
+crabik_slot_esp32_s3.menu.USBMode.usbotg.build.usb_mode=0
+crabik_slot_esp32_s3.menu.USBMode.usbotg.build.cdc_on_boot=0
+
+crabik_slot_esp32_s3.menu.UploadMode.default=UART0 / Hardware CDC
+crabik_slot_esp32_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+crabik_slot_esp32_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+crabik_slot_esp32_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+crabik_slot_esp32_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+crabik_slot_esp32_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+crabik_slot_esp32_s3.menu.CPUFreq.240=240MHz (WiFi)
+crabik_slot_esp32_s3.menu.CPUFreq.240.build.f_cpu=240000000L
+crabik_slot_esp32_s3.menu.CPUFreq.160=160MHz (WiFi)
+crabik_slot_esp32_s3.menu.CPUFreq.160.build.f_cpu=160000000L
+crabik_slot_esp32_s3.menu.CPUFreq.80=80MHz (WiFi)
+crabik_slot_esp32_s3.menu.CPUFreq.80.build.f_cpu=80000000L
+
+crabik_slot_esp32_s3.menu.PartitionScheme.default=8M Flash (3MB APP/1.5MB FATFS)
+crabik_slot_esp32_s3.menu.PartitionScheme.default.build.partitions=default_8MB
+crabik_slot_esp32_s3.menu.PartitionScheme.default.upload.maximum_size=3342336
+crabik_slot_esp32_s3.menu.PartitionScheme.default_4MB=4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+crabik_slot_esp32_s3.menu.PartitionScheme.default_4MB.build.partitions=default
+crabik_slot_esp32_s3.menu.PartitionScheme.defaultffat=4MB with ffat (1.2MB APP/1.5MB FATFS)
+crabik_slot_esp32_s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+crabik_slot_esp32_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+crabik_slot_esp32_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+crabik_slot_esp32_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+crabik_slot_esp32_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+crabik_slot_esp32_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+crabik_slot_esp32_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+crabik_slot_esp32_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+crabik_slot_esp32_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+crabik_slot_esp32_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+crabik_slot_esp32_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+crabik_slot_esp32_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+crabik_slot_esp32_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+
+crabik_slot_esp32_s3.menu.UploadSpeed.921600=921600
+crabik_slot_esp32_s3.menu.UploadSpeed.921600.upload.speed=921600
+crabik_slot_esp32_s3.menu.UploadSpeed.115200=115200
+crabik_slot_esp32_s3.menu.UploadSpeed.115200.upload.speed=115200
+crabik_slot_esp32_s3.menu.UploadSpeed.256000.windows=256000
+crabik_slot_esp32_s3.menu.UploadSpeed.256000.upload.speed=256000
+crabik_slot_esp32_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+crabik_slot_esp32_s3.menu.UploadSpeed.230400=230400
+crabik_slot_esp32_s3.menu.UploadSpeed.230400.upload.speed=230400
+crabik_slot_esp32_s3.menu.UploadSpeed.460800.linux=460800
+crabik_slot_esp32_s3.menu.UploadSpeed.460800.macosx=460800
+crabik_slot_esp32_s3.menu.UploadSpeed.460800.upload.speed=460800
+crabik_slot_esp32_s3.menu.UploadSpeed.512000.windows=512000
+crabik_slot_esp32_s3.menu.UploadSpeed.512000.upload.speed=512000
+
+crabik_slot_esp32_s3.menu.DebugLevel.none=None
+crabik_slot_esp32_s3.menu.DebugLevel.none.build.code_debug=0
+crabik_slot_esp32_s3.menu.DebugLevel.error=Error
+crabik_slot_esp32_s3.menu.DebugLevel.error.build.code_debug=1
+crabik_slot_esp32_s3.menu.DebugLevel.warn=Warn
+crabik_slot_esp32_s3.menu.DebugLevel.warn.build.code_debug=2
+crabik_slot_esp32_s3.menu.DebugLevel.info=Info
+crabik_slot_esp32_s3.menu.DebugLevel.info.build.code_debug=3
+crabik_slot_esp32_s3.menu.DebugLevel.debug=Debug
+crabik_slot_esp32_s3.menu.DebugLevel.debug.build.code_debug=4
+crabik_slot_esp32_s3.menu.DebugLevel.verbose=Verbose
+crabik_slot_esp32_s3.menu.DebugLevel.verbose.build.code_debug=5
+
+crabik_slot_esp32_s3.menu.EraseFlash.none=Disabled
+crabik_slot_esp32_s3.menu.EraseFlash.none.upload.erase_cmd=
+crabik_slot_esp32_s3.menu.EraseFlash.all=Enabled
+crabik_slot_esp32_s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+
+nebulas3.name=Nebula S3
+
+nebulas3.bootloader.tool=esptool_py
+nebulas3.bootloader.tool.default=esptool_py
+
+nebulas3.upload.tool=esptool_py
+nebulas3.upload.tool.default=esptool_py
+nebulas3.upload.tool.network=esp_ota
+
+nebulas3.upload.maximum_size=1310720
+nebulas3.upload.maximum_data_size=327680
+nebulas3.upload.flags=
+nebulas3.upload.extra_flags=
+nebulas3.upload.use_1200bps_touch=false
+nebulas3.upload.wait_for_upload_port=false
+
+nebulas3.serial.disableDTR=false
+nebulas3.serial.disableRTS=false
+
+nebulas3.build.tarch=xtensa
+nebulas3.build.bootloader_addr=0x0
+nebulas3.build.target=esp32s3
+nebulas3.build.mcu=esp32s3
+nebulas3.build.core=esp32
+nebulas3.build.variant=Nebula_S3
+nebulas3.build.board=NEBULAS3
+
+nebulas3.build.usb_mode=1
+nebulas3.build.cdc_on_boot=0
+nebulas3.build.msc_on_boot=0
+nebulas3.build.dfu_on_boot=0
+nebulas3.build.f_cpu=240000000L
+nebulas3.build.flash_size=4MB
+nebulas3.build.flash_freq=80m
+nebulas3.build.flash_mode=dio
+nebulas3.build.boot=qio
+nebulas3.build.boot_freq=80m
+nebulas3.build.partitions=default
+nebulas3.build.defines=
+nebulas3.build.loop_core=
+nebulas3.build.event_core=
+nebulas3.build.psram_type=qspi
+nebulas3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+nebulas3.menu.JTAGAdapter.default=Disabled
+nebulas3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+nebulas3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+nebulas3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+nebulas3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+nebulas3.menu.JTAGAdapter.external=FTDI Adapter
+nebulas3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+nebulas3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+nebulas3.menu.JTAGAdapter.bridge=ESP USB Bridge
+nebulas3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+nebulas3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+nebulas3.menu.PSRAM.disabled=Disabled
+nebulas3.menu.PSRAM.disabled.build.defines=
+nebulas3.menu.PSRAM.disabled.build.psram_type=qspi
+nebulas3.menu.PSRAM.enabled=QSPI PSRAM
+nebulas3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+nebulas3.menu.PSRAM.enabled.build.psram_type=qspi
+nebulas3.menu.PSRAM.opi=OPI PSRAM
+nebulas3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+nebulas3.menu.PSRAM.opi.build.psram_type=opi
+
+nebulas3.menu.FlashMode.qio=QIO 80MHz
+nebulas3.menu.FlashMode.qio.build.flash_mode=dio
+nebulas3.menu.FlashMode.qio.build.boot=qio
+nebulas3.menu.FlashMode.qio.build.boot_freq=80m
+nebulas3.menu.FlashMode.qio.build.flash_freq=80m
+nebulas3.menu.FlashMode.qio120=QIO 120MHz
+nebulas3.menu.FlashMode.qio120.build.flash_mode=dio
+nebulas3.menu.FlashMode.qio120.build.boot=qio
+nebulas3.menu.FlashMode.qio120.build.boot_freq=120m
+nebulas3.menu.FlashMode.qio120.build.flash_freq=80m
+nebulas3.menu.FlashMode.dio=DIO 80MHz
+nebulas3.menu.FlashMode.dio.build.flash_mode=dio
+nebulas3.menu.FlashMode.dio.build.boot=dio
+nebulas3.menu.FlashMode.dio.build.boot_freq=80m
+nebulas3.menu.FlashMode.dio.build.flash_freq=80m
+nebulas3.menu.FlashMode.opi=OPI 80MHz
+nebulas3.menu.FlashMode.opi.build.flash_mode=dout
+nebulas3.menu.FlashMode.opi.build.boot=opi
+nebulas3.menu.FlashMode.opi.build.boot_freq=80m
+nebulas3.menu.FlashMode.opi.build.flash_freq=80m
+
+nebulas3.menu.FlashSize.4M=4MB (32Mb)
+nebulas3.menu.FlashSize.4M.build.flash_size=4MB
+nebulas3.menu.FlashSize.8M=8MB (64Mb)
+nebulas3.menu.FlashSize.8M.build.flash_size=8MB
+nebulas3.menu.FlashSize.16M=16MB (128Mb)
+nebulas3.menu.FlashSize.16M.build.flash_size=16MB
+
+nebulas3.menu.LoopCore.1=Core 1
+nebulas3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+nebulas3.menu.LoopCore.0=Core 0
+nebulas3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+nebulas3.menu.EventsCore.1=Core 1
+nebulas3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+nebulas3.menu.EventsCore.0=Core 0
+nebulas3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+nebulas3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+nebulas3.menu.USBMode.hwcdc.build.usb_mode=1
+nebulas3.menu.USBMode.default=USB-OTG (TinyUSB)
+nebulas3.menu.USBMode.default.build.usb_mode=0
+
+nebulas3.menu.CDCOnBoot.default= Enabled
+nebulas3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+nebulas3.menu.CDCOnBoot.cdc=Disabled
+nebulas3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+nebulas3.menu.MSCOnBoot.default=Disabled
+nebulas3.menu.MSCOnBoot.default.build.msc_on_boot=0
+nebulas3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+nebulas3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+nebulas3.menu.DFUOnBoot.default=Disabled
+nebulas3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+nebulas3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+nebulas3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+nebulas3.menu.UploadMode.default=UART0 / Hardware CDC
+nebulas3.menu.UploadMode.default.upload.use_1200bps_touch=false
+nebulas3.menu.UploadMode.default.upload.wait_for_upload_port=false
+nebulas3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+nebulas3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+nebulas3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+nebulas3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+nebulas3.menu.PartitionScheme.default.build.partitions=default
+nebulas3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+nebulas3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+nebulas3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+nebulas3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+nebulas3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+nebulas3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+nebulas3.menu.PartitionScheme.minimal.build.partitions=minimal
+nebulas3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+nebulas3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+nebulas3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+nebulas3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+nebulas3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+nebulas3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+nebulas3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+nebulas3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+nebulas3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+nebulas3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+nebulas3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+nebulas3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+nebulas3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+nebulas3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+nebulas3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+nebulas3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+nebulas3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+nebulas3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+nebulas3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+nebulas3.menu.PartitionScheme.fatflash.build.partitions=ffat
+nebulas3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+nebulas3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+nebulas3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+nebulas3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+nebulas3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+nebulas3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+nebulas3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+nebulas3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+nebulas3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+nebulas3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+nebulas3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+nebulas3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+nebulas3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+nebulas3.menu.CPUFreq.240=240MHz (WiFi)
+nebulas3.menu.CPUFreq.240.build.f_cpu=240000000L
+nebulas3.menu.CPUFreq.160=160MHz (WiFi)
+nebulas3.menu.CPUFreq.160.build.f_cpu=160000000L
+nebulas3.menu.CPUFreq.80=80MHz (WiFi)
+nebulas3.menu.CPUFreq.80.build.f_cpu=80000000L
+nebulas3.menu.CPUFreq.40=40MHz
+nebulas3.menu.CPUFreq.40.build.f_cpu=40000000L
+nebulas3.menu.CPUFreq.20=20MHz
+nebulas3.menu.CPUFreq.20.build.f_cpu=20000000L
+nebulas3.menu.CPUFreq.10=10MHz
+nebulas3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+nebulas3.menu.UploadSpeed.921600=921600
+nebulas3.menu.UploadSpeed.921600.upload.speed=921600
+nebulas3.menu.UploadSpeed.115200=115200
+nebulas3.menu.UploadSpeed.115200.upload.speed=115200
+nebulas3.menu.UploadSpeed.256000.windows=256000
+nebulas3.menu.UploadSpeed.256000.upload.speed=256000
+nebulas3.menu.UploadSpeed.230400.windows.upload.speed=256000
+nebulas3.menu.UploadSpeed.230400=230400
+nebulas3.menu.UploadSpeed.230400.upload.speed=230400
+nebulas3.menu.UploadSpeed.460800.linux=460800
+nebulas3.menu.UploadSpeed.460800.macosx=460800
+nebulas3.menu.UploadSpeed.460800.upload.speed=460800
+nebulas3.menu.UploadSpeed.512000.windows=512000
+nebulas3.menu.UploadSpeed.512000.upload.speed=512000
+
+nebulas3.menu.DebugLevel.none=None
+nebulas3.menu.DebugLevel.none.build.code_debug=0
+nebulas3.menu.DebugLevel.error=Error
+nebulas3.menu.DebugLevel.error.build.code_debug=1
+nebulas3.menu.DebugLevel.warn=Warn
+nebulas3.menu.DebugLevel.warn.build.code_debug=2
+nebulas3.menu.DebugLevel.info=Info
+nebulas3.menu.DebugLevel.info.build.code_debug=3
+nebulas3.menu.DebugLevel.debug=Debug
+nebulas3.menu.DebugLevel.debug.build.code_debug=4
+nebulas3.menu.DebugLevel.verbose=Verbose
+nebulas3.menu.DebugLevel.verbose.build.code_debug=5
+
+nebulas3.menu.EraseFlash.none=Disabled
+nebulas3.menu.EraseFlash.none.upload.erase_cmd=
+nebulas3.menu.EraseFlash.all=Enabled
+nebulas3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+lionbits3.name=Lion:Bit S3 STEM Dev Board
+
+lionbits3.bootloader.tool=esptool_py
+lionbits3.bootloader.tool.default=esptool_py
+
+lionbits3.upload.tool=esptool_py
+lionbits3.upload.tool.default=esptool_py
+lionbits3.upload.tool.network=esp_ota
+
+lionbits3.upload.maximum_size=1310720
+lionbits3.upload.maximum_data_size=327680
+lionbits3.upload.flags=
+lionbits3.upload.extra_flags=
+lionbits3.upload.use_1200bps_touch=false
+lionbits3.upload.wait_for_upload_port=false
+
+lionbits3.serial.disableDTR=false
+lionbits3.serial.disableRTS=false
+
+lionbits3.build.tarch=xtensa
+lionbits3.build.bootloader_addr=0x0
+lionbits3.build.target=esp32s3
+lionbits3.build.mcu=esp32s3
+lionbits3.build.core=esp32
+lionbits3.build.variant=lionbits3
+lionbits3.build.board=LIONBITS3_DEV
+
+
+lionbits3.build.usb_mode=1
+lionbits3.build.cdc_on_boot=0
+lionbits3.build.msc_on_boot=0
+lionbits3.build.dfu_on_boot=0
+lionbits3.build.f_cpu=240000000L
+lionbits3.build.flash_size=4MB
+lionbits3.build.flash_freq=80m
+lionbits3.build.flash_mode=dio
+lionbits3.build.boot=qio
+lionbits3.build.boot_freq=80m
+lionbits3.build.partitions=default
+lionbits3.build.defines=
+lionbits3.build.loop_core=
+lionbits3.build.event_core=
+lionbits3.build.psram_type=qspi
+lionbits3.build.memory_type={build.boot}_{build.psram_type}
+
+
+lionbits3.menu.JTAGAdapter.default=Disabled
+lionbits3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+lionbits3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+lionbits3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+lionbits3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+lionbits3.menu.JTAGAdapter.external=FTDI Adapter
+lionbits3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+lionbits3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+lionbits3.menu.JTAGAdapter.bridge=ESP USB Bridge
+lionbits3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+lionbits3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+lionbits3.menu.PSRAM.disabled=Disabled
+lionbits3.menu.PSRAM.disabled.build.defines=
+lionbits3.menu.PSRAM.disabled.build.psram_type=qspi
+lionbits3.menu.PSRAM.enabled=QSPI PSRAM
+lionbits3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+lionbits3.menu.PSRAM.enabled.build.psram_type=qspi
+lionbits3.menu.PSRAM.opi=OPI PSRAM
+lionbits3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+lionbits3.menu.PSRAM.opi.build.psram_type=opi
+
+lionbits3.menu.FlashMode.qio=QIO 80MHz
+lionbits3.menu.FlashMode.qio.build.flash_mode=dio
+lionbits3.menu.FlashMode.qio.build.boot=qio
+lionbits3.menu.FlashMode.qio.build.boot_freq=80m
+lionbits3.menu.FlashMode.qio.build.flash_freq=80m
+lionbits3.menu.FlashMode.qio120=QIO 120MHz
+lionbits3.menu.FlashMode.qio120.build.flash_mode=dio
+lionbits3.menu.FlashMode.qio120.build.boot=qio
+lionbits3.menu.FlashMode.qio120.build.boot_freq=120m
+lionbits3.menu.FlashMode.qio120.build.flash_freq=80m
+lionbits3.menu.FlashMode.dio=DIO 80MHz
+lionbits3.menu.FlashMode.dio.build.flash_mode=dio
+lionbits3.menu.FlashMode.dio.build.boot=dio
+lionbits3.menu.FlashMode.dio.build.boot_freq=80m
+lionbits3.menu.FlashMode.dio.build.flash_freq=80m
+lionbits3.menu.FlashMode.opi=OPI 80MHz
+lionbits3.menu.FlashMode.opi.build.flash_mode=dout
+lionbits3.menu.FlashMode.opi.build.boot=opi
+lionbits3.menu.FlashMode.opi.build.boot_freq=80m
+lionbits3.menu.FlashMode.opi.build.flash_freq=80m
+
+lionbits3.menu.FlashSize.4M=4MB (32Mb)
+lionbits3.menu.FlashSize.4M.build.flash_size=4MB
+lionbits3.menu.FlashSize.8M=8MB (64Mb)
+lionbits3.menu.FlashSize.8M.build.flash_size=8MB
+lionbits3.menu.FlashSize.16M=16MB (128Mb)
+lionbits3.menu.FlashSize.16M.build.flash_size=16MB
+#lionbits3.menu.FlashSize.32M=32MB (256Mb)
+#lionbits3.menu.FlashSize.32M.build.flash_size=32MB
+
+lionbits3.menu.LoopCore.1=Core 1
+lionbits3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+lionbits3.menu.LoopCore.0=Core 0
+lionbits3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+lionbits3.menu.EventsCore.1=Core 1
+lionbits3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+lionbits3.menu.EventsCore.0=Core 0
+lionbits3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+lionbits3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+lionbits3.menu.USBMode.hwcdc.build.usb_mode=1
+lionbits3.menu.USBMode.default=USB-OTG (TinyUSB)
+lionbits3.menu.USBMode.default.build.usb_mode=0
+
+lionbits3.menu.CDCOnBoot.default=Disabled
+lionbits3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+lionbits3.menu.CDCOnBoot.cdc=Enabled
+lionbits3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+lionbits3.menu.MSCOnBoot.default=Disabled
+lionbits3.menu.MSCOnBoot.default.build.msc_on_boot=0
+lionbits3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+lionbits3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+lionbits3.menu.DFUOnBoot.default=Disabled
+lionbits3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+lionbits3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+lionbits3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+lionbits3.menu.UploadMode.default=UART0 / Hardware CDC
+lionbits3.menu.UploadMode.default.upload.use_1200bps_touch=false
+lionbits3.menu.UploadMode.default.upload.wait_for_upload_port=false
+lionbits3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+lionbits3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+lionbits3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+lionbits3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+lionbits3.menu.PartitionScheme.default.build.partitions=default
+lionbits3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+lionbits3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+lionbits3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+lionbits3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+lionbits3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+lionbits3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+lionbits3.menu.PartitionScheme.minimal.build.partitions=minimal
+lionbits3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+lionbits3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+lionbits3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+lionbits3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+lionbits3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+lionbits3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+lionbits3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+lionbits3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+lionbits3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+lionbits3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+lionbits3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+lionbits3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+lionbits3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+lionbits3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+lionbits3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+lionbits3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+lionbits3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+lionbits3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+lionbits3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+lionbits3.menu.PartitionScheme.fatflash.build.partitions=ffat
+lionbits3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+lionbits3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+lionbits3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+lionbits3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+lionbits3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+lionbits3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+lionbits3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+lionbits3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+lionbits3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+lionbits3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+lionbits3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+lionbits3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+lionbits3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+lionbits3.menu.CPUFreq.240=240MHz (WiFi)
+lionbits3.menu.CPUFreq.240.build.f_cpu=240000000L
+lionbits3.menu.CPUFreq.160=160MHz (WiFi)
+lionbits3.menu.CPUFreq.160.build.f_cpu=160000000L
+lionbits3.menu.CPUFreq.80=80MHz (WiFi)
+lionbits3.menu.CPUFreq.80.build.f_cpu=80000000L
+lionbits3.menu.CPUFreq.40=40MHz
+lionbits3.menu.CPUFreq.40.build.f_cpu=40000000L
+lionbits3.menu.CPUFreq.20=20MHz
+lionbits3.menu.CPUFreq.20.build.f_cpu=20000000L
+lionbits3.menu.CPUFreq.10=10MHz
+lionbits3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+lionbits3.menu.UploadSpeed.921600=921600
+lionbits3.menu.UploadSpeed.921600.upload.speed=921600
+lionbits3.menu.UploadSpeed.115200=115200
+lionbits3.menu.UploadSpeed.115200.upload.speed=115200
+lionbits3.menu.UploadSpeed.256000.windows=256000
+lionbits3.menu.UploadSpeed.256000.upload.speed=256000
+lionbits3.menu.UploadSpeed.230400.windows.upload.speed=256000
+lionbits3.menu.UploadSpeed.230400=230400
+lionbits3.menu.UploadSpeed.230400.upload.speed=230400
+lionbits3.menu.UploadSpeed.460800.linux=460800
+lionbits3.menu.UploadSpeed.460800.macosx=460800
+lionbits3.menu.UploadSpeed.460800.upload.speed=460800
+lionbits3.menu.UploadSpeed.512000.windows=512000
+lionbits3.menu.UploadSpeed.512000.upload.speed=512000
+
+lionbits3.menu.DebugLevel.none=None
+lionbits3.menu.DebugLevel.none.build.code_debug=0
+lionbits3.menu.DebugLevel.error=Error
+lionbits3.menu.DebugLevel.error.build.code_debug=1
+lionbits3.menu.DebugLevel.warn=Warn
+lionbits3.menu.DebugLevel.warn.build.code_debug=2
+lionbits3.menu.DebugLevel.info=Info
+lionbits3.menu.DebugLevel.info.build.code_debug=3
+lionbits3.menu.DebugLevel.debug=Debug
+lionbits3.menu.DebugLevel.debug.build.code_debug=4
+lionbits3.menu.DebugLevel.verbose=Verbose
+lionbits3.menu.DebugLevel.verbose.build.code_debug=5
+
+lionbits3.menu.EraseFlash.none=Disabled
+lionbits3.menu.EraseFlash.none.upload.erase_cmd=
+lionbits3.menu.EraseFlash.all=Enabled
+lionbits3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+
+gen4-ESP32-S3R8n16.name=4D Systems gen4-ESP32 16MB Modules (ESP32-S3R8n16)
+
+gen4-ESP32-S3R8n16.bootloader.tool=esptool_py
+gen4-ESP32-S3R8n16.bootloader.tool.default=esptool_py
+
+gen4-ESP32-S3R8n16.upload.tool=esptool_py
+gen4-ESP32-S3R8n16.upload.tool.default=esptool_py
+gen4-ESP32-S3R8n16.upload.tool.network=esp_ota
+
+gen4-ESP32-S3R8n16.upload.maximum_size=1310720
+gen4-ESP32-S3R8n16.upload.maximum_data_size=327680
+gen4-ESP32-S3R8n16.upload.flags=
+gen4-ESP32-S3R8n16.upload.extra_flags=
+gen4-ESP32-S3R8n16.upload.use_1200bps_touch=false
+gen4-ESP32-S3R8n16.upload.wait_for_upload_port=false
+
+gen4-ESP32-S3R8n16.serial.disableDTR=false
+gen4-ESP32-S3R8n16.serial.disableRTS=false
+
+gen4-ESP32-S3R8n16.build.tarch=xtensa
+gen4-ESP32-S3R8n16.build.bootloader_addr=0x0
+gen4-ESP32-S3R8n16.build.target=esp32s3
+gen4-ESP32-S3R8n16.build.mcu=esp32s3
+gen4-ESP32-S3R8n16.build.core=esp32
+gen4-ESP32-S3R8n16.build.variant=esp32_s3r8n16
+gen4-ESP32-S3R8n16.build.board=ESP32_S3R8N16
+
+gen4-ESP32-S3R8n16.build.usb_mode=1
+gen4-ESP32-S3R8n16.build.cdc_on_boot=1
+gen4-ESP32-S3R8n16.build.msc_on_boot=0
+gen4-ESP32-S3R8n16.build.dfu_on_boot=0
+gen4-ESP32-S3R8n16.build.f_cpu=240000000L
+gen4-ESP32-S3R8n16.build.flash_size=16MB (128Mb)
+gen4-ESP32-S3R8n16.build.flash_freq=80m
+gen4-ESP32-S3R8n16.build.flash_mode=dio
+gen4-ESP32-S3R8n16.build.boot=qio
+gen4-ESP32-S3R8n16.build.boot_freq=80m
+gen4-ESP32-S3R8n16.build.partitions=default
+gen4-ESP32-S3R8n16.build.defines=-DBOARD_HAS_PSRAM
+gen4-ESP32-S3R8n16.build.loop_core=
+gen4-ESP32-S3R8n16.build.event_core=
+gen4-ESP32-S3R8n16.build.psram_type=opi
+gen4-ESP32-S3R8n16.build.memory_type={build.boot}_{build.psram_type}
+
+gen4-ESP32-S3R8n16.menu.PSRAM.opi=OPI PSRAM
+gen4-ESP32-S3R8n16.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+gen4-ESP32-S3R8n16.menu.PSRAM.opi.build.psram_type=opi
+
+gen4-ESP32-S3R8n16.menu.FlashMode.qio=QIO 80MHz
+gen4-ESP32-S3R8n16.menu.FlashMode.qio.build.flash_mode=dio
+gen4-ESP32-S3R8n16.menu.FlashMode.qio.build.boot=qio
+gen4-ESP32-S3R8n16.menu.FlashMode.qio.build.boot_freq=80m
+gen4-ESP32-S3R8n16.menu.FlashMode.qio.build.flash_freq=80m
+
+gen4-ESP32-S3R8n16.menu.FlashSize.16M=16MB (128Mb)
+gen4-ESP32-S3R8n16.menu.FlashSize.16M.build.flash_size=16MB
+
+gen4-ESP32-S3R8n16.menu.LoopCore.1=Core 1
+gen4-ESP32-S3R8n16.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+gen4-ESP32-S3R8n16.menu.LoopCore.0=Core 0
+gen4-ESP32-S3R8n16.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+gen4-ESP32-S3R8n16.menu.EventsCore.1=Core 1
+gen4-ESP32-S3R8n16.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+gen4-ESP32-S3R8n16.menu.EventsCore.0=Core 0
+gen4-ESP32-S3R8n16.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+gen4-ESP32-S3R8n16.menu.USBMode.default=Hardware CDC and JTAG
+gen4-ESP32-S3R8n16.menu.USBMode.default.build.usb_mode=1
+gen4-ESP32-S3R8n16.menu.USBMode.hwcdc=USB-OTG (TinyUSB)
+gen4-ESP32-S3R8n16.menu.USBMode.hwcdc.build.usb_mode=0
+
+gen4-ESP32-S3R8n16.menu.CDCOnBoot.cdc=Enabled
+gen4-ESP32-S3R8n16.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+gen4-ESP32-S3R8n16.menu.CDCOnBoot.default=Disabled
+gen4-ESP32-S3R8n16.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+gen4-ESP32-S3R8n16.menu.MSCOnBoot.default=Disabled
+gen4-ESP32-S3R8n16.menu.MSCOnBoot.default.build.msc_on_boot=0
+gen4-ESP32-S3R8n16.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+gen4-ESP32-S3R8n16.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+gen4-ESP32-S3R8n16.menu.DFUOnBoot.default=Disabled
+gen4-ESP32-S3R8n16.menu.DFUOnBoot.default.build.dfu_on_boot=0
+gen4-ESP32-S3R8n16.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+gen4-ESP32-S3R8n16.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+gen4-ESP32-S3R8n16.menu.UploadMode.default=UART0 / Hardware CDC
+gen4-ESP32-S3R8n16.menu.UploadMode.default.upload.use_1200bps_touch=false
+gen4-ESP32-S3R8n16.menu.UploadMode.default.upload.wait_for_upload_port=false
+gen4-ESP32-S3R8n16.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+gen4-ESP32-S3R8n16.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+gen4-ESP32-S3R8n16.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme1=Small App w/ OTA + Huge FS (2MB APP/2MB OTA/12MB SPIFFS)
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme1.build.custom_partitions=gen4esp32_2MBapp_2MBota_12MBspiffs
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme1.upload.maximum_size=2097152
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme2=Medium App w/ OTA + Large FS (4MB APP/4MB OTA/7MB SPIFFS)
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme2.build.custom_partitions=gen4esp32_4MBapp_4MBota_7MBspiffs
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme2.upload.maximum_size=4718592
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme3=Large App w/ OTA (8MB APP/8MB OTA)
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme3.build.custom_partitions=gen4esp32_8MBapp_8MBota
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme3.upload.maximum_size=8323072
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme4=Huge App (16MB APP)
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme4.build.custom_partitions=gen4esp32_16MBapp
+gen4-ESP32-S3R8n16.menu.PartitionScheme.gen4esp32scheme4.upload.maximum_size=16646144
+
+gen4-ESP32-S3R8n16.menu.CPUFreq.240=240MHz (WiFi)
+gen4-ESP32-S3R8n16.menu.CPUFreq.240.build.f_cpu=240000000L
+gen4-ESP32-S3R8n16.menu.CPUFreq.160=160MHz (WiFi)
+gen4-ESP32-S3R8n16.menu.CPUFreq.160.build.f_cpu=160000000L
+gen4-ESP32-S3R8n16.menu.CPUFreq.80=80MHz (WiFi)
+gen4-ESP32-S3R8n16.menu.CPUFreq.80.build.f_cpu=80000000L
+gen4-ESP32-S3R8n16.menu.CPUFreq.40=40MHz
+gen4-ESP32-S3R8n16.menu.CPUFreq.40.build.f_cpu=40000000L
+gen4-ESP32-S3R8n16.menu.CPUFreq.20=20MHz
+gen4-ESP32-S3R8n16.menu.CPUFreq.20.build.f_cpu=20000000L
+gen4-ESP32-S3R8n16.menu.CPUFreq.10=10MHz
+gen4-ESP32-S3R8n16.menu.CPUFreq.10.build.f_cpu=10000000L
+
+gen4-ESP32-S3R8n16.menu.UploadSpeed.921600=921600
+gen4-ESP32-S3R8n16.menu.UploadSpeed.921600.upload.speed=921600
+gen4-ESP32-S3R8n16.menu.UploadSpeed.115200=115200
+gen4-ESP32-S3R8n16.menu.UploadSpeed.115200.upload.speed=115200
+gen4-ESP32-S3R8n16.menu.UploadSpeed.256000.windows=256000
+gen4-ESP32-S3R8n16.menu.UploadSpeed.256000.upload.speed=256000
+gen4-ESP32-S3R8n16.menu.UploadSpeed.230400.windows.upload.speed=256000
+gen4-ESP32-S3R8n16.menu.UploadSpeed.230400=230400
+gen4-ESP32-S3R8n16.menu.UploadSpeed.230400.upload.speed=230400
+gen4-ESP32-S3R8n16.menu.UploadSpeed.460800.linux=460800
+gen4-ESP32-S3R8n16.menu.UploadSpeed.460800.macosx=460800
+gen4-ESP32-S3R8n16.menu.UploadSpeed.460800.upload.speed=460800
+gen4-ESP32-S3R8n16.menu.UploadSpeed.512000.windows=512000
+gen4-ESP32-S3R8n16.menu.UploadSpeed.512000.upload.speed=512000
+
+gen4-ESP32-S3R8n16.menu.DebugLevel.none=None
+gen4-ESP32-S3R8n16.menu.DebugLevel.none.build.code_debug=0
+gen4-ESP32-S3R8n16.menu.DebugLevel.error=Error
+gen4-ESP32-S3R8n16.menu.DebugLevel.error.build.code_debug=1
+gen4-ESP32-S3R8n16.menu.DebugLevel.warn=Warn
+gen4-ESP32-S3R8n16.menu.DebugLevel.warn.build.code_debug=2
+gen4-ESP32-S3R8n16.menu.DebugLevel.info=Info
+gen4-ESP32-S3R8n16.menu.DebugLevel.info.build.code_debug=3
+gen4-ESP32-S3R8n16.menu.DebugLevel.debug=Debug
+gen4-ESP32-S3R8n16.menu.DebugLevel.debug.build.code_debug=4
+gen4-ESP32-S3R8n16.menu.DebugLevel.verbose=Verbose
+gen4-ESP32-S3R8n16.menu.DebugLevel.verbose.build.code_debug=5
+
+gen4-ESP32-S3R8n16.menu.EraseFlash.none=Disabled
+gen4-ESP32-S3R8n16.menu.EraseFlash.none.upload.erase_cmd=
+gen4-ESP32-S3R8n16.menu.EraseFlash.all=Enabled
+gen4-ESP32-S3R8n16.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# Namino Rosso
+
+namino_rosso.name=Namino Rosso
+
+namino_rosso.bootloader.tool=esptool_py
+namino_rosso.bootloader.tool.default=esptool_py
+
+namino_rosso.upload.tool=esptool_py
+namino_rosso.upload.tool.default=esptool_py
+namino_rosso.upload.tool.network=esp_ota
+
+namino_rosso.upload.maximum_size=1310720
+namino_rosso.upload.maximum_data_size=327680
+namino_rosso.upload.flags=
+namino_rosso.upload.extra_flags=
+namino_rosso.upload.use_1200bps_touch=true
+namino_rosso.upload.wait_for_upload_port=true
+
+namino_rosso.serial.disableDTR=false
+namino_rosso.serial.disableRTS=false
+
+namino_rosso.build.tarch=xtensa
+namino_rosso.build.bootloader_addr=0x0
+namino_rosso.build.target=esp32s3
+namino_rosso.build.mcu=esp32s3
+namino_rosso.build.core=esp32
+namino_rosso.build.variant=namino_rosso
+namino_rosso.build.board=NAMINO_ROSSO
+
+namino_rosso.build.usb_mode=0
+namino_rosso.build.cdc_on_boot=1
+namino_rosso.build.msc_on_boot=0
+namino_rosso.build.dfu_on_boot=0
+namino_rosso.build.f_cpu=240000000L
+namino_rosso.build.flash_size=4MB
+namino_rosso.build.flash_freq=80m
+namino_rosso.build.flash_mode=dio
+namino_rosso.build.boot=qio
+namino_rosso.build.partitions=default
+namino_rosso.build.defines=
+namino_rosso.build.loop_core=
+namino_rosso.build.event_core=
+namino_rosso.build.flash_type=qio
+namino_rosso.build.psram_type=qspi
+namino_rosso.build.memory_type={build.flash_type}_{build.psram_type}
+
+namino_rosso.menu.LoopCore.1=Core 1
+namino_rosso.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+namino_rosso.menu.LoopCore.0=Core 0
+namino_rosso.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+namino_rosso.menu.EventsCore.1=Core 1
+namino_rosso.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+namino_rosso.menu.EventsCore.0=Core 0
+namino_rosso.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+namino_rosso.menu.USBMode.default=USB-OTG (TinyUSB)
+namino_rosso.menu.USBMode.default.build.usb_mode=0
+namino_rosso.menu.USBMode.hwcdc=Hardware CDC and JTAG
+namino_rosso.menu.USBMode.hwcdc.build.usb_mode=1
+
+namino_rosso.menu.CDCOnBoot.cdc=Enabled
+namino_rosso.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+namino_rosso.menu.CDCOnBoot.default=Disabled
+namino_rosso.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+namino_rosso.menu.MSCOnBoot.default=Disabled
+namino_rosso.menu.MSCOnBoot.default.build.msc_on_boot=0
+namino_rosso.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+namino_rosso.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+namino_rosso.menu.DFUOnBoot.default=Disabled
+namino_rosso.menu.DFUOnBoot.default.build.dfu_on_boot=0
+namino_rosso.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+namino_rosso.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+namino_rosso.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+namino_rosso.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+namino_rosso.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+namino_rosso.menu.UploadMode.default=UART0 / Hardware CDC
+namino_rosso.menu.UploadMode.default.upload.use_1200bps_touch=false
+namino_rosso.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+namino_rosso.menu.PSRAM.disabled=Disabled
+namino_rosso.menu.PSRAM.disabled.build.defines=
+namino_rosso.menu.PSRAM.disabled.build.psram_type=qspi
+namino_rosso.menu.PSRAM.enabled=QSPI PSRAM
+namino_rosso.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+namino_rosso.menu.PSRAM.enabled.build.psram_type=qspi
+namino_rosso.menu.PSRAM.opi=OPI PSRAM
+namino_rosso.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+namino_rosso.menu.PSRAM.opi.build.psram_type=opi
+
+namino_rosso.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+namino_rosso.menu.PartitionScheme.default.build.partitions=default
+namino_rosso.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+namino_rosso.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+namino_rosso.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+namino_rosso.menu.PartitionScheme.minimal.build.partitions=minimal
+namino_rosso.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+namino_rosso.menu.PartitionScheme.no_ota.build.partitions=no_ota
+namino_rosso.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+namino_rosso.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+namino_rosso.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+namino_rosso.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+namino_rosso.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+namino_rosso.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+namino_rosso.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+namino_rosso.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+namino_rosso.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+namino_rosso.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+namino_rosso.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+namino_rosso.menu.PartitionScheme.huge_app.build.partitions=huge_app
+namino_rosso.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+namino_rosso.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+namino_rosso.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+namino_rosso.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+namino_rosso.menu.CPUFreq.240=240MHz (WiFi)
+namino_rosso.menu.CPUFreq.240.build.f_cpu=240000000L
+namino_rosso.menu.CPUFreq.160=160MHz (WiFi)
+namino_rosso.menu.CPUFreq.160.build.f_cpu=160000000L
+namino_rosso.menu.CPUFreq.80=80MHz (WiFi)
+namino_rosso.menu.CPUFreq.80.build.f_cpu=80000000L
+namino_rosso.menu.CPUFreq.40=40MHz
+namino_rosso.menu.CPUFreq.40.build.f_cpu=40000000L
+namino_rosso.menu.CPUFreq.20=20MHz
+namino_rosso.menu.CPUFreq.20.build.f_cpu=20000000L
+namino_rosso.menu.CPUFreq.10=10MHz
+namino_rosso.menu.CPUFreq.10.build.f_cpu=10000000L
+
+namino_rosso.menu.FlashMode.qio=QIO 80MHz
+namino_rosso.menu.FlashMode.qio.build.flash_mode=dio
+namino_rosso.menu.FlashMode.qio.build.boot=qio
+namino_rosso.menu.FlashMode.qio.build.boot_freq=80m
+namino_rosso.menu.FlashMode.qio.build.flash_freq=80m
+namino_rosso.menu.FlashMode.qio120=QIO 120MHz
+namino_rosso.menu.FlashMode.qio120.build.flash_mode=dio
+namino_rosso.menu.FlashMode.qio120.build.boot=qio
+namino_rosso.menu.FlashMode.qio120.build.boot_freq=120m
+namino_rosso.menu.FlashMode.qio120.build.flash_freq=80m
+namino_rosso.menu.FlashMode.dio=DIO 80MHz
+namino_rosso.menu.FlashMode.dio.build.flash_mode=dio
+namino_rosso.menu.FlashMode.dio.build.boot=dio
+namino_rosso.menu.FlashMode.dio.build.boot_freq=80m
+namino_rosso.menu.FlashMode.dio.build.flash_freq=80m
+namino_rosso.menu.FlashMode.opi=OPI 80MHz
+namino_rosso.menu.FlashMode.opi.build.flash_mode=dout
+namino_rosso.menu.FlashMode.opi.build.boot=opi
+namino_rosso.menu.FlashMode.opi.build.boot_freq=80m
+namino_rosso.menu.FlashMode.opi.build.flash_freq=80m
+
+namino_rosso.menu.FlashSize.4M=4MB (32Mb)
+namino_rosso.menu.FlashSize.4M.build.flash_size=4MB
+
+namino_rosso.menu.UploadSpeed.921600=921600
+namino_rosso.menu.UploadSpeed.921600.upload.speed=921600
+namino_rosso.menu.UploadSpeed.115200=115200
+namino_rosso.menu.UploadSpeed.115200.upload.speed=115200
+namino_rosso.menu.UploadSpeed.256000.windows=256000
+namino_rosso.menu.UploadSpeed.256000.upload.speed=256000
+namino_rosso.menu.UploadSpeed.230400.windows.upload.speed=256000
+namino_rosso.menu.UploadSpeed.230400=230400
+namino_rosso.menu.UploadSpeed.230400.upload.speed=230400
+namino_rosso.menu.UploadSpeed.460800.linux=460800
+namino_rosso.menu.UploadSpeed.460800.macosx=460800
+namino_rosso.menu.UploadSpeed.460800.upload.speed=460800
+namino_rosso.menu.UploadSpeed.512000.windows=512000
+namino_rosso.menu.UploadSpeed.512000.upload.speed=512000
+
+namino_rosso.menu.DebugLevel.none=None
+namino_rosso.menu.DebugLevel.none.build.code_debug=0
+namino_rosso.menu.DebugLevel.error=Error
+namino_rosso.menu.DebugLevel.error.build.code_debug=1
+namino_rosso.menu.DebugLevel.warn=Warn
+namino_rosso.menu.DebugLevel.warn.build.code_debug=2
+namino_rosso.menu.DebugLevel.info=Info
+namino_rosso.menu.DebugLevel.info.build.code_debug=3
+namino_rosso.menu.DebugLevel.debug=Debug
+namino_rosso.menu.DebugLevel.debug.build.code_debug=4
+namino_rosso.menu.DebugLevel.verbose=Verbose
+namino_rosso.menu.DebugLevel.verbose.build.code_debug=5
+
+namino_rosso.menu.EraseFlash.none=Disabled
+namino_rosso.menu.EraseFlash.none.upload.erase_cmd=
+namino_rosso.menu.EraseFlash.all=Enabled
+namino_rosso.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# Namino Arancio
+
+namino_arancio.name=Namino Arancio
+
+namino_arancio.bootloader.tool=esptool_py
+namino_arancio.bootloader.tool.default=esptool_py
+
+namino_arancio.upload.tool=esptool_py
+namino_arancio.upload.tool.default=esptool_py
+namino_arancio.upload.tool.network=esp_ota
+
+namino_arancio.upload.maximum_size=1310720
+namino_arancio.upload.maximum_data_size=327680
+namino_arancio.upload.flags=
+namino_arancio.upload.extra_flags=
+namino_arancio.upload.use_1200bps_touch=true
+namino_arancio.upload.wait_for_upload_port=true
+
+namino_arancio.serial.disableDTR=false
+namino_arancio.serial.disableRTS=false
+
+namino_arancio.build.tarch=xtensa
+namino_arancio.build.bootloader_addr=0x0
+namino_arancio.build.target=esp32s3
+namino_arancio.build.mcu=esp32s3
+namino_arancio.build.core=esp32
+namino_arancio.build.variant=namino_arancio
+namino_arancio.build.board=NAMINO_ARANCIO
+
+namino_arancio.build.usb_mode=0
+namino_arancio.build.cdc_on_boot=1
+namino_arancio.build.msc_on_boot=0
+namino_arancio.build.dfu_on_boot=0
+namino_arancio.build.f_cpu=240000000L
+namino_arancio.build.flash_size=4MB
+namino_arancio.build.flash_freq=80m
+namino_arancio.build.flash_mode=dio
+namino_arancio.build.boot=qio
+namino_arancio.build.partitions=default
+namino_arancio.build.defines=
+namino_arancio.build.loop_core=
+namino_arancio.build.event_core=
+namino_arancio.build.flash_type=qio
+namino_arancio.build.psram_type=qspi
+namino_arancio.build.memory_type={build.flash_type}_{build.psram_type}
+
+namino_arancio.menu.LoopCore.1=Core 1
+namino_arancio.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+namino_arancio.menu.LoopCore.0=Core 0
+namino_arancio.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+namino_arancio.menu.EventsCore.1=Core 1
+namino_arancio.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+namino_arancio.menu.EventsCore.0=Core 0
+namino_arancio.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+namino_arancio.menu.USBMode.default=USB-OTG (TinyUSB)
+namino_arancio.menu.USBMode.default.build.usb_mode=0
+namino_arancio.menu.USBMode.hwcdc=Hardware CDC and JTAG
+namino_arancio.menu.USBMode.hwcdc.build.usb_mode=1
+
+namino_arancio.menu.CDCOnBoot.cdc=Enabled
+namino_arancio.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+namino_arancio.menu.CDCOnBoot.default=Disabled
+namino_arancio.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+namino_arancio.menu.MSCOnBoot.default=Disabled
+namino_arancio.menu.MSCOnBoot.default.build.msc_on_boot=0
+namino_arancio.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+namino_arancio.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+namino_arancio.menu.DFUOnBoot.default=Disabled
+namino_arancio.menu.DFUOnBoot.default.build.dfu_on_boot=0
+namino_arancio.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+namino_arancio.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+namino_arancio.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+namino_arancio.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+namino_arancio.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+namino_arancio.menu.UploadMode.default=UART0 / Hardware CDC
+namino_arancio.menu.UploadMode.default.upload.use_1200bps_touch=false
+namino_arancio.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+namino_arancio.menu.PSRAM.disabled=Disabled
+namino_arancio.menu.PSRAM.disabled.build.defines=
+namino_arancio.menu.PSRAM.disabled.build.psram_type=qspi
+namino_arancio.menu.PSRAM.enabled=QSPI PSRAM
+namino_arancio.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+namino_arancio.menu.PSRAM.enabled.build.psram_type=qspi
+namino_arancio.menu.PSRAM.opi=OPI PSRAM
+namino_arancio.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+namino_arancio.menu.PSRAM.opi.build.psram_type=opi
+
+namino_arancio.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+namino_arancio.menu.PartitionScheme.default.build.partitions=default
+namino_arancio.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+namino_arancio.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+namino_arancio.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+namino_arancio.menu.PartitionScheme.minimal.build.partitions=minimal
+namino_arancio.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+namino_arancio.menu.PartitionScheme.no_ota.build.partitions=no_ota
+namino_arancio.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+namino_arancio.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+namino_arancio.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+namino_arancio.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+namino_arancio.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+namino_arancio.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+namino_arancio.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+namino_arancio.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+namino_arancio.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+namino_arancio.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+namino_arancio.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+namino_arancio.menu.PartitionScheme.huge_app.build.partitions=huge_app
+namino_arancio.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+namino_arancio.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+namino_arancio.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+namino_arancio.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+namino_arancio.menu.CPUFreq.240=240MHz (WiFi)
+namino_arancio.menu.CPUFreq.240.build.f_cpu=240000000L
+namino_arancio.menu.CPUFreq.160=160MHz (WiFi)
+namino_arancio.menu.CPUFreq.160.build.f_cpu=160000000L
+namino_arancio.menu.CPUFreq.80=80MHz (WiFi)
+namino_arancio.menu.CPUFreq.80.build.f_cpu=80000000L
+namino_arancio.menu.CPUFreq.40=40MHz
+namino_arancio.menu.CPUFreq.40.build.f_cpu=40000000L
+namino_arancio.menu.CPUFreq.20=20MHz
+namino_arancio.menu.CPUFreq.20.build.f_cpu=20000000L
+namino_arancio.menu.CPUFreq.10=10MHz
+namino_arancio.menu.CPUFreq.10.build.f_cpu=10000000L
+
+namino_arancio.menu.FlashMode.qio=QIO 80MHz
+namino_arancio.menu.FlashMode.qio.build.flash_mode=dio
+namino_arancio.menu.FlashMode.qio.build.boot=qio
+namino_arancio.menu.FlashMode.qio.build.boot_freq=80m
+namino_arancio.menu.FlashMode.qio.build.flash_freq=80m
+namino_arancio.menu.FlashMode.qio120=QIO 120MHz
+namino_arancio.menu.FlashMode.qio120.build.flash_mode=dio
+namino_arancio.menu.FlashMode.qio120.build.boot=qio
+namino_arancio.menu.FlashMode.qio120.build.boot_freq=120m
+namino_arancio.menu.FlashMode.qio120.build.flash_freq=80m
+namino_arancio.menu.FlashMode.dio=DIO 80MHz
+namino_arancio.menu.FlashMode.dio.build.flash_mode=dio
+namino_arancio.menu.FlashMode.dio.build.boot=dio
+namino_arancio.menu.FlashMode.dio.build.boot_freq=80m
+namino_arancio.menu.FlashMode.dio.build.flash_freq=80m
+namino_arancio.menu.FlashMode.opi=OPI 80MHz
+namino_arancio.menu.FlashMode.opi.build.flash_mode=dout
+namino_arancio.menu.FlashMode.opi.build.boot=opi
+namino_arancio.menu.FlashMode.opi.build.boot_freq=80m
+namino_arancio.menu.FlashMode.opi.build.flash_freq=80m
+
+namino_arancio.menu.FlashSize.4M=4MB (32Mb)
+namino_arancio.menu.FlashSize.4M.build.flash_size=4MB
+
+namino_arancio.menu.UploadSpeed.921600=921600
+namino_arancio.menu.UploadSpeed.921600.upload.speed=921600
+namino_arancio.menu.UploadSpeed.115200=115200
+namino_arancio.menu.UploadSpeed.115200.upload.speed=115200
+namino_arancio.menu.UploadSpeed.256000.windows=256000
+namino_arancio.menu.UploadSpeed.256000.upload.speed=256000
+namino_arancio.menu.UploadSpeed.230400.windows.upload.speed=256000
+namino_arancio.menu.UploadSpeed.230400=230400
+namino_arancio.menu.UploadSpeed.230400.upload.speed=230400
+namino_arancio.menu.UploadSpeed.460800.linux=460800
+namino_arancio.menu.UploadSpeed.460800.macosx=460800
+namino_arancio.menu.UploadSpeed.460800.upload.speed=460800
+namino_arancio.menu.UploadSpeed.512000.windows=512000
+namino_arancio.menu.UploadSpeed.512000.upload.speed=512000
+
+namino_arancio.menu.DebugLevel.none=None
+namino_arancio.menu.DebugLevel.none.build.code_debug=0
+namino_arancio.menu.DebugLevel.error=Error
+namino_arancio.menu.DebugLevel.error.build.code_debug=1
+namino_arancio.menu.DebugLevel.warn=Warn
+namino_arancio.menu.DebugLevel.warn.build.code_debug=2
+namino_arancio.menu.DebugLevel.info=Info
+namino_arancio.menu.DebugLevel.info.build.code_debug=3
+namino_arancio.menu.DebugLevel.debug=Debug
+namino_arancio.menu.DebugLevel.debug.build.code_debug=4
+namino_arancio.menu.DebugLevel.verbose=Verbose
+namino_arancio.menu.DebugLevel.verbose.build.code_debug=5
+
+namino_arancio.menu.EraseFlash.none=Disabled
+namino_arancio.menu.EraseFlash.none.upload.erase_cmd=
+namino_arancio.menu.EraseFlash.all=Enabled
+namino_arancio.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# Namino Bianco
+
+namino_bianco.name=Namino Bianco
+
+namino_bianco.bootloader.tool=esptool_py
+namino_bianco.bootloader.tool.default=esptool_py
+
+namino_bianco.upload.tool=esptool_py
+namino_bianco.upload.tool.default=esptool_py
+namino_bianco.upload.tool.network=esp_ota
+
+namino_bianco.upload.maximum_size=1310720
+namino_bianco.upload.maximum_data_size=327680
+namino_bianco.upload.flags=
+namino_bianco.upload.extra_flags=
+namino_bianco.upload.use_1200bps_touch=true
+namino_bianco.upload.wait_for_upload_port=true
+
+namino_bianco.serial.disableDTR=false
+namino_bianco.serial.disableRTS=false
+
+namino_bianco.build.tarch=xtensa
+namino_bianco.build.bootloader_addr=0x0
+namino_bianco.build.target=esp32s3
+namino_bianco.build.mcu=esp32s3
+namino_bianco.build.core=esp32
+namino_bianco.build.variant=namino_bianco
+namino_bianco.build.board=NAMINO_BIANCO
+
+namino_bianco.build.usb_mode=0
+namino_bianco.build.cdc_on_boot=1
+namino_bianco.build.msc_on_boot=0
+namino_bianco.build.dfu_on_boot=0
+namino_bianco.build.f_cpu=240000000L
+namino_bianco.build.flash_size=4MB
+namino_bianco.build.flash_freq=80m
+namino_bianco.build.flash_mode=dio
+namino_bianco.build.boot=qio
+namino_bianco.build.partitions=default
+namino_bianco.build.defines=
+namino_bianco.build.loop_core=
+namino_bianco.build.event_core=
+namino_bianco.build.flash_type=qio
+namino_bianco.build.psram_type=qspi
+namino_bianco.build.memory_type={build.flash_type}_{build.psram_type}
+
+namino_bianco.menu.LoopCore.1=Core 1
+namino_bianco.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+namino_bianco.menu.LoopCore.0=Core 0
+namino_bianco.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+namino_bianco.menu.EventsCore.1=Core 1
+namino_bianco.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+namino_bianco.menu.EventsCore.0=Core 0
+namino_bianco.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+namino_bianco.menu.USBMode.default=USB-OTG (TinyUSB)
+namino_bianco.menu.USBMode.default.build.usb_mode=0
+namino_bianco.menu.USBMode.hwcdc=Hardware CDC and JTAG
+namino_bianco.menu.USBMode.hwcdc.build.usb_mode=1
+
+namino_bianco.menu.CDCOnBoot.cdc=Enabled
+namino_bianco.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+namino_bianco.menu.CDCOnBoot.default=Disabled
+namino_bianco.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+namino_bianco.menu.MSCOnBoot.default=Disabled
+namino_bianco.menu.MSCOnBoot.default.build.msc_on_boot=0
+namino_bianco.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+namino_bianco.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+namino_bianco.menu.DFUOnBoot.default=Disabled
+namino_bianco.menu.DFUOnBoot.default.build.dfu_on_boot=0
+namino_bianco.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+namino_bianco.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+namino_bianco.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+namino_bianco.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+namino_bianco.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+namino_bianco.menu.UploadMode.default=UART0 / Hardware CDC
+namino_bianco.menu.UploadMode.default.upload.use_1200bps_touch=false
+namino_bianco.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+namino_bianco.menu.PSRAM.disabled=Disabled
+namino_bianco.menu.PSRAM.disabled.build.defines=
+namino_bianco.menu.PSRAM.disabled.build.psram_type=qspi
+namino_bianco.menu.PSRAM.enabled=QSPI PSRAM
+namino_bianco.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+namino_bianco.menu.PSRAM.enabled.build.psram_type=qspi
+namino_bianco.menu.PSRAM.opi=OPI PSRAM
+namino_bianco.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+namino_bianco.menu.PSRAM.opi.build.psram_type=opi
+
+namino_bianco.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+namino_bianco.menu.PartitionScheme.default.build.partitions=default
+namino_bianco.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+namino_bianco.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+namino_bianco.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+namino_bianco.menu.PartitionScheme.minimal.build.partitions=minimal
+namino_bianco.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+namino_bianco.menu.PartitionScheme.no_ota.build.partitions=no_ota
+namino_bianco.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+namino_bianco.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+namino_bianco.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+namino_bianco.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+namino_bianco.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+namino_bianco.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+namino_bianco.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+namino_bianco.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+namino_bianco.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+namino_bianco.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+namino_bianco.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+namino_bianco.menu.PartitionScheme.huge_app.build.partitions=huge_app
+namino_bianco.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+namino_bianco.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+namino_bianco.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+namino_bianco.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+namino_bianco.menu.CPUFreq.240=240MHz (WiFi)
+namino_bianco.menu.CPUFreq.240.build.f_cpu=240000000L
+namino_bianco.menu.CPUFreq.160=160MHz (WiFi)
+namino_bianco.menu.CPUFreq.160.build.f_cpu=160000000L
+namino_bianco.menu.CPUFreq.80=80MHz (WiFi)
+namino_bianco.menu.CPUFreq.80.build.f_cpu=80000000L
+namino_bianco.menu.CPUFreq.40=40MHz
+namino_bianco.menu.CPUFreq.40.build.f_cpu=40000000L
+namino_bianco.menu.CPUFreq.20=20MHz
+namino_bianco.menu.CPUFreq.20.build.f_cpu=20000000L
+namino_bianco.menu.CPUFreq.10=10MHz
+namino_bianco.menu.CPUFreq.10.build.f_cpu=10000000L
+
+namino_bianco.menu.FlashMode.qio=QIO 80MHz
+namino_bianco.menu.FlashMode.qio.build.flash_mode=dio
+namino_bianco.menu.FlashMode.qio.build.boot=qio
+namino_bianco.menu.FlashMode.qio.build.boot_freq=80m
+namino_bianco.menu.FlashMode.qio.build.flash_freq=80m
+namino_bianco.menu.FlashMode.qio120=QIO 120MHz
+namino_bianco.menu.FlashMode.qio120.build.flash_mode=dio
+namino_bianco.menu.FlashMode.qio120.build.boot=qio
+namino_bianco.menu.FlashMode.qio120.build.boot_freq=120m
+namino_bianco.menu.FlashMode.qio120.build.flash_freq=80m
+namino_bianco.menu.FlashMode.dio=DIO 80MHz
+namino_bianco.menu.FlashMode.dio.build.flash_mode=dio
+namino_bianco.menu.FlashMode.dio.build.boot=dio
+namino_bianco.menu.FlashMode.dio.build.boot_freq=80m
+namino_bianco.menu.FlashMode.dio.build.flash_freq=80m
+namino_bianco.menu.FlashMode.opi=OPI 80MHz
+namino_bianco.menu.FlashMode.opi.build.flash_mode=dout
+namino_bianco.menu.FlashMode.opi.build.boot=opi
+namino_bianco.menu.FlashMode.opi.build.boot_freq=80m
+namino_bianco.menu.FlashMode.opi.build.flash_freq=80m
+
+namino_bianco.menu.FlashSize.4M=4MB (32Mb)
+namino_bianco.menu.FlashSize.4M.build.flash_size=4MB
+
+namino_bianco.menu.UploadSpeed.921600=921600
+namino_bianco.menu.UploadSpeed.921600.upload.speed=921600
+namino_bianco.menu.UploadSpeed.115200=115200
+namino_bianco.menu.UploadSpeed.115200.upload.speed=115200
+namino_bianco.menu.UploadSpeed.256000.windows=256000
+namino_bianco.menu.UploadSpeed.256000.upload.speed=256000
+namino_bianco.menu.UploadSpeed.230400.windows.upload.speed=256000
+namino_bianco.menu.UploadSpeed.230400=230400
+namino_bianco.menu.UploadSpeed.230400.upload.speed=230400
+namino_bianco.menu.UploadSpeed.460800.linux=460800
+namino_bianco.menu.UploadSpeed.460800.macosx=460800
+namino_bianco.menu.UploadSpeed.460800.upload.speed=460800
+namino_bianco.menu.UploadSpeed.512000.windows=512000
+namino_bianco.menu.UploadSpeed.512000.upload.speed=512000
+
+namino_bianco.menu.DebugLevel.none=None
+namino_bianco.menu.DebugLevel.none.build.code_debug=0
+namino_bianco.menu.DebugLevel.error=Error
+namino_bianco.menu.DebugLevel.error.build.code_debug=1
+namino_bianco.menu.DebugLevel.warn=Warn
+namino_bianco.menu.DebugLevel.warn.build.code_debug=2
+namino_bianco.menu.DebugLevel.info=Info
+namino_bianco.menu.DebugLevel.info.build.code_debug=3
+namino_bianco.menu.DebugLevel.debug=Debug
+namino_bianco.menu.DebugLevel.debug.build.code_debug=4
+namino_bianco.menu.DebugLevel.verbose=Verbose
+namino_bianco.menu.DebugLevel.verbose.build.code_debug=5
+
+namino_bianco.menu.EraseFlash.none=Disabled
+namino_bianco.menu.EraseFlash.none.upload.erase_cmd=
+namino_bianco.menu.EraseFlash.all=Enabled
+namino_bianco.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# IOXESP32, IOXESP32U
+
+ioxesp32.name=IOXESP32
+
+ioxesp32.bootloader.tool=esptool_py
+ioxesp32.bootloader.tool.default=esptool_py
+
+ioxesp32.upload.tool=esptool_py
+ioxesp32.upload.tool.default=esptool_py
+ioxesp32.upload.tool.network=esp_ota
+
+ioxesp32.upload.maximum_size=1310720
+ioxesp32.upload.maximum_data_size=327680
+ioxesp32.upload.flags=
+ioxesp32.upload.extra_flags=
+
+ioxesp32.serial.disableDTR=true
+ioxesp32.serial.disableRTS=true
+
+ioxesp32.build.tarch=xtensa
+ioxesp32.build.bootloader_addr=0x1000
+ioxesp32.build.target=esp32
+ioxesp32.build.mcu=esp32
+ioxesp32.build.core=esp32
+ioxesp32.build.variant=ioxesp32
+ioxesp32.build.board=IOXESP32
+
+ioxesp32.build.f_cpu=240000000L
+ioxesp32.build.flash_mode=dio
+ioxesp32.build.flash_size=4MB
+ioxesp32ps.build.flash_freq=40m
+ioxesp32.build.boot=dio
+ioxesp32.build.partitions=default
+ioxesp32.build.defines=
+ioxesp32.build.extra_libs=
+
+ioxesp32.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+ioxesp32.menu.PartitionScheme.default.build.partitions=default
+ioxesp32.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+ioxesp32.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+ioxesp32.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+ioxesp32.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+ioxesp32.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+ioxesp32.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+ioxesp32.menu.PartitionScheme.minimal.build.partitions=minimal
+ioxesp32.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+ioxesp32.menu.PartitionScheme.no_ota.build.partitions=no_ota
+ioxesp32.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+ioxesp32.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+ioxesp32.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+ioxesp32.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+ioxesp32.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+ioxesp32.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+ioxesp32.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+ioxesp32.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+ioxesp32.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+ioxesp32.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+ioxesp32.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+ioxesp32.menu.PartitionScheme.huge_app.build.partitions=huge_app
+ioxesp32.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+ioxesp32.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+ioxesp32.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+ioxesp32.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+ioxesp32.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+ioxesp32.menu.PartitionScheme.fatflash.build.partitions=ffat
+ioxesp32.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+ioxesp32.menu.PartitionScheme.rainmaker=RainMaker 4MB
+ioxesp32.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+ioxesp32.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+ioxesp32.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+ioxesp32.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+ioxesp32.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+ioxesp32.menu.FlashFreq.80=80MHz
+ioxesp32.menu.FlashFreq.80.build.flash_freq=80m
+ioxesp32.menu.FlashFreq.40=40MHz
+ioxesp32.menu.FlashFreq.40.build.flash_freq=40m
+
+ioxesp32.menu.UploadSpeed.921600=921600
+ioxesp32.menu.UploadSpeed.921600.upload.speed=921600
+ioxesp32.menu.UploadSpeed.115200=115200
+ioxesp32.menu.UploadSpeed.115200.upload.speed=115200
+ioxesp32.menu.UploadSpeed.256000.windows=256000
+ioxesp32.menu.UploadSpeed.256000.upload.speed=256000
+ioxesp32.menu.UploadSpeed.230400.windows.upload.speed=256000
+ioxesp32.menu.UploadSpeed.230400=230400
+ioxesp32.menu.UploadSpeed.230400.upload.speed=230400
+ioxesp32.menu.UploadSpeed.460800.linux=460800
+ioxesp32.menu.UploadSpeed.460800.macosx=460800
+ioxesp32.menu.UploadSpeed.460800.upload.speed=460800
+ioxesp32.menu.UploadSpeed.512000.windows=512000
+ioxesp32.menu.UploadSpeed.512000.upload.speed=512000
+
+ioxesp32.menu.DebugLevel.none=None
+ioxesp32.menu.DebugLevel.none.build.code_debug=0
+ioxesp32.menu.DebugLevel.error=Error
+ioxesp32.menu.DebugLevel.error.build.code_debug=1
+ioxesp32.menu.DebugLevel.warn=Warn
+ioxesp32.menu.DebugLevel.warn.build.code_debug=2
+ioxesp32.menu.DebugLevel.info=Info
+ioxesp32.menu.DebugLevel.info.build.code_debug=3
+ioxesp32.menu.DebugLevel.debug=Debug
+ioxesp32.menu.DebugLevel.debug.build.code_debug=4
+ioxesp32.menu.DebugLevel.verbose=Verbose
+ioxesp32.menu.DebugLevel.verbose.build.code_debug=5
+
+ioxesp32.menu.EraseFlash.none=Disabled
+ioxesp32.menu.EraseFlash.none.upload.erase_cmd=
+ioxesp32.menu.EraseFlash.all=Enabled
+ioxesp32.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# IOXESP32PS
+
+ioxesp32ps.name=IOXESP32PS
+
+ioxesp32ps.bootloader.tool=esptool_py
+ioxesp32ps.bootloader.tool.default=esptool_py
+
+ioxesp32ps.upload.tool=esptool_py
+ioxesp32ps.upload.tool.default=esptool_py
+ioxesp32ps.upload.tool.network=esp_ota
+
+ioxesp32ps.upload.maximum_size=1310720
+ioxesp32ps.upload.maximum_data_size=327680
+ioxesp32ps.upload.flags=
+ioxesp32ps.upload.extra_flags=
+
+ioxesp32ps.serial.disableDTR=true
+ioxesp32ps.serial.disableRTS=true
+
+ioxesp32ps.build.tarch=xtensa
+ioxesp32ps.build.bootloader_addr=0x1000
+ioxesp32ps.build.target=esp32
+ioxesp32ps.build.mcu=esp32
+ioxesp32ps.build.core=esp32
+ioxesp32ps.build.variant=ioxesp32
+ioxesp32ps.build.board=IOXESP32PS
+
+ioxesp32ps.build.f_cpu=240000000L
+ioxesp32ps.build.flash_mode=dio
+ioxesp32ps.build.flash_size=4MB
+ioxesp32ps.build.flash_freq=40m
+ioxesp32ps.build.boot=dio
+ioxesp32ps.build.partitions=default
+ioxesp32ps.build.defines=-DBOARD_HAS_PSRAM -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw
+ioxesp32ps.build.extra_libs=
+
+ioxesp32ps.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+ioxesp32ps.menu.PartitionScheme.default.build.partitions=default
+ioxesp32ps.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+ioxesp32ps.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+ioxesp32ps.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+ioxesp32ps.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+ioxesp32ps.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+ioxesp32ps.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+ioxesp32ps.menu.PartitionScheme.minimal.build.partitions=minimal
+ioxesp32ps.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+ioxesp32ps.menu.PartitionScheme.no_ota.build.partitions=no_ota
+ioxesp32ps.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+ioxesp32ps.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+ioxesp32ps.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+ioxesp32ps.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+ioxesp32ps.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+ioxesp32ps.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+ioxesp32ps.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+ioxesp32ps.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+ioxesp32ps.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+ioxesp32ps.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+ioxesp32ps.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+ioxesp32ps.menu.PartitionScheme.huge_app.build.partitions=huge_app
+ioxesp32ps.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+ioxesp32ps.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+ioxesp32ps.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+ioxesp32ps.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+ioxesp32ps.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+ioxesp32ps.menu.PartitionScheme.fatflash.build.partitions=ffat
+ioxesp32ps.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+ioxesp32ps.menu.PartitionScheme.rainmaker=RainMaker 4MB
+ioxesp32ps.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+ioxesp32ps.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+ioxesp32ps.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+ioxesp32ps.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+ioxesp32ps.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+ioxesp32ps.menu.FlashFreq.80=80MHz
+ioxesp32ps.menu.FlashFreq.80.build.flash_freq=80m
+ioxesp32ps.menu.FlashFreq.40=40MHz
+ioxesp32ps.menu.FlashFreq.40.build.flash_freq=40m
+
+ioxesp32ps.menu.UploadSpeed.921600=921600
+ioxesp32ps.menu.UploadSpeed.921600.upload.speed=921600
+ioxesp32ps.menu.UploadSpeed.115200=115200
+ioxesp32ps.menu.UploadSpeed.115200.upload.speed=115200
+ioxesp32ps.menu.UploadSpeed.256000.windows=256000
+ioxesp32ps.menu.UploadSpeed.256000.upload.speed=256000
+ioxesp32ps.menu.UploadSpeed.230400.windows.upload.speed=256000
+ioxesp32ps.menu.UploadSpeed.230400=230400
+ioxesp32ps.menu.UploadSpeed.230400.upload.speed=230400
+ioxesp32ps.menu.UploadSpeed.460800.linux=460800
+ioxesp32ps.menu.UploadSpeed.460800.macosx=460800
+ioxesp32ps.menu.UploadSpeed.460800.upload.speed=460800
+ioxesp32ps.menu.UploadSpeed.512000.windows=512000
+ioxesp32ps.menu.UploadSpeed.512000.upload.speed=512000
+
+ioxesp32ps.menu.DebugLevel.none=None
+ioxesp32ps.menu.DebugLevel.none.build.code_debug=0
+ioxesp32ps.menu.DebugLevel.error=Error
+ioxesp32ps.menu.DebugLevel.error.build.code_debug=1
+ioxesp32ps.menu.DebugLevel.warn=Warn
+ioxesp32ps.menu.DebugLevel.warn.build.code_debug=2
+ioxesp32ps.menu.DebugLevel.info=Info
+ioxesp32ps.menu.DebugLevel.info.build.code_debug=3
+ioxesp32ps.menu.DebugLevel.debug=Debug
+ioxesp32ps.menu.DebugLevel.debug.build.code_debug=4
+ioxesp32ps.menu.DebugLevel.verbose=Verbose
+ioxesp32ps.menu.DebugLevel.verbose.build.code_debug=5
+
+ioxesp32ps.menu.EraseFlash.none=Disabled
+ioxesp32ps.menu.EraseFlash.none.upload.erase_cmd=
+ioxesp32ps.menu.EraseFlash.all=Enabled
+ioxesp32ps.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# IOXESP32-C6
+
+ioxesp32c6.name=IOXESP32-C6
+
+ioxesp32c6.bootloader.tool=esptool_py
+ioxesp32c6.bootloader.tool.default=esptool_py
+
+ioxesp32c6.upload.tool=esptool_py
+ioxesp32c6.upload.tool.default=esptool_py
+ioxesp32c6.upload.tool.network=esp_ota
+
+ioxesp32c6.upload.maximum_size=1310720
+ioxesp32c6.upload.maximum_data_size=327680
+ioxesp32c6.upload.flags=
+ioxesp32c6.upload.extra_flags=
+ioxesp32c6.upload.use_1200bps_touch=false
+ioxesp32c6.upload.wait_for_upload_port=false
+
+ioxesp32c6.serial.disableDTR=false
+ioxesp32c6.serial.disableRTS=false
+
+ioxesp32c6.build.tarch=riscv32
+ioxesp32c6.build.target=esp
+ioxesp32c6.build.mcu=esp32c6
+ioxesp32c6.build.core=esp32
+ioxesp32c6.build.variant=ioxesp32c6
+ioxesp32c6.build.board=ESP32C6_DEV
+ioxesp32c6.build.bootloader_addr=0x0
+
+ioxesp32c6.build.cdc_on_boot=0
+ioxesp32c6.build.f_cpu=160000000L
+ioxesp32c6.build.flash_size=4MB
+ioxesp32c6.build.flash_freq=80m
+ioxesp32c6.build.flash_mode=qio
+ioxesp32c6.build.boot=qio
+ioxesp32c6.build.partitions=default
+ioxesp32c6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+ioxesp32c6.menu.JTAGAdapter.default=Disabled
+ioxesp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+ioxesp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+ioxesp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+ioxesp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+ioxesp32c6.menu.JTAGAdapter.external=FTDI Adapter
+ioxesp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+ioxesp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+ioxesp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge
+ioxesp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+ioxesp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+ioxesp32c6.menu.CDCOnBoot.default=Disabled
+ioxesp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=0
+ioxesp32c6.menu.CDCOnBoot.cdc=Enabled
+ioxesp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+ioxesp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+ioxesp32c6.menu.PartitionScheme.default.build.partitions=default
+ioxesp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+ioxesp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+ioxesp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+ioxesp32c6.menu.PartitionScheme.minimal.build.partitions=minimal
+ioxesp32c6.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+ioxesp32c6.menu.PartitionScheme.no_fs.build.partitions=no_fs
+ioxesp32c6.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+ioxesp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+ioxesp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+ioxesp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+ioxesp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+ioxesp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+ioxesp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+ioxesp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+ioxesp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+ioxesp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+ioxesp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+ioxesp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+ioxesp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+ioxesp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+ioxesp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+ioxesp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+ioxesp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+ioxesp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+ioxesp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+ioxesp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB
+ioxesp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+ioxesp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+ioxesp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+ioxesp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+ioxesp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+ioxesp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+ioxesp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+ioxesp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+ioxesp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+ioxesp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+ioxesp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+ioxesp32c6.menu.PartitionScheme.custom=Custom
+ioxesp32c6.menu.PartitionScheme.custom.build.partitions=
+ioxesp32c6.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+ioxesp32c6.menu.CPUFreq.160=160MHz (WiFi)
+ioxesp32c6.menu.CPUFreq.160.build.f_cpu=160000000L
+ioxesp32c6.menu.CPUFreq.120=120MHz (WiFi)
+ioxesp32c6.menu.CPUFreq.120.build.f_cpu=120000000L
+ioxesp32c6.menu.CPUFreq.80=80MHz (WiFi)
+ioxesp32c6.menu.CPUFreq.80.build.f_cpu=80000000L
+ioxesp32c6.menu.CPUFreq.40=40MHz
+ioxesp32c6.menu.CPUFreq.40.build.f_cpu=40000000L
+ioxesp32c6.menu.CPUFreq.20=20MHz
+ioxesp32c6.menu.CPUFreq.20.build.f_cpu=20000000L
+ioxesp32c6.menu.CPUFreq.10=10MHz
+ioxesp32c6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+ioxesp32c6.menu.FlashMode.qio=QIO
+ioxesp32c6.menu.FlashMode.qio.build.flash_mode=dio
+ioxesp32c6.menu.FlashMode.qio.build.boot=qio
+ioxesp32c6.menu.FlashMode.dio=DIO
+ioxesp32c6.menu.FlashMode.dio.build.flash_mode=dio
+ioxesp32c6.menu.FlashMode.dio.build.boot=dio
+
+ioxesp32c6.menu.FlashFreq.80=80MHz
+ioxesp32c6.menu.FlashFreq.80.build.flash_freq=80m
+ioxesp32c6.menu.FlashFreq.40=40MHz
+ioxesp32c6.menu.FlashFreq.40.build.flash_freq=40m
+
+ioxesp32c6.menu.UploadSpeed.921600=921600
+ioxesp32c6.menu.UploadSpeed.921600.upload.speed=921600
+ioxesp32c6.menu.UploadSpeed.115200=115200
+ioxesp32c6.menu.UploadSpeed.115200.upload.speed=115200
+ioxesp32c6.menu.UploadSpeed.256000.windows=256000
+ioxesp32c6.menu.UploadSpeed.256000.upload.speed=256000
+ioxesp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000
+ioxesp32c6.menu.UploadSpeed.230400=230400
+ioxesp32c6.menu.UploadSpeed.230400.upload.speed=230400
+ioxesp32c6.menu.UploadSpeed.460800.linux=460800
+ioxesp32c6.menu.UploadSpeed.460800.macosx=460800
+ioxesp32c6.menu.UploadSpeed.460800.upload.speed=460800
+ioxesp32c6.menu.UploadSpeed.512000.windows=512000
+ioxesp32c6.menu.UploadSpeed.512000.upload.speed=512000
+
+ioxesp32c6.menu.DebugLevel.none=None
+ioxesp32c6.menu.DebugLevel.none.build.code_debug=0
+ioxesp32c6.menu.DebugLevel.error=Error
+ioxesp32c6.menu.DebugLevel.error.build.code_debug=1
+ioxesp32c6.menu.DebugLevel.warn=Warn
+ioxesp32c6.menu.DebugLevel.warn.build.code_debug=2
+ioxesp32c6.menu.DebugLevel.info=Info
+ioxesp32c6.menu.DebugLevel.info.build.code_debug=3
+ioxesp32c6.menu.DebugLevel.debug=Debug
+ioxesp32c6.menu.DebugLevel.debug.build.code_debug=4
+ioxesp32c6.menu.DebugLevel.verbose=Verbose
+ioxesp32c6.menu.DebugLevel.verbose.build.code_debug=5
+
+ioxesp32c6.menu.EraseFlash.none=Disabled
+ioxesp32c6.menu.EraseFlash.none.upload.erase_cmd=
+ioxesp32c6.menu.EraseFlash.all=Enabled
+ioxesp32c6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+ioxesp32c6.menu.ZigbeeMode.default=Disabled
+ioxesp32c6.menu.ZigbeeMode.default.build.zigbee_mode=
+ioxesp32c6.menu.ZigbeeMode.default.build.zigbee_libs=
+ioxesp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+ioxesp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+ioxesp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+ioxesp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator)
+ioxesp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+ioxesp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+# ATD1.47-S3
+
+atd147_s3.name=ATD1.47-S3
+
+atd147_s3.bootloader.tool=esptool_py
+atd147_s3.bootloader.tool.default=esptool_py
+
+atd147_s3.upload.tool=esptool_py
+atd147_s3.upload.tool.default=esptool_py
+atd147_s3.upload.tool.network=esp_ota
+
+atd147_s3.upload.maximum_size=1310720
+atd147_s3.upload.maximum_data_size=327680
+atd147_s3.upload.flags=
+atd147_s3.upload.extra_flags=
+atd147_s3.upload.use_1200bps_touch=false
+atd147_s3.upload.wait_for_upload_port=false
+
+atd147_s3.serial.disableDTR=false
+atd147_s3.serial.disableRTS=false
+
+atd147_s3.build.tarch=xtensa
+atd147_s3.build.bootloader_addr=0x0
+atd147_s3.build.target=esp32s3
+atd147_s3.build.mcu=esp32s3
+atd147_s3.build.core=esp32
+atd147_s3.build.variant=atd147_s3
+atd147_s3.build.board=ATD143_S3
+
+atd147_s3.build.usb_mode=1
+atd147_s3.build.cdc_on_boot=0
+atd147_s3.build.msc_on_boot=0
+atd147_s3.build.dfu_on_boot=0
+atd147_s3.build.f_cpu=240000000L
+atd147_s3.build.flash_size=8MB
+atd147_s3.build.flash_freq=80m
+atd147_s3.build.flash_mode=dio
+atd147_s3.build.boot=qio
+atd147_s3.build.boot_freq=80m
+atd147_s3.build.partitions=default_8MB
+atd147_s3.build.defines=
+atd147_s3.build.loop_core=
+atd147_s3.build.event_core=
+atd147_s3.build.psram_type=opi
+atd147_s3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+atd147_s3.menu.JTAGAdapter.default=Disabled
+atd147_s3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+atd147_s3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+atd147_s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+atd147_s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+atd147_s3.menu.JTAGAdapter.external=FTDI Adapter
+atd147_s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+atd147_s3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+atd147_s3.menu.JTAGAdapter.bridge=ESP USB Bridge
+atd147_s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+atd147_s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+atd147_s3.menu.PSRAM.disabled=Disabled
+atd147_s3.menu.PSRAM.disabled.build.defines=
+atd147_s3.menu.PSRAM.disabled.build.psram_type=opi
+atd147_s3.menu.PSRAM.enabled=Enable
+atd147_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+atd147_s3.menu.PSRAM.enabled.build.psram_type=opi
+
+atd147_s3.menu.LoopCore.1=Core 1
+atd147_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+atd147_s3.menu.LoopCore.0=Core 0
+atd147_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+atd147_s3.menu.EventsCore.1=Core 1
+atd147_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+atd147_s3.menu.EventsCore.0=Core 0
+atd147_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+atd147_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+atd147_s3.menu.USBMode.hwcdc.build.usb_mode=1
+atd147_s3.menu.USBMode.default=USB-OTG (TinyUSB)
+atd147_s3.menu.USBMode.default.build.usb_mode=0
+
+atd147_s3.menu.CDCOnBoot.default=Disabled
+atd147_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+atd147_s3.menu.CDCOnBoot.cdc=Enabled
+atd147_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+atd147_s3.menu.MSCOnBoot.default=Disabled
+atd147_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+atd147_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+atd147_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+atd147_s3.menu.DFUOnBoot.default=Disabled
+atd147_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+atd147_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+atd147_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+atd147_s3.menu.UploadMode.default=UART0 / Hardware CDC
+atd147_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+atd147_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+atd147_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+atd147_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+atd147_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+atd147_s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+atd147_s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+atd147_s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+atd147_s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+atd147_s3.menu.PartitionScheme.minimal.build.partitions=minimal
+atd147_s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+atd147_s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+atd147_s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+atd147_s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+atd147_s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+atd147_s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+atd147_s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+atd147_s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+atd147_s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+atd147_s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+atd147_s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+atd147_s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+atd147_s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+atd147_s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+atd147_s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+atd147_s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+atd147_s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+atd147_s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+atd147_s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+atd147_s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+atd147_s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+atd147_s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+atd147_s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+atd147_s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+atd147_s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+atd147_s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+atd147_s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+atd147_s3.menu.CPUFreq.240=240MHz (WiFi)
+atd147_s3.menu.CPUFreq.240.build.f_cpu=240000000L
+atd147_s3.menu.CPUFreq.160=160MHz (WiFi)
+atd147_s3.menu.CPUFreq.160.build.f_cpu=160000000L
+atd147_s3.menu.CPUFreq.80=80MHz (WiFi)
+atd147_s3.menu.CPUFreq.80.build.f_cpu=80000000L
+atd147_s3.menu.CPUFreq.40=40MHz
+atd147_s3.menu.CPUFreq.40.build.f_cpu=40000000L
+atd147_s3.menu.CPUFreq.20=20MHz
+atd147_s3.menu.CPUFreq.20.build.f_cpu=20000000L
+atd147_s3.menu.CPUFreq.10=10MHz
+atd147_s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+atd147_s3.menu.UploadSpeed.921600=921600
+atd147_s3.menu.UploadSpeed.921600.upload.speed=921600
+atd147_s3.menu.UploadSpeed.115200=115200
+atd147_s3.menu.UploadSpeed.115200.upload.speed=115200
+atd147_s3.menu.UploadSpeed.256000.windows=256000
+atd147_s3.menu.UploadSpeed.256000.upload.speed=256000
+atd147_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+atd147_s3.menu.UploadSpeed.230400=230400
+atd147_s3.menu.UploadSpeed.230400.upload.speed=230400
+atd147_s3.menu.UploadSpeed.460800.linux=460800
+atd147_s3.menu.UploadSpeed.460800.macosx=460800
+atd147_s3.menu.UploadSpeed.460800.upload.speed=460800
+atd147_s3.menu.UploadSpeed.512000.windows=512000
+atd147_s3.menu.UploadSpeed.512000.upload.speed=512000
+
+atd147_s3.menu.DebugLevel.none=None
+atd147_s3.menu.DebugLevel.none.build.code_debug=0
+atd147_s3.menu.DebugLevel.error=Error
+atd147_s3.menu.DebugLevel.error.build.code_debug=1
+atd147_s3.menu.DebugLevel.warn=Warn
+atd147_s3.menu.DebugLevel.warn.build.code_debug=2
+atd147_s3.menu.DebugLevel.info=Info
+atd147_s3.menu.DebugLevel.info.build.code_debug=3
+atd147_s3.menu.DebugLevel.debug=Debug
+atd147_s3.menu.DebugLevel.debug.build.code_debug=4
+atd147_s3.menu.DebugLevel.verbose=Verbose
+atd147_s3.menu.DebugLevel.verbose.build.code_debug=5
+
+atd147_s3.menu.EraseFlash.none=Disabled
+atd147_s3.menu.EraseFlash.none.upload.erase_cmd=
+atd147_s3.menu.EraseFlash.all=Enabled
+atd147_s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# ATD3.5-S3
+
+atd35s3.name=ATD3.5-S3
+
+atd35s3.bootloader.tool=esptool_py
+atd35s3.bootloader.tool.default=esptool_py
+
+atd35s3.upload.tool=esptool_py
+atd35s3.upload.tool.default=esptool_py
+atd35s3.upload.tool.network=esp_ota
+
+atd35s3.upload.maximum_size=1310720
+atd35s3.upload.maximum_data_size=327680
+atd35s3.upload.flags=
+atd35s3.upload.extra_flags=
+atd35s3.upload.use_1200bps_touch=false
+atd35s3.upload.wait_for_upload_port=false
+
+atd35s3.serial.disableDTR=false
+atd35s3.serial.disableRTS=false
+
+atd35s3.build.tarch=xtensa
+atd35s3.build.bootloader_addr=0x0
+atd35s3.build.target=esp32s3
+atd35s3.build.mcu=esp32s3
+atd35s3.build.core=esp32
+atd35s3.build.variant=atd35s3
+atd35s3.build.board=ATD143_S3
+
+atd35s3.build.usb_mode=1
+atd35s3.build.cdc_on_boot=0
+atd35s3.build.msc_on_boot=0
+atd35s3.build.dfu_on_boot=0
+atd35s3.build.f_cpu=240000000L
+atd35s3.build.flash_size=8MB
+atd35s3.build.flash_freq=80m
+atd35s3.build.flash_mode=dio
+atd35s3.build.boot=qio
+atd35s3.build.boot_freq=80m
+atd35s3.build.partitions=default_8MB
+atd35s3.build.defines=
+atd35s3.build.loop_core=
+atd35s3.build.event_core=
+atd35s3.build.psram_type=opi
+atd35s3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+atd35s3.menu.JTAGAdapter.default=Disabled
+atd35s3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+atd35s3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+atd35s3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+atd35s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+atd35s3.menu.JTAGAdapter.external=FTDI Adapter
+atd35s3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+atd35s3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+atd35s3.menu.JTAGAdapter.bridge=ESP USB Bridge
+atd35s3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+atd35s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+atd35s3.menu.PSRAM.disabled=Disabled
+atd35s3.menu.PSRAM.disabled.build.defines=
+atd35s3.menu.PSRAM.disabled.build.psram_type=opi
+atd35s3.menu.PSRAM.enabled=Enable
+atd35s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+atd35s3.menu.PSRAM.enabled.build.psram_type=opi
+
+atd35s3.menu.LoopCore.1=Core 1
+atd35s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+atd35s3.menu.LoopCore.0=Core 0
+atd35s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+atd35s3.menu.EventsCore.1=Core 1
+atd35s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+atd35s3.menu.EventsCore.0=Core 0
+atd35s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+atd35s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+atd35s3.menu.USBMode.hwcdc.build.usb_mode=1
+atd35s3.menu.USBMode.default=USB-OTG (TinyUSB)
+atd35s3.menu.USBMode.default.build.usb_mode=0
+
+atd35s3.menu.CDCOnBoot.default=Disabled
+atd35s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+atd35s3.menu.CDCOnBoot.cdc=Enabled
+atd35s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+atd35s3.menu.MSCOnBoot.default=Disabled
+atd35s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+atd35s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+atd35s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+atd35s3.menu.DFUOnBoot.default=Disabled
+atd35s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+atd35s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+atd35s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+atd35s3.menu.UploadMode.default=UART0 / Hardware CDC
+atd35s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+atd35s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+atd35s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+atd35s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+atd35s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+atd35s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+atd35s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+atd35s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+atd35s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+atd35s3.menu.PartitionScheme.minimal.build.partitions=minimal
+atd35s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+atd35s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+atd35s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+atd35s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+atd35s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+atd35s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+atd35s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+atd35s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+atd35s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+atd35s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+atd35s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+atd35s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+atd35s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+atd35s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+atd35s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+atd35s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+atd35s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+atd35s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+atd35s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+atd35s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+atd35s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+atd35s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+atd35s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+atd35s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+atd35s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+atd35s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+atd35s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+atd35s3.menu.CPUFreq.240=240MHz (WiFi)
+atd35s3.menu.CPUFreq.240.build.f_cpu=240000000L
+atd35s3.menu.CPUFreq.160=160MHz (WiFi)
+atd35s3.menu.CPUFreq.160.build.f_cpu=160000000L
+atd35s3.menu.CPUFreq.80=80MHz (WiFi)
+atd35s3.menu.CPUFreq.80.build.f_cpu=80000000L
+atd35s3.menu.CPUFreq.40=40MHz
+atd35s3.menu.CPUFreq.40.build.f_cpu=40000000L
+atd35s3.menu.CPUFreq.20=20MHz
+atd35s3.menu.CPUFreq.20.build.f_cpu=20000000L
+atd35s3.menu.CPUFreq.10=10MHz
+atd35s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+atd35s3.menu.UploadSpeed.921600=921600
+atd35s3.menu.UploadSpeed.921600.upload.speed=921600
+atd35s3.menu.UploadSpeed.115200=115200
+atd35s3.menu.UploadSpeed.115200.upload.speed=115200
+atd35s3.menu.UploadSpeed.256000.windows=256000
+atd35s3.menu.UploadSpeed.256000.upload.speed=256000
+atd35s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+atd35s3.menu.UploadSpeed.230400=230400
+atd35s3.menu.UploadSpeed.230400.upload.speed=230400
+atd35s3.menu.UploadSpeed.460800.linux=460800
+atd35s3.menu.UploadSpeed.460800.macosx=460800
+atd35s3.menu.UploadSpeed.460800.upload.speed=460800
+atd35s3.menu.UploadSpeed.512000.windows=512000
+atd35s3.menu.UploadSpeed.512000.upload.speed=512000
+
+atd35s3.menu.DebugLevel.none=None
+atd35s3.menu.DebugLevel.none.build.code_debug=0
+atd35s3.menu.DebugLevel.error=Error
+atd35s3.menu.DebugLevel.error.build.code_debug=1
+atd35s3.menu.DebugLevel.warn=Warn
+atd35s3.menu.DebugLevel.warn.build.code_debug=2
+atd35s3.menu.DebugLevel.info=Info
+atd35s3.menu.DebugLevel.info.build.code_debug=3
+atd35s3.menu.DebugLevel.debug=Debug
+atd35s3.menu.DebugLevel.debug.build.code_debug=4
+atd35s3.menu.DebugLevel.verbose=Verbose
+atd35s3.menu.DebugLevel.verbose.build.code_debug=5
+
+atd35s3.menu.EraseFlash.none=Disabled
+atd35s3.menu.EraseFlash.none.upload.erase_cmd=
+atd35s3.menu.EraseFlash.all=Enabled
+atd35s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# ESP32-S3 PowerFeather
+
+esp32s3_powerfeather.name=ESP32-S3 PowerFeather
+esp32s3_powerfeather.vid.0=0x303a
+esp32s3_powerfeather.pid.0=0x81BB
+
+esp32s3_powerfeather.bootloader.tool=esptool_py
+esp32s3_powerfeather.bootloader.tool.default=esptool_py
+
+esp32s3_powerfeather.upload.tool=esptool_py
+esp32s3_powerfeather.upload.tool.default=esptool_py
+esp32s3_powerfeather.upload.tool.network=esp_ota
+
+esp32s3_powerfeather.upload.maximum_size=1310720
+esp32s3_powerfeather.upload.maximum_data_size=327680
+esp32s3_powerfeather.upload.flags=
+esp32s3_powerfeather.upload.extra_flags=
+esp32s3_powerfeather.upload.use_1200bps_touch=false
+esp32s3_powerfeather.upload.wait_for_upload_port=false
+
+esp32s3_powerfeather.serial.disableDTR=false
+esp32s3_powerfeather.serial.disableRTS=false
+
+esp32s3_powerfeather.build.tarch=xtensa
+esp32s3_powerfeather.build.bootloader_addr=0x0
+esp32s3_powerfeather.build.target=esp32s3
+esp32s3_powerfeather.build.mcu=esp32s3
+esp32s3_powerfeather.build.core=esp32
+esp32s3_powerfeather.build.variant=esp32s3_powerfeather
+esp32s3_powerfeather.build.board=ESP32S3_POWERFEATHER
+
+esp32s3_powerfeather.build.usb_mode=1
+esp32s3_powerfeather.build.cdc_on_boot=1
+esp32s3_powerfeather.build.msc_on_boot=0
+esp32s3_powerfeather.build.dfu_on_boot=0
+esp32s3_powerfeather.build.f_cpu=240000000L
+esp32s3_powerfeather.build.flash_size=8MB
+esp32s3_powerfeather.build.flash_freq=80m
+esp32s3_powerfeather.build.flash_mode=dio
+esp32s3_powerfeather.build.boot=qio
+esp32s3_powerfeather.build.boot_freq=80m
+esp32s3_powerfeather.build.partitions=default_8MB
+esp32s3_powerfeather.build.defines=
+esp32s3_powerfeather.build.loop_core=
+esp32s3_powerfeather.build.event_core=
+esp32s3_powerfeather.build.flash_type=qio
+esp32s3_powerfeather.build.psram_type=qspi
+esp32s3_powerfeather.build.memory_type={build.flash_type}_{build.psram_type}
+
+esp32s3_powerfeather.menu.PSRAM.disabled=Disabled
+esp32s3_powerfeather.menu.PSRAM.disabled.build.defines=
+esp32s3_powerfeather.menu.PSRAM.disabled.build.psram_type=qspi
+esp32s3_powerfeather.menu.PSRAM.enabled=QSPI PSRAM
+esp32s3_powerfeather.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+esp32s3_powerfeather.menu.PSRAM.enabled.build.psram_type=qspi
+
+esp32s3_powerfeather.menu.FlashMode.qio=QIO 80MHz
+esp32s3_powerfeather.menu.FlashMode.qio.build.flash_mode=dio
+esp32s3_powerfeather.menu.FlashMode.qio.build.boot=qio
+esp32s3_powerfeather.menu.FlashMode.qio.build.boot_freq=80m
+esp32s3_powerfeather.menu.FlashMode.qio.build.flash_freq=80m
+esp32s3_powerfeather.menu.FlashMode.qio120=QIO 120MHz
+esp32s3_powerfeather.menu.FlashMode.qio120.build.flash_mode=dio
+esp32s3_powerfeather.menu.FlashMode.qio120.build.boot=qio
+esp32s3_powerfeather.menu.FlashMode.qio120.build.boot_freq=120m
+esp32s3_powerfeather.menu.FlashMode.qio120.build.flash_freq=80m
+esp32s3_powerfeather.menu.FlashMode.dio=DIO 80MHz
+esp32s3_powerfeather.menu.FlashMode.dio.build.flash_mode=dio
+esp32s3_powerfeather.menu.FlashMode.dio.build.boot=dio
+esp32s3_powerfeather.menu.FlashMode.dio.build.boot_freq=80m
+esp32s3_powerfeather.menu.FlashMode.dio.build.flash_freq=80m
+
+esp32s3_powerfeather.menu.LoopCore.1=Core 1
+esp32s3_powerfeather.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+esp32s3_powerfeather.menu.LoopCore.0=Core 0
+esp32s3_powerfeather.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+esp32s3_powerfeather.menu.EventsCore.1=Core 1
+esp32s3_powerfeather.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+esp32s3_powerfeather.menu.EventsCore.0=Core 0
+esp32s3_powerfeather.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+esp32s3_powerfeather.menu.USBMode.hwcdc=Hardware CDC and JTAG
+esp32s3_powerfeather.menu.USBMode.hwcdc.build.usb_mode=1
+esp32s3_powerfeather.menu.USBMode.default=USB-OTG (TinyUSB)
+esp32s3_powerfeather.menu.USBMode.default.build.usb_mode=0
+
+esp32s3_powerfeather.menu.CDCOnBoot.cdc=Enabled
+esp32s3_powerfeather.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+esp32s3_powerfeather.menu.CDCOnBoot.default=Disabled
+esp32s3_powerfeather.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+esp32s3_powerfeather.menu.MSCOnBoot.default=Disabled
+esp32s3_powerfeather.menu.MSCOnBoot.default.build.msc_on_boot=0
+esp32s3_powerfeather.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+esp32s3_powerfeather.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+esp32s3_powerfeather.menu.DFUOnBoot.default=Disabled
+esp32s3_powerfeather.menu.DFUOnBoot.default.build.dfu_on_boot=0
+esp32s3_powerfeather.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+esp32s3_powerfeather.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+esp32s3_powerfeather.menu.UploadMode.default=UART0 / Hardware CDC
+esp32s3_powerfeather.menu.UploadMode.default.upload.use_1200bps_touch=false
+esp32s3_powerfeather.menu.UploadMode.default.upload.wait_for_upload_port=false
+esp32s3_powerfeather.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+esp32s3_powerfeather.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+esp32s3_powerfeather.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+esp32s3_powerfeather.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+esp32s3_powerfeather.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+esp32s3_powerfeather.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+esp32s3_powerfeather.menu.PartitionScheme.default_ffat_8MB=8M with ffat (3MB APP/1.5MB FATFS)
+esp32s3_powerfeather.menu.PartitionScheme.default_ffat_8MB.build.partitions=default_ffat_8MB
+esp32s3_powerfeather.menu.PartitionScheme.default_ffat_8MB.upload.maximum_size=3342336
+esp32s3_powerfeather.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.2MB APP/5.3MB SPIFFS)
+esp32s3_powerfeather.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB
+esp32s3_powerfeather.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720
+esp32s3_powerfeather.menu.PartitionScheme.large_ffat_8MB=Large FFAT (1.2MB APP/5.3MB FATFS)
+esp32s3_powerfeather.menu.PartitionScheme.large_ffat_8MB.build.partitions=large_ffat_8MB
+esp32s3_powerfeather.menu.PartitionScheme.large_ffat_8MB.upload.maximum_size=1310720
+esp32s3_powerfeather.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS)
+esp32s3_powerfeather.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB
+esp32s3_powerfeather.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536
+
+esp32s3_powerfeather.menu.CPUFreq.240=240MHz (WiFi)
+esp32s3_powerfeather.menu.CPUFreq.240.build.f_cpu=240000000L
+esp32s3_powerfeather.menu.CPUFreq.160=160MHz (WiFi)
+esp32s3_powerfeather.menu.CPUFreq.160.build.f_cpu=160000000L
+esp32s3_powerfeather.menu.CPUFreq.80=80MHz (WiFi)
+esp32s3_powerfeather.menu.CPUFreq.80.build.f_cpu=80000000L
+esp32s3_powerfeather.menu.CPUFreq.40=40MHz
+esp32s3_powerfeather.menu.CPUFreq.40.build.f_cpu=40000000L
+esp32s3_powerfeather.menu.CPUFreq.20=20MHz
+esp32s3_powerfeather.menu.CPUFreq.20.build.f_cpu=20000000L
+esp32s3_powerfeather.menu.CPUFreq.10=10MHz
+esp32s3_powerfeather.menu.CPUFreq.10.build.f_cpu=10000000L
+
+esp32s3_powerfeather.menu.UploadSpeed.921600=921600
+esp32s3_powerfeather.menu.UploadSpeed.921600.upload.speed=921600
+esp32s3_powerfeather.menu.UploadSpeed.115200=115200
+esp32s3_powerfeather.menu.UploadSpeed.115200.upload.speed=115200
+esp32s3_powerfeather.menu.UploadSpeed.256000.windows=256000
+esp32s3_powerfeather.menu.UploadSpeed.256000.upload.speed=256000
+esp32s3_powerfeather.menu.UploadSpeed.230400.windows.upload.speed=256000
+esp32s3_powerfeather.menu.UploadSpeed.230400=230400
+esp32s3_powerfeather.menu.UploadSpeed.230400.upload.speed=230400
+esp32s3_powerfeather.menu.UploadSpeed.460800.linux=460800
+esp32s3_powerfeather.menu.UploadSpeed.460800.macosx=460800
+esp32s3_powerfeather.menu.UploadSpeed.460800.upload.speed=460800
+esp32s3_powerfeather.menu.UploadSpeed.512000.windows=512000
+esp32s3_powerfeather.menu.UploadSpeed.512000.upload.speed=512000
+
+esp32s3_powerfeather.menu.DebugLevel.none=None
+esp32s3_powerfeather.menu.DebugLevel.none.build.code_debug=0
+esp32s3_powerfeather.menu.DebugLevel.error=Error
+esp32s3_powerfeather.menu.DebugLevel.error.build.code_debug=1
+esp32s3_powerfeather.menu.DebugLevel.warn=Warn
+esp32s3_powerfeather.menu.DebugLevel.warn.build.code_debug=2
+esp32s3_powerfeather.menu.DebugLevel.info=Info
+esp32s3_powerfeather.menu.DebugLevel.info.build.code_debug=3
+esp32s3_powerfeather.menu.DebugLevel.debug=Debug
+esp32s3_powerfeather.menu.DebugLevel.debug.build.code_debug=4
+esp32s3_powerfeather.menu.DebugLevel.verbose=Verbose
+esp32s3_powerfeather.menu.DebugLevel.verbose.build.code_debug=5
+
+esp32s3_powerfeather.menu.EraseFlash.none=Disabled
+esp32s3_powerfeather.menu.EraseFlash.none.upload.erase_cmd=
+esp32s3_powerfeather.menu.EraseFlash.all=Enabled
+esp32s3_powerfeather.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# senseBox MCU ESP32-S2
+
+sensebox_mcu_esp32s2.name=senseBox MCU-S2 ESP32-S2
+sensebox_mcu_esp32s2.vid.0=0x303A
+sensebox_mcu_esp32s2.pid.0=0x81B8
+sensebox_mcu_esp32s2.vid.1=0x303A
+sensebox_mcu_esp32s2.pid.1=0x81B9
+sensebox_mcu_esp32s2.vid.2=0x303A
+sensebox_mcu_esp32s2.pid.2=0x81BA
+
+sensebox_mcu_esp32s2.bootloader.tool=esptool_py
+sensebox_mcu_esp32s2.bootloader.tool.default=esptool_py
+
+sensebox_mcu_esp32s2.upload.tool=esptool_py
+sensebox_mcu_esp32s2.upload.tool.default=esptool_py
+sensebox_mcu_esp32s2.upload.tool.network=esp_ota
+
+sensebox_mcu_esp32s2.upload.maximum_size=1310720
+sensebox_mcu_esp32s2.upload.maximum_data_size=327680
+sensebox_mcu_esp32s2.upload.flags=
+sensebox_mcu_esp32s2.upload.extra_flags=
+sensebox_mcu_esp32s2.upload.use_1200bps_touch=true
+sensebox_mcu_esp32s2.upload.wait_for_upload_port=true
+
+sensebox_mcu_esp32s2.serial.disableDTR=false
+sensebox_mcu_esp32s2.serial.disableRTS=false
+
+sensebox_mcu_esp32s2.build.tarch=xtensa
+sensebox_mcu_esp32s2.build.bootloader_addr=0x1000
+sensebox_mcu_esp32s2.build.target=esp32s2
+sensebox_mcu_esp32s2.build.mcu=esp32s2
+sensebox_mcu_esp32s2.build.core=esp32
+sensebox_mcu_esp32s2.build.variant=sensebox_mcu_esp32s2
+sensebox_mcu_esp32s2.build.board=SENSEBOX_MCU_ESP32S2
+
+sensebox_mcu_esp32s2.build.cdc_on_boot=1
+sensebox_mcu_esp32s2.build.msc_on_boot=1
+sensebox_mcu_esp32s2.build.dfu_on_boot=0
+sensebox_mcu_esp32s2.build.f_cpu=240000000L
+sensebox_mcu_esp32s2.build.flash_size=4MB
+sensebox_mcu_esp32s2.build.flash_freq=80m
+sensebox_mcu_esp32s2.build.flash_mode=dio
+sensebox_mcu_esp32s2.build.boot=qio
+sensebox_mcu_esp32s2.build.partitions=default
+sensebox_mcu_esp32s2.build.defines=
+
+sensebox_mcu_esp32s2.menu.CDCOnBoot.cdc=Enabled
+sensebox_mcu_esp32s2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+sensebox_mcu_esp32s2.menu.CDCOnBoot.default=Disabled
+sensebox_mcu_esp32s2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+sensebox_mcu_esp32s2.menu.MSCOnBoot.msc=Enabled
+sensebox_mcu_esp32s2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+sensebox_mcu_esp32s2.menu.MSCOnBoot.default=Disabled
+sensebox_mcu_esp32s2.menu.MSCOnBoot.default.build.msc_on_boot=0
+
+sensebox_mcu_esp32s2.menu.DFUOnBoot.default=Disabled
+sensebox_mcu_esp32s2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+sensebox_mcu_esp32s2.menu.DFUOnBoot.dfu=Enabled
+sensebox_mcu_esp32s2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+sensebox_mcu_esp32s2.menu.UploadMode.cdc=Internal USB
+sensebox_mcu_esp32s2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+sensebox_mcu_esp32s2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+sensebox_mcu_esp32s2.menu.UploadMode.default=UART0
+sensebox_mcu_esp32s2.menu.UploadMode.default.upload.use_1200bps_touch=false
+sensebox_mcu_esp32s2.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+sensebox_mcu_esp32s2.menu.PSRAM.enabled=Enabled
+sensebox_mcu_esp32s2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+sensebox_mcu_esp32s2.menu.PSRAM.disabled=Disabled
+sensebox_mcu_esp32s2.menu.PSRAM.disabled.build.defines=
+
+sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2=TinyUF2 4MB (1.3MB APP/960KB FATFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader-tinyuf2
+sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions-4MB-tinyuf2
+sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2.upload.maximum_size=1441792
+sensebox_mcu_esp32s2.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x2d0000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+sensebox_mcu_esp32s2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.default.build.partitions=default
+sensebox_mcu_esp32s2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+sensebox_mcu_esp32s2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.minimal.build.partitions=minimal
+sensebox_mcu_esp32s2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+sensebox_mcu_esp32s2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+sensebox_mcu_esp32s2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+sensebox_mcu_esp32s2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+sensebox_mcu_esp32s2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+sensebox_mcu_esp32s2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+sensebox_mcu_esp32s2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+sensebox_mcu_esp32s2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+sensebox_mcu_esp32s2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+sensebox_mcu_esp32s2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+sensebox_mcu_esp32s2.menu.CPUFreq.240=240MHz (WiFi)
+sensebox_mcu_esp32s2.menu.CPUFreq.240.build.f_cpu=240000000L
+sensebox_mcu_esp32s2.menu.CPUFreq.160=160MHz (WiFi)
+sensebox_mcu_esp32s2.menu.CPUFreq.160.build.f_cpu=160000000L
+sensebox_mcu_esp32s2.menu.CPUFreq.80=80MHz (WiFi)
+sensebox_mcu_esp32s2.menu.CPUFreq.80.build.f_cpu=80000000L
+sensebox_mcu_esp32s2.menu.CPUFreq.40=40MHz
+sensebox_mcu_esp32s2.menu.CPUFreq.40.build.f_cpu=40000000L
+sensebox_mcu_esp32s2.menu.CPUFreq.20=20MHz
+sensebox_mcu_esp32s2.menu.CPUFreq.20.build.f_cpu=20000000L
+sensebox_mcu_esp32s2.menu.CPUFreq.10=10MHz
+sensebox_mcu_esp32s2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+sensebox_mcu_esp32s2.menu.FlashMode.qio=QIO
+sensebox_mcu_esp32s2.menu.FlashMode.qio.build.flash_mode=dio
+sensebox_mcu_esp32s2.menu.FlashMode.qio.build.boot=qio
+sensebox_mcu_esp32s2.menu.FlashMode.dio=DIO
+sensebox_mcu_esp32s2.menu.FlashMode.dio.build.flash_mode=dio
+sensebox_mcu_esp32s2.menu.FlashMode.dio.build.boot=dio
+sensebox_mcu_esp32s2.menu.FlashMode.qout=QOUT
+sensebox_mcu_esp32s2.menu.FlashMode.qout.build.flash_mode=dout
+sensebox_mcu_esp32s2.menu.FlashMode.qout.build.boot=qout
+sensebox_mcu_esp32s2.menu.FlashMode.dout=DOUT
+sensebox_mcu_esp32s2.menu.FlashMode.dout.build.flash_mode=dout
+sensebox_mcu_esp32s2.menu.FlashMode.dout.build.boot=dout
+
+sensebox_mcu_esp32s2.menu.FlashFreq.80=80MHz
+sensebox_mcu_esp32s2.menu.FlashFreq.80.build.flash_freq=80m
+sensebox_mcu_esp32s2.menu.FlashFreq.40=40MHz
+sensebox_mcu_esp32s2.menu.FlashFreq.40.build.flash_freq=40m
+
+sensebox_mcu_esp32s2.menu.FlashSize.4M=4MB (32Mb)
+sensebox_mcu_esp32s2.menu.FlashSize.4M.build.flash_size=4MB
+
+sensebox_mcu_esp32s2.menu.UploadSpeed.921600=921600
+sensebox_mcu_esp32s2.menu.UploadSpeed.921600.upload.speed=921600
+sensebox_mcu_esp32s2.menu.UploadSpeed.115200=115200
+sensebox_mcu_esp32s2.menu.UploadSpeed.115200.upload.speed=115200
+sensebox_mcu_esp32s2.menu.UploadSpeed.256000.windows=256000
+sensebox_mcu_esp32s2.menu.UploadSpeed.256000.upload.speed=256000
+sensebox_mcu_esp32s2.menu.UploadSpeed.230400.windows.upload.speed=256000
+sensebox_mcu_esp32s2.menu.UploadSpeed.230400=230400
+sensebox_mcu_esp32s2.menu.UploadSpeed.230400.upload.speed=230400
+sensebox_mcu_esp32s2.menu.UploadSpeed.460800.linux=460800
+sensebox_mcu_esp32s2.menu.UploadSpeed.460800.macosx=460800
+sensebox_mcu_esp32s2.menu.UploadSpeed.460800.upload.speed=460800
+sensebox_mcu_esp32s2.menu.UploadSpeed.512000.windows=512000
+sensebox_mcu_esp32s2.menu.UploadSpeed.512000.upload.speed=512000
+
+sensebox_mcu_esp32s2.menu.DebugLevel.none=None
+sensebox_mcu_esp32s2.menu.DebugLevel.none.build.code_debug=0
+sensebox_mcu_esp32s2.menu.DebugLevel.error=Error
+sensebox_mcu_esp32s2.menu.DebugLevel.error.build.code_debug=1
+sensebox_mcu_esp32s2.menu.DebugLevel.warn=Warn
+sensebox_mcu_esp32s2.menu.DebugLevel.warn.build.code_debug=2
+sensebox_mcu_esp32s2.menu.DebugLevel.info=Info
+sensebox_mcu_esp32s2.menu.DebugLevel.info.build.code_debug=3
+sensebox_mcu_esp32s2.menu.DebugLevel.debug=Debug
+sensebox_mcu_esp32s2.menu.DebugLevel.debug.build.code_debug=4
+sensebox_mcu_esp32s2.menu.DebugLevel.verbose=Verbose
+sensebox_mcu_esp32s2.menu.DebugLevel.verbose.build.code_debug=5
+
+sensebox_mcu_esp32s2.menu.EraseFlash.none=Disabled
+sensebox_mcu_esp32s2.menu.EraseFlash.none.upload.erase_cmd=
+sensebox_mcu_esp32s2.menu.EraseFlash.all=Enabled
+sensebox_mcu_esp32s2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+nano_nora.name=Arduino Nano ESP32
+nano_nora.vid.0=0x2341
+nano_nora.pid.0=0x0070
+nano_nora.upload_port.0.vid=0x2341
+nano_nora.upload_port.0.pid=0x0070
+
+nano_nora.bootloader.tool=esptool_py
+nano_nora.bootloader.tool.default=esptool_py
+
+nano_nora.upload.tool=dfu-util
+nano_nora.upload.tool.default=dfu-util
+nano_nora.upload.tool.network=esp_ota
+nano_nora.upload.protocol=serial
+nano_nora.upload.maximum_size=3145728
+nano_nora.upload.maximum_data_size=327680
+nano_nora.upload.use_1200bps_touch=false
+nano_nora.upload.wait_for_upload_port=false
+
+nano_nora.serial.disableDTR=false
+nano_nora.serial.disableRTS=false
+
+nano_nora.build.tarch=xtensa
+nano_nora.build.bootloader_addr=0x0
+nano_nora.build.target=esp32s3
+nano_nora.build.mcu=esp32s3
+nano_nora.build.core=esp32
+nano_nora.build.variant=arduino_nano_nora
+nano_nora.build.board=NANO_ESP32
+nano_nora.build.code_debug=0
+
+nano_nora.build.usb_mode=0
+nano_nora.build.cdc_on_boot=1
+nano_nora.build.msc_on_boot=0
+nano_nora.build.dfu_on_boot=1
+nano_nora.build.f_cpu=240000000L
+nano_nora.build.flash_size=16MB
+nano_nora.build.flash_freq=80m
+nano_nora.build.flash_mode=dio
+nano_nora.build.boot=qio
+nano_nora.build.boot_freq=80m
+nano_nora.build.partitions=app3M_fat9M_fact512k_16MB
+nano_nora.build.defines=-DBOARD_HAS_PIN_REMAP {build.disable_pin_remap} -DBOARD_HAS_PSRAM '-DUSB_MANUFACTURER="Arduino"' '-DUSB_PRODUCT="Nano ESP32"'
+nano_nora.build.loop_core=-DARDUINO_RUNNING_CORE=1
+nano_nora.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+nano_nora.build.psram_type=opi
+nano_nora.build.memory_type={build.boot}_{build.psram_type}
+nano_nora.build.disable_pin_remap=
+
+nano_nora.debug_config.nano_nora.cortex-debug.custom.name=Arduino on Nano ESP32
+nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideAttachCommands.0=set remote hardware-watchpoint-limit 2
+nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideAttachCommands.1=monitor reset halt
+nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideAttachCommands.2=monitor gdb_sync
+nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideAttachCommands.3=interrupt
+nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideRestartCommands.0=monitor reset halt
+nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideRestartCommands.1=monitor gdb_sync
+nano_nora.debug_config.nano_nora.cortex-debug.custom.overrideRestartCommands.2=interrupt
+nano_nora.debug.additional_config=debug_config.nano_nora
+
+nano_nora.tools.esptool_py.program.pattern_args=--chip {build.mcu} --port "{serial.port}" --before default_reset --after hard_reset write_flash -z --flash_mode {build.flash_mode} --flash_freq {build.flash_freq} --flash_size {build.flash_size} {build.bootloader_addr} "{build.path}/{build.project_name}.bootloader.bin" 0x8000 "{build.path}/{build.project_name}.partitions.bin" 0xe000 "{runtime.platform.path}/tools/partitions/boot_app0.bin" 0xf70000 "{build.variant.path}/extra/nora_recovery/nora_recovery.ino.bin" 0x10000 "{build.path}/{build.project_name}.bin"
+nano_nora.tools.esptool_py.erase.pattern_args=--chip {build.mcu} --port "{serial.port}" --before default_reset --after hard_reset erase_flash
+
+nano_nora.debug.executable=
+
+nano_nora.menu.PartitionScheme.default=With FAT partition (default)
+nano_nora.menu.PartitionScheme.spiffs=With SPIFFS partition (advanced)
+nano_nora.menu.PartitionScheme.spiffs.build.partitions=app3M_spiffs9M_fact512k_16MB
+
+nano_nora.menu.PinNumbers.default=By Arduino pin (default)
+nano_nora.menu.PinNumbers.byGPIONumber=By GPIO number (legacy)
+nano_nora.menu.PinNumbers.byGPIONumber.build.disable_pin_remap=-DBOARD_USES_HW_GPIO_NUMBERS
+
+nano_nora.menu.USBMode.default=Normal mode (TinyUSB)
+nano_nora.menu.USBMode.hwcdc=Debug mode (Hardware CDC)
+nano_nora.menu.USBMode.hwcdc.build.usb_mode=1
+nano_nora.menu.USBMode.hwcdc.debug.executable={build.path}/{build.project_name}.elf
+
+##############################################################
+
+makergo_c3_supermini.name=MakerGO ESP32 C3 SuperMini
+
+makergo_c3_supermini.bootloader.tool=esptool_py
+makergo_c3_supermini.bootloader.tool.default=esptool_py
+
+makergo_c3_supermini.upload.tool=esptool_py
+makergo_c3_supermini.upload.tool.default=esptool_py
+makergo_c3_supermini.upload.tool.network=esp_ota
+
+makergo_c3_supermini.upload.maximum_size=1310720
+makergo_c3_supermini.upload.maximum_data_size=327680
+makergo_c3_supermini.upload.flags=
+makergo_c3_supermini.upload.extra_flags=
+makergo_c3_supermini.upload.use_1200bps_touch=false
+makergo_c3_supermini.upload.wait_for_upload_port=false
+
+makergo_c3_supermini.serial.disableDTR=true
+makergo_c3_supermini.serial.disableRTS=true
+
+makergo_c3_supermini.build.tarch=riscv32
+makergo_c3_supermini.build.target=esp
+makergo_c3_supermini.build.mcu=esp32c3
+makergo_c3_supermini.build.core=esp32
+makergo_c3_supermini.build.variant=makergo_c3_supermini
+makergo_c3_supermini.build.board=MAKERGO_C3_SUPERMINI
+makergo_c3_supermini.build.bootloader_addr=0x0
+
+makergo_c3_supermini.build.cdc_on_boot=1
+makergo_c3_supermini.build.f_cpu=160000000L
+makergo_c3_supermini.build.flash_size=4MB
+makergo_c3_supermini.build.flash_freq=80m
+makergo_c3_supermini.build.flash_mode=dio
+makergo_c3_supermini.build.boot=qio
+makergo_c3_supermini.build.partitions=default
+makergo_c3_supermini.build.defines=
+
+makergo_c3_supermini.menu.CDCOnBoot.default=Enabled
+makergo_c3_supermini.menu.CDCOnBoot.default.build.cdc_on_boot=1
+makergo_c3_supermini.menu.CDCOnBoot.dis_cdc=Disabled
+makergo_c3_supermini.menu.CDCOnBoot.dis_cdc.build.cdc_on_boot=0
+
+makergo_c3_supermini.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+makergo_c3_supermini.menu.PartitionScheme.default.build.partitions=default
+makergo_c3_supermini.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+makergo_c3_supermini.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+makergo_c3_supermini.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+makergo_c3_supermini.menu.PartitionScheme.no_ota.build.partitions=no_ota
+makergo_c3_supermini.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+makergo_c3_supermini.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+makergo_c3_supermini.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+makergo_c3_supermini.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+makergo_c3_supermini.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+makergo_c3_supermini.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+makergo_c3_supermini.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+makergo_c3_supermini.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+makergo_c3_supermini.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+makergo_c3_supermini.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+makergo_c3_supermini.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+makergo_c3_supermini.menu.PartitionScheme.huge_app.build.partitions=huge_app
+makergo_c3_supermini.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+
+makergo_c3_supermini.menu.CPUFreq.160=160MHz (WiFi)
+makergo_c3_supermini.menu.CPUFreq.160.build.f_cpu=160000000L
+makergo_c3_supermini.menu.CPUFreq.80=80MHz (WiFi)
+makergo_c3_supermini.menu.CPUFreq.80.build.f_cpu=80000000L
+makergo_c3_supermini.menu.CPUFreq.40=40MHz
+makergo_c3_supermini.menu.CPUFreq.40.build.f_cpu=40000000L
+makergo_c3_supermini.menu.CPUFreq.20=20MHz
+makergo_c3_supermini.menu.CPUFreq.20.build.f_cpu=20000000L
+makergo_c3_supermini.menu.CPUFreq.10=10MHz
+makergo_c3_supermini.menu.CPUFreq.10.build.f_cpu=10000000L
+
+
+makergo_c3_supermini.menu.FlashFreq.80=80MHz
+makergo_c3_supermini.menu.FlashFreq.80.build.flash_freq=80m
+makergo_c3_supermini.menu.FlashFreq.40=40MHz
+makergo_c3_supermini.menu.FlashFreq.40.build.flash_freq=40m
+
+makergo_c3_supermini.menu.UploadSpeed.921600=921600
+makergo_c3_supermini.menu.UploadSpeed.921600.upload.speed=921600
+makergo_c3_supermini.menu.UploadSpeed.115200=115200
+makergo_c3_supermini.menu.UploadSpeed.115200.upload.speed=115200
+makergo_c3_supermini.menu.UploadSpeed.256000.windows=256000
+makergo_c3_supermini.menu.UploadSpeed.256000.upload.speed=256000
+makergo_c3_supermini.menu.UploadSpeed.230400.windows.upload.speed=256000
+makergo_c3_supermini.menu.UploadSpeed.230400=230400
+makergo_c3_supermini.menu.UploadSpeed.230400.upload.speed=230400
+makergo_c3_supermini.menu.UploadSpeed.460800.linux=460800
+makergo_c3_supermini.menu.UploadSpeed.460800.macosx=460800
+makergo_c3_supermini.menu.UploadSpeed.460800.upload.speed=460800
+makergo_c3_supermini.menu.UploadSpeed.512000.windows=512000
+makergo_c3_supermini.menu.UploadSpeed.512000.upload.speed=512000
+
+makergo_c3_supermini.menu.DebugLevel.none=None
+makergo_c3_supermini.menu.DebugLevel.none.build.code_debug=0
+makergo_c3_supermini.menu.DebugLevel.error=Error
+makergo_c3_supermini.menu.DebugLevel.error.build.code_debug=1
+makergo_c3_supermini.menu.DebugLevel.warn=Warn
+makergo_c3_supermini.menu.DebugLevel.warn.build.code_debug=2
+makergo_c3_supermini.menu.DebugLevel.info=Info
+makergo_c3_supermini.menu.DebugLevel.info.build.code_debug=3
+makergo_c3_supermini.menu.DebugLevel.debug=Debug
+makergo_c3_supermini.menu.DebugLevel.debug.build.code_debug=4
+makergo_c3_supermini.menu.DebugLevel.verbose=Verbose
+makergo_c3_supermini.menu.DebugLevel.verbose.build.code_debug=5
+
+makergo_c3_supermini.menu.EraseFlash.none=Disabled
+makergo_c3_supermini.menu.EraseFlash.none.upload.erase_cmd=
+makergo_c3_supermini.menu.EraseFlash.all=Enabled
+makergo_c3_supermini.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# ThingPulse ePulse Feather
+
+epulse_feather.name=ThingPulse ePulse Feather
+
+epulse_feather.bootloader.tool=esptool_py
+epulse_feather.bootloader.tool.default=esptool_py
+
+epulse_feather.upload.tool=esptool_py
+epulse_feather.upload.tool.default=esptool_py
+epulse_feather.upload.tool.network=esp_ota
+
+epulse_feather.upload.maximum_size=1310720
+epulse_feather.upload.maximum_data_size=327680
+epulse_feather.upload.flags=
+epulse_feather.upload.extra_flags=
+
+epulse_feather.serial.disableDTR=true
+epulse_feather.serial.disableRTS=true
+
+epulse_feather.build.tarch=xtensa
+epulse_feather.build.bootloader_addr=0x1000
+epulse_feather.build.target=esp32
+epulse_feather.build.mcu=esp32
+epulse_feather.build.core=esp32
+epulse_feather.build.variant=thingpulse_epulse_feather
+epulse_feather.build.board=THINGPULSE_EPULSE_FEATHER
+
+epulse_feather.build.f_cpu=240000000L
+epulse_feather.build.flash_size=8MB
+epulse_feather.build.flash_freq=80m
+epulse_feather.build.flash_mode=dio
+epulse_feather.build.boot=dio
+epulse_feather.build.partitions=default_8MB
+epulse_feather.build.defines=
+epulse_feather.build.loop_core=
+epulse_feather.build.event_core=
+
+epulse_feather.menu.PSRAM.enabled=Enabled
+epulse_feather.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+epulse_feather.menu.PSRAM.disabled=Disabled
+epulse_feather.menu.PSRAM.disabled.build.defines=
+
+epulse_feather.menu.LoopCore.1=Core 1
+epulse_feather.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+epulse_feather.menu.LoopCore.0=Core 0
+epulse_feather.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+epulse_feather.menu.EventsCore.1=Core 1
+epulse_feather.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+epulse_feather.menu.EventsCore.0=Core 0
+epulse_feather.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+epulse_feather.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+epulse_feather.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+epulse_feather.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+epulse_feather.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS)
+epulse_feather.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB
+epulse_feather.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536
+
+epulse_feather.menu.CPUFreq.240=240MHz (WiFi/BT)
+epulse_feather.menu.CPUFreq.240.build.f_cpu=240000000L
+epulse_feather.menu.CPUFreq.160=160MHz (WiFi/BT)
+epulse_feather.menu.CPUFreq.160.build.f_cpu=160000000L
+epulse_feather.menu.CPUFreq.80=80MHz (WiFi/BT)
+epulse_feather.menu.CPUFreq.80.build.f_cpu=80000000L
+epulse_feather.menu.CPUFreq.40=40MHz
+epulse_feather.menu.CPUFreq.40.build.f_cpu=40000000L
+epulse_feather.menu.CPUFreq.20=20MHz
+epulse_feather.menu.CPUFreq.20.build.f_cpu=20000000L
+epulse_feather.menu.CPUFreq.10=10MHz
+epulse_feather.menu.CPUFreq.10.build.f_cpu=10000000L
+
+epulse_feather.menu.FlashFreq.80=80MHz
+epulse_feather.menu.FlashFreq.80.build.flash_freq=80m
+epulse_feather.menu.FlashFreq.40=40MHz
+epulse_feather.menu.FlashFreq.40.build.flash_freq=40m
+
+epulse_feather.menu.UploadSpeed.921600=921600
+epulse_feather.menu.UploadSpeed.921600.upload.speed=921600
+epulse_feather.menu.UploadSpeed.115200=115200
+epulse_feather.menu.UploadSpeed.115200.upload.speed=115200
+epulse_feather.menu.UploadSpeed.256000.windows=256000
+epulse_feather.menu.UploadSpeed.256000.upload.speed=256000
+epulse_feather.menu.UploadSpeed.230400.windows.upload.speed=256000
+epulse_feather.menu.UploadSpeed.230400=230400
+epulse_feather.menu.UploadSpeed.230400.upload.speed=230400
+epulse_feather.menu.UploadSpeed.460800.linux=460800
+epulse_feather.menu.UploadSpeed.460800.macosx=460800
+epulse_feather.menu.UploadSpeed.460800.upload.speed=460800
+epulse_feather.menu.UploadSpeed.512000.windows=512000
+epulse_feather.menu.UploadSpeed.512000.upload.speed=512000
+
+epulse_feather.menu.DebugLevel.none=None
+epulse_feather.menu.DebugLevel.none.build.code_debug=0
+epulse_feather.menu.DebugLevel.error=Error
+epulse_feather.menu.DebugLevel.error.build.code_debug=1
+epulse_feather.menu.DebugLevel.warn=Warn
+epulse_feather.menu.DebugLevel.warn.build.code_debug=2
+epulse_feather.menu.DebugLevel.info=Info
+epulse_feather.menu.DebugLevel.info.build.code_debug=3
+epulse_feather.menu.DebugLevel.debug=Debug
+epulse_feather.menu.DebugLevel.debug.build.code_debug=4
+epulse_feather.menu.DebugLevel.verbose=Verbose
+epulse_feather.menu.DebugLevel.verbose.build.code_debug=5
+
+epulse_feather.menu.EraseFlash.none=Disabled
+epulse_feather.menu.EraseFlash.none.upload.erase_cmd=
+epulse_feather.menu.EraseFlash.all=Enabled
+epulse_feather.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# ThingPulse ePulse Feather C6
+
+epulse_feather_c6.name=ThingPulse ePulse Feather C6
+
+epulse_feather_c6.bootloader.tool=esptool_py
+epulse_feather_c6.bootloader.tool.default=esptool_py
+
+epulse_feather_c6.upload.tool=esptool_py
+epulse_feather_c6.upload.tool.default=esptool_py
+epulse_feather_c6.upload.tool.network=esp_ota
+
+epulse_feather_c6.upload.maximum_size=1310720
+epulse_feather_c6.upload.maximum_data_size=327680
+epulse_feather_c6.upload.flags=
+epulse_feather_c6.upload.extra_flags=
+epulse_feather_c6.upload.use_1200bps_touch=false
+epulse_feather_c6.upload.wait_for_upload_port=false
+
+epulse_feather_c6.serial.disableDTR=false
+epulse_feather_c6.serial.disableRTS=false
+
+epulse_feather_c6.build.tarch=riscv32
+epulse_feather_c6.build.target=esp
+epulse_feather_c6.build.mcu=esp32c6
+epulse_feather_c6.build.core=esp32
+epulse_feather_c6.build.variant=thingpulse_epulse_feather_c6
+epulse_feather_c6.build.board=THINGPULSE_EPULSE_FEATHER_C6
+epulse_feather_c6.build.bootloader_addr=0x0
+
+epulse_feather_c6.build.cdc_on_boot=0
+epulse_feather_c6.build.f_cpu=160000000L
+epulse_feather_c6.build.flash_size=4MB
+epulse_feather_c6.build.flash_freq=80m
+epulse_feather_c6.build.flash_mode=qio
+epulse_feather_c6.build.boot=qio
+epulse_feather_c6.build.partitions=default
+epulse_feather_c6.build.defines=
+
+epulse_feather_c6.menu.JTAGAdapter.default=Disabled
+epulse_feather_c6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+epulse_feather_c6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+epulse_feather_c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+epulse_feather_c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+epulse_feather_c6.menu.JTAGAdapter.external=FTDI Adapter
+epulse_feather_c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+epulse_feather_c6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+epulse_feather_c6.menu.JTAGAdapter.bridge=ESP USB Bridge
+epulse_feather_c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+epulse_feather_c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+epulse_feather_c6.menu.CDCOnBoot.default=Disabled
+epulse_feather_c6.menu.CDCOnBoot.default.build.cdc_on_boot=0
+epulse_feather_c6.menu.CDCOnBoot.cdc=Enabled
+epulse_feather_c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+epulse_feather_c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+epulse_feather_c6.menu.PartitionScheme.default.build.partitions=default
+epulse_feather_c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+epulse_feather_c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+epulse_feather_c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+epulse_feather_c6.menu.PartitionScheme.minimal.build.partitions=minimal
+epulse_feather_c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+epulse_feather_c6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+epulse_feather_c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+epulse_feather_c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+epulse_feather_c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+epulse_feather_c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+epulse_feather_c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+epulse_feather_c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+epulse_feather_c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+epulse_feather_c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+epulse_feather_c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+epulse_feather_c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+epulse_feather_c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+epulse_feather_c6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+epulse_feather_c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+epulse_feather_c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+epulse_feather_c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+epulse_feather_c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+epulse_feather_c6.menu.PartitionScheme.rainmaker=RainMaker 4MB
+epulse_feather_c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+epulse_feather_c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+epulse_feather_c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+epulse_feather_c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+epulse_feather_c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+epulse_feather_c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+epulse_feather_c6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+epulse_feather_c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+epulse_feather_c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+epulse_feather_c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+epulse_feather_c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+epulse_feather_c6.menu.PartitionScheme.custom=Custom
+epulse_feather_c6.menu.PartitionScheme.custom.build.partitions=
+epulse_feather_c6.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+epulse_feather_c6.menu.CPUFreq.160=160MHz (WiFi)
+epulse_feather_c6.menu.CPUFreq.160.build.f_cpu=160000000L
+epulse_feather_c6.menu.CPUFreq.120=120MHz (WiFi)
+epulse_feather_c6.menu.CPUFreq.120.build.f_cpu=120000000L
+epulse_feather_c6.menu.CPUFreq.80=80MHz (WiFi)
+epulse_feather_c6.menu.CPUFreq.80.build.f_cpu=80000000L
+epulse_feather_c6.menu.CPUFreq.40=40MHz
+epulse_feather_c6.menu.CPUFreq.40.build.f_cpu=40000000L
+epulse_feather_c6.menu.CPUFreq.20=20MHz
+epulse_feather_c6.menu.CPUFreq.20.build.f_cpu=20000000L
+epulse_feather_c6.menu.CPUFreq.10=10MHz
+epulse_feather_c6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+epulse_feather_c6.menu.FlashMode.qio=QIO
+epulse_feather_c6.menu.FlashMode.qio.build.flash_mode=dio
+epulse_feather_c6.menu.FlashMode.qio.build.boot=qio
+epulse_feather_c6.menu.FlashMode.dio=DIO
+epulse_feather_c6.menu.FlashMode.dio.build.flash_mode=dio
+epulse_feather_c6.menu.FlashMode.dio.build.boot=dio
+
+epulse_feather_c6.menu.FlashFreq.80=80MHz
+epulse_feather_c6.menu.FlashFreq.80.build.flash_freq=80m
+epulse_feather_c6.menu.FlashFreq.40=40MHz
+epulse_feather_c6.menu.FlashFreq.40.build.flash_freq=40m
+
+epulse_feather_c6.menu.FlashSize.4M=4MB (32Mb)
+epulse_feather_c6.menu.FlashSize.4M.build.flash_size=4MB
+epulse_feather_c6.menu.FlashSize.2M=2MB (16Mb)
+epulse_feather_c6.menu.FlashSize.2M.build.flash_size=2MB
+
+epulse_feather_c6.menu.UploadSpeed.921600=921600
+epulse_feather_c6.menu.UploadSpeed.921600.upload.speed=921600
+epulse_feather_c6.menu.UploadSpeed.115200=115200
+epulse_feather_c6.menu.UploadSpeed.115200.upload.speed=115200
+epulse_feather_c6.menu.UploadSpeed.256000.windows=256000
+epulse_feather_c6.menu.UploadSpeed.256000.upload.speed=256000
+epulse_feather_c6.menu.UploadSpeed.230400.windows.upload.speed=256000
+epulse_feather_c6.menu.UploadSpeed.230400=230400
+epulse_feather_c6.menu.UploadSpeed.230400.upload.speed=230400
+epulse_feather_c6.menu.UploadSpeed.460800.linux=460800
+epulse_feather_c6.menu.UploadSpeed.460800.macosx=460800
+epulse_feather_c6.menu.UploadSpeed.460800.upload.speed=460800
+epulse_feather_c6.menu.UploadSpeed.512000.windows=512000
+epulse_feather_c6.menu.UploadSpeed.512000.upload.speed=512000
+
+epulse_feather_c6.menu.DebugLevel.none=None
+epulse_feather_c6.menu.DebugLevel.none.build.code_debug=0
+epulse_feather_c6.menu.DebugLevel.error=Error
+epulse_feather_c6.menu.DebugLevel.error.build.code_debug=1
+epulse_feather_c6.menu.DebugLevel.warn=Warn
+epulse_feather_c6.menu.DebugLevel.warn.build.code_debug=2
+epulse_feather_c6.menu.DebugLevel.info=Info
+epulse_feather_c6.menu.DebugLevel.info.build.code_debug=3
+epulse_feather_c6.menu.DebugLevel.debug=Debug
+epulse_feather_c6.menu.DebugLevel.debug.build.code_debug=4
+epulse_feather_c6.menu.DebugLevel.verbose=Verbose
+epulse_feather_c6.menu.DebugLevel.verbose.build.code_debug=5
+
+epulse_feather_c6.menu.EraseFlash.none=Disabled
+epulse_feather_c6.menu.EraseFlash.none.upload.erase_cmd=
+epulse_feather_c6.menu.EraseFlash.all=Enabled
+epulse_feather_c6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+epulse_feather_c6.menu.ZigbeeMode.default=Disabled
+epulse_feather_c6.menu.ZigbeeMode.default.build.zigbee_mode=
+epulse_feather_c6.menu.ZigbeeMode.default.build.zigbee_libs=
+epulse_feather_c6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+epulse_feather_c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+epulse_feather_c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+epulse_feather_c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+epulse_feather_c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+epulse_feather_c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+Geekble_ESP32C3.name=Geekble Mini ESP32-C3
+
+Geekble_ESP32C3.bootloader.tool=esptool_py
+Geekble_ESP32C3.bootloader.tool.default=esptool_py
+
+Geekble_ESP32C3.upload.tool=esptool_py
+Geekble_ESP32C3.upload.tool.default=esptool_py
+Geekble_ESP32C3.upload.tool.network=esp_ota
+
+Geekble_ESP32C3.upload.maximum_size=1310720
+Geekble_ESP32C3.upload.maximum_data_size=327680
+Geekble_ESP32C3.upload.flags=
+Geekble_ESP32C3.upload.extra_flags=
+Geekble_ESP32C3.upload.use_1200bps_touch=false
+Geekble_ESP32C3.upload.wait_for_upload_port=false
+
+Geekble_ESP32C3.serial.disableDTR=true
+Geekble_ESP32C3.serial.disableRTS=true
+
+Geekble_ESP32C3.build.tarch=riscv32
+Geekble_ESP32C3.build.target=esp
+Geekble_ESP32C3.build.mcu=esp32c3
+Geekble_ESP32C3.build.core=esp32
+Geekble_ESP32C3.build.variant=Geekble_ESP32C3
+Geekble_ESP32C3.build.board=GEEKBLE_ESP32C3
+Geekble_ESP32C3.build.bootloader_addr=0x0
+
+Geekble_ESP32C3.build.cdc_on_boot=1
+Geekble_ESP32C3.build.f_cpu=160000000L
+Geekble_ESP32C3.build.flash_size=4MB
+Geekble_ESP32C3.build.flash_freq=80m
+Geekble_ESP32C3.build.flash_mode=dio
+Geekble_ESP32C3.build.boot=qio
+Geekble_ESP32C3.build.partitions=default
+Geekble_ESP32C3.build.defines=
+
+Geekble_ESP32C3.menu.CDCOnBoot.default=Enabled
+Geekble_ESP32C3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+Geekble_ESP32C3.menu.CDCOnBoot.cdc=Disabled
+Geekble_ESP32C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+Geekble_ESP32C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Geekble_ESP32C3.menu.PartitionScheme.default.build.partitions=default
+Geekble_ESP32C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Geekble_ESP32C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Geekble_ESP32C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Geekble_ESP32C3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Geekble_ESP32C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Geekble_ESP32C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Geekble_ESP32C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Geekble_ESP32C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Geekble_ESP32C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Geekble_ESP32C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Geekble_ESP32C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Geekble_ESP32C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Geekble_ESP32C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Geekble_ESP32C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Geekble_ESP32C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Geekble_ESP32C3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Geekble_ESP32C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+Geekble_ESP32C3.menu.CPUFreq.160=160MHz (WiFi) (Default)
+Geekble_ESP32C3.menu.CPUFreq.160.build.f_cpu=160000000L
+Geekble_ESP32C3.menu.CPUFreq.80=80MHz (WiFi)
+Geekble_ESP32C3.menu.CPUFreq.80.build.f_cpu=80000000L
+Geekble_ESP32C3.menu.CPUFreq.40=40MHz
+Geekble_ESP32C3.menu.CPUFreq.40.build.f_cpu=40000000L
+Geekble_ESP32C3.menu.CPUFreq.20=20MHz
+Geekble_ESP32C3.menu.CPUFreq.20.build.f_cpu=20000000L
+Geekble_ESP32C3.menu.CPUFreq.10=10MHz
+Geekble_ESP32C3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+Geekble_ESP32C3.menu.FlashMode.qio=QIO (Default)
+Geekble_ESP32C3.menu.FlashMode.qio.build.flash_mode=dio
+Geekble_ESP32C3.menu.FlashMode.qio.build.boot=qio
+Geekble_ESP32C3.menu.FlashMode.dio=DIO
+Geekble_ESP32C3.menu.FlashMode.dio.build.flash_mode=dio
+Geekble_ESP32C3.menu.FlashMode.dio.build.boot=dio
+Geekble_ESP32C3.menu.FlashMode.qout=QOUT
+Geekble_ESP32C3.menu.FlashMode.qout.build.flash_mode=dout
+Geekble_ESP32C3.menu.FlashMode.qout.build.boot=qout
+Geekble_ESP32C3.menu.FlashMode.dout=DOUT
+Geekble_ESP32C3.menu.FlashMode.dout.build.flash_mode=dout
+
+Geekble_ESP32C3.menu.FlashFreq.80=80MHz (Default)
+Geekble_ESP32C3.menu.FlashFreq.80.build.flash_freq=80m
+Geekble_ESP32C3.menu.FlashFreq.40=40MHz
+Geekble_ESP32C3.menu.FlashFreq.40.build.flash_freq=40m
+
+Geekble_ESP32C3.menu.FlashSize.4M=4MB (Default)
+Geekble_ESP32C3.menu.FlashSize.4M.build.flash_size=4MB
+Geekble_ESP32C3.menu.FlashSize.2M=2MB
+Geekble_ESP32C3.menu.FlashSize.2M.build.flash_size=2MB
+
+Geekble_ESP32C3.menu.UploadSpeed.921600=921600 (Default)
+Geekble_ESP32C3.menu.UploadSpeed.921600.upload.speed=921600
+Geekble_ESP32C3.menu.UploadSpeed.115200=115200
+Geekble_ESP32C3.menu.UploadSpeed.115200.upload.speed=115200
+Geekble_ESP32C3.menu.UploadSpeed.256000.windows=256000
+Geekble_ESP32C3.menu.UploadSpeed.256000.upload.speed=256000
+Geekble_ESP32C3.menu.UploadSpeed.230400.windows.upload.speed=256000
+Geekble_ESP32C3.menu.UploadSpeed.230400=230400
+Geekble_ESP32C3.menu.UploadSpeed.230400.upload.speed=230400
+Geekble_ESP32C3.menu.UploadSpeed.460800.linux=460800
+Geekble_ESP32C3.menu.UploadSpeed.460800.macosx=460800
+Geekble_ESP32C3.menu.UploadSpeed.460800.upload.speed=460800
+Geekble_ESP32C3.menu.UploadSpeed.512000.windows=512000
+Geekble_ESP32C3.menu.UploadSpeed.512000.upload.speed=512000
+
+Geekble_ESP32C3.menu.DebugLevel.none=None
+Geekble_ESP32C3.menu.DebugLevel.none.build.code_debug=0
+Geekble_ESP32C3.menu.DebugLevel.error=Error
+Geekble_ESP32C3.menu.DebugLevel.error.build.code_debug=1
+Geekble_ESP32C3.menu.DebugLevel.warn=Warn
+Geekble_ESP32C3.menu.DebugLevel.warn.build.code_debug=2
+Geekble_ESP32C3.menu.DebugLevel.info=Info
+Geekble_ESP32C3.menu.DebugLevel.info.build.code_debug=3
+Geekble_ESP32C3.menu.DebugLevel.debug=Debug
+Geekble_ESP32C3.menu.DebugLevel.debug.build.code_debug=4
+Geekble_ESP32C3.menu.DebugLevel.verbose=Verbose
+Geekble_ESP32C3.menu.DebugLevel.verbose.build.code_debug=5
+
+Geekble_ESP32C3.menu.EraseFlash.none=Disabled
+Geekble_ESP32C3.menu.EraseFlash.none.upload.erase_cmd=
+Geekble_ESP32C3.menu.EraseFlash.all=Enabled
+Geekble_ESP32C3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+Geekble_Nano_ESP32S3.name=Geekble nano ESP32-S3
+Geekble_Nano_ESP32S3.vid.0=0x303a
+Geekble_Nano_ESP32S3.pid.0= 0x82C5
+Geekble_Nano_ESP32S3.upload_port.0.vid=0x303a
+Geekble_Nano_ESP32S3.upload_port.0.pid= 0x82C5
+
+Geekble_Nano_ESP32S3.bootloader.tool=esptool_py
+Geekble_Nano_ESP32S3.bootloader.tool.default=esptool_py
+
+Geekble_Nano_ESP32S3.upload.tool=esptool_py
+Geekble_Nano_ESP32S3.upload.tool.default=esptool_py
+Geekble_Nano_ESP32S3.upload.tool.network=esp_ota
+
+Geekble_Nano_ESP32S3.upload.maximum_size=1310720
+Geekble_Nano_ESP32S3.upload.maximum_data_size=327680
+Geekble_Nano_ESP32S3.upload.speed=921600
+Geekble_Nano_ESP32S3.upload.flags=
+Geekble_Nano_ESP32S3.upload.extra_flags=
+Geekble_Nano_ESP32S3.upload.use_1200bps_touch=false
+Geekble_Nano_ESP32S3.upload.wait_for_upload_port=false
+
+Geekble_Nano_ESP32S3.serial.disableDTR=false
+Geekble_Nano_ESP32S3.serial.disableRTS=false
+
+Geekble_Nano_ESP32S3.build.tarch=xtensa
+Geekble_Nano_ESP32S3.build.bootloader_addr=0x0
+Geekble_Nano_ESP32S3.build.target=esp32s3
+Geekble_Nano_ESP32S3.build.mcu=esp32s3
+Geekble_Nano_ESP32S3.build.core=esp32
+Geekble_Nano_ESP32S3.build.variant=Geekble_Nano_ESP32S3
+Geekble_Nano_ESP32S3.build.board=GEEKBLE_NANO_ESP32S3
+
+Geekble_Nano_ESP32S3.build.usb_mode=1
+Geekble_Nano_ESP32S3.build.cdc_on_boot=1
+Geekble_Nano_ESP32S3.build.msc_on_boot=0
+Geekble_Nano_ESP32S3.build.dfu_on_boot=0
+Geekble_Nano_ESP32S3.build.f_cpu=240000000L
+Geekble_Nano_ESP32S3.build.flash_size=4MB
+Geekble_Nano_ESP32S3.build.flash_freq=80m
+Geekble_Nano_ESP32S3.build.flash_mode=dio
+Geekble_Nano_ESP32S3.build.boot=qio
+Geekble_Nano_ESP32S3.build.partitions=default
+Geekble_Nano_ESP32S3.build.defines=
+Geekble_Nano_ESP32S3.build.memory_type=qio_qspi
+Geekble_Nano_ESP32S3.build.loop_core=-DARDUINO_RUNNING_CORE=1
+Geekble_Nano_ESP32S3.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+Geekble_Nano_ESP32S3.menu.USBMode.default=USB-OTG (TinyUSB)
+Geekble_Nano_ESP32S3.menu.USBMode.default.build.usb_mode=0
+Geekble_Nano_ESP32S3.menu.USBMode.default.build.cdc_on_boot=1
+Geekble_Nano_ESP32S3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+Geekble_Nano_ESP32S3.menu.USBMode.hwcdc.build.usb_mode=1
+Geekble_Nano_ESP32S3.menu.USBMode.hwcdc.build.cdc_on_boot=1
+
+Geekble_Nano_ESP32S3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+Geekble_Nano_ESP32S3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+Geekble_Nano_ESP32S3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+Geekble_Nano_ESP32S3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.default.build.partitions=default
+Geekble_Nano_ESP32S3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Geekble_Nano_ESP32S3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Geekble_Nano_ESP32S3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Geekble_Nano_ESP32S3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Geekble_Nano_ESP32S3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Geekble_Nano_ESP32S3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+Geekble_Nano_ESP32S3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+Geekble_Nano_ESP32S3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+Geekble_Nano_ESP32S3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+Geekble_Nano_ESP32S3.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.otanofs.build.custom_partitions=ota_nofs_4MB
+Geekble_Nano_ESP32S3.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+Geekble_Nano_ESP32S3.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+Geekble_Nano_ESP32S3.menu.PartitionScheme.all_app.build.custom_partitions=max_app_4MB
+Geekble_Nano_ESP32S3.menu.PartitionScheme.all_app.upload.maximum_size=4063232
+Geekble_Nano_ESP32S3.menu.PartitionScheme.custom=Custom
+Geekble_Nano_ESP32S3.menu.PartitionScheme.custom.build.partitions=
+Geekble_Nano_ESP32S3.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+Geekble_Nano_ESP32S3.menu.DebugLevel.none=None
+Geekble_Nano_ESP32S3.menu.DebugLevel.none.build.code_debug=0
+Geekble_Nano_ESP32S3.menu.DebugLevel.error=Error
+Geekble_Nano_ESP32S3.menu.DebugLevel.error.build.code_debug=1
+Geekble_Nano_ESP32S3.menu.DebugLevel.warn=Warn
+Geekble_Nano_ESP32S3.menu.DebugLevel.warn.build.code_debug=2
+Geekble_Nano_ESP32S3.menu.DebugLevel.info=Info
+Geekble_Nano_ESP32S3.menu.DebugLevel.info.build.code_debug=3
+Geekble_Nano_ESP32S3.menu.DebugLevel.debug=Debug
+Geekble_Nano_ESP32S3.menu.DebugLevel.debug.build.code_debug=4
+Geekble_Nano_ESP32S3.menu.DebugLevel.verbose=Verbose
+Geekble_Nano_ESP32S3.menu.DebugLevel.verbose.build.code_debug=5
+
+Geekble_Nano_ESP32S3.menu.EraseFlash.none=Disabled
+Geekble_Nano_ESP32S3.menu.EraseFlash.none.upload.erase_cmd=
+Geekble_Nano_ESP32S3.menu.EraseFlash.all=Enabled
+Geekble_Nano_ESP32S3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_zero.name=Waveshare ESP32-S3-Zero
+waveshare_esp32_s3_zero.vid.0=0x303a
+waveshare_esp32_s3_zero.pid.0=0x822B
+waveshare_esp32_s3_zero.upload_port.0.vid=0x303a
+waveshare_esp32_s3_zero.upload_port.0.pid=0x822B
+
+waveshare_esp32_s3_zero.bootloader.tool=esptool_py
+waveshare_esp32_s3_zero.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_zero.upload.tool=esptool_py
+waveshare_esp32_s3_zero.upload.tool.default=esptool_py
+waveshare_esp32_s3_zero.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_zero.upload.maximum_size=1310720
+
+waveshare_esp32_s3_zero.upload.maximum_data_size=327680
+waveshare_esp32_s3_zero.upload.flags=
+waveshare_esp32_s3_zero.upload.extra_flags=
+waveshare_esp32_s3_zero.upload.use_1200bps_touch=false
+waveshare_esp32_s3_zero.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_zero.serial.disableDTR=false
+waveshare_esp32_s3_zero.serial.disableRTS=false
+
+waveshare_esp32_s3_zero.build.tarch=xtensa
+waveshare_esp32_s3_zero.build.bootloader_addr=0x0
+waveshare_esp32_s3_zero.build.target=esp32s3
+waveshare_esp32_s3_zero.build.mcu=esp32s3
+waveshare_esp32_s3_zero.build.core=esp32
+waveshare_esp32_s3_zero.build.variant=waveshare_esp32_s3_zero
+waveshare_esp32_s3_zero.build.board=WAVESHARE_ESP32_S3_ZERO
+
+waveshare_esp32_s3_zero.build.usb_mode=1
+waveshare_esp32_s3_zero.build.cdc_on_boot=0
+waveshare_esp32_s3_zero.build.msc_on_boot=0
+waveshare_esp32_s3_zero.build.dfu_on_boot=0
+waveshare_esp32_s3_zero.build.f_cpu=240000000L
+waveshare_esp32_s3_zero.build.flash_size=4MB
+waveshare_esp32_s3_zero.build.flash_freq=80m
+waveshare_esp32_s3_zero.build.flash_mode=dio
+waveshare_esp32_s3_zero.build.boot=qio
+waveshare_esp32_s3_zero.build.boot_freq=80m
+waveshare_esp32_s3_zero.build.partitions=default
+waveshare_esp32_s3_zero.build.defines=
+waveshare_esp32_s3_zero.build.loop_core=
+waveshare_esp32_s3_zero.build.event_core=
+waveshare_esp32_s3_zero.build.psram_type=qspi
+waveshare_esp32_s3_zero.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_zero.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_zero.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_zero.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_zero.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_zero.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_zero.menu.PSRAM.enabled.build.psram_type=qspi
+
+waveshare_esp32_s3_zero.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_zero.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_zero.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_zero.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_zero.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_zero.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_zero.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_zero.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_zero.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_zero.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_zero.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_zero.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_zero.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_zero.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_zero.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_zero.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_zero.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_zero.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_zero.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_zero.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_zero.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_zero.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_zero.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_zero.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_zero.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_zero.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_zero.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_zero.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_zero.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_zero.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_zero.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_zero.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_zero.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_zero.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_zero.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_zero.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_zero.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_zero.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_zero.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_zero.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_zero.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_zero.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_zero.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_zero.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_zero.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_zero.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_zero.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_zero.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_zero.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_zero.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_zero.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_zero.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_zero.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_zero.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_zero.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_zero.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_zero.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_zero.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+waveshare_esp32_s3_zero.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_zero.menu.PartitionScheme.otanofs.build.custom_partitions=ota_nofs_4MB
+waveshare_esp32_s3_zero.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_zero.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_zero.menu.PartitionScheme.all_app.build.custom_partitions=max_app_4MB
+waveshare_esp32_s3_zero.menu.PartitionScheme.all_app.upload.maximum_size=4063232
+
+waveshare_esp32_s3_zero.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_zero.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_zero.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_zero.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_zero.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_zero.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_zero.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_zero.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_zero.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_zero.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_zero.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_zero.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_zero.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_zero.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_zero.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_zero.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_zero.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_zero.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_zero.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_zero.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_zero.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_zero.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_zero.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_zero.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_zero.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_zero.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_zero.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_zero.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_zero.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_zero.menu.DebugLevel.none=None
+waveshare_esp32_s3_zero.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_zero.menu.DebugLevel.error=Error
+waveshare_esp32_s3_zero.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_zero.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_zero.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_zero.menu.DebugLevel.info=Info
+waveshare_esp32_s3_zero.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_zero.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_zero.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_zero.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_zero.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_zero.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_zero.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_zero.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_zero.menu.EraseFlash.all.upload.erase_cmd=-e
+
+######################################################
+
+ws_esp32_s3_matrix.name=Waveshare ESP32-S3-Matrix
+ws_esp32_s3_matrix.vid.0=0x303a
+ws_esp32_s3_matrix.pid.0=0x81FB
+ws_esp32_s3_matrix.upload_port.0.vid=0x303a
+ws_esp32_s3_matrix.upload_port.0.pid=0x81FB
+
+ws_esp32_s3_matrix.bootloader.tool=esptool_py
+ws_esp32_s3_matrix.bootloader.tool.default=esptool_py
+
+ws_esp32_s3_matrix.upload.tool=esptool_py
+ws_esp32_s3_matrix.upload.tool.default=esptool_py
+ws_esp32_s3_matrix.upload.tool.network=esp_ota
+
+ws_esp32_s3_matrix.upload.maximum_size=1310720
+
+ws_esp32_s3_matrix.upload.maximum_data_size=327680
+ws_esp32_s3_matrix.upload.flags=
+ws_esp32_s3_matrix.upload.extra_flags=
+ws_esp32_s3_matrix.upload.use_1200bps_touch=false
+ws_esp32_s3_matrix.upload.wait_for_upload_port=false
+
+ws_esp32_s3_matrix.serial.disableDTR=false
+ws_esp32_s3_matrix.serial.disableRTS=false
+
+ws_esp32_s3_matrix.build.tarch=xtensa
+ws_esp32_s3_matrix.build.bootloader_addr=0x0
+ws_esp32_s3_matrix.build.target=esp32s3
+ws_esp32_s3_matrix.build.mcu=esp32s3
+ws_esp32_s3_matrix.build.core=esp32
+ws_esp32_s3_matrix.build.variant=ws_esp32_s3_matrix
+ws_esp32_s3_matrix.build.board=WS_ESP32_S3_MATRIX
+
+ws_esp32_s3_matrix.build.usb_mode=1
+ws_esp32_s3_matrix.build.cdc_on_boot=0
+ws_esp32_s3_matrix.build.msc_on_boot=0
+ws_esp32_s3_matrix.build.dfu_on_boot=0
+ws_esp32_s3_matrix.build.f_cpu=240000000L
+ws_esp32_s3_matrix.build.flash_size=4MB
+ws_esp32_s3_matrix.build.flash_freq=80m
+ws_esp32_s3_matrix.build.flash_mode=dio
+ws_esp32_s3_matrix.build.boot=qio
+ws_esp32_s3_matrix.build.boot_freq=80m
+ws_esp32_s3_matrix.build.partitions=default
+ws_esp32_s3_matrix.build.defines=
+ws_esp32_s3_matrix.build.loop_core=
+ws_esp32_s3_matrix.build.event_core=
+ws_esp32_s3_matrix.build.psram_type=qspi
+ws_esp32_s3_matrix.build.memory_type={build.boot}_{build.psram_type}
+
+ws_esp32_s3_matrix.menu.PSRAM.disabled=Disabled
+ws_esp32_s3_matrix.menu.PSRAM.disabled.build.defines=
+ws_esp32_s3_matrix.menu.PSRAM.disabled.build.psram_type=qspi
+ws_esp32_s3_matrix.menu.PSRAM.enabled=Enabled
+ws_esp32_s3_matrix.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+ws_esp32_s3_matrix.menu.PSRAM.enabled.build.psram_type=qspi
+
+ws_esp32_s3_matrix.menu.FlashMode.qio=QIO 80MHz
+ws_esp32_s3_matrix.menu.FlashMode.qio.build.flash_mode=dio
+ws_esp32_s3_matrix.menu.FlashMode.qio.build.boot=qio
+ws_esp32_s3_matrix.menu.FlashMode.qio.build.boot_freq=80m
+ws_esp32_s3_matrix.menu.FlashMode.qio.build.flash_freq=80m
+ws_esp32_s3_matrix.menu.FlashMode.qio120=QIO 120MHz
+ws_esp32_s3_matrix.menu.FlashMode.qio120.build.flash_mode=dio
+ws_esp32_s3_matrix.menu.FlashMode.qio120.build.boot=qio
+ws_esp32_s3_matrix.menu.FlashMode.qio120.build.boot_freq=120m
+ws_esp32_s3_matrix.menu.FlashMode.qio120.build.flash_freq=80m
+
+ws_esp32_s3_matrix.menu.FlashSize.4M=4MB (32Mb)
+ws_esp32_s3_matrix.menu.FlashSize.4M.build.flash_size=4MB
+
+ws_esp32_s3_matrix.menu.LoopCore.1=Core 1
+ws_esp32_s3_matrix.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+ws_esp32_s3_matrix.menu.LoopCore.0=Core 0
+ws_esp32_s3_matrix.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+ws_esp32_s3_matrix.menu.EventsCore.1=Core 1
+ws_esp32_s3_matrix.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+ws_esp32_s3_matrix.menu.EventsCore.0=Core 0
+ws_esp32_s3_matrix.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+ws_esp32_s3_matrix.menu.USBMode.hwcdc=Hardware CDC and JTAG
+ws_esp32_s3_matrix.menu.USBMode.hwcdc.build.usb_mode=1
+ws_esp32_s3_matrix.menu.USBMode.default=USB-OTG (TinyUSB)
+ws_esp32_s3_matrix.menu.USBMode.default.build.usb_mode=0
+
+ws_esp32_s3_matrix.menu.CDCOnBoot.default=Disabled
+ws_esp32_s3_matrix.menu.CDCOnBoot.default.build.cdc_on_boot=0
+ws_esp32_s3_matrix.menu.CDCOnBoot.cdc=Enabled
+ws_esp32_s3_matrix.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+ws_esp32_s3_matrix.menu.MSCOnBoot.default=Disabled
+ws_esp32_s3_matrix.menu.MSCOnBoot.default.build.msc_on_boot=0
+ws_esp32_s3_matrix.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+ws_esp32_s3_matrix.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+ws_esp32_s3_matrix.menu.DFUOnBoot.default=Disabled
+ws_esp32_s3_matrix.menu.DFUOnBoot.default.build.dfu_on_boot=0
+ws_esp32_s3_matrix.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+ws_esp32_s3_matrix.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+ws_esp32_s3_matrix.menu.UploadMode.default=UART0 / Hardware CDC
+ws_esp32_s3_matrix.menu.UploadMode.default.upload.use_1200bps_touch=false
+ws_esp32_s3_matrix.menu.UploadMode.default.upload.wait_for_upload_port=false
+ws_esp32_s3_matrix.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+ws_esp32_s3_matrix.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+ws_esp32_s3_matrix.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+ws_esp32_s3_matrix.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+ws_esp32_s3_matrix.menu.PartitionScheme.default.build.partitions=default
+ws_esp32_s3_matrix.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+ws_esp32_s3_matrix.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+ws_esp32_s3_matrix.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+ws_esp32_s3_matrix.menu.PartitionScheme.no_ota.build.partitions=no_ota
+ws_esp32_s3_matrix.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+ws_esp32_s3_matrix.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+ws_esp32_s3_matrix.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+ws_esp32_s3_matrix.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+ws_esp32_s3_matrix.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+ws_esp32_s3_matrix.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+ws_esp32_s3_matrix.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+ws_esp32_s3_matrix.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+ws_esp32_s3_matrix.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+ws_esp32_s3_matrix.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+ws_esp32_s3_matrix.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+ws_esp32_s3_matrix.menu.PartitionScheme.huge_app.build.partitions=huge_app
+ws_esp32_s3_matrix.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+ws_esp32_s3_matrix.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+ws_esp32_s3_matrix.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+ws_esp32_s3_matrix.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker=RainMaker 4MB
+ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+ws_esp32_s3_matrix.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+ws_esp32_s3_matrix.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+ws_esp32_s3_matrix.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+ws_esp32_s3_matrix.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+ws_esp32_s3_matrix.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+ws_esp32_s3_matrix.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+ws_esp32_s3_matrix.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+ws_esp32_s3_matrix.menu.PartitionScheme.custom=Custom
+ws_esp32_s3_matrix.menu.PartitionScheme.custom.build.partitions=
+ws_esp32_s3_matrix.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+ws_esp32_s3_matrix.menu.CPUFreq.240=240MHz (WiFi)
+ws_esp32_s3_matrix.menu.CPUFreq.240.build.f_cpu=240000000L
+ws_esp32_s3_matrix.menu.CPUFreq.160=160MHz (WiFi)
+ws_esp32_s3_matrix.menu.CPUFreq.160.build.f_cpu=160000000L
+ws_esp32_s3_matrix.menu.CPUFreq.80=80MHz (WiFi)
+ws_esp32_s3_matrix.menu.CPUFreq.80.build.f_cpu=80000000L
+ws_esp32_s3_matrix.menu.CPUFreq.40=40MHz
+ws_esp32_s3_matrix.menu.CPUFreq.40.build.f_cpu=40000000L
+ws_esp32_s3_matrix.menu.CPUFreq.20=20MHz
+ws_esp32_s3_matrix.menu.CPUFreq.20.build.f_cpu=20000000L
+ws_esp32_s3_matrix.menu.CPUFreq.10=10MHz
+ws_esp32_s3_matrix.menu.CPUFreq.10.build.f_cpu=10000000L
+
+ws_esp32_s3_matrix.menu.UploadSpeed.921600=921600
+ws_esp32_s3_matrix.menu.UploadSpeed.921600.upload.speed=921600
+ws_esp32_s3_matrix.menu.UploadSpeed.115200=115200
+ws_esp32_s3_matrix.menu.UploadSpeed.115200.upload.speed=115200
+ws_esp32_s3_matrix.menu.UploadSpeed.256000.windows=256000
+ws_esp32_s3_matrix.menu.UploadSpeed.256000.upload.speed=256000
+ws_esp32_s3_matrix.menu.UploadSpeed.230400.windows.upload.speed=256000
+ws_esp32_s3_matrix.menu.UploadSpeed.230400=230400
+ws_esp32_s3_matrix.menu.UploadSpeed.230400.upload.speed=230400
+ws_esp32_s3_matrix.menu.UploadSpeed.460800.linux=460800
+ws_esp32_s3_matrix.menu.UploadSpeed.460800.macosx=460800
+ws_esp32_s3_matrix.menu.UploadSpeed.460800.upload.speed=460800
+ws_esp32_s3_matrix.menu.UploadSpeed.512000.windows=512000
+ws_esp32_s3_matrix.menu.UploadSpeed.512000.upload.speed=512000
+
+ws_esp32_s3_matrix.menu.DebugLevel.none=None
+ws_esp32_s3_matrix.menu.DebugLevel.none.build.code_debug=0
+ws_esp32_s3_matrix.menu.DebugLevel.error=Error
+ws_esp32_s3_matrix.menu.DebugLevel.error.build.code_debug=1
+ws_esp32_s3_matrix.menu.DebugLevel.warn=Warn
+ws_esp32_s3_matrix.menu.DebugLevel.warn.build.code_debug=2
+ws_esp32_s3_matrix.menu.DebugLevel.info=Info
+ws_esp32_s3_matrix.menu.DebugLevel.info.build.code_debug=3
+ws_esp32_s3_matrix.menu.DebugLevel.debug=Debug
+ws_esp32_s3_matrix.menu.DebugLevel.debug.build.code_debug=4
+ws_esp32_s3_matrix.menu.DebugLevel.verbose=Verbose
+ws_esp32_s3_matrix.menu.DebugLevel.verbose.build.code_debug=5
+
+ws_esp32_s3_matrix.menu.EraseFlash.none=Disabled
+ws_esp32_s3_matrix.menu.EraseFlash.none.upload.erase_cmd=
+ws_esp32_s3_matrix.menu.EraseFlash.all=Enabled
+ws_esp32_s3_matrix.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_169.name=Waveshare ESP32-S3-Touch-LCD-1.69
+waveshare_esp32_s3_touch_lcd_169.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_169.pid.0=0x821E
+waveshare_esp32_s3_touch_lcd_169.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_169.upload_port.0.pid=0x821E
+
+waveshare_esp32_s3_touch_lcd_169.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_169.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_169.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_169.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_169.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_169.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_lcd_169.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_169.upload.flags=
+waveshare_esp32_s3_touch_lcd_169.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_169.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_169.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_169.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_169.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_169.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_169.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_169.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_169.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_169.build.core=esp32
+waveshare_esp32_s3_touch_lcd_169.build.variant=waveshare_esp32_s3_touch_lcd_169
+waveshare_esp32_s3_touch_lcd_169.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_169
+
+waveshare_esp32_s3_touch_lcd_169.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_169.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_169.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_169.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_169.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_169.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_169.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_169.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_169.build.boot=qio
+waveshare_esp32_s3_touch_lcd_169.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_169.build.partitions=default
+waveshare_esp32_s3_touch_lcd_169.build.defines=
+waveshare_esp32_s3_touch_lcd_169.build.loop_core=
+waveshare_esp32_s3_touch_lcd_169.build.event_core=
+waveshare_esp32_s3_touch_lcd_169.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_169.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_169.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_169.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_169.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_169.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_169.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_169.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_169.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_169.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_169.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_169.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_169.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_169.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_169.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_169.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_169.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_169.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_169.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_169.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_169.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_169.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_169.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_169.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_169.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_169.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_169.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_169.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_169.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_169.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_169.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_169.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_169.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_169.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_169.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_169.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_169.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_amoled_18.name=Waveshare ESP32-S3-Touch-AMOLED-1.8
+waveshare_esp32_s3_touch_amoled_18.vid.0=0x303a
+waveshare_esp32_s3_touch_amoled_18.pid.0=0x8255
+waveshare_esp32_s3_touch_amoled_18.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_amoled_18.upload_port.0.pid=0x8255
+
+waveshare_esp32_s3_touch_amoled_18.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_18.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_amoled_18.upload.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_18.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_amoled_18.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_amoled_18.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_amoled_18.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_amoled_18.upload.flags=
+waveshare_esp32_s3_touch_amoled_18.upload.extra_flags=
+waveshare_esp32_s3_touch_amoled_18.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_18.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_amoled_18.serial.disableDTR=false
+waveshare_esp32_s3_touch_amoled_18.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_amoled_18.build.tarch=xtensa
+waveshare_esp32_s3_touch_amoled_18.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_amoled_18.build.target=esp32s3
+waveshare_esp32_s3_touch_amoled_18.build.mcu=esp32s3
+waveshare_esp32_s3_touch_amoled_18.build.core=esp32
+waveshare_esp32_s3_touch_amoled_18.build.variant=waveshare_esp32_s3_touch_amoled_18
+waveshare_esp32_s3_touch_amoled_18.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_18
+
+waveshare_esp32_s3_touch_amoled_18.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_18.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_18.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_18.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_18.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_18.build.flash_size=16MB
+waveshare_esp32_s3_touch_amoled_18.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_18.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_18.build.boot=qio
+waveshare_esp32_s3_touch_amoled_18.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_18.build.partitions=default
+waveshare_esp32_s3_touch_amoled_18.build.defines=
+waveshare_esp32_s3_touch_amoled_18.build.loop_core=
+waveshare_esp32_s3_touch_amoled_18.build.event_core=
+waveshare_esp32_s3_touch_amoled_18.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_18.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_amoled_18.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_amoled_18.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_amoled_18.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_18.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_18.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_18.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_18.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_18.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_18.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_18.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_18.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_amoled_18.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_18.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_amoled_18.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_amoled_18.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_18.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_18.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_amoled_18.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_18.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_18.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_18.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_18.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_18.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_18.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_18.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_18.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_amoled_18.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_amoled_18.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_amoled_18.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_amoled_18.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_amoled_18.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_amoled_18.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_amoled_18.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_amoled_18.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_amoled_18.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_lcd_169.name=Waveshare ESP32-S3-LCD-1.69
+waveshare_esp32_s3_lcd_169.vid.0=0x303a
+waveshare_esp32_s3_lcd_169.pid.0=0x8221
+waveshare_esp32_s3_lcd_169.upload_port.0.vid=0x303a
+waveshare_esp32_s3_lcd_169.upload_port.0.pid=0x8221
+
+waveshare_esp32_s3_lcd_169.bootloader.tool=esptool_py
+waveshare_esp32_s3_lcd_169.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_lcd_169.upload.tool=esptool_py
+waveshare_esp32_s3_lcd_169.upload.tool.default=esptool_py
+waveshare_esp32_s3_lcd_169.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_lcd_169.upload.maximum_size=1310720
+
+waveshare_esp32_s3_lcd_169.upload.maximum_data_size=327680
+waveshare_esp32_s3_lcd_169.upload.flags=
+waveshare_esp32_s3_lcd_169.upload.extra_flags=
+waveshare_esp32_s3_lcd_169.upload.use_1200bps_touch=false
+waveshare_esp32_s3_lcd_169.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_lcd_169.serial.disableDTR=false
+waveshare_esp32_s3_lcd_169.serial.disableRTS=false
+
+waveshare_esp32_s3_lcd_169.build.tarch=xtensa
+waveshare_esp32_s3_lcd_169.build.bootloader_addr=0x0
+waveshare_esp32_s3_lcd_169.build.target=esp32s3
+waveshare_esp32_s3_lcd_169.build.mcu=esp32s3
+waveshare_esp32_s3_lcd_169.build.core=esp32
+waveshare_esp32_s3_lcd_169.build.variant=waveshare_esp32_s3_lcd_169
+waveshare_esp32_s3_lcd_169.build.board=WAVESHARE_ESP32_S3_LCD_169
+
+waveshare_esp32_s3_lcd_169.build.usb_mode=1
+waveshare_esp32_s3_lcd_169.build.cdc_on_boot=0
+waveshare_esp32_s3_lcd_169.build.msc_on_boot=0
+waveshare_esp32_s3_lcd_169.build.dfu_on_boot=0
+waveshare_esp32_s3_lcd_169.build.f_cpu=240000000L
+waveshare_esp32_s3_lcd_169.build.flash_size=16MB
+waveshare_esp32_s3_lcd_169.build.flash_freq=80m
+waveshare_esp32_s3_lcd_169.build.flash_mode=dio
+waveshare_esp32_s3_lcd_169.build.boot=qio
+waveshare_esp32_s3_lcd_169.build.boot_freq=80m
+waveshare_esp32_s3_lcd_169.build.partitions=default
+waveshare_esp32_s3_lcd_169.build.defines=
+waveshare_esp32_s3_lcd_169.build.loop_core=
+waveshare_esp32_s3_lcd_169.build.event_core=
+waveshare_esp32_s3_lcd_169.build.psram_type=qspi
+waveshare_esp32_s3_lcd_169.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_lcd_169.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_lcd_169.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_lcd_169.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_lcd_169.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_lcd_169.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_lcd_169.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_lcd_169.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_lcd_169.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_lcd_169.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_lcd_169.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_lcd_169.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_lcd_169.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_lcd_169.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_lcd_169.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_lcd_169.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_lcd_169.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_lcd_169.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_lcd_169.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_lcd_169.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_lcd_169.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_169.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_lcd_169.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_lcd_169.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_lcd_169.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_169.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_lcd_169.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_lcd_169.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_lcd_169.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_169.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_lcd_169.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_lcd_169.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_lcd_169.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_lcd_169.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_lcd_169.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_lcd_169.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_lcd_169.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_lcd_169.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_lcd_169.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_lcd_169.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_lcd_169.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.none=None
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.error=Error
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.info=Info
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_lcd_169.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_lcd_169.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_lcd_169.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_lcd_169.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_lcd_169.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32s3_touch_lcd_128.name=Waveshare ESP32S3 Touch LCD 128
+
+waveshare_esp32s3_touch_lcd_128.upload.tool=esptool_py
+waveshare_esp32s3_touch_lcd_128.upload.tool.default=esptool_py
+waveshare_esp32s3_touch_lcd_128.upload.tool.network=esp_ota
+waveshare_esp32s3_touch_lcd_128.upload.maximum_size=16777216
+waveshare_esp32s3_touch_lcd_128.upload.maximum_data_size=327680
+waveshare_esp32s3_touch_lcd_128.upload.wait_for_upload_port=false
+waveshare_esp32s3_touch_lcd_128.upload.speed=460800
+waveshare_esp32s3_touch_lcd_128.upload.flags=
+waveshare_esp32s3_touch_lcd_128.upload.extra_flags=
+
+waveshare_esp32s3_touch_lcd_128.bootloader.tool=esptool_py
+waveshare_esp32s3_touch_lcd_128.bootloader.tool.default=esptool_py
+
+waveshare_esp32s3_touch_lcd_128.serial.disableDTR=true
+waveshare_esp32s3_touch_lcd_128.serial.disableRTS=true
+
+waveshare_esp32s3_touch_lcd_128.build.tarch=xtensa
+waveshare_esp32s3_touch_lcd_128.build.bootloader_addr=0x0
+waveshare_esp32s3_touch_lcd_128.build.mcu=esp32s3
+waveshare_esp32s3_touch_lcd_128.build.core=esp32
+waveshare_esp32s3_touch_lcd_128.build.target=esp32s3
+waveshare_esp32s3_touch_lcd_128.build.variant=waveshare_esp32s3_touch_lcd_128
+waveshare_esp32s3_touch_lcd_128.build.board=WAVESHARE_ESP32S3_TOUCH_LCD_128
+
+waveshare_esp32s3_touch_lcd_128.build.usb_mode=1
+waveshare_esp32s3_touch_lcd_128.build.cdc_on_boot=1
+waveshare_esp32s3_touch_lcd_128.build.msc_on_boot=0
+waveshare_esp32s3_touch_lcd_128.build.dfu_on_boot=0
+
+waveshare_esp32s3_touch_lcd_128.build.f_cpu=240000000L
+waveshare_esp32s3_touch_lcd_128.build.flash_size=16MB
+waveshare_esp32s3_touch_lcd_128.build.flash_freq=80m
+waveshare_esp32s3_touch_lcd_128.build.flash_mode=dio
+waveshare_esp32s3_touch_lcd_128.build.boot=dio
+waveshare_esp32s3_touch_lcd_128.build.partitions=default
+
+waveshare_esp32s3_touch_lcd_128.menu.PSRAM.disabled=Disabled
+waveshare_esp32s3_touch_lcd_128.menu.PSRAM.disabled.build.defines=
+waveshare_esp32s3_touch_lcd_128.menu.PSRAM.enabled=Enabled
+waveshare_esp32s3_touch_lcd_128.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32s3_touch_lcd_128.menu.PSRAM.enabled.build.psram_type=qspi
+
+waveshare_esp32s3_touch_lcd_128.menu.LoopCore.1=Core 1
+waveshare_esp32s3_touch_lcd_128.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32s3_touch_lcd_128.menu.LoopCore.0=Core 0
+waveshare_esp32s3_touch_lcd_128.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32s3_touch_lcd_128.menu.EventsCore.1=Core 1
+waveshare_esp32s3_touch_lcd_128.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32s3_touch_lcd_128.menu.EventsCore.0=Core 0
+waveshare_esp32s3_touch_lcd_128.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32s3_touch_lcd_128.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.240=240MHz (WiFi/BT)
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.160=160MHz (WiFi/BT)
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.80=80MHz (WiFi/BT)
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.40=40MHz (40MHz XTAL)
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.26=26MHz (26MHz XTAL)
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.26.build.f_cpu=26000000L
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.20=20MHz (40MHz XTAL)
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.13=13MHz (26MHz XTAL)
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.13.build.f_cpu=13000000L
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.10=10MHz (40MHz XTAL)
+waveshare_esp32s3_touch_lcd_128.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32s3_touch_lcd_128.menu.FlashMode.qio=QIO
+waveshare_esp32s3_touch_lcd_128.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32s3_touch_lcd_128.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32s3_touch_lcd_128.menu.FlashMode.dio=DIO
+waveshare_esp32s3_touch_lcd_128.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32s3_touch_lcd_128.menu.FlashMode.dio.build.boot=dio
+
+waveshare_esp32s3_touch_lcd_128.menu.FlashFreq.80=80MHz
+waveshare_esp32s3_touch_lcd_128.menu.FlashFreq.80.build.flash_freq=80m
+waveshare_esp32s3_touch_lcd_128.menu.FlashFreq.40=40MHz
+waveshare_esp32s3_touch_lcd_128.menu.FlashFreq.40.build.flash_freq=40m
+
+waveshare_esp32s3_touch_lcd_128.menu.FlashSize.16M=16MB (128Mb)
+waveshare_esp32s3_touch_lcd_128.menu.FlashSize.16M.build.flash_size=16MB
+
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.921600=921600
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.115200=115200
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.230400=230400
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32s3_touch_lcd_128.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.none=None
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.error=Error
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.warn=Warn
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.info=Info
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.debug=Debug
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.verbose=Verbose
+waveshare_esp32s3_touch_lcd_128.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32s3_touch_lcd_128.menu.EraseFlash.none=Disabled
+waveshare_esp32s3_touch_lcd_128.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32s3_touch_lcd_128.menu.EraseFlash.all=Enabled
+waveshare_esp32s3_touch_lcd_128.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+weact_studio_esp32c3.name=WeAct Studio ESP32C3
+
+weact_studio_esp32c3.upload.tool=esptool_py
+weact_studio_esp32c3.upload.tool.default=esptool_py
+weact_studio_esp32c3.upload.tool.network=esp_ota
+weact_studio_esp32c3.upload.maximum_size=1310720
+weact_studio_esp32c3.upload.maximum_data_size=327680
+weact_studio_esp32c3.upload.flags=
+weact_studio_esp32c3.upload.extra_flags=
+weact_studio_esp32c3.upload.use_1200bps_touch=false
+weact_studio_esp32c3.upload.wait_for_upload_port=false
+
+weact_studio_esp32c3.serial.disableDTR=false
+weact_studio_esp32c3.serial.disableRTS=false
+
+weact_studio_esp32c3.build.tarch=riscv32
+weact_studio_esp32c3.build.target=esp
+weact_studio_esp32c3.build.mcu=esp32c3
+weact_studio_esp32c3.build.core=esp32
+weact_studio_esp32c3.build.variant=weact_studio_esp32c3
+weact_studio_esp32c3.build.board=WEACT_STUDIO_ESP32C3
+weact_studio_esp32c3.build.bootloader_addr=0x0
+
+weact_studio_esp32c3.build.usb_mode=1
+weact_studio_esp32c3.build.cdc_on_boot=1
+weact_studio_esp32c3.build.f_cpu=160000000L
+weact_studio_esp32c3.build.flash_size=4MB
+weact_studio_esp32c3.build.flash_freq=80m
+weact_studio_esp32c3.build.flash_mode=qio
+weact_studio_esp32c3.build.boot=qio
+weact_studio_esp32c3.build.partitions=default
+weact_studio_esp32c3.build.defines=
+
+weact_studio_esp32c3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+weact_studio_esp32c3.menu.USBMode.hwcdc.build.usb_mode=1
+weact_studio_esp32c3.menu.USBMode.default=USB-OTG
+weact_studio_esp32c3.menu.USBMode.default.build.usb_mode=0
+
+weact_studio_esp32c3.menu.JTAGAdapter.default=Disabled
+weact_studio_esp32c3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+weact_studio_esp32c3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+weact_studio_esp32c3.menu.JTAGAdapter.builtin.build.openocdscript=esp32c3-builtin.cfg
+weact_studio_esp32c3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+weact_studio_esp32c3.menu.JTAGAdapter.external=FTDI Adapter
+weact_studio_esp32c3.menu.JTAGAdapter.external.build.openocdscript=esp32c3-ftdi.cfg
+weact_studio_esp32c3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+weact_studio_esp32c3.menu.JTAGAdapter.bridge=ESP USB Bridge
+weact_studio_esp32c3.menu.JTAGAdapter.bridge.build.openocdscript=esp32c3-bridge.cfg
+weact_studio_esp32c3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+weact_studio_esp32c3.menu.CDCOnBoot.default=Enabled
+weact_studio_esp32c3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+weact_studio_esp32c3.menu.CDCOnBoot.cdc=Enabled
+weact_studio_esp32c3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+weact_studio_esp32c3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+weact_studio_esp32c3.menu.PartitionScheme.default.build.partitions=default
+weact_studio_esp32c3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+weact_studio_esp32c3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+weact_studio_esp32c3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+weact_studio_esp32c3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+weact_studio_esp32c3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+weact_studio_esp32c3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+weact_studio_esp32c3.menu.PartitionScheme.minimal.build.partitions=minimal
+weact_studio_esp32c3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+weact_studio_esp32c3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+weact_studio_esp32c3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+weact_studio_esp32c3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+weact_studio_esp32c3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+weact_studio_esp32c3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+weact_studio_esp32c3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+weact_studio_esp32c3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+weact_studio_esp32c3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+weact_studio_esp32c3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+weact_studio_esp32c3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+weact_studio_esp32c3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+weact_studio_esp32c3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+weact_studio_esp32c3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+weact_studio_esp32c3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+weact_studio_esp32c3.menu.CPUFreq.160=160MHz (WiFi)
+weact_studio_esp32c3.menu.CPUFreq.160.build.f_cpu=160000000L
+weact_studio_esp32c3.menu.CPUFreq.80=80MHz (WiFi)
+weact_studio_esp32c3.menu.CPUFreq.80.build.f_cpu=80000000L
+weact_studio_esp32c3.menu.CPUFreq.40=40MHz
+weact_studio_esp32c3.menu.CPUFreq.40.build.f_cpu=40000000L
+weact_studio_esp32c3.menu.CPUFreq.20=20MHz
+weact_studio_esp32c3.menu.CPUFreq.20.build.f_cpu=20000000L
+weact_studio_esp32c3.menu.CPUFreq.10=10MHz
+weact_studio_esp32c3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+weact_studio_esp32c3.menu.FlashMode.qio=QIO
+weact_studio_esp32c3.menu.FlashMode.qio.build.flash_mode=dio
+weact_studio_esp32c3.menu.FlashMode.qio.build.boot=qio
+weact_studio_esp32c3.menu.FlashMode.dio=DIO
+weact_studio_esp32c3.menu.FlashMode.dio.build.flash_mode=dio
+weact_studio_esp32c3.menu.FlashMode.dio.build.boot=dio
+
+weact_studio_esp32c3.menu.FlashFreq.80=80MHz
+weact_studio_esp32c3.menu.FlashFreq.80.build.flash_freq=80m
+weact_studio_esp32c3.menu.FlashFreq.40=40MHz
+weact_studio_esp32c3.menu.FlashFreq.40.build.flash_freq=40m
+
+weact_studio_esp32c3.menu.UploadSpeed.921600=921600
+weact_studio_esp32c3.menu.UploadSpeed.921600.upload.speed=921600
+weact_studio_esp32c3.menu.UploadSpeed.115200=115200
+weact_studio_esp32c3.menu.UploadSpeed.115200.upload.speed=115200
+weact_studio_esp32c3.menu.UploadSpeed.256000.windows=256000
+weact_studio_esp32c3.menu.UploadSpeed.256000.upload.speed=256000
+weact_studio_esp32c3.menu.UploadSpeed.230400.windows.upload.speed=256000
+weact_studio_esp32c3.menu.UploadSpeed.230400=230400
+weact_studio_esp32c3.menu.UploadSpeed.230400.upload.speed=230400
+weact_studio_esp32c3.menu.UploadSpeed.460800.linux=460800
+weact_studio_esp32c3.menu.UploadSpeed.460800.macosx=460800
+weact_studio_esp32c3.menu.UploadSpeed.460800.upload.speed=460800
+weact_studio_esp32c3.menu.UploadSpeed.512000.windows=512000
+weact_studio_esp32c3.menu.UploadSpeed.512000.upload.speed=512000
+
+weact_studio_esp32c3.menu.DebugLevel.none=None
+weact_studio_esp32c3.menu.DebugLevel.none.build.code_debug=0
+weact_studio_esp32c3.menu.DebugLevel.error=Error
+weact_studio_esp32c3.menu.DebugLevel.error.build.code_debug=1
+weact_studio_esp32c3.menu.DebugLevel.warn=Warn
+weact_studio_esp32c3.menu.DebugLevel.warn.build.code_debug=2
+weact_studio_esp32c3.menu.DebugLevel.info=Info
+weact_studio_esp32c3.menu.DebugLevel.info.build.code_debug=3
+weact_studio_esp32c3.menu.DebugLevel.debug=Debug
+weact_studio_esp32c3.menu.DebugLevel.debug.build.code_debug=4
+weact_studio_esp32c3.menu.DebugLevel.verbose=Verbose
+weact_studio_esp32c3.menu.DebugLevel.verbose.build.code_debug=5
+
+weact_studio_esp32c3.menu.EraseFlash.none=Disabled
+weact_studio_esp32c3.menu.EraseFlash.none.upload.erase_cmd=
+weact_studio_esp32c3.menu.EraseFlash.all=Enabled
+weact_studio_esp32c3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+aslcanx2.name=AutosportLabs ESP-CAN-X2
+
+aslcanx2.bootloader.tool=esptool_py
+aslcanx2.bootloader.tool.default=esptool_py
+
+aslcanx2.upload.tool=esptool_py
+aslcanx2.upload.tool.default=esptool_py
+aslcanx2.upload.tool.network=esp_ota
+
+aslcanx2.upload.maximum_size=1310720
+aslcanx2.upload.maximum_data_size=327680
+aslcanx2.upload.flags=
+aslcanx2.upload.extra_flags=
+aslcanx2.upload.use_1200bps_touch=false
+aslcanx2.upload.wait_for_upload_port=false
+
+aslcanx2.serial.disableDTR=false
+aslcanx2.serial.disableRTS=false
+
+aslcanx2.build.tarch=xtensa
+aslcanx2.build.bootloader_addr=0x0
+aslcanx2.build.target=esp32s3
+aslcanx2.build.mcu=esp32s3
+aslcanx2.build.core=esp32
+aslcanx2.build.variant=aslcanx2
+aslcanx2.build.board=ASL_CAN_X2
+
+aslcanx2.build.usb_mode=1
+aslcanx2.build.cdc_on_boot=0
+aslcanx2.build.msc_on_boot=0
+aslcanx2.build.dfu_on_boot=0
+aslcanx2.build.f_cpu=240000000L
+aslcanx2.build.flash_size=8MB
+aslcanx2.build.flash_freq=80m
+aslcanx2.build.flash_mode=dio
+aslcanx2.build.boot=qio
+aslcanx2.build.boot_freq=80m
+aslcanx2.build.partitions=default_8MB
+aslcanx2.build.defines=
+aslcanx2.build.loop_core=
+aslcanx2.build.event_core=
+aslcanx2.build.psram_type=qspi
+aslcanx2.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+aslcanx2.menu.JTAGAdapter.default=Disabled
+aslcanx2.menu.JTAGAdapter.default.build.copy_jtag_files=0
+aslcanx2.menu.JTAGAdapter.builtin=Integrated USB JTAG
+aslcanx2.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+aslcanx2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+aslcanx2.menu.JTAGAdapter.external=FTDI Adapter
+aslcanx2.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+aslcanx2.menu.JTAGAdapter.external.build.copy_jtag_files=1
+aslcanx2.menu.JTAGAdapter.bridge=ESP USB Bridge
+aslcanx2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+aslcanx2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+aslcanx2.menu.PSRAM.disabled=Disabled
+aslcanx2.menu.PSRAM.disabled.build.defines=
+aslcanx2.menu.PSRAM.disabled.build.psram_type=qspi
+aslcanx2.menu.PSRAM.opi=OPI PSRAM
+aslcanx2.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+aslcanx2.menu.PSRAM.opi.build.psram_type=opi
+
+aslcanx2.menu.FlashMode.qio=QIO 80MHz
+aslcanx2.menu.FlashMode.qio.build.flash_mode=dio
+aslcanx2.menu.FlashMode.qio.build.boot=qio
+aslcanx2.menu.FlashMode.qio.build.boot_freq=80m
+aslcanx2.menu.FlashMode.qio.build.flash_freq=80m
+aslcanx2.menu.FlashMode.qio120=QIO 120MHz
+aslcanx2.menu.FlashMode.qio120.build.flash_mode=dio
+aslcanx2.menu.FlashMode.qio120.build.boot=qio
+aslcanx2.menu.FlashMode.qio120.build.boot_freq=120m
+aslcanx2.menu.FlashMode.qio120.build.flash_freq=80m
+aslcanx2.menu.FlashMode.dio=DIO 80MHz
+aslcanx2.menu.FlashMode.dio.build.flash_mode=dio
+aslcanx2.menu.FlashMode.dio.build.boot=dio
+aslcanx2.menu.FlashMode.dio.build.boot_freq=80m
+aslcanx2.menu.FlashMode.dio.build.flash_freq=80m
+aslcanx2.menu.FlashMode.opi=OPI 80MHz
+aslcanx2.menu.FlashMode.opi.build.flash_mode=dout
+aslcanx2.menu.FlashMode.opi.build.boot=opi
+aslcanx2.menu.FlashMode.opi.build.boot_freq=80m
+aslcanx2.menu.FlashMode.opi.build.flash_freq=80m
+
+aslcanx2.menu.LoopCore.1=Core 1
+aslcanx2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+aslcanx2.menu.LoopCore.0=Core 0
+aslcanx2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+aslcanx2.menu.EventsCore.1=Core 1
+aslcanx2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+aslcanx2.menu.EventsCore.0=Core 0
+aslcanx2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+aslcanx2.menu.USBMode.hwcdc=Hardware CDC and JTAG
+aslcanx2.menu.USBMode.hwcdc.build.usb_mode=1
+aslcanx2.menu.USBMode.default=USB-OTG (TinyUSB)
+aslcanx2.menu.USBMode.default.build.usb_mode=0
+
+aslcanx2.menu.CDCOnBoot.default=Enabled
+aslcanx2.menu.CDCOnBoot.default.build.cdc_on_boot=1
+aslcanx2.menu.CDCOnBoot.cdc=Disabled
+aslcanx2.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+aslcanx2.menu.MSCOnBoot.default=Disabled
+aslcanx2.menu.MSCOnBoot.default.build.msc_on_boot=0
+aslcanx2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+aslcanx2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+aslcanx2.menu.DFUOnBoot.default=Disabled
+aslcanx2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+aslcanx2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+aslcanx2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+aslcanx2.menu.UploadMode.default=UART0 / Hardware CDC
+aslcanx2.menu.UploadMode.default.upload.use_1200bps_touch=false
+aslcanx2.menu.UploadMode.default.upload.wait_for_upload_port=false
+aslcanx2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+aslcanx2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+aslcanx2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+aslcanx2.menu.PartitionScheme.default=Default with spiffs (3MB APP/1.5MB SPIFFS)
+aslcanx2.menu.PartitionScheme.default.build.partitions=default_8MB
+aslcanx2.menu.PartitionScheme.default.upload.maximum_size=3342336
+aslcanx2.menu.PartitionScheme.defaultffat=Default with ffat (3MB APP/1.5MB FATFS)
+aslcanx2.menu.PartitionScheme.defaultffat.build.partitions=default_8MB_ffat
+aslcanx2.menu.PartitionScheme.defaultffat.upload.maximum_size=3342336
+aslcanx2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+aslcanx2.menu.PartitionScheme.minimal.build.partitions=minimal
+aslcanx2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+aslcanx2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+aslcanx2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+aslcanx2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+aslcanx2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+aslcanx2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+aslcanx2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+aslcanx2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+aslcanx2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+aslcanx2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+aslcanx2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+aslcanx2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+aslcanx2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+aslcanx2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+aslcanx2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+aslcanx2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+aslcanx2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+aslcanx2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+aslcanx2.menu.PartitionScheme.rainmaker=RainMaker 4MB
+aslcanx2.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+aslcanx2.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+aslcanx2.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+aslcanx2.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+aslcanx2.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+aslcanx2.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+aslcanx2.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+aslcanx2.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+
+aslcanx2.menu.CPUFreq.240=240MHz (WiFi)
+aslcanx2.menu.CPUFreq.240.build.f_cpu=240000000L
+aslcanx2.menu.CPUFreq.160=160MHz (WiFi)
+aslcanx2.menu.CPUFreq.160.build.f_cpu=160000000L
+aslcanx2.menu.CPUFreq.80=80MHz (WiFi)
+aslcanx2.menu.CPUFreq.80.build.f_cpu=80000000L
+aslcanx2.menu.CPUFreq.40=40MHz
+aslcanx2.menu.CPUFreq.40.build.f_cpu=40000000L
+aslcanx2.menu.CPUFreq.20=20MHz
+aslcanx2.menu.CPUFreq.20.build.f_cpu=20000000L
+aslcanx2.menu.CPUFreq.10=10MHz
+aslcanx2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+aslcanx2.menu.UploadSpeed.921600=921600
+aslcanx2.menu.UploadSpeed.921600.upload.speed=921600
+aslcanx2.menu.UploadSpeed.115200=115200
+aslcanx2.menu.UploadSpeed.115200.upload.speed=115200
+aslcanx2.menu.UploadSpeed.256000.windows=256000
+aslcanx2.menu.UploadSpeed.256000.upload.speed=256000
+aslcanx2.menu.UploadSpeed.230400.windows.upload.speed=256000
+aslcanx2.menu.UploadSpeed.230400=230400
+aslcanx2.menu.UploadSpeed.230400.upload.speed=230400
+aslcanx2.menu.UploadSpeed.460800.linux=460800
+aslcanx2.menu.UploadSpeed.460800.macosx=460800
+aslcanx2.menu.UploadSpeed.460800.upload.speed=460800
+aslcanx2.menu.UploadSpeed.512000.windows=512000
+aslcanx2.menu.UploadSpeed.512000.upload.speed=512000
+
+aslcanx2.menu.DebugLevel.none=None
+aslcanx2.menu.DebugLevel.none.build.code_debug=0
+aslcanx2.menu.DebugLevel.error=Error
+aslcanx2.menu.DebugLevel.error.build.code_debug=1
+aslcanx2.menu.DebugLevel.warn=Warn
+aslcanx2.menu.DebugLevel.warn.build.code_debug=2
+aslcanx2.menu.DebugLevel.info=Info
+aslcanx2.menu.DebugLevel.info.build.code_debug=3
+aslcanx2.menu.DebugLevel.debug=Debug
+aslcanx2.menu.DebugLevel.debug.build.code_debug=4
+aslcanx2.menu.DebugLevel.verbose=Verbose
+aslcanx2.menu.DebugLevel.verbose.build.code_debug=5
+
+aslcanx2.menu.EraseFlash.none=Disabled
+aslcanx2.menu.EraseFlash.none.upload.erase_cmd=
+aslcanx2.menu.EraseFlash.all=Enabled
+aslcanx2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+walter.name=DPTechnics Walter
+
+walter.bootloader.tool=esptool_py
+walter.bootloader.tool.default=esptool_py
+
+walter.upload.tool=esptool_py
+walter.upload.tool.default=esptool_py
+walter.upload.tool.network=esp_ota
+
+walter.upload.maximum_size=1310720
+walter.upload.maximum_data_size=327680
+walter.upload.flags=
+walter.upload.extra_flags=
+walter.upload.use_1200bps_touch=false
+walter.upload.wait_for_upload_port=false
+
+walter.serial.disableDTR=false
+walter.serial.disableRTS=false
+
+walter.build.tarch=xtensa
+walter.build.bootloader_addr=0x0
+walter.build.target=esp32s3
+walter.build.mcu=esp32s3
+walter.build.core=esp32
+walter.build.variant=walter
+walter.build.board=DPTECHNICS_WALTER
+
+walter.build.usb_mode=1
+walter.build.cdc_on_boot=1
+walter.build.msc_on_boot=0
+walter.build.dfu_on_boot=0
+walter.build.f_cpu=240000000L
+walter.build.flash_size=16MB
+walter.build.flash_freq=80m
+walter.build.flash_mode=dio
+walter.build.boot=qio
+walter.build.boot_freq=80m
+walter.build.partitions=default
+walter.build.defines=
+walter.build.loop_core=
+walter.build.event_core=
+walter.build.psram_type=qspi
+walter.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+walter.menu.JTAGAdapter.default=Disabled
+walter.menu.JTAGAdapter.default.build.copy_jtag_files=0
+walter.menu.JTAGAdapter.builtin=Integrated USB JTAG
+walter.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+walter.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+walter.menu.JTAGAdapter.external=FTDI Adapter
+walter.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+walter.menu.JTAGAdapter.external.build.copy_jtag_files=1
+walter.menu.JTAGAdapter.bridge=ESP USB Bridge
+walter.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+walter.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+walter.menu.PSRAM.enabled=QSPI PSRAM
+walter.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+walter.menu.PSRAM.enabled.build.psram_type=qspi
+walter.menu.PSRAM.disabled=Disabled
+walter.menu.PSRAM.disabled.build.defines=
+walter.menu.PSRAM.disabled.build.psram_type=qspi
+
+walter.menu.FlashMode.qio=QIO 80MHz
+walter.menu.FlashMode.qio.build.flash_mode=dio
+walter.menu.FlashMode.qio.build.boot=qio
+walter.menu.FlashMode.qio.build.boot_freq=80m
+walter.menu.FlashMode.qio.build.flash_freq=80m
+walter.menu.FlashMode.dio=DIO 80MHz
+walter.menu.FlashMode.dio.build.flash_mode=dio
+walter.menu.FlashMode.dio.build.boot=dio
+walter.menu.FlashMode.dio.build.boot_freq=80m
+walter.menu.FlashMode.dio.build.flash_freq=80m
+
+walter.menu.FlashSize.16M=16MB (128Mb)
+walter.menu.FlashSize.16M.build.flash_size=16MB
+
+walter.menu.LoopCore.1=Core 1
+walter.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+walter.menu.LoopCore.0=Core 0
+walter.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+walter.menu.EventsCore.1=Core 1
+walter.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+walter.menu.EventsCore.0=Core 0
+walter.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+walter.menu.USBMode.hwcdc=Hardware CDC and JTAG
+walter.menu.USBMode.hwcdc.build.usb_mode=1
+walter.menu.USBMode.default=USB-OTG (TinyUSB)
+walter.menu.USBMode.default.build.usb_mode=0
+
+walter.menu.CDCOnBoot.cdc=Enabled
+walter.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+walter.menu.CDCOnBoot.default=Disabled
+walter.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+walter.menu.MSCOnBoot.default=Disabled
+walter.menu.MSCOnBoot.default.build.msc_on_boot=0
+walter.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+walter.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+walter.menu.DFUOnBoot.default=Disabled
+walter.menu.DFUOnBoot.default.build.dfu_on_boot=0
+walter.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+walter.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+walter.menu.UploadMode.default=UART0 / Hardware CDC
+walter.menu.UploadMode.default.upload.use_1200bps_touch=false
+walter.menu.UploadMode.default.upload.wait_for_upload_port=false
+walter.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+walter.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+walter.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+walter.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+walter.menu.PartitionScheme.fatflash.build.partitions=ffat
+walter.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+walter.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+walter.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+walter.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+walter.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS)
+walter.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
+walter.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
+
+walter.menu.CPUFreq.240=240MHz (WiFi)
+walter.menu.CPUFreq.240.build.f_cpu=240000000L
+walter.menu.CPUFreq.160=160MHz (WiFi)
+walter.menu.CPUFreq.160.build.f_cpu=160000000L
+walter.menu.CPUFreq.80=80MHz (WiFi)
+walter.menu.CPUFreq.80.build.f_cpu=80000000L
+walter.menu.CPUFreq.40=40MHz
+walter.menu.CPUFreq.40.build.f_cpu=40000000L
+walter.menu.CPUFreq.20=20MHz
+walter.menu.CPUFreq.20.build.f_cpu=20000000L
+walter.menu.CPUFreq.10=10MHz
+walter.menu.CPUFreq.10.build.f_cpu=10000000L
+
+walter.menu.UploadSpeed.921600=921600
+walter.menu.UploadSpeed.921600.upload.speed=921600
+walter.menu.UploadSpeed.115200=115200
+walter.menu.UploadSpeed.115200.upload.speed=115200
+walter.menu.UploadSpeed.256000.windows=256000
+walter.menu.UploadSpeed.256000.upload.speed=256000
+walter.menu.UploadSpeed.230400.windows.upload.speed=256000
+walter.menu.UploadSpeed.230400=230400
+walter.menu.UploadSpeed.230400.upload.speed=230400
+walter.menu.UploadSpeed.460800.linux=460800
+walter.menu.UploadSpeed.460800.macosx=460800
+walter.menu.UploadSpeed.460800.upload.speed=460800
+walter.menu.UploadSpeed.512000.windows=512000
+walter.menu.UploadSpeed.512000.upload.speed=512000
+
+walter.menu.DebugLevel.none=None
+walter.menu.DebugLevel.none.build.code_debug=0
+walter.menu.DebugLevel.error=Error
+walter.menu.DebugLevel.error.build.code_debug=1
+walter.menu.DebugLevel.warn=Warn
+walter.menu.DebugLevel.warn.build.code_debug=2
+walter.menu.DebugLevel.info=Info
+walter.menu.DebugLevel.info.build.code_debug=3
+walter.menu.DebugLevel.debug=Debug
+walter.menu.DebugLevel.debug.build.code_debug=4
+walter.menu.DebugLevel.verbose=Verbose
+walter.menu.DebugLevel.verbose.build.code_debug=5
+
+walter.menu.EraseFlash.none=Disabled
+walter.menu.EraseFlash.none.upload.erase_cmd=
+walter.menu.EraseFlash.all=Enabled
+walter.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+elecrow_crowpanel_7.name=Elecrow CrowPanel 7.0P
+
+elecrow_crowpanel_7.upload.tool=esptool_py
+elecrow_crowpanel_7.upload.tool.default=esptool_py
+elecrow_crowpanel_7.upload.tool.network=esp_ota
+elecrow_crowpanel_7.upload.maximum_size=1310720
+elecrow_crowpanel_7.upload.maximum_data_size=327680
+elecrow_crowpanel_7.upload.wait_for_upload_port=false
+elecrow_crowpanel_7.upload.speed=460800
+elecrow_crowpanel_7.upload.flags=
+elecrow_crowpanel_7.upload.extra_flags=
+
+elecrow_crowpanel_7.bootloader.tool=esptool_py
+elecrow_crowpanel_7.bootloader.tool.default=esptool_py
+
+elecrow_crowpanel_7.serial.disableDTR=true
+elecrow_crowpanel_7.serial.disableRTS=true
+
+elecrow_crowpanel_7.build.tarch=xtensa
+elecrow_crowpanel_7.build.bootloader_addr=0x0
+elecrow_crowpanel_7.build.mcu=esp32s3
+elecrow_crowpanel_7.build.core=esp32
+elecrow_crowpanel_7.build.target=esp32s3
+elecrow_crowpanel_7.build.variant=elecrow_crowpanel_7
+elecrow_crowpanel_7.build.board=ELECROW_CROWPANEL_7
+
+elecrow_crowpanel_7.build.usb_mode=1
+elecrow_crowpanel_7.build.cdc_on_boot=1
+elecrow_crowpanel_7.build.msc_on_boot=0
+elecrow_crowpanel_7.build.dfu_on_boot=0
+
+elecrow_crowpanel_7.build.f_cpu=240000000L
+elecrow_crowpanel_7.build.flash_size=4MB
+elecrow_crowpanel_7.build.flash_freq=80m
+elecrow_crowpanel_7.build.flash_mode=dio
+elecrow_crowpanel_7.build.boot=dio
+elecrow_crowpanel_7.build.partitions=default
+
+elecrow_crowpanel_7.menu.PSRAM.disabled=Disabled
+elecrow_crowpanel_7.menu.PSRAM.disabled.build.defines=
+elecrow_crowpanel_7.menu.PSRAM.enabled=Enabled
+elecrow_crowpanel_7.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+elecrow_crowpanel_7.menu.PSRAM.enabled.build.psram_type=opi
+
+elecrow_crowpanel_7.menu.LoopCore.1=Core 1
+elecrow_crowpanel_7.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+elecrow_crowpanel_7.menu.LoopCore.0=Core 0
+elecrow_crowpanel_7.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+elecrow_crowpanel_7.menu.EventsCore.1=Core 1
+elecrow_crowpanel_7.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+elecrow_crowpanel_7.menu.EventsCore.0=Core 0
+elecrow_crowpanel_7.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+elecrow_crowpanel_7.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+elecrow_crowpanel_7.menu.PartitionScheme.default.build.partitions=default
+elecrow_crowpanel_7.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+elecrow_crowpanel_7.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+elecrow_crowpanel_7.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+elecrow_crowpanel_7.menu.PartitionScheme.minimal.build.partitions=minimal
+elecrow_crowpanel_7.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+elecrow_crowpanel_7.menu.PartitionScheme.no_ota.build.partitions=no_ota
+elecrow_crowpanel_7.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+elecrow_crowpanel_7.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+elecrow_crowpanel_7.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+elecrow_crowpanel_7.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+elecrow_crowpanel_7.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+elecrow_crowpanel_7.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+elecrow_crowpanel_7.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+elecrow_crowpanel_7.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+elecrow_crowpanel_7.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+elecrow_crowpanel_7.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+elecrow_crowpanel_7.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+elecrow_crowpanel_7.menu.PartitionScheme.huge_app.build.partitions=huge_app
+elecrow_crowpanel_7.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+elecrow_crowpanel_7.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+elecrow_crowpanel_7.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+elecrow_crowpanel_7.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+
+elecrow_crowpanel_7.menu.CPUFreq.240=240MHz (WiFi/BT)
+elecrow_crowpanel_7.menu.CPUFreq.240.build.f_cpu=240000000L
+elecrow_crowpanel_7.menu.CPUFreq.160=160MHz (WiFi/BT)
+elecrow_crowpanel_7.menu.CPUFreq.160.build.f_cpu=160000000L
+elecrow_crowpanel_7.menu.CPUFreq.80=80MHz (WiFi/BT)
+elecrow_crowpanel_7.menu.CPUFreq.80.build.f_cpu=80000000L
+elecrow_crowpanel_7.menu.CPUFreq.40=40MHz (40MHz XTAL)
+elecrow_crowpanel_7.menu.CPUFreq.40.build.f_cpu=40000000L
+elecrow_crowpanel_7.menu.CPUFreq.26=26MHz (26MHz XTAL)
+elecrow_crowpanel_7.menu.CPUFreq.26.build.f_cpu=26000000L
+elecrow_crowpanel_7.menu.CPUFreq.20=20MHz (40MHz XTAL)
+elecrow_crowpanel_7.menu.CPUFreq.20.build.f_cpu=20000000L
+elecrow_crowpanel_7.menu.CPUFreq.13=13MHz (26MHz XTAL)
+elecrow_crowpanel_7.menu.CPUFreq.13.build.f_cpu=13000000L
+elecrow_crowpanel_7.menu.CPUFreq.10=10MHz (40MHz XTAL)
+elecrow_crowpanel_7.menu.CPUFreq.10.build.f_cpu=10000000L
+
+elecrow_crowpanel_7.menu.FlashMode.qio=QIO
+elecrow_crowpanel_7.menu.FlashMode.qio.build.flash_mode=dio
+elecrow_crowpanel_7.menu.FlashMode.qio.build.boot=qio
+elecrow_crowpanel_7.menu.FlashMode.dio=DIO
+elecrow_crowpanel_7.menu.FlashMode.dio.build.flash_mode=dio
+elecrow_crowpanel_7.menu.FlashMode.dio.build.boot=dio
+
+elecrow_crowpanel_7.menu.FlashFreq.80=80MHz
+elecrow_crowpanel_7.menu.FlashFreq.80.build.flash_freq=80m
+elecrow_crowpanel_7.menu.FlashFreq.40=40MHz
+elecrow_crowpanel_7.menu.FlashFreq.40.build.flash_freq=40m
+
+elecrow_crowpanel_7.menu.FlashSize.4MB=4MB (32Mb)
+elecrow_crowpanel_7.menu.FlashSize.4MB.build.flash_size=4MB
+
+elecrow_crowpanel_7.menu.UploadSpeed.921600=921600
+elecrow_crowpanel_7.menu.UploadSpeed.921600.upload.speed=921600
+elecrow_crowpanel_7.menu.UploadSpeed.115200=115200
+elecrow_crowpanel_7.menu.UploadSpeed.115200.upload.speed=115200
+elecrow_crowpanel_7.menu.UploadSpeed.256000.windows=256000
+elecrow_crowpanel_7.menu.UploadSpeed.256000.upload.speed=256000
+elecrow_crowpanel_7.menu.UploadSpeed.230400.windows.upload.speed=256000
+elecrow_crowpanel_7.menu.UploadSpeed.230400=230400
+elecrow_crowpanel_7.menu.UploadSpeed.230400.upload.speed=230400
+elecrow_crowpanel_7.menu.UploadSpeed.460800.linux=460800
+elecrow_crowpanel_7.menu.UploadSpeed.460800.macosx=460800
+elecrow_crowpanel_7.menu.UploadSpeed.460800.upload.speed=460800
+elecrow_crowpanel_7.menu.UploadSpeed.512000.windows=512000
+elecrow_crowpanel_7.menu.UploadSpeed.512000.upload.speed=512000
+
+elecrow_crowpanel_7.menu.DebugLevel.none=None
+elecrow_crowpanel_7.menu.DebugLevel.none.build.code_debug=0
+elecrow_crowpanel_7.menu.DebugLevel.error=Error
+elecrow_crowpanel_7.menu.DebugLevel.error.build.code_debug=1
+elecrow_crowpanel_7.menu.DebugLevel.warn=Warn
+elecrow_crowpanel_7.menu.DebugLevel.warn.build.code_debug=2
+elecrow_crowpanel_7.menu.DebugLevel.info=Info
+elecrow_crowpanel_7.menu.DebugLevel.info.build.code_debug=3
+elecrow_crowpanel_7.menu.DebugLevel.debug=Debug
+elecrow_crowpanel_7.menu.DebugLevel.debug.build.code_debug=4
+elecrow_crowpanel_7.menu.DebugLevel.verbose=Verbose
+elecrow_crowpanel_7.menu.DebugLevel.verbose.build.code_debug=5
+
+elecrow_crowpanel_7.menu.EraseFlash.none=Disabled
+elecrow_crowpanel_7.menu.EraseFlash.none.upload.erase_cmd=
+elecrow_crowpanel_7.menu.EraseFlash.all=Enabled
+elecrow_crowpanel_7.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+circuitart_zero_s3.name=CircuitART Zero S3
+circuitart_zero_s3.vid.0=0x303a
+circuitart_zero_s3.pid.0=0x80DB
+
+circuitart_zero_s3.bootloader.tool=esptool_py
+circuitart_zero_s3.bootloader.tool.default=esptool_py
+
+circuitart_zero_s3.upload.tool=esptool_py
+circuitart_zero_s3.upload.tool.default=esptool_py
+circuitart_zero_s3.upload.tool.network=esp_ota
+
+circuitart_zero_s3.upload.maximum_size=1310720
+circuitart_zero_s3.upload.maximum_data_size=327680
+circuitart_zero_s3.upload.flags=
+circuitart_zero_s3.upload.extra_flags=
+circuitart_zero_s3.upload.use_1200bps_touch=false
+circuitart_zero_s3.upload.wait_for_upload_port=false
+
+circuitart_zero_s3.serial.disableDTR=false
+circuitart_zero_s3.serial.disableRTS=false
+
+circuitart_zero_s3.build.tarch=xtensa
+circuitart_zero_s3.build.bootloader_addr=0x0
+circuitart_zero_s3.build.target=esp32s3
+circuitart_zero_s3.build.mcu=esp32s3
+circuitart_zero_s3.build.core=esp32
+circuitart_zero_s3.build.variant=circuitart_zero_s3
+circuitart_zero_s3.build.board=CIRCUITART_ZERO_S3
+
+circuitart_zero_s3.build.usb_mode=1
+circuitart_zero_s3.build.cdc_on_boot=0
+circuitart_zero_s3.build.msc_on_boot=0
+circuitart_zero_s3.build.dfu_on_boot=0
+circuitart_zero_s3.build.f_cpu=240000000L
+circuitart_zero_s3.build.flash_size=16MB
+circuitart_zero_s3.build.flash_freq=80m
+circuitart_zero_s3.build.flash_mode=dio
+circuitart_zero_s3.build.boot=qio
+circuitart_zero_s3.build.partitions=default
+circuitart_zero_s3.build.defines=
+circuitart_zero_s3.build.loop_core=
+circuitart_zero_s3.build.event_core=
+circuitart_zero_s3.build.flash_type=qio
+circuitart_zero_s3.build.psram_type=qspi
+circuitart_zero_s3.build.memory_type=qio_qspi
+
+circuitart_zero_s3.menu.LoopCore.1=Core 1
+circuitart_zero_s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+circuitart_zero_s3.menu.LoopCore.0=Core 0
+circuitart_zero_s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+circuitart_zero_s3.menu.EventsCore.1=Core 1
+circuitart_zero_s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+circuitart_zero_s3.menu.EventsCore.0=Core 0
+circuitart_zero_s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+circuitart_zero_s3.menu.USBMode.default=USB-OTG (TinyUSB)
+circuitart_zero_s3.menu.USBMode.default.build.usb_mode=0
+circuitart_zero_s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+circuitart_zero_s3.menu.USBMode.hwcdc.build.usb_mode=1
+
+circuitart_zero_s3.menu.CDCOnBoot.cdc=Enabled
+circuitart_zero_s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+circuitart_zero_s3.menu.CDCOnBoot.default=Disabled
+circuitart_zero_s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+circuitart_zero_s3.menu.MSCOnBoot.default=Disabled
+circuitart_zero_s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+circuitart_zero_s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+circuitart_zero_s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+circuitart_zero_s3.menu.DFUOnBoot.default=Disabled
+circuitart_zero_s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+circuitart_zero_s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+circuitart_zero_s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+circuitart_zero_s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+circuitart_zero_s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+circuitart_zero_s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+circuitart_zero_s3.menu.UploadMode.default=UART0 / Hardware CDC
+circuitart_zero_s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+circuitart_zero_s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+
+circuitart_zero_s3.menu.PSRAM.enabled=Enabled
+circuitart_zero_s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+circuitart_zero_s3.menu.PSRAM.disabled=Disabled
+circuitart_zero_s3.menu.PSRAM.disabled.build.defines=
+
+circuitart_zero_s3.menu.PartitionScheme.default_16MB=Default (6.25MB APP/3.43MB SPIFFS)
+circuitart_zero_s3.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
+circuitart_zero_s3.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
+circuitart_zero_s3.menu.PartitionScheme.tinyuf2=TinyUF2 Compatibility (2MB APP/12MB FFAT)
+circuitart_zero_s3.menu.PartitionScheme.tinyuf2.build.custom_bootloader=bootloader_tinyuf2
+circuitart_zero_s3.menu.PartitionScheme.tinyuf2.build.custom_partitions=partitions_tinyuf2
+circuitart_zero_s3.menu.PartitionScheme.tinyuf2.upload.extra_flags=0x410000 "{runtime.platform.path}/variants/{build.variant}/tinyuf2.bin"
+circuitart_zero_s3.menu.PartitionScheme.tinyuf2.upload.maximum_size=2097152
+circuitart_zero_s3.menu.PartitionScheme.large_spiffs=Large SPIFFS (4.5MB APP/6.93MB SPIFFS)
+circuitart_zero_s3.menu.PartitionScheme.large_spiffs.build.partitions=large_spiffs_16MB
+circuitart_zero_s3.menu.PartitionScheme.large_spiffs.upload.maximum_size=4718592
+circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB=FFAT (3MB APP/9MB FATFS)
+circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+circuitart_zero_s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+circuitart_zero_s3.menu.PartitionScheme.fatflash=Large FFAT (2MB APP/12.5MB FATFS)
+circuitart_zero_s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+circuitart_zero_s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+
+circuitart_zero_s3.menu.CPUFreq.240=240MHz (WiFi)
+circuitart_zero_s3.menu.CPUFreq.240.build.f_cpu=240000000L
+circuitart_zero_s3.menu.CPUFreq.160=160MHz (WiFi)
+circuitart_zero_s3.menu.CPUFreq.160.build.f_cpu=160000000L
+circuitart_zero_s3.menu.CPUFreq.80=80MHz (WiFi)
+circuitart_zero_s3.menu.CPUFreq.80.build.f_cpu=80000000L
+circuitart_zero_s3.menu.CPUFreq.40=40MHz
+circuitart_zero_s3.menu.CPUFreq.40.build.f_cpu=40000000L
+circuitart_zero_s3.menu.CPUFreq.20=20MHz
+circuitart_zero_s3.menu.CPUFreq.20.build.f_cpu=20000000L
+circuitart_zero_s3.menu.CPUFreq.10=10MHz
+circuitart_zero_s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+circuitart_zero_s3.menu.FlashMode.qio=QIO
+circuitart_zero_s3.menu.FlashMode.qio.build.flash_mode=dio
+circuitart_zero_s3.menu.FlashMode.qio.build.boot=qio
+circuitart_zero_s3.menu.FlashMode.dio=DIO
+circuitart_zero_s3.menu.FlashMode.dio.build.flash_mode=dio
+circuitart_zero_s3.menu.FlashMode.dio.build.boot=dio
+
+circuitart_zero_s3.menu.UploadSpeed.921600=921600
+circuitart_zero_s3.menu.UploadSpeed.921600.upload.speed=921600
+circuitart_zero_s3.menu.UploadSpeed.115200=115200
+circuitart_zero_s3.menu.UploadSpeed.115200.upload.speed=115200
+circuitart_zero_s3.menu.UploadSpeed.256000.windows=256000
+circuitart_zero_s3.menu.UploadSpeed.256000.upload.speed=256000
+circuitart_zero_s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+circuitart_zero_s3.menu.UploadSpeed.230400=230400
+circuitart_zero_s3.menu.UploadSpeed.230400.upload.speed=230400
+circuitart_zero_s3.menu.UploadSpeed.460800.linux=460800
+circuitart_zero_s3.menu.UploadSpeed.460800.macosx=460800
+circuitart_zero_s3.menu.UploadSpeed.460800.upload.speed=460800
+circuitart_zero_s3.menu.UploadSpeed.512000.windows=512000
+circuitart_zero_s3.menu.UploadSpeed.512000.upload.speed=512000
+
+circuitart_zero_s3.menu.DebugLevel.none=None
+circuitart_zero_s3.menu.DebugLevel.none.build.code_debug=0
+circuitart_zero_s3.menu.DebugLevel.error=Error
+circuitart_zero_s3.menu.DebugLevel.error.build.code_debug=1
+circuitart_zero_s3.menu.DebugLevel.warn=Warn
+circuitart_zero_s3.menu.DebugLevel.warn.build.code_debug=2
+circuitart_zero_s3.menu.DebugLevel.info=Info
+circuitart_zero_s3.menu.DebugLevel.info.build.code_debug=3
+circuitart_zero_s3.menu.DebugLevel.debug=Debug
+circuitart_zero_s3.menu.DebugLevel.debug.build.code_debug=4
+circuitart_zero_s3.menu.DebugLevel.verbose=Verbose
+circuitart_zero_s3.menu.DebugLevel.verbose.build.code_debug=5
+
+circuitart_zero_s3.menu.EraseFlash.none=Disabled
+circuitart_zero_s3.menu.EraseFlash.none.upload.erase_cmd=
+circuitart_zero_s3.menu.EraseFlash.all=Enabled
+circuitart_zero_s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+# Alfredo NoU3
+
+alfredo-nou3.name=Alfredo NoU3
+alfredo-nou3.vid.0=0xAFD0
+alfredo-nou3.pid.0=0x0003
+alfredo-nou3.upload_port.0.vid=0xAFD0
+alfredo-nou3.upload_port.0.pid=0x0003
+
+alfredo-nou3.bootloader.tool=esptool_py
+alfredo-nou3.bootloader.tool.default=esptool_py
+
+alfredo-nou3.upload.tool=esptool_py
+alfredo-nou3.upload.tool.default=esptool_py
+alfredo-nou3.upload.tool.network=esp_ota
+
+alfredo-nou3.upload.maximum_size=3342336
+alfredo-nou3.upload.maximum_data_size=327680
+alfredo-nou3.upload.flags=
+alfredo-nou3.upload.extra_flags=
+alfredo-nou3.upload.use_1200bps_touch=false
+alfredo-nou3.upload.wait_for_upload_port=false
+
+alfredo-nou3.serial.disableDTR=false
+alfredo-nou3.serial.disableRTS=false
+
+alfredo-nou3.build.tarch=xtensa
+alfredo-nou3.build.bootloader_addr=0x0
+alfredo-nou3.build.target=esp32s3
+alfredo-nou3.build.mcu=esp32s3
+alfredo-nou3.build.core=esp32
+alfredo-nou3.build.variant=alfredo-nou3
+alfredo-nou3.build.board=ALFREDO_NOU3
+
+alfredo-nou3.build.usb_mode=1
+alfredo-nou3.build.cdc_on_boot=1
+alfredo-nou3.build.msc_on_boot=0
+alfredo-nou3.build.dfu_on_boot=0
+alfredo-nou3.build.f_cpu=240000000L
+alfredo-nou3.build.flash_size=8MB
+alfredo-nou3.build.flash_freq=80m
+alfredo-nou3.build.flash_mode=dio
+alfredo-nou3.build.boot=qio
+alfredo-nou3.build.partitions=default
+alfredo-nou3.build.defines=
+alfredo-nou3.build.loop_core=
+alfredo-nou3.build.event_core=
+alfredo-nou3.build.flash_type=qio
+alfredo-nou3.build.psram_type=qspi
+alfredo-nou3.build.memory_type={build.flash_type}_{build.psram_type}
+
+alfredo-nou3.menu.LoopCore.1=Core 1
+alfredo-nou3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+alfredo-nou3.menu.LoopCore.0=Core 0
+alfredo-nou3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+alfredo-nou3.menu.EventsCore.1=Core 1
+alfredo-nou3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+alfredo-nou3.menu.EventsCore.0=Core 0
+alfredo-nou3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+alfredo-nou3.menu.USBMode.default=Hardware CDC and JTAG
+alfredo-nou3.menu.USBMode.default.build.usb_mode=1
+alfredo-nou3.menu.USBMode.usbotg=USB-OTG (TinyUSB)
+alfredo-nou3.menu.USBMode.usbotg.build.usb_mode=0
+
+alfredo-nou3.menu.CDCOnBoot.cdc=Enabled
+alfredo-nou3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+alfredo-nou3.menu.CDCOnBoot.default=Disabled
+alfredo-nou3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+alfredo-nou3.menu.MSCOnBoot.default=Disabled
+alfredo-nou3.menu.MSCOnBoot.default.build.msc_on_boot=0
+alfredo-nou3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+alfredo-nou3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+alfredo-nou3.menu.DFUOnBoot.default=Disabled
+alfredo-nou3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+alfredo-nou3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+alfredo-nou3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+alfredo-nou3.menu.UploadMode.default=UART0 / Hardware CDC
+alfredo-nou3.menu.UploadMode.default.upload.use_1200bps_touch=false
+alfredo-nou3.menu.UploadMode.default.upload.wait_for_upload_port=false
+alfredo-nou3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+alfredo-nou3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+alfredo-nou3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+alfredo-nou3.menu.PartitionScheme.default_8MB=Default (3MB APP/1.5MB SPIFFS)
+alfredo-nou3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+alfredo-nou3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+alfredo-nou3.menu.PartitionScheme.big_8MB=Max App (8MB APP)
+alfredo-nou3.menu.PartitionScheme.big_8MB.build.partitions=max_app_8MB
+alfredo-nou3.menu.PartitionScheme.big_8MB.upload.maximum_size=8257536
+
+alfredo-nou3.menu.CPUFreq.240=240MHz (WiFi)
+alfredo-nou3.menu.CPUFreq.240.build.f_cpu=240000000L
+alfredo-nou3.menu.CPUFreq.160=160MHz (WiFi)
+alfredo-nou3.menu.CPUFreq.160.build.f_cpu=160000000L
+alfredo-nou3.menu.CPUFreq.80=80MHz (WiFi)
+alfredo-nou3.menu.CPUFreq.80.build.f_cpu=80000000L
+alfredo-nou3.menu.CPUFreq.40=40MHz
+alfredo-nou3.menu.CPUFreq.40.build.f_cpu=40000000L
+alfredo-nou3.menu.CPUFreq.20=20MHz
+alfredo-nou3.menu.CPUFreq.20.build.f_cpu=20000000L
+alfredo-nou3.menu.CPUFreq.10=10MHz
+alfredo-nou3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+alfredo-nou3.menu.FlashMode.qio=QIO 80MHz
+alfredo-nou3.menu.FlashMode.qio.build.flash_mode=dio
+alfredo-nou3.menu.FlashMode.qio.build.boot=qio
+alfredo-nou3.menu.FlashMode.qio.build.boot_freq=80m
+alfredo-nou3.menu.FlashMode.qio.build.flash_freq=80m
+alfredo-nou3.menu.FlashMode.qio120=QIO 120MHz
+alfredo-nou3.menu.FlashMode.qio120.build.flash_mode=dio
+alfredo-nou3.menu.FlashMode.qio120.build.boot=qio
+alfredo-nou3.menu.FlashMode.qio120.build.boot_freq=120m
+alfredo-nou3.menu.FlashMode.qio120.build.flash_freq=80m
+alfredo-nou3.menu.FlashMode.dio=DIO 80MHz
+alfredo-nou3.menu.FlashMode.dio.build.flash_mode=dio
+alfredo-nou3.menu.FlashMode.dio.build.boot=dio
+alfredo-nou3.menu.FlashMode.dio.build.boot_freq=80m
+alfredo-nou3.menu.FlashMode.dio.build.flash_freq=80m
+alfredo-nou3.menu.FlashMode.opi=OPI 80MHz
+alfredo-nou3.menu.FlashMode.opi.build.flash_mode=dout
+alfredo-nou3.menu.FlashMode.opi.build.boot=opi
+alfredo-nou3.menu.FlashMode.opi.build.boot_freq=80m
+alfredo-nou3.menu.FlashMode.opi.build.flash_freq=80m
+
+alfredo-nou3.menu.FlashSize.8M=8MB (64Mb)
+alfredo-nou3.menu.FlashSize.8M.build.flash_size=8MB
+
+alfredo-nou3.menu.UploadSpeed.921600=921600
+alfredo-nou3.menu.UploadSpeed.921600.upload.speed=921600
+alfredo-nou3.menu.UploadSpeed.512000.windows=512000
+alfredo-nou3.menu.UploadSpeed.512000.upload.speed=512000
+alfredo-nou3.menu.UploadSpeed.460800.linux=460800
+alfredo-nou3.menu.UploadSpeed.460800.macosx=460800
+alfredo-nou3.menu.UploadSpeed.460800.upload.speed=460800
+alfredo-nou3.menu.UploadSpeed.256000.windows=256000
+alfredo-nou3.menu.UploadSpeed.256000.upload.speed=256000
+alfredo-nou3.menu.UploadSpeed.230400.windows.upload.speed=256000
+alfredo-nou3.menu.UploadSpeed.230400=230400
+alfredo-nou3.menu.UploadSpeed.230400.upload.speed=230400
+alfredo-nou3.menu.UploadSpeed.115200=115200
+alfredo-nou3.menu.UploadSpeed.115200.upload.speed=115200
+
+alfredo-nou3.menu.DebugLevel.none=None
+alfredo-nou3.menu.DebugLevel.none.build.code_debug=0
+alfredo-nou3.menu.DebugLevel.error=Error
+alfredo-nou3.menu.DebugLevel.error.build.code_debug=1
+alfredo-nou3.menu.DebugLevel.warn=Warn
+alfredo-nou3.menu.DebugLevel.warn.build.code_debug=2
+alfredo-nou3.menu.DebugLevel.info=Info
+alfredo-nou3.menu.DebugLevel.info.build.code_debug=3
+alfredo-nou3.menu.DebugLevel.debug=Debug
+alfredo-nou3.menu.DebugLevel.debug.build.code_debug=4
+alfredo-nou3.menu.DebugLevel.verbose=Verbose
+alfredo-nou3.menu.DebugLevel.verbose.build.code_debug=5
+
+alfredo-nou3.menu.EraseFlash.none=Disabled
+alfredo-nou3.menu.EraseFlash.none.upload.erase_cmd=
+alfredo-nou3.menu.EraseFlash.all=Enabled
+alfredo-nou3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+codecell.name=CodeCell
+codecell.vid.0=0x303a
+codecell.pid.0=0x1002
+codecell.upload_port.0.vid=0x303a
+codecell.upload_port.0.pid=0x1002
+
+codecell.bootloader.tool=esptool_py
+codecell.upload.tool=esptool_py
+codecell.upload.maximum_size=4194304
+codecell.upload.maximum_data_size=327680
+codecell.upload.use_1200bps_touch=false
+codecell.upload.wait_for_upload_port=false
+
+codecell.upload.speed=921600
+codecell.serial.disableDTR=false
+codecell.serial.disableRTS=false
+
+codecell.build.tarch=riscv32
+codecell.build.target=esp
+codecell.build.mcu=esp32c3
+codecell.build.core=esp32
+codecell.build.variant=codecell
+codecell.build.board=ESP32C3_DEV
+codecell.build.bootloader_addr=0x0
+codecell.build.cdc_on_boot=1
+codecell.build.f_cpu=160000000L
+codecell.build.flash_size=4MB
+codecell.build.flash_freq=80m
+codecell.build.flash_mode=qio
+codecell.build.boot=qio
+codecell.build.partitions=default
+
+codecell.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+codecell.menu.CPUFreq.160=160MHz
+codecell.menu.FlashMode.qio=QIO
+codecell.menu.FlashFreq.80=80MHz
+codecell.menu.FlashSize.4M=4MB (32Mb)
+codecell.menu.UploadSpeed.921600=921600
+
+codecell.menu.DebugLevel.none=None
+codecell.menu.DebugLevel.none.build.code_debug=0
+codecell.menu.DebugLevel.error=Error
+codecell.menu.DebugLevel.error.build.code_debug=1
+codecell.menu.DebugLevel.warn=Warn
+codecell.menu.DebugLevel.warn.build.code_debug=2
+codecell.menu.DebugLevel.info=Info
+codecell.menu.DebugLevel.info.build.code_debug=3
+codecell.menu.DebugLevel.debug=Debug
+codecell.menu.DebugLevel.debug.build.code_debug=4
+codecell.menu.DebugLevel.verbose=Verbose
+codecell.menu.DebugLevel.verbose.build.code_debug=5
+
+codecell.menu.EraseFlash.none=Disabled
+codecell.menu.EraseFlash.none.upload.erase_cmd=
+codecell.menu.EraseFlash.all=Enabled
+codecell.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+jczn_2432s028r.name=ESP32-2432S028R CYD
+
+jczn_2432s028r.bootloader.tool=esptool_py
+jczn_2432s028r.bootloader.tool.default=esptool_py
+
+jczn_2432s028r.upload.tool=esptool_py
+jczn_2432s028r.upload.tool.default=esptool_py
+jczn_2432s028r.upload.tool.network=esp_ota
+
+jczn_2432s028r.upload.maximum_size=1310720
+jczn_2432s028r.upload.maximum_data_size=327680
+jczn_2432s028r.upload.flags=
+jczn_2432s028r.upload.extra_flags=
+
+jczn_2432s028r.serial.disableDTR=true
+jczn_2432s028r.serial.disableRTS=true
+
+jczn_2432s028r.build.tarch=xtensa
+jczn_2432s028r.build.bootloader_addr=0x1000
+jczn_2432s028r.build.target=esp32
+jczn_2432s028r.build.mcu=esp32
+jczn_2432s028r.build.core=esp32
+jczn_2432s028r.build.variant=jczn_2432s028r
+jczn_2432s028r.build.board=ESP32_2432S028R
+
+jczn_2432s028r.build.f_cpu=240000000L
+jczn_2432s028r.build.flash_size=4MB
+jczn_2432s028r.build.flash_freq=40m
+jczn_2432s028r.build.flash_mode=dio
+jczn_2432s028r.build.boot=dio
+jczn_2432s028r.build.partitions=default
+jczn_2432s028r.build.defines=
+jczn_2432s028r.build.loop_core=
+jczn_2432s028r.build.event_core=
+
+## IDE 2.0 Seems to not update the value
+jczn_2432s028r.menu.JTAGAdapter.default=Disabled
+jczn_2432s028r.menu.JTAGAdapter.default.build.copy_jtag_files=0
+jczn_2432s028r.menu.JTAGAdapter.external=FTDI Adapter
+jczn_2432s028r.menu.JTAGAdapter.external.build.openocdscript=esp32-wrover-kit-3.3v.cfg
+jczn_2432s028r.menu.JTAGAdapter.external.build.copy_jtag_files=1
+jczn_2432s028r.menu.JTAGAdapter.bridge=ESP USB Bridge
+jczn_2432s028r.menu.JTAGAdapter.bridge.build.openocdscript=esp32-bridge.cfg
+jczn_2432s028r.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+jczn_2432s028r.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+jczn_2432s028r.menu.PartitionScheme.default.build.partitions=default
+jczn_2432s028r.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+jczn_2432s028r.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+jczn_2432s028r.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+jczn_2432s028r.menu.PartitionScheme.no_ota.build.partitions=no_ota
+jczn_2432s028r.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+jczn_2432s028r.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+jczn_2432s028r.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+jczn_2432s028r.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+jczn_2432s028r.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+jczn_2432s028r.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+jczn_2432s028r.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+jczn_2432s028r.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+jczn_2432s028r.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+jczn_2432s028r.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+jczn_2432s028r.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+jczn_2432s028r.menu.PartitionScheme.huge_app.build.partitions=huge_app
+jczn_2432s028r.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+jczn_2432s028r.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+jczn_2432s028r.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+jczn_2432s028r.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+jczn_2432s028r.menu.PartitionScheme.rainmaker=RainMaker 4MB
+jczn_2432s028r.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+jczn_2432s028r.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+jczn_2432s028r.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+jczn_2432s028r.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+jczn_2432s028r.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+jczn_2432s028r.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+jczn_2432s028r.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+jczn_2432s028r.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+
+jczn_2432s028r.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+jczn_2432s028r.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+jczn_2432s028r.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+jczn_2432s028r.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+jczn_2432s028r.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+jczn_2432s028r.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+jczn_2432s028r.menu.PartitionScheme.custom=Custom
+jczn_2432s028r.menu.PartitionScheme.custom.build.partitions=
+jczn_2432s028r.menu.PartitionScheme.custom.upload.maximum_size=4128768
+
+jczn_2432s028r.menu.CPUFreq.240=240MHz (WiFi/BT)
+jczn_2432s028r.menu.CPUFreq.240.build.f_cpu=240000000L
+jczn_2432s028r.menu.CPUFreq.160=160MHz (WiFi/BT)
+jczn_2432s028r.menu.CPUFreq.160.build.f_cpu=160000000L
+jczn_2432s028r.menu.CPUFreq.80=80MHz (WiFi/BT)
+jczn_2432s028r.menu.CPUFreq.80.build.f_cpu=80000000L
+jczn_2432s028r.menu.CPUFreq.40=40MHz
+jczn_2432s028r.menu.CPUFreq.40.build.f_cpu=40000000L
+jczn_2432s028r.menu.CPUFreq.20=20MHz
+jczn_2432s028r.menu.CPUFreq.20.build.f_cpu=20000000L
+jczn_2432s028r.menu.CPUFreq.10=10MHz
+jczn_2432s028r.menu.CPUFreq.10.build.f_cpu=10000000L
+
+jczn_2432s028r.menu.FlashMode.qio=QIO
+jczn_2432s028r.menu.FlashMode.qio.build.flash_mode=dio
+jczn_2432s028r.menu.FlashMode.qio.build.boot=qio
+
+jczn_2432s028r.menu.FlashFreq.80=80MHz
+jczn_2432s028r.menu.FlashFreq.80.build.flash_freq=80m
+jczn_2432s028r.menu.FlashFreq.40=40MHz
+jczn_2432s028r.menu.FlashFreq.40.build.flash_freq=40m
+
+jczn_2432s028r.menu.FlashSize.4M=4MB
+jczn_2432s028r.menu.FlashSize.4M.build.flash_size=4MB
+
+jczn_2432s028r.menu.UploadSpeed.921600=921600
+jczn_2432s028r.menu.UploadSpeed.921600.upload.speed=921600
+jczn_2432s028r.menu.UploadSpeed.115200=115200
+jczn_2432s028r.menu.UploadSpeed.115200.upload.speed=115200
+jczn_2432s028r.menu.UploadSpeed.256000.windows=256000
+jczn_2432s028r.menu.UploadSpeed.256000.upload.speed=256000
+jczn_2432s028r.menu.UploadSpeed.230400.windows.upload.speed=256000
+jczn_2432s028r.menu.UploadSpeed.230400=230400
+jczn_2432s028r.menu.UploadSpeed.230400.upload.speed=230400
+jczn_2432s028r.menu.UploadSpeed.460800.linux=460800
+jczn_2432s028r.menu.UploadSpeed.460800.macosx=460800
+jczn_2432s028r.menu.UploadSpeed.460800.upload.speed=460800
+jczn_2432s028r.menu.UploadSpeed.512000.windows=512000
+jczn_2432s028r.menu.UploadSpeed.512000.upload.speed=512000
+
+jczn_2432s028r.menu.LoopCore.1=Core 1
+jczn_2432s028r.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+jczn_2432s028r.menu.LoopCore.0=Core 0
+jczn_2432s028r.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+jczn_2432s028r.menu.EventsCore.1=Core 1
+jczn_2432s028r.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+jczn_2432s028r.menu.EventsCore.0=Core 0
+jczn_2432s028r.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+jczn_2432s028r.menu.DebugLevel.none=None
+jczn_2432s028r.menu.DebugLevel.none.build.code_debug=0
+jczn_2432s028r.menu.DebugLevel.error=Error
+jczn_2432s028r.menu.DebugLevel.error.build.code_debug=1
+jczn_2432s028r.menu.DebugLevel.warn=Warn
+jczn_2432s028r.menu.DebugLevel.warn.build.code_debug=2
+jczn_2432s028r.menu.DebugLevel.info=Info
+jczn_2432s028r.menu.DebugLevel.info.build.code_debug=3
+jczn_2432s028r.menu.DebugLevel.debug=Debug
+jczn_2432s028r.menu.DebugLevel.debug.build.code_debug=4
+jczn_2432s028r.menu.DebugLevel.verbose=Verbose
+jczn_2432s028r.menu.DebugLevel.verbose.build.code_debug=5
+
+jczn_2432s028r.menu.EraseFlash.none=Disabled
+jczn_2432s028r.menu.EraseFlash.none.upload.erase_cmd=
+jczn_2432s028r.menu.EraseFlash.all=Enabled
+jczn_2432s028r.menu.EraseFlash.all.upload.erase_cmd=-e
+
+jczn_2432s028r.menu.ZigbeeMode.default=Disabled
+jczn_2432s028r.menu.ZigbeeMode.default.build.zigbee_mode=
+jczn_2432s028r.menu.ZigbeeMode.default.build.zigbee_libs=
+jczn_2432s028r.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+jczn_2432s028r.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+jczn_2432s028r.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+waveshare_esp32_s3_touch_amoled_241.name=Waveshare ESP32-S3-Touch-AMOLED-2.41
+waveshare_esp32_s3_touch_amoled_241.vid.0=0x303a
+waveshare_esp32_s3_touch_amoled_241.pid.0=0x8242
+waveshare_esp32_s3_touch_amoled_241.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_amoled_241.upload_port.0.pid=0x8242
+
+waveshare_esp32_s3_touch_amoled_241.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_241.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_amoled_241.upload.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_241.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_amoled_241.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_amoled_241.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_amoled_241.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_amoled_241.upload.flags=
+waveshare_esp32_s3_touch_amoled_241.upload.extra_flags=
+waveshare_esp32_s3_touch_amoled_241.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_241.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_amoled_241.serial.disableDTR=false
+waveshare_esp32_s3_touch_amoled_241.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_amoled_241.build.tarch=xtensa
+waveshare_esp32_s3_touch_amoled_241.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_amoled_241.build.target=esp32s3
+waveshare_esp32_s3_touch_amoled_241.build.mcu=esp32s3
+waveshare_esp32_s3_touch_amoled_241.build.core=esp32
+waveshare_esp32_s3_touch_amoled_241.build.variant=waveshare_esp32_s3_touch_amoled_241
+waveshare_esp32_s3_touch_amoled_241.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_241
+
+waveshare_esp32_s3_touch_amoled_241.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_241.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_241.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_241.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_241.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_241.build.flash_size=16MB
+
+waveshare_esp32_s3_touch_amoled_241.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_241.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_241.build.boot=qio
+waveshare_esp32_s3_touch_amoled_241.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_241.build.partitions=default
+waveshare_esp32_s3_touch_amoled_241.build.defines=
+waveshare_esp32_s3_touch_amoled_241.build.loop_core=
+waveshare_esp32_s3_touch_amoled_241.build.event_core=
+waveshare_esp32_s3_touch_amoled_241.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_241.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_amoled_241.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_amoled_241.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_amoled_241.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_241.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_241.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_241.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_241.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_241.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_241.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_241.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_241.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_amoled_241.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_241.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_amoled_241.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_amoled_241.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_241.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_241.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_amoled_241.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_241.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_241.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_241.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_241.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_241.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_241.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_241.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_241.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_amoled_241.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_amoled_241.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_amoled_241.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_amoled_241.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_amoled_241.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_amoled_241.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_amoled_241.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_amoled_241.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_amoled_241.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_43.name=Waveshare ESP32-S3-Touch-LCD-4.3
+waveshare_esp32_s3_touch_lcd_43.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_43.pid.0=0x822E
+waveshare_esp32_s3_touch_lcd_43.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_43.upload_port.0.pid=0x822E
+
+waveshare_esp32_s3_touch_lcd_43.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_43.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_43.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_43.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_43.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_43.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_lcd_43.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_43.upload.flags=
+waveshare_esp32_s3_touch_lcd_43.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_43.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_43.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_43.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_43.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_43.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_43.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_43.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_43.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_43.build.core=esp32
+waveshare_esp32_s3_touch_lcd_43.build.variant=waveshare_esp32_s3_touch_lcd_43
+waveshare_esp32_s3_touch_lcd_43.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_43
+
+waveshare_esp32_s3_touch_lcd_43.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_43.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_43.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_43.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_43.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_43.build.flash_size=8MB
+waveshare_esp32_s3_touch_lcd_43.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_43.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_43.build.boot=qio
+waveshare_esp32_s3_touch_lcd_43.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_43.build.partitions=default
+waveshare_esp32_s3_touch_lcd_43.build.defines=
+waveshare_esp32_s3_touch_lcd_43.build.loop_core=
+waveshare_esp32_s3_touch_lcd_43.build.event_core=
+waveshare_esp32_s3_touch_lcd_43.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_43.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_43.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_43.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_43.menu.FlashSize.8M=8MB (64Mb)
+waveshare_esp32_s3_touch_lcd_43.menu.FlashSize.8M.build.flash_size=8MB
+waveshare_esp32_s3_touch_lcd_43.menu.FlashSize.16M=16MB (128Mb)
+waveshare_esp32_s3_touch_lcd_43.menu.FlashSize.16M.build.flash_size=16MB
+
+waveshare_esp32_s3_touch_lcd_43.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_43.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_43.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_43.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_43.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_43.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_43.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_43.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_43.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_43.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_43.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_43.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_43.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_43.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_43.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_43.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_43.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_43.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_43.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_43.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_43.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_43.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_43.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_43.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_43.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_43.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_43.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_43.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_43.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_43.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_43.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_43.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_43.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_43B.name=Waveshare ESP32-S3-Touch-LCD-4.3B
+waveshare_esp32_s3_touch_lcd_43B.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_43B.pid.0=0x8231
+waveshare_esp32_s3_touch_lcd_43B.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_43B.upload_port.0.pid=0x8231
+
+waveshare_esp32_s3_touch_lcd_43B.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_43B.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_43B.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_43B.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_43B.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_43B.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_lcd_43B.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_43B.upload.flags=
+waveshare_esp32_s3_touch_lcd_43B.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_43B.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_43B.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_43B.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_43B.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_43B.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_43B.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_43B.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_43B.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_43B.build.core=esp32
+waveshare_esp32_s3_touch_lcd_43B.build.variant=waveshare_esp32_s3_touch_lcd_43b
+waveshare_esp32_s3_touch_lcd_43B.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_43B
+
+waveshare_esp32_s3_touch_lcd_43B.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_43B.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_43B.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_43B.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_43B.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_43B.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_43B.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_43B.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_43B.build.boot=qio
+waveshare_esp32_s3_touch_lcd_43B.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_43B.build.partitions=default
+waveshare_esp32_s3_touch_lcd_43B.build.defines=
+waveshare_esp32_s3_touch_lcd_43B.build.loop_core=
+waveshare_esp32_s3_touch_lcd_43B.build.event_core=
+waveshare_esp32_s3_touch_lcd_43B.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_43B.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_43B.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_43B.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_43B.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_43B.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_43B.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_43B.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_43B.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_43B.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_43B.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_43B.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_43B.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_43B.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_43B.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_43B.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_43B.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_43B.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_43B.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_43B.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_43B.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_43B.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_43B.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_43B.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_43B.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_43B.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_43B.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_43B.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_43B.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_43B.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_43B.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_43B.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_43B.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_43B.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_43B.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_43B.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_7.name=Waveshare ESP32-S3-Touch-LCD-7
+waveshare_esp32_s3_touch_lcd_7.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_7.pid.0=0x8234
+waveshare_esp32_s3_touch_lcd_7.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_7.upload_port.0.pid=0x8234
+
+waveshare_esp32_s3_touch_lcd_7.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_7.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_7.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_7.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_7.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_7.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_lcd_7.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_7.upload.flags=
+waveshare_esp32_s3_touch_lcd_7.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_7.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_7.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_7.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_7.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_7.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_7.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_7.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_7.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_7.build.core=esp32
+waveshare_esp32_s3_touch_lcd_7.build.variant=waveshare_esp32_s3_touch_lcd_7
+waveshare_esp32_s3_touch_lcd_7.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_7
+
+waveshare_esp32_s3_touch_lcd_7.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_7.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_7.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_7.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_7.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_7.build.flash_size=8MB
+waveshare_esp32_s3_touch_lcd_7.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_7.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_7.build.boot=qio
+waveshare_esp32_s3_touch_lcd_7.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_7.build.partitions=default
+waveshare_esp32_s3_touch_lcd_7.build.defines=
+waveshare_esp32_s3_touch_lcd_7.build.loop_core=
+waveshare_esp32_s3_touch_lcd_7.build.event_core=
+waveshare_esp32_s3_touch_lcd_7.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_7.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_7.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_7.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_7.menu.FlashSize.8M=8MB (64Mb)
+waveshare_esp32_s3_touch_lcd_7.menu.FlashSize.8M.build.flash_size=8MB
+waveshare_esp32_s3_touch_lcd_7.menu.FlashSize.16M=16MB (128Mb)
+waveshare_esp32_s3_touch_lcd_7.menu.FlashSize.16M.build.flash_size=16MB
+
+waveshare_esp32_s3_touch_lcd_7.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_7.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_7.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_7.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_7.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_7.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_7.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_7.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_7.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_7.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_7.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_7.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_7.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_7.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_7.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_7.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_7.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_7.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_7.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_7.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_7.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_7.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_7.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_7.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_7.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_7.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_7.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_7.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_7.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_7.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_7.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_7.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_7.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_5.name=Waveshare ESP32-S3-Touch-LCD-5
+waveshare_esp32_s3_touch_lcd_5.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_5.pid.0=0x8237
+waveshare_esp32_s3_touch_lcd_5.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_5.upload_port.0.pid=0x8237
+
+waveshare_esp32_s3_touch_lcd_5.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_5.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_5.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_5.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_5.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_5.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_lcd_5.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_5.upload.flags=
+waveshare_esp32_s3_touch_lcd_5.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_5.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_5.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_5.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_5.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_5.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_5.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_5.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_5.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_5.build.core=esp32
+waveshare_esp32_s3_touch_lcd_5.build.variant=waveshare_esp32_s3_touch_lcd_5
+waveshare_esp32_s3_touch_lcd_5.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_5
+
+waveshare_esp32_s3_touch_lcd_5.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_5.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_5.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_5.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_5.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_5.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_5.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_5.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_5.build.boot=qio
+waveshare_esp32_s3_touch_lcd_5.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_5.build.partitions=default
+waveshare_esp32_s3_touch_lcd_5.build.defines=
+waveshare_esp32_s3_touch_lcd_5.build.loop_core=
+waveshare_esp32_s3_touch_lcd_5.build.event_core=
+waveshare_esp32_s3_touch_lcd_5.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_5.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_5.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_5.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_5.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_5.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_5.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_5.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_5.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_5.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_5.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_5.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_5.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_5.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_5.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_5.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_5.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_5.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_5.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_5.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_5.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_5.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_5.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_5.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_5.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_5.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_5.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_5.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_5.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_5.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_5.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_5.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_5.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_5.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_5.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_5.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_5.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_5B.name=Waveshare ESP32-S3-Touch-LCD-5B
+waveshare_esp32_s3_touch_lcd_5B.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_5B.pid.0=0x823A
+waveshare_esp32_s3_touch_lcd_5B.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_5B.upload_port.0.pid=0x823A
+
+waveshare_esp32_s3_touch_lcd_5B.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_5B.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_5B.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_5B.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_5B.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_5B.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_lcd_5B.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_5B.upload.flags=
+waveshare_esp32_s3_touch_lcd_5B.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_5B.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_5B.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_5B.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_5B.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_5B.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_5B.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_5B.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_5B.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_5B.build.core=esp32
+waveshare_esp32_s3_touch_lcd_5B.build.variant=waveshare_esp32_s3_touch_lcd_5b
+waveshare_esp32_s3_touch_lcd_5B.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_5B
+
+waveshare_esp32_s3_touch_lcd_5B.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_5B.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_5B.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_5B.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_5B.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_5B.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_5B.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_5B.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_5B.build.boot=qio
+waveshare_esp32_s3_touch_lcd_5B.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_5B.build.partitions=default
+waveshare_esp32_s3_touch_lcd_5B.build.defines=
+waveshare_esp32_s3_touch_lcd_5B.build.loop_core=
+waveshare_esp32_s3_touch_lcd_5B.build.event_core=
+waveshare_esp32_s3_touch_lcd_5B.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_5B.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_5B.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_5B.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_5B.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_5B.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_5B.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_5B.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_5B.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_5B.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_5B.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_5B.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_5B.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_5B.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_5B.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_5B.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_5B.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_5B.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_5B.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_5B.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_5B.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_5B.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_5B.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_5B.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_5B.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_5B.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_5B.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_5B.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_5B.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_5B.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_5B.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_5B.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_5B.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_5B.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_5B.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_5B.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_4.name=Waveshare ESP32-S3-Touch-LCD-4
+waveshare_esp32_s3_touch_lcd_4.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_4.pid.0=0x823D
+waveshare_esp32_s3_touch_lcd_4.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_4.upload_port.0.pid=0x823D
+
+waveshare_esp32_s3_touch_lcd_4.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_4.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_4.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_4.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_4.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_4.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_lcd_4.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_4.upload.flags=
+waveshare_esp32_s3_touch_lcd_4.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_4.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_4.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_4.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_4.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_4.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_4.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_4.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_4.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_4.build.core=esp32
+waveshare_esp32_s3_touch_lcd_4.build.variant=waveshare_esp32_s3_touch_lcd_4
+waveshare_esp32_s3_touch_lcd_4.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_4
+
+waveshare_esp32_s3_touch_lcd_4.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_4.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_4.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_4.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_4.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_4.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_4.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_4.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_4.build.boot=qio
+waveshare_esp32_s3_touch_lcd_4.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_4.build.partitions=default
+waveshare_esp32_s3_touch_lcd_4.build.defines=
+waveshare_esp32_s3_touch_lcd_4.build.loop_core=
+waveshare_esp32_s3_touch_lcd_4.build.event_core=
+waveshare_esp32_s3_touch_lcd_4.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_4.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_4.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_4.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_4.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_4.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_4.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_4.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_4.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_4.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_4.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_4.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_4.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_4.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_4.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_4.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_4.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_4.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_4.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_4.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_4.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_4.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_4.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_4.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_4.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_4.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_4.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_4.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_4.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_4.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_4.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_4.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_4.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_4.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_4.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_4.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_4.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_185.name=Waveshare ESP32-S3-Touch-LCD-1.85
+waveshare_esp32_s3_touch_lcd_185.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_185.pid.0=0x8290
+waveshare_esp32_s3_touch_lcd_185.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_185.upload_port.0.pid=0x8290
+
+waveshare_esp32_s3_touch_lcd_185.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_185.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_185.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_185.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_185.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_185.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_185.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_185.upload.flags=
+waveshare_esp32_s3_touch_lcd_185.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_185.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_185.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_185.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_185.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_185.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_185.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_185.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_185.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_185.build.core=esp32
+waveshare_esp32_s3_touch_lcd_185.build.variant=waveshare_esp32_s3_touch_lcd_185
+waveshare_esp32_s3_touch_lcd_185.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_185
+
+waveshare_esp32_s3_touch_lcd_185.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_185.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_185.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_185.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_185.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_185.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_185.build.flash_freq=120m
+waveshare_esp32_s3_touch_lcd_185.build.flash_mode=qio
+waveshare_esp32_s3_touch_lcd_185.build.boot=qio
+waveshare_esp32_s3_touch_lcd_185.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_185.build.partitions=default
+waveshare_esp32_s3_touch_lcd_185.build.defines=
+waveshare_esp32_s3_touch_lcd_185.build.loop_core=
+waveshare_esp32_s3_touch_lcd_185.build.event_core=
+waveshare_esp32_s3_touch_lcd_185.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_185.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.default=Disabled
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.default.build.copy_jtag_files=0
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.builtin=Integrated USB JTAG
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.external=FTDI Adapter
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.external.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.bridge=ESP USB Bridge
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+waveshare_esp32_s3_touch_lcd_185.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.enabled.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_185.menu.PSRAM.disabled.build.psram_type=qspi
+
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio120.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio=DIO 80MHz
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio.build.boot=dio
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.dio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi=OPI 80MHz
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi.build.flash_mode=dout
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi.build.boot=opi
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_185.menu.FlashMode.opi.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_185.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_185.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_185.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_185.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_185.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_185.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+waveshare_esp32_s3_touch_lcd_185.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_185.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+waveshare_esp32_s3_touch_lcd_185.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_185.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_185.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_185.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_185.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_185.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_185.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_185.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_185.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_185.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_185.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_185.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_185.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_185.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_185.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_185.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_185.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_fs.build.partitions=no_fs
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_185.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_185.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_185.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_185.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_185.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_185.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_185.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_185.menu.EraseFlash.all.upload.erase_cmd=-e
+
+waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.default=Disabled
+waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.default.build.zigbee_mode=
+waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.default.build.zigbee_libs=
+waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+waveshare_esp32_s3_touch_lcd_185.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+cezerio_dev_esp32c6.name=cezerio dev ESP32C6
+
+cezerio_dev_esp32c6.bootloader.tool=esptool_py
+cezerio_dev_esp32c6.bootloader.tool.default=esptool_py
+
+cezerio_dev_esp32c6.upload.tool=esptool_py
+cezerio_dev_esp32c6.upload.tool.default=esptool_py
+cezerio_dev_esp32c6.upload.tool.network=esp_ota
+
+cezerio_dev_esp32c6.upload.maximum_size=1310720
+cezerio_dev_esp32c6.upload.maximum_data_size=327680
+cezerio_dev_esp32c6.upload.flags=
+cezerio_dev_esp32c6.upload.extra_flags=
+cezerio_dev_esp32c6.upload.use_1200bps_touch=false
+cezerio_dev_esp32c6.upload.wait_for_upload_port=false
+
+cezerio_dev_esp32c6.serial.disableDTR=false
+cezerio_dev_esp32c6.serial.disableRTS=false
+
+cezerio_dev_esp32c6.build.tarch=riscv32
+cezerio_dev_esp32c6.build.target=esp
+cezerio_dev_esp32c6.build.mcu=esp32c6
+cezerio_dev_esp32c6.build.core=esp32
+cezerio_dev_esp32c6.build.variant=cezerio_dev_esp32c6
+cezerio_dev_esp32c6.build.board=CEZERIO_DEV_ESP32C6
+cezerio_dev_esp32c6.build.bootloader_addr=0x0
+
+cezerio_dev_esp32c6.build.cdc_on_boot=0
+cezerio_dev_esp32c6.build.f_cpu=160000000L
+cezerio_dev_esp32c6.build.flash_size=4MB
+cezerio_dev_esp32c6.build.flash_freq=80m
+cezerio_dev_esp32c6.build.flash_mode=qio
+cezerio_dev_esp32c6.build.boot=qio
+cezerio_dev_esp32c6.build.partitions=default
+cezerio_dev_esp32c6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+cezerio_dev_esp32c6.menu.JTAGAdapter.default=Disabled
+cezerio_dev_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+cezerio_dev_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+cezerio_dev_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+cezerio_dev_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+cezerio_dev_esp32c6.menu.JTAGAdapter.external=FTDI Adapter
+cezerio_dev_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+cezerio_dev_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+cezerio_dev_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge
+cezerio_dev_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+cezerio_dev_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+cezerio_dev_esp32c6.menu.CDCOnBoot.default=Enabled
+cezerio_dev_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=1
+cezerio_dev_esp32c6.menu.CDCOnBoot.cdc=Disabled
+cezerio_dev_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+cezerio_dev_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+cezerio_dev_esp32c6.menu.PartitionScheme.default.build.partitions=default
+cezerio_dev_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+cezerio_dev_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+cezerio_dev_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+cezerio_dev_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal
+cezerio_dev_esp32c6.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+cezerio_dev_esp32c6.menu.PartitionScheme.no_fs.build.partitions=no_fs
+cezerio_dev_esp32c6.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+cezerio_dev_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+cezerio_dev_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+cezerio_dev_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+cezerio_dev_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+cezerio_dev_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+cezerio_dev_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+cezerio_dev_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+cezerio_dev_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+cezerio_dev_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+cezerio_dev_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+cezerio_dev_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+cezerio_dev_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+cezerio_dev_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+cezerio_dev_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+cezerio_dev_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+cezerio_dev_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+cezerio_dev_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+cezerio_dev_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB
+cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+cezerio_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+cezerio_dev_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+cezerio_dev_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+cezerio_dev_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+cezerio_dev_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+cezerio_dev_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+cezerio_dev_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+cezerio_dev_esp32c6.menu.PartitionScheme.custom=Custom
+cezerio_dev_esp32c6.menu.PartitionScheme.custom.build.partitions=
+cezerio_dev_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+cezerio_dev_esp32c6.menu.CPUFreq.160=160MHz (WiFi)
+cezerio_dev_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L
+cezerio_dev_esp32c6.menu.CPUFreq.120=120MHz (WiFi)
+cezerio_dev_esp32c6.menu.CPUFreq.120.build.f_cpu=120000000L
+cezerio_dev_esp32c6.menu.CPUFreq.80=80MHz (WiFi)
+cezerio_dev_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L
+cezerio_dev_esp32c6.menu.CPUFreq.40=40MHz
+cezerio_dev_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L
+cezerio_dev_esp32c6.menu.CPUFreq.20=20MHz
+cezerio_dev_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L
+cezerio_dev_esp32c6.menu.CPUFreq.10=10MHz
+cezerio_dev_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+cezerio_dev_esp32c6.menu.FlashMode.qio=QIO
+cezerio_dev_esp32c6.menu.FlashMode.qio.build.flash_mode=dio
+cezerio_dev_esp32c6.menu.FlashMode.qio.build.boot=qio
+cezerio_dev_esp32c6.menu.FlashMode.dio=DIO
+cezerio_dev_esp32c6.menu.FlashMode.dio.build.flash_mode=dio
+cezerio_dev_esp32c6.menu.FlashMode.dio.build.boot=dio
+
+cezerio_dev_esp32c6.menu.FlashFreq.80=80MHz
+cezerio_dev_esp32c6.menu.FlashFreq.80.build.flash_freq=80m
+cezerio_dev_esp32c6.menu.FlashFreq.40=40MHz
+cezerio_dev_esp32c6.menu.FlashFreq.40.build.flash_freq=40m
+
+cezerio_dev_esp32c6.menu.FlashSize.4M=4MB (32Mb)
+cezerio_dev_esp32c6.menu.FlashSize.4M.build.flash_size=4MB
+
+cezerio_dev_esp32c6.menu.UploadSpeed.921600=921600
+cezerio_dev_esp32c6.menu.UploadSpeed.921600.upload.speed=921600
+cezerio_dev_esp32c6.menu.UploadSpeed.115200=115200
+cezerio_dev_esp32c6.menu.UploadSpeed.115200.upload.speed=115200
+cezerio_dev_esp32c6.menu.UploadSpeed.256000.windows=256000
+cezerio_dev_esp32c6.menu.UploadSpeed.256000.upload.speed=256000
+cezerio_dev_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000
+cezerio_dev_esp32c6.menu.UploadSpeed.230400=230400
+cezerio_dev_esp32c6.menu.UploadSpeed.230400.upload.speed=230400
+cezerio_dev_esp32c6.menu.UploadSpeed.460800.linux=460800
+cezerio_dev_esp32c6.menu.UploadSpeed.460800.macosx=460800
+cezerio_dev_esp32c6.menu.UploadSpeed.460800.upload.speed=460800
+cezerio_dev_esp32c6.menu.UploadSpeed.512000.windows=512000
+cezerio_dev_esp32c6.menu.UploadSpeed.512000.upload.speed=512000
+
+cezerio_dev_esp32c6.menu.DebugLevel.none=None
+cezerio_dev_esp32c6.menu.DebugLevel.none.build.code_debug=0
+cezerio_dev_esp32c6.menu.DebugLevel.error=Error
+cezerio_dev_esp32c6.menu.DebugLevel.error.build.code_debug=1
+cezerio_dev_esp32c6.menu.DebugLevel.warn=Warn
+cezerio_dev_esp32c6.menu.DebugLevel.warn.build.code_debug=2
+cezerio_dev_esp32c6.menu.DebugLevel.info=Info
+cezerio_dev_esp32c6.menu.DebugLevel.info.build.code_debug=3
+cezerio_dev_esp32c6.menu.DebugLevel.debug=Debug
+cezerio_dev_esp32c6.menu.DebugLevel.debug.build.code_debug=4
+cezerio_dev_esp32c6.menu.DebugLevel.verbose=Verbose
+cezerio_dev_esp32c6.menu.DebugLevel.verbose.build.code_debug=5
+
+cezerio_dev_esp32c6.menu.EraseFlash.none=Disabled
+cezerio_dev_esp32c6.menu.EraseFlash.none.upload.erase_cmd=
+cezerio_dev_esp32c6.menu.EraseFlash.all=Enabled
+cezerio_dev_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+cezerio_dev_esp32c6.menu.ZigbeeMode.default=Disabled
+cezerio_dev_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode=
+cezerio_dev_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs=
+cezerio_dev_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+cezerio_dev_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+cezerio_dev_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+cezerio_dev_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator)
+cezerio_dev_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+cezerio_dev_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+cezerio_mini_dev_esp32c6.name=cezerio mini dev ESP32C6
+
+cezerio_mini_dev_esp32c6.bootloader.tool=esptool_py
+cezerio_mini_dev_esp32c6.bootloader.tool.default=esptool_py
+
+cezerio_mini_dev_esp32c6.upload.tool=esptool_py
+cezerio_mini_dev_esp32c6.upload.tool.default=esptool_py
+cezerio_mini_dev_esp32c6.upload.tool.network=esp_ota
+
+cezerio_mini_dev_esp32c6.upload.maximum_size=1310720
+cezerio_mini_dev_esp32c6.upload.maximum_data_size=327680
+cezerio_mini_dev_esp32c6.upload.flags=
+cezerio_mini_dev_esp32c6.upload.extra_flags=
+cezerio_mini_dev_esp32c6.upload.use_1200bps_touch=false
+cezerio_mini_dev_esp32c6.upload.wait_for_upload_port=false
+
+cezerio_mini_dev_esp32c6.serial.disableDTR=false
+cezerio_mini_dev_esp32c6.serial.disableRTS=false
+
+cezerio_mini_dev_esp32c6.build.tarch=riscv32
+cezerio_mini_dev_esp32c6.build.target=esp
+cezerio_mini_dev_esp32c6.build.mcu=esp32c6
+cezerio_mini_dev_esp32c6.build.core=esp32
+cezerio_mini_dev_esp32c6.build.variant=cezerio_mini_dev_esp32c6
+cezerio_mini_dev_esp32c6.build.board=CEZERIO_MINI_DEV_ESP32C6
+cezerio_mini_dev_esp32c6.build.bootloader_addr=0x0
+
+cezerio_mini_dev_esp32c6.build.cdc_on_boot=0
+cezerio_mini_dev_esp32c6.build.f_cpu=160000000L
+cezerio_mini_dev_esp32c6.build.flash_size=4MB
+cezerio_mini_dev_esp32c6.build.flash_freq=80m
+cezerio_mini_dev_esp32c6.build.flash_mode=qio
+cezerio_mini_dev_esp32c6.build.boot=qio
+cezerio_mini_dev_esp32c6.build.partitions=default
+cezerio_mini_dev_esp32c6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.default=Disabled
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.external=FTDI Adapter
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.bridge=ESP USB Bridge
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+cezerio_mini_dev_esp32c6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+cezerio_mini_dev_esp32c6.menu.CDCOnBoot.default=Enabled
+cezerio_mini_dev_esp32c6.menu.CDCOnBoot.default.build.cdc_on_boot=1
+cezerio_mini_dev_esp32c6.menu.CDCOnBoot.cdc=Disabled
+cezerio_mini_dev_esp32c6.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.default.build.partitions=default
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.minimal.build.partitions=minimal
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_fs.build.partitions=no_fs
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker=RainMaker 4MB
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.custom=Custom
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.custom.build.partitions=
+cezerio_mini_dev_esp32c6.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+cezerio_mini_dev_esp32c6.menu.CPUFreq.160=160MHz (WiFi)
+cezerio_mini_dev_esp32c6.menu.CPUFreq.160.build.f_cpu=160000000L
+cezerio_mini_dev_esp32c6.menu.CPUFreq.120=120MHz (WiFi)
+cezerio_mini_dev_esp32c6.menu.CPUFreq.120.build.f_cpu=120000000L
+cezerio_mini_dev_esp32c6.menu.CPUFreq.80=80MHz (WiFi)
+cezerio_mini_dev_esp32c6.menu.CPUFreq.80.build.f_cpu=80000000L
+cezerio_mini_dev_esp32c6.menu.CPUFreq.40=40MHz
+cezerio_mini_dev_esp32c6.menu.CPUFreq.40.build.f_cpu=40000000L
+cezerio_mini_dev_esp32c6.menu.CPUFreq.20=20MHz
+cezerio_mini_dev_esp32c6.menu.CPUFreq.20.build.f_cpu=20000000L
+cezerio_mini_dev_esp32c6.menu.CPUFreq.10=10MHz
+cezerio_mini_dev_esp32c6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+cezerio_mini_dev_esp32c6.menu.FlashMode.qio=QIO
+cezerio_mini_dev_esp32c6.menu.FlashMode.qio.build.flash_mode=dio
+cezerio_mini_dev_esp32c6.menu.FlashMode.qio.build.boot=qio
+cezerio_mini_dev_esp32c6.menu.FlashMode.dio=DIO
+cezerio_mini_dev_esp32c6.menu.FlashMode.dio.build.flash_mode=dio
+cezerio_mini_dev_esp32c6.menu.FlashMode.dio.build.boot=dio
+
+cezerio_mini_dev_esp32c6.menu.FlashFreq.80=80MHz
+cezerio_mini_dev_esp32c6.menu.FlashFreq.80.build.flash_freq=80m
+cezerio_mini_dev_esp32c6.menu.FlashFreq.40=40MHz
+cezerio_mini_dev_esp32c6.menu.FlashFreq.40.build.flash_freq=40m
+
+cezerio_mini_dev_esp32c6.menu.FlashSize.4M=4MB (32Mb)
+cezerio_mini_dev_esp32c6.menu.FlashSize.4M.build.flash_size=4MB
+
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.921600=921600
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.921600.upload.speed=921600
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.115200=115200
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.115200.upload.speed=115200
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.256000.windows=256000
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.256000.upload.speed=256000
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.230400.windows.upload.speed=256000
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.230400=230400
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.230400.upload.speed=230400
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.460800.linux=460800
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.460800.macosx=460800
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.460800.upload.speed=460800
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.512000.windows=512000
+cezerio_mini_dev_esp32c6.menu.UploadSpeed.512000.upload.speed=512000
+
+cezerio_mini_dev_esp32c6.menu.DebugLevel.none=None
+cezerio_mini_dev_esp32c6.menu.DebugLevel.none.build.code_debug=0
+cezerio_mini_dev_esp32c6.menu.DebugLevel.error=Error
+cezerio_mini_dev_esp32c6.menu.DebugLevel.error.build.code_debug=1
+cezerio_mini_dev_esp32c6.menu.DebugLevel.warn=Warn
+cezerio_mini_dev_esp32c6.menu.DebugLevel.warn.build.code_debug=2
+cezerio_mini_dev_esp32c6.menu.DebugLevel.info=Info
+cezerio_mini_dev_esp32c6.menu.DebugLevel.info.build.code_debug=3
+cezerio_mini_dev_esp32c6.menu.DebugLevel.debug=Debug
+cezerio_mini_dev_esp32c6.menu.DebugLevel.debug.build.code_debug=4
+cezerio_mini_dev_esp32c6.menu.DebugLevel.verbose=Verbose
+cezerio_mini_dev_esp32c6.menu.DebugLevel.verbose.build.code_debug=5
+
+cezerio_mini_dev_esp32c6.menu.EraseFlash.none=Disabled
+cezerio_mini_dev_esp32c6.menu.EraseFlash.none.upload.erase_cmd=
+cezerio_mini_dev_esp32c6.menu.EraseFlash.all=Enabled
+cezerio_mini_dev_esp32c6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+cezerio_mini_dev_esp32c6.menu.ZigbeeMode.default=Disabled
+cezerio_mini_dev_esp32c6.menu.ZigbeeMode.default.build.zigbee_mode=
+cezerio_mini_dev_esp32c6.menu.ZigbeeMode.default.build.zigbee_libs=
+cezerio_mini_dev_esp32c6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+cezerio_mini_dev_esp32c6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+cezerio_mini_dev_esp32c6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+cezerio_mini_dev_esp32c6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator)
+cezerio_mini_dev_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+cezerio_mini_dev_esp32c6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+waveshare_esp32_s3_lcd_185.name=Waveshare ESP32-S3-LCD-1.85
+waveshare_esp32_s3_lcd_185.vid.0=0x303a
+waveshare_esp32_s3_lcd_185.pid.0=0x8242
+waveshare_esp32_s3_lcd_185.upload_port.0.vid=0x303a
+waveshare_esp32_s3_lcd_185.upload_port.0.pid=0x8242
+
+waveshare_esp32_s3_lcd_185.bootloader.tool=esptool_py
+waveshare_esp32_s3_lcd_185.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_lcd_185.upload.tool=esptool_py
+waveshare_esp32_s3_lcd_185.upload.tool.default=esptool_py
+waveshare_esp32_s3_lcd_185.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_lcd_185.upload.maximum_size=1310720
+waveshare_esp32_s3_lcd_185.upload.maximum_data_size=327680
+waveshare_esp32_s3_lcd_185.upload.flags=
+waveshare_esp32_s3_lcd_185.upload.extra_flags=
+waveshare_esp32_s3_lcd_185.upload.use_1200bps_touch=false
+waveshare_esp32_s3_lcd_185.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_lcd_185.serial.disableDTR=false
+waveshare_esp32_s3_lcd_185.serial.disableRTS=false
+
+waveshare_esp32_s3_lcd_185.build.tarch=xtensa
+waveshare_esp32_s3_lcd_185.build.bootloader_addr=0x0
+waveshare_esp32_s3_lcd_185.build.target=esp32s3
+waveshare_esp32_s3_lcd_185.build.mcu=esp32s3
+waveshare_esp32_s3_lcd_185.build.core=esp32
+waveshare_esp32_s3_lcd_185.build.variant=waveshare_esp32_s3_lcd_185
+waveshare_esp32_s3_lcd_185.build.board=WAVESHARE_ESP32_S3_LCD_185
+
+waveshare_esp32_s3_lcd_185.build.usb_mode=1
+waveshare_esp32_s3_lcd_185.build.cdc_on_boot=0
+waveshare_esp32_s3_lcd_185.build.msc_on_boot=0
+waveshare_esp32_s3_lcd_185.build.dfu_on_boot=0
+waveshare_esp32_s3_lcd_185.build.f_cpu=240000000L
+waveshare_esp32_s3_lcd_185.build.flash_size=16MB
+waveshare_esp32_s3_lcd_185.build.flash_freq=120m
+waveshare_esp32_s3_lcd_185.build.flash_mode=qio
+waveshare_esp32_s3_lcd_185.build.boot=qio
+waveshare_esp32_s3_lcd_185.build.boot_freq=80m
+waveshare_esp32_s3_lcd_185.build.partitions=default
+waveshare_esp32_s3_lcd_185.build.defines=
+waveshare_esp32_s3_lcd_185.build.loop_core=
+waveshare_esp32_s3_lcd_185.build.event_core=
+waveshare_esp32_s3_lcd_185.build.psram_type=opi
+waveshare_esp32_s3_lcd_185.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.default=Disabled
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.default.build.copy_jtag_files=0
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.builtin=Integrated USB JTAG
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.external=FTDI Adapter
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.external.build.copy_jtag_files=1
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.bridge=ESP USB Bridge
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+waveshare_esp32_s3_lcd_185.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+waveshare_esp32_s3_lcd_185.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_lcd_185.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_lcd_185.menu.PSRAM.enabled.build.psram_type=opi
+waveshare_esp32_s3_lcd_185.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_lcd_185.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_lcd_185.menu.PSRAM.disabled.build.psram_type=qspi
+
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio120.build.flash_freq=80m
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_lcd_185.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_lcd_185.menu.FlashMode.dio=DIO 80MHz
+waveshare_esp32_s3_lcd_185.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32_s3_lcd_185.menu.FlashMode.dio.build.boot=dio
+waveshare_esp32_s3_lcd_185.menu.FlashMode.dio.build.boot_freq=80m
+waveshare_esp32_s3_lcd_185.menu.FlashMode.dio.build.flash_freq=80m
+waveshare_esp32_s3_lcd_185.menu.FlashMode.opi=OPI 80MHz
+waveshare_esp32_s3_lcd_185.menu.FlashMode.opi.build.flash_mode=dout
+waveshare_esp32_s3_lcd_185.menu.FlashMode.opi.build.boot=opi
+waveshare_esp32_s3_lcd_185.menu.FlashMode.opi.build.boot_freq=80m
+waveshare_esp32_s3_lcd_185.menu.FlashMode.opi.build.flash_freq=80m
+
+waveshare_esp32_s3_lcd_185.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_lcd_185.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_lcd_185.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_lcd_185.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_lcd_185.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_lcd_185.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+waveshare_esp32_s3_lcd_185.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_lcd_185.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+waveshare_esp32_s3_lcd_185.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_lcd_185.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_lcd_185.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_lcd_185.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_lcd_185.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_185.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_lcd_185.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_lcd_185.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_lcd_185.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_185.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_lcd_185.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_lcd_185.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_lcd_185.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_185.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_lcd_185.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_lcd_185.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_lcd_185.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_lcd_185.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_lcd_185.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_lcd_185.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_lcd_185.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_lcd_185.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_fs.build.partitions=no_fs
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_lcd_185.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_lcd_185.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_lcd_185.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.none=None
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.error=Error
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.info=Info
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_lcd_185.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_lcd_185.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_lcd_185.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_lcd_185.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_lcd_185.menu.EraseFlash.all.upload.erase_cmd=-e
+
+waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.default=Disabled
+waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.default.build.zigbee_mode=
+waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.default.build.zigbee_libs=
+waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+waveshare_esp32_s3_lcd_185.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_146.name=Waveshare ESP32-S3-Touch-LCD-1.46
+waveshare_esp32_s3_touch_lcd_146.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_146.pid.0=0x8242
+waveshare_esp32_s3_touch_lcd_146.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_146.upload_port.0.pid=0x8242
+
+waveshare_esp32_s3_touch_lcd_146.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_146.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_146.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_146.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_146.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_146.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_146.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_146.upload.flags=
+waveshare_esp32_s3_touch_lcd_146.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_146.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_146.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_146.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_146.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_146.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_146.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_146.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_146.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_146.build.core=esp32
+waveshare_esp32_s3_touch_lcd_146.build.variant=waveshare_esp32_s3_touch_lcd_146
+waveshare_esp32_s3_touch_lcd_146.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_146
+
+waveshare_esp32_s3_touch_lcd_146.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_146.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_146.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_146.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_146.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_146.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_146.build.flash_freq=120m
+waveshare_esp32_s3_touch_lcd_146.build.flash_mode=qio
+waveshare_esp32_s3_touch_lcd_146.build.boot=qio
+waveshare_esp32_s3_touch_lcd_146.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_146.build.partitions=default
+waveshare_esp32_s3_touch_lcd_146.build.defines=
+waveshare_esp32_s3_touch_lcd_146.build.loop_core=
+waveshare_esp32_s3_touch_lcd_146.build.event_core=
+waveshare_esp32_s3_touch_lcd_146.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_146.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.default=Disabled
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.default.build.copy_jtag_files=0
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.builtin=Integrated USB JTAG
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.external=FTDI Adapter
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.external.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.bridge=ESP USB Bridge
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+waveshare_esp32_s3_touch_lcd_146.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.enabled.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_146.menu.PSRAM.disabled.build.psram_type=qspi
+
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio120.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio=DIO 80MHz
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio.build.boot=dio
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.dio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi=OPI 80MHz
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi.build.flash_mode=dout
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi.build.boot=opi
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_146.menu.FlashMode.opi.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_146.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_146.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_146.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_146.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_146.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_146.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+waveshare_esp32_s3_touch_lcd_146.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_146.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+waveshare_esp32_s3_touch_lcd_146.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_146.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_146.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_146.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_146.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_146.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_146.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_146.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_146.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_146.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_146.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_146.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_146.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_146.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_146.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_146.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_146.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_fs.build.partitions=no_fs
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_146.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_146.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_146.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_146.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_146.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_146.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_146.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_146.menu.EraseFlash.all.upload.erase_cmd=-e
+
+waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.default=Disabled
+waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.default.build.zigbee_mode=
+waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.default.build.zigbee_libs=
+waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+waveshare_esp32_s3_touch_lcd_146.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+waveshare_esp32_s3_lcd_146.name=Waveshare ESP32-S3-LCD-1.46
+waveshare_esp32_s3_lcd_146.vid.0=0x303a
+waveshare_esp32_s3_lcd_146.pid.0=0x8242
+waveshare_esp32_s3_lcd_146.upload_port.0.vid=0x303a
+waveshare_esp32_s3_lcd_146.upload_port.0.pid=0x8242
+
+waveshare_esp32_s3_lcd_146.bootloader.tool=esptool_py
+waveshare_esp32_s3_lcd_146.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_lcd_146.upload.tool=esptool_py
+waveshare_esp32_s3_lcd_146.upload.tool.default=esptool_py
+waveshare_esp32_s3_lcd_146.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_lcd_146.upload.maximum_size=1310720
+waveshare_esp32_s3_lcd_146.upload.maximum_data_size=327680
+waveshare_esp32_s3_lcd_146.upload.flags=
+waveshare_esp32_s3_lcd_146.upload.extra_flags=
+waveshare_esp32_s3_lcd_146.upload.use_1200bps_touch=false
+waveshare_esp32_s3_lcd_146.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_lcd_146.serial.disableDTR=false
+waveshare_esp32_s3_lcd_146.serial.disableRTS=false
+
+waveshare_esp32_s3_lcd_146.build.tarch=xtensa
+waveshare_esp32_s3_lcd_146.build.bootloader_addr=0x0
+waveshare_esp32_s3_lcd_146.build.target=esp32s3
+waveshare_esp32_s3_lcd_146.build.mcu=esp32s3
+waveshare_esp32_s3_lcd_146.build.core=esp32
+waveshare_esp32_s3_lcd_146.build.variant=waveshare_esp32_s3_lcd_146
+waveshare_esp32_s3_lcd_146.build.board=WAVESHARE_ESP32_S3_LCD_146
+
+waveshare_esp32_s3_lcd_146.build.usb_mode=1
+waveshare_esp32_s3_lcd_146.build.cdc_on_boot=0
+waveshare_esp32_s3_lcd_146.build.msc_on_boot=0
+waveshare_esp32_s3_lcd_146.build.dfu_on_boot=0
+waveshare_esp32_s3_lcd_146.build.f_cpu=240000000L
+waveshare_esp32_s3_lcd_146.build.flash_size=16MB
+waveshare_esp32_s3_lcd_146.build.flash_freq=120m
+waveshare_esp32_s3_lcd_146.build.flash_mode=qio
+waveshare_esp32_s3_lcd_146.build.boot=qio
+waveshare_esp32_s3_lcd_146.build.boot_freq=80m
+waveshare_esp32_s3_lcd_146.build.partitions=default
+waveshare_esp32_s3_lcd_146.build.defines=
+waveshare_esp32_s3_lcd_146.build.loop_core=
+waveshare_esp32_s3_lcd_146.build.event_core=
+waveshare_esp32_s3_lcd_146.build.psram_type=opi
+waveshare_esp32_s3_lcd_146.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.default=Disabled
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.default.build.copy_jtag_files=0
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.builtin=Integrated USB JTAG
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.external=FTDI Adapter
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.external.build.copy_jtag_files=1
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.bridge=ESP USB Bridge
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+waveshare_esp32_s3_lcd_146.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+waveshare_esp32_s3_lcd_146.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_lcd_146.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_lcd_146.menu.PSRAM.enabled.build.psram_type=opi
+waveshare_esp32_s3_lcd_146.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_lcd_146.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_lcd_146.menu.PSRAM.disabled.build.psram_type=qspi
+
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio120.build.flash_freq=80m
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_lcd_146.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_lcd_146.menu.FlashMode.dio=DIO 80MHz
+waveshare_esp32_s3_lcd_146.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32_s3_lcd_146.menu.FlashMode.dio.build.boot=dio
+waveshare_esp32_s3_lcd_146.menu.FlashMode.dio.build.boot_freq=80m
+waveshare_esp32_s3_lcd_146.menu.FlashMode.dio.build.flash_freq=80m
+waveshare_esp32_s3_lcd_146.menu.FlashMode.opi=OPI 80MHz
+waveshare_esp32_s3_lcd_146.menu.FlashMode.opi.build.flash_mode=dout
+waveshare_esp32_s3_lcd_146.menu.FlashMode.opi.build.boot=opi
+waveshare_esp32_s3_lcd_146.menu.FlashMode.opi.build.boot_freq=80m
+waveshare_esp32_s3_lcd_146.menu.FlashMode.opi.build.flash_freq=80m
+
+waveshare_esp32_s3_lcd_146.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_lcd_146.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_lcd_146.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_lcd_146.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_lcd_146.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_lcd_146.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+waveshare_esp32_s3_lcd_146.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_lcd_146.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+waveshare_esp32_s3_lcd_146.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_lcd_146.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_lcd_146.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_lcd_146.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_lcd_146.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_146.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_lcd_146.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_lcd_146.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_lcd_146.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_146.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_lcd_146.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_lcd_146.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_lcd_146.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_146.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_lcd_146.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_lcd_146.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_lcd_146.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_lcd_146.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_lcd_146.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_lcd_146.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_lcd_146.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_lcd_146.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_fs.build.partitions=no_fs
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_lcd_146.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_lcd_146.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_lcd_146.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.none=None
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.error=Error
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.info=Info
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_lcd_146.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_lcd_146.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_lcd_146.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_lcd_146.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_lcd_146.menu.EraseFlash.all.upload.erase_cmd=-e
+
+waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.default=Disabled
+waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.default.build.zigbee_mode=
+waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.default.build.zigbee_libs=
+waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+waveshare_esp32_s3_lcd_146.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_185_box.name=Waveshare ESP32-S3-Touch-LCD-1.85-BOX
+waveshare_esp32_s3_touch_lcd_185_box.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_185_box.pid.0=0x8242
+waveshare_esp32_s3_touch_lcd_185_box.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_185_box.upload_port.0.pid=0x8242
+
+waveshare_esp32_s3_touch_lcd_185_box.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_185_box.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_185_box.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_185_box.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_185_box.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_185_box.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_185_box.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_185_box.upload.flags=
+waveshare_esp32_s3_touch_lcd_185_box.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_185_box.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_185_box.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_185_box.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_185_box.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_185_box.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_185_box.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_185_box.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_185_box.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_185_box.build.core=esp32
+waveshare_esp32_s3_touch_lcd_185_box.build.variant=waveshare_esp32_s3_touch_lcd_185_box
+waveshare_esp32_s3_touch_lcd_185_box.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_185_BOX
+
+waveshare_esp32_s3_touch_lcd_185_box.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_185_box.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_185_box.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_185_box.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_185_box.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_185_box.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_185_box.build.flash_freq=120m
+waveshare_esp32_s3_touch_lcd_185_box.build.flash_mode=qio
+waveshare_esp32_s3_touch_lcd_185_box.build.boot=qio
+waveshare_esp32_s3_touch_lcd_185_box.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_185_box.build.partitions=default
+waveshare_esp32_s3_touch_lcd_185_box.build.defines=
+waveshare_esp32_s3_touch_lcd_185_box.build.loop_core=
+waveshare_esp32_s3_touch_lcd_185_box.build.event_core=
+waveshare_esp32_s3_touch_lcd_185_box.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_185_box.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.default=Disabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.default.build.copy_jtag_files=0
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.builtin=Integrated USB JTAG
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.external=FTDI Adapter
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.external.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.bridge=ESP USB Bridge
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+waveshare_esp32_s3_touch_lcd_185_box.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.enabled.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_185_box.menu.PSRAM.disabled.build.psram_type=qspi
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio120.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio=DIO 80MHz
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio.build.boot=dio
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.dio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi=OPI 80MHz
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi.build.flash_mode=dout
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi.build.boot=opi
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_185_box.menu.FlashMode.opi.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_185_box.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_185_box.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_185_box.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_185_box.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+waveshare_esp32_s3_touch_lcd_185_box.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_185_box.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_185_box.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_185_box.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_185_box.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_185_box.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_185_box.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_185_box.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_185_box.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_185_box.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_fs.build.partitions=no_fs
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_185_box.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_185_box.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_185_box.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_185_box.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_185_box.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.EraseFlash.all.upload.erase_cmd=-e
+
+waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.default=Disabled
+waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.default.build.zigbee_mode=
+waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.default.build.zigbee_libs=
+waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+waveshare_esp32_s3_touch_lcd_185_box.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+waveshare_esp32_s3_lcd_147.name=Waveshare ESP32-S3-LCD-1.47
+waveshare_esp32_s3_lcd_147.vid.0=0x303a
+waveshare_esp32_s3_lcd_147.pid.0=0x8242
+waveshare_esp32_s3_lcd_147.upload_port.0.vid=0x303a
+waveshare_esp32_s3_lcd_147.upload_port.0.pid=0x8242
+
+waveshare_esp32_s3_lcd_147.bootloader.tool=esptool_py
+waveshare_esp32_s3_lcd_147.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_lcd_147.upload.tool=esptool_py
+waveshare_esp32_s3_lcd_147.upload.tool.default=esptool_py
+waveshare_esp32_s3_lcd_147.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_lcd_147.upload.maximum_size=1310720
+waveshare_esp32_s3_lcd_147.upload.maximum_data_size=327680
+waveshare_esp32_s3_lcd_147.upload.flags=
+waveshare_esp32_s3_lcd_147.upload.extra_flags=
+waveshare_esp32_s3_lcd_147.upload.use_1200bps_touch=false
+waveshare_esp32_s3_lcd_147.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_lcd_147.serial.disableDTR=false
+waveshare_esp32_s3_lcd_147.serial.disableRTS=false
+
+waveshare_esp32_s3_lcd_147.build.tarch=xtensa
+waveshare_esp32_s3_lcd_147.build.bootloader_addr=0x0
+waveshare_esp32_s3_lcd_147.build.target=esp32s3
+waveshare_esp32_s3_lcd_147.build.mcu=esp32s3
+waveshare_esp32_s3_lcd_147.build.core=esp32
+waveshare_esp32_s3_lcd_147.build.variant=waveshare_esp32_s3_lcd_147
+waveshare_esp32_s3_lcd_147.build.board=WAVESHARE_ESP32_S3_LCD_147
+
+waveshare_esp32_s3_lcd_147.build.usb_mode=1
+waveshare_esp32_s3_lcd_147.build.cdc_on_boot=0
+waveshare_esp32_s3_lcd_147.build.msc_on_boot=0
+waveshare_esp32_s3_lcd_147.build.dfu_on_boot=0
+waveshare_esp32_s3_lcd_147.build.f_cpu=240000000L
+waveshare_esp32_s3_lcd_147.build.flash_size=16MB
+waveshare_esp32_s3_lcd_147.build.flash_freq=80m
+waveshare_esp32_s3_lcd_147.build.flash_mode=qio
+waveshare_esp32_s3_lcd_147.build.boot=qio
+waveshare_esp32_s3_lcd_147.build.boot_freq=80m
+waveshare_esp32_s3_lcd_147.build.partitions=default
+waveshare_esp32_s3_lcd_147.build.defines=
+waveshare_esp32_s3_lcd_147.build.loop_core=
+waveshare_esp32_s3_lcd_147.build.event_core=
+waveshare_esp32_s3_lcd_147.build.psram_type=opi
+waveshare_esp32_s3_lcd_147.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.default=Disabled
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.default.build.copy_jtag_files=0
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.builtin=Integrated USB JTAG
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.external=FTDI Adapter
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.external.build.copy_jtag_files=1
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.bridge=ESP USB Bridge
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+waveshare_esp32_s3_lcd_147.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+waveshare_esp32_s3_lcd_147.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_lcd_147.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_lcd_147.menu.PSRAM.enabled.build.psram_type=opi
+waveshare_esp32_s3_lcd_147.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_lcd_147.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_lcd_147.menu.PSRAM.disabled.build.psram_type=qspi
+
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_lcd_147.menu.FlashMode.qio120.build.flash_freq=80m
+waveshare_esp32_s3_lcd_147.menu.FlashMode.dio=DIO 80MHz
+waveshare_esp32_s3_lcd_147.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32_s3_lcd_147.menu.FlashMode.dio.build.boot=dio
+waveshare_esp32_s3_lcd_147.menu.FlashMode.dio.build.boot_freq=80m
+waveshare_esp32_s3_lcd_147.menu.FlashMode.dio.build.flash_freq=80m
+waveshare_esp32_s3_lcd_147.menu.FlashMode.opi=OPI 80MHz
+waveshare_esp32_s3_lcd_147.menu.FlashMode.opi.build.flash_mode=dout
+waveshare_esp32_s3_lcd_147.menu.FlashMode.opi.build.boot=opi
+waveshare_esp32_s3_lcd_147.menu.FlashMode.opi.build.boot_freq=80m
+waveshare_esp32_s3_lcd_147.menu.FlashMode.opi.build.flash_freq=80m
+
+waveshare_esp32_s3_lcd_147.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_lcd_147.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_lcd_147.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_lcd_147.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_lcd_147.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_lcd_147.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_lcd_147.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_lcd_147.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_lcd_147.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_lcd_147.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_lcd_147.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_lcd_147.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_lcd_147.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_147.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_lcd_147.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_lcd_147.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_lcd_147.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_147.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_lcd_147.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_lcd_147.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_lcd_147.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_lcd_147.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_lcd_147.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_lcd_147.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_lcd_147.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_lcd_147.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_lcd_147.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_lcd_147.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_lcd_147.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_lcd_147.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_fs.build.partitions=no_fs
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_lcd_147.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_lcd_147.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_lcd_147.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.none=None
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.error=Error
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.info=Info
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_lcd_147.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_lcd_147.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_lcd_147.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_lcd_147.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_lcd_147.menu.EraseFlash.all.upload.erase_cmd=-e
+
+waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.default=Disabled
+waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.default.build.zigbee_mode=
+waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.default.build.zigbee_libs=
+waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+waveshare_esp32_s3_lcd_147.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_21.name=Waveshare ESP32-S3-Touch-LCD-2.1
+waveshare_esp32_s3_touch_lcd_21.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_21.pid.0=0x8242
+waveshare_esp32_s3_touch_lcd_21.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_21.upload_port.0.pid=0x8242
+
+waveshare_esp32_s3_touch_lcd_21.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_21.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_21.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_21.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_21.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_21.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_21.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_21.upload.flags=
+waveshare_esp32_s3_touch_lcd_21.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_21.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_21.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_21.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_21.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_21.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_21.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_21.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_21.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_21.build.core=esp32
+waveshare_esp32_s3_touch_lcd_21.build.variant=waveshare_esp32_s3_touch_lcd_21
+waveshare_esp32_s3_touch_lcd_21.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_21
+
+waveshare_esp32_s3_touch_lcd_21.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_21.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_21.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_21.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_21.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_21.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_21.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_21.build.flash_mode=qio
+waveshare_esp32_s3_touch_lcd_21.build.boot=qio
+waveshare_esp32_s3_touch_lcd_21.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_21.build.partitions=default
+waveshare_esp32_s3_touch_lcd_21.build.defines=
+waveshare_esp32_s3_touch_lcd_21.build.loop_core=
+waveshare_esp32_s3_touch_lcd_21.build.event_core=
+waveshare_esp32_s3_touch_lcd_21.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_21.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.default=Disabled
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.default.build.copy_jtag_files=0
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.builtin=Integrated USB JTAG
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.external=FTDI Adapter
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.external.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.bridge=ESP USB Bridge
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+waveshare_esp32_s3_touch_lcd_21.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.enabled.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_21.menu.PSRAM.disabled.build.psram_type=qspi
+
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.qio120.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio=DIO 80MHz
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio.build.boot=dio
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.dio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi=OPI 80MHz
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi.build.flash_mode=dout
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi.build.boot=opi
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_21.menu.FlashMode.opi.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_21.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_21.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_21.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_21.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_21.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_21.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_21.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_21.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_21.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_21.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_21.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_21.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_21.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_21.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_21.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_21.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_21.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_21.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_21.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_21.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_21.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_21.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_21.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_21.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_21.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_fs.build.partitions=no_fs
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_21.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_21.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_21.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_21.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_21.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_21.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_21.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_21.menu.EraseFlash.all.upload.erase_cmd=-e
+
+waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.default=Disabled
+waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.default.build.zigbee_mode=
+waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.default.build.zigbee_libs=
+waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+waveshare_esp32_s3_touch_lcd_21.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+waveshare_esp32_s3_touch_lcd_28.name=Waveshare ESP32-S3-Touch-LCD-2.8
+waveshare_esp32_s3_touch_lcd_28.vid.0=0x303a
+waveshare_esp32_s3_touch_lcd_28.pid.0=0x8242
+waveshare_esp32_s3_touch_lcd_28.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_lcd_28.upload_port.0.pid=0x8242
+
+waveshare_esp32_s3_touch_lcd_28.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_28.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_lcd_28.upload.tool=esptool_py
+waveshare_esp32_s3_touch_lcd_28.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_lcd_28.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_lcd_28.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_28.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_lcd_28.upload.flags=
+waveshare_esp32_s3_touch_lcd_28.upload.extra_flags=
+waveshare_esp32_s3_touch_lcd_28.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_28.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_lcd_28.serial.disableDTR=false
+waveshare_esp32_s3_touch_lcd_28.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_lcd_28.build.tarch=xtensa
+waveshare_esp32_s3_touch_lcd_28.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_lcd_28.build.target=esp32s3
+waveshare_esp32_s3_touch_lcd_28.build.mcu=esp32s3
+waveshare_esp32_s3_touch_lcd_28.build.core=esp32
+waveshare_esp32_s3_touch_lcd_28.build.variant=waveshare_esp32_s3_touch_lcd_28
+waveshare_esp32_s3_touch_lcd_28.build.board=WAVESHARE_ESP32_S3_TOUCH_LCD_28
+
+waveshare_esp32_s3_touch_lcd_28.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_28.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_28.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_28.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_28.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_28.build.flash_size=16MB
+waveshare_esp32_s3_touch_lcd_28.build.flash_freq=120m
+waveshare_esp32_s3_touch_lcd_28.build.flash_mode=qio
+waveshare_esp32_s3_touch_lcd_28.build.boot=qio
+waveshare_esp32_s3_touch_lcd_28.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_28.build.partitions=default
+waveshare_esp32_s3_touch_lcd_28.build.defines=
+waveshare_esp32_s3_touch_lcd_28.build.loop_core=
+waveshare_esp32_s3_touch_lcd_28.build.event_core=
+waveshare_esp32_s3_touch_lcd_28.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_28.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.default=Disabled
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.default.build.copy_jtag_files=0
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.builtin=Integrated USB JTAG
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.external=FTDI Adapter
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.external.build.copy_jtag_files=1
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.bridge=ESP USB Bridge
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+waveshare_esp32_s3_touch_lcd_28.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.enabled.build.psram_type=opi
+waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_lcd_28.menu.PSRAM.disabled.build.psram_type=qspi
+
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio120.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio=DIO 80MHz
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio.build.boot=dio
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.dio.build.flash_freq=80m
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi=OPI 80MHz
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi.build.flash_mode=dout
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi.build.boot=opi
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi.build.boot_freq=80m
+waveshare_esp32_s3_touch_lcd_28.menu.FlashMode.opi.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_lcd_28.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_28.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_lcd_28.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_28.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_lcd_28.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_lcd_28.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+waveshare_esp32_s3_touch_lcd_28.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_lcd_28.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+
+waveshare_esp32_s3_touch_lcd_28.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_lcd_28.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_lcd_28.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_lcd_28.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_lcd_28.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_28.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_lcd_28.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_lcd_28.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_28.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_28.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_lcd_28.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_28.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_28.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_lcd_28.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_lcd_28.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_lcd_28.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_lcd_28.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_fs.build.partitions=no_fs
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_lcd_28.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_lcd_28.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_lcd_28.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_lcd_28.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_lcd_28.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_lcd_28.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_lcd_28.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_lcd_28.menu.EraseFlash.all.upload.erase_cmd=-e
+
+waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.default=Disabled
+waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.default.build.zigbee_mode=
+waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.default.build.zigbee_libs=
+waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+waveshare_esp32_s3_touch_lcd_28.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+waveshare_esp32_s3_relay_6ch.name=Waveshare ESP32-S3-Relay-6CH
+waveshare_esp32_s3_relay_6ch.vid.0=0x303a
+waveshare_esp32_s3_relay_6ch.pid.0=0x8242
+waveshare_esp32_s3_relay_6ch.upload_port.0.vid=0x303a
+waveshare_esp32_s3_relay_6ch.upload_port.0.pid=0x8242
+
+waveshare_esp32_s3_relay_6ch.bootloader.tool=esptool_py
+waveshare_esp32_s3_relay_6ch.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_relay_6ch.upload.tool=esptool_py
+waveshare_esp32_s3_relay_6ch.upload.tool.default=esptool_py
+waveshare_esp32_s3_relay_6ch.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_relay_6ch.upload.maximum_size=1310720
+waveshare_esp32_s3_relay_6ch.upload.maximum_data_size=327680
+waveshare_esp32_s3_relay_6ch.upload.flags=
+waveshare_esp32_s3_relay_6ch.upload.extra_flags=
+waveshare_esp32_s3_relay_6ch.upload.use_1200bps_touch=false
+waveshare_esp32_s3_relay_6ch.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_relay_6ch.serial.disableDTR=false
+waveshare_esp32_s3_relay_6ch.serial.disableRTS=false
+
+waveshare_esp32_s3_relay_6ch.build.tarch=xtensa
+waveshare_esp32_s3_relay_6ch.build.bootloader_addr=0x0
+waveshare_esp32_s3_relay_6ch.build.target=esp32s3
+waveshare_esp32_s3_relay_6ch.build.mcu=esp32s3
+waveshare_esp32_s3_relay_6ch.build.core=esp32
+waveshare_esp32_s3_relay_6ch.build.variant=waveshare_esp32_s3_relay_6ch
+waveshare_esp32_s3_relay_6ch.build.board=WAVESHARE_ESP32_S3_RELAY_6CH
+
+waveshare_esp32_s3_relay_6ch.build.usb_mode=1
+waveshare_esp32_s3_relay_6ch.build.cdc_on_boot=0
+waveshare_esp32_s3_relay_6ch.build.msc_on_boot=0
+waveshare_esp32_s3_relay_6ch.build.dfu_on_boot=0
+waveshare_esp32_s3_relay_6ch.build.f_cpu=240000000L
+waveshare_esp32_s3_relay_6ch.build.flash_size=8MB
+waveshare_esp32_s3_relay_6ch.build.flash_freq=80m
+waveshare_esp32_s3_relay_6ch.build.flash_mode=qio
+waveshare_esp32_s3_relay_6ch.build.boot=qio
+waveshare_esp32_s3_relay_6ch.build.boot_freq=80m
+waveshare_esp32_s3_relay_6ch.build.partitions=default
+waveshare_esp32_s3_relay_6ch.build.defines=
+waveshare_esp32_s3_relay_6ch.build.loop_core=
+waveshare_esp32_s3_relay_6ch.build.event_core=
+waveshare_esp32_s3_relay_6ch.build.psram_type=
+waveshare_esp32_s3_relay_6ch.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.default=Disabled
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.default.build.copy_jtag_files=0
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.builtin=Integrated USB JTAG
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.external=FTDI Adapter
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.external.build.copy_jtag_files=1
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.bridge=ESP USB Bridge
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+waveshare_esp32_s3_relay_6ch.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+waveshare_esp32_s3_relay_6ch.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_relay_6ch.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_relay_6ch.menu.PSRAM.disabled.build.psram_type=qspi
+
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.qio120.build.flash_freq=80m
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio=DIO 80MHz
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio.build.flash_mode=dio
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio.build.boot=dio
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio.build.boot_freq=80m
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.dio.build.flash_freq=80m
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi=OPI 80MHz
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi.build.flash_mode=dout
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi.build.boot=opi
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi.build.boot_freq=80m
+waveshare_esp32_s3_relay_6ch.menu.FlashMode.opi.build.flash_freq=80m
+
+waveshare_esp32_s3_relay_6ch.menu.FlashSize.8M=8MB (64Mb)
+waveshare_esp32_s3_relay_6ch.menu.FlashSize.8M.build.flash_size=8MB
+waveshare_esp32_s3_relay_6ch.menu.FlashSize.8M.build.partitions=default_8MB
+waveshare_esp32_s3_relay_6ch.menu.FlashSize.16M=16MB (128Mb)
+waveshare_esp32_s3_relay_6ch.menu.FlashSize.16M.build.flash_size=16MB
+
+waveshare_esp32_s3_relay_6ch.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_relay_6ch.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_relay_6ch.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_relay_6ch.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_relay_6ch.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_relay_6ch.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_relay_6ch.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_relay_6ch.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_relay_6ch.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_relay_6ch.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_relay_6ch.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_relay_6ch.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_relay_6ch.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_relay_6ch.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_relay_6ch.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_relay_6ch.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_relay_6ch.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_relay_6ch.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_relay_6ch.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_relay_6ch.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_relay_6ch.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_relay_6ch.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_relay_6ch.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_relay_6ch.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_relay_6ch.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_relay_6ch.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_relay_6ch.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_relay_6ch.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_relay_6ch.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_relay_6ch.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.minimal.build.partitions=minimal
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_fs.build.partitions=no_fs
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_relay_6ch.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_relay_6ch.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_relay_6ch.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.none=None
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.error=Error
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.info=Info
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_relay_6ch.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_relay_6ch.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_relay_6ch.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_relay_6ch.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_relay_6ch.menu.EraseFlash.all.upload.erase_cmd=-e
+
+waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.default=Disabled
+waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.default.build.zigbee_mode=
+waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.default.build.zigbee_libs=
+waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+waveshare_esp32_s3_relay_6ch.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
+
+waveshare_esp32_s3_touch_amoled_164.name=Waveshare ESP32-S3-Touch-AMOLED-1.64
+waveshare_esp32_s3_touch_amoled_164.vid.0=0x303a
+waveshare_esp32_s3_touch_amoled_164.pid.0=0x8249
+waveshare_esp32_s3_touch_amoled_164.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_amoled_164.upload_port.0.pid=0x8249
+
+waveshare_esp32_s3_touch_amoled_164.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_164.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_amoled_164.upload.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_164.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_amoled_164.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_amoled_164.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_amoled_164.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_amoled_164.upload.flags=
+waveshare_esp32_s3_touch_amoled_164.upload.extra_flags=
+waveshare_esp32_s3_touch_amoled_164.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_164.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_amoled_164.serial.disableDTR=false
+waveshare_esp32_s3_touch_amoled_164.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_amoled_164.build.tarch=xtensa
+waveshare_esp32_s3_touch_amoled_164.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_amoled_164.build.target=esp32s3
+waveshare_esp32_s3_touch_amoled_164.build.mcu=esp32s3
+waveshare_esp32_s3_touch_amoled_164.build.core=esp32
+waveshare_esp32_s3_touch_amoled_164.build.variant=waveshare_esp32_s3_touch_amoled_164
+waveshare_esp32_s3_touch_amoled_164.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_164
+
+waveshare_esp32_s3_touch_amoled_164.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_164.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_164.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_164.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_164.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_164.build.flash_size=16MB
+
+waveshare_esp32_s3_touch_amoled_164.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_164.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_164.build.boot=qio
+waveshare_esp32_s3_touch_amoled_164.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_164.build.partitions=default
+waveshare_esp32_s3_touch_amoled_164.build.defines=
+waveshare_esp32_s3_touch_amoled_164.build.loop_core=
+waveshare_esp32_s3_touch_amoled_164.build.event_core=
+waveshare_esp32_s3_touch_amoled_164.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_164.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_amoled_164.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_amoled_164.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_amoled_164.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_164.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_164.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_164.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_164.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_164.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_164.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_164.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_164.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_amoled_164.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_164.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_amoled_164.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_amoled_164.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_164.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_164.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_amoled_164.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_164.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_164.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_164.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_164.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_164.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_164.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_164.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_164.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_amoled_164.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_amoled_164.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_amoled_164.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_amoled_164.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_amoled_164.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_amoled_164.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_amoled_164.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_amoled_164.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_amoled_164.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_amoled_143.name=Waveshare ESP32-S3-Touch-AMOLED-1.43
+waveshare_esp32_s3_touch_amoled_143.vid.0=0x303a
+waveshare_esp32_s3_touch_amoled_143.pid.0=0x824a
+waveshare_esp32_s3_touch_amoled_143.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_amoled_143.upload_port.0.pid=0x824a
+
+waveshare_esp32_s3_touch_amoled_143.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_143.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_amoled_143.upload.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_143.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_amoled_143.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_amoled_143.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_amoled_143.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_amoled_143.upload.flags=
+waveshare_esp32_s3_touch_amoled_143.upload.extra_flags=
+waveshare_esp32_s3_touch_amoled_143.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_143.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_amoled_143.serial.disableDTR=false
+waveshare_esp32_s3_touch_amoled_143.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_amoled_143.build.tarch=xtensa
+waveshare_esp32_s3_touch_amoled_143.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_amoled_143.build.target=esp32s3
+waveshare_esp32_s3_touch_amoled_143.build.mcu=esp32s3
+waveshare_esp32_s3_touch_amoled_143.build.core=esp32
+waveshare_esp32_s3_touch_amoled_143.build.variant=waveshare_esp32_s3_touch_amoled_143
+waveshare_esp32_s3_touch_amoled_143.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_143
+
+waveshare_esp32_s3_touch_amoled_143.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_143.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_143.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_143.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_143.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_143.build.flash_size=16MB
+
+waveshare_esp32_s3_touch_amoled_143.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_143.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_143.build.boot=qio
+waveshare_esp32_s3_touch_amoled_143.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_143.build.partitions=default
+waveshare_esp32_s3_touch_amoled_143.build.defines=
+waveshare_esp32_s3_touch_amoled_143.build.loop_core=
+waveshare_esp32_s3_touch_amoled_143.build.event_core=
+waveshare_esp32_s3_touch_amoled_143.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_143.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_amoled_143.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_amoled_143.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_amoled_143.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_143.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_143.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_143.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_143.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_143.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_143.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_143.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_143.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_amoled_143.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_143.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_amoled_143.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_amoled_143.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_143.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_143.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_amoled_143.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_143.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_143.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_143.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_143.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_143.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_143.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_143.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_143.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_amoled_143.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_amoled_143.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_amoled_143.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_amoled_143.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_amoled_143.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_amoled_143.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_amoled_143.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_amoled_143.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_amoled_143.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+waveshare_esp32_s3_touch_amoled_191.name=Waveshare ESP32-S3-Touch-AMOLED-1.91
+waveshare_esp32_s3_touch_amoled_191.vid.0=0x303a
+waveshare_esp32_s3_touch_amoled_191.pid.0=0x824b
+waveshare_esp32_s3_touch_amoled_191.upload_port.0.vid=0x303a
+waveshare_esp32_s3_touch_amoled_191.upload_port.0.pid=0x824b
+
+waveshare_esp32_s3_touch_amoled_191.bootloader.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_191.bootloader.tool.default=esptool_py
+
+waveshare_esp32_s3_touch_amoled_191.upload.tool=esptool_py
+waveshare_esp32_s3_touch_amoled_191.upload.tool.default=esptool_py
+waveshare_esp32_s3_touch_amoled_191.upload.tool.network=esp_ota
+
+waveshare_esp32_s3_touch_amoled_191.upload.maximum_size=1310720
+
+waveshare_esp32_s3_touch_amoled_191.upload.maximum_data_size=327680
+waveshare_esp32_s3_touch_amoled_191.upload.flags=
+waveshare_esp32_s3_touch_amoled_191.upload.extra_flags=
+waveshare_esp32_s3_touch_amoled_191.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_191.upload.wait_for_upload_port=false
+
+waveshare_esp32_s3_touch_amoled_191.serial.disableDTR=false
+waveshare_esp32_s3_touch_amoled_191.serial.disableRTS=false
+
+waveshare_esp32_s3_touch_amoled_191.build.tarch=xtensa
+waveshare_esp32_s3_touch_amoled_191.build.bootloader_addr=0x0
+waveshare_esp32_s3_touch_amoled_191.build.target=esp32s3
+waveshare_esp32_s3_touch_amoled_191.build.mcu=esp32s3
+waveshare_esp32_s3_touch_amoled_191.build.core=esp32
+waveshare_esp32_s3_touch_amoled_191.build.variant=waveshare_esp32_s3_touch_amoled_191
+waveshare_esp32_s3_touch_amoled_191.build.board=WAVESHARE_ESP32_S3_TOUCH_AMOLED_191
+
+waveshare_esp32_s3_touch_amoled_191.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_191.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_191.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_191.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_191.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_191.build.flash_size=16MB
+
+waveshare_esp32_s3_touch_amoled_191.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_191.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_191.build.boot=qio
+waveshare_esp32_s3_touch_amoled_191.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_191.build.partitions=default
+waveshare_esp32_s3_touch_amoled_191.build.defines=
+waveshare_esp32_s3_touch_amoled_191.build.loop_core=
+waveshare_esp32_s3_touch_amoled_191.build.event_core=
+waveshare_esp32_s3_touch_amoled_191.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_191.build.memory_type={build.boot}_{build.psram_type}
+
+waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.disabled=Disabled
+waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.disabled.build.defines=
+waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.disabled.build.psram_type=qspi
+waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.enabled=Enabled
+waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+waveshare_esp32_s3_touch_amoled_191.menu.PSRAM.enabled.build.psram_type=opi
+
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio=QIO 80MHz
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio.build.boot=qio
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio.build.boot_freq=80m
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio.build.flash_freq=80m
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120=QIO 120MHz
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120.build.flash_mode=dio
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120.build.boot=qio
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120.build.boot_freq=120m
+waveshare_esp32_s3_touch_amoled_191.menu.FlashMode.qio120.build.flash_freq=80m
+
+waveshare_esp32_s3_touch_amoled_191.menu.LoopCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_191.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_191.menu.LoopCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_191.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_191.menu.EventsCore.1=Core 1
+waveshare_esp32_s3_touch_amoled_191.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+waveshare_esp32_s3_touch_amoled_191.menu.EventsCore.0=Core 0
+waveshare_esp32_s3_touch_amoled_191.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+waveshare_esp32_s3_touch_amoled_191.menu.USBMode.hwcdc=Hardware CDC and JTAG
+waveshare_esp32_s3_touch_amoled_191.menu.USBMode.hwcdc.build.usb_mode=1
+waveshare_esp32_s3_touch_amoled_191.menu.USBMode.default=USB-OTG (TinyUSB)
+waveshare_esp32_s3_touch_amoled_191.menu.USBMode.default.build.usb_mode=0
+
+waveshare_esp32_s3_touch_amoled_191.menu.CDCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_191.menu.CDCOnBoot.default.build.cdc_on_boot=0
+waveshare_esp32_s3_touch_amoled_191.menu.CDCOnBoot.cdc=Enabled
+waveshare_esp32_s3_touch_amoled_191.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_191.menu.MSCOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_191.menu.MSCOnBoot.default.build.msc_on_boot=0
+waveshare_esp32_s3_touch_amoled_191.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_191.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_191.menu.DFUOnBoot.default=Disabled
+waveshare_esp32_s3_touch_amoled_191.menu.DFUOnBoot.default.build.dfu_on_boot=0
+waveshare_esp32_s3_touch_amoled_191.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+waveshare_esp32_s3_touch_amoled_191.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.default=UART0 / Hardware CDC
+waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.default.upload.use_1200bps_touch=false
+waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.default.upload.wait_for_upload_port=false
+waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+waveshare_esp32_s3_touch_amoled_191.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.default.build.partitions=default
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.no_ota.build.partitions=no_ota
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.huge_app.build.partitions=huge_app
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker=RainMaker 4MB
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.fatflash.build.partitions=ffat
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.otanofs=OTA no FS (2MB APP with OTA)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.otanofs.build.custom_partitions=partitions_otanofs_4MB
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.otanofs.upload.maximum_size=2031616
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.all_app=Max APP (4MB APP no OTA)
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.all_app.build.custom_partitions=partitions_all_app_4MB
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.all_app.upload.maximum_size=4128768
+
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.custom=Custom
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.custom.build.partitions=
+waveshare_esp32_s3_touch_amoled_191.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.240=240MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.240.build.f_cpu=240000000L
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.160=160MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.160.build.f_cpu=160000000L
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.80=80MHz (WiFi)
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.80.build.f_cpu=80000000L
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.40=40MHz
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.40.build.f_cpu=40000000L
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.20=20MHz
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.20.build.f_cpu=20000000L
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.10=10MHz
+waveshare_esp32_s3_touch_amoled_191.menu.CPUFreq.10.build.f_cpu=10000000L
+
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.921600=921600
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.921600.upload.speed=921600
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.115200=115200
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.115200.upload.speed=115200
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.256000.windows=256000
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.256000.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.230400.windows.upload.speed=256000
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.230400=230400
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.230400.upload.speed=230400
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.460800.linux=460800
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.460800.macosx=460800
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.460800.upload.speed=460800
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.512000.windows=512000
+waveshare_esp32_s3_touch_amoled_191.menu.UploadSpeed.512000.upload.speed=512000
+
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.none=None
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.none.build.code_debug=0
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.error=Error
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.error.build.code_debug=1
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.warn=Warn
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.warn.build.code_debug=2
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.info=Info
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.info.build.code_debug=3
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.debug=Debug
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.debug.build.code_debug=4
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.verbose=Verbose
+waveshare_esp32_s3_touch_amoled_191.menu.DebugLevel.verbose.build.code_debug=5
+
+waveshare_esp32_s3_touch_amoled_191.menu.EraseFlash.none=Disabled
+waveshare_esp32_s3_touch_amoled_191.menu.EraseFlash.none.upload.erase_cmd=
+waveshare_esp32_s3_touch_amoled_191.menu.EraseFlash.all=Enabled
+waveshare_esp32_s3_touch_amoled_191.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+
+Pcbcupid_GLYPH_C3.name=Pcbcupid GLYPH C3
+Pcbcupid_GLYPH_C3.vid.0=0x2886
+Pcbcupid_GLYPH_C3.pid.0=0x0046
+
+Pcbcupid_GLYPH_C3.bootloader.tool=esptool_py
+Pcbcupid_GLYPH_C3.bootloader.tool.default=esptool_py
+
+Pcbcupid_GLYPH_C3.upload.tool=esptool_py
+Pcbcupid_GLYPH_C3.upload.tool.default=esptool_py
+Pcbcupid_GLYPH_C3.upload.tool.network=esp_ota
+
+Pcbcupid_GLYPH_C3.upload.maximum_size=1310720
+Pcbcupid_GLYPH_C3.upload.maximum_data_size=327680
+Pcbcupid_GLYPH_C3.upload.flags=
+Pcbcupid_GLYPH_C3.upload.extra_flags=
+Pcbcupid_GLYPH_C3.upload.use_1200bps_touch=false
+Pcbcupid_GLYPH_C3.upload.wait_for_upload_port=false
+
+Pcbcupid_GLYPH_C3.serial.disableDTR=false
+Pcbcupid_GLYPH_C3.serial.disableRTS=false
+
+Pcbcupid_GLYPH_C3.build.tarch=riscv32
+Pcbcupid_GLYPH_C3.build.target=esp
+Pcbcupid_GLYPH_C3.build.mcu=esp32c3
+Pcbcupid_GLYPH_C3.build.core=esp32
+Pcbcupid_GLYPH_C3.build.variant=Pcbcupid_GLYPH_C3
+Pcbcupid_GLYPH_C3.build.board=PCBCUPID_GLYPHC3
+Pcbcupid_GLYPH_C3.build.bootloader_addr=0x0
+
+Pcbcupid_GLYPH_C3.build.cdc_on_boot=1
+Pcbcupid_GLYPH_C3.build.f_cpu=160000000L
+Pcbcupid_GLYPH_C3.build.flash_size=4MB
+Pcbcupid_GLYPH_C3.build.flash_freq=80m
+Pcbcupid_GLYPH_C3.build.flash_mode=qio
+Pcbcupid_GLYPH_C3.build.boot=qio
+Pcbcupid_GLYPH_C3.build.partitions=default
+Pcbcupid_GLYPH_C3.build.defines=
+
+Pcbcupid_GLYPH_C3.menu.CDCOnBoot.default=Enabled
+Pcbcupid_GLYPH_C3.menu.CDCOnBoot.default.build.cdc_on_boot=1
+Pcbcupid_GLYPH_C3.menu.CDCOnBoot.cdc=Disabled
+Pcbcupid_GLYPH_C3.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.default.build.partitions=default
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.minimal.build.partitions=minimal
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+Pcbcupid_GLYPH_C3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+
+Pcbcupid_GLYPH_C3.menu.CPUFreq.160=160MHz (WiFi)
+Pcbcupid_GLYPH_C3.menu.CPUFreq.160.build.f_cpu=160000000L
+Pcbcupid_GLYPH_C3.menu.CPUFreq.80=80MHz (WiFi)
+Pcbcupid_GLYPH_C3.menu.CPUFreq.80.build.f_cpu=80000000L
+Pcbcupid_GLYPH_C3.menu.CPUFreq.40=40MHz
+Pcbcupid_GLYPH_C3.menu.CPUFreq.40.build.f_cpu=40000000L
+Pcbcupid_GLYPH_C3.menu.CPUFreq.20=20MHz
+Pcbcupid_GLYPH_C3.menu.CPUFreq.20.build.f_cpu=20000000L
+Pcbcupid_GLYPH_C3.menu.CPUFreq.10=10MHz
+Pcbcupid_GLYPH_C3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+Pcbcupid_GLYPH_C3.menu.FlashMode.qio=QIO
+Pcbcupid_GLYPH_C3.menu.FlashMode.qio.build.flash_mode=dio
+Pcbcupid_GLYPH_C3.menu.FlashMode.qio.build.boot=qio
+Pcbcupid_GLYPH_C3.menu.FlashMode.dio=DIO
+Pcbcupid_GLYPH_C3.menu.FlashMode.dio.build.flash_mode=dio
+Pcbcupid_GLYPH_C3.menu.FlashMode.dio.build.boot=dio
+
+Pcbcupid_GLYPH_C3.menu.FlashFreq.80=80MHz
+Pcbcupid_GLYPH_C3.menu.FlashFreq.80.build.flash_freq=80m
+Pcbcupid_GLYPH_C3.menu.FlashFreq.40=40MHz
+Pcbcupid_GLYPH_C3.menu.FlashFreq.40.build.flash_freq=40m
+
+Pcbcupid_GLYPH_C3.menu.FlashSize.4M=4MB (32Mb)
+Pcbcupid_GLYPH_C3.menu.FlashSize.4M.build.flash_size=4MB
+
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.921600=921600
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.921600.upload.speed=921600
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.115200=115200
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.115200.upload.speed=115200
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.256000.windows=256000
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.256000.upload.speed=256000
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.230400.windows.upload.speed=256000
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.230400=230400
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.230400.upload.speed=230400
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.460800.linux=460800
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.460800.macosx=460800
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.460800.upload.speed=460800
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.512000.windows=512000
+Pcbcupid_GLYPH_C3.menu.UploadSpeed.512000.upload.speed=512000
+
+Pcbcupid_GLYPH_C3.menu.DebugLevel.none=None
+Pcbcupid_GLYPH_C3.menu.DebugLevel.none.build.code_debug=0
+Pcbcupid_GLYPH_C3.menu.DebugLevel.error=Error
+Pcbcupid_GLYPH_C3.menu.DebugLevel.error.build.code_debug=1
+Pcbcupid_GLYPH_C3.menu.DebugLevel.warn=Warn
+Pcbcupid_GLYPH_C3.menu.DebugLevel.warn.build.code_debug=2
+Pcbcupid_GLYPH_C3.menu.DebugLevel.info=Info
+Pcbcupid_GLYPH_C3.menu.DebugLevel.info.build.code_debug=3
+Pcbcupid_GLYPH_C3.menu.DebugLevel.debug=Debug
+Pcbcupid_GLYPH_C3.menu.DebugLevel.debug.build.code_debug=4
+Pcbcupid_GLYPH_C3.menu.DebugLevel.verbose=Verbose
+Pcbcupid_GLYPH_C3.menu.DebugLevel.verbose.build.code_debug=5
+
+Pcbcupid_GLYPH_C3.menu.EraseFlash.none=Disabled
+Pcbcupid_GLYPH_C3.menu.EraseFlash.none.upload.erase_cmd=
+Pcbcupid_GLYPH_C3.menu.EraseFlash.all=Enabled
+Pcbcupid_GLYPH_C3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+
+Pcbcupid_GLYPH_H2.name=Pcbcupid GLYPH H2
+
+Pcbcupid_GLYPH_H2.bootloader.tool=esptool_py
+Pcbcupid_GLYPH_H2.bootloader.tool.default=esptool_py
+
+Pcbcupid_GLYPH_H2.upload.tool=esptool_py
+Pcbcupid_GLYPH_H2.upload.tool.default=esptool_py
+Pcbcupid_GLYPH_H2.upload.tool.network=esp_ota
+
+Pcbcupid_GLYPH_H2.upload.maximum_size=1310720
+Pcbcupid_GLYPH_H2.upload.maximum_data_size=327680
+Pcbcupid_GLYPH_H2.upload.flags=
+Pcbcupid_GLYPH_H2.upload.extra_flags=
+Pcbcupid_GLYPH_H2.upload.use_1200bps_touch=false
+Pcbcupid_GLYPH_H2.upload.wait_for_upload_port=false
+
+Pcbcupid_GLYPH_H2.serial.disableDTR=false
+Pcbcupid_GLYPH_H2.serial.disableRTS=false
+
+Pcbcupid_GLYPH_H2.build.tarch=riscv32
+Pcbcupid_GLYPH_H2.build.target=esp
+Pcbcupid_GLYPH_H2.build.mcu=esp32h2
+Pcbcupid_GLYPH_H2.build.core=esp32
+Pcbcupid_GLYPH_H2.build.variant=Pcbcupid_GLYPH_H2
+Pcbcupid_GLYPH_H2.build.board=PCBCUPID_GLYPHH2
+Pcbcupid_GLYPH_H2.build.bootloader_addr=0x0
+
+Pcbcupid_GLYPH_H2.build.cdc_on_boot=1
+Pcbcupid_GLYPH_H2.build.f_cpu=96000000L
+Pcbcupid_GLYPH_H2.build.flash_size=4MB
+Pcbcupid_GLYPH_H2.build.flash_freq=64m
+Pcbcupid_GLYPH_H2.build.img_freq=48m
+Pcbcupid_GLYPH_H2.build.flash_mode=qio
+Pcbcupid_GLYPH_H2.build.boot=qio
+Pcbcupid_GLYPH_H2.build.partitions=default
+Pcbcupid_GLYPH_H2.build.defines=
+
+## IDE 2.0 Seems to not update the value
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.default=Disabled
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.default.build.copy_jtag_files=0
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.builtin=Integrated USB JTAG
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.builtin.build.openocdscript=esp32h2-builtin.cfg
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.external=FTDI Adapter
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.external.build.openocdscript=esp32h2-ftdi.cfg
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.external.build.copy_jtag_files=1
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.bridge=ESP USB Bridge
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.bridge.build.openocdscript=esp32h2-bridge.cfg
+Pcbcupid_GLYPH_H2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+Pcbcupid_GLYPH_H2.menu.CDCOnBoot.default=Enabled
+Pcbcupid_GLYPH_H2.menu.CDCOnBoot.default.build.cdc_on_boot=1
+Pcbcupid_GLYPH_H2.menu.CDCOnBoot.cdc=Disabled
+Pcbcupid_GLYPH_H2.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.default.build.partitions=default
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.minimal.build.partitions=minimal
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_fs.build.partitions=no_fs
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee.build.partitions=zigbee
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.custom=Custom
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.custom.build.partitions=
+Pcbcupid_GLYPH_H2.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+Pcbcupid_GLYPH_H2.menu.FlashMode.qio=QIO
+Pcbcupid_GLYPH_H2.menu.FlashMode.qio.build.flash_mode=dio
+Pcbcupid_GLYPH_H2.menu.FlashMode.qio.build.boot=qio
+Pcbcupid_GLYPH_H2.menu.FlashMode.dio=DIO
+Pcbcupid_GLYPH_H2.menu.FlashMode.dio.build.flash_mode=dio
+Pcbcupid_GLYPH_H2.menu.FlashMode.dio.build.boot=dio
+
+Pcbcupid_GLYPH_H2.menu.FlashFreq.64=64MHz
+Pcbcupid_GLYPH_H2.menu.FlashFreq.64.build.flash_freq=64m
+Pcbcupid_GLYPH_H2.menu.FlashFreq.64.build.img_freq=48m
+#Pcbcupid_GLYPH_H2.menu.FlashFreq.32=32MHz
+#Pcbcupid_GLYPH_H2.menu.FlashFreq.32.build.flash_freq=32m
+#Pcbcupid_GLYPH_H2.menu.FlashFreq.32.build.img_freq=24m
+Pcbcupid_GLYPH_H2.menu.FlashFreq.16=16MHz
+Pcbcupid_GLYPH_H2.menu.FlashFreq.16.build.flash_freq=16m
+Pcbcupid_GLYPH_H2.menu.FlashFreq.16.build.img_freq=12m
+
+Pcbcupid_GLYPH_H2.menu.FlashSize.2M=2MB (16Mb)
+Pcbcupid_GLYPH_H2.menu.FlashSize.2M.build.flash_size=2MB
+Pcbcupid_GLYPH_H2.menu.FlashSize.4M=4MB (32Mb)
+Pcbcupid_GLYPH_H2.menu.FlashSize.4M.build.flash_size=4MB
+
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.921600=921600
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.921600.upload.speed=921600
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.115200=115200
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.115200.upload.speed=115200
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.256000.windows=256000
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.256000.upload.speed=256000
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.230400.windows.upload.speed=256000
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.230400=230400
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.230400.upload.speed=230400
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.460800.linux=460800
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.460800.macosx=460800
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.460800.upload.speed=460800
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.512000.windows=512000
+Pcbcupid_GLYPH_H2.menu.UploadSpeed.512000.upload.speed=512000
+
+Pcbcupid_GLYPH_H2.menu.DebugLevel.none=None
+Pcbcupid_GLYPH_H2.menu.DebugLevel.none.build.code_debug=0
+Pcbcupid_GLYPH_H2.menu.DebugLevel.error=Error
+Pcbcupid_GLYPH_H2.menu.DebugLevel.error.build.code_debug=1
+Pcbcupid_GLYPH_H2.menu.DebugLevel.warn=Warn
+Pcbcupid_GLYPH_H2.menu.DebugLevel.warn.build.code_debug=2
+Pcbcupid_GLYPH_H2.menu.DebugLevel.info=Info
+Pcbcupid_GLYPH_H2.menu.DebugLevel.info.build.code_debug=3
+Pcbcupid_GLYPH_H2.menu.DebugLevel.debug=Debug
+Pcbcupid_GLYPH_H2.menu.DebugLevel.debug.build.code_debug=4
+Pcbcupid_GLYPH_H2.menu.DebugLevel.verbose=Verbose
+Pcbcupid_GLYPH_H2.menu.DebugLevel.verbose.build.code_debug=5
+
+Pcbcupid_GLYPH_H2.menu.EraseFlash.none=Disabled
+Pcbcupid_GLYPH_H2.menu.EraseFlash.none.upload.erase_cmd=
+Pcbcupid_GLYPH_H2.menu.EraseFlash.all=Enabled
+Pcbcupid_GLYPH_H2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+Pcbcupid_GLYPH_H2.menu.ZigbeeMode.default=Disabled
+Pcbcupid_GLYPH_H2.menu.ZigbeeMode.default.build.zigbee_mode=
+Pcbcupid_GLYPH_H2.menu.ZigbeeMode.default.build.zigbee_libs=
+Pcbcupid_GLYPH_H2.menu.ZigbeeMode.ed=Zigbee ED (end device)
+Pcbcupid_GLYPH_H2.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+Pcbcupid_GLYPH_H2.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+Pcbcupid_GLYPH_H2.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+Pcbcupid_GLYPH_H2.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+Pcbcupid_GLYPH_H2.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+Pcbcupid_GLYPH_C6.name=Pcbcupid GLYPH C6
+
+Pcbcupid_GLYPH_C6.bootloader.tool=esptool_py
+Pcbcupid_GLYPH_C6.bootloader.tool.default=esptool_py
+
+Pcbcupid_GLYPH_C6.upload.tool=esptool_py
+Pcbcupid_GLYPH_C6.upload.tool.default=esptool_py
+Pcbcupid_GLYPH_C6.upload.tool.network=esp_ota
+
+Pcbcupid_GLYPH_C6.upload.maximum_size=1310720
+Pcbcupid_GLYPH_C6.upload.maximum_data_size=327680
+Pcbcupid_GLYPH_C6.upload.flags=
+Pcbcupid_GLYPH_C6.upload.extra_flags=
+Pcbcupid_GLYPH_C6.upload.use_1200bps_touch=false
+Pcbcupid_GLYPH_C6.upload.wait_for_upload_port=false
+
+Pcbcupid_GLYPH_C6.serial.disableDTR=false
+Pcbcupid_GLYPH_C6.serial.disableRTS=false
+
+Pcbcupid_GLYPH_C6.build.tarch=riscv32
+Pcbcupid_GLYPH_C6.build.target=esp
+Pcbcupid_GLYPH_C6.build.mcu=esp32c6
+Pcbcupid_GLYPH_C6.build.core=esp32
+Pcbcupid_GLYPH_C6.build.variant=Pcbcupid_GLYPH_C6
+Pcbcupid_GLYPH_C6.build.board=PCBCUPID_GLYPHC6
+Pcbcupid_GLYPH_C6.build.bootloader_addr=0x0
+
+Pcbcupid_GLYPH_C6.build.cdc_on_boot=1
+Pcbcupid_GLYPH_C6.build.f_cpu=160000000L
+Pcbcupid_GLYPH_C6.build.flash_size=4MB
+Pcbcupid_GLYPH_C6.build.flash_freq=80m
+Pcbcupid_GLYPH_C6.build.flash_mode=qio
+Pcbcupid_GLYPH_C6.build.boot=qio
+Pcbcupid_GLYPH_C6.build.partitions=default
+Pcbcupid_GLYPH_C6.build.defines=
+
+## IDE 2.0 Seems to not update the value
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.default=Disabled
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.default.build.copy_jtag_files=0
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.builtin=Integrated USB JTAG
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.builtin.build.openocdscript=esp32c6-builtin.cfg
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.external=FTDI Adapter
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.external.build.openocdscript=esp32c6-ftdi.cfg
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.external.build.copy_jtag_files=1
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.bridge=ESP USB Bridge
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.bridge.build.openocdscript=esp32c6-bridge.cfg
+Pcbcupid_GLYPH_C6.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+Pcbcupid_GLYPH_C6.menu.CDCOnBoot.cdc=Enabled
+Pcbcupid_GLYPH_C6.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+Pcbcupid_GLYPH_C6.menu.CDCOnBoot.default=Disabled
+Pcbcupid_GLYPH_C6.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.default.build.partitions=default
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.no_ota.build.partitions=no_ota
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.huge_app.build.partitions=huge_app
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee.build.partitions=zigbee
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+Pcbcupid_GLYPH_C6.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+
+Pcbcupid_GLYPH_C6.menu.CPUFreq.160=160MHz (WiFi)
+Pcbcupid_GLYPH_C6.menu.CPUFreq.160.build.f_cpu=160000000L
+Pcbcupid_GLYPH_C6.menu.CPUFreq.80=80MHz (WiFi)
+Pcbcupid_GLYPH_C6.menu.CPUFreq.80.build.f_cpu=80000000L
+Pcbcupid_GLYPH_C6.menu.CPUFreq.40=40MHz
+Pcbcupid_GLYPH_C6.menu.CPUFreq.40.build.f_cpu=40000000L
+Pcbcupid_GLYPH_C6.menu.CPUFreq.20=20MHz
+Pcbcupid_GLYPH_C6.menu.CPUFreq.20.build.f_cpu=20000000L
+Pcbcupid_GLYPH_C6.menu.CPUFreq.10=10MHz
+Pcbcupid_GLYPH_C6.menu.CPUFreq.10.build.f_cpu=10000000L
+
+Pcbcupid_GLYPH_C6.menu.FlashMode.qio=QIO
+Pcbcupid_GLYPH_C6.menu.FlashMode.qio.build.flash_mode=dio
+Pcbcupid_GLYPH_C6.menu.FlashMode.qio.build.boot=qio
+Pcbcupid_GLYPH_C6.menu.FlashMode.dio=DIO
+Pcbcupid_GLYPH_C6.menu.FlashMode.dio.build.flash_mode=dio
+Pcbcupid_GLYPH_C6.menu.FlashMode.dio.build.boot=dio
+
+Pcbcupid_GLYPH_C6.menu.FlashFreq.80=80MHz
+Pcbcupid_GLYPH_C6.menu.FlashFreq.80.build.flash_freq=80m
+Pcbcupid_GLYPH_C6.menu.FlashFreq.40=40MHz
+Pcbcupid_GLYPH_C6.menu.FlashFreq.40.build.flash_freq=40m
+
+Pcbcupid_GLYPH_C6.menu.FlashSize.4M=4MB (32Mb)
+Pcbcupid_GLYPH_C6.menu.FlashSize.4M.build.flash_size=4MB
+
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.921600=921600
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.921600.upload.speed=921600
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.115200=115200
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.115200.upload.speed=115200
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.256000.windows=256000
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.256000.upload.speed=256000
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.230400.windows.upload.speed=256000
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.230400=230400
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.230400.upload.speed=230400
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.460800.linux=460800
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.460800.macosx=460800
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.460800.upload.speed=460800
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.512000.windows=512000
+Pcbcupid_GLYPH_C6.menu.UploadSpeed.512000.upload.speed=512000
+
+Pcbcupid_GLYPH_C6.menu.DebugLevel.none=None
+Pcbcupid_GLYPH_C6.menu.DebugLevel.none.build.code_debug=0
+Pcbcupid_GLYPH_C6.menu.DebugLevel.error=Error
+Pcbcupid_GLYPH_C6.menu.DebugLevel.error.build.code_debug=1
+Pcbcupid_GLYPH_C6.menu.DebugLevel.warn=Warn
+Pcbcupid_GLYPH_C6.menu.DebugLevel.warn.build.code_debug=2
+Pcbcupid_GLYPH_C6.menu.DebugLevel.info=Info
+Pcbcupid_GLYPH_C6.menu.DebugLevel.info.build.code_debug=3
+Pcbcupid_GLYPH_C6.menu.DebugLevel.debug=Debug
+Pcbcupid_GLYPH_C6.menu.DebugLevel.debug.build.code_debug=4
+Pcbcupid_GLYPH_C6.menu.DebugLevel.verbose=Verbose
+Pcbcupid_GLYPH_C6.menu.DebugLevel.verbose.build.code_debug=5
+
+Pcbcupid_GLYPH_C6.menu.EraseFlash.none=Disabled
+Pcbcupid_GLYPH_C6.menu.EraseFlash.none.upload.erase_cmd=
+Pcbcupid_GLYPH_C6.menu.EraseFlash.all=Enabled
+Pcbcupid_GLYPH_C6.menu.EraseFlash.all.upload.erase_cmd=-e
+
+Pcbcupid_GLYPH_C6.menu.ZigbeeMode.default=Disabled
+Pcbcupid_GLYPH_C6.menu.ZigbeeMode.default.build.zigbee_mode=
+Pcbcupid_GLYPH_C6.menu.ZigbeeMode.default.build.zigbee_libs=
+Pcbcupid_GLYPH_C6.menu.ZigbeeMode.ed=Zigbee ED (end device)
+Pcbcupid_GLYPH_C6.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
+Pcbcupid_GLYPH_C6.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api.ed -lzboss_stack.ed -lzboss_port.native
+Pcbcupid_GLYPH_C6.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+Pcbcupid_GLYPH_C6.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+Pcbcupid_GLYPH_C6.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.native
+
+##############################################################
+
+yb_esp32s3_amp_v2.name=YelloByte YB-ESP32-S3-AMP (Rev.2)
+
+yb_esp32s3_amp_v2.bootloader.tool=esptool_py
+yb_esp32s3_amp_v2.bootloader.tool.default=esptool_py
+
+yb_esp32s3_amp_v2.upload.tool=esptool_py
+yb_esp32s3_amp_v2.upload.tool.default=esptool_py
+yb_esp32s3_amp_v2.upload.tool.network=esp_ota
+
+yb_esp32s3_amp_v2.upload.maximum_size=1310720
+yb_esp32s3_amp_v2.upload.maximum_data_size=327680
+yb_esp32s3_amp_v2.upload.flags=
+yb_esp32s3_amp_v2.upload.extra_flags=
+yb_esp32s3_amp_v2.upload.use_1200bps_touch=false
+yb_esp32s3_amp_v2.upload.wait_for_upload_port=false
+
+yb_esp32s3_amp_v2.serial.disableDTR=false
+yb_esp32s3_amp_v2.serial.disableRTS=false
+
+yb_esp32s3_amp_v2.build.tarch=xtensa
+yb_esp32s3_amp_v2.build.bootloader_addr=0x0
+yb_esp32s3_amp_v2.build.target=esp32s3
+yb_esp32s3_amp_v2.build.mcu=esp32s3
+yb_esp32s3_amp_v2.build.core=esp32
+yb_esp32s3_amp_v2.build.variant=yb_esp32s3_amp_v2
+yb_esp32s3_amp_v2.build.board=YB_ESP32S3_AMP_V2
+
+yb_esp32s3_amp_v2.build.usb_mode=1
+yb_esp32s3_amp_v2.build.cdc_on_boot=0
+yb_esp32s3_amp_v2.build.msc_on_boot=0
+yb_esp32s3_amp_v2.build.dfu_on_boot=0
+yb_esp32s3_amp_v2.build.f_cpu=240000000L
+yb_esp32s3_amp_v2.build.flash_size=8MB
+yb_esp32s3_amp_v2.build.flash_freq=80m
+yb_esp32s3_amp_v2.build.flash_mode=dio
+yb_esp32s3_amp_v2.build.boot=qio
+yb_esp32s3_amp_v2.build.partitions=default
+yb_esp32s3_amp_v2.build.defines=
+yb_esp32s3_amp_v2.build.loop_core=
+yb_esp32s3_amp_v2.build.event_core=
+yb_esp32s3_amp_v2.build.flash_type=qio
+yb_esp32s3_amp_v2.build.psram_type=qspi
+yb_esp32s3_amp_v2.build.memory_type={build.flash_type}_{build.psram_type}
+
+yb_esp32s3_amp_v2.menu.JTAGAdapter.default=Disabled
+yb_esp32s3_amp_v2.menu.JTAGAdapter.default.build.copy_jtag_files=0
+yb_esp32s3_amp_v2.menu.JTAGAdapter.external=FTDI Adapter
+yb_esp32s3_amp_v2.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+yb_esp32s3_amp_v2.menu.JTAGAdapter.external.build.copy_jtag_files=1
+yb_esp32s3_amp_v2.menu.JTAGAdapter.bridge=ESP USB Bridge
+yb_esp32s3_amp_v2.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+yb_esp32s3_amp_v2.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+yb_esp32s3_amp_v2.menu.LoopCore.1=Core 1
+yb_esp32s3_amp_v2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+yb_esp32s3_amp_v2.menu.LoopCore.0=Core 0
+yb_esp32s3_amp_v2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+yb_esp32s3_amp_v2.menu.EventsCore.1=Core 1
+yb_esp32s3_amp_v2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+yb_esp32s3_amp_v2.menu.EventsCore.0=Core 0
+yb_esp32s3_amp_v2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+yb_esp32s3_amp_v2.menu.USBMode.hwcdc=Hardware CDC and JTAG
+yb_esp32s3_amp_v2.menu.USBMode.hwcdc.build.usb_mode=1
+yb_esp32s3_amp_v2.menu.USBMode.default=USB-OTG (TinyUSB)
+yb_esp32s3_amp_v2.menu.USBMode.default.build.usb_mode=0
+
+yb_esp32s3_amp_v2.menu.CDCOnBoot.default=Disabled
+yb_esp32s3_amp_v2.menu.CDCOnBoot.default.build.cdc_on_boot=0
+yb_esp32s3_amp_v2.menu.CDCOnBoot.cdc=Enabled
+yb_esp32s3_amp_v2.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+yb_esp32s3_amp_v2.menu.MSCOnBoot.default=Disabled
+yb_esp32s3_amp_v2.menu.MSCOnBoot.default.build.msc_on_boot=0
+yb_esp32s3_amp_v2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+yb_esp32s3_amp_v2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+yb_esp32s3_amp_v2.menu.DFUOnBoot.default=Disabled
+yb_esp32s3_amp_v2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+yb_esp32s3_amp_v2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+yb_esp32s3_amp_v2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+yb_esp32s3_amp_v2.menu.UploadMode.default=UART0 / Hardware CDC
+yb_esp32s3_amp_v2.menu.UploadMode.default.upload.use_1200bps_touch=false
+yb_esp32s3_amp_v2.menu.UploadMode.default.upload.wait_for_upload_port=false
+yb_esp32s3_amp_v2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+yb_esp32s3_amp_v2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+yb_esp32s3_amp_v2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+yb_esp32s3_amp_v2.menu.PSRAM.enabled=QSPI PSRAM
+yb_esp32s3_amp_v2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+yb_esp32s3_amp_v2.menu.PSRAM.enabled.build.psram_type=qspi
+yb_esp32s3_amp_v2.menu.PSRAM.disabled=Disabled
+yb_esp32s3_amp_v2.menu.PSRAM.disabled.build.defines=
+yb_esp32s3_amp_v2.menu.PSRAM.disabled.build.psram_type=qspi
+yb_esp32s3_amp_v2.menu.PSRAM.opi=OPI PSRAM
+yb_esp32s3_amp_v2.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+yb_esp32s3_amp_v2.menu.PSRAM.opi.build.psram_type=opi
+
+yb_esp32s3_amp_v2.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.default.build.partitions=default
+yb_esp32s3_amp_v2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+yb_esp32s3_amp_v2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+yb_esp32s3_amp_v2.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+yb_esp32s3_amp_v2.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.minimal.build.partitions=minimal
+yb_esp32s3_amp_v2.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.no_ota.build.partitions=no_ota
+yb_esp32s3_amp_v2.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+yb_esp32s3_amp_v2.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+yb_esp32s3_amp_v2.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+yb_esp32s3_amp_v2.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+yb_esp32s3_amp_v2.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.huge_app.build.partitions=huge_app
+yb_esp32s3_amp_v2.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+yb_esp32s3_amp_v2.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+yb_esp32s3_amp_v2.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+yb_esp32s3_amp_v2.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS)
+yb_esp32s3_amp_v2.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB
+yb_esp32s3_amp_v2.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536
+
+yb_esp32s3_amp_v2.menu.CPUFreq.240=240MHz (WiFi)
+yb_esp32s3_amp_v2.menu.CPUFreq.240.build.f_cpu=240000000L
+yb_esp32s3_amp_v2.menu.CPUFreq.160=160MHz (WiFi)
+yb_esp32s3_amp_v2.menu.CPUFreq.160.build.f_cpu=160000000L
+yb_esp32s3_amp_v2.menu.CPUFreq.80=80MHz (WiFi)
+yb_esp32s3_amp_v2.menu.CPUFreq.80.build.f_cpu=80000000L
+yb_esp32s3_amp_v2.menu.CPUFreq.40=40MHz
+yb_esp32s3_amp_v2.menu.CPUFreq.40.build.f_cpu=40000000L
+yb_esp32s3_amp_v2.menu.CPUFreq.20=20MHz
+yb_esp32s3_amp_v2.menu.CPUFreq.20.build.f_cpu=20000000L
+yb_esp32s3_amp_v2.menu.CPUFreq.10=10MHz
+yb_esp32s3_amp_v2.menu.CPUFreq.10.build.f_cpu=10000000L
+
+yb_esp32s3_amp_v2.menu.FlashMode.qio=QIO 80MHz
+yb_esp32s3_amp_v2.menu.FlashMode.qio.build.flash_mode=dio
+yb_esp32s3_amp_v2.menu.FlashMode.qio.build.boot=qio
+yb_esp32s3_amp_v2.menu.FlashMode.qio.build.boot_freq=80m
+yb_esp32s3_amp_v2.menu.FlashMode.qio.build.flash_freq=80m
+yb_esp32s3_amp_v2.menu.FlashMode.qio120=QIO 120MHz
+yb_esp32s3_amp_v2.menu.FlashMode.qio120.build.flash_mode=dio
+yb_esp32s3_amp_v2.menu.FlashMode.qio120.build.boot=qio
+yb_esp32s3_amp_v2.menu.FlashMode.qio120.build.boot_freq=120m
+yb_esp32s3_amp_v2.menu.FlashMode.qio120.build.flash_freq=80m
+yb_esp32s3_amp_v2.menu.FlashMode.dio=DIO 80MHz
+yb_esp32s3_amp_v2.menu.FlashMode.dio.build.flash_mode=dio
+yb_esp32s3_amp_v2.menu.FlashMode.dio.build.boot=dio
+yb_esp32s3_amp_v2.menu.FlashMode.dio.build.boot_freq=80m
+yb_esp32s3_amp_v2.menu.FlashMode.dio.build.flash_freq=80m
+yb_esp32s3_amp_v2.menu.FlashMode.opi=OPI 80MHz
+yb_esp32s3_amp_v2.menu.FlashMode.opi.build.flash_mode=dout
+yb_esp32s3_amp_v2.menu.FlashMode.opi.build.boot=opi
+yb_esp32s3_amp_v2.menu.FlashMode.opi.build.boot_freq=80m
+yb_esp32s3_amp_v2.menu.FlashMode.opi.build.flash_freq=80m
+
+yb_esp32s3_amp_v2.menu.FlashSize.4M=4MB (32Mb)
+yb_esp32s3_amp_v2.menu.FlashSize.4M.build.flash_size=4MB
+yb_esp32s3_amp_v2.menu.FlashSize.8M=8MB (64Mb)
+yb_esp32s3_amp_v2.menu.FlashSize.8M.build.flash_size=8MB
+yb_esp32s3_amp_v2.menu.FlashSize.16M=16MB (128Mb)
+yb_esp32s3_amp_v2.menu.FlashSize.16M.build.flash_size=16MB
+
+yb_esp32s3_amp_v2.menu.UploadSpeed.921600=921600
+yb_esp32s3_amp_v2.menu.UploadSpeed.921600.upload.speed=921600
+yb_esp32s3_amp_v2.menu.UploadSpeed.115200=115200
+yb_esp32s3_amp_v2.menu.UploadSpeed.115200.upload.speed=115200
+yb_esp32s3_amp_v2.menu.UploadSpeed.256000.windows=256000
+yb_esp32s3_amp_v2.menu.UploadSpeed.256000.upload.speed=256000
+yb_esp32s3_amp_v2.menu.UploadSpeed.230400.windows.upload.speed=256000
+yb_esp32s3_amp_v2.menu.UploadSpeed.230400=230400
+yb_esp32s3_amp_v2.menu.UploadSpeed.230400.upload.speed=230400
+yb_esp32s3_amp_v2.menu.UploadSpeed.460800.linux=460800
+yb_esp32s3_amp_v2.menu.UploadSpeed.460800.macosx=460800
+yb_esp32s3_amp_v2.menu.UploadSpeed.460800.upload.speed=460800
+yb_esp32s3_amp_v2.menu.UploadSpeed.512000.windows=512000
+yb_esp32s3_amp_v2.menu.UploadSpeed.512000.upload.speed=512000
+
+yb_esp32s3_amp_v2.menu.DebugLevel.none=None
+yb_esp32s3_amp_v2.menu.DebugLevel.none.build.code_debug=0
+yb_esp32s3_amp_v2.menu.DebugLevel.error=Error
+yb_esp32s3_amp_v2.menu.DebugLevel.error.build.code_debug=1
+yb_esp32s3_amp_v2.menu.DebugLevel.warn=Warn
+yb_esp32s3_amp_v2.menu.DebugLevel.warn.build.code_debug=2
+yb_esp32s3_amp_v2.menu.DebugLevel.info=Info
+yb_esp32s3_amp_v2.menu.DebugLevel.info.build.code_debug=3
+yb_esp32s3_amp_v2.menu.DebugLevel.debug=Debug
+yb_esp32s3_amp_v2.menu.DebugLevel.debug.build.code_debug=4
+yb_esp32s3_amp_v2.menu.DebugLevel.verbose=Verbose
+yb_esp32s3_amp_v2.menu.DebugLevel.verbose.build.code_debug=5
+
+yb_esp32s3_amp_v2.menu.EraseFlash.none=Disabled
+yb_esp32s3_amp_v2.menu.EraseFlash.none.upload.erase_cmd=
+yb_esp32s3_amp_v2.menu.EraseFlash.all=Enabled
+yb_esp32s3_amp_v2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+yb_esp32s3_amp_v3.name=YelloByte YB-ESP32-S3-AMP (Rev.3)
+
+yb_esp32s3_amp_v3.bootloader.tool=esptool_py
+yb_esp32s3_amp_v3.bootloader.tool.default=esptool_py
+
+yb_esp32s3_amp_v3.upload.tool=esptool_py
+yb_esp32s3_amp_v3.upload.tool.default=esptool_py
+yb_esp32s3_amp_v3.upload.tool.network=esp_ota
+
+yb_esp32s3_amp_v3.upload.maximum_size=1310720
+yb_esp32s3_amp_v3.upload.maximum_data_size=327680
+yb_esp32s3_amp_v3.upload.flags=
+yb_esp32s3_amp_v3.upload.extra_flags=
+yb_esp32s3_amp_v3.upload.use_1200bps_touch=false
+yb_esp32s3_amp_v3.upload.wait_for_upload_port=false
+
+yb_esp32s3_amp_v3.serial.disableDTR=false
+yb_esp32s3_amp_v3.serial.disableRTS=false
+
+yb_esp32s3_amp_v3.build.tarch=xtensa
+yb_esp32s3_amp_v3.build.bootloader_addr=0x0
+yb_esp32s3_amp_v3.build.target=esp32s3
+yb_esp32s3_amp_v3.build.mcu=esp32s3
+yb_esp32s3_amp_v3.build.core=esp32
+yb_esp32s3_amp_v3.build.variant=yb_esp32s3_amp_v3
+yb_esp32s3_amp_v3.build.board=YB_ESP32S3_AMP_V3
+
+yb_esp32s3_amp_v3.build.usb_mode=1
+yb_esp32s3_amp_v3.build.cdc_on_boot=1
+yb_esp32s3_amp_v3.build.msc_on_boot=0
+yb_esp32s3_amp_v3.build.dfu_on_boot=0
+yb_esp32s3_amp_v3.build.f_cpu=240000000L
+yb_esp32s3_amp_v3.build.flash_size=8MB
+yb_esp32s3_amp_v3.build.flash_freq=80m
+yb_esp32s3_amp_v3.build.flash_mode=dio
+yb_esp32s3_amp_v3.build.boot=qio
+yb_esp32s3_amp_v3.build.partitions=default
+yb_esp32s3_amp_v3.build.defines=
+yb_esp32s3_amp_v3.build.loop_core=
+yb_esp32s3_amp_v3.build.event_core=
+yb_esp32s3_amp_v3.build.flash_type=qio
+yb_esp32s3_amp_v3.build.psram_type=qspi
+yb_esp32s3_amp_v3.build.memory_type={build.flash_type}_{build.psram_type}
+
+yb_esp32s3_amp_v3.menu.JTAGAdapter.default=Disabled
+yb_esp32s3_amp_v3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+yb_esp32s3_amp_v3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+yb_esp32s3_amp_v3.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+yb_esp32s3_amp_v3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+yb_esp32s3_amp_v3.menu.JTAGAdapter.external=FTDI Adapter
+yb_esp32s3_amp_v3.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+yb_esp32s3_amp_v3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+yb_esp32s3_amp_v3.menu.JTAGAdapter.bridge=ESP USB Bridge
+yb_esp32s3_amp_v3.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+yb_esp32s3_amp_v3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+yb_esp32s3_amp_v3.menu.LoopCore.1=Core 1
+yb_esp32s3_amp_v3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+yb_esp32s3_amp_v3.menu.LoopCore.0=Core 0
+yb_esp32s3_amp_v3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+yb_esp32s3_amp_v3.menu.EventsCore.1=Core 1
+yb_esp32s3_amp_v3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+yb_esp32s3_amp_v3.menu.EventsCore.0=Core 0
+yb_esp32s3_amp_v3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+yb_esp32s3_amp_v3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+yb_esp32s3_amp_v3.menu.USBMode.hwcdc.build.usb_mode=1
+yb_esp32s3_amp_v3.menu.USBMode.default=USB-OTG (TinyUSB)
+yb_esp32s3_amp_v3.menu.USBMode.default.build.usb_mode=0
+
+yb_esp32s3_amp_v3.menu.CDCOnBoot.cdc=Enabled
+yb_esp32s3_amp_v3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+yb_esp32s3_amp_v3.menu.CDCOnBoot.default=Disabled
+yb_esp32s3_amp_v3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+
+yb_esp32s3_amp_v3.menu.MSCOnBoot.default=Disabled
+yb_esp32s3_amp_v3.menu.MSCOnBoot.default.build.msc_on_boot=0
+yb_esp32s3_amp_v3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+yb_esp32s3_amp_v3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+yb_esp32s3_amp_v3.menu.DFUOnBoot.default=Disabled
+yb_esp32s3_amp_v3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+yb_esp32s3_amp_v3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+yb_esp32s3_amp_v3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+yb_esp32s3_amp_v3.menu.UploadMode.default=UART0 / Hardware CDC
+yb_esp32s3_amp_v3.menu.UploadMode.default.upload.use_1200bps_touch=false
+yb_esp32s3_amp_v3.menu.UploadMode.default.upload.wait_for_upload_port=false
+yb_esp32s3_amp_v3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+yb_esp32s3_amp_v3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+yb_esp32s3_amp_v3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+yb_esp32s3_amp_v3.menu.PSRAM.enabled=QSPI PSRAM
+yb_esp32s3_amp_v3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+yb_esp32s3_amp_v3.menu.PSRAM.enabled.build.psram_type=qspi
+yb_esp32s3_amp_v3.menu.PSRAM.disabled=Disabled
+yb_esp32s3_amp_v3.menu.PSRAM.disabled.build.defines=
+yb_esp32s3_amp_v3.menu.PSRAM.disabled.build.psram_type=qspi
+yb_esp32s3_amp_v3.menu.PSRAM.opi=OPI PSRAM
+yb_esp32s3_amp_v3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+yb_esp32s3_amp_v3.menu.PSRAM.opi.build.psram_type=opi
+
+yb_esp32s3_amp_v3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.default.build.partitions=default
+yb_esp32s3_amp_v3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+yb_esp32s3_amp_v3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+yb_esp32s3_amp_v3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+yb_esp32s3_amp_v3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.minimal.build.partitions=minimal
+yb_esp32s3_amp_v3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+yb_esp32s3_amp_v3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+yb_esp32s3_amp_v3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+yb_esp32s3_amp_v3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+yb_esp32s3_amp_v3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+yb_esp32s3_amp_v3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+yb_esp32s3_amp_v3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+yb_esp32s3_amp_v3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+yb_esp32s3_amp_v3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+yb_esp32s3_amp_v3.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS)
+yb_esp32s3_amp_v3.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB
+yb_esp32s3_amp_v3.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536
+
+yb_esp32s3_amp_v3.menu.CPUFreq.240=240MHz (WiFi)
+yb_esp32s3_amp_v3.menu.CPUFreq.240.build.f_cpu=240000000L
+yb_esp32s3_amp_v3.menu.CPUFreq.160=160MHz (WiFi)
+yb_esp32s3_amp_v3.menu.CPUFreq.160.build.f_cpu=160000000L
+yb_esp32s3_amp_v3.menu.CPUFreq.80=80MHz (WiFi)
+yb_esp32s3_amp_v3.menu.CPUFreq.80.build.f_cpu=80000000L
+yb_esp32s3_amp_v3.menu.CPUFreq.40=40MHz
+yb_esp32s3_amp_v3.menu.CPUFreq.40.build.f_cpu=40000000L
+yb_esp32s3_amp_v3.menu.CPUFreq.20=20MHz
+yb_esp32s3_amp_v3.menu.CPUFreq.20.build.f_cpu=20000000L
+yb_esp32s3_amp_v3.menu.CPUFreq.10=10MHz
+yb_esp32s3_amp_v3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+yb_esp32s3_amp_v3.menu.FlashMode.qio=QIO 80MHz
+yb_esp32s3_amp_v3.menu.FlashMode.qio.build.flash_mode=dio
+yb_esp32s3_amp_v3.menu.FlashMode.qio.build.boot=qio
+yb_esp32s3_amp_v3.menu.FlashMode.qio.build.boot_freq=80m
+yb_esp32s3_amp_v3.menu.FlashMode.qio.build.flash_freq=80m
+yb_esp32s3_amp_v3.menu.FlashMode.qio120=QIO 120MHz
+yb_esp32s3_amp_v3.menu.FlashMode.qio120.build.flash_mode=dio
+yb_esp32s3_amp_v3.menu.FlashMode.qio120.build.boot=qio
+yb_esp32s3_amp_v3.menu.FlashMode.qio120.build.boot_freq=120m
+yb_esp32s3_amp_v3.menu.FlashMode.qio120.build.flash_freq=80m
+yb_esp32s3_amp_v3.menu.FlashMode.dio=DIO 80MHz
+yb_esp32s3_amp_v3.menu.FlashMode.dio.build.flash_mode=dio
+yb_esp32s3_amp_v3.menu.FlashMode.dio.build.boot=dio
+yb_esp32s3_amp_v3.menu.FlashMode.dio.build.boot_freq=80m
+yb_esp32s3_amp_v3.menu.FlashMode.dio.build.flash_freq=80m
+yb_esp32s3_amp_v3.menu.FlashMode.opi=OPI 80MHz
+yb_esp32s3_amp_v3.menu.FlashMode.opi.build.flash_mode=dout
+yb_esp32s3_amp_v3.menu.FlashMode.opi.build.boot=opi
+yb_esp32s3_amp_v3.menu.FlashMode.opi.build.boot_freq=80m
+yb_esp32s3_amp_v3.menu.FlashMode.opi.build.flash_freq=80m
+
+yb_esp32s3_amp_v3.menu.FlashSize.4M=4MB (32Mb)
+yb_esp32s3_amp_v3.menu.FlashSize.4M.build.flash_size=4MB
+yb_esp32s3_amp_v3.menu.FlashSize.8M=8MB (64Mb)
+yb_esp32s3_amp_v3.menu.FlashSize.8M.build.flash_size=8MB
+yb_esp32s3_amp_v3.menu.FlashSize.16M=16MB (128Mb)
+yb_esp32s3_amp_v3.menu.FlashSize.16M.build.flash_size=16MB
+
+yb_esp32s3_amp_v3.menu.UploadSpeed.921600=921600
+yb_esp32s3_amp_v3.menu.UploadSpeed.921600.upload.speed=921600
+yb_esp32s3_amp_v3.menu.UploadSpeed.115200=115200
+yb_esp32s3_amp_v3.menu.UploadSpeed.115200.upload.speed=115200
+yb_esp32s3_amp_v3.menu.UploadSpeed.256000.windows=256000
+yb_esp32s3_amp_v3.menu.UploadSpeed.256000.upload.speed=256000
+yb_esp32s3_amp_v3.menu.UploadSpeed.230400.windows.upload.speed=256000
+yb_esp32s3_amp_v3.menu.UploadSpeed.230400=230400
+yb_esp32s3_amp_v3.menu.UploadSpeed.230400.upload.speed=230400
+yb_esp32s3_amp_v3.menu.UploadSpeed.460800.linux=460800
+yb_esp32s3_amp_v3.menu.UploadSpeed.460800.macosx=460800
+yb_esp32s3_amp_v3.menu.UploadSpeed.460800.upload.speed=460800
+yb_esp32s3_amp_v3.menu.UploadSpeed.512000.windows=512000
+yb_esp32s3_amp_v3.menu.UploadSpeed.512000.upload.speed=512000
+
+yb_esp32s3_amp_v3.menu.DebugLevel.none=None
+yb_esp32s3_amp_v3.menu.DebugLevel.none.build.code_debug=0
+yb_esp32s3_amp_v3.menu.DebugLevel.error=Error
+yb_esp32s3_amp_v3.menu.DebugLevel.error.build.code_debug=1
+yb_esp32s3_amp_v3.menu.DebugLevel.warn=Warn
+yb_esp32s3_amp_v3.menu.DebugLevel.warn.build.code_debug=2
+yb_esp32s3_amp_v3.menu.DebugLevel.info=Info
+yb_esp32s3_amp_v3.menu.DebugLevel.info.build.code_debug=3
+yb_esp32s3_amp_v3.menu.DebugLevel.debug=Debug
+yb_esp32s3_amp_v3.menu.DebugLevel.debug.build.code_debug=4
+yb_esp32s3_amp_v3.menu.DebugLevel.verbose=Verbose
+yb_esp32s3_amp_v3.menu.DebugLevel.verbose.build.code_debug=5
+
+yb_esp32s3_amp_v3.menu.EraseFlash.none=Disabled
+yb_esp32s3_amp_v3.menu.EraseFlash.none.upload.erase_cmd=
+yb_esp32s3_amp_v3.menu.EraseFlash.all=Enabled
+yb_esp32s3_amp_v3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+yb_esp32s3_eth.name=YelloByte YB-ESP32-S3-ETH
+
+yb_esp32s3_eth.bootloader.tool=esptool_py
+yb_esp32s3_eth.bootloader.tool.default=esptool_py
+
+yb_esp32s3_eth.upload.tool=esptool_py
+yb_esp32s3_eth.upload.tool.default=esptool_py
+yb_esp32s3_eth.upload.tool.network=esp_ota
+
+yb_esp32s3_eth.upload.maximum_size=1310720
+yb_esp32s3_eth.upload.maximum_data_size=327680
+yb_esp32s3_eth.upload.flags=
+yb_esp32s3_eth.upload.extra_flags=
+yb_esp32s3_eth.upload.use_1200bps_touch=false
+yb_esp32s3_eth.upload.wait_for_upload_port=false
+
+yb_esp32s3_eth.serial.disableDTR=false
+yb_esp32s3_eth.serial.disableRTS=false
+
+yb_esp32s3_eth.build.tarch=xtensa
+yb_esp32s3_eth.build.bootloader_addr=0x0
+yb_esp32s3_eth.build.target=esp32s3
+yb_esp32s3_eth.build.mcu=esp32s3
+yb_esp32s3_eth.build.core=esp32
+yb_esp32s3_eth.build.variant=yb_esp32s3_eth
+yb_esp32s3_eth.build.board=YB_ESP32S3_ETH
+
+yb_esp32s3_eth.build.usb_mode=1
+yb_esp32s3_eth.build.cdc_on_boot=0
+yb_esp32s3_eth.build.msc_on_boot=0
+yb_esp32s3_eth.build.dfu_on_boot=0
+yb_esp32s3_eth.build.f_cpu=240000000L
+yb_esp32s3_eth.build.flash_size=4MB
+yb_esp32s3_eth.build.flash_freq=80m
+yb_esp32s3_eth.build.flash_mode=dio
+yb_esp32s3_eth.build.boot=qio
+yb_esp32s3_eth.build.boot_freq=80m
+yb_esp32s3_eth.build.partitions=default
+yb_esp32s3_eth.build.defines=
+yb_esp32s3_eth.build.loop_core=
+yb_esp32s3_eth.build.event_core=
+yb_esp32s3_eth.build.psram_type=qspi
+yb_esp32s3_eth.build.memory_type={build.boot}_{build.psram_type}
+
+yb_esp32s3_eth.menu.JTAGAdapter.default=Disabled
+yb_esp32s3_eth.menu.JTAGAdapter.default.build.copy_jtag_files=0
+yb_esp32s3_eth.menu.JTAGAdapter.builtin=Integrated USB JTAG
+yb_esp32s3_eth.menu.JTAGAdapter.builtin.build.openocdscript=esp32s3-builtin.cfg
+yb_esp32s3_eth.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+yb_esp32s3_eth.menu.JTAGAdapter.external=FTDI Adapter
+yb_esp32s3_eth.menu.JTAGAdapter.external.build.openocdscript=esp32s3-ftdi.cfg
+yb_esp32s3_eth.menu.JTAGAdapter.external.build.copy_jtag_files=1
+yb_esp32s3_eth.menu.JTAGAdapter.bridge=ESP USB Bridge
+yb_esp32s3_eth.menu.JTAGAdapter.bridge.build.openocdscript=esp32s3-bridge.cfg
+yb_esp32s3_eth.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+yb_esp32s3_eth.menu.LoopCore.1=Core 1
+yb_esp32s3_eth.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+yb_esp32s3_eth.menu.LoopCore.0=Core 0
+yb_esp32s3_eth.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+yb_esp32s3_eth.menu.EventsCore.1=Core 1
+yb_esp32s3_eth.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+yb_esp32s3_eth.menu.EventsCore.0=Core 0
+yb_esp32s3_eth.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+yb_esp32s3_eth.menu.USBMode.hwcdc=Hardware CDC and JTAG
+yb_esp32s3_eth.menu.USBMode.hwcdc.build.usb_mode=1
+yb_esp32s3_eth.menu.USBMode.default=USB-OTG (TinyUSB)
+yb_esp32s3_eth.menu.USBMode.default.build.usb_mode=0
+
+yb_esp32s3_eth.menu.CDCOnBoot.default=Disabled
+yb_esp32s3_eth.menu.CDCOnBoot.default.build.cdc_on_boot=0
+yb_esp32s3_eth.menu.CDCOnBoot.cdc=Enabled
+yb_esp32s3_eth.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+yb_esp32s3_eth.menu.MSCOnBoot.default=Disabled
+yb_esp32s3_eth.menu.MSCOnBoot.default.build.msc_on_boot=0
+yb_esp32s3_eth.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+yb_esp32s3_eth.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+yb_esp32s3_eth.menu.DFUOnBoot.default=Disabled
+yb_esp32s3_eth.menu.DFUOnBoot.default.build.dfu_on_boot=0
+yb_esp32s3_eth.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+yb_esp32s3_eth.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+yb_esp32s3_eth.menu.UploadMode.default=UART0 / Hardware CDC
+yb_esp32s3_eth.menu.UploadMode.default.upload.use_1200bps_touch=false
+yb_esp32s3_eth.menu.UploadMode.default.upload.wait_for_upload_port=false
+yb_esp32s3_eth.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+yb_esp32s3_eth.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+yb_esp32s3_eth.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+yb_esp32s3_eth.menu.PSRAM.disabled=Disabled
+yb_esp32s3_eth.menu.PSRAM.disabled.build.defines=
+yb_esp32s3_eth.menu.PSRAM.disabled.build.psram_type=qspi
+yb_esp32s3_eth.menu.PSRAM.enabled=QSPI PSRAM
+yb_esp32s3_eth.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+yb_esp32s3_eth.menu.PSRAM.enabled.build.psram_type=qspi
+yb_esp32s3_eth.menu.PSRAM.opi=OPI PSRAM
+yb_esp32s3_eth.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+yb_esp32s3_eth.menu.PSRAM.opi.build.psram_type=opi
+
+yb_esp32s3_eth.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+yb_esp32s3_eth.menu.PartitionScheme.default.build.partitions=default
+yb_esp32s3_eth.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+yb_esp32s3_eth.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+yb_esp32s3_eth.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+yb_esp32s3_eth.menu.PartitionScheme.default_16MB=16M with spiffs (6.25MB APP/3.43MB SPIFFS)
+yb_esp32s3_eth.menu.PartitionScheme.default_16MB.build.partitions=default_16MB
+yb_esp32s3_eth.menu.PartitionScheme.default_16MB.upload.maximum_size=6553600
+yb_esp32s3_eth.menu.PartitionScheme.max_app_8MB=Maximum APP (7.9MB APP No OTA/No FS)
+yb_esp32s3_eth.menu.PartitionScheme.max_app_8MB.build.partitions=max_app_8MB
+yb_esp32s3_eth.menu.PartitionScheme.max_app_8MB.upload.maximum_size=8257536
+yb_esp32s3_eth.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+yb_esp32s3_eth.menu.PartitionScheme.fatflash.build.partitions=ffat
+yb_esp32s3_eth.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+yb_esp32s3_eth.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+yb_esp32s3_eth.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+yb_esp32s3_eth.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+yb_esp32s3_eth.menu.PartitionScheme.minimal.build.partitions=minimal
+yb_esp32s3_eth.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+yb_esp32s3_eth.menu.PartitionScheme.no_ota.build.partitions=no_ota
+yb_esp32s3_eth.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+yb_esp32s3_eth.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+yb_esp32s3_eth.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+yb_esp32s3_eth.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+yb_esp32s3_eth.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+yb_esp32s3_eth.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+yb_esp32s3_eth.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+yb_esp32s3_eth.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+yb_esp32s3_eth.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+yb_esp32s3_eth.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+yb_esp32s3_eth.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+yb_esp32s3_eth.menu.PartitionScheme.huge_app.build.partitions=huge_app
+yb_esp32s3_eth.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+yb_esp32s3_eth.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+yb_esp32s3_eth.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+yb_esp32s3_eth.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+yb_esp32s3_eth.menu.PartitionScheme.custom=Custom
+yb_esp32s3_eth.menu.PartitionScheme.custom.build.partitions=
+yb_esp32s3_eth.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+yb_esp32s3_eth.menu.CPUFreq.240=240MHz (WiFi)
+yb_esp32s3_eth.menu.CPUFreq.240.build.f_cpu=240000000L
+yb_esp32s3_eth.menu.CPUFreq.160=160MHz (WiFi)
+yb_esp32s3_eth.menu.CPUFreq.160.build.f_cpu=160000000L
+yb_esp32s3_eth.menu.CPUFreq.80=80MHz (WiFi)
+yb_esp32s3_eth.menu.CPUFreq.80.build.f_cpu=80000000L
+yb_esp32s3_eth.menu.CPUFreq.40=40MHz
+yb_esp32s3_eth.menu.CPUFreq.40.build.f_cpu=40000000L
+yb_esp32s3_eth.menu.CPUFreq.20=20MHz
+yb_esp32s3_eth.menu.CPUFreq.20.build.f_cpu=20000000L
+yb_esp32s3_eth.menu.CPUFreq.10=10MHz
+yb_esp32s3_eth.menu.CPUFreq.10.build.f_cpu=10000000L
+
+yb_esp32s3_eth.menu.FlashMode.qio=QIO 80MHz
+yb_esp32s3_eth.menu.FlashMode.qio.build.flash_mode=dio
+yb_esp32s3_eth.menu.FlashMode.qio.build.boot=qio
+yb_esp32s3_eth.menu.FlashMode.qio.build.boot_freq=80m
+yb_esp32s3_eth.menu.FlashMode.qio.build.flash_freq=80m
+yb_esp32s3_eth.menu.FlashMode.qio120=QIO 120MHz
+yb_esp32s3_eth.menu.FlashMode.qio120.build.flash_mode=dio
+yb_esp32s3_eth.menu.FlashMode.qio120.build.boot=qio
+yb_esp32s3_eth.menu.FlashMode.qio120.build.boot_freq=120m
+yb_esp32s3_eth.menu.FlashMode.qio120.build.flash_freq=80m
+yb_esp32s3_eth.menu.FlashMode.dio=DIO 80MHz
+yb_esp32s3_eth.menu.FlashMode.dio.build.flash_mode=dio
+yb_esp32s3_eth.menu.FlashMode.dio.build.boot=dio
+yb_esp32s3_eth.menu.FlashMode.dio.build.boot_freq=80m
+yb_esp32s3_eth.menu.FlashMode.dio.build.flash_freq=80m
+yb_esp32s3_eth.menu.FlashMode.opi=OPI 80MHz
+yb_esp32s3_eth.menu.FlashMode.opi.build.flash_mode=dout
+yb_esp32s3_eth.menu.FlashMode.opi.build.boot=opi
+yb_esp32s3_eth.menu.FlashMode.opi.build.boot_freq=80m
+yb_esp32s3_eth.menu.FlashMode.opi.build.flash_freq=80m
+
+yb_esp32s3_eth.menu.FlashSize.4M=4MB (32Mb)
+yb_esp32s3_eth.menu.FlashSize.4M.build.flash_size=4MB
+yb_esp32s3_eth.menu.FlashSize.8M=8MB (64Mb)
+yb_esp32s3_eth.menu.FlashSize.8M.build.flash_size=8MB
+yb_esp32s3_eth.menu.FlashSize.16M=16MB (128Mb)
+yb_esp32s3_eth.menu.FlashSize.16M.build.flash_size=16MB
+
+yb_esp32s3_eth.menu.UploadSpeed.921600=921600
+yb_esp32s3_eth.menu.UploadSpeed.921600.upload.speed=921600
+yb_esp32s3_eth.menu.UploadSpeed.115200=115200
+yb_esp32s3_eth.menu.UploadSpeed.115200.upload.speed=115200
+yb_esp32s3_eth.menu.UploadSpeed.256000.windows=256000
+yb_esp32s3_eth.menu.UploadSpeed.256000.upload.speed=256000
+yb_esp32s3_eth.menu.UploadSpeed.230400.windows.upload.speed=256000
+yb_esp32s3_eth.menu.UploadSpeed.230400=230400
+yb_esp32s3_eth.menu.UploadSpeed.230400.upload.speed=230400
+yb_esp32s3_eth.menu.UploadSpeed.460800.linux=460800
+yb_esp32s3_eth.menu.UploadSpeed.460800.macosx=460800
+yb_esp32s3_eth.menu.UploadSpeed.460800.upload.speed=460800
+yb_esp32s3_eth.menu.UploadSpeed.512000.windows=512000
+yb_esp32s3_eth.menu.UploadSpeed.512000.upload.speed=512000
+
+yb_esp32s3_eth.menu.DebugLevel.none=None
+yb_esp32s3_eth.menu.DebugLevel.none.build.code_debug=0
+yb_esp32s3_eth.menu.DebugLevel.error=Error
+yb_esp32s3_eth.menu.DebugLevel.error.build.code_debug=1
+yb_esp32s3_eth.menu.DebugLevel.warn=Warn
+yb_esp32s3_eth.menu.DebugLevel.warn.build.code_debug=2
+yb_esp32s3_eth.menu.DebugLevel.info=Info
+yb_esp32s3_eth.menu.DebugLevel.info.build.code_debug=3
+yb_esp32s3_eth.menu.DebugLevel.debug=Debug
+yb_esp32s3_eth.menu.DebugLevel.debug.build.code_debug=4
+yb_esp32s3_eth.menu.DebugLevel.verbose=Verbose
+yb_esp32s3_eth.menu.DebugLevel.verbose.build.code_debug=5
+
+yb_esp32s3_eth.menu.EraseFlash.none=Disabled
+yb_esp32s3_eth.menu.EraseFlash.none.upload.erase_cmd=
+yb_esp32s3_eth.menu.EraseFlash.all=Enabled
+yb_esp32s3_eth.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# Huidu HD-WF2 - esp32-s3 HUB75 driver board
+# https://www.hdwell.com/Product/index46.html
+
+huidu_hd_wf2.name=Huidu HD-WF2
+
+huidu_hd_wf2.bootloader.tool=esptool_py
+huidu_hd_wf2.bootloader.tool.default=esptool_py
+
+huidu_hd_wf2.upload.tool=esptool_py
+huidu_hd_wf2.upload.tool.default=esptool_py
+huidu_hd_wf2.upload.tool.network=esp_ota
+
+huidu_hd_wf2.upload.maximum_size=1310720
+huidu_hd_wf2.upload.maximum_data_size=327680
+huidu_hd_wf2.upload.flags=
+huidu_hd_wf2.upload.extra_flags=
+huidu_hd_wf2.upload.use_1200bps_touch=true
+huidu_hd_wf2.upload.wait_for_upload_port=true
+
+huidu_hd_wf2.serial.disableDTR=false
+huidu_hd_wf2.serial.disableRTS=false
+
+huidu_hd_wf2.build.tarch=xtensa
+huidu_hd_wf2.build.bootloader_addr=0x0
+huidu_hd_wf2.build.target=esp32s3
+huidu_hd_wf2.build.mcu=esp32s3
+huidu_hd_wf2.build.core=esp32
+huidu_hd_wf2.build.variant=huidu_hd_wf2
+huidu_hd_wf2.build.board=HUIDU_HD_WF2
+
+huidu_hd_wf2.build.usb_mode=0
+huidu_hd_wf2.build.cdc_on_boot=1
+huidu_hd_wf2.build.msc_on_boot=0
+huidu_hd_wf2.build.dfu_on_boot=0
+huidu_hd_wf2.build.f_cpu=240000000L
+huidu_hd_wf2.build.flash_size=8MB
+huidu_hd_wf2.build.flash_freq=80m
+huidu_hd_wf2.build.flash_mode=qio
+huidu_hd_wf2.build.boot=qio
+huidu_hd_wf2.build.partitions=default
+huidu_hd_wf2.build.defines=
+huidu_hd_wf2.build.loop_core=
+huidu_hd_wf2.build.event_core=
+huidu_hd_wf2.build.flash_type=qio
+huidu_hd_wf2.build.psram_type=qspi
+huidu_hd_wf2.build.memory_type={build.flash_type}_{build.psram_type}
+
+huidu_hd_wf2.menu.FlashSize.8M=8MB (64Mb)
+huidu_hd_wf2.menu.FlashSize.8M.build.flash_size=8MB
+
+huidu_hd_wf2.menu.LoopCore.1=Core 1
+huidu_hd_wf2.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+huidu_hd_wf2.menu.LoopCore.0=Core 0
+huidu_hd_wf2.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+huidu_hd_wf2.menu.EventsCore.1=Core 1
+huidu_hd_wf2.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+huidu_hd_wf2.menu.EventsCore.0=Core 0
+huidu_hd_wf2.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+huidu_hd_wf2.menu.USBMode.hwcdc=Hardware CDC and JTAG
+huidu_hd_wf2.menu.USBMode.hwcdc.build.usb_mode=1
+huidu_hd_wf2.menu.USBMode.default=USB-OTG (TinyUSB)
+huidu_hd_wf2.menu.USBMode.default.build.usb_mode=0
+
+huidu_hd_wf2.menu.CDCOnBoot.default=Enabled
+huidu_hd_wf2.menu.CDCOnBoot.default.build.cdc_on_boot=1
+huidu_hd_wf2.menu.CDCOnBoot.cdc=Disabled
+huidu_hd_wf2.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+huidu_hd_wf2.menu.MSCOnBoot.default=Disabled
+huidu_hd_wf2.menu.MSCOnBoot.default.build.msc_on_boot=0
+huidu_hd_wf2.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+huidu_hd_wf2.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+huidu_hd_wf2.menu.DFUOnBoot.default=Disabled
+huidu_hd_wf2.menu.DFUOnBoot.default.build.dfu_on_boot=0
+huidu_hd_wf2.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+huidu_hd_wf2.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+huidu_hd_wf2.menu.UploadMode.default=UART0 / Hardware CDC
+huidu_hd_wf2.menu.UploadMode.default.upload.use_1200bps_touch=false
+huidu_hd_wf2.menu.UploadMode.default.upload.wait_for_upload_port=false
+huidu_hd_wf2.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+huidu_hd_wf2.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+huidu_hd_wf2.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+huidu_hd_wf2.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+huidu_hd_wf2.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+huidu_hd_wf2.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+huidu_hd_wf2.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.3MB APP/5.5MiB SPIFFS)
+huidu_hd_wf2.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB
+huidu_hd_wf2.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720
+huidu_hd_wf2.menu.PartitionScheme.default_ffat_8MB=8MiB fatfs (3MB APP/1.5MB FATFS)
+huidu_hd_wf2.menu.PartitionScheme.default_ffat_8MB.build.partitions=default_ffat_8MB
+huidu_hd_wf2.menu.PartitionScheme.default_ffat_8MB.upload.maximum_size=3342336
+
+huidu_hd_wf2.menu.CPUFreq.240=240MHz (WiFi)
+huidu_hd_wf2.menu.CPUFreq.240.build.f_cpu=240000000L
+huidu_hd_wf2.menu.CPUFreq.160=160MHz (WiFi)
+huidu_hd_wf2.menu.CPUFreq.160.build.f_cpu=160000000L
+huidu_hd_wf2.menu.CPUFreq.80=80MHz (WiFi)
+huidu_hd_wf2.menu.CPUFreq.80.build.f_cpu=80000000L
+huidu_hd_wf2.menu.CPUFreq.40=40MHz
+huidu_hd_wf2.menu.CPUFreq.40.build.f_cpu=40000000L
+
+huidu_hd_wf2.menu.FlashMode.dio=DIO 80MHz
+huidu_hd_wf2.menu.FlashMode.dio.build.flash_mode=dio
+huidu_hd_wf2.menu.FlashMode.dio.build.boot=dio
+huidu_hd_wf2.menu.FlashMode.dio.build.boot_freq=80m
+huidu_hd_wf2.menu.FlashMode.dio.build.flash_freq=80m
+
+huidu_hd_wf2.menu.UploadSpeed.921600=921600
+huidu_hd_wf2.menu.UploadSpeed.921600.upload.speed=921600
+huidu_hd_wf2.menu.UploadSpeed.115200=115200
+huidu_hd_wf2.menu.UploadSpeed.115200.upload.speed=115200
+huidu_hd_wf2.menu.UploadSpeed.460800.linux=460800
+huidu_hd_wf2.menu.UploadSpeed.460800.macosx=460800
+huidu_hd_wf2.menu.UploadSpeed.460800.upload.speed=460800
+
+huidu_hd_wf2.menu.DebugLevel.none=None
+huidu_hd_wf2.menu.DebugLevel.none.build.code_debug=0
+huidu_hd_wf2.menu.DebugLevel.error=Error
+huidu_hd_wf2.menu.DebugLevel.error.build.code_debug=1
+huidu_hd_wf2.menu.DebugLevel.warn=Warn
+huidu_hd_wf2.menu.DebugLevel.warn.build.code_debug=2
+huidu_hd_wf2.menu.DebugLevel.info=Info
+huidu_hd_wf2.menu.DebugLevel.info.build.code_debug=3
+huidu_hd_wf2.menu.DebugLevel.debug=Debug
+huidu_hd_wf2.menu.DebugLevel.debug.build.code_debug=4
+huidu_hd_wf2.menu.DebugLevel.verbose=Verbose
+huidu_hd_wf2.menu.DebugLevel.verbose.build.code_debug=5
+
+huidu_hd_wf2.menu.EraseFlash.none=Disabled
+huidu_hd_wf2.menu.EraseFlash.none.upload.erase_cmd=
+huidu_hd_wf2.menu.EraseFlash.all=Enabled
+huidu_hd_wf2.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+# Huidu HD-WF4 - esp32-s3 HUB75 driver board
+# https://www.hdwell.com/Product/index46.html
+
+huidu_hd_wf4.name=Huidu HD-WF4
+
+huidu_hd_wf4.bootloader.tool=esptool_py
+huidu_hd_wf4.bootloader.tool.default=esptool_py
+
+huidu_hd_wf4.upload.tool=esptool_py
+huidu_hd_wf4.upload.tool.default=esptool_py
+huidu_hd_wf4.upload.tool.network=esp_ota
+
+huidu_hd_wf4.upload.maximum_size=1310720
+huidu_hd_wf4.upload.maximum_data_size=327680
+huidu_hd_wf4.upload.flags=
+huidu_hd_wf4.upload.extra_flags=
+huidu_hd_wf4.upload.use_1200bps_touch=true
+huidu_hd_wf4.upload.wait_for_upload_port=true
+
+huidu_hd_wf4.serial.disableDTR=false
+huidu_hd_wf4.serial.disableRTS=false
+
+huidu_hd_wf4.build.tarch=xtensa
+huidu_hd_wf4.build.bootloader_addr=0x0
+huidu_hd_wf4.build.target=esp32s3
+huidu_hd_wf4.build.mcu=esp32s3
+huidu_hd_wf4.build.core=esp32
+huidu_hd_wf4.build.variant=huidu_hd_wf4
+huidu_hd_wf4.build.board=HUIDU_HD_WF4
+
+huidu_hd_wf4.build.usb_mode=0
+huidu_hd_wf4.build.cdc_on_boot=1
+huidu_hd_wf4.build.msc_on_boot=0
+huidu_hd_wf4.build.dfu_on_boot=0
+huidu_hd_wf4.build.f_cpu=240000000L
+huidu_hd_wf4.build.flash_size=8MB
+huidu_hd_wf4.build.flash_freq=80m
+huidu_hd_wf4.build.flash_mode=qio
+huidu_hd_wf4.build.boot=qio
+huidu_hd_wf4.build.partitions=default
+huidu_hd_wf4.build.defines=
+huidu_hd_wf4.build.loop_core=
+huidu_hd_wf4.build.event_core=
+huidu_hd_wf4.build.flash_type=qio
+huidu_hd_wf4.build.psram_type=qspi
+huidu_hd_wf4.build.memory_type={build.flash_type}_{build.psram_type}
+
+huidu_hd_wf4.menu.FlashSize.8M=8MB (64Mb)
+huidu_hd_wf4.menu.FlashSize.8M.build.flash_size=8MB
+
+huidu_hd_wf4.menu.LoopCore.1=Core 1
+huidu_hd_wf4.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+huidu_hd_wf4.menu.LoopCore.0=Core 0
+huidu_hd_wf4.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+huidu_hd_wf4.menu.EventsCore.1=Core 1
+huidu_hd_wf4.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+huidu_hd_wf4.menu.EventsCore.0=Core 0
+huidu_hd_wf4.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+huidu_hd_wf4.menu.USBMode.hwcdc=Hardware CDC and JTAG
+huidu_hd_wf4.menu.USBMode.hwcdc.build.usb_mode=1
+huidu_hd_wf4.menu.USBMode.default=USB-OTG (TinyUSB)
+huidu_hd_wf4.menu.USBMode.default.build.usb_mode=0
+
+huidu_hd_wf4.menu.CDCOnBoot.default=Enabled
+huidu_hd_wf4.menu.CDCOnBoot.default.build.cdc_on_boot=1
+huidu_hd_wf4.menu.CDCOnBoot.cdc=Disabled
+huidu_hd_wf4.menu.CDCOnBoot.cdc.build.cdc_on_boot=0
+
+huidu_hd_wf4.menu.MSCOnBoot.default=Disabled
+huidu_hd_wf4.menu.MSCOnBoot.default.build.msc_on_boot=0
+huidu_hd_wf4.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+huidu_hd_wf4.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+huidu_hd_wf4.menu.DFUOnBoot.default=Disabled
+huidu_hd_wf4.menu.DFUOnBoot.default.build.dfu_on_boot=0
+huidu_hd_wf4.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+huidu_hd_wf4.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+huidu_hd_wf4.menu.UploadMode.default=UART0 / Hardware CDC
+huidu_hd_wf4.menu.UploadMode.default.upload.use_1200bps_touch=false
+huidu_hd_wf4.menu.UploadMode.default.upload.wait_for_upload_port=false
+huidu_hd_wf4.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+huidu_hd_wf4.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+huidu_hd_wf4.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+huidu_hd_wf4.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+huidu_hd_wf4.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+huidu_hd_wf4.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+huidu_hd_wf4.menu.PartitionScheme.large_spiffs_8MB=Large SPIFFS (1.3MB APP/5.5MiB SPIFFS)
+huidu_hd_wf4.menu.PartitionScheme.large_spiffs_8MB.build.partitions=large_spiffs_8MB
+huidu_hd_wf4.menu.PartitionScheme.large_spiffs_8MB.upload.maximum_size=1310720
+huidu_hd_wf4.menu.PartitionScheme.default_ffat_8MB=8MiB fatfs (3MB APP/1.5MB FATFS)
+huidu_hd_wf4.menu.PartitionScheme.default_ffat_8MB.build.partitions=default_ffat_8MB
+huidu_hd_wf4.menu.PartitionScheme.default_ffat_8MB.upload.maximum_size=3342336
+
+huidu_hd_wf4.menu.CPUFreq.240=240MHz (WiFi)
+huidu_hd_wf4.menu.CPUFreq.240.build.f_cpu=240000000L
+huidu_hd_wf4.menu.CPUFreq.160=160MHz (WiFi)
+huidu_hd_wf4.menu.CPUFreq.160.build.f_cpu=160000000L
+huidu_hd_wf4.menu.CPUFreq.80=80MHz (WiFi)
+huidu_hd_wf4.menu.CPUFreq.80.build.f_cpu=80000000L
+huidu_hd_wf4.menu.CPUFreq.40=40MHz
+huidu_hd_wf4.menu.CPUFreq.40.build.f_cpu=40000000L
+
+huidu_hd_wf4.menu.FlashMode.dio=DIO 80MHz
+huidu_hd_wf4.menu.FlashMode.dio.build.flash_mode=dio
+huidu_hd_wf4.menu.FlashMode.dio.build.boot=dio
+huidu_hd_wf4.menu.FlashMode.dio.build.boot_freq=80m
+huidu_hd_wf4.menu.FlashMode.dio.build.flash_freq=80m
+
+huidu_hd_wf4.menu.UploadSpeed.921600=921600
+huidu_hd_wf4.menu.UploadSpeed.921600.upload.speed=921600
+huidu_hd_wf4.menu.UploadSpeed.115200=115200
+huidu_hd_wf4.menu.UploadSpeed.115200.upload.speed=115200
+huidu_hd_wf4.menu.UploadSpeed.460800.linux=460800
+huidu_hd_wf4.menu.UploadSpeed.460800.macosx=460800
+huidu_hd_wf4.menu.UploadSpeed.460800.upload.speed=460800
+
+huidu_hd_wf4.menu.DebugLevel.none=None
+huidu_hd_wf4.menu.DebugLevel.none.build.code_debug=0
+huidu_hd_wf4.menu.DebugLevel.error=Error
+huidu_hd_wf4.menu.DebugLevel.error.build.code_debug=1
+huidu_hd_wf4.menu.DebugLevel.warn=Warn
+huidu_hd_wf4.menu.DebugLevel.warn.build.code_debug=2
+huidu_hd_wf4.menu.DebugLevel.info=Info
+huidu_hd_wf4.menu.DebugLevel.info.build.code_debug=3
+huidu_hd_wf4.menu.DebugLevel.debug=Debug
+huidu_hd_wf4.menu.DebugLevel.debug.build.code_debug=4
+huidu_hd_wf4.menu.DebugLevel.verbose=Verbose
+huidu_hd_wf4.menu.DebugLevel.verbose.build.code_debug=5
+
+huidu_hd_wf4.menu.EraseFlash.none=Disabled
+huidu_hd_wf4.menu.EraseFlash.none.upload.erase_cmd=
+huidu_hd_wf4.menu.EraseFlash.all=Enabled
+huidu_hd_wf4.menu.EraseFlash.all.upload.erase_cmd=-e
+
+##############################################################
+
+# CYOBot (CYOBrain V2 ESP32S3) Board
+cyobot_v2_esp32s3.name=CYOBOT V2 ESP32S3
+
+cyobot_v2_esp32s3.bootloader.tool=esptool_py
+cyobot_v2_esp32s3.bootloader.tool.default=esptool_py
+
+cyobot_v2_esp32s3.upload.tool=esptool_py
+cyobot_v2_esp32s3.upload.tool.default=esptool_py
+cyobot_v2_esp32s3.upload.tool.network=esp_ota
+
+cyobot_v2_esp32s3.upload.maximum_size=1310720
+cyobot_v2_esp32s3.upload.maximum_data_size=327680
+cyobot_v2_esp32s3.upload.flags=
+cyobot_v2_esp32s3.upload.extra_flags=
+cyobot_v2_esp32s3.upload.use_1200bps_touch=false
+cyobot_v2_esp32s3.upload.wait_for_upload_port=false
+
+cyobot_v2_esp32s3.serial.disableDTR=false
+cyobot_v2_esp32s3.serial.disableRTS=false
+
+cyobot_v2_esp32s3.build.tarch=xtensa
+cyobot_v2_esp32s3.build.bootloader_addr=0x0
+cyobot_v2_esp32s3.build.target=esp32s3
+cyobot_v2_esp32s3.build.mcu=esp32s3
+cyobot_v2_esp32s3.build.core=esp32
+cyobot_v2_esp32s3.build.variant=cyobot_v2_esp32s3
+cyobot_v2_esp32s3.build.board=CYOBOT_V2_ESP32S3
+
+cyobot_v2_esp32s3.build.usb_mode=1
+cyobot_v2_esp32s3.build.cdc_on_boot=0
+cyobot_v2_esp32s3.build.msc_on_boot=0
+cyobot_v2_esp32s3.build.dfu_on_boot=0
+cyobot_v2_esp32s3.build.f_cpu=240000000L
+cyobot_v2_esp32s3.build.flash_size=4MB
+cyobot_v2_esp32s3.build.flash_freq=80m
+cyobot_v2_esp32s3.build.flash_mode=dio
+cyobot_v2_esp32s3.build.boot=qio
+cyobot_v2_esp32s3.build.boot_freq=80m
+cyobot_v2_esp32s3.build.partitions=default
+cyobot_v2_esp32s3.build.defines=
+cyobot_v2_esp32s3.build.loop_core=
+cyobot_v2_esp32s3.build.event_core=
+cyobot_v2_esp32s3.build.psram_type=qspi
+cyobot_v2_esp32s3.build.memory_type={build.boot}_{build.psram_type}
+
+## IDE 2.0 Seems to not update the value
+cyobot_v2_esp32s3.menu.JTAGAdapter.default=Disabled
+cyobot_v2_esp32s3.menu.JTAGAdapter.default.build.copy_jtag_files=0
+cyobot_v2_esp32s3.menu.JTAGAdapter.builtin=Integrated USB JTAG
+cyobot_v2_esp32s3.menu.JTAGAdapter.builtin.build.openocdscript=cyobot_v2_esp32s3-builtin.cfg
+cyobot_v2_esp32s3.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
+cyobot_v2_esp32s3.menu.JTAGAdapter.external=FTDI Adapter
+cyobot_v2_esp32s3.menu.JTAGAdapter.external.build.openocdscript=cyobot_v2_esp32s3-ftdi.cfg
+cyobot_v2_esp32s3.menu.JTAGAdapter.external.build.copy_jtag_files=1
+cyobot_v2_esp32s3.menu.JTAGAdapter.bridge=ESP USB Bridge
+cyobot_v2_esp32s3.menu.JTAGAdapter.bridge.build.openocdscript=cyobot_v2_esp32s3-bridge.cfg
+cyobot_v2_esp32s3.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
+
+cyobot_v2_esp32s3.menu.PSRAM.disabled=Disabled
+cyobot_v2_esp32s3.menu.PSRAM.disabled.build.defines=
+cyobot_v2_esp32s3.menu.PSRAM.disabled.build.psram_type=qspi
+cyobot_v2_esp32s3.menu.PSRAM.enabled=QSPI PSRAM
+cyobot_v2_esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
+cyobot_v2_esp32s3.menu.PSRAM.enabled.build.psram_type=qspi
+cyobot_v2_esp32s3.menu.PSRAM.opi=OPI PSRAM
+cyobot_v2_esp32s3.menu.PSRAM.opi.build.defines=-DBOARD_HAS_PSRAM
+cyobot_v2_esp32s3.menu.PSRAM.opi.build.psram_type=opi
+
+cyobot_v2_esp32s3.menu.FlashMode.qio=QIO 80MHz
+cyobot_v2_esp32s3.menu.FlashMode.qio.build.flash_mode=dio
+cyobot_v2_esp32s3.menu.FlashMode.qio.build.boot=qio
+cyobot_v2_esp32s3.menu.FlashMode.qio.build.boot_freq=80m
+cyobot_v2_esp32s3.menu.FlashMode.qio.build.flash_freq=80m
+cyobot_v2_esp32s3.menu.FlashMode.qio120=QIO 120MHz
+cyobot_v2_esp32s3.menu.FlashMode.qio120.build.flash_mode=dio
+cyobot_v2_esp32s3.menu.FlashMode.qio120.build.boot=qio
+cyobot_v2_esp32s3.menu.FlashMode.qio120.build.boot_freq=120m
+cyobot_v2_esp32s3.menu.FlashMode.qio120.build.flash_freq=80m
+cyobot_v2_esp32s3.menu.FlashMode.dio=DIO 80MHz
+cyobot_v2_esp32s3.menu.FlashMode.dio.build.flash_mode=dio
+cyobot_v2_esp32s3.menu.FlashMode.dio.build.boot=dio
+cyobot_v2_esp32s3.menu.FlashMode.dio.build.boot_freq=80m
+cyobot_v2_esp32s3.menu.FlashMode.dio.build.flash_freq=80m
+cyobot_v2_esp32s3.menu.FlashMode.opi=OPI 80MHz
+cyobot_v2_esp32s3.menu.FlashMode.opi.build.flash_mode=dout
+cyobot_v2_esp32s3.menu.FlashMode.opi.build.boot=opi
+cyobot_v2_esp32s3.menu.FlashMode.opi.build.boot_freq=80m
+cyobot_v2_esp32s3.menu.FlashMode.opi.build.flash_freq=80m
+
+cyobot_v2_esp32s3.menu.FlashSize.4M=4MB (32Mb)
+cyobot_v2_esp32s3.menu.FlashSize.4M.build.flash_size=4MB
+cyobot_v2_esp32s3.menu.FlashSize.8M=8MB (64Mb)
+cyobot_v2_esp32s3.menu.FlashSize.8M.build.flash_size=8MB
+cyobot_v2_esp32s3.menu.FlashSize.16M=16MB (128Mb)
+cyobot_v2_esp32s3.menu.FlashSize.16M.build.flash_size=16MB
+cyobot_v2_esp32s3.menu.FlashSize.32M=32MB (256Mb)
+cyobot_v2_esp32s3.menu.FlashSize.32M.build.flash_size=32MB
+
+cyobot_v2_esp32s3.menu.LoopCore.1=Core 1
+cyobot_v2_esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
+cyobot_v2_esp32s3.menu.LoopCore.0=Core 0
+cyobot_v2_esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
+
+cyobot_v2_esp32s3.menu.EventsCore.1=Core 1
+cyobot_v2_esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
+cyobot_v2_esp32s3.menu.EventsCore.0=Core 0
+cyobot_v2_esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
+
+cyobot_v2_esp32s3.menu.USBMode.hwcdc=Hardware CDC and JTAG
+cyobot_v2_esp32s3.menu.USBMode.hwcdc.build.usb_mode=1
+cyobot_v2_esp32s3.menu.USBMode.default=USB-OTG (TinyUSB)
+cyobot_v2_esp32s3.menu.USBMode.default.build.usb_mode=0
+
+cyobot_v2_esp32s3.menu.CDCOnBoot.default=Disabled
+cyobot_v2_esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
+cyobot_v2_esp32s3.menu.CDCOnBoot.cdc=Enabled
+cyobot_v2_esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
+
+cyobot_v2_esp32s3.menu.MSCOnBoot.default=Disabled
+cyobot_v2_esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
+cyobot_v2_esp32s3.menu.MSCOnBoot.msc=Enabled (Requires USB-OTG Mode)
+cyobot_v2_esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
+
+cyobot_v2_esp32s3.menu.DFUOnBoot.default=Disabled
+cyobot_v2_esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
+cyobot_v2_esp32s3.menu.DFUOnBoot.dfu=Enabled (Requires USB-OTG Mode)
+cyobot_v2_esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
+
+cyobot_v2_esp32s3.menu.UploadMode.default=UART0 / Hardware CDC
+cyobot_v2_esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
+cyobot_v2_esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
+cyobot_v2_esp32s3.menu.UploadMode.cdc=USB-OTG CDC (TinyUSB)
+cyobot_v2_esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
+cyobot_v2_esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
+
+cyobot_v2_esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.default.build.partitions=default
+cyobot_v2_esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
+cyobot_v2_esp32s3.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
+cyobot_v2_esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
+cyobot_v2_esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal
+cyobot_v2_esp32s3.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
+cyobot_v2_esp32s3.menu.PartitionScheme.no_fs.build.partitions=no_fs
+cyobot_v2_esp32s3.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
+cyobot_v2_esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
+cyobot_v2_esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
+cyobot_v2_esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
+cyobot_v2_esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
+cyobot_v2_esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
+cyobot_v2_esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
+cyobot_v2_esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
+cyobot_v2_esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
+cyobot_v2_esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
+cyobot_v2_esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+cyobot_v2_esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
+cyobot_v2_esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
+cyobot_v2_esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat
+cyobot_v2_esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
+cyobot_v2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
+cyobot_v2_esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
+cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker=RainMaker 4MB
+cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
+cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
+cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
+cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
+cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
+cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
+cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
+cyobot_v2_esp32s3.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
+cyobot_v2_esp32s3.menu.PartitionScheme.app5M_fat24M_32MB=32M Flash (4.8MB APP/22MB FATFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.app5M_fat24M_32MB.build.partitions=large_fat_32MB
+cyobot_v2_esp32s3.menu.PartitionScheme.app5M_fat24M_32MB.upload.maximum_size=4718592
+cyobot_v2_esp32s3.menu.PartitionScheme.app5M_little24M_32MB=32M Flash (4.8MB APP/22MB LittleFS)
+cyobot_v2_esp32s3.menu.PartitionScheme.app5M_little24M_32MB.build.partitions=large_littlefs_32MB
+cyobot_v2_esp32s3.menu.PartitionScheme.app5M_little24M_32MB.upload.maximum_size=4718592
+cyobot_v2_esp32s3.menu.PartitionScheme.esp_sr_16=ESP SR 16M (3MB APP/7MB SPIFFS/2.9MB MODEL)
+cyobot_v2_esp32s3.menu.PartitionScheme.esp_sr_16.upload.maximum_size=3145728
+cyobot_v2_esp32s3.menu.PartitionScheme.esp_sr_16.upload.extra_flags=0xD10000 {build.path}/srmodels.bin
+cyobot_v2_esp32s3.menu.PartitionScheme.esp_sr_16.build.partitions=esp_sr_16
+cyobot_v2_esp32s3.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
+cyobot_v2_esp32s3.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
+cyobot_v2_esp32s3.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
+cyobot_v2_esp32s3.menu.PartitionScheme.custom=Custom
+cyobot_v2_esp32s3.menu.PartitionScheme.custom.build.partitions=
+cyobot_v2_esp32s3.menu.PartitionScheme.custom.upload.maximum_size=16777216
+
+cyobot_v2_esp32s3.menu.CPUFreq.240=240MHz (WiFi)
+cyobot_v2_esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
+cyobot_v2_esp32s3.menu.CPUFreq.160=160MHz (WiFi)
+cyobot_v2_esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
+cyobot_v2_esp32s3.menu.CPUFreq.80=80MHz (WiFi)
+cyobot_v2_esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
+cyobot_v2_esp32s3.menu.CPUFreq.40=40MHz
+cyobot_v2_esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
+cyobot_v2_esp32s3.menu.CPUFreq.20=20MHz
+cyobot_v2_esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
+cyobot_v2_esp32s3.menu.CPUFreq.10=10MHz
+cyobot_v2_esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
+
+cyobot_v2_esp32s3.menu.UploadSpeed.921600=921600
+cyobot_v2_esp32s3.menu.UploadSpeed.921600.upload.speed=921600
+cyobot_v2_esp32s3.menu.UploadSpeed.115200=115200
+cyobot_v2_esp32s3.menu.UploadSpeed.115200.upload.speed=115200
+cyobot_v2_esp32s3.menu.UploadSpeed.256000.windows=256000
+cyobot_v2_esp32s3.menu.UploadSpeed.256000.upload.speed=256000
+cyobot_v2_esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
+cyobot_v2_esp32s3.menu.UploadSpeed.230400=230400
+cyobot_v2_esp32s3.menu.UploadSpeed.230400.upload.speed=230400
+cyobot_v2_esp32s3.menu.UploadSpeed.460800.linux=460800
+cyobot_v2_esp32s3.menu.UploadSpeed.460800.macosx=460800
+cyobot_v2_esp32s3.menu.UploadSpeed.460800.upload.speed=460800
+cyobot_v2_esp32s3.menu.UploadSpeed.512000.windows=512000
+cyobot_v2_esp32s3.menu.UploadSpeed.512000.upload.speed=512000
+
+cyobot_v2_esp32s3.menu.DebugLevel.none=None
+cyobot_v2_esp32s3.menu.DebugLevel.none.build.code_debug=0
+cyobot_v2_esp32s3.menu.DebugLevel.error=Error
+cyobot_v2_esp32s3.menu.DebugLevel.error.build.code_debug=1
+cyobot_v2_esp32s3.menu.DebugLevel.warn=Warn
+cyobot_v2_esp32s3.menu.DebugLevel.warn.build.code_debug=2
+cyobot_v2_esp32s3.menu.DebugLevel.info=Info
+cyobot_v2_esp32s3.menu.DebugLevel.info.build.code_debug=3
+cyobot_v2_esp32s3.menu.DebugLevel.debug=Debug
+cyobot_v2_esp32s3.menu.DebugLevel.debug.build.code_debug=4
+cyobot_v2_esp32s3.menu.DebugLevel.verbose=Verbose
+cyobot_v2_esp32s3.menu.DebugLevel.verbose.build.code_debug=5
+
+cyobot_v2_esp32s3.menu.EraseFlash.none=Disabled
+cyobot_v2_esp32s3.menu.EraseFlash.none.upload.erase_cmd=
+cyobot_v2_esp32s3.menu.EraseFlash.all=Enabled
+cyobot_v2_esp32s3.menu.EraseFlash.all.upload.erase_cmd=-e
+
+cyobot_v2_esp32s3.menu.ZigbeeMode.default=Disabled
+cyobot_v2_esp32s3.menu.ZigbeeMode.default.build.zigbee_mode=
+cyobot_v2_esp32s3.menu.ZigbeeMode.default.build.zigbee_libs=
+cyobot_v2_esp32s3.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
+cyobot_v2_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
+cyobot_v2_esp32s3.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api.zczr -lzboss_stack.zczr -lzboss_port.remote
+
+##############################################################
diff --git a/component.mk b/component.mk
deleted file mode 100644
index 4b85ee4f217..00000000000
--- a/component.mk
+++ /dev/null
@@ -1,36 +0,0 @@
-ARDUINO_ALL_LIBRARIES := $(patsubst $(COMPONENT_PATH)/libraries/%,%,$(wildcard $(COMPONENT_PATH)/libraries/*))
-
-# Macro returns non-empty if Arduino library $(1) should be included in the build
-# (either because selective compilation is of, or this library is enabled
-define ARDUINO_LIBRARY_ENABLED
-$(if $(CONFIG_ARDUINO_SELECTIVE_COMPILATION),$(CONFIG_ARDUINO_SELECTIVE_$(1)),y)
-endef
-
-ARDUINO_ENABLED_LIBRARIES := $(foreach LIBRARY,$(sort $(ARDUINO_ALL_LIBRARIES)),$(if $(call ARDUINO_LIBRARY_ENABLED,$(LIBRARY)),$(LIBRARY)))
-
-$(info Arduino libraries in build: $(ARDUINO_ENABLED_LIBRARIES))
-
-# Expand all subdirs under $(1)
-define EXPAND_SUBDIRS
-$(sort $(dir $(wildcard $(1)/* $(1)/*/* $(1)/*/*/* $(1)/*/*/*/* $(1)/*/*/*/*/*)))
-endef
-
-# Macro returns SRCDIRS for library
-define ARDUINO_LIBRARY_GET_SRCDIRS
-	$(if $(wildcard $(COMPONENT_PATH)/libraries/$(1)/src/.), 							\
-		$(call EXPAND_SUBDIRS,$(COMPONENT_PATH)/libraries/$(1)/src), 					\
-		$(filter-out $(call EXPAND_SUBDIRS,$(COMPONENT_PATH)/libraries/$(1)/examples),  \
-			$(call EXPAND_SUBDIRS,$(COMPONENT_PATH)/libraries/$(1)) 				   	\
-		) 																				\
-	)
-endef
-
-# Make a list of all srcdirs in enabled libraries
-ARDUINO_LIBRARY_SRCDIRS := $(patsubst $(COMPONENT_PATH)/%,%,$(foreach LIBRARY,$(ARDUINO_ENABLED_LIBRARIES),$(call ARDUINO_LIBRARY_GET_SRCDIRS,$(LIBRARY))))
-
-#$(info Arduino libraries src dirs: $(ARDUINO_LIBRARY_SRCDIRS))
-
-COMPONENT_ADD_INCLUDEDIRS := cores/esp32 variants/esp32 $(ARDUINO_LIBRARY_SRCDIRS)
-COMPONENT_PRIV_INCLUDEDIRS := cores/esp32/libb64
-COMPONENT_SRCDIRS := cores/esp32/libb64 cores/esp32 variants/esp32 $(ARDUINO_LIBRARY_SRCDIRS)
-CXXFLAGS += -fno-rtti
diff --git a/cores/esp32/Arduino.h b/cores/esp32/Arduino.h
index addcb2066d3..d21089cc3fe 100644
--- a/cores/esp32/Arduino.h
+++ b/cores/esp32/Arduino.h
@@ -29,22 +29,27 @@
 #include <string.h>
 #include <inttypes.h>
 
+#include "esp_arduino_version.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "freertos/semphr.h"
-#include "esp32-hal.h"
 #include "esp8266-compat.h"
 #include "soc/gpio_reg.h"
 
 #include "stdlib_noniso.h"
 #include "binary.h"
+#include "extra_attr.h"
 
-#define PI 3.1415926535897932384626433832795
-#define HALF_PI 1.5707963267948966192313216916398
-#define TWO_PI 6.283185307179586476925286766559
+#include "pins_arduino.h"
+#include "io_pin_remap.h"
+#include "esp32-hal.h"
+
+#define PI         3.1415926535897932384626433832795
+#define HALF_PI    1.5707963267948966192313216916398
+#define TWO_PI     6.283185307179586476925286766559
 #define DEG_TO_RAD 0.017453292519943295769236907684886
 #define RAD_TO_DEG 57.295779513082320876798154814105
-#define EULER 2.718281828459045235360287471352
+#define EULER      2.718281828459045235360287471352
 
 #define SERIAL  0x0
 #define DISPLAY 0x1
@@ -61,65 +66,109 @@
 #define ONLOW_WE  0x0C
 #define ONHIGH_WE 0x0D
 
-#define DEFAULT 1
+#define DEFAULT  1
 #define EXTERNAL 0
 
 #ifndef __STRINGIFY
 #define __STRINGIFY(a) #a
 #endif
 
-#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt)))
-#define radians(deg) ((deg)*DEG_TO_RAD)
-#define degrees(rad) ((rad)*RAD_TO_DEG)
-#define sq(x) ((x)*(x))
-
-#define sei()
-#define cli()
-#define interrupts() sei()
+// can't define max() / min() because of conflicts with C++
+#define _min(a, b)                ((a) < (b) ? (a) : (b))
+#define _max(a, b)                ((a) > (b) ? (a) : (b))
+#define _abs(x)                   ((x) > 0 ? (x) : -(x))  // abs() comes from STL
+#define constrain(amt, low, high) ((amt) < (low) ? (low) : ((amt) > (high) ? (high) : (amt)))
+#define _round(x)                 ((x) >= 0 ? (long)((x) + 0.5) : (long)((x) - 0.5))  // round() comes from STL
+#define radians(deg)              ((deg) * DEG_TO_RAD)
+#define degrees(rad)              ((rad) * RAD_TO_DEG)
+#define sq(x)                     ((x) * (x))
+
+// ESP32xx runs FreeRTOS... disabling interrupts can lead to issues, such as Watchdog Timeout
+#define sei()          portENABLE_INTERRUPTS()
+#define cli()          portDISABLE_INTERRUPTS()
+#define interrupts()   sei()
 #define noInterrupts() cli()
 
-#define clockCyclesPerMicrosecond() ( (long int)getCpuFrequencyMhz() )
-#define clockCyclesToMicroseconds(a) ( (a) / clockCyclesPerMicrosecond() )
-#define microsecondsToClockCycles(a) ( (a) * clockCyclesPerMicrosecond() )
+#define clockCyclesPerMicrosecond()  ((long int)getCpuFrequencyMhz())
+#define clockCyclesToMicroseconds(a) ((a) / clockCyclesPerMicrosecond())
+#define microsecondsToClockCycles(a) ((a) * clockCyclesPerMicrosecond())
 
-#define lowByte(w) ((uint8_t) ((w) & 0xff))
-#define highByte(w) ((uint8_t) ((w) >> 8))
+#define lowByte(w)  ((uint8_t)((w) & 0xff))
+#define highByte(w) ((uint8_t)((w) >> 8))
 
-#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
-#define bitSet(value, bit) ((value) |= (1UL << (bit)))
-#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
+#define bitRead(value, bit)            (((value) >> (bit)) & 0x01)
+#define bitSet(value, bit)             ((value) |= (1UL << (bit)))
+#define bitClear(value, bit)           ((value) &= ~(1UL << (bit)))
+#define bitToggle(value, bit)          ((value) ^= (1UL << (bit)))
 #define bitWrite(value, bit, bitvalue) ((bitvalue) ? bitSet(value, bit) : bitClear(value, bit))
 
 // avr-libc defines _NOP() since 1.6.2
 #ifndef _NOP
-#define _NOP() do { __asm__ volatile ("nop"); } while (0)
+#define _NOP()               \
+  do {                       \
+    __asm__ volatile("nop"); \
+  } while (0)
 #endif
 
 #define bit(b) (1UL << (b))
 #define _BV(b) (1UL << (b))
 
-#define digitalPinToPort(pin)       (((pin)>31)?1:0)
-#define digitalPinToBitMask(pin)    (1UL << (((pin)>31)?((pin)-32):(pin)))
-#define digitalPinToTimer(pin)      (0)
-#define analogInPinToBit(P)         (P)
-#define portOutputRegister(port)    ((volatile uint32_t*)((port)?GPIO_OUT1_REG:GPIO_OUT_REG))
-#define portInputRegister(port)     ((volatile uint32_t*)((port)?GPIO_IN1_REG:GPIO_IN_REG))
-#define portModeRegister(port)      ((volatile uint32_t*)((port)?GPIO_ENABLE1_REG:GPIO_ENABLE_REG))
+#define digitalPinToTimer(pin) (0)
+#define analogInPinToBit(P)    (P)
+#if SOC_GPIO_PIN_COUNT <= 32
+#define digitalPinToPort(pin)    (0)
+#define digitalPinToBitMask(pin) (1UL << digitalPinToGPIONumber(pin))
+#define portOutputRegister(port) ((volatile uint32_t *)GPIO_OUT_REG)
+#define portInputRegister(port)  ((volatile uint32_t *)GPIO_IN_REG)
+#define portModeRegister(port)   ((volatile uint32_t *)GPIO_ENABLE_REG)
+#elif SOC_GPIO_PIN_COUNT <= 64
+#define digitalPinToPort(pin)    ((digitalPinToGPIONumber(pin) > 31) ? 1 : 0)
+#define digitalPinToBitMask(pin) (1UL << (digitalPinToGPIONumber(pin) & 31))
+#define portOutputRegister(port) ((volatile uint32_t *)((port) ? GPIO_OUT1_REG : GPIO_OUT_REG))
+#define portInputRegister(port)  ((volatile uint32_t *)((port) ? GPIO_IN1_REG : GPIO_IN_REG))
+#define portModeRegister(port)   ((volatile uint32_t *)((port) ? GPIO_ENABLE1_REG : GPIO_ENABLE_REG))
+#else
+#error SOC_GPIO_PIN_COUNT > 64 not implemented
+#endif
 
-#define NOT_A_PIN -1
-#define NOT_A_PORT -1
+#define NOT_A_PIN        -1
+#define NOT_A_PORT       -1
 #define NOT_AN_INTERRUPT -1
-#define NOT_ON_TIMER 0
+#define NOT_ON_TIMER     0
+
+// some defines generic for all SoC moved from variants/board_name/pins_arduino.h
+#define NUM_DIGITAL_PINS SOC_GPIO_PIN_COUNT  // All GPIOs
+#if SOC_ADC_PERIPH_NUM == 1
+#define NUM_ANALOG_INPUTS (SOC_ADC_CHANNEL_NUM(0))  // Depends on the SoC (ESP32C6, ESP32H2, ESP32C2, ESP32P4)
+#elif SOC_ADC_PERIPH_NUM == 2
+#define NUM_ANALOG_INPUTS (SOC_ADC_CHANNEL_NUM(0) + SOC_ADC_CHANNEL_NUM(1))  // Depends on the SoC (ESP32, ESP32S2, ESP32S3, ESP32C3)
+#endif
+#define EXTERNAL_NUM_INTERRUPTS    NUM_DIGITAL_PINS  // All GPIOs
+#define analogInputToDigitalPin(p) (((p) < NUM_ANALOG_INPUTS) ? (analogChannelToDigitalPin(p)) : -1)
+#define digitalPinToInterrupt(p)   ((((uint8_t)digitalPinToGPIONumber(p)) < NUM_DIGITAL_PINS) ? (p) : NOT_AN_INTERRUPT)
+#define digitalPinHasPWM(p)        (((uint8_t)digitalPinToGPIONumber(p)) < NUM_DIGITAL_PINS)
 
 typedef bool boolean;
 typedef uint8_t byte;
 typedef unsigned int word;
 
+#ifdef __cplusplus
 void setup(void);
 void loop(void);
 
+// The default is using Real Hardware random number generator
+// But when randomSeed() is called, it turns to Psedo random
+// generator, exactly as done in Arduino mainstream
+long random(long);
 long random(long, long);
+// Calling randomSeed() will make random()
+// using pseudo random like in Arduino
 void randomSeed(unsigned long);
+// Allow the Application to decide if the random generator
+// will use Real Hardware random generation (true - default)
+// or Pseudo random generation (false) as in Arduino MainStream
+void useRealRandomGenerator(bool useRandomHW);
+#endif
 long map(long, long, long, long, long);
 
 #ifdef __cplusplus
@@ -133,7 +182,7 @@ void initArduino(void);
 unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout);
 unsigned long pulseInLong(uint8_t pin, uint8_t state, unsigned long timeout);
 
-uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder);
+uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder);  // codespell:ignore shiftin
 void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val);
 
 #ifdef __cplusplus
@@ -153,35 +202,53 @@ void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val);
 #include "Udp.h"
 #include "HardwareSerial.h"
 #include "Esp.h"
+#include "freertos_stats.h"
 
+// Use float-compatible stl abs() and round(), we don't use Arduino macros to avoid issues with the C++ libraries
 using std::abs;
 using std::isinf;
 using std::isnan;
 using std::max;
 using std::min;
-using ::round;
+using std::round;
 
 uint16_t makeWord(uint16_t w);
-uint16_t makeWord(byte h, byte l);
+uint16_t makeWord(uint8_t h, uint8_t l);
 
 #define word(...) makeWord(__VA_ARGS__)
 
+size_t getArduinoLoopTaskStackSize(void);
+#define SET_LOOP_TASK_STACK_SIZE(sz)     \
+  size_t getArduinoLoopTaskStackSize() { \
+    return sz;                           \
+  }
+
+bool shouldPrintChipDebugReport(void);
+#define ENABLE_CHIP_DEBUG_REPORT          \
+  bool shouldPrintChipDebugReport(void) { \
+    return true;                          \
+  }
+
+// allows user to bypass esp_spiram_test()
+bool esp_psram_extram_test(void);
+#define BYPASS_SPIRAM_TEST(bypass)    \
+  bool testSPIRAM(void) {             \
+    if (bypass)                       \
+      return true;                    \
+    else                              \
+      return esp_psram_extram_test(); \
+  }
+
 unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout = 1000000L);
 unsigned long pulseInLong(uint8_t pin, uint8_t state, unsigned long timeout = 1000000L);
 
-extern "C" bool getLocalTime(struct tm * info, uint32_t ms = 5000);
-extern "C" void configTime(long gmtOffset_sec, int daylightOffset_sec,
-        const char* server1, const char* server2 = nullptr, const char* server3 = nullptr);
-extern "C" void configTzTime(const char* tz,
-        const char* server1, const char* server2 = nullptr, const char* server3 = nullptr);
-
-// WMath prototypes
-long random(long);
-#endif /* __cplusplus */
-
-#define _min(a,b) ((a)<(b)?(a):(b))
-#define _max(a,b) ((a)>(b)?(a):(b))
+extern "C" bool getLocalTime(struct tm *info, uint32_t ms = 5000);
+extern "C" void configTime(long gmtOffset_sec, int daylightOffset_sec, const char *server1, const char *server2 = nullptr, const char *server3 = nullptr);
+extern "C" void configTzTime(const char *tz, const char *server1, const char *server2 = nullptr, const char *server3 = nullptr);
 
-#include "pins_arduino.h"
+void setToneChannel(uint8_t channel = 0);
+void tone(uint8_t _pin, unsigned int frequency, unsigned long duration = 0);
+void noTone(uint8_t _pin);
 
+#endif /* __cplusplus */
 #endif /* _ESP32_CORE_ARDUINO_H_ */
diff --git a/cores/esp32/Client.h b/cores/esp32/Client.h
index 962cacc51da..ab013612401 100644
--- a/cores/esp32/Client.h
+++ b/cores/esp32/Client.h
@@ -23,26 +23,25 @@
 #include "Stream.h"
 #include "IPAddress.h"
 
-class Client: public Stream
-{
+class Client : public Stream {
 public:
-    virtual int connect(IPAddress ip, uint16_t port) =0;
-    virtual int connect(const char *host, uint16_t port) =0;
-    virtual size_t write(uint8_t) =0;
-    virtual size_t write(const uint8_t *buf, size_t size) =0;
-    virtual int available() = 0;
-    virtual int read() = 0;
-    virtual int read(uint8_t *buf, size_t size) = 0;
-    virtual int peek() = 0;
-    virtual void flush() = 0;
-    virtual void stop() = 0;
-    virtual uint8_t connected() = 0;
-    virtual operator bool() = 0;
+  virtual int connect(IPAddress ip, uint16_t port) = 0;
+  virtual int connect(const char *host, uint16_t port) = 0;
+  virtual size_t write(uint8_t) = 0;
+  virtual size_t write(const uint8_t *buf, size_t size) = 0;
+  virtual int available() = 0;
+  virtual int read() = 0;
+  virtual int read(uint8_t *buf, size_t size) = 0;
+  virtual int peek() = 0;
+  virtual void flush() = 0;
+  virtual void stop() = 0;
+  virtual uint8_t connected() = 0;
+  virtual operator bool() = 0;
+
 protected:
-    uint8_t* rawIPAddress(IPAddress& addr)
-    {
-        return addr.raw_address();
-    }
+  uint8_t *rawIPAddress(IPAddress &addr) {
+    return addr.raw_address();
+  }
 };
 
 #endif
diff --git a/cores/esp32/ColorFormat.c b/cores/esp32/ColorFormat.c
new file mode 100644
index 00000000000..a01123545b3
--- /dev/null
+++ b/cores/esp32/ColorFormat.c
@@ -0,0 +1,279 @@
+/*
+ *
+ *    Copyright (c) 2021 Project CHIP Authors
+ *    All rights reserved.
+ *
+ *    Licensed under the Apache License, Version 2.0 (the "License");
+ *    you may not use this file except in compliance with the License.
+ *    You may obtain a copy of the License at
+ *
+ *        http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *    Unless required by applicable law or agreed to in writing, software
+ *    distributed under the License is distributed on an "AS IS" BASIS,
+ *    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *    See the License for the specific language governing permissions and
+ *    limitations under the License.
+ */
+
+#include "ColorFormat.h"
+
+#include <math.h>
+
+// define a clamp macro to substitute the std::clamp macro which is available from C++17 onwards
+#define clamp(a, min, max) ((a) < (min) ? (min) : ((a) > (max) ? (max) : (a)))
+
+const espHsvColor_t HSV_BLACK = {0, 0, 0};
+const espHsvColor_t HSV_WHITE = {0, 0, 254};
+const espHsvColor_t HSV_RED = {0, 254, 254};
+const espHsvColor_t HSV_YELLOW = {42, 254, 254};
+const espHsvColor_t HSV_GREEN = {84, 254, 254};
+const espHsvColor_t HSV_CYAN = {127, 254, 254};
+const espHsvColor_t HSV_BLUE = {169, 254, 254};
+const espHsvColor_t HSV_MAGENTA = {211, 254, 254};
+
+const espRgbColor_t RGB_BLACK = {0, 0, 0};
+const espRgbColor_t RGB_WHITE = {255, 255, 255};
+const espRgbColor_t RGB_RED = {255, 0, 0};
+const espRgbColor_t RGB_YELLOW = {255, 255, 0};
+const espRgbColor_t RGB_GREEN = {0, 255, 0};
+const espRgbColor_t RGB_CYAN = {0, 255, 255};
+const espRgbColor_t RGB_BLUE = {0, 0, 255};
+const espRgbColor_t RGB_MAGENTA = {255, 0, 255};
+
+// main color temperature values
+const espCtColor_t COOL_WHITE_COLOR_TEMPERATURE = {142};
+const espCtColor_t DAYLIGHT_WHITE_COLOR_TEMPERATURE = {181};
+const espCtColor_t WHITE_COLOR_TEMPERATURE = {250};
+const espCtColor_t SOFT_WHITE_COLOR_TEMPERATURE = {370};
+const espCtColor_t WARM_WHITE_COLOR_TEMPERATURE = {454};
+
+espRgbColor_t espHsvToRgbColor(uint16_t h, uint8_t s, uint8_t v) {
+  espHsvColor_t hsv = {h, s, v};
+  return espHsvColorToRgbColor(hsv);
+}
+
+espRgbColor_t espHsvColorToRgbColor(espHsvColor_t hsv) {
+  espRgbColor_t rgb;
+
+  uint8_t region, p, q, t;
+  uint32_t h, s, v, remainder;
+
+  if (hsv.s == 0) {
+    rgb.r = rgb.g = rgb.b = hsv.v;
+  } else {
+    h = hsv.h;
+    s = hsv.s;
+    v = hsv.v;
+
+    region = h / 43;
+    remainder = (h - (region * 43)) * 6;
+    p = (v * (255 - s)) >> 8;
+    q = (v * (255 - ((s * remainder) >> 8))) >> 8;
+    t = (v * (255 - ((s * (255 - remainder)) >> 8))) >> 8;
+    switch (region) {
+      case 0:  rgb.r = v, rgb.g = t, rgb.b = p; break;
+      case 1:  rgb.r = q, rgb.g = v, rgb.b = p; break;
+      case 2:  rgb.r = p, rgb.g = v, rgb.b = t; break;
+      case 3:  rgb.r = p, rgb.g = q, rgb.b = v; break;
+      case 4:  rgb.r = t, rgb.g = p, rgb.b = v; break;
+      case 5:
+      default: rgb.r = v, rgb.g = p, rgb.b = q; break;
+    }
+  }
+  return rgb;
+}
+
+espHsvColor_t espRgbToHsvColor(uint8_t r, uint8_t g, uint8_t b) {
+  espRgbColor_t rgb = {r, g, b};
+  return espRgbColorToHsvColor(rgb);
+}
+
+espHsvColor_t espRgbColorToHsvColor(espRgbColor_t rgb) {
+  espHsvColor_t hsv;
+  uint8_t rgbMin, rgbMax;
+
+  rgbMin = rgb.r < rgb.g ? (rgb.r < rgb.b ? rgb.r : rgb.b) : (rgb.g < rgb.b ? rgb.g : rgb.b);
+  rgbMax = rgb.r > rgb.g ? (rgb.r > rgb.b ? rgb.r : rgb.b) : (rgb.g > rgb.b ? rgb.g : rgb.b);
+
+  hsv.v = rgbMax;
+  if (hsv.v == 0) {
+    hsv.h = 0;
+    hsv.s = 0;
+    return hsv;
+  }
+
+  hsv.s = 255 * (rgbMax - rgbMin) / hsv.v;
+  if (hsv.s == 0) {
+    hsv.h = 0;
+    return hsv;
+  }
+  if (rgbMax == rgb.r) {
+    hsv.h = 0 + 43 * (rgb.g - rgb.b) / (rgbMax - rgbMin);
+  } else if (rgbMax == rgb.g) {
+    hsv.h = 85 + 43 * (rgb.b - rgb.r) / (rgbMax - rgbMin);
+  } else {
+    hsv.h = 171 + 43 * (rgb.r - rgb.g) / (rgbMax - rgbMin);
+  }
+  return hsv;
+}
+
+espRgbColor_t espXYColorToRgbColor(uint8_t Level, espXyColor_t xy) {
+  return espXYToRgbColor(Level, xy.x, xy.y);
+}
+
+espRgbColor_t espXYToRgbColor(uint8_t Level, uint16_t current_X, uint16_t current_Y) {
+  // convert xyY color space to RGB
+
+  // https://www.easyrgb.com/en/math.php
+  // https://en.wikipedia.org/wiki/SRGB
+  // refer https://en.wikipedia.org/wiki/CIE_1931_color_space#CIE_xy_chromaticity_diagram_and_the_CIE_xyY_color_space
+
+  // The current_X/current_Y attribute contains the current value of the normalized chromaticity value of x/y.
+  // The value of x/y shall be related to the current_X/current_Y attribute by the relationship
+  // x = current_X/65536
+  // y = current_Y/65536
+  // z = 1-x-y
+
+  espRgbColor_t rgb;
+
+  float x, y, z;
+  float X, Y, Z;
+  float r, g, b;
+
+  x = ((float)current_X) / 65535.0f;
+  y = ((float)current_Y) / 65535.0f;
+
+  z = 1.0f - x - y;
+
+  // Calculate XYZ values
+
+  // Y - given brightness in 0 - 1 range
+  Y = ((float)Level) / 254.0f;
+  X = (Y / y) * x;
+  Z = (Y / y) * z;
+
+  // X, Y and Z input refer to a D65/2° standard illuminant.
+  // sR, sG and sB (standard RGB) output range = 0 ÷ 255
+  // convert XYZ to RGB - CIE XYZ to sRGB
+  X = X / 100.0f;
+  Y = Y / 100.0f;
+  Z = Z / 100.0f;
+
+  r = (X * 3.2406f) - (Y * 1.5372f) - (Z * 0.4986f);
+  g = -(X * 0.9689f) + (Y * 1.8758f) + (Z * 0.0415f);
+  b = (X * 0.0557f) - (Y * 0.2040f) + (Z * 1.0570f);
+
+  // apply gamma 2.2 correction
+  r = (r <= 0.0031308f ? 12.92f * r : (1.055f) * pow(r, (1.0f / 2.4f)) - 0.055f);
+  g = (g <= 0.0031308f ? 12.92f * g : (1.055f) * pow(g, (1.0f / 2.4f)) - 0.055f);
+  b = (b <= 0.0031308f ? 12.92f * b : (1.055f) * pow(b, (1.0f / 2.4f)) - 0.055f);
+
+  // Round off
+  r = clamp(r, 0, 1);
+  g = clamp(g, 0, 1);
+  b = clamp(b, 0, 1);
+
+  // these rgb values are in  the range of 0 to 1, convert to limit of HW specific LED
+  rgb.r = (uint8_t)(r * 255);
+  rgb.g = (uint8_t)(g * 255);
+  rgb.b = (uint8_t)(b * 255);
+
+  return rgb;
+}
+
+espXyColor_t espRgbToXYColor(uint8_t r, uint8_t g, uint8_t b) {
+  espRgbColor_t rgb = {r, g, b};
+  return espRgbColorToXYColor(rgb);
+}
+
+espXyColor_t espRgbColorToXYColor(espRgbColor_t rgb) {
+  // convert RGB to xy color space
+
+  // https://www.easyrgb.com/en/math.php
+  // https://en.wikipedia.org/wiki/SRGB
+  // refer https://en.wikipedia.org/wiki/CIE_1931_color_space#CIE_xy_chromaticity_diagram_and_the_CIE_xyY_color_space
+
+  espXyColor_t xy;
+
+  float r, g, b;
+  float X, Y, Z;
+  float x, y;
+
+  r = ((float)rgb.r) / 255.0f;
+  g = ((float)rgb.g) / 255.0f;
+  b = ((float)rgb.b) / 255.0f;
+
+  // convert RGB to XYZ - sRGB to CIE XYZ
+  r = (r <= 0.04045f ? r / 12.92f : pow((r + 0.055f) / 1.055f, 2.4f));
+  g = (g <= 0.04045f ? g / 12.92f : pow((g + 0.055f) / 1.055f, 2.4f));
+  b = (b <= 0.04045f ? b / 12.92f : pow((b + 0.055f) / 1.055f, 2.4f));
+
+  // https://gist.github.com/popcorn245/30afa0f98eea1c2fd34d
+  X = r * 0.649926f + g * 0.103455f + b * 0.197109f;
+  Y = r * 0.234327f + g * 0.743075f + b * 0.022598f;
+  Z = r * 0.0000000f + g * 0.053077f + b * 1.035763f;
+
+  // sR, sG and sB (standard RGB) input range = 0 ÷ 255
+  // X, Y and Z output refer to a D65/2° standard illuminant.
+  X = r * 0.4124564f + g * 0.3575761f + b * 0.1804375f;
+  Y = r * 0.2126729f + g * 0.7151522f + b * 0.0721750f;
+  Z = r * 0.0193339f + g * 0.1191920f + b * 0.9503041f;
+
+  // Calculate xy values
+  x = X / (X + Y + Z);
+  y = Y / (X + Y + Z);
+
+  // convert to 0-65535 range
+  xy.x = (uint16_t)(x * 65535);
+  xy.y = (uint16_t)(y * 65535);
+  return xy;
+}
+
+espRgbColor_t espCTToRgbColor(uint16_t ct) {
+  espCtColor_t ctColor = {ct};
+  return espCTColorToRgbColor(ctColor);
+}
+
+espRgbColor_t espCTColorToRgbColor(espCtColor_t ct) {
+  espRgbColor_t rgb = {0, 0, 0};
+  float r, g, b;
+
+  if (ct.ctMireds == 0) {
+    return rgb;
+  }
+  // Algorithm credits to Tanner Helland: https://tannerhelland.com/2012/09/18/convert-temperature-rgb-algorithm-code.html
+
+  // Convert Mireds to centiKelvins. k = 1,000,000/mired
+  float ctCentiKelvin = 10000 / ct.ctMireds;
+
+  // Red
+  if (ctCentiKelvin <= 66) {
+    r = 255;
+  } else {
+    r = 329.698727446f * pow(ctCentiKelvin - 60, -0.1332047592f);
+  }
+
+  // Green
+  if (ctCentiKelvin <= 66) {
+    g = 99.4708025861f * log(ctCentiKelvin) - 161.1195681661f;
+  } else {
+    g = 288.1221695283f * pow(ctCentiKelvin - 60, -0.0755148492f);
+  }
+
+  // Blue
+  if (ctCentiKelvin >= 66) {
+    b = 255;
+  } else {
+    if (ctCentiKelvin <= 19) {
+      b = 0;
+    } else {
+      b = 138.5177312231 * log(ctCentiKelvin - 10) - 305.0447927307;
+    }
+  }
+  rgb.r = (uint8_t)clamp(r, 0, 255);
+  rgb.g = (uint8_t)clamp(g, 0, 255);
+  rgb.b = (uint8_t)clamp(b, 0, 255);
+
+  return rgb;
+}
diff --git a/cores/esp32/ColorFormat.h b/cores/esp32/ColorFormat.h
new file mode 100644
index 00000000000..0bb87145d16
--- /dev/null
+++ b/cores/esp32/ColorFormat.h
@@ -0,0 +1,70 @@
+/*
+ *
+ *    Copyright (c) 2021 Project CHIP Authors
+ *    All rights reserved.
+ *
+ *    Licensed under the Apache License, Version 2.0 (the "License");
+ *    you may not use this file except in compliance with the License.
+ *    You may obtain a copy of the License at
+ *
+ *        http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *    Unless required by applicable law or agreed to in writing, software
+ *    distributed under the License is distributed on an "AS IS" BASIS,
+ *    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *    See the License for the specific language governing permissions and
+ *    limitations under the License.
+ */
+
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct RgbColor_t {
+  uint8_t r;
+  uint8_t g;
+  uint8_t b;
+};
+
+struct HsvColor_t {
+  uint16_t h;
+  uint8_t s;
+  uint8_t v;
+};
+
+struct XyColor_t {
+  uint16_t x;
+  uint16_t y;
+};
+
+struct CtColor_t {
+  uint16_t ctMireds;
+};
+
+typedef struct RgbColor_t espRgbColor_t;
+typedef struct HsvColor_t espHsvColor_t;
+typedef struct XyColor_t espXyColor_t;
+typedef struct CtColor_t espCtColor_t;
+
+espRgbColor_t espXYToRgbColor(uint8_t Level, uint16_t current_X, uint16_t current_Y);
+espRgbColor_t espXYColorToRgb(uint8_t Level, espXyColor_t xy);
+espXyColor_t espRgbColorToXYColor(espRgbColor_t rgb);
+espXyColor_t espRgbToXYColor(uint8_t r, uint8_t g, uint8_t b);
+espRgbColor_t espHsvColorToRgbColor(espHsvColor_t hsv);
+espRgbColor_t espHsvToRgbColor(uint16_t h, uint8_t s, uint8_t v);
+espRgbColor_t espCTColorToRgbColor(espCtColor_t ct);
+espRgbColor_t espCTToRgbColor(uint16_t ct);
+espHsvColor_t espRgbColorToHsvColor(espRgbColor_t rgb);
+espHsvColor_t espRgbToHsvColor(uint8_t r, uint8_t g, uint8_t b);
+
+extern const espHsvColor_t HSV_BLACK, HSV_WHITE, HSV_RED, HSV_YELLOW, HSV_GREEN, HSV_CYAN, HSV_BLUE, HSV_MAGENTA;
+extern const espCtColor_t COOL_WHITE_COLOR_TEMPERATURE, DAYLIGHT_WHITE_COLOR_TEMPERATURE, WHITE_COLOR_TEMPERATURE, SOFT_WHITE_COLOR_TEMPERATURE,
+  WARM_WHITE_COLOR_TEMPERATURE;
+extern const espRgbColor_t RGB_BLACK, RGB_WHITE, RGB_RED, RGB_YELLOW, RGB_GREEN, RGB_CYAN, RGB_BLUE, RGB_MAGENTA;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/cores/esp32/Esp.cpp b/cores/esp32/Esp.cpp
index b44b85c97f0..9f90a828b25 100644
--- a/cores/esp32/Esp.cpp
+++ b/cores/esp32/Esp.cpp
@@ -19,12 +19,10 @@
 
 #include "Arduino.h"
 #include "Esp.h"
-#include "rom/spi_flash.h"
 #include "esp_sleep.h"
-#include "esp_spi_flash.h"
+#include "spi_flash_mmap.h"
 #include <memory>
 #include <soc/soc.h>
-#include <soc/efuse_reg.h>
 #include <esp_partition.h>
 extern "C" {
 #include "esp_ota_ops.h"
@@ -32,6 +30,56 @@ extern "C" {
 }
 #include <MD5Builder.h>
 
+#include "soc/spi_reg.h"
+#include "esp_system.h"
+#include "esp_chip_info.h"
+#include "esp_mac.h"
+#include "esp_flash.h"
+#ifdef ESP_IDF_VERSION_MAJOR  // IDF 4+
+#if CONFIG_IDF_TARGET_ESP32   // ESP32/PICO-D4
+#include "esp32/rom/spi_flash.h"
+#include "soc/efuse_reg.h"
+#define ESP_FLASH_IMAGE_BASE 0x1000  // Flash offset containing flash size and spi mode
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/spi_flash.h"
+#include "soc/efuse_reg.h"
+#define ESP_FLASH_IMAGE_BASE 0x1000
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/spi_flash.h"
+#include "soc/efuse_reg.h"
+#define ESP_FLASH_IMAGE_BASE 0x0000  // Esp32s3 is located at 0x0000
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x0000  // Esp32c2 is located at 0x0000
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x0000  // Esp32c3 is located at 0x0000
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x0000  // Esp32c6 is located at 0x0000
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x0000  // Esp32h2 is located at 0x0000
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x2000  // Esp32p4 is located at 0x2000
+#else
+#error Target CONFIG_IDF_TARGET is not supported
+#endif
+#else  // ESP32 Before IDF 4.0
+#include "rom/spi_flash.h"
+#define ESP_FLASH_IMAGE_BASE 0x1000
+#endif
+
+// REG_SPI_BASE is not defined for S3/C3 ??
+
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
+#ifdef REG_SPI_BASE
+#undef REG_SPI_BASE
+#endif  // REG_SPI_BASE
+#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000)))
+#endif  // TARGET
+
 /**
  * User-defined Literals
  *  usage:
@@ -39,321 +87,423 @@ extern "C" {
  *   uint32_t = test = 10_MHz; // --> 10000000
  */
 
-unsigned long long operator"" _kHz(unsigned long long x)
-{
-    return x * 1000;
+unsigned long long operator"" _kHz(unsigned long long x) {
+  return x * 1000;
 }
 
-unsigned long long operator"" _MHz(unsigned long long x)
-{
-    return x * 1000 * 1000;
+unsigned long long operator"" _MHz(unsigned long long x) {
+  return x * 1000 * 1000;
 }
 
-unsigned long long operator"" _GHz(unsigned long long x)
-{
-    return x * 1000 * 1000 * 1000;
+unsigned long long operator"" _GHz(unsigned long long x) {
+  return x * 1000 * 1000 * 1000;
 }
 
-unsigned long long operator"" _kBit(unsigned long long x)
-{
-    return x * 1024;
+unsigned long long operator"" _kBit(unsigned long long x) {
+  return x * 1024;
 }
 
-unsigned long long operator"" _MBit(unsigned long long x)
-{
-    return x * 1024 * 1024;
+unsigned long long operator"" _MBit(unsigned long long x) {
+  return x * 1024 * 1024;
 }
 
-unsigned long long operator"" _GBit(unsigned long long x)
-{
-    return x * 1024 * 1024 * 1024;
+unsigned long long operator"" _GBit(unsigned long long x) {
+  return x * 1024 * 1024 * 1024;
 }
 
-unsigned long long operator"" _kB(unsigned long long x)
-{
-    return x * 1024;
+unsigned long long operator"" _kB(unsigned long long x) {
+  return x * 1024;
 }
 
-unsigned long long operator"" _MB(unsigned long long x)
-{
-    return x * 1024 * 1024;
+unsigned long long operator"" _MB(unsigned long long x) {
+  return x * 1024 * 1024;
 }
 
-unsigned long long operator"" _GB(unsigned long long x)
-{
-    return x * 1024 * 1024 * 1024;
+unsigned long long operator"" _GB(unsigned long long x) {
+  return x * 1024 * 1024 * 1024;
 }
 
-
 EspClass ESP;
 
-void EspClass::deepSleep(uint32_t time_us)
-{
-    esp_deep_sleep(time_us);
+void EspClass::deepSleep(uint64_t time_us) {
+  esp_deep_sleep(time_us);
 }
 
-void EspClass::restart(void)
-{
-    esp_restart();
+void EspClass::restart(void) {
+  esp_restart();
 }
 
-uint32_t EspClass::getHeapSize(void)
-{
-    multi_heap_info_t info;
-    heap_caps_get_info(&info, MALLOC_CAP_INTERNAL);
-    return info.total_free_bytes + info.total_allocated_bytes;
+uint32_t EspClass::getHeapSize(void) {
+  return heap_caps_get_total_size(MALLOC_CAP_INTERNAL);
 }
 
-uint32_t EspClass::getFreeHeap(void)
-{
-    return heap_caps_get_free_size(MALLOC_CAP_INTERNAL);
+uint32_t EspClass::getFreeHeap(void) {
+  return heap_caps_get_free_size(MALLOC_CAP_INTERNAL);
 }
 
-uint32_t EspClass::getMinFreeHeap(void)
-{
-    return heap_caps_get_minimum_free_size(MALLOC_CAP_INTERNAL);
+uint32_t EspClass::getMinFreeHeap(void) {
+  return heap_caps_get_minimum_free_size(MALLOC_CAP_INTERNAL);
 }
 
-uint32_t EspClass::getMaxAllocHeap(void)
-{
-    return heap_caps_get_largest_free_block(MALLOC_CAP_INTERNAL);
+uint32_t EspClass::getMaxAllocHeap(void) {
+  return heap_caps_get_largest_free_block(MALLOC_CAP_INTERNAL);
 }
 
-uint32_t EspClass::getPsramSize(void)
-{
-    multi_heap_info_t info;
-    heap_caps_get_info(&info, MALLOC_CAP_SPIRAM);
-    return info.total_free_bytes + info.total_allocated_bytes;
+uint32_t EspClass::getPsramSize(void) {
+  if (psramFound()) {
+    return heap_caps_get_total_size(MALLOC_CAP_SPIRAM);
+  }
+  return 0;
 }
 
-uint32_t EspClass::getFreePsram(void)
-{
+uint32_t EspClass::getFreePsram(void) {
+  if (psramFound()) {
     return heap_caps_get_free_size(MALLOC_CAP_SPIRAM);
+  }
+  return 0;
 }
 
-uint32_t EspClass::getMinFreePsram(void)
-{
+uint32_t EspClass::getMinFreePsram(void) {
+  if (psramFound()) {
     return heap_caps_get_minimum_free_size(MALLOC_CAP_SPIRAM);
+  }
+  return 0;
 }
 
-uint32_t EspClass::getMaxAllocPsram(void)
-{
+uint32_t EspClass::getMaxAllocPsram(void) {
+  if (psramFound()) {
     return heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM);
+  }
+  return 0;
 }
 
 static uint32_t sketchSize(sketchSize_t response) {
-    esp_image_metadata_t data;
-    const esp_partition_t *running = esp_ota_get_running_partition();
-    if (!running) return 0;
-    const esp_partition_pos_t running_pos  = {
-        .offset = running->address,
-        .size = running->size,
-    };
-    data.start_addr = running_pos.offset;
-    esp_image_verify(ESP_IMAGE_VERIFY, &running_pos, &data);
-    if (response) {
-        return running_pos.size - data.image_len;
-    } else {
-        return data.image_len;
-    }
-}
-    
-uint32_t EspClass::getSketchSize () {
-    return sketchSize(SKETCH_SIZE_TOTAL);
-}
-
-String EspClass::getSketchMD5()
-{
-    static String result;
-    if (result.length()) {
-        return result;
-    }
-    uint32_t lengthLeft = getSketchSize();
-
-    const esp_partition_t *running = esp_ota_get_running_partition();
-    if (!running) {
-        log_e("Partition could not be found");
-
-        return String();
-    }
-    const size_t bufSize = SPI_FLASH_SEC_SIZE;
-    std::unique_ptr<uint8_t[]> buf(new uint8_t[bufSize]);
-    uint32_t offset = 0;
-    if(!buf.get()) {
-        log_e("Not enough memory to allocate buffer");
-
-        return String();
-    }
-    MD5Builder md5;
-    md5.begin();
-    while( lengthLeft > 0) {
-        size_t readBytes = (lengthLeft < bufSize) ? lengthLeft : bufSize;
-        if (!ESP.flashRead(running->address + offset, reinterpret_cast<uint32_t*>(buf.get()), (readBytes + 3) & ~3)) {
-            log_e("Could not read buffer from flash");
-
-            return String();
-        }
-        md5.add(buf.get(), readBytes);
-        lengthLeft -= readBytes;
-        offset += readBytes;
-    }
-    md5.calculate();
-    result = md5.toString();
+  esp_image_metadata_t data;
+  const esp_partition_t *running = esp_ota_get_running_partition();
+  if (!running) {
+    return 0;
+  }
+  const esp_partition_pos_t running_pos = {
+    .offset = running->address,
+    .size = running->size,
+  };
+  data.start_addr = running_pos.offset;
+  esp_image_verify(ESP_IMAGE_VERIFY, &running_pos, &data);
+  if (response) {
+    return running_pos.size - data.image_len;
+  } else {
+    return data.image_len;
+  }
+}
+
+uint32_t EspClass::getSketchSize() {
+  return sketchSize(SKETCH_SIZE_TOTAL);
+}
+
+String EspClass::getSketchMD5() {
+  static String result;
+  if (result.length()) {
     return result;
-}
-
-uint32_t EspClass::getFreeSketchSpace () {
-    const esp_partition_t* _partition = esp_ota_get_next_update_partition(NULL);
-    if(!_partition){
-        return 0;
+  }
+  uint32_t lengthLeft = getSketchSize();
+
+  const esp_partition_t *running = esp_ota_get_running_partition();
+  if (!running) {
+    log_e("Partition could not be found");
+    return String();
+  }
+
+  const size_t bufSize = SPI_FLASH_SEC_SIZE;
+  uint8_t *pb = (uint8_t *)malloc(bufSize);
+  if (!pb) {
+    log_e("Not enough memory to allocate buffer");
+    return String();
+  }
+  uint32_t offset = 0;
+
+  MD5Builder md5;
+  md5.begin();
+  while (lengthLeft > 0) {
+    size_t readBytes = (lengthLeft < bufSize) ? lengthLeft : bufSize;
+    if (!ESP.flashRead(running->address + offset, (uint32_t *)pb, (readBytes + 3) & ~3)) {
+      free(pb);
+      log_e("Could not read buffer from flash");
+      return String();
     }
-
-    return _partition->size;
-}
-
-uint8_t EspClass::getChipRevision(void)
-{
-    esp_chip_info_t chip_info;
-    esp_chip_info(&chip_info);
-    return chip_info.revision;
-}
-
-const char * EspClass::getChipModel(void)
-{
-    uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
-    uint32_t pkg_ver = chip_ver & 0x7;
-    switch (pkg_ver) {
-        case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 :
-            return "ESP32-D0WDQ6";
-        case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 :
-            return "ESP32-D0WDQ5";
-        case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 :
-            return "ESP32-D2WDQ5";
-        case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 :
-            return "ESP32-PICO-D2";
-        case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 :
-            return "ESP32-PICO-D4";
-        default:
-            return "Unknown";
+    md5.add(pb, readBytes);
+    lengthLeft -= readBytes;
+    offset += readBytes;
+
+#if CONFIG_FREERTOS_UNICORE
+    delay(1);  // Fix solo WDT
+#endif
+  }
+  free(pb);
+  md5.calculate();
+  result = md5.toString();
+  return result;
+}
+
+uint32_t EspClass::getFreeSketchSpace() {
+  const esp_partition_t *_partition = esp_ota_get_next_update_partition(NULL);
+  if (!_partition) {
+    return 0;
+  }
+
+  return _partition->size;
+}
+
+uint16_t EspClass::getChipRevision(void) {
+  esp_chip_info_t chip_info;
+  esp_chip_info(&chip_info);
+  return chip_info.revision;
+}
+
+const char *EspClass::getChipModel(void) {
+#if CONFIG_IDF_TARGET_ESP32
+  uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_PACKAGE);
+  uint32_t pkg_ver = chip_ver & 0x7;
+  switch (pkg_ver) {
+    case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6:
+      if ((getChipRevision() / 100) == 3) {
+        return "ESP32-D0WDQ6-V3";
+      } else {
+        return "ESP32-D0WDQ6";
+      }
+    case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5:
+      if ((getChipRevision() / 100) == 3) {
+        return "ESP32-D0WD-V3";
+      } else {
+        return "ESP32-D0WD";
+      }
+    case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:   return "ESP32-D2WD";
+    case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH:    return "ESP32-U4WDH";
+    case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:   return "ESP32-PICO-D4";
+    case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302: return "ESP32-PICO-V3-02";
+    case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3: return "ESP32-D0WDR2-V3";
+    default:                                  return "Unknown";
+  }
+#elif CONFIG_IDF_TARGET_ESP32S2
+  uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
+  switch (pkg_ver) {
+    case 0:  return "ESP32-S2";
+    case 1:  return "ESP32-S2FH16";
+    case 2:  return "ESP32-S2FH32";
+    default: return "ESP32-S2 (Unknown)";
+  }
+#else
+  esp_chip_info_t chip_info;
+  esp_chip_info(&chip_info);
+  switch (chip_info.model) {
+    case CHIP_ESP32S3: return "ESP32-S3";
+    case CHIP_ESP32C3: return "ESP32-C3";
+    case CHIP_ESP32C2: return "ESP32-C2";
+    case CHIP_ESP32C6: return "ESP32-C6";
+    case CHIP_ESP32H2: return "ESP32-H2";
+    case CHIP_ESP32P4: return "ESP32-P4";
+    default:           return "UNKNOWN";
+  }
+#endif
+}
+
+uint8_t EspClass::getChipCores(void) {
+  esp_chip_info_t chip_info;
+  esp_chip_info(&chip_info);
+  return chip_info.cores;
+}
+
+const char *EspClass::getSdkVersion(void) {
+  return esp_get_idf_version();
+}
+
+const char *EspClass::getCoreVersion(void) {
+  return ESP_ARDUINO_VERSION_STR;
+}
+
+uint32_t ESP_getFlashChipId(void) {
+  uint32_t id = g_rom_flashchip.device_id;
+  id = ((id & 0xff) << 16) | ((id >> 16) & 0xff) | (id & 0xff00);
+  return id;
+}
+
+uint32_t EspClass::getFlashChipSize(void) {
+  uint32_t id = (ESP_getFlashChipId() >> 16) & 0xFF;
+  return 2 << (id - 1);
+}
+
+uint32_t EspClass::getFlashChipSpeed(void) {
+  esp_image_header_t fhdr;
+  if (esp_flash_read(esp_flash_default_chip, (void *)&fhdr, ESP_FLASH_IMAGE_BASE, sizeof(esp_image_header_t)) && fhdr.magic != ESP_IMAGE_HEADER_MAGIC) {
+    return 0;
+  }
+  return magicFlashChipSpeed(fhdr.spi_speed);
+}
+
+// FIXME for P4
+#if !defined(CONFIG_IDF_TARGET_ESP32P4)
+FlashMode_t EspClass::getFlashChipMode(void) {
+#if CONFIG_IDF_TARGET_ESP32S2
+  uint32_t spi_ctrl = REG_READ(PERIPHS_SPI_FLASH_CTRL);
+#else
+#if CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
+  uint32_t spi_ctrl = REG_READ(DR_REG_SPI0_BASE + 0x8);
+#else
+  uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
+#endif
+#endif
+  /* Not all of the following constants are already defined in older versions of spi_reg.h, so do it manually for now*/
+  if (spi_ctrl & BIT(24)) {  //SPI_FREAD_QIO
+    return (FM_QIO);
+  } else if (spi_ctrl & BIT(20)) {  //SPI_FREAD_QUAD
+    return (FM_QOUT);
+  } else if (spi_ctrl & BIT(23)) {  //SPI_FREAD_DIO
+    return (FM_DIO);
+  } else if (spi_ctrl & BIT(14)) {  // SPI_FREAD_DUAL
+    return (FM_DOUT);
+  } else if (spi_ctrl & BIT(13)) {  //SPI_FASTRD_MODE
+    return (FM_FAST_READ);
+  } else {
+    return (FM_SLOW_READ);
+  }
+  return (FM_DOUT);
+}
+#endif  // if !defined(CONFIG_IDF_TARGET_ESP32P4)
+
+uint32_t EspClass::magicFlashChipSize(uint8_t byte) {
+  /*
+    FLASH_SIZES = {
+        "1MB": 0x00,
+        "2MB": 0x10,
+        "4MB": 0x20,
+        "8MB": 0x30,
+        "16MB": 0x40,
+        "32MB": 0x50,
+        "64MB": 0x60,
+        "128MB": 0x70,
     }
-}
-
-uint8_t EspClass::getChipCores(void)
-{
-    esp_chip_info_t chip_info;
-    esp_chip_info(&chip_info);
-    return chip_info.cores;
-}
-
-const char * EspClass::getSdkVersion(void)
-{
-    return esp_get_idf_version();
-}
-
-uint32_t EspClass::getFlashChipSize(void)
-{
-    esp_image_header_t fhdr;
-    if(flashRead(0x1000, (uint32_t*)&fhdr, sizeof(esp_image_header_t)) && fhdr.magic != ESP_IMAGE_HEADER_MAGIC) {
-        return 0;
+*/
+  switch (byte & 0x0F) {
+    case 0x0: return (1_MB);    // 8 MBit (1MB)
+    case 0x1: return (2_MB);    // 16 MBit (2MB)
+    case 0x2: return (4_MB);    // 32 MBit (4MB)
+    case 0x3: return (8_MB);    // 64 MBit (8MB)
+    case 0x4: return (16_MB);   // 128 MBit (16MB)
+    case 0x5: return (32_MB);   // 256 MBit (32MB)
+    case 0x6: return (64_MB);   // 512 MBit (64MB)
+    case 0x7: return (128_MB);  // 1 GBit (128MB)
+    default:                    // fail?
+      return 0;
+  }
+}
+
+uint32_t EspClass::magicFlashChipSpeed(uint8_t byte) {
+#if CONFIG_IDF_TARGET_ESP32C2
+  /*
+    FLASH_FREQUENCY = {
+        "60m": 0xF,
+        "30m": 0x0,
+        "20m": 0x1,
+        "15m": 0x2,
     }
-    return magicFlashChipSize(fhdr.spi_size);
-}
-
-uint32_t EspClass::getFlashChipSpeed(void)
-{
-    esp_image_header_t fhdr;
-    if(flashRead(0x1000, (uint32_t*)&fhdr, sizeof(esp_image_header_t)) && fhdr.magic != ESP_IMAGE_HEADER_MAGIC) {
-        return 0;
-    }
-    return magicFlashChipSpeed(fhdr.spi_speed);
-}
-
-FlashMode_t EspClass::getFlashChipMode(void)
-{
-    esp_image_header_t fhdr;
-    if(flashRead(0x1000, (uint32_t*)&fhdr, sizeof(esp_image_header_t)) && fhdr.magic != ESP_IMAGE_HEADER_MAGIC) {
-        return FM_UNKNOWN;
+*/
+  switch (byte & 0x0F) {
+    case 0xF: return (60_MHz);
+    case 0x0: return (30_MHz);
+    case 0x1: return (20_MHz);
+    case 0x2: return (15_MHz);
+    default:  // fail?
+      return 0;
+  }
+
+#elif CONFIG_IDF_TARGET_ESP32C6
+  /*
+   FLASH_FREQUENCY = {
+        "80m": 0x0,  # workaround for wrong mspi HS div value in ROM
+        "40m": 0x0,
+        "20m": 0x2,
     }
-    return magicFlashChipMode(fhdr.spi_mode);
-}
-
-uint32_t EspClass::magicFlashChipSize(uint8_t byte)
-{
-    switch(byte & 0x0F) {
-    case 0x0: // 8 MBit (1MB)
-        return (1_MB);
-    case 0x1: // 16 MBit (2MB)
-        return (2_MB);
-    case 0x2: // 32 MBit (4MB)
-        return (4_MB);
-    case 0x3: // 64 MBit (8MB)
-        return (8_MB);
-    case 0x4: // 128 MBit (16MB)
-        return (16_MB);
-    default: // fail?
-        return 0;
+*/
+  switch (byte & 0x0F) {
+    case 0x0: return (80_MHz);
+    case 0x2: return (20_MHz);
+    default:  // fail?
+      return 0;
+  }
+
+#elif CONFIG_IDF_TARGET_ESP32H2
+
+  /*
+    FLASH_FREQUENCY = {
+        "48m": 0xF,
+        "24m": 0x0,
+        "16m": 0x1,
+        "12m": 0x2,
     }
-}
-
-uint32_t EspClass::magicFlashChipSpeed(uint8_t byte)
-{
-    switch(byte & 0x0F) {
-    case 0x0: // 40 MHz
-        return (40_MHz);
-    case 0x1: // 26 MHz
-        return (26_MHz);
-    case 0x2: // 20 MHz
-        return (20_MHz);
-    case 0xf: // 80 MHz
-        return (80_MHz);
-    default: // fail?
-        return 0;
+*/
+  switch (byte & 0x0F) {
+    case 0xF: return (48_MHz);
+    case 0x0: return (24_MHz);
+    case 0x1: return (16_MHz);
+    case 0x2: return (12_MHz);
+    default:  // fail?
+      return 0;
+  }
+
+#else
+  /*
+    FLASH_FREQUENCY = {
+        "80m": 0xF,
+        "40m": 0x0,
+        "26m": 0x1,
+        "20m": 0x2,
     }
+*/
+  switch (byte & 0x0F) {
+    case 0xF: return (80_MHz);
+    case 0x0: return (40_MHz);
+    case 0x1: return (26_MHz);
+    case 0x2: return (20_MHz);
+    default:  // fail?
+      return 0;
+  }
+#endif
 }
 
-FlashMode_t EspClass::magicFlashChipMode(uint8_t byte)
-{
-    FlashMode_t mode = (FlashMode_t) byte;
-    if(mode > FM_SLOW_READ) {
-        mode = FM_UNKNOWN;
-    }
-    return mode;
+FlashMode_t EspClass::magicFlashChipMode(uint8_t byte) {
+  FlashMode_t mode = (FlashMode_t)byte;
+  if (mode > FM_SLOW_READ) {
+    mode = FM_UNKNOWN;
+  }
+  return mode;
 }
 
-bool EspClass::flashEraseSector(uint32_t sector)
-{
-    return spi_flash_erase_sector(sector) == ESP_OK;
+bool EspClass::flashEraseSector(uint32_t sector) {
+  return esp_flash_erase_region(esp_flash_default_chip, sector * SPI_FLASH_SEC_SIZE, SPI_FLASH_SEC_SIZE) == ESP_OK;
 }
 
 // Warning: These functions do not work with encrypted flash
-bool EspClass::flashWrite(uint32_t offset, uint32_t *data, size_t size)
-{
-    return spi_flash_write(offset, (uint32_t*) data, size) == ESP_OK;
+bool EspClass::flashWrite(uint32_t offset, uint32_t *data, size_t size) {
+  return esp_flash_write(esp_flash_default_chip, (const void *)data, offset, size) == ESP_OK;
 }
 
-bool EspClass::flashRead(uint32_t offset, uint32_t *data, size_t size)
-{
-    return spi_flash_read(offset, (uint32_t*) data, size) == ESP_OK;
+bool EspClass::flashRead(uint32_t offset, uint32_t *data, size_t size) {
+  return esp_flash_read(esp_flash_default_chip, (void *)data, offset, size) == ESP_OK;
 }
 
-bool EspClass::partitionEraseRange(const esp_partition_t *partition, uint32_t offset, size_t size) 
-{
-    return esp_partition_erase_range(partition, offset, size) == ESP_OK;
+bool EspClass::partitionEraseRange(const esp_partition_t *partition, uint32_t offset, size_t size) {
+  return esp_partition_erase_range(partition, offset, size) == ESP_OK;
 }
 
-bool EspClass::partitionWrite(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size) 
-{
-    return esp_partition_write(partition, offset, data, size) == ESP_OK;
+bool EspClass::partitionWrite(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size) {
+  return esp_partition_write(partition, offset, data, size) == ESP_OK;
 }
 
-bool EspClass::partitionRead(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size) 
-{
-    return esp_partition_read(partition, offset, data, size) == ESP_OK;
+bool EspClass::partitionRead(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size) {
+  return esp_partition_read(partition, offset, data, size) == ESP_OK;
 }
 
-uint64_t EspClass::getEfuseMac(void)
-{
-    uint64_t _chipmacid = 0LL;
-    esp_efuse_mac_get_default((uint8_t*) (&_chipmacid));
-    return _chipmacid;
+uint64_t EspClass::getEfuseMac(void) {
+  uint64_t _chipmacid = 0LL;
+  esp_efuse_mac_get_default((uint8_t *)(&_chipmacid));
+  return _chipmacid;
 }
diff --git a/cores/esp32/Esp.h b/cores/esp32/Esp.h
index 76baadd72da..41068fb9e65 100644
--- a/cores/esp32/Esp.h
+++ b/cores/esp32/Esp.h
@@ -22,99 +22,99 @@
 
 #include <Arduino.h>
 #include <esp_partition.h>
+#include <hal/cpu_hal.h>
+#include "esp_cpu.h"
 
 /**
- * AVR macros for WDT managment
+ * AVR macros for WDT management
  */
 typedef enum {
-    WDTO_0MS    = 0,   //!< WDTO_0MS
-    WDTO_15MS   = 15,  //!< WDTO_15MS
-    WDTO_30MS   = 30,  //!< WDTO_30MS
-    WDTO_60MS   = 60,  //!< WDTO_60MS
-    WDTO_120MS  = 120, //!< WDTO_120MS
-    WDTO_250MS  = 250, //!< WDTO_250MS
-    WDTO_500MS  = 500, //!< WDTO_500MS
-    WDTO_1S     = 1000,//!< WDTO_1S
-    WDTO_2S     = 2000,//!< WDTO_2S
-    WDTO_4S     = 4000,//!< WDTO_4S
-    WDTO_8S     = 8000 //!< WDTO_8S
+  WDTO_0MS = 0,      //!< WDTO_0MS
+  WDTO_15MS = 15,    //!< WDTO_15MS
+  WDTO_30MS = 30,    //!< WDTO_30MS
+  WDTO_60MS = 60,    //!< WDTO_60MS
+  WDTO_120MS = 120,  //!< WDTO_120MS
+  WDTO_250MS = 250,  //!< WDTO_250MS
+  WDTO_500MS = 500,  //!< WDTO_500MS
+  WDTO_1S = 1000,    //!< WDTO_1S
+  WDTO_2S = 2000,    //!< WDTO_2S
+  WDTO_4S = 4000,    //!< WDTO_4S
+  WDTO_8S = 8000     //!< WDTO_8S
 } WDTO_t;
 
-
 typedef enum {
-    FM_QIO = 0x00,
-    FM_QOUT = 0x01,
-    FM_DIO = 0x02,
-    FM_DOUT = 0x03,
-    FM_FAST_READ = 0x04,
-    FM_SLOW_READ = 0x05,
-    FM_UNKNOWN = 0xff
+  FM_QIO = 0x00,
+  FM_QOUT = 0x01,
+  FM_DIO = 0x02,
+  FM_DOUT = 0x03,
+  FM_FAST_READ = 0x04,
+  FM_SLOW_READ = 0x05,
+  FM_UNKNOWN = 0xff
 } FlashMode_t;
 
 typedef enum {
-    SKETCH_SIZE_TOTAL = 0,
-    SKETCH_SIZE_FREE = 1
+  SKETCH_SIZE_TOTAL = 0,
+  SKETCH_SIZE_FREE = 1
 } sketchSize_t;
 
-class EspClass
-{
+class EspClass {
 public:
-    EspClass() {}
-    ~EspClass() {}
-    void restart();
-
-    //Internal RAM
-    uint32_t getHeapSize(); //total heap size
-    uint32_t getFreeHeap(); //available heap
-    uint32_t getMinFreeHeap(); //lowest level of free heap since boot
-    uint32_t getMaxAllocHeap(); //largest block of heap that can be allocated at once
-
-    //SPI RAM
-    uint32_t getPsramSize();
-    uint32_t getFreePsram();
-    uint32_t getMinFreePsram();
-    uint32_t getMaxAllocPsram();
-
-    uint8_t getChipRevision();
-    const char * getChipModel();
-    uint8_t getChipCores();
-    uint32_t getCpuFreqMHz(){ return getCpuFrequencyMhz(); }
-    inline uint32_t getCycleCount() __attribute__((always_inline));
-    const char * getSdkVersion();
-
-    void deepSleep(uint32_t time_us);
-
-    uint32_t getFlashChipSize();
-    uint32_t getFlashChipSpeed();
-    FlashMode_t getFlashChipMode();
-
-    uint32_t magicFlashChipSize(uint8_t byte);
-    uint32_t magicFlashChipSpeed(uint8_t byte);
-    FlashMode_t magicFlashChipMode(uint8_t byte);
-
-    uint32_t getSketchSize();
-    String getSketchMD5();
-    uint32_t getFreeSketchSpace();
-
-    bool flashEraseSector(uint32_t sector);
-    bool flashWrite(uint32_t offset, uint32_t *data, size_t size);
-    bool flashRead(uint32_t offset, uint32_t *data, size_t size);
-
-    bool partitionEraseRange(const esp_partition_t *partition, uint32_t offset, size_t size);
-    bool partitionWrite(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size);
-    bool partitionRead(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size);
-
-    uint64_t getEfuseMac();
-
+  EspClass() {}
+  ~EspClass() {}
+  void restart();
+
+  //Internal RAM
+  uint32_t getHeapSize();      //total heap size
+  uint32_t getFreeHeap();      //available heap
+  uint32_t getMinFreeHeap();   //lowest level of free heap since boot
+  uint32_t getMaxAllocHeap();  //largest block of heap that can be allocated at once
+
+  //SPI RAM
+  uint32_t getPsramSize();
+  uint32_t getFreePsram();
+  uint32_t getMinFreePsram();
+  uint32_t getMaxAllocPsram();
+
+  uint16_t getChipRevision();
+  const char *getChipModel();
+  uint8_t getChipCores();
+  uint32_t getCpuFreqMHz() {
+    return getCpuFrequencyMhz();
+  }
+  inline uint32_t getCycleCount() __attribute__((always_inline));
+
+  const char *getSdkVersion();   //version of ESP-IDF
+  const char *getCoreVersion();  //version of this core
+
+  void deepSleep(uint64_t time_us);
+
+  uint32_t getFlashChipSize();
+  uint32_t getFlashChipSpeed();
+  FlashMode_t getFlashChipMode();
+
+  uint32_t magicFlashChipSize(uint8_t byte);
+  uint32_t magicFlashChipSpeed(uint8_t byte);
+  FlashMode_t magicFlashChipMode(uint8_t byte);
+
+  uint32_t getSketchSize();
+  String getSketchMD5();
+  uint32_t getFreeSketchSpace();
+
+  bool flashEraseSector(uint32_t sector);
+  bool flashWrite(uint32_t offset, uint32_t *data, size_t size);
+  bool flashRead(uint32_t offset, uint32_t *data, size_t size);
+
+  bool partitionEraseRange(const esp_partition_t *partition, uint32_t offset, size_t size);
+  bool partitionWrite(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size);
+  bool partitionRead(const esp_partition_t *partition, uint32_t offset, uint32_t *data, size_t size);
+
+  uint64_t getEfuseMac();
 };
 
-uint32_t IRAM_ATTR EspClass::getCycleCount()
-{
-    uint32_t ccount;
-    __asm__ __volatile__("esync; rsr %0,ccount":"=a" (ccount));
-    return ccount;
+uint32_t ARDUINO_ISR_ATTR EspClass::getCycleCount() {
+  return (uint32_t)esp_cpu_get_cycle_count();
 }
 
 extern EspClass ESP;
 
-#endif //ESP_H
+#endif  //ESP_H
diff --git a/cores/esp32/FirmwareMSC.cpp b/cores/esp32/FirmwareMSC.cpp
new file mode 100644
index 00000000000..2e944ad4df3
--- /dev/null
+++ b/cores/esp32/FirmwareMSC.cpp
@@ -0,0 +1,427 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include "FirmwareMSC.h"
+
+#if CONFIG_TINYUSB_MSC_ENABLED
+
+#include <cstring>
+#include "esp_partition.h"
+#include "esp_ota_ops.h"
+#include "esp_image_format.h"
+#include "pins_arduino.h"
+#include "esp32-hal.h"
+#include "firmware_msc_fat.h"
+#include "spi_flash_mmap.h"
+
+#ifndef USB_FW_MSC_VENDOR_ID
+#define USB_FW_MSC_VENDOR_ID "ESP32"  //max 8 chars
+#endif
+#ifndef USB_FW_MSC_PRODUCT_ID
+#define USB_FW_MSC_PRODUCT_ID "Firmware MSC"  //max 16 chars
+#endif
+#ifndef USB_FW_MSC_PRODUCT_REVISION
+#define USB_FW_MSC_PRODUCT_REVISION "1.0"  //max 4 chars
+#endif
+#ifndef USB_FW_MSC_VOLUME_NAME
+#define USB_FW_MSC_VOLUME_NAME "ESP32-FWMSC"  //max 11 chars
+#endif
+#ifndef USB_FW_MSC_SERIAL_NUMBER
+#define USB_FW_MSC_SERIAL_NUMBER 0x00000000
+#endif
+
+ESP_EVENT_DEFINE_BASE(ARDUINO_FIRMWARE_MSC_EVENTS);
+esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait);
+esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg);
+
+//General Variables
+static uint8_t *msc_ram_disk = NULL;
+static fat_boot_sector_t *msc_boot = NULL;
+static uint8_t *msc_table = NULL;
+static uint16_t msc_table_sectors = 0;
+static uint16_t msc_total_sectors = 0;
+static bool mcs_is_fat16 = false;
+
+//Firmware Read
+static const esp_partition_t *msc_run_partition = NULL;
+static uint16_t fw_start_sector = 0;
+static uint16_t fw_end_sector = 0;
+static size_t fw_size = 0;
+static fat_dir_entry_t *fw_entry = NULL;
+
+//Firmware Write
+typedef enum {
+  MSC_UPDATE_IDLE,
+  MSC_UPDATE_STARTING,
+  MSC_UPDATE_RUNNING,
+  MSC_UPDATE_END
+} msc_update_state_t;
+
+static const esp_partition_t *msc_ota_partition = NULL;
+static msc_update_state_t msc_update_state = MSC_UPDATE_IDLE;
+static uint16_t msc_update_start_sector = 0;
+static uint32_t msc_update_bytes_written = 0;
+static fat_dir_entry_t *msc_update_entry = NULL;
+
+static uint32_t get_firmware_size(const esp_partition_t *partition) {
+  esp_image_metadata_t data;
+  const esp_partition_pos_t running_pos = {
+    .offset = partition->address,
+    .size = partition->size,
+  };
+  data.start_addr = running_pos.offset;
+  esp_image_verify(ESP_IMAGE_VERIFY, &running_pos, &data);
+  return data.image_len;
+}
+
+//Get number of sectors required based on the size of the firmware and OTA partition
+static size_t msc_update_get_required_disk_sectors() {
+  size_t data_sectors = 16;
+  size_t total_sectors = 0;
+  msc_run_partition = esp_ota_get_running_partition();
+  msc_ota_partition = esp_ota_get_next_update_partition(NULL);
+  if (msc_run_partition) {
+    fw_size = get_firmware_size(msc_run_partition);
+    data_sectors += FAT_SIZE_TO_SECTORS(fw_size);
+    log_d("APP size: %u (%u sectors)", fw_size, FAT_SIZE_TO_SECTORS(fw_size));
+  } else {
+    log_w("APP partition not found. Reading disabled");
+  }
+  if (msc_ota_partition) {
+    data_sectors += FAT_SIZE_TO_SECTORS(msc_ota_partition->size);
+    log_d("OTA size: %u (%u sectors)", msc_ota_partition->size, FAT_SIZE_TO_SECTORS(msc_ota_partition->size));
+  } else {
+    log_w("OTA partition not found. Writing disabled");
+  }
+  msc_table_sectors = fat_sectors_per_alloc_table(data_sectors, false);
+  total_sectors = data_sectors + msc_table_sectors + 2;
+  if (total_sectors > 0xFF4) {
+    log_d("USING FAT16");
+    mcs_is_fat16 = true;
+    total_sectors -= msc_table_sectors;
+    msc_table_sectors = fat_sectors_per_alloc_table(data_sectors, true);
+    total_sectors += msc_table_sectors;
+  } else {
+    log_d("USING FAT12");
+    mcs_is_fat16 = false;
+  }
+  log_d("FAT sector size: %u", DISK_SECTOR_SIZE);
+  log_d("FAT data sectors: %u", data_sectors);
+  log_d("FAT table sectors: %u", msc_table_sectors);
+  log_d("FAT total sectors: %u (%uKB)", total_sectors, (total_sectors * DISK_SECTOR_SIZE) / 1024);
+  return total_sectors;
+}
+
+//setup the ramdisk and add the firmware download file
+static bool msc_update_setup_disk(const char *volume_label, uint32_t serial_number) {
+  msc_total_sectors = msc_update_get_required_disk_sectors();
+  uint8_t ram_sectors = msc_table_sectors + 2;
+  msc_ram_disk = (uint8_t *)calloc(ram_sectors, DISK_SECTOR_SIZE);
+  if (!msc_ram_disk) {
+    log_e("Failed to allocate RAM Disk: %u bytes", ram_sectors * DISK_SECTOR_SIZE);
+    return false;
+  }
+  fw_start_sector = ram_sectors;
+  fw_end_sector = fw_start_sector;
+  msc_boot = fat_add_boot_sector(msc_ram_disk, msc_total_sectors, msc_table_sectors, fat_file_system_type(mcs_is_fat16), volume_label, serial_number);
+  msc_table = fat_add_table(msc_ram_disk, msc_boot, mcs_is_fat16);
+  //fat_dir_entry_t * label = fat_add_label(msc_ram_disk, volume_label);
+  if (msc_run_partition) {
+    fw_entry = fat_add_root_file(msc_ram_disk, 0, "FIRMWARE", "BIN", fw_size, 2, mcs_is_fat16);
+    fw_end_sector = FAT_SIZE_TO_SECTORS(fw_size) + fw_start_sector;
+  }
+  return true;
+}
+
+static void msc_update_delete_disk() {
+  fw_entry = NULL;
+  fw_size = 0;
+  fw_end_sector = 0;
+  fw_start_sector = 0;
+  msc_table = NULL;
+  msc_boot = NULL;
+  msc_table_sectors = 0;
+  msc_total_sectors = 0;
+  msc_run_partition = NULL;
+  msc_ota_partition = NULL;
+  msc_update_state = MSC_UPDATE_IDLE;
+  msc_update_start_sector = 0;
+  msc_update_bytes_written = 0;
+  msc_update_entry = NULL;
+  free(msc_ram_disk);
+  msc_ram_disk = NULL;
+}
+
+//filter out entries to only include BINs in the root folder
+static fat_dir_entry_t *msc_update_get_root_bin_entry(uint8_t index) {
+  fat_dir_entry_t *entry = (fat_dir_entry_t *)(msc_ram_disk + ((msc_boot->sectors_per_alloc_table + 1) * DISK_SECTOR_SIZE) + (index * sizeof(fat_dir_entry_t)));
+  fat_lfn_entry_t *lfn = (fat_lfn_entry_t *)entry;
+
+  //empty entry
+  if (entry->file_magic == 0) {
+    return NULL;
+  }
+  //long file name
+  if (lfn->attr == 0x0F && lfn->type == 0x00 && lfn->first_cluster == 0x0000) {
+    return NULL;
+  }
+  //only files marked as archives
+  if (entry->file_attr != FAT_FILE_ATTR_ARCHIVE) {
+    return NULL;
+  }
+  //deleted
+  if (entry->file_magic == 0xE5 || entry->file_magic == 0x05) {
+    return NULL;
+  }
+  //not bins
+  if (memcmp("BIN", entry->file_extension, 3)) {
+    return NULL;
+  }
+  return entry;
+}
+
+//get an empty bin (the host will add an entry for file about to be written with size of zero)
+static fat_dir_entry_t *msc_update_find_new_bin() {
+  for (uint8_t i = 16; i;) {
+    i--;
+    fat_dir_entry_t *entry = msc_update_get_root_bin_entry(i);
+    if (entry && entry->file_size == 0) {
+      return entry;
+    }
+  }
+  return NULL;
+}
+
+//get a bin starting from particular sector
+static fat_dir_entry_t *msc_update_find_bin(uint16_t sector) {
+  for (uint8_t i = 16; i;) {
+    i--;
+    fat_dir_entry_t *entry = msc_update_get_root_bin_entry(i);
+    if (entry && entry->data_start_sector == (sector - msc_boot->sectors_per_alloc_table)) {
+      return entry;
+    }
+  }
+  return NULL;
+}
+
+//write the new data and erase the flash blocks when necessary
+static esp_err_t msc_update_write(const esp_partition_t *partition, uint32_t offset, void *data, size_t size) {
+  esp_err_t err = ESP_OK;
+  if ((offset & (SPI_FLASH_SEC_SIZE - 1)) == 0) {
+    err = esp_partition_erase_range(partition, offset, SPI_FLASH_SEC_SIZE);
+    log_v("ERASE[0x%08X]: %s", offset, (err != ESP_OK) ? "FAIL" : "OK");
+    if (err != ESP_OK) {
+      return err;
+    }
+  }
+  return esp_partition_write(partition, offset, data, size);
+}
+
+//called when error was encountered while updating
+static void msc_update_error() {
+  log_e("UPDATE_ERROR: %u", msc_update_bytes_written);
+  arduino_firmware_msc_event_data_t p;
+  p.error.size = msc_update_bytes_written;
+  arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_ERROR_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY);
+  msc_update_state = MSC_UPDATE_IDLE;
+  msc_update_entry = NULL;
+  msc_update_bytes_written = 0;
+  msc_update_start_sector = 0;
+}
+
+//called when all firmware bytes have been received
+static void msc_update_end() {
+  log_d("UPDATE_END: %u", msc_update_entry->file_size);
+  msc_update_state = MSC_UPDATE_END;
+  size_t ota_size = get_firmware_size(msc_ota_partition);
+  if (ota_size != msc_update_entry->file_size) {
+    log_e("OTA SIZE MISMATCH %u != %u", ota_size, msc_update_entry->file_size);
+    msc_update_error();
+    return;
+  }
+  if (!ota_size || esp_ota_set_boot_partition(msc_ota_partition) != ESP_OK) {
+    log_e("ENABLING OTA PARTITION FAILED");
+    msc_update_error();
+    return;
+  }
+  arduino_firmware_msc_event_data_t p;
+  p.end.size = msc_update_entry->file_size;
+  arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_END_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY);
+}
+
+static int32_t msc_write(uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize) {
+  //log_d("lba: %u, offset: %u, bufsize: %u", lba, offset, bufsize);
+  if (lba < fw_start_sector) {
+    //write to sectors that are in RAM
+    memcpy(msc_ram_disk + (lba * DISK_SECTOR_SIZE) + offset, buffer, bufsize);
+    if (msc_ota_partition && lba == (fw_start_sector - 1)) {
+      //monitor the root folder table
+      if (msc_update_state <= MSC_UPDATE_RUNNING) {
+        fat_dir_entry_t *update_entry = msc_update_find_new_bin();
+        if (update_entry) {
+          if (msc_update_entry) {
+            log_v("REPLACING ENTRY");
+          } else {
+            log_v("ASSIGNING ENTRY");
+          }
+          if (msc_update_state <= MSC_UPDATE_STARTING) {
+            msc_update_state = MSC_UPDATE_STARTING;
+            msc_update_bytes_written = 0;
+            msc_update_start_sector = 0;
+          }
+          msc_update_entry = update_entry;
+        } else if (msc_update_state == MSC_UPDATE_RUNNING) {
+          if (!msc_update_entry && msc_update_start_sector) {
+            msc_update_entry = msc_update_find_bin(msc_update_start_sector);
+          }
+          if (msc_update_entry && msc_update_bytes_written >= msc_update_entry->file_size) {
+            msc_update_end();
+          }
+        }
+      }
+    }
+  } else if (msc_ota_partition && lba >= msc_update_start_sector) {
+    //handle writes to the region where the new firmware will be uploaded
+    arduino_firmware_msc_event_data_t p;
+    if (msc_update_state <= MSC_UPDATE_STARTING && buffer[0] == 0xE9) {
+      msc_update_state = MSC_UPDATE_RUNNING;
+      msc_update_start_sector = lba;
+      msc_update_bytes_written = 0;
+      log_d("UPDATE_START: %u (0x%02X)", lba, lba - msc_boot->sectors_per_alloc_table);
+      arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_START_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY);
+      if (msc_update_write(msc_ota_partition, ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset, buffer, bufsize) == ESP_OK) {
+        log_v("UPDATE_WRITE: %u %u", ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset, bufsize);
+        msc_update_bytes_written = ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset + bufsize;
+        p.write.offset = ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset;
+        p.write.size = bufsize;
+        arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_WRITE_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY);
+      } else {
+        msc_update_error();
+        return 0;
+      }
+    } else if (msc_update_state == MSC_UPDATE_RUNNING) {
+      if (msc_update_entry && msc_update_entry->file_size && msc_update_bytes_written < msc_update_entry->file_size
+          && (msc_update_bytes_written + bufsize) >= msc_update_entry->file_size) {
+        bufsize = msc_update_entry->file_size - msc_update_bytes_written;
+      }
+      if (msc_update_write(msc_ota_partition, ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset, buffer, bufsize) == ESP_OK) {
+        log_v("UPDATE_WRITE: %u %u", ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset, bufsize);
+        msc_update_bytes_written = ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset + bufsize;
+        p.write.offset = ((lba - msc_update_start_sector) * DISK_SECTOR_SIZE) + offset;
+        p.write.size = bufsize;
+        arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_WRITE_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY);
+        if (msc_update_entry && msc_update_entry->file_size && msc_update_bytes_written >= msc_update_entry->file_size) {
+          msc_update_end();
+        }
+      } else {
+        msc_update_error();
+        return 0;
+      }
+    }
+  }
+  return bufsize;
+}
+
+static int32_t msc_read(uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize) {
+  //log_d("lba: %u, offset: %u, bufsize: %u", lba, offset, bufsize);
+  if (lba < fw_start_sector) {
+    memcpy(buffer, msc_ram_disk + (lba * DISK_SECTOR_SIZE) + offset, bufsize);
+  } else if (msc_run_partition && lba < fw_end_sector) {
+    //read the currently running firmware
+    if (esp_partition_read(msc_run_partition, ((lba - fw_start_sector) * DISK_SECTOR_SIZE) + offset, buffer, bufsize) != ESP_OK) {
+      return 0;
+    }
+  } else {
+    memset(buffer, 0, bufsize);
+  }
+  return bufsize;
+}
+
+static bool msc_start_stop(uint8_t power_condition, bool start, bool load_eject) {
+  //log_d("power: %u, start: %u, eject: %u", power_condition, start, load_eject);
+  arduino_firmware_msc_event_data_t p;
+  p.power.power_condition = power_condition;
+  p.power.start = start;
+  p.power.load_eject = load_eject;
+  arduino_usb_event_post(ARDUINO_FIRMWARE_MSC_EVENTS, ARDUINO_FIRMWARE_MSC_POWER_EVENT, &p, sizeof(arduino_firmware_msc_event_data_t), portMAX_DELAY);
+  return true;
+}
+
+static volatile TaskHandle_t msc_task_handle = NULL;
+static void msc_task(void *pvParameters) {
+  for (;;) {
+    if (msc_update_state == MSC_UPDATE_END) {
+      delay(100);
+      esp_restart();
+    }
+    delay(100);
+  }
+  msc_task_handle = NULL;
+  vTaskDelete(NULL);
+}
+
+FirmwareMSC::FirmwareMSC() : msc() {}
+
+FirmwareMSC::~FirmwareMSC() {
+  end();
+}
+
+bool FirmwareMSC::begin() {
+  if (msc_ram_disk) {
+    return true;
+  }
+
+  if (!msc_update_setup_disk(USB_FW_MSC_VOLUME_NAME, USB_FW_MSC_SERIAL_NUMBER)) {
+    return false;
+  }
+
+  if (!msc_task_handle) {
+    xTaskCreateUniversal(msc_task, "msc_disk", 1024, NULL, 2, (TaskHandle_t *)&msc_task_handle, 0);
+    if (!msc_task_handle) {
+      msc_update_delete_disk();
+      return false;
+    }
+  }
+
+  msc.vendorID(USB_FW_MSC_VENDOR_ID);
+  msc.productID(USB_FW_MSC_PRODUCT_ID);
+  msc.productRevision(USB_FW_MSC_PRODUCT_REVISION);
+  msc.onStartStop(msc_start_stop);
+  msc.onRead(msc_read);
+  msc.onWrite(msc_write);
+  msc.mediaPresent(true);
+  msc.begin(msc_boot->fat12_sector_num, DISK_SECTOR_SIZE);
+  return true;
+}
+
+void FirmwareMSC::end() {
+  msc.end();
+  if (msc_task_handle) {
+    vTaskDelete(msc_task_handle);
+    msc_task_handle = NULL;
+  }
+  msc_update_delete_disk();
+}
+
+void FirmwareMSC::onEvent(esp_event_handler_t callback) {
+  onEvent(ARDUINO_FIRMWARE_MSC_ANY_EVENT, callback);
+}
+void FirmwareMSC::onEvent(arduino_firmware_msc_event_t event, esp_event_handler_t callback) {
+  arduino_usb_event_handler_register_with(ARDUINO_FIRMWARE_MSC_EVENTS, event, callback, this);
+}
+
+#if ARDUINO_USB_MSC_ON_BOOT
+FirmwareMSC MSC_Update;
+#endif
+
+#endif /* CONFIG_USB_MSC_ENABLED */
diff --git a/cores/esp32/FirmwareMSC.h b/cores/esp32/FirmwareMSC.h
new file mode 100644
index 00000000000..3eaa184bcd6
--- /dev/null
+++ b/cores/esp32/FirmwareMSC.h
@@ -0,0 +1,70 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <stdbool.h>
+#include "USBMSC.h"
+
+#if CONFIG_TINYUSB_MSC_ENABLED
+
+#include "esp_event.h"
+
+ESP_EVENT_DECLARE_BASE(ARDUINO_FIRMWARE_MSC_EVENTS);
+
+typedef enum {
+  ARDUINO_FIRMWARE_MSC_ANY_EVENT = ESP_EVENT_ANY_ID,
+  ARDUINO_FIRMWARE_MSC_START_EVENT = 0,
+  ARDUINO_FIRMWARE_MSC_WRITE_EVENT,
+  ARDUINO_FIRMWARE_MSC_END_EVENT,
+  ARDUINO_FIRMWARE_MSC_ERROR_EVENT,
+  ARDUINO_FIRMWARE_MSC_POWER_EVENT,
+  ARDUINO_FIRMWARE_MSC_MAX_EVENT,
+} arduino_firmware_msc_event_t;
+
+typedef union {
+  struct {
+    size_t offset;
+    size_t size;
+  } write;
+  struct {
+    uint8_t power_condition;
+    bool start;
+    bool load_eject;
+  } power;
+  struct {
+    size_t size;
+  } end;
+  struct {
+    size_t size;
+  } error;
+} arduino_firmware_msc_event_data_t;
+
+class FirmwareMSC {
+private:
+  USBMSC msc;
+
+public:
+  FirmwareMSC();
+  ~FirmwareMSC();
+  bool begin();
+  void end();
+  void onEvent(esp_event_handler_t callback);
+  void onEvent(arduino_firmware_msc_event_t event, esp_event_handler_t callback);
+};
+
+#if ARDUINO_USB_MSC_ON_BOOT
+extern FirmwareMSC MSC_Update;
+#endif
+
+#endif /* CONFIG_TINYUSB_MSC_ENABLED */
diff --git a/cores/esp32/FunctionalInterrupt.cpp b/cores/esp32/FunctionalInterrupt.cpp
index d2e6dfd4236..bc3fdf167c4 100644
--- a/cores/esp32/FunctionalInterrupt.cpp
+++ b/cores/esp32/FunctionalInterrupt.cpp
@@ -9,36 +9,26 @@
 #include "Arduino.h"
 
 typedef void (*voidFuncPtr)(void);
-typedef void (*voidFuncPtrArg)(void*);
+typedef void (*voidFuncPtrArg)(void *);
 
-extern "C"
-{
-	extern void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtrArg userFunc, void * arg, int intr_type, bool functional);
+extern "C" {
+extern void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtrArg userFunc, void *arg, int intr_type, bool functional);
 }
 
-void IRAM_ATTR interruptFunctional(void* arg)
-{
-    InterruptArgStructure* localArg = (InterruptArgStructure*)arg;
-	if (localArg->interruptFunction)
-	{
-	  localArg->interruptFunction();
-	}
+void ARDUINO_ISR_ATTR interruptFunctional(void *arg) {
+  InterruptArgStructure *localArg = (InterruptArgStructure *)arg;
+  if (localArg->interruptFunction) {
+    localArg->interruptFunction();
+  }
 }
 
-void attachInterrupt(uint8_t pin, std::function<void(void)> intRoutine, int mode)
-{
-	// use the local interrupt routine which takes the ArgStructure as argument
-	__attachInterruptFunctionalArg (pin, (voidFuncPtrArg)interruptFunctional, new InterruptArgStructure{intRoutine}, mode, true);
+void attachInterrupt(uint8_t pin, std::function<void(void)> intRoutine, int mode) {
+  // use the local interrupt routine which takes the ArgStructure as argument
+  __attachInterruptFunctionalArg(pin, (voidFuncPtrArg)interruptFunctional, new InterruptArgStructure{intRoutine}, mode, true);
 }
 
-extern "C"
-{
-   void cleanupFunctional(void* arg)
-   {
-	 delete (InterruptArgStructure*)arg;
-   }
+extern "C" {
+void cleanupFunctional(void *arg) {
+  delete (InterruptArgStructure *)arg;
+}
 }
-
-
-
-
diff --git a/cores/esp32/FunctionalInterrupt.h b/cores/esp32/FunctionalInterrupt.h
index b5e3181f986..4b31d328663 100644
--- a/cores/esp32/FunctionalInterrupt.h
+++ b/cores/esp32/FunctionalInterrupt.h
@@ -9,12 +9,14 @@
 #define CORE_CORE_FUNCTIONALINTERRUPT_H_
 
 #include <functional>
+#include <stdint.h>
 
 struct InterruptArgStructure {
-	std::function<void(void)> interruptFunction;
+  std::function<void(void)> interruptFunction;
 };
 
-void attachInterrupt(uint8_t pin, std::function<void(void)> intRoutine, int mode);
-
+// The extra set of parentheses here prevents macros defined
+// in io_pin_remap.h from applying to this declaration.
+void(attachInterrupt)(uint8_t pin, std::function<void(void)> intRoutine, int mode);
 
 #endif /* CORE_CORE_FUNCTIONALINTERRUPT_H_ */
diff --git a/cores/esp32/HEXBuilder.cpp b/cores/esp32/HEXBuilder.cpp
new file mode 100644
index 00000000000..6154f58b384
--- /dev/null
+++ b/cores/esp32/HEXBuilder.cpp
@@ -0,0 +1,76 @@
+/*
+  Copyright (c) 2015 Hristo Gochkov. All rights reserved.
+  This file is part of the esp32 core for Arduino environment.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <Arduino.h>
+#include <HEXBuilder.h>
+
+static uint8_t hex_char_to_byte(uint8_t c) {
+  return (c >= 'a' && c <= 'f')   ? (c - ((uint8_t)'a' - 0xa))
+         : (c >= 'A' && c <= 'F') ? (c - ((uint8_t)'A' - 0xA))
+         : (c >= '0' && c <= '9') ? (c - (uint8_t)'0')
+                                  : 0x10;  // unknown char is 16
+}
+
+size_t HEXBuilder::hex2bytes(unsigned char *out, size_t maxlen, String &in) {
+  return hex2bytes(out, maxlen, in.c_str());
+}
+
+size_t HEXBuilder::hex2bytes(unsigned char *out, size_t maxlen, const char *in) {
+  size_t len = 0;
+  for (; *in; in++) {
+    uint8_t c = hex_char_to_byte(*in);
+    // Silently skip anything unknown.
+    if (c > 15) {
+      continue;
+    }
+
+    if (len & 1) {
+      if (len / 2 < maxlen) {
+        out[len / 2] |= c;
+      }
+    } else {
+      if (len / 2 < maxlen) {
+        out[len / 2] = c << 4;
+      }
+    }
+    len++;
+  }
+  return (len + 1) / 2;
+}
+
+size_t HEXBuilder::bytes2hex(char *out, size_t maxlen, const unsigned char *in, size_t len) {
+  for (size_t i = 0; i < len; i++) {
+    if (i * 2 + 1 < maxlen) {
+      sprintf(out + (i * 2), "%02x", in[i]);
+    }
+  }
+  return len * 2 + 1;
+}
+
+String HEXBuilder::bytes2hex(const unsigned char *in, size_t len) {
+  size_t maxlen = len * 2 + 1;
+  char *out = (char *)malloc(maxlen);
+  if (!out) {
+    return String();
+  }
+  bytes2hex(out, maxlen, in, len);
+  String ret = String(out);
+  free(out);
+  return ret;
+}
diff --git a/cores/esp32/HEXBuilder.h b/cores/esp32/HEXBuilder.h
new file mode 100644
index 00000000000..0c35fbc1acc
--- /dev/null
+++ b/cores/esp32/HEXBuilder.h
@@ -0,0 +1,34 @@
+/*
+  Copyright (c) 2015 Hristo Gochkov. All rights reserved.
+  This file is part of the esp32 core for Arduino environment.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef HEXBuilder_h
+#define HEXBuilder_h
+
+#include <WString.h>
+#include <Stream.h>
+
+class HEXBuilder {
+public:
+  static size_t hex2bytes(unsigned char *out, size_t maxlen, String &in);
+  static size_t hex2bytes(unsigned char *out, size_t maxlen, const char *in);
+
+  static String bytes2hex(const unsigned char *in, size_t len);
+  static size_t bytes2hex(char *out, size_t maxlen, const unsigned char *in, size_t len);
+};
+#endif
diff --git a/cores/esp32/HWCDC.cpp b/cores/esp32/HWCDC.cpp
new file mode 100644
index 00000000000..062317d9f53
--- /dev/null
+++ b/cores/esp32/HWCDC.cpp
@@ -0,0 +1,614 @@
+// Copyright 2015-2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include "USB.h"
+#if SOC_USB_SERIAL_JTAG_SUPPORTED
+
+#include "esp32-hal.h"
+#include "esp32-hal-periman.h"
+#include "HWCDC.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "freertos/queue.h"
+#include "freertos/ringbuf.h"
+#include "esp_intr_alloc.h"
+#include "soc/periph_defs.h"
+#include "soc/io_mux_reg.h"
+#include "soc/usb_serial_jtag_struct.h"
+#pragma GCC diagnostic ignored "-Wvolatile"
+#include "hal/usb_serial_jtag_ll.h"
+#pragma GCC diagnostic warning "-Wvolatile"
+#include "rom/ets_sys.h"
+
+ESP_EVENT_DEFINE_BASE(ARDUINO_HW_CDC_EVENTS);
+
+static RingbufHandle_t tx_ring_buf = NULL;
+static QueueHandle_t rx_queue = NULL;
+static uint8_t rx_data_buf[64] = {0};
+static intr_handle_t intr_handle = NULL;
+static SemaphoreHandle_t tx_lock = NULL;
+static volatile bool connected = false;
+
+// SOF in ISR causes problems for uploading firmware
+//static volatile unsigned long lastSOF_ms;
+//static volatile uint8_t SOF_TIMEOUT;
+
+// timeout has no effect when USB CDC is unplugged
+static uint32_t tx_timeout_ms = 100;
+
+static esp_event_loop_handle_t arduino_hw_cdc_event_loop_handle = NULL;
+
+static esp_err_t
+  arduino_hw_cdc_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, BaseType_t *task_unblocked) {
+  if (arduino_hw_cdc_event_loop_handle == NULL) {
+    return ESP_FAIL;
+  }
+  return esp_event_isr_post_to(arduino_hw_cdc_event_loop_handle, event_base, event_id, event_data, event_data_size, task_unblocked);
+}
+
+static esp_err_t
+  arduino_hw_cdc_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg) {
+  if (!arduino_hw_cdc_event_loop_handle) {
+    esp_event_loop_args_t event_task_args = {
+      .queue_size = 5, .task_name = "arduino_hw_cdc_events", .task_priority = 5, .task_stack_size = 2048, .task_core_id = tskNO_AFFINITY
+    };
+    if (esp_event_loop_create(&event_task_args, &arduino_hw_cdc_event_loop_handle) != ESP_OK) {
+      log_e("esp_event_loop_create failed");
+    }
+  }
+  if (arduino_hw_cdc_event_loop_handle == NULL) {
+    return ESP_FAIL;
+  }
+  return esp_event_handler_register_with(arduino_hw_cdc_event_loop_handle, event_base, event_id, event_handler, event_handler_arg);
+}
+
+static void hw_cdc_isr_handler(void *arg) {
+  portBASE_TYPE xTaskWoken = 0;
+  uint32_t usbjtag_intr_status = 0;
+  arduino_hw_cdc_event_data_t event = {0};
+  usbjtag_intr_status = usb_serial_jtag_ll_get_intsts_mask();
+
+  if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY) {
+    // Interrupt tells us the host picked up the data we sent.
+    if (!HWCDC::isPlugged()) {
+      connected = false;
+      usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+      // USB is unplugged, nothing to be done here
+      return;
+    } else {
+      connected = true;
+    }
+    if (tx_ring_buf != NULL && usb_serial_jtag_ll_txfifo_writable() == 1) {
+      // We disable the interrupt here so that the interrupt won't be triggered if there is no data to send.
+      usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+      size_t queued_size = 0;
+      uint8_t *queued_buff = (uint8_t *)xRingbufferReceiveUpToFromISR(tx_ring_buf, &queued_size, 64);
+      // If the hardware fifo is available, write in it. Otherwise, do nothing.
+      if (queued_buff != NULL) {  //Although tx_queued_bytes may be larger than 0. We may have interrupt before xRingbufferSend() was called.
+        //Copy the queued buffer into the TX FIFO
+        usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+        usb_serial_jtag_ll_write_txfifo(queued_buff, queued_size);
+        usb_serial_jtag_ll_txfifo_flush();
+        vRingbufferReturnItemFromISR(tx_ring_buf, queued_buff, &xTaskWoken);
+        if (connected) {
+          usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+        }
+        //send event?
+        //ets_printf("TX:%u\n", queued_size);
+        event.tx.len = queued_size;
+        arduino_hw_cdc_event_post(ARDUINO_HW_CDC_EVENTS, ARDUINO_HW_CDC_TX_EVENT, &event, sizeof(arduino_hw_cdc_event_data_t), &xTaskWoken);
+      }
+    } else {
+      usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+    }
+  }
+
+  if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT) {
+    // read rx buffer(max length is 64), and send available data to ringbuffer.
+    // Ensure the rx buffer size is larger than RX_MAX_SIZE.
+    usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
+    uint32_t rx_fifo_len = usb_serial_jtag_ll_read_rxfifo(rx_data_buf, 64);
+    uint32_t i = 0;
+    for (i = 0; i < rx_fifo_len; i++) {
+      if (rx_queue == NULL || !xQueueSendFromISR(rx_queue, rx_data_buf + i, &xTaskWoken)) {
+        break;
+      }
+    }
+    event.rx.len = i;
+    arduino_hw_cdc_event_post(ARDUINO_HW_CDC_EVENTS, ARDUINO_HW_CDC_RX_EVENT, &event, sizeof(arduino_hw_cdc_event_data_t), &xTaskWoken);
+    connected = true;
+  }
+
+  if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_BUS_RESET) {
+    usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_BUS_RESET);
+    arduino_hw_cdc_event_post(ARDUINO_HW_CDC_EVENTS, ARDUINO_HW_CDC_BUS_RESET_EVENT, &event, sizeof(arduino_hw_cdc_event_data_t), &xTaskWoken);
+    connected = false;
+  }
+
+  // SOF ISR is causing esptool to be unable to upload firmware to the board
+  // if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_SOF) {
+  //   usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SOF);
+  //   lastSOF_ms = millis();
+  // }
+
+  if (xTaskWoken == pdTRUE) {
+    portYIELD_FROM_ISR();
+  }
+}
+
+// Moved to header file as inline function. Kept just as future reference.
+//inline bool HWCDC::isPlugged(void) {
+// SOF ISR is causing esptool to be unable to upload firmware to the board
+// Timer test for SOF seems to work when uploading firmware
+//  return usb_serial_jtag_is_connected();//(lastSOF_ms + SOF_TIMEOUT) >= millis();
+//}
+
+bool HWCDC::isCDC_Connected() {
+  static bool running = false;
+
+  // USB may be unplugged
+  if (!isPlugged()) {
+    connected = false;
+    running = false;
+    // SOF in ISR causes problems for uploading firmware
+    //SOF_TIMEOUT = 5;  // SOF timeout when unplugged
+    return false;
+  }
+  //else {
+  //  SOF_TIMEOUT = 50;  // SOF timeout when plugged
+  //}
+
+  if (connected) {
+    running = false;
+    return true;
+  }
+
+  if (running == false && !connected) {  // enables it only once!
+    usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+  }
+
+  // this will feed CDC TX FIFO to trigger IN_EMPTY
+  usb_serial_jtag_ll_txfifo_flush();
+  running = true;
+  return false;
+}
+
+static void flushTXBuffer(const uint8_t *buffer, size_t size) {
+  if (!tx_ring_buf) {
+    return;
+  }
+  UBaseType_t uxItemsWaiting = 0;
+  vRingbufferGetInfo(tx_ring_buf, NULL, NULL, NULL, NULL, &uxItemsWaiting);
+  size_t freeSpace = xRingbufferGetCurFreeSize(tx_ring_buf);
+  size_t ringbufferLength = freeSpace + uxItemsWaiting;
+
+  if (buffer == NULL) {
+    // just flush the whole ring buffer and exit - used by HWCDC::flush()
+    size_t queued_size = 0;
+    uint8_t *queued_buff = (uint8_t *)xRingbufferReceiveUpTo(tx_ring_buf, &queued_size, 0, ringbufferLength);
+    if (queued_size && queued_buff != NULL) {
+      vRingbufferReturnItem(tx_ring_buf, (void *)queued_buff);
+    }
+    return;
+  }
+  if (size == 0) {
+    return;  // nothing to do
+  }
+  if (freeSpace >= size) {
+    // there is enough space, just add the data to the ring buffer
+    if (xRingbufferSend(tx_ring_buf, (void *)buffer, size, 0) != pdTRUE) {
+      return;
+    }
+  } else {
+    // how many byte should be flushed to make space for the new data
+    size_t to_flush = size - freeSpace;
+    if (to_flush > ringbufferLength) {
+      to_flush = ringbufferLength;
+    }
+    size_t queued_size = 0;
+    uint8_t *queued_buff = (uint8_t *)xRingbufferReceiveUpTo(tx_ring_buf, &queued_size, 0, to_flush);
+    if (queued_size && queued_buff != NULL) {
+      vRingbufferReturnItem(tx_ring_buf, (void *)queued_buff);
+    }
+    // now add the new data that fits into the ring buffer
+    uint8_t *bptr = (uint8_t *)buffer;
+    if (size >= ringbufferLength) {
+      size = ringbufferLength;
+      bptr = (uint8_t *)buffer + (size - ringbufferLength);
+    }
+    if (xRingbufferSend(tx_ring_buf, (void *)bptr, size, 0) != pdTRUE) {
+      return;
+    }
+  }
+  // flushes CDC FIFO
+  usb_serial_jtag_ll_txfifo_flush();
+}
+
+static void ARDUINO_ISR_ATTR cdc0_write_char(char c) {
+  if (tx_ring_buf == NULL) {
+    return;
+  }
+  if (!HWCDC::isConnected()) {
+    // just pop/push RingBuffer and apply FIFO policy
+    flushTXBuffer((const uint8_t *)&c, 1);
+    return;
+  }
+  if (xPortInIsrContext()) {
+    xRingbufferSendFromISR(tx_ring_buf, (void *)(&c), 1, NULL);
+  } else {
+    xRingbufferSend(tx_ring_buf, (void *)(&c), 1, tx_timeout_ms / portTICK_PERIOD_MS);
+  }
+  usb_serial_jtag_ll_txfifo_flush();
+  usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+}
+
+HWCDC::HWCDC() {
+  perimanSetBusDeinit(ESP32_BUS_TYPE_USB_DM, HWCDC::deinit);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_USB_DP, HWCDC::deinit);
+  // SOF in ISR causes problems for uploading firmware
+  //  lastSOF_ms = 0;
+  //  SOF_TIMEOUT = 5;
+}
+
+HWCDC::~HWCDC() {
+  end();
+}
+
+// It should return <true> just when USB is plugged and CDC is connected.
+HWCDC::operator bool() const {
+  return HWCDC::isCDC_Connected();
+}
+
+void HWCDC::onEvent(esp_event_handler_t callback) {
+  onEvent(ARDUINO_HW_CDC_ANY_EVENT, callback);
+}
+
+void HWCDC::onEvent(arduino_hw_cdc_event_t event, esp_event_handler_t callback) {
+  arduino_hw_cdc_event_handler_register_with(ARDUINO_HW_CDC_EVENTS, event, callback, this);
+}
+
+bool HWCDC::deinit(void *busptr) {
+  // avoid any recursion issue with Peripheral Manager perimanSetPinBus() call
+  static bool running = false;
+  if (running) {
+    return true;
+  }
+  running = true;
+  // Setting USB D+ D- pins
+  bool retCode = true;
+  retCode &= perimanClearPinBus(USB_INT_PHY0_DM_GPIO_NUM);
+  retCode &= perimanClearPinBus(USB_INT_PHY0_DP_GPIO_NUM);
+  if (retCode) {
+    // Force the host to re-enumerate (BUS_RESET)
+    pinMode(USB_INT_PHY0_DM_GPIO_NUM, OUTPUT_OPEN_DRAIN);
+    pinMode(USB_INT_PHY0_DP_GPIO_NUM, OUTPUT_OPEN_DRAIN);
+    digitalWrite(USB_INT_PHY0_DM_GPIO_NUM, LOW);
+    digitalWrite(USB_INT_PHY0_DP_GPIO_NUM, LOW);
+  }
+  // release the flag
+  running = false;
+  return retCode;
+}
+
+void HWCDC::begin(unsigned long baud) {
+  if (tx_lock == NULL) {
+    tx_lock = xSemaphoreCreateMutex();
+  }
+  //RX Buffer default has 256 bytes if not preset
+  if (rx_queue == NULL) {
+    if (!setRxBufferSize(256)) {
+      log_e("HW CDC RX Buffer error");
+    }
+  }
+  //TX Buffer default has 256 bytes if not preset
+  if (tx_ring_buf == NULL) {
+    if (!setTxBufferSize(256)) {
+      log_e("HW CDC TX Buffer error");
+    }
+  }
+
+  // the HW Serial pins needs to be first deinited in order to allow `if(Serial)` to work :-(
+  // But this is also causing terminal to hang, so they are disabled
+  // deinit(NULL);
+  // delay(10);  // USB Host has to enumerate it again
+
+  // Peripheral Manager setting for USB D+ D- pins
+  uint8_t pin = USB_INT_PHY0_DM_GPIO_NUM;
+  if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_USB_DM, (void *)this, -1, -1)) {
+    goto err;
+  }
+  pin = USB_INT_PHY0_DP_GPIO_NUM;
+  if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_USB_DP, (void *)this, -1, -1)) {
+    goto err;
+  }
+
+  // Configure PHY
+  // USB_Serial_JTAG use internal PHY
+  USB_SERIAL_JTAG.conf0.phy_sel = 0;
+  // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
+  USB_SERIAL_JTAG.conf0.pad_pull_override = 0;
+  // Enable USB D+ pullup
+  USB_SERIAL_JTAG.conf0.dp_pullup = 1;
+  // Enable USB pad function
+  USB_SERIAL_JTAG.conf0.usb_pad_enable = 1;
+  usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_LL_INTR_MASK);
+  usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY | USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT | USB_SERIAL_JTAG_INTR_BUS_RESET);
+  // SOF ISR is causing esptool to be unable to upload firmware to the board
+  // usb_serial_jtag_ll_ena_intr_mask(
+  //   USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY | USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT | USB_SERIAL_JTAG_INTR_BUS_RESET | USB_SERIAL_JTAG_INTR_SOF
+  // );
+  if (!intr_handle && esp_intr_alloc(ETS_USB_SERIAL_JTAG_INTR_SOURCE, 0, hw_cdc_isr_handler, NULL, &intr_handle) != ESP_OK) {
+    isr_log_e("HW USB CDC failed to init interrupts");
+    end();
+    return;
+  }
+  return;
+
+err:
+  log_e("Serial JTAG Pin %u can't be set into Peripheral Manager.", pin);
+  end();
+}
+
+void HWCDC::end() {
+  //Disable/clear/free tx/rx interrupt.
+  usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_LL_INTR_MASK);
+  usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_LL_INTR_MASK);
+  esp_intr_free(intr_handle);
+  intr_handle = NULL;
+  if (tx_lock != NULL) {
+    vSemaphoreDelete(tx_lock);
+    tx_lock = NULL;
+  }
+  setRxBufferSize(0);
+  setTxBufferSize(0);
+  if (arduino_hw_cdc_event_loop_handle) {
+    esp_event_loop_delete(arduino_hw_cdc_event_loop_handle);
+    arduino_hw_cdc_event_loop_handle = NULL;
+  }
+  HWCDC::deinit(this);
+  setDebugOutput(false);
+  connected = false;
+}
+
+void HWCDC::setTxTimeoutMs(uint32_t timeout) {
+  tx_timeout_ms = timeout;
+}
+
+/*
+ * WRITING
+*/
+
+size_t HWCDC::setTxBufferSize(size_t tx_queue_len) {
+  if (tx_ring_buf) {
+    vRingbufferDelete(tx_ring_buf);
+    tx_ring_buf = NULL;
+  }
+  if (!tx_queue_len) {
+    return 0;
+  }
+  tx_ring_buf = xRingbufferCreate(tx_queue_len, RINGBUF_TYPE_BYTEBUF);
+  if (!tx_ring_buf) {
+    return 0;
+  }
+  return tx_queue_len;
+}
+
+int HWCDC::availableForWrite(void) {
+  if (tx_ring_buf == NULL || tx_lock == NULL) {
+    return 0;
+  }
+  if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) {
+    return 0;
+  }
+  size_t a = xRingbufferGetCurFreeSize(tx_ring_buf);
+  xSemaphoreGive(tx_lock);
+  return a;
+}
+
+size_t HWCDC::write(const uint8_t *buffer, size_t size) {
+  if (buffer == NULL || size == 0 || tx_ring_buf == NULL || tx_lock == NULL) {
+    return 0;
+  }
+  if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) {
+    return 0;
+  }
+  if (!isCDC_Connected()) {
+    // just pop/push RingBuffer and apply FIFO policy
+    flushTXBuffer(buffer, size);
+  } else {
+    size_t space = xRingbufferGetCurFreeSize(tx_ring_buf);
+    size_t to_send = size, so_far = 0;
+
+    if (space > size) {
+      space = size;
+    }
+    // Non-Blocking method, Sending data to ringbuffer, and handle the data in ISR.
+    if (space > 0 && xRingbufferSend(tx_ring_buf, (void *)(buffer), space, 0) != pdTRUE) {
+      size = 0;
+    } else {
+      to_send -= space;
+      so_far += space;
+      // Now trigger the ISR to read data from the ring buffer.
+      usb_serial_jtag_ll_txfifo_flush();
+      if (connected) {
+        usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+      }
+      // tracks CDC transmission progress to avoid hanging if CDC is unplugged while still sending data
+      size_t last_toSend = to_send;
+      uint32_t tries = tx_timeout_ms;  // waits 1ms per sending data attempt, in case CDC is unplugged
+      while (connected && to_send) {
+        space = xRingbufferGetCurFreeSize(tx_ring_buf);
+        if (space > to_send) {
+          space = to_send;
+        }
+        // Blocking method, Sending data to ringbuffer, and handle the data in ISR.
+        if (xRingbufferSend(tx_ring_buf, (void *)(buffer + so_far), space, tx_timeout_ms / portTICK_PERIOD_MS) != pdTRUE) {
+          size = so_far;
+          log_w("write failed due to ring buffer full - timeout");
+          break;
+        }
+        so_far += space;
+        to_send -= space;
+        // Now trigger the ISR to read data from the ring buffer.
+        usb_serial_jtag_ll_txfifo_flush();
+        if (connected) {
+          usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+        }
+        if (last_toSend == to_send) {
+          // no progress in sending data... USB CDC is probably unplugged
+          tries--;
+          delay(1);
+        } else {
+          last_toSend = to_send;
+          tries = tx_timeout_ms;  // reset the timeout
+        }
+        if (tries == 0) {  // CDC isn't connected anymore...
+          size = so_far;
+          log_w("write failed due to waiting USB Host - timeout");
+          connected = false;
+        }
+      }
+    }
+    // CDC was disconnected while sending data ==> flush the TX buffer keeping the last data
+    if (to_send && !usb_serial_jtag_ll_txfifo_writable()) {
+      connected = false;
+      flushTXBuffer(buffer + so_far, to_send);
+    }
+  }
+  xSemaphoreGive(tx_lock);
+  return size;
+}
+
+size_t HWCDC::write(uint8_t c) {
+  return write(&c, 1);
+}
+
+void HWCDC::flush(void) {
+  if (tx_ring_buf == NULL || tx_lock == NULL) {
+    return;
+  }
+  if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) {
+    return;
+  }
+  if (!isCDC_Connected()) {
+    flushTXBuffer(NULL, 0);
+  } else {
+    UBaseType_t uxItemsWaiting = 0;
+    vRingbufferGetInfo(tx_ring_buf, NULL, NULL, NULL, NULL, &uxItemsWaiting);
+    if (uxItemsWaiting) {
+      // Now trigger the ISR to read data from the ring buffer.
+      usb_serial_jtag_ll_txfifo_flush();
+      if (connected) {
+        usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+      }
+    }
+    uint32_t tries = tx_timeout_ms;  // waits 1ms per ISR sending data attempt, in case CDC is unplugged
+    while (connected && tries && uxItemsWaiting) {
+      delay(1);
+      UBaseType_t lastUxItemsWaiting = uxItemsWaiting;
+      vRingbufferGetInfo(tx_ring_buf, NULL, NULL, NULL, NULL, &uxItemsWaiting);
+      if (lastUxItemsWaiting == uxItemsWaiting) {
+        tries--;
+      }
+      if (connected) {
+        usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY);
+      }
+    }
+    if (tries == 0) {  // CDC isn't connected anymore...
+      connected = false;
+      flushTXBuffer(NULL, 0);  // flushes all TX Buffer
+    }
+  }
+  xSemaphoreGive(tx_lock);
+}
+
+/*
+ * READING
+*/
+
+size_t HWCDC::setRxBufferSize(size_t rx_queue_len) {
+  if (rx_queue) {
+    vQueueDelete(rx_queue);
+    rx_queue = NULL;
+  }
+  if (!rx_queue_len) {
+    return 0;
+  }
+  rx_queue = xQueueCreate(rx_queue_len, sizeof(uint8_t));
+  if (!rx_queue) {
+    return 0;
+  }
+  return rx_queue_len;
+}
+
+int HWCDC::available(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  return uxQueueMessagesWaiting(rx_queue);
+}
+
+int HWCDC::peek(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c;
+  if (xQueuePeek(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+int HWCDC::read(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  if (xQueueReceive(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+size_t HWCDC::read(uint8_t *buffer, size_t size) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  size_t count = 0;
+  while (count < size && xQueueReceive(rx_queue, &c, 0)) {
+    buffer[count++] = c;
+  }
+  return count;
+}
+
+/*
+ * DEBUG
+*/
+
+void HWCDC::setDebugOutput(bool en) {
+  if (en) {
+    uartSetDebug(NULL);
+    ets_install_putc2((void (*)(char)) & cdc0_write_char);
+  } else {
+    ets_install_putc2(NULL);
+  }
+  ets_install_putc1(NULL);  // closes UART log output
+}
+
+#if ARDUINO_USB_MODE && ARDUINO_USB_CDC_ON_BOOT  // Hardware JTAG CDC selected
+// USBSerial is always available to be used
+HWCDC HWCDCSerial;
+#endif
+
+#endif /* SOC_USB_SERIAL_JTAG_SUPPORTED */
diff --git a/cores/esp32/HWCDC.h b/cores/esp32/HWCDC.h
new file mode 100644
index 00000000000..29caae34062
--- /dev/null
+++ b/cores/esp32/HWCDC.h
@@ -0,0 +1,118 @@
+// Copyright 2015-2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include "sdkconfig.h"
+#include "soc/soc_caps.h"
+
+#if SOC_USB_SERIAL_JTAG_SUPPORTED
+
+#include <inttypes.h>
+#include "esp_event.h"
+#include "Stream.h"
+#include "driver/usb_serial_jtag.h"
+
+ESP_EVENT_DECLARE_BASE(ARDUINO_HW_CDC_EVENTS);
+
+typedef enum {
+  ARDUINO_HW_CDC_ANY_EVENT = ESP_EVENT_ANY_ID,
+  ARDUINO_HW_CDC_CONNECTED_EVENT = 0,
+  ARDUINO_HW_CDC_BUS_RESET_EVENT,
+  ARDUINO_HW_CDC_RX_EVENT,
+  ARDUINO_HW_CDC_TX_EVENT,
+  ARDUINO_HW_CDC_MAX_EVENT,
+} arduino_hw_cdc_event_t;
+
+typedef union {
+  struct {
+    size_t len;
+  } rx;
+  struct {
+    size_t len;
+  } tx;
+} arduino_hw_cdc_event_data_t;
+
+class HWCDC : public Stream {
+private:
+  static bool deinit(void *busptr);
+  static bool isCDC_Connected();
+
+public:
+  HWCDC();
+  ~HWCDC();
+
+  void onEvent(esp_event_handler_t callback);
+  void onEvent(arduino_hw_cdc_event_t event, esp_event_handler_t callback);
+
+  size_t setRxBufferSize(size_t);
+  size_t setTxBufferSize(size_t);
+  void setTxTimeoutMs(uint32_t timeout);
+  void begin(unsigned long baud = 0);
+  void end();
+
+  int available(void);
+  int availableForWrite(void);
+  int peek(void);
+  int read(void);
+  size_t read(uint8_t *buffer, size_t size);
+  size_t write(uint8_t);
+  size_t write(const uint8_t *buffer, size_t size);
+  void flush(void);
+
+  inline static bool isPlugged(void) {
+    // SOF ISR is causing esptool to be unable to upload firmware to the board
+    // Using IDF 5.1 helper function because it is based on Timer check instead of ISR
+    return usb_serial_jtag_is_connected();
+  }
+
+  inline static bool isConnected(void) {
+    return isCDC_Connected();
+  }
+
+  inline size_t read(char *buffer, size_t size) {
+    return read((uint8_t *)buffer, size);
+  }
+  inline size_t write(const char *buffer, size_t size) {
+    return write((uint8_t *)buffer, size);
+  }
+  inline size_t write(const char *s) {
+    return write((uint8_t *)s, strlen(s));
+  }
+  inline size_t write(unsigned long n) {
+    return write((uint8_t)n);
+  }
+  inline size_t write(long n) {
+    return write((uint8_t)n);
+  }
+  inline size_t write(unsigned int n) {
+    return write((uint8_t)n);
+  }
+  inline size_t write(int n) {
+    return write((uint8_t)n);
+  }
+  operator bool() const;
+  void setDebugOutput(bool);
+  uint32_t baudRate() {
+    return 115200;
+  }
+};
+#if ARDUINO_USB_MODE && ARDUINO_USB_CDC_ON_BOOT  // Hardware JTAG CDC selected
+#ifndef HWCDC_SERIAL_IS_DEFINED
+#define HWCDC_SERIAL_IS_DEFINED 1
+#endif
+// HWCDCSerial is always available to be used
+extern HWCDC HWCDCSerial;
+#endif
+
+#endif /* SOC_USB_SERIAL_JTAG_SUPPORTED */
diff --git a/cores/esp32/HardwareI2C.h b/cores/esp32/HardwareI2C.h
new file mode 100644
index 00000000000..65b7e2036b2
--- /dev/null
+++ b/cores/esp32/HardwareI2C.h
@@ -0,0 +1,41 @@
+/*
+  Copyright (c) 2016 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include <inttypes.h>
+#include "Stream.h"
+
+class HardwareI2C : public Stream {
+public:
+  virtual bool begin() = 0;
+  virtual bool begin(uint8_t address) = 0;
+  virtual bool end() = 0;
+
+  virtual bool setClock(uint32_t freq) = 0;
+
+  virtual void beginTransmission(uint8_t address) = 0;
+  virtual uint8_t endTransmission(bool stopBit) = 0;
+  virtual uint8_t endTransmission(void) = 0;
+
+  virtual size_t requestFrom(uint8_t address, size_t len, bool stopBit) = 0;
+  virtual size_t requestFrom(uint8_t address, size_t len) = 0;
+
+  virtual void onReceive(void (*)(int)) = 0;
+  virtual void onRequest(void (*)(void)) = 0;
+};
diff --git a/cores/esp32/HardwareSerial.cpp b/cores/esp32/HardwareSerial.cpp
index b06e0735a71..6d762da21fb 100644
--- a/cores/esp32/HardwareSerial.cpp
+++ b/cores/esp32/HardwareSerial.cpp
@@ -2,190 +2,663 @@
 #include <stdio.h>
 #include <string.h>
 #include <inttypes.h>
+#include <ctime>
 
 #include "pins_arduino.h"
+#include "io_pin_remap.h"
 #include "HardwareSerial.h"
+#include "soc/soc_caps.h"
+#include "driver/uart.h"
+#include "freertos/queue.h"
 
-#ifndef RX1
-#define RX1 9
+#if (SOC_UART_LP_NUM >= 1)
+#define UART_HW_FIFO_LEN(uart_num) ((uart_num < SOC_UART_HP_NUM) ? SOC_UART_FIFO_LEN : SOC_LP_UART_FIFO_LEN)
+#else
+#define UART_HW_FIFO_LEN(uart_num) SOC_UART_FIFO_LEN
 #endif
 
-#ifndef TX1
-#define TX1 10
-#endif
+void serialEvent(void) __attribute__((weak));
 
-#ifndef RX2
-#define RX2 16
-#endif
+#if SOC_UART_NUM > 1
+void serialEvent1(void) __attribute__((weak));
+#endif /* SOC_UART_NUM > 1 */
 
-#ifndef TX2
-#define TX2 17
-#endif
+#if SOC_UART_NUM > 2
+void serialEvent2(void) __attribute__((weak));
+#endif /* SOC_UART_NUM > 2 */
+
+#if SOC_UART_NUM > 3
+void serialEvent3(void) __attribute__((weak));
+#endif /* SOC_UART_NUM > 3 */
+
+#if SOC_UART_NUM > 4
+void serialEvent4(void) __attribute__((weak));
+#endif /* SOC_UART_NUM > 4 */
+
+#if SOC_UART_NUM > 5
+void serialEvent5(void) __attribute__((weak));
+#endif /* SOC_UART_NUM > 5 */
 
 #if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL)
-HardwareSerial Serial(0);
+// There is always Seria0 for UART0
+HardwareSerial Serial0(0);
+#if SOC_UART_NUM > 1
 HardwareSerial Serial1(1);
+#endif
+#if SOC_UART_NUM > 2
 HardwareSerial Serial2(2);
 #endif
+#if SOC_UART_NUM > 3
+HardwareSerial Serial3(3);
+#endif
+#if SOC_UART_NUM > 4
+HardwareSerial Serial4(4);
+#endif
+#if (SOC_UART_NUM > 5)
+HardwareSerial Serial5(5);
+#endif
+#if HWCDC_SERIAL_IS_DEFINED == 1  // Hardware JTAG CDC Event
+extern void HWCDCSerialEvent(void) __attribute__((weak));
+#endif
+
+#if USB_SERIAL_IS_DEFINED == 1  // Native USB CDC Event
+// Used by Hardware Serial for USB CDC events
+extern void USBSerialEvent(void) __attribute__((weak));
+#endif
+
+void serialEventRun(void) {
+#if HWCDC_SERIAL_IS_DEFINED == 1  // Hardware JTAG CDC Event
+  if (HWCDCSerialEvent && HWCDCSerial.available()) {
+    HWCDCSerialEvent();
+  }
+#endif
+#if USB_SERIAL_IS_DEFINED == 1  // Native USB CDC Event
+  if (USBSerialEvent && USBSerial.available()) {
+    USBSerialEvent();
+  }
+#endif
+  // UART0 is default serialEvent()
+  if (serialEvent && Serial0.available()) {
+    serialEvent();
+  }
+#if SOC_UART_NUM > 1
+  if (serialEvent1 && Serial1.available()) {
+    serialEvent1();
+  }
+#endif
+#if SOC_UART_NUM > 2
+  if (serialEvent2 && Serial2.available()) {
+    serialEvent2();
+  }
+#endif
+#if SOC_UART_NUM > 3
+  if (serialEvent3 && Serial3.available()) {
+    serialEvent3();
+  }
+#endif
+#if SOC_UART_NUM > 4
+  if (serialEvent4 && Serial4.available()) {
+    serialEvent4();
+  }
+#endif
+#if SOC_UART_NUM > 5
+  if (serialEvent5 && Serial5.available()) {
+    serialEvent5();
+  }
+#endif
+}
+#endif
 
-HardwareSerial::HardwareSerial(int uart_nr) : _uart_nr(uart_nr), _uart(NULL) {}
+#if !CONFIG_DISABLE_HAL_LOCKS
+#define HSERIAL_MUTEX_LOCK() \
+  do {                       \
+  } while (xSemaphoreTake(_lock, portMAX_DELAY) != pdPASS)
+#define HSERIAL_MUTEX_UNLOCK() xSemaphoreGive(_lock)
+#else
+#define HSERIAL_MUTEX_LOCK()
+#define HSERIAL_MUTEX_UNLOCK()
+#endif
 
-void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, int8_t txPin, bool invert, unsigned long timeout_ms)
+HardwareSerial::HardwareSerial(uint8_t uart_nr)
+  : _uart_nr(uart_nr), _uart(NULL), _rxBufferSize(256), _txBufferSize(0), _onReceiveCB(NULL), _onReceiveErrorCB(NULL), _onReceiveTimeout(false), _rxTimeout(1),
+    _rxFIFOFull(0), _eventTask(NULL)
+#if !CONFIG_DISABLE_HAL_LOCKS
+    ,
+    _lock(NULL)
+#endif
 {
-    if(0 > _uart_nr || _uart_nr > 2) {
-        log_e("Serial number is invalid, please use 0, 1 or 2");
-        return;
-    }
-    if(_uart) {
-        end();
-    }
-    if(_uart_nr == 0 && rxPin < 0 && txPin < 0) {
-        rxPin = 3;
-        txPin = 1;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (_lock == NULL) {
+    _lock = xSemaphoreCreateMutex();
+    if (_lock == NULL) {
+      log_e("xSemaphoreCreateMutex failed");
+      return;
     }
-    if(_uart_nr == 1 && rxPin < 0 && txPin < 0) {
-        rxPin = RX1;
-        txPin = TX1;
+  }
+#endif
+  // set deinit function in the Peripheral Manager
+  uart_init_PeriMan();
+}
+
+HardwareSerial::~HardwareSerial() {
+  end();  // explicit Full UART termination
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (_lock != NULL) {
+    vSemaphoreDelete(_lock);
+  }
+#endif
+}
+
+void HardwareSerial::_createEventTask(void *args) {
+  // Creating UART event Task
+  xTaskCreateUniversal(
+    _uartEventTask, "uart_event_task", ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE, this, ARDUINO_SERIAL_EVENT_TASK_PRIORITY, &_eventTask,
+    ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE
+  );
+  if (_eventTask == NULL) {
+    log_e(" -- UART%d Event Task not Created!", _uart_nr);
+  }
+}
+
+void HardwareSerial::_destroyEventTask(void) {
+  if (_eventTask != NULL) {
+    vTaskDelete(_eventTask);
+    _eventTask = NULL;
+  }
+}
+
+void HardwareSerial::onReceiveError(OnReceiveErrorCb function) {
+  HSERIAL_MUTEX_LOCK();
+  // function may be NULL to cancel onReceive() from its respective task
+  _onReceiveErrorCB = function;
+  // this can be called after Serial.begin(), therefore it shall create the event task
+  if (function != NULL && _uart != NULL && _eventTask == NULL) {
+    _createEventTask(this);
+  }
+  HSERIAL_MUTEX_UNLOCK();
+}
+
+void HardwareSerial::onReceive(OnReceiveCb function, bool onlyOnTimeout) {
+  HSERIAL_MUTEX_LOCK();
+  // function may be NULL to cancel onReceive() from its respective task
+  _onReceiveCB = function;
+
+  // setting the callback to NULL will just disable it
+  if (_onReceiveCB != NULL) {
+    // When Rx timeout is Zero (disabled), there is only one possible option that is callback when FIFO reaches 120 bytes
+    _onReceiveTimeout = _rxTimeout > 0 ? onlyOnTimeout : false;
+
+    // in case that onReceive() shall work only with RX Timeout, FIFO shall be high
+    // this is a work around for an IDF issue with events and low FIFO Full value (< 3)
+    // Not valid for the LP UART
+    if (_onReceiveTimeout && _uart_nr < SOC_UART_HP_NUM) {
+      uartSetRxFIFOFull(_uart, 120);
+      log_w("OnReceive is set to Timeout only, thus FIFO Full is now 120 bytes.");
     }
-    if(_uart_nr == 2 && rxPin < 0 && txPin < 0) {
-        rxPin = RX2;
-        txPin = TX2;
+
+    // this method can be called after Serial.begin(), therefore it shall create the event task
+    if (_uart != NULL && _eventTask == NULL) {
+      _createEventTask(this);  // Create event task
     }
+  }
+  HSERIAL_MUTEX_UNLOCK();
+}
 
-    _uart = uartBegin(_uart_nr, baud ? baud : 9600, config, rxPin, txPin, 256, invert);
-    _tx_pin = txPin;
-    _rx_pin = rxPin;
+// This function allow the user to define how many bytes will trigger an Interrupt that will copy RX FIFO to the internal RX Ringbuffer
+// ISR will also move data from FIFO to RX Ringbuffer after a RX Timeout defined in HardwareSerial::setRxTimeout(uint8_t symbols_timeout)
+// A low value of FIFO Full bytes will consume more CPU time within the ISR
+// A high value of FIFO Full bytes will make the application wait longer to have byte available for the Stkech in a streaming scenario
+// Both RX FIFO Full and RX Timeout may affect when onReceive() will be called
+bool HardwareSerial::setRxFIFOFull(uint8_t fifoBytes) {
+  HSERIAL_MUTEX_LOCK();
+  // in case that onReceive() shall work only with RX Timeout, FIFO shall be high
+  // this is a work around for an IDF issue with events and low FIFO Full value (< 3)
+  // Not valid for the LP UART
+  if (_onReceiveCB != NULL && _onReceiveTimeout && _uart_nr < SOC_UART_HP_NUM) {
+    fifoBytes = 120;
+    log_w("OnReceive is set to Timeout only, thus FIFO Full is now 120 bytes.");
+  }
+  bool retCode = uartSetRxFIFOFull(_uart, fifoBytes);  // Set new timeout
+  if (fifoBytes > 0 && fifoBytes < UART_HW_FIFO_LEN(_uart_nr) - 1) {
+    _rxFIFOFull = fifoBytes;
+  }
+  HSERIAL_MUTEX_UNLOCK();
+  return retCode;
+}
 
-    if(!baud) {
-        uartStartDetectBaudrate(_uart);
-        time_t startMillis = millis();
-        unsigned long detectedBaudRate = 0;
-        while(millis() - startMillis < timeout_ms && !(detectedBaudRate = uartDetectBaudrate(_uart))) {
-            yield();
-        }
+// timeout is calculates in time to receive UART symbols at the UART baudrate.
+// the estimation is about 11 bits per symbol (SERIAL_8N1)
+bool HardwareSerial::setRxTimeout(uint8_t symbols_timeout) {
+  HSERIAL_MUTEX_LOCK();
 
-        end();
+  // Zero disables timeout, thus, onReceive callback will only be called when RX FIFO reaches 120 bytes
+  // Any non-zero value will activate onReceive callback based on UART baudrate with about 11 bits per symbol
+  _rxTimeout = symbols_timeout;
+  if (!symbols_timeout) {
+    _onReceiveTimeout = false;  // only when RX timeout is disabled, we also must disable this flag
+  }
 
-        if(detectedBaudRate) {
-            delay(100); // Give some time...
-            _uart = uartBegin(_uart_nr, detectedBaudRate, config, rxPin, txPin, 256, invert);
-        } else {
-            log_e("Could not detect baudrate. Serial data at the port must be present within the timeout for detection to be possible");
-            _uart = NULL;
-            _tx_pin = 255;
-            _rx_pin = 255;
-        }
-    }
+  bool retCode = uartSetRxTimeout(_uart, _rxTimeout);  // Set new timeout
+
+  HSERIAL_MUTEX_UNLOCK();
+  return retCode;
 }
 
-void HardwareSerial::updateBaudRate(unsigned long baud)
-{
-	uartSetBaudRate(_uart, baud);
+void HardwareSerial::eventQueueReset() {
+  QueueHandle_t uartEventQueue = NULL;
+  if (_uart == NULL) {
+    return;
+  }
+  uartGetEventQueue(_uart, &uartEventQueue);
+  if (uartEventQueue != NULL) {
+    xQueueReset(uartEventQueue);
+  }
 }
 
-void HardwareSerial::end()
-{
-    if(uartGetDebug() == _uart_nr) {
-        uartSetDebug(0);
+void HardwareSerial::_uartEventTask(void *args) {
+  HardwareSerial *uart = (HardwareSerial *)args;
+  uart_event_t event;
+  QueueHandle_t uartEventQueue = NULL;
+  uartGetEventQueue(uart->_uart, &uartEventQueue);
+  if (uartEventQueue != NULL) {
+    for (;;) {
+      //Waiting for UART event.
+      if (xQueueReceive(uartEventQueue, (void *)&event, (TickType_t)portMAX_DELAY)) {
+        hardwareSerial_error_t currentErr = UART_NO_ERROR;
+        switch (event.type) {
+          case UART_DATA:
+            if (uart->_onReceiveCB && uart->available() > 0 && ((uart->_onReceiveTimeout && event.timeout_flag) || !uart->_onReceiveTimeout)) {
+              uart->_onReceiveCB();
+            }
+            break;
+          case UART_FIFO_OVF:
+            log_w("UART%d FIFO Overflow. Consider adding Hardware Flow Control to your Application.", uart->_uart_nr);
+            currentErr = UART_FIFO_OVF_ERROR;
+            break;
+          case UART_BUFFER_FULL:
+            log_w("UART%d Buffer Full. Consider increasing your buffer size of your Application.", uart->_uart_nr);
+            currentErr = UART_BUFFER_FULL_ERROR;
+            break;
+          case UART_BREAK:
+            log_v("UART%d RX break.", uart->_uart_nr);
+            currentErr = UART_BREAK_ERROR;
+            break;
+          case UART_PARITY_ERR:
+            log_v("UART%d parity error.", uart->_uart_nr);
+            currentErr = UART_PARITY_ERROR;
+            break;
+          case UART_FRAME_ERR:
+            log_v("UART%d frame error.", uart->_uart_nr);
+            currentErr = UART_FRAME_ERROR;
+            break;
+          default: log_v("UART%d unknown event type %d.", uart->_uart_nr, event.type); break;
+        }
+        if (currentErr != UART_NO_ERROR) {
+          if (uart->_onReceiveErrorCB) {
+            uart->_onReceiveErrorCB(currentErr);
+          }
+        }
+      }
     }
-    log_v("pins %d %d",_tx_pin, _rx_pin);
-    uartEnd(_uart, _tx_pin, _rx_pin);
-    _uart = 0;
+  }
+  vTaskDelete(NULL);
 }
 
-size_t HardwareSerial::setRxBufferSize(size_t new_size) {
-    return uartResizeRxBuffer(_uart, new_size);
-}
+void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, int8_t txPin, bool invert, unsigned long timeout_ms, uint8_t rxfifo_full_thrhd) {
+  if (_uart_nr >= SOC_UART_NUM) {
+    log_e("Serial number is invalid, please use a number from 0 to %u", SOC_UART_NUM - 1);
+    return;
+  }
 
-void HardwareSerial::setDebugOutput(bool en)
-{
-    if(_uart == 0) {
-        return;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (_lock == NULL) {
+    log_e("MUTEX Lock failed. Can't begin.");
+    return;
+  }
+#endif
+
+  // map logical pins to GPIO numbers
+  rxPin = digitalPinToGPIONumber(rxPin);
+  txPin = digitalPinToGPIONumber(txPin);
+  int8_t _rxPin = uart_get_RxPin(_uart_nr);
+  int8_t _txPin = uart_get_TxPin(_uart_nr);
+
+  rxPin = rxPin < 0 ? _rxPin : rxPin;
+  txPin = txPin < 0 ? _txPin : txPin;
+
+  HSERIAL_MUTEX_LOCK();
+  // First Time or after end() --> set default Pins
+  if (!uartIsDriverInstalled(_uart)) {
+    // get previously used RX/TX pins, if any.
+    int8_t _rxPin = uart_get_RxPin(_uart_nr);
+    int8_t _txPin = uart_get_TxPin(_uart_nr);
+    switch (_uart_nr) {
+      case UART_NUM_0:
+        if (rxPin < 0 && txPin < 0) {
+          // do not change RX0/TX0 if it has already been set before
+          rxPin = _rxPin < 0 ? (int8_t)SOC_RX0 : _rxPin;
+          txPin = _txPin < 0 ? (int8_t)SOC_TX0 : _txPin;
+        }
+        break;
+#if SOC_UART_HP_NUM > 1
+      case UART_NUM_1:
+        if (rxPin < 0 && txPin < 0) {
+          // do not change RX1/TX1 if it has already been set before
+          rxPin = _rxPin < 0 ? (int8_t)RX1 : _rxPin;
+          txPin = _txPin < 0 ? (int8_t)TX1 : _txPin;
+        }
+        break;
+#endif  // UART_NUM_1
+#if SOC_UART_HP_NUM > 2
+      case UART_NUM_2:
+        if (rxPin < 0 && txPin < 0) {
+          // do not change RX2/TX2 if it has already been set before
+#ifdef RX2
+          rxPin = _rxPin < 0 ? (int8_t)RX2 : _rxPin;
+#endif
+#ifdef TX2
+          txPin = _txPin < 0 ? (int8_t)TX2 : _txPin;
+#endif
+        }
+        break;
+#endif  // UART_NUM_2
+#if SOC_UART_HP_NUM > 3
+      case UART_NUM_3:
+        if (rxPin < 0 && txPin < 0) {
+          // do not change RX3/TX3 if it has already been set before
+#ifdef RX3
+          rxPin = _rxPin < 0 ? (int8_t)RX3 : _rxPin;
+#endif
+#ifdef TX3
+          txPin = _txPin < 0 ? (int8_t)TX3 : _txPin;
+#endif
+        }
+        break;
+#endif  // UART_NUM_3
+#if SOC_UART_HP_NUM > 4
+      case UART_NUM_4:
+        if (rxPin < 0 && txPin < 0) {
+          // do not change RX4/TX4 if it has already been set before
+#ifdef RX4
+          rxPin = _rxPin < 0 ? (int8_t)RX4 : _rxPin;
+#endif
+#ifdef TX4
+          txPin = _txPin < 0 ? (int8_t)TX4 : _txPin;
+#endif
+        }
+        break;
+#endif  // UART_NUM_4
+#if (SOC_UART_LP_NUM >= 1)
+      case LP_UART_NUM_0:
+        if (rxPin < 0 && txPin < 0) {
+          // do not change RX0_LP/TX0_LP if it has already been set before
+#ifdef LP_RX0
+          rxPin = _rxPin < 0 ? (int8_t)LP_RX0 : _rxPin;
+#endif
+#ifdef LP_TX0
+          txPin = _txPin < 0 ? (int8_t)LP_TX0 : _txPin;
+#endif
+        }
+        break;
+#endif  // LP_UART_NUM_0
+    }
+  }
+
+  // if no RX/TX pins are defined, it will not start the UART driver
+  if (rxPin < 0 && txPin < 0) {
+    log_e("No RX/TX pins defined. Please set RX/TX pins.");
+    HSERIAL_MUTEX_UNLOCK();
+    return;
+  }
+
+  // IDF UART driver keeps Pin setting on restarting. Negative Pin number will keep it unmodified.
+  // it will detach previous UART attached pins
+
+  // indicates that uartbegin() has to initialize a new IDF driver
+  if (_testUartBegin(_uart_nr, baud ? baud : 9600, config, rxPin, txPin, _rxBufferSize, _txBufferSize, invert, rxfifo_full_thrhd)) {
+    _destroyEventTask();  // when IDF uart driver must be restarted, _eventTask must finish too
+  }
+
+  // IDF UART driver keeps Pin setting on restarting. Negative Pin number will keep it unmodified.
+  // it will detach previous UART attached pins
+  _uart = uartBegin(_uart_nr, baud ? baud : 9600, config, rxPin, txPin, _rxBufferSize, _txBufferSize, invert, rxfifo_full_thrhd);
+  if (_uart == NULL) {
+    log_e("UART driver failed to start. Please check the logs.");
+    HSERIAL_MUTEX_UNLOCK();
+    return;
+  }
+  if (!baud) {
+    // using baud rate as zero, forces it to try to detect the current baud rate in place
+    uartStartDetectBaudrate(_uart);
+    time_t startMillis = millis();
+    unsigned long detectedBaudRate = 0;
+    while (millis() - startMillis < timeout_ms && !(detectedBaudRate = uartDetectBaudrate(_uart))) {
+      yield();
     }
-    if(en) {
-        uartSetDebug(_uart);
+
+    if (detectedBaudRate) {
+      delay(100);  // Give some time...
+      _uart = uartBegin(_uart_nr, detectedBaudRate, config, rxPin, txPin, _rxBufferSize, _txBufferSize, invert, rxfifo_full_thrhd);
+      if (_uart == NULL) {
+        log_e("UART driver failed to start. Please check the logs.");
+        HSERIAL_MUTEX_UNLOCK();
+        return;
+      }
     } else {
-        if(uartGetDebug() == _uart_nr) {
-            uartSetDebug(0);
-        }
+      log_e("Could not detect baudrate. Serial data at the port must be present within the timeout for detection to be possible");
+      _uart = NULL;
+    }
+  }
+  // create a task to deal with Serial Events when, for example, calling begin() twice to change the baudrate,
+  // or when setting the callback before calling begin()
+  if (_uart != NULL && (_onReceiveCB != NULL || _onReceiveErrorCB != NULL) && _eventTask == NULL) {
+    _createEventTask(this);
+  }
+
+  // Set UART RX timeout
+  uartSetRxTimeout(_uart, _rxTimeout);
+
+  // Set UART FIFO Full depending on the baud rate.
+  // Lower baud rates will force to emulate byte-by-byte reading
+  // Higher baud rates will keep IDF default of 120 bytes for FIFO FULL Interrupt
+  // It can also be changed by the application at any time
+  if (!_rxFIFOFull) {  // it has not being changed before calling begin()
+    //  set a default FIFO Full value for the IDF driver
+    uint8_t fifoFull = 1;
+    // if baud rate is higher than 57600 or onReceive() is set, it will set FIFO Full to 120 bytes, except for LP UART
+    if (_uart_nr < SOC_UART_HP_NUM && (baud > 57600 || (_onReceiveCB != NULL && _onReceiveTimeout))) {
+      fifoFull = 120;
     }
+    uartSetRxFIFOFull(_uart, fifoFull);
+    _rxFIFOFull = fifoFull;
+  }
+
+  HSERIAL_MUTEX_UNLOCK();
 }
 
-int HardwareSerial::available(void)
-{
-    return uartAvailable(_uart);
+void HardwareSerial::updateBaudRate(unsigned long baud) {
+  uartSetBaudRate(_uart, baud);
 }
-int HardwareSerial::availableForWrite(void)
-{
-    return uartAvailableForWrite(_uart);
+
+void HardwareSerial::end() {
+  // default Serial.end() will completely disable HardwareSerial,
+  // including any tasks or debug message channel (log_x()) - but not for IDF log messages!
+  _onReceiveCB = NULL;
+  _onReceiveErrorCB = NULL;
+  if (uartGetDebug() == _uart_nr) {
+    uartSetDebug(0);
+  }
+  _rxFIFOFull = 0;
+  uartEnd(_uart_nr);    // fully detach all pins and delete the UART driver
+  _destroyEventTask();  // when IDF uart driver is deleted, _eventTask must finish too
+  _uart = NULL;
 }
 
-int HardwareSerial::peek(void)
-{
-    if (available()) {
-        return uartPeek(_uart);
+void HardwareSerial::setDebugOutput(bool en) {
+  if (_uart == 0) {
+    return;
+  }
+#if (SOC_UART_LP_NUM >= 1)
+  if (_uart_nr >= SOC_UART_HP_NUM) {
+    log_e("LP UART does not support Debug Output.");
+    return;
+  }
+#endif
+  if (en) {
+    uartSetDebug(_uart);
+  } else {
+    if (uartGetDebug() == _uart_nr) {
+      uartSetDebug(NULL);
     }
-    return -1;
+  }
 }
 
-int HardwareSerial::read(void)
-{
-    if(available()) {
-        return uartRead(_uart);
-    }
+int HardwareSerial::available(void) {
+  return uartAvailable(_uart);
+}
+int HardwareSerial::availableForWrite(void) {
+  return uartAvailableForWrite(_uart);
+}
+
+int HardwareSerial::peek(void) {
+  if (available()) {
+    return uartPeek(_uart);
+  }
+  return -1;
+}
+
+int HardwareSerial::read(void) {
+  uint8_t c = 0;
+  if (uartReadBytes(_uart, &c, 1, 0) == 1) {
+    return c;
+  } else {
     return -1;
+  }
 }
 
 // read characters into buffer
 // terminates if size characters have been read, or no further are pending
 // returns the number of characters placed in the buffer
 // the buffer is NOT null terminated.
-size_t HardwareSerial::read(uint8_t *buffer, size_t size)
-{
-    size_t avail = available();
-    if (size < avail) {
-        avail = size;
-    }
-    size_t count = 0;
-    while(count < avail) {
-        *buffer++ = uartRead(_uart);
-        count++;
-    }
-    return count;
+size_t HardwareSerial::read(uint8_t *buffer, size_t size) {
+  return uartReadBytes(_uart, buffer, size, 0);
 }
 
-void HardwareSerial::flush(void)
-{
-    uartFlush(_uart);
+// Overrides Stream::readBytes() to be faster using IDF
+size_t HardwareSerial::readBytes(uint8_t *buffer, size_t length) {
+  return uartReadBytes(_uart, buffer, length, (uint32_t)getTimeout());
 }
 
-void HardwareSerial::flush(bool txOnly)
-{
-    uartFlushTxOnly(_uart, txOnly);
+void HardwareSerial::flush(void) {
+  uartFlush(_uart);
 }
 
-size_t HardwareSerial::write(uint8_t c)
-{
-    uartWrite(_uart, c);
-    return 1;
+void HardwareSerial::flush(bool txOnly) {
+  uartFlushTxOnly(_uart, txOnly);
 }
 
-size_t HardwareSerial::write(const uint8_t *buffer, size_t size)
-{
-    uartWriteBuf(_uart, buffer, size);
-    return size;
+size_t HardwareSerial::write(uint8_t c) {
+  uartWrite(_uart, c);
+  return 1;
 }
-uint32_t  HardwareSerial::baudRate()
 
-{
-	return uartGetBaudRate(_uart);
+size_t HardwareSerial::write(const uint8_t *buffer, size_t size) {
+  uartWriteBuf(_uart, buffer, size);
+  return size;
 }
-HardwareSerial::operator bool() const
-{
-    return true;
+
+uint32_t HardwareSerial::baudRate() {
+  return uartGetBaudRate(_uart);
+}
+HardwareSerial::operator bool() const {
+  return uartIsDriverInstalled(_uart);
 }
 
-void HardwareSerial::setRxInvert(bool invert)
-{
-    uartSetRxInvert(_uart, invert);
+void HardwareSerial::setRxInvert(bool invert) {
+  uartSetRxInvert(_uart, invert);
+}
+
+// negative Pin value will keep it unmodified
+// can be called after or before begin()
+bool HardwareSerial::setPins(int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin) {
+  // map logical pins to GPIO numbers
+  rxPin = digitalPinToGPIONumber(rxPin);
+  txPin = digitalPinToGPIONumber(txPin);
+  ctsPin = digitalPinToGPIONumber(ctsPin);
+  rtsPin = digitalPinToGPIONumber(rtsPin);
+
+  // uartSetPins() checks if pins are valid and, if necessary, detaches the previous ones
+  return uartSetPins(_uart_nr, rxPin, txPin, ctsPin, rtsPin);
+}
+
+// Enables or disables Hardware Flow Control using RTS and/or CTS pins
+// must use setAllPins() in order to set RTS/CTS pins
+// SerialHwFlowCtrl = UART_HW_FLOWCTRL_DISABLE, UART_HW_FLOWCTRL_RTS,
+//                    UART_HW_FLOWCTRL_CTS, UART_HW_FLOWCTRL_CTS_RTS
+bool HardwareSerial::setHwFlowCtrlMode(SerialHwFlowCtrl mode, uint8_t threshold) {
+  return uartSetHwFlowCtrlMode(_uart, mode, threshold);
+}
+
+// Sets the uart mode in the esp32 uart for use with RS485 modes
+// HwFlowCtrl must be disabled and RTS pin set
+// SerialMode = UART_MODE_UART, UART_MODE_RS485_HALF_DUPLEX, UART_MODE_IRDA,
+// or testing mode: UART_MODE_RS485_COLLISION_DETECT, UART_MODE_RS485_APP_CTRL
+bool HardwareSerial::setMode(SerialMode mode) {
+  return uartSetMode(_uart, mode);
+}
+
+// Sets the UART Clock Source based on the compatible SoC options
+// This method must be called before starting UART using begin(), otherwise it won't have any effect.
+// Clock Source Options are:
+// UART_CLK_SRC_DEFAULT      :: any SoC - it will set whatever IDF defines as the default UART Clock Source
+// UART_CLK_SRC_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
+// UART_CLK_SRC_PLL          :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
+// UART_CLK_SRC_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+// UART_CLK_SRC_RTC          :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+// UART_CLK_SRC_REF_TICK     :: ESP32 and ESP32-S2
+// Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
+// Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
+bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
+  if (_uart) {
+    log_e("No Clock Source change was done. This function must be called before beginning UART%d.", _uart_nr);
+    return false;
+  }
+  return uartSetClockSource(_uart_nr, (uart_sclk_t)clkSrc);
+}
+// minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.
+// LP UART has FIFO of 16 bytes
+size_t HardwareSerial::setRxBufferSize(size_t new_size) {
+
+  if (_uart) {
+    log_e("RX Buffer can't be resized when Serial is already running. Set it before calling begin().");
+    return 0;
+  }
+  uint8_t FIFOLen = UART_HW_FIFO_LEN(_uart_nr);
+  // Valid value is higher than the FIFO length
+  if (new_size <= FIFOLen) {
+    new_size = FIFOLen + 1;
+    log_w("RX Buffer set to minimum value: %d.", new_size);
+  }
+
+  _rxBufferSize = new_size;
+  return _rxBufferSize;
+}
+
+// minimum total TX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1.
+// LP UART has FIFO of 16 bytes
+size_t HardwareSerial::setTxBufferSize(size_t new_size) {
+
+  if (_uart) {
+    log_e("TX Buffer can't be resized when Serial is already running. Set it before calling begin().");
+    return 0;
+  }
+  uint8_t FIFOLen = UART_HW_FIFO_LEN(_uart_nr);
+  // Valid values are zero or higher than the FIFO length
+  if (new_size > 0 && new_size <= FIFOLen) {
+    new_size = FIFOLen + 1;
+    log_w("TX Buffer set to minimum value: %d.", new_size);
+  }
+  // if new_size is higher than SOC_UART_FIFO_LEN, TX Ringbuffer will be active and it will be used to report back "availableToWrite()"
+  _txBufferSize = new_size;
+  return new_size;
 }
diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h
index e776e939d0b..e974f112701 100644
--- a/cores/esp32/HardwareSerial.h
+++ b/cores/esp32/HardwareSerial.h
@@ -46,76 +46,396 @@
 #define HardwareSerial_h
 
 #include <inttypes.h>
-
+#include <functional>
 #include "Stream.h"
 #include "esp32-hal.h"
+#include "soc/soc_caps.h"
+#include "HWCDC.h"
+#include "USBCDC.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+
+enum SerialConfig {
+  SERIAL_5N1 = 0x8000010,
+  SERIAL_6N1 = 0x8000014,
+  SERIAL_7N1 = 0x8000018,
+  SERIAL_8N1 = 0x800001c,
+  SERIAL_5N2 = 0x8000030,
+  SERIAL_6N2 = 0x8000034,
+  SERIAL_7N2 = 0x8000038,
+  SERIAL_8N2 = 0x800003c,
+  SERIAL_5E1 = 0x8000012,
+  SERIAL_6E1 = 0x8000016,
+  SERIAL_7E1 = 0x800001a,
+  SERIAL_8E1 = 0x800001e,
+  SERIAL_5E2 = 0x8000032,
+  SERIAL_6E2 = 0x8000036,
+  SERIAL_7E2 = 0x800003a,
+  SERIAL_8E2 = 0x800003e,
+  SERIAL_5O1 = 0x8000013,
+  SERIAL_6O1 = 0x8000017,
+  SERIAL_7O1 = 0x800001b,
+  SERIAL_8O1 = 0x800001f,
+  SERIAL_5O2 = 0x8000033,
+  SERIAL_6O2 = 0x8000037,
+  SERIAL_7O2 = 0x800003b,
+  SERIAL_8O2 = 0x800003f
+};
+
+typedef uart_mode_t SerialMode;
+typedef uart_hw_flowcontrol_t SerialHwFlowCtrl;
+
+typedef enum {
+  UART_NO_ERROR,
+  UART_BREAK_ERROR,
+  UART_BUFFER_FULL_ERROR,
+  UART_FIFO_OVF_ERROR,
+  UART_FRAME_ERROR,
+  UART_PARITY_ERROR
+} hardwareSerial_error_t;
+
+typedef enum {
+  UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT,
+#if SOC_UART_SUPPORT_APB_CLK
+  UART_CLK_SRC_APB = UART_SCLK_APB,
+#endif
+#if SOC_UART_SUPPORT_PLL_F40M_CLK
+  UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M,
+#elif SOC_UART_SUPPORT_PLL_F80M_CLK
+  UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M,
+#elif CONFIG_IDF_TARGET_ESP32H2
+  UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M,
+#endif
+#if SOC_UART_SUPPORT_XTAL_CLK
+  UART_CLK_SRC_XTAL = UART_SCLK_XTAL,
+#endif
+#if SOC_UART_SUPPORT_RTC_CLK
+  UART_CLK_SRC_RTC = UART_SCLK_RTC,
+#endif
+#if SOC_UART_SUPPORT_REF_TICK
+  UART_CLK_SRC_REF_TICK = UART_SCLK_REF_TICK,
+#endif
+} SerialClkSrc;
+
+#ifndef ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
+#ifndef CONFIG_ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
+#define ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE 2048
+#else
+#define ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE CONFIG_ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
+#endif
+#endif
+
+#ifndef ARDUINO_SERIAL_EVENT_TASK_PRIORITY
+#ifndef CONFIG_ARDUINO_SERIAL_EVENT_TASK_PRIORITY
+#define ARDUINO_SERIAL_EVENT_TASK_PRIORITY (configMAX_PRIORITIES - 1)
+#else
+#define ARDUINO_SERIAL_EVENT_TASK_PRIORITY CONFIG_ARDUINO_SERIAL_EVENT_TASK_PRIORITY
+#endif
+#endif
+
+#ifndef ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE
+#ifndef CONFIG_ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE
+#define ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE -1
+#else
+#define ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE CONFIG_ARDUINO_SERIAL_EVENT_TASK_RUNNING_CORE
+#endif
+#endif
+
+// UART0 pins are defined by default by the bootloader.
+// The definitions for SOC_* should not be changed unless the bootloader pins
+// have changed and you know what you are doing.
+
+#ifndef SOC_RX0
+#if CONFIG_IDF_TARGET_ESP32
+#define SOC_RX0 (gpio_num_t)3
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#define SOC_RX0 (gpio_num_t)44
+#elif CONFIG_IDF_TARGET_ESP32C2
+#define SOC_RX0 (gpio_num_t)19
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define SOC_RX0 (gpio_num_t)20
+#elif CONFIG_IDF_TARGET_ESP32C6
+#define SOC_RX0 (gpio_num_t)17
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define SOC_RX0 (gpio_num_t)23
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define SOC_RX0 (gpio_num_t)38
+#endif
+#endif
+
+#ifndef SOC_TX0
+#if CONFIG_IDF_TARGET_ESP32
+#define SOC_TX0 (gpio_num_t)1
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#define SOC_TX0 (gpio_num_t)43
+#elif CONFIG_IDF_TARGET_ESP32C2
+#define SOC_TX0 (gpio_num_t)20
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define SOC_TX0 (gpio_num_t)21
+#elif CONFIG_IDF_TARGET_ESP32C6
+#define SOC_TX0 (gpio_num_t)16
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define SOC_TX0 (gpio_num_t)24
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define SOC_TX0 (gpio_num_t)37
+#endif
+#endif
+
+// Default pins for UART1 are arbitrary, and defined here for convenience.
+
+#if SOC_UART_HP_NUM > 1
+#ifndef RX1
+#if CONFIG_IDF_TARGET_ESP32
+#define RX1 (gpio_num_t)26
+#elif CONFIG_IDF_TARGET_ESP32S2
+#define RX1 (gpio_num_t)4
+#elif CONFIG_IDF_TARGET_ESP32C2
+#define RX1 (gpio_num_t)10
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define RX1 (gpio_num_t)18
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define RX1 (gpio_num_t)15
+#elif CONFIG_IDF_TARGET_ESP32C6
+#define RX1 (gpio_num_t)4
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define RX1 (gpio_num_t)0
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define RX1 (gpio_num_t)11
+#endif
+#endif
 
-class HardwareSerial: public Stream
-{
+#ifndef TX1
+#if CONFIG_IDF_TARGET_ESP32
+#define TX1 (gpio_num_t)27
+#elif CONFIG_IDF_TARGET_ESP32S2
+#define TX1 (gpio_num_t)5
+#elif CONFIG_IDF_TARGET_ESP32C2
+#define TX1 (gpio_num_t)18
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define TX1 (gpio_num_t)19
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define TX1 (gpio_num_t)16
+#elif CONFIG_IDF_TARGET_ESP32C6
+#define TX1 (gpio_num_t)5
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define TX1 (gpio_num_t)1
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define TX1 (gpio_num_t)10
+#endif
+#endif
+#endif /* SOC_UART_HP_NUM > 1 */
+
+// Default pins for UART2 are arbitrary, and defined here for convenience.
+
+#if SOC_UART_HP_NUM > 2
+#ifndef RX2
+#if CONFIG_IDF_TARGET_ESP32
+#define RX2 (gpio_num_t)4
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define RX2 (gpio_num_t)19
+#endif
+#endif
+
+#ifndef TX2
+#if CONFIG_IDF_TARGET_ESP32
+#define TX2 (gpio_num_t)25
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define TX2 (gpio_num_t)20
+#endif
+#endif
+#endif /* SOC_UART_HP_NUM > 2 */
+
+#if SOC_UART_LP_NUM >= 1
+#ifndef LP_RX0
+#define LP_RX0 (gpio_num_t) LP_U0RXD_GPIO_NUM
+#endif
+
+#ifndef LP_TX0
+#define LP_TX0 (gpio_num_t) LP_U0TXD_GPIO_NUM
+#endif
+#endif /* SOC_UART_LP_NUM >= 1 */
+
+typedef std::function<void(void)> OnReceiveCb;
+typedef std::function<void(hardwareSerial_error_t)> OnReceiveErrorCb;
+
+class HardwareSerial : public Stream {
 public:
-    HardwareSerial(int uart_nr);
-
-    void begin(unsigned long baud, uint32_t config=SERIAL_8N1, int8_t rxPin=-1, int8_t txPin=-1, bool invert=false, unsigned long timeout_ms = 20000UL);
-    void end();
-    void updateBaudRate(unsigned long baud);
-    int available(void);
-    int availableForWrite(void);
-    int peek(void);
-    int read(void);
-    size_t read(uint8_t *buffer, size_t size);
-    inline size_t read(char * buffer, size_t size)
-    {
-        return read((uint8_t*) buffer, size);
-    }
-    void flush(void);
-    void flush( bool txOnly);
-    size_t write(uint8_t);
-    size_t write(const uint8_t *buffer, size_t size);
-    inline size_t write(const char * buffer, size_t size)
-    {
-        return write((uint8_t*) buffer, size);
-    }
-    inline size_t write(const char * s)
-    {
-        return write((uint8_t*) s, strlen(s));
-    }
-    inline size_t write(unsigned long n)
-    {
-        return write((uint8_t) n);
-    }
-    inline size_t write(long n)
-    {
-        return write((uint8_t) n);
-    }
-    inline size_t write(unsigned int n)
-    {
-        return write((uint8_t) n);
-    }
-    inline size_t write(int n)
-    {
-        return write((uint8_t) n);
-    }
-    uint32_t baudRate();
-    operator bool() const;
-
-    size_t setRxBufferSize(size_t);
-    void setDebugOutput(bool);
-    
-    void setRxInvert(bool);
+  HardwareSerial(uint8_t uart_nr);
+  ~HardwareSerial();
+
+  // setRxTimeout sets the timeout after which onReceive callback will be called (after receiving data, it waits for this time of UART rx inactivity to call the callback fnc)
+  // param symbols_timeout defines a timeout threshold in uart symbol periods. Setting 0 symbol timeout disables the callback call by timeout.
+  //                       Maximum timeout setting is calculacted automatically by IDF. If set above the maximum, it is ignored and an error is printed on Serial0 (check console).
+  //                       Examples: Maximum for 11 bits symbol is 92 (SERIAL_8N2, SERIAL_8E1, SERIAL_8O1, etc), Maximum for 10 bits symbol is 101 (SERIAL_8N1).
+  //                       For example symbols_timeout=1 defines a timeout equal to transmission time of one symbol (~11 bit) on current baudrate.
+  //                       For a baudrate of 9600, SERIAL_8N1 (10 bit symbol) and symbols_timeout = 3, the timeout would be 3 / (9600 / 10) = 3.125 ms
+  bool setRxTimeout(uint8_t symbols_timeout);
+
+  // setRxFIFOFull(uint8_t fifoBytes) will set the number of bytes that will trigger UART_INTR_RXFIFO_FULL interrupt and fill up RxRingBuffer
+  // This affects some functions such as Serial::available() and Serial.read() because, in a UART flow of receiving data, Serial internal
+  // RxRingBuffer will be filled only after these number of bytes arrive or a RX Timeout happens.
+  // This parameter can be set to 1 in order to receive byte by byte, but it will also consume more CPU time as the ISR will be activates often.
+  bool setRxFIFOFull(uint8_t fifoBytes);
+
+  // onReceive will setup a callback that will be called whenever an UART interruption occurs (UART_INTR_RXFIFO_FULL or UART_INTR_RXFIFO_TOUT)
+  // UART_INTR_RXFIFO_FULL interrupt triggers at UART_FULL_THRESH_DEFAULT bytes received (defined as 120 bytes by default in IDF)
+  // UART_INTR_RXFIFO_TOUT interrupt triggers at UART_TOUT_THRESH_DEFAULT symbols passed without any reception (defined as 10 symbols by default in IDF)
+  // onlyOnTimeout parameter will define how onReceive will behave:
+  // Default: true -- The callback will only be called when RX Timeout happens.
+  //                  Whole stream of bytes will be ready for being read on the callback function at once.
+  //                  This option may lead to Rx Overflow depending on the Rx Buffer Size and number of bytes received in the streaming
+  //         false -- The callback will be called when FIFO reaches 120 bytes and also on RX Timeout.
+  //                  The stream of incommig bytes will be "split" into blocks of 120 bytes on each callback.
+  //                  This option avoid any sort of Rx Overflow, but leaves the UART packet reassembling work to the Application.
+  void onReceive(OnReceiveCb function, bool onlyOnTimeout = false);
+
+  // onReceive will be called on error events (see hardwareSerial_error_t)
+  void onReceiveError(OnReceiveErrorCb function);
+
+  // eventQueueReset clears all events in the queue (the events that trigger onReceive and onReceiveError) - maybe useful in some use cases
+  void eventQueueReset();
+
+  // When pins are changed, it will detach the previous ones
+  // if pin is negative, it won't be set/changed and will be kept as is
+  // timeout_ms is used in baudrate detection (ESP32, ESP32S2 only)
+  // invert will invert RX/TX polarity
+  // rxfifo_full_thrhd if the UART Flow Control Threshold in the UART FIFO (max 127)
+  void begin(
+    unsigned long baud, uint32_t config = SERIAL_8N1, int8_t rxPin = -1, int8_t txPin = -1, bool invert = false, unsigned long timeout_ms = 20000UL,
+    uint8_t rxfifo_full_thrhd = 120
+  );
+  void end(void);
+  void updateBaudRate(unsigned long baud);
+  int available(void);
+  int availableForWrite(void);
+  int peek(void);
+  int read(void);
+  size_t read(uint8_t *buffer, size_t size);
+  inline size_t read(char *buffer, size_t size) {
+    return read((uint8_t *)buffer, size);
+  }
+  // Overrides Stream::readBytes() to be faster using IDF
+  size_t readBytes(uint8_t *buffer, size_t length);
+  size_t readBytes(char *buffer, size_t length) {
+    return readBytes((uint8_t *)buffer, length);
+  }
+  void flush(void);
+  void flush(bool txOnly);
+  size_t write(uint8_t);
+  size_t write(const uint8_t *buffer, size_t size);
+  inline size_t write(const char *buffer, size_t size) {
+    return write((uint8_t *)buffer, size);
+  }
+  inline size_t write(const char *s) {
+    return write((uint8_t *)s, strlen(s));
+  }
+  inline size_t write(unsigned long n) {
+    return write((uint8_t)n);
+  }
+  inline size_t write(long n) {
+    return write((uint8_t)n);
+  }
+  inline size_t write(unsigned int n) {
+    return write((uint8_t)n);
+  }
+  inline size_t write(int n) {
+    return write((uint8_t)n);
+  }
+  uint32_t baudRate();
+  operator bool() const;
+
+  void setDebugOutput(bool);
+
+  void setRxInvert(bool);
+
+  // Negative Pin Number will keep it unmodified, thus this function can set individual pins
+  // setPins() can be called after or before begin()
+  // When pins are changed, it will detach the previous ones
+  bool setPins(int8_t rxPin, int8_t txPin, int8_t ctsPin = -1, int8_t rtsPin = -1);
+  // Enables or disables Hardware Flow Control using RTS and/or CTS pins (must use setAllPins() before)
+  //    UART_HW_FLOWCTRL_DISABLE = 0x0   disable hardware flow control
+  //    UART_HW_FLOWCTRL_RTS     = 0x1   enable RX hardware flow control (rts)
+  //    UART_HW_FLOWCTRL_CTS     = 0x2   enable TX hardware flow control (cts)
+  //    UART_HW_FLOWCTRL_CTS_RTS = 0x3   enable hardware flow control
+  bool setHwFlowCtrlMode(SerialHwFlowCtrl mode = UART_HW_FLOWCTRL_CTS_RTS, uint8_t threshold = 64);  // 64 is half FIFO Length
+  // Used to set RS485 modes such as UART_MODE_RS485_HALF_DUPLEX for Auto RTS function on ESP32
+  //    UART_MODE_UART                   = 0x00    mode: regular UART mode
+  //    UART_MODE_RS485_HALF_DUPLEX      = 0x01    mode: half duplex RS485 UART mode control by RTS pin
+  //    UART_MODE_IRDA                   = 0x02    mode: IRDA UART mode
+  //    UART_MODE_RS485_COLLISION_DETECT = 0x03    mode: RS485 collision detection UART mode (used for test purposes)
+  //    UART_MODE_RS485_APP_CTRL         = 0x04    mode: application control RS485 UART mode (used for test purposes)
+  bool setMode(SerialMode mode);
+  // Used to set the UART clock source mode. It must be set before calling begin(), otherwise it won't have any effect.
+  // Not all clock source are available to every SoC. The compatible option are listed here:
+  // UART_CLK_SRC_DEFAULT      :: any SoC - it will set whatever IDF defines as the default UART Clock Source
+  // UART_CLK_SRC_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
+  // UART_CLK_SRC_PLL          :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
+  // UART_CLK_SRC_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+  // UART_CLK_SRC_RTC          :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+  // UART_CLK_SRC_REF_TICK     :: ESP32 and ESP32-S2
+  // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
+  // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
+  bool setClockSource(SerialClkSrc clkSrc);
+  size_t setRxBufferSize(size_t new_size);
+  size_t setTxBufferSize(size_t new_size);
 
 protected:
-    int _uart_nr;
-    uart_t* _uart;
-    uint8_t _tx_pin;
-    uint8_t _rx_pin;
+  uint8_t _uart_nr;
+  uart_t *_uart;
+  size_t _rxBufferSize;
+  size_t _txBufferSize;
+  OnReceiveCb _onReceiveCB;
+  OnReceiveErrorCb _onReceiveErrorCB;
+  // _onReceive and _rxTimeout have be consistent when timeout is disabled
+  bool _onReceiveTimeout;
+  uint8_t _rxTimeout, _rxFIFOFull;
+  TaskHandle_t _eventTask;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  SemaphoreHandle_t _lock;
+#endif
+
+  void _createEventTask(void *args);
+  void _destroyEventTask(void);
+  static void _uartEventTask(void *args);
 };
 
 extern void serialEventRun(void) __attribute__((weak));
 
 #if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL)
-extern HardwareSerial Serial;
+#ifndef ARDUINO_USB_CDC_ON_BOOT
+#define ARDUINO_USB_CDC_ON_BOOT 0
+#endif
+#if ARDUINO_USB_CDC_ON_BOOT  //Serial used from Native_USB_CDC | HW_CDC_JTAG
+#if ARDUINO_USB_MODE         // Hardware CDC mode
+// Arduino Serial is the HW JTAG CDC device
+#define Serial HWCDCSerial
+#else  // !ARDUINO_USB_MODE -- Native USB Mode
+// Arduino Serial is the Native USB CDC device
+#define Serial USBSerial
+#endif  // ARDUINO_USB_MODE
+#else   // !ARDUINO_USB_CDC_ON_BOOT -- Serial is used from UART0
+// if not using CDC on Boot, Arduino Serial is the UART0 device
+#define Serial Serial0
+#endif  // ARDUINO_USB_CDC_ON_BOOT
+// There is always Seria0 for UART0
+extern HardwareSerial Serial0;
+#if SOC_UART_NUM > 1
 extern HardwareSerial Serial1;
+#endif
+#if SOC_UART_NUM > 2
 extern HardwareSerial Serial2;
 #endif
+#if SOC_UART_NUM > 3
+extern HardwareSerial Serial3;
+#endif
+#if SOC_UART_NUM > 4
+extern HardwareSerial Serial4;
+#endif
+#if SOC_UART_NUM > 5
+extern HardwareSerial Serial5;
+#endif
+#endif  //!defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL)
 
-#endif // HardwareSerial_h
+#endif  // HardwareSerial_h
diff --git a/cores/esp32/HashBuilder.h b/cores/esp32/HashBuilder.h
new file mode 100644
index 00000000000..77d1c71dbde
--- /dev/null
+++ b/cores/esp32/HashBuilder.h
@@ -0,0 +1,48 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef HashBuilder_h
+#define HashBuilder_h
+
+#include <WString.h>
+#include <Stream.h>
+
+#include "HEXBuilder.h"
+
+class HashBuilder : public HEXBuilder {
+public:
+  virtual ~HashBuilder() {}
+  virtual void begin() = 0;
+
+  virtual void add(const uint8_t *data, size_t len) = 0;
+  virtual void add(const char *data) {
+    add((const uint8_t *)data, strlen(data));
+  }
+  virtual void add(String data) {
+    add(data.c_str());
+  }
+
+  virtual void addHexString(const char *data) = 0;
+  virtual void addHexString(String data) {
+    addHexString(data.c_str());
+  }
+
+  virtual bool addStream(Stream &stream, const size_t maxLen) = 0;
+  virtual void calculate() = 0;
+  virtual void getBytes(uint8_t *output) = 0;
+  virtual void getChars(char *output) = 0;
+  virtual String toString() = 0;
+};
+
+#endif
diff --git a/cores/esp32/IPAddress.cpp b/cores/esp32/IPAddress.cpp
index cabfdf32d26..299a625ff27 100644
--- a/cores/esp32/IPAddress.cpp
+++ b/cores/esp32/IPAddress.cpp
@@ -1,122 +1,453 @@
 /*
- IPAddress.cpp - Base class that provides IPAddress
- Copyright (c) 2011 Adrian McEwen.  All right reserved.
+  IPAddress.cpp - Base class that provides IPAddress
+  Copyright (c) 2011 Adrian McEwen.  All right reserved.
 
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
 
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
 
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
 
-#include <Arduino.h>
-#include <IPAddress.h>
-#include <Print.h>
+#include "IPAddress.h"
+#include "Print.h"
+#include "lwip/netif.h"
+#include "StreamString.h"
 
-IPAddress::IPAddress()
-{
-    _address.dword = 0;
+#ifndef CONFIG_LWIP_IPV6
+#define IP6_NO_ZONE 0
+#endif
+
+IPAddress::IPAddress() : IPAddress(IPv4) {}
+
+IPAddress::IPAddress(IPType ip_type) {
+  _type = ip_type;
+  _zone = IP6_NO_ZONE;
+  memset(_address.bytes, 0, sizeof(_address.bytes));
 }
 
-IPAddress::IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet)
-{
-    _address.bytes[0] = first_octet;
-    _address.bytes[1] = second_octet;
-    _address.bytes[2] = third_octet;
-    _address.bytes[3] = fourth_octet;
+IPAddress::IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet) {
+  _type = IPv4;
+  _zone = IP6_NO_ZONE;
+  memset(_address.bytes, 0, sizeof(_address.bytes));
+  _address.bytes[IPADDRESS_V4_BYTES_INDEX] = first_octet;
+  _address.bytes[IPADDRESS_V4_BYTES_INDEX + 1] = second_octet;
+  _address.bytes[IPADDRESS_V4_BYTES_INDEX + 2] = third_octet;
+  _address.bytes[IPADDRESS_V4_BYTES_INDEX + 3] = fourth_octet;
 }
 
-IPAddress::IPAddress(uint32_t address)
-{
-    _address.dword = address;
+IPAddress::IPAddress(
+  uint8_t o1, uint8_t o2, uint8_t o3, uint8_t o4, uint8_t o5, uint8_t o6, uint8_t o7, uint8_t o8, uint8_t o9, uint8_t o10, uint8_t o11, uint8_t o12,
+  uint8_t o13, uint8_t o14, uint8_t o15, uint8_t o16, uint8_t z
+) {
+  _type = IPv6;
+  _address.bytes[0] = o1;
+  _address.bytes[1] = o2;
+  _address.bytes[2] = o3;
+  _address.bytes[3] = o4;
+  _address.bytes[4] = o5;
+  _address.bytes[5] = o6;
+  _address.bytes[6] = o7;
+  _address.bytes[7] = o8;
+  _address.bytes[8] = o9;
+  _address.bytes[9] = o10;
+  _address.bytes[10] = o11;
+  _address.bytes[11] = o12;
+  _address.bytes[12] = o13;
+  _address.bytes[13] = o14;
+  _address.bytes[14] = o15;
+  _address.bytes[15] = o16;
+  _zone = z;
 }
 
-IPAddress::IPAddress(const uint8_t *address)
-{
-    memcpy(_address.bytes, address, sizeof(_address.bytes));
+IPAddress::IPAddress(uint32_t address) {
+  // IPv4 only
+  _type = IPv4;
+  _zone = IP6_NO_ZONE;
+  memset(_address.bytes, 0, sizeof(_address.bytes));
+  _address.dword[IPADDRESS_V4_DWORD_INDEX] = address;
+
+  // NOTE on conversion/comparison and uint32_t:
+  // These conversions are host platform dependent.
+  // There is a defined integer representation of IPv4 addresses,
+  // based on network byte order (will be the value on big endian systems),
+  // e.g. http://2398766798 is the same as http://142.250.70.206,
+  // However on little endian systems the octets 0x83, 0xFA, 0x46, 0xCE,
+  // in that order, will form the integer (uint32_t) 3460758158 .
 }
 
-IPAddress& IPAddress::operator=(const uint8_t *address)
-{
+IPAddress::IPAddress(const uint8_t *address) : IPAddress(IPv4, address) {}
+
+IPAddress::IPAddress(IPType ip_type, const uint8_t *address, uint8_t z) {
+  _type = ip_type;
+  if (ip_type == IPv4) {
+    memset(_address.bytes, 0, sizeof(_address.bytes));
+    memcpy(&_address.bytes[IPADDRESS_V4_BYTES_INDEX], address, sizeof(uint32_t));
+    _zone = 0;
+  } else {
     memcpy(_address.bytes, address, sizeof(_address.bytes));
-    return *this;
+    _zone = z;
+  }
+}
+
+IPAddress::IPAddress(const char *address) {
+  fromString(address);
+}
+
+IPAddress::IPAddress(const IPAddress &address) {
+  *this = address;
 }
 
-IPAddress& IPAddress::operator=(uint32_t address)
-{
-    _address.dword = address;
-    return *this;
+String IPAddress::toString(bool includeZone) const {
+  StreamString s;
+  printTo(s, includeZone);
+  return String(s);
 }
 
-bool IPAddress::operator==(const uint8_t* addr) const
-{
-    return memcmp(addr, _address.bytes, sizeof(_address.bytes)) == 0;
+bool IPAddress::fromString(const char *address) {
+  if (!fromString4(address)) {
+    return fromString6(address);
+  }
+  return true;
 }
 
-size_t IPAddress::printTo(Print& p) const
-{
-    size_t n = 0;
-    for(int i = 0; i < 3; i++) {
-        n += p.print(_address.bytes[i], DEC);
-        n += p.print('.');
+bool IPAddress::fromString4(const char *address) {
+  // TODO: add support for "a", "a.b", "a.b.c" formats
+
+  int16_t acc = -1;  // Accumulator
+  uint8_t dots = 0;
+
+  memset(_address.bytes, 0, sizeof(_address.bytes));
+  while (*address) {
+    char c = *address++;
+    if (c >= '0' && c <= '9') {
+      acc = (acc < 0) ? (c - '0') : acc * 10 + (c - '0');
+      if (acc > 255) {
+        // Value out of [0..255] range
+        return false;
+      }
+    } else if (c == '.') {
+      if (dots == 3) {
+        // Too many dots (there must be 3 dots)
+        return false;
+      }
+      if (acc < 0) {
+        /* No value between dots, e.g. '1..' */
+        return false;
+      }
+      _address.bytes[IPADDRESS_V4_BYTES_INDEX + dots++] = acc;
+      acc = -1;
+    } else {
+      // Invalid char
+      return false;
     }
-    n += p.print(_address.bytes[3], DEC);
-    return n;
+  }
+
+  if (dots != 3) {
+    // Too few dots (there must be 3 dots)
+    return false;
+  }
+  if (acc < 0) {
+    /* No value between dots, e.g. '1..' */
+    return false;
+  }
+  _address.bytes[IPADDRESS_V4_BYTES_INDEX + 3] = acc;
+  _type = IPv4;
+  return true;
+}
+
+bool IPAddress::fromString6(const char *address) {
+  uint32_t acc = 0;  // Accumulator
+  int colons = 0, double_colons = -1;
+
+  while (*address) {
+    char c = tolower(*address++);
+    if (isalnum(c) && c <= 'f') {
+      if (c >= 'a') {
+        c -= 'a' - '0' - 10;
+      }
+      acc = acc * 16 + (c - '0');
+      if (acc > 0xffff) {
+        // Value out of range
+        return false;
+      }
+    } else if (c == ':') {
+      if (*address == ':') {
+        if (double_colons >= 0) {
+          // :: allowed once
+          return false;
+        }
+        if (*address != '\0' && *(address + 1) == ':') {
+          // ::: not allowed
+          return false;
+        }
+        // remember location
+        double_colons = colons + !!acc;
+        address++;
+      } else if (*address == '\0') {
+        // can't end with a single colon
+        return false;
+      }
+      if (colons == 7) {
+        // too many separators
+        return false;
+      }
+      _address.bytes[colons * 2] = acc >> 8;
+      _address.bytes[colons * 2 + 1] = acc & 0xff;
+      colons++;
+      acc = 0;
+    } else if (c == '%') {
+      // netif_index_to_name crashes on latest esp-idf
+      // _zone = netif_name_to_index(address);
+      // in the interim, we parse the suffix as a zone number
+      while ((*address != '\0') && (!isdigit(*address))) {  // skip all non-digit after '%'
+        address++;
+      }
+      _zone = atol(address) + 1;  // increase by one by convention, so we can have zone '0'
+      while (*address != '\0') {
+        address++;
+      }
+    } else {
+      // Invalid char
+      return false;
+    }
+  }
+
+  if (double_colons == -1 && colons != 7) {
+    // Too few separators
+    return false;
+  }
+  if (double_colons > -1 && colons > 6) {
+    // Too many segments (double colon must be at least one zero field)
+    return false;
+  }
+  _address.bytes[colons * 2] = acc >> 8;
+  _address.bytes[colons * 2 + 1] = acc & 0xff;
+  colons++;
+
+  if (double_colons != -1) {
+    for (int i = colons * 2 - double_colons * 2 - 1; i >= 0; i--) {
+      _address.bytes[16 - colons * 2 + double_colons * 2 + i] = _address.bytes[double_colons * 2 + i];
+    }
+    for (int i = double_colons * 2; i < 16 - colons * 2 + double_colons * 2; i++) {
+      _address.bytes[i] = 0;
+    }
+  }
+
+  _type = IPv6;
+  return true;
+}
+
+IPAddress &IPAddress::operator=(const uint8_t *address) {
+  // IPv4 only conversion from byte pointer
+  _type = IPv4;
+  memset(_address.bytes, 0, sizeof(_address.bytes));
+  memcpy(&_address.bytes[IPADDRESS_V4_BYTES_INDEX], address, sizeof(uint32_t));
+  return *this;
 }
 
-String IPAddress::toString() const
-{
-    char szRet[16];
-    sprintf(szRet,"%u.%u.%u.%u", _address.bytes[0], _address.bytes[1], _address.bytes[2], _address.bytes[3]);
-    return String(szRet);
+IPAddress &IPAddress::operator=(const char *address) {
+  fromString(address);
+  return *this;
 }
 
-bool IPAddress::fromString(const char *address)
-{
-    // TODO: add support for "a", "a.b", "a.b.c" formats
+IPAddress &IPAddress::operator=(uint32_t address) {
+  // IPv4 conversion
+  // See note on conversion/comparison and uint32_t
+  _type = IPv4;
+  memset(_address.bytes, 0, sizeof(_address.bytes));
+  _address.dword[IPADDRESS_V4_DWORD_INDEX] = address;
+  return *this;
+}
+
+IPAddress &IPAddress::operator=(const IPAddress &address) {
+  _type = address.type();
+  _zone = address.zone();
+  memcpy(_address.bytes, address._address.bytes, sizeof(_address.bytes));
+  return *this;
+}
+
+bool IPAddress::operator==(const IPAddress &addr) const {
+  return (addr._type == _type) && (_type == IPType::IPv4 ? addr._address.dword[IPADDRESS_V4_DWORD_INDEX] == _address.dword[IPADDRESS_V4_DWORD_INDEX] : memcmp(addr._address.bytes, _address.bytes, sizeof(_address.bytes)) == 0);
+}
+
+bool IPAddress::operator==(const uint8_t *addr) const {
+  // IPv4 only comparison to byte pointer
+  // Can't support IPv6 as we know our type, but not the length of the pointer
+  return _type == IPv4 && memcmp(addr, &_address.bytes[IPADDRESS_V4_BYTES_INDEX], sizeof(uint32_t)) == 0;
+}
+
+uint8_t IPAddress::operator[](int index) const {
+  if (_type == IPv4) {
+    return _address.bytes[IPADDRESS_V4_BYTES_INDEX + index];
+  }
+  return _address.bytes[index];
+}
+
+uint8_t &IPAddress::operator[](int index) {
+  if (_type == IPv4) {
+    return _address.bytes[IPADDRESS_V4_BYTES_INDEX + index];
+  }
+  return _address.bytes[index];
+}
+
+size_t IPAddress::printTo(Print &p) const {
+  return printTo(p, false);
+}
 
-    uint16_t acc = 0; // Accumulator
-    uint8_t dots = 0;
+size_t IPAddress::printTo(Print &p, bool includeZone) const {
+  size_t n = 0;
 
-    while (*address)
-    {
-        char c = *address++;
-        if (c >= '0' && c <= '9')
-        {
-            acc = acc * 10 + (c - '0');
-            if (acc > 255) {
-                // Value out of [0..255] range
-                return false;
-            }
+  if (_type == IPv6) {
+    // IPv6 IETF canonical format: compress left-most longest run of two or more zero fields, lower case
+    int8_t longest_start = -1;
+    int8_t longest_length = 1;
+    int8_t current_start = -1;
+    int8_t current_length = 0;
+    for (int8_t f = 0; f < 8; f++) {
+      if (_address.bytes[f * 2] == 0 && _address.bytes[f * 2 + 1] == 0) {
+        if (current_start == -1) {
+          current_start = f;
+          current_length = 1;
+        } else {
+          current_length++;
+        }
+        if (current_length > longest_length) {
+          longest_start = current_start;
+          longest_length = current_length;
+        }
+      } else {
+        current_start = -1;
+      }
+    }
+    for (int f = 0; f < 8; f++) {
+      if (f < longest_start || f >= longest_start + longest_length) {
+        uint8_t c1 = _address.bytes[f * 2] >> 4;
+        uint8_t c2 = _address.bytes[f * 2] & 0xf;
+        uint8_t c3 = _address.bytes[f * 2 + 1] >> 4;
+        uint8_t c4 = _address.bytes[f * 2 + 1] & 0xf;
+        if (c1 > 0) {
+          n += p.print((char)(c1 < 10 ? '0' + c1 : 'a' + c1 - 10));
         }
-        else if (c == '.')
-        {
-            if (dots == 3) {
-                // Too much dots (there must be 3 dots)
-                return false;
-            }
-            _address.bytes[dots++] = acc;
-            acc = 0;
+        if (c1 > 0 || c2 > 0) {
+          n += p.print((char)(c2 < 10 ? '0' + c2 : 'a' + c2 - 10));
         }
-        else
-        {
-            // Invalid char
-            return false;
+        if (c1 > 0 || c2 > 0 || c3 > 0) {
+          n += p.print((char)(c3 < 10 ? '0' + c3 : 'a' + c3 - 10));
         }
+        n += p.print((char)(c4 < 10 ? '0' + c4 : 'a' + c4 - 10));
+        if (f < 7) {
+          n += p.print(':');
+        }
+      } else if (f == longest_start) {
+        if (longest_start == 0) {
+          n += p.print(':');
+        }
+        n += p.print(':');
+      }
     }
-
-    if (dots != 3) {
-        // Too few dots (there must be 3 dots)
-        return false;
+    // add a zone if zone-id is non-zero (causes exception on recent IDF builds)
+    // if (_zone > 0 && includeZone) {
+    //   n += p.print('%');
+    //   char if_name[NETIF_NAMESIZE];
+    //   netif_index_to_name(_zone, if_name);
+    //   n += p.print(if_name);
+    // }
+    // In the interim, we just output the index number
+    if (_zone > 0 && includeZone) {
+      n += p.print('%');
+      // look for the interface name
+      for (netif *intf = netif_list; intf != nullptr; intf = intf->next) {
+        if (_zone - 1 == intf->num) {
+          n += p.print(intf->name[0]);
+          n += p.print(intf->name[1]);
+          break;
+        }
+      }
+      n += p.print(_zone - 1);
     }
-    _address.bytes[3] = acc;
-    return true;
+    return n;
+  }
+
+  // IPv4
+  for (int i = 0; i < 3; i++) {
+    n += p.print(_address.bytes[IPADDRESS_V4_BYTES_INDEX + i], DEC);
+    n += p.print('.');
+  }
+  n += p.print(_address.bytes[IPADDRESS_V4_BYTES_INDEX + 3], DEC);
+  return n;
+}
+
+IPAddress::IPAddress(const ip_addr_t *addr) {
+  from_ip_addr_t(addr);
+}
+
+void IPAddress::to_ip_addr_t(ip_addr_t *addr) const {
+#if CONFIG_LWIP_IPV6
+  if (_type == IPv6) {
+    addr->type = IPADDR_TYPE_V6;
+    addr->u_addr.ip6.addr[0] = _address.dword[0];
+    addr->u_addr.ip6.addr[1] = _address.dword[1];
+    addr->u_addr.ip6.addr[2] = _address.dword[2];
+    addr->u_addr.ip6.addr[3] = _address.dword[3];
+#if LWIP_IPV6_SCOPES
+    addr->u_addr.ip6.zone = _zone;
+#endif /* LWIP_IPV6_SCOPES */
+  } else {
+    addr->type = IPADDR_TYPE_V4;
+    addr->u_addr.ip4.addr = _address.dword[IPADDRESS_V4_DWORD_INDEX];
+  }
+#else
+  addr->addr = _address.dword[IPADDRESS_V4_DWORD_INDEX];
+#endif
+}
+
+IPAddress &IPAddress::from_ip_addr_t(const ip_addr_t *addr) {
+#if CONFIG_LWIP_IPV6
+  if (addr->type == IPADDR_TYPE_V6) {
+    _type = IPv6;
+    _address.dword[0] = addr->u_addr.ip6.addr[0];
+    _address.dword[1] = addr->u_addr.ip6.addr[1];
+    _address.dword[2] = addr->u_addr.ip6.addr[2];
+    _address.dword[3] = addr->u_addr.ip6.addr[3];
+#if LWIP_IPV6_SCOPES
+    _zone = addr->u_addr.ip6.zone;
+#endif /* LWIP_IPV6_SCOPES */
+  } else {
+#endif
+    _type = IPv4;
+    memset(_address.bytes, 0, sizeof(_address.bytes));
+#if CONFIG_LWIP_IPV6
+    _address.dword[IPADDRESS_V4_DWORD_INDEX] = addr->u_addr.ip4.addr;
+#else
+  _address.dword[IPADDRESS_V4_DWORD_INDEX] = addr->addr;
+#endif
+#if CONFIG_LWIP_IPV6
+  }
+#endif
+  return *this;
+}
+
+#if CONFIG_LWIP_IPV6
+esp_ip6_addr_type_t IPAddress::addr_type() const {
+  if (_type != IPv6) {
+    return ESP_IP6_ADDR_IS_UNKNOWN;
+  }
+  ip_addr_t addr;
+  to_ip_addr_t(&addr);
+  return esp_netif_ip6_get_addr_type((esp_ip6_addr_t *)(&(addr.u_addr.ip6)));
 }
+#endif
+
+#if CONFIG_LWIP_IPV6
+const IPAddress IN6ADDR_ANY(IPv6);
+#endif
+const IPAddress INADDR_NONE(0, 0, 0, 0);
diff --git a/cores/esp32/IPAddress.h b/cores/esp32/IPAddress.h
index aa1d10cee29..923f4dd5ca6 100644
--- a/cores/esp32/IPAddress.h
+++ b/cores/esp32/IPAddress.h
@@ -1,96 +1,140 @@
 /*
- IPAddress.h - Base class that provides IPAddress
- Copyright (c) 2011 Adrian McEwen.  All right reserved.
+  IPAddress.h - Base class that provides IPAddress
+  Copyright (c) 2011 Adrian McEwen.  All right reserved.
 
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
 
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
 
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
 
-#ifndef IPAddress_h
-#define IPAddress_h
+#pragma once
 
 #include <stdint.h>
-#include <WString.h>
-#include <Printable.h>
+#include "Printable.h"
+#include "WString.h"
+#include "lwip/ip_addr.h"
+#include "esp_netif_ip_addr.h"
+#include "sdkconfig.h"
+
+#define IPADDRESS_V4_BYTES_INDEX 12
+#define IPADDRESS_V4_DWORD_INDEX 3
 
 // A class to make it easier to handle and pass around IP addresses
 
-class IPAddress: public Printable
-{
+enum IPType {
+  IPv4,
+  IPv6
+};
+
+class IPAddress : public Printable {
 private:
-    union {
-        uint8_t bytes[4];  // IPv4 address
-        uint32_t dword;
-    } _address;
-
-    // Access the raw byte array containing the address.  Because this returns a pointer
-    // to the internal structure rather than a copy of the address this function should only
-    // be used when you know that the usage of the returned uint8_t* will be transient and not
-    // stored.
-    uint8_t* raw_address()
-    {
-        return _address.bytes;
-    }
+  union {
+    uint8_t bytes[16];
+    uint32_t dword[4];
+  } _address;
+  IPType _type;
+  uint8_t _zone;
+
+  // Access the raw byte array containing the address.  Because this returns a pointer
+  // to the internal structure rather than a copy of the address this function should only
+  // be used when you know that the usage of the returned uint8_t* will be transient and not
+  // stored.
+  uint8_t *raw_address() {
+    return _type == IPv4 ? &_address.bytes[IPADDRESS_V4_BYTES_INDEX] : _address.bytes;
+  }
 
 public:
-    // Constructors
-    IPAddress();
-    IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet);
-    IPAddress(uint32_t address);
-    IPAddress(const uint8_t *address);
-    virtual ~IPAddress() {}
-
-    bool fromString(const char *address);
-    bool fromString(const String &address) { return fromString(address.c_str()); }
-
-    // Overloaded cast operator to allow IPAddress objects to be used where a pointer
-    // to a four-byte uint8_t array is expected
-    operator uint32_t() const
-    {
-        return _address.dword;
-    }
-    bool operator==(const IPAddress& addr) const
-    {
-        return _address.dword == addr._address.dword;
-    }
-    bool operator==(const uint8_t* addr) const;
-
-    // Overloaded index operator to allow getting and setting individual octets of the address
-    uint8_t operator[](int index) const
-    {
-        return _address.bytes[index];
-    }
-    uint8_t& operator[](int index)
-    {
-        return _address.bytes[index];
-    }
-
-    // Overloaded copy operators to allow initialisation of IPAddress objects from other types
-    IPAddress& operator=(const uint8_t *address);
-    IPAddress& operator=(uint32_t address);
-
-    virtual size_t printTo(Print& p) const;
-    String toString() const;
-
-    friend class EthernetClass;
-    friend class UDP;
-    friend class Client;
-    friend class Server;
-    friend class DhcpClass;
-    friend class DNSClient;
+  // Constructors
+
+  // Default IPv4
+  IPAddress();
+  IPAddress(IPType ip_type);
+  IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet);
+  IPAddress(
+    uint8_t o1, uint8_t o2, uint8_t o3, uint8_t o4, uint8_t o5, uint8_t o6, uint8_t o7, uint8_t o8, uint8_t o9, uint8_t o10, uint8_t o11, uint8_t o12,
+    uint8_t o13, uint8_t o14, uint8_t o15, uint8_t o16, uint8_t z = 0
+  );
+  // IPv4; see implementation note
+  IPAddress(uint32_t address);
+  // Default IPv4
+  IPAddress(const uint8_t *address);
+  IPAddress(IPType ip_type, const uint8_t *address, uint8_t z = 0);
+  // If IPv4 fails tries IPv6 see fromString function
+  IPAddress(const char *address);
+  IPAddress(const IPAddress &address);
+
+  bool fromString(const char *address);
+  bool fromString(const String &address) {
+    return fromString(address.c_str());
+  }
+
+  // Overloaded cast operator to allow IPAddress objects to be used where a uint32_t is expected
+  // NOTE: IPv4 only; see implementation note
+  operator uint32_t() const {
+    return _type == IPv4 ? _address.dword[IPADDRESS_V4_DWORD_INDEX] : 0;
+  };
+
+  bool operator==(const IPAddress &addr) const;
+  bool operator!=(const IPAddress &addr) const {
+    return !(*this == addr);
+  };
+
+  // NOTE: IPv4 only; we don't know the length of the pointer
+  bool operator==(const uint8_t *addr) const;
+
+  // Overloaded index operator to allow getting and setting individual octets of the address
+  uint8_t operator[](int index) const;
+  uint8_t &operator[](int index);
+
+  // Overloaded copy operators to allow initialization of IPAddress objects from other types
+  // NOTE: IPv4 only
+  IPAddress &operator=(const uint8_t *address);
+  // NOTE: IPv4 only; see implementation note
+  IPAddress &operator=(uint32_t address);
+  // If IPv4 fails tries IPv6 see fromString function
+  IPAddress &operator=(const char *address);
+  IPAddress &operator=(const IPAddress &address);
+
+  virtual size_t printTo(Print &p) const;
+  String toString(bool includeZone = false) const;
+
+  IPType type() const {
+    return _type;
+  }
+
+  // Espresif LwIP conversions
+  IPAddress(const ip_addr_t *addr);
+  void to_ip_addr_t(ip_addr_t *addr) const;
+  IPAddress &from_ip_addr_t(const ip_addr_t *addr);
+#if CONFIG_LWIP_IPV6
+  esp_ip6_addr_type_t addr_type() const;
+#endif
+  uint8_t zone() const {
+    return (type() == IPv6) ? _zone : 0;
+  }
+  size_t printTo(Print &p, bool includeZone) const;
+
+  friend class UDP;
+  friend class Client;
+  friend class Server;
+  friend class EthernetClass;
+  friend class DhcpClass;
+  friend class DNSClient;
+
+protected:
+  bool fromString4(const char *address);
+  bool fromString6(const char *address);
 };
 
-const IPAddress INADDR_NONE(0, 0, 0, 0);
-
-#endif
+extern const IPAddress IN6ADDR_ANY;
+extern const IPAddress INADDR_NONE;
diff --git a/cores/esp32/IPv6Address.cpp b/cores/esp32/IPv6Address.cpp
deleted file mode 100644
index 7d3c0de5f53..00000000000
--- a/cores/esp32/IPv6Address.cpp
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- IPv6Address.cpp - Base class that provides IPv6Address
- Copyright (c) 2011 Adrian McEwen.  All right reserved.
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <Arduino.h>
-#include <IPv6Address.h>
-#include <Print.h>
-
-IPv6Address::IPv6Address()
-{
-    memset(_address.bytes, 0, sizeof(_address.bytes));
-}
-
-IPv6Address::IPv6Address(const uint8_t *address)
-{
-    memcpy(_address.bytes, address, sizeof(_address.bytes));
-}
-
-IPv6Address::IPv6Address(const uint32_t *address)
-{
-    memcpy(_address.bytes, (const uint8_t *)address, sizeof(_address.bytes));
-}
-
-IPv6Address& IPv6Address::operator=(const uint8_t *address)
-{
-    memcpy(_address.bytes, address, sizeof(_address.bytes));
-    return *this;
-}
-
-bool IPv6Address::operator==(const uint8_t* addr) const
-{
-    return memcmp(addr, _address.bytes, sizeof(_address.bytes)) == 0;
-}
-
-size_t IPv6Address::printTo(Print& p) const
-{
-    size_t n = 0;
-    for(int i = 0; i < 16; i+=2) {
-        if(i){
-            n += p.print(':');
-        }
-        n += p.printf("%02x", _address.bytes[i]);
-        n += p.printf("%02x", _address.bytes[i+1]);
-
-    }
-    return n;
-}
-
-String IPv6Address::toString() const
-{
-    char szRet[40];
-    sprintf(szRet,"%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x",
-            _address.bytes[0], _address.bytes[1], _address.bytes[2], _address.bytes[3],
-            _address.bytes[4], _address.bytes[5], _address.bytes[6], _address.bytes[7],
-            _address.bytes[8], _address.bytes[9], _address.bytes[10], _address.bytes[11],
-            _address.bytes[12], _address.bytes[13], _address.bytes[14], _address.bytes[15]);
-    return String(szRet);
-}
-
-bool IPv6Address::fromString(const char *address)
-{
-    //format 0011:2233:4455:6677:8899:aabb:ccdd:eeff
-    if(strlen(address) != 39){
-        return false;
-    }
-    char * pos = (char *)address;
-    size_t i = 0;
-    for(i = 0; i < 16; i+=2) {
-        if(!sscanf(pos, "%2hhx", &_address.bytes[i]) || !sscanf(pos+2, "%2hhx", &_address.bytes[i+1])){
-            return false;
-        }
-        pos += 5;
-    }
-    return true;
-}
diff --git a/cores/esp32/IPv6Address.h b/cores/esp32/IPv6Address.h
deleted file mode 100644
index e61d0e7b371..00000000000
--- a/cores/esp32/IPv6Address.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- IPv6Address.h - Base class that provides IPv6Address
- Copyright (c) 2011 Adrian McEwen.  All right reserved.
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef IPv6Address_h
-#define IPv6Address_h
-
-#include <stdint.h>
-#include <WString.h>
-#include <Printable.h>
-
-// A class to make it easier to handle and pass around IP addresses
-
-class IPv6Address: public Printable
-{
-private:
-    union {
-        uint8_t bytes[16];  // IPv4 address
-        uint32_t dword[4];
-    } _address;
-
-    // Access the raw byte array containing the address.  Because this returns a pointer
-    // to the internal structure rather than a copy of the address this function should only
-    // be used when you know that the usage of the returned uint8_t* will be transient and not
-    // stored.
-    uint8_t* raw_address()
-    {
-        return _address.bytes;
-    }
-
-public:
-    // Constructors
-    IPv6Address();
-    IPv6Address(const uint8_t *address);
-    IPv6Address(const uint32_t *address);
-    virtual ~IPv6Address() {}
-
-    bool fromString(const char *address);
-    bool fromString(const String &address) { return fromString(address.c_str()); }
-
-    operator const uint8_t*() const
-    {
-        return _address.bytes;
-    }
-    operator const uint32_t*() const
-    {
-        return _address.dword;
-    }
-    bool operator==(const IPv6Address& addr) const
-    {
-        return (_address.dword[0] == addr._address.dword[0])
-            && (_address.dword[1] == addr._address.dword[1])
-            && (_address.dword[2] == addr._address.dword[2])
-            && (_address.dword[3] == addr._address.dword[3]);
-    }
-    bool operator==(const uint8_t* addr) const;
-
-    // Overloaded index operator to allow getting and setting individual octets of the address
-    uint8_t operator[](int index) const
-    {
-        return _address.bytes[index];
-    }
-    uint8_t& operator[](int index)
-    {
-        return _address.bytes[index];
-    }
-
-    // Overloaded copy operators to allow initialisation of IPv6Address objects from other types
-    IPv6Address& operator=(const uint8_t *address);
-
-    virtual size_t printTo(Print& p) const;
-    String toString() const;
-
-    friend class UDP;
-    friend class Client;
-    friend class Server;
-};
-
-#endif
diff --git a/cores/esp32/MD5Builder.cpp b/cores/esp32/MD5Builder.cpp
index f2168f4e6c4..cd8aa31b6cc 100644
--- a/cores/esp32/MD5Builder.cpp
+++ b/cores/esp32/MD5Builder.cpp
@@ -1,7 +1,7 @@
-/* 
+/*
   Copyright (c) 2015 Hristo Gochkov. All rights reserved.
   This file is part of the esp8266 core for Arduino environment.
- 
+
   This library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
@@ -16,102 +16,84 @@
   License along with this library; if not, write to the Free Software
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
+
 #include <Arduino.h>
+#include <HEXBuilder.h>
 #include <MD5Builder.h>
 
-uint8_t hex_char_to_byte(uint8_t c)
-{
-    return  (c >= 'a' && c <= 'f') ? (c - ((uint8_t)'a' - 0xa)) :
-            (c >= 'A' && c <= 'F') ? (c - ((uint8_t)'A' - 0xA)) :
-            (c >= '0' &&  c<= '9') ? (c - (uint8_t)'0') : 0;
+void MD5Builder::begin(void) {
+  memset(_buf, 0x00, ESP_ROM_MD5_DIGEST_LEN);
+  esp_rom_md5_init(&_ctx);
 }
 
-void MD5Builder::begin(void)
-{
-    memset(_buf, 0x00, 16);
-    MD5Init(&_ctx);
+void MD5Builder::add(const uint8_t *data, size_t len) {
+  esp_rom_md5_update(&_ctx, data, len);
 }
 
-void MD5Builder::add(uint8_t * data, uint16_t len)
-{
-    MD5Update(&_ctx, data, len);
+void MD5Builder::addHexString(const char *data) {
+  size_t len = strlen(data);
+  uint8_t *tmp = (uint8_t *)malloc(len / 2);
+  if (tmp == NULL) {
+    return;
+  }
+  hex2bytes(tmp, len / 2, data);
+  add(tmp, len / 2);
+  free(tmp);
 }
 
-void MD5Builder::addHexString(const char * data)
-{
-    uint16_t i, len = strlen(data);
-    uint8_t * tmp = (uint8_t*)malloc(len/2);
-    if(tmp == NULL) {
-        return;
-    }
-    for(i=0; i<len; i+=2) {
-        uint8_t high = hex_char_to_byte(data[i]);
-        uint8_t low = hex_char_to_byte(data[i+1]);
-        tmp[i/2] = (high & 0x0F) << 4 | (low & 0x0F);
-    }
-    add(tmp, len/2);
-    free(tmp);
-}
+bool MD5Builder::addStream(Stream &stream, const size_t maxLen) {
+  const int buf_size = 512;
+  int maxLengthLeft = maxLen;
+  uint8_t *buf = (uint8_t *)malloc(buf_size);
 
-bool MD5Builder::addStream(Stream & stream, const size_t maxLen)
-{
-    const int buf_size = 512;
-    int maxLengthLeft = maxLen;
-    uint8_t * buf = (uint8_t*) malloc(buf_size);
+  if (!buf) {
+    return false;
+  }
 
-    if(!buf) {
-        return false;
+  int bytesAvailable = stream.available();
+  while ((bytesAvailable > 0) && (maxLengthLeft > 0)) {
+
+    // determine number of bytes to read
+    int readBytes = bytesAvailable;
+    if (readBytes > maxLengthLeft) {
+      readBytes = maxLengthLeft;  // read only until max_len
+    }
+    if (readBytes > buf_size) {
+      readBytes = buf_size;  // not read more the buffer can handle
     }
 
-    int bytesAvailable = stream.available();
-    while((bytesAvailable > 0) && (maxLengthLeft > 0)) {
-
-        // determine number of bytes to read
-        int readBytes = bytesAvailable;
-        if(readBytes > maxLengthLeft) {
-            readBytes = maxLengthLeft ;    // read only until max_len
-        }
-        if(readBytes > buf_size) {
-            readBytes = buf_size;    // not read more the buffer can handle
-        }
-
-        // read data and check if we got something
-        int numBytesRead = stream.readBytes(buf, readBytes);
-        if(numBytesRead< 1) {
-            return false;
-        }
-
-        // Update MD5 with buffer payload
-        MD5Update(&_ctx, buf, numBytesRead);
-
-        // update available number of bytes
-        maxLengthLeft -= numBytesRead;
-        bytesAvailable = stream.available();
+    // read data and check if we got something
+    int numBytesRead = stream.readBytes(buf, readBytes);
+    if (numBytesRead < 1) {
+      free(buf);
+      return false;
     }
-    free(buf);
-    return true;
+
+    // Update MD5 with buffer payload
+    esp_rom_md5_update(&_ctx, buf, numBytesRead);
+
+    // update available number of bytes
+    maxLengthLeft -= numBytesRead;
+    bytesAvailable = stream.available();
+  }
+  free(buf);
+  return true;
 }
 
-void MD5Builder::calculate(void)
-{
-    MD5Final(_buf, &_ctx);
+void MD5Builder::calculate(void) {
+  esp_rom_md5_final(_buf, &_ctx);
 }
 
-void MD5Builder::getBytes(uint8_t * output)
-{
-    memcpy(output, _buf, 16);
+void MD5Builder::getBytes(uint8_t *output) {
+  memcpy(output, _buf, ESP_ROM_MD5_DIGEST_LEN);
 }
 
-void MD5Builder::getChars(char * output)
-{
-    for(uint8_t i = 0; i < 16; i++) {
-        sprintf(output + (i * 2), "%02x", _buf[i]);
-    }
+void MD5Builder::getChars(char *output) {
+  bytes2hex(output, ESP_ROM_MD5_DIGEST_LEN * 2 + 1, _buf, ESP_ROM_MD5_DIGEST_LEN);
 }
 
-String MD5Builder::toString(void)
-{
-    char out[33];
-    getChars(out);
-    return String(out);
+String MD5Builder::toString(void) {
+  char out[(ESP_ROM_MD5_DIGEST_LEN * 2) + 1];
+  getChars(out);
+  return String(out);
 }
diff --git a/cores/esp32/MD5Builder.h b/cores/esp32/MD5Builder.h
index 5429d9aea60..5728bd3bac0 100644
--- a/cores/esp32/MD5Builder.h
+++ b/cores/esp32/MD5Builder.h
@@ -1,7 +1,7 @@
-/* 
+/*
   Copyright (c) 2015 Hristo Gochkov. All rights reserved.
-  This file is part of the esp8266 core for Arduino environment.
- 
+  This file is part of the esp32 core for Arduino environment.
+
   This library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
@@ -15,49 +15,39 @@
   You should have received a copy of the GNU Lesser General Public
   License along with this library; if not, write to the Free Software
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+
+  Modified 10 Jan 2024 by Lucas Saavedra Vaz (Use abstract class HashBuilder)
 */
-#ifndef __ESP8266_MD5_BUILDER__
-#define __ESP8266_MD5_BUILDER__
+#ifndef MD5Builder_h
+#define MD5Builder_h
 
 #include <WString.h>
 #include <Stream.h>
-#include "rom/md5_hash.h"
 
-class MD5Builder
-{
+#include "esp_system.h"
+#include "esp_rom_md5.h"
+
+#include "HashBuilder.h"
+
+class MD5Builder : public HashBuilder {
 private:
-    struct MD5Context _ctx;
-    uint8_t _buf[16];
+  md5_context_t _ctx;
+  uint8_t _buf[ESP_ROM_MD5_DIGEST_LEN];
+
 public:
-    void begin(void);
-    void add(uint8_t * data, uint16_t len);
-    void add(const char * data)
-    {
-        add((uint8_t*)data, strlen(data));
-    }
-    void add(char * data)
-    {
-        add((const char*)data);
-    }
-    void add(String data)
-    {
-        add(data.c_str());
-    }
-    void addHexString(const char * data);
-    void addHexString(char * data)
-    {
-        addHexString((const char*)data);
-    }
-    void addHexString(String data)
-    {
-        addHexString(data.c_str());
-    }
-    bool addStream(Stream & stream, const size_t maxLen);
-    void calculate(void);
-    void getBytes(uint8_t * output);
-    void getChars(char * output);
-    String toString(void);
-};
+  void begin(void) override;
+
+  using HashBuilder::add;
+  void add(const uint8_t *data, size_t len) override;
 
+  using HashBuilder::addHexString;
+  void addHexString(const char *data) override;
+
+  bool addStream(Stream &stream, const size_t maxLen) override;
+  void calculate(void) override;
+  void getBytes(uint8_t *output) override;
+  void getChars(char *output) override;
+  String toString(void) override;
+};
 
 #endif
diff --git a/cores/esp32/MacAddress.cpp b/cores/esp32/MacAddress.cpp
new file mode 100644
index 00000000000..8b4fab1781a
--- /dev/null
+++ b/cores/esp32/MacAddress.cpp
@@ -0,0 +1,228 @@
+#include <MacAddress.h>
+#include <stdio.h>
+#include <Print.h>
+
+//Default constructor, blank mac address.
+MacAddress::MacAddress() : MacAddress(MAC6) {}
+
+MacAddress::MacAddress(MACType mac_type) {
+  _type = mac_type;
+  memset(_mac.bytes, 0, sizeof(_mac.bytes));
+}
+MacAddress::MacAddress(MACType mac_type, uint64_t mac) {
+  _type = mac_type;
+  _mac.val = mac;
+}
+
+MacAddress::MacAddress(MACType mac_type, const uint8_t *macbytearray) {
+  _type = mac_type;
+  memset(_mac.bytes, 0, sizeof(_mac.bytes));
+  if (_type == MAC6) {
+    memcpy(_mac.bytes, macbytearray, 6);
+  } else {
+    memcpy(_mac.bytes, macbytearray, 8);
+  }
+}
+
+MacAddress::MacAddress(const char *macstr) {
+  fromString(macstr);
+}
+
+MacAddress::MacAddress(const String &macstr) {
+  fromString(macstr.c_str());
+}
+
+MacAddress::MacAddress(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint8_t b6) {
+  _type = MAC6;
+  memset(_mac.bytes, 0, sizeof(_mac.bytes));
+  _mac.bytes[0] = b1;
+  _mac.bytes[1] = b2;
+  _mac.bytes[2] = b3;
+  _mac.bytes[3] = b4;
+  _mac.bytes[4] = b5;
+  _mac.bytes[5] = b6;
+}
+
+MacAddress::MacAddress(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint8_t b6, uint8_t b7, uint8_t b8) {
+  _type = MAC8;
+  _mac.bytes[0] = b1;
+  _mac.bytes[1] = b2;
+  _mac.bytes[2] = b3;
+  _mac.bytes[3] = b4;
+  _mac.bytes[4] = b5;
+  _mac.bytes[5] = b6;
+  _mac.bytes[6] = b7;
+  _mac.bytes[7] = b8;
+}
+
+//Parse user entered string into MAC address
+bool MacAddress::fromString(const char *buf) {
+  if (strlen(buf) == 17) {
+    return fromString6(buf);
+  } else if (strlen(buf) == 23) {
+    return fromString8(buf);
+  }
+  return false;
+}
+
+//Parse user entered string into MAC address
+bool MacAddress::fromString6(const char *buf) {
+  char cs[18];  // 17 + 1 for null terminator
+  char *token;
+  char *next;  //Unused but required
+  int i;
+
+  strncpy(cs, buf, sizeof(cs) - 1);  //strtok modifies the buffer: copy to working buffer.
+
+  for (i = 0; i < 6; i++) {
+    token = strtok((i == 0) ? cs : NULL, ":");  //Find first or next token
+    if (!token) {                               //No more tokens found
+      return false;
+    }
+    _mac.bytes[i] = strtol(token, &next, 16);
+  }
+  _type = MAC6;
+  return true;
+}
+
+bool MacAddress::fromString8(const char *buf) {
+  char cs[24];  // 23 + 1 for null terminator
+  char *token;
+  char *next;  //Unused but required
+  int i;
+
+  strncpy(cs, buf, sizeof(cs) - 1);  //strtok modifies the buffer: copy to working buffer.
+
+  for (i = 0; i < 8; i++) {
+    token = strtok((i == 0) ? cs : NULL, ":");  //Find first or next token
+    if (!token) {                               //No more tokens found
+      return false;
+    }
+    _mac.bytes[i] = strtol(token, &next, 16);
+  }
+  _type = MAC8;
+  return true;
+}
+
+//Copy MAC into byte array
+void MacAddress::toBytes(uint8_t *buf) {
+  if (_type == MAC6) {
+    memcpy(buf, _mac.bytes, 6);
+  } else {
+    memcpy(buf, _mac.bytes, sizeof(_mac.bytes));
+  }
+}
+
+//Print MAC address into a C string.
+//MAC: Buffer must be at least 18 chars
+int MacAddress::toString(char *buf) {
+  if (_type == MAC6) {
+    return sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", _mac.bytes[0], _mac.bytes[1], _mac.bytes[2], _mac.bytes[3], _mac.bytes[4], _mac.bytes[5]);
+  } else {
+    return sprintf(
+      buf, "%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X", _mac.bytes[0], _mac.bytes[1], _mac.bytes[2], _mac.bytes[3], _mac.bytes[4], _mac.bytes[5], _mac.bytes[6],
+      _mac.bytes[7]
+    );
+  }
+}
+
+String MacAddress::toString() const {
+  uint8_t bytes = (_type == MAC6) ? 18 : 24;
+  char buf[bytes];
+  if (_type == MAC6) {
+    snprintf(buf, sizeof(buf), "%02X:%02X:%02X:%02X:%02X:%02X", _mac.bytes[0], _mac.bytes[1], _mac.bytes[2], _mac.bytes[3], _mac.bytes[4], _mac.bytes[5]);
+  } else {
+    snprintf(
+      buf, sizeof(buf), "%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X", _mac.bytes[0], _mac.bytes[1], _mac.bytes[2], _mac.bytes[3], _mac.bytes[4], _mac.bytes[5],
+      _mac.bytes[6], _mac.bytes[7]
+    );
+  }
+  return String(buf);
+}
+
+uint64_t MacAddress::Value() {
+  return _mac.val;
+}
+
+//Allow getting individual octets of the address. e.g. uint8_t b0 = ma[0];
+uint8_t MacAddress::operator[](int index) const {
+  index = EnforceIndexBounds(index);
+  return _mac.bytes[index];
+}
+
+//Allow setting individual octets of the address. e.g. ma[2] = 255;
+uint8_t &MacAddress::operator[](int index) {
+  index = EnforceIndexBounds(index);
+  return _mac.bytes[index];
+}
+
+//Overloaded copy operator: init MacAddress object from byte array
+MacAddress &MacAddress::operator=(const uint8_t *macbytearray) {
+  // 6-bytes MacAddress only
+  _type = MAC6;
+  memset(_mac.bytes, 0, sizeof(_mac.bytes));
+  memcpy(_mac.bytes, macbytearray, 6);
+  return *this;
+}
+
+//Overloaded copy operator: init MacAddress object from uint64_t
+MacAddress &MacAddress::operator=(uint64_t macval) {
+  // 6-bytes MacAddress only
+  _type = MAC6;
+  _mac.val = macval;
+  return *this;
+}
+
+//Compare class to byte array
+bool MacAddress::operator==(const uint8_t *macbytearray) const {
+  return !memcmp(_mac.bytes, macbytearray, 6);
+}
+
+//Allow comparing value of two classes
+bool MacAddress::operator==(const MacAddress &mac2) const {
+  return _mac.val == mac2._mac.val;
+}
+
+//Type converter object to uint64_t [same as .Value()]
+MacAddress::operator uint64_t() const {
+  return _mac.val;
+}
+
+//Type converter object to read only pointer to mac bytes. e.g. const uint8_t *ip_8 = ma;
+MacAddress::operator const uint8_t *() const {
+  return _mac.bytes;
+}
+
+//Type converter object to read only pointer to mac value. e.g. const uint32_t *ip_64 = ma;
+MacAddress::operator const uint64_t *() const {
+  return &_mac.val;
+}
+
+size_t MacAddress::printTo(Print &p) const {
+  uint8_t bytes = (_type == MAC6) ? 6 : 8;
+  size_t n = 0;
+  for (int i = 0; i < bytes; i++) {
+    if (i) {
+      n += p.print(':');
+    }
+    n += p.printf("%02X", _mac.bytes[i]);
+  }
+  return n;
+}
+
+//Bounds checking
+int MacAddress::EnforceIndexBounds(int i) const {
+  if (i < 0) {
+    return 0;
+  }
+  if (_type == MAC6) {
+    if (i >= 6) {
+      return 5;
+    }
+  } else {
+    if (i >= 8) {
+      return 7;
+    }
+  }
+  return i;
+}
diff --git a/cores/esp32/MacAddress.h b/cores/esp32/MacAddress.h
new file mode 100644
index 00000000000..5b42649c774
--- /dev/null
+++ b/cores/esp32/MacAddress.h
@@ -0,0 +1,104 @@
+//-----------------------------------------------------------------------------
+// MacAddress.h - class to make it easier to handle BSSID and MAC addresses.
+//
+// Copyright 2022 David McCurley
+// Modified by Espressif Systems 2024
+//
+// Licensed under the Apache License, Version 2.0 (the "License").
+// You may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+//   distributed under the License is distributed on an "AS IS" BASIS,
+//   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+//   limitations under the License.
+//-----------------------------------------------------------------------------
+
+#ifndef MacAddress_h
+#define MacAddress_h
+
+#include <stdint.h>
+#include <WString.h>
+#include <Printable.h>
+
+enum MACType {
+  MAC6,
+  MAC8
+};
+
+// A class to make it easier to handle and pass around MAC addresses, supporting both 6-byte and 8-byte MAC addresses.
+class MacAddress : public Printable {
+private:
+  union {
+    uint8_t bytes[8];
+    uint64_t val;
+  } _mac;
+  MACType _type;
+
+public:
+  //Default MAC6
+  MacAddress();
+
+  MacAddress(MACType mac_type);
+  MacAddress(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint8_t b6);
+  MacAddress(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5, uint8_t b6, uint8_t b7, uint8_t b8);
+
+  MacAddress(MACType mac_type, uint64_t mac);
+  MacAddress(MACType mac_type, const uint8_t *macbytearray);
+
+  //Default MAC6
+  MacAddress(uint64_t mac) : MacAddress(MAC6, mac) {}
+  MacAddress(const uint8_t *macbytearray) : MacAddress(MAC6, macbytearray) {}
+
+  MacAddress(const char *macstr);
+  MacAddress(const String &macstr);
+
+  virtual ~MacAddress() {}
+
+  bool fromString(const char *buf);
+  bool fromString(const String &macstr) {
+    return fromString(macstr.c_str());
+  }
+
+  void toBytes(uint8_t *buf);
+  int toString(char *buf);
+  String toString() const;
+  uint64_t Value();
+
+  uint8_t operator[](int index) const;
+  uint8_t &operator[](int index);
+
+  //MAC6 only
+  MacAddress &operator=(const uint8_t *macbytearray);
+  MacAddress &operator=(uint64_t macval);
+
+  bool operator==(const uint8_t *macbytearray) const;
+  bool operator==(const MacAddress &mac2) const;
+  operator uint64_t() const;
+  operator const uint8_t *() const;
+  operator const uint64_t *() const;
+
+  virtual size_t printTo(Print &p) const;
+
+  // future use in Arduino Networking
+  /*
+    friend class EthernetClass;
+    friend class UDP;
+    friend class Client;
+    friend class Server;
+    friend class DhcpClass;
+    friend class DNSClient;
+    */
+
+protected:
+  bool fromString6(const char *buf);
+  bool fromString8(const char *buf);
+
+private:
+  int EnforceIndexBounds(int i) const;
+};
+
+#endif
diff --git a/cores/esp32/Print.cpp b/cores/esp32/Print.cpp
index 3636d99e658..53780d55abd 100644
--- a/cores/esp32/Print.cpp
+++ b/cores/esp32/Print.cpp
@@ -29,346 +29,317 @@
 
 #include "Print.h"
 extern "C" {
-    #include "time.h"
+#include "time.h"
 }
 
 // Public Methods //////////////////////////////////////////////////////////////
 
 /* default implementation: may be overridden */
-size_t Print::write(const uint8_t *buffer, size_t size)
-{
-    size_t n = 0;
-    while(size--) {
-        n += write(*buffer++);
-    }
-    return n;
-}
-
-size_t Print::printf(const char *format, ...)
-{
-    char loc_buf[64];
-    char * temp = loc_buf;
-    va_list arg;
-    va_list copy;
-    va_start(arg, format);
-    va_copy(copy, arg);
-    int len = vsnprintf(temp, sizeof(loc_buf), format, copy);
-    va_end(copy);
-    if(len < 0) {
-        va_end(arg);
-        return 0;
-    };
-    if(len >= sizeof(loc_buf)){
-        temp = (char*) malloc(len+1);
-        if(temp == NULL) {
-            va_end(arg);
-            return 0;
-        }
-        len = vsnprintf(temp, len+1, format, arg);
-    }
+size_t Print::write(const uint8_t *buffer, size_t size) {
+  size_t n = 0;
+  while (size--) {
+    n += write(*buffer++);
+  }
+  return n;
+}
+
+size_t Print::vprintf(const char *format, va_list arg) {
+  char loc_buf[64];
+  char *temp = loc_buf;
+  va_list copy;
+  va_copy(copy, arg);
+  int len = vsnprintf(temp, sizeof(loc_buf), format, copy);
+  va_end(copy);
+  if (len < 0) {
     va_end(arg);
-    len = write((uint8_t*)temp, len);
-    if(temp != loc_buf){
-        free(temp);
+    return 0;
+  }
+  if (len >= (int)sizeof(loc_buf)) {  // comparison of same sign type for the compiler
+    temp = (char *)malloc(len + 1);
+    if (temp == NULL) {
+      va_end(arg);
+      return 0;
     }
-    return len;
+    len = vsnprintf(temp, len + 1, format, arg);
+  }
+  va_end(arg);
+  len = write((uint8_t *)temp, len);
+  if (temp != loc_buf) {
+    free(temp);
+  }
+  return len;
 }
 
-size_t Print::print(const __FlashStringHelper *ifsh)
-{
-    return print(reinterpret_cast<const char *>(ifsh));
+size_t Print::printf(const __FlashStringHelper *ifsh, ...) {
+  va_list arg;
+  va_start(arg, ifsh);
+  const char *format = (reinterpret_cast<const char *>(ifsh));
+  size_t ret = vprintf(format, arg);
+  va_end(arg);
+  return ret;
 }
 
-size_t Print::print(const String &s)
-{
-    return write(s.c_str(), s.length());
+size_t Print::printf(const char *format, ...) {
+  va_list arg;
+  va_start(arg, format);
+  size_t ret = vprintf(format, arg);
+  va_end(arg);
+  return ret;
 }
 
-size_t Print::print(const char str[])
-{
-    return write(str);
+size_t Print::print(const String &s) {
+  return write(s.c_str(), s.length());
 }
 
-size_t Print::print(char c)
-{
-    return write(c);
+size_t Print::print(const char str[]) {
+  return write(str);
 }
 
-size_t Print::print(unsigned char b, int base)
-{
-    return print((unsigned long) b, base);
+size_t Print::print(char c) {
+  return write(c);
 }
 
-size_t Print::print(int n, int base)
-{
-    return print((long) n, base);
+size_t Print::print(unsigned char b, int base) {
+  return print((unsigned long)b, base);
 }
 
-size_t Print::print(unsigned int n, int base)
-{
-    return print((unsigned long) n, base);
+size_t Print::print(int n, int base) {
+  return print((long)n, base);
 }
 
-size_t Print::print(long n, int base)
-{
-    int t = 0;
-    if (base == 10 && n < 0) {
-        t = print('-');
-        n = -n;
-    }
-    return printNumber(static_cast<unsigned long>(n), base) + t;
+size_t Print::print(unsigned int n, int base) {
+  return print((unsigned long)n, base);
 }
 
-size_t Print::print(unsigned long n, int base)
-{
-    if(base == 0) {
-        return write(n);
-    } else {
-        return printNumber(n, base);
-    }
+size_t Print::print(long n, int base) {
+  int t = 0;
+  if (base == 10 && n < 0) {
+    t = print('-');
+    n = -n;
+  }
+  return printNumber(static_cast<unsigned long>(n), base) + t;
 }
 
-size_t Print::print(long long n, int base)
-{
-    int t = 0;
-    if (base == 10 && n < 0) {
-        t = print('-');
-        n = -n;
-    }
-    return printNumber(static_cast<unsigned long long>(n), base) + t;
+size_t Print::print(unsigned long n, int base) {
+  if (base == 0) {
+    return write(n);
+  } else {
+    return printNumber(n, base);
+  }
 }
 
-size_t Print::print(unsigned long long n, int base)
-{
-    if (base == 0) {
-        return write(n);
-    } else {
-        return printNumber(n, base);
-    }
+size_t Print::print(long long n, int base) {
+  int t = 0;
+  if (base == 10 && n < 0) {
+    t = print('-');
+    n = -n;
+  }
+  return printNumber(static_cast<unsigned long long>(n), base) + t;
 }
 
-size_t Print::print(double n, int digits)
-{
-    return printFloat(n, digits);
+size_t Print::print(unsigned long long n, int base) {
+  if (base == 0) {
+    return write(n);
+  } else {
+    return printNumber(n, base);
+  }
 }
 
-size_t Print::println(const __FlashStringHelper *ifsh)
-{
-    size_t n = print(ifsh);
-    n += println();
-    return n;
+size_t Print::print(double n, int digits) {
+  return printFloat(n, digits);
 }
 
-size_t Print::print(const Printable& x)
-{
-    return x.printTo(*this);
+size_t Print::print(const Printable &x) {
+  return x.printTo(*this);
 }
 
-size_t Print::print(struct tm * timeinfo, const char * format)
-{
-    const char * f = format;
-    if(!f){
-        f = "%c";
-    }
-    char buf[64];
-    size_t written = strftime(buf, 64, f, timeinfo);
-    if(written == 0){
-        return written;
-    }
-    return print(buf);
+size_t Print::print(struct tm *timeinfo, const char *format) {
+  const char *f = format;
+  if (!f) {
+    f = "%c";
+  }
+  char buf[64];
+  size_t written = strftime(buf, 64, f, timeinfo);
+  if (written == 0) {
+    return written;
+  }
+  return print(buf);
 }
 
-size_t Print::println(void)
-{
-    return print("\r\n");
+size_t Print::println(void) {
+  return print("\r\n");
 }
 
-size_t Print::println(const String &s)
-{
-    size_t n = print(s);
-    n += println();
-    return n;
+size_t Print::println(const String &s) {
+  size_t n = print(s);
+  n += println();
+  return n;
 }
 
-size_t Print::println(const char c[])
-{
-    size_t n = print(c);
-    n += println();
-    return n;
+size_t Print::println(const char c[]) {
+  size_t n = print(c);
+  n += println();
+  return n;
 }
 
-size_t Print::println(char c)
-{
-    size_t n = print(c);
-    n += println();
-    return n;
+size_t Print::println(char c) {
+  size_t n = print(c);
+  n += println();
+  return n;
 }
 
-size_t Print::println(unsigned char b, int base)
-{
-    size_t n = print(b, base);
-    n += println();
-    return n;
+size_t Print::println(unsigned char b, int base) {
+  size_t n = print(b, base);
+  n += println();
+  return n;
 }
 
-size_t Print::println(int num, int base)
-{
-    size_t n = print(num, base);
-    n += println();
-    return n;
+size_t Print::println(int num, int base) {
+  size_t n = print(num, base);
+  n += println();
+  return n;
 }
 
-size_t Print::println(unsigned int num, int base)
-{
-    size_t n = print(num, base);
-    n += println();
-    return n;
+size_t Print::println(unsigned int num, int base) {
+  size_t n = print(num, base);
+  n += println();
+  return n;
 }
 
-size_t Print::println(long num, int base)
-{
-    size_t n = print(num, base);
-    n += println();
-    return n;
+size_t Print::println(long num, int base) {
+  size_t n = print(num, base);
+  n += println();
+  return n;
 }
 
-size_t Print::println(unsigned long num, int base)
-{
-    size_t n = print(num, base);
-    n += println();
-    return n;
+size_t Print::println(unsigned long num, int base) {
+  size_t n = print(num, base);
+  n += println();
+  return n;
 }
 
-size_t Print::println(long long num, int base)
-{
-    size_t n = print(num, base);
-    n += println();
-    return n;
+size_t Print::println(long long num, int base) {
+  size_t n = print(num, base);
+  n += println();
+  return n;
 }
 
-size_t Print::println(unsigned long long num, int base)
-{
-    size_t n = print(num, base);
-    n += println();
-    return n;
+size_t Print::println(unsigned long long num, int base) {
+  size_t n = print(num, base);
+  n += println();
+  return n;
 }
 
-size_t Print::println(double num, int digits)
-{
-    size_t n = print(num, digits);
-    n += println();
-    return n;
+size_t Print::println(double num, int digits) {
+  size_t n = print(num, digits);
+  n += println();
+  return n;
 }
 
-size_t Print::println(const Printable& x)
-{
-    size_t n = print(x);
-    n += println();
-    return n;
+size_t Print::println(const Printable &x) {
+  size_t n = print(x);
+  n += println();
+  return n;
 }
 
-size_t Print::println(struct tm * timeinfo, const char * format)
-{
-    size_t n = print(timeinfo, format);
-    n += println();
-    return n;
+size_t Print::println(struct tm *timeinfo, const char *format) {
+  size_t n = print(timeinfo, format);
+  n += println();
+  return n;
 }
 
 // Private Methods /////////////////////////////////////////////////////////////
 
-size_t Print::printNumber(unsigned long n, uint8_t base)
-{
-    char buf[8 * sizeof(n) + 1]; // Assumes 8-bit chars plus zero byte.
-    char *str = &buf[sizeof(buf) - 1];
+size_t Print::printNumber(unsigned long n, uint8_t base) {
+  char buf[8 * sizeof(n) + 1];  // Assumes 8-bit chars plus zero byte.
+  char *str = &buf[sizeof(buf) - 1];
 
-    *str = '\0';
+  *str = '\0';
 
-    // prevent crash if called with base == 1
-    if(base < 2) {
-        base = 10;
-    }
+  // prevent crash if called with base == 1
+  if (base < 2) {
+    base = 10;
+  }
 
-    do {
-        char c = n % base;
-        n /= base;
+  do {
+    char c = n % base;
+    n /= base;
 
-        *--str = c < 10 ? c + '0' : c + 'A' - 10;
-    } while (n);
+    *--str = c < 10 ? c + '0' : c + 'A' - 10;
+  } while (n);
 
-    return write(str);
+  return write(str);
 }
 
-size_t Print::printNumber(unsigned long long n, uint8_t base)
-{
-    char buf[8 * sizeof(n) + 1]; // Assumes 8-bit chars plus zero byte.
-    char* str = &buf[sizeof(buf) - 1];
+size_t Print::printNumber(unsigned long long n, uint8_t base) {
+  char buf[8 * sizeof(n) + 1];  // Assumes 8-bit chars plus zero byte.
+  char *str = &buf[sizeof(buf) - 1];
 
-    *str = '\0';
+  *str = '\0';
 
-    // prevent crash if called with base == 1
-    if (base < 2) {
-        base = 10;
-    }
+  // prevent crash if called with base == 1
+  if (base < 2) {
+    base = 10;
+  }
 
-    do {
-        auto m = n;
-        n /= base;
-        char c = m - base * n;
+  do {
+    auto m = n;
+    n /= base;
+    char c = m - base * n;
 
-        *--str = c < 10 ? c + '0' : c + 'A' - 10;
-    } while (n);
+    *--str = c < 10 ? c + '0' : c + 'A' - 10;
+  } while (n);
 
-    return write(str);
+  return write(str);
 }
 
-size_t Print::printFloat(double number, uint8_t digits)
-{
-    size_t n = 0;
+size_t Print::printFloat(double number, uint8_t digits) {
+  size_t n = 0;
 
-    if(isnan(number)) {
-        return print("nan");
-    }
-    if(isinf(number)) {
-        return print("inf");
-    }
-    if(number > 4294967040.0) {
-        return print("ovf");    // constant determined empirically
-    }
-    if(number < -4294967040.0) {
-        return print("ovf");    // constant determined empirically
-    }
+  if (isnan(number)) {
+    return print("nan");
+  }
+  if (isinf(number)) {
+    return print("inf");
+  }
+  if (number > 4294967040.0) {
+    return print("ovf");  // constant determined empirically
+  }
+  if (number < -4294967040.0) {
+    return print("ovf");  // constant determined empirically
+  }
 
-    // Handle negative numbers
-    if(number < 0.0) {
-        n += print('-');
-        number = -number;
-    }
+  // Handle negative numbers
+  if (number < 0.0) {
+    n += print('-');
+    number = -number;
+  }
 
-    // Round correctly so that print(1.999, 2) prints as "2.00"
-    double rounding = 0.5;
-    for(uint8_t i = 0; i < digits; ++i) {
-        rounding /= 10.0;
-    }
+  // Round correctly so that print(1.999, 2) prints as "2.00"
+  double rounding = 0.5;
+  for (uint8_t i = 0; i < digits; ++i) {
+    rounding /= 10.0;
+  }
 
-    number += rounding;
+  number += rounding;
 
-    // Extract the integer part of the number and print it
-    unsigned long int_part = (unsigned long) number;
-    double remainder = number - (double) int_part;
-    n += print(int_part);
+  // Extract the integer part of the number and print it
+  unsigned long int_part = (unsigned long)number;
+  double remainder = number - (double)int_part;
+  n += print(int_part);
 
-    // Print the decimal point, but only if there are digits beyond
-    if(digits > 0) {
-        n += print(".");
-    }
+  // Print the decimal point, but only if there are digits beyond
+  if (digits > 0) {
+    n += print(".");
+  }
 
-    // Extract digits from the remainder one at a time
-    while(digits-- > 0) {
-        remainder *= 10.0;
-        int toPrint = int(remainder);
-        n += print(toPrint);
-        remainder -= toPrint;
-    }
+  // Extract digits from the remainder one at a time
+  while (digits-- > 0) {
+    remainder *= 10.0;
+    int toPrint = int(remainder);
+    n += print(toPrint);
+    remainder -= toPrint;
+  }
 
-    return n;
+  return n;
 }
diff --git a/cores/esp32/Print.h b/cores/esp32/Print.h
index 15d07357ae9..d02a8233a6c 100644
--- a/cores/esp32/Print.h
+++ b/cores/esp32/Print.h
@@ -21,6 +21,7 @@
 #define Print_h
 
 #include <stdint.h>
+#include <stdio.h>
 #include <stddef.h>
 
 #include "WString.h"
@@ -31,78 +32,87 @@
 #define OCT 8
 #define BIN 2
 
-class Print
-{
+class Print {
 private:
-    int write_error;
-    size_t printNumber(unsigned long, uint8_t);
-    size_t printNumber(unsigned long long, uint8_t);
-    size_t printFloat(double, uint8_t);
+  int write_error;
+  size_t printNumber(unsigned long, uint8_t);
+  size_t printNumber(unsigned long long, uint8_t);
+  size_t printFloat(double, uint8_t);
+
 protected:
-    void setWriteError(int err = 1)
-    {
-        write_error = err;
-    }
+  void setWriteError(int err = 1) {
+    write_error = err;
+  }
+
 public:
-    Print() :
-        write_error(0)
-    {
-    }
-    virtual ~Print() {}
-    int getWriteError()
-    {
-        return write_error;
-    }
-    void clearWriteError()
-    {
-        setWriteError(0);
-    }
+  Print() : write_error(0) {}
+  virtual ~Print() {}
+  int getWriteError() {
+    return write_error;
+  }
+  void clearWriteError() {
+    setWriteError(0);
+  }
 
-    virtual size_t write(uint8_t) = 0;
-    size_t write(const char *str)
-    {
-        if(str == NULL) {
-            return 0;
-        }
-        return write((const uint8_t *) str, strlen(str));
-    }
-    virtual size_t write(const uint8_t *buffer, size_t size);
-    size_t write(const char *buffer, size_t size)
-    {
-        return write((const uint8_t *) buffer, size);
+  virtual size_t write(uint8_t) = 0;
+  size_t write(const char *str) {
+    if (str == NULL) {
+      return 0;
     }
+    return write((const uint8_t *)str, strlen(str));
+  }
+  virtual size_t write(const uint8_t *buffer, size_t size);
+  size_t write(const char *buffer, size_t size) {
+    return write((const uint8_t *)buffer, size);
+  }
+
+  size_t vprintf(const char *format, va_list arg);
+
+  size_t printf(const char *format, ...) __attribute__((format(printf, 2, 3)));
+  size_t printf(const __FlashStringHelper *ifsh, ...);
+
+  // add availableForWrite to make compatible with Arduino Print.h
+  // default to zero, meaning "a single write may block"
+  // should be overridden by subclasses with buffering
+  virtual int availableForWrite() {
+    return 0;
+  }
+  size_t print(const __FlashStringHelper *ifsh) {
+    return print(reinterpret_cast<const char *>(ifsh));
+  }
+  size_t print(const String &);
+  size_t print(const char[]);
+  size_t print(char);
+  size_t print(unsigned char, int = DEC);
+  size_t print(int, int = DEC);
+  size_t print(unsigned int, int = DEC);
+  size_t print(long, int = DEC);
+  size_t print(unsigned long, int = DEC);
+  size_t print(long long, int = DEC);
+  size_t print(unsigned long long, int = DEC);
+  size_t print(double, int = 2);
+  size_t print(const Printable &);
+  size_t print(struct tm *timeinfo, const char *format = NULL);
+
+  size_t println(const __FlashStringHelper *ifsh) {
+    return println(reinterpret_cast<const char *>(ifsh));
+  }
+  size_t println(const String &s);
+  size_t println(const char[]);
+  size_t println(char);
+  size_t println(unsigned char, int = DEC);
+  size_t println(int, int = DEC);
+  size_t println(unsigned int, int = DEC);
+  size_t println(long, int = DEC);
+  size_t println(unsigned long, int = DEC);
+  size_t println(long long, int = DEC);
+  size_t println(unsigned long long, int = DEC);
+  size_t println(double, int = 2);
+  size_t println(const Printable &);
+  size_t println(struct tm *timeinfo, const char *format = NULL);
+  size_t println(void);
 
-    size_t printf(const char * format, ...)  __attribute__ ((format (printf, 2, 3)));
-    size_t print(const __FlashStringHelper *);
-    size_t print(const String &);
-    size_t print(const char[]);
-    size_t print(char);
-    size_t print(unsigned char, int = DEC);
-    size_t print(int, int = DEC);
-    size_t print(unsigned int, int = DEC);
-    size_t print(long, int = DEC);
-    size_t print(unsigned long, int = DEC);
-    size_t print(long long, int = DEC);
-    size_t print(unsigned long long, int = DEC);
-    size_t print(double, int = 2);
-    size_t print(const Printable&);
-    size_t print(struct tm * timeinfo, const char * format = NULL);
-
-    size_t println(const __FlashStringHelper *);
-    size_t println(const String &s);
-    size_t println(const char[]);
-    size_t println(char);
-    size_t println(unsigned char, int = DEC);
-    size_t println(int, int = DEC);
-    size_t println(unsigned int, int = DEC);
-    size_t println(long, int = DEC);
-    size_t println(unsigned long, int = DEC);
-    size_t println(long long, int = DEC);
-    size_t println(unsigned long long, int = DEC);
-    size_t println(double, int = 2);
-    size_t println(const Printable&);
-    size_t println(struct tm * timeinfo, const char * format = NULL);
-    size_t println(void);
+  virtual void flush() { /* Empty implementation for backward compatibility */ }
 };
 
 #endif
diff --git a/cores/esp32/Printable.h b/cores/esp32/Printable.h
index aa4e62f8f11..3a8fe009207 100644
--- a/cores/esp32/Printable.h
+++ b/cores/esp32/Printable.h
@@ -30,12 +30,10 @@ class Print;
  Print::print and Print::println methods.
  */
 
-class Printable
-{
+class Printable {
 public:
-    virtual ~Printable() {}
-    virtual size_t printTo(Print& p) const = 0;
+  virtual ~Printable() {}
+  virtual size_t printTo(Print &p) const = 0;
 };
 
 #endif
-
diff --git a/cores/esp32/SHA1Builder.cpp b/cores/esp32/SHA1Builder.cpp
new file mode 100644
index 00000000000..6bbe3ca83e0
--- /dev/null
+++ b/cores/esp32/SHA1Builder.cpp
@@ -0,0 +1,340 @@
+/*
+ *  FIPS-180-1 compliant SHA-1 implementation
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *  This file is part of mbed TLS (https://tls.mbed.org)
+ *  Modified for esp32 by Lucas Saavedra Vaz on 11 Jan 2024
+ */
+
+#include <Arduino.h>
+#include <SHA1Builder.h>
+
+// 32-bit integer manipulation macros (big endian)
+
+#ifndef GET_UINT32_BE
+#define GET_UINT32_BE(n, b, i) \
+  { (n) = ((uint32_t)(b)[(i)] << 24) | ((uint32_t)(b)[(i) + 1] << 16) | ((uint32_t)(b)[(i) + 2] << 8) | ((uint32_t)(b)[(i) + 3]); }
+#endif
+
+#ifndef PUT_UINT32_BE
+#define PUT_UINT32_BE(n, b, i)           \
+  {                                      \
+    (b)[(i)] = (uint8_t)((n) >> 24);     \
+    (b)[(i) + 1] = (uint8_t)((n) >> 16); \
+    (b)[(i) + 2] = (uint8_t)((n) >> 8);  \
+    (b)[(i) + 3] = (uint8_t)((n));       \
+  }
+#endif
+
+// Constants
+
+static const uint8_t sha1_padding[64] = {0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                                         0,    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+// Private methods
+
+void SHA1Builder::process(const uint8_t *data) {
+  uint32_t temp, W[16], A, B, C, D, E;
+
+  GET_UINT32_BE(W[0], data, 0);
+  GET_UINT32_BE(W[1], data, 4);
+  GET_UINT32_BE(W[2], data, 8);
+  GET_UINT32_BE(W[3], data, 12);
+  GET_UINT32_BE(W[4], data, 16);
+  GET_UINT32_BE(W[5], data, 20);
+  GET_UINT32_BE(W[6], data, 24);
+  GET_UINT32_BE(W[7], data, 28);
+  GET_UINT32_BE(W[8], data, 32);
+  GET_UINT32_BE(W[9], data, 36);
+  GET_UINT32_BE(W[10], data, 40);
+  GET_UINT32_BE(W[11], data, 44);
+  GET_UINT32_BE(W[12], data, 48);
+  GET_UINT32_BE(W[13], data, 52);
+  GET_UINT32_BE(W[14], data, 56);
+  GET_UINT32_BE(W[15], data, 60);
+
+#define sha1_S(x, n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
+
+#define sha1_R(t) (temp = W[(t - 3) & 0x0F] ^ W[(t - 8) & 0x0F] ^ W[(t - 14) & 0x0F] ^ W[t & 0x0F], (W[t & 0x0F] = sha1_S(temp, 1)))
+
+#define sha1_P(a, b, c, d, e, x)                      \
+  {                                                   \
+    e += sha1_S(a, 5) + sha1_F(b, c, d) + sha1_K + x; \
+    b = sha1_S(b, 30);                                \
+  }
+
+  A = state[0];
+  B = state[1];
+  C = state[2];
+  D = state[3];
+  E = state[4];
+
+#define sha1_F(x, y, z) (z ^ (x & (y ^ z)))
+#define sha1_K          0x5A827999
+
+  sha1_P(A, B, C, D, E, W[0]);
+  sha1_P(E, A, B, C, D, W[1]);
+  sha1_P(D, E, A, B, C, W[2]);
+  sha1_P(C, D, E, A, B, W[3]);
+  sha1_P(B, C, D, E, A, W[4]);
+  sha1_P(A, B, C, D, E, W[5]);
+  sha1_P(E, A, B, C, D, W[6]);
+  sha1_P(D, E, A, B, C, W[7]);
+  sha1_P(C, D, E, A, B, W[8]);
+  sha1_P(B, C, D, E, A, W[9]);
+  sha1_P(A, B, C, D, E, W[10]);
+  sha1_P(E, A, B, C, D, W[11]);
+  sha1_P(D, E, A, B, C, W[12]);
+  sha1_P(C, D, E, A, B, W[13]);
+  sha1_P(B, C, D, E, A, W[14]);
+  sha1_P(A, B, C, D, E, W[15]);
+  sha1_P(E, A, B, C, D, sha1_R(16));
+  sha1_P(D, E, A, B, C, sha1_R(17));
+  sha1_P(C, D, E, A, B, sha1_R(18));
+  sha1_P(B, C, D, E, A, sha1_R(19));
+
+#undef sha1_K
+#undef sha1_F
+
+#define sha1_F(x, y, z) (x ^ y ^ z)
+#define sha1_K          0x6ED9EBA1
+
+  sha1_P(A, B, C, D, E, sha1_R(20));
+  sha1_P(E, A, B, C, D, sha1_R(21));
+  sha1_P(D, E, A, B, C, sha1_R(22));
+  sha1_P(C, D, E, A, B, sha1_R(23));
+  sha1_P(B, C, D, E, A, sha1_R(24));
+  sha1_P(A, B, C, D, E, sha1_R(25));
+  sha1_P(E, A, B, C, D, sha1_R(26));
+  sha1_P(D, E, A, B, C, sha1_R(27));
+  sha1_P(C, D, E, A, B, sha1_R(28));
+  sha1_P(B, C, D, E, A, sha1_R(29));
+  sha1_P(A, B, C, D, E, sha1_R(30));
+  sha1_P(E, A, B, C, D, sha1_R(31));
+  sha1_P(D, E, A, B, C, sha1_R(32));
+  sha1_P(C, D, E, A, B, sha1_R(33));
+  sha1_P(B, C, D, E, A, sha1_R(34));
+  sha1_P(A, B, C, D, E, sha1_R(35));
+  sha1_P(E, A, B, C, D, sha1_R(36));
+  sha1_P(D, E, A, B, C, sha1_R(37));
+  sha1_P(C, D, E, A, B, sha1_R(38));
+  sha1_P(B, C, D, E, A, sha1_R(39));
+
+#undef sha1_K
+#undef sha1_F
+
+#define sha1_F(x, y, z) ((x & y) | (z & (x | y)))
+#define sha1_K          0x8F1BBCDC
+
+  sha1_P(A, B, C, D, E, sha1_R(40));
+  sha1_P(E, A, B, C, D, sha1_R(41));
+  sha1_P(D, E, A, B, C, sha1_R(42));
+  sha1_P(C, D, E, A, B, sha1_R(43));
+  sha1_P(B, C, D, E, A, sha1_R(44));
+  sha1_P(A, B, C, D, E, sha1_R(45));
+  sha1_P(E, A, B, C, D, sha1_R(46));
+  sha1_P(D, E, A, B, C, sha1_R(47));
+  sha1_P(C, D, E, A, B, sha1_R(48));
+  sha1_P(B, C, D, E, A, sha1_R(49));
+  sha1_P(A, B, C, D, E, sha1_R(50));
+  sha1_P(E, A, B, C, D, sha1_R(51));
+  sha1_P(D, E, A, B, C, sha1_R(52));
+  sha1_P(C, D, E, A, B, sha1_R(53));
+  sha1_P(B, C, D, E, A, sha1_R(54));
+  sha1_P(A, B, C, D, E, sha1_R(55));
+  sha1_P(E, A, B, C, D, sha1_R(56));
+  sha1_P(D, E, A, B, C, sha1_R(57));
+  sha1_P(C, D, E, A, B, sha1_R(58));
+  sha1_P(B, C, D, E, A, sha1_R(59));
+
+#undef sha1_K
+#undef sha1_F
+
+#define sha1_F(x, y, z) (x ^ y ^ z)
+#define sha1_K          0xCA62C1D6
+
+  sha1_P(A, B, C, D, E, sha1_R(60));
+  sha1_P(E, A, B, C, D, sha1_R(61));
+  sha1_P(D, E, A, B, C, sha1_R(62));
+  sha1_P(C, D, E, A, B, sha1_R(63));
+  sha1_P(B, C, D, E, A, sha1_R(64));
+  sha1_P(A, B, C, D, E, sha1_R(65));
+  sha1_P(E, A, B, C, D, sha1_R(66));
+  sha1_P(D, E, A, B, C, sha1_R(67));
+  sha1_P(C, D, E, A, B, sha1_R(68));
+  sha1_P(B, C, D, E, A, sha1_R(69));
+  sha1_P(A, B, C, D, E, sha1_R(70));
+  sha1_P(E, A, B, C, D, sha1_R(71));
+  sha1_P(D, E, A, B, C, sha1_R(72));
+  sha1_P(C, D, E, A, B, sha1_R(73));
+  sha1_P(B, C, D, E, A, sha1_R(74));
+  sha1_P(A, B, C, D, E, sha1_R(75));
+  sha1_P(E, A, B, C, D, sha1_R(76));
+  sha1_P(D, E, A, B, C, sha1_R(77));
+  sha1_P(C, D, E, A, B, sha1_R(78));
+  sha1_P(B, C, D, E, A, sha1_R(79));
+
+#undef sha1_K
+#undef sha1_F
+
+  state[0] += A;
+  state[1] += B;
+  state[2] += C;
+  state[3] += D;
+  state[4] += E;
+}
+
+// Public methods
+
+void SHA1Builder::begin(void) {
+  total[0] = 0;
+  total[1] = 0;
+
+  state[0] = 0x67452301;
+  state[1] = 0xEFCDAB89;
+  state[2] = 0x98BADCFE;
+  state[3] = 0x10325476;
+  state[4] = 0xC3D2E1F0;
+
+  memset(buffer, 0x00, sizeof(buffer));
+  memset(hash, 0x00, sizeof(hash));
+}
+
+void SHA1Builder::add(const uint8_t *data, size_t len) {
+  size_t fill;
+  uint32_t left;
+
+  if (len == 0) {
+    return;
+  }
+
+  left = total[0] & 0x3F;
+  fill = 64 - left;
+
+  total[0] += (uint32_t)len;
+  total[0] &= 0xFFFFFFFF;
+
+  if (total[0] < (uint32_t)len) {
+    total[1]++;
+  }
+
+  if (left && len >= fill) {
+    memcpy((void *)(buffer + left), data, fill);
+    process(buffer);
+    data += fill;
+    len -= fill;
+    left = 0;
+  }
+
+  while (len >= 64) {
+    process(data);
+    data += 64;
+    len -= 64;
+  }
+
+  if (len > 0) {
+    memcpy((void *)(buffer + left), data, len);
+  }
+}
+
+void SHA1Builder::addHexString(const char *data) {
+  uint16_t len = strlen(data);
+  uint8_t *tmp = (uint8_t *)malloc(len / 2);
+  if (tmp == NULL) {
+    return;
+  }
+  hex2bytes(tmp, len / 2, data);
+  add(tmp, len / 2);
+  free(tmp);
+}
+
+bool SHA1Builder::addStream(Stream &stream, const size_t maxLen) {
+  const int buf_size = 512;
+  int maxLengthLeft = maxLen;
+  uint8_t *buf = (uint8_t *)malloc(buf_size);
+
+  if (!buf) {
+    return false;
+  }
+
+  int bytesAvailable = stream.available();
+  while ((bytesAvailable > 0) && (maxLengthLeft > 0)) {
+
+    // determine number of bytes to read
+    int readBytes = bytesAvailable;
+    if (readBytes > maxLengthLeft) {
+      readBytes = maxLengthLeft;  // read only until max_len
+    }
+    if (readBytes > buf_size) {
+      readBytes = buf_size;  // not read more the buffer can handle
+    }
+
+    // read data and check if we got something
+    int numBytesRead = stream.readBytes(buf, readBytes);
+    if (numBytesRead < 1) {
+      free(buf);
+      return false;
+    }
+
+    // Update SHA1 with buffer payload
+    add(buf, numBytesRead);
+
+    // update available number of bytes
+    maxLengthLeft -= numBytesRead;
+    bytesAvailable = stream.available();
+  }
+  free(buf);
+  return true;
+}
+
+void SHA1Builder::calculate(void) {
+  uint32_t last, padn;
+  uint32_t high, low;
+  uint8_t msglen[8];
+
+  high = (total[0] >> 29) | (total[1] << 3);
+  low = (total[0] << 3);
+
+  PUT_UINT32_BE(high, msglen, 0);
+  PUT_UINT32_BE(low, msglen, 4);
+
+  last = total[0] & 0x3F;
+  padn = (last < 56) ? (56 - last) : (120 - last);
+
+  add((uint8_t *)sha1_padding, padn);
+  add(msglen, 8);
+
+  PUT_UINT32_BE(state[0], hash, 0);
+  PUT_UINT32_BE(state[1], hash, 4);
+  PUT_UINT32_BE(state[2], hash, 8);
+  PUT_UINT32_BE(state[3], hash, 12);
+  PUT_UINT32_BE(state[4], hash, 16);
+}
+
+void SHA1Builder::getBytes(uint8_t *output) {
+  memcpy(output, hash, SHA1_HASH_SIZE);
+}
+
+void SHA1Builder::getChars(char *output) {
+  bytes2hex(output, SHA1_HASH_SIZE * 2 + 1, hash, SHA1_HASH_SIZE);
+}
+
+String SHA1Builder::toString(void) {
+  char out[(SHA1_HASH_SIZE * 2) + 1];
+  getChars(out);
+  return String(out);
+}
diff --git a/cores/esp32/SHA1Builder.h b/cores/esp32/SHA1Builder.h
new file mode 100644
index 00000000000..b587e4fdc96
--- /dev/null
+++ b/cores/esp32/SHA1Builder.h
@@ -0,0 +1,50 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef SHA1Builder_h
+#define SHA1Builder_h
+
+#include <WString.h>
+#include <Stream.h>
+
+#include "HashBuilder.h"
+
+#define SHA1_HASH_SIZE 20
+
+class SHA1Builder : public HashBuilder {
+private:
+  uint32_t total[2];            /* number of bytes processed  */
+  uint32_t state[5];            /* intermediate digest state  */
+  unsigned char buffer[64];     /* data block being processed */
+  uint8_t hash[SHA1_HASH_SIZE]; /* SHA-1 result               */
+
+  void process(const uint8_t *data);
+
+public:
+  void begin() override;
+
+  using HashBuilder::add;
+  void add(const uint8_t *data, size_t len) override;
+
+  using HashBuilder::addHexString;
+  void addHexString(const char *data) override;
+
+  bool addStream(Stream &stream, const size_t maxLen) override;
+  void calculate() override;
+  void getBytes(uint8_t *output) override;
+  void getChars(char *output) override;
+  String toString() override;
+};
+
+#endif
diff --git a/cores/esp32/Server.h b/cores/esp32/Server.h
index 6a940a0b5fa..f4825d3dd09 100644
--- a/cores/esp32/Server.h
+++ b/cores/esp32/Server.h
@@ -22,10 +22,9 @@
 
 #include "Print.h"
 
-class Server: public Print
-{
+class Server : public Print {
 public:
-    virtual void begin(uint16_t port=0) =0;
+  virtual void begin() = 0;
 };
 
 #endif
diff --git a/cores/esp32/Stream.cpp b/cores/esp32/Stream.cpp
index 7d1649a6fb5..5c2060eaa35 100644
--- a/cores/esp32/Stream.cpp
+++ b/cores/esp32/Stream.cpp
@@ -18,61 +18,66 @@
 
  Created July 2011
  parsing functions based on TextFinder library by Michael Margolis
+
+ findMulti/findUntil routines written by Jim Leonard/Xuth
  */
 
 #include "Arduino.h"
 #include "Stream.h"
-#include "esp32-hal.h"
 
 #define PARSE_TIMEOUT 1000  // default number of milli-seconds to wait
-#define NO_SKIP_CHAR  1  // a magic char not found in a valid ASCII numeric field
 
 // private method to read stream with timeout
-int Stream::timedRead()
-{
-    int c;
-    _startMillis = millis();
-    do {
-        c = read();
-        if(c >= 0) {
-            return c;
-        }
-    } while(millis() - _startMillis < _timeout);
-    return -1;     // -1 indicates timeout
+int Stream::timedRead() {
+  int c;
+  _startMillis = millis();
+  do {
+    c = read();
+    if (c >= 0) {
+      return c;
+    }
+  } while (millis() - _startMillis < _timeout);
+  return -1;  // -1 indicates timeout
 }
 
 // private method to peek stream with timeout
-int Stream::timedPeek()
-{
-    int c;
-    _startMillis = millis();
-    do {
-        c = peek();
-        if(c >= 0) {
-            return c;
-        }
-    } while(millis() - _startMillis < _timeout);
-    return -1;     // -1 indicates timeout
+int Stream::timedPeek() {
+  int c;
+  _startMillis = millis();
+  do {
+    c = peek();
+    if (c >= 0) {
+      return c;
+    }
+  } while (millis() - _startMillis < _timeout);
+  return -1;  // -1 indicates timeout
 }
 
 // returns peek of the next digit in the stream or -1 if timeout
 // discards non-numeric characters
-int Stream::peekNextDigit()
-{
-    int c;
-    while(1) {
-        c = timedPeek();
-        if(c < 0) {
-            return c;    // timeout
-        }
-        if(c == '-') {
-            return c;
-        }
-        if(c >= '0' && c <= '9') {
-            return c;
+int Stream::peekNextDigit(LookaheadMode lookahead, bool detectDecimal) {
+  int c;
+  while (1) {
+    c = timedPeek();
+
+    if (c < 0 || c == '-' || (c >= '0' && c <= '9') || (detectDecimal && c == '.')) {
+      return c;
+    }
+
+    switch (lookahead) {
+      case SKIP_NONE: return -1;  // Fail code.
+      case SKIP_WHITESPACE:
+        switch (c) {
+          case ' ':
+          case '\t':
+          case '\r':
+          case '\n': break;
+          default:   return -1;  // Fail code.
         }
-        read();  // discard non-numeric
+      case SKIP_ALL: break;
     }
+    read();  // discard non-numeric
+  }
 }
 
 // Public Methods
@@ -80,80 +85,207 @@ int Stream::peekNextDigit()
 
 void Stream::setTimeout(unsigned long timeout)  // sets the maximum number of milliseconds to wait
 {
-    _timeout = timeout;
-}
-unsigned long Stream::getTimeout(void) {
-  return _timeout;
+  _timeout = timeout;
 }
 
 // find returns true if the target string is found
-bool  Stream::find(const char *target)
-{
+bool Stream::find(const char *target) {
   return findUntil(target, strlen(target), NULL, 0);
 }
 
 // reads data from the stream until the target string of given length is found
 // returns true if target string is found, false if timed out
-bool Stream::find(const char *target, size_t length)
-{
+bool Stream::find(const char *target, size_t length) {
   return findUntil(target, length, NULL, 0);
 }
 
 // as find but search ends if the terminator string is found
-bool  Stream::findUntil(const char *target, const char *terminator)
-{
+bool Stream::findUntil(const char *target, const char *terminator) {
   return findUntil(target, strlen(target), terminator, strlen(terminator));
 }
 
 // reads data from the stream until the target string of the given length is found
 // search terminated if the terminator string is found
 // returns true if target string is found, false if terminated or timed out
-bool Stream::findUntil(const char *target, size_t targetLen, const char *terminator, size_t termLen)
-{
+bool Stream::findUntil(const char *target, size_t targetLen, const char *terminator, size_t termLen) {
   if (terminator == NULL) {
     MultiTarget t[1] = {{target, targetLen, 0}};
-    return findMulti(t, 1) == 0 ? true : false;
+    return findMulti(t, 1) == 0;
   } else {
     MultiTarget t[2] = {{target, targetLen, 0}, {terminator, termLen, 0}};
-    return findMulti(t, 2) == 0 ? true : false;
+    return findMulti(t, 2) == 0;
+  }
+}
+
+// returns the first valid (long) integer value from the current position.
+// lookahead determines how parseInt looks ahead in the stream.
+// See LookaheadMode enumeration at the top of the file.
+// Lookahead is terminated by the first character that is not a valid part of an integer.
+// Once parsing commences, 'ignore' will be skipped in the stream.
+long Stream::parseInt(LookaheadMode lookahead, char ignore) {
+  bool isNegative = false;
+  long value = 0;
+  int c;
+
+  c = peekNextDigit(lookahead, false);
+  // ignore non numeric leading characters
+  if (c < 0) {
+    return 0;  // zero returned if timeout
+  }
+
+  do {
+    if ((char)c == ignore)
+      ;  // ignore this character
+    else if (c == '-') {
+      isNegative = true;
+    } else if (c >= '0' && c <= '9') {  // is c a digit?
+      value = value * 10 + c - '0';
+    }
+    read();  // consume the character we got with peek
+    c = timedPeek();
+  } while ((c >= '0' && c <= '9') || (char)c == ignore);
+
+  if (isNegative) {
+    value = -value;
+  }
+  return value;
+}
+
+// as parseInt but returns a floating point value
+float Stream::parseFloat(LookaheadMode lookahead, char ignore) {
+  bool isNegative = false;
+  bool isFraction = false;
+  double value = 0.0;
+  int c;
+  double fraction = 1.0;
+
+  c = peekNextDigit(lookahead, true);
+  // ignore non numeric leading characters
+  if (c < 0) {
+    return 0;  // zero returned if timeout
+  }
+
+  do {
+    if ((char)c == ignore)
+      ;  // ignore
+    else if (c == '-') {
+      isNegative = true;
+    } else if (c == '.') {
+      isFraction = true;
+    } else if (c >= '0' && c <= '9') {  // is c a digit?
+      if (isFraction) {
+        fraction *= 0.1;
+        value = value + fraction * (c - '0');
+      } else {
+        value = value * 10 + c - '0';
+      }
+    }
+    read();  // consume the character we got with peek
+    c = timedPeek();
+  } while ((c >= '0' && c <= '9') || (c == '.' && !isFraction) || (char)c == ignore);
+
+  if (isNegative) {
+    value = -value;
+  }
+
+  return value;
+}
+
+// read characters from stream into buffer
+// terminates if length characters have been read, or timeout (see setTimeout)
+// returns the number of characters placed in the buffer
+// the buffer is NOT null terminated.
+//
+size_t Stream::readBytes(char *buffer, size_t length) {
+  size_t count = 0;
+  while (count < length) {
+    int c = timedRead();
+    if (c < 0) {
+      break;
+    }
+    *buffer++ = (char)c;
+    count++;
+  }
+  return count;
+}
+
+// as readBytes with terminator character
+// terminates if length characters have been read, timeout, or if the terminator character  detected
+// returns the number of characters placed in the buffer (0 means no valid data found)
+
+size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length) {
+  size_t index = 0;
+  while (index < length) {
+    int c = timedRead();
+    if (c < 0 || (char)c == terminator) {
+      break;
+    }
+    *buffer++ = (char)c;
+    index++;
+  }
+  return index;  // return number of characters, not including null terminator
+}
+
+String Stream::readString() {
+  String ret;
+  int c = timedRead();
+  while (c >= 0) {
+    ret += (char)c;
+    c = timedRead();
+  }
+  return ret;
+}
+
+String Stream::readStringUntil(char terminator) {
+  String ret;
+  int c = timedRead();
+  while (c >= 0 && (char)c != terminator) {
+    ret += (char)c;
+    c = timedRead();
   }
+  return ret;
 }
 
-int Stream::findMulti( struct Stream::MultiTarget *targets, int tCount) {
+int Stream::findMulti(struct Stream::MultiTarget *targets, int tCount) {
   // any zero length target string automatically matches and would make
   // a mess of the rest of the algorithm.
-  for (struct MultiTarget *t = targets; t < targets+tCount; ++t) {
-    if (t->len <= 0)
+  for (struct MultiTarget *t = targets; t < targets + tCount; ++t) {
+    if (t->len <= 0) {
       return t - targets;
+    }
   }
 
   while (1) {
     int c = timedRead();
-    if (c < 0)
+    if (c < 0) {
       return -1;
+    }
 
-    for (struct MultiTarget *t = targets; t < targets+tCount; ++t) {
+    for (struct MultiTarget *t = targets; t < targets + tCount; ++t) {
       // the simple case is if we match, deal with that first.
-      if (c == t->str[t->index]) {
-        if (++t->index == t->len)
+      if ((char)c == t->str[t->index]) {
+        if (++t->index == t->len) {
           return t - targets;
-        else
+        } else {
           continue;
+        }
       }
 
       // if not we need to walk back and see if we could have matched further
       // down the stream (ie '1112' doesn't match the first position in '11112'
       // but it will match the second position so we can't just reset the current
       // index to 0 when we find a mismatch.
-      if (t->index == 0)
+      if (t->index == 0) {
         continue;
+      }
 
       int origIndex = t->index;
       do {
         --t->index;
         // first check if current char works against the new current index
-        if (c != t->str[t->index])
+        if ((char)c != t->str[t->index]) {
           continue;
+        }
 
         // if it's the only char then we're good, nothing more to check
         if (t->index == 0) {
@@ -165,8 +297,9 @@ int Stream::findMulti( struct Stream::MultiTarget *targets, int tCount) {
         int diff = origIndex - t->index;
         size_t i;
         for (i = 0; i < t->index; ++i) {
-          if (t->str[i] != t->str[i + diff])
+          if (t->str[i] != t->str[i + diff]) {
             break;
+          }
         }
 
         // if we successfully got through the previous loop then our current
@@ -183,155 +316,3 @@ int Stream::findMulti( struct Stream::MultiTarget *targets, int tCount) {
   // unreachable
   return -1;
 }
-
-// returns the first valid (long) integer value from the current position.
-// initial characters that are not digits (or the minus sign) are skipped
-// function is terminated by the first character that is not a digit.
-long Stream::parseInt()
-{
-    return parseInt(NO_SKIP_CHAR); // terminate on first non-digit character (or timeout)
-}
-
-// as above but a given skipChar is ignored
-// this allows format characters (typically commas) in values to be ignored
-long Stream::parseInt(char skipChar)
-{
-    boolean isNegative = false;
-    long value = 0;
-    int c;
-
-    c = peekNextDigit();
-    // ignore non numeric leading characters
-    if(c < 0) {
-        return 0;    // zero returned if timeout
-    }
-
-    do {
-        if(c == skipChar) {
-        } // ignore this charactor
-        else if(c == '-') {
-            isNegative = true;
-        } else if(c >= '0' && c <= '9') {    // is c a digit?
-            value = value * 10 + c - '0';
-        }
-        read();  // consume the character we got with peek
-        c = timedPeek();
-    } while((c >= '0' && c <= '9') || c == skipChar);
-
-    if(isNegative) {
-        value = -value;
-    }
-    return value;
-}
-
-// as parseInt but returns a floating point value
-float Stream::parseFloat()
-{
-    return parseFloat(NO_SKIP_CHAR);
-}
-
-// as above but the given skipChar is ignored
-// this allows format characters (typically commas) in values to be ignored
-float Stream::parseFloat(char skipChar)
-{
-    boolean isNegative = false;
-    boolean isFraction = false;
-    long value = 0;
-    int c;
-    float fraction = 1.0;
-
-    c = peekNextDigit();
-    // ignore non numeric leading characters
-    if(c < 0) {
-        return 0;    // zero returned if timeout
-    }
-
-    do {
-        if(c == skipChar) {
-        } // ignore
-        else if(c == '-') {
-            isNegative = true;
-        } else if(c == '.') {
-            isFraction = true;
-        } else if(c >= '0' && c <= '9') {    // is c a digit?
-            value = value * 10 + c - '0';
-            if(isFraction) {
-                fraction *= 0.1;
-            }
-        }
-        read();  // consume the character we got with peek
-        c = timedPeek();
-    } while((c >= '0' && c <= '9') || c == '.' || c == skipChar);
-
-    if(isNegative) {
-        value = -value;
-    }
-    if(isFraction) {
-        return value * fraction;
-    } else {
-        return value;
-    }
-}
-
-// read characters from stream into buffer
-// terminates if length characters have been read, or timeout (see setTimeout)
-// returns the number of characters placed in the buffer
-// the buffer is NOT null terminated.
-//
-size_t Stream::readBytes(char *buffer, size_t length)
-{
-    size_t count = 0;
-    while(count < length) {
-        int c = timedRead();
-        if(c < 0) {
-            break;
-        }
-        *buffer++ = (char) c;
-        count++;
-    }
-    return count;
-}
-
-// as readBytes with terminator character
-// terminates if length characters have been read, timeout, or if the terminator character  detected
-// returns the number of characters placed in the buffer (0 means no valid data found)
-
-size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length)
-{
-    if(length < 1) {
-        return 0;
-    }
-    size_t index = 0;
-    while(index < length) {
-        int c = timedRead();
-        if(c < 0 || c == terminator) {
-            break;
-        }
-        *buffer++ = (char) c;
-        index++;
-    }
-    return index; // return number of characters, not including null terminator
-}
-
-String Stream::readString()
-{
-    String ret;
-    int c = timedRead();
-    while(c >= 0) {
-        ret += (char) c;
-        c = timedRead();
-    }
-    return ret;
-}
-
-String Stream::readStringUntil(char terminator)
-{
-    String ret;
-    int c = timedRead();
-    while(c >= 0 && c != terminator) {
-        ret += (char) c;
-        c = timedRead();
-    }
-    return ret;
-}
-
diff --git a/cores/esp32/Stream.h b/cores/esp32/Stream.h
index 2debee7e4f9..37346cdb99f 100644
--- a/cores/esp32/Stream.h
+++ b/cores/esp32/Stream.h
@@ -1,140 +1,148 @@
 /*
- Stream.h - base class for character-based streams.
- Copyright (c) 2010 David A. Mellis.  All right reserved.
+  Stream.h - base class for character-based streams.
+  Copyright (c) 2010 David A. Mellis.  All right reserved.
 
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
 
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
 
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 
- parsing functions based on TextFinder library by Michael Margolis
- */
+  parsing functions based on TextFinder library by Michael Margolis
+*/
 
-#ifndef Stream_h
-#define Stream_h
+#pragma once
 
 #include <inttypes.h>
 #include "Print.h"
 
-// compatability macros for testing
+// compatibility macros for testing
 /*
- #define   getInt()            parseInt()
- #define   getInt(skipChar)    parseInt(skipchar)
- #define   getFloat()          parseFloat()
- #define   getFloat(skipChar)  parseFloat(skipChar)
- #define   getString( pre_string, post_string, buffer, length)
- readBytesBetween( pre_string, terminator, buffer, length)
- */
-
-class Stream: public Print
-{
+#define   getInt()            parseInt()
+#define   getInt(ignore)      parseInt(ignore)
+#define   getFloat()          parseFloat()
+#define   getFloat(ignore)    parseFloat(ignore)
+#define   getString( pre_string, post_string, buffer, length)
+readBytesBetween( pre_string, terminator, buffer, length)
+*/
+
+// This enumeration provides the lookahead options for parseInt(), parseFloat()
+// The rules set out here are used until either the first valid character is found
+// or a time out occurs due to lack of input.
+enum LookaheadMode {
+  SKIP_ALL,        // All invalid characters are ignored.
+  SKIP_NONE,       // Nothing is skipped, and the stream is not touched unless the first waiting character is valid.
+  SKIP_WHITESPACE  // Only tabs, spaces, line feeds & carriage returns are skipped.
+};
+
+#define NO_IGNORE_CHAR '\x01'  // a char not found in a valid ASCII numeric field
+
+class Stream : public Print {
 protected:
-    unsigned long _timeout;      // number of milliseconds to wait for the next char before aborting timed read
-    unsigned long _startMillis;  // used for timeout measurement
-    int timedRead();    // private method to read stream with timeout
-    int timedPeek();    // private method to peek stream with timeout
-    int peekNextDigit(); // returns the next numeric digit in the stream or -1 if timeout
+  unsigned long _timeout;                                          // number of milliseconds to wait for the next char before aborting timed read
+  unsigned long _startMillis;                                      // used for timeout measurement
+  int timedRead();                                                 // private method to read stream with timeout
+  int timedPeek();                                                 // private method to peek stream with timeout
+  int peekNextDigit(LookaheadMode lookahead, bool detectDecimal);  // returns the next numeric digit in the stream or -1 if timeout
 
 public:
-    virtual int available() = 0;
-    virtual int read() = 0;
-    virtual int peek() = 0;
-    virtual void flush() = 0;
-
-    Stream():_startMillis(0)
-    {
-        _timeout = 1000;
-    }
-    virtual ~Stream() {}
-
-// parsing methods
-
-    void setTimeout(unsigned long timeout);  // sets maximum milliseconds to wait for stream data, default is 1 second
-    unsigned long getTimeout(void);
-      
-    bool find(const char *target);   // reads data from the stream until the target string is found
-    bool find(uint8_t *target)
-    {
-        return find((char *) target);
-    }
-    // returns true if target string is found, false if timed out (see setTimeout)
-
-    bool find(const char *target, size_t length);   // reads data from the stream until the target string of given length is found
-    bool find(const uint8_t *target, size_t length)
-    {
-        return find((char *) target, length);
-    }
-    // returns true if target string is found, false if timed out
-
-    bool find(char target)
-    {
-        return find (&target, 1);
-    }
-
-    bool findUntil(const char *target, const char *terminator);   // as find but search ends if the terminator string is found
-    bool findUntil(const uint8_t *target, const char *terminator)
-    {
-        return findUntil((char *) target, terminator);
-    }
-
-    bool findUntil(const char *target, size_t targetLen, const char *terminate, size_t termLen);   // as above but search ends if the terminate string is found
-    bool findUntil(const uint8_t *target, size_t targetLen, const char *terminate, size_t termLen)
-    {
-        return findUntil((char *) target, targetLen, terminate, termLen);
-    }
-
-    long parseInt(); // returns the first valid (long) integer value from the current position.
-    // initial characters that are not digits (or the minus sign) are skipped
-    // integer is terminated by the first character that is not a digit.
-
-    float parseFloat();               // float version of parseInt
-
-    virtual size_t readBytes(char *buffer, size_t length); // read chars from stream into buffer
-    virtual size_t readBytes(uint8_t *buffer, size_t length)
-    {
-        return readBytes((char *) buffer, length);
-    }
-    // terminates if length characters have been read or timeout (see setTimeout)
-    // returns the number of characters placed in the buffer (0 means no valid data found)
-
-    size_t readBytesUntil(char terminator, char *buffer, size_t length); // as readBytes with terminator character
-    size_t readBytesUntil(char terminator, uint8_t *buffer, size_t length)
-    {
-        return readBytesUntil(terminator, (char *) buffer, length);
-    }
-    // terminates if length characters have been read, timeout, or if the terminator character  detected
-    // returns the number of characters placed in the buffer (0 means no valid data found)
-
-    // Arduino String functions to be added here
-    virtual String readString();
-    String readStringUntil(char terminator);
+  virtual int available() = 0;
+  virtual int read() = 0;
+  virtual int peek() = 0;
+
+  Stream() {
+    _timeout = 1000;
+  }
+
+  // parsing methods
+
+  void setTimeout(unsigned long timeout);  // sets maximum milliseconds to wait for stream data, default is 1 second
+  unsigned long getTimeout(void) {
+    return _timeout;
+  }
+
+  bool find(const char *target);  // reads data from the stream until the target string is found
+  bool find(const uint8_t *target) {
+    return find((const char *)target);
+  }
+  // returns true if target string is found, false if timed out (see setTimeout)
+
+  bool find(const char *target, size_t length);  // reads data from the stream until the target string of given length is found
+  bool find(const uint8_t *target, size_t length) {
+    return find((const char *)target, length);
+  }
+  // returns true if target string is found, false if timed out
+
+  bool find(char target) {
+    return find(&target, 1);
+  }
+
+  bool findUntil(const char *target, const char *terminator);  // as find but search ends if the terminator string is found
+  bool findUntil(const uint8_t *target, const char *terminator) {
+    return findUntil((const char *)target, terminator);
+  }
+
+  bool findUntil(const char *target, size_t targetLen, const char *terminate, size_t termLen);  // as above but search ends if the terminate string is found
+  bool findUntil(const uint8_t *target, size_t targetLen, const char *terminate, size_t termLen) {
+    return findUntil((const char *)target, targetLen, terminate, termLen);
+  }
+
+  long parseInt(LookaheadMode lookahead = SKIP_ALL, char ignore = NO_IGNORE_CHAR);
+  // returns the first valid (long) integer value from the current position.
+  // lookahead determines how parseInt looks ahead in the stream.
+  // See LookaheadMode enumeration at the top of the file.
+  // Lookahead is terminated by the first character that is not a valid part of an integer.
+  // Once parsing commences, 'ignore' will be skipped in the stream.
+
+  float parseFloat(LookaheadMode lookahead = SKIP_ALL, char ignore = NO_IGNORE_CHAR);
+  // float version of parseInt
+
+  virtual size_t readBytes(char *buffer, size_t length);  // read chars from stream into buffer
+  virtual size_t readBytes(uint8_t *buffer, size_t length) {
+    return readBytes((char *)buffer, length);
+  }
+  // terminates if length characters have been read or timeout (see setTimeout)
+  // returns the number of characters placed in the buffer (0 means no valid data found)
+
+  size_t readBytesUntil(char terminator, char *buffer, size_t length);  // as readBytes with terminator character
+  size_t readBytesUntil(char terminator, uint8_t *buffer, size_t length) {
+    return readBytesUntil(terminator, (char *)buffer, length);
+  }
+  // terminates if length characters have been read, timeout, or if the terminator character  detected
+  // returns the number of characters placed in the buffer (0 means no valid data found)
+
+  // Arduino String functions to be added here
+  virtual String readString();
+  String readStringUntil(char terminator);
 
 protected:
-    long parseInt(char skipChar); // as above but the given skipChar is ignored
-    // as above but the given skipChar is ignored
-    // this allows format characters (typically commas) in values to be ignored
-
-    float parseFloat(char skipChar);  // as above but the given skipChar is ignored
-  
-    struct MultiTarget {
-      const char *str;  // string you're searching for
-      size_t len;       // length of string you're searching for
-      size_t index;     // index used by the search routine.
-    };
+  long parseInt(char ignore) {
+    return parseInt(SKIP_ALL, ignore);
+  }
+  float parseFloat(char ignore) {
+    return parseFloat(SKIP_ALL, ignore);
+  }
+  // These overload exists for compatibility with any class that has derived
+  // Stream and used parseFloat/Int with a custom ignore character. To keep
+  // the public API simple, these overload remains protected.
+
+  struct MultiTarget {
+    const char *str;  // string you're searching for
+    size_t len;       // length of string you're searching for
+    size_t index;     // index used by the search routine.
+  };
 
   // This allows you to search for an arbitrary number of strings.
   // Returns index of the target that is found first or -1 if timeout occurs.
   int findMulti(struct MultiTarget *targets, int tCount);
-
 };
 
-#endif
+#undef NO_IGNORE_CHAR
diff --git a/cores/esp32/StreamString.cpp b/cores/esp32/StreamString.cpp
index f50b6825b55..d0117c399eb 100644
--- a/cores/esp32/StreamString.cpp
+++ b/cores/esp32/StreamString.cpp
@@ -24,44 +24,41 @@
 #include "StreamString.h"
 
 size_t StreamString::write(const uint8_t *data, size_t size) {
-    if(size && data) {
-        const unsigned int newlen = length() + size;
-        if(reserve(newlen + 1)) {
-            memcpy((void *) (wbuffer() + len()), (const void *) data, size);
-            setLen(newlen);
-            *(wbuffer() + newlen) = 0x00; // add null for string end
-            return size;
-        }
+  if (size && data) {
+    const unsigned int newlen = length() + size;
+    if (reserve(newlen + 1)) {
+      memcpy((void *)(wbuffer() + len()), (const void *)data, size);
+      setLen(newlen);
+      *(wbuffer() + newlen) = 0x00;  // add null for string end
+      return size;
     }
-    return 0;
+  }
+  return 0;
 }
 
 size_t StreamString::write(uint8_t data) {
-    return concat((char) data);
+  return concat((char)data);
 }
 
 int StreamString::available() {
-    return length();
+  return length();
 }
 
 int StreamString::read() {
-    if(length()) {
-        char c = charAt(0);
-        remove(0, 1);
-        return c;
-
-    }
-    return -1;
+  if (length()) {
+    char c = charAt(0);
+    remove(0, 1);
+    return c;
+  }
+  return -1;
 }
 
 int StreamString::peek() {
-    if(length()) {
-        char c = charAt(0);
-        return c;
-    }
-    return -1;
-}
-
-void StreamString::flush() {
+  if (length()) {
+    char c = charAt(0);
+    return c;
+  }
+  return -1;
 }
 
+void StreamString::flush() {}
diff --git a/cores/esp32/StreamString.h b/cores/esp32/StreamString.h
index dbdf3fb0097..b4f20147277 100644
--- a/cores/esp32/StreamString.h
+++ b/cores/esp32/StreamString.h
@@ -21,19 +21,18 @@
 
 #ifndef STREAMSTRING_H_
 #define STREAMSTRING_H_
+#include "Stream.h"
+#include "WString.h"
 
-
-class StreamString: public Stream, public String
-{
+class StreamString : public Stream, public String {
 public:
-    size_t write(const uint8_t *buffer, size_t size) override;
-    size_t write(uint8_t data) override;
+  size_t write(const uint8_t *buffer, size_t size) override;
+  size_t write(uint8_t data) override;
 
-    int available() override;
-    int read() override;
-    int peek() override;
-    void flush() override;
+  int available() override;
+  int read() override;
+  int peek() override;
+  void flush() override;
 };
 
-
 #endif /* STREAMSTRING_H_ */
diff --git a/cores/esp32/Tone.cpp b/cores/esp32/Tone.cpp
new file mode 100644
index 00000000000..ec8587d8de3
--- /dev/null
+++ b/cores/esp32/Tone.cpp
@@ -0,0 +1,152 @@
+#include <Arduino.h>
+#include "esp32-hal-ledc.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+
+#if SOC_LEDC_SUPPORTED
+static TaskHandle_t _tone_task = NULL;
+static QueueHandle_t _tone_queue = NULL;
+static int8_t _pin = -1;
+static uint8_t _channel = 255;
+
+typedef enum {
+  TONE_START,
+  TONE_END
+} tone_cmd_t;
+
+typedef struct {
+  tone_cmd_t tone_cmd;
+  uint8_t pin;
+  unsigned int frequency;
+  unsigned long duration;
+} tone_msg_t;
+
+#ifdef SOC_LEDC_SUPPORT_HS_MODE
+#define LEDC_CHANNELS (SOC_LEDC_CHANNEL_NUM << 1)
+#else
+#define LEDC_CHANNELS (SOC_LEDC_CHANNEL_NUM)
+#endif
+
+static void tone_task(void *) {
+  tone_msg_t tone_msg;
+  while (1) {
+    xQueueReceive(_tone_queue, &tone_msg, portMAX_DELAY);
+    switch (tone_msg.tone_cmd) {
+      case TONE_START:
+        log_d("Task received from queue TONE_START: pin=%d, frequency=%u Hz, duration=%lu ms", tone_msg.pin, tone_msg.frequency, tone_msg.duration);
+
+        if (_pin == -1) {
+          bool ret = true;
+          if (_channel == 255) {
+            ret = ledcAttach(tone_msg.pin, tone_msg.frequency, 10);
+          } else {
+            ret = ledcAttachChannel(tone_msg.pin, tone_msg.frequency, 10, _channel);
+          }
+          if (!ret) {
+            log_e("Tone start failed");
+            break;
+          }
+          _pin = tone_msg.pin;
+        }
+        ledcWriteTone(tone_msg.pin, tone_msg.frequency);
+
+        if (tone_msg.duration) {
+          delay(tone_msg.duration);
+          ledcWriteTone(tone_msg.pin, 0);
+        }
+        break;
+
+      case TONE_END:
+        log_d("Task received from queue TONE_END: pin=%d", tone_msg.pin);
+        ledcWriteTone(tone_msg.pin, 0);
+        ledcDetach(tone_msg.pin);
+        _pin = -1;
+        break;
+
+      default:;  // do nothing
+    }  // switch
+  }  // infinite loop
+}
+
+static int tone_init() {
+  if (_tone_queue == NULL) {
+    log_v("Creating tone queue");
+    _tone_queue = xQueueCreate(128, sizeof(tone_msg_t));
+    if (_tone_queue == NULL) {
+      log_e("Could not create tone queue");
+      return 0;  // ERR
+    }
+    log_v("Tone queue created");
+  }
+
+  if (_tone_task == NULL) {
+    log_v("Creating tone task");
+    xTaskCreate(
+      tone_task,   // Function to implement the task
+      "toneTask",  // Name of the task
+      3500,        // Stack size in words
+      NULL,        // Task input parameter
+      10,          // Priority of the task must be higher than Arduino task
+      &_tone_task  // Task handle.
+    );
+    if (_tone_task == NULL) {
+      log_e("Could not create tone task");
+      return 0;  // ERR
+    }
+    log_v("Tone task created");
+  }
+  return 1;  // OK
+}
+
+void noTone(uint8_t pin) {
+  log_d("noTone was called");
+  if (_pin == pin) {
+    if (tone_init()) {
+      tone_msg_t tone_msg = {
+        .tone_cmd = TONE_END,
+        .pin = pin,
+        .frequency = 0,  // Ignored
+        .duration = 0,   // Ignored
+      };
+      xQueueReset(_tone_queue);  // clear queue
+      xQueueSend(_tone_queue, &tone_msg, portMAX_DELAY);
+    }
+  } else {
+    log_e("Tone is not running on given pin %d", pin);
+  }
+}
+
+// parameters:
+// pin - pin number which will output the signal
+// frequency - PWM frequency in Hz
+// duration - time in ms - how long will the signal be outputted.
+//   If not provided, or 0 you must manually call noTone to end output
+void tone(uint8_t pin, unsigned int frequency, unsigned long duration) {
+  log_d("pin=%d, frequency=%u Hz, duration=%lu ms", pin, frequency, duration);
+  if (_pin == -1 || _pin == pin) {
+    if (tone_init()) {
+      tone_msg_t tone_msg = {
+        .tone_cmd = TONE_START,
+        .pin = pin,
+        .frequency = frequency,
+        .duration = duration,
+      };
+      xQueueSend(_tone_queue, &tone_msg, portMAX_DELAY);
+      return;
+    }
+  } else {
+    log_e("Tone is still running on pin %d, call noTone(%d) first!", _pin, _pin);
+    return;
+  }
+}
+
+void setToneChannel(uint8_t channel) {
+  if (channel >= LEDC_CHANNELS) {
+    log_e("Channel %u is not available (maximum %u)!", channel, LEDC_CHANNELS);
+    return;
+  }
+  _channel = channel;
+}
+
+#endif /* SOC_LEDC_SUPPORTED */
diff --git a/cores/esp32/USB.cpp b/cores/esp32/USB.cpp
new file mode 100644
index 00000000000..269e9a76cb3
--- /dev/null
+++ b/cores/esp32/USB.cpp
@@ -0,0 +1,358 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "USB.h"
+
+#if SOC_USB_OTG_SUPPORTED
+#if CONFIG_TINYUSB_ENABLED
+
+#include "pins_arduino.h"
+#include "esp32-hal.h"
+#include "esp32-hal-tinyusb.h"
+#include "common/tusb_common.h"
+#include "StreamString.h"
+#include "rom/ets_sys.h"
+#include "esp_mac.h"
+
+#ifndef USB_VID
+#define USB_VID USB_ESPRESSIF_VID
+#endif
+#ifndef USB_PID
+#define USB_PID 0x0002
+#endif
+#ifndef USB_MANUFACTURER
+#define USB_MANUFACTURER "Espressif Systems"
+#endif
+#ifndef USB_PRODUCT
+#define USB_PRODUCT ARDUINO_BOARD
+#endif
+#ifndef USB_SERIAL
+#if CONFIG_IDF_TARGET_ESP32S3
+#define USB_SERIAL "__MAC__"
+#else
+#define USB_SERIAL "0"
+#endif
+#endif
+#ifndef USB_WEBUSB_ENABLED
+#define USB_WEBUSB_ENABLED false
+#endif
+#ifndef USB_WEBUSB_URL
+#define USB_WEBUSB_URL "https://docs.espressif.com/projects/arduino-esp32/en/latest/_static/webusb.html"
+#endif
+
+#if CFG_TUD_DFU
+__attribute__((weak)) uint16_t load_dfu_ota_descriptor(uint8_t *dst, uint8_t *itf) {
+  return 0;
+}
+#elif CFG_TUD_DFU_RUNTIME
+static uint16_t load_dfu_descriptor(uint8_t *dst, uint8_t *itf) {
+#define DFU_ATTRS (DFU_ATTR_CAN_DOWNLOAD | DFU_ATTR_CAN_UPLOAD | DFU_ATTR_MANIFESTATION_TOLERANT)
+
+  uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB DFU_RT");
+  uint8_t descriptor[TUD_DFU_RT_DESC_LEN] = {// Interface number, string index, attributes, detach timeout, transfer size */
+                                             TUD_DFU_RT_DESCRIPTOR(*itf, str_index, DFU_ATTRS, 700, 64)
+  };
+  *itf += 1;
+  memcpy(dst, descriptor, TUD_DFU_RT_DESC_LEN);
+  return TUD_DFU_RT_DESC_LEN;
+}
+#endif /* CFG_TUD_DFU_RUNTIME */
+
+#if CFG_TUD_DFU_RUNTIME
+// Invoked on DFU_DETACH request to reboot to the bootloader
+void tud_dfu_runtime_reboot_to_dfu_cb(void) {
+  usb_persist_restart(RESTART_BOOTLOADER_DFU);
+}
+#endif /* CFG_TUD_DFU_RUNTIME */
+
+ESP_EVENT_DEFINE_BASE(ARDUINO_USB_EVENTS);
+
+static esp_event_loop_handle_t arduino_usb_event_loop_handle = NULL;
+
+esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait) {
+  if (arduino_usb_event_loop_handle == NULL) {
+    return ESP_FAIL;
+  }
+  return esp_event_post_to(arduino_usb_event_loop_handle, event_base, event_id, event_data, event_data_size, ticks_to_wait);
+}
+esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg) {
+  if (arduino_usb_event_loop_handle == NULL) {
+    return ESP_FAIL;
+  }
+  return esp_event_handler_register_with(arduino_usb_event_loop_handle, event_base, event_id, event_handler, event_handler_arg);
+}
+
+static bool tinyusb_device_mounted = false;
+static bool tinyusb_device_suspended = false;
+
+// Invoked when device is mounted (configured)
+void tud_mount_cb(void) {
+  tinyusb_device_mounted = true;
+  arduino_usb_event_data_t p;
+  p.suspend.remote_wakeup_en = 0;
+  arduino_usb_event_post(ARDUINO_USB_EVENTS, ARDUINO_USB_STARTED_EVENT, &p, sizeof(arduino_usb_event_data_t), portMAX_DELAY);
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void) {
+  tinyusb_device_mounted = false;
+  arduino_usb_event_data_t p;
+  p.suspend.remote_wakeup_en = 0;
+  arduino_usb_event_post(ARDUINO_USB_EVENTS, ARDUINO_USB_STOPPED_EVENT, &p, sizeof(arduino_usb_event_data_t), portMAX_DELAY);
+}
+
+// Invoked when usb bus is suspended
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en) {
+  tinyusb_device_suspended = true;
+  arduino_usb_event_data_t p;
+  p.suspend.remote_wakeup_en = remote_wakeup_en;
+  arduino_usb_event_post(ARDUINO_USB_EVENTS, ARDUINO_USB_SUSPEND_EVENT, &p, sizeof(arduino_usb_event_data_t), portMAX_DELAY);
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void) {
+  tinyusb_device_suspended = false;
+  arduino_usb_event_data_t p;
+  p.suspend.remote_wakeup_en = 0;
+  arduino_usb_event_post(ARDUINO_USB_EVENTS, ARDUINO_USB_RESUME_EVENT, &p, sizeof(arduino_usb_event_data_t), portMAX_DELAY);
+}
+
+ESPUSB::ESPUSB(size_t task_stack_size, uint8_t event_task_priority)
+  : vid(USB_VID), pid(USB_PID), product_name(USB_PRODUCT), manufacturer_name(USB_MANUFACTURER), serial_number(USB_SERIAL), fw_version(0x0100),
+    usb_version(0x0200)  // at least 2.1 or 3.x for BOS & webUSB
+    ,
+    usb_class(TUSB_CLASS_MISC), usb_subclass(MISC_SUBCLASS_COMMON), usb_protocol(MISC_PROTOCOL_IAD), usb_attributes(TUSB_DESC_CONFIG_ATT_SELF_POWERED),
+    usb_power_ma(500), webusb_enabled(USB_WEBUSB_ENABLED), webusb_url(USB_WEBUSB_URL), _started(false), _task_stack_size(task_stack_size),
+    _event_task_priority(event_task_priority) {
+  if (!arduino_usb_event_loop_handle) {
+    esp_event_loop_args_t event_task_args = {
+      .queue_size = 5,
+      .task_name = "arduino_usb_events",
+      .task_priority = _event_task_priority,
+      .task_stack_size = _task_stack_size,
+      .task_core_id = tskNO_AFFINITY
+    };
+    if (esp_event_loop_create(&event_task_args, &arduino_usb_event_loop_handle) != ESP_OK) {
+      log_e("esp_event_loop_create failed");
+    }
+  }
+}
+
+ESPUSB::~ESPUSB() {
+  if (arduino_usb_event_loop_handle) {
+    esp_event_loop_delete(arduino_usb_event_loop_handle);
+    arduino_usb_event_loop_handle = NULL;
+  }
+}
+
+bool ESPUSB::begin() {
+  if (!_started) {
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+    if (serial_number == "__MAC__") {
+      StreamString s;
+      uint8_t m[6];
+      esp_efuse_mac_get_default(m);
+      s.printf("%02X%02X%02X%02X%02X%02X", m[0], m[1], m[2], m[3], m[4], m[5]);
+      serial_number = s;
+    }
+#endif
+    tinyusb_device_config_t tinyusb_device_config = {
+      .vid = vid,
+      .pid = pid,
+      .product_name = product_name.c_str(),
+      .manufacturer_name = manufacturer_name.c_str(),
+      .serial_number = serial_number.c_str(),
+      .fw_version = fw_version,
+      .usb_version = usb_version,
+      .usb_class = usb_class,
+      .usb_subclass = usb_subclass,
+      .usb_protocol = usb_protocol,
+      .usb_attributes = usb_attributes,
+      .usb_power_ma = usb_power_ma,
+      .webusb_enabled = webusb_enabled,
+      .webusb_url = webusb_url.c_str()
+    };
+    _started = tinyusb_init(&tinyusb_device_config) == ESP_OK;
+  }
+  return _started;
+}
+
+void ESPUSB::onEvent(esp_event_handler_t callback) {
+  onEvent(ARDUINO_USB_ANY_EVENT, callback);
+}
+void ESPUSB::onEvent(arduino_usb_event_t event, esp_event_handler_t callback) {
+  arduino_usb_event_handler_register_with(ARDUINO_USB_EVENTS, event, callback, this);
+}
+
+ESPUSB::operator bool() const {
+  return _started && tinyusb_device_mounted;
+}
+
+bool ESPUSB::enableDFU() {
+#if CFG_TUD_DFU
+  return tinyusb_enable_interface(USB_INTERFACE_DFU, TUD_DFU_DESC_LEN(1), load_dfu_ota_descriptor) == ESP_OK;
+#elif CFG_TUD_DFU_RUNTIME
+  return tinyusb_enable_interface(USB_INTERFACE_DFU, TUD_DFU_RT_DESC_LEN, load_dfu_descriptor) == ESP_OK;
+#endif /* CFG_TUD_DFU_RUNTIME */
+  return false;
+}
+
+bool ESPUSB::VID(uint16_t v) {
+  if (!_started) {
+    vid = v;
+  }
+  return !_started;
+}
+uint16_t ESPUSB::VID(void) {
+  return vid;
+}
+
+bool ESPUSB::PID(uint16_t p) {
+  if (!_started) {
+    pid = p;
+  }
+  return !_started;
+}
+uint16_t ESPUSB::PID(void) {
+  return pid;
+}
+
+bool ESPUSB::firmwareVersion(uint16_t version) {
+  if (!_started) {
+    fw_version = version;
+  }
+  return !_started;
+}
+uint16_t ESPUSB::firmwareVersion(void) {
+  return fw_version;
+}
+
+bool ESPUSB::usbVersion(uint16_t version) {
+  if (!_started) {
+    usb_version = version;
+  }
+  return !_started;
+}
+uint16_t ESPUSB::usbVersion(void) {
+  return usb_version;
+}
+
+bool ESPUSB::usbPower(uint16_t mA) {
+  if (!_started) {
+    usb_power_ma = mA;
+  }
+  return !_started;
+}
+uint16_t ESPUSB::usbPower(void) {
+  return usb_power_ma;
+}
+
+bool ESPUSB::usbClass(uint8_t _class) {
+  if (!_started) {
+    usb_class = _class;
+  }
+  return !_started;
+}
+uint8_t ESPUSB::usbClass(void) {
+  return usb_class;
+}
+
+bool ESPUSB::usbSubClass(uint8_t subClass) {
+  if (!_started) {
+    usb_subclass = subClass;
+  }
+  return !_started;
+}
+uint8_t ESPUSB::usbSubClass(void) {
+  return usb_subclass;
+}
+
+bool ESPUSB::usbProtocol(uint8_t protocol) {
+  if (!_started) {
+    usb_protocol = protocol;
+  }
+  return !_started;
+}
+uint8_t ESPUSB::usbProtocol(void) {
+  return usb_protocol;
+}
+
+bool ESPUSB::usbAttributes(uint8_t attr) {
+  if (!_started) {
+    usb_attributes = attr;
+  }
+  return !_started;
+}
+uint8_t ESPUSB::usbAttributes(void) {
+  return usb_attributes;
+}
+
+bool ESPUSB::webUSB(bool enabled) {
+  if (!_started) {
+    webusb_enabled = enabled;
+    if (enabled && usb_version < 0x0210) {
+      usb_version = 0x0210;
+    }
+  }
+  return !_started;
+}
+bool ESPUSB::webUSB(void) {
+  return webusb_enabled;
+}
+
+bool ESPUSB::productName(const char *name) {
+  if (!_started) {
+    product_name = name;
+  }
+  return !_started;
+}
+const char *ESPUSB::productName(void) {
+  return product_name.c_str();
+}
+
+bool ESPUSB::manufacturerName(const char *name) {
+  if (!_started) {
+    manufacturer_name = name;
+  }
+  return !_started;
+}
+const char *ESPUSB::manufacturerName(void) {
+  return manufacturer_name.c_str();
+}
+
+bool ESPUSB::serialNumber(const char *name) {
+  if (!_started) {
+    serial_number = name;
+  }
+  return !_started;
+}
+const char *ESPUSB::serialNumber(void) {
+  return serial_number.c_str();
+}
+
+bool ESPUSB::webUSBURL(const char *name) {
+  if (!_started) {
+    webusb_url = name;
+  }
+  return !_started;
+}
+const char *ESPUSB::webUSBURL(void) {
+  return webusb_url.c_str();
+}
+
+ESPUSB USB;
+
+#endif /* CONFIG_TINYUSB_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/cores/esp32/USB.h b/cores/esp32/USB.h
new file mode 100644
index 00000000000..6d284937e00
--- /dev/null
+++ b/cores/esp32/USB.h
@@ -0,0 +1,122 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "sdkconfig.h"
+#if CONFIG_TINYUSB_ENABLED
+
+#include "esp_event.h"
+#include "USBCDC.h"
+
+#define ARDUINO_USB_ON_BOOT (ARDUINO_USB_CDC_ON_BOOT | ARDUINO_USB_MSC_ON_BOOT | ARDUINO_USB_DFU_ON_BOOT)
+
+ESP_EVENT_DECLARE_BASE(ARDUINO_USB_EVENTS);
+
+typedef enum {
+  ARDUINO_USB_ANY_EVENT = ESP_EVENT_ANY_ID,
+  ARDUINO_USB_STARTED_EVENT = 0,
+  ARDUINO_USB_STOPPED_EVENT,
+  ARDUINO_USB_SUSPEND_EVENT,
+  ARDUINO_USB_RESUME_EVENT,
+  ARDUINO_USB_MAX_EVENT,
+} arduino_usb_event_t;
+
+typedef union {
+  struct {
+    bool remote_wakeup_en;
+  } suspend;
+} arduino_usb_event_data_t;
+
+class ESPUSB {
+public:
+  ESPUSB(size_t event_task_stack_size = 2048, uint8_t event_task_priority = 5);
+  ~ESPUSB();
+
+  void onEvent(esp_event_handler_t callback);
+  void onEvent(arduino_usb_event_t event, esp_event_handler_t callback);
+
+  bool VID(uint16_t v);
+  uint16_t VID(void);
+
+  bool PID(uint16_t p);
+  uint16_t PID(void);
+
+  bool firmwareVersion(uint16_t version);
+  uint16_t firmwareVersion(void);
+
+  bool usbVersion(uint16_t version);
+  uint16_t usbVersion(void);
+
+  bool usbPower(uint16_t mA);
+  uint16_t usbPower(void);
+
+  bool usbClass(uint8_t _class);
+  uint8_t usbClass(void);
+
+  bool usbSubClass(uint8_t subClass);
+  uint8_t usbSubClass(void);
+
+  bool usbProtocol(uint8_t protocol);
+  uint8_t usbProtocol(void);
+
+  bool usbAttributes(uint8_t attr);
+  uint8_t usbAttributes(void);
+
+  bool webUSB(bool enabled);
+  bool webUSB(void);
+
+  bool productName(const char *name);
+  const char *productName(void);
+
+  bool manufacturerName(const char *name);
+  const char *manufacturerName(void);
+
+  bool serialNumber(const char *name);
+  const char *serialNumber(void);
+
+  bool webUSBURL(const char *name);
+  const char *webUSBURL(void);
+
+  bool enableDFU();
+  bool begin();
+  operator bool() const;
+
+private:
+  uint16_t vid;
+  uint16_t pid;
+  String product_name;
+  String manufacturer_name;
+  String serial_number;
+  uint16_t fw_version;
+  uint16_t usb_version;
+  uint8_t usb_class;
+  uint8_t usb_subclass;
+  uint8_t usb_protocol;
+  uint8_t usb_attributes;
+  uint16_t usb_power_ma;
+  bool webusb_enabled;
+  String webusb_url;
+
+  bool _started;
+  size_t _task_stack_size;
+  uint8_t _event_task_priority;
+};
+
+extern ESPUSB USB;
+
+#endif /* CONFIG_TINYUSB_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/cores/esp32/USBCDC.cpp b/cores/esp32/USBCDC.cpp
new file mode 100644
index 00000000000..c7bb4582d4f
--- /dev/null
+++ b/cores/esp32/USBCDC.cpp
@@ -0,0 +1,474 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "USBCDC.h"
+
+#if SOC_USB_OTG_SUPPORTED
+#include "USB.h"
+#if CONFIG_TINYUSB_CDC_ENABLED
+
+#include "esp32-hal-tinyusb.h"
+#include "rom/ets_sys.h"
+
+ESP_EVENT_DEFINE_BASE(ARDUINO_USB_CDC_EVENTS);
+esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait);
+esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg);
+
+USBCDC *devices[CFG_TUD_CDC];
+
+static uint16_t load_cdc_descriptor(uint8_t *dst, uint8_t *itf) {
+  uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB CDC");
+  uint8_t descriptor[TUD_CDC_DESC_LEN] = {// Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+                                          TUD_CDC_DESCRIPTOR(*itf, str_index, 0x85, CFG_TUD_ENDOINT_SIZE, 0x03, 0x84, CFG_TUD_ENDOINT_SIZE)
+  };
+  *itf += 2;
+  memcpy(dst, descriptor, TUD_CDC_DESC_LEN);
+  return TUD_CDC_DESC_LEN;
+}
+
+static uint16_t load_cdc_descriptor2(uint8_t *dst, uint8_t *itf) {
+  uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB CDC2");
+  uint8_t ep_ntfy = tinyusb_get_free_in_endpoint();
+  TU_VERIFY(ep_ntfy != 0);
+  uint8_t ep_in = tinyusb_get_free_in_endpoint();
+  TU_VERIFY(ep_in != 0);
+  uint8_t ep_out = tinyusb_get_free_out_endpoint();
+  TU_VERIFY(ep_out != 0);
+  uint8_t descriptor[TUD_CDC_DESC_LEN] = {
+    // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(*itf, str_index, (uint8_t)(0x80 | ep_ntfy), CFG_TUD_ENDOINT_SIZE, ep_out, (uint8_t)(0x80 | ep_in), CFG_TUD_ENDOINT_SIZE)
+  };
+  *itf += 2;
+  memcpy(dst, descriptor, TUD_CDC_DESC_LEN);
+  return TUD_CDC_DESC_LEN;
+}
+
+// Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) {
+  //log_v("ITF: %u, DTR: %u, RTS: %u", itf, dtr, rts);
+  if (itf < CFG_TUD_CDC && devices[itf] != NULL) {
+    devices[itf]->_onLineState(dtr, rts);
+  }
+}
+
+// Invoked when line coding is change via SET_LINE_CODING
+void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const *p_line_coding) {
+  //log_v("ITF: %u, BITRATE: %lu, STOP_BITS: %u, PARITY: %u, DATA_BITS: %u", itf, p_line_coding->bit_rate, p_line_coding->stop_bits, p_line_coding->parity, p_line_coding->data_bits);
+  if (itf < CFG_TUD_CDC && devices[itf] != NULL) {
+    devices[itf]->_onLineCoding(p_line_coding->bit_rate, p_line_coding->stop_bits, p_line_coding->parity, p_line_coding->data_bits);
+  }
+}
+
+// Invoked when received new data
+void tud_cdc_rx_cb(uint8_t itf) {
+  //log_v("ITF: %u", itf);
+  if (itf < CFG_TUD_CDC && devices[itf] != NULL) {
+    devices[itf]->_onRX();
+  }
+}
+
+// Invoked when received send break
+void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms) {
+  //log_v("itf: %u, duration_ms: %u", itf, duration_ms);
+}
+
+// Invoked when space becomes available in TX buffer
+void tud_cdc_tx_complete_cb(uint8_t itf) {
+  if (itf < CFG_TUD_CDC && devices[itf] != NULL) {
+    devices[itf]->_onTX();
+  }
+}
+
+static void ARDUINO_ISR_ATTR cdc0_write_char(char c) {
+  if (CFG_TUD_CDC && devices[0] != NULL) {
+    tud_cdc_n_write_char(0, c);
+  }
+}
+
+static void usb_unplugged_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  ((USBCDC *)arg)->_onUnplugged();
+}
+
+USBCDC::USBCDC(uint8_t itfn)
+  : itf(itfn), bit_rate(0), stop_bits(0), parity(0), data_bits(0), dtr(false), rts(false), connected(false), reboot_enable(true), rx_queue(NULL), tx_lock(NULL),
+    tx_timeout_ms(250) {
+  if (itf < CFG_TUD_CDC) {
+    if (itf == 0) {
+      tinyusb_enable_interface(USB_INTERFACE_CDC, TUD_CDC_DESC_LEN, load_cdc_descriptor);
+    } else {
+      tinyusb_enable_interface(USB_INTERFACE_CDC2, TUD_CDC_DESC_LEN, load_cdc_descriptor2);
+    }
+    arduino_usb_event_handler_register_with(ARDUINO_USB_EVENTS, ARDUINO_USB_STOPPED_EVENT, usb_unplugged_cb, this);
+  } else {
+    log_e("Maximum of %u CDC devices are supported", CFG_TUD_CDC);
+  }
+}
+
+USBCDC::~USBCDC() {
+  end();
+}
+
+void USBCDC::onEvent(esp_event_handler_t callback) {
+  onEvent(ARDUINO_USB_CDC_ANY_EVENT, callback);
+}
+void USBCDC::onEvent(arduino_usb_cdc_event_t event, esp_event_handler_t callback) {
+  arduino_usb_event_handler_register_with(ARDUINO_USB_CDC_EVENTS, event, callback, this);
+}
+
+size_t USBCDC::setRxBufferSize(size_t rx_queue_len) {
+  size_t currentQueueSize = rx_queue ? uxQueueSpacesAvailable(rx_queue) + uxQueueMessagesWaiting(rx_queue) : 0;
+
+  if (rx_queue_len != currentQueueSize) {
+    QueueHandle_t new_rx_queue = NULL;
+    if (rx_queue_len) {
+      new_rx_queue = xQueueCreate(rx_queue_len, sizeof(uint8_t));
+      if (!new_rx_queue) {
+        log_e("CDC Queue creation failed.");
+        return 0;
+      }
+      if (rx_queue) {
+        size_t copySize = uxQueueMessagesWaiting(rx_queue);
+        if (copySize > 0) {
+          for (size_t i = 0; i < copySize; i++) {
+            uint8_t ch = 0;
+            xQueueReceive(rx_queue, &ch, 0);
+            if (!xQueueSend(new_rx_queue, &ch, 0)) {
+              arduino_usb_cdc_event_data_t p;
+              p.rx_overflow.dropped_bytes = copySize - i;
+              arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_RX_OVERFLOW_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+              log_e("CDC RX Overflow.");
+              break;
+            }
+          }
+        }
+        vQueueDelete(rx_queue);
+      }
+      rx_queue = new_rx_queue;
+      return rx_queue_len;
+    } else {
+      if (rx_queue) {
+        vQueueDelete(rx_queue);
+        rx_queue = NULL;
+      }
+    }
+  }
+  return rx_queue_len;
+}
+
+void USBCDC::begin(unsigned long baud) {
+  if (itf >= CFG_TUD_CDC) {
+    return;
+  }
+  if (tx_lock == NULL) {
+    tx_lock = xSemaphoreCreateMutex();
+  }
+  // if rx_queue was set before begin(), keep it
+  if (!rx_queue) {
+    setRxBufferSize(256);  //default if not preset
+  }
+  devices[itf] = this;
+}
+
+void USBCDC::end() {
+  if (itf >= CFG_TUD_CDC) {
+    return;
+  }
+  connected = false;
+  devices[itf] = NULL;
+  setRxBufferSize(0);
+  if (tx_lock != NULL) {
+    vSemaphoreDelete(tx_lock);
+    tx_lock = NULL;
+  }
+}
+
+void USBCDC::setTxTimeoutMs(uint32_t timeout) {
+  tx_timeout_ms = timeout;
+}
+
+void USBCDC::_onUnplugged(void) {
+  if (connected) {
+    connected = false;
+    dtr = false;
+    rts = false;
+    arduino_usb_cdc_event_data_t p;
+    arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_DISCONNECTED_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+  }
+}
+
+enum {
+  CDC_LINE_IDLE,
+  CDC_LINE_1,
+  CDC_LINE_2,
+  CDC_LINE_3
+};
+void USBCDC::_onLineState(bool _dtr, bool _rts) {
+  static uint8_t lineState = CDC_LINE_IDLE;
+
+  if (dtr == _dtr && rts == _rts) {
+    return;  // Skip duplicate events
+  }
+
+  dtr = _dtr;
+  rts = _rts;
+
+  if (reboot_enable) {
+    if (!dtr && rts) {
+      if (lineState == CDC_LINE_IDLE) {
+        lineState++;
+        if (connected) {
+          connected = false;
+          arduino_usb_cdc_event_data_t p;
+          arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_DISCONNECTED_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+        }
+        // } else if(lineState == CDC_LINE_2){//esptool.js
+        //     lineState++;
+      } else {
+        lineState = CDC_LINE_IDLE;
+      }
+    } else if (dtr && rts) {
+      if (lineState == CDC_LINE_1) {
+        lineState++;
+      } else {
+        lineState = CDC_LINE_IDLE;
+      }
+    } else if (dtr && !rts) {
+      if (lineState == CDC_LINE_2) {
+        lineState++;
+        // } else if(lineState == CDC_LINE_IDLE){//esptool.js
+        //     lineState++;
+      } else {
+        lineState = CDC_LINE_IDLE;
+      }
+    } else if (!dtr && !rts) {
+      if (lineState == CDC_LINE_3) {
+        usb_persist_restart(RESTART_BOOTLOADER);
+      } else {
+        lineState = CDC_LINE_IDLE;
+      }
+    }
+  }
+
+  if (lineState == CDC_LINE_IDLE) {
+    if (dtr && rts && !connected) {
+      connected = true;
+      arduino_usb_cdc_event_data_t p;
+      arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_CONNECTED_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+    } else if (!dtr && connected) {
+      connected = false;
+      arduino_usb_cdc_event_data_t p;
+      arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_DISCONNECTED_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+    }
+    arduino_usb_cdc_event_data_t l;
+    l.line_state.dtr = dtr;
+    l.line_state.rts = rts;
+    arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_LINE_STATE_EVENT, &l, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+  }
+}
+
+void USBCDC::_onLineCoding(uint32_t _bit_rate, uint8_t _stop_bits, uint8_t _parity, uint8_t _data_bits) {
+  if (bit_rate != _bit_rate || data_bits != _data_bits || stop_bits != _stop_bits || parity != _parity) {
+    // ArduinoIDE sends LineCoding with 1200bps baud to reset the device
+    if (reboot_enable && _bit_rate == 1200) {
+      usb_persist_restart(RESTART_BOOTLOADER);
+    } else {
+      bit_rate = _bit_rate;
+      data_bits = _data_bits;
+      stop_bits = _stop_bits;
+      parity = _parity;
+      arduino_usb_cdc_event_data_t p;
+      p.line_coding.bit_rate = bit_rate;
+      p.line_coding.data_bits = data_bits;
+      p.line_coding.stop_bits = stop_bits;
+      p.line_coding.parity = parity;
+      arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_LINE_CODING_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+    }
+  }
+}
+
+void USBCDC::_onRX() {
+  arduino_usb_cdc_event_data_t p;
+  uint8_t buf[CONFIG_TINYUSB_CDC_RX_BUFSIZE + 1];
+  uint32_t count = tud_cdc_n_read(itf, buf, CONFIG_TINYUSB_CDC_RX_BUFSIZE);
+  for (uint32_t i = 0; i < count; i++) {
+    if (rx_queue == NULL || !xQueueSend(rx_queue, buf + i, 10)) {
+      p.rx_overflow.dropped_bytes = count - i;
+      arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_RX_OVERFLOW_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+      log_e("CDC RX Overflow.");
+      count = i;
+      break;
+    }
+  }
+  if (count) {
+    p.rx.len = count;
+    arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_RX_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+  }
+}
+
+void USBCDC::_onTX() {
+  arduino_usb_cdc_event_data_t p;
+  arduino_usb_event_post(ARDUINO_USB_CDC_EVENTS, ARDUINO_USB_CDC_TX_EVENT, &p, sizeof(arduino_usb_cdc_event_data_t), portMAX_DELAY);
+}
+
+void USBCDC::enableReboot(bool enable) {
+  reboot_enable = enable;
+}
+bool USBCDC::rebootEnabled(void) {
+  return reboot_enable;
+}
+
+int USBCDC::available(void) {
+  if (itf >= CFG_TUD_CDC || rx_queue == NULL) {
+    return -1;
+  }
+  return uxQueueMessagesWaiting(rx_queue);
+}
+
+int USBCDC::peek(void) {
+  if (itf >= CFG_TUD_CDC || rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c;
+  if (xQueuePeek(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+int USBCDC::read(void) {
+  if (itf >= CFG_TUD_CDC || rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  if (xQueueReceive(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+size_t USBCDC::read(uint8_t *buffer, size_t size) {
+  if (itf >= CFG_TUD_CDC || rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  size_t count = 0;
+  while (count < size && xQueueReceive(rx_queue, &c, 0)) {
+    buffer[count++] = c;
+  }
+  return count;
+}
+
+void USBCDC::flush(void) {
+  if (itf >= CFG_TUD_CDC || tx_lock == NULL || !tud_cdc_n_connected(itf)) {
+    return;
+  }
+  if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) {
+    return;
+  }
+  tud_cdc_n_write_flush(itf);
+  xSemaphoreGive(tx_lock);
+}
+
+int USBCDC::availableForWrite(void) {
+  if (itf >= CFG_TUD_CDC || tx_lock == NULL || !tud_cdc_n_connected(itf)) {
+    return 0;
+  }
+  if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) {
+    return 0;
+  }
+  size_t a = tud_cdc_n_write_available(itf);
+  xSemaphoreGive(tx_lock);
+  return a;
+}
+
+size_t USBCDC::write(const uint8_t *buffer, size_t size) {
+  if (itf >= CFG_TUD_CDC || tx_lock == NULL || buffer == NULL || size == 0 || !tud_cdc_n_connected(itf)) {
+    return 0;
+  }
+  if (xPortInIsrContext()) {
+    BaseType_t taskWoken = false;
+    if (xSemaphoreTakeFromISR(tx_lock, &taskWoken) != pdPASS) {
+      return 0;
+    }
+  } else if (xSemaphoreTake(tx_lock, tx_timeout_ms / portTICK_PERIOD_MS) != pdPASS) {
+    return 0;
+  }
+  size_t to_send = size, so_far = 0;
+  while (to_send) {
+    if (!tud_cdc_n_connected(itf)) {
+      size = so_far;
+      break;
+    }
+    size_t space = tud_cdc_n_write_available(itf);
+    if (!space) {
+      tud_cdc_n_write_flush(itf);
+      continue;
+    }
+    if (space > to_send) {
+      space = to_send;
+    }
+    size_t sent = tud_cdc_n_write(itf, buffer + so_far, space);
+    if (sent) {
+      so_far += sent;
+      to_send -= sent;
+      tud_cdc_n_write_flush(itf);
+    } else {
+      size = so_far;
+      break;
+    }
+  }
+  if (xPortInIsrContext()) {
+    BaseType_t taskWoken = false;
+    xSemaphoreGiveFromISR(tx_lock, &taskWoken);
+  } else {
+    xSemaphoreGive(tx_lock);
+  }
+  return size;
+}
+
+size_t USBCDC::write(uint8_t c) {
+  return write(&c, 1);
+}
+
+uint32_t USBCDC::baudRate() {
+  return bit_rate;
+}
+
+void USBCDC::setDebugOutput(bool en) {
+  if (itf) {
+    return;
+  }
+  if (en) {
+    uartSetDebug(NULL);
+    ets_install_putc2((void (*)(char)) & cdc0_write_char);
+  } else {
+    ets_install_putc2(NULL);
+  }
+  ets_install_putc1(NULL);  // closes UART log output
+}
+
+USBCDC::operator bool() const {
+  if (itf >= CFG_TUD_CDC) {
+    return false;
+  }
+  return connected;
+}
+
+#if !ARDUINO_USB_MODE && ARDUINO_USB_CDC_ON_BOOT  // Native USB CDC selected
+// USBSerial is always available to be used
+USBCDC USBSerial(0);
+#endif
+
+#endif /* CONFIG_TINYUSB_CDC_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/cores/esp32/USBCDC.h b/cores/esp32/USBCDC.h
new file mode 100644
index 00000000000..4221c37c351
--- /dev/null
+++ b/cores/esp32/USBCDC.h
@@ -0,0 +1,144 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "sdkconfig.h"
+#if CONFIG_TINYUSB_CDC_ENABLED
+
+#include <inttypes.h>
+#include "esp_event.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+#include "Stream.h"
+
+ESP_EVENT_DECLARE_BASE(ARDUINO_USB_CDC_EVENTS);
+
+typedef enum {
+  ARDUINO_USB_CDC_ANY_EVENT = ESP_EVENT_ANY_ID,
+  ARDUINO_USB_CDC_CONNECTED_EVENT = 0,
+  ARDUINO_USB_CDC_DISCONNECTED_EVENT,
+  ARDUINO_USB_CDC_LINE_STATE_EVENT,
+  ARDUINO_USB_CDC_LINE_CODING_EVENT,
+  ARDUINO_USB_CDC_RX_EVENT,
+  ARDUINO_USB_CDC_TX_EVENT,
+  ARDUINO_USB_CDC_RX_OVERFLOW_EVENT,
+  ARDUINO_USB_CDC_MAX_EVENT,
+} arduino_usb_cdc_event_t;
+
+typedef union {
+  struct {
+    bool dtr;
+    bool rts;
+  } line_state;
+  struct {
+    uint32_t bit_rate;
+    uint8_t stop_bits;  ///< 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits
+    uint8_t parity;     ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space
+    uint8_t data_bits;  ///< can be 5, 6, 7, 8 or 16
+  } line_coding;
+  struct {
+    size_t len;
+  } rx;
+  struct {
+    size_t dropped_bytes;
+  } rx_overflow;
+} arduino_usb_cdc_event_data_t;
+
+class USBCDC : public Stream {
+public:
+  USBCDC(uint8_t itf = 0);
+  ~USBCDC();
+
+  void onEvent(esp_event_handler_t callback);
+  void onEvent(arduino_usb_cdc_event_t event, esp_event_handler_t callback);
+
+  size_t setRxBufferSize(size_t size);
+  void setTxTimeoutMs(uint32_t timeout);
+  void begin(unsigned long baud = 0);
+  void end();
+
+  int available(void);
+  int availableForWrite(void);
+  int peek(void);
+  int read(void);
+  size_t read(uint8_t *buffer, size_t size);
+  size_t write(uint8_t);
+  size_t write(const uint8_t *buffer, size_t size);
+  void flush(void);
+
+  inline size_t read(char *buffer, size_t size) {
+    return read((uint8_t *)buffer, size);
+  }
+  inline size_t write(const char *buffer, size_t size) {
+    return write((uint8_t *)buffer, size);
+  }
+  inline size_t write(const char *s) {
+    return write((uint8_t *)s, strlen(s));
+  }
+  inline size_t write(unsigned long n) {
+    return write((uint8_t)n);
+  }
+  inline size_t write(long n) {
+    return write((uint8_t)n);
+  }
+  inline size_t write(unsigned int n) {
+    return write((uint8_t)n);
+  }
+  inline size_t write(int n) {
+    return write((uint8_t)n);
+  }
+  uint32_t baudRate();
+  void setDebugOutput(bool);
+  operator bool() const;
+
+  void enableReboot(bool enable);
+  bool rebootEnabled(void);
+
+  //internal methods
+  void _onDFU(void);
+  void _onLineState(bool _dtr, bool _rts);
+  void _onLineCoding(uint32_t _bit_rate, uint8_t _stop_bits, uint8_t _parity, uint8_t _data_bits);
+  void _onRX(void);
+  void _onTX(void);
+  void _onUnplugged(void);
+
+protected:
+  uint8_t itf;
+  uint32_t bit_rate;
+  uint8_t stop_bits;  ///< 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits
+  uint8_t parity;     ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space
+  uint8_t data_bits;  ///< can be 5, 6, 7, 8 or 16
+  bool dtr;
+  bool rts;
+  bool connected;
+  bool reboot_enable;
+  QueueHandle_t rx_queue;
+  SemaphoreHandle_t tx_lock;
+  uint32_t tx_timeout_ms;
+};
+
+#if !ARDUINO_USB_MODE && ARDUINO_USB_CDC_ON_BOOT  // Native USB CDC selected
+#ifndef USB_SERIAL_IS_DEFINED
+#define USB_SERIAL_IS_DEFINED 1
+#endif
+// USBSerial is always available to be used
+extern USBCDC USBSerial;
+#endif
+
+#endif /* CONFIG_TINYUSB_CDC_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/cores/esp32/USBMSC.cpp b/cores/esp32/USBMSC.cpp
new file mode 100644
index 00000000000..aeb79883f0d
--- /dev/null
+++ b/cores/esp32/USBMSC.cpp
@@ -0,0 +1,267 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "USBMSC.h"
+
+#if SOC_USB_OTG_SUPPORTED
+#if CONFIG_TINYUSB_MSC_ENABLED
+
+#include "esp32-hal-tinyusb.h"
+
+extern "C" uint16_t tusb_msc_load_descriptor(uint8_t *dst, uint8_t *itf) {
+  uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB MSC");
+  uint8_t ep_num = tinyusb_get_free_duplex_endpoint();
+  TU_VERIFY(ep_num != 0);
+  uint8_t descriptor[TUD_MSC_DESC_LEN] = {// Interface number, string index, EP Out & EP In address, EP size
+                                          TUD_MSC_DESCRIPTOR(*itf, str_index, ep_num, (uint8_t)(0x80 | ep_num), CFG_TUD_ENDOINT_SIZE)
+  };
+  *itf += 1;
+  memcpy(dst, descriptor, TUD_MSC_DESC_LEN);
+  return TUD_MSC_DESC_LEN;
+}
+
+typedef struct {
+  bool media_present;
+  bool is_writable;
+  uint8_t vendor_id[8];
+  uint8_t product_id[16];
+  uint8_t product_rev[4];
+  uint16_t block_size;
+  uint32_t block_count;
+  bool (*start_stop)(uint8_t power_condition, bool start, bool load_eject);
+  int32_t (*read)(uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize);
+  int32_t (*write)(uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize);
+} msc_lun_t;
+
+static const uint8_t MSC_MAX_LUN = 3;
+static uint8_t MSC_ACTIVE_LUN = 0;
+static msc_lun_t msc_luns[MSC_MAX_LUN];
+
+static void cplstr(void *dst, const void *src, size_t max_len) {
+  if (!src || !dst || !max_len) {
+    return;
+  }
+  size_t l = strlen((const char *)src);
+  if (l > max_len) {
+    l = max_len;
+  }
+  memcpy(dst, src, l);
+}
+
+// Invoked when received GET_MAX_LUN request, required for multiple LUNs implementation
+uint8_t tud_msc_get_maxlun_cb(void) {
+  log_v("%u", MSC_ACTIVE_LUN);
+  return MSC_ACTIVE_LUN;
+}
+
+// Invoked when received SCSI_CMD_INQUIRY
+// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively
+void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) {
+  log_v("[%u]", lun);
+  cplstr(vendor_id, msc_luns[lun].vendor_id, 8);
+  cplstr(product_id, msc_luns[lun].product_id, 16);
+  cplstr(product_rev, msc_luns[lun].product_rev, 4);
+}
+
+// Invoked when received Test Unit Ready command.
+// return true allowing host to read/write this LUN e.g SD card inserted
+bool tud_msc_test_unit_ready_cb(uint8_t lun) {
+  log_v("[%u]: %u", lun, msc_luns[lun].media_present);
+  return msc_luns[lun].media_present;  // RAM disk is always ready
+}
+
+// Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size
+// Application update block count and block size
+void tud_msc_capacity_cb(uint8_t lun, uint32_t *block_count, uint16_t *block_size) {
+  log_v("[%u]", lun);
+  if (!msc_luns[lun].media_present) {
+    *block_count = 0;
+    *block_size = 0;
+    return;
+  }
+
+  *block_count = msc_luns[lun].block_count;
+  *block_size = msc_luns[lun].block_size;
+}
+
+// Invoked when received Start Stop Unit command
+// - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage
+// - Start = 1 : active mode, if load_eject = 1 : load disk storage
+bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject) {
+  log_v("[%u] power: %u, start: %u, eject: %u", lun, power_condition, start, load_eject);
+  if (msc_luns[lun].start_stop) {
+    return msc_luns[lun].start_stop(power_condition, start, load_eject);
+  }
+  return true;
+}
+
+// Callback invoked when received READ10 command.
+// Copy disk's data to buffer (up to bufsize) and return number of copied bytes.
+int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize) {
+  log_v("[%u], lba: %u, offset: %u, bufsize: %u", lun, lba, offset, bufsize);
+  if (!msc_luns[lun].media_present) {
+    return 0;
+  }
+  if (msc_luns[lun].read) {
+    return msc_luns[lun].read(lba, offset, buffer, bufsize);
+  }
+  return 0;
+}
+
+// Callback invoked when received WRITE10 command.
+// Process data in buffer to disk's storage and return number of written bytes
+int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize) {
+  log_v("[%u], lba: %u, offset: %u, bufsize: %u", lun, lba, offset, bufsize);
+  if (!msc_luns[lun].media_present) {
+    return 0;
+  }
+  if (msc_luns[lun].write) {
+    return msc_luns[lun].write(lba, offset, buffer, bufsize);
+  }
+  return 0;
+}
+
+// Callback invoked when received an SCSI command not in built-in list below
+// - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE
+// - READ10 and WRITE10 has their own callbacks
+int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, uint16_t bufsize) {
+  // read10 & write10 has their own callback and MUST not be handled here
+  log_v("[%u] cmd: %u, bufsize: %u", lun, scsi_cmd[0], bufsize);
+
+  void const *response = NULL;
+  uint16_t resplen = 0;
+
+  // most scsi handled is input
+  bool in_xfer = true;
+
+  if (!msc_luns[lun].media_present) {
+    return -1;
+  }
+
+  switch (scsi_cmd[0]) {
+    case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
+      // Host is about to read/write etc ... better not to disconnect disk
+      resplen = 0;
+      break;
+
+    default:
+      // Set Sense = Invalid Command Operation
+      tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+
+      // negative means error -> tinyusb could stall and/or response with failed status
+      resplen = -1;
+      break;
+  }
+
+  // return resplen must not larger than bufsize
+  if (resplen > bufsize) {
+    resplen = bufsize;
+  }
+
+  if (response && (resplen > 0)) {
+    if (in_xfer) {
+      memcpy(buffer, response, resplen);
+    } else {
+      // SCSI output
+    }
+  }
+
+  return resplen;
+}
+
+bool tud_msc_is_writable_cb(uint8_t lun) {
+  log_v("[%u]: %u", lun, msc_luns[lun].is_writable);
+  return msc_luns[lun].is_writable;  // RAM disk is always ready
+}
+
+USBMSC::USBMSC() {
+  if (MSC_ACTIVE_LUN < MSC_MAX_LUN) {
+    _lun = MSC_ACTIVE_LUN;
+    MSC_ACTIVE_LUN++;
+    msc_luns[_lun].media_present = false;
+    msc_luns[_lun].is_writable = true;
+    msc_luns[_lun].vendor_id[0] = 0;
+    msc_luns[_lun].product_id[0] = 0;
+    msc_luns[_lun].product_rev[0] = 0;
+    msc_luns[_lun].block_size = 0;
+    msc_luns[_lun].block_count = 0;
+    msc_luns[_lun].start_stop = NULL;
+    msc_luns[_lun].read = NULL;
+    msc_luns[_lun].write = NULL;
+  }
+  if (_lun == 0) {
+    tinyusb_enable_interface(USB_INTERFACE_MSC, TUD_MSC_DESC_LEN, tusb_msc_load_descriptor);
+  }
+}
+
+USBMSC::~USBMSC() {
+  end();
+}
+
+bool USBMSC::begin(uint32_t block_count, uint16_t block_size) {
+  msc_luns[_lun].block_size = block_size;
+  msc_luns[_lun].block_count = block_count;
+  if (!msc_luns[_lun].block_size || !msc_luns[_lun].block_count || !msc_luns[_lun].read || !msc_luns[_lun].write) {
+    return false;
+  }
+  return true;
+}
+
+void USBMSC::end() {
+  msc_luns[_lun].media_present = false;
+  msc_luns[_lun].is_writable = false;
+  msc_luns[_lun].vendor_id[0] = 0;
+  msc_luns[_lun].product_id[0] = 0;
+  msc_luns[_lun].product_rev[0] = 0;
+  msc_luns[_lun].block_size = 0;
+  msc_luns[_lun].block_count = 0;
+  msc_luns[_lun].start_stop = NULL;
+  msc_luns[_lun].read = NULL;
+  msc_luns[_lun].write = NULL;
+}
+
+void USBMSC::vendorID(const char *vid) {
+  cplstr(msc_luns[_lun].vendor_id, vid, 8);
+}
+
+void USBMSC::productID(const char *pid) {
+  cplstr(msc_luns[_lun].product_id, pid, 16);
+}
+
+void USBMSC::productRevision(const char *rev) {
+  cplstr(msc_luns[_lun].product_rev, rev, 4);
+}
+
+void USBMSC::onStartStop(msc_start_stop_cb cb) {
+  msc_luns[_lun].start_stop = cb;
+}
+
+void USBMSC::onRead(msc_read_cb cb) {
+  msc_luns[_lun].read = cb;
+}
+
+void USBMSC::onWrite(msc_write_cb cb) {
+  msc_luns[_lun].write = cb;
+}
+
+void USBMSC::isWritable(bool is_writable) {
+  msc_luns[_lun].is_writable = is_writable;
+}
+
+void USBMSC::mediaPresent(bool media_present) {
+  msc_luns[_lun].media_present = media_present;
+}
+
+#endif /* CONFIG_TINYUSB_MSC_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/cores/esp32/USBMSC.h b/cores/esp32/USBMSC.h
new file mode 100644
index 00000000000..454aca3520a
--- /dev/null
+++ b/cores/esp32/USBMSC.h
@@ -0,0 +1,57 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "sdkconfig.h"
+
+#if CONFIG_TINYUSB_MSC_ENABLED
+
+// Invoked when received Start Stop Unit command
+// - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage
+// - Start = 1 : active mode, if load_eject = 1 : load disk storage
+typedef bool (*msc_start_stop_cb)(uint8_t power_condition, bool start, bool load_eject);
+
+// Copy disk's data to buffer (up to bufsize) and return number of copied bytes.
+typedef int32_t (*msc_read_cb)(uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize);
+
+// Process data in buffer to disk's storage and return number of written bytes
+typedef int32_t (*msc_write_cb)(uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize);
+
+class USBMSC {
+public:
+  USBMSC();
+  ~USBMSC();
+  bool begin(uint32_t block_count, uint16_t block_size);
+  void end();
+  void vendorID(const char *vid);         //max 8 chars
+  void productID(const char *pid);        //max 16 chars
+  void productRevision(const char *ver);  //max 4 chars
+  void mediaPresent(bool media_present);
+  void isWritable(bool is_writable);
+  void onStartStop(msc_start_stop_cb cb);
+  void onRead(msc_read_cb cb);
+  void onWrite(msc_write_cb cb);
+
+private:
+  uint8_t _lun;
+};
+
+#endif /* CONFIG_TINYUSB_MSC_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/cores/esp32/Udp.h b/cores/esp32/Udp.h
index fd79975eb0a..3d3daef3bf6 100644
--- a/cores/esp32/Udp.h
+++ b/cores/esp32/Udp.h
@@ -38,56 +38,57 @@
 #include <Stream.h>
 #include <IPAddress.h>
 
-class UDP: public Stream
-{
+class UDP : public Stream {
 
 public:
-    virtual uint8_t begin(uint16_t) =0;	// initialize, start listening on specified port. Returns 1 if successful, 0 if there are no sockets available to use
-    virtual uint8_t beginMulticast(IPAddress, uint16_t) { return 0; }  // initialize, start listening on specified multicast IP address and port. Returns 1 if successful, 0 on failure
-    virtual void stop() =0;  // Finish with the UDP socket
+  virtual uint8_t begin(uint16_t) = 0;  // initialize, start listening on specified port. Returns 1 if successful, 0 if there are no sockets available to use
+  virtual uint8_t beginMulticast(IPAddress, uint16_t) {
+    return 0;
+  }  // initialize, start listening on specified multicast IP address and port. Returns 1 if successful, 0 on failure
+  virtual void stop() = 0;  // Finish with the UDP socket
 
-    // Sending UDP packets
+  // Sending UDP packets
 
-    // Start building up a packet to send to the remote host specific in ip and port
-    // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port
-    virtual int beginPacket(IPAddress ip, uint16_t port) =0;
-    // Start building up a packet to send to the remote host specific in host and port
-    // Returns 1 if successful, 0 if there was a problem resolving the hostname or port
-    virtual int beginPacket(const char *host, uint16_t port) =0;
-    // Finish off this packet and send it
-    // Returns 1 if the packet was sent successfully, 0 if there was an error
-    virtual int endPacket() =0;
-    // Write a single byte into the packet
-    virtual size_t write(uint8_t) =0;
-    // Write size bytes from buffer into the packet
-    virtual size_t write(const uint8_t *buffer, size_t size) =0;
+  // Start building up a packet to send to the remote host specific in ip and port
+  // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port
+  virtual int beginPacket(IPAddress ip, uint16_t port) = 0;
+  // Start building up a packet to send to the remote host specific in host and port
+  // Returns 1 if successful, 0 if there was a problem resolving the hostname or port
+  virtual int beginPacket(const char *host, uint16_t port) = 0;
+  // Finish off this packet and send it
+  // Returns 1 if the packet was sent successfully, 0 if there was an error
+  virtual int endPacket() = 0;
+  // Write a single byte into the packet
+  virtual size_t write(uint8_t) = 0;
+  // Write size bytes from buffer into the packet
+  virtual size_t write(const uint8_t *buffer, size_t size) = 0;
 
-    // Start processing the next available incoming packet
-    // Returns the size of the packet in bytes, or 0 if no packets are available
-    virtual int parsePacket() =0;
-    // Number of bytes remaining in the current packet
-    virtual int available() =0;
-    // Read a single byte from the current packet
-    virtual int read() =0;
-    // Read up to len bytes from the current packet and place them into buffer
-    // Returns the number of bytes read, or 0 if none are available
-    virtual int read(unsigned char* buffer, size_t len) =0;
-    // Read up to len characters from the current packet and place them into buffer
-    // Returns the number of characters read, or 0 if none are available
-    virtual int read(char* buffer, size_t len) =0;
-    // Return the next byte from the current packet without moving on to the next byte
-    virtual int peek() =0;
-    virtual void flush() =0;	// Finish reading the current packet
+  // Start processing the next available incoming packet
+  // Returns the size of the packet in bytes, or 0 if no packets are available
+  virtual int parsePacket() = 0;
+  // Number of bytes remaining in the current packet
+  virtual int available() = 0;
+  // Read a single byte from the current packet
+  virtual int read() = 0;
+  // Read up to len bytes from the current packet and place them into buffer
+  // Returns the number of bytes read, or 0 if none are available
+  virtual int read(unsigned char *buffer, size_t len) = 0;
+  // Read up to len characters from the current packet and place them into buffer
+  // Returns the number of characters read, or 0 if none are available
+  virtual int read(char *buffer, size_t len) = 0;
+  // Return the next byte from the current packet without moving on to the next byte
+  virtual int peek() = 0;
+  virtual void flush() = 0;  // Finish reading the current packet
+
+  // Return the IP address of the host who sent the current incoming packet
+  virtual IPAddress remoteIP() = 0;
+  // Return the port of the host who sent the current incoming packet
+  virtual uint16_t remotePort() = 0;
 
-    // Return the IP address of the host who sent the current incoming packet
-    virtual IPAddress remoteIP() =0;
-    // Return the port of the host who sent the current incoming packet
-    virtual uint16_t remotePort() =0;
 protected:
-    uint8_t* rawIPAddress(IPAddress& addr)
-    {
-        return addr.raw_address();
-    }
+  uint8_t *rawIPAddress(IPAddress &addr) {
+    return addr.raw_address();
+  }
 };
 
 #endif
diff --git a/cores/esp32/WCharacter.h b/cores/esp32/WCharacter.h
index 53428873421..611d943e633 100644
--- a/cores/esp32/WCharacter.h
+++ b/cores/esp32/WCharacter.h
@@ -21,8 +21,8 @@
 #define Character_h
 
 #include <ctype.h>
-#define isascii(__c) ((unsigned)(__c)<=0177)
-#define toascii(__c)  ((__c)&0177)
+#define isascii(__c) ((unsigned)(__c) <= 0177)
+#define toascii(__c) ((__c) & 0177)
 
 // WCharacter.h prototypes
 inline boolean isAlphaNumeric(int c) __attribute__((always_inline));
@@ -44,94 +44,80 @@ inline int toUpperCase(int c) __attribute__((always_inline));
 
 // Checks for an alphanumeric character.
 // It is equivalent to (isalpha(c) || isdigit(c)).
-inline boolean isAlphaNumeric(int c)
-{
-    return (isalnum(c) == 0 ? false : true);
+inline boolean isAlphaNumeric(int c) {
+  return (isalnum(c) == 0 ? false : true);
 }
 
 // Checks for an alphabetic character.
 // It is equivalent to (isupper(c) || islower(c)).
-inline boolean isAlpha(int c)
-{
-    return (isalpha(c) == 0 ? false : true);
+inline boolean isAlpha(int c) {
+  return (isalpha(c) == 0 ? false : true);
 }
 
 // Checks whether c is a 7-bit unsigned char value
 // that fits into the ASCII character set.
-inline boolean isAscii(int c)
-{
-    return ( isascii (c) == 0 ? false : true);
+inline boolean isAscii(int c) {
+  return (isascii(c) == 0 ? false : true);
 }
 
 // Checks for a blank character, that is, a space or a tab.
-inline boolean isWhitespace(int c)
-{
-    return (isblank(c) == 0 ? false : true);
+inline boolean isWhitespace(int c) {
+  return (isblank(c) == 0 ? false : true);
 }
 
 // Checks for a control character.
-inline boolean isControl(int c)
-{
-    return (iscntrl(c) == 0 ? false : true);
+inline boolean isControl(int c) {
+  return (iscntrl(c) == 0 ? false : true);
 }
 
 // Checks for a digit (0 through 9).
-inline boolean isDigit(int c)
-{
-    return (isdigit(c) == 0 ? false : true);
+inline boolean isDigit(int c) {
+  return (isdigit(c) == 0 ? false : true);
 }
 
 // Checks for any printable character except space.
-inline boolean isGraph(int c)
-{
-    return (isgraph(c) == 0 ? false : true);
+inline boolean isGraph(int c) {
+  return (isgraph(c) == 0 ? false : true);
 }
 
 // Checks for a lower-case character.
-inline boolean isLowerCase(int c)
-{
-    return (islower(c) == 0 ? false : true);
+inline boolean isLowerCase(int c) {
+  return (islower(c) == 0 ? false : true);
 }
 
 // Checks for any printable character including space.
-inline boolean isPrintable(int c)
-{
-    return (isprint(c) == 0 ? false : true);
+inline boolean isPrintable(int c) {
+  return (isprint(c) == 0 ? false : true);
 }
 
 // Checks for any printable character which is not a space
 // or an alphanumeric character.
-inline boolean isPunct(int c)
-{
-    return (ispunct(c) == 0 ? false : true);
+inline boolean isPunct(int c) {
+  return (ispunct(c) == 0 ? false : true);
 }
 
 // Checks for white-space characters. For the avr-libc library,
 // these are: space, formfeed ('\f'), newline ('\n'), carriage
 // return ('\r'), horizontal tab ('\t'), and vertical tab ('\v').
-inline boolean isSpace(int c)
-{
-    return (isspace(c) == 0 ? false : true);
+inline boolean isSpace(int c) {
+  return (isspace(c) == 0 ? false : true);
 }
 
 // Checks for an uppercase letter.
-inline boolean isUpperCase(int c)
-{
-    return (isupper(c) == 0 ? false : true);
+inline boolean isUpperCase(int c) {
+  return (isupper(c) == 0 ? false : true);
 }
 
 // Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7
 // 8 9 a b c d e f A B C D E F.
-inline boolean isHexadecimalDigit(int c)
-{
-    return (isxdigit(c) == 0 ? false : true);
+inline boolean isHexadecimalDigit(int c) {
+  return (isxdigit(c) == 0 ? false : true);
 }
 
 // Converts c to a 7-bit unsigned char value that fits into the
 // ASCII character set, by clearing the high-order bits.
-inline int toAscii(int c)
-{
-    return toascii(c);
+inline int toAscii(int c) {
+  return toascii(c);
 }
 
 // Warning:
@@ -140,15 +126,13 @@ inline int toAscii(int c)
 // characters.
 
 // Converts the letter c to lower case, if possible.
-inline int toLowerCase(int c)
-{
-    return tolower(c);
+inline int toLowerCase(int c) {
+  return tolower(c);
 }
 
 // Converts the letter c to upper case, if possible.
-inline int toUpperCase(int c)
-{
-    return toupper(c);
+inline int toUpperCase(int c) {
+  return toupper(c);
 }
 
 #endif
diff --git a/cores/esp32/WMath.cpp b/cores/esp32/WMath.cpp
index d351b194e23..13b736a17e5 100644
--- a/cores/esp32/WMath.cpp
+++ b/cores/esp32/WMath.cpp
@@ -27,58 +27,63 @@ extern "C" {
 #include <stdlib.h>
 #include "esp_system.h"
 }
+#include "esp32-hal-log.h"
+#include "esp_random.h"
 
-void randomSeed(unsigned long seed)
-{
-    if(seed != 0) {
-        srand(seed);
-    }
+// Allows the user to choose between Real Hardware
+// or Software Pseudo random generators for the
+// Arduino random() functions
+static bool s_useRandomHW = true;
+void useRealRandomGenerator(bool useRandomHW) {
+  s_useRandomHW = useRandomHW;
 }
 
-long random(long howbig)
-{
-    uint32_t x = esp_random();
-    uint64_t m = uint64_t(x) * uint64_t(howbig);
-    uint32_t l = uint32_t(m);
-    if (l < howbig) {
-        uint32_t t = -howbig;
-        if (t >= howbig) {
-            t -= howbig;
-            if (t >= howbig)
-                t %= howbig;
-        }
-        while (l < t) {
-            x = esp_random();
-            m = uint64_t(x) * uint64_t(howbig);
-            l = uint32_t(m);
-        }
-    }
-    return m >> 32;
+// Calling randomSeed() will force the
+// Pseudo Random generator like in
+// Arduino mainstream API
+void randomSeed(unsigned long seed) {
+  if (seed != 0) {
+    srand(seed);
+    s_useRandomHW = false;
+  }
 }
 
-long random(long howsmall, long howbig)
-{
-    if(howsmall >= howbig) {
-        return howsmall;
-    }
-    long diff = howbig - howsmall;
-    return random(diff) + howsmall;
+long random(long howsmall, long howbig);
+long random(long howbig) {
+  if (howbig == 0) {
+    return 0;
+  }
+  if (howbig < 0) {
+    return (random(0, -howbig));
+  }
+  // if randomSeed was called, fall back to software PRNG
+  uint32_t val = (s_useRandomHW) ? esp_random() : rand();
+  return val % howbig;
 }
 
-long map(long x, long in_min, long in_max, long out_min, long out_max) {
-    const long dividend = out_max - out_min;
-    const long divisor = in_max - in_min;
-    const long delta = x - in_min;
+long random(long howsmall, long howbig) {
+  if (howsmall >= howbig) {
+    return howsmall;
+  }
+  long diff = howbig - howsmall;
+  return random(diff) + howsmall;
+}
 
-    return (delta * dividend + (divisor / 2)) / divisor + out_min;
+long map(long x, long in_min, long in_max, long out_min, long out_max) {
+  const long run = in_max - in_min;
+  if (run == 0) {
+    log_e("map(): Invalid input range, min == max");
+    return -1;  // AVR returns -1, SAM returns 0
+  }
+  const long rise = out_max - out_min;
+  const long delta = x - in_min;
+  return (delta * rise) / run + out_min;
 }
 
-unsigned int makeWord(unsigned int w)
-{
-    return w;
+uint16_t makeWord(uint16_t w) {
+  return w;
 }
 
-unsigned int makeWord(unsigned char h, unsigned char l)
-{
-    return (h << 8) | l;
+uint16_t makeWord(uint8_t h, uint8_t l) {
+  return (h << 8) | l;
 }
diff --git a/cores/esp32/WString.cpp b/cores/esp32/WString.cpp
index aee4b1c94bd..18e64767545 100644
--- a/cores/esp32/WString.cpp
+++ b/cores/esp32/WString.cpp
@@ -21,839 +21,905 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#include <Arduino.h>
+#include "Arduino.h"
 #include "WString.h"
 #include "stdlib_noniso.h"
+#include "esp32-hal-log.h"
 
 /*********************************************/
 /*  Constructors                             */
 /*********************************************/
 
 String::String(const char *cstr) {
-    init();
-    if (cstr)
-        copy(cstr, strlen(cstr));
+  init();
+  if (cstr) {
+    copy(cstr, strlen(cstr));
+  }
 }
 
-String::String(const String &value) {
-    init();
-    *this = value;
+String::String(const char *cstr, unsigned int length) {
+  init();
+  if (cstr) {
+    copy(cstr, length);
+  }
 }
 
-String::String(const __FlashStringHelper *pstr) {
-    init();
-    *this = pstr; // see operator =
+String::String(const String &value) {
+  init();
+  *this = value;
 }
 
 #ifdef __GXX_EXPERIMENTAL_CXX0X__
 String::String(String &&rval) {
-    init();
-    move(rval);
+  init();
+  move(rval);
 }
 
 String::String(StringSumHelper &&rval) {
-    init();
-    move(rval);
+  init();
+  move(rval);
 }
 #endif
 
 String::String(char c) {
-    init();
-    char buf[2];
-    buf[0] = c;
-    buf[1] = 0;
-    *this = buf;
+  init();
+  char buf[] = {c, '\0'};
+  *this = buf;
 }
 
 String::String(unsigned char value, unsigned char base) {
-    init();
-    char buf[1 + 8 * sizeof(unsigned char)];
-    utoa(value, buf, base);
-    *this = buf;
+  init();
+  char buf[1 + 8 * sizeof(unsigned char)];
+  utoa(value, buf, base);
+  *this = buf;
 }
 
 String::String(int value, unsigned char base) {
-    init();
-    char buf[2 + 8 * sizeof(int)];
-    if (base == 10) {
-        sprintf(buf, "%d", value);
-    } else {
-        itoa(value, buf, base);
-    }
-    *this = buf;
+  init();
+  char buf[2 + 8 * sizeof(int)];
+  itoa(value, buf, base);
+  *this = buf;
 }
 
 String::String(unsigned int value, unsigned char base) {
-    init();
-    char buf[1 + 8 * sizeof(unsigned int)];
-    utoa(value, buf, base);
-    *this = buf;
+  init();
+  char buf[1 + 8 * sizeof(unsigned int)];
+  utoa(value, buf, base);
+  *this = buf;
 }
 
 String::String(long value, unsigned char base) {
-    init();
-    char buf[2 + 8 * sizeof(long)];
-    if (base==10) {
-        sprintf(buf, "%ld", value);
-    } else {
-        ltoa(value, buf, base);
-    }
-    *this = buf;
+  init();
+  char buf[2 + 8 * sizeof(long)];
+  ltoa(value, buf, base);
+  *this = buf;
 }
 
 String::String(unsigned long value, unsigned char base) {
-    init();
-    char buf[1 + 8 * sizeof(unsigned long)];
-    ultoa(value, buf, base);
-    *this = buf;
+  init();
+  char buf[1 + 8 * sizeof(unsigned long)];
+  ultoa(value, buf, base);
+  *this = buf;
 }
 
-String::String(float value, unsigned char decimalPlaces) {
-    init();
-    char buf[33];
+String::String(float value, unsigned int decimalPlaces) {
+  init();
+  char *buf = (char *)malloc(decimalPlaces + 42);
+  if (buf) {
     *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);
+    free(buf);
+  } else {
+    *this = "nan";
+    log_e("No enough memory for the operation.");
+  }
 }
 
-String::String(double value, unsigned char decimalPlaces) {
-    init();
-    char buf[33];
+String::String(double value, unsigned int decimalPlaces) {
+  init();
+  char *buf = (char *)malloc(decimalPlaces + 312);
+  if (buf) {
     *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);
+    free(buf);
+  } else {
+    *this = "nan";
+    log_e("No enough memory for the operation.");
+  }
+}
+
+String::String(long long value, unsigned char base) {
+  init();
+  char buf[2 + 8 * sizeof(long long)];
+  lltoa(value, buf, base);
+  *this = buf;
+}
+
+String::String(unsigned long long value, unsigned char base) {
+  init();
+  char buf[1 + 8 * sizeof(unsigned long long)];
+  ulltoa(value, buf, base);
+  *this = buf;
 }
 
 String::~String() {
-    invalidate();
+  invalidate();
 }
 
-// /*********************************************/
-// /*  Memory Management                        */
-// /*********************************************/
+/*********************************************/
+/*  Memory Management                        */
+/*********************************************/
 
 inline void String::init(void) {
-    setSSO(false);
-    setCapacity(0);
-    setLen(0);
-    setBuffer(nullptr);
+  setSSO(false);
+  setBuffer(nullptr);
+  setCapacity(0);
+  setLen(0);
 }
 
 void String::invalidate(void) {
-    if(!isSSO() && wbuffer())
-        free(wbuffer());
-    init();
-}
-
-unsigned char String::reserve(unsigned int size) {
-    if(buffer() && capacity() >= size)
-        return 1;
-    if(changeBuffer(size)) {
-        if(len() == 0)
-            wbuffer()[0] = 0;
-        return 1;
+  if (!isSSO() && wbuffer()) {
+    free(wbuffer());
+  }
+  init();
+}
+
+bool String::reserve(unsigned int size) {
+  if (buffer() && capacity() >= size) {
+    return true;
+  }
+  if (changeBuffer(size)) {
+    if (len() == 0) {
+      wbuffer()[0] = 0;
     }
-    return 0;
-}
-
-unsigned char String::changeBuffer(unsigned int maxStrLen) {
-    // Can we use SSO here to avoid allocation?
-    if (maxStrLen < sizeof(sso.buff) - 1) {
-        if (isSSO() || !buffer()) {
-            // Already using SSO, nothing to do
-	    uint16_t oldLen = len();
-            setSSO(true);
-	    setLen(oldLen);
-            return 1;
-        } else { // if bufptr && !isSSO()
-            // Using bufptr, need to shrink into sso.buff
-            char temp[sizeof(sso.buff)];
-            memcpy(temp, buffer(), maxStrLen);
-            free(wbuffer());
-            uint16_t oldLen = len();
-            setSSO(true);
-	    setLen(oldLen);
-            memcpy(wbuffer(), temp, maxStrLen);
-            return 1;
-        }
+    return true;
+  }
+  return false;
+}
+
+bool String::changeBuffer(unsigned int maxStrLen) {
+  // Can we use SSO here to avoid allocation?
+  if (maxStrLen < sizeof(sso.buff) - 1) {
+    if (isSSO() || !buffer()) {
+      // Already using SSO, nothing to do
+      uint16_t oldLen = len();
+      setSSO(true);
+      setLen(oldLen);
+    } else {  // if bufptr && !isSSO()
+      // Using bufptr, need to shrink into sso.buff
+      char temp[sizeof(sso.buff)];
+      memcpy(temp, buffer(), maxStrLen);
+      free(wbuffer());
+      uint16_t oldLen = len();
+      setSSO(true);
+      memcpy(wbuffer(), temp, maxStrLen);
+      setLen(oldLen);
     }
-    // Fallthrough to normal allocator
-    size_t newSize = (maxStrLen + 16) & (~0xf);
-    // Make sure we can fit newsize in the buffer
-    if (newSize > CAPACITY_MAX) {
-        return false;
+    return true;
+  }
+  // Fallthrough to normal allocator
+  size_t newSize = (maxStrLen + 16) & (~0xf);
+  // Make sure we can fit newsize in the buffer
+  if (newSize > CAPACITY_MAX) {
+    return false;
+  }
+  uint16_t oldLen = len();
+  char *newbuffer = (char *)realloc(isSSO() ? nullptr : wbuffer(), newSize);
+  if (newbuffer) {
+    size_t oldSize = capacity() + 1;  // include NULL.
+    if (isSSO()) {
+      // Copy the SSO buffer into allocated space
+      memmove(newbuffer, sso.buff, sizeof(sso.buff));
     }
-    uint16_t oldLen = len();
-    char *newbuffer = (char *) realloc(isSSO() ? nullptr : wbuffer(), newSize);
-    if (newbuffer) {
-        size_t oldSize = capacity() + 1; // include NULL.
-        if (isSSO()) {
-            // Copy the SSO buffer into allocated space
-            memmove(newbuffer, sso.buff, sizeof(sso.buff));
-        }
-        if (newSize > oldSize)
-        {
-            memset(newbuffer + oldSize, 0, newSize - oldSize);
-        }
-        setSSO(false);
-        setCapacity(newSize - 1);
-        setLen(oldLen); // Needed in case of SSO where len() never existed
-        setBuffer(newbuffer);
-        return 1;
+    if (newSize > oldSize) {
+      memset(newbuffer + oldSize, 0, newSize - oldSize);
     }
-    return 0;
+    setSSO(false);
+    setCapacity(newSize - 1);
+    setBuffer(newbuffer);
+    setLen(oldLen);  // Needed in case of SSO where len() never existed
+    return true;
+  }
+  return false;
 }
 
-// /*********************************************/
-// /*  Copy and Move                            */
-// /*********************************************/
-
-String & String::copy(const char *cstr, unsigned int length) {
-    if(!reserve(length)) {
-        invalidate();
-        return *this;
-    }
-    setLen(length);
-    memmove(wbuffer(), cstr, length + 1);
-    return *this;
-}
+/*********************************************/
+/*  Copy and Move                            */
+/*********************************************/
 
-String & String::copy(const __FlashStringHelper *pstr, unsigned int length) {
-    if (!reserve(length)) {
-        invalidate();
-        return *this;
-    }
-    setLen(length);
-    memcpy_P(wbuffer(), (PGM_P)pstr, length + 1); // We know wbuffer() cannot ever be in PROGMEM, so memcpy safe here
+String &String::copy(const char *cstr, unsigned int length) {
+  if (cstr == nullptr || !reserve(length)) {
+    invalidate();
     return *this;
+  }
+  memmove(wbuffer(), cstr, length);
+  setLen(length);
+  return *this;
 }
 
 #ifdef __GXX_EXPERIMENTAL_CXX0X__
 void String::move(String &rhs) {
-    if(buffer()) {
-        if(capacity() >= rhs.len()) {
-            memmove(wbuffer(), rhs.buffer(), rhs.length() + 1);
-            setLen(rhs.len());
-	    rhs.invalidate();
-            return;
-        } else {
-            if (!isSSO()) {
-                free(wbuffer());
-                setBuffer(nullptr);
-            }
-        }
+  if (buffer()) {
+    if (capacity() >= rhs.len()) {
+      // Use case: When 'reserve()' was called and the first
+      // assignment/append is the return value of a function.
+      if (rhs.len() && rhs.buffer()) {
+        memmove(wbuffer(), rhs.buffer(), rhs.length());
+      }
+      setLen(rhs.len());
+      rhs.invalidate();
+      return;
     }
-    if (rhs.isSSO()) {
-        setSSO(true);
-        memmove(sso.buff, rhs.sso.buff, sizeof(sso.buff));
-    } else {
-        setSSO(false);
-        setBuffer(rhs.wbuffer());
+    if (!isSSO()) {
+      free(wbuffer());
+      setBuffer(nullptr);
     }
-    setCapacity(rhs.capacity());
-    setLen(rhs.len());
-    rhs.setSSO(false);
-    rhs.setCapacity(0);
-    rhs.setLen(0);
-    rhs.setBuffer(nullptr);
+  }
+  if (rhs.isSSO()) {
+    setSSO(true);
+    memmove(sso.buff, rhs.sso.buff, sizeof(sso.buff));
+  } else {
+    setSSO(false);
+    setBuffer(rhs.wbuffer());
+  }
+  setCapacity(rhs.capacity());
+  setLen(rhs.len());
+  rhs.init();
 }
 #endif
 
-String & String::operator =(const String &rhs) {
-    if(this == &rhs)
-        return *this;
-
-    if(rhs.buffer())
-        copy(rhs.buffer(), rhs.len());
-    else
-        invalidate();
-
+String &String::operator=(const String &rhs) {
+  if (this == &rhs) {
     return *this;
+  }
+  return copy(rhs.buffer(), rhs.len());
 }
 
 #ifdef __GXX_EXPERIMENTAL_CXX0X__
-String & String::operator =(String &&rval) {
-    if(this != &rval)
-        move(rval);
-    return *this;
+String &String::operator=(String &&rval) {
+  if (this != &rval) {
+    move(rval);
+  }
+  return *this;
 }
 
-String & String::operator =(StringSumHelper &&rval) {
-    if(this != &rval)
-        move(rval);
-    return *this;
+String &String::operator=(StringSumHelper &&rval) {
+  if (this != &rval) {
+    move(rval);
+  }
+  return *this;
 }
 #endif
 
-String & String::operator =(const char *cstr) {
-    if(cstr)
-        copy(cstr, strlen(cstr));
-    else
-        invalidate();
-
-    return *this;
+String &String::operator=(const char *cstr) {
+  const uint32_t length = cstr ? strlen(cstr) : 0u;
+  return copy(cstr, length);
 }
 
-String & String::operator = (const __FlashStringHelper *pstr)
-{
-    if (pstr) copy(pstr, strlen_P((PGM_P)pstr));
-    else invalidate();
+/*********************************************/
+/*  concat                                   */
+/*********************************************/
 
-    return *this;
+bool String::concat(const String &s) {
+  // Special case if we're concatting ourself (s += s;) since we may end up
+  // realloc'ing the buffer and moving s.buffer in the method called
+  if (&s == this) {
+    if (s.len() == 0) {
+      return true;
+    }
+    if (!s.buffer()) {
+      return false;
+    }
+    unsigned int newlen = 2 * len();
+    if (!reserve(newlen)) {
+      return false;
+    }
+    memmove(wbuffer() + len(), buffer(), len());
+    setLen(newlen);
+    return true;
+  }
+  return concat(s.buffer(), s.len());
 }
 
-// /*********************************************/
-// /*  concat                                   */
-// /*********************************************/
-
-unsigned char String::concat(const String &s) {
-    // Special case if we're concatting ourself (s += s;) since we may end up
-    // realloc'ing the buffer and moving s.buffer in the method called
-    if (&s == this) {
-        unsigned int newlen = 2 * len();
-        if (!s.buffer())
-            return 0;
-        if (s.len() == 0)
-            return 1;
-        if (!reserve(newlen))
-            return 0;
-        memmove(wbuffer() + len(), buffer(), len());
-        setLen(newlen);
-        wbuffer()[len()] = 0;
-        return 1;
-    } else {
-        return concat(s.buffer(), s.len());
-    }
+bool String::concat(const char *cstr, unsigned int length) {
+  unsigned int newlen = len() + length;
+  if (!cstr) {
+    return false;
+  }
+  if (length == 0) {
+    return true;
+  }
+  if (!reserve(newlen)) {
+    return false;
+  }
+  if (cstr >= wbuffer() && cstr < wbuffer() + len()) {
+    // compatible with SSO in ram #6155 (case "x += x.c_str()")
+    memmove(wbuffer() + len(), cstr, length);
+  } else {
+    // compatible with source in flash #6367
+    memcpy_P(wbuffer() + len(), cstr, length);
+  }
+  setLen(newlen);
+  return true;
 }
 
-unsigned char String::concat(const char *cstr, unsigned int length) {
-    unsigned int newlen = len() + length;
-    if(!cstr)
-        return 0;
-    if(length == 0)
-        return 1;
-    if(!reserve(newlen))
-        return 0;
-    if (cstr >= wbuffer() && cstr < wbuffer() + len())
-        // compatible with SSO in ram #6155 (case "x += x.c_str()")
-        memmove(wbuffer() + len(), cstr, length + 1);
-    else
-        // compatible with source in flash #6367
-        memcpy_P(wbuffer() + len(), cstr, length + 1);
-    setLen(newlen);
-    return 1;
+bool String::concat(const char *cstr) {
+  if (!cstr) {
+    return false;
+  }
+  return concat(cstr, strlen(cstr));
 }
 
-unsigned char String::concat(const char *cstr) {
-    if(!cstr)
-        return 0;
-    return concat(cstr, strlen(cstr));
+bool String::concat(char c) {
+  char buf[] = {c, '\0'};
+  return concat(buf, 1);
 }
 
-unsigned char String::concat(char c) {
-    char buf[2];
-    buf[0] = c;
-    buf[1] = 0;
-    return concat(buf, 1);
+bool String::concat(unsigned char num) {
+  char buf[1 + 3 * sizeof(unsigned char)];
+  utoa(num, buf, 10);
+  return concat(buf, strlen(buf));
 }
 
-unsigned char String::concat(unsigned char num) {
-    char buf[1 + 3 * sizeof(unsigned char)];
-    sprintf(buf, "%d", num);
-    return concat(buf, strlen(buf));
+bool String::concat(int num) {
+  char buf[2 + 3 * sizeof(int)];
+  itoa(num, buf, 10);
+  return concat(buf, strlen(buf));
 }
 
-unsigned char String::concat(int num) {
-    char buf[2 + 3 * sizeof(int)];
-    sprintf(buf, "%d", num);
-    return concat(buf, strlen(buf));
+bool String::concat(unsigned int num) {
+  char buf[1 + 3 * sizeof(unsigned int)];
+  utoa(num, buf, 10);
+  return concat(buf, strlen(buf));
 }
 
-unsigned char String::concat(unsigned int num) {
-    char buf[1 + 3 * sizeof(unsigned int)];
-    utoa(num, buf, 10);
-    return concat(buf, strlen(buf));
+bool String::concat(long num) {
+  char buf[2 + 3 * sizeof(long)];
+  ltoa(num, buf, 10);
+  return concat(buf, strlen(buf));
 }
 
-unsigned char String::concat(long num) {
-    char buf[2 + 3 * sizeof(long)];
-    sprintf(buf, "%ld", num);
-    return concat(buf, strlen(buf));
+bool String::concat(unsigned long num) {
+  char buf[1 + 3 * sizeof(unsigned long)];
+  ultoa(num, buf, 10);
+  return concat(buf, strlen(buf));
 }
 
-unsigned char String::concat(unsigned long num) {
-    char buf[1 + 3 * sizeof(unsigned long)];
-    ultoa(num, buf, 10);
-    return concat(buf, strlen(buf));
+bool String::concat(long long num) {
+  char buf[2 + 3 * sizeof(long long)];
+  lltoa(num, buf, 10);
+  return concat(buf, strlen(buf));
 }
 
-unsigned char String::concat(float num) {
-    char buf[20];
-    char* string = dtostrf(num, 4, 2, buf);
-    return concat(string, strlen(string));
+bool String::concat(unsigned long long num) {
+  char buf[1 + 3 * sizeof(unsigned long long)];
+  ulltoa(num, buf, 10);
+  return concat(buf, strlen(buf));
 }
 
-unsigned char String::concat(double num) {
-    char buf[20];
-    char* string = dtostrf(num, 4, 2, buf);
-    return concat(string, strlen(string));
+bool String::concat(float num) {
+  char buf[20];
+  char *string = dtostrf(num, 4, 2, buf);
+  return concat(string, strlen(string));
 }
 
-unsigned char String::concat(const __FlashStringHelper * str) {
-    if (!str) return 0;
-    int length = strlen_P((PGM_P)str);
-    if (length == 0) return 1;
-    unsigned int newlen = len() + length;
-    if (!reserve(newlen)) return 0;
-    memcpy_P(wbuffer() + len(), (PGM_P)str, length + 1);
-    setLen(newlen);
-    return 1;
+bool String::concat(double num) {
+  char buf[20];
+  char *string = dtostrf(num, 4, 2, buf);
+  return concat(string, strlen(string));
 }
 
 /*********************************************/
 /*  Concatenate                              */
 /*********************************************/
 
-StringSumHelper & operator +(const StringSumHelper &lhs, const String &rhs) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!a.concat(rhs.buffer(), rhs.len()))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, const String &rhs) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(rhs.buffer(), rhs.len())) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator +(const StringSumHelper &lhs, const char *cstr) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!cstr || !a.concat(cstr, strlen(cstr)))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, const char *cstr) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!cstr || !a.concat(cstr, strlen(cstr))) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator +(const StringSumHelper &lhs, char c) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!a.concat(c))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, char c) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(c)) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator +(const StringSumHelper &lhs, unsigned char num) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!a.concat(num))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, unsigned char num) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(num)) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator +(const StringSumHelper &lhs, int num) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!a.concat(num))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, int num) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(num)) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator +(const StringSumHelper &lhs, unsigned int num) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!a.concat(num))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, unsigned int num) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(num)) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator +(const StringSumHelper &lhs, long num) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!a.concat(num))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, long num) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(num)) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator +(const StringSumHelper &lhs, unsigned long num) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!a.concat(num))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long num) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(num)) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator +(const StringSumHelper &lhs, float num) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!a.concat(num))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, float num) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(num)) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator +(const StringSumHelper &lhs, double num) {
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if(!a.concat(num))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, double num) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(num)) {
+    a.invalidate();
+  }
+  return a;
 }
 
-StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs)
-{
-    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
-    if (!a.concat(rhs))
-        a.invalidate();
-    return a;
+StringSumHelper &operator+(const StringSumHelper &lhs, long long num) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(num)) {
+    a.invalidate();
+  }
+  return a;
 }
 
-// /*********************************************/
-// /*  Comparison                               */
-// /*********************************************/
+StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long long num) {
+  StringSumHelper &a = const_cast<StringSumHelper &>(lhs);
+  if (!a.concat(num)) {
+    a.invalidate();
+  }
+  return a;
+}
+
+/*********************************************/
+/*  Comparison                               */
+/*********************************************/
 
 int String::compareTo(const String &s) const {
-    if(!buffer() || !s.buffer()) {
-        if(s.buffer() && s.len() > 0)
-            return 0 - *(unsigned char *) s.buffer();
-        if(buffer() && len() > 0)
-            return *(unsigned char *) buffer();
-        return 0;
+  if (!buffer() || !s.buffer()) {
+    if (s.buffer() && s.len() > 0) {
+      return 0 - *(unsigned char *)s.buffer();
+    }
+    if (buffer() && len() > 0) {
+      return *(unsigned char *)buffer();
     }
-    return strcmp(buffer(), s.buffer());
+    return 0;
+  }
+  return strcmp(buffer(), s.buffer());
 }
 
-unsigned char String::equals(const String &s2) const {
-    return (len() == s2.len() && compareTo(s2) == 0);
+bool String::equals(const String &s2) const {
+  return (len() == s2.len() && compareTo(s2) == 0);
 }
 
-unsigned char String::equals(const char *cstr) const {
-    if(len() == 0)
-        return (cstr == NULL || *cstr == 0);
-    if(cstr == NULL)
-        return buffer()[0] == 0;
-    return strcmp(buffer(), cstr) == 0;
+bool String::equals(const char *cstr) const {
+  if (len() == 0) {
+    return (cstr == NULL || *cstr == 0);
+  }
+  if (cstr == NULL) {
+    return buffer()[0] == 0;
+  }
+  return strcmp(buffer(), cstr) == 0;
 }
 
-unsigned char String::operator<(const String &rhs) const {
-    return compareTo(rhs) < 0;
+bool String::operator<(const String &rhs) const {
+  return compareTo(rhs) < 0;
 }
 
-unsigned char String::operator>(const String &rhs) const {
-    return compareTo(rhs) > 0;
+bool String::operator>(const String &rhs) const {
+  return compareTo(rhs) > 0;
 }
 
-unsigned char String::operator<=(const String &rhs) const {
-    return compareTo(rhs) <= 0;
+bool String::operator<=(const String &rhs) const {
+  return compareTo(rhs) <= 0;
 }
 
-unsigned char String::operator>=(const String &rhs) const {
-    return compareTo(rhs) >= 0;
+bool String::operator>=(const String &rhs) const {
+  return compareTo(rhs) >= 0;
 }
 
-unsigned char String::equalsIgnoreCase(const String &s2) const {
-    if(this == &s2)
-        return 1;
-    if(len() != s2.len())
-        return 0;
-    if(len() == 0)
-        return 1;
-    const char *p1 = buffer();
-    const char *p2 = s2.buffer();
-    while(*p1) {
-        if(tolower(*p1++) != tolower(*p2++))
-            return 0;
+bool String::equalsIgnoreCase(const String &s2) const {
+  if (this == &s2) {
+    return true;
+  }
+  if (len() != s2.len()) {
+    return false;
+  }
+  if (len() == 0) {
+    return true;
+  }
+  const char *p1 = buffer();
+  const char *p2 = s2.buffer();
+  while (*p1) {
+    if (tolower(*p1++) != tolower(*p2++)) {
+      return false;
     }
-    return 1;
+  }
+  return true;
 }
 
 unsigned char String::equalsConstantTime(const String &s2) const {
-    // To avoid possible time-based attacks present function
-    // compares given strings in a constant time.
-    if(len() != s2.len())
-        return 0;
-    //at this point lengths are the same
-    if(len() == 0)
-        return 1;
-    //at this point lenghts are the same and non-zero
-    const char *p1 = buffer();
-    const char *p2 = s2.buffer();
-    unsigned int equalchars = 0;
-    unsigned int diffchars = 0;
-    while(*p1) {
-        if(*p1 == *p2)
-            ++equalchars;
-        else
-            ++diffchars;
-        ++p1;
-        ++p2;
+  // To avoid possible time-based attacks present function
+  // compares given strings in a constant time.
+  if (len() != s2.len()) {
+    return 0;
+  }
+  //at this point lengths are the same
+  if (len() == 0) {
+    return 1;
+  }
+  //at this point lengths are the same and non-zero
+  const char *p1 = buffer();
+  const char *p2 = s2.buffer();
+  unsigned int equalchars = 0;
+  unsigned int diffchars = 0;
+  while (*p1) {
+    if (*p1 == *p2) {
+      ++equalchars;
+    } else {
+      ++diffchars;
     }
-    //the following should force a constant time eval of the condition without a compiler "logical shortcut"
-    unsigned char equalcond = (equalchars == len());
-    unsigned char diffcond = (diffchars == 0);
-    return (equalcond & diffcond); //bitwise AND
+    ++p1;
+    ++p2;
+  }
+  //the following should force a constant time eval of the condition without a compiler "logical shortcut"
+  unsigned char equalcond = (equalchars == len());
+  unsigned char diffcond = (diffchars == 0);
+  return (equalcond & diffcond);  //bitwise AND
 }
 
-unsigned char String::startsWith(const String &s2) const {
-    if(len() < s2.len())
-        return 0;
-    return startsWith(s2, 0);
+bool String::startsWith(const String &s2) const {
+  if (len() < s2.len()) {
+    return false;
+  }
+  return startsWith(s2, 0);
 }
 
-unsigned char String::startsWith(const String &s2, unsigned int offset) const {
-    if(offset > (unsigned)(len() - s2.len()) || !buffer() || !s2.buffer())
-        return 0;
-    return strncmp(&buffer()[offset], s2.buffer(), s2.len()) == 0;
+bool String::startsWith(const String &s2, unsigned int offset) const {
+  if (offset > (unsigned)(len() - s2.len()) || !buffer() || !s2.buffer()) {
+    return false;
+  }
+  return strncmp(&buffer()[offset], s2.buffer(), s2.len()) == 0;
 }
 
-unsigned char String::endsWith(const String &s2) const {
-    if(len() < s2.len() || !buffer() || !s2.buffer())
-        return 0;
-    return strcmp(&buffer()[len() - s2.len()], s2.buffer()) == 0;
+bool String::endsWith(const String &s2) const {
+  if (len() < s2.len() || !buffer() || !s2.buffer()) {
+    return false;
+  }
+  return strcmp(&buffer()[len() - s2.len()], s2.buffer()) == 0;
 }
 
-// /*********************************************/
-// /*  Character Access                         */
-// /*********************************************/
+/*********************************************/
+/*  Character Access                         */
+/*********************************************/
 
 char String::charAt(unsigned int loc) const {
-    return operator[](loc);
+  return operator[](loc);
 }
 
 void String::setCharAt(unsigned int loc, char c) {
-    if(loc < len())
-        wbuffer()[loc] = c;
+  if (loc < len()) {
+    wbuffer()[loc] = c;
+  }
 }
 
-char & String::operator[](unsigned int index) {
-    static char dummy_writable_char;
-    if(index >= len() || !buffer()) {
-        dummy_writable_char = 0;
-        return dummy_writable_char;
-    }
-    return wbuffer()[index];
+char &String::operator[](unsigned int index) {
+  static char dummy_writable_char;
+  if (index >= len() || !buffer()) {
+    dummy_writable_char = 0;
+    return dummy_writable_char;
+  }
+  return wbuffer()[index];
 }
 
 char String::operator[](unsigned int index) const {
-    if(index >= len() || !buffer())
-        return 0;
-    return buffer()[index];
+  if (index >= len() || !buffer()) {
+    return 0;
+  }
+  return buffer()[index];
 }
 
 void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const {
-    if(!bufsize || !buf)
-        return;
-    if(index >= len()) {
-        buf[0] = 0;
-        return;
-    }
-    unsigned int n = bufsize - 1;
-    if(n > len() - index)
-        n = len() - index;
-    strncpy((char *) buf, buffer() + index, n);
-    buf[n] = 0;
+  if (!bufsize || !buf) {
+    return;
+  }
+  if (index >= len()) {
+    buf[0] = 0;
+    return;
+  }
+  unsigned int n = bufsize - 1;
+  if (n > len() - index) {
+    n = len() - index;
+  }
+  strncpy((char *)buf, buffer() + index, n);
+  buf[n] = 0;
 }
 
-// /*********************************************/
-// /*  Search                                   */
-// /*********************************************/
+/*********************************************/
+/*  Search                                   */
+/*********************************************/
 
 int String::indexOf(char c) const {
-    return indexOf(c, 0);
+  return indexOf(c, 0);
 }
 
 int String::indexOf(char ch, unsigned int fromIndex) const {
-    if(fromIndex >= len())
-        return -1;
-    const char* temp = strchr(buffer() + fromIndex, ch);
-    if(temp == NULL)
-        return -1;
-    return temp - buffer();
+  if (fromIndex >= len()) {
+    return -1;
+  }
+  const char *temp = strchr(buffer() + fromIndex, ch);
+  if (temp == NULL) {
+    return -1;
+  }
+  return temp - buffer();
 }
 
 int String::indexOf(const String &s2) const {
-    return indexOf(s2, 0);
+  return indexOf(s2, 0);
 }
 
 int String::indexOf(const String &s2, unsigned int fromIndex) const {
-    if(fromIndex >= len())
-        return -1;
-    const char *found = strstr(buffer() + fromIndex, s2.buffer());
-    if(found == NULL)
-        return -1;
-    return found - buffer();
+  if (fromIndex >= len()) {
+    return -1;
+  }
+  const char *found = strstr(buffer() + fromIndex, s2.buffer());
+  if (found == NULL) {
+    return -1;
+  }
+  return found - buffer();
 }
 
 int String::lastIndexOf(char theChar) const {
-    return lastIndexOf(theChar, len() - 1);
+  return lastIndexOf(theChar, len() - 1);
 }
 
 int String::lastIndexOf(char ch, unsigned int fromIndex) const {
-    if(fromIndex >= len())
-        return -1;
-    char tempchar = buffer()[fromIndex + 1];
-    wbuffer()[fromIndex + 1] = '\0';
-    char* temp = strrchr(wbuffer(), ch);
-    wbuffer()[fromIndex + 1] = tempchar;
-    if(temp == NULL)
-        return -1;
-    return temp - buffer();
+  if (fromIndex >= len()) {
+    return -1;
+  }
+  char tempchar = buffer()[fromIndex + 1];
+  wbuffer()[fromIndex + 1] = '\0';
+  char *temp = strrchr(wbuffer(), ch);
+  wbuffer()[fromIndex + 1] = tempchar;
+  if (temp == NULL) {
+    return -1;
+  }
+  const int rv = temp - buffer();
+  if (rv >= len()) {
+    return -1;
+  }
+  return rv;
 }
 
 int String::lastIndexOf(const String &s2) const {
-    return lastIndexOf(s2, len() - s2.len());
+  return lastIndexOf(s2, len() - s2.len());
 }
 
 int String::lastIndexOf(const String &s2, unsigned int fromIndex) const {
-    if(s2.len() == 0 || len() == 0 || s2.len() > len())
-        return -1;
-    if(fromIndex >= len())
-        fromIndex = len() - 1;
-    int found = -1;
-    for(char *p = wbuffer(); p <= wbuffer() + fromIndex; p++) {
-        p = strstr(p, s2.buffer());
-        if(!p)
-            break;
-        if((unsigned int) (p - wbuffer()) <= fromIndex)
-            found = p - buffer();
+  if (s2.len() == 0 || len() == 0 || s2.len() > len()) {
+    return -1;
+  }
+  if (fromIndex >= len()) {
+    fromIndex = len() - 1;
+  }
+  int found = -1;
+  for (char *p = wbuffer(); p <= wbuffer() + fromIndex; p++) {
+    p = strstr(p, s2.buffer());
+    if (!p) {
+      break;
     }
-    return found;
+    if ((unsigned int)(p - wbuffer()) <= fromIndex) {
+      found = p - buffer();
+    }
+  }
+  return found;
 }
 
 String String::substring(unsigned int left, unsigned int right) const {
-    if(left > right) {
-        unsigned int temp = right;
-        right = left;
-        left = temp;
-    }
-    String out;
-    if(left >= len())
-        return out;
-    if(right > len())
-        right = len();
-    char temp = buffer()[right];  // save the replaced character
-    wbuffer()[right] = '\0';
-    out = wbuffer() + left;  // pointer arithmetic
-    wbuffer()[right] = temp;  //restore character
+  if (left > right) {
+    unsigned int temp = right;
+    right = left;
+    left = temp;
+  }
+  String out;
+  if (left >= len()) {
     return out;
+  }
+  if (right > len()) {
+    right = len();
+  }
+  out.copy(buffer() + left, right - left);
+  return out;
 }
 
-// /*********************************************/
-// /*  Modification                             */
-// /*********************************************/
+/*********************************************/
+/*  Modification                             */
+/*********************************************/
 
 void String::replace(char find, char replace) {
-    if(!buffer())
-        return;
-    for(char *p = wbuffer(); *p; p++) {
-        if(*p == find)
-            *p = replace;
+  if (!buffer()) {
+    return;
+  }
+  for (char *p = wbuffer(); *p; p++) {
+    if (*p == find) {
+      *p = replace;
     }
-}
-
-void String::replace(const String& find, const String& replace) {
-    if(len() == 0 || find.len() == 0)
-        return;
-    int diff = replace.len() - find.len();
-    char *readFrom = wbuffer();
-    char *foundAt;
-    if(diff == 0) {
-        while((foundAt = strstr(readFrom, find.buffer())) != NULL) {
-            memmove(foundAt, replace.buffer(), replace.len());
-            readFrom = foundAt + replace.len();
-        }
-    } else if(diff < 0) {
-        char *writeTo = wbuffer();
-        while((foundAt = strstr(readFrom, find.buffer())) != NULL) {
-            unsigned int n = foundAt - readFrom;
-            memmove(writeTo, readFrom, n);
-            writeTo += n;
-            memmove(writeTo, replace.buffer(), replace.len());
-            writeTo += replace.len();
-            readFrom = foundAt + find.len();
-            setLen(len() + diff);
-        }
-        memmove(writeTo, readFrom, strlen(readFrom)+1);
-    } else {
-        unsigned int size = len(); // compute size needed for result
-        while((foundAt = strstr(readFrom, find.buffer())) != NULL) {
-            readFrom = foundAt + find.len();
-            size += diff;
-        }
-        if(size == len())
-            return;
-        if(size > capacity() && !changeBuffer(size))
-            return; // XXX: tell user!
-        int index = len() - 1;
-        while(index >= 0 && (index = lastIndexOf(find, index)) >= 0) {
-            readFrom = wbuffer() + index + find.len();
-            memmove(readFrom + diff, readFrom, len() - (readFrom - buffer()));
-	    int newLen = len() + diff;
-            memmove(wbuffer() + index, replace.buffer(), replace.len());
-            setLen(newLen);
-            wbuffer()[newLen] = 0;
-            index--;
-        }
+  }
+}
+
+void String::replace(const String &find, const String &replace) {
+  if (len() == 0 || find.len() == 0) {
+    return;
+  }
+  int diff = replace.len() - find.len();
+  char *readFrom = wbuffer();
+  char *foundAt;
+  if (diff == 0) {
+    while ((foundAt = strstr(readFrom, find.buffer())) != NULL) {
+      memmove(foundAt, replace.buffer(), replace.len());
+      readFrom = foundAt + replace.len();
+    }
+  } else if (diff < 0) {
+    char *writeTo = wbuffer();
+    unsigned int l = len();
+    while ((foundAt = strstr(readFrom, find.buffer())) != NULL) {
+      unsigned int n = foundAt - readFrom;
+      memmove(writeTo, readFrom, n);
+      writeTo += n;
+      memmove(writeTo, replace.buffer(), replace.len());
+      writeTo += replace.len();
+      readFrom = foundAt + find.len();
+      l += diff;
+    }
+    memmove(writeTo, readFrom, strlen(readFrom) + 1);
+    setLen(l);
+  } else {
+    unsigned int size = len();  // compute size needed for result
+    while ((foundAt = strstr(readFrom, find.buffer())) != NULL) {
+      readFrom = foundAt + find.len();
+      size += diff;
+    }
+    if (size == len()) {
+      return;
+    }
+    if (size > capacity() && !changeBuffer(size)) {
+      log_w("String.Replace() Insufficient space to replace string");
+      return;
+    }
+    int index = len() - 1;
+    while (index >= 0 && (index = lastIndexOf(find, index)) >= 0) {
+      readFrom = wbuffer() + index + find.len();
+      memmove(readFrom + diff, readFrom, len() - (readFrom - buffer()));
+      int newLen = len() + diff;
+      memmove(wbuffer() + index, replace.buffer(), replace.len());
+      setLen(newLen);
+      wbuffer()[newLen] = 0;
+      index--;
     }
+  }
 }
 
 void String::remove(unsigned int index) {
-    // Pass the biggest integer as the count. The remove method
-    // below will take care of truncating it at the end of the
-    // string.
-    remove(index, (unsigned int) -1);
+  // Pass the biggest integer as the count. The remove method
+  // below will take care of truncating it at the end of the
+  // string.
+  remove(index, (unsigned int)-1);
 }
 
 void String::remove(unsigned int index, unsigned int count) {
-    if(index >= len()) {
-        return;
-    }
-    if(count <= 0) {
-        return;
-    }
-    if(count > len() - index) {
-        count = len() - index;
-    }
-    char *writeTo = wbuffer() + index;
-    unsigned int newlen = len() - count;
-    setLen(newlen);
-    memmove(writeTo, wbuffer() + index + count, newlen - index);
-    wbuffer()[newlen] = 0;
+  if (index >= len()) {
+    return;
+  }
+  if (count <= 0) {
+    return;
+  }
+  if (count > len() - index) {
+    count = len() - index;
+  }
+  char *writeTo = wbuffer() + index;
+  unsigned int newlen = len() - count;
+  memmove(writeTo, wbuffer() + index + count, newlen - index);
+  setLen(newlen);
+  wbuffer()[newlen] = 0;
 }
 
 void String::toLowerCase(void) {
-    if(!buffer())
-        return;
-    for(char *p = wbuffer(); *p; p++) {
-        *p = tolower(*p);
-    }
+  if (!buffer()) {
+    return;
+  }
+  for (char *p = wbuffer(); *p; p++) {
+    *p = tolower(*p);
+  }
 }
 
 void String::toUpperCase(void) {
-    if(!buffer())
-        return;
-    for(char *p = wbuffer(); *p; p++) {
-        *p = toupper(*p);
-    }
+  if (!buffer()) {
+    return;
+  }
+  for (char *p = wbuffer(); *p; p++) {
+    *p = toupper(*p);
+  }
 }
 
 void String::trim(void) {
-    if(!buffer() || len() == 0)
-        return;
-    char *begin = wbuffer();
-    while(isspace(*begin))
-        begin++;
-    char *end = wbuffer() + len() - 1;
-    while(isspace(*end) && end >= begin)
-        end--;
-    unsigned int newlen = end + 1 - begin;
-    setLen(newlen);
-    if(begin > buffer())
-        memmove(wbuffer(), begin, newlen);
-    wbuffer()[newlen] = 0;
+  if (!buffer() || len() == 0) {
+    return;
+  }
+  char *begin = wbuffer();
+  while (isspace(*begin)) {
+    begin++;
+  }
+  char *end = wbuffer() + len() - 1;
+  while (isspace(*end) && end >= begin) {
+    end--;
+  }
+  unsigned int newlen = end + 1 - begin;
+  if (begin > buffer()) {
+    memmove(wbuffer(), begin, newlen);
+  }
+  setLen(newlen);
+  wbuffer()[newlen] = 0;
 }
 
-// /*********************************************/
-// /*  Parsing / Conversion                     */
-// /*********************************************/
+/*********************************************/
+/*  Parsing / Conversion                     */
+/*********************************************/
 
 long String::toInt(void) const {
-    if (buffer())
-        return atol(buffer());
-    return 0;
+  if (buffer()) {
+    return atol(buffer());
+  }
+  return 0;
 }
 
 float String::toFloat(void) const {
-    if (buffer())
-        return atof(buffer());
-    return 0;
+  if (buffer()) {
+    return atof(buffer());
+  }
+  return 0;
 }
 
-double String::toDouble(void) const
-{
-    if (buffer())
-        return atof(buffer());
-    return 0.0;
+double String::toDouble(void) const {
+  if (buffer()) {
+    return atof(buffer());
+  }
+  return 0.0;
 }
 
 // global empty string to allow returning const String& with nothing
diff --git a/cores/esp32/WString.h b/cores/esp32/WString.h
index 9111d9aac11..a8327f40de0 100644
--- a/cores/esp32/WString.h
+++ b/cores/esp32/WString.h
@@ -23,339 +23,399 @@
 #define String_class_h
 #ifdef __cplusplus
 
+#include <pgmspace.h>
+
 #include <stdlib.h>
+#include <stdint.h>
 #include <string.h>
 #include <ctype.h>
-#include <pgmspace.h>
-#include <stdint.h>
+
+// A pure abstract class forward used as a means to proide a unique pointer type
+// but really is never defined.
+class __FlashStringHelper;
+#define FPSTR(str_pointer) (reinterpret_cast<const __FlashStringHelper *>(str_pointer))
+#define F(string_literal)  (FPSTR(PSTR(string_literal)))
 
 // An inherited class for holding the result of a concatenation.  These
 // result objects are assumed to be writable by subsequent concatenations.
 class StringSumHelper;
 
-// an abstract class used as a means to proide a unique pointer type
-// but really has no body
-class __FlashStringHelper;
-#define FPSTR(pstr_pointer) (reinterpret_cast<const __FlashStringHelper *>(pstr_pointer))
-#define F(string_literal) (FPSTR(PSTR(string_literal)))
-
 // The string class
 class String {
-        // use a function pointer to allow for "if (s)" without the
-        // complications of an operator bool(). for more information, see:
-        // http://www.artima.com/cppsource/safebool.html
-        typedef void (String::*StringIfHelperType)() const;
-        void StringIfHelper() const {
-        }
+  // use a function pointer to allow for "if (s)" without the
+  // complications of an operator bool(). for more information, see:
+  // http://www.artima.com/cppsource/safebool.html
+  typedef void (String::*StringIfHelperType)() const;
+  void StringIfHelper() const {}
 
-    public:
-        // constructors
-        // creates a copy of the initial value.
-        // if the initial value is null or invalid, or if memory allocation
-        // fails, the string will be marked as invalid (i.e. "if (s)" will
-        // be false).
-        String(const char *cstr = "");
-        String(const String &str);
-        String(const __FlashStringHelper *str);
+public:
+  // constructors
+  // creates a copy of the initial value.
+  // if the initial value is null or invalid, or if memory allocation
+  // fails, the string will be marked as invalid (i.e. "if (s)" will
+  // be false).
+  String(const char *cstr = "");
+  String(const char *cstr, unsigned int length);
+#ifdef __GXX_EXPERIMENTAL_CXX0X__
+  String(const uint8_t *cstr, unsigned int length) : String(reinterpret_cast<const char *>(cstr), length) {}
+#endif
+  String(const String &str);
+  String(const __FlashStringHelper *str) : String(reinterpret_cast<const char *>(str)) {}
 #ifdef __GXX_EXPERIMENTAL_CXX0X__
-        String(String &&rval);
-        String(StringSumHelper &&rval);
+  String(String &&rval);
+  String(StringSumHelper &&rval);
 #endif
-        explicit String(char c);
-        explicit String(unsigned char, unsigned char base = 10);
-        explicit String(int, unsigned char base = 10);
-        explicit String(unsigned int, unsigned char base = 10);
-        explicit String(long, unsigned char base = 10);
-        explicit String(unsigned long, unsigned char base = 10);
-        explicit String(float, unsigned char decimalPlaces = 2);
-        explicit String(double, unsigned char decimalPlaces = 2);
-        ~String(void);
+  explicit String(char c);
+  explicit String(unsigned char, unsigned char base = 10);
+  explicit String(int, unsigned char base = 10);
+  explicit String(unsigned int, unsigned char base = 10);
+  explicit String(long, unsigned char base = 10);
+  explicit String(unsigned long, unsigned char base = 10);
+  explicit String(float, unsigned int decimalPlaces = 2);
+  explicit String(double, unsigned int decimalPlaces = 2);
+  explicit String(long long, unsigned char base = 10);
+  explicit String(unsigned long long, unsigned char base = 10);
+  ~String(void);
 
-        // memory management
-        // return true on success, false on failure (in which case, the string
-        // is left unchanged).  reserve(0), if successful, will validate an
-        // invalid string (i.e., "if (s)" will be true afterwards)
-        unsigned char reserve(unsigned int size);
-        inline unsigned int length(void) const {
-            if(buffer()) {
-                return len();
-            } else {
-                return 0;
-            }
-        }
-        inline void clear(void) {
-            setLen(0);
-        }
-        inline bool isEmpty(void) const {
-            return length() == 0;
-        }
+  // memory management
+  // return true on success, false on failure (in which case, the string
+  // is left unchanged).  reserve(0), if successful, will validate an
+  // invalid string (i.e., "if (s)" will be true afterwards)
+  bool reserve(unsigned int size);
+  inline unsigned int length(void) const {
+    if (buffer()) {
+      return len();
+    } else {
+      return 0;
+    }
+  }
+  inline void clear(void) {
+    setLen(0);
+  }
+  inline bool isEmpty(void) const {
+    return length() == 0;
+  }
 
-        // creates a copy of the assigned value.  if the value is null or
-        // invalid, or if the memory allocation fails, the string will be
-        // marked as invalid ("if (s)" will be false).
-        String & operator =(const String &rhs);
-        String & operator =(const char *cstr);
-        String & operator = (const __FlashStringHelper *str);
+  // creates a copy of the assigned value.  if the value is null or
+  // invalid, or if the memory allocation fails, the string will be
+  // marked as invalid ("if (s)" will be false).
+  String &operator=(const String &rhs);
+  String &operator=(const char *cstr);
+  String &operator=(const __FlashStringHelper *str) {
+    return *this = reinterpret_cast<const char *>(str);
+  }
 #ifdef __GXX_EXPERIMENTAL_CXX0X__
-        String & operator =(String &&rval);
-        String & operator =(StringSumHelper &&rval);
+  String &operator=(String &&rval);
+  String &operator=(StringSumHelper &&rval);
 #endif
 
-        // concatenate (works w/ built-in types)
+  // concatenate (works w/ built-in types, same as assignment)
 
-        // returns true on success, false on failure (in which case, the string
-        // is left unchanged).  if the argument is null or invalid, the
-        // concatenation is considered unsuccessful.
-        unsigned char concat(const String &str);
-        unsigned char concat(const char *cstr);
-        unsigned char concat(char c);
-        unsigned char concat(unsigned char c);
-        unsigned char concat(int num);
-        unsigned char concat(unsigned int num);
-        unsigned char concat(long num);
-        unsigned char concat(unsigned long num);
-        unsigned char concat(float num);
-        unsigned char concat(double num);
-        unsigned char concat(const __FlashStringHelper * str);
+  // returns true on success, false on failure (in which case, the string
+  // is left unchanged).  if the argument is null or invalid, the
+  // concatenation is considered unsuccessful.
+  bool concat(const String &str);
+  bool concat(const char *cstr);
+  bool concat(const char *cstr, unsigned int length);
+  bool concat(const uint8_t *cstr, unsigned int length) {
+    return concat(reinterpret_cast<const char *>(cstr), length);
+  }
+  bool concat(char c);
+  bool concat(unsigned char c);
+  bool concat(int num);
+  bool concat(unsigned int num);
+  bool concat(long num);
+  bool concat(unsigned long num);
+  bool concat(float num);
+  bool concat(double num);
+  bool concat(long long num);
+  bool concat(unsigned long long num);
+  bool concat(const __FlashStringHelper *str) {
+    return concat(reinterpret_cast<const char *>(str));
+  }
 
-        // if there's not enough memory for the concatenated value, the string
-        // will be left unchanged (but this isn't signalled in any way)
-        String & operator +=(const String &rhs) {
-            concat(rhs);
-            return (*this);
-        }
-        String & operator +=(const char *cstr) {
-            concat(cstr);
-            return (*this);
-        }
-        String & operator +=(char c) {
-            concat(c);
-            return (*this);
-        }
-        String & operator +=(unsigned char num) {
-            concat(num);
-            return (*this);
-        }
-        String & operator +=(int num) {
-            concat(num);
-            return (*this);
-        }
-        String & operator +=(unsigned int num) {
-            concat(num);
-            return (*this);
-        }
-        String & operator +=(long num) {
-            concat(num);
-            return (*this);
-        }
-        String & operator +=(unsigned long num) {
-            concat(num);
-            return (*this);
-        }
-        String & operator +=(float num) {
-            concat(num);
-            return (*this);
-        }
-        String & operator +=(double num) {
-            concat(num);
-            return (*this);
-        }
-        String & operator += (const __FlashStringHelper *str){
-            concat(str);
-            return (*this);
-        }
+  // if there's not enough memory for the concatenated value, the string
+  // will be left unchanged (but this isn't signaled in any way)
+  String &operator+=(const String &rhs) {
+    concat(rhs);
+    return (*this);
+  }
+  String &operator+=(const char *cstr) {
+    concat(cstr);
+    return (*this);
+  }
+  String &operator+=(char c) {
+    concat(c);
+    return (*this);
+  }
+  String &operator+=(unsigned char num) {
+    concat(num);
+    return (*this);
+  }
+  String &operator+=(int num) {
+    concat(num);
+    return (*this);
+  }
+  String &operator+=(unsigned int num) {
+    concat(num);
+    return (*this);
+  }
+  String &operator+=(long num) {
+    concat(num);
+    return (*this);
+  }
+  String &operator+=(unsigned long num) {
+    concat(num);
+    return (*this);
+  }
+  String &operator+=(float num) {
+    concat(num);
+    return (*this);
+  }
+  String &operator+=(double num) {
+    concat(num);
+    return (*this);
+  }
+  String &operator+=(long long num) {
+    concat(num);
+    return (*this);
+  }
+  String &operator+=(unsigned long long num) {
+    concat(num);
+    return (*this);
+  }
+  String &operator+=(const __FlashStringHelper *str) {
+    return *this += reinterpret_cast<const char *>(str);
+  }
 
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, const String &rhs);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, const char *cstr);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, char c);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned char num);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, int num);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned int num);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, long num);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned long num);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, float num);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, double num);
-        friend StringSumHelper & operator +(const StringSumHelper &lhs, const __FlashStringHelper *rhs);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, const String &rhs);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, const char *cstr);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, char c);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned char num);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, int num);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned int num);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, long num);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long num);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, float num);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, double num);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, long long num);
+  friend StringSumHelper &operator+(const StringSumHelper &lhs, unsigned long long num);
 
-        // comparison (only works w/ Strings and "strings")
-        operator StringIfHelperType() const {
-            return buffer() ? &String::StringIfHelper : 0;
-        }
-        int compareTo(const String &s) const;
-        unsigned char equals(const String &s) const;
-        unsigned char equals(const char *cstr) const;
-        unsigned char operator ==(const String &rhs) const {
-            return equals(rhs);
-        }
-        unsigned char operator ==(const char *cstr) const {
-            return equals(cstr);
-        }
-        unsigned char operator !=(const String &rhs) const {
-            return !equals(rhs);
-        }
-        unsigned char operator !=(const char *cstr) const {
-            return !equals(cstr);
-        }
-        unsigned char operator <(const String &rhs) const;
-        unsigned char operator >(const String &rhs) const;
-        unsigned char operator <=(const String &rhs) const;
-        unsigned char operator >=(const String &rhs) const;
-        unsigned char equalsIgnoreCase(const String &s) const;
-        unsigned char equalsConstantTime(const String &s) const;
-        unsigned char startsWith(const String &prefix) const;
-        unsigned char startsWith(const char *prefix) const {
-            return this->startsWith(String(prefix));
-        }
-        unsigned char startsWith(const __FlashStringHelper *prefix) const {
-            return this->startsWith(String(prefix));
-        }
-        unsigned char startsWith(const String &prefix, unsigned int offset) const;
-        unsigned char endsWith(const String &suffix) const;
-        unsigned char endsWith(const char *suffix) const {
-            return this->endsWith(String(suffix));
-        }
-        unsigned char endsWith(const __FlashStringHelper * suffix) const {
-            return this->endsWith(String(suffix));
-        }
+  // comparison (only works w/ Strings and "strings")
+  operator StringIfHelperType() const {
+    return buffer() ? &String::StringIfHelper : 0;
+  }
+  int compareTo(const String &s) const;
+  bool equals(const String &s) const;
+  bool equals(const char *cstr) const;
+  bool operator==(const String &rhs) const {
+    return equals(rhs);
+  }
+  bool operator==(const char *cstr) const {
+    return equals(cstr);
+  }
+  bool operator!=(const String &rhs) const {
+    return !equals(rhs);
+  }
+  bool operator!=(const char *cstr) const {
+    return !equals(cstr);
+  }
+  bool operator<(const String &rhs) const;
+  bool operator>(const String &rhs) const;
+  bool operator<=(const String &rhs) const;
+  bool operator>=(const String &rhs) const;
+  bool equalsIgnoreCase(const String &s) const;
+  unsigned char equalsConstantTime(const String &s) const;
+  bool startsWith(const String &prefix) const;
+  bool startsWith(const char *prefix) const {
+    return this->startsWith(String(prefix));
+  }
+  bool startsWith(const __FlashStringHelper *prefix) const {
+    return this->startsWith(reinterpret_cast<const char *>(prefix));
+  }
+  bool startsWith(const String &prefix, unsigned int offset) const;
+  bool endsWith(const String &suffix) const;
+  bool endsWith(const char *suffix) const {
+    return this->endsWith(String(suffix));
+  }
+  bool endsWith(const __FlashStringHelper *suffix) const {
+    return this->endsWith(reinterpret_cast<const char *>(suffix));
+  }
 
-        // character access
-        char charAt(unsigned int index) const;
-        void setCharAt(unsigned int index, char c);
-        char operator [](unsigned int index) const;
-        char& operator [](unsigned int index);
-        void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index = 0) const;
-        void toCharArray(char *buf, unsigned int bufsize, unsigned int index = 0) const {
-            getBytes((unsigned char *) buf, bufsize, index);
-        }
-        const char* c_str() const { return buffer(); }
-        char* begin() { return wbuffer(); }
-        char* end() { return wbuffer() + length(); }
-        const char* begin() const { return c_str(); }
-        const char* end() const { return c_str() + length(); }
+  // character access
+  char charAt(unsigned int index) const;
+  void setCharAt(unsigned int index, char c);
+  char operator[](unsigned int index) const;
+  char &operator[](unsigned int index);
+  void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index = 0) const;
+  void toCharArray(char *buf, unsigned int bufsize, unsigned int index = 0) const {
+    getBytes((unsigned char *)buf, bufsize, index);
+  }
+  const char *c_str() const {
+    return buffer();
+  }
+  char *begin() {
+    return wbuffer();
+  }
+  char *end() {
+    return wbuffer() + length();
+  }
+  const char *begin() const {
+    return c_str();
+  }
+  const char *end() const {
+    return c_str() + length();
+  }
 
-        // search
-        int indexOf(char ch) const;
-        int indexOf(char ch, unsigned int fromIndex) const;
-        int indexOf(const String &str) const;
-        int indexOf(const String &str, unsigned int fromIndex) const;
-        int lastIndexOf(char ch) const;
-        int lastIndexOf(char ch, unsigned int fromIndex) const;
-        int lastIndexOf(const String &str) const;
-        int lastIndexOf(const String &str, unsigned int fromIndex) const;
-        String substring(unsigned int beginIndex) const {
-            return substring(beginIndex, len());
-        }
-        ;
-        String substring(unsigned int beginIndex, unsigned int endIndex) const;
+  // search
+  int indexOf(char ch) const;
+  int indexOf(char ch, unsigned int fromIndex) const;
+  int indexOf(const String &str) const;
+  int indexOf(const String &str, unsigned int fromIndex) const;
+  int lastIndexOf(char ch) const;
+  int lastIndexOf(char ch, unsigned int fromIndex) const;
+  int lastIndexOf(const String &str) const;
+  int lastIndexOf(const String &str, unsigned int fromIndex) const;
+  String substring(unsigned int beginIndex) const {
+    return substring(beginIndex, len());
+  }
+  String substring(unsigned int beginIndex, unsigned int endIndex) const;
 
-        // modification
-        void replace(char find, char replace);
-        void replace(const String &find, const String &replace);
-        void replace(const char *find, const String &replace) {
-            this->replace(String(find), replace);
-        }
-        void replace(const __FlashStringHelper *find, const String &replace) {
-            this->replace(String(find), replace);
-        }
-        void replace(const char *find, const char *replace) {
-            this->replace(String(find), String(replace));
-        }
-        void replace(const __FlashStringHelper *find, const char *replace) {
-            this->replace(String(find), String(replace));
-        }
-        void replace(const __FlashStringHelper *find, const __FlashStringHelper *replace) {
-            this->replace(String(find), String(replace));
-        }
-        void remove(unsigned int index);
-        void remove(unsigned int index, unsigned int count);
-        void toLowerCase(void);
-        void toUpperCase(void);
-        void trim(void);
+  // modification
+  void replace(char find, char replace);
+  void replace(const String &find, const String &replace);
+  void replace(const char *find, const String &replace) {
+    this->replace(String(find), replace);
+  }
+  void replace(const __FlashStringHelper *find, const String &replace) {
+    this->replace(reinterpret_cast<const char *>(find), replace);
+  }
+  void replace(const char *find, const char *replace) {
+    this->replace(String(find), String(replace));
+  }
+  void replace(const __FlashStringHelper *find, const char *replace) {
+    this->replace(reinterpret_cast<const char *>(find), String(replace));
+  }
+  void replace(const __FlashStringHelper *find, const __FlashStringHelper *replace) {
+    this->replace(reinterpret_cast<const char *>(find), reinterpret_cast<const char *>(replace));
+  }
+  void remove(unsigned int index);
+  void remove(unsigned int index, unsigned int count);
+  void toLowerCase(void);
+  void toUpperCase(void);
+  void trim(void);
 
-        // parsing/conversion
-        long toInt(void) const;
-        float toFloat(void) const;
-	double toDouble(void) const;
+  // parsing/conversion
+  long toInt(void) const;
+  float toFloat(void) const;
+  double toDouble(void) const;
 
-    protected:
-        // Contains the string info when we're not in SSO mode
-        struct _ptr { 
-            char *   buff;
-            uint16_t cap;
-            uint16_t len;
-        };
-        // This allows strings up up to 11 (10 + \0 termination) without any extra space.
-        enum { SSOSIZE = sizeof(struct _ptr) + 4 - 1 }; // Characters to allocate space for SSO, must be 12 or more
-        struct _sso {
-            char     buff[SSOSIZE];
-            unsigned char len   : 7; // Ensure only one byte is allocated by GCC for the bitfields
-            unsigned char isSSO : 1;
-        } __attribute__((packed)); // Ensure that GCC doesn't expand the flag byte to a 32-bit word for alignment issues
-        enum { CAPACITY_MAX = 65535 }; // If typeof(cap) changed from uint16_t, be sure to update this enum to the max value storable in the type
-        union {
-            struct _ptr ptr;
-            struct _sso sso;
-        };
-        // Accessor functions
-        inline bool isSSO() const { return sso.isSSO; }
-        inline unsigned int len() const { return isSSO() ? sso.len : ptr.len; }
-        inline unsigned int capacity() const { return isSSO() ? (unsigned int)SSOSIZE - 1 : ptr.cap; } // Size of max string not including terminal NUL
-        inline void setSSO(bool set) { sso.isSSO = set; }
-        inline void setLen(int len) { if (isSSO()) sso.len = len; else ptr.len = len; }
-        inline void setCapacity(int cap) { if (!isSSO()) ptr.cap = cap; }
-	inline void setBuffer(char *buff) { if (!isSSO()) ptr.buff = buff; }
-        // Buffer accessor functions
-        inline const char *buffer() const { return (const char *)(isSSO() ? sso.buff : ptr.buff); }
-        inline char *wbuffer() const { return isSSO() ? const_cast<char *>(sso.buff) : ptr.buff; } // Writable version of buffer
+protected:
+  // Contains the string info when we're not in SSO mode
+  struct _ptr {
+    char *buff;
+    uint32_t cap;
+    uint32_t len;
+  };
+  // This allows strings up up to 11 (10 + \0 termination) without any extra space.
+  enum {
+    SSOSIZE = sizeof(struct _ptr) + 4 - 1
+  };  // Characters to allocate space for SSO, must be 12 or more
+  struct _sso {
+    char buff[SSOSIZE];
+    unsigned char len   : 7;  // Ensure only one byte is allocated by GCC for the bitfields
+    unsigned char isSSO : 1;
+  } __attribute__((packed));  // Ensure that GCC doesn't expand the flag byte to a 32-bit word for alignment issues
+#ifdef BOARD_HAS_PSRAM
+  enum {
+    CAPACITY_MAX = 3145728
+  };
+#else
+  enum {
+    CAPACITY_MAX = 65535
+  };
+#endif
+  union {
+    struct _ptr ptr;
+    struct _sso sso;
+  };
+  // Accessor functions
+  inline bool isSSO() const {
+    return sso.isSSO;
+  }
+  inline unsigned int len() const {
+    return isSSO() ? sso.len : ptr.len;
+  }
+  inline unsigned int capacity() const {
+    return isSSO() ? (unsigned int)SSOSIZE - 1 : ptr.cap;
+  }  // Size of max string not including terminal NUL
+  inline void setSSO(bool set) {
+    sso.isSSO = set;
+  }
+  inline void setLen(int len) {
+    if (isSSO()) {
+      sso.len = len;
+      sso.buff[len] = 0;
+    } else {
+      ptr.len = len;
+      if (ptr.buff) {
+        ptr.buff[len] = 0;
+      }
+    }
+  }
+  inline void setCapacity(int cap) {
+    if (!isSSO()) {
+      ptr.cap = cap;
+    }
+  }
+  inline void setBuffer(char *buff) {
+    if (!isSSO()) {
+      ptr.buff = buff;
+    }
+  }
+  // Buffer accessor functions
+  inline const char *buffer() const {
+    return reinterpret_cast<const char *>(isSSO() ? sso.buff : ptr.buff);
+  }
+  inline char *wbuffer() const {
+    return isSSO() ? const_cast<char *>(sso.buff) : ptr.buff;
+  }  // Writable version of buffer
 
-    protected:
-        void init(void);
-        void invalidate(void);
-        unsigned char changeBuffer(unsigned int maxStrLen);
-        unsigned char concat(const char *cstr, unsigned int length);
+protected:
+  void init(void);
+  void invalidate(void);
+  bool changeBuffer(unsigned int maxStrLen);
 
-        // copy and move
-        String & copy(const char *cstr, unsigned int length);
-        String & copy(const __FlashStringHelper *pstr, unsigned int length);
+  // copy and move
+  String &copy(const char *cstr, unsigned int length);
+  String &copy(const __FlashStringHelper *pstr, unsigned int length) {
+    return copy(reinterpret_cast<const char *>(pstr), length);
+  }
 #ifdef __GXX_EXPERIMENTAL_CXX0X__
-        void move(String &rhs);
+  void move(String &rhs);
 #endif
 };
 
-class StringSumHelper: public String {
-    public:
-        StringSumHelper(const String &s) :
-                String(s) {
-        }
-        StringSumHelper(const char *p) :
-                String(p) {
-        }
-        StringSumHelper(char c) :
-                String(c) {
-        }
-        StringSumHelper(unsigned char num) :
-                String(num) {
-        }
-        StringSumHelper(int num) :
-                String(num) {
-        }
-        StringSumHelper(unsigned int num) :
-                String(num) {
-        }
-        StringSumHelper(long num) :
-                String(num) {
-        }
-        StringSumHelper(unsigned long num) :
-                String(num) {
-        }
-        StringSumHelper(float num) :
-                String(num) {
-        }
-        StringSumHelper(double num) :
-                String(num) {
-        }
+class StringSumHelper : public String {
+public:
+  StringSumHelper(const String &s) : String(s) {}
+  StringSumHelper(const char *p) : String(p) {}
+  StringSumHelper(char c) : String(c) {}
+  StringSumHelper(unsigned char num) : String(num) {}
+  StringSumHelper(int num) : String(num) {}
+  StringSumHelper(unsigned int num) : String(num) {}
+  StringSumHelper(long num) : String(num) {}
+  StringSumHelper(unsigned long num) : String(num) {}
+  StringSumHelper(float num) : String(num) {}
+  StringSumHelper(double num) : String(num) {}
+  StringSumHelper(long long num) : String(num) {}
+  StringSumHelper(unsigned long long num) : String(num) {}
 };
 
+inline StringSumHelper &operator+(const StringSumHelper &lhs, const __FlashStringHelper *rhs) {
+  return lhs + reinterpret_cast<const char *>(rhs);
+}
+
 extern const String emptyString;
 
 #endif  // __cplusplus
diff --git a/cores/esp32/base64.cpp b/cores/esp32/base64.cpp
index 1fc144e2659..8fa9617668c 100644
--- a/cores/esp32/base64.cpp
+++ b/cores/esp32/base64.cpp
@@ -35,21 +35,20 @@ extern "C" {
  * @param length size_t
  * @return String
  */
-String base64::encode(const uint8_t * data, size_t length)
-{
-    size_t size = base64_encode_expected_len(length) + 1;
-    char * buffer = (char *) malloc(size);
-    if(buffer) {
-        base64_encodestate _state;
-        base64_init_encodestate(&_state);
-        int len = base64_encode_block((const char *) &data[0], length, &buffer[0], &_state);
-        len = base64_encode_blockend((buffer + len), &_state);
+String base64::encode(const uint8_t *data, size_t length) {
+  size_t size = base64_encode_expected_len(length) + 1;
+  char *buffer = (char *)malloc(size);
+  if (buffer) {
+    base64_encodestate _state;
+    base64_init_encodestate(&_state);
+    int len = base64_encode_block((const char *)&data[0], length, &buffer[0], &_state);
+    len = base64_encode_blockend((buffer + len), &_state);
 
-        String base64 = String(buffer);
-        free(buffer);
-        return base64;
-    }
-    return String("-FAIL-");
+    String base64 = String(buffer);
+    free(buffer);
+    return base64;
+  }
+  return String("-FAIL-");
 }
 
 /**
@@ -57,8 +56,6 @@ String base64::encode(const uint8_t * data, size_t length)
  * @param text const String&
  * @return String
  */
-String base64::encode(const String& text)
-{
-    return base64::encode((uint8_t *) text.c_str(), text.length());
+String base64::encode(const String &text) {
+  return base64::encode((uint8_t *)text.c_str(), text.length());
 }
-
diff --git a/cores/esp32/base64.h b/cores/esp32/base64.h
index 97095817b8f..63a0e21535c 100644
--- a/cores/esp32/base64.h
+++ b/cores/esp32/base64.h
@@ -1,13 +1,12 @@
 #ifndef CORE_BASE64_H_
 #define CORE_BASE64_H_
 
-class base64
-{
+class base64 {
 public:
-    static String encode(const uint8_t * data, size_t length);
-    static String encode(const String& text);
+  static String encode(const uint8_t *data, size_t length);
+  static String encode(const String &text);
+
 private:
 };
 
-
 #endif /* CORE_BASE64_H_ */
diff --git a/cores/esp32/binary.h b/cores/esp32/binary.h
index c2f189dad18..4a8e4e70819 100644
--- a/cores/esp32/binary.h
+++ b/cores/esp32/binary.h
@@ -1,534 +1,552 @@
 /*
- binary.h - Definitions for binary constants
- Copyright (c) 2006 David A. Mellis.  All right reserved.
+  binary.h - Definitions for binary constants
+  Deprecated -- use 0b binary literals instead
+  Copyright (c) 2006 David A. Mellis.  All right reserved.
 
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
 
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
 
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
 
 #ifndef Binary_h
 #define Binary_h
 
-#define B0 0
-#define B00 0
-#define B000 0
-#define B0000 0
-#define B00000 0
-#define B000000 0
-#define B0000000 0
-#define B00000000 0
-#define B1 1
-#define B01 1
-#define B001 1
-#define B0001 1
-#define B00001 1
-#define B000001 1
-#define B0000001 1
-#define B00000001 1
-#define B10 2
-#define B010 2
-#define B0010 2
-#define B00010 2
-#define B000010 2
-#define B0000010 2
-#define B00000010 2
-#define B11 3
-#define B011 3
-#define B0011 3
-#define B00011 3
-#define B000011 3
-#define B0000011 3
-#define B00000011 3
-#define B100 4
-#define B0100 4
-#define B00100 4
-#define B000100 4
-#define B0000100 4
-#define B00000100 4
-#define B101 5
-#define B0101 5
-#define B00101 5
-#define B000101 5
-#define B0000101 5
-#define B00000101 5
-#define B110 6
-#define B0110 6
-#define B00110 6
-#define B000110 6
-#define B0000110 6
-#define B00000110 6
-#define B111 7
-#define B0111 7
-#define B00111 7
-#define B000111 7
-#define B0000111 7
-#define B00000111 7
-#define B1000 8
-#define B01000 8
-#define B001000 8
-#define B0001000 8
-#define B00001000 8
-#define B1001 9
-#define B01001 9
-#define B001001 9
-#define B0001001 9
-#define B00001001 9
-#define B1010 10
-#define B01010 10
-#define B001010 10
-#define B0001010 10
-#define B00001010 10
-#define B1011 11
-#define B01011 11
-#define B001011 11
-#define B0001011 11
-#define B00001011 11
-#define B1100 12
-#define B01100 12
-#define B001100 12
-#define B0001100 12
-#define B00001100 12
-#define B1101 13
-#define B01101 13
-#define B001101 13
-#define B0001101 13
-#define B00001101 13
-#define B1110 14
-#define B01110 14
-#define B001110 14
-#define B0001110 14
-#define B00001110 14
-#define B1111 15
-#define B01111 15
-#define B001111 15
-#define B0001111 15
-#define B00001111 15
-#define B10000 16
-#define B010000 16
-#define B0010000 16
-#define B00010000 16
-#define B10001 17
-#define B010001 17
-#define B0010001 17
-#define B00010001 17
-#define B10010 18
-#define B010010 18
-#define B0010010 18
-#define B00010010 18
-#define B10011 19
-#define B010011 19
-#define B0010011 19
-#define B00010011 19
-#define B10100 20
-#define B010100 20
-#define B0010100 20
-#define B00010100 20
-#define B10101 21
-#define B010101 21
-#define B0010101 21
-#define B00010101 21
-#define B10110 22
-#define B010110 22
-#define B0010110 22
-#define B00010110 22
-#define B10111 23
-#define B010111 23
-#define B0010111 23
-#define B00010111 23
-#define B11000 24
-#define B011000 24
-#define B0011000 24
-#define B00011000 24
-#define B11001 25
-#define B011001 25
-#define B0011001 25
-#define B00011001 25
-#define B11010 26
-#define B011010 26
-#define B0011010 26
-#define B00011010 26
-#define B11011 27
-#define B011011 27
-#define B0011011 27
-#define B00011011 27
-#define B11100 28
-#define B011100 28
-#define B0011100 28
-#define B00011100 28
-#define B11101 29
-#define B011101 29
-#define B0011101 29
-#define B00011101 29
-#define B11110 30
-#define B011110 30
-#define B0011110 30
-#define B00011110 30
-#define B11111 31
-#define B011111 31
-#define B0011111 31
-#define B00011111 31
-#define B100000 32
-#define B0100000 32
-#define B00100000 32
-#define B100001 33
-#define B0100001 33
-#define B00100001 33
-#define B100010 34
-#define B0100010 34
-#define B00100010 34
-#define B100011 35
-#define B0100011 35
-#define B00100011 35
-#define B100100 36
-#define B0100100 36
-#define B00100100 36
-#define B100101 37
-#define B0100101 37
-#define B00100101 37
-#define B100110 38
-#define B0100110 38
-#define B00100110 38
-#define B100111 39
-#define B0100111 39
-#define B00100111 39
-#define B101000 40
-#define B0101000 40
-#define B00101000 40
-#define B101001 41
-#define B0101001 41
-#define B00101001 41
-#define B101010 42
-#define B0101010 42
-#define B00101010 42
-#define B101011 43
-#define B0101011 43
-#define B00101011 43
-#define B101100 44
-#define B0101100 44
-#define B00101100 44
-#define B101101 45
-#define B0101101 45
-#define B00101101 45
-#define B101110 46
-#define B0101110 46
-#define B00101110 46
-#define B101111 47
-#define B0101111 47
-#define B00101111 47
-#define B110000 48
-#define B0110000 48
-#define B00110000 48
-#define B110001 49
-#define B0110001 49
-#define B00110001 49
-#define B110010 50
-#define B0110010 50
-#define B00110010 50
-#define B110011 51
-#define B0110011 51
-#define B00110011 51
-#define B110100 52
-#define B0110100 52
-#define B00110100 52
-#define B110101 53
-#define B0110101 53
-#define B00110101 53
-#define B110110 54
-#define B0110110 54
-#define B00110110 54
-#define B110111 55
-#define B0110111 55
-#define B00110111 55
-#define B111000 56
-#define B0111000 56
-#define B00111000 56
-#define B111001 57
-#define B0111001 57
-#define B00111001 57
-#define B111010 58
-#define B0111010 58
-#define B00111010 58
-#define B111011 59
-#define B0111011 59
-#define B00111011 59
-#define B111100 60
-#define B0111100 60
-#define B00111100 60
-#define B111101 61
-#define B0111101 61
-#define B00111101 61
-#define B111110 62
-#define B0111110 62
-#define B00111110 62
-#define B111111 63
-#define B0111111 63
-#define B00111111 63
-#define B1000000 64
-#define B01000000 64
-#define B1000001 65
-#define B01000001 65
-#define B1000010 66
-#define B01000010 66
-#define B1000011 67
-#define B01000011 67
-#define B1000100 68
-#define B01000100 68
-#define B1000101 69
-#define B01000101 69
-#define B1000110 70
-#define B01000110 70
-#define B1000111 71
-#define B01000111 71
-#define B1001000 72
-#define B01001000 72
-#define B1001001 73
-#define B01001001 73
-#define B1001010 74
-#define B01001010 74
-#define B1001011 75
-#define B01001011 75
-#define B1001100 76
-#define B01001100 76
-#define B1001101 77
-#define B01001101 77
-#define B1001110 78
-#define B01001110 78
-#define B1001111 79
-#define B01001111 79
-#define B1010000 80
-#define B01010000 80
-#define B1010001 81
-#define B01010001 81
-#define B1010010 82
-#define B01010010 82
-#define B1010011 83
-#define B01010011 83
-#define B1010100 84
-#define B01010100 84
-#define B1010101 85
-#define B01010101 85
-#define B1010110 86
-#define B01010110 86
-#define B1010111 87
-#define B01010111 87
-#define B1011000 88
-#define B01011000 88
-#define B1011001 89
-#define B01011001 89
-#define B1011010 90
-#define B01011010 90
-#define B1011011 91
-#define B01011011 91
-#define B1011100 92
-#define B01011100 92
-#define B1011101 93
-#define B01011101 93
-#define B1011110 94
-#define B01011110 94
-#define B1011111 95
-#define B01011111 95
-#define B1100000 96
-#define B01100000 96
-#define B1100001 97
-#define B01100001 97
-#define B1100010 98
-#define B01100010 98
-#define B1100011 99
-#define B01100011 99
-#define B1100100 100
-#define B01100100 100
-#define B1100101 101
-#define B01100101 101
-#define B1100110 102
-#define B01100110 102
-#define B1100111 103
-#define B01100111 103
-#define B1101000 104
-#define B01101000 104
-#define B1101001 105
-#define B01101001 105
-#define B1101010 106
-#define B01101010 106
-#define B1101011 107
-#define B01101011 107
-#define B1101100 108
-#define B01101100 108
-#define B1101101 109
-#define B01101101 109
-#define B1101110 110
-#define B01101110 110
-#define B1101111 111
-#define B01101111 111
-#define B1110000 112
-#define B01110000 112
-#define B1110001 113
-#define B01110001 113
-#define B1110010 114
-#define B01110010 114
-#define B1110011 115
-#define B01110011 115
-#define B1110100 116
-#define B01110100 116
-#define B1110101 117
-#define B01110101 117
-#define B1110110 118
-#define B01110110 118
-#define B1110111 119
-#define B01110111 119
-#define B1111000 120
-#define B01111000 120
-#define B1111001 121
-#define B01111001 121
-#define B1111010 122
-#define B01111010 122
-#define B1111011 123
-#define B01111011 123
-#define B1111100 124
-#define B01111100 124
-#define B1111101 125
-#define B01111101 125
-#define B1111110 126
-#define B01111110 126
-#define B1111111 127
-#define B01111111 127
-#define B10000000 128
-#define B10000001 129
-#define B10000010 130
-#define B10000011 131
-#define B10000100 132
-#define B10000101 133
-#define B10000110 134
-#define B10000111 135
-#define B10001000 136
-#define B10001001 137
-#define B10001010 138
-#define B10001011 139
-#define B10001100 140
-#define B10001101 141
-#define B10001110 142
-#define B10001111 143
-#define B10010000 144
-#define B10010001 145
-#define B10010010 146
-#define B10010011 147
-#define B10010100 148
-#define B10010101 149
-#define B10010110 150
-#define B10010111 151
-#define B10011000 152
-#define B10011001 153
-#define B10011010 154
-#define B10011011 155
-#define B10011100 156
-#define B10011101 157
-#define B10011110 158
-#define B10011111 159
-#define B10100000 160
-#define B10100001 161
-#define B10100010 162
-#define B10100011 163
-#define B10100100 164
-#define B10100101 165
-#define B10100110 166
-#define B10100111 167
-#define B10101000 168
-#define B10101001 169
-#define B10101010 170
-#define B10101011 171
-#define B10101100 172
-#define B10101101 173
-#define B10101110 174
-#define B10101111 175
-#define B10110000 176
-#define B10110001 177
-#define B10110010 178
-#define B10110011 179
-#define B10110100 180
-#define B10110101 181
-#define B10110110 182
-#define B10110111 183
-#define B10111000 184
-#define B10111001 185
-#define B10111010 186
-#define B10111011 187
-#define B10111100 188
-#define B10111101 189
-#define B10111110 190
-#define B10111111 191
-#define B11000000 192
-#define B11000001 193
-#define B11000010 194
-#define B11000011 195
-#define B11000100 196
-#define B11000101 197
-#define B11000110 198
-#define B11000111 199
-#define B11001000 200
-#define B11001001 201
-#define B11001010 202
-#define B11001011 203
-#define B11001100 204
-#define B11001101 205
-#define B11001110 206
-#define B11001111 207
-#define B11010000 208
-#define B11010001 209
-#define B11010010 210
-#define B11010011 211
-#define B11010100 212
-#define B11010101 213
-#define B11010110 214
-#define B11010111 215
-#define B11011000 216
-#define B11011001 217
-#define B11011010 218
-#define B11011011 219
-#define B11011100 220
-#define B11011101 221
-#define B11011110 222
-#define B11011111 223
-#define B11100000 224
-#define B11100001 225
-#define B11100010 226
-#define B11100011 227
-#define B11100100 228
-#define B11100101 229
-#define B11100110 230
-#define B11100111 231
-#define B11101000 232
-#define B11101001 233
-#define B11101010 234
-#define B11101011 235
-#define B11101100 236
-#define B11101101 237
-#define B11101110 238
-#define B11101111 239
-#define B11110000 240
-#define B11110001 241
-#define B11110010 242
-#define B11110011 243
-#define B11110100 244
-#define B11110101 245
-#define B11110110 246
-#define B11110111 247
-#define B11111000 248
-#define B11111001 249
-#define B11111010 250
-#define B11111011 251
-#define B11111100 252
-#define B11111101 253
-#define B11111110 254
-#define B11111111 255
+/* If supported, 0b binary literals are preferable to these constants.
+ * In that case, warn the user about these being deprecated (if possible). */
+#if __cplusplus >= 201402L
+/* C++14 introduces binary literals; C++11 introduces [[deprecated()]] */
+#define DEPRECATED(x) [[deprecated("use " #x " instead")]]
+#elif __GNUC__ >= 6
+/* GCC 4.3 supports binary literals; GCC 6 supports __deprecated__ on enums*/
+#define DEPRECATED(x) __attribute__((__deprecated__("use " #x " instead")))
+#else
+/* binary literals not supported, or "deprecated" warning not displayable */
+#define DEPRECATED(x)
+#endif
+
+enum {
+  B0 DEPRECATED(0b0) = 0,
+  B00 DEPRECATED(0b00) = 0,
+  B000 DEPRECATED(0b000) = 0,
+  B0000 DEPRECATED(0b0000) = 0,
+  B00000 DEPRECATED(0b00000) = 0,
+  B000000 DEPRECATED(0b000000) = 0,
+  B0000000 DEPRECATED(0b0000000) = 0,
+  B00000000 DEPRECATED(0b00000000) = 0,
+  B1 DEPRECATED(0b1) = 1,
+  B01 DEPRECATED(0b01) = 1,
+  B001 DEPRECATED(0b001) = 1,
+  B0001 DEPRECATED(0b0001) = 1,
+  B00001 DEPRECATED(0b00001) = 1,
+  B000001 DEPRECATED(0b000001) = 1,
+  B0000001 DEPRECATED(0b0000001) = 1,
+  B00000001 DEPRECATED(0b00000001) = 1,
+  B10 DEPRECATED(0b10) = 2,
+  B010 DEPRECATED(0b010) = 2,
+  B0010 DEPRECATED(0b0010) = 2,
+  B00010 DEPRECATED(0b00010) = 2,
+  B000010 DEPRECATED(0b000010) = 2,
+  B0000010 DEPRECATED(0b0000010) = 2,
+  B00000010 DEPRECATED(0b00000010) = 2,
+  B11 DEPRECATED(0b11) = 3,
+  B011 DEPRECATED(0b011) = 3,
+  B0011 DEPRECATED(0b0011) = 3,
+  B00011 DEPRECATED(0b00011) = 3,
+  B000011 DEPRECATED(0b000011) = 3,
+  B0000011 DEPRECATED(0b0000011) = 3,
+  B00000011 DEPRECATED(0b00000011) = 3,
+  B100 DEPRECATED(0b100) = 4,
+  B0100 DEPRECATED(0b0100) = 4,
+  B00100 DEPRECATED(0b00100) = 4,
+  B000100 DEPRECATED(0b000100) = 4,
+  B0000100 DEPRECATED(0b0000100) = 4,
+  B00000100 DEPRECATED(0b00000100) = 4,
+  B101 DEPRECATED(0b101) = 5,
+  B0101 DEPRECATED(0b0101) = 5,
+  B00101 DEPRECATED(0b00101) = 5,
+  B000101 DEPRECATED(0b000101) = 5,
+  B0000101 DEPRECATED(0b0000101) = 5,
+  B00000101 DEPRECATED(0b00000101) = 5,
+  B110 DEPRECATED(0b110) = 6,
+  B0110 DEPRECATED(0b0110) = 6,
+  B00110 DEPRECATED(0b00110) = 6,
+  B000110 DEPRECATED(0b000110) = 6,
+  B0000110 DEPRECATED(0b0000110) = 6,
+  B00000110 DEPRECATED(0b00000110) = 6,
+  B111 DEPRECATED(0b111) = 7,
+  B0111 DEPRECATED(0b0111) = 7,
+  B00111 DEPRECATED(0b00111) = 7,
+  B000111 DEPRECATED(0b000111) = 7,
+  B0000111 DEPRECATED(0b0000111) = 7,
+  B00000111 DEPRECATED(0b00000111) = 7,
+  B1000 DEPRECATED(0b1000) = 8,
+  B01000 DEPRECATED(0b01000) = 8,
+  B001000 DEPRECATED(0b001000) = 8,
+  B0001000 DEPRECATED(0b0001000) = 8,
+  B00001000 DEPRECATED(0b00001000) = 8,
+  B1001 DEPRECATED(0b1001) = 9,
+  B01001 DEPRECATED(0b01001) = 9,
+  B001001 DEPRECATED(0b001001) = 9,
+  B0001001 DEPRECATED(0b0001001) = 9,
+  B00001001 DEPRECATED(0b00001001) = 9,
+  B1010 DEPRECATED(0b1010) = 10,
+  B01010 DEPRECATED(0b01010) = 10,
+  B001010 DEPRECATED(0b001010) = 10,
+  B0001010 DEPRECATED(0b0001010) = 10,
+  B00001010 DEPRECATED(0b00001010) = 10,
+  B1011 DEPRECATED(0b1011) = 11,
+  B01011 DEPRECATED(0b01011) = 11,
+  B001011 DEPRECATED(0b001011) = 11,
+  B0001011 DEPRECATED(0b0001011) = 11,
+  B00001011 DEPRECATED(0b00001011) = 11,
+  B1100 DEPRECATED(0b1100) = 12,
+  B01100 DEPRECATED(0b01100) = 12,
+  B001100 DEPRECATED(0b001100) = 12,
+  B0001100 DEPRECATED(0b0001100) = 12,
+  B00001100 DEPRECATED(0b00001100) = 12,
+  B1101 DEPRECATED(0b1101) = 13,
+  B01101 DEPRECATED(0b01101) = 13,
+  B001101 DEPRECATED(0b001101) = 13,
+  B0001101 DEPRECATED(0b0001101) = 13,
+  B00001101 DEPRECATED(0b00001101) = 13,
+  B1110 DEPRECATED(0b1110) = 14,
+  B01110 DEPRECATED(0b01110) = 14,
+  B001110 DEPRECATED(0b001110) = 14,
+  B0001110 DEPRECATED(0b0001110) = 14,
+  B00001110 DEPRECATED(0b00001110) = 14,
+  B1111 DEPRECATED(0b1111) = 15,
+  B01111 DEPRECATED(0b01111) = 15,
+  B001111 DEPRECATED(0b001111) = 15,
+  B0001111 DEPRECATED(0b0001111) = 15,
+  B00001111 DEPRECATED(0b00001111) = 15,
+  B10000 DEPRECATED(0b10000) = 16,
+  B010000 DEPRECATED(0b010000) = 16,
+  B0010000 DEPRECATED(0b0010000) = 16,
+  B00010000 DEPRECATED(0b00010000) = 16,
+  B10001 DEPRECATED(0b10001) = 17,
+  B010001 DEPRECATED(0b010001) = 17,
+  B0010001 DEPRECATED(0b0010001) = 17,
+  B00010001 DEPRECATED(0b00010001) = 17,
+  B10010 DEPRECATED(0b10010) = 18,
+  B010010 DEPRECATED(0b010010) = 18,
+  B0010010 DEPRECATED(0b0010010) = 18,
+  B00010010 DEPRECATED(0b00010010) = 18,
+  B10011 DEPRECATED(0b10011) = 19,
+  B010011 DEPRECATED(0b010011) = 19,
+  B0010011 DEPRECATED(0b0010011) = 19,
+  B00010011 DEPRECATED(0b00010011) = 19,
+  B10100 DEPRECATED(0b10100) = 20,
+  B010100 DEPRECATED(0b010100) = 20,
+  B0010100 DEPRECATED(0b0010100) = 20,
+  B00010100 DEPRECATED(0b00010100) = 20,
+  B10101 DEPRECATED(0b10101) = 21,
+  B010101 DEPRECATED(0b010101) = 21,
+  B0010101 DEPRECATED(0b0010101) = 21,
+  B00010101 DEPRECATED(0b00010101) = 21,
+  B10110 DEPRECATED(0b10110) = 22,
+  B010110 DEPRECATED(0b010110) = 22,
+  B0010110 DEPRECATED(0b0010110) = 22,
+  B00010110 DEPRECATED(0b00010110) = 22,
+  B10111 DEPRECATED(0b10111) = 23,
+  B010111 DEPRECATED(0b010111) = 23,
+  B0010111 DEPRECATED(0b0010111) = 23,
+  B00010111 DEPRECATED(0b00010111) = 23,
+  B11000 DEPRECATED(0b11000) = 24,
+  B011000 DEPRECATED(0b011000) = 24,
+  B0011000 DEPRECATED(0b0011000) = 24,
+  B00011000 DEPRECATED(0b00011000) = 24,
+  B11001 DEPRECATED(0b11001) = 25,
+  B011001 DEPRECATED(0b011001) = 25,
+  B0011001 DEPRECATED(0b0011001) = 25,
+  B00011001 DEPRECATED(0b00011001) = 25,
+  B11010 DEPRECATED(0b11010) = 26,
+  B011010 DEPRECATED(0b011010) = 26,
+  B0011010 DEPRECATED(0b0011010) = 26,
+  B00011010 DEPRECATED(0b00011010) = 26,
+  B11011 DEPRECATED(0b11011) = 27,
+  B011011 DEPRECATED(0b011011) = 27,
+  B0011011 DEPRECATED(0b0011011) = 27,
+  B00011011 DEPRECATED(0b00011011) = 27,
+  B11100 DEPRECATED(0b11100) = 28,
+  B011100 DEPRECATED(0b011100) = 28,
+  B0011100 DEPRECATED(0b0011100) = 28,
+  B00011100 DEPRECATED(0b00011100) = 28,
+  B11101 DEPRECATED(0b11101) = 29,
+  B011101 DEPRECATED(0b011101) = 29,
+  B0011101 DEPRECATED(0b0011101) = 29,
+  B00011101 DEPRECATED(0b00011101) = 29,
+  B11110 DEPRECATED(0b11110) = 30,
+  B011110 DEPRECATED(0b011110) = 30,
+  B0011110 DEPRECATED(0b0011110) = 30,
+  B00011110 DEPRECATED(0b00011110) = 30,
+  B11111 DEPRECATED(0b11111) = 31,
+  B011111 DEPRECATED(0b011111) = 31,
+  B0011111 DEPRECATED(0b0011111) = 31,
+  B00011111 DEPRECATED(0b00011111) = 31,
+  B100000 DEPRECATED(0b100000) = 32,
+  B0100000 DEPRECATED(0b0100000) = 32,
+  B00100000 DEPRECATED(0b00100000) = 32,
+  B100001 DEPRECATED(0b100001) = 33,
+  B0100001 DEPRECATED(0b0100001) = 33,
+  B00100001 DEPRECATED(0b00100001) = 33,
+  B100010 DEPRECATED(0b100010) = 34,
+  B0100010 DEPRECATED(0b0100010) = 34,
+  B00100010 DEPRECATED(0b00100010) = 34,
+  B100011 DEPRECATED(0b100011) = 35,
+  B0100011 DEPRECATED(0b0100011) = 35,
+  B00100011 DEPRECATED(0b00100011) = 35,
+  B100100 DEPRECATED(0b100100) = 36,
+  B0100100 DEPRECATED(0b0100100) = 36,
+  B00100100 DEPRECATED(0b00100100) = 36,
+  B100101 DEPRECATED(0b100101) = 37,
+  B0100101 DEPRECATED(0b0100101) = 37,
+  B00100101 DEPRECATED(0b00100101) = 37,
+  B100110 DEPRECATED(0b100110) = 38,
+  B0100110 DEPRECATED(0b0100110) = 38,
+  B00100110 DEPRECATED(0b00100110) = 38,
+  B100111 DEPRECATED(0b100111) = 39,
+  B0100111 DEPRECATED(0b0100111) = 39,
+  B00100111 DEPRECATED(0b00100111) = 39,
+  B101000 DEPRECATED(0b101000) = 40,
+  B0101000 DEPRECATED(0b0101000) = 40,
+  B00101000 DEPRECATED(0b00101000) = 40,
+  B101001 DEPRECATED(0b101001) = 41,
+  B0101001 DEPRECATED(0b0101001) = 41,
+  B00101001 DEPRECATED(0b00101001) = 41,
+  B101010 DEPRECATED(0b101010) = 42,
+  B0101010 DEPRECATED(0b0101010) = 42,
+  B00101010 DEPRECATED(0b00101010) = 42,
+  B101011 DEPRECATED(0b101011) = 43,
+  B0101011 DEPRECATED(0b0101011) = 43,
+  B00101011 DEPRECATED(0b00101011) = 43,
+  B101100 DEPRECATED(0b101100) = 44,
+  B0101100 DEPRECATED(0b0101100) = 44,
+  B00101100 DEPRECATED(0b00101100) = 44,
+  B101101 DEPRECATED(0b101101) = 45,
+  B0101101 DEPRECATED(0b0101101) = 45,
+  B00101101 DEPRECATED(0b00101101) = 45,
+  B101110 DEPRECATED(0b101110) = 46,
+  B0101110 DEPRECATED(0b0101110) = 46,
+  B00101110 DEPRECATED(0b00101110) = 46,
+  B101111 DEPRECATED(0b101111) = 47,
+  B0101111 DEPRECATED(0b0101111) = 47,
+  B00101111 DEPRECATED(0b00101111) = 47,
+  B110000 DEPRECATED(0b110000) = 48,
+  B0110000 DEPRECATED(0b0110000) = 48,
+  B00110000 DEPRECATED(0b00110000) = 48,
+  B110001 DEPRECATED(0b110001) = 49,
+  B0110001 DEPRECATED(0b0110001) = 49,
+  B00110001 DEPRECATED(0b00110001) = 49,
+  B110010 DEPRECATED(0b110010) = 50,
+  B0110010 DEPRECATED(0b0110010) = 50,
+  B00110010 DEPRECATED(0b00110010) = 50,
+  B110011 DEPRECATED(0b110011) = 51,
+  B0110011 DEPRECATED(0b0110011) = 51,
+  B00110011 DEPRECATED(0b00110011) = 51,
+  B110100 DEPRECATED(0b110100) = 52,
+  B0110100 DEPRECATED(0b0110100) = 52,
+  B00110100 DEPRECATED(0b00110100) = 52,
+  B110101 DEPRECATED(0b110101) = 53,
+  B0110101 DEPRECATED(0b0110101) = 53,
+  B00110101 DEPRECATED(0b00110101) = 53,
+  B110110 DEPRECATED(0b110110) = 54,
+  B0110110 DEPRECATED(0b0110110) = 54,
+  B00110110 DEPRECATED(0b00110110) = 54,
+  B110111 DEPRECATED(0b110111) = 55,
+  B0110111 DEPRECATED(0b0110111) = 55,
+  B00110111 DEPRECATED(0b00110111) = 55,
+  B111000 DEPRECATED(0b111000) = 56,
+  B0111000 DEPRECATED(0b0111000) = 56,
+  B00111000 DEPRECATED(0b00111000) = 56,
+  B111001 DEPRECATED(0b111001) = 57,
+  B0111001 DEPRECATED(0b0111001) = 57,
+  B00111001 DEPRECATED(0b00111001) = 57,
+  B111010 DEPRECATED(0b111010) = 58,
+  B0111010 DEPRECATED(0b0111010) = 58,
+  B00111010 DEPRECATED(0b00111010) = 58,
+  B111011 DEPRECATED(0b111011) = 59,
+  B0111011 DEPRECATED(0b0111011) = 59,
+  B00111011 DEPRECATED(0b00111011) = 59,
+  B111100 DEPRECATED(0b111100) = 60,
+  B0111100 DEPRECATED(0b0111100) = 60,
+  B00111100 DEPRECATED(0b00111100) = 60,
+  B111101 DEPRECATED(0b111101) = 61,
+  B0111101 DEPRECATED(0b0111101) = 61,
+  B00111101 DEPRECATED(0b00111101) = 61,
+  B111110 DEPRECATED(0b111110) = 62,
+  B0111110 DEPRECATED(0b0111110) = 62,
+  B00111110 DEPRECATED(0b00111110) = 62,
+  B111111 DEPRECATED(0b111111) = 63,
+  B0111111 DEPRECATED(0b0111111) = 63,
+  B00111111 DEPRECATED(0b00111111) = 63,
+  B1000000 DEPRECATED(0b1000000) = 64,
+  B01000000 DEPRECATED(0b01000000) = 64,
+  B1000001 DEPRECATED(0b1000001) = 65,
+  B01000001 DEPRECATED(0b01000001) = 65,
+  B1000010 DEPRECATED(0b1000010) = 66,
+  B01000010 DEPRECATED(0b01000010) = 66,
+  B1000011 DEPRECATED(0b1000011) = 67,
+  B01000011 DEPRECATED(0b01000011) = 67,
+  B1000100 DEPRECATED(0b1000100) = 68,
+  B01000100 DEPRECATED(0b01000100) = 68,
+  B1000101 DEPRECATED(0b1000101) = 69,
+  B01000101 DEPRECATED(0b01000101) = 69,
+  B1000110 DEPRECATED(0b1000110) = 70,
+  B01000110 DEPRECATED(0b01000110) = 70,
+  B1000111 DEPRECATED(0b1000111) = 71,
+  B01000111 DEPRECATED(0b01000111) = 71,
+  B1001000 DEPRECATED(0b1001000) = 72,
+  B01001000 DEPRECATED(0b01001000) = 72,
+  B1001001 DEPRECATED(0b1001001) = 73,
+  B01001001 DEPRECATED(0b01001001) = 73,
+  B1001010 DEPRECATED(0b1001010) = 74,
+  B01001010 DEPRECATED(0b01001010) = 74,
+  B1001011 DEPRECATED(0b1001011) = 75,
+  B01001011 DEPRECATED(0b01001011) = 75,
+  B1001100 DEPRECATED(0b1001100) = 76,
+  B01001100 DEPRECATED(0b01001100) = 76,
+  B1001101 DEPRECATED(0b1001101) = 77,
+  B01001101 DEPRECATED(0b01001101) = 77,
+  B1001110 DEPRECATED(0b1001110) = 78,
+  B01001110 DEPRECATED(0b01001110) = 78,
+  B1001111 DEPRECATED(0b1001111) = 79,
+  B01001111 DEPRECATED(0b01001111) = 79,
+  B1010000 DEPRECATED(0b1010000) = 80,
+  B01010000 DEPRECATED(0b01010000) = 80,
+  B1010001 DEPRECATED(0b1010001) = 81,
+  B01010001 DEPRECATED(0b01010001) = 81,
+  B1010010 DEPRECATED(0b1010010) = 82,
+  B01010010 DEPRECATED(0b01010010) = 82,
+  B1010011 DEPRECATED(0b1010011) = 83,
+  B01010011 DEPRECATED(0b01010011) = 83,
+  B1010100 DEPRECATED(0b1010100) = 84,
+  B01010100 DEPRECATED(0b01010100) = 84,
+  B1010101 DEPRECATED(0b1010101) = 85,
+  B01010101 DEPRECATED(0b01010101) = 85,
+  B1010110 DEPRECATED(0b1010110) = 86,
+  B01010110 DEPRECATED(0b01010110) = 86,
+  B1010111 DEPRECATED(0b1010111) = 87,
+  B01010111 DEPRECATED(0b01010111) = 87,
+  B1011000 DEPRECATED(0b1011000) = 88,
+  B01011000 DEPRECATED(0b01011000) = 88,
+  B1011001 DEPRECATED(0b1011001) = 89,
+  B01011001 DEPRECATED(0b01011001) = 89,
+  B1011010 DEPRECATED(0b1011010) = 90,
+  B01011010 DEPRECATED(0b01011010) = 90,
+  B1011011 DEPRECATED(0b1011011) = 91,
+  B01011011 DEPRECATED(0b01011011) = 91,
+  B1011100 DEPRECATED(0b1011100) = 92,
+  B01011100 DEPRECATED(0b01011100) = 92,
+  B1011101 DEPRECATED(0b1011101) = 93,
+  B01011101 DEPRECATED(0b01011101) = 93,
+  B1011110 DEPRECATED(0b1011110) = 94,
+  B01011110 DEPRECATED(0b01011110) = 94,
+  B1011111 DEPRECATED(0b1011111) = 95,
+  B01011111 DEPRECATED(0b01011111) = 95,
+  B1100000 DEPRECATED(0b1100000) = 96,
+  B01100000 DEPRECATED(0b01100000) = 96,
+  B1100001 DEPRECATED(0b1100001) = 97,
+  B01100001 DEPRECATED(0b01100001) = 97,
+  B1100010 DEPRECATED(0b1100010) = 98,
+  B01100010 DEPRECATED(0b01100010) = 98,
+  B1100011 DEPRECATED(0b1100011) = 99,
+  B01100011 DEPRECATED(0b01100011) = 99,
+  B1100100 DEPRECATED(0b1100100) = 100,
+  B01100100 DEPRECATED(0b01100100) = 100,
+  B1100101 DEPRECATED(0b1100101) = 101,
+  B01100101 DEPRECATED(0b01100101) = 101,
+  B1100110 DEPRECATED(0b1100110) = 102,
+  B01100110 DEPRECATED(0b01100110) = 102,
+  B1100111 DEPRECATED(0b1100111) = 103,
+  B01100111 DEPRECATED(0b01100111) = 103,
+  B1101000 DEPRECATED(0b1101000) = 104,
+  B01101000 DEPRECATED(0b01101000) = 104,
+  B1101001 DEPRECATED(0b1101001) = 105,
+  B01101001 DEPRECATED(0b01101001) = 105,
+  B1101010 DEPRECATED(0b1101010) = 106,
+  B01101010 DEPRECATED(0b01101010) = 106,
+  B1101011 DEPRECATED(0b1101011) = 107,
+  B01101011 DEPRECATED(0b01101011) = 107,
+  B1101100 DEPRECATED(0b1101100) = 108,
+  B01101100 DEPRECATED(0b01101100) = 108,
+  B1101101 DEPRECATED(0b1101101) = 109,
+  B01101101 DEPRECATED(0b01101101) = 109,
+  B1101110 DEPRECATED(0b1101110) = 110,
+  B01101110 DEPRECATED(0b01101110) = 110,
+  B1101111 DEPRECATED(0b1101111) = 111,
+  B01101111 DEPRECATED(0b01101111) = 111,
+  B1110000 DEPRECATED(0b1110000) = 112,
+  B01110000 DEPRECATED(0b01110000) = 112,
+  B1110001 DEPRECATED(0b1110001) = 113,
+  B01110001 DEPRECATED(0b01110001) = 113,
+  B1110010 DEPRECATED(0b1110010) = 114,
+  B01110010 DEPRECATED(0b01110010) = 114,
+  B1110011 DEPRECATED(0b1110011) = 115,
+  B01110011 DEPRECATED(0b01110011) = 115,
+  B1110100 DEPRECATED(0b1110100) = 116,
+  B01110100 DEPRECATED(0b01110100) = 116,
+  B1110101 DEPRECATED(0b1110101) = 117,
+  B01110101 DEPRECATED(0b01110101) = 117,
+  B1110110 DEPRECATED(0b1110110) = 118,
+  B01110110 DEPRECATED(0b01110110) = 118,
+  B1110111 DEPRECATED(0b1110111) = 119,
+  B01110111 DEPRECATED(0b01110111) = 119,
+  B1111000 DEPRECATED(0b1111000) = 120,
+  B01111000 DEPRECATED(0b01111000) = 120,
+  B1111001 DEPRECATED(0b1111001) = 121,
+  B01111001 DEPRECATED(0b01111001) = 121,
+  B1111010 DEPRECATED(0b1111010) = 122,
+  B01111010 DEPRECATED(0b01111010) = 122,
+  B1111011 DEPRECATED(0b1111011) = 123,
+  B01111011 DEPRECATED(0b01111011) = 123,
+  B1111100 DEPRECATED(0b1111100) = 124,
+  B01111100 DEPRECATED(0b01111100) = 124,
+  B1111101 DEPRECATED(0b1111101) = 125,
+  B01111101 DEPRECATED(0b01111101) = 125,
+  B1111110 DEPRECATED(0b1111110) = 126,
+  B01111110 DEPRECATED(0b01111110) = 126,
+  B1111111 DEPRECATED(0b1111111) = 127,
+  B01111111 DEPRECATED(0b01111111) = 127,
+  B10000000 DEPRECATED(0b10000000) = 128,
+  B10000001 DEPRECATED(0b10000001) = 129,
+  B10000010 DEPRECATED(0b10000010) = 130,
+  B10000011 DEPRECATED(0b10000011) = 131,
+  B10000100 DEPRECATED(0b10000100) = 132,
+  B10000101 DEPRECATED(0b10000101) = 133,
+  B10000110 DEPRECATED(0b10000110) = 134,
+  B10000111 DEPRECATED(0b10000111) = 135,
+  B10001000 DEPRECATED(0b10001000) = 136,
+  B10001001 DEPRECATED(0b10001001) = 137,
+  B10001010 DEPRECATED(0b10001010) = 138,
+  B10001011 DEPRECATED(0b10001011) = 139,
+  B10001100 DEPRECATED(0b10001100) = 140,
+  B10001101 DEPRECATED(0b10001101) = 141,
+  B10001110 DEPRECATED(0b10001110) = 142,
+  B10001111 DEPRECATED(0b10001111) = 143,
+  B10010000 DEPRECATED(0b10010000) = 144,
+  B10010001 DEPRECATED(0b10010001) = 145,
+  B10010010 DEPRECATED(0b10010010) = 146,
+  B10010011 DEPRECATED(0b10010011) = 147,
+  B10010100 DEPRECATED(0b10010100) = 148,
+  B10010101 DEPRECATED(0b10010101) = 149,
+  B10010110 DEPRECATED(0b10010110) = 150,
+  B10010111 DEPRECATED(0b10010111) = 151,
+  B10011000 DEPRECATED(0b10011000) = 152,
+  B10011001 DEPRECATED(0b10011001) = 153,
+  B10011010 DEPRECATED(0b10011010) = 154,
+  B10011011 DEPRECATED(0b10011011) = 155,
+  B10011100 DEPRECATED(0b10011100) = 156,
+  B10011101 DEPRECATED(0b10011101) = 157,
+  B10011110 DEPRECATED(0b10011110) = 158,
+  B10011111 DEPRECATED(0b10011111) = 159,
+  B10100000 DEPRECATED(0b10100000) = 160,
+  B10100001 DEPRECATED(0b10100001) = 161,
+  B10100010 DEPRECATED(0b10100010) = 162,
+  B10100011 DEPRECATED(0b10100011) = 163,
+  B10100100 DEPRECATED(0b10100100) = 164,
+  B10100101 DEPRECATED(0b10100101) = 165,
+  B10100110 DEPRECATED(0b10100110) = 166,
+  B10100111 DEPRECATED(0b10100111) = 167,
+  B10101000 DEPRECATED(0b10101000) = 168,
+  B10101001 DEPRECATED(0b10101001) = 169,
+  B10101010 DEPRECATED(0b10101010) = 170,
+  B10101011 DEPRECATED(0b10101011) = 171,
+  B10101100 DEPRECATED(0b10101100) = 172,
+  B10101101 DEPRECATED(0b10101101) = 173,
+  B10101110 DEPRECATED(0b10101110) = 174,
+  B10101111 DEPRECATED(0b10101111) = 175,
+  B10110000 DEPRECATED(0b10110000) = 176,
+  B10110001 DEPRECATED(0b10110001) = 177,
+  B10110010 DEPRECATED(0b10110010) = 178,
+  B10110011 DEPRECATED(0b10110011) = 179,
+  B10110100 DEPRECATED(0b10110100) = 180,
+  B10110101 DEPRECATED(0b10110101) = 181,
+  B10110110 DEPRECATED(0b10110110) = 182,
+  B10110111 DEPRECATED(0b10110111) = 183,
+  B10111000 DEPRECATED(0b10111000) = 184,
+  B10111001 DEPRECATED(0b10111001) = 185,
+  B10111010 DEPRECATED(0b10111010) = 186,
+  B10111011 DEPRECATED(0b10111011) = 187,
+  B10111100 DEPRECATED(0b10111100) = 188,
+  B10111101 DEPRECATED(0b10111101) = 189,
+  B10111110 DEPRECATED(0b10111110) = 190,
+  B10111111 DEPRECATED(0b10111111) = 191,
+  B11000000 DEPRECATED(0b11000000) = 192,
+  B11000001 DEPRECATED(0b11000001) = 193,
+  B11000010 DEPRECATED(0b11000010) = 194,
+  B11000011 DEPRECATED(0b11000011) = 195,
+  B11000100 DEPRECATED(0b11000100) = 196,
+  B11000101 DEPRECATED(0b11000101) = 197,
+  B11000110 DEPRECATED(0b11000110) = 198,
+  B11000111 DEPRECATED(0b11000111) = 199,
+  B11001000 DEPRECATED(0b11001000) = 200,
+  B11001001 DEPRECATED(0b11001001) = 201,
+  B11001010 DEPRECATED(0b11001010) = 202,
+  B11001011 DEPRECATED(0b11001011) = 203,
+  B11001100 DEPRECATED(0b11001100) = 204,
+  B11001101 DEPRECATED(0b11001101) = 205,
+  B11001110 DEPRECATED(0b11001110) = 206,
+  B11001111 DEPRECATED(0b11001111) = 207,
+  B11010000 DEPRECATED(0b11010000) = 208,
+  B11010001 DEPRECATED(0b11010001) = 209,
+  B11010010 DEPRECATED(0b11010010) = 210,
+  B11010011 DEPRECATED(0b11010011) = 211,
+  B11010100 DEPRECATED(0b11010100) = 212,
+  B11010101 DEPRECATED(0b11010101) = 213,
+  B11010110 DEPRECATED(0b11010110) = 214,
+  B11010111 DEPRECATED(0b11010111) = 215,
+  B11011000 DEPRECATED(0b11011000) = 216,
+  B11011001 DEPRECATED(0b11011001) = 217,
+  B11011010 DEPRECATED(0b11011010) = 218,
+  B11011011 DEPRECATED(0b11011011) = 219,
+  B11011100 DEPRECATED(0b11011100) = 220,
+  B11011101 DEPRECATED(0b11011101) = 221,
+  B11011110 DEPRECATED(0b11011110) = 222,
+  B11011111 DEPRECATED(0b11011111) = 223,
+  B11100000 DEPRECATED(0b11100000) = 224,
+  B11100001 DEPRECATED(0b11100001) = 225,
+  B11100010 DEPRECATED(0b11100010) = 226,
+  B11100011 DEPRECATED(0b11100011) = 227,
+  B11100100 DEPRECATED(0b11100100) = 228,
+  B11100101 DEPRECATED(0b11100101) = 229,
+  B11100110 DEPRECATED(0b11100110) = 230,
+  B11100111 DEPRECATED(0b11100111) = 231,
+  B11101000 DEPRECATED(0b11101000) = 232,
+  B11101001 DEPRECATED(0b11101001) = 233,
+  B11101010 DEPRECATED(0b11101010) = 234,
+  B11101011 DEPRECATED(0b11101011) = 235,
+  B11101100 DEPRECATED(0b11101100) = 236,
+  B11101101 DEPRECATED(0b11101101) = 237,
+  B11101110 DEPRECATED(0b11101110) = 238,
+  B11101111 DEPRECATED(0b11101111) = 239,
+  B11110000 DEPRECATED(0b11110000) = 240,
+  B11110001 DEPRECATED(0b11110001) = 241,
+  B11110010 DEPRECATED(0b11110010) = 242,
+  B11110011 DEPRECATED(0b11110011) = 243,
+  B11110100 DEPRECATED(0b11110100) = 244,
+  B11110101 DEPRECATED(0b11110101) = 245,
+  B11110110 DEPRECATED(0b11110110) = 246,
+  B11110111 DEPRECATED(0b11110111) = 247,
+  B11111000 DEPRECATED(0b11111000) = 248,
+  B11111001 DEPRECATED(0b11111001) = 249,
+  B11111010 DEPRECATED(0b11111010) = 250,
+  B11111011 DEPRECATED(0b11111011) = 251,
+  B11111100 DEPRECATED(0b11111100) = 252,
+  B11111101 DEPRECATED(0b11111101) = 253,
+  B11111110 DEPRECATED(0b11111110) = 254,
+  B11111111 DEPRECATED(0b11111111) = 255
+};
+
+#undef DEPRECATED
 
 #endif
diff --git a/cores/esp32/cbuf.cpp b/cores/esp32/cbuf.cpp
index ef7370a8a07..2f942d5bf79 100644
--- a/cores/esp32/cbuf.cpp
+++ b/cores/esp32/cbuf.cpp
@@ -19,178 +19,271 @@
  */
 
 #include "cbuf.h"
+#include "esp32-hal-log.h"
 
-cbuf::cbuf(size_t size) :
-    next(NULL), _size(size+1), _buf(new char[size+1]), _bufend(_buf + size + 1), _begin(_buf), _end(_begin)
-{
+#if CONFIG_DISABLE_HAL_LOCKS
+#define CBUF_MUTEX_CREATE()
+#define CBUF_MUTEX_LOCK()
+#define CBUF_MUTEX_UNLOCK()
+#define CBUF_MUTEX_DELETE()
+#else
+#define CBUF_MUTEX_CREATE()            \
+  if (_lock == NULL) {                 \
+    _lock = xSemaphoreCreateMutex();   \
+    if (_lock == NULL) {               \
+      log_e("failed to create mutex"); \
+    }                                  \
+  }
+#define CBUF_MUTEX_LOCK()                          \
+  if (_lock != NULL) {                             \
+    xSemaphoreTakeRecursive(_lock, portMAX_DELAY); \
+  }
+#define CBUF_MUTEX_UNLOCK()         \
+  if (_lock != NULL) {              \
+    xSemaphoreGiveRecursive(_lock); \
+  }
+#define CBUF_MUTEX_DELETE()      \
+  if (_lock != NULL) {           \
+    SemaphoreHandle_t l = _lock; \
+    _lock = NULL;                \
+    vSemaphoreDelete(l);         \
+  }
+#endif
+
+cbuf::cbuf(size_t size) : next(NULL), has_peek(false), peek_byte(0), _buf(xRingbufferCreate(size, RINGBUF_TYPE_BYTEBUF)) {
+  if (_buf == NULL) {
+    log_e("failed to allocate ring buffer");
+  }
+  CBUF_MUTEX_CREATE();
 }
 
-cbuf::~cbuf()
-{
-    delete[] _buf;
+cbuf::~cbuf() {
+  CBUF_MUTEX_LOCK();
+  if (_buf != NULL) {
+    RingbufHandle_t b = _buf;
+    _buf = NULL;
+    vRingbufferDelete(b);
+  }
+  CBUF_MUTEX_UNLOCK();
+  CBUF_MUTEX_DELETE();
 }
 
-size_t cbuf::resizeAdd(size_t addSize)
-{
-    return resize(_size + addSize);
+size_t cbuf::resizeAdd(size_t addSize) {
+  return resize(size() + addSize);
 }
 
-size_t cbuf::resize(size_t newSize)
-{
+size_t cbuf::resize(size_t newSize) {
+  CBUF_MUTEX_LOCK();
+  size_t _size = size();
+  if (newSize == _size) {
+    return _size;
+  }
 
-    size_t bytes_available = available();
-    newSize += 1;
-    // not lose any data
-    // if data can be lost use remove or flush before resize
-    if((newSize < bytes_available) || (newSize == _size)) {
-        return _size;
-    }
+  // not lose any data
+  // if data can be lost use remove or flush before resize
+  size_t bytes_available = available();
+  if (newSize < bytes_available) {
+    CBUF_MUTEX_UNLOCK();
+    log_e("new size is less than the currently available data size");
+    return _size;
+  }
 
-    char *newbuf = new char[newSize];
-    char *oldbuf = _buf;
+  RingbufHandle_t newbuf = xRingbufferCreate(newSize, RINGBUF_TYPE_BYTEBUF);
+  if (newbuf == NULL) {
+    CBUF_MUTEX_UNLOCK();
+    log_e("failed to allocate new ring buffer");
+    return _size;
+  }
 
-    if(!newbuf) {
+  if (_buf != NULL) {
+    if (bytes_available) {
+      char *old_data = (char *)malloc(bytes_available);
+      if (old_data == NULL) {
+        vRingbufferDelete(newbuf);
+        CBUF_MUTEX_UNLOCK();
+        log_e("failed to allocate temporary buffer");
         return _size;
+      }
+      bytes_available = read(old_data, bytes_available);
+      if (!bytes_available) {
+        free(old_data);
+        vRingbufferDelete(newbuf);
+        CBUF_MUTEX_UNLOCK();
+        log_e("failed to read previous data");
+        return _size;
+      }
+      if (xRingbufferSend(newbuf, (void *)old_data, bytes_available, 0) != pdTRUE) {
+        write(old_data, bytes_available);
+        free(old_data);
+        vRingbufferDelete(newbuf);
+        CBUF_MUTEX_UNLOCK();
+        log_e("failed to restore previous data");
+        return _size;
+      }
+      free(old_data);
     }
 
-    if(_buf) {
-        read(newbuf, bytes_available);
-        memset((newbuf + bytes_available), 0x00, (newSize - bytes_available));
-    }
-
-    _begin = newbuf;
-    _end = newbuf + bytes_available;
-    _bufend = newbuf + newSize;
-    _size = newSize;
-
+    RingbufHandle_t b = _buf;
     _buf = newbuf;
-    delete[] oldbuf;
-
-    return _size;
+    vRingbufferDelete(b);
+  } else {
+    _buf = newbuf;
+  }
+  CBUF_MUTEX_UNLOCK();
+  return newSize;
 }
 
-size_t cbuf::available() const
-{
-    if(_end >= _begin) {
-        return _end - _begin;
-    }
-    return _size - (_begin - _end);
+size_t cbuf::available() const {
+  size_t available = 0;
+  if (_buf != NULL) {
+    vRingbufferGetInfo(_buf, NULL, NULL, NULL, NULL, (UBaseType_t *)&available);
+  }
+  if (has_peek) {
+    available++;
+  }
+  return available;
 }
 
-size_t cbuf::size()
-{
-    return _size;
+size_t cbuf::size() {
+  size_t _size = 0;
+  if (_buf != NULL) {
+    _size = xRingbufferGetMaxItemSize(_buf);
+  }
+  return _size;
 }
 
-size_t cbuf::room() const
-{
-    if(_end >= _begin) {
-        return _size - (_end - _begin) - 1;
-    }
-    return _begin - _end - 1;
+size_t cbuf::room() const {
+  size_t _room = 0;
+  if (_buf != NULL) {
+    _room = xRingbufferGetCurFreeSize(_buf);
+  }
+  return _room;
 }
 
-int cbuf::peek()
-{
-    if(empty()) {
-        return -1;
-    }
-
-    return static_cast<int>(*_begin);
+bool cbuf::empty() const {
+  return available() == 0;
 }
 
-size_t cbuf::peek(char *dst, size_t size)
-{
-    size_t bytes_available = available();
-    size_t size_to_read = (size < bytes_available) ? size : bytes_available;
-    size_t size_read = size_to_read;
-    char * begin = _begin;
-    if(_end < _begin && size_to_read > (size_t) (_bufend - _begin)) {
-        size_t top_size = _bufend - _begin;
-        memcpy(dst, _begin, top_size);
-        begin = _buf;
-        size_to_read -= top_size;
-        dst += top_size;
-    }
-    memcpy(dst, begin, size_to_read);
-    return size_read;
+bool cbuf::full() const {
+  return room() == 0;
 }
 
-int cbuf::read()
-{
-    if(empty()) {
-        return -1;
+int cbuf::peek() {
+  if (!available()) {
+    return -1;
+  }
+
+  int c;
+
+  CBUF_MUTEX_LOCK();
+  if (has_peek) {
+    c = peek_byte;
+  } else {
+    c = read();
+    if (c >= 0) {
+      has_peek = true;
+      peek_byte = c;
     }
+  }
+  CBUF_MUTEX_UNLOCK();
+  return c;
+}
 
-    char result = *_begin;
-    _begin = wrap_if_bufend(_begin + 1);
-    return static_cast<int>(result);
+int cbuf::read() {
+  char result = 0;
+  if (!read(&result, 1)) {
+    return -1;
+  }
+  return static_cast<int>(result);
 }
 
-size_t cbuf::read(char* dst, size_t size)
-{
-    size_t bytes_available = available();
+size_t cbuf::read(char *dst, size_t size) {
+  CBUF_MUTEX_LOCK();
+  size_t bytes_available = available();
+  if (!bytes_available || !size) {
+    CBUF_MUTEX_UNLOCK();
+    return 0;
+  }
+
+  if (has_peek) {
+    if (dst != NULL) {
+      *dst++ = peek_byte;
+    }
+    size--;
+  }
+
+  size_t size_read = 0;
+  if (size) {
+    size_t received_size = 0;
     size_t size_to_read = (size < bytes_available) ? size : bytes_available;
-    size_t size_read = size_to_read;
-    if(_end < _begin && size_to_read > (size_t) (_bufend - _begin)) {
-        size_t top_size = _bufend - _begin;
-        memcpy(dst, _begin, top_size);
-        _begin = _buf;
-        size_to_read -= top_size;
-        dst += top_size;
+    uint8_t *received_buff = (uint8_t *)xRingbufferReceiveUpTo(_buf, &received_size, 0, size_to_read);
+    if (received_buff != NULL) {
+      if (dst != NULL) {
+        memcpy(dst, received_buff, received_size);
+      }
+      vRingbufferReturnItem(_buf, received_buff);
+      size_read = received_size;
+      size_to_read -= received_size;
+      // wrap around data
+      if (size_to_read) {
+        received_size = 0;
+        received_buff = (uint8_t *)xRingbufferReceiveUpTo(_buf, &received_size, 0, size_to_read);
+        if (received_buff != NULL) {
+          if (dst != NULL) {
+            memcpy(dst + size_read, received_buff, received_size);
+          }
+          vRingbufferReturnItem(_buf, received_buff);
+          size_read += received_size;
+        } else {
+          log_e("failed to read wrap around data from ring buffer");
+        }
+      }
+    } else {
+      log_e("failed to read from ring buffer");
     }
-    memcpy(dst, _begin, size_to_read);
-    _begin = wrap_if_bufend(_begin + size_to_read);
-    return size_read;
+  }
+
+  if (has_peek) {
+    has_peek = false;
+    size_read++;
+  }
+
+  CBUF_MUTEX_UNLOCK();
+  return size_read;
 }
 
-size_t cbuf::write(char c)
-{
-    if(full()) {
-        return 0;
-    }
+size_t cbuf::write(char c) {
+  return write(&c, 1);
+}
 
-    *_end = c;
-    _end = wrap_if_bufend(_end + 1);
-    return 1;
-}
-
-size_t cbuf::write(const char* src, size_t size)
-{
-    size_t bytes_available = room();
-    size_t size_to_write = (size < bytes_available) ? size : bytes_available;
-    size_t size_written = size_to_write;
-    if(_end >= _begin && size_to_write > (size_t) (_bufend - _end)) {
-        size_t top_size = _bufend - _end;
-        memcpy(_end, src, top_size);
-        _end = _buf;
-        size_to_write -= top_size;
-        src += top_size;
-    }
-    memcpy(_end, src, size_to_write);
-    _end = wrap_if_bufend(_end + size_to_write);
-    return size_written;
+size_t cbuf::write(const char *src, size_t size) {
+  CBUF_MUTEX_LOCK();
+  size_t bytes_available = room();
+  if (!bytes_available || !size) {
+    CBUF_MUTEX_UNLOCK();
+    return 0;
+  }
+  size_t size_to_write = (size < bytes_available) ? size : bytes_available;
+  if (xRingbufferSend(_buf, (void *)src, size_to_write, 0) != pdTRUE) {
+    CBUF_MUTEX_UNLOCK();
+    log_e("failed to write to ring buffer");
+    return 0;
+  }
+  CBUF_MUTEX_UNLOCK();
+  return size_to_write;
 }
 
-void cbuf::flush()
-{
-    _begin = _buf;
-    _end = _buf;
+void cbuf::flush() {
+  read(NULL, available());
 }
 
-size_t cbuf::remove(size_t size)
-{
-    size_t bytes_available = available();
-    if(size >= bytes_available) {
-        flush();
-        return 0;
-    }
+size_t cbuf::remove(size_t size) {
+  CBUF_MUTEX_LOCK();
+  size_t bytes_available = available();
+  if (bytes_available && size) {
     size_t size_to_remove = (size < bytes_available) ? size : bytes_available;
-    if(_end < _begin && size_to_remove > (size_t) (_bufend - _begin)) {
-        size_t top_size = _bufend - _begin;
-        _begin = _buf;
-        size_to_remove -= top_size;
-    }
-    _begin = wrap_if_bufend(_begin + size_to_remove);
-    return available();
+    bytes_available -= read(NULL, size_to_remove);
+  }
+  CBUF_MUTEX_UNLOCK();
+  return bytes_available;
 }
diff --git a/cores/esp32/cbuf.h b/cores/esp32/cbuf.h
index ca65affcce9..3d2a173a887 100644
--- a/cores/esp32/cbuf.h
+++ b/cores/esp32/cbuf.h
@@ -18,62 +18,48 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#ifndef __cbuf_h
-#define __cbuf_h
+#pragma once
 
 #include <stddef.h>
 #include <stdint.h>
 #include <string.h>
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/ringbuf.h"
+#include "freertos/semphr.h"
 
-class cbuf
-{
+class cbuf {
 public:
-    cbuf(size_t size);
-    ~cbuf();
+  cbuf(size_t size);
+  ~cbuf();
 
-    size_t resizeAdd(size_t addSize);
-    size_t resize(size_t newSize);
-    size_t available() const;
-    size_t size();
+  size_t resizeAdd(size_t addSize);
+  size_t resize(size_t newSize);
 
-    size_t room() const;
+  size_t available() const;
+  size_t size();
+  size_t room() const;
+  bool empty() const;
+  bool full() const;
 
-    inline bool empty() const
-    {
-        return _begin == _end;
-    }
+  int peek();
 
-    inline bool full() const
-    {
-        return wrap_if_bufend(_end + 1) == _begin;
-    }
+  int read();
+  size_t read(char *dst, size_t size);
 
-    int peek();
-    size_t peek(char *dst, size_t size);
+  size_t write(char c);
+  size_t write(const char *src, size_t size);
 
-    int read();
-    size_t read(char* dst, size_t size);
+  void flush();
+  size_t remove(size_t size);
 
-    size_t write(char c);
-    size_t write(const char* src, size_t size);
-
-    void flush();
-    size_t remove(size_t size);
-
-    cbuf *next;
-
-private:
-    inline char* wrap_if_bufend(char* ptr) const
-    {
-        return (ptr == _bufend) ? _buf : ptr;
-    }
-
-    size_t _size;
-    char* _buf;
-    const char* _bufend;
-    char* _begin;
-    char* _end;
+  cbuf *next;
+  bool has_peek;
+  uint8_t peek_byte;
 
+protected:
+  RingbufHandle_t _buf = NULL;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  SemaphoreHandle_t _lock = NULL;
+#endif
 };
-
-#endif//__cbuf_h
diff --git a/cores/esp32/chip-debug-report.cpp b/cores/esp32/chip-debug-report.cpp
new file mode 100644
index 00000000000..daafef3cab9
--- /dev/null
+++ b/cores/esp32/chip-debug-report.cpp
@@ -0,0 +1,338 @@
+#include "esp_heap_caps.h"
+#include "esp_chip_info.h"
+#include "esp_idf_version.h"
+#include "esp_arduino_version.h"
+#include "esp_rom_spiflash.h"
+#include "esp_flash.h"
+#include "esp_partition.h"
+#include "esp_app_format.h"
+#include "soc/efuse_reg.h"
+#include "soc/rtc.h"
+#include "soc/spi_reg.h"
+#if CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/spi_flash.h"
+#endif
+#include "esp_bit_defs.h"
+
+#include "Arduino.h"
+#include "esp32-hal-periman.h"
+
+#define chip_report_printf log_printf
+
+#define printMemCapsInfo(caps) _printMemCapsInfo(MALLOC_CAP_##caps, #caps)
+#define b2kb(b)                ((float)b / 1024.0)
+#define b2mb(b)                ((float)b / (1024.0 * 1024.0))
+static void _printMemCapsInfo(uint32_t caps, const char *caps_str) {
+  multi_heap_info_t info;
+  size_t total = heap_caps_get_total_size(caps);
+  heap_caps_get_info(&info, caps);
+  chip_report_printf("%s Memory Info:\n", caps_str);
+  chip_report_printf("------------------------------------------\n");
+  chip_report_printf("  Total Size        : %8u B (%6.1f KB)\n", total, b2kb(total));
+  chip_report_printf("  Free Bytes        : %8u B (%6.1f KB)\n", info.total_free_bytes, b2kb(info.total_free_bytes));
+  chip_report_printf("  Allocated Bytes   : %8u B (%6.1f KB)\n", info.total_allocated_bytes, b2kb(info.total_allocated_bytes));
+  chip_report_printf("  Minimum Free Bytes: %8u B (%6.1f KB)\n", info.minimum_free_bytes, b2kb(info.minimum_free_bytes));
+  chip_report_printf("  Largest Free Block: %8u B (%6.1f KB)\n", info.largest_free_block, b2kb(info.largest_free_block));
+}
+
+static void printPkgVersion(void) {
+  chip_report_printf("  Package           : ");
+#if CONFIG_IDF_TARGET_ESP32
+  uint32_t pkg_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_PACKAGE);
+  switch (pkg_ver) {
+    case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3: chip_report_printf("D0WD-R2-V3"); break;
+    case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6:   chip_report_printf("D0WD-Q6"); break;
+    case EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5:   chip_report_printf("D0WD-Q5"); break;
+    case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:   chip_report_printf("D2WD-Q5"); break;
+    case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH:    chip_report_printf("U4WD-H"); break;
+    case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:   chip_report_printf("PICO-D4"); break;
+    case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302: chip_report_printf("PICO-V3-02"); break;
+  }
+#elif CONFIG_IDF_TARGET_ESP32S2
+  uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
+  switch (pkg_ver) {
+    case 1:  chip_report_printf("FH16"); break;
+    case 2:  chip_report_printf("FH32"); break;
+    default: chip_report_printf("%lu", pkg_ver); break;
+  }
+#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6
+  uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
+  chip_report_printf("%lu", pkg_ver);
+#elif CONFIG_IDF_TARGET_ESP32C2
+  uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_BLK2_DATA1_REG, EFUSE_PKG_VERSION);
+  chip_report_printf("%lu", pkg_ver);
+#elif CONFIG_IDF_TARGET_ESP32H2
+  uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_4_REG, EFUSE_PKG_VERSION);
+  chip_report_printf("%lu", pkg_ver);
+#elif CONFIG_IDF_TARGET_ESP32P4
+  uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_2_REG, EFUSE_PKG_VERSION);
+  chip_report_printf("%lu", pkg_ver);
+#else
+  chip_report_printf("Unknown");
+#endif
+  chip_report_printf("\n");
+}
+
+static void printChipInfo(void) {
+  esp_chip_info_t info;
+  esp_chip_info(&info);
+  chip_report_printf("Chip Info:\n");
+  chip_report_printf("------------------------------------------\n");
+  chip_report_printf("  Model             : ");
+  switch (info.model) {
+    case CHIP_ESP32:   chip_report_printf("ESP32\n"); break;
+    case CHIP_ESP32S2: chip_report_printf("ESP32-S2\n"); break;
+    case CHIP_ESP32S3: chip_report_printf("ESP32-S3\n"); break;
+    case CHIP_ESP32C2: chip_report_printf("ESP32-C2\n"); break;
+    case CHIP_ESP32C3: chip_report_printf("ESP32-C3\n"); break;
+    case CHIP_ESP32C6: chip_report_printf("ESP32-C6\n"); break;
+    case CHIP_ESP32H2: chip_report_printf("ESP32-H2\n"); break;
+    case CHIP_ESP32P4: chip_report_printf("ESP32-P4\n"); break;
+    default:           chip_report_printf("Unknown %d\n", info.model); break;
+  }
+  printPkgVersion();
+  chip_report_printf("  Revision          : %.2f\n", (float)(info.revision) / 100.0);
+  chip_report_printf("  Cores             : %d\n", info.cores);
+  rtc_cpu_freq_config_t conf;
+  rtc_clk_cpu_freq_get_config(&conf);
+  chip_report_printf("  CPU Frequency     : %lu MHz\n", conf.freq_mhz);
+  chip_report_printf("  XTAL Frequency    : %d MHz\n", rtc_clk_xtal_freq_get());
+  chip_report_printf("  Features Bitfield : %#010x\n", info.features);
+  chip_report_printf("  Embedded Flash    : %s\n", (info.features & CHIP_FEATURE_EMB_FLASH) ? "Yes" : "No");
+  chip_report_printf("  Embedded PSRAM    : %s\n", (info.features & CHIP_FEATURE_EMB_PSRAM) ? "Yes" : "No");
+  chip_report_printf("  2.4GHz WiFi       : %s\n", (info.features & CHIP_FEATURE_WIFI_BGN) ? "Yes" : "No");
+  chip_report_printf("  Classic BT        : %s\n", (info.features & CHIP_FEATURE_BT) ? "Yes" : "No");
+  chip_report_printf("  BT Low Energy     : %s\n", (info.features & CHIP_FEATURE_BLE) ? "Yes" : "No");
+  chip_report_printf("  IEEE 802.15.4     : %s\n", (info.features & CHIP_FEATURE_IEEE802154) ? "Yes" : "No");
+}
+
+static void printFlashInfo(void) {
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+#define ESP_FLASH_IMAGE_BASE 0x1000
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define ESP_FLASH_IMAGE_BASE 0x2000
+#else
+#define ESP_FLASH_IMAGE_BASE 0x0000
+#endif
+// REG_SPI_BASE is not defined for S3/C3 ??
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
+#ifdef REG_SPI_BASE
+#undef REG_SPI_BASE
+#endif  // REG_SPI_BASE
+#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000)))
+#endif  // TARGET
+
+  chip_report_printf("Flash Info:\n");
+  chip_report_printf("------------------------------------------\n");
+  uint32_t hw_size = 1 << (g_rom_flashchip.device_id & 0xFF);
+  chip_report_printf("  Chip Size         : %8lu B (%.0f MB)\n", hw_size, b2mb(hw_size));
+  chip_report_printf("  Block Size        : %8lu B (%6.1f KB)\n", g_rom_flashchip.block_size, b2kb(g_rom_flashchip.block_size));
+  chip_report_printf("  Sector Size       : %8lu B (%6.1f KB)\n", g_rom_flashchip.sector_size, b2kb(g_rom_flashchip.sector_size));
+  chip_report_printf("  Page Size         : %8lu B (%6.1f KB)\n", g_rom_flashchip.page_size, b2kb(g_rom_flashchip.page_size));
+  esp_image_header_t fhdr;
+  esp_flash_read(esp_flash_default_chip, (void *)&fhdr, ESP_FLASH_IMAGE_BASE, sizeof(esp_image_header_t));
+  if (fhdr.magic == ESP_IMAGE_HEADER_MAGIC) {
+    uint32_t f_freq = 0;
+    switch (fhdr.spi_speed) {
+#if CONFIG_IDF_TARGET_ESP32H2
+      case 0x0: f_freq = 32; break;
+      case 0x2: f_freq = 16; break;
+      case 0xf: f_freq = 64; break;
+#else
+      case 0x0: f_freq = 40; break;
+      case 0x1: f_freq = 26; break;
+      case 0x2: f_freq = 20; break;
+      case 0xf: f_freq = 80; break;
+#endif
+      default: f_freq = fhdr.spi_speed; break;
+    }
+    chip_report_printf("  Bus Speed         : %lu MHz\n", f_freq);
+  }
+  chip_report_printf("  Bus Mode          : ");
+#if CONFIG_ESPTOOLPY_OCT_FLASH
+  chip_report_printf("OPI\n");
+#elif CONFIG_ESPTOOLPY_FLASHMODE_QIO
+  chip_report_printf("QIO\n");
+#elif CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+  chip_report_printf("QOUT\n");
+#elif CONFIG_ESPTOOLPY_FLASHMODE_DIO
+  chip_report_printf("DIO\n");
+#elif CONFIG_ESPTOOLPY_FLASHMODE_DOUT
+  chip_report_printf("DOUT\n");
+#endif
+}
+
+static void printPartitionsInfo(void) {
+  chip_report_printf("Partitions Info:\n");
+  chip_report_printf("------------------------------------------\n");
+  esp_partition_iterator_t iterator = esp_partition_find(ESP_PARTITION_TYPE_ANY, ESP_PARTITION_SUBTYPE_ANY, NULL);
+  if (iterator != NULL) {
+    esp_partition_iterator_t it = iterator;
+    while (it != NULL) {
+      const esp_partition_t *partition = esp_partition_get(it);
+      if (partition) {
+        chip_report_printf("  %17s : addr: 0x%08X, size: %7.1f KB", partition->label, partition->address, b2kb(partition->size));
+        if (partition->type == ESP_PARTITION_TYPE_APP) {
+          chip_report_printf(", type:  APP");
+          if (partition->subtype == 0) {
+            chip_report_printf(", subtype: FACTORY");
+          } else if (partition->subtype >= 0x10 && partition->subtype < 0x20) {
+            chip_report_printf(", subtype: OTA_%lu", partition->subtype - 0x10);
+          } else if (partition->subtype == 0x20) {
+            chip_report_printf(", subtype: TEST");
+          } else {
+            chip_report_printf(", subtype: 0x%02X", partition->subtype);
+          }
+        } else {
+          chip_report_printf(", type: DATA");
+          chip_report_printf(", subtype: ");
+          switch (partition->subtype) {
+            case ESP_PARTITION_SUBTYPE_DATA_OTA:       chip_report_printf("OTA"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_PHY:       chip_report_printf("PHY"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_NVS:       chip_report_printf("NVS"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_COREDUMP:  chip_report_printf("COREDUMP"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_NVS_KEYS:  chip_report_printf("NVS_KEYS"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM:  chip_report_printf("EFUSE_EM"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_UNDEFINED: chip_report_printf("UNDEFINED"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_ESPHTTPD:  chip_report_printf("ESPHTTPD"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_FAT:       chip_report_printf("FAT"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_SPIFFS:    chip_report_printf("SPIFFS"); break;
+            case ESP_PARTITION_SUBTYPE_DATA_LITTLEFS:  chip_report_printf("LITTLEFS"); break;
+            default:                                   chip_report_printf("0x%02X", partition->subtype); break;
+          }
+        }
+        chip_report_printf("\n");
+      }
+      it = esp_partition_next(it);
+    }
+    //esp_partition_iterator_release(iterator);
+  }
+}
+
+static void printSoftwareInfo(void) {
+  chip_report_printf("Software Info:\n");
+  chip_report_printf("------------------------------------------\n");
+  chip_report_printf("  Compile Date/Time : %s %s\n", __DATE__, __TIME__);
+#ifdef ARDUINO_HOST_OS
+  chip_report_printf("  Compile Host OS   : %s\n", ARDUINO_HOST_OS);
+#endif
+  chip_report_printf("  ESP-IDF Version   : %s\n", esp_get_idf_version());
+  chip_report_printf("  Arduino Version   : %s\n", ESP_ARDUINO_VERSION_STR);
+}
+
+static void printBoardInfo(void) {
+  chip_report_printf("Board Info:\n");
+  chip_report_printf("------------------------------------------\n");
+  chip_report_printf("  Arduino Board     : %s\n", ARDUINO_BOARD);
+  chip_report_printf("  Arduino Variant   : %s\n", ARDUINO_VARIANT);
+#ifdef ARDUINO_FQBN
+  chip_report_printf("  Arduino FQBN      : %s\n", ARDUINO_FQBN);
+#else
+#ifdef CORE_DEBUG_LEVEL
+  chip_report_printf("  Core Debug Level  : %d\n", CORE_DEBUG_LEVEL);
+#endif
+#ifdef ARDUINO_RUNNING_CORE
+  chip_report_printf("  Arduino Runs Core : %d\n", ARDUINO_RUNNING_CORE);
+  chip_report_printf("  Arduino Events on : %d\n", ARDUINO_EVENT_RUNNING_CORE);
+#endif
+#ifdef ARDUINO_USB_MODE
+  chip_report_printf("  Arduino USB Mode  : %d\n", ARDUINO_USB_MODE);
+#endif
+#ifdef ARDUINO_USB_CDC_ON_BOOT
+  chip_report_printf("  CDC On Boot       : %d\n", ARDUINO_USB_CDC_ON_BOOT);
+#endif
+#endif /* ARDUINO_FQBN */
+}
+
+static void printPerimanInfo(void) {
+  chip_report_printf("GPIO Info:\n");
+  chip_report_printf("------------------------------------------\n");
+#if defined(BOARD_HAS_PIN_REMAP)
+  chip_report_printf("  DPIN|GPIO : BUS_TYPE[bus/unit][chan]\n");
+#else
+  chip_report_printf("  GPIO : BUS_TYPE[bus/unit][chan]\n");
+#endif
+  chip_report_printf("  --------------------------------------  \n");
+  for (uint8_t i = 0; i < SOC_GPIO_PIN_COUNT; i++) {
+    if (!perimanPinIsValid(i)) {
+      continue;  //invalid pin
+    }
+    peripheral_bus_type_t type = perimanGetPinBusType(i);
+    if (type == ESP32_BUS_TYPE_INIT) {
+      continue;  //unused pin
+    }
+#if defined(BOARD_HAS_PIN_REMAP)
+    int dpin = gpioNumberToDigitalPin(i);
+    if (dpin < 0) {
+      continue;  //pin is not exported
+    } else {
+      chip_report_printf("  D%-3d|%4u : ", dpin, i);
+    }
+#else
+    chip_report_printf("  %4u : ", i);
+#endif
+    const char *extra_type = perimanGetPinBusExtraType(i);
+    if (extra_type) {
+      chip_report_printf("%s", extra_type);
+    } else {
+      chip_report_printf("%s", perimanGetTypeName(type));
+    }
+    int8_t bus_number = perimanGetPinBusNum(i);
+    if (bus_number != -1) {
+      chip_report_printf("[%u]", bus_number);
+    }
+    int8_t bus_channel = perimanGetPinBusChannel(i);
+    if (bus_channel != -1) {
+      chip_report_printf("[%u]", bus_channel);
+    }
+    chip_report_printf("\n");
+  }
+}
+
+void printBeforeSetupInfo(void) {
+#if ARDUINO_USB_CDC_ON_BOOT
+  Serial.begin(0);
+  Serial.setDebugOutput(true);
+  uint8_t t = 0;
+  while (!Serial && (t++ < 200)) {
+    delay(10);  //wait up to 2 seconds for the IDE to connect
+  }
+#endif
+  chip_report_printf("=========== Before Setup Start ===========\n");
+  printChipInfo();
+  chip_report_printf("------------------------------------------\n");
+  printMemCapsInfo(INTERNAL);
+  chip_report_printf("------------------------------------------\n");
+  if (psramFound()) {
+    printMemCapsInfo(SPIRAM);
+    chip_report_printf("  Bus Mode          : ");
+#if CONFIG_SPIRAM_MODE_OCT
+    chip_report_printf("OPI\n");
+#else
+    chip_report_printf("QSPI\n");
+#endif
+    chip_report_printf("------------------------------------------\n");
+  }
+  printFlashInfo();
+  chip_report_printf("------------------------------------------\n");
+  printPartitionsInfo();
+  chip_report_printf("------------------------------------------\n");
+  printSoftwareInfo();
+  chip_report_printf("------------------------------------------\n");
+  printBoardInfo();
+  chip_report_printf("============ Before Setup End ============\n");
+  delay(100);  //allow the print to finish
+}
+
+void printAfterSetupInfo(void) {
+  chip_report_printf("=========== After Setup Start ============\n");
+  printMemCapsInfo(INTERNAL);
+  chip_report_printf("------------------------------------------\n");
+  if (psramFound()) {
+    printMemCapsInfo(SPIRAM);
+    chip_report_printf("------------------------------------------\n");
+  }
+  printPerimanInfo();
+  chip_report_printf("============ After Setup End =============\n");
+  delay(20);  //allow the print to finish
+}
diff --git a/cores/esp32/chip-debug-report.h b/cores/esp32/chip-debug-report.h
new file mode 100644
index 00000000000..5c2c8498722
--- /dev/null
+++ b/cores/esp32/chip-debug-report.h
@@ -0,0 +1,9 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+void printBeforeSetupInfo(void);
+void printAfterSetupInfo(void);
diff --git a/cores/esp32/esp32-hal-adc.c b/cores/esp32/esp32-hal-adc.c
index ab9e7622c3a..c7cc1f5d556 100644
--- a/cores/esp32/esp32-hal-adc.c
+++ b/cores/esp32/esp32-hal-adc.c
@@ -1,4 +1,4 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2023 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,227 +13,680 @@
 // limitations under the License.
 
 #include "esp32-hal-adc.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "rom/ets_sys.h"
-#include "esp_attr.h"
-#include "esp_intr.h"
-#include "soc/rtc_io_reg.h"
-#include "soc/rtc_cntl_reg.h"
-#include "soc/sens_reg.h"
 
-#include "driver/adc.h"
-#include "esp_adc_cal.h"
+#if SOC_ADC_SUPPORTED
+#include "esp32-hal.h"
+#include "esp32-hal-periman.h"
+#include "esp_adc/adc_oneshot.h"
+#include "esp_adc/adc_continuous.h"
+#include "esp_adc/adc_cali_scheme.h"
 
-#define DEFAULT_VREF    1100
-static esp_adc_cal_characteristics_t *__analogCharacteristics[2] = {NULL, NULL};
-static uint8_t __analogAttenuation = 3;//11db
-static uint8_t __analogWidth = 3;//12 bits
-static uint8_t __analogClockDiv = 1;
-static uint16_t __analogVRef = 0;
-static uint8_t __analogVRefPin = 0;
+// ESP32-C2 does not define those two for some reason
+#ifndef SOC_ADC_DIGI_RESULT_BYTES
+#define SOC_ADC_DIGI_RESULT_BYTES (4)
+#endif
+#ifndef SOC_ADC_DIGI_DATA_BYTES_PER_CONV
+#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
+#endif
 
-void __analogSetWidth(uint8_t bits){
-    if(bits < 9){
-        bits = 9;
-    } else if(bits > 12){
-        bits = 12;
+static uint8_t __analogAttenuation = ADC_11db;
+static uint8_t __analogWidth = SOC_ADC_RTC_MAX_BITWIDTH;
+static uint8_t __analogReturnedWidth = SOC_ADC_RTC_MAX_BITWIDTH;
+
+typedef struct {
+  voidFuncPtr fn;
+  void *arg;
+} interrupt_config_t;
+
+typedef struct {
+  adc_oneshot_unit_handle_t adc_oneshot_handle;
+  adc_continuous_handle_t adc_continuous_handle;
+  interrupt_config_t adc_interrupt_handle;
+  adc_cali_handle_t adc_cali_handle;
+  uint32_t buffer_size;
+  uint32_t conversion_frame_size;
+} adc_handle_t;
+
+adc_handle_t adc_handle[SOC_ADC_PERIPH_NUM];
+
+static bool adcDetachBus(void *pin) {
+  adc_channel_t adc_channel;
+  adc_unit_t adc_unit;
+  uint8_t used_channels = 0;
+
+  adc_oneshot_io_to_channel((int)(pin - 1), &adc_unit, &adc_channel);
+  for (uint8_t channel = 0; channel < SOC_ADC_CHANNEL_NUM(adc_unit); channel++) {
+    int io_pin;
+    adc_oneshot_channel_to_io(adc_unit, channel, &io_pin);
+    if (perimanGetPinBusType(io_pin) == ESP32_BUS_TYPE_ADC_ONESHOT) {
+      used_channels++;
+    }
+  }
+
+  if (used_channels == 1) {  //only 1 channel is used
+    esp_err_t err = adc_oneshot_del_unit(adc_handle[adc_unit].adc_oneshot_handle);
+    if (err != ESP_OK) {
+      return false;
     }
-    __analogWidth = bits - 9;
-    adc1_config_width(__analogWidth);
+    adc_handle[adc_unit].adc_oneshot_handle = NULL;
+    if (adc_handle[adc_unit].adc_cali_handle != NULL) {
+#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED
+      err = adc_cali_delete_scheme_curve_fitting(adc_handle[adc_unit].adc_cali_handle);
+      if (err != ESP_OK) {
+        return false;
+      }
+#elif (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))
+      err = adc_cali_delete_scheme_line_fitting(adc_handle[adc_unit].adc_cali_handle);
+      if (err != ESP_OK) {
+        return false;
+      }
+#endif
+    }
+    adc_handle[adc_unit].adc_cali_handle = NULL;
+  }
+  return true;
 }
 
-void __analogSetClockDiv(uint8_t clockDiv){
-    if(!clockDiv){
-        clockDiv = 1;
+esp_err_t __analogChannelConfig(adc_bitwidth_t width, adc_attenuation_t atten, int8_t pin) {
+  esp_err_t err = ESP_OK;
+  adc_oneshot_chan_cfg_t config = {
+    .bitwidth = width,
+    .atten = (atten & 3),
+  };
+  if (pin == -1) {  //Reconfigure all used analog pins/channels
+    for (int adc_unit = 0; adc_unit < SOC_ADC_PERIPH_NUM; adc_unit++) {
+      if (adc_handle[adc_unit].adc_oneshot_handle != NULL) {
+        for (uint8_t channel = 0; channel < SOC_ADC_CHANNEL_NUM(adc_unit); channel++) {
+          int io_pin;
+          adc_oneshot_channel_to_io(adc_unit, channel, &io_pin);
+          if (perimanGetPinBusType(io_pin) == ESP32_BUS_TYPE_ADC_ONESHOT) {
+            err = adc_oneshot_config_channel(adc_handle[adc_unit].adc_oneshot_handle, channel, &config);
+            if (err != ESP_OK) {
+              log_e("adc_oneshot_config_channel failed with error: %d", err);
+              return err;
+            }
+          }
+        }
+        //ADC calibration reconfig only if all channels are updated
+        if (adc_handle[adc_unit].adc_cali_handle != NULL) {
+#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED
+          log_d("Deleting ADC_UNIT_%d cali handle", adc_unit);
+          err = adc_cali_delete_scheme_curve_fitting(adc_handle[adc_unit].adc_cali_handle);
+          if (err != ESP_OK) {
+            log_e("adc_cali_delete_scheme_curve_fitting failed with error: %d", err);
+            return err;
+          }
+          adc_cali_curve_fitting_config_t cali_config = {
+            .unit_id = adc_unit,
+            .atten = atten,
+            .bitwidth = width,
+          };
+          log_d("Creating ADC_UNIT_%d curve cali handle", adc_unit);
+          err = adc_cali_create_scheme_curve_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle);
+          if (err != ESP_OK) {
+            log_e("adc_cali_create_scheme_curve_fitting failed with error: %d", err);
+            return err;
+          }
+#elif (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))  //ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
+          log_d("Deleting ADC_UNIT_%d line cali handle", adc_unit);
+          err = adc_cali_delete_scheme_line_fitting(adc_handle[adc_unit].adc_cali_handle);
+          if (err != ESP_OK) {
+            log_e("adc_cali_delete_scheme_line_fitting failed with error: %d", err);
+            return err;
+          }
+          adc_cali_line_fitting_config_t cali_config = {
+            .unit_id = adc_unit,
+            .atten = atten,
+            .bitwidth = width,
+          };
+          log_d("Creating ADC_UNIT_%d line cali handle", adc_unit);
+          err = adc_cali_create_scheme_line_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle);
+          if (err != ESP_OK) {
+            log_e("adc_cali_create_scheme_line_fitting failed with error: %d", err);
+            return err;
+          }
+#endif
+        }
+      }
+    }
+
+    //make it default for next channels
+    __analogWidth = width;
+    __analogAttenuation = atten;
+  } else {  //Reconfigure single channel
+    if (perimanGetPinBusType(pin) == ESP32_BUS_TYPE_ADC_ONESHOT) {
+      adc_channel_t channel;
+      adc_unit_t adc_unit;
+
+      adc_oneshot_io_to_channel(pin, &adc_unit, &channel);
+      if (err != ESP_OK) {
+        log_e("Pin %u is not ADC pin!", pin);
+        return err;
+      }
+      err = adc_oneshot_config_channel(adc_handle[adc_unit].adc_oneshot_handle, channel, &config);
+      if (err != ESP_OK) {
+        log_e("adc_oneshot_config_channel failed with error: %d", err);
+        return err;
+      }
+    } else {
+      log_e("Pin is not configured as analog channel");
+    }
+  }
+  return ESP_OK;
+}
+
+static inline uint16_t mapResolution(uint16_t value) {
+  uint8_t from = __analogWidth;
+  if (from == __analogReturnedWidth) {
+    return value;
+  }
+  if (from > __analogReturnedWidth) {
+    return value >> (from - __analogReturnedWidth);
+  }
+  return value << (__analogReturnedWidth - from);
+}
+
+void __analogSetAttenuation(adc_attenuation_t attenuation) {
+  if (__analogChannelConfig(__analogWidth, attenuation, -1) != ESP_OK) {
+    log_e("__analogChannelConfig failed!");
+  }
+}
+
+#if CONFIG_IDF_TARGET_ESP32
+void __analogSetWidth(uint8_t bits) {
+  if (bits < SOC_ADC_RTC_MIN_BITWIDTH) {
+    bits = SOC_ADC_RTC_MIN_BITWIDTH;
+  } else if (bits > SOC_ADC_RTC_MAX_BITWIDTH) {
+    bits = SOC_ADC_RTC_MAX_BITWIDTH;
+  }
+  if (__analogChannelConfig(bits, __analogAttenuation, -1) != ESP_OK) {
+    log_e("__analogChannelConfig failed!");
+  }
+}
+#endif
+
+esp_err_t __analogInit(uint8_t pin, adc_channel_t channel, adc_unit_t adc_unit) {
+  esp_err_t err = ESP_OK;
+  if (adc_handle[adc_unit].adc_oneshot_handle == NULL) {
+    adc_oneshot_unit_init_cfg_t init_config1 = {
+      .unit_id = adc_unit,
+      .ulp_mode = ADC_ULP_MODE_DISABLE,
+    };
+    err = adc_oneshot_new_unit(&init_config1, &adc_handle[adc_unit].adc_oneshot_handle);
+
+    if (err != ESP_OK) {
+      log_e("adc_oneshot_new_unit failed with error: %d", err);
+      return err;
     }
-    __analogClockDiv = clockDiv;
-    adc_set_clk_div(__analogClockDiv);
+  }
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ADC_ONESHOT, adcDetachBus);
+
+  if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_ADC_ONESHOT, (void *)(pin + 1), adc_unit, channel)) {
+    adcDetachBus((void *)(pin + 1));
+    return err;
+  }
+
+  adc_oneshot_chan_cfg_t config = {
+    .bitwidth = __analogWidth,
+    .atten = __analogAttenuation,
+  };
+
+  err = adc_oneshot_config_channel(adc_handle[adc_unit].adc_oneshot_handle, channel, &config);
+  if (err != ESP_OK) {
+    log_e("adc_oneshot_config_channel failed with error: %d", err);
+    return err;
+  }
+  return ESP_OK;
+}
+
+void __analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation) {
+  if (__analogChannelConfig(__analogWidth, attenuation, pin) != ESP_OK) {
+    log_e("__analogChannelConfig failed!");
+  }
 }
 
-void __analogSetAttenuation(adc_attenuation_t attenuation)
-{
-    __analogAttenuation = attenuation & 3;
+void __analogReadResolution(uint8_t bits) {
+  if (!bits || bits > 16) {
+    return;
+  }
+  __analogReturnedWidth = bits;
+
+#if CONFIG_IDF_TARGET_ESP32
+  __analogSetWidth(bits);  // hardware analog resolution from 9 to 12
+#endif
 }
 
-void __analogInit(){
-    static bool initialized = false;
-    if(initialized){
-        return;
+uint16_t __analogRead(uint8_t pin) {
+  int value = 0;
+  adc_channel_t channel;
+  adc_unit_t adc_unit;
+
+  esp_err_t err = ESP_OK;
+  err = adc_oneshot_io_to_channel(pin, &adc_unit, &channel);
+  if (err != ESP_OK) {
+    log_e("Pin %u is not ADC pin!", pin);
+    return value;
+  }
+
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_ADC_ONESHOT) == NULL) {
+    log_d("Calling __analogInit! pin = %d", pin);
+    err = __analogInit(pin, channel, adc_unit);
+    if (err != ESP_OK) {
+      log_e("Analog initialization failed!");
+      return value;
     }
-    initialized = true;
-    __analogSetClockDiv(__analogClockDiv);
-    __analogSetWidth(__analogWidth + 9);//in bits
+  }
+
+  adc_oneshot_read(adc_handle[adc_unit].adc_oneshot_handle, channel, &value);
+  return mapResolution(value);
 }
 
-void __analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation)
-{
-    int8_t channel = digitalPinToAnalogChannel(pin);
-    if(channel < 0 || attenuation > 3){
-        return ;
+uint32_t __analogReadMilliVolts(uint8_t pin) {
+  int value = 0;
+  adc_channel_t channel;
+  adc_unit_t adc_unit;
+  esp_err_t err = ESP_OK;
+
+  adc_oneshot_io_to_channel(pin, &adc_unit, &channel);
+  if (err != ESP_OK) {
+    log_e("Pin %u is not ADC pin!", pin);
+    return value;
+  }
+
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_ADC_ONESHOT) == NULL) {
+    err = __analogInit(pin, channel, adc_unit);
+    if (err != ESP_OK) {
+      log_e("Analog initialization failed!");
+      return value;
     }
-    if(channel > 9){
-        adc2_config_channel_atten(channel - 10, attenuation);
-    } else {
-        adc1_config_channel_atten(channel, attenuation);
+  }
+
+  if (adc_handle[adc_unit].adc_cali_handle == NULL) {
+    log_d("Creating cali handle for ADC_%d", adc_unit);
+#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED
+    adc_cali_curve_fitting_config_t cali_config = {
+      .unit_id = adc_unit,
+      .atten = __analogAttenuation,
+      .bitwidth = __analogWidth,
+    };
+    err = adc_cali_create_scheme_curve_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle);
+#elif (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))  //ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
+    adc_cali_line_fitting_config_t cali_config = {
+      .unit_id = adc_unit,
+      .bitwidth = __analogWidth,
+      .atten = __analogAttenuation,
+    };
+    err = adc_cali_create_scheme_line_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle);
+#endif
+    if (err != ESP_OK) {
+      log_e("adc_cali_create_scheme_x failed!");
+      return value;
     }
-    __analogInit();
+  }
+
+  err = adc_oneshot_get_calibrated_result(adc_handle[adc_unit].adc_oneshot_handle, adc_handle[adc_unit].adc_cali_handle, channel, &value);
+  if (err != ESP_OK) {
+    log_e("adc_oneshot_get_calibrated_result failed!");
+    return 0;
+  }
+  return value;
 }
 
-bool __adcAttachPin(uint8_t pin){
-    int8_t channel = digitalPinToAnalogChannel(pin);
-    if(channel < 0){
-        log_e("Pin %u is not ADC pin!", pin);
+extern uint16_t analogRead(uint8_t pin) __attribute__((weak, alias("__analogRead")));
+extern uint32_t analogReadMilliVolts(uint8_t pin) __attribute__((weak, alias("__analogReadMilliVolts")));
+extern void analogReadResolution(uint8_t bits) __attribute__((weak, alias("__analogReadResolution")));
+extern void analogSetAttenuation(adc_attenuation_t attenuation) __attribute__((weak, alias("__analogSetAttenuation")));
+extern void analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation) __attribute__((weak, alias("__analogSetPinAttenuation")));
+
+#if CONFIG_IDF_TARGET_ESP32
+extern void analogSetWidth(uint8_t bits) __attribute__((weak, alias("__analogSetWidth")));
+#endif
+
+/*
+ *  ADC Continuous mode
+ */
+
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+#define ADC_OUTPUT_TYPE         ADC_DIGI_OUTPUT_FORMAT_TYPE1
+#define ADC_GET_CHANNEL(p_data) ((p_data)->type1.channel)
+#define ADC_GET_DATA(p_data)    ((p_data)->type1.data)
+#else
+#define ADC_OUTPUT_TYPE         ADC_DIGI_OUTPUT_FORMAT_TYPE2
+#define ADC_GET_CHANNEL(p_data) ((p_data)->type2.channel)
+#define ADC_GET_DATA(p_data)    ((p_data)->type2.data)
+#endif
+
+static uint8_t __adcContinuousAtten = ADC_11db;
+static uint8_t __adcContinuousWidth = SOC_ADC_DIGI_MAX_BITWIDTH;
+
+static uint8_t used_adc_channels = 0;
+adc_continuous_data_t *adc_result = NULL;
+
+static bool adcContinuousDetachBus(void *adc_unit_number) {
+  adc_unit_t adc_unit = (adc_unit_t)adc_unit_number - 1;
+
+  if (adc_handle[adc_unit].adc_continuous_handle == NULL) {
+    return true;
+  } else {
+    esp_err_t err = adc_continuous_deinit(adc_handle[adc_unit].adc_continuous_handle);
+    if (err != ESP_OK) {
+      return false;
+    }
+    adc_handle[adc_unit].adc_continuous_handle = NULL;
+    if (adc_handle[adc_unit].adc_cali_handle != NULL) {
+#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED
+      err = adc_cali_delete_scheme_curve_fitting(adc_handle[adc_unit].adc_cali_handle);
+      if (err != ESP_OK) {
         return false;
+      }
+#elif (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))
+      err = adc_cali_delete_scheme_line_fitting(adc_handle[adc_unit].adc_cali_handle);
+      if (err != ESP_OK) {
+        return false;
+      }
+#endif
     }
-    int8_t pad = digitalPinToTouchChannel(pin);
-    if(pad >= 0){
-        uint32_t touch = READ_PERI_REG(SENS_SAR_TOUCH_ENABLE_REG);
-        if(touch & (1 << pad)){
-            touch &= ~((1 << (pad + SENS_TOUCH_PAD_OUTEN2_S))
-                    | (1 << (pad + SENS_TOUCH_PAD_OUTEN1_S))
-                    | (1 << (pad + SENS_TOUCH_PAD_WORKEN_S)));
-            WRITE_PERI_REG(SENS_SAR_TOUCH_ENABLE_REG, touch);
+    adc_handle[adc_unit].adc_cali_handle = NULL;
+
+    //set all used pins to INIT state
+    for (uint8_t channel = 0; channel < SOC_ADC_CHANNEL_NUM(adc_unit); channel++) {
+      int io_pin;
+      adc_oneshot_channel_to_io(adc_unit, channel, &io_pin);
+      if (perimanGetPinBusType(io_pin) == ESP32_BUS_TYPE_ADC_CONT) {
+        if (!perimanClearPinBus(io_pin)) {
+          return false;
         }
-    } else if(pin == 25){
-        CLEAR_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC | RTC_IO_PDAC1_DAC_XPD_FORCE);//stop dac1
-    } else if(pin == 26){
-        CLEAR_PERI_REG_MASK(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_XPD_DAC | RTC_IO_PDAC2_DAC_XPD_FORCE);//stop dac2
+      }
     }
-
-    pinMode(pin, ANALOG);
-    __analogSetPinAttenuation(pin, __analogAttenuation);
-    return true;
+  }
+  return true;
 }
 
-void __analogReadResolution(uint8_t bits)
-{
-    if(!bits || bits > 16){
-        return;
+bool IRAM_ATTR adcFnWrapper(adc_continuous_handle_t handle, const adc_continuous_evt_data_t *edata, void *args) {
+  interrupt_config_t *isr = (interrupt_config_t *)args;
+  //Check if edata->size matches conversion_frame_size, else just return from ISR
+  if (edata->size == adc_handle[0].conversion_frame_size) {
+    if (isr->fn) {
+      if (isr->arg) {
+        ((voidFuncPtrArg)isr->fn)(isr->arg);
+      } else {
+        isr->fn();
+      }
     }
-    __analogSetWidth(bits);         // hadware from 9 to 12
+  }
+  return false;
 }
 
-uint16_t __analogRead(uint8_t pin)
-{
-    int8_t channel = digitalPinToAnalogChannel(pin);
-    int value = 0;
-    esp_err_t r = ESP_OK;
-    if(channel < 0){
-        log_e("Pin %u is not ADC pin!", pin);
-        return value;
-    }
-    __adcAttachPin(pin);
-    if(channel > 9){
-        channel -= 10;
-        r = adc2_get_raw( channel, __analogWidth, &value);
-        if ( r == ESP_OK ) {
-            return value;
-        } else if ( r == ESP_ERR_INVALID_STATE ) {
-            log_e("GPIO%u: %s: ADC2 not initialized yet.", pin, esp_err_to_name(r));
-        } else if ( r == ESP_ERR_TIMEOUT ) {
-            log_e("GPIO%u: %s: ADC2 is in use by Wi-Fi.", pin, esp_err_to_name(r));
-        } else {
-            log_e("GPIO%u: %s", pin, esp_err_to_name(r));
-        }
-    } else {
-        return adc1_get_raw(channel);
-    }
-    return value;
+esp_err_t __analogContinuousInit(adc_channel_t *channel, uint8_t channel_num, adc_unit_t adc_unit, uint32_t sampling_freq_hz) {
+  //Create new ADC continuous handle
+  adc_continuous_handle_cfg_t adc_config = {
+    .max_store_buf_size = adc_handle[adc_unit].buffer_size,
+    .conv_frame_size = adc_handle[adc_unit].conversion_frame_size,
+  };
+
+  esp_err_t err = adc_continuous_new_handle(&adc_config, &adc_handle[adc_unit].adc_continuous_handle);
+  if (err != ESP_OK) {
+    log_e("adc_continuous_new_handle failed with error: %d", err);
+    return ESP_FAIL;
+  }
+
+  //Configure adc pins
+  adc_continuous_config_t dig_cfg = {
+    .sample_freq_hz = sampling_freq_hz,
+    .conv_mode = ADC_CONV_SINGLE_UNIT_1,
+    .format = ADC_OUTPUT_TYPE,
+  };
+  adc_digi_pattern_config_t adc_pattern[SOC_ADC_PATT_LEN_MAX] = {0};
+  dig_cfg.pattern_num = channel_num;
+  for (int i = 0; i < channel_num; i++) {
+    adc_pattern[i].atten = __adcContinuousAtten;
+    adc_pattern[i].channel = channel[i];
+    adc_pattern[i].unit = ADC_UNIT_1;
+    adc_pattern[i].bit_width = __adcContinuousWidth;
+  }
+  dig_cfg.adc_pattern = adc_pattern;
+  err = adc_continuous_config(adc_handle[adc_unit].adc_continuous_handle, &dig_cfg);
+
+  if (err != ESP_OK) {
+    log_e("adc_continuous_config failed with error: %d", err);
+    return ESP_FAIL;
+  }
+
+  used_adc_channels = channel_num;
+  return ESP_OK;
 }
 
-void __analogSetVRefPin(uint8_t pin){
-    if(pin <25 || pin > 27){
-        pin = 0;
+bool analogContinuous(const uint8_t pins[], size_t pins_count, uint32_t conversions_per_pin, uint32_t sampling_freq_hz, void (*userFunc)(void)) {
+  adc_channel_t channel[pins_count];
+  adc_unit_t adc_unit = ADC_UNIT_1;
+  esp_err_t err = ESP_OK;
+
+  //Convert pins to channels and check if all are ADC1s unit
+  for (int i = 0; i < pins_count; i++) {
+    err = adc_continuous_io_to_channel(pins[i], &adc_unit, &channel[i]);
+    if (err != ESP_OK) {
+      log_e("Pin %u is not ADC pin!", pins[i]);
+      return false;
+    }
+    if (adc_unit != 0) {
+      log_e("Only ADC1 pins are supported in continuous mode!");
+      return false;
     }
-    __analogVRefPin = pin;
+  }
+
+  //Check if Oneshot and Continuous handle exists
+  if (adc_handle[adc_unit].adc_oneshot_handle != NULL) {
+    log_e("ADC%d is running in oneshot mode. Aborting.", adc_unit + 1);
+    return false;
+  }
+  if (adc_handle[adc_unit].adc_continuous_handle != NULL) {
+    log_e("ADC%d continuous is already initialized. To reconfigure call analogContinuousDeinit() first.", adc_unit + 1);
+    return false;
+  }
+
+  //Check sampling frequency
+  if ((sampling_freq_hz < SOC_ADC_SAMPLE_FREQ_THRES_LOW) || (sampling_freq_hz > SOC_ADC_SAMPLE_FREQ_THRES_HIGH)) {
+    log_e("Sampling frequency is out of range. Supported sampling frequencies are %d - %d", SOC_ADC_SAMPLE_FREQ_THRES_LOW, SOC_ADC_SAMPLE_FREQ_THRES_HIGH);
+    return false;
+  }
+
+  //Set periman deinit function and reset all pins to init state.
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ADC_CONT, adcContinuousDetachBus);
+  for (int j = 0; j < pins_count; j++) {
+    if (!perimanClearPinBus(pins[j])) {
+      return false;
+    }
+  }
+
+  //Set conversion frame and buffer size (conversion frame must be in multiples of SOC_ADC_DIGI_DATA_BYTES_PER_CONV)
+  adc_handle[adc_unit].conversion_frame_size = conversions_per_pin * pins_count * SOC_ADC_DIGI_RESULT_BYTES;
+
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+  uint8_t calc_multiple = adc_handle[adc_unit].conversion_frame_size % SOC_ADC_DIGI_DATA_BYTES_PER_CONV;
+  if (calc_multiple != 0) {
+    adc_handle[adc_unit].conversion_frame_size = (adc_handle[adc_unit].conversion_frame_size + calc_multiple);
+  }
+#endif
+
+  adc_handle[adc_unit].buffer_size = adc_handle[adc_unit].conversion_frame_size * 2;
+
+  //Conversion frame size buffer cant be bigger than 4092 bytes
+  if (adc_handle[adc_unit].conversion_frame_size > 4092) {
+    log_e("Buffers are too big. Please set lower conversions per pin.");
+    return false;
+  }
+
+  //Initialize continuous handle and pins
+  err = __analogContinuousInit(channel, sizeof(channel) / sizeof(adc_channel_t), adc_unit, sampling_freq_hz);
+  if (err != ESP_OK) {
+    log_e("Analog initialization failed!");
+    return false;
+  }
+
+  //Setup callbacks for complete event
+  adc_continuous_evt_cbs_t cbs = {
+    .on_conv_done = adcFnWrapper,
+    //.on_pool_ovf can be used in future
+  };
+  adc_handle[adc_unit].adc_interrupt_handle.fn = (voidFuncPtr)userFunc;
+  err = adc_continuous_register_event_callbacks(adc_handle[adc_unit].adc_continuous_handle, &cbs, &adc_handle[adc_unit].adc_interrupt_handle);
+  if (err != ESP_OK) {
+    log_e("adc_continuous_register_event_callbacks failed!");
+    return false;
+  }
+
+  //Allocate and prepare result structure for adc readings
+  adc_result = malloc(pins_count * sizeof(adc_continuous_data_t));
+  for (int k = 0; k < pins_count; k++) {
+    adc_result[k].pin = pins[k];
+    adc_result[k].channel = channel[k];
+  }
+
+  //Initialize ADC calibration handle
+  if (adc_handle[adc_unit].adc_cali_handle == NULL) {
+    log_d("Creating cali handle for ADC_%d", adc_unit);
+#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED
+    adc_cali_curve_fitting_config_t cali_config = {
+      .unit_id = adc_unit,
+      .atten = __adcContinuousAtten,
+      .bitwidth = __adcContinuousWidth,
+    };
+    err = adc_cali_create_scheme_curve_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle);
+#elif (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))  //ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
+    adc_cali_line_fitting_config_t cali_config = {
+      .unit_id = adc_unit,
+      .bitwidth = __adcContinuousWidth,
+      .atten = __adcContinuousAtten,
+    };
+    err = adc_cali_create_scheme_line_fitting(&cali_config, &adc_handle[adc_unit].adc_cali_handle);
+#endif
+    if (err != ESP_OK) {
+      log_e("adc_cali_create_scheme_x failed!");
+      return false;
+    }
+  }
+
+  for (int k = 0; k < pins_count; k++) {
+    if (!perimanSetPinBus(pins[k], ESP32_BUS_TYPE_ADC_CONT, (void *)(adc_unit + 1), adc_unit, channel[k])) {
+      log_e("perimanSetPinBus to ADC Continuous failed!");
+      adcContinuousDetachBus((void *)(adc_unit + 1));
+      return false;
+    }
+  }
+
+  return true;
 }
 
-uint32_t __analogReadMilliVolts(uint8_t pin){
-    int8_t channel = digitalPinToAnalogChannel(pin);
-    if(channel < 0){
-        log_e("Pin %u is not ADC pin!", pin);
-        return 0;
+bool analogContinuousRead(adc_continuous_data_t **buffer, uint32_t timeout_ms) {
+  if (adc_handle[ADC_UNIT_1].adc_continuous_handle != NULL) {
+    uint32_t bytes_read = 0;
+    uint32_t read_raw[used_adc_channels];
+    uint32_t read_count[used_adc_channels];
+    uint8_t adc_read[adc_handle[ADC_UNIT_1].conversion_frame_size];
+    memset(adc_read, 0xcc, sizeof(adc_read));
+    memset(read_raw, 0, sizeof(read_raw));
+    memset(read_count, 0, sizeof(read_count));
+
+    esp_err_t err = adc_continuous_read(adc_handle[ADC_UNIT_1].adc_continuous_handle, adc_read, adc_handle[0].conversion_frame_size, &bytes_read, timeout_ms);
+    if (err != ESP_OK) {
+      if (err == ESP_ERR_TIMEOUT) {
+        log_e("Reading data failed: No data, increase timeout");
+      } else {
+        log_e("Reading data failed with error: %X", err);
+      }
+      *buffer = NULL;
+      return false;
     }
-    if(!__analogVRef){
-        if (esp_adc_cal_check_efuse(ESP_ADC_CAL_VAL_EFUSE_TP) == ESP_OK) {
-            log_d("eFuse Two Point: Supported");
-            __analogVRef = DEFAULT_VREF;
-        }
-        if (esp_adc_cal_check_efuse(ESP_ADC_CAL_VAL_EFUSE_VREF) == ESP_OK) {
-            log_d("eFuse Vref: Supported");
-            __analogVRef = DEFAULT_VREF;
-        }
-        if(!__analogVRef){
-            __analogVRef = DEFAULT_VREF;
-            if(__analogVRefPin){
-                esp_adc_cal_characteristics_t chars;
-                if(adc2_vref_to_gpio(__analogVRefPin) == ESP_OK){
-                    __analogVRef = __analogRead(__analogVRefPin);
-                    esp_adc_cal_characterize(1, __analogAttenuation, __analogWidth, DEFAULT_VREF, &chars);
-                    __analogVRef = esp_adc_cal_raw_to_voltage(__analogVRef, &chars);
-                    log_d("Vref to GPIO%u: %u", __analogVRefPin, __analogVRef);
-                }
-            }
+
+    for (int i = 0; i < bytes_read; i += SOC_ADC_DIGI_RESULT_BYTES) {
+      adc_digi_output_data_t *p = (adc_digi_output_data_t *)&adc_read[i];
+      uint32_t chan_num = ADC_GET_CHANNEL(p);
+      uint32_t data = ADC_GET_DATA(p);
+
+      /* Check the channel number validation, the data is invalid if the channel num exceed the maximum channel */
+      if (chan_num >= SOC_ADC_CHANNEL_NUM(0)) {
+        log_e("Invalid data [%d_%d]", chan_num, data);
+        *buffer = NULL;
+        return false;
+      }
+      if (data >= (1 << SOC_ADC_DIGI_MAX_BITWIDTH)) {
+        data = 0;
+        log_e("Invalid data");
+      }
+
+      for (int j = 0; j < used_adc_channels; j++) {
+        if (adc_result[j].channel == chan_num) {
+          read_raw[j] += data;
+          read_count[j] += 1;
+          break;
         }
+      }
     }
-    uint8_t unit = 1;
-    if(channel > 9){
-        unit = 2;
+
+    for (int j = 0; j < used_adc_channels; j++) {
+      if (read_count[j] != 0) {
+        adc_result[j].avg_read_raw = read_raw[j] / read_count[j];
+        adc_cali_raw_to_voltage(adc_handle[ADC_UNIT_1].adc_cali_handle, adc_result[j].avg_read_raw, &adc_result[j].avg_read_mvolts);
+      } else {
+        log_w("No data read for pin %d", adc_result[j].pin);
+      }
     }
-    uint16_t adc_reading = __analogRead(pin);
-    if(__analogCharacteristics[unit - 1] == NULL){
-        __analogCharacteristics[unit - 1] = calloc(1, sizeof(esp_adc_cal_characteristics_t));
-        if(__analogCharacteristics[unit - 1] == NULL){
-            return 0;
-        }
-        esp_adc_cal_value_t val_type = esp_adc_cal_characterize(unit, __analogAttenuation, __analogWidth, __analogVRef, __analogCharacteristics[unit - 1]);
-        if (val_type == ESP_ADC_CAL_VAL_EFUSE_TP) {
-            log_i("ADC%u: Characterized using Two Point Value: %u\n", unit, __analogCharacteristics[unit - 1]->vref);
-        } else if (val_type == ESP_ADC_CAL_VAL_EFUSE_VREF) {
-            log_i("ADC%u: Characterized using eFuse Vref: %u\n", unit, __analogCharacteristics[unit - 1]->vref);
-        } else if(__analogVRef != DEFAULT_VREF){
-            log_i("ADC%u: Characterized using Vref to GPIO%u: %u\n", unit, __analogVRefPin, __analogCharacteristics[unit - 1]->vref);
-        } else {
-            log_i("ADC%u: Characterized using Default Vref: %u\n", unit, __analogCharacteristics[unit - 1]->vref);
-        }
+
+    *buffer = adc_result;
+    return true;
+
+  } else {
+    log_e("ADC Continuous is not initialized!");
+    return false;
+  }
+}
+
+bool analogContinuousStart() {
+  if (adc_handle[ADC_UNIT_1].adc_continuous_handle != NULL) {
+    if (adc_continuous_start(adc_handle[ADC_UNIT_1].adc_continuous_handle) == ESP_OK) {
+      return true;
+    }
+  } else {
+    log_e("ADC Continuous is not initialized!");
+  }
+  return false;
+}
+
+bool analogContinuousStop() {
+  if (adc_handle[ADC_UNIT_1].adc_continuous_handle != NULL) {
+    if (adc_continuous_stop(adc_handle[ADC_UNIT_1].adc_continuous_handle) == ESP_OK) {
+      return true;
+    }
+  } else {
+    log_e("ADC Continuous is not initialized!");
+  }
+  return false;
+}
+
+bool analogContinuousDeinit() {
+  if (adc_handle[ADC_UNIT_1].adc_continuous_handle != NULL) {
+    esp_err_t err = adc_continuous_deinit(adc_handle[ADC_UNIT_1].adc_continuous_handle);
+    if (err != ESP_OK) {
+      return false;
     }
-    return esp_adc_cal_raw_to_voltage(adc_reading, __analogCharacteristics[unit - 1]);
-}
-
-int __hallRead()    //hall sensor without LNA
-{
-    int Sens_Vp0;
-    int Sens_Vn0;
-    int Sens_Vp1;
-    int Sens_Vn1;
-
-    pinMode(36, ANALOG);
-    pinMode(39, ANALOG);
-    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_XPD_HALL_FORCE_M);     // hall sens force enable
-    SET_PERI_REG_MASK(RTC_IO_HALL_SENS_REG, RTC_IO_XPD_HALL);               // xpd hall
-    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_HALL_PHASE_FORCE_M);   // phase force
-    CLEAR_PERI_REG_MASK(RTC_IO_HALL_SENS_REG, RTC_IO_HALL_PHASE);           // hall phase
-    Sens_Vp0 = __analogRead(36);
-    Sens_Vn0 = __analogRead(39);
-    SET_PERI_REG_MASK(RTC_IO_HALL_SENS_REG, RTC_IO_HALL_PHASE);
-    Sens_Vp1 = __analogRead(36);
-    Sens_Vn1 = __analogRead(39);
-    SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
-    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_XPD_HALL_FORCE);
-    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_HALL_PHASE_FORCE);
-    return (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0);
-}
-
-extern uint16_t analogRead(uint8_t pin) __attribute__ ((weak, alias("__analogRead")));
-extern void analogReadResolution(uint8_t bits) __attribute__ ((weak, alias("__analogReadResolution")));
-extern void analogSetWidth(uint8_t bits) __attribute__ ((weak, alias("__analogSetWidth")));
-extern void analogSetClockDiv(uint8_t clockDiv) __attribute__ ((weak, alias("__analogSetClockDiv")));
-extern void analogSetAttenuation(adc_attenuation_t attenuation) __attribute__ ((weak, alias("__analogSetAttenuation")));
-extern void analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation) __attribute__ ((weak, alias("__analogSetPinAttenuation")));
-extern int hallRead() __attribute__ ((weak, alias("__hallRead")));
-
-extern bool adcAttachPin(uint8_t pin) __attribute__ ((weak, alias("__adcAttachPin")));
-
-extern void analogSetVRefPin(uint8_t pin) __attribute__ ((weak, alias("__analogSetVRefPin")));
-extern uint32_t analogReadMilliVolts(uint8_t pin) __attribute__ ((weak, alias("__analogReadMilliVolts")));
+    free(adc_result);
+    adc_handle[ADC_UNIT_1].adc_continuous_handle = NULL;
+  } else {
+    log_i("ADC Continuous was not initialized");
+  }
+  return true;
+}
+
+void analogContinuousSetAtten(adc_attenuation_t attenuation) {
+  __adcContinuousAtten = attenuation;
+}
+
+void analogContinuousSetWidth(uint8_t bits) {
+  if ((bits < SOC_ADC_DIGI_MIN_BITWIDTH) || (bits > SOC_ADC_DIGI_MAX_BITWIDTH)) {
+    log_e("Selected width cannot be set. Range is from %d to %d", SOC_ADC_DIGI_MIN_BITWIDTH, SOC_ADC_DIGI_MAX_BITWIDTH);
+    return;
+  }
+  __adcContinuousWidth = bits;
+}
+
+#endif
diff --git a/cores/esp32/esp32-hal-adc.h b/cores/esp32/esp32-hal-adc.h
index bba56fdcd4f..6ab5c920cfc 100644
--- a/cores/esp32/esp32-hal-adc.h
+++ b/cores/esp32/esp32-hal-adc.h
@@ -17,8 +17,10 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#ifndef MAIN_ESP32_HAL_ADC_H_
-#define MAIN_ESP32_HAL_ADC_H_
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_ADC_SUPPORTED
 
 #ifdef __cplusplus
 extern "C" {
@@ -27,10 +29,11 @@ extern "C" {
 #include "esp32-hal.h"
 
 typedef enum {
-    ADC_0db,
-    ADC_2_5db,
-    ADC_6db,
-    ADC_11db
+  ADC_0db,
+  ADC_2_5db,
+  ADC_6db,
+  ADC_11db,
+  ADC_ATTENDB_MAX
 } adc_attenuation_t;
 
 /*
@@ -38,6 +41,11 @@ typedef enum {
  * */
 uint16_t analogRead(uint8_t pin);
 
+/*
+ * Get MilliVolts value for pin
+ * */
+uint32_t analogReadMilliVolts(uint8_t pin);
+
 /*
  * Set the resolution of analogRead return values. Default is 12 bits (range from 0 to 4096).
  * If between 9 and 12, it will equal the set hardware resolution, else value will be shifted.
@@ -47,6 +55,19 @@ uint16_t analogRead(uint8_t pin);
  */
 void analogReadResolution(uint8_t bits);
 
+/*
+ * Set the attenuation for all channels
+ * Default is 11db
+ * */
+void analogSetAttenuation(adc_attenuation_t attenuation);
+
+/*
+ * Set the attenuation for particular pin
+ * Default is 11db
+ * */
+void analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation);
+
+#if CONFIG_IDF_TARGET_ESP32
 /*
  * Sets the sample bits and read resolution
  * Default is 12bit (0 - 4095)
@@ -54,48 +75,59 @@ void analogReadResolution(uint8_t bits);
  * */
 void analogSetWidth(uint8_t bits);
 
+#endif
+
 /*
- * Set the divider for the ADC clock.
- * Default is 1
- * Range is 1 - 255
+ * Analog Continuous mode
  * */
-void analogSetClockDiv(uint8_t clockDiv);
+
+typedef struct {
+  uint8_t pin;         /*!<ADC pin */
+  uint8_t channel;     /*!<ADC channel */
+  int avg_read_raw;    /*!<ADC average raw data */
+  int avg_read_mvolts; /*!<ADC average voltage in mV */
+} adc_continuous_data_t;
 
 /*
- * Set the attenuation for all channels
- * Default is 11db
+ * Setup ADC continuous peripheral
  * */
-void analogSetAttenuation(adc_attenuation_t attenuation);
+bool analogContinuous(const uint8_t pins[], size_t pins_count, uint32_t conversions_per_pin, uint32_t sampling_freq_hz, void (*userFunc)(void));
 
 /*
- * Set the attenuation for particular pin
- * Default is 11db
+ * Read ADC continuous conversion data
  * */
-void analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation);
+bool analogContinuousRead(adc_continuous_data_t **buffer, uint32_t timeout_ms);
 
 /*
- * Get value for HALL sensor (without LNA)
- * connected to pins 36(SVP) and 39(SVN)
+ * Start ADC continuous conversions
  * */
-int hallRead();
+bool analogContinuousStart();
 
 /*
- * Attach pin to ADC (will also clear any other analog mode that could be on)
+ * Stop ADC continuous conversions
  * */
-bool adcAttachPin(uint8_t pin);
+bool analogContinuousStop();
 
 /*
- * Set pin to use for ADC calibration if the esp is not already calibrated (25, 26 or 27)
+ * Deinitialize ADC continuous peripheral
  * */
-void analogSetVRefPin(uint8_t pin);
+bool analogContinuousDeinit();
 
 /*
- * Get MilliVolts value for pin
+ * Sets the attenuation for continuous mode reading
+ * Default is 11db
  * */
-uint32_t analogReadMilliVolts(uint8_t pin);
+void analogContinuousSetAtten(adc_attenuation_t attenuation);
+
+/*
+ * Sets the read resolution for continuous mode
+ * Default is 12bit (0 - 4095)
+ * Range is 9 - 12
+ * */
+void analogContinuousSetWidth(uint8_t bits);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* MAIN_ESP32_HAL_ADC_H_ */
+#endif /* SOC_ADC_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-bt.c b/cores/esp32/esp32-hal-bt.c
index 99762243469..1e5f73e324c 100644
--- a/cores/esp32/esp32-hal-bt.c
+++ b/cores/esp32/esp32-hal-bt.c
@@ -14,86 +14,121 @@
 
 #include "esp32-hal-bt.h"
 
-#ifdef CONFIG_BT_ENABLED
+#if SOC_BT_SUPPORTED
+#ifdef CONFIG_BT_BLUEDROID_ENABLED
 
-bool btInUse(){ return true; }
+#if CONFIG_IDF_TARGET_ESP32
+bool btInUse() {
+  return true;
+}
+#else
+// user may want to change it to free resources
+__attribute__((weak)) bool btInUse() {
+  return true;
+}
+#endif
 
-#ifdef CONFIG_BLUEDROID_ENABLED
 #include "esp_bt.h"
 
-#ifdef CONFIG_CLASSIC_BT_ENABLED
+#ifdef CONFIG_BTDM_CONTROLLER_MODE_BTDM
 #define BT_MODE ESP_BT_MODE_BTDM
+#elif defined(CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY)
+#define BT_MODE ESP_BT_MODE_CLASSIC_BT
 #else
 #define BT_MODE ESP_BT_MODE_BLE
 #endif
 
-bool btStarted(){
-    return (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED);
+bool btStarted() {
+  return (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED);
 }
 
-bool btStart(){
-    esp_bt_controller_config_t cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
-    if(esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED){
-        return true;
-    }
-    if(esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_IDLE){
-        esp_bt_controller_init(&cfg);
-        while(esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_IDLE){}
-    }
-    if(esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_INITED){
-        if (esp_bt_controller_enable(BT_MODE)) {
-            log_e("BT Enable failed");
-            return false;
-        }
+bool btStart() {
+  return btStartMode(BT_MODE);
+}
+
+bool btStartMode(bt_mode mode) {
+  esp_bt_mode_t esp_bt_mode;
+  esp_bt_controller_config_t cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
+#if CONFIG_IDF_TARGET_ESP32
+  switch (mode) {
+    case BT_MODE_BLE:        esp_bt_mode = ESP_BT_MODE_BLE; break;
+    case BT_MODE_CLASSIC_BT: esp_bt_mode = ESP_BT_MODE_CLASSIC_BT; break;
+    case BT_MODE_BTDM:       esp_bt_mode = ESP_BT_MODE_BTDM; break;
+    default:                 esp_bt_mode = BT_MODE; break;
+  }
+  // esp_bt_controller_enable(MODE) This mode must be equal as the mode in “cfg” of esp_bt_controller_init().
+  cfg.mode = esp_bt_mode;
+  if (cfg.mode == ESP_BT_MODE_CLASSIC_BT) {
+    esp_bt_controller_mem_release(ESP_BT_MODE_BLE);
+  }
+#else
+  // other esp variants dont support BT-classic / DM.
+  esp_bt_mode = BT_MODE;
+#endif
+
+  if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED) {
+    return true;
+  }
+  esp_err_t ret;
+  if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_IDLE) {
+    if ((ret = esp_bt_controller_init(&cfg)) != ESP_OK) {
+      log_e("initialize controller failed: %s", esp_err_to_name(ret));
+      return false;
     }
-    if(esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED){
-        return true;
+    while (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_IDLE) {}
+  }
+  if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_INITED) {
+    if ((ret = esp_bt_controller_enable(esp_bt_mode)) != ESP_OK) {
+      log_e("BT Enable mode=%d failed %s", BT_MODE, esp_err_to_name(ret));
+      return false;
     }
-    log_e("BT Start failed");
-    return false;
+  }
+  if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED) {
+    return true;
+  }
+  log_e("BT Start failed");
+  return false;
 }
 
-bool btStop(){
-    if(esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_IDLE){
-        return true;
+bool btStop() {
+  if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_IDLE) {
+    return true;
+  }
+  if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED) {
+    if (esp_bt_controller_disable()) {
+      log_e("BT Disable failed");
+      return false;
     }
-    if(esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED){
-        if (esp_bt_controller_disable()) {
-            log_e("BT Disable failed");
-            return false;
-        }
-        while(esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED);
+    while (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_ENABLED);
+  }
+  if (esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_INITED) {
+    if (esp_bt_controller_deinit()) {
+      log_e("BT deint failed");
+      return false;
     }
-    if(esp_bt_controller_get_status() == ESP_BT_CONTROLLER_STATUS_INITED){
-        if (esp_bt_controller_deinit()) {
-			log_e("BT deint failed");
-			return false;
-		}
-		vTaskDelay(1);
-		if (esp_bt_controller_get_status() != ESP_BT_CONTROLLER_STATUS_IDLE) {			
-			return false;		
-		}
-        return true;
+    vTaskDelay(1);
+    if (esp_bt_controller_get_status() != ESP_BT_CONTROLLER_STATUS_IDLE) {
+      return false;
     }
-    log_e("BT Stop failed");
-    return false;
+    return true;
+  }
+  log_e("BT Stop failed");
+  return false;
 }
 
-#else
-bool btStarted()
-{
-    return false;
+#else  // CONFIG_BT_ENABLED
+bool btStarted() {
+  return false;
 }
 
-bool btStart()
-{
-    return false;
+bool btStart() {
+  return false;
 }
 
-bool btStop()
-{
-    return false;
+bool btStop() {
+  return false;
 }
-#endif
-#endif
 
+#endif /* CONFIG_BT_ENABLED */
+
+#endif /* SOC_BT_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-bt.h b/cores/esp32/esp32-hal-bt.h
index 56222da3182..8ab03eea904 100644
--- a/cores/esp32/esp32-hal-bt.h
+++ b/cores/esp32/esp32-hal-bt.h
@@ -15,18 +15,31 @@
 #ifndef _ESP32_ESP32_HAL_BT_H_
 #define _ESP32_ESP32_HAL_BT_H_
 
+#include "soc/soc_caps.h"
+#if SOC_BT_SUPPORTED
+
 #include "esp32-hal.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+typedef enum {
+  BT_MODE_DEFAULT,
+  BT_MODE_BLE,
+  BT_MODE_CLASSIC_BT,
+  BT_MODE_BTDM
+} bt_mode;
+
 bool btStarted();
 bool btStart();
+bool btStartMode(bt_mode mode);
 bool btStop();
 
 #ifdef __cplusplus
 }
 #endif
 
+#endif /* SOC_BT_SUPPORTED */
+
 #endif /* _ESP32_ESP32_HAL_BT_H_ */
diff --git a/cores/esp32/esp32-hal-cpu.c b/cores/esp32/esp32-hal-cpu.c
index db002858827..1ffde860792 100644
--- a/cores/esp32/esp32-hal-cpu.c
+++ b/cores/esp32/esp32-hal-cpu.c
@@ -16,215 +16,276 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "freertos/task.h"
-#include "freertos/xtensa_timer.h"
 #include "esp_attr.h"
 #include "esp_log.h"
 #include "soc/rtc.h"
+#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4)
 #include "soc/rtc_cntl_reg.h"
-#include "rom/rtc.h"
-#include "soc/apb_ctrl_reg.h"
+#include "soc/syscon_reg.h"
+#endif
 #include "soc/efuse_reg.h"
 #include "esp32-hal.h"
 #include "esp32-hal-cpu.h"
 
+#include "esp_system.h"
+#ifdef ESP_IDF_VERSION_MAJOR  // IDF 4+
+#if CONFIG_IDF_TARGET_ESP32   // ESP32/PICO-D4
+#include "xtensa_timer.h"
+#include "esp32/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "xtensa_timer.h"
+#include "esp32s2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "xtensa_timer.h"
+#include "esp32s3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/rtc.h"
+#else
+#error Target CONFIG_IDF_TARGET is not supported
+#endif
+#else  // ESP32 Before IDF 4.0
+#include "rom/rtc.h"
+#endif
+
 typedef struct apb_change_cb_s {
-        struct apb_change_cb_s * prev;
-        struct apb_change_cb_s * next;
-        void * arg;
-        apb_change_cb_t cb;
+  struct apb_change_cb_s *prev;
+  struct apb_change_cb_s *next;
+  void *arg;
+  apb_change_cb_t cb;
 } apb_change_t;
 
-const uint32_t MHZ = 1000000;
+static apb_change_t *apb_change_callbacks = NULL;
+static SemaphoreHandle_t apb_change_lock = NULL;
 
-static apb_change_t * apb_change_callbacks = NULL;
-static xSemaphoreHandle apb_change_lock = NULL;
-
-static void initApbChangeCallback(){
-    static volatile bool initialized = false;
-    if(!initialized){
-        initialized = true;
-        apb_change_lock = xSemaphoreCreateMutex();
-        if(!apb_change_lock){
-            initialized = false;
-        }
+static void initApbChangeCallback() {
+  static volatile bool initialized = false;
+  if (!initialized) {
+    initialized = true;
+    apb_change_lock = xSemaphoreCreateMutex();
+    if (!apb_change_lock) {
+      initialized = false;
     }
+  }
 }
 
-static void triggerApbChangeCallback(apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb){
-    initApbChangeCallback();
-    xSemaphoreTake(apb_change_lock, portMAX_DELAY);
-    apb_change_t * r = apb_change_callbacks;
-    if( r != NULL ){
-        if(ev_type == APB_BEFORE_CHANGE )
-            while(r != NULL){
-                r->cb(r->arg, ev_type, old_apb, new_apb);
-                r=r->next;
-            }
-        else { // run backwards through chain
-            while(r->next != NULL) r = r->next; // find first added
-            while( r != NULL){
-                r->cb(r->arg, ev_type, old_apb, new_apb);
-                r=r->prev;
-            }
-        }
+static void triggerApbChangeCallback(apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb) {
+  initApbChangeCallback();
+  xSemaphoreTake(apb_change_lock, portMAX_DELAY);
+  apb_change_t *r = apb_change_callbacks;
+  if (r != NULL) {
+    if (ev_type == APB_BEFORE_CHANGE) {
+      while (r != NULL) {
+        r->cb(r->arg, ev_type, old_apb, new_apb);
+        r = r->next;
+      }
+    } else {  // run backwards through chain
+      while (r->next != NULL) {
+        r = r->next;  // find first added
+      }
+      while (r != NULL) {
+        r->cb(r->arg, ev_type, old_apb, new_apb);
+        r = r->prev;
+      }
     }
-    xSemaphoreGive(apb_change_lock);
+  }
+  xSemaphoreGive(apb_change_lock);
 }
 
-bool addApbChangeCallback(void * arg, apb_change_cb_t cb){
-    initApbChangeCallback();
-    apb_change_t * c = (apb_change_t*)malloc(sizeof(apb_change_t));
-    if(!c){
-        log_e("Callback Object Malloc Failed");
-        return false;
+bool addApbChangeCallback(void *arg, apb_change_cb_t cb) {
+  initApbChangeCallback();
+  apb_change_t *c = (apb_change_t *)malloc(sizeof(apb_change_t));
+  if (!c) {
+    log_e("Callback Object Malloc Failed");
+    return false;
+  }
+  c->next = NULL;
+  c->prev = NULL;
+  c->arg = arg;
+  c->cb = cb;
+  xSemaphoreTake(apb_change_lock, portMAX_DELAY);
+  if (apb_change_callbacks == NULL) {
+    apb_change_callbacks = c;
+  } else {
+    apb_change_t *r = apb_change_callbacks;
+    // look for duplicate callbacks
+    while ((r != NULL) && !((r->cb == cb) && (r->arg == arg))) {
+      r = r->next;
     }
-    c->next = NULL;
-    c->prev = NULL;
-    c->arg = arg;
-    c->cb = cb;
-    xSemaphoreTake(apb_change_lock, portMAX_DELAY);
-    if(apb_change_callbacks == NULL){
-        apb_change_callbacks = c;
+    if (r) {
+      log_e("duplicate func=%8p arg=%8p", c->cb, c->arg);
+      free(c);
+      xSemaphoreGive(apb_change_lock);
+      return false;
     } else {
-        apb_change_t * r = apb_change_callbacks;
-        // look for duplicate callbacks
-        while( (r != NULL ) && !((r->cb == cb) && ( r->arg == arg))) r = r->next;
-        if (r) {
-            log_e("duplicate func=%08X arg=%08X",c->cb,c->arg);
-            free(c);
-            xSemaphoreGive(apb_change_lock);
-            return false;
-        }
-        else {
-            c->next = apb_change_callbacks;
-            apb_change_callbacks-> prev = c;
-            apb_change_callbacks = c;
-        }
+      c->next = apb_change_callbacks;
+      apb_change_callbacks->prev = c;
+      apb_change_callbacks = c;
     }
-    xSemaphoreGive(apb_change_lock);
-    return true;
+  }
+  xSemaphoreGive(apb_change_lock);
+  return true;
 }
 
-bool removeApbChangeCallback(void * arg, apb_change_cb_t cb){
-    initApbChangeCallback();
-    xSemaphoreTake(apb_change_lock, portMAX_DELAY);
-    apb_change_t * r = apb_change_callbacks;
-    // look for matching callback
-    while( (r != NULL ) && !((r->cb == cb) && ( r->arg == arg))) r = r->next;
-    if ( r == NULL ) {
-        log_e("not found func=%08X arg=%08X",cb,arg);
-        xSemaphoreGive(apb_change_lock);
-        return false;
-        }
-    else {
-        // patch links
-        if(r->prev) r->prev->next = r->next;
-        else { // this is first link
-           apb_change_callbacks = r->next;
-        }
-        if(r->next) r->next->prev = r->prev;
-        free(r);
-    }
+bool removeApbChangeCallback(void *arg, apb_change_cb_t cb) {
+  initApbChangeCallback();
+  xSemaphoreTake(apb_change_lock, portMAX_DELAY);
+  apb_change_t *r = apb_change_callbacks;
+  // look for matching callback
+  while ((r != NULL) && !((r->cb == cb) && (r->arg == arg))) {
+    r = r->next;
+  }
+  if (r == NULL) {
+    log_e("not found func=%8p arg=%8p", cb, arg);
     xSemaphoreGive(apb_change_lock);
-    return true;
+    return false;
+  } else {
+    // patch links
+    if (r->prev) {
+      r->prev->next = r->next;
+    } else {  // this is first link
+      apb_change_callbacks = r->next;
+    }
+    if (r->next) {
+      r->next->prev = r->prev;
+    }
+    free(r);
+  }
+  xSemaphoreGive(apb_change_lock);
+  return true;
 }
 
-static uint32_t calculateApb(rtc_cpu_freq_config_t * conf){
-    if(conf->freq_mhz >= 80){
-        return 80 * MHZ;
-    }
-    return (conf->source_freq_mhz * MHZ) / conf->div;
+static uint32_t calculateApb(rtc_cpu_freq_config_t *conf) {
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+  if (conf->freq_mhz >= 80) {
+    return 80 * MHZ;
+  }
+  return (conf->source_freq_mhz * MHZ) / conf->div;
+#else
+  return APB_CLK_FREQ;
+#endif
 }
 
-void esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us); //private in IDF
-
-bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz){
-    rtc_cpu_freq_config_t conf, cconf;
-    uint32_t capb, apb;
-    //Get XTAL Frequency and calculate min CPU MHz
-    rtc_xtal_freq_t xtal = rtc_clk_xtal_freq_get();
-    if(xtal > RTC_XTAL_FREQ_AUTO){
-        if(xtal < RTC_XTAL_FREQ_40M) {
-            if(cpu_freq_mhz <= xtal && cpu_freq_mhz != xtal && cpu_freq_mhz != (xtal/2)){
-                log_e("Bad frequency: %u MHz! Options are: 240, 160, 80, %u and %u MHz", cpu_freq_mhz, xtal, xtal/2);
-                return false;
-            }
-        } else if(cpu_freq_mhz <= xtal && cpu_freq_mhz != xtal && cpu_freq_mhz != (xtal/2) && cpu_freq_mhz != (xtal/4)){
-            log_e("Bad frequency: %u MHz! Options are: 240, 160, 80, %u, %u and %u MHz", cpu_freq_mhz, xtal, xtal/2, xtal/4);
-            return false;
-        }
-    }
-    if(cpu_freq_mhz > xtal && cpu_freq_mhz != 240 && cpu_freq_mhz != 160 && cpu_freq_mhz != 80){
-        if(xtal >= RTC_XTAL_FREQ_40M){
-            log_e("Bad frequency: %u MHz! Options are: 240, 160, 80, %u, %u and %u MHz", cpu_freq_mhz, xtal, xtal/2, xtal/4);
-        } else {
-            log_e("Bad frequency: %u MHz! Options are: 240, 160, 80, %u and %u MHz", cpu_freq_mhz, xtal, xtal/2);
-        }
-        return false;
-    }
-    //check if cpu supports the frequency
-    if(cpu_freq_mhz == 240){
-        //Check if ESP32 is rated for a CPU frequency of 160MHz only
-        if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) &&
-            REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
-            log_e("Can not switch to 240 MHz! Chip CPU frequency rated for 160MHz.");
-            cpu_freq_mhz = 160;
-        }
-    }
-    //Get current CPU clock configuration
-    rtc_clk_cpu_freq_get_config(&cconf);
-    //return if frequency has not changed
-    if(cconf.freq_mhz == cpu_freq_mhz){
-        return true;
-    }
-    //Get configuration for the new CPU frequency
-    if(!rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &conf)){
-        log_e("CPU clock could not be set to %u MHz", cpu_freq_mhz);
+void esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us);  //private in IDF
+
+bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
+  rtc_cpu_freq_config_t conf, cconf;
+  uint32_t capb, apb;
+  //Get XTAL Frequency and calculate min CPU MHz
+#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))
+  rtc_xtal_freq_t xtal = rtc_clk_xtal_freq_get();
+#endif
+#if CONFIG_IDF_TARGET_ESP32
+  if (xtal > RTC_XTAL_FREQ_AUTO) {
+    if (xtal < RTC_XTAL_FREQ_40M) {
+      if (cpu_freq_mhz <= xtal && cpu_freq_mhz != xtal && cpu_freq_mhz != (xtal / 2)) {
+        log_e("Bad frequency: %u MHz! Options are: 240, 160, 80, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2);
         return false;
+      }
+    } else if (cpu_freq_mhz <= xtal && cpu_freq_mhz != xtal && cpu_freq_mhz != (xtal / 2) && cpu_freq_mhz != (xtal / 4)) {
+      log_e("Bad frequency: %u MHz! Options are: 240, 160, 80, %u, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2, xtal / 4);
+      return false;
     }
-    //Current APB
-    capb = calculateApb(&cconf);
-    //New APB
-    apb = calculateApb(&conf);
-    log_d("%s: %u / %u = %u Mhz, APB: %u Hz", (conf.source == RTC_CPU_FREQ_SRC_PLL)?"PLL":((conf.source == RTC_CPU_FREQ_SRC_APLL)?"APLL":((conf.source == RTC_CPU_FREQ_SRC_XTAL)?"XTAL":"8M")), conf.source_freq_mhz, conf.div, conf.freq_mhz, apb);
-    //Call peripheral functions before the APB change
-    if(apb_change_callbacks){
-        triggerApbChangeCallback(APB_BEFORE_CHANGE, capb, apb);
-    }
-    //Make the frequency change
-    rtc_clk_cpu_freq_set_config_fast(&conf);
-    if(capb != apb){
-        //Update REF_TICK (uncomment if REF_TICK is different than 1MHz)
-        //if(conf.freq_mhz < 80){
-        //    ESP_REG(APB_CTRL_XTAL_TICK_CONF_REG) = conf.freq_mhz / (REF_CLK_FREQ / MHZ) - 1;
-        // }
-        //Update APB Freq REG
-        rtc_clk_apb_freq_update(apb);
-        //Update esp_timer divisor
-        esp_timer_impl_update_apb_freq(apb / MHZ);
+  }
+#endif
+#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))
+  if (cpu_freq_mhz > xtal && cpu_freq_mhz != 240 && cpu_freq_mhz != 160 && cpu_freq_mhz != 120 && cpu_freq_mhz != 80) {
+    if (xtal >= RTC_XTAL_FREQ_40M) {
+      log_e("Bad frequency: %u MHz! Options are: 240, 160, 120, 80, %u, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2, xtal / 4);
+    } else {
+      log_e("Bad frequency: %u MHz! Options are: 240, 160, 120, 80, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2);
     }
-    //Update FreeRTOS Tick Divisor
-    uint32_t fcpu = (conf.freq_mhz >= 80)?(conf.freq_mhz * MHZ):(apb);
-    _xt_tick_divisor = fcpu / XT_TICK_PER_SEC;
-    //Call peripheral functions after the APB change
-    if(apb_change_callbacks){
-        triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb);
+    return false;
+  }
+#endif
+#if CONFIG_IDF_TARGET_ESP32
+  //check if cpu supports the frequency
+  if (cpu_freq_mhz == 240) {
+    //Check if ESP32 is rated for a CPU frequency of 160MHz only
+    if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) && REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
+      log_e("Can not switch to 240 MHz! Chip CPU frequency rated for 160MHz.");
+      cpu_freq_mhz = 160;
     }
+  }
+#endif
+  //Get current CPU clock configuration
+  rtc_clk_cpu_freq_get_config(&cconf);
+  //return if frequency has not changed
+  if (cconf.freq_mhz == cpu_freq_mhz) {
     return true;
+  }
+  //Get configuration for the new CPU frequency
+  if (!rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &conf)) {
+    log_e("CPU clock could not be set to %u MHz", cpu_freq_mhz);
+    return false;
+  }
+  //Current APB
+  capb = calculateApb(&cconf);
+  //New APB
+  apb = calculateApb(&conf);
+
+  //Call peripheral functions before the APB change
+  if (apb_change_callbacks) {
+    triggerApbChangeCallback(APB_BEFORE_CHANGE, capb, apb);
+  }
+  //Make the frequency change
+  rtc_clk_cpu_freq_set_config_fast(&conf);
+#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C3)
+  if (capb != apb) {
+    //Update REF_TICK (uncomment if REF_TICK is different than 1MHz)
+    //if(conf.freq_mhz < 80){
+    //    ESP_REG(APB_CTRL_XTAL_TICK_CONF_REG) = conf.freq_mhz / (REF_CLK_FREQ / MHZ) - 1;
+    // }
+    //Update APB Freq REG
+    rtc_clk_apb_freq_update(apb);
+    //Update esp_timer divisor
+    esp_timer_impl_update_apb_freq(apb / MHZ);
+  }
+#endif
+  //Update FreeRTOS Tick Divisor
+
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+  uint32_t fcpu = (conf.freq_mhz >= 80) ? (conf.freq_mhz * MHZ) : (apb);
+  _xt_tick_divisor = fcpu / XT_TICK_PER_SEC;
+#endif
+  //Call peripheral functions after the APB change
+  if (apb_change_callbacks) {
+    triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb);
+  }
+#if defined(SOC_CLK_APLL_SUPPORTED) && !defined(CONFIG_IDF_TARGET_ESP32P4)  // APLL not yet supported in ESP32-P4
+  log_d(
+    "%s: %u / %u = %u Mhz, APB: %u Hz",
+    (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M")),
+    conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
+  );
+#else
+  log_d(
+    "%s: %u / %u = %u Mhz, APB: %u Hz", (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "17.5M"),
+    conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
+  );
+#endif
+  return true;
 }
 
-uint32_t getCpuFrequencyMhz(){
-    rtc_cpu_freq_config_t conf;
-    rtc_clk_cpu_freq_get_config(&conf);
-    return conf.freq_mhz;
+uint32_t getCpuFrequencyMhz() {
+  rtc_cpu_freq_config_t conf;
+  rtc_clk_cpu_freq_get_config(&conf);
+  return conf.freq_mhz;
 }
 
-uint32_t getXtalFrequencyMhz(){
-    return rtc_clk_xtal_freq_get();
+uint32_t getXtalFrequencyMhz() {
+  return rtc_clk_xtal_freq_get();
 }
 
-uint32_t getApbFrequency(){
-    rtc_cpu_freq_config_t conf;
-    rtc_clk_cpu_freq_get_config(&conf);
-    return calculateApb(&conf);
+uint32_t getApbFrequency() {
+  rtc_cpu_freq_config_t conf;
+  rtc_clk_cpu_freq_get_config(&conf);
+  return calculateApb(&conf);
 }
diff --git a/cores/esp32/esp32-hal-cpu.h b/cores/esp32/esp32-hal-cpu.h
index 646b59858f5..59806b460ae 100644
--- a/cores/esp32/esp32-hal-cpu.h
+++ b/cores/esp32/esp32-hal-cpu.h
@@ -23,12 +23,15 @@ extern "C" {
 #include <stdbool.h>
 #include <stdlib.h>
 
-typedef enum { APB_BEFORE_CHANGE, APB_AFTER_CHANGE } apb_change_ev_t;
+typedef enum {
+  APB_BEFORE_CHANGE,
+  APB_AFTER_CHANGE
+} apb_change_ev_t;
 
-typedef void (* apb_change_cb_t)(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb);
+typedef void (*apb_change_cb_t)(void *arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb);
 
-bool addApbChangeCallback(void * arg, apb_change_cb_t cb);
-bool removeApbChangeCallback(void * arg, apb_change_cb_t cb);
+bool addApbChangeCallback(void *arg, apb_change_cb_t cb);
+bool removeApbChangeCallback(void *arg, apb_change_cb_t cb);
 
 //function takes the following frequencies as valid values:
 //  240, 160, 80    <<< For all XTAL types
@@ -37,9 +40,9 @@ bool removeApbChangeCallback(void * arg, apb_change_cb_t cb);
 //  24, 12          <<< For 24MHz XTAL
 bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz);
 
-uint32_t getCpuFrequencyMhz();  // In MHz
-uint32_t getXtalFrequencyMhz(); // In MHz
-uint32_t getApbFrequency();     // In Hz
+uint32_t getCpuFrequencyMhz();   // In MHz
+uint32_t getXtalFrequencyMhz();  // In MHz
+uint32_t getApbFrequency();      // In Hz
 
 #ifdef __cplusplus
 }
diff --git a/cores/esp32/esp32-hal-dac.c b/cores/esp32/esp32-hal-dac.c
index e407c221116..267f9cd461e 100644
--- a/cores/esp32/esp32-hal-dac.c
+++ b/cores/esp32/esp32-hal-dac.c
@@ -1,54 +1,76 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "esp32-hal-dac.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "rom/ets_sys.h"
-#include "esp_attr.h"
-#include "esp_intr.h"
-#include "soc/rtc_io_reg.h"
-#include "soc/rtc_cntl_reg.h"
-#include "soc/sens_reg.h"
-
-void IRAM_ATTR __dacWrite(uint8_t pin, uint8_t value)
-{
-    if(pin < 25 || pin > 26){
-        return;//not dac pin
+
+#if SOC_DAC_SUPPORTED
+#include "esp32-hal.h"
+#include "esp32-hal-periman.h"
+#include "soc/dac_channel.h"
+#include "driver/dac_oneshot.h"
+
+static bool dacDetachBus(void *bus) {
+  esp_err_t err = dac_oneshot_del_channel((dac_oneshot_handle_t)bus);
+  if (err != ESP_OK) {
+    log_e("dac_oneshot_del_channel failed with error: %d", err);
+    return false;
+  }
+  return true;
+}
+
+bool __dacWrite(uint8_t pin, uint8_t value) {
+  esp_err_t err = ESP_OK;
+  if (pin != DAC_CHAN0_GPIO_NUM && pin != DAC_CHAN1_GPIO_NUM) {
+    log_e("pin %u is not a DAC pin", pin);
+    return false;  //not dac pin
+  }
+
+  dac_oneshot_handle_t bus = (dac_oneshot_handle_t)perimanGetPinBus(pin, ESP32_BUS_TYPE_DAC_ONESHOT);
+  if (bus == NULL) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_DAC_ONESHOT, dacDetachBus);
+    if (!perimanClearPinBus(pin)) {
+      return false;
     }
-    pinMode(pin, ANALOG);
-    uint8_t channel = pin - 25;
-
-
-    //Disable Tone
-    CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL1_REG, SENS_SW_TONE_EN);
-
-    if (channel) {
-        //Disable Channel Tone
-        CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN2_M);
-        //Set the Dac value
-        SET_PERI_REG_BITS(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_DAC, value, RTC_IO_PDAC2_DAC_S);   //dac_output
-        //Channel output enable
-        SET_PERI_REG_MASK(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_XPD_DAC | RTC_IO_PDAC2_DAC_XPD_FORCE);
-    } else {
-        //Disable Channel Tone
-        CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN1_M);
-        //Set the Dac value
-        SET_PERI_REG_BITS(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC, value, RTC_IO_PDAC1_DAC_S);   //dac_output
-        //Channel output enable
-        SET_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC | RTC_IO_PDAC1_DAC_XPD_FORCE);
+    dac_channel_t channel = (pin == DAC_CHAN0_GPIO_NUM) ? DAC_CHAN_0 : DAC_CHAN_1;
+    dac_oneshot_config_t config = {.chan_id = channel};
+    err = dac_oneshot_new_channel(&config, &bus);
+    if (err != ESP_OK) {
+      log_e("dac_oneshot_new_channel failed with error: %d", err);
+      return false;
     }
+    if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_DAC_ONESHOT, (void *)bus, -1, channel)) {
+      dacDetachBus((void *)bus);
+      return false;
+    }
+  }
+
+  err = dac_oneshot_output_voltage(bus, value);
+  if (err != ESP_OK) {
+    log_e("dac_oneshot_output_voltage failed with error: %d", err);
+    return false;
+  }
+  return true;
 }
 
-extern void dacWrite(uint8_t pin, uint8_t value) __attribute__ ((weak, alias("__dacWrite")));
+bool __dacDisable(uint8_t pin) {
+  if (pin != DAC_CHAN0_GPIO_NUM && pin != DAC_CHAN1_GPIO_NUM) {
+    log_e("pin %u is not a DAC pin", pin);
+    return false;  //not dac pin
+  }
+  void *bus = perimanGetPinBus(pin, ESP32_BUS_TYPE_DAC_ONESHOT);
+  if (bus != NULL) {
+    // will call dacDetachBus
+    return perimanClearPinBus(pin);
+  } else {
+    log_e("pin %u is not attached to DAC", pin);
+  }
+  return false;
+}
+
+extern bool dacWrite(uint8_t pin, uint8_t value) __attribute__((weak, alias("__dacWrite")));
+extern bool dacDisable(uint8_t pin) __attribute__((weak, alias("__dacDisable")));
+
+#endif
diff --git a/cores/esp32/esp32-hal-dac.h b/cores/esp32/esp32-hal-dac.h
index 47b2265800f..113354ba830 100644
--- a/cores/esp32/esp32-hal-dac.h
+++ b/cores/esp32/esp32-hal-dac.h
@@ -1,36 +1,26 @@
 /*
- Arduino.h - Main include file for the Arduino SDK
- Copyright (c) 2005-2013 Arduino Team.  All right reserved.
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef MAIN_ESP32_HAL_DAC_H_
-#define MAIN_ESP32_HAL_DAC_H_
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_DAC_SUPPORTED
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "esp32-hal.h"
-#include "driver/gpio.h"
+#include <stdint.h>
+#include <stdbool.h>
 
-void dacWrite(uint8_t pin, uint8_t value);
+bool dacWrite(uint8_t pin, uint8_t value);
+bool dacDisable(uint8_t pin);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* MAIN_ESP32_HAL_DAC_H_ */
+#endif /* SOC_DAC_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-gpio.c b/cores/esp32/esp32-hal-gpio.c
index 4da7272c597..90ad1e7f36d 100644
--- a/cores/esp32/esp32-hal-gpio.c
+++ b/cores/esp32/esp32-hal-gpio.c
@@ -13,292 +13,267 @@
 // limitations under the License.
 
 #include "esp32-hal-gpio.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "rom/ets_sys.h"
-#include "esp_attr.h"
-#include "esp_intr.h"
-#include "rom/gpio.h"
-#include "soc/gpio_reg.h"
-#include "soc/io_mux_reg.h"
-#include "soc/gpio_struct.h"
-#include "soc/rtc_io_reg.h"
-
-const int8_t esp32_adc2gpio[20] = {36, 37, 38, 39, 32, 33, 34, 35, -1, -1, 4, 0, 2, 15, 13, 12, 14, 27, 25, 26};
-
-const DRAM_ATTR esp32_gpioMux_t esp32_gpioMux[GPIO_PIN_COUNT]={
-    {0x44, 11, 11, 1},
-    {0x88, -1, -1, -1},
-    {0x40, 12, 12, 2},
-    {0x84, -1, -1, -1},
-    {0x48, 10, 10, 0},
-    {0x6c, -1, -1, -1},
-    {0x60, -1, -1, -1},
-    {0x64, -1, -1, -1},
-    {0x68, -1, -1, -1},
-    {0x54, -1, -1, -1},
-    {0x58, -1, -1, -1},
-    {0x5c, -1, -1, -1},
-    {0x34, 15, 15, 5},
-    {0x38, 14, 14, 4},
-    {0x30, 16, 16, 6},
-    {0x3c, 13, 13, 3},
-    {0x4c, -1, -1, -1},
-    {0x50, -1, -1, -1},
-    {0x70, -1, -1, -1},
-    {0x74, -1, -1, -1},
-    {0x78, -1, -1, -1},
-    {0x7c, -1, -1, -1},
-    {0x80, -1, -1, -1},
-    {0x8c, -1, -1, -1},
-    {0, -1, -1, -1},
-    {0x24, 6, 18, -1}, //DAC1
-    {0x28, 7, 19, -1}, //DAC2
-    {0x2c, 17, 17, 7},
-    {0, -1, -1, -1},
-    {0, -1, -1, -1},
-    {0, -1, -1, -1},
-    {0, -1, -1, -1},
-    {0x1c, 9, 4, 8},
-    {0x20, 8, 5, 9},
-    {0x14, 4, 6, -1},
-    {0x18, 5, 7, -1},
-    {0x04, 0, 0, -1},
-    {0x08, 1, 1, -1},
-    {0x0c, 2, 2, -1},
-    {0x10, 3, 3, -1}
-};
+#include "esp32-hal-periman.h"
+#include "hal/gpio_hal.h"
+#include "soc/soc_caps.h"
+
+// RGB_BUILTIN is defined in pins_arduino.h
+// If RGB_BUILTIN is defined, it will be used as a pin number for the RGB LED
+// If RGB_BUILTIN has a side effect that prevents using RMT Legacy driver in IDF 5.1
+// Define ESP32_ARDUINO_NO_RGB_BUILTIN in build_opt.h or through CLI to disable RGB_BUILTIN
+#ifdef ESP32_ARDUINO_NO_RGB_BUILTIN
+#ifdef RGB_BUILTIN
+#undef RGB_BUILTIN
+#endif
+#endif
+
+// It fixes lack of pin definition for S3 and for any future SoC
+// this function works for ESP32, ESP32-S2 and ESP32-S3 - including the C3, it will return -1 for any pin
+#if SOC_TOUCH_SENSOR_NUM > 0
+#include "soc/touch_sensor_periph.h"
+
+int8_t digitalPinToTouchChannel(uint8_t pin) {
+  int8_t ret = -1;
+  if (pin < SOC_GPIO_PIN_COUNT) {
+    for (uint8_t i = 0; i < SOC_TOUCH_SENSOR_NUM; i++) {
+      if (touch_sensor_channel_io_map[i] == pin) {
+        ret = i;
+        break;
+      }
+    }
+  }
+  return ret;
+}
+#else
+// No Touch Sensor available
+int8_t digitalPinToTouchChannel(uint8_t pin) {
+  return -1;
+}
+#endif
+
+#ifdef SOC_ADC_SUPPORTED
+#include "soc/adc_periph.h"
+
+int8_t digitalPinToAnalogChannel(uint8_t pin) {
+  uint8_t channel = 0;
+  if (pin < SOC_GPIO_PIN_COUNT) {
+    for (uint8_t i = 0; i < SOC_ADC_PERIPH_NUM; i++) {
+      for (uint8_t j = 0; j < SOC_ADC_MAX_CHANNEL_NUM; j++) {
+        if (adc_channel_io_map[i][j] == pin) {
+          return channel;
+        }
+        channel++;
+      }
+    }
+  }
+  return -1;
+}
+
+int8_t analogChannelToDigitalPin(uint8_t channel) {
+  if (channel >= (SOC_ADC_PERIPH_NUM * SOC_ADC_MAX_CHANNEL_NUM)) {
+    return -1;
+  }
+  uint8_t adc_unit = (channel / SOC_ADC_MAX_CHANNEL_NUM);
+  uint8_t adc_chan = (channel % SOC_ADC_MAX_CHANNEL_NUM);
+  return adc_channel_io_map[adc_unit][adc_chan];
+}
+#else
+// No Analog channels available
+int8_t analogChannelToDigitalPin(uint8_t channel) {
+  return -1;
+}
+#endif
 
 typedef void (*voidFuncPtr)(void);
-typedef void (*voidFuncPtrArg)(void*);
+typedef void (*voidFuncPtrArg)(void *);
 typedef struct {
-    voidFuncPtr fn;
-    void* arg;
-    bool functional;
+  voidFuncPtr fn;
+  void *arg;
+  bool functional;
 } InterruptHandle_t;
-static InterruptHandle_t __pinInterruptHandlers[GPIO_PIN_COUNT] = {0,};
+static InterruptHandle_t __pinInterruptHandlers[SOC_GPIO_PIN_COUNT] = {
+  0,
+};
 
 #include "driver/rtc_io.h"
 
-extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode)
-{
+static bool gpioDetachBus(void *bus) {
+  return true;
+}
 
-    if(!digitalPinIsValid(pin)) {
-        return;
+extern void ARDUINO_ISR_ATTR __pinMode(uint8_t pin, uint8_t mode) {
+#ifdef RGB_BUILTIN
+  if (pin == RGB_BUILTIN) {
+    __pinMode(RGB_BUILTIN - SOC_GPIO_PIN_COUNT, mode);
+    return;
+  }
+#endif
+
+  if (pin >= SOC_GPIO_PIN_COUNT) {
+    log_e("Invalid IO %i selected", pin);
+    return;
+  }
+
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_GPIO) == NULL) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_GPIO, gpioDetachBus);
+    if (!perimanClearPinBus(pin)) {
+      log_e("Deinit of previous bus from IO %i failed", pin);
+      return;
     }
-
-    uint32_t rtc_reg = rtc_gpio_desc[pin].reg;
-    if(mode == ANALOG) {
-        if(!rtc_reg) {
-            return;//not rtc pin
-        }
-        //lock rtc
-        uint32_t reg_val = ESP_REG(rtc_reg);
-        if(reg_val & rtc_gpio_desc[pin].mux){
-            return;//already in adc mode
-        }
-        reg_val &= ~(
-                (RTC_IO_TOUCH_PAD1_FUN_SEL_V << rtc_gpio_desc[pin].func)
-                |rtc_gpio_desc[pin].ie
-                |rtc_gpio_desc[pin].pullup
-                |rtc_gpio_desc[pin].pulldown);
-        ESP_REG(RTC_GPIO_ENABLE_W1TC_REG) = (1 << (rtc_gpio_desc[pin].rtc_num + RTC_GPIO_ENABLE_W1TC_S));
-        ESP_REG(rtc_reg) = reg_val | rtc_gpio_desc[pin].mux;
-        //unlock rtc
-        ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = ((uint32_t)2 << MCU_SEL_S) | ((uint32_t)2 << FUN_DRV_S) | FUN_IE;
-        return;
+  }
+
+  gpio_hal_context_t gpiohal;
+  gpiohal.dev = GPIO_LL_GET_HW(GPIO_PORT_0);
+
+  gpio_config_t conf = {
+    .pin_bit_mask = (1ULL << pin),              /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */
+    .mode = GPIO_MODE_DISABLE,                  /*!< GPIO mode: set input/output mode                     */
+    .pull_up_en = GPIO_PULLUP_DISABLE,          /*!< GPIO pull-up                                         */
+    .pull_down_en = GPIO_PULLDOWN_DISABLE,      /*!< GPIO pull-down                                       */
+    .intr_type = gpiohal.dev->pin[pin].int_type /*!< GPIO interrupt type - previously set                 */
+  };
+  if (mode < 0x20) {  //io
+    conf.mode = mode & (INPUT | OUTPUT);
+    if (mode & OPEN_DRAIN) {
+      conf.mode |= GPIO_MODE_DEF_OD;
     }
-
-    //RTC pins PULL settings
-    if(rtc_reg) {
-        //lock rtc
-        ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].mux);
-        if(mode & PULLUP) {
-            ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pullup) & ~(rtc_gpio_desc[pin].pulldown);
-        } else if(mode & PULLDOWN) {
-            ESP_REG(rtc_reg) = (ESP_REG(rtc_reg) | rtc_gpio_desc[pin].pulldown) & ~(rtc_gpio_desc[pin].pullup);
-        } else {
-            ESP_REG(rtc_reg) = ESP_REG(rtc_reg) & ~(rtc_gpio_desc[pin].pullup | rtc_gpio_desc[pin].pulldown);
-        }
-        //unlock rtc
+    if (mode & PULLUP) {
+      conf.pull_up_en = GPIO_PULLUP_ENABLE;
     }
-
-    uint32_t pinFunction = 0, pinControl = 0;
-
-    //lock gpio
-    if(mode & INPUT) {
-        if(pin < 32) {
-            GPIO.enable_w1tc = ((uint32_t)1 << pin);
-        } else {
-            GPIO.enable1_w1tc.val = ((uint32_t)1 << (pin - 32));
-        }
-    } else if(mode & OUTPUT) {
-        if(pin > 33){
-            //unlock gpio
-            return;//pins above 33 can be only inputs
-        } else if(pin < 32) {
-            GPIO.enable_w1ts = ((uint32_t)1 << pin);
-        } else {
-            GPIO.enable1_w1ts.val = ((uint32_t)1 << (pin - 32));
-        }
+    if (mode & PULLDOWN) {
+      conf.pull_down_en = GPIO_PULLDOWN_ENABLE;
     }
-
-    if(mode & PULLUP) {
-        pinFunction |= FUN_PU;
-    } else if(mode & PULLDOWN) {
-        pinFunction |= FUN_PD;
+  }
+  if (gpio_config(&conf) != ESP_OK) {
+    log_e("IO %i config failed", pin);
+    return;
+  }
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_GPIO) == NULL) {
+    if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_GPIO, (void *)(pin + 1), -1, -1)) {
+      //gpioDetachBus((void *)(pin+1));
+      return;
     }
-
-    pinFunction |= ((uint32_t)2 << FUN_DRV_S);//what are the drivers?
-    pinFunction |= FUN_IE;//input enable but required for output as well?
-
-    if(mode & (INPUT | OUTPUT)) {
-        pinFunction |= ((uint32_t)2 << MCU_SEL_S);
-    } else if(mode == SPECIAL) {
-        pinFunction |= ((uint32_t)(((pin)==1||(pin)==3)?0:1) << MCU_SEL_S);
-    } else {
-        pinFunction |= ((uint32_t)(mode >> 5) << MCU_SEL_S);
-    }
-
-    ESP_REG(DR_REG_IO_MUX_BASE + esp32_gpioMux[pin].reg) = pinFunction;
-
-    if(mode & OPEN_DRAIN) {
-        pinControl = (1 << GPIO_PIN0_PAD_DRIVER_S);
-    }
-
-    GPIO.pin[pin].val = pinControl;
-    //unlock gpio
+  }
 }
 
-extern void IRAM_ATTR __digitalWrite(uint8_t pin, uint8_t val)
-{
-    if(val) {
-        if(pin < 32) {
-            GPIO.out_w1ts = ((uint32_t)1 << pin);
-        } else if(pin < 34) {
-            GPIO.out1_w1ts.val = ((uint32_t)1 << (pin - 32));
-        }
-    } else {
-        if(pin < 32) {
-            GPIO.out_w1tc = ((uint32_t)1 << pin);
-        } else if(pin < 34) {
-            GPIO.out1_w1tc.val = ((uint32_t)1 << (pin - 32));
-        }
-    }
+#ifdef RGB_BUILTIN
+uint8_t RGB_BUILTIN_storage = 0;
+#endif
+
+extern void ARDUINO_ISR_ATTR __digitalWrite(uint8_t pin, uint8_t val) {
+#ifdef RGB_BUILTIN
+  if (pin == RGB_BUILTIN) {
+    //use RMT to set all channels on/off
+    RGB_BUILTIN_storage = val;
+    const uint8_t comm_val = val != 0 ? RGB_BRIGHTNESS : 0;
+    rgbLedWrite(RGB_BUILTIN, comm_val, comm_val, comm_val);
+    return;
+  }
+#endif  // RGB_BUILTIN
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_GPIO) != NULL) {
+    gpio_set_level((gpio_num_t)pin, val);
+  } else {
+    log_e("IO %i is not set as GPIO. Execute digitalMode(%i, OUTPUT) first.", pin, pin);
+  }
 }
 
-extern int IRAM_ATTR __digitalRead(uint8_t pin)
-{
-    if(pin < 32) {
-        return (GPIO.in >> pin) & 0x1;
-    } else if(pin < 40) {
-        return (GPIO.in1.val >> (pin - 32)) & 0x1;
-    }
-    return 0;
+extern int ARDUINO_ISR_ATTR __digitalRead(uint8_t pin) {
+#ifdef RGB_BUILTIN
+  if (pin == RGB_BUILTIN) {
+    return RGB_BUILTIN_storage;
+  }
+#endif  // RGB_BUILTIN
+  // This work when the pin is set as GPIO and in INPUT mode. For all other pin functions, it may return inconsistent response
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_GPIO) == NULL) {
+    log_w("IO %i is not set as GPIO. digitalRead() may return an inconsistent value.", pin);
+  }
+  return gpio_get_level((gpio_num_t)pin);
 }
 
-static intr_handle_t gpio_intr_handle = NULL;
-
-static void IRAM_ATTR __onPinInterrupt()
-{
-    uint32_t gpio_intr_status_l=0;
-    uint32_t gpio_intr_status_h=0;
-
-    gpio_intr_status_l = GPIO.status;
-    gpio_intr_status_h = GPIO.status1.val;
-    GPIO.status_w1tc = gpio_intr_status_l;//Clear intr for gpio0-gpio31
-    GPIO.status1_w1tc.val = gpio_intr_status_h;//Clear intr for gpio32-39
-
-    uint8_t pin=0;
-    if(gpio_intr_status_l) {
-        do {
-            if(gpio_intr_status_l & ((uint32_t)1 << pin)) {
-                if(__pinInterruptHandlers[pin].fn) {
-                    if(__pinInterruptHandlers[pin].arg){
-                        ((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg);
-                    } else {
-                        __pinInterruptHandlers[pin].fn();
-                    }
-                }
-            }
-        } while(++pin<32);
-    }
-    if(gpio_intr_status_h) {
-        pin=32;
-        do {
-            if(gpio_intr_status_h & ((uint32_t)1 << (pin - 32))) {
-                if(__pinInterruptHandlers[pin].fn) {
-                    if(__pinInterruptHandlers[pin].arg){
-                        ((voidFuncPtrArg)__pinInterruptHandlers[pin].fn)(__pinInterruptHandlers[pin].arg);
-                    } else {
-                        __pinInterruptHandlers[pin].fn();
-                    }
-                }
-            }
-        } while(++pin<GPIO_PIN_COUNT);
+static void ARDUINO_ISR_ATTR __onPinInterrupt(void *arg) {
+  InterruptHandle_t *isr = (InterruptHandle_t *)arg;
+  if (isr->fn) {
+    if (isr->arg) {
+      ((voidFuncPtrArg)isr->fn)(isr->arg);
+    } else {
+      isr->fn();
     }
+  }
 }
 
-extern void cleanupFunctional(void* arg);
-
-extern void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtrArg userFunc, void * arg, int intr_type, bool functional)
-{
-    static bool interrupt_initialized = false;
-
-    if(!interrupt_initialized) {
-        interrupt_initialized = true;
-        esp_intr_alloc(ETS_GPIO_INTR_SOURCE, (int)ESP_INTR_FLAG_IRAM, __onPinInterrupt, NULL, &gpio_intr_handle);
-    }
-
-    // if new attach without detach remove old info
-    if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg)
-    {
-    	cleanupFunctional(__pinInterruptHandlers[pin].arg);
-    }
-    __pinInterruptHandlers[pin].fn = (voidFuncPtr)userFunc;
-    __pinInterruptHandlers[pin].arg = arg;
-    __pinInterruptHandlers[pin].functional = functional;
-
-    esp_intr_disable(gpio_intr_handle);
-    if(esp_intr_get_cpu(gpio_intr_handle)) { //APP_CPU
-        GPIO.pin[pin].int_ena = 1;
-    } else { //PRO_CPU
-        GPIO.pin[pin].int_ena = 4;
-    }
-    GPIO.pin[pin].int_type = intr_type;
-    esp_intr_enable(gpio_intr_handle);
+extern void cleanupFunctional(void *arg);
+
+extern void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtrArg userFunc, void *arg, int intr_type, bool functional) {
+  static bool interrupt_initialized = false;
+
+  // makes sure that pin -1 (255) will never work -- this follows Arduino standard
+  if (pin >= SOC_GPIO_PIN_COUNT) {
+    return;
+  }
+
+  if (!interrupt_initialized) {
+    esp_err_t err = gpio_install_isr_service((int)ARDUINO_ISR_FLAG);
+    interrupt_initialized = (err == ESP_OK) || (err == ESP_ERR_INVALID_STATE);
+  }
+  if (!interrupt_initialized) {
+    log_e("IO %i ISR Service Failed To Start", pin);
+    return;
+  }
+
+  // if new attach without detach remove old info
+  if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg) {
+    cleanupFunctional(__pinInterruptHandlers[pin].arg);
+  }
+  __pinInterruptHandlers[pin].fn = (voidFuncPtr)userFunc;
+  __pinInterruptHandlers[pin].arg = arg;
+  __pinInterruptHandlers[pin].functional = functional;
+
+  gpio_set_intr_type((gpio_num_t)pin, (gpio_int_type_t)(intr_type & 0x7));
+  if (intr_type & 0x8) {
+    gpio_wakeup_enable((gpio_num_t)pin, (gpio_int_type_t)(intr_type & 0x7));
+  }
+  gpio_isr_handler_add((gpio_num_t)pin, __onPinInterrupt, &__pinInterruptHandlers[pin]);
+
+  //FIX interrupts on peripherals outputs (eg. LEDC,...)
+  //Enable input in GPIO register
+  gpio_hal_context_t gpiohal;
+  gpiohal.dev = GPIO_LL_GET_HW(GPIO_PORT_0);
+  gpio_hal_input_enable(&gpiohal, pin);
 }
 
-extern void __attachInterruptArg(uint8_t pin, voidFuncPtrArg userFunc, void * arg, int intr_type)
-{
-	__attachInterruptFunctionalArg(pin, userFunc, arg, intr_type, false);
+extern void __attachInterruptArg(uint8_t pin, voidFuncPtrArg userFunc, void *arg, int intr_type) {
+  __attachInterruptFunctionalArg(pin, userFunc, arg, intr_type, false);
 }
 
 extern void __attachInterrupt(uint8_t pin, voidFuncPtr userFunc, int intr_type) {
-    __attachInterruptFunctionalArg(pin, (voidFuncPtrArg)userFunc, NULL, intr_type, false);
+  __attachInterruptFunctionalArg(pin, (voidFuncPtrArg)userFunc, NULL, intr_type, false);
 }
 
-extern void __detachInterrupt(uint8_t pin)
-{
-    esp_intr_disable(gpio_intr_handle);
-    if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg)
-    {
-    	cleanupFunctional(__pinInterruptHandlers[pin].arg);
-    }
-    __pinInterruptHandlers[pin].fn = NULL;
-    __pinInterruptHandlers[pin].arg = NULL;
-    __pinInterruptHandlers[pin].functional = false;
+extern void __detachInterrupt(uint8_t pin) {
+  gpio_isr_handler_remove((gpio_num_t)pin);  //remove handle and disable isr for pin
+  gpio_wakeup_disable((gpio_num_t)pin);
+
+  if (__pinInterruptHandlers[pin].functional && __pinInterruptHandlers[pin].arg) {
+    cleanupFunctional(__pinInterruptHandlers[pin].arg);
+  }
+  __pinInterruptHandlers[pin].fn = NULL;
+  __pinInterruptHandlers[pin].arg = NULL;
+  __pinInterruptHandlers[pin].functional = false;
 
-    GPIO.pin[pin].int_ena = 0;
-    GPIO.pin[pin].int_type = 0;
-    esp_intr_enable(gpio_intr_handle);
+  gpio_set_intr_type((gpio_num_t)pin, GPIO_INTR_DISABLE);
 }
 
+extern void enableInterrupt(uint8_t pin) {
+  gpio_intr_enable((gpio_num_t)pin);
+}
 
-extern void pinMode(uint8_t pin, uint8_t mode) __attribute__ ((weak, alias("__pinMode")));
-extern void digitalWrite(uint8_t pin, uint8_t val) __attribute__ ((weak, alias("__digitalWrite")));
-extern int digitalRead(uint8_t pin) __attribute__ ((weak, alias("__digitalRead")));
-extern void attachInterrupt(uint8_t pin, voidFuncPtr handler, int mode) __attribute__ ((weak, alias("__attachInterrupt")));
-extern void attachInterruptArg(uint8_t pin, voidFuncPtrArg handler, void * arg, int mode) __attribute__ ((weak, alias("__attachInterruptArg")));
-extern void detachInterrupt(uint8_t pin) __attribute__ ((weak, alias("__detachInterrupt")));
+extern void disableInterrupt(uint8_t pin) {
+  gpio_intr_disable((gpio_num_t)pin);
+}
 
+extern void pinMode(uint8_t pin, uint8_t mode) __attribute__((weak, alias("__pinMode")));
+extern void digitalWrite(uint8_t pin, uint8_t val) __attribute__((weak, alias("__digitalWrite")));
+extern int digitalRead(uint8_t pin) __attribute__((weak, alias("__digitalRead")));
+extern void attachInterrupt(uint8_t pin, voidFuncPtr handler, int mode) __attribute__((weak, alias("__attachInterrupt")));
+extern void attachInterruptArg(uint8_t pin, voidFuncPtrArg handler, void *arg, int mode) __attribute__((weak, alias("__attachInterruptArg")));
+extern void detachInterrupt(uint8_t pin) __attribute__((weak, alias("__detachInterrupt")));
diff --git a/cores/esp32/esp32-hal-gpio.h b/cores/esp32/esp32-hal-gpio.h
index daa9f6e66fa..9fce4368c22 100644
--- a/cores/esp32/esp32-hal-gpio.h
+++ b/cores/esp32/esp32-hal-gpio.h
@@ -24,27 +24,35 @@
 extern "C" {
 #endif
 
+#include "pins_arduino.h"
 #include "esp32-hal.h"
+#include "soc/soc_caps.h"
+#include "driver/gpio.h"
+
+#if (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3)
+#define NUM_OUPUT_PINS 46
+#define PIN_DAC1       17
+#define PIN_DAC2       18
+#else
+#define NUM_OUPUT_PINS 34
+#define PIN_DAC1       25
+#define PIN_DAC2       26
+#endif
 
-#define LOW               0x0
-#define HIGH              0x1
+#define LOW  0x0
+#define HIGH 0x1
 
 //GPIO FUNCTIONS
-#define INPUT             0x01
-#define OUTPUT            0x02
+#define INPUT 0x01
+// Changed OUTPUT from 0x02 to behave the same as Arduino pinMode(pin,OUTPUT)
+// where you can read the state of pin even when it is set as OUTPUT
+#define OUTPUT            0x03
 #define PULLUP            0x04
 #define INPUT_PULLUP      0x05
 #define PULLDOWN          0x08
 #define INPUT_PULLDOWN    0x09
 #define OPEN_DRAIN        0x10
-#define OUTPUT_OPEN_DRAIN 0x12
-#define SPECIAL           0xF0
-#define FUNCTION_1        0x00
-#define FUNCTION_2        0x20
-#define FUNCTION_3        0x40
-#define FUNCTION_4        0x60
-#define FUNCTION_5        0x80
-#define FUNCTION_6        0xA0
+#define OUTPUT_OPEN_DRAIN 0x13
 #define ANALOG            0xC0
 
 //Interrupt Modes
@@ -57,30 +65,25 @@ extern "C" {
 #define ONLOW_WE  0x0C
 #define ONHIGH_WE 0x0D
 
-typedef struct {
-    uint8_t reg;      /*!< GPIO register offset from DR_REG_IO_MUX_BASE */
-    int8_t rtc;       /*!< RTC GPIO number (-1 if not RTC GPIO pin) */
-    int8_t adc;       /*!< ADC Channel number (-1 if not ADC pin) */
-    int8_t touch;     /*!< Touch Channel number (-1 if not Touch pin) */
-} esp32_gpioMux_t;
-
-extern const esp32_gpioMux_t esp32_gpioMux[40];
-extern const int8_t esp32_adc2gpio[20];
+#define digitalPinIsValid(pin)   GPIO_IS_VALID_GPIO(pin)
+#define digitalPinCanOutput(pin) GPIO_IS_VALID_OUTPUT_GPIO(pin)
 
-#define digitalPinIsValid(pin)          ((pin) < 40 && esp32_gpioMux[(pin)].reg)
-#define digitalPinCanOutput(pin)        ((pin) < 34 && esp32_gpioMux[(pin)].reg)
-#define digitalPinToRtcPin(pin)         (((pin) < 40)?esp32_gpioMux[(pin)].rtc:-1)
-#define digitalPinToAnalogChannel(pin)  (((pin) < 40)?esp32_gpioMux[(pin)].adc:-1)
-#define digitalPinToTouchChannel(pin)   (((pin) < 40)?esp32_gpioMux[(pin)].touch:-1)
-#define digitalPinToDacChannel(pin)     (((pin) == 25)?0:((pin) == 26)?1:-1)
+#define digitalPinToRtcPin(pin)     ((RTC_GPIO_IS_VALID_GPIO(pin)) ? rtc_io_number_get(pin) : -1)
+#define digitalPinToDacChannel(pin) (((pin) == DAC_CHANNEL_1_GPIO_NUM) ? 0 : ((pin) == DAC_CHANNEL_2_GPIO_NUM) ? 1 : -1)
 
 void pinMode(uint8_t pin, uint8_t mode);
 void digitalWrite(uint8_t pin, uint8_t val);
 int digitalRead(uint8_t pin);
 
 void attachInterrupt(uint8_t pin, void (*)(void), int mode);
-void attachInterruptArg(uint8_t pin, void (*)(void*), void * arg, int mode);
+void attachInterruptArg(uint8_t pin, void (*)(void *), void *arg, int mode);
 void detachInterrupt(uint8_t pin);
+void enableInterrupt(uint8_t pin);
+void disableInterrupt(uint8_t pin);
+
+int8_t digitalPinToTouchChannel(uint8_t pin);
+int8_t digitalPinToAnalogChannel(uint8_t pin);
+int8_t analogChannelToDigitalPin(uint8_t channel);
 
 #ifdef __cplusplus
 }
diff --git a/cores/esp32/esp32-hal-i2c-ng.c b/cores/esp32/esp32-hal-i2c-ng.c
new file mode 100644
index 00000000000..8e48d0e0397
--- /dev/null
+++ b/cores/esp32/esp32-hal-i2c-ng.c
@@ -0,0 +1,445 @@
+// Copyright 2015-2025 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "esp32-hal-i2c.h"
+
+#if SOC_I2C_SUPPORTED
+#include "esp_idf_version.h"
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
+#include "esp32-hal.h"
+#if !CONFIG_DISABLE_HAL_LOCKS
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#endif
+#include "esp_attr.h"
+#include "esp_system.h"
+#include "soc/soc_caps.h"
+#include "driver/i2c_master.h"
+#include "esp32-hal-periman.h"
+
+typedef volatile struct {
+  bool initialized;
+  uint32_t frequency;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  SemaphoreHandle_t lock;
+#endif
+  int8_t scl;
+  int8_t sda;
+  i2c_master_bus_handle_t bus_handle;
+  i2c_master_dev_handle_t dev_handles[128];
+} i2c_bus_t;
+
+static i2c_bus_t bus[SOC_I2C_NUM];
+
+static bool i2cDetachBus(void *bus_i2c_num) {
+  uint8_t i2c_num = (int)bus_i2c_num - 1;
+  if (!bus[i2c_num].initialized) {
+    return true;
+  }
+  esp_err_t err = i2cDeinit(i2c_num);
+  if (err != ESP_OK) {
+    log_e("i2cDeinit failed with error: %d", err);
+    return false;
+  }
+  return true;
+}
+
+bool i2cIsInit(uint8_t i2c_num) {
+  if (i2c_num >= SOC_I2C_NUM) {
+    return false;
+  }
+  return bus[i2c_num].initialized;
+}
+
+esp_err_t i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency) {
+  esp_err_t ret = ESP_OK;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (bus[i2c_num].lock == NULL) {
+    bus[i2c_num].lock = xSemaphoreCreateMutex();
+    if (bus[i2c_num].lock == NULL) {
+      log_e("xSemaphoreCreateMutex failed");
+      return ESP_ERR_NO_MEM;
+    }
+  }
+  //acquire lock
+  if (xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ESP_FAIL;
+  }
+#endif
+  if (bus[i2c_num].initialized) {
+    log_e("bus is already initialized");
+    ret = ESP_FAIL;
+    goto init_fail;
+  }
+
+  if (!frequency) {
+    frequency = 100000UL;
+  } else if (frequency > 1000000UL) {
+    frequency = 1000000UL;
+  }
+
+  perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SDA, i2cDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SCL, i2cDetachBus);
+
+  if (!perimanClearPinBus(sda) || !perimanClearPinBus(scl)) {
+    ret = ESP_FAIL;
+    goto init_fail;
+  }
+
+  log_i("Initializing I2C Master: num=%u sda=%d scl=%d freq=%lu", i2c_num, sda, scl, frequency);
+
+  i2c_master_bus_handle_t bus_handle = NULL;
+  i2c_master_bus_config_t bus_config;
+  memset(&bus_config, 0, sizeof(i2c_master_bus_config_t));
+  bus_config.i2c_port = (i2c_port_num_t)i2c_num;
+  bus_config.sda_io_num = (gpio_num_t)sda;
+  bus_config.scl_io_num = (gpio_num_t)scl;
+#if SOC_LP_I2C_SUPPORTED
+  if (i2c_num >= SOC_HP_I2C_NUM) {
+    bus_config.lp_source_clk = LP_I2C_SCLK_DEFAULT;
+  } else
+#endif
+  {
+    bus_config.clk_source = I2C_CLK_SRC_DEFAULT;
+  }
+  bus_config.glitch_ignore_cnt = 7;
+  bus_config.intr_priority = 0;      // auto
+  bus_config.trans_queue_depth = 0;  // only valid in asynchronous transaction, which Arduino does not use
+  bus_config.flags.enable_internal_pullup = 1;
+#if SOC_I2C_SUPPORT_SLEEP_RETENTION
+  bus_config.flags.allow_pd = 1;  // backup/restore the I2C registers before/after entering/exist sleep mode
+#endif
+
+  ret = i2c_new_master_bus(&bus_config, &bus_handle);
+  if (ret != ESP_OK) {
+    log_e("i2c_new_master_bus failed: [%d] %s", ret, esp_err_to_name(ret));
+  } else {
+    bus[i2c_num].initialized = true;
+    bus[i2c_num].frequency = frequency;
+    bus[i2c_num].scl = scl;
+    bus[i2c_num].sda = sda;
+    bus[i2c_num].bus_handle = bus_handle;
+    for (uint8_t i = 0; i < 128; i++) {
+      bus[i2c_num].dev_handles[i] = NULL;
+    }
+    if (!perimanSetPinBus(sda, ESP32_BUS_TYPE_I2C_MASTER_SDA, (void *)(i2c_num + 1), i2c_num, -1)
+        || !perimanSetPinBus(scl, ESP32_BUS_TYPE_I2C_MASTER_SCL, (void *)(i2c_num + 1), i2c_num, -1)) {
+#if !CONFIG_DISABLE_HAL_LOCKS
+      //release lock so that i2cDetachBus can execute i2cDeinit
+      xSemaphoreGive(bus[i2c_num].lock);
+#endif
+      i2cDetachBus((void *)(i2c_num + 1));
+      return ESP_FAIL;
+    }
+  }
+
+init_fail:
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
+#endif
+  return ret;
+}
+
+esp_err_t i2cDeinit(uint8_t i2c_num) {
+  esp_err_t err = ESP_FAIL;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return err;
+  }
+#endif
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+  } else {
+    // remove devices from the bus
+    for (uint8_t i = 0; i < 128; i++) {
+      if (bus[i2c_num].dev_handles[i] != NULL) {
+        err = i2c_master_bus_rm_device(bus[i2c_num].dev_handles[i]);
+        bus[i2c_num].dev_handles[i] = NULL;
+        if (err != ESP_OK) {
+          log_e("i2c_master_bus_rm_device failed: [%d] %s", err, esp_err_to_name(err));
+        }
+      }
+    }
+    err = i2c_del_master_bus(bus[i2c_num].bus_handle);
+    if (err != ESP_OK) {
+      log_e("i2c_del_master_bus failed: [%d] %s", err, esp_err_to_name(err));
+    } else {
+      bus[i2c_num].initialized = false;
+      perimanClearPinBus(bus[i2c_num].scl);
+      perimanClearPinBus(bus[i2c_num].sda);
+      bus[i2c_num].scl = -1;
+      bus[i2c_num].sda = -1;
+      bus[i2c_num].bus_handle = NULL;
+    }
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
+#endif
+  return err;
+}
+
+static esp_err_t i2cAddDeviceIfNeeded(uint8_t i2c_num, uint16_t address) {
+  esp_err_t ret = ESP_OK;
+  if (bus[i2c_num].dev_handles[address] == NULL) {
+    i2c_master_dev_handle_t dev_handle = NULL;
+    i2c_device_config_t dev_config;
+    memset(&dev_config, 0, sizeof(i2c_device_config_t));
+    dev_config.dev_addr_length = I2C_ADDR_BIT_LEN_7;  // Arduino supports only 7bit addresses
+    dev_config.device_address = address;
+    dev_config.scl_speed_hz = bus[i2c_num].frequency;
+    dev_config.scl_wait_us = 0;
+    dev_config.flags.disable_ack_check = 0;
+
+    ret = i2c_master_bus_add_device(bus[i2c_num].bus_handle, &dev_config, &dev_handle);
+    if (ret != ESP_OK) {
+      log_e("i2c_master_bus_add_device failed: [%d] %s", ret, esp_err_to_name(ret));
+    } else {
+      bus[i2c_num].dev_handles[address] = dev_handle;
+      log_v("added device: bus=%u addr=0x%x handle=0x%08x", i2c_num, address, dev_handle);
+    }
+  }
+  return ret;
+}
+
+esp_err_t i2cWrite(uint8_t i2c_num, uint16_t address, const uint8_t *buff, size_t size, uint32_t timeOutMillis) {
+  esp_err_t ret = ESP_FAIL;
+  // i2c_cmd_handle_t cmd = NULL;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+  if (address >= 128) {
+    log_e("Only 7bit I2C addresses are supported");
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ret;
+  }
+#endif
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+    goto end;
+  }
+
+  if (size == 0) {
+    // Probe device
+    ret = i2c_master_probe(bus[i2c_num].bus_handle, address, timeOutMillis);
+    if (ret != ESP_OK) {
+      log_v("i2c_master_probe failed: [%d] %s", ret, esp_err_to_name(ret));
+    }
+  } else {
+    // writing data to device
+    ret = i2cAddDeviceIfNeeded(i2c_num, address);
+    if (ret != ESP_OK) {
+      goto end;
+    }
+
+    log_v("i2c_master_transmit: bus=%u addr=0x%x handle=0x%08x size=%u", i2c_num, address, bus[i2c_num].dev_handles[address], size);
+    ret = i2c_master_transmit(bus[i2c_num].dev_handles[address], buff, size, timeOutMillis);
+    if (ret != ESP_OK) {
+      log_e("i2c_master_transmit failed: [%d] %s", ret, esp_err_to_name(ret));
+      goto end;
+    }
+
+    // wait for transactions to finish (is it needed with sync transactions?)
+    // ret = i2c_master_bus_wait_all_done(bus[i2c_num].bus_handle, timeOutMillis);
+    // if (ret != ESP_OK) {
+    //   log_e("i2c_master_bus_wait_all_done failed: [%d] %s", ret, esp_err_to_name(ret));
+    //   goto end;
+    // }
+  }
+
+end:
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
+#endif
+  return ret;
+}
+
+esp_err_t i2cRead(uint8_t i2c_num, uint16_t address, uint8_t *buff, size_t size, uint32_t timeOutMillis, size_t *readCount) {
+  esp_err_t ret = ESP_FAIL;
+  *readCount = 0;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ret;
+  }
+#endif
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+    goto end;
+  }
+
+  ret = i2cAddDeviceIfNeeded(i2c_num, address);
+  if (ret != ESP_OK) {
+    goto end;
+  }
+
+  log_v("i2c_master_receive: bus=%u addr=0x%x handle=0x%08x size=%u", i2c_num, address, bus[i2c_num].dev_handles[address], size);
+  ret = i2c_master_receive(bus[i2c_num].dev_handles[address], buff, size, timeOutMillis);
+  if (ret != ESP_OK) {
+    log_e("i2c_master_receive failed: [%d] %s", ret, esp_err_to_name(ret));
+    goto end;
+  }
+
+  // wait for transactions to finish (is it needed with sync transactions?)
+  // ret = i2c_master_bus_wait_all_done(bus[i2c_num].bus_handle, timeOutMillis);
+  // if (ret != ESP_OK) {
+  //   log_e("i2c_master_bus_wait_all_done failed: [%d] %s", ret, esp_err_to_name(ret));
+  //   goto end;
+  // }
+  *readCount = size;
+
+end:
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
+#endif
+  return ret;
+}
+
+esp_err_t i2cWriteReadNonStop(
+  uint8_t i2c_num, uint16_t address, const uint8_t *wbuff, size_t wsize, uint8_t *rbuff, size_t rsize, uint32_t timeOutMillis, size_t *readCount
+) {
+  esp_err_t ret = ESP_FAIL;
+  *readCount = 0;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ret;
+  }
+#endif
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+    goto end;
+  }
+
+  ret = i2cAddDeviceIfNeeded(i2c_num, address);
+  if (ret != ESP_OK) {
+    goto end;
+  }
+
+  log_v("i2c_master_transmit_receive: bus=%u addr=0x%x handle=0x%08x write=%u read=%u", i2c_num, address, bus[i2c_num].dev_handles[address], wsize, rsize);
+  ret = i2c_master_transmit_receive(bus[i2c_num].dev_handles[address], wbuff, wsize, rbuff, rsize, timeOutMillis);
+  if (ret != ESP_OK) {
+    log_e("i2c_master_transmit_receive failed: [%d] %s", ret, esp_err_to_name(ret));
+    goto end;
+  }
+
+  // wait for transactions to finish (is it needed with sync transactions?)
+  // ret = i2c_master_bus_wait_all_done(bus[i2c_num].bus_handle, timeOutMillis);
+  // if (ret != ESP_OK) {
+  //   log_e("i2c_master_bus_wait_all_done failed: [%d] %s", ret, esp_err_to_name(ret));
+  //   goto end;
+  // }
+  *readCount = rsize;
+
+end:
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
+#endif
+  return ret;
+}
+
+esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency) {
+  esp_err_t ret = ESP_FAIL;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ret;
+  }
+#endif
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+    goto end;
+  }
+  if (bus[i2c_num].frequency == frequency) {
+    ret = ESP_OK;
+    goto end;
+  }
+  if (!frequency) {
+    frequency = 100000UL;
+  } else if (frequency > 1000000UL) {
+    frequency = 1000000UL;
+  }
+
+  bus[i2c_num].frequency = frequency;
+
+  // loop through devices, remove them and then re-add them with the new frequency
+  for (uint8_t i = 0; i < 128; i++) {
+    if (bus[i2c_num].dev_handles[i] != NULL) {
+      ret = i2c_master_bus_rm_device(bus[i2c_num].dev_handles[i]);
+      if (ret != ESP_OK) {
+        log_e("i2c_master_bus_rm_device failed: [%d] %s", ret, esp_err_to_name(ret));
+        goto end;
+      } else {
+        bus[i2c_num].dev_handles[i] = NULL;
+        ret = i2cAddDeviceIfNeeded(i2c_num, i);
+        if (ret != ESP_OK) {
+          goto end;
+        }
+      }
+    }
+  }
+
+end:
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
+#endif
+  return ret;
+}
+
+esp_err_t i2cGetClock(uint8_t i2c_num, uint32_t *frequency) {
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+    return ESP_FAIL;
+  }
+  *frequency = bus[i2c_num].frequency;
+  return ESP_OK;
+}
+
+#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0) */
+#endif /* SOC_I2C_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-i2c-slave.c b/cores/esp32/esp32-hal-i2c-slave.c
new file mode 100644
index 00000000000..46c3a4d58c2
--- /dev/null
+++ b/cores/esp32/esp32-hal-i2c-slave.c
@@ -0,0 +1,911 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/soc_caps.h"
+
+#if SOC_I2C_SUPPORT_SLAVE
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <inttypes.h>
+#include <string.h>
+#include <math.h>
+
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "rom/gpio.h"
+#include "soc/gpio_sig_map.h"
+#include "hal/gpio_types.h"
+#include "driver/gpio.h"
+#include "esp_err.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+#include "freertos/ringbuf.h"
+
+#include "esp_intr_alloc.h"
+#include "soc/i2c_reg.h"
+#include "soc/i2c_struct.h"
+#include "soc/periph_defs.h"
+#include "hal/i2c_ll.h"
+#include "hal/clk_gate_ll.h"
+#include "esp32-hal-log.h"
+#include "esp32-hal-i2c-slave.h"
+#include "esp32-hal-periman.h"
+#include "esp_private/periph_ctrl.h"
+
+#if SOC_PERIPH_CLK_CTRL_SHARED
+#define I2C_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define I2C_CLOCK_SRC_ATOMIC()
+#endif
+
+#if !SOC_RCC_IS_INDEPENDENT
+#define I2C_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define I2C_RCC_ATOMIC()
+#endif
+
+#define I2C_SLAVE_USE_RX_QUEUE 0  // 1: Queue, 0: RingBuffer
+
+#ifdef CONFIG_IDF_TARGET_ESP32P4
+#define I2C_SCL_IDX(p) ((p == 0) ? I2C0_SCL_PAD_OUT_IDX : ((p == 1) ? I2C1_SCL_PAD_OUT_IDX : 0))
+#define I2C_SDA_IDX(p) ((p == 0) ? I2C0_SDA_PAD_OUT_IDX : ((p == 1) ? I2C1_SDA_PAD_OUT_IDX : 0))
+#else
+#if SOC_HP_I2C_NUM > 1
+#define I2C_SCL_IDX(p) ((p == 0) ? I2CEXT0_SCL_OUT_IDX : ((p == 1) ? I2CEXT1_SCL_OUT_IDX : 0))
+#define I2C_SDA_IDX(p) ((p == 0) ? I2CEXT0_SDA_OUT_IDX : ((p == 1) ? I2CEXT1_SDA_OUT_IDX : 0))
+#else
+#define I2C_SCL_IDX(p) I2CEXT0_SCL_OUT_IDX
+#define I2C_SDA_IDX(p) I2CEXT0_SDA_OUT_IDX
+#endif
+#endif  // ifdef CONFIG_IDF_TARGET_ESP32P4
+
+#if CONFIG_IDF_TARGET_ESP32
+#define I2C_TXFIFO_WM_INT_ENA I2C_TXFIFO_EMPTY_INT_ENA
+#define I2C_RXFIFO_WM_INT_ENA I2C_RXFIFO_FULL_INT_ENA
+#endif
+
+enum {
+  I2C_SLAVE_EVT_RX,
+  I2C_SLAVE_EVT_TX
+};
+
+typedef struct i2c_slave_struct_t {
+  i2c_dev_t *dev;
+  uint8_t num;
+  int8_t sda;
+  int8_t scl;
+  i2c_slave_request_cb_t request_callback;
+  i2c_slave_receive_cb_t receive_callback;
+  void *arg;
+  intr_handle_t intr_handle;
+  TaskHandle_t task_handle;
+  QueueHandle_t event_queue;
+#if I2C_SLAVE_USE_RX_QUEUE
+  QueueHandle_t rx_queue;
+#else
+  RingbufHandle_t rx_ring_buf;
+#endif
+  QueueHandle_t tx_queue;
+  uint32_t rx_data_count;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  SemaphoreHandle_t lock;
+#endif
+} i2c_slave_struct_t;
+
+typedef union {
+  struct {
+    uint32_t event : 2;
+    uint32_t stop  : 1;
+    uint32_t param : 29;
+  };
+  uint32_t val;
+} i2c_slave_queue_event_t;
+
+static i2c_slave_struct_t _i2c_bus_array[SOC_HP_I2C_NUM] = {
+  {&I2C0, 0, -1, -1, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 0
+#if !CONFIG_DISABLE_HAL_LOCKS
+   ,
+   NULL
+#endif
+  },
+#if SOC_HP_I2C_NUM > 1
+  {&I2C1, 1, -1, -1, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 0
+#if !CONFIG_DISABLE_HAL_LOCKS
+   ,
+   NULL
+#endif
+  }
+#endif
+};
+
+#if CONFIG_DISABLE_HAL_LOCKS
+#define I2C_SLAVE_MUTEX_LOCK()
+#define I2C_SLAVE_MUTEX_UNLOCK()
+#else
+#define I2C_SLAVE_MUTEX_LOCK()                \
+  if (i2c->lock) {                            \
+    xSemaphoreTake(i2c->lock, portMAX_DELAY); \
+  }
+#define I2C_SLAVE_MUTEX_UNLOCK() \
+  if (i2c->lock) {               \
+    xSemaphoreGive(i2c->lock);   \
+  }
+#endif
+
+//-------------------------------------- HAL_LL (Missing Functions) ------------------------------------------------
+typedef enum {
+  I2C_STRETCH_CAUSE_MASTER_READ,
+  I2C_STRETCH_CAUSE_TX_FIFO_EMPTY,
+  I2C_STRETCH_CAUSE_RX_FIFO_FULL,
+  I2C_STRETCH_CAUSE_MAX
+} i2c_stretch_cause_t;
+
+static inline i2c_stretch_cause_t i2c_ll_stretch_cause(i2c_dev_t *hw) {
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
+  return hw->sr.stretch_cause;
+#elif CONFIG_IDF_TARGET_ESP32S2
+  return hw->status_reg.stretch_cause;
+#else
+  return I2C_STRETCH_CAUSE_MAX;
+#endif
+}
+
+static inline void i2c_ll_set_stretch(i2c_dev_t *hw, uint16_t time) {
+#ifndef CONFIG_IDF_TARGET_ESP32
+  typeof(hw->scl_stretch_conf) scl_stretch_conf;
+  scl_stretch_conf.val = 0;
+  scl_stretch_conf.slave_scl_stretch_en = (time > 0);
+  scl_stretch_conf.stretch_protect_num = time;
+  scl_stretch_conf.slave_scl_stretch_clr = 1;
+  hw->scl_stretch_conf.val = scl_stretch_conf.val;
+  if (time > 0) {
+    //enable interrupt
+    hw->int_ena.val |= I2C_SLAVE_STRETCH_INT_ENA;
+  } else {
+    //disable interrupt
+    hw->int_ena.val &= (~I2C_SLAVE_STRETCH_INT_ENA);
+  }
+#endif
+}
+
+static inline void i2c_ll_stretch_clr(i2c_dev_t *hw) {
+#ifndef CONFIG_IDF_TARGET_ESP32
+  hw->scl_stretch_conf.slave_scl_stretch_clr = 1;
+#endif
+}
+
+static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw) {
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+  return hw->status_reg.slave_addressed;
+#else
+  return hw->sr.slave_addressed;
+#endif
+}
+
+static inline bool i2c_ll_slave_rw(i2c_dev_t *hw)  //not exposed by hal_ll
+{
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+  return hw->status_reg.slave_rw;
+#else
+  return hw->sr.slave_rw;
+#endif
+}
+
+//-------------------------------------- PRIVATE (Function Prototypes) ------------------------------------------------
+static void i2c_slave_free_resources(i2c_slave_struct_t *i2c);
+static void i2c_slave_delay_us(uint64_t us);
+static void i2c_slave_gpio_mode(int8_t pin, gpio_mode_t mode);
+static bool i2c_slave_check_line_state(int8_t sda, int8_t scl);
+static bool i2c_slave_attach_gpio(i2c_slave_struct_t *i2c, int8_t sda, int8_t scl);
+static bool i2c_slave_detach_gpio(i2c_slave_struct_t *i2c);
+static bool i2c_slave_set_frequency(i2c_slave_struct_t *i2c, uint32_t clk_speed);
+static bool i2c_slave_send_event(i2c_slave_struct_t *i2c, i2c_slave_queue_event_t *event);
+static bool i2c_slave_handle_tx_fifo_empty(i2c_slave_struct_t *i2c);
+static bool i2c_slave_handle_rx_fifo_full(i2c_slave_struct_t *i2c, uint32_t len);
+static size_t i2c_slave_read_rx(i2c_slave_struct_t *i2c, uint8_t *data, size_t len);
+static void i2c_slave_isr_handler(void *arg);
+static void i2c_slave_task(void *pv_args);
+static bool i2cSlaveDetachBus(void *bus_i2c_num);
+
+//=====================================================================================================================
+//-------------------------------------- Public Functions -------------------------------------------------------------
+//=====================================================================================================================
+
+esp_err_t i2cSlaveAttachCallbacks(uint8_t num, i2c_slave_request_cb_t request_callback, i2c_slave_receive_cb_t receive_callback, void *arg) {
+  if (num >= SOC_HP_I2C_NUM) {
+    log_e("Invalid port num: %u", num);
+    return ESP_ERR_INVALID_ARG;
+  }
+  i2c_slave_struct_t *i2c = &_i2c_bus_array[num];
+  I2C_SLAVE_MUTEX_LOCK();
+  i2c->request_callback = request_callback;
+  i2c->receive_callback = receive_callback;
+  i2c->arg = arg;
+  I2C_SLAVE_MUTEX_UNLOCK();
+  return ESP_OK;
+}
+
+esp_err_t i2cSlaveInit(uint8_t num, int sda, int scl, uint16_t slaveID, uint32_t frequency, size_t rx_len, size_t tx_len) {
+  if (num >= SOC_HP_I2C_NUM) {
+    log_e("Invalid port num: %u", num);
+    return ESP_ERR_INVALID_ARG;
+  }
+
+  if (sda < 0 || scl < 0) {
+    log_e("invalid pins sda=%d, scl=%d", sda, scl);
+    return ESP_ERR_INVALID_ARG;
+  }
+
+  if (!frequency) {
+    frequency = 100000;
+  } else if (frequency > 1000000) {
+    frequency = 1000000;
+  }
+
+  perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_SLAVE_SDA, i2cSlaveDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_SLAVE_SCL, i2cSlaveDetachBus);
+
+  if (!perimanClearPinBus(sda) || !perimanClearPinBus(scl)) {
+    return false;
+  }
+
+  log_i("Initializing I2C Slave: sda=%d scl=%d freq=%d, addr=0x%x", sda, scl, frequency, slaveID);
+
+  i2c_slave_struct_t *i2c = &_i2c_bus_array[num];
+  esp_err_t ret = ESP_OK;
+
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (!i2c->lock) {
+    i2c->lock = xSemaphoreCreateMutex();
+    if (i2c->lock == NULL) {
+      log_e("RX queue create failed");
+      return ESP_ERR_NO_MEM;
+    }
+  }
+#endif
+
+  I2C_SLAVE_MUTEX_LOCK();
+  i2c_slave_free_resources(i2c);
+
+#if I2C_SLAVE_USE_RX_QUEUE
+  i2c->rx_queue = xQueueCreate(rx_len, sizeof(uint8_t));
+  if (i2c->rx_queue == NULL) {
+    log_e("RX queue create failed");
+    ret = ESP_ERR_NO_MEM;
+    goto fail;
+  }
+#else
+  i2c->rx_ring_buf = xRingbufferCreate(rx_len, RINGBUF_TYPE_BYTEBUF);
+  if (i2c->rx_ring_buf == NULL) {
+    log_e("RX RingBuf create failed");
+    ret = ESP_ERR_NO_MEM;
+    goto fail;
+  }
+#endif
+
+  i2c->tx_queue = xQueueCreate(tx_len, sizeof(uint8_t));
+  if (i2c->tx_queue == NULL) {
+    log_e("TX queue create failed");
+    ret = ESP_ERR_NO_MEM;
+    goto fail;
+  }
+
+  i2c->event_queue = xQueueCreate(16, sizeof(i2c_slave_queue_event_t));
+  if (i2c->event_queue == NULL) {
+    log_e("Event queue create failed");
+    ret = ESP_ERR_NO_MEM;
+    goto fail;
+  }
+
+  xTaskCreate(i2c_slave_task, "i2c_slave_task", 4096, i2c, 20, &i2c->task_handle);
+  if (i2c->task_handle == NULL) {
+    log_e("Event thread create failed");
+    ret = ESP_ERR_NO_MEM;
+    goto fail;
+  }
+
+  if (frequency == 0) {
+    frequency = 100000L;
+  }
+  frequency = (frequency * 5) / 4;
+#if !defined(CONFIG_IDF_TARGET_ESP32P4)
+  if (i2c->num == 0) {
+    periph_ll_enable_clk_clear_rst(PERIPH_I2C0_MODULE);
+#if SOC_HP_I2C_NUM > 1
+  } else {
+    periph_ll_enable_clk_clear_rst(PERIPH_I2C1_MODULE);
+#endif
+  }
+#endif  // !defined(CONFIG_IDF_TARGET_ESP32P4)
+
+  i2c_ll_slave_init(i2c->dev);
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
+  i2c_ll_enable_fifo_mode(i2c->dev, true);
+#else
+  i2c_ll_slave_set_fifo_mode(i2c->dev, true);
+#endif
+  i2c_ll_set_slave_addr(i2c->dev, slaveID, false);
+  i2c_ll_set_tout(i2c->dev, I2C_LL_MAX_TIMEOUT);
+  i2c_slave_set_frequency(i2c, frequency);
+
+  if (!i2c_slave_check_line_state(sda, scl)) {
+    log_e("bad pin state");
+    ret = ESP_FAIL;
+    goto fail;
+  }
+
+  i2c_slave_attach_gpio(i2c, sda, scl);
+
+  if (i2c_ll_is_bus_busy(i2c->dev)) {
+    log_w("Bus busy, reinit");
+    ret = ESP_FAIL;
+    goto fail;
+  }
+
+  i2c_ll_disable_intr_mask(i2c->dev, I2C_LL_INTR_MASK);
+  i2c_ll_clear_intr_mask(i2c->dev, I2C_LL_INTR_MASK);
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
+  i2c_ll_enable_fifo_mode(i2c->dev, true);
+#else
+  i2c_ll_slave_set_fifo_mode(i2c->dev, true);
+#endif
+
+  if (!i2c->intr_handle) {
+    uint32_t flags = ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED;
+    if (i2c->num == 0) {
+#if !defined(CONFIG_IDF_TARGET_ESP32P4)
+      ret = esp_intr_alloc(ETS_I2C_EXT0_INTR_SOURCE, flags, &i2c_slave_isr_handler, i2c, &i2c->intr_handle);
+#else
+      ret = esp_intr_alloc(ETS_I2C0_INTR_SOURCE, flags, &i2c_slave_isr_handler, i2c, &i2c->intr_handle);
+#endif
+#if SOC_HP_I2C_NUM > 1
+    } else {
+#if !defined(CONFIG_IDF_TARGET_ESP32P4)
+      ret = esp_intr_alloc(ETS_I2C_EXT1_INTR_SOURCE, flags, &i2c_slave_isr_handler, i2c, &i2c->intr_handle);
+#else
+      ret = esp_intr_alloc(ETS_I2C1_INTR_SOURCE, flags, &i2c_slave_isr_handler, i2c, &i2c->intr_handle);
+#endif
+#endif
+    }
+
+    if (ret != ESP_OK) {
+      log_e("install interrupt handler Failed=%d", ret);
+      goto fail;
+    }
+  }
+
+  i2c_ll_txfifo_rst(i2c->dev);
+  i2c_ll_rxfifo_rst(i2c->dev);
+  i2c_ll_slave_enable_rx_it(i2c->dev);
+  i2c_ll_set_stretch(i2c->dev, 0x3FF);
+  i2c_ll_update(i2c->dev);
+  if (!perimanSetPinBus(sda, ESP32_BUS_TYPE_I2C_SLAVE_SDA, (void *)(i2c->num + 1), i2c->num, -1)
+      || !perimanSetPinBus(scl, ESP32_BUS_TYPE_I2C_SLAVE_SCL, (void *)(i2c->num + 1), i2c->num, -1)) {
+    i2cSlaveDetachBus((void *)(i2c->num + 1));
+    ret = ESP_FAIL;
+  }
+  I2C_SLAVE_MUTEX_UNLOCK();
+  return ret;
+
+fail:
+  i2c_slave_free_resources(i2c);
+  I2C_SLAVE_MUTEX_UNLOCK();
+  return ret;
+}
+
+esp_err_t i2cSlaveDeinit(uint8_t num) {
+  if (num >= SOC_HP_I2C_NUM) {
+    log_e("Invalid port num: %u", num);
+    return ESP_ERR_INVALID_ARG;
+  }
+
+  i2c_slave_struct_t *i2c = &_i2c_bus_array[num];
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (!i2c->lock) {
+    log_e("Lock is not initialized! Did you call i2c_slave_init()?");
+    return ESP_ERR_NO_MEM;
+  }
+#endif
+  I2C_SLAVE_MUTEX_LOCK();
+  int scl = i2c->scl;
+  int sda = i2c->sda;
+  i2c_slave_free_resources(i2c);
+  perimanClearPinBus(scl);
+  perimanClearPinBus(sda);
+  I2C_SLAVE_MUTEX_UNLOCK();
+  return ESP_OK;
+}
+
+size_t i2cSlaveWrite(uint8_t num, const uint8_t *buf, uint32_t len, uint32_t timeout_ms) {
+  if (num >= SOC_HP_I2C_NUM) {
+    log_e("Invalid port num: %u", num);
+    return 0;
+  }
+  uint32_t to_queue = 0, to_fifo = 0;
+  i2c_slave_struct_t *i2c = &_i2c_bus_array[num];
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (!i2c->lock) {
+    log_e("Lock is not initialized! Did you call i2c_slave_init()?");
+    return ESP_ERR_NO_MEM;
+  }
+#endif
+  if (!i2c->tx_queue) {
+    return 0;
+  }
+  I2C_SLAVE_MUTEX_LOCK();
+#if CONFIG_IDF_TARGET_ESP32
+  i2c_ll_slave_disable_tx_it(i2c->dev);
+  uint32_t txfifo_len = 0;
+  i2c_ll_get_txfifo_len(i2c->dev, &txfifo_len);
+  if (txfifo_len < SOC_I2C_FIFO_LEN) {
+    i2c_ll_txfifo_rst(i2c->dev);
+  }
+#endif
+  i2c_ll_get_txfifo_len(i2c->dev, &to_fifo);
+  if (to_fifo) {
+    if (len < to_fifo) {
+      to_fifo = len;
+    }
+    i2c_ll_write_txfifo(i2c->dev, (uint8_t *)buf, to_fifo);
+    buf += to_fifo;
+    len -= to_fifo;
+    //reset tx_queue
+    xQueueReset(i2c->tx_queue);
+    //write the rest of the bytes to the queue
+    if (len) {
+      to_queue = uxQueueSpacesAvailable(i2c->tx_queue);
+      if (len < to_queue) {
+        to_queue = len;
+      }
+      for (size_t i = 0; i < to_queue; i++) {
+        if (xQueueSend(i2c->tx_queue, &buf[i], timeout_ms / portTICK_PERIOD_MS) != pdTRUE) {
+          xQueueReset(i2c->tx_queue);
+          to_queue = 0;
+          break;
+        }
+      }
+      //no need to enable TX_EMPTY if tx_queue is empty
+      if (to_queue) {
+        i2c_ll_slave_enable_tx_it(i2c->dev);
+      }
+    }
+  }
+  I2C_SLAVE_MUTEX_UNLOCK();
+  return to_queue + to_fifo;
+}
+
+//=====================================================================================================================
+//-------------------------------------- Private Functions ------------------------------------------------------------
+//=====================================================================================================================
+
+static void i2c_slave_free_resources(i2c_slave_struct_t *i2c) {
+  i2c_slave_detach_gpio(i2c);
+  i2c_ll_set_slave_addr(i2c->dev, 0, false);
+  i2c_ll_disable_intr_mask(i2c->dev, I2C_LL_INTR_MASK);
+  i2c_ll_clear_intr_mask(i2c->dev, I2C_LL_INTR_MASK);
+
+  if (i2c->intr_handle) {
+    esp_intr_free(i2c->intr_handle);
+    i2c->intr_handle = NULL;
+  }
+
+  if (i2c->task_handle) {
+    vTaskDelete(i2c->task_handle);
+    i2c->task_handle = NULL;
+  }
+
+#if I2C_SLAVE_USE_RX_QUEUE
+  if (i2c->rx_queue) {
+    vQueueDelete(i2c->rx_queue);
+    i2c->rx_queue = NULL;
+  }
+#else
+  if (i2c->rx_ring_buf) {
+    vRingbufferDelete(i2c->rx_ring_buf);
+    i2c->rx_ring_buf = NULL;
+  }
+#endif
+
+  if (i2c->tx_queue) {
+    vQueueDelete(i2c->tx_queue);
+    i2c->tx_queue = NULL;
+  }
+
+  if (i2c->event_queue) {
+    vQueueDelete(i2c->event_queue);
+    i2c->event_queue = NULL;
+  }
+
+  i2c->rx_data_count = 0;
+}
+
+static bool i2c_slave_set_frequency(i2c_slave_struct_t *i2c, uint32_t clk_speed) {
+  if (i2c == NULL) {
+    log_e("no control buffer");
+    return false;
+  }
+  if (clk_speed > 1100000UL) {
+    clk_speed = 1100000UL;
+  }
+
+  // Adjust Fifo thresholds based on frequency
+  uint32_t a = (clk_speed / 50000L) + 2;
+  log_d("Fifo thresholds: rx_fifo_full = %d, tx_fifo_empty = %d", SOC_I2C_FIFO_LEN - a, a);
+
+  i2c_hal_clk_config_t clk_cal;
+#if SOC_I2C_SUPPORT_APB
+  i2c_ll_master_cal_bus_clk(APB_CLK_FREQ, clk_speed, &clk_cal);
+  I2C_CLOCK_SRC_ATOMIC() {
+    i2c_ll_set_source_clk(i2c->dev, SOC_MOD_CLK_APB); /*!< I2C source clock from APB, 80M*/
+  }
+#elif SOC_I2C_SUPPORT_XTAL
+  i2c_ll_master_cal_bus_clk(XTAL_CLK_FREQ, clk_speed, &clk_cal);
+  I2C_CLOCK_SRC_ATOMIC() {
+    i2c_ll_set_source_clk(i2c->dev, SOC_MOD_CLK_XTAL); /*!< I2C source clock from XTAL, 40M */
+  }
+#endif
+  i2c_ll_set_txfifo_empty_thr(i2c->dev, a);
+  i2c_ll_set_rxfifo_full_thr(i2c->dev, SOC_I2C_FIFO_LEN - a);
+  i2c_ll_master_set_bus_timing(i2c->dev, &clk_cal);
+  i2c_ll_master_set_filter(i2c->dev, 3);
+  return true;
+}
+
+static void i2c_slave_delay_us(uint64_t us) {
+  uint64_t m = esp_timer_get_time();
+  if (us) {
+    uint64_t e = (m + us);
+    if (m > e) {  //overflow
+      while ((uint64_t)esp_timer_get_time() > e);
+    }
+    while ((uint64_t)esp_timer_get_time() < e);
+  }
+}
+
+static void i2c_slave_gpio_mode(int8_t pin, gpio_mode_t mode) {
+  gpio_config_t conf = {
+    .pin_bit_mask = 1LL << pin, .mode = mode, .pull_up_en = GPIO_PULLUP_ENABLE, .pull_down_en = GPIO_PULLDOWN_DISABLE, .intr_type = GPIO_INTR_DISABLE
+  };
+  gpio_config(&conf);
+}
+
+static bool i2c_slave_check_line_state(int8_t sda, int8_t scl) {
+  if (sda < 0 || scl < 0) {
+    return false;  //return false since there is nothing to do
+  }
+  // if the bus is not 'clear' try the cycling SCL until SDA goes High or 9 cycles
+  gpio_set_level(sda, 1);
+  gpio_set_level(scl, 1);
+  i2c_slave_gpio_mode(sda, GPIO_MODE_INPUT | GPIO_MODE_DEF_OD);
+  i2c_slave_gpio_mode(scl, GPIO_MODE_INPUT | GPIO_MODE_DEF_OD);
+  gpio_set_level(scl, 1);
+
+  if (!gpio_get_level(sda) || !gpio_get_level(scl)) {  // bus in busy state
+    log_w("invalid state sda(%d)=%d, scl(%d)=%d", sda, gpio_get_level(sda), scl, gpio_get_level(scl));
+    for (uint8_t a = 0; a < 9; a++) {
+      i2c_slave_delay_us(5);
+      if (gpio_get_level(sda) && gpio_get_level(scl)) {  // bus recovered
+        log_w("Recovered after %d Cycles", a);
+        gpio_set_level(sda, 0);  // start
+        i2c_slave_delay_us(5);
+        for (uint8_t a = 0; a < 9; a++) {
+          gpio_set_level(scl, 1);
+          i2c_slave_delay_us(5);
+          gpio_set_level(scl, 0);
+          i2c_slave_delay_us(5);
+        }
+        gpio_set_level(scl, 1);
+        i2c_slave_delay_us(5);
+        gpio_set_level(sda, 1);  // stop
+        break;
+      }
+      gpio_set_level(scl, 0);
+      i2c_slave_delay_us(5);
+      gpio_set_level(scl, 1);
+    }
+  }
+
+  if (!gpio_get_level(sda) || !gpio_get_level(scl)) {  // bus in busy state
+    log_e("Bus Invalid State, Can't init sda=%d, scl=%d", gpio_get_level(sda), gpio_get_level(scl));
+    return false;  // bus is busy
+  }
+  return true;
+}
+
+static bool i2c_slave_attach_gpio(i2c_slave_struct_t *i2c, int8_t sda, int8_t scl) {
+  if (i2c == NULL) {
+    log_e("no control block");
+    return false;
+  }
+
+  if ((sda < 0) || (scl < 0)) {
+    log_e("bad pins sda=%d, scl=%d", sda, scl);
+    return false;
+  }
+
+  i2c->scl = scl;
+  gpio_set_level(scl, 1);
+  i2c_slave_gpio_mode(scl, GPIO_MODE_INPUT_OUTPUT_OD);
+  gpio_matrix_out(scl, I2C_SCL_IDX(i2c->num), false, false);
+  gpio_matrix_in(scl, I2C_SCL_IDX(i2c->num), false);
+
+  i2c->sda = sda;
+  gpio_set_level(sda, 1);
+  i2c_slave_gpio_mode(sda, GPIO_MODE_INPUT_OUTPUT_OD);
+  gpio_matrix_out(sda, I2C_SDA_IDX(i2c->num), false, false);
+  gpio_matrix_in(sda, I2C_SDA_IDX(i2c->num), false);
+
+  return true;
+}
+
+static bool i2c_slave_detach_gpio(i2c_slave_struct_t *i2c) {
+  if (i2c == NULL) {
+    log_e("no control Block");
+    return false;
+  }
+  if (i2c->scl >= 0) {
+    gpio_matrix_out(i2c->scl, 0x100, false, false);
+    gpio_matrix_in(0x30, I2C_SCL_IDX(i2c->num), false);
+    i2c_slave_gpio_mode(i2c->scl, GPIO_MODE_INPUT);
+    i2c->scl = -1;  // un attached
+  }
+  if (i2c->sda >= 0) {
+    gpio_matrix_out(i2c->sda, 0x100, false, false);
+    gpio_matrix_in(0x30, I2C_SDA_IDX(i2c->num), false);
+    i2c_slave_gpio_mode(i2c->sda, GPIO_MODE_INPUT);
+    i2c->sda = -1;  // un attached
+  }
+  return true;
+}
+
+static bool i2c_slave_send_event(i2c_slave_struct_t *i2c, i2c_slave_queue_event_t *event) {
+  bool pxHigherPriorityTaskWoken = false;
+  if (i2c->event_queue) {
+    if (xQueueSendFromISR(i2c->event_queue, event, (BaseType_t *const)&pxHigherPriorityTaskWoken) != pdTRUE) {
+      //log_e("event_queue_full");
+    }
+  }
+  return pxHigherPriorityTaskWoken;
+}
+
+static bool i2c_slave_handle_tx_fifo_empty(i2c_slave_struct_t *i2c) {
+  bool pxHigherPriorityTaskWoken = false;
+  uint32_t d = 0, moveCnt = 0;
+  i2c_ll_get_txfifo_len(i2c->dev, &moveCnt);
+  while (moveCnt > 0) {  // read tx queue until Fifo is full or queue is empty
+    if (xQueueReceiveFromISR(i2c->tx_queue, &d, (BaseType_t *const)&pxHigherPriorityTaskWoken) == pdTRUE) {
+      i2c_ll_write_txfifo(i2c->dev, (uint8_t *)&d, 1);
+      moveCnt--;
+    } else {
+      i2c_ll_slave_disable_tx_it(i2c->dev);
+      break;
+    }
+  }
+  return pxHigherPriorityTaskWoken;
+}
+
+static bool i2c_slave_handle_rx_fifo_full(i2c_slave_struct_t *i2c, uint32_t len) {
+#if I2C_SLAVE_USE_RX_QUEUE
+  uint32_t d = 0;
+#else
+  uint8_t data[SOC_I2C_FIFO_LEN];
+#endif
+  bool pxHigherPriorityTaskWoken = false;
+#if I2C_SLAVE_USE_RX_QUEUE
+  while (len > 0) {
+    i2c_ll_read_rxfifo(i2c->dev, (uint8_t *)&d, 1);
+    if (xQueueSendFromISR(i2c->rx_queue, &d, (BaseType_t *const)&pxHigherPriorityTaskWoken) != pdTRUE) {
+      log_e("rx_queue_full");
+    } else {
+      i2c->rx_data_count++;
+    }
+    if (--len == 0) {
+      len = i2c_ll_get_rxfifo_cnt(i2c->dev);
+    }
+#else
+  if (len) {
+    i2c_ll_read_rxfifo(i2c->dev, data, len);
+    if (xRingbufferSendFromISR(i2c->rx_ring_buf, (void *)data, len, (BaseType_t *const)&pxHigherPriorityTaskWoken) != pdTRUE) {
+      log_e("rx_ring_buf_full");
+    } else {
+      i2c->rx_data_count += len;
+    }
+#endif
+  }
+  return pxHigherPriorityTaskWoken;
+}
+
+static void i2c_slave_isr_handler(void *arg) {
+  bool pxHigherPriorityTaskWoken = false;
+  i2c_slave_struct_t *i2c = (i2c_slave_struct_t *)arg;  // recover data
+
+  uint32_t activeInt = 0;
+  i2c_ll_get_intr_mask(i2c->dev, &activeInt);
+  i2c_ll_clear_intr_mask(i2c->dev, activeInt);
+  uint32_t rx_fifo_len = 0;
+  i2c_ll_get_rxfifo_cnt(i2c->dev, &rx_fifo_len);
+  bool slave_rw = i2c_ll_slave_rw(i2c->dev);
+
+  if (activeInt & I2C_RXFIFO_WM_INT_ENA) {  // RX FiFo Full
+    pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo_full(i2c, rx_fifo_len);
+    i2c_ll_slave_enable_rx_it(i2c->dev);  //is this necessary?
+  }
+
+  if (activeInt & I2C_TRANS_COMPLETE_INT_ENA) {  // STOP
+    if (rx_fifo_len) {                           //READ RX FIFO
+      pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo_full(i2c, rx_fifo_len);
+    }
+    if (i2c->rx_data_count) {  //WRITE or RepeatedStart
+      //SEND RX Event
+      i2c_slave_queue_event_t event;
+      event.event = I2C_SLAVE_EVT_RX;
+      event.stop = !slave_rw;
+      event.param = i2c->rx_data_count;
+      pxHigherPriorityTaskWoken |= i2c_slave_send_event(i2c, &event);
+      //Zero RX count
+      i2c->rx_data_count = 0;
+    }
+    if (slave_rw) {  // READ
+#if CONFIG_IDF_TARGET_ESP32
+      if (i2c->dev->status_reg.scl_main_state_last == 6) {
+        //SEND TX Event
+        i2c_slave_queue_event_t event;
+        event.event = I2C_SLAVE_EVT_TX;
+        pxHigherPriorityTaskWoken |= i2c_slave_send_event(i2c, &event);
+      }
+#else
+      //reset TX data
+      i2c_ll_txfifo_rst(i2c->dev);
+      uint8_t d;
+      while (xQueueReceiveFromISR(i2c->tx_queue, &d, (BaseType_t *const)&pxHigherPriorityTaskWoken) == pdTRUE);  //flush partial write
+#endif
+    }
+  }
+
+#ifndef CONFIG_IDF_TARGET_ESP32
+  if (activeInt & I2C_SLAVE_STRETCH_INT_ENA) {  // STRETCH
+    i2c_stretch_cause_t cause = i2c_ll_stretch_cause(i2c->dev);
+    if (cause == I2C_STRETCH_CAUSE_MASTER_READ) {
+      //on C3 RX data disappears with repeated start, so we need to get it here
+      if (rx_fifo_len) {
+        pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo_full(i2c, rx_fifo_len);
+      }
+      //SEND TX Event
+      i2c_slave_queue_event_t event;
+      event.event = I2C_SLAVE_EVT_TX;
+      pxHigherPriorityTaskWoken |= i2c_slave_send_event(i2c, &event);
+      //will clear after execution
+    } else if (cause == I2C_STRETCH_CAUSE_TX_FIFO_EMPTY) {
+      pxHigherPriorityTaskWoken |= i2c_slave_handle_tx_fifo_empty(i2c);
+      i2c_ll_stretch_clr(i2c->dev);
+    } else if (cause == I2C_STRETCH_CAUSE_RX_FIFO_FULL) {
+      pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo_full(i2c, rx_fifo_len);
+      i2c_ll_stretch_clr(i2c->dev);
+    }
+  }
+#endif
+
+  if (activeInt & I2C_TXFIFO_WM_INT_ENA) {  // TX FiFo Empty
+    pxHigherPriorityTaskWoken |= i2c_slave_handle_tx_fifo_empty(i2c);
+  }
+
+  if (pxHigherPriorityTaskWoken) {
+    portYIELD_FROM_ISR();
+  }
+}
+
+static size_t i2c_slave_read_rx(i2c_slave_struct_t *i2c, uint8_t *data, size_t len) {
+  if (!len) {
+    return 0;
+  }
+#if I2C_SLAVE_USE_RX_QUEUE
+  uint8_t d = 0;
+  BaseType_t res = pdTRUE;
+  for (size_t i = 0; i < len; i++) {
+    if (data) {
+      res = xQueueReceive(i2c->rx_queue, &data[i], 0);
+    } else {
+      res = xQueueReceive(i2c->rx_queue, &d, 0);
+    }
+    if (res != pdTRUE) {
+      log_e("Read Queue(%u) Failed", i);
+      len = i;
+      break;
+    }
+  }
+  return (data) ? len : 0;
+#else
+  size_t dlen = 0, to_read = len, so_far = 0, available = 0;
+  uint8_t *rx_data = NULL;
+
+  vRingbufferGetInfo(i2c->rx_ring_buf, NULL, NULL, NULL, NULL, &available);
+  if (available < to_read) {
+    log_e("Less available than requested. %u < %u", available, len);
+    to_read = available;
+  }
+
+  while (to_read) {
+    dlen = 0;
+    rx_data = (uint8_t *)xRingbufferReceiveUpTo(i2c->rx_ring_buf, &dlen, 0, to_read);
+    if (!rx_data) {
+      log_e("Receive %u Failed", to_read);
+      return so_far;
+    }
+    if (data) {
+      memcpy(data + so_far, rx_data, dlen);
+    }
+    vRingbufferReturnItem(i2c->rx_ring_buf, rx_data);
+    so_far += dlen;
+    to_read -= dlen;
+  }
+  return (data) ? so_far : 0;
+#endif
+}
+
+static void i2c_slave_task(void *pv_args) {
+  i2c_slave_struct_t *i2c = (i2c_slave_struct_t *)pv_args;
+  i2c_slave_queue_event_t event;
+  size_t len = 0;
+  bool stop = false;
+  uint8_t *data = NULL;
+  for (;;) {
+    if (xQueueReceive(i2c->event_queue, &event, portMAX_DELAY) == pdTRUE) {
+      // Write
+      if (event.event == I2C_SLAVE_EVT_RX) {
+        len = event.param;
+        stop = event.stop;
+        data = (len > 0) ? (uint8_t *)malloc(len) : NULL;
+
+        if (len && data == NULL) {
+          log_e("Malloc (%u) Failed", len);
+        }
+        len = i2c_slave_read_rx(i2c, data, len);
+        if (i2c->receive_callback) {
+          i2c->receive_callback(i2c->num, data, len, stop, i2c->arg);
+        }
+        free(data);
+
+        // Read
+      } else if (event.event == I2C_SLAVE_EVT_TX) {
+        if (i2c->request_callback) {
+          i2c->request_callback(i2c->num, i2c->arg);
+        }
+        i2c_ll_stretch_clr(i2c->dev);
+      }
+    }
+  }
+  vTaskDelete(NULL);
+}
+
+static bool i2cSlaveDetachBus(void *bus_i2c_num) {
+  uint8_t num = (int)bus_i2c_num - 1;
+  i2c_slave_struct_t *i2c = &_i2c_bus_array[num];
+  if (i2c->scl == -1 && i2c->sda == -1) {
+    return true;
+  }
+  esp_err_t err = i2cSlaveDeinit(num);
+  if (err != ESP_OK) {
+    log_e("i2cSlaveDeinit failed with error: %d", err);
+    return false;
+  }
+  return true;
+}
+
+#endif /* SOC_I2C_SUPPORT_SLAVE */
diff --git a/cores/esp32/esp32-hal-i2c-slave.h b/cores/esp32/esp32-hal-i2c-slave.h
new file mode 100644
index 00000000000..787656599da
--- /dev/null
+++ b/cores/esp32/esp32-hal-i2c-slave.h
@@ -0,0 +1,40 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_I2C_SUPPORT_SLAVE
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stdint.h"
+#include "stddef.h"
+#include "esp_err.h"
+
+typedef void (*i2c_slave_request_cb_t)(uint8_t num, void *arg);
+typedef void (*i2c_slave_receive_cb_t)(uint8_t num, uint8_t *data, size_t len, bool stop, void *arg);
+esp_err_t i2cSlaveAttachCallbacks(uint8_t num, i2c_slave_request_cb_t request_callback, i2c_slave_receive_cb_t receive_callback, void *arg);
+
+esp_err_t i2cSlaveInit(uint8_t num, int sda, int scl, uint16_t slaveID, uint32_t frequency, size_t rx_len, size_t tx_len);
+esp_err_t i2cSlaveDeinit(uint8_t num);
+size_t i2cSlaveWrite(uint8_t num, const uint8_t *buf, uint32_t len, uint32_t timeout_ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SOC_I2C_SUPPORT_SLAVE */
diff --git a/cores/esp32/esp32-hal-i2c.c b/cores/esp32/esp32-hal-i2c.c
index d50ce4cc029..71c8ae1c428 100644
--- a/cores/esp32/esp32-hal-i2c.c
+++ b/cores/esp32/esp32-hal-i2c.c
@@ -13,1766 +13,423 @@
 // limitations under the License.
 
 #include "esp32-hal-i2c.h"
+
+#if SOC_I2C_SUPPORTED
+#include "esp_idf_version.h"
+#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 4, 0)
 #include "esp32-hal.h"
+#if !CONFIG_DISABLE_HAL_LOCKS
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "freertos/semphr.h"
-#include "freertos/event_groups.h"
-#include "rom/ets_sys.h"
-#include "driver/periph_ctrl.h"
-#include "soc/i2c_reg.h"
-#include "soc/i2c_struct.h"
-#include "soc/dport_reg.h"
+#endif
 #include "esp_attr.h"
-#include "esp32-hal-cpu.h" // cpu clock change support 31DEC2018
-//#define I2C_DEV(i)   (volatile i2c_dev_t *)((i)?DR_REG_I2C1_EXT_BASE:DR_REG_I2C_EXT_BASE)
-//#define I2C_DEV(i)   ((i2c_dev_t *)(REG_I2C_BASE(i)))
-#define I2C_SCL_IDX(p)  ((p==0)?I2CEXT0_SCL_OUT_IDX:((p==1)?I2CEXT1_SCL_OUT_IDX:0))
-#define I2C_SDA_IDX(p) ((p==0)?I2CEXT0_SDA_OUT_IDX:((p==1)?I2CEXT1_SDA_OUT_IDX:0))
-
-#define DR_REG_I2C_EXT_BASE_FIXED               0x60013000
-#define DR_REG_I2C1_EXT_BASE_FIXED              0x60027000
-
-/* Stickbreaker ISR mode debug support
-
-ENABLE_I2C_DEBUG_BUFFER
-  Enable debug interrupt history buffer, fifoTx history buffer.
-  Setting this define will result in 2570 bytes of RAM being used whenever CORE_DEBUG_LEVEL
-  is higher than WARNING. Unless you are debugging a problem in the I2C subsystem,
-  I would recommend you leave it commented out.
-  */
-
-//#define ENABLE_I2C_DEBUG_BUFFER
-
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER)
-#define INTBUFFMAX 64
-#define FIFOMAX 512
-static uint32_t intBuff[INTBUFFMAX][3][2];
-static uint32_t intPos[2]= {0,0};
-static uint16_t fifoBuffer[FIFOMAX];
-static uint16_t fifoPos = 0;
+#include "esp_system.h"
+#include "soc/soc_caps.h"
+#include "soc/i2c_periph.h"
+#include "hal/i2c_hal.h"
+#include "hal/i2c_ll.h"
+#include "driver/i2c.h"
+#include "esp32-hal-periman.h"
+#include "esp_private/periph_ctrl.h"
+
+#if SOC_PERIPH_CLK_CTRL_SHARED
+#define I2C_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define I2C_CLOCK_SRC_ATOMIC()
 #endif
 
-// start from tools/sdk/include/soc/soc/i2c_struct.h
-
-typedef union {
-    struct {
-        uint32_t byte_num:      8;              /*Byte_num represent the number of data need to be send or data need to be received.*/
-        uint32_t ack_en:        1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-        uint32_t ack_exp:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-        uint32_t ack_val:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-        uint32_t op_code:       3;              /*op_code is the command  0：RSTART   1：WRITE  2：READ  3：STOP . 4:END.*/
-        uint32_t reserved14:   17;
-        uint32_t done:  1;                      /*When command0 is done in I2C Master mode  this bit changes to high level.*/
-    };
-    uint32_t val;
-} I2C_COMMAND_t;
-
-typedef union {
-    struct {
-        uint32_t rx_fifo_full_thrhd: 5;
-        uint32_t tx_fifo_empty_thrhd:5;         //Config tx_fifo empty threhd value when using apb fifo access * /
-        uint32_t nonfifo_en:         1;         //Set this bit to enble apb nonfifo access. * /
-        uint32_t fifo_addr_cfg_en:   1;         //When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram. * /
-        uint32_t rx_fifo_rst:        1;         //Set this bit to reset rx fifo when using apb fifo access. * /
-        // chuck while this bit is 1, the RX fifo is held in REST, Toggle it * /
-        uint32_t tx_fifo_rst:        1;         //Set this bit to reset tx fifo when using apb fifo access. * /
-        // chuck while this bit is 1, the TX fifo is held in REST, Toggle it * /
-        uint32_t nonfifo_rx_thres:   6;         //when I2C receives more than nonfifo_rx_thres data  it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.* /
-        uint32_t nonfifo_tx_thres:   6;         //when I2C sends more than nonfifo_tx_thres data  it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. * /
-        uint32_t reserved26:         6;
-    };
-    uint32_t val;
-} I2C_FIFO_CONF_t;
-
-typedef union {
-        struct {
-            uint32_t rx_fifo_start_addr: 5;         /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
-            uint32_t rx_fifo_end_addr:   5;         /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
-            uint32_t tx_fifo_start_addr: 5;         /*This is the offset address of the first  sending data as described in nonfifo_tx_thres register.*/
-            uint32_t tx_fifo_end_addr:   5;         /*This is the offset address of the last  sending data as described in nonfifo_tx_thres register.*/
-            uint32_t reserved20:        12;
-        };
-        uint32_t val;
-    } I2C_FIFO_ST_t;
-   
-// end from tools/sdk/include/soc/soc/i2c_struct.h
-
-// sync between dispatch(i2cProcQueue) and worker(i2c_isr_handler_default)
-typedef enum {
-    //I2C_NONE=0,
-    I2C_STARTUP=1,
-    I2C_RUNNING,
-    I2C_DONE
-} I2C_STAGE_t;
-
-typedef enum {
-    I2C_NONE=0,
-    I2C_MASTER,
-    I2C_SLAVE,
-    I2C_MASTERSLAVE
-} I2C_MODE_t;
-
-// internal Error condition
-typedef enum {
-    //  I2C_NONE=0,
-    I2C_OK=1,
-    I2C_ERROR,
-    I2C_ADDR_NAK,
-    I2C_DATA_NAK,
-    I2C_ARBITRATION,
-    I2C_TIMEOUT
-} I2C_ERROR_t;
-
-// i2c_event bits for EVENTGROUP bits
-// needed to minimize change events, FreeRTOS Daemon overload, so ISR will only set values
-// on Exit.  Dispatcher will set bits for each dq before/after ISR completion
-#define EVENT_ERROR_NAK (BIT(0))
-#define EVENT_ERROR     (BIT(1))
-#define EVENT_ERROR_BUS_BUSY  (BIT(2))
-#define EVENT_RUNNING   (BIT(3))
-#define EVENT_DONE      (BIT(4))
-#define EVENT_IN_END    (BIT(5))
-#define EVENT_ERROR_PREV  (BIT(6))
-#define EVENT_ERROR_TIMEOUT   (BIT(7))
-#define EVENT_ERROR_ARBITRATION (BIT(8))
-#define EVENT_ERROR_DATA_NAK  (BIT(9))
-#define EVENT_MASK 0x3F
-
-// control record for each dq entry
-typedef union {
-    struct {
-        uint32_t  addr: 16; // I2C address, if 10bit must have 0x7800 mask applied, else 8bit
-        uint32_t  mode:         1; // transaction direction 0 write, 1 read
-        uint32_t  stop:         1; // sendStop 0 no, 1 yes
-        uint32_t  startCmdSent: 1; // START cmd has been added to command[]
-        uint32_t  addrCmdSent:  1; // addr WRITE cmd has been added to command[]
-        uint32_t  dataCmdSent:  1; // all necessary DATA(READ/WRITE) cmds added to command[]
-        uint32_t  stopCmdSent:  1; // completed all necessary commands
-        uint32_t  addrReq:      2; // number of addr bytes need to send address
-        uint32_t  addrSent:     2; // number of addr bytes added to FIFO
-        uint32_t  reserved_31:  6;
-    };
-    uint32_t val;
-} I2C_DATA_CTRL_t;
+#if !SOC_RCC_IS_INDEPENDENT
+#define I2C_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define I2C_RCC_ATOMIC()
+#endif
 
-// individual dq element
-typedef struct {
-    uint8_t *data;           // data pointer for read/write buffer
-    uint16_t length;         // size of data buffer
-    uint16_t position;       // current position for next char in buffer (<length)
-    uint16_t cmdBytesNeeded; // used to control number of I2C_COMMAND_t blocks added to queue
-    I2C_DATA_CTRL_t ctrl;
-    EventGroupHandle_t queueEvent;  // optional user supplied for Async feedback EventBits
-} I2C_DATA_QUEUE_t;
+#if SOC_I2C_SUPPORT_APB || SOC_I2C_SUPPORT_XTAL
+#include "esp_private/esp_clk.h"
+#endif
+#if SOC_I2C_SUPPORT_RTC
+#include "clk_ctrl_os.h"
+#endif
 
-struct i2c_struct_t {
-    i2c_dev_t * dev;
+typedef volatile struct {
+  bool initialized;
+  uint32_t frequency;
 #if !CONFIG_DISABLE_HAL_LOCKS
-    xSemaphoreHandle lock;
+  SemaphoreHandle_t lock;
 #endif
-    uint8_t num;
-    int8_t sda;
-    int8_t scl;
-    I2C_MODE_t mode;
-    I2C_STAGE_t stage;
-    I2C_ERROR_t error;
-    EventGroupHandle_t i2c_event; // a way to monitor ISR process
-    // maybe use it to trigger callback for OnRequest()
-    intr_handle_t intr_handle;       /*!< I2C interrupt handle*/
-    I2C_DATA_QUEUE_t * dq;
-    uint16_t queueCount; // number of dq entries in queue.
-    uint16_t queuePos; // current queue that still has or needs data (out/in)
-    int16_t  errorByteCnt;  // byte pos where error happened, -1 devId, 0..(length-1) data
-    uint16_t errorQueue; // errorByteCnt is in this queue,(for error locus)
-    uint32_t exitCode;
-    uint32_t debugFlags;
-};
+  int8_t scl;
+  int8_t sda;
 
-enum {
-    I2C_CMD_RSTART,
-    I2C_CMD_WRITE,
-    I2C_CMD_READ,
-    I2C_CMD_STOP,
-    I2C_CMD_END
-};
+} i2c_bus_t;
 
-#if CONFIG_DISABLE_HAL_LOCKS
-#define I2C_MUTEX_LOCK()
-#define I2C_MUTEX_UNLOCK()
+static i2c_bus_t bus[SOC_I2C_NUM];
 
-static i2c_t _i2c_bus_array[2] = {
-    {(volatile i2c_dev_t *)(DR_REG_I2C_EXT_BASE_FIXED), 0, -1, -1,I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0},
-    {(volatile i2c_dev_t *)(DR_REG_I2C1_EXT_BASE_FIXED), 1, -1, -1,I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0}
-};
-#else
-#define I2C_MUTEX_LOCK()    do {} while (xSemaphoreTakeRecursive(i2c->lock, portMAX_DELAY) != pdPASS)
-#define I2C_MUTEX_UNLOCK()  xSemaphoreGiveRecursive(i2c->lock)
-
-static i2c_t _i2c_bus_array[2] = {
-    {(volatile i2c_dev_t *)(DR_REG_I2C_EXT_BASE_FIXED), NULL, 0, -1, -1, I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0,0},
-    {(volatile i2c_dev_t *)(DR_REG_I2C1_EXT_BASE_FIXED), NULL, 1, -1, -1,I2C_NONE,I2C_NONE,I2C_ERROR_OK,NULL,NULL,NULL,0,0,0,0,0,0}
-};
+static bool i2cDetachBus(void *bus_i2c_num) {
+  uint8_t i2c_num = (int)bus_i2c_num - 1;
+  if (!bus[i2c_num].initialized) {
+    return true;
+  }
+  esp_err_t err = i2cDeinit(i2c_num);
+  if (err != ESP_OK) {
+    log_e("i2cDeinit failed with error: %d", err);
+    return false;
+  }
+  return true;
+}
+
+bool i2cIsInit(uint8_t i2c_num) {
+  if (i2c_num >= SOC_I2C_NUM) {
+    return false;
+  }
+  return bus[i2c_num].initialized;
+}
+
+esp_err_t i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency) {
+  esp_err_t ret = ESP_OK;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (bus[i2c_num].lock == NULL) {
+    bus[i2c_num].lock = xSemaphoreCreateMutex();
+    if (bus[i2c_num].lock == NULL) {
+      log_e("xSemaphoreCreateMutex failed");
+      return ESP_ERR_NO_MEM;
+    }
+  }
+  //acquire lock
+  if (xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ESP_FAIL;
+  }
 #endif
-
-/*
- * index     - command index (0 to 15)
- * op_code   - is the command
- * byte_num  - This register is to store the amounts of data that is read and written. byte_num in RSTART, STOP, END is null.
- * ack_val   - Each data byte is terminated by an ACK bit used to set the bit level.
- * ack_exp   - This bit is to set an expected ACK value for the transmitter.
- * ack_check - This bit is to decide whether the transmitter checks ACK bit. 1 means yes and 0 means no.
- * */
-
-
-/* Stickbreaker ISR mode debug support
- */
-static void IRAM_ATTR i2cDumpCmdQueue(i2c_t *i2c)
-{
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR)&&(defined ENABLE_I2C_DEBUG_BUFFER)
-    static const char * const cmdName[] ={"RSTART","WRITE","READ","STOP","END"};
-    uint8_t i=0;
-    while(i<16) {
-        I2C_COMMAND_t c;
-        c.val=i2c->dev->command[i].val;
-        log_e("[%2d]\t%c\t%s\tval[%d]\texp[%d]\ten[%d]\tbytes[%d]",i,(c.done?'Y':'N'),
-              cmdName[c.op_code],
-              c.ack_val,
-              c.ack_exp,
-              c.ack_en,
-              c.byte_num);
-        i++;
-    }
+  if (bus[i2c_num].initialized) {
+    log_e("bus is already initialized");
+    ret = ESP_FAIL;
+    goto init_fail;
+  }
+
+  if (!frequency) {
+    frequency = 100000UL;
+  } else if (frequency > 1000000UL) {
+    frequency = 1000000UL;
+  }
+
+  perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SDA, i2cDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_I2C_MASTER_SCL, i2cDetachBus);
+
+  if (!perimanClearPinBus(sda) || !perimanClearPinBus(scl)) {
+    ret = ESP_FAIL;
+    goto init_fail;
+  }
+
+  log_i("Initializing I2C Master: sda=%d scl=%d freq=%d", sda, scl, frequency);
+
+  i2c_config_t conf = {};
+  conf.mode = I2C_MODE_MASTER;
+  conf.scl_io_num = (gpio_num_t)scl;
+  conf.sda_io_num = (gpio_num_t)sda;
+  conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
+  conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
+  conf.master.clk_speed = frequency;
+  conf.clk_flags = I2C_SCLK_SRC_FLAG_FOR_NOMAL;  //Any one clock source that is available for the specified frequency may be chosen
+
+  ret = i2c_param_config((i2c_port_t)i2c_num, &conf);
+  if (ret != ESP_OK) {
+    log_e("i2c_param_config failed");
+  } else {
+    ret = i2c_driver_install((i2c_port_t)i2c_num, conf.mode, 0, 0, 0);
+    if (ret != ESP_OK) {
+      log_e("i2c_driver_install failed");
+    } else {
+      bus[i2c_num].initialized = true;
+      bus[i2c_num].frequency = frequency;
+      bus[i2c_num].scl = scl;
+      bus[i2c_num].sda = sda;
+      //Clock Stretching Timeout: 20b:esp32, 5b:esp32-c3, 24b:esp32-s2
+      i2c_set_timeout((i2c_port_t)i2c_num, I2C_LL_MAX_TIMEOUT);
+      if (!perimanSetPinBus(sda, ESP32_BUS_TYPE_I2C_MASTER_SDA, (void *)(i2c_num + 1), i2c_num, -1)
+          || !perimanSetPinBus(scl, ESP32_BUS_TYPE_I2C_MASTER_SCL, (void *)(i2c_num + 1), i2c_num, -1)) {
+#if !CONFIG_DISABLE_HAL_LOCKS
+        //release lock so that i2cDetachBus can execute i2cDeinit
+        xSemaphoreGive(bus[i2c_num].lock);
 #endif
-}
-
-/* Stickbreaker ISR mode debug support
- */
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)
-static void i2cDumpDqData(i2c_t * i2c)
-{
-#if defined (ENABLE_I2C_DEBUG_BUFFER)
-    uint16_t a=0;
-    char buff[140];
-    I2C_DATA_QUEUE_t *tdq;
-    int digits=0,lenDigits=0;
-    a = i2c->queueCount;
-    while(a>0) {
-        digits++;
-        a /= 10;
-    }
-    while(a<i2c->queueCount) { // find maximum number of len decimal digits for formatting
-        if (i2c->dq[a].length > lenDigits ) lenDigits = i2c->dq[a].length;
-        a++;
-    }
-    a=0;
-    while(lenDigits>0){
-      a++;
-      lenDigits /= 10;
-    }
-    lenDigits = a;
-    a = 0;
-    while(a<i2c->queueCount) {
-        tdq=&i2c->dq[a];
-        char buf1[10],buf2[10];
-        sprintf(buf1,"%0*d",lenDigits,tdq->length);
-        sprintf(buf2,"%0*d",lenDigits,tdq->position);
-        log_i("[%0*d] %sbit %x %c %s buf@=%p, len=%s, pos=%s, ctrl=%d%d%d%d%d",digits,a,
-        (tdq->ctrl.addr>0x100)?"10":"7",
-        (tdq->ctrl.addr>0x100)?(((tdq->ctrl.addr&0x600)>>1)|(tdq->ctrl.addr&0xff)):(tdq->ctrl.addr>>1),
-        (tdq->ctrl.mode)?'R':'W',
-        (tdq->ctrl.stop)?"STOP":"",
-        tdq->data,
-        buf1,buf2,
-        tdq->ctrl.startCmdSent,tdq->ctrl.addrCmdSent,tdq->ctrl.dataCmdSent,(tdq->ctrl.stop)?tdq->ctrl.stopCmdSent:0,tdq->ctrl.addrSent
-        );
-        uint16_t offset = 0;
-        while(offset<tdq->length) {
-            memset(buff,' ',140);
-            buff[139]='\0';
-            uint16_t i = 0,j;
-            j=sprintf(buff,"0x%04x: ",offset);
-            while((i<32)&&(offset < tdq->length)) {
-                char ch = tdq->data[offset];
-                sprintf((char*)&buff[(i*3)+41],"%02x ",ch);
-                if((ch<32)||(ch>126)) {
-                    ch='.';
-                }
-                j+=sprintf((char*)&buff[j],"%c",ch);
-                buff[j]=' ';
-                i++;
-                offset++;
-            }
-            log_i("%s",buff);
-        }
-        a++;
+        i2cDetachBus((void *)(i2c_num + 1));
+        return ESP_FAIL;
+      }
     }
-#else
-    log_i("Debug Buffer not Enabled");
+  }
+init_fail:
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
 #endif
+  return ret;
 }
+
+esp_err_t i2cDeinit(uint8_t i2c_num) {
+  esp_err_t err = ESP_FAIL;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return err;
+  }
 #endif
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
-static void i2cDumpI2c(i2c_t * i2c)
-{
-    log_e("i2c=%p",i2c);
-    log_i("dev=%p date=%p",i2c->dev,i2c->dev->date);
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+  } else {
+    err = i2c_driver_delete((i2c_port_t)i2c_num);
+    if (err == ESP_OK) {
+      bus[i2c_num].initialized = false;
+      perimanClearPinBus(bus[i2c_num].scl);
+      perimanClearPinBus(bus[i2c_num].sda);
+      bus[i2c_num].scl = -1;
+      bus[i2c_num].sda = -1;
+    }
+  }
 #if !CONFIG_DISABLE_HAL_LOCKS
-    log_i("lock=%p",i2c->lock);
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
 #endif
-    log_i("num=%d",i2c->num);
-    log_i("mode=%d",i2c->mode);
-    log_i("stage=%d",i2c->stage);
-    log_i("error=%d",i2c->error);
-    log_i("event=%p bits=%x",i2c->i2c_event,(i2c->i2c_event)?xEventGroupGetBits(i2c->i2c_event):0);
-    log_i("intr_handle=%p",i2c->intr_handle);
-    log_i("dq=%p",i2c->dq);
-    log_i("queueCount=%d",i2c->queueCount);
-    log_i("queuePos=%d",i2c->queuePos);
-    log_i("errorByteCnt=%d",i2c->errorByteCnt);
-    log_i("errorQueue=%d",i2c->errorQueue);
-    log_i("debugFlags=0x%08X",i2c->debugFlags);
-    if(i2c->dq) {
-        i2cDumpDqData(i2c);
-    }
+  return err;
 }
-#endif
 
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)  
-static void i2cDumpInts(uint8_t num)
-{
-#if defined (ENABLE_I2C_DEBUG_BUFFER)
-    uint32_t b;
-    log_i("%u row\tcount\tINTR\tTX\tRX\tTick ",num);
-    for(uint32_t a=1; a<=INTBUFFMAX; a++) {
-        b=(a+intPos[num])%INTBUFFMAX;
-        if(intBuff[b][0][num]!=0) {
-            log_i("[%02d]\t0x%04x\t0x%04x\t0x%04x\t0x%04x\t0x%08x",b,((intBuff[b][0][num]>>16)&0xFFFF),(intBuff[b][0][num]&0xFFFF),((intBuff[b][1][num]>>16)&0xFFFF),(intBuff[b][1][num]&0xFFFF),intBuff[b][2][num]);
-        }
-    }
-#else
-    log_i("Debug Buffer not Enabled");
-#endif
-}
+esp_err_t i2cWrite(uint8_t i2c_num, uint16_t address, const uint8_t *buff, size_t size, uint32_t timeOutMillis) {
+  esp_err_t ret = ESP_FAIL;
+  i2c_cmd_handle_t cmd = NULL;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ret;
+  }
 #endif
-
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER)
-static void IRAM_ATTR i2cDumpStatus(i2c_t * i2c){
-    typedef union {
-        struct {
-            uint32_t ack_rec:             1;        /*This register stores the value of ACK bit.*/
-            uint32_t slave_rw:            1;        /*when in slave mode  1：master read slave  0: master write slave.*/
-            uint32_t time_out:            1;        /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/
-            uint32_t arb_lost:            1;        /*when I2C lost control of SDA line  this register changes to high level.*/
-            uint32_t bus_busy:            1;        /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
-            uint32_t slave_addressed:     1;        /*when configured as i2c slave  and the address send by master is equal to slave's address  then this bit will be high level.*/
-            uint32_t byte_trans:          1;        /*This register changes to high level when one byte is transferred.*/
-            uint32_t reserved7:           1;
-            uint32_t rx_fifo_cnt:         6;        /*This register represent the amount of data need to send.*/
-            uint32_t reserved14:          4;
-            uint32_t tx_fifo_cnt:         6;        /*This register stores the amount of received data  in ram.*/
-            uint32_t scl_main_state_last: 3;        /*This register stores the value of state machine for i2c module.  3'h0: SCL_MAIN_IDLE  3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS  3'h3: SCL_RX_DATA  3'h4 SCL_TX_DATA  3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
-            uint32_t reserved27:          1;
-            uint32_t scl_state_last:      3;        /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE  3'h1:SCL_START   3'h2:SCL_LOW_EDGE  3'h3: SCL_LOW   3'h4:SCL_HIGH_EDGE   3'h5:SCL_HIGH  3'h6:SCL_STOP*/
-            uint32_t reserved31:          1;
-        };
-        uint32_t val;
-    } status_reg;
-     
-    status_reg sr;
-    sr.val= i2c->dev->status_reg.val;
-    
-    log_i("ack(%d) sl_rw(%d) to(%d) arb(%d) busy(%d) sl(%d) trans(%d) rx(%d) tx(%d) sclMain(%d) scl(%d)",sr.ack_rec,sr.slave_rw,sr.time_out,sr.arb_lost,sr.bus_busy,sr.slave_addressed,sr.byte_trans, sr.rx_fifo_cnt, sr.tx_fifo_cnt,sr.scl_main_state_last, sr.scl_state_last);
-}
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+    goto end;
+  }
+
+  //short implementation does not support zero size writes (example when scanning) PR in IDF?
+  //ret =  i2c_master_write_to_device((i2c_port_t)i2c_num, address, buff, size, timeOutMillis / portTICK_PERIOD_MS);
+
+  ret = ESP_OK;
+  uint8_t cmd_buff[I2C_LINK_RECOMMENDED_SIZE(1)] = {0};
+  cmd = i2c_cmd_link_create_static(cmd_buff, I2C_LINK_RECOMMENDED_SIZE(1));
+  ret = i2c_master_start(cmd);
+  if (ret != ESP_OK) {
+    goto end;
+  }
+  ret = i2c_master_write_byte(cmd, (address << 1) | I2C_MASTER_WRITE, true);
+  if (ret != ESP_OK) {
+    goto end;
+  }
+  if (size) {
+    ret = i2c_master_write(cmd, buff, size, true);
+    if (ret != ESP_OK) {
+      goto end;
+    }
+  }
+  ret = i2c_master_stop(cmd);
+  if (ret != ESP_OK) {
+    goto end;
+  }
+  ret = i2c_master_cmd_begin((i2c_port_t)i2c_num, cmd, timeOutMillis / portTICK_PERIOD_MS);
+
+end:
+  if (cmd != NULL) {
+    i2c_cmd_link_delete_static(cmd);
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
 #endif
-
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER)
-static void i2cDumpFifo(i2c_t * i2c){
-char buf[64];
-uint16_t k = 0;
-uint16_t i = fifoPos+1;
-  i %=FIFOMAX;
-while((fifoBuffer[i]==0)&&(i!=fifoPos)){
-  i++;
-  i %=FIFOMAX;
+  return ret;
 }
-if(i != fifoPos){// actual data
-    do{
-      if(fifoBuffer[i] & 0x8000){ // address byte
-        if(fifoBuffer[i] & 0x100) { // read
-          if(fifoBuffer[i] & 0x1) { // valid read dev id
-            k+= sprintf(&buf[k],"READ  0x%02X",(fifoBuffer[i]&0xff)>>1);
-          } else { // invalid read dev id
-            k+= sprintf(&buf[k],"Bad READ  0x%02X",(fifoBuffer[i]&0xff));
-          }
-        } else { // write
-          if(fifoBuffer[i] & 0x1) { // bad write dev id
-            k+= sprintf(&buf[k],"bad WRITE 0x%02X",(fifoBuffer[i]&0xff));
-          } else { // good Write
-            k+= sprintf(&buf[k],"WRITE 0x%02X",(fifoBuffer[i]&0xff)>>1);
-          }
-        }
-      } else k += sprintf(&buf[k],"% 4X ",fifoBuffer[i]);
 
-      i++;
-      i %= FIFOMAX;
-      bool outBuffer=false;
-      if( fifoBuffer[i] & 0x8000){
-        outBuffer=true;
-        k=0;
-      }
-      if((outBuffer)||(k>50)||(i==fifoPos)) log_i("%s",buf);
-      outBuffer = false;
-      if(k>50) {
-        k=sprintf(buf,"-> ");
-      }
-    }while( i!= fifoPos);
-}
-}
+esp_err_t i2cRead(uint8_t i2c_num, uint16_t address, uint8_t *buff, size_t size, uint32_t timeOutMillis, size_t *readCount) {
+  esp_err_t ret = ESP_FAIL;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ret;
+  }
 #endif
-
-static void IRAM_ATTR i2cTriggerDumps(i2c_t * i2c, uint8_t trigger, const char locus[]){
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&&(defined ENABLE_I2C_DEBUG_BUFFER)
-    if( trigger ){
-      log_i("%s",locus);      
-      if(trigger & 1) i2cDumpI2c(i2c);
-      if(trigger & 2) i2cDumpInts(i2c->num);
-      if(trigger & 4) i2cDumpCmdQueue(i2c);
-      if(trigger & 8) i2cDumpStatus(i2c);
-      if(trigger & 16) i2cDumpFifo(i2c);
-    }
-#endif    
-}
- // end of debug support routines
- 
-/* Start of CPU Clock change Support
-*/
-
-static void i2cApbChangeCallback(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb){
-    i2c_t* i2c = (i2c_t*) arg; // recover data
-    if(i2c == NULL) {  // point to peripheral control block does not exits
-        return;
-    }
-    uint32_t oldFreq=0;
-    switch(ev_type){
-        case APB_BEFORE_CHANGE : 
-            if(new_apb < 3000000) {// too slow
-                log_e("apb speed %d too slow",new_apb);
-                break;
-            }
-            I2C_MUTEX_LOCK(); // lock will spin until current transaction is completed
-            break;
-        case APB_AFTER_CHANGE :
-            oldFreq = (i2c->dev->scl_low_period.period+i2c->dev->scl_high_period.period); //read old apbCycles 
-            if(oldFreq>0) { // was configured with value
-                oldFreq = old_apb / oldFreq;
-                i2cSetFrequency(i2c,oldFreq);
-            }
-            I2C_MUTEX_UNLOCK();
-            break;
-        default : 
-            log_e("unk ev %u",ev_type);
-            I2C_MUTEX_UNLOCK();
-    }
-    return;
-}
-/* End of CPU Clock change Support
-*/ 
-static void IRAM_ATTR i2cSetCmd(i2c_t * i2c, uint8_t index, uint8_t op_code, uint8_t byte_num, bool ack_val, bool ack_exp, bool ack_check)
-{
-    I2C_COMMAND_t cmd;
-    cmd.val=0;
-    cmd.ack_en = ack_check;
-    cmd.ack_exp = ack_exp;
-    cmd.ack_val = ack_val;
-    cmd.byte_num = byte_num;
-    cmd.op_code = op_code;
-    i2c->dev->command[index].val = cmd.val;
-}
- 
-
-static void IRAM_ATTR fillCmdQueue(i2c_t * i2c, bool INTS)
-{
-    /* this function is called on initial i2cProcQueue() or when a I2C_END_DETECT_INT occurs
-     */
-    uint16_t cmdIdx = 0;
-    uint16_t qp = i2c->queuePos; // all queues before queuePos have been completely processed,
-      // so look start by checking the 'current queue' so see if it needs commands added to
-      // hardware peripheral command list. walk through each queue entry until all queues have been
-      // checked
-    bool done;
-    bool needMoreCmds = false;
-    bool ena_rx=false; // if we add a read op, better enable Rx_Fifo IRQ
-    bool ena_tx=false; // if we add a Write op, better enable TX_Fifo IRQ
-
-    while(!needMoreCmds&&(qp < i2c->queueCount)) { // check if more possible cmds
-        if(i2c->dq[qp].ctrl.stopCmdSent) {// marks that all required cmds[] have been added to peripheral 
-            qp++;
-        } else {
-            needMoreCmds=true;
-        }
-    }
-    //log_e("needMoreCmds=%d",needMoreCmds);
-    done=(!needMoreCmds)||(cmdIdx>14);
-
-    while(!done) { // fill the command[] until either 0..14 filled or out of cmds and last cmd is STOP
-        //CMD START
-        I2C_DATA_QUEUE_t *tdq=&i2c->dq[qp]; // simpler coding
-
-        if((!tdq->ctrl.startCmdSent) && (cmdIdx < 14)) { // has this dq element's START command been added?
-            // (cmdIdx<14)  because a START op cannot directly precede an END op, else a time out cascade occurs
-            i2cSetCmd(i2c, cmdIdx++, I2C_CMD_RSTART, 0, false, false, false);
-            tdq->ctrl.startCmdSent=1;
-        }
-
-        //CMD WRITE ADDRESS
-        if((!done)&&(tdq->ctrl.startCmdSent)) { // have to leave room for continue(END), and START must have been sent!
-            if(!tdq->ctrl.addrCmdSent) {
-                i2cSetCmd(i2c, cmdIdx++, I2C_CMD_WRITE, tdq->ctrl.addrReq, false, false, true); //load address in cmdlist, validate (low) ack
-                tdq->ctrl.addrCmdSent=1;
-                done =(cmdIdx>14);
-                ena_tx=true; // tx Data necessary
-            }
-        }
-
-        /* Can I have another Sir?
-        ALL CMD queues must be terminated with either END or STOP.
-
-        If END is used, when refilling the cmd[] next time, no entries from END to [15] can be used.
-        AND the cmd[] must be filled starting at [0] with commands. Either fill all 15 [0]..[14] and leave the
-        END in [15] or include a STOP in one of the positions [0]..[14].  Any entries after a STOP are IGNORED by the StateMachine.
-        The END operation does not complete until ctr->trans_start=1 has been issued.
-
-        So, only refill from [0]..[14], leave [15] for a continuation(END) if necessary.
-        As a corollary, once END exists in [15], you do not need to overwrite it for the
-        next continuation. It is never modified. But, I update it every time because it might
-        actually be the first time!
-
-        23NOV17  START cannot proceed END.  if START is in[14], END cannot be in [15].
-        So, if END is moved to [14], [14] and [15] can no longer be used for anything other than END.
-        If a START is found in [14] then a prior READ or WRITE must be expanded so that there is no START element in [14].
-         */
-
-         if((!done)&&(tdq->ctrl.addrCmdSent)) { //room in command[] for at least One data (read/Write) cmd
-            uint8_t blkSize=0; // max is 255
-            while(( tdq->cmdBytesNeeded > tdq->ctrl.mode )&&(!done )) { // more bytes needed and room in cmd queue, leave room for END
-                blkSize = (tdq->cmdBytesNeeded > 255)?255:(tdq->cmdBytesNeeded - tdq->ctrl.mode); // Last read cmd needs different ACK setting, so leave 1 byte remainder on reads
-                tdq->cmdBytesNeeded -= blkSize; 
-                if(tdq->ctrl.mode==1) { //read mode
-                    i2cSetCmd(i2c, (cmdIdx)++, I2C_CMD_READ, blkSize,false,false,false); // read    cmd, this can't be the last read.
-                    ena_rx=true; // need to enable rxFifo IRQ
-                } else { // write
-                    i2cSetCmd(i2c, cmdIdx++, I2C_CMD_WRITE, blkSize, false, false, true); // check for Nak
-                    ena_tx=true; // need to enable txFifo IRQ
-                }
-                done = cmdIdx>14; //have to leave room for END
-            }
-
-            if(!done) { // buffer is not filled completely
-                if((tdq->ctrl.mode==1)&&(tdq->cmdBytesNeeded==1)) { //special last read byte NAK
-                    i2cSetCmd(i2c, (cmdIdx)++, I2C_CMD_READ, 1,true,false,false);
-                    // send NAK to mark end of read
-                    tdq->cmdBytesNeeded=0;
-                    done = cmdIdx > 14;
-                    ena_rx=true;
-                }
-            }
-
-            tdq->ctrl.dataCmdSent=(tdq->cmdBytesNeeded==0); // enough command[] to send all data
-
-            if((!done)&&(tdq->ctrl.dataCmdSent)) { // possibly add stop
-                if(!tdq->ctrl.stopCmdSent){
-                    if(tdq->ctrl.stop) { //send a stop
-                        i2cSetCmd(i2c, (cmdIdx)++,I2C_CMD_STOP,0,false,false,false);
-                        done = cmdIdx > 14;
-                    }
-                    tdq->ctrl.stopCmdSent = 1;
-                }
-            }
-        }
-
-        if((cmdIdx==14)&&(!tdq->ctrl.startCmdSent)) {
-            // START would have preceded END, causes SM TIMEOUT
-            // need to stretch out a prior WRITE or READ to two Command[] elements
-            done = false; // reuse it
-            uint16_t i = 13; // start working back until a READ/WRITE has >1 numBytes
-            cmdIdx =15;
-            while(!done) {
-                i2c->dev->command[i+1].val = i2c->dev->command[i].val; // push it down
-                if (((i2c->dev->command[i].op_code == 1)||(i2c->dev->command[i].op_code==2))) {
-                    /* add a dummy read/write cmd[] with num_bytes set to zero,just a place holder in the cmd[]list
-                     */
-                    i2c->dev->command[i].byte_num = 0;
-                    done = true;
-
-                } else {
-                    if(i > 0) {
-                        i--;
-                    } else { // unable to stretch, fatal
-                        log_e("invalid CMD[] layout Stretch Failed");
-                        i2cDumpCmdQueue(i2c);
-                        done = true;
-                    }
-                }
-            }
-
-        }
-
-
-        if(cmdIdx==15) { //need continuation, even if STOP is in 14, it will not matter
-            // cmd buffer is almost full, Add END as a continuation feature
-            i2cSetCmd(i2c, (cmdIdx)++,I2C_CMD_END, 0,false,false,false);
-            i2c->dev->int_ena.end_detect=1; 
-            i2c->dev->int_clr.end_detect=1; 
-            done = true;
-        }
-
-        if(!done) {
-            if(tdq->ctrl.stopCmdSent) { // this queue element has been completely added to command[] buffer
-                qp++;
-                if(qp < i2c->queueCount) {
-                    tdq = &i2c->dq[qp];
-                } else {
-                    done = true;
-                }
-            }
-        }
-
-    }// while(!done)
-    if(INTS) { // don't want to prematurely enable fifo ints until ISR is ready to handle them.
-        if(ena_rx) {
-            i2c->dev->int_ena.rx_fifo_full = 1;
-        }
-        if(ena_tx) {
-            i2c->dev->int_ena.tx_fifo_empty = 1;
-        }
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+  } else {
+    ret = i2c_master_read_from_device((i2c_port_t)i2c_num, address, buff, size, timeOutMillis / portTICK_PERIOD_MS);
+    if (ret == ESP_OK) {
+      *readCount = size;
+    } else {
+      *readCount = 0;
     }
-}
-
-static void IRAM_ATTR fillTxFifo(i2c_t * i2c)
-{
-    /*
-    12/01/2017 The Fifo's are independent, 32 bytes of tx and 32 bytes of Rx.
-    overlap is not an issue, just keep them full/empty the status_reg.xx_fifo_cnt
-    tells the truth. And the INT's fire correctly
-     */
-    uint16_t a=i2c->queuePos; // currently executing dq,
-    bool full=!(i2c->dev->status_reg.tx_fifo_cnt<31);
-    uint8_t cnt;
-    bool rxQueueEncountered = false;
-    while((a < i2c->queueCount) && !full) {
-        I2C_DATA_QUEUE_t *tdq = &i2c->dq[a];
-        cnt=0;
-        // add to address to fifo ctrl.addr already has R/W bit positioned correctly
-        if(tdq->ctrl.addrSent < tdq->ctrl.addrReq) { // need to send address bytes
-            if(tdq->ctrl.addrReq==2) { //10bit
-                if(tdq->ctrl.addrSent==0) { //10bit highbyte needs sent
-                    if(!full) { // room in fifo
-                        i2c->dev->fifo_data.val = ((tdq->ctrl.addr>>8)&0xFF);
-                        cnt++;
-                        tdq->ctrl.addrSent=1; //10bit highbyte sent
-                    }
-                }
-                full=!(i2c->dev->status_reg.tx_fifo_cnt<31);
-
-                if(tdq->ctrl.addrSent==1) { //10bit Lowbyte needs sent
-                    if(!full) { // room in fifo
-                        i2c->dev->fifo_data.val = tdq->ctrl.addr&0xFF;
-                        cnt++;
-                        tdq->ctrl.addrSent=2; //10bit lowbyte sent
-                    }
-                }
-            } else { // 7bit}
-                if(tdq->ctrl.addrSent==0) { // 7bit Lowbyte needs sent
-                    if(!full) { // room in fifo
-                        i2c->dev->fifo_data.val = tdq->ctrl.addr&0xFF;
-                        cnt++;
-                        tdq->ctrl.addrSent=1; // 7bit lowbyte sent
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER)
-                        uint16_t a = 0x8000 | tdq->ctrl.addr | (tdq->ctrl.mode<<8);
-                        fifoBuffer[fifoPos++] = a;
-                        fifoPos %= FIFOMAX;
-#endif
-                    }
-                }
-            }
-        }
-        // add write data to fifo
-        if(tdq->ctrl.mode==0) { // write
-            if(tdq->ctrl.addrSent == tdq->ctrl.addrReq) { //address has been sent, is Write Mode!
-                uint32_t moveCnt = 32 - i2c->dev->status_reg.tx_fifo_cnt; // how much room in txFifo?
-                while(( moveCnt>0)&&(tdq->position < tdq->length)) {
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER)
-                    fifoBuffer[fifoPos++] =  tdq->data[tdq->position];
-                    fifoPos %= FIFOMAX;
-#endif
-                    i2c->dev->fifo_data.val = tdq->data[tdq->position++];
-                    cnt++;
-                    moveCnt--;
-
-                }
-            }
-        } else { // read Queue Encountered, can't update QueuePos past this point, emptyRxfifo will do it
-            if( ! rxQueueEncountered ) {
-              rxQueueEncountered = true;
-              if(a > i2c->queuePos){
-                i2c->queuePos = a; 
-              }
-           }              
-        }
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER)
-
-        // update debug buffer tx counts
-        cnt += intBuff[intPos[i2c->num]][1][i2c->num]>>16;
-        intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF)|(cnt<<16);
-
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
 #endif
-        full=!(i2c->dev->status_reg.tx_fifo_cnt<31);
-        if(!full) {
-            a++;    // check next buffer for address tx, or write data
-        }
-    }
-
-    if(a >= i2c->queueCount ) { // disable TX IRQ, all tx Data has been queued
-        i2c->dev->int_ena.tx_fifo_empty= 0;
-    }
-
-    i2c->dev->int_clr.tx_fifo_empty=1;
+  return ret;
 }
 
-
-static void IRAM_ATTR emptyRxFifo(i2c_t * i2c)
-{
-    uint32_t d, cnt=0, moveCnt;
-    
-    moveCnt = i2c->dev->status_reg.rx_fifo_cnt;//no need to check the reg until this many are read
-
-    while((moveCnt > 0)&&(i2c->queuePos < i2c->queueCount)){ // data to move    
-
-        I2C_DATA_QUEUE_t *tdq =&i2c->dq[i2c->queuePos]; //short cut
-
-        while((tdq->position >= tdq->length)&&( i2c->queuePos < i2c->queueCount)){ // find were to store
-            i2c->queuePos++;
-            tdq = &i2c->dq[i2c->queuePos];
-        }
-      
-        if(i2c->queuePos >= i2c->queueCount){ // bad stuff, rx data but no place to put it!
-            log_e("no Storage location for %d",moveCnt);
-        // discard
-            while(moveCnt>0){
-                d = i2c->dev->fifo_data.val;
-                moveCnt--;
-                cnt++;
-            }
-            break;
-        }
-        
-        if(tdq->ctrl.mode == 1){ // read command
-            if(moveCnt > (tdq->length - tdq->position)) { //make sure they go in this dq
-        // part of these reads go into the next dq
-                moveCnt = (tdq->length - tdq->position);
-            }
-        } else {// error
-            log_e("RxEmpty(%d) call on TxBuffer? dq=%d",moveCnt,i2c->queuePos);
-        // discard
-            while(moveCnt>0){
-                d = i2c->dev->fifo_data.val;
-                moveCnt--;
-                cnt++;
-            }
-            break;
-        }
-
-        while(moveCnt > 0) { // store data
-            d = i2c->dev->fifo_data.val;
-            moveCnt--;
-            cnt++;
-            tdq->data[tdq->position++] = (d&0xFF);
-        }
-
-        moveCnt = i2c->dev->status_reg.rx_fifo_cnt; //any more out there?
-    }
-    
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)&& (defined ENABLE_I2C_DEBUG_BUFFER)
-        // update Debug rxCount
-        cnt += (intBuff[intPos[i2c->num]][1][i2c->num])&0xffFF;
-        intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF0000)|cnt;
+esp_err_t i2cWriteReadNonStop(
+  uint8_t i2c_num, uint16_t address, const uint8_t *wbuff, size_t wsize, uint8_t *rbuff, size_t rsize, uint32_t timeOutMillis, size_t *readCount
+) {
+  esp_err_t ret = ESP_FAIL;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ret;
+  }
 #endif
-}
-
-static void IRAM_ATTR i2cIsrExit(i2c_t * i2c,const uint32_t eventCode,bool Fatal)
-{
-
-    switch(eventCode) {
-    case EVENT_DONE:
-        i2c->error = I2C_OK;
-        break;
-    case EVENT_ERROR_NAK :
-        i2c->error =I2C_ADDR_NAK;
-        break;
-    case EVENT_ERROR_DATA_NAK :
-        i2c->error =I2C_DATA_NAK;
-        break;
-    case EVENT_ERROR_TIMEOUT :
-        i2c->error = I2C_TIMEOUT;
-        break;
-    case EVENT_ERROR_ARBITRATION:
-        i2c->error = I2C_ARBITRATION;
-        break;
-    default :
-        i2c->error = I2C_ERROR;
-    }
-    uint32_t exitCode = EVENT_DONE | eventCode |(Fatal?EVENT_ERROR:0);
-    if((i2c->queuePos < i2c->queueCount) && (i2c->dq[i2c->queuePos].ctrl.mode == 1)) {
-        emptyRxFifo(i2c);    // grab last few characters
-    }
-    i2c->dev->int_ena.val = 0; // shut down interrupts
-    i2c->dev->int_clr.val = 0x1FFF;
-    i2c->stage = I2C_DONE;
-    i2c->exitCode = exitCode; //true eventcode
-
-    portBASE_TYPE HPTaskAwoken = pdFALSE,xResult;
-    // try to notify Dispatch we are done,
-    // else the 50ms time out will recover the APP, just a little slower
-    HPTaskAwoken = pdFALSE;
-    xResult = xEventGroupSetBitsFromISR(i2c->i2c_event, exitCode, &HPTaskAwoken);
-    if(xResult == pdPASS) {
-        if(HPTaskAwoken==pdTRUE) {
-            portYIELD_FROM_ISR();
-            //      log_e("Yield to Higher");
-        }
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+  } else {
+    ret = i2c_master_write_read_device((i2c_port_t)i2c_num, address, wbuff, wsize, rbuff, rsize, timeOutMillis / portTICK_PERIOD_MS);
+    if (ret == ESP_OK) {
+      *readCount = rsize;
+    } else {
+      *readCount = 0;
     }
-
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
+#endif
+  return ret;
 }
 
-static void IRAM_ATTR i2c_update_error_byte_cnt(i2c_t * i2c)
-{
-/* i2c_update_error_byte_cnt 07/18/2018
-  Only called after an error has occurred, so, most of the time this function is never used.
-  This function obliterates the need to interrupt monitor each byte transferred, at high bitrates
-  the byte interrupts were overwhelming the OS.  Spurious Interrupts were being generated.
-  it updates errorByteCnt, errorQueue. 
- */
-    uint16_t a=0; // start at top of DQ, count how many bytes added to tx fifo, and received from rx_fifo.
-    int16_t bc = 0;
-    I2C_DATA_QUEUE_t *tdq;
-    i2c->errorByteCnt = 0; 
-    while( a < i2c->queueCount){ // add up all bytes loaded into fifo's
-        tdq = &i2c->dq[a];
-        i2c->errorByteCnt += tdq->ctrl.addrSent;
-        i2c->errorByteCnt += tdq->position; 
-        a++;
-    }
-  // now errorByteCnt contains total bytes moved into and out of FIFO's
-  // but, there may still be bytes waiting in Fifo's
-    i2c->errorByteCnt -= i2c->dev->status_reg.tx_fifo_cnt; // waiting to go out;
-    i2c->errorByteCnt += i2c->dev->status_reg.rx_fifo_cnt; // already received
-// now walk thru DQ again, find which byte is 'current'
-    bc = i2c->errorByteCnt;
-    i2c->errorQueue = 0;
-    while( i2c->errorQueue < i2c->queueCount ){
-        tdq = &i2c->dq[i2c->errorQueue];
-        if(bc>0){ // not found yet
-            if( tdq->ctrl.addrSent >= bc){ // in address
-                bc = -1; // in address
-                break;
-            } else {
-                bc -= tdq->ctrl.addrSent;
-                if( tdq->length > bc) { // data nak
-                    break;
-                } else { // count down
-                    bc -= tdq->length;
-                }
-            }
-        } else break;
-        
-        i2c->errorQueue++;
-    }  
-  
-    i2c->errorByteCnt = bc;
- }
-
-static void IRAM_ATTR i2c_isr_handler_default(void* arg)
-{
-    i2c_t* p_i2c = (i2c_t*) arg; // recover data
-    uint32_t activeInt = p_i2c->dev->int_status.val&0x7FF;
-
-    if(p_i2c->stage==I2C_DONE) { //get Out, can't service, not configured
-        p_i2c->dev->int_ena.val = 0;
-        p_i2c->dev->int_clr.val = 0x1FFF;
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
-        uint32_t raw = p_i2c->dev->int_raw.val;
-        log_w("eject raw=%p, int=%p",raw,activeInt);
+esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency) {
+  esp_err_t ret = ESP_FAIL;
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return ret;
+  }
 #endif
-        return;
-    }
-    while (activeInt != 0) { // Ordering of 'if(activeInt)' statements is important, don't change
-
-    #if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER)
-        if(activeInt==(intBuff[intPos[p_i2c->num]][0][p_i2c->num]&0x1fff)) {
-            intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (((intBuff[intPos[p_i2c->num]][0][p_i2c->num]>>16)+1)<<16)|activeInt;
-        } else {
-            intPos[p_i2c->num]++;
-            intPos[p_i2c->num] %= INTBUFFMAX;
-            intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (1<<16) | activeInt;
-            intBuff[intPos[p_i2c->num]][1][p_i2c->num] = 0;
-        }
-
-        intBuff[intPos[p_i2c->num]][2][p_i2c->num] = xTaskGetTickCountFromISR(); // when IRQ fired
-
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+    goto end;
+  }
+  if (bus[i2c_num].frequency == frequency) {
+    ret = ESP_OK;
+    goto end;
+  }
+  if (!frequency) {
+    frequency = 100000UL;
+  } else if (frequency > 1000000UL) {
+    frequency = 1000000UL;
+  }
+
+  typedef struct {
+    soc_module_clk_t clk; /*!< I2C source clock */
+    uint32_t clk_freq;    /*!< I2C source clock frequency */
+  } i2c_clk_alloc_t;
+
+  typedef enum {
+    I2C_SCLK_DEFAULT = 0, /*!< I2C source clock not selected*/
+#if SOC_I2C_SUPPORT_APB
+    I2C_SCLK_APB, /*!< I2C source clock from APB, 80M*/
 #endif
- 
-        if (activeInt & I2C_TRANS_START_INT_ST_M) {
-            if(p_i2c->stage==I2C_STARTUP) {
-                p_i2c->stage=I2C_RUNNING;
-            }
-
-            activeInt &=~I2C_TRANS_START_INT_ST_M;
-            p_i2c->dev->int_ena.trans_start = 1; // already enabled? why Again?
-            p_i2c->dev->int_clr.trans_start = 1; // so that will trigger after next 'END'
-        }
-
-        if (activeInt & I2C_TXFIFO_EMPTY_INT_ST) {//should this be before Trans_start?
-            fillTxFifo(p_i2c); //fillTxFifo will enable/disable/clear interrupt
-            activeInt&=~I2C_TXFIFO_EMPTY_INT_ST;
-        }
-
-        if(activeInt & I2C_RXFIFO_FULL_INT_ST) {
-            emptyRxFifo(p_i2c);
-            p_i2c->dev->int_clr.rx_fifo_full=1;
-            p_i2c->dev->int_ena.rx_fifo_full=1; //why?
-
-            activeInt &=~I2C_RXFIFO_FULL_INT_ST;
-        }
-
-        if(activeInt & I2C_RXFIFO_OVF_INT_ST) {
-            emptyRxFifo(p_i2c);
-            p_i2c->dev->int_clr.rx_fifo_full=1;
-            p_i2c->dev->int_ena.rx_fifo_full=1; //why?
-
-            activeInt &=~I2C_RXFIFO_OVF_INT_ST;
-        }
-
-        if (activeInt & I2C_ACK_ERR_INT_ST_M) {//fatal error, abort i2c service
-            if (p_i2c->mode == I2C_MASTER) {
-                i2c_update_error_byte_cnt(p_i2c); // calc which byte caused ack Error, check if address or data
-                if(p_i2c->errorByteCnt < 0 ) { // address
-                    i2cIsrExit(p_i2c,EVENT_ERROR_NAK,true);
-                } else {
-                    i2cIsrExit(p_i2c,EVENT_ERROR_DATA_NAK,true); //data
-                }
-            }
-            return;
-        }
-
-        if (activeInt & I2C_TIME_OUT_INT_ST_M) {
-            // let Gross timeout occur, Slave may release SCL before the configured timeout expires
-            // the Statemachine only has a 13.1ms max timout, some Devices >500ms
-            p_i2c->dev->int_clr.time_out =1;
-            activeInt &=~I2C_TIME_OUT_INT_ST;
-          // since a timeout occurred, capture the rxFifo data 
-            emptyRxFifo(p_i2c);
-            p_i2c->dev->int_clr.rx_fifo_full=1;
-            p_i2c->dev->int_ena.rx_fifo_full=1; //why?
-
-        }
-
-        if (activeInt & I2C_TRANS_COMPLETE_INT_ST_M) {
-            p_i2c->dev->int_clr.trans_complete = 1;
-            i2cIsrExit(p_i2c,EVENT_DONE,false);
-            return; // no more work to do
-            /*
-            // how does slave mode act?
-            if (p_i2c->mode == I2C_SLAVE) { // STOP detected
-            // empty fifo
-            // dispatch callback
-             */
-        }
-
-        if (activeInt & I2C_ARBITRATION_LOST_INT_ST_M) { //fatal
-            i2cIsrExit(p_i2c,EVENT_ERROR_ARBITRATION,true);
-            return; // no more work to do
-        }
-
-        if (activeInt & I2C_SLAVE_TRAN_COMP_INT_ST_M) {
-            p_i2c->dev->int_clr.slave_tran_comp = 1;
-            // need to complete this !
-        }
-
-        if (activeInt & I2C_END_DETECT_INT_ST_M) {
-            p_i2c->dev->int_ena.end_detect = 0;
-            p_i2c->dev->int_clr.end_detect = 1;
-            p_i2c->dev->ctr.trans_start=0;
-            fillCmdQueue(p_i2c,true); // enable interrupts
-            p_i2c->dev->ctr.trans_start=1; // go for it
-            activeInt&=~I2C_END_DETECT_INT_ST_M;
-        }
-
-        if(activeInt) { // clear unhandled if possible?  What about Disabling interrupt?
-            p_i2c->dev->int_clr.val = activeInt;
-            log_e("unknown int=%x",activeInt);
-            // disable unhandled IRQ,
-            p_i2c->dev->int_ena.val = p_i2c->dev->int_ena.val & (~activeInt);
-        }
-
-//        activeInt = p_i2c->dev->int_status.val; // start all over if another interrupt happened
-// 01AUG2018 if another interrupt happened, the OS will schedule another interrupt
-// this is the source of spurious interrupts
-    }
-}
-
-/* Stickbreaker added for ISR 11/2017
-functional with Silicon date=0x16042000
- */
-static i2c_err_t i2cAddQueue(i2c_t * i2c,uint8_t mode, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop, bool dataOnly, EventGroupHandle_t event)
-{
-    // need to grab a MUTEX for exclusive Queue,
-    // what about if ISR is running?
-
-    if(i2c==NULL) {
-        return I2C_ERROR_DEV;
-    }
-
-    I2C_DATA_QUEUE_t dqx;
-    dqx.data = dataPtr;
-    dqx.length = dataLen;
-    dqx.position = 0;
-    dqx.cmdBytesNeeded = dataLen;
-    dqx.ctrl.val = 0;
-    if( dataOnly) {
-     /* special case to add a queue data only element.
-        START and devAddr will not be sent, this dq element can have a STOP.
-        allows multiple buffers to be used for one transaction.
-        sequence: normal transaction(sendStop==false), [dataonly(sendStop==false)],dataOnly(sendStop==true)
-       *** Currently only works with WRITE, final byte NAK an READ will cause a fail between dq buffer elements.  (in progress 30JUL2018)
-        */
-        dqx.ctrl.startCmdSent = 1; // mark as already sent
-        dqx.ctrl.addrCmdSent = 1;
-    } else {
-        dqx.ctrl.addrReq = ((i2cDeviceAddr&0xFC00)==0x7800)?2:1; // 10bit or 7bit address
-    }
-    dqx.ctrl.addr = i2cDeviceAddr;
-    dqx.ctrl.mode = mode;
-    dqx.ctrl.stop= sendStop;
-    dqx.queueEvent = event;
-
-    if(event) { // an eventGroup exist, so, initialize it
-        xEventGroupClearBits(event, EVENT_MASK); // all of them
-    }
-
-    if(i2c->dq!=NULL) { // expand
-        //log_i("expand");
-        I2C_DATA_QUEUE_t* tq =(I2C_DATA_QUEUE_t*)realloc(i2c->dq,sizeof(I2C_DATA_QUEUE_t)*(i2c->queueCount +1));
-        if(tq!=NULL) { // ok
-            i2c->dq = tq;
-            memmove(&i2c->dq[i2c->queueCount++],&dqx,sizeof(I2C_DATA_QUEUE_t));
-        } else { // bad stuff, unable to allocate more memory!
-            log_e("realloc Failure");
-            return I2C_ERROR_MEMORY;
-        }
-    } else { // first Time
-        //log_i("new");
-        i2c->queueCount=0;
-        i2c->dq =(I2C_DATA_QUEUE_t*)malloc(sizeof(I2C_DATA_QUEUE_t));
-        if(i2c->dq!=NULL) {
-            memmove(&i2c->dq[i2c->queueCount++],&dqx,sizeof(I2C_DATA_QUEUE_t));
-        } else {
-            log_e("malloc failure");
-            return I2C_ERROR_MEMORY;
-        }
-    }
-    return I2C_ERROR_OK;
-}
-
-i2c_err_t i2cAddQueueWrite(i2c_t * i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop,EventGroupHandle_t event)
-{
-    return i2cAddQueue(i2c,0,i2cDeviceAddr,dataPtr,dataLen,sendStop,false,event);
-}
-
-i2c_err_t i2cAddQueueRead(i2c_t * i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen,bool sendStop,EventGroupHandle_t event)
-{
-    //10bit read is kind of weird, first you do a 0byte Write with 10bit
-    //  address, then a ReSTART then a 7bit Read using the the upper 7bit +
-    // readBit.
-
-    // this might cause an internal register pointer problem with 10bit
-    // devices, But, Don't have any to test against.
-    // this is the Industry Standard specification.
-
-    if((i2cDeviceAddr &0xFC00)==0x7800) { // ten bit read
-        i2c_err_t err = i2cAddQueue(i2c,0,i2cDeviceAddr,NULL,0,false,false,event);
-        if(err==I2C_ERROR_OK) {
-            return i2cAddQueue(i2c,1,(i2cDeviceAddr>>8),dataPtr,dataLen,sendStop,false,event);
-        } else {
-            return err;
-        }
-    }
-    return i2cAddQueue(i2c,1,i2cDeviceAddr,dataPtr,dataLen,sendStop,false,event);
-}
-
-i2c_err_t i2cProcQueue(i2c_t * i2c, uint32_t *readCount, uint16_t timeOutMillis)
-{
-    /* do the hard stuff here
-    install ISR if necessary
-    setup EventGroup
-    handle bus busy?
-     */
-    //log_e("procQueue i2c=%p",&i2c);
-    if(readCount){ //total reads accomplished in all queue elements
-        *readCount = 0;
-    }
-    if(i2c == NULL) {
-        return I2C_ERROR_DEV;
-    }
-    if(i2c->debugFlags & 0xff000000) i2cTriggerDumps(i2c,(i2c->debugFlags>>24),"before ProcQueue");
-    if (i2c->dev->status_reg.bus_busy) { // return error, let TwoWire() handle resetting the hardware.
-        /* if multi master then this if should be changed to this 03/12/2018
-        if(multiMaster){// try to let the bus clear by its self
-            uint32_t timeOutTick = millis();
-            while((i2c->dev->status_reg.bus_busy)&&(millis()-timeOutTick<timeOutMillis())){
-              delay(2); // allow task switch
-            }
-        }
-        if(i2c->dev->status_reg.bus_busy){ // still busy, so die
-             */
-        log_i("Bus busy, reinit");
-        return I2C_ERROR_BUSY;
-    }
-
-    I2C_MUTEX_LOCK();
-    /* what about co-existence with SLAVE mode?
-    Should I check if a slaveMode xfer is in progress and hang
-    until it completes?
-    if i2c->stage == I2C_RUNNING or I2C_SLAVE_ACTIVE
-     */
-    i2c->stage = I2C_DONE; // until ready
-
-#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO) && (defined ENABLE_I2C_DEBUG_BUFFER)
-    for(uint16_t i=0; i<INTBUFFMAX; i++) {
-        intBuff[i][0][i2c->num] = 0;
-        intBuff[i][1][i2c->num] = 0;
-        intBuff[i][2][i2c->num] = 0;
-    }
-    intPos[i2c->num] = 0;
-    fifoPos = 0;
-    memset(fifoBuffer,0,FIFOMAX);
+#if SOC_I2C_SUPPORT_XTAL
+    I2C_SCLK_XTAL, /*!< I2C source clock from XTAL, 40M */
 #endif
-    // EventGroup is used to signal transmission completion from ISR
-    // not always reliable. Sometimes, the FreeRTOS scheduler is maxed out and refuses request
-    // if that happens, this call hangs until the timeout period expires, then it continues.
-    if(!i2c->i2c_event) {
-        i2c->i2c_event = xEventGroupCreate();
-    }
-    if(i2c->i2c_event) {
-        xEventGroupClearBits(i2c->i2c_event, 0xFF);
-    } else { // failed to create EventGroup
-        log_e("eventCreate failed=%p",i2c->i2c_event);
-        I2C_MUTEX_UNLOCK();
-        return I2C_ERROR_MEMORY;
-    }
-
-    i2c_err_t reason = I2C_ERROR_OK;
-    i2c->mode = I2C_MASTER;
-    i2c->dev->ctr.trans_start=0; // Pause Machine
-    i2c->dev->timeout.tout = 0xFFFFF; // max 13ms
-    i2c->dev->int_clr.val = 0x1FFF; // kill them All!
-    
-    i2c->dev->ctr.ms_mode = 1; // master!
-    i2c->queuePos=0;
-    i2c->errorByteCnt=0;
-    i2c->errorQueue = 0;
-    uint32_t totalBytes=0; // total number of bytes to be Moved!
-    // convert address field to required I2C format
-    while(i2c->queuePos < i2c->queueCount) { // need to push these address modes upstream, to AddQueue
-        I2C_DATA_QUEUE_t *tdq = &i2c->dq[i2c->queuePos++];
-        uint16_t taddr=0;
-        if(tdq->ctrl.addrReq ==2) { // 10bit address
-            taddr =((tdq->ctrl.addr >> 7) & 0xFE)
-                   |tdq->ctrl.mode;
-            taddr = (taddr <<8) | (tdq->ctrl.addr&0xFF);
-        } else { // 7bit address
-            taddr =  ((tdq->ctrl.addr<<1)&0xFE)
-                     |tdq->ctrl.mode;
-        }
-        tdq->ctrl.addr = taddr; // all fixed with R/W bit
-        totalBytes += tdq->length + tdq->ctrl.addrReq; // total number of byte to be moved!
-    }
-    i2c->queuePos=0;
-
-    fillCmdQueue(i2c,false); // don't enable Tx/RX irq's
-    // start adding command[], END irq will keep it full
-    //Data Fifo will be filled after trans_start is issued
-    i2c->exitCode=0;
-
-    I2C_FIFO_CONF_t f;
-    f.val = i2c->dev->fifo_conf.val;
-    f.rx_fifo_rst = 1; // fifo in reset
-    f.tx_fifo_rst = 1; // fifo in reset
-    f.nonfifo_en = 0; // use fifo mode
-    f.nonfifo_tx_thres = 31;
-    // need to adjust threshold based on I2C clock rate, at 100k, 30 usually works,
-    // sometimes the emptyRx() actually moves 31 bytes
-    // it hasn't overflowed yet, I cannot tell if the new byte is added while
-    // emptyRX() is executing or before?
-  // let i2cSetFrequency() set thrhds  
-  //   f.rx_fifo_full_thrhd = 30; // 30 bytes before INT is issued
-  //  f.tx_fifo_empty_thrhd = 0;
-    f.fifo_addr_cfg_en = 0; // no directed access
-    i2c->dev->fifo_conf.val = f.val; // post them all
-
-    f.rx_fifo_rst = 0; // release fifo
-    f.tx_fifo_rst = 0;
-    i2c->dev->fifo_conf.val = f.val; // post them all
-
-    i2c->stage = I2C_STARTUP; // everything configured, now start the I2C StateMachine, and
-    // As soon as interrupts are enabled, the ISR will start handling them.
-    // it should receive a TXFIFO_EMPTY immediately, even before it
-    // receives the TRANS_START
-
-    
-    uint32_t interruptsEnabled =
-        I2C_ACK_ERR_INT_ENA | // (BIT(10))  Causes Fatal Error Exit
-        I2C_TRANS_START_INT_ENA | // (BIT(9))  Triggered by trans_start=1, initial,END
-        I2C_TIME_OUT_INT_ENA  | //(BIT(8))  Trigger by SLAVE SCL stretching, NOT an ERROR
-        I2C_TRANS_COMPLETE_INT_ENA | // (BIT(7))  triggered by STOP, successful exit
-        I2C_ARBITRATION_LOST_INT_ENA | // (BIT(5))  cause fatal error exit
-        I2C_SLAVE_TRAN_COMP_INT_ENA  | // (BIT(4))  unhandled
-        I2C_END_DETECT_INT_ENA  | // (BIT(3))   refills cmd[] list
-        I2C_RXFIFO_OVF_INT_ENA  | //(BIT(2))  unhandled
-        I2C_TXFIFO_EMPTY_INT_ENA | // (BIT(1))    triggers fillTxFifo()
-        I2C_RXFIFO_FULL_INT_ENA;  // (BIT(0))     trigger emptyRxFifo()
-  
-    i2c->dev->int_ena.val = interruptsEnabled;
- 
-    if(!i2c->intr_handle) { // create ISR for either peripheral
-        // log_i("create ISR %d",i2c->num);
-        uint32_t ret = 0;
-        uint32_t flags = ESP_INTR_FLAG_IRAM |  //< ISR can be called if cache is disabled
-          ESP_INTR_FLAG_LOWMED |   //< Low and medium prio interrupts. These can be handled in C.
-          ESP_INTR_FLAG_SHARED; //< Reduce resource requirements, Share interrupts
-      
-        if(i2c->num) {
-            ret = esp_intr_alloc_intrstatus(ETS_I2C_EXT1_INTR_SOURCE, flags, (uint32_t)&i2c->dev->int_status.val, interruptsEnabled, &i2c_isr_handler_default,i2c, &i2c->intr_handle);
-        } else {
-            ret = esp_intr_alloc_intrstatus(ETS_I2C_EXT0_INTR_SOURCE, flags, (uint32_t)&i2c->dev->int_status.val, interruptsEnabled, &i2c_isr_handler_default,i2c, &i2c->intr_handle);
-        }
-
-        if(ret!=ESP_OK) {
-            log_e("install interrupt handler Failed=%d",ret);
-            I2C_MUTEX_UNLOCK();
-            return I2C_ERROR_MEMORY;
-        }
-        if( !addApbChangeCallback( i2c, i2cApbChangeCallback)) {
-            log_e("install apb Callback failed");
-            I2C_MUTEX_UNLOCK();
-            return I2C_ERROR_DEV;
-        }
-
-    }
-    //hang until it completes.
-
-    // how many ticks should it take to transfer totalBytes through the I2C hardware,
-    // add user supplied timeOutMillis to Calculated Value
-
-    portTickType ticksTimeOut = ((totalBytes*10*1000)/(i2cGetFrequency(i2c))+timeOutMillis)/portTICK_PERIOD_MS;
-
-    i2c->dev->ctr.trans_start=1; // go for it
-
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-    portTickType tBefore=xTaskGetTickCount();
+#if SOC_I2C_SUPPORT_RTC
+    I2C_SCLK_RTC, /*!< I2C source clock from 8M RTC, 8M */
 #endif
-    
-    // wait for ISR to complete the transfer, or until timeOut in case of bus fault, hardware problem
-    
-    uint32_t eBits = xEventGroupWaitBits(i2c->i2c_event,EVENT_DONE,pdFALSE,pdTRUE,ticksTimeOut);
-
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-    portTickType tAfter=xTaskGetTickCount();
+#if SOC_I2C_SUPPORT_REF_TICK
+    I2C_SCLK_REF_TICK, /*!< I2C source clock from REF_TICK, 1M */
 #endif
-
-
-    // if xEventGroupSetBitsFromISR() failed, the ISR could have succeeded but never been
-    // able to mark the success
-
-    if(i2c->exitCode!=eBits) { // try to recover from O/S failure
-        //  log_e("EventGroup Failed:%p!=%p",eBits,i2c->exitCode);
-        eBits=i2c->exitCode;
-    }
-    if((eBits&EVENT_ERROR)||(!(eBits & EVENT_DONE))){ // need accurate errorByteCnt for debug
-      i2c_update_error_byte_cnt(i2c);
-    }
-
-    if(!(eBits==EVENT_DONE)&&(eBits&~(EVENT_ERROR_NAK|EVENT_ERROR_DATA_NAK|EVENT_ERROR|EVENT_DONE))) { // not only Done, therefore error, exclude ADDR NAK, DATA_NAK
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
-        i2cDumpI2c(i2c);
-        i2cDumpInts(i2c->num);
+    I2C_SCLK_MAX,
+  } i2c_sclk_t;
+
+  // i2c clock characteristic, The order is the same as i2c_sclk_t.
+  i2c_clk_alloc_t i2c_clk_alloc[I2C_SCLK_MAX] = {
+    {0, 0},
+#if SOC_I2C_SUPPORT_APB
+    {SOC_MOD_CLK_APB, esp_clk_apb_freq()}, /*!< I2C APB clock characteristic*/
 #endif
-    }
-
-    if(eBits&EVENT_DONE) { // no gross timeout
-        switch(i2c->error) {
-        case I2C_OK :
-            reason = I2C_ERROR_OK;
-            break;
-        case I2C_ERROR :
-            reason = I2C_ERROR_DEV;
-            break;
-        case I2C_ADDR_NAK:
-            reason = I2C_ERROR_ACK;
-            break;
-        case I2C_DATA_NAK:
-            reason = I2C_ERROR_ACK;
-            break;
-        case I2C_ARBITRATION:
-            reason = I2C_ERROR_BUS;
-            break;
-        case I2C_TIMEOUT:
-            reason = I2C_ERROR_TIMEOUT;
-            break;
-        default :
-            reason = I2C_ERROR_DEV;
-        }
-    } else { // GROSS timeout, shutdown ISR , report Timeout
-        i2c->stage = I2C_DONE;
-        i2c->dev->int_ena.val =0;
-        i2c->dev->int_clr.val = 0x1FFF;
-        i2c_update_error_byte_cnt(i2c);
-        if((i2c->errorByteCnt == 0)&&(i2c->errorQueue==0)) { // Bus Busy no bytes Moved
-            reason = I2C_ERROR_BUSY;
-            eBits = eBits | EVENT_ERROR_BUS_BUSY|EVENT_ERROR|EVENT_DONE;
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-            log_d(" Busy Timeout start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error);
-            i2cDumpI2c(i2c);
-            i2cDumpInts(i2c->num);
+#if SOC_I2C_SUPPORT_XTAL
+    {SOC_MOD_CLK_XTAL, esp_clk_xtal_freq()}, /*!< I2C XTAL characteristic*/
 #endif
-        } else { // just a timeout, some data made it out or in.
-            reason = I2C_ERROR_TIMEOUT;
-            eBits = eBits | EVENT_ERROR_TIMEOUT|EVENT_ERROR|EVENT_DONE;
-
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-            log_d(" Gross Timeout Dead start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error);
-            i2cDumpI2c(i2c);
-            i2cDumpInts(i2c->num);
+#if SOC_I2C_SUPPORT_RTC
+    {SOC_MOD_CLK_RC_FAST, periph_rtc_dig_clk8m_get_freq()}, /*!< I2C 20M RTC characteristic*/
 #endif
-        }
-    }
-
-    /* offloading all EventGroups to dispatch, EventGroups in ISR is not always successful
-     11/20/2017
-       if error, need to trigger all succeeding dataQueue events with the EVENT_ERROR_PREV
-     07/22/2018
-       Need to use the queueEvent value to identify transaction blocks, if an error occurs,
-       all subsequent queue items with the same queueEvent value will receive the EVENT_ERROR_PREV.
-       But, ProcQue should re-queue queue items that have a different queueEvent value(different transaction)
-       This change will support multi-thread i2c usage.  Use the queueEvent as the transaction event
-       identifier.
-    */
-    uint32_t b = 0;
-
-    while(b < i2c->queueCount) {
-        if(i2c->dq[b].ctrl.mode==1 && readCount) {
-            *readCount += i2c->dq[b].position; // number of data bytes received
-        }
-        if(b < i2c->queuePos) { // before any error
-            if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup
-                xEventGroupSetBits(i2c->dq[b].queueEvent,EVENT_DONE);
-            }
-        } else if(b == i2c->queuePos) { // last processed queue
-            if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup
-                xEventGroupSetBits(i2c->dq[b].queueEvent,eBits);
-            }
-        } else { // never processed queues
-            if(i2c->dq[b].queueEvent) { // this data queue element has an EventGroup
-                xEventGroupSetBits(i2c->dq[b].queueEvent,eBits|EVENT_ERROR_PREV);
-            }
-        }
-        b++;
-    }
-    if(i2c->debugFlags & 0x00ff0000) i2cTriggerDumps(i2c,(i2c->debugFlags>>16),"after ProcQueue");
-
-    I2C_MUTEX_UNLOCK();
-    return reason;
-}
-
-static void i2cReleaseISR(i2c_t * i2c)
-{
-    if(i2c->intr_handle) {
-        esp_intr_free(i2c->intr_handle);
-        i2c->intr_handle=NULL;
-        if (!removeApbChangeCallback( i2c, i2cApbChangeCallback)) {
-            log_e("unable to release apbCallback");
-        }
-    }
-}
-
-static bool i2cCheckLineState(int8_t sda, int8_t scl){
-     if(sda < 0 || scl < 0){
-        return false;//return false since there is nothing to do
-    }
-    // if the bus is not 'clear' try the cycling SCL until SDA goes High or 9 cycles
-    digitalWrite(sda, HIGH);
-    digitalWrite(scl, HIGH);
-    pinMode(sda, PULLUP|OPEN_DRAIN|INPUT);
-    pinMode(scl, PULLUP|OPEN_DRAIN|OUTPUT);
-
-    if(!digitalRead(sda) || !digitalRead(scl)) { // bus in busy state
-        log_w("invalid state sda(%d)=%d, scl(%d)=%d", sda, digitalRead(sda), scl, digitalRead(scl));
-        digitalWrite(scl, HIGH);
-        for(uint8_t a=0; a<9; a++) {
-            delayMicroseconds(5);
-            digitalWrite(scl, LOW);
-            delayMicroseconds(5);
-            digitalWrite(scl, HIGH);
-            if(digitalRead(sda)){ // bus recovered
-                log_d("Recovered after %d Cycles",a+1);
-                break;
-            }
-        }
-    }
-
-    if(!digitalRead(sda) || !digitalRead(scl)) { // bus in busy state
-        log_e("Bus Invalid State, TwoWire() Can't init sda=%d, scl=%d",digitalRead(sda),digitalRead(scl));
-        return false; // bus is busy
-    }
-    return true;
-}
-
-i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl)
-{
-    if(i2c == NULL) {
-        return I2C_ERROR_DEV;
-    }
-    digitalWrite(scl, HIGH);
-    pinMode(scl, OPEN_DRAIN | PULLUP | INPUT | OUTPUT);
-    pinMatrixOutAttach(scl, I2C_SCL_IDX(i2c->num), false, false);
-    pinMatrixInAttach(scl, I2C_SCL_IDX(i2c->num), false);
-    return I2C_ERROR_OK;
-}
-
-i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl)
-{
-    if(i2c == NULL) {
-        return I2C_ERROR_DEV;
-    }
-    pinMatrixOutDetach(scl, false, false);
-    pinMatrixInDetach(I2C_SCL_IDX(i2c->num), false, false);
-    pinMode(scl, INPUT | PULLUP);
-    return I2C_ERROR_OK;
-}
-
-i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda)
-{
-    if(i2c == NULL) {
-        return I2C_ERROR_DEV;
-    }
-    digitalWrite(sda, HIGH);
-    pinMode(sda, OPEN_DRAIN | PULLUP | INPUT | OUTPUT );
-    pinMatrixOutAttach(sda, I2C_SDA_IDX(i2c->num), false, false);
-    pinMatrixInAttach(sda, I2C_SDA_IDX(i2c->num), false);
-    return I2C_ERROR_OK;
-}
-
-i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda)
-{
-    if(i2c == NULL) {
-        return I2C_ERROR_DEV;
-    }
-    pinMatrixOutDetach(sda, false, false);
-    pinMatrixInDetach(I2C_SDA_IDX(i2c->num), false, false);
-    pinMode(sda, INPUT | PULLUP);
-    return I2C_ERROR_OK;
-}
-
-/*
- * PUBLIC API
- * */
-// 24Nov17 only supports Master Mode
-i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency) {
-#ifdef ENABLE_I2C_DEBUG_BUFFER
-  log_v("num=%d sda=%d scl=%d freq=%d",i2c_num, sda, scl, frequency);
+#if SOC_I2C_SUPPORT_REF_TICK
+    {SOC_MOD_CLK_REF_TICK, REF_CLK_FREQ}, /*!< I2C REF_TICK characteristic*/
 #endif
-    if(i2c_num > 1) {
-        return NULL;
-    }
-
-    i2c_t * i2c = &_i2c_bus_array[i2c_num];
+  };
 
-    // pins should be detached, else glitch
-    if(i2c->sda >= 0){
-        i2cDetachSDA(i2c, i2c->sda);
-    }
-    if(i2c->scl >= 0){
-        i2cDetachSCL(i2c, i2c->scl);
-    }
-    i2c->sda = sda;
-    i2c->scl = scl;
-
-#if !CONFIG_DISABLE_HAL_LOCKS
-    if(i2c->lock == NULL) {
-        i2c->lock = xSemaphoreCreateRecursiveMutex();
-        if(i2c->lock == NULL) {
-            return NULL;
-        }
+  i2c_sclk_t src_clk = I2C_SCLK_DEFAULT;
+  ret = ESP_OK;
+  for (i2c_sclk_t clk = I2C_SCLK_DEFAULT + 1; clk < I2C_SCLK_MAX; clk++) {
+#if CONFIG_IDF_TARGET_ESP32S3
+    if (clk == I2C_SCLK_RTC) {  // RTC clock for s3 is inaccessible now.
+      continue;
     }
 #endif
-    I2C_MUTEX_LOCK();
-
-    i2cReleaseISR(i2c); // ISR exists, release it before disabling hardware
-
-    if(frequency == 0) {// don't change existing frequency
-        frequency = i2cGetFrequency(i2c);
-        if(frequency == 0) {
-            frequency = 100000L;    // default to 100khz
-        }
-    }
-
-    if(i2c_num == 0) {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); //reset hardware
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST);//  release reset
-    } else {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); //reset Hardware
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST);
-    }
-    i2c->dev->ctr.val = 0;
-    i2c->dev->ctr.ms_mode = 1;
-    i2c->dev->ctr.sda_force_out = 1 ;
-    i2c->dev->ctr.scl_force_out = 1 ;
-    i2c->dev->ctr.clk_en = 1;
-
-    //the max clock number of receiving  a data
-    i2c->dev->timeout.tout = 400000;//clocks max=1048575
-    //disable apb nonfifo access
-    i2c->dev->fifo_conf.nonfifo_en = 0;
-
-    i2c->dev->slave_addr.val = 0;
-    I2C_MUTEX_UNLOCK();
-
-    i2cSetFrequency(i2c, frequency);    // reconfigure
-
-    if(!i2cCheckLineState(i2c->sda, i2c->scl)){
-        return NULL;
+    if (frequency <= i2c_clk_alloc[clk].clk_freq) {
+      src_clk = clk;
+      break;
+    }
+  }
+  if (src_clk == I2C_SCLK_DEFAULT || src_clk == I2C_SCLK_MAX) {
+    log_e("clock source could not be selected");
+    ret = ESP_FAIL;
+  } else {
+    i2c_hal_context_t hal;
+    hal.dev = I2C_LL_GET_HW(i2c_num);
+#if SOC_I2C_SUPPORT_RTC
+    if (src_clk == I2C_SCLK_RTC) {
+      periph_rtc_dig_clk8m_enable();
     }
-
-    if(i2c->sda >= 0){
-        i2cAttachSDA(i2c, i2c->sda);
-    }
-    if(i2c->scl >= 0){
-        i2cAttachSCL(i2c, i2c->scl);
-    }
-    return i2c;
-}
-
-void i2cRelease(i2c_t *i2c)  // release all resources, power down peripheral
-{
-    I2C_MUTEX_LOCK();
-
-    if(i2c->sda >= 0){
-        i2cDetachSDA(i2c, i2c->sda);
-    }
-    if(i2c->scl >= 0){
-        i2cDetachSCL(i2c, i2c->scl);
-    }
-
-    i2cReleaseISR(i2c);
-
-    if(i2c->i2c_event) {
-        vEventGroupDelete(i2c->i2c_event);
-        i2c->i2c_event = NULL;
-    }
-
-    i2cFlush(i2c);
-
-    // reset the I2C hardware and shut off the clock, power it down.
-    if(i2c->num == 0) {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT0_RST); //reset hardware
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT0_CLK_EN); // shutdown hardware
-    } else {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,DPORT_I2C_EXT1_RST); //reset Hardware
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,DPORT_I2C_EXT1_CLK_EN); // shutdown Hardware
-    }
-
-    I2C_MUTEX_UNLOCK();
-}
-
-i2c_err_t i2cFlush(i2c_t * i2c)
-{
-    if(i2c==NULL) {
-        return I2C_ERROR_DEV;
-    }
-    i2cTriggerDumps(i2c,i2c->debugFlags & 0xff, "FLUSH");
-
-    // need to grab a MUTEX for exclusive Queue,
-    // what out if ISR is running?
-    i2c_err_t rc=I2C_ERROR_OK;
-    if(i2c->dq!=NULL) {
-        //  log_i("free");
-        // what about EventHandle?
-        free(i2c->dq);
-        i2c->dq = NULL;
-    }
-    i2c->queueCount=0;
-    i2c->queuePos=0;
-    // release Mutex
-    return rc;
-}
-
-i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis){
-    if((i2c==NULL)||((size>0)&&(buff==NULL))) { // need to have location to store requested data
-        return I2C_ERROR_DEV;
-    }
-    i2c_err_t last_error = i2cAddQueueWrite(i2c, address, buff, size, sendStop, NULL);
-
-    if(last_error == I2C_ERROR_OK) { //queued
-        if(sendStop) { //now actually process the queued commands, including READs
-            last_error = i2cProcQueue(i2c, NULL, timeOutMillis);
-            if(last_error == I2C_ERROR_BUSY) { // try to clear the bus
-                if(i2cInit(i2c->num, i2c->sda, i2c->scl, 0)) {
-                    last_error = i2cProcQueue(i2c, NULL, timeOutMillis);
-                }
-            }
-            i2cFlush(i2c);
-        } else { // stop not received, so wait for I2C stop,
-            last_error = I2C_ERROR_CONTINUE;
-        }
-    }
-    return last_error;
-}
-
-i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount){
-    if((size == 0)||(i2c == NULL)||(buff==NULL)){ // hardware will hang if no data requested on READ
-        return I2C_ERROR_DEV;
-    }
-    i2c_err_t last_error=i2cAddQueueRead(i2c, address, buff, size, sendStop, NULL);
-
-    if(last_error == I2C_ERROR_OK) { //queued
-        if(sendStop) { //now actually process the queued commands, including READs
-            last_error = i2cProcQueue(i2c, readCount, timeOutMillis);
-            if(last_error == I2C_ERROR_BUSY) { // try to clear the bus
-                if(i2cInit(i2c->num, i2c->sda, i2c->scl, 0)) {
-                    last_error = i2cProcQueue(i2c, readCount, timeOutMillis);
-                }
-            }
-            i2cFlush(i2c);
-        } else { // stop not received, so wait for I2C stop,
-            last_error = I2C_ERROR_CONTINUE;
-        }
-    }
-    return last_error;
-}
-
-#define MIN_I2C_CLKS 100              // minimum ratio between cpu and i2c Bus clocks
-#define INTERRUPT_CYCLE_OVERHEAD 16000 // number of cpu clocks necessary to respond to interrupt
-i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed)
-{
-    if(i2c == NULL) {
-        return I2C_ERROR_DEV;
-    }
-    uint32_t apb = getApbFrequency(); 
-    uint32_t period = (apb/clk_speed) / 2;
-
-    if((apb/8192 > clk_speed)||(apb/MIN_I2C_CLKS < clk_speed)){ //out of bounds
-        log_d("i2c freq(%d) out of bounds.vs APB Clock(%d), min=%d, max=%d",clk_speed,apb,(apb/8192),(apb/MIN_I2C_CLKS));
-    }
-    if(period < (MIN_I2C_CLKS/2) ){
-        period = (MIN_I2C_CLKS/2);
-        clk_speed = apb/(period*2);
-        log_d("APB Freq too slow, Reducing i2c Freq to %d Hz",clk_speed);
-    } else if ( period> 4095) {
-        period = 4095;
-        clk_speed = apb/(period*2);
-        log_d("APB Freq too fast, Increasing i2c Freq to %d Hz",clk_speed);
+#endif
+    I2C_CLOCK_SRC_ATOMIC() {
+      i2c_hal_set_bus_timing(&(hal), frequency, i2c_clk_alloc[src_clk].clk, i2c_clk_alloc[src_clk].clk_freq);
     }
-#ifdef ENABLE_I2C_DEBUG_BUFFER
-    log_v("freq=%dHz",clk_speed);
-#endif      
-    uint32_t halfPeriod = period/2;
-    uint32_t quarterPeriod = period/4;
-
-    I2C_MUTEX_LOCK();
-
-    I2C_FIFO_CONF_t f;
+    bus[i2c_num].frequency = frequency;
+    //Clock Stretching Timeout: 20b:esp32, 5b:esp32-c3, 24b:esp32-s2
+    i2c_set_timeout((i2c_port_t)i2c_num, I2C_LL_MAX_TIMEOUT);
+  }
 
-    f.val    = i2c->dev->fifo_conf.val;
-/*  Adjust Fifo thresholds based on differential between cpu frequency and bus clock.
-    The fifo_delta is calculated such that at least INTERRUPT_CYCLE_OVERHEAD cpu clocks are
-    available when a Fifo interrupt is triggered.  This allows enough room in the Fifo so that
-    interrupt latency does not cause a Fifo overflow/underflow event.
-*/
-#ifdef ENABLE_I2C_DEBUG_BUFFER
-    log_v("cpu Freq=%dMhz, i2c Freq=%dHz",getCpuFrequencyMhz(),clk_speed);
-#endif
-    uint32_t fifo_delta = (INTERRUPT_CYCLE_OVERHEAD/((getCpuFrequencyMhz()*1000000 / clk_speed)*10))+1; 
-    if (fifo_delta > 24) fifo_delta=24;   
-    f.rx_fifo_full_thrhd = 32 - fifo_delta;
-    f.tx_fifo_empty_thrhd = fifo_delta;
-    i2c->dev->fifo_conf.val = f.val; // set thresholds
-#ifdef ENABLE_I2C_DEBUG_BUFFER
-    log_v("Fifo delta=%d",fifo_delta);
+end:
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(bus[i2c_num].lock);
 #endif
-    //the clock num during SCL is low level
-    i2c->dev->scl_low_period.period = period;
-    //the clock num during SCL is high level
-    i2c->dev->scl_high_period.period = period;
-
-    //the clock num between the negedge of SDA and negedge of SCL for start mark
-    i2c->dev->scl_start_hold.time = halfPeriod;
-    //the clock num between the posedge of SCL and the negedge of SDA for restart mark
-    i2c->dev->scl_rstart_setup.time = halfPeriod;
-
-    //the clock num after the STOP bit's posedge
-    i2c->dev->scl_stop_hold.time = halfPeriod;
-    //the clock num between the posedge of SCL and the posedge of SDA
-    i2c->dev->scl_stop_setup.time = halfPeriod;
-
-    //the clock num I2C used to hold the data after the negedge of SCL.
-    i2c->dev->sda_hold.time = quarterPeriod;
-    //the clock num I2C used to sample data on SDA after the posedge of SCL
-    i2c->dev->sda_sample.time = quarterPeriod;
-    I2C_MUTEX_UNLOCK();
-    return I2C_ERROR_OK;
-}
-
-uint32_t i2cGetFrequency(i2c_t * i2c)
-{
-    if(i2c == NULL) {
-        return 0;
-    }
-    uint32_t result = 0;
-    uint32_t old_count = (i2c->dev->scl_low_period.period+i2c->dev->scl_high_period.period);
-    if(old_count>0) {
-        result = getApbFrequency() / old_count;
-    } else {
-        result = 0;
-    }
-    return result;
+  return ret;
 }
 
-
-uint32_t i2cDebug(i2c_t * i2c, uint32_t setBits, uint32_t resetBits){
-    if(i2c != NULL) {
-        i2c->debugFlags = ((i2c->debugFlags | setBits) & ~resetBits);
-        return i2c->debugFlags;
-    }
-    return 0;
-    
- }
- 
-uint32_t i2cGetStatus(i2c_t * i2c){
-    if(i2c != NULL){
-        return i2c->dev->status_reg.val;
-    }
-    else return 0;
+esp_err_t i2cGetClock(uint8_t i2c_num, uint32_t *frequency) {
+  if (i2c_num >= SOC_I2C_NUM) {
+    return ESP_ERR_INVALID_ARG;
+  }
+  if (!bus[i2c_num].initialized) {
+    log_e("bus is not initialized");
+    return ESP_FAIL;
+  }
+  *frequency = bus[i2c_num].frequency;
+  return ESP_OK;
 }
 
-
-/* todo
-  22JUL18
-    need to add multi-thread capability, use dq.queueEvent as the group marker. When multiple threads
-    transactions are present in the same queue, and an error occurs, abort all succeeding unserviced transactions
-    with the same dq.queueEvent value.  Succeeding unserviced transactions with different dq.queueEvent values
-    can be re-queued and processed independently. 
-  30JUL18 complete data only queue elements, this will allow transfers to use multiple data blocks, 
- */
-
+#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 4, 0) */
+#endif /* SOC_I2C_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-i2c.h b/cores/esp32/esp32-hal-i2c.h
index 1a696aca7d6..35783d350b0 100644
--- a/cores/esp32/esp32-hal-i2c.h
+++ b/cores/esp32/esp32-hal-i2c.h
@@ -12,71 +12,36 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 // modified Nov 2017 by Chuck Todd <StickBreaker> to support Interrupt Driven I/O
+// modified Nov 2021 by Hristo Gochkov <Me-No-Dev> to support ESP-IDF API
 
 #ifndef _ESP32_HAL_I2C_H_
 #define _ESP32_HAL_I2C_H_
 
+#include "soc/soc_caps.h"
+#if SOC_I2C_SUPPORTED
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #include <stdint.h>
 #include <stdbool.h>
-#include "freertos/FreeRTOS.h"
-#include "freertos/event_groups.h"
-
-// External Wire.h equivalent error Codes
-typedef enum {
-    I2C_ERROR_OK=0,
-    I2C_ERROR_DEV,
-    I2C_ERROR_ACK,
-    I2C_ERROR_TIMEOUT,
-    I2C_ERROR_BUS,
-    I2C_ERROR_BUSY,
-    I2C_ERROR_MEMORY,
-    I2C_ERROR_CONTINUE,
-    I2C_ERROR_NO_BEGIN
-} i2c_err_t;
-
-struct i2c_struct_t;
-typedef struct i2c_struct_t i2c_t;
-
-i2c_t * i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t clk_speed);
-void i2cRelease(i2c_t *i2c); // free ISR, Free DQ, Power off peripheral clock.  Must call i2cInit() to recover
-i2c_err_t i2cWrite(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis);
-i2c_err_t i2cRead(i2c_t * i2c, uint16_t address, uint8_t* buff, uint16_t size, bool sendStop, uint16_t timeOutMillis, uint32_t *readCount);
-i2c_err_t i2cFlush(i2c_t *i2c);
-i2c_err_t i2cSetFrequency(i2c_t * i2c, uint32_t clk_speed);
-uint32_t i2cGetFrequency(i2c_t * i2c);
-uint32_t i2cGetStatus(i2c_t * i2c); // Status register of peripheral
-
-//Functions below should be used only if well understood
-//Might be deprecated and removed in future
-i2c_err_t i2cAttachSCL(i2c_t * i2c, int8_t scl);
-i2c_err_t i2cDetachSCL(i2c_t * i2c, int8_t scl);
-i2c_err_t i2cAttachSDA(i2c_t * i2c, int8_t sda);
-i2c_err_t i2cDetachSDA(i2c_t * i2c, int8_t sda);
-
-//Stickbreakers ISR Support
-i2c_err_t i2cProcQueue(i2c_t *i2c, uint32_t *readCount, uint16_t timeOutMillis);
-i2c_err_t i2cAddQueueWrite(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event);
-i2c_err_t i2cAddQueueRead(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr, uint16_t dataLen, bool SendStop, EventGroupHandle_t event);
-
-//stickbreaker debug support
-uint32_t i2cDebug(i2c_t *, uint32_t setBits, uint32_t resetBits);
-//  Debug actions have 3 currently defined locus 
-// 0xXX------ : at entry of ProcQueue 
-// 0x--XX---- : at exit of ProcQueue
-// 0x------XX : at entry of Flush
-// 
-// bit 0 causes DumpI2c to execute 
-// bit 1 causes DumpInts to execute
-// bit 2 causes DumpCmdqueue to execute
-// bit 3 causes DumpStatus to execute
-// bit 4 causes DumpFifo to execute
+#include <esp_err.h>
+
+esp_err_t i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t clk_speed);
+esp_err_t i2cDeinit(uint8_t i2c_num);
+esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency);
+esp_err_t i2cGetClock(uint8_t i2c_num, uint32_t *frequency);
+esp_err_t i2cWrite(uint8_t i2c_num, uint16_t address, const uint8_t *buff, size_t size, uint32_t timeOutMillis);
+esp_err_t i2cRead(uint8_t i2c_num, uint16_t address, uint8_t *buff, size_t size, uint32_t timeOutMillis, size_t *readCount);
+esp_err_t i2cWriteReadNonStop(
+  uint8_t i2c_num, uint16_t address, const uint8_t *wbuff, size_t wsize, uint8_t *rbuff, size_t rsize, uint32_t timeOutMillis, size_t *readCount
+);
+bool i2cIsInit(uint8_t i2c_num);
 
 #ifdef __cplusplus
 }
 #endif
 
+#endif /* SOC_I2C_SUPPORTED */
 #endif /* _ESP32_HAL_I2C_H_ */
diff --git a/cores/esp32/esp32-hal-ledc.c b/cores/esp32/esp32-hal-ledc.c
index 24bbf329404..039fa1312f1 100644
--- a/cores/esp32/esp32-hal-ledc.c
+++ b/cores/esp32/esp32-hal-ledc.c
@@ -1,4 +1,4 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2023 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -12,269 +12,484 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+#include "soc/soc_caps.h"
+
+#if SOC_LEDC_SUPPORTED
 #include "esp32-hal.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/semphr.h"
-#include "rom/ets_sys.h"
-#include "esp32-hal-matrix.h"
-#include "soc/dport_reg.h"
-#include "soc/ledc_reg.h"
-#include "soc/ledc_struct.h"
-
-#if CONFIG_DISABLE_HAL_LOCKS
-#define LEDC_MUTEX_LOCK()
-#define LEDC_MUTEX_UNLOCK()
+#include "esp32-hal-ledc.h"
+#include "driver/ledc.h"
+#include "esp32-hal-periman.h"
+#include "soc/gpio_sig_map.h"
+#include "esp_rom_gpio.h"
+#include "hal/ledc_ll.h"
+
+#ifdef SOC_LEDC_SUPPORT_HS_MODE
+#define LEDC_CHANNELS (SOC_LEDC_CHANNEL_NUM << 1)
 #else
-#define LEDC_MUTEX_LOCK()    do {} while (xSemaphoreTake(_ledc_sys_lock, portMAX_DELAY) != pdPASS)
-#define LEDC_MUTEX_UNLOCK()  xSemaphoreGive(_ledc_sys_lock)
-xSemaphoreHandle _ledc_sys_lock = NULL;
+#define LEDC_CHANNELS (SOC_LEDC_CHANNEL_NUM)
 #endif
 
-/*
- * LEDC Chan to Group/Channel/Timer Mapping
-** ledc: 0  => Group: 0, Channel: 0, Timer: 0
-** ledc: 1  => Group: 0, Channel: 1, Timer: 0
-** ledc: 2  => Group: 0, Channel: 2, Timer: 1
-** ledc: 3  => Group: 0, Channel: 3, Timer: 1
-** ledc: 4  => Group: 0, Channel: 4, Timer: 2
-** ledc: 5  => Group: 0, Channel: 5, Timer: 2
-** ledc: 6  => Group: 0, Channel: 6, Timer: 3
-** ledc: 7  => Group: 0, Channel: 7, Timer: 3
-** ledc: 8  => Group: 1, Channel: 0, Timer: 0
-** ledc: 9  => Group: 1, Channel: 1, Timer: 0
-** ledc: 10 => Group: 1, Channel: 2, Timer: 1
-** ledc: 11 => Group: 1, Channel: 3, Timer: 1
-** ledc: 12 => Group: 1, Channel: 4, Timer: 2
-** ledc: 13 => Group: 1, Channel: 5, Timer: 2
-** ledc: 14 => Group: 1, Channel: 6, Timer: 3
-** ledc: 15 => Group: 1, Channel: 7, Timer: 3
-*/
-#define LEDC_CHAN(g,c) LEDC.channel_group[(g)].channel[(c)]
-#define LEDC_TIMER(g,t) LEDC.timer_group[(g)].timer[(t)]
-
-static void _on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb){
-    if(ev_type == APB_AFTER_CHANGE && old_apb != new_apb){
-        uint16_t iarg = *(uint16_t*)arg;
-        uint8_t chan = 0;
-        old_apb /= 1000000;
-        new_apb /= 1000000;
-        while(iarg){ // run though all active channels, adjusting timing configurations
-            if(iarg & 1) {// this channel is active
-                uint8_t group=(chan/8), timer=((chan/2)%4);
-                if(LEDC_TIMER(group, timer).conf.tick_sel){
-                    LEDC_MUTEX_LOCK();
-                    uint32_t old_div = LEDC_TIMER(group, timer).conf.clock_divider;
-                    uint32_t div_num = (new_apb * old_div) / old_apb;
-                    if(div_num > LEDC_DIV_NUM_HSTIMER0_V){
-                        div_num = ((REF_CLK_FREQ /1000000) * old_div) / old_apb;
-                        if(div_num > LEDC_DIV_NUM_HSTIMER0_V) {
-                            div_num = LEDC_DIV_NUM_HSTIMER0_V;//lowest clock possible
-                        }
-                        LEDC_TIMER(group, timer).conf.tick_sel = 0;
-                    } else if(div_num < 256) {
-                        div_num = 256;//highest clock possible
-                    }
-                    LEDC_TIMER(group, timer).conf.clock_divider = div_num;
-                    LEDC_MUTEX_UNLOCK();
-                }
-                else {
-                    log_d("using REF_CLK chan=%d",chan);
-                }
-            }
-            iarg = iarg >> 1;
-            chan++;
-        }
-    }
+//Use XTAL clock if possible to avoid timer frequency error when setting APB clock < 80 Mhz
+//Need to be fixed in ESP-IDF
+#ifdef SOC_LEDC_SUPPORT_XTAL_CLOCK
+#define LEDC_DEFAULT_CLK LEDC_USE_XTAL_CLK
+#else
+#define LEDC_DEFAULT_CLK LEDC_AUTO_CLK
+#endif
+
+#define LEDC_MAX_BIT_WIDTH SOC_LEDC_TIMER_BIT_WIDTH
+
+typedef struct {
+  int used_channels : LEDC_CHANNELS;  // Used channels as a bits
+} ledc_periph_t;
+
+ledc_periph_t ledc_handle = {0};
+
+static bool fade_initialized = false;
+
+static ledc_clk_cfg_t clock_source = LEDC_DEFAULT_CLK;
+
+ledc_clk_cfg_t ledcGetClockSource(void) {
+  return clock_source;
 }
 
-//uint32_t frequency = (80MHz or 1MHz)/((div_num / 256.0)*(1 << bit_num));
-static void _ledcSetupTimer(uint8_t chan, uint32_t div_num, uint8_t bit_num, bool apb_clk)
-{
-    uint8_t group=(chan/8), timer=((chan/2)%4);
-    static bool tHasStarted = false;
-    static uint16_t _activeChannels = 0;
-    if(!tHasStarted) {
-        tHasStarted = true;
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
-        LEDC.conf.apb_clk_sel = 1;//LS use apb clock
-        addApbChangeCallback((void*)&_activeChannels, _on_apb_change);
+bool ledcSetClockSource(ledc_clk_cfg_t source) {
+  if (ledc_handle.used_channels) {
+    log_e("Cannot change LEDC clock source! LEDC channels in use.");
+    return false;
+  }
+  clock_source = source;
+  return true;
+}
 
-#if !CONFIG_DISABLE_HAL_LOCKS
-        _ledc_sys_lock = xSemaphoreCreateMutex();
-#endif
+static bool ledcDetachBus(void *bus) {
+  ledc_channel_handle_t *handle = (ledc_channel_handle_t *)bus;
+  bool channel_found = false;
+  // Check if more pins are attached to the same ledc channel
+  for (uint8_t i = 0; i < SOC_GPIO_PIN_COUNT; i++) {
+    if (!perimanPinIsValid(i) || i == handle->pin) {
+      continue;  //invalid pin or same pin
     }
-    LEDC_MUTEX_LOCK();
-    LEDC_TIMER(group, timer).conf.clock_divider = div_num;//18 bit (10.8) This register is used to configure parameter for divider in timer the least significant eight bits represent the decimal part.
-    LEDC_TIMER(group, timer).conf.duty_resolution = bit_num;//5 bit This register controls the range of the counter in timer. the counter range is [0 2**bit_num] the max bit width for counter is 20.
-    LEDC_TIMER(group, timer).conf.tick_sel = apb_clk;//apb clock
-    if(group) {
-        LEDC_TIMER(group, timer).conf.low_speed_update = 1;//This bit is only useful for low speed timer channels, reserved for high speed timers
+    peripheral_bus_type_t type = perimanGetPinBusType(i);
+    if (type == ESP32_BUS_TYPE_LEDC) {
+      ledc_channel_handle_t *bus_check = (ledc_channel_handle_t *)perimanGetPinBus(i, ESP32_BUS_TYPE_LEDC);
+      if (bus_check->channel == handle->channel) {
+        channel_found = true;
+        break;
+      }
     }
-    LEDC_TIMER(group, timer).conf.pause = 0;
-    LEDC_TIMER(group, timer).conf.rst = 1;//This bit is used to reset timer the counter will be 0 after reset.
-    LEDC_TIMER(group, timer).conf.rst = 0;
-    LEDC_MUTEX_UNLOCK();
-    _activeChannels |= (1 << chan); // mark as active for APB callback
+  }
+  pinMatrixOutDetach(handle->pin, false, false);
+  if (!channel_found) {
+    ledc_handle.used_channels &= ~(1UL << handle->channel);
+  }
+  free(handle);
+  if (ledc_handle.used_channels == 0) {
+    ledc_fade_func_uninstall();
+    fade_initialized = false;
+  }
+  return true;
 }
 
-//max div_num 0x3FFFF (262143)
-//max bit_num 0x1F (31)
-static double _ledcSetupTimerFreq(uint8_t chan, double freq, uint8_t bit_num)
-{
-    uint64_t clk_freq = getApbFrequency();
-    clk_freq <<= 8;//div_num is 8 bit decimal
-    uint32_t div_num = (clk_freq >> bit_num) / freq;
-    bool apb_clk = true;
-    if(div_num > LEDC_DIV_NUM_HSTIMER0_V) {
-        clk_freq /= 80;
-        div_num = (clk_freq >> bit_num) / freq;
-        if(div_num > LEDC_DIV_NUM_HSTIMER0_V) {
-            div_num = LEDC_DIV_NUM_HSTIMER0_V;//lowest clock possible
-        }
-        apb_clk = false;
-    } else if(div_num < 256) {
-        div_num = 256;//highest clock possible
+bool ledcAttachChannel(uint8_t pin, uint32_t freq, uint8_t resolution, uint8_t channel) {
+  if (channel >= LEDC_CHANNELS) {
+    log_e("Channel %u is not available (maximum %u)!", channel, LEDC_CHANNELS);
+    return false;
+  }
+  if (freq == 0) {
+    log_e("LEDC pin %u - frequency can't be zero.", pin);
+    return false;
+  }
+  if (resolution == 0 || resolution > LEDC_MAX_BIT_WIDTH) {
+    log_e("LEDC pin %u - resolution is zero or it is too big (maximum %u)", pin, LEDC_MAX_BIT_WIDTH);
+    return false;
+  }
+
+  perimanSetBusDeinit(ESP32_BUS_TYPE_LEDC, ledcDetachBus);
+  ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+  if (bus != NULL) {
+    log_e("Pin %u is already attached to LEDC (channel %u, resolution %u)", pin, bus->channel, bus->channel_resolution);
+    return false;
+  }
+
+  if (!perimanClearPinBus(pin)) {
+    log_e("Pin %u is already attached to another bus and failed to detach", pin);
+    return false;
+  }
+
+  uint8_t group = (channel / 8), timer = ((channel / 2) % 4);
+  bool channel_used = ledc_handle.used_channels & (1UL << channel);
+  if (channel_used) {
+    log_i("Channel %u is already set up, given frequency and resolution will be ignored", channel);
+    if (ledc_set_pin(pin, group, channel % 8) != ESP_OK) {
+      log_e("Attaching pin to already used channel failed!");
+      return false;
     }
-    _ledcSetupTimer(chan, div_num, bit_num, apb_clk);
-    //log_i("Fin: %f, Fclk: %uMhz, bits: %u, DIV: %u, Fout: %f",
-    //        freq, apb_clk?80:1, bit_num, div_num, (clk_freq >> bit_num) / (double)div_num);
-    return (clk_freq >> bit_num) / (double)div_num;
+  } else {
+    ledc_timer_config_t ledc_timer;
+    memset((void *)&ledc_timer, 0, sizeof(ledc_timer_config_t));
+    ledc_timer.speed_mode = group;
+    ledc_timer.timer_num = timer;
+    ledc_timer.duty_resolution = resolution;
+    ledc_timer.freq_hz = freq;
+    ledc_timer.clk_cfg = clock_source;
+
+    if (ledc_timer_config(&ledc_timer) != ESP_OK) {
+      log_e("ledc setup failed!");
+      return false;
+    }
+
+    uint32_t duty = ledc_get_duty(group, (channel % 8));
+
+    ledc_channel_config_t ledc_channel;
+    memset((void *)&ledc_channel, 0, sizeof(ledc_channel_config_t));
+    ledc_channel.speed_mode = group;
+    ledc_channel.channel = (channel % 8);
+    ledc_channel.timer_sel = timer;
+    ledc_channel.intr_type = LEDC_INTR_DISABLE;
+    ledc_channel.gpio_num = pin;
+    ledc_channel.duty = duty;
+    ledc_channel.hpoint = 0;
+
+    ledc_channel_config(&ledc_channel);
+  }
+
+  ledc_channel_handle_t *handle = (ledc_channel_handle_t *)malloc(sizeof(ledc_channel_handle_t));
+  handle->pin = pin;
+  handle->channel = channel;
+#ifndef SOC_LEDC_SUPPORT_FADE_STOP
+  handle->lock = NULL;
+#endif
+
+  //get resolution of selected channel when used
+  if (channel_used) {
+    uint32_t channel_resolution = 0;
+    ledc_ll_get_duty_resolution(LEDC_LL_GET_HW(), group, timer, &channel_resolution);
+    log_i("Channel %u frequency: %u, resolution: %u", channel, ledc_get_freq(group, timer), channel_resolution);
+    handle->channel_resolution = (uint8_t)channel_resolution;
+  } else {
+    handle->channel_resolution = resolution;
+    ledc_handle.used_channels |= 1UL << channel;
+  }
+
+  if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_LEDC, (void *)handle, group, channel)) {
+    ledcDetachBus((void *)handle);
+    return false;
+  }
+
+  log_i("LEDC attached to pin %u (channel %u, resolution %u)", pin, channel, resolution);
+  return true;
+}
+
+bool ledcAttach(uint8_t pin, uint32_t freq, uint8_t resolution) {
+  int free_channel = ~ledc_handle.used_channels & (ledc_handle.used_channels + 1);
+  if (free_channel == 0) {
+    log_e("No more LEDC channels available! (maximum is %u channels)", LEDC_CHANNELS);
+    return false;
+  }
+  uint8_t channel = __builtin_ctz(free_channel);  // Convert the free_channel bit to channel number
+
+  return ledcAttachChannel(pin, freq, resolution, channel);
 }
 
-static double _ledcTimerRead(uint8_t chan)
-{
-    uint32_t div_num;
-    uint8_t bit_num;
-    bool apb_clk;
-    uint8_t group=(chan/8), timer=((chan/2)%4);
-    LEDC_MUTEX_LOCK();
-    div_num = LEDC_TIMER(group, timer).conf.clock_divider;//18 bit (10.8) This register is used to configure parameter for divider in timer the least significant eight bits represent the decimal part.
-    bit_num = LEDC_TIMER(group, timer).conf.duty_resolution;//5 bit This register controls the range of the counter in timer. the counter range is [0 2**bit_num] the max bit width for counter is 20.
-    apb_clk = LEDC_TIMER(group, timer).conf.tick_sel;//apb clock
-    LEDC_MUTEX_UNLOCK();
-    uint64_t clk_freq = 1000000;
-    if(apb_clk) {
-        clk_freq = getApbFrequency();
+bool ledcWrite(uint8_t pin, uint32_t duty) {
+  ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+  if (bus != NULL) {
+
+    uint8_t group = (bus->channel / 8), channel = (bus->channel % 8);
+
+    //Fixing if all bits in resolution is set = LEDC FULL ON
+    uint32_t max_duty = (1 << bus->channel_resolution) - 1;
+
+    if ((duty == max_duty) && (max_duty != 1)) {
+      duty = max_duty + 1;
     }
-    clk_freq <<= 8;//div_num is 8 bit decimal
-    return (clk_freq >> bit_num) / (double)div_num;
+
+    ledc_set_duty(group, channel, duty);
+    ledc_update_duty(group, channel);
+
+    return true;
+  }
+  return false;
 }
 
-static void _ledcSetupChannel(uint8_t chan, uint8_t idle_level)
-{
-    uint8_t group=(chan/8), channel=(chan%8), timer=((chan/2)%4);
-    LEDC_MUTEX_LOCK();
-    LEDC_CHAN(group, channel).conf0.timer_sel = timer;//2 bit Selects the timer to attach 0-3
-    LEDC_CHAN(group, channel).conf0.idle_lv = idle_level;//1 bit This bit is used to control the output value when channel is off.
-    LEDC_CHAN(group, channel).hpoint.hpoint = 0;//20 bit The output value changes to high when timer selected by channel has reached hpoint
-    LEDC_CHAN(group, channel).conf1.duty_inc = 1;//1 bit This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel
-    LEDC_CHAN(group, channel).conf1.duty_num = 1;//10 bit This register is used to control the number of increased or decreased times for channel
-    LEDC_CHAN(group, channel).conf1.duty_cycle = 1;//10 bit This register is used to increase or decrease the duty every duty_cycle cycles for channel
-    LEDC_CHAN(group, channel).conf1.duty_scale = 0;//10 bit This register controls the increase or decrease step scale for channel.
-    LEDC_CHAN(group, channel).duty.duty = 0;
-    LEDC_CHAN(group, channel).conf0.sig_out_en = 0;//This is the output enable control bit for channel
-    LEDC_CHAN(group, channel).conf1.duty_start = 0;//When duty_num duty_cycle and duty_scale has been configured. these register won't take effect until set duty_start. this bit is automatically cleared by hardware.
-    if(group) {
-        LEDC_CHAN(group, channel).conf0.low_speed_update = 1;
-    } else {
-        LEDC_CHAN(group, channel).conf0.clk_en = 0;
+bool ledcWriteChannel(uint8_t channel, uint32_t duty) {
+  //check if channel is valid and used
+  if (channel >= LEDC_CHANNELS || !(ledc_handle.used_channels & (1UL << channel))) {
+    log_e("Channel %u is not available (maximum %u) or not used!", channel, LEDC_CHANNELS);
+    return false;
+  }
+  uint8_t group = (channel / 8), timer = ((channel / 2) % 4);
+
+  //Fixing if all bits in resolution is set = LEDC FULL ON
+  uint32_t resolution = 0;
+  ledc_ll_get_duty_resolution(LEDC_LL_GET_HW(), group, timer, &resolution);
+
+  uint32_t max_duty = (1 << resolution) - 1;
+
+  if ((duty == max_duty) && (max_duty != 1)) {
+    duty = max_duty + 1;
+  }
+
+  ledc_set_duty(group, channel, duty);
+  ledc_update_duty(group, channel);
+
+  return true;
+}
+
+uint32_t ledcRead(uint8_t pin) {
+  ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+  if (bus != NULL) {
+
+    uint8_t group = (bus->channel / 8), channel = (bus->channel % 8);
+    return ledc_get_duty(group, channel);
+  }
+  return 0;
+}
+
+uint32_t ledcReadFreq(uint8_t pin) {
+  ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+  if (bus != NULL) {
+    if (!ledcRead(pin)) {
+      return 0;
     }
-    LEDC_MUTEX_UNLOCK();
+    uint8_t group = (bus->channel / 8), timer = ((bus->channel / 2) % 4);
+    return ledc_get_freq(group, timer);
+  }
+  return 0;
 }
 
-double ledcSetup(uint8_t chan, double freq, uint8_t bit_num)
-{
-    if(chan > 15) {
-        return 0;
+uint32_t ledcWriteTone(uint8_t pin, uint32_t freq) {
+  ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+  if (bus != NULL) {
+
+    if (!freq) {
+      ledcWrite(pin, 0);
+      return 0;
     }
-    double res_freq = _ledcSetupTimerFreq(chan, freq, bit_num);
-    _ledcSetupChannel(chan, LOW);
+
+    uint8_t group = (bus->channel / 8), timer = ((bus->channel / 2) % 4);
+
+    ledc_timer_config_t ledc_timer;
+    memset((void *)&ledc_timer, 0, sizeof(ledc_timer_config_t));
+    ledc_timer.speed_mode = group;
+    ledc_timer.timer_num = timer;
+    ledc_timer.duty_resolution = 10;
+    ledc_timer.freq_hz = freq;
+    ledc_timer.clk_cfg = clock_source;
+
+    if (ledc_timer_config(&ledc_timer) != ESP_OK) {
+      log_e("ledcWriteTone configuration failed!");
+      return 0;
+    }
+    bus->channel_resolution = 10;
+
+    uint32_t res_freq = ledc_get_freq(group, timer);
+    ledcWrite(pin, 0x1FF);
     return res_freq;
+  }
+  return 0;
 }
 
-void ledcWrite(uint8_t chan, uint32_t duty)
-{
-    if(chan > 15) {
-        return;
+uint32_t ledcWriteNote(uint8_t pin, note_t note, uint8_t octave) {
+  const uint16_t noteFrequencyBase[12] = {//   C        C#       D        Eb       E        F       F#        G       G#        A       Bb        B
+                                          4186, 4435, 4699, 4978, 5274, 5588, 5920, 6272, 6645, 7040, 7459, 7902
+  };
+
+  if (octave > 8 || note >= NOTE_MAX) {
+    return 0;
+  }
+  uint32_t noteFreq = (uint32_t)noteFrequencyBase[note] / (uint32_t)(1 << (8 - octave));
+  return ledcWriteTone(pin, noteFreq);
+}
+
+bool ledcDetach(uint8_t pin) {
+  ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+  if (bus != NULL) {
+    // will call ledcDetachBus
+    return perimanClearPinBus(pin);
+  } else {
+    log_e("pin %u is not attached to LEDC", pin);
+  }
+  return false;
+}
+
+uint32_t ledcChangeFrequency(uint8_t pin, uint32_t freq, uint8_t resolution) {
+  ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+  if (bus != NULL) {
+    if (freq == 0) {
+      log_e("LEDC pin %u - frequency can't be zero.", pin);
+      return 0;
     }
-    uint8_t group=(chan/8), channel=(chan%8);
-    LEDC_MUTEX_LOCK();
-    LEDC_CHAN(group, channel).duty.duty = duty << 4;//25 bit (21.4)
-    if(duty) {
-        LEDC_CHAN(group, channel).conf0.sig_out_en = 1;//This is the output enable control bit for channel
-        LEDC_CHAN(group, channel).conf1.duty_start = 1;//When duty_num duty_cycle and duty_scale has been configured. these register won't take effect until set duty_start. this bit is automatically cleared by hardware.
-        if(group) {
-            LEDC_CHAN(group, channel).conf0.low_speed_update = 1;
-        } else {
-            LEDC_CHAN(group, channel).conf0.clk_en = 1;
-        }
-    } else {
-        LEDC_CHAN(group, channel).conf0.sig_out_en = 0;//This is the output enable control bit for channel
-        LEDC_CHAN(group, channel).conf1.duty_start = 0;//When duty_num duty_cycle and duty_scale has been configured. these register won't take effect until set duty_start. this bit is automatically cleared by hardware.
-        if(group) {
-            LEDC_CHAN(group, channel).conf0.low_speed_update = 1;
-        } else {
-            LEDC_CHAN(group, channel).conf0.clk_en = 0;
-        }
+    if (resolution == 0 || resolution > LEDC_MAX_BIT_WIDTH) {
+      log_e("LEDC pin %u - resolution is zero or it is too big (maximum %u)", pin, LEDC_MAX_BIT_WIDTH);
+      return 0;
     }
-    LEDC_MUTEX_UNLOCK();
-}
+    uint8_t group = (bus->channel / 8), timer = ((bus->channel / 2) % 4);
 
-uint32_t ledcRead(uint8_t chan)
-{
-    if(chan > 15) {
-        return 0;
+    ledc_timer_config_t ledc_timer;
+    memset((void *)&ledc_timer, 0, sizeof(ledc_timer_config_t));
+    ledc_timer.speed_mode = group;
+    ledc_timer.timer_num = timer;
+    ledc_timer.duty_resolution = resolution;
+    ledc_timer.freq_hz = freq;
+    ledc_timer.clk_cfg = clock_source;
+
+    if (ledc_timer_config(&ledc_timer) != ESP_OK) {
+      log_e("ledcChangeFrequency failed!");
+      return 0;
     }
-    return LEDC.channel_group[chan/8].channel[chan%8].duty.duty >> 4;
+    bus->channel_resolution = resolution;
+    return ledc_get_freq(group, timer);
+  }
+  return 0;
 }
 
-double ledcReadFreq(uint8_t chan)
-{
-    if(!ledcRead(chan)){
-        return 0;
+bool ledcOutputInvert(uint8_t pin, bool out_invert) {
+  ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+  if (bus != NULL) {
+    gpio_set_level(pin, out_invert);
+
+#ifdef CONFIG_IDF_TARGET_ESP32P4
+    esp_rom_gpio_connect_out_signal(pin, LEDC_LS_SIG_OUT_PAD_OUT0_IDX + ((bus->channel) % 8), out_invert, 0);
+#else
+#ifdef SOC_LEDC_SUPPORT_HS_MODE
+    esp_rom_gpio_connect_out_signal(pin, ((bus->channel / 8 == 0) ? LEDC_HS_SIG_OUT0_IDX : LEDC_LS_SIG_OUT0_IDX) + ((bus->channel) % 8), out_invert, 0);
+#else
+    esp_rom_gpio_connect_out_signal(pin, LEDC_LS_SIG_OUT0_IDX + ((bus->channel) % 8), out_invert, 0);
+#endif
+#endif  // ifdef CONFIG_IDF_TARGET_ESP32P4
+    return true;
+  }
+  return false;
+}
+
+static IRAM_ATTR bool ledcFnWrapper(const ledc_cb_param_t *param, void *user_arg) {
+  if (param->event == LEDC_FADE_END_EVT) {
+    ledc_channel_handle_t *bus = (ledc_channel_handle_t *)user_arg;
+#ifndef SOC_LEDC_SUPPORT_FADE_STOP
+    portBASE_TYPE xTaskWoken = 0;
+    xSemaphoreGiveFromISR(bus->lock, &xTaskWoken);
+#endif
+    if (bus->fn) {
+      if (bus->arg) {
+        ((voidFuncPtrArg)bus->fn)(bus->arg);
+      } else {
+        bus->fn();
+      }
     }
-    return _ledcTimerRead(chan);
+  }
+  return true;
 }
 
-double ledcWriteTone(uint8_t chan, double freq)
-{
-    if(chan > 15) {
-        return 0;
+static bool ledcFadeConfig(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void *), void *arg) {
+  ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+  if (bus != NULL) {
+
+#ifndef SOC_LEDC_SUPPORT_FADE_STOP
+#if !CONFIG_DISABLE_HAL_LOCKS
+    if (bus->lock == NULL) {
+      bus->lock = xSemaphoreCreateBinary();
+      if (bus->lock == NULL) {
+        log_e("xSemaphoreCreateBinary failed");
+        return false;
+      }
+      xSemaphoreGive(bus->lock);
     }
-    if(!freq) {
-        ledcWrite(chan, 0);
-        return 0;
+    //acquire lock
+    if (xSemaphoreTake(bus->lock, 0) != pdTRUE) {
+      log_e("LEDC Fade is still running on pin %u! SoC does not support stopping fade.", pin);
+      return false;
     }
-    double res_freq = _ledcSetupTimerFreq(chan, freq, 10);
-    ledcWrite(chan, 0x1FF);
-    return res_freq;
-}
+#endif
+#endif
+    uint8_t group = (bus->channel / 8), channel = (bus->channel % 8);
+
+    // Initialize fade service.
+    if (!fade_initialized) {
+      ledc_fade_func_install(0);
+      fade_initialized = true;
+    }
+
+    bus->fn = (voidFuncPtr)userFunc;
+    bus->arg = arg;
+
+    ledc_cbs_t callbacks = {.fade_cb = ledcFnWrapper};
+    ledc_cb_register(group, channel, &callbacks, (void *)bus);
+
+    //Fixing if all bits in resolution is set = LEDC FULL ON
+    uint32_t max_duty = (1 << bus->channel_resolution) - 1;
+
+    if ((target_duty == max_duty) && (max_duty != 1)) {
+      target_duty = max_duty + 1;
+    } else if ((start_duty == max_duty) && (max_duty != 1)) {
+      start_duty = max_duty + 1;
+    }
+
+#if SOC_LEDC_SUPPORT_FADE_STOP
+    ledc_fade_stop(group, channel);
+#endif
 
-double ledcWriteNote(uint8_t chan, note_t note, uint8_t octave){
-    const uint16_t noteFrequencyBase[12] = {
-    //   C        C#       D        Eb       E        F       F#        G       G#        A       Bb        B
-        4186,    4435,    4699,    4978,    5274,    5588,    5920,    6272,    6645,    7040,    7459,    7902
-    };
+    if (ledc_set_duty_and_update(group, channel, start_duty, 0) != ESP_OK) {
+      log_e("ledc_set_duty_and_update failed");
+      return false;
+    }
+    // Wait for LEDCs next PWM cycle to update duty (~ 1-2 ms)
+    while (ledc_get_duty(group, channel) != start_duty);
 
-    if(octave > 8 || note >= NOTE_MAX){
-        return 0;
+    if (ledc_set_fade_time_and_start(group, channel, target_duty, max_fade_time_ms, LEDC_FADE_NO_WAIT) != ESP_OK) {
+      log_e("ledc_set_fade_time_and_start failed");
+      return false;
     }
-    double noteFreq =  (double)noteFrequencyBase[note] / (double)(1 << (8-octave));
-    return ledcWriteTone(chan, noteFreq);
+  } else {
+    log_e("Pin %u is not attached to LEDC. Call ledcAttach first!", pin);
+    return false;
+  }
+  return true;
+}
+
+bool ledcFade(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms) {
+  return ledcFadeConfig(pin, start_duty, target_duty, max_fade_time_ms, NULL, NULL);
+}
+
+bool ledcFadeWithInterrupt(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, voidFuncPtr userFunc) {
+  return ledcFadeConfig(pin, start_duty, target_duty, max_fade_time_ms, (voidFuncPtrArg)userFunc, NULL);
 }
 
-void ledcAttachPin(uint8_t pin, uint8_t chan)
-{
-    if(chan > 15) {
+bool ledcFadeWithInterruptArg(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void *), void *arg) {
+  return ledcFadeConfig(pin, start_duty, target_duty, max_fade_time_ms, userFunc, arg);
+}
+
+static uint8_t analog_resolution = 8;
+static int analog_frequency = 1000;
+void analogWrite(uint8_t pin, int value) {
+  // Use ledc hardware for internal pins
+  if (pin < SOC_GPIO_PIN_COUNT) {
+    ledc_channel_handle_t *bus = (ledc_channel_handle_t *)perimanGetPinBus(pin, ESP32_BUS_TYPE_LEDC);
+    if (bus == NULL && perimanClearPinBus(pin)) {
+      if (ledcAttach(pin, analog_frequency, analog_resolution) == 0) {
+        log_e("analogWrite setup failed (freq = %u, resolution = %u). Try setting different resolution or frequency");
         return;
+      }
     }
-    pinMode(pin, OUTPUT);
-    pinMatrixOutAttach(pin, ((chan/8)?LEDC_LS_SIG_OUT0_IDX:LEDC_HS_SIG_OUT0_IDX) + (chan%8), false, false);
+    ledcWrite(pin, value);
+  }
 }
 
-void ledcDetachPin(uint8_t pin)
-{
-    pinMatrixOutDetach(pin, false, false);
+void analogWriteFrequency(uint8_t pin, uint32_t freq) {
+  if (ledcChangeFrequency(pin, freq, analog_resolution) == 0) {
+    log_e("analogWrite frequency cant be set due to selected resolution! Try to adjust resolution first");
+    return;
+  }
+  analog_frequency = freq;
 }
+
+void analogWriteResolution(uint8_t pin, uint8_t resolution) {
+  if (ledcChangeFrequency(pin, analog_frequency, resolution) == 0) {
+    log_e("analogWrite resolution cant be set due to selected frequency! Try to adjust frequency first");
+    return;
+  }
+  analog_resolution = resolution;
+}
+
+#endif /* SOC_LEDC_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-ledc.h b/cores/esp32/esp32-hal-ledc.h
index 159f98d5351..5b44aaad452 100644
--- a/cores/esp32/esp32-hal-ledc.h
+++ b/cores/esp32/esp32-hal-ledc.h
@@ -1,4 +1,4 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2023 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,30 +15,224 @@
 #ifndef _ESP32_HAL_LEDC_H_
 #define _ESP32_HAL_LEDC_H_
 
+#include "soc/soc_caps.h"
+#if SOC_LEDC_SUPPORTED
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "hal/ledc_types.h"
 
 typedef enum {
-    NOTE_C, NOTE_Cs, NOTE_D, NOTE_Eb, NOTE_E, NOTE_F, NOTE_Fs, NOTE_G, NOTE_Gs, NOTE_A, NOTE_Bb, NOTE_B, NOTE_MAX
+  NOTE_C,
+  NOTE_Cs,
+  NOTE_D,
+  NOTE_Eb,
+  NOTE_E,
+  NOTE_F,
+  NOTE_Fs,
+  NOTE_G,
+  NOTE_Gs,
+  NOTE_A,
+  NOTE_Bb,
+  NOTE_B,
+  NOTE_MAX
 } note_t;
 
-//channel 0-15 resolution 1-16bits freq limits depend on resolution
-double      ledcSetup(uint8_t channel, double freq, uint8_t resolution_bits);
-void        ledcWrite(uint8_t channel, uint32_t duty);
-double      ledcWriteTone(uint8_t channel, double freq);
-double      ledcWriteNote(uint8_t channel, note_t note, uint8_t octave);
-uint32_t    ledcRead(uint8_t channel);
-double      ledcReadFreq(uint8_t channel);
-void        ledcAttachPin(uint8_t pin, uint8_t channel);
-void        ledcDetachPin(uint8_t pin);
+typedef void (*voidFuncPtr)(void);
+typedef void (*voidFuncPtrArg)(void *);
+
+typedef struct {
+  uint8_t pin;                 // Pin assigned to channel
+  uint8_t channel;             // Channel number
+  uint8_t channel_resolution;  // Resolution of channel
+  voidFuncPtr fn;
+  void *arg;
+#ifndef SOC_LEDC_SUPPORT_FADE_STOP
+  SemaphoreHandle_t lock;  //xSemaphoreCreateBinary
+#endif
+} ledc_channel_handle_t;
+
+/**
+ * @brief Get the LEDC clock source.
+ *
+ * @return LEDC clock source.
+ */
+ledc_clk_cfg_t ledcGetClockSource(void);
+
+/**
+ * @brief Set the LEDC clock source.
+ *
+ * @param source LEDC clock source to set.
+ *
+ * @return true if LEDC clock source was successfully set, false otherwise.
+ */
+bool ledcSetClockSource(ledc_clk_cfg_t source);
+
+/**
+ * @brief Attach a pin to the LEDC driver, with a given frequency and resolution.
+ *        Channel is automatically assigned.
+ *
+ * @param pin GPIO pin
+ * @param freq frequency of PWM signal
+ * @param resolution resolution for LEDC pin
+ *
+ * @return true if configuration is successful and pin was successfully attached, false otherwise.
+ */
+bool ledcAttach(uint8_t pin, uint32_t freq, uint8_t resolution);
+
+/**
+ * @brief Attach a pin to the LEDC driver, with a given frequency, resolution and channel.
+ *
+ * @param pin GPIO pin
+ * @param freq frequency of PWM signal
+ * @param resolution resolution for LEDC pin
+ * @param channel LEDC channel to attach to
+ *
+ * @return true if configuration is successful and pin was successfully attached, false otherwise.
+ */
+bool ledcAttachChannel(uint8_t pin, uint32_t freq, uint8_t resolution, uint8_t channel);
+
+/**
+ * @brief Set the duty cycle of a given pin.
+ *
+ * @param pin GPIO pin
+ * @param duty duty cycle to set
+ *
+ * @return true if duty cycle was successfully set, false otherwise.
+ */
+bool ledcWrite(uint8_t pin, uint32_t duty);
+
+/**
+ * @brief Set the duty cycle of a given channel.
+ *
+ * @param channel LEDC channel
+ * @param duty duty cycle to set
+ *
+ * @return true if duty cycle was successfully set, false otherwise.
+ */
+bool ledcWriteChannel(uint8_t channel, uint32_t duty);
+
+/**
+ * @brief Sets the duty to 50 % PWM tone on selected frequency.
+ *
+ * @param pin GPIO pin
+ * @param freq select frequency of pwm signal. If frequency is 0, duty will be set to 0.
+ *
+ * @return frequency if tone was successfully set.
+ *         If ``0`` is returned, error occurs and LEDC pin was not configured.
+ */
+uint32_t ledcWriteTone(uint8_t pin, uint32_t freq);
+
+/**
+ * @brief Sets the LEDC pin to specific note.
+ *
+ * @param pin GPIO pin
+ * @param note select note to be set (NOTE_C, NOTE_Cs, NOTE_D, NOTE_Eb, NOTE_E, NOTE_F, NOTE_Fs, NOTE_G, NOTE_Gs, NOTE_A, NOTE_Bb, NOTE_B).
+ * @param octave select octave for note.
+ *
+ * @return frequency if note was successfully set.
+ *         If ``0`` is returned, error occurs and LEDC pin was not configured.
+ */
+uint32_t ledcWriteNote(uint8_t pin, note_t note, uint8_t octave);
+
+/**
+ * @brief Read the duty cycle of a given LEDC pin.
+ *
+ * @param pin GPIO pin
+ *
+ * @return duty cycle of selected LEDC pin.
+ */
+uint32_t ledcRead(uint8_t pin);
+
+/**
+ * @brief Read the frequency of a given LEDC pin.
+ *
+ * @param pin GPIO pin
+ *
+ * @return frequency of selected LEDC pin.
+ */
+uint32_t ledcReadFreq(uint8_t pin);
+
+/**
+ * @brief Detach a pin from the LEDC driver.
+ *
+ * @param pin GPIO pin
+ *
+ * @return true if pin was successfully detached, false otherwise.
+ */
+bool ledcDetach(uint8_t pin);
+
+/**
+ * @brief Change the frequency and resolution of a given LEDC pin.
+ *
+ * @param pin GPIO pin
+ * @param freq frequency of PWM signal
+ * @param resolution resolution for LEDC pin
+ *
+ * @return frequency configured for the LEDC channel.
+ *         If ``0`` is returned, error occurs and LEDC pin was not configured.
+ */
+uint32_t ledcChangeFrequency(uint8_t pin, uint32_t freq, uint8_t resolution);
+
+/**
+ * @brief Sets inverting of the output signal for a given LEDC pin.
+ *
+ * @param pin GPIO pin
+ * @param out_invert select, if output should be inverted (true = inverting output).
+ *
+ * @return true if output inverting was successfully set, false otherwise.
+ */
+bool ledcOutputInvert(uint8_t pin, bool out_invert);
+
+//Fade functions
+/**
+ * @brief Setup and start a fade on a given LEDC pin.
+ *
+ * @param pin GPIO pin
+ * @param start_duty initial duty cycle of the fade
+ * @param target_duty target duty cycle of the fade
+ * @param max_fade_time_ms maximum fade time in milliseconds
+ *
+ * @return true if fade was successfully set and started, false otherwise.
+ */
+bool ledcFade(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms);
+
+/**
+ * @brief Setup and start a fade on a given LEDC pin with a callback function.
+ *
+ * @param pin GPIO pin
+ * @param start_duty initial duty cycle of the fade
+ * @param target_duty target duty cycle of the fade
+ * @param max_fade_time_ms maximum fade time in milliseconds
+ * @param userFunc callback function to be called after fade is finished
+ *
+ * @return true if fade was successfully set and started, false otherwise.
+ */
+bool ledcFadeWithInterrupt(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void));
 
+/**
+ * @brief Setup and start a fade on a given LEDC pin with a callback function and argument.
+ *
+ * @param pin GPIO pin
+ * @param start_duty initial duty cycle of the fade
+ * @param target_duty target duty cycle of the fade
+ * @param max_fade_time_ms maximum fade time in milliseconds
+ * @param userFunc callback function to be called after fade is finished
+ * @param arg argument to be passed to the callback function
+ *
+ * @return true if fade was successfully set and started, false otherwise.
+ */
+bool ledcFadeWithInterruptArg(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void *), void *arg);
 
 #ifdef __cplusplus
 }
 #endif
 
+#endif /* SOC_LEDC_SUPPORTED */
 #endif /* _ESP32_HAL_LEDC_H_ */
diff --git a/cores/esp32/esp32-hal-log.h b/cores/esp32/esp32-hal-log.h
index e1d4e56f3bb..da63c6dea94 100644
--- a/cores/esp32/esp32-hal-log.h
+++ b/cores/esp32/esp32-hal-log.h
@@ -15,18 +15,19 @@
 #define __ARDUHAL_LOG_H__
 
 #ifdef __cplusplus
-extern "C"
-{
+extern "C" {
 #endif
 
 #include "sdkconfig.h"
+#include "esp_timer.h"
+#include "rom/ets_sys.h"
 
-#define ARDUHAL_LOG_LEVEL_NONE       (0)
-#define ARDUHAL_LOG_LEVEL_ERROR      (1)
-#define ARDUHAL_LOG_LEVEL_WARN       (2)
-#define ARDUHAL_LOG_LEVEL_INFO       (3)
-#define ARDUHAL_LOG_LEVEL_DEBUG      (4)
-#define ARDUHAL_LOG_LEVEL_VERBOSE    (5)
+#define ARDUHAL_LOG_LEVEL_NONE    (0)
+#define ARDUHAL_LOG_LEVEL_ERROR   (1)
+#define ARDUHAL_LOG_LEVEL_WARN    (2)
+#define ARDUHAL_LOG_LEVEL_INFO    (3)
+#define ARDUHAL_LOG_LEVEL_DEBUG   (4)
+#define ARDUHAL_LOG_LEVEL_VERBOSE (5)
 
 #ifndef CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL
 #define CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL ARDUHAL_LOG_LEVEL_NONE
@@ -36,6 +37,11 @@ extern "C"
 #define ARDUHAL_LOG_LEVEL CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL
 #else
 #define ARDUHAL_LOG_LEVEL CORE_DEBUG_LEVEL
+#ifdef USE_ESP_IDF_LOG
+#ifndef LOG_LOCAL_LEVEL
+#define LOG_LOCAL_LEVEL CORE_DEBUG_LEVEL
+#endif
+#endif
 #endif
 
 #ifndef CONFIG_ARDUHAL_LOG_COLORS
@@ -44,24 +50,26 @@ extern "C"
 
 #if CONFIG_ARDUHAL_LOG_COLORS
 #define ARDUHAL_LOG_COLOR_BLACK   "30"
-#define ARDUHAL_LOG_COLOR_RED     "31" //ERROR
-#define ARDUHAL_LOG_COLOR_GREEN   "32" //INFO
-#define ARDUHAL_LOG_COLOR_YELLOW  "33" //WARNING
+#define ARDUHAL_LOG_COLOR_RED     "31"  //ERROR
+#define ARDUHAL_LOG_COLOR_GREEN   "32"  //INFO
+#define ARDUHAL_LOG_COLOR_YELLOW  "33"  //WARNING
 #define ARDUHAL_LOG_COLOR_BLUE    "34"
 #define ARDUHAL_LOG_COLOR_MAGENTA "35"
-#define ARDUHAL_LOG_COLOR_CYAN    "36" //DEBUG
-#define ARDUHAL_LOG_COLOR_GRAY    "37" //VERBOSE
+#define ARDUHAL_LOG_COLOR_CYAN    "36"  //DEBUG
+#define ARDUHAL_LOG_COLOR_GRAY    "37"  //VERBOSE
 #define ARDUHAL_LOG_COLOR_WHITE   "38"
 
-#define ARDUHAL_LOG_COLOR(COLOR)  "\033[0;" COLOR "m"
-#define ARDUHAL_LOG_BOLD(COLOR)   "\033[1;" COLOR "m"
-#define ARDUHAL_LOG_RESET_COLOR   "\033[0m"
+#define ARDUHAL_LOG_COLOR(COLOR) "\033[0;" COLOR "m"
+#define ARDUHAL_LOG_BOLD(COLOR)  "\033[1;" COLOR "m"
+#define ARDUHAL_LOG_RESET_COLOR  "\033[0m"
 
-#define ARDUHAL_LOG_COLOR_E       ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_RED)
-#define ARDUHAL_LOG_COLOR_W       ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_YELLOW)
-#define ARDUHAL_LOG_COLOR_I       ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_GREEN)
-#define ARDUHAL_LOG_COLOR_D       ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_CYAN)
-#define ARDUHAL_LOG_COLOR_V       ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_GRAY)
+#define ARDUHAL_LOG_COLOR_E             ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_RED)
+#define ARDUHAL_LOG_COLOR_W             ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_YELLOW)
+#define ARDUHAL_LOG_COLOR_I             ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_GREEN)
+#define ARDUHAL_LOG_COLOR_D             ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_CYAN)
+#define ARDUHAL_LOG_COLOR_V             ARDUHAL_LOG_COLOR(ARDUHAL_LOG_COLOR_GRAY)
+#define ARDUHAL_LOG_COLOR_PRINT(letter) log_printf(ARDUHAL_LOG_COLOR_##letter)
+#define ARDUHAL_LOG_COLOR_PRINT_END     log_printf(ARDUHAL_LOG_RESET_COLOR)
 #else
 #define ARDUHAL_LOG_COLOR_E
 #define ARDUHAL_LOG_COLOR_W
@@ -69,64 +77,246 @@ extern "C"
 #define ARDUHAL_LOG_COLOR_D
 #define ARDUHAL_LOG_COLOR_V
 #define ARDUHAL_LOG_RESET_COLOR
+#define ARDUHAL_LOG_COLOR_PRINT(letter)
+#define ARDUHAL_LOG_COLOR_PRINT_END
+#endif
+
+#ifdef USE_ESP_IDF_LOG
+#ifndef ARDUHAL_ESP_LOG_TAG
+#define ARDUHAL_ESP_LOG_TAG "ARDUINO"
+#endif
 #endif
 
-const char * pathToFileName(const char * path);
+const char *pathToFileName(const char *path);
 int log_printf(const char *fmt, ...);
+void log_print_buf(const uint8_t *b, size_t len);
 
-#define ARDUHAL_SHORT_LOG_FORMAT(letter, format)  ARDUHAL_LOG_COLOR_ ## letter format ARDUHAL_LOG_RESET_COLOR "\r\n"
-#define ARDUHAL_LOG_FORMAT(letter, format)  ARDUHAL_LOG_COLOR_ ## letter "[" #letter "][%s:%u] %s(): " format ARDUHAL_LOG_RESET_COLOR "\r\n", pathToFileName(__FILE__), __LINE__, __FUNCTION__
+#define ARDUHAL_SHORT_LOG_FORMAT(letter, format) ARDUHAL_LOG_COLOR_##letter format ARDUHAL_LOG_RESET_COLOR "\r\n"
+#define ARDUHAL_LOG_FORMAT(letter, format)                                                                                                              \
+  ARDUHAL_LOG_COLOR_##letter "[%6u][" #letter "][%s:%u] %s(): " format ARDUHAL_LOG_RESET_COLOR "\r\n", (unsigned long)(esp_timer_get_time() / 1000ULL), \
+    pathToFileName(__FILE__), __LINE__, __FUNCTION__
+
+//esp_rom_printf(DRAM_STR("ST:%d\n"), frame_pos);
 
 #if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
-#define log_v(format, ...) log_printf(ARDUHAL_LOG_FORMAT(V, format), ##__VA_ARGS__)
+#ifndef USE_ESP_IDF_LOG
+#define log_v(format, ...)     log_printf(ARDUHAL_LOG_FORMAT(V, format), ##__VA_ARGS__)
 #define isr_log_v(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(V, format), ##__VA_ARGS__)
+#define log_buf_v(b, l)          \
+  do {                           \
+    ARDUHAL_LOG_COLOR_PRINT(V);  \
+    log_print_buf(b, l);         \
+    ARDUHAL_LOG_COLOR_PRINT_END; \
+  } while (0)
+#else
+#define log_v(format, ...)                                                            \
+  do {                                                                                \
+    ESP_LOG_LEVEL_LOCAL(ESP_LOG_VERBOSE, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \
+  } while (0)
+#define isr_log_v(format, ...)                                                                  \
+  do {                                                                                          \
+    ets_printf(LOG_FORMAT(V, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \
+  } while (0)
+#define log_buf_v(b, l)                                                 \
+  do {                                                                  \
+    ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_VERBOSE); \
+  } while (0)
+#endif
 #else
-#define log_v(format, ...)
-#define isr_log_v(format, ...)
+#define log_v(format, ...) \
+  do {                     \
+  } while (0)
+#define isr_log_v(format, ...) \
+  do {                         \
+  } while (0)
+#define log_buf_v(b, l) \
+  do {                  \
+  } while (0)
 #endif
 
 #if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-#define log_d(format, ...) log_printf(ARDUHAL_LOG_FORMAT(D, format), ##__VA_ARGS__)
+#ifndef USE_ESP_IDF_LOG
+#define log_d(format, ...)     log_printf(ARDUHAL_LOG_FORMAT(D, format), ##__VA_ARGS__)
 #define isr_log_d(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(D, format), ##__VA_ARGS__)
+#define log_buf_d(b, l)          \
+  do {                           \
+    ARDUHAL_LOG_COLOR_PRINT(D);  \
+    log_print_buf(b, l);         \
+    ARDUHAL_LOG_COLOR_PRINT_END; \
+  } while (0)
+#else
+#define log_d(format, ...)                                                          \
+  do {                                                                              \
+    ESP_LOG_LEVEL_LOCAL(ESP_LOG_DEBUG, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \
+  } while (0)
+#define isr_log_d(format, ...)                                                                  \
+  do {                                                                                          \
+    ets_printf(LOG_FORMAT(D, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \
+  } while (0)
+#define log_buf_d(b, l)                                               \
+  do {                                                                \
+    ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_DEBUG); \
+  } while (0)
+#endif
 #else
-#define log_d(format, ...)
-#define isr_log_d(format, ...)
+#define log_d(format, ...) \
+  do {                     \
+  } while (0)
+#define isr_log_d(format, ...) \
+  do {                         \
+  } while (0)
+#define log_buf_d(b, l) \
+  do {                  \
+  } while (0)
 #endif
 
 #if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
-#define log_i(format, ...) log_printf(ARDUHAL_LOG_FORMAT(I, format), ##__VA_ARGS__)
+#ifndef USE_ESP_IDF_LOG
+#define log_i(format, ...)     log_printf(ARDUHAL_LOG_FORMAT(I, format), ##__VA_ARGS__)
 #define isr_log_i(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(I, format), ##__VA_ARGS__)
+#define log_buf_i(b, l)          \
+  do {                           \
+    ARDUHAL_LOG_COLOR_PRINT(I);  \
+    log_print_buf(b, l);         \
+    ARDUHAL_LOG_COLOR_PRINT_END; \
+  } while (0)
 #else
-#define log_i(format, ...)
-#define isr_log_i(format, ...)
+#define log_i(format, ...)                                                         \
+  do {                                                                             \
+    ESP_LOG_LEVEL_LOCAL(ESP_LOG_INFO, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \
+  } while (0)
+#define isr_log_i(format, ...)                                                                  \
+  do {                                                                                          \
+    ets_printf(LOG_FORMAT(I, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \
+  } while (0)
+#define log_buf_i(b, l)                                              \
+  do {                                                               \
+    ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_INFO); \
+  } while (0)
+#endif
+#else
+#define log_i(format, ...) \
+  do {                     \
+  } while (0)
+#define isr_log_i(format, ...) \
+  do {                         \
+  } while (0)
+#define log_buf_i(b, l) \
+  do {                  \
+  } while (0)
 #endif
 
 #if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_WARN
-#define log_w(format, ...) log_printf(ARDUHAL_LOG_FORMAT(W, format), ##__VA_ARGS__)
+#ifndef USE_ESP_IDF_LOG
+#define log_w(format, ...)     log_printf(ARDUHAL_LOG_FORMAT(W, format), ##__VA_ARGS__)
 #define isr_log_w(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(W, format), ##__VA_ARGS__)
+#define log_buf_w(b, l)          \
+  do {                           \
+    ARDUHAL_LOG_COLOR_PRINT(W);  \
+    log_print_buf(b, l);         \
+    ARDUHAL_LOG_COLOR_PRINT_END; \
+  } while (0)
 #else
-#define log_w(format, ...)
-#define isr_log_w(format, ...)
+#define log_w(format, ...)                                                         \
+  do {                                                                             \
+    ESP_LOG_LEVEL_LOCAL(ESP_LOG_WARN, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \
+  } while (0)
+#define isr_log_w(format, ...)                                                                  \
+  do {                                                                                          \
+    ets_printf(LOG_FORMAT(W, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \
+  } while (0)
+#define log_buf_w(b, l)                                              \
+  do {                                                               \
+    ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_WARN); \
+  } while (0)
+#endif
+#else
+#define log_w(format, ...) \
+  do {                     \
+  } while (0)
+#define isr_log_w(format, ...) \
+  do {                         \
+  } while (0)
+#define log_buf_w(b, l) \
+  do {                  \
+  } while (0)
 #endif
 
 #if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
-#define log_e(format, ...) log_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__)
+#ifndef USE_ESP_IDF_LOG
+#define log_e(format, ...)     log_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__)
 #define isr_log_e(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__)
+#define log_buf_e(b, l)          \
+  do {                           \
+    ARDUHAL_LOG_COLOR_PRINT(E);  \
+    log_print_buf(b, l);         \
+    ARDUHAL_LOG_COLOR_PRINT_END; \
+  } while (0)
 #else
-#define log_e(format, ...)
-#define isr_log_e(format, ...)
+#define log_e(format, ...)                                                          \
+  do {                                                                              \
+    ESP_LOG_LEVEL_LOCAL(ESP_LOG_ERROR, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \
+  } while (0)
+#define isr_log_e(format, ...)                                                                  \
+  do {                                                                                          \
+    ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \
+  } while (0)
+#define log_buf_e(b, l)                                               \
+  do {                                                                \
+    ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_ERROR); \
+  } while (0)
+#endif
+#else
+#define log_e(format, ...) \
+  do {                     \
+  } while (0)
+#define isr_log_e(format, ...) \
+  do {                         \
+  } while (0)
+#define log_buf_e(b, l) \
+  do {                  \
+  } while (0)
 #endif
 
 #if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_NONE
-#define log_n(format, ...) log_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__)
+#ifndef USE_ESP_IDF_LOG
+#define log_n(format, ...)     log_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__)
 #define isr_log_n(format, ...) ets_printf(ARDUHAL_LOG_FORMAT(E, format), ##__VA_ARGS__)
+#define log_buf_n(b, l)          \
+  do {                           \
+    ARDUHAL_LOG_COLOR_PRINT(E);  \
+    log_print_buf(b, l);         \
+    ARDUHAL_LOG_COLOR_PRINT_END; \
+  } while (0)
+#else
+#define log_n(format, ...)                                                          \
+  do {                                                                              \
+    ESP_LOG_LEVEL_LOCAL(ESP_LOG_ERROR, ARDUHAL_ESP_LOG_TAG, format, ##__VA_ARGS__); \
+  } while (0)
+#define isr_log_n(format, ...)                                                                  \
+  do {                                                                                          \
+    ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), ARDUHAL_ESP_LOG_TAG, ##__VA_ARGS__); \
+  } while (0)
+#define log_buf_n(b, l)                                               \
+  do {                                                                \
+    ESP_LOG_BUFFER_HEXDUMP(ARDUHAL_ESP_LOG_TAG, b, l, ESP_LOG_ERROR); \
+  } while (0)
+#endif
 #else
-#define log_n(format, ...)
-#define isr_log_n(format, ...)
+#define log_n(format, ...) \
+  do {                     \
+  } while (0)
+#define isr_log_n(format, ...) \
+  do {                         \
+  } while (0)
+#define log_buf_n(b, l) \
+  do {                  \
+  } while (0)
 #endif
 
 #include "esp_log.h"
 
+#ifndef USE_ESP_IDF_LOG
 #ifdef CONFIG_ARDUHAL_ESP_LOG
 #undef ESP_LOGE
 #undef ESP_LOGW
@@ -139,16 +329,17 @@ int log_printf(const char *fmt, ...);
 #undef ESP_EARLY_LOGD
 #undef ESP_EARLY_LOGV
 
-#define ESP_LOGE(tag, ...)  log_e(__VA_ARGS__)
-#define ESP_LOGW(tag, ...)  log_w(__VA_ARGS__)
-#define ESP_LOGI(tag, ...)  log_i(__VA_ARGS__)
-#define ESP_LOGD(tag, ...)  log_d(__VA_ARGS__)
-#define ESP_LOGV(tag, ...)  log_v(__VA_ARGS__)
-#define ESP_EARLY_LOGE(tag, ...)  isr_log_e(__VA_ARGS__)
-#define ESP_EARLY_LOGW(tag, ...)  isr_log_w(__VA_ARGS__)
-#define ESP_EARLY_LOGI(tag, ...)  isr_log_i(__VA_ARGS__)
-#define ESP_EARLY_LOGD(tag, ...)  isr_log_d(__VA_ARGS__)
-#define ESP_EARLY_LOGV(tag, ...)  isr_log_v(__VA_ARGS__)
+#define ESP_LOGE(tag, format, ...)       log_e("[%s] " format, tag, ##__VA_ARGS__)
+#define ESP_LOGW(tag, format, ...)       log_w("[%s] " format, tag, ##__VA_ARGS__)
+#define ESP_LOGI(tag, format, ...)       log_i("[%s] " format, tag, ##__VA_ARGS__)
+#define ESP_LOGD(tag, format, ...)       log_d("[%s] " format, tag, ##__VA_ARGS__)
+#define ESP_LOGV(tag, format, ...)       log_v("[%s] " format, tag, ##__VA_ARGS__)
+#define ESP_EARLY_LOGE(tag, format, ...) isr_log_e("[%s] " format, tag, ##__VA_ARGS__)
+#define ESP_EARLY_LOGW(tag, format, ...) isr_log_w("[%s] " format, tag, ##__VA_ARGS__)
+#define ESP_EARLY_LOGI(tag, format, ...) isr_log_i("[%s] " format, tag, ##__VA_ARGS__)
+#define ESP_EARLY_LOGD(tag, format, ...) isr_log_d("[%s] " format, tag, ##__VA_ARGS__)
+#define ESP_EARLY_LOGV(tag, format, ...) isr_log_v("[%s] " format, tag, ##__VA_ARGS__)
+#endif
 #endif
 
 #ifdef __cplusplus
diff --git a/cores/esp32/esp32-hal-matrix.c b/cores/esp32/esp32-hal-matrix.c
index fb1b498c4c8..7cddb4e04db 100644
--- a/cores/esp32/esp32-hal-matrix.c
+++ b/cores/esp32/esp32-hal-matrix.c
@@ -14,34 +14,52 @@
 
 #include "esp32-hal-matrix.h"
 #include "esp_attr.h"
-#include "rom/gpio.h"
 
-#define MATRIX_DETACH_OUT_SIG 0x100
-#define MATRIX_DETACH_IN_LOW_PIN 0x30
-#define MATRIX_DETACH_IN_LOW_HIGH 0x38
+#include "esp_system.h"
+#ifdef ESP_IDF_VERSION_MAJOR  // IDF 4+
+#include "soc/gpio_pins.h"
+#if CONFIG_IDF_TARGET_ESP32  // ESP32/PICO-D4
+#include "esp32/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/gpio.h"
+#else
+#error Target CONFIG_IDF_TARGET is not supported
+#endif
+#else  // ESP32 Before IDF 4.0
+#include "rom/gpio.h"
+#define GPIO_MATRIX_CONST_ZERO_INPUT GPIO_FUNC_IN_LOW
+#define GPIO_MATRIX_CONST_ONE_INPUT  GPIO_FUNC_IN_HIGH
+#endif
 
-void IRAM_ATTR pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable)
-{
-    gpio_matrix_out(pin, function, invertOut, invertEnable);
+void ARDUINO_ISR_ATTR pinMatrixOutAttach(uint8_t pin, uint8_t function, bool invertOut, bool invertEnable) {
+  gpio_matrix_out(pin, function, invertOut, invertEnable);
 }
 
-void IRAM_ATTR pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable)
-{
-    gpio_matrix_out(pin, MATRIX_DETACH_OUT_SIG, invertOut, invertEnable);
+void ARDUINO_ISR_ATTR pinMatrixOutDetach(uint8_t pin, bool invertOut, bool invertEnable) {
+  gpio_matrix_out(pin, SIG_GPIO_OUT_IDX, invertOut, invertEnable);
 }
 
-void IRAM_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted)
-{
-    gpio_matrix_in(pin, signal, inverted);
+void ARDUINO_ISR_ATTR pinMatrixInAttach(uint8_t pin, uint8_t signal, bool inverted) {
+  gpio_matrix_in(pin, signal, inverted);
 }
 
-void IRAM_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted)
-{
-    gpio_matrix_in(high?MATRIX_DETACH_IN_LOW_HIGH:MATRIX_DETACH_IN_LOW_PIN, signal, inverted);
+void ARDUINO_ISR_ATTR pinMatrixInDetach(uint8_t signal, bool high, bool inverted) {
+  gpio_matrix_in(high ? GPIO_MATRIX_CONST_ONE_INPUT : GPIO_MATRIX_CONST_ZERO_INPUT, signal, inverted);
 }
 /*
-void IRAM_ATTR intrMatrixAttach(uint32_t source, uint32_t inum){
+void ARDUINO_ISR_ATTR intrMatrixAttach(uint32_t source, uint32_t inum){
   intr_matrix_set(PRO_CPU_NUM, source, inum);
 }
 */
-
diff --git a/cores/esp32/esp32-hal-matrix.h b/cores/esp32/esp32-hal-matrix.h
index 3bc90498d6b..f7c99ae77ee 100644
--- a/cores/esp32/esp32-hal-matrix.h
+++ b/cores/esp32/esp32-hal-matrix.h
@@ -15,7 +15,6 @@
 #ifndef _ESP32_HAL_MATRIX_H_
 #define _ESP32_HAL_MATRIX_H_
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/cores/esp32/esp32-hal-misc.c b/cores/esp32/esp32-hal-misc.c
index be08e4b7313..594acd38153 100644
--- a/cores/esp32/esp32-hal-misc.c
+++ b/cores/esp32/esp32-hal-misc.c
@@ -23,143 +23,206 @@
 #include "esp_timer.h"
 #ifdef CONFIG_APP_ROLLBACK_ENABLE
 #include "esp_ota_ops.h"
-#endif //CONFIG_APP_ROLLBACK_ENABLE
-#ifdef CONFIG_BT_ENABLED
+#endif  //CONFIG_APP_ROLLBACK_ENABLE
+#include "esp_private/startup_internal.h"
+#if defined(CONFIG_BT_BLUEDROID_ENABLED) && SOC_BT_SUPPORTED
 #include "esp_bt.h"
-#endif //CONFIG_BT_ENABLED
+#endif  //CONFIG_BT_BLUEDROID_ENABLED
 #include <sys/time.h>
 #include "soc/rtc.h"
+#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4)
 #include "soc/rtc_cntl_reg.h"
-#include "soc/apb_ctrl_reg.h"
-#include "rom/rtc.h"
+#include "soc/syscon_reg.h"
+#endif
 #include "esp_task_wdt.h"
 #include "esp32-hal.h"
 
-//Undocumented!!! Get chip temperature in Farenheit
+#include "esp_system.h"
+#ifdef ESP_IDF_VERSION_MAJOR  // IDF 4+
+
+#if CONFIG_IDF_TARGET_ESP32  // ESP32/PICO-D4
+#include "esp32/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/rtc.h"
+
+#else
+#error Target CONFIG_IDF_TARGET is not supported
+#endif
+
+#if SOC_TEMP_SENSOR_SUPPORTED
+#include "driver/temperature_sensor.h"
+#endif
+
+#else  // ESP32 Before IDF 4.0
+#include "rom/rtc.h"
+#endif
+
+//Undocumented!!! Get chip temperature in Fahrenheit
 //Source: https://github.com/pcbreflux/espressif/blob/master/esp32/arduino/sketchbook/ESP32_int_temp_sensor/ESP32_int_temp_sensor.ino
+#ifdef CONFIG_IDF_TARGET_ESP32
 uint8_t temprature_sens_read();
 
-float temperatureRead()
-{
-    return (temprature_sens_read() - 32) / 1.8;
+float temperatureRead() {
+  return (temprature_sens_read() - 32) / 1.8;
+}
+#elif SOC_TEMP_SENSOR_SUPPORTED
+static temperature_sensor_handle_t temp_sensor = NULL;
+
+static bool temperatureReadInit() {
+  static volatile bool initialized = false;
+  if (!initialized) {
+    initialized = true;
+    //Install temperature sensor, expected temp ranger range: 10~50 ℃
+    temperature_sensor_config_t temp_sensor_config = TEMPERATURE_SENSOR_CONFIG_DEFAULT(10, 50);
+    if (temperature_sensor_install(&temp_sensor_config, &temp_sensor) != ESP_OK) {
+      initialized = false;
+      temp_sensor = NULL;
+      log_e("temperature_sensor_install failed");
+    } else if (temperature_sensor_enable(temp_sensor) != ESP_OK) {
+      temperature_sensor_uninstall(temp_sensor);
+      initialized = false;
+      temp_sensor = NULL;
+      log_e("temperature_sensor_enable failed");
+    }
+  }
+  return initialized;
 }
 
-void __yield()
-{
-    vPortYield();
+float temperatureRead() {
+  float result = NAN;
+  if (temperatureReadInit()) {
+    if (temperature_sensor_get_celsius(temp_sensor, &result) != ESP_OK) {
+      log_e("temperature_sensor_get_celsius failed");
+    }
+  }
+  return result;
+}
+#endif
+
+void __yield() {
+  vPortYield();
 }
 
-void yield() __attribute__ ((weak, alias("__yield")));
+void yield() __attribute__((weak, alias("__yield")));
 
 #if CONFIG_AUTOSTART_ARDUINO
 
 extern TaskHandle_t loopTaskHandle;
 extern bool loopTaskWDTEnabled;
 
-void enableLoopWDT(){
-    if(loopTaskHandle != NULL){
-        if(esp_task_wdt_add(loopTaskHandle) != ESP_OK){
-            log_e("Failed to add loop task to WDT");
-        } else {
-            loopTaskWDTEnabled = true;
-        }
+void enableLoopWDT() {
+  if (loopTaskHandle != NULL) {
+    if (esp_task_wdt_add(loopTaskHandle) != ESP_OK) {
+      log_e("Failed to add loop task to WDT");
+    } else {
+      loopTaskWDTEnabled = true;
     }
+  }
 }
 
-void disableLoopWDT(){
-    if(loopTaskHandle != NULL && loopTaskWDTEnabled){
-        loopTaskWDTEnabled = false;
-        if(esp_task_wdt_delete(loopTaskHandle) != ESP_OK){
-            log_e("Failed to remove loop task from WDT");
-        }
+void disableLoopWDT() {
+  if (loopTaskHandle != NULL && loopTaskWDTEnabled) {
+    loopTaskWDTEnabled = false;
+    if (esp_task_wdt_delete(loopTaskHandle) != ESP_OK) {
+      log_e("Failed to remove loop task from WDT");
     }
+  }
 }
 
-void feedLoopWDT(){
-    esp_err_t err = esp_task_wdt_reset();
-    if(err != ESP_OK){
-        log_e("Failed to feed WDT! Error: %d", err);
-    }
+void feedLoopWDT() {
+  esp_err_t err = esp_task_wdt_reset();
+  if (err != ESP_OK) {
+    log_e("Failed to feed WDT! Error: %d", err);
+  }
 }
 #endif
 
-void enableCore0WDT(){
-    TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
-    if(idle_0 == NULL || esp_task_wdt_add(idle_0) != ESP_OK){
-        log_e("Failed to add Core 0 IDLE task to WDT");
-    }
+void enableCore0WDT() {
+  TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCore(0);
+  if (idle_0 == NULL || esp_task_wdt_add(idle_0) != ESP_OK) {
+    log_e("Failed to add Core 0 IDLE task to WDT");
+  }
 }
 
-void disableCore0WDT(){
-    TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
-    if(idle_0 == NULL || esp_task_wdt_delete(idle_0) != ESP_OK){
-        log_e("Failed to remove Core 0 IDLE task from WDT");
-    }
+bool disableCore0WDT() {
+  TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCore(0);
+  if (idle_0 == NULL || esp_task_wdt_status(idle_0) || esp_task_wdt_delete(idle_0) != ESP_OK) {
+    log_e("Failed to remove Core 0 IDLE task from WDT");
+    return false;
+  }
+  return true;
 }
 
 #ifndef CONFIG_FREERTOS_UNICORE
-void enableCore1WDT(){
-    TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
-    if(idle_1 == NULL || esp_task_wdt_add(idle_1) != ESP_OK){
-        log_e("Failed to add Core 1 IDLE task to WDT");
-    }
+void enableCore1WDT() {
+  TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCore(1);
+  if (idle_1 == NULL || esp_task_wdt_add(idle_1) != ESP_OK) {
+    log_e("Failed to add Core 1 IDLE task to WDT");
+  }
 }
 
-void disableCore1WDT(){
-    TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
-    if(idle_1 == NULL || esp_task_wdt_delete(idle_1) != ESP_OK){
-        log_e("Failed to remove Core 1 IDLE task from WDT");
-    }
+bool disableCore1WDT() {
+  TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCore(1);
+  if (idle_1 == NULL || esp_task_wdt_status(idle_1) || esp_task_wdt_delete(idle_1) != ESP_OK) {
+    log_e("Failed to remove Core 1 IDLE task from WDT");
+    return false;
+  }
+  return true;
 }
 #endif
 
-BaseType_t xTaskCreateUniversal( TaskFunction_t pxTaskCode,
-                        const char * const pcName,
-                        const uint32_t usStackDepth,
-                        void * const pvParameters,
-                        UBaseType_t uxPriority,
-                        TaskHandle_t * const pxCreatedTask,
-                        const BaseType_t xCoreID ){
+BaseType_t xTaskCreateUniversal(
+  TaskFunction_t pxTaskCode, const char *const pcName, const uint32_t usStackDepth, void *const pvParameters, UBaseType_t uxPriority,
+  TaskHandle_t *const pxCreatedTask, const BaseType_t xCoreID
+) {
 #ifndef CONFIG_FREERTOS_UNICORE
-    if(xCoreID >= 0 && xCoreID < 2) {
-        return xTaskCreatePinnedToCore(pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, xCoreID);
-    } else {
+  if (xCoreID >= 0 && xCoreID < 2) {
+    return xTaskCreatePinnedToCore(pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, xCoreID);
+  } else {
 #endif
     return xTaskCreate(pxTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask);
 #ifndef CONFIG_FREERTOS_UNICORE
-    }
+  }
 #endif
 }
 
-unsigned long IRAM_ATTR micros()
-{
-    return (unsigned long) (esp_timer_get_time());
+unsigned long ARDUINO_ISR_ATTR micros() {
+  return (unsigned long)(esp_timer_get_time());
 }
 
-unsigned long IRAM_ATTR millis()
-{
-    return (unsigned long) (esp_timer_get_time() / 1000ULL);
+unsigned long ARDUINO_ISR_ATTR millis() {
+  return (unsigned long)(esp_timer_get_time() / 1000ULL);
 }
 
-void delay(uint32_t ms)
-{
-    vTaskDelay(ms / portTICK_PERIOD_MS);
+void delay(uint32_t ms) {
+  vTaskDelay(ms / portTICK_PERIOD_MS);
 }
 
-void IRAM_ATTR delayMicroseconds(uint32_t us)
-{
-    uint32_t m = micros();
-    if(us){
-        uint32_t e = (m + us);
-        if(m > e){ //overflow
-            while(micros() > e){
-                NOP();
-            }
-        }
-        while(micros() < e){
-            NOP();
-        }
+void ARDUINO_ISR_ATTR delayMicroseconds(uint32_t us) {
+  uint64_t m = (uint64_t)esp_timer_get_time();
+  if (us) {
+    uint64_t e = (m + us);
+    if (m > e) {  //overflow
+      while ((uint64_t)esp_timer_get_time() > e) {
+        NOP();
+      }
     }
+    while ((uint64_t)esp_timer_get_time() < e) {
+      NOP();
+    }
+  }
 }
 
 void initVariant() __attribute__((weak));
@@ -168,77 +231,190 @@ void initVariant() {}
 void init() __attribute__((weak));
 void init() {}
 
+#ifdef CONFIG_APP_ROLLBACK_ENABLE
 bool verifyOta() __attribute__((weak));
-bool verifyOta() { return true; }
+bool verifyOta() {
+  return true;
+}
 
-#ifdef CONFIG_BT_ENABLED
+bool verifyRollbackLater() __attribute__((weak));
+bool verifyRollbackLater() {
+  return false;
+}
+#endif
+
+#ifdef CONFIG_BT_BLUEDROID_ENABLED
+#if CONFIG_IDF_TARGET_ESP32
 //overwritten in esp32-hal-bt.c
 bool btInUse() __attribute__((weak));
-bool btInUse(){ return false; }
+bool btInUse() {
+  return false;
+}
+#else
+//from esp32-hal-bt.c
+extern bool btInUse();
+#endif
 #endif
 
-void initArduino()
-{
+#if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM
+ESP_SYSTEM_INIT_FN(init_psram_new, CORE, BIT(0), 99) {
+  psramInit();
+  return ESP_OK;
+}
+#endif
+
+void initArduino() {
+  //init proper ref tick value for PLL (uncomment if REF_TICK is different than 1MHz)
+  //ESP_REG(APB_CTRL_PLL_TICK_CONF_REG) = APB_CLK_FREQ / REF_CLK_FREQ - 1;
+#if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM
+#ifndef CONFIG_SPIRAM_BOOT_INIT
+  psramAddToHeap();
+#endif
+#endif
 #ifdef CONFIG_APP_ROLLBACK_ENABLE
+  if (!verifyRollbackLater()) {
     const esp_partition_t *running = esp_ota_get_running_partition();
     esp_ota_img_states_t ota_state;
     if (esp_ota_get_state_partition(running, &ota_state) == ESP_OK) {
-        if (ota_state == ESP_OTA_IMG_PENDING_VERIFY) {
-            if (verifyOta()) {
-                esp_ota_mark_app_valid_cancel_rollback();
-            } else {
-                log_e("OTA verification failed! Start rollback to the previous version ...");
-                esp_ota_mark_app_invalid_rollback_and_reboot();
-            }
+      if (ota_state == ESP_OTA_IMG_PENDING_VERIFY) {
+        if (verifyOta()) {
+          esp_ota_mark_app_valid_cancel_rollback();
+        } else {
+          log_e("OTA verification failed! Start rollback to the previous version ...");
+          esp_ota_mark_app_invalid_rollback_and_reboot();
         }
+      }
     }
+  }
 #endif
-    //init proper ref tick value for PLL (uncomment if REF_TICK is different than 1MHz)
-    //ESP_REG(APB_CTRL_PLL_TICK_CONF_REG) = APB_CLK_FREQ / REF_CLK_FREQ - 1;
-#ifdef F_CPU
-    setCpuFrequencyMhz(F_CPU/1000000);
-#endif
-#if CONFIG_SPIRAM_SUPPORT
-    psramInit();
-#endif
-    esp_log_level_set("*", CONFIG_LOG_DEFAULT_LEVEL);
-    esp_err_t err = nvs_flash_init();
-    if(err == ESP_ERR_NVS_NO_FREE_PAGES){
-        const esp_partition_t* partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NVS, NULL);
-        if (partition != NULL) {
-            err = esp_partition_erase_range(partition, 0, partition->size);
-            if(!err){
-                err = nvs_flash_init();
-            } else {
-                log_e("Failed to format the broken NVS partition!");
-            }
-        }
-    }
-    if(err) {
-        log_e("Failed to initialize NVS! Error: %u", err);
-    }
-#ifdef CONFIG_BT_ENABLED
-    if(!btInUse()){
-        esp_bt_controller_mem_release(ESP_BT_MODE_BTDM);
+  esp_log_level_set("*", CONFIG_LOG_DEFAULT_LEVEL);
+  esp_err_t err = nvs_flash_init();
+  if (err == ESP_ERR_NVS_NO_FREE_PAGES || err == ESP_ERR_NVS_NEW_VERSION_FOUND) {
+    const esp_partition_t *partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NVS, NULL);
+    if (partition != NULL) {
+      err = esp_partition_erase_range(partition, 0, partition->size);
+      if (!err) {
+        err = nvs_flash_init();
+      } else {
+        log_e("Failed to format the broken NVS partition!");
+      }
+    } else {
+      log_e("Could not find NVS partition");
     }
+  }
+  if (err) {
+    log_e("Failed to initialize NVS! Error: %u", err);
+  }
+#if defined(CONFIG_BT_BLUEDROID_ENABLED) && SOC_BT_SUPPORTED
+  if (!btInUse()) {
+    esp_bt_controller_mem_release(ESP_BT_MODE_BTDM);
+  }
 #endif
-    init();
-    initVariant();
+  init();
+  initVariant();
 }
 
 //used by hal log
-const char * IRAM_ATTR pathToFileName(const char * path)
-{
-    size_t i = 0;
-    size_t pos = 0;
-    char * p = (char *)path;
-    while(*p){
-        i++;
-        if(*p == '/' || *p == '\\'){
-            pos = i;
+const char *ARDUINO_ISR_ATTR pathToFileName(const char *path) {
+  size_t i = 0;
+  size_t pos = 0;
+  char *p = (char *)path;
+  while (*p) {
+    i++;
+    if (*p == '/' || *p == '\\') {
+      pos = i;
+    }
+    p++;
+  }
+  return path + pos;
+}
+
+#include "esp_rom_sys.h"
+#include "esp_debug_helpers.h"
+#if CONFIG_IDF_TARGET_ARCH_XTENSA
+#include "esp_cpu_utils.h"
+#else
+#include "riscv/rvruntime-frames.h"
+#endif
+#include "esp_memory_utils.h"
+#include "esp_private/panic_internal.h"
+
+static arduino_panic_handler_t _panic_handler = NULL;
+static void *_panic_handler_arg = NULL;
+
+void set_arduino_panic_handler(arduino_panic_handler_t handler, void *arg) {
+  _panic_handler = handler;
+  _panic_handler_arg = arg;
+}
+
+arduino_panic_handler_t get_arduino_panic_handler(void) {
+  return _panic_handler;
+}
+
+void *get_arduino_panic_handler_arg(void) {
+  return _panic_handler_arg;
+}
+
+static void handle_custom_backtrace(panic_info_t *info) {
+  arduino_panic_info_t p_info;
+  p_info.reason = info->reason;
+  p_info.core = info->core;
+  p_info.pc = info->addr;
+  p_info.backtrace_len = 0;
+  p_info.backtrace_corrupt = false;
+  p_info.backtrace_continues = false;
+
+#if CONFIG_IDF_TARGET_ARCH_XTENSA
+  XtExcFrame *xt_frame = (XtExcFrame *)info->frame;
+  esp_backtrace_frame_t stk_frame = {.pc = xt_frame->pc, .sp = xt_frame->a1, .next_pc = xt_frame->a0, .exc_frame = xt_frame};
+  uint32_t i = 100, pc_ptr = esp_cpu_process_stack_pc(stk_frame.pc);
+  p_info.backtrace[p_info.backtrace_len++] = pc_ptr;
+
+  bool corrupted = !(esp_stack_ptr_is_sane(stk_frame.sp) && (esp_ptr_executable((void *)esp_cpu_process_stack_pc(stk_frame.pc)) ||
+                                                             /* Ignore the first corrupted PC in case of InstrFetchProhibited */
+                                                             (stk_frame.exc_frame && ((XtExcFrame *)stk_frame.exc_frame)->exccause == EXCCAUSE_INSTR_PROHIBITED)));
+
+  while (i-- > 0 && stk_frame.next_pc != 0 && !corrupted) {
+    if (!esp_backtrace_get_next_frame(&stk_frame)) {
+      corrupted = true;
+    }
+    pc_ptr = esp_cpu_process_stack_pc(stk_frame.pc);
+    if (esp_ptr_executable((void *)pc_ptr)) {
+      p_info.backtrace[p_info.backtrace_len++] = pc_ptr;
+      if (p_info.backtrace_len == 60) {
+        break;
+      }
+    }
+  }
+
+  if (corrupted) {
+    p_info.backtrace_corrupt = true;
+  } else if (stk_frame.next_pc != 0) {
+    p_info.backtrace_continues = true;
+  }
+#elif CONFIG_IDF_TARGET_ARCH_RISCV
+  uint32_t sp = (uint32_t)((RvExcFrame *)info->frame)->sp;
+  p_info.backtrace[p_info.backtrace_len++] = sp;
+  uint32_t *spptr = (uint32_t *)(sp);
+  for (int i = 0; i < 256; i++) {
+    if (esp_ptr_executable((void *)spptr[i])) {
+      p_info.backtrace[p_info.backtrace_len++] = spptr[i];
+      if (p_info.backtrace_len == 60) {
+        if (i < 255) {
+          p_info.backtrace_continues = true;
         }
-        p++;
+        break;
+      }
     }
-    return path+pos;
+  }
+#endif
+  _panic_handler(&p_info, _panic_handler_arg);
 }
 
+void __real_esp_panic_handler(panic_info_t *);
+void __wrap_esp_panic_handler(panic_info_t *info) {
+  if (_panic_handler != NULL) {
+    handle_custom_backtrace(info);
+  }
+  __real_esp_panic_handler(info);
+}
diff --git a/cores/esp32/esp32-hal-periman.c b/cores/esp32/esp32-hal-periman.c
new file mode 100644
index 00000000000..6ef3c3d984a
--- /dev/null
+++ b/cores/esp32/esp32-hal-periman.c
@@ -0,0 +1,241 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32-hal-log.h"
+#include "esp32-hal-periman.h"
+#include "esp_bit_defs.h"
+
+typedef struct ATTR_PACKED {
+  peripheral_bus_type_t type;
+  const char *extra_type;
+  void *bus;
+  int8_t bus_num;
+  int8_t bus_channel;
+} peripheral_pin_item_t;
+
+static peripheral_bus_deinit_cb_t deinit_functions[ESP32_BUS_TYPE_MAX];
+static peripheral_pin_item_t pins[SOC_GPIO_PIN_COUNT];
+
+#define GPIO_NOT_VALID(p) ((p >= SOC_GPIO_PIN_COUNT) || ((SOC_GPIO_VALID_GPIO_MASK & (1ULL << p)) == 0))
+
+const char *perimanGetTypeName(peripheral_bus_type_t type) {
+  switch (type) {
+    case ESP32_BUS_TYPE_INIT:     return "INIT";
+    case ESP32_BUS_TYPE_GPIO:     return "GPIO";
+    case ESP32_BUS_TYPE_UART_RX:  return "UART_RX";
+    case ESP32_BUS_TYPE_UART_TX:  return "UART_TX";
+    case ESP32_BUS_TYPE_UART_CTS: return "UART_CTS";
+    case ESP32_BUS_TYPE_UART_RTS: return "UART_RTS";
+#if SOC_SDM_SUPPORTED
+    case ESP32_BUS_TYPE_SIGMADELTA: return "SIGMADELTA";
+#endif
+#if SOC_ADC_SUPPORTED
+    case ESP32_BUS_TYPE_ADC_ONESHOT: return "ADC_ONESHOT";
+    case ESP32_BUS_TYPE_ADC_CONT:    return "ADC_CONT";
+#endif
+#if SOC_DAC_SUPPORTED
+    case ESP32_BUS_TYPE_DAC_ONESHOT: return "DAC_ONESHOT";
+    case ESP32_BUS_TYPE_DAC_CONT:    return "DAC_CONT";
+    case ESP32_BUS_TYPE_DAC_COSINE:  return "DAC_COSINE";
+#endif
+#if SOC_LEDC_SUPPORTED
+    case ESP32_BUS_TYPE_LEDC: return "LEDC";
+#endif
+#if SOC_RMT_SUPPORTED
+    case ESP32_BUS_TYPE_RMT_TX: return "RMT_TX";
+    case ESP32_BUS_TYPE_RMT_RX: return "RMT_RX";
+#endif
+#if SOC_I2S_SUPPORTED
+    case ESP32_BUS_TYPE_I2S_STD_MCLK:     return "I2S_STD_MCLK";
+    case ESP32_BUS_TYPE_I2S_STD_BCLK:     return "I2S_STD_BCLK";
+    case ESP32_BUS_TYPE_I2S_STD_WS:       return "I2S_STD_WS";
+    case ESP32_BUS_TYPE_I2S_STD_DOUT:     return "I2S_STD_DOUT";
+    case ESP32_BUS_TYPE_I2S_STD_DIN:      return "I2S_STD_DIN";
+    case ESP32_BUS_TYPE_I2S_TDM_MCLK:     return "I2S_TDM_MCLK";
+    case ESP32_BUS_TYPE_I2S_TDM_BCLK:     return "I2S_TDM_BCLK";
+    case ESP32_BUS_TYPE_I2S_TDM_WS:       return "I2S_TDM_WS";
+    case ESP32_BUS_TYPE_I2S_TDM_DOUT:     return "I2S_TDM_DOUT";
+    case ESP32_BUS_TYPE_I2S_TDM_DIN:      return "I2S_TDM_DIN";
+    case ESP32_BUS_TYPE_I2S_PDM_TX_CLK:   return "I2S_PDM_TX_CLK";
+    case ESP32_BUS_TYPE_I2S_PDM_TX_DOUT0: return "I2S_PDM_TX_DOUT0";
+    case ESP32_BUS_TYPE_I2S_PDM_TX_DOUT1: return "I2S_PDM_TX_DOUT1";
+    case ESP32_BUS_TYPE_I2S_PDM_RX_CLK:   return "I2S_PDM_RX_CLK";
+    case ESP32_BUS_TYPE_I2S_PDM_RX_DIN0:  return "I2S_PDM_RX_DIN0";
+    case ESP32_BUS_TYPE_I2S_PDM_RX_DIN1:  return "I2S_PDM_RX_DIN1";
+    case ESP32_BUS_TYPE_I2S_PDM_RX_DIN2:  return "I2S_PDM_RX_DIN2";
+    case ESP32_BUS_TYPE_I2S_PDM_RX_DIN3:  return "I2S_PDM_RX_DIN3";
+#endif
+#if SOC_I2C_SUPPORTED
+    case ESP32_BUS_TYPE_I2C_MASTER_SDA: return "I2C_MASTER_SDA";
+    case ESP32_BUS_TYPE_I2C_MASTER_SCL: return "I2C_MASTER_SCL";
+    case ESP32_BUS_TYPE_I2C_SLAVE_SDA:  return "I2C_SLAVE_SDA";
+    case ESP32_BUS_TYPE_I2C_SLAVE_SCL:  return "I2C_SLAVE_SCL";
+#endif
+#if SOC_GPSPI_SUPPORTED
+    case ESP32_BUS_TYPE_SPI_MASTER_SCK:  return "SPI_MASTER_SCK";
+    case ESP32_BUS_TYPE_SPI_MASTER_MISO: return "SPI_MASTER_MISO";
+    case ESP32_BUS_TYPE_SPI_MASTER_MOSI: return "SPI_MASTER_MOSI";
+    case ESP32_BUS_TYPE_SPI_MASTER_SS:   return "SPI_MASTER_SS";
+#endif
+#if SOC_SDMMC_HOST_SUPPORTED
+    case ESP32_BUS_TYPE_SDMMC_CLK: return "SDMMC_CLK";
+    case ESP32_BUS_TYPE_SDMMC_CMD: return "SDMMC_CMD";
+    case ESP32_BUS_TYPE_SDMMC_D0:  return "SDMMC_D0";
+    case ESP32_BUS_TYPE_SDMMC_D1:  return "SDMMC_D1";
+    case ESP32_BUS_TYPE_SDMMC_D2:  return "SDMMC_D2";
+    case ESP32_BUS_TYPE_SDMMC_D3:  return "SDMMC_D3";
+#endif
+#if SOC_TOUCH_SENSOR_SUPPORTED
+    case ESP32_BUS_TYPE_TOUCH: return "TOUCH";
+#endif
+#if SOC_USB_SERIAL_JTAG_SUPPORTED || SOC_USB_OTG_SUPPORTED
+    case ESP32_BUS_TYPE_USB_DM: return "USB_DM";
+    case ESP32_BUS_TYPE_USB_DP: return "USB_DP";
+#endif
+#if SOC_GPSPI_SUPPORTED
+    case ESP32_BUS_TYPE_ETHERNET_SPI: return "ETHERNET_SPI";
+#endif
+#if CONFIG_ETH_USE_ESP32_EMAC
+    case ESP32_BUS_TYPE_ETHERNET_RMII: return "ETHERNET_RMII";
+    case ESP32_BUS_TYPE_ETHERNET_CLK:  return "ETHERNET_CLK";
+    case ESP32_BUS_TYPE_ETHERNET_MCD:  return "ETHERNET_MCD";
+    case ESP32_BUS_TYPE_ETHERNET_MDIO: return "ETHERNET_MDIO";
+    case ESP32_BUS_TYPE_ETHERNET_PWR:  return "ETHERNET_PWR";
+#endif
+#if CONFIG_LWIP_PPP_SUPPORT
+    case ESP32_BUS_TYPE_PPP_TX:  return "PPP_MODEM_TX";
+    case ESP32_BUS_TYPE_PPP_RX:  return "PPP_MODEM_RX";
+    case ESP32_BUS_TYPE_PPP_RTS: return "PPP_MODEM_RTS";
+    case ESP32_BUS_TYPE_PPP_CTS: return "PPP_MODEM_CTS";
+#endif
+    default: return "UNKNOWN";
+  }
+}
+
+bool perimanSetPinBus(uint8_t pin, peripheral_bus_type_t type, void *bus, int8_t bus_num, int8_t bus_channel) {
+  peripheral_bus_type_t otype = ESP32_BUS_TYPE_INIT;
+  void *obus = NULL;
+  if (GPIO_NOT_VALID(pin)) {
+    log_e("Invalid pin: %u", pin);
+    return false;
+  }
+  if (type >= ESP32_BUS_TYPE_MAX) {
+    log_e("Invalid type: %s (%u) when setting pin %u", perimanGetTypeName(type), (unsigned int)type, pin);
+    return false;
+  }
+  if (type > ESP32_BUS_TYPE_GPIO && bus == NULL) {
+    log_e("Bus is NULL for pin %u with type %s (%u)", pin, perimanGetTypeName(type), (unsigned int)type);
+    return false;
+  }
+  if (type == ESP32_BUS_TYPE_INIT && bus != NULL) {
+    log_e("Can't set a Bus to INIT Type (pin %u)", pin);
+    return false;
+  }
+  otype = pins[pin].type;
+  obus = pins[pin].bus;
+  if (type == otype && bus == obus) {
+    if (type != ESP32_BUS_TYPE_INIT) {
+      log_i("Pin %u already has type %s (%u) with bus %p", pin, perimanGetTypeName(type), (unsigned int)type, bus);
+    }
+    return true;
+  }
+  if (obus != NULL) {
+    if (deinit_functions[otype] == NULL) {
+      log_e("No deinit function for type %s (%u) (pin %u)", perimanGetTypeName(otype), (unsigned int)otype, pin);
+      return false;
+    }
+    if (!deinit_functions[otype](obus)) {
+      log_e("Deinit function for previous bus type %s (%u) failed (pin %u)", perimanGetTypeName(otype), (unsigned int)otype, pin);
+      return false;
+    }
+  }
+  pins[pin].type = type;
+  pins[pin].bus = bus;
+  pins[pin].bus_num = bus_num;
+  pins[pin].bus_channel = bus_channel;
+  pins[pin].extra_type = NULL;
+  log_v("Pin %u successfully set to type %s (%u) with bus %p", pin, perimanGetTypeName(type), (unsigned int)type, bus);
+  return true;
+}
+
+bool perimanSetPinBusExtraType(uint8_t pin, const char *extra_type) {
+  if (GPIO_NOT_VALID(pin)) {
+    log_e("Invalid pin: %u", pin);
+    return false;
+  }
+  if (pins[pin].type == ESP32_BUS_TYPE_INIT) {
+    log_e("Can't set extra type for Bus INIT Type (pin %u)", pin);
+    return false;
+  }
+  pins[pin].extra_type = extra_type;
+  log_v("Successfully set extra_type %s for pin %u", extra_type, pin);
+  return true;
+}
+
+void *perimanGetPinBus(uint8_t pin, peripheral_bus_type_t type) {
+  if (GPIO_NOT_VALID(pin)) {
+    log_e("Invalid pin: %u", pin);
+    return NULL;
+  }
+  if (type >= ESP32_BUS_TYPE_MAX || type == ESP32_BUS_TYPE_INIT) {
+    log_e("Invalid type %s (%u) for pin %u", perimanGetTypeName(type), (unsigned int)type, pin);
+    return NULL;
+  }
+  if (pins[pin].type == type) {
+    return pins[pin].bus;
+  }
+  return NULL;
+}
+
+peripheral_bus_type_t perimanGetPinBusType(uint8_t pin) {
+  if (GPIO_NOT_VALID(pin)) {
+    log_e("Invalid pin: %u", pin);
+    return ESP32_BUS_TYPE_MAX;
+  }
+  return pins[pin].type;
+}
+
+const char *perimanGetPinBusExtraType(uint8_t pin) {
+  if (GPIO_NOT_VALID(pin)) {
+    log_e("Invalid pin: %u", pin);
+    return NULL;
+  }
+  return pins[pin].extra_type;
+}
+
+int8_t perimanGetPinBusNum(uint8_t pin) {
+  if (GPIO_NOT_VALID(pin)) {
+    log_e("Invalid pin: %u", pin);
+    return -1;
+  }
+  return pins[pin].bus_num;
+}
+
+int8_t perimanGetPinBusChannel(uint8_t pin) {
+  if (GPIO_NOT_VALID(pin)) {
+    log_e("Invalid pin: %u", pin);
+    return -1;
+  }
+  return pins[pin].bus_channel;
+}
+
+bool perimanSetBusDeinit(peripheral_bus_type_t type, peripheral_bus_deinit_cb_t cb) {
+  if (type >= ESP32_BUS_TYPE_MAX || type == ESP32_BUS_TYPE_INIT) {
+    log_e("Invalid type: %s (%u)", perimanGetTypeName(type), (unsigned int)type);
+    return false;
+  }
+  if (cb == NULL) {
+    log_e("Callback is NULL when setting deinit function for type %s (%u)", perimanGetTypeName(type), (unsigned int)type);
+    return false;
+  }
+  deinit_functions[type] = cb;
+  log_v("Deinit function for type %s (%u) successfully set to %p", perimanGetTypeName(type), (unsigned int)type, cb);
+  return true;
+}
+
+bool perimanPinIsValid(uint8_t pin) {
+  return !(GPIO_NOT_VALID(pin));
+}
diff --git a/cores/esp32/esp32-hal-periman.h b/cores/esp32/esp32-hal-periman.h
new file mode 100644
index 00000000000..217d62b8741
--- /dev/null
+++ b/cores/esp32/esp32-hal-periman.h
@@ -0,0 +1,148 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "soc/soc_caps.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#define perimanClearPinBus(p) perimanSetPinBus(p, ESP32_BUS_TYPE_INIT, NULL, -1, -1)
+
+typedef enum {
+  ESP32_BUS_TYPE_INIT,      // IO has not been attached to a bus yet
+  ESP32_BUS_TYPE_GPIO,      // IO is used as GPIO
+  ESP32_BUS_TYPE_UART_RX,   // IO is used as UART RX pin
+  ESP32_BUS_TYPE_UART_TX,   // IO is used as UART TX pin
+  ESP32_BUS_TYPE_UART_CTS,  // IO is used as UART CTS pin
+  ESP32_BUS_TYPE_UART_RTS,  // IO is used as UART RTS pin
+#if SOC_SDM_SUPPORTED
+  ESP32_BUS_TYPE_SIGMADELTA,  // IO is used as SigmeDelta output
+#endif
+#if SOC_ADC_SUPPORTED
+  ESP32_BUS_TYPE_ADC_ONESHOT,  // IO is used as ADC OneShot input
+  ESP32_BUS_TYPE_ADC_CONT,     // IO is used as ADC continuous input
+#endif
+#if SOC_DAC_SUPPORTED
+  ESP32_BUS_TYPE_DAC_ONESHOT,  // IO is used as DAC OneShot output
+  ESP32_BUS_TYPE_DAC_CONT,     // IO is used as DAC continuous output
+  ESP32_BUS_TYPE_DAC_COSINE,   // IO is used as DAC cosine output
+#endif
+#if SOC_LEDC_SUPPORTED
+  ESP32_BUS_TYPE_LEDC,  // IO is used as LEDC output
+#endif
+#if SOC_RMT_SUPPORTED
+  ESP32_BUS_TYPE_RMT_TX,  // IO is used as RMT output
+  ESP32_BUS_TYPE_RMT_RX,  // IO is used as RMT input
+#endif
+#if SOC_I2S_SUPPORTED
+  ESP32_BUS_TYPE_I2S_STD_MCLK,  // IO is used as I2S STD MCLK pin
+  ESP32_BUS_TYPE_I2S_STD_BCLK,  // IO is used as I2S STD BCLK pin
+  ESP32_BUS_TYPE_I2S_STD_WS,    // IO is used as I2S STD WS pin
+  ESP32_BUS_TYPE_I2S_STD_DOUT,  // IO is used as I2S STD DOUT pin
+  ESP32_BUS_TYPE_I2S_STD_DIN,   // IO is used as I2S STD DIN pin
+
+  ESP32_BUS_TYPE_I2S_TDM_MCLK,  // IO is used as I2S TDM MCLK pin
+  ESP32_BUS_TYPE_I2S_TDM_BCLK,  // IO is used as I2S TDM BCLK pin
+  ESP32_BUS_TYPE_I2S_TDM_WS,    // IO is used as I2S TDM WS pin
+  ESP32_BUS_TYPE_I2S_TDM_DOUT,  // IO is used as I2S TDM DOUT pin
+  ESP32_BUS_TYPE_I2S_TDM_DIN,   // IO is used as I2S TDM DIN pin
+
+  ESP32_BUS_TYPE_I2S_PDM_TX_CLK,    // IO is used as I2S PDM CLK pin
+  ESP32_BUS_TYPE_I2S_PDM_TX_DOUT0,  // IO is used as I2S PDM DOUT0 pin
+  ESP32_BUS_TYPE_I2S_PDM_TX_DOUT1,  // IO is used as I2S PDM DOUT1 pin
+
+  ESP32_BUS_TYPE_I2S_PDM_RX_CLK,   // IO is used as I2S PDM CLK pin
+  ESP32_BUS_TYPE_I2S_PDM_RX_DIN0,  // IO is used as I2S PDM DIN0 pin
+  ESP32_BUS_TYPE_I2S_PDM_RX_DIN1,  // IO is used as I2S PDM DIN1 pin
+  ESP32_BUS_TYPE_I2S_PDM_RX_DIN2,  // IO is used as I2S PDM DIN2 pin
+  ESP32_BUS_TYPE_I2S_PDM_RX_DIN3,  // IO is used as I2S PDM DIN3 pin
+#endif
+#if SOC_I2C_SUPPORTED
+  ESP32_BUS_TYPE_I2C_MASTER_SDA,  // IO is used as I2C master SDA pin
+  ESP32_BUS_TYPE_I2C_MASTER_SCL,  // IO is used as I2C master SCL pin
+  ESP32_BUS_TYPE_I2C_SLAVE_SDA,   // IO is used as I2C slave SDA pin
+  ESP32_BUS_TYPE_I2C_SLAVE_SCL,   // IO is used as I2C slave SCL pin
+#endif
+#if SOC_GPSPI_SUPPORTED
+  ESP32_BUS_TYPE_SPI_MASTER_SCK,   // IO is used as SPI master SCK pin
+  ESP32_BUS_TYPE_SPI_MASTER_MISO,  // IO is used as SPI master MISO pin
+  ESP32_BUS_TYPE_SPI_MASTER_MOSI,  // IO is used as SPI master MOSI pin
+  ESP32_BUS_TYPE_SPI_MASTER_SS,    // IO is used as SPI master SS pin
+#endif
+#if SOC_SDMMC_HOST_SUPPORTED
+  ESP32_BUS_TYPE_SDMMC_CLK,  // IO is used as SDMMC CLK pin
+  ESP32_BUS_TYPE_SDMMC_CMD,  // IO is used as SDMMC CMD pin
+  ESP32_BUS_TYPE_SDMMC_D0,   // IO is used as SDMMC D0 pin
+  ESP32_BUS_TYPE_SDMMC_D1,   // IO is used as SDMMC D1 pin
+  ESP32_BUS_TYPE_SDMMC_D2,   // IO is used as SDMMC D2 pin
+  ESP32_BUS_TYPE_SDMMC_D3,   // IO is used as SDMMC D3 pin
+#endif
+#if SOC_TOUCH_SENSOR_SUPPORTED
+  ESP32_BUS_TYPE_TOUCH,  // IO is used as TOUCH pin
+#endif
+#if SOC_USB_SERIAL_JTAG_SUPPORTED || SOC_USB_OTG_SUPPORTED
+  ESP32_BUS_TYPE_USB_DM,  // IO is used as USB DM (+) pin
+  ESP32_BUS_TYPE_USB_DP,  // IO is used as USB DP (-) pin
+#endif
+#if SOC_GPSPI_SUPPORTED
+  ESP32_BUS_TYPE_ETHERNET_SPI,  // IO is used as ETHERNET SPI pin
+#endif
+#if CONFIG_ETH_USE_ESP32_EMAC
+  ESP32_BUS_TYPE_ETHERNET_RMII,  // IO is used as ETHERNET RMII pin
+  ESP32_BUS_TYPE_ETHERNET_CLK,   // IO is used as ETHERNET CLK pin
+  ESP32_BUS_TYPE_ETHERNET_MCD,   // IO is used as ETHERNET MCD pin
+  ESP32_BUS_TYPE_ETHERNET_MDIO,  // IO is used as ETHERNET MDIO pin
+  ESP32_BUS_TYPE_ETHERNET_PWR,   // IO is used as ETHERNET PWR pin
+#endif
+#if CONFIG_LWIP_PPP_SUPPORT
+  ESP32_BUS_TYPE_PPP_TX,   // IO is used as PPP Modem TX pin
+  ESP32_BUS_TYPE_PPP_RX,   // IO is used as PPP Modem RX pin
+  ESP32_BUS_TYPE_PPP_RTS,  // IO is used as PPP Modem RTS pin
+  ESP32_BUS_TYPE_PPP_CTS,  // IO is used as PPP Modem CTS pin
+#endif
+  ESP32_BUS_TYPE_MAX
+} peripheral_bus_type_t;
+
+typedef bool (*peripheral_bus_deinit_cb_t)(void *bus);
+
+const char *perimanGetTypeName(peripheral_bus_type_t type);
+
+// Sets the bus type, bus handle, bus number and bus channel for given pin.
+bool perimanSetPinBus(uint8_t pin, peripheral_bus_type_t type, void *bus, int8_t bus_num, int8_t bus_channel);
+
+// Returns handle of the bus for the given pin if type of bus matches. NULL otherwise
+void *perimanGetPinBus(uint8_t pin, peripheral_bus_type_t type);
+
+// Returns the type of the bus for the given pin if attached. ESP32_BUS_TYPE_MAX otherwise
+peripheral_bus_type_t perimanGetPinBusType(uint8_t pin);
+
+// Returns the bus number or unit of the bus for the given pin if set. -1 otherwise
+int8_t perimanGetPinBusNum(uint8_t pin);
+
+// Returns the bus channel of the bus for the given pin if set. -1 otherwise
+int8_t perimanGetPinBusChannel(uint8_t pin);
+
+// Sets the peripheral destructor callback. Used to destroy bus when pin is assigned another function
+bool perimanSetBusDeinit(peripheral_bus_type_t type, peripheral_bus_deinit_cb_t cb);
+
+// Check if given pin is a valid GPIO number
+bool perimanPinIsValid(uint8_t pin);
+
+// Sets the extra type for non Init bus. Used to customize pin bus name which can be printed by printPerimanInfo().
+bool perimanSetPinBusExtraType(uint8_t pin, const char *extra_type);
+
+// Returns the extra type of the bus for given pin if set. NULL otherwise
+const char *perimanGetPinBusExtraType(uint8_t pin);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/cores/esp32/esp32-hal-psram.c b/cores/esp32/esp32-hal-psram.c
index 905cb96a313..3c7a51c3343 100644
--- a/cores/esp32/esp32-hal-psram.c
+++ b/cores/esp32/esp32-hal-psram.c
@@ -1,98 +1,153 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
 
 #include "esp32-hal.h"
 
-#if CONFIG_SPIRAM_SUPPORT
-#include "esp_spiram.h"
+#if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM
 #include "soc/efuse_reg.h"
 #include "esp_heap_caps.h"
 
+#include "esp_system.h"
+#include "esp_psram.h"
+#include "esp_private/esp_psram_extram.h"
+#if CONFIG_IDF_TARGET_ESP32  // ESP32/PICO-D4
+#include "esp32/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/cache.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/cache.h"
+#else
+#error Target CONFIG_IDF_TARGET is not supported
+#endif
+
+#define TAG "arduino-psram"
+
 static volatile bool spiramDetected = false;
 static volatile bool spiramFailed = false;
 
-bool psramInit(){
-    if (spiramDetected) {
-        return true;
-    }
+//allows user to bypass SPI RAM test routine
+__attribute__((weak)) bool testSPIRAM(void) {
+  return esp_psram_extram_test();
+}
+
+bool psramInit() {
+  if (spiramDetected) {
+    return true;
+  }
 #ifndef CONFIG_SPIRAM_BOOT_INIT
-    if (spiramFailed) {
-        return false;
-    }
-    uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
-    uint32_t pkg_ver = chip_ver & 0x7;
-    if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
-        spiramFailed = true;
-        log_w("PSRAM not supported!");
-        return false;
-    }
-    esp_spiram_init_cache();
-    if (esp_spiram_init() != ESP_OK) {
-        spiramFailed = true;
-        log_w("PSRAM init failed!");
-        pinMatrixOutDetach(16, false, false);
-        pinMatrixOutDetach(17, false, false);
-        return false;
-    }
-    if (!esp_spiram_test()) {
-        spiramFailed = true;
-        log_e("PSRAM test failed!");
-        return false;
-    }
-    if (esp_spiram_add_to_heapalloc() != ESP_OK) {
-        spiramFailed = true;
-        log_e("PSRAM could not be added to the heap!");
-        return false;
+  if (spiramFailed) {
+    return false;
+  }
+#if CONFIG_IDF_TARGET_ESP32
+  uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_PACKAGE);
+  uint32_t pkg_ver = chip_ver & 0x7;
+  if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
+    spiramFailed = true;
+    ESP_EARLY_LOGW(TAG, "PSRAM not supported!");
+    return false;
+  }
+#elif CONFIG_IDF_TARGET_ESP32S2
+  extern void esp_config_data_cache_mode(void);
+  esp_config_data_cache_mode();
+  Cache_Enable_DCache(0);
+#endif
+  if (esp_psram_init() != ESP_OK) {
+    spiramFailed = true;
+    ESP_EARLY_LOGW(TAG, "PSRAM init failed!");
+#if CONFIG_IDF_TARGET_ESP32
+    if (pkg_ver != EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
+      pinMatrixOutDetach(16, false, false);
+      pinMatrixOutDetach(17, false, false);
     }
 #endif
-    spiramDetected = true;
-    log_d("PSRAM enabled");
-    return true;
+    return false;
+  }
+  //testSPIRAM() allows user to bypass SPI RAM test routine
+  if (!testSPIRAM()) {
+    spiramFailed = true;
+    ESP_EARLY_LOGE(TAG, "PSRAM test failed!");
+    return false;
+  }
+  //ESP_EARLY_LOGI(TAG, "PSRAM enabled");
+#endif /* CONFIG_SPIRAM_BOOT_INIT */
+  spiramDetected = true;
+  return true;
 }
 
-bool IRAM_ATTR psramFound(){
-    return spiramDetected;
+bool psramAddToHeap() {
+  if (!spiramDetected) {
+    log_e("PSRAM not initialized!");
+    return false;
+  }
+  if (esp_psram_extram_add_to_heap_allocator() != ESP_OK) {
+    log_e("PSRAM could not be added to the heap!");
+    return false;
+  }
+#if CONFIG_SPIRAM_USE_MALLOC && !CONFIG_ARDUINO_ISR_IRAM
+  heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
+#endif
+  log_i("PSRAM added to the heap.");
+  return true;
 }
 
-void IRAM_ATTR *ps_malloc(size_t size){
-    if(!spiramDetected){
-        return NULL;
-    }
-    return heap_caps_malloc(size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
+bool ARDUINO_ISR_ATTR psramFound() {
+  return spiramDetected;
 }
 
-void IRAM_ATTR *ps_calloc(size_t n, size_t size){
-    if(!spiramDetected){
-        return NULL;
-    }
-    return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
+void ARDUINO_ISR_ATTR *ps_malloc(size_t size) {
+  if (!spiramDetected) {
+    return NULL;
+  }
+  return heap_caps_malloc(size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
 }
 
-void IRAM_ATTR *ps_realloc(void *ptr, size_t size){
-    if(!spiramDetected){
-        return NULL;
-    }
-    return heap_caps_realloc(ptr, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
+void ARDUINO_ISR_ATTR *ps_calloc(size_t n, size_t size) {
+  if (!spiramDetected) {
+    return NULL;
+  }
+  return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
+}
+
+void ARDUINO_ISR_ATTR *ps_realloc(void *ptr, size_t size) {
+  if (!spiramDetected) {
+    return NULL;
+  }
+  return heap_caps_realloc(ptr, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
 }
 
 #else
 
-bool psramInit(){
-    return false;
+bool psramInit() {
+  return false;
 }
 
-bool IRAM_ATTR psramFound(){
-    return false;
+bool ARDUINO_ISR_ATTR psramFound() {
+  return false;
 }
 
-void IRAM_ATTR *ps_malloc(size_t size){
-    return NULL;
+void ARDUINO_ISR_ATTR *ps_malloc(size_t size) {
+  return NULL;
 }
 
-void IRAM_ATTR *ps_calloc(size_t n, size_t size){
-    return NULL;
+void ARDUINO_ISR_ATTR *ps_calloc(size_t n, size_t size) {
+  return NULL;
 }
 
-void IRAM_ATTR *ps_realloc(void *ptr, size_t size){
-    return NULL;
+void ARDUINO_ISR_ATTR *ps_realloc(void *ptr, size_t size) {
+  return NULL;
 }
 
 #endif
diff --git a/cores/esp32/esp32-hal-psram.h b/cores/esp32/esp32-hal-psram.h
index 36acc0a03de..69c1c625157 100644
--- a/cores/esp32/esp32-hal-psram.h
+++ b/cores/esp32/esp32-hal-psram.h
@@ -19,7 +19,20 @@
 extern "C" {
 #endif
 
+#include "sdkconfig.h"
+
+// Clear flags in Arduino IDE when PSRAM is disabled
+#if defined(ESP32_ARDUINO_LIB_BUILDER) && !defined(BOARD_HAS_PSRAM)
+#ifdef CONFIG_SPIRAM_SUPPORT
+#undef CONFIG_SPIRAM_SUPPORT
+#endif
+#ifdef CONFIG_SPIRAM
+#undef CONFIG_SPIRAM
+#endif
+#endif
+
 bool psramInit();
+bool psramAddToHeap();
 bool psramFound();
 
 void *ps_malloc(size_t size);
diff --git a/cores/esp32/esp32-hal-rgb-led.c b/cores/esp32/esp32-hal-rgb-led.c
new file mode 100644
index 00000000000..d47dde53664
--- /dev/null
+++ b/cores/esp32/esp32-hal-rgb-led.c
@@ -0,0 +1,98 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/soc_caps.h"
+
+#include "esp32-hal-rgb-led.h"
+
+// Backward compatibility - Deprecated. It will be removed in future releases.
+void neopixelWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val) {
+  log_w("neopixelWrite() is deprecated. Use rgbLedWrite().");
+  rgbLedWrite(pin, red_val, green_val, blue_val);
+}
+
+void rgbLedWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val) {
+  rgbLedWriteOrdered(pin, RGB_BUILTIN_LED_COLOR_ORDER, red_val, green_val, blue_val);
+}
+
+void rgbLedWriteOrdered(uint8_t pin, rgb_led_color_order_t order, uint8_t red_val, uint8_t green_val, uint8_t blue_val) {
+#if SOC_RMT_SUPPORTED
+  rmt_data_t led_data[24];
+
+  // Verify if the pin used is RGB_BUILTIN and fix GPIO number
+#ifdef RGB_BUILTIN
+  pin = pin == RGB_BUILTIN ? pin - SOC_GPIO_PIN_COUNT : pin;
+#endif
+  if (!rmtInit(pin, RMT_TX_MODE, RMT_MEM_NUM_BLOCKS_1, 10000000)) {
+    log_e("RGB LED driver initialization failed for GPIO%d!", pin);
+    return;
+  }
+
+  // default WS2812B color order is G, R, B
+  int color[3] = {green_val, red_val, blue_val};
+
+  switch (order) {
+    case LED_COLOR_ORDER_RGB:
+      color[0] = red_val;
+      color[1] = green_val;
+      color[2] = blue_val;
+      break;
+    case LED_COLOR_ORDER_BGR:
+      color[0] = blue_val;
+      color[1] = green_val;
+      color[2] = red_val;
+      break;
+    case LED_COLOR_ORDER_BRG:
+      color[0] = blue_val;
+      color[1] = red_val;
+      color[2] = green_val;
+      break;
+    case LED_COLOR_ORDER_RBG:
+      color[0] = red_val;
+      color[1] = blue_val;
+      color[2] = green_val;
+      break;
+    case LED_COLOR_ORDER_GBR:
+      color[0] = green_val;
+      color[1] = blue_val;
+      color[2] = red_val;
+      break;
+    default:  // GRB
+      break;
+  }
+
+  int i = 0;
+  for (int col = 0; col < 3; col++) {
+    for (int bit = 0; bit < 8; bit++) {
+      if ((color[col] & (1 << (7 - bit)))) {
+        // HIGH bit
+        led_data[i].level0 = 1;     // T1H
+        led_data[i].duration0 = 8;  // 0.8us
+        led_data[i].level1 = 0;     // T1L
+        led_data[i].duration1 = 4;  // 0.4us
+      } else {
+        // LOW bit
+        led_data[i].level0 = 1;     // T0H
+        led_data[i].duration0 = 4;  // 0.4us
+        led_data[i].level1 = 0;     // T0L
+        led_data[i].duration1 = 8;  // 0.8us
+      }
+      i++;
+    }
+  }
+  rmtWrite(pin, led_data, RMT_SYMBOLS_OF(led_data), RMT_WAIT_FOR_EVER);
+#else
+  log_e("RMT is not supported on " CONFIG_IDF_TARGET);
+#endif /* SOC_RMT_SUPPORTED */
+}
diff --git a/cores/esp32/esp32-hal-rgb-led.h b/cores/esp32/esp32-hal-rgb-led.h
new file mode 100644
index 00000000000..b151732e565
--- /dev/null
+++ b/cores/esp32/esp32-hal-rgb-led.h
@@ -0,0 +1,40 @@
+#ifndef MAIN_ESP32_HAL_RGB_LED_H_
+#define MAIN_ESP32_HAL_RGB_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "esp32-hal.h"
+
+#ifndef RGB_BRIGHTNESS
+#define RGB_BRIGHTNESS 64
+#endif
+
+#ifndef RGB_BUILTIN_LED_COLOR_ORDER
+#define RGB_BUILTIN_LED_COLOR_ORDER LED_COLOR_ORDER_GRB  // default WS2812B color order
+#endif
+
+typedef enum {
+  LED_COLOR_ORDER_RGB,
+  LED_COLOR_ORDER_BGR,
+  LED_COLOR_ORDER_BRG,
+  LED_COLOR_ORDER_RBG,
+  LED_COLOR_ORDER_GBR,
+  LED_COLOR_ORDER_GRB
+} rgb_led_color_order_t;
+
+void rgbLedWriteOrdered(uint8_t pin, rgb_led_color_order_t order, uint8_t red_val, uint8_t green_val, uint8_t blue_val);
+
+// Will use RGB_BUILTIN_LED_COLOR_ORDER
+void rgbLedWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val);
+
+// Backward compatibility - Deprecated. It will be removed in future releases.
+[[deprecated("Use rgbLedWrite() instead.")]]
+void neopixelWrite(uint8_t p, uint8_t r, uint8_t g, uint8_t b);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MAIN_ESP32_HAL_RGB_LED_H_ */
diff --git a/cores/esp32/esp32-hal-rmt.c b/cores/esp32/esp32-hal-rmt.c
index 07750d96bba..7bca1a1b529 100644
--- a/cores/esp32/esp32-hal-rmt.c
+++ b/cores/esp32/esp32-hal-rmt.c
@@ -1,4 +1,4 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -12,844 +12,625 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "freertos/FreeRTOS.h"
-#include "freertos/event_groups.h"
-#include "freertos/semphr.h"
+#include "soc/soc_caps.h"
 
+#if SOC_RMT_SUPPORTED
 #include "esp32-hal.h"
-#include "esp8266-compat.h"
-#include "soc/gpio_reg.h"
-#include "soc/gpio_reg.h"
+#include "driver/gpio.h"
+#include "driver/rmt_tx.h"
+#include "driver/rmt_rx.h"
+#include "hal/rmt_ll.h"
 
 #include "esp32-hal-rmt.h"
-#include "driver/periph_ctrl.h"
+#include "esp32-hal-periman.h"
+#include "esp_idf_version.h"
 
-#include "soc/rmt_struct.h"
-#include "esp_intr_alloc.h"
+// Arduino Task Handle indicates if the Arduino Task has been started already
+extern TaskHandle_t loopTaskHandle;
+
+// RMT Events
+#define RMT_FLAG_RX_DONE (1)
+#define RMT_FLAG_TX_DONE (2)
 
 /**
- * Internal macros
- */
-#define MAX_CHANNELS 8
-#define MAX_DATA_PER_CHANNEL 64
-#define MAX_DATA_PER_ITTERATION 62
-#define _ABS(a) (a>0?a:-a)
-#define _LIMIT(a,b) (a>b?b:a)
-#define __INT_TX_END     (1)
-#define __INT_RX_END     (2)
-#define __INT_ERROR      (4)
-#define __INT_THR_EVNT   (1<<24)
-
-#define _INT_TX_END(channel) (__INT_TX_END<<(channel*3))
-#define _INT_RX_END(channel) (__INT_RX_END<<(channel*3))
-#define _INT_ERROR(channel)  (__INT_ERROR<<(channel*3))
-#define _INT_THR_EVNT(channel)  ((__INT_THR_EVNT)<<(channel))
+   Internal macros
+*/
 
 #if CONFIG_DISABLE_HAL_LOCKS
-# define RMT_MUTEX_LOCK(channel)
-# define RMT_MUTEX_UNLOCK(channel)
+#define RMT_MUTEX_LOCK(busptr)
+#define RMT_MUTEX_UNLOCK(busptr)
 #else
-# define RMT_MUTEX_LOCK(channel)    do {} while (xSemaphoreTake(g_rmt_objlocks[channel], portMAX_DELAY) != pdPASS)
-# define RMT_MUTEX_UNLOCK(channel)  xSemaphoreGive(g_rmt_objlocks[channel])
+#define RMT_MUTEX_LOCK(busptr) \
+  do {                         \
+  } while (xSemaphoreTake(busptr->g_rmt_objlocks, portMAX_DELAY) != pdPASS)
+#define RMT_MUTEX_UNLOCK(busptr) xSemaphoreGive(busptr->g_rmt_objlocks)
 #endif /* CONFIG_DISABLE_HAL_LOCKS */
 
-#define _RMT_INTERNAL_DEBUG
-#ifdef _RMT_INTERNAL_DEBUG
-# define DEBUG_INTERRUPT_START(pin)    digitalWrite(pin, 1);
-# define DEBUG_INTERRUPT_END(pin)      digitalWrite(pin, 0);
-#else
-# define DEBUG_INTERRUPT_START(pin)
-# define DEBUG_INTERRUPT_END(pin)
-#endif /* _RMT_INTERNAL_DEBUG */
-
 /**
- * Typedefs for internal stuctures, enums
- */
-typedef enum {
-    E_NO_INTR = 0,
-    E_TX_INTR = 1,
-    E_TXTHR_INTR = 2,
-    E_RX_INTR = 4,
-} intr_mode_t;
-
-typedef enum {
-    E_INACTIVE   = 0,
-    E_FIRST_HALF = 1,
-    E_LAST_DATA  = 2,
-    E_END_TRANS  = 4,
-    E_SET_CONTI =  8,
-} transaction_state_t;
-
-struct rmt_obj_s
-{
-    bool allocated;
-    EventGroupHandle_t events;
-    int pin;
-    int channel;
-    bool tx_not_rx;
-    int buffers;
-    int data_size;
-    uint32_t* data_ptr;
-    intr_mode_t intr_mode;
-    transaction_state_t tx_state;
-    rmt_rx_data_cb_t cb;
-    bool data_alloc;
-    void * arg;
-};
+   Typedefs for internal structures, enums
+*/
 
-/**
- * Internal variables for channel descriptors
- */
-static xSemaphoreHandle g_rmt_objlocks[MAX_CHANNELS] = {
-    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
-};
+struct rmt_obj_s {
+  // general RMT information
+  rmt_channel_handle_t rmt_channel_h;       // IDF RMT channel handler
+  rmt_encoder_handle_t rmt_copy_encoder_h;  // RMT simple copy encoder handle
 
-static rmt_obj_t g_rmt_objects[MAX_CHANNELS] = {
-    { false, NULL, 0, 0, 0, 0, 0, NULL, E_NO_INTR, E_INACTIVE, NULL, false, NULL},
-    { false, NULL, 0, 0, 0, 0, 0, NULL, E_NO_INTR, E_INACTIVE, NULL, false, NULL},
-    { false, NULL, 0, 0, 0, 0, 0, NULL, E_NO_INTR, E_INACTIVE, NULL, false, NULL},
-    { false, NULL, 0, 0, 0, 0, 0, NULL, E_NO_INTR, E_INACTIVE, NULL, false, NULL},
-    { false, NULL, 0, 0, 0, 0, 0, NULL, E_NO_INTR, E_INACTIVE, NULL, false, NULL},
-    { false, NULL, 0, 0, 0, 0, 0, NULL, E_NO_INTR, E_INACTIVE, NULL, false, NULL},
-    { false, NULL, 0, 0, 0, 0, 0, NULL, E_NO_INTR, E_INACTIVE, NULL, false, NULL},
-    { false, NULL, 0, 0, 0, 0, 0, NULL, E_NO_INTR, E_INACTIVE, NULL, false, NULL},
-};
+  uint32_t signal_range_min_ns;  // RX Filter data - Low Pass pulse width
+  uint32_t signal_range_max_ns;  // RX idle time that defines end of reading
 
-/**
- * Internal variables for driver data
- */
-static  intr_handle_t intr_handle;
+  EventGroupHandle_t rmt_events;   // read/write done event RMT callback handle
+  bool rmt_ch_is_looping;          // Is this RMT TX Channel in LOOPING MODE?
+  size_t *num_symbols_read;        // Pointer to the number of RMT symbol read by IDF RMT RX Done
+  rmt_reserve_memsize_t mem_size;  // RMT Memory size
+  uint32_t frequency_Hz;           // RMT Frequency
+  uint8_t rmt_EOT_Level;           // RMT End of Transmission Level - default is LOW
 
-static bool periph_enabled = false;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  SemaphoreHandle_t g_rmt_objlocks;  // Channel Semaphore Lock
+#endif                               /* CONFIG_DISABLE_HAL_LOCKS */
+};
 
-static xSemaphoreHandle g_rmt_block_lock = NULL;
+typedef struct rmt_obj_s *rmt_bus_handle_t;
 
 /**
- * Internal method (private) declarations
- */
-static void _initPin(int pin, int channel, bool tx_not_rx);
-
-static bool _rmtSendOnce(rmt_obj_t* rmt, rmt_data_t* data, size_t size, bool continuous);
-
-static void IRAM_ATTR _rmt_isr(void* arg);
-
-static rmt_obj_t* _rmtAllocate(int pin, int from, int size);
-
-static void _initPin(int pin, int channel, bool tx_not_rx);
-
-static int IRAM_ATTR _rmt_get_mem_len(uint8_t channel);
-
-static void IRAM_ATTR _rmt_tx_mem_first(uint8_t ch);
-
-static void IRAM_ATTR _rmt_tx_mem_second(uint8_t ch);
-
+   Internal variables used in RMT API
+*/
+static SemaphoreHandle_t g_rmt_block_lock = NULL;
 
 /**
- * Public method definitions
- */
-bool rmtSetCarrier(rmt_obj_t* rmt, bool carrier_en, bool carrier_level, uint32_t low, uint32_t high)
-{
-    if (!rmt || low > 0xFFFF || high > 0xFFFF) {
-        return false;
-    }
-    size_t channel = rmt->channel;
-
-    RMT_MUTEX_LOCK(channel);
-
-    RMT.carrier_duty_ch[channel].low = low;
-    RMT.carrier_duty_ch[channel].high = high;
-    RMT.conf_ch[channel].conf0.carrier_en = carrier_en;
-    RMT.conf_ch[channel].conf0.carrier_out_lv = carrier_level;
-
-    RMT_MUTEX_UNLOCK(channel);
-
-    return true;
-
+   Internal method (private) declarations
+*/
+
+// This is called from an IDF ISR code, therefore this code is part of an ISR
+static bool _rmt_rx_done_callback(rmt_channel_handle_t channel, const rmt_rx_done_event_data_t *data, void *args) {
+  BaseType_t high_task_wakeup = pdFALSE;
+  rmt_bus_handle_t bus = (rmt_bus_handle_t)args;
+  // sets the returning number of RMT symbols (32 bits) effectively read
+  *bus->num_symbols_read = data->num_symbols;
+  // set RX event group and signal the received RMT symbols of that channel
+  xEventGroupSetBitsFromISR(bus->rmt_events, RMT_FLAG_RX_DONE, &high_task_wakeup);
+  // A "need to yield" is returned in order to execute portYIELD_FROM_ISR() in the main IDF RX ISR
+  return high_task_wakeup == pdTRUE;
 }
 
-bool rmtSetFilter(rmt_obj_t* rmt, bool filter_en, uint32_t filter_level)
-{
-    if (!rmt || filter_level > 0xFF) {
-        return false;
-    }
-    size_t channel = rmt->channel;
-
-    RMT_MUTEX_LOCK(channel);
-
-    RMT.conf_ch[channel].conf1.rx_filter_thres = filter_level;
-    RMT.conf_ch[channel].conf1.rx_filter_en = filter_en;
-
-    RMT_MUTEX_UNLOCK(channel);
-
-    return true;
-
+// This is called from an IDF ISR code, therefore this code is part of an ISR
+static bool _rmt_tx_done_callback(rmt_channel_handle_t channel, const rmt_tx_done_event_data_t *data, void *args) {
+  BaseType_t high_task_wakeup = pdFALSE;
+  rmt_bus_handle_t bus = (rmt_bus_handle_t)args;
+  // set RX event group and signal the received RMT symbols of that channel
+  xEventGroupSetBitsFromISR(bus->rmt_events, RMT_FLAG_TX_DONE, &high_task_wakeup);
+  // A "need to yield" is returned in order to execute portYIELD_FROM_ISR() in the main IDF RX ISR
+  return high_task_wakeup == pdTRUE;
 }
 
-bool rmtSetRxThreshold(rmt_obj_t* rmt, uint32_t value)
-{
-    if (!rmt || value > 0xFFFF) {
-        return false;
-    }
-    size_t channel = rmt->channel;
-
-    RMT_MUTEX_LOCK(channel);
-    RMT.conf_ch[channel].conf0.idle_thres = value;
-    RMT_MUTEX_UNLOCK(channel);
+// This function must be called only after checking the pin and its bus with _rmtGetBus()
+static bool _rmtCheckDirection(uint8_t gpio_num, rmt_ch_dir_t rmt_dir, const char *labelFunc) {
+  // gets bus RMT direction from the Peripheral Manager information
+  rmt_ch_dir_t bus_rmt_dir = perimanGetPinBusType(gpio_num) == ESP32_BUS_TYPE_RMT_TX ? RMT_TX_MODE : RMT_RX_MODE;
 
+  if (bus_rmt_dir == rmt_dir) {  // matches expected RX/TX channel
     return true;
+  }
+
+  // print error message
+  if (rmt_dir == RMT_RX_MODE) {
+    log_w("==>%s():Channel set as TX instead of RX.", labelFunc);
+  } else {
+    log_w("==>%s():Channel set as RX instead of TX.", labelFunc);
+  }
+  return false;  // mismatched
 }
 
+static rmt_bus_handle_t _rmtGetBus(int pin, const char *labelFunc) {
+  // Is pin RX or TX? Let's find it out
+  peripheral_bus_type_t rmt_bus_type = perimanGetPinBusType(pin);
+  if (rmt_bus_type != ESP32_BUS_TYPE_RMT_TX && rmt_bus_type != ESP32_BUS_TYPE_RMT_RX) {
+    log_e("==>%s():GPIO %u is not attached to an RMT channel.", labelFunc, pin);
+    return NULL;
+  }
 
-bool rmtDeinit(rmt_obj_t *rmt)
-{
-    if (!rmt) {
-        return false;
-    }
-
-    // sanity check
-    if (rmt != &(g_rmt_objects[rmt->channel])) {
-        return false;
-    }
-
-    size_t from = rmt->channel;
-    size_t to = rmt->buffers + rmt->channel;
-    size_t i;
+  return (rmt_bus_handle_t)perimanGetPinBus(pin, rmt_bus_type);
+}
 
+// Peripheral Manager detach callback
+static bool _rmtDetachBus(void *busptr) {
+  // sanity check - it should never happen
+  assert(busptr && "_rmtDetachBus bus NULL pointer.");
+
+  bool retCode = true;
+  rmt_bus_handle_t bus = (rmt_bus_handle_t)busptr;
+  log_v("Detaching RMT GPIO Bus");
+
+  // lock it
+  while (xSemaphoreTake(g_rmt_block_lock, portMAX_DELAY) != pdPASS) {}
+
+  // free Event Group
+  if (bus->rmt_events != NULL) {
+    vEventGroupDelete(bus->rmt_events);
+    bus->rmt_events = NULL;
+  }
+  // deallocate the channel encoder
+  if (bus->rmt_copy_encoder_h != NULL) {
+    if (ESP_OK != rmt_del_encoder(bus->rmt_copy_encoder_h)) {
+      log_w("RMT Encoder Deletion has failed.");
+      retCode = false;
+    }
+  }
+  // disable and deallocate RMT channel
+  if (bus->rmt_channel_h != NULL) {
+    // force stopping rmt TX/RX processing and unlock Power Management (APB Freq)
+    rmt_disable(bus->rmt_channel_h);
+    if (ESP_OK != rmt_del_channel(bus->rmt_channel_h)) {
+      log_w("RMT Channel Deletion has failed.");
+      retCode = false;
+    }
+  }
 #if !CONFIG_DISABLE_HAL_LOCKS
-    if(g_rmt_objlocks[from] != NULL) {
-        vSemaphoreDelete(g_rmt_objlocks[from]);
-    }
+  // deallocate channel semaphore
+  if (bus->g_rmt_objlocks != NULL) {
+    vSemaphoreDelete(bus->g_rmt_objlocks);
+  }
 #endif
+  // free the allocated bus data structure
+  free(bus);
 
-    if (g_rmt_objects[from].data_alloc) {
-        free(g_rmt_objects[from].data_ptr);
-    }
-    
-    for (i = from; i < to; i++) {
-        g_rmt_objects[i].allocated = false;
-    }
-
-    g_rmt_objects[from].channel = 0;
-    g_rmt_objects[from].buffers = 0;
-
-    return true;
+  // release the mutex
+  xSemaphoreGive(g_rmt_block_lock);
+  return retCode;
 }
 
-bool rmtLoop(rmt_obj_t* rmt, rmt_data_t* data, size_t size)
-{
-    if (!rmt) {
-        return false;
-    }
-
-    int channel = rmt->channel;
-    int allocated_size = MAX_DATA_PER_CHANNEL * rmt->buffers;
-
-    if (size > allocated_size) {
-        return false;
-    }
-    return _rmtSendOnce(rmt, data, size, true);
+/**
+   Public method definitions
+*/
+
+bool rmtSetEOT(int pin, uint8_t EOT_Level) {
+  rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__);
+  if (bus == NULL) {
+    return false;
+  }
+  if (!_rmtCheckDirection(pin, RMT_TX_MODE, __FUNCTION__)) {
+    return false;
+  }
+
+  bus->rmt_EOT_Level = EOT_Level > 0 ? 1 : 0;
+  return true;
 }
 
-bool rmtWrite(rmt_obj_t* rmt, rmt_data_t* data, size_t size)
-{
-    if (!rmt) {
-        return false;
-    }
-    
-    int channel = rmt->channel;
-    int allocated_size = MAX_DATA_PER_CHANNEL * rmt->buffers;
-
-    if (size > allocated_size) {
-
-        int half_tx_nr = MAX_DATA_PER_ITTERATION/2;
-        RMT_MUTEX_LOCK(channel);
-        // setup interrupt handler if not yet installed for half and full tx
-        if (!intr_handle) {
-            esp_intr_alloc(ETS_RMT_INTR_SOURCE, (int)ESP_INTR_FLAG_IRAM, _rmt_isr, NULL, &intr_handle);
-        }
-
-        rmt->data_size = size - MAX_DATA_PER_ITTERATION;
-        rmt->data_ptr = ((uint32_t*)data) + MAX_DATA_PER_ITTERATION;
-        rmt->intr_mode = E_TX_INTR | E_TXTHR_INTR;
-        rmt->tx_state = E_SET_CONTI | E_FIRST_HALF;
-
-        // init the tx limit for interruption
-        RMT.tx_lim_ch[channel].limit = half_tx_nr+2;
-        // reset memory pointer
-        RMT.conf_ch[channel].conf1.apb_mem_rst = 1;
-        RMT.conf_ch[channel].conf1.apb_mem_rst = 0;
-        RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
-        RMT.conf_ch[channel].conf1.mem_rd_rst = 0;
-        RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
-        RMT.conf_ch[channel].conf1.mem_wr_rst = 0;
-
-        // set the tx end mark
-        RMTMEM.chan[channel].data32[MAX_DATA_PER_ITTERATION].val = 0;
-
-        // clear and enable both Tx completed and half tx event
-        RMT.int_clr.val = _INT_TX_END(channel);
-        RMT.int_clr.val = _INT_THR_EVNT(channel);
-        RMT.int_clr.val = _INT_ERROR(channel);
-        
-        RMT.int_ena.val |= _INT_TX_END(channel);
-        RMT.int_ena.val |= _INT_THR_EVNT(channel);
-        RMT.int_ena.val |= _INT_ERROR(channel);
-
-        RMT_MUTEX_UNLOCK(channel);
-
-        // start the transation
-        return _rmtSendOnce(rmt, data, MAX_DATA_PER_ITTERATION, false);
-    } else {
-        // use one-go mode if data fits one buffer 
-        return _rmtSendOnce(rmt, data, size, false);
-    }
+bool rmtSetCarrier(int pin, bool carrier_en, bool carrier_level, uint32_t frequency_Hz, float duty_percent) {
+  rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__);
+  if (bus == NULL) {
+    return false;
+  }
+
+  if (duty_percent > 1) {
+    log_w("GPIO %d - RMT Carrier must be a float percentage from 0 to 1. Setting to 50%.", pin);
+    duty_percent = 0.5;
+  }
+  rmt_carrier_config_t carrier_cfg;
+  memset((void *)&carrier_cfg, 0, sizeof(rmt_carrier_config_t));
+  carrier_cfg.duty_cycle = duty_percent;                     // duty cycle
+  carrier_cfg.frequency_hz = carrier_en ? frequency_Hz : 0;  // carrier frequency in Hz
+  carrier_cfg.flags.polarity_active_low = carrier_level;     // carrier modulation polarity level
+
+  bool retCode = true;
+  RMT_MUTEX_LOCK(bus);
+  // modulate carrier to TX channel
+  if (ESP_OK != rmt_apply_carrier(bus->rmt_channel_h, &carrier_cfg)) {
+    log_w("GPIO %d - Error applying RMT carrier.", pin);
+    retCode = false;
+  }
+  RMT_MUTEX_UNLOCK(bus);
+
+  return retCode;
 }
 
-bool rmtReadData(rmt_obj_t* rmt, uint32_t* data, size_t size)
-{
-    if (!rmt) {
-        return false;
-    }
-    int channel = rmt->channel;
-
-    if (g_rmt_objects[channel].buffers < size/MAX_DATA_PER_CHANNEL) {
-        return false;
-    }
-
-    size_t i;
-    volatile uint32_t* rmt_mem_ptr = &(RMTMEM.chan[channel].data32[0].val);
-    for (i=0; i<size; i++) {
-        data[i] = *rmt_mem_ptr++;
-    }
+bool rmtSetRxMinThreshold(int pin, uint8_t filter_pulse_ticks) {
+  rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__);
+  if (bus == NULL) {
+    return false;
+  }
+
+  if (!_rmtCheckDirection(pin, RMT_RX_MODE, __FUNCTION__)) {
+    return false;
+  }
+
+  uint32_t filter_pulse_ns = (1000000000 / bus->frequency_Hz) * filter_pulse_ticks;
+  // RMT_LL_MAX_FILTER_VALUE is 255 for ESP32, S2, S3, C3, C6 and H2;
+  // filter_pulse_ticks is 8 bits, thus it will not exceed 255
+#if 0  // for the future, in case some other SoC has different limit
+  if (filter_pulse_ticks > RMT_LL_MAX_FILTER_VALUE) {
+    log_e("filter_pulse_ticks is too big. Max = %d", RMT_LL_MAX_FILTER_VALUE);
+    return false;
+  }
+#endif
 
-    return true;
+  RMT_MUTEX_LOCK(bus);
+  bus->signal_range_min_ns = filter_pulse_ns;  // set zero to disable it
+  RMT_MUTEX_UNLOCK(bus);
+  return true;
 }
 
+bool rmtSetRxMaxThreshold(int pin, uint16_t idle_thres_ticks) {
+  rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__);
+  if (bus == NULL) {
+    return false;
+  }
+
+  if (!_rmtCheckDirection(pin, RMT_RX_MODE, __FUNCTION__)) {
+    return false;
+  }
+
+  uint32_t idle_thres_ns = (1000000000 / bus->frequency_Hz) * idle_thres_ticks;
+  // RMT_LL_MAX_IDLE_VALUE is 65535 for ESP32,S2 and 32767 for S3, C3, C6 and H2
+#if RMT_LL_MAX_IDLE_VALUE < 65535  // idle_thres_ticks is 16 bits anyway - save some bytes
+  if (idle_thres_ticks > RMT_LL_MAX_IDLE_VALUE) {
+    log_e("idle_thres_ticks is too big. Max = %ld", RMT_LL_MAX_IDLE_VALUE);
+    return false;
+  }
+#endif
 
-bool rmtBeginReceive(rmt_obj_t* rmt)
-{
-    if (!rmt) {
-        return false;
-    }
-    int channel = rmt->channel;
-
-    RMT.int_clr.val = _INT_ERROR(channel);
-    RMT.int_ena.val |= _INT_ERROR(channel);
-
-    RMT.conf_ch[channel].conf1.mem_owner = 1;
-    RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
-    RMT.conf_ch[channel].conf1.rx_en = 1;
-
-    return true;
+  RMT_MUTEX_LOCK(bus);
+  bus->signal_range_max_ns = idle_thres_ns;
+  RMT_MUTEX_UNLOCK(bus);
+  return true;
 }
 
-bool rmtReceiveCompleted(rmt_obj_t* rmt)
-{
-    if (!rmt) {
-        return false;
-    }
-    int channel = rmt->channel;
+bool rmtDeinit(int pin) {
+  log_v("Deiniting RMT GPIO %d", pin);
+  if (_rmtGetBus(pin, __FUNCTION__) != NULL) {
+    // release all allocated data
+    return perimanClearPinBus(pin);
+  }
+  log_e("GPIO %d - No RMT channel associated.", pin);
+  return false;
+}
 
-    if (RMT.int_raw.val&_INT_RX_END(channel)) {
-        // RX end flag
-        RMT.int_clr.val = _INT_RX_END(channel);
-        return true;
+static bool _rmtWrite(int pin, rmt_data_t *data, size_t num_rmt_symbols, bool blocking, bool loop, uint32_t timeout_ms) {
+  rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__);
+  if (bus == NULL) {
+    return false;
+  }
+  if (!_rmtCheckDirection(pin, RMT_TX_MODE, __FUNCTION__)) {
+    return false;
+  }
+  bool loopCancel = false;  // user wants to cancel the writing loop mode
+  if (data == NULL || num_rmt_symbols == 0) {
+    if (!loop) {
+      log_w("GPIO %d - RMT Write Data NULL pointer or size is zero.", pin);
+      return false;
     } else {
-        return false;
+      loopCancel = true;
+    }
+  }
+
+  log_v("GPIO: %d - Request: %d RMT Symbols - %s - Timeout: %d", pin, num_rmt_symbols, blocking ? "Blocking" : "Non-Blocking", timeout_ms);
+  log_v(
+    "GPIO: %d - Currently in Loop Mode: [%s] | Asked to Loop: %s, LoopCancel: %s", pin, bus->rmt_ch_is_looping ? "YES" : "NO", loop ? "YES" : "NO",
+    loopCancel ? "YES" : "NO"
+  );
+
+  if ((xEventGroupGetBits(bus->rmt_events) & RMT_FLAG_TX_DONE) == 0) {
+    log_v("GPIO %d - RMT Write still pending to be completed.", pin);
+    return false;
+  }
+
+  rmt_transmit_config_t transmit_cfg;  // loop mode disabled
+  memset((void *)&transmit_cfg, 0, sizeof(rmt_transmit_config_t));
+  bool retCode = true;
+
+  RMT_MUTEX_LOCK(bus);
+  // wants to start in writing or looping over a previous looping --> resets the channel
+  if (bus->rmt_ch_is_looping == true) {
+    // must force stopping a previous loop transmission first
+    rmt_disable(bus->rmt_channel_h);
+    // enable it again for looping or writing
+    rmt_enable(bus->rmt_channel_h);
+    bus->rmt_ch_is_looping = false;  // not looping anymore
+  }
+  // sets the End of Transmission level to HIGH if the user has requested so
+  if (bus->rmt_EOT_Level) {
+    transmit_cfg.flags.eot_level = 1;  // EOT is HIGH
+  }
+  if (loopCancel) {
+    // just resets and releases the channel, maybe, already done above, then exits
+    bus->rmt_ch_is_looping = false;
+  } else {  // new writing | looping request
+    // looping | Writing over a previous looping state is valid
+    if (loop) {
+      transmit_cfg.loop_count = -1;  // enable infinite loop mode
+      // keeps RMT_FLAG_TX_DONE set - it never changes
+    } else {
+      // looping mode never sets this flag (IDF 5.1) in the callback
+      xEventGroupClearBits(bus->rmt_events, RMT_FLAG_TX_DONE);
+    }
+    // transmits just once or looping data
+    if (ESP_OK != rmt_transmit(bus->rmt_channel_h, bus->rmt_copy_encoder_h, (const void *)data, num_rmt_symbols * sizeof(rmt_data_t), &transmit_cfg)) {
+      retCode = false;
+      log_w("GPIO %d - RMT Transmission failed.", pin);
+    } else {  // transmit OK
+      if (loop) {
+        bus->rmt_ch_is_looping = true;  // for ever... until a channel canceling or new writing
+      } else {
+        if (blocking) {
+          // wait for transmission confirmation | timeout
+          retCode = (xEventGroupWaitBits(bus->rmt_events, RMT_FLAG_TX_DONE, pdFALSE /* do not clear on exit */, pdFALSE /* wait for all bits */, timeout_ms)
+                     & RMT_FLAG_TX_DONE)
+                    != 0;
+        }
+      }
     }
+  }
+  RMT_MUTEX_UNLOCK(bus);
+  return retCode;
 }
 
-bool rmtRead(rmt_obj_t* rmt, rmt_rx_data_cb_t cb, void * arg)
-{
-    if (!rmt && !cb) {
-        return false;
-    }
-    int channel = rmt->channel;
-
-    RMT_MUTEX_LOCK(channel);
-    rmt->arg = arg;
-    rmt->intr_mode = E_RX_INTR;
-    rmt->tx_state = E_FIRST_HALF;
-    rmt->cb = cb;
-    // allocate internally two buffers which would alternate
-    if (!rmt->data_alloc) {
-        rmt->data_ptr = (uint32_t*)malloc(2*MAX_DATA_PER_CHANNEL*(rmt->buffers)*sizeof(uint32_t));
-        rmt->data_size = MAX_DATA_PER_CHANNEL*rmt->buffers;
-        rmt->data_alloc = true;
-    }
-
-    RMT.conf_ch[channel].conf1.mem_owner = 1;
-
-    RMT.int_clr.val = _INT_RX_END(channel);
-    RMT.int_clr.val = _INT_ERROR(channel);
-    
-    RMT.int_ena.val |= _INT_RX_END(channel);
-    RMT.int_ena.val |= _INT_ERROR(channel);
-
-    RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
-
-    RMT.conf_ch[channel].conf1.rx_en = 1;
-    RMT_MUTEX_UNLOCK(channel);
-
-    return true;
+static bool _rmtRead(int pin, rmt_data_t *data, size_t *num_rmt_symbols, bool waitForData, uint32_t timeout_ms) {
+  rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__);
+  if (bus == NULL) {
+    return false;
+  }
+  if (!_rmtCheckDirection(pin, RMT_RX_MODE, __FUNCTION__)) {
+    return false;
+  }
+  if (data == NULL || num_rmt_symbols == NULL) {
+    log_w("GPIO %d - RMT Read Data and/or Size NULL pointer.", pin);
+    return false;
+  }
+  log_v("GPIO: %d - Request: %d RMT Symbols - %s - Timeout: %d", pin, *num_rmt_symbols, waitForData ? "Blocking" : "Non-Blocking", timeout_ms);
+  bool retCode = true;
+  RMT_MUTEX_LOCK(bus);
+
+  // request reading RMT Channel Data
+  rmt_receive_config_t receive_config;
+  memset((void *)&receive_config, 0, sizeof(rmt_receive_config_t));
+  receive_config.signal_range_min_ns = bus->signal_range_min_ns;
+  receive_config.signal_range_max_ns = bus->signal_range_max_ns;
+
+  xEventGroupClearBits(bus->rmt_events, RMT_FLAG_RX_DONE);
+  bus->num_symbols_read = num_rmt_symbols;
+
+  rmt_receive(bus->rmt_channel_h, data, *num_rmt_symbols * sizeof(rmt_data_t), &receive_config);
+  // wait for data if requested
+  if (waitForData) {
+    retCode = (xEventGroupWaitBits(bus->rmt_events, RMT_FLAG_RX_DONE, pdFALSE /* do not clear on exit */, pdFALSE /* wait for all bits */, timeout_ms)
+               & RMT_FLAG_RX_DONE)
+              != 0;
+  }
+
+  RMT_MUTEX_UNLOCK(bus);
+  return retCode;
 }
 
-bool rmtEnd(rmt_obj_t* rmt) {
-    if (!rmt) {
-        return false;
-    }
-    int channel = rmt->channel;
-
-    RMT_MUTEX_LOCK(channel);
-    RMT.conf_ch[channel].conf1.rx_en = 1;
-    RMT_MUTEX_UNLOCK(channel);
-
-    return  true;
+bool rmtWrite(int pin, rmt_data_t *data, size_t num_rmt_symbols, uint32_t timeout_ms) {
+  return _rmtWrite(pin, data, num_rmt_symbols, true /*blocks*/, false /*looping*/, timeout_ms);
 }
 
-bool rmtReadAsync(rmt_obj_t* rmt, rmt_data_t* data, size_t size, void* eventFlag, bool waitForData, uint32_t timeout)
-{
-    if (!rmt) {
-        return false;
-    }
-    int channel = rmt->channel;
-
-    if (g_rmt_objects[channel].buffers < size/MAX_DATA_PER_CHANNEL) {
-        return false;
-    }
-
-    if (eventFlag) {
-        xEventGroupClearBits(eventFlag, RMT_FLAGS_ALL);
-        rmt->events = eventFlag;
-    }
-
-    if (data && size>0) {
-        rmt->data_ptr = (uint32_t*)data;
-        rmt->data_size = size;
-    }
-
-    RMT_MUTEX_LOCK(channel);
-    rmt->intr_mode = E_RX_INTR;
-
-    RMT.conf_ch[channel].conf1.mem_owner = 1;
-
-    RMT.int_clr.val = _INT_RX_END(channel);
-    RMT.int_clr.val = _INT_ERROR(channel);
-    
-    RMT.int_ena.val |= _INT_RX_END(channel);
-    RMT.int_ena.val |= _INT_ERROR(channel);
-
-    RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
-
-    RMT.conf_ch[channel].conf1.rx_en = 1;
-    RMT_MUTEX_UNLOCK(channel);
-
-    // wait for data if requested so
-    if (waitForData && eventFlag) {
-        uint32_t flags = xEventGroupWaitBits(eventFlag, RMT_FLAGS_ALL,
-                            pdTRUE /* clear on exit */, pdFALSE /* wait for all bits */, timeout);
-        if (flags & RMT_FLAG_ERROR) {
-            return false;
-        }
-    }
-
-    return true;
+bool rmtWriteAsync(int pin, rmt_data_t *data, size_t num_rmt_symbols) {
+  return _rmtWrite(pin, data, num_rmt_symbols, false /*blocks*/, false /*looping*/, 0 /*N/A*/);
 }
 
-float rmtSetTick(rmt_obj_t* rmt, float tick)
-{
-    if (!rmt) {
-        return false;
-    }
-    /*
-     divider field span from 1 (smallest), 2, 3, ... , 0xFF, 0x00 (highest)
-     * rmt tick from 1/80M -> 12.5ns  (1x)    div_cnt = 0x01
-                              3.2 us (256x)   div_cnt = 0x00
-     * rmt tick for 1 MHz  -> 1us (1x)        div_cnt = 0x01
-                              256us (256x)    div_cnt = 0x00
-    */
-    int apb_div = _LIMIT(tick/12.5, 256);
-    int ref_div = _LIMIT(tick/1000, 256);
-
-    float apb_tick = 12.5 * apb_div;
-    float ref_tick = 1000.0 * ref_div;
-    
-    size_t channel = rmt->channel;
-
-    if (_ABS(apb_tick - tick) < _ABS(ref_tick - tick)) {
-        RMT.conf_ch[channel].conf0.div_cnt = apb_div & 0xFF;
-        RMT.conf_ch[channel].conf1.ref_always_on = 1;
-        return apb_tick;
-    } else {
-        RMT.conf_ch[channel].conf0.div_cnt = ref_div & 0xFF;
-        RMT.conf_ch[channel].conf1.ref_always_on = 0;
-        return ref_tick;
-    }
+bool rmtWriteLooping(int pin, rmt_data_t *data, size_t num_rmt_symbols) {
+  return _rmtWrite(pin, data, num_rmt_symbols, false /*blocks*/, true /*looping*/, 0 /*N/A*/);
 }
 
-rmt_obj_t* rmtInit(int pin, bool tx_not_rx, rmt_reserve_memsize_t memsize)
-{
-    int buffers = memsize;
-    rmt_obj_t* rmt;
-    size_t i;
-    size_t j;
-
-    // create common block mutex for protecting allocs from multiple threads
-    if (!g_rmt_block_lock) {
-        g_rmt_block_lock = xSemaphoreCreateMutex();
-    }
-    // lock
-    while (xSemaphoreTake(g_rmt_block_lock, portMAX_DELAY) != pdPASS) {}
-
-    for (i=0; i<MAX_CHANNELS; i++) {
-        for (j=0; j<buffers && i+j < MAX_CHANNELS; j++) {
-            // if the space is ocupied break and continue on other channel
-            if (g_rmt_objects[i+j].allocated) {
-                i += j; // continue searching from latter channel
-                break;
-            }
-        }
-        if (j == buffers) {
-            // found a space in channel descriptors
-            break;
-        }
-    }
-    if (i == MAX_CHANNELS || i+j > MAX_CHANNELS || j != buffers)  {
-        xSemaphoreGive(g_rmt_block_lock);
-        return NULL;
-    }
-    rmt = _rmtAllocate(pin, i, buffers);
-
-    xSemaphoreGive(g_rmt_block_lock);
-
-    size_t channel = i;
-
-#if !CONFIG_DISABLE_HAL_LOCKS
-    if(g_rmt_objlocks[channel] == NULL) {
-        g_rmt_objlocks[channel] = xSemaphoreCreateMutex();
-        if(g_rmt_objlocks[channel] == NULL) {
-            return NULL;
-        }
-    }
-#endif
-
-    RMT_MUTEX_LOCK(channel);
-
-    rmt->pin = pin;
-    rmt->tx_not_rx = tx_not_rx;
-    rmt->buffers =buffers;
-    rmt->channel = channel;
-    rmt->arg = NULL;
-
-    _initPin(pin, channel, tx_not_rx);
-
-    // Initialize the registers in default mode:
-    // - no carrier, filter
-    // - timebase tick of 1us
-    // - idle threshold set to 0x8000 (max pulse width + 1)
-    RMT.conf_ch[channel].conf0.div_cnt = 1;
-    RMT.conf_ch[channel].conf0.mem_size = buffers;
-    RMT.conf_ch[channel].conf0.carrier_en = 0;
-    RMT.conf_ch[channel].conf0.carrier_out_lv = 0;
-    RMT.conf_ch[channel].conf0.mem_pd = 0;
-
-    RMT.conf_ch[channel].conf0.idle_thres = 0x80;
-    RMT.conf_ch[channel].conf1.rx_en = 0;
-    RMT.conf_ch[channel].conf1.tx_conti_mode = 0;
-    RMT.conf_ch[channel].conf1.ref_cnt_rst = 0;
-    RMT.conf_ch[channel].conf1.rx_filter_en = 0;
-    RMT.conf_ch[channel].conf1.rx_filter_thres = 0;
-    RMT.conf_ch[channel].conf1.idle_out_lv = 0;     // signal level for idle
-    RMT.conf_ch[channel].conf1.idle_out_en = 1;     // enable idle
-    RMT.conf_ch[channel].conf1.ref_always_on = 0;     // base clock
-
-    RMT.apb_conf.fifo_mask = 1;
-
-    if (tx_not_rx) {
-        // RMT.conf_ch[channel].conf1.rx_en = 0;
-        RMT.conf_ch[channel].conf1.mem_owner = 0;
-        RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
-    } else {
-        // RMT.conf_ch[channel].conf1.rx_en = 1;
-        RMT.conf_ch[channel].conf1.mem_owner = 1;
-        RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
-    }
-
-    // install interrupt if at least one channel is active
-    if (!intr_handle) {
-        esp_intr_alloc(ETS_RMT_INTR_SOURCE, (int)ESP_INTR_FLAG_IRAM, _rmt_isr, NULL, &intr_handle);
-    }
-    RMT_MUTEX_UNLOCK(channel);
-
-    return rmt;
+bool rmtTransmitCompleted(int pin) {
+  rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__);
+  if (bus == NULL) {
+    return false;
+  }
+  if (!_rmtCheckDirection(pin, RMT_TX_MODE, __FUNCTION__)) {
+    return false;
+  }
+
+  bool retCode = true;
+  RMT_MUTEX_LOCK(bus);
+  retCode = (xEventGroupGetBits(bus->rmt_events) & RMT_FLAG_TX_DONE) != 0;
+  RMT_MUTEX_UNLOCK(bus);
+  return retCode;
 }
 
-/**
- * Private methods definitions
- */
-bool _rmtSendOnce(rmt_obj_t* rmt, rmt_data_t* data, size_t size, bool continuous)
-{
-    if (!rmt) {
-        return false;
-    }
-    int channel = rmt->channel;
-    RMT.apb_conf.fifo_mask = 1;
-    if (data && size>0) {
-        size_t i;
-        volatile uint32_t* rmt_mem_ptr = &(RMTMEM.chan[channel].data32[0].val);
-        for (i = 0; i < size; i++) {
-            *rmt_mem_ptr++ = data[i].val;
-        }
-        // tx end mark
-        RMTMEM.chan[channel].data32[size].val = 0;
-    }
-
-    RMT_MUTEX_LOCK(channel);
-    RMT.conf_ch[channel].conf1.tx_conti_mode = continuous;
-    RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
-    RMT.conf_ch[channel].conf1.tx_start = 1;
-    RMT_MUTEX_UNLOCK(channel);
-
-    return true;
+bool rmtRead(int pin, rmt_data_t *data, size_t *num_rmt_symbols, uint32_t timeout_ms) {
+  return _rmtRead(pin, data, num_rmt_symbols, true /* blocking */, timeout_ms);
 }
 
-
-static rmt_obj_t* _rmtAllocate(int pin, int from, int size)
-{
-    size_t i;
-    // setup how many buffers shall we use
-    g_rmt_objects[from].buffers = size;
-
-    for (i=0; i<size; i++) {
-        // mark the block of channels as used
-        g_rmt_objects[i+from].allocated = true;
-    }
-    return &(g_rmt_objects[from]);
+bool rmtReadAsync(int pin, rmt_data_t *data, size_t *num_rmt_symbols) {
+  return _rmtRead(pin, data, num_rmt_symbols, false /* non-blocking */, 0 /* N/A */);
 }
 
-
-static void _initPin(int pin, int channel, bool tx_not_rx) 
-{
-    if (!periph_enabled) {
-        periph_enabled = true;
-        periph_module_enable( PERIPH_RMT_MODULE );
-    }
-    if (tx_not_rx) {
-        pinMode(pin, OUTPUT);
-        pinMatrixOutAttach(pin, RMT_SIG_OUT0_IDX + channel, 0, 0);
-    } else {
-        pinMode(pin, INPUT);
-        pinMatrixInAttach(pin, RMT_SIG_IN0_IDX + channel, 0);
-
-    }
+bool rmtReceiveCompleted(int pin) {
+  rmt_bus_handle_t bus = _rmtGetBus(pin, __FUNCTION__);
+  if (bus == NULL) {
+    return false;
+  }
+  if (!_rmtCheckDirection(pin, RMT_RX_MODE, __FUNCTION__)) {
+    return false;
+  }
+
+  bool retCode = true;
+  RMT_MUTEX_LOCK(bus);
+  retCode = (xEventGroupGetBits(bus->rmt_events) & RMT_FLAG_RX_DONE) != 0;
+  RMT_MUTEX_UNLOCK(bus);
+  return retCode;
 }
 
+bool rmtInit(int pin, rmt_ch_dir_t channel_direction, rmt_reserve_memsize_t mem_size, uint32_t frequency_Hz) {
+  log_v(
+    "GPIO %d - %s - MemSize[%d] - Freq=%dHz", pin, channel_direction == RMT_RX_MODE ? "RX MODE" : "TX MODE", mem_size * RMT_SYMBOLS_PER_CHANNEL_BLOCK,
+    frequency_Hz
+  );
+
+  // create common block mutex for protecting allocs from multiple threads allocating RMT channels
+  if (!g_rmt_block_lock) {
+    g_rmt_block_lock = xSemaphoreCreateMutex();
+    if (g_rmt_block_lock == NULL) {
+      log_e("GPIO %d - Failed creating RMT Mutex.", pin);
+      return false;
+    }
+  }
+
+  // check if the RMT peripheral is already initialized with the same parameters
+  rmt_bus_handle_t bus = NULL;
+  peripheral_bus_type_t rmt_bus_type = perimanGetPinBusType(pin);
+  if (rmt_bus_type == ESP32_BUS_TYPE_RMT_TX || rmt_bus_type == ESP32_BUS_TYPE_RMT_RX) {
+    rmt_ch_dir_t bus_rmt_dir = rmt_bus_type == ESP32_BUS_TYPE_RMT_TX ? RMT_TX_MODE : RMT_RX_MODE;
+    bus = (rmt_bus_handle_t)perimanGetPinBus(pin, rmt_bus_type);
+    if (bus->frequency_Hz == frequency_Hz && bus_rmt_dir == channel_direction && bus->mem_size == mem_size) {
+      return true;  // already initialized with the same parameters
+    }
+  }
+
+  // set Peripheral Manager deInit Callback
+  perimanSetBusDeinit(ESP32_BUS_TYPE_RMT_TX, _rmtDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_RMT_RX, _rmtDetachBus);
+
+  // check is pin is valid and in the right direction
+  if ((channel_direction == RMT_TX_MODE && !GPIO_IS_VALID_OUTPUT_GPIO(pin)) || (!GPIO_IS_VALID_GPIO(pin))) {
+    log_e("GPIO %d is not valid or can't be used for output in TX mode.", pin);
+    return false;
+  }
+
+  // validate the RMT ticks by the requested frequency
+  // Based on 80Mhz using a divider of 8 bits (calculated as 1..256)
+  if (frequency_Hz > 80000000 || frequency_Hz < 312500) {
+    log_e("GPIO %d - Bad RMT frequency resolution. Must be between 312.5KHz to 80MHz.", pin);
+    return false;
+  }
+
+  // Try to detach any (Tx|Rx|Whatever) previous bus or just keep it as not attached
+  if (!perimanClearPinBus(pin)) {
+    log_w("GPIO %d - Can't detach previous peripheral.", pin);
+    return false;
+  }
+
+  // lock it
+  while (xSemaphoreTake(g_rmt_block_lock, portMAX_DELAY) != pdPASS) {}
+
+  // allocate the rmt bus object and sets all fields to NULL
+  bus = (rmt_bus_handle_t)heap_caps_calloc(1, sizeof(struct rmt_obj_s), MALLOC_CAP_DEFAULT);
+  if (bus == NULL) {
+    log_e("GPIO %d - Bus Memory allocation fault.", pin);
+    goto Err;
+  }
+
+  // store the RMT Freq and mem_size to check Initialization, Filter and Idle valid values in the RMT API
+  bus->frequency_Hz = frequency_Hz;
+  bus->mem_size = mem_size;
+  // pulses with width smaller than min_ns will be ignored (as a glitch)
+  //bus->signal_range_min_ns = 0; // disabled  --> not necessary CALLOC set all to ZERO.
+  // RMT stops reading if the input stays idle for longer than max_ns
+  bus->signal_range_max_ns = (1000000000 / frequency_Hz) * RMT_LL_MAX_IDLE_VALUE;  // maximum possible
+  // creates the event group to control read_done and write_done
+  bus->rmt_events = xEventGroupCreate();
+  if (bus->rmt_events == NULL) {
+    log_e("GPIO %d - RMT Group Event allocation fault.", pin);
+    goto Err;
+  }
+
+  // Starting with Receive|Transmit DONE bits set, for allowing a new request from user
+  xEventGroupSetBits(bus->rmt_events, RMT_FLAG_RX_DONE | RMT_FLAG_TX_DONE);
+
+  // channel particular configuration
+  if (channel_direction == RMT_TX_MODE) {
+    // TX Channel
+    rmt_tx_channel_config_t tx_cfg;
+    memset((void *)&tx_cfg, 0, sizeof(rmt_tx_channel_config_t));
+    tx_cfg.gpio_num = pin;
+    // CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F80M for C6 -- CLK_XTAL for H2
+    tx_cfg.clk_src = RMT_CLK_SRC_DEFAULT;
+    tx_cfg.resolution_hz = frequency_Hz;
+    tx_cfg.mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL * mem_size;
+    tx_cfg.trans_queue_depth = 10;  // maximum allowed
+    tx_cfg.flags.invert_out = 0;
+    tx_cfg.flags.with_dma = 0;
+    tx_cfg.flags.io_loop_back = 0;
+    tx_cfg.flags.io_od_mode = 0;
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 2)
+    tx_cfg.intr_priority = 0;
+#endif
 
-static void IRAM_ATTR _rmt_isr(void* arg)
-{
-    int intr_val = RMT.int_st.val;
-    size_t ch;
-    for (ch = 0; ch < MAX_CHANNELS; ch++) {
-
-        if (intr_val & _INT_RX_END(ch)) {
-            // clear the flag
-            RMT.int_clr.val = _INT_RX_END(ch);
-            RMT.int_ena.val &= ~_INT_RX_END(ch);
-
-            if ((g_rmt_objects[ch].intr_mode) & E_RX_INTR) {
-                if (g_rmt_objects[ch].events) {
-                    xEventGroupSetBits(g_rmt_objects[ch].events, RMT_FLAG_RX_DONE);
-                }
-                if (g_rmt_objects[ch].data_ptr && g_rmt_objects[ch].data_size > 0) {
-                    size_t i;
-                    uint32_t * data = g_rmt_objects[ch].data_ptr;
-                    // in case of callback, provide switching between memories
-                    if (g_rmt_objects[ch].cb) {
-                        if (g_rmt_objects[ch].tx_state & E_FIRST_HALF) {
-                            g_rmt_objects[ch].tx_state &= ~E_FIRST_HALF;
-                        } else {
-                            g_rmt_objects[ch].tx_state |= E_FIRST_HALF;
-                            data += MAX_DATA_PER_CHANNEL*(g_rmt_objects[ch].buffers);
-                        }
-                    }
-                    uint32_t *data_received = data;
-                    for (i = 0; i < g_rmt_objects[ch].data_size; i++ ) {
-                        *data++ = RMTMEM.chan[ch].data32[i].val;
-                    }
-                    if (g_rmt_objects[ch].cb) {
-                        // actually received data ptr                        
-                        (g_rmt_objects[ch].cb)(data_received, _rmt_get_mem_len(ch), g_rmt_objects[ch].arg);
-
-                        // restart the reception
-                        RMT.conf_ch[ch].conf1.mem_owner = 1;
-                        RMT.conf_ch[ch].conf1.mem_wr_rst = 1;
-                        RMT.conf_ch[ch].conf1.rx_en = 1;
-                        RMT.int_ena.val |= _INT_RX_END(ch);
-                    } else {
-                        // if not callback provide, expect only one Rx
-                        g_rmt_objects[ch].intr_mode &= ~E_RX_INTR;
-                    }
-                }
-            } else {
-                // Report error and disable Rx interrupt
-                log_e("Unexpected Rx interrupt!\n");  // TODO: eplace messages with log_X
-                RMT.int_ena.val &= ~_INT_RX_END(ch);
-            }
-
-
-        }
-
-        if (intr_val & _INT_ERROR(ch)) {
-            // clear the flag
-            RMT.int_clr.val = _INT_ERROR(ch);
-            RMT.int_ena.val &= ~_INT_ERROR(ch);
-            // report error 
-            log_e("RMT Error %d!\n", ch);
-            if (g_rmt_objects[ch].events) {
-                xEventGroupSetBits(g_rmt_objects[ch].events, RMT_FLAG_ERROR);
-            }
-            // reset memory
-            RMT.conf_ch[ch].conf1.mem_rd_rst = 1;
-            RMT.conf_ch[ch].conf1.mem_rd_rst = 0;
-            RMT.conf_ch[ch].conf1.mem_wr_rst = 1;
-            RMT.conf_ch[ch].conf1.mem_wr_rst = 0;
-        }
-
-        if (intr_val & _INT_TX_END(ch)) {
-
-            RMT.int_clr.val = _INT_TX_END(ch);
-            _rmt_tx_mem_second(ch);
-        }
-
-        if (intr_val & _INT_THR_EVNT(ch)) {
-            // clear the flag
-            RMT.int_clr.val = _INT_THR_EVNT(ch);
-
-            // initial setup of continuous mode
-            if (g_rmt_objects[ch].tx_state & E_SET_CONTI) {
-                RMT.conf_ch[ch].conf1.tx_conti_mode = 1;
-                g_rmt_objects[ch].intr_mode &= ~E_SET_CONTI;
-            }
-            _rmt_tx_mem_first(ch);
-        }
+    if (rmt_new_tx_channel(&tx_cfg, &bus->rmt_channel_h) != ESP_OK) {
+      log_e("GPIO %d - RMT TX Initialization error.", pin);
+      goto Err;
+    }
+
+    // set TX Callback
+    rmt_tx_event_callbacks_t cbs = {.on_trans_done = _rmt_tx_done_callback};
+    if (ESP_OK != rmt_tx_register_event_callbacks(bus->rmt_channel_h, &cbs, bus)) {
+      log_e("GPIO %d RMT - Error registering TX Callback.", pin);
+      goto Err;
+    }
+
+  } else {
+    // RX Channel
+    rmt_rx_channel_config_t rx_cfg;
+    memset((void *)&rx_cfg, 0, sizeof(rmt_rx_channel_config_t));
+    rx_cfg.gpio_num = pin;
+    // CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F80M for C6 -- CLK_XTAL for H2
+    rx_cfg.clk_src = RMT_CLK_SRC_DEFAULT;
+    rx_cfg.resolution_hz = frequency_Hz;
+    rx_cfg.mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL * mem_size;
+    rx_cfg.flags.invert_in = 0;
+    rx_cfg.flags.with_dma = 0;
+    rx_cfg.flags.io_loop_back = 0;
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 1, 2)
+    rx_cfg.intr_priority = 0;
+#endif
+    // try to allocate the RMT Channel
+    if (ESP_OK != rmt_new_rx_channel(&rx_cfg, &bus->rmt_channel_h)) {
+      log_e("GPIO %d RMT - RX Initialization error.", pin);
+      goto Err;
     }
-}
-
-static void IRAM_ATTR _rmt_tx_mem_second(uint8_t ch)
-{
-    DEBUG_INTERRUPT_START(4)
-    uint32_t* data = g_rmt_objects[ch].data_ptr;
-    int half_tx_nr = MAX_DATA_PER_ITTERATION/2;
-    int i;
-
-    RMT.tx_lim_ch[ch].limit = half_tx_nr+2;
-    RMT.int_clr.val = _INT_THR_EVNT(ch);
-    RMT.int_ena.val |= _INT_THR_EVNT(ch);
-
-    g_rmt_objects[ch].tx_state |= E_FIRST_HALF;
-
-    if (data) {
-        int remaining_size = g_rmt_objects[ch].data_size;
-        // will the remaining data occupy the entire halfbuffer
-        if (remaining_size > half_tx_nr) {
-            for (i = 0; i < half_tx_nr; i++) {
-                RMTMEM.chan[ch].data32[half_tx_nr+i].val = data[i];
-            }
-            g_rmt_objects[ch].data_size -= half_tx_nr;
-            g_rmt_objects[ch].data_ptr += half_tx_nr;
-        } else {
-            for (i = 0; i < half_tx_nr; i++) {
-                if (i < remaining_size) {
-                    RMTMEM.chan[ch].data32[half_tx_nr+i].val = data[i];
-                } else {
-                    RMTMEM.chan[ch].data32[half_tx_nr+i].val = 0x000F000F;
-                }
-            }
-            g_rmt_objects[ch].data_ptr = NULL;
 
-        }
-    } else if   ((!(g_rmt_objects[ch].tx_state & E_LAST_DATA)) &&
-                 (!(g_rmt_objects[ch].tx_state & E_END_TRANS))) {
-        for (i = 0; i < half_tx_nr; i++) {
-            RMTMEM.chan[ch].data32[half_tx_nr+i].val = 0x000F000F;
-        }
-        RMTMEM.chan[ch].data32[half_tx_nr+i].val = 0;
-        g_rmt_objects[ch].tx_state |= E_LAST_DATA;
-        RMT.conf_ch[ch].conf1.tx_conti_mode = 0;
-    } else {
-        log_d("RMT Tx finished %d!\n", ch);
-        RMT.conf_ch[ch].conf1.tx_conti_mode = 0;
-        RMT.int_ena.val &= ~_INT_TX_END(ch);
-        RMT.int_ena.val &= ~_INT_THR_EVNT(ch);
-        g_rmt_objects[ch].intr_mode = E_NO_INTR;
-        g_rmt_objects[ch].tx_state = E_INACTIVE;
+    // set RX Callback
+    rmt_rx_event_callbacks_t cbs = {.on_recv_done = _rmt_rx_done_callback};
+    if (ESP_OK != rmt_rx_register_event_callbacks(bus->rmt_channel_h, &cbs, bus)) {
+      log_e("GPIO %d RMT - Error registering RX Callback.", pin);
+      goto Err;
     }
-    DEBUG_INTERRUPT_END(4);
-}
+  }
 
-static void IRAM_ATTR _rmt_tx_mem_first(uint8_t ch)
-{
-    DEBUG_INTERRUPT_START(2);
-    uint32_t* data = g_rmt_objects[ch].data_ptr;
-    int half_tx_nr = MAX_DATA_PER_ITTERATION/2;
-    int i;
-    RMT.int_ena.val &= ~_INT_THR_EVNT(ch);
-    RMT.tx_lim_ch[ch].limit = 0;
-
-    if (data) {
-        int remaining_size = g_rmt_objects[ch].data_size;
-
-        // will the remaining data occupy the entire halfbuffer
-        if (remaining_size > half_tx_nr) {
-            RMTMEM.chan[ch].data32[0].val = data[0] - 1;
-            for (i = 1; i < half_tx_nr; i++) {
-                RMTMEM.chan[ch].data32[i].val = data[i];
-            }
-            g_rmt_objects[ch].tx_state &= ~E_FIRST_HALF;
-            // turn off the treshold interrupt
-            RMT.int_ena.val &= ~_INT_THR_EVNT(ch);
-            RMT.tx_lim_ch[ch].limit = 0;
-            g_rmt_objects[ch].data_size -= half_tx_nr;
-            g_rmt_objects[ch].data_ptr += half_tx_nr;
-        } else {
-            RMTMEM.chan[ch].data32[0].val = data[0] - 1;
-            for (i = 1; i < half_tx_nr; i++) {
-                if (i < remaining_size) {
-                    RMTMEM.chan[ch].data32[i].val = data[i];
-                } else {
-                    RMTMEM.chan[ch].data32[i].val = 0x000F000F;
-                }
-            }
-
-            g_rmt_objects[ch].tx_state &= ~E_FIRST_HALF;
-            g_rmt_objects[ch].data_ptr = NULL;
-        }
-    } else { 
-        for (i = 0; i < half_tx_nr; i++) {
-            RMTMEM.chan[ch].data32[i].val = 0x000F000F;
-        }
-        RMTMEM.chan[ch].data32[i].val = 0;
+  // allocate memory for the RMT Copy encoder
+  rmt_copy_encoder_config_t copy_encoder_config;
+  memset((void *)&copy_encoder_config, 0, sizeof(rmt_copy_encoder_config_t));
+  if (rmt_new_copy_encoder(&copy_encoder_config, &bus->rmt_copy_encoder_h) != ESP_OK) {
+    log_e("GPIO %d - RMT Encoder Memory Allocation error.", pin);
+    goto Err;
+  }
 
-        g_rmt_objects[ch].tx_state &= ~E_FIRST_HALF;
-        RMT.tx_lim_ch[ch].limit = 0;
-        g_rmt_objects[ch].tx_state |= E_LAST_DATA;
-        RMT.conf_ch[ch].conf1.tx_conti_mode = 0;
-    }
-    DEBUG_INTERRUPT_END(2);
-}
+  // create each channel Mutex for multi thread operations
+#if !CONFIG_DISABLE_HAL_LOCKS
+  bus->g_rmt_objlocks = xSemaphoreCreateMutex();
+  if (bus->g_rmt_objlocks == NULL) {
+    log_e("GPIO %d - Failed creating RMT Channel Mutex.", pin);
+    goto Err;
+  }
+#endif
 
-static int IRAM_ATTR _rmt_get_mem_len(uint8_t channel)
-{
-    int block_num = RMT.conf_ch[channel].conf0.mem_size;
-    int item_block_len = block_num * 64;
-    volatile rmt_item32_t* data = RMTMEM.chan[channel].data32;
-    int idx;
-    for(idx = 0; idx < item_block_len; idx++) {
-        if(data[idx].duration0 == 0) {
-            return idx;
-        } else if(data[idx].duration1 == 0) {
-            return idx + 1;
-        }
-    }
-    return idx;
+  rmt_enable(bus->rmt_channel_h);  // starts/enables the channel
+
+  // Finally, allocate Peripheral Manager RMT bus and associate it to its GPIO
+  peripheral_bus_type_t pinBusType = channel_direction == RMT_TX_MODE ? ESP32_BUS_TYPE_RMT_TX : ESP32_BUS_TYPE_RMT_RX;
+  if (!perimanSetPinBus(pin, pinBusType, (void *)bus, -1, -1)) {
+    log_e("Can't allocate the GPIO %d in the Peripheral Manager.", pin);
+    goto Err;
+  }
+
+  // this delay is necessary when CPU frequency changes, but internal RMT setup is "old/wrong"
+  // The use case is related to the RMT_CPUFreq_Test example. The very first RMT Write
+  // goes in the wrong pace (frequency). The delay allows other IDF tasks to run to fix it.
+  if (loopTaskHandle != NULL) {
+    // it can only run when Arduino task has been already started.
+    delay(1);
+  }  // prevent panic when rmtInit() is executed within an C++ object constructor
+  // release the mutex
+  xSemaphoreGive(g_rmt_block_lock);
+  return true;
+
+Err:
+  // release LOCK and the RMT object
+  xSemaphoreGive(g_rmt_block_lock);
+  _rmtDetachBus((void *)bus);
+  return false;
 }
+
+#endif /* SOC_RMT_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-rmt.h b/cores/esp32/esp32-hal-rmt.h
index cce6c8c8107..c15eadfbcd1 100644
--- a/cores/esp32/esp32-hal-rmt.h
+++ b/cores/esp32/esp32-hal-rmt.h
@@ -1,4 +1,4 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2023 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,138 +15,222 @@
 #ifndef MAIN_ESP32_HAL_RMT_H_
 #define MAIN_ESP32_HAL_RMT_H_
 
+#include "soc/soc_caps.h"
+#if SOC_RMT_SUPPORTED
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-// notification flags
-#define RMT_FLAG_TX_DONE     (1)
-#define RMT_FLAG_RX_DONE     (2)
-#define RMT_FLAG_ERROR       (4)
-#define RMT_FLAGS_ALL        (RMT_FLAG_TX_DONE | RMT_FLAG_RX_DONE | RMT_FLAG_ERROR)
-
-struct rmt_obj_s;
+typedef enum {
+  RMT_RX_MODE = 0,  // false
+  RMT_TX_MODE = 1,  // true
+} rmt_ch_dir_t;
 
 typedef enum {
-    RMT_MEM_64 =  1,
-    RMT_MEM_128 = 2,
-    RMT_MEM_192 = 3,
-    RMT_MEM_256 = 4,
-    RMT_MEM_320 = 5,
-    RMT_MEM_384 = 6,
-    RMT_MEM_448 = 7,
-    RMT_MEM_512 = 8,
+  RMT_MEM_NUM_BLOCKS_1 = 1,
+  RMT_MEM_NUM_BLOCKS_2 = 2,
+#if SOC_RMT_TX_CANDIDATES_PER_GROUP > 2
+  RMT_MEM_NUM_BLOCKS_3 = 3,
+  RMT_MEM_NUM_BLOCKS_4 = 4,
+#if SOC_RMT_TX_CANDIDATES_PER_GROUP > 4
+  RMT_MEM_NUM_BLOCKS_5 = 5,
+  RMT_MEM_NUM_BLOCKS_6 = 6,
+  RMT_MEM_NUM_BLOCKS_7 = 7,
+  RMT_MEM_NUM_BLOCKS_8 = 8,
+#endif
+#endif
 } rmt_reserve_memsize_t;
 
-typedef struct rmt_obj_s rmt_obj_t;
+// Each RMT Symbols has 4 bytes
+// Total number of bytes per RMT_MEM_BLOCK is RMT_SYMBOLS_PER_CHANNEL_BLOCK * 4 bytes
+typedef union {
+  struct {
+    uint32_t duration0 : 15;
+    uint32_t level0    : 1;
+    uint32_t duration1 : 15;
+    uint32_t level1    : 1;
+  };
+  uint32_t val;
+} rmt_data_t;
+
+// Reading and Writing shall use as rmt_symbols_size this unit
+// ESP32 has 8 MEM BLOCKS in total shared with Reading and/or Writing
+// ESP32-S2 has 4 MEM BLOCKS in total shared with Reading and/or Writing
+// ESP32-S3 has 4 MEM BLOCKS for Reading and another 4 MEM BLOCKS for Writing
+// ESP32-C3 has 2 MEM BLOCKS for Reading and another 2 MEM BLOCKS for Writing
+#define RMT_SYMBOLS_PER_CHANNEL_BLOCK SOC_RMT_MEM_WORDS_PER_CHANNEL
 
-typedef void (*rmt_rx_data_cb_t)(uint32_t *data, size_t len, void *arg);
+// Used to tell rmtRead() to wait for ever until reading data from the RMT channel
+#define RMT_WAIT_FOR_EVER ((uint32_t)portMAX_DELAY)
 
-typedef struct {
-    union {
-        struct {
-            uint32_t duration0 :15;
-            uint32_t level0 :1;
-            uint32_t duration1 :15;
-            uint32_t level1 :1;
-        };
-        uint32_t val;
-    };
-} rmt_data_t;
+// Helper macro to calculate the number of RTM symbols in a array or type
+#define RMT_SYMBOLS_OF(x) (sizeof(x) / sizeof(rmt_data_t))
 
 /**
-*    Initialize the object
-*
-*/
-rmt_obj_t* rmtInit(int pin, bool tx_not_rx, rmt_reserve_memsize_t memsize);
+    Initialize the object
 
-/**
-*    Sets the clock/divider of timebase the nearest tick to the supplied value in nanoseconds
-*    return the real actual tick value in ns
+    New Parameters in Arduino Core 3: RMT tick is set in the rmtInit() function by the
+    frequency of the RMT channel. Example: 100ns tick => 10MHz, thus frequency will be 10,000,000 Hz
+    Returns <true> on execution success, <false> otherwise
 */
-float rmtSetTick(rmt_obj_t* rmt, float tick);
+bool rmtInit(int pin, rmt_ch_dir_t channel_direction, rmt_reserve_memsize_t memsize, uint32_t frequency_Hz);
 
 /**
-*    Sending data in one-go mode or continual mode
-*     (more data being send while updating buffers in interrupts)
-*
+     Sets the End of Transmission level to be set for the <pin> when the RMT transmission ends.
+     This function affects how rmtWrite(), rmtWriteAsync() or rmtWriteLooping() will set the pin after writing the data.
+     The default EOT level is LOW, in case this function isn't used before RMT Writing.
+     This level can be set for each RMT pin and can be changed between writings to the same pin.
+
+     <EOT_Level> shall be Zero (LOW) or non-zero (HIGH) value.
+     It only affects the transmission process, therefore, it doesn't affect any IDLE LEVEL before starting the RMT transmission.
+     The pre-transmission idle level can be set manually calling, for instance, digitalWrite(pin, Level).
+
+     Returns <true> when EOT has been correctly set for <pin>, <false> otherwise.
 */
-bool rmtWrite(rmt_obj_t* rmt, rmt_data_t* data, size_t size);
+bool rmtSetEOT(int pin, uint8_t EOT_Level);
 
 /**
-*    Loop data up to the reserved memsize continuously
-*
+     Sending data in Blocking Mode.
+     <rmt_symbol> is a 32 bits structure as defined by rmt_data_t type.
+     It is possible to use the macro RMT_SYMBOLS_OF(data), if data is an array of <rmt_data_t>.
+
+     Blocking mode - only returns after sending all data or by timeout.
+     If the writing operation takes longer than <timeout_ms> in milliseconds, it will end its
+     execution returning <false>.
+     Timeout can be set as undefined time by passing <RMT_WAIT_FOR_EVER> as <timeout_ms> parameter.
+     When the operation is timed out, rmtTransmitCompleted() will return <false> until the transmission
+     is finished, when rmtTransmitCompleted() will return <true>.
+
+     Returns <true> when there is no error in the write operation, <false> otherwise, including when it
+     exits by timeout.
 */
-bool rmtLoop(rmt_obj_t* rmt, rmt_data_t* data, size_t size);
+bool rmtWrite(int pin, rmt_data_t *data, size_t num_rmt_symbols, uint32_t timeout_ms);
 
 /**
-*    Initiates async receive, event flag indicates data received
-*
+     Sending data in Async Mode.
+     <rmt_symbol> is a 32 bits structure as defined by rmt_data_t type.
+     It is possible to use the macro RMT_SYMBOLS_OF(data), if <data> is an array of <rmt_data_t>
+
+     If more than one rmtWriteAsync() is executed in sequence, it will wait for the first transmission
+     to finish, resulting in a return <false> that indicates that the rmtWriteAsync() call has failed.
+     In such case, this channel will have to finish the previous transmission before starting a new one.
+
+     Non-Blocking mode - returns right after execution.
+     Returns <true> on execution success, <false> otherwise.
+
+     <bool rmtTransmitCompleted(int pin)> will return <true> when all data is sent.
 */
-bool rmtReadAsync(rmt_obj_t* rmt, rmt_data_t* data, size_t size, void* eventFlag, bool waitForData, uint32_t timeout);
+bool rmtWriteAsync(int pin, rmt_data_t *data, size_t num_rmt_symbols);
 
 /**
-*    Initiates async receive with automatic buffering
-*    and callback with data from ISR
-*
-*/
-bool rmtRead(rmt_obj_t* rmt, rmt_rx_data_cb_t cb, void * arg);
+     Writing data up to the reserved memsize, looping continuously
+     <rmt_symbol> is a 32 bits structure as defined by rmt_data_t type.
+     It is possible to use the macro RMT_SYMBOLS_OF(data), if data is an array of rmt_data_t
+
+     If *data or size_byte are NULL | Zero, it will disable the writing loop and stop transmission
 
-/***
- * Ends async receive started with rmtRead(); but does not
- * rmtDeInit().
- */
-bool rmtEnd(rmt_obj_t* rmt);
+     Non-Blocking mode - returns right after execution
+     Returns <true> on execution success, <false> otherwise
 
-/*  Additional interface */
+     <bool rmtTransmitCompleted(int pin)> will return always <true> while it is looping.
+*/
+bool rmtWriteLooping(int pin, rmt_data_t *data, size_t num_rmt_symbols);
 
 /**
-*    Start reception
-*
+     Checks if transmission is completed and the rmtChannel ready for transmitting new data.
+     To be ready for a new transmission, means that the previous transmission is completed.
+     Returns <true> when all data has been sent, <false> otherwise.
+     The data transmission information is reset when a new rmtWrite/Async function is called.
+     If rmtWrite() times out or rmtWriteAsync() is called, this function will return <false> until
+     all data is sent out.
+     rmtTranmitCompleted() will always return <true> when rmtWriteLooping() is called,
+     because it has no effect in such case.
 */
-bool rmtBeginReceive(rmt_obj_t* rmt);
+bool rmtTransmitCompleted(int pin);
 
 /**
-*    Checks if reception completes
-*
+     Initiates blocking receive. Read data will be stored in a user provided buffer <*data>
+     It will read up to <num_rmt_symbols> RMT Symbols and the value of this variable will
+     change to the effective number of symbols read.
+     <rmt_symbol> is a 32 bits structure as defined by rmt_data_t type.
+
+     If the reading operation takes longer than <timeout_ms> in milliseconds, it will end its
+     execution and the function will return <false>. In a time out scenario, <num_rmt_symbols> won't
+     change and rmtReceiveCompleted() can be used latter to check if there is data available.
+     Timeout can be set as undefined time by passing RMT_WAIT_FOR_EVER as <timeout_ms> parameter
+
+     Returns <true> when there is no error in the read operation, <false> otherwise, including when it
+     exits by timeout.
+     Returns, by value, the number of RMT Symbols read in <num_rmt_symbols> and the user buffer <data>
+     when the read operation has success within the defined <timeout_ms>. If the function times out, it
+     will read RMT data latter asynchronously, affecting <*data> and <*num_rmt_symbols>. After timeout,
+     the application can check if data is already available using <rmtReceiveCompleted(int pin)>
 */
-bool rmtReceiveCompleted(rmt_obj_t* rmt);
+bool rmtRead(int pin, rmt_data_t *data, size_t *num_rmt_symbols, uint32_t timeout_ms);
 
 /**
-*    Reads the data for particular channel
-*
+     Initiates async (non-blocking) receive. It will return immediately after execution.
+     Read data will be stored in a user provided buffer <*data>.
+     It will read up to <num_rmt_symbols> RMT Symbols and the value of this variable will
+     change to the effective number of symbols read, whenever the read is completed.
+     <rmt_symbol> is a 32 bits structure as defined by <rmt_data_t> type.
+
+     Returns <true> when there is no error in the read operation, <false> otherwise.
+     Returns asynchronously, by value, the number of RMT Symbols read, and also, it will copy
+     the RMT received data to the user buffer <data> when the read operation happens.
+     The application can check if data is already available using <rmtReceiveCompleted(int pin)>
 */
-bool rmtReadData(rmt_obj_t* rmt, uint32_t* data, size_t size);
+bool rmtReadAsync(int pin, rmt_data_t *data, size_t *num_rmt_symbols);
 
 /**
- * Setting threshold for Rx completed
- */
-bool rmtSetRxThreshold(rmt_obj_t* rmt, uint32_t value);
+     Checks if a data reception is completed and the rmtChannel has new data for processing.
+     Returns <true> when data has been received, <false> otherwise.
+     The data reception information is reset when a new rmtRead/Async function is called.
+*/
+bool rmtReceiveCompleted(int pin);
 
 /**
- * Setting carrier
- */
-bool rmtSetCarrier(rmt_obj_t* rmt, bool carrier_en, bool carrier_level, uint32_t low, uint32_t high);
+   Function used to set a threshold (in ticks) used to consider that a data reception has ended.
+   In receive mode, when no edge is detected on the input signal for longer than idle_thres_ticks
+   time, the receiving process is finished and the Data is made available by
+   the rmtRead/Async functions. Note that this time (in RMT channel frequency cycles) will also
+   define how many low/high bits are read at the end of the received data.
+   The function returns <true> if it is correctly executed, <false> otherwise.
+*/
+bool rmtSetRxMaxThreshold(int pin, uint16_t idle_thres_ticks);
 
 /**
- * Setting input filter
- */
-bool rmtSetFilter(rmt_obj_t* rmt, bool filter_en, uint32_t filter_level);
+   Parameters changed in Arduino Core 3: low and high (ticks) are now expressed in Carrier Freq in Hz and
+   duty cycle in percentage float 0.0 to 1.0 - example: 38.5KHz 33% High => 38500, 0.33
+
+   Function to set a RX demodulation carrier or TX modulation carrier
+    <carrier_en> is used to enable/disable the use of demodulation/modulation for RX/TX
+    <carrier_level> true means that the polarity level for the (de)modulation is positive
+    <frequency_Hz> is the carrier frequency used
+    <duty_percent> is a float deom 0 to 1 (0.5 means a square wave) of the carrier frequency
+   The function returns <true> if it is correctly executed, <false> otherwise.
+*/
+bool rmtSetCarrier(int pin, bool carrier_en, bool carrier_level, uint32_t frequency_Hz, float duty_percent);
 
 /**
- * Deinitialize the driver
- */
-bool rmtDeinit(rmt_obj_t *rmt);
+   Function used to filter input noise in the RX channel.
+   In receiving mode, channel will ignore any input pulse which width (high or low)
+   is smaller than <filter_pulse_ticks>
+   If <filter_pulse_ns> is Zero, it will to disable the filter.
+   The function returns <true> if it is correctly executed, <false> otherwise.
+*/
+bool rmtSetRxMinThreshold(int pin, uint8_t filter_pulse_ticks);
 
-// TODO:
-//  * uninstall interrupt when all channels are deinit
-//  * send only-conti mode with circular-buffer
-//  * put sanity checks to some macro or inlines
-//  * doxy comments
-//  * error reporting
+/**
+   Deinitializes the driver and releases all allocated memory
+   It also disables RMT for this gpio
+*/
+bool rmtDeinit(int pin);
 
 #ifdef __cplusplus
 }
 #endif
 
+#endif /* SOC_RMT_SUPPORTED */
 #endif /* MAIN_ESP32_HAL_RMT_H_ */
diff --git a/cores/esp32/esp32-hal-sigmadelta.c b/cores/esp32/esp32-hal-sigmadelta.c
index 098181c77ae..988f44103c5 100644
--- a/cores/esp32/esp32-hal-sigmadelta.c
+++ b/cores/esp32/esp32-hal-sigmadelta.c
@@ -1,115 +1,83 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
+/*
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+#include "esp32-hal-sigmadelta.h"
 
+#if SOC_SDM_SUPPORTED
 #include "esp32-hal.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/semphr.h"
-#include "rom/ets_sys.h"
-#include "esp32-hal-matrix.h"
-#include "soc/gpio_sd_reg.h"
-#include "soc/gpio_sd_struct.h"
+#include "esp32-hal-periman.h"
+#include "driver/sdm.h"
 
-
-#if CONFIG_DISABLE_HAL_LOCKS
-#define SD_MUTEX_LOCK()
-#define SD_MUTEX_UNLOCK()
-#else
-#define SD_MUTEX_LOCK()    do {} while (xSemaphoreTake(_sd_sys_lock, portMAX_DELAY) != pdPASS)
-#define SD_MUTEX_UNLOCK()  xSemaphoreGive(_sd_sys_lock)
-xSemaphoreHandle _sd_sys_lock;
-#endif
-
-static void _on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb){
-    if(old_apb == new_apb){
-        return;
-    }
-    uint32_t iarg = (uint32_t)arg;
-    uint8_t channel = iarg;
-    if(ev_type == APB_BEFORE_CHANGE){
-        SIGMADELTA.cg.clk_en = 0;
-    } else {
-        old_apb /= 1000000;
-        new_apb /= 1000000;
-        SD_MUTEX_LOCK();
-        uint32_t old_prescale = SIGMADELTA.channel[channel].prescale + 1;
-        SIGMADELTA.channel[channel].prescale = ((new_apb * old_prescale) / old_apb) - 1;
-        SIGMADELTA.cg.clk_en = 0;
-        SIGMADELTA.cg.clk_en = 1;
-        SD_MUTEX_UNLOCK();
-    }
+static bool sigmaDeltaDetachBus(void *bus) {
+  esp_err_t err = sdm_channel_disable((sdm_channel_handle_t)bus);
+  if (err != ESP_OK) {
+    log_w("sdm_channel_disable failed with error: %d", err);
+  }
+  err = sdm_del_channel((sdm_channel_handle_t)bus);
+  if (err != ESP_OK) {
+    log_e("sdm_del_channel failed with error: %d", err);
+    return false;
+  }
+  return true;
 }
 
-uint32_t sigmaDeltaSetup(uint8_t channel, uint32_t freq) //chan 0-7 freq 1220-312500
+bool sigmaDeltaAttach(uint8_t pin, uint32_t freq)  //freq 1220-312500
 {
-    if(channel > 7) {
-        return 0;
-    }
-#if !CONFIG_DISABLE_HAL_LOCKS
-    static bool tHasStarted = false;
-    if(!tHasStarted) {
-        tHasStarted = true;
-        _sd_sys_lock = xSemaphoreCreateMutex();
-    }
-#endif
-    uint32_t apb_freq = getApbFrequency();
-    uint32_t prescale = (apb_freq/(freq*256)) - 1;
-    if(prescale > 0xFF) {
-        prescale = 0xFF;
-    }
-    SD_MUTEX_LOCK();
-    SIGMADELTA.channel[channel].prescale = prescale;
-    SIGMADELTA.cg.clk_en = 0;
-    SIGMADELTA.cg.clk_en = 1;
-    SD_MUTEX_UNLOCK();
-    uint32_t iarg = channel;
-    addApbChangeCallback((void*)iarg, _on_apb_change);
-    return apb_freq/((prescale + 1) * 256);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_SIGMADELTA, sigmaDeltaDetachBus);
+  sdm_channel_handle_t bus = NULL;
+  // pin may be previously attached to other peripheral -> detach it.
+  // if attached to sigmaDelta, detach it and set the new frequency
+  if (perimanGetPinBusType(pin) != ESP32_BUS_TYPE_INIT && !perimanClearPinBus(pin)) {
+    log_e("Pin %u could not be detached.", pin);
+    return false;
+  }
+  sdm_config_t config = {.gpio_num = (int)pin, .clk_src = SDM_CLK_SRC_DEFAULT, .sample_rate_hz = freq, .flags = {.invert_out = 0, .io_loop_back = 0}};
+  esp_err_t err = sdm_new_channel(&config, &bus);
+  if (err != ESP_OK) {
+    log_e("sdm_new_channel failed with error: %d", err);
+    return false;
+  }
+  err = sdm_channel_enable(bus);
+  if (err != ESP_OK) {
+    sigmaDeltaDetachBus((void *)bus);
+    log_e("sdm_channel_enable failed with error: %d", err);
+    return false;
+  }
+  if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_SIGMADELTA, (void *)bus, -1, -1)) {
+    sigmaDeltaDetachBus((void *)bus);
+    return false;
+  }
+  return true;
 }
 
-void sigmaDeltaWrite(uint8_t channel, uint8_t duty) //chan 0-7 duty 8 bit
+bool sigmaDeltaWrite(uint8_t pin, uint8_t duty)  //chan 0-x according to SOC duty 8 bit
 {
-    if(channel > 7) {
-        return;
+  sdm_channel_handle_t bus = (sdm_channel_handle_t)perimanGetPinBus(pin, ESP32_BUS_TYPE_SIGMADELTA);
+  if (bus != NULL) {
+    int8_t d = duty - 128;
+    esp_err_t err = sdm_channel_set_duty(bus, d);
+    if (err != ESP_OK) {
+      log_e("sdm_channel_set_duty failed with error: %d", err);
+      return false;
     }
-    duty -= 128;
-    SD_MUTEX_LOCK();
-    SIGMADELTA.channel[channel].duty = duty;
-    SD_MUTEX_UNLOCK();
+    return true;
+  } else {
+    log_e("pin %u is not attached to SigmaDelta", pin);
+  }
+  return false;
 }
 
-uint8_t sigmaDeltaRead(uint8_t channel) //chan 0-7
-{
-    if(channel > 7) {
-        return 0;
-    }
-    SD_MUTEX_LOCK();
-    uint8_t duty = SIGMADELTA.channel[channel].duty + 128;
-    SD_MUTEX_UNLOCK();
-    return duty;
-}
-
-void sigmaDeltaAttachPin(uint8_t pin, uint8_t channel) //channel 0-7
-{
-    if(channel > 7) {
-        return;
-    }
-    pinMode(pin, OUTPUT);
-    pinMatrixOutAttach(pin, GPIO_SD0_OUT_IDX + channel, false, false);
-}
-
-void sigmaDeltaDetachPin(uint8_t pin)
-{
-    pinMatrixOutDetach(pin, false, false);
+bool sigmaDeltaDetach(uint8_t pin) {
+  void *bus = perimanGetPinBus(pin, ESP32_BUS_TYPE_SIGMADELTA);
+  if (bus != NULL) {
+    // will call sigmaDeltaDetachBus
+    return perimanClearPinBus(pin);
+  } else {
+    log_e("pin %u is not attached to SigmaDelta", pin);
+  }
+  return false;
 }
+#endif
diff --git a/cores/esp32/esp32-hal-sigmadelta.h b/cores/esp32/esp32-hal-sigmadelta.h
index 95bcb17c22c..3ae5dd7be95 100644
--- a/cores/esp32/esp32-hal-sigmadelta.h
+++ b/cores/esp32/esp32-hal-sigmadelta.h
@@ -1,19 +1,13 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
+/*
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+#pragma once
 
-#ifndef _ESP32_HAL_SD_H_
-#define _ESP32_HAL_SD_H_
+#include "soc/soc_caps.h"
+#if SOC_SDM_SUPPORTED
 
 #ifdef __cplusplus
 extern "C" {
@@ -22,16 +16,13 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 
-//channel 0-7 freq 1220-312500 duty 0-255
-uint32_t    sigmaDeltaSetup(uint8_t channel, uint32_t freq);
-void        sigmaDeltaWrite(uint8_t channel, uint8_t duty);
-uint8_t     sigmaDeltaRead(uint8_t channel);
-void        sigmaDeltaAttachPin(uint8_t pin, uint8_t channel);
-void        sigmaDeltaDetachPin(uint8_t pin);
-
+//freq 1220-312500 duty 0-255
+bool sigmaDeltaAttach(uint8_t pin, uint32_t freq);
+bool sigmaDeltaWrite(uint8_t pin, uint8_t duty);
+bool sigmaDeltaDetach(uint8_t pin);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* _ESP32_HAL_SD_H_ */
+#endif /* SOC_SDM_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-spi.c b/cores/esp32/esp32-hal-spi.c
index b3b703ccc2a..80928309670 100644
--- a/cores/esp32/esp32-hal-spi.c
+++ b/cores/esp32/esp32-hal-spi.c
@@ -13,1083 +13,1607 @@
 // limitations under the License.
 
 #include "esp32-hal-spi.h"
+
+#if SOC_GPSPI_SUPPORTED
 #include "esp32-hal.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "freertos/semphr.h"
-#include "rom/ets_sys.h"
 #include "esp_attr.h"
-#include "esp_intr.h"
-#include "rom/gpio.h"
 #include "soc/spi_reg.h"
 #include "soc/spi_struct.h"
+#include "soc/periph_defs.h"
 #include "soc/io_mux_reg.h"
 #include "soc/gpio_sig_map.h"
-#include "soc/dport_reg.h"
 #include "soc/rtc.h"
+#include "hal/clk_gate_ll.h"
+#include "esp32-hal-periman.h"
+#include "esp_private/periph_ctrl.h"
 
-#define SPI_CLK_IDX(p)  ((p==0)?SPICLK_OUT_IDX:((p==1)?SPICLK_OUT_IDX:((p==2)?HSPICLK_OUT_IDX:((p==3)?VSPICLK_OUT_IDX:0))))
-#define SPI_MISO_IDX(p) ((p==0)?SPIQ_OUT_IDX:((p==1)?SPIQ_OUT_IDX:((p==2)?HSPIQ_OUT_IDX:((p==3)?VSPIQ_OUT_IDX:0))))
-#define SPI_MOSI_IDX(p) ((p==0)?SPID_IN_IDX:((p==1)?SPID_IN_IDX:((p==2)?HSPID_IN_IDX:((p==3)?VSPID_IN_IDX:0))))
+#include "esp_system.h"
+#include "esp_intr_alloc.h"
 
-#define SPI_SPI_SS_IDX(n)   ((n==0)?SPICS0_OUT_IDX:((n==1)?SPICS1_OUT_IDX:((n==2)?SPICS2_OUT_IDX:SPICS0_OUT_IDX)))
-#define SPI_HSPI_SS_IDX(n)   ((n==0)?HSPICS0_OUT_IDX:((n==1)?HSPICS1_OUT_IDX:((n==2)?HSPICS2_OUT_IDX:HSPICS0_OUT_IDX)))
-#define SPI_VSPI_SS_IDX(n)   ((n==0)?VSPICS0_OUT_IDX:((n==1)?VSPICS1_OUT_IDX:((n==2)?VSPICS2_OUT_IDX:VSPICS0_OUT_IDX)))
-#define SPI_SS_IDX(p, n)   ((p==0)?SPI_SPI_SS_IDX(n):((p==1)?SPI_SPI_SS_IDX(n):((p==2)?SPI_HSPI_SS_IDX(n):((p==3)?SPI_VSPI_SS_IDX(n):0))))
-
-#define SPI_INUM(u)        (2)
-#define SPI_INTR_SOURCE(u) ((u==0)?ETS_SPI0_INTR_SOURCE:((u==1)?ETS_SPI1_INTR_SOURCE:((u==2)?ETS_SPI2_INTR_SOURCE:((p==3)?ETS_SPI3_INTR_SOURCE:0))))
+#if CONFIG_IDF_TARGET_ESP32  // ESP32/PICO-D4
+#include "soc/dport_reg.h"
+#include "esp32/rom/ets_sys.h"
+#include "esp32/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "soc/dport_reg.h"
+#include "esp32s2/rom/ets_sys.h"
+#include "esp32s2/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "soc/dport_reg.h"
+#include "esp32s3/rom/ets_sys.h"
+#include "esp32s3/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/ets_sys.h"
+#include "esp32c2/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/ets_sys.h"
+#include "esp32c3/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/ets_sys.h"
+#include "esp32c6/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/ets_sys.h"
+#include "esp32h2/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/ets_sys.h"
+#include "esp32p4/rom/gpio.h"
+#else
+#error Target CONFIG_IDF_TARGET is not supported
+#endif
 
 struct spi_struct_t {
-    spi_dev_t * dev;
+  volatile spi_dev_t *dev;
 #if !CONFIG_DISABLE_HAL_LOCKS
-    xSemaphoreHandle lock;
+  SemaphoreHandle_t lock;
 #endif
-    uint8_t num;
+  uint8_t num;
+  int8_t sck;
+  int8_t miso;
+  int8_t mosi;
+  int8_t ss;
 };
 
+#if CONFIG_IDF_TARGET_ESP32S2
+// ESP32S2
+#define SPI_COUNT (3)
+
+#define SPI_CLK_IDX(p)  ((p == 0) ? SPICLK_OUT_MUX_IDX : ((p == 1) ? FSPICLK_OUT_MUX_IDX : ((p == 2) ? SPI3_CLK_OUT_MUX_IDX : 0)))
+#define SPI_MISO_IDX(p) ((p == 0) ? SPIQ_OUT_IDX : ((p == 1) ? FSPIQ_OUT_IDX : ((p == 2) ? SPI3_Q_OUT_IDX : 0)))
+#define SPI_MOSI_IDX(p) ((p == 0) ? SPID_IN_IDX : ((p == 1) ? FSPID_IN_IDX : ((p == 2) ? SPI3_D_IN_IDX : 0)))
+
+#define SPI_SPI_SS_IDX(n)  ((n == 0) ? SPICS0_OUT_IDX : ((n == 1) ? SPICS1_OUT_IDX : 0))
+#define SPI_HSPI_SS_IDX(n) ((n == 0) ? SPI3_CS0_OUT_IDX : ((n == 1) ? SPI3_CS1_OUT_IDX : ((n == 2) ? SPI3_CS2_OUT_IDX : SPI3_CS0_OUT_IDX)))
+#define SPI_FSPI_SS_IDX(n) ((n == 0) ? FSPICS0_OUT_IDX : ((n == 1) ? FSPICS1_OUT_IDX : ((n == 2) ? FSPICS2_OUT_IDX : FSPICS0_OUT_IDX)))
+#define SPI_SS_IDX(p, n)   ((p == 0) ? SPI_SPI_SS_IDX(n) : ((p == 1) ? SPI_SPI_SS_IDX(n) : ((p == 2) ? SPI_HSPI_SS_IDX(n) : 0)))
+
+#elif CONFIG_IDF_TARGET_ESP32S3
+// ESP32S3
+#define SPI_COUNT (2)
+
+#define SPI_CLK_IDX(p)  ((p == 0) ? FSPICLK_OUT_IDX : ((p == 1) ? SPI3_CLK_OUT_IDX : 0))
+#define SPI_MISO_IDX(p) ((p == 0) ? FSPIQ_OUT_IDX : ((p == 1) ? SPI3_Q_OUT_IDX : 0))
+#define SPI_MOSI_IDX(p) ((p == 0) ? FSPID_IN_IDX : ((p == 1) ? SPI3_D_IN_IDX : 0))
+
+#define SPI_HSPI_SS_IDX(n) ((n == 0) ? SPI3_CS0_OUT_IDX : ((n == 1) ? SPI3_CS1_OUT_IDX : 0))
+#define SPI_FSPI_SS_IDX(n) ((n == 0) ? FSPICS0_OUT_IDX : ((n == 1) ? FSPICS1_OUT_IDX : 0))
+#define SPI_SS_IDX(p, n)   ((p == 0) ? SPI_FSPI_SS_IDX(n) : ((p == 1) ? SPI_HSPI_SS_IDX(n) : 0))
+
+#elif CONFIG_IDF_TARGET_ESP32P4
+// ESP32P4
+#define SPI_COUNT (2)  // SPI2 and SPI3. SPI0 and SPI1 are reserved for flash and PSRAM
+
+#define SPI_CLK_IDX(p)  ((p == 0) ? SPI2_CK_PAD_OUT_IDX : ((p == 1) ? SPI3_CK_PAD_OUT_IDX : 0))
+#define SPI_MISO_IDX(p) ((p == 0) ? SPI2_Q_PAD_OUT_IDX : ((p == 1) ? SPI3_QO_PAD_OUT_IDX : 0))
+#define SPI_MOSI_IDX(p) ((p == 0) ? SPI2_D_PAD_IN_IDX : ((p == 1) ? SPI3_D_PAD_IN_IDX : 0))
+
+#define SPI_HSPI_SS_IDX(n) ((n == 0) ? SPI3_CS_PAD_OUT_IDX : ((n == 1) ? SPI3_CS1_PAD_OUT_IDX : ((n == 2) ? SPI3_CS2_PAD_OUT_IDX : 0)))
+
+#define SPI_FSPI_SS_IDX(n)                                 \
+  ((n == 0) ? SPI2_CS_PAD_OUT_IDX                          \
+            : ((n == 1) ? SPI2_CS1_PAD_OUT_IDX             \
+                        : ((n == 2) ? SPI2_CS2_PAD_OUT_IDX \
+                                    : ((n == 3) ? SPI2_CS3_PAD_OUT_IDX : ((n == 4) ? SPI2_CS4_PAD_OUT_IDX : ((n == 5) ? SPI2_CS5_PAD_OUT_IDX : 0))))))
+
+#define SPI_SS_IDX(p, n) ((p == 0) ? SPI_FSPI_SS_IDX(n) : ((p == 1) ? SPI_HSPI_SS_IDX(n) : 0))
+
+#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+// ESP32C3
+#define SPI_COUNT (1)
+
+#define SPI_CLK_IDX(p)  FSPICLK_OUT_IDX
+#define SPI_MISO_IDX(p) FSPIQ_OUT_IDX
+#define SPI_MOSI_IDX(p) FSPID_IN_IDX
+
+#define SPI_SPI_SS_IDX(n) ((n == 0) ? FSPICS0_OUT_IDX : ((n == 1) ? FSPICS1_OUT_IDX : ((n == 2) ? FSPICS2_OUT_IDX : FSPICS0_OUT_IDX)))
+#define SPI_SS_IDX(p, n)  SPI_SPI_SS_IDX(n)
+
+#else
+// ESP32
+#define SPI_COUNT (4)
+
+#define SPI_CLK_IDX(p)  ((p == 0) ? SPICLK_OUT_IDX : ((p == 1) ? SPICLK_OUT_IDX : ((p == 2) ? HSPICLK_OUT_IDX : ((p == 3) ? VSPICLK_OUT_IDX : 0))))
+#define SPI_MISO_IDX(p) ((p == 0) ? SPIQ_OUT_IDX : ((p == 1) ? SPIQ_OUT_IDX : ((p == 2) ? HSPIQ_OUT_IDX : ((p == 3) ? VSPIQ_OUT_IDX : 0))))
+#define SPI_MOSI_IDX(p) ((p == 0) ? SPID_IN_IDX : ((p == 1) ? SPID_IN_IDX : ((p == 2) ? HSPID_IN_IDX : ((p == 3) ? VSPID_IN_IDX : 0))))
+
+#define SPI_SPI_SS_IDX(n)  ((n == 0) ? SPICS0_OUT_IDX : ((n == 1) ? SPICS1_OUT_IDX : ((n == 2) ? SPICS2_OUT_IDX : SPICS0_OUT_IDX)))
+#define SPI_HSPI_SS_IDX(n) ((n == 0) ? HSPICS0_OUT_IDX : ((n == 1) ? HSPICS1_OUT_IDX : ((n == 2) ? HSPICS2_OUT_IDX : HSPICS0_OUT_IDX)))
+#define SPI_VSPI_SS_IDX(n) ((n == 0) ? VSPICS0_OUT_IDX : ((n == 1) ? VSPICS1_OUT_IDX : ((n == 2) ? VSPICS2_OUT_IDX : VSPICS0_OUT_IDX)))
+#define SPI_SS_IDX(p, n)   ((p == 0) ? SPI_SPI_SS_IDX(n) : ((p == 1) ? SPI_SPI_SS_IDX(n) : ((p == 2) ? SPI_HSPI_SS_IDX(n) : ((p == 3) ? SPI_VSPI_SS_IDX(n) : 0))))
+
+#endif
+
 #if CONFIG_DISABLE_HAL_LOCKS
 #define SPI_MUTEX_LOCK()
 #define SPI_MUTEX_UNLOCK()
-
-static spi_t _spi_bus_array[4] = {
-    {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), 0},
-    {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 1},
-    {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 2},
-    {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 3}
+// clang-format off
+static spi_t _spi_bus_array[] = {
+#if CONFIG_IDF_TARGET_ESP32S2
+  {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 0, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 1, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 2, -1, -1, -1, -1}
+#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 1, -1, -1, -1, -1}
+#elif CONFIG_IDF_TARGET_ESP32C2
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1}
+#elif CONFIG_IDF_TARGET_ESP32C3
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1}
+#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+  {(spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1}
+#else
+  {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), 0, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 1, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 2, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 3, -1, -1, -1, -1}
+#endif
 };
+// clang-format on
+#else
+#define SPI_MUTEX_LOCK() \
+  do {                   \
+  } while (xSemaphoreTake(spi->lock, portMAX_DELAY) != pdPASS)
+#define SPI_MUTEX_UNLOCK() xSemaphoreGive(spi->lock)
+
+static spi_t _spi_bus_array[] = {
+#if CONFIG_IDF_TARGET_ESP32S2
+  {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), NULL, 0, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 1, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 2, -1, -1, -1, -1}
+#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1}, {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 1, -1, -1, -1, -1}
+#elif CONFIG_IDF_TARGET_ESP32C2
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1}
+#elif CONFIG_IDF_TARGET_ESP32C3
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1}
+#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+  {(spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1}
 #else
-#define SPI_MUTEX_LOCK()    do {} while (xSemaphoreTake(spi->lock, portMAX_DELAY) != pdPASS)
-#define SPI_MUTEX_UNLOCK()  xSemaphoreGive(spi->lock)
-
-static spi_t _spi_bus_array[4] = {
-    {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), NULL, 0},
-    {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), NULL, 1},
-    {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 2},
-    {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 3}
+  {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), NULL, 0, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), NULL, 1, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 2, -1, -1, -1, -1},
+  {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 3, -1, -1, -1, -1}
+#endif
 };
 #endif
 
-void spiAttachSCK(spi_t * spi, int8_t sck)
-{
-    if(!spi) {
-        return;
-    }
-    if(sck < 0) {
-        if(spi->num == HSPI) {
-            sck = 14;
-        } else if(spi->num == VSPI) {
-            sck = 18;
-        } else {
-            sck = 6;
-        }
-    }
-    pinMode(sck, OUTPUT);
-    pinMatrixOutAttach(sck, SPI_CLK_IDX(spi->num), false, false);
+static bool spiDetachBus(void *bus) {
+  uint8_t spi_num = (int)bus - 1;
+  spi_t *spi = &_spi_bus_array[spi_num];
+
+  if (spi->dev->clock.val == 0) {
+    log_d("SPI bus already stopped");
+    return true;
+  } else if (spi->sck == -1 || (spi->miso == -1 && spi->mosi == -1)) {
+    log_d("Stopping SPI bus");
+    spiStopBus(spi);
+
+    spiDetachSCK(spi);
+    spiDetachMISO(spi);
+    spiDetachMOSI(spi);
+    spiDetachSS(spi);
+    spi = NULL;
+    return true;
+  }
+  return true;
 }
 
-void spiAttachMISO(spi_t * spi, int8_t miso)
-{
-    if(!spi) {
-        return;
-    }
-    if(miso < 0) {
-        if(spi->num == HSPI) {
-            miso = 12;
-        } else if(spi->num == VSPI) {
-            miso = 19;
-        } else {
-            miso = 7;
-        }
-    }
-    SPI_MUTEX_LOCK();
-    pinMode(miso, INPUT);
-    pinMatrixInAttach(miso, SPI_MISO_IDX(spi->num), false);
-    SPI_MUTEX_UNLOCK();
+static bool spiDetachBus_SCK(void *bus) {
+  uint8_t spi_num = (int)bus - 1;
+  spi_t *spi = &_spi_bus_array[spi_num];
+  if (spi->sck != -1) {
+    spiDetachSCK(spi);
+    spiDetachBus(bus);
+  }
+  return true;
 }
 
-void spiAttachMOSI(spi_t * spi, int8_t mosi)
-{
-    if(!spi) {
-        return;
-    }
-    if(mosi < 0) {
-        if(spi->num == HSPI) {
-            mosi = 13;
-        } else if(spi->num == VSPI) {
-            mosi = 23;
-        } else {
-            mosi = 8;
-        }
-    }
-    pinMode(mosi, OUTPUT);
-    pinMatrixOutAttach(mosi, SPI_MOSI_IDX(spi->num), false, false);
+static bool spiDetachBus_MISO(void *bus) {
+  uint8_t spi_num = (int)bus - 1;
+  spi_t *spi = &_spi_bus_array[spi_num];
+  if (spi->miso != -1) {
+    spiDetachMISO(spi);
+    spiDetachBus(bus);
+  }
+  return true;
 }
 
-void spiDetachSCK(spi_t * spi, int8_t sck)
-{
-    if(!spi) {
-        return;
-    }
-    if(sck < 0) {
-        if(spi->num == HSPI) {
-            sck = 14;
-        } else if(spi->num == VSPI) {
-            sck = 18;
-        } else {
-            sck = 6;
-        }
-    }
+static bool spiDetachBus_MOSI(void *bus) {
+  uint8_t spi_num = (int)bus - 1;
+  spi_t *spi = &_spi_bus_array[spi_num];
+  if (spi->mosi != -1) {
+    spiDetachMOSI(spi);
+    spiDetachBus(bus);
+  }
+  return true;
+}
+
+static bool spiDetachBus_SS(void *bus) {
+  uint8_t spi_num = (int)bus - 1;
+  spi_t *spi = &_spi_bus_array[spi_num];
+  if (spi->ss != -1) {
+    spiDetachSS(spi);
+    spiDetachBus(bus);
+  }
+  return true;
+}
+
+bool spiAttachSCK(spi_t *spi, int8_t sck) {
+  if (!spi || sck < 0) {
+    return false;
+  }
+  void *bus = perimanGetPinBus(sck, ESP32_BUS_TYPE_SPI_MASTER_SCK);
+  if (bus != NULL && !perimanClearPinBus(sck)) {
+    return false;
+  }
+  pinMode(sck, OUTPUT);
+  pinMatrixOutAttach(sck, SPI_CLK_IDX(spi->num), false, false);
+  spi->sck = sck;
+  if (!perimanSetPinBus(sck, ESP32_BUS_TYPE_SPI_MASTER_SCK, (void *)(spi->num + 1), spi->num, -1)) {
+    spiDetachBus_SCK((void *)(spi->num + 1));
+    log_e("Failed to set pin bus to SPI for pin %d", sck);
+    return false;
+  }
+  return true;
+}
+
+bool spiAttachMISO(spi_t *spi, int8_t miso) {
+  if (!spi || miso < 0) {
+    return false;
+  }
+  void *bus = perimanGetPinBus(miso, ESP32_BUS_TYPE_SPI_MASTER_MISO);
+  if (bus != NULL && !perimanClearPinBus(miso)) {
+    return false;
+  }
+  pinMode(miso, INPUT);
+  pinMatrixInAttach(miso, SPI_MISO_IDX(spi->num), false);
+  spi->miso = miso;
+  if (!perimanSetPinBus(miso, ESP32_BUS_TYPE_SPI_MASTER_MISO, (void *)(spi->num + 1), spi->num, -1)) {
+    spiDetachBus_MISO((void *)(spi->num + 1));
+    log_e("Failed to set pin bus to SPI for pin %d", miso);
+    return false;
+  }
+  return true;
+}
+
+bool spiAttachMOSI(spi_t *spi, int8_t mosi) {
+  if (!spi || mosi < 0) {
+    return false;
+  }
+  void *bus = perimanGetPinBus(mosi, ESP32_BUS_TYPE_SPI_MASTER_MOSI);
+  if (bus != NULL && !perimanClearPinBus(mosi)) {
+    return false;
+  }
+  pinMode(mosi, OUTPUT);
+  pinMatrixOutAttach(mosi, SPI_MOSI_IDX(spi->num), false, false);
+  spi->mosi = mosi;
+  if (!perimanSetPinBus(mosi, ESP32_BUS_TYPE_SPI_MASTER_MOSI, (void *)(spi->num + 1), spi->num, -1)) {
+    spiDetachBus_MOSI((void *)(spi->num + 1));
+    log_e("Failed to set pin bus to SPI for pin %d", mosi);
+    return false;
+  }
+  return true;
+}
+
+bool spiDetachSCK(spi_t *spi) {
+  if (!spi) {
+    return false;
+  }
+  int8_t sck = spi->sck;
+  if (sck != -1) {
     pinMatrixOutDetach(sck, false, false);
-    pinMode(sck, INPUT);
+    spi->sck = -1;
+    perimanClearPinBus(sck);
+  }
+  return true;
 }
 
-void spiDetachMISO(spi_t * spi, int8_t miso)
-{
-    if(!spi) {
-        return;
-    }
-    if(miso < 0) {
-        if(spi->num == HSPI) {
-            miso = 12;
-        } else if(spi->num == VSPI) {
-            miso = 19;
-        } else {
-            miso = 7;
-        }
-    }
+bool spiDetachMISO(spi_t *spi) {
+  if (!spi) {
+    return false;
+  }
+  int8_t miso = spi->miso;
+  if (miso != -1) {
     pinMatrixInDetach(SPI_MISO_IDX(spi->num), false, false);
-    pinMode(miso, INPUT);
+    spi->miso = -1;
+    perimanClearPinBus(miso);
+  }
+  return true;
 }
 
-void spiDetachMOSI(spi_t * spi, int8_t mosi)
-{
-    if(!spi) {
-        return;
-    }
-    if(mosi < 0) {
-        if(spi->num == HSPI) {
-            mosi = 13;
-        } else if(spi->num == VSPI) {
-            mosi = 23;
-        } else {
-            mosi = 8;
-        }
-    }
+bool spiDetachMOSI(spi_t *spi) {
+  if (!spi) {
+    return false;
+  }
+  int8_t mosi = spi->mosi;
+  if (mosi != -1) {
     pinMatrixOutDetach(mosi, false, false);
-    pinMode(mosi, INPUT);
+    spi->mosi = -1;
+    perimanClearPinBus(mosi);
+  }
+  return true;
 }
 
-void spiAttachSS(spi_t * spi, uint8_t cs_num, int8_t ss)
-{
-    if(!spi) {
-        return;
-    }
-    if(cs_num > 2) {
-        return;
-    }
-    if(ss < 0) {
-        cs_num = 0;
-        if(spi->num == HSPI) {
-            ss = 15;
-        } else if(spi->num == VSPI) {
-            ss = 5;
-        } else {
-            ss = 11;
-        }
-    }
-    pinMode(ss, OUTPUT);
-    pinMatrixOutAttach(ss, SPI_SS_IDX(spi->num, cs_num), false, false);
-    spiEnableSSPins(spi, (1 << cs_num));
+bool spiAttachSS(spi_t *spi, uint8_t ss_num, int8_t ss) {
+  if (!spi || ss < 0 || ss_num > 2) {
+    return false;
+  }
+  void *bus = perimanGetPinBus(ss, ESP32_BUS_TYPE_SPI_MASTER_SS);
+  if (bus != NULL && !perimanClearPinBus(ss)) {
+    return false;
+  }
+  pinMode(ss, OUTPUT);
+  pinMatrixOutAttach(ss, SPI_SS_IDX(spi->num, ss_num), false, false);
+  spiEnableSSPins(spi, (1 << ss_num));
+  spi->ss = ss;
+  if (!perimanSetPinBus(ss, ESP32_BUS_TYPE_SPI_MASTER_SS, (void *)(spi->num + 1), spi->num, -1)) {
+    spiDetachBus_SS((void *)(spi->num + 1));
+    log_e("Failed to set pin bus to SPI for pin %d", ss);
+    return false;
+  }
+  return true;
 }
 
-void spiDetachSS(spi_t * spi, int8_t ss)
-{
-    if(!spi) {
-        return;
-    }
-    if(ss < 0) {
-        if(spi->num == HSPI) {
-            ss = 15;
-        } else if(spi->num == VSPI) {
-            ss = 5;
-        } else {
-            ss = 11;
-        }
-    }
+bool spiDetachSS(spi_t *spi) {
+  if (!spi) {
+    return false;
+  }
+  int8_t ss = spi->ss;
+  if (ss != -1) {
     pinMatrixOutDetach(ss, false, false);
-    pinMode(ss, INPUT);
+    spi->ss = -1;
+    perimanClearPinBus(ss);
+  }
+  return true;
 }
 
-void spiEnableSSPins(spi_t * spi, uint8_t cs_mask)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->pin.val &= ~(cs_mask & SPI_CS_MASK_ALL);
-    SPI_MUTEX_UNLOCK();
+void spiEnableSSPins(spi_t *spi, uint8_t ss_mask) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+#if CONFIG_IDF_TARGET_ESP32
+  spi->dev->pin.val &= ~(ss_mask & SPI_SS_MASK_ALL);
+#else
+  spi->dev->misc.val &= ~(ss_mask & SPI_SS_MASK_ALL);
+#endif
+  SPI_MUTEX_UNLOCK();
 }
 
-void spiDisableSSPins(spi_t * spi, uint8_t cs_mask)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->pin.val |= (cs_mask & SPI_CS_MASK_ALL);
-    SPI_MUTEX_UNLOCK();
+void spiDisableSSPins(spi_t *spi, uint8_t ss_mask) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+#if CONFIG_IDF_TARGET_ESP32
+  spi->dev->pin.val |= (ss_mask & SPI_SS_MASK_ALL);
+#else
+  spi->dev->misc.val |= (ss_mask & SPI_SS_MASK_ALL);
+#endif
+  SPI_MUTEX_UNLOCK();
 }
 
-void spiSSEnable(spi_t * spi)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->user.cs_setup = 1;
-    spi->dev->user.cs_hold = 1;
-    SPI_MUTEX_UNLOCK();
+void spiSSEnable(spi_t *spi) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->user.cs_setup = 1;
+  spi->dev->user.cs_hold = 1;
+  SPI_MUTEX_UNLOCK();
 }
 
-void spiSSDisable(spi_t * spi)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->user.cs_setup = 0;
-    spi->dev->user.cs_hold = 0;
-    SPI_MUTEX_UNLOCK();
+void spiSSDisable(spi_t *spi) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->user.cs_setup = 0;
+  spi->dev->user.cs_hold = 0;
+  SPI_MUTEX_UNLOCK();
 }
 
-void spiSSSet(spi_t * spi)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->pin.cs_keep_active = 1;
-    SPI_MUTEX_UNLOCK();
+void spiSSSet(spi_t *spi) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+#if CONFIG_IDF_TARGET_ESP32
+  spi->dev->pin.cs_keep_active = 1;
+#else
+  spi->dev->misc.cs_keep_active = 1;
+#endif
+  SPI_MUTEX_UNLOCK();
 }
 
-void spiSSClear(spi_t * spi)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->pin.cs_keep_active = 0;
-    SPI_MUTEX_UNLOCK();
+void spiSSClear(spi_t *spi) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+#if CONFIG_IDF_TARGET_ESP32
+  spi->dev->pin.cs_keep_active = 0;
+#else
+  spi->dev->misc.cs_keep_active = 0;
+#endif
+  SPI_MUTEX_UNLOCK();
 }
 
-uint32_t spiGetClockDiv(spi_t * spi)
-{
-    if(!spi) {
-        return 0;
-    }
-    return spi->dev->clock.val;
+uint32_t spiGetClockDiv(spi_t *spi) {
+  if (!spi) {
+    return 0;
+  }
+  return spi->dev->clock.val;
 }
 
-void spiSetClockDiv(spi_t * spi, uint32_t clockDiv)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->clock.val = clockDiv;
-    SPI_MUTEX_UNLOCK();
+void spiSetClockDiv(spi_t *spi, uint32_t clockDiv) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->clock.val = clockDiv;
+  SPI_MUTEX_UNLOCK();
 }
 
-uint8_t spiGetDataMode(spi_t * spi)
-{
-    if(!spi) {
-        return 0;
-    }
-    bool idleEdge = spi->dev->pin.ck_idle_edge;
-    bool outEdge = spi->dev->user.ck_out_edge;
-    if(idleEdge) {
-        if(outEdge) {
-            return SPI_MODE2;
-        }
-        return SPI_MODE3;
-    }
-    if(outEdge) {
-        return SPI_MODE1;
-    }
-    return SPI_MODE0;
+uint8_t spiGetDataMode(spi_t *spi) {
+  if (!spi) {
+    return 0;
+  }
+#if CONFIG_IDF_TARGET_ESP32
+  bool idleEdge = spi->dev->pin.ck_idle_edge;
+#else
+  bool idleEdge = spi->dev->misc.ck_idle_edge;
+#endif
+  bool outEdge = spi->dev->user.ck_out_edge;
+  if (idleEdge) {
+    if (outEdge) {
+      return SPI_MODE2;
+    }
+    return SPI_MODE3;
+  }
+  if (outEdge) {
+    return SPI_MODE1;
+  }
+  return SPI_MODE0;
 }
 
-void spiSetDataMode(spi_t * spi, uint8_t dataMode)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    switch (dataMode) {
+void spiSetDataMode(spi_t *spi, uint8_t dataMode) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+  switch (dataMode) {
     case SPI_MODE1:
-        spi->dev->pin.ck_idle_edge = 0;
-        spi->dev->user.ck_out_edge = 1;
-        break;
+#if CONFIG_IDF_TARGET_ESP32
+      spi->dev->pin.ck_idle_edge = 0;
+#else
+      spi->dev->misc.ck_idle_edge = 0;
+#endif
+      spi->dev->user.ck_out_edge = 1;
+      break;
     case SPI_MODE2:
-        spi->dev->pin.ck_idle_edge = 1;
-        spi->dev->user.ck_out_edge = 1;
-        break;
+#if CONFIG_IDF_TARGET_ESP32
+      spi->dev->pin.ck_idle_edge = 1;
+#else
+      spi->dev->misc.ck_idle_edge = 1;
+#endif
+      spi->dev->user.ck_out_edge = 1;
+      break;
     case SPI_MODE3:
-        spi->dev->pin.ck_idle_edge = 1;
-        spi->dev->user.ck_out_edge = 0;
-        break;
+#if CONFIG_IDF_TARGET_ESP32
+      spi->dev->pin.ck_idle_edge = 1;
+#else
+      spi->dev->misc.ck_idle_edge = 1;
+#endif
+      spi->dev->user.ck_out_edge = 0;
+      break;
     case SPI_MODE0:
     default:
-        spi->dev->pin.ck_idle_edge = 0;
-        spi->dev->user.ck_out_edge = 0;
-        break;
-    }
-    SPI_MUTEX_UNLOCK();
+#if CONFIG_IDF_TARGET_ESP32
+      spi->dev->pin.ck_idle_edge = 0;
+#else
+      spi->dev->misc.ck_idle_edge = 0;
+#endif
+      spi->dev->user.ck_out_edge = 0;
+      break;
+  }
+  SPI_MUTEX_UNLOCK();
 }
 
-uint8_t spiGetBitOrder(spi_t * spi)
-{
-    if(!spi) {
-        return 0;
-    }
-    return (spi->dev->ctrl.wr_bit_order | spi->dev->ctrl.rd_bit_order) == 0;
+uint8_t spiGetBitOrder(spi_t *spi) {
+  if (!spi) {
+    return 0;
+  }
+  return (spi->dev->ctrl.wr_bit_order | spi->dev->ctrl.rd_bit_order) == 0;
 }
 
-void spiSetBitOrder(spi_t * spi, uint8_t bitOrder)
-{
-    if(!spi) {
-        return;
-    }
+void spiSetBitOrder(spi_t *spi, uint8_t bitOrder) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+  if (SPI_MSBFIRST == bitOrder) {
+    spi->dev->ctrl.wr_bit_order = 0;
+    spi->dev->ctrl.rd_bit_order = 0;
+  } else if (SPI_LSBFIRST == bitOrder) {
+    spi->dev->ctrl.wr_bit_order = 1;
+    spi->dev->ctrl.rd_bit_order = 1;
+  }
+  SPI_MUTEX_UNLOCK();
+}
+
+static void _on_apb_change(void *arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb) {
+  spi_t *spi = (spi_t *)arg;
+  if (ev_type == APB_BEFORE_CHANGE) {
     SPI_MUTEX_LOCK();
-    if (SPI_MSBFIRST == bitOrder) {
-        spi->dev->ctrl.wr_bit_order = 0;
-        spi->dev->ctrl.rd_bit_order = 0;
-    } else if (SPI_LSBFIRST == bitOrder) {
-        spi->dev->ctrl.wr_bit_order = 1;
-        spi->dev->ctrl.rd_bit_order = 1;
-    }
+    while (spi->dev->cmd.usr);
+  } else {
+    spi->dev->clock.val = spiFrequencyToClockDiv(old_apb / ((spi->dev->clock.clkdiv_pre + 1) * (spi->dev->clock.clkcnt_n + 1)));
     SPI_MUTEX_UNLOCK();
+  }
 }
 
-static void _on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb)
-{
-    spi_t * spi = (spi_t *)arg;
-    if(ev_type == APB_BEFORE_CHANGE){
-        SPI_MUTEX_LOCK();
-        while(spi->dev->cmd.usr);
-    } else {
-        spi->dev->clock.val = spiFrequencyToClockDiv(old_apb / ((spi->dev->clock.clkdiv_pre + 1) * (spi->dev->clock.clkcnt_n + 1)));
-        SPI_MUTEX_UNLOCK();
-    }
+static void spiInitBus(spi_t *spi) {
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+  spi->dev->slave.trans_done = 0;
+#endif
+  spi->dev->slave.val = 0;
+#if CONFIG_IDF_TARGET_ESP32
+  spi->dev->pin.val = 0;
+#else
+  spi->dev->misc.val = 0;
+#endif
+  spi->dev->user.val = 0;
+  spi->dev->user1.val = 0;
+  spi->dev->ctrl.val = 0;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+  spi->dev->ctrl1.val = 0;
+  spi->dev->ctrl2.val = 0;
+#else
+  spi->dev->clk_gate.val = 0;
+  spi->dev->dma_conf.val = 0;
+  spi->dev->dma_conf.rx_afifo_rst = 1;
+  spi->dev->dma_conf.buf_afifo_rst = 1;
+#endif
+  spi->dev->clock.val = 0;
 }
 
-static void spiInitBus(spi_t * spi)
-{
-    spi->dev->slave.trans_done = 0;
-    spi->dev->slave.slave_mode = 0;
-    spi->dev->pin.val = 0;
-    spi->dev->user.val = 0;
-    spi->dev->user1.val = 0;
-    spi->dev->ctrl.val = 0;
-    spi->dev->ctrl1.val = 0;
-    spi->dev->ctrl2.val = 0;
-    spi->dev->clock.val = 0;
-}
+void spiStopBus(spi_t *spi) {
+  if (!spi) {
+    return;
+  }
 
-void spiStopBus(spi_t * spi)
-{
-    if(!spi) {
-        return;
-    }
-    
-    removeApbChangeCallback(spi, _on_apb_change);
-    
-    SPI_MUTEX_LOCK();
-    spiInitBus(spi);
-    SPI_MUTEX_UNLOCK();
+  removeApbChangeCallback(spi, _on_apb_change);
+
+  SPI_MUTEX_LOCK();
+  spiInitBus(spi);
+  SPI_MUTEX_UNLOCK();
 }
 
-spi_t * spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder)
-{
-    if(spi_num > 3){
-        return NULL;
-    }
+spi_t *spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder) {
+  if (spi_num >= SPI_COUNT) {
+    return NULL;
+  }
+
+  perimanSetBusDeinit(ESP32_BUS_TYPE_SPI_MASTER_SCK, spiDetachBus_SCK);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_SPI_MASTER_MISO, spiDetachBus_MISO);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_SPI_MASTER_MOSI, spiDetachBus_MOSI);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_SPI_MASTER_SS, spiDetachBus_SS);
 
-    spi_t * spi = &_spi_bus_array[spi_num];
+  spi_t *spi = &_spi_bus_array[spi_num];
 
 #if !CONFIG_DISABLE_HAL_LOCKS
-    if(spi->lock == NULL){
-        spi->lock = xSemaphoreCreateMutex();
-        if(spi->lock == NULL) {
-            return NULL;
-        }
+  if (spi->lock == NULL) {
+    spi->lock = xSemaphoreCreateMutex();
+    if (spi->lock == NULL) {
+      return NULL;
     }
+  }
 #endif
 
-    if(spi_num == HSPI) {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST);
-    } else if(spi_num == VSPI) {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2);
-    } else {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1);
-    }
+#if CONFIG_IDF_TARGET_ESP32S2
+  if (spi_num == FSPI) {
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_CLK_EN);
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_RST);
+  } else if (spi_num == HSPI) {
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN);
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST);
+  } else {
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
+  }
+#elif CONFIG_IDF_TARGET_ESP32S3
+  if (spi_num == FSPI) {
+    periph_ll_reset(PERIPH_SPI2_MODULE);
+    periph_ll_enable_clk_clear_rst(PERIPH_SPI2_MODULE);
+  } else if (spi_num == HSPI) {
+    periph_ll_reset(PERIPH_SPI3_MODULE);
+    periph_ll_enable_clk_clear_rst(PERIPH_SPI3_MODULE);
+  }
+#elif CONFIG_IDF_TARGET_ESP32
+  if (spi_num == HSPI) {
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_CLK_EN);
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_RST);
+  } else if (spi_num == VSPI) {
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN);
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI3_RST);
+  } else {
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
+  }
+#elif defined(__PERIPH_CTRL_ALLOW_LEGACY_API)
+  periph_ll_reset(PERIPH_SPI2_MODULE);
+  periph_ll_enable_clk_clear_rst(PERIPH_SPI2_MODULE);
+#endif
 
-    SPI_MUTEX_LOCK();
-    spiInitBus(spi);
-    spi->dev->user.usr_mosi = 1;
-    spi->dev->user.usr_miso = 1;
-    spi->dev->user.doutdin = 1;
-
-    int i;
-    for(i=0; i<16; i++) {
-        spi->dev->data_buf[i] = 0x00000000;
-    }
-    SPI_MUTEX_UNLOCK();
+  SPI_MUTEX_LOCK();
+  spiInitBus(spi);
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->clk_gate.clk_en = 1;
+  spi->dev->clk_gate.mst_clk_sel = 1;
+  spi->dev->clk_gate.mst_clk_active = 1;
+#if defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C2) || defined(CONFIG_IDF_TARGET_ESP32C3)
+  spi->dev->dma_conf.tx_seg_trans_clr_en = 1;
+  spi->dev->dma_conf.rx_seg_trans_clr_en = 1;
+  spi->dev->dma_conf.dma_seg_trans_en = 0;
+#endif
+#endif
+  spi->dev->user.usr_mosi = 1;
+  spi->dev->user.usr_miso = 1;
+  spi->dev->user.doutdin = 1;
+  int i;
+  for (i = 0; i < 16; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+    spi->dev->data_buf[i].val = 0x00000000;
+#else
+    spi->dev->data_buf[i] = 0x00000000;
+#endif
+  }
+  SPI_MUTEX_UNLOCK();
 
-    spiSetDataMode(spi, dataMode);
-    spiSetBitOrder(spi, bitOrder);
-    spiSetClockDiv(spi, clockDiv);
+  spiSetDataMode(spi, dataMode);
+  spiSetBitOrder(spi, bitOrder);
+  spiSetClockDiv(spi, clockDiv);
 
-    addApbChangeCallback(spi, _on_apb_change);
-    return spi;
+  addApbChangeCallback(spi, _on_apb_change);
+
+  return spi;
 }
 
-void spiWaitReady(spi_t * spi)
-{
-    if(!spi) {
-        return;
-    }
-    while(spi->dev->cmd.usr);
+void spiWaitReady(spi_t *spi) {
+  if (!spi) {
+    return;
+  }
+  while (spi->dev->cmd.usr);
 }
 
-void spiWrite(spi_t * spi, const uint32_t *data, uint8_t len)
-{
-    if(!spi) {
-        return;
-    }
-    int i;
-    if(len > 16) {
-        len = 16;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 0;
-    for(i=0; i<len; i++) {
-        spi->dev->data_buf[i] = data[i];
-    }
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    SPI_MUTEX_UNLOCK();
+#if CONFIG_IDF_TARGET_ESP32S2
+#define usr_mosi_dbitlen usr_mosi_bit_len
+#define usr_miso_dbitlen usr_miso_bit_len
+#elif !defined(CONFIG_IDF_TARGET_ESP32)
+#define usr_mosi_dbitlen ms_data_bitlen
+#define usr_miso_dbitlen ms_data_bitlen
+#define mosi_dlen        ms_dlen
+#define miso_dlen        ms_dlen
+#endif
+
+void spiWrite(spi_t *spi, const uint32_t *data, uint8_t len) {
+  if (!spi) {
+    return;
+  }
+  int i;
+  if (len > 16) {
+    len = 16;
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+  spi->dev->miso_dlen.usr_miso_dbitlen = 0;
+#endif
+  for (i = 0; i < len; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+    spi->dev->data_buf[i].val = data[i];
+#else
+    spi->dev->data_buf[i] = data[i];
+#endif
+  }
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+  SPI_MUTEX_UNLOCK();
 }
 
-void spiTransfer(spi_t * spi, uint32_t *data, uint8_t len)
-{
-    if(!spi) {
-        return;
-    }
-    int i;
-    if(len > 16) {
-        len = 16;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1;
-    spi->dev->miso_dlen.usr_miso_dbitlen = (len * 32) - 1;
-    for(i=0; i<len; i++) {
-        spi->dev->data_buf[i] = data[i];
-    }
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    for(i=0; i<len; i++) {
-        data[i] = spi->dev->data_buf[i];
-    }
-    SPI_MUTEX_UNLOCK();
+void spiTransfer(spi_t *spi, uint32_t *data, uint8_t len) {
+  if (!spi) {
+    return;
+  }
+  int i;
+  if (len > 16) {
+    len = 16;
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1;
+  spi->dev->miso_dlen.usr_miso_dbitlen = (len * 32) - 1;
+  for (i = 0; i < len; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+    spi->dev->data_buf[i].val = data[i];
+#else
+    spi->dev->data_buf[i] = data[i];
+#endif
+  }
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+  for (i = 0; i < len; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+    data[i] = spi->dev->data_buf[i].val;
+#else
+    data[i] = spi->dev->data_buf[i];
+#endif
+  }
+  SPI_MUTEX_UNLOCK();
 }
 
-void spiWriteByte(spi_t * spi, uint8_t data)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 0;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    SPI_MUTEX_UNLOCK();
+void spiWriteByte(spi_t *spi, uint8_t data) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+  spi->dev->miso_dlen.usr_miso_dbitlen = 0;
+#endif
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+  SPI_MUTEX_UNLOCK();
 }
 
-uint8_t spiTransferByte(spi_t * spi, uint8_t data)
-{
-    if(!spi) {
-        return 0;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 7;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    data = spi->dev->data_buf[0] & 0xFF;
-    SPI_MUTEX_UNLOCK();
-    return data;
+uint8_t spiTransferByte(spi_t *spi, uint8_t data) {
+  if (!spi) {
+    return 0;
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
+  spi->dev->miso_dlen.usr_miso_dbitlen = 7;
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  data = spi->dev->data_buf[0].val & 0xFF;
+#else
+  data = spi->dev->data_buf[0] & 0xFF;
+#endif
+  SPI_MUTEX_UNLOCK();
+  return data;
 }
 
-static uint32_t __spiTranslate32(uint32_t data)
-{
-    union {
-        uint32_t l;
-        uint8_t b[4];
-    } out;
-    out.l = data;
-    return out.b[3] | (out.b[2] << 8) | (out.b[1] << 16) | (out.b[0] << 24);
+static uint32_t __spiTranslate32(uint32_t data) {
+  union {
+    uint32_t l;
+    uint8_t b[4];
+  } out;
+  out.l = data;
+  return out.b[3] | (out.b[2] << 8) | (out.b[1] << 16) | (out.b[0] << 24);
 }
 
-void spiWriteWord(spi_t * spi, uint16_t data)
-{
-    if(!spi) {
-        return;
-    }
-    if(!spi->dev->ctrl.wr_bit_order){
-        data = (data >> 8) | (data << 8);
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 0;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    SPI_MUTEX_UNLOCK();
+void spiWriteWord(spi_t *spi, uint16_t data) {
+  if (!spi) {
+    return;
+  }
+  if (!spi->dev->ctrl.wr_bit_order) {
+    data = (data >> 8) | (data << 8);
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+  spi->dev->miso_dlen.usr_miso_dbitlen = 0;
+#endif
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+  SPI_MUTEX_UNLOCK();
 }
 
-uint16_t spiTransferWord(spi_t * spi, uint16_t data)
-{
-    if(!spi) {
-        return 0;
-    }
-    if(!spi->dev->ctrl.wr_bit_order){
-        data = (data >> 8) | (data << 8);
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 15;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    data = spi->dev->data_buf[0];
-    SPI_MUTEX_UNLOCK();
-    if(!spi->dev->ctrl.rd_bit_order){
-        data = (data >> 8) | (data << 8);
-    }
-    return data;
+uint16_t spiTransferWord(spi_t *spi, uint16_t data) {
+  if (!spi) {
+    return 0;
+  }
+  if (!spi->dev->ctrl.wr_bit_order) {
+    data = (data >> 8) | (data << 8);
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
+  spi->dev->miso_dlen.usr_miso_dbitlen = 15;
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  data = spi->dev->data_buf[0].val;
+#else
+  data = spi->dev->data_buf[0];
+#endif
+  SPI_MUTEX_UNLOCK();
+  if (!spi->dev->ctrl.rd_bit_order) {
+    data = (data >> 8) | (data << 8);
+  }
+  return data;
 }
 
-void spiWriteLong(spi_t * spi, uint32_t data)
-{
-    if(!spi) {
-        return;
-    }
-    if(!spi->dev->ctrl.wr_bit_order){
-        data = __spiTranslate32(data);
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 0;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    SPI_MUTEX_UNLOCK();
+void spiWriteLong(spi_t *spi, uint32_t data) {
+  if (!spi) {
+    return;
+  }
+  if (!spi->dev->ctrl.wr_bit_order) {
+    data = __spiTranslate32(data);
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+  spi->dev->miso_dlen.usr_miso_dbitlen = 0;
+#endif
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+  SPI_MUTEX_UNLOCK();
 }
 
-uint32_t spiTransferLong(spi_t * spi, uint32_t data)
-{
-    if(!spi) {
-        return 0;
-    }
-    if(!spi->dev->ctrl.wr_bit_order){
-        data = __spiTranslate32(data);
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 31;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    data = spi->dev->data_buf[0];
-    SPI_MUTEX_UNLOCK();
-    if(!spi->dev->ctrl.rd_bit_order){
-        data = __spiTranslate32(data);
-    }
-    return data;
+uint32_t spiTransferLong(spi_t *spi, uint32_t data) {
+  if (!spi) {
+    return 0;
+  }
+  if (!spi->dev->ctrl.wr_bit_order) {
+    data = __spiTranslate32(data);
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
+  spi->dev->miso_dlen.usr_miso_dbitlen = 31;
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  data = spi->dev->data_buf[0].val;
+#else
+  data = spi->dev->data_buf[0];
+#endif
+  SPI_MUTEX_UNLOCK();
+  if (!spi->dev->ctrl.rd_bit_order) {
+    data = __spiTranslate32(data);
+  }
+  return data;
 }
 
-static void __spiTransferBytes(spi_t * spi, const uint8_t * data, uint8_t * out, uint32_t bytes)
-{
-    if(!spi) {
-        return;
-    }
-    int i;
+static void __spiTransferBytes(spi_t *spi, const uint8_t *data, uint8_t *out, uint32_t bytes) {
+  if (!spi) {
+    return;
+  }
+  uint32_t i;
 
-    if(bytes > 64) {
-        bytes = 64;
-    }
+  if (bytes > 64) {
+    bytes = 64;
+  }
 
-    uint32_t words = (bytes + 3) / 4;//16 max
+  uint32_t words = (bytes + 3) / 4;  //16 max
 
-    uint32_t wordsBuf[16] = {0,};
-    uint8_t * bytesBuf = (uint8_t *) wordsBuf;
+  uint32_t wordsBuf[16] = {
+    0,
+  };
+  uint8_t *bytesBuf = (uint8_t *)wordsBuf;
 
-    if(data) {
-        memcpy(bytesBuf, data, bytes);//copy data to buffer
-    } else {
-        memset(bytesBuf, 0xFF, bytes);
-    }
+  if (data) {
+    memcpy(bytesBuf, data, bytes);  //copy data to buffer
+  } else {
+    memset(bytesBuf, 0xFF, bytes);
+  }
 
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = ((bytes * 8) - 1);
-    spi->dev->miso_dlen.usr_miso_dbitlen = ((bytes * 8) - 1);
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = ((bytes * 8) - 1);
+  spi->dev->miso_dlen.usr_miso_dbitlen = ((bytes * 8) - 1);
 
-    for(i=0; i<words; i++) {
-        spi->dev->data_buf[i] = wordsBuf[i];    //copy buffer to spi fifo
-    }
+  for (i = 0; i < words; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+    spi->dev->data_buf[i].val = wordsBuf[i];  //copy buffer to spi fifo
+#else
+    spi->dev->data_buf[i] = wordsBuf[i];  //copy buffer to spi fifo
+#endif
+  }
 
-    spi->dev->cmd.usr = 1;
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
 
-    while(spi->dev->cmd.usr);
+  while (spi->dev->cmd.usr);
 
-    if(out) {
-        for(i=0; i<words; i++) {
-            wordsBuf[i] = spi->dev->data_buf[i];//copy spi fifo to buffer
-        }
-        memcpy(out, bytesBuf, bytes);//copy buffer to output
+  if (out) {
+    for (i = 0; i < words; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+      wordsBuf[i] = spi->dev->data_buf[i].val;  //copy spi fifo to buffer
+#else
+      wordsBuf[i] = spi->dev->data_buf[i];  //copy spi fifo to buffer
+#endif
     }
+    memcpy(out, bytesBuf, bytes);  //copy buffer to output
+  }
 }
 
-void spiTransferBytes(spi_t * spi, const uint8_t * data, uint8_t * out, uint32_t size)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    while(size) {
-        if(size > 64) {
-            __spiTransferBytes(spi, data, out, 64);
-            size -= 64;
-            if(data) {
-                data += 64;
-            }
-            if(out) {
-                out += 64;
-            }
-        } else {
-            __spiTransferBytes(spi, data, out, size);
-            size = 0;
-        }
+void spiTransferBytes(spi_t *spi, const uint8_t *data, uint8_t *out, uint32_t size) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+  while (size) {
+    if (size > 64) {
+      __spiTransferBytes(spi, data, out, 64);
+      size -= 64;
+      if (data) {
+        data += 64;
+      }
+      if (out) {
+        out += 64;
+      }
+    } else {
+      __spiTransferBytes(spi, data, out, size);
+      size = 0;
     }
-    SPI_MUTEX_UNLOCK();
+  }
+  SPI_MUTEX_UNLOCK();
 }
 
-void spiTransferBits(spi_t * spi, uint32_t data, uint32_t * out, uint8_t bits)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spiTransferBitsNL(spi, data, out, bits);
-    SPI_MUTEX_UNLOCK();
+void spiTransferBits(spi_t *spi, uint32_t data, uint32_t *out, uint8_t bits) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+  spiTransferBitsNL(spi, data, out, bits);
+  SPI_MUTEX_UNLOCK();
 }
 
 /*
  * Manual Lock Management
  * */
 
-#define MSB_32_SET(var, val) { uint8_t * d = (uint8_t *)&(val); (var) = d[3] | (d[2] << 8) | (d[1] << 16) | (d[0] << 24); }
-#define MSB_24_SET(var, val) { uint8_t * d = (uint8_t *)&(val); (var) = d[2] | (d[1] << 8) | (d[0] << 16); }
-#define MSB_16_SET(var, val) { (var) = (((val) & 0xFF00) >> 8) | (((val) & 0xFF) << 8); }
-#define MSB_PIX_SET(var, val) { uint8_t * d = (uint8_t *)&(val); (var) = d[1] | (d[0] << 8) | (d[3] << 16) | (d[2] << 24); }
-
-void spiTransaction(spi_t * spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
-    spi->dev->clock.val = clockDiv;
-    switch (dataMode) {
-        case SPI_MODE1:
-            spi->dev->pin.ck_idle_edge = 0;
-            spi->dev->user.ck_out_edge = 1;
-            break;
-        case SPI_MODE2:
-            spi->dev->pin.ck_idle_edge = 1;
-            spi->dev->user.ck_out_edge = 1;
-            break;
-        case SPI_MODE3:
-            spi->dev->pin.ck_idle_edge = 1;
-            spi->dev->user.ck_out_edge = 0;
-            break;
-        case SPI_MODE0:
-        default:
-            spi->dev->pin.ck_idle_edge = 0;
-            spi->dev->user.ck_out_edge = 0;
-            break;
-    }
-    if (SPI_MSBFIRST == bitOrder) {
-        spi->dev->ctrl.wr_bit_order = 0;
-        spi->dev->ctrl.rd_bit_order = 0;
-    } else if (SPI_LSBFIRST == bitOrder) {
-        spi->dev->ctrl.wr_bit_order = 1;
-        spi->dev->ctrl.rd_bit_order = 1;
-    }
+#define MSB_32_SET(var, val)                                  \
+  {                                                           \
+    uint8_t *d = (uint8_t *)&(val);                           \
+    (var) = d[3] | (d[2] << 8) | (d[1] << 16) | (d[0] << 24); \
+  }
+#define MSB_24_SET(var, val)                   \
+  {                                            \
+    uint8_t *d = (uint8_t *)&(val);            \
+    (var) = d[2] | (d[1] << 8) | (d[0] << 16); \
+  }
+#define MSB_16_SET(var, val) \
+  { (var) = (((val) & 0xFF00) >> 8) | (((val) & 0xFF) << 8); }
+#define MSB_PIX_SET(var, val)                                 \
+  {                                                           \
+    uint8_t *d = (uint8_t *)&(val);                           \
+    (var) = d[1] | (d[0] << 8) | (d[3] << 16) | (d[2] << 24); \
+  }
+
+void spiTransaction(spi_t *spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
+  spi->dev->clock.val = clockDiv;
+  switch (dataMode) {
+    case SPI_MODE1:
+#if CONFIG_IDF_TARGET_ESP32
+      spi->dev->pin.ck_idle_edge = 0;
+#else
+      spi->dev->misc.ck_idle_edge = 0;
+#endif
+      spi->dev->user.ck_out_edge = 1;
+      break;
+    case SPI_MODE2:
+#if CONFIG_IDF_TARGET_ESP32
+      spi->dev->pin.ck_idle_edge = 1;
+#else
+      spi->dev->misc.ck_idle_edge = 1;
+#endif
+      spi->dev->user.ck_out_edge = 1;
+      break;
+    case SPI_MODE3:
+#if CONFIG_IDF_TARGET_ESP32
+      spi->dev->pin.ck_idle_edge = 1;
+#else
+      spi->dev->misc.ck_idle_edge = 1;
+#endif
+      spi->dev->user.ck_out_edge = 0;
+      break;
+    case SPI_MODE0:
+    default:
+#if CONFIG_IDF_TARGET_ESP32
+      spi->dev->pin.ck_idle_edge = 0;
+#else
+      spi->dev->misc.ck_idle_edge = 0;
+#endif
+      spi->dev->user.ck_out_edge = 0;
+      break;
+  }
+  if (SPI_MSBFIRST == bitOrder) {
+    spi->dev->ctrl.wr_bit_order = 0;
+    spi->dev->ctrl.rd_bit_order = 0;
+  } else if (SPI_LSBFIRST == bitOrder) {
+    spi->dev->ctrl.wr_bit_order = 1;
+    spi->dev->ctrl.rd_bit_order = 1;
+  }
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  // Sync new config with hardware, fixes https://github.com/espressif/arduino-esp32/issues/9221
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
 }
 
-void spiSimpleTransaction(spi_t * spi)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_LOCK();
+void spiSimpleTransaction(spi_t *spi) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_LOCK();
 }
 
-void spiEndTransaction(spi_t * spi)
-{
-    if(!spi) {
-        return;
-    }
-    SPI_MUTEX_UNLOCK();
+void spiEndTransaction(spi_t *spi) {
+  if (!spi) {
+    return;
+  }
+  SPI_MUTEX_UNLOCK();
 }
 
-void IRAM_ATTR spiWriteByteNL(spi_t * spi, uint8_t data)
-{
-    if(!spi) {
-        return;
-    }
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 0;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
+void ARDUINO_ISR_ATTR spiWriteByteNL(spi_t *spi, uint8_t data) {
+  if (!spi) {
+    return;
+  }
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+  spi->dev->miso_dlen.usr_miso_dbitlen = 0;
+#endif
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
 }
 
-uint8_t spiTransferByteNL(spi_t * spi, uint8_t data)
-{
-    if(!spi) {
-        return 0;
-    }
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 7;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    data = spi->dev->data_buf[0] & 0xFF;
-    return data;
+uint8_t spiTransferByteNL(spi_t *spi, uint8_t data) {
+  if (!spi) {
+    return 0;
+  }
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
+  spi->dev->miso_dlen.usr_miso_dbitlen = 7;
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  data = spi->dev->data_buf[0].val & 0xFF;
+#else
+  data = spi->dev->data_buf[0] & 0xFF;
+#endif
+  return data;
 }
 
-void IRAM_ATTR spiWriteShortNL(spi_t * spi, uint16_t data)
-{
-    if(!spi) {
-        return;
-    }
-    if(!spi->dev->ctrl.wr_bit_order){
-        MSB_16_SET(data, data);
-    }
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 0;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
+void ARDUINO_ISR_ATTR spiWriteShortNL(spi_t *spi, uint16_t data) {
+  if (!spi) {
+    return;
+  }
+  if (!spi->dev->ctrl.wr_bit_order) {
+    MSB_16_SET(data, data);
+  }
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+  spi->dev->miso_dlen.usr_miso_dbitlen = 0;
+#endif
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
 }
 
-uint16_t spiTransferShortNL(spi_t * spi, uint16_t data)
-{
-    if(!spi) {
-        return 0;
-    }
-    if(!spi->dev->ctrl.wr_bit_order){
-        MSB_16_SET(data, data);
-    }
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 15;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    data = spi->dev->data_buf[0] & 0xFFFF;
-    if(!spi->dev->ctrl.rd_bit_order){
-        MSB_16_SET(data, data);
-    }
-    return data;
+uint16_t spiTransferShortNL(spi_t *spi, uint16_t data) {
+  if (!spi) {
+    return 0;
+  }
+  if (!spi->dev->ctrl.wr_bit_order) {
+    MSB_16_SET(data, data);
+  }
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
+  spi->dev->miso_dlen.usr_miso_dbitlen = 15;
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  data = spi->dev->data_buf[0].val & 0xFFFF;
+#else
+  data = spi->dev->data_buf[0] & 0xFFFF;
+#endif
+  if (!spi->dev->ctrl.rd_bit_order) {
+    MSB_16_SET(data, data);
+  }
+  return data;
 }
 
-void IRAM_ATTR spiWriteLongNL(spi_t * spi, uint32_t data)
-{
-    if(!spi) {
-        return;
-    }
-    if(!spi->dev->ctrl.wr_bit_order){
-        MSB_32_SET(data, data);
-    }
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 0;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
+void ARDUINO_ISR_ATTR spiWriteLongNL(spi_t *spi, uint32_t data) {
+  if (!spi) {
+    return;
+  }
+  if (!spi->dev->ctrl.wr_bit_order) {
+    MSB_32_SET(data, data);
+  }
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+  spi->dev->miso_dlen.usr_miso_dbitlen = 0;
+#endif
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
 }
 
-uint32_t spiTransferLongNL(spi_t * spi, uint32_t data)
-{
-    if(!spi) {
-        return 0;
-    }
-    if(!spi->dev->ctrl.wr_bit_order){
-        MSB_32_SET(data, data);
-    }
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
-    spi->dev->miso_dlen.usr_miso_dbitlen = 31;
-    spi->dev->data_buf[0] = data;
-    spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    data = spi->dev->data_buf[0];
-    if(!spi->dev->ctrl.rd_bit_order){
-        MSB_32_SET(data, data);
-    }
-    return data;
+uint32_t spiTransferLongNL(spi_t *spi, uint32_t data) {
+  if (!spi) {
+    return 0;
+  }
+  if (!spi->dev->ctrl.wr_bit_order) {
+    MSB_32_SET(data, data);
+  }
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
+  spi->dev->miso_dlen.usr_miso_dbitlen = 31;
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  data = spi->dev->data_buf[0].val;
+#else
+  data = spi->dev->data_buf[0];
+#endif
+  if (!spi->dev->ctrl.rd_bit_order) {
+    MSB_32_SET(data, data);
+  }
+  return data;
 }
 
-void spiWriteNL(spi_t * spi, const void * data_in, uint32_t len){
-    size_t longs = len >> 2;
-    if(len & 3){
-        longs++;
+void spiWriteNL(spi_t *spi, const void *data_in, uint32_t len) {
+  if (!spi) {
+    return;
+  }
+  size_t longs = len >> 2;
+  if (len & 3) {
+    longs++;
+  }
+  uint32_t *data = (uint32_t *)data_in;
+  size_t c_len = 0, c_longs = 0;
+
+  while (len) {
+    c_len = (len > 64) ? 64 : len;
+    c_longs = (longs > 16) ? 16 : longs;
+
+    spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len * 8) - 1;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+    spi->dev->miso_dlen.usr_miso_dbitlen = 0;
+#endif
+    for (size_t i = 0; i < c_longs; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+      spi->dev->data_buf[i].val = data[i];
+#else
+      spi->dev->data_buf[i] = data[i];
+#endif
     }
-    uint32_t * data = (uint32_t*)data_in;
-    size_t c_len = 0, c_longs = 0;
-
-    while(len){
-        c_len = (len>64)?64:len;
-        c_longs = (longs > 16)?16:longs;
-
-        spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len*8)-1;
-        spi->dev->miso_dlen.usr_miso_dbitlen = 0;
-        for (int i=0; i<c_longs; i++) {
-            spi->dev->data_buf[i] = data[i];
-        }
-        spi->dev->cmd.usr = 1;
-        while(spi->dev->cmd.usr);
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+    spi->dev->cmd.update = 1;
+    while (spi->dev->cmd.update);
+#endif
+    spi->dev->cmd.usr = 1;
+    while (spi->dev->cmd.usr);
 
-        data += c_longs;
-        longs -= c_longs;
-        len -= c_len;
-    }
+    data += c_longs;
+    longs -= c_longs;
+    len -= c_len;
+  }
 }
 
-void spiTransferBytesNL(spi_t * spi, const void * data_in, uint8_t * data_out, uint32_t len){
-    if(!spi) {
-        return;
-    }
-    size_t longs = len >> 2;
-    if(len & 3){
-        longs++;
+void spiTransferBytesNL(spi_t *spi, const void *data_in, uint8_t *data_out, uint32_t len) {
+  if (!spi) {
+    return;
+  }
+  size_t longs = len >> 2;
+  if (len & 3) {
+    longs++;
+  }
+  uint32_t *data = (uint32_t *)data_in;
+  uint32_t *result = (uint32_t *)data_out;
+  size_t c_len = 0, c_longs = 0;
+
+  while (len) {
+    c_len = (len > 64) ? 64 : len;
+    c_longs = (longs > 16) ? 16 : longs;
+
+    spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len * 8) - 1;
+    spi->dev->miso_dlen.usr_miso_dbitlen = (c_len * 8) - 1;
+    if (data) {
+      for (size_t i = 0; i < c_longs; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+        spi->dev->data_buf[i].val = data[i];
+#else
+        spi->dev->data_buf[i] = data[i];
+#endif
+      }
+    } else {
+      for (size_t i = 0; i < c_longs; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+        spi->dev->data_buf[i].val = 0xFFFFFFFF;
+#else
+        spi->dev->data_buf[i] = 0xFFFFFFFF;
+#endif
+      }
     }
-    uint32_t * data = (uint32_t*)data_in;
-    uint32_t * result = (uint32_t*)data_out;
-    size_t c_len = 0, c_longs = 0;
-
-    while(len){
-        c_len = (len>64)?64:len;
-        c_longs = (longs > 16)?16:longs;
-
-        spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len*8)-1;
-        spi->dev->miso_dlen.usr_miso_dbitlen = (c_len*8)-1;
-        if(data){
-            for (int i=0; i<c_longs; i++) {
-                spi->dev->data_buf[i] = data[i];
-            }
-        } else {
-            for (int i=0; i<c_longs; i++) {
-                spi->dev->data_buf[i] = 0xFFFFFFFF;
-            }
-        }
-        spi->dev->cmd.usr = 1;
-        while(spi->dev->cmd.usr);
-        if(result){
-            for (int i=0; i<c_longs; i++) {
-                result[i] = spi->dev->data_buf[i];
-            }
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+    spi->dev->cmd.update = 1;
+    while (spi->dev->cmd.update);
+#endif
+    spi->dev->cmd.usr = 1;
+    while (spi->dev->cmd.usr);
+    if (result) {
+      if (c_len & 3) {
+        for (size_t i = 0; i < (c_longs - 1); i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+          result[i] = spi->dev->data_buf[i].val;
+#else
+          result[i] = spi->dev->data_buf[i];
+#endif
         }
-        if(data){
-            data += c_longs;
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+        uint32_t last_data = spi->dev->data_buf[c_longs - 1].val;
+#else
+        uint32_t last_data = spi->dev->data_buf[c_longs - 1];
+#endif
+        uint8_t *last_out8 = (uint8_t *)&result[c_longs - 1];
+        uint8_t *last_data8 = (uint8_t *)&last_data;
+        for (size_t i = 0; i < (c_len & 3); i++) {
+          last_out8[i] = last_data8[i];
         }
-        if(result){
-            result += c_longs;
+      } else {
+        for (size_t i = 0; i < c_longs; i++) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+          result[i] = spi->dev->data_buf[i].val;
+#else
+          result[i] = spi->dev->data_buf[i];
+#endif
         }
-        longs -= c_longs;
-        len -= c_len;
+      }
+    }
+    if (data) {
+      data += c_longs;
     }
+    if (result) {
+      result += c_longs;
+    }
+    longs -= c_longs;
+    len -= c_len;
+  }
 }
 
-void spiTransferBitsNL(spi_t * spi, uint32_t data, uint32_t * out, uint8_t bits)
-{
-    if(!spi) {
-        return;
+void spiTransferBitsNL(spi_t *spi, uint32_t data, uint32_t *out, uint8_t bits) {
+  if (!spi) {
+    return;
+  }
+
+  if (bits > 32) {
+    bits = 32;
+  }
+  uint32_t bytes = (bits + 7) / 8;  //64 max
+  uint32_t mask = (((uint64_t)1 << bits) - 1) & 0xFFFFFFFF;
+  data = data & mask;
+  if (!spi->dev->ctrl.wr_bit_order) {
+    if (bytes == 2) {
+      MSB_16_SET(data, data);
+    } else if (bytes == 3) {
+      MSB_24_SET(data, data);
+    } else {
+      MSB_32_SET(data, data);
     }
+  }
 
-    if(bits > 32) {
-        bits = 32;
-    }
-    uint32_t bytes = (bits + 7) / 8;//64 max
-    uint32_t mask = (((uint64_t)1 << bits) - 1) & 0xFFFFFFFF;
-    data = data & mask;
-    if(!spi->dev->ctrl.wr_bit_order){
-        if(bytes == 2) {
-            MSB_16_SET(data, data);
-        } else if(bytes == 3) {
-            MSB_24_SET(data, data);
+  spi->dev->mosi_dlen.usr_mosi_dbitlen = (bits - 1);
+  spi->dev->miso_dlen.usr_miso_dbitlen = (bits - 1);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  spi->dev->data_buf[0].val = data;
+#else
+  spi->dev->data_buf[0] = data;
+#endif
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+  spi->dev->cmd.update = 1;
+  while (spi->dev->cmd.update);
+#endif
+  spi->dev->cmd.usr = 1;
+  while (spi->dev->cmd.usr);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  data = spi->dev->data_buf[0].val;
+#else
+  data = spi->dev->data_buf[0];
+#endif
+  if (out) {
+    *out = data;
+    if (!spi->dev->ctrl.rd_bit_order) {
+      if (bytes == 2) {
+        MSB_16_SET(*out, data);
+      } else if (bytes == 3) {
+        MSB_24_SET(*out, data);
+      } else {
+        MSB_32_SET(*out, data);
+      }
+    }
+  }
+}
+
+void ARDUINO_ISR_ATTR spiWritePixelsNL(spi_t *spi, const void *data_in, uint32_t len) {
+  size_t longs = len >> 2;
+  if (len & 3) {
+    longs++;
+  }
+  bool msb = !spi->dev->ctrl.wr_bit_order;
+  uint32_t *data = (uint32_t *)data_in;
+  size_t c_len = 0, c_longs = 0, l_bytes = 0;
+
+  while (len) {
+    c_len = (len > 64) ? 64 : len;
+    c_longs = (longs > 16) ? 16 : longs;
+    l_bytes = (c_len & 3);
+
+    spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len * 8) - 1;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32
+    spi->dev->miso_dlen.usr_miso_dbitlen = 0;
+#endif
+    for (size_t i = 0; i < c_longs; i++) {
+      if (msb) {
+        if (l_bytes && i == (c_longs - 1)) {
+          if (l_bytes == 2) {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+            MSB_16_SET(spi->dev->data_buf[i].val, data[i]);
+#else
+            MSB_16_SET(spi->dev->data_buf[i], data[i]);
+#endif
+          } else {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+            spi->dev->data_buf[i].val = data[i] & 0xFF;
+#else
+            spi->dev->data_buf[i] = data[i] & 0xFF;
+#endif
+          }
         } else {
-            MSB_32_SET(data, data);
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+          MSB_PIX_SET(spi->dev->data_buf[i].val, data[i]);
+#else
+          MSB_PIX_SET(spi->dev->data_buf[i], data[i]);
+#endif
         }
+      } else {
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+        spi->dev->data_buf[i].val = data[i];
+#else
+        spi->dev->data_buf[i] = data[i];
+#endif
+      }
     }
-
-    spi->dev->mosi_dlen.usr_mosi_dbitlen = (bits - 1);
-    spi->dev->miso_dlen.usr_miso_dbitlen = (bits - 1);
-    spi->dev->data_buf[0] = data;
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+    spi->dev->cmd.update = 1;
+    while (spi->dev->cmd.update);
+#endif
     spi->dev->cmd.usr = 1;
-    while(spi->dev->cmd.usr);
-    data = spi->dev->data_buf[0];
-    if(out) {
-        *out = data;
-        if(!spi->dev->ctrl.rd_bit_order){
-            if(bytes == 2) {
-                MSB_16_SET(*out, data);
-            } else if(bytes == 3) {
-                MSB_24_SET(*out, data);
-            } else {
-                MSB_32_SET(*out, data);
-            }
-        }
-    }
-}
+    while (spi->dev->cmd.usr);
 
-void IRAM_ATTR spiWritePixelsNL(spi_t * spi, const void * data_in, uint32_t len){
-    size_t longs = len >> 2;
-    if(len & 3){
-        longs++;
-    }
-    bool msb = !spi->dev->ctrl.wr_bit_order;
-    uint32_t * data = (uint32_t*)data_in;
-    size_t c_len = 0, c_longs = 0, l_bytes = 0;
-
-    while(len){
-        c_len = (len>64)?64:len;
-        c_longs = (longs > 16)?16:longs;
-        l_bytes = (c_len & 3);
-
-        spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len*8)-1;
-        spi->dev->miso_dlen.usr_miso_dbitlen = 0;
-        for (int i=0; i<c_longs; i++) {
-            if(msb){
-                if(l_bytes && i == (c_longs - 1)){
-                    if(l_bytes == 2){
-                        MSB_16_SET(spi->dev->data_buf[i], data[i]);
-                    } else {
-                        spi->dev->data_buf[i] = data[i] & 0xFF;
-                    }
-                } else {
-                    MSB_PIX_SET(spi->dev->data_buf[i], data[i]);
-                }
-            } else {
-                spi->dev->data_buf[i] = data[i];
-            }
-        }
-        spi->dev->cmd.usr = 1;
-        while(spi->dev->cmd.usr);
-
-        data += c_longs;
-        longs -= c_longs;
-        len -= c_len;
-    }
+    data += c_longs;
+    longs -= c_longs;
+    len -= c_len;
+  }
 }
 
-
-
 /*
  * Clock Calculators
  *
  * */
 
 typedef union {
-    uint32_t value;
-    struct {
-            uint32_t clkcnt_l:       6;                     /*it must be equal to spi_clkcnt_N.*/
-            uint32_t clkcnt_h:       6;                     /*it must be floor((spi_clkcnt_N+1)/2-1).*/
-            uint32_t clkcnt_n:       6;                     /*it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
-            uint32_t clkdiv_pre:    13;                     /*it is pre-divider of spi_clk.*/
-            uint32_t clk_equ_sysclk: 1;                     /*1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
-    };
+  uint32_t value;
+  struct {
+    uint32_t clkcnt_l : 6; /*it must be equal to spi_clkcnt_N.*/
+    uint32_t clkcnt_h : 6; /*it must be floor((spi_clkcnt_N+1)/2-1).*/
+    uint32_t clkcnt_n : 6; /*it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+    uint32_t clkdiv_pre : 4; /*it is pre-divider of spi_clk.*/
+    uint32_t reserved   : 9; /*reserved*/
+#else
+    uint32_t clkdiv_pre : 13; /*it is pre-divider of spi_clk.*/
+#endif
+    uint32_t clk_equ_sysclk : 1; /*1: spi_clk is equal to system 0: spi_clk is divided from system clock.*/
+  };
 } spiClk_t;
 
 #define ClkRegToFreq(reg) (apb_freq / (((reg)->clkdiv_pre + 1) * ((reg)->clkcnt_n + 1)))
 
-uint32_t spiClockDivToFrequency(uint32_t clockDiv)
-{
-    uint32_t apb_freq = getApbFrequency();
-    spiClk_t reg = { clockDiv };
-    return ClkRegToFreq(&reg);
+uint32_t spiClockDivToFrequency(uint32_t clockDiv) {
+  uint32_t apb_freq = getApbFrequency();
+  spiClk_t reg = {clockDiv};
+  return ClkRegToFreq(&reg);
 }
 
-uint32_t spiFrequencyToClockDiv(uint32_t freq)
-{
-    uint32_t apb_freq = getApbFrequency();
+uint32_t spiFrequencyToClockDiv(uint32_t freq) {
+  uint32_t apb_freq = getApbFrequency();
 
-    if(freq >= apb_freq) {
-        return SPI_CLK_EQU_SYSCLK;
-    }
+  if (freq >= apb_freq) {
+    return SPI_CLK_EQU_SYSCLK;
+  }
 
-    const spiClk_t minFreqReg = { 0x7FFFF000 };
-    uint32_t minFreq = ClkRegToFreq((spiClk_t*) &minFreqReg);
-    if(freq < minFreq) {
-        return minFreqReg.value;
-    }
+  const spiClk_t minFreqReg = {0x7FFFF000};
+  uint32_t minFreq = ClkRegToFreq((spiClk_t *)&minFreqReg);
+  if (freq < minFreq) {
+    return minFreqReg.value;
+  }
 
-    uint8_t calN = 1;
-    spiClk_t bestReg = { 0 };
-    int32_t bestFreq = 0;
-
-    while(calN <= 0x3F) {
-        spiClk_t reg = { 0 };
-        int32_t calFreq;
-        int32_t calPre;
-        int8_t calPreVari = -2;
-
-        reg.clkcnt_n = calN;
-
-        while(calPreVari++ <= 1) {
-            calPre = (((apb_freq / (reg.clkcnt_n + 1)) / freq) - 1) + calPreVari;
-            if(calPre > 0x1FFF) {
-                reg.clkdiv_pre = 0x1FFF;
-            } else if(calPre <= 0) {
-                reg.clkdiv_pre = 0;
-            } else {
-                reg.clkdiv_pre = calPre;
-            }
-            reg.clkcnt_l = ((reg.clkcnt_n + 1) / 2);
-            calFreq = ClkRegToFreq(&reg);
-            if(calFreq == (int32_t) freq) {
-                memcpy(&bestReg, &reg, sizeof(bestReg));
-                break;
-            } else if(calFreq < (int32_t) freq) {
-                if(abs(freq - calFreq) < abs(freq - bestFreq)) {
-                    bestFreq = calFreq;
-                    memcpy(&bestReg, &reg, sizeof(bestReg));
-                }
-            }
-        }
-        if(calFreq == (int32_t) freq) {
-            break;
+  uint8_t calN = 1;
+  spiClk_t bestReg = {0};
+  uint32_t bestFreq = 0;
+
+  while (calN <= 0x3F) {
+    spiClk_t reg = {0};
+    uint32_t calFreq;
+    int32_t calPre;
+    int8_t calPreVari = -2;
+
+    reg.clkcnt_n = calN;
+
+    while (calPreVari++ <= 1) {
+      calPre = (((apb_freq / (reg.clkcnt_n + 1)) / freq) - 1) + calPreVari;
+#if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2)
+      if (calPre > 0xF) {
+        reg.clkdiv_pre = 0xF;
+#else
+      if (calPre > 0x1FFF) {
+        reg.clkdiv_pre = 0x1FFF;
+#endif
+      } else if (calPre <= 0) {
+        reg.clkdiv_pre = 0;
+      } else {
+        reg.clkdiv_pre = calPre;
+      }
+      reg.clkcnt_l = ((reg.clkcnt_n + 1) / 2);
+      calFreq = ClkRegToFreq(&reg);
+      if (calFreq == freq) {
+        memcpy(&bestReg, &reg, sizeof(bestReg));
+        break;
+      } else if (calFreq < freq) {
+        if ((freq - calFreq) < (freq - bestFreq)) {
+          bestFreq = calFreq;
+          memcpy(&bestReg, &reg, sizeof(bestReg));
         }
-        calN++;
+      }
+    }
+    if (calFreq == (int32_t)freq) {
+      break;
     }
-    return bestReg.value;
+    calN++;
+  }
+  return bestReg.value;
 }
 
+#endif /* SOC_GPSPI_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-spi.h b/cores/esp32/esp32-hal-spi.h
index 65d56b2e018..b77abff7854 100644
--- a/cores/esp32/esp32-hal-spi.h
+++ b/cores/esp32/esp32-hal-spi.h
@@ -15,38 +15,52 @@
 #ifndef MAIN_ESP32_HAL_SPI_H_
 #define MAIN_ESP32_HAL_SPI_H_
 
+#include "soc/soc_caps.h"
+#if SOC_GPSPI_SUPPORTED
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include "sdkconfig.h"
 #include <stdint.h>
 #include <stdbool.h>
 
 #define SPI_HAS_TRANSACTION
 
-#define FSPI  1 //SPI bus attached to the flash (can use the same data lines but different SS)
-#define HSPI  2 //SPI bus normally mapped to pins 12 - 15, but can be matrixed to any pins
-#define VSPI  3 //SPI bus normally attached to pins 5, 18, 19 and 23, but can be matrixed to any pins
+#ifdef CONFIG_IDF_TARGET_ESP32S2
+#define FSPI 1  //SPI 1 bus. ESP32S2: for external memory only (can use the same data lines but different SS)
+#define HSPI 2  //SPI 2 bus. ESP32S2: external memory or device  - it can be matrixed to any pins
+#define SPI2 2  // Another name for ESP32S2 SPI 2
+#define SPI3 3  //SPI 3 bus. ESP32S2: device only - it can be matrixed to any pins
+#elif CONFIG_IDF_TARGET_ESP32
+#define FSPI 1  //SPI 1 bus attached to the flash (can use the same data lines but different SS)
+#define HSPI 2  //SPI 2 bus normally mapped to pins 12 - 15, but can be matrixed to any pins
+#define VSPI 3  //SPI 3 bus normally attached to pins 5, 18, 19 and 23, but can be matrixed to any pins
+#else
+#define FSPI 0
+#define HSPI 1
+#endif
 
 // This defines are not representing the real Divider of the ESP32
 // the Defines match to an AVR Arduino on 16MHz for better compatibility
-#define SPI_CLOCK_DIV2    0x00101001 //8 MHz
-#define SPI_CLOCK_DIV4    0x00241001 //4 MHz
-#define SPI_CLOCK_DIV8    0x004c1001 //2 MHz
-#define SPI_CLOCK_DIV16   0x009c1001 //1 MHz
-#define SPI_CLOCK_DIV32   0x013c1001 //500 KHz
-#define SPI_CLOCK_DIV64   0x027c1001 //250 KHz
-#define SPI_CLOCK_DIV128  0x04fc1001 //125 KHz
+#define SPI_CLOCK_DIV2   0x00101001  //8 MHz
+#define SPI_CLOCK_DIV4   0x00241001  //4 MHz
+#define SPI_CLOCK_DIV8   0x004c1001  //2 MHz
+#define SPI_CLOCK_DIV16  0x009c1001  //1 MHz
+#define SPI_CLOCK_DIV32  0x013c1001  //500 KHz
+#define SPI_CLOCK_DIV64  0x027c1001  //250 KHz
+#define SPI_CLOCK_DIV128 0x04fc1001  //125 KHz
 
 #define SPI_MODE0 0
 #define SPI_MODE1 1
 #define SPI_MODE2 2
 #define SPI_MODE3 3
 
-#define SPI_CS0 0
-#define SPI_CS1 1
-#define SPI_CS2 2
-#define SPI_CS_MASK_ALL 0x7
+#define SPI_SS0         0
+#define SPI_SS1         1
+#define SPI_SS2         2
+#define SPI_SS_MASK_ALL 0x7
 
 #define SPI_LSBFIRST 0
 #define SPI_MSBFIRST 1
@@ -54,79 +68,78 @@ extern "C" {
 struct spi_struct_t;
 typedef struct spi_struct_t spi_t;
 
-spi_t * spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder);
-void spiStopBus(spi_t * spi);
+spi_t *spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder);
+void spiStopBus(spi_t *spi);
 
 //Attach/Detach Signal Pins
-void spiAttachSCK(spi_t * spi, int8_t sck);
-void spiAttachMISO(spi_t * spi, int8_t miso);
-void spiAttachMOSI(spi_t * spi, int8_t mosi);
-void spiDetachSCK(spi_t * spi, int8_t sck);
-void spiDetachMISO(spi_t * spi, int8_t miso);
-void spiDetachMOSI(spi_t * spi, int8_t mosi);
-
-//Attach/Detach SS pin to SPI_CSx signal
-void spiAttachSS(spi_t * spi, uint8_t cs_num, int8_t ss);
-void spiDetachSS(spi_t * spi, int8_t ss);
+bool spiAttachSCK(spi_t *spi, int8_t sck);
+bool spiAttachMISO(spi_t *spi, int8_t miso);
+bool spiAttachMOSI(spi_t *spi, int8_t mosi);
+bool spiDetachSCK(spi_t *spi);
+bool spiDetachMISO(spi_t *spi);
+bool spiDetachMOSI(spi_t *spi);
 
-//Enable/Disable SPI_CSx pins
-void spiEnableSSPins(spi_t * spi, uint8_t cs_mask);
-void spiDisableSSPins(spi_t * spi, uint8_t cs_mask);
+//Attach/Detach SS pin to SPI_SSx signal
+bool spiAttachSS(spi_t *spi, uint8_t ss_num, int8_t ss);
+bool spiDetachSS(spi_t *spi);
 
-//Enable/Disable hardware control of SPI_CSx pins
-void spiSSEnable(spi_t * spi);
-void spiSSDisable(spi_t * spi);
+//Enable/Disable SPI_SSx pins
+void spiEnableSSPins(spi_t *spi, uint8_t ss_mask);
+void spiDisableSSPins(spi_t *spi, uint8_t ss_mask);
 
-//Activate enabled SPI_CSx pins
-void spiSSSet(spi_t * spi);
-//Deactivate enabled SPI_CSx pins
-void spiSSClear(spi_t * spi);
+//Enable/Disable hardware control of SPI_SSx pins
+void spiSSEnable(spi_t *spi);
+void spiSSDisable(spi_t *spi);
 
-void spiWaitReady(spi_t * spi);
+//Activate enabled SPI_SSx pins
+void spiSSSet(spi_t *spi);
+//Deactivate enabled SPI_SSx pins
+void spiSSClear(spi_t *spi);
 
-uint32_t spiGetClockDiv(spi_t * spi);
-uint8_t spiGetDataMode(spi_t * spi);
-uint8_t spiGetBitOrder(spi_t * spi);
+void spiWaitReady(spi_t *spi);
 
+uint32_t spiGetClockDiv(spi_t *spi);
+uint8_t spiGetDataMode(spi_t *spi);
+uint8_t spiGetBitOrder(spi_t *spi);
 
 /*
  * Non transaction based lock methods (each locks and unlocks when called)
  * */
-void spiSetClockDiv(spi_t * spi, uint32_t clockDiv);
-void spiSetDataMode(spi_t * spi, uint8_t dataMode);
-void spiSetBitOrder(spi_t * spi, uint8_t bitOrder);
-
-void spiWrite(spi_t * spi, const uint32_t *data, uint8_t len);
-void spiWriteByte(spi_t * spi, uint8_t data);
-void spiWriteWord(spi_t * spi, uint16_t data);
-void spiWriteLong(spi_t * spi, uint32_t data);
-
-void spiTransfer(spi_t * spi, uint32_t *out, uint8_t len);
-uint8_t spiTransferByte(spi_t * spi, uint8_t data);
-uint16_t spiTransferWord(spi_t * spi, uint16_t data);
-uint32_t spiTransferLong(spi_t * spi, uint32_t data);
-void spiTransferBytes(spi_t * spi, const uint8_t * data, uint8_t * out, uint32_t size);
-void spiTransferBits(spi_t * spi, uint32_t data, uint32_t * out, uint8_t bits);
+void spiSetClockDiv(spi_t *spi, uint32_t clockDiv);
+void spiSetDataMode(spi_t *spi, uint8_t dataMode);
+void spiSetBitOrder(spi_t *spi, uint8_t bitOrder);
+
+void spiWrite(spi_t *spi, const uint32_t *data, uint8_t len);
+void spiWriteByte(spi_t *spi, uint8_t data);
+void spiWriteWord(spi_t *spi, uint16_t data);
+void spiWriteLong(spi_t *spi, uint32_t data);
+
+void spiTransfer(spi_t *spi, uint32_t *out, uint8_t len);
+uint8_t spiTransferByte(spi_t *spi, uint8_t data);
+uint16_t spiTransferWord(spi_t *spi, uint16_t data);
+uint32_t spiTransferLong(spi_t *spi, uint32_t data);
+void spiTransferBytes(spi_t *spi, const uint8_t *data, uint8_t *out, uint32_t size);
+void spiTransferBits(spi_t *spi, uint32_t data, uint32_t *out, uint8_t bits);
 
 /*
  * New (EXPERIMENTAL) Transaction lock based API (lock once until endTransaction)
  * */
-void spiTransaction(spi_t * spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder);
-void spiSimpleTransaction(spi_t * spi);
-void spiEndTransaction(spi_t * spi);
+void spiTransaction(spi_t *spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder);
+void spiSimpleTransaction(spi_t *spi);
+void spiEndTransaction(spi_t *spi);
 
-void spiWriteNL(spi_t * spi, const void * data_in, uint32_t len);
-void spiWriteByteNL(spi_t * spi, uint8_t data);
-void spiWriteShortNL(spi_t * spi, uint16_t data);
-void spiWriteLongNL(spi_t * spi, uint32_t data);
-void spiWritePixelsNL(spi_t * spi, const void * data_in, uint32_t len);
+void spiWriteNL(spi_t *spi, const void *data_in, uint32_t len);
+void spiWriteByteNL(spi_t *spi, uint8_t data);
+void spiWriteShortNL(spi_t *spi, uint16_t data);
+void spiWriteLongNL(spi_t *spi, uint32_t data);
+void spiWritePixelsNL(spi_t *spi, const void *data_in, uint32_t len);
 
 #define spiTransferNL(spi, data, len) spiTransferBytesNL(spi, data, data, len)
-uint8_t spiTransferByteNL(spi_t * spi, uint8_t data);
-uint16_t spiTransferShortNL(spi_t * spi, uint16_t data);
-uint32_t spiTransferLongNL(spi_t * spi, uint32_t data);
-void spiTransferBytesNL(spi_t * spi, const void * data_in, uint8_t * data_out, uint32_t len);
-void spiTransferBitsNL(spi_t * spi, uint32_t data_in, uint32_t * data_out, uint8_t bits);
+uint8_t spiTransferByteNL(spi_t *spi, uint8_t data);
+uint16_t spiTransferShortNL(spi_t *spi, uint16_t data);
+uint32_t spiTransferLongNL(spi_t *spi, uint32_t data);
+void spiTransferBytesNL(spi_t *spi, const void *data_in, uint8_t *data_out, uint32_t len);
+void spiTransferBitsNL(spi_t *spi, uint32_t data_in, uint32_t *data_out, uint8_t bits);
 
 /*
  * Helper functions to translate frequency to clock divider and back
@@ -138,4 +151,5 @@ uint32_t spiClockDivToFrequency(uint32_t freq);
 }
 #endif
 
+#endif /* SOC_GPSPI_SUPPORTED */
 #endif /* MAIN_ESP32_HAL_SPI_H_ */
diff --git a/cores/esp32/esp32-hal-time.c b/cores/esp32/esp32-hal-time.c
index 5647f1f50dc..074e999be71 100644
--- a/cores/esp32/esp32-hal-time.c
+++ b/cores/esp32/esp32-hal-time.c
@@ -14,81 +14,113 @@
 
 #include "esp32-hal.h"
 #include "lwip/apps/sntp.h"
-#include "tcpip_adapter.h"
+//#include "tcpip_adapter.h"
+#include "esp_netif.h"
 
-static void setTimeZone(long offset, int daylight)
-{
-    char cst[17] = {0};
-    char cdt[17] = "DST";
-    char tz[33] = {0};
+#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING
+#include "lwip/priv/tcpip_priv.h"
+#endif
 
-    if(offset % 3600){
-        sprintf(cst, "UTC%ld:%02u:%02u", offset / 3600, abs((offset % 3600) / 60), abs(offset % 60));
+static void setTimeZone(long offset, int daylight) {
+  char cst[17] = {0};
+  char cdt[17] = "DST";
+  char tz[33] = {0};
+
+  if (offset % 3600) {
+    sprintf(cst, "UTC%ld:%02u:%02u", offset / 3600, abs((offset % 3600) / 60), abs(offset % 60));
+  } else {
+    sprintf(cst, "UTC%ld", offset / 3600);
+  }
+  if (daylight != 3600) {
+    long tz_dst = offset - daylight;
+    if (tz_dst % 3600) {
+      sprintf(cdt, "DST%ld:%02u:%02u", tz_dst / 3600, abs((tz_dst % 3600) / 60), abs(tz_dst % 60));
     } else {
-        sprintf(cst, "UTC%ld", offset / 3600);
-    }
-    if(daylight != 3600){
-        long tz_dst = offset - daylight;
-        if(tz_dst % 3600){
-            sprintf(cdt, "DST%ld:%02u:%02u", tz_dst / 3600, abs((tz_dst % 3600) / 60), abs(tz_dst % 60));
-        } else {
-            sprintf(cdt, "DST%ld", tz_dst / 3600);
-        }
+      sprintf(cdt, "DST%ld", tz_dst / 3600);
     }
-    sprintf(tz, "%s%s", cst, cdt);
-    setenv("TZ", tz, 1);
-    tzset();
+  }
+  sprintf(tz, "%s%s", cst, cdt);
+  setenv("TZ", tz, 1);
+  tzset();
 }
 
 /*
  * configTime
  * Source: https://github.com/esp8266/Arduino/blob/master/cores/esp8266/time.c
  * */
-void configTime(long gmtOffset_sec, int daylightOffset_sec, const char* server1, const char* server2, const char* server3)
-{
-    tcpip_adapter_init();  // Should not hurt anything if already inited
-    if(sntp_enabled()){
-        sntp_stop();
-    }
-    sntp_setoperatingmode(SNTP_OPMODE_POLL);
-    sntp_setservername(0, (char*)server1);
-    sntp_setservername(1, (char*)server2);
-    sntp_setservername(2, (char*)server3);
-    sntp_init();
-    setTimeZone(-gmtOffset_sec, daylightOffset_sec);
+void configTime(long gmtOffset_sec, int daylightOffset_sec, const char *server1, const char *server2, const char *server3) {
+  //tcpip_adapter_init();  // Should not hurt anything if already inited
+  esp_netif_init();
+
+#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING
+  if (!sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) {
+    LOCK_TCPIP_CORE();
+  }
+#endif
+
+  if (sntp_enabled()) {
+    sntp_stop();
+  }
+
+  sntp_setoperatingmode(SNTP_OPMODE_POLL);
+  sntp_setservername(0, (char *)server1);
+  sntp_setservername(1, (char *)server2);
+  sntp_setservername(2, (char *)server3);
+  sntp_init();
+
+#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING
+  if (sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) {
+    UNLOCK_TCPIP_CORE();
+  }
+#endif
+
+  setTimeZone(-gmtOffset_sec, daylightOffset_sec);
 }
 
 /*
  * configTzTime
  * sntp setup using TZ environment variable
  * */
-void configTzTime(const char* tz, const char* server1, const char* server2, const char* server3)
-{
-    tcpip_adapter_init();  // Should not hurt anything if already inited
-    if(sntp_enabled()){
-        sntp_stop();
-    }
-    sntp_setoperatingmode(SNTP_OPMODE_POLL);
-    sntp_setservername(0, (char*)server1);
-    sntp_setservername(1, (char*)server2);
-    sntp_setservername(2, (char*)server3);
-    sntp_init();
-    setenv("TZ", tz, 1);
-    tzset();
+void configTzTime(const char *tz, const char *server1, const char *server2, const char *server3) {
+  //tcpip_adapter_init();  // Should not hurt anything if already inited
+  esp_netif_init();
+
+#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING
+  if (!sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) {
+    LOCK_TCPIP_CORE();
+  }
+#endif
+
+  if (sntp_enabled()) {
+    sntp_stop();
+  }
+
+  sntp_setoperatingmode(SNTP_OPMODE_POLL);
+  sntp_setservername(0, (char *)server1);
+  sntp_setservername(1, (char *)server2);
+  sntp_setservername(2, (char *)server3);
+  sntp_init();
+
+#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING
+  if (sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) {
+    UNLOCK_TCPIP_CORE();
+  }
+#endif
+
+  setenv("TZ", tz, 1);
+  tzset();
 }
 
-bool getLocalTime(struct tm * info, uint32_t ms)
-{
-    uint32_t start = millis();
-    time_t now;
-    while((millis()-start) <= ms) {
-        time(&now);
-        localtime_r(&now, info);
-        if(info->tm_year > (2016 - 1900)){
-            return true;
-        }
-        delay(10);
+bool getLocalTime(struct tm *info, uint32_t ms) {
+  uint32_t start = millis();
+  time_t now;
+  while ((millis() - start) <= ms) {
+    time(&now);
+    localtime_r(&now, info);
+    if (info->tm_year > (2016 - 1900)) {
+      return true;
     }
-    return false;
+    delay(10);
+  }
+  return false;
 }
-
diff --git a/cores/esp32/esp32-hal-timer.c b/cores/esp32/esp32-hal-timer.c
index ed804d4e348..ec6c507358e 100644
--- a/cores/esp32/esp32-hal-timer.c
+++ b/cores/esp32/esp32-hal-timer.c
@@ -13,296 +13,253 @@
 // limitations under the License.
 
 #include "esp32-hal-timer.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/xtensa_api.h"
-#include "freertos/task.h"
-#include "rom/ets_sys.h"
-#include "soc/timer_group_struct.h"
-#include "soc/dport_reg.h"
-#include "esp_attr.h"
-#include "esp_intr.h"
 
-#define HWTIMER_LOCK()      portENTER_CRITICAL(timer->lock)
-#define HWTIMER_UNLOCK()    portEXIT_CRITICAL(timer->lock)
-
-typedef struct {
-    union {
-        struct {
-            uint32_t reserved0:   10;
-            uint32_t alarm_en:     1;             /*When set  alarm is enabled*/
-            uint32_t level_int_en: 1;             /*When set  level type interrupt will be generated during alarm*/
-            uint32_t edge_int_en:  1;             /*When set  edge type interrupt will be generated during alarm*/
-            uint32_t divider:     16;             /*Timer clock (T0/1_clk) pre-scale value.*/
-            uint32_t autoreload:   1;             /*When set  timer 0/1 auto-reload at alarming is enabled*/
-            uint32_t increase:     1;             /*When set  timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/
-            uint32_t enable:       1;             /*When set  timer 0/1 time-base counter is enabled*/
-        };
-        uint32_t val;
-    } config;
-    uint32_t cnt_low;                             /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
-    uint32_t cnt_high;                            /*Register to store timer 0 time-base counter current value higher 32 bits.*/
-    uint32_t update;                              /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
-    uint32_t alarm_low;                           /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
-    uint32_t alarm_high;                          /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
-    uint32_t load_low;                            /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
-    uint32_t load_high;                           /*higher 32 bits of the value that will load into timer 0 time-base counter*/
-    uint32_t reload;                              /*Write any value will trigger timer 0 time-base counter reload*/
-} hw_timer_reg_t;
-
-typedef struct hw_timer_s {
-        hw_timer_reg_t * dev;
-        uint8_t num;
-        uint8_t group;
-        uint8_t timer;
-        portMUX_TYPE lock;
-} hw_timer_t;
-
-static hw_timer_t hw_timer[4] = {
-        {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE),0,0,0,portMUX_INITIALIZER_UNLOCKED},
-        {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x0024),1,0,1,portMUX_INITIALIZER_UNLOCKED},
-        {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1000),2,1,0,portMUX_INITIALIZER_UNLOCKED},
-        {(hw_timer_reg_t *)(DR_REG_TIMERGROUP0_BASE + 0x1024),3,1,1,portMUX_INITIALIZER_UNLOCKED}
-};
+#if SOC_GPTIMER_SUPPORTED
+#include "driver/gptimer.h"
+#if defined __has_include && __has_include("clk_tree.h")
+#include "clk_tree.h"
+#else
+#include "esp_clk_tree.h"
+#endif
 
 typedef void (*voidFuncPtr)(void);
-static voidFuncPtr __timerInterruptHandlers[4] = {0,0,0,0};
-
-void IRAM_ATTR __timerISR(void * arg){
-    uint32_t s0 = TIMERG0.int_st_timers.val;
-    uint32_t s1 = TIMERG1.int_st_timers.val;
-    TIMERG0.int_clr_timers.val = s0;
-    TIMERG1.int_clr_timers.val = s1;
-    uint8_t status = (s1 & 3) << 2 | (s0 & 3);
-    uint8_t i = 4;
-    //restart the timers that should autoreload
-    while(i--){
-        hw_timer_reg_t * dev = hw_timer[i].dev;
-        if((status & (1 << i)) && dev->config.autoreload){
-            dev->config.alarm_en = 1;
-        }
-    }
-    i = 4;
-    //call callbacks
-    while(i--){
-        if(__timerInterruptHandlers[i] && (status & (1 << i))){
-            __timerInterruptHandlers[i]();
-        }
-    }
-}
-
-uint64_t timerRead(hw_timer_t *timer){
-    timer->dev->update = 1;
-    uint64_t h = timer->dev->cnt_high;
-    uint64_t l = timer->dev->cnt_low;
-    return (h << 32) | l;
-}
+typedef void (*voidFuncPtrArg)(void *);
 
-uint64_t timerAlarmRead(hw_timer_t *timer){
-    uint64_t h = timer->dev->alarm_high;
-    uint64_t l = timer->dev->alarm_low;
-    return (h << 32) | l;
-}
-
-void timerWrite(hw_timer_t *timer, uint64_t val){
-    timer->dev->load_high = (uint32_t) (val >> 32);
-    timer->dev->load_low = (uint32_t) (val);
-    timer->dev->reload = 1;
-}
+typedef struct {
+  voidFuncPtr fn;
+  void *arg;
+} interrupt_config_t;
+
+struct timer_struct_t {
+  gptimer_handle_t timer_handle;
+  interrupt_config_t interrupt_handle;
+  bool timer_started;
+};
 
-void timerAlarmWrite(hw_timer_t *timer, uint64_t alarm_value, bool autoreload){
-    timer->dev->alarm_high = (uint32_t) (alarm_value >> 32);
-    timer->dev->alarm_low = (uint32_t) alarm_value;
-    timer->dev->config.autoreload = autoreload;
+inline uint64_t timerRead(hw_timer_t *timer) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return 0;
+  }
+  uint64_t value;
+  gptimer_get_raw_count(timer->timer_handle, &value);
+  return value;
 }
 
-void timerSetConfig(hw_timer_t *timer, uint32_t config){
-    timer->dev->config.val = config;
+void timerWrite(hw_timer_t *timer, uint64_t val) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return;
+  }
+  gptimer_set_raw_count(timer->timer_handle, val);
 }
 
-uint32_t timerGetConfig(hw_timer_t *timer){
-    return timer->dev->config.val;
+void timerAlarm(hw_timer_t *timer, uint64_t alarm_value, bool autoreload, uint64_t reload_count) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return;
+  }
+  esp_err_t err = ESP_OK;
+  gptimer_alarm_config_t alarm_cfg = {
+    .alarm_count = alarm_value,
+    .reload_count = reload_count,
+    .flags.auto_reload_on_alarm = autoreload,
+  };
+  err = gptimer_set_alarm_action(timer->timer_handle, &alarm_cfg);
+  if (err != ESP_OK) {
+    log_e("Timer Alarm Write failed, error num=%d", err);
+  }
 }
 
-void timerSetCountUp(hw_timer_t *timer, bool countUp){
-    timer->dev->config.increase = countUp;
+uint32_t timerGetFrequency(hw_timer_t *timer) {
+  if (timer == NULL) {
+    return 0;
+  }
+  uint32_t frequency;
+  gptimer_get_resolution(timer->timer_handle, &frequency);
+  return frequency;
 }
 
-bool timerGetCountUp(hw_timer_t *timer){
-    return timer->dev->config.increase;
+void timerStart(hw_timer_t *timer) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return;
+  }
+  gptimer_start(timer->timer_handle);
+  timer->timer_started = true;
 }
 
-void timerSetAutoReload(hw_timer_t *timer, bool autoreload){
-    timer->dev->config.autoreload = autoreload;
+void timerStop(hw_timer_t *timer) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return;
+  }
+  gptimer_stop(timer->timer_handle);
+  timer->timer_started = false;
 }
 
-bool timerGetAutoReload(hw_timer_t *timer){
-    return timer->dev->config.autoreload;
+void timerRestart(hw_timer_t *timer) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return;
+  }
+  gptimer_set_raw_count(timer->timer_handle, 0);
 }
 
-void timerSetDivider(hw_timer_t *timer, uint16_t divider){//2 to 65536
-    if(!divider){
-        divider = 0xFFFF;
-    } else if(divider == 1){
-        divider = 2;
+hw_timer_t *timerBegin(uint32_t frequency) {
+  esp_err_t err = ESP_OK;
+  uint32_t counter_src_hz = 0;
+  uint32_t divider = 0;
+  soc_periph_gptimer_clk_src_t clk;
+
+  soc_periph_gptimer_clk_src_t gptimer_clks[] = SOC_GPTIMER_CLKS;
+  for (size_t i = 0; i < sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+    clk = gptimer_clks[i];
+#if defined __has_include && __has_include("clk_tree.h")
+    clk_tree_src_get_freq_hz(clk, CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz);
+#else
+    esp_clk_tree_src_get_freq_hz(clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz);
+#endif
+    divider = counter_src_hz / frequency;
+    if ((divider >= 2) && (divider <= 65536)) {
+      break;
+    } else {
+      divider = 0;
     }
-    int timer_en = timer->dev->config.enable;
-    timer->dev->config.enable = 0;
-    timer->dev->config.divider = divider;
-    timer->dev->config.enable = timer_en;
-}
-
-uint16_t timerGetDivider(hw_timer_t *timer){
-    return timer->dev->config.divider;
-}
-
-void timerStart(hw_timer_t *timer){
-    timer->dev->config.enable = 1;
+  }
+
+  if (divider == 0) {
+    log_e("Resolution cannot be reached with any clock source, aborting!");
+    return NULL;
+  }
+
+  gptimer_config_t config = {
+    .clk_src = clk,
+    .direction = GPTIMER_COUNT_UP,
+    .resolution_hz = frequency,
+    .flags.intr_shared = true,
+  };
+
+  hw_timer_t *timer = malloc(sizeof(hw_timer_t));
+
+  err = gptimer_new_timer(&config, &timer->timer_handle);
+  if (err != ESP_OK) {
+    log_e("Failed to create a new GPTimer, error num=%d", err);
+    free(timer);
+    return NULL;
+  }
+  gptimer_enable(timer->timer_handle);
+  gptimer_start(timer->timer_handle);
+  timer->timer_started = true;
+  return timer;
 }
 
-void timerStop(hw_timer_t *timer){
-    timer->dev->config.enable = 0;
-}
-
-void timerRestart(hw_timer_t *timer){
-    timer->dev->config.enable = 0;
-    timer->dev->reload = 1;
-    timer->dev->config.enable = 1;
-}
-
-bool timerStarted(hw_timer_t *timer){
-    return timer->dev->config.enable;
-}
-
-void timerAlarmEnable(hw_timer_t *timer){
-    timer->dev->config.alarm_en = 1;
-}
-
-void timerAlarmDisable(hw_timer_t *timer){
-    timer->dev->config.alarm_en = 0;
-}
-
-bool timerAlarmEnabled(hw_timer_t *timer){
-    return timer->dev->config.alarm_en;
-}
-
-static void _on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb){
-    hw_timer_t * timer = (hw_timer_t *)arg;
-    if(ev_type == APB_BEFORE_CHANGE){
-        timer->dev->config.enable = 0;
-    } else {
-        old_apb /= 1000000;
-        new_apb /= 1000000;
-        timer->dev->config.divider = (new_apb * timer->dev->config.divider) / old_apb;
-        timer->dev->config.enable = 1;
+void timerEnd(hw_timer_t *timer) {
+  if (timer != NULL) {
+    esp_err_t err = ESP_OK;
+    if (timer->timer_started == true) {
+      gptimer_stop(timer->timer_handle);
     }
+    gptimer_disable(timer->timer_handle);
+    err = gptimer_del_timer(timer->timer_handle);
+    if (err != ESP_OK) {
+      log_e("Failed to destroy GPTimer, error num=%d", err);
+      return;
+    }
+    free(timer);
+  }
 }
 
-hw_timer_t * timerBegin(uint8_t num, uint16_t divider, bool countUp){
-    if(num > 3){
-        return NULL;
-    }
-    hw_timer_t * timer = &hw_timer[num];
-    if(timer->group) {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP1_CLK_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP1_RST);
-        TIMERG1.int_ena.val &= ~BIT(timer->timer);
+bool IRAM_ATTR timerFnWrapper(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *args) {
+  interrupt_config_t *isr = (interrupt_config_t *)args;
+  if (isr->fn) {
+    if (isr->arg) {
+      ((voidFuncPtrArg)isr->fn)(isr->arg);
     } else {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_TIMERGROUP_CLK_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERGROUP_RST);
-        TIMERG0.int_ena.val &= ~BIT(timer->timer);
+      isr->fn();
     }
-    timer->dev->config.enable = 0;
-    timerSetDivider(timer, divider);
-    timerSetCountUp(timer, countUp);
-    timerSetAutoReload(timer, false);
-    timerAttachInterrupt(timer, NULL, false);
-    timerWrite(timer, 0);
-    timer->dev->config.enable = 1;
-    addApbChangeCallback(timer, _on_apb_change);
-    return timer;
+  }
+  // some additional logic or handling may be required here to appropriately yield or not
+  return false;
 }
 
-void timerEnd(hw_timer_t *timer){
-    timer->dev->config.enable = 0;
-    timerAttachInterrupt(timer, NULL, false);
-    removeApbChangeCallback(timer, _on_apb_change);
+void timerAttachInterruptFunctionalArg(hw_timer_t *timer, void (*userFunc)(void *), void *arg) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return;
+  }
+  esp_err_t err = ESP_OK;
+  gptimer_event_callbacks_t cbs = {
+    .on_alarm = timerFnWrapper,
+  };
+
+  timer->interrupt_handle.fn = (voidFuncPtr)userFunc;
+  timer->interrupt_handle.arg = arg;
+
+  if (timer->timer_started == true) {
+    gptimer_stop(timer->timer_handle);
+  }
+  gptimer_disable(timer->timer_handle);
+  err = gptimer_register_event_callbacks(timer->timer_handle, &cbs, &timer->interrupt_handle);
+  if (err != ESP_OK) {
+    log_e("Timer Attach Interrupt failed, error num=%d", err);
+  }
+  gptimer_enable(timer->timer_handle);
+  if (timer->timer_started == true) {
+    gptimer_start(timer->timer_handle);
+  }
 }
 
-void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge){
-    static bool initialized = false;
-    static intr_handle_t intr_handle = NULL;
-    if(intr_handle){
-        esp_intr_disable(intr_handle);
-    }
-    if(fn == NULL){
-        timer->dev->config.level_int_en = 0;
-        timer->dev->config.edge_int_en = 0;
-        timer->dev->config.alarm_en = 0;
-        if(timer->num & 2){
-            TIMERG1.int_ena.val &= ~BIT(timer->timer);
-        } else {
-            TIMERG0.int_ena.val &= ~BIT(timer->timer);
-        }
-        __timerInterruptHandlers[timer->num] = NULL;
-    } else {
-        __timerInterruptHandlers[timer->num] = fn;
-        timer->dev->config.level_int_en = edge?0:1;//When set, an alarm will generate a level type interrupt.
-        timer->dev->config.edge_int_en = edge?1:0;//When set, an alarm will generate an edge type interrupt.
-        int intr_source = 0;
-        if(!edge){
-            if(timer->group){
-                intr_source = ETS_TG1_T0_LEVEL_INTR_SOURCE + timer->timer;
-            } else {
-                intr_source = ETS_TG0_T0_LEVEL_INTR_SOURCE + timer->timer;
-            }
-        } else {
-            if(timer->group){
-                intr_source = ETS_TG1_T0_EDGE_INTR_SOURCE + timer->timer;
-            } else {
-                intr_source = ETS_TG0_T0_EDGE_INTR_SOURCE + timer->timer;
-            }
-        }
-        if(!initialized){
-            initialized = true;
-            esp_intr_alloc(intr_source, (int)(ESP_INTR_FLAG_IRAM|ESP_INTR_FLAG_LOWMED|ESP_INTR_FLAG_EDGE), __timerISR, NULL, &intr_handle);
-        } else {
-            intr_matrix_set(esp_intr_get_cpu(intr_handle), intr_source, esp_intr_get_intno(intr_handle));
-        }
-        if(timer->group){
-            TIMERG1.int_ena.val |= BIT(timer->timer);
-        } else {
-            TIMERG0.int_ena.val |= BIT(timer->timer);
-        }
-    }
-    if(intr_handle){
-        esp_intr_enable(intr_handle);
-    }
+void timerAttachInterruptArg(hw_timer_t *timer, void (*userFunc)(void *), void *arg) {
+  timerAttachInterruptFunctionalArg(timer, userFunc, arg);
 }
 
-void timerDetachInterrupt(hw_timer_t *timer){
-    timerAttachInterrupt(timer, NULL, false);
+void timerAttachInterrupt(hw_timer_t *timer, voidFuncPtr userFunc) {
+  timerAttachInterruptFunctionalArg(timer, (voidFuncPtrArg)userFunc, NULL);
 }
 
-uint64_t timerReadMicros(hw_timer_t *timer){
-    uint64_t timer_val = timerRead(timer);
-    uint16_t div = timerGetDivider(timer);
-    return timer_val * div / (getApbFrequency() / 1000000);
+void timerDetachInterrupt(hw_timer_t *timer) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return;
+  }
+  esp_err_t err = ESP_OK;
+  err = gptimer_set_alarm_action(timer->timer_handle, NULL);
+  timer->interrupt_handle.fn = NULL;
+  timer->interrupt_handle.arg = NULL;
+  if (err != ESP_OK) {
+    log_e("Timer Detach Interrupt failed, error num=%d", err);
+  }
 }
 
-double timerReadSeconds(hw_timer_t *timer){
-    uint64_t timer_val = timerRead(timer);
-    uint16_t div = timerGetDivider(timer);
-    return (double)timer_val * div / getApbFrequency();
+uint64_t timerReadMicros(hw_timer_t *timer) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return 0;
+  }
+  uint64_t timer_val = timerRead(timer);
+  uint32_t frequency = timerGetFrequency(timer);
+  return timer_val * 1000000 / frequency;
 }
 
-uint64_t timerAlarmReadMicros(hw_timer_t *timer){
-    uint64_t timer_val = timerAlarmRead(timer);
-    uint16_t div = timerGetDivider(timer);
-    return timer_val * div / (getApbFrequency() / 1000000);
+uint64_t timerReadMillis(hw_timer_t *timer) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return 0;
+  }
+  uint64_t timer_val = timerRead(timer);
+  uint32_t frequency = timerGetFrequency(timer);
+  return timer_val * 1000 / frequency;
 }
 
-double timerAlarmReadSeconds(hw_timer_t *timer){
-    uint64_t timer_val = timerAlarmRead(timer);
-    uint16_t div = timerGetDivider(timer);
-    return (double)timer_val * div / getApbFrequency();
+double timerReadSeconds(hw_timer_t *timer) {
+  if (timer == NULL) {
+    log_e("Timer handle is NULL");
+    return 0;
+  }
+  uint64_t timer_val = timerRead(timer);
+  uint32_t frequency = timerGetFrequency(timer);
+  return (double)timer_val / frequency;
 }
+
+#endif /* SOC_GPTIMER_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-timer.h b/cores/esp32/esp32-hal-timer.h
index 7624fc5a9f6..59b88c99cba 100644
--- a/cores/esp32/esp32-hal-timer.h
+++ b/cores/esp32/esp32-hal-timer.h
@@ -17,56 +17,44 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#ifndef MAIN_ESP32_HAL_TIMER_H_
-#define MAIN_ESP32_HAL_TIMER_H_
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_GPTIMER_SUPPORTED
+
+#include "esp32-hal.h"
+#include "driver/gptimer_types.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "esp32-hal.h"
-#include "freertos/FreeRTOS.h"
-
-struct hw_timer_s;
-typedef struct hw_timer_s hw_timer_t;
+struct timer_struct_t;
+typedef struct timer_struct_t hw_timer_t;
 
-hw_timer_t * timerBegin(uint8_t timer, uint16_t divider, bool countUp);
+hw_timer_t *timerBegin(uint32_t frequency);
 void timerEnd(hw_timer_t *timer);
 
-void timerSetConfig(hw_timer_t *timer, uint32_t config);
-uint32_t timerGetConfig(hw_timer_t *timer);
-
-void timerAttachInterrupt(hw_timer_t *timer, void (*fn)(void), bool edge);
-void timerDetachInterrupt(hw_timer_t *timer);
-
 void timerStart(hw_timer_t *timer);
 void timerStop(hw_timer_t *timer);
 void timerRestart(hw_timer_t *timer);
 void timerWrite(hw_timer_t *timer, uint64_t val);
-void timerSetDivider(hw_timer_t *timer, uint16_t divider);
-void timerSetCountUp(hw_timer_t *timer, bool countUp);
-void timerSetAutoReload(hw_timer_t *timer, bool autoreload);
 
-bool timerStarted(hw_timer_t *timer);
 uint64_t timerRead(hw_timer_t *timer);
 uint64_t timerReadMicros(hw_timer_t *timer);
+uint64_t timerReadMillis(hw_timer_t *timer);
 double timerReadSeconds(hw_timer_t *timer);
-uint16_t timerGetDivider(hw_timer_t *timer);
-bool timerGetCountUp(hw_timer_t *timer);
-bool timerGetAutoReload(hw_timer_t *timer);
 
-void timerAlarmEnable(hw_timer_t *timer);
-void timerAlarmDisable(hw_timer_t *timer);
-void timerAlarmWrite(hw_timer_t *timer, uint64_t interruptAt, bool autoreload);
+uint32_t timerGetFrequency(hw_timer_t *timer);
 
-bool timerAlarmEnabled(hw_timer_t *timer);
-uint64_t timerAlarmRead(hw_timer_t *timer);
-uint64_t timerAlarmReadMicros(hw_timer_t *timer);
-double timerAlarmReadSeconds(hw_timer_t *timer);
+void timerAttachInterrupt(hw_timer_t *timer, void (*userFunc)(void));
+void timerAttachInterruptArg(hw_timer_t *timer, void (*userFunc)(void *), void *arg);
+void timerDetachInterrupt(hw_timer_t *timer);
 
+void timerAlarm(hw_timer_t *timer, uint64_t alarm_value, bool autoreload, uint64_t reload_count);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* MAIN_ESP32_HAL_TIMER_H_ */
+#endif /* SOC_GPTIMER_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-tinyusb.c b/cores/esp32/esp32-hal-tinyusb.c
new file mode 100644
index 00000000000..0991e08d27f
--- /dev/null
+++ b/cores/esp32/esp32-hal-tinyusb.c
@@ -0,0 +1,915 @@
+#include "soc/soc_caps.h"
+
+#if SOC_USB_OTG_SUPPORTED
+#include "sdkconfig.h"
+#if CONFIG_TINYUSB_ENABLED
+#include <stdlib.h>
+#include <stdbool.h>
+
+#include "esp_log.h"
+
+#include "soc/soc.h"
+#include "soc/efuse_reg.h"
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#include "soc/rtc_cntl_reg.h"
+#include "soc/usb_struct.h"
+#include "soc/usb_reg.h"
+#include "soc/usb_wrap_reg.h"
+#include "soc/usb_wrap_struct.h"
+#include "soc/usb_periph.h"
+#endif
+
+#include "soc/periph_defs.h"
+#include "soc/timer_group_struct.h"
+#include "soc/system_reg.h"
+
+#include "rom/gpio.h"
+
+#include "hal/gpio_ll.h"
+#include "hal/clk_gate_ll.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+
+#include "driver/gpio.h"
+
+#include "esp_rom_gpio.h"
+
+#include "esp32-hal.h"
+#include "esp32-hal-periman.h"
+#include "esp32-hal-tinyusb.h"
+
+#if CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/usb/usb_persist.h"
+#include "esp32s2/rom/usb/usb_dc.h"
+#include "esp32s2/rom/usb/chip_usb_dw_wrapper.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#if defined __has_include && __has_include("hal/usb_phy_ll.h")
+#include "hal/usb_phy_ll.h"
+#elif defined __has_include && __has_include("hal/usb_fsls_phy_ll.h")
+#include "hal/usb_fsls_phy_ll.h"
+#endif
+#include "hal/usb_serial_jtag_ll.h"
+#include "esp32s3/rom/usb/usb_persist.h"
+#include "esp32s3/rom/usb/usb_dc.h"
+#include "esp32s3/rom/usb/chip_usb_dw_wrapper.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#endif
+
+typedef enum {
+  TINYUSB_USBDEV_0,
+} tinyusb_usbdev_t;
+
+typedef char *tusb_desc_strarray_device_t[USB_STRING_DESCRIPTOR_ARRAY_SIZE];
+
+typedef struct {
+  bool external_phy;
+} tinyusb_config_t;
+
+#if __has_include("hal/usb_hal.h")
+
+#include "hal/usb_hal.h"
+
+static bool usb_otg_deinit(void *busptr) {
+  // Once USB OTG is initialized, its GPIOs are assigned and it shall never be deinited
+  // except when S3 swithicng usb from cdc to jtag while resetting to bootrom
+#if CONFIG_IDF_TARGET_ESP32S3
+  return true;
+#else
+  return false;
+#endif
+}
+
+static void configure_pins(usb_hal_context_t *usb) {
+  for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
+    if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
+      esp_rom_gpio_pad_select_gpio(iopin->pin);
+      if (iopin->is_output) {
+        esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
+      } else {
+        esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
+        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH)) {
+          gpio_ll_input_enable(&GPIO, iopin->pin);
+        }
+      }
+      esp_rom_gpio_pad_unhold(iopin->pin);
+    }
+  }
+  if (!usb->use_external_phy) {
+    gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
+    gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
+    if (perimanSetBusDeinit(ESP32_BUS_TYPE_USB_DM, usb_otg_deinit) && perimanSetBusDeinit(ESP32_BUS_TYPE_USB_DP, usb_otg_deinit)) {
+      // Bus Pointer is not used anyway - once the USB GPIOs are assigned, they can't be detached
+      perimanSetPinBus(USBPHY_DM_NUM, ESP32_BUS_TYPE_USB_DM, (void *)usb, -1, -1);
+      perimanSetPinBus(USBPHY_DP_NUM, ESP32_BUS_TYPE_USB_DP, (void *)usb, -1, -1);
+    } else {
+      log_e("USB OTG Pins can't be set into Peripheral Manager.");
+    }
+  }
+}
+
+esp_err_t init_usb_hal(bool external_phy) {
+  usb_hal_context_t hal = {.use_external_phy = external_phy};
+  usb_hal_init(&hal);
+  configure_pins(&hal);
+  return ESP_OK;
+}
+
+esp_err_t deinit_usb_hal() {
+  return ESP_OK;
+}
+
+#elif __has_include("esp_private/usb_phy.h")
+
+#include "esp_private/usb_phy.h"
+
+static usb_phy_handle_t phy_handle = NULL;
+
+esp_err_t init_usb_hal(bool external_phy) {
+  esp_err_t ret = ESP_OK;
+  usb_phy_config_t phy_config = {
+    .controller = USB_PHY_CTRL_OTG,
+    .target = USB_PHY_TARGET_INT,
+    .otg_mode = USB_OTG_MODE_DEVICE,
+#if CONFIG_IDF_TARGET_ESP32P4
+    .otg_speed = USB_PHY_SPEED_HIGH,
+#else
+    .otg_speed = USB_PHY_SPEED_FULL,
+#endif
+    .ext_io_conf = NULL,
+    .otg_io_conf = NULL,
+  };
+
+  ret = usb_new_phy(&phy_config, &phy_handle);
+  if (ret != ESP_OK) {
+    log_e("Failed to init USB PHY");
+  }
+  return ret;
+}
+
+esp_err_t deinit_usb_hal() {
+  esp_err_t ret = ESP_OK;
+  if (phy_handle) {
+    ret = usb_del_phy(phy_handle);
+    if (ret != ESP_OK) {
+      log_e("Failed to deinit USB PHY");
+    }
+  }
+  return ret;
+}
+
+#else
+
+#error No way to initialize USP PHY
+
+void init_usb_hal(bool external_phy) {
+  return ESP_OK;
+}
+
+void deinit_usb_hal() {
+  return ESP_OK;
+}
+#endif
+
+esp_err_t tinyusb_driver_install(const tinyusb_config_t *config) {
+  init_usb_hal(config->external_phy);
+  tusb_rhport_init_t tinit;
+  memset(&tinit, 0, sizeof(tusb_rhport_init_t));
+  tinit.role = TUSB_ROLE_DEVICE;
+#if CONFIG_IDF_TARGET_ESP32P4
+  tinit.speed = TUSB_SPEED_HIGH;
+  if (!tusb_init(1, &tinit)) {
+#else
+  tinit.speed = TUSB_SPEED_FULL;
+  if (!tusb_init(0, &tinit)) {
+#endif
+    log_e("Can't initialize the TinyUSB stack.");
+    return ESP_FAIL;
+  }
+  return ESP_OK;
+}
+
+typedef char tusb_str_t[127];
+
+static bool WEBUSB_ENABLED = false;
+
+static tusb_str_t WEBUSB_URL = "";
+static tusb_str_t USB_DEVICE_PRODUCT = "";
+static tusb_str_t USB_DEVICE_MANUFACTURER = "";
+static tusb_str_t USB_DEVICE_SERIAL = "";
+static tusb_str_t USB_DEVICE_LANGUAGE = "\x09\x04";  //English (0x0409)
+
+static uint8_t USB_DEVICE_ATTRIBUTES = 0;
+static uint16_t USB_DEVICE_POWER = 0;
+
+/*
+ * Device Descriptor
+ * */
+static tusb_desc_device_t tinyusb_device_descriptor = {
+  .bLength = sizeof(tusb_desc_device_t),
+  .bDescriptorType = TUSB_DESC_DEVICE,
+  .bcdUSB = 0,
+  .bDeviceClass = 0,
+  .bDeviceSubClass = 0,
+  .bDeviceProtocol = 0,
+  .bMaxPacketSize0 = CFG_TUD_ENDOINT0_SIZE,
+
+  .idVendor = 0,
+  .idProduct = 0,
+  .bcdDevice = 0,
+
+  .iManufacturer = 0x01,
+  .iProduct = 0x02,
+  .iSerialNumber = 0x03,
+
+  .bNumConfigurations = 0x01
+};
+
+/*
+ * String Descriptors
+ * */
+#define MAX_STRING_DESCRIPTORS 20
+static uint32_t tinyusb_string_descriptor_len = 4;
+static char *tinyusb_string_descriptor[MAX_STRING_DESCRIPTORS] = {
+  // array of pointer to string descriptors
+  USB_DEVICE_LANGUAGE,      // 0: is supported language
+  USB_DEVICE_MANUFACTURER,  // 1: Manufacturer
+  USB_DEVICE_PRODUCT,       // 2: Product
+  USB_DEVICE_SERIAL,        // 3: Serials, should use chip ID
+};
+
+/* Microsoft OS 2.0 registry property descriptor
+Per MS requirements https://msdn.microsoft.com/en-us/library/windows/hardware/hh450799(v=vs.85).aspx
+device should create DeviceInterfaceGUIDs. It can be done by driver and
+in case of real PnP solution device should expose MS "Microsoft OS 2.0
+registry property descriptor". Such descriptor can insert any record
+into Windows registry per device/configuration/interface. In our case it
+will insert "DeviceInterfaceGUIDs" multistring property.
+
+GUID is freshly generated and should be OK to use.
+
+https://developers.google.com/web/fundamentals/native-hardware/build-for-webusb/
+(Section Microsoft OS compatibility descriptors)
+ */
+
+#define MS_OS_20_DESC_LEN 0xB2
+
+static uint8_t const tinyusb_ms_os_20_descriptor[] = {
+  // Set header: length, type, windows version, total length
+  U16_TO_U8S_LE(0x000A), U16_TO_U8S_LE(MS_OS_20_SET_HEADER_DESCRIPTOR), U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(MS_OS_20_DESC_LEN),
+
+  // Configuration subset header: length, type, configuration index, reserved, configuration total length
+  U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_CONFIGURATION), 0, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A),
+
+  // Function Subset header: length, type, first interface, reserved, subset length
+  U16_TO_U8S_LE(0x0008), U16_TO_U8S_LE(MS_OS_20_SUBSET_HEADER_FUNCTION), 0, 0, U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x08),
+
+  // MS OS 2.0 Compatible ID descriptor: length, type, compatible ID, sub compatible ID
+  U16_TO_U8S_LE(0x0014), U16_TO_U8S_LE(MS_OS_20_FEATURE_COMPATBLE_ID), 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00,  // sub-compatible
+
+  // MS OS 2.0 Registry property descriptor: length, type
+  U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x08 - 0x08 - 0x14), U16_TO_U8S_LE(MS_OS_20_FEATURE_REG_PROPERTY), U16_TO_U8S_LE(0x0007),
+  U16_TO_U8S_LE(0x002A),  // wPropertyDataType, wPropertyNameLength and PropertyName "DeviceInterfaceGUIDs\0" in UTF-16
+  'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e',
+  0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, 0x00, 0x00,
+  U16_TO_U8S_LE(0x0050),  // wPropertyDataLength
+  //bPropertyData: “{975F44D9-0D08-43FD-8B3E-127CA8AFFF9D}”.
+  '{', 0x00, '9', 0x00, '7', 0x00, '5', 0x00, 'F', 0x00, '4', 0x00, '4', 0x00, 'D', 0x00, '9', 0x00, '-', 0x00, '0', 0x00, 'D', 0x00, '0', 0x00, '8', 0x00, '-',
+  0x00, '4', 0x00, '3', 0x00, 'F', 0x00, 'D', 0x00, '-', 0x00, '8', 0x00, 'B', 0x00, '3', 0x00, 'E', 0x00, '-', 0x00, '1', 0x00, '2', 0x00, '7', 0x00, 'C',
+  0x00, 'A', 0x00, '8', 0x00, 'A', 0x00, 'F', 0x00, 'F', 0x00, 'F', 0x00, '9', 0x00, 'D', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+TU_VERIFY_STATIC(sizeof(tinyusb_ms_os_20_descriptor) == MS_OS_20_DESC_LEN, "Incorrect size");
+
+/*
+ * BOS Descriptor (required for webUSB)
+ * */
+#define BOS_TOTAL_LEN (TUD_BOS_DESC_LEN + TUD_BOS_WEBUSB_DESC_LEN + TUD_BOS_MICROSOFT_OS_DESC_LEN)
+
+enum {
+  VENDOR_REQUEST_WEBUSB = 1,
+  VENDOR_REQUEST_MICROSOFT = 2
+};
+
+static uint8_t const tinyusb_bos_descriptor[] = {// total length, number of device caps
+                                                 TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 2),
+
+                                                 // Vendor Code, iLandingPage
+                                                 TUD_BOS_WEBUSB_DESCRIPTOR(VENDOR_REQUEST_WEBUSB, 1),
+
+                                                 // Microsoft OS 2.0 descriptor
+                                                 TUD_BOS_MS_OS_20_DESCRIPTOR(MS_OS_20_DESC_LEN, VENDOR_REQUEST_MICROSOFT)
+};
+
+/*
+ * URL Descriptor (required for webUSB)
+ * */
+typedef struct TU_ATTR_PACKED {
+  uint8_t bLength;
+  uint8_t bDescriptorType;
+  uint8_t bScheme;
+  char url[127];
+} tinyusb_desc_webusb_url_t;
+
+static tinyusb_desc_webusb_url_t tinyusb_url_descriptor = {
+  .bLength = 3,
+  .bDescriptorType = 3,  // WEBUSB URL type
+  .bScheme = 255,        // URL Scheme Prefix: 0: "http://", 1: "https://", 255: ""
+  .url = ""
+};
+
+/*
+ * Configuration Descriptor
+ * */
+
+static tinyusb_descriptor_cb_t tinyusb_loaded_interfaces_callbacks[USB_INTERFACE_MAX];
+static uint32_t tinyusb_loaded_interfaces_mask = 0;
+static uint8_t tinyusb_loaded_interfaces_num = 0;
+static uint16_t tinyusb_config_descriptor_len = 0;
+static uint8_t *tinyusb_config_descriptor = NULL;
+
+/*
+ * Endpoint Usage Tracking
+ * */
+typedef union {
+  struct {
+    uint32_t in  : 16;
+    uint32_t out : 16;
+  };
+  uint32_t val;
+} tinyusb_endpoints_usage_t;
+
+static tinyusb_endpoints_usage_t tinyusb_endpoints;
+
+/*
+ * TinyUSB Callbacks
+ * */
+
+/**
+ * @brief Invoked when received GET CONFIGURATION DESCRIPTOR.
+ */
+__attribute__((weak)) uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
+  //log_d("%u", index);
+  return tinyusb_config_descriptor;
+}
+
+/**
+ * @brief Invoked when received GET DEVICE DESCRIPTOR.
+ */
+__attribute__((weak)) uint8_t const *tud_descriptor_device_cb(void) {
+  //log_d("");
+  return (uint8_t const *)&tinyusb_device_descriptor;
+}
+
+/**
+ * @brief Invoked when received GET STRING DESCRIPTOR request.
+ */
+__attribute__((weak)) uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  //log_d("%u (0x%x)", index, langid);
+  static uint16_t _desc_str[127];
+  uint8_t chr_count;
+
+  if (index == 0) {
+    memcpy(&_desc_str[1], tinyusb_string_descriptor[0], 2);
+    chr_count = 1;
+  } else {
+    // Convert ASCII string into UTF-16
+    if (index >= tinyusb_string_descriptor_len) {
+      return NULL;
+    }
+    const char *str = tinyusb_string_descriptor[index];
+    // Cap at max char
+    chr_count = strlen(str);
+    if (chr_count > 126) {
+      chr_count = 126;
+    }
+    for (uint8_t i = 0; i < chr_count; i++) {
+      _desc_str[1 + i] = str[i];
+    }
+  }
+
+  // first byte is len, second byte is string type
+  _desc_str[0] = (TUSB_DESC_STRING << 8) | (2 * chr_count + 2);
+
+  return _desc_str;
+}
+
+/**
+ * @brief Invoked when received GET BOS DESCRIPTOR request.
+ */
+uint8_t const *tud_descriptor_bos_cb(void) {
+  //log_v("");
+  return tinyusb_bos_descriptor;
+}
+
+__attribute__((weak)) bool tinyusb_vendor_control_request_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) {
+  return false;
+}
+
+/**
+ * @brief Handle WebUSB and Vendor requests.
+ */
+bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) {
+  if (WEBUSB_ENABLED && (request->bRequest == VENDOR_REQUEST_WEBUSB || (request->bRequest == VENDOR_REQUEST_MICROSOFT && request->wIndex == 7))) {
+    // we only care for SETUP stage
+    if (stage == CONTROL_STAGE_SETUP) {
+      if (request->bRequest == VENDOR_REQUEST_WEBUSB) {
+        // match vendor request in BOS descriptor
+        // Get landing page url
+        tinyusb_url_descriptor.bLength = 3 + strlen(WEBUSB_URL);
+        snprintf(tinyusb_url_descriptor.url, 127, "%s", WEBUSB_URL);
+        return tud_control_xfer(rhport, request, (void *)&tinyusb_url_descriptor, tinyusb_url_descriptor.bLength);
+      }
+      // Get Microsoft OS 2.0 compatible descriptor
+      uint16_t total_len;
+      memcpy(&total_len, tinyusb_ms_os_20_descriptor + 8, 2);
+      return tud_control_xfer(rhport, request, (void *)tinyusb_ms_os_20_descriptor, total_len);
+    }
+    return true;
+  }
+  log_v("rhport: %u, stage: %u, type: 0x%x, request: 0x%x", rhport, stage, request->bmRequestType_bit.type, request->bRequest);
+  return tinyusb_vendor_control_request_cb(rhport, stage, request);
+}
+
+/*
+ * Required Callbacks
+ * */
+#if CFG_TUD_DFU
+__attribute__((weak)) uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state) {
+  return 0;
+}
+__attribute__((weak)) void tud_dfu_download_cb(uint8_t alt, uint16_t block_num, uint8_t const *data, uint16_t length) {}
+__attribute__((weak)) void tud_dfu_manifest_cb(uint8_t alt) {}
+#endif
+#if CFG_TUD_HID
+__attribute__((weak)) const uint8_t *tud_hid_descriptor_report_cb(uint8_t itf) {
+  return NULL;
+}
+__attribute__((weak)) uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t *buffer, uint16_t reqlen) {
+  return 0;
+}
+__attribute__((weak)) void tud_hid_set_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, const uint8_t *buffer, uint16_t bufsize) {}
+#endif
+#if CFG_TUD_MSC
+__attribute__((weak)) bool tud_msc_test_unit_ready_cb(uint8_t lun) {
+  return false;
+}
+__attribute__((weak)) void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) {}
+__attribute__((weak)) void tud_msc_capacity_cb(uint8_t lun, uint32_t *block_count, uint16_t *block_size) {}
+__attribute__((weak)) int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize) {
+  return -1;
+}
+__attribute__((weak)) int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize) {
+  return -1;
+}
+__attribute__((weak)) int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer, uint16_t bufsize) {
+  return -1;
+}
+__attribute__((weak)) bool tud_msc_is_writable_cb(uint8_t lun) {
+  return false;
+}
+#endif
+#if CFG_TUD_NCM
+__attribute__((weak)) bool tud_network_recv_cb(const uint8_t *src, uint16_t size) {
+  return false;
+}
+__attribute__((weak)) uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg) {
+  return 0;
+}
+__attribute__((weak)) void tud_network_init_cb(void) {}
+#endif
+
+/*
+ * Private API
+ * */
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+static bool usb_persist_enabled = false;
+static restart_type_t usb_persist_mode = RESTART_NO_PERSIST;
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32S3
+
+static void hw_cdc_reset_handler(void *arg) {
+  portBASE_TYPE xTaskWoken = 0;
+  uint32_t usbjtag_intr_status = usb_serial_jtag_ll_get_intsts_mask();
+  usb_serial_jtag_ll_clr_intsts_mask(usbjtag_intr_status);
+
+  if (usbjtag_intr_status & USB_SERIAL_JTAG_INTR_BUS_RESET) {
+    xSemaphoreGiveFromISR((SemaphoreHandle_t)arg, &xTaskWoken);
+  }
+
+  if (xTaskWoken == pdTRUE) {
+    portYIELD_FROM_ISR();
+  }
+}
+
+static void usb_switch_to_cdc_jtag() {
+  // Disable USB-OTG
+  deinit_usb_hal();
+  periph_ll_reset(PERIPH_USB_MODULE);
+  //periph_ll_enable_clk_clear_rst(PERIPH_USB_MODULE);
+  periph_ll_disable_clk_set_rst(PERIPH_USB_MODULE);
+
+  // Switch to hardware CDC+JTAG
+  CLEAR_PERI_REG_MASK(RTC_CNTL_USB_CONF_REG, (RTC_CNTL_SW_HW_USB_PHY_SEL | RTC_CNTL_SW_USB_PHY_SEL | RTC_CNTL_USB_PAD_ENABLE));
+
+  // Do not use external PHY
+  CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PHY_SEL);
+
+  // Release GPIO pins from  CDC+JTAG
+  CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
+
+  // Force the host to re-enumerate (BUS_RESET)
+  pinMode(USBPHY_DM_NUM, OUTPUT_OPEN_DRAIN);
+  pinMode(USBPHY_DP_NUM, OUTPUT_OPEN_DRAIN);
+  digitalWrite(USBPHY_DM_NUM, LOW);
+  digitalWrite(USBPHY_DP_NUM, LOW);
+
+// Initialize CDC+JTAG ISR to listen for BUS_RESET
+#if defined __has_include && __has_include("hal/usb_phy_ll.h")
+  usb_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
+#elif defined __has_include && __has_include("hal/usb_fsls_phy_ll.h")
+  usb_fsls_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
+#else
+  // usb_serial_jtag_ll_phy_set_defaults();
+  const usb_serial_jtag_pull_override_vals_t pull_conf = {.dp_pu = 1, .dm_pu = 0, .dp_pd = 0, .dm_pd = 0};
+  usb_serial_jtag_ll_phy_enable_pull_override(&pull_conf);
+  usb_serial_jtag_ll_phy_disable_pull_override();
+#endif
+  usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_LL_INTR_MASK);
+  usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_LL_INTR_MASK);
+  usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_BUS_RESET);
+  intr_handle_t intr_handle = NULL;
+  SemaphoreHandle_t reset_sem = xSemaphoreCreateBinary();
+  if (reset_sem) {
+    if (esp_intr_alloc(ETS_USB_SERIAL_JTAG_INTR_SOURCE, 0, hw_cdc_reset_handler, reset_sem, &intr_handle) != ESP_OK) {
+      vSemaphoreDelete(reset_sem);
+      reset_sem = NULL;
+      log_e("HW USB CDC failed to init interrupts");
+    }
+  } else {
+    log_e("reset_sem init failed");
+  }
+
+  // Connect GPIOs to integrated CDC+JTAG
+  SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
+
+  // Wait for BUS_RESET to give us back the semaphore
+  if (reset_sem) {
+    if (xSemaphoreTake(reset_sem, 1000 / portTICK_PERIOD_MS) != pdPASS) {
+      log_e("reset_sem timeout");
+    }
+    usb_serial_jtag_ll_disable_intr_mask(USB_SERIAL_JTAG_LL_INTR_MASK);
+    esp_intr_free(intr_handle);
+    vSemaphoreDelete(reset_sem);
+  }
+}
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+static void IRAM_ATTR usb_persist_shutdown_handler(void) {
+  if (usb_persist_mode != RESTART_NO_PERSIST) {
+    if (usb_persist_enabled) {
+      usb_dc_prepare_persist();
+    }
+    if (usb_persist_mode == RESTART_BOOTLOADER) {
+      //USB CDC Download
+      if (usb_persist_enabled) {
+        chip_usb_set_persist_flags(USBDC_PERSIST_ENA);
+#if CONFIG_IDF_TARGET_ESP32S2
+      } else {
+        periph_ll_reset(PERIPH_USB_MODULE);
+        periph_ll_enable_clk_clear_rst(PERIPH_USB_MODULE);
+#endif
+      }
+      REG_WRITE(RTC_CNTL_OPTION1_REG, RTC_CNTL_FORCE_DOWNLOAD_BOOT);
+    } else if (usb_persist_mode == RESTART_BOOTLOADER_DFU) {
+      //DFU Download
+#if CONFIG_IDF_TARGET_ESP32S2
+      // Reset USB Core
+      USB0.grstctl |= USB_CSFTRST;
+      while ((USB0.grstctl & USB_CSFTRST) == USB_CSFTRST) {}
+#endif
+      chip_usb_set_persist_flags(USBDC_BOOT_DFU);
+      REG_WRITE(RTC_CNTL_OPTION1_REG, RTC_CNTL_FORCE_DOWNLOAD_BOOT);
+    } else if (usb_persist_enabled) {
+      //USB Persist reboot
+      chip_usb_set_persist_flags(USBDC_PERSIST_ENA);
+    }
+  }
+}
+#endif
+
+void usb_persist_restart(restart_type_t mode) {
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+  if (mode < RESTART_TYPE_MAX && esp_register_shutdown_handler(usb_persist_shutdown_handler) == ESP_OK) {
+    usb_persist_mode = mode;
+#if CONFIG_IDF_TARGET_ESP32S3
+    if (mode == RESTART_BOOTLOADER) {
+      usb_switch_to_cdc_jtag();
+    }
+#endif
+    esp_restart();
+  }
+#endif
+}
+
+static bool tinyusb_reserve_in_endpoint(uint8_t endpoint) {
+  if (endpoint > CFG_TUD_NUM_EPS || (tinyusb_endpoints.in & BIT(endpoint)) != 0) {
+    return false;
+  }
+  tinyusb_endpoints.in |= BIT(endpoint);
+  return true;
+}
+
+static bool tinyusb_reserve_out_endpoint(uint8_t endpoint) {
+  if (endpoint > CFG_TUD_NUM_EPS || (tinyusb_endpoints.out & BIT(endpoint)) != 0) {
+    return false;
+  }
+  tinyusb_endpoints.out |= BIT(endpoint);
+  return true;
+}
+
+static bool tinyusb_has_available_fifos(void) {
+  uint8_t max_endpoints = CFG_TUD_NUM_IN_EPS - 1, active_endpoints = 0;
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+  if (tinyusb_loaded_interfaces_mask & BIT(USB_INTERFACE_CDC)) {
+    max_endpoints = CFG_TUD_NUM_IN_EPS;  //CDC endpoint 0x85 is actually not linked to FIFO and not used
+  }
+#endif
+  for (uint8_t i = 1; i <= CFG_TUD_NUM_EPS; i++) {
+    if ((tinyusb_endpoints.in & BIT(i)) != 0) {
+      active_endpoints++;
+    }
+  }
+
+  return active_endpoints < max_endpoints;
+}
+
+static uint16_t tinyusb_load_descriptor(tinyusb_interface_t interface, uint8_t *dst, uint8_t *itf) {
+  if (tinyusb_loaded_interfaces_callbacks[interface]) {
+    return tinyusb_loaded_interfaces_callbacks[interface](dst, itf);
+  }
+  return 0;
+}
+
+static bool tinyusb_load_enabled_interfaces() {
+  tinyusb_config_descriptor_len += TUD_CONFIG_DESC_LEN;
+  tinyusb_config_descriptor = (uint8_t *)malloc(tinyusb_config_descriptor_len);
+  if (tinyusb_config_descriptor == NULL) {
+    log_e("Descriptor Malloc Failed");
+    return false;
+  }
+  uint8_t *dst = tinyusb_config_descriptor + TUD_CONFIG_DESC_LEN;
+
+  for (int i = 0; i < USB_INTERFACE_MAX; i++) {
+    if (tinyusb_loaded_interfaces_mask & (1U << i)) {
+      uint16_t len = tinyusb_load_descriptor((tinyusb_interface_t)i, dst, &tinyusb_loaded_interfaces_num);
+      if (!len) {
+        log_e("Descriptor Load Failed");
+        return false;
+      } else {
+        dst += len;
+      }
+    }
+  }
+  uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB Device");
+  uint8_t descriptor[TUD_CONFIG_DESC_LEN] = {
+    //num configs, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, tinyusb_loaded_interfaces_num, str_index, tinyusb_config_descriptor_len, USB_DEVICE_ATTRIBUTES, USB_DEVICE_POWER)
+  };
+  memcpy(tinyusb_config_descriptor, descriptor, TUD_CONFIG_DESC_LEN);
+  if ((tinyusb_loaded_interfaces_mask == (BIT(USB_INTERFACE_CDC) | BIT(USB_INTERFACE_DFU))) || (tinyusb_loaded_interfaces_mask == BIT(USB_INTERFACE_CDC))) {
+    //usb_persist_enabled = true;
+    //log_d("USB Persist enabled");
+  }
+  log_d("Load Done: if_num: %u, descr_len: %u, if_mask: 0x%x", tinyusb_loaded_interfaces_num, tinyusb_config_descriptor_len, tinyusb_loaded_interfaces_mask);
+  return true;
+}
+
+static inline char nibble_to_hex_char(uint8_t b) {
+  if (b < 0xa) {
+    return '0' + b;
+  } else {
+    return 'a' + b - 0xa;
+  }
+}
+
+static void set_usb_serial_num(void) {
+  /* Get the MAC address */
+#if CONFIG_IDF_TARGET_ESP32P4
+  const uint32_t mac0 = REG_GET_FIELD(EFUSE_RD_MAC_SYS_0_REG, EFUSE_MAC_0);
+  const uint32_t mac1 = REG_GET_FIELD(EFUSE_RD_MAC_SYS_0_REG, EFUSE_MAC_1);
+#else
+  const uint32_t mac0 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_MAC_0);
+  const uint32_t mac1 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_1_REG, EFUSE_MAC_1);
+#endif
+  uint8_t mac_bytes[6];
+  memcpy(mac_bytes, &mac0, 4);
+  memcpy(mac_bytes + 4, &mac1, 2);
+
+  /* Convert to UTF16 string */
+  uint8_t *srl = (uint8_t *)USB_DEVICE_SERIAL;
+  for (int i = 0; i < 6; ++i) {
+    uint8_t b = mac_bytes[5 - i]; /* printing from the MSB */
+    if (i) {
+      *srl++ = ':';
+    }
+    *srl++ = nibble_to_hex_char(b >> 4);
+    *srl++ = nibble_to_hex_char(b & 0xf);
+  }
+  *srl++ = '\0';
+}
+
+static void tinyusb_apply_device_config(tinyusb_device_config_t *config) {
+  if (config->product_name) {
+    snprintf(USB_DEVICE_PRODUCT, 126, "%s", config->product_name);
+  }
+
+  if (config->manufacturer_name) {
+    snprintf(USB_DEVICE_MANUFACTURER, 126, "%s", config->manufacturer_name);
+  }
+
+  if (config->serial_number && config->serial_number[0]) {
+    snprintf(USB_DEVICE_SERIAL, 126, "%s", config->serial_number);
+  } else {
+    set_usb_serial_num();
+  }
+
+  if (config->webusb_url) {
+    snprintf(WEBUSB_URL, 126, "%s", config->webusb_url);
+  }
+
+  // Windows 10 will not recognize the CDC device if WebUSB is enabled and USB Class is not 2 (CDC)
+  if ((tinyusb_loaded_interfaces_mask & BIT(USB_INTERFACE_CDC)) && config->webusb_enabled && (config->usb_class != TUSB_CLASS_CDC)) {
+    config->usb_class = TUSB_CLASS_CDC;
+    config->usb_protocol = 0x00;
+  }
+
+  WEBUSB_ENABLED = config->webusb_enabled;
+  USB_DEVICE_ATTRIBUTES = config->usb_attributes;
+  USB_DEVICE_POWER = config->usb_power_ma;
+
+  tinyusb_device_descriptor.bcdUSB = config->usb_version;
+  tinyusb_device_descriptor.idVendor = config->vid;
+  tinyusb_device_descriptor.idProduct = config->pid;
+  tinyusb_device_descriptor.bcdDevice = config->fw_version;
+  tinyusb_device_descriptor.bDeviceClass = config->usb_class;
+  tinyusb_device_descriptor.bDeviceSubClass = config->usb_subclass;
+  tinyusb_device_descriptor.bDeviceProtocol = config->usb_protocol;
+}
+
+// USB Device Driver task
+// This top level thread processes all usb events and invokes callbacks
+static void usb_device_task(void *param) {
+  (void)param;
+  while (1) {
+    tud_task();  // RTOS forever loop
+  }
+}
+
+/*
+ * PUBLIC API
+ * */
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
+const char *tinyusb_interface_names[USB_INTERFACE_MAX] = {"MSC", "DFU", "HID", "VENDOR", "CDC", "CDC2", "MIDI", "CUSTOM"};
+#endif
+static bool tinyusb_is_initialized = false;
+
+esp_err_t tinyusb_enable_interface(tinyusb_interface_t interface, uint16_t descriptor_len, tinyusb_descriptor_cb_t cb) {
+  return tinyusb_enable_interface2(interface, descriptor_len, cb, false);
+}
+
+esp_err_t tinyusb_enable_interface2(tinyusb_interface_t interface, uint16_t descriptor_len, tinyusb_descriptor_cb_t cb, bool reserve_endpoints) {
+  if (tinyusb_is_initialized) {
+    log_e("TinyUSB has already started! Interface %s not enabled", (interface >= USB_INTERFACE_MAX) ? "" : tinyusb_interface_names[interface]);
+    return ESP_FAIL;
+  }
+  if ((interface >= USB_INTERFACE_MAX) || (tinyusb_loaded_interfaces_mask & (1U << interface))) {
+    log_e("Interface %s invalid or already enabled", (interface >= USB_INTERFACE_MAX) ? "" : tinyusb_interface_names[interface]);
+    return ESP_FAIL;
+  }
+  if (interface == USB_INTERFACE_HID && reserve_endpoints) {
+    // Some simple PC BIOS requires specific endpoint addresses for keyboard at boot
+    if (!tinyusb_reserve_out_endpoint(1) || !tinyusb_reserve_in_endpoint(1)) {
+      log_e("HID Reserve Endpoints Failed");
+      return ESP_FAIL;
+    }
+  }
+  if (interface == USB_INTERFACE_CDC) {
+    if (!tinyusb_reserve_out_endpoint(3) || !tinyusb_reserve_in_endpoint(4) || !tinyusb_reserve_in_endpoint(5)) {
+      log_e("CDC Reserve Endpoints Failed");
+      return ESP_FAIL;
+    }
+  }
+  tinyusb_loaded_interfaces_mask |= (1U << interface);
+  tinyusb_config_descriptor_len += descriptor_len;
+  tinyusb_loaded_interfaces_callbacks[interface] = cb;
+  log_d("Interface %s enabled", tinyusb_interface_names[interface]);
+  return ESP_OK;
+}
+
+esp_err_t tinyusb_init(tinyusb_device_config_t *config) {
+  if (tinyusb_is_initialized) {
+    return ESP_OK;
+  }
+  tinyusb_is_initialized = true;
+
+  //tinyusb_endpoints.val = 0;
+  tinyusb_apply_device_config(config);
+  if (!tinyusb_load_enabled_interfaces()) {
+    tinyusb_is_initialized = false;
+    return ESP_FAIL;
+  }
+
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+  bool usb_did_persist = (USB_WRAP.date.val == USBDC_PERSIST_ENA);
+
+  //if(usb_did_persist && usb_persist_enabled){
+  // Enable USB/IO_MUX peripheral reset, if coming from persistent reboot
+  REG_CLR_BIT(RTC_CNTL_USB_CONF_REG, RTC_CNTL_IO_MUX_RESET_DISABLE);
+  REG_CLR_BIT(RTC_CNTL_USB_CONF_REG, RTC_CNTL_USB_RESET_DISABLE);
+  //} else
+  if (!usb_did_persist || !usb_persist_enabled) {
+    // Reset USB module
+    periph_ll_reset(PERIPH_USB_MODULE);
+    periph_ll_enable_clk_clear_rst(PERIPH_USB_MODULE);
+  }
+#endif
+
+  tinyusb_config_t tusb_cfg = {
+    .external_phy = false  // In the most cases you need to use a `false` value
+  };
+  esp_err_t err = tinyusb_driver_install(&tusb_cfg);
+  if (err != ESP_OK) {
+    tinyusb_is_initialized = false;
+    return err;
+  }
+  xTaskCreate(usb_device_task, "usbd", 4096, NULL, configMAX_PRIORITIES - 1, NULL);
+  return err;
+}
+
+uint8_t tinyusb_add_string_descriptor(const char *str) {
+  if (str == NULL || tinyusb_string_descriptor_len >= MAX_STRING_DESCRIPTORS) {
+    return 0;
+  }
+  uint8_t index = tinyusb_string_descriptor_len;
+  tinyusb_string_descriptor[tinyusb_string_descriptor_len++] = (char *)str;
+  return index;
+}
+
+uint8_t tinyusb_get_free_duplex_endpoint(void) {
+  if (!tinyusb_has_available_fifos()) {
+    log_e("No available IN endpoints");
+    return 0;
+  }
+  for (uint8_t i = 1; i <= CFG_TUD_NUM_IN_EPS; i++) {
+    if ((tinyusb_endpoints.in & BIT(i)) == 0 && (tinyusb_endpoints.out & BIT(i)) == 0) {
+      tinyusb_endpoints.in |= BIT(i);
+      tinyusb_endpoints.out |= BIT(i);
+      return i;
+    }
+  }
+  log_e("No available duplex endpoints");
+  return 0;
+}
+
+uint8_t tinyusb_get_free_in_endpoint(void) {
+  if (!tinyusb_has_available_fifos()) {
+    log_e("No available IN endpoints");
+    return 0;
+  }
+  for (uint8_t i = 1; i <= CFG_TUD_NUM_IN_EPS; i++) {
+    if ((tinyusb_endpoints.in & BIT(i)) == 0 && (tinyusb_endpoints.out & BIT(i)) != 0) {
+      tinyusb_endpoints.in |= BIT(i);
+      return i;
+    }
+  }
+  for (uint8_t i = 1; i <= CFG_TUD_NUM_IN_EPS; i++) {
+    if ((tinyusb_endpoints.in & BIT(i)) == 0) {
+      tinyusb_endpoints.in |= BIT(i);
+      return i;
+    }
+  }
+  return 0;
+}
+
+uint8_t tinyusb_get_free_out_endpoint(void) {
+  for (uint8_t i = 1; i <= CFG_TUD_NUM_EPS; i++) {
+    if ((tinyusb_endpoints.out & BIT(i)) == 0 && (tinyusb_endpoints.in & BIT(i)) != 0) {
+      tinyusb_endpoints.out |= BIT(i);
+      return i;
+    }
+  }
+  for (uint8_t i = 1; i <= CFG_TUD_NUM_EPS; i++) {
+    if ((tinyusb_endpoints.out & BIT(i)) == 0) {
+      tinyusb_endpoints.out |= BIT(i);
+      return i;
+    }
+  }
+  return 0;
+}
+
+#endif /* CONFIG_TINYUSB_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-tinyusb.h b/cores/esp32/esp32-hal-tinyusb.h
new file mode 100644
index 00000000000..73210c4872b
--- /dev/null
+++ b/cores/esp32/esp32-hal-tinyusb.h
@@ -0,0 +1,118 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "esp32-hal.h"
+
+#if CONFIG_TINYUSB_ENABLED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "tusb.h"
+#include "tusb_option.h"
+#include "tusb_config.h"
+
+#define USB_ESPRESSIF_VID                0x303A
+#define USB_STRING_DESCRIPTOR_ARRAY_SIZE 10
+
+#ifndef CFG_TUD_ENDOINT_SIZE
+#if CONFIG_IDF_TARGET_ESP32P4
+#define CFG_TUD_ENDOINT_SIZE 512
+#else
+#define CFG_TUD_ENDOINT_SIZE 64
+#endif
+#endif
+#if CONFIG_IDF_TARGET_ESP32P4
+#define CFG_TUD_NUM_EPS    15
+#define CFG_TUD_NUM_IN_EPS 8
+#else
+#define CFG_TUD_NUM_EPS    6
+#define CFG_TUD_NUM_IN_EPS 5
+#endif
+
+typedef struct {
+  uint16_t vid;
+  uint16_t pid;
+  const char *product_name;
+  const char *manufacturer_name;
+  const char *serial_number;
+  uint16_t fw_version;
+
+  uint16_t usb_version;
+  uint8_t usb_class;
+  uint8_t usb_subclass;
+  uint8_t usb_protocol;
+  uint8_t usb_attributes;
+  uint16_t usb_power_ma;
+
+  bool webusb_enabled;
+  const char *webusb_url;
+} tinyusb_device_config_t;
+
+#define TINYUSB_CONFIG_DEFAULT()                                                                                                                               \
+  {                                                                                                                                                            \
+    .vid = USB_ESPRESSIF_VID, .pid = 0x0002, .product_name = CONFIG_TINYUSB_DESC_PRODUCT_STRING, .manufacturer_name = CONFIG_TINYUSB_DESC_MANUFACTURER_STRING, \
+    .serial_number = CONFIG_TINYUSB_DESC_SERIAL_STRING, .fw_version = CONFIG_TINYUSB_DESC_BCDDEVICE, .usb_version = 0x0200, .usb_class = TUSB_CLASS_MISC,      \
+    .usb_subclass = MISC_SUBCLASS_COMMON, .usb_protocol = MISC_PROTOCOL_IAD, .usb_attributes = TUSB_DESC_CONFIG_ATT_SELF_POWERED, .usb_power_ma = 500,         \
+    .webusb_enabled = false, .webusb_url = "espressif.github.io/arduino-esp32/webusb.html"                                                                     \
+  }
+
+esp_err_t tinyusb_init(tinyusb_device_config_t *config);
+
+/*
+ * USB Persistence API
+ * */
+typedef enum {
+  RESTART_NO_PERSIST,
+  RESTART_PERSIST,
+  RESTART_BOOTLOADER,
+  RESTART_BOOTLOADER_DFU,
+  RESTART_TYPE_MAX
+} restart_type_t;
+
+void usb_persist_restart(restart_type_t mode);
+
+// The following definitions and functions are to be used only by the drivers
+typedef enum {
+  USB_INTERFACE_MSC,
+  USB_INTERFACE_DFU,
+  USB_INTERFACE_HID,
+  USB_INTERFACE_VENDOR,
+  USB_INTERFACE_CDC,
+  USB_INTERFACE_CDC2,
+  USB_INTERFACE_MIDI,
+  USB_INTERFACE_CUSTOM,
+  USB_INTERFACE_MAX
+} tinyusb_interface_t;
+
+typedef uint16_t (*tinyusb_descriptor_cb_t)(uint8_t *dst, uint8_t *itf);
+
+esp_err_t tinyusb_enable_interface(tinyusb_interface_t interface, uint16_t descriptor_len, tinyusb_descriptor_cb_t cb);
+esp_err_t tinyusb_enable_interface2(tinyusb_interface_t interface, uint16_t descriptor_len, tinyusb_descriptor_cb_t cb, bool reserve_endpoints);
+uint8_t tinyusb_add_string_descriptor(const char *str);
+uint8_t tinyusb_get_free_duplex_endpoint(void);
+uint8_t tinyusb_get_free_in_endpoint(void);
+uint8_t tinyusb_get_free_out_endpoint(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CONFIG_TINYUSB_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-touch-ng.c b/cores/esp32/esp32-hal-touch-ng.c
new file mode 100644
index 00000000000..888a299ec0c
--- /dev/null
+++ b/cores/esp32/esp32-hal-touch-ng.c
@@ -0,0 +1,453 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include "soc/soc_caps.h"
+
+#if SOC_TOUCH_SENSOR_SUPPORTED
+#if SOC_TOUCH_SENSOR_VERSION == 3  // ESP32P4 for now
+
+#include "driver/touch_sens.h"
+#include "esp32-hal-touch-ng.h"
+#include "esp32-hal-periman.h"
+
+/*
+    Internal Private Touch Data Structure and Functions
+*/
+
+typedef void (*voidFuncPtr)(void);
+typedef void (*voidArgFuncPtr)(void *);
+
+typedef struct {
+  voidFuncPtr fn;
+  bool callWithArgs;
+  void *arg;
+  bool lastStatusIsPressed;
+} TouchInterruptHandle_t;
+
+static TouchInterruptHandle_t __touchInterruptHandlers[SOC_TOUCH_SENSOR_NUM] = {
+  0,
+};
+
+static uint8_t _sample_num = 1;
+static uint32_t _div_num = 1;
+static uint8_t _coarse_freq_tune = 1;
+static uint8_t _fine_freq_tune = 1;
+static uint8_t used_pads = 0;
+
+static uint32_t __touchSleepTime = 256;
+static float __touchMeasureTime = 32.0f;
+
+static touch_sensor_config_t sensor_config;
+
+static bool initialized = false;
+static bool enabled = false;
+static bool running = false;
+static bool channels_initialized[SOC_TOUCH_SENSOR_NUM] = {false};
+
+static touch_sensor_handle_t touch_sensor_handle = NULL;
+static touch_channel_handle_t touch_channel_handle[SOC_TOUCH_SENSOR_NUM] = {};
+
+// Active threshold to benchmark ratio. (i.e., touch will be activated when data >= benchmark * (1 + ratio))
+static float s_thresh2bm_ratio = 0.015f;  // 1.5% for all channels
+
+static bool ARDUINO_ISR_ATTR __touchOnActiveISR(touch_sensor_handle_t sens_handle, const touch_active_event_data_t *event, void *user_ctx) {
+  uint8_t pad_num = (uint8_t)event->chan_id;
+  __touchInterruptHandlers[pad_num].lastStatusIsPressed = true;
+  if (__touchInterruptHandlers[pad_num].fn) {
+    // keeping backward compatibility with "void cb(void)" and with new "void cb(void *)"
+    if (__touchInterruptHandlers[pad_num].callWithArgs) {
+      ((voidArgFuncPtr)__touchInterruptHandlers[pad_num].fn)(__touchInterruptHandlers[pad_num].arg);
+    } else {
+      __touchInterruptHandlers[pad_num].fn();
+    }
+  }
+  return false;
+}
+
+static bool ARDUINO_ISR_ATTR __touchOnInactiveISR(touch_sensor_handle_t sens_handle, const touch_inactive_event_data_t *event, void *user_ctx) {
+  uint8_t pad_num = (uint8_t)event->chan_id;
+  __touchInterruptHandlers[pad_num].lastStatusIsPressed = false;
+  if (__touchInterruptHandlers[pad_num].fn) {
+    // keeping backward compatibility with "void cb(void)" and with new "void cb(void *)"
+    if (__touchInterruptHandlers[pad_num].callWithArgs) {
+      ((voidArgFuncPtr)__touchInterruptHandlers[pad_num].fn)(__touchInterruptHandlers[pad_num].arg);
+    } else {
+      __touchInterruptHandlers[pad_num].fn();
+    }
+  }
+  return false;
+}
+
+bool touchStop() {
+  if (!running) {  // Already stopped
+    return true;
+  }
+  if (touch_sensor_stop_continuous_scanning(touch_sensor_handle) != ESP_OK) {
+    log_e("Touch sensor stop scanning failed!");
+    return false;
+  }
+  running = false;
+  return true;
+}
+
+bool touchDisable() {
+  if (!enabled) {  // Already disabled
+    return true;
+  }
+  if (!running && (touch_sensor_disable(touch_sensor_handle) != ESP_OK)) {
+    log_e("Touch sensor still running or disable failed!");
+    return false;
+  }
+  enabled = false;
+  return true;
+}
+
+bool touchStart() {
+  if (running) {  // Already running
+    return true;
+  }
+  if (enabled && (touch_sensor_start_continuous_scanning(touch_sensor_handle) != ESP_OK)) {
+    log_e("Touch sensor not enabled or failed to start continuous scanning failed!");
+    return false;
+  }
+  running = true;
+  return true;
+}
+
+bool touchEnable() {
+  if (enabled) {  // Already enabled
+    return true;
+  }
+  if (touch_sensor_enable(touch_sensor_handle) != ESP_OK) {
+    log_e("Touch sensor enable failed!");
+    return false;
+  }
+  enabled = true;
+  return true;
+}
+
+bool touchBenchmarkThreshold(uint8_t pad) {
+  if (!touchEnable()) {
+    return false;
+  }
+
+  /* Scan the enabled touch channels for several times, to make sure the initial channel data is stable */
+  for (int i = 0; i < 3; i++) {
+    if (touch_sensor_trigger_oneshot_scanning(touch_sensor_handle, 2000) != ESP_OK) {
+      log_e("Touch sensor trigger oneshot scanning failed!");
+      return false;
+    }
+  }
+
+  /* Disable the touch channel to rollback the state */
+  if (!touchDisable()) {
+    return false;
+  }
+
+  // Reconfigure passed pad with new threshold
+  uint32_t benchmark[_sample_num] = {};
+  if (touch_channel_read_data(touch_channel_handle[pad], TOUCH_CHAN_DATA_TYPE_BENCHMARK, benchmark) != ESP_OK) {
+    log_e("Touch channel read data failed!");
+    return false;
+  }
+  /* Calculate the proper active thresholds regarding the initial benchmark */
+  touch_channel_config_t chan_cfg = {};
+  for (int i = 0; i < _sample_num; i++) {
+    chan_cfg.active_thresh[i] = (uint32_t)(benchmark[i] * s_thresh2bm_ratio);
+    log_v("Configured [CH %d] sample %d: benchmark = %" PRIu32 ", threshold = %" PRIu32 "\t", pad, i, benchmark[i], chan_cfg.active_thresh[i]);
+  }
+  /* Update the channel configuration */
+  if (touch_sensor_reconfig_channel(touch_channel_handle[pad], &chan_cfg) != ESP_OK) {
+    log_e("Touch sensor threshold reconfig channel failed!");
+    return false;
+  }
+  return true;
+}
+
+static bool touchDetachBus(void *pin) {
+  int8_t pad = digitalPinToTouchChannel((int)(pin - 1));
+  channels_initialized[pad] = false;
+  //disable touch pad and delete the channel
+  touch_sensor_del_channel(touch_channel_handle[pad]);
+  used_pads--;
+  if (used_pads == 0) {
+    touchStop();
+    touchDisable();
+    if (touch_sensor_del_controller(touch_sensor_handle) != ESP_OK)  //deinit touch module, as no pads are used
+    {
+      log_e("Touch module deinit failed!");
+      return false;
+    }
+    initialized = false;
+  }
+  return true;
+}
+
+static void __touchInit() {
+  if (initialized) {
+    return;
+  }
+  // Support only one sample configuration for now
+  touch_sensor_sample_config_t single_sample_cfg = TOUCH_SENSOR_V3_DEFAULT_SAMPLE_CONFIG(_div_num, _coarse_freq_tune, _fine_freq_tune);
+  touch_sensor_sample_config_t sample_cfg[_sample_num] = {};
+  sample_cfg[0] = single_sample_cfg;
+
+  /* Allocate new touch controller handle */
+  touch_sensor_config_t sens_cfg = {
+    .power_on_wait_us = __touchSleepTime,
+    .meas_interval_us = __touchMeasureTime,
+    .max_meas_time_us = 0,
+    .output_mode = TOUCH_PAD_OUT_AS_CLOCK,
+    .sample_cfg_num = _sample_num,
+    .sample_cfg = sample_cfg,
+  };
+
+  // touch_sensor_config_t sens_cfg = TOUCH_SENSOR_DEFAULT_BASIC_CONFIG(_sample_num, sample_cfg);
+  if (touch_sensor_new_controller(&sens_cfg, &touch_sensor_handle) != ESP_OK) {
+    goto err;
+  }
+
+  sensor_config = sens_cfg;
+  /* Configure the touch sensor filter */
+  touch_sensor_filter_config_t filter_cfg = TOUCH_SENSOR_DEFAULT_FILTER_CONFIG();
+  if (touch_sensor_config_filter(touch_sensor_handle, &filter_cfg) != ESP_OK) {
+    goto err;
+  }
+
+  /* Register the touch sensor on_active and on_inactive callbacks */
+  touch_event_callbacks_t callbacks = {
+    .on_active = __touchOnActiveISR,
+    .on_inactive = __touchOnInactiveISR,
+    .on_measure_done = NULL,
+    .on_scan_done = NULL,
+    .on_timeout = NULL,
+    .on_proximity_meas_done = NULL,
+  };
+  if (touch_sensor_register_callbacks(touch_sensor_handle, &callbacks, NULL) != ESP_OK) {
+    goto err;
+  }
+
+  initialized = true;
+  return;
+err:
+  log_e(" Touch sensor initialization error.");
+  initialized = false;
+  return;
+}
+
+static void __touchChannelInit(int pad) {
+  if (channels_initialized[pad]) {
+    return;
+  }
+
+  // Initial setup with default Threshold
+  __touchInterruptHandlers[pad].fn = NULL;
+
+  touch_channel_config_t chan_cfg = {
+    .active_thresh = {1000}  // default threshold, will be updated after benchmark
+  };
+
+  if (!touchStop() || !touchDisable()) {
+    log_e("Touch sensor stop and disable failed!");
+    return;
+  }
+
+  if (touch_sensor_new_channel(touch_sensor_handle, pad, &chan_cfg, &touch_channel_handle[pad]) != ESP_OK) {
+    log_e("Touch sensor new channel failed!");
+    return;
+  }
+
+  // Benchmark active threshold and reconfigure pad
+  if (!touchBenchmarkThreshold(pad)) {
+    log_e("Touch sensor benchmark threshold failed!");
+    return;
+  }
+
+  channels_initialized[pad] = true;
+  used_pads++;
+
+  if (!touchEnable() || !touchStart()) {
+    log_e("Touch sensor enable and start failed!");
+  }
+}
+
+static touch_value_t __touchRead(uint8_t pin) {
+  int8_t pad = digitalPinToTouchChannel(pin);
+  if (pad < 0) {
+    log_e(" No touch pad on selected pin!");
+    return 0;
+  }
+
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_TOUCH) == NULL) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_TOUCH, touchDetachBus);
+    if (!perimanClearPinBus(pin)) {
+      return 0;
+    }
+    __touchInit();
+    __touchChannelInit(pad);
+
+    if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_TOUCH, (void *)(pin + 1), -1, pad)) {
+      touchDetachBus((void *)(pin + 1));
+      return 0;
+    }
+  }
+
+  uint32_t touch_read[_sample_num] = {};
+  touch_channel_read_data(touch_channel_handle[pad], TOUCH_CHAN_DATA_TYPE_SMOOTH, touch_read);
+  touch_value_t touch_value = touch_read[0];  // only one sample configuration for now
+
+  return touch_value;
+}
+
+static void __touchConfigInterrupt(uint8_t pin, void (*userFunc)(void), void *Args, bool callWithArgs, touch_value_t threshold) {
+  int8_t pad = digitalPinToTouchChannel(pin);
+  if (pad < 0) {
+    log_e(" No touch pad on selected pin!");
+    return;
+  }
+
+  if (userFunc == NULL) {
+    // detach ISR User Call
+    __touchInterruptHandlers[pad].fn = NULL;
+    __touchInterruptHandlers[pad].callWithArgs = false;
+    __touchInterruptHandlers[pad].arg = NULL;
+  } else {
+    // attach ISR User Call
+    __touchInit();
+    __touchChannelInit(pad);
+    __touchInterruptHandlers[pad].fn = userFunc;
+    __touchInterruptHandlers[pad].callWithArgs = callWithArgs;
+    __touchInterruptHandlers[pad].arg = Args;
+  }
+
+  if (threshold != 0) {
+    if (!touchStop() || !touchDisable()) {
+      log_e("Touch sensor stop and disable failed!");
+      return;
+    }
+
+    touch_channel_config_t chan_cfg = {};
+    for (int i = 0; i < _sample_num; i++) {
+      chan_cfg.active_thresh[i] = threshold;
+    }
+
+    if (touch_sensor_reconfig_channel(touch_channel_handle[pad], &chan_cfg) != ESP_OK) {
+      log_e("Touch sensor threshold reconfig channel failed!");
+    }
+
+    if (!touchEnable() || !touchStart()) {
+      log_e("Touch sensor enable and start failed!");
+    }
+  }
+}
+
+// it keeps backwards compatibility
+static void __touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), touch_value_t threshold) {
+  __touchConfigInterrupt(pin, userFunc, NULL, threshold, false);
+}
+
+// new additional version of the API with User Args
+static void __touchAttachArgsInterrupt(uint8_t pin, void (*userFunc)(void), void *args, touch_value_t threshold) {
+  __touchConfigInterrupt(pin, userFunc, args, threshold, true);
+}
+
+// new additional API to detach touch ISR
+static void __touchDettachInterrupt(uint8_t pin) {
+  __touchConfigInterrupt(pin, NULL, NULL, 0, false);  // userFunc as NULL acts as detaching
+}
+
+// /*
+//     External Public Touch API Functions
+// */
+
+bool touchInterruptGetLastStatus(uint8_t pin) {
+  int8_t pad = digitalPinToTouchChannel(pin);
+  if (pad < 0) {
+    return false;
+  }
+
+  return __touchInterruptHandlers[pad].lastStatusIsPressed;
+}
+
+void touchSleepWakeUpEnable(uint8_t pin, touch_value_t threshold) {
+  int8_t pad = digitalPinToTouchChannel(pin);
+  if (pad < 0) {
+    log_e(" No touch pad on selected pin!");
+    return;
+  }
+
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_TOUCH) == NULL) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_TOUCH, touchDetachBus);
+    __touchInit();
+    __touchChannelInit(pad);
+    if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_TOUCH, (void *)(pin + 1), -1, pad)) {
+      log_e("Failed to set bus to Peripheral manager");
+      touchDetachBus((void *)(pin + 1));
+      return;
+    }
+  }
+
+  log_v("Touch sensor deep sleep wake-up configuration for pad %d with threshold %d", pad, threshold);
+  if (!touchStop() || !touchDisable()) {
+    log_e("Touch sensor stop and disable failed!");
+    return;
+  }
+
+  touch_sleep_config_t deep_slp_cfg = {
+    .slp_wakeup_lvl = TOUCH_DEEP_SLEEP_WAKEUP,
+    .deep_slp_chan = touch_channel_handle[pad],
+    .deep_slp_thresh = {threshold},
+    .deep_slp_sens_cfg = NULL,  // Use the original touch sensor configuration
+  };
+
+  // Register the deep sleep wake-up
+  if (touch_sensor_config_sleep_wakeup(touch_sensor_handle, &deep_slp_cfg) != ESP_OK) {
+    log_e("Touch sensor deep sleep wake-up failed!");
+    return;
+  }
+
+  if (!touchEnable() || !touchStart()) {
+    log_e("Touch sensor enable and start failed!");
+  }
+}
+
+void touchSetDefaultThreshold(float percentage) {
+  s_thresh2bm_ratio = (float)percentage / 100.0f;
+}
+
+void touchSetTiming(float measure, uint32_t sleep) {
+  if (initialized) {
+    log_e("Touch sensor already initialized. Cannot set cycles.");
+    return;
+  }
+  __touchSleepTime = sleep;
+  __touchMeasureTime = measure;
+}
+
+void touchSetConfig(uint32_t div_num, uint8_t coarse_freq_tune, uint8_t fine_freq_tune) {
+  if (initialized) {
+    log_e("Touch sensor already initialized. Cannot set configuration.");
+    return;
+  }
+  _div_num = div_num;
+  _coarse_freq_tune = coarse_freq_tune;
+  _fine_freq_tune = fine_freq_tune;
+}
+
+extern touch_value_t touchRead(uint8_t) __attribute__((weak, alias("__touchRead")));
+extern void touchAttachInterrupt(uint8_t, voidFuncPtr, touch_value_t) __attribute__((weak, alias("__touchAttachInterrupt")));
+extern void touchAttachInterruptArg(uint8_t, voidArgFuncPtr, void *, touch_value_t) __attribute__((weak, alias("__touchAttachArgsInterrupt")));
+extern void touchDetachInterrupt(uint8_t) __attribute__((weak, alias("__touchDettachInterrupt")));
+
+#endif /* SOC_TOUCH_SENSOR_VERSION == 3 */
+#endif /* SOC_TOUCH_SENSOR_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-touch-ng.h b/cores/esp32/esp32-hal-touch-ng.h
new file mode 100644
index 00000000000..0d4eb79ac58
--- /dev/null
+++ b/cores/esp32/esp32-hal-touch-ng.h
@@ -0,0 +1,91 @@
+/*
+ Arduino.h - Main include file for the Arduino SDK
+ Copyright (c) 2005-2013 Arduino Team.  All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef MAIN_ESP32_HAL_TOUCH_NEW_H_
+#define MAIN_ESP32_HAL_TOUCH_NEW_H_
+
+#include "soc/soc_caps.h"
+#if SOC_TOUCH_SENSOR_SUPPORTED
+#if SOC_TOUCH_SENSOR_VERSION == 3  // ESP32P4
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "esp32-hal.h"
+
+typedef uint32_t touch_value_t;
+
+/*
+ * Set time in us that measurement operation takes
+ * The result from touchRead, threshold and detection
+ * accuracy depend on these values.
+ * Note: must be called before setting up touch pads
+ **/
+void touchSetTiming(float measure, uint32_t sleep);
+
+/*
+ * Tune the touch pad frequency.
+ * Note: Must be called before setting up touch pads
+*/
+void touchSetConfig(uint32_t _div_num, uint8_t coarse_freq_tune, uint8_t fine_freq_tune);
+
+/*
+ * Read touch pad value.
+ * You can use this method to chose a good threshold value
+ * to use as value for touchAttachInterrupt.
+ * */
+touch_value_t touchRead(uint8_t pin);
+
+/*
+ * Set function to be called if touch pad value rises by given increment (threshold).
+ * Use touchRead to determine a proper threshold between touched and untouched state.
+ * */
+void touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), touch_value_t threshold);
+void touchAttachInterruptArg(uint8_t pin, void (*userFunc)(void *), void *arg, touch_value_t threshold);
+void touchDetachInterrupt(uint8_t pin);
+
+/*
+ * Returns true when the latest ISR status for the Touchpad is that it is touched (Active)
+ * and false when the Touchpad is untoouched (Inactive).
+ * This function can be used in conjunction with ISR User callback in order to take action
+ * as soon as the touchpad is touched and/or released.
+ **/
+bool touchInterruptGetLastStatus(uint8_t pin);
+
+/*
+ * Set the default threshold for touch pads.
+ * The threshold is a percentage of the benchmark value.
+ * The default value is 1.5%.
+ **/
+void touchSetDefaultThreshold(float percentage);
+
+/*
+ * Setup touch pad wake up from deep sleep /light sleep with given threshold.
+ * When light sleep is used, all used touch pads will be able to wake up the chip.
+ **/
+void touchSleepWakeUpEnable(uint8_t pin, touch_value_t threshold);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SOC_TOUCH_SENSOR_VERSION == 3 */
+#endif /* SOC_TOUCH_SENSOR_SUPPORTED */
+#endif /* MAIN_ESP32_HAL_TOUCH_H_ */
diff --git a/cores/esp32/esp32-hal-touch.c b/cores/esp32/esp32-hal-touch.c
index 94e8a8b8ac3..701bf6d16c9 100644
--- a/cores/esp32/esp32-hal-touch.c
+++ b/cores/esp32/esp32-hal-touch.c
@@ -11,158 +11,319 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
+#include "soc/soc_caps.h"
 
+#if SOC_TOUCH_SENSOR_SUPPORTED
+#if SOC_TOUCH_SENSOR_VERSION <= 2  // ESP32, ESP32S2, ESP32S3
+
+#include "driver/touch_sensor.h"
 #include "esp32-hal-touch.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "rom/ets_sys.h"
-#include "esp_attr.h"
-#include "esp_intr.h"
-#include "soc/rtc_io_reg.h"
-#include "soc/rtc_cntl_reg.h"
-#include "soc/sens_reg.h"
+#include "esp32-hal-periman.h"
+
+/*
+    Internal Private Touch Data Structure and Functions
+*/
 
+#if SOC_TOUCH_SENSOR_VERSION == 1  // ESP32
 static uint16_t __touchSleepCycles = 0x1000;
 static uint16_t __touchMeasureCycles = 0x1000;
+#elif SOC_TOUCH_SENSOR_VERSION == 2  // ESP32S2, ESP32S3
+static uint16_t __touchSleepCycles = TOUCH_PAD_SLEEP_CYCLE_DEFAULT;
+static uint16_t __touchMeasureCycles = TOUCH_PAD_MEASURE_CYCLE_DEFAULT;
+#endif
 
 typedef void (*voidFuncPtr)(void);
-static voidFuncPtr __touchInterruptHandlers[10] = {0,};
-static intr_handle_t touch_intr_handle = NULL;
-
-void IRAM_ATTR __touchISR(void * arg)
-{
-    uint32_t pad_intr = READ_PERI_REG(SENS_SAR_TOUCH_CTRL2_REG) & 0x3ff;
-    uint32_t rtc_intr = READ_PERI_REG(RTC_CNTL_INT_ST_REG);
-    uint8_t i = 0;
-    //clear interrupt
-    WRITE_PERI_REG(RTC_CNTL_INT_CLR_REG, rtc_intr);
-    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_MEAS_EN_CLR);
-
-    if (rtc_intr & RTC_CNTL_TOUCH_INT_ST) {
-        for (i = 0; i < 10; ++i) {
-            if ((pad_intr >> i) & 0x01) {
-                if(__touchInterruptHandlers[i]){
-                    __touchInterruptHandlers[i]();
-                }
-            }
+typedef void (*voidArgFuncPtr)(void *);
+
+typedef struct {
+  voidFuncPtr fn;
+  bool callWithArgs;
+  void *arg;
+#if SOC_TOUCH_SENSOR_VERSION == 2  // Only for ESP32S2 and ESP32S3
+  bool lastStatusIsPressed;
+#endif
+} TouchInterruptHandle_t;
+
+static TouchInterruptHandle_t __touchInterruptHandlers[SOC_TOUCH_SENSOR_NUM] = {
+  0,
+};
+
+static uint8_t used_pads = 0;
+static bool initialized = false;
+static bool channels_initialized[SOC_TOUCH_SENSOR_NUM] = {false};
+
+static void ARDUINO_ISR_ATTR __touchISR(void *arg) {
+#if SOC_TOUCH_SENSOR_VERSION == 1  // ESP32
+  uint32_t pad_intr = touch_pad_get_status();
+  //clear interrupt
+  touch_pad_clear_status();
+  // call Pad ISR User callback
+  for (int i = 0; i < SOC_TOUCH_SENSOR_NUM; i++) {
+    if ((pad_intr >> i) & 0x01) {
+      if (__touchInterruptHandlers[i].fn) {
+        // keeping backward compatibility with "void cb(void)" and with new "void cb(vooid *)"
+        if (__touchInterruptHandlers[i].callWithArgs) {
+          ((voidArgFuncPtr)__touchInterruptHandlers[i].fn)(__touchInterruptHandlers[i].arg);
+        } else {
+          __touchInterruptHandlers[i].fn();
         }
+      }
+    }
+  }
+#elif SOC_TOUCH_SENSOR_VERSION == 2  // ESP32S2, ESP32S3
+  touch_pad_intr_mask_t evt = touch_pad_read_intr_status_mask();
+  uint8_t pad_num = touch_pad_get_current_meas_channel();
+  if (evt & TOUCH_PAD_INTR_MASK_ACTIVE) {
+    // touch has been pressed / touched
+    __touchInterruptHandlers[pad_num].lastStatusIsPressed = true;
+  }
+  if (evt & TOUCH_PAD_INTR_MASK_INACTIVE) {
+    // touch has been released / untouched
+    __touchInterruptHandlers[pad_num].lastStatusIsPressed = false;
+  }
+  if (__touchInterruptHandlers[pad_num].fn) {
+    // keeping backward compatibility with "void cb(void)" and with new "void cb(vooid *)"
+    if (__touchInterruptHandlers[pad_num].callWithArgs) {
+      ((voidArgFuncPtr)__touchInterruptHandlers[pad_num].fn)(__touchInterruptHandlers[pad_num].arg);
+    } else {
+      __touchInterruptHandlers[pad_num].fn();
     }
+  }
+#endif
 }
 
-void __touchSetCycles(uint16_t measure, uint16_t sleep)
-{
-    __touchSleepCycles = sleep;
-    __touchMeasureCycles = measure;
-    //Touch pad SleepCycle Time
-    SET_PERI_REG_BITS(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_SLEEP_CYCLES, __touchSleepCycles, SENS_TOUCH_SLEEP_CYCLES_S);
-    //Touch Pad Measure Time
-    SET_PERI_REG_BITS(SENS_SAR_TOUCH_CTRL1_REG, SENS_TOUCH_MEAS_DELAY, __touchMeasureCycles, SENS_TOUCH_MEAS_DELAY_S);
+static void __touchSetCycles(uint16_t measure, uint16_t sleep) {
+  __touchSleepCycles = sleep;
+  __touchMeasureCycles = measure;
+#if SOC_TOUCH_SENSOR_VERSION == 1  // ESP32
+  touch_pad_set_measurement_clock_cycles(measure);
+#elif SOC_TOUCH_SENSOR_VERSION == 2  // ESP32S2, ESP32S3
+  touch_pad_set_charge_discharge_times(measure);
+#endif
+  touch_pad_set_measurement_interval(sleep);
 }
 
-void __touchInit()
-{
-    static bool initialized = false;
-    if(initialized){
-        return;
+static bool touchDetachBus(void *pin) {
+  int8_t pad = digitalPinToTouchChannel((int)(pin - 1));
+  channels_initialized[pad] = false;
+  used_pads--;
+  if (used_pads == 0) {
+    if (touch_pad_deinit() != ESP_OK)  //deinit touch module, as no pads are used
+    {
+      log_e("Touch module deinit failed!");
+      return false;
     }
-    initialized = true;
-    SET_PERI_REG_BITS(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS, 1, RTC_IO_TOUCH_XPD_BIAS_S);
-    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_MEAS_EN_CLR);
-    //clear touch enable
-    WRITE_PERI_REG(SENS_SAR_TOUCH_ENABLE_REG, 0x0);
-    SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_TOUCH_SLP_TIMER_EN);
+    initialized = false;
+  }
+  return true;
+}
 
-    __touchSetCycles(__touchMeasureCycles, __touchSleepCycles);
+static void __touchInit() {
+  if (initialized) {
+    return;
+  }
+
+  esp_err_t err = ESP_OK;
+
+#if SOC_TOUCH_SENSOR_VERSION == 1  // ESP32
+  err = touch_pad_init();
+  if (err != ESP_OK) {
+    goto err;
+  }
+  // the next two lines will drive the touch reading values -- both will return ESP_OK
+  touch_pad_set_voltage(TOUCH_HVOLT_2V7, TOUCH_LVOLT_0V5, TOUCH_HVOLT_ATTEN_0V);
+  touch_pad_set_measurement_clock_cycles(__touchMeasureCycles);
+  touch_pad_set_measurement_interval(__touchSleepCycles);
+  // Touch Sensor Timer initiated
+  touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER);  // returns ESP_OK
+  err = touch_pad_filter_start(10);
+  if (err != ESP_OK) {
+    goto err;
+  }
+  // keep ISR activated - it can run all together (ISR + touchRead())
+  err = touch_pad_isr_register(__touchISR, NULL);
+  if (err != ESP_OK) {
+    goto err;
+  }
+  touch_pad_intr_enable();           // returns ESP_OK
+#elif SOC_TOUCH_SENSOR_VERSION == 2  // ESP32S2, ESP32S3
+  err = touch_pad_init();
+  if (err != ESP_OK) {
+    goto err;
+  }
+  // the next lines will drive the touch reading values -- all os them return ESP_OK
+  touch_pad_set_charge_discharge_times(__touchMeasureCycles);
+  touch_pad_set_measurement_interval(__touchSleepCycles);
+  touch_pad_set_voltage(TOUCH_PAD_HIGH_VOLTAGE_THRESHOLD, TOUCH_PAD_LOW_VOLTAGE_THRESHOLD, TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD);
+  touch_pad_set_idle_channel_connect(TOUCH_PAD_IDLE_CH_CONNECT_DEFAULT);
+  touch_pad_denoise_t denoise = {
+    .grade = TOUCH_PAD_DENOISE_BIT4,
+    .cap_level = TOUCH_PAD_DENOISE_CAP_L4,
+  };
+  touch_pad_denoise_set_config(&denoise);
+  touch_pad_denoise_enable();
+  // Touch Sensor Timer initiated
+  touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER);  // returns ESP_OK
+  touch_pad_fsm_start();                         // returns ESP_OK
+  //ISR setup moved to __touchChannelInit
+#endif
+  initialized = true;
+  return;
+err:
+  log_e(" Touch sensor initialization error.");
+  initialized = false;
+  return;
+}
 
-    esp_intr_alloc(ETS_RTC_CORE_INTR_SOURCE, (int)ESP_INTR_FLAG_IRAM, __touchISR, NULL, &touch_intr_handle);
+static void __touchChannelInit(int pad) {
+  if (channels_initialized[pad]) {
+    return;
+  }
+
+#if SOC_TOUCH_SENSOR_VERSION == 1  // ESP32
+  // Initial no Threshold and setup
+  __touchInterruptHandlers[pad].fn = NULL;
+  touch_pad_config(pad, TOUCH_PAD_THRESHOLD_MAX);  // returns ESP_OK
+#elif SOC_TOUCH_SENSOR_VERSION == 2                // ESP32S2, ESP32S3
+  // Initial no Threshold and setup
+  __touchInterruptHandlers[pad].fn = NULL;
+  touch_pad_config(pad);  // returns ESP_OK
+  // keep ISR activated - it can run all together (ISR + touchRead())
+  esp_err_t err = touch_pad_isr_register(__touchISR, NULL, TOUCH_PAD_INTR_MASK_ACTIVE | TOUCH_PAD_INTR_MASK_INACTIVE);
+  if (err != ESP_OK) {
+    log_e(" Touch sensor initialization error.");
+    return;
+  }
+  touch_pad_intr_enable(TOUCH_PAD_INTR_MASK_ACTIVE | TOUCH_PAD_INTR_MASK_INACTIVE);  // returns ESP_OK
+#endif
+
+  channels_initialized[pad] = true;
+  used_pads++;
+  delay(20);  //delay needed before reading from touch channel after config
 }
 
-uint16_t __touchRead(uint8_t pin)
-{
-    int8_t pad = digitalPinToTouchChannel(pin);
-    if(pad < 0){
-        return 0;
+static touch_value_t __touchRead(uint8_t pin) {
+  int8_t pad = digitalPinToTouchChannel(pin);
+  if (pad < 0) {
+    log_e(" No touch pad on selected pin!");
+    return 0;
+  }
+
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_TOUCH) == NULL) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_TOUCH, touchDetachBus);
+    if (!perimanClearPinBus(pin)) {
+      return 0;
     }
-
-    pinMode(pin, ANALOG);
-
     __touchInit();
+    __touchChannelInit(pad);
 
-    uint32_t v0 = READ_PERI_REG(SENS_SAR_TOUCH_ENABLE_REG);
-    //Disable Intr & enable touch pad
-    WRITE_PERI_REG(SENS_SAR_TOUCH_ENABLE_REG,
-            (v0 & ~((1 << (pad + SENS_TOUCH_PAD_OUTEN2_S)) | (1 << (pad + SENS_TOUCH_PAD_OUTEN1_S))))
-            | (1 << (pad + SENS_TOUCH_PAD_WORKEN_S)));
-
-    SET_PERI_REG_MASK(SENS_SAR_TOUCH_ENABLE_REG, (1 << (pad + SENS_TOUCH_PAD_WORKEN_S)));
+    if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_TOUCH, (void *)(pin + 1), -1, pad)) {
+      touchDetachBus((void *)(pin + 1));
+      return 0;
+    }
+  }
 
-    uint32_t rtc_tio_reg = RTC_IO_TOUCH_PAD0_REG + pad * 4;
-    WRITE_PERI_REG(rtc_tio_reg, (READ_PERI_REG(rtc_tio_reg)
-                      & ~(RTC_IO_TOUCH_PAD0_DAC_M))
-                      | (7 << RTC_IO_TOUCH_PAD0_DAC_S)//Touch Set Slope
-                      | RTC_IO_TOUCH_PAD0_TIE_OPT_M   //Enable Tie,Init Level
-                      | RTC_IO_TOUCH_PAD0_START_M     //Enable Touch Pad IO
-                      | RTC_IO_TOUCH_PAD0_XPD_M);     //Enable Touch Pad Power on
+  touch_value_t touch_value;
+  touch_pad_read_raw_data(pad, &touch_value);
 
-    //force oneTime test start
-    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_EN_M|SENS_TOUCH_START_FORCE_M);
+  return touch_value;
+}
 
-    SET_PERI_REG_BITS(SENS_SAR_TOUCH_CTRL1_REG, SENS_TOUCH_XPD_WAIT, 10, SENS_TOUCH_XPD_WAIT_S);
+static void __touchConfigInterrupt(uint8_t pin, void (*userFunc)(void), void *Args, touch_value_t threshold, bool callWithArgs) {
+  int8_t pad = digitalPinToTouchChannel(pin);
+  if (pad < 0) {
+    log_e(" No touch pad on selected pin!");
+    return;
+  }
+
+  if (userFunc == NULL) {
+    // detach ISR User Call
+    __touchInterruptHandlers[pad].fn = NULL;
+    threshold = TOUCH_PAD_THRESHOLD_MAX;  // deactivate the ISR with SOC_TOUCH_PAD_THRESHOLD_MAX
+  } else {
+    // attach ISR User Call
+    __touchInit();
+    __touchChannelInit(pad);
+    __touchInterruptHandlers[pad].fn = userFunc;
+    __touchInterruptHandlers[pad].callWithArgs = callWithArgs;
+    __touchInterruptHandlers[pad].arg = Args;
+  }
 
-    while (GET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_MEAS_DONE) == 0) {};
+  touch_pad_set_thresh(pad, threshold);
+}
 
-    uint16_t touch_value = READ_PERI_REG(SENS_SAR_TOUCH_OUT1_REG + (pad / 2) * 4) >> ((pad & 1) ? SENS_TOUCH_MEAS_OUT1_S : SENS_TOUCH_MEAS_OUT0_S);
+// it keeps backwards compatibility
+static void __touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), touch_value_t threshold) {
+  __touchConfigInterrupt(pin, userFunc, NULL, threshold, false);
+}
 
-    //clear touch force ,select the Touch mode is Timer
-    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_EN_M|SENS_TOUCH_START_FORCE_M);
+// new additional version of the API with User Args
+static void __touchAttachArgsInterrupt(uint8_t pin, void (*userFunc)(void), void *args, touch_value_t threshold) {
+  __touchConfigInterrupt(pin, userFunc, args, threshold, true);
+}
 
-    //restore previous value
-    WRITE_PERI_REG(SENS_SAR_TOUCH_ENABLE_REG, v0);
-    return touch_value;
+// new additional API to detach touch ISR
+static void __touchDettachInterrupt(uint8_t pin) {
+  __touchConfigInterrupt(pin, NULL, NULL, 0, false);  // userFunc as NULL acts as detaching
 }
 
-void __touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), uint16_t threshold)
-{
-    int8_t pad = digitalPinToTouchChannel(pin);
-    if(pad < 0){
-        return;
-    }
+/*
+    External Public Touch API Functions
+*/
+
+#if SOC_TOUCH_SENSOR_VERSION == 1  // Only for ESP32 SoC
+void touchInterruptSetThresholdDirection(bool mustbeLower) {
+  if (mustbeLower) {
+    touch_pad_set_trigger_mode(TOUCH_TRIGGER_BELOW);
+  } else {
+    touch_pad_set_trigger_mode(TOUCH_TRIGGER_ABOVE);
+  }
+}
+#elif SOC_TOUCH_SENSOR_VERSION == 2  // Only for ESP32S2 and ESP32S3
+// returns true if touch pad has been and continues pressed and false otherwise
+bool touchInterruptGetLastStatus(uint8_t pin) {
+  int8_t pad = digitalPinToTouchChannel(pin);
+  if (pad < 0) {
+    return false;
+  }
+
+  return __touchInterruptHandlers[pad].lastStatusIsPressed;
+}
+#endif
 
-    pinMode(pin, ANALOG);
+void touchSleepWakeUpEnable(uint8_t pin, touch_value_t threshold) {
+  int8_t pad = digitalPinToTouchChannel(pin);
+  if (pad < 0) {
+    log_e(" No touch pad on selected pin!");
+    return;
+  }
 
+  if (perimanGetPinBus(pin, ESP32_BUS_TYPE_TOUCH) == NULL) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_TOUCH, touchDetachBus);
     __touchInit();
+    __touchChannelInit(pad);
+    if (!perimanSetPinBus(pin, ESP32_BUS_TYPE_TOUCH, (void *)(pin + 1), -1, pad)) {
+      log_e("Failed to set bus to Peripheral manager");
+      touchDetachBus((void *)(pin + 1));
+      return;
+    }
+  }
+#if SOC_TOUCH_SENSOR_VERSION == 1  // Only for ESP32 SoC
+  touch_pad_set_thresh(pad, threshold);
 
-    __touchInterruptHandlers[pad] = userFunc;
-
-    //clear touch force ,select the Touch mode is Timer
-    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_EN_M|SENS_TOUCH_START_FORCE_M);
-
-    //interrupt when touch value < threshold
-    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_TOUCH_OUT_SEL);
-    //Intr will give ,when SET0 < threshold
-    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_TOUCH_OUT_1EN);
-    //Enable Rtc Touch Module Intr,the Interrupt need Rtc out  Enable
-    SET_PERI_REG_MASK(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_INT_ENA);
-
-    //set threshold
-    uint8_t shift = (pad & 1) ? SENS_TOUCH_OUT_TH1_S : SENS_TOUCH_OUT_TH0_S;
-    SET_PERI_REG_BITS((SENS_SAR_TOUCH_THRES1_REG + (pad / 2) * 4), SENS_TOUCH_OUT_TH0, threshold, shift);
-
-    uint32_t rtc_tio_reg = RTC_IO_TOUCH_PAD0_REG + pad * 4;
-    WRITE_PERI_REG(rtc_tio_reg, (READ_PERI_REG(rtc_tio_reg)
-                      & ~(RTC_IO_TOUCH_PAD0_DAC_M))
-                      | (7 << RTC_IO_TOUCH_PAD0_DAC_S)//Touch Set Slope
-                      | RTC_IO_TOUCH_PAD0_TIE_OPT_M   //Enable Tie,Init Level
-                      | RTC_IO_TOUCH_PAD0_START_M     //Enable Touch Pad IO
-                      | RTC_IO_TOUCH_PAD0_XPD_M);     //Enable Touch Pad Power on
-
-    //Enable Digital rtc control :work mode and out mode
-    SET_PERI_REG_MASK(SENS_SAR_TOUCH_ENABLE_REG,
-                      (1 << (pad + SENS_TOUCH_PAD_WORKEN_S)) | \
-                      (1 << (pad + SENS_TOUCH_PAD_OUTEN2_S)) | \
-                      (1 << (pad + SENS_TOUCH_PAD_OUTEN1_S)));
+#elif SOC_TOUCH_SENSOR_VERSION == 2
+  touch_pad_sleep_channel_enable(pad, true);
+  touch_pad_sleep_set_threshold(pad, threshold);
+
+#endif
+  esp_sleep_enable_touchpad_wakeup();
 }
 
-extern uint16_t touchRead(uint8_t pin) __attribute__ ((weak, alias("__touchRead")));
-extern void touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), uint16_t threshold) __attribute__ ((weak, alias("__touchAttachInterrupt")));
-extern void touchSetCycles(uint16_t measure, uint16_t sleep) __attribute__ ((weak, alias("__touchSetCycles")));
+extern touch_value_t touchRead(uint8_t) __attribute__((weak, alias("__touchRead")));
+extern void touchAttachInterrupt(uint8_t, voidFuncPtr, touch_value_t) __attribute__((weak, alias("__touchAttachInterrupt")));
+extern void touchAttachInterruptArg(uint8_t, voidArgFuncPtr, void *, touch_value_t) __attribute__((weak, alias("__touchAttachArgsInterrupt")));
+extern void touchDetachInterrupt(uint8_t) __attribute__((weak, alias("__touchDettachInterrupt")));
+extern void touchSetCycles(uint16_t, uint16_t) __attribute__((weak, alias("__touchSetCycles")));
+
+#endif /* SOC_TOUCH_SENSOR_VERSION <= 2 */
+#endif /* SOC_TOUCH_SENSOR_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-touch.h b/cores/esp32/esp32-hal-touch.h
index 6f3b0fd0f7d..4b06c7db766 100644
--- a/cores/esp32/esp32-hal-touch.h
+++ b/cores/esp32/esp32-hal-touch.h
@@ -20,12 +20,26 @@
 #ifndef MAIN_ESP32_HAL_TOUCH_H_
 #define MAIN_ESP32_HAL_TOUCH_H_
 
+#include "soc/soc_caps.h"
+#if SOC_TOUCH_SENSOR_SUPPORTED
+#if SOC_TOUCH_SENSOR_VERSION <= 2  // ESP32 ESP32S2 ESP32S3
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #include "esp32-hal.h"
 
+#if !SOC_TOUCH_SENSOR_SUPPORTED
+#error Touch IDF driver Not supported!
+#endif
+
+#if SOC_TOUCH_SENSOR_VERSION == 1  // ESP32
+typedef uint16_t touch_value_t;
+#elif SOC_TOUCH_SENSOR_VERSION == 2  // ESP32S2 ESP32S3
+typedef uint32_t touch_value_t;
+#endif
+
 /*
  * Set cycles that measurement operation takes
  * The result from touchRead, threshold and detection
@@ -36,21 +50,54 @@ extern "C" {
 void touchSetCycles(uint16_t measure, uint16_t sleep);
 
 /*
- * Read touch pad (values close to 0 mean touch detected)
+ * Read touch pad (for ESP32 values close to 0 mean touch detected /
+ * for ESP32-S2/S3 higher values mean touch detected)
  * You can use this method to chose a good threshold value
  * to use as value for touchAttachInterrupt
  * */
-uint16_t touchRead(uint8_t pin);
+touch_value_t touchRead(uint8_t pin);
 
 /*
- * Set function to be called if touch pad value falls
- * below the given threshold. Use touchRead to determine
- * a proper threshold between touched and untouched state
+ * Set function to be called if touch pad value falls (ESP32)
+ * below the given threshold / rises (ESP32-S2/S3) by given increment (threshold).
+ * Use touchRead to determine a proper threshold between touched and untouched state
  * */
-void touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), uint16_t threshold);
+void touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), touch_value_t threshold);
+void touchAttachInterruptArg(uint8_t pin, void (*userFunc)(void *), void *arg, touch_value_t threshold);
+void touchDetachInterrupt(uint8_t pin);
+
+/*
+ * Specific functions to ESP32
+ * Tells the driver if it shall activate the ISR if the sensor is Lower or Higher than the Threshold
+ * Default if Lower.
+ **/
+
+#if SOC_TOUCH_SENSOR_VERSION == 1  // Only for ESP32 SoC
+void touchInterruptSetThresholdDirection(bool mustbeLower);
+#endif
+
+/*
+ * Specific functions to ESP32-S2 and ESP32-S3
+ * Returns true when the latest ISR status for the Touchpad is that it is touched (Active)
+ * and false when the Touchpad is untoouched (Inactive)
+ * This function can be used in conjunction with ISR User callback in order to take action
+ * as soon as the touchpad is touched and/or released
+ **/
+
+#if SOC_TOUCH_SENSOR_VERSION == 2  // Only for ESP32S2 and ESP32S3
+// returns true if touch pad has been and continues pressed and false otherwise
+bool touchInterruptGetLastStatus(uint8_t pin);
+#endif
+
+/*
+ * Setup touch pad wake up from deep sleep with given threshold.
+ **/
+void touchSleepWakeUpEnable(uint8_t pin, touch_value_t threshold);
 
 #ifdef __cplusplus
 }
 #endif
 
+#endif /* SOC_TOUCH_SENSOR_VERSION <= 2 */
+#endif /* SOC_TOUCH_SENSOR_SUPPORTED */
 #endif /* MAIN_ESP32_HAL_TOUCH_H_ */
diff --git a/cores/esp32/esp32-hal-uart.c b/cores/esp32/esp32-hal-uart.c
index 7ee23b95c95..5311aff4f37 100644
--- a/cores/esp32/esp32-hal-uart.c
+++ b/cores/esp32/esp32-hal-uart.c
@@ -1,4 +1,4 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2025 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -13,623 +13,1463 @@
 // limitations under the License.
 
 #include "esp32-hal-uart.h"
+
+#if SOC_UART_SUPPORTED
 #include "esp32-hal.h"
+#include "esp32-hal-periman.h"
+
 #include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/queue.h"
 #include "freertos/semphr.h"
-#include "rom/ets_sys.h"
-#include "esp_attr.h"
-#include "esp_intr.h"
-#include "rom/uart.h"
-#include "soc/uart_reg.h"
+
+#include "driver/uart.h"
+#include "hal/uart_ll.h"
+#include "soc/soc_caps.h"
 #include "soc/uart_struct.h"
-#include "soc/io_mux_reg.h"
-#include "soc/gpio_sig_map.h"
-#include "soc/dport_reg.h"
-#include "soc/rtc.h"
-#include "esp_intr_alloc.h"
+#include "soc/uart_periph.h"
+#include "rom/ets_sys.h"
+#include "rom/gpio.h"
+
+#include "driver/gpio.h"
+#include "hal/gpio_hal.h"
+#include "esp_rom_gpio.h"
 
-#define UART_REG_BASE(u)    ((u==0)?DR_REG_UART_BASE:(      (u==1)?DR_REG_UART1_BASE:(    (u==2)?DR_REG_UART2_BASE:0)))
-#define UART_RXD_IDX(u)     ((u==0)?U0RXD_IN_IDX:(          (u==1)?U1RXD_IN_IDX:(         (u==2)?U2RXD_IN_IDX:0)))
-#define UART_TXD_IDX(u)     ((u==0)?U0TXD_OUT_IDX:(         (u==1)?U1TXD_OUT_IDX:(        (u==2)?U2TXD_OUT_IDX:0)))
-#define UART_INTR_SOURCE(u) ((u==0)?ETS_UART0_INTR_SOURCE:( (u==1)?ETS_UART1_INTR_SOURCE:((u==2)?ETS_UART2_INTR_SOURCE:0)))
+#include "driver/rtc_io.h"
+#include "driver/lp_io.h"
+#include "soc/uart_periph.h"
+#include "esp_private/uart_share_hw_ctrl.h"
 
-static int s_uart_debug_nr = 0;
+static int s_uart_debug_nr = 0;         // UART number for debug output
+#define REF_TICK_BAUDRATE_LIMIT 250000  // this is maximum UART badrate using REF_TICK as clock
 
 struct uart_struct_t {
-    uart_dev_t * dev;
+
 #if !CONFIG_DISABLE_HAL_LOCKS
-    xSemaphoreHandle lock;
+  SemaphoreHandle_t lock;  // UART lock
 #endif
-    uint8_t num;
-    xQueueHandle queue;
-    intr_handle_t intr_handle;
+
+  uint8_t num;                     // UART number for IDF driver API
+  bool has_peek;                   // flag to indicate that there is a peek byte pending to be read
+  uint8_t peek_byte;               // peek byte that has been read but not consumed
+  QueueHandle_t uart_event_queue;  // export it by some uartGetEventQueue() function
+  // configuration data:: Arduino API typical data
+  int8_t _rxPin, _txPin, _ctsPin, _rtsPin;  // UART GPIOs
+  uint32_t _baudrate, _config;              // UART baudrate and config
+  // UART ESP32 specific data
+  uint16_t _rx_buffer_size, _tx_buffer_size;  // UART RX and TX buffer sizes
+  bool _inverted;                             // UART inverted signal
+  uint8_t _rxfifo_full_thrhd;                 // UART RX FIFO full threshold
+  int8_t _uart_clock_source;                  // UART Clock Source used when it is started using uartBegin()
 };
 
 #if CONFIG_DISABLE_HAL_LOCKS
+
 #define UART_MUTEX_LOCK()
 #define UART_MUTEX_UNLOCK()
 
-static uart_t _uart_bus_array[3] = {
-    {(volatile uart_dev_t *)(DR_REG_UART_BASE), 0, NULL, NULL},
-    {(volatile uart_dev_t *)(DR_REG_UART1_BASE), 1, NULL, NULL},
-    {(volatile uart_dev_t *)(DR_REG_UART2_BASE), 2, NULL, NULL}
+static uart_t _uart_bus_array[] = {
+  {0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#if SOC_UART_NUM > 1
+  {1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
+#if SOC_UART_NUM > 2
+  {2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
+#if SOC_UART_NUM > 3
+  {3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
+#if SOC_UART_NUM > 4
+  {4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
+#if SOC_UART_NUM > 5
+  {5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
 };
+
 #else
-#define UART_MUTEX_LOCK()    do {} while (xSemaphoreTake(uart->lock, portMAX_DELAY) != pdPASS)
-#define UART_MUTEX_UNLOCK()  xSemaphoreGive(uart->lock)
 
-static uart_t _uart_bus_array[3] = {
-    {(volatile uart_dev_t *)(DR_REG_UART_BASE), NULL, 0, NULL, NULL},
-    {(volatile uart_dev_t *)(DR_REG_UART1_BASE), NULL, 1, NULL, NULL},
-    {(volatile uart_dev_t *)(DR_REG_UART2_BASE), NULL, 2, NULL, NULL}
+#define UART_MUTEX_LOCK() \
+  if (uart->lock != NULL) \
+    do {                  \
+  } while (xSemaphoreTake(uart->lock, portMAX_DELAY) != pdPASS)
+#define UART_MUTEX_UNLOCK() \
+  if (uart->lock != NULL)   \
+  xSemaphoreGive(uart->lock)
+
+static uart_t _uart_bus_array[] = {
+  {NULL, 0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#if SOC_UART_NUM > 1
+  {NULL, 1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
+#if SOC_UART_NUM > 2
+  {NULL, 2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
+#if SOC_UART_NUM > 3
+  {NULL, 3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
+#if SOC_UART_NUM > 4
+  {NULL, 4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
+#if SOC_UART_NUM > 5
+  {NULL, 5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
+#endif
 };
+
 #endif
 
-static void uart_on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb);
+#if SOC_UART_LP_NUM >= 1
+// LP UART enable pins routine
+static bool lp_uart_config_io(uint8_t uart_num, int8_t pin, rtc_gpio_mode_t direction, uint32_t idx) {
+  /* Skip configuration if the LP_IO is -1 */
+  if (pin < 0) {
+    return true;
+  }
+
+  // Initialize LP_IO
+  if (rtc_gpio_init(pin) != ESP_OK) {
+    log_e("Failed to initialize LP_IO %d", pin);
+    return false;
+  }
+
+  // Set LP_IO direction
+  if (rtc_gpio_set_direction(pin, direction) != ESP_OK) {
+    log_e("Failed to set LP_IO %d direction", pin);
+    return false;
+  }
+
+  // Connect pins
+  const uart_periph_sig_t *upin = &uart_periph_signal[uart_num].pins[idx];
+#if !SOC_LP_GPIO_MATRIX_SUPPORTED  // ESP32-C6/C61/C5
+  // When LP_IO Matrix is not support, LP_IO Mux must be connected to the pins
+  if (rtc_gpio_iomux_func_sel(pin, upin->iomux_func) != ESP_OK) {
+    log_e("Failed to set LP_IO pin %d into Mux function", pin);
+    return false;
+  }
+#else   // So far, only ESP32-P4
+  // If the configured pin is the default LP_IO Mux pin for LP UART, then set the LP_IO MUX function
+  if (upin->default_gpio == pin) {
+    if (rtc_gpio_iomux_func_sel(pin, upin->iomux_func) != ESP_OK) {
+      log_e("Failed to set LP_IO pin %d into Mux function", pin);
+      return false;
+    }
+  } else {
+    // Otherwise, set the LP_IO Matrix and select FUNC1
+    if (rtc_gpio_iomux_func_sel(pin, 1) != ESP_OK) {
+      log_e("Failed to set LP_IO pin %d into Mux function GPIO", pin);
+      return false;
+    }
+    // Connect the LP_IO to the LP UART peripheral signal
+    esp_err_t ret;
+    if (direction == RTC_GPIO_MODE_OUTPUT_ONLY) {
+      ret = lp_gpio_connect_out_signal(pin, UART_PERIPH_SIGNAL(uart_num, idx), 0, 0);
+    } else {
+      ret = lp_gpio_connect_in_signal(pin, UART_PERIPH_SIGNAL(uart_num, idx), 0);
+    }
+    if (ret != ESP_OK) {
+      log_e("Failed to connect LP_IO pin %d to UART%d signal", pin, uart_num);
+      return false;
+    }
+  }
+#endif  // SOC_LP_GPIO_MATRIX_SUPPORTED
 
-static void IRAM_ATTR _uart_isr(void *arg)
-{
-    uint8_t i, c;
-    BaseType_t xHigherPriorityTaskWoken;
-    uart_t* uart;
+  return true;
+}
 
-    for(i=0;i<3;i++){
-        uart = &_uart_bus_array[i];
-        if(uart->intr_handle == NULL){
-            continue;
-        }
-        uart->dev->int_clr.rxfifo_full = 1;
-        uart->dev->int_clr.frm_err = 1;
-        uart->dev->int_clr.rxfifo_tout = 1;
-        while(uart->dev->status.rxfifo_cnt || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
-            c = uart->dev->fifo.rw_byte;
-            if(uart->queue != NULL)  {
-                xQueueSendFromISR(uart->queue, &c, &xHigherPriorityTaskWoken);
-            }
-        }
+// When LP UART needs the RTC IO MUX to set the pin, it will always have fixed pins for RX, TX, CTS and RTS
+static bool lpuartCheckPins(int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin, uint8_t uart_nr) {
+// check if LP UART is being used and if the pins are valid
+#if !SOC_LP_GPIO_MATRIX_SUPPORTED  // ESP32-C6/C61/C5
+  uint16_t lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_RX_PIN_IDX].default_gpio;
+  if (uart_nr >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
+    if (rxPin > 0 && rxPin != lp_uart_fixed_pin) {
+      log_e("UART%d LP UART requires RX pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
+      return false;
     }
-
-    if (xHigherPriorityTaskWoken) {
-        portYIELD_FROM_ISR();
+    lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_TX_PIN_IDX].default_gpio;
+    if (txPin > 0 && txPin != lp_uart_fixed_pin) {
+      log_e("UART%d LP UART requires TX pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
+      return false;
+    }
+    lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_CTS_PIN_IDX].default_gpio;
+    if (ctsPin > 0 && ctsPin != lp_uart_fixed_pin) {
+      log_e("UART%d LP UART requires CTS pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
+      return false;
     }
+    lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_RTS_PIN_IDX].default_gpio;
+    if (rtsPin > 0 && rtsPin != lp_uart_fixed_pin) {
+      log_e("UART%d LP UART requires RTS pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
+      return false;
+    }
+  }
+  return true;
+#else   // ESP32-P4 can set any pin for LP UART
+  return true;
+#endif  // SOC_LP_GPIO_MATRIX_SUPPORTED
+}
+#endif  // SOC_UART_LP_NUM >= 1
+
+// Negative Pin Number will keep it unmodified, thus this function can detach individual pins
+// This function will also unset the pins in the Peripheral Manager and set the pin to -1 after detaching
+static bool _uartDetachPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin) {
+  if (uart_num >= SOC_UART_NUM) {
+    log_e("Serial number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1);
+    return false;
+  }
+  // get UART information
+  uart_t *uart = &_uart_bus_array[uart_num];
+  bool retCode = true;
+  //log_v("detaching UART%d pins: prev,pin RX(%d,%d) TX(%d,%d) CTS(%d,%d) RTS(%d,%d)", uart_num,
+  //        uart->_rxPin, rxPin, uart->_txPin, txPin, uart->_ctsPin, ctsPin, uart->_rtsPin, rtsPin); vTaskDelay(10);
+
+  // detaches HP and LP pins and sets Peripheral Manager and UART information
+  if (rxPin >= 0 && uart->_rxPin == rxPin && perimanGetPinBusType(rxPin) == ESP32_BUS_TYPE_UART_RX) {
+    gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rxPin], PIN_FUNC_GPIO);
+    // avoids causing BREAK in the UART line
+    if (uart->_inverted) {
+      esp_rom_gpio_connect_in_signal(GPIO_FUNC_IN_LOW, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false);
+    } else {
+      esp_rom_gpio_connect_in_signal(GPIO_FUNC_IN_HIGH, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false);
+    }
+    uart->_rxPin = -1;  // -1 means unassigned/detached
+    if (!perimanClearPinBus(rxPin)) {
+      retCode = false;
+      log_e("UART%d failed to detach RX pin %d", uart_num, rxPin);
+    }
+  }
+  if (txPin >= 0 && uart->_txPin == txPin && perimanGetPinBusType(txPin) == ESP32_BUS_TYPE_UART_TX) {
+    gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[txPin], PIN_FUNC_GPIO);
+    esp_rom_gpio_connect_out_signal(txPin, SIG_GPIO_OUT_IDX, false, false);
+    uart->_txPin = -1;  // -1 means unassigned/detached
+    if (!perimanClearPinBus(txPin)) {
+      retCode = false;
+      log_e("UART%d failed to detach TX pin %d", uart_num, txPin);
+    }
+  }
+  if (ctsPin >= 0 && uart->_ctsPin == ctsPin && perimanGetPinBusType(ctsPin) == ESP32_BUS_TYPE_UART_CTS) {
+    gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[ctsPin], PIN_FUNC_GPIO);
+    esp_rom_gpio_connect_in_signal(GPIO_FUNC_IN_LOW, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), false);
+    uart->_ctsPin = -1;  // -1 means unassigned/detached
+    if (!perimanClearPinBus(ctsPin)) {
+      retCode = false;
+      log_e("UART%d failed to detach CTS pin %d", uart_num, ctsPin);
+    }
+  }
+  if (rtsPin >= 0 && uart->_rtsPin == rtsPin && perimanGetPinBusType(rtsPin) == ESP32_BUS_TYPE_UART_RTS) {
+    gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rtsPin], PIN_FUNC_GPIO);
+    esp_rom_gpio_connect_out_signal(rtsPin, SIG_GPIO_OUT_IDX, false, false);
+    uart->_rtsPin = -1;  // -1 means unassigned/detached
+    if (!perimanClearPinBus(rtsPin)) {
+      retCode = false;
+      log_e("UART%d failed to detach RTS pin %d", uart_num, rtsPin);
+    }
+  }
+  return retCode;
 }
 
-void uartEnableInterrupt(uart_t* uart)
-{
-    UART_MUTEX_LOCK();
-    uart->dev->conf1.rxfifo_full_thrhd = 112;
-    uart->dev->conf1.rx_tout_thrhd = 2;
-    uart->dev->conf1.rx_tout_en = 1;
-    uart->dev->int_ena.rxfifo_full = 1;
-    uart->dev->int_ena.frm_err = 1;
-    uart->dev->int_ena.rxfifo_tout = 1;
-    uart->dev->int_clr.val = 0xffffffff;
-
-    esp_intr_alloc(UART_INTR_SOURCE(uart->num), (int)ESP_INTR_FLAG_IRAM, _uart_isr, NULL, &uart->intr_handle);
-    UART_MUTEX_UNLOCK();
+// Peripheral Manager detach callback for each specific UART PIN
+static bool _uartDetachBus_RX(void *busptr) {
+  // sanity check - it should never happen
+  assert(busptr && "_uartDetachBus_RX bus NULL pointer.");
+  uart_t *bus = (uart_t *)busptr;
+  return _uartDetachPins(bus->num, bus->_rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
 }
 
-void uartDisableInterrupt(uart_t* uart)
-{
-    UART_MUTEX_LOCK();
-    uart->dev->conf1.val = 0;
-    uart->dev->int_ena.val = 0;
-    uart->dev->int_clr.val = 0xffffffff;
+static bool _uartDetachBus_TX(void *busptr) {
+  // sanity check - it should never happen
+  assert(busptr && "_uartDetachBus_TX bus NULL pointer.");
+  uart_t *bus = (uart_t *)busptr;
+  return _uartDetachPins(bus->num, UART_PIN_NO_CHANGE, bus->_txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+}
 
-    esp_intr_free(uart->intr_handle);
-    uart->intr_handle = NULL;
+static bool _uartDetachBus_CTS(void *busptr) {
+  // sanity check - it should never happen
+  assert(busptr && "_uartDetachBus_CTS bus NULL pointer.");
+  uart_t *bus = (uart_t *)busptr;
+  return _uartDetachPins(bus->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, bus->_ctsPin, UART_PIN_NO_CHANGE);
+}
 
-    UART_MUTEX_UNLOCK();
+static bool _uartDetachBus_RTS(void *busptr) {
+  // sanity check - it should never happen
+  assert(busptr && "_uartDetachBus_RTS bus NULL pointer.");
+  uart_t *bus = (uart_t *)busptr;
+  return _uartDetachPins(bus->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, bus->_rtsPin);
 }
 
-void uartDetachRx(uart_t* uart, uint8_t rxPin)
-{
-    if(uart == NULL) {
-        return;
+// Attach function for UART
+// connects the IO Pad, set Paripheral Manager and internal UART structure data
+static bool _uartAttachPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin) {
+  if (uart_num >= SOC_UART_NUM) {
+    log_e("Serial number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1);
+    return false;
+  }
+  // get UART information
+  uart_t *uart = &_uart_bus_array[uart_num];
+  //log_v("attaching UART%d pins: prev,new RX(%d,%d) TX(%d,%d) CTS(%d,%d) RTS(%d,%d)", uart_num,
+  //        uart->_rxPin, rxPin, uart->_txPin, txPin, uart->_ctsPin, ctsPin, uart->_rtsPin, rtsPin); vTaskDelay(10);
+
+  // IDF uart_set_pin() checks if the pin is used within LP UART and if it is a valid RTC IO pin
+  // No need for Arduino Layer to check it again
+  bool retCode = true;
+  if (rxPin >= 0) {
+    // forces a clean detaching from a previous peripheral
+    if (perimanGetPinBusType(rxPin) != ESP32_BUS_TYPE_INIT) {
+      perimanClearPinBus(rxPin);
+    }
+    // connect RX Pad
+    bool ret = ESP_OK == uart_set_pin(uart->num, UART_PIN_NO_CHANGE, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+#if SOC_UART_LP_NUM >= 1
+    if (ret && uart_num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
+      ret &= lp_uart_config_io(uart->num, rxPin, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_RX_PIN_IDX);
+    }
+#endif
+    if (ret) {
+      ret &= perimanSetPinBus(rxPin, ESP32_BUS_TYPE_UART_RX, (void *)uart, uart_num, -1);
+      if (ret) {
+        uart->_rxPin = rxPin;
+      }
+    }
+    if (!ret) {
+      log_e("UART%d failed to attach RX pin %d", uart_num, rxPin);
+    }
+    retCode &= ret;
+  }
+  if (txPin >= 0) {
+    // forces a clean detaching from a previous peripheral
+    if (perimanGetPinBusType(txPin) != ESP32_BUS_TYPE_INIT) {
+      perimanClearPinBus(txPin);
+    }
+    // connect TX Pad
+    bool ret = ESP_OK == uart_set_pin(uart->num, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+#if SOC_UART_LP_NUM >= 1
+    if (ret && uart_num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
+      ret &= lp_uart_config_io(uart->num, txPin, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_TX_PIN_IDX);
+    }
+#endif
+    if (ret) {
+      ret &= perimanSetPinBus(txPin, ESP32_BUS_TYPE_UART_TX, (void *)uart, uart_num, -1);
+      if (ret) {
+        uart->_txPin = txPin;
+      }
+    }
+    if (!ret) {
+      log_e("UART%d failed to attach TX pin %d", uart_num, txPin);
+    }
+    retCode &= ret;
+  }
+  if (ctsPin >= 0) {
+    // forces a clean detaching from a previous peripheral
+    if (perimanGetPinBusType(ctsPin) != ESP32_BUS_TYPE_INIT) {
+      perimanClearPinBus(ctsPin);
+    }
+    // connect CTS Pad
+    bool ret = ESP_OK == uart_set_pin(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, ctsPin);
+#if SOC_UART_LP_NUM >= 1
+    if (ret && uart_num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
+      ret &= lp_uart_config_io(uart->num, ctsPin, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_CTS_PIN_IDX);
+    }
+#endif
+    if (ret) {
+      ret &= perimanSetPinBus(ctsPin, ESP32_BUS_TYPE_UART_CTS, (void *)uart, uart_num, -1);
+      if (ret) {
+        uart->_ctsPin = ctsPin;
+      }
+    }
+    if (!ret) {
+      log_e("UART%d failed to attach CTS pin %d", uart_num, ctsPin);
+    }
+    retCode &= ret;
+  }
+  if (rtsPin >= 0) {
+    // forces a clean detaching from a previous peripheral
+    if (perimanGetPinBusType(rtsPin) != ESP32_BUS_TYPE_INIT) {
+      perimanClearPinBus(rtsPin);
+    }
+    // connect RTS Pad
+    bool ret = ESP_OK == uart_set_pin(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, rtsPin, UART_PIN_NO_CHANGE);
+#if SOC_UART_LP_NUM >= 1
+    if (ret && uart_num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
+      ret &= lp_uart_config_io(uart->num, rtsPin, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_RTS_PIN_IDX);
     }
-    pinMatrixInDetach(rxPin, false, false);
-    uartDisableInterrupt(uart);
+#endif
+    if (ret) {
+      ret &= perimanSetPinBus(rtsPin, ESP32_BUS_TYPE_UART_RTS, (void *)uart, uart_num, -1);
+      if (ret) {
+        uart->_rtsPin = rtsPin;
+      }
+    }
+    if (!ret) {
+      log_e("UART%d failed to attach RTS pin %d", uart_num, rtsPin);
+    }
+    retCode &= ret;
+  }
+  return retCode;
 }
 
-void uartDetachTx(uart_t* uart, uint8_t txPin)
-{
-    if(uart == NULL) {
-        return;
-    }
-    pinMatrixOutDetach(txPin, false, false);
+// just helper functions
+int8_t uart_get_RxPin(uint8_t uart_num) {
+  return _uart_bus_array[uart_num]._rxPin;
 }
 
-void uartAttachRx(uart_t* uart, uint8_t rxPin, bool inverted)
-{
-    if(uart == NULL || rxPin > 39) {
-        return;
-    }
-    pinMode(rxPin, INPUT);
-    pinMatrixInAttach(rxPin, UART_RXD_IDX(uart->num), inverted);
-    uartEnableInterrupt(uart);
+int8_t uart_get_TxPin(uint8_t uart_num) {
+  return _uart_bus_array[uart_num]._txPin;
 }
 
-void uartAttachTx(uart_t* uart, uint8_t txPin, bool inverted)
-{
-    if(uart == NULL || txPin > 39) {
-        return;
-    }
-    pinMode(txPin, OUTPUT);
-    pinMatrixOutAttach(txPin, UART_TXD_IDX(uart->num), inverted, false);
+void uart_init_PeriMan(void) {
+  // set Peripheral Manager deInit Callback for each UART pin
+  perimanSetBusDeinit(ESP32_BUS_TYPE_UART_RX, _uartDetachBus_RX);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_UART_TX, _uartDetachBus_TX);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_UART_CTS, _uartDetachBus_CTS);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_UART_RTS, _uartDetachBus_RTS);
 }
 
-uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint16_t queueLen, bool inverted)
-{
-    if(uart_nr > 2) {
-        return NULL;
-    }
+// Routines that take care of UART events will be in the HardwareSerial Class code
+void uartGetEventQueue(uart_t *uart, QueueHandle_t *q) {
+  // passing back NULL for the Queue pointer when UART is not initialized yet
+  *q = NULL;
+  if (uart == NULL) {
+    return;
+  }
+  *q = uart->uart_event_queue;
+  return;
+}
+
+bool uartIsDriverInstalled(uart_t *uart) {
+  if (uart == NULL) {
+    return false;
+  }
+
+  if (uart_is_driver_installed(uart->num)) {
+    return true;
+  }
+  return false;
+}
+
+// Negative Pin Number will keep it unmodified, thus this function can set individual pins
+// When pins are changed, it will detach the previous one
+bool uartSetPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin) {
+  if (uart_num >= SOC_UART_NUM) {
+    log_e("Serial number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1);
+    return false;
+  }
+  // get UART information
+  uart_t *uart = &_uart_bus_array[uart_num];
+
+#if SOC_UART_LP_NUM >= 1
+  // check if LP UART is being used and if the pins are valid
+  if (!lpuartCheckPins(rxPin, txPin, ctsPin, rtsPin, uart_num)) {
+    return false;  // failed to set pins
+  }
+#endif
+
+  bool retCode = true;
+  UART_MUTEX_LOCK();
+
+  //log_v("setting UART%d pins: prev->new RX(%d->%d) TX(%d->%d) CTS(%d->%d) RTS(%d->%d)", uart_num,
+  //        uart->_rxPin, rxPin, uart->_txPin, txPin, uart->_ctsPin, ctsPin, uart->_rtsPin, rtsPin); vTaskDelay(10);
+
+  // First step: detaches all previous UART pins
+  bool rxPinChanged = rxPin >= 0 && rxPin != uart->_rxPin;
+  if (rxPinChanged) {
+    retCode &= _uartDetachPins(uart_num, uart->_rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+  }
+  bool txPinChanged = txPin >= 0 && txPin != uart->_txPin;
+  if (txPinChanged) {
+    retCode &= _uartDetachPins(uart_num, UART_PIN_NO_CHANGE, uart->_txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+  }
+  bool ctsPinChanged = ctsPin >= 0 && ctsPin != uart->_ctsPin;
+  if (ctsPinChanged) {
+    retCode &= _uartDetachPins(uart_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, uart->_ctsPin, UART_PIN_NO_CHANGE);
+  }
+  bool rtsPinChanged = rtsPin >= 0 && rtsPin != uart->_rtsPin;
+  if (rtsPinChanged) {
+    retCode &= _uartDetachPins(uart_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, uart->_rtsPin);
+  }
+
+  // Second step: attach all UART new pins
+  if (rxPinChanged) {
+    retCode &= _uartAttachPins(uart_num, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+  }
+  if (txPinChanged) {
+    retCode &= _uartAttachPins(uart_num, UART_PIN_NO_CHANGE, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+  }
+  if (ctsPinChanged) {
+    retCode &= _uartAttachPins(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, ctsPin, UART_PIN_NO_CHANGE);
+  }
+  if (rtsPinChanged) {
+    retCode &= _uartAttachPins(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, rtsPin);
+  }
+  UART_MUTEX_UNLOCK();
+
+  if (!retCode) {
+    log_e("UART%d set pins failed.", uart_num);
+  }
+  return retCode;
+}
 
-    if(rxPin == -1 && txPin == -1) {
-        return NULL;
+//
+bool uartSetHwFlowCtrlMode(uart_t *uart, uart_hw_flowcontrol_t mode, uint8_t threshold) {
+  if (uart == NULL) {
+    return false;
+  }
+  // IDF will issue corresponding error message when mode or threshold are wrong and prevent crashing
+  // IDF will check (mode > HW_FLOWCTRL_CTS_RTS || threshold >= SOC_UART_FIFO_LEN)
+  UART_MUTEX_LOCK();
+  bool retCode = (ESP_OK == uart_set_hw_flow_ctrl(uart->num, mode, threshold));
+  UART_MUTEX_UNLOCK();
+  return retCode;
+}
+
+// This helper function will return true if a new IDF UART driver needs to be restarted and false if the current one can continue its execution
+bool _testUartBegin(
+  uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint32_t rx_buffer_size, uint32_t tx_buffer_size, bool inverted,
+  uint8_t rxfifo_full_thrhd
+) {
+  if (uart_nr >= SOC_UART_NUM) {
+    return false;  // no new driver has to be installed
+  }
+  uart_t *uart = &_uart_bus_array[uart_nr];
+  // verify if is necessary to restart the UART driver
+  if (uart_is_driver_installed(uart_nr)) {
+    // some parameters can't be changed unless we end the UART driver
+    if (uart->_rx_buffer_size != rx_buffer_size || uart->_tx_buffer_size != tx_buffer_size || uart->_inverted != inverted
+        || uart->_rxfifo_full_thrhd != rxfifo_full_thrhd) {
+      return true;  // the current IDF UART driver must be terminated and a new driver shall be installed
+    } else {
+      return false;  // The current IDF UART driver can continue its execution
     }
+  } else {
+    return true;  // no IDF UART driver is running and a new driver shall be installed
+  }
+}
 
-    uart_t* uart = &_uart_bus_array[uart_nr];
+uart_t *uartBegin(
+  uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint32_t rx_buffer_size, uint32_t tx_buffer_size, bool inverted,
+  uint8_t rxfifo_full_thrhd
+) {
+  if (uart_nr >= SOC_UART_NUM) {
+    log_e("UART number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1);
+    return NULL;  // no new driver was installed
+  }
+  uart_t *uart = &_uart_bus_array[uart_nr];
+  log_v("UART%d baud(%ld) Mode(%x) rxPin(%d) txPin(%d)", uart_nr, baudrate, config, rxPin, txPin);
+
+#if SOC_UART_LP_NUM >= 1
+  // check if LP UART is being used and if the pins are valid
+  if (!lpuartCheckPins(rxPin, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, uart_nr)) {
+    if (uart_is_driver_installed(uart_nr)) {
+      return uart;  // keep the same installed driver
+    } else {
+      return NULL;  // no new driver was installed
+    }
+  }
+#endif
 
 #if !CONFIG_DISABLE_HAL_LOCKS
-    if(uart->lock == NULL) {
-        uart->lock = xSemaphoreCreateMutex();
-        if(uart->lock == NULL) {
-            return NULL;
-        }
+  if (uart->lock == NULL) {
+    uart->lock = xSemaphoreCreateMutex();
+    if (uart->lock == NULL) {
+      log_e("HAL LOCK error.");
+      return NULL;  // no new driver was installed
     }
+  }
 #endif
 
-    if(queueLen && uart->queue == NULL) {
-        uart->queue = xQueueCreate(queueLen, sizeof(uint8_t)); //initialize the queue
-        if(uart->queue == NULL) {
-            return NULL;
+  if (uart_is_driver_installed(uart_nr)) {
+    log_v("UART%d Driver already installed.", uart_nr);
+    // some parameters can't be changed unless we end the UART driver
+    if (uart->_rx_buffer_size != rx_buffer_size || uart->_tx_buffer_size != tx_buffer_size || uart->_inverted != inverted
+        || uart->_rxfifo_full_thrhd != rxfifo_full_thrhd) {
+      log_v("UART%d changing buffer sizes or inverted signal or rxfifo_full_thrhd. IDF driver will be restarted", uart_nr);
+      log_v("RX buffer size: %d -> %d", uart->_rx_buffer_size, rx_buffer_size);
+      log_v("TX buffer size: %d -> %d", uart->_tx_buffer_size, tx_buffer_size);
+      log_v("Inverted signal: %s -> %s", uart->_inverted ? "true" : "false", inverted ? "true" : "false");
+      log_v("RX FIFO full threshold: %d -> %d", uart->_rxfifo_full_thrhd, rxfifo_full_thrhd);
+      uartEnd(uart_nr);
+    } else {
+      bool retCode = true;
+      //User may just want to change some parameters, such as baudrate, data length, parity, stop bits or pins
+      if (uart->_baudrate != baudrate) {
+        retCode = uartSetBaudRate(uart, baudrate);
+      }
+      UART_MUTEX_LOCK();
+      uart_word_length_t data_bits = (config & 0xc) >> 2;
+      uart_parity_t parity = config & 0x3;
+      uart_stop_bits_t stop_bits = (config & 0x30) >> 4;
+      if (retCode && (uart->_config & 0xc) >> 2 != data_bits) {
+        if (ESP_OK != uart_set_word_length(uart_nr, data_bits)) {
+          log_e("UART%d changing data length failed.", uart_nr);
+          retCode = false;
+        } else {
+          log_v("UART%d changed data length to %d", uart_nr, data_bits + 5);
+        }
+      }
+      if (retCode && (uart->_config & 0x3) != parity) {
+        if (ESP_OK != uart_set_parity(uart_nr, parity)) {
+          log_e("UART%d changing parity failed.", uart_nr);
+          retCode = false;
+        } else {
+          log_v("UART%d changed parity to %s", uart_nr, parity == 0 ? "NONE" : parity == 2 ? "EVEN" : "ODD");
+        }
+      }
+      if (retCode && (uart->_config & 0xc30) >> 4 != stop_bits) {
+        if (ESP_OK != uart_set_stop_bits(uart_nr, stop_bits)) {
+          log_e("UART%d changing stop bits failed.", uart_nr);
+          retCode = false;
+        } else {
+          log_v("UART%d changed stop bits to %d", uart_nr, stop_bits == 3 ? 2 : 1);
+        }
+      }
+      if (retCode) {
+        uart->_config = config;
+      }
+      if (retCode && rxPin > 0 && uart->_rxPin != rxPin) {
+        retCode &= _uartDetachPins(uart_nr, uart->_rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+        retCode &= _uartAttachPins(uart_nr, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+        if (!retCode) {
+          log_e("UART%d changing RX pin failed.", uart_nr);
+        } else {
+          log_v("UART%d changed RX pin to %d", uart_nr, rxPin);
+        }
+      }
+      if (retCode && txPin > 0 && uart->_txPin != txPin) {
+        retCode &= _uartDetachPins(uart_nr, UART_PIN_NO_CHANGE, uart->_txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+        retCode &= _uartAttachPins(uart_nr, UART_PIN_NO_CHANGE, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+        if (!retCode) {
+          log_e("UART%d changing TX pin failed.", uart_nr);
+        } else {
+          log_v("UART%d changed TX pin to %d", uart_nr, txPin);
         }
+      }
+      UART_MUTEX_UNLOCK();
+      if (retCode) {
+        // UART driver was already working, just return the uart_t structure, saying that no new driver was installed
+        return uart;
+      }
+      // if we reach this point, it means that we need to restart the UART driver
+      uartEnd(uart_nr);
     }
-    if(uart_nr == 1){
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART1_CLK_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
-    } else if(uart_nr == 2){
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART2_CLK_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
+  } else {
+    log_v("UART%d not installed. Starting installation", uart_nr);
+  }
+  uart_config_t uart_config;
+  memset(&uart_config, 0, sizeof(uart_config_t));
+  uart_config.flags.backup_before_sleep = false;  // new flag from IDF v5.3
+  uart_config.data_bits = (config & 0xc) >> 2;
+  uart_config.parity = (config & 0x3);
+  uart_config.stop_bits = (config & 0x30) >> 4;
+  uart_config.flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
+  uart_config.rx_flow_ctrl_thresh = rxfifo_full_thrhd >= UART_HW_FIFO_LEN(uart_nr) ? UART_HW_FIFO_LEN(uart_nr) - 6 : rxfifo_full_thrhd;
+  log_v(
+    "UART%d RX FIFO full threshold set to %d (value requested: %d || FIFO Max = %d)", uart_nr, uart_config.rx_flow_ctrl_thresh, rxfifo_full_thrhd,
+    UART_HW_FIFO_LEN(uart_nr)
+  );
+  rxfifo_full_thrhd = uart_config.rx_flow_ctrl_thresh;  // makes sure that it will be set correctly in the struct
+  uart_config.baud_rate = baudrate;
+#if SOC_UART_LP_NUM >= 1
+  if (uart_nr >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
+    if (uart->_uart_clock_source > 0) {
+      uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source;  // use user defined LP UART clock
+      log_v("Setting UART%d to user defined LP clock source (%d) ", uart_nr, uart->_uart_clock_source);
     } else {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_UART_CLK_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
+      uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT;  // use default LP clock
+      log_v("Setting UART%d to Default LP clock source", uart_nr);
     }
-    uartFlush(uart);
-    uartSetBaudRate(uart, baudrate);
-    UART_MUTEX_LOCK();
-    uart->dev->conf0.val = config;
-    #define TWO_STOP_BITS_CONF 0x3
-    #define ONE_STOP_BITS_CONF 0x1
-
-    if ( uart->dev->conf0.stop_bit_num == TWO_STOP_BITS_CONF) {
-        uart->dev->conf0.stop_bit_num = ONE_STOP_BITS_CONF;
-        uart->dev->rs485_conf.dl1_en = 1;
+  } else
+#endif  // SOC_UART_LP_NUM >= 1
+  {
+    if (uart->_uart_clock_source >= 0) {
+      uart_config.source_clk = (soc_module_clk_t)uart->_uart_clock_source;  // use user defined HP UART clock
+      log_v("Setting UART%d to user defined HP clock source (%d) ", uart_nr, uart->_uart_clock_source);
+    } else {
+      // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
+      // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
+#if SOC_UART_SUPPORT_XTAL_CLK
+      uart_config.source_clk = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
+      log_v("Setting UART%d to use XTAL clock", uart_nr);
+#elif SOC_UART_SUPPORT_REF_TICK
+      if (baudrate <= REF_TICK_BAUDRATE_LIMIT) {
+        uart_config.source_clk = UART_SCLK_REF_TICK;  // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
+        log_v("Setting UART%d to use REF_TICK clock", uart_nr);
+      } else {
+        uart_config.source_clk = UART_SCLK_APB;  // baudrate may change with the APB Frequency!
+        log_v("Setting UART%d to use APB clock", uart_nr);
+      }
+#else
+      // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
+      uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
+      log_v("Setting UART%d to use DEFAULT clock", uart_nr);
+#endif  // SOC_UART_SUPPORT_XTAL_CLK
     }
+  }
 
-    // tx_idle_num : idle interval after tx FIFO is empty(unit: the time it takes to send one bit under current baudrate)
-    // Setting it to 0 prevents line idle time/delays when sending messages with small intervals
-    uart->dev->idle_conf.tx_idle_num = 0;  //
+  UART_MUTEX_LOCK();
+  bool retCode = ESP_OK == uart_driver_install(uart_nr, rx_buffer_size, tx_buffer_size, 20, &(uart->uart_event_queue), 0);
 
-    UART_MUTEX_UNLOCK();
+  if (retCode) {
+    retCode &= ESP_OK == uart_param_config(uart_nr, &uart_config);
+  }
 
-    if(rxPin != -1) {
-        uartAttachRx(uart, rxPin, inverted);
+  if (retCode) {
+    if (inverted) {
+      // invert signal for both Rx and Tx
+      retCode &= ESP_OK == uart_set_line_inverse(uart_nr, UART_SIGNAL_TXD_INV | UART_SIGNAL_RXD_INV);
+    } else {
+      // disable invert signal for both Rx and Tx
+      retCode &= ESP_OK == uart_set_line_inverse(uart_nr, UART_SIGNAL_INV_DISABLE);
     }
-
-    if(txPin != -1) {
-        uartAttachTx(uart, txPin, inverted);
+  }
+  // if all fine, set internal parameters
+  if (retCode) {
+    uart->_baudrate = baudrate;
+    uart->_config = config;
+    uart->_inverted = inverted;
+    uart->_rxfifo_full_thrhd = rxfifo_full_thrhd;
+    uart->_rx_buffer_size = rx_buffer_size;
+    uart->_tx_buffer_size = tx_buffer_size;
+    uart->has_peek = false;
+    uart->peek_byte = 0;
+#if SOC_UART_LP_NUM >= 1
+    if (uart_nr >= SOC_UART_HP_NUM) {
+      uart->_uart_clock_source = uart_config.lp_source_clk;
+    } else
+#endif
+    {
+      uart->_uart_clock_source = uart_config.source_clk;
     }
-    addApbChangeCallback(uart, uart_on_apb_change);
-    return uart;
+  }
+  UART_MUTEX_UNLOCK();
+
+  // uartSetPins detaches previous pins if new ones are used over a previous begin()
+  if (retCode) {
+    retCode &= uartSetPins(uart_nr, rxPin, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+  }
+  if (!retCode) {
+    log_e("UART%d initialization error.", uart->num);
+    uartEnd(uart_nr);
+    uart = NULL;
+  } else {
+    uartFlush(uart);
+    log_v("UART%d initialization done.", uart->num);
+  }
+  return uart;  // a new driver was installed
 }
 
-void uartEnd(uart_t* uart, uint8_t txPin, uint8_t rxPin)
-{
-    if(uart == NULL) {
-        return;
-    }
-    removeApbChangeCallback(uart, uart_on_apb_change);
-
-    UART_MUTEX_LOCK();
-    if(uart->queue != NULL) {
-        vQueueDelete(uart->queue);
-        uart->queue = NULL;
-    }
-
-    uart->dev->conf0.val = 0;
-
-    UART_MUTEX_UNLOCK();
+// This function code is under testing - for now just keep it here
+void uartSetFastReading(uart_t *uart) {
+  if (uart == NULL) {
+    return;
+  }
+
+  UART_MUTEX_LOCK();
+  // override default RX IDF Driver Interrupt - no BREAK, PARITY or OVERFLOW
+  uart_intr_config_t uart_intr = {
+    .intr_enable_mask = UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT,  // only these IRQs - no BREAK, PARITY or OVERFLOW
+    .rx_timeout_thresh = 1,
+    .txfifo_empty_intr_thresh = 10,
+    .rxfifo_full_thresh = 2,
+  };
+
+  ESP_ERROR_CHECK(uart_intr_config(uart->num, &uart_intr));
+  UART_MUTEX_UNLOCK();
+}
 
-    uartDetachRx(uart, rxPin);
-    uartDetachTx(uart, txPin);
+bool uartSetRxTimeout(uart_t *uart, uint8_t numSymbTimeout) {
+  if (uart == NULL) {
+    return false;
+  }
+  uint16_t maxRXTimeout = uart_get_max_rx_timeout(uart->num);
+  if (numSymbTimeout > maxRXTimeout) {
+    log_e("Invalid RX Timeout value, its limit is %d", maxRXTimeout);
+    return false;
+  }
+  UART_MUTEX_LOCK();
+  bool retCode = (ESP_OK == uart_set_rx_timeout(uart->num, numSymbTimeout));
+  UART_MUTEX_UNLOCK();
+  return retCode;
 }
 
-size_t uartResizeRxBuffer(uart_t * uart, size_t new_size) {
-    if(uart == NULL) {
-        return 0;
+bool uartSetRxFIFOFull(uart_t *uart, uint8_t numBytesFIFOFull) {
+  if (uart == NULL) {
+    return false;
+  }
+  uint8_t rxfifo_full_thrhd = numBytesFIFOFull >= UART_HW_FIFO_LEN(uart->num) ? UART_HW_FIFO_LEN(uart->num) - 6 : numBytesFIFOFull;
+  UART_MUTEX_LOCK();
+  bool retCode = (ESP_OK == uart_set_rx_full_threshold(uart->num, rxfifo_full_thrhd));
+  if (retCode) {
+    uart->_rxfifo_full_thrhd = rxfifo_full_thrhd;
+    if (rxfifo_full_thrhd != numBytesFIFOFull) {
+      log_w("The RX FIFO Full value for UART%d was set to %d instead of %d", uart->num, rxfifo_full_thrhd, numBytesFIFOFull);
     }
+    log_v("UART%d RX FIFO Full value set to %d from a requested value of %d", uart->num, rxfifo_full_thrhd, numBytesFIFOFull);
+  } else {
+    log_e("UART%d failed to set RX FIFO Full value to %d", uart->num, numBytesFIFOFull);
+  }
+  UART_MUTEX_UNLOCK();
+  return retCode;
+}
 
-    UART_MUTEX_LOCK();
-    if(uart->queue != NULL) {
-        vQueueDelete(uart->queue);
-        uart->queue = xQueueCreate(new_size, sizeof(uint8_t));
-        if(uart->queue == NULL) {
-            UART_MUTEX_UNLOCK();
-            return NULL;
-        }
-    }
-    UART_MUTEX_UNLOCK();
+void uartEnd(uint8_t uart_num) {
+  if (uart_num >= SOC_UART_NUM) {
+    log_e("Serial number is invalid, please use number from 0 to %u", SOC_UART_NUM - 1);
+    return;
+  }
+  // get UART information
+  uart_t *uart = &_uart_bus_array[uart_num];
+
+  UART_MUTEX_LOCK();
+  _uartDetachPins(uart_num, uart->_rxPin, uart->_txPin, uart->_ctsPin, uart->_rtsPin);
+  if (uart_is_driver_installed(uart_num)) {
+    uart_driver_delete(uart_num);
+  }
+  UART_MUTEX_UNLOCK();
+}
 
-    return new_size;
+void uartSetRxInvert(uart_t *uart, bool invert) {
+  if (uart == NULL) {
+    return;
+  }
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+  // POTENTIAL ISSUE :: original code only set/reset rxd_inv bit
+  // IDF or LL set/reset the whole inv_mask!
+  // if (invert)
+  //     ESP_ERROR_CHECK(uart_set_line_inverse(uart->num, UART_SIGNAL_RXD_INV));
+  // else
+  //     ESP_ERROR_CHECK(uart_set_line_inverse(uart->num, UART_SIGNAL_INV_DISABLE));
+  log_e("uartSetRxInvert is not supported in ESP32C6, ESP32H2 and ESP32P4");
+#else
+  // this implementation is better over IDF API because it only affects RXD
+  // this is supported in ESP32, ESP32-S2 and ESP32-C3
+  uart_dev_t *hw = UART_LL_GET_HW(uart->num);
+  if (invert) {
+    hw->conf0.rxd_inv = 1;
+  } else {
+    hw->conf0.rxd_inv = 0;
+  }
+#endif
 }
 
-void uartSetRxInvert(uart_t* uart, bool invert)
-{
-    if (uart == NULL)
-        return;
-    
-    if (invert)
-        uart->dev->conf0.rxd_inv = 1;
-    else
-        uart->dev->conf0.rxd_inv = 0;
+uint32_t uartAvailable(uart_t *uart) {
+
+  if (uart == NULL) {
+    return 0;
+  }
+
+  UART_MUTEX_LOCK();
+  size_t available;
+  uart_get_buffered_data_len(uart->num, &available);
+  if (uart->has_peek) {
+    available++;
+  }
+  UART_MUTEX_UNLOCK();
+  return available;
 }
 
-uint32_t uartAvailable(uart_t* uart)
-{
-    if(uart == NULL || uart->queue == NULL) {
-        return 0;
-    }
-    return (uxQueueMessagesWaiting(uart->queue) + uart->dev->status.rxfifo_cnt) ;
+uint32_t uartAvailableForWrite(uart_t *uart) {
+  if (uart == NULL) {
+    return 0;
+  }
+  UART_MUTEX_LOCK();
+  uint32_t available = uart_ll_get_txfifo_len(UART_LL_GET_HW(uart->num));
+  size_t txRingBufferAvailable = 0;
+  if (ESP_OK == uart_get_tx_buffer_free_size(uart->num, &txRingBufferAvailable)) {
+    available = txRingBufferAvailable == 0 ? available : txRingBufferAvailable;
+  }
+  UART_MUTEX_UNLOCK();
+  return available;
 }
 
-uint32_t uartAvailableForWrite(uart_t* uart)
-{
-    if(uart == NULL) {
-        return 0;
+size_t uartReadBytes(uart_t *uart, uint8_t *buffer, size_t size, uint32_t timeout_ms) {
+  if (uart == NULL || size == 0 || buffer == NULL) {
+    return 0;
+  }
+
+  size_t bytes_read = 0;
+
+  UART_MUTEX_LOCK();
+
+  if (uart->has_peek) {
+    uart->has_peek = false;
+    *buffer++ = uart->peek_byte;
+    size--;
+    bytes_read = 1;
+  }
+
+  if (size > 0) {
+    int len = uart_read_bytes(uart->num, buffer, size, pdMS_TO_TICKS(timeout_ms));
+    if (len < 0) {
+      len = 0;  // error reading UART
     }
-    return 0x7f - uart->dev->status.txfifo_cnt;
-}
+    bytes_read += len;
+  }
 
-void uartRxFifoToQueue(uart_t* uart)
-{
-	uint8_t c;
-    UART_MUTEX_LOCK();
-	//disable interrupts
-	uart->dev->int_ena.val = 0;
-	uart->dev->int_clr.val = 0xffffffff;
-	while (uart->dev->status.rxfifo_cnt || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
-		c = uart->dev->fifo.rw_byte;
-		xQueueSend(uart->queue, &c, 0);
-	}
-	//enable interrupts
-	uart->dev->int_ena.rxfifo_full = 1;
-	uart->dev->int_ena.frm_err = 1;
-	uart->dev->int_ena.rxfifo_tout = 1;
-	uart->dev->int_clr.val = 0xffffffff;
-    UART_MUTEX_UNLOCK();
+  UART_MUTEX_UNLOCK();
+  return bytes_read;
 }
 
-uint8_t uartRead(uart_t* uart)
-{
-    if(uart == NULL || uart->queue == NULL) {
-        return 0;
-    }
-    uint8_t c;
-    if ((uxQueueMessagesWaiting(uart->queue) == 0) && (uart->dev->status.rxfifo_cnt > 0))
-    {
-    	uartRxFifoToQueue(uart);
-    }
-    if(xQueueReceive(uart->queue, &c, 0)) {
-        return c;
-    }
+// DEPRECATED but the original code will be kepts here as future reference when a final solution
+// to the UART driver is defined in the use case of reading byte by byte from UART.
+uint8_t uartRead(uart_t *uart) {
+  if (uart == NULL) {
     return 0;
-}
+  }
+  uint8_t c = 0;
 
-uint8_t uartPeek(uart_t* uart)
-{
-    if(uart == NULL || uart->queue == NULL) {
-        return 0;
-    }
-    uint8_t c;
-    if ((uxQueueMessagesWaiting(uart->queue) == 0) && (uart->dev->status.rxfifo_cnt > 0))
-    {
-    	uartRxFifoToQueue(uart);
-    }
-    if(xQueuePeek(uart->queue, &c, 0)) {
-        return c;
+  UART_MUTEX_LOCK();
+
+  if (uart->has_peek) {
+    uart->has_peek = false;
+    c = uart->peek_byte;
+  } else {
+
+    int len = uart_read_bytes(uart->num, &c, 1, 20 / portTICK_PERIOD_MS);
+    if (len <= 0) {  // includes negative return from IDF in case of error
+      c = 0;
     }
-    return 0;
+  }
+  UART_MUTEX_UNLOCK();
+  return c;
 }
 
-void uartWrite(uart_t* uart, uint8_t c)
-{
-    if(uart == NULL) {
-        return;
+uint8_t uartPeek(uart_t *uart) {
+  if (uart == NULL) {
+    return 0;
+  }
+  uint8_t c = 0;
+
+  UART_MUTEX_LOCK();
+
+  if (uart->has_peek) {
+    c = uart->peek_byte;
+  } else {
+    int len = uart_read_bytes(uart->num, &c, 1, 20 / portTICK_PERIOD_MS);
+    if (len <= 0) {  // includes negative return from IDF in case of error
+      c = 0;
+    } else {
+      uart->has_peek = true;
+      uart->peek_byte = c;
     }
-    UART_MUTEX_LOCK();
-    while(uart->dev->status.txfifo_cnt == 0x7F);
-    uart->dev->fifo.rw_byte = c;
-    UART_MUTEX_UNLOCK();
+  }
+  UART_MUTEX_UNLOCK();
+  return c;
 }
 
-void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len)
-{
-    if(uart == NULL) {
-        return;
-    }
-    UART_MUTEX_LOCK();
-    while(len) {
-        while(uart->dev->status.txfifo_cnt == 0x7F);
-        uart->dev->fifo.rw_byte = *data++;
-        len--;
-    }
-    UART_MUTEX_UNLOCK();
+void uartWrite(uart_t *uart, uint8_t c) {
+  if (uart == NULL) {
+    return;
+  }
+  UART_MUTEX_LOCK();
+  uart_write_bytes(uart->num, &c, 1);
+  UART_MUTEX_UNLOCK();
+}
+
+void uartWriteBuf(uart_t *uart, const uint8_t *data, size_t len) {
+  if (uart == NULL || data == NULL || !len) {
+    return;
+  }
+
+  UART_MUTEX_LOCK();
+  uart_write_bytes(uart->num, data, len);
+  UART_MUTEX_UNLOCK();
 }
 
-void uartFlush(uart_t* uart)
-{
-    uartFlushTxOnly(uart,true);
+void uartFlush(uart_t *uart) {
+  uartFlushTxOnly(uart, true);
 }
 
-void uartFlushTxOnly(uart_t* uart, bool txOnly)
-{
-    if(uart == NULL) {
-        return;
-    }
+void uartFlushTxOnly(uart_t *uart, bool txOnly) {
+  if (uart == NULL) {
+    return;
+  }
 
-    UART_MUTEX_LOCK();
-    while(uart->dev->status.txfifo_cnt || uart->dev->status.st_utx_out);
-    
-    if( !txOnly ){
-        //Due to hardware issue, we can not use fifo_rst to reset uart fifo.
-        //See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
+  UART_MUTEX_LOCK();
+  while (!uart_ll_is_tx_idle(UART_LL_GET_HW(uart->num)));
 
-        // we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
-        while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
-            READ_PERI_REG(UART_FIFO_REG(uart->num));
-        }
+  if (!txOnly) {
+    ESP_ERROR_CHECK(uart_flush_input(uart->num));
+  }
+  UART_MUTEX_UNLOCK();
+}
 
-        xQueueReset(uart->queue);
-    }
-    
-    UART_MUTEX_UNLOCK();
-}
-
-void uartSetBaudRate(uart_t* uart, uint32_t baud_rate)
-{
-    if(uart == NULL) {
-        return;
-    }
-    UART_MUTEX_LOCK();
-    uint32_t clk_div = ((getApbFrequency()<<4)/baud_rate);
-    uart->dev->clk_div.div_int = clk_div>>4 ;
-    uart->dev->clk_div.div_frag = clk_div & 0xf;
-    UART_MUTEX_UNLOCK();
-}
-
-static void uart_on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb)
-{
-    uart_t* uart = (uart_t*)arg;
-    if(ev_type == APB_BEFORE_CHANGE){
-        UART_MUTEX_LOCK();
-        //disabple interrupt
-        uart->dev->int_ena.val = 0;
-        uart->dev->int_clr.val = 0xffffffff;
-        // read RX fifo
-        uint8_t c;
-   //     BaseType_t xHigherPriorityTaskWoken;
-        while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
-            c = uart->dev->fifo.rw_byte;
-            if(uart->queue != NULL ) {
-                xQueueSend(uart->queue, &c, 1); //&xHigherPriorityTaskWoken);
-            }
-        }
-        UART_MUTEX_UNLOCK();
- 
-        // wait TX empty
-        while(uart->dev->status.txfifo_cnt || uart->dev->status.st_utx_out);
+bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
+  if (uart == NULL) {
+    return false;
+  }
+  bool retCode = true;
+  soc_module_clk_t newClkSrc = UART_SCLK_DEFAULT;
+  int8_t previousClkSrc = uart->_uart_clock_source;
+#if SOC_UART_LP_NUM >= 1
+  if (uart->num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
+    if (uart->_uart_clock_source > 0) {
+      newClkSrc = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source;  // use user defined LP UART clock
+      log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc);
+    } else {
+      newClkSrc = LP_UART_SCLK_DEFAULT;  // use default LP clock
+      log_v("Setting UART%d to Default LP clock source", uart->num);
+    }
+  } else
+#endif  // SOC_UART_LP_NUM >= 1
+  {
+    if (uart->_uart_clock_source >= 0) {
+      newClkSrc = (soc_module_clk_t)uart->_uart_clock_source;  // use user defined HP UART clock
+      log_v("Setting UART%d to use HP clock source (%d) ", uart->num, newClkSrc);
     } else {
-        //todo:
-        // set baudrate
-        UART_MUTEX_LOCK();
-        uint32_t clk_div = (uart->dev->clk_div.div_int << 4) | (uart->dev->clk_div.div_frag & 0x0F);
-        uint32_t baud_rate = ((old_apb<<4)/clk_div);
-        clk_div = ((new_apb<<4)/baud_rate);
-        uart->dev->clk_div.div_int = clk_div>>4 ;
-        uart->dev->clk_div.div_frag = clk_div & 0xf;
-        //enable interrupts
-        uart->dev->int_ena.rxfifo_full = 1;
-        uart->dev->int_ena.frm_err = 1;
-        uart->dev->int_ena.rxfifo_tout = 1;
-        uart->dev->int_clr.val = 0xffffffff;
-        UART_MUTEX_UNLOCK();
+      // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
+      // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
+#if SOC_UART_SUPPORT_XTAL_CLK
+      newClkSrc = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
+      log_v("Setting UART%d to use XTAL clock", uart->num);
+#elif SOC_UART_SUPPORT_REF_TICK
+      if (baud_rate <= REF_TICK_BAUDRATE_LIMIT) {
+        newClkSrc = UART_SCLK_REF_TICK;  // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
+        log_v("Setting UART%d to use REF_TICK clock", uart->num);
+      } else {
+        newClkSrc = UART_SCLK_APB;  // baudrate may change with the APB Frequency!
+        log_v("Setting UART%d to use APB clock", uart->num);
+      }
+#else
+      // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
+      // using newClkSrc = UART_SCLK_DEFAULT as defined in the variable declaration
+      log_v("Setting UART%d to use DEFAULT clock", uart->num);
+#endif  // SOC_UART_SUPPORT_XTAL_CLK
     }
+  }
+  UART_MUTEX_LOCK();
+  // if necessary, set the correct UART Clock Source before changing the baudrate
+  if (previousClkSrc < 0 || previousClkSrc != newClkSrc) {
+    HP_UART_SRC_CLK_ATOMIC() {
+      uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
+    }
+    uart->_uart_clock_source = newClkSrc;
+  }
+  if (uart_set_baudrate(uart->num, baud_rate) == ESP_OK) {
+    log_v("Setting UART%d baud rate to %ld.", uart->num, baud_rate);
+    uart->_baudrate = baud_rate;
+  } else {
+    retCode = false;
+    log_e("Setting UART%d baud rate to %ld has failed.", uart->num, baud_rate);
+  }
+  UART_MUTEX_UNLOCK();
+  return retCode;
 }
 
-uint32_t uartGetBaudRate(uart_t* uart)
-{
-    if(uart == NULL) {
-        return 0;
-    }
+uint32_t uartGetBaudRate(uart_t *uart) {
+  uint32_t baud_rate = 0;
 
-    uint32_t clk_div = (uart->dev->clk_div.div_int << 4) | (uart->dev->clk_div.div_frag & 0x0F);
-    if(!clk_div) {
-        return 0;
-    }
+  if (uart == NULL) {
+    return 0;
+  }
+
+  UART_MUTEX_LOCK();
+  if (uart_get_baudrate(uart->num, &baud_rate) != ESP_OK) {
+    log_e("Getting UART%d baud rate has failed.", uart->num);
+    baud_rate = (uint32_t)-1;  // return value when failed
+  }
+  UART_MUTEX_UNLOCK();
+  return baud_rate;
+}
 
-    return ((getApbFrequency()<<4)/clk_div);
+static void ARDUINO_ISR_ATTR uart0_write_char(char c) {
+  while (uart_ll_get_txfifo_len(&UART0) == 0);
+  uart_ll_write_txfifo(&UART0, (const uint8_t *)&c, 1);
 }
 
-static void IRAM_ATTR uart0_write_char(char c)
-{
-    while(((ESP_REG(0x01C+DR_REG_UART_BASE) >> UART_TXFIFO_CNT_S) & 0x7F) == 0x7F);
-    ESP_REG(DR_REG_UART_BASE) = c;
+#if SOC_UART_HP_NUM > 1
+static void ARDUINO_ISR_ATTR uart1_write_char(char c) {
+  while (uart_ll_get_txfifo_len(&UART1) == 0);
+  uart_ll_write_txfifo(&UART1, (const uint8_t *)&c, 1);
 }
+#endif
 
-static void IRAM_ATTR uart1_write_char(char c)
-{
-    while(((ESP_REG(0x01C+DR_REG_UART1_BASE) >> UART_TXFIFO_CNT_S) & 0x7F) == 0x7F);
-    ESP_REG(DR_REG_UART1_BASE) = c;
+#if SOC_UART_HP_NUM > 2
+static void ARDUINO_ISR_ATTR uart2_write_char(char c) {
+  while (uart_ll_get_txfifo_len(&UART2) == 0);
+  uart_ll_write_txfifo(&UART2, (const uint8_t *)&c, 1);
 }
+#endif
 
-static void IRAM_ATTR uart2_write_char(char c)
-{
-    while(((ESP_REG(0x01C+DR_REG_UART2_BASE) >> UART_TXFIFO_CNT_S) & 0x7F) == 0x7F);
-    ESP_REG(DR_REG_UART2_BASE) = c;
+#if SOC_UART_HP_NUM > 3
+static void ARDUINO_ISR_ATTR uart3_write_char(char c) {
+  while (uart_ll_get_txfifo_len(&UART3) == 0);
+  uart_ll_write_txfifo(&UART3, (const uint8_t *)&c, 1);
 }
+#endif
 
-void uart_install_putc()
-{
-    switch(s_uart_debug_nr) {
-    case 0:
-        ets_install_putc1((void (*)(char)) &uart0_write_char);
-        break;
-    case 1:
-        ets_install_putc1((void (*)(char)) &uart1_write_char);
-        break;
-    case 2:
-        ets_install_putc1((void (*)(char)) &uart2_write_char);
-        break;
-    default:
-        ets_install_putc1(NULL);
-        break;
+#if SOC_UART_HP_NUM > 4
+static void ARDUINO_ISR_ATTR uart4_write_char(char c) {
+  while (uart_ll_get_txfifo_len(&UART4) == 0);
+  uart_ll_write_txfifo(&UART4, (const uint8_t *)&c, 1);
+}
+#endif
+
+void uart_install_putc() {
+  switch (s_uart_debug_nr) {
+    case 0: ets_install_putc1((void (*)(char)) & uart0_write_char); break;
+#if SOC_UART_HP_NUM > 1
+    case 1: ets_install_putc1((void (*)(char)) & uart1_write_char); break;
+#endif
+#if SOC_UART_HP_NUM > 2
+    case 2: ets_install_putc1((void (*)(char)) & uart2_write_char); break;
+#endif
+#if SOC_UART_HP_NUM > 3
+    case 3: ets_install_putc1((void (*)(char)) & uart3_write_char); break;
+#endif
+#if SOC_UART_HP_NUM > 4
+    case 4: ets_install_putc1((void (*)(char)) & uart4_write_char); break;
+#endif
+    default: ets_install_putc1(NULL); break;
+  }
+  ets_install_putc2(NULL);
+}
+
+// Routines that take care of UART mode in the HardwareSerial Class code
+// used to set UART_MODE_RS485_HALF_DUPLEX auto RTS for TXD for ESP32 chips
+bool uartSetMode(uart_t *uart, uart_mode_t mode) {
+  if (uart == NULL || uart->num >= SOC_UART_NUM) {
+    return false;
+  }
+
+  UART_MUTEX_LOCK();
+  bool retCode = (ESP_OK == uart_set_mode(uart->num, mode));
+  UART_MUTEX_UNLOCK();
+  return retCode;
+}
+
+// this function will set the uart clock source
+// it must be called before uartBegin(), otherwise it won't change any thing.
+bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc) {
+  if (uartNum >= SOC_UART_NUM) {
+    log_e("UART%d is invalid. This device has %d UARTs, from 0 to %d.", uartNum, SOC_UART_NUM, SOC_UART_NUM - 1);
+    return false;
+  }
+  uart_t *uart = &_uart_bus_array[uartNum];
+#if SOC_UART_LP_NUM >= 1
+  if (uart->num >= SOC_UART_HP_NUM) {
+    switch (clkSrc) {
+      case UART_SCLK_XTAL:    uart->_uart_clock_source = LP_UART_SCLK_XTAL_D2; break;
+      case UART_SCLK_RTC:     uart->_uart_clock_source = LP_UART_SCLK_LP_FAST; break;
+      case UART_SCLK_DEFAULT:
+      default:                uart->_uart_clock_source = LP_UART_SCLK_DEFAULT;
     }
+  } else
+#endif
+  {
+    uart->_uart_clock_source = clkSrc;
+  }
+  //log_i("UART%d set clock source to %d", uart->num, uart->_uart_clock_source);
+  return true;
 }
 
-void uartSetDebug(uart_t* uart)
-{
-    if(uart == NULL || uart->num > 2) {
-        s_uart_debug_nr = -1;
-        //ets_install_putc1(NULL);
-        //return;
-    } else
-    if(s_uart_debug_nr == uart->num) {
-        return;
-    } else
+void uartSetDebug(uart_t *uart) {
+  // LP UART is not supported for debug
+  if (uart == NULL || uart->num >= SOC_UART_HP_NUM) {
+    s_uart_debug_nr = -1;
+  } else {
     s_uart_debug_nr = uart->num;
-    uart_install_putc();
-}
-
-int uartGetDebug()
-{
-    return s_uart_debug_nr;
-}
-
-int log_printf(const char *format, ...)
-{
-    if(s_uart_debug_nr < 0){
-        return 0;
-    }
-    static char loc_buf[64];
-    char * temp = loc_buf;
-    int len;
-    va_list arg;
-    va_list copy;
-    va_start(arg, format);
-    va_copy(copy, arg);
-    len = vsnprintf(NULL, 0, format, arg);
-    va_end(copy);
-    if(len >= sizeof(loc_buf)){
-        temp = (char*)malloc(len+1);
-        if(temp == NULL) {
-            return 0;
-        }
+  }
+  uart_install_putc();
+}
+
+int uartGetDebug() {
+  return s_uart_debug_nr;
+}
+
+int log_printfv(const char *format, va_list arg) {
+  static char loc_buf[64];
+  char *temp = loc_buf;
+  uint32_t len;
+  va_list copy;
+  va_copy(copy, arg);
+  len = vsnprintf(NULL, 0, format, copy);
+  va_end(copy);
+  if (len >= sizeof(loc_buf)) {
+    temp = (char *)malloc(len + 1);
+    if (temp == NULL) {
+      return 0;
     }
-    vsnprintf(temp, len+1, format, arg);
+  }
+  /*
+// This causes dead locks with logging in specific cases and also with C++ constructors that may send logs
 #if !CONFIG_DISABLE_HAL_LOCKS
-    if(_uart_bus_array[s_uart_debug_nr].lock){
+    if(s_uart_debug_nr != -1 && _uart_bus_array[s_uart_debug_nr].lock){
         xSemaphoreTake(_uart_bus_array[s_uart_debug_nr].lock, portMAX_DELAY);
-        ets_printf("%s", temp);
+    }
+#endif
+*/
+  vsnprintf(temp, len + 1, format, arg);
+  ets_printf("%s", temp);
+  /*
+// This causes dead locks with logging and also with constructors that may send logs
+#if !CONFIG_DISABLE_HAL_LOCKS
+    if(s_uart_debug_nr != -1 && _uart_bus_array[s_uart_debug_nr].lock){
         xSemaphoreGive(_uart_bus_array[s_uart_debug_nr].lock);
-    } else {
-        ets_printf("%s", temp);
     }
-#else
-    ets_printf("%s", temp);
 #endif
-    va_end(arg);
-    if(len >= sizeof(loc_buf)){
-        free(temp);
+*/
+  if (len >= sizeof(loc_buf)) {
+    free(temp);
+  }
+  // flushes TX - make sure that the log message is completely sent.
+  if (s_uart_debug_nr != -1) {
+    while (!uart_ll_is_tx_idle(UART_LL_GET_HW(s_uart_debug_nr)));
+  }
+  return len;
+}
+
+int log_printf(const char *format, ...) {
+  int len;
+  va_list arg;
+  va_start(arg, format);
+  len = log_printfv(format, arg);
+  va_end(arg);
+  return len;
+}
+
+static void log_print_buf_line(const uint8_t *b, size_t len, size_t total_len) {
+  for (size_t i = 0; i < len; i++) {
+    log_printf("%s0x%02x,", i ? " " : "", b[i]);
+  }
+  if (total_len > 16) {
+    for (size_t i = len; i < 16; i++) {
+      log_printf("      ");
     }
-    return len;
+    log_printf("    // ");
+  } else {
+    log_printf(" // ");
+  }
+  for (size_t i = 0; i < len; i++) {
+    log_printf("%c", ((b[i] >= 0x20) && (b[i] < 0x80)) ? b[i] : '.');
+  }
+  log_printf("\n");
+}
+
+void log_print_buf(const uint8_t *b, size_t len) {
+  if (!len || !b) {
+    return;
+  }
+  for (size_t i = 0; i < len; i += 16) {
+    if (len > 16) {
+      log_printf("/* 0x%04X */ ", i);
+    }
+    log_print_buf_line(b + i, ((len - i) < 16) ? (len - i) : 16, len);
+  }
 }
 
 /*
- * if enough pulses are detected return the minimum high pulse duration + minimum low pulse duration divided by two. 
- * This equals one bit period. If flag is true the function return inmediately, otherwise it waits for enough pulses.
+ * if enough pulses are detected return the minimum high pulse duration + minimum low pulse duration divided by two.
+ * This equals one bit period. If flag is true the function return immediately, otherwise it waits for enough pulses.
  */
-unsigned long uartBaudrateDetect(uart_t *uart, bool flg)
-{
-    while(uart->dev->rxd_cnt.edge_cnt < 30) { // UART_PULSE_NUM(uart_num)
-        if(flg) return 0;
-        ets_delay_us(1000);
+unsigned long uartBaudrateDetect(uart_t *uart, bool flg) {
+// Baud rate detection only works for ESP32 and ESP32S2
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+  if (uart == NULL) {
+    return 0;
+  }
+
+  uart_dev_t *hw = UART_LL_GET_HW(uart->num);
+
+  while (hw->rxd_cnt.edge_cnt < 30) {  // UART_PULSE_NUM(uart_num)
+    if (flg) {
+      return 0;
     }
+    ets_delay_us(1000);
+  }
 
-    UART_MUTEX_LOCK();
-    unsigned long ret = ((uart->dev->lowpulse.min_cnt + uart->dev->highpulse.min_cnt) >> 1) + 12;
-    UART_MUTEX_UNLOCK();
+  UART_MUTEX_LOCK();
+  //log_i("lowpulse_min_cnt = %d hightpulse_min_cnt = %d", hw->lowpulse.min_cnt, hw->highpulse.min_cnt);
+  unsigned long ret = ((hw->lowpulse.min_cnt + hw->highpulse.min_cnt) >> 1);
+  UART_MUTEX_UNLOCK();
 
-    return ret;
+  return ret;
+#else
+  return 0;
+#endif
 }
 
 /*
- * To start detection of baud rate with the uart the auto_baud.en bit needs to be cleared and set. The bit period is 
- * detected calling uartBadrateDetect(). The raw baudrate is computed using the UART_CLK_FREQ. The raw baudrate is 
+ * To start detection of baud rate with the uart the auto_baud.en bit needs to be cleared and set. The bit period is
+ * detected calling uartBadrateDetect(). The raw baudrate is computed using the UART_CLK_FREQ. The raw baudrate is
  * rounded to the closed real baudrate.
+ *
+ * ESP32-C3 reports wrong baud rate detection as shown below:
+ *
+ * This will help in a future recall for the C3.
+ * Baud Sent:          Baud Read:
+ *  300        -->       19536
+ * 2400        -->       19536
+ * 4800        -->       19536
+ * 9600        -->       28818
+ * 19200       -->       57678
+ * 38400       -->       115440
+ * 57600       -->       173535
+ * 115200      -->       347826
+ * 230400      -->       701754
+ *
+ *
 */
 void uartStartDetectBaudrate(uart_t *uart) {
-  if(!uart) return;
+  if (uart == NULL) {
+    return;
+  }
+
+// Baud rate detection only works for ESP32 and ESP32S2
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+  uart_dev_t *hw = UART_LL_GET_HW(uart->num);
+  hw->auto_baud.glitch_filt = 0x08;
+  hw->auto_baud.en = 0;
+  hw->auto_baud.en = 1;
+#else
+
+  // ESP32-C3 requires further testing
+  // Baud rate detection returns wrong values
+
+  log_e("baud rate detection for this SoC is not supported.");
+  return;
 
-  uart->dev->auto_baud.glitch_filt = 0x08;
-  uart->dev->auto_baud.en = 0;
-  uart->dev->auto_baud.en = 1;
+  // Code bellow for C3 kept for future recall
+  //hw->rx_filt.glitch_filt = 0x08;
+  //hw->rx_filt.glitch_filt_en = 1;
+  //hw->conf0.autobaud_en = 0;
+  //hw->conf0.autobaud_en = 1;
+#endif
 }
 
-unsigned long
-uartDetectBaudrate(uart_t *uart)
-{
-    static bool uartStateDetectingBaudrate = false;
+unsigned long uartDetectBaudrate(uart_t *uart) {
+  if (uart == NULL) {
+    return 0;
+  }
 
-    if(!uartStateDetectingBaudrate) {
-        uart->dev->auto_baud.glitch_filt = 0x08;
-        uart->dev->auto_baud.en = 0;
-        uart->dev->auto_baud.en = 1;
-        uartStateDetectingBaudrate = true;
-    }
+// Baud rate detection only works for ESP32 and ESP32S2
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
 
-    unsigned long divisor = uartBaudrateDetect(uart, true);
-    if (!divisor) {
-        return 0;
-    }
+  static bool uartStateDetectingBaudrate = false;
 
-    uart->dev->auto_baud.en = 0;
-    uartStateDetectingBaudrate = false; // Initialize for the next round
+  if (!uartStateDetectingBaudrate) {
+    uartStartDetectBaudrate(uart);
+    uartStateDetectingBaudrate = true;
+  }
 
-    unsigned long baudrate = getApbFrequency() / divisor;
+  unsigned long divisor = uartBaudrateDetect(uart, true);
+  if (!divisor) {
+    return 0;
+  }
 
-    static const unsigned long default_rates[] = {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 74880, 115200, 230400, 256000, 460800, 921600, 1843200, 3686400};
+  uart_dev_t *hw = UART_LL_GET_HW(uart->num);
+  hw->auto_baud.en = 0;
 
-    size_t i;
-    for (i = 1; i < sizeof(default_rates) / sizeof(default_rates[0]) - 1; i++)	// find the nearest real baudrate
-    {
-        if (baudrate <= default_rates[i])
-        {
-            if (baudrate - default_rates[i - 1] < default_rates[i] - baudrate) {
-                i--;
-            }
-            break;
-        }
+  uartStateDetectingBaudrate = false;  // Initialize for the next round
+
+  unsigned long baudrate = getApbFrequency() / divisor;
+
+  //log_i("APB_FREQ = %d\nraw baudrate detected = %d", getApbFrequency(), baudrate);
+
+  static const unsigned long default_rates[] = {300,   600,    1200,   2400,   4800,   9600,   19200,   38400,  57600,
+                                                74880, 115200, 230400, 256000, 460800, 921600, 1843200, 3686400};
+
+  size_t i;
+  for (i = 1; i < sizeof(default_rates) / sizeof(default_rates[0]) - 1; i++)  // find the nearest real baudrate
+  {
+    if (baudrate <= default_rates[i]) {
+      if (baudrate - default_rates[i - 1] < default_rates[i] - baudrate) {
+        i--;
+      }
+      break;
     }
+  }
 
-    return default_rates[i];
+  return default_rates[i];
+#else
+  log_e("baud rate detection this SoC is not supported.");
+  return 0;
+#endif
 }
 
 /*
- * Returns the status of the RX state machine, if the value is non-zero the state machine is active.
- */
-bool uartRxActive(uart_t* uart) {
-    return uart->dev->status.st_urx_out != 0;
+    These functions are for testing purpose only and can be used in Arduino Sketches
+    Those are used in the UART examples
+*/
+
+/*
+    This is intended to make an internal loopback connection using IOMUX
+    The function uart_internal_loopback() shall be used right after Arduino Serial.begin(...)
+    This code "replaces" the physical wiring for connecting TX <--> RX in a loopback
+*/
+
+// gets the right TX or RX SIGNAL, based on the UART number from gpio_sig_map.h
+#ifdef CONFIG_IDF_TARGET_ESP32P4
+#define UART_TX_SIGNAL(uartNumber) \
+  (uartNumber == UART_NUM_0        \
+     ? UART0_TXD_PAD_OUT_IDX       \
+     : (uartNumber == UART_NUM_1   \
+          ? UART1_TXD_PAD_OUT_IDX  \
+          : (uartNumber == UART_NUM_2 ? UART2_TXD_PAD_OUT_IDX : (uartNumber == UART_NUM_3 ? UART3_TXD_PAD_OUT_IDX : UART4_TXD_PAD_OUT_IDX))))
+#define UART_RX_SIGNAL(uartNumber) \
+  (uartNumber == UART_NUM_0        \
+     ? UART0_RXD_PAD_IN_IDX        \
+     : (uartNumber == UART_NUM_1   \
+          ? UART1_RXD_PAD_IN_IDX   \
+          : (uartNumber == UART_NUM_2 ? UART2_RXD_PAD_IN_IDX : (uartNumber == UART_NUM_3 ? UART3_RXD_PAD_IN_IDX : UART4_RXD_PAD_IN_IDX))))
+#else
+#if SOC_UART_HP_NUM > 2
+#define UART_TX_SIGNAL(uartNumber) (uartNumber == UART_NUM_0 ? U0TXD_OUT_IDX : (uartNumber == UART_NUM_1 ? U1TXD_OUT_IDX : U2TXD_OUT_IDX))
+#define UART_RX_SIGNAL(uartNumber) (uartNumber == UART_NUM_0 ? U0RXD_IN_IDX : (uartNumber == UART_NUM_1 ? U1RXD_IN_IDX : U2RXD_IN_IDX))
+#else
+#define UART_TX_SIGNAL(uartNumber) (uartNumber == UART_NUM_0 ? U0TXD_OUT_IDX : U1TXD_OUT_IDX)
+#define UART_RX_SIGNAL(uartNumber) (uartNumber == UART_NUM_0 ? U0RXD_IN_IDX : U1RXD_IN_IDX)
+#endif
+#endif  // ifdef CONFIG_IDF_TARGET_ESP32P4
+
+/*
+   This function internally binds defined UARTs TX signal with defined RX pin of any UART (same or different).
+   This creates a loop that lets us receive anything we send on the UART without external wires.
+*/
+void uart_internal_loopback(uint8_t uartNum, int8_t rxPin) {
+  // LP UART is not supported for loopback
+  if (uartNum >= SOC_UART_HP_NUM || !GPIO_IS_VALID_GPIO(rxPin)) {
+    log_e("UART%d is not supported for loopback or RX pin %d is invalid.", uartNum, rxPin);
+    return;
+  }
+  esp_rom_gpio_connect_out_signal(rxPin, UART_TX_SIGNAL(uartNum), false, false);
+}
+
+/*
+    This is intended to generate BREAK in an UART line
+*/
+
+// Forces a BREAK in the line based on SERIAL_8N1 configuration at any baud rate
+void uart_send_break(uint8_t uartNum) {
+  uint32_t currentBaudrate = 0;
+  uart_get_baudrate(uartNum, &currentBaudrate);
+  // calculates 10 bits of breaks in microseconds for baudrates up to 500mbps
+  // This is very sensitive timing... it works fine for SERIAL_8N1
+  uint32_t breakTime = (uint32_t)(10.0 * (1000000.0 / currentBaudrate));
+  uart_set_line_inverse(uartNum, UART_SIGNAL_TXD_INV);
+  esp_rom_delay_us(breakTime);
+  uart_set_line_inverse(uartNum, UART_SIGNAL_INV_DISABLE);
+}
+
+// Sends a buffer and at the end of the stream, it generates BREAK in the line
+int uart_send_msg_with_break(uint8_t uartNum, uint8_t *msg, size_t msgSize) {
+  // 12 bits long BREAK for 8N1
+  return uart_write_bytes_with_break(uartNum, (const void *)msg, msgSize, 12);
 }
+
+// returns the maximum valid uart RX Timeout based on the UART Source Clock and Baudrate
+uint16_t uart_get_max_rx_timeout(uint8_t uartNum) {
+  if (uartNum >= SOC_UART_NUM) {
+    log_e("UART%d is invalid. This device has %d UARTs, from 0 to %d.", uartNum, SOC_UART_NUM, SOC_UART_NUM - 1);
+    return (uint16_t)-1;
+  }
+  uint16_t tout_max_thresh = uart_ll_max_tout_thrd(UART_LL_GET_HW(uartNum));
+  uint8_t symbol_len = 1;  // number of bits per symbol including start
+  uart_parity_t parity_mode;
+  uart_stop_bits_t stop_bit;
+  uart_word_length_t data_bit;
+  uart_ll_get_data_bit_num(UART_LL_GET_HW(uartNum), &data_bit);
+  uart_ll_get_stop_bits(UART_LL_GET_HW(uartNum), &stop_bit);
+  uart_ll_get_parity(UART_LL_GET_HW(uartNum), &parity_mode);
+  symbol_len += (data_bit < UART_DATA_BITS_MAX) ? (uint8_t)data_bit + 5 : 8;
+  symbol_len += (stop_bit > UART_STOP_BITS_1) ? 2 : 1;
+  symbol_len += (parity_mode > UART_PARITY_DISABLE) ? 1 : 0;
+  return (uint16_t)(tout_max_thresh / symbol_len);
+}
+
+#endif /* SOC_UART_SUPPORTED */
diff --git a/cores/esp32/esp32-hal-uart.h b/cores/esp32/esp32-hal-uart.h
index e35f05d4cff..41b005aa151 100644
--- a/cores/esp32/esp32-hal-uart.h
+++ b/cores/esp32/esp32-hal-uart.h
@@ -1,4 +1,4 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2025 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -15,6 +15,10 @@
 #ifndef MAIN_ESP32_HAL_UART_H_
 #define MAIN_ESP32_HAL_UART_H_
 
+#include "soc/soc_caps.h"
+#if SOC_UART_SUPPORTED
+#include "soc/uart_pins.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -22,66 +26,116 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include <stdlib.h>
-
-#define SERIAL_5N1 0x8000010
-#define SERIAL_6N1 0x8000014
-#define SERIAL_7N1 0x8000018
-#define SERIAL_8N1 0x800001c
-#define SERIAL_5N2 0x8000030
-#define SERIAL_6N2 0x8000034
-#define SERIAL_7N2 0x8000038
-#define SERIAL_8N2 0x800003c
-#define SERIAL_5E1 0x8000012
-#define SERIAL_6E1 0x8000016
-#define SERIAL_7E1 0x800001a
-#define SERIAL_8E1 0x800001e
-#define SERIAL_5E2 0x8000032
-#define SERIAL_6E2 0x8000036
-#define SERIAL_7E2 0x800003a
-#define SERIAL_8E2 0x800003e
-#define SERIAL_5O1 0x8000013
-#define SERIAL_6O1 0x8000017
-#define SERIAL_7O1 0x800001b
-#define SERIAL_8O1 0x800001f
-#define SERIAL_5O2 0x8000033
-#define SERIAL_6O2 0x8000037
-#define SERIAL_7O2 0x800003b
-#define SERIAL_8O2 0x800003f
+#include "freertos/FreeRTOS.h"
+#include "freertos/queue.h"
+#include "hal/uart_types.h"
 
 struct uart_struct_t;
 typedef struct uart_struct_t uart_t;
 
-uart_t* uartBegin(uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint16_t queueLen, bool inverted);
-void uartEnd(uart_t* uart, uint8_t rxPin, uint8_t txPin);
+bool _testUartBegin(
+  uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint32_t rx_buffer_size, uint32_t tx_buffer_size, bool inverted,
+  uint8_t rxfifo_full_thrhd
+);
+uart_t *uartBegin(
+  uint8_t uart_nr, uint32_t baudrate, uint32_t config, int8_t rxPin, int8_t txPin, uint32_t rx_buffer_size, uint32_t tx_buffer_size, bool inverted,
+  uint8_t rxfifo_full_thrhd
+);
+void uartEnd(uint8_t uart_num);
 
-uint32_t uartAvailable(uart_t* uart);
-uint32_t uartAvailableForWrite(uart_t* uart);
-uint8_t uartRead(uart_t* uart);
-uint8_t uartPeek(uart_t* uart);
+// This is used to retrieve the Event Queue pointer from a UART IDF Driver in order to allow user to deal with its events
+void uartGetEventQueue(uart_t *uart, QueueHandle_t *q);
 
-void uartWrite(uart_t* uart, uint8_t c);
-void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len);
+uint32_t uartAvailable(uart_t *uart);
+uint32_t uartAvailableForWrite(uart_t *uart);
+size_t uartReadBytes(uart_t *uart, uint8_t *buffer, size_t size, uint32_t timeout_ms);
+uint8_t uartRead(uart_t *uart);
+uint8_t uartPeek(uart_t *uart);
 
-void uartFlush(uart_t* uart);
-void uartFlushTxOnly(uart_t* uart, bool txOnly );
+void uartWrite(uart_t *uart, uint8_t c);
+void uartWriteBuf(uart_t *uart, const uint8_t *data, size_t len);
 
-void uartSetBaudRate(uart_t* uart, uint32_t baud_rate);
-uint32_t uartGetBaudRate(uart_t* uart);
+void uartFlush(uart_t *uart);
+void uartFlushTxOnly(uart_t *uart, bool txOnly);
 
-size_t uartResizeRxBuffer(uart_t* uart, size_t new_size);
+bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate);
+uint32_t uartGetBaudRate(uart_t *uart);
 
-void uartSetRxInvert(uart_t* uart, bool invert);
+void uartSetRxInvert(uart_t *uart, bool invert);
+bool uartSetRxTimeout(uart_t *uart, uint8_t numSymbTimeout);
+bool uartSetRxFIFOFull(uart_t *uart, uint8_t numBytesFIFOFull);
+void uartSetFastReading(uart_t *uart);
 
-void uartSetDebug(uart_t* uart);
+void uartSetDebug(uart_t *uart);
 int uartGetDebug();
 
+bool uartIsDriverInstalled(uart_t *uart);
+
+// Negative Pin Number will keep it unmodified, thus this function can set individual pins
+// When pins are changed, it will detach the previous ones
+// Can be called before or after begin()
+bool uartSetPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin);
+
+// helper functions
+int8_t uart_get_RxPin(uint8_t uart_num);
+int8_t uart_get_TxPin(uint8_t uart_num);
+void uart_init_PeriMan(void);
+
+// Enables or disables HW Flow Control function -- needs also to set CTS and/or RTS pins
+//    UART_HW_FLOWCTRL_DISABLE = 0x0   disable hardware flow control
+//    UART_HW_FLOWCTRL_RTS     = 0x1   enable RX hardware flow control (rts)
+//    UART_HW_FLOWCTRL_CTS     = 0x2   enable TX hardware flow control (cts)
+//    UART_HW_FLOWCTRL_CTS_RTS = 0x3   enable hardware flow control
+bool uartSetHwFlowCtrlMode(uart_t *uart, uart_hw_flowcontrol_t mode, uint8_t threshold);
+
+// Used to set RS485 function -- needs to disable HW Flow Control and set RTS pin to use
+// RTS pin becomes RS485 half duplex RE/DE
+//    UART_MODE_UART                   = 0x00    mode: regular UART mode
+//    UART_MODE_RS485_HALF_DUPLEX      = 0x01    mode: half duplex RS485 UART mode control by RTS pin
+//    UART_MODE_IRDA                   = 0x02    mode: IRDA  UART mode
+//    UART_MODE_RS485_COLLISION_DETECT = 0x03    mode: RS485 collision detection UART mode (used for test purposes)
+//    UART_MODE_RS485_APP_CTRL         = 0x04    mode: application control RS485 UART mode (used for test purposes)
+bool uartSetMode(uart_t *uart, uart_mode_t mode);
+
+// Used to set the UART clock source mode. It must be set before calling uartBegin(), otherwise it won't have any effect.
+// Not all clock source are available to every SoC. The compatible option are listed here:
+// UART_SCLK_DEFAULT      :: any SoC - it will set whatever IDF defines as the default UART Clock Source
+// UART_SCLK_APB          :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
+// UART_SCLK_PLL_F80M     :: ESP32-C5, ESP32-C6, ESP32-C61 and ESP32-P4
+// UART_SCLK_PLL_F40M     :: ESP32-C2
+// UART_SCLK_PLL_F48M     :: ESP32-H2
+// UART_SCLK_XTAL         :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+// UART_SCLK_RTC          :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
+// UART_SCLK_REF_TICK     :: ESP32 and ESP32-S2
+// Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only LP_UART_SCLK_LP_FAST (RTC_FAST) or LP_UART_SCLK_XTAL_D2 (XTAL/2) as Clock Source
+bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc);
+
 void uartStartDetectBaudrate(uart_t *uart);
 unsigned long uartDetectBaudrate(uart_t *uart);
 
-bool uartRxActive(uart_t* uart);
+/*
+    These functions are for testing puspose only and can be used in Arduino Sketches
+    Those are used in the UART examples
+*/
+
+// Make sure UART's RX signal is connected to TX pin
+// This creates a loop that lets us receive anything we send on the UART
+void uart_internal_loopback(uint8_t uartNum, int8_t rxPin);
+
+// Routines that generate BREAK in the UART for testing purpose
+
+// Forces a BREAK in the line based on SERIAL_8N1 configuration at any baud rate
+void uart_send_break(uint8_t uartNum);
+// Sends a buffer and at the end of the stream, it generates BREAK in the line
+int uart_send_msg_with_break(uint8_t uartNum, uint8_t *msg, size_t msgSize);
+
+// UART RX Timeout (in UART Symbols) depends on the UART Clock Source and the SoC that is used
+// This is a helper function that calculates what is the maximum RX Timeout that a running UART IDF driver allows.
+uint16_t uart_get_max_rx_timeout(uint8_t uartNum);
 
 #ifdef __cplusplus
 }
 #endif
 
+#endif /* SOC_UART_SUPPORTED */
 #endif /* MAIN_ESP32_HAL_UART_H_ */
diff --git a/cores/esp32/esp32-hal.h b/cores/esp32/esp32-hal.h
index 4b5fb2c2ebb..5ed99aeb205 100644
--- a/cores/esp32/esp32-hal.h
+++ b/cores/esp32/esp32-hal.h
@@ -20,10 +20,6 @@
 #ifndef HAL_ESP32_HAL_H_
 #define HAL_ESP32_HAL_H_
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 #include <stdint.h>
 #include <stdbool.h>
 #include <stdio.h>
@@ -34,24 +30,64 @@ extern "C" {
 #include <math.h>
 #include "sdkconfig.h"
 #include "esp_system.h"
+#include "esp_sleep.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+#include "freertos/event_groups.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #ifndef F_CPU
-#define F_CPU (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000U)
+#define F_CPU (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 1000000U)
+#endif
+
+#if CONFIG_ARDUINO_ISR_IRAM
+#define ARDUINO_ISR_ATTR IRAM_ATTR
+#define ARDUINO_ISR_FLAG ESP_INTR_FLAG_IRAM
+#else
+#define ARDUINO_ISR_ATTR
+#define ARDUINO_ISR_FLAG (0)
 #endif
 
+#ifndef ARDUINO_RUNNING_CORE
+#define ARDUINO_RUNNING_CORE CONFIG_ARDUINO_RUNNING_CORE
+#endif
+
+#ifndef ARDUINO_EVENT_RUNNING_CORE
+#define ARDUINO_EVENT_RUNNING_CORE CONFIG_ARDUINO_EVENT_RUNNING_CORE
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+static const uint8_t BOOT_PIN = 0;
+#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C61
+static const uint8_t BOOT_PIN = 9;
+#elif CONFIG_IDF_TARGET_ESP32P4
+static const uint8_t BOOT_PIN = 35;
+#elif CONFIG_IDF_TARGET_ESP32C5
+static const uint8_t BOOT_PIN = 28;
+#else
+#error BOOT_PIN not defined for this chip!
+#endif
+#define BOOT_PIN BOOT_PIN
+
 //forward declaration from freertos/portmacro.h
 void vPortYield(void);
 void yield(void);
 #define optimistic_yield(u)
 
 #define ESP_REG(addr) *((volatile uint32_t *)(addr))
-#define NOP() asm volatile ("nop")
+#define NOP()         asm volatile("nop")
 
 #include "esp32-hal-log.h"
 #include "esp32-hal-matrix.h"
 #include "esp32-hal-uart.h"
 #include "esp32-hal-gpio.h"
 #include "esp32-hal-touch.h"
+#include "esp32-hal-touch-ng.h"
 #include "esp32-hal-dac.h"
 #include "esp32-hal-adc.h"
 #include "esp32-hal-spi.h"
@@ -62,17 +98,19 @@ void yield(void);
 #include "esp32-hal-timer.h"
 #include "esp32-hal-bt.h"
 #include "esp32-hal-psram.h"
+#include "esp32-hal-rgb-led.h"
 #include "esp32-hal-cpu.h"
 
-#ifndef BOARD_HAS_PSRAM
-#ifdef CONFIG_SPIRAM_SUPPORT
-#undef CONFIG_SPIRAM_SUPPORT
-#endif
-#endif
+void analogWrite(uint8_t pin, int value);
+void analogWriteFrequency(uint8_t pin, uint32_t freq);
+void analogWriteResolution(uint8_t pin, uint8_t bits);
 
 //returns chip temperature in Celsius
 float temperatureRead();
 
+//allows user to bypass SPI RAM test routine
+bool testSPIRAM(void);
+
 #if CONFIG_AUTOSTART_ARDUINO
 //enable/disable WDT for Arduino's setup and loop functions
 void enableLoopWDT();
@@ -83,22 +121,19 @@ void feedLoopWDT();
 
 //enable/disable WDT for the IDLE task on Core 0 (SYSTEM)
 void enableCore0WDT();
-void disableCore0WDT();
+bool disableCore0WDT();
 #ifndef CONFIG_FREERTOS_UNICORE
 //enable/disable WDT for the IDLE task on Core 1 (Arduino)
 void enableCore1WDT();
-void disableCore1WDT();
+bool disableCore1WDT();
 #endif
 
 //if xCoreID < 0 or CPU is unicore, it will use xTaskCreate, else xTaskCreatePinnedToCore
 //allows to easily handle all possible situations without repetitive code
-BaseType_t xTaskCreateUniversal( TaskFunction_t pxTaskCode,
-                        const char * const pcName,
-                        const uint32_t usStackDepth,
-                        void * const pvParameters,
-                        UBaseType_t uxPriority,
-                        TaskHandle_t * const pxCreatedTask,
-                        const BaseType_t xCoreID );
+BaseType_t xTaskCreateUniversal(
+  TaskFunction_t pxTaskCode, const char *const pcName, const uint32_t usStackDepth, void *const pvParameters, UBaseType_t uxPriority,
+  TaskHandle_t *const pxCreatedTask, const BaseType_t xCoreID
+);
 
 unsigned long micros();
 unsigned long millis();
@@ -113,6 +148,22 @@ void arduino_phy_init();
 void initArduino();
 #endif
 
+typedef struct {
+  int core;                    // core which triggered panic
+  const char *reason;          // exception string
+  const void *pc;              // instruction address that triggered the exception
+  bool backtrace_corrupt;      // if backtrace is corrupt
+  bool backtrace_continues;    // if backtrace continues, but did not fit
+  unsigned int backtrace_len;  // number of backtrace addresses
+  unsigned int backtrace[60];  // backtrace addresses array
+} arduino_panic_info_t;
+
+typedef void (*arduino_panic_handler_t)(arduino_panic_info_t *info, void *arg);
+
+void set_arduino_panic_handler(arduino_panic_handler_t handler, void *arg);
+arduino_panic_handler_t get_arduino_panic_handler(void);
+void *get_arduino_panic_handler_arg(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/cores/esp32/esp8266-compat.h b/cores/esp32/esp8266-compat.h
index 078fdb72f09..8123cd0787b 100644
--- a/cores/esp32/esp8266-compat.h
+++ b/cores/esp32/esp8266-compat.h
@@ -18,7 +18,6 @@
 #define _ESP8266_COMPAT_H_
 
 #define ICACHE_FLASH_ATTR
-#define ICACHE_RAM_ATTR IRAM_ATTR
+#define ICACHE_RAM_ATTR ARDUINO_ISR_ATTR
 
-
-#endif /* _ESP8266_COMPAT_H_ */
\ No newline at end of file
+#endif /* _ESP8266_COMPAT_H_ */
diff --git a/cores/esp32/esp_arduino_version.h b/cores/esp32/esp_arduino_version.h
new file mode 100644
index 00000000000..b1355e908ae
--- /dev/null
+++ b/cores/esp32/esp_arduino_version.h
@@ -0,0 +1,51 @@
+// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Major version number (X.x.x) */
+#define ESP_ARDUINO_VERSION_MAJOR 3
+/** Minor version number (x.X.x) */
+#define ESP_ARDUINO_VERSION_MINOR 2
+/** Patch version number (x.x.X) */
+#define ESP_ARDUINO_VERSION_PATCH 0
+
+/**
+ * Macro to convert ARDUINO version number into an integer
+ *
+ * To be used in comparisons, such as ESP_ARDUINO_VERSION >= ESP_ARDUINO_VERSION_VAL(2, 0, 0)
+ */
+#define ESP_ARDUINO_VERSION_VAL(major, minor, patch) ((major << 16) | (minor << 8) | (patch))
+
+/**
+ * Current ARDUINO version, as an integer
+ *
+ * To be used in comparisons, such as ESP_ARDUINO_VERSION >= ESP_ARDUINO_VERSION_VAL(2, 0, 0)
+ */
+#define ESP_ARDUINO_VERSION ESP_ARDUINO_VERSION_VAL(ESP_ARDUINO_VERSION_MAJOR, ESP_ARDUINO_VERSION_MINOR, ESP_ARDUINO_VERSION_PATCH)
+
+/**
+ * Current ARDUINO version, as string
+ */
+#define df2xstr(s)              #s
+#define df2str(s)               df2xstr(s)
+#define ESP_ARDUINO_VERSION_STR df2str(ESP_ARDUINO_VERSION_MAJOR) "." df2str(ESP_ARDUINO_VERSION_MINOR) "." df2str(ESP_ARDUINO_VERSION_PATCH)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/cores/esp32/extra_attr.h b/cores/esp32/extra_attr.h
new file mode 100644
index 00000000000..d5342a5bcc8
--- /dev/null
+++ b/cores/esp32/extra_attr.h
@@ -0,0 +1,3 @@
+#define ATTR_PACKED     __attribute__((__packed__))
+#define ATTR_ALIGNED(x) __attribute__((__aligned__(x)))
+#define ATTR_SECTION(x) __attribute__((__section__(x)))
diff --git a/cores/esp32/firmware_msc_fat.c b/cores/esp32/firmware_msc_fat.c
new file mode 100644
index 00000000000..e66cc262c2d
--- /dev/null
+++ b/cores/esp32/firmware_msc_fat.c
@@ -0,0 +1,210 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "firmware_msc_fat.h"
+//copy up to max_len chars from src to dst and do not terminate
+static size_t cplstr(void *dst, const void *src, size_t max_len) {
+  if (!src || !dst || !max_len) {
+    return 0;
+  }
+  size_t l = strlen((const char *)src);
+  if (l > max_len) {
+    l = max_len;
+  }
+  memcpy(dst, src, l);
+  return l;
+}
+
+//copy up to max_len chars from src to dst, adding spaces up to max_len. do not terminate
+static void cplstrsp(void *dst, const void *src, size_t max_len) {
+  size_t l = cplstr(dst, src, max_len);
+  for (; l < max_len; l++) {
+    ((uint8_t *)dst)[l] = 0x20;
+  }
+}
+
+// FAT12
+static const char *FAT12_FILE_SYSTEM_TYPE = "FAT12";
+
+static uint16_t fat12_sectors_per_alloc_table(uint32_t sector_num) {
+  uint32_t required_bytes = (((sector_num * 3) + 1) / 2);
+  return (required_bytes / DISK_SECTOR_SIZE) + ((required_bytes & (DISK_SECTOR_SIZE - 1)) ? 1 : 0);
+}
+
+static uint8_t *fat12_add_table(uint8_t *dst, fat_boot_sector_t *boot) {
+  memset(dst + DISK_SECTOR_SIZE, 0, boot->sectors_per_alloc_table * DISK_SECTOR_SIZE);
+  uint8_t *d = dst + DISK_SECTOR_SIZE;
+  d[0] = 0xF8;
+  d[1] = 0xFF;
+  d[2] = 0xFF;
+  return d;
+}
+
+static void fat12_set_table_index(uint8_t *table, uint16_t index, uint16_t value) {
+  uint16_t offset = (index >> 1) * 3;
+  uint8_t *data = table + offset;
+  if (index & 1) {
+    data[2] = (value >> 4) & 0xFF;
+    data[1] = (data[1] & 0xF) | ((value & 0xF) << 4);
+  } else {
+    data[0] = value & 0xFF;
+    data[1] = (data[1] & 0xF0) | ((value >> 8) & 0xF);
+  }
+}
+
+//FAT16
+static const char *FAT16_FILE_SYSTEM_TYPE = "FAT16";
+
+static uint16_t fat16_sectors_per_alloc_table(uint32_t sector_num) {
+  uint32_t required_bytes = sector_num * 2;
+  return (required_bytes / DISK_SECTOR_SIZE) + ((required_bytes & (DISK_SECTOR_SIZE - 1)) ? 1 : 0);
+}
+
+static uint8_t *fat16_add_table(uint8_t *dst, fat_boot_sector_t *boot) {
+  memset(dst + DISK_SECTOR_SIZE, 0, boot->sectors_per_alloc_table * DISK_SECTOR_SIZE);
+  uint16_t *d = (uint16_t *)(dst + DISK_SECTOR_SIZE);
+  d[0] = 0xFFF8;
+  d[1] = 0xFFFF;
+  return (uint8_t *)d;
+}
+
+static void fat16_set_table_index(uint8_t *table, uint16_t index, uint16_t value) {
+  uint16_t offset = index * 2;
+  *(uint16_t *)(table + offset) = value;
+}
+
+//Interface
+const char *fat_file_system_type(bool fat16) {
+  return ((fat16) ? FAT16_FILE_SYSTEM_TYPE : FAT12_FILE_SYSTEM_TYPE);
+}
+
+uint16_t fat_sectors_per_alloc_table(uint32_t sector_num, bool fat16) {
+  if (fat16) {
+    return fat16_sectors_per_alloc_table(sector_num);
+  }
+  return fat12_sectors_per_alloc_table(sector_num);
+}
+
+uint8_t *fat_add_table(uint8_t *dst, fat_boot_sector_t *boot, bool fat16) {
+  if (fat16) {
+    return fat16_add_table(dst, boot);
+  }
+  return fat12_add_table(dst, boot);
+}
+
+void fat_set_table_index(uint8_t *table, uint16_t index, uint16_t value, bool fat16) {
+  if (fat16) {
+    fat16_set_table_index(table, index, value);
+  } else {
+    fat12_set_table_index(table, index, value);
+  }
+}
+
+fat_boot_sector_t *fat_add_boot_sector(
+  uint8_t *dst, uint16_t sector_num, uint16_t table_sectors, const char *file_system_type, const char *volume_label, uint32_t serial_number
+) {
+  fat_boot_sector_t *boot = (fat_boot_sector_t *)dst;
+  boot->jump_instruction[0] = 0xEB;
+  boot->jump_instruction[1] = 0x3C;
+  boot->jump_instruction[2] = 0x90;
+  cplstr(boot->oem_name, "MSDOS5.0", 8);
+  boot->bytes_per_sector = DISK_SECTOR_SIZE;
+  boot->sectors_per_cluster = 1;
+  boot->reserved_sectors_count = 1;
+  boot->file_alloc_tables_num = 1;
+  boot->max_root_dir_entries = 16;
+  boot->fat12_sector_num = sector_num;
+  boot->media_descriptor = 0xF8;
+  boot->sectors_per_alloc_table = table_sectors;
+  boot->sectors_per_track = 1;
+  boot->num_heads = 1;
+  boot->hidden_sectors_count = 0;
+  boot->total_sectors_32 = 0;
+  boot->physical_drive_number = 0x80;
+  boot->reserved0 = 0x00;
+  boot->extended_boot_signature = 0x29;
+  boot->serial_number = serial_number;
+  cplstrsp(boot->volume_label, volume_label, 11);
+  memset(boot->reserved, 0, 448);
+  cplstrsp(boot->file_system_type, file_system_type, 8);
+  boot->signature = 0xAA55;
+  return boot;
+}
+
+fat_dir_entry_t *fat_add_label(uint8_t *dst, const char *volume_label) {
+  fat_boot_sector_t *boot = (fat_boot_sector_t *)dst;
+  fat_dir_entry_t *entry = (fat_dir_entry_t *)(dst + ((boot->sectors_per_alloc_table + 1) * DISK_SECTOR_SIZE));
+  memset(entry, 0, sizeof(fat_dir_entry_t));
+  cplstrsp(entry->volume_label, volume_label, 11);
+  entry->file_attr = FAT_FILE_ATTR_VOLUME_LABEL;
+  return entry;
+}
+
+fat_dir_entry_t *fat_add_root_file(
+  uint8_t *dst, uint8_t index, const char *file_name, const char *file_extension, size_t file_size, uint16_t data_start_sector, bool is_fat16
+) {
+  fat_boot_sector_t *boot = (fat_boot_sector_t *)dst;
+  uint8_t *table = dst + DISK_SECTOR_SIZE;
+  fat_dir_entry_t *entry = (fat_dir_entry_t *)(dst + ((boot->sectors_per_alloc_table + 1) * DISK_SECTOR_SIZE) + (index * sizeof(fat_dir_entry_t)));
+  memset(entry, 0, sizeof(fat_dir_entry_t));
+  cplstrsp(entry->file_name, file_name, 8);
+  cplstrsp(entry->file_extension, file_extension, 3);
+  entry->file_attr = FAT_FILE_ATTR_ARCHIVE;
+  entry->file_size = file_size;
+  entry->data_start_sector = data_start_sector;
+  entry->extended_attr = 0;
+
+  uint16_t file_sectors = file_size / DISK_SECTOR_SIZE;
+  if (file_size % DISK_SECTOR_SIZE) {
+    file_sectors++;
+  }
+
+  uint16_t data_end_sector = data_start_sector + file_sectors;
+  for (uint16_t i = data_start_sector; i < (data_end_sector - 1); i++) {
+    fat_set_table_index(table, i, i + 1, is_fat16);
+  }
+  fat_set_table_index(table, data_end_sector - 1, 0xFFFF, is_fat16);
+
+  //Set Firmware Date based on the build time
+  static const char *month_names_short[12] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"};
+  char mstr[8] = {
+    '\0',
+  };
+  const char *str = __DATE__ " " __TIME__;
+  int ms = 0, seconds = 0, minutes = 0, hours = 0, year = 0, date = 0, month = 0;
+  int r = sscanf(str, "%s %d %d %d:%d:%d", mstr, &date, &year, &hours, &minutes, &seconds);
+  if (r >= 0) {
+    for (int i = 0; i < 12; i++) {
+      if (!strcmp(mstr, month_names_short[i])) {
+        month = i;
+        break;
+      }
+    }
+    entry->creation_time_ms = FAT_MS2V(seconds, ms);
+    entry->creation_time_hms = FAT_HMS2V(hours, minutes, seconds);
+    entry->creation_time_ymd = FAT_YMD2V(year, month, date);
+    entry->last_access_ymd = entry->creation_time_ymd;
+    entry->last_modified_hms = entry->creation_time_hms;
+    entry->last_modified_ymd = entry->creation_time_ymd;
+  }
+  return entry;
+}
+
+uint8_t fat_lfn_checksum(const uint8_t *short_filename) {
+  uint8_t sum = 0;
+  for (uint8_t i = 11; i; i--) {
+    sum = ((sum & 1) << 7) + (sum >> 1) + *short_filename++;
+  }
+  return sum;
+}
diff --git a/cores/esp32/firmware_msc_fat.h b/cores/esp32/firmware_msc_fat.h
new file mode 100644
index 00000000000..a88e051b1c9
--- /dev/null
+++ b/cores/esp32/firmware_msc_fat.h
@@ -0,0 +1,145 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define FAT_U8(v)  ((v) & 0xFF)
+#define FAT_U16(v) FAT_U8(v), FAT_U8((v) >> 8)
+#define FAT_U32(v) FAT_U8(v), FAT_U8((v) >> 8), FAT_U8((v) >> 16), FAT_U8((v) >> 24)
+
+#define FAT12_TBL2B(l, h) FAT_U8(l), FAT_U8(((l >> 8) & 0xF) | ((h << 4) & 0xF0)), FAT_U8(h >> 4)
+
+#define FAT_MS2B(s, ms)    FAT_U8(((((s) & 0x1) * 1000) + (ms)) / 10)
+#define FAT_HMS2B(h, m, s) FAT_U8(((s) >> 1) | (((m) & 0x7) << 5)), FAT_U8((((m) >> 3) & 0x7) | ((h) << 3))
+#define FAT_YMD2B(y, m, d) FAT_U8(((d) & 0x1F) | (((m) & 0x7) << 5)), FAT_U8((((m) >> 3) & 0x1) | ((((y) - 1980) & 0x7F) << 1))
+
+#define FAT_MS2V(s, ms)    FAT_U8(((((s) & 0x1) * 1000) + (ms)) / 10)
+#define FAT_HMS2V(h, m, s) (FAT_U8(((s) >> 1) | (((m) & 0x7) << 5)) | (FAT_U8((((m) >> 3) & 0x7) | ((h) << 3)) << 8))
+#define FAT_YMD2V(y, m, d) (FAT_U8(((d) & 0x1F) | (((m) & 0x7) << 5)) | (FAT_U8((((m) >> 3) & 0x1) | ((((y) - 1980) & 0x7F) << 1)) << 8))
+
+#define FAT_B2HMS(hms) ((hms >> 11) & 0x1F), ((hms >> 5) & 0x3F), ((hms & 0x1F) << 1)
+#define FAT_B2YMD(ymd) (((ymd >> 9) & 0x7F) + 1980), ((ymd >> 5) & 0x0F), (ymd & 0x1F)
+
+#define FAT_FILE_ATTR_READ_ONLY    0x01
+#define FAT_FILE_ATTR_HIDDEN       0x02
+#define FAT_FILE_ATTR_SYSTEM       0x04
+#define FAT_FILE_ATTR_VOLUME_LABEL 0x08
+#define FAT_FILE_ATTR_SUBDIRECTORY 0x10
+#define FAT_FILE_ATTR_ARCHIVE      0x20
+#define FAT_FILE_ATTR_DEVICE       0x40
+
+static const uint16_t DISK_SECTOR_SIZE = 512;
+
+#define FAT_SIZE_TO_SECTORS(bytes) ((bytes) / DISK_SECTOR_SIZE) + (((bytes) % DISK_SECTOR_SIZE) ? 1 : 0)
+
+typedef struct __attribute__((packed)) {
+  uint8_t jump_instruction[3];
+  char oem_name[8];                 //padded with spaces (0x20)
+  uint16_t bytes_per_sector;        //DISK_SECTOR_SIZE usually 512
+  uint8_t sectors_per_cluster;      //Allowed values are 1, 2, 4, 8, 16, 32, 64, and 128
+  uint16_t reserved_sectors_count;  //At least 1 for this sector, usually 32 for FAT32
+  uint8_t file_alloc_tables_num;    //Almost always 2; RAM disks might use 1
+  uint16_t max_root_dir_entries;    //FAT12 and FAT16
+  uint16_t fat12_sector_num;        //DISK_SECTOR_NUM FAT12 and FAT16
+  uint8_t media_descriptor;
+  uint16_t sectors_per_alloc_table;  //FAT12 and FAT16
+  uint16_t sectors_per_track;        //A value of 0 may indicate LBA-only access
+  uint16_t num_heads;
+  uint32_t hidden_sectors_count;
+  uint32_t total_sectors_32;
+  uint8_t physical_drive_number;  //0x00 for (first) removable media, 0x80 for (first) fixed disk
+  uint8_t reserved0;
+  uint8_t extended_boot_signature;  //should be 0x29
+  uint32_t serial_number;           //0x1234 => 1234
+  char volume_label[11];            //padded with spaces (0x20)
+  char file_system_type[8];         //padded with spaces (0x20)
+  uint8_t reserved[448];
+  uint16_t signature;  //should be 0xAA55
+} fat_boot_sector_t;
+
+typedef struct __attribute__((packed)) {
+  union {
+    struct {
+      char file_name[8];       //padded with spaces (0x20)
+      char file_extension[3];  //padded with spaces (0x20)
+    };
+    struct {
+      uint8_t file_magic;  // 0xE5:deleted, 0x05:will_be_deleted, 0x00:end_marker, 0x2E:dot_marker(. or ..)
+      char file_magic_data[10];
+    };
+    char volume_label[11];  //padded with spaces (0x20)
+  };
+  uint8_t file_attr;           //mask of FAT_FILE_ATTR_*
+  uint8_t reserved;            //always 0
+  uint8_t creation_time_ms;    //ms * 10; max 1990 (1s 990ms)
+  uint16_t creation_time_hms;  // [5:6:5] => h:m:(s/2)
+  uint16_t creation_time_ymd;  // [7:4:5] => (y+1980):m:d
+  uint16_t last_access_ymd;
+  uint16_t extended_attr;
+  uint16_t last_modified_hms;
+  uint16_t last_modified_ymd;
+  uint16_t data_start_sector;
+  uint32_t file_size;
+} fat_dir_entry_t;
+
+typedef struct __attribute__((packed)) {
+  union {
+    struct {
+      uint8_t number    : 5;
+      uint8_t reserved0 : 1;
+      uint8_t llfp      : 1;
+      uint8_t reserved1 : 1;
+    } seq;
+    uint8_t seq_num;  //0xE5: Deleted Entry
+  };
+  uint16_t name0[5];
+  uint8_t attr;  //ALWAYS 0x0F
+  uint8_t type;  //ALWAYS 0x00
+  uint8_t dos_checksum;
+  uint16_t name1[6];
+  uint16_t first_cluster;  //ALWAYS 0x0000
+  uint16_t name2[2];
+} fat_lfn_entry_t;
+
+typedef union {
+  fat_dir_entry_t dir;
+  fat_lfn_entry_t lfn;
+} fat_entry_t;
+
+const char *fat_file_system_type(bool fat16);
+uint16_t fat_sectors_per_alloc_table(uint32_t sector_num, bool fat16);
+uint8_t *fat_add_table(uint8_t *dst, fat_boot_sector_t *boot, bool fat16);
+void fat_set_table_index(uint8_t *table, uint16_t index, uint16_t value, bool fat16);
+fat_boot_sector_t *fat_add_boot_sector(
+  uint8_t *dst, uint16_t sector_num, uint16_t table_sectors, const char *file_system_type, const char *volume_label, uint32_t serial_number
+);
+fat_dir_entry_t *fat_add_label(uint8_t *dst, const char *volume_label);
+fat_dir_entry_t *fat_add_root_file(
+  uint8_t *dst, uint8_t index, const char *file_name, const char *file_extension, size_t file_size, uint16_t data_start_sector, bool is_fat16
+);
+uint8_t fat_lfn_checksum(const uint8_t *short_filename);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/cores/esp32/freertos_stats.cpp b/cores/esp32/freertos_stats.cpp
new file mode 100644
index 00000000000..b37a5205e11
--- /dev/null
+++ b/cores/esp32/freertos_stats.cpp
@@ -0,0 +1,112 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "freertos_stats.h"
+#include "sdkconfig.h"
+
+#if CONFIG_FREERTOS_USE_TRACE_FACILITY
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/portable.h"
+#endif /* CONFIG_FREERTOS_USE_TRACE_FACILITY */
+
+void printRunningTasks(Print &printer) {
+#if CONFIG_FREERTOS_USE_TRACE_FACILITY
+#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS
+#define FREERTOS_TASK_NUMBER_MAX_NUM 256  // RunTime stats for how many Tasks to be stored
+  static configRUN_TIME_COUNTER_TYPE ulRunTimeCounters[FREERTOS_TASK_NUMBER_MAX_NUM];
+  static configRUN_TIME_COUNTER_TYPE ulLastRunTime = 0;
+  configRUN_TIME_COUNTER_TYPE ulCurrentRunTime = 0, ulTaskRunTime = 0;
+#endif
+  configRUN_TIME_COUNTER_TYPE ulTotalRunTime = 0;
+  TaskStatus_t *pxTaskStatusArray = NULL;
+  volatile UBaseType_t uxArraySize = 0;
+  uint32_t x = 0;
+  const char *taskStates[] = {"Running", "Ready", "Blocked", "Suspended", "Deleted", "Invalid"};
+
+  // Take a snapshot of the number of tasks in case it changes while this function is executing.
+  uxArraySize = uxTaskGetNumberOfTasks();
+
+  // Allocate a TaskStatus_t structure for each task.
+  pxTaskStatusArray = (TaskStatus_t *)pvPortMalloc(uxArraySize * sizeof(TaskStatus_t));
+
+  if (pxTaskStatusArray != NULL) {
+    // Generate raw status information about each task.
+    uxArraySize = uxTaskGetSystemState(pxTaskStatusArray, uxArraySize, &ulTotalRunTime);
+
+#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS
+    ulCurrentRunTime = ulTotalRunTime - ulLastRunTime;
+    ulLastRunTime = ulTotalRunTime;
+#endif
+    printer.printf(
+      "Tasks: %u"
+#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS
+      ", Runtime: %lus, Period: %luus"
+#endif
+      "\n",
+      uxArraySize
+#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS
+      ,
+      ulTotalRunTime / 1000000, ulCurrentRunTime
+#endif
+    );
+    printer.printf("Num\t            Name"
+#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS
+                   "\tLoad"
+#endif
+                   "\tPrio\t Free"
+#if CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID
+                   "\tCore"
+#endif
+                   "\tState\r\n");
+    for (x = 0; x < uxArraySize; x++) {
+#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS
+      if (pxTaskStatusArray[x].xTaskNumber < FREERTOS_TASK_NUMBER_MAX_NUM) {
+        ulTaskRunTime = (pxTaskStatusArray[x].ulRunTimeCounter - ulRunTimeCounters[pxTaskStatusArray[x].xTaskNumber]);
+        ulRunTimeCounters[pxTaskStatusArray[x].xTaskNumber] = pxTaskStatusArray[x].ulRunTimeCounter;
+        ulTaskRunTime = (ulTaskRunTime * 100) / ulCurrentRunTime;  // in percentage
+      } else {
+        ulTaskRunTime = 0;
+      }
+#endif
+      printer.printf(
+        "%3u\t%16s"
+#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS
+        "\t%3lu%%"
+#endif
+        "\t%4u\t%5lu"
+#if CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID
+        "\t%4c"
+#endif
+        "\t%s\r\n",
+        pxTaskStatusArray[x].xTaskNumber, pxTaskStatusArray[x].pcTaskName,
+#if CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS
+        ulTaskRunTime,
+#endif
+        pxTaskStatusArray[x].uxCurrentPriority, pxTaskStatusArray[x].usStackHighWaterMark,
+#if CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID
+        (pxTaskStatusArray[x].xCoreID == tskNO_AFFINITY) ? '*' : ('0' + pxTaskStatusArray[x].xCoreID),
+#endif
+        taskStates[pxTaskStatusArray[x].eCurrentState]
+      );
+    }
+
+    // The array is no longer needed, free the memory it consumes.
+    vPortFree(pxTaskStatusArray);
+    printer.println();
+  }
+#else
+  printer.println("FreeRTOS trace facility is not enabled.");
+#endif /* CONFIG_FREERTOS_USE_TRACE_FACILITY */
+}
diff --git a/cores/esp32/freertos_stats.h b/cores/esp32/freertos_stats.h
new file mode 100644
index 00000000000..ea9e1a55a21
--- /dev/null
+++ b/cores/esp32/freertos_stats.h
@@ -0,0 +1,28 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+
+#include "Print.h"
+
+/*
+ * Executing this function will cause interrupts and
+ * the scheduler to be blocked for some time.
+ * Please use only for debugging purposes.
+ */
+void printRunningTasks(Print &printer);
+
+#endif
diff --git a/cores/esp32/io_pin_remap.h b/cores/esp32/io_pin_remap.h
new file mode 100644
index 00000000000..10f11a5bf4c
--- /dev/null
+++ b/cores/esp32/io_pin_remap.h
@@ -0,0 +1,137 @@
+#ifndef __IO_PIN_REMAP_H__
+#define __IO_PIN_REMAP_H__
+
+#include "Arduino.h"
+
+#if defined(BOARD_HAS_PIN_REMAP) && !defined(BOARD_USES_HW_GPIO_NUMBERS)
+
+// Pin remapping functions
+int8_t digitalPinToGPIONumber(int8_t digitalPin);
+int8_t gpioNumberToDigitalPin(int8_t gpioNumber);
+
+// Apply pin remapping to API only when building libraries and user sketch
+#ifndef ARDUINO_CORE_BUILD
+
+// Override APIs requiring pin remapping
+
+// cores/esp32/Arduino.h
+#define pulseInLong(pin, args...) pulseInLong(digitalPinToGPIONumber(pin), args)
+#define pulseIn(pin, args...)     pulseIn(digitalPinToGPIONumber(pin), args)
+#define noTone(_pin)              noTone(digitalPinToGPIONumber(_pin))
+#define tone(_pin, args...)       tone(digitalPinToGPIONumber(_pin), args)
+
+// cores/esp32/esp32-hal.h
+#define analogGetChannel(pin)            analogGetChannel(digitalPinToGPIONumber(pin))
+#define analogWrite(pin, value)          analogWrite(digitalPinToGPIONumber(pin), value)
+#define analogWriteFrequency(pin, freq)  analogWriteFrequency(digitalPinToGPIONumber(pin), freq)
+#define analogWriteResolution(pin, bits) analogWriteResolution(digitalPinToGPIONumber(pin), bits)
+
+// cores/esp32/esp32-hal-adc.h
+#define analogRead(pin)                           analogRead(digitalPinToGPIONumber(pin))
+#define analogReadMilliVolts(pin)                 analogReadMilliVolts(digitalPinToGPIONumber(pin))
+#define analogSetPinAttenuation(pin, attenuation) analogSetPinAttenuation(digitalPinToGPIONumber(pin), attenuation)
+
+// cores/esp32/esp32-hal-dac.h
+#define dacDisable(pin)      dacDisable(digitalPinToGPIONumber(pin))
+#define dacWrite(pin, value) dacWrite(digitalPinToGPIONumber(pin), value)
+
+// cores/esp32/esp32-hal-gpio.h
+#define analogChannelToDigitalPin(channel)      gpioNumberToDigitalPin(analogChannelToDigitalPin(channel))
+#define digitalPinToAnalogChannel(pin)          digitalPinToAnalogChannel(digitalPinToGPIONumber(pin))
+#define digitalPinToTouchChannel(pin)           digitalPinToTouchChannel(digitalPinToGPIONumber(pin))
+#define digitalRead(pin)                        digitalRead(digitalPinToGPIONumber(pin))
+#define attachInterruptArg(pin, fcn, arg, mode) attachInterruptArg(digitalPinToGPIONumber(pin), fcn, arg, mode)
+#define attachInterrupt(pin, fcn, mode)         attachInterrupt(digitalPinToGPIONumber(pin), fcn, mode)
+#define detachInterrupt(pin)                    detachInterrupt(digitalPinToGPIONumber(pin))
+#define digitalWrite(pin, val)                  digitalWrite(digitalPinToGPIONumber(pin), val)
+#define pinMode(pin, mode)                      pinMode(digitalPinToGPIONumber(pin), mode)
+
+// cores/esp32/esp32-hal-i2c.h
+#define i2cInit(i2c_num, sda, scl, clk_speed) i2cInit(i2c_num, digitalPinToGPIONumber(sda), digitalPinToGPIONumber(scl), clk_speed)
+
+// cores/esp32/esp32-hal-i2c-slave.h
+#define i2cSlaveInit(num, sda, scl, slaveID, frequency, rx_len, tx_len) \
+  i2cSlaveInit(num, digitalPinToGPIONumber(sda), digitalPinToGPIONumber(scl), slaveID, frequency, rx_len, tx_len)
+
+// cores/esp32/esp32-hal-ledc.h
+#define ledcAttach(pin, freq, resolution)                 ledcAttach(digitalPinToGPIONumber(pin), freq, resolution)
+#define ledcAttachChannel(pin, freq, resolution, channel) ledcAttachChannel(digitalPinToGPIONumber(pin), freq, resolution, channel)
+#define ledcWrite(pin, duty)                              ledcWrite(digitalPinToGPIONumber(pin), duty)
+#define ledcWriteTone(pin, freq)                          ledcWriteTone(digitalPinToGPIONumber(pin), freq)
+#define ledcWriteNote(pin, note, octave)                  ledcWriteNote(digitalPinToGPIONumber(pin), note, octave)
+#define ledcRead(pin)                                     ledcRead(digitalPinToGPIONumber(pin))
+#define ledcReadFreq(pin)                                 ledcReadFreq(digitalPinToGPIONumber(pin))
+#define ledcDetach(pin)                                   ledcDetach(digitalPinToGPIONumber(pin))
+#define ledcChangeFrequency(pin, freq, resolution)        ledcChangeFrequency(digitalPinToGPIONumber(pin), freq, resolution)
+#define ledcOutputInvert(pin, out_invert)                 ledcOutputInvert(digitalPinToGPIONumber(pin), out_invert)
+
+#define ledcFade(pin, start_duty, target_duty, max_fade_time_ms) ledcFade(digitalPinToGPIONumber(pin), start_duty, target_duty, max_fade_time_ms)
+#define ledcFadeWithInterrupt(pin, start_duty, target_duty, max_fade_time_ms, userFunc) \
+  ledcFadeWithInterrupt(digitalPinToGPIONumber(pin), start_duty, target_duty, max_fade_time_ms, userFunc)
+#define ledcFadeWithInterruptArg(pin, start_duty, target_duty, max_fade_time_ms, userFunc, arg) \
+  ledcFadeWithInterruptArg(digitalPinToGPIONumber(pin), start_duty, target_duty, max_fade_time_ms, userFunc, arg)
+
+// cores/esp32/esp32-hal-matrix.h
+#define pinMatrixInAttach(pin, signal, inverted)                   pinMatrixInAttach(digitalPinToGPIONumber(pin), signal, inverted)
+#define pinMatrixOutAttach(pin, function, invertOut, invertEnable) pinMatrixOutAttach(digitalPinToGPIONumber(pin), function, invertOut, invertEnable)
+#define pinMatrixOutDetach(pin, invertOut, invertEnable)           pinMatrixOutDetach(digitalPinToGPIONumber(pin), invertOut, invertEnable)
+
+// cores/esp32/esp32-hal-rgb-led.h
+#define rgbLedWrite(pin, red_val, green_val, blue_val) rgbLedWrite(digitalPinToGPIONumber(pin), red_val, green_val, blue_val)
+
+// cores/esp32/esp32-hal-rmt.h
+#define rmtInit(pin, channel_direction, memsize, frequency_Hz) rmtInit(digitalPinToGPIONumber(pin), channel_direction, memsize, frequency_Hz)
+#define rmtSetEOT(pin, EOT_Level)                              rmtSetEOT(digitalPinToGPIONumber(pin), EOT_Level)
+#define rmtWrite(pin, data, num_rmt_symbols, timeout_ms)       rmtWrite(digitalPinToGPIONumber(pin), data, num_rmt_symbols, timeout_ms)
+#define rmtWriteAsync(pin, data, num_rmt_symbols)              rmtWriteAsync(digitalPinToGPIONumber(pin), data, num_rmt_symbols)
+#define rmtWriteLooping(pin, data, num_rmt_symbols)            rmtWriteLooping(digitalPinToGPIONumber(pin), data, num_rmt_symbols)
+#define rmtTransmitCompleted(pin)                              rmtTransmitCompleted(digitalPinToGPIONumber(pin))
+#define rmtRead(pin, data, num_rmt_symbols, timeout_ms)        rmtRead(digitalPinToGPIONumber(pin), data, num_rmt_symbols, timeout_ms)
+#define rmtReadAsync(pin, data, num_rmt_symbols)               rmtReadAsync(digitalPinToGPIONumber(pin), data, num_rmt_symbols)
+#define rmtReceiveCompleted(pin)                               rmtReceiveCompleted(digitalPinToGPIONumber(pin))
+#define rmtSetRxMaxThreshold(pin, idle_thres_ticks)            rmtSetRxMaxThreshold(digitalPinToGPIONumber(pin), idle_thres_ticks)
+#define rmtSetCarrier(pin, carrier_en, carrier_level, frequency_Hz, duty_percent) \
+  rmtSetCarrier(digitalPinToGPIONumber(pin), carrier_en, carrier_level, frequency_Hz, duty_percent)
+#define rmtSetRxMinThreshold(pin, filter_pulse_ticks) rmtSetRxMinThreshold(digitalPinToGPIONumber(pin), filter_pulse_ticks)
+#define rmtDeinit(pin)                                rmtDeinit(digitalPinToGPIONumber(pin))
+
+// cores/esp32/esp32-hal-sigmadelta.h
+#define sigmaDeltaAttach(pin, freq) sigmaDeltaAttach(digitalPinToGPIONumber(pin), freq)
+#define sigmaDeltaWrite(pin, duty)  sigmaDeltaWrite(digitalPinToGPIONumber(pin), duty)
+#define sigmaDeltaDetach(pin)       sigmaDeltaDetach(digitalPinToGPIONumber(pin))
+
+// cores/esp32/esp32-hal-spi.h
+#define spiAttachSCK(spi, sck)       spiAttachSCK(spi, digitalPinToGPIONumber(sck))
+#define spiAttachMISO(spi, miso)     spiAttachMISO(spi, digitalPinToGPIONumber(miso))
+#define spiAttachMOSI(spi, mosi)     spiAttachMOSI(spi, digitalPinToGPIONumber(mosi))
+#define spiAttachSS(spi, cs_num, ss) spiAttachSS(spi, cs_num, digitalPinToGPIONumber(ss))
+
+// cores/esp32/esp32-hal-touch.h && cores/esp32/esp32-hal-touch-ng.h
+#define touchInterruptGetLastStatus(pin)                       touchInterruptGetLastStatus(digitalPinToGPIONumber(pin))
+#define touchRead(pin)                                         touchRead(digitalPinToGPIONumber(pin))
+#define touchAttachInterruptArg(pin, userFunc, arg, threshold) touchAttachInterruptArg(digitalPinToGPIONumber(pin), userFunc, arg, threshold)
+#define touchAttachInterrupt(pin, userFunc, threshold)         touchAttachInterrupt(digitalPinToGPIONumber(pin), userFunc, threshold)
+#define touchDetachInterrupt(pin)                              touchDetachInterrupt(digitalPinToGPIONumber(pin))
+#define touchSleepWakeUpEnable(pin, threshold)                 touchSleepWakeUpEnable(digitalPinToGPIONumber(pin), threshold)
+
+// cores/esp32/esp32-hal-uart.h
+#define uartBegin(uart_nr, baudrate, config, rxPin, txPin, rx_buffer_size, tx_buffer_size, inverted, rxfifo_full_thrhd)                                  \
+  uartBegin(                                                                                                                                             \
+    uart_nr, baudrate, config, digitalPinToGPIONumber(rxPin), digitalPinToGPIONumber(txPin), rx_buffer_size, tx_buffer_size, inverted, rxfifo_full_thrhd \
+  )
+#define uartSetPins(uart, rxPin, txPin, ctsPin, rtsPin) \
+  uartSetPins(uart, digitalPinToGPIONumber(rxPin), digitalPinToGPIONumber(txPin), digitalPinToGPIONumber(ctsPin), digitalPinToGPIONumber(rtsPin))
+#define uartDetachPins(uart, rxPin, txPin, ctsPin, rtsPin) \
+  uartDetachPins(uart, digitalPinToGPIONumber(rxPin), digitalPinToGPIONumber(txPin), digitalPinToGPIONumber(ctsPin), digitalPinToGPIONumber(rtsPin))
+
+#endif  // ARDUINO_CORE_BUILD
+
+#else
+
+// pin remapping disabled: use stubs
+#define digitalPinToGPIONumber(digitalPin) (digitalPin)
+#define gpioNumberToDigitalPin(gpioNumber) (gpioNumber)
+
+#endif
+
+#endif /* __GPIO_PIN_REMAP_H__ */
diff --git a/cores/esp32/libb64/AUTHORS b/cores/esp32/libb64/AUTHORS
old mode 100755
new mode 100644
diff --git a/cores/esp32/libb64/LICENSE b/cores/esp32/libb64/LICENSE
old mode 100755
new mode 100644
index a6b56069e7f..ae8a7b9d181
--- a/cores/esp32/libb64/LICENSE
+++ b/cores/esp32/libb64/LICENSE
@@ -1,4 +1,4 @@
-Copyright-Only Dedication (based on United States law) 
+Copyright-Only Dedication (based on United States law)
 or Public Domain Certification
 
 The person or persons who have associated work with this document (the
@@ -26,4 +26,4 @@ Dedicator recognizes that, once placed in the public domain, the Work may be
 freely reproduced, distributed, transmitted, used, modified, built upon, or
 otherwise exploited by anyone for any purpose, commercial or non-commercial,
 and in any way, including by methods that have not yet been invented or
-conceived.
\ No newline at end of file
+conceived.
diff --git a/cores/esp32/libb64/cdecode.c b/cores/esp32/libb64/cdecode.c
old mode 100755
new mode 100644
index aa84ef60a8d..2485397d223
--- a/cores/esp32/libb64/cdecode.c
+++ b/cores/esp32/libb64/cdecode.c
@@ -8,41 +8,46 @@ For details, see http://sourceforge.net/projects/libb64
 #include "cdecode.h"
 #include <stdint.h>
 
-static int base64_decode_value_signed(int8_t value_in){
-  static const int8_t decoding[] = {62,-1,-1,-1,63,52,53,54,55,56,57,58,59,60,61,-1,-1,-1,-2,-1,-1,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,-1,-1,-1,-1,-1,-1,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51};
+static int base64_decode_value_signed(int8_t value_in) {
+  static const int8_t decoding[] = {62, -1, -1, -1, 63, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, -1, -1, -1, -2, -1, -1, -1, 0,  1,  2,  3,  4,
+                                    5,  6,  7,  8,  9,  10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, -1, -1, -1, -1, -1, -1,
+                                    26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51};
   static const int8_t decoding_size = sizeof(decoding);
   value_in -= 43;
-  if (value_in < 0 || value_in > decoding_size) return -1;
+  if (value_in < 0 || value_in >= decoding_size) {
+    return -1;
+  }
   return decoding[(int)value_in];
 }
 
-void base64_init_decodestate(base64_decodestate* state_in){
+void base64_init_decodestate(base64_decodestate *state_in) {
   state_in->step = step_a;
   state_in->plainchar = 0;
 }
 
-static int base64_decode_block_signed(const int8_t* code_in, const int length_in, int8_t* plaintext_out, base64_decodestate* state_in){
-  const int8_t* codechar = code_in;
-  int8_t* plainchar = plaintext_out;
+static int base64_decode_block_signed(const int8_t *code_in, const int length_in, int8_t *plaintext_out, base64_decodestate *state_in) {
+  const int8_t *codechar = code_in;
+  int8_t *plainchar = plaintext_out;
   int8_t fragment;
-  
+
   *plainchar = state_in->plainchar;
-  
-  switch (state_in->step){
-    while (1){
+
+  switch (state_in->step) {
+    while (1) {
       case step_a:
         do {
-          if (codechar == code_in+length_in){
+          if (codechar == code_in + length_in) {
             state_in->step = step_a;
             state_in->plainchar = *plainchar;
             return plainchar - plaintext_out;
           }
           fragment = (int8_t)base64_decode_value_signed(*codechar++);
         } while (fragment < 0);
-        *plainchar    = (fragment & 0x03f) << 2;
+        *plainchar = (fragment & 0x03f) << 2;
+        // fall through
       case step_b:
         do {
-          if (codechar == code_in+length_in){
+          if (codechar == code_in + length_in) {
             state_in->step = step_b;
             state_in->plainchar = *plainchar;
             return plainchar - plaintext_out;
@@ -50,10 +55,11 @@ static int base64_decode_block_signed(const int8_t* code_in, const int length_in
           fragment = (int8_t)base64_decode_value_signed(*codechar++);
         } while (fragment < 0);
         *plainchar++ |= (fragment & 0x030) >> 4;
-        *plainchar    = (fragment & 0x00f) << 4;
+        *plainchar = (fragment & 0x00f) << 4;
+        // fall through
       case step_c:
         do {
-          if (codechar == code_in+length_in){
+          if (codechar == code_in + length_in) {
             state_in->step = step_c;
             state_in->plainchar = *plainchar;
             return plainchar - plaintext_out;
@@ -61,39 +67,42 @@ static int base64_decode_block_signed(const int8_t* code_in, const int length_in
           fragment = (int8_t)base64_decode_value_signed(*codechar++);
         } while (fragment < 0);
         *plainchar++ |= (fragment & 0x03c) >> 2;
-        *plainchar    = (fragment & 0x003) << 6;
+        *plainchar = (fragment & 0x003) << 6;
+        // fall through
       case step_d:
         do {
-          if (codechar == code_in+length_in){
+          if (codechar == code_in + length_in) {
             state_in->step = step_d;
             state_in->plainchar = *plainchar;
             return plainchar - plaintext_out;
           }
           fragment = (int8_t)base64_decode_value_signed(*codechar++);
         } while (fragment < 0);
-        *plainchar++   |= (fragment & 0x03f);
+        *plainchar++ |= (fragment & 0x03f);
     }
   }
   /* control should not reach here */
   return plainchar - plaintext_out;
 }
 
-static int base64_decode_chars_signed(const int8_t* code_in, const int length_in, int8_t* plaintext_out){
+static int base64_decode_chars_signed(const int8_t *code_in, const int length_in, int8_t *plaintext_out) {
   base64_decodestate _state;
   base64_init_decodestate(&_state);
   int len = base64_decode_block_signed(code_in, length_in, plaintext_out, &_state);
-  if(len > 0) plaintext_out[len] = 0;
+  if (len > 0) {
+    plaintext_out[len] = 0;
+  }
   return len;
 }
 
-int base64_decode_value(char value_in){
-  return base64_decode_value_signed(*((int8_t *) &value_in));
+int base64_decode_value(char value_in) {
+  return base64_decode_value_signed(*((int8_t *)&value_in));
 }
 
-int base64_decode_block(const char* code_in, const int length_in, char* plaintext_out, base64_decodestate* state_in){
-  return base64_decode_block_signed((int8_t *) code_in, length_in, (int8_t *) plaintext_out, state_in);
+int base64_decode_block(const char *code_in, const int length_in, char *plaintext_out, base64_decodestate *state_in) {
+  return base64_decode_block_signed((int8_t *)code_in, length_in, (int8_t *)plaintext_out, state_in);
 }
 
-int base64_decode_chars(const char* code_in, const int length_in, char* plaintext_out){
-  return base64_decode_chars_signed((int8_t *) code_in, length_in, (int8_t *) plaintext_out);
+int base64_decode_chars(const char *code_in, const int length_in, char *plaintext_out) {
+  return base64_decode_chars_signed((int8_t *)code_in, length_in, (int8_t *)plaintext_out);
 }
diff --git a/cores/esp32/libb64/cdecode.h b/cores/esp32/libb64/cdecode.h
old mode 100755
new mode 100644
index 44f114f691c..f2ec3d60673
--- a/cores/esp32/libb64/cdecode.h
+++ b/cores/esp32/libb64/cdecode.h
@@ -15,24 +15,27 @@ extern "C" {
 #endif
 
 typedef enum {
-    step_a, step_b, step_c, step_d
+  step_a,
+  step_b,
+  step_c,
+  step_d
 } base64_decodestep;
 
 typedef struct {
-    base64_decodestep step;
-    char plainchar;
+  base64_decodestep step;
+  char plainchar;
 } base64_decodestate;
 
-void base64_init_decodestate(base64_decodestate* state_in);
+void base64_init_decodestate(base64_decodestate *state_in);
 
 int base64_decode_value(char value_in);
 
-int base64_decode_block(const char* code_in, const int length_in, char* plaintext_out, base64_decodestate* state_in);
+int base64_decode_block(const char *code_in, const int length_in, char *plaintext_out, base64_decodestate *state_in);
 
-int base64_decode_chars(const char* code_in, const int length_in, char* plaintext_out);
+int base64_decode_chars(const char *code_in, const int length_in, char *plaintext_out);
 
 #ifdef __cplusplus
-} // extern "C"
+}  // extern "C"
 #endif
 
 #endif /* BASE64_CDECODE_H */
diff --git a/cores/esp32/libb64/cencode.c b/cores/esp32/libb64/cencode.c
old mode 100755
new mode 100644
index 48a0d30b7e9..75b0f31bc41
--- a/cores/esp32/libb64/cencode.c
+++ b/cores/esp32/libb64/cencode.c
@@ -7,96 +7,92 @@ For details, see http://sourceforge.net/projects/libb64
 
 #include "cencode.h"
 
-void base64_init_encodestate(base64_encodestate* state_in)
-{
-    state_in->step = step_A;
-    state_in->result = 0;
+void base64_init_encodestate(base64_encodestate *state_in) {
+  state_in->step = step_A;
+  state_in->result = 0;
 }
 
-char base64_encode_value(char value_in)
-{
-    static const char* encoding = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
-    if (value_in > 63) {
-        return '=';
-    }
-    return encoding[(int)value_in];
+char base64_encode_value(char value_in) {
+  static const char *encoding = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
+  if (value_in > 63) {
+    return '=';
+  }
+  return encoding[(int)value_in];
 }
 
-int base64_encode_block(const char* plaintext_in, int length_in, char* code_out, base64_encodestate* state_in)
-{
-    const char* plainchar = plaintext_in;
-    const char* const plaintextend = plaintext_in + length_in;
-    char* codechar = code_out;
-    char result;
-    char fragment;
+int base64_encode_block(const char *plaintext_in, int length_in, char *code_out, base64_encodestate *state_in) {
+  const char *plainchar = plaintext_in;
+  const char *const plaintextend = plaintext_in + length_in;
+  char *codechar = code_out;
+  char result;
+  char fragment;
 
-    result = state_in->result;
+  result = state_in->result;
 
-    switch (state_in->step) {
-        while (1) {
-        case step_A:
-            if (plainchar == plaintextend) {
-                state_in->result = result;
-                state_in->step = step_A;
-                return codechar - code_out;
-            }
-            fragment = *plainchar++;
-            result = (fragment & 0x0fc) >> 2;
-            *codechar++ = base64_encode_value(result);
-            result = (fragment & 0x003) << 4;
-        case step_B:
-            if (plainchar == plaintextend) {
-                state_in->result = result;
-                state_in->step = step_B;
-                return codechar - code_out;
-            }
-            fragment = *plainchar++;
-            result |= (fragment & 0x0f0) >> 4;
-            *codechar++ = base64_encode_value(result);
-            result = (fragment & 0x00f) << 2;
-        case step_C:
-            if (plainchar == plaintextend) {
-                state_in->result = result;
-                state_in->step = step_C;
-                return codechar - code_out;
-            }
-            fragment = *plainchar++;
-            result |= (fragment & 0x0c0) >> 6;
-            *codechar++ = base64_encode_value(result);
-            result  = (fragment & 0x03f) >> 0;
-            *codechar++ = base64_encode_value(result);
+  switch (state_in->step) {
+    while (1) {
+      case step_A:
+        if (plainchar == plaintextend) {
+          state_in->result = result;
+          state_in->step = step_A;
+          return codechar - code_out;
+        }
+        fragment = *plainchar++;
+        result = (fragment & 0x0fc) >> 2;
+        *codechar++ = base64_encode_value(result);
+        result = (fragment & 0x003) << 4;
+        // fall through
+      case step_B:
+        if (plainchar == plaintextend) {
+          state_in->result = result;
+          state_in->step = step_B;
+          return codechar - code_out;
         }
+        fragment = *plainchar++;
+        result |= (fragment & 0x0f0) >> 4;
+        *codechar++ = base64_encode_value(result);
+        result = (fragment & 0x00f) << 2;
+        // fall through
+      case step_C:
+        if (plainchar == plaintextend) {
+          state_in->result = result;
+          state_in->step = step_C;
+          return codechar - code_out;
+        }
+        fragment = *plainchar++;
+        result |= (fragment & 0x0c0) >> 6;
+        *codechar++ = base64_encode_value(result);
+        result = (fragment & 0x03f) >> 0;
+        *codechar++ = base64_encode_value(result);
     }
-    /* control should not reach here */
-    return codechar - code_out;
+  }
+  /* control should not reach here */
+  return codechar - code_out;
 }
 
-int base64_encode_blockend(char* code_out, base64_encodestate* state_in)
-{
-    char* codechar = code_out;
+int base64_encode_blockend(char *code_out, base64_encodestate *state_in) {
+  char *codechar = code_out;
 
-    switch (state_in->step) {
+  switch (state_in->step) {
     case step_B:
-        *codechar++ = base64_encode_value(state_in->result);
-        *codechar++ = '=';
-        *codechar++ = '=';
-        break;
+      *codechar++ = base64_encode_value(state_in->result);
+      *codechar++ = '=';
+      *codechar++ = '=';
+      break;
     case step_C:
-        *codechar++ = base64_encode_value(state_in->result);
-        *codechar++ = '=';
-        break;
-    case step_A:
-        break;
-    }
-    *codechar = 0x00;
+      *codechar++ = base64_encode_value(state_in->result);
+      *codechar++ = '=';
+      break;
+    case step_A: break;
+  }
+  *codechar = 0x00;
 
-    return codechar - code_out;
+  return codechar - code_out;
 }
 
-int base64_encode_chars(const char* plaintext_in, int length_in, char* code_out)
-{
-    base64_encodestate _state;
-    base64_init_encodestate(&_state);
-    int len = base64_encode_block(plaintext_in, length_in, code_out, &_state);
-    return len + base64_encode_blockend((code_out + len), &_state);
+int base64_encode_chars(const char *plaintext_in, int length_in, char *code_out) {
+  base64_encodestate _state;
+  base64_init_encodestate(&_state);
+  int len = base64_encode_block(plaintext_in, length_in, code_out, &_state);
+  return len + base64_encode_blockend((code_out + len), &_state);
 }
diff --git a/cores/esp32/libb64/cencode.h b/cores/esp32/libb64/cencode.h
old mode 100755
new mode 100644
index 51bb3f3dd75..165220ec0bf
--- a/cores/esp32/libb64/cencode.h
+++ b/cores/esp32/libb64/cencode.h
@@ -15,27 +15,29 @@ extern "C" {
 #endif
 
 typedef enum {
-    step_A, step_B, step_C
+  step_A,
+  step_B,
+  step_C
 } base64_encodestep;
 
 typedef struct {
-    base64_encodestep step;
-    char result;
-    int stepcount;
+  base64_encodestep step;
+  char result;
+  int stepcount;
 } base64_encodestate;
 
-void base64_init_encodestate(base64_encodestate* state_in);
+void base64_init_encodestate(base64_encodestate *state_in);
 
 char base64_encode_value(char value_in);
 
-int base64_encode_block(const char* plaintext_in, int length_in, char* code_out, base64_encodestate* state_in);
+int base64_encode_block(const char *plaintext_in, int length_in, char *code_out, base64_encodestate *state_in);
 
-int base64_encode_blockend(char* code_out, base64_encodestate* state_in);
+int base64_encode_blockend(char *code_out, base64_encodestate *state_in);
 
-int base64_encode_chars(const char* plaintext_in, int length_in, char* code_out);
+int base64_encode_chars(const char *plaintext_in, int length_in, char *code_out);
 
 #ifdef __cplusplus
-} // extern "C"
+}  // extern "C"
 #endif
 
 #endif /* BASE64_CENCODE_H */
diff --git a/cores/esp32/main.cpp b/cores/esp32/main.cpp
index 41f1985b94c..6c4d50a9a84 100644
--- a/cores/esp32/main.cpp
+++ b/cores/esp32/main.cpp
@@ -1,31 +1,108 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "esp_task_wdt.h"
+#include "soc/rtc.h"
 #include "Arduino.h"
+#if (ARDUINO_USB_CDC_ON_BOOT | ARDUINO_USB_MSC_ON_BOOT | ARDUINO_USB_DFU_ON_BOOT) && !ARDUINO_USB_MODE
+#include "USB.h"
+#if ARDUINO_USB_MSC_ON_BOOT
+#include "FirmwareMSC.h"
+#endif
+#endif
+
+#include "chip-debug-report.h"
+
+#ifndef ARDUINO_LOOP_STACK_SIZE
+#ifndef CONFIG_ARDUINO_LOOP_STACK_SIZE
+#define ARDUINO_LOOP_STACK_SIZE 8192
+#else
+#define ARDUINO_LOOP_STACK_SIZE CONFIG_ARDUINO_LOOP_STACK_SIZE
+#endif
+#endif
 
 TaskHandle_t loopTaskHandle = NULL;
 
 #if CONFIG_AUTOSTART_ARDUINO
+#if CONFIG_FREERTOS_UNICORE
+void yieldIfNecessary(void) {
+  static uint64_t lastYield = 0;
+  uint64_t now = millis();
+  if ((now - lastYield) > 2000) {
+    lastYield = now;
+    vTaskDelay(5);  //delay 1 RTOS tick
+  }
+}
+#endif
 
 bool loopTaskWDTEnabled;
 
-void loopTask(void *pvParameters)
-{
-    setup();
-    for(;;) {
-        if(loopTaskWDTEnabled){
-            esp_task_wdt_reset();
-        }
-        loop();
-        if (serialEventRun) serialEventRun();
+__attribute__((weak)) size_t getArduinoLoopTaskStackSize(void) {
+  return ARDUINO_LOOP_STACK_SIZE;
+}
+
+__attribute__((weak)) bool shouldPrintChipDebugReport(void) {
+  return false;
+}
+
+void loopTask(void *pvParameters) {
+#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL)
+  // sets UART0 (default console) RX/TX pins as already configured in boot or as defined in variants/pins_arduino.h
+  Serial0.setPins(gpioNumberToDigitalPin(SOC_RX0), gpioNumberToDigitalPin(SOC_TX0));
+#endif
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+  printBeforeSetupInfo();
+#else
+  if (shouldPrintChipDebugReport()) {
+    printBeforeSetupInfo();
+  }
+#endif
+  setup();
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+  printAfterSetupInfo();
+#else
+  if (shouldPrintChipDebugReport()) {
+    printAfterSetupInfo();
+  }
+#endif
+  for (;;) {
+#if CONFIG_FREERTOS_UNICORE
+    yieldIfNecessary();
+#endif
+    if (loopTaskWDTEnabled) {
+      esp_task_wdt_reset();
+    }
+    loop();
+    if (serialEventRun) {
+      serialEventRun();
     }
+  }
 }
 
-extern "C" void app_main()
-{
-    loopTaskWDTEnabled = false;
-    initArduino();
-    xTaskCreateUniversal(loopTask, "loopTask", 8192, NULL, 1, &loopTaskHandle, CONFIG_ARDUINO_RUNNING_CORE);
+extern "C" void app_main() {
+#ifdef F_XTAL_MHZ
+#if !CONFIG_IDF_TARGET_ESP32S2  // ESP32-S2 does not support rtc_clk_xtal_freq_update
+  rtc_clk_xtal_freq_update((rtc_xtal_freq_t)F_XTAL_MHZ);
+  rtc_clk_cpu_freq_set_xtal();
+#endif
+#endif
+#ifdef F_CPU
+  setCpuFrequencyMhz(F_CPU / 1000000);
+#endif
+#if ARDUINO_USB_CDC_ON_BOOT && !ARDUINO_USB_MODE
+  Serial.begin();
+#endif
+#if ARDUINO_USB_MSC_ON_BOOT && !ARDUINO_USB_MODE
+  MSC_Update.begin();
+#endif
+#if ARDUINO_USB_DFU_ON_BOOT && !ARDUINO_USB_MODE
+  USB.enableDFU();
+#endif
+#if ARDUINO_USB_ON_BOOT && !ARDUINO_USB_MODE
+  USB.begin();
+#endif
+  loopTaskWDTEnabled = false;
+  initArduino();
+  xTaskCreateUniversal(loopTask, "loopTask", getArduinoLoopTaskStackSize(), NULL, 1, &loopTaskHandle, ARDUINO_RUNNING_CORE);
 }
 
 #endif
diff --git a/cores/esp32/pgmspace.h b/cores/esp32/pgmspace.h
index 75f7e801b95..4a53b1d668f 100644
--- a/cores/esp32/pgmspace.h
+++ b/cores/esp32/pgmspace.h
@@ -1,7 +1,7 @@
-/* 
+/*
   Copyright (c) 2015 Hristo Gochkov. All rights reserved.
   This file is part of the RaspberryPi core for Arduino environment.
- 
+
   This library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
@@ -30,28 +30,32 @@ typedef long prog_int32_t;
 typedef unsigned long prog_uint32_t;
 
 #define PROGMEM
-#define PGM_P         const char *
-#define PGM_VOID_P    const void *
-#define PSTR(s)       (s)
-#define _SFR_BYTE(n)  (n)
+#define PGM_P        const char *
+#define PGM_VOID_P   const void *
+#define PSTR(s)      (s)
+#define _SFR_BYTE(n) (n)
 
-#define pgm_read_byte(addr)   (*(const unsigned char *)(addr))
-#define pgm_read_word(addr) ({ \
-  typeof(addr) _addr = (addr); \
-  *(const unsigned short *)(_addr); \
-})
-#define pgm_read_dword(addr) ({ \
-  typeof(addr) _addr = (addr); \
-  *(const unsigned long *)(_addr); \
-})
-#define pgm_read_float(addr) ({ \
-  typeof(addr) _addr = (addr); \
-  *(const float *)(_addr); \
-})
-#define pgm_read_ptr(addr) ({ \
-  typeof(addr) _addr = (addr); \
-  *(void * const *)(_addr); \
-})
+#define pgm_read_byte(addr) (*(const unsigned char *)(addr))
+#define pgm_read_word(addr)           \
+  ({                                  \
+    typeof(addr) _addr = (addr);      \
+    *(const unsigned short *)(_addr); \
+  })
+#define pgm_read_dword(addr)         \
+  ({                                 \
+    typeof(addr) _addr = (addr);     \
+    *(const unsigned long *)(_addr); \
+  })
+#define pgm_read_float(addr)     \
+  ({                             \
+    typeof(addr) _addr = (addr); \
+    *(const float *)(_addr);     \
+  })
+#define pgm_read_ptr(addr)       \
+  ({                             \
+    typeof(addr) _addr = (addr); \
+    *(void *const *)(_addr);     \
+  })
 
 #define pgm_get_far_address(x) ((uint32_t)(&(x)))
 
diff --git a/cores/esp32/stdlib_noniso.c b/cores/esp32/stdlib_noniso.c
index e7920489037..0acb26c67b9 100644
--- a/cores/esp32/stdlib_noniso.c
+++ b/cores/esp32/stdlib_noniso.c
@@ -1,5 +1,5 @@
 /*
- core_esp8266_noniso.c - nonstandard (but usefull) conversion functions
+ core_esp8266_noniso.c - nonstandard (but useful) conversion functions
 
  Copyright (c) 2014 Ivan Grokhotkov. All rights reserved.
  This file is part of the esp8266 core for Arduino environment.
@@ -28,134 +28,188 @@
 #include <stdint.h>
 #include <math.h>
 #include "stdlib_noniso.h"
-
-void reverse(char* begin, char* end) {
-    char *is = begin;
-    char *ie = end - 1;
-    while(is < ie) {
-        char tmp = *ie;
-        *ie = *is;
-        *is = tmp;
-        ++is;
-        --ie;
-    }
+#include "esp_system.h"
+
+static void reverse(char *begin, char *end) {
+  char *is = begin;
+  char *ie = end - 1;
+  while (is < ie) {
+    char tmp = *ie;
+    *ie = *is;
+    *is = tmp;
+    ++is;
+    --ie;
+  }
 }
 
-char* ltoa(long value, char* result, int base) {
-    if(base < 2 || base > 16) {
-        *result = 0;
-        return result;
-    }
-
-    char* out = result;
-    long quotient = abs(value);
-
-    do {
-        const long tmp = quotient / base;
-        *out = "0123456789abcdef"[quotient - (tmp * base)];
-        ++out;
-        quotient = tmp;
-    } while(quotient);
-
-    // Apply negative sign
-    if(value < 0)
-        *out++ = '-';
+char *ltoa(long value, char *result, int base) {
+  if (base < 2 || base > 16) {
+    *result = 0;
+    return result;
+  }
+
+  char *out = result;
+  long quotient = abs(value);
+
+  do {
+    const long tmp = quotient / base;
+    *out = "0123456789abcdef"[quotient - (tmp * base)];
+    ++out;
+    quotient = tmp;
+  } while (quotient);
+
+  // Apply negative sign
+  if (value < 0) {
+    *out++ = '-';
+  }
+
+  reverse(result, out);
+  *out = 0;
+  return result;
+}
 
-    reverse(result, out);
-    *out = 0;
+char *lltoa(long long val, char *result, int base) {
+  if (base < 2 || base > 16) {
+    *result = 0;
     return result;
+  }
+
+  char *out = result;
+  long long quotient = val > 0 ? val : -val;
+
+  do {
+    const long long tmp = quotient / base;
+    *out = "0123456789abcdef"[quotient - (tmp * base)];
+    ++out;
+    quotient = tmp;
+  } while (quotient);
+
+  // Apply negative sign
+  if (val < 0) {
+    *out++ = '-';
+  }
+
+  reverse(result, out);
+  *out = 0;
+  return result;
 }
 
-char* ultoa(unsigned long value, char* result, int base) {
-    if(base < 2 || base > 16) {
-        *result = 0;
-        return result;
-    }
+char *ultoa(unsigned long value, char *result, int base) {
+  if (base < 2 || base > 16) {
+    *result = 0;
+    return result;
+  }
 
-    char* out = result;
-    unsigned long quotient = value;
+  char *out = result;
+  unsigned long quotient = value;
 
-    do {
-        const unsigned long tmp = quotient / base;
-        *out = "0123456789abcdef"[quotient - (tmp * base)];
-        ++out;
-        quotient = tmp;
-    } while(quotient);
+  do {
+    const unsigned long tmp = quotient / base;
+    *out = "0123456789abcdef"[quotient - (tmp * base)];
+    ++out;
+    quotient = tmp;
+  } while (quotient);
 
-    reverse(result, out);
-    *out = 0;
-    return result;
+  reverse(result, out);
+  *out = 0;
+  return result;
 }
 
-char * dtostrf(double number, signed char width, unsigned char prec, char *s) {
-    bool negative = false;
-
-    if (isnan(number)) {
-        strcpy(s, "nan");
-        return s;
-    }
-    if (isinf(number)) {
-        strcpy(s, "inf");
-        return s;
-    }
-
-    char* out = s;
+char *ulltoa(unsigned long long val, char *result, int base) {
+  if (base < 2 || base > 16) {
+    *result = 0;
+    return result;
+  }
 
-    int fillme = width; // how many cells to fill for the integer part
-    if (prec > 0) {
-        fillme -= (prec+1);
-    }
+  char *out = result;
+  unsigned long long quotient = val;
 
-    // Handle negative numbers
-    if (number < 0.0) {
-        negative = true;
-        fillme--;
-        number = -number;
-    }
+  do {
+    const unsigned long long tmp = quotient / base;
+    *out = "0123456789abcdef"[quotient - (tmp * base)];
+    ++out;
+    quotient = tmp;
+  } while (quotient);
 
-    // Round correctly so that print(1.999, 2) prints as "2.00"
-    // I optimized out most of the divisions
-    double rounding = 2.0;
-    for (uint8_t i = 0; i < prec; ++i)
-        rounding *= 10.0;
-    rounding = 1.0 / rounding;
-
-    number += rounding;
-
-    // Figure out how big our number really is
-    double tenpow = 1.0;
-    int digitcount = 1;
-    while (number >= 10.0 * tenpow) {
-        tenpow *= 10.0;
-        digitcount++;
-    }
+  reverse(result, out);
+  *out = 0;
+  return result;
+}
 
-    number /= tenpow;
-    fillme -= digitcount;
+char *dtostrf(double number, signed int width, unsigned int prec, char *s) {
+  bool negative = false;
 
-    // Pad unused cells with spaces
-    while (fillme-- > 0) {
-        *out++ = ' ';
+  if (isnan(number)) {
+    strcpy(s, "nan");
+    return s;
+  }
+  if (isinf(number)) {
+    strcpy(s, "inf");
+    return s;
+  }
+
+  char *out = s;
+
+  int fillme = width;  // how many cells to fill for the integer part
+  if (prec > 0) {
+    fillme -= (prec + 1);
+  }
+
+  // Handle negative numbers
+  if (number < 0.0) {
+    negative = true;
+    fillme--;
+    number = -number;
+  }
+
+  // Round correctly so that print(1.999, 2) prints as "2.00"
+  // I optimized out most of the divisions
+  double rounding = 2.0;
+  for (unsigned int i = 0; i < prec; ++i) {
+    rounding *= 10.0;
+  }
+  rounding = 1.0 / rounding;
+
+  number += rounding;
+
+  // Figure out how big our number really is
+  double tenpow = 1.0;
+  unsigned int digitcount = 1;
+  while (number >= 10.0 * tenpow) {
+    tenpow *= 10.0;
+    digitcount++;
+  }
+
+  number /= tenpow;
+  fillme -= digitcount;
+
+  // Pad unused cells with spaces
+  while (fillme-- > 0) {
+    *out++ = ' ';
+  }
+
+  // Handle negative sign
+  if (negative) {
+    *out++ = '-';
+  }
+
+  // Print the digits, and if necessary, the decimal point
+  digitcount += prec;
+  int8_t digit = 0;
+  while (digitcount-- > 0) {
+    digit = (int8_t)number;
+    if (digit > 9) {
+      digit = 9;  // insurance
     }
-
-    // Handle negative sign
-    if (negative) *out++ = '-';
-
-    // Print the digits, and if necessary, the decimal point
-    digitcount += prec;
-    int8_t digit = 0;
-    while (digitcount-- > 0) {
-        digit = (int8_t)number;
-        if (digit > 9) digit = 9; // insurance
-        *out++ = (char)('0' | digit);
-        if ((digitcount == prec) && (prec > 0)) {
-            *out++ = '.';
-        }
-        number -= digit;
-        number *= 10.0;
+    *out++ = (char)('0' | digit);
+    if ((digitcount == prec) && (prec > 0)) {
+      *out++ = '.';
     }
+    number -= digit;
+    number *= 10.0;
+  }
 
-    // make sure the string is terminated
-    *out = 0;
-    return s;
+  // make sure the string is terminated
+  *out = 0;
+  return s;
 }
diff --git a/cores/esp32/stdlib_noniso.h b/cores/esp32/stdlib_noniso.h
index 3df2cc2a1b6..8c162e69065 100644
--- a/cores/esp32/stdlib_noniso.h
+++ b/cores/esp32/stdlib_noniso.h
@@ -1,5 +1,5 @@
 /*
-  stdlib_noniso.h - nonstandard (but usefull) conversion functions
+  stdlib_noniso.h - nonstandard (but useful) conversion functions
 
   Copyright (c) 2014 Ivan Grokhotkov. All rights reserved.
 
@@ -27,23 +27,26 @@ extern "C" {
 
 int atoi(const char *s);
 
-long atol(const char* s);
+long atol(const char *s);
 
-double atof(const char* s);
+double atof(const char *s);
 
-char* itoa (int val, char *s, int radix);
+char *itoa(int val, char *s, int radix);
 
-char* ltoa (long val, char *s, int radix);
+char *ltoa(long val, char *s, int radix);
 
-char* utoa (unsigned int val, char *s, int radix);
+char *lltoa(long long val, char *s, int radix);
 
-char* ultoa (unsigned long val, char *s, int radix);
+char *utoa(unsigned int val, char *s, int radix);
 
-char* dtostrf (double val, signed char width, unsigned char prec, char *s);
+char *ultoa(unsigned long val, char *s, int radix);
+
+char *ulltoa(unsigned long long val, char *s, int radix);
+
+char *dtostrf(double val, signed int width, unsigned int prec, char *s);
 
 #ifdef __cplusplus
-} // extern "C"
+}  // extern "C"
 #endif
 
-
 #endif
diff --git a/cores/esp32/wiring_private.h b/cores/esp32/wiring_private.h
index 2c53565a674..753fe40f867 100644
--- a/cores/esp32/wiring_private.h
+++ b/cores/esp32/wiring_private.h
@@ -39,7 +39,7 @@ typedef void (*voidFuncPtr)(void);
 void initPins();
 
 #ifdef __cplusplus
-} // extern "C"
+}  // extern "C"
 #endif
 
 #endif
diff --git a/cores/esp32/wiring_pulse.c b/cores/esp32/wiring_pulse.c
index e63267895d4..1f9d175ad84 100644
--- a/cores/esp32/wiring_pulse.c
+++ b/cores/esp32/wiring_pulse.c
@@ -17,34 +17,30 @@
 //#include <limits.h>
 #include "wiring_private.h"
 #include "pins_arduino.h"
+#include "esp_cpu.h"
 
-
-extern uint32_t xthal_get_ccount();
-
-#define WAIT_FOR_PIN_STATE(state) \
-    while (digitalRead(pin) != (state)) { \
-        if (xthal_get_ccount() - start_cycle_count > timeout_cycles) { \
-            return 0; \
-        } \
-    }
+#define WAIT_FOR_PIN_STATE(state)                                         \
+  while (digitalRead(pin) != (state)) {                                   \
+    if (esp_cpu_get_cycle_count() - start_cycle_count > timeout_cycles) { \
+      return 0;                                                           \
+    }                                                                     \
+  }
 
 // max timeout is 27 seconds at 160MHz clock and 54 seconds at 80MHz clock
-unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout)
-{
-    const uint32_t max_timeout_us = clockCyclesToMicroseconds(UINT_MAX);
-    if (timeout > max_timeout_us) {
-        timeout = max_timeout_us;
-    }
-    const uint32_t timeout_cycles = microsecondsToClockCycles(timeout);
-    const uint32_t start_cycle_count = xthal_get_ccount();
-    WAIT_FOR_PIN_STATE(!state);
-    WAIT_FOR_PIN_STATE(state);
-    const uint32_t pulse_start_cycle_count = xthal_get_ccount();
-    WAIT_FOR_PIN_STATE(!state);
-    return clockCyclesToMicroseconds(xthal_get_ccount() - pulse_start_cycle_count);
+unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout) {
+  const uint32_t max_timeout_us = clockCyclesToMicroseconds(UINT_MAX);
+  if (timeout > max_timeout_us) {
+    timeout = max_timeout_us;
+  }
+  const uint32_t timeout_cycles = microsecondsToClockCycles(timeout);
+  const uint32_t start_cycle_count = esp_cpu_get_cycle_count();
+  WAIT_FOR_PIN_STATE(!state);
+  WAIT_FOR_PIN_STATE(state);
+  const uint32_t pulse_start_cycle_count = esp_cpu_get_cycle_count();
+  WAIT_FOR_PIN_STATE(!state);
+  return clockCyclesToMicroseconds(esp_cpu_get_cycle_count() - pulse_start_cycle_count);
 }
 
-unsigned long pulseInLong(uint8_t pin, uint8_t state, unsigned long timeout)
-{
-    return pulseIn(pin, state, timeout);
+unsigned long pulseInLong(uint8_t pin, uint8_t state, unsigned long timeout) {
+  return pulseIn(pin, state, timeout);
 }
diff --git a/cores/esp32/wiring_shift.c b/cores/esp32/wiring_shift.c
index 41cf8a0fa5b..2198b2e5243 100644
--- a/cores/esp32/wiring_shift.c
+++ b/cores/esp32/wiring_shift.c
@@ -20,32 +20,34 @@
 #include "esp32-hal.h"
 #include "wiring_private.h"
 
-uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) {
-    uint8_t value = 0;
-    uint8_t i;
+uint8_t shiftIn(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder) {  // codespell:ignore shiftin
+  uint8_t value = 0;
+  uint8_t i;
 
-    for(i = 0; i < 8; ++i) {
-        //digitalWrite(clockPin, HIGH);
-        if(bitOrder == LSBFIRST)
-            value |= digitalRead(dataPin) << i;
-        else
-            value |= digitalRead(dataPin) << (7 - i);
-        digitalWrite(clockPin, HIGH);
-        digitalWrite(clockPin, LOW);
+  for (i = 0; i < 8; ++i) {
+    //digitalWrite(clockPin, HIGH);
+    if (bitOrder == LSBFIRST) {
+      value |= digitalRead(dataPin) << i;
+    } else {
+      value |= digitalRead(dataPin) << (7 - i);
     }
-    return value;
+    digitalWrite(clockPin, HIGH);
+    digitalWrite(clockPin, LOW);
+  }
+  return value;
 }
 
 void shiftOut(uint8_t dataPin, uint8_t clockPin, uint8_t bitOrder, uint8_t val) {
-    uint8_t i;
+  uint8_t i;
 
-    for(i = 0; i < 8; i++) {
-        if(bitOrder == LSBFIRST)
-            digitalWrite(dataPin, !!(val & (1 << i)));
-        else
-            digitalWrite(dataPin, !!(val & (1 << (7 - i))));
-
-        digitalWrite(clockPin, HIGH);
-        digitalWrite(clockPin, LOW);
+  for (i = 0; i < 8; i++) {
+    if (bitOrder == LSBFIRST) {
+      digitalWrite(dataPin, !!(val & (1 << i)));
+    } else {
+      digitalWrite(dataPin, !!(val & (1 << (7 - i))));
     }
+
+    digitalWrite(clockPin, HIGH);
+    digitalWrite(clockPin, LOW);
+  }
 }
diff --git a/docs/ISSUE_TEMPLATE.md b/docs/ISSUE_TEMPLATE.md
deleted file mode 100644
index 5cf96ef213b..00000000000
--- a/docs/ISSUE_TEMPLATE.md
+++ /dev/null
@@ -1,47 +0,0 @@
-Make your question, not a Statement, inclusive. Include all pertinent information:
-
-What you are trying to do  
-Describe your system (Hardware, computer, O/S, core version, environment)  
-Describe what is failing  
-Show the shortest possible code that will duplicate the error  
-Show the EXACT error message (it doesn't work is not enough)  
-Then if someone is interested and knowledgeable you might get a answer.  All of this work on your part shows us that you have worked to solve YOUR problem. The more complete your issue posting is, the more likely someone will volunteer their time to help you.
-
-If you have a Guru Meditation Error or Backtrace, ***please decode it***:
-[ExceptionDecoder](https://github.com/me-no-dev/EspExceptionDecoder)
-
------------------------------ Remove above -----------------------------
-
-
-### Hardware:
-|||||||
-|:---|---|---|---|---|---|
-|<B>Board</B>|ESP32 Dev Module|node32|ttgo_lora|ESP32-S2-Saola|Custom w/ ESP32-S2-WROVER 16MB|
-|<B>Version/Date</B>|1.0.4|2.0.0|0badbeef|11/jul/2017|today's master|
-|<B>IDE name</B>|Arduino IDE|Atom + Platform.io|IDF component|VSCode|
-|<B>Flash Frequency</B>|40Mhz|80Mhz|
-|<B>PSRAM enabled</B>|yes|no|
-|<B>Upload Speed</B>|115200|
-|<B>Computer OS</B>|Windows 10|Mac OSX|Ubuntu|
-
-### Description:
-Describe your problem here
-
-
-### Sketch:  (leave the backquotes for [code formatting](https://help.github.com/articles/creating-and-highlighting-code-blocks/))
-```cpp
-
-//Change the code below by your sketch
-#include <Arduino.h>
-
-void setup() {
-}
-
-void loop() {
-}
-```
-
-### Debug Messages:
-```
-Enable Core debug level: Debug on tools menu of Arduino IDE, then put the serial output here 
-```
diff --git a/docs/OTAWebUpdate/OTAWebUpdate.md b/docs/OTAWebUpdate/OTAWebUpdate.md
deleted file mode 100644
index 383f6214433..00000000000
--- a/docs/OTAWebUpdate/OTAWebUpdate.md
+++ /dev/null
@@ -1,59 +0,0 @@
-# Over the Air through Web browser
-OTAWebUpdate is done with a web browser that can be useful in the following typical scenarios:
-- Once the application developed and loading directly from Arduino IDE is inconvenient or not possible
-- after deployment if user is unable to expose Firmware for OTA from external update server
-- provide updates after deployment to small quantity of modules when setting an update server is not practicable
-
-## Requirements
-- The ESP and the computer must be connected to the same network
-
-## Implementation
-The sample implementation has been done using:
-- example sketch OTAWebUpdater.ino
-- ESP32 (Dev Module)
-
-You can use another module also if it meets Flash chip size of the sketch
-
-1-Before you begin, please make sure that you have the following software installed:
- - Arduino IDE
- - Host software depending on O/S you use:
-   - Avahi http://avahi.org/ for Linux
-   - Bonjour http://www.apple.com/support/bonjour/ for Windows
-   - Mac OSX and iOS - support is already built in / no any extra s/w is required
-
-Prepare the sketch and configuration for initial upload with a serial port
-- Start Arduino IDE and load sketch OTAWebUpdater.ino available under File > Examples > OTAWebUpdater.ino
-- Update ssid and pass in the sketch so the module can join your Wi-Fi network
-- Open File > Preferences, look for “Show verbose output during:” and check out “compilation” option
-
-![verbrose](esp32verbose.PNG)
-
-- Upload sketch (Ctrl+U)
-- Now open web browser and enter the url, i.e. http://esp32.local. Once entered, browser should display a form
-
-![login](esp32login.PNG)
-
-> username= admin
-
-> password= admin
-
-**Note**-*If entering “http://ESP32.local” does not work, try replacing “ESP32” with module’s IP address.This workaround is useful in case the host software installed does not work*. 
-
-Now click on Login button and browser will display a upload form
-
-![upload](esp32upload.PNG)
-
-For Uploading the New Firmware you need to provide the Binary File of your Code.
-
-Exporting Binary file of the Firmware (Code)
-- Open up the Arduino IDE
-- Open up the Code, for Exporting up Binary file
-- Now go to Sketch > export compiled Binary
-![export](exportTobinary.PNG)
-
-- Binary file is exported to the same Directory where your code is present
-
-Once you are comfortable with this procedure go ahead and modify OTAWebUpdater.ino sketch to print some additional messages, compile it, Export new binary file and upload it using web browser to see entered changes on a Serial Monitor
-
-
-
diff --git a/docs/arduino-ide/win-screenshots/arduino-ide.png b/docs/_static/arduino-ide.png
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diff --git a/docs/_static/arduino_i2c_master.png b/docs/_static/arduino_i2c_master.png
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diff --git a/docs/_static/arduino_versions.js b/docs/_static/arduino_versions.js
new file mode 100644
index 00000000000..825bc0cbc27
--- /dev/null
+++ b/docs/_static/arduino_versions.js
@@ -0,0 +1,16 @@
+var DOCUMENTATION_VERSIONS = {
+    DEFAULTS: { has_targets: false,
+                supported_targets: [ "esp32" ]
+              },
+    VERSIONS: [
+      { name: "latest", has_targets: true, supported_targets: [ "esp32", "esp32s2", "esp32s3", "esp32c3", "esp32h2", "esp32c6"  ] },
+    ],
+    IDF_TARGETS: [
+       { text: "ESP32", value: "esp32"},
+       { text: "ESP32-S2", value: "esp32s2"},
+       { text: "ESP32-S3", value: "esp32s3"},
+       { text: "ESP32-C3", value: "esp32c3"},
+       { text: "ESP32-H2", value: "esp32h2"},
+       { text: "ESP32-C6", value: "esp32c6"},
+    ]
+};
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diff --git a/docs/_static/webusb.html b/docs/_static/webusb.html
new file mode 100644
index 00000000000..34eb986ba72
--- /dev/null
+++ b/docs/_static/webusb.html
@@ -0,0 +1,128 @@
+<!-- Based on https://github.com/zephyrproject-rtos/zephyr/tree/main/samples/subsys/usb/webusb -->
+
+<!DOCTYPE html>
+<html lang="en">
+  <head>
+    <title>Espressif WebUSB Console Example</title>
+  </head>
+
+<body>
+  <script>
+    var serial = {};
+
+    (function() {
+      'use strict';
+
+      serial.getPorts = function() {
+        return navigator.usb.getDevices().then(devices => {
+          return devices.map(device => new serial.Port(device));
+        });
+      };
+
+      serial.requestPort = function() {
+        const filters = [
+          { 'vendorId': 0x10c4, 'productId': 0xea60 },
+          { 'vendorId': 0x303a, 'productId': 0x1001 },
+          { 'vendorId': 0x303a, 'productId': 0x0002 },
+        ];
+        return navigator.usb.requestDevice({ 'filters': filters }).then(
+          device => new serial.Port(device)
+        );
+      }
+
+      serial.Port = function(device) {
+        this.device_ = device;
+      };
+
+      serial.Port.prototype.connect = function() {
+        let readLoop = () => {
+          const {
+            endpointNumber
+          } = this.device_.configuration.interfaces[0].alternate.endpoints[0]
+          this.device_.transferIn(endpointNumber, 64).then(result => {
+            this.onReceive(result.data);
+            readLoop();
+          }, error => {
+            this.onReceiveError(error);
+          });
+        };
+
+        return this.device_.open()
+            .then(() => {
+              if (this.device_.configuration === null) {
+                return this.device_.selectConfiguration(1);
+              }
+            })
+            .then(() => this.device_.claimInterface(0))
+            .then(() => {
+              readLoop();
+            });
+      };
+
+      serial.Port.prototype.disconnect = function() {
+        return this.device_.close();
+      };
+
+      serial.Port.prototype.send = function(data) {
+        const {
+          endpointNumber
+        } = this.device_.configuration.interfaces[0].alternate.endpoints[1]
+        return this.device_.transferOut(endpointNumber, data);
+      };
+    })();
+
+    let port;
+
+    function connect() {
+      port.connect().then(() => {
+        port.onReceive = data => {
+          let textDecoder = new TextDecoder();
+          console.log("Received:", textDecoder.decode(data));
+          document.getElementById('output').value += textDecoder.decode(data);
+        }
+        port.onReceiveError = error => {
+          console.error(error);
+          document.querySelector("#connect").style = "visibility: initial";
+          port.disconnect();
+        };
+      });
+    }
+
+    function send(string) {
+      console.log("sending to serial:" + string.length);
+      if (string.length === 0)
+        return;
+      console.log("sending to serial: [" + string +"]\n");
+
+      let view = new TextEncoder('utf-8').encode(string);
+      console.log(view);
+      if (port) {
+        port.send(view);
+      }
+    };
+
+    window.onload = _ => {
+      document.querySelector("#connect").onclick = function() {
+        serial.requestPort().then(selectedPort => {
+          port = selectedPort;
+          this.style = "visibility: hidden";
+          connect();
+        });
+      }
+
+      document.querySelector("#submit").onclick = () => {
+        let source = document.querySelector("#input").value;
+        send(source);
+      }
+    }
+  </script>
+
+  <button id="connect" style="visibility: initial">Connect To ESP Device</button>
+  <br><br><label for="input">Sender: </label> <br>
+  <textarea id="input" rows="25" cols="80">Send to ESP Device</textarea>
+  <br><button id="submit">Send</button>
+  <br><br>
+  <label for="output">Receiver: </label> <br>
+  <textarea id="output" rows="25" cols="80"></textarea>
+</body>
+</html>
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diff --git a/docs/arduino-ide/win-screenshots/win-gui-5.png b/docs/_static/win-gui-5.png
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rename to docs/_static/win-gui-5.png
diff --git a/docs/arduino-ide/win-screenshots/win-gui-update-1.png b/docs/_static/win-gui-update-1.png
similarity index 100%
rename from docs/arduino-ide/win-screenshots/win-gui-update-1.png
rename to docs/_static/win-gui-update-1.png
diff --git a/docs/arduino-ide/win-screenshots/win-gui-update-2.png b/docs/_static/win-gui-update-2.png
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rename from docs/arduino-ide/win-screenshots/win-gui-update-2.png
rename to docs/_static/win-gui-update-2.png
diff --git a/docs/arduino-ide/boards_manager.md b/docs/arduino-ide/boards_manager.md
deleted file mode 100644
index c689314fb4c..00000000000
--- a/docs/arduino-ide/boards_manager.md
+++ /dev/null
@@ -1,12 +0,0 @@
-## Installation instructions using Arduino IDE Boards Manager
-### ==========================================================
-
-- Stable release link: `https://raw.githubusercontent.com/espressif/arduino-esp32/gh-pages/package_esp32_index.json`
-- Development release link: `https://raw.githubusercontent.com/espressif/arduino-esp32/gh-pages/package_esp32_dev_index.json`
-
-Starting with 1.6.4, Arduino allows installation of third-party platform packages using Boards Manager. We have packages available for Windows, Mac OS, and Linux (x86, amd64, armhf and arm64).
-
-- Install the current upstream Arduino IDE at the 1.8 level or later. The current version is at the [Arduino website](http://www.arduino.cc/en/main/software).
-- Start Arduino and open Preferences window.
-- Enter one of the release links above into *Additional Board Manager URLs* field. You can add multiple URLs, separating them with commas.
-- Open Boards Manager from Tools > Board menu and install *esp32* platform (and don't forget to select your ESP32 board from Tools > Board menu after installation).
diff --git a/docs/arduino-ide/debian_ubuntu.md b/docs/arduino-ide/debian_ubuntu.md
deleted file mode 100644
index 79149673677..00000000000
--- a/docs/arduino-ide/debian_ubuntu.md
+++ /dev/null
@@ -1,36 +0,0 @@
-Installation instructions for Debian / Ubuntu OS
-=================================================
-
-- Install latest Arduino IDE from [arduino.cc](https://www.arduino.cc/en/Main/Software)
-- Open Terminal and execute the following command (copy->paste and hit enter):
-
-  ```bash
-  sudo usermod -a -G dialout $USER && \
-  sudo apt-get install git && \
-  wget https://bootstrap.pypa.io/get-pip.py && \
-  sudo python get-pip.py && \
-  sudo pip install pyserial && \
-  mkdir -p ~/Arduino/hardware/espressif && \
-  cd ~/Arduino/hardware/espressif && \
-  git clone https://github.com/espressif/arduino-esp32.git esp32 && \
-  cd esp32 && \
-  git submodule update --init --recursive && \
-  cd tools && \
-  python3 get.py
-  ```
-- Restart Arduino IDE
-
-
-
-- If you have Arduino installed to ~/, modify the installation as follows, beginning at `mkdir -p ~/Arduino/hardware`:
-
-  ```bash
-  cd ~/Arduino/hardware
-  mkdir -p espressif && \
-  cd espressif && \
-  git clone https://github.com/espressif/arduino-esp32.git esp32 && \
-  cd esp32 && \
-  git submodule update --init --recursive && \
-  cd tools && \
-  python3 get.py
-  ```
diff --git a/docs/arduino-ide/fedora.md b/docs/arduino-ide/fedora.md
deleted file mode 100644
index c28a2cace5b..00000000000
--- a/docs/arduino-ide/fedora.md
+++ /dev/null
@@ -1,18 +0,0 @@
-Installation instructions for Fedora
-=====================================
-
-- Install the latest Arduino IDE from [arduino.cc](https://www.arduino.cc/en/Main/Software). `$ sudo dnf -y install arduino` will most likely install an older release.
-- Open Terminal and execute the following command (copy->paste and hit enter):
-
-  ```bash
-  sudo usermod -a -G dialout $USER && \
-  sudo dnf install git python3-pip python3-pyserial && \
-  mkdir -p ~/Arduino/hardware/espressif && \
-  cd ~/Arduino/hardware/espressif && \
-  git clone https://github.com/espressif/arduino-esp32.git esp32 && \
-  cd esp32 && \
-  git submodule update --init --recursive && \
-  cd tools && \
-  python get.py
-  ```
-- Restart Arduino IDE
diff --git a/docs/arduino-ide/mac.md b/docs/arduino-ide/mac.md
deleted file mode 100644
index 18553530067..00000000000
--- a/docs/arduino-ide/mac.md
+++ /dev/null
@@ -1,29 +0,0 @@
-Installation instructions for Mac OS
-=====================================
-
-- Install latest Arduino IDE from [arduino.cc](https://www.arduino.cc/en/Main/Software)
-- Open Terminal and execute the following command (copy->paste and hit enter):
-
-  ```bash
-  mkdir -p ~/Documents/Arduino/hardware/espressif && \
-  cd ~/Documents/Arduino/hardware/espressif && \
-  git clone https://github.com/espressif/arduino-esp32.git esp32 --depth 1 && \
-  cd esp32 && \
-  git submodule update --init --recursive --depth 1 && \
-  cd tools && \
-  python get.py 
-  ```
-  Where `~/Documents/Arduino` represents your sketch book location as per "Arduino" > "Preferences" > "Sketchbook location" (in the IDE once started). Adjust the command above accordingly if necessary!
-  
-- If you get the error below. Install the command line dev tools with xcode-select --install and try the command above again:
-  
-  ```xcrun: error: invalid active developer path (/Library/Developer/CommandLineTools), missing xcrun at: /Library/Developer/CommandLineTools/usr/bin/xcrun```
-  
-  ```xcode-select --install```
-  
-- Try `python3` instead of `python` if you get the error: `IOError: [Errno socket error] [SSL: TLSV1_ALERT_PROTOCOL_VERSION] tlsv1 alert protocol version (_ssl.c:590)` when running `python get.py`
-
-- If you get the following error when running `python get.py` urllib.error.URLError: <urlopen error SSL: CERTIFICATE_VERIFY_FAILED, go to Macintosh HD > Applications > Python3.6 folder (or any other python version), and run the following scripts: Install Certificates.command and Update Shell Profile.command
-
-- Restart Arduino IDE
-
diff --git a/docs/arduino-ide/opensuse.md b/docs/arduino-ide/opensuse.md
deleted file mode 100644
index 4f28b9dd346..00000000000
--- a/docs/arduino-ide/opensuse.md
+++ /dev/null
@@ -1,22 +0,0 @@
-Installation instructions for openSUSE
-======================================
-
-- Install the latest Arduino IDE from [arduino.cc](https://www.arduino.cc/en/Main/Software).
-- Open Terminal and execute the following command (copy->paste and hit enter):
-
-  ```bash
-  sudo usermod -a -G dialout $USER && \
-  if [ `python --version 2>&1 | grep '2.7' | wc -l` = "1" ]; then \
-  sudo zypper install git python-pip python-pyserial; \
-  else \
-  sudo zypper install git python3-pip python3-pyserial; \
-  fi && \
-  mkdir -p ~/Arduino/hardware/espressif && \
-  cd ~/Arduino/hardware/espressif && \
-  git clone https://github.com/espressif/arduino-esp32.git esp32 && \
-  cd esp32 && \
-  git submodule update --init --recursive && \
-  cd tools && \
-  python get.py
-  ```
-- Restart Arduino IDE
diff --git a/docs/arduino-ide/windows.md b/docs/arduino-ide/windows.md
deleted file mode 100644
index d98f2b285ab..00000000000
--- a/docs/arduino-ide/windows.md
+++ /dev/null
@@ -1,49 +0,0 @@
-## Steps to install Arduino ESP32 support on Windows
-### Tested on 32 and 64 bit Windows 10 machines
-
-1. Download and install the latest Arduino IDE ```Windows Installer``` from [arduino.cc](https://www.arduino.cc/en/Main/Software)
-2. Download and install Git from [git-scm.com](https://git-scm.com/download/win)
-3. Start ```Git GUI``` and run through the following steps:
-    - Select ```Clone Existing Repository```
-
-        ![Step 1](win-screenshots/win-gui-1.png)
-
-    - Select source and destination
-        - Sketchbook Directory: Usually ```C:/Users/[YOUR_USER_NAME]/Documents/Arduino``` and is listed underneath the "Sketchbook location" in Arduino preferences.
-        - Source Location: ```https://github.com/espressif/arduino-esp32.git```
-        - Target Directory: ```[ARDUINO_SKETCHBOOK_DIR]/hardware/espressif/esp32```
-        - Click ```Clone``` to start cloning the repository
-
-            ![Step 2](win-screenshots/win-gui-2.png)
-            ![Step 3](win-screenshots/win-gui-3.png)
-    - open a `Git Bash` session pointing to ```[ARDUINO_SKETCHBOOK_DIR]/hardware/espressif/esp32``` and execute ```git submodule update --init --recursive``` 
-    - Open ```[ARDUINO_SKETCHBOOK_DIR]/hardware/espressif/esp32/tools``` and double-click ```get.exe```
-
-        ![Step 4](win-screenshots/win-gui-4.png)
-
-    - When ```get.exe``` finishes, you should see the following files in the directory
-
-        ![Step 5](win-screenshots/win-gui-5.png)
-
-4. Plug your ESP32 board and wait for the drivers to install (or install manually any that might be required)
-5. Start Arduino IDE
-6. Select your board in ```Tools > Board``` menu
-7. Select the COM port that the board is attached to
-8. Compile and upload (You might need to hold the boot button while uploading)
-
-    ![Arduino IDE Example](win-screenshots/arduino-ide.png)
-
-### How to update to the latest code
-
-1. Start ```Git GUI``` and you should see the repository under ```Open Recent Repository```. Click on it!
-
-    ![Update Step 1](win-screenshots/win-gui-update-1.png)
-
-2. From menu ```Remote``` select ```Fetch from``` > ```origin```
-
-    ![Update Step 2](win-screenshots/win-gui-update-2.png)
-
-3. Wait for git to pull any changes and close ```Git GUI```
-4. Open ```[ARDUINO_SKETCHBOOK_DIR]/hardware/espressif/esp32/tools``` and double-click ```get.exe```
-
-    ![Step 4](win-screenshots/win-gui-4.png)
diff --git a/docs/conf_common.py b/docs/conf_common.py
new file mode 100644
index 00000000000..676cca899d5
--- /dev/null
+++ b/docs/conf_common.py
@@ -0,0 +1,55 @@
+# ---------------------------------------------------------------
+
+from esp_docs.conf_docs import *  # noqa: F403,F401
+
+languages = ["en"]
+
+# idf_targets = [
+#     "esp32",
+#     "esp32s2",
+#     "esp32s3",
+#     "esp32c3",
+#     "esp32c6",
+#     "esp32h2",
+# ]
+
+# link roles config
+github_repo = "espressif/arduino-esp32"
+
+# context used by sphinx_idf_theme
+html_context["github_user"] = "espressif"  # noqa: F405
+html_context["github_repo"] = "arduino-esp32"  # noqa: F405
+
+html_static_path = ["../_static"]
+
+# Conditional content
+
+extensions += [  # noqa: F405
+    "sphinx_copybutton",
+    "sphinx_tabs.tabs",
+    "esp_docs.esp_extensions.dummy_build_system",
+]
+
+# ESP32_DOCS = [
+#     "index.rst",
+# ]
+
+# ESP32S2_DOCS = ESP32_DOCS
+# ESP32C3_DOCS = ESP32S2_DOCS
+# ESP32S3_DOCS = ESP32S2_DOCS
+# ESP32C6_DOCS = ESP32S2_DOCS
+# ESP32H2_DOCS = ESP32S2_DOCS
+
+# conditional_include_dict = {
+#     "esp32": ESP32_DOCS,
+#     "esp32s2": ESP32S2_DOCS,
+#     "esp32c3": ESP32C3_DOCS,
+#     "esp32s3": ESP32S3_DOCS,
+#     "esp32c6": ESP32C6_DOCS,
+#     "esp32h2": ESP32H2_DOCS,
+# }
+
+# Extra options required by sphinx_idf_theme
+project_slug = "arduino-esp32"
+
+# versions_url = "./../_static/arduino_versions.js"
diff --git a/docs/en/advanced_utils.rst b/docs/en/advanced_utils.rst
new file mode 100644
index 00000000000..a1dbe54d04b
--- /dev/null
+++ b/docs/en/advanced_utils.rst
@@ -0,0 +1,11 @@
+##################
+Advanced Utilities
+##################
+
+.. toctree::
+    :maxdepth: 2
+
+    Library Builder <lib_builder>
+    Arduino as an ESP-IDF component <esp-idf_component>
+    OTA Web Update <ota_web_update>
+    makeEspArduino <make>
diff --git a/docs/en/api/adc.rst b/docs/en/api/adc.rst
new file mode 100644
index 00000000000..434384f8d9b
--- /dev/null
+++ b/docs/en/api/adc.rst
@@ -0,0 +1,281 @@
+###
+ADC
+###
+
+About
+-----
+
+ADC (analog to digital converter) is a very common peripheral used to convert an analog signal such as voltage
+to a digital form so that it can be read and processed by a microcontroller.
+
+ADCs are very useful in control and monitoring applications since most sensors
+(e.g., temperature, pressure, force) produce analog output voltages.
+
+.. note:: Each SoC or module has a different number of ADC's with a different number of channels and pins available. Refer to datasheet of each board for more info.
+
+Arduino-ESP32 ADC API
+---------------------
+
+ADC OneShot mode
+****************
+
+
+The ADC OneShot mode API is fully compatible with Arduino's ``analogRead`` function.
+When you call the ``analogRead`` or ``analogReadMilliVolts`` function, it returns the result of a single conversion on the requested pin.
+
+analogRead
+^^^^^^^^^^
+
+This function is used to get the ADC raw value for a given pin/ADC channel.
+
+.. code-block:: arduino
+
+    uint16_t analogRead(uint8_t pin);
+
+* ``pin`` GPIO pin to read analog value
+
+This function will return analog raw value (non-calibrated).
+
+analogReadMilliVolts
+^^^^^^^^^^^^^^^^^^^^
+
+This function is used to get ADC raw value for a given pin/ADC channel and convert it to calibrated result in millivolts.
+
+.. code-block:: arduino
+
+    uint32_t analogReadMilliVolts(uint8_t pin);
+
+* ``pin`` GPIO pin to read analog value
+
+This function will return analog value in millivolts (calibrated).
+
+analogReadResolution
+^^^^^^^^^^^^^^^^^^^^
+
+This function is used to set the resolution of ``analogRead`` return value. Default is 12 bits (range from 0 to 4095)
+for all chips except ESP32-S3 where default is 13 bits (range from 0 to 8191).
+When different resolution is set, the values read will be shifted to match the given resolution.
+
+Range is 1 - 16 .The default value will be used, if this function is not used.
+
+.. note:: For the ESP32, the resolution is between 9 to12 and it will change the ADC hardware resolution. Else value will be shifted.
+
+.. code-block:: arduino
+
+    void analogReadResolution(uint8_t bits);
+
+* ``bits`` sets analog read resolution
+
+analogSetAttenuation
+^^^^^^^^^^^^^^^^^^^^
+
+This function is used to set the attenuation for all channels.
+
+Input voltages can be attenuated before being input to the ADCs.
+There are 4 available attenuation options, the higher the attenuation is, the higher the measurable input voltage could be.
+
+The measurable input voltage differs for each chip, see table below for detailed information.
+
+.. tabs::
+
+   .. tab:: ESP32
+
+      =====================  ===========================================
+      Attenuation            Measurable input voltage range
+      =====================  ===========================================
+      ``ADC_ATTEN_DB_0``     100 mV ~ 950 mV
+      ``ADC_ATTEN_DB_2_5``   100 mV ~ 1250 mV
+      ``ADC_ATTEN_DB_6``     150 mV ~ 1750 mV
+      ``ADC_ATTEN_DB_11``    150 mV ~ 3100 mV
+      =====================  ===========================================
+
+   .. tab:: ESP32-S2
+
+      =====================  ===========================================
+      Attenuation            Measurable input voltage range
+      =====================  ===========================================
+      ``ADC_ATTEN_DB_0``     0 mV ~ 750 mV
+      ``ADC_ATTEN_DB_2_5``   0 mV ~ 1050 mV
+      ``ADC_ATTEN_DB_6``     0 mV ~ 1300 mV
+      ``ADC_ATTEN_DB_11``    0 mV ~ 2500 mV
+      =====================  ===========================================
+
+   .. tab:: ESP32-C3
+
+      =====================  ===========================================
+      Attenuation            Measurable input voltage range
+      =====================  ===========================================
+      ``ADC_ATTEN_DB_0``     0 mV ~ 750 mV
+      ``ADC_ATTEN_DB_2_5``   0 mV ~ 1050 mV
+      ``ADC_ATTEN_DB_6``     0 mV ~ 1300 mV
+      ``ADC_ATTEN_DB_11``    0 mV ~ 2500 mV
+      =====================  ===========================================
+
+   .. tab:: ESP32-S3
+
+      =====================  ===========================================
+      Attenuation            Measurable input voltage range
+      =====================  ===========================================
+      ``ADC_ATTEN_DB_0``     0 mV ~ 950 mV
+      ``ADC_ATTEN_DB_2_5``   0 mV ~ 1250 mV
+      ``ADC_ATTEN_DB_6``     0 mV ~ 1750 mV
+      ``ADC_ATTEN_DB_11``    0 mV ~ 3100 mV
+      =====================  ===========================================
+
+.. code-block:: arduino
+
+    void analogSetAttenuation(adc_attenuation_t attenuation);
+
+* ``attenuation`` sets the attenuation.
+
+analogSetPinAttenuation
+^^^^^^^^^^^^^^^^^^^^^^^
+
+This function is used to set the attenuation for a specific pin/ADC channel. For more information refer to `analogSetAttenuation`_.
+
+.. code-block:: arduino
+
+    void analogSetPinAttenuation(uint8_t pin, adc_attenuation_t attenuation);
+
+* ``pin`` selects specific pin for attenuation settings.
+* ``attenuation`` sets the attenuation.
+
+analogSetWidth
+^^^^^^^^^^^^^^
+
+.. note:: This function is only available for ESP32 chip.
+
+This function is used to set the hardware sample bits and read resolution.
+Default is 12 bits (0 - 4095).
+Range is 9 - 12.
+
+.. code-block:: arduino
+
+    void analogSetWidth(uint8_t bits);
+
+ADC Continuous mode
+*******************
+
+ADC Continuous mode is an API designed for performing analog conversions on multiple pins in the background,
+with the feature of receiving a callback upon completion of these conversions to access the results.
+
+This API allows you to specify the desired number of conversions per pin within a single cycle, along with its corresponding sampling rate.
+The outcome of the ``analogContinuousRead`` function is an array of ``adc_continuous_data_t`` structures.
+These structures hold both the raw average value and the average value in millivolts for each pin.
+
+analogContinuous
+^^^^^^^^^^^^^^^^
+
+This function is used to configure ADC continuous peripheral on selected pins.
+
+.. code-block:: arduino
+
+    bool analogContinuous(const uint8_t pins[], size_t pins_count, uint32_t conversions_per_pin, uint32_t sampling_freq_hz, void (*userFunc)(void));
+
+* ``pins[]`` array of pins to be set up
+* ``pins_count`` count of pins in array
+* ``conversions_per_pin`` sets how many conversions per pin will run each ADC cycle
+* ``sampling_freq_hz`` sets sampling frequency of ADC in Hz
+* ``userFunc`` sets callback function to be called after adc conversion is done (can be set to ``NULL``)
+
+This function will return ``true`` if configuration is successful.
+If ``false`` is returned, error occurs and ADC continuous was not configured.
+
+analogContinuousRead
+^^^^^^^^^^^^^^^^^^^^
+
+This function is used to read ADC continuous data to the result buffer. The result buffer is an array of ``adc_continuous_data_t``.
+
+.. code-block:: arduino
+
+    typedef struct {
+        uint8_t pin;           /*!<ADC pin */
+        uint8_t channel;       /*!<ADC channel */
+        int avg_read_raw;      /*!<ADC average raw data */
+        int avg_read_mvolts;   /*!<ADC average voltage in mV */
+    } adc_continuous_data_t;
+
+.. code-block:: arduino
+
+    bool analogContinuousRead(adc_continuous_data_t ** buffer, uint32_t timeout_ms);
+
+* ``buffer`` conversion result buffer to read from ADC in adc_continuous_data_t format.
+* ``timeout_ms`` time to wait for data in milliseconds.
+
+This function will return ``true`` if reading is successful and ``buffer`` is filled with data.
+If ``false`` is returned, reading has failed and ``buffer`` is set to NULL.
+
+analogContinuousStart
+^^^^^^^^^^^^^^^^^^^^^
+
+This function is used to start ADC continuous conversions.
+
+.. code-block:: arduino
+
+    bool analogContinuousStart();
+
+This function will return ``true`` if ADC continuous is successfully started.
+If ``false`` is returned, starting ADC continuous has failed.
+
+analogContinuousStop
+^^^^^^^^^^^^^^^^^^^^
+
+This function is used to stop ADC continuous conversions.
+
+.. code-block:: arduino
+
+    bool analogContinuousStop();
+
+This function will return ``true`` if ADC continuous is successfully stopped.
+If ``false`` is returned, stopping ADC continuous has failed.
+
+analogContinuousDeinit
+^^^^^^^^^^^^^^^^^^^^^^
+
+This function is used to deinitialize ADC continuous peripheral.
+
+.. code-block:: arduino
+
+    bool analogContinuousDeinit();
+
+This function will return ``true`` if ADC continuous is successfully deinitialized.
+If ``false`` is returned, deinitilization of ADC continuous has failed.
+
+analogContinuousSetAtten
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+This function is used to set the attenuation for ADC continuous peripheral. For more information refer to `analogSetAttenuation`_.
+
+.. code-block:: arduino
+
+    void analogContinuousSetAtten(adc_attenuation_t attenuation);
+
+* ``attenuation`` sets the attenuation (default is 11 dB).
+
+analogContinuousSetWidth
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+This function is used to set the hardware resolution bits.
+Default value for all chips is 12 bits (0 - 4095).
+
+.. note:: This function will take effect only for ESP32 chip, as it allows to set resolution in range 9-12 bits.
+
+.. code-block:: arduino
+
+    void analogContinuousSetWidth(uint8_t bits);
+
+* ``bits`` sets resolution bits.
+
+
+Example Applications
+********************
+
+Here is an example of how to use the ADC in OneShot mode or you can run Arduino example 01.Basics -> AnalogReadSerial.
+
+.. literalinclude:: ../../../libraries/ESP32/examples/AnalogRead/AnalogRead.ino
+    :language: arduino
+
+Here is an example of how to use the ADC in Continuous mode.
+
+.. literalinclude:: ../../../libraries/ESP32/examples/AnalogReadContinuous/AnalogReadContinuous.ino
+    :language: arduino
diff --git a/docs/en/api/ble.rst b/docs/en/api/ble.rst
new file mode 100644
index 00000000000..8a994605312
--- /dev/null
+++ b/docs/en/api/ble.rst
@@ -0,0 +1,27 @@
+###
+BLE
+###
+
+About
+-----
+
+.. note:: This is a work in progress project and this section is still missing. If you want to contribute, please see the `Contributions Guide <../contributing.html>`_.
+
+Examples
+--------
+
+To get started with BLE, you can try:
+
+BLE Scan
+********
+
+.. literalinclude:: ../../../libraries/BLE/examples/Scan/Scan.ino
+    :language: arduino
+
+BLE UART
+********
+
+.. literalinclude:: ../../../libraries/BLE/examples/UART/UART.ino
+    :language: arduino
+
+Complete list of `BLE examples <https://github.com/espressif/arduino-esp32/tree/master/libraries/BLE/examples>`_.
diff --git a/docs/en/api/bluetooth.rst b/docs/en/api/bluetooth.rst
new file mode 100644
index 00000000000..ebabfca5a9e
--- /dev/null
+++ b/docs/en/api/bluetooth.rst
@@ -0,0 +1,27 @@
+#########
+Bluetooth
+#########
+
+About
+-----
+
+.. note:: This is a work in progress project and this section is still missing. If you want to contribute, please see the `Contributions Guide <../contributing.html>`_.
+
+Examples
+--------
+
+To get started with Bluetooth, you can try:
+
+Serial To Serial BT
+*******************
+
+.. literalinclude:: ../../../libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino
+    :language: arduino
+
+BT Classic Device Discovery
+***************************
+
+.. literalinclude:: ../../../libraries/BluetoothSerial/examples/bt_classic_device_discovery/bt_classic_device_discovery.ino
+    :language: arduino
+
+Complete list of `Bluetooth examples <https://github.com/espressif/arduino-esp32/tree/master/libraries/BluetoothSerial/examples>`_.
diff --git a/docs/en/api/dac.rst b/docs/en/api/dac.rst
new file mode 100644
index 00000000000..96939be96f3
--- /dev/null
+++ b/docs/en/api/dac.rst
@@ -0,0 +1,47 @@
+###
+DAC
+###
+
+About
+-----
+
+DAC (digital to analog converter) is a very common peripheral used to convert a digital signal to an
+analog form.
+
+ESP32 and ESP32-S2 have two 8-bit DAC channels. The DAC driver allows these channels to be set to arbitrary voltages.
+
+DACs can be used for generating a specific (and dynamic) reference voltage for external sensors,
+controlling transistors, etc.
+
+========= ========= =========
+ESP32 SoC DAC_1 pin DAC_2 pin
+========= ========= =========
+ESP32     GPIO 25   GPIO 26
+ESP32-S2  GPIO 17   GPIO 18
+========= ========= =========
+
+Arduino-ESP32 DAC API
+---------------------
+
+dacWrite
+********
+
+This function is used to set the DAC value for a given pin/DAC channel.
+
+.. code-block:: arduino
+
+    void dacWrite(uint8_t pin, uint8_t value);
+
+* ``pin`` GPIO pin.
+* ``value`` to be set. Range is 0 - 255 (equals 0 V - 3.3 V).
+
+dacDisable
+**********
+
+This function is used to disable DAC output on a given pin/DAC channel.
+
+.. code-block:: arduino
+
+    void dacDisable(uint8_t pin);
+
+* ``pin`` GPIO pin.
diff --git a/docs/en/api/deepsleep.rst b/docs/en/api/deepsleep.rst
new file mode 100644
index 00000000000..6c06f8fc628
--- /dev/null
+++ b/docs/en/api/deepsleep.rst
@@ -0,0 +1,25 @@
+##########
+Deep Sleep
+##########
+
+About
+-----
+
+.. note:: This is a work in progress project and this section is still missing. If you want to contribute, please see the `Contributions Guide <../contributing.html>`_.
+
+Examples
+--------
+
+To get started with Hall sensor, you can try:
+
+ExternalWakeUp
+**************
+
+.. literalinclude:: ../../../libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ExternalWakeUp.ino
+    :language: arduino
+
+Timer Wake Up
+*************
+
+.. literalinclude:: ../../../libraries/ESP32/examples/DeepSleep/TimerWakeUp/TimerWakeUp.ino
+    :language: arduino
diff --git a/docs/en/api/espnow.rst b/docs/en/api/espnow.rst
new file mode 100644
index 00000000000..585c2e3f53e
--- /dev/null
+++ b/docs/en/api/espnow.rst
@@ -0,0 +1,276 @@
+#######
+ESP-NOW
+#######
+
+About
+-----
+
+ESP-NOW is a communication protocol designed for low-power, low-latency, and high-throughput communication between ESP32 devices without the need for an access point (AP).
+It is ideal for scenarios where devices need to communicate directly with each other in a local network.
+ESP-NOW can be used for smart lights, remote control devices, sensors and many other applications.
+
+This library provides an easy-to-use interface for setting up ESP-NOW communication, adding and removing peers, and sending and receiving data packets.
+
+Arduino-ESP32 ESP-NOW API
+-------------------------
+
+ESP-NOW Class
+*************
+
+The `ESP_NOW_Class` is the main class used for managing ESP-NOW communication.
+
+begin
+^^^^^
+
+Initialize the ESP-NOW communication. This function must be called before using any other ESP-NOW functionalities.
+
+.. code-block:: cpp
+
+    bool begin(const uint8_t *pmk = NULL);
+
+* ``pmk``: Optional. Pass the pairwise master key (PMK) if encryption is enabled.
+
+Returns ``true`` if initialization is successful, ``false`` otherwise.
+
+end
+^^^
+
+End the ESP-NOW communication. This function releases all resources used by the ESP-NOW library.
+
+.. code-block:: cpp
+
+    bool end();
+
+Returns ``true`` if the operation is successful, ``false`` otherwise.
+
+getTotalPeerCount
+^^^^^^^^^^^^^^^^^
+
+Get the total number of peers currently added.
+
+.. code-block:: cpp
+
+    int getTotalPeerCount();
+
+Returns the total number of peers, or ``-1`` if an error occurs.
+
+getEncryptedPeerCount
+^^^^^^^^^^^^^^^^^^^^^
+
+Get the number of peers using encryption.
+
+.. code-block:: cpp
+
+    int getEncryptedPeerCount();
+
+Returns the number of peers using encryption, or ``-1`` if an error occurs.
+
+onNewPeer
+^^^^^^^^^
+
+You can register a callback function to handle incoming data from new peers using the `onNewPeer` function.
+
+.. code-block:: cpp
+
+    void onNewPeer(void (*cb)(const esp_now_recv_info_t *info, const uint8_t *data, int len, void *arg), void *arg);
+
+* ``cb``: Pointer to the callback function.
+* ``arg``: Optional. Pointer to user-defined argument to be passed to the callback function.
+
+``cb`` function signature:
+
+.. code-block:: cpp
+
+    void cb(const esp_now_recv_info_t *info, const uint8_t *data, int len, void *arg);
+
+``info``: Information about the received packet.
+``data``: Pointer to the received data.
+``len``: Length of the received data.
+``arg``: User-defined argument passed to the callback function.
+
+ESP-NOW Peer Class
+******************
+
+The `ESP_NOW_Peer` class represents a peer device in the ESP-NOW network. It is an abstract class that must be inherited by a child class that properly handles the peer connections and implements the `_onReceive` and `_onSent` methods.
+
+Constructor
+^^^^^^^^^^^
+
+Create an instance of the `ESP_NOW_Peer` class.
+
+.. code-block:: cpp
+
+    ESP_NOW_Peer(const uint8_t *mac_addr, uint8_t channel, wifi_interface_t iface, const uint8_t *lmk);
+
+* ``mac_addr``: MAC address of the peer device.
+* ``channel``: Communication channel.
+* ``iface``: Wi-Fi interface.
+* ``lmk``: Optional. Pass the local master key (LMK) if encryption is enabled.
+
+add
+^^^
+
+Add the peer to the ESP-NOW network.
+
+.. code-block:: cpp
+
+    bool add();
+
+Returns ``true`` if the peer is added successfully, ``false`` otherwise.
+
+remove
+^^^^^^
+
+Remove the peer from the ESP-NOW network.
+
+.. code-block:: cpp
+
+    bool remove();
+
+Returns ``true`` if the peer is removed successfully, ``false`` otherwise.
+
+send
+^^^^
+
+Send data to the peer.
+
+.. code-block:: cpp
+
+    size_t send(const uint8_t *data, int len);
+
+* ``data``: Pointer to the data to be sent.
+* ``len``: Length of the data in bytes.
+
+Returns the number of bytes sent, or ``0`` if an error occurs.
+
+addr
+^^^^
+
+Get the MAC address of the peer.
+
+.. code-block:: cpp
+
+    const uint8_t * addr() const;
+
+Returns a pointer to the MAC address.
+
+addr
+^^^^
+
+Set the MAC address of the peer.
+
+.. code-block:: cpp
+
+    void addr(const uint8_t *mac_addr);
+
+* ``mac_addr``: MAC address of the peer.
+
+getChannel
+^^^^^^^^^^
+
+Get the communication channel of the peer.
+
+.. code-block:: cpp
+
+    uint8_t getChannel() const;
+
+Returns the communication channel.
+
+setChannel
+^^^^^^^^^^
+
+Set the communication channel of the peer.
+
+.. code-block:: cpp
+
+    void setChannel(uint8_t channel);
+
+* ``channel``: Communication channel.
+
+getInterface
+^^^^^^^^^^^^
+
+Get the Wi-Fi interface of the peer.
+
+.. code-block:: cpp
+
+    wifi_interface_t getInterface() const;
+
+Returns the Wi-Fi interface.
+
+setInterface
+^^^^^^^^^^^^
+
+Set the Wi-Fi interface of the peer.
+
+.. code-block:: cpp
+
+    void setInterface(wifi_interface_t iface);
+
+* ``iface``: Wi-Fi interface.
+
+isEncrypted
+^^^^^^^^^^^
+
+Check if the peer is using encryption.
+
+.. code-block:: cpp
+
+    bool isEncrypted() const;
+
+Returns ``true`` if the peer is using encryption, ``false`` otherwise.
+
+setKey
+^^^^^^
+
+Set the local master key (LMK) for the peer.
+
+.. code-block:: cpp
+
+    void setKey(const uint8_t *lmk);
+
+* ``lmk``: Local master key.
+
+onReceive
+^^^^^^^^^^
+
+Callback function to handle incoming data from the peer. This is a virtual method can be implemented by the upper class for custom handling.
+
+.. code-block:: cpp
+
+    void onReceive(const uint8_t *data, int len, bool broadcast);
+
+* ``data``: Pointer to the received data.
+* ``len``: Length of the received data.
+* ``broadcast``: ``true`` if the data is broadcasted, ``false`` otherwise.
+
+onSent
+^^^^^^^
+
+Callback function to handle the completion of sending data to the peer. This is a virtual method can be implemented by the upper class for custom handling.
+
+.. code-block:: cpp
+
+    void onSent(bool success);
+
+* ``success``: ``true`` if the data is sent successfully, ``false`` otherwise.
+
+Examples
+--------
+
+Set of 2 examples of the ESP-NOW library to send and receive data using broadcast messages between multiple ESP32 devices (multiple masters, multiple slaves).
+
+1. ESP-NOW Broadcast Master Example:
+
+.. literalinclude:: ../../../libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Master/ESP_NOW_Broadcast_Master.ino
+    :language: cpp
+
+2. ESP-NOW Broadcast Slave Example:
+
+.. literalinclude:: ../../../libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Slave/ESP_NOW_Broadcast_Slave.ino
+    :language: cpp
+
+Example of the ESP-NOW Serial library to send and receive data as a stream between 2 ESP32 devices using the serial monitor:
+
+.. literalinclude:: ../../../libraries/ESP_NOW/examples/ESP_NOW_Serial/ESP_NOW_Serial.ino
+    :language: cpp
diff --git a/docs/en/api/ethernet.rst b/docs/en/api/ethernet.rst
new file mode 100644
index 00000000000..ad4297e6668
--- /dev/null
+++ b/docs/en/api/ethernet.rst
@@ -0,0 +1,27 @@
+########
+Ethernet
+########
+
+About
+-----
+
+.. note:: This is a work in progress project and this section is still missing. If you want to contribute, please see the `Contributions Guide <../contributing.html>`_.
+
+Examples
+--------
+
+To get started with Ethernet, you can try:
+
+LAN8720
+*******
+
+.. literalinclude:: ../../../libraries/Ethernet/examples/ETH_LAN8720/ETH_LAN8720.ino
+    :language: arduino
+
+TLK110
+******
+
+.. literalinclude:: ../../../libraries/Ethernet/examples/ETH_TLK110/ETH_TLK110.ino
+    :language: arduino
+
+Complete list of `Ethernet examples <https://github.com/espressif/arduino-esp32/tree/master/libraries/Ethernet/examples>`_.
diff --git a/docs/en/api/gpio.rst b/docs/en/api/gpio.rst
new file mode 100644
index 00000000000..ebf31088ffd
--- /dev/null
+++ b/docs/en/api/gpio.rst
@@ -0,0 +1,170 @@
+####
+GPIO
+####
+
+About
+-----
+
+One of the most used and versatile peripheral in a microcontroller is the GPIO. The GPIO is commonly used to write and read the pin state.
+
+GPIO stands to General Purpose Input Output, and is responsible to control or read the state of a specific pin in the digital world. For example, this peripheral is widely used to create the LED blinking or to read a simple button.
+
+.. note:: There are some GPIOs with special restrictions, and not all GPIOs are accessible through the development board. For more information about it, see the corresponding board pin layout information.
+
+GPIOs Modes
+***********
+
+There are two different modes in the GPIO configuration:
+
+- **Input Mode**
+
+In this mode, the GPIO will receive the digital state from a specific device. This device could be a button or a switch.
+
+- **Output Mode**
+
+For the output mode, the GPIO will change the GPIO digital state to a specific device. You can drive an LED for example.
+
+GPIO API
+--------
+
+Here is the common functions used for the GPIO peripheral.
+
+pinMode
+*******
+
+The ``pinMode`` function is used to define the GPIO operation mode for a specific pin.
+
+.. code-block:: arduino
+
+    void pinMode(uint8_t pin, uint8_t mode);
+
+* ``pin``   defines the GPIO pin number.
+* ``mode``  sets operation mode.
+
+The following modes are supported for the basic `input` and `output`:
+
+* **INPUT** sets the GPIO as input without pullup or pulldown (high impedance).
+* **OUTPUT** sets the GPIO as output/read mode.
+* **INPUT_PULLDOWN** sets the GPIO as input with the internal pulldown.
+* **INPUT_PULLUP** sets the GPIO as input with the internal pullup.
+
+Internal Pullup and Pulldown
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The ESP32 SoC families supports the internal pullup and pulldown through a 45kR resistor, that can be enabled when configuring the GPIO mode as ``INPUT`` mode.
+If the pullup or pulldown mode is not defined, the pin will stay in the high impedance mode.
+
+digitalWrite
+*************
+
+The function ``digitalWrite`` sets the state of the selected GPIO to ``HIGH`` or ``LOW``. This function is only used if the ``pinMode`` was configured as ``OUTPUT``.
+
+.. code-block:: arduino
+
+    void digitalWrite(uint8_t pin, uint8_t val);
+
+* ``pin``  defines the GPIO pin number.
+* ``val``  set the output digital state to ``HIGH`` or ``LOW``.
+
+digitalRead
+***********
+
+To read the state of a given pin configured as ``INPUT``, the function ``digitalRead`` is used.
+
+.. code-block:: arduino
+
+    int digitalRead(uint8_t pin);
+
+* ``pin`` select GPIO
+
+This function will return the logical state of the selected pin as ``HIGH`` or ``LOW``.
+
+Interrupts
+----------
+
+The GPIO peripheral on the ESP32 supports interruptions.
+
+attachInterrupt
+***************
+
+The function ``attachInterrupt`` is used to attach the interrupt to the defined pin.
+
+.. code-block:: arduino
+
+  attachInterrupt(uint8_t pin, voidFuncPtr handler, int mode);
+
+* ``pin``  defines the GPIO pin number.
+* ``handler``  set the handler function.
+* ``mode``  set the interrupt mode.
+
+Here are the supported interrupt modes:
+
+* **DISABLED**
+* **RISING**
+* **FALLING**
+* **CHANGE**
+* **ONLOW**
+* **ONHIGH**
+* **ONLOW_WE**
+* **ONHIGH_WE**
+
+attachInterruptArg
+******************
+
+The function ``attachInterruptArg`` is used to attach the interrupt to the defined pin using arguments.
+
+.. code-block:: arduino
+
+  attachInterruptArg(uint8_t pin, voidFuncPtrArg handler, void * arg, int mode);
+
+* ``pin``  defines the GPIO pin number.
+* ``handler``  set the handler function.
+* ``arg`` pointer to the interrupt arguments.
+* ``mode``  set the interrupt mode.
+
+detachInterrupt
+***************
+
+To detach the interruption from a specific pin, use the ``detachInterrupt`` function giving the GPIO to be detached.
+
+.. code-block:: arduino
+
+  detachInterrupt(uint8_t pin);
+
+* ``pin``  defines the GPIO pin number.
+
+.. _gpio_example_code:
+
+Example Code
+------------
+
+GPIO Input and Output Modes
+***************************
+
+.. code-block:: arduino
+
+  #define LED    12
+  #define BUTTON 2
+
+  uint8_t stateLED = 0;
+
+    void setup() {
+        pinMode(LED, OUTPUT);
+        pinMode(BUTTON,INPUT_PULLUP);
+    }
+
+    void loop() {
+
+       if(!digitalRead(BUTTON)){
+         stateLED = stateLED^1;
+        digitalWrite(LED,stateLED);
+      }
+    }
+
+GPIO Interrupt
+**************
+
+.. literalinclude:: ../../../libraries/ESP32/examples/GPIO/GPIOInterrupt/GPIOInterrupt.ino
+    :language: arduino
+
+.. _datasheet: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf
diff --git a/docs/en/api/i2c.rst b/docs/en/api/i2c.rst
new file mode 100644
index 00000000000..eac04b76a23
--- /dev/null
+++ b/docs/en/api/i2c.rst
@@ -0,0 +1,384 @@
+###
+I2C
+###
+
+About
+-----
+
+I2C (Inter-Integrated Circuit) / TWI (Two-wire Interface) is a widely used serial communication to connect devices in a short distance. This is one of the most common peripherals used to connect sensors, EEPROMs, RTC, ADC, DAC, displays, OLED, and many other devices and microcontrollers.
+
+This serial communication is considered as a low-speed bus, and multiple devices can be connected on the same two-wires bus, each with a unique 7-bits address (up to 128 devices). These two wires are called SDA (serial data line) and SCL (serial clock line).
+
+.. note:: The SDA and SCL lines require pull-up resistors. See the device datasheet for more details about the resistors' values and the operating voltage.
+
+I2C Modes
+*********
+
+The I2C can be used in two different modes:
+
+* **I2C Master Mode**
+    * In this mode, the ESP32 generates the clock signal and initiates the communication with the slave device.
+
+.. figure:: ../../_static/arduino_i2c_master.png
+    :align: center
+    :width: 720
+    :figclass: align-center
+
+* **I2C Slave Mode**
+    * The slave mode, the clock is generated by the master device and responds to the master if the destination address is the same as the destination.
+
+.. figure:: ../../_static/arduino_i2c_slave.png
+    :align: center
+    :width: 520
+    :figclass: align-center
+
+Arduino-ESP32 I2C API
+---------------------
+
+The ESP32 I2C library is based on the `Arduino Wire Library`_ and implements a few more APIs, described in this documentation.
+
+I2C Common API
+**************
+
+Here are the common functions used for master and slave modes.
+
+begin
+^^^^^
+
+This function is used to start the peripheral using the default configuration.
+
+.. code-block:: arduino
+
+    bool begin();
+
+This function will return ``true`` if the peripheral was initialized correctly.
+
+setPins
+^^^^^^^
+
+This function is used to define the ``SDA`` and ``SCL`` pins.
+
+.. note:: Call this function before ``begin`` to change the pins from the default ones.
+
+.. code-block:: arduino
+
+    bool setPins(int sdaPin, int sclPin);
+
+* ``sdaPin`` sets the GPIO to be used as the I2C peripheral data line.
+
+* ``sclPin`` sets the GPIO to be used as the I2C peripheral clock line.
+
+The default pins may vary from board to board. On the *Generic ESP32* the default I2C pins are:
+
+* ``sdaPin`` **GPIO21**
+
+* ``sclPin`` **GPIO22**
+
+This function will return ``true`` if the peripheral was configured correctly.
+
+setClock
+^^^^^^^^
+
+Use this function to set the bus clock. The default value will be used if this function is not used.
+
+.. code-block:: arduino
+
+    bool setClock(uint32_t frequency);
+
+* ``frequency`` sets the bus frequency clock.
+
+This function will return ``true`` if the clock was configured correctly.
+
+getClock
+^^^^^^^^
+
+Use this function to get the bus clock.
+
+.. code-block:: arduino
+
+    uint32_t getClock();
+
+This function will return the current frequency configuration.
+
+setTimeOut
+^^^^^^^^^^
+
+Set the bus timeout given in milliseconds. The default value is 50 ms.
+
+.. code-block:: arduino
+
+    void setTimeOut(uint16_t timeOutMillis);
+
+* ``timeOutMillis`` sets the timeout in ms.
+
+getTimeOut
+^^^^^^^^^^
+
+Get the bus timeout in milliseconds.
+
+.. code-block:: arduino
+
+    uint16_t getTimeOut();
+
+This function will return the current timeout configuration.
+
+.. _i2c write:
+
+write
+^^^^^
+
+This function writes data to the buffer.
+
+.. code-block:: arduino
+
+    size_t write(uint8_t);
+
+or
+
+.. code-block:: arduino
+
+    size_t write(const uint8_t *, size_t);
+
+The return will be the size of the data added to the buffer.
+
+.. _i2c end:
+
+end
+^^^
+
+This function will finish the communication and release all the allocated resources. After calling ``end`` you need to use ``begin`` again in order to initialize the I2C driver again.
+
+.. code-block:: arduino
+
+    bool end();
+
+
+I2C Master Mode
+***************
+
+This mode is used to initiate communication to the slave.
+
+Basic Usage
+^^^^^^^^^^^
+
+To start using I2C master mode on the Arduino, the first step is to include the ``Wire.h`` header to the sketch.
+
+.. code-block:: arduino
+
+    #include "Wire.h"
+
+Now, we can start the peripheral configuration by calling ``begin`` function.
+
+.. code-block:: arduino
+
+    Wire.begin();
+
+By using ``begin`` without any arguments, all the settings will be done by using the default values. To set the values by your own, see the function description. This function is described here: `i2c begin`_
+
+After calling ``begin``, we can start the transmission by calling ``beginTransmission`` and passing the I2C slave address:
+
+.. code-block:: arduino
+
+    Wire.beginTransmission(I2C_DEV_ADDR);
+
+To write some bytes to the slave, use the ``write`` function.
+
+.. code-block:: arduino
+
+    Wire.write(x);
+
+You can pass different data types using ``write`` function. This function is described here: `i2c write`_
+
+.. note:: The ``write`` function does not write directly to the slave device but adds to the I2C buffer. To do so, you need to use the ``endTransmission`` function to send the buffered bytes to the slave device.
+
+.. code-block:: arduino
+
+    Wire.endTransmission(true);
+
+After calling ``endTransmission``, the data stored in the I2C buffer will be transmitted to the slave device.
+
+Now you can request a reading from the slave device. The ``requestFrom`` will ask for a readout to the selected device by giving the address and the size.
+
+.. code-block:: arduino
+
+    Wire.requestFrom(I2C_DEV_ADDR, SIZE);
+
+and the ``readBytes`` will read it.
+
+.. code-block:: arduino
+
+    Wire.readBytes(temp, error);
+
+.. _i2c begin:
+
+I2C Master APIs
+***************
+
+Here are the I2C master APIs. These function are intended to be used only for master mode.
+
+begin
+^^^^^
+
+In master mode, the ``begin`` function can be used by passing the **pins** and **bus frequency**. Use this function only for the master mode.
+
+.. code-block:: arduino
+
+    bool begin(int sdaPin, int sclPin, uint32_t frequency)
+
+Alternatively, you can use the ``begin`` function without any argument to use all default values.
+
+This function will return ``true`` if the peripheral was initialized correctly.
+
+beginTransmission
+^^^^^^^^^^^^^^^^^
+
+This function is used to star a communication process with the slave device. Call this function by passing the slave ``address`` before writing the message to the buffer.
+
+.. code-block:: arduino
+
+    void beginTransmission(uint16_t address)
+
+endTransmission
+^^^^^^^^^^^^^^^
+
+After writing to the buffer using `i2c write`_, use the function ``endTransmission`` to send the message to the slave device address defined on the ``beginTransmission`` function.
+
+.. code-block:: arduino
+
+    uint8_t endTransmission(bool sendStop);
+
+* ``sendStop`` enables **(true)** or disables **(false)** the stop signal *(only used in master mode)*.
+
+Calling the this function without ``sendStop`` is equivalent to ``sendStop = true``.
+
+.. code-block:: arduino
+
+    uint8_t endTransmission(void);
+
+This function will return the error code.
+
+requestFrom
+^^^^^^^^^^^
+
+To read from the slave device, use the ``requestFrom`` function.
+
+.. code-block:: arduino
+
+    uint8_t requestFrom(uint16_t address, uint8_t size, bool sendStop)
+
+* ``address`` set the device address.
+
+* ``size`` define the size to be requested.
+
+* ``sendStop`` enables (true) or disables (false) the stop signal.
+
+This function will return the number of bytes read from the device.
+
+Example Application - WireMaster.ino
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Here is an example of how to use the I2C in Master Mode.
+
+.. literalinclude:: ../../../libraries/Wire/examples/WireMaster/WireMaster.ino
+    :language: arduino
+
+
+I2C Slave Mode
+**************
+
+This mode is used to accept communication from the master.
+
+Basic Usage
+^^^^^^^^^^^
+
+To start using I2C as slave mode on the Arduino, the first step is to include the ``Wire.h`` header to the sketch.
+
+.. code-block:: arduino
+
+    #include "Wire.h"
+
+Before calling ``begin`` we must create two callback functions to handle the communication with the master device.
+
+.. code-block:: arduino
+
+    Wire.onReceive(onReceive);
+
+and
+
+.. code-block:: arduino
+
+    Wire.onRequest(onRequest);
+
+The ``onReceive`` will handle the request from the master device upon a slave read request and the ``onRequest`` will handle the answer to the master.
+
+Now, we can start the peripheral configuration by calling ``begin`` function with the device address.
+
+.. code-block:: arduino
+
+    Wire.begin((uint8_t)I2C_DEV_ADDR);
+
+By using ``begin`` without any arguments, all the settings will be done by using the default values. To set the values by your own, see the function description. This function is described here: `i2c begin`_
+
+
+**For ESP32 only!**
+
+Use the function ``slaveWrite`` in order to pre-write to the slave response buffer. This is used only for the ESP32 in order to add the slave capability on the chip and keep compatibility with Arduino.
+
+.. code-block:: arduino
+
+    Wire.slaveWrite((uint8_t *)message, strlen(message));
+
+I2C Slave APIs
+**************
+
+Here are the I2C slave APIs. These function are intended to be used only for slave mode.
+
+begin
+^^^^^
+
+In slave mode, the ``begin`` function must be used by passing the **slave address**. You can also define the **pins** and the **bus frequency**.
+
+.. code-block:: arduino
+
+    bool Wire.begin(uint8_t addr, int sdaPin, int sclPin, uint32_t frequency)
+
+This function will return ``true`` if the peripheral was initialized correctly.
+
+onReceive
+^^^^^^^^^
+
+The ``onReceive`` function is used to define the callback for the data received from the master.
+
+.. code-block:: arduino
+
+    void onReceive( void (*)(int) );
+
+onRequest
+^^^^^^^^^
+
+The ``onRequest`` function is used to define the callback for the data to be send to the master.
+
+.. code-block:: arduino
+
+    void onRequest( void (*)(void) );
+
+slaveWrite
+^^^^^^^^^^
+
+The ``slaveWrite`` function writes on the slave response buffer before receiving the response message. This function is only used for adding the slave compatibility for the ESP32.
+
+.. warning:: This function is only required for the ESP32. You **don't** need to use for ESP32-S2 and ESP32-C3.
+
+.. code-block:: arduino
+
+    size_t slaveWrite(const uint8_t *, size_t);
+
+Example Application - WireSlave.ino
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Here is an example of how to use the I2C in Slave Mode.
+
+.. literalinclude:: ../../../libraries/Wire/examples/WireSlave/WireSlave.ino
+    :language: arduino
+
+.. _Arduino Wire Library: https://www.arduino.cc/en/reference/wire
diff --git a/docs/en/api/i2s.rst b/docs/en/api/i2s.rst
new file mode 100644
index 00000000000..f67713c750f
--- /dev/null
+++ b/docs/en/api/i2s.rst
@@ -0,0 +1,557 @@
+###
+I2S
+###
+
+About
+-----
+
+I2S - Inter-IC Sound, correctly written I²S pronounced "eye-squared-ess", alternative notation is IIS. I²S is an electrical serial bus interface standard used for connecting digital audio devices together.
+
+It is used to communicate PCM (Pulse-Code Modulation) audio data between integrated circuits in an electronic device. The I²S bus separates clock and serial data signals, resulting in simpler receivers than those required for asynchronous communications systems that need to recover the clock from the data stream.
+
+Despite the similar name, I²S is unrelated and incompatible with the bidirectional I²C (IIC) bus.
+
+The I²S bus consists of at least three lines:
+
+.. note:: All lines can be attached to almost any pin and this change can occur even during operation.
+
+* **Bit clock line**
+
+  * Officially "continuous serial clock (SCK)". Typically written "bit clock (BCLK)".
+  *  In this library function parameter ``sck``.
+
+* **Word clock line**
+
+  * Officially "word select (WS)". Typically called "left-right clock (LRCLK)" or "frame sync (FS)".
+  * 0 = Left channel, 1 = Right channel
+  * In this library function parameter ``ws``.
+
+* **Data line**
+
+  * Officially "serial data (SD)", but can be called SDATA, SDIN, SDOUT, DACDAT, ADCDAT, etc.
+  * Unlike Arduino I2S with single data pin switching between input and output, in ESP core driver use separate data line for input and output.
+  * Output data line is called ``dout`` for function parameter.
+  * Input data line is called ``din`` for function parameter.
+
+It may also include a **Master clock** line:
+
+* **Master clock**
+
+  * Officially "master clock (MCLK)".
+  * This is not a part of I2S bus, but is used to synchronize multiple I2S devices.
+  * In this library function parameter ``mclk``.
+
+.. note:: Please check the `ESP-IDF documentation <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/i2s.html>`_ for more details on the I2S peripheral for each ESP32 chip.
+
+I2S Configuration
+-----------------
+
+Master / Slave Mode
+*******************
+
+In **Master mode** (default) the device is generating clock signal ``sck`` and word select signal on ``ws``.
+
+In **Slave mode** the device listens on attached pins for the clock signal and word select - i.e. unless externally driven the pins will remain LOW.
+This mode is not supported yet.
+
+Operation Modes
+***************
+
+Setting the operation mode is done with function ``begin`` and is set by function parameter ``mode``.
+
+* ``I2S_MODE_STD``
+    In standard mode, there are always two sound channels, i.e., the left and right channels, which are called "slots".
+    These slots support 8/16/24/32-bit width sample data.
+    The communication format for the slots follows the Philips standard.
+
+* ``I2S_MODE_TDM``
+    In Time Division Multiplexing mode (TDM), the number of sound channels is variable, and the width of each channel
+    is fixed.
+
+* ``I2S_MODE_PDM_TX``
+    PDM (Pulse-density Modulation) mode for the TX channel can convert PCM data into PDM format which always
+    has left and right slots.
+    PDM TX is only supported on I2S0 and it only supports 16-bit width sample data.
+    It needs at least a CLK pin for clock signal and a DOUT pin for data signal.
+
+* ``I2S_MODE_PDM_RX``
+    PDM (Pulse-density Modulation) mode for RX channel can receive PDM-format data and convert the data
+    into PCM format. PDM RX is only supported on I2S0, and it only supports 16-bit width sample data.
+    PDM RX needs at least a CLK pin for clock signal and a DIN pin for data signal.
+
+Simplex / Duplex Mode
+*********************
+
+Due to the different clock sources the PDM modes are always in **Simplex** mode, using only one data pin.
+
+The STD and TDM modes operate in the **Duplex** mode, using two separate data pins:
+
+* Output pin ``dout`` for function parameter
+* Input pin ``din`` for function parameter
+
+In this mode, the driver is able to read and write simultaneously on each line and is suitable for applications like walkie-talkie or phone.
+
+Data Bit Width
+**************
+
+This is the number of bits in a channel sample. The data bit width is set by function parameter ``bits_cfg``.
+The current supported values are:
+
+* ``I2S_DATA_BIT_WIDTH_8BIT``
+* ``I2S_DATA_BIT_WIDTH_16BIT``
+* ``I2S_DATA_BIT_WIDTH_24BIT``, requires the MCLK multiplier to be manually set to 384
+* ``I2S_DATA_BIT_WIDTH_32BIT``
+
+Sample Rate
+***********
+
+The sample rate is set by function parameter ``rate``. It is the number of samples per second in Hz.
+
+Slot Mode
+*********
+
+The slot mode is set by function parameter ``ch``. The current supported values are:
+
+* ``I2S_SLOT_MODE_MONO``
+    I2S channel slot format mono. Transmit the same data in all slots for TX mode.
+    Only receive the data in the first slots for RX mode.
+
+* ``I2S_SLOT_MODE_STEREO``
+    I2S channel slot format stereo. Transmit different data in different slots for TX mode.
+    Receive the data in all slots for RX mode.
+
+Arduino-ESP32 I2S API
+---------------------
+
+Initialization and deinitialization
+***********************************
+
+Before initialization, set which pins you want to use.
+
+begin (Master Mode)
+^^^^^^^^^^^^^^^^^^^
+
+Before usage choose which pins you want to use.
+
+.. code-block:: arduino
+
+    bool begin(i2s_mode_t mode, uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask=-1)
+
+Parameters:
+
+* [in] ``mode`` one of above mentioned operation mode, for example ``I2S_MODE_STD``.
+
+* [in] ``rate`` is the sampling rate in Hz, for example ``16000``.
+
+* [in] ``bits_cfg``  is the number of bits in a channel sample, for example ``I2S_DATA_BIT_WIDTH_16BIT``.
+
+* [in] ``ch`` is the slot mode, for example ``I2S_SLOT_MODE_STEREO``.
+
+* [in] ``slot_mask`` is the slot mask, for example ``0b11``. This parameter is optional and defaults to ``-1`` (not used).
+
+This function will return ``true`` on success or ``fail`` in case of failure.
+
+When failed, an error message will be printed if the correct log level is set.
+
+end
+^^^
+
+Performs safe deinitialization - free buffers, destroy task, end driver operation, etc.
+
+.. code-block:: arduino
+
+  void end()
+
+Pin setup
+*********
+
+The function to set the pins will depend on the operation mode.
+
+setPins
+^^^^^^^
+
+Set the pins for the I2S interface when using the standard or TDM mode.
+
+.. code-block:: arduino
+
+  void setPins(int8_t bclk, int8_t ws, int8_t dout, int8_t din=-1, int8_t mclk=-1)
+
+Parameters:
+
+* [in] ``bclk`` is the bit clock pin.
+
+* [in] ``ws`` is the word select pin.
+
+* [in] ``dout`` is the data output pin. Can be set to ``-1`` if not used.
+
+* [in] ``din`` is the data input pin. This parameter is optional and defaults to ``-1`` (not used).
+
+* [in] ``mclk`` is the master clock pin. This parameter is optional and defaults to ``-1`` (not used).
+
+setPinsPdmTx
+^^^^^^^^^^^^
+
+Set the pins for the I2S interface when using the PDM TX mode.
+
+.. code-block:: arduino
+
+  void setPinsPdmTx(int8_t clk, int8_t dout0, int8_t dout1=-1)
+
+Parameters:
+
+* [in] ``clk`` is the clock pin.
+
+* [in] ``dout0`` is the data output pin 0.
+
+* [in] ``dout1`` is the data output pin 1. This parameter is optional and defaults to ``-1`` (not used).
+
+setPinsPdmRx
+^^^^^^^^^^^^
+
+Set the pins for the I2S interface when using the PDM RX mode.
+
+.. code-block:: arduino
+
+  void setPinsPdmRx(int8_t clk, int8_t din0, int8_t din1=-1, int8_t din2=-1, int8_t din3=-1)
+
+Parameters:
+
+* [in] ``clk`` is the clock pin.
+
+* [in] ``din0`` is the data input pin 0.
+
+* [in] ``din1`` is the data input pin 1. This parameter is optional and defaults to ``-1`` (not used).
+
+* [in] ``din2`` is the data input pin 2. This parameter is optional and defaults to ``-1`` (not used).
+
+* [in] ``din3`` is the data input pin 3. This parameter is optional and defaults to ``-1`` (not used).
+
+setInverted
+^^^^^^^^^^^
+
+Set which pins have inverted logic when using the standard or TDM mode. Data pins cannot be inverted.
+
+.. code-block:: arduino
+
+  void setInverted(bool bclk, bool ws, bool mclk=false)
+
+Parameters:
+
+* [in] ``bclk`` true if the bit clock pin is inverted. False otherwise.
+
+* [in] ``ws`` true if the word select pin is inverted. False otherwise.
+
+* [in] ``mclk`` true if the master clock pin is inverted. False otherwise. This parameter is optional and defaults to ``false``.
+
+setInvertedPdm
+^^^^^^^^^^^^^^
+
+Set which pins have inverted logic when using the PDM mode. Data pins cannot be inverted.
+
+.. code-block:: arduino
+
+  void setInvertedPdm(bool clk)
+
+Parameters:
+
+* [in] ``clk`` true if the clock pin is inverted. False otherwise.
+
+I2S Configuration
+*****************
+
+The I2S configuration can be changed during operation.
+
+configureTX
+^^^^^^^^^^^
+
+Configure the I2S TX channel.
+
+.. code-block:: arduino
+
+  bool configureTX(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask=-1)
+
+Parameters:
+
+* [in] ``rate`` is the sampling rate in Hz, for example ``16000``.
+
+* [in] ``bits_cfg``  is the number of bits in a channel sample, for example ``I2S_DATA_BIT_WIDTH_16BIT``.
+
+* [in] ``ch`` is the slot mode, for example ``I2S_SLOT_MODE_STEREO``.
+
+* [in] ``slot_mask`` is the slot mask, for example ``0b11``. This parameter is optional and defaults to ``-1`` (not used).
+
+This function will return ``true`` on success or ``fail`` in case of failure.
+
+When failed, an error message will be printed if the correct log level is set.
+
+configureRX
+^^^^^^^^^^^
+
+Configure the I2S RX channel.
+
+.. code-block:: arduino
+
+  bool configureRX(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, i2s_rx_transform_t transform=I2S_RX_TRANSFORM_NONE)
+
+Parameters:
+
+* [in] ``rate`` is the sampling rate in Hz, for example ``16000``.
+
+* [in] ``bits_cfg``  is the number of bits in a channel sample, for example ``I2S_DATA_BIT_WIDTH_16BIT``.
+
+* [in] ``ch`` is the slot mode, for example ``I2S_SLOT_MODE_STEREO``.
+
+* [in] ``transform`` is the transform mode, for example ``I2S_RX_TRANSFORM_NONE``.
+         This can be used to apply a transformation/conversion to the received data.
+         The supported values are: ``I2S_RX_TRANSFORM_NONE`` (no transformation),
+         ``I2S_RX_TRANSFORM_32_TO_16`` (convert from 32 bits of data width to 16 bits) and
+         ``I2S_RX_TRANSFORM_16_STEREO_TO_MONO`` (convert from stereo to mono when using 16 bits of data width).
+
+This function will return ``true`` on success or ``fail`` in case of failure.
+
+When failed, an error message will be printed if the correct log level is set.
+
+txChan
+^^^^^^
+
+Get the TX channel handler pointer.
+
+.. code-block:: arduino
+
+  i2s_chan_handle_t txChan()
+
+txSampleRate
+^^^^^^^^^^^^
+
+Get the TX sample rate.
+
+.. code-block:: arduino
+
+  uint32_t txSampleRate()
+
+txDataWidth
+^^^^^^^^^^^
+
+Get the TX data width (8, 16 or 32 bits).
+
+.. code-block:: arduino
+
+  i2s_data_bit_width_t txDataWidth()
+
+txSlotMode
+^^^^^^^^^^
+
+Get the TX slot mode (stereo or mono).
+
+.. code-block:: arduino
+
+  i2s_slot_mode_t txSlotMode()
+
+rxChan
+^^^^^^
+
+Get the RX channel handler pointer.
+
+.. code-block:: arduino
+
+  i2s_chan_handle_t rxChan()
+
+rxSampleRate
+^^^^^^^^^^^^
+
+Get the RX sample rate.
+
+.. code-block:: arduino
+
+  uint32_t rxSampleRate()
+
+rxDataWidth
+^^^^^^^^^^^
+
+Get the RX data width (8, 16 or 32 bits).
+
+.. code-block:: arduino
+
+  i2s_data_bit_width_t rxDataWidth()
+
+rxSlotMode
+^^^^^^^^^^
+
+Get the RX slot mode (stereo or mono).
+
+.. code-block:: arduino
+
+  i2s_slot_mode_t rxSlotMode()
+
+I/O Operations
+**************
+
+readBytes
+^^^^^^^^^
+
+Read a certain amount of data bytes from the I2S interface.
+
+.. code-block:: arduino
+
+  size_t readBytes(char *buffer, size_t size)
+
+Parameters:
+
+* [in] ``buffer`` is the buffer to store the read data. The buffer must be at least ``size`` bytes long.
+
+* [in] ``size`` is the number of bytes to read.
+
+This function will return the number of bytes read.
+
+read
+^^^^
+
+Read the next available byte from the I2S interface.
+
+.. code-block:: arduino
+
+  int read()
+
+This function will return the next available byte or ``-1`` if no data is available
+or an error occurred.
+
+write
+
+There are two versions of the write function:
+
+The first version writes a certain amount of data bytes to the I2S interface.
+
+.. code-block:: arduino
+
+  size_t write(uint8_t *buffer, size_t size)
+
+Parameters:
+
+* [in] ``buffer`` is the buffer containing the data to be written.
+
+* [in] ``size`` is the number of bytes to write from the buffer.
+
+This function will return the number of bytes written.
+
+The second version writes a single byte to the I2S interface.
+
+.. code-block:: arduino
+
+  size_t write(uint8_t d)
+
+Parameters:
+
+* [in] ``d`` is the byte to be written.
+
+This function will return ``1`` if the byte was written or ``0`` if an error occurred.
+
+available
+^^^^^^^^^
+
+Get if there is data available to be read.
+
+.. code-block:: arduino
+
+  int available()
+
+This function will return ``I2S_READ_CHUNK_SIZE`` if there is data available to be read or ``-1`` if not.
+
+peek
+^^^^
+
+Get the next available byte from the I2S interface without removing it from the buffer. Currently not implemented.
+
+.. code-block:: arduino
+
+  int peek()
+
+This function will currently always return ``-1``.
+
+lastError
+^^^^^^^^^
+
+Get the last error code for an I/O operation on the I2S interface.
+
+.. code-block:: arduino
+
+  int lastError()
+
+recordWAV
+^^^^^^^^^
+
+Record a short PCM WAV to memory with the current RX settings.
+Returns a buffer that must be freed by the user.
+
+.. code-block:: arduino
+
+  uint8_t * recordWAV(size_t rec_seconds, size_t * out_size)
+
+Parameters:
+
+* [in] ``rec_seconds`` is the number of seconds to record.
+
+* [out] ``out_size`` is the size of the returned buffer in bytes.
+
+This function will return a pointer to the buffer containing the recorded WAV data or ``NULL`` if an error occurred.
+
+playWAV
+^^^^^^^
+
+Play a PCM WAV from memory with the current TX settings.
+
+.. code-block:: arduino
+
+  void playWAV(uint8_t * data, size_t len)
+
+Parameters:
+
+* [in] ``data`` is the buffer containing the WAV data.
+
+* [in] ``len`` is the size of the buffer in bytes.
+
+playMP3
+^^^^^^^
+
+Play a MP3 from memory with the current TX settings.
+
+.. code-block:: arduino
+
+  bool playMP3(uint8_t *src, size_t src_len)
+
+Parameters:
+
+* [in] ``src`` is the buffer containing the MP3 data.
+
+* [in] ``src_len`` is the size of the buffer in bytes.
+
+This function will return ``true`` on success or ``false`` in case of failure.
+
+When failed, an error message will be printed if the correct log level is set.
+
+Sample code
+-----------
+
+.. code-block:: arduino
+
+  #include <ESP_I2S.h>
+
+  const int buff_size = 128;
+  int available_bytes, read_bytes;
+  uint8_t buffer[buff_size];
+  I2SClass I2S;
+
+  void setup() {
+    I2S.setPins(5, 25, 26, 35, 0); //SCK, WS, SDOUT, SDIN, MCLK
+    I2S.begin(I2S_MODE_STD, 16000, I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO);
+    I2S.read();
+    available_bytes = I2S.available();
+    if(available_bytes < buff_size) {
+      read_bytes = I2S.readBytes(buffer, available_bytes);
+    } else {
+      read_bytes = I2S.readBytes(buffer, buff_size);
+    }
+    I2S.write(buffer, read_bytes);
+    I2S.end();
+  }
+
+  void loop() {}
diff --git a/docs/en/api/insights.rst b/docs/en/api/insights.rst
new file mode 100644
index 00000000000..a5e294f82f1
--- /dev/null
+++ b/docs/en/api/insights.rst
@@ -0,0 +1,274 @@
+############
+ESP Insights
+############
+
+About
+-----
+
+ESP Insights is a remote diagnostics solution that allows users to remotely monitor the health of Espressif devices in the field.
+
+Developers normally prefer debugging issues by physically probing them using gdb or observing the logs. This surely helps debug issues, but there are often cases wherein issues are seen only in specific environments under specific conditions. Even things like casings and placement of the product can affect the behavior. A few examples are
+
+- Wi-Fi disconnections for a smart switch concealed in a wall.
+- Smart speakers crashing during some specific usage pattern.
+- Appliance frequently rebooting due to power supply issues.
+
+Additional information about ESP Insights can be found `here <https://insights.espressif.com/>`__.
+
+ESP Insights Agent API
+----------------------
+
+Insights.begin
+**************
+
+This initializes the ESP Insights agent.
+
+.. code-block:: arduino
+
+    bool begin(const char *auth_key, const char *node_id = NULL, uint32_t log_type = 0xFFFFFFFF, bool alloc_ext_ram = false);
+
+* ``auth_key`` Auth key generated using Insights dashboard
+* ``log_type`` Type of logs to be captured (value can be a mask of ESP_DIAG_LOG_TYPE_ERROR,  ESP_DIAG_LOG_TYPE_WARNING and ESP_DIAG_LOG_TYPE_EVENT)
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.send
+*************
+
+Read insights data from buffers and send it to the cloud. Call to this function is asynchronous, it may take some time to send the data.
+
+.. code-block:: arduino
+
+    bool sendData()
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.end
+************
+
+Deinitialize ESP Insights.
+
+.. code-block:: arduino
+
+    void end();
+
+Insights.disable
+****************
+
+Disable ESP Insights.
+
+.. code-block:: arduino
+
+    void disable();
+
+ESP Insights Metrics API
+------------------------
+
+`metrics` object of `Insights` class expose API's for using metrics.
+
+Insights.metrics.addX
+*********************
+
+Register a metric of type X, where X is one of: Bool, Int, Uint, Float, String, IPv4 or MAC
+
+.. code-block:: arduino
+
+    bool addX(const char *tag, const char *key, const char *label, const char *path);
+
+* ``tag`` :  Tag of metrics
+* ``key`` :  Unique key for the metrics
+* ``label`` : Label for the metrics
+* ``path`` : Hierarchical path for key, must be separated by '.' for more than one level
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.metrics.remove
+***********************
+
+Unregister a diagnostics metrics
+
+.. code-block:: arduino
+
+    bool remove(const char *key);
+
+* ``key`` : Key for the metrics
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.metrics.removeAll
+**************************
+
+Unregister all previously registered metrics
+
+.. code-block:: arduino
+
+    bool removeAll();
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.metrics.setX
+*********************
+
+Add metrics of type X to storage, where X is one of: Bool, Int, Uint, Float, String, IPv4 or MAC
+
+.. code-block:: arduino
+
+    bool setX(const char *key, const void val);
+
+* ``key`` :       Key of metrics
+* ``val`` :       Value of metrics
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+Insights.metrics.dumpHeap
+*************************
+
+Dumps the heap metrics and prints them to the console.
+This API collects and reports metrics value at any give point in time.
+
+.. code-block:: arduino
+
+    bool dumpHeap();
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.metrics.dumpWiFi
+*************************
+
+Dumps the Wi-Fi metrics and prints them to the console.
+This API can be used to collect Wi-Fi metrics at any given point in time.
+
+.. code-block:: arduino
+
+    bool dumpWiFi();
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.metrics.setHeapPeriod
+******************************
+
+Reset the periodic interval
+By default, heap metrics are collected every 30 seconds, this function can be used to change the interval.
+If the interval is set to 0, heap metrics collection disabled.
+
+.. code-block:: arduino
+
+    void setHeapPeriod(uint32_t period);
+
+* ``period`` : Period interval in seconds
+
+Insights.metrics.setWiFiPeriod
+******************************
+
+Reset the periodic interval
+By default, Wi-Fi metrics are collected every 30 seconds, this function can be used to change the interval.
+If the interval is set to 0, Wi-Fi metrics collection disabled.
+
+.. code-block:: arduino
+
+    void setHeapPeriod(uint32_t period);
+
+* ``period`` : Period interval in seconds
+
+ESP Insights Variables API
+--------------------------
+
+`variables` object of `Insights` class expose API's for using variables.
+
+Insights.variables.addX
+***********************
+
+Register a variable of type X, where X is one of: Bool, Int, Uint, Float, String, IPv4 or MAC
+
+.. code-block:: arduino
+
+    bool addX(const char *tag, const char *key, const char *label, const char *path);
+
+* ``tag`` :  Tag of variable
+* ``key`` :  Unique key for the variable
+* ``label`` : Label for the variable
+* ``path`` : Hierarchical path for key, must be separated by '.' for more than one level
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.variables.remove
+*************************
+
+Unregister a diagnostics variable
+
+.. code-block:: arduino
+
+    bool remove(const char *key);
+
+* ``key`` : Key for the variable
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.variables.removeAll
+****************************
+
+Unregister all previously registered variables
+
+.. code-block:: arduino
+
+    bool unregisterAll();
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Insights.variables.setX
+***********************
+
+Add variable of type X to storage, where X is one of: Bool, Int, Uint, Float, String, IPv4 or MAC
+
+.. code-block:: arduino
+
+    bool setX(const char *key, const void val);
+
+* ``key`` :       Key of metrics
+* ``val`` :       Value of metrics
+
+This function will return
+
+1. true : On success
+2. false in case of failure
+
+Example
+-------
+
+To get started with Insights, you can try:
+
+.. literalinclude:: ../../../libraries/Insights/examples/MinimalDiagnostics/MinimalDiagnostics.ino
+    :language: arduino
diff --git a/docs/en/api/ledc.rst b/docs/en/api/ledc.rst
new file mode 100644
index 00000000000..6ea3437bbf5
--- /dev/null
+++ b/docs/en/api/ledc.rst
@@ -0,0 +1,341 @@
+##################
+LED Control (LEDC)
+##################
+
+About
+-----
+The LED control (LEDC) peripheral is primarily designed to control the intensity of LEDs,
+although it can also be used to generate PWM signals for other purposes.
+
+ESP32 SoCs has from 6 to 16 channels (variates on socs, see table below) which can generate independent waveforms, that can be used for example to drive RGB LED devices.
+
+========= =======================
+ESP32 SoC Number of LEDC channels
+========= =======================
+ESP32     16
+ESP32-S2  8
+ESP32-S3  8
+ESP32-C3  6
+ESP32-C6  6
+ESP32-H2  6
+========= =======================
+
+Arduino-ESP32 LEDC API
+----------------------
+
+ledcSetCLockSource
+******************
+
+This function is used to set the LEDC peripheral clock source. Must be called before any LEDC channel is used.
+The default clock source is XTAL clock (``LEDC_USE_XTAL_CLK``) if supported by the SoC, otherwise it is AUTO clock (``LEDC_AUTO_CLK``).
+
+.. code-block:: arduino
+
+    bool ledcSetClockSource(ledc_clk_cfg_t source);
+
+* ``source`` select the clock source for LEDC peripheral.
+
+  * ``LEDC_APB_CLK`` - APB clock.
+  * ``LEDC_REF_CLK`` - REF clock.
+
+This function will return ``true`` if setting the clock source is successful, otherwise it will return ``false``.
+
+ledcGetClockSource
+******************
+
+This function is used to get the LEDC peripheral clock source.
+
+.. code-block:: arduino
+
+    ledc_clk_cfg_t ledcGetClockSource(void);
+
+This function will return the clock source for the LEDC peripheral.
+
+ledcAttach
+**********
+
+This function is used to setup LEDC pin with given frequency and resolution. LEDC channel will be selected automatically.
+
+.. code-block:: arduino
+
+    bool ledcAttach(uint8_t pin, uint32_t freq, uint8_t resolution);
+
+* ``pin`` select LEDC pin.
+* ``freq`` select frequency of pwm.
+* ``resolution`` select resolution for LEDC channel.
+
+  * range is 1-14 bits (1-20 bits for ESP32).
+
+This function will return ``true`` if configuration is successful.
+If ``false`` is returned, error occurs and LEDC channel was not configured.
+
+ledcAttachChannel
+*****************
+
+This function is used to setup LEDC pin with given frequency, resolution and channel.
+Attaching multiple pins to the same channel will make them share the same duty cycle. Given frequency, resolution will be ignored if channel is already configured.
+
+.. code-block:: arduino
+
+    bool ledcAttachChannel(uint8_t pin, uint32_t freq, uint8_t resolution, int8_t channel);
+
+* ``pin`` select LEDC pin.
+* ``freq`` select frequency of pwm.
+* ``resolution`` select resolution for LEDC channel.
+
+  * range is 1-14 bits (1-20 bits for ESP32).
+
+* ``channel`` select LEDC channel.
+
+This function will return ``true`` if configuration is successful.
+If ``false`` is returned, error occurs and LEDC channel was not configured.
+
+ledcWrite
+*********
+
+This function is used to set duty for the LEDC pin.
+
+.. code-block:: arduino
+
+    bool ledcWrite(uint8_t pin, uint32_t duty);
+
+* ``pin`` select LEDC pin.
+* ``duty`` select duty to be set for selected LEDC pin.
+
+This function will return ``true`` if setting duty is successful.
+If ``false`` is returned, error occurs and duty was not set.
+
+ledcWriteChannel
+****************
+
+This function is used to set duty for the LEDC channel.
+
+.. code-block:: arduino
+
+    bool ledcWriteChannel(uint8_t channel, uint32_t duty);
+
+* ``channel`` select LEDC channel.
+* ``duty`` select duty to be set for selected LEDC channel.
+
+This function will return ``true`` if setting duty is successful.
+If ``false`` is returned, error occurs and duty was not set.
+
+ledcRead
+********
+
+This function is used to get configured duty for the LEDC pin.
+
+.. code-block:: arduino
+
+    uint32_t ledcRead(uint8_t pin);
+
+* ``pin`` select LEDC pin to read the configured LEDC duty.
+
+This function will return ``duty`` set for selected LEDC pin.
+
+ledcReadFreq
+************
+
+This function is used to get configured frequency for the LEDC channel.
+
+.. code-block:: arduino
+
+    uint32_t ledcReadFreq(uint8_t pin);
+
+* ``pin`` select LEDC pin to read the configured frequency.
+
+This function will return ``frequency`` configured for selected LEDC pin.
+
+ledcWriteTone
+*************
+
+This function is used to setup the LEDC pin to 50 % PWM tone on selected frequency.
+
+.. code-block:: arduino
+
+    uint32_t ledcWriteTone(uint8_t pin, uint32_t freq);
+
+* ``pin`` select LEDC pin.
+* ``freq`` select frequency of pwm signal. If frequency is ``0``, duty will be set to 0.
+
+This function will return ``frequency`` set for LEDC pin.
+If ``0`` is returned, error occurs and LEDC pin was not configured.
+
+ledcWriteNote
+*************
+
+This function is used to setup the LEDC pin to specific note.
+
+.. code-block:: arduino
+
+    uint32_t ledcWriteNote(uint8_t pin, note_t note, uint8_t octave);
+
+* ``pin`` select LEDC pin.
+* ``note`` select note to be set.
+
+======= ======= ======= ======= ======= ======
+NOTE_C  NOTE_Cs NOTE_D  NOTE_Eb NOTE_E  NOTE_F
+NOTE_Fs NOTE_G  NOTE_Gs NOTE_A  NOTE_Bb NOTE_B
+======= ======= ======= ======= ======= ======
+
+* ``octave`` select octave for note.
+
+This function will return ``frequency`` configured for the LEDC pin according to note and octave inputs.
+If ``0`` is returned, error occurs and the LEDC channel was not configured.
+
+ledcDetach
+**********
+
+This function is used to detach the pin from LEDC.
+
+.. code-block:: arduino
+
+    bool ledcDetach(uint8_t pin);
+
+* ``pin`` select LEDC pin.
+
+This function returns ``true`` if detaching was successful.
+If ``false`` is returned, an error occurred and the pin was not detached.
+
+ledcChangeFrequency
+*******************
+
+This function is used to set frequency for the LEDC pin.
+
+.. code-block:: arduino
+
+    uint32_t ledcChangeFrequency(uint8_t pin, uint32_t freq, uint8_t resolution);
+
+* ``pin`` select LEDC pin.
+* ``freq`` select frequency of pwm.
+* ``resolution`` select resolution for LEDC channel.
+
+  * range is 1-14 bits (1-20 bits for ESP32).
+
+This function will return ``frequency`` configured for the LEDC channel.
+If ``0`` is returned, error occurs and the LEDC channel frequency was not set.
+
+ledcOutputInvert
+****************
+
+This function is used to set inverting output for the LEDC pin.
+
+.. code-block:: arduino
+
+    bool ledcOutputInvert(uint8_t pin, bool out_invert);
+
+* ``pin`` select LEDC pin.
+* ``out_invert`` select, if output should be inverted (true = inverting output).
+
+This function returns ``true`` if setting inverting output was successful.
+If ``false`` is returned, an error occurred and the inverting output was not set.
+
+ledcFade
+********
+
+This function is used to setup and start fade for the LEDC pin.
+
+.. code-block:: arduino
+
+    bool ledcFade(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms);
+
+* ``pin`` select LEDC pin.
+* ``start_duty`` select starting duty of fade.
+* ``target_duty`` select target duty of fade.
+* ``max_fade_time_ms`` select maximum time for fade.
+
+This function will return ``true`` if configuration is successful.
+If ``false`` is returned, error occurs and LEDC fade was not configured / started.
+
+ledcFadeWithInterrupt
+*********************
+
+This function is used to setup and start fade for the LEDC pin with interrupt.
+
+.. code-block:: arduino
+
+    bool ledcFadeWithInterrupt(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void));
+
+* ``pin`` select LEDC pin.
+* ``start_duty`` select starting duty of fade.
+* ``target_duty`` select target duty of fade.
+* ``max_fade_time_ms`` select maximum time for fade.
+* ``userFunc`` function to be called when interrupt is triggered.
+
+This function will return ``true`` if configuration is successful and fade start.
+If ``false`` is returned, error occurs and LEDC fade was not configured / started.
+
+ledcFadeWithInterruptArg
+************************
+
+This function is used to setup and start fade for the LEDC pin with interrupt using arguments.
+
+.. code-block:: arduino
+
+    bool ledcFadeWithInterruptArg(uint8_t pin, uint32_t start_duty, uint32_t target_duty, int max_fade_time_ms, void (*userFunc)(void*), void * arg);
+
+* ``pin`` select LEDC pin.
+* ``start_duty`` select starting duty of fade.
+* ``target_duty`` select target duty of fade.
+* ``max_fade_time_ms`` select maximum time for fade.
+* ``userFunc`` function to be called when interrupt is triggered.
+* ``arg`` pointer to the interrupt arguments.
+
+This function will return ``true`` if configuration is successful and fade start.
+If ``false`` is returned, error occurs and LEDC fade was not configured / started.
+
+analogWrite
+***********
+
+This function is used to write an analog value (PWM wave) on the pin.
+It is compatible with Arduinos analogWrite function.
+
+.. code-block:: arduino
+
+    void analogWrite(uint8_t pin, int value);
+
+* ``pin`` select the GPIO pin.
+* ``value`` select the duty cycle of pwm.
+  * range is from 0 (always off) to 255 (always on).
+
+analogWriteResolution
+*********************
+
+This function is used to set resolution for selected analogWrite pin.
+
+.. code-block:: arduino
+
+    void analogWriteResolution(uint8_t pin, uint8_t resolution);
+
+* ``pin`` select the GPIO pin.
+* ``resolution`` select resolution for analog channel.
+
+analogWriteFrequency
+********************
+
+This function is used to set frequency for selected analogWrite pin.
+
+.. code-block:: arduino
+
+    void analogWriteFrequency(uint8_t pin, uint32_t freq);
+
+* ``pin`` select the GPIO pin.
+* ``freq`` select frequency of pwm.
+
+Example Applications
+********************
+
+LEDC fade example:
+
+.. literalinclude:: ../../../libraries/ESP32/examples/AnalogOut/LEDCFade/LEDCFade.ino
+    :language: arduino
+
+LEDC software fade example:
+
+.. literalinclude:: ../../../libraries/ESP32/examples/AnalogOut/LEDCSoftwareFade/LEDCSoftwareFade.ino
+    :language: arduino
+
+LEDC Write RGB example:
+
+.. literalinclude:: ../../../libraries/ESP32/examples/AnalogOut/ledcWrite_RGB/ledcWrite_RGB.ino
+    :language: arduino
diff --git a/docs/en/api/preferences.rst b/docs/en/api/preferences.rst
new file mode 100644
index 00000000000..2ff6f178347
--- /dev/null
+++ b/docs/en/api/preferences.rst
@@ -0,0 +1,724 @@
+###########
+Preferences
+###########
+
+About
+-----
+
+The Preferences library is unique to arduino-esp32. It should be considered as the replacement for the Arduino EEPROM library.
+
+It uses a portion of the on-board non-volatile memory (NVS) of the ESP32 to store data. This data is retained across restarts and loss of power events to the system.
+
+Preferences works best for storing many small values, rather than a few large values. If large amounts of data are to be stored, consider using a file system library such as LitteFS.
+
+The Preferences library is usable by all ESP32 variants.
+
+
+Header File
+-----------
+
+.. code-block:: arduino
+
+    #include <Preferences.h>
+..
+
+
+Overview
+--------
+
+Library methods are provided to:
+   - create a namespace;
+   - open and close a namespace;
+   - store and retrieve data within a namespace for supported data types;
+   - determine if a key value has been initialized;
+   - delete a ``key-value`` pair;
+   - delete all ``key-value`` pairs in a namespace;
+   - determine data types stored against a key;
+   - determine the number of key entries in the namespace.
+
+Preferences directly supports the following data types:
+
+.. table:: **Table 1 — Preferences Data Types**
+   :align: center
+
+   +-------------------+-------------------+---------------+
+   | Preferences Type  | Data Type         | Size (bytes)  |
+   +===================+===================+===============+
+   | Bool              | bool              | 1             |
+   +-------------------+-------------------+---------------+
+   | Char              | int8_t            | 1             |
+   +-------------------+-------------------+---------------+
+   | UChar             | uint8_t           | 1             |
+   +-------------------+-------------------+---------------+
+   | Short             | int16_t           | 2             |
+   +-------------------+-------------------+---------------+
+   | UShort            | uint16_t          | 2             |
+   +-------------------+-------------------+---------------+
+   | Int               | int32_t           | 4             |
+   +-------------------+-------------------+---------------+
+   | UInt              | uint32_t          | 4             |
+   +-------------------+-------------------+---------------+
+   | Long              | int32_t           | 4             |
+   +-------------------+-------------------+---------------+
+   | ULong             | uint32_t          | 4             |
+   +-------------------+-------------------+---------------+
+   | Float             | float_t           | 4             |
+   +-------------------+-------------------+---------------+
+   | Long64            | int64_t           | 8             |
+   +-------------------+-------------------+---------------+
+   | ULong64           | uint64_t          | 8             |
+   +-------------------+-------------------+---------------+
+   | Double            | double_t          | 8             |
+   +-------------------+-------------------+---------------+
+   |                   | const char*       | variable      |
+   | String            +-------------------+               |
+   |                   | String            |               |
+   +-------------------+-------------------+---------------+
+   | Bytes             | uint8_t           | variable      |
+   +-------------------+-------------------+---------------+
+
+String values can be stored and retrieved either as an Arduino String or as a null terminated ``char`` array (c-string).
+
+Bytes type is used for storing and retrieving an arbitrary number of bytes in a namespace.
+
+
+Arduino-esp32 Preferences API
+-----------------------------
+
+``begin``
+**********
+
+   Open non-volatile storage with a given namespace name from an NVS partition.
+
+   .. code-block:: arduino
+
+     bool begin(const char * name, bool readOnly=false, const char* partition_label=NULL)
+   ..
+
+   **Parameters**
+      * ``name`` (Required)
+         - Namespace name. Maximum length is 15 characters.
+
+      * ``readOnly`` (Optional)
+         - ``false`` will open the namespace in read-write mode.
+         - ``true``  will open the namespace in read-only mode.
+         - if omitted, the namespace is opened in read-write mode.
+
+      * ``partition_label`` (Optional)
+         - name of the NVS partition in which to open the namespace.
+         - if omitted, the namespace is opened in the "``nvs``" partition.
+
+   **Returns**
+      * ``true`` if the namespace was opened successfully; ``false`` otherwise.
+
+   **Notes**
+      * If the namespace does not exist within the partition, it is first created.
+      * Attempting to write a key value to a namespace open in read-only mode will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``end``
+*********
+
+   Close the currently opened namespace.
+
+   .. code-block:: arduino
+
+      void end()
+   ..
+
+   **Parameters**
+      * None
+
+   **Returns**
+      * Nothing
+
+   **Note**
+      * After closing a namespace, methods used to access it will fail.
+
+
+``clear``
+**********
+
+   Delete all keys and values from the currently opened namespace.
+
+   .. code-block:: arduino
+
+      bool clear()
+   ..
+
+   **Parameters**
+      * None
+
+   **Returns**
+      * ``true`` if all keys and values were deleted; ``false`` otherwise.
+
+   **Note**
+      * the namespace name still exists afterward.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``remove``
+*************
+
+   Delete a key-value pair from the currently open namespace.
+
+   .. code-block:: arduino
+
+       bool remove(const char * key)
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+         -  the name of the key to be deleted.
+
+   **Returns**
+      * ``true`` if key-value pair was deleted; ``false`` otherwise.
+
+   **Note**
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``isKey``
+*************
+
+   Check if a key-value pair from the currently open namespace exists.
+
+   .. code-block:: arduino
+
+       bool isKey(const char * key)
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+         -  the name of the key to be checked.
+
+   **Returns**
+      * ``true`` if key-value pair exists; ``false`` otherwise.
+
+   **Note**
+      * Attempting to check a key without a namespace being open will return false.
+
+
+``putChar, putUChar``
+**********************
+
+   Store a value against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+       size_t putChar(const char* key, int8_t value)
+       size_t putUChar(const char* key, uint8_t value)
+
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+         - if the key does not exist in the currently opened namespace it is first created.
+
+      * ``value`` (Required)
+         - must match the data type of the method.
+
+   **Returns**
+      * ``1`` (the number of bytes stored for these data types) if the call is successful; ``0`` otherwise.
+
+   **Notes**
+      * Attempting to store a value without a namespace being open in read-write mode will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``putShort, putUShort``
+************************
+
+   Store a value against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+       size_t putShort(const char* key, int16_t value)
+       size_t putUShort(const char* key, uint16_t value)
+
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+         - if the key does not exist in the currently opened namespace it is first created.
+
+      * ``value`` (Required)
+         - must match the data type of the method.
+
+   **Returns**
+      * ``2`` (the number of bytes stored for these data types) if the call is successful; ``0`` otherwise.
+
+   **Notes**
+      * Attempting to store a value without a namespace being open in read-write mode will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+
+``putInt, putUInt``
+********************
+``putLong, putULong``
+**********************
+``putFloat``
+**********************
+
+   Store a value against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+       size_t putInt(const char* key, int32_t value)
+       size_t putUInt(const char* key, uint32_t value)
+       size_t putLong(const char* key, int32_t value)
+       size_t putULong(const char* key, uint32_t value)
+       size_t putFloat(const char* key, float_t value)
+
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+         - if the key does not exist in the currently opened namespace it is first created.
+
+      * ``value`` (Required)
+         - must match the data type of the method.
+
+   **Returns**
+      * ``4`` (the number of bytes stored for these data types) if the call is successful; ``0`` otherwise.
+
+   **Notes**
+      * Attempting to store a value without a namespace being open in read-write mode will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``putLong64, putULong64``
+*************************
+``putDouble``
+*************************
+
+   Store a value against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+       size_t putLong64(const char* key, int64_t value)
+       size_t putULong64(const char* key, uint64_t value)
+       size_t putDouble(const char* key, double_t value)
+
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+         - if the key does not exist in the currently opened namespace it is first created.
+
+      * ``value`` (Required)
+         - must match the data type of the method.
+
+   **Returns**
+      * ``8`` (the number of bytes stored for these data types) if the call is successful; ``0`` otherwise.
+
+   **Notes**
+      * Attempting to store a value without a namespace being open in read-write mode will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``putBool``
+***********
+
+   Store a value against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+          size_t putBool(const char* key, bool value)
+
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+         - if the key does not exist in the currently opened namespace it is first created.
+
+      * ``value`` (Required)
+         - must match the data type of the method.
+
+   **Returns**
+      * ``true`` if successful; ``false`` otherwise.
+
+   **Notes**
+      * Attempting to store a value without a namespace being open in read-write mode will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``putString``
+**************
+
+   Store a variable length value against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+       size_t putString(const char* key, const char* value);
+       size_t putString(const char* key, String value);
+
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+         - if the key does not exist in the currently opened namespace it is first created.
+
+      * ``value`` (Required)
+         - if ``const char*``, a null-terminated (c-string) character array.
+         - if ``String``, a valid Arduino String type.
+
+   **Returns**
+      * if successful: the number of bytes stored; ``0`` otherwise.
+
+   **Notes**
+      * Attempting to store a value without a namespace being open in read-write mode will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``putBytes``
+************
+
+   Store a variable number of bytes against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+       size_t putBytes(const char* key, const void* value, size_t len);
+
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+         - if the key does not exist in the currently opened namespace it is first created.
+
+      * ``value`` (Required)
+         - pointer to an array or buffer containing the bytes to be stored.
+
+      * ``len`` (Required)
+         - the number of bytes from ``value`` to be stored.
+
+   **Returns**
+      *  if successful: the number of bytes stored; ``0`` otherwise.
+
+   **Notes**
+      * Attempting to store a value without a namespace being open in read-write mode will fail.
+      * This method operates on the bytes used by the underlying data type, not the number of elements of a given data type. The data type of ``value`` is not retained by the Preferences library afterward.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``getChar, getUChar``
+*********************
+
+   Retrieve a value stored against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+      int8_t getChar(const char* key, int8_t defaultValue = 0)
+      uint8_t getUChar(const char* key, uint8_t defaultValue = 0)
+
+   ..
+
+   **Parameters**
+      * ``key`` (Required)
+
+      * ``defaultValue`` (Optional)
+         - must match the data type of the method if provided.
+
+   **Returns**
+      * the value stored against ``key`` if the call is successful.
+      * ``defaultValue``, if it is provided; ``0`` otherwise.
+
+   **Notes**
+      * Attempting to retrieve a key without a namespace being available will fail.
+      * Attempting to retrieve value from a non existent key will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``getShort, getUShort``
+****************************
+
+   Retrieve a value stored against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+      int16_t getShort(const char* key, int16_t defaultValue = 0)
+      uint16_t getUShort(const char* key, uint16_t defaultValue = 0)
+   ..
+
+   Except for the data type returned, behaves exactly like ``getChar``.
+
+
+
+``getInt, getUInt``
+*******************
+
+   Retrieve a value stored against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+    int32_t getInt(const char* key, int32_t defaultValue = 0)
+    uint32_t getUInt(const char* key, uint32_t defaultValue = 0)
+
+   ..
+
+   Except for the data type returned, behaves exactly like ``getChar``.
+
+
+``getLong, getULong``
+*********************
+
+   Retrieve a value stored against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+      int32_t getLong(const char* key, int32_t defaultValue = 0)
+      uint32_t getULong(const char* key, uint32_t defaultValue = 0)
+
+   ..
+
+   Except for the data type returned, behaves exactly like ``getChar``.
+
+
+``getLong64, getULong64``
+*************************
+
+   Retrieve a value stored against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+      int64_t getLong64(const char* key, int64_t defaultValue = 0)
+      uint64_t getULong64(const char* key, uint64_t defaultValue = 0)
+
+   ..
+
+   Except for the data type returned, behaves exactly like ``getChar``.
+
+
+``getFloat``
+*************
+
+   Retrieve a value stored against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+      float_t getFloat(const char* key, float_t defaultValue = NAN)
+
+   ..
+
+   Except for the data type returned and the value of ``defaultValue``, behaves exactly like ``getChar``.
+
+
+``getDouble``
+*************
+
+   Retrieve a value stored against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+      double_t getDouble(const char* key, double_t defaultValue = NAN)
+
+   ..
+
+   Except for the data type returned and the value of ``defaultValue``, behaves exactly like ``getChar``.
+
+
+``getBool``
+************
+
+   Retrieve a value stored against a given key in the currently open namespace.
+
+   .. code-block:: arduino
+
+      bool getBool(const char* key, bool defaultValue = false);
+
+   ..
+
+   Except for the data type returned, behaves exactly like ``getChar``.
+
+
+``getString``
+*************
+
+   Copy a string of ``char`` stored against a given key in the currently open namespace to a buffer.
+
+.. code-block:: arduino
+
+    size_t getString(const char* key, char* value, size_t len);
+..
+
+   **Parameters**
+      * ``key`` (Required)
+      * ``value`` (Required)
+         - a buffer of a size large enough to hold ``len`` bytes
+      * ``len`` (Required)
+         - the number of type ``char``` to be written to the buffer pointed to by ``value``
+
+   **Returns**
+      * if successful; the number of bytes equal to ``len`` is written to the buffer pointed to by ``value``, and the method returns ``1``.
+      * if the method fails, nothing is written to the buffer pointed to by ``value`` and the method returns ``0``.
+
+   **Notes**
+      * ``len`` must equal the number of bytes stored against the key or the call will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``getString``
+*************
+
+   Retrieve an Arduino String value stored against a given key in the currently open namespace.
+
+.. code-block:: arduino
+
+    String getString(const char* key, String defaultValue = String());
+
+..
+
+   **Parameters**
+      * ``key`` (Required)
+      * ``defaultValue`` (Optional)
+
+   **Returns**
+      * the value stored against ``key`` if the call if successful
+      * if the method fails: it returns ``defaultValue``, if provided; ``""`` (an empty String) otherwise.
+
+   **Notes**
+      * ``defaultValue`` must be of type ``String``.
+
+
+``getBytes``
+*************
+
+Copy a series of bytes stored against a given key in the currently open namespace to a buffer.
+
+.. code-block:: arduino
+
+   size_t getBytes(const char* key, void * buf, size_t len);
+
+..
+
+   **Parameters**
+      * ``key`` (Required)
+      * ``buf`` (Required)
+         - a buffer of a size large enough to hold ``len`` bytes.
+      * ``len`` (Required)
+         - the number of bytes to be written to the buffer pointed to by ``buf``
+
+   **Returns**
+      * if successful, the number of bytes equal to ``len`` is written to buffer ``buf``, and the method returns ``len``.
+      * if the method fails, nothing is written to the buffer and the method returns ``0``.
+
+   **Notes**
+      * ``len`` must equal the number of bytes stored against the key or the call will fail.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``getBytesLength``
+******************
+
+Get the number of bytes stored in the value against a key of type ``Bytes`` in the currently open namespace.
+
+.. code-block:: arduino
+
+   size_t getBytesLength(const char* key)
+
+..
+
+   **Parameters**
+      * ``key`` (Required)
+
+   **Returns**
+      * if successful: the number of bytes in the value stored against ``key``; ``0`` otherwise.
+
+   **Notes**
+      * This method will fail if ``key`` is not of type ``Bytes``.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+``getType``
+***********
+
+Get the Preferences data type of a given key within the currently open namespace.
+
+.. code-block:: arduino
+
+   PreferenceType getType(const char* key)
+
+..
+
+   **Parameters**
+      * ``key`` (Required)
+
+   **Returns**
+      * an ``int`` value as per Table 2 below.
+      * a value of ``10`` (PT_INVALID) if the call fails.
+
+   **Notes**
+      * The return values are enumerated in ``Preferences.h``. Table 2 includes the enumerated values for information.
+      * A return value can map to more than one Prefs Type.
+      * The method will fail if: the namespace is not open; the key does not exist; the provided key exceeds 15 characters.
+
+.. table:: **Table 2 — getType Return Values**
+   :align: center
+
+   +---------------+---------------+-------------------+-----------------------+
+   | Return value  | Prefs Type    | Data Type         | Enumerated Value      |
+   +===============+===============+===================+=======================+
+   | 0             | Char          | int8_t            | PT_I8                 |
+   +---------------+---------------+-------------------+-----------------------+
+   | 1             | UChar         | uint8_t           | PT_U8                 |
+   |               +---------------+-------------------+                       |
+   |               | Bool          | bool              |                       |
+   +---------------+---------------+-------------------+-----------------------+
+   | 2             | Short         | int16_t           | PT_I16                |
+   +---------------+---------------+-------------------+-----------------------+
+   | 3             | UShort        | uint16_t          | PT_U16                |
+   +---------------+---------------+-------------------+-----------------------+
+   | 4             | Int           | int32_t           | PT_I32                |
+   |               +---------------+                   |                       |
+   |               | Long          |                   |                       |
+   +---------------+---------------+-------------------+-----------------------+
+   | 5             | UInt          | uint32_t          | PT_U32                |
+   |               +---------------+                   |                       |
+   |               | ULong         |                   |                       |
+   +---------------+---------------+-------------------+-----------------------+
+   | 6             | Long64        | int64_t           | PT_I64                |
+   +---------------+---------------+-------------------+-----------------------+
+   | 7             | ULong64       | uint64_t          | PT_U64                |
+   +---------------+---------------+-------------------+-----------------------+
+   | 8             | String        | String            | PT_STR                |
+   |               |               +-------------------+                       |
+   |               |               | \*char            |                       |
+   +---------------+---------------+-------------------+-----------------------+
+   | 9             | Double        | double_t          | PT_BLOB               |
+   |               +---------------+-------------------+                       |
+   |               | Float         | float_t           |                       |
+   |               +---------------+-------------------+                       |
+   |               | Bytes         | uint8_t           |                       |
+   +---------------+---------------+-------------------+-----------------------+
+   | 10            | \-            | \-                | PT_INVALID            |
+   +---------------+---------------+-------------------+-----------------------+
+
+
+``freeEntries``
+***************
+
+Get the number of free entries available in the key table of the currently open namespace.
+
+.. code-block:: arduino
+
+   size_t freeEntries()
+
+..
+
+   **Parameters**
+      * none
+
+   **Returns**
+      * if successful: the number of free entries available in the key table of the currently open namespace; ``0`` otherwise.
+
+   **Notes**
+      * keys storing values of type ``Bool``, ``Char``, ``UChar``, ``Short``, ``UShort``, ``Int``, ``UInt``, ``Long``, ``ULong``, ``Long64``, ``ULong64`` use one entry in the key table.
+      * keys storing values of type ``Float`` and ``Double`` use three entries in the key table.
+      * Arduino or c-string ``String`` types use a minimum of two key table entries with the number of entries increasing with the length of the string.
+      * keys storing values of type ``Bytes`` use a minimum of three key table entries with the number of entries increasing with the number of bytes stored.
+      * A message providing the reason for a failed call is sent to the arduino-esp32 ``log_e`` facility.
+
+
+..    --- EOF ----
diff --git a/docs/en/api/pulse_counter.rst b/docs/en/api/pulse_counter.rst
new file mode 100644
index 00000000000..2fedd8ffd96
--- /dev/null
+++ b/docs/en/api/pulse_counter.rst
@@ -0,0 +1,8 @@
+#############
+Pulse Counter
+#############
+
+About
+-----
+
+.. note:: This peripheral is not supported yet by the Arduino API's.
diff --git a/docs/en/api/rainmaker.rst b/docs/en/api/rainmaker.rst
new file mode 100644
index 00000000000..01309f605ad
--- /dev/null
+++ b/docs/en/api/rainmaker.rst
@@ -0,0 +1,663 @@
+#############
+ESP Rainmaker
+#############
+
+About
+-----
+
+This library allows to work with ESP RainMaker.
+
+ESP RainMaker is an end-to-end solution offered by Espressif to enable remote control and monitoring for ESP32-S2 and ESP32 based products without any configuration required in the Cloud. The primary components of this solution are:
+
+- Claiming Service (to get the Cloud connectivity credentials)
+- RainMaker library (i.e. this library, to develop the firmware)
+- RainMaker Cloud (backend, offering remote connectivity)
+- RainMaker Phone App/CLI (Client utilities for remote access)
+
+The key features of ESP RainMaker are:
+
+1. Ability to define own devices and parameters, of any type, in the firmware.
+2. Zero configuration required on the Cloud.
+3. Phone apps that dynamically render the UI as per the device information.
+
+Additional information about ESP RainMaker can be found `here <https://rainmaker.espressif.com/>`__.
+
+
+ESP RainMaker Agent API
+-----------------------
+
+RMaker.initNode
+***************
+
+This initializes the ESP RainMaker agent, Wi-Fi and creates the node.
+
+You can also set the configuration of the node using the following API
+
+``RMaker.setTimeSync(bool val)``
+
+**NOTE**: If you want to set the configuration for the node then these configuration API must be called before `RMaker.initNode()`.
+
+.. code-block:: arduino
+
+    Node initNode(const char *name, const char *type);
+
+* ``name`` Name of the node
+* ``type`` Type of the node
+
+This function will return object of Node.
+
+RMaker.start
+************
+
+It starts the ESP RainMaker agent.
+
+**NOTE**:
+
+1. ESP RainMaker agent should be initialized before this call.
+2. Once ESP RainMaker agent starts, compulsorily call ``WiFi.beginProvision()`` API.
+
+.. code-block:: arduino
+
+    esp_err_t start();
+
+This function will return `ESP_OK` on success or  `Error` in case of failure.
+
+RMaker.stop
+***********
+
+It stops the ESP RainMaker agent which was started using `RMaker.start()`.
+
+.. code-block:: arduino
+
+    esp_err_t stop()
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure.
+
+RMaker.deinitNode
+*****************
+
+It deinitializes the ESP RainMaker agent and the node created using `RMaker.initNode()`.
+
+.. code-block:: arduino
+
+    esp_err_t deinitNode(Node node)
+
+* ``node`` : Node object created using `RMaker.initNode()`
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+RMaker.enableOTA
+****************
+
+It enables OTA as per the ESP RainMaker Specification. For more details refer ESP RainMaker documentation. check `here <https://rainmaker.espressif.com/docs/ota.html>`__.
+
+.. code-block:: arduino
+
+    esp_err_t enableOTA(ota_type_t type);
+
+* ``type`` : The OTA workflow type.
+    - OTA_USING_PARAMS
+    - OTA_USING_TOPICS
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+RMaker.enableSchedule
+*********************
+
+This API enables the scheduling service for the node. For more information, check `here <https://rainmaker.espressif.com/docs/scheduling.html>`__.
+
+.. code-block:: arduino
+
+    esp_err_t enableSchedule();
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+RMaker.enableScenes
+*******************
+
+This API enables the Scenes service for the node. It should be called after `RMaker.initNode()` and before `RMaker.start()`.
+For more information, check `here <https://rainmaker.espressif.com/docs/scenes.html>`__.
+
+.. code-block:: arduino
+
+    esp_err_t enableScenes()
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+RMaker.enableSystemService
+**************************
+
+This API enables the System service for the node. It should be called after `RMaker.initNode()` and before `RMaker.start()`.
+For more information, check `here <https://rainmaker.espressif.com/docs/sys-service.html>`__.
+
+.. code-block:: arduino
+
+    esp_err_t enableSystemService(uint16_t flags, int8_t reboot_seconds, int8_t reset_seconds, int8_t reset_reboot_seconds)
+
+* ``flags`` : Logical OR of system service flags (SYSTEM_SERV_FLAG_REBOOT, SYSTEM_SERV_FLAG_FACTORY_RESET, SYSTEM_SERV_FLAG_WIFI_RESET) as required or SYSTEM_SERV_FLAGS_ALL.
+* ``reboot_seconds`` Time in seconds after which the device should reboot. Recommended value: 2
+* ``reset_seconds`` Time in seconds after which the device should reset(Wi-Fi or Factory). Recommended value: 2
+* ``reset_reboot_seconds`` Time in seconds after which the device should reboot after it has been reset. Zero as a value would mean there won't be any reboot after the reset. Recommended value: 2
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+RMaker.setTimeZone
+******************
+
+This API set's the timezone as a user friendly location string. Check
+`here <https://rainmaker.espressif.com/docs/time-service.html>`__ for a list of valid values.
+
+**NOTE** : default value is "Asia/Shanghai".
+
+This API comes into picture only when working with scheduling.
+
+.. code-block:: arduino
+
+    esp_err_t setTimeZone(const char *tz);
+
+* ``tz`` : Valid values as specified in documentation.
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+ESP RainMaker Node API
+-----------------------
+
+`Node` class expose API's for node.
+
+**NOTE** : my_node is the object of Node class.
+
+my_node.getNodeID
+*****************
+
+It returns the unique node_id assigned to the node. This node_id is usually the MAC address of the board.
+
+.. code-block:: arduino
+
+    char * getNodeID()
+
+* ``tz`` : Valid values as specified in documentation.
+
+This function will return
+
+1. `char *` : Pointer to a NULL terminated node_id string.
+
+my_node.getNodeInfo
+*******************
+
+It returns pointer to the node_info_t as configured during node initialization.
+
+.. code-block:: arduino
+
+    node_info_t * getNodeInfo();
+
+This function will return
+
+1. `node_info_t` : Pointer to the structure node_info_t on success.
+2. `NULL` : On failure.
+
+**ESP RainMaker node info**
+
+It has following data member
+
+1. char * name
+2. char * type
+3. char * fw_version
+4. char * model
+
+my_node.addNodeAttr
+*******************
+
+It adds a new attribute as the metadata to the node.
+
+**NOTE** : Only string values are allowed.
+
+.. code-block:: arduino
+
+    esp_err_t addNodeAttr(const char *attr_name, const char *val);
+
+* ``attr_name`` : Name of the attribute
+* ``val`` : Value of the attribute
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+my_node.addDevice
+*****************
+
+It adds a device to the node.
+
+**NOTE** :
+
+- This is the mandatory API to register device to node.
+- Single Node can have multiple devices.
+- Device name should be unique for each device.
+
+.. code-block:: arduino
+
+    esp_err_t addDevice(Device device);
+
+* ``device`` : Device object
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+my_node.removeDevice
+********************
+
+It removes a device from the node.
+
+.. code-block:: arduino
+
+    esp_err_t removeDevice(Device device);
+
+* ``device`` : Device object
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+ESP RainMaker Device API
+-----------------------------
+
+`Device` class expose API's for virtual devices on the node.
+Parameterized constructor is defined which creates the virtual device on the node. Using Device class object you can create your own device.
+
+**NOTE** : my_device is the object of Device class
+
+.. code-block:: arduino
+
+    Device my_device(const char *dev_name, const char *dev_type, void *priv_data);
+
+* ``dev_name`` : Unique device name
+* ``dev_type`` : Optional device type. It can be kept NULL.
+    * Standard Device Types
+        * ESP_RMAKER_DEVICE_SWITCH
+        * ESP_RMAKER_DEVICE_LIGHTBULB
+        * ESP_RMAKER_DEVICE_FAN
+        * ESP_RMAKER_DEVICE_TEMP_SENSOR
+* ``priv_data`` : Private data associated with the device. This will be passed to the callbacks.
+
+**NOTE** : This created device should be added to the node using ``my_node.addDevice(my_device);``
+
+- Sample example
+
+.. code-block:: arduino
+
+    Device my_device("Switch");
+    Device my_device("Switch1", NULL, NULL);
+
+- Here, dev_name is compulsory, rest are optional.
+- Node can have multiple device, each device should have unique device name.
+
+**Standard Devices**
+
+- Classes are defined for the standard devices.
+- Creating object of these class creates the standard device with default parameters to it.
+- Class for standard devices
+    * Switch
+    * LightBulb
+    * TemperatureSensor
+    * Fan
+
+.. code-block:: arduino
+
+    Switch my_switch(const char *dev_name, void *priv_data, bool power);
+
+* ``dev_name`` : Unique device name by default it is "switch" for switch device.
+* ``priv_data`` : Private data associated with the device. This will be passed to the callbacks.
+* ``power`` : It is the value that can be set for primary parameter.
+
+Sample example for standard device.
+
+.. code-block:: arduino
+
+    Switch switch1;
+    Switch switch2("switch2", NULL, true);
+
+- `"switch2"` : Name for standard device.
+- `NULL` : Private data for the device, which will be used in callback.
+- `true` : Default value for the primary param, in case of switch it is power.
+
+**NOTE**: No parameter are compulsory for standard devices. However if you are creating two objects of same standard class then in that case you will have to set the device name, if not then both device will have same name which is set by default, hence device will not get create. *Device name should be unique for each device.*
+
+my_device.getDeviceName
+***********************
+
+It returns the name of the Device.
+
+.. code-block:: arduino
+
+    const char * getDeviceName();
+
+* ``device`` : Device object
+
+This function will return
+
+- `char *`: Returns Device name.
+
+**NOTE**: Each device on the node should have unique device name.
+
+my_device.addDeviceAttr
+***********************
+
+It adds attribute to the device. Device attributes are reported only once after a boot-up as part of the node configuration. Eg. Serial Number
+
+.. code-block:: arduino
+
+    esp_err_t addDeviceAttr(const char *attr_name, const char *val);
+
+* ``attr_name`` : Name of the attribute
+* ``val`` : Value of the attribute
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case  of failure
+
+my_device.deleteDevice
+**********************
+
+It deletes the device created using parameterized constructor.
+
+This device should be first removed from the node using `my_node.removeDevice(my_device)`.
+
+.. code-block:: arduino
+
+    esp_err_t deleteDevice();
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+my_device.addXParam
+*******************
+
+It adds standard parameter to the device.
+
+**NOTE**: X is the default name by which parameter is referred, you can specify your own name to each parameter.
+
+- Eg. `my_device.addPowerParam(true)` here power parameter is referred with name Power.
+- Eg. `my_device.addHueParam(12)` here hue parameter is referred with name Hue.
+
+You can specify your own name to each parameter
+
+- Eg. `my_device.addNameParam("NickName")` here name parameter is referred with name NickName.
+- Eg. `my_device.addPowerParam(true, "FanPower")` here power parameter is referred with name FanPower.
+
+**Standard Parameters**
+
+* These are the standard parameters.
+    * Name : ESP_RMAKER_DEF_NAME_PARAM
+    * Power : ESP_RMAKER_DEF_POWER_NAME
+    * Brightness : ESP_RMAKER_DEF_BRIGHTNESS_NAME
+    * Hue : ESP_RMAKER_DEF_HUE_NAME
+    * Saturation : ESP_RMAKER_DEF_SATURATION_NAME
+    * Intensity : ESP_RMAKER_DEF_INTENSITY_NAME
+    * CCT : ESP_RMAKER_DEF_CCT_NAME
+    * Direction : ESP_RMAKER_DEF_DIRECTION_NAME
+    * Speed : ESP_RMAKER_DEF_SPEED_NAME
+    * Temperature : ESP_RMAKER_DEF_TEMPERATURE_NAME
+
+.. code-block:: arduino
+
+    esp_err_t addNameParam(const char *param_name = ESP_RMAKER_DEF_NAME_PARAM);
+    esp_err_t addPowerParam(bool val, const char *param_name = ESP_RMAKER_DEF_POWER_NAME);
+    esp_err_t addBrightnessParam(int val, const char *param_name = ESP_RMAKER_DEF_BRIGHTNESS_NAME);
+    esp_err_t addHueParam(int val, const char *param_name = ESP_RMAKER_DEF_HUE_NAME);
+    esp_err_t addSaturationParam(int val, const char *param_name = ESP_RMAKER_DEF_SATURATION_NAME);
+    esp_err_t addIntensityParam(int val, const char *param_name = ESP_RMAKER_DEF_INTENSITY_NAME);
+    esp_err_t addCCTParam(int val, const char *param_name = ESP_RMAKER_DEF_CCT_NAME);
+    esp_err_t addDirectionParam(int val, const char *param_name = ESP_RMAKER_DEF_DIRECTION_NAME);
+    esp_err_t addSpeedParam(int val, const char *param_name = ESP_RMAKER_DEF_SPEED_NAME);
+    esp_err_t addTempratureParam(float val, const char *param_name = ESP_RMAKER_DEF_TEMPERATURE_NAME);
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+**NOTE** : Care should be taken while accessing name of parameter. Above mentioned are the two ways using which default name of parameters can be accessed. Either LHS or RHS.
+
+my_device.assignPrimaryParam
+****************************
+
+It assigns a parameter (already added using addXParam() or addParam()) as a primary parameter, which can be used by clients (phone apps specifically) to give prominence to it.
+
+.. code-block:: arduino
+
+    esp_err_t assignPrimaryParam(param_handle_t *param);
+
+* ``param`` : Handle of the parameter. It is obtained using `my_device.getParamByName()`.
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+my_device.getParamByName
+************************
+
+.. code-block:: arduino
+
+    param_handle_t * getParamByName(const char *param_name);
+
+* ``param_name`` : It is the name of the parameter which was added using addXparam() or addParam().
+
+This function will return object of the parameter.
+
+my_device.addParam
+******************
+
+It allows user to add custom parameter to the device created using `Param` class.
+
+.. code-block:: arduino
+
+    esp_err_t addParam(Param parameter);
+
+* ``parameter`` : Object of Param
+
+This function will return
+
+1.`ESP_OK` : On success
+2. Error in case of failure
+
+**NOTE**: Param class exposes API's to create the custom parameter.
+
+my_device.updateAndReportParam
+******************************
+
+It updates the parameter assosicated with particular device on ESP RainMaker cloud.
+
+.. code-block:: arduino
+
+    esp_err_t updateAndReportParam(const char *param_name, value);
+
+* ``param_name`` : Name of the parameter
+* ``value`` : Value to be updated. It can be int, bool, char * , float.
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+my_device.addCb
+***************
+
+It registers read and write callback for the device which will be invoked as per requests received from the cloud (or other paths as may be added in future).
+
+.. code-block:: arduino
+
+    void addCb(deviceWriteCb write_cb, deviceReadCb read_cb);
+
+* ``write_cb`` : Function with signature
+        func_name(Device \*device, Param \*param, const param_val_t val, void \*priv_data, write_ctx_t \*ctx);
+* ``read_cb`` : Function with signature
+        func_name(Device \*device, Param \*param, void \*priv_data, read_ctx_t \*ctx);
+
+**Parameters**
+
+**param_val_t val**
+
+Value can be accessed as below
+
+1. `bool` : val.val.b
+2. `integer` : val.val.i
+3. `float` : val.val.f
+4. `char *` : val.val.s
+
+ESP RainMaker Param API
+-----------------------
+
+`Param` class expose API's for creating custom parameters for the devices and report and update values associated with parameter to the ESP RainMaker cloud. Parameterized constructor is defined which creates custom parameter.
+
+**NOTE** : `my_param` is the object of Param class.
+
+.. code-block:: arduino
+
+    Param my_param(const char *param_name, const char *param_type, param_val_t val, uint8_t properties);
+
+* ``param_name`` : Name of the parameter
+* ``param_type`` : Type of the parameter. It is optional can be kept NULL.
+* ``val`` : Define the default value for the parameter. It should be defined using `value(int ival)` , `value(bool bval)` , `value(float fval)` , `value(char *sval)`.
+* ``properties`` : Properties of the parameter, which will be a logical OR of flags.
+    * Flags
+        * PROP_FLAG_WRITE
+        * PROP_FLAG_READ
+        * PROP_FLAG_TIME_SERIES
+        * PROP_FLAG_PERSIST
+
+Sample example :
+
+.. code-block:: arduino
+
+    Param my_param(const char *param_name, const char *param_type, param_val_t val, uint8_t properties);
+    Param my_param("bright", NULL, value(30), PROP_FLAG_READ | PROP_FLAG_WRITE | PROP_FLAG_PERSIST);
+
+**NOTE** : Parameter created using Param class should be added to the device using `my_device.addParam(my_param);`
+
+my_param.addUIType
+******************
+
+Add a UI type to the parameter. This will be used by the Phone apps (or other clients) to render appropriate UI for the given parameter. Please refer the RainMaker documentation
+`here <https://rainmaker.espressif.com/docs/standard-types.html#ui-elements>`__ for supported UI Types.
+
+.. code-block:: arduino
+
+    esp_err_t addUIType(const char *ui_type);
+
+* ``ui_type`` : String describing the UI Type.
+    * Standard UI Types
+        * ESP_RMAKER_UI_TOGGLE
+        * ESP_RMAKER_UI_SLIDER
+        * ESP_RMAKER_UI_DROPDOWN
+        * ESP_RMAKER_UI_TEXT
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+my_param.addBounds
+******************
+
+Add bounds for an integer/float parameter. This can be used to add bounds (min/max values) for a given integer/float parameter. Eg. brightness will have bounds as 0 and 100 if it is a percentage.
+
+.. code-block:: arduino
+
+    esp_err_t addBounds(param_val_t min, param_val_t max, param_val_t step);
+
+* ``min`` : Minimum value
+* ``max`` : Maximum value
+* ``step`` : step Minimum stepping
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+`Sample example : my_param.addBounds(value(0), value(100), value(5));`
+
+my_param.updateAndReport
+************************
+
+It updates the parameter and report it to ESP RainMaker cloud. This is called in callback.
+
+.. code-block:: arduino
+
+    esp_err_t updateAndReport(param_val_t val);
+
+* ``val`` : New value of the parameter
+
+This function will return
+
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+**NOTE**:
+
+- This API should always be called inside device write callback, if you aimed at updating n reporting parameter values, changed via RainMaker Client (Phone App), to the ESP RainMaker cloud.
+- If not called then parameter values will not be updated to the ESP RainMaker cloud.
+
+printQR
+*******
+
+This API displays QR code, which is used in provisioning.
+
+.. code-block:: arduino
+
+    printQR(const char *serv_name, const char *pop, const char *transport);
+
+* ``name`` : Service name used in provisioning API.
+* ``pop`` : Proof of possession used in provisioning API.
+* ``transport`` :
+    1. `softap` : In case of provisioning using SOFTAP.
+    2. `ble` : In case of provisioning using BLE.
+
+RMakerFactoryReset
+******************
+
+Reset the device to factory defaults.
+
+.. code-block:: arduino
+
+    RMakerFactoryReset(int seconds);
+
+* ``seconds`` : Time in seconds after which the chip should reboot after doing a factory reset.
+
+RMakerWiFiReset
+***************
+
+Reset Wi-Fi credentials.
+
+.. code-block:: arduino
+
+    RMakerWiFiReset(int seconds);
+
+* ``seconds`` : Time in seconds after which the chip should reboot after doing a Wi-Fi reset.
diff --git a/docs/en/api/reset_reason.rst b/docs/en/api/reset_reason.rst
new file mode 100644
index 00000000000..813216909b0
--- /dev/null
+++ b/docs/en/api/reset_reason.rst
@@ -0,0 +1,19 @@
+############
+Reset Reason
+############
+
+About
+-----
+
+.. note:: This is a work in progress project and this section is still missing. If you want to contribute, please see the `Contributions Guide <../contributing.html>`_.
+
+Example
+-------
+
+To get started with Reset Reason, you can try:
+
+Reset Reason
+************
+
+.. literalinclude:: ../../../libraries/ESP32/examples/ResetReason/ResetReason/ResetReason.ino
+    :language: arduino
diff --git a/docs/en/api/rmt.rst b/docs/en/api/rmt.rst
new file mode 100644
index 00000000000..6f87054a9c2
--- /dev/null
+++ b/docs/en/api/rmt.rst
@@ -0,0 +1,24 @@
+###
+RMT
+###
+
+About
+-----
+
+.. note:: This is a work in progress project and this section is still missing. If you want to contribute, please see the `Contributions Guide <../contributing.html>`_.
+
+Remote Control Transceiver (RMT) peripheral was designed to act as an infrared transceiver.
+
+Example
+-------
+
+To get started with RMT, you can try:
+
+RMT Write RGB LED
+*****************
+
+.. literalinclude:: ../../../libraries/ESP32/examples/RMT/RMTWrite_RGB_LED/RMTWrite_RGB_LED.ino
+    :language: arduino
+
+
+Complete list of `RMT examples <https://github.com/espressif/arduino-esp32/tree/master/libraries/ESP32/examples/RMT>`_.
diff --git a/docs/en/api/sdio.rst b/docs/en/api/sdio.rst
new file mode 100644
index 00000000000..d057e71db3a
--- /dev/null
+++ b/docs/en/api/sdio.rst
@@ -0,0 +1,8 @@
+####
+SDIO
+####
+
+About
+-----
+
+.. note:: This peripheral is not supported yet by the Arduino API's.
diff --git a/docs/en/api/sdmmc.rst b/docs/en/api/sdmmc.rst
new file mode 100644
index 00000000000..f6c9db77101
--- /dev/null
+++ b/docs/en/api/sdmmc.rst
@@ -0,0 +1,22 @@
+######
+SD MMC
+######
+
+About
+-----
+
+.. note:: This is a work in progress project and this section is still missing. If you want to contribute, please see the `Contributions Guide <../contributing.html>`_.
+
+Example
+-------
+
+To get started with SD_MMC, you can try:
+
+SDMMC Test
+**********
+
+.. literalinclude:: ../../../libraries/SD_MMC/examples/SDMMC_Test/SDMMC_Test.ino
+    :language: arduino
+
+
+Complete list of `SD MMC examples <https://github.com/espressif/arduino-esp32/tree/master/libraries/SD_MMC/examples>`_.
diff --git a/docs/en/api/sigmadelta.rst b/docs/en/api/sigmadelta.rst
new file mode 100644
index 00000000000..d3035af2938
--- /dev/null
+++ b/docs/en/api/sigmadelta.rst
@@ -0,0 +1,78 @@
+##########
+SigmaDelta
+##########
+
+About
+-----
+
+ESP32 provides a second-order sigma delta modulation module and 8 (4 for ESP32-C3)
+independent modulation channels. The channels are capable to output 1-bit
+signals (output index: 100 ~ 107) with sigma delta modulation.
+
+========= =============================
+ESP32 SoC Number of SigmaDelta channels
+========= =============================
+ESP32     8
+ESP32-S2  8
+ESP32-S3  8
+ESP32-C3  4
+ESP32-C6  4
+ESP32-H2  4
+========= =============================
+
+Arduino-ESP32 SigmaDelta API
+----------------------------
+
+sigmaDeltaAttach
+****************
+
+This function is used to set up the SigmaDelta channel with the selected frequency and attach it to the selected pin.
+
+.. code-block:: arduino
+
+    bool sigmaDeltaAttach(uint8_t pin, uint32_t freq);
+
+* ``pin`` select GPIO pin.
+* ``freq`` select frequency.
+
+  * range is 1-14 bits (1-20 bits for ESP32).
+
+This function returns ``true`` if the configuration was successful.
+If ``false`` is returned, an error occurred and the SigmaDelta channel was not configured.
+
+sigmaDeltaWrite
+***************
+
+This function is used to set duty for the SigmaDelta pin.
+
+.. code-block:: arduino
+
+    bool sigmaDeltaWrite(uint8_t pin, uint8_t duty);
+
+* ``pin`` selects the GPIO pin.
+* ``duty`` selects the duty to be set for selected pin.
+
+This function returns ``true`` if setting the duty was successful.
+If ``false`` is returned, error occurs and duty was not set.
+
+sigmaDeltaDetach
+****************
+
+This function is used to detach a pin from SigmaDelta and deinitialize the channel that was attached to the pin.
+
+.. code-block:: arduino
+
+    bool sigmaDeltaDetach(uint8_t pin);
+
+* ``pin`` select GPIO pin.
+
+This function returns ``true`` if detaching was successful.
+If ``false`` is returned, an error occurred and pin was not detached.
+
+Example Applications
+********************
+
+Here is example use of SigmaDelta:
+
+.. literalinclude:: ../../../libraries/ESP32/examples/AnalogOut/SigmaDelta/SigmaDelta.ino
+    :language: arduino
diff --git a/docs/en/api/spi.rst b/docs/en/api/spi.rst
new file mode 100644
index 00000000000..c82b0de5ccb
--- /dev/null
+++ b/docs/en/api/spi.rst
@@ -0,0 +1,26 @@
+###
+SPI
+###
+
+About
+-----
+
+For some APIs, the reference to be used is the same as the Arduino Core.
+
+Arduino API Reference
+---------------------
+
+`SPI Reference <https://www.arduino.cc/reference/en/language/functions/communication/spi/>`_
+
+`SPI Description <https://docs.arduino.cc/learn/communication/spi>`_
+
+Example
+-------
+
+To get started with SPI, you can try:
+
+SPI Multiple Buses
+******************
+
+.. literalinclude:: ../../../libraries/SPI/examples/SPI_Multiple_Buses/SPI_Multiple_Buses.ino
+    :language: arduino
diff --git a/docs/en/api/timer.rst b/docs/en/api/timer.rst
new file mode 100644
index 00000000000..2637f9eec1d
--- /dev/null
+++ b/docs/en/api/timer.rst
@@ -0,0 +1,224 @@
+#####
+Timer
+#####
+
+About
+-----
+
+The ESP32 SoCs contains from 2 to 4 hardware timers.
+They are all 64-bit (54-bit for ESP32-C3) generic timers based on 16-bit pre-scalers and 64-bit (54-bit for ESP32-C3)
+up / down counters which are capable of being auto-reloaded.
+
+========= ================
+ESP32 SoC Number of timers
+========= ================
+ESP32     4
+ESP32-S2  4
+ESP32-S3  4
+ESP32-C3  2
+ESP32-C6  2
+ESP32-H2  2
+========= ================
+
+Arduino-ESP32 Timer API
+-----------------------
+
+timerBegin
+**********
+
+This function is used to configure the timer. After successful setup the timer will automatically start.
+
+.. code-block:: arduino
+
+    hw_timer_t * timerBegin(uint32_t frequency);
+
+* ``frequency`` select timer frequency in Hz. Sets how quickly the timer counter is “ticking”.
+
+This function will return ``timer`` structure if configuration is successful.
+If ``NULL`` is returned, error occurs and the timer was not configured.
+
+timerEnd
+********
+
+This function is used to end timer.
+
+.. code-block:: arduino
+
+    void timerEnd(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+timerStart
+**********
+
+This function is used to start counter of the timer.
+
+.. code-block:: arduino
+
+    void timerStart(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+timerStop
+*********
+
+This function is used to stop counter of the timer.
+
+.. code-block:: arduino
+
+    void timerStop(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+timerRestart
+************
+
+This function is used to restart counter of the timer.
+
+.. code-block:: arduino
+
+    void timerRestart(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+timerWrite
+**********
+
+This function is used to set counter value of the timer.
+
+.. code-block:: arduino
+
+    void timerWrite(hw_timer_t * timer, uint64_t val);
+
+* ``timer`` timer struct.
+* ``val`` counter value to be set.
+
+timerRead
+*********
+
+This function is used to read counter value of the timer.
+
+.. code-block:: arduino
+
+    uint64_t timerRead(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+This function will return ``counter value`` of the timer.
+
+timerReadMicros
+***************
+
+This function is used to read counter value in microseconds of the timer.
+
+.. code-block:: arduino
+
+    uint64_t timerReadMicros(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+This function will return ``counter value`` of the timer in microseconds.
+
+timerReadMillis
+***************
+
+This function is used to read counter value in milliseconds of the timer.
+
+.. code-block:: arduino
+
+    uint64_t timerReadMillis(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+This function will return ``counter value`` of the timer in milliseconds.
+
+timerReadSeconds
+****************
+
+This function is used to read counter value in seconds of the timer.
+
+.. code-block:: arduino
+
+    double timerReadSeconds(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+This function will return ``counter value`` of the timer in seconds.
+
+timerGetFrequency
+*****************
+
+This function is used to get resolution in Hz of the timer.
+
+.. code-block:: arduino
+
+    uint16_t timerGetFrequency(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+This function will return ``frequency`` in Hz of the timer.
+
+timerAttachInterrupt
+********************
+
+This function is used to attach interrupt to timer.
+
+.. code-block:: arduino
+
+    void timerAttachInterrupt(hw_timer_t * timer, void (*userFunc)(void));
+
+* ``timer`` timer struct.
+* ``userFunc`` function to be called when interrupt is triggered.
+
+timerAttachInterruptArg
+***********************
+
+This function is used to attach interrupt to timer using arguments.
+
+.. code-block:: arduino
+
+    void timerAttachInterruptArg(hw_timer_t * timer, void (*userFunc)(void*), void * arg);
+
+* ``timer`` timer struct.
+* ``userFunc`` function to be called when interrupt is triggered.
+* ``arg`` pointer to the interrupt arguments.
+
+timerDetachInterrupt
+********************
+
+This function is used to detach interrupt from timer.
+
+.. code-block:: arduino
+
+    void timerDetachInterrupt(hw_timer_t * timer);
+
+* ``timer`` timer struct.
+
+timerAlarm
+**********
+
+This function is used to configure alarm value and autoreload of the timer. Alarm is automatically enabled.
+
+.. code-block:: arduino
+
+    void timerAlarm(hw_timer_t * timer, uint64_t alarm_value, bool autoreload, uint64_t reload_count);
+
+* ``timer`` timer struct.
+* ``alarm_value`` alarm value to generate event.
+* ``autoreload`` enabled/disabled autorealod.
+* ``reload_count`` number of autoreloads (0 = unlimited). Has no effect if autorealod is disabled.
+
+Example Applications
+********************
+
+There are 2 examples uses of Timer:
+
+Repeat timer example:
+
+.. literalinclude:: ../../../libraries/ESP32/examples/Timer/RepeatTimer/RepeatTimer.ino
+    :language: arduino
+
+Watchdog timer example:
+
+.. literalinclude:: ../../../libraries/ESP32/examples/Timer/WatchdogTimer/WatchdogTimer.ino
+    :language: arduino
diff --git a/docs/en/api/touch.rst b/docs/en/api/touch.rst
new file mode 100644
index 00000000000..d4a905f86e8
--- /dev/null
+++ b/docs/en/api/touch.rst
@@ -0,0 +1,142 @@
+#####
+TOUCH
+#####
+
+About
+-----
+
+Touch sensor is a peripheral, that has an internal oscillator circuit and it measures charge/discharge frequency over a fixed period of time on respective GPIO pins.
+Therefore these touch sensors are also known as capacitive sensors. For example, if you touch any of these pins, finger electrical charge will change this number of cycles,
+by changing the RC circuit attached to the touch sensor. The TouchRead() will return the number of cycles (charges/discharges) in a certain time (meas).
+The change of this count will be used to validate if a touch has happened or not. These pins can be easily integrated into capacitive pads, and replace mechanical buttons.
+
+.. note:: Touch peripheral is not present in every SoC. Refer to datasheet of each chip for more info.
+
+Arduino-ESP32 TOUCH API
+-----------------------
+
+TOUCH common API
+****************
+
+touchRead
+^^^^^^^^^
+
+This function gets the touch sensor data. Each touch sensor has a counter to count the number of charge/discharge cycles. When the pad is ‘touched’,
+the value in the counter will change because of the larger equivalent capacitance. The change of the data determines if the pad has been touched or not.
+
+.. code-block:: arduino
+
+    touch_value_t touchRead(uint8_t pin);
+
+* ``pin`` GPIO pin to read TOUCH value
+
+This function will return touch pad value as uint16_t (ESP32) or uint32_t (ESP32-S2/S3).
+
+touchSetCycles
+^^^^^^^^^^^^^^
+
+This function is used to set cycles that measurement operation takes. The result from touchRead, threshold and detection accuracy depend on these values.
+The defaults are setting touchRead to take ~0.5 ms.
+
+.. code-block:: arduino
+
+    void touchSetCycles(uint16_t measure, uint16_t sleep);
+
+* ``measure`` Sets the time that it takes to measure touch sensor value
+* ``sleep`` Sets waiting time before next measure cycle
+
+touchAttachInterrupt
+^^^^^^^^^^^^^^^^^^^^
+
+This function is used to attach interrupt to the touch pad. The function will be called if a touch sensor value falls below the given
+threshold for ESP32 or rises above the given threshold for ESP32-S2/S3. To determine a proper threshold value between touched and untouched state,
+use touchRead() function.
+
+.. code-block:: arduino
+
+    void touchAttachInterrupt(uint8_t pin, void (*userFunc)(void), touch_value_t threshold);
+
+* ``pin`` GPIO TOUCH pad pin
+* ``userFunc`` Function to be called when interrupt is triggered
+* ``threshold`` Sets the threshold when to call interrupt
+
+touchAttachInterruptArg
+^^^^^^^^^^^^^^^^^^^^^^^
+
+This function is used to attach interrupt to the touch pad. In the function called by ISR you have the given arguments available.
+
+.. code-block:: arduino
+
+    void touchAttachInterruptArg(uint8_t pin, void (*userFunc)(void*), void *arg, touch_value_t threshold);
+
+* ``pin`` GPIO TOUCH pad pin
+* ``userFunc`` Function to be called when interrupt is triggered
+* ``arg`` Sets arguments to the interrupt
+* ``threshold`` Sets the threshold when to call interrupt
+
+touchDetachInterrupt
+^^^^^^^^^^^^^^^^^^^^
+
+This function is used to detach interrupt from the touch pad.
+
+.. code-block:: arduino
+
+    void touchDetachInterrupt(uint8_t pin);
+
+* ``pin`` GPIO TOUCH pad pin.
+
+touchSleepWakeUpEnable
+^^^^^^^^^^^^^^^^^^^^^^
+
+This function is used to setup touch pad as the wake up source from the deep sleep.
+
+.. note:: ESP32-S2 and ESP32-S3 only support one sleep wake up touch pad.
+
+.. code-block:: arduino
+
+    void touchSleepWakeUpEnable(uint8_t pin, touch_value_t threshold);
+
+* ``pin`` GPIO TOUCH pad pin
+* ``threshold`` Sets the threshold when to wake up
+
+TOUCH API specific for ESP32 chip (TOUCH_V1)
+********************************************
+
+touchInterruptSetThresholdDirection
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This function is used to tell the driver if it shall activate the interrupt if the sensor is lower or higher than
+the threshold value. Default is lower.
+
+.. code-block:: arduino
+
+    void touchInterruptSetThresholdDirection(bool mustbeLower);
+
+TOUCH API specific for ESP32-S2 and ESP32-S3 chip (TOUCH_V2)
+************************************************************
+
+touchInterruptGetLastStatus
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This function is used get the latest ISR status for the touch pad.
+
+.. code-block:: arduino
+
+    bool touchInterruptGetLastStatus(uint8_t pin);
+
+This function returns true if the touch pad has been and continues pressed or false otherwise.
+
+Example Applications
+********************
+
+Example of reading the touch sensor.
+
+.. literalinclude:: ../../../libraries/ESP32/examples/Touch/TouchRead/TouchRead.ino
+    :language: arduino
+
+A usage example for the touch interrupts.
+
+.. literalinclude:: ../../../libraries/ESP32/examples/Touch/TouchInterrupt/TouchInterrupt.ino
+    :language: arduino
+
+More examples can be found in our repository -> `Touch examples <https://github.com/espressif/arduino-esp32/tree/master/libraries/ESP32/examples/Touch>`_.
diff --git a/docs/en/api/usb.rst b/docs/en/api/usb.rst
new file mode 100644
index 00000000000..8e5388a4d0e
--- /dev/null
+++ b/docs/en/api/usb.rst
@@ -0,0 +1,331 @@
+#######
+USB API
+#######
+
+.. note:: This feature is only supported on ESP chips that have USB peripheral, like the ESP32-S2 and ESP32-S3. Some chips, like the ESP32-C3 include native CDC+JTAG peripheral that is not covered here.
+
+About
+-----
+
+The **Universal Serial Bus** is a widely used peripheral to exchange data between devices. USB was introduced on the ESP32, supporting both device and host mode.
+
+To learn about the USB, see the `USB.org`_ for developers.
+
+USB as Device
+*************
+
+In the device mode, the ESP32 acts as an USB device, like a mouse or keyboard to be connected to a host device, like your computer or smartphone.
+
+USB as Host
+***********
+
+The USB host mode, you can connect devices on the ESP32, like external modems, mouse and keyboards.
+
+.. note:: This mode is still under development for the ESP32.
+
+API Description
+---------------
+
+This is the common USB API description.
+
+For more supported USB classes implementation, see the following sections:
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Classes:
+
+   USB CDC <usb_cdc>
+   USB MSC <usb_msc>
+
+USB Common
+**********
+
+These are the common APIs for the USB driver.
+
+onEvent
+^^^^^^^
+
+Event handling function to set the callback.
+
+.. code-block:: arduino
+
+    void onEvent(esp_event_handler_t callback);
+
+Event handling function for the specific event.
+
+.. code-block:: arduino
+
+    void onEvent(arduino_usb_event_t event, esp_event_handler_t callback);
+
+Where ``event`` can be:
+
+* ARDUINO_USB_ANY_EVENT
+* ARDUINO_USB_STARTED_EVENT
+* ARDUINO_USB_STOPPED_EVENT
+* ARDUINO_USB_SUSPEND_EVENT
+* ARDUINO_USB_RESUME_EVENT
+* ARDUINO_USB_MAX_EVENT
+
+VID
+^^^
+
+Set the Vendor ID. This 16 bits identification is used to identify the company that develops the product.
+
+.. note:: You can't define your own VID. If you need your own VID, you need to buy one. See https://www.usb.org/getting-vendor-id for more details.
+
+.. code-block:: arduino
+
+    bool VID(uint16_t v);
+
+
+Get the Vendor ID.
+
+.. code-block:: arduino
+
+    uint16_t VID(void);
+
+Returns the Vendor ID. The default value for the VID is: ``0x303A``.
+
+PID
+^^^
+
+Set the Product ID. This 16 bits identification is used to identify the product.
+
+.. code-block:: arduino
+
+    bool PID(uint16_t p);
+
+Get the Product ID.
+
+.. code-block:: arduino
+
+    uint16_t PID(void);
+
+Returns the Product ID. The default PID is: ``0x0002``.
+
+firmwareVersion
+^^^^^^^^^^^^^^^
+
+Set the firmware version. This is a 16 bits unsigned value.
+
+.. code-block:: arduino
+
+    bool firmwareVersion(uint16_t version);
+
+Get the firmware version.
+
+.. code-block:: arduino
+
+    uint16_t firmwareVersion(void);
+
+Return the 16 bits unsigned value. The default value is: ``0x100``.
+
+usbVersion
+^^^^^^^^^^
+
+Set the USB version.
+
+.. code-block:: arduino
+
+    bool usbVersion(uint16_t version);
+
+Get the USB version.
+
+.. code-block:: arduino
+
+    uint16_t usbVersion(void);
+
+Return the USB version. The default value is: ``0x200`` (USB 2.0).
+
+usbPower
+^^^^^^^^
+
+Set the USB power as mA (current).
+
+.. note:: This configuration does not change the physical power output. This is only used for the USB device information.
+
+.. code-block:: arduino
+
+    bool usbPower(uint16_t mA);
+
+Get the USB power configuration.
+
+.. code-block:: arduino
+
+    uint16_t usbPower(void);
+
+Return the current in mA. The default value is: ``0x500`` (500 mA).
+
+usbClass
+^^^^^^^^
+
+Set the USB class.
+
+.. code-block:: arduino
+
+    bool usbClass(uint8_t _class);
+
+Get the USB class.
+
+.. code-block:: arduino
+
+    uint8_t usbClass(void);
+
+Return the USB class. The default value is: ``TUSB_CLASS_MISC``.
+
+usbSubClass
+^^^^^^^^^^^
+
+Set the USB sub-class.
+
+.. code-block:: arduino
+
+    bool usbSubClass(uint8_t subClass);
+
+Get the USB sub-class.
+
+.. code-block:: arduino
+
+    uint8_t usbSubClass(void);
+
+Return the USB sub-class. The default value is: ``MISC_SUBCLASS_COMMON``.
+
+usbProtocol
+^^^^^^^^^^^
+
+Define the USB protocol.
+
+.. code-block:: arduino
+
+    bool usbProtocol(uint8_t protocol);
+
+Get the USB protocol.
+
+.. code-block:: arduino
+
+    uint8_t usbProtocol(void);
+
+Return the USB protocol. The default value is: ``MISC_PROTOCOL_IAD``
+
+usbAttributes
+^^^^^^^^^^^^^
+
+Set the USB attributes.
+
+.. code-block:: arduino
+
+    bool usbAttributes(uint8_t attr);
+
+Get the USB attributes.
+
+.. code-block:: arduino
+
+    uint8_t usbAttributes(void);
+
+Return the USB attributes. The default value is: ``TUSB_DESC_CONFIG_ATT_SELF_POWERED``
+
+webUSB
+^^^^^^
+
+This function is used to enable the ``webUSB`` functionality.
+
+.. code-block:: arduino
+
+    bool webUSB(bool enabled);
+
+This function is used to get the ``webUSB`` setting.
+
+.. code-block:: arduino
+
+    bool webUSB(void);
+
+Return the ``webUSB`` setting (`Enabled` or `Disabled`)
+
+productName
+^^^^^^^^^^^
+
+This function is used to define the product name.
+
+.. code-block:: arduino
+
+    bool productName(const char * name);
+
+This function is used to get the product's name.
+
+.. code-block:: arduino
+
+    const char * productName(void);
+
+manufacturerName
+^^^^^^^^^^^^^^^^
+
+This function is used to define the manufacturer name.
+
+.. code-block:: arduino
+
+    bool manufacturerName(const char * name);
+
+This function is used to get the manufacturer's name.
+
+.. code-block:: arduino
+
+    const char * manufacturerName(void);
+
+serialNumber
+^^^^^^^^^^^^
+
+This function is used to define the serial number.
+
+.. code-block:: arduino
+
+    bool serialNumber(const char * name);
+
+This function is used to get the serial number.
+
+.. code-block:: arduino
+
+    const char * serialNumber(void);
+
+The default serial number is: ``0``.
+
+webUSBURL
+^^^^^^^^^
+
+This function is used to define the ``webUSBURL``.
+
+.. code-block:: arduino
+
+    bool webUSBURL(const char * name);
+
+This function is used to get the ``webUSBURL``.
+
+.. code-block:: arduino
+
+    const char * webUSBURL(void);
+
+The default ``webUSBURL`` is: https://docs.espressif.com/projects/arduino-esp32/en/latest/_static/webusb.html
+
+enableDFU
+^^^^^^^^^
+
+This function is used to enable the DFU capability.
+
+.. code-block:: arduino
+
+    bool enableDFU();
+
+begin
+^^^^^
+
+This function is used to start the peripheral using the default configuration.
+
+.. code-block:: arduino
+
+    bool begin();
+
+Example Code
+------------
+
+There are a collection of USB device examples on the project GitHub, including Firmware MSC update, USB CDC, HID and composite device.
+
+.. _USB.org: https://www.usb.org/developers
diff --git a/docs/en/api/usb_cdc.rst b/docs/en/api/usb_cdc.rst
new file mode 100644
index 00000000000..61e9fcdf928
--- /dev/null
+++ b/docs/en/api/usb_cdc.rst
@@ -0,0 +1,193 @@
+#######
+USB CDC
+#######
+
+About
+-----
+
+USB Communications Device Class API. This class is used to enable communication between the host and the device.
+
+This class is often used to enable serial communication and can be used to flash the firmware on the ESP32 without the external USB to Serial chip.
+
+APIs
+****
+
+onEvent
+^^^^^^^
+
+Event handling functions.
+
+.. code-block:: arduino
+
+    void onEvent(esp_event_handler_t callback);
+
+.. code-block:: arduino
+
+    void onEvent(arduino_usb_cdc_event_t event, esp_event_handler_t callback);
+
+Where ``event`` can be:
+
+* ARDUINO_USB_CDC_ANY_EVENT
+* ARDUINO_USB_CDC_CONNECTED_EVENT
+* ARDUINO_USB_CDC_DISCONNECTED_EVENT
+* ARDUINO_USB_CDC_LINE_STATE_EVENT
+* ARDUINO_USB_CDC_LINE_CODING_EVENT
+* ARDUINO_USB_CDC_RX_EVENT
+* ARDUINO_USB_CDC_TX_EVENT
+* ARDUINO_USB_CDC_RX_OVERFLOW_EVENT
+* ARDUINO_USB_CDC_MAX_EVENT
+
+setRxBufferSize
+^^^^^^^^^^^^^^^
+
+The ``setRxBufferSize`` function is used to set the size of the RX buffer.
+
+.. code-block:: arduino
+
+    size_t setRxBufferSize(size_t size);
+
+setTxTimeoutMs
+^^^^^^^^^^^^^^
+
+This function is used to define the time to reach the timeout for the TX.
+
+.. code-block:: arduino
+
+    void setTxTimeoutMs(uint32_t timeout);
+
+begin
+^^^^^
+
+This function is used to start the peripheral using the default CDC configuration.
+
+.. code-block:: arduino
+
+    void begin(unsigned long baud);
+
+Where:
+
+* ``baud`` is the baud rate.
+
+end
+^^^
+
+This function will finish the peripheral as CDC and release all the allocated resources. After calling ``end`` you need to use ``begin`` again in order to initialize the USB CDC driver again.
+
+.. code-block:: arduino
+
+    void end();
+
+available
+^^^^^^^^^
+
+This function will return if there are messages in the queue.
+
+.. code-block:: arduino
+
+    int available(void);
+
+The return is the number of bytes available to read.
+
+availableForWrite
+^^^^^^^^^^^^^^^^^
+
+This function will return if the hardware is available to write data.
+
+.. code-block:: arduino
+
+    int availableForWrite(void);
+
+peek
+^^^^
+
+This function is used to ``peek`` messages from the queue.
+
+.. code-block:: arduino
+
+    int peek(void);
+
+read
+^^^^
+
+This function is used to read the bytes available.
+
+.. code-block:: arduino
+
+    size_t read(uint8_t *buffer, size_t size);
+
+Where:
+
+* ``buffer`` is the pointer to the buffer to be read.
+* ``size`` is the number of bytes to be read.
+
+write
+^^^^^
+
+This function is used to write the message.
+
+.. code-block:: arduino
+
+    size_t write(const uint8_t *buffer, size_t size);
+
+Where:
+
+* ``buffer`` is the pointer to the buffer to be written.
+* ``size`` is the number of bytes to be written.
+
+flush
+^^^^^
+
+This function is used to flush the data.
+
+.. code-block:: arduino
+
+    void flush(void);
+
+baudRate
+^^^^^^^^
+
+This function is used to get the ``baudRate``.
+
+.. code-block:: arduino
+
+    uint32_t baudRate();
+
+setDebugOutput
+^^^^^^^^^^^^^^
+
+This function will enable the debug output, usually from the `UART0`, to the USB CDC.
+
+.. code-block:: arduino
+
+    void setDebugOutput(bool);
+
+enableReboot
+^^^^^^^^^^^^
+
+This function enables the device to reboot by the DTR as RTS signals.
+
+.. code-block:: arduino
+
+    void enableReboot(bool enable);
+
+rebootEnabled
+^^^^^^^^^^^^^
+
+This function will return if the reboot is enabled.
+
+.. code-block:: arduino
+
+    bool rebootEnabled(void);
+
+Example Code
+------------
+
+Here is an example of how to use the USB CDC.
+
+USBSerial
+*********
+
+.. literalinclude:: ../../../libraries/USB/examples/USBSerial/USBSerial.ino
+    :language: arduino
+
+.. _USB.org: https://www.usb.org/developers
diff --git a/docs/en/api/usb_msc.rst b/docs/en/api/usb_msc.rst
new file mode 100644
index 00000000000..846e72e8db0
--- /dev/null
+++ b/docs/en/api/usb_msc.rst
@@ -0,0 +1,114 @@
+#######
+USB MSC
+#######
+
+About
+-----
+
+USB Mass Storage Class API. This class makes the device accessible as a mass storage device and allows you to transfer data between the host and the device.
+
+One of the examples for this mode is to flash the device by dropping the firmware binary like a flash memory device when connecting the ESP32 to the host computer.
+
+APIs
+****
+
+begin
+^^^^^
+
+This function is used to start the peripheral using the default MSC configuration.
+
+.. code-block:: arduino
+
+    bool begin(uint32_t block_count, uint16_t block_size);
+
+Where:
+
+* ``block_count`` set the disk sector count.
+* ``block_size`` set the disk sector size.
+
+This function will return ``true`` if the configuration was successful.
+
+end
+^^^
+
+This function will finish the peripheral as MSC and release all the allocated resources. After calling ``end`` you need to use ``begin`` again in order to initialize the USB MSC driver again.
+
+.. code-block:: arduino
+
+    void end();
+
+vendorID
+^^^^^^^^
+
+This function is used to define the vendor ID.
+
+.. code-block:: arduino
+
+    void vendorID(const char * vid);//max 8 chars
+
+productID
+^^^^^^^^^
+
+This function is used to define the product ID.
+
+.. code-block:: arduino
+
+    void productID(const char * pid);//max 16 chars
+
+productRevision
+^^^^^^^^^^^^^^^
+
+This function is used to define the product revision.
+
+.. code-block:: arduino
+
+    void productRevision(const char * ver);//max 4 chars
+
+mediaPresent
+^^^^^^^^^^^^
+
+Set the ``mediaPresent`` configuration.
+
+.. code-block:: arduino
+
+    void mediaPresent(bool media_present);
+
+onStartStop
+^^^^^^^^^^^
+
+Set the ``onStartStop`` callback function.
+
+.. code-block:: arduino
+
+    void onStartStop(msc_start_stop_cb cb);
+
+onRead
+^^^^^^
+
+Set the ``onRead`` callback function.
+
+.. code-block:: arduino
+
+    void onRead(msc_read_cb cb);
+
+onWrite
+^^^^^^^
+
+Set the ``onWrite`` callback function.
+
+.. code-block:: arduino
+
+    void onWrite(msc_write_cb cb);
+
+Example Code
+------------
+
+Here is an example of how to use the USB MSC.
+
+FirmwareMSC
+***********
+
+.. literalinclude:: ../../../libraries/USB/examples/FirmwareMSC/FirmwareMSC.ino
+    :language: arduino
+
+.. _USB.org: https://www.usb.org/developers
diff --git a/docs/en/api/wifi.rst b/docs/en/api/wifi.rst
new file mode 100644
index 00000000000..16d8a9d5666
--- /dev/null
+++ b/docs/en/api/wifi.rst
@@ -0,0 +1,675 @@
+#########
+Wi-Fi API
+#########
+
+About
+-----
+
+The Wi-Fi API provides support for the 802.11b/g/n protocol driver. This API includes:
+
+* Station mode (STA mode or Wi-Fi client mode). ESP32 connects to an access point
+
+* AP mode (aka Soft-AP mode or Access Point mode). Devices connect to the ESP32
+
+* Security modes (WPA2, WPA3 etc.)
+
+* Scanning for access points
+
+Working as AP
+*************
+
+In this mode, the ESP32 is configured as an Access Point (AP) and it's capable of receiving incoming connections from other devices (stations) by providing
+a Wi-Fi network.
+
+.. figure:: ../../_static/wifi_esp32_ap.png
+    :align: center
+    :width: 520
+    :figclass: align-center
+
+This mode can be used for serving an HTTP or HTTPS server inside the ESP32, for example.
+
+Working as STA
+**************
+
+The STA mode is used to connect the ESP32 to a Wi-Fi network, provided by an Access Point.
+
+.. figure:: ../../_static/wifi_esp32_sta.png
+    :align: center
+    :width: 520
+    :figclass: align-center
+
+This is the mode to be used if you want to connect your project to the Internet.
+
+API Description
+---------------
+
+Here is the description of the Wi-Fi API.
+
+Common API
+----------
+
+Here are the common APIs that are used for both modes, AP and STA.
+
+onEvent (and removeEvent)
+*************************
+
+Registers a caller-supplied function to be called when Wi-Fi events
+occur. Several forms are available.
+
+Function pointer callback taking the event ID:
+
+.. code-block:: arduino
+
+    typedef void (*WiFiEventCb)(arduino_event_id_t);
+    wifi_event_id_t onEvent(WiFiEventCb, arduino_event_id_t = ARDUINO_EVENT_MAX);
+
+Function pointer callback taking an event-ID-and-info struct:
+
+.. code-block:: arduino
+
+    typedef struct{
+        arduino_event_id_t event_id;
+        arduino_event_info_t event_info;
+    } arduino_event_t;
+
+    typedef void (*WiFiEventSysCb)(arduino_event_t *);
+    wifi_event_id_t onEvent(WiFiEventSysCb, arduino_event_id_t = ARDUINO_EVENT_MAX);
+
+Callback using ``std::function`` taking event ID and info separately:
+
+.. code-block:: arduino
+
+    typedef std::function<void(arduino_event_id_t, arduino_event_info_t)> WiFiEventFuncCb;
+    wifi_event_id_t onEvent(WiFiEventFuncCb, arduino_event_id_t = ARDUINO_EVENT_MAX);
+
+A similar set of functions are available to remove callbacks:
+
+.. code-block:: arduino
+
+    void removeEvent(WiFiEventCb, arduino_event_id_t = ARDUINO_EVENT_MAX);
+    void removeEvent(WiFiEventSysCb, arduino_event_id_t = ARDUINO_EVENT_MAX);
+    void removeEvent(wifi_event_id_t = ARDUINO_EVENT_MAX);
+
+In all cases, the subscribing function accepts an optional event type to
+invoke the callback only for that specific event; with the default
+``ARDUINO_EVENT_MAX``, the callback will be invoked for all Wi-Fi events.
+
+Any callback function is given the event type in a parameter.
+Some of the possible callback function formats also take an
+``arduino_event_info_t`` (or use ``arduino_event_t`` which includes both
+ID and info) which is a union of structs with additional information
+about different event types.
+
+See
+`WiFiGeneric.h <https://github.com/espressif/arduino-esp32/blob/master/libraries/WiFi/src/WiFiGeneric.h>`_
+for the list of event types and "info" substructures, and also see a full
+example of event handling: `events example`_.
+
+.. warning::
+
+    Event callback functions are invoked on a separate
+    `thread <https://en.wikipedia.org/wiki/Thread_(computing)>`_
+    (`FreeRTOS task <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/freertos_idf.html#tasks>`_)
+    independent of the main application thread that runs ``setup()`` and
+    ``loop()``. Callback functions must therefore be
+    `thread-safe <https://en.wikipedia.org/wiki/Thread_safety>`_;
+    they must not access shared/global variables directly without locking,
+    and must only call similarly thread-safe functions.
+
+    Some core operations like ``Serial.print()`` are thread-safe but many
+    functions are not. Notably, ``WiFi.onEvent()`` and ``WiFi.removeEvent()``
+    are not thread-safe and should never be invoked from a callback thread.
+
+setHostname (and getHostname)
+*****************************
+
+Sets the name the DHCP client uses to identify itself. In a typical network
+setup this will be the name that shows up in the Wi-Fi router's device list.
+The hostname must be no longer than 32 characters.
+
+.. code-block:: arduino
+
+    setHostname(const char *hostname);
+
+If the hostname is never specified, a default one will be assigned based
+on the chip type and MAC address. The current hostname (default or custom)
+may be retrieved:
+
+.. code-block:: arduino
+
+    const char *getHostname();
+
+.. warning::
+
+    The ``setHostname()`` function must be called BEFORE Wi-Fi is started with
+    ``WiFi.begin()``, ``WiFi.softAP()``, ``WiFi.mode()``, or ``WiFi.run()``.
+    To change the name, reset Wi-Fi with ``WiFi.mode(WIFI_MODE_NULL)``,
+    then proceed with ``WiFi.setHostname(...)`` and restart WiFi from scratch.
+
+useStaticBuffers
+****************
+
+This function is used to set the memory allocation mode for the Wi-Fi buffers.
+
+.. code-block:: arduino
+
+    static void useStaticBuffers(bool bufferMode);
+
+* Set ``true`` to use the Wi-Fi buffers memory allocation as **static**.
+* Set ``false`` to set the buffers memory allocation to **dynamic**.
+
+The use of dynamic allocation is recommended to save memory and reduce resources usage. However, the dynamic performs slightly slower than the static allocation.
+Use static allocation if you want to have more performance and if your application is multi-tasking.
+
+By default, the memory allocation will be set to **dynamic** if this function is not being used.
+
+setDualAntennaConfig
+********************
+
+Configures the Dual antenna functionality. This function should be used only on the **ESP32-WROOM-DA** module or any other ESP32 with RF switch.
+
+.. code-block:: arduino
+
+    bool setDualAntennaConfig(uint8_t gpio_ant1, uint8_t gpio_ant2, wifi_rx_ant_t rx_mode, wifi_tx_ant_t tx_mode);
+
+
+* ``gpio_ant1`` Configure the GPIO number for the antenna 1 connected to the RF switch (default ``GPIO2`` on ESP32-WROOM-DA)
+* ``gpio_ant2`` Configure the GPIO number for the antenna 2 connected to the RF switch (default ``GPIO25`` on ESP32-WROOM-DA)
+* ``rx_mode`` Set the RX antenna mode. See wifi_rx_ant_t for the options.
+* ``tx_mode`` Set the TX antenna mode. See wifi_tx_ant_t for the options.
+
+Return ``true`` if the configuration was successful.
+
+For the ``rx_mode`` you can use the following configuration:
+
+* ``WIFI_RX_ANT0`` Selects the antenna 1 for all RX activity.
+* ``WIFI_RX_ANT1`` Selects the antenna 2 for all RX activity.
+* ``WIFI_RX_ANT_AUTO``  Selects the antenna for RX automatically.
+
+For the ``tx_mode`` you can use the following configuration:
+
+* ``WIFI_TX_ANT0`` Selects the antenna 1 for all TX activity.
+* ``WIFI_TX_ANT1`` Selects the antenna 2 for all TX activity.
+* ``WIFI_TX_ANT_AUTO`` Selects the antenna for TX automatically.
+
+WiFiAP
+------
+
+The ``WiFiAP`` is used to configure and manage the Wi-Fi as an Access Point. This is where you can find the related functions for the AP.
+
+Basic Usage
+***********
+
+To start the Wi-Fi as an Access Point.
+
+.. code-block:: arduino
+
+    WiFi.softAP(ssid, password);
+
+Please see the full WiFiAP example in: `ap example`_.
+
+AP Configuration
+----------------
+
+softAP
+******
+
+Use the function ``softAP`` to configure the Wi-Fi AP characteristics:
+
+.. code-block:: arduino
+
+    bool softAP(const char* ssid, const char* passphrase = NULL, int channel = 1, int ssid_hidden = 0, int max_connection = 4, bool ftm_responder = false);
+
+Where:
+
+* ``ssid`` sets the Wi-Fi network SSID.
+* ``passphrase`` sets the Wi-Fi network password. If the network is open, set as ``NULL``.
+* ``channel`` configures the Wi-Fi channel.
+* ``ssid_hidden`` sets the network as hidden.
+* ``max_connection`` sets the maximum number of simultaneous connections. The default is 4.
+* ``ftm_responder`` sets the Wi-Fi FTM responder feature. **Only for ESP32-S2 and ESP32-C3 SoC!**
+
+Return ``true`` if the configuration was successful.
+
+softAPConfig
+************
+
+Function used to configure the IP as static (fixed) as well as the gateway and subnet.
+
+.. code-block:: arduino
+
+    bool softAPConfig(IPAddress local_ip, IPAddress gateway, IPAddress subnet);
+
+Where:
+
+* ``local_ip`` sets the local IP address.
+* ``gateway`` sets the gateway IP.
+* ``subnet`` sets the subnet mask.
+
+The function will return ``true`` if the configuration is successful.
+
+AP Connection
+-------------
+
+softAPdisconnect
+****************
+
+Function used to force the AP disconnection.
+
+.. code-block:: arduino
+
+    bool softAPdisconnect(bool wifioff = false);
+
+Where:
+
+* ``wifioff`` sets the Wi-Fi off if ``true``.
+
+The function will return ``true`` if the configuration is successful.
+
+
+softAPgetStationNum
+*******************
+
+This function returns the number of clients connected to the AP.
+
+.. code-block:: arduino
+
+    uint8_t softAPgetStationNum();
+
+softAPIP
+********
+
+Function to get the AP IPv4 address.
+
+.. code-block:: arduino
+
+    IPAddress softAPIP();
+
+The function will return the AP IP address in ``IPAddress`` format.
+
+softAPBroadcastIP
+*****************
+
+Function to get the AP IPv4 broadcast address.
+
+.. code-block:: arduino
+
+    IPAddress softAPBroadcastIP();
+
+The function will return the AP broadcast address in ``IPAddress`` format.
+
+softAPNetworkID
+***************
+
+Get the softAP network ID.
+
+.. code-block:: arduino
+
+    IPAddress softAPNetworkID();
+
+The function will return the AP network address in ``IPAddress`` format.
+
+softAPSubnetCIDR
+****************
+
+Get the softAP subnet CIDR.
+
+.. code-block:: arduino
+
+    uint8_t softAPSubnetCIDR();
+
+softAPSubnetMask
+****************
+
+Get the softAP subnet mask.
+
+.. code-block:: arduino
+
+    IPAddress softAPSubnetMask();
+
+softAPenableIPv6
+****************
+
+Function used to enable the IPv6 support.
+
+.. code-block:: arduino
+
+    bool softAPenableIPv6(bool enable=true);
+
+The function will return ``true`` if the configuration is successful.
+
+softAPIPv6
+**********
+
+Function to get the IPv6 address.
+
+.. code-block:: arduino
+
+    IPAddress softAPlinkLocalIPv6();
+
+The function will return the AP IPv6 address in ``IPAddress`` format.
+
+softAPgetHostname
+*****************
+
+Function to get the AP hostname.
+
+.. code-block:: arduino
+
+    const char * softAPgetHostname();
+
+softAPsetHostname
+*****************
+
+Function to set the AP hostname.
+
+.. code-block:: arduino
+
+    bool softAPsetHostname(const char * hostname);
+
+Where:
+
+* ``hostname`` sets the device hostname.
+
+The function will return ``true`` if the configuration is successful.
+
+
+softAPmacAddress
+****************
+
+Function to define the AP MAC address.
+
+.. code-block:: arduino
+
+    uint8_t* softAPmacAddress(uint8_t* mac);
+
+Where:
+
+* ``mac`` sets the new MAC address.
+
+Function to get the AP MAC address.
+
+.. code-block:: arduino
+
+    String softAPmacAddress(void);
+
+softAPSSID
+**********
+
+Function to get the AP SSID.
+
+.. code-block:: arduino
+
+    String softAPSSID(void) const;
+
+Returns the AP SSID.
+
+WiFiSTA
+-------
+
+The ``WiFiSTA`` is used to configure and manage the Wi-Fi as Station. The related functions for the STA are here.
+
+Basic Usage
+***********
+
+The following code shows the basic usage of the WifiSTA functionality.
+
+.. code-block:: arduino
+
+    WiFi.begin(ssid, password);
+
+Where the ``ssid`` and ``password`` are from the network you want to connect the ESP32.
+
+To check if the connection is successful, you can use:
+
+.. code-block:: arduino
+
+    while (WiFi.status() != WL_CONNECTED) {
+        delay(500);
+        Serial.print(".");
+    }
+
+After a successful connection, you can print the IP address given by the network.
+
+.. code-block:: arduino
+
+    Serial.println("IP address: ");
+    Serial.println(WiFi.localIP());
+
+Please see the full example of the WiFiSTA in: `sta example`_.
+
+STA Configuration
+-----------------
+
+begin
+*****
+
+- Functions ``begin`` are used to configure and start the Wi-Fi.
+
+.. code-block:: arduino
+
+    wl_status_t begin(const char* ssid, const char *passphrase = NULL, int32_t channel = 0, const uint8_t* bssid = NULL, bool connect = true);
+
+Where:
+
+* ``ssid`` sets the AP SSID.
+* ``passphrase`` sets the AP password. Set as ``NULL`` for open networks.
+* ``channel`` sets the Wi-Fi channel.
+* ``uint8_t* bssid`` sets the AP BSSID.
+* ``connect`` sets ``true`` to connect to the configured network automatically.
+
+.. code-block:: arduino
+
+    wl_status_t begin(char* ssid, char *passphrase = NULL, int32_t channel = 0, const uint8_t* bssid = NULL, bool connect = true);
+
+Where:
+
+* ``ssid`` sets the AP SSID.
+* ``passphrase`` sets the AP password. Set as ``NULL`` for open networks.
+* ``channel`` sets the Wi-Fi channel.
+* ``bssid`` sets the AP BSSID.
+* ``connect`` sets ``true`` to connect to the configured network automatically.
+
+Function to start the connection after being configured.
+
+.. code-block:: arduino
+
+    wl_status_t begin();
+
+config
+******
+
+Function ``config`` is used to configure Wi-Fi. After configuring, you can call function ``begin`` to start the Wi-Fi process.
+
+.. code-block:: arduino
+
+    bool config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1 = (uint32_t)0x00000000, IPAddress dns2 = (uint32_t)0x00000000);
+
+Where:
+
+* ``local_ip`` sets the local IP.
+* ``gateway`` sets the gateway IP.
+* ``subnet`` sets the subnet mask.
+* ``dns1`` sets the DNS.
+* ``dns2`` sets the DNS alternative option.
+
+The function will return ``true`` if the configuration is successful.
+
+The ``IPAddress`` format is defined by 4 bytes as described here:
+
+.. code-block:: arduino
+
+    IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet);
+
+Example:
+
+.. code-block:: arduino
+
+    IPAddress local_ip(192, 168, 10, 20);
+
+See the ``WiFiClientStaticIP.ino`` for more details on how to use this feature.
+
+STA Connection
+--------------
+
+reconnect
+*********
+
+Function used to reconnect the Wi-Fi connection.
+
+.. code-block:: arduino
+
+    bool reconnect();
+
+disconnect
+**********
+
+Function to force disconnection.
+
+.. code-block:: arduino
+
+    bool disconnect(bool wifioff = false, bool eraseap = false);
+
+Where:
+
+* ``wifioff`` use ``true`` to turn the Wi-Fi radio off.
+* ``eraseap`` use ``true`` to erase the AP configuration from the NVS memory.
+
+The function will return ``true`` if the configuration is successful.
+
+isConnected
+***********
+
+Function used to get the connection state.
+
+.. code-block:: arduino
+
+    bool isConnected();
+
+Return the connection state.
+
+setAutoConnect
+**************
+
+Function is deprecated.
+
+getAutoConnect
+**************
+
+Function is deprecated.
+
+setAutoReconnect
+****************
+
+Function used to set the automatic reconnection if the connection is lost.
+
+.. code-block:: arduino
+
+    bool setAutoReconnect(bool autoReconnect);
+
+Where:
+
+* ``autoConnect`` is set to ``true`` to enable this option.
+
+getAutoReconnect
+****************
+
+Function used to get the automatic reconnection if the connection is lost.
+
+.. code-block:: arduino
+
+    bool getAutoReconnect();
+
+The function will return ``true`` if this setting is enabled.
+
+setMinSecurity
+**************
+
+Function used to set the minimum security for AP to be considered connectable.
+
+.. code-block:: arduino
+
+    bool setMinSecurity(wifi_auth_mode_t minSecurity);
+
+Where:
+
+* ``minSecurity`` is the minimum security for AP to be considered connectable. Default is ``WIFI_AUTH_WPA2_PSK``.
+
+WiFiMulti
+---------
+
+The ``WiFiMulti`` allows you to add more than one option for the AP connection while running as a station.
+
+To add the AP, use the following function. You can add multiple AP's and this library will handle the connection.
+
+.. code-block:: arduino
+
+    bool addAP(const char* ssid, const char *passphrase = NULL);
+
+After adding the AP's, run by the following function.
+
+.. code-block:: arduino
+
+    uint8_t run(uint32_t connectTimeout=5000);
+
+To see how to use the ``WiFiMulti``, take a look at the ``WiFiMulti.ino`` example available.
+
+WiFiScan
+--------
+
+To perform the Wi-Fi scan for networks, you can use the following functions:
+
+Start scan Wi-Fi networks available.
+
+.. code-block:: arduino
+
+    int16_t scanNetworks(bool async = false, bool show_hidden = false, bool passive = false, uint32_t max_ms_per_chan = 300, uint8_t channel = 0);
+
+Called to get the scan state in Async mode.
+
+.. code-block:: arduino
+
+    int16_t scanComplete();
+
+Delete last scan result from RAM.
+
+.. code-block:: arduino
+
+    void scanDelete();
+
+Loads all infos from a scanned Wi-Fi in to the ptr parameters.
+
+.. code-block:: arduino
+
+    bool getNetworkInfo(uint8_t networkItem, String &ssid, uint8_t &encryptionType, int32_t &RSSI, uint8_t* &BSSID, int32_t &channel);
+
+To see how to use the ``WiFiScan``, take a look at the ``WiFiScan.ino`` or ``WiFiScanAsync.ino`` example available.
+
+Examples
+--------
+
+`Complete list of Wi-Fi examples <https://github.com/espressif/arduino-esp32/tree/master/libraries/WiFi/examples>`_.
+
+.. _ap example:
+
+Wi-Fi AP Example
+****************
+
+.. literalinclude:: ../../../libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino
+    :language: arduino
+
+.. _sta example:
+
+Wi-Fi STA Example
+*****************
+
+.. literalinclude:: ../../../libraries/WiFi/examples/WiFiClient/WiFiClient.ino
+    :language: arduino
+
+.. _events example:
+
+Wi-Fi Events Example
+********************
+
+.. literalinclude:: ../../../libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino
+    :language: arduino
diff --git a/docs/en/boards/ESP32-C3-DevKitM-1.rst b/docs/en/boards/ESP32-C3-DevKitM-1.rst
new file mode 100644
index 00000000000..abf7d2cef34
--- /dev/null
+++ b/docs/en/boards/ESP32-C3-DevKitM-1.rst
@@ -0,0 +1,125 @@
+##################
+ESP32-C3-DevKitM-1
+##################
+
+The ESP32-C3-DevKitM-1 development board is one of Espressif's official boards. This board is based on the `ESP32-C3-MINI-1`_ module, with the `ESP32-C3`_ as the core.
+
+Specifications
+--------------
+
+- Small sized 2.4 GHz Wi-Fi (802.11b/g/n) and Bluetooth® 5 module
+- Built around ESP32-C3 series of SoCs, RISC-V single-core microprocessor
+- 4 MB flash in chip package
+- 15 available GPIOs (module)
+- Peripherals
+    - 22 × programmable GPIOs
+    - Digital interfaces:
+    - 3 × SPI
+    - 2 × UART
+    - 1 × I2C
+    - 1 × I2S
+    - Remote control peripheral, with 2 transmit channels and 2 receive channels
+    - LED PWM controller, with up to 6 channels
+    - Full-speed USB Serial/JTAG controller
+    - General DMA controller (GDMA), with 3 transmit channels and 3 receive channels
+    - 1 × TWAI® controller (compatible with ISO 11898-1)
+    - Analog interfaces:
+        - 2 × 12-bit SAR ADCs, up to 6 channels
+        - 1 × temperature sensor
+    - Timers:
+        - 2 × 54-bit general-purpose timers
+        - 3 × watchdog timers
+        - 1 × 52-bit system timer
+- PCB antenna or external antenna connector
+
+Header Block
+------------
+
+.. note::
+    Not all of the chip pins are exposed to the pin headers.
+
+J1
+^^^
+
+.. vale off
+
+===  ====  ==========  ===================================
+No.  Name  Type [1]_   Function
+===  ====  ==========  ===================================
+1    GND   G           Ground
+2    3V3   P           3.3 V power supply
+3    3V3   P           3.3 V power supply
+4    IO2   I/O/T       GPIO2 [2]_, ADC1_CH2, FSPIQ
+5    IO3   I/O/T       GPIO3, ADC1_CH3
+6    GND   G           Ground
+7    RST   I           CHIP_PU
+8    GND   G           Ground
+9    IO0   I/O/T       GPIO0, ADC1_CH0, XTAL_32K_P
+10   IO1   I/O/T       GPIO1, ADC1_CH1, XTAL_32K_N
+11   IO10  I/O/T       GPIO10, FSPICS0
+12   GND   G           Ground
+13   5V    P           5 V power supply
+14   5V    P           5 V power supply
+15   GND   G           Ground
+===  ====  ==========  ===================================
+
+.. vale on
+
+J3
+^^^
+===  ====  ==========  ====================================
+No.  Name  Type [1]_   Function
+===  ====  ==========  ====================================
+1    GND   G           Ground
+2    TX    I/O/T       GPIO21, U0TXD
+3    RX    I/O/T       GPIO20, U0RXD
+4    GND   G           Ground
+5    IO9   I/O/T       GPIO9 [2]_
+6    IO8   I/O/T       GPIO8 [2]_, RGB LED
+7    GND   G           Ground
+8    IO7   I/O/T       GPIO7, FSPID, MTDO
+9    IO6   I/O/T       GPIO6, FSPICLK, MTCK
+10   IO5   I/O/T       GPIO5, ADC2_CH0, FSPIWP, MTDI
+11   IO4   I/O/T       GPIO4, ADC1_CH4, FSPIHD, MTMS
+12   GND   G           Ground
+13   IO18  I/O/T       GPIO18, USB_D-
+14   IO19  I/O/T       GPIO19, USB_D+
+15   GND   G           Ground
+===  ====  ==========  ====================================
+
+.. [1] P: Power supply; I: Input; O: Output; T: High impedance.
+.. [2] GPIO2, GPIO8, and GPIO9 are strapping pins of the ESP32-C3FN4 chip. During the chip's system reset, the latches of the strapping pins sample the voltage level as strapping bits, and hold these bits until the chip is powered down or shut down.
+
+Pin Layout
+----------
+
+.. figure:: ../../_static/esp32-c3_devkitM-1_pinlayout.png
+    :align: center
+    :width: 600
+    :alt: ESP32-C3-DevKitM-1 (click to enlarge)
+    :figclass: align-center
+
+Strapping Pins
+--------------
+
+Some of the GPIO's have important features during the booting process. Here is the list of the strapping pins on the `ESP32-C3`_.
+
+====  =========  =====================================================================  ================  =================
+GPIO   Default    Function                                                               Pull-up          Pull-down
+====  =========  =====================================================================  ================  =================
+IO2   N/A        Booting Mode                                                           See `ESP32-C3`_   See `ESP32-C3`_
+IO9   Pull-up    Booting Mode                                                           SPI Boot          Download Boot
+IO8   N/A        Booting Mode                                                           Don't Care        Download Boot
+IO8   Pull-up    Enabling/Disabling Log Print                                           See `ESP32-C3`_   See `ESP32-C3`_
+====  =========  =====================================================================  ================  =================
+
+For more detailed information, see the `ESP32-C3`_ datasheet.
+
+Resources
+---------
+
+* `ESP32-C3`_ (Datasheet)
+* `ESP32-C3-MINI-1`_ (Datasheet)
+
+.. _ESP32-C3: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf
+.. _ESP32-C3-MINI-1: https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf
diff --git a/docs/en/boards/ESP32-DevKitC-1.rst b/docs/en/boards/ESP32-DevKitC-1.rst
new file mode 100644
index 00000000000..6a7f1c78864
--- /dev/null
+++ b/docs/en/boards/ESP32-DevKitC-1.rst
@@ -0,0 +1,163 @@
+###############
+ESP32-DevKitC-1
+###############
+
+The `ESP32-DevKitC-1`_ development board is one of Espressif's official boards. This board is based on the `ESP32-WROVER-E`_ module, with the `ESP32`_ as the core.
+
+Specifications
+--------------
+
+- Wi-Fi 802.11b/g/n (802.11n up to 150 Mbps)
+- Bluetooth v4.2 BR/EDR and BLE specification
+- Built around ESP32 series of SoCs
+- Integrated 4 MB SPI flash
+- Integrated 8 MB PSRAM
+- Peripherals
+    - SD card
+    - UART
+    - SPI
+    - SDIO
+    - I2C
+    - LED PWM
+    - Motor PWM
+    - I2S
+    - IR
+    - Pulse Counter
+    - GPIO
+    - Capacitive Touch Sensor
+    - ADC
+    - DAC
+    - Two-Wire Automotive Interface (TWAI®, compatible with ISO11898-1)
+- PCB antenna or external antenna connector
+
+Header Block
+------------
+
+.. note::
+    Not all of the chip pins are exposed to the pin headers.
+
+J1
+^^^
+
+.. vale off
+
+===  ====  =====  ===================================
+No.  Name  Type   Function
+===  ====  =====  ===================================
+1    3V3   P      3.3 V power supply
+2    EN    I      CHIP_PU, Reset
+3    IO36  I      GPIO36, ADC1_CH0, S_VP
+4    IO39  I      GPIO39, ADC1_CH3, S_VN
+5    IO34  I      GPIO34, ADC1_CH6, VDET_1
+6    IO35  I      GPIO35, ADC1_CH7, VDET_2
+7    IO32  I/O    GPIO32, ADC1_CH4, TOUCH_CH9, XTAL_32K_P
+8    IO33  I/O    GPIO33, ADC1_CH5, TOUCH_CH8, XTAL_32K_N
+9    IO25  I/O    GPIO25, ADC1_CH8, DAC_1
+10   IO26  I/O    GPIO26, ADC2_CH9, DAC_2
+11   IO27  I/O    GPIO27, ADC2_CH7, TOUCH_CH7
+12   IO14  I/O    GPIO14, ADC2_CH6, TOUCH_CH6, MTMS
+13   IO12  I/O    GPIO12, ADC2_CH5, TOUCH_CH5, MTDI
+14   GND   G      Ground
+15   IO13  I/O    GPIO13, ADC2_CH4, TOUCH_CH4, MTCK
+16   IO9   I/O    GPIO9, D2
+17   IO10  I/O    GPIO10, D3
+18   IO11  I/O    GPIO11, CMD
+19   5V0   P      5 V power supply
+===  ====  =====  ===================================
+
+.. vale on
+
+J3
+^^^
+===  ====  =====  ====================================
+No.  Name  Type   Function
+===  ====  =====  ====================================
+1    GND   G      Ground
+2    IO23  I/O    GPIO23
+3    IO22  I/O    GPIO22
+4    IO1   I/O    GPIO1, U0TXD
+5    IO3   I/O    GPIO3, U0RXD
+6    IO21  I/O    GPIO21
+7    GND   G      Ground
+8    IO19  I/O    GPIO19
+9    IO18  I/O    GPIO18
+10   IO5   I/O    GPIO5
+11   IO17  I/O    GPIO17
+12   IO16  I/O    GPIO16
+13   IO4   I/O    GPIO4, ADC2_CH0, TOUCH_CH0
+14   IO0   I/O    GPIO0, ADC2_CH1, TOUCH_CH1, Boot
+16   IO2   I/O    GPIO2, ADC2_CH2, TOUCH_CH2
+17   IO15  I/O    GPIO15, ADC2_CH3, TOUCH_CH3, MTDO
+17   IO8   I/O    GPIO8, D1
+18   IO7   I/O    GPIO7, D0
+19   IO6   I/O    GPIO6, SCK
+===  ====  =====  ====================================
+
+    P: Power supply;
+    I: Input;
+    O: Output;
+    T: High impedance.
+
+Pin Layout
+----------
+
+.. figure:: ../../_static/esp32_devkitC_pinlayout.png
+    :align: center
+    :width: 600
+    :alt: ESP32-DevKitC-1 (click to enlarge)
+    :figclass: align-center
+
+Strapping Pins
+--------------
+
+Some of the GPIO's have important features during the booting process. Here is the list of the strapping pins on the `ESP32`_.
+
+====  =========  =====================================================================  ============  ==============
+GPIO   Default    Function                                                               Pull-up       Pull-down
+====  =========  =====================================================================  ============  ==============
+IO12  Pull-down  Voltage of Internal LDO (VDD_SDIO)                                     1.8 V         3.3 V
+IO0   Pull-up    Booting Mode                                                           SPI Boot      Download Boot
+IO2   Pull-down  Booting Mode                                                           Don't Care    Download Boot
+IO15  Pull-up    Enabling/Disabling Log Print During Booting and Timing of SDIO Slave   U0TXD Active  U0TXD Silent
+IO5   Pull-up    Timing of SDIO Slave                                                   See `ESP32`_  See `ESP32`_
+====  =========  =====================================================================  ============  ==============
+
+Be aware when choosing which pins to use.
+
+Restricted Usage GPIO's
+-----------------------
+
+Some of the GPIO's are used for the external flash and PSRAM. These GPIO's cannot be used:
+
+====  ===================
+GPIO   Shared Function
+====  ===================
+IO6   External SPI Flash
+IO7   External SPI Flash
+IO8   External SPI Flash
+IO9   External SPI Flash
+IO10  External SPI Flash
+IO11  External SPI Flash
+====  ===================
+
+Other GPIO's are `INPUT ONLY` and cannot be used as output pin:
+
+====  =========================
+GPIO   Function
+====  =========================
+IO34  GPIO34, ADC1_CH6, VDET_1
+IO35  GPIO35, ADC1_CH7, VDET_2
+IO36  GPIO36, ADC1_CH0, S_VP
+IO39  GPIO39, ADC1_CH3, S_VN
+====  =========================
+
+Resources
+---------
+
+* `ESP32`_ (Datasheet)
+* `ESP32-WROVER-E`_ (Datasheet)
+* `ESP32-DevKitC`_ (Schematic)
+
+.. _ESP32: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf
+.. _ESP32-WROVER-E: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf
+.. _ESP32-DevKitC: https://dl.espressif.com/dl/schematics/esp32_devkitc_v4-sch.pdf
diff --git a/docs/en/boards/ESP32-S2-Saola-1.rst b/docs/en/boards/ESP32-S2-Saola-1.rst
new file mode 100644
index 00000000000..9c8c83c6211
--- /dev/null
+++ b/docs/en/boards/ESP32-S2-Saola-1.rst
@@ -0,0 +1,158 @@
+################
+ESP32-S2-Saola-1
+################
+
+The `ESP32-S2-Saola-1`_ development board is one of Espressif's official boards. This board is based on the `ESP32-S2-WROVER`_ module, with the `ESP32-S2`_ as the core.
+
+Specifications
+--------------
+
+- Wi-Fi 802.11b/g/n (802.11n up to 150 Mbps)
+- Built around ESP32-S2 series of SoCs Xtensa® single-core
+- Integrated 4 MB SPI flash
+- Integrated 2 MB PSRAM
+- Peripherals
+    - 43 × programmable GPIOs
+    - 2 × 13-bit SAR ADCs, up to 20 channels
+    - 2 × 8-bit DAC
+    - 14 × touch sensing IOs
+    - 4 × SPI
+    - 1 × I2S
+    - 2 × I2C
+    - 2 × UART
+    - RMT (TX/RX)
+    - LED PWM controller, up to 8 channels
+    - 1 × full-speed USB OTG
+    - 1 × temperature sensor
+    - 1 × DVP 8/16 camera interface, implemented using the hardware resources of I2S
+    - 1 × LCD interface (8-bit serial RGB/8080/6800), implemented using the hardware resources of SPI2
+    - 1 × LCD interface (8/16/24-bit parallel), implemented using the hardware resources of I2S
+    - 1 × TWAI® controller (compatible with ISO 11898-1)
+- PCB antenna or external antenna connector
+
+Header Block
+------------
+
+.. note::
+    Not all of the chip pins are exposed to the pin headers.
+
+J2
+^^^
+
+.. vale off
+
+===  ====  =====  ===================================
+No.  Name  Type   Function
+===  ====  =====  ===================================
+1    3V3   P      3.3 V power supply
+2    IO0   I/O    GPIO0, Boot
+3    IO1   I/O    GPIO1, ADC1_CH0, TOUCH_CH1
+4    IO2   I/O    GPIO2, ADC1_CH1, TOUCH_CH2
+5    IO3   I/O    GPIO3, ADC1_CH2, TOUCH_CH3
+6    IO4   I/O    GPIO4, ADC1_CH3, TOUCH_CH4
+7    IO5   I/O    GPIO5, ADC1_CH4, TOUCH_CH5
+8    IO6   I/O    GPIO6, ADC1_CH5, TOUCH_CH6
+9    IO7   I/O    GPIO7, ADC1_CH6, TOUCH_CH7
+10   IO8   I/O    GPIO8, ADC1_CH7, TOUCH_CH8
+11   IO9   I/O    GPIO9, ADC1_CH8, TOUCH_CH9
+12   IO10  I/O    GPIO10, ADC1_CH9, TOUCH_CH10
+13   IO11  I/O    GPIO11, ADC2_CH0, TOUCH_CH11
+14   IO12  I/O    GPIO12, ADC2_CH1, TOUCH_CH12
+15   IO13  I/O    GPIO13, ADC2_CH2, TOUCH_CH13
+16   IO14  I/O    GPIO14, ADC2_CH3, TOUCH_CH14
+17   IO15  I/O    GPIO15, ADC2_CH4, XTAL_32K_P
+18   IO16  I/O    GPIO16, ADC2_CH5, XTAL_32K_N
+19   IO17  I/O    GPIO17, ADC2_CH6, DAC_1
+20   5V0   P      5 V power supply
+21   GND   G      Ground
+===  ====  =====  ===================================
+
+.. vale on
+
+J3
+^^^
+===  ====  =====  ====================================
+No.  Name  Type   Function
+===  ====  =====  ====================================
+1    GND   G      Ground
+2    RST   I      CHIP_PU, Reset
+3    IO46  I      GPIO46
+4    IO45  I/O    GPIO45
+5    IO44  I/O    GPIO44, U0RXD
+6    IO43  I/O    GPIO43, U0TXD
+7    IO42  I/O    GPIO42, MTMS
+8    IO41  I/O    GPIO41, MTDI
+9    IO40  I/O    GPIO40, MTDO
+10   IO39  I/O    GPIO39, MTCK
+11   IO38  I/O    GPIO38
+12   IO37  I/O    GPIO37
+13   IO36  I/O    GPIO36
+14   IO35  I/O    GPIO35
+16   IO34  I/O    GPIO34
+17   IO33  I/O    GPIO33
+17   IO26  I/O    GPIO26
+18   IO21  I/O    GPIO21
+19   IO20  I/O    GPIO20, ADC2_CH3, USB_D+
+20   IO19  I/O    GPIO19, ADC2_CH3, USB_D-
+21   IO18  I/O    GPIO18, ADC2_CH3, DAC_2
+===  ====  =====  ====================================
+
+    P: Power supply;
+    I: Input;
+    O: Output;
+    T: High impedance.
+
+Pin Layout
+----------
+
+.. figure:: ../../_static/esp32-s2_saola1_pinlayout.png
+    :align: center
+    :width: 600
+    :alt: ESP32-S2-Saola-1 (click to enlarge)
+    :figclass: align-center
+
+Strapping Pins
+--------------
+
+Some of the GPIO's have important features during the booting process. Here is the list of the strapping pins on the `ESP32-S2`_.
+
+====  =========  =====================================================================  ============  ==============
+GPIO   Default    Function                                                               Pull-up       Pull-down
+====  =========  =====================================================================  ============  ==============
+IO45  Pull-down  Voltage of Internal LDO (VDD_SDIO)                                     1.8 V         3.3 V
+IO0   Pull-up    Booting Mode                                                           SPI Boot      Download Boot
+IO46  Pull-down  Booting Mode                                                           Don't Care    Download Boot
+IO46  Pull-up    Enabling/Disabling Log Print During Booting and Timing of SDIO Slave   U0TXD Active  U0TXD Silent
+====  =========  =====================================================================  ============  ==============
+
+For more detailed information, see the `ESP32-S2`_ datasheet.
+
+Restricted Usage GPIOS
+----------------------
+
+Some of the GPIO's are used for the external flash and PSRAM. These GPIO's cannot be used:
+
+====  ===================
+GPIO   Shared Function
+====  ===================
+IO26  Connected to PSRAM
+====  ===================
+
+Other GPIO's are `INPUT ONLY` and cannot be used as output pin:
+
+====  ===========================
+GPIO   Function
+====  ===========================
+IO46  GPIO46
+====  ===========================
+
+Resources
+---------
+
+* `ESP32-S2`_ (Datasheet)
+* `ESP32-S2-WROVER`_ (Datasheet)
+* `ESP32-S2-Saola-1`_ (Schematics)
+
+.. _ESP32-S2: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf
+.. _ESP32-S2-WROVER: https://www.espressif.com/sites/default/files/documentation/esp32-s2-wrover_esp32-s2-wrover-i_datasheet_en.pdf
+.. _ESP32-S2-Saola-1: https://dl.espressif.com/dl/schematics/ESP32-S2-SAOLA-1_V1.1_schematics.pdf
diff --git a/docs/en/boards/boards.rst b/docs/en/boards/boards.rst
new file mode 100644
index 00000000000..407b019a78b
--- /dev/null
+++ b/docs/en/boards/boards.rst
@@ -0,0 +1,126 @@
+######
+Boards
+######
+
+Development Boards
+------------------
+
+You will need a development board or a custom board with the ESP32 (see Supported SoC's) to start playing.
+There is a bunch of different types and models widely available on the Internet. You need to choose one that covers all your requirements.
+
+To help you on this selection, we point out some facts about choosing the proper boards to help you to save money and time.
+
+**One ESP32 to rule them all!**
+
+One important information that usually bring about some confusion is regarding the different models of the ESP32 SoC and modules.
+
+The ESP32 is divided by family:
+
+* ESP32
+    * Wi-Fi, BT and BLE 4
+* ESP32-C3
+    * Wi-Fi and BLE 5
+* ESP32-C6
+    * Wi-Fi, BLE 5 and IEEE 802.15.4
+* ESP32-H2
+    * BLE 5 and IEEE 802.15.4
+* ESP32-P4
+    * 400 MHz Dual Core RISC-V CPU, 40 MHz ULP Co-processor, single-precision FPU and AI extensions.
+* ESP32-S2
+    * Wi-Fi only
+* ESP32-S3
+    * Wi-Fi and BLE 5
+
+For each family, we have SoC variants with some differentiation. The differences are more about the embedded flash and its size and the number of the cores (dual or single).
+
+The modules use the SoC internally, including the external flash, PSRAM (in some models) and other essential electronic components. Essentially, all
+modules from the same family use the same SoC.
+
+.. figure:: ../../_static/soc-module.png
+    :align: center
+    :width: 250
+    :alt: ESP32 SoC and Module (click to enlarge)
+    :figclass: align-center
+
+**For example:**
+
+The SoC partnumber is the ESP32-D0WD-V3 and it's the same SoC used inside of the ESP32-WROVER (with PSRAM) and ESP32-WROOM modules. This means that the
+same characteristics are present in both modules' core.
+
+For more detailed information regarding the SoC's and modules, see the `Espressif Product Selector`_.
+
+Now that you know that the module can be different but the heart is the same, you can choose your development board.
+
+Before buying: Keep in mind that for some "must have" features when choosing the best board for your needs:
+
+- Embedded USB-to-Serial
+    - This is very convenient for programming and monitoring the logs with the terminal via USB.
+- Breadboard friendly
+    - If you are prototyping, this will be very useful to connect your board directly on the breadboard.
+- open-source/open-hardware
+    - Check if the schematics are available for download. This helps a lot on prototyping.
+- Support
+    - Some of the manufacturers offer a very good level of support, with examples and demo projects.
+
+
+Espressif
+---------
+
+.. figure:: ../../_static/logo_espressif.png
+    :align: center
+    :width: 250
+    :alt: Espressif Logo
+    :figclass: align-center
+
+.. toctree::
+    :maxdepth: 1
+
+    ESP32-DevKitC <ESP32-DevKitC-1>
+    ESP32-S2-Saola-1 <ESP32-S2-Saola-1>
+    ESP32-C3-DevKitM-1 <ESP32-C3-DevKitM-1>
+
+.. note::
+   Only a few development boards are described on this documentation page. For more information about other Espressif development boards please refer to the `Espressif website <https://www.espressif.com/en/products/devkits>`_.
+
+Third Party
+-----------
+
+Add here the third party boards, listed by vendors.
+
+.. note::
+    All the information must be provided by the vendor. If your favorite board is not here, consider
+    creating an `issue on GitHub <https://github.com/espressif/arduino-esp32/issues>`_ and directly
+    link/mention the vendor in the issue description.
+
+LOLIN
+*****
+
+* |board_lolin_d32|
+* |board_lolin_d32_pro|
+
+Generic Vendor
+**************
+
+    .. toctree::
+        :maxdepth: 1
+
+        Generic Board Name <generic>
+
+    .. note::
+        Create one file per board or one file with multiple boards. Do not add board information/description on this file.
+
+.. include:: ../common/datasheet.inc
+
+Resources
+---------
+
+.. _Espressif Systems: https://www.espressif.com
+.. _Espressif Product Selector: https://products.espressif.com/
+
+.. |board_lolin_d32| raw:: html
+
+  <a href="https://www.wemos.cc/en/latest/d32/d32.html" target="_blank">LOLIN D32</a>
+
+.. |board_lolin_d32_pro| raw:: html
+
+  <a href="https://www.wemos.cc/en/latest/d32/d32_pro.html" target="_blank">LOLIN D32 Pro</a>
diff --git a/docs/en/boards/generic.rst b/docs/en/boards/generic.rst
new file mode 100644
index 00000000000..d40db616f13
--- /dev/null
+++ b/docs/en/boards/generic.rst
@@ -0,0 +1,34 @@
+####################
+Generic ESP32 Boards
+####################
+
+Specifications
+--------------
+
+Add here the board/kit specifications.
+
+Header Block
+------------
+
+Header1
+^^^^^^^
+
+.. vale off
+
+===  ====  =====  ===================================
+No.  Name  Type   Function
+===  ====  =====  ===================================
+1    3V3   P      3.3 V power supply
+2    IO0   I/O    GPIO0, Boot
+3    5V0   P      5 V power supply
+4    GND   G      Ground
+===  ====  =====  ===================================
+
+.. vale on
+
+Pin Layout
+----------
+
+Add here the pin layout image (not required).
+
+.. include:: ../common/datasheet.inc
diff --git a/docs/en/common/datasheet.inc b/docs/en/common/datasheet.inc
new file mode 100644
index 00000000000..7086a12d1a8
--- /dev/null
+++ b/docs/en/common/datasheet.inc
@@ -0,0 +1,21 @@
+Datasheet
+---------
+
+* `ESP32`_ (Datasheet)
+* `ESP32-C2`_ (Datasheet)
+* `ESP32-C3`_ (Datasheet)
+* `ESP32-C6`_ (Datasheet)
+* `ESP32-H2`_ (Datasheet)
+* `ESP32-P4`_ (Datasheet)
+* `ESP32-S2`_ (Datasheet)
+* `ESP32-S3`_ (Datasheet)
+
+.. _Espressif Product Selector: https://products.espressif.com/
+.. _ESP32: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf
+.. _ESP32-C2: https://www.espressif.com/sites/default/files/documentation/esp8684_datasheet_en.pdf
+.. _ESP32-C3: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf
+.. _ESP32-C6: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf
+.. _ESP32-H2: https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf
+.. _ESP32-P4: https://www.espressif.com/sites/default/files/documentation/esp32-p4_datasheet_en.pdf
+.. _ESP32-S2: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf
+.. _ESP32-S3: https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf
diff --git a/docs/en/conf.py b/docs/en/conf.py
new file mode 100644
index 00000000000..c4291af80e8
--- /dev/null
+++ b/docs/en/conf.py
@@ -0,0 +1,33 @@
+# -*- coding: utf-8 -*-
+#
+# English Language RTD & Sphinx config file
+#
+# Uses ../conf_common.py for most non-language-specific settings.
+
+# Importing conf_common adds all the non-language-specific
+# parts to this conf module
+
+try:
+    from conf_common import *  # noqa: F403,F401
+except ImportError:
+    import os
+    import sys
+
+    sys.path.insert(0, os.path.abspath("../"))
+    from conf_common import *  # noqa: F403,F401
+
+import datetime
+
+current_year = datetime.datetime.now().year
+
+# General information about the project.
+project = "Arduino ESP32"
+copyright = "2016 - {}, Espressif Systems (Shanghai) Co., Ltd".format(current_year)
+pdf_title = "Arduino ESP32 Documentation Guide"
+
+# The language for content autogenerated by Sphinx. Refer to documentation
+# for a list of supported languages.
+language = "en"
+
+# Tracking ID for Google Analytics
+google_analytics_id = "G-F58JM78930"
diff --git a/docs/en/contributing.rst b/docs/en/contributing.rst
new file mode 100644
index 00000000000..4ebe01cbf5b
--- /dev/null
+++ b/docs/en/contributing.rst
@@ -0,0 +1,490 @@
+###################
+Contributions Guide
+###################
+
+We welcome contributions to the Arduino ESP32 project!
+
+How to Contribute
+-----------------
+
+Contributions to the Arduino ESP32 (fixing bugs, adding features, adding documentation) are welcome.
+We accept contributions via `Github Pull Requests <https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/about-pull-requests>`_.
+
+Before Contributing
+-------------------
+
+Before sending us a Pull Request, please consider this:
+
+* All contributions must be written in English to ensure effective communication and support.
+  Pull Requests written in other languages will be closed, with a request to rewrite them in English.
+
+* Is the contribution entirely your own work, or is it already licensed under an LGPL 2.1 compatible Open Source License?
+  If not, cannot accept it.
+
+* Is the code adequately commented and can people understand how it is structured?
+
+* Is there documentation or examples that go with code contributions?
+
+* Are comments and documentation written in clear English, with no spelling or grammar errors?
+
+* Example contributions are also welcome.
+
+  * If you are contributing by adding a new example, please use the `Arduino style guide`_ and the example guideline below.
+
+* If the contribution contains multiple commits, are they grouped together into logical changes (one major change per pull request)?
+  Are any commits with names like "fixed typo" `squashed into previous commits <https://eli.thegreenplace.net/2014/02/19/squashing-github-pull-requests-into-a-single-commit/>`_?
+
+If you're unsure about any of these points, please open the Pull Request anyhow and then ask us for feedback.
+
+Pull Request Process
+--------------------
+
+After you open the Pull Request, there will probably be some discussion in the comments field of the request itself.
+
+Once the Pull Request is ready to merge, it will first be merged into our internal git system for "in-house" automated testing.
+
+If this process passes, it will be merged into the public GitHub repository.
+
+Example Contribution Guideline
+------------------------------
+
+Checklist
+*********
+
+* Check if your example proposal has no similarities to the project (**already existing examples**)
+* Use the `Arduino style guide`_
+* Add the header to all source files
+* Add the ``README.md`` file
+* Add inline comments if needed
+* Test the example
+
+Header
+******
+
+All the source files must include the header with the example name and license, if applicable. You can change this header as you wish,
+but it will be reviewed by the community and may not be accepted.
+
+Ideally, you can add some description about the example, links to the documentation, or the author's name.
+Just have in mind to keep it simple and short.
+
+**Header Example**
+
+.. code-block:: arduino
+
+    /* Wi-Fi FTM Initiator Arduino Example
+
+      This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+      Unless required by applicable law or agreed to in writing, this
+      software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+      CONDITIONS OF ANY KIND, either express or implied.
+    */
+
+
+README file
+***********
+
+The ``README.md`` file should contain the example details.
+
+Please see the recommended ``README.md`` file in the `example template folder <https://github.com/espressif/arduino-esp32/tree/master/libraries/ESP32/examples/Template/ExampleTemplate>`_.
+
+Inline Comments
+***************
+
+Inline comments are important if the example contains complex algorithms or specific configurations that the user needs to change.
+
+Brief and clear inline comments are really helpful for the example understanding and it's fast usage.
+
+See the `FTM example <https://github.com/espressif/arduino-esp32/blob/master/libraries/WiFi/examples/FTM/FTM_Initiator/FTM_Initiator.ino>`_
+as a reference:
+
+.. code-block:: arduino
+
+    // Number of FTM frames requested in terms of 4 or 8 bursts (allowed values - 0 (No pref), 16, 24, 32, 64)
+
+Also:
+
+.. code-block:: arduino
+
+    const char * WIFI_FTM_SSID = "WiFi_FTM_Responder"; // SSID of AP that has FTM Enabled
+    const char * WIFI_FTM_PASS = "ftm_responder"; // STA Password
+
+Testing
+*******
+
+Be sure you have tested the example in all the supported targets. If the example some specific hardware requirements,
+edit/add the ``ci.json`` in the same folder as the sketch to specify the regular expression for the
+required configurations from ``sdkconfig``.
+This will ensure that the CI system will run the test only on the targets that have the required configurations.
+
+You can check the available configurations in the ``sdkconfig`` file in the ``tools/esp32-arduino-libs/<target>`` folder.
+
+Here is an example of the ``ci.json`` file where the example requires Wi-Fi to work properly:
+
+.. code-block:: json
+
+    {
+      "requires": [
+        "CONFIG_SOC_WIFI_SUPPORTED=y"
+      ]
+    }
+
+.. note::
+
+    The list of configurations will be checked against the ``sdkconfig`` file in the target folder. If the configuration is not present in the ``sdkconfig``,
+    the test will be skipped for that target. That means that the test will only run on the targets that have **ALL** the required configurations.
+
+    Also, by default, the "match start of line" character (``^``) will be added to the beginning of each configuration.
+    That means that the configuration must be at the beginning of the line in the ``sdkconfig`` file.
+
+Sometimes, the example might not be supported by some target, even if the target has the required configurations
+(like resources limitations or requiring a specific SoC). To avoid compilation errors, you can add the target to the ``ci.json``
+file so the CI system will force to skip the test on that target.
+
+Here is an example of the ``ci.json`` file where the example is requires Wi-Fi to work properly but is also not supported by the ESP32-S2 target:
+
+.. code-block:: json
+
+    {
+      "requires": [
+        "CONFIG_SOC_WIFI_SUPPORTED=y"
+      ],
+      "targets": {
+        "esp32s2": false
+      }
+    }
+
+You also need to add this information in the ``README.md`` file, on the **Supported Targets**, and in the example code as an inline comment.
+For example, in the sketch:
+
+.. code-block:: arduino
+
+    /*
+      THIS FEATURE REQUIRES WI-FI SUPPORT AND IS NOT AVAILABLE FOR ESP32-S2 AS IT DOES NOT HAVE ENOUGH RAM.
+    */
+
+And in the ``README.md`` file:
+
+.. code-block:: markdown
+
+    Currently, this example requires Wi-Fi and supports the following targets.
+
+    | Supported Targets | ESP32 | ESP32-S3 | ESP32-C3 | ESP32-C6 |
+    | ----------------- | ----- | -------- | -------- | -------- |
+
+By default, the CI system will use the FQBNs specified in the ``.github/scripts/sketch_utils.sh`` file to compile the sketches.
+Currently, the default FQBNs are:
+
+* ``espressif:esp32:esp32:PSRAM=enabled``
+* ``espressif:esp32:esp32s2:PSRAM=enabled``
+* ``espressif:esp32:esp32s3:PSRAM=opi,USBMode=default``
+* ``espressif:esp32:esp32c3``
+* ``espressif:esp32:esp32c6``
+* ``espressif:esp32:esp32h2``
+* ``espressif:esp32:esp32p4:USBMode=default``
+
+There are two ways to alter the FQBNs used to compile the sketches: by using the ``fqbn`` or ``fqbn_append`` fields in the ``ci.json`` file.
+
+If you just want to append a string to the default FQBNs, you can use the ``fqbn_append`` field. For example, to add the ``DebugLevel=debug`` to the FQBNs, you would use:
+
+.. code-block:: json
+
+    {
+      "fqbn_append": "DebugLevel=debug"
+    }
+
+If you want to override the default FQBNs, you can use the ``fqbn`` field. It is a dictionary where the key is the target name and the value is a list of FQBNs.
+The FQBNs in the list will be used in sequence to compile the sketch. For example, to compile a sketch for ESP32-S2 with and without PSRAM enabled, you would use:
+
+.. code-block:: json
+
+    {
+      "fqbn": {
+        "esp32s2": [
+          "espressif:esp32:esp32s2:PSRAM=enabled,FlashMode=dio",
+          "espressif:esp32:esp32s2:PSRAM=disabled,FlashMode=dio"
+        ]
+      }
+    }
+
+.. note::
+
+    The FQBNs specified in the ``fqbn`` field will also override the options specified in the ``fqbn_append`` field.
+    That means that if the ``fqbn`` field is specified, the ``fqbn_append`` field will be ignored and will have no effect.
+
+Example Template
+****************
+
+The example template can be found `here <https://github.com/espressif/arduino-esp32/tree/master/libraries/ESP32/examples/Template/ExampleTemplate>`_
+and can be used as a reference.
+
+Documentation
+-------------
+
+If you are contributing to the documentation, please follow the instructions described in the
+`documentation guidelines <guides/docs_contributing>`_ to properly format and test your changes.
+
+Testing and CI
+--------------
+
+After you have made your changes, you should test them. You can do this in different ways depending on the type of change you have made.
+
+Examples
+********
+
+The easiest way to test an example is to load it into the Arduino IDE and run it on your board. If you have multiple boards,
+you should test it on all of them to ensure that the example works on all supported targets.
+
+You can refer to the `Example Contribution Guideline`_ section for more information on how to write and test examples.
+
+Library Changes
+***************
+
+If you have made changes to a library, you should test it on all supported targets. You can do this by loading the library examples (or creating new ones)
+into the Arduino IDE and running them on your board. If you have multiple boards, you should test it on all of them to ensure that the library
+works as expected on all targets.
+
+You can also add a new test suite to automatically check the library. You can refer to the `Adding a New Test Suite`_ section for more information.
+
+Core Changes
+************
+
+If you have made changes to the core, it is important to ensure that the changes do not break the existing functionality. You can do this by running the
+tests on all supported targets. You can refer to the `Runtime Tests`_ section for more information.
+
+CI
+**
+
+In our repository, we have a Continuous Integration (CI) system that runs tests and fixes on every Pull Request. This system will run the tests
+on all supported targets and check if everything is working as expected.
+
+We have many types of tests and checks, including:
+
+* Compilation tests;
+* Runtime tests;
+* Documentation checks;
+* Code style checks;
+* And more.
+
+Let's go deeper into each type of test in the CI system:
+
+Compilation Tests
+^^^^^^^^^^^^^^^^^
+
+The compilation tests are the first type of tests in the CI system. They check if the code compiles on all supported targets.
+If the code does not compile, the CI system will fail the test and the Pull Request will not be merged.
+This is important to ensure that the code is compatible with all supported targets and no broken code is merged.
+
+It will go through all the sketches in the repository and check if they compile on all supported targets. This process is automated and controlled
+by GitHub Actions. The CI system will run the ``arduino-cli`` tool to compile the sketches on all supported targets.
+
+Testing it locally using the CI scripts would be too time consuming, so we recommend running the tests locally using the Arduino IDE with
+a sketch that uses the changes you made (you can also add the sketch as an example if your change is not covered by the existing ones).
+Make sure to set ``Compiler Warnings`` to ``All`` in the Arduino IDE to catch any potential issues.
+
+Runtime Tests
+^^^^^^^^^^^^^
+
+Another type of test is the runtime tests. They check if the code runs and behaves as expected on all supported targets. If the
+code does not run as expected, the CI system will fail the test and the Pull Request will not be merged. This is important to ensure that the code
+works as expected on all supported targets and no unintended crashes or bugs are introduced.
+
+These tests are specialized sketches that run on the target board and check if the code behaves as expected. This process is automated and
+controlled by the ``pytest_embedded`` tool. You can read more about this tool in its
+`documentation <https://docs.espressif.com/projects/pytest-embedded/en/latest/>`_.
+
+The tests are divided into two categories inside the ``tests`` folder:
+
+* ``validation``: These tests are used to validate the behavior of the Arduino core and libraries. They are used to check if the core and libraries
+  are working as expected;
+* ``performance``: These tests are used to check the performance of the Arduino core and libraries. They are used to check if the changes made
+  to the core and libraries have any big impact on the performance. These tests usually run for a longer time than the validation tests and include
+  common benchmark tools like `CoreMark <https://github.com/eembc/coremark>`_.
+
+To run the runtime tests locally, first install the required dependencies by running:
+
+.. code-block:: bash
+
+    pip install -U -r tests/requirements.txt
+
+Before running the test, we need to build it by running:
+
+.. code-block:: bash
+
+    ./.github/scripts/tests_build.sh -s <test_name> -t <target>
+
+The ``<test_name>`` is the name of the test you want to run (you can check the available tests in the ``tests/validation`` and
+``tests/performance`` folders), and the ``<target>`` is the target board you want to run the test on. For example, to run the ``uart`` test on the
+ESP32-C3 target, you would run:
+
+.. code-block:: bash
+
+    ./.github/scripts/tests_build.sh -s uart -t esp32c3
+
+You should see the output of the build process and the test binary should be generated in the ``~/.arduino/tests/<target_chip>/<test_name>/build.tmp`` folder.
+
+Now that the test is built, you can run it in the target board. Connect the target board to your computer and run:
+
+.. code-block:: bash
+
+    ./.github/scripts/tests_run.sh -s <test_name> -t <target>
+
+For example, to run the ``uart`` test on the ESP32-C3 target, you would run:
+
+.. code-block:: bash
+
+    ./.github/scripts/tests_run.sh -s uart -t esp32c3
+
+The test will run on the target board and you should see the output of the test in the terminal:
+
+.. code-block:: bash
+
+    lucassvaz@Lucas--MacBook-Pro esp32 % ./.github/scripts/tests_run.sh -s uart -t esp32c3
+    Sketch uart test type: validation
+    Running test: uart -- Config: Default
+    pytest tests --build-dir /Users/lucassvaz/.arduino/tests/esp32c3/uart/build.tmp -k test_uart --junit-xml=/Users/lucassvaz/Espressif/Arduino/hardware/espressif/esp32/tests/validation/uart/esp32c3/uart.xml --embedded-services esp,arduino
+    =============================================================================================== test session starts ================================================================================================
+    platform darwin -- Python 3.12.3, pytest-8.2.2, pluggy-1.5.0
+    rootdir: /Users/lucassvaz/Espressif/Arduino/hardware/espressif/esp32/tests
+    configfile: pytest.ini
+    plugins: cov-5.0.0, embedded-1.11.5, anyio-4.4.0
+    collected 15 items / 14 deselected / 1 selected
+
+    tests/validation/uart/test_uart.py::test_uart
+    -------------------------------------------------------------------------------------------------- live log setup --------------------------------------------------------------------------------------------------
+    2024-08-22 11:49:30 INFO Target: esp32c3, Port: /dev/cu.usbserial-2120
+    PASSED                                                                                                                                                                                                       [100%]
+    ------------------------------------------------------------------------------------------------ live log teardown -------------------------------------------------------------------------------------------------
+    2024-08-22 11:49:52 INFO Created unity output junit report: /private/var/folders/vp/g9wctsvn7b91k3pv_7cwpt_h0000gn/T/pytest-embedded/2024-08-22_14-49-30-392993/test_uart/dut.xml
+
+
+    ---------------------------------------------- generated xml file: /Users/lucassvaz/Espressif/Arduino/hardware/espressif/esp32/tests/validation/uart/esp32c3/uart.xml ----------------------------------------------
+    ======================================================================================== 1 passed, 14 deselected in 22.18s =========================================================================================
+
+After the test is finished, you can check the output in the terminal and the generated XML file in the test folder.
+Additionally, for performance tests, you can check the generated JSON file in the same folder.
+
+You can also run the tests in `Wokwi <https://docs.wokwi.com/>`_ or `Espressif's QEMU <https://github.com/espressif/esp-toolchain-docs/tree/main/qemu>`_
+by using the ``-W <timeout_in_ms>`` and ``-Q`` flags respectively. You will need to have the Wokwi and/or QEMU installed in your system
+and set the ``WOKWI_CLI_TOKEN`` and/or ``QEMU_PATH`` environment variables. The ``WOKWI_CLI_TOKEN`` is the CI token that can be obtained from the
+`Wokwi website <https://wokwi.com/dashboard/ci>`_ and the ``QEMU_PATH`` is the path to the QEMU binary.
+
+For example, to run the ``uart`` test using Wokwi, you would run:
+
+.. code-block:: bash
+
+    WOKWI_CLI_TOKEN=<your_wokwi_token> ./.github/scripts/tests_run.sh -s uart -t esp32c3 -W <timeout_in_ms>
+
+And to run the ``uart`` test using QEMU, you would run:
+
+.. code-block:: bash
+
+    QEMU_PATH=<path_to_qemu_binary> ./.github/scripts/tests_run.sh -s uart -t esp32c3 -Q
+
+.. note::
+
+    Not all tests are supported by Wokwi and QEMU. QEMU is only supported for ESP32 and ESP32-C3 targets.
+    Wokwi support depends on the `currently implemented peripherals <https://docs.wokwi.com/guides/esp32#simulation-features>`_.
+
+Adding a New Test Suite
+#######################
+
+If you want to add a new test suite, you can create a new folder inside ``tests/validation`` or ``tests/performance`` with the name of the test suite.
+You can use the ``hello_world`` test suite as a starting point and the other test suites as a reference.
+
+A test suite contains the following files:
+
+* ``test_<test_name>.py``: The test file that contains the test cases. Required.
+* ``<test_name>.ino``: The sketch that will be tested. Required.
+* ``ci.json``: The file that specifies how the test suite will be run in the CI system. Optional.
+* ``diagram.<target>.json``: The diagram file that specifies the connections between the components in Wokwi. Optional.
+* ``scenario.yaml``: The scenario file that specifies how Wokwi will interact with the components. Optional.
+* Any other files that are needed for the test suite.
+
+You can read more about the test python API in the `pytest-embedded documentation <https://docs.espressif.com/projects/pytest-embedded/en/latest/usages/expecting.html>`_.
+For more information about the Unity testing framework, you can check the `Unity documentation <https://github.com/ThrowTheSwitch/Unity>`_.
+
+After creating the test suite, make sure to test it locally and run it in the CI system to ensure that it works as expected.
+
+CI JSON File
+############
+
+The ``ci.json`` file is used to specify how the test suite and sketches will handled by the CI system. It can contain the following fields:
+
+* ``requires``: A list of configurations in ``sdkconfig`` that are required to run the test suite. The test suite will only run on the targets
+  that have **ALL** the required configurations. By default, no configurations are required.
+* ``requires_any``: A list of configurations in ``sdkconfig`` that are required to run the test suite. The test suite will only run on the targets
+  that have **ANY** of the required configurations. By default, no configurations are required.
+* ``targets``: A dictionary that specifies the targets for which the tests will be run. The key is the target name and the value is a boolean
+  that specifies if the test should be run for that target. By default, all targets are enabled as long as they have the required configurations
+  specified in the ``requires`` field. This field is also valid for examples.
+* ``platforms``: A dictionary that specifies the supported platforms. The key is the platform name and the value is a boolean that specifies if
+  the platform is supported. By default, all platforms are assumed to be supported.
+* ``extra_tags``: A list of extra tags that the runner will require when running the test suite in hardware. By default, no extra tags are required.
+* ``fqbn_append``: A string to be appended to the default FQBNs. By default, no string is appended. This has no effect if ``fqbn`` is specified.
+* ``fqbn``: A dictionary that specifies the FQBNs that will be used to compile the sketch. The key is the target name and the value is a list
+  of FQBNs. The `default FQBNs <https://github.com/espressif/arduino-esp32/blob/a31a5fca1739993173caba995f7785b8eed6b30e/.github/scripts/sketch_utils.sh#L86-L91>`_
+  are used if this field is not specified. This overrides the default FQBNs and the ``fqbn_append`` field.
+
+The ``wifi`` test suite is a good example of how to use the ``ci.json`` file:
+
+.. literalinclude:: ../../tests/validation/wifi/ci.json
+    :language: json
+
+Documentation Checks
+^^^^^^^^^^^^^^^^^^^^
+
+The CI also checks the documentation for any compilation errors. This is important to ensure that the documentation layout is not broken.
+To build the documentation locally, please refer to the `documentation guidelines <guides/docs_contributing>`_.
+
+Code Style Checks
+^^^^^^^^^^^^^^^^^
+
+For checking the code style and other code quality checks, we use pre-commit hooks.
+These hooks will be automatically run by the CI when a Pull Request is marked as ``Status: Pending Merge``.
+You can check which hooks are being run in the ``.pre-commit-config.yaml`` file.
+
+Currently, we have hooks for the following tasks:
+
+* Formatters for C, C++, Python, Bash, JSON, Markdown and ReStructuredText files;
+* Linters for Python, Bash and prose (spoken language);
+* Checking for spelling errors in the code and documentation;
+* Removing trailing whitespaces and tabs in the code;
+* Checking for the presence of private keys and other sensitive information in the code;
+* Fixing the line endings and end of files (EOF) in the code;
+* And more.
+
+You can read more about the pre-commit hooks in the `pre-commit documentation <https://pre-commit.com/>`_.
+
+If you want to run the pre-commit hooks locally, you first need to install the required dependencies by running:
+
+.. code-block:: bash
+
+    pip install -U -r tools/pre-commit/requirements.txt
+
+Then, you can run the pre-commit hooks staging your changes and running:
+
+.. code-block:: bash
+
+    pre-commit run
+
+To run a specific hook, you can use the hook name as an argument. For example, to run the ``codespell`` hook, you would run:
+
+.. code-block:: bash
+
+    pre-commit run codespell
+
+If you want to run the pre-commit hooks automatically against the changed files on every ``git commit``,
+you can install the pre-commit hooks by running:
+
+.. code-block:: bash
+
+    pre-commit install
+
+Legal Part
+----------
+
+Before a contribution can be accepted, you will need to sign our contributor agreement. You will be prompted for this automatically as part of
+the Pull Request process.
+
+.. _Arduino style guide: https://docs.arduino.cc/learn/contributions/arduino-writing-style-guide
diff --git a/docs/en/esp-idf_component.rst b/docs/en/esp-idf_component.rst
new file mode 100644
index 00000000000..f38dc44ec0c
--- /dev/null
+++ b/docs/en/esp-idf_component.rst
@@ -0,0 +1,273 @@
+###############################
+Arduino as an ESP-IDF component
+###############################
+
+About
+-----
+
+You can use the Arduino framework as an ESP-IDF component. This allows you to use the Arduino framework in your ESP-IDF projects with the full flexibility of the ESP-IDF.
+
+This method is recommended for advanced users. To use this method, you will need to have the ESP-IDF toolchain installed.
+
+For a simplified method, see `Installing using Boards Manager <https://docs.espressif.com/projects/arduino-esp32/en/latest/installing.html#installing-using-boards-manager>`_.
+
+If you plan to use these modified settings multiple times, for different projects and targets, you can recompile the Arduino core with the new settings using the Arduino Static Library Builder.
+For more information, see the `Lib Builder documentation <lib_builder.html>`_.
+
+.. note:: Latest Arduino Core ESP32 version (3.0.X) is now compatible with `ESP-IDF v5.1 <https://github.com/espressif/esp-idf/tree/release/v5.1>`_. Please consider this compatibility when using Arduino as a component in ESP-IDF.
+
+For easiest use of Arduino framework as a ESP-IDF component, you can use the `IDF Component Manager <https://docs.espressif.com/projects/esp-idf/en/v5.1.4/esp32/api-guides/tools/idf-component-manager.html>`_ to add the Arduino component to your project.
+This will automatically clone the repository and its submodules. You can find the Arduino component in the `ESP Registry <https://components.espressif.com/components/espressif/arduino-esp32>`_ together with dependencies list and examples.
+
+Installation
+------------
+
+#. Download and install `ESP-IDF <https://github.com/espressif/esp-idf>`_.
+
+   * For more information see `Get Started <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/index.html#installation-step-by-step>`_.
+
+Installing using IDF Component Manager
+**************************************
+
+To add the Arduino component to your project using the IDF Component Manager, run the following command in your project directory:
+
+.. code-block:: bash
+
+    idf.py add-dependency "espressif/arduino-esp32^3.0.2"
+
+Or you can start a new project from a template with the Arduino component:
+
+.. code-block:: bash
+
+    idf.py create-project-from-example "espressif/arduino-esp32^3.0.2:hello_world"
+
+Manual installation of Arduino framework
+****************************************
+
+#. Create a blank ESP-IDF project (use sample_project from /examples/get-started) or choose one of the examples.
+#. In the project folder, create a new folder called ``components`` and clone this repository inside the newly created folder.
+
+.. code-block:: bash
+
+    mkdir -p components && \
+    cd components && \
+    git clone https://github.com/espressif/arduino-esp32.git arduino && \
+    cd arduino && \
+    git submodule update --init --recursive && \
+    cd ../.. && \
+    idf.py menuconfig
+
+.. note:: If you use Arduino with ESP-IDF often, you can place the arduino folder into global components folder.
+
+If you're targeting the ESP32-S2 or ESP32-S3 and you want to use USBHID classes such as ``USBHID``, ``USBHIDConsumerControl``, ``USBHIDGamepad``, ``USBHIDKeyboard``, ``USBHIDMouse``, ``USBHIDSystemControl``, or ``USBHIDVendor``:
+
+1. Clone these nested repos somewhere:
+
+.. code-block:: bash
+
+    git clone https://github.com/espressif/esp32-arduino-lib-builder.git esp32-arduino-lib-builder && \
+    git clone https://github.com/hathach/tinyusb.git esp32-arduino-lib-builder/components/arduino_tinyusb/tinyusb
+
+2. In the project folder, edit ``CMakeLists.txt`` and add the following before the ``project()`` line:
+
+.. code-block:: bash
+
+    set(EXTRA_COMPONENT_DIRS <path to esp32-arduino-lib-builder/components/arduino_tinyusb>)
+
+Configuration
+-------------
+
+Depending on one of the two following options, in the menuconfig set the appropriate settings.
+
+Go to the section ``Arduino Configuration --->``
+
+1. For usage of ``app_main()`` function - Turn off ``Autostart Arduino setup and loop on boot``
+2. For usage of ``setup()`` and ``loop()`` functions - Turn on ``Autostart Arduino setup and loop on boot``
+
+Experienced users can explore other options in the Arduino section.
+
+After the setup you can save and exit:
+
+- Save [S]
+- Confirm default filename [Enter]
+- Close confirmation window [Enter] or [Space] or [Esc]
+- Quit [Q]
+
+As the Arduino libraries use C++ features, you will need to swap some file extensions from ``.c`` to ``.cpp``:
+
+- In main folder rename file `main.c` to `main.cpp`.
+- In main folder open file `CMakeLists.txt` and change `main.c` to `main.cpp` as described below.
+
+Option 1. Using Arduino setup() and loop()
+******************************************
+
+Your main.cpp should be formatted like any other sketch. Don't forget to include ``Arduino.h``.
+
+.. code-block:: cpp
+
+    //file: main.cpp
+    #include "Arduino.h"
+
+    void setup(){
+      Serial.begin(115200);
+      while(!Serial){
+        ; // wait for serial port to connect
+      }
+    }
+
+    void loop(){
+        Serial.println("loop");
+        delay(1000);
+    }
+
+Option 2. Using ESP-IDF appmain()
+*********************************
+
+In main.cpp you need to implement ``app_main()`` and call ``initArduino();`` in it.
+
+Keep in mind that setup() and loop() will not be called in this case.
+Furthermore the ``app_main()`` is single execution as a normal function so if you need an infinite loop as in Arduino place it there.
+
+.. code-block:: cpp
+
+    //file: main.cpp
+    #include "Arduino.h"
+
+    extern "C" void app_main()
+    {
+      initArduino();
+
+      // Arduino-like setup()
+      Serial.begin(115200);
+      while(!Serial){
+        ; // wait for serial port to connect
+      }
+
+      // Arduino-like loop()
+      while(true){
+        Serial.println("loop");
+      }
+
+      // WARNING: if program reaches end of function app_main() the MCU will restart.
+    }
+
+Build, flash and monitor
+************************
+
+- For both options use command ``idf.py -p <your-board-serial-port> flash monitor``
+
+- The project will build, upload and open the serial monitor to your board
+
+  - Some boards require button combo press on the board: press-and-hold Boot button + press-and-release RST button, release Boot button
+
+  - After a successful flash, you may need to press the RST button again
+
+  - To terminate the serial monitor press ``Ctrl`` + ``]``
+
+Logging To Serial
+-----------------
+
+If you are writing code that does not require Arduino to compile and you want your `ESP_LOGx` macros to work in Arduino IDE, you can enable the compatibility by adding the following lines:
+
+.. code-block:: c
+
+    #ifdef ARDUINO_ARCH_ESP32
+    #include "esp32-hal-log.h"
+    #endif
+
+FreeRTOS Tick Rate (Hz)
+-----------------------
+
+The Arduino component requires the FreeRTOS tick rate `CONFIG_FREERTOS_HZ` set to 1000 Hz in `make menuconfig` -> `Component config` -> `FreeRTOS` -> `Tick rate`.
+
+Compilation Errors
+------------------
+
+As commits are made to ESP-IDF and submodules, the codebases can develop incompatibilities that cause compilation errors.
+If you have problems compiling, follow the instructions in `Issue #1142 <https://github.com/espressif/arduino-esp32/issues/1142>`_
+to roll ESP-IDF back to a different version.
+
+Adding arduino library
+----------------------
+
+There are few approaches:
+
+1. Add global library to ``components/arduino-esp32/libraries/new_library``
+2. Add local project library to ``examples/your_project/main/libraries/new_library``
+
+1 Adding global library
+***********************
+
+Download the library:
+
+.. code-block:: bash
+
+    cd ~/esp/esp-idf/components/arduino/
+    git clone --recursive git@github.com:Author/new_library.git libraries/new_library
+
+
+Edit file ``components/arduino-esp32/CMakeLists.txt``
+
+Get the source file list with shell command:
+
+.. code-block:: bash
+
+    find libraries/new_library/src/ -name '*.c' -o -name '*.cpp'
+      libraries/new_library/src/new_library.cpp
+      libraries/new_library/src/new_library_extra_file.c
+
+Locate block which starts with ``set(LIBRARY_SRCS`` and copy the list there. Now it should look something like this:
+
+.. code-block:: bash
+
+    set(LIBRARY_SRCS
+      libraries/ArduinoOTA/src/ArduinoOTA.cpp
+      libraries/AsyncUDP/src/AsyncUDP.cpp
+      libraries/new_library/src/new_library.cpp
+      libraries/new_library/src/new_library_extra_file.c
+
+
+After this add the library path to block which starts with ``set(includedirs``. It should look like this:
+
+.. code-block:: bash
+
+    set(includedirs
+      variants/${CONFIG_ARDUINO_VARIANT}/
+      cores/esp32/
+      libraries/ArduinoOTA/src
+      libraries/AsyncUDP/src
+      libraries/new_library/src
+
+
+2 Adding local library
+**********************
+
+Download the library:
+
+.. code-block:: bash
+
+    cd ~/esp/esp-idf/examples/your_project
+    mkdir components
+    git clone --recursive git@github.com:Author/new_library.git components/new_library
+
+Create new CMakeists.txt in the library folder: ``components/new_library/CMakeLists.txt``
+
+.. code-block:: bash
+
+    idf_component_register(SRCS "new_library.cpp" "another_source.c"
+                          INCLUDE_DIRS "."
+                          REQUIRES arduino-esp32
+                          )
+
+You can read more about CMakeLists in the IDF documentation regarding the `Build System <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/build-system.html>`_
+
+Tip
+---
+
+If you want to use arduino-esp32 both as an ESP-IDF component and with Arduino IDE you can simply create a symlink:
+
+.. code-block:: bash
+
+    ln -s ~/Arduino/hardware/espressif/esp32  ~/esp/esp-idf/components/arduino-esp32
+
+This will allow you to install new libraries as usual with Arduino IDE. To use them with IDF component, use ``add_lib.sh -e ~/Arduino/libraries/New_lib``
diff --git a/docs/en/external_libraries_test.rst b/docs/en/external_libraries_test.rst
new file mode 100644
index 00000000000..4dda53cda0b
--- /dev/null
+++ b/docs/en/external_libraries_test.rst
@@ -0,0 +1,132 @@
+##########################
+External Libraries Testing
+##########################
+
+About
+-----
+
+External libraries testing is a compilation test for listed libraries on arduino-esp32 master branch. The test was made for users, so they can check which libraries are compiling without errors on which SoC.
+External libraries test is running periodically (once a week) against master branch and can also run on PR by adding a label ``lib_test``.
+The test is running on all supported ESP32 chips.
+
+.. note::
+  As the test is just a compilation of example, that does not guarantee that the library/sketch will run without any problems after flashing it on your device.
+
+How to Add Library to Test
+--------------------------
+
+To add a library to the CI test you need to add your library to the `lib.json`_. file located in ``./github/workflows/``.
+
+.. note::
+  Please add the libraries to the `lib.json`_ in alphabetical order, thanks.
+
+List of parameters:
+*******************
+
+Where the library will be installed from (use only 1 option):
+
+* ``name`` - Name of the Library in Arduino Library Manager.
+* ``source-url`` - URL to the library github repository (example: "https://github.com/Arduino-IRremote/Arduino-IRremote.git"). Use when your Library is not listed in Arduino Library Manager.
+
+Required:
+
+* ``exclude_targets`` - List of targets to be excluded from testing. Use only when the SoC dont support used peripheral.
+* ``sketch_path`` - Path / paths to the sketch / sketches to be tested.
+
+Optional:
+
+* ``version`` - Version of the library.
+* ``required-libs`` - Libraries that are necessary to be installed to compile the tested library.
+* ``destination-name`` - Folder name used for the installation of library (use only when needed).
+
+
+Example of library addition from Arduino Library Manager with ESP32-S2 excluded:
+********************************************************************************
+
+  .. code-block:: json
+
+    {
+        "name": "ArduinoBLE",
+        "exclude_targets": [
+            "esp32s2"
+        ],
+        "sketch_path": [
+            "~/Arduino/libraries/ArduinoBLE/examples/Central/Scan/Scan.ino"
+        ]
+    }
+
+Example of library addition from Github URL with required library:
+******************************************************************
+
+  .. code-block:: json
+
+    {
+        "source-url": "https://github.com/me-no-dev/ESPAsyncWebServer.git",
+        "required-libs": [
+            {"source-url": "https://github.com/me-no-dev/AsyncTCP.git"}
+        ],
+        "exclude_targets": [],
+        "sketch_path": [
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/CaptivePortal/CaptivePortal.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/ESP_AsyncFSBrowser/ESP_AsyncFSBrowser.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/regex_patterns/regex_patterns.ino",
+            "~/Arduino/libraries/ESPAsyncWebServer/examples/simple_server/simple_server.ino"
+        ]
+    },
+
+Submit a PR
+***********
+
+* Open a PR with the changes and someone from Espressif team will add a label ``lib_test`` to the PR and CI will run the test to check, if the addition is fine and the library/example is compiling.
+
+* After merging your PR, the next scheduled test will test your library and add the results to the `LIBRARIES_TEST.md`_.
+
+Test Results
+------------
+
+Icons meaning
+*************
+
+There is a number before each icon, which means the number of examples which were compiled with that result.
+
+* |success| - Compilation was successful.
+
+* |warning| - Compilation was successful, but some warnings occurs.
+
+* |fail| - Compilation failed.
+
+* ``N/A`` - Not tested (target is in exclude_targets list).
+
+Scheduled test result
+*********************
+
+You can check the results in `LIBRARIES_TEST.md`_.
+
+The results file example:
+
+.. image:: ../_static/external_library_test_schedule.png
+  :width: 600
+
+Pull Request test result
+************************
+
+If the test run on Pull Request, it will compile all libraries and sketches 2 times (before/after changes in PR) to see, if the PR is breaking/fixing libraries.
+In the table the results are in order ``BEFORE -> AFTER``.
+
+.. image:: ../_static/external_library_test_pr.png
+  :width: 600
+
+.. |success| image:: ../_static/green_checkmark.png
+   :height: 2ex
+   :class: no-scaled-link
+
+.. |warning| image:: ../_static/warning.png
+   :height: 2ex
+   :class: no-scaled-link
+
+.. |fail| image:: ../_static/cross.png
+   :height: 2ex
+   :class: no-scaled-link
+
+.. _LIBRARIES_TEST.md: https://github.com/espressif/arduino-esp32/blob/gh-pages/LIBRARIES_TEST.md
+.. _lib.json: https://github.com/espressif/arduino-esp32/.github/workflow/lib.json
diff --git a/docs/en/faq.rst b/docs/en/faq.rst
new file mode 100644
index 00000000000..97520b35673
--- /dev/null
+++ b/docs/en/faq.rst
@@ -0,0 +1,17 @@
+##########################
+Frequently Asked Questions
+##########################
+
+How to modify an sdkconfig option in Arduino?
+---------------------------------------------
+
+Arduino-esp32 project is based on ESP-IDF. While ESP-IDF supports configuration of various compile-time options (known as "Kconfig options" or "sdkconfig options") via a "menuconfig" tool, this feature is not available in Arduino IDE.
+
+To use the arduino-esp32 core with a modified sdkconfig option, you need to use ESP-IDF to compile Arduino libraries. Please see :doc:`esp-idf_component` and :doc:`lib_builder` for the two solutions available.
+
+Note that modifying ``sdkconfig`` or ``sdkconfig.h`` files found in the arduino-esp32 project tree **does not** result in changes to these options. This is because ESP-IDF libraries are included into the arduino-esp32 project tree as pre-built libraries.
+
+How to compile libs with different debug level?
+-----------------------------------------------
+
+The short answer is ``esp32-arduino-lib-builder/configs/defconfig.common:44``. A guide explaining the process can be found here <guides/core_debug>
diff --git a/docs/en/getting_started.rst b/docs/en/getting_started.rst
new file mode 100644
index 00000000000..1b0f1bba87a
--- /dev/null
+++ b/docs/en/getting_started.rst
@@ -0,0 +1,162 @@
+###############
+Getting Started
+###############
+
+About Arduino ESP32
+-------------------
+
+Welcome to the Arduino ESP32 support documentation! Here you will find important information on how to use the project.
+
+First Things First
+------------------
+
+.. note::
+    Before continuing, we must be clear that this project is supported by `Espressif Systems`_ and the community.
+    Everyone is more than welcome to contribute back to this project.
+
+ESP32 is a single 2.4 GHz Wi-Fi-and-Bluetooth SoC (System On a Chip) designed by `Espressif Systems`_.
+
+ESP32 is designed for mobile, wearable electronics, and Internet-of-Things (IoT) applications. It features all the state-of-the-art characteristics
+of low-power chips, including fine-grained clock gating, multiple power modes,and dynamic power scaling. For instance, in a low-power IoT sensor
+hub application scenario, ESP32 is woken-up periodically and only when a specified condition is detected. Low-duty cycle is used to minimize the
+amount of energy that the chip expends.
+
+The output of the power amplifier is also adjustable, thus contributing to an optimal trade-off between communication range, data rate and
+power consumption.
+
+The ESP32 series is available as a chip or module.
+
+
+.. _supported_socs:
+
+Supported SoC's
+---------------
+
+Here are the ESP32 series supported by the Arduino-ESP32 project:
+
+========== ====== =========== =================================
+SoC        Stable Development Datasheet
+========== ====== =========== =================================
+ESP32      Yes    Yes         `ESP32`_
+ESP32-C3   Yes    Yes         `ESP32-C3`_
+ESP32-C6   Yes    Yes         `ESP32-C6`_
+ESP32-H2   Yes    Yes         `ESP32-H2`_
+ESP32-P4   Yes    Yes         `ESP32-P4`_
+ESP32-S2   Yes    Yes         `ESP32-S2`_
+ESP32-S3   Yes    Yes         `ESP32-S3`_
+========== ====== =========== =================================
+
+.. note::
+    ESP32-C2 is also supported by Arduino-ESP32 but requires using Arduino as an ESP-IDF component or rebuilding the static libraries.
+    For more information, see the `Arduino as an ESP-IDF component documentation <esp-idf_component.html>`_ or the
+    `Lib Builder documentation <lib_builder.html>`_, respectively.
+
+See `Boards <boards/boards.html>`_ for more details about ESP32 development boards.
+
+Arduino Core Reference
+----------------------
+
+This documentation is built on the ESP32 and we are not going to cover the common Arduino API. To see the Arduino reference documentation,
+please consider reading the official documentation.
+
+Arduino Official Documentation: `Arduino Reference`_.
+
+Supported Operating Systems
+---------------------------
+
++-------------------+-------------------+-------------------+
+| |windows-logo|    | |linux-logo|      | |macOS-logo|      |
++-------------------+-------------------+-------------------+
+| Windows           | Linux             | macOS             |
++-------------------+-------------------+-------------------+
+
+.. |windows-logo| image:: ../_static/logo_windows.png
+.. |linux-logo| image:: ../_static/logo_linux.png
+.. |macOS-logo| image:: ../_static/logo_macos.png
+
+Supported IDEs
+---------------------------
+
+Here is the list of supported IDE for Arduino ESP32 support integration.
+
++-------------------+
+| |arduino-logo|    |
++-------------------+
+| Arduino IDE       |
++-------------------+
+
+.. |arduino-logo| image:: ../_static/logo_arduino.png
+
+See `Installing Guides <installing.html>`_ for more details on how to install the Arduino ESP32 support.
+
+Support
+-------
+
+This is an open project and it's supported by the community. Fell free to ask for help in one of the community channels.
+
+Community
+---------
+
+The Arduino community is huge! You can find a lot of useful content on the Internet.
+Here are some community channels where you may find information and ask for some help, if needed.
+
+- `ESP32 Forum`_: Official Espressif Forum.
+- `ESP32 Forum - Arduino`_: Official Espressif Forum for Arduino related discussions.
+- `ESP32 Forum - Hardware`_: Official Espressif Forum for Hardware related discussions.
+- `Espressif Developer Portal`_: Official Espressif Developer Portal with tutorials, examples, workshops, and more.
+- `Arduino Core for Espressif (Discord)`_: Official Espressif Discord channel for the Arduino Core.
+- `Espressif MCUs (Discord)`_
+- `ESP32 on Reddit`_
+
+Issues Reporting
+----------------
+
+Before opening a new issue, please read this:
+
+Be sure to search for a similar reported issue. This avoids duplicating or creating noise in the GitHub Issues reporting.
+We also have the troubleshooting guide to save your time on the most common issues reported by users.
+
+For more details about creating new Issue, see the `Issue Template <https://github.com/espressif/arduino-esp32/blob/master/.github/ISSUE_TEMPLATE/Issue-report.yml>`_.
+
+If you have any new idea, see the `Feature request Template <https://github.com/espressif/arduino-esp32/blob/master/.github/ISSUE_TEMPLATE/Feature-request.yml>`_.
+
+First Steps
+-----------
+
+Here are the first steps to get the Arduino ESP32 support running.
+
+To install Arduino-ESP32, please see the dedicated section on the Installation guide. We recommend you install it using the boards manager.
+
+.. toctree::
+    :maxdepth: 2
+
+    How to Install <installing>
+    Development Boards <boards/boards>
+
+Examples
+--------
+
+After installing the toolchain into your environment, you will be able to see all the dedicated examples for the ESP32. These examples are located
+in the examples menu or inside each library folder.
+
+    https://github.com/espressif/arduino-esp32/tree/master/libraries
+
+There is also a `list of examples <https://techtutorialsx.com/category/esp32/>`_ managed outside of Espressif, so check them out.
+
+.. include:: common/datasheet.inc
+
+Resources
+---------
+
+.. _Espressif Systems: https://www.espressif.com
+.. _Espressif Product Selector: https://products.espressif.com/
+.. _Espressif Developer Portal: https://developer.espressif.com/
+.. _Arduino.cc: https://www.arduino.cc/en/Main/Software
+.. _Arduino Reference: https://www.arduino.cc/reference/en/
+.. _ESP32 Forum: https://esp32.com
+.. _ESP32 Forum - Arduino: https://esp32.com/viewforum.php?f=19
+.. _ESP32 Forum - Hardware: https://esp32.com/viewforum.php?f=12
+.. _Arduino Core for Espressif (Discord): https://discord.gg/8xY6e9crwv
+.. _Adafruit (Discord): https://discord.gg/adafruit
+.. _Espressif MCUs (Discord): https://discord.com/invite/XqnZPbF
+.. _ESP32 on Reddit: https://www.reddit.com/r/esp32
diff --git a/docs/en/guides/core_compatibility.rst b/docs/en/guides/core_compatibility.rst
new file mode 100644
index 00000000000..cb530ac5e7c
--- /dev/null
+++ b/docs/en/guides/core_compatibility.rst
@@ -0,0 +1,44 @@
+Compatibility Guide for ESP32 Arduino Core
+==========================================
+
+Introduction
+------------
+
+Welcome to the compatibility guide for library developers aiming to support multiple versions of the ESP32 Arduino core. This documentation provides essential tips and best practices for ensuring compatibility with 2.x, 3.x and future versions of the ESP32 Arduino core.
+
+Code Adaptations
+----------------
+
+To ensure compatibility with both versions of the ESP32 Arduino core, developers should utilize conditional compilation directives in their code. Below is an example of how to conditionally include code based on the ESP32 Arduino core version::
+
+    .. code-block:: cpp
+
+      #ifdef ESP_ARDUINO_VERSION_MAJOR
+      #if ESP_ARDUINO_VERSION >= ESP_ARDUINO_VERSION_VAL(3, 0, 0)
+          // Code for version 3.x
+      #else
+          // Code for version 2.x
+      #endif
+      #else
+          // Code for version 1.x
+      #endif
+
+Version Print
+-------------
+
+To easily print the ESP32 Arduino core version at runtime, developers can use the `ESP_ARDUINO_VERSION_STR` macro. Below is an example of how to print the ESP32 Arduino core version::
+
+    .. code-block:: cpp
+
+      Serial.printf(" ESP32 Arduino core version: %s\n", ESP_ARDUINO_VERSION_STR);
+
+API Differences
+---------------
+
+Developers should be aware, that there may be API differences between major versions of the ESP32 Arduino core. For this we created a `Migration guide <https://docs.espressif.com/projects/arduino-esp32/en/latest/migration_guides.html>`_. to help developers transition from between major versions of the ESP32 Arduino core.
+
+Library Testing
+---------------
+
+We have added an External Library Test CI job, which tests external libraries with the latest version of the ESP32 Arduino core to help developers ensure compatibility with the latest version of the ESP32 Arduino core.
+If you want to include your library in the External Library Test CI job, please follow the instructions in the `External Libraries Test <https://docs.espressif.com/projects/arduino-esp32/en/latest/esp32/external_libraries_test.html>`_.
diff --git a/docs/en/guides/core_debug.rst b/docs/en/guides/core_debug.rst
new file mode 100644
index 00000000000..c2a0158e225
--- /dev/null
+++ b/docs/en/guides/core_debug.rst
@@ -0,0 +1,37 @@
+##################################
+Compile Arduino libs with ESP_LOGx
+##################################
+
+There are 2 primary approaches and both of them involve editing file ``configs/defconfig.common``.
+Edit the file directly and then build.
+Later you can ``git restore configs/defconfig.common`` to go back.
+Copy the file ``cp configs/defconfig.common configs/defconfig.debug`` and edit the debug version.
+
+``vim configs/defconfig.common`` or ``vim configs/defconfig.debug``
+
+Edit **line 44** containing by default ``CONFIG_LOG_DEFAULT_LEVEL_ERROR=y`` to one of the following lines depending on your desired log level:
+
+.. code-block:: bash
+
+   CONFIG_LOG_DEFAULT_LEVEL_NONE=y # No output
+   CONFIG_LOG_DEFAULT_LEVEL_ERROR=y # Errors - default
+   CONFIG_LOG_DEFAULT_LEVEL_WARN=y # Warnings
+   CONFIG_LOG_DEFAULT_LEVEL_INFO=y # Info
+   CONFIG_LOG_DEFAULT_LEVEL_DEBUG=y # Debug
+   CONFIG_LOG_DEFAULT_LEVEL_VERBOSE=y # Verbose
+
+Then simply build the libs for all SoCs or one specific SoC. Note that building for all SoCs takes a lot of time, so if you are working only with specific SoC(s), build only for those.
+
+.. note::
+   If you have copied the ``defconfig`` file and the debug settings are in file ``configs/defconfig.debug`` add flag ``debug`` to compilation command.
+   Example : ``./build.sh debug``
+
+   - **Option 1**: Build for all SoCs: ``./build.sh``
+   - **Option 2**: Build for one SoC: ``./build.sh -t <soc>``. The exact text to choose the SoC:
+
+      - ``esp32``
+      - ``esp32s2``
+      - ``esp32c3``
+      - ``esp32s3``
+      - Example: ``./build.sh -t esp32``
+      - A wrong format or non-existing SoC will result in the error sed: can't read sdkconfig: No such file or directory
diff --git a/docs/en/guides/docs_contributing.rst b/docs/en/guides/docs_contributing.rst
new file mode 100644
index 00000000000..20dc4c84cab
--- /dev/null
+++ b/docs/en/guides/docs_contributing.rst
@@ -0,0 +1,334 @@
+#####################################
+Documentation Contribution Guidelines
+#####################################
+
+Introduction
+------------
+
+This is a guideline for the Arduino ESP32 project documentation. The idea for this guideline is to show how to start collaborating on the project.
+
+The guideline works to give you the directions and to keep the documentation more concise, helping users to better understand the structure.
+
+About Documentation
+-------------------
+
+We all know how important documentation is. This project is no different.
+
+This documentation was created in a collaborative and open way, letting everyone contribute, from a small typo fix to a new chapter writing. We try to motivate our community by giving all the support needed through this guide.
+
+The documentation is in **English only**. Future translations can be added when we finish the essential content in English first.
+
+How to Collaborate
+------------------
+
+Everyone with some knowledge to share is welcome to collaborate.
+
+One thing you need to consider is the fact that your contribution must be concise and assertive since it will be used by people developing projects. The information is very important for everyone, be sure you are not making the developer's life harder!
+
+Documentation Guide
+-------------------
+
+This documentation is based on the `Sphinx`_ with `reStructuredText`_ and hosted by `ReadTheDocs`_.
+
+If you want to get started with `Sphinx`_, see the official documentation:
+
+* `Documentation Index <https://www.sphinx-doc.org/en/master/usage/restructuredtext/index.html>`_
+* `Basics <https://www.sphinx-doc.org/en/master/usage/restructuredtext/basics.html>`_
+* `Directives <https://www.sphinx-doc.org/en/master/usage/restructuredtext/directives.html>`_
+
+First Steps
+***********
+
+Before starting your collaboration, you need to get the documentation source code from the Arduino-ESP32 project.
+
+* **Step 1** - Fork the `Arduino-ESP32`_ to your GitHub account.
+* **Step 2** - Check out the recently created fork.
+* **Step 3** - Create a new branch for the changes/addition to the docs.
+* **Step 4** - Write!
+
+Requirements
+************
+
+To properly work with the documentation, you need to install some packages in your system.
+
+.. code-block::
+
+    pip install -U Sphinx
+    pip install -r requirements.txt
+
+The requirements file is under the ``docs`` folder.
+
+Using Visual Studio Code
+************************
+
+If you are using the Visual Studio Code, you can install some extensions to help you while writing documentation.
+
+`reStructuredText Pack <https://marketplace.visualstudio.com/items?itemName=lextudio.restructuredtext-pack>`_
+
+We also recommend you install to grammar check extension to help you to review English grammar.
+
+`Grammarly <https://marketplace.visualstudio.com/items?itemName=znck.grammarly>`_
+
+Building
+********
+
+To build the documentation and generate the HTML files, you can use the following command inside the ``docs`` folder. After a successful build, you can check the files inside the `_build/en/generic/html` folder.
+
+.. code-block::
+
+    build-docs -l en
+
+This step is essential to ensure that there are no syntax errors and also to see the final result.
+
+If everything is ok, you will see some output logs similar to this one:
+
+.. code-block::
+
+    Running Sphinx v2.3.1
+    loading pickled environment... done
+    building [mo]: targets for 0 po files that are out of date
+    building [html]: targets for 35 source files that are out of date
+    updating environment: [extensions changed ('sphinx_tabs.tabs')] 41 added, 3 changed, 0 removed
+    reading sources... [100%] tutorials/tutorials
+    looking for now-outdated files... none found
+    pickling environment... done
+    checking consistency... done
+    preparing documents... done
+    writing output... [100%] tutorials/tutorials
+    generating indices...  genindexdone
+    writing additional pages...  searchdone
+    copying images... [100%] tutorials/../../_static/tutorials/peripherals/tutorial_peripheral_diagram.png
+    copying static files... ... done
+    copying extra files... done
+    dumping search index in English (code: en)... done
+    dumping object inventory... done
+    build succeeded.
+
+The HTML pages are in ``_build/en/generic/html``.
+
+Sections
+--------
+
+The Arduino ESP32 is structured in some sections to make it easier to maintain. Here is a brief description of this structure.
+
+API
+***
+
+In this section, you will include all the documentation about drivers, libraries, and any other related to the core.
+
+In this section, we do not add general information. For more general information, we have sections for other related parts, like the FAQ, library builder, troubleshooting, etc.
+
+Boards
+******
+
+Here is the place to add any special guide on the development boards, pin layout, schematics, and any other relevant content.
+
+Common
+******
+
+In this folder, you can add all common information used in several different places. This helps to make documentation easily maintainable.
+
+
+Guides
+******
+
+This is the place to add the guides for common applications, IDEs configuration, and any other information that can be used as a guideline.
+
+Tutorials
+*********
+
+If you want to add a specific tutorial related to the Arduino core for ESP32, this is the place. The intention is not to create a blog or a demo area, but this can be used to add some complex description or to add some more information about APIs.
+
+Images and Assets
+*****************
+
+All the files used on the documentation must be stored in the ``_static`` folder. Be sure that the content used is not with any copyright restriction.
+
+Documentation Rules
+-------------------
+
+Here are some guidelines to help you. We also recommend copying a sample file from the same category you are creating.
+
+This will help you to follow the structure as well as to get inspired.
+
+Basic Structure
+***************
+
+To help you create a new section from scratch, we recommend you include this structure in your content if it applies.
+
+* **About** - Brief description of the document.
+    * Description of the peripheral, driver, protocol, including all different modes and configurations.
+* **API** - Description of each public function, macros, and structs.
+* **Basic Usage**
+* **Example Application**
+
+About Section
+^^^^^^^^^^^^^
+
+In this section, you need to add a brief description of the API. If you are describing a peripheral API, you should explain a little bit about the peripheral and the working modes, if it's applicable.
+
+API Functions
+^^^^^^^^^^^^^
+
+To add a new function description, you must know that the users only have access to the public functions.
+
+
+Here is an example of how to add the function description from `I2C API <https://docs.espressif.com/projects/arduino-esp32/en/latest/api/i2c.html>`_:
+
+.. code-block::
+
+    setPins
+    ^^^^^^^
+
+    This function is used to define the ``SDA`` and ``SCL`` pins.
+
+    .. note:: Call this function before ``begin`` to change the pins from the default ones.
+
+    .. code-block:: arduino
+
+        bool setPins(int sdaPin, int sclPin);
+
+    * ``sdaPin`` sets the GPIO to be used as the I2C peripheral data line.
+
+    * ``sclPin`` sets the GPIO to be used as the I2C peripheral clock line.
+
+    The default pins may vary from board to board. On the *Generic ESP32* the default I2C pins are:
+
+    * ``sdaPin`` **GPIO21**
+
+    * ``sclPin`` **GPIO22**
+
+    This function will return ``true`` if the peripheral was configured correctly.
+
+Be sure to include a very comprehensive description, add all the parameters in and out, and describe the desired output.
+
+If the function uses a specific structure, you can also describe the structure in the same function block or add a specific section if the structure is shared with other functions.
+
+Basic Usage
+^^^^^^^^^^^
+
+Some APIs are more complex to use or require more steps in order to configure or initialize. If the API is not straightforward in terms of usability, please consider adding a how-to-use section describing all the steps to get the API configured.
+
+Here is an example:
+
+.. code-block::
+
+    Basic Usage
+    ^^^^^^^^^^^
+
+    To start using I2C as slave mode on the Arduino, the first step is to include the ``Wire.h`` header to the sketch.
+
+    .. code-block:: arduino
+
+        #include "Wire.h"
+
+    Before calling ``begin``, you must create two callback functions to handle the communication with the master device.
+
+    .. code-block:: arduino
+
+        Wire.onReceive(onReceive);
+
+    and
+
+    .. code-block:: arduino
+
+        Wire.onRequest(onRequest);
+
+    The ``onReceive`` will handle the request from the ``master`` device upon a slave read request and the ``onRequest`` will handle the answer to the master.
+
+    Now, we can start the peripheral configuration by calling ``begin`` function with the device address.
+
+    .. code-block:: arduino
+
+        Wire.begin((uint8_t)I2C_DEV_ADDR);
+
+    By using ``begin`` without any arguments, all the settings will be done by using the default values. To set the values on your own, see the function description. This function is described here: `i2c begin`_
+
+
+
+Example Application
+^^^^^^^^^^^^^^^^^^^
+It is very important to include at least one application example or a code snippet to help people using the API.
+
+If the API does not have any application example, you can embed the code directly. However, if the example is available, you must include it as a literal block.
+
+.. code-block::
+
+    .. literalinclude:: ../../../libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino
+        :language: arduino
+
+
+Sphinx Basics
+-------------
+
+Heading Levels
+**************
+
+The heading levels used on this documentation are:
+
+* **H1**: - (Dash)
+* **H2**: * (Asterisk)
+* **H3**: ^ (Circumflex)
+* **H4**: # (Sharp)
+
+Code Block
+**********
+
+To add a code block, you can use the following structure:
+
+.. code-block::
+
+    .. code-block:: arduino
+        bool begin(); //Code example
+
+Links
+*****
+
+To include links to external content, you can use two ways.
+
+* First option:
+
+.. code-block::
+
+    `Arduino Wire Library`_
+
+    _Arduino Wire Library: https://www.arduino.cc/en/reference/wire
+
+* Second option:
+
+.. code-block::
+
+    `Arduino Wire Library <https://www.arduino.cc/en/reference/wire>`_
+
+Images
+******
+
+To include images in the docs, first, add all the files into the ``_static`` folder with a filename that makes sense for the topic.
+
+After that, you can use the following structure to include the image in the docs.
+
+.. code-block::
+
+    .. figure:: ../../_static/arduino_i2c_master.png
+        :align: center
+        :width: 720
+        :figclass: align-center
+
+You can adjust the ``width`` according to the image size.
+
+Be sure the file size does not exceed 600 kB.
+
+Support
+*******
+
+If you need support on the documentation, you can ask a question in the discussion `here <https://github.com/espressif/arduino-esp32/discussions>`_.
+
+Additional Guidelines
+---------------------
+
+If you want to contribute with code on the Arduino ESP32 core, be sure to follow the `ESP-IDF Documenting Code <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/contribute/documenting-code.html>`_ as a reference.
+
+.. _Arduino-ESP32: https://github.com/espressif/arduino-esp32
+.. _Sphinx: https://www.sphinx-doc.org/en/master/
+.. _ReadTheDocs: https://readthedocs.org/
+.. _reStructuredText: https://docutils.sourceforge.io/rst.html
diff --git a/docs/en/guides/guides.rst b/docs/en/guides/guides.rst
new file mode 100644
index 00000000000..4aa538a7e22
--- /dev/null
+++ b/docs/en/guides/guides.rst
@@ -0,0 +1,10 @@
+######
+Guides
+######
+
+.. toctree::
+    :caption: Guides:
+    :maxdepth: 1
+    :glob:
+
+    *
diff --git a/docs/en/guides/tools_menu.rst b/docs/en/guides/tools_menu.rst
new file mode 100644
index 00000000000..f4ea4929944
--- /dev/null
+++ b/docs/en/guides/tools_menu.rst
@@ -0,0 +1,256 @@
+######################
+Arduino IDE Tools Menu
+######################
+
+Introduction
+------------
+
+This guide is a walkthrough of the Arduino IDE configuration menu for the ESP32 System on Chip (SoC's). In this guide, you will see the most relevant configuration
+to get your project optimized and working.
+
+Since some boards and SoC's may vary in terms of hardware configuration, be sure you know all the board characteristics that you are using, like flash memory size, SoC variant (ESP32 family), PSRAM, etc.
+
+.. note:: To help you identify the characteristics, you can see the `Espressif Product Selector`_.
+
+Arduino IDE
+-----------
+
+The Arduino IDE is widely used for ESP32 on Arduino development and offers a wide variety of configurations.
+
+Tools Menu
+----------
+
+To properly configure your project build and flash, some settings must be done in order to get it compiled and flashed without any issues.
+Some boards are natively supported and almost no configuration is required. However, if your is not yet supported or you have a custom board, you need to configure the environment by yourself.
+
+For more details or to add a new board, see the `boards.txt`_ file.
+
+Generic Options
+---------------
+
+Most of the options are available for every ESP32 family. Some options will be available only for specific targets, like the USB configuration.
+
+Board
+*****
+
+This option is the target board and must be selected in order to get all the default configuration settings. Once you select the correct board, you will see that some configurations will be automatically selected, but be aware that some boards can have multiple versions (i.e different flash sizes).
+
+To select the board, go to ``Tools -> Board -> ESP32 Arduino`` and select the target board.
+
+If your board is not present on this list, you can select the generic ``ESP32-XX Dev Module``.
+
+Currently, we have one generic development module for each of the supported targets.
+
+If the board selected belongs to another SoC family, you will see the following information at the build output:
+
+    ``A fatal error occurred: This chip is ESP32 not ESP32-S2. Wrong --chip argument?``
+
+Upload Speed
+************
+
+To select the flashing speed, change the ``Tools -> Upload Speed``. This value will be used for flashing the code to the device.
+
+.. note:: If you have issues while flashing the device at high speed, try to decrease this value. This could be due to the external serial-to-USB chip limitations.
+
+CPU Frequency
+*************
+
+On this option, you can select the CPU clock frequency. This option is critical and must be selected according to the high-frequency crystal present on the board and the radio usage (Wi-Fi and Bluetooth).
+
+In some applications, reducing the CPU clock frequency is recommended in order to reduce power consumption.
+
+If you don't know why you should change this frequency, leave the default option.
+
+Flash Frequency
+***************
+
+Use this function to select the flash memory frequency. The frequency will be dependent on the memory model.
+
+* **40 MHz**
+* **80 MHz**
+
+If you don't know if your memory supports **80 MHz**, you can try to upload the sketch using the **80 MHz** option and watch the log output via the serial monitor.
+
+.. note:: In some boards/SoC, the flash frequency is automatically selected according to the flash mode. In some cases (i.e ESP32-S3), the flash frequency is up to 120 MHz.
+
+Flash Mode
+**********
+
+This option is used to select the SPI communication mode with the flash memory.
+
+Depending on the application, this mode can be changed in order to increase the flash communication speed.
+
+* **QIO** - Quad I/O Fast Read
+    * Four SPI pins are used to write to the flash and to read from the flash.
+
+* **DIO** - Dual I/O Fast Read
+    * Two SPI pins are used to write to the flash and to read from the flash.
+
+* **QOUT** - Quad Output Fast Read
+    * Four SPI pins are used to read the flash data.
+
+* **DOUT** - Dual Output Fast Read
+    * Two SPI pins are used to read flash data.
+
+* **OPI** - Octal I/O
+    * Eight SPI pins are used to write and to read from the flash.
+
+If you don't know how the board flash is physically connected or the flash memory model, try the **QIO** at **80 MHz** first.
+
+Flash Size
+**********
+
+This option is used to select the flash size. The flash size should be selected according to the flash model used on your board.
+
+* **2 MB** (16 Mb)
+* **4 MB** (32 Mb)
+* **8 MB** (64 Mb)
+* **16 MB** (128 Mb)
+
+If you choose the wrong size, you may have issues when selecting the partition scheme.
+
+Embedded Flash
+^^^^^^^^^^^^^^
+
+Some SoC has embedded flash. The ESP32-S3 is a good example.
+
+.. note:: Check the manufacturer part number of your SoC/module to see the right version.
+
+Example: **ESP32-S3FH4R2**
+
+This particular ESP32-S3 variant comes with 4 MB Flash and 2 MB PSRAM.
+
+**Options for Embedded Flash**
+
+* **Fx4** 4 MB Flash (*QIO*)
+* **Fx8** 8 MB Flash (*QIO*)
+* **V** 1.8 V SPI
+
+The **x** stands for the temperature range specification.
+
+* **H** High Temperature (*-40 to 85ºC*)
+* **N** Low Temperature (*-40 to 65ºC*)
+
+For more details, please see the corresponding datasheet at `Espressif Product Selector`_.
+
+Partition Scheme
+****************
+
+This option is used to select the partition model according to the flash size and the resources needed, like storage area and OTA (Over The Air updates).
+
+.. note:: Be careful selecting the right partition according to the flash size. If you select the wrong partition, the system will crash.
+
+Core Debug Level
+****************
+
+This option is used to select the Arduino core debugging level to be printed to the serial debug.
+
+* **None** - Prints nothing.
+* **Error** - Only at error level.
+* **Warning** - Only at warning level and above.
+* **Info** - Only at info level and above.
+* **Debug** - Only at debug level and above.
+* **Verbose** - Prints everything.
+
+PSRAM
+*****
+
+The PSRAM is an internal or external extended RAM present on some boards, modules or SoC.
+
+This option can be used to ``Enable`` or ``Disable`` PSRAM. In some SoCs, you can select the PSRAM mode as the following.
+
+* **QSPI PSRAM** - Quad PSRAM
+* **OPI PSRAM** - Octal PSRAM
+
+Embedded PSRAM
+^^^^^^^^^^^^^^
+
+Some SoC has embedded PSRAM. The ESP32-S3 is a good example.
+
+Example: **ESP32-S3FH4R2**
+
+This particular ESP32-S3 comes with 4 MB Flash and 2 MB PSRAM.
+
+**Options for Embedded Flash and PSRAM**
+
+* **R2** 2 MB PSRAM (*QSPI*)
+* **R8** 8 MB PSRAM (*OPI*)
+* **V** 1.8 V SPI
+
+The **x** stands for the temperature range specification.
+
+* **H** High Temperature (*-40 to 85ºC*)
+* **N** Low Temperature (*-40 to 65ºC*)
+
+For more details, please see the corresponding datasheet at `Espressif Product Selector`_.
+
+Arduino Runs On
+***************
+
+This function is used to select the core that runs the Arduino core. This is only valid if the target SoC has 2 cores.
+
+When you have some heavy task running, you might want to run this task on a different core than the Arduino tasks. For this reason, you have this configuration to select the right core.
+
+Events Run On
+*************
+
+This function is also used to select the core that runs the Arduino events. This is only valid if the target SoC has 2 cores.
+
+Erase All Flash Before Sketch Upload
+************************************
+
+This option selects the flash memory region to be erased before uploading the new sketch.
+
+* **Disabled** - Upload the sketch without erasing all flash contents. (Default)
+* **Enabled** - Erase all flash contents before uploading the sketch.
+
+Port
+****
+
+This option is used to select the serial port to be used on the flashing and monitor.
+
+USB Options
+-----------
+
+Some ESP32 families have a USB peripheral. This peripheral can be used for flashing and debugging.
+
+To see the supported list for each SoC, see this section: `Libraries <../libraries.html>`_.
+
+The USB option will be available only if the correct target is selected.
+
+USB CDC On Boot
+***************
+
+The USB Communications Device Class, or USB CDC, is a class used for basic communication to be used as a regular serial controller (like RS-232).
+
+This class is used for flashing the device without any other external device attached to the SoC.
+
+This option can be used to ``Enable`` or ``Disable`` this function at the boot. If this option is ``Enabled``, once the device is connected via USB, one new serial port will appear in the list of the serial ports.
+Use this new serial port for flashing the device.
+
+This option can be used as well for debugging via the ``Serial Monitor`` using **CDC** instead of the **UART0**.
+
+To use the UART as serial output, you can use ``Serial0.print("Hello World!");`` instead of ``Serial.print("Hello World!");`` which will be printed using USB CDC.
+
+USB Firmware MSC On Boot
+************************
+
+The USB Mass Storage Class, or USB MSC, is a class used for storage devices, like a USB flash drive.
+
+This option can be used to ``Enable`` or ``Disable`` this function at the boot. If this option is ``Enabled``, once the device is connected via USB, one new storage device will appear in the system as a storage drive.
+Use this new storage drive to write and read files or to drop a new firmware binary to flash the device.
+
+.. figure:: ../../_static/usb_msc_drive.png
+    :align: center
+    :width: 720
+    :figclass: align-center
+
+USB DFU On Boot
+***************
+
+The USB Device Firmware Upgrade is a class used for flashing the device through USB.
+
+This option can be used to ``Enable`` or ``Disable`` this function at the boot. If this option is ``Enabled``, once the device is connected via USB, the device will appear as a USB DFU capable device.
+
+.. _Espressif Product Selector: https://products.espressif.com/
+.. _boards.txt: https://github.com/espressif/arduino-esp32/blob/master/boards.txt
diff --git a/docs/en/index.rst b/docs/en/index.rst
new file mode 100644
index 00000000000..1314a8fc78d
--- /dev/null
+++ b/docs/en/index.rst
@@ -0,0 +1,24 @@
+#############################################
+Welcome to ESP32 Arduino Core's documentation
+#############################################
+
+Here you will find all the relevant information about the project.
+
+.. note::
+   This is a work in progress documentation and we will appreciate your help! We are looking for contributors!
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Contents:
+
+   Getting Started <getting_started>
+   Libraries <libraries>
+   Guides <guides/guides>
+   Tutorials <tutorials/tutorials>
+   Advanced Utilities <advanced_utils>
+   Third Party Tools <third_party_tools>
+   Migration Guides <migration_guides/migration_guides>
+   FAQ <faq>
+   Troubleshooting <troubleshooting>
+   Contributing <contributing>
+   External Libraries Testing <external_libraries_test>
diff --git a/docs/en/installing.rst b/docs/en/installing.rst
new file mode 100644
index 00000000000..d5392d4b5ec
--- /dev/null
+++ b/docs/en/installing.rst
@@ -0,0 +1,276 @@
+##########
+Installing
+##########
+
+This guide will show how to install the Arduino-ESP32 support.
+
+Before Installing
+-----------------
+
+We recommend you install the support using your favorite IDE, but other options are available depending on your operating system.
+To install Arduino-ESP32 support, you can use one of the following options.
+
+Installing using Arduino IDE
+----------------------------
+
+.. figure:: ../_static/logo_arduino.png
+   :align: center
+   :width: 200
+   :figclass: align-center
+
+This is the way to install Arduino-ESP32 directly from the Arduino IDE.
+
+.. note::
+   For overview of SoC's support, take a look on `Supported Soc's table <https://docs.espressif.com/projects/arduino-esp32/en/latest/getting_started.html#supported-soc-s>`_ where you can find if the particular chip is under stable or development release.
+
+- Stable release link::
+
+   https://espressif.github.io/arduino-esp32/package_esp32_index.json
+
+- Development release link::
+
+   https://espressif.github.io/arduino-esp32/package_esp32_dev_index.json
+
+
+.. note::
+   Starting with the Arduino IDE version 1.6.4, Arduino allows installation of third-party platform
+   packages using Boards Manager. We have packages available for Windows, macOS, and Linux.
+
+To start the installation process using the Boards Manager, follow these steps:
+
+-  Install the current upstream Arduino IDE at the 1.8 level or later. The current version is at the `arduino.cc`_ website.
+
+-  Start Arduino and open the Preferences window.
+
+.. figure:: ../_static/install_guide_preferences.png
+   :align: center
+   :width: 600
+   :figclass: align-center
+
+-  Enter one of the release links above into *Additional Board Manager URLs* field. You can add multiple URLs, separating them with commas.
+
+.. figure:: ../_static/install_guide_boards_manager_url.png
+   :align: center
+   :width: 600
+   :figclass: align-center
+
+-  Open Boards Manager from Tools > Board menu and install *esp32* platform (and do not forget to select your ESP32 board from Tools > Board menu after installation).
+
+.. figure:: ../_static/install_guide_boards_manager_esp32.png
+   :align: center
+   :width: 600
+   :figclass: align-center
+
+- Restart Arduino IDE.
+
+Windows (manual installation)
+-----------------------------
+
+.. warning:: Arduino ESP32 core v2.x.x cannot be used on Windows 8.x x86 (32 bits), Windows 7 or earlier. The Windows 32 bits OS is no longer supported by this toolchain.
+
+   The Arduino ESP32 v1.0.6 still works on WIN32. You might want to install python 3.8.x because it is the latest release supported by Windows 7.
+
+Steps to install Arduino ESP32 support on Windows:
+
+**Step 1**
+
+1. Download and install the latest Arduino IDE ``Windows Installer`` from [arduino.cc](https://www.arduino.cc/en/Main/Software)
+2. Download and install Git from [git-scm.com](https://git-scm.com/download/win)
+3. Start ``Git GUI`` and do the following steps:
+
+- Select ``Clone Existing Repository``
+
+.. figure:: ../_static/win-gui-1.png
+   :align: center
+   :width: 600
+   :figclass: align-center
+
+- Select source and destination
+   - Sketchbook Directory: Usually ``C:/Users/[YOUR_USER_NAME]/Documents/Arduino`` and is listed underneath the "Sketchbook location" in Arduino preferences.
+   - Source Location: ``https://github.com/espressif/arduino-esp32.git``
+   - Target Directory: ``[ARDUINO_SKETCHBOOK_DIR]/hardware/espressif/esp32``
+   - Click ``Clone`` to start cloning the repository
+
+**Step 2**
+
+.. figure:: ../_static/win-gui-2.png
+   :align: center
+   :figclass: align-center
+
+**Step 3**
+
+.. figure:: ../_static/win-gui-3.png
+   :align: center
+   :figclass: align-center
+
+- open a `Git Bash` session pointing to ``[ARDUINO_SKETCHBOOK_DIR]/hardware/espressif/esp32`` and execute ```git submodule update --init --recursive```
+- Open ``[ARDUINO_SKETCHBOOK_DIR]/hardware/espressif/esp32/tools`` and double-click ``get.exe``
+
+**Step 4**
+
+.. figure:: ../_static/win-gui-4.png
+   :align: center
+   :figclass: align-center
+
+- When ```get.exe``` finishes, you should see the following files in the directory
+
+**Step 5**
+
+.. figure:: ../_static/win-gui-5.png
+   :align: center
+   :figclass: align-center
+
+1. Plug your ESP32 board and wait for the drivers to install (or install manually any that might be required)
+2. Start Arduino IDE
+3. Select your board in ``Tools > Board`` menu
+4. Select the COM port that the board is attached to
+5. Compile and upload (You might need to hold the boot button while uploading)
+
+.. figure:: ../_static/arduino-ide.png
+   :align: center
+   :figclass: align-center
+
+How to update to the latest code
+********************************
+
+1. Start ``Git GUI`` and you should see the repository under ``Open Recent Repository``. Click on it!
+
+.. figure:: ../_static/win-gui-update-1.png
+   :align: center
+   :figclass: align-center
+
+1. From menu ``Remote`` select ``Fetch from`` > ``origin``
+
+.. figure:: ../_static/win-gui-update-2.png
+   :align: center
+   :figclass: align-center
+
+1. Wait for git to pull any changes and close ``Git GUI``
+2. Open ``[ARDUINO_SKETCHBOOK_DIR]/hardware/espressif/esp32/tools`` and double-click ``get.exe``
+
+.. figure:: ../_static/win-gui-4.png
+   :align: center
+   :figclass: align-center
+
+Linux
+-----
+
+.. figure:: ../_static/logo_linux.png
+   :align: center
+   :width: 200
+   :figclass: align-center
+
+Debian/Ubuntu
+*************
+
+- Install latest Arduino IDE from `arduino.cc`_.
+
+- Open Terminal and execute the following command (copy -> paste and hit enter):
+
+.. code-block:: bash
+
+   sudo usermod -a -G dialout $USER && \
+   sudo apt-get install git && \
+   wget https://bootstrap.pypa.io/get-pip.py && \
+   sudo python3 get-pip.py && \
+   sudo pip3 install pyserial && \
+   mkdir -p ~/Arduino/hardware/espressif && \
+   cd ~/Arduino/hardware/espressif && \
+   git clone https://github.com/espressif/arduino-esp32.git esp32 && \
+   cd esp32/tools && \
+   python3 get.py
+
+- Restart Arduino IDE.
+
+- If you have Arduino installed to ~/, modify the installation as follows, beginning at `mkdir -p ~/Arduino/hardware`:
+
+.. code-block:: bash
+
+   cd ~/Arduino/hardware
+   mkdir -p espressif && \
+   cd espressif && \
+   git clone https://github.com/espressif/arduino-esp32.git esp32 && \
+   cd esp32/tools && \
+   python3 get.py
+
+Fedora
+******
+
+- Install the latest Arduino IDE from `arduino.cc`_.
+
+.. note::
+   Command ``$ sudo dnf -y install arduino`` will most likely install an older release.
+
+- Open Terminal and execute the following command (copy -> paste and hit enter):
+
+.. code-block:: bash
+
+   sudo usermod -a -G dialout $USER && \
+   sudo dnf install git python3-pip python3-pyserial && \
+   mkdir -p ~/Arduino/hardware/espressif && \
+   cd ~/Arduino/hardware/espressif && \
+   git clone https://github.com/espressif/arduino-esp32.git esp32 && \
+   cd esp32/tools && \
+   python get.py
+
+- Restart Arduino IDE.
+
+openSUSE
+********
+
+- Install the latest Arduino IDE from `arduino.cc`_.
+
+- Open Terminal and execute the following command (copy -> paste and hit enter):
+
+.. code-block:: bash
+
+   sudo usermod -a -G dialout $USER && \
+   if [ `python --version 2>&1 | grep '2.7' | wc -l` = "1" ]; then \
+   sudo zypper install git python-pip python-pyserial; \
+   else \
+   sudo zypper install git python3-pip python3-pyserial; \
+   fi && \
+   mkdir -p ~/Arduino/hardware/espressif && \
+   cd ~/Arduino/hardware/espressif && \
+   git clone https://github.com/espressif/arduino-esp32.git esp32 && \
+   cd esp32/tools && \
+   python get.py
+
+- Restart Arduino IDE.
+
+macOS
+-----
+
+- Install the latest Arduino IDE from `arduino.cc`_.
+
+- Open Terminal and execute the following command (copy -> paste and hit enter):
+
+.. code-block:: bash
+
+   mkdir -p ~/Documents/Arduino/hardware/espressif && \
+   cd ~/Documents/Arduino/hardware/espressif && \
+   git clone https://github.com/espressif/arduino-esp32.git esp32 && \
+   cd esp32/tools && \
+   python get.py
+
+Where ``~/Documents/Arduino`` represents your sketch book location as per "Arduino" > "Preferences" > "Sketchbook location" (in the IDE once started). Adjust the command above accordingly.
+
+- If you get the error below, install through the command line dev tools with `xcode-select --install` and try the command above again:
+
+.. code-block:: bash
+
+   xcrun: error: invalid active developer path (/Library/Developer/CommandLineTools), missing xcrun at: /Library/Developer/CommandLineTools/usr/bin/xcrun
+
+- Run the command:
+
+.. code-block:: bash
+
+   xcode-select --install
+
+- Try ``python3`` instead of ``python`` if you get the error: ``IOError: [Errno socket error] [SSL: TLSV1_ALERT_PROTOCOL_VERSION] tlsv1 alert protocol version (_ssl.c:590)`` when running ``python get.py``
+
+- If you get the following error when running ``python get.py``: ``urllib.error.URLError: <urlopen error SSL: CERTIFICATE_VERIFY_FAILED``, go to ``Macintosh HD > Applications > Python3.6 folder (or any other python version)``, and run the following scripts: Install Certificates.command and Update Shell Profile.command
+
+- Restart Arduino IDE.
+
+.. _Arduino.cc: https://www.arduino.cc/en/Main/Software
diff --git a/docs/en/lib_builder.rst b/docs/en/lib_builder.rst
new file mode 100644
index 00000000000..e7edb331fd3
--- /dev/null
+++ b/docs/en/lib_builder.rst
@@ -0,0 +1,379 @@
+###############
+Library Builder
+###############
+
+About
+-----
+
+Espressif provides a macOS and Linux `tool <https://github.com/espressif/esp32-arduino-lib-builder>`_ to simplify building your own compiled libraries for use in Arduino IDE (or your favorite IDE).
+
+This tool can be used to change the project or a specific configuration according to your needs.
+
+Installing
+----------
+
+To install the Library Builder into your environment, please, follow the instructions below.
+
+- Clone the ESP32 Arduino lib builder:
+
+.. code-block:: bash
+
+    git clone https://github.com/espressif/esp32-arduino-lib-builder
+
+- Go to the ``esp32-arduino-lib-builder`` folder:
+
+.. code-block:: bash
+
+    cd esp32-arduino-lib-builder
+
+- Build:
+
+.. code-block:: bash
+
+    ./build.sh
+
+If everything works, you may see the following message: ``Successfully created esp32 image.``
+
+Dependencies
+************
+
+To build the library you will need to install some dependencies. Maybe you already have installed it, but it is a good idea to check before building.
+
+- Install all dependencies (**Ubuntu**):
+
+.. code-block:: bash
+
+    sudo apt-get install git wget curl libssl-dev libncurses-dev flex bison gperf cmake ninja-build ccache jq
+
+- Install Python and upgrade pip:
+
+.. code-block:: bash
+
+    sudo apt-get install python3
+    sudo pip install --upgrade pip
+
+- Install all required packages:
+
+.. code-block:: bash
+
+    pip install --user setuptools pyserial click cryptography future pyparsing pyelftools
+
+Building
+--------
+
+If you have all the dependencies met, it is time to build the libraries.
+
+To build using the default configuration:
+
+.. code-block:: bash
+
+    ./build.sh
+
+Custom Build
+************
+
+There are some options to help you create custom libraries. You can use the following options:
+
+Usage
+^^^^^
+
+.. code-block:: bash
+
+    build.sh [-s] [-A arduino_branch] [-I idf_branch] [-i idf_commit] [-c path] [-t <target>] [-b <build|menuconfig|idf_libs|copy_bootloader|mem_variant>] [config ...]
+
+Skip Install/Update
+^^^^^^^^^^^^^^^^^^^
+
+Skip installing/updating of ESP-IDF and all components
+
+.. code-block:: bash
+
+    ./build.sh -s
+
+This option can be used if you already have the ESP-IDF and all components already in your environment.
+
+Set Arduino-ESP32 Branch
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+Set which branch of arduino-esp32 to be used for compilation
+
+.. code-block:: bash
+
+    ./build.sh -A <arduino_branch>
+
+Set ESP-IDF Branch
+^^^^^^^^^^^^^^^^^^
+
+Set which branch of ESP-IDF is to be used for compilation
+
+.. code-block:: bash
+
+    ./build.sh -I <idf_branch>
+
+Set the ESP-IDF Commit
+^^^^^^^^^^^^^^^^^^^^^^
+
+Set which commit of ESP-IDF to be used for compilation
+
+.. code-block:: bash
+
+    ./build.sh -i <idf_commit>
+
+Deploy
+^^^^^^
+
+Deploy the build to github arduino-esp32
+
+.. code-block:: bash
+
+    ./build.sh -d
+
+Set the Arduino-ESP32 Destination Folder
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Set the arduino-esp32 folder to copy the result to. ex. '$HOME/Arduino/hardware/espressif/esp32'
+
+.. code-block:: bash
+
+    ./build.sh -c <path>
+
+This function is used to copy the compiled libraries to the Arduino folder.
+
+Set the Target
+^^^^^^^^^^^^^^
+
+Set the build target(chip). ex. 'esp32s3'
+
+.. code-block:: bash
+
+    ./build.sh -t <target>
+
+This build command will build for the ESP32-S3 target. You can specify other targets.
+
+* esp32
+* esp32c2
+* esp32c3
+* esp32c6
+* esp32h2
+* esp32p4
+* esp32s2
+* esp32s3
+
+Set Build Type
+^^^^^^^^^^^^^^
+
+Set the build type. ex. 'build' to build the project and prepare for uploading to a board.
+
+.. note:: This command depends on the ``-t`` argument.
+
+.. code-block:: bash
+
+    ./build.sh -t esp32 -b <build|menuconfig|idf_libs|copy_bootloader|mem_variant>
+
+Additional Configuration
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+Specify additional configs to be applied. ex. ``qio 80m`` to compile for QIO Flash at 80 MHz.
+
+.. note:: This command requires the ``-b`` to work properly.
+
+
+.. code-block:: bash
+
+    ./build.sh -t esp32 -b idf_libs qio 80m
+
+User Interface
+--------------
+
+Starting from ``arduino-esp32`` version 3.0.0 (IDF v5.1), there is also a terminal user interface that can be used
+to configure the libraries to be compiled.
+
+It allows the user to select the targets to compile, change the configuration options and compile the libraries.
+It has mouse support and can be pre-configured using command line arguments.
+
+For more information and troubleshooting, check `the documentation <https://github.com/espressif/esp32-arduino-lib-builder/blob/master/tools/config_editor/README.md>`_.
+
+To use the terminal user interface, make sure to have ``python>=3.9``, all the previous dependencies and install the ``textual`` library:
+
+.. code-block:: bash
+
+    pip install --user textual
+
+You can then run the UI using the following command:
+
+.. code-block:: bash
+
+    ./tools/config_editor/app.py
+
+Pre-Configuring the UI
+**********************
+
+The UI can be pre-configured using command line arguments. The following arguments are available:
+
+- ``-t, --target <target>``: Comma-separated list of targets to be compiled.
+  Choose from: *all*, *esp32*, *esp32s2*, *esp32s3*, *esp32c2*, *esp32c3*, *esp32c6*, *esp32h2*. Default: all except *esp32c2*;
+- ``--copy, --no-copy``: Enable/disable copying the compiled libraries to ``arduino-esp32``. Enabled by default;
+- ``-c, --arduino-path <path>``: Path to ``arduino-esp32`` directory. Default: OS dependent;
+- ``-A, --arduino-branch <branch>``: Branch of the ``arduino-esp32`` repository to be used. Default: set by the build script;
+- ``-I, --idf-branch <branch>``: Branch of the ``ESP-IDF`` repository to be used. Default: set by the build script;
+- ``-i, --idf-commit <commit>``: Commit of the ``ESP-IDF`` repository to be used. Default: set by the build script;
+- ``-D, --debug-level <level>``: Debug level to be set in ``ESP-IDF``.
+  Choose from: *default*, *none*, *error*, *warning*, *info*, *debug*, *verbose*. Default: *default*.
+
+Please note that all these options can be changed in the UI itself and are only used for automation purposes.
+
+Screens
+*******
+
+There are many screens in the UI that are used to configure the libraries to be compiled.
+Note that in all screens you can also use the shortcut keys shown in the footer bar to navigate.
+
+The UI consists of the following screens:
+
+- **Main Menu**: The main screen shows buttons to navigate to the other screens.
+- **Compile Screen**: The compile screen shows the output of the compilation process and any errors that may have occurred.
+- **Sdkconfig Editor**: The sdkconfig editor screen is a simple text editor that shows you the sdkconfig files that will be used for compilation.
+  You can edit the files here to customize the generated libraries.
+- **Settings Screen**: The settings screen allows you to change the settings of the compilation process.
+  Here you can change:
+
+  - The targets that the libraries will be compiled for. To save time, you can compile the libraries only for the target you are using;
+  - Whether the compiled libraries will be copied to the ``arduino-esp32`` directory after compilation so that they can be used in the Arduino IDE;
+  - The path to the ``arduino-esp32`` directory. This will be automatically set if the ``arduino-esp32`` repository is in one of the default locations.
+    If not, you can set it manually here. If using the docker image, it should not be changed as the mount point is fixed;
+  - The branch of the ``arduino-esp32`` repository to be used. This is useful if you want to compile the libraries for a
+    specific branch or pull request of the ``arduino-esp32`` repository. Leave empty to use the default branch for this ``ESP-IDF`` version;
+  - The branch of the ``ESP-IDF`` repository to be used. This is useful if you want to compile the libraries for a specific branch of the ``ESP-IDF`` repository.
+    Leave empty to use the default branch for this IDF version;
+  - The commit of the ``ESP-IDF`` repository to be used. This is useful if you want to compile the libraries for a specific commit on the selected branch.
+    Leave empty to use the latest commit;
+  - The debug level to be set in ``ESP-IDF``.
+
+Docker Image
+------------
+
+You can use a docker image for building the static libraries of ESP-IDF components for use in Arduino projects.
+This image contains a copy of the ``esp32-arduino-lib-builder`` repository and already includes or will obtain all the required tools and dependencies to build the Arduino static libraries.
+
+The current supported architectures by the Docker image are:
+
+* ``amd64``
+* ``arm64``
+
+.. note::
+    Building the libraries using the Docker image is much slower than building them natively on the host machine.
+    It is recommended to use the Docker image only when the host machine does not meet the requirements for building the libraries (e.g., building on Windows).
+
+Tags
+****
+
+Multiple tags of this image are maintained:
+
+- ``latest``: tracks ``master`` branch of the Lib Builder. Note that the ``latest`` tag is not recommended for use as, depending on the
+  development stage of the Lib Builder, it might not be stable or might not contain the latest changes;
+- ``release-vX.Y``: tracks ``release/vX.Y`` branch of the Lib Builder.
+
+.. note::
+    Versions of Lib Builder released before this feature was introduced do not have corresponding Docker image versions.
+    You can check the up-to-date list of available tags at https://hub.docker.com/r/espressif/esp32-arduino-lib-builder/tags.
+
+Usage
+*****
+
+Before using the ``espressif/esp32-arduino-lib-builder`` Docker image locally, make sure you have Docker installed and running on your machine.
+Follow the instructions at https://docs.docker.com/install/, if it is not installed yet.
+
+If using the image in a CI environment, consult the documentation of your CI service on how to specify the image used for the build process.
+
+Building the Libraries
+^^^^^^^^^^^^^^^^^^^^^^
+
+You have two options to run the Docker image to build the libraries. Manually or using the provided run script.
+
+To run the Docker image manually, use the following command from the root of the ``arduino-esp32`` repository:
+
+.. code-block:: bash
+
+    docker run --rm -it -v $PWD:/arduino-esp32 -e TERM=xterm-256color espressif/esp32-arduino-lib-builder:release-v5.1
+
+This will start the Lib Builder UI for compiling the libraries. The above command explained:
+
+- ``docker run``: Runs a command in a container;
+- ``--rm``: Optional. Automatically removes the container when it exits. Remove this flag if you plan to use the container multiple times;
+- ``-i`` Run the container in interactive mode;
+- ``-t`` Allocate a pseudo-TTY;
+- ``-e TERM=xterm-256color``: Optional. Sets the terminal type to ``xterm-256color`` to display colors correctly;
+- ``-v $PWD:/arduino-esp32``: Optional. Mounts the current folder at ``/arduino-esp32`` inside the container. If not provided, the container will not copy the compiled libraries to the host machine;
+- ``espressif/esp32-arduino-lib-builder:release-v5.1``: uses Docker image ``espressif/esp32-arduino-lib-builder`` with tag ``release-v5.1``.
+  The ``latest`` tag is implicitly added by Docker when no tag is specified. It is recommended to use a specific version tag to ensure reproducibility of the build process.
+
+.. warning::
+    The ``-v`` option is used to mount a folder from the host machine to the container. Make sure the folder already exists on the host machine before running the command.
+    Otherwise, the folder will be created with root permissions and files generated inside the container might cause permission issues and compilation errors.
+
+.. note::
+   When the mounted directory ``/arduino-esp32`` contains a git repository owned by a different user (``UID``) than the one running the Docker container,
+   git commands executed within ``/arduino-esp32`` might fail, displaying an error message ``fatal: detected dubious ownership in repository at '/arduino-esp32'``.
+   To resolve this issue, you can designate the ``/arduino-esp32`` directory as safe by setting the ``LIBBUILDER_GIT_SAFE_DIR`` environment variable during the Docker container startup.
+   For instance, you can achieve this by including ``-e LIBBUILDER_GIT_SAFE_DIR='/arduino-esp32'`` as a parameter. Additionally, multiple directories can be specified by using a ``:`` separator.
+   To entirely disable this git security check, ``*`` can be used.
+
+After running the above command, you will be inside the container and the libraries can be built using the user interface.
+
+By default the docker container will run the user interface script. If you want to run a specific command, you can pass it as an argument to the ``docker run`` command.
+For example, to run a terminal inside the container, you can run:
+
+.. code-block:: bash
+
+    docker run -it espressif/esp32-arduino-lib-builder:release-v5.1 /bin/bash
+
+Running the Docker image using the provided run script will depend on the host OS.
+Use the following command from the root of the ``arduino-esp32`` repository to execute the image in a Linux or macOS environment for
+the ``release-v5.1`` tag:
+
+.. code-block:: bash
+
+    curl -LJO https://raw.githubusercontent.com/espressif/esp32-arduino-lib-builder/refs/heads/release/v5.1/tools/docker/run.sh
+    chmod +x run.sh
+    ./run.sh $PWD
+
+For Windows, use the following command in PowerShell from the root of the ``arduino-esp32`` repository:
+
+.. code-block:: powershell
+
+    Invoke-WebRequest -Uri "https://raw.githubusercontent.com/espressif/esp32-arduino-lib-builder/refs/heads/release/v5.1/tools/docker/run.ps1" -OutFile "run.ps1"
+    .\run.ps1 $pwd
+
+As the script is unsigned, you may need to change the execution policy of the current session before running the script.
+To do so, run the following command in PowerShell:
+
+.. code-block:: powershell
+
+    Set-ExecutionPolicy -Scope Process -ExecutionPolicy Bypass
+
+.. warning::
+    It is always a good practice to understand what the script does before running it.
+    Make sure to analyze the content of the script to ensure it is safe to run and won't cause any harm to your system.
+
+Building Custom Images
+**********************
+
+To build a custom Docker image, you need to clone the Lib Builder repository and use the provided Dockerfile in the Lib Builder repository. The Dockerfile is located in the ``tools/docker`` directory.
+
+The `Docker file in the Lib Builder repository <https://github.com/espressif/esp32-arduino-lib-builder/blob/master/tools/docker/Dockerfile>`_ provides several build arguments which can be used to customize the Docker image:
+
+- ``LIBBUILDER_CLONE_URL``: URL of the repository to clone Lib Builder from. Can be set to a custom URL when working with a fork of Lib Builder. The default is ``https://github.com/espressif/esp32-arduino-lib-builder.git``;
+- ``LIBBUILDER_CLONE_BRANCH_OR_TAG``: Name of a git branch or tag used when cloning Lib Builder. This value is passed to the ``git clone`` command using the ``--branch`` argument. The default is ``master``;
+- ``LIBBUILDER_CHECKOUT_REF``: If this argument is set to a non-empty value, ``git checkout $LIBBUILDER_CHECKOUT_REF`` command performs after cloning. This argument can be set to the SHA of the specific commit to check out, for example, if some specific commit on a release branch is desired;
+- ``LIBBUILDER_CLONE_SHALLOW``: If this argument is set to a non-empty value, ``--depth=1 --shallow-submodules`` arguments are used when performing ``git clone``. Depth can be customized using ``LIBBUILDER_CLONE_SHALLOW_DEPTH``. Doing a shallow clone significantly reduces the amount of data downloaded and the size of the resulting Docker image. However, if switching to a different branch in such a "shallow" repository is necessary, an additional ``git fetch origin <branch>`` command must be executed first;
+- ``LIBBUILDER_CLONE_SHALLOW_DEPTH``: This argument specifies the depth value to use when doing a shallow clone. If not set, ``--depth=1`` will be used. This argument has effect only if ``LIBBUILDER_CLONE_SHALLOW`` is used. Use this argument if you are building a Docker image for a branch, and the image has to contain the latest tag on that branch. To determine the required depth, run ``git describe`` for the given branch and note the offset number. Increment it by 1, then use it as the value of this argument. The resulting image will contain the latest tag on the branch, and consequently ``git describe`` command inside the Docker image will work as expected;
+
+To use these arguments, pass them via the ``--build-arg`` command line option. For example, the following command builds a Docker image with a shallow clone of Lib Builder from a specific repository and branch:
+
+.. code-block:: bash
+
+    docker buildx build -t lib-builder-custom:master \
+        --build-arg LIBBUILDER_CLONE_BRANCH_OR_TAG=master \
+        --build-arg LIBBUILDER_CLONE_SHALLOW=1 \
+        --build-arg LIBBUILDER_CLONE_URL=https://github.com/espressif/esp32-arduino-lib-builder \
+        tools/docker
diff --git a/docs/en/libraries.rst b/docs/en/libraries.rst
new file mode 100644
index 00000000000..525a5c4ba26
--- /dev/null
+++ b/docs/en/libraries.rst
@@ -0,0 +1,93 @@
+#########
+Libraries
+#########
+
+Here is where the Libraries API's descriptions are located:
+
+Supported Peripherals
+---------------------
+
+Currently, the Arduino ESP32 supports the following peripherals with Arduino APIs.
+
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| Peripheral    | ESP32 | C3    | C6    | H2    | P4    | S2    | S3    | Notes |
++===============+=======+=======+=======+=======+=======+=======+=======+=======+
+| ADC           | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |  (1)  |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| BT Classic    | Yes   | N/A   | N/A   | N/A   | N/A   | N/A   | N/A   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| BLE           | Yes   | Yes   | Yes   | Yes   | No    | N/A   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| DAC           | Yes   | N/A   | N/A   | N/A   | Yes   | Yes   | N/A   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| Ethernet      | Yes   | N/A   | N/A   | N/A   | Yes   | N/A   | N/A   |  (2)  |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| GPIO          | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| Hall Sensor   | N/A   | N/A   | N/A   | N/A   | N/A   | N/A   | N/A   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| I2C           | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| I2S           | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| LEDC          | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| MIPI          | N/A   | N/A   | N/A   | N/A   | No    | N/A   | N/A   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| Motor PWM     | No    | N/A   | N/A   | N/A   | N/A   | N/A   | N/A   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| MSPI          | N/A   | N/A   | N/A   | N/A   | No    | N/A   | N/A   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| Pulse Counter | No    | No    | No    | No    | No    | No    | No    |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| RMT           | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| SDIO          | No    | No    | No    | No    | No    | No    | No    |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| SDMMC         | Yes   | N/A   | N/A   | N/A   | N/A   | N/A   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| Timer         | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| Temp. Sensor  | N/A   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| Touch         | Yes   | N/A   | N/A   | N/A   | Yes   | Yes   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| TWAI          | No    | No    | No    | No    | No    | No    | No    |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| UART          | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |       |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| USB           | N/A   | Yes   | Yes   | Yes   | Yes   | Yes   | Yes   |  (3)  |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+| Wi-Fi         | Yes   | Yes   | Yes   | N/A   | Yes   | Yes   | Yes   |  (4)  |
++---------------+-------+-------+-------+-------+-------+-------+-------+-------+
+
+Notes
+^^^^^
+
+(1) ESP32-P4 calibration schemes not supported yet in IDF and ADC Continuous also lacks IDF support.
+
+(2) SPI Ethernet is supported by all ESP32 families and RMII only for ESP32 and ESP32-P4.
+
+(3) ESP32-C3, C6, H2 only support USB CDC/JTAG
+
+(4) ESP32-P4 only supports Wi-Fi through another SoC by using ``esp_hosted``.
+
+.. note:: Some peripherals are not available for all ESP32 families. To see more details about it, see the corresponding SoC at `Product Selector <https://products.espressif.com>`_ page.
+
+.. include:: common/datasheet.inc
+
+APIs
+----
+
+The Arduino ESP32 offers some unique APIs, described in this section:
+
+.. note::
+    Please be advised that we cannot ensure continuous compatibility between the Arduino Core ESP32 APIs and ESP8266 APIs, as well as Arduino-Core APIs (Arduino.cc).
+    While our aim is to maintain harmony, the addition of new features may result in occasional divergence. We strive to achieve the best possible integration but acknowledge
+    that perfect compatibility might not always be feasible. Please refer to the documentation for any specific considerations.
+
+.. toctree::
+    :maxdepth: 1
+    :glob:
+
+    api/*
diff --git a/docs/en/make.rst b/docs/en/make.rst
new file mode 100644
index 00000000000..fce7f94a7a7
--- /dev/null
+++ b/docs/en/make.rst
@@ -0,0 +1,6 @@
+==============
+makeEspArduino
+==============
+
+The `makeEspArduino <https://github.com/plerup/makeEspArduino>`_ is a generic makefile for any ESP8266/ESP32 Arduino project.
+Using it instead of the Arduino IDE makes it easier to do automated and production builds.
diff --git a/docs/en/migration_guides/2.x_to_3.0.rst b/docs/en/migration_guides/2.x_to_3.0.rst
new file mode 100644
index 00000000000..a7730ceb1b4
--- /dev/null
+++ b/docs/en/migration_guides/2.x_to_3.0.rst
@@ -0,0 +1,228 @@
+#########################
+Migration from 2.x to 3.0
+#########################
+
+Introduction
+------------
+
+This is a guide to highlight **breaking changes** in the API and build system to help the migration of projects from versions 2.X (based on ESP-IDF 4.4) to version 3.0 (based on ESP-IDF 5.1) of the Arduino ESP32 core.
+
+All the examples on the version 3.0.0 were updated to be compatible to the new API. The old examples from the versions below 3.0.0 will be not compatible with the version 3.0.0 or newer releases.
+
+For more information about all changes and new features, check project `RELEASE NOTES <https://github.com/espressif/arduino-esp32/releases>`_.
+
+Build System
+------------
+
+Compilation Flags
+*****************
+
+Functional changes
+^^^^^^^^^^^^^^^^^^
+
+* If your project uses extra flags in the compilation process, it will now overwrite `some required default flags <https://github.com/espressif/arduino-esp32/blob/e5330d1797accfc8334e645372595d1bfda07ba2/platform.txt#L66-L67>`_.
+  To ensure your project compiles correctly, make sure to have the ``-MMD -c`` flags in your C and C++ extra flags.
+
+APIs
+----
+
+ADC
+***
+
+Removed APIs
+^^^^^^^^^^^^
+
+* ``analogSetClockDiv``
+* ``adcAttachPin``
+* ``analogSetVRefPin``
+
+BLE
+***
+
+Changes in APIs
+^^^^^^^^^^^^^^^
+
+* Changed APIs return and parameter type from ``std::string`` to Arduino style ``String``.
+* Changed UUID data type from ``uint16_t`` to ``BLEUUID`` class.
+* ``BLEScan::start`` and ``BLEScan::getResults`` methods return type changed from ``BLEScanResults`` to ``BLEScanResults*``.
+
+Hall Sensor
+***********
+
+Hall sensor is no longer supported.
+
+Removed APIs
+^^^^^^^^^^^^
+
+* ``hallRead``
+
+I2S
+***
+
+The I2S driver has been completely redesigned and refactored to use the new ESP-IDF driver.
+For more information about the new API, check :doc:`/api/i2s`.
+
+LEDC
+****
+
+The LEDC API has been changed in order to support the Peripheral Manager and make it easier to use, as LEDC channels are now automatically assigned to pins.
+For more information about the new API, check :doc:`/api/ledc`.
+
+Removed APIs
+^^^^^^^^^^^^
+
+* ``ledcSetup``
+* ``ledcAttachPin``
+
+New APIs
+^^^^^^^^
+
+* ``ledcAttach`` used to set up the LEDC pin (merged ``ledcSetup`` and ``ledcAttachPin`` functions).
+* ``ledcOutputInvert`` used to attach the interrupt to a timer using arguments.
+* ``ledcFade`` used to set up and start a fade on a given LEDC pin.
+* ``ledcFadeWithInterrupt`` used to set up and start a fade on a given LEDC pin with an interrupt.
+* ``ledcFadeWithInterruptArg`` used to set up and start a fade on a given LEDC pin with an interrupt using arguments.
+
+Changes in APIs
+^^^^^^^^^^^^^^^
+
+* ``ledcDetachPin`` renamed to ``ledcDetach``.
+* In all functions, input parameter ``channel`` has been changed to ``pin``.
+
+RMT
+***
+
+For more information about the new API, check :doc:`/api/rmt`.
+
+Removed APIs
+^^^^^^^^^^^^
+
+* ``_rmtDumpStatus``
+* ``rmtSetTick``
+* ``rmtWriteBlocking``
+* ``rmtEnd``
+* ``rmtBeginReceive``
+* ``rmtReadData``
+
+New APIs
+^^^^^^^^
+
+* ``rmtSetEOT``
+* ``rmtWriteAsync``
+* ``rmtTransmitCompleted``
+* ``rmtSetRxMinThreshold``
+
+
+Changes in APIs
+^^^^^^^^^^^^^^^
+
+* In all functions, input parameter ``rmt_obj_t* rmt`` has been changed to ``int pin``.
+* ``rmtInit`` return parameter changed to bool.
+* ``rmtInit`` input parameter ``bool tx_not_rx`` has been changed to ``rmt_ch_dir_t channel_direction``.
+* ``rmtInit`` new input parameter ``uint32_t frequency_Hz`` to set frequency of RMT channel (as function ``rmtSetTick`` was removed).
+* ``rmtWrite`` now sending data in blocking mode. It only returns after sending all data or through a timeout. For Async mode use the new ``rmtWriteAsync`` function.
+* ``rmtWrite`` new input parameter ``uint32_t timeout_ms``.
+* ``rmtLoop`` renamed to ``rmtWriteLooping``.
+* ``rmtRead`` input parameters changed to ``int pin, rmt_data_t* data, size_t *num_rmt_symbols, uint32_t timeout_ms``.
+* ``rmtReadAsync`` input parameters changed to ``int pin, rmt_data_t* data, size_t *num_rmt_symbols``.
+* ``rmtSetRxThreshold`` renamed to ``rmtSetRxMaxThreshold`` and input parameter ``uint32_t value`` has been changed to ``uint16_t idle_thres_ticks``.
+* ``rmtSetCarrier`` input parameters ``uint32_t low, uint32_t high`` have been changed to ``uint32_t frequency_Hz, float duty_percent``.
+
+SigmaDelta
+**********
+
+SigmaDelta has been refactored to use the new ESP-IDF driver.
+For more information about the new API, check :doc:`/api/sigmadelta`.
+
+Removed APIs
+^^^^^^^^^^^^
+
+* ``sigmaDeltaSetup``
+* ``sigmaDeltaRead``
+
+New APIs
+^^^^^^^^
+
+* ``sigmaDeltaAttach`` used to set up the SigmaDelta pin (channel is acquired automatically).
+* ``timerGetFrequency`` used to get the actual frequency of the timer.
+* ``timerAttachInterruptArg`` used to attach the interrupt to a timer using arguments.
+
+Changes in APIs
+^^^^^^^^^^^^^^^
+
+* ``sigmaDeltaDetachPin`` renamed to ``sigmaDeltaDetach``.
+* ``sigmaDeltaWrite`` input parameter ``channel`` has been changed to ``pin``.
+
+Timer
+*****
+
+Timer has been refactored to use the new ESP-IDF driver and its API got simplified. For more information about the new API check :doc:`/api/timer`.
+
+Removed APIs
+^^^^^^^^^^^^
+
+* ``timerGetConfig``
+* ``timerSetConfig``
+* ``timerSetDivider``
+* ``timerSetCountUp``
+* ``timerSetAutoReload``
+* ``timerGetDivider``
+* ``timerGetCountUp``
+* ``timerGetAutoReload``
+* ``timerAlarmEnable``
+* ``timerAlarmDisable``
+* ``timerAlarmWrite``
+* ``timerAlarmEnabled``
+* ``timerAlarmRead``
+* ``timerAlarmReadMicros``
+* ``timerAlarmReadSeconds``
+* ``timerAttachInterruptFlag``
+
+New APIs
+^^^^^^^^
+
+* ``timerAlarm`` used to set up Alarm for the timer and enable it automatically (merged ``timerAlarmWrite`` and ``timerAlarmEnable`` functions).
+* ``timerGetFrequency`` used to get the actual frequency of the timer.
+* ``timerAttachInterruptArg`` used to attach the interrupt to a timer using arguments.
+
+Changes in APIs
+^^^^^^^^^^^^^^^
+
+* ``timerBegin`` has now only 1 parameter (frequency). There is an automatic calculation of the divider using different clock sources
+  to achieve the selected frequency.
+* ``timerAttachInterrupt`` has now only 2 parameters. The ``edge`` parameter has been removed.
+
+UART (HardwareSerial)
+*********************
+
+Changes in APIs
+^^^^^^^^^^^^^^^
+
+* ``setHwFlowCtrlMode`` input parameter ``uint8_t mode`` has been changed to ``SerialHwFlowCtrl mode``.
+* ``setMode`` input parameter ``uint8_t mode`` has been changed to ``SerialMode mode``.
+
+Functional changes
+^^^^^^^^^^^^^^^^^^
+
+* Default pins for some SoCs have been changed to avoid conflicts with other peripherals:
+  * ESP32's UART1 RX and TX pins are now GPIO26 and GPIO27, respectively;
+  * ESP32's UART2 RX and TX pins are now GPIO4 and GPIO25, respectively;
+  * ESP32-S2's UART1 RX and TX pins are now GPIO4 and GPIO5, respectively.
+* It is now possible to detach UART0 pins by calling ``end()`` with no previous call of ``begin()``.
+* It is now possible to call ``setPins()`` before ``begin()`` or in any order.
+* ``setPins()`` will detach any previous pins that have been changed.
+* ``begin(baud, rx, tx)`` will detach any previous attached pins.
+* ``setPins()`` or ``begin(baud, rx, tx)`` when called at first, will detach console RX0/TX0, attached in boot.
+* Any pin set as -1 in ``begin()`` or ``setPins()`` won't be changed nor detached.
+* ``begin(baud)`` will not change any pins that have been set before this call, through a previous ``begin(baud, rx, tx)`` or ``setPin()``.
+* If the application only uses RX or TX, ``begin(baud, -1, tx)`` or ``begin(baud, rx)`` will change only the assigned pin and keep the other unchanged.
+
+Wi-Fi
+*****
+
+Functional changes
+^^^^^^^^^^^^^^^^^^
+
+* In Arduino (and other frameworks) the method named ``flush()`` is intended to send out the transmit buffer content. ``WiFiClient`` and ``WiFiUDP`` method ``flush()`` won't clear the receive buffer anymore. A new method called ``clear()`` is now used for that. Currently ``flush()`` does nothing in ``WiFiClient``, ``WiFiClientSecure`` and ``WiFiUDP``.
+* ``WiFiServer`` has functions ``accept()`` and ``available()`` with the same functionality. In Arduino, ``available()`` should work differently so it is now deprecated.
+* ``WiFiServer`` had unimplemented write functions inherited from ``Print`` class. These are now removed. Also unimplemented method ``stopAll()`` is removed. The methods were unimplemented because ``WiFiServer`` doesn't manage connected ``WiFiClient`` objects for print-to-all-clients functionality.
diff --git a/docs/en/migration_guides/migration_guides.rst b/docs/en/migration_guides/migration_guides.rst
new file mode 100644
index 00000000000..e1254c19ba5
--- /dev/null
+++ b/docs/en/migration_guides/migration_guides.rst
@@ -0,0 +1,10 @@
+################
+Migration Guides
+################
+
+.. toctree::
+    :caption: Migration Guides:
+    :maxdepth: 1
+    :glob:
+
+    *
diff --git a/docs/en/ota_web_update.rst b/docs/en/ota_web_update.rst
new file mode 100644
index 00000000000..2d5c4e529c0
--- /dev/null
+++ b/docs/en/ota_web_update.rst
@@ -0,0 +1,79 @@
+##############
+OTA Web Update
+##############
+
+OTAWebUpdate is done with a web browser that can be useful in the following typical scenarios:
+
+- Once the application developed and loading directly from Arduino IDE is inconvenient or not possible
+- after deployment if user is unable to expose Firmware for OTA from external update server
+- provide updates after deployment to small quantity of modules when setting an update server is not practicable
+
+For more information about the update process, please refer to the `OTA API reference <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/ota.html>`_
+section of the ESP-IDF documentation.
+
+Requirements
+------------
+
+- The ESP and the computer must be connected to the same network
+
+Implementation
+--------------
+
+The sample implementation has been done using:
+
+- Example sketch ```OTAWebUpdater.ino```.
+- ESP32 Board.
+
+You can also use another module if it meets Flash chip size of the sketch
+
+Before you begin, please make sure that you have the following software installed:
+
+- Arduino IDE
+- Host software depending on O/S you use
+    - `Avahi <http://avahi.org/>`_ for Linux
+    - `Bonjour <http://www.apple.com/support/bonjour/>`_ for Windows
+    - Mac OSX and iOS - support is already built in / no any extra s/w is required
+
+Prepare the sketch and configuration for initial upload with a serial port
+- Start Arduino IDE and load sketch OTAWebUpdater.ino available under File > Examples > OTAWebUpdater.ino
+- Update ssid and pass in the sketch so the module can join your Wi-Fi network
+- Open File > Preferences, look for “Show verbose output during:” and check out “compilation” option
+
+.. figure:: ../_static/ota_esp32_verbose.png
+    :align: center
+    :figclass: align-center
+
+- Upload sketch (Ctrl+U)
+- Now open web browser and enter the url, i.e. http://esp32.local. Once entered, browser should display a form
+
+.. figure:: ../_static/ota_esp32_login.png
+    :align: center
+    :figclass: align-center
+
+* username = admin
+
+* password = admin
+
+.. note::
+    *If entering “http://ESP32.local” does not work, try replacing “ESP32” with module’s IP address. This workaround is useful in case the host software installed does not work*.
+
+Now click on the Login button and browser will display an upload form
+
+.. figure:: ../_static/ota_esp32_upload.png
+    :align: center
+    :figclass: align-center
+
+For Uploading the New Firmware, you need to provide the Binary File of your Code.
+
+Exporting Binary file of the Firmware (Code)
+- Open up the Arduino IDE
+- Open up the Code, for Exporting up Binary file
+- Now go to Sketch > export compiled Binary
+
+.. figure:: ../_static/ota_export_to_binary.png
+    :align: center
+    :figclass: align-center
+
+- Binary file is exported to the same Directory where your code is present
+
+Once you are comfortable with this procedure, go ahead and modify OTAWebUpdater.ino sketch to print some additional messages and compile it. Then, export the new binary file and upload it using web browser to see entered changes on a Serial Monitor.
diff --git a/docs/en/third_party/pioarduino.rst b/docs/en/third_party/pioarduino.rst
new file mode 100644
index 00000000000..49af583befa
--- /dev/null
+++ b/docs/en/third_party/pioarduino.rst
@@ -0,0 +1,14 @@
+#######################################################
+pioarduino - (p)eople (i)nitiated (o)ptimized (arduino)
+#######################################################
+
+.. warning::
+  This tool is **not maintained by the ESP32 Arduino Core team**, so we cannot provide support or guarantee that it will work as expected.
+
+.. note::
+  This is a work in progress documentation and we will appreciate your help! We are looking for contributors!
+
+About
+-----
+
+For more information, please refer to the `official documentation <https://github.com/pioarduino/platform-espressif32>`_.
diff --git a/docs/en/third_party/wokwi.rst b/docs/en/third_party/wokwi.rst
new file mode 100644
index 00000000000..0a6eb9d0992
--- /dev/null
+++ b/docs/en/third_party/wokwi.rst
@@ -0,0 +1,42 @@
+#####
+Wokwi
+#####
+
+.. warning::
+  This tool is **not maintained by the ESP32 Arduino Core team**, so we cannot provide support or guarantee that it will work as expected.
+
+.. note::
+  This is a work in progress documentation and we will appreciate your help! We are looking for contributors!
+
+About
+-----
+
+Wokwi is an online Electronics simulator. You can use it to simulate Arduino, ESP32, and many other popular boards, parts and sensors.
+
+The advantages of using Wokwi include:
+
+- Immediate start: No need to wait for components or download large software. Everything required is available in your browser, enabling you to begin coding your IoT project within seconds.
+- Safe experimentation: Virtual hardware cannot be damaged, allowing users to experiment freely without the risk of destroying components. Mistakes can be easily undone.
+- Easy collaboration: Sharing a link to your Wokwi project facilitates obtaining help and feedback from others.
+- Code reliability: Helps in distinguishing between hardware and software issues, thereby increasing confidence in your code.
+- Unlimited resources: Access to an unlimited number of parts without concerns about cost or availability.
+- Supportive community: A maker-friendly environment where users can share projects, seek assistance, and find inspiration.
+
+Unique features provided by Wokwi:
+
+- Wi-Fi simulation - Connect your simulated project to the internet. You can use MQTT, HTTP, NTP, and many other network protocols.
+- Virtual Logic Analyzer - Capture digital signals in your simulation (e.g. UART, I2C, SPI) and analyze them on your computer.
+- Advanced debugging with GDB - Powerful Arduino debugger for advanced users.
+- SD card simulation - Store and retrieve files and directories from your code. Paying users can also upload binary files (such as images)
+- Chips API - Create your own custom chips and parts, and share them with the community.
+- Visual Studio Code integration - Simulate your embedded projects directly from VS Code.
+
+Pricing
+-------
+
+Wokwi is free for personal use. For commercial users and professionals, please check out the paid plans in the `pricing page <https://wokwi.com/pricing>`_.
+
+Learn more
+----------
+
+For more information, please refer to the `official Wokwi website <https://wokwi.com>`_ and the `Wokwi documentation <https://docs.wokwi.com>`_.
diff --git a/docs/en/third_party_tools.rst b/docs/en/third_party_tools.rst
new file mode 100644
index 00000000000..fd8fd92ae0c
--- /dev/null
+++ b/docs/en/third_party_tools.rst
@@ -0,0 +1,16 @@
+#################
+Third Party Tools
+#################
+
+Here you will find documentation pages for third party tools that can be used with the ESP32 Arduino Core.
+
+.. warning::
+  These tools are **not maintained by the ESP32 Arduino Core team**, so we cannot provide support or guarantee that they will work as expected.
+  Each tool documentation should be provided and maintained by the community.
+
+.. toctree::
+  :maxdepth: 1
+  :caption: Contents:
+
+  pioarduino <third_party/pioarduino>
+  Wokwi <third_party/wokwi>
diff --git a/docs/en/troubleshooting.rst b/docs/en/troubleshooting.rst
new file mode 100644
index 00000000000..f6a241729f5
--- /dev/null
+++ b/docs/en/troubleshooting.rst
@@ -0,0 +1,253 @@
+###############
+Troubleshooting
+###############
+
+Common Issues
+=============
+
+Here are some of the most common issues around the ESP32 development using Arduino.
+
+.. note:: Please consider contributing if you have found any issues with the solution here.
+
+Installing
+----------
+
+Here are the common issues during the installation.
+
+Building
+--------
+
+Missing Python: "python": executable file not found in $PATH
+************************************************************
+
+You are trying to build your sketch using Ubuntu and this message appears:
+
+.. code-block:: bash
+
+    "exec: "python": executable file not found in $PATH
+    Error compiling for board ESP32 Dev Module"
+
+Solution
+^^^^^^^^
+
+To avoid this error, you can install the ``python-is-python3`` package to create the symbolic links.
+
+.. code-block:: bash
+
+    sudo apt install python-is-python3
+
+If you are not using Ubuntu, you can check if you have the Python correctly installed or the presence of the symbolic links/environment variables.
+
+Flashing
+--------
+
+Why is my board not flashing/uploading when I try to upload my sketch?
+**********************************************************************
+
+To be able to upload the sketch via the serial interface, the ESP32 must be in the download mode. The download mode allows you to upload the sketch over the serial port, and to get into it, you need to keep the **GPIO0** in LOW while resetting (**EN** pin) the cycle.
+If you are trying to upload a new sketch and your board is not responding, there are some possible reasons.
+
+Possible fatal error message from the Arduino IDE:
+
+    *A fatal error occurred: Failed to connect to ESP32: Timed out waiting for packet header*
+
+Solution
+^^^^^^^^
+
+Here are some steps that you can try:
+
+* Check your USB cable and try a new one (some cables are only for charging and there is no data connection).
+* Change the USB port - prefer direct connection to the computer and avoid USB hubs. Some USB ports may share the power source with other ports used, for example, for charging a phone.
+* Check your power supply.
+* Make sure that nothing is connected to pins labeled **TX** and **RX**. Please refer to the pin layout table - some TX and RX pins may not be labeled on the dev board.
+* In some instances, you must keep **GPIO0** LOW during the uploading process via the serial interface.
+* Hold down the **“BOOT”** button on your ESP32 board while uploading/flashing.
+* Solder a **10 uF** capacitor in parallel with **RST** and **GND**.
+* If you are using external power connected to pins, it is easy to confuse pins **CMD** (which is usually next to the ``5V`` pin) and **GND**.
+
+In some development boards, you can try adding the reset delay circuit, as described in the *Power-on Sequence* section on the `ESP32 Hardware Design Guidelines <https://www.espressif.com/sites/default/files/documentation/esp32_hardware_design_guidelines_en.pdf>`_ to get into the download mode automatically.
+
+Hardware
+--------
+
+Why is my computer not detecting my board?
+******************************************
+
+If your board is not being detected after connecting to the USB, you can try the following:
+
+Solution
+^^^^^^^^
+
+* Check if the USB driver is missing. - `USB Driver Download Link  <https://www.silabs.com/developers/usb-to-uart-bridge-vcp-drivers>`_
+* Check your USB cable and try a new one.
+* Change the USB port.
+* Check your power supply.
+* Check if the board is damaged or defective.
+
+Wi-Fi
+-----
+
+Why does the board not connect to WEP/WPA-"encrypted" Wi-Fi?
+************************************************************
+
+Please note that WEP/WPA has significant security vulnerabilities, and its use is strongly discouraged.
+The support may, therefore, be removed in the future. Please migrate to WPA2 or newer.
+
+Solution
+^^^^^^^^
+
+Nevertheless, it may be necessary to connect to insecure networks. To do this, the security requirement of the ESP32 must be lowered to an insecure level by using:
+
+.. code-block:: arduino
+
+    WiFi.setMinSecurity(WIFI_AUTH_WEP); // Lower min security to WEP.
+    // or
+    WiFi.setMinSecurity(WIFI_AUTH_WPA_PSK); // Lower min security to WPA.
+
+Why does the board not connect to WPA3-encrypted Wi-Fi?
+*******************************************************
+
+WPA3 support is resource-intensive and may not be compiled into the used SDK.
+
+Solution
+^^^^^^^^
+
+* Check WPA3 support by your SDK.
+* Compile your custom SDK with WPA3 support.
+
+Sample code to check SDK WPA3 support at compile time:
+
+.. code-block:: arduino
+
+    #ifndef CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE
+    #warning "No WPA3 support."
+    #endif
+
+Serial not printing
+*******************
+
+I have uploaded firmware to the ESP32 device, but I don't see any response from a Serial.print (HardwareSerial).
+
+Solution
+^^^^^^^^
+
+Newer ESP32 variants have two possible USB connectors - USB and UART. The UART connector will go through a USB->UART adapter, and will typically present itself with the name of that mfr (eg, Silicon Labs CP210x UART Bridge). The USB connector can be used as a USB-CDC bridge and will appear as an Espressif device (Espressif USB JTAG/serial debug unit). On Espressif devkits, both connections are available, and will be labeled. ESP32 can only use UART, so will only have one connector. Other variants with one connector will typically be using USB. Please check in the product [datasheet](https://products.espressif.com) or [hardware guide](https://www.espressif.com/en/products/devkits) to find Espressif products with the appropriate USB connections for your needs.
+If you use the UART connector, you should disable USB-CDC on boot under the Tools menu (-D ARDUINO_USB_CDC_ON_BOOT=0). If you use the USB connector, you should have that enabled (-D ARDUINO_USB_CDC_ON_BOOT=1) and set USB Mode to "Hardware CDC and JTAG" (-D ARDUINO_USB_MODE=0).
+USB-CDC may not be able to initialize in time to catch all the data if your device is in a tight reboot loop. This can make it difficult to troubleshoot initialization issues.
+
+SPIFFS mount failed
+-------------------
+When you come across an error like this:
+
+.. code-block:: shell
+
+   E (588) SPIFFS: mount failed, -10025
+   [E][SPIFFS.cpp:47] begin(): Mounting SPIFFS failed! Error: -1
+
+Try enforcing format on fail in your code by adding ``true`` in the ``begin`` method such as this:
+
+.. code-block:: c++
+
+   SPIFFS.begin(true);
+
+See the method prototype for reference: ``bool begin(bool formatOnFail=false, const char * basePath="/spiffs", uint8_t maxOpenFiles=10, const char * partitionLabel=NULL);``
+
+SD card mount fail
+------------------
+Even though you made sure that the pins are correctly connected, and not using restricted pins, you may still get an error such as this:
+
+.. code-block:: shell
+
+  [ 1065][E][sd_diskio.cpp:807] sdcard_mount(): f_mount failed: (3) The physical drive cannot work
+
+Most of the problems originate from a poor connection caused by prototyping cables/wires, and one of the best solutions is to **solder all the connections** or use good quality connectors.
+
+Note that with SD_MMC lib all the data pins need to be pulled up with an external 10k to 3.3V. This applies especially to card's D3 which needs to be pulled up even when using 1-bit line connection and the D3 is not used.
+
+If you want to try the software approach before soldering, try manually specifying SPI pins, like this:
+
+.. code-block:: c++
+
+  int SD_CS_PIN = 19;
+  SPI.begin(18, 36, 26, SD_CS_PIN);
+  SPI.setDataMode(SPI_MODE0);
+  SD.begin(SD_CS_PIN);
+
+
+ESP32-S3 is rebooting even with a bare minimum sketch
+*****************************************************
+Some ESP32-S3 boards are equipped with Quad SPI (QSPI) or Octal SPI (OPI) PSRAM. If you upload such a board with default settings for ESP32-S3, it will result in rebooting with a message similar to this:
+
+https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/flash_psram_config.html
+
+.. code-block:: bash
+
+    E (124) esp_core_dump_flash: Core dump flash config is corrupted! CRC=0x7bd5c66f instead of 0x0
+    Rebooting...
+    ⸮⸮⸮ESP-ROM:esp32s3-20210327
+    Build:Mar 27 2021
+    rst:0xc (RTC_SW_CPU_RST),boot:0x18 (SPI_FAST_FLASH_BOOT)
+    Saved PC:0x40376af0
+    SPIWP:0xee
+    Octal Flash Mode Enabled
+    For OPI Flash, Use Default Flash Boot Mode
+    mode:SLOW_RD, clock div:1
+    load:0x3fce3808,len:0x44c
+    load:0x403c9700,len:0xbec
+    load:0x403cc700,len:0x2920
+    entry 0x403c98d8
+
+    assert failed: do_core_init startup.c:326 (flash_ret == ESP_OK)
+
+
+To fix the issue, you will need to find out the precise module you are using and set **PSRAM** in the Arduino IDE Tools according to the following table.
+
+How to determine the module version:
+------------------------------------
+
+* First determine if you have a `WROOM-1 <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf>`_ or `WROOM-2 <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-2_datasheet_en.pdf>`_ module - this is written on the module shielding almost at the top, right under the ESP logo and company name (Espresif) right after the ESP32-S3 - for example ESP32-S3-WROOM-2.
+* Then locate the version code on left bottom corner on the module shielding. The markings are very small and it might be really difficult to read with naked eyes - try using a camera with careful lighting.
+
+With this knowledge find your module in the table and note what is written in the **PSRAM** column.
+
+- If the results is empty (-) you don't need to change anything
+- For QSPI go to Tools > PSRAM > QSPI PSRAM
+- For OPI go to Tools > PSRAM > OPI PSRAM
+
+Note that WROOM-2 has always OPI.
+
++---------+--------+------------+-------+
+| Module  | Code   | Flash Mode | PSRAM |
++=========+========+============+=======+
+| WROOM-1 | N4     | QSPI       | -     |
++---------+--------+------------+-------+
+| WROOM-1 | N8     | QSPI       | -     |
++---------+--------+------------+-------+
+| WROOM-1 | N16    | QSPI       | -     |
++---------+--------+------------+-------+
+| WROOM-1 | H4     | QSPI       | -     |
++---------+--------+------------+-------+
+| WROOM-1 | N4R2   | QSPI       | QSPI  |
++---------+--------+------------+-------+
+| WROOM-1 | N8R2   | QSPI       | QSPI  |
++---------+--------+------------+-------+
+| WROOM-1 | N16R2  | QSPI       | QSPI  |
++---------+--------+------------+-------+
+| WROOM-1 | N4R8   | QSPI       | OPI   |
++---------+--------+------------+-------+
+| WROOM-1 | N8R8   | QSPI       | OPI   |
++---------+--------+------------+-------+
+| WROOM-1 | N16R8  | QSPI       | OPI   |
++---------+--------+------------+-------+
+| WROOM-2 | N16R8V | OPI        | OPI   |
++---------+--------+------------+-------+
+| WROOM-2 | N16R8V | OPI        | OPI   |
++---------+--------+------------+-------+
+| WROOM-2 | N32R8V | OPI        | OPI   |
++---------+--------+------------+-------+
+
+
+Further Help
+------------
+
+If you encounter any other issues or need further assistance, please consult the `ESP32 Arduino Core <https://github.com/espressif/arduino-esp32>`_ documentation or seek help from the `ESP32 community forums <https://esp32.com>`_.
diff --git a/docs/en/tutorials/basic.rst b/docs/en/tutorials/basic.rst
new file mode 100644
index 00000000000..8b932987bea
--- /dev/null
+++ b/docs/en/tutorials/basic.rst
@@ -0,0 +1,92 @@
+##############
+Basic Tutorial
+##############
+
+Introduction
+------------
+
+This is the basic tutorial and should be used as template for other tutorials.
+
+Requirements
+------------
+
+* Arduino IDE
+* ESP32 Board
+* Good USB Cable
+
+Steps
+-----
+
+Here are the steps for this tutorial.
+
+1. Open the Arduino IDE
+
+.. figure:: ../../_static/tutorials/basic/tutorial_basic_ide.png
+    :align: center
+    :width: 600
+    :alt: Arduino IDE (click to enlarge)
+    :figclass: align-center
+
+2. Build and Flash the `blink` project.
+
+Code
+----
+
+.. code-block:: arduino
+    :caption: Blink.ino
+
+    /*
+    Blink
+
+    Turns an LED on for one second, then off for one second, repeatedly.
+
+    Most Arduinos have an on-board LED you can control. On the UNO, MEGA and ZERO
+    it is attached to digital pin 13, on MKR1000 on pin 6. LED_BUILTIN is set to
+    the correct LED pin independent of which board is used.
+    If you want to know what pin the on-board LED is connected to on your Arduino
+    model, check the Technical Specs of your board at:
+    https://www.arduino.cc/en/Main/Products
+
+    modified 8 May 2014
+    by Scott Fitzgerald
+    modified 2 Sep 2016
+    by Arturo Guadalupi
+    modified 8 Sep 2016
+    by Colby Newman
+
+    This example code is in the public domain.
+
+    http://www.arduino.cc/en/Tutorial/Blink
+    */
+
+    // the setup function runs once when you press reset or power the board
+    void setup() {
+    // initialize digital pin LED_BUILTIN as an output.
+    pinMode(LED_BUILTIN, OUTPUT);
+    }
+
+    // the loop function runs over and over again forever
+    void loop() {
+    digitalWrite(LED_BUILTIN, HIGH);   // turn the LED on (HIGH is the voltage level)
+    delay(1000);                       // wait for a second
+    digitalWrite(LED_BUILTIN, LOW);    // turn the LED off by making the voltage LOW
+    delay(1000);                       // wait for a second
+    }
+
+Log Output
+----------
+
+If the log output from the serial monitor is relevant, please add here:
+
+.. code-block::
+
+    I (0) cpu_start: App cpu up.
+    I (418) cpu_start: Pro cpu start user code
+    I (418) cpu_start: cpu freq: 160000000
+
+Resources
+---------
+
+* `ESP32 Datasheet`_ (Datasheet)
+
+.. _ESP32 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf
diff --git a/docs/en/tutorials/blink.rst b/docs/en/tutorials/blink.rst
new file mode 100644
index 00000000000..f4a53ec945d
--- /dev/null
+++ b/docs/en/tutorials/blink.rst
@@ -0,0 +1,112 @@
+##########################
+Blink Interactive Tutorial
+##########################
+
+Introduction
+------------
+
+This is the interactive blink tutorial using `Wokwi`_. For this tutorial, you don't need the ESP32 board or the Arduino toolchain.
+
+.. note:: If you don't want to use this tutorial with the simulation, you can copy and paste the :ref:`blink_example_code` from `Wokwi`_ editor and use it on the `Arduino IDE`.
+
+About this Tutorial
+-------------------
+
+This tutorial is the most basic for any get started. In this tutorial, we will show how to set a GPIO pin as an output to drive a LED to blink each 1 second.
+
+Step by step
+------------
+
+In order to make this simple blink tutorial, you'll need to do the following steps.
+
+1. **Define the GPIO for the LED.**
+
+.. code-block::
+
+    #define LED 2
+
+This ``#define LED 2`` will be used to set the GPIO2 as the ``LED`` output pin.
+
+2. **Setup.**
+
+Inside the ``setup()`` function, we need to add all things we want to run once during the startup.
+Here we'll add the ``pinMode`` function to set the pin as output.
+
+.. code-block::
+
+    void setup() {
+        pinMode(LED, OUTPUT);
+    }
+
+The first argument is the GPIO number, already defined and the second is the mode, here defined as an output.
+
+3. **Main Loop.**
+
+After the ``setup``, the code runs the ``loop`` function infinitely. Here we will handle the GPIO in order to get the LED blinking.
+
+.. code-block::
+
+    void loop() {
+        digitalWrite(LED, HIGH);
+        delay(100);
+        digitalWrite(LED, LOW);
+        delay(100);
+    }
+
+The first function is the ``digitalWrite()`` with two arguments:
+
+* GPIO: Set the GPIO pin. Here defined by our ``LED`` connected to the GPIO2.
+* State: Set the GPIO state as HIGH (ON) or LOW (OFF).
+
+This first ``digitalWrite`` we will set the LED ON.
+
+After the ``digitalWrite``, we will set a ``delay`` function in order to wait for some time, defined in milliseconds.
+
+Now we can set the GPIO to ``LOW`` to turn the LED off and ``delay`` for more few milliseconds to get the LED blinking.
+
+4. **Run the code.**
+
+To run this code, you'll need a development board and the Arduino toolchain installed on your computer. If you don't have both, you can use the simulator to test and edit the code.
+
+Simulation
+----------
+
+This simulator is provided by `Wokwi`_ and you can test the blink code and play with some modifications to learn more about this example.
+
+.. raw:: html
+
+    <iframe src="https://wokwi.com/arduino/projects/305566932847821378?embed=1" width="100%" height="400" border="0"></iframe>
+
+Change the parameters, like the delay period, to test the code right on your browser. You can add more LEDs, change the GPIO, and more.
+
+.. _blink_example_code:
+
+Example Code
+------------
+
+Here is the full blink code.
+
+.. code-block::
+
+    #define LED 2
+
+    void setup() {
+        pinMode(LED, OUTPUT);
+    }
+
+    void loop() {
+        digitalWrite(LED, HIGH);
+        delay(100);
+        digitalWrite(LED, LOW);
+        delay(100);
+    }
+
+Resources
+---------
+
+* `ESP32 Datasheet`_ (Datasheet)
+* `Wokwi`_ (Wokwi Website)
+
+.. _ESP32 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf
+.. _Wokwi: https://wokwi.com/
+.. _Arduino IDE: https://docs.espressif.com/projects/arduino-esp32/en/latest/installing.html#installing-using-boards-manager
diff --git a/docs/en/tutorials/cdc_dfu_flash.rst b/docs/en/tutorials/cdc_dfu_flash.rst
new file mode 100644
index 00000000000..0c54e38d67b
--- /dev/null
+++ b/docs/en/tutorials/cdc_dfu_flash.rst
@@ -0,0 +1,122 @@
+########################
+USB CDC and DFU Flashing
+########################
+
+Introduction
+------------
+
+Since the ESP32-S2 introduction, Espressif has been working on USB peripheral support for some of the SoC families, including the ESP32-C3 and the ESP32-S3.
+
+This new peripheral allows a lot of new possibilities, including flashing the firmware directly to the SoC without any external USB-to-Serial converter.
+
+In this tutorial, you will be guided on how to use the embedded USB to flash the firmware.
+
+**The current list of supported SoCs:**
+
+========= =======================
+SoC       USB Peripheral Support
+========= =======================
+ESP32-S2  CDC and DFU
+ESP32-C3  CDC only
+ESP32-S3  CDC and DFU
+ESP32-C6  CDC only
+ESP32-H2  CDC only
+========= =======================
+
+It's important that your board includes the USB connector attached to the embedded USB from the SoC. If your board doesn't have the USB connector, you can attach an external one to the USB pins.
+
+These instructions will only work on the supported devices with the embedded USB peripheral. This tutorial will not work if you are using an external USB-to-serial converter like FTDI, CP210x, CH340, etc.
+
+For a complete reference to the Arduino IDE tools menu, please see the `Tools Menus <../guides/tools_menu.html>`_ reference guide.
+
+USB DFU
+-------
+
+The USB DFU (Device Firmware Upgrade) is a class specification from the USB standard that adds the ability to upgrade the device firmware by the USB interface.
+
+Flashing Using DFU
+******************
+
+.. note::
+    DFU is only supported by the ESP32-S2 and ESP32-S3. See the table of supported SoCs.
+
+To use the USB DFU to flash the device, you will need to configure some settings in the Arduino IDE according to the following steps:
+
+1. Enter into Download Mode manually
+
+This step is done only for the first time you flash the firmware in this mode. To enter into the download mode, you need to press and hold BOOT button and press and release the RESET button.
+
+To check if this procedure was done correctly, now you will see the new USB device listed in the available ports. Select this new device in the **Port** option.
+
+2. Configure the USB DFU
+
+In the next step you can set the USB DFU as default on BOOT and for flashing.
+
+Go to the Tools menu in the Arduino IDE and set the following options:
+
+**For ESP32-S2**
+
+* USB DFU On Boot -> Enable
+
+* Upload Mode -> Internal USB
+
+**For ESP32-S3**
+
+* USB Mode -> USB-OTG (TinyUSB)
+
+* USB DFU On Boot -> Enabled
+
+3. Flash
+^^^^^^^^
+
+Now you can upload your sketch to the device. After flashing, you need to manually reset the device.
+
+.. note::
+        On the USB DFU, you can't use the USB for the serial output for the logging, just for flashing. To enable the serial output, use the CDC option instead.
+        If you want to use the USB DFU for just upgrading the firmware using the manual download mode, this will work just fine, however, for developing please consider using USB CDC.
+
+
+USB CDC
+-------
+
+The USB CDC (Communications Device Class) allows you to communicate to the device like in a serial interface. This mode can be used on the supported targets to flash and monitor the device in a similar way on devices that uses the external serial interfaces.
+
+To use the USB CDC, you need to configure your device in the Tools menu:
+
+
+1. Enter into Download Mode manually
+
+Similar to the DFU mode, you will need to enter into download mode manually. To enter into the download mode, you need to press and hold BOOT button and press and release the RESET button.
+
+To check if this procedure was done correctly, now you will see the new USB device listed in the available ports. Select this new device in the **Port** option.
+
+2. Configure the USB CDC
+
+**For ESP32-S2**
+
+* USB CDC On Boot -> Enabled
+
+* Upload Mode -> Internal USB
+
+**For ESP32-C3**
+
+* USB CDC On Boot -> Enabled
+
+**For ESP32-S3**
+
+* USB CDC On Boot -> Enabled
+
+* Upload Mode -> UART0 / Hardware CDC
+
+3. Flash and Monitor
+
+You can now upload your sketch to the device. After flashing for the first time, you need to manually reset the device.
+
+This procedure enables the flashing and monitoring thought the internal USB and does not requires you to manually enter into the download mode or to do the manual reset after flashing.
+
+To monitor the device, you need to select the USB port and open the Monitor tool selecting the correct baud rate (usually 115200) according to the ``Serial.begin()`` defined in your code.
+
+Hardware
+--------
+
+If you are developing a custom hardware using the compatible SoC, and want to remove the external USB-to-Serial chip, this feature will complete substitute the needs of the external chip. See the SoC datasheet for more details about this peripheral.
diff --git a/docs/en/tutorials/io_mux.rst b/docs/en/tutorials/io_mux.rst
new file mode 100644
index 00000000000..3cff49812b1
--- /dev/null
+++ b/docs/en/tutorials/io_mux.rst
@@ -0,0 +1,120 @@
+#######################
+GPIO Matrix and Pin Mux
+#######################
+
+Introduction
+------------
+
+This is a basic introduction to how the peripherals work in the ESP32. This tutorial can be used to understand
+how to define the peripheral usage and its corresponding pins.
+
+In some microcontrollers' architecture, the peripherals are attached to specific pins and cannot be redefined to another one.
+
+For example:
+
+The *XYZ* MCU defines that the I2C peripheral SDA signal is the IO5 on the physical pin 10 and the SCL is on the IO6 and physical pin 11.
+
+This means that, in your hardware project, you **NEED** to use these pins as the I2C and this cannot be changed due to the internal architecture.
+In this case, you must be very careful during the hardware design to not make any mistake by switching the SDA and SCL connections. Firmware will not help you if you do so.
+
+GPIO Matrix and Pin Mux
+-----------------------
+
+The ESP32 architecture includes the capability of configuring some peripherals to any of the GPIOs pins, managed by the `IO MUX GPIO`_.
+Essentially, this capability means that we can route the internal peripheral into a different physical pin using the IO MUX and the GPIO Matrix.
+
+.. figure:: ../../_static/tutorials/peripherals/tutorial_peripheral_diagram.png
+    :align: center
+    :width: 600
+    :figclass: align-center
+
+It means that in the scenario of the *XYZ* MCU, in the ESP32 we can use any of the GPIOs to route the SDA (input/output) and the SCL (output).
+
+To use this functionality, we must be aware of some precautions:
+
+* Some of the GPIOs are **INPUT** only.
+* Some peripherals have output signals and must be used on GPIO's capable to be configured as **OUTPUT**.
+* Some peripherals, mostly the high speed ones, ADC, DAC, Touch, and JTAG use dedicated GPIOs pins.
+* Some pins are used to connect flash memory on the module - this prevents them from any other use - if a peripheral is routed to one of these pins the device will not be able to boot.
+
+.. warning::
+    Before assigning the peripheral pins in your design, double check if the pins you're using are appropriate.
+    The input-only pins cannot be used for peripherals that require output or input/output signals.
+
+The greatest advantage of this functionality is the fact that we don't need to be fully dependent on the physical pin, since we can change according to our needs.
+This can facilitate the hardware design routing or in some cases, fix some pin swap mistake during the hardware design phase.
+
+Peripherals
+-----------
+
+Here is the basic peripherals list present on the `ESP32`_. The peripheral list may vary from each ESP32 SoC family.
+To see all peripherals available on the `ESP32-S2`_ and `ESP32-C3`_, check each of the datasheets.
+
+Peripheral Table
+****************
+
+==============================  ===================================
+Type                            Function
+==============================  ===================================
+ADC                             Dedicated GPIOs
+DAC                             Dedicated GPIOs
+Touch Sensor                    Dedicated GPIOs
+JTAG                            Dedicated GPIOs
+SD/SDIO/MMC HostController      Dedicated GPIOs
+Motor PWM                       Any GPIO
+SDIO/SPI SlaveController        Dedicated GPIOs
+UART                            Any GPIO[1]
+I2C                             Any GPIO
+I2S                             Any GPIO
+LED PWM                         Any GPIO
+RMT                             Any GPIO
+GPIO                            Any GPIO
+Parallel QSPI                   Dedicated GPIOs
+EMAC                            Dedicated GPIOs
+Pulse Counter                   Any GPIO
+TWAI                            Any GPIO
+USB                             Dedicated GPIOs
+==============================  ===================================
+
+[1] except for the download/programming mode decided by the bootloader.
+
+This table is present on each datasheet provided by Espressif.
+
+Usage Examples
+--------------
+
+In the Arduino Uno, we have the I2C pins defined by hardware, A4 is the SDA and A5 the SCL. In this case, we do not need to set
+these pins in the ``Wire.begin();`` function, because they are already into the Wire library.
+
+.. code-block:: arduino
+
+    void setup()
+    {
+        Wire.begin(); // join i2c bus (address optional for master)
+    }
+
+Now, for the ESP32, the default pins for the I2C are SDA (GPIO21) and SCL (GPIO22). We can use a different pin as alternative for the
+default ones if you need to change the pins.
+To change the pins, we must call the ``Wire.setPins(int sda, int scl);`` function before calling ``Wire.begin();``.
+
+.. code-block:: arduino
+
+    int sda_pin = 16; // GPIO16 as I2C SDA
+    int scl_pin = 17; // GPIO17 as I2C SCL
+
+    void setup()
+    {
+        Wire.setPins(sda_pin, scl_pin); // Set the I2C pins before begin
+        Wire.begin(); // join i2c bus (address optional for master)
+    }
+
+A similar approach also applies for the other peripherals.
+
+.. include:: ../common/datasheet.inc
+
+Resources
+---------
+
+.. _Espressif Systems: https://www.espressif.com
+.. _Espressif Product Selector: https://products.espressif.com/
+.. _IO MUX GPIO: https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf#iomuxgpio
diff --git a/docs/en/tutorials/partition_table.rst b/docs/en/tutorials/partition_table.rst
new file mode 100644
index 00000000000..fdaee9f9bbb
--- /dev/null
+++ b/docs/en/tutorials/partition_table.rst
@@ -0,0 +1,202 @@
+###############
+Partition Table
+###############
+
+Introduction
+------------
+
+Partition table is used to define the flash memory organization and the different kind of data will be stored on each partition.
+
+You can use one of the available partition table scheme or create your own. You can see all the different schemes on the `tools/partitions <https://github.com/espressif/arduino-esp32/tree/master/tools/partitions>`_ folder or by the Arduino IDE tools menu `Tools -> Partition Scheme`.
+
+The partition table is created by a .CSV (Comma-separated Values) file with the following structure:
+
+.. code-block::
+
+    # ESP-IDF Partition Table
+    # Name, Type, SubType, Offset, Size, Flags
+
+Where:
+
+1. **Name**
+
+    Is the partition name and must be a unique name. This name is not relevant for the system and the size must be at maximum of 16-chars (no special chars).
+
+2. **Type**
+
+    This is the type of the partition. This value can be ``data`` or ``app``.
+
+    * ``app`` type is used to define the partition that will store the application.
+
+    * ``data`` type can be used to define the partition that stores general data, not the application.
+
+3. **SubType**
+
+    The SubType defines the usage of the ``app`` and ``data`` partitions.
+
+   **data**
+
+       ``ota``
+
+           The ota subtype is used to store the OTA information. This partition is used only when the OTA is used to select the initialization partition, otherwise no need to add it to your custom partition table.
+           The size of this partition should be a fixed size of 8 kB (0x2000 bytes).
+
+       ``nvs``
+
+           The nvs partition subtype is used to define the partition to store general data, like the Wi-Fi data, device PHY calibration data and any other data to be stored on the non-volatile memory.
+           This kind of partition is suitable for small custom configuration data, cloud certificates, etc. Another usage for the NVS is to store sensitive data, since the NVS supports encryption.
+           It is highly recommended to add at least one nvs partition, labeled with the name nvs, in your custom partition tables with size of at least 12 kB (0x3000 bytes). If needed, you can increase the size of the nvs partition.
+           The recommended size for this partition is from 12 kB to 64 kB. Although larger NVS partitions can be defined, we recommend using FAT or SPIFFS filesystem for storage of larger amounts of data.
+
+       ``coredump``
+
+           The coredump partition subtype is used to store the core dump on the flash. The core dump is used to analyze critical errors like crash and panic.
+           This function must be enabled in the project configuration menu and set the data destination to flash.
+           The recommended size for this partition is 64 kB (0x10000).
+
+       ``nvs_keys``
+
+           The nvs_keys partition subtype is used to store the keys when the NVS encryption is used.
+           The size for this partition is 4 kB (0x1000).
+
+       ``fat``
+
+           The fat partition subtype defines the FAT filesystem usage, and it is suitable for larger data and if this data is often updated and changed. The FAT FS can be used with wear leveling feature to increase the erase/modification cycles per memory sector and encryption for sensitive data storage, like cloud certificates or any other data that may be protected.
+           To use FAT FS with wear leveling see the example.
+
+       ``spiffs``
+
+           The spiffs partition subtype defines the SPI flash filesystem usage, and it is also suitable for larger files and it also performs the wear leveling and file system consistency check.
+           The SPIFFS do not support flash encryption.
+
+   **app**
+
+    ``factory``
+
+        The factory partition subtype is the default application. The bootloader will set this partition as the default application initialization if no OTA partition is found, or the OTA partitions are empty.
+        If the OTA partition is used, the ota_0 can be used as the default application and the factory can be removed from the partition table to save memory space.
+
+    ``ota_0`` to ``ota_15``
+
+        The ota_x partition subtype is used for the Over-the air update. The OTA feature requires at least two ota_x partition (usually ota_0 and ota_1) and it also requires the ota partition to keep the OTA information data.
+        Up to 16 OTA partitions can be defined but only two are needed for basic OTA feature.
+
+    ``test``
+
+        The test partition subtype is used for factory test procedures.
+
+4. **Offset**
+
+    The offset defines the partition start address. The offset is defined by the sum of the offset and the size of the earlier partition.
+
+.. note::
+    Offset must be multiple of 4 kB (0x1000) and for app partitions it must be aligned by 64 kB (0x10000).
+    If left blank, the offset will be automatically calculated based on the end of the previous partition, including any necessary alignment, however, the offset for the first partition must be always set as **0x9000** and for the first application partition **0x10000**.
+
+5. **Size**
+
+    Size defines the amount of memory to be allocated on the partition. The size can be formatted as decimal, hex numbers (0x prefix), or using unit prefix K (kilo) or M (mega) i.e: 4096 = 4K = 0x1000.
+
+6. **Flags**
+
+    The last column in the CSV file is the flags and it is currently used to define if the partition will be encrypted by the flash encryption feature.
+
+
+For example, **the most common partition** is the ``default_8MB.csv`` (see `tools/partitions <https://github.com/espressif/arduino-esp32/tree/master/tools/partitions>`_ folder for some examples):
+
+.. code-block::
+
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     0x9000,  0x5000,
+    otadata,  data, ota,     0xe000,  0x2000,
+    app0,     app,  ota_0,   0x10000, 0x330000,
+    app1,     app,  ota_1,   0x340000,0x330000,
+    spiffs,   data, spiffs,  0x670000,0x190000,
+
+Using a Custom Partition Scheme
+-------------------------------
+
+To create your own partition table, you can create the ``partitions.csv`` file **in the same folder you created your sketch**. The build system will automatically pick the partition table file and use it instead of the predefined ones.
+
+Here is an example you can use for a custom partition table:
+
+.. code-block::
+
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     36K,     20K,
+    otadata,  data, ota,     56K,     8K,
+    app0,     app,  ota_0,   64K,     2M,
+    app1,     app,  ota_1,   ,        2M,
+    spiffs,   data, spiffs,  ,        8M,
+
+This partition will use about 12 MB of the 16 MB flash. The offset will be automatically calculated after the first application partition and the units are in K and M.
+
+An alternative is to create the new partition table as a new file in the `tools/partitions <https://github.com/espressif/arduino-esp32/tree/master/tools/partitions>`_ folder and edit the `boards.txt <https://github.com/espressif/arduino-esp32/tree/master/boards.txt>`_ file to add your custom partition table.
+
+Another alternative is to create the new partition table as a new file, and place it in the `variants <https://github.com/espressif/arduino-esp32/tree/master/variants>`_ folder under your boards folder, and edit the `boards.txt <https://github.com/espressif/arduino-esp32/tree/master/boards.txt>`_ file to add your custom partition table, noting that in order for the compiler to find your custom partition table file you must use the '.build.custom_partitions=' option in the boards.txt file, rather than the standard '.build.partitions=' option. The '.build.variant=' option has the name of the folder holding your custom partition table in the variants folder.
+
+An example of the PartitionScheme listing using the ESP32-S3 Dev Module as a reference, would be to have the following:
+
+**Custom Partition - CSV file in /variants/custom_esp32s3/ folder**
+
+.. code-block::
+
+    esp32s3.build.variant=custom_esp32s3
+    --
+    esp32s3.menu.PartitionScheme.huge_app=Custom Huge APP (3MB No OTA/1MB SPIFFS)
+    esp32s3.menu.PartitionScheme.huge_app.build.custom_partitions=custom_huge_app
+    esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
+
+Examples
+--------
+
+**2 MB no OTA**
+
+.. code-block::
+
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     36K,     20K,
+    factory,  app,  factory, 64K,     1900K,
+
+**4 MB no OTA**
+
+.. code-block::
+
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     36K,     20K,
+    factory,  app,  factory, 64K,     4000K,
+
+**4 MB with OTA**
+
+.. code-block::
+
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     36K,     20K,
+    otadata,  data, ota,     56K,     8K,
+    app0,     app,  ota_0,   64K,     1900K,
+    app1,     app,  ota_1,   ,        1900K,
+
+**8 MB no OTA with Storage**
+
+.. code-block::
+
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     36K,     20K,
+    factory,  app,  factory, 64K,     2M,
+    spiffs,   data, spiffs,  ,        5M,
+
+**8 MB with OTA and Storage**
+
+.. code-block::
+
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     36K,     20K,
+    otadata,  data, ota,     56K,     8K,
+    app0,     app,  ota_0,   64K,     2M,
+    app1,     app,  ota_1,   ,        2M,
+    spiffs,   data, spiffs,  ,        3M,
+
+Reference
+---------
+
+This documentation was based on the `How to use custom partition tables on ESP32 <https://medium.com/p/69c0f3fa89c8>`_ article.
diff --git a/docs/en/tutorials/preferences.rst b/docs/en/tutorials/preferences.rst
new file mode 100644
index 00000000000..9354fa83b16
--- /dev/null
+++ b/docs/en/tutorials/preferences.rst
@@ -0,0 +1,710 @@
+###########
+Preferences
+###########
+
+
+Introduction
+------------
+
+The Preferences library is unique to arduino-esp32. It should be considered as the replacement for the Arduino EEPROM library.
+
+It uses a portion of the on-board non-volatile memory (NVS) of the ESP32 to store data. This data is retained across restarts and loss of power events to the system.
+
+Preferences works best for storing many small values, rather than a few large values. If you need to store large amounts of data, consider using a file system library such as LitteFS.
+
+The Preferences library is usable by all ESP32 variants.
+
+
+Preferences Attributes
+----------------------
+
+Preferences data is stored in NVS in sections called a "``namespace``". Within each namespace are a set of ``key-value`` pairs. The "``key``" is the name of the data item and the "``value``" is, well, the value of that piece of data. Kind of like variables. The key is the name of the variable and the value is its value. Like variables, a ``key-value`` pair has a data type.
+
+Multiple namespaces are permitted within NVS. The name of each namespace must be unique. The keys within that namespace are unique to that namespace. Meaning the same key name can be used in multiple namespaces without conflict.
+
+Namespace and key names are case sensitive.
+
+Each key name must be unique within a namespace.
+
+Namespace and key names are character strings and are limited to a maximum of 15 characters.
+
+Only one namespace can be open (in use) at a time.
+
+
+Library Overview
+----------------
+
+Library methods are provided to:
+   - create a namespace;
+   - open and close a namespace;
+   - store and retrieve data within a namespace for supported data types;
+   - determine if a key value has been initialized;
+   - delete a ``key-value`` pair;
+   - delete all ``key-value`` pairs in a namespace;
+   - determine data types stored against a key;
+   - determine the number of key entries available in the namespace.
+
+Preferences directly supports the following data types:
+
+.. table:: **Table 1 — Preferences Types**
+   :align: center
+
+   +-------------------+-------------------+---------------+
+   | Preferences Type  | Data Type         | Size (bytes)  |
+   +===================+===================+===============+
+   | Bool              | bool              | 1             |
+   +-------------------+-------------------+---------------+
+   | Char              | int8_t            | 1             |
+   +-------------------+-------------------+---------------+
+   | UChar             | uint8_t           | 1             |
+   +-------------------+-------------------+---------------+
+   | Short             | int16_t           | 2             |
+   +-------------------+-------------------+---------------+
+   | UShort            | uint16_t          | 2             |
+   +-------------------+-------------------+---------------+
+   | Int               | int32_t           | 4             |
+   +-------------------+-------------------+---------------+
+   | UInt              | uint32_t          | 4             |
+   +-------------------+-------------------+---------------+
+   | Long              | int32_t           | 4             |
+   +-------------------+-------------------+---------------+
+   | ULong             | uint32_t          | 4             |
+   +-------------------+-------------------+---------------+
+   | Float             | float_t           | 4             |
+   +-------------------+-------------------+---------------+
+   | Long64            | int64_t           | 8             |
+   +-------------------+-------------------+---------------+
+   | ULong64           | uint64_t          | 8             |
+   +-------------------+-------------------+---------------+
+   | Double            | double_t          | 8             |
+   +-------------------+-------------------+---------------+
+   |                   | const char*       | variable      |
+   | String            +-------------------+               |
+   |                   | String            |               |
+   +-------------------+-------------------+---------------+
+   | Bytes             | uint8_t           | variable      |
+   +-------------------+-------------------+---------------+
+
+String values can be stored and retrieved either as an Arduino String or as a null terminated ``char`` array (C-string).
+
+Bytes type is used for storing and retrieving an arbitrary number of bytes in a namespace.
+
+
+Workflow
+--------
+
+Preferences workflow, once everything is initialized, is pretty simple.
+
+To store a value:
+   -  Open the namespace in read-write mode.
+   -  Put the value into the key.
+   -  Close the namespace.
+
+To retrieve a value:
+   -  Open the namespace in read-only mode.
+   -  Use the key to get the value.
+   -  Close the namespace.
+
+*(Technically, you can retrieve a value if the namespace is open in either read-only or read-write mode but it's good practice to open the namespace in read-only mode if you are only retrieving values.)*
+
+When storing information, a "``put[PreferencesType]``" method referenced to its key is used.
+
+When retrieving information a "``get[PreferencesType]``" method referenced to its key is used.
+
+Ensuring that the data types of your “``get``'s” and “``put``'s” all match, you’re good to go.
+
+The nuance is in initializing everything at the start.
+
+Before you can store or retrieve anything using Preferences, both the namespace and the key within that namespace need to exist. So the workflow is:
+
+#. Create or open the namespace.
+#. Test for the existence of a key that should exist if the namespace has been initialized.
+#. If that key does not exist, create the key(s).
+#. Carry on with the rest of your sketch where data can now be stored and retrieved from the namespace.
+
+Each step is discussed below.
+
+.. note::
+
+   From here on when referring in general to a method used to store or retrieve data we'll use the shorthand "``putX``" and "``getX``" where the "``X``" is understood to be a Preferences Type; Bool, UInt, Char, and so on from the Preferences Types table above.
+
+..
+
+
+Create or Open the Namespace
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+In your sketch, first insert a declaration of a ``Preferences`` object by including a line like;
+
+.. code-block:: arduino
+
+   Preferences mySketchPrefs;    // "mySketchPrefs" is the name of the Preferences object.
+                                 //  Can be whatever you want.
+
+This object is used with the Preferences methods to access the namespace and the key-value pairs it contains.
+
+A namespace is made available for use with the ``.begin`` method:
+
+.. code-block:: arduino
+
+  mySketchPrefs.begin("myPrefs", false)
+
+If the namespace does not yet exist, this will create and then open the namespace ``myPrefs``.
+
+If the namespace already exists, this will open the namespace ``myPrefs``.
+
+If the second argument is ``false`` the namespace is opened in read-write (RW) mode — values can be stored in to and retrieved from the namespace. If it is ``true`` the namespace is opened in read-only (RO) mode — values can be retrieved from the namespace but nothing can be stored.
+
+
+Test for Initial Existence of Your Key(s)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+When the ESP32 boots, there is no inherent way to know if this is the very first time it has ever powered on or if it is a subsequent launch and it has run its sketch before. We can use Preferences to store information that is retained across reboots that we can read, and based on that, decide if this is a first-time run and take the required actions if so.
+
+We do this by testing for the existence of a certain key within a namespace. If that key exists, it is safe to assume the key was created during the first-time run of the sketch and so the namespace has already been initialized.
+
+To determine if a key exists, use:
+
+.. code-block:: arduino
+
+   isKey("myTestKey")
+
+This returns ``true`` if  ``"myTestKey"`` exists in the namespace, and ``false`` if it does not.
+
+By example, consider this code segment:
+
+.. code-block:: arduino
+
+   Preferences mySketchPrefs;
+   String doesExist;
+
+   mySketchPrefs.begin("myPrefs", false);   // open (or create and then open if it does not
+                                            //  yet exist) the namespace "myPrefs" in RW mode.
+
+   bool doesExist = mySketchPrefs.isKey("myTestKey");
+
+   if (doesExist == false) {
+       /*
+          If doesExist is false, we will need to create our
+           namespace key(s) and store a value into them.
+      */
+
+      // Insert your "first time run" code to create your keys & assign their values below here.
+   }
+   else {
+      /*
+          If doesExist is true, the key(s) we need have been created before
+           and so we can access their values as needed during startup.
+      */
+
+      // Insert your "we've been here before" startup code below here.
+   }
+
+
+
+Creating Namespace Keys and Storing Values
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To create a key, we use one of the  ``.putX`` methods, matching ``"X"`` to the Preferences Type of the data we wish to store:
+
+.. code-block:: arduino
+
+   myPreferences.putX("myKeyName", value)
+
+If ``"myKeyName"`` does not exist in the namespace, it is first created and then ``value`` is stored against that keyname. The namespace must be open in RW mode to do this. Note that ``value`` is not optional and must be provided with every "``.putX``" statement. Thus every key within a namespace will always hold a valid value.
+
+An example is:
+
+.. code-block:: arduino
+
+   myPreferences.putFloat("pi", 3.14159265359);    // stores an float_t data type
+                                                   //  against the key "pi".
+
+Reading Values From a Namespace
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Once a key exists in a namespace and the namespace is open, its value is retrieved using one of the ``getX`` methods, matching ``"X"`` to the type of data stored against that key.
+
+.. code-block:: arduino
+
+   myPreferences.getX("myKeyName")
+
+Like so:
+
+.. code-block:: arduino
+
+   float_t myFloat = myPreferences.getFloat("pi");
+
+This will retrieve the float_t value from the namespace key ``"pi"`` and assign it to the float_t type variable ``myFloat``.
+
+
+Summary
+~~~~~~~
+
+So the basics of using Preferences are:
+
+   #. You cannot store into or retrieve from a ``key-value`` pair until a namespace is created and opened and the key exists in that namespace.
+
+   #. If the key already exists, it was created the first time the sketch was run.
+
+   #. A key value can be retrieved regardless of the mode in which the namespace was opened, but a value can only be stored if the namespace is open in read-write mode.
+
+   #. Data types of the “``get``'s” and “``put``'s” must match.
+
+   #. Remember the 15 character limit for namespace and key names.
+
+
+Real World Example
+------------------
+
+Here is part of a ``setup()`` function that uses Preferences.
+
+Its purpose is to set either a factory default configuration if the system has never run before, or use the last configuration if it has.
+
+When started, the system has no way of knowing which of the above conditions is true. So the first thing it does after opening the namespace is check for the existence of a key that we have predetermined can only exist if we have previously run the sketch. Based on its existence we decide if a factory default set of operating parameters should be used (and in so doing create the namespace keys and populate the values with defaults) or if we should use operating parameters from the last time the system was running.
+
+.. code-block:: arduino
+
+   #include <Preferences.h>
+
+   #define RW_MODE false
+   #define RO_MODE true
+
+   Preferences stcPrefs;
+
+   void setup() {
+
+      // not the complete setup(), but in setup(), include this...
+
+      stcPrefs.begin("STCPrefs", RO_MODE);           // Open our namespace (or create it
+                                                     //  if it doesn't exist) in RO mode.
+
+      bool tpInit = stcPrefs.isKey("nvsInit");       // Test for the existence
+                                                     // of the "already initialized" key.
+
+      if (tpInit == false) {
+         // If tpInit is 'false', the key "nvsInit" does not yet exist therefore this
+         //  must be our first-time run. We need to set up our Preferences namespace keys. So...
+         stcPrefs.end();                             // close the namespace in RO mode and...
+         stcPrefs.begin("STCPrefs", RW_MODE);        //  reopen it in RW mode.
+
+
+         // The .begin() method created the "STCPrefs" namespace and since this is our
+         //  first-time run we will create
+         //  our keys and store the initial "factory default" values.
+         stcPrefs.putUChar("curBright", 10);
+         stcPrefs.putString("talChan", "one");
+         stcPrefs.putLong("talMax", -220226);
+         stcPrefs.putBool("ctMde", true);
+
+         stcPrefs.putBool("nvsInit", true);          // Create the "already initialized"
+                                                     //  key and store a value.
+
+         // The "factory defaults" are created and stored so...
+         stcPrefs.end();                             // Close the namespace in RW mode and...
+         stcPrefs.begin("STCPrefs", RO_MODE);        //  reopen it in RO mode so the setup code
+                                                     //  outside this first-time run 'if' block
+                                                     //  can retrieve the run-time values
+                                                     //  from the "STCPrefs" namespace.
+      }
+
+      // Retrieve the operational parameters from the namespace
+      //  and save them into their run-time variables.
+      currentBrightness = stcPrefs.getUChar("curBright");  //
+      tChannel = stcPrefs.getString("talChan");            //  The LHS variables were defined
+      tChanMax = stcPrefs.getLong("talMax");               //   earlier in the sketch.
+      ctMode = stcPrefs.getBool("ctMde");                  //
+
+      // All done. Last run state (or the factory default) is now restored.
+      stcPrefs.end();                                      // Close our preferences namespace.
+
+      // Carry on with the rest of your setup code...
+
+      // When the sketch is running, it updates any changes to an operational parameter
+      //  to the appropriate key-value pair in the namespace.
+
+   }
+
+
+Utility Functions
+-----------------
+
+There are a few other functions useful when working with namespaces.
+
+Deleting key-value Pairs
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: arduino
+
+   preferences.clear();
+
+..
+
+      - Deletes *all* the key-value pairs in the currently opened namespace.
+
+        - The namespace still exists.
+
+        - The namespace must be open in read-write mode for this to work.
+
+.. code-block:: arduino
+
+   preferences.remove("keyname");
+
+..
+
+      - Deletes the "keyname" and value associated with it from the currently opened namespace.
+
+        - The namespace must be open in read-write mode for this to work.
+        - Tip: use this to remove the "test key" to force a "factory reset" during the next reboot (see the *Real World Example* above).
+
+If either of the above are used, the ``key-value`` pair will need to be recreated before using it again.
+
+
+Determining the Number of Available Keys
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For each namespace, Preferences keeps track of the keys in a key table. There must be an open entry in the table before a key can be created. This method will return the number of entries available in the table.
+
+.. code-block:: arduino
+
+   freeEntries()
+
+..
+
+To send to the serial monitor the number of available entries the following could be used.
+
+.. code-block:: arduino
+
+   Preferences mySketchPrefs;
+
+   mySketchPrefs.begin("myPrefs", true);
+   size_t whatsLeft = freeEntries();    // this method works regardless of the mode in which the namespace is opened.
+   Serial.printf("There are: %u entries available in the namespace table.\n, whatsLeft);
+   mySketchPrefs.end();
+
+..
+
+The number of available entries in the key table changes depending on the number of keys in the namespace and also the dynamic size of certain types of data stored in the namespace. Details are in the `Preferences API Reference`_.
+
+Do note that the number of entries in the key table does not guarantee that there is room in the opened NVS namespace for all the data to be stored in that namespace. Refer to the Espressif `Non-volatile storage library`_ documentation for full details.
+
+
+Determining the Type of a key-value Pair
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Keeping track of the data types stored against a key-value pair is one of the bookkeeping tasks left to you. Should you want to discover the Preferences data type stored against a given key, use this method:
+
+.. code-block:: arduino
+
+   getType("myKey")
+
+..
+
+As in:
+
+.. code-block:: arduino
+
+   PreferenceType whatType = getType("myKey");
+
+..
+
+The value returned is a ``PreferenceType`` value that maps to a Preferences Type. Refer to the description in the `Preferences API Reference`_ for details.
+
+
+
+Working with Large Data
+-----------------------
+
+Recall that the Preferences library works best for storing many small values, rather than a few large values. Regardless, it may be desirable to store larger amounts of arbitrary data than what is provided by the basic types in the Preferences Types table above.
+
+The library provides the following methods to facilitate this.
+
+.. code-block:: arduino
+
+   putBytes("myBytesKey", value, valueLen)
+   getBytes("myBytesKey", buffer, valueLen)
+   getBytesLength("myBytesKey")
+
+..
+
+The ``put`` and ``get`` ``Bytes`` methods store and retrieve the data. The ``getBytesLength`` method is used to find the size of the data stored against the key (which is needed to retrieve ``Bytes`` data).
+
+As the names of the methods imply, they operate on variable length bytes of data (often referred to as a "blob") and not on individual elements of a certain data type.
+
+Meaning if you store for example an array of type ``int16_t`` against a ``Bytes`` type key, the value of that key becomes a series of bytes with no associated data type. Or if you like, all data stored as a blob gets converted to a series of ``uint8_t`` type bytes.
+
+As a result, when using the ``getBytes`` method to retrieve the value of the key, what is returned to the buffer is a series of ``uint8_t`` bytes. It is up to you to manage the data types and size of the arrays and buffers when retrieving ``Bytes`` data.
+
+Fortunately this is not as difficult as it may sound as the ``getBytesLength`` method and the ``sizeof`` operator help with keeping track of it all.
+
+This is best explained with an example. Here the ``Bytes`` methods are used to store and retrieve an array, while ensuring the data type is preserved.
+
+.. code-block:: arduino
+
+   /*
+    *  An example sketch using the Preferences "Bytes" methods
+    *   to store and retrieve an arbitrary number of bytes in
+    *   a namespace.
+    */
+
+   #include <Preferences.h>
+
+   #define RO_MODE true
+   #define RW_MODE false
+
+   void setup() {
+
+       Preferences mySketchPrefs;
+
+       Serial.begin(115200);
+       delay(250);
+
+       mySketchPrefs.begin("myPrefs", RW_MODE);   // open (or create) the namespace
+                                                  //  "myPrefs" in RW mode
+       mySketchPrefs.clear();                     // delete any previous keys in this namespace
+
+       // Create an array of test values. We're using hex numbers
+       //  throughout to better show how the bytes move around.
+       int16_t myArray[] = { 0x1112, 0x2122, 0x3132, 0x4142, 0x5152, 0x6162, 0x7172 };
+
+       Serial.println("Printing myArray...");
+       for (int i = 0; i < sizeof(myArray) / sizeof(int16_t); i++) {
+           Serial.print(myArray[i], HEX); Serial.print(", ");
+       }
+       Serial.println("\r\n");
+
+       // In the next statement, the second sizeof() needs
+       //  to match the data type of the elements of myArray
+       Serial.print("The number of elements in myArray is: ");
+       Serial.println( sizeof(myArray) / sizeof(int16_t) );
+       Serial.print("But the size of myArray in bytes is: ");
+       Serial.println( sizeof(myArray) );
+       Serial.println("");
+
+       Serial.println(
+         "Storing myArray into the Preferences namespace \"myPrefs\" against the key \"myPrefsBytes\".");
+       // Note: in the next statement, to store the entire array, we must use the
+       //  size of the array in bytes, not the number of elements in the array.
+       mySketchPrefs.putBytes( "myPrefsBytes", myArray, sizeof(myArray) );
+       Serial.print("The size of \"myPrefsBytes\" is (in bytes): ");
+       Serial.println( mySketchPrefs.getBytesLength("myPrefsBytes") );
+       Serial.println("");
+
+       int16_t myIntBuffer[20] = {}; // No magic about 20. Just making a buffer (array) big enough.
+       Serial.println("Retrieving the value of myPrefsBytes into myIntBuffer.");
+       Serial.println("   - Note the data type of myIntBuffer matches that of myArray");
+       mySketchPrefs.getBytes("myPrefsBytes", myIntBuffer,
+                              mySketchPrefs.getBytesLength("myPrefsBytes"));
+
+       Serial.println("Printing myIntBuffer...");
+       // In the next statement, sizeof() needs to match the data type of the elements of myArray
+       for (int i = 0; i < mySketchPrefs.getBytesLength("myPrefsBytes") / sizeof(int16_t); i++) {
+          Serial.print(myIntBuffer[i], HEX); Serial.print(", ");
+       }
+       Serial.println("\r\n");
+
+       Serial.println(
+         "We can see how the data from myArray is actually stored in the namespace as follows.");
+       uint8_t myByteBuffer[40] = {}; // No magic about 40. Just making a buffer (array) big enough.
+       mySketchPrefs.getBytes("myPrefsBytes", myByteBuffer,
+                              mySketchPrefs.getBytesLength("myPrefsBytes"));
+
+       Serial.println("Printing myByteBuffer...");
+       for (int i = 0; i < mySketchPrefs.getBytesLength("myPrefsBytes"); i++) {
+          Serial.print(myByteBuffer[i], HEX); Serial.print(", ");
+       }
+       Serial.println("");
+
+   }
+
+   void loop() {
+     ;
+   }
+
+..
+
+The resulting output is:
+::
+
+   Printing myArray...
+   1112, 2122, 3132, 4142, 5152, 6162, 7172,
+
+   The number of elements in myArray is: 7
+   But the size of myArray in bytes is: 14
+
+   Storing myArray into the Preferences namespace "myPrefs" against the key "myPrefsBytes".
+   The size of "myPrefsBytes" is (in bytes): 14
+
+   Retrieving the value of myPrefsBytes into myIntBuffer.
+      - Note the data type of myIntBuffer matches that of myArray
+   Printing myIntBuffer...
+   1112, 2122, 3132, 4142, 5152, 6162, 7172,
+
+   We can see how the data from myArray is actually stored in the namespace as follows.
+   Printing myByteBuffer...
+   12, 11, 22, 21, 32, 31, 42, 41, 52, 51, 62, 61, 72, 71,
+
+You can copy the sketch and change the data type and values in ``myArray`` and follow along with the code and output to see how the ``Bytes`` methods work. The data type of ``myIntBuffer`` should be changed to match that of ``myArray`` (and check the "``sizeof()``'s" where indicated in the comments).
+
+The main takeaway is to remember you're working with bytes and so attention needs to be paid to store all the data based on the size of its type and to manage the buffer size and data type for the value retrieved.
+
+
+Multiple Namespaces
+-------------------
+
+As stated earlier, multiple namespaces can exist in the Preferences NVS partition. However, only one namespace at a time can be open (in use).
+
+If you need to access a different namespace, close the one before opening the other. For example:
+
+.. code-block:: arduino
+
+   Preferences currentNamespace;
+
+      currentNamespace.begin("myNamespace", false);
+         // do stuff...
+
+      currentNamespace.end();                              // closes 'myNamespace'
+
+      currentNamespace.begin("myOtherNamespace", false);   // opens a different Preferences namespace.
+         // do other stuff...
+
+      currentNamespace.end();                              // closes 'myOtherNamespace'
+
+Here the "``currentNamespace``" object is reused, but different Preferences objects can be declared and used. Just remember to keep it all straight as all "``putX``'s" and "``getX``'s", etc. will only operate on the single currently opened namespace.
+
+
+A Closer Look at ``getX``
+--------------------------
+
+Methods in the Preferences library return a status code that can be used to determine if the method completed successfully. This is described in the `Preferences API Reference`_.
+
+Assume we have a key named ``favorites`` that contains a value of a ``String`` data type.
+
+After executing the statement:
+
+.. code-block:: arduino
+
+  dessert = mySketchPrefs.getString("favorites");
+
+..
+
+the variable ``dessert`` will contain the value of the string stored against the key ``"favorites"``.
+
+But what if something went wrong and the ``getString`` call failed to retrieve the key value? How would we be able to detect the error?
+
+With Preferences, the ``getX`` methods listed in Table 2 below will return a default value if an error is encountered.
+
+.. table:: **Table 2 — getX Methods Defaults**
+   :align: center
+
+   +------------------+-----------------+
+   | Preferences      | Default Return  |
+   | Type             | Value           |
+   +==================+=================+
+   | Char, UChar,     | 0               |
+   |                  |                 |
+   | Short, UShort,   |                 |
+   |                  |                 |
+   | Int, UInt,       |                 |
+   |                  |                 |
+   | Long, ULong,     |                 |
+   |                  |                 |
+   | Long64, ULong64  |                 |
+   +------------------+-----------------+
+   | Bool             | false           |
+   +------------------+-----------------+
+   | Float            | NAN             |
+   |                  |                 |
+   | Double           |                 |
+   +------------------+-----------------+
+   | String (String)  | ""              |
+   +------------------+-----------------+
+   | String (* buf)   | \\0             |
+   +------------------+-----------------+
+
+Thus to detect an error we could compare the value returned against its default return value and if they are equal assume an error occurred and take the appropriate action.
+
+But what if a method default return value is also a potential legitimate value? How can we then know if an error occurred?
+
+As it turns out, the complete form of the ``getX`` methods for each of the Preferences Types in Table 2 is:
+
+.. code-block:: arduino
+
+   preferences.getX("myKey", myDefault)
+
+..
+
+In this form the method will return either the value associated with "``myKey``" or, if an error occurred, return the value ``myDefault``, where ``myDefault`` must be the same data type as the ``getX``.
+
+Returning to the example above:
+
+.. code-block:: arduino
+
+  dessert = mySketchPrefs.getString("favorites", "gravel");
+
+..
+
+will assign to the variable ``dessert`` the String ``gravel`` if an error occurred, or the value stored against the key ``favorites`` if not.
+
+If we predetermine a default value that is outside all legitimate values, we now have a way to test if an error actually occurred.
+
+In summary, if you need to confirm that a value was retrieved without error from a namespace, use the complete form of the ``getX`` method with a predetermined default "this can only happen if an error" value and compare that against the value returned by the call. Otherwise, you can omit the default value as the call will return the default for that particular ``getX`` method.
+
+Additional detail is given in the `Preferences API Reference`_.
+
+
+Advanced Item
+-------------
+
+In the arduino-esp32 implementation of Preferences there is no method to completely remove a namespace. As a result, over the course of a number of projects, it is possible that the ESP32 NVS Preferences partition becomes cluttered or full.
+
+To completely erase and reformat the NVS memory used by Preferences, create and run a sketch that contains:
+
+.. code-block:: arduino
+
+   #include <nvs_flash.h>
+
+   void setup() {
+
+       nvs_flash_erase();      // erase the NVS partition and...
+       nvs_flash_init();       // initialize the NVS partition.
+       while (true);
+
+   }
+
+   void loop() {
+      ;
+   }
+
+..
+
+.. warning::
+   **You should download a new sketch to your board immediately after running the above or else it will reformat the NVS partition every time it is powered up or restarted!**
+
+
+Resources
+---------
+
+* `Preferences API Reference <../api/preferences.html>`_
+* `Non-volatile storage library`_ (espressif-IDF API Reference)
+* `Official ESP-IDF documentation`_ (espressif-IDF Reference)
+
+
+.. _Non-volatile storage library: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-reference/storage/nvs_flash.html
+.. _Official ESP-IDF documentation: https://docs.espressif.com/projects/esp-idf/en/stable
+
+
+Contribute
+----------
+
+.. ==*Do not change! Keep as is.*==
+
+To contribute to this project, see `How to contribute`_.
+
+If you have any **feedback** or **issue** to report on this tutorial, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else.
+
+.. _How to Contribute: https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst
+
+.. ---- EOF ----
diff --git a/docs/en/tutorials/tutorials.rst b/docs/en/tutorials/tutorials.rst
new file mode 100644
index 00000000000..9fca4ac3ce5
--- /dev/null
+++ b/docs/en/tutorials/tutorials.rst
@@ -0,0 +1,10 @@
+#########
+Tutorials
+#########
+
+.. toctree::
+    :caption: Tutorials:
+    :maxdepth: 1
+    :glob:
+
+    *
diff --git a/docs/esp-idf_component.md b/docs/esp-idf_component.md
deleted file mode 100644
index 7fd4225d83c..00000000000
--- a/docs/esp-idf_component.md
+++ /dev/null
@@ -1,82 +0,0 @@
-To use as a component of ESP-IDF
-=================================================
-
-## esp32-arduino-lib-builder
-
-For a simplified method, see [lib-builder](lib_builder.md)
-
-## Installation
-
-- Download and install [esp-idf](https://github.com/espressif/esp-idf)
-- Create blank idf project (from one of the examples)
-- in the project folder, create a folder called components and clone this repository inside
-
-    ```bash
-    mkdir -p components && \
-    cd components && \
-    git clone https://github.com/espressif/arduino-esp32.git arduino && \
-    cd arduino && \
-    git submodule update --init --recursive && \
-    cd ../.. && \
-    make menuconfig
-  ```
-- ```make menuconfig``` has some Arduino options
-    - "Autostart Arduino setup and loop on boot"
-        - If you enable this options, your main.cpp should be formated like any other sketch
-
-          ```arduino
-          //file: main.cpp
-          #include "Arduino.h"
-
-          void setup(){
-            Serial.begin(115200);
-          }
-
-          void loop(){
-            Serial.println("loop");
-            delay(1000);
-          }
-          ```
-
-        - Else you need to implement ```app_main()``` and call ```initArduino();``` in it.
-
-          Keep in mind that setup() and loop() will not be called in this case.
-          If you plan to base your code on examples provided in [esp-idf](https://github.com/espressif/esp-idf/tree/master/examples), please make sure move the app_main() function in main.cpp from the files in the example.
-
-          ```arduino
-          //file: main.cpp
-          #include "Arduino.h"
-
-          extern "C" void app_main()
-          {
-              initArduino();
-              pinMode(4, OUTPUT);
-              digitalWrite(4, HIGH);
-              //do your own thing
-          }
-          ```
-    - "Disable mutex locks for HAL"
-        - If enabled, there will be no protection on the drivers from concurently accessing them from another thread/interrupt/core
-    - "Autoconnect WiFi on boot"
-        - If enabled, WiFi will start with the last known configuration
-        - Else it will wait for WiFi.begin
-- ```make flash monitor``` will build, upload and open serial monitor to your board
-
-## Logging To Serial
-
-If you are writing code that does not require Arduino to compile and you want your `ESP_LOGx` macros to work in Arduino IDE, you can enable the compatibility by adding the following lines after your includes:
-
-```cpp
-#ifdef ARDUINO_ARCH_ESP32
-#include "esp32-hal-log.h"
-#endif
-```
-
-## FreeRTOS Tick Rate (Hz)
-
-You might notice that Arduino-esp32's `delay()` function will only work in multiples of 10ms. That is because, by default, esp-idf handles task events 100 times per second.
-To fix that behavior you need to set FreeRTOS tick rate to 1000Hz in `make menuconfig` -> `Component config` -> `FreeRTOS` -> `Tick rate`.
-
-## Compilation Errors
-
-As commits are made to esp-idf and submodules, the codebases can develop incompatibilities which cause compilation errors.  If you have problems compiling, follow the instructions in [Issue #1142](https://github.com/espressif/arduino-esp32/issues/1142) to roll esp-idf back to a known good version.
diff --git a/docs/esp32_pinmap.png b/docs/esp32_pinmap.png
deleted file mode 100644
index 2c46148f330..00000000000
Binary files a/docs/esp32_pinmap.png and /dev/null differ
diff --git a/docs/lib_builder.md b/docs/lib_builder.md
deleted file mode 100644
index 66cca92206a..00000000000
--- a/docs/lib_builder.md
+++ /dev/null
@@ -1,14 +0,0 @@
-## Using esp32-arduino-lib-builder to compile custom libraries
-
-Espressif has provided a [tool](https://github.com/espressif/esp32-arduino-lib-builder) to simplify building your own compiled libraries for use in Arduino IDE (or your favorite IDE).
-To use it to generate custom libraries, follow these steps:
-1. `git clone https://github.com/espressif/esp32-arduino-lib-builder`
-2. `cd esp32-arduino-lib-builder`
-3. `./tools/update-components.sh`
-4. `./tools/install-esp-idf.sh` (if you already have an $IDF_PATH defined, it will use your local copy of the repository)
-5. `make menuconfig` or directly edit sdkconfig.
-6. `./build.sh`
-
-The script automates the process of building [arduino as an ESP-IDF component](https://github.com/espressif/arduino-esp32/blob/master/docs/esp-idf_component.md).
-Once it is complete, you can cherry pick the needed libraries from `out/tools/sdk/lib`, or run `tools/copy-to-arduino.sh` to copy the entire built system.
-`tools/config.sh` contains a number of variables that control the process, particularly the $IDF_BRANCH variable.  You can adjust this to try building against newer versions, but there are absolutely no guarantees that any components will work or even successfully compile against a newer IDF.
diff --git a/docs/make.md b/docs/make.md
deleted file mode 100644
index 1fca5d79f9f..00000000000
--- a/docs/make.md
+++ /dev/null
@@ -1,4 +0,0 @@
-To use make
-============
-
- [makeEspArduino](https://github.com/plerup/makeEspArduino) is a generic makefile for any ESP8266/ESP32 Arduino project.Using make instead of the Arduino IDE makes it easier to do automated and production builds.
diff --git a/docs/platformio.md b/docs/platformio.md
deleted file mode 100644
index 33f4b22cba3..00000000000
--- a/docs/platformio.md
+++ /dev/null
@@ -1,11 +0,0 @@
-Installation instructions for using PlatformIO
-=================================================
-
-- [What is PlatformIO?](https://docs.platformio.org/en/latest/what-is-platformio.html?utm_source=github&utm_medium=arduino-esp32)
-- [PlatformIO IDE](https://platformio.org/platformio-ide?utm_source=github&utm_medium=arduino-esp32)
-- [PlatformIO Core](https://docs.platformio.org/en/latest/core.html?utm_source=github&utm_medium=arduino-esp32) (command line tool)
-- [Advanced usage](https://docs.platformio.org/en/latest/platforms/espressif32.html?utm_source=github&utm_medium=arduino-esp32) -
-  custom settings, uploading to SPIFFS, Over-the-Air (OTA), staging version
-- [Integration with Cloud and Standalone IDEs](https://docs.platformio.org/en/latest/ide.html?utm_source=github&utm_medium=arduino-esp32) -
-  Cloud9, Codeanywhere, Eclipse Che (Codenvy), Atom, CLion, Eclipse, Emacs, NetBeans, Qt Creator, Sublime Text, VIM, Visual Studio, and VSCode
-- [Project Examples](https://docs.platformio.org/en/latest/platforms/espressif32.html?utm_source=github&utm_medium=arduino-esp32#examples)
diff --git a/docs/requirements.txt b/docs/requirements.txt
new file mode 100644
index 00000000000..d3017fb5adc
--- /dev/null
+++ b/docs/requirements.txt
@@ -0,0 +1,5 @@
+esp-docs>=1.4.0
+sphinx-copybutton==0.5.0
+sphinx-tabs==3.2.0
+numpydoc==1.5.0
+standard-imghdr==3.13.0
diff --git a/docs/utils.sh b/docs/utils.sh
new file mode 100644
index 00000000000..3a860ac8a2c
--- /dev/null
+++ b/docs/utils.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+# Bash helper functions for adding SSH keys
+
+function add_ssh_keys {
+    local key_string="${1}"
+    mkdir -p ~/.ssh
+    chmod 700 ~/.ssh
+    echo -n "${key_string}" >~/.ssh/id_rsa_base64
+    base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 >~/.ssh/id_rsa
+    chmod 600 ~/.ssh/id_rsa
+}
+
+function add_doc_server_ssh_keys {
+    local key_string="${1}"
+    local server_url="${2}"
+    local server_user="${3}"
+    add_ssh_keys "${key_string}"
+    echo -e "Host ${server_url}\n\tStrictHostKeyChecking no\n\tUser ${server_user}\n" >>~/.ssh/config
+}
diff --git a/idf_component.yml b/idf_component.yml
new file mode 100644
index 00000000000..967c4ecf0f6
--- /dev/null
+++ b/idf_component.yml
@@ -0,0 +1,127 @@
+description: "Arduino core for ESP32, ESP32-S and ESP32-C series of SoCs"
+url: "https://github.com/espressif/arduino-esp32"
+license: "LGPL-2.1"
+targets:
+  - esp32
+  - esp32s2
+  - esp32s3
+  - esp32c2
+  - esp32c3
+  - esp32c6
+  - esp32h2
+  - esp32p4
+tags:
+  - arduino
+files:
+  include:
+    - "variants/esp32/**/*"
+    - "variants/esp32s2/**/*"
+    - "variants/esp32s3/**/*"
+    - "variants/esp32c2/**/*"
+    - "variants/esp32c3/**/*"
+    - "variants/esp32c6/**/*"
+    - "variants/esp32h2/**/*"
+    - "variants/esp32p4/**/*"
+  exclude:
+    - "docs/"
+    - "docs/**/*"
+    - "idf_component_examples/"
+    - "idf_component_examples/**/*"
+    - "package/"
+    - "package/**/*"
+    - "tests/"
+    - "tests/**/*"
+    - "tools/"
+    - "tools/**/*"
+    - "variants/**/*"
+    - ".gitignore"
+    - ".gitmodules"
+    - ".readthedocs.yaml"
+    - "boards.txt"
+    - "CODE_OF_CONDUCT.md"
+    - "LICENSE.md"
+    - "package.json"
+    - "platform.txt"
+    - "programmers.txt"
+dependencies:
+  idf: ">=5.3,<5.5"
+  # mdns 1.2.1 is necessary to build H2 with no WiFi
+  espressif/mdns:
+    version: "^1.2.3"
+    require: public
+  espressif/esp_modem:
+    version: "^1.1.0"
+  espressif/esp-zboss-lib:
+    version: "==1.6.3"
+    require: public
+    rules:
+      - if: "target not in [esp32c2, esp32p4]"
+  espressif/esp-zigbee-lib:
+    version: "==1.6.3"
+    require: public
+    rules:
+      - if: "target not in [esp32c2, esp32p4]"
+  espressif/esp-dsp:
+    version: "^1.3.4"
+    rules:
+      - if: "target != esp32c2"
+  # RainMaker Start (Fixed versions, because Matter supports only Insights 1.0.1)
+  espressif/network_provisioning:
+    version: "1.0.2"
+  espressif/esp_rainmaker:
+    version: "1.5.2"
+    rules:
+      - if: "target not in [esp32c2, esp32p4]"
+  espressif/rmaker_common:
+    version: "1.4.6"
+    rules:
+      - if: "target not in [esp32c2, esp32p4]"
+  espressif/esp_insights:
+    version: "1.2.2"
+    rules:
+      - if: "target not in [esp32c2, esp32p4]"
+  # New version breaks esp_insights 1.0.1
+  espressif/esp_diag_data_store:
+    version: "1.0.2"
+    rules:
+      - if: "target not in [esp32c2, esp32p4]"
+  espressif/esp_diagnostics:
+    version: "1.2.1"
+    rules:
+      - if: "target not in [esp32c2, esp32p4]"
+  espressif/cbor:
+    version: "0.6.0~1"
+    rules:
+      - if: "target not in [esp32c2, esp32p4]"
+  espressif/qrcode:
+    version: "0.1.0~2"
+    rules:
+      - if: "target not in [esp32c2, esp32p4]"
+  # RainMaker End
+  espressif/esp-sr:
+    version: "^1.4.2"
+    rules:
+      - if: "target in [esp32s3]"
+  espressif/esp_hosted:
+    version: "^0.0.25"
+    rules:
+      - if: "target == esp32p4"
+  espressif/esp_wifi_remote:
+    version: "^0.4.1"
+    rules:
+      - if: "target == esp32p4"
+  espressif/libsodium:
+    version: "^1.0.20~1"
+    require: public
+  espressif/esp-modbus:
+    version: "^1.0.15"
+    require: public
+  joltwallet/littlefs:
+    version: "^1.10.2"
+  chmorgan/esp-libhelix-mp3:
+    version: "1.0.3"
+    require: public
+examples:
+  - path: ./idf_component_examples/hello_world
+  - path: ./idf_component_examples/hw_cdc_hello_world
+  - path: ./idf_component_examples/esp_matter_light
diff --git a/idf_component_examples/esp_matter_light/CMakeLists.txt b/idf_component_examples/esp_matter_light/CMakeLists.txt
new file mode 100644
index 00000000000..16a7533f2a5
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/CMakeLists.txt
@@ -0,0 +1,27 @@
+# The following lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.5)
+
+set(PROJECT_VER "1.0")
+set(PROJECT_VER_NUMBER 1)
+
+# This should be done before using the IDF_TARGET variable.
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+project(arduino_managed_component_light)
+
+# WARNING: This is just an example for using key for decrypting the encrypted OTA image
+# Please do not use it as is.
+if(CONFIG_ENABLE_ENCRYPTED_OTA)
+    target_add_binary_data(light.elf "esp_image_encryption_key.pem" TEXT)
+endif()
+
+if(CONFIG_IDF_TARGET_ESP32C2)
+    include(relinker)
+endif()
+
+idf_build_set_property(CXX_COMPILE_OPTIONS "-std=gnu++17;-Os;-DCHIP_HAVE_CONFIG_H" APPEND)
+idf_build_set_property(C_COMPILE_OPTIONS "-Os" APPEND)
+# For RISCV chips, project_include.cmake sets -Wno-format, but does not clear various
+# flags that depend on -Wformat
+idf_build_set_property(COMPILE_OPTIONS "-Wno-format-nonliteral;-Wno-format-security" APPEND)
diff --git a/idf_component_examples/esp_matter_light/README.md b/idf_component_examples/esp_matter_light/README.md
new file mode 100644
index 00000000000..06a22cdceac
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/README.md
@@ -0,0 +1,113 @@
+| Supported Targets | ESP32-S3 | ESP32-C3 | ESP32-C6 |
+| ----------------- | -------- | -------- | -------- |
+
+
+# Managed Component Light
+
+This example sets automatically the RGB LED GPIO and BOOT Button GPIO based on the default pin used by the selected Devkit Board.
+
+This example creates a Color Temperature Light device using the esp_matter component downloaded from the [Espressif Component Registry](https://components.espressif.com/) instead of an extra component locally, so the example can work without setting up the esp-matter environment.
+
+Read the [documentation](https://docs.espressif.com/projects/esp-matter/en/latest/esp32/developing.html) for more information about building and flashing the firmware.
+
+The code is based on the Arduino API and uses Arduino as an IDF Component.
+
+## How to use it
+
+Once the device runs for the first time, it must be commissioned to the Matter Fabric of the available Matter Environment.  
+Possible Matter Environments are:  
+- Amazon Alexa
+- Google Home Assistant (*)
+- Apple Home
+- Open Source Home Assistant
+
+(*) Google Home Assistant requires the user to set up a Matter Light using the [Google Home Developer Console](https://developers.home.google.com/codelabs/matter-device#2). It is necessary to create a Matter Light device with VID = 0xFFF1 and PID = 0x8000. Otherwise, the Light won't show up in the GHA APP. This action is necessary because the Firmware uses Testing credentials and Google requires the user to create the testing device before using it.
+
+**There is no QR Code** to be used when the Smartphone APP wants to add the Matter Device.  
+Please enter the code manually: `34970112332`
+
+Each Devkit Board has a built-in LED that will be used as the Matter Light.  
+The default setting for ESP32-S3 is pin 48, for ESP32-C3 and ESP32-C6, it is pin 8.  
+The BOOT Button pin of ESP32-S3 is GPIO 0, by toher hand, the ESP32-C3 and ESP32-C6 use GPIO 9.  
+Please change it in using the MenuConfig executing `idf.py menuconfig` and selecting `Menu->Light Matter Accessory` options.
+
+## LED Status and Factory Mode
+
+The WS2812b built-in LED will turn purple as soon as the device is flashed and runs for the first time.  
+The purple color indicates that the Matter Accessory has not been commissioned yet.  
+After using a Matter provider Smartphone APP to add a Matter device to your Home Application, it may turn orange to indicate that it has no Wi-Fi connection.
+
+Once it connects to the Wi-Fi network, the LED will turn white to indicate that Matter is working and the device is connected to the Matter Environment.
+Please note that Matter over Wi-Fi using an ESP32 device will connect to a 2.4 GHz Wi-Fi SSID, therefore the Commissioner APP Smartphone shall be connected to this SSID.
+
+The Matter and Wi-Fi configuration will be stored in NVS to ensure that it will connect to the Matter Fabric and Wi-Fi Network again once it is reset.
+
+The Matter Smartphone APP will control the light state (ON/OFF), temperature (Warm/Cold White), and brightness.
+
+## On Board Light toggle button
+
+The built-in BOOT button will toggle On/Off and replicate the new state to the Matter Environment, making it visible in the Matter Smartphone APP as well.
+
+## Returning to the Factory State
+
+Holding the BOOT button pressed for more than 10 seconds and then releasing it will erase all Matter and Wi-Fi configuration, forcing it to reset to factory state. After that, the device needs to be commissioned again.  
+Previous setups done in the Smartphone APP won't work again; therefore, the virtual device shall be removed from the APP.
+
+## Building the Application using Wi-Fi and Matter
+
+Use ESP-IDF 5.1.4 from https://github.com/espressif/esp-idf/tree/release/v5.1  
+This example has been tested with Arduino Core 3.0.4
+
+The project will download all necessary components, including the Arduino Core.  
+Run `idf.py -D SDKCONFIG_DEFAULTS="sdkconfig.defaults.<SOC>.idf" -p <PORT> flash monitor`
+
+Example for ESP32-S3/Linux | macOS:  
+```
+idf.py -D SDKCONFIG_DEFAULTS="sdkconfig.defaults.esp32s3" -p /dev/ttyACM0 flash monitor
+```
+Example for ESP32-C3/Windows:  
+```
+idf.py -D SDKCONFIG_DEFAULTS="sdkconfig.defaults.esp32c3" -p com3 flash monitor
+```
+
+It may be necessary to delete some folders and files  before running `idf.py`  
+- Linux/macOS:
+  ```
+  rm -rf build managed_components sdkconfig dependencies.lock
+  ```  
+- Windows:
+  ```
+  rmdir /s/q build managed_components && del sdkconfig dependencies.lock
+  ```
+
+There is a configuration file for these SoC: esp32s3, esp32c3, esp32c6.
+Those are the tested devices that have a WS2812 RGB LED and can run BLE, Wi-Fi and Matter.
+
+In case it is necessary to change the Button Pin or the REG LED Pin, please use the `menuconfig`
+`idf.py menuconfig` and change the Menu Option `Light Matter Accessory`
+
+## Building the Application using OpenThread and Matter
+
+This is possible with the ESP32-C6.
+It is necessary to have a Thread Border Router in the Matter Environment.  
+Check your Matter hardware provider.  
+In order to build the application that will use Thread Networking instead of Wi-Fi, please execute:
+
+Example for ESP32-C6/Linux | macOS:  
+```
+idf.py -D SDKCONFIG_DEFAULTS="sdkconfig.defaults.c6_thread" -p /dev/ttyACM0 flash monitor
+```
+Example for ESP32-C6/Windows:  
+```
+idf.py -D SDKCONFIG_DEFAULTS="sdkconfig.defaults.c6_thread" -p com3 flash monitor
+```
+
+It may be necessary to delete some folders and files before running `idf.py`  
+- Linux/macOS
+  ```
+  rm -rf build managed_components sdkconfig dependencies.lock
+  ```  
+- Windows
+  ```
+  rmdir /s/q build managed_components && del sdkconfig dependencies.lock
+  ```
diff --git a/idf_component_examples/esp_matter_light/main/CMakeLists.txt b/idf_component_examples/esp_matter_light/main/CMakeLists.txt
new file mode 100644
index 00000000000..6b91a8cf510
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/main/CMakeLists.txt
@@ -0,0 +1,5 @@
+idf_component_register(SRC_DIRS          "."
+                       INCLUDE_DIRS      ".")
+
+set_property(TARGET ${COMPONENT_LIB} PROPERTY CXX_STANDARD 17)
+target_compile_options(${COMPONENT_LIB} PRIVATE "-DCHIP_HAVE_CONFIG_H")
diff --git a/idf_component_examples/esp_matter_light/main/Kconfig.projbuild b/idf_component_examples/esp_matter_light/main/Kconfig.projbuild
new file mode 100644
index 00000000000..6e6abcb7fcf
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/main/Kconfig.projbuild
@@ -0,0 +1,102 @@
+menu "Light Matter Accessory"
+    menu "On Board Light ON/OFF Button"
+        config BUTTON_PIN
+            int
+            prompt "Button 1 GPIO"
+            default ENV_GPIO_BOOT_BUTTON
+            range -1 ENV_GPIO_IN_RANGE_MAX
+            help
+                The GPIO pin for button that will be used to turn on/off the Matter Light. It shall be connected to a push button. It can use the BOOT button of the development board.
+    endmenu
+
+
+    menu "LEDs"
+        config WS2812_PIN
+            int
+            prompt "WS2812 RGB LED GPIO"
+            default ENV_GPIO_RGB_LED
+            range -1 ENV_GPIO_OUT_RANGE_MAX
+            help
+                The GPIO pin for the Matter Light that will be driven by RMT. It shall be connected to one single WS2812 RGB LED.
+    endmenu
+
+    # TARGET CONFIGURATION
+    if IDF_TARGET_ESP32C3
+        config ENV_GPIO_RANGE_MIN
+            int
+            default 0
+
+        config ENV_GPIO_RANGE_MAX
+            int
+            default 19
+            # GPIOs 20/21 are always used by UART in examples
+
+        config ENV_GPIO_IN_RANGE_MAX
+            int
+            default ENV_GPIO_RANGE_MAX
+
+        config ENV_GPIO_OUT_RANGE_MAX
+            int
+            default ENV_GPIO_RANGE_MAX
+
+        config ENV_GPIO_BOOT_BUTTON
+            int
+            default 9
+
+        config ENV_GPIO_RGB_LED
+            int
+            default 8
+    endif
+    if IDF_TARGET_ESP32C6
+        config ENV_GPIO_RANGE_MIN
+            int
+            default 0
+
+        config ENV_GPIO_RANGE_MAX
+            int
+            default 30
+            # GPIOs 16/17 are always used by UART in examples
+
+        config ENV_GPIO_IN_RANGE_MAX
+            int
+            default ENV_GPIO_RANGE_MAX
+
+        config ENV_GPIO_OUT_RANGE_MAX
+            int
+            default ENV_GPIO_RANGE_MAX
+
+        config ENV_GPIO_BOOT_BUTTON
+            int
+            default 9
+
+        config ENV_GPIO_RGB_LED
+            int
+            default 8
+    endif
+    if IDF_TARGET_ESP32S3
+        config ENV_GPIO_RANGE_MIN
+            int
+            default 0
+
+        config ENV_GPIO_RANGE_MAX
+            int
+            default 48
+
+        config ENV_GPIO_IN_RANGE_MAX
+            int
+            default ENV_GPIO_RANGE_MAX
+
+        config ENV_GPIO_OUT_RANGE_MAX
+            int
+            default ENV_GPIO_RANGE_MAX
+
+        config ENV_GPIO_BOOT_BUTTON
+            int
+            default 0
+
+        config ENV_GPIO_RGB_LED
+            int
+            default 48
+    endif
+
+endmenu
diff --git a/idf_component_examples/esp_matter_light/main/builtinLED.cpp b/idf_component_examples/esp_matter_light/main/builtinLED.cpp
new file mode 100644
index 00000000000..8795dde2756
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/main/builtinLED.cpp
@@ -0,0 +1,237 @@
+/*
+    This example code is in the Public Domain (or CC0 licensed, at your option.)
+    Unless required by applicable law or agreed to in writing, this
+    software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+    CONDITIONS OF ANY KIND, either express or implied.
+        This will implement the onboard WS2812b LED as a LED indicator
+        It can be used to indicate some state or status of the device
+        The LED can be controlled using RGB, HSV or color temperature, brightness
+
+        In this example, the LED Indicator class is used as the Matter light accessory
+*/
+
+#include "builtinLED.h"
+
+typedef struct {
+  uint16_t hue;
+  uint8_t saturation;
+} HS_color_t;
+
+static const HS_color_t temperatureTable[] = {
+  {4, 100},  {8, 100},  {11, 100}, {14, 100}, {16, 100}, {18, 100}, {20, 100}, {22, 100}, {24, 100}, {25, 100}, {27, 100}, {28, 100}, {30, 100}, {31, 100},
+  {31, 95},  {30, 89},  {30, 85},  {29, 80},  {29, 76},  {29, 73},  {29, 69},  {28, 66},  {28, 63},  {28, 60},  {28, 57},  {28, 54},  {28, 52},  {27, 49},
+  {27, 47},  {27, 45},  {27, 43},  {27, 41},  {27, 39},  {27, 37},  {27, 35},  {27, 33},  {27, 31},  {27, 30},  {27, 28},  {27, 26},  {27, 25},  {27, 23},
+  {27, 22},  {27, 21},  {27, 19},  {27, 18},  {27, 17},  {27, 15},  {28, 14},  {28, 13},  {28, 12},  {29, 10},  {29, 9},   {30, 8},   {31, 7},   {32, 6},
+  {34, 5},   {36, 4},   {41, 3},   {49, 2},   {0, 0},    {294, 2},  {265, 3},  {251, 4},  {242, 5},  {237, 6},  {233, 7},  {231, 8},  {229, 9},  {228, 10},
+  {227, 11}, {226, 11}, {226, 12}, {225, 13}, {225, 13}, {224, 14}, {224, 14}, {224, 15}, {224, 15}, {223, 16}, {223, 16}, {223, 17}, {223, 17}, {223, 17},
+  {222, 18}, {222, 18}, {222, 19}, {222, 19}, {222, 19}, {222, 19}, {222, 20}, {222, 20}, {222, 20}, {222, 21}, {222, 21}
+};
+
+/* step brightness table: gamma = 2.3 */
+static const uint8_t gamma_table[MAX_PROGRESS] = {
+  0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   0,   1,   1,   1,   1,   1,   1,
+  1,   1,   2,   2,   2,   2,   2,   2,   3,   3,   3,   3,   3,   4,   4,   4,   4,   4,   5,   5,   5,   6,   6,   6,   6,   7,   7,   7,   8,
+  8,   8,   9,   9,   9,   10,  10,  10,  11,  11,  12,  12,  13,  13,  13,  14,  14,  15,  15,  16,  16,  17,  17,  18,  18,  19,  19,  20,  20,
+  21,  22,  22,  23,  23,  24,  25,  25,  26,  26,  27,  28,  28,  29,  30,  30,  31,  32,  33,  33,  34,  35,  36,  36,  37,  38,  39,  40,  40,
+  41,  42,  43,  44,  45,  45,  46,  47,  48,  49,  50,  51,  52,  53,  54,  55,  56,  57,  58,  59,  60,  61,  62,  63,  64,  65,  66,  67,  68,
+  69,  70,  71,  72,  74,  75,  76,  77,  78,  79,  81,  82,  83,  84,  86,  87,  88,  89,  91,  92,  93,  95,  96,  97,  99,  100, 101, 103, 104,
+  105, 107, 108, 110, 111, 112, 114, 115, 117, 118, 120, 121, 123, 124, 126, 128, 129, 131, 132, 134, 135, 137, 139, 140, 142, 144, 145, 147, 149,
+  150, 152, 154, 156, 157, 159, 161, 163, 164, 166, 168, 170, 172, 174, 175, 177, 179, 181, 183, 185, 187, 189, 191, 193, 195, 197, 199, 201, 203,
+  205, 207, 209, 211, 213, 215, 217, 219, 221, 223, 226, 228, 230, 232, 234, 236, 239, 241, 243, 245, 248, 250, 252, 255,
+};
+
+BuiltInLED::BuiltInLED() {
+  pin_number = (uint8_t)-1;  // no pin number
+  state = false;             // LED is off
+  hsv_color.value = 0;       // black color
+}
+
+BuiltInLED::~BuiltInLED() {
+  end();
+}
+
+led_indicator_color_hsv_t BuiltInLED::rgb2hsv(led_indicator_color_rgb_t rgb) {
+  led_indicator_color_hsv_t hsv;
+  uint8_t minRGB, maxRGB;
+  uint8_t delta;
+
+  minRGB = rgb.r < rgb.g ? (rgb.r < rgb.b ? rgb.r : rgb.b) : (rgb.g < rgb.b ? rgb.g : rgb.b);
+  maxRGB = rgb.r > rgb.g ? (rgb.r > rgb.b ? rgb.r : rgb.b) : (rgb.g > rgb.b ? rgb.g : rgb.b);
+  hsv.value = 0;
+  hsv.v = maxRGB;
+  delta = maxRGB - minRGB;
+
+  if (delta == 0) {
+    hsv.h = 0;
+    hsv.s = 0;
+  } else {
+    hsv.s = delta * 255 / maxRGB;
+
+    if (rgb.r == maxRGB) {
+      hsv.h = (60 * (rgb.g - rgb.b) / delta + 360) % 360;
+    } else if (rgb.g == maxRGB) {
+      hsv.h = (60 * (rgb.b - rgb.r) / delta + 120);
+    } else {
+      hsv.h = (60 * (rgb.r - rgb.g) / delta + 240);
+    }
+  }
+  return hsv;
+}
+
+led_indicator_color_rgb_t BuiltInLED::hsv2rgb(led_indicator_color_hsv_t hsv) {
+  led_indicator_color_rgb_t rgb;
+  uint8_t rgb_max = hsv.v;
+  uint8_t rgb_min = rgb_max * (255 - hsv.s) / 255.0f;
+
+  uint8_t i = hsv.h / 60;
+  uint8_t diff = hsv.h % 60;
+
+  // RGB adjustment amount by hue
+  uint8_t rgb_adj = (rgb_max - rgb_min) * diff / 60;
+  rgb.value = 0;
+  switch (i) {
+    case 0:
+      rgb.r = rgb_max;
+      rgb.g = rgb_min + rgb_adj;
+      rgb.b = rgb_min;
+      break;
+    case 1:
+      rgb.r = rgb_max - rgb_adj;
+      rgb.g = rgb_max;
+      rgb.b = rgb_min;
+      break;
+    case 2:
+      rgb.r = rgb_min;
+      rgb.g = rgb_max;
+      rgb.b = rgb_min + rgb_adj;
+      break;
+    case 3:
+      rgb.r = rgb_min;
+      rgb.g = rgb_max - rgb_adj;
+      rgb.b = rgb_max;
+      break;
+    case 4:
+      rgb.r = rgb_min + rgb_adj;
+      rgb.g = rgb_min;
+      rgb.b = rgb_max;
+      break;
+    default:
+      rgb.r = rgb_max;
+      rgb.g = rgb_min;
+      rgb.b = rgb_max - rgb_adj;
+      break;
+  }
+
+  // gamma correction
+  rgb.r = gamma_table[rgb.r];
+  rgb.g = gamma_table[rgb.g];
+  rgb.b = gamma_table[rgb.b];
+  return rgb;
+}
+
+void BuiltInLED::begin(uint8_t pin) {
+  if (pin < NUM_DIGITAL_PINS) {
+    pin_number = pin;
+    log_i("Initializing pin %d", pin);
+  } else {
+    log_e("Invalid pin (%d) number", pin);
+  }
+}
+void BuiltInLED::end() {
+  state = false;
+  write();  // turn off the LED
+  if (pin_number < NUM_DIGITAL_PINS) {
+    if (!rmtDeinit(pin_number)) {
+      log_e("Failed to deinitialize RMT");
+    }
+  }
+}
+
+void BuiltInLED::on() {
+  state = true;
+}
+
+void BuiltInLED::off() {
+  state = false;
+}
+
+void BuiltInLED::toggle() {
+  state = !state;
+}
+
+bool BuiltInLED::getState() {
+  return state;
+}
+
+bool BuiltInLED::write() {
+  led_indicator_color_rgb_t rgb_color = getRGB();
+  log_d("Writing to pin %d with state = %s", pin_number, state ? "ON" : "OFF");
+  log_d("HSV: %d, %d, %d", hsv_color.h, hsv_color.s, hsv_color.v);
+  log_d("RGB: %d, %d, %d", rgb_color.r, rgb_color.g, rgb_color.b);
+  if (pin_number < NUM_DIGITAL_PINS) {
+    if (state) {
+      rgbLedWrite(pin_number, rgb_color.r, rgb_color.g, rgb_color.b);
+    } else {
+      rgbLedWrite(pin_number, 0, 0, 0);
+    }
+    return true;
+  } else {
+    log_e("Invalid pin (%d) number", pin_number);
+    return false;
+  }
+}
+
+void BuiltInLED::setBrightness(uint8_t brightness) {
+  hsv_color.v = brightness;
+}
+
+uint8_t BuiltInLED::getBrightness() {
+  return hsv_color.v;
+}
+
+void BuiltInLED::setHSV(led_indicator_color_hsv_t hsv) {
+  if (hsv.h > MAX_HUE) {
+    hsv.h = MAX_HUE;
+  }
+  hsv_color.value = hsv.value;
+}
+
+led_indicator_color_hsv_t BuiltInLED::getHSV() {
+  return hsv_color;
+}
+
+void BuiltInLED::setRGB(led_indicator_color_rgb_t rgb_color) {
+  hsv_color = rgb2hsv(rgb_color);
+}
+
+led_indicator_color_rgb_t BuiltInLED::getRGB() {
+  return hsv2rgb(hsv_color);
+}
+
+void BuiltInLED::setTemperature(uint32_t temperature) {
+  uint16_t hue;
+  uint8_t saturation;
+
+  log_d("Requested Temperature: %ld", temperature);
+  //hsv_color.v = gamma_table[((temperature >> 25) & 0x7F)];
+  temperature &= 0xFFFFFF;
+  if (temperature < 600) {
+    hue = 0;
+    saturation = 100;
+  } else {
+    if (temperature > 10000) {
+      hue = 222;
+      saturation = 21 + (temperature - 10000) * 41 / 990000;
+    } else {
+      temperature -= 600;
+      temperature /= 100;
+      hue = temperatureTable[temperature].hue;
+      saturation = temperatureTable[temperature].saturation;
+    }
+  }
+  saturation = (saturation * 255) / 100;
+  // brightness is not changed
+  hsv_color.h = hue;
+  hsv_color.s = saturation;
+  log_d("Calculated Temperature: %ld, Hue: %d, Saturation: %d, Brightness: %d", temperature, hue, saturation, hsv_color.v);
+}
diff --git a/idf_component_examples/esp_matter_light/main/builtinLED.h b/idf_component_examples/esp_matter_light/main/builtinLED.h
new file mode 100644
index 00000000000..1ca8c935569
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/main/builtinLED.h
@@ -0,0 +1,74 @@
+/*
+    This example code is in the Public Domain (or CC0 licensed, at your option.)
+    Unless required by applicable law or agreed to in writing, this
+    software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+    CONDITIONS OF ANY KIND, either express or implied.
+        This will implement the onboard WS2812b LED as a LED indicator
+        It can be used to indicate some state or status of the device
+        The LED can be controlled using RGB, HSV or color temperature, brightness
+
+        In this example, the BuiltInLED class is used as the Matter light accessory
+*/
+
+#pragma once
+
+#include <Arduino.h>
+
+#define MAX_HUE        360
+#define MAX_SATURATION 255
+#define MAX_BRIGHTNESS 255
+#define MAX_PROGRESS   256
+
+typedef struct {
+  union {
+    struct {
+      uint32_t v : 8; /*!< Brightness/Value of the LED. 0-255 */
+      uint32_t s : 8; /*!< Saturation of the LED. 0-255 */
+      uint32_t h : 9; /*!< Hue of the LED. 0-360 */
+    };
+    uint32_t value; /*!< IHSV value of the LED. */
+  };
+} led_indicator_color_hsv_t;
+
+typedef struct {
+  union {
+    struct {
+      uint32_t r : 8; /*!< Red component of the LED color. Range: 0-255. */
+      uint32_t g : 8; /*!< Green component of the LED color. Range: 0-255. */
+      uint32_t b : 8; /*!< Blue component of the LED color. Range: 0-255. */
+    };
+    uint32_t value; /*!< Combined RGB value of the LED color. */
+  };
+} led_indicator_color_rgb_t;
+
+class BuiltInLED {
+private:
+  uint8_t pin_number;
+  bool state;
+  led_indicator_color_hsv_t hsv_color;
+
+public:
+  BuiltInLED();
+  ~BuiltInLED();
+
+  static led_indicator_color_hsv_t rgb2hsv(led_indicator_color_rgb_t rgb_value);
+  static led_indicator_color_rgb_t hsv2rgb(led_indicator_color_hsv_t hsv);
+
+  void begin(uint8_t pin);
+  void end();
+
+  void on();
+  void off();
+  void toggle();
+  bool getState();
+
+  bool write();
+
+  void setBrightness(uint8_t brightness);
+  uint8_t getBrightness();
+  void setHSV(led_indicator_color_hsv_t hsv);
+  led_indicator_color_hsv_t getHSV();
+  void setRGB(led_indicator_color_rgb_t color);
+  led_indicator_color_rgb_t getRGB();
+  void setTemperature(uint32_t temperature);
+};
diff --git a/idf_component_examples/esp_matter_light/main/idf_component.yml b/idf_component_examples/esp_matter_light/main/idf_component.yml
new file mode 100644
index 00000000000..2b4ae4b34a4
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/main/idf_component.yml
@@ -0,0 +1,12 @@
+dependencies:
+  espressif/esp_matter:
+    version: "^1.3.0"
+  # Adds Arduino Core from GitHub repository using main branch
+  espressif/arduino-esp32:
+    version: "^3.0.5"
+    override_path: "../../../"
+    pre_release: true
+
+    # testing - using Arduino from the repository
+    # version: "master"  # branch or commit
+    # git: https://github.com/espressif/arduino-esp32.git
diff --git a/idf_component_examples/esp_matter_light/main/matter_accessory_driver.cpp b/idf_component_examples/esp_matter_light/main/matter_accessory_driver.cpp
new file mode 100644
index 00000000000..523c38e6855
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/main/matter_accessory_driver.cpp
@@ -0,0 +1,89 @@
+/*
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+#include <Arduino.h>
+#include <esp_err.h>
+#include <esp_matter_attribute_utils.h>
+#include "builtinLED.h"
+#include "matter_accessory_driver.h"
+
+/* Do any conversions/remapping for the actual value here */
+esp_err_t light_accessory_set_power(void *led, uint8_t val) {
+  BuiltInLED *builtinLED = (BuiltInLED *)led;
+  esp_err_t err = ESP_OK;
+  if (val) {
+    builtinLED->on();
+  } else {
+    builtinLED->off();
+  }
+  if (!builtinLED->write()) {
+    err = ESP_FAIL;
+  }
+  log_i("LED set power: %d", val);
+  return err;
+}
+
+esp_err_t light_accessory_set_brightness(void *led, uint8_t val) {
+  esp_err_t err = ESP_OK;
+  BuiltInLED *builtinLED = (BuiltInLED *)led;
+  int value = REMAP_TO_RANGE(val, MATTER_BRIGHTNESS, STANDARD_BRIGHTNESS);
+
+  builtinLED->setBrightness(value);
+  if (!builtinLED->write()) {
+    err = ESP_FAIL;
+  }
+  log_i("LED set brightness: %d", value);
+  return err;
+}
+
+esp_err_t light_accessory_set_hue(void *led, uint8_t val) {
+  esp_err_t err = ESP_OK;
+  BuiltInLED *builtinLED = (BuiltInLED *)led;
+  int value = REMAP_TO_RANGE(val, MATTER_HUE, STANDARD_HUE);
+  led_indicator_color_hsv_t hsv = builtinLED->getHSV();
+  hsv.h = value;
+  builtinLED->setHSV(hsv);
+  if (!builtinLED->write()) {
+    err = ESP_FAIL;
+  }
+  log_i("LED set hue: %d", value);
+  return err;
+}
+
+esp_err_t light_accessory_set_saturation(void *led, uint8_t val) {
+  esp_err_t err = ESP_OK;
+  BuiltInLED *builtinLED = (BuiltInLED *)led;
+  int value = REMAP_TO_RANGE(val, MATTER_SATURATION, STANDARD_SATURATION);
+  led_indicator_color_hsv_t hsv = builtinLED->getHSV();
+  hsv.s = value;
+  builtinLED->setHSV(hsv);
+  if (!builtinLED->write()) {
+    err = ESP_FAIL;
+  }
+  log_i("LED set saturation: %d", value);
+  return err;
+}
+
+esp_err_t light_accessory_set_temperature(void *led, uint16_t val) {
+  esp_err_t err = ESP_OK;
+  BuiltInLED *builtinLED = (BuiltInLED *)led;
+  uint32_t value = REMAP_TO_RANGE_INVERSE(val, STANDARD_TEMPERATURE_FACTOR);
+  builtinLED->setTemperature(value);
+  if (!builtinLED->write()) {
+    err = ESP_FAIL;
+  }
+  log_i("LED set temperature: %ld", value);
+  return err;
+}
+
+app_driver_handle_t light_accessory_init() {
+  /* Initialize led */
+  static BuiltInLED builtinLED;
+
+  const uint8_t pin = WS2812_PIN;  // set your board WS2812b pin here
+  builtinLED.begin(pin);
+  return (app_driver_handle_t)&builtinLED;
+}
diff --git a/idf_component_examples/esp_matter_light/main/matter_accessory_driver.h b/idf_component_examples/esp_matter_light/main/matter_accessory_driver.h
new file mode 100644
index 00000000000..3bf6655ab16
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/main/matter_accessory_driver.h
@@ -0,0 +1,47 @@
+#include <esp_err.h>
+#include <sdkconfig.h>
+
+// set your board WS2812b pin here (e.g. 48 is the default pin for the ESP32-S3 devkit)
+#ifndef CONFIG_WS2812_PIN
+#define WS2812_PIN 48  // ESP32-S3 DevKitC built-in LED
+#else
+#define WS2812_PIN CONFIG_WS2812_PIN  // From sdkconfig.defaults.<soc>
+#endif
+
+#ifndef RGB_BUILTIN
+#define RGB_BUILTIN WS2812_PIN
+#endif
+
+// Set your board button pin here (e.g. 0 is the default pin for the ESP32-S3 devkit)
+#ifndef CONFIG_BUTTON_PIN
+#define BUTTON_PIN 0  // ESP32-S3 DevKitC built-in button
+#else
+#define BUTTON_PIN CONFIG_BUTTON_PIN  // From sdkconfig.defaults.<soc>
+#endif
+
+/** Standard max values (used for remapping attributes) */
+#define STANDARD_BRIGHTNESS         255
+#define STANDARD_HUE                360
+#define STANDARD_SATURATION         255
+#define STANDARD_TEMPERATURE_FACTOR 1000000
+
+/** Matter max values (used for remapping attributes) */
+#define MATTER_BRIGHTNESS         254
+#define MATTER_HUE                254
+#define MATTER_SATURATION         254
+#define MATTER_TEMPERATURE_FACTOR 1000000
+
+/** Default attribute values used during initialization */
+#define DEFAULT_POWER      true
+#define DEFAULT_BRIGHTNESS 64
+#define DEFAULT_HUE        128
+#define DEFAULT_SATURATION 254
+
+typedef void *app_driver_handle_t;
+
+esp_err_t light_accessory_set_power(void *led, uint8_t val);
+esp_err_t light_accessory_set_brightness(void *led, uint8_t val);
+esp_err_t light_accessory_set_hue(void *led, uint8_t val);
+esp_err_t light_accessory_set_saturation(void *led, uint8_t val);
+esp_err_t light_accessory_set_temperature(void *led, uint16_t val);
+app_driver_handle_t light_accessory_init();
diff --git a/idf_component_examples/esp_matter_light/main/matter_light.cpp b/idf_component_examples/esp_matter_light/main/matter_light.cpp
new file mode 100644
index 00000000000..6079ce46add
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/main/matter_light.cpp
@@ -0,0 +1,384 @@
+/*
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+#include <Arduino.h>
+#include "matter_accessory_driver.h"
+
+#include <esp_err.h>
+
+#include <esp_matter.h>
+#include <esp_matter_console.h>
+#include <esp_matter_ota.h>
+
+#include <app/server/CommissioningWindowManager.h>
+#include <app/server/Server.h>
+
+#if CHIP_DEVICE_CONFIG_ENABLE_THREAD
+#include <platform/ESP32/OpenthreadLauncher.h>
+#include "esp_openthread_types.h"
+
+#define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG() \
+  { .radio_mode = RADIO_MODE_NATIVE, }
+
+#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG() \
+  { .host_connection_mode = HOST_CONNECTION_MODE_NONE, }
+
+#define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG() \
+  { .storage_partition_name = "nvs", .netif_queue_size = 10, .task_queue_size = 10, }
+#endif
+
+// set your board button pin here
+const uint8_t button_gpio = BUTTON_PIN;  // GPIO BOOT Button
+
+uint16_t light_endpoint_id = 0;
+
+using namespace esp_matter;
+using namespace esp_matter::attribute;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+constexpr auto k_timeout_seconds = 300;
+
+#if CONFIG_ENABLE_ENCRYPTED_OTA
+extern const char decryption_key_start[] asm("_binary_esp_image_encryption_key_pem_start");
+extern const char decryption_key_end[] asm("_binary_esp_image_encryption_key_pem_end");
+
+static const char *s_decryption_key = decryption_key_start;
+static const uint16_t s_decryption_key_len = decryption_key_end - decryption_key_start;
+#endif  // CONFIG_ENABLE_ENCRYPTED_OTA
+
+bool isAccessoryCommissioned() {
+  return chip::Server::GetInstance().GetFabricTable().FabricCount() > 0;
+}
+
+#if CHIP_DEVICE_CONFIG_ENABLE_WIFI_STATION
+bool isWifiConnected() {
+  return chip::DeviceLayer::ConnectivityMgr().IsWiFiStationConnected();
+}
+#endif
+
+#if CHIP_DEVICE_CONFIG_ENABLE_THREAD
+bool isThreadConnected() {
+  return chip::DeviceLayer::ConnectivityMgr().IsThreadAttached();
+}
+#endif
+
+static void app_event_cb(const ChipDeviceEvent *event, intptr_t arg) {
+  switch (event->Type) {
+    case chip::DeviceLayer::DeviceEventType::kInterfaceIpAddressChanged:
+      log_i(
+        "Interface %s Address changed", event->InterfaceIpAddressChanged.Type == chip::DeviceLayer::InterfaceIpChangeType::kIpV4_Assigned ? "IPv4" : "IPV6"
+      );
+      break;
+
+    case chip::DeviceLayer::DeviceEventType::kCommissioningComplete: log_i("Commissioning complete"); break;
+
+    case chip::DeviceLayer::DeviceEventType::kFailSafeTimerExpired: log_i("Commissioning failed, fail safe timer expired"); break;
+
+    case chip::DeviceLayer::DeviceEventType::kCommissioningSessionStarted: log_i("Commissioning session started"); break;
+
+    case chip::DeviceLayer::DeviceEventType::kCommissioningSessionStopped: log_i("Commissioning session stopped"); break;
+
+    case chip::DeviceLayer::DeviceEventType::kCommissioningWindowOpened: log_i("Commissioning window opened"); break;
+
+    case chip::DeviceLayer::DeviceEventType::kCommissioningWindowClosed: log_i("Commissioning window closed"); break;
+
+    case chip::DeviceLayer::DeviceEventType::kFabricRemoved:
+    {
+      log_i("Fabric removed successfully");
+      if (chip::Server::GetInstance().GetFabricTable().FabricCount() == 0) {
+        chip::CommissioningWindowManager &commissionMgr = chip::Server::GetInstance().GetCommissioningWindowManager();
+        constexpr auto kTimeoutSeconds = chip::System::Clock::Seconds16(k_timeout_seconds);
+        if (!commissionMgr.IsCommissioningWindowOpen()) {
+          /* After removing last fabric, this example does not remove the Wi-Fi credentials
+                     * and still has IP connectivity so, only advertising on DNS-SD.
+                     */
+          CHIP_ERROR err = commissionMgr.OpenBasicCommissioningWindow(kTimeoutSeconds, chip::CommissioningWindowAdvertisement::kDnssdOnly);
+          if (err != CHIP_NO_ERROR) {
+            log_e("Failed to open commissioning window, err:%" CHIP_ERROR_FORMAT, err.Format());
+          }
+        }
+      }
+      break;
+    }
+
+    case chip::DeviceLayer::DeviceEventType::kFabricWillBeRemoved: log_i("Fabric will be removed"); break;
+
+    case chip::DeviceLayer::DeviceEventType::kFabricUpdated: log_i("Fabric is updated"); break;
+
+    case chip::DeviceLayer::DeviceEventType::kFabricCommitted: log_i("Fabric is committed"); break;
+
+    case chip::DeviceLayer::DeviceEventType::kBLEDeinitialized: log_i("BLE deinitialized and memory reclaimed"); break;
+
+    default: break;
+  }
+}
+
+esp_err_t matter_light_attribute_update(
+  app_driver_handle_t driver_handle, uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val
+) {
+  esp_err_t err = ESP_OK;
+  if (endpoint_id == light_endpoint_id) {
+    void *led = (void *)driver_handle;
+    if (cluster_id == OnOff::Id) {
+      if (attribute_id == OnOff::Attributes::OnOff::Id) {
+        err = light_accessory_set_power(led, val->val.b);
+      }
+    } else if (cluster_id == LevelControl::Id) {
+      if (attribute_id == LevelControl::Attributes::CurrentLevel::Id) {
+        err = light_accessory_set_brightness(led, val->val.u8);
+      }
+    } else if (cluster_id == ColorControl::Id) {
+      if (attribute_id == ColorControl::Attributes::CurrentHue::Id) {
+        err = light_accessory_set_hue(led, val->val.u8);
+      } else if (attribute_id == ColorControl::Attributes::CurrentSaturation::Id) {
+        err = light_accessory_set_saturation(led, val->val.u8);
+      } else if (attribute_id == ColorControl::Attributes::ColorTemperatureMireds::Id) {
+        err = light_accessory_set_temperature(led, val->val.u16);
+      }
+    }
+  }
+  return err;
+}
+
+esp_err_t matter_light_set_defaults(uint16_t endpoint_id) {
+  esp_err_t err = ESP_OK;
+
+  void *led = endpoint::get_priv_data(endpoint_id);
+  node_t *node = node::get();
+  endpoint_t *endpoint = endpoint::get(node, endpoint_id);
+  cluster_t *cluster = NULL;
+  attribute_t *attribute = NULL;
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+
+  /* Setting brightness */
+  cluster = cluster::get(endpoint, LevelControl::Id);
+  attribute = attribute::get(cluster, LevelControl::Attributes::CurrentLevel::Id);
+  attribute::get_val(attribute, &val);
+  err |= light_accessory_set_brightness(led, val.val.u8);
+
+  /* Setting color */
+  cluster = cluster::get(endpoint, ColorControl::Id);
+  attribute = attribute::get(cluster, ColorControl::Attributes::ColorMode::Id);
+  attribute::get_val(attribute, &val);
+  if (val.val.u8 == (uint8_t)ColorControl::ColorMode::kCurrentHueAndCurrentSaturation) {
+    /* Setting hue */
+    attribute = attribute::get(cluster, ColorControl::Attributes::CurrentHue::Id);
+    attribute::get_val(attribute, &val);
+    err |= light_accessory_set_hue(led, val.val.u8);
+    /* Setting saturation */
+    attribute = attribute::get(cluster, ColorControl::Attributes::CurrentSaturation::Id);
+    attribute::get_val(attribute, &val);
+    err |= light_accessory_set_saturation(led, val.val.u8);
+  } else if (val.val.u8 == (uint8_t)ColorControl::ColorMode::kColorTemperature) {
+    /* Setting temperature */
+    attribute = attribute::get(cluster, ColorControl::Attributes::ColorTemperatureMireds::Id);
+    attribute::get_val(attribute, &val);
+    err |= light_accessory_set_temperature(led, val.val.u16);
+  } else {
+    log_e("Color mode not supported");
+  }
+
+  /* Setting power */
+  cluster = cluster::get(endpoint, OnOff::Id);
+  attribute = attribute::get(cluster, OnOff::Attributes::OnOff::Id);
+  attribute::get_val(attribute, &val);
+  err |= light_accessory_set_power(led, val.val.b);
+
+  return err;
+}
+
+void button_driver_init() {
+  /* Initialize button */
+  pinMode(button_gpio, INPUT_PULLUP);
+}
+
+// This callback is called for every attribute update. The callback implementation shall
+// handle the desired attributes and return an appropriate error code. If the attribute
+// is not of your interest, please do not return an error code and strictly return ESP_OK.
+static esp_err_t app_attribute_update_cb(
+  attribute::callback_type_t type, uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val, void *priv_data
+) {
+  esp_err_t err = ESP_OK;
+
+  if (type == PRE_UPDATE) {
+    /* Driver update */
+    app_driver_handle_t driver_handle = (app_driver_handle_t)priv_data;
+    err = matter_light_attribute_update(driver_handle, endpoint_id, cluster_id, attribute_id, val);
+  }
+
+  return err;
+}
+
+// This callback is invoked when clients interact with the Identify Cluster.
+// In the callback implementation, an endpoint can identify itself. (e.g., by flashing an LED or light).
+static esp_err_t app_identification_cb(identification::callback_type_t type, uint16_t endpoint_id, uint8_t effect_id, uint8_t effect_variant, void *priv_data) {
+  log_i("Identification callback: type: %u, effect: %u, variant: %u", type, effect_id, effect_variant);
+  return ESP_OK;
+}
+
+void setup() {
+  esp_err_t err = ESP_OK;
+
+  /* Initialize driver */
+  app_driver_handle_t light_handle = light_accessory_init();
+  button_driver_init();
+
+  /* Create a Matter node and add the mandatory Root Node device type on endpoint 0 */
+  node::config_t node_config;
+
+  // node handle can be used to add/modify other endpoints.
+  node_t *node = node::create(&node_config, app_attribute_update_cb, app_identification_cb);
+  if (node == nullptr) {
+    log_e("Failed to create Matter node");
+    abort();
+  }
+
+  extended_color_light::config_t light_config;
+  light_config.on_off.on_off = DEFAULT_POWER;
+  light_config.on_off.lighting.start_up_on_off = nullptr;
+  light_config.level_control.current_level = DEFAULT_BRIGHTNESS;
+  light_config.level_control.lighting.start_up_current_level = DEFAULT_BRIGHTNESS;
+  light_config.color_control.color_mode = (uint8_t)ColorControl::ColorMode::kColorTemperature;
+  light_config.color_control.enhanced_color_mode = (uint8_t)ColorControl::ColorMode::kColorTemperature;
+  light_config.color_control.color_temperature.startup_color_temperature_mireds = nullptr;
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = extended_color_light::create(node, &light_config, ENDPOINT_FLAG_NONE, light_handle);
+  if (endpoint == nullptr) {
+    log_e("Failed to create extended color light endpoint");
+    abort();
+  }
+
+  light_endpoint_id = endpoint::get_id(endpoint);
+  log_i("Light created with endpoint_id %d", light_endpoint_id);
+
+  /* Mark deferred persistence for some attributes that might be changed rapidly */
+  cluster_t *level_control_cluster = cluster::get(endpoint, LevelControl::Id);
+  attribute_t *current_level_attribute = attribute::get(level_control_cluster, LevelControl::Attributes::CurrentLevel::Id);
+  attribute::set_deferred_persistence(current_level_attribute);
+
+  cluster_t *color_control_cluster = cluster::get(endpoint, ColorControl::Id);
+  attribute_t *current_x_attribute = attribute::get(color_control_cluster, ColorControl::Attributes::CurrentX::Id);
+  attribute::set_deferred_persistence(current_x_attribute);
+  attribute_t *current_y_attribute = attribute::get(color_control_cluster, ColorControl::Attributes::CurrentY::Id);  // codespell:ignore
+  attribute::set_deferred_persistence(current_y_attribute);
+  attribute_t *color_temp_attribute = attribute::get(color_control_cluster, ColorControl::Attributes::ColorTemperatureMireds::Id);
+  attribute::set_deferred_persistence(color_temp_attribute);
+
+#if CHIP_DEVICE_CONFIG_ENABLE_THREAD
+  /* Set OpenThread platform config */
+  esp_openthread_platform_config_t config = {
+    .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(),
+    .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(),
+    .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(),
+  };
+  set_openthread_platform_config(&config);
+#endif
+
+  /* Matter start */
+  err = esp_matter::start(app_event_cb);
+  if (err != ESP_OK) {
+    log_e("Failed to start Matter, err:%d", err);
+    abort();
+  }
+
+#if CONFIG_ENABLE_ENCRYPTED_OTA
+  err = esp_matter_ota_requestor_encrypted_init(s_decryption_key, s_decryption_key_len);
+  if (err != ESP_OK) {
+    log_e("Failed to initialized the encrypted OTA, err: %d", err);
+    abort();
+  }
+#endif  // CONFIG_ENABLE_ENCRYPTED_OTA
+
+#if CONFIG_ENABLE_CHIP_SHELL
+  esp_matter::console::diagnostics_register_commands();
+  esp_matter::console::wifi_register_commands();
+#if CONFIG_OPENTHREAD_CLI
+  esp_matter::console::otcli_register_commands();
+#endif
+  esp_matter::console::init();
+#endif
+}
+
+void loop() {
+  static uint32_t button_time_stamp = 0;
+  static bool button_state = false;
+  static bool started = false;
+
+  if (!isAccessoryCommissioned()) {
+    log_w("Accessory not commissioned yet. Waiting for commissioning.");
+#ifdef RGB_BUILTIN
+    rgbLedWrite(RGB_BUILTIN, 48, 0, 20);  // Purple indicates accessory not commissioned
+#endif
+    delay(5000);
+    return;
+  }
+
+#if CHIP_DEVICE_CONFIG_ENABLE_WIFI_STATION
+  if (!isWifiConnected()) {
+    log_w("Wi-Fi not connected yet. Waiting for connection.");
+#ifdef RGB_BUILTIN
+    rgbLedWrite(RGB_BUILTIN, 48, 20, 0);  // Orange indicates accessory not connected to Wi-Fi
+#endif
+    delay(5000);
+    return;
+  }
+#endif
+
+#if CHIP_DEVICE_CONFIG_ENABLE_THREAD
+  if (!isThreadConnected()) {
+    log_w("Thread not connected yet. Waiting for connection.");
+#ifdef RGB_BUILTIN
+    rgbLedWrite(RGB_BUILTIN, 0, 20, 48);  // Blue indicates accessory not connected to Trhead
+#endif
+    delay(5000);
+    return;
+  }
+#endif
+
+  // Once all network connections are established, the accessory is ready for use
+  // Run it only once
+  if (!started) {
+    log_i("Accessory is commissioned and connected to Wi-Fi. Ready for use.");
+    started = true;
+    // Starting driver with default values
+    matter_light_set_defaults(light_endpoint_id);
+  }
+
+  // Check if the button is pressed and toggle the light right away
+  if (digitalRead(button_gpio) == LOW && !button_state) {
+    // deals with button debounce
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+
+    // Toggle button is pressed - toggle the light
+    log_i("Toggle button pressed");
+
+    endpoint_t *endpoint = endpoint::get(node::get(), light_endpoint_id);
+    cluster_t *cluster = cluster::get(endpoint, OnOff::Id);
+    attribute_t *attribute = attribute::get(cluster, OnOff::Attributes::OnOff::Id);
+
+    esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+    attribute::get_val(attribute, &val);
+    val.val.b = !val.val.b;
+    attribute::update(light_endpoint_id, OnOff::Id, OnOff::Attributes::OnOff::Id, &val);
+  }
+
+  // Check if the button is released and handle the factory reset
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > 100 && digitalRead(button_gpio) == HIGH) {
+    button_state = false;  // released. It can be pressed again after 100ms debounce.
+
+    // Factory reset is triggered if the button is pressed for more than 10 seconds
+    if (time_diff > 10000) {
+      log_i("Factory reset triggered. Light will restored to factory settings.");
+      esp_matter::factory_reset();
+    }
+  }
+
+  delay(50);  // WDT is happier with a delay
+}
diff --git a/idf_component_examples/esp_matter_light/partitions.csv b/idf_component_examples/esp_matter_light/partitions.csv
new file mode 100644
index 00000000000..ffe5f242e76
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/partitions.csv
@@ -0,0 +1,10 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+# Note: Firmware partition offset needs to be 64K aligned, initial 36K (9 sectors) are reserved for bootloader and partition table
+esp_secure_cert,  0x3F, ,0xd000,    0x2000, encrypted
+nvs,      data, nvs,     0x10000,   0xC000,
+nvs_keys, data, nvs_keys,,          0x1000, encrypted
+otadata,  data, ota,     ,          0x2000
+phy_init, data, phy,     ,          0x1000,
+ota_0,    app,  ota_0,   0x20000,   0x1E0000,
+ota_1,    app,  ota_1,   0x200000,  0x1E0000,
+fctry,    data, nvs,     0x3E0000,  0x6000
diff --git a/idf_component_examples/esp_matter_light/sdkconfig.defaults.c6_thread b/idf_component_examples/esp_matter_light/sdkconfig.defaults.c6_thread
new file mode 100644
index 00000000000..502480f94b1
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/sdkconfig.defaults.c6_thread
@@ -0,0 +1,79 @@
+CONFIG_IDF_TARGET="esp32c6"
+
+# Arduino Settings
+CONFIG_FREERTOS_HZ=1000
+CONFIG_AUTOSTART_ARDUINO=y
+
+# Log Levels
+# Boot Messages - Log level
+CONFIG_BOOTLOADER_LOG_LEVEL_ERROR=y
+# Arduino Log Level
+CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_INFO=y
+# IDF Log Level
+CONFIG_LOG_DEFAULT_LEVEL_ERROR=y
+
+# Default to 921600 baud when flashing and monitoring device
+CONFIG_ESPTOOLPY_BAUD_921600B=y
+CONFIG_ESPTOOLPY_BAUD=921600
+CONFIG_ESPTOOLPY_COMPRESSED=y
+CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
+CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+
+# libsodium
+CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y
+
+# NIMBLE
+CONFIG_BT_ENABLED=y
+CONFIG_BT_NIMBLE_ENABLED=y
+CONFIG_BT_NIMBLE_EXT_ADV=n
+CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE=70
+CONFIG_USE_BLE_ONLY_FOR_COMMISSIONING=n
+
+# FreeRTOS should use legacy API
+CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY=y
+
+# Enable OpenThread
+CONFIG_OPENTHREAD_ENABLED=y
+CONFIG_OPENTHREAD_SRP_CLIENT=y
+CONFIG_OPENTHREAD_DNS_CLIENT=y
+CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC=n
+CONFIG_OPENTHREAD_LOG_LEVEL_NOTE=y
+CONFIG_OPENTHREAD_CLI=n
+
+# Disable lwip ipv6 autoconfig
+CONFIG_LWIP_IPV6_AUTOCONFIG=n
+
+# Use a custom partition table
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
+
+# LwIP config for OpenThread
+CONFIG_LWIP_IPV6_NUM_ADDRESSES=8
+CONFIG_LWIP_MULTICAST_PING=y
+
+# MDNS platform
+CONFIG_USE_MINIMAL_MDNS=n
+CONFIG_ENABLE_EXTENDED_DISCOVERY=y
+
+# Enable OTA Requester
+CONFIG_ENABLE_OTA_REQUESTOR=n
+
+# Disable STA and AP for ESP32C6
+CONFIG_ENABLE_WIFI_STATION=n
+CONFIG_ENABLE_WIFI_AP=n
+
+# Enable chip shell
+CONFIG_ENABLE_CHIP_SHELL=n
+
+# Disable persist subscriptions
+CONFIG_ENABLE_PERSIST_SUBSCRIPTIONS=n
+
+# MRP configs
+CONFIG_MRP_LOCAL_ACTIVE_RETRY_INTERVAL_FOR_THREAD=5000
+CONFIG_MRP_LOCAL_IDLE_RETRY_INTERVAL_FOR_THREAD=5000
+CONFIG_MRP_RETRY_INTERVAL_SENDER_BOOST_FOR_THREAD=5000
+CONFIG_MRP_MAX_RETRANS=3
+
+# Enable HKDF in mbedtls
+CONFIG_MBEDTLS_HKDF_C=y
diff --git a/idf_component_examples/esp_matter_light/sdkconfig.defaults.esp32c3 b/idf_component_examples/esp_matter_light/sdkconfig.defaults.esp32c3
new file mode 100644
index 00000000000..df6d6b0d585
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/sdkconfig.defaults.esp32c3
@@ -0,0 +1,64 @@
+CONFIG_IDF_TARGET="esp32c3"
+
+# Arduino Settings
+CONFIG_FREERTOS_HZ=1000
+CONFIG_AUTOSTART_ARDUINO=y
+
+# Log Levels
+# Boot Messages - Log level
+CONFIG_BOOTLOADER_LOG_LEVEL_ERROR=y
+# Arduino Log Level
+CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_INFO=y
+# IDF Log Level
+CONFIG_LOG_DEFAULT_LEVEL_ERROR=y
+
+# Default to 921600 baud when flashing and monitoring device
+CONFIG_ESPTOOLPY_BAUD_921600B=y
+CONFIG_ESPTOOLPY_BAUD=921600
+CONFIG_ESPTOOLPY_COMPRESSED=y
+CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
+CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+
+#enable BT
+CONFIG_BT_ENABLED=y
+CONFIG_BT_NIMBLE_ENABLED=y
+
+#disable BT connection reattempt
+CONFIG_BT_NIMBLE_ENABLE_CONN_REATTEMPT=n
+
+#enable lwip ipv6 autoconfig
+CONFIG_LWIP_IPV6_AUTOCONFIG=y
+
+# Use a custom partition table
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_PARTITION_TABLE_OFFSET=0xC000
+
+# Disable chip shell
+CONFIG_ENABLE_CHIP_SHELL=n
+
+# Enable OTA Requester
+CONFIG_ENABLE_OTA_REQUESTOR=n
+
+#enable lwIP route hooks
+CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT=y
+CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT=y
+
+# disable softap by default
+CONFIG_ESP_WIFI_SOFTAP_SUPPORT=n
+CONFIG_ENABLE_WIFI_STATION=y
+CONFIG_ENABLE_WIFI_AP=n
+
+# Disable DS Peripheral
+CONFIG_ESP_SECURE_CERT_DS_PERIPHERAL=n
+
+# Use compact attribute storage mode
+CONFIG_ESP_MATTER_NVS_USE_COMPACT_ATTR_STORAGE=y
+
+# Enable HKDF in mbedtls
+CONFIG_MBEDTLS_HKDF_C=y
+
+# Increase LwIP IPv6 address number to 6 (MAX_FABRIC + 1)
+# unique local addresses for fabrics(MAX_FABRIC), a link local address(1)
+CONFIG_LWIP_IPV6_NUM_ADDRESSES=6
diff --git a/idf_component_examples/esp_matter_light/sdkconfig.defaults.esp32c6 b/idf_component_examples/esp_matter_light/sdkconfig.defaults.esp32c6
new file mode 100644
index 00000000000..f228f3158c8
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/sdkconfig.defaults.esp32c6
@@ -0,0 +1,79 @@
+CONFIG_IDF_TARGET="esp32c6"
+
+# Arduino Settings
+CONFIG_FREERTOS_HZ=1000
+CONFIG_AUTOSTART_ARDUINO=y
+
+# Log Levels
+# Boot Messages - Log level
+CONFIG_BOOTLOADER_LOG_LEVEL_ERROR=y
+# Arduino Log Level
+CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_INFO=y
+# IDF Log Level
+CONFIG_LOG_DEFAULT_LEVEL_ERROR=y
+
+# Default to 921600 baud when flashing and monitoring device
+CONFIG_ESPTOOLPY_BAUD_921600B=y
+CONFIG_ESPTOOLPY_BAUD=921600
+CONFIG_ESPTOOLPY_COMPRESSED=y
+CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
+CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+
+#enable BT
+CONFIG_BT_ENABLED=y
+CONFIG_BT_NIMBLE_ENABLED=y
+
+#disable BT connection reattempt
+CONFIG_BT_NIMBLE_ENABLE_CONN_REATTEMPT=n
+
+#enable lwip ipv6 autoconfig
+CONFIG_LWIP_IPV6_AUTOCONFIG=y
+
+# Use a custom partition table
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_PARTITION_TABLE_OFFSET=0xC000
+
+# Disable chip shell
+CONFIG_ENABLE_CHIP_SHELL=n
+
+# Enable OTA Requester
+CONFIG_ENABLE_OTA_REQUESTOR=n
+
+#enable lwIP route hooks
+CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT=y
+CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT=y
+
+# disable softap by default
+CONFIG_ESP_WIFI_SOFTAP_SUPPORT=n
+CONFIG_ENABLE_WIFI_STATION=y
+CONFIG_ENABLE_WIFI_AP=n
+
+# Disable DS Peripheral
+CONFIG_ESP_SECURE_CERT_DS_PERIPHERAL=n
+
+# Use compact attribute storage mode
+CONFIG_ESP_MATTER_NVS_USE_COMPACT_ATTR_STORAGE=y
+
+# Enable HKDF in mbedtls
+CONFIG_MBEDTLS_HKDF_C=y
+
+# Increase LwIP IPv6 address number to 6 (MAX_FABRIC + 1)
+# unique local addresses for fabrics(MAX_FABRIC), a link local address(1)
+CONFIG_LWIP_IPV6_NUM_ADDRESSES=6
+
+# libsodium
+CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y
+
+# NIMBLE
+CONFIG_BT_NIMBLE_EXT_ADV=n
+CONFIG_BT_NIMBLE_HCI_EVT_BUF_SIZE=70
+CONFIG_USE_BLE_ONLY_FOR_COMMISSIONING=y
+
+# FreeRTOS should use legacy API
+CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY=y
+
+# Use minimal mDNS
+CONFIG_USE_MINIMAL_MDNS=y
+CONFIG_ENABLE_EXTENDED_DISCOVERY=y
diff --git a/idf_component_examples/esp_matter_light/sdkconfig.defaults.esp32s3 b/idf_component_examples/esp_matter_light/sdkconfig.defaults.esp32s3
new file mode 100644
index 00000000000..9c1aa36b6c9
--- /dev/null
+++ b/idf_component_examples/esp_matter_light/sdkconfig.defaults.esp32s3
@@ -0,0 +1,64 @@
+CONFIG_IDF_TARGET="esp32s3"
+
+# Arduino Settings
+CONFIG_FREERTOS_HZ=1000
+CONFIG_AUTOSTART_ARDUINO=y
+
+# Log Levels
+# Boot Messages - Log level
+CONFIG_BOOTLOADER_LOG_LEVEL_ERROR=y
+# Arduino Log Level
+CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_INFO=y
+# IDF Log Level
+CONFIG_LOG_DEFAULT_LEVEL_ERROR=y
+
+# Default to 921600 baud when flashing and monitoring device
+CONFIG_ESPTOOLPY_BAUD_921600B=y
+CONFIG_ESPTOOLPY_BAUD=921600
+CONFIG_ESPTOOLPY_COMPRESSED=y
+CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
+CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+
+#enable BT
+CONFIG_BT_ENABLED=y
+CONFIG_BT_NIMBLE_ENABLED=y
+
+#disable BT connection reattempt
+CONFIG_BT_NIMBLE_ENABLE_CONN_REATTEMPT=n
+
+#enable lwip ipv6 autoconfig
+CONFIG_LWIP_IPV6_AUTOCONFIG=y
+
+# Use a custom partition table
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_PARTITION_TABLE_OFFSET=0xC000
+
+# Disable chip shell
+CONFIG_ENABLE_CHIP_SHELL=n
+
+# Enable OTA Requester
+CONFIG_ENABLE_OTA_REQUESTOR=n
+
+#enable lwIP route hooks
+CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT=y
+CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT=y
+
+# disable softap by default
+CONFIG_ESP_WIFI_SOFTAP_SUPPORT=n
+CONFIG_ENABLE_WIFI_STATION=y
+CONFIG_ENABLE_WIFI_AP=n
+
+# Disable DS Peripheral
+CONFIG_ESP_SECURE_CERT_DS_PERIPHERAL=n
+
+# Use compact attribute storage mode
+CONFIG_ESP_MATTER_NVS_USE_COMPACT_ATTR_STORAGE=y
+
+# Enable HKDF in mbedtls
+CONFIG_MBEDTLS_HKDF_C=y
+
+# Increase LwIP IPv6 address number to 6 (MAX_FABRIC + 1)
+# unique local addresses for fabrics(MAX_FABRIC), a link local address(1)
+CONFIG_LWIP_IPV6_NUM_ADDRESSES=6
diff --git a/idf_component_examples/hello_world/CMakeLists.txt b/idf_component_examples/hello_world/CMakeLists.txt
new file mode 100644
index 00000000000..664d45871d0
--- /dev/null
+++ b/idf_component_examples/hello_world/CMakeLists.txt
@@ -0,0 +1,8 @@
+# For more information about build system see
+# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html
+# The following five lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(main)
diff --git a/idf_component_examples/hello_world/README.md b/idf_component_examples/hello_world/README.md
new file mode 100644
index 00000000000..6e5f1e9acff
--- /dev/null
+++ b/idf_component_examples/hello_world/README.md
@@ -0,0 +1,63 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+
+# _Hello world example_
+
+This is the simplest buildable example made to be used as a template for new projects running Arduino-esp32 as an ESP-IDF component.
+See [Arduino-esp32](https://components.espressif.com/components/espressif/arduino-esp32) in ESP Registry.
+
+## How to use example
+
+To create a ESP-IDF project from this example with the latest release of Arduino-esp32, you can simply run command: `idf.py create-project-from-example "espressif/arduino-esp32:hello_world"`.
+ESP-IDF will download all dependencies needed from the component registry and setup the project for you.
+
+If you want to use cloned Arduino-esp32 repository, you can build this example directly.
+Go to the example folder `arduino-esp32/idf_component_examples/hello_world`.
+First you need to comment line 6 `pre_release: true` in examples `/main/idf_component.yml`.
+Then just run command: `idf.py build`.
+
+## Example folder contents
+
+The project **hello_world** contains one source file in C++ language [main.cpp](main/main.cpp). The file is located in folder [main](main).
+
+ESP-IDF projects are built using CMake. The project build configuration is contained in `CMakeLists.txt`
+files that provide set of directives and instructions describing the project's source files and targets
+(executable, library, or both).
+
+Below is short explanation of remaining files in the project folder.
+
+```
+├── CMakeLists.txt
+├── main
+│   ├── CMakeLists.txt
+│   ├── idf_component.yml
+│   └── main.cpp
+└── README.md                  This is the file you are currently reading
+```
+
+## How to add Arduino libraries
+
+In the project create folder `components/` and clone the library there.
+In the library folder create new CMakeLists.txt file, add lines shown below to the file and edit the SRCS to match the library source files.
+
+```
+idf_component_register(SRCS "user_library.cpp" "another_source.c"
+                      INCLUDE_DIRS "."
+                      REQUIRES arduino-esp32
+                      )
+```
+
+Below is structure of the project folder with the Arduino libraries.
+
+```
+├── CMakeLists.txt
+├── components
+│   ├── user_library
+│   │   ├── CMakeLists.txt     This needs to be added
+│   │   ├── ...
+├── main
+│   ├── CMakeLists.txt
+│   ├── idf_component.yml
+│   └── main.cpp
+└── README.md                  This is the file you are currently reading
+```
diff --git a/idf_component_examples/hello_world/main/CMakeLists.txt b/idf_component_examples/hello_world/main/CMakeLists.txt
new file mode 100644
index 00000000000..9eb7ec47a07
--- /dev/null
+++ b/idf_component_examples/hello_world/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "main.cpp"
+                    INCLUDE_DIRS ".")
diff --git a/idf_component_examples/hello_world/main/idf_component.yml b/idf_component_examples/hello_world/main/idf_component.yml
new file mode 100644
index 00000000000..f955824767c
--- /dev/null
+++ b/idf_component_examples/hello_world/main/idf_component.yml
@@ -0,0 +1,6 @@
+## IDF Component Manager Manifest File
+dependencies:
+  espressif/arduino-esp32:
+    version: "*"
+    override_path: "../../../"
+    pre_release: true
diff --git a/idf_component_examples/hello_world/main/main.cpp b/idf_component_examples/hello_world/main/main.cpp
new file mode 100644
index 00000000000..7068f5f15cf
--- /dev/null
+++ b/idf_component_examples/hello_world/main/main.cpp
@@ -0,0 +1,10 @@
+#include "Arduino.h"
+
+void setup() {
+  Serial.begin(115200);
+}
+
+void loop() {
+  Serial.println("Hello world!");
+  delay(1000);
+}
diff --git a/idf_component_examples/hello_world/sdkconfig.defaults b/idf_component_examples/hello_world/sdkconfig.defaults
new file mode 100644
index 00000000000..bb723653f8a
--- /dev/null
+++ b/idf_component_examples/hello_world/sdkconfig.defaults
@@ -0,0 +1,12 @@
+#
+# Arduino ESP32
+#
+CONFIG_AUTOSTART_ARDUINO=y
+# end of Arduino ESP32
+
+#
+# FREERTOS
+#
+CONFIG_FREERTOS_HZ=1000
+# end of FREERTOS
+# end of Component config
diff --git a/idf_component_examples/hw_cdc_hello_world/CMakeLists.txt b/idf_component_examples/hw_cdc_hello_world/CMakeLists.txt
new file mode 100644
index 00000000000..16bb1063af3
--- /dev/null
+++ b/idf_component_examples/hw_cdc_hello_world/CMakeLists.txt
@@ -0,0 +1,12 @@
+# For more information about build system see
+# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html
+# The following five lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+# Adds necessary definitions for compiling it using Serial symbol attached to the HW USB CDC port
+list(APPEND compile_definitions "ARDUINO_USB_CDC_ON_BOOT=1")
+list(APPEND compile_definitions "ARDUINO_USB_MODE=1")
+
+project(hw_cdc_hello_world)
diff --git a/idf_component_examples/hw_cdc_hello_world/README.md b/idf_component_examples/hw_cdc_hello_world/README.md
new file mode 100644
index 00000000000..e4356d75ac3
--- /dev/null
+++ b/idf_component_examples/hw_cdc_hello_world/README.md
@@ -0,0 +1,63 @@
+| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- |
+
+# _HW Serial USB CDC example_
+
+This is the simplest buildable example made to be used as a template for new projects running Arduino-ESP32 as an ESP-IDF component that will redefine the `Serial` interface to be attached to the USB CDC Hardware Serial port.\
+See [arduino-esp32](https://components.espressif.com/components/espressif/arduino-esp32) in ESP Registry.
+
+## How to use example
+
+After cloning this repository, go to the `hw_cdc_hello_world` folder and select the target by executing\
+`idf.py set-target <SoC_target>`.\
+`<SoC_target>` can be one of the installed IDF version supported targets.
+
+It is possible to just clone this folder be executing\
+`idf.py create-project-from-example "espressif/arduino-esp32^3.0.5:hw_cdc_hello_world"`
+
+For IDF 5.1.x and forward, the list of targets that support Hardware USB CDC are, at least: esp32s3, esp32c3, esp32c6 and esp32h2.\
+Then just run command: `idf.py build` or `idf.py -p USB_PORT flash monitor`.
+
+Usually, it is necessary to make the ESP32 SoC to enter in `Download Mode` before uploading the firmware.\
+After that, just press `RESET/EN` to start the new firmware.
+
+## Example folder contents
+
+The project **hw_serial_example** contains one source file in C++ language [main.cpp](main/main.cpp). The file is located in folder [main](main).
+
+ESP-IDF projects are built using CMake. The project building configuration is contained in `CMakeLists.txt`
+file that provide a set of directives and instructions describing the project's source files and targets
+(executable, library, or both).
+
+Below is the minimum list of files in the project folder.
+
+```
+├── CMakeLists.txt             Global project CMake configuration file
+├── sdkconfig.defaults         sdkconfig setting for an Arduino project
+├── main  
+│   ├── CMakeLists.txt         Arduino sketch CMake configuration file
+│   ├── idf_component.yml      List of IDF components necessary to build the project
+│   └── main.cpp               Arduino Sketch code - don't forget to add "#include <Arduino.h>" on it
+└── README.md                  This is the file you are currently reading
+```
+
+## Configuring the Hardware USB CDC Serial
+
+ESP32 Arduino has two macro defined symbols that control what `Serial` symbol will represent.
+Default `Serial` is the UART0 from `HardwareSerial` class.
+
+`Serial` can be changed to be attached to the HW Serial JTAG port fro the SoC.
+In order to make it work, it is necessary to define 2 symbols: `ARDUINO_USB_CDC_ON_BOOT` and `ARDUINO_USB_MODE` to `1`.
+This is achieved by adding a couple lines to the [Project Folder CMakeLists.txt](CMakeLists.txt) file.
+
+
+```
+# Adds necessary definitions for compiling it using Serial symbol attached to the HW USB CDC port
+list(APPEND compile_definitions "ARDUINO_USB_CDC_ON_BOOT=1")
+list(APPEND compile_definitions "ARDUINO_USB_MODE=1")
+
+```
+
+Those two lines will add a `-DSYMBOL=VAL` when compiling every source code file.
+
+In order to make sure that it is actually working correctly, the [sketch](main/main.cpp) will execute `Serial.begin();` with no baudrate, which only works for USB CDC.
diff --git a/idf_component_examples/hw_cdc_hello_world/main/CMakeLists.txt b/idf_component_examples/hw_cdc_hello_world/main/CMakeLists.txt
new file mode 100644
index 00000000000..25a78dec2a6
--- /dev/null
+++ b/idf_component_examples/hw_cdc_hello_world/main/CMakeLists.txt
@@ -0,0 +1,4 @@
+idf_component_register(
+    SRC_DIRS     "."
+    INCLUDE_DIRS "."
+)
diff --git a/idf_component_examples/hw_cdc_hello_world/main/idf_component.yml b/idf_component_examples/hw_cdc_hello_world/main/idf_component.yml
new file mode 100644
index 00000000000..f955824767c
--- /dev/null
+++ b/idf_component_examples/hw_cdc_hello_world/main/idf_component.yml
@@ -0,0 +1,6 @@
+## IDF Component Manager Manifest File
+dependencies:
+  espressif/arduino-esp32:
+    version: "*"
+    override_path: "../../../"
+    pre_release: true
diff --git a/idf_component_examples/hw_cdc_hello_world/main/main.cpp b/idf_component_examples/hw_cdc_hello_world/main/main.cpp
new file mode 100644
index 00000000000..18718678430
--- /dev/null
+++ b/idf_component_examples/hw_cdc_hello_world/main/main.cpp
@@ -0,0 +1,18 @@
+#include <Arduino.h>
+
+void setup() {
+  // USB CDC doesn't need a baud rate
+  Serial.begin();
+
+  // wait for the Serial Monitor to be open
+  while (!Serial) {
+    delay(100);
+  }
+
+  Serial.println("\r\nStarting...\r\n");
+}
+
+void loop() {
+  Serial.println("Hello world!");
+  delay(1000);
+}
diff --git a/idf_component_examples/hw_cdc_hello_world/sdkconfig.defaults b/idf_component_examples/hw_cdc_hello_world/sdkconfig.defaults
new file mode 100644
index 00000000000..bb723653f8a
--- /dev/null
+++ b/idf_component_examples/hw_cdc_hello_world/sdkconfig.defaults
@@ -0,0 +1,12 @@
+#
+# Arduino ESP32
+#
+CONFIG_AUTOSTART_ARDUINO=y
+# end of Arduino ESP32
+
+#
+# FREERTOS
+#
+CONFIG_FREERTOS_HZ=1000
+# end of FREERTOS
+# end of Component config
diff --git a/libraries/ArduinoOTA/examples/BasicOTA/BasicOTA.ino b/libraries/ArduinoOTA/examples/BasicOTA/BasicOTA.ino
index 83652495295..b3b01be61cd 100644
--- a/libraries/ArduinoOTA/examples/BasicOTA/BasicOTA.ino
+++ b/libraries/ArduinoOTA/examples/BasicOTA/BasicOTA.ino
@@ -1,10 +1,24 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
 #include <WiFi.h>
 #include <ESPmDNS.h>
-#include <WiFiUdp.h>
+#include <NetworkUdp.h>
 #include <ArduinoOTA.h>
 
-const char* ssid = "..........";
-const char* password = "..........";
+const char *ssid = "..........";
+const char *password = "..........";
 
 void setup() {
   Serial.begin(115200);
@@ -33,10 +47,11 @@ void setup() {
   ArduinoOTA
     .onStart([]() {
       String type;
-      if (ArduinoOTA.getCommand() == U_FLASH)
+      if (ArduinoOTA.getCommand() == U_FLASH) {
         type = "sketch";
-      else // U_SPIFFS
+      } else {  // U_SPIFFS
         type = "filesystem";
+      }
 
       // NOTE: if updating SPIFFS this would be the place to unmount SPIFFS using SPIFFS.end()
       Serial.println("Start updating " + type);
@@ -49,11 +64,17 @@ void setup() {
     })
     .onError([](ota_error_t error) {
       Serial.printf("Error[%u]: ", error);
-      if (error == OTA_AUTH_ERROR) Serial.println("Auth Failed");
-      else if (error == OTA_BEGIN_ERROR) Serial.println("Begin Failed");
-      else if (error == OTA_CONNECT_ERROR) Serial.println("Connect Failed");
-      else if (error == OTA_RECEIVE_ERROR) Serial.println("Receive Failed");
-      else if (error == OTA_END_ERROR) Serial.println("End Failed");
+      if (error == OTA_AUTH_ERROR) {
+        Serial.println("Auth Failed");
+      } else if (error == OTA_BEGIN_ERROR) {
+        Serial.println("Begin Failed");
+      } else if (error == OTA_CONNECT_ERROR) {
+        Serial.println("Connect Failed");
+      } else if (error == OTA_RECEIVE_ERROR) {
+        Serial.println("Receive Failed");
+      } else if (error == OTA_END_ERROR) {
+        Serial.println("End Failed");
+      }
     });
 
   ArduinoOTA.begin();
@@ -65,4 +86,4 @@ void setup() {
 
 void loop() {
   ArduinoOTA.handle();
-}
\ No newline at end of file
+}
diff --git a/libraries/ArduinoOTA/examples/BasicOTA/ci.json b/libraries/ArduinoOTA/examples/BasicOTA/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/ArduinoOTA/examples/BasicOTA/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/ArduinoOTA/examples/OTAWebUpdater/OTAWebUpdater.ino b/libraries/ArduinoOTA/examples/OTAWebUpdater/OTAWebUpdater.ino
deleted file mode 100644
index 4c4adc7fe87..00000000000
--- a/libraries/ArduinoOTA/examples/OTAWebUpdater/OTAWebUpdater.ino
+++ /dev/null
@@ -1,169 +0,0 @@
-#include <WiFi.h>
-#include <WiFiClient.h>
-#include <WebServer.h>
-#include <ESPmDNS.h>
-#include <Update.h>
-
-const char* host = "esp32";
-const char* ssid = "xxx";
-const char* password = "xxxx";
-
-WebServer server(80);
-
-/*
- * Login page
- */
-
-const char* loginIndex =
- "<form name='loginForm'>"
-    "<table width='20%' bgcolor='A09F9F' align='center'>"
-        "<tr>"
-            "<td colspan=2>"
-                "<center><font size=4><b>ESP32 Login Page</b></font></center>"
-                "<br>"
-            "</td>"
-            "<br>"
-            "<br>"
-        "</tr>"
-        "<tr>"
-             "<td>Username:</td>"
-             "<td><input type='text' size=25 name='userid'><br></td>"
-        "</tr>"
-        "<br>"
-        "<br>"
-        "<tr>"
-            "<td>Password:</td>"
-            "<td><input type='Password' size=25 name='pwd'><br></td>"
-            "<br>"
-            "<br>"
-        "</tr>"
-        "<tr>"
-            "<td><input type='submit' onclick='check(this.form)' value='Login'></td>"
-        "</tr>"
-    "</table>"
-"</form>"
-"<script>"
-    "function check(form)"
-    "{"
-    "if(form.userid.value=='admin' && form.pwd.value=='admin')"
-    "{"
-    "window.open('/serverIndex')"
-    "}"
-    "else"
-    "{"
-    " alert('Error Password or Username')/*displays error message*/"
-    "}"
-    "}"
-"</script>";
-
-/*
- * Server Index Page
- */
-
-const char* serverIndex =
-"<script src='https://ajax.googleapis.com/ajax/libs/jquery/3.2.1/jquery.min.js'></script>"
-"<form method='POST' action='#' enctype='multipart/form-data' id='upload_form'>"
-   "<input type='file' name='update'>"
-        "<input type='submit' value='Update'>"
-    "</form>"
- "<div id='prg'>progress: 0%</div>"
- "<script>"
-  "$('form').submit(function(e){"
-  "e.preventDefault();"
-  "var form = $('#upload_form')[0];"
-  "var data = new FormData(form);"
-  " $.ajax({"
-  "url: '/update',"
-  "type: 'POST',"
-  "data: data,"
-  "contentType: false,"
-  "processData:false,"
-  "xhr: function() {"
-  "var xhr = new window.XMLHttpRequest();"
-  "xhr.upload.addEventListener('progress', function(evt) {"
-  "if (evt.lengthComputable) {"
-  "var per = evt.loaded / evt.total;"
-  "$('#prg').html('progress: ' + Math.round(per*100) + '%');"
-  "}"
-  "}, false);"
-  "return xhr;"
-  "},"
-  "success:function(d, s) {"
-  "console.log('success!')"
- "},"
- "error: function (a, b, c) {"
- "}"
- "});"
- "});"
- "</script>";
-
-/*
- * setup function
- */
-void setup(void) {
-  Serial.begin(115200);
-
-  // Connect to WiFi network
-  WiFi.begin(ssid, password);
-  Serial.println("");
-
-  // Wait for connection
-  while (WiFi.status() != WL_CONNECTED) {
-    delay(500);
-    Serial.print(".");
-  }
-  Serial.println("");
-  Serial.print("Connected to ");
-  Serial.println(ssid);
-  Serial.print("IP address: ");
-  Serial.println(WiFi.localIP());
-
-  /*use mdns for host name resolution*/
-  if (!MDNS.begin(host)) { //http://esp32.local
-    Serial.println("Error setting up MDNS responder!");
-    while (1) {
-      delay(1000);
-    }
-  }
-  Serial.println("mDNS responder started");
-  /*return index page which is stored in serverIndex */
-  server.on("/", HTTP_GET, []() {
-    server.sendHeader("Connection", "close");
-    server.send(200, "text/html", loginIndex);
-  });
-  server.on("/serverIndex", HTTP_GET, []() {
-    server.sendHeader("Connection", "close");
-    server.send(200, "text/html", serverIndex);
-  });
-  /*handling uploading firmware file */
-  server.on("/update", HTTP_POST, []() {
-    server.sendHeader("Connection", "close");
-    server.send(200, "text/plain", (Update.hasError()) ? "FAIL" : "OK");
-    ESP.restart();
-  }, []() {
-    HTTPUpload& upload = server.upload();
-    if (upload.status == UPLOAD_FILE_START) {
-      Serial.printf("Update: %s\n", upload.filename.c_str());
-      if (!Update.begin(UPDATE_SIZE_UNKNOWN)) { //start with max available size
-        Update.printError(Serial);
-      }
-    } else if (upload.status == UPLOAD_FILE_WRITE) {
-      /* flashing firmware to ESP*/
-      if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) {
-        Update.printError(Serial);
-      }
-    } else if (upload.status == UPLOAD_FILE_END) {
-      if (Update.end(true)) { //true to set the size to the current progress
-        Serial.printf("Update Success: %u\nRebooting...\n", upload.totalSize);
-      } else {
-        Update.printError(Serial);
-      }
-    }
-  });
-  server.begin();
-}
-
-void loop(void) {
-  server.handleClient();
-  delay(1);
-}
diff --git a/libraries/ArduinoOTA/keywords.txt b/libraries/ArduinoOTA/keywords.txt
index 1c14d9e8989..9774de881ea 100644
--- a/libraries/ArduinoOTA/keywords.txt
+++ b/libraries/ArduinoOTA/keywords.txt
@@ -7,20 +7,40 @@
 #######################################
 
 ArduinoOTA	KEYWORD1
+ArduinoOTAClass	KEYWORD1
 
 #######################################
 # Methods and Functions (KEYWORD2)
 #######################################
 
 begin	KEYWORD2
-setup	KEYWORD2
+end	KEYWORD2
 handle	KEYWORD2
 onStart	KEYWORD2
 onEnd	KEYWORD2
 onError	KEYWORD2
 onProgress	KEYWORD2
+setPort	KEYWORD2
+setHostname	KEYWORD2
+getHostname	KEYWORD2
+setPassword	KEYWORD2
+setPasswordHash	KEYWORD2
+setPartitionLabel	KEYWORD2
+getPartitionLabel	KEYWORD2
+setRebootOnSuccess	KEYWORD2
+setMdnsEnabled	KEYWORD2
+getCommand	KEYWORD2
+setTimeout	KEYWORD2
 
 #######################################
 # Constants (LITERAL1)
 #######################################
 
+OTA_IDLE  LITERAL1
+OTA_WAITAUTH  LITERAL1
+OTA_RUNUPDATE  LITERAL1
+OTA_AUTH_ERROR  LITERAL1
+OTA_BEGIN_ERROR  LITERAL1
+OTA_CONNECT_ERROR  LITERAL1
+OTA_RECEIVE_ERROR  LITERAL1
+OTA_END_ERROR  LITERAL1
diff --git a/libraries/ArduinoOTA/library.properties b/libraries/ArduinoOTA/library.properties
index 22d78c55a7b..0796eddf318 100644
--- a/libraries/ArduinoOTA/library.properties
+++ b/libraries/ArduinoOTA/library.properties
@@ -1,9 +1,9 @@
 name=ArduinoOTA
-version=1.0
+version=3.2.0
 author=Ivan Grokhotkov and Hristo Gochkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=Enables Over The Air upgrades, via wifi and espota.py UDP request/TCP download.
-paragraph=With this library you can enable your sketch to be upgraded over network. Includes mdns anounces to get discovered by the arduino IDE.
+paragraph=With this library you can enable your sketch to be upgraded over network. Includes mdns announces to get discovered by the arduino IDE.
 category=Communication
 url=
 architectures=esp32
diff --git a/libraries/ArduinoOTA/src/ArduinoOTA.cpp b/libraries/ArduinoOTA/src/ArduinoOTA.cpp
index fe85580f566..cb3ddc1e797 100644
--- a/libraries/ArduinoOTA/src/ArduinoOTA.cpp
+++ b/libraries/ArduinoOTA/src/ArduinoOTA.cpp
@@ -1,393 +1,408 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
 #ifndef LWIP_OPEN_SRC
 #define LWIP_OPEN_SRC
 #endif
 #include <functional>
-#include <WiFiUdp.h>
 #include "ArduinoOTA.h"
+#include "NetworkClient.h"
 #include "ESPmDNS.h"
 #include "MD5Builder.h"
 #include "Update.h"
 
-
 // #define OTA_DEBUG Serial
 
 ArduinoOTAClass::ArduinoOTAClass()
-: _port(0)
-, _initialized(false)
-, _rebootOnSuccess(true)
-, _mdnsEnabled(true)
-, _state(OTA_IDLE)
-, _size(0)
-, _cmd(0)
-, _ota_port(0)
-, _ota_timeout(1000)
-, _start_callback(NULL)
-, _end_callback(NULL)
-, _error_callback(NULL)
-, _progress_callback(NULL)
-{
-}
+  : _port(0), _initialized(false), _rebootOnSuccess(true), _mdnsEnabled(true), _state(OTA_IDLE), _size(0), _cmd(0), _ota_port(0), _ota_timeout(1000),
+    _start_callback(NULL), _end_callback(NULL), _error_callback(NULL), _progress_callback(NULL) {}
 
-ArduinoOTAClass::~ArduinoOTAClass(){
-    _udp_ota.stop();
+ArduinoOTAClass::~ArduinoOTAClass() {
+  end();
 }
 
-ArduinoOTAClass& ArduinoOTAClass::onStart(THandlerFunction fn) {
-    _start_callback = fn;
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::onStart(THandlerFunction fn) {
+  _start_callback = fn;
+  return *this;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::onEnd(THandlerFunction fn) {
-    _end_callback = fn;
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::onEnd(THandlerFunction fn) {
+  _end_callback = fn;
+  return *this;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::onProgress(THandlerFunction_Progress fn) {
-    _progress_callback = fn;
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::onProgress(THandlerFunction_Progress fn) {
+  _progress_callback = fn;
+  return *this;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::onError(THandlerFunction_Error fn) {
-    _error_callback = fn;
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::onError(THandlerFunction_Error fn) {
+  _error_callback = fn;
+  return *this;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::setPort(uint16_t port) {
-    if (!_initialized && !_port && port) {
-        _port = port;
-    }
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::setPort(uint16_t port) {
+  if (!_initialized && !_port && port) {
+    _port = port;
+  }
+  return *this;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::setHostname(const char * hostname) {
-    if (!_initialized && !_hostname.length() && hostname) {
-        _hostname = hostname;
-    }
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::setHostname(const char *hostname) {
+  if (!_initialized && !_hostname.length() && hostname) {
+    _hostname = hostname;
+  }
+  return *this;
 }
 
 String ArduinoOTAClass::getHostname() {
-    return _hostname;
+  return _hostname;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::setPassword(const char * password) {
-    if (!_initialized && !_password.length() && password) {
-        MD5Builder passmd5;
-        passmd5.begin();
-        passmd5.add(password);
-        passmd5.calculate();
-        _password = passmd5.toString();
-    }
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::setPassword(const char *password) {
+  if (_state == OTA_IDLE && password) {
+    MD5Builder passmd5;
+    passmd5.begin();
+    passmd5.add(password);
+    passmd5.calculate();
+    _password.clear();
+    _password = passmd5.toString();
+  }
+  return *this;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::setPasswordHash(const char * password) {
-    if (!_initialized && !_password.length() && password) {
-        _password = password;
-    }
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::setPasswordHash(const char *password) {
+  if (_state == OTA_IDLE && password) {
+    _password.clear();
+    _password = password;
+  }
+  return *this;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::setPartitionLabel(const char * partition_label) {
-    if (!_initialized && !_partition_label.length() && partition_label) {
-        _partition_label = partition_label;
-    }
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::setPartitionLabel(const char *partition_label) {
+  if (_state == OTA_IDLE && partition_label) {
+    _partition_label.clear();
+    _partition_label = partition_label;
+  }
+  return *this;
 }
 
 String ArduinoOTAClass::getPartitionLabel() {
-    return _partition_label;
+  return _partition_label;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::setRebootOnSuccess(bool reboot){
-    _rebootOnSuccess = reboot;
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::setRebootOnSuccess(bool reboot) {
+  _rebootOnSuccess = reboot;
+  return *this;
 }
 
-ArduinoOTAClass& ArduinoOTAClass::setMdnsEnabled(bool enabled){
-    _mdnsEnabled = enabled;
-    return *this;
+ArduinoOTAClass &ArduinoOTAClass::setMdnsEnabled(bool enabled) {
+  _mdnsEnabled = enabled;
+  return *this;
 }
 
 void ArduinoOTAClass::begin() {
-    if (_initialized){
-        log_w("already initialized");
-        return;
-    }
+  if (_initialized) {
+    log_w("already initialized");
+    return;
+  }
+
+  if (!_port) {
+    _port = 3232;
+  }
+
+  if (!_udp_ota.begin(_port)) {
+    log_e("udp bind failed");
+    return;
+  }
+
+  if (!_hostname.length()) {
+    char tmp[20];
+    uint8_t mac[6];
+    Network.macAddress(mac);
+    sprintf(tmp, "esp32-%02x%02x%02x%02x%02x%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+    _hostname = tmp;
+  }
+#ifdef CONFIG_MDNS_MAX_INTERFACES
+  if (_mdnsEnabled) {
+    MDNS.begin(_hostname.c_str());
+    MDNS.enableArduino(_port, (_password.length() > 0));
+  }
+#endif
+  _initialized = true;
+  _state = OTA_IDLE;
+  log_i("OTA server at: %s.local:%u", _hostname.c_str(), _port);
+}
 
-    if (!_port) {
-        _port = 3232;
+int ArduinoOTAClass::parseInt() {
+  char data[INT_BUFFER_SIZE];
+  uint8_t index = 0;
+  char value;
+  while (_udp_ota.peek() == ' ') {
+    _udp_ota.read();
+  }
+  while (index < INT_BUFFER_SIZE - 1) {
+    value = _udp_ota.peek();
+    if (value < '0' || value > '9') {
+      data[index++] = '\0';
+      return atoi(data);
     }
+    data[index++] = _udp_ota.read();
+  }
+  return 0;
+}
 
-    if(!_udp_ota.begin(_port)){
-        log_e("udp bind failed");
-        return;
+String ArduinoOTAClass::readStringUntil(char end) {
+  String res = "";
+  int value;
+  while (true) {
+    value = _udp_ota.read();
+    if (value <= 0 || value == end) {
+      return res;
     }
+    res += (char)value;
+  }
+  return res;
+}
 
-
-    if (!_hostname.length()) {
-        char tmp[20];
-        uint8_t mac[6];
-        WiFi.macAddress(mac);
-        sprintf(tmp, "esp32-%02x%02x%02x%02x%02x%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-        _hostname = tmp;
+void ArduinoOTAClass::_onRx() {
+  if (_state == OTA_IDLE) {
+    int cmd = parseInt();
+    if (cmd != U_FLASH && cmd != U_SPIFFS) {
+      return;
     }
-    if(_mdnsEnabled){
-        MDNS.begin(_hostname.c_str());
-        MDNS.enableArduino(_port, (_password.length() > 0));
+    _cmd = cmd;
+    _ota_port = parseInt();
+    _size = parseInt();
+    _udp_ota.read();
+    _md5 = readStringUntil('\n');
+    _md5.trim();
+    if (_md5.length() != 32) {
+      log_e("bad md5 length");
+      return;
     }
-    _initialized = true;
-    _state = OTA_IDLE;
-    log_i("OTA server at: %s.local:%u", _hostname.c_str(), _port);
-}
 
-int ArduinoOTAClass::parseInt(){
-    char data[INT_BUFFER_SIZE];
-    uint8_t index = 0;
-    char value;
-    while(_udp_ota.peek() == ' ') _udp_ota.read();
-    while(index < INT_BUFFER_SIZE - 1){
-        value = _udp_ota.peek();
-        if(value < '0' || value > '9'){
-            data[index++] = '\0';
-            return atoi(data);
-        }
-        data[index++] = _udp_ota.read();
+    if (_password.length()) {
+      MD5Builder nonce_md5;
+      nonce_md5.begin();
+      nonce_md5.add(String(micros()));
+      nonce_md5.calculate();
+      _nonce = nonce_md5.toString();
+
+      _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort());
+      _udp_ota.printf("AUTH %s", _nonce.c_str());
+      _udp_ota.endPacket();
+      _state = OTA_WAITAUTH;
+      return;
+    } else {
+      _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort());
+      _udp_ota.print("OK");
+      _udp_ota.endPacket();
+      _ota_ip = _udp_ota.remoteIP();
+      _state = OTA_RUNUPDATE;
     }
-    return 0;
-}
-
-String ArduinoOTAClass::readStringUntil(char end){
-    String res = "";
-    int value;
-    while(true){
-        value = _udp_ota.read();
-        if(value <= 0 || value == end){
-            return res;
-        }
-        res += (char)value;
+  } else if (_state == OTA_WAITAUTH) {
+    int cmd = parseInt();
+    if (cmd != U_AUTH) {
+      log_e("%d was expected. got %d instead", U_AUTH, cmd);
+      _state = OTA_IDLE;
+      return;
+    }
+    _udp_ota.read();
+    String cnonce = readStringUntil(' ');
+    String response = readStringUntil('\n');
+    if (cnonce.length() != 32 || response.length() != 32) {
+      log_e("auth param fail");
+      _state = OTA_IDLE;
+      return;
     }
-    return res;
-}
-
-void ArduinoOTAClass::_onRx(){
-    if (_state == OTA_IDLE) {
-        int cmd = parseInt();
-        if (cmd != U_FLASH && cmd != U_SPIFFS)
-            return;
-        _cmd  = cmd;
-        _ota_port = parseInt();
-        _size = parseInt();
-        _udp_ota.read();
-        _md5 = readStringUntil('\n');
-        _md5.trim();
-        if(_md5.length() != 32){
-            log_e("bad md5 length");
-            return;
-        }
-
-        if (_password.length()){
-            MD5Builder nonce_md5;
-            nonce_md5.begin();
-            nonce_md5.add(String(micros()));
-            nonce_md5.calculate();
-            _nonce = nonce_md5.toString();
-
-            _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort());
-            _udp_ota.printf("AUTH %s", _nonce.c_str());
-            _udp_ota.endPacket();
-            _state = OTA_WAITAUTH;
-            return;
-        } else {
-            _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort());
-            _udp_ota.print("OK");
-            _udp_ota.endPacket();
-            _ota_ip = _udp_ota.remoteIP();
-            _state = OTA_RUNUPDATE;
-        }
-    } else if (_state == OTA_WAITAUTH) {
-        int cmd = parseInt();
-        if (cmd != U_AUTH) {
-            log_e("%d was expected. got %d instead", U_AUTH, cmd);
-            _state = OTA_IDLE;
-            return;
-        }
-        _udp_ota.read();
-        String cnonce = readStringUntil(' ');
-        String response = readStringUntil('\n');
-        if (cnonce.length() != 32 || response.length() != 32) {
-            log_e("auth param fail");
-            _state = OTA_IDLE;
-            return;
-        }
 
-        String challenge = _password + ":" + String(_nonce) + ":" + cnonce;
-        MD5Builder _challengemd5;
-        _challengemd5.begin();
-        _challengemd5.add(challenge);
-        _challengemd5.calculate();
-        String result = _challengemd5.toString();
-
-        if(result.equals(response)){
-            _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort());
-            _udp_ota.print("OK");
-            _udp_ota.endPacket();
-            _ota_ip = _udp_ota.remoteIP();
-            _state = OTA_RUNUPDATE;
-        } else {
-            _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort());
-            _udp_ota.print("Authentication Failed");
-            log_w("Authentication Failed");
-            _udp_ota.endPacket();
-            if (_error_callback) _error_callback(OTA_AUTH_ERROR);
-            _state = OTA_IDLE;
-        }
+    String challenge = _password + ":" + String(_nonce) + ":" + cnonce;
+    MD5Builder _challengemd5;
+    _challengemd5.begin();
+    _challengemd5.add(challenge);
+    _challengemd5.calculate();
+    String result = _challengemd5.toString();
+
+    if (result.equals(response)) {
+      _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort());
+      _udp_ota.print("OK");
+      _udp_ota.endPacket();
+      _ota_ip = _udp_ota.remoteIP();
+      _state = OTA_RUNUPDATE;
+    } else {
+      _udp_ota.beginPacket(_udp_ota.remoteIP(), _udp_ota.remotePort());
+      _udp_ota.print("Authentication Failed");
+      log_w("Authentication Failed");
+      _udp_ota.endPacket();
+      if (_error_callback) {
+        _error_callback(OTA_AUTH_ERROR);
+      }
+      _state = OTA_IDLE;
     }
+  }
 }
 
 void ArduinoOTAClass::_runUpdate() {
-    const char *partition_label = _partition_label.length() ? _partition_label.c_str() : NULL;
-    if (!Update.begin(_size, _cmd, -1, LOW, partition_label)) {
+  const char *partition_label = _partition_label.length() ? _partition_label.c_str() : NULL;
+  if (!Update.begin(_size, _cmd, -1, LOW, partition_label)) {
 
-        log_e("Begin ERROR: %s", Update.errorString());
+    log_e("Begin ERROR: %s", Update.errorString());
 
-        if (_error_callback) {
-            _error_callback(OTA_BEGIN_ERROR);
-        }
-        _state = OTA_IDLE;
-        return;
+    if (_error_callback) {
+      _error_callback(OTA_BEGIN_ERROR);
     }
-    Update.setMD5(_md5.c_str());
-
-    if (_start_callback) {
-        _start_callback();
-    }
-    if (_progress_callback) {
-        _progress_callback(0, _size);
-    }
-
-    WiFiClient client;
-    if (!client.connect(_ota_ip, _ota_port)) {
-        if (_error_callback) {
-            _error_callback(OTA_CONNECT_ERROR);
-        }
-        _state = OTA_IDLE;
+    _state = OTA_IDLE;
+    return;
+  }
+  Update.setMD5(_md5.c_str());
+
+  if (_start_callback) {
+    _start_callback();
+  }
+  if (_progress_callback) {
+    _progress_callback(0, _size);
+  }
+
+  NetworkClient client;
+  if (!client.connect(_ota_ip, _ota_port)) {
+    if (_error_callback) {
+      _error_callback(OTA_CONNECT_ERROR);
     }
+    _state = OTA_IDLE;
+  }
 
-    uint32_t written = 0, total = 0, tried = 0;
-
-    while (!Update.isFinished() && client.connected()) {
-        size_t waited = _ota_timeout;
-        size_t available = client.available();
-        while (!available && waited){
-            delay(1);
-            waited -=1 ;
-            available = client.available();
-        }
-        if (!waited){
-            if(written && tried++ < 3){
-                log_i("Try[%u]: %u", tried, written);
-                if(!client.printf("%u", written)){
-                    log_e("failed to respond");
-                    _state = OTA_IDLE;
-                    break;
-                }
-                continue;
-            }
-            log_e("Receive Failed");
-            if (_error_callback) {
-                _error_callback(OTA_RECEIVE_ERROR);
-            }
-            _state = OTA_IDLE;
-            Update.abort();
-            return;
-        }
-        if(!available){
-            log_e("No Data: %u", waited);
-            _state = OTA_IDLE;
-            break;
-        }
-        tried = 0;
-        static uint8_t buf[1460];
-        if(available > 1460){
-            available = 1460;
-        }
-        size_t r = client.read(buf, available);
-        if(r != available){
-            log_w("didn't read enough! %u != %u", r, available);
-        }
+  uint32_t written = 0, total = 0, tried = 0;
 
-        written = Update.write(buf, r);
-        if (written > 0) {
-            if(written != r){
-                log_w("didn't write enough! %u != %u", written, r);
-            }
-            if(!client.printf("%u", written)){
-                log_w("failed to respond");
-            }
-            total += written;
-            if(_progress_callback) {
-                _progress_callback(total, _size);
-            }
-        } else {
-            log_e("Write ERROR: %s", Update.errorString());
+  while (!Update.isFinished() && client.connected()) {
+    size_t waited = _ota_timeout;
+    size_t available = client.available();
+    while (!available && waited) {
+      delay(1);
+      waited -= 1;
+      available = client.available();
+    }
+    if (!waited) {
+      if (written && tried++ < 3) {
+        log_i("Try[%u]: %u", tried, written);
+        if (!client.printf("%lu", written)) {
+          log_e("failed to respond");
+          _state = OTA_IDLE;
+          break;
         }
+        continue;
+      }
+      log_e("Receive Failed");
+      if (_error_callback) {
+        _error_callback(OTA_RECEIVE_ERROR);
+      }
+      _state = OTA_IDLE;
+      Update.abort();
+      return;
+    }
+    if (!available) {
+      log_e("No Data: %u", waited);
+      _state = OTA_IDLE;
+      break;
+    }
+    tried = 0;
+    static uint8_t buf[1460];
+    if (available > 1460) {
+      available = 1460;
+    }
+    size_t r = client.read(buf, available);
+    if (r != available) {
+      log_w("didn't read enough! %u != %u", r, available);
+      if ((int32_t)r < 0) {
+        delay(1);
+        continue;  //let's not try to write 4 gigabytes when client.read returns -1
+      }
     }
 
-    if (Update.end()) {
-        client.print("OK");
-        client.stop();
-        delay(10);
-        if (_end_callback) {
-            _end_callback();
-        }
-        if(_rebootOnSuccess){
-            //let serial/network finish tasks that might be given in _end_callback
-            delay(100);
-            ESP.restart();
-        }
+    written = Update.write(buf, r);
+    if (written > 0) {
+      if (written != r) {
+        log_w("didn't write enough! %u != %u", written, r);
+      }
+      if (!client.printf("%lu", written)) {
+        log_w("failed to respond");
+      }
+      total += written;
+      if (_progress_callback) {
+        _progress_callback(total, _size);
+      }
     } else {
-        if (_error_callback) {
-            _error_callback(OTA_END_ERROR);
-        }
-        Update.printError(client);
-        client.stop();
-        delay(10);
-        log_e("Update ERROR: %s", Update.errorString());
-        _state = OTA_IDLE;
+      log_e("Write ERROR: %s", Update.errorString());
     }
+  }
+
+  if (Update.end()) {
+    client.print("OK");
+    client.stop();
+    delay(10);
+    if (_end_callback) {
+      _end_callback();
+    }
+    if (_rebootOnSuccess) {
+      //let serial/network finish tasks that might be given in _end_callback
+      delay(100);
+      ESP.restart();
+    }
+  } else {
+    if (_error_callback) {
+      _error_callback(OTA_END_ERROR);
+    }
+    Update.printError(client);
+    client.stop();
+    delay(10);
+    log_e("Update ERROR: %s", Update.errorString());
+    _state = OTA_IDLE;
+  }
 }
 
 void ArduinoOTAClass::end() {
-    _initialized = false;
-    _udp_ota.stop();
-    if(_mdnsEnabled){
-        MDNS.end();
-    }
-    _state = OTA_IDLE;
-    log_i("OTA server stopped.");
+  _initialized = false;
+  _udp_ota.stop();
+#ifdef CONFIG_MDNS_MAX_INTERFACES
+  if (_mdnsEnabled) {
+    MDNS.end();
+  }
+#endif
+  _state = OTA_IDLE;
+  log_i("OTA server stopped.");
 }
 
 void ArduinoOTAClass::handle() {
-    if (!_initialized) {
-        return;
-    }
-    if (_state == OTA_RUNUPDATE) {
-        _runUpdate();
-        _state = OTA_IDLE;
-    }
-    if(_udp_ota.parsePacket()){
-        _onRx();
-    }
-    _udp_ota.flush(); // always flush, even zero length packets must be flushed.
+  if (!_initialized) {
+    return;
+  }
+  if (_state == OTA_RUNUPDATE) {
+    _runUpdate();
+    _state = OTA_IDLE;
+  }
+  if (_udp_ota.parsePacket()) {
+    _onRx();
+  }
+  _udp_ota.clear();  // always clear, even zero length packets must be cleared.
 }
 
 int ArduinoOTAClass::getCommand() {
-    return _cmd;
+  return _cmd;
 }
 
 void ArduinoOTAClass::setTimeout(int timeoutInMillis) {
-    _ota_timeout = timeoutInMillis;
+  _ota_timeout = timeoutInMillis;
 }
 
 #if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_ARDUINOOTA)
diff --git a/libraries/ArduinoOTA/src/ArduinoOTA.h b/libraries/ArduinoOTA/src/ArduinoOTA.h
index cd0ba05f547..7916e3b328d 100644
--- a/libraries/ArduinoOTA/src/ArduinoOTA.h
+++ b/libraries/ArduinoOTA/src/ArduinoOTA.h
@@ -1,9 +1,23 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
 #ifndef __ARDUINO_OTA_H
 #define __ARDUINO_OTA_H
 
-#include <WiFi.h>
-#include <functional>
+#include "Network.h"
 #include "Update.h"
+#include <functional>
 
 #define INT_BUFFER_SIZE 16
 
@@ -21,96 +35,95 @@ typedef enum {
   OTA_END_ERROR
 } ota_error_t;
 
-class ArduinoOTAClass
-{
-  public:
-    typedef std::function<void(void)> THandlerFunction;
-    typedef std::function<void(ota_error_t)> THandlerFunction_Error;
-    typedef std::function<void(unsigned int, unsigned int)> THandlerFunction_Progress;
+class ArduinoOTAClass {
+public:
+  typedef std::function<void(void)> THandlerFunction;
+  typedef std::function<void(ota_error_t)> THandlerFunction_Error;
+  typedef std::function<void(unsigned int, unsigned int)> THandlerFunction_Progress;
 
-    ArduinoOTAClass();
-    ~ArduinoOTAClass();
+  ArduinoOTAClass();
+  ~ArduinoOTAClass();
 
-    //Sets the service port. Default 3232
-    ArduinoOTAClass& setPort(uint16_t port);
+  //Sets the service port. Default 3232
+  ArduinoOTAClass &setPort(uint16_t port);
 
-    //Sets the device hostname. Default esp32-xxxxxx
-    ArduinoOTAClass& setHostname(const char *hostname);
-    String getHostname();
+  //Sets the device hostname. Default esp32-xxxxxx
+  ArduinoOTAClass &setHostname(const char *hostname);
+  String getHostname();
 
-    //Sets the password that will be required for OTA. Default NULL
-    ArduinoOTAClass& setPassword(const char *password);
+  //Sets the password that will be required for OTA. Default NULL
+  ArduinoOTAClass &setPassword(const char *password);
 
-    //Sets the password as above but in the form MD5(password). Default NULL
-    ArduinoOTAClass& setPasswordHash(const char *password);
+  //Sets the password as above but in the form MD5(password). Default NULL
+  ArduinoOTAClass &setPasswordHash(const char *password);
 
-    //Sets the partition label to write to when updating SPIFFS. Default NULL
-    ArduinoOTAClass &setPartitionLabel(const char *partition_label);
-    String getPartitionLabel();
+  //Sets the partition label to write to when updating SPIFFS. Default NULL
+  ArduinoOTAClass &setPartitionLabel(const char *partition_label);
+  String getPartitionLabel();
 
-    //Sets if the device should be rebooted after successful update. Default true
-    ArduinoOTAClass& setRebootOnSuccess(bool reboot);
+  //Sets if the device should be rebooted after successful update. Default true
+  ArduinoOTAClass &setRebootOnSuccess(bool reboot);
 
-    //Sets if the device should advertise itself to Arduino IDE. Default true
-    ArduinoOTAClass& setMdnsEnabled(bool enabled);
+  //Sets if the device should advertise itself to Arduino IDE. Default true
+  ArduinoOTAClass &setMdnsEnabled(bool enabled);
 
-    //This callback will be called when OTA connection has begun
-    ArduinoOTAClass& onStart(THandlerFunction fn);
+  //This callback will be called when OTA connection has begun
+  ArduinoOTAClass &onStart(THandlerFunction fn);
 
-    //This callback will be called when OTA has finished
-    ArduinoOTAClass& onEnd(THandlerFunction fn);
+  //This callback will be called when OTA has finished
+  ArduinoOTAClass &onEnd(THandlerFunction fn);
 
-    //This callback will be called when OTA encountered Error
-    ArduinoOTAClass& onError(THandlerFunction_Error fn);
+  //This callback will be called when OTA encountered Error
+  ArduinoOTAClass &onError(THandlerFunction_Error fn);
 
-    //This callback will be called when OTA is receiving data
-    ArduinoOTAClass& onProgress(THandlerFunction_Progress fn);
+  //This callback will be called when OTA is receiving data
+  ArduinoOTAClass &onProgress(THandlerFunction_Progress fn);
 
-    //Starts the ArduinoOTA service
-    void begin();
+  //Starts the ArduinoOTA service
+  void begin();
 
-    //Ends the ArduinoOTA service
-    void end();
+  //Ends the ArduinoOTA service
+  void end();
 
-    //Call this in loop() to run the service
-    void handle();
+  //Call this in loop() to run the service
+  void handle();
 
-    //Gets update command type after OTA has started. Either U_FLASH or U_SPIFFS
-    int getCommand();
+  //Gets update command type after OTA has started. Either U_FLASH or U_SPIFFS
+  int getCommand();
 
-    void setTimeout(int timeoutInMillis);
+  void setTimeout(int timeoutInMillis);
 
-  private:
-    int _port;
-    String _password;
-    String _hostname;
-    String _partition_label;
-    String _nonce;
-    WiFiUDP _udp_ota;
-    bool _initialized;
-    bool _rebootOnSuccess;
-    bool _mdnsEnabled;
-    ota_state_t _state;
-    int _size;
-    int _cmd;
-    int _ota_port;
-    int _ota_timeout;
-    IPAddress _ota_ip;
-    String _md5;
+private:
+  int _port;
+  String _password;
+  String _hostname;
+  String _partition_label;
+  String _nonce;
+  NetworkUDP _udp_ota;
+  bool _initialized;
+  bool _rebootOnSuccess;
+  bool _mdnsEnabled;
+  ota_state_t _state;
+  int _size;
+  int _cmd;
+  int _ota_port;
+  int _ota_timeout;
+  IPAddress _ota_ip;
+  String _md5;
 
-    THandlerFunction _start_callback;
-    THandlerFunction _end_callback;
-    THandlerFunction_Error _error_callback;
-    THandlerFunction_Progress _progress_callback;
+  THandlerFunction _start_callback;
+  THandlerFunction _end_callback;
+  THandlerFunction_Error _error_callback;
+  THandlerFunction_Progress _progress_callback;
 
-    void _runUpdate(void);
-    void _onRx(void);
-    int parseInt(void);
-    String readStringUntil(char end);
+  void _runUpdate(void);
+  void _onRx(void);
+  int parseInt(void);
+  String readStringUntil(char end);
 };
 
 #if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_ARDUINOOTA)
 extern ArduinoOTAClass ArduinoOTA;
 #endif
 
-#endif /* __ARDUINO_OTA_H */
\ No newline at end of file
+#endif /* __ARDUINO_OTA_H */
diff --git a/libraries/AsyncUDP/examples/AsyncUDPClient/AsyncUDPClient.ino b/libraries/AsyncUDP/examples/AsyncUDPClient/AsyncUDPClient.ino
index 3348f8a76a4..c842eab721d 100644
--- a/libraries/AsyncUDP/examples/AsyncUDPClient/AsyncUDPClient.ino
+++ b/libraries/AsyncUDP/examples/AsyncUDPClient/AsyncUDPClient.ino
@@ -1,51 +1,49 @@
 #include "WiFi.h"
 #include "AsyncUDP.h"
 
-const char * ssid = "***********";
-const char * password = "***********";
+const char *ssid = "***********";
+const char *password = "***********";
 
 AsyncUDP udp;
 
-void setup()
-{
-    Serial.begin(115200);
-    WiFi.mode(WIFI_STA);
-    WiFi.begin(ssid, password);
-    if (WiFi.waitForConnectResult() != WL_CONNECTED) {
-        Serial.println("WiFi Failed");
-        while(1) {
-            delay(1000);
-        }
-    }
-    if(udp.connect(IPAddress(192,168,1,100), 1234)) {
-        Serial.println("UDP connected");
-        udp.onPacket([](AsyncUDPPacket packet) {
-            Serial.print("UDP Packet Type: ");
-            Serial.print(packet.isBroadcast()?"Broadcast":packet.isMulticast()?"Multicast":"Unicast");
-            Serial.print(", From: ");
-            Serial.print(packet.remoteIP());
-            Serial.print(":");
-            Serial.print(packet.remotePort());
-            Serial.print(", To: ");
-            Serial.print(packet.localIP());
-            Serial.print(":");
-            Serial.print(packet.localPort());
-            Serial.print(", Length: ");
-            Serial.print(packet.length());
-            Serial.print(", Data: ");
-            Serial.write(packet.data(), packet.length());
-            Serial.println();
-            //reply to the client
-            packet.printf("Got %u bytes of data", packet.length());
-        });
-        //Send unicast
-        udp.print("Hello Server!");
+void setup() {
+  Serial.begin(115200);
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(ssid, password);
+  if (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("WiFi Failed");
+    while (1) {
+      delay(1000);
     }
+  }
+  if (udp.connect(IPAddress(192, 168, 1, 100), 1234)) {
+    Serial.println("UDP connected");
+    udp.onPacket([](AsyncUDPPacket packet) {
+      Serial.print("UDP Packet Type: ");
+      Serial.print(packet.isBroadcast() ? "Broadcast" : packet.isMulticast() ? "Multicast" : "Unicast");
+      Serial.print(", From: ");
+      Serial.print(packet.remoteIP());
+      Serial.print(":");
+      Serial.print(packet.remotePort());
+      Serial.print(", To: ");
+      Serial.print(packet.localIP());
+      Serial.print(":");
+      Serial.print(packet.localPort());
+      Serial.print(", Length: ");
+      Serial.print(packet.length());
+      Serial.print(", Data: ");
+      Serial.write(packet.data(), packet.length());
+      Serial.println();
+      //reply to the client
+      packet.printf("Got %u bytes of data", packet.length());
+    });
+    //Send unicast
+    udp.print("Hello Server!");
+  }
 }
 
-void loop()
-{
-    delay(1000);
-    //Send broadcast on port 1234
-    udp.broadcastTo("Anyone here?", 1234);
+void loop() {
+  delay(1000);
+  //Send broadcast on port 1234
+  udp.broadcastTo("Anyone here?", 1234);
 }
diff --git a/libraries/AsyncUDP/examples/AsyncUDPClient/ci.json b/libraries/AsyncUDP/examples/AsyncUDPClient/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/AsyncUDP/examples/AsyncUDPClient/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/AsyncUDPMulticastServer.ino b/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/AsyncUDPMulticastServer.ino
index 2bbbac51c4d..0da2f1f00e4 100644
--- a/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/AsyncUDPMulticastServer.ino
+++ b/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/AsyncUDPMulticastServer.ino
@@ -1,52 +1,50 @@
 #include "WiFi.h"
 #include "AsyncUDP.h"
 
-const char * ssid = "***********";
-const char * password = "***********";
+const char *ssid = "***********";
+const char *password = "***********";
 
 AsyncUDP udp;
 
-void setup()
-{
-    Serial.begin(115200);
-    WiFi.mode(WIFI_STA);
-    WiFi.begin(ssid, password);
-    if (WiFi.waitForConnectResult() != WL_CONNECTED) {
-        Serial.println("WiFi Failed");
-        while(1) {
-            delay(1000);
-        }
-    }
-    if(udp.listenMulticast(IPAddress(239,1,2,3), 1234)) {
-        Serial.print("UDP Listening on IP: ");
-        Serial.println(WiFi.localIP());
-        udp.onPacket([](AsyncUDPPacket packet) {
-            Serial.print("UDP Packet Type: ");
-            Serial.print(packet.isBroadcast()?"Broadcast":packet.isMulticast()?"Multicast":"Unicast");
-            Serial.print(", From: ");
-            Serial.print(packet.remoteIP());
-            Serial.print(":");
-            Serial.print(packet.remotePort());
-            Serial.print(", To: ");
-            Serial.print(packet.localIP());
-            Serial.print(":");
-            Serial.print(packet.localPort());
-            Serial.print(", Length: ");
-            Serial.print(packet.length());
-            Serial.print(", Data: ");
-            Serial.write(packet.data(), packet.length());
-            Serial.println();
-            //reply to the client
-            packet.printf("Got %u bytes of data", packet.length());
-        });
-        //Send multicast
-        udp.print("Hello!");
+void setup() {
+  Serial.begin(115200);
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(ssid, password);
+  if (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("WiFi Failed");
+    while (1) {
+      delay(1000);
     }
+  }
+  if (udp.listenMulticast(IPAddress(239, 1, 2, 3), 1234)) {
+    Serial.print("UDP Listening on IP: ");
+    Serial.println(WiFi.localIP());
+    udp.onPacket([](AsyncUDPPacket packet) {
+      Serial.print("UDP Packet Type: ");
+      Serial.print(packet.isBroadcast() ? "Broadcast" : packet.isMulticast() ? "Multicast" : "Unicast");
+      Serial.print(", From: ");
+      Serial.print(packet.remoteIP());
+      Serial.print(":");
+      Serial.print(packet.remotePort());
+      Serial.print(", To: ");
+      Serial.print(packet.localIP());
+      Serial.print(":");
+      Serial.print(packet.localPort());
+      Serial.print(", Length: ");
+      Serial.print(packet.length());
+      Serial.print(", Data: ");
+      Serial.write(packet.data(), packet.length());
+      Serial.println();
+      //reply to the client
+      packet.printf("Got %u bytes of data", packet.length());
+    });
+    //Send multicast
+    udp.print("Hello!");
+  }
 }
 
-void loop()
-{
-    delay(1000);
-    //Send multicast
-    udp.print("Anyone here?");
+void loop() {
+  delay(1000);
+  //Send multicast
+  udp.print("Anyone here?");
 }
diff --git a/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/ci.json b/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/AsyncUDP/examples/AsyncUDPMulticastServer/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/AsyncUDP/examples/AsyncUDPServer/AsyncUDPServer.ino b/libraries/AsyncUDP/examples/AsyncUDPServer/AsyncUDPServer.ino
index 1f8529bd51d..18cd66a5d44 100644
--- a/libraries/AsyncUDP/examples/AsyncUDPServer/AsyncUDPServer.ino
+++ b/libraries/AsyncUDP/examples/AsyncUDPServer/AsyncUDPServer.ino
@@ -1,50 +1,48 @@
 #include "WiFi.h"
 #include "AsyncUDP.h"
 
-const char * ssid = "***********";
-const char * password = "***********";
+const char *ssid = "***********";
+const char *password = "***********";
 
 AsyncUDP udp;
 
-void setup()
-{
-    Serial.begin(115200);
-    WiFi.mode(WIFI_STA);
-    WiFi.begin(ssid, password);
-    if (WiFi.waitForConnectResult() != WL_CONNECTED) {
-        Serial.println("WiFi Failed");
-        while(1) {
-            delay(1000);
-        }
-    }
-    if(udp.listen(1234)) {
-        Serial.print("UDP Listening on IP: ");
-        Serial.println(WiFi.localIP());
-        udp.onPacket([](AsyncUDPPacket packet) {
-            Serial.print("UDP Packet Type: ");
-            Serial.print(packet.isBroadcast()?"Broadcast":packet.isMulticast()?"Multicast":"Unicast");
-            Serial.print(", From: ");
-            Serial.print(packet.remoteIP());
-            Serial.print(":");
-            Serial.print(packet.remotePort());
-            Serial.print(", To: ");
-            Serial.print(packet.localIP());
-            Serial.print(":");
-            Serial.print(packet.localPort());
-            Serial.print(", Length: ");
-            Serial.print(packet.length());
-            Serial.print(", Data: ");
-            Serial.write(packet.data(), packet.length());
-            Serial.println();
-            //reply to the client
-            packet.printf("Got %u bytes of data", packet.length());
-        });
+void setup() {
+  Serial.begin(115200);
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(ssid, password);
+  if (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("WiFi Failed");
+    while (1) {
+      delay(1000);
     }
+  }
+  if (udp.listen(1234)) {
+    Serial.print("UDP Listening on IP: ");
+    Serial.println(WiFi.localIP());
+    udp.onPacket([](AsyncUDPPacket packet) {
+      Serial.print("UDP Packet Type: ");
+      Serial.print(packet.isBroadcast() ? "Broadcast" : packet.isMulticast() ? "Multicast" : "Unicast");
+      Serial.print(", From: ");
+      Serial.print(packet.remoteIP());
+      Serial.print(":");
+      Serial.print(packet.remotePort());
+      Serial.print(", To: ");
+      Serial.print(packet.localIP());
+      Serial.print(":");
+      Serial.print(packet.localPort());
+      Serial.print(", Length: ");
+      Serial.print(packet.length());
+      Serial.print(", Data: ");
+      Serial.write(packet.data(), packet.length());
+      Serial.println();
+      //reply to the client
+      packet.printf("Got %u bytes of data", packet.length());
+    });
+  }
 }
 
-void loop()
-{
-    delay(1000);
-    //Send broadcast
-    udp.broadcast("Anyone here?");
+void loop() {
+  delay(1000);
+  //Send broadcast
+  udp.broadcast("Anyone here?");
 }
diff --git a/libraries/AsyncUDP/examples/AsyncUDPServer/ci.json b/libraries/AsyncUDP/examples/AsyncUDPServer/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/AsyncUDP/examples/AsyncUDPServer/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/AsyncUDP/keywords.txt b/libraries/AsyncUDP/keywords.txt
index 67c0b97a715..1401ea66c72 100644
--- a/libraries/AsyncUDP/keywords.txt
+++ b/libraries/AsyncUDP/keywords.txt
@@ -8,6 +8,7 @@
 
 AsyncUDP	KEYWORD1
 AsyncUDPPacket	KEYWORD1
+AsyncUDPMessage	KEYWORD1
 
 #######################################
 # Methods and Functions (KEYWORD2)
@@ -19,6 +20,21 @@ listen	KEYWORD2
 listenMulticast	KEYWORD2
 close	KEYWORD2
 write	KEYWORD2
+space	KEYWORD2
+flush	KEYWORD2
+isBroadcast	KEYWORD2
+isMulticast	KEYWORD2
+isIPv6	KEYWORD2
+interface	KEYWORD2
+localIPv6	KEYWORD2
+remoteIPv6	KEYWORD2
+remoteMac	KEYWORD2
+send	KEYWORD2
+peek	KEYWORD2
+available	KEYWORD2
+writeTo	KEYWORD2
+broadcastTo	KEYWORD2
+sendTo	KEYWORD2
 broadcast	KEYWORD2
 onPacket	KEYWORD2
 data	KEYWORD2
@@ -27,7 +43,17 @@ localIP	KEYWORD2
 localPort	KEYWORD2
 remoteIP	KEYWORD2
 remotePort	KEYWORD2
+listenIP	KEYWORD2
+listenIPv6	KEYWORD2
+lastErr	KEYWORD2
+_s_recv	KEYWORD2
 
 #######################################
 # Constants (LITERAL1)
 #######################################
+
+TCPIP_ADAPTER_IF_STA	LITERAL1
+TCPIP_ADAPTER_IF_STA	LITERAL1
+TCPIP_ADAPTER_IF_AP	LITERAL1
+TCPIP_ADAPTER_IF_ETH	LITERAL1
+TCPIP_ADAPTER_IF_PPP	LITERAL1
diff --git a/libraries/AsyncUDP/library.properties b/libraries/AsyncUDP/library.properties
index 95a5e148d2f..116dcbacaa8 100644
--- a/libraries/AsyncUDP/library.properties
+++ b/libraries/AsyncUDP/library.properties
@@ -1,5 +1,5 @@
 name=ESP32 Async UDP
-version=1.0.0
+version=3.2.0
 author=Me-No-Dev
 maintainer=Me-No-Dev
 sentence=Async UDP Library for ESP32
diff --git a/libraries/AsyncUDP/src/AsyncUDP.cpp b/libraries/AsyncUDP/src/AsyncUDP.cpp
index ea2fc04e744..f44cc839c97 100644
--- a/libraries/AsyncUDP/src/AsyncUDP.cpp
+++ b/libraries/AsyncUDP/src/AsyncUDP.cpp
@@ -15,181 +15,218 @@ extern "C" {
 
 #include "lwip/priv/tcpip_priv.h"
 
+#ifdef CONFIG_LWIP_TCPIP_CORE_LOCKING
+#define UDP_MUTEX_LOCK()                                \
+  if (!sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) { \
+    LOCK_TCPIP_CORE();                                  \
+  }
+
+#define UDP_MUTEX_UNLOCK()                             \
+  if (sys_thread_tcpip(LWIP_CORE_LOCK_QUERY_HOLDER)) { \
+    UNLOCK_TCPIP_CORE();                               \
+  }
+#else  // CONFIG_LWIP_TCPIP_CORE_LOCKING
+#define UDP_MUTEX_LOCK()
+#define UDP_MUTEX_UNLOCK()
+#endif  // CONFIG_LWIP_TCPIP_CORE_LOCKING
+
+static const char *netif_ifkeys[TCPIP_ADAPTER_IF_MAX] = {"WIFI_STA_DEF", "WIFI_AP_DEF", "ETH_DEF", "PPP_DEF"};
+
+static esp_err_t tcpip_adapter_get_netif(tcpip_adapter_if_t tcpip_if, void **netif) {
+  *netif = NULL;
+  if (tcpip_if < TCPIP_ADAPTER_IF_MAX) {
+    esp_netif_t *esp_netif = esp_netif_get_handle_from_ifkey(netif_ifkeys[tcpip_if]);
+    if (esp_netif == NULL) {
+      return ESP_FAIL;
+    }
+    int netif_index = esp_netif_get_netif_impl_index(esp_netif);
+    if (netif_index < 0) {
+      return ESP_FAIL;
+    }
+    UDP_MUTEX_LOCK();
+    *netif = (void *)netif_get_by_index(netif_index);
+    UDP_MUTEX_UNLOCK();
+  } else {
+    *netif = netif_default;
+  }
+  return (*netif != NULL) ? ESP_OK : ESP_FAIL;
+}
+
 typedef struct {
-    struct tcpip_api_call_data call;
-    udp_pcb * pcb;
-    const ip_addr_t *addr;
-    uint16_t port;
-    struct pbuf *pb;
-    struct netif *netif;
-    err_t err;
+  struct tcpip_api_call_data call;
+  udp_pcb *pcb;
+  const ip_addr_t *addr;
+  uint16_t port;
+  struct pbuf *pb;
+  struct netif *netif;
+  err_t err;
 } udp_api_call_t;
 
-static err_t _udp_connect_api(struct tcpip_api_call_data *api_call_msg){
-    udp_api_call_t * msg = (udp_api_call_t *)api_call_msg;
-    msg->err = udp_connect(msg->pcb, msg->addr, msg->port);
-    return msg->err;
+static err_t _udp_connect_api(struct tcpip_api_call_data *api_call_msg) {
+  udp_api_call_t *msg = (udp_api_call_t *)api_call_msg;
+  msg->err = udp_connect(msg->pcb, msg->addr, msg->port);
+  return msg->err;
 }
 
-static err_t _udp_connect(struct udp_pcb *pcb, const ip_addr_t *addr, u16_t port){
-    udp_api_call_t msg;
-    msg.pcb = pcb;
-    msg.addr = addr;
-    msg.port = port;
-    tcpip_api_call(_udp_connect_api, (struct tcpip_api_call_data*)&msg);
-    return msg.err;
+static err_t _udp_connect(struct udp_pcb *pcb, const ip_addr_t *addr, u16_t port) {
+  udp_api_call_t msg;
+  msg.pcb = pcb;
+  msg.addr = addr;
+  msg.port = port;
+  tcpip_api_call(_udp_connect_api, (struct tcpip_api_call_data *)&msg);
+  return msg.err;
 }
 
-static err_t _udp_disconnect_api(struct tcpip_api_call_data *api_call_msg){
-    udp_api_call_t * msg = (udp_api_call_t *)api_call_msg;
-    msg->err = 0;
-    udp_disconnect(msg->pcb);
-    return msg->err;
+static err_t _udp_disconnect_api(struct tcpip_api_call_data *api_call_msg) {
+  udp_api_call_t *msg = (udp_api_call_t *)api_call_msg;
+  msg->err = 0;
+  udp_disconnect(msg->pcb);
+  return msg->err;
 }
 
-static void  _udp_disconnect(struct udp_pcb *pcb){
-    udp_api_call_t msg;
-    msg.pcb = pcb;
-    tcpip_api_call(_udp_disconnect_api, (struct tcpip_api_call_data*)&msg);
+static void _udp_disconnect(struct udp_pcb *pcb) {
+  udp_api_call_t msg;
+  msg.pcb = pcb;
+  tcpip_api_call(_udp_disconnect_api, (struct tcpip_api_call_data *)&msg);
 }
 
-static err_t _udp_remove_api(struct tcpip_api_call_data *api_call_msg){
-    udp_api_call_t * msg = (udp_api_call_t *)api_call_msg;
-    msg->err = 0;
-    udp_remove(msg->pcb);
-    return msg->err;
+static err_t _udp_remove_api(struct tcpip_api_call_data *api_call_msg) {
+  udp_api_call_t *msg = (udp_api_call_t *)api_call_msg;
+  msg->err = 0;
+  udp_remove(msg->pcb);
+  return msg->err;
 }
 
-static void  _udp_remove(struct udp_pcb *pcb){
-    udp_api_call_t msg;
-    msg.pcb = pcb;
-    tcpip_api_call(_udp_remove_api, (struct tcpip_api_call_data*)&msg);
+static void _udp_remove(struct udp_pcb *pcb) {
+  udp_api_call_t msg;
+  msg.pcb = pcb;
+  tcpip_api_call(_udp_remove_api, (struct tcpip_api_call_data *)&msg);
 }
 
-static err_t _udp_bind_api(struct tcpip_api_call_data *api_call_msg){
-    udp_api_call_t * msg = (udp_api_call_t *)api_call_msg;
-    msg->err = udp_bind(msg->pcb, msg->addr, msg->port);
-    return msg->err;
+static err_t _udp_bind_api(struct tcpip_api_call_data *api_call_msg) {
+  udp_api_call_t *msg = (udp_api_call_t *)api_call_msg;
+  msg->err = udp_bind(msg->pcb, msg->addr, msg->port);
+  return msg->err;
 }
 
-static err_t _udp_bind(struct udp_pcb *pcb, const ip_addr_t *addr, u16_t port){
-    udp_api_call_t msg;
-    msg.pcb = pcb;
-    msg.addr = addr;
-    msg.port = port;
-    tcpip_api_call(_udp_bind_api, (struct tcpip_api_call_data*)&msg);
-    return msg.err;
+static err_t _udp_bind(struct udp_pcb *pcb, const ip_addr_t *addr, u16_t port) {
+  udp_api_call_t msg;
+  msg.pcb = pcb;
+  msg.addr = addr;
+  msg.port = port;
+  tcpip_api_call(_udp_bind_api, (struct tcpip_api_call_data *)&msg);
+  return msg.err;
 }
 
-static err_t _udp_sendto_api(struct tcpip_api_call_data *api_call_msg){
-    udp_api_call_t * msg = (udp_api_call_t *)api_call_msg;
-    msg->err = udp_sendto(msg->pcb, msg->pb, msg->addr, msg->port);
-    return msg->err;
+static err_t _udp_sendto_api(struct tcpip_api_call_data *api_call_msg) {
+  udp_api_call_t *msg = (udp_api_call_t *)api_call_msg;
+  msg->err = udp_sendto(msg->pcb, msg->pb, msg->addr, msg->port);
+  return msg->err;
 }
 
-static err_t _udp_sendto(struct udp_pcb *pcb, struct pbuf *pb, const ip_addr_t *addr, u16_t port){
-    udp_api_call_t msg;
-    msg.pcb = pcb;
-    msg.addr = addr;
-    msg.port = port;
-    msg.pb = pb;
-    tcpip_api_call(_udp_sendto_api, (struct tcpip_api_call_data*)&msg);
-    return msg.err;
+static err_t _udp_sendto(struct udp_pcb *pcb, struct pbuf *pb, const ip_addr_t *addr, u16_t port) {
+  udp_api_call_t msg;
+  msg.pcb = pcb;
+  msg.addr = addr;
+  msg.port = port;
+  msg.pb = pb;
+  tcpip_api_call(_udp_sendto_api, (struct tcpip_api_call_data *)&msg);
+  return msg.err;
 }
 
-static err_t _udp_sendto_if_api(struct tcpip_api_call_data *api_call_msg){
-    udp_api_call_t * msg = (udp_api_call_t *)api_call_msg;
-    msg->err = udp_sendto_if(msg->pcb, msg->pb, msg->addr, msg->port, msg->netif);
-    return msg->err;
+static err_t _udp_sendto_if_api(struct tcpip_api_call_data *api_call_msg) {
+  udp_api_call_t *msg = (udp_api_call_t *)api_call_msg;
+  msg->err = udp_sendto_if(msg->pcb, msg->pb, msg->addr, msg->port, msg->netif);
+  return msg->err;
 }
 
-static err_t _udp_sendto_if(struct udp_pcb *pcb, struct pbuf *pb, const ip_addr_t *addr, u16_t port, struct netif *netif){
-    udp_api_call_t msg;
-    msg.pcb = pcb;
-    msg.addr = addr;
-    msg.port = port;
-    msg.pb = pb;
-    msg.netif = netif;
-    tcpip_api_call(_udp_sendto_if_api, (struct tcpip_api_call_data*)&msg);
-    return msg.err;
+static err_t _udp_sendto_if(struct udp_pcb *pcb, struct pbuf *pb, const ip_addr_t *addr, u16_t port, struct netif *netif) {
+  udp_api_call_t msg;
+  msg.pcb = pcb;
+  msg.addr = addr;
+  msg.port = port;
+  msg.pb = pb;
+  msg.netif = netif;
+  tcpip_api_call(_udp_sendto_if_api, (struct tcpip_api_call_data *)&msg);
+  return msg.err;
 }
 
 typedef struct {
-        void *arg;
-        udp_pcb *pcb;
-        pbuf *pb;
-        const ip_addr_t *addr;
-        uint16_t port;
-        struct netif * netif;
+  void *arg;
+  udp_pcb *pcb;
+  pbuf *pb;
+  const ip_addr_t *addr;
+  uint16_t port;
+  struct netif *netif;
 } lwip_event_packet_t;
 
-static xQueueHandle _udp_queue;
+static QueueHandle_t _udp_queue;
 static volatile TaskHandle_t _udp_task_handle = NULL;
 
-static void _udp_task(void *pvParameters){
-    lwip_event_packet_t * e = NULL;
-    for (;;) {
-        if(xQueueReceive(_udp_queue, &e, portMAX_DELAY) == pdTRUE){
-            if(!e->pb){
-                free((void*)(e));
-                continue;
-            }
-            AsyncUDP::_s_recv(e->arg, e->pcb, e->pb, e->addr, e->port, e->netif);
-            free((void*)(e));
-        }
-    }
-    _udp_task_handle = NULL;
-    vTaskDelete(NULL);
-}
-
-static bool _udp_task_start(){
-    if(!_udp_queue){
-        _udp_queue = xQueueCreate(32, sizeof(lwip_event_packet_t *));
-        if(!_udp_queue){
-            return false;
-        }
-    }
-    if(!_udp_task_handle){
-        xTaskCreateUniversal(_udp_task, "async_udp", 4096, NULL, CONFIG_ARDUINO_UDP_TASK_PRIORITY, (TaskHandle_t*)&_udp_task_handle, CONFIG_ARDUINO_UDP_RUNNING_CORE);
-        if(!_udp_task_handle){
-            return false;
-        }
-    }
-    return true;
-}
-
-static bool _udp_task_post(void *arg, udp_pcb *pcb, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif *netif)
-{
-    if(!_udp_task_handle || !_udp_queue){
-        return false;
-    }
-    lwip_event_packet_t * e = (lwip_event_packet_t *)malloc(sizeof(lwip_event_packet_t));
-    if(!e){
-        return false;
-    }
-    e->arg = arg;
-    e->pcb = pcb;
-    e->pb = pb;
-    e->addr = addr;
-    e->port = port;
-    e->netif = netif;
-    if (xQueueSend(_udp_queue, &e, portMAX_DELAY) != pdPASS) {
-        free((void*)(e));
-        return false;
-    }
-    return true;
-}
-
-static void _udp_recv(void *arg, udp_pcb *pcb, pbuf *pb, const ip_addr_t *addr, uint16_t port)
-{
-    while(pb != NULL) {
-        pbuf * this_pb = pb;
-        pb = pb->next;
-        this_pb->next = NULL;
-        if(!_udp_task_post(arg, pcb, this_pb, addr, port, ip_current_input_netif())){
-            pbuf_free(this_pb);
-        }
-    }
+static void _udp_task(void *pvParameters) {
+  lwip_event_packet_t *e = NULL;
+  for (;;) {
+    if (xQueueReceive(_udp_queue, &e, portMAX_DELAY) == pdTRUE) {
+      if (!e->pb) {
+        free((void *)(e));
+        continue;
+      }
+      AsyncUDP::_s_recv(e->arg, e->pcb, e->pb, e->addr, e->port, e->netif);
+      free((void *)(e));
+    }
+  }
+  _udp_task_handle = NULL;
+  vTaskDelete(NULL);
+}
+
+static bool _udp_task_start() {
+  if (!_udp_queue) {
+    _udp_queue = xQueueCreate(32, sizeof(lwip_event_packet_t *));
+    if (!_udp_queue) {
+      return false;
+    }
+  }
+  if (!_udp_task_handle) {
+    xTaskCreateUniversal(
+      _udp_task, "async_udp", 4096, NULL, CONFIG_ARDUINO_UDP_TASK_PRIORITY, (TaskHandle_t *)&_udp_task_handle, CONFIG_ARDUINO_UDP_RUNNING_CORE
+    );
+    if (!_udp_task_handle) {
+      return false;
+    }
+  }
+  return true;
+}
+
+static bool _udp_task_post(void *arg, udp_pcb *pcb, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif *netif) {
+  if (!_udp_task_handle || !_udp_queue) {
+    return false;
+  }
+  lwip_event_packet_t *e = (lwip_event_packet_t *)malloc(sizeof(lwip_event_packet_t));
+  if (!e) {
+    return false;
+  }
+  e->arg = arg;
+  e->pcb = pcb;
+  e->pb = pb;
+  e->addr = addr;
+  e->port = port;
+  e->netif = netif;
+  if (xQueueSend(_udp_queue, &e, portMAX_DELAY) != pdPASS) {
+    free((void *)(e));
+    return false;
+  }
+  return true;
+}
+
+static void _udp_recv(void *arg, udp_pcb *pcb, pbuf *pb, const ip_addr_t *addr, uint16_t port) {
+  while (pb != NULL) {
+    pbuf *this_pb = pb;
+    pb = pb->next;
+    this_pb->next = NULL;
+    if (!_udp_task_post(arg, pcb, this_pb, addr, port, ip_current_input_netif())) {
+      pbuf_free(this_pb);
+    }
+  }
 }
 /*
 static bool _udp_task_stop(){
@@ -212,670 +249,639 @@ static bool _udp_task_stop(){
 }
 */
 
+AsyncUDPMessage::AsyncUDPMessage(size_t size) {
+  _index = 0;
+  if (size > CONFIG_TCP_MSS) {
+    size = CONFIG_TCP_MSS;
+  }
+  _size = size;
+  _buffer = (uint8_t *)malloc(size);
+}
 
-
-#define UDP_MUTEX_LOCK()    //xSemaphoreTake(_lock, portMAX_DELAY)
-#define UDP_MUTEX_UNLOCK()  //xSemaphoreGive(_lock)
-
-
-AsyncUDPMessage::AsyncUDPMessage(size_t size)
-{
-    _index = 0;
-    if(size > CONFIG_TCP_MSS) {
-        size = CONFIG_TCP_MSS;
-    }
-    _size = size;
-    _buffer = (uint8_t *)malloc(size);
+AsyncUDPMessage::~AsyncUDPMessage() {
+  if (_buffer) {
+    free(_buffer);
+  }
 }
 
-AsyncUDPMessage::~AsyncUDPMessage()
-{
-    if(_buffer) {
-        free(_buffer);
-    }
+size_t AsyncUDPMessage::write(const uint8_t *data, size_t len) {
+  if (_buffer == NULL) {
+    return 0;
+  }
+  size_t s = space();
+  if (len > s) {
+    len = s;
+  }
+  memcpy(_buffer + _index, data, len);
+  _index += len;
+  return len;
 }
 
-size_t AsyncUDPMessage::write(const uint8_t *data, size_t len)
-{
-    if(_buffer == NULL) {
-        return 0;
-    }
-    size_t s = space();
-    if(len > s) {
-        len = s;
-    }
-    memcpy(_buffer + _index, data, len);
-    _index += len;
-    return len;
+size_t AsyncUDPMessage::write(uint8_t data) {
+  return write(&data, 1);
 }
 
-size_t AsyncUDPMessage::write(uint8_t data)
-{
-    return write(&data, 1);
+size_t AsyncUDPMessage::space() {
+  if (_buffer == NULL) {
+    return 0;
+  }
+  return _size - _index;
 }
 
-size_t AsyncUDPMessage::space()
-{
-    if(_buffer == NULL) {
-        return 0;
-    }
-    return _size - _index;
+uint8_t *AsyncUDPMessage::data() {
+  return _buffer;
 }
 
-uint8_t * AsyncUDPMessage::data()
-{
-    return _buffer;
+size_t AsyncUDPMessage::length() {
+  return _index;
 }
 
-size_t AsyncUDPMessage::length()
-{
-    return _index;
+void AsyncUDPMessage::flush() {
+  _index = 0;
 }
 
-void AsyncUDPMessage::flush()
-{
-    _index = 0;
+AsyncUDPPacket::AsyncUDPPacket(AsyncUDPPacket &packet) {
+  _udp = packet._udp;
+  _pb = packet._pb;
+  _if = packet._if;
+  _data = packet._data;
+  _len = packet._len;
+  _index = 0;
+
+  memcpy(&_remoteIp, &packet._remoteIp, sizeof(ip_addr_t));
+  memcpy(&_localIp, &packet._localIp, sizeof(ip_addr_t));
+  _localPort = packet._localPort;
+  _remotePort = packet._remotePort;
+  memcpy(_remoteMac, packet._remoteMac, 6);
+
+  pbuf_ref(_pb);
 }
 
+AsyncUDPPacket::AsyncUDPPacket(AsyncUDP *udp, pbuf *pb, const ip_addr_t *raddr, uint16_t rport, struct netif *ntif) {
+  _udp = udp;
+  _pb = pb;
+  _if = TCPIP_ADAPTER_IF_MAX;
+  _data = (uint8_t *)(pb->payload);
+  _len = pb->len;
+  _index = 0;
 
-AsyncUDPPacket::AsyncUDPPacket(AsyncUDP *udp, pbuf *pb, const ip_addr_t *raddr, uint16_t rport, struct netif * ntif)
-{
-    _udp = udp;
-    _pb = pb;
-    _if = TCPIP_ADAPTER_IF_MAX;
-    _data = (uint8_t*)(pb->payload);
-    _len = pb->len;
-    _index = 0;
+  pbuf_ref(_pb);
 
-    pbuf_ref(_pb);
+  //memcpy(&_remoteIp, raddr, sizeof(ip_addr_t));
+#if CONFIG_LWIP_IPV6
+  _remoteIp.type = raddr->type;
+  _localIp.type = _remoteIp.type;
+#endif
 
-    //memcpy(&_remoteIp, raddr, sizeof(ip_addr_t));
-    _remoteIp.type = raddr->type;
-    _localIp.type = _remoteIp.type;
+  eth_hdr *eth = NULL;
+  udp_hdr *udphdr = (udp_hdr *)(_data - UDP_HLEN);
+  _localPort = ntohs(udphdr->dest);
+  _remotePort = ntohs(udphdr->src);
 
-    eth_hdr* eth = NULL;
-    udp_hdr* udphdr = reinterpret_cast<udp_hdr*>(_data - UDP_HLEN);
-    _localPort = ntohs(udphdr->dest);
-    _remotePort = ntohs(udphdr->src);
+#if CONFIG_LWIP_IPV6
+  if (_remoteIp.type == IPADDR_TYPE_V4) {
+#endif
+    eth = (eth_hdr *)(_data - UDP_HLEN - IP_HLEN - SIZEOF_ETH_HDR);
+    struct ip_hdr *iphdr = (struct ip_hdr *)(_data - UDP_HLEN - IP_HLEN);
+#if CONFIG_LWIP_IPV6
+    _localIp.u_addr.ip4.addr = iphdr->dest.addr;
+    _remoteIp.u_addr.ip4.addr = iphdr->src.addr;
+#else
+  _localIp.addr = iphdr->dest.addr;
+  _remoteIp.addr = iphdr->src.addr;
+#endif
+#if CONFIG_LWIP_IPV6
+  } else {
+    eth = (eth_hdr *)(_data - UDP_HLEN - IP6_HLEN - SIZEOF_ETH_HDR);
+    struct ip6_hdr *ip6hdr = (struct ip6_hdr *)(_data - UDP_HLEN - IP6_HLEN);
+    memcpy(&_localIp.u_addr.ip6.addr, (uint8_t *)ip6hdr->dest.addr, 16);
+    memcpy(&_remoteIp.u_addr.ip6.addr, (uint8_t *)ip6hdr->src.addr, 16);
+  }
+#endif
+  memcpy(_remoteMac, eth->src.addr, 6);
 
-    if (_remoteIp.type == IPADDR_TYPE_V4) {
-        eth = (eth_hdr *)(((uint8_t *)(pb->payload)) - UDP_HLEN - IP_HLEN - SIZEOF_ETH_HDR);
-        struct ip_hdr * iphdr = (struct ip_hdr *)(((uint8_t *)(pb->payload)) - UDP_HLEN - IP_HLEN);
-        _localIp.u_addr.ip4.addr = iphdr->dest.addr;
-        _remoteIp.u_addr.ip4.addr = iphdr->src.addr;
-    } else {
-        eth = (eth_hdr *)(((uint8_t *)(pb->payload)) - UDP_HLEN - IP6_HLEN - SIZEOF_ETH_HDR);
-        struct ip6_hdr * ip6hdr = (struct ip6_hdr *)(((uint8_t *)(pb->payload)) - UDP_HLEN - IP6_HLEN);
-        memcpy(&_localIp.u_addr.ip6.addr, (uint8_t *)ip6hdr->dest.addr, 16);
-        memcpy(&_remoteIp.u_addr.ip6.addr, (uint8_t *)ip6hdr->src.addr, 16);
-    }
-    memcpy(_remoteMac, eth->src.addr, 6);
-
-    struct netif * netif = NULL;
-    void * nif = NULL;
-    int i;
-    for (i=0; i<TCPIP_ADAPTER_IF_MAX; i++) {
-        tcpip_adapter_get_netif ((tcpip_adapter_if_t)i, &nif);
-        netif = (struct netif *)nif;
-        if (netif && netif == ntif) {
-            _if = (tcpip_adapter_if_t)i;
-            break;
-        }
+  struct netif *netif = NULL;
+  void *nif = NULL;
+  int i;
+  for (i = 0; i < TCPIP_ADAPTER_IF_MAX; i++) {
+    tcpip_adapter_get_netif((tcpip_adapter_if_t)i, &nif);
+    netif = (struct netif *)nif;
+    if (netif && netif == ntif) {
+      _if = (tcpip_adapter_if_t)i;
+      break;
     }
+  }
 }
 
-AsyncUDPPacket::~AsyncUDPPacket()
-{
-    pbuf_free(_pb);
+AsyncUDPPacket::~AsyncUDPPacket() {
+  pbuf_free(_pb);
 }
 
-uint8_t * AsyncUDPPacket::data()
-{
-    return _data;
+uint8_t *AsyncUDPPacket::data() {
+  return _data;
 }
 
-size_t AsyncUDPPacket::length()
-{
-    return _len;
+size_t AsyncUDPPacket::length() {
+  return _len;
 }
 
-int AsyncUDPPacket::available(){
-    return _len - _index;
+int AsyncUDPPacket::available() {
+  return _len - _index;
 }
 
-size_t AsyncUDPPacket::read(uint8_t *data, size_t len){
-    size_t i;
-    size_t a = _len - _index;
-    if(len > a){
-        len = a;
-    }
-    for(i=0;i<len;i++){
-        data[i] = read();
-    }
-    return len;
+size_t AsyncUDPPacket::read(uint8_t *data, size_t len) {
+  size_t i;
+  size_t a = _len - _index;
+  if (len > a) {
+    len = a;
+  }
+  for (i = 0; i < len; i++) {
+    data[i] = read();
+  }
+  return len;
 }
 
-int AsyncUDPPacket::read(){
-    if(_index < _len){
-        return _data[_index++];
-    }
-    return -1;
+int AsyncUDPPacket::read() {
+  if (_index < _len) {
+    return _data[_index++];
+  }
+  return -1;
 }
 
-int AsyncUDPPacket::peek(){
-    if(_index < _len){
-        return _data[_index];
-    }
-    return -1;
+int AsyncUDPPacket::peek() {
+  if (_index < _len) {
+    return _data[_index];
+  }
+  return -1;
 }
 
-void AsyncUDPPacket::flush(){
-    _index = _len;
+void AsyncUDPPacket::flush() {
+  _index = _len;
 }
 
-tcpip_adapter_if_t AsyncUDPPacket::interface()
-{
-    return _if;
+tcpip_adapter_if_t AsyncUDPPacket::interface() {
+  return _if;
 }
 
-IPAddress AsyncUDPPacket::localIP()
-{
-    if(_localIp.type != IPADDR_TYPE_V4){
-        return IPAddress();
-    }
-    return IPAddress(_localIp.u_addr.ip4.addr);
+IPAddress AsyncUDPPacket::localIP() {
+#if CONFIG_LWIP_IPV6
+  if (_localIp.type != IPADDR_TYPE_V4) {
+    return IPAddress();
+  }
+  return IPAddress(_localIp.u_addr.ip4.addr);
+#else
+  return IPAddress(_localIp.addr);
+#endif
 }
 
-IPv6Address AsyncUDPPacket::localIPv6()
-{
-    if(_localIp.type != IPADDR_TYPE_V6){
-        return IPv6Address();
-    }
-    return IPv6Address(_localIp.u_addr.ip6.addr);
+#if CONFIG_LWIP_IPV6
+IPAddress AsyncUDPPacket::localIPv6() {
+  if (_localIp.type != IPADDR_TYPE_V6) {
+    return IPAddress(IPv6);
+  }
+  return IPAddress(IPv6, (const uint8_t *)_localIp.u_addr.ip6.addr, _localIp.u_addr.ip6.zone);
 }
+#endif
 
-uint16_t AsyncUDPPacket::localPort()
-{
-    return _localPort;
+uint16_t AsyncUDPPacket::localPort() {
+  return _localPort;
 }
 
-IPAddress AsyncUDPPacket::remoteIP()
-{
-    if(_remoteIp.type != IPADDR_TYPE_V4){
-        return IPAddress();
-    }
-    return IPAddress(_remoteIp.u_addr.ip4.addr);
+IPAddress AsyncUDPPacket::remoteIP() {
+#if CONFIG_LWIP_IPV6
+  if (_remoteIp.type != IPADDR_TYPE_V4) {
+    return IPAddress();
+  }
+  return IPAddress(_remoteIp.u_addr.ip4.addr);
+#else
+  return IPAddress(_remoteIp.addr);
+#endif
 }
 
-IPv6Address AsyncUDPPacket::remoteIPv6()
-{
-    if(_remoteIp.type != IPADDR_TYPE_V6){
-        return IPv6Address();
-    }
-    return IPv6Address(_remoteIp.u_addr.ip6.addr);
+#if CONFIG_LWIP_IPV6
+IPAddress AsyncUDPPacket::remoteIPv6() {
+  if (_remoteIp.type != IPADDR_TYPE_V6) {
+    return IPAddress(IPv6);
+  }
+  return IPAddress(IPv6, (const uint8_t *)_remoteIp.u_addr.ip6.addr, _remoteIp.u_addr.ip6.zone);
 }
+#endif
 
-uint16_t AsyncUDPPacket::remotePort()
-{
-    return _remotePort;
+uint16_t AsyncUDPPacket::remotePort() {
+  return _remotePort;
 }
 
-void AsyncUDPPacket::remoteMac(uint8_t * mac)
-{
-    memcpy(mac, _remoteMac, 6);
+void AsyncUDPPacket::remoteMac(uint8_t *mac) {
+  memcpy(mac, _remoteMac, 6);
 }
 
-bool AsyncUDPPacket::isIPv6()
-{
-    return _localIp.type == IPADDR_TYPE_V6;
+bool AsyncUDPPacket::isIPv6() {
+#if CONFIG_LWIP_IPV6
+  return _localIp.type == IPADDR_TYPE_V6;
+#else
+  return false;
+#endif
 }
 
-bool AsyncUDPPacket::isBroadcast()
-{
-    if(_localIp.type == IPADDR_TYPE_V6){
-        return false;
-    }
-    uint32_t ip = _localIp.u_addr.ip4.addr;
-    return ip == 0xFFFFFFFF || ip == 0 || (ip & 0xFF000000) == 0xFF000000;
+bool AsyncUDPPacket::isBroadcast() {
+#if CONFIG_LWIP_IPV6
+  if (_localIp.type == IPADDR_TYPE_V6) {
+    return false;
+  }
+  uint32_t ip = _localIp.u_addr.ip4.addr;
+#else
+  uint32_t ip = _localIp.addr;
+#endif
+  return ip == 0xFFFFFFFF || ip == 0 || (ip & 0xFF000000) == 0xFF000000;
 }
 
-bool AsyncUDPPacket::isMulticast()
-{
-    return ip_addr_ismulticast(&(_localIp));
+bool AsyncUDPPacket::isMulticast() {
+  return ip_addr_ismulticast(&(_localIp));
 }
 
-size_t AsyncUDPPacket::write(const uint8_t *data, size_t len)
-{
-    if(!data){
-        return 0;
-    }
-    return _udp->writeTo(data, len, &_remoteIp, _remotePort, _if);
+size_t AsyncUDPPacket::write(const uint8_t *data, size_t len) {
+  if (!data) {
+    return 0;
+  }
+  return _udp->writeTo(data, len, &_remoteIp, _remotePort, _if);
 }
 
-size_t AsyncUDPPacket::write(uint8_t data)
-{
-    return write(&data, 1);
+size_t AsyncUDPPacket::write(uint8_t data) {
+  return write(&data, 1);
 }
 
-size_t AsyncUDPPacket::send(AsyncUDPMessage &message)
-{
-    return write(message.data(), message.length());
+size_t AsyncUDPPacket::send(AsyncUDPMessage &message) {
+  return write(message.data(), message.length());
 }
 
-bool AsyncUDP::_init(){
-    if(_pcb){
-        return true;
-    }
-    _pcb = udp_new();
-    if(!_pcb){
-        return false;
-    }
-    //_lock = xSemaphoreCreateMutex();
-    udp_recv(_pcb, &_udp_recv, (void *) this);
+bool AsyncUDP::_init() {
+  if (_pcb) {
     return true;
+  }
+  UDP_MUTEX_LOCK();
+  _pcb = udp_new();
+  if (!_pcb) {
+    UDP_MUTEX_UNLOCK();
+    return false;
+  }
+  udp_recv(_pcb, &_udp_recv, (void *)this);
+  UDP_MUTEX_UNLOCK();
+  return true;
 }
 
-AsyncUDP::AsyncUDP()
-{
-    _pcb = NULL;
-    _connected = false;
-    _handler = NULL;
-}
-
-AsyncUDP::~AsyncUDP()
-{
-    close();
-    UDP_MUTEX_LOCK();
-    udp_recv(_pcb, NULL, NULL);
-    _udp_remove(_pcb);
-    _pcb = NULL;
-    UDP_MUTEX_UNLOCK();
-    //vSemaphoreDelete(_lock);
+AsyncUDP::AsyncUDP() {
+  _pcb = NULL;
+  _connected = false;
+  _lastErr = ERR_OK;
+  _handler = NULL;
 }
 
-void AsyncUDP::close()
-{
-    UDP_MUTEX_LOCK();
-    if(_pcb != NULL) {
-        if(_connected) {
-            _udp_disconnect(_pcb);
-        }
-        _connected = false;
-        //todo: unjoin multicast group
-    }
-    UDP_MUTEX_UNLOCK();
+AsyncUDP::~AsyncUDP() {
+  close();
+  UDP_MUTEX_LOCK();
+  udp_recv(_pcb, NULL, NULL);
+  UDP_MUTEX_UNLOCK();
+  _udp_remove(_pcb);
+  _pcb = NULL;
 }
 
-bool AsyncUDP::connect(const ip_addr_t *addr, uint16_t port)
-{
-    if(!_udp_task_start()){
-        log_e("failed to start task");
-        return false;
+void AsyncUDP::close() {
+  if (_pcb != NULL) {
+    if (_connected) {
+      _udp_disconnect(_pcb);
     }
-    if(!_init()) {
-        return false;
-    }
-    close();
+    _connected = false;
+    //todo: unjoin multicast group
+  }
+}
+
+bool AsyncUDP::connect(const ip_addr_t *addr, uint16_t port) {
+  if (!_udp_task_start()) {
+    log_e("failed to start task");
+    return false;
+  }
+  if (!_init()) {
+    return false;
+  }
+  close();
+  _lastErr = _udp_connect(_pcb, addr, port);
+  if (_lastErr != ERR_OK) {
+    return false;
+  }
+  _connected = true;
+  return true;
+}
+
+bool AsyncUDP::listen(const ip_addr_t *addr, uint16_t port) {
+  if (!_udp_task_start()) {
+    log_e("failed to start task");
+    return false;
+  }
+  if (!_init()) {
+    return false;
+  }
+  close();
+  if (addr) {
+    IP_SET_TYPE_VAL(_pcb->local_ip, addr->type);
+    IP_SET_TYPE_VAL(_pcb->remote_ip, addr->type);
+  }
+  if (_udp_bind(_pcb, addr, port) != ERR_OK) {
+    return false;
+  }
+  _connected = true;
+  return true;
+}
+
+static esp_err_t joinMulticastGroup(const ip_addr_t *addr, bool join, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX) {
+  struct netif *netif = NULL;
+  if (tcpip_if < TCPIP_ADAPTER_IF_MAX) {
+    void *nif = NULL;
+    esp_err_t err = tcpip_adapter_get_netif(tcpip_if, &nif);
+    if (err) {
+      return ESP_ERR_INVALID_ARG;
+    }
+    netif = (struct netif *)nif;
     UDP_MUTEX_LOCK();
-    err_t err = _udp_connect(_pcb, addr, port);
-    if(err != ERR_OK) {
-        UDP_MUTEX_UNLOCK();
-        return false;
-    }
-    _connected = true;
-    UDP_MUTEX_UNLOCK();
-    return true;
-}
 
-bool AsyncUDP::listen(const ip_addr_t *addr, uint16_t port)
-{
-    if(!_udp_task_start()){
-        log_e("failed to start task");
-        return false;
-    }
-    if(!_init()) {
-        return false;
-    }
-    close();
-    if(addr){
-        IP_SET_TYPE_VAL(_pcb->local_ip,  addr->type);
-        IP_SET_TYPE_VAL(_pcb->remote_ip, addr->type);
+#if CONFIG_LWIP_IPV6
+    if (addr->type == IPADDR_TYPE_V4) {
+      if (join) {
+        if (igmp_joingroup_netif(netif, (const ip4_addr *)&(addr->u_addr.ip4))) {
+          goto igmp_fail;
+        }
+      } else {
+        if (igmp_leavegroup_netif(netif, (const ip4_addr *)&(addr->u_addr.ip4))) {
+          goto igmp_fail;
+        }
+      }
+    } else {
+      if (join) {
+        if (mld6_joingroup_netif(netif, &(addr->u_addr.ip6))) {
+          goto igmp_fail;
+        }
+      } else {
+        if (mld6_leavegroup_netif(netif, &(addr->u_addr.ip6))) {
+          goto igmp_fail;
+        }
+      }
     }
-    UDP_MUTEX_LOCK();
-    if(_udp_bind(_pcb, addr, port) != ERR_OK) {
-        UDP_MUTEX_UNLOCK();
-        return false;
+#else
+    if (join) {
+      if (igmp_joingroup_netif(netif, (const ip4_addr *)(addr))) {
+        goto igmp_fail;
+      }
+    } else {
+      if (igmp_leavegroup_netif(netif, (const ip4_addr *)(addr))) {
+        goto igmp_fail;
+      }
     }
-    _connected = true;
+#endif
     UDP_MUTEX_UNLOCK();
-    return true;
-}
-
-static esp_err_t joinMulticastGroup(const ip_addr_t *addr, bool join, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX)
-{
-    struct netif * netif = NULL;
-    if(tcpip_if < TCPIP_ADAPTER_IF_MAX){
-        void * nif = NULL;
-        esp_err_t err = tcpip_adapter_get_netif(tcpip_if, &nif);
-        if (err) {
-            return ESP_ERR_INVALID_ARG;
+  } else {
+    UDP_MUTEX_LOCK();
+#if CONFIG_LWIP_IPV6
+    if (addr->type == IPADDR_TYPE_V4) {
+      if (join) {
+        if (igmp_joingroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)&(addr->u_addr.ip4))) {
+          goto igmp_fail;
+        }
+      } else {
+        if (igmp_leavegroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)&(addr->u_addr.ip4))) {
+          goto igmp_fail;
         }
-        netif = (struct netif *)nif;
-
-        if (addr->type == IPADDR_TYPE_V4) {
-            if(join){
-                if (igmp_joingroup_netif(netif, (const ip4_addr *)&(addr->u_addr.ip4))) {
-                    return ESP_ERR_INVALID_STATE;
-                }
-            } else {
-                if (igmp_leavegroup_netif(netif, (const ip4_addr *)&(addr->u_addr.ip4))) {
-                    return ESP_ERR_INVALID_STATE;
-                }
-            }
-        } else {
-            if(join){
-                if (mld6_joingroup_netif(netif, &(addr->u_addr.ip6))) {
-                    return ESP_ERR_INVALID_STATE;
-                }
-            } else {
-                if (mld6_leavegroup_netif(netif, &(addr->u_addr.ip6))) {
-                    return ESP_ERR_INVALID_STATE;
-                }
-            }
+      }
+    } else {
+      if (join) {
+        if (mld6_joingroup((const ip6_addr *)IP6_ADDR_ANY, &(addr->u_addr.ip6))) {
+          goto igmp_fail;
         }
-    }  else {
-        if (addr->type == IPADDR_TYPE_V4) {
-            if(join){
-                if (igmp_joingroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)&(addr->u_addr.ip4))) {
-                    return ESP_ERR_INVALID_STATE;
-                }
-            } else {
-                if (igmp_leavegroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)&(addr->u_addr.ip4))) {
-                    return ESP_ERR_INVALID_STATE;
-                }
-            }
-        } else {
-            if(join){
-                if (mld6_joingroup((const ip6_addr *)IP6_ADDR_ANY, &(addr->u_addr.ip6))) {
-                    return ESP_ERR_INVALID_STATE;
-                }
-            } else {
-                if (mld6_leavegroup((const ip6_addr *)IP6_ADDR_ANY, &(addr->u_addr.ip6))) {
-                    return ESP_ERR_INVALID_STATE;
-                }
-            }
+      } else {
+        if (mld6_leavegroup((const ip6_addr *)IP6_ADDR_ANY, &(addr->u_addr.ip6))) {
+          goto igmp_fail;
         }
+      }
+    }
+#else
+    if (join) {
+      if (igmp_joingroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)(addr))) {
+        goto igmp_fail;
+      }
+    } else {
+      if (igmp_leavegroup((const ip4_addr *)IP4_ADDR_ANY, (const ip4_addr *)(addr))) {
+        goto igmp_fail;
+      }
     }
-    return ESP_OK;
+#endif
+    UDP_MUTEX_UNLOCK();
+  }
+  return ESP_OK;
+
+igmp_fail:
+  UDP_MUTEX_UNLOCK();
+  return ESP_ERR_INVALID_STATE;
 }
 
-bool AsyncUDP::listenMulticast(const ip_addr_t *addr, uint16_t port, uint8_t ttl, tcpip_adapter_if_t tcpip_if)
-{
-    if(!ip_addr_ismulticast(addr)) {
-        return false;
-    }
+bool AsyncUDP::listenMulticast(const ip_addr_t *addr, uint16_t port, uint8_t ttl, tcpip_adapter_if_t tcpip_if) {
+  if (!ip_addr_ismulticast(addr)) {
+    return false;
+  }
 
-    if (joinMulticastGroup(addr, true, tcpip_if)!= ERR_OK) {
-        return false;
-    }
+  if (joinMulticastGroup(addr, true, tcpip_if) != ERR_OK) {
+    return false;
+  }
 
-    if(!listen(NULL, port)) {
-        return false;
-    }
+  if (!listen(NULL, port)) {
+    return false;
+  }
 
-    UDP_MUTEX_LOCK();
-    _pcb->mcast_ttl = ttl;
-    _pcb->remote_port = port;
-    ip_addr_copy(_pcb->remote_ip, *addr);
-    //ip_addr_copy(_pcb->remote_ip, ip_addr_any_type);
-    UDP_MUTEX_UNLOCK();
+  _pcb->mcast_ttl = ttl;
+  _pcb->remote_port = port;
+  ip_addr_copy(_pcb->remote_ip, *addr);
+  //ip_addr_copy(_pcb->remote_ip, ip_addr_any_type);
 
-    return true;
+  return true;
 }
 
-size_t AsyncUDP::writeTo(const uint8_t * data, size_t len, const ip_addr_t * addr, uint16_t port, tcpip_adapter_if_t tcpip_if)
-{
-    if(!_pcb) {
-        UDP_MUTEX_LOCK();
-        _pcb = udp_new();
-        UDP_MUTEX_UNLOCK();
-        if(_pcb == NULL) {
-            return 0;
-        }
-    }
-    if(len > CONFIG_TCP_MSS) {
-        len = CONFIG_TCP_MSS;
+size_t AsyncUDP::writeTo(const uint8_t *data, size_t len, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if) {
+  if (!_pcb) {
+    UDP_MUTEX_LOCK();
+    _pcb = udp_new();
+    UDP_MUTEX_UNLOCK();
+    if (_pcb == NULL) {
+      return 0;
+    }
+  }
+  if (len > CONFIG_TCP_MSS) {
+    len = CONFIG_TCP_MSS;
+  }
+  _lastErr = ERR_OK;
+  pbuf *pbt = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM);
+  if (pbt != NULL) {
+    uint8_t *dst = reinterpret_cast<uint8_t *>(pbt->payload);
+    memcpy(dst, data, len);
+    if (tcpip_if < TCPIP_ADAPTER_IF_MAX) {
+      void *nif = NULL;
+      tcpip_adapter_get_netif((tcpip_adapter_if_t)tcpip_if, &nif);
+      if (!nif) {
+        _lastErr = _udp_sendto(_pcb, pbt, addr, port);
+      } else {
+        _lastErr = _udp_sendto_if(_pcb, pbt, addr, port, (struct netif *)nif);
+      }
+    } else {
+      _lastErr = _udp_sendto(_pcb, pbt, addr, port);
     }
-    err_t err = ERR_OK;
-    pbuf* pbt = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM);
-    if(pbt != NULL) {
-        uint8_t* dst = reinterpret_cast<uint8_t*>(pbt->payload);
-        memcpy(dst, data, len);
-        UDP_MUTEX_LOCK();
-        if(tcpip_if < TCPIP_ADAPTER_IF_MAX){
-            void * nif = NULL;
-            tcpip_adapter_get_netif((tcpip_adapter_if_t)tcpip_if, &nif);
-            if(!nif){
-                err = _udp_sendto(_pcb, pbt, addr, port);
-            } else {
-                err = _udp_sendto_if(_pcb, pbt, addr, port, (struct netif *)nif);
-            }
-        } else {
-            err = _udp_sendto(_pcb, pbt, addr, port);
-        }
-        UDP_MUTEX_UNLOCK();
-        pbuf_free(pbt);
-        if(err < ERR_OK) {
-            return 0;
-        }
-        return len;
+    pbuf_free(pbt);
+    if (_lastErr < ERR_OK) {
+      return 0;
     }
-    return 0;
+    return len;
+  }
+  return 0;
 }
 
-void AsyncUDP::_recv(udp_pcb *upcb, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif * netif)
-{
-    while(pb != NULL) {
-        pbuf * this_pb = pb;
-        pb = pb->next;
-        this_pb->next = NULL;
-        if(_handler) {
-            AsyncUDPPacket packet(this, this_pb, addr, port, netif);
-            _handler(packet);
-        } else {
-            pbuf_free(this_pb);
-        }
+void AsyncUDP::_recv(udp_pcb *upcb, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif *netif) {
+  while (pb != NULL) {
+    pbuf *this_pb = pb;
+    pb = pb->next;
+    this_pb->next = NULL;
+    if (_handler) {
+      AsyncUDPPacket packet(this, this_pb, addr, port, netif);
+      _handler(packet);
     }
+    pbuf_free(this_pb);
+  }
 }
 
-void AsyncUDP::_s_recv(void *arg, udp_pcb *upcb, pbuf *p, const ip_addr_t *addr, uint16_t port, struct netif * netif)
-{
-    reinterpret_cast<AsyncUDP*>(arg)->_recv(upcb, p, addr, port, netif);
-}
-
-bool AsyncUDP::listen(uint16_t port)
-{
-    return listen(IP_ANY_TYPE, port);
-}
-
-bool AsyncUDP::listen(const IPAddress addr, uint16_t port)
-{
-    ip_addr_t laddr;
-    laddr.type = IPADDR_TYPE_V4;
-    laddr.u_addr.ip4.addr = addr;
-    return listen(&laddr, port);
+void AsyncUDP::_s_recv(void *arg, udp_pcb *upcb, pbuf *p, const ip_addr_t *addr, uint16_t port, struct netif *netif) {
+  reinterpret_cast<AsyncUDP *>(arg)->_recv(upcb, p, addr, port, netif);
 }
 
-bool AsyncUDP::listenMulticast(const IPAddress addr, uint16_t port, uint8_t ttl, tcpip_adapter_if_t tcpip_if)
-{
-    ip_addr_t laddr;
-    laddr.type = IPADDR_TYPE_V4;
-    laddr.u_addr.ip4.addr = addr;
-    return listenMulticast(&laddr, port, ttl, tcpip_if);
+bool AsyncUDP::listen(uint16_t port) {
+  return listen(IP_ANY_TYPE, port);
 }
 
-bool AsyncUDP::connect(const IPAddress addr, uint16_t port)
-{
-    ip_addr_t daddr;
-    daddr.type = IPADDR_TYPE_V4;
-    daddr.u_addr.ip4.addr = addr;
-    return connect(&daddr, port);
+bool AsyncUDP::listen(const IPAddress addr, uint16_t port) {
+  ip_addr_t laddr;
+  addr.to_ip_addr_t(&laddr);
+  return listen(&laddr, port);
 }
 
-size_t AsyncUDP::writeTo(const uint8_t *data, size_t len, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if)
-{
-    ip_addr_t daddr;
-    daddr.type = IPADDR_TYPE_V4;
-    daddr.u_addr.ip4.addr = addr;
-    return writeTo(data, len, &daddr, port, tcpip_if);
+bool AsyncUDP::listenMulticast(const IPAddress addr, uint16_t port, uint8_t ttl, tcpip_adapter_if_t tcpip_if) {
+  ip_addr_t laddr;
+  addr.to_ip_addr_t(&laddr);
+  return listenMulticast(&laddr, port, ttl, tcpip_if);
 }
 
-IPAddress AsyncUDP::listenIP()
-{
-    if(!_pcb || _pcb->remote_ip.type != IPADDR_TYPE_V4){
-        return IPAddress();
-    }
-    return IPAddress(_pcb->remote_ip.u_addr.ip4.addr);
+bool AsyncUDP::connect(const IPAddress addr, uint16_t port) {
+  ip_addr_t daddr;
+  addr.to_ip_addr_t(&daddr);
+  return connect(&daddr, port);
 }
 
-bool AsyncUDP::listen(const IPv6Address addr, uint16_t port)
-{
-    ip_addr_t laddr;
-    laddr.type = IPADDR_TYPE_V6;
-    memcpy((uint8_t*)(laddr.u_addr.ip6.addr), (const uint8_t*)addr, 16);
-    return listen(&laddr, port);
+size_t AsyncUDP::writeTo(const uint8_t *data, size_t len, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if) {
+  ip_addr_t daddr;
+  addr.to_ip_addr_t(&daddr);
+  return writeTo(data, len, &daddr, port, tcpip_if);
 }
 
-bool AsyncUDP::listenMulticast(const IPv6Address addr, uint16_t port, uint8_t ttl, tcpip_adapter_if_t tcpip_if)
-{
-    ip_addr_t laddr;
-    laddr.type = IPADDR_TYPE_V6;
-    memcpy((uint8_t*)(laddr.u_addr.ip6.addr), (const uint8_t*)addr, 16);
-    return listenMulticast(&laddr, port, ttl, tcpip_if);
+IPAddress AsyncUDP::listenIP() {
+#if CONFIG_LWIP_IPV6
+  if (!_pcb || _pcb->remote_ip.type != IPADDR_TYPE_V4) {
+    return IPAddress();
+  }
+  return IPAddress(_pcb->remote_ip.u_addr.ip4.addr);
+#else
+  return IPAddress(_pcb->remote_ip.addr);
+#endif
 }
 
-bool AsyncUDP::connect(const IPv6Address addr, uint16_t port)
-{
-    ip_addr_t daddr;
-    daddr.type = IPADDR_TYPE_V6;
-    memcpy((uint8_t*)(daddr.u_addr.ip6.addr), (const uint8_t*)addr, 16);
-    return connect(&daddr, port);
+#if CONFIG_LWIP_IPV6
+IPAddress AsyncUDP::listenIPv6() {
+  if (!_pcb || _pcb->remote_ip.type != IPADDR_TYPE_V6) {
+    return IPAddress(IPv6);
+  }
+  return IPAddress(IPv6, (const uint8_t *)_pcb->remote_ip.u_addr.ip6.addr, _pcb->remote_ip.u_addr.ip6.zone);
 }
+#endif
 
-size_t AsyncUDP::writeTo(const uint8_t *data, size_t len, const IPv6Address addr, uint16_t port, tcpip_adapter_if_t tcpip_if)
-{
-    ip_addr_t daddr;
-    daddr.type = IPADDR_TYPE_V6;
-    memcpy((uint8_t*)(daddr.u_addr.ip6.addr), (const uint8_t*)addr, 16);
-    return writeTo(data, len, &daddr, port, tcpip_if);
+size_t AsyncUDP::write(const uint8_t *data, size_t len) {
+  return writeTo(data, len, &(_pcb->remote_ip), _pcb->remote_port);
 }
 
-IPv6Address AsyncUDP::listenIPv6()
-{
-    if(!_pcb || _pcb->remote_ip.type != IPADDR_TYPE_V6){
-        return IPv6Address();
-    }
-    return IPv6Address(_pcb->remote_ip.u_addr.ip6.addr);
+size_t AsyncUDP::write(uint8_t data) {
+  return write(&data, 1);
 }
 
-size_t AsyncUDP::write(const uint8_t *data, size_t len)
-{
-    return writeTo(data, len, &(_pcb->remote_ip), _pcb->remote_port);
+size_t AsyncUDP::broadcastTo(uint8_t *data, size_t len, uint16_t port, tcpip_adapter_if_t tcpip_if) {
+  return writeTo(data, len, IP_ADDR_BROADCAST, port, tcpip_if);
 }
 
-size_t AsyncUDP::write(uint8_t data)
-{
-    return write(&data, 1);
+size_t AsyncUDP::broadcastTo(const char *data, uint16_t port, tcpip_adapter_if_t tcpip_if) {
+  return broadcastTo((uint8_t *)data, strlen(data), port, tcpip_if);
 }
 
-size_t AsyncUDP::broadcastTo(uint8_t *data, size_t len, uint16_t port, tcpip_adapter_if_t tcpip_if)
-{
-    return writeTo(data, len, IP_ADDR_BROADCAST, port, tcpip_if);
+size_t AsyncUDP::broadcast(uint8_t *data, size_t len) {
+  if (_pcb->local_port != 0) {
+    return broadcastTo(data, len, _pcb->local_port);
+  }
+  return 0;
 }
 
-size_t AsyncUDP::broadcastTo(const char * data, uint16_t port, tcpip_adapter_if_t tcpip_if)
-{
-    return broadcastTo((uint8_t *)data, strlen(data), port, tcpip_if);
+size_t AsyncUDP::broadcast(const char *data) {
+  return broadcast((uint8_t *)data, strlen(data));
 }
 
-size_t AsyncUDP::broadcast(uint8_t *data, size_t len)
-{
-    if(_pcb->local_port != 0) {
-        return broadcastTo(data, len, _pcb->local_port);
-    }
+size_t AsyncUDP::sendTo(AsyncUDPMessage &message, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if) {
+  if (!message) {
     return 0;
+  }
+  return writeTo(message.data(), message.length(), addr, port, tcpip_if);
 }
 
-size_t AsyncUDP::broadcast(const char * data)
-{
-    return broadcast((uint8_t *)data, strlen(data));
-}
-
-
-size_t AsyncUDP::sendTo(AsyncUDPMessage &message, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if)
-{
-    if(!message) {
-        return 0;
-    }
-    return writeTo(message.data(), message.length(), addr, port, tcpip_if);
-}
-
-size_t AsyncUDP::sendTo(AsyncUDPMessage &message, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if)
-{
-    if(!message) {
-        return 0;
-    }
-    return writeTo(message.data(), message.length(), addr, port, tcpip_if);
+size_t AsyncUDP::sendTo(AsyncUDPMessage &message, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if) {
+  if (!message) {
+    return 0;
+  }
+  return writeTo(message.data(), message.length(), addr, port, tcpip_if);
 }
 
-size_t AsyncUDP::sendTo(AsyncUDPMessage &message, const IPv6Address addr, uint16_t port, tcpip_adapter_if_t tcpip_if)
-{
-    if(!message) {
-        return 0;
-    }
-    return writeTo(message.data(), message.length(), addr, port, tcpip_if);
+size_t AsyncUDP::send(AsyncUDPMessage &message) {
+  if (!message) {
+    return 0;
+  }
+  return writeTo(message.data(), message.length(), &(_pcb->remote_ip), _pcb->remote_port);
 }
 
-size_t AsyncUDP::send(AsyncUDPMessage &message)
-{
-    if(!message) {
-        return 0;
-    }
-    return writeTo(message.data(), message.length(), &(_pcb->remote_ip), _pcb->remote_port);
+size_t AsyncUDP::broadcastTo(AsyncUDPMessage &message, uint16_t port, tcpip_adapter_if_t tcpip_if) {
+  if (!message) {
+    return 0;
+  }
+  return broadcastTo(message.data(), message.length(), port, tcpip_if);
 }
 
-size_t AsyncUDP::broadcastTo(AsyncUDPMessage &message, uint16_t port, tcpip_adapter_if_t tcpip_if)
-{
-    if(!message) {
-        return 0;
-    }
-    return broadcastTo(message.data(), message.length(), port, tcpip_if);
+size_t AsyncUDP::broadcast(AsyncUDPMessage &message) {
+  if (!message) {
+    return 0;
+  }
+  return broadcast(message.data(), message.length());
 }
 
-size_t AsyncUDP::broadcast(AsyncUDPMessage &message)
-{
-    if(!message) {
-        return 0;
-    }
-    return broadcast(message.data(), message.length());
+AsyncUDP::operator bool() {
+  return _connected;
 }
 
-AsyncUDP::operator bool()
-{
-    return _connected;
+bool AsyncUDP::connected() {
+  return _connected;
 }
 
-bool AsyncUDP::connected()
-{
-    return _connected;
+esp_err_t AsyncUDP::lastErr() {
+  return _lastErr;
 }
 
-void AsyncUDP::onPacket(AuPacketHandlerFunctionWithArg cb, void * arg)
-{
-    onPacket(std::bind(cb, arg, std::placeholders::_1));
+void AsyncUDP::onPacket(AuPacketHandlerFunctionWithArg cb, void *arg) {
+  onPacket(std::bind(cb, arg, std::placeholders::_1));
 }
 
-void AsyncUDP::onPacket(AuPacketHandlerFunction cb)
-{
-    _handler = cb;
+void AsyncUDP::onPacket(AuPacketHandlerFunction cb) {
+  _handler = cb;
 }
diff --git a/libraries/AsyncUDP/src/AsyncUDP.h b/libraries/AsyncUDP/src/AsyncUDP.h
index 2ac48a69684..cd96d852542 100644
--- a/libraries/AsyncUDP/src/AsyncUDP.h
+++ b/libraries/AsyncUDP/src/AsyncUDP.h
@@ -2,16 +2,25 @@
 #define ESPASYNCUDP_H
 
 #include "IPAddress.h"
-#include "IPv6Address.h"
 #include "Print.h"
+#include "Stream.h"
 #include <functional>
 extern "C" {
+#include "esp_netif.h"
 #include "lwip/ip_addr.h"
-#include <tcpip_adapter.h>
 #include "freertos/queue.h"
 #include "freertos/semphr.h"
 }
 
+// This enum and it's uses are copied and adapted for compatibility from ESP-IDF 4-
+typedef enum {
+  TCPIP_ADAPTER_IF_STA = 0, /**< Wi-Fi STA (station) interface */
+  TCPIP_ADAPTER_IF_AP,      /**< Wi-Fi soft-AP interface */
+  TCPIP_ADAPTER_IF_ETH,     /**< Ethernet interface */
+  TCPIP_ADAPTER_IF_PPP,     /**< PPP interface */
+  TCPIP_ADAPTER_IF_MAX
+} tcpip_adapter_if_t;
+
 class AsyncUDP;
 class AsyncUDPPacket;
 class AsyncUDPMessage;
@@ -19,134 +28,136 @@ struct udp_pcb;
 struct pbuf;
 struct netif;
 
-typedef std::function<void(AsyncUDPPacket& packet)> AuPacketHandlerFunction;
-typedef std::function<void(void * arg, AsyncUDPPacket& packet)> AuPacketHandlerFunctionWithArg;
+typedef std::function<void(AsyncUDPPacket &packet)> AuPacketHandlerFunction;
+typedef std::function<void(void *arg, AsyncUDPPacket &packet)> AuPacketHandlerFunctionWithArg;
 
-class AsyncUDPMessage : public Print
-{
+class AsyncUDPMessage : public Print {
 protected:
-    uint8_t *_buffer;
-    size_t _index;
-    size_t _size;
+  uint8_t *_buffer;
+  size_t _index;
+  size_t _size;
+
 public:
-    AsyncUDPMessage(size_t size=CONFIG_TCP_MSS);
-    virtual ~AsyncUDPMessage();
-    size_t write(const uint8_t *data, size_t len);
-    size_t write(uint8_t data);
-    size_t space();
-    uint8_t * data();
-    size_t length();
-    void flush();
-    operator bool()
-    {
-        return _buffer != NULL;
-    }
+  AsyncUDPMessage(size_t size = CONFIG_TCP_MSS);
+  virtual ~AsyncUDPMessage();
+  size_t write(const uint8_t *data, size_t len);
+  size_t write(uint8_t data);
+  size_t space();
+  uint8_t *data();
+  size_t length();
+  void flush();
+  operator bool() {
+    return _buffer != NULL;
+  }
 };
 
-class AsyncUDPPacket : public Stream
-{
+class AsyncUDPPacket : public Stream {
 protected:
-    AsyncUDP *_udp;
-    pbuf *_pb;
-    tcpip_adapter_if_t _if;
-    ip_addr_t _localIp;
-    uint16_t _localPort;
-    ip_addr_t _remoteIp;
-    uint16_t _remotePort;
-    uint8_t _remoteMac[6];
-    uint8_t *_data;
-    size_t _len;
-    size_t _index;
+  AsyncUDP *_udp;
+  pbuf *_pb;
+  tcpip_adapter_if_t _if;
+  ip_addr_t _localIp;
+  uint16_t _localPort;
+  ip_addr_t _remoteIp;
+  uint16_t _remotePort;
+  uint8_t _remoteMac[6];
+  uint8_t *_data;
+  size_t _len;
+  size_t _index;
+
 public:
-    AsyncUDPPacket(AsyncUDP *udp, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif * netif);
-    virtual ~AsyncUDPPacket();
-
-    uint8_t * data();
-    size_t length();
-    bool isBroadcast();
-    bool isMulticast();
-    bool isIPv6();
-
-    tcpip_adapter_if_t interface();
-
-    IPAddress localIP();
-    IPv6Address localIPv6();
-    uint16_t localPort();
-    IPAddress remoteIP();
-    IPv6Address remoteIPv6();
-    uint16_t remotePort();
-    void remoteMac(uint8_t * mac);
-
-    size_t send(AsyncUDPMessage &message);
-
-    int available();
-    size_t read(uint8_t *data, size_t len);
-    int read();
-    int peek();
-    void flush();
-
-    size_t write(const uint8_t *data, size_t len);
-    size_t write(uint8_t data);
+  AsyncUDPPacket(AsyncUDPPacket &packet);
+  AsyncUDPPacket(AsyncUDP *udp, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif *netif);
+  virtual ~AsyncUDPPacket();
+
+  uint8_t *data();
+  size_t length();
+  bool isBroadcast();
+  bool isMulticast();
+  bool isIPv6();
+
+  tcpip_adapter_if_t interface();
+
+  IPAddress localIP();
+#if CONFIG_LWIP_IPV6
+  IPAddress localIPv6();
+#endif
+  uint16_t localPort();
+  IPAddress remoteIP();
+#if CONFIG_LWIP_IPV6
+  IPAddress remoteIPv6();
+#endif
+  uint16_t remotePort();
+  void remoteMac(uint8_t *mac);
+
+  size_t send(AsyncUDPMessage &message);
+
+  int available();
+  size_t read(uint8_t *data, size_t len);
+  int read();
+  int peek();
+  void flush();
+
+  size_t write(const uint8_t *data, size_t len);
+  size_t write(uint8_t data);
 };
 
-class AsyncUDP : public Print
-{
+class AsyncUDP : public Print {
 protected:
-    udp_pcb *_pcb;
-    //xSemaphoreHandle _lock;
-    bool _connected;
-    AuPacketHandlerFunction _handler;
+  udp_pcb *_pcb;
+  //SemaphoreHandle_t _lock;
+  bool _connected;
+  esp_err_t _lastErr;
+  AuPacketHandlerFunction _handler;
 
-    bool _init();
-    void _recv(udp_pcb *upcb, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif * netif);
+  bool _init();
+  void _recv(udp_pcb *upcb, pbuf *pb, const ip_addr_t *addr, uint16_t port, struct netif *netif);
 
 public:
-    AsyncUDP();
-    virtual ~AsyncUDP();
+  AsyncUDP();
+  virtual ~AsyncUDP();
 
-    void onPacket(AuPacketHandlerFunctionWithArg cb, void * arg=NULL);
-    void onPacket(AuPacketHandlerFunction cb);
+  void onPacket(AuPacketHandlerFunctionWithArg cb, void *arg = NULL);
+  void onPacket(AuPacketHandlerFunction cb);
 
-    bool listen(const ip_addr_t *addr, uint16_t port);
-    bool listen(const IPAddress addr, uint16_t port);
-    bool listen(const IPv6Address addr, uint16_t port);
-    bool listen(uint16_t port);
+  bool listen(const ip_addr_t *addr, uint16_t port);
+  bool listen(const IPAddress addr, uint16_t port);
+  bool listen(uint16_t port);
 
-    bool listenMulticast(const ip_addr_t *addr, uint16_t port, uint8_t ttl=1, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    bool listenMulticast(const IPAddress addr, uint16_t port, uint8_t ttl=1, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    bool listenMulticast(const IPv6Address addr, uint16_t port, uint8_t ttl=1, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
+  bool listenMulticast(const ip_addr_t *addr, uint16_t port, uint8_t ttl = 1, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX);
+  bool listenMulticast(const IPAddress addr, uint16_t port, uint8_t ttl = 1, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX);
 
-    bool connect(const ip_addr_t *addr, uint16_t port);
-    bool connect(const IPAddress addr, uint16_t port);
-    bool connect(const IPv6Address addr, uint16_t port);
+  bool connect(const ip_addr_t *addr, uint16_t port);
+  bool connect(const IPAddress addr, uint16_t port);
 
-    void close();
+  void close();
 
-    size_t writeTo(const uint8_t *data, size_t len, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    size_t writeTo(const uint8_t *data, size_t len, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    size_t writeTo(const uint8_t *data, size_t len, const IPv6Address addr, uint16_t port, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    size_t write(const uint8_t *data, size_t len);
-    size_t write(uint8_t data);
+  size_t writeTo(const uint8_t *data, size_t len, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX);
+  size_t writeTo(const uint8_t *data, size_t len, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX);
+  size_t write(const uint8_t *data, size_t len);
+  size_t write(uint8_t data);
 
-    size_t broadcastTo(uint8_t *data, size_t len, uint16_t port, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    size_t broadcastTo(const char * data, uint16_t port, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    size_t broadcast(uint8_t *data, size_t len);
-    size_t broadcast(const char * data);
+  size_t broadcastTo(uint8_t *data, size_t len, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX);
+  size_t broadcastTo(const char *data, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX);
+  size_t broadcast(uint8_t *data, size_t len);
+  size_t broadcast(const char *data);
 
-    size_t sendTo(AsyncUDPMessage &message, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    size_t sendTo(AsyncUDPMessage &message, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    size_t sendTo(AsyncUDPMessage &message, const IPv6Address addr, uint16_t port, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    size_t send(AsyncUDPMessage &message);
+  size_t sendTo(AsyncUDPMessage &message, const ip_addr_t *addr, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX);
+  size_t sendTo(AsyncUDPMessage &message, const IPAddress addr, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX);
+  size_t send(AsyncUDPMessage &message);
 
-    size_t broadcastTo(AsyncUDPMessage &message, uint16_t port, tcpip_adapter_if_t tcpip_if=TCPIP_ADAPTER_IF_MAX);
-    size_t broadcast(AsyncUDPMessage &message);
+  size_t broadcastTo(AsyncUDPMessage &message, uint16_t port, tcpip_adapter_if_t tcpip_if = TCPIP_ADAPTER_IF_MAX);
+  size_t broadcast(AsyncUDPMessage &message);
 
-    IPAddress listenIP();
-    IPv6Address listenIPv6();
-    bool connected();
-    operator bool();
+  IPAddress listenIP();
+#if CONFIG_LWIP_IPV6
+  IPAddress listenIPv6();
+#endif
+  bool connected();
+  esp_err_t lastErr();
+  operator bool();
 
-    static void _s_recv(void *arg, udp_pcb *upcb, pbuf *p, const ip_addr_t *addr, uint16_t port, struct netif * netif);
+  static void _s_recv(void *arg, udp_pcb *upcb, pbuf *p, const ip_addr_t *addr, uint16_t port, struct netif *netif);
 };
 
 #endif
diff --git a/libraries/AzureIoT b/libraries/AzureIoT
deleted file mode 160000
index 5e8ffb21115..00000000000
--- a/libraries/AzureIoT
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 5e8ffb21115675f8c258e81bb287a9cd610e3205
diff --git a/libraries/BLE/LICENSE b/libraries/BLE/LICENSE
new file mode 100644
index 00000000000..4558f79ff9b
--- /dev/null
+++ b/libraries/BLE/LICENSE
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
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+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
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+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
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+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
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+      for use, reproduction, or distribution of Your modifications, or
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+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "{}"
+      replaced with your own identifying information. (Don't include
+      the brackets!)  The text should be enclosed in the appropriate
+      comment syntax for the file format. We also recommend that a
+      file or class name and description of purpose be included on the
+      same "printed page" as the copyright notice for easier
+      identification within third-party archives.
+
+   Copyright 2017 Neil Kolban
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
diff --git a/libraries/BLE/README.md b/libraries/BLE/README.md
index e80fbe0c52b..eb70ee9ff00 100644
--- a/libraries/BLE/README.md
+++ b/libraries/BLE/README.md
@@ -1,15 +1,8 @@
 # ESP32 BLE for Arduino
-The Arduino IDE provides an excellent library package manager where versions of libraries can be downloaded and installed.  This Github project provides the repository for the ESP32 BLE support for Arduino.
+The Arduino IDE provides an excellent library package manager where versions of libraries can be downloaded and installed. This Github project provides the repository for the ESP32 BLE support for Arduino.
 
-The actual source of the project which is being maintained can be found here:
+The original source of the project, **which is not maintained anymore**, can be found here: https://github.com/nkolban/esp32-snippets
 
-https://github.com/nkolban/esp32-snippets
+Issues and questions should be raised here: https://github.com/espressif/arduino-esp32/issues <br> (please don't use https://github.com/nkolban/esp32-snippets/issues!)
 
-Issues and questions should be raised here:
-
-https://github.com/nkolban/esp32-snippets/issues
-
-
-Documentation for using the library can be found here:
-
-https://github.com/nkolban/esp32-snippets/tree/master/Documentation
\ No newline at end of file
+Documentation for using the library can be found here: https://github.com/nkolban/esp32-snippets/tree/master/Documentation
diff --git a/libraries/BLE/examples/BLE5_extended_scan/BLE5_extended_scan.ino b/libraries/BLE/examples/BLE5_extended_scan/BLE5_extended_scan.ino
new file mode 100644
index 00000000000..42daff86835
--- /dev/null
+++ b/libraries/BLE/examples/BLE5_extended_scan/BLE5_extended_scan.ino
@@ -0,0 +1,50 @@
+/*
+   BLE5 extended scan example for esp32 C3 and S3
+   with this code it is simple to scan legacy (BLE4) compatible advertising,
+   and BLE5 extended advertising. New coded added in BLEScan is not changing old behavior,
+   which can be used with old esp32, but is adding functionality to use on C3/S3.
+   With this new API advertised device wont be stored in API, it is now user responsibility
+
+   author: chegewara
+*/
+#ifndef SOC_BLE_50_SUPPORTED
+#warning "This SoC does not support BLE5. Try using ESP32-C3, or ESP32-S3"
+#else
+
+#include <BLEDevice.h>
+#include <BLEUtils.h>
+#include <BLEScan.h>
+#include <BLEAdvertisedDevice.h>
+
+uint32_t scanTime = 100;  //In 10ms (1000ms)
+BLEScan *pBLEScan;
+
+class MyBLEExtAdvertisingCallbacks : public BLEExtAdvertisingCallbacks {
+  void onResult(esp_ble_gap_ext_adv_report_t report) {
+    if (report.event_type & ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY) {
+      // here we can receive regular advertising data from BLE4.x devices
+      Serial.println("BLE4.2");
+    } else {
+      // here we will get extended advertising data that are advertised over data channel by BLE5 devices
+      Serial.printf("Ext advertise: data_le: %d, data_status: %d \n", report.adv_data_len, report.data_status);
+    }
+  }
+};
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Scanning...");
+
+  BLEDevice::init("");
+  pBLEScan = BLEDevice::getScan();  //create new scan
+  pBLEScan->setExtendedScanCallback(new MyBLEExtAdvertisingCallbacks());
+  pBLEScan->setExtScanParams();         // use with pre-defined/default values, overloaded function allows to pass parameters
+  delay(1000);                          // it is just for simplicity this example, to let ble stack to set extended scan params
+  pBLEScan->startExtScan(scanTime, 3);  // scan duration in n * 10ms, period - repeat after n seconds (period >= duration)
+}
+
+void loop() {
+  // put your main code here, to run repeatedly:
+  delay(2000);
+}
+#endif  // SOC_BLE_50_SUPPORTED
diff --git a/libraries/BLE/examples/BLE5_extended_scan/ci.json b/libraries/BLE/examples/BLE5_extended_scan/ci.json
new file mode 100644
index 00000000000..184cc25a2b0
--- /dev/null
+++ b/libraries/BLE/examples/BLE5_extended_scan/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_50_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/BLE5_multi_advertising/BLE5_multi_advertising.ino b/libraries/BLE/examples/BLE5_multi_advertising/BLE5_multi_advertising.ino
new file mode 100644
index 00000000000..c4d614786b0
--- /dev/null
+++ b/libraries/BLE/examples/BLE5_multi_advertising/BLE5_multi_advertising.ino
@@ -0,0 +1,141 @@
+/*
+   Simple BLE5 multi advertising example on esp32 C3/S3
+   only ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_IND is backward compatible
+   and can be scanned with BLE4.2 devices
+
+   author: chegewara
+*/
+
+#ifndef CONFIG_BT_BLE_50_FEATURES_SUPPORTED
+#error "This SoC does not support BLE5. Try using ESP32-C3, or ESP32-S3"
+#else
+
+#include <BLEDevice.h>
+#include <BLEAdvertising.h>
+
+esp_ble_gap_ext_adv_params_t ext_adv_params_1M = {
+  .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_CONNECTABLE,
+  .interval_min = 0x30,
+  .interval_max = 0x30,
+  .channel_map = ADV_CHNL_ALL,
+  .own_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr = {0, 0, 0, 0, 0, 0},
+  .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY,
+  .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE,
+  .primary_phy = ESP_BLE_GAP_PHY_CODED,
+  .max_skip = 0,
+  .secondary_phy = ESP_BLE_GAP_PHY_1M,
+  .sid = 0,
+  .scan_req_notif = false,
+};
+
+esp_ble_gap_ext_adv_params_t ext_adv_params_2M = {
+  .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_SCANNABLE,
+  .interval_min = 0x40,
+  .interval_max = 0x40,
+  .channel_map = ADV_CHNL_ALL,
+  .own_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr = {0, 0, 0, 0, 0, 0},
+  .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY,
+  .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE,
+  .primary_phy = ESP_BLE_GAP_PHY_1M,
+  .max_skip = 0,
+  .secondary_phy = ESP_BLE_GAP_PHY_2M,
+  .sid = 1,
+  .scan_req_notif = false,
+};
+
+esp_ble_gap_ext_adv_params_t legacy_adv_params = {
+  .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_IND,
+  .interval_min = 0x45,
+  .interval_max = 0x45,
+  .channel_map = ADV_CHNL_ALL,
+  .own_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr = {0, 0, 0, 0, 0, 0},
+  .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY,
+  .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE,
+  .primary_phy = ESP_BLE_GAP_PHY_1M,
+  .max_skip = 0,
+  .secondary_phy = ESP_BLE_GAP_PHY_1M,
+  .sid = 2,
+  .scan_req_notif = false,
+};
+
+esp_ble_gap_ext_adv_params_t ext_adv_params_coded = {
+  .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_SCANNABLE,
+  .interval_min = 0x50,
+  .interval_max = 0x50,
+  .channel_map = ADV_CHNL_ALL,
+  .own_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr = {0, 0, 0, 0, 0, 0},
+  .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY,
+  .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE,
+  .primary_phy = ESP_BLE_GAP_PHY_1M,
+  .max_skip = 0,
+  .secondary_phy = ESP_BLE_GAP_PHY_CODED,
+  .sid = 3,
+  .scan_req_notif = false,
+};
+
+static uint8_t raw_adv_data_1m[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x12, 0x09, 'E', 'S', 'P', '_', 'M',
+                                    'U',  'L',  'T',  'I',  '_',  'A',  'D',  'V',  '_', '1', 'M', 0X0};
+
+static uint8_t raw_scan_rsp_data_2m[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x12, 0x09, 'E', 'S', 'P', '_', 'M',
+                                         'U',  'L',  'T',  'I',  '_',  'A',  'D',  'V',  '_', '2', 'M', 0X0};
+
+static uint8_t legacy_adv_data[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x15, 0x09, 'E', 'S', 'P', '_', 'M', 'U',
+                                    'L',  'T',  'I',  '_',  'A',  'D',  'V',  '_',  'C', 'O', 'D', 'E', 'D', 0X0};
+
+static uint8_t legacy_scan_rsp_data[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x16, 0x09, 'E', 'S', 'P', '_', 'M', 'U', 'L',
+                                         'T',  'I',  '_',  'A',  'D',  'V',  '_',  'L',  'E', 'G', 'A', 'C', 'Y', 0X0};
+
+static uint8_t raw_scan_rsp_data_coded[] = {0x37, 0x09, 'V', 'E', 'R', 'Y', '_', 'L', 'O', 'N', 'G', '_', 'D', 'E', 'V', 'I', 'C', 'E', '_',
+                                            'N',  'A',  'M', 'E', '_', 'S', 'E', 'N', 'T', '_', 'U', 'S', 'I', 'N', 'G', '_', 'E', 'X', 'T',
+                                            'E',  'N',  'D', 'E', 'D', '_', 'A', 'D', 'V', 'E', 'R', 'T', 'I', 'S', 'I', 'N', 'G', 0X0};
+
+uint8_t addr_1m[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x01};
+uint8_t addr_2m[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x02};
+uint8_t addr_legacy[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x03};
+uint8_t addr_coded[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x04};
+
+BLEMultiAdvertising advert(4);  // max number of advertisement data
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Multi-Advertising...");
+
+  BLEDevice::init("");
+
+  advert.setAdvertisingParams(0, &ext_adv_params_1M);
+  advert.setAdvertisingData(0, sizeof(raw_adv_data_1m), &raw_adv_data_1m[0]);
+  advert.setInstanceAddress(0, addr_1m);
+  advert.setDuration(0);
+
+  advert.setAdvertisingParams(1, &ext_adv_params_2M);
+  advert.setScanRspData(1, sizeof(raw_scan_rsp_data_2m), &raw_scan_rsp_data_2m[0]);
+  advert.setInstanceAddress(1, addr_2m);
+  advert.setDuration(1);
+
+  advert.setAdvertisingParams(2, &legacy_adv_params);
+  advert.setAdvertisingData(2, sizeof(legacy_adv_data), &legacy_adv_data[0]);
+  advert.setScanRspData(2, sizeof(legacy_scan_rsp_data), &legacy_scan_rsp_data[0]);
+  advert.setInstanceAddress(2, addr_legacy);
+  advert.setDuration(2);
+
+  advert.setAdvertisingParams(3, &ext_adv_params_coded);
+  advert.setDuration(3);
+  advert.setScanRspData(3, sizeof(raw_scan_rsp_data_coded), &raw_scan_rsp_data_coded[0]);
+  advert.setInstanceAddress(3, addr_coded);
+
+  delay(1000);
+  advert.start(4, 0);
+}
+
+void loop() {
+  delay(2000);
+}
+#endif
diff --git a/libraries/BLE/examples/BLE5_multi_advertising/ci.json b/libraries/BLE/examples/BLE5_multi_advertising/ci.json
new file mode 100644
index 00000000000..184cc25a2b0
--- /dev/null
+++ b/libraries/BLE/examples/BLE5_multi_advertising/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_50_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/BLE5_periodic_advertising/BLE5_periodic_advertising.ino b/libraries/BLE/examples/BLE5_periodic_advertising/BLE5_periodic_advertising.ino
new file mode 100644
index 00000000000..0b9d4f87630
--- /dev/null
+++ b/libraries/BLE/examples/BLE5_periodic_advertising/BLE5_periodic_advertising.ino
@@ -0,0 +1,68 @@
+/*
+   Simple BLE5 periodic advertising example on esp32 C3/S3
+   only ESP_BLE_GAP_SET_EXT_ADV_PROP_NONCONN_NONSCANNABLE_UNDIRECTED can be used for periodic advertising
+
+   author: chegewara
+*/
+
+#ifndef CONFIG_BT_BLE_50_FEATURES_SUPPORTED
+#error "This SoC does not support BLE5. Try using ESP32-C3, or ESP32-S3"
+#else
+#include <BLEDevice.h>
+#include <BLEAdvertising.h>
+
+esp_ble_gap_ext_adv_params_t ext_adv_params_2M = {
+  .type = ESP_BLE_GAP_SET_EXT_ADV_PROP_NONCONN_NONSCANNABLE_UNDIRECTED,
+  .interval_min = 0x40,
+  .interval_max = 0x40,
+  .channel_map = ADV_CHNL_ALL,
+  .own_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr_type = BLE_ADDR_TYPE_RANDOM,
+  .peer_addr = {0, 0, 0, 0, 0, 0},
+  .filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY,
+  .tx_power = EXT_ADV_TX_PWR_NO_PREFERENCE,
+  .primary_phy = ESP_BLE_GAP_PHY_1M,
+  .max_skip = 0,
+  .secondary_phy = ESP_BLE_GAP_PHY_2M,
+  .sid = 1,
+  .scan_req_notif = false,
+};
+
+static uint8_t raw_scan_rsp_data_2m[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x12, 0x09, 'E', 'S', 'P', '_', 'M',
+                                         'U',  'L',  'T',  'I',  '_',  'A',  'D',  'V',  '_', '2', 'M', 0X0};
+
+static esp_ble_gap_periodic_adv_params_t periodic_adv_params = {
+  .interval_min = 0x320,  // 1000 ms interval
+  .interval_max = 0x640,
+  .properties = 0,  // Do not include TX power
+};
+
+static uint8_t periodic_adv_raw_data[] = {0x02, 0x01, 0x06, 0x02, 0x0a, 0xeb, 0x03, 0x03, 0xab, 0xcd, 0x11, 0x09, 'E', 'S',
+                                          'P',  '_',  'P',  'E',  'R',  'I',  'O',  'D',  'I',  'C',  '_',  'A',  'D', 'V'};
+
+uint8_t addr_2m[6] = {0xc0, 0xde, 0x52, 0x00, 0x00, 0x02};
+
+BLEMultiAdvertising advert(1);  // max number of advertisement data
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Multi-Advertising...");
+
+  BLEDevice::init("");
+
+  advert.setAdvertisingParams(0, &ext_adv_params_2M);
+  advert.setAdvertisingData(0, sizeof(raw_scan_rsp_data_2m), &raw_scan_rsp_data_2m[0]);
+  advert.setInstanceAddress(0, addr_2m);
+  advert.setDuration(0, 0, 0);
+
+  delay(100);
+  advert.start();
+  advert.setPeriodicAdvertisingParams(0, &periodic_adv_params);
+  advert.setPeriodicAdvertisingData(0, sizeof(periodic_adv_raw_data), &periodic_adv_raw_data[0]);
+  advert.startPeriodicAdvertising(0);
+}
+
+void loop() {
+  delay(2000);
+}
+#endif
diff --git a/libraries/BLE/examples/BLE5_periodic_advertising/ci.json b/libraries/BLE/examples/BLE5_periodic_advertising/ci.json
new file mode 100644
index 00000000000..184cc25a2b0
--- /dev/null
+++ b/libraries/BLE/examples/BLE5_periodic_advertising/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_50_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/BLE5_periodic_sync/BLE5_periodic_sync.ino b/libraries/BLE/examples/BLE5_periodic_sync/BLE5_periodic_sync.ino
new file mode 100644
index 00000000000..9e976e6ca6a
--- /dev/null
+++ b/libraries/BLE/examples/BLE5_periodic_sync/BLE5_periodic_sync.ino
@@ -0,0 +1,91 @@
+/*
+   BLE5 extended scan example for esp32 C3 and S3
+   with this code it is simple to scan legacy (BLE4) compatible advertising,
+   and BLE5 extended advertising. New coded added in BLEScan is not changing old behavior,
+   which can be used with old esp32, but is adding functionality to use on C3/S3.
+   With this new API advertised device wont be stored in API, it is now user responsibility
+
+   author: chegewara
+*/
+#ifndef SOC_BLE_50_SUPPORTED
+#warning "This SoC does not support BLE5. Try using ESP32-C3, or ESP32-S3"
+#else
+#include <BLEDevice.h>
+#include <BLEUtils.h>
+#include <BLEScan.h>
+
+BLEScan *pBLEScan;
+static bool periodic_sync = false;
+
+static esp_ble_gap_periodic_adv_sync_params_t periodic_adv_sync_params = {
+  .filter_policy = 0,
+  .sid = 0,
+  .addr_type = BLE_ADDR_TYPE_RANDOM,
+  .addr = {0, 0, 0, 0, 0, 0},
+  .skip = 10,
+  .sync_timeout = 1000,  // timeout: 1000 * 10ms
+};
+
+class MyBLEExtAdvertisingCallbacks : public BLEExtAdvertisingCallbacks {
+  void onResult(esp_ble_gap_ext_adv_report_t params) {
+    uint8_t *adv_name = NULL;
+    uint8_t adv_name_len = 0;
+    adv_name = esp_ble_resolve_adv_data(params.adv_data, ESP_BLE_AD_TYPE_NAME_CMPL, &adv_name_len);
+    if ((adv_name != NULL) && (memcmp(adv_name, "ESP_MULTI_ADV_2M", adv_name_len) == 0) && !periodic_sync) {
+      periodic_sync = true;
+      char adv_temp_name[60] = {'0'};
+      memcpy(adv_temp_name, adv_name, adv_name_len);
+      log_i("Start create sync with the peer device %s", adv_temp_name);
+      periodic_adv_sync_params.sid = params.sid;
+      //          periodic_adv_sync_params.addr_type = params.addr_type;
+      memcpy(periodic_adv_sync_params.addr, params.addr, sizeof(esp_bd_addr_t));
+      esp_ble_gap_periodic_adv_create_sync(&periodic_adv_sync_params);
+    }
+  }
+};
+
+class MyPeriodicScan : public BLEPeriodicScanCallbacks {
+  // void onCreateSync(esp_bt_status_t status){}
+  // void onCancelSync(esp_bt_status_t status){}
+  // void onTerminateSync(esp_bt_status_t status){}
+
+  void onStop(esp_bt_status_t status) {
+    log_i("ESP_GAP_BLE_EXT_SCAN_STOP_COMPLETE_EVT");
+    periodic_sync = false;
+    pBLEScan->startExtScan(0, 0);  // scan duration in n * 10ms, period - repeat after n seconds (period >= duration)
+  }
+
+  void onLostSync(uint16_t sync_handle) {
+    log_i("ESP_GAP_BLE_PERIODIC_ADV_SYNC_LOST_EVT");
+    esp_ble_gap_stop_ext_scan();
+  }
+
+  void onSync(esp_ble_periodic_adv_sync_estab_param_t params) {
+    log_i("ESP_GAP_BLE_PERIODIC_ADV_SYNC_ESTAB_EVT, status %d", params.status);
+    // esp_log_buffer_hex("sync addr", param->periodic_adv_sync_estab.adv_addr, 6);
+    log_i("sync handle %d sid %d perioic adv interval %d adv phy %d", params.sync_handle, params.sid, params.period_adv_interval, params.adv_phy);
+  }
+
+  void onReport(esp_ble_gap_periodic_adv_report_t params) {
+    log_i("periodic adv report, sync handle %d data status %d data len %d rssi %d", params.sync_handle, params.data_status, params.data_length, params.rssi);
+  }
+};
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Periodic scan...");
+
+  BLEDevice::init("");
+  pBLEScan = BLEDevice::getScan();  //create new scan
+  pBLEScan->setExtendedScanCallback(new MyBLEExtAdvertisingCallbacks());
+  pBLEScan->setExtScanParams();  // use with pre-defined/default values, overloaded function allows to pass parameters
+  pBLEScan->setPeriodicScanCallback(new MyPeriodicScan());
+  delay(100);  // it is just for simplicity this example, to let ble stack to set extended scan params
+  pBLEScan->startExtScan(0, 0);
+}
+
+void loop() {
+  delay(2000);
+}
+
+#endif  // SOC_BLE_50_SUPPORTED
diff --git a/libraries/BLE/examples/BLE5_periodic_sync/ci.json b/libraries/BLE/examples/BLE5_periodic_sync/ci.json
new file mode 100644
index 00000000000..184cc25a2b0
--- /dev/null
+++ b/libraries/BLE/examples/BLE5_periodic_sync/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_50_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/BLE_Beacon_Scanner/BLE_Beacon_Scanner.ino b/libraries/BLE/examples/BLE_Beacon_Scanner/BLE_Beacon_Scanner.ino
deleted file mode 100644
index b46baa7c84e..00000000000
--- a/libraries/BLE/examples/BLE_Beacon_Scanner/BLE_Beacon_Scanner.ino
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
-   Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleScan.cpp
-   Ported to Arduino ESP32 by Evandro Copercini
-   Changed to a beacon scanner to report iBeacon, EddystoneURL and EddystoneTLM beacons by beegee-tokyo
-*/
-
-#include <Arduino.h>
-
-#include <BLEDevice.h>
-#include <BLEUtils.h>
-#include <BLEScan.h>
-#include <BLEAdvertisedDevice.h>
-#include <BLEEddystoneURL.h>
-#include <BLEEddystoneTLM.h>
-#include <BLEBeacon.h>
-
-#define ENDIAN_CHANGE_U16(x) ((((x)&0xFF00) >> 8) + (((x)&0xFF) << 8))
-
-int scanTime = 5; //In seconds
-BLEScan *pBLEScan;
-
-class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks
-{
-    void onResult(BLEAdvertisedDevice advertisedDevice)
-    {
-      if (advertisedDevice.haveName())
-      {
-        Serial.print("Device name: ");
-        Serial.println(advertisedDevice.getName().c_str());
-        Serial.println("");
-      }
-
-      if (advertisedDevice.haveServiceUUID())
-      {
-        BLEUUID devUUID = advertisedDevice.getServiceUUID();
-        Serial.print("Found ServiceUUID: ");
-        Serial.println(devUUID.toString().c_str());
-        Serial.println("");
-      }
-      else
-      {
-        if (advertisedDevice.haveManufacturerData() == true)
-        {
-          std::string strManufacturerData = advertisedDevice.getManufacturerData();
-
-          uint8_t cManufacturerData[100];
-          strManufacturerData.copy((char *)cManufacturerData, strManufacturerData.length(), 0);
-
-          if (strManufacturerData.length() == 25 && cManufacturerData[0] == 0x4C && cManufacturerData[1] == 0x00)
-          {
-            Serial.println("Found an iBeacon!");
-            BLEBeacon oBeacon = BLEBeacon();
-            oBeacon.setData(strManufacturerData);
-            Serial.printf("iBeacon Frame\n");
-            Serial.printf("ID: %04X Major: %d Minor: %d UUID: %s Power: %d\n", oBeacon.getManufacturerId(), ENDIAN_CHANGE_U16(oBeacon.getMajor()), ENDIAN_CHANGE_U16(oBeacon.getMinor()), oBeacon.getProximityUUID().toString().c_str(), oBeacon.getSignalPower());
-          }
-          else
-          {
-            Serial.println("Found another manufacturers beacon!");
-            Serial.printf("strManufacturerData: %d ", strManufacturerData.length());
-            for (int i = 0; i < strManufacturerData.length(); i++)
-            {
-              Serial.printf("[%X]", cManufacturerData[i]);
-            }
-            Serial.printf("\n");
-          }
-        }
-        return;
-      }
-
-      uint8_t *payLoad = advertisedDevice.getPayload();
-
-      BLEUUID checkUrlUUID = (uint16_t)0xfeaa;
-
-      if (advertisedDevice.getServiceUUID().equals(checkUrlUUID))
-      {
-        if (payLoad[11] == 0x10)
-        {
-          Serial.println("Found an EddystoneURL beacon!");
-          BLEEddystoneURL foundEddyURL = BLEEddystoneURL();
-          std::string eddyContent((char *)&payLoad[11]); // incomplete EddystoneURL struct!
-
-          foundEddyURL.setData(eddyContent);
-          std::string bareURL = foundEddyURL.getURL();
-          if (bareURL[0] == 0x00)
-          {
-            size_t payLoadLen = advertisedDevice.getPayloadLength();
-            Serial.println("DATA-->");
-            for (int idx = 0; idx < payLoadLen; idx++)
-            {
-              Serial.printf("0x%08X ", payLoad[idx]);
-            }
-            Serial.println("\nInvalid Data");
-            return;
-          }
-
-          Serial.printf("Found URL: %s\n", foundEddyURL.getURL().c_str());
-          Serial.printf("Decoded URL: %s\n", foundEddyURL.getDecodedURL().c_str());
-          Serial.printf("TX power %d\n", foundEddyURL.getPower());
-          Serial.println("\n");
-        }
-        else if (payLoad[11] == 0x20)
-        {
-          Serial.println("Found an EddystoneTLM beacon!");
-          BLEEddystoneTLM foundEddyURL = BLEEddystoneTLM();
-          std::string eddyContent((char *)&payLoad[11]); // incomplete EddystoneURL struct!
-
-          eddyContent = "01234567890123";
-
-          for (int idx = 0; idx < 14; idx++)
-          {
-            eddyContent[idx] = payLoad[idx + 11];
-          }
-
-          foundEddyURL.setData(eddyContent);
-          Serial.printf("Reported battery voltage: %dmV\n", foundEddyURL.getVolt());
-          Serial.printf("Reported temperature from TLM class: %.2fC\n", (double)foundEddyURL.getTemp());
-          int temp = (int)payLoad[16] + (int)(payLoad[15] << 8);
-          float calcTemp = temp / 256.0f;
-          Serial.printf("Reported temperature from data: %.2fC\n", calcTemp);
-          Serial.printf("Reported advertise count: %d\n", foundEddyURL.getCount());
-          Serial.printf("Reported time since last reboot: %ds\n", foundEddyURL.getTime());
-          Serial.println("\n");
-          Serial.print(foundEddyURL.toString().c_str());
-          Serial.println("\n");
-        }
-      }
-    }
-};
-
-void setup()
-{
-  Serial.begin(115200);
-  Serial.println("Scanning...");
-
-  BLEDevice::init("");
-  pBLEScan = BLEDevice::getScan(); //create new scan
-  pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks());
-  pBLEScan->setActiveScan(true); //active scan uses more power, but get results faster
-  pBLEScan->setInterval(100);
-  pBLEScan->setWindow(99); // less or equal setInterval value
-}
-
-void loop()
-{
-  // put your main code here, to run repeatedly:
-  BLEScanResults foundDevices = pBLEScan->start(scanTime, false);
-  Serial.print("Devices found: ");
-  Serial.println(foundDevices.getCount());
-  Serial.println("Scan done!");
-  pBLEScan->clearResults(); // delete results fromBLEScan buffer to release memory
-  delay(2000);
-}
diff --git a/libraries/BLE/examples/BLE_Beacon_Scanner/BLE_Beacon_Scanner.md b/libraries/BLE/examples/BLE_Beacon_Scanner/BLE_Beacon_Scanner.md
deleted file mode 100644
index 558c3e7aec0..00000000000
--- a/libraries/BLE/examples/BLE_Beacon_Scanner/BLE_Beacon_Scanner.md
+++ /dev/null
@@ -1,9 +0,0 @@
-## BLE Beacon Scanner
-
-Initiates a BLE device scan.
-Checks if the discovered devices are 
-- an iBeacon
-- an Eddystone TLM beacon
-- an Eddystone URL beacon
-
-and sends the decoded beacon information over Serial log
\ No newline at end of file
diff --git a/libraries/BLE/examples/BLE_EddystoneTLM_Beacon/BLE_EddystoneTLM_Beacon.ino b/libraries/BLE/examples/BLE_EddystoneTLM_Beacon/BLE_EddystoneTLM_Beacon.ino
deleted file mode 100644
index 96be28cd588..00000000000
--- a/libraries/BLE/examples/BLE_EddystoneTLM_Beacon/BLE_EddystoneTLM_Beacon.ino
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
-   EddystoneTLM beacon by BeeGee based on https://github.com/pcbreflux/espressif/blob/master/esp32/arduino/sketchbook/ESP32_Eddystone_TLM_deepsleep/ESP32_Eddystone_TLM_deepsleep.ino
-   EddystoneTLM frame specification https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md
-*/
-
-/*
-   Create a BLE server that will send periodic Eddystone URL frames.
-   The design of creating the BLE server is:
-   1. Create a BLE Server
-   2. Create advertising data
-   3. Start advertising.
-   4. wait
-   5. Stop advertising.
-   6. deep sleep
-   
-*/
-#include "sys/time.h"
-
-#include <Arduino.h>
-
-#include "BLEDevice.h"
-#include "BLEUtils.h"
-#include "BLEBeacon.h"
-#include "BLEAdvertising.h"
-#include "BLEEddystoneURL.h"
-
-#include "esp_sleep.h"
-
-#define GPIO_DEEP_SLEEP_DURATION 10     // sleep x seconds and then wake up
-RTC_DATA_ATTR static time_t last;    // remember last boot in RTC Memory
-RTC_DATA_ATTR static uint32_t bootcount; // remember number of boots in RTC Memory
-
-// See the following for generating UUIDs:
-// https://www.uuidgenerator.net/
-BLEAdvertising *pAdvertising;
-struct timeval nowTimeStruct;
-
-time_t lastTenth;
-
-#define BEACON_UUID "8ec76ea3-6668-48da-9866-75be8bc86f4d" // UUID 1 128-Bit (may use linux tool uuidgen or random numbers via https://www.uuidgenerator.net/)
-
-// Check
-// https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md
-// and http://www.hugi.scene.org/online/coding/hugi%2015%20-%20cmtadfix.htm
-// for the temperature value. It is a 8.8 fixed-point notation
-void setBeacon()
-{
-  char beacon_data[25];
-  uint16_t beconUUID = 0xFEAA;
-  uint16_t volt = random(2800, 3700); // 3300mV = 3.3V
-  float tempFloat = random(2000, 3100) / 100.0f;
-  Serial.printf("Random temperature is %.2fC\n", tempFloat);
-  int temp = (int)(tempFloat * 256); //(uint16_t)((float)23.00);
-  Serial.printf("Converted to 8.8 format %0X%0X\n", (temp >> 8), (temp & 0xFF));
-
-  BLEAdvertisementData oAdvertisementData = BLEAdvertisementData();
-  BLEAdvertisementData oScanResponseData = BLEAdvertisementData();
-
-  oScanResponseData.setFlags(0x06); // GENERAL_DISC_MODE 0x02 | BR_EDR_NOT_SUPPORTED 0x04
-  oScanResponseData.setCompleteServices(BLEUUID(beconUUID));
-
-  beacon_data[0] = 0x20;                // Eddystone Frame Type (Unencrypted Eddystone-TLM)
-  beacon_data[1] = 0x00;                // TLM version
-  beacon_data[2] = (volt >> 8);           // Battery voltage, 1 mV/bit i.e. 0xCE4 = 3300mV = 3.3V
-  beacon_data[3] = (volt & 0xFF);           //
-  beacon_data[4] = (temp >> 8);           // Beacon temperature
-  beacon_data[5] = (temp & 0xFF);           //
-  beacon_data[6] = ((bootcount & 0xFF000000) >> 24);  // Advertising PDU count
-  beacon_data[7] = ((bootcount & 0xFF0000) >> 16);  //
-  beacon_data[8] = ((bootcount & 0xFF00) >> 8);   //
-  beacon_data[9] = (bootcount & 0xFF);        //
-  beacon_data[10] = ((lastTenth & 0xFF000000) >> 24); // Time since power-on or reboot as 0.1 second resolution counter
-  beacon_data[11] = ((lastTenth & 0xFF0000) >> 16);   //
-  beacon_data[12] = ((lastTenth & 0xFF00) >> 8);    //
-  beacon_data[13] = (lastTenth & 0xFF);       //
-
-  oScanResponseData.setServiceData(BLEUUID(beconUUID), std::string(beacon_data, 14));
-  oAdvertisementData.setName("TLMBeacon");
-  pAdvertising->setAdvertisementData(oAdvertisementData);
-  pAdvertising->setScanResponseData(oScanResponseData);
-}
-
-void setup()
-{
-
-  Serial.begin(115200);
-  gettimeofday(&nowTimeStruct, NULL);
-
-  Serial.printf("start ESP32 %d\n", bootcount++);
-
-  Serial.printf("deep sleep (%lds since last reset, %lds since last boot)\n", nowTimeStruct.tv_sec, nowTimeStruct.tv_sec - last);
-
-  last = nowTimeStruct.tv_sec;
-  lastTenth = nowTimeStruct.tv_sec * 10; // Time since last reset as 0.1 second resolution counter
-
-  // Create the BLE Device
-  BLEDevice::init("TLMBeacon");
-
-  BLEDevice::setPower(ESP_PWR_LVL_N12);
-
-  pAdvertising = BLEDevice::getAdvertising();
-
-  setBeacon();
-  // Start advertising
-  pAdvertising->start();
-  Serial.println("Advertizing started for 10s ...");
-  delay(10000);
-  pAdvertising->stop();
-  Serial.printf("enter deep sleep for 10s\n");
-  esp_deep_sleep(1000000LL * GPIO_DEEP_SLEEP_DURATION);
-  Serial.printf("in deep sleep\n");
-}
-
-void loop()
-{
-}
diff --git a/libraries/BLE/examples/BLE_EddystoneURL_Beacon/BLE_EddystoneURL_Beacon.ino b/libraries/BLE/examples/BLE_EddystoneURL_Beacon/BLE_EddystoneURL_Beacon.ino
deleted file mode 100644
index 335ea1ffbe6..00000000000
--- a/libraries/BLE/examples/BLE_EddystoneURL_Beacon/BLE_EddystoneURL_Beacon.ino
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
-   EddystoneURL beacon by BeeGee
-   EddystoneURL frame specification https://github.com/google/eddystone/blob/master/eddystone-url/README.md
-
-*/
-
-/*
-   Create a BLE server that will send periodic Eddystone URL frames.
-   The design of creating the BLE server is:
-   1. Create a BLE Server
-   2. Create advertising data
-   3. Start advertising.
-   4. wait
-   5. Stop advertising.
-   6. deep sleep
-
-*/
-#include "sys/time.h"
-
-#include <Arduino.h>
-
-#include "BLEDevice.h"
-#include "BLEUtils.h"
-#include "BLEBeacon.h"
-#include "BLEAdvertising.h"
-#include "BLEEddystoneURL.h"
-
-#include "esp_sleep.h"
-
-#define GPIO_DEEP_SLEEP_DURATION 10     // sleep x seconds and then wake up
-RTC_DATA_ATTR static time_t last;    // remember last boot in RTC Memory
-RTC_DATA_ATTR static uint32_t bootcount; // remember number of boots in RTC Memory
-
-// See the following for generating UUIDs:
-// https://www.uuidgenerator.net/
-BLEAdvertising *pAdvertising;
-struct timeval now;
-
-#define BEACON_UUID "8ec76ea3-6668-48da-9866-75be8bc86f4d" // UUID 1 128-Bit (may use linux tool uuidgen or random numbers via https://www.uuidgenerator.net/)
-
-static const char *eddystone_url_prefix_subs[] = {
-  "http://www.",
-  "https://www.",
-  "http://",
-  "https://",
-  "urn:uuid:",
-  NULL
-};
-
-static const char *eddystone_url_suffix_subs[] = {
-  ".com/",
-  ".org/",
-  ".edu/",
-  ".net/",
-  ".info/",
-  ".biz/",
-  ".gov/",
-  ".com",
-  ".org",
-  ".edu",
-  ".net",
-  ".info",
-  ".biz",
-  ".gov",
-  NULL
-};
-
-static int string_begin_with(const char *str, const char *prefix)
-{
-  int prefix_len = strlen(prefix);
-  if (strncmp(prefix, str, prefix_len) == 0)
-  {
-    return prefix_len;
-  }
-  return 0;
-}
-
-void setBeacon()
-{
-  BLEAdvertisementData oAdvertisementData = BLEAdvertisementData();
-  BLEAdvertisementData oScanResponseData = BLEAdvertisementData();
-
-  const char url[] = "https://d.giesecke.tk";
-
-  int scheme_len, ext_len = 1, i, idx, url_idx;
-  char *ret_data;
-  int url_len = strlen(url);
-
-  ret_data = (char *)calloc(1, url_len + 13);
-
-  ret_data[0] = 2;   // Len
-  ret_data[1] = 0x01;  // Type Flags
-  ret_data[2] = 0x06;  // GENERAL_DISC_MODE 0x02 | BR_EDR_NOT_SUPPORTED 0x04
-  ret_data[3] = 3;   // Len
-  ret_data[4] = 0x03;  // Type 16-Bit UUID
-  ret_data[5] = 0xAA;  // Eddystone UUID 2 -> 0xFEAA LSB
-  ret_data[6] = 0xFE;  // Eddystone UUID 1 MSB
-  ret_data[7] = 19; // Length of Beacon Data
-  ret_data[8] = 0x16;  // Type Service Data
-  ret_data[9] = 0xAA;  // Eddystone UUID 2 -> 0xFEAA LSB
-  ret_data[10] = 0xFE; // Eddystone UUID 1 MSB
-  ret_data[11] = 0x10; // Eddystone Frame Type
-  ret_data[12] = 0xF4; // Beacons TX power at 0m
-
-  i = 0, idx = 13, url_idx = 0;
-
-  //replace prefix
-  scheme_len = 0;
-  while (eddystone_url_prefix_subs[i] != NULL)
-  {
-    if ((scheme_len = string_begin_with(url, eddystone_url_prefix_subs[i])) > 0)
-    {
-      ret_data[idx] = i;
-      idx++;
-      url_idx += scheme_len;
-      break;
-    }
-    i++;
-  }
-  while (url_idx < url_len)
-  {
-    i = 0;
-    ret_data[idx] = url[url_idx];
-    ext_len = 1;
-    while (eddystone_url_suffix_subs[i] != NULL)
-    {
-      if ((ext_len = string_begin_with(&url[url_idx], eddystone_url_suffix_subs[i])) > 0)
-      {
-        ret_data[idx] = i;
-        break;
-      }
-      else
-      {
-        ext_len = 1; //inc 1
-      }
-      i++;
-    }
-    url_idx += ext_len;
-    idx++;
-  }
-  ret_data[7] = idx - 8;
-
-  Serial.printf("struct size %d url size %d reported len %d\n",
-                url_len + 13,
-                url_len, ret_data[7]);
-
-  Serial.printf("URL in data %s\n", &ret_data[13]);
-
-  std::string eddyStoneData(ret_data);
-
-  oAdvertisementData.addData(eddyStoneData);
-  oScanResponseData.setName("URLBeacon");
-  pAdvertising->setAdvertisementData(oAdvertisementData);
-  pAdvertising->setScanResponseData(oScanResponseData);
-}
-
-void setup()
-{
-
-  Serial.begin(115200);
-  gettimeofday(&now, NULL);
-
-  Serial.printf("start ESP32 %d\n", bootcount++);
-
-  Serial.printf("deep sleep (%lds since last reset, %lds since last boot)\n", now.tv_sec, now.tv_sec - last);
-
-  last = now.tv_sec;
-
-  // Create the BLE Device
-  BLEDevice::init("URLBeacon");
-
-  BLEDevice::setPower(ESP_PWR_LVL_N12);
-
-  // Create the BLE Server
-  // BLEServer *pServer = BLEDevice::createServer(); // <-- no longer required to instantiate BLEServer, less flash and ram usage
-
-  pAdvertising = BLEDevice::getAdvertising();
-
-  setBeacon();
-  // Start advertising
-  pAdvertising->start();
-  Serial.println("Advertizing started...");
-  delay(10000);
-  pAdvertising->stop();
-  Serial.printf("enter deep sleep\n");
-  esp_deep_sleep(1000000LL * GPIO_DEEP_SLEEP_DURATION);
-  Serial.printf("in deep sleep\n");
-}
-
-void loop()
-{
-}
diff --git a/libraries/BLE/examples/BLE_client/BLE_client.ino b/libraries/BLE/examples/BLE_client/BLE_client.ino
deleted file mode 100644
index 55d9fa0de6a..00000000000
--- a/libraries/BLE/examples/BLE_client/BLE_client.ino
+++ /dev/null
@@ -1,161 +0,0 @@
-/**
- * A BLE client example that is rich in capabilities.
- * There is a lot new capabilities implemented.
- * author unknown
- * updated by chegewara
- */
-
-#include "BLEDevice.h"
-//#include "BLEScan.h"
-
-// The remote service we wish to connect to.
-static BLEUUID serviceUUID("4fafc201-1fb5-459e-8fcc-c5c9c331914b");
-// The characteristic of the remote service we are interested in.
-static BLEUUID    charUUID("beb5483e-36e1-4688-b7f5-ea07361b26a8");
-
-static boolean doConnect = false;
-static boolean connected = false;
-static boolean doScan = false;
-static BLERemoteCharacteristic* pRemoteCharacteristic;
-static BLEAdvertisedDevice* myDevice;
-
-static void notifyCallback(
-  BLERemoteCharacteristic* pBLERemoteCharacteristic,
-  uint8_t* pData,
-  size_t length,
-  bool isNotify) {
-    Serial.print("Notify callback for characteristic ");
-    Serial.print(pBLERemoteCharacteristic->getUUID().toString().c_str());
-    Serial.print(" of data length ");
-    Serial.println(length);
-    Serial.print("data: ");
-    Serial.println((char*)pData);
-}
-
-class MyClientCallback : public BLEClientCallbacks {
-  void onConnect(BLEClient* pclient) {
-  }
-
-  void onDisconnect(BLEClient* pclient) {
-    connected = false;
-    Serial.println("onDisconnect");
-  }
-};
-
-bool connectToServer() {
-    Serial.print("Forming a connection to ");
-    Serial.println(myDevice->getAddress().toString().c_str());
-    
-    BLEClient*  pClient  = BLEDevice::createClient();
-    Serial.println(" - Created client");
-
-    pClient->setClientCallbacks(new MyClientCallback());
-
-    // Connect to the remove BLE Server.
-    pClient->connect(myDevice);  // if you pass BLEAdvertisedDevice instead of address, it will be recognized type of peer device address (public or private)
-    Serial.println(" - Connected to server");
-
-    // Obtain a reference to the service we are after in the remote BLE server.
-    BLERemoteService* pRemoteService = pClient->getService(serviceUUID);
-    if (pRemoteService == nullptr) {
-      Serial.print("Failed to find our service UUID: ");
-      Serial.println(serviceUUID.toString().c_str());
-      pClient->disconnect();
-      return false;
-    }
-    Serial.println(" - Found our service");
-
-
-    // Obtain a reference to the characteristic in the service of the remote BLE server.
-    pRemoteCharacteristic = pRemoteService->getCharacteristic(charUUID);
-    if (pRemoteCharacteristic == nullptr) {
-      Serial.print("Failed to find our characteristic UUID: ");
-      Serial.println(charUUID.toString().c_str());
-      pClient->disconnect();
-      return false;
-    }
-    Serial.println(" - Found our characteristic");
-
-    // Read the value of the characteristic.
-    if(pRemoteCharacteristic->canRead()) {
-      std::string value = pRemoteCharacteristic->readValue();
-      Serial.print("The characteristic value was: ");
-      Serial.println(value.c_str());
-    }
-
-    if(pRemoteCharacteristic->canNotify())
-      pRemoteCharacteristic->registerForNotify(notifyCallback);
-
-    connected = true;
-    return true;
-}
-/**
- * Scan for BLE servers and find the first one that advertises the service we are looking for.
- */
-class MyAdvertisedDeviceCallbacks: public BLEAdvertisedDeviceCallbacks {
- /**
-   * Called for each advertising BLE server.
-   */
-  void onResult(BLEAdvertisedDevice advertisedDevice) {
-    Serial.print("BLE Advertised Device found: ");
-    Serial.println(advertisedDevice.toString().c_str());
-
-    // We have found a device, let us now see if it contains the service we are looking for.
-    if (advertisedDevice.haveServiceUUID() && advertisedDevice.isAdvertisingService(serviceUUID)) {
-
-      BLEDevice::getScan()->stop();
-      myDevice = new BLEAdvertisedDevice(advertisedDevice);
-      doConnect = true;
-      doScan = true;
-
-    } // Found our server
-  } // onResult
-}; // MyAdvertisedDeviceCallbacks
-
-
-void setup() {
-  Serial.begin(115200);
-  Serial.println("Starting Arduino BLE Client application...");
-  BLEDevice::init("");
-
-  // Retrieve a Scanner and set the callback we want to use to be informed when we
-  // have detected a new device.  Specify that we want active scanning and start the
-  // scan to run for 5 seconds.
-  BLEScan* pBLEScan = BLEDevice::getScan();
-  pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks());
-  pBLEScan->setInterval(1349);
-  pBLEScan->setWindow(449);
-  pBLEScan->setActiveScan(true);
-  pBLEScan->start(5, false);
-} // End of setup.
-
-
-// This is the Arduino main loop function.
-void loop() {
-
-  // If the flag "doConnect" is true then we have scanned for and found the desired
-  // BLE Server with which we wish to connect.  Now we connect to it.  Once we are 
-  // connected we set the connected flag to be true.
-  if (doConnect == true) {
-    if (connectToServer()) {
-      Serial.println("We are now connected to the BLE Server.");
-    } else {
-      Serial.println("We have failed to connect to the server; there is nothin more we will do.");
-    }
-    doConnect = false;
-  }
-
-  // If we are connected to a peer BLE Server, update the characteristic each time we are reached
-  // with the current time since boot.
-  if (connected) {
-    String newValue = "Time since boot: " + String(millis()/1000);
-    Serial.println("Setting new characteristic value to \"" + newValue + "\"");
-    
-    // Set the characteristic's value to be the array of bytes that is actually a string.
-    pRemoteCharacteristic->writeValue(newValue.c_str(), newValue.length());
-  }else if(doScan){
-    BLEDevice::getScan()->start(0);  // this is just example to start scan after disconnect, most likely there is better way to do it in arduino
-  }
-  
-  delay(1000); // Delay a second between loops.
-} // End of loop
diff --git a/libraries/BLE/examples/BLE_iBeacon/BLE_iBeacon.ino b/libraries/BLE/examples/BLE_iBeacon/BLE_iBeacon.ino
deleted file mode 100644
index 324e821e95c..00000000000
--- a/libraries/BLE/examples/BLE_iBeacon/BLE_iBeacon.ino
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
-   Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleScan.cpp
-   Ported to Arduino ESP32 by pcbreflux
-*/
-
- 
-/*
-   Create a BLE server that will send periodic iBeacon frames.
-   The design of creating the BLE server is:
-   1. Create a BLE Server
-   2. Create advertising data
-   3. Start advertising.
-   4. wait
-   5. Stop advertising.
-   6. deep sleep
-   
-*/
-#include "sys/time.h"
-
-#include "BLEDevice.h"
-#include "BLEUtils.h"
-#include "BLEBeacon.h"
-#include "esp_sleep.h"
-
-#define GPIO_DEEP_SLEEP_DURATION     10  // sleep x seconds and then wake up
-RTC_DATA_ATTR static time_t last;        // remember last boot in RTC Memory
-RTC_DATA_ATTR static uint32_t bootcount; // remember number of boots in RTC Memory
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-uint8_t temprature_sens_read();
-//uint8_t g_phyFuns;
-
-#ifdef __cplusplus
-}
-#endif
-
-// See the following for generating UUIDs:
-// https://www.uuidgenerator.net/
-BLEAdvertising *pAdvertising;
-struct timeval now;
-
-#define BEACON_UUID           "8ec76ea3-6668-48da-9866-75be8bc86f4d" // UUID 1 128-Bit (may use linux tool uuidgen or random numbers via https://www.uuidgenerator.net/)
-
-void setBeacon() {
-
-  BLEBeacon oBeacon = BLEBeacon();
-  oBeacon.setManufacturerId(0x4C00); // fake Apple 0x004C LSB (ENDIAN_CHANGE_U16!)
-  oBeacon.setProximityUUID(BLEUUID(BEACON_UUID));
-  oBeacon.setMajor((bootcount & 0xFFFF0000) >> 16);
-  oBeacon.setMinor(bootcount&0xFFFF);
-  BLEAdvertisementData oAdvertisementData = BLEAdvertisementData();
-  BLEAdvertisementData oScanResponseData = BLEAdvertisementData();
-  
-  oAdvertisementData.setFlags(0x04); // BR_EDR_NOT_SUPPORTED 0x04
-  
-  std::string strServiceData = "";
-  
-  strServiceData += (char)26;     // Len
-  strServiceData += (char)0xFF;   // Type
-  strServiceData += oBeacon.getData(); 
-  oAdvertisementData.addData(strServiceData);
-  
-  pAdvertising->setAdvertisementData(oAdvertisementData);
-  pAdvertising->setScanResponseData(oScanResponseData);
-  pAdvertising->setAdvertisementType(ADV_TYPE_NONCONN_IND);
-
-}
-
-void setup() {
-
-    
-  Serial.begin(115200);
-  gettimeofday(&now, NULL);
-
-  Serial.printf("start ESP32 %d\n",bootcount++);
-
-  Serial.printf("deep sleep (%lds since last reset, %lds since last boot)\n",now.tv_sec,now.tv_sec-last);
-
-  last = now.tv_sec;
-  
-  // Create the BLE Device
-  BLEDevice::init("");
-
-  // Create the BLE Server
-  // BLEServer *pServer = BLEDevice::createServer(); // <-- no longer required to instantiate BLEServer, less flash and ram usage
-
-  pAdvertising = BLEDevice::getAdvertising();
-  
-  setBeacon();
-   // Start advertising
-  pAdvertising->start();
-  Serial.println("Advertizing started...");
-  delay(100);
-  pAdvertising->stop();
-  Serial.printf("enter deep sleep\n");
-  esp_deep_sleep(1000000LL * GPIO_DEEP_SLEEP_DURATION);
-  Serial.printf("in deep sleep\n");
-}
-
-void loop() {
-}
diff --git a/libraries/BLE/examples/BLE_notify/BLE_notify.ino b/libraries/BLE/examples/BLE_notify/BLE_notify.ino
deleted file mode 100644
index 42b9e7273f3..00000000000
--- a/libraries/BLE/examples/BLE_notify/BLE_notify.ino
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
-    Video: https://www.youtube.com/watch?v=oCMOYS71NIU
-    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleNotify.cpp
-    Ported to Arduino ESP32 by Evandro Copercini
-    updated by chegewara
-
-   Create a BLE server that, once we receive a connection, will send periodic notifications.
-   The service advertises itself as: 4fafc201-1fb5-459e-8fcc-c5c9c331914b
-   And has a characteristic of: beb5483e-36e1-4688-b7f5-ea07361b26a8
-
-   The design of creating the BLE server is:
-   1. Create a BLE Server
-   2. Create a BLE Service
-   3. Create a BLE Characteristic on the Service
-   4. Create a BLE Descriptor on the characteristic
-   5. Start the service.
-   6. Start advertising.
-
-   A connect hander associated with the server starts a background task that performs notification
-   every couple of seconds.
-*/
-#include <BLEDevice.h>
-#include <BLEServer.h>
-#include <BLEUtils.h>
-#include <BLE2902.h>
-
-BLEServer* pServer = NULL;
-BLECharacteristic* pCharacteristic = NULL;
-bool deviceConnected = false;
-bool oldDeviceConnected = false;
-uint32_t value = 0;
-
-// See the following for generating UUIDs:
-// https://www.uuidgenerator.net/
-
-#define SERVICE_UUID        "4fafc201-1fb5-459e-8fcc-c5c9c331914b"
-#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8"
-
-
-class MyServerCallbacks: public BLEServerCallbacks {
-    void onConnect(BLEServer* pServer) {
-      deviceConnected = true;
-    };
-
-    void onDisconnect(BLEServer* pServer) {
-      deviceConnected = false;
-    }
-};
-
-
-
-void setup() {
-  Serial.begin(115200);
-
-  // Create the BLE Device
-  BLEDevice::init("ESP32");
-
-  // Create the BLE Server
-  pServer = BLEDevice::createServer();
-  pServer->setCallbacks(new MyServerCallbacks());
-
-  // Create the BLE Service
-  BLEService *pService = pServer->createService(SERVICE_UUID);
-
-  // Create a BLE Characteristic
-  pCharacteristic = pService->createCharacteristic(
-                      CHARACTERISTIC_UUID,
-                      BLECharacteristic::PROPERTY_READ   |
-                      BLECharacteristic::PROPERTY_WRITE  |
-                      BLECharacteristic::PROPERTY_NOTIFY |
-                      BLECharacteristic::PROPERTY_INDICATE
-                    );
-
-  // https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.client_characteristic_configuration.xml
-  // Create a BLE Descriptor
-  pCharacteristic->addDescriptor(new BLE2902());
-
-  // Start the service
-  pService->start();
-
-  // Start advertising
-  BLEAdvertising *pAdvertising = BLEDevice::getAdvertising();
-  pAdvertising->addServiceUUID(SERVICE_UUID);
-  pAdvertising->setScanResponse(false);
-  pAdvertising->setMinPreferred(0x0);  // set value to 0x00 to not advertise this parameter
-  BLEDevice::startAdvertising();
-  Serial.println("Waiting a client connection to notify...");
-}
-
-void loop() {
-    // notify changed value
-    if (deviceConnected) {
-        pCharacteristic->setValue((uint8_t*)&value, 4);
-        pCharacteristic->notify();
-        value++;
-        delay(3); // bluetooth stack will go into congestion, if too many packets are sent, in 6 hours test i was able to go as low as 3ms
-    }
-    // disconnecting
-    if (!deviceConnected && oldDeviceConnected) {
-        delay(500); // give the bluetooth stack the chance to get things ready
-        pServer->startAdvertising(); // restart advertising
-        Serial.println("start advertising");
-        oldDeviceConnected = deviceConnected;
-    }
-    // connecting
-    if (deviceConnected && !oldDeviceConnected) {
-        // do stuff here on connecting
-        oldDeviceConnected = deviceConnected;
-    }
-}
\ No newline at end of file
diff --git a/libraries/BLE/examples/BLE_scan/BLE_scan.ino b/libraries/BLE/examples/BLE_scan/BLE_scan.ino
deleted file mode 100644
index 094f7933ac7..00000000000
--- a/libraries/BLE/examples/BLE_scan/BLE_scan.ino
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-   Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleScan.cpp
-   Ported to Arduino ESP32 by Evandro Copercini
-*/
-
-#include <BLEDevice.h>
-#include <BLEUtils.h>
-#include <BLEScan.h>
-#include <BLEAdvertisedDevice.h>
-
-int scanTime = 5; //In seconds
-BLEScan* pBLEScan;
-
-class MyAdvertisedDeviceCallbacks: public BLEAdvertisedDeviceCallbacks {
-    void onResult(BLEAdvertisedDevice advertisedDevice) {
-      Serial.printf("Advertised Device: %s \n", advertisedDevice.toString().c_str());
-    }
-};
-
-void setup() {
-  Serial.begin(115200);
-  Serial.println("Scanning...");
-
-  BLEDevice::init("");
-  pBLEScan = BLEDevice::getScan(); //create new scan
-  pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks());
-  pBLEScan->setActiveScan(true); //active scan uses more power, but get results faster
-  pBLEScan->setInterval(100);
-  pBLEScan->setWindow(99);  // less or equal setInterval value
-}
-
-void loop() {
-  // put your main code here, to run repeatedly:
-  BLEScanResults foundDevices = pBLEScan->start(scanTime, false);
-  Serial.print("Devices found: ");
-  Serial.println(foundDevices.getCount());
-  Serial.println("Scan done!");
-  pBLEScan->clearResults();   // delete results fromBLEScan buffer to release memory
-  delay(2000);
-}
\ No newline at end of file
diff --git a/libraries/BLE/examples/BLE_server/BLE_server.ino b/libraries/BLE/examples/BLE_server/BLE_server.ino
deleted file mode 100644
index 3f9176acf5e..00000000000
--- a/libraries/BLE/examples/BLE_server/BLE_server.ino
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
-    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleServer.cpp
-    Ported to Arduino ESP32 by Evandro Copercini
-    updates by chegewara
-*/
-
-#include <BLEDevice.h>
-#include <BLEUtils.h>
-#include <BLEServer.h>
-
-// See the following for generating UUIDs:
-// https://www.uuidgenerator.net/
-
-#define SERVICE_UUID        "4fafc201-1fb5-459e-8fcc-c5c9c331914b"
-#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8"
-
-void setup() {
-  Serial.begin(115200);
-  Serial.println("Starting BLE work!");
-
-  BLEDevice::init("Long name works now");
-  BLEServer *pServer = BLEDevice::createServer();
-  BLEService *pService = pServer->createService(SERVICE_UUID);
-  BLECharacteristic *pCharacteristic = pService->createCharacteristic(
-                                         CHARACTERISTIC_UUID,
-                                         BLECharacteristic::PROPERTY_READ |
-                                         BLECharacteristic::PROPERTY_WRITE
-                                       );
-
-  pCharacteristic->setValue("Hello World says Neil");
-  pService->start();
-  // BLEAdvertising *pAdvertising = pServer->getAdvertising();  // this still is working for backward compatibility
-  BLEAdvertising *pAdvertising = BLEDevice::getAdvertising();
-  pAdvertising->addServiceUUID(SERVICE_UUID);
-  pAdvertising->setScanResponse(true);
-  pAdvertising->setMinPreferred(0x06);  // functions that help with iPhone connections issue
-  pAdvertising->setMinPreferred(0x12);
-  BLEDevice::startAdvertising();
-  Serial.println("Characteristic defined! Now you can read it in your phone!");
-}
-
-void loop() {
-  // put your main code here, to run repeatedly:
-  delay(2000);
-}
\ No newline at end of file
diff --git a/libraries/BLE/examples/BLE_server_multiconnect/BLE_server_multiconnect.ino b/libraries/BLE/examples/BLE_server_multiconnect/BLE_server_multiconnect.ino
deleted file mode 100644
index 90704ef16ad..00000000000
--- a/libraries/BLE/examples/BLE_server_multiconnect/BLE_server_multiconnect.ino
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
-    Video: https://www.youtube.com/watch?v=oCMOYS71NIU
-    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleNotify.cpp
-    Ported to Arduino ESP32 by Evandro Copercini
-    updated by chegewara
-
-   Create a BLE server that, once we receive a connection, will send periodic notifications.
-   The service advertises itself as: 4fafc201-1fb5-459e-8fcc-c5c9c331914b
-   And has a characteristic of: beb5483e-36e1-4688-b7f5-ea07361b26a8
-
-   The design of creating the BLE server is:
-   1. Create a BLE Server
-   2. Create a BLE Service
-   3. Create a BLE Characteristic on the Service
-   4. Create a BLE Descriptor on the characteristic
-   5. Start the service.
-   6. Start advertising.
-
-   A connect hander associated with the server starts a background task that performs notification
-   every couple of seconds.
-*/
-#include <BLEDevice.h>
-#include <BLEServer.h>
-#include <BLEUtils.h>
-#include <BLE2902.h>
-
-BLEServer* pServer = NULL;
-BLECharacteristic* pCharacteristic = NULL;
-bool deviceConnected = false;
-bool oldDeviceConnected = false;
-uint32_t value = 0;
-
-// See the following for generating UUIDs:
-// https://www.uuidgenerator.net/
-
-#define SERVICE_UUID        "4fafc201-1fb5-459e-8fcc-c5c9c331914b"
-#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8"
-
-
-class MyServerCallbacks: public BLEServerCallbacks {
-    void onConnect(BLEServer* pServer) {
-      deviceConnected = true;
-      BLEDevice::startAdvertising();
-    };
-
-    void onDisconnect(BLEServer* pServer) {
-      deviceConnected = false;
-    }
-};
-
-
-
-void setup() {
-  Serial.begin(115200);
-
-  // Create the BLE Device
-  BLEDevice::init("ESP32");
-
-  // Create the BLE Server
-  pServer = BLEDevice::createServer();
-  pServer->setCallbacks(new MyServerCallbacks());
-
-  // Create the BLE Service
-  BLEService *pService = pServer->createService(SERVICE_UUID);
-
-  // Create a BLE Characteristic
-  pCharacteristic = pService->createCharacteristic(
-                      CHARACTERISTIC_UUID,
-                      BLECharacteristic::PROPERTY_READ   |
-                      BLECharacteristic::PROPERTY_WRITE  |
-                      BLECharacteristic::PROPERTY_NOTIFY |
-                      BLECharacteristic::PROPERTY_INDICATE
-                    );
-
-  // https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.client_characteristic_configuration.xml
-  // Create a BLE Descriptor
-  pCharacteristic->addDescriptor(new BLE2902());
-
-  // Start the service
-  pService->start();
-
-  // Start advertising
-  BLEAdvertising *pAdvertising = BLEDevice::getAdvertising();
-  pAdvertising->addServiceUUID(SERVICE_UUID);
-  pAdvertising->setScanResponse(false);
-  pAdvertising->setMinPreferred(0x0);  // set value to 0x00 to not advertise this parameter
-  BLEDevice::startAdvertising();
-  Serial.println("Waiting a client connection to notify...");
-}
-
-void loop() {
-    // notify changed value
-    if (deviceConnected) {
-        pCharacteristic->setValue((uint8_t*)&value, 4);
-        pCharacteristic->notify();
-        value++;
-        delay(10); // bluetooth stack will go into congestion, if too many packets are sent, in 6 hours test i was able to go as low as 3ms
-    }
-    // disconnecting
-    if (!deviceConnected && oldDeviceConnected) {
-        delay(500); // give the bluetooth stack the chance to get things ready
-        pServer->startAdvertising(); // restart advertising
-        Serial.println("start advertising");
-        oldDeviceConnected = deviceConnected;
-    }
-    // connecting
-    if (deviceConnected && !oldDeviceConnected) {
-        // do stuff here on connecting
-        oldDeviceConnected = deviceConnected;
-    }
-}
diff --git a/libraries/BLE/examples/BLE_uart/BLE_uart.ino b/libraries/BLE/examples/BLE_uart/BLE_uart.ino
deleted file mode 100644
index 35b570b9192..00000000000
--- a/libraries/BLE/examples/BLE_uart/BLE_uart.ino
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
-    Video: https://www.youtube.com/watch?v=oCMOYS71NIU
-    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleNotify.cpp
-    Ported to Arduino ESP32 by Evandro Copercini
-
-   Create a BLE server that, once we receive a connection, will send periodic notifications.
-   The service advertises itself as: 6E400001-B5A3-F393-E0A9-E50E24DCCA9E
-   Has a characteristic of: 6E400002-B5A3-F393-E0A9-E50E24DCCA9E - used for receiving data with "WRITE" 
-   Has a characteristic of: 6E400003-B5A3-F393-E0A9-E50E24DCCA9E - used to send data with  "NOTIFY"
-
-   The design of creating the BLE server is:
-   1. Create a BLE Server
-   2. Create a BLE Service
-   3. Create a BLE Characteristic on the Service
-   4. Create a BLE Descriptor on the characteristic
-   5. Start the service.
-   6. Start advertising.
-
-   In this example rxValue is the data received (only accessible inside that function).
-   And txValue is the data to be sent, in this example just a byte incremented every second. 
-*/
-#include <BLEDevice.h>
-#include <BLEServer.h>
-#include <BLEUtils.h>
-#include <BLE2902.h>
-
-BLEServer *pServer = NULL;
-BLECharacteristic * pTxCharacteristic;
-bool deviceConnected = false;
-bool oldDeviceConnected = false;
-uint8_t txValue = 0;
-
-// See the following for generating UUIDs:
-// https://www.uuidgenerator.net/
-
-#define SERVICE_UUID           "6E400001-B5A3-F393-E0A9-E50E24DCCA9E" // UART service UUID
-#define CHARACTERISTIC_UUID_RX "6E400002-B5A3-F393-E0A9-E50E24DCCA9E"
-#define CHARACTERISTIC_UUID_TX "6E400003-B5A3-F393-E0A9-E50E24DCCA9E"
-
-
-class MyServerCallbacks: public BLEServerCallbacks {
-    void onConnect(BLEServer* pServer) {
-      deviceConnected = true;
-    };
-
-    void onDisconnect(BLEServer* pServer) {
-      deviceConnected = false;
-    }
-};
-
-class MyCallbacks: public BLECharacteristicCallbacks {
-    void onWrite(BLECharacteristic *pCharacteristic) {
-      std::string rxValue = pCharacteristic->getValue();
-
-      if (rxValue.length() > 0) {
-        Serial.println("*********");
-        Serial.print("Received Value: ");
-        for (int i = 0; i < rxValue.length(); i++)
-          Serial.print(rxValue[i]);
-
-        Serial.println();
-        Serial.println("*********");
-      }
-    }
-};
-
-
-void setup() {
-  Serial.begin(115200);
-
-  // Create the BLE Device
-  BLEDevice::init("UART Service");
-
-  // Create the BLE Server
-  pServer = BLEDevice::createServer();
-  pServer->setCallbacks(new MyServerCallbacks());
-
-  // Create the BLE Service
-  BLEService *pService = pServer->createService(SERVICE_UUID);
-
-  // Create a BLE Characteristic
-  pTxCharacteristic = pService->createCharacteristic(
-										CHARACTERISTIC_UUID_TX,
-										BLECharacteristic::PROPERTY_NOTIFY
-									);
-                      
-  pTxCharacteristic->addDescriptor(new BLE2902());
-
-  BLECharacteristic * pRxCharacteristic = pService->createCharacteristic(
-											 CHARACTERISTIC_UUID_RX,
-											BLECharacteristic::PROPERTY_WRITE
-										);
-
-  pRxCharacteristic->setCallbacks(new MyCallbacks());
-
-  // Start the service
-  pService->start();
-
-  // Start advertising
-  pServer->getAdvertising()->start();
-  Serial.println("Waiting a client connection to notify...");
-}
-
-void loop() {
-
-    if (deviceConnected) {
-        pTxCharacteristic->setValue(&txValue, 1);
-        pTxCharacteristic->notify();
-        txValue++;
-		delay(10); // bluetooth stack will go into congestion, if too many packets are sent
-	}
-
-    // disconnecting
-    if (!deviceConnected && oldDeviceConnected) {
-        delay(500); // give the bluetooth stack the chance to get things ready
-        pServer->startAdvertising(); // restart advertising
-        Serial.println("start advertising");
-        oldDeviceConnected = deviceConnected;
-    }
-    // connecting
-    if (deviceConnected && !oldDeviceConnected) {
-		// do stuff here on connecting
-        oldDeviceConnected = deviceConnected;
-    }
-}
diff --git a/libraries/BLE/examples/BLE_write/BLE_write.ino b/libraries/BLE/examples/BLE_write/BLE_write.ino
deleted file mode 100644
index 24a0cd23d7a..00000000000
--- a/libraries/BLE/examples/BLE_write/BLE_write.ino
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
-    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleWrite.cpp
-    Ported to Arduino ESP32 by Evandro Copercini
-*/
-
-#include <BLEDevice.h>
-#include <BLEUtils.h>
-#include <BLEServer.h>
-
-// See the following for generating UUIDs:
-// https://www.uuidgenerator.net/
-
-#define SERVICE_UUID        "4fafc201-1fb5-459e-8fcc-c5c9c331914b"
-#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8"
-
-
-class MyCallbacks: public BLECharacteristicCallbacks {
-    void onWrite(BLECharacteristic *pCharacteristic) {
-      std::string value = pCharacteristic->getValue();
-
-      if (value.length() > 0) {
-        Serial.println("*********");
-        Serial.print("New value: ");
-        for (int i = 0; i < value.length(); i++)
-          Serial.print(value[i]);
-
-        Serial.println();
-        Serial.println("*********");
-      }
-    }
-};
-
-void setup() {
-  Serial.begin(115200);
-
-  Serial.println("1- Download and install an BLE scanner app in your phone");
-  Serial.println("2- Scan for BLE devices in the app");
-  Serial.println("3- Connect to MyESP32");
-  Serial.println("4- Go to CUSTOM CHARACTERISTIC in CUSTOM SERVICE and write something");
-  Serial.println("5- See the magic =)");
-
-  BLEDevice::init("MyESP32");
-  BLEServer *pServer = BLEDevice::createServer();
-
-  BLEService *pService = pServer->createService(SERVICE_UUID);
-
-  BLECharacteristic *pCharacteristic = pService->createCharacteristic(
-                                         CHARACTERISTIC_UUID,
-                                         BLECharacteristic::PROPERTY_READ |
-                                         BLECharacteristic::PROPERTY_WRITE
-                                       );
-
-  pCharacteristic->setCallbacks(new MyCallbacks());
-
-  pCharacteristic->setValue("Hello World");
-  pService->start();
-
-  BLEAdvertising *pAdvertising = pServer->getAdvertising();
-  pAdvertising->start();
-}
-
-void loop() {
-  // put your main code here, to run repeatedly:
-  delay(2000);
-}
\ No newline at end of file
diff --git a/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.ino b/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.ino
new file mode 100644
index 00000000000..fbbf89ad274
--- /dev/null
+++ b/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.ino
@@ -0,0 +1,110 @@
+/*
+   Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleScan.cpp
+   Ported to Arduino ESP32 by Evandro Copercini
+   Changed to a beacon scanner to report iBeacon, EddystoneURL and EddystoneTLM beacons by beegee-tokyo
+   Upgraded Eddystone part by Tomas Pilny on Feb 20, 2023
+*/
+
+#include <Arduino.h>
+
+#include <BLEDevice.h>
+#include <BLEUtils.h>
+#include <BLEScan.h>
+#include <BLEAdvertisedDevice.h>
+#include <BLEEddystoneURL.h>
+#include <BLEEddystoneTLM.h>
+#include <BLEBeacon.h>
+
+int scanTime = 5;  //In seconds
+BLEScan *pBLEScan;
+
+class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks {
+  void onResult(BLEAdvertisedDevice advertisedDevice) {
+    if (advertisedDevice.haveName()) {
+      Serial.print("Device name: ");
+      Serial.println(advertisedDevice.getName().c_str());
+      Serial.println("");
+    }
+
+    if (advertisedDevice.haveServiceUUID()) {
+      BLEUUID devUUID = advertisedDevice.getServiceUUID();
+      Serial.print("Found ServiceUUID: ");
+      Serial.println(devUUID.toString().c_str());
+      Serial.println("");
+    }
+
+    if (advertisedDevice.haveManufacturerData() == true) {
+      String strManufacturerData = advertisedDevice.getManufacturerData();
+
+      uint8_t cManufacturerData[100];
+      memcpy(cManufacturerData, strManufacturerData.c_str(), strManufacturerData.length());
+
+      if (strManufacturerData.length() == 25 && cManufacturerData[0] == 0x4C && cManufacturerData[1] == 0x00) {
+        Serial.println("Found an iBeacon!");
+        BLEBeacon oBeacon = BLEBeacon();
+        oBeacon.setData(strManufacturerData);
+        Serial.printf("iBeacon Frame\n");
+        Serial.printf(
+          "ID: %04X Major: %d Minor: %d UUID: %s Power: %d\n", oBeacon.getManufacturerId(), ENDIAN_CHANGE_U16(oBeacon.getMajor()),
+          ENDIAN_CHANGE_U16(oBeacon.getMinor()), oBeacon.getProximityUUID().toString().c_str(), oBeacon.getSignalPower()
+        );
+      } else {
+        Serial.println("Found another manufacturers beacon!");
+        Serial.printf("strManufacturerData: %d ", strManufacturerData.length());
+        for (int i = 0; i < strManufacturerData.length(); i++) {
+          Serial.printf("[%X]", cManufacturerData[i]);
+        }
+        Serial.printf("\n");
+      }
+    }
+
+    if (advertisedDevice.getFrameType() == BLE_EDDYSTONE_URL_FRAME) {
+      Serial.println("Found an EddystoneURL beacon!");
+      BLEEddystoneURL EddystoneURL = BLEEddystoneURL(&advertisedDevice);
+      Serial.printf("URL bytes: 0x");
+      String url = EddystoneURL.getURL();
+      for (auto byte : url) {
+        Serial.printf("%02X", byte);
+      }
+      Serial.printf("\n");
+      Serial.printf("Decoded URL: %s\n", EddystoneURL.getDecodedURL().c_str());
+      Serial.printf("EddystoneURL.getDecodedURL(): %s\n", EddystoneURL.getDecodedURL().c_str());
+      Serial.printf("TX power %d (Raw 0x%02X)\n", EddystoneURL.getPower(), EddystoneURL.getPower());
+      Serial.println("\n");
+    }
+
+    if (advertisedDevice.getFrameType() == BLE_EDDYSTONE_TLM_FRAME) {
+      Serial.println("Found an EddystoneTLM beacon!");
+      BLEEddystoneTLM EddystoneTLM(&advertisedDevice);
+      Serial.printf("Reported battery voltage: %dmV\n", EddystoneTLM.getVolt());
+      Serial.printf("Reported temperature: %.2f°C (raw data=0x%04X)\n", EddystoneTLM.getTemp(), EddystoneTLM.getRawTemp());
+      Serial.printf("Reported advertise count: %lu\n", EddystoneTLM.getCount());
+      Serial.printf("Reported time since last reboot: %lus\n", EddystoneTLM.getTime());
+      Serial.println("\n");
+      Serial.print(EddystoneTLM.toString().c_str());
+      Serial.println("\n");
+    }
+  }
+};
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Scanning...");
+
+  BLEDevice::init("");
+  pBLEScan = BLEDevice::getScan();  //create new scan
+  pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks());
+  pBLEScan->setActiveScan(true);  //active scan uses more power, but get results faster
+  pBLEScan->setInterval(100);
+  pBLEScan->setWindow(99);  // less or equal setInterval value
+}
+
+void loop() {
+  // put your main code here, to run repeatedly:
+  BLEScanResults *foundDevices = pBLEScan->start(scanTime, false);
+  Serial.print("Devices found: ");
+  Serial.println(foundDevices->getCount());
+  Serial.println("Scan done!");
+  pBLEScan->clearResults();  // delete results fromBLEScan buffer to release memory
+  delay(2000);
+}
diff --git a/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.md b/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.md
new file mode 100644
index 00000000000..34101fe82b7
--- /dev/null
+++ b/libraries/BLE/examples/Beacon_Scanner/Beacon_Scanner.md
@@ -0,0 +1,9 @@
+## BLE Beacon Scanner
+
+Initiates a BLE device scan.
+Checks if the discovered devices are
+- an iBeacon
+- an Eddystone TLM beacon
+- an Eddystone URL beacon
+
+and sends the decoded beacon information over Serial log
diff --git a/libraries/BLE/examples/Beacon_Scanner/ci.json b/libraries/BLE/examples/Beacon_Scanner/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/Beacon_Scanner/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/Client/Client.ino b/libraries/BLE/examples/Client/Client.ino
new file mode 100644
index 00000000000..ce2eb2ff7d1
--- /dev/null
+++ b/libraries/BLE/examples/Client/Client.ino
@@ -0,0 +1,156 @@
+/**
+ * A BLE client example that is rich in capabilities.
+ * There is a lot new capabilities implemented.
+ * author unknown
+ * updated by chegewara
+ */
+
+#include "BLEDevice.h"
+//#include "BLEScan.h"
+
+// The remote service we wish to connect to.
+static BLEUUID serviceUUID("4fafc201-1fb5-459e-8fcc-c5c9c331914b");
+// The characteristic of the remote service we are interested in.
+static BLEUUID charUUID("beb5483e-36e1-4688-b7f5-ea07361b26a8");
+
+static boolean doConnect = false;
+static boolean connected = false;
+static boolean doScan = false;
+static BLERemoteCharacteristic *pRemoteCharacteristic;
+static BLEAdvertisedDevice *myDevice;
+
+static void notifyCallback(BLERemoteCharacteristic *pBLERemoteCharacteristic, uint8_t *pData, size_t length, bool isNotify) {
+  Serial.print("Notify callback for characteristic ");
+  Serial.print(pBLERemoteCharacteristic->getUUID().toString().c_str());
+  Serial.print(" of data length ");
+  Serial.println(length);
+  Serial.print("data: ");
+  Serial.write(pData, length);
+  Serial.println();
+}
+
+class MyClientCallback : public BLEClientCallbacks {
+  void onConnect(BLEClient *pclient) {}
+
+  void onDisconnect(BLEClient *pclient) {
+    connected = false;
+    Serial.println("onDisconnect");
+  }
+};
+
+bool connectToServer() {
+  Serial.print("Forming a connection to ");
+  Serial.println(myDevice->getAddress().toString().c_str());
+
+  BLEClient *pClient = BLEDevice::createClient();
+  Serial.println(" - Created client");
+
+  pClient->setClientCallbacks(new MyClientCallback());
+
+  // Connect to the remove BLE Server.
+  pClient->connect(myDevice);  // if you pass BLEAdvertisedDevice instead of address, it will be recognized type of peer device address (public or private)
+  Serial.println(" - Connected to server");
+  pClient->setMTU(517);  //set client to request maximum MTU from server (default is 23 otherwise)
+
+  // Obtain a reference to the service we are after in the remote BLE server.
+  BLERemoteService *pRemoteService = pClient->getService(serviceUUID);
+  if (pRemoteService == nullptr) {
+    Serial.print("Failed to find our service UUID: ");
+    Serial.println(serviceUUID.toString().c_str());
+    pClient->disconnect();
+    return false;
+  }
+  Serial.println(" - Found our service");
+
+  // Obtain a reference to the characteristic in the service of the remote BLE server.
+  pRemoteCharacteristic = pRemoteService->getCharacteristic(charUUID);
+  if (pRemoteCharacteristic == nullptr) {
+    Serial.print("Failed to find our characteristic UUID: ");
+    Serial.println(charUUID.toString().c_str());
+    pClient->disconnect();
+    return false;
+  }
+  Serial.println(" - Found our characteristic");
+
+  // Read the value of the characteristic.
+  if (pRemoteCharacteristic->canRead()) {
+    String value = pRemoteCharacteristic->readValue();
+    Serial.print("The characteristic value was: ");
+    Serial.println(value.c_str());
+  }
+
+  if (pRemoteCharacteristic->canNotify()) {
+    pRemoteCharacteristic->registerForNotify(notifyCallback);
+  }
+
+  connected = true;
+  return true;
+}
+/**
+ * Scan for BLE servers and find the first one that advertises the service we are looking for.
+ */
+class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks {
+  /**
+   * Called for each advertising BLE server.
+   */
+  void onResult(BLEAdvertisedDevice advertisedDevice) {
+    Serial.print("BLE Advertised Device found: ");
+    Serial.println(advertisedDevice.toString().c_str());
+
+    // We have found a device, let us now see if it contains the service we are looking for.
+    if (advertisedDevice.haveServiceUUID() && advertisedDevice.isAdvertisingService(serviceUUID)) {
+
+      BLEDevice::getScan()->stop();
+      myDevice = new BLEAdvertisedDevice(advertisedDevice);
+      doConnect = true;
+      doScan = true;
+
+    }  // Found our server
+  }  // onResult
+};  // MyAdvertisedDeviceCallbacks
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Starting Arduino BLE Client application...");
+  BLEDevice::init("");
+
+  // Retrieve a Scanner and set the callback we want to use to be informed when we
+  // have detected a new device.  Specify that we want active scanning and start the
+  // scan to run for 5 seconds.
+  BLEScan *pBLEScan = BLEDevice::getScan();
+  pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks());
+  pBLEScan->setInterval(1349);
+  pBLEScan->setWindow(449);
+  pBLEScan->setActiveScan(true);
+  pBLEScan->start(5, false);
+}  // End of setup.
+
+// This is the Arduino main loop function.
+void loop() {
+
+  // If the flag "doConnect" is true then we have scanned for and found the desired
+  // BLE Server with which we wish to connect.  Now we connect to it.  Once we are
+  // connected we set the connected flag to be true.
+  if (doConnect == true) {
+    if (connectToServer()) {
+      Serial.println("We are now connected to the BLE Server.");
+    } else {
+      Serial.println("We have failed to connect to the server; there is nothing more we will do.");
+    }
+    doConnect = false;
+  }
+
+  // If we are connected to a peer BLE Server, update the characteristic each time we are reached
+  // with the current time since boot.
+  if (connected) {
+    String newValue = "Time since boot: " + String(millis() / 1000);
+    Serial.println("Setting new characteristic value to \"" + newValue + "\"");
+
+    // Set the characteristic's value to be the array of bytes that is actually a string.
+    pRemoteCharacteristic->writeValue(newValue.c_str(), newValue.length());
+  } else if (doScan) {
+    BLEDevice::getScan()->start(0);  // this is just example to start scan after disconnect, most likely there is better way to do it in arduino
+  }
+
+  delay(1000);  // Delay a second between loops.
+}  // End of loop
diff --git a/libraries/BLE/examples/Client/ci.json b/libraries/BLE/examples/Client/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/Client/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.ino b/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.ino
new file mode 100644
index 00000000000..d66ceb53b69
--- /dev/null
+++ b/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.ino
@@ -0,0 +1,92 @@
+/*
+   EddystoneTLM beacon by BeeGee based on https://github.com/pcbreflux/espressif/blob/master/esp32/arduino/sketchbook/ESP32_Eddystone_TLM_deepsleep/ESP32_Eddystone_TLM_deepsleep.ino
+   EddystoneTLM frame specification https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md
+*/
+
+/*
+   Create a BLE server that will send periodic Eddystone URL frames.
+   The design of creating the BLE server is:
+   1. Create a BLE Server
+   2. Create advertising data
+   3. Start advertising.
+   4. wait
+   5. Stop advertising.
+   6. deep sleep
+
+   To read data advertised by this beacon use second ESP with example sketch BLE_Beacon_Scanner
+*/
+#include "sys/time.h"
+
+#include <Arduino.h>
+
+#include "BLEDevice.h"
+#include "BLEUtils.h"
+#include "BLEBeacon.h"
+#include "BLEAdvertising.h"
+#include "BLEEddystoneTLM.h"
+
+#include "esp_sleep.h"
+
+#define GPIO_DEEP_SLEEP_DURATION 10  // sleep x seconds and then wake up
+#define BEACON_POWER             ESP_PWR_LVL_N12
+RTC_DATA_ATTR static time_t last;         // remember last boot in RTC Memory
+RTC_DATA_ATTR static uint32_t bootcount;  // remember number of boots in RTC Memory
+
+// See the following for generating UUIDs:
+// https://www.uuidgenerator.net/
+BLEAdvertising *pAdvertising;
+struct timeval nowTimeStruct;
+
+time_t lastTenth;
+
+#define BEACON_UUID "8ec76ea3-6668-48da-9866-75be8bc86f4d"  // UUID 1 128-Bit (may use linux tool uuidgen or random numbers via https://www.uuidgenerator.net/)
+
+// Check
+// https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md
+// and http://www.hugi.scene.org/online/coding/hugi%2015%20-%20cmtadfix.htm
+// for the temperature value. It is a 8.8 fixed-point notation
+void setBeacon() {
+  BLEEddystoneTLM EddystoneTLM;
+  EddystoneTLM.setVolt((uint16_t)random(2800, 3700));  // 3300mV = 3.3V
+  EddystoneTLM.setTemp(random(-3000, 3000) / 100.0f);  // 3000 = 30.00 ˚C
+  Serial.printf("Random Battery voltage is %d mV = 0x%04X\n", EddystoneTLM.getVolt(), EddystoneTLM.getVolt());
+  Serial.printf("Random temperature is %.2f°C\n", EddystoneTLM.getTemp());
+  Serial.printf("Converted to 8.8 format: 0x%04X\n", EddystoneTLM.getRawTemp());
+
+  BLEAdvertisementData oAdvertisementData = BLEAdvertisementData();
+  BLEAdvertisementData oScanResponseData = BLEAdvertisementData();
+  oScanResponseData.setServiceData(BLEUUID((uint16_t)0xFEAA), String(EddystoneTLM.getData().c_str(), EddystoneTLM.getData().length()));
+
+  oAdvertisementData.setName("ESP32 TLM Beacon");
+  pAdvertising->setAdvertisementData(oAdvertisementData);
+  pAdvertising->setScanResponseData(oScanResponseData);
+}
+
+void setup() {
+  Serial.begin(115200);
+  gettimeofday(&nowTimeStruct, NULL);
+
+  Serial.printf("Starting ESP32. Bootcount = %lu\n", bootcount++);
+  Serial.printf("Deep sleep (%llds since last reset, %llds since last boot)\n", nowTimeStruct.tv_sec, nowTimeStruct.tv_sec - last);
+
+  last = nowTimeStruct.tv_sec;
+  lastTenth = nowTimeStruct.tv_sec * 10;  // Time since last reset as 0.1 second resolution counter
+
+  // Create the BLE Device
+  BLEDevice::init("TLMBeacon");
+
+  BLEDevice::setPower(BEACON_POWER);
+
+  pAdvertising = BLEDevice::getAdvertising();
+
+  setBeacon();
+  // Start advertising
+  pAdvertising->start();
+  Serial.println("Advertising started for 10s ...");
+  delay(10000);
+  pAdvertising->stop();
+  Serial.printf("Enter deep sleep for 10s\n");
+  esp_deep_sleep(1000000LL * GPIO_DEEP_SLEEP_DURATION);
+}
+
+void loop() {}
diff --git a/libraries/BLE/examples/BLE_EddystoneTLM_Beacon/BLE_EddystoneTLM_Beacon.md b/libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.md
similarity index 100%
rename from libraries/BLE/examples/BLE_EddystoneTLM_Beacon/BLE_EddystoneTLM_Beacon.md
rename to libraries/BLE/examples/EddystoneTLM_Beacon/EddystoneTLM_Beacon.md
diff --git a/libraries/BLE/examples/EddystoneTLM_Beacon/ci.json b/libraries/BLE/examples/EddystoneTLM_Beacon/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/EddystoneTLM_Beacon/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.ino b/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.ino
new file mode 100644
index 00000000000..d520c844b30
--- /dev/null
+++ b/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.ino
@@ -0,0 +1,105 @@
+/*
+   EddystoneURL beacon by BeeGee
+   EddystoneURL frame specification https://github.com/google/eddystone/blob/master/eddystone-url/README.md
+
+   Upgraded on: Feb 20, 2023
+       By: Tomas Pilny
+*/
+
+/*
+   Create a BLE server that will send periodic Eddystone URL frames.
+   The design of creating the BLE server is:
+   1. Create a BLE Server
+   2. Create advertising data
+   3. Start advertising.
+   4. wait
+   5. Stop advertising.
+   6. deep sleep
+
+*/
+#include "sys/time.h"
+
+#include <Arduino.h>
+
+#include "BLEDevice.h"
+#include "BLEUtils.h"
+#include "BLEBeacon.h"
+#include "BLEAdvertising.h"
+#include "BLEEddystoneURL.h"
+#include "esp_sleep.h"
+
+char unprintable[] = {0x01, 0xFF, 0xDE, 0xAD};
+String URL[] = {
+  "http://www.espressif.com/",  // prefix 0x00, suffix 0x00
+  "https://www.texas.gov",      // prefix 0x01, suffix 0x0D
+  "http://en.mapy.cz",          // prefix 0x02, no valid suffix
+  "https://arduino.cc",         // prefix 0x03, no valid suffix
+  "google.com",                 // URL without specified prefix - the function will assume default prefix "http://www." = 0x00
+  "diginfo.tv",                 // URL without specified prefix - the function will assume default prefix "http://www." = 0x00
+  //  "http://www.URLsAbove17BytesAreNotAllowed.com", // Too long URL - setSmartURL() will return 0 = ERR
+  //  "",  // Empty string - setSmartURL() will return 0 = ERR
+  //  String(unprintable), // Unprintable characters / corrupted String - setSmartURL() will return 0 = ERR
+};
+
+#define GPIO_DEEP_SLEEP_DURATION 10  // sleep x seconds and then wake up
+#define BEACON_POWER             ESP_PWR_LVL_N12
+RTC_DATA_ATTR static time_t last;         // remember last boot in RTC Memory
+RTC_DATA_ATTR static uint32_t bootcount;  // remember number of boots in RTC Memory
+
+// See the following for generating UUIDs:
+// https://www.uuidgenerator.net/
+BLEAdvertising *pAdvertising;
+struct timeval now;
+
+int setBeacon() {
+  BLEAdvertisementData oAdvertisementData = BLEAdvertisementData();
+  BLEAdvertisementData oScanResponseData = BLEAdvertisementData();
+
+  BLEEddystoneURL EddystoneURL;
+  EddystoneURL.setPower(BEACON_POWER);  // This is only information about the power. The actual power is set by `BLEDevice::setPower(BEACON_POWER)`
+  if (EddystoneURL.setSmartURL(URL[bootcount % (sizeof(URL) / sizeof(URL[0]))])) {
+    String frame = EddystoneURL.getFrame();
+    String data(EddystoneURL.getFrame().c_str(), frame.length());
+    oAdvertisementData.addData(data);
+    oScanResponseData.setName("ESP32 URLBeacon");
+    pAdvertising->setAdvertisementData(oAdvertisementData);
+    pAdvertising->setScanResponseData(oScanResponseData);
+    Serial.printf("Advertise URL \"%s\"\n", URL[bootcount % (sizeof(URL) / sizeof(URL[0]))].c_str());
+    return 1;  // OK
+  } else {
+    Serial.println("Smart URL set ERR");
+    return 0;  // ERR
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  gettimeofday(&now, NULL);
+
+  Serial.printf("Start ESP32 %lu\n", bootcount++);
+  Serial.printf("Deep sleep (%llds since last reset, %llds since last boot)\n", now.tv_sec, now.tv_sec - last);
+
+  last = now.tv_sec;
+
+  // Create the BLE Device
+  BLEDevice::init("URLBeacon");
+  BLEDevice::setPower(BEACON_POWER);
+
+  // Create the BLE Server
+  // BLEServer *pServer = BLEDevice::createServer(); // <-- no longer required to instantiate BLEServer, less flash and ram usage
+
+  pAdvertising = BLEDevice::getAdvertising();
+
+  if (setBeacon()) {
+    // Start advertising
+    pAdvertising->start();
+    Serial.println("Advertising started...");
+    delay(10000);
+    pAdvertising->stop();
+  }
+  Serial.println("Enter deep sleep");
+  bootcount++;
+  esp_deep_sleep(1000000LL * GPIO_DEEP_SLEEP_DURATION);
+}
+
+void loop() {}
diff --git a/libraries/BLE/examples/BLE_EddystoneURL_Beacon/BLE_EddystoneURL_Beacon.md b/libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.md
similarity index 100%
rename from libraries/BLE/examples/BLE_EddystoneURL_Beacon/BLE_EddystoneURL_Beacon.md
rename to libraries/BLE/examples/EddystoneURL_Beacon/EddystoneURL_Beacon.md
diff --git a/libraries/BLE/examples/EddystoneURL_Beacon/ci.json b/libraries/BLE/examples/EddystoneURL_Beacon/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/EddystoneURL_Beacon/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/Notify/Notify.ino b/libraries/BLE/examples/Notify/Notify.ino
new file mode 100644
index 00000000000..6b552b01d11
--- /dev/null
+++ b/libraries/BLE/examples/Notify/Notify.ino
@@ -0,0 +1,111 @@
+/*
+    Video: https://www.youtube.com/watch?v=oCMOYS71NIU
+    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleNotify.cpp
+    Ported to Arduino ESP32 by Evandro Copercini
+    updated by chegewara
+
+   Create a BLE server that, once we receive a connection, will send periodic notifications.
+   The service advertises itself as: 4fafc201-1fb5-459e-8fcc-c5c9c331914b
+   And has a characteristic of: beb5483e-36e1-4688-b7f5-ea07361b26a8
+
+   The design of creating the BLE server is:
+   1. Create a BLE Server
+   2. Create a BLE Service
+   3. Create a BLE Characteristic on the Service
+   4. Create a BLE Descriptor on the characteristic
+   5. Start the service.
+   6. Start advertising.
+
+   A connect handler associated with the server starts a background task that performs notification
+   every couple of seconds.
+*/
+#include <BLEDevice.h>
+#include <BLEServer.h>
+#include <BLEUtils.h>
+#include <BLE2902.h>
+#include <BLE2901.h>
+
+BLEServer *pServer = NULL;
+BLECharacteristic *pCharacteristic = NULL;
+BLE2901 *descriptor_2901 = NULL;
+
+bool deviceConnected = false;
+bool oldDeviceConnected = false;
+uint32_t value = 0;
+
+// See the following for generating UUIDs:
+// https://www.uuidgenerator.net/
+
+#define SERVICE_UUID        "4fafc201-1fb5-459e-8fcc-c5c9c331914b"
+#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8"
+
+class MyServerCallbacks : public BLEServerCallbacks {
+  void onConnect(BLEServer *pServer) {
+    deviceConnected = true;
+  };
+
+  void onDisconnect(BLEServer *pServer) {
+    deviceConnected = false;
+  }
+};
+
+void setup() {
+  Serial.begin(115200);
+
+  // Create the BLE Device
+  BLEDevice::init("ESP32");
+
+  // Create the BLE Server
+  pServer = BLEDevice::createServer();
+  pServer->setCallbacks(new MyServerCallbacks());
+
+  // Create the BLE Service
+  BLEService *pService = pServer->createService(SERVICE_UUID);
+
+  // Create a BLE Characteristic
+  pCharacteristic = pService->createCharacteristic(
+    CHARACTERISTIC_UUID,
+    BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_NOTIFY | BLECharacteristic::PROPERTY_INDICATE
+  );
+
+  // Creates BLE Descriptor 0x2902: Client Characteristic Configuration Descriptor (CCCD)
+  pCharacteristic->addDescriptor(new BLE2902());
+  // Adds also the Characteristic User Description - 0x2901 descriptor
+  descriptor_2901 = new BLE2901();
+  descriptor_2901->setDescription("My own description for this characteristic.");
+  descriptor_2901->setAccessPermissions(ESP_GATT_PERM_READ);  // enforce read only - default is Read|Write
+  pCharacteristic->addDescriptor(descriptor_2901);
+
+  // Start the service
+  pService->start();
+
+  // Start advertising
+  BLEAdvertising *pAdvertising = BLEDevice::getAdvertising();
+  pAdvertising->addServiceUUID(SERVICE_UUID);
+  pAdvertising->setScanResponse(false);
+  pAdvertising->setMinPreferred(0x0);  // set value to 0x00 to not advertise this parameter
+  BLEDevice::startAdvertising();
+  Serial.println("Waiting a client connection to notify...");
+}
+
+void loop() {
+  // notify changed value
+  if (deviceConnected) {
+    pCharacteristic->setValue((uint8_t *)&value, 4);
+    pCharacteristic->notify();
+    value++;
+    delay(500);
+  }
+  // disconnecting
+  if (!deviceConnected && oldDeviceConnected) {
+    delay(500);                   // give the bluetooth stack the chance to get things ready
+    pServer->startAdvertising();  // restart advertising
+    Serial.println("start advertising");
+    oldDeviceConnected = deviceConnected;
+  }
+  // connecting
+  if (deviceConnected && !oldDeviceConnected) {
+    // do stuff here on connecting
+    oldDeviceConnected = deviceConnected;
+  }
+}
diff --git a/libraries/BLE/examples/Notify/ci.json b/libraries/BLE/examples/Notify/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/Notify/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/Scan/Scan.ino b/libraries/BLE/examples/Scan/Scan.ino
new file mode 100644
index 00000000000..6b8a1fa6f48
--- /dev/null
+++ b/libraries/BLE/examples/Scan/Scan.ino
@@ -0,0 +1,40 @@
+/*
+   Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleScan.cpp
+   Ported to Arduino ESP32 by Evandro Copercini
+*/
+
+#include <BLEDevice.h>
+#include <BLEUtils.h>
+#include <BLEScan.h>
+#include <BLEAdvertisedDevice.h>
+
+int scanTime = 5;  //In seconds
+BLEScan *pBLEScan;
+
+class MyAdvertisedDeviceCallbacks : public BLEAdvertisedDeviceCallbacks {
+  void onResult(BLEAdvertisedDevice advertisedDevice) {
+    Serial.printf("Advertised Device: %s \n", advertisedDevice.toString().c_str());
+  }
+};
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Scanning...");
+
+  BLEDevice::init("");
+  pBLEScan = BLEDevice::getScan();  //create new scan
+  pBLEScan->setAdvertisedDeviceCallbacks(new MyAdvertisedDeviceCallbacks());
+  pBLEScan->setActiveScan(true);  //active scan uses more power, but get results faster
+  pBLEScan->setInterval(100);
+  pBLEScan->setWindow(99);  // less or equal setInterval value
+}
+
+void loop() {
+  // put your main code here, to run repeatedly:
+  BLEScanResults *foundDevices = pBLEScan->start(scanTime, false);
+  Serial.print("Devices found: ");
+  Serial.println(foundDevices->getCount());
+  Serial.println("Scan done!");
+  pBLEScan->clearResults();  // delete results fromBLEScan buffer to release memory
+  delay(2000);
+}
diff --git a/libraries/BLE/examples/Scan/ci.json b/libraries/BLE/examples/Scan/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/Scan/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/Server/Server.ino b/libraries/BLE/examples/Server/Server.ino
new file mode 100644
index 00000000000..e86ed723267
--- /dev/null
+++ b/libraries/BLE/examples/Server/Server.ino
@@ -0,0 +1,42 @@
+/*
+    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleServer.cpp
+    Ported to Arduino ESP32 by Evandro Copercini
+    updates by chegewara
+*/
+
+#include <BLEDevice.h>
+#include <BLEUtils.h>
+#include <BLEServer.h>
+
+// See the following for generating UUIDs:
+// https://www.uuidgenerator.net/
+
+#define SERVICE_UUID        "4fafc201-1fb5-459e-8fcc-c5c9c331914b"
+#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8"
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Starting BLE work!");
+
+  BLEDevice::init("Long name works now");
+  BLEServer *pServer = BLEDevice::createServer();
+  BLEService *pService = pServer->createService(SERVICE_UUID);
+  BLECharacteristic *pCharacteristic =
+    pService->createCharacteristic(CHARACTERISTIC_UUID, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE);
+
+  pCharacteristic->setValue("Hello World says Neil");
+  pService->start();
+  // BLEAdvertising *pAdvertising = pServer->getAdvertising();  // this still is working for backward compatibility
+  BLEAdvertising *pAdvertising = BLEDevice::getAdvertising();
+  pAdvertising->addServiceUUID(SERVICE_UUID);
+  pAdvertising->setScanResponse(true);
+  pAdvertising->setMinPreferred(0x06);  // functions that help with iPhone connections issue
+  pAdvertising->setMinPreferred(0x12);
+  BLEDevice::startAdvertising();
+  Serial.println("Characteristic defined! Now you can read it in your phone!");
+}
+
+void loop() {
+  // put your main code here, to run repeatedly:
+  delay(2000);
+}
diff --git a/libraries/BLE/examples/Server/ci.json b/libraries/BLE/examples/Server/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/Server/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/Server_multiconnect/Server_multiconnect.ino b/libraries/BLE/examples/Server_multiconnect/Server_multiconnect.ino
new file mode 100644
index 00000000000..afd15e9ae4f
--- /dev/null
+++ b/libraries/BLE/examples/Server_multiconnect/Server_multiconnect.ino
@@ -0,0 +1,105 @@
+/*
+    Video: https://www.youtube.com/watch?v=oCMOYS71NIU
+    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleNotify.cpp
+    Ported to Arduino ESP32 by Evandro Copercini
+    updated by chegewara
+
+   Create a BLE server that, once we receive a connection, will send periodic notifications.
+   The service advertises itself as: 4fafc201-1fb5-459e-8fcc-c5c9c331914b
+   And has a characteristic of: beb5483e-36e1-4688-b7f5-ea07361b26a8
+
+   The design of creating the BLE server is:
+   1. Create a BLE Server
+   2. Create a BLE Service
+   3. Create a BLE Characteristic on the Service
+   4. Create a BLE Descriptor on the characteristic
+   5. Start the service.
+   6. Start advertising.
+
+   A connect handler associated with the server starts a background task that performs notification
+   every couple of seconds.
+*/
+#include <BLEDevice.h>
+#include <BLEServer.h>
+#include <BLEUtils.h>
+#include <BLE2902.h>
+
+BLEServer *pServer = NULL;
+BLECharacteristic *pCharacteristic = NULL;
+bool deviceConnected = false;
+bool oldDeviceConnected = false;
+uint32_t value = 0;
+
+// See the following for generating UUIDs:
+// https://www.uuidgenerator.net/
+
+#define SERVICE_UUID        "4fafc201-1fb5-459e-8fcc-c5c9c331914b"
+#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8"
+
+class MyServerCallbacks : public BLEServerCallbacks {
+  void onConnect(BLEServer *pServer) {
+    deviceConnected = true;
+    BLEDevice::startAdvertising();
+  };
+
+  void onDisconnect(BLEServer *pServer) {
+    deviceConnected = false;
+  }
+};
+
+void setup() {
+  Serial.begin(115200);
+
+  // Create the BLE Device
+  BLEDevice::init("ESP32");
+
+  // Create the BLE Server
+  pServer = BLEDevice::createServer();
+  pServer->setCallbacks(new MyServerCallbacks());
+
+  // Create the BLE Service
+  BLEService *pService = pServer->createService(SERVICE_UUID);
+
+  // Create a BLE Characteristic
+  pCharacteristic = pService->createCharacteristic(
+    CHARACTERISTIC_UUID,
+    BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_NOTIFY | BLECharacteristic::PROPERTY_INDICATE
+  );
+
+  // https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.client_characteristic_configuration.xml
+  // Create a BLE Descriptor
+  pCharacteristic->addDescriptor(new BLE2902());
+
+  // Start the service
+  pService->start();
+
+  // Start advertising
+  BLEAdvertising *pAdvertising = BLEDevice::getAdvertising();
+  pAdvertising->addServiceUUID(SERVICE_UUID);
+  pAdvertising->setScanResponse(false);
+  pAdvertising->setMinPreferred(0x0);  // set value to 0x00 to not advertise this parameter
+  BLEDevice::startAdvertising();
+  Serial.println("Waiting a client connection to notify...");
+}
+
+void loop() {
+  // notify changed value
+  if (deviceConnected) {
+    pCharacteristic->setValue((uint8_t *)&value, 4);
+    pCharacteristic->notify();
+    value++;
+    delay(10);  // bluetooth stack will go into congestion, if too many packets are sent, in 6 hours test i was able to go as low as 3ms
+  }
+  // disconnecting
+  if (!deviceConnected && oldDeviceConnected) {
+    delay(500);                   // give the bluetooth stack the chance to get things ready
+    pServer->startAdvertising();  // restart advertising
+    Serial.println("start advertising");
+    oldDeviceConnected = deviceConnected;
+  }
+  // connecting
+  if (deviceConnected && !oldDeviceConnected) {
+    // do stuff here on connecting
+    oldDeviceConnected = deviceConnected;
+  }
+}
diff --git a/libraries/BLE/examples/Server_multiconnect/ci.json b/libraries/BLE/examples/Server_multiconnect/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/Server_multiconnect/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/UART/UART.ino b/libraries/BLE/examples/UART/UART.ino
new file mode 100644
index 00000000000..71cc850db66
--- /dev/null
+++ b/libraries/BLE/examples/UART/UART.ino
@@ -0,0 +1,118 @@
+/*
+    Video: https://www.youtube.com/watch?v=oCMOYS71NIU
+    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleNotify.cpp
+    Ported to Arduino ESP32 by Evandro Copercini
+
+   Create a BLE server that, once we receive a connection, will send periodic notifications.
+   The service advertises itself as: 6E400001-B5A3-F393-E0A9-E50E24DCCA9E
+   Has a characteristic of: 6E400002-B5A3-F393-E0A9-E50E24DCCA9E - used for receiving data with "WRITE"
+   Has a characteristic of: 6E400003-B5A3-F393-E0A9-E50E24DCCA9E - used to send data with  "NOTIFY"
+
+   The design of creating the BLE server is:
+   1. Create a BLE Server
+   2. Create a BLE Service
+   3. Create a BLE Characteristic on the Service
+   4. Create a BLE Descriptor on the characteristic
+   5. Start the service.
+   6. Start advertising.
+
+   In this example rxValue is the data received (only accessible inside that function).
+   And txValue is the data to be sent, in this example just a byte incremented every second.
+*/
+#include <BLEDevice.h>
+#include <BLEServer.h>
+#include <BLEUtils.h>
+#include <BLE2902.h>
+
+BLEServer *pServer = NULL;
+BLECharacteristic *pTxCharacteristic;
+bool deviceConnected = false;
+bool oldDeviceConnected = false;
+uint8_t txValue = 0;
+
+// See the following for generating UUIDs:
+// https://www.uuidgenerator.net/
+
+#define SERVICE_UUID           "6E400001-B5A3-F393-E0A9-E50E24DCCA9E"  // UART service UUID
+#define CHARACTERISTIC_UUID_RX "6E400002-B5A3-F393-E0A9-E50E24DCCA9E"
+#define CHARACTERISTIC_UUID_TX "6E400003-B5A3-F393-E0A9-E50E24DCCA9E"
+
+class MyServerCallbacks : public BLEServerCallbacks {
+  void onConnect(BLEServer *pServer) {
+    deviceConnected = true;
+  };
+
+  void onDisconnect(BLEServer *pServer) {
+    deviceConnected = false;
+  }
+};
+
+class MyCallbacks : public BLECharacteristicCallbacks {
+  void onWrite(BLECharacteristic *pCharacteristic) {
+    String rxValue = pCharacteristic->getValue();
+
+    if (rxValue.length() > 0) {
+      Serial.println("*********");
+      Serial.print("Received Value: ");
+      for (int i = 0; i < rxValue.length(); i++) {
+        Serial.print(rxValue[i]);
+      }
+
+      Serial.println();
+      Serial.println("*********");
+    }
+  }
+};
+
+void setup() {
+  Serial.begin(115200);
+
+  // Create the BLE Device
+  BLEDevice::init("UART Service");
+
+  // Create the BLE Server
+  pServer = BLEDevice::createServer();
+  pServer->setCallbacks(new MyServerCallbacks());
+
+  // Create the BLE Service
+  BLEService *pService = pServer->createService(SERVICE_UUID);
+
+  // Create a BLE Characteristic
+  pTxCharacteristic = pService->createCharacteristic(CHARACTERISTIC_UUID_TX, BLECharacteristic::PROPERTY_NOTIFY);
+
+  pTxCharacteristic->addDescriptor(new BLE2902());
+
+  BLECharacteristic *pRxCharacteristic = pService->createCharacteristic(CHARACTERISTIC_UUID_RX, BLECharacteristic::PROPERTY_WRITE);
+
+  pRxCharacteristic->setCallbacks(new MyCallbacks());
+
+  // Start the service
+  pService->start();
+
+  // Start advertising
+  pServer->getAdvertising()->start();
+  Serial.println("Waiting a client connection to notify...");
+}
+
+void loop() {
+
+  if (deviceConnected) {
+    pTxCharacteristic->setValue(&txValue, 1);
+    pTxCharacteristic->notify();
+    txValue++;
+    delay(10);  // bluetooth stack will go into congestion, if too many packets are sent
+  }
+
+  // disconnecting
+  if (!deviceConnected && oldDeviceConnected) {
+    delay(500);                   // give the bluetooth stack the chance to get things ready
+    pServer->startAdvertising();  // restart advertising
+    Serial.println("start advertising");
+    oldDeviceConnected = deviceConnected;
+  }
+  // connecting
+  if (deviceConnected && !oldDeviceConnected) {
+    // do stuff here on connecting
+    oldDeviceConnected = deviceConnected;
+  }
+}
diff --git a/libraries/BLE/examples/UART/ci.json b/libraries/BLE/examples/UART/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/UART/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/Write/Write.ino b/libraries/BLE/examples/Write/Write.ino
new file mode 100644
index 00000000000..3cc693618ab
--- /dev/null
+++ b/libraries/BLE/examples/Write/Write.ino
@@ -0,0 +1,62 @@
+/*
+    Based on Neil Kolban example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleWrite.cpp
+    Ported to Arduino ESP32 by Evandro Copercini
+*/
+
+#include <BLEDevice.h>
+#include <BLEUtils.h>
+#include <BLEServer.h>
+
+// See the following for generating UUIDs:
+// https://www.uuidgenerator.net/
+
+#define SERVICE_UUID        "4fafc201-1fb5-459e-8fcc-c5c9c331914b"
+#define CHARACTERISTIC_UUID "beb5483e-36e1-4688-b7f5-ea07361b26a8"
+
+class MyCallbacks : public BLECharacteristicCallbacks {
+  void onWrite(BLECharacteristic *pCharacteristic) {
+    String value = pCharacteristic->getValue();
+
+    if (value.length() > 0) {
+      Serial.println("*********");
+      Serial.print("New value: ");
+      for (int i = 0; i < value.length(); i++) {
+        Serial.print(value[i]);
+      }
+
+      Serial.println();
+      Serial.println("*********");
+    }
+  }
+};
+
+void setup() {
+  Serial.begin(115200);
+
+  Serial.println("1- Download and install an BLE scanner app in your phone");
+  Serial.println("2- Scan for BLE devices in the app");
+  Serial.println("3- Connect to MyESP32");
+  Serial.println("4- Go to CUSTOM CHARACTERISTIC in CUSTOM SERVICE and write something");
+  Serial.println("5- See the magic =)");
+
+  BLEDevice::init("MyESP32");
+  BLEServer *pServer = BLEDevice::createServer();
+
+  BLEService *pService = pServer->createService(SERVICE_UUID);
+
+  BLECharacteristic *pCharacteristic =
+    pService->createCharacteristic(CHARACTERISTIC_UUID, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE);
+
+  pCharacteristic->setCallbacks(new MyCallbacks());
+
+  pCharacteristic->setValue("Hello World");
+  pService->start();
+
+  BLEAdvertising *pAdvertising = pServer->getAdvertising();
+  pAdvertising->start();
+}
+
+void loop() {
+  // put your main code here, to run repeatedly:
+  delay(2000);
+}
diff --git a/libraries/BLE/examples/Write/ci.json b/libraries/BLE/examples/Write/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/Write/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/iBeacon/ci.json b/libraries/BLE/examples/iBeacon/ci.json
new file mode 100644
index 00000000000..abe13a7ebbb
--- /dev/null
+++ b/libraries/BLE/examples/iBeacon/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_BLE_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/BLE/examples/iBeacon/iBeacon.ino b/libraries/BLE/examples/iBeacon/iBeacon.ino
new file mode 100644
index 00000000000..d5db613dcb0
--- /dev/null
+++ b/libraries/BLE/examples/iBeacon/iBeacon.ino
@@ -0,0 +1,133 @@
+/*
+   Based on 31337Ghost's reference code from https://github.com/nkolban/esp32-snippets/issues/385#issuecomment-362535434
+   which is based on pcbreflux's Arduino ESP32 port of Neil Kolban's example for IDF: https://github.com/nkolban/esp32-snippets/blob/master/cpp_utils/tests/BLE%20Tests/SampleScan.cpp
+*/
+
+/*
+   Create a BLE server that will send periodic iBeacon frames.
+   The design of creating the BLE server is:
+   1. Create a BLE Server
+   2. Create advertising data
+   3. Start advertising.
+   4. wait
+   5. Stop advertising.
+*/
+#include <BLEDevice.h>
+#include <BLEServer.h>
+#include <BLEUtils.h>
+#include <BLE2902.h>
+#include <BLEBeacon.h>
+
+#define DEVICE_NAME         "ESP32"
+#define SERVICE_UUID        "7A0247E7-8E88-409B-A959-AB5092DDB03E"
+#define BEACON_UUID         "2D7A9F0C-E0E8-4CC9-A71B-A21DB2D034A1"
+#define BEACON_UUID_REV     "A134D0B2-1DA2-1BA7-C94C-E8E00C9F7A2D"
+#define CHARACTERISTIC_UUID "82258BAA-DF72-47E8-99BC-B73D7ECD08A5"
+
+BLEServer *pServer;
+BLECharacteristic *pCharacteristic;
+bool deviceConnected = false;
+uint8_t value = 0;
+
+class MyServerCallbacks : public BLEServerCallbacks {
+  void onConnect(BLEServer *pServer) {
+    deviceConnected = true;
+    Serial.println("deviceConnected = true");
+  };
+
+  void onDisconnect(BLEServer *pServer) {
+    deviceConnected = false;
+    Serial.println("deviceConnected = false");
+
+    // Restart advertising to be visible and connectable again
+    BLEAdvertising *pAdvertising;
+    pAdvertising = pServer->getAdvertising();
+    pAdvertising->start();
+    Serial.println("iBeacon advertising restarted");
+  }
+};
+
+class MyCallbacks : public BLECharacteristicCallbacks {
+  void onWrite(BLECharacteristic *pCharacteristic) {
+    String rxValue = pCharacteristic->getValue();
+
+    if (rxValue.length() > 0) {
+      Serial.println("*********");
+      Serial.print("Received Value: ");
+      for (int i = 0; i < rxValue.length(); i++) {
+        Serial.print(rxValue[i]);
+      }
+      Serial.println();
+      Serial.println("*********");
+    }
+  }
+};
+
+void init_service() {
+  BLEAdvertising *pAdvertising;
+  pAdvertising = pServer->getAdvertising();
+  pAdvertising->stop();
+
+  // Create the BLE Service
+  BLEService *pService = pServer->createService(BLEUUID(SERVICE_UUID));
+
+  // Create a BLE Characteristic
+  pCharacteristic = pService->createCharacteristic(
+    CHARACTERISTIC_UUID, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_NOTIFY
+  );
+  pCharacteristic->setCallbacks(new MyCallbacks());
+  pCharacteristic->addDescriptor(new BLE2902());
+
+  pAdvertising->addServiceUUID(BLEUUID(SERVICE_UUID));
+
+  // Start the service
+  pService->start();
+
+  pAdvertising->start();
+}
+
+void init_beacon() {
+  BLEAdvertising *pAdvertising;
+  pAdvertising = pServer->getAdvertising();
+  pAdvertising->stop();
+  // iBeacon
+  BLEBeacon myBeacon;
+  myBeacon.setManufacturerId(0x4c00);
+  myBeacon.setMajor(5);
+  myBeacon.setMinor(88);
+  myBeacon.setSignalPower(0xc5);
+  myBeacon.setProximityUUID(BLEUUID(BEACON_UUID_REV));
+
+  BLEAdvertisementData advertisementData;
+  advertisementData.setFlags(0x1A);
+  advertisementData.setManufacturerData(myBeacon.getData());
+  pAdvertising->setAdvertisementData(advertisementData);
+
+  pAdvertising->start();
+}
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println();
+  Serial.println("Initializing...");
+  Serial.flush();
+
+  BLEDevice::init(DEVICE_NAME);
+  pServer = BLEDevice::createServer();
+  pServer->setCallbacks(new MyServerCallbacks());
+
+  init_service();
+  init_beacon();
+
+  Serial.println("iBeacon + service defined and advertising!");
+}
+
+void loop() {
+  if (deviceConnected) {
+    Serial.printf("*** NOTIFY: %d ***\n", value);
+    pCharacteristic->setValue(&value, 1);
+    pCharacteristic->notify();
+    value++;
+  }
+  delay(2000);
+}
diff --git a/libraries/BLE/library.properties b/libraries/BLE/library.properties
index 8c2a019fe57..7ef636223ec 100644
--- a/libraries/BLE/library.properties
+++ b/libraries/BLE/library.properties
@@ -1,10 +1,10 @@
-name=ESP32 BLE Arduino
-version=1.0.1
+name=BLE
+version=3.2.0
 author=Neil Kolban <kolban1@kolban.com>
 maintainer=Dariusz Krempa <esp32@esp32.eu.org>
 sentence=BLE functions for ESP32
-paragraph=This library provides an implementation Bluetooth Low Energy support for the ESP32 using the Arduino platform. 
+paragraph=This library provides an implementation Bluetooth Low Energy support for the ESP32 using the Arduino platform.
 category=Communication
-url=https://github.com/nkolban/ESP32_BLE_Arduino
+url=https://github.com/espressif/arduino-esp32/tree/master/libraries/BLE
 architectures=esp32
 includes=BLEDevice.h, BLEUtils.h, BLEScan.h, BLEAdvertisedDevice.h
diff --git a/libraries/BLE/src/BLE2901.cpp b/libraries/BLE/src/BLE2901.cpp
new file mode 100644
index 00000000000..e929262b023
--- /dev/null
+++ b/libraries/BLE/src/BLE2901.cpp
@@ -0,0 +1,40 @@
+/*
+   BLE2901.h
+
+     GATT Descriptor 0x2901 Characteristic User Description
+
+     The value of this description is a user-readable string
+     describing the characteristic.
+
+     The Characteristic User Description descriptor
+     provides a textual user description for a characteristic
+     value.
+     If the Writable Auxiliary bit of the Characteristics
+     Properties is set then this descriptor is written. Only one
+     User Description descriptor exists in a characteristic
+     definition.
+*/
+
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
+#include "sdkconfig.h"
+#if defined(CONFIG_BLUEDROID_ENABLED)
+
+#include "BLE2901.h"
+
+BLE2901::BLE2901() : BLEDescriptor(BLEUUID((uint16_t)0x2901)) {}  // BLE2901
+
+/**
+ * @brief Set the Characteristic User Description
+ */
+void BLE2901::setDescription(String userDesc) {
+  if (userDesc.length() > ESP_GATT_MAX_ATTR_LEN) {
+    log_e("Size %d too large, must be no bigger than %d", userDesc.length(), ESP_GATT_MAX_ATTR_LEN);
+    return;
+  }
+  setValue(userDesc);
+}
+
+#endif
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLE2901.h b/libraries/BLE/src/BLE2901.h
new file mode 100644
index 00000000000..f5ad7c94add
--- /dev/null
+++ b/libraries/BLE/src/BLE2901.h
@@ -0,0 +1,37 @@
+/*
+   BLE2901.h
+
+     GATT Descriptor 0x2901 Characteristic User Description
+
+     The value of this description is a user-readable string
+     describing the characteristic.
+
+     The Characteristic User Description descriptor
+     provides a textual user description for a characteristic
+     value.
+     If the Writable Auxiliary bit of the Characteristics
+     Properties is set then this descriptor is written. Only one
+     User Description descriptor exists in a characteristic
+     definition.
+
+*/
+
+#ifndef COMPONENTS_CPP_UTILS_BLE2901_H_
+#define COMPONENTS_CPP_UTILS_BLE2901_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
+#include "sdkconfig.h"
+#if defined(CONFIG_BLUEDROID_ENABLED)
+
+#include "BLEDescriptor.h"
+
+class BLE2901 : public BLEDescriptor {
+public:
+  BLE2901();
+  void setDescription(String desc);
+};  // BLE2901
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
+#endif /* COMPONENTS_CPP_UTILS_BLE2901_H_ */
diff --git a/libraries/BLE/src/BLE2902.cpp b/libraries/BLE/src/BLE2902.cpp
index 23d9c77c093..90cdf088ff2 100644
--- a/libraries/BLE/src/BLE2902.cpp
+++ b/libraries/BLE/src/BLE2902.cpp
@@ -9,54 +9,62 @@
  * See also:
  * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.client_characteristic_configuration.xml
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include "BLE2902.h"
 
-BLE2902::BLE2902() : BLEDescriptor(BLEUUID((uint16_t) 0x2902)) {
-	uint8_t data[2] = { 0, 0 };
-	setValue(data, 2);
-} // BLE2902
-
+BLE2902::BLE2902() : BLEDescriptor(BLEUUID((uint16_t)0x2902)) {
+  uint8_t data[2] = {0, 0};
+  setValue(data, 2);
+}  // BLE2902
 
 /**
  * @brief Get the notifications value.
  * @return The notifications value.  True if notifications are enabled and false if not.
  */
 bool BLE2902::getNotifications() {
-	return (getValue()[0] & (1 << 0)) != 0;
-} // getNotifications
-
+  return (getValue()[0] & (1 << 0)) != 0;
+}  // getNotifications
 
 /**
  * @brief Get the indications value.
  * @return The indications value.  True if indications are enabled and false if not.
  */
 bool BLE2902::getIndications() {
-	return (getValue()[0] & (1 << 1)) != 0;
-} // getIndications
-
+  return (getValue()[0] & (1 << 1)) != 0;
+}  // getIndications
 
 /**
  * @brief Set the indications flag.
  * @param [in] flag The indications flag.
  */
 void BLE2902::setIndications(bool flag) {
-	uint8_t *pValue = getValue();
-	if (flag) pValue[0] |= 1 << 1;
-	else pValue[0] &= ~(1 << 1);
-} // setIndications
-
+  uint8_t *pValue = getValue();
+  if (flag) {
+    pValue[0] |= 1 << 1;
+  } else {
+    pValue[0] &= ~(1 << 1);
+  }
+  setValue(pValue, 2);
+}  // setIndications
 
 /**
  * @brief Set the notifications flag.
  * @param [in] flag The notifications flag.
  */
 void BLE2902::setNotifications(bool flag) {
-	uint8_t *pValue = getValue();
-	if (flag) pValue[0] |= 1 << 0;
-	else pValue[0] &= ~(1 << 0);
-} // setNotifications
+  uint8_t *pValue = getValue();
+  if (flag) {
+    pValue[0] |= 1 << 0;
+  } else {
+    pValue[0] &= ~(1 << 0);
+  }
+  setValue(pValue, 2);
+}  // setNotifications
 
 #endif
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLE2902.h b/libraries/BLE/src/BLE2902.h
index 397360ab128..74a477f3151 100644
--- a/libraries/BLE/src/BLE2902.h
+++ b/libraries/BLE/src/BLE2902.h
@@ -7,8 +7,11 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLE2902_H_
 #define COMPONENTS_CPP_UTILS_BLE2902_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include "BLEDescriptor.h"
 
@@ -20,15 +23,16 @@
  * See also:
  * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.client_characteristic_configuration.xml
  */
-class BLE2902: public BLEDescriptor {
+class BLE2902 : public BLEDescriptor {
 public:
-	BLE2902();
-	bool getNotifications();
-	bool getIndications();
-	void setNotifications(bool flag);
-	void setIndications(bool flag);
+  BLE2902();
+  bool getNotifications();
+  bool getIndications();
+  void setNotifications(bool flag);
+  void setIndications(bool flag);
 
-}; // BLE2902
+};  // BLE2902
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLE2902_H_ */
diff --git a/libraries/BLE/src/BLE2904.cpp b/libraries/BLE/src/BLE2904.cpp
index 02252a1d676..aeed11ebad1 100644
--- a/libraries/BLE/src/BLE2904.cpp
+++ b/libraries/BLE/src/BLE2904.cpp
@@ -9,57 +9,54 @@
  * See also:
  * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include "BLE2904.h"
 
-
-BLE2904::BLE2904() : BLEDescriptor(BLEUUID((uint16_t) 0x2904)) {
-	m_data.m_format      = 0;
-	m_data.m_exponent    = 0;
-	m_data.m_namespace   = 1;  // 1 = Bluetooth SIG Assigned Numbers
-	m_data.m_unit        = 0;
-	m_data.m_description = 0;
-	setValue((uint8_t*) &m_data, sizeof(m_data));
-} // BLE2902
-
+BLE2904::BLE2904() : BLEDescriptor(BLEUUID((uint16_t)0x2904)) {
+  m_data.m_format = 0;
+  m_data.m_exponent = 0;
+  m_data.m_namespace = 1;  // 1 = Bluetooth SIG Assigned Numbers
+  m_data.m_unit = 0;
+  m_data.m_description = 0;
+  setValue((uint8_t *)&m_data, sizeof(m_data));
+}  // BLE2902
 
 /**
  * @brief Set the description.
  */
 void BLE2904::setDescription(uint16_t description) {
-	m_data.m_description = description;
-	setValue((uint8_t*) &m_data, sizeof(m_data));
+  m_data.m_description = description;
+  setValue((uint8_t *)&m_data, sizeof(m_data));
 }
 
-
 /**
  * @brief Set the exponent.
  */
 void BLE2904::setExponent(int8_t exponent) {
-	m_data.m_exponent = exponent;
-	setValue((uint8_t*) &m_data, sizeof(m_data));
-} // setExponent
-
+  m_data.m_exponent = exponent;
+  setValue((uint8_t *)&m_data, sizeof(m_data));
+}  // setExponent
 
 /**
  * @brief Set the format.
  */
 void BLE2904::setFormat(uint8_t format) {
-	m_data.m_format = format;
-	setValue((uint8_t*) &m_data, sizeof(m_data));
-} // setFormat
-
+  m_data.m_format = format;
+  setValue((uint8_t *)&m_data, sizeof(m_data));
+}  // setFormat
 
 /**
  * @brief Set the namespace.
  */
 void BLE2904::setNamespace(uint8_t namespace_value) {
-	m_data.m_namespace = namespace_value;
-	setValue((uint8_t*) &m_data, sizeof(m_data));
-} // setNamespace
-
+  m_data.m_namespace = namespace_value;
+  setValue((uint8_t *)&m_data, sizeof(m_data));
+}  // setNamespace
 
 /**
  * @brief Set the units for this value.  It should be one of the encoded values defined here:
@@ -67,8 +64,9 @@ void BLE2904::setNamespace(uint8_t namespace_value) {
  * @param [in] unit The type of units of this characteristic as defined by assigned numbers.
  */
 void BLE2904::setUnit(uint16_t unit) {
-	m_data.m_unit = unit;
-	setValue((uint8_t*) &m_data, sizeof(m_data));
-} // setUnit
+  m_data.m_unit = unit;
+  setValue((uint8_t *)&m_data, sizeof(m_data));
+}  // setUnit
 
 #endif
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLE2904.h b/libraries/BLE/src/BLE2904.h
index cb337e22bed..3ba66da0dc8 100644
--- a/libraries/BLE/src/BLE2904.h
+++ b/libraries/BLE/src/BLE2904.h
@@ -7,17 +7,20 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLE2904_H_
 #define COMPONENTS_CPP_UTILS_BLE2904_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include "BLEDescriptor.h"
 
 struct BLE2904_Data {
-	uint8_t  m_format;
-	int8_t   m_exponent;
-	uint16_t m_unit;      // See https://www.bluetooth.com/specifications/assigned-numbers/units
-	uint8_t  m_namespace;
-	uint16_t m_description;
+  uint8_t m_format;
+  int8_t m_exponent;
+  uint16_t m_unit;  // See https://www.bluetooth.com/specifications/assigned-numbers/units
+  uint8_t m_namespace;
+  uint16_t m_description;
 
 } __attribute__((packed));
 
@@ -29,46 +32,47 @@ struct BLE2904_Data {
  * See also:
  * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml
  */
-class BLE2904: public BLEDescriptor {
+class BLE2904 : public BLEDescriptor {
 public:
-	BLE2904();
-	static const uint8_t FORMAT_BOOLEAN   = 1;
-	static const uint8_t FORMAT_UINT2     = 2;
-	static const uint8_t FORMAT_UINT4     = 3;
-	static const uint8_t FORMAT_UINT8     = 4;
-	static const uint8_t FORMAT_UINT12    = 5;
-	static const uint8_t FORMAT_UINT16    = 6;
-	static const uint8_t FORMAT_UINT24    = 7;
-	static const uint8_t FORMAT_UINT32    = 8;
-	static const uint8_t FORMAT_UINT48    = 9;
-	static const uint8_t FORMAT_UINT64    = 10;
-	static const uint8_t FORMAT_UINT128   = 11;
-	static const uint8_t FORMAT_SINT8     = 12;
-	static const uint8_t FORMAT_SINT12    = 13;
-	static const uint8_t FORMAT_SINT16    = 14;
-	static const uint8_t FORMAT_SINT24    = 15;
-	static const uint8_t FORMAT_SINT32    = 16;
-	static const uint8_t FORMAT_SINT48    = 17;
-	static const uint8_t FORMAT_SINT64    = 18;
-	static const uint8_t FORMAT_SINT128   = 19;
-	static const uint8_t FORMAT_FLOAT32   = 20;
-	static const uint8_t FORMAT_FLOAT64   = 21;
-	static const uint8_t FORMAT_SFLOAT16  = 22;
-	static const uint8_t FORMAT_SFLOAT32  = 23;
-	static const uint8_t FORMAT_IEEE20601 = 24;
-	static const uint8_t FORMAT_UTF8      = 25;
-	static const uint8_t FORMAT_UTF16     = 26;
-	static const uint8_t FORMAT_OPAQUE    = 27;
+  BLE2904();
+  static const uint8_t FORMAT_BOOLEAN = 1;
+  static const uint8_t FORMAT_UINT2 = 2;
+  static const uint8_t FORMAT_UINT4 = 3;
+  static const uint8_t FORMAT_UINT8 = 4;
+  static const uint8_t FORMAT_UINT12 = 5;
+  static const uint8_t FORMAT_UINT16 = 6;
+  static const uint8_t FORMAT_UINT24 = 7;
+  static const uint8_t FORMAT_UINT32 = 8;
+  static const uint8_t FORMAT_UINT48 = 9;
+  static const uint8_t FORMAT_UINT64 = 10;
+  static const uint8_t FORMAT_UINT128 = 11;
+  static const uint8_t FORMAT_SINT8 = 12;
+  static const uint8_t FORMAT_SINT12 = 13;
+  static const uint8_t FORMAT_SINT16 = 14;
+  static const uint8_t FORMAT_SINT24 = 15;
+  static const uint8_t FORMAT_SINT32 = 16;
+  static const uint8_t FORMAT_SINT48 = 17;
+  static const uint8_t FORMAT_SINT64 = 18;
+  static const uint8_t FORMAT_SINT128 = 19;
+  static const uint8_t FORMAT_FLOAT32 = 20;
+  static const uint8_t FORMAT_FLOAT64 = 21;
+  static const uint8_t FORMAT_SFLOAT16 = 22;
+  static const uint8_t FORMAT_SFLOAT32 = 23;
+  static const uint8_t FORMAT_IEEE20601 = 24;
+  static const uint8_t FORMAT_UTF8 = 25;
+  static const uint8_t FORMAT_UTF16 = 26;
+  static const uint8_t FORMAT_OPAQUE = 27;
 
-	void setDescription(uint16_t);
-	void setExponent(int8_t exponent);
-	void setFormat(uint8_t format);
-	void setNamespace(uint8_t namespace_value);
-	void setUnit(uint16_t unit);
+  void setDescription(uint16_t);
+  void setExponent(int8_t exponent);
+  void setFormat(uint8_t format);
+  void setNamespace(uint8_t namespace_value);
+  void setUnit(uint16_t unit);
 
 private:
-	BLE2904_Data m_data;
-}; // BLE2904
+  BLE2904_Data m_data;
+};  // BLE2904
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLE2904_H_ */
diff --git a/libraries/BLE/src/BLEAddress.cpp b/libraries/BLE/src/BLEAddress.cpp
index 6d83b17e68e..b91ef3cc4de 100644
--- a/libraries/BLE/src/BLEAddress.cpp
+++ b/libraries/BLE/src/BLEAddress.cpp
@@ -4,8 +4,11 @@
  *  Created on: Jul 2, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include "BLEAddress.h"
 #include <string>
@@ -18,15 +21,13 @@
 #include "esp32-hal-log.h"
 #endif
 
-
 /**
  * @brief Create an address from the native ESP32 representation.
  * @param [in] address The native representation.
  */
 BLEAddress::BLEAddress(esp_bd_addr_t address) {
-	memcpy(m_address, address, ESP_BD_ADDR_LEN);
-} // BLEAddress
-
+  memcpy(m_address, address, ESP_BD_ADDR_LEN);
+}  // BLEAddress
 
 /**
  * @brief Create an address from a hex string
@@ -39,19 +40,20 @@ BLEAddress::BLEAddress(esp_bd_addr_t address) {
  *
  * @param [in] stringAddress The hex representation of the address.
  */
-BLEAddress::BLEAddress(std::string stringAddress) {
-	if (stringAddress.length() != 17) return;
-
-	int data[6];
-	sscanf(stringAddress.c_str(), "%x:%x:%x:%x:%x:%x", &data[0], &data[1], &data[2], &data[3], &data[4], &data[5]);
-	m_address[0] = (uint8_t) data[0];
-	m_address[1] = (uint8_t) data[1];
-	m_address[2] = (uint8_t) data[2];
-	m_address[3] = (uint8_t) data[3];
-	m_address[4] = (uint8_t) data[4];
-	m_address[5] = (uint8_t) data[5];
-} // BLEAddress
+BLEAddress::BLEAddress(String stringAddress) {
+  if (stringAddress.length() != 17) {
+    return;
+  }
 
+  int data[6];
+  sscanf(stringAddress.c_str(), "%x:%x:%x:%x:%x:%x", &data[0], &data[1], &data[2], &data[3], &data[4], &data[5]);
+  m_address[0] = (uint8_t)data[0];
+  m_address[1] = (uint8_t)data[1];
+  m_address[2] = (uint8_t)data[2];
+  m_address[3] = (uint8_t)data[3];
+  m_address[4] = (uint8_t)data[4];
+  m_address[5] = (uint8_t)data[5];
+}  // BLEAddress
 
 /**
  * @brief Determine if this address equals another.
@@ -59,18 +61,40 @@ BLEAddress::BLEAddress(std::string stringAddress) {
  * @return True if the addresses are equal.
  */
 bool BLEAddress::equals(BLEAddress otherAddress) {
-	return memcmp(otherAddress.getNative(), m_address, 6) == 0;
-} // equals
+  return memcmp(otherAddress.getNative(), m_address, ESP_BD_ADDR_LEN) == 0;
+}  // equals
+
+bool BLEAddress::operator==(const BLEAddress &otherAddress) const {
+  return memcmp(otherAddress.m_address, m_address, ESP_BD_ADDR_LEN) == 0;
+}
+
+bool BLEAddress::operator!=(const BLEAddress &otherAddress) const {
+  return !(*this == otherAddress);
+}
 
+bool BLEAddress::operator<(const BLEAddress &otherAddress) const {
+  return memcmp(m_address, otherAddress.m_address, ESP_BD_ADDR_LEN) < 0;
+}
+
+bool BLEAddress::operator<=(const BLEAddress &otherAddress) const {
+  return !(*this > otherAddress);
+}
+
+bool BLEAddress::operator>=(const BLEAddress &otherAddress) const {
+  return !(*this < otherAddress);
+}
+
+bool BLEAddress::operator>(const BLEAddress &otherAddress) const {
+  return memcmp(m_address, otherAddress.m_address, ESP_BD_ADDR_LEN) > 0;
+}
 
 /**
  * @brief Return the native representation of the address.
  * @return The native representation of the address.
  */
 esp_bd_addr_t *BLEAddress::getNative() {
-	return &m_address;
-} // getNative
-
+  return &m_address;
+}  // getNative
 
 /**
  * @brief Convert a BLE address to a string.
@@ -83,12 +107,14 @@ esp_bd_addr_t *BLEAddress::getNative() {
  *
  * @return The string representation of the address.
  */
-std::string BLEAddress::toString() {
-	auto size = 18;
-	char *res = (char*)malloc(size);
-	snprintf(res, size, "%02x:%02x:%02x:%02x:%02x:%02x", m_address[0], m_address[1], m_address[2], m_address[3], m_address[4], m_address[5]);
-	std::string ret(res);
-	free(res);
-	return ret;
-} // toString
+String BLEAddress::toString() {
+  auto size = 18;
+  char *res = (char *)malloc(size);
+  snprintf(res, size, "%02x:%02x:%02x:%02x:%02x:%02x", m_address[0], m_address[1], m_address[2], m_address[3], m_address[4], m_address[5]);
+  String ret(res);
+  free(res);
+  return ret;
+}  // toString
+
 #endif
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEAddress.h b/libraries/BLE/src/BLEAddress.h
index 7eff4da4bb6..f1c8aa9b632 100644
--- a/libraries/BLE/src/BLEAddress.h
+++ b/libraries/BLE/src/BLEAddress.h
@@ -7,12 +7,15 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEADDRESS_H_
 #define COMPONENTS_CPP_UTILS_BLEADDRESS_H_
+#include "soc/soc_caps.h"
+#include "WString.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
-#include <esp_gap_ble_api.h> // ESP32 BLE
+#if defined(CONFIG_BLUEDROID_ENABLED)
+#include <esp_gap_ble_api.h>  // ESP32 BLE
 #include <string>
 
-
 /**
  * @brief A %BLE device address.
  *
@@ -20,15 +23,22 @@
  */
 class BLEAddress {
 public:
-	BLEAddress(esp_bd_addr_t address);
-	BLEAddress(std::string stringAddress);
-	bool           equals(BLEAddress otherAddress);
-	esp_bd_addr_t* getNative();
-	std::string    toString();
+  BLEAddress(esp_bd_addr_t address);
+  BLEAddress(String stringAddress);
+  bool equals(BLEAddress otherAddress);
+  bool operator==(const BLEAddress &otherAddress) const;
+  bool operator!=(const BLEAddress &otherAddress) const;
+  bool operator<(const BLEAddress &otherAddress) const;
+  bool operator<=(const BLEAddress &otherAddress) const;
+  bool operator>(const BLEAddress &otherAddress) const;
+  bool operator>=(const BLEAddress &otherAddress) const;
+  esp_bd_addr_t *getNative();
+  String toString();
 
 private:
-	esp_bd_addr_t m_address;
+  esp_bd_addr_t m_address;
 };
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEADDRESS_H_ */
diff --git a/libraries/BLE/src/BLEAdvertisedDevice.cpp b/libraries/BLE/src/BLEAdvertisedDevice.cpp
index 4b9c3380e51..8752d24a199 100644
--- a/libraries/BLE/src/BLEAdvertisedDevice.cpp
+++ b/libraries/BLE/src/BLEAdvertisedDevice.cpp
@@ -11,35 +11,35 @@
  *  Created on: Jul 3, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <sstream>
 #include "BLEAdvertisedDevice.h"
 #include "BLEUtils.h"
 #include "esp32-hal-log.h"
 
 BLEAdvertisedDevice::BLEAdvertisedDevice() {
-	m_adFlag           = 0;
-	m_appearance       = 0;
-	m_deviceType       = 0;
-	m_manufacturerData = "";
-	m_name             = "";
-	m_rssi             = -9999;
-	m_serviceData      = {};
-	m_serviceDataUUIDs = {};
-	m_txPower          = 0;
-	m_pScan            = nullptr;
-
-	m_haveAppearance       = false;
-	m_haveManufacturerData = false;
-	m_haveName             = false;
-	m_haveRSSI             = false;
-	m_haveServiceData      = false;
-	m_haveServiceUUID      = false;
-	m_haveTXPower          = false;
-
-} // BLEAdvertisedDevice
-
+  m_adFlag = 0;
+  m_appearance = 0;
+  m_deviceType = 0;
+  m_manufacturerData = "";
+  m_name = "";
+  m_rssi = -9999;
+  m_serviceUUIDs = {};
+  m_serviceData = {};
+  m_serviceDataUUIDs = {};
+  m_txPower = 0;
+  m_pScan = nullptr;
+
+  m_haveAppearance = false;
+  m_haveManufacturerData = false;
+  m_haveName = false;
+  m_haveRSSI = false;
+  m_haveTXPower = false;
+
+}  // BLEAdvertisedDevice
 
 /**
  * @brief Get the address.
@@ -50,127 +50,136 @@ BLEAdvertisedDevice::BLEAdvertisedDevice() {
  * @return The address of the advertised device.
  */
 BLEAddress BLEAdvertisedDevice::getAddress() {
-	return m_address;
-} // getAddress
-
+  return m_address;
+}  // getAddress
 
 /**
  * @brief Get the appearance.
  *
  * A %BLE device can declare its own appearance.  The appearance is how it would like to be shown to an end user
- * typcially in the form of an icon.
+ * typically in the form of an icon.
  *
  * @return The appearance of the advertised device.
  */
 uint16_t BLEAdvertisedDevice::getAppearance() {
-	return m_appearance;
-} // getAppearance
-
+  return m_appearance;
+}  // getAppearance
 
 /**
  * @brief Get the manufacturer data.
  * @return The manufacturer data of the advertised device.
  */
-std::string BLEAdvertisedDevice::getManufacturerData() {
-	return m_manufacturerData;
-} // getManufacturerData
-
+String BLEAdvertisedDevice::getManufacturerData() {
+  return m_manufacturerData;
+}  // getManufacturerData
 
 /**
  * @brief Get the name.
  * @return The name of the advertised device.
  */
-std::string BLEAdvertisedDevice::getName() {
-	return m_name;
-} // getName
-
+String BLEAdvertisedDevice::getName() {
+  return m_name;
+}  // getName
 
 /**
  * @brief Get the RSSI.
  * @return The RSSI of the advertised device.
  */
 int BLEAdvertisedDevice::getRSSI() {
-	return m_rssi;
-} // getRSSI
-
+  return m_rssi;
+}  // getRSSI
 
 /**
  * @brief Get the scan object that created this advertisement.
  * @return The scan object.
  */
-BLEScan* BLEAdvertisedDevice::getScan() {
-	return m_pScan;
-} // getScan
+BLEScan *BLEAdvertisedDevice::getScan() {
+  return m_pScan;
+}  // getScan
 
 /**
  * @brief Get the number of service data.
  * @return Number of service data discovered.
  */
 int BLEAdvertisedDevice::getServiceDataCount() {
-	if (m_haveServiceData)
-		return m_serviceData.size();
-	else
-		return 0;
-
-} //getServiceDataCount
+  return m_serviceData.size();
+}  //getServiceDataCount
 
 /**
  * @brief Get the service data.
  * @return The ServiceData of the advertised device.
  */
-std::string BLEAdvertisedDevice::getServiceData() {
-	return m_serviceData[0];
-} //getServiceData
+String BLEAdvertisedDevice::getServiceData() {
+  return m_serviceData.empty() ? String() : m_serviceData.front();
+}  //getServiceData
 
 /**
  * @brief Get the service data.
  * @return The ServiceData of the advertised device.
  */
-std::string BLEAdvertisedDevice::getServiceData(int i) {
-	return m_serviceData[i];
-} //getServiceData
+String BLEAdvertisedDevice::getServiceData(int i) {
+  return m_serviceData[i];
+}  //getServiceData
+
+/**
+ * @brief Get the number of service data UUIDs.
+ * @return Number of service data UUIDs discovered.
+ */
+int BLEAdvertisedDevice::getServiceDataUUIDCount() {
+  return m_serviceDataUUIDs.size();
+}  //getServiceDataUUIDCount
 
 /**
  * @brief Get the service data UUID.
  * @return The service data UUID.
  */
 BLEUUID BLEAdvertisedDevice::getServiceDataUUID() {
-	return m_serviceDataUUIDs[0];
-} // getServiceDataUUID
+  return m_serviceDataUUIDs.empty() ? BLEUUID() : m_serviceDataUUIDs.front();
+}  // getServiceDataUUID
 
 /**
  * @brief Get the service data UUID.
  * @return The service data UUID.
  */
 BLEUUID BLEAdvertisedDevice::getServiceDataUUID(int i) {
-	return m_serviceDataUUIDs[i];
-} // getServiceDataUUID
+  return m_serviceDataUUIDs[i];
+}  // getServiceDataUUID
+
+/**
+ * @brief Get the number of service UUIDs.
+ * @return Number of service UUIDs discovered.
+ */
+int BLEAdvertisedDevice::getServiceUUIDCount() {
+  return m_serviceUUIDs.size();
+}  //getServiceUUIDCount
 
 /**
  * @brief Get the Service UUID.
  * @return The Service UUID of the advertised device.
  */
 BLEUUID BLEAdvertisedDevice::getServiceUUID() {
-	return m_serviceUUIDs[0];
-} // getServiceUUID
+  return m_serviceUUIDs.empty() ? BLEUUID() : m_serviceUUIDs.front();
+}  // getServiceUUID
 
 /**
  * @brief Get the Service UUID.
  * @return The Service UUID of the advertised device.
  */
 BLEUUID BLEAdvertisedDevice::getServiceUUID(int i) {
-	return m_serviceUUIDs[i];
-} // getServiceUUID
+  return m_serviceUUIDs[i];
+}  // getServiceUUID
 
 /**
  * @brief Check advertised serviced for existence required UUID
  * @return Return true if service is advertised
  */
-bool BLEAdvertisedDevice::isAdvertisingService(BLEUUID uuid){
-	for (int i = 0; i < m_serviceUUIDs.size(); i++) {
-		if (m_serviceUUIDs[i].equals(uuid)) return true;
-	}
-	return false;
+bool BLEAdvertisedDevice::isAdvertisingService(BLEUUID uuid) {
+  for (int i = 0; i < getServiceUUIDCount(); i++) {
+    if (m_serviceUUIDs[i].equals(uuid)) {
+      return true;
+    }
+  }
+  return false;
 }
 
 /**
@@ -178,73 +187,64 @@ bool BLEAdvertisedDevice::isAdvertisingService(BLEUUID uuid){
  * @return The TX Power of the advertised device.
  */
 int8_t BLEAdvertisedDevice::getTXPower() {
-	return m_txPower;
-} // getTXPower
-
-
+  return m_txPower;
+}  // getTXPower
 
 /**
  * @brief Does this advertisement have an appearance value?
  * @return True if there is an appearance value present.
  */
 bool BLEAdvertisedDevice::haveAppearance() {
-	return m_haveAppearance;
-} // haveAppearance
-
+  return m_haveAppearance;
+}  // haveAppearance
 
 /**
  * @brief Does this advertisement have manufacturer data?
  * @return True if there is manufacturer data present.
  */
 bool BLEAdvertisedDevice::haveManufacturerData() {
-	return m_haveManufacturerData;
-} // haveManufacturerData
-
+  return m_haveManufacturerData;
+}  // haveManufacturerData
 
 /**
  * @brief Does this advertisement have a name value?
  * @return True if there is a name value present.
  */
 bool BLEAdvertisedDevice::haveName() {
-	return m_haveName;
-} // haveName
-
+  return m_haveName;
+}  // haveName
 
 /**
  * @brief Does this advertisement have a signal strength value?
  * @return True if there is a signal strength value present.
  */
 bool BLEAdvertisedDevice::haveRSSI() {
-	return m_haveRSSI;
-} // haveRSSI
-
+  return m_haveRSSI;
+}  // haveRSSI
 
 /**
  * @brief Does this advertisement have a service data value?
  * @return True if there is a service data value present.
  */
 bool BLEAdvertisedDevice::haveServiceData() {
-	return m_haveServiceData;
-} // haveServiceData
-
+  return !m_serviceData.empty();
+}  // haveServiceData
 
 /**
  * @brief Does this advertisement have a service UUID value?
  * @return True if there is a service UUID value present.
  */
 bool BLEAdvertisedDevice::haveServiceUUID() {
-	return m_haveServiceUUID;
-} // haveServiceUUID
-
+  return !m_serviceUUIDs.empty();
+}  // haveServiceUUID
 
 /**
  * @brief Does this advertisement have a transmission power value?
  * @return True if there is a transmission power value present.
  */
 bool BLEAdvertisedDevice::haveTXPower() {
-	return m_haveTXPower;
-} // haveTXPower
-
+  return m_haveTXPower;
+}  // haveTXPower
 
 /**
  * @brief Parse the advertising pay load.
@@ -258,318 +258,342 @@ bool BLEAdvertisedDevice::haveTXPower() {
  *
  * https://www.bluetooth.com/specifications/assigned-numbers/generic-access-profile
  */
-void BLEAdvertisedDevice::parseAdvertisement(uint8_t* payload, size_t total_len) {
-	uint8_t length;
-	uint8_t ad_type;
-	uint8_t sizeConsumed = 0;
-	bool finished = false;
-	m_payload = payload;
-	m_payloadLength = total_len;
-
-	while(!finished) {
-		length = *payload;          // Retrieve the length of the record.
-		payload++;                  // Skip to type
-		sizeConsumed += 1 + length; // increase the size consumed.
-
-		if (length != 0) { // A length of 0 indicates that we have reached the end.
-			ad_type = *payload;
-			payload++;
-			length--;
-
-			char* pHex = BLEUtils::buildHexData(nullptr, payload, length);
-			log_d("Type: 0x%.2x (%s), length: %d, data: %s",
-					ad_type, BLEUtils::advTypeToString(ad_type), length, pHex);
-			free(pHex);
-
-			switch(ad_type) {
-				case ESP_BLE_AD_TYPE_NAME_CMPL: {   // Adv Data Type: 0x09
-					setName(std::string(reinterpret_cast<char*>(payload), length));
-					break;
-				} // ESP_BLE_AD_TYPE_NAME_CMPL
-
-				case ESP_BLE_AD_TYPE_TX_PWR: {      // Adv Data Type: 0x0A
-					setTXPower(*payload);
-					break;
-				} // ESP_BLE_AD_TYPE_TX_PWR
-
-				case ESP_BLE_AD_TYPE_APPEARANCE: { // Adv Data Type: 0x19
-					setAppearance(*reinterpret_cast<uint16_t*>(payload));
-					break;
-				} // ESP_BLE_AD_TYPE_APPEARANCE
-
-				case ESP_BLE_AD_TYPE_FLAG: {        // Adv Data Type: 0x01
-					setAdFlag(*payload);
-					break;
-				} // ESP_BLE_AD_TYPE_FLAG
-
-				case ESP_BLE_AD_TYPE_16SRV_CMPL:
-				case ESP_BLE_AD_TYPE_16SRV_PART: {   // Adv Data Type: 0x02
-					for (int var = 0; var < length/2; ++var) {
-						setServiceUUID(BLEUUID(*reinterpret_cast<uint16_t*>(payload + var * 2)));
-					}
-					break;
-				} // ESP_BLE_AD_TYPE_16SRV_PART
-
-				case ESP_BLE_AD_TYPE_32SRV_CMPL:
-				case ESP_BLE_AD_TYPE_32SRV_PART: {   // Adv Data Type: 0x04
-					for (int var = 0; var < length/4; ++var) {
-						setServiceUUID(BLEUUID(*reinterpret_cast<uint32_t*>(payload + var * 4)));
-					}
-					break;
-				} // ESP_BLE_AD_TYPE_32SRV_PART
-
-				case ESP_BLE_AD_TYPE_128SRV_CMPL: { // Adv Data Type: 0x07
-					setServiceUUID(BLEUUID(payload, 16, false));
-					break;
-				} // ESP_BLE_AD_TYPE_128SRV_CMPL
-
-				case ESP_BLE_AD_TYPE_128SRV_PART: { // Adv Data Type: 0x06
-					setServiceUUID(BLEUUID(payload, 16, false));
-					break;
-				} // ESP_BLE_AD_TYPE_128SRV_PART
-
-				// See CSS Part A 1.4 Manufacturer Specific Data
-				case ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE: {
-					setManufacturerData(std::string(reinterpret_cast<char*>(payload), length));
-					break;
-				} // ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE
-
-				case ESP_BLE_AD_TYPE_SERVICE_DATA: {  // Adv Data Type: 0x16 (Service Data) - 2 byte UUID
-					if (length < 2) {
-						log_e("Length too small for ESP_BLE_AD_TYPE_SERVICE_DATA");
-						break;
-					}
-					uint16_t uuid = *(uint16_t*)payload;
-					setServiceDataUUID(BLEUUID(uuid));
-					if (length > 2) {
-						setServiceData(std::string(reinterpret_cast<char*>(payload + 2), length - 2));
-					}
-					break;
-				} //ESP_BLE_AD_TYPE_SERVICE_DATA
-
-				case ESP_BLE_AD_TYPE_32SERVICE_DATA: {  // Adv Data Type: 0x20 (Service Data) - 4 byte UUID
-					if (length < 4) {
-						log_e("Length too small for ESP_BLE_AD_TYPE_32SERVICE_DATA");
-						break;
-					}
-					uint32_t uuid = *(uint32_t*) payload;
-					setServiceDataUUID(BLEUUID(uuid));
-					if (length > 4) {
-						setServiceData(std::string(reinterpret_cast<char*>(payload + 4), length - 4));
-					}
-					break;
-				} //ESP_BLE_AD_TYPE_32SERVICE_DATA
-
-				case ESP_BLE_AD_TYPE_128SERVICE_DATA: {  // Adv Data Type: 0x21 (Service Data) - 16 byte UUID
-					if (length < 16) {
-						log_e("Length too small for ESP_BLE_AD_TYPE_128SERVICE_DATA");
-						break;
-					}
-
-					setServiceDataUUID(BLEUUID(payload, (size_t)16, false));
-					if (length > 16) {
-						setServiceData(std::string(reinterpret_cast<char*>(payload + 16), length - 16));
-					}
-					break;
-				} //ESP_BLE_AD_TYPE_32SERVICE_DATA
-
-				default: {
-					log_d("Unhandled type: adType: %d - 0x%.2x", ad_type, ad_type);
-					break;
-				}
-			} // switch
-			payload += length;
-		} // Length <> 0
-
-
-		if (sizeConsumed >= total_len)
-			finished = true;
-
-	} // !finished
-} // parseAdvertisement
+void BLEAdvertisedDevice::parseAdvertisement(uint8_t *payload, size_t total_len) {
+  uint8_t length;
+  uint8_t ad_type;
+  uint8_t sizeConsumed = 0;
+  bool finished = false;
+  m_payload = payload;
+  m_payloadLength = total_len;
+
+  while (!finished) {
+    length = *payload;           // Retrieve the length of the record.
+    payload++;                   // Skip to type
+    sizeConsumed += 1 + length;  // increase the size consumed.
+
+    if (length != 0) {  // A length of 0 indicates that we have reached the end.
+      ad_type = *payload;
+      payload++;
+      length--;
+
+      char *pHex = BLEUtils::buildHexData(nullptr, payload, length);
+      log_d("Type: 0x%.2x (%s), length: %d, data: %s", ad_type, BLEUtils::advTypeToString(ad_type), length, pHex);
+      free(pHex);
+
+      switch (ad_type) {
+        case ESP_BLE_AD_TYPE_NAME_CMPL:
+        {  // Adv Data Type: 0x09
+          setName(String(reinterpret_cast<char *>(payload), length));
+          break;
+        }  // ESP_BLE_AD_TYPE_NAME_CMPL
+
+        case ESP_BLE_AD_TYPE_TX_PWR:
+        {  // Adv Data Type: 0x0A
+          setTXPower(*payload);
+          break;
+        }  // ESP_BLE_AD_TYPE_TX_PWR
+
+        case ESP_BLE_AD_TYPE_APPEARANCE:
+        {  // Adv Data Type: 0x19
+          setAppearance(*reinterpret_cast<uint16_t *>(payload));
+          break;
+        }  // ESP_BLE_AD_TYPE_APPEARANCE
+
+        case ESP_BLE_AD_TYPE_FLAG:
+        {  // Adv Data Type: 0x01
+          setAdFlag(*payload);
+          break;
+        }  // ESP_BLE_AD_TYPE_FLAG
+
+        case ESP_BLE_AD_TYPE_16SRV_CMPL:
+        case ESP_BLE_AD_TYPE_16SRV_PART:
+        {  // Adv Data Type: 0x02
+          for (int var = 0; var < length / 2; ++var) {
+            setServiceUUID(BLEUUID(*reinterpret_cast<uint16_t *>(payload + var * 2)));
+          }
+          break;
+        }  // ESP_BLE_AD_TYPE_16SRV_PART
+
+        case ESP_BLE_AD_TYPE_32SRV_CMPL:
+        case ESP_BLE_AD_TYPE_32SRV_PART:
+        {  // Adv Data Type: 0x04
+          for (int var = 0; var < length / 4; ++var) {
+            setServiceUUID(BLEUUID(*reinterpret_cast<uint32_t *>(payload + var * 4)));
+          }
+          break;
+        }  // ESP_BLE_AD_TYPE_32SRV_PART
+
+        case ESP_BLE_AD_TYPE_128SRV_CMPL:
+        {  // Adv Data Type: 0x07
+          setServiceUUID(BLEUUID(payload, 16, false));
+          break;
+        }  // ESP_BLE_AD_TYPE_128SRV_CMPL
+
+        case ESP_BLE_AD_TYPE_128SRV_PART:
+        {  // Adv Data Type: 0x06
+          setServiceUUID(BLEUUID(payload, 16, false));
+          break;
+        }  // ESP_BLE_AD_TYPE_128SRV_PART
+
+        // See CSS Part A 1.4 Manufacturer Specific Data
+        case ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE:
+        {
+          setManufacturerData(String(reinterpret_cast<char *>(payload), length));
+          break;
+        }  // ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE
+
+        case ESP_BLE_AD_TYPE_SERVICE_DATA:
+        {  // Adv Data Type: 0x16 (Service Data) - 2 byte UUID
+          if (length < 2) {
+            log_e("Length too small for ESP_BLE_AD_TYPE_SERVICE_DATA");
+            break;
+          }
+          uint16_t uuid = *(uint16_t *)payload;
+          setServiceDataUUID(BLEUUID(uuid));
+          if (length > 2) {
+            setServiceData(String(reinterpret_cast<char *>(payload + 2), length - 2));
+          }
+          break;
+        }  //ESP_BLE_AD_TYPE_SERVICE_DATA
+
+        case ESP_BLE_AD_TYPE_32SERVICE_DATA:
+        {  // Adv Data Type: 0x20 (Service Data) - 4 byte UUID
+          if (length < 4) {
+            log_e("Length too small for ESP_BLE_AD_TYPE_32SERVICE_DATA");
+            break;
+          }
+          uint32_t uuid = *(uint32_t *)payload;
+          setServiceDataUUID(BLEUUID(uuid));
+          if (length > 4) {
+            setServiceData(String(reinterpret_cast<char *>(payload + 4), length - 4));
+          }
+          break;
+        }  //ESP_BLE_AD_TYPE_32SERVICE_DATA
+
+        case ESP_BLE_AD_TYPE_128SERVICE_DATA:
+        {  // Adv Data Type: 0x21 (Service Data) - 16 byte UUID
+          if (length < 16) {
+            log_e("Length too small for ESP_BLE_AD_TYPE_128SERVICE_DATA");
+            break;
+          }
+
+          setServiceDataUUID(BLEUUID(payload, (size_t)16, false));
+          if (length > 16) {
+            setServiceData(String(reinterpret_cast<char *>(payload + 16), length - 16));
+          }
+          break;
+        }  //ESP_BLE_AD_TYPE_32SERVICE_DATA
+
+        default:
+        {
+          log_d("Unhandled type: adType: %d - 0x%.2x", ad_type, ad_type);
+          break;
+        }
+      }  // switch
+      payload += length;
+    }  // Length <> 0
+
+    if (sizeConsumed >= total_len) {
+      finished = true;
+    }
+
+  }  // !finished
+}  // parseAdvertisement
 
 /**
  * @brief Parse the advertising payload.
  * @param [in] payload The payload of the advertised device.
  * @param [in] total_len The length of payload
  */
-void BLEAdvertisedDevice::setPayload(uint8_t* payload, size_t total_len) {
-	m_payload = payload;
-	m_payloadLength = total_len;
-} // setPayload
+void BLEAdvertisedDevice::setPayload(uint8_t *payload, size_t total_len) {
+  m_payload = payload;
+  m_payloadLength = total_len;
+}  // setPayload
 
 /**
  * @brief Set the address of the advertised device.
  * @param [in] address The address of the advertised device.
  */
 void BLEAdvertisedDevice::setAddress(BLEAddress address) {
-	m_address = address;
-} // setAddress
-
+  m_address = address;
+}  // setAddress
 
 /**
  * @brief Set the adFlag for this device.
  * @param [in] The discovered adFlag.
  */
 void BLEAdvertisedDevice::setAdFlag(uint8_t adFlag) {
-	m_adFlag = adFlag;
-} // setAdFlag
-
+  m_adFlag = adFlag;
+}  // setAdFlag
 
 /**
  * @brief Set the appearance for this device.
  * @param [in] The discovered appearance.
  */
 void BLEAdvertisedDevice::setAppearance(uint16_t appearance) {
-	m_appearance     = appearance;
-	m_haveAppearance = true;
-	log_d("- appearance: %d", m_appearance);
-} // setAppearance
-
+  m_appearance = appearance;
+  m_haveAppearance = true;
+  log_d("- appearance: %d", m_appearance);
+}  // setAppearance
 
 /**
  * @brief Set the manufacturer data for this device.
  * @param [in] The discovered manufacturer data.
  */
-void BLEAdvertisedDevice::setManufacturerData(std::string manufacturerData) {
-	m_manufacturerData     = manufacturerData;
-	m_haveManufacturerData = true;
-	char* pHex = BLEUtils::buildHexData(nullptr, (uint8_t*) m_manufacturerData.data(), (uint8_t) m_manufacturerData.length());
-	log_d("- manufacturer data: %s", pHex);
-	free(pHex);
-} // setManufacturerData
-
+void BLEAdvertisedDevice::setManufacturerData(String manufacturerData) {
+  m_manufacturerData = manufacturerData;
+  m_haveManufacturerData = true;
+  char *pHex = BLEUtils::buildHexData(nullptr, (uint8_t *)m_manufacturerData.c_str(), (uint8_t)m_manufacturerData.length());
+  log_d("- manufacturer data: %s", pHex);
+  free(pHex);
+}  // setManufacturerData
 
 /**
  * @brief Set the name for this device.
  * @param [in] name The discovered name.
  */
-void BLEAdvertisedDevice::setName(std::string name) {
-	m_name     = name;
-	m_haveName = true;
-	log_d("- setName(): name: %s", m_name.c_str());
-} // setName
-
+void BLEAdvertisedDevice::setName(String name) {
+  m_name = name;
+  m_haveName = true;
+  log_d("- setName(): name: %s", m_name.c_str());
+}  // setName
 
 /**
  * @brief Set the RSSI for this device.
  * @param [in] rssi The discovered RSSI.
  */
 void BLEAdvertisedDevice::setRSSI(int rssi) {
-	m_rssi     = rssi;
-	m_haveRSSI = true;
-	log_d("- setRSSI(): rssi: %d", m_rssi);
-} // setRSSI
-
+  m_rssi = rssi;
+  m_haveRSSI = true;
+  log_d("- setRSSI(): rssi: %d", m_rssi);
+}  // setRSSI
 
 /**
  * @brief Set the Scan that created this advertised device.
  * @param pScan The Scan that created this advertised device.
  */
-void BLEAdvertisedDevice::setScan(BLEScan* pScan) {
-	m_pScan = pScan;
-} // setScan
-
+void BLEAdvertisedDevice::setScan(BLEScan *pScan) {
+  m_pScan = pScan;
+}  // setScan
 
 /**
  * @brief Set the Service UUID for this device.
  * @param [in] serviceUUID The discovered serviceUUID
  */
-void BLEAdvertisedDevice::setServiceUUID(const char* serviceUUID) {
-	return setServiceUUID(BLEUUID(serviceUUID));
-} // setServiceUUID
-
+void BLEAdvertisedDevice::setServiceUUID(const char *serviceUUID) {
+  return setServiceUUID(BLEUUID(serviceUUID));
+}  // setServiceUUID
 
 /**
  * @brief Set the Service UUID for this device.
  * @param [in] serviceUUID The discovered serviceUUID
  */
 void BLEAdvertisedDevice::setServiceUUID(BLEUUID serviceUUID) {
-	m_serviceUUIDs.push_back(serviceUUID);
-	m_haveServiceUUID = true;
-	log_d("- addServiceUUID(): serviceUUID: %s", serviceUUID.toString().c_str());
-} // setServiceUUID
-
+  m_serviceUUIDs.push_back(serviceUUID);
+  log_d("- addServiceUUID(): serviceUUID: %s", serviceUUID.toString().c_str());
+}  // setServiceUUID
 
 /**
  * @brief Set the ServiceData value.
  * @param [in] data ServiceData value.
  */
-void BLEAdvertisedDevice::setServiceData(std::string serviceData) {
-	m_haveServiceData = true;         // Set the flag that indicates we have service data.
-	m_serviceData.push_back(serviceData); // Save the service data that we received.
-} //setServiceData
-
+void BLEAdvertisedDevice::setServiceData(String serviceData) {
+  m_serviceData.push_back(serviceData);  // Save the service data that we received.
+}  //setServiceData
 
 /**
  * @brief Set the ServiceDataUUID value.
  * @param [in] data ServiceDataUUID value.
  */
 void BLEAdvertisedDevice::setServiceDataUUID(BLEUUID uuid) {
-	m_haveServiceData = true;         // Set the flag that indicates we have service data.
-	m_serviceDataUUIDs.push_back(uuid);
-	log_d("- addServiceDataUUID(): serviceDataUUID: %s", uuid.toString().c_str());
-} // setServiceDataUUID
-
+  m_serviceDataUUIDs.push_back(uuid);
+  log_d("- addServiceDataUUID(): serviceDataUUID: %s", uuid.toString().c_str());
+}  // setServiceDataUUID
 
 /**
  * @brief Set the power level for this device.
  * @param [in] txPower The discovered power level.
  */
 void BLEAdvertisedDevice::setTXPower(int8_t txPower) {
-	m_txPower     = txPower;
-	m_haveTXPower = true;
-	log_d("- txPower: %d", m_txPower);
-} // setTXPower
-
+  m_txPower = txPower;
+  m_haveTXPower = true;
+  log_d("- txPower: %d", m_txPower);
+}  // setTXPower
 
 /**
  * @brief Create a string representation of this device.
  * @return A string representation of this device.
  */
-std::string BLEAdvertisedDevice::toString() {
-	std::string res = "Name: " + getName() + ", Address: " + getAddress().toString();
-	if (haveAppearance()) {
-		char val[6];
-		snprintf(val, sizeof(val), "%d", getAppearance());
-		res += ", appearance: ";
-		res += val;
-	}
-	if (haveManufacturerData()) {
-		char *pHex = BLEUtils::buildHexData(nullptr, (uint8_t*)getManufacturerData().data(), getManufacturerData().length());
-		res += ", manufacturer data: ";
-		res += pHex;
-		free(pHex);
-	}
-	if (haveServiceUUID()) {
-		for (int i=0; i < m_serviceUUIDs.size(); i++) {
-		    res += ", serviceUUID: " + getServiceUUID(i).toString();
-		}
-	}
-	if (haveTXPower()) {
-		char val[4];
-		snprintf(val, sizeof(val), "%d", getTXPower());
-		res += ", txPower: ";
-		res += val;
-	}
-	return res;
-} // toString
-
-uint8_t* BLEAdvertisedDevice::getPayload() {
-	return m_payload;
+String BLEAdvertisedDevice::toString() {
+  String res = "Name: " + getName() + ", Address: " + getAddress().toString();
+  if (haveAppearance()) {
+    char val[6];
+    snprintf(val, sizeof(val), "%d", getAppearance());
+    res += ", appearance: ";
+    res += val;
+  }
+  if (haveManufacturerData()) {
+    char *pHex = BLEUtils::buildHexData(nullptr, (uint8_t *)getManufacturerData().c_str(), getManufacturerData().length());
+    res += ", manufacturer data: ";
+    res += pHex;
+    free(pHex);
+  }
+  if (haveServiceUUID()) {
+    for (int i = 0; i < getServiceUUIDCount(); i++) {
+      res += ", serviceUUID: " + getServiceUUID(i).toString();
+    }
+  }
+  if (haveTXPower()) {
+    char val[6];
+    snprintf(val, sizeof(val), "%d", getTXPower());
+    res += ", txPower: ";
+    res += val;
+  }
+  if (haveRSSI()) {
+    char val[4];
+    snprintf(val, sizeof(val), "%i", getRSSI());
+    res += ", rssi: ";
+    res += val;
+  }
+  if (haveServiceData()) {
+    for (int i = 0; i < getServiceDataCount(); i++) {
+      res += ", serviceData: " + getServiceData(i);
+    }
+  }
+  return res;
+}  // toString
+
+uint8_t *BLEAdvertisedDevice::getPayload() {
+  return m_payload;
 }
 
 esp_ble_addr_type_t BLEAdvertisedDevice::getAddressType() {
-	return m_addressType;
+  return m_addressType;
+}
+
+ble_frame_type_t BLEAdvertisedDevice::getFrameType() {
+  for (int i = 0; i < m_payloadLength; ++i) {
+    log_d("check [%d]=0x%02X", i, m_payload[i]);
+    if (m_payload[i] == 0x16 && m_payloadLength >= i + 3 && m_payload[i + 1] == 0xAA && m_payload[i + 2] == 0xFE && m_payload[i + 3] == 0x00) {
+      return BLE_EDDYSTONE_UUID_FRAME;
+    }
+    if (m_payload[i] == 0x16 && m_payloadLength >= i + 3 && m_payload[i + 1] == 0xAA && m_payload[i + 2] == 0xFE && m_payload[i + 3] == 0x10) {
+      return BLE_EDDYSTONE_URL_FRAME;
+    }
+    if (m_payload[i] == 0x16 && m_payloadLength >= i + 3 && m_payload[i + 1] == 0xAA && m_payload[i + 2] == 0xFE && m_payload[i + 3] == 0x20) {
+      return BLE_EDDYSTONE_TLM_FRAME;
+    }
+  }
+  return BLE_UNKNOWN_FRAME;
 }
 
 void BLEAdvertisedDevice::setAddressType(esp_ble_addr_type_t type) {
-	m_addressType = type;
+  m_addressType = type;
 }
 
 size_t BLEAdvertisedDevice::getPayloadLength() {
-	return m_payloadLength;
+  return m_payloadLength;
 }
 
-#endif /* CONFIG_BT_ENABLED */
-
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEAdvertisedDevice.h b/libraries/BLE/src/BLEAdvertisedDevice.h
index 4cfa494e38d..700e5704034 100644
--- a/libraries/BLE/src/BLEAdvertisedDevice.h
+++ b/libraries/BLE/src/BLEAdvertisedDevice.h
@@ -7,8 +7,11 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEADVERTISEDDEVICE_H_
 #define COMPONENTS_CPP_UTILS_BLEADVERTISEDDEVICE_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <esp_gattc_api.h>
 
 #include <map>
@@ -17,6 +20,13 @@
 #include "BLEScan.h"
 #include "BLEUUID.h"
 
+typedef enum {
+  BLE_UNKNOWN_FRAME,
+  BLE_EDDYSTONE_UUID_FRAME,
+  BLE_EDDYSTONE_URL_FRAME,
+  BLE_EDDYSTONE_TLM_FRAME,
+  BLE_FRAME_MAX
+} ble_frame_type_t;
 
 class BLEScan;
 /**
@@ -27,82 +37,81 @@ class BLEScan;
  */
 class BLEAdvertisedDevice {
 public:
-	BLEAdvertisedDevice();
-
-	BLEAddress  getAddress();
-	uint16_t    getAppearance();
-	std::string getManufacturerData();
-	std::string getName();
-	int         getRSSI();
-	BLEScan*    getScan();
-	std::string getServiceData();
-	std::string getServiceData(int i);
-	BLEUUID     getServiceDataUUID();
-	BLEUUID     getServiceDataUUID(int i);
-	BLEUUID     getServiceUUID();
-	BLEUUID     getServiceUUID(int i);
-	int         getServiceDataCount();
-	int8_t      getTXPower();
-	uint8_t* 	getPayload();
-	size_t		getPayloadLength();
-	esp_ble_addr_type_t getAddressType();
-	void setAddressType(esp_ble_addr_type_t type);
-
-
-	bool		isAdvertisingService(BLEUUID uuid);
-	bool        haveAppearance();
-	bool        haveManufacturerData();
-	bool        haveName();
-	bool        haveRSSI();
-	bool        haveServiceData();
-	bool        haveServiceUUID();
-	bool        haveTXPower();
-
-	std::string toString();
+  BLEAdvertisedDevice();
+
+  BLEAddress getAddress();
+  uint16_t getAppearance();
+  String getManufacturerData();
+  String getName();
+  int getRSSI();
+  BLEScan *getScan();
+  String getServiceData();
+  String getServiceData(int i);
+  BLEUUID getServiceDataUUID();
+  BLEUUID getServiceDataUUID(int i);
+  BLEUUID getServiceUUID();
+  BLEUUID getServiceUUID(int i);
+  int getServiceDataCount();
+  int getServiceDataUUIDCount();
+  int getServiceUUIDCount();
+  int8_t getTXPower();
+  uint8_t *getPayload();
+  size_t getPayloadLength();
+  esp_ble_addr_type_t getAddressType();
+  ble_frame_type_t getFrameType();
+  void setAddressType(esp_ble_addr_type_t type);
+
+  bool isAdvertisingService(BLEUUID uuid);
+  bool haveAppearance();
+  bool haveManufacturerData();
+  bool haveName();
+  bool haveRSSI();
+  bool haveServiceData();
+  bool haveServiceUUID();
+  bool haveTXPower();
+
+  String toString();
 
 private:
-	friend class BLEScan;
-
-	void parseAdvertisement(uint8_t* payload, size_t total_len=62);
-	void setPayload(uint8_t* payload, size_t total_len=62);
-	void setAddress(BLEAddress address);
-	void setAdFlag(uint8_t adFlag);
-	void setAdvertizementResult(uint8_t* payload);
-	void setAppearance(uint16_t appearance);
-	void setManufacturerData(std::string manufacturerData);
-	void setName(std::string name);
-	void setRSSI(int rssi);
-	void setScan(BLEScan* pScan);
-	void setServiceData(std::string data);
-	void setServiceDataUUID(BLEUUID uuid);
-	void setServiceUUID(const char* serviceUUID);
-	void setServiceUUID(BLEUUID serviceUUID);
-	void setTXPower(int8_t txPower);
-
-	bool m_haveAppearance;
-	bool m_haveManufacturerData;
-	bool m_haveName;
-	bool m_haveRSSI;
-	bool m_haveServiceData;
-	bool m_haveServiceUUID;
-	bool m_haveTXPower;
-
-
-	BLEAddress  m_address = BLEAddress((uint8_t*)"\0\0\0\0\0\0");
-	uint8_t     m_adFlag;
-	uint16_t    m_appearance;
-	int         m_deviceType;
-	std::string m_manufacturerData;
-	std::string m_name;
-	BLEScan*    m_pScan;
-	int         m_rssi;
-	std::vector<BLEUUID> m_serviceUUIDs;
-	int8_t      m_txPower;
-	std::vector<std::string> m_serviceData;
-	std::vector<BLEUUID> m_serviceDataUUIDs;
-	uint8_t*	m_payload;
-	size_t		m_payloadLength = 0;
-	esp_ble_addr_type_t m_addressType;
+  friend class BLEScan;
+
+  void parseAdvertisement(uint8_t *payload, size_t total_len = 62);
+  void setPayload(uint8_t *payload, size_t total_len = 62);
+  void setAddress(BLEAddress address);
+  void setAdFlag(uint8_t adFlag);
+  void setAdvertizementResult(uint8_t *payload);
+  void setAppearance(uint16_t appearance);
+  void setManufacturerData(String manufacturerData);
+  void setName(String name);
+  void setRSSI(int rssi);
+  void setScan(BLEScan *pScan);
+  void setServiceData(String data);
+  void setServiceDataUUID(BLEUUID uuid);
+  void setServiceUUID(const char *serviceUUID);
+  void setServiceUUID(BLEUUID serviceUUID);
+  void setTXPower(int8_t txPower);
+
+  bool m_haveAppearance;
+  bool m_haveManufacturerData;
+  bool m_haveName;
+  bool m_haveRSSI;
+  bool m_haveTXPower;
+
+  BLEAddress m_address = BLEAddress((uint8_t *)"\0\0\0\0\0\0");
+  uint8_t m_adFlag;
+  uint16_t m_appearance;
+  int m_deviceType;
+  String m_manufacturerData;
+  String m_name;
+  BLEScan *m_pScan;
+  int m_rssi;
+  std::vector<BLEUUID> m_serviceUUIDs;
+  int8_t m_txPower;
+  std::vector<String> m_serviceData;
+  std::vector<BLEUUID> m_serviceDataUUIDs;
+  uint8_t *m_payload;
+  size_t m_payloadLength = 0;
+  esp_ble_addr_type_t m_addressType;
 };
 
 /**
@@ -114,15 +123,30 @@ class BLEAdvertisedDevice {
  */
 class BLEAdvertisedDeviceCallbacks {
 public:
-	virtual ~BLEAdvertisedDeviceCallbacks() {}
-	/**
+  virtual ~BLEAdvertisedDeviceCallbacks() {}
+  /**
+	 * @brief Called when a new scan result is detected.
+	 *
+	 * As we are scanning, we will find new devices.  When found, this call back is invoked with a reference to the
+	 * device that was found.  During any individual scan, a device will only be detected one time.
+	 */
+  virtual void onResult(BLEAdvertisedDevice advertisedDevice) = 0;
+};
+
+#ifdef SOC_BLE_50_SUPPORTED
+class BLEExtAdvertisingCallbacks {
+public:
+  virtual ~BLEExtAdvertisingCallbacks() {}
+  /**
 	 * @brief Called when a new scan result is detected.
 	 *
 	 * As we are scanning, we will find new devices.  When found, this call back is invoked with a reference to the
 	 * device that was found.  During any individual scan, a device will only be detected one time.
 	 */
-	virtual void onResult(BLEAdvertisedDevice advertisedDevice) = 0;
+  virtual void onResult(esp_ble_gap_ext_adv_report_t report) = 0;
 };
+#endif  // SOC_BLE_50_SUPPORTED
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEADVERTISEDDEVICE_H_ */
diff --git a/libraries/BLE/src/BLEAdvertising.cpp b/libraries/BLE/src/BLEAdvertising.cpp
index 58f371ed981..fe39a69c206 100644
--- a/libraries/BLE/src/BLEAdvertising.cpp
+++ b/libraries/BLE/src/BLEAdvertising.cpp
@@ -16,8 +16,11 @@
  * set in the data will be advertised.
  *
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include "BLEAdvertising.h"
 #include <esp_err.h>
 #include "BLEUtils.h"
@@ -28,53 +31,85 @@
  * @brief Construct a default advertising object.
  *
  */
-BLEAdvertising::BLEAdvertising()
-: m_scanRespData{}
-{
-	m_advData.set_scan_rsp        = false;
-	m_advData.include_name        = true;
-	m_advData.include_txpower     = true;
-	m_advData.min_interval        = 0x20;
-	m_advData.max_interval        = 0x40;
-	m_advData.appearance          = 0x00;
-	m_advData.manufacturer_len    = 0;
-	m_advData.p_manufacturer_data = nullptr;
-	m_advData.service_data_len    = 0;
-	m_advData.p_service_data      = nullptr;
-	m_advData.service_uuid_len    = 0;
-	m_advData.p_service_uuid      = nullptr;
-	m_advData.flag                = (ESP_BLE_ADV_FLAG_GEN_DISC | ESP_BLE_ADV_FLAG_BREDR_NOT_SPT);
-
-	m_advParams.adv_int_min       = 0x20;
-	m_advParams.adv_int_max       = 0x40;
-	m_advParams.adv_type          = ADV_TYPE_IND;
-	m_advParams.own_addr_type     = BLE_ADDR_TYPE_PUBLIC;
-	m_advParams.channel_map       = ADV_CHNL_ALL;
-	m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY;
-	m_advParams.peer_addr_type    = BLE_ADDR_TYPE_PUBLIC;
-
-	m_customAdvData               = false;   // No custom advertising data
-	m_customScanResponseData      = false;   // No custom scan response data
-} // BLEAdvertising
-
+BLEAdvertising::BLEAdvertising() : m_scanRespData{} {
+  m_advData.set_scan_rsp = false;
+  m_advData.include_name = true;
+  m_advData.include_txpower = true;
+  m_advData.min_interval = 0x20;
+  m_advData.max_interval = 0x40;
+  m_advData.appearance = 0x00;
+  m_advData.manufacturer_len = 0;
+  m_advData.p_manufacturer_data = nullptr;
+  m_advData.service_data_len = 0;
+  m_advData.p_service_data = nullptr;
+  m_advData.service_uuid_len = 0;
+  m_advData.p_service_uuid = nullptr;
+  m_advData.flag = (ESP_BLE_ADV_FLAG_GEN_DISC | ESP_BLE_ADV_FLAG_BREDR_NOT_SPT);
+
+  m_advParams.adv_int_min = 0x20;
+  m_advParams.adv_int_max = 0x40;
+  m_advParams.adv_type = ADV_TYPE_IND;
+  m_advParams.own_addr_type = BLE_ADDR_TYPE_PUBLIC;
+  m_advParams.channel_map = ADV_CHNL_ALL;
+  m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY;
+  m_advParams.peer_addr_type = BLE_ADDR_TYPE_PUBLIC;
+
+  m_customAdvData = false;           // No custom advertising data
+  m_customScanResponseData = false;  // No custom scan response data
+}  // BLEAdvertising
 
 /**
  * @brief Add a service uuid to exposed list of services.
  * @param [in] serviceUUID The UUID of the service to expose.
  */
 void BLEAdvertising::addServiceUUID(BLEUUID serviceUUID) {
-	m_serviceUUIDs.push_back(serviceUUID);
-} // addServiceUUID
-
+  m_serviceUUIDs.push_back(serviceUUID);
+}  // addServiceUUID
 
 /**
  * @brief Add a service uuid to exposed list of services.
  * @param [in] serviceUUID The string representation of the service to expose.
  */
-void BLEAdvertising::addServiceUUID(const char* serviceUUID) {
-	addServiceUUID(BLEUUID(serviceUUID));
-} // addServiceUUID
+void BLEAdvertising::addServiceUUID(const char *serviceUUID) {
+  addServiceUUID(BLEUUID(serviceUUID));
+}  // addServiceUUID
+
+/**
+ * @brief Remove a service uuid to exposed list of services.
+ * @param [in] index The index of the service to stop exposing.
+ */
+bool BLEAdvertising::removeServiceUUID(int index) {
+
+  // If index is larger than the size of the
+  // advertised services, return false
+  if (index > m_serviceUUIDs.size()) {
+    return false;
+  }
 
+  m_serviceUUIDs.erase(m_serviceUUIDs.begin() + index);
+  return true;
+}
+
+/**
+ * @brief Remove a service uuid to exposed list of services.
+ * @param [in] serviceUUID The BLEUUID of the service to stop exposing.
+ */
+bool BLEAdvertising::removeServiceUUID(BLEUUID serviceUUID) {
+  for (int i = 0; i < m_serviceUUIDs.size(); i++) {
+    if (m_serviceUUIDs.at(i).equals(serviceUUID)) {
+      return removeServiceUUID(i);
+    }
+  }
+  return false;
+}
+
+/**
+ * @brief Remove a service uuid to exposed list of services.
+ * @param [in] serviceUUID The string of the service to stop exposing.
+ */
+bool BLEAdvertising::removeServiceUUID(const char *serviceUUID) {
+  return removeServiceUUID(BLEUUID(serviceUUID));
+}
 
 /**
  * @brief Set the device appearance in the advertising data.
@@ -84,31 +119,35 @@ void BLEAdvertising::addServiceUUID(const char* serviceUUID) {
  * @return N/A.
  */
 void BLEAdvertising::setAppearance(uint16_t appearance) {
-	m_advData.appearance = appearance;
-} // setAppearance
+  m_advData.appearance = appearance;
+}  // setAppearance
+
+void BLEAdvertising::setAdvertisementType(esp_ble_adv_type_t adv_type) {
+  m_advParams.adv_type = adv_type;
+}  // setAdvertisementType
 
-void BLEAdvertising::setAdvertisementType(esp_ble_adv_type_t adv_type){
-	m_advParams.adv_type = adv_type;
-} // setAdvertisementType
+void BLEAdvertising::setAdvertisementChannelMap(esp_ble_adv_channel_t channel_map) {
+  m_advParams.channel_map = channel_map;
+}  // setAdvertisementChannelMap
 
 void BLEAdvertising::setMinInterval(uint16_t mininterval) {
-	m_advParams.adv_int_min = mininterval;
-} // setMinInterval
+  m_advParams.adv_int_min = mininterval;
+}  // setMinInterval
 
 void BLEAdvertising::setMaxInterval(uint16_t maxinterval) {
-	m_advParams.adv_int_max = maxinterval;
-} // setMaxInterval
+  m_advParams.adv_int_max = maxinterval;
+}  // setMaxInterval
 
 void BLEAdvertising::setMinPreferred(uint16_t mininterval) {
-	m_advData.min_interval = mininterval;
-} // 
+  m_advData.min_interval = mininterval;
+}  //
 
 void BLEAdvertising::setMaxPreferred(uint16_t maxinterval) {
-	m_advData.max_interval = maxinterval;
-} // 
+  m_advData.max_interval = maxinterval;
+}  //
 
 void BLEAdvertising::setScanResponse(bool set) {
-	m_scanResp = set;
+  m_scanResp = set;
 }
 
 /**
@@ -117,152 +156,152 @@ void BLEAdvertising::setScanResponse(bool set) {
  * @param [in] connectWhitelistOnly If true, only allow connections from those on the white list.
  */
 void BLEAdvertising::setScanFilter(bool scanRequestWhitelistOnly, bool connectWhitelistOnly) {
-	log_v(">> setScanFilter: scanRequestWhitelistOnly: %d, connectWhitelistOnly: %d", scanRequestWhitelistOnly, connectWhitelistOnly);
-	if (!scanRequestWhitelistOnly && !connectWhitelistOnly) {
-		m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY;
-		log_v("<< setScanFilter");
-		return;
-	}
-	if (scanRequestWhitelistOnly && !connectWhitelistOnly) {
-		m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_WLST_CON_ANY;
-		log_v("<< setScanFilter");
-		return;
-	}
-	if (!scanRequestWhitelistOnly && connectWhitelistOnly) {
-		m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_WLST;
-		log_v("<< setScanFilter");
-		return;
-	}
-	if (scanRequestWhitelistOnly && connectWhitelistOnly) {
-		m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_WLST_CON_WLST;
-		log_v("<< setScanFilter");
-		return;
-	}
-} // setScanFilter
-
+  log_v(">> setScanFilter: scanRequestWhitelistOnly: %d, connectWhitelistOnly: %d", scanRequestWhitelistOnly, connectWhitelistOnly);
+  if (!scanRequestWhitelistOnly && !connectWhitelistOnly) {
+    m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY;
+    log_v("<< setScanFilter");
+    return;
+  }
+  if (scanRequestWhitelistOnly && !connectWhitelistOnly) {
+    m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_WLST_CON_ANY;
+    log_v("<< setScanFilter");
+    return;
+  }
+  if (!scanRequestWhitelistOnly && connectWhitelistOnly) {
+    m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_WLST;
+    log_v("<< setScanFilter");
+    return;
+  }
+  if (scanRequestWhitelistOnly && connectWhitelistOnly) {
+    m_advParams.adv_filter_policy = ADV_FILTER_ALLOW_SCAN_WLST_CON_WLST;
+    log_v("<< setScanFilter");
+    return;
+  }
+}  // setScanFilter
 
 /**
  * @brief Set the advertisement data that is to be published in a regular advertisement.
  * @param [in] advertisementData The data to be advertised.
  */
-void BLEAdvertising::setAdvertisementData(BLEAdvertisementData& advertisementData) {
-	log_v(">> setAdvertisementData");
-	esp_err_t errRc = ::esp_ble_gap_config_adv_data_raw(
-		(uint8_t*)advertisementData.getPayload().data(),
-		advertisementData.getPayload().length());
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gap_config_adv_data_raw: %d %s", errRc, GeneralUtils::errorToString(errRc));
-	}
-	m_customAdvData = true;   // Set the flag that indicates we are using custom advertising data.
-	log_v("<< setAdvertisementData");
-} // setAdvertisementData
-
+bool BLEAdvertising::setAdvertisementData(BLEAdvertisementData &advertisementData) {
+  log_v(">> setAdvertisementData");
+  esp_err_t errRc = ::esp_ble_gap_config_adv_data_raw((uint8_t *)advertisementData.getPayload().c_str(), advertisementData.getPayload().length());
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gap_config_adv_data_raw: %d %s", errRc, GeneralUtils::errorToString(errRc));
+  }
+  m_customAdvData = true;  // Set the flag that indicates we are using custom advertising data.
+  log_v("<< setAdvertisementData");
+  return ESP_OK == errRc;
+}  // setAdvertisementData
 
 /**
  * @brief Set the advertisement data that is to be published in a scan response.
  * @param [in] advertisementData The data to be advertised.
  */
-void BLEAdvertising::setScanResponseData(BLEAdvertisementData& advertisementData) {
-	log_v(">> setScanResponseData");
-	esp_err_t errRc = ::esp_ble_gap_config_scan_rsp_data_raw(
-		(uint8_t*)advertisementData.getPayload().data(),
-		advertisementData.getPayload().length());
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gap_config_scan_rsp_data_raw: %d %s", errRc, GeneralUtils::errorToString(errRc));
-	}
-	m_customScanResponseData = true;   // Set the flag that indicates we are using custom scan response data.
-	log_v("<< setScanResponseData");
-} // setScanResponseData
+bool BLEAdvertising::setScanResponseData(BLEAdvertisementData &advertisementData) {
+  log_v(">> setScanResponseData");
+  esp_err_t errRc = ::esp_ble_gap_config_scan_rsp_data_raw((uint8_t *)advertisementData.getPayload().c_str(), advertisementData.getPayload().length());
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gap_config_scan_rsp_data_raw: %d %s", errRc, GeneralUtils::errorToString(errRc));
+  }
+  m_customScanResponseData = true;  // Set the flag that indicates we are using custom scan response data.
+  log_v("<< setScanResponseData");
+  return ESP_OK == errRc;
+}  // setScanResponseData
 
 /**
  * @brief Start advertising.
  * Start advertising.
  * @return N/A.
  */
-void BLEAdvertising::start() {
-	log_v(">> start: customAdvData: %d, customScanResponseData: %d", m_customAdvData, m_customScanResponseData);
-
-	// We have a vector of service UUIDs that we wish to advertise.  In order to use the
-	// ESP-IDF framework, these must be supplied in a contiguous array of their 128bit (16 byte)
-	// representations.  If we have 1 or more services to advertise then we allocate enough
-	// storage to host them and then copy them in one at a time into the contiguous storage.
-	int numServices = m_serviceUUIDs.size();
-	if (numServices > 0) {
-		m_advData.service_uuid_len = 16 * numServices;
-		m_advData.p_service_uuid = new uint8_t[m_advData.service_uuid_len];
-		uint8_t* p = m_advData.p_service_uuid;
-		for (int i = 0; i < numServices; i++) {
-			log_d("- advertising service: %s", m_serviceUUIDs[i].toString().c_str());
-			BLEUUID serviceUUID128 = m_serviceUUIDs[i].to128();
-			memcpy(p, serviceUUID128.getNative()->uuid.uuid128, 16);
-			p += 16;
-		}
-	} else {
-		m_advData.service_uuid_len = 0;
-		log_d("- no services advertised");
-	}
-
-	esp_err_t errRc;
-
-	if (!m_customAdvData) {
-		// Set the configuration for advertising.
-		m_advData.set_scan_rsp = false;
-		m_advData.include_name = !m_scanResp;
-		m_advData.include_txpower = !m_scanResp;
-		errRc = ::esp_ble_gap_config_adv_data(&m_advData);
-		if (errRc != ESP_OK) {
-			log_e("<< esp_ble_gap_config_adv_data: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		}
-	}
-
-	if (!m_customScanResponseData && m_scanResp) {
-		// Set the configuration for scan response.
-		memcpy(&m_scanRespData, &m_advData, sizeof(esp_ble_adv_data_t)); // Copy the content of m_advData.
-		m_scanRespData.set_scan_rsp = true; // Define this struct as scan response data
-		m_scanRespData.include_name = true; // Caution: This may lead to a crash if the device name has more than 29 characters
-		m_scanRespData.include_txpower = true;
-		m_scanRespData.appearance = 0; // If defined the 'Appearance' attribute is already included in the advertising data
-		m_scanRespData.flag = 0; // 'Flags' attribute should no be included in the scan response
-
-		errRc = ::esp_ble_gap_config_adv_data(&m_scanRespData);
-		if (errRc != ESP_OK) {
-			log_e("<< esp_ble_gap_config_adv_data (Scan response): rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		}
-	}
-
-	// If we had services to advertise then we previously allocated some storage for them.
-	// Here we release that storage.
-	if (m_advData.service_uuid_len > 0) {
-		delete[] m_advData.p_service_uuid;
-		m_advData.p_service_uuid = nullptr;
-	}
-
-	// Start advertising.
-	errRc = ::esp_ble_gap_start_advertising(&m_advParams);
-	if (errRc != ESP_OK) {
-		log_e("<< esp_ble_gap_start_advertising: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
-	log_v("<< start");
-} // start
-
+bool BLEAdvertising::start() {
+  log_v(">> start: customAdvData: %d, customScanResponseData: %d", m_customAdvData, m_customScanResponseData);
+
+  // We have a vector of service UUIDs that we wish to advertise.  In order to use the
+  // ESP-IDF framework, these must be supplied in a contiguous array of their 128bit (16 byte)
+  // representations.  If we have 1 or more services to advertise then we allocate enough
+  // storage to host them and then copy them in one at a time into the contiguous storage.
+  int numServices = m_serviceUUIDs.size();
+  if (numServices > 0) {
+    m_advData.service_uuid_len = 16 * numServices;
+    m_advData.p_service_uuid = (uint8_t *)malloc(m_advData.service_uuid_len);
+    if (!m_advData.p_service_uuid) {
+      log_e(">> start failed: out of memory");
+      return false;
+    }
+
+    uint8_t *p = m_advData.p_service_uuid;
+    for (int i = 0; i < numServices; i++) {
+      log_d("- advertising service: %s", m_serviceUUIDs[i].toString().c_str());
+      BLEUUID serviceUUID128 = m_serviceUUIDs[i].to128();
+      memcpy(p, serviceUUID128.getNative()->uuid.uuid128, 16);
+      p += 16;
+    }
+  } else {
+    m_advData.service_uuid_len = 0;
+    log_d("- no services advertised");
+  }
+
+  esp_err_t errRc;
+
+  if (!m_customAdvData) {
+    // Set the configuration for advertising.
+    m_advData.set_scan_rsp = false;
+    m_advData.include_name = !m_scanResp;
+    m_advData.include_txpower = !m_scanResp;
+    errRc = ::esp_ble_gap_config_adv_data(&m_advData);
+    if (errRc != ESP_OK) {
+      log_e("<< esp_ble_gap_config_adv_data: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return false;
+    }
+  }
+
+  if (!m_customScanResponseData && m_scanResp) {
+    // Set the configuration for scan response.
+    memcpy(&m_scanRespData, &m_advData, sizeof(esp_ble_adv_data_t));  // Copy the content of m_advData.
+    m_scanRespData.set_scan_rsp = true;                               // Define this struct as scan response data
+    m_scanRespData.include_name = true;                               // Caution: This may lead to a crash if the device name has more than 29 characters
+    m_scanRespData.include_txpower = true;
+    m_scanRespData.appearance = 0;  // If defined the 'Appearance' attribute is already included in the advertising data
+    m_scanRespData.flag = 0;        // 'Flags' attribute should no be included in the scan response
+
+    errRc = ::esp_ble_gap_config_adv_data(&m_scanRespData);
+    if (errRc != ESP_OK) {
+      log_e("<< esp_ble_gap_config_adv_data (Scan response): rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return false;
+    }
+  }
+
+  // If we had services to advertise then we previously allocated some storage for them.
+  // Here we release that storage.
+  free(m_advData.p_service_uuid);  //TODO change this variable to local scope?
+  m_advData.p_service_uuid = nullptr;
+
+  // Start advertising.
+  errRc = ::esp_ble_gap_start_advertising(&m_advParams);
+  if (errRc != ESP_OK) {
+    log_e("<< esp_ble_gap_start_advertising: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+  } else {
+    log_v("<< start");
+  }
+  return ESP_OK == errRc;
+}  // start
 
 /**
  * @brief Stop advertising.
  * Stop advertising.
  * @return N/A.
  */
-void BLEAdvertising::stop() {
-	log_v(">> stop");
-	esp_err_t errRc = ::esp_ble_gap_stop_advertising();
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gap_stop_advertising: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
-	log_v("<< stop");
-} // stop
+bool BLEAdvertising::stop() {
+  log_v(">> stop");
+  esp_err_t errRc = ::esp_ble_gap_stop_advertising();
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gap_stop_advertising: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+  } else {
+    log_v("<< stop");
+  }
+  return ESP_OK == errRc;
+}  // stop
 
 /**
  * @brief Set BLE address.
@@ -270,32 +309,29 @@ void BLEAdvertising::stop() {
  * @param [in] Bluetooth address type.
  * Set BLE address.
  */
-
-void BLEAdvertising::setDeviceAddress(esp_bd_addr_t addr, esp_ble_addr_type_t type)
-{
-	log_v(">> setPrivateAddress");
-
-	m_advParams.own_addr_type = type;
-	esp_err_t errRc = esp_ble_gap_set_rand_addr((uint8_t*)addr);
-	if (errRc != ESP_OK)
-	{
-		log_e("esp_ble_gap_set_rand_addr: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
-	log_v("<< setPrivateAddress");
-} // setPrivateAddress
+bool BLEAdvertising::setDeviceAddress(esp_bd_addr_t addr, esp_ble_addr_type_t type) {
+  log_v(">> setPrivateAddress");
+
+  m_advParams.own_addr_type = type;
+  esp_err_t errRc = esp_ble_gap_set_rand_addr((uint8_t *)addr);
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gap_set_rand_addr: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+  } else {
+    log_v("<< setPrivateAddress");
+  }
+  return ESP_OK == errRc;
+}  // setPrivateAddress
 
 /**
  * @brief Add data to the payload to be advertised.
  * @param [in] data The data to be added to the payload.
  */
-void BLEAdvertisementData::addData(std::string data) {
-	if ((m_payload.length() + data.length()) > ESP_BLE_ADV_DATA_LEN_MAX) {
-		return;
-	}
-	m_payload.append(data);
-} // addData
-
+void BLEAdvertisementData::addData(String data) {
+  if ((m_payload.length() + data.length()) > ESP_BLE_ADV_DATA_LEN_MAX) {
+    return;
+  }
+  m_payload.concat(data);
+}  // addData
 
 /**
  * @brief Set the appearance.
@@ -305,49 +341,49 @@ void BLEAdvertisementData::addData(std::string data) {
  * https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.characteristic.gap.appearance.xml
  */
 void BLEAdvertisementData::setAppearance(uint16_t appearance) {
-	char cdata[2];
-	cdata[0] = 3;
-	cdata[1] = ESP_BLE_AD_TYPE_APPEARANCE; // 0x19
-	addData(std::string(cdata, 2) + std::string((char*) &appearance, 2));
-} // setAppearance
-
+  char cdata[2];
+  cdata[0] = 3;
+  cdata[1] = ESP_BLE_AD_TYPE_APPEARANCE;  // 0x19
+  addData(String(cdata, 2) + String((char *)&appearance, 2));
+}  // setAppearance
 
 /**
  * @brief Set the complete services.
  * @param [in] uuid The single service to advertise.
  */
 void BLEAdvertisementData::setCompleteServices(BLEUUID uuid) {
-	char cdata[2];
-	switch (uuid.bitSize()) {
-		case 16: {
-			// [Len] [0x02] [LL] [HH]
-			cdata[0] = 3;
-			cdata[1] = ESP_BLE_AD_TYPE_16SRV_CMPL;  // 0x03
-			addData(std::string(cdata, 2) + std::string((char*) &uuid.getNative()->uuid.uuid16, 2));
-			break;
-		}
-
-		case 32: {
-			// [Len] [0x04] [LL] [LL] [HH] [HH]
-			cdata[0] = 5;
-			cdata[1] = ESP_BLE_AD_TYPE_32SRV_CMPL;  // 0x05
-			addData(std::string(cdata, 2) + std::string((char*) &uuid.getNative()->uuid.uuid32, 4));
-			break;
-		}
-
-		case 128: {
-			// [Len] [0x04] [0] [1] ... [15]
-			cdata[0] = 17;
-			cdata[1] = ESP_BLE_AD_TYPE_128SRV_CMPL;  // 0x07
-			addData(std::string(cdata, 2) + std::string((char*) uuid.getNative()->uuid.uuid128, 16));
-			break;
-		}
-
-		default:
-			return;
-	}
-} // setCompleteServices
-
+  char cdata[2];
+  switch (uuid.bitSize()) {
+    case 16:
+    {
+      // [Len] [0x03] [LL] [HH]
+      cdata[0] = 3;
+      cdata[1] = ESP_BLE_AD_TYPE_16SRV_CMPL;  // 0x03
+      addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid16, 2));
+      break;
+    }
+
+    case 32:
+    {
+      // [Len] [0x05] [LL] [LL] [HH] [HH]
+      cdata[0] = 5;
+      cdata[1] = ESP_BLE_AD_TYPE_32SRV_CMPL;  // 0x05
+      addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid32, 4));
+      break;
+    }
+
+    case 128:
+    {
+      // [Len] [0x07] [0] [1] ... [15]
+      cdata[0] = 17;
+      cdata[1] = ESP_BLE_AD_TYPE_128SRV_CMPL;  // 0x07
+      addData(String(cdata, 2) + String((char *)uuid.getNative()->uuid.uuid128, 16));
+      break;
+    }
+
+    default: return;
+  }
+}  // setCompleteServices
 
 /**
  * @brief Set the advertisement flags.
@@ -361,168 +397,413 @@ void BLEAdvertisementData::setCompleteServices(BLEUUID uuid) {
  * * ESP_BLE_ADV_FLAG_NON_LIMIT_DISC
  */
 void BLEAdvertisementData::setFlags(uint8_t flag) {
-	char cdata[3];
-	cdata[0] = 2;
-	cdata[1] = ESP_BLE_AD_TYPE_FLAG;  // 0x01
-	cdata[2] = flag;
-	addData(std::string(cdata, 3));
-} // setFlag
-
-
+  char cdata[3];
+  cdata[0] = 2;
+  cdata[1] = ESP_BLE_AD_TYPE_FLAG;  // 0x01
+  cdata[2] = flag;
+  addData(String(cdata, 3));
+}  // setFlag
 
 /**
  * @brief Set manufacturer specific data.
  * @param [in] data Manufacturer data.
  */
-void BLEAdvertisementData::setManufacturerData(std::string data) {
-	log_d("BLEAdvertisementData", ">> setManufacturerData");
-	char cdata[2];
-	cdata[0] = data.length() + 1;
-	cdata[1] = ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE;  // 0xff
-	addData(std::string(cdata, 2) + data);
-	log_d("BLEAdvertisementData", "<< setManufacturerData");
-} // setManufacturerData
-
+void BLEAdvertisementData::setManufacturerData(String data) {
+  log_d("BLEAdvertisementData", ">> setManufacturerData");
+  char cdata[2];
+  cdata[0] = data.length() + 1;
+  cdata[1] = ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE;  // 0xff
+  addData(String(cdata, 2) + data);
+  log_d("BLEAdvertisementData", "<< setManufacturerData");
+}  // setManufacturerData
 
 /**
  * @brief Set the name.
  * @param [in] The complete name of the device.
  */
-void BLEAdvertisementData::setName(std::string name) {
-	log_d("BLEAdvertisementData", ">> setName: %s", name.c_str());
-	char cdata[2];
-	cdata[0] = name.length() + 1;
-	cdata[1] = ESP_BLE_AD_TYPE_NAME_CMPL;  // 0x09
-	addData(std::string(cdata, 2) + name);
-	log_d("BLEAdvertisementData", "<< setName");
-} // setName
-
+void BLEAdvertisementData::setName(String name) {
+  log_d("BLEAdvertisementData", ">> setName: %s", name.c_str());
+  char cdata[2];
+  cdata[0] = name.length() + 1;
+  cdata[1] = ESP_BLE_AD_TYPE_NAME_CMPL;  // 0x09
+  addData(String(cdata, 2) + name);
+  log_d("BLEAdvertisementData", "<< setName");
+}  // setName
 
 /**
  * @brief Set the partial services.
  * @param [in] uuid The single service to advertise.
  */
 void BLEAdvertisementData::setPartialServices(BLEUUID uuid) {
-	char cdata[2];
-	switch (uuid.bitSize()) {
-		case 16: {
-			// [Len] [0x02] [LL] [HH]
-			cdata[0] = 3;
-			cdata[1] = ESP_BLE_AD_TYPE_16SRV_PART;  // 0x02
-			addData(std::string(cdata, 2) + std::string((char *) &uuid.getNative()->uuid.uuid16, 2));
-			break;
-		}
-
-		case 32: {
-			// [Len] [0x04] [LL] [LL] [HH] [HH]
-			cdata[0] = 5;
-			cdata[1] = ESP_BLE_AD_TYPE_32SRV_PART; // 0x04
-			addData(std::string(cdata, 2) + std::string((char *) &uuid.getNative()->uuid.uuid32, 4));
-			break;
-		}
-
-		case 128: {
-			// [Len] [0x04] [0] [1] ... [15]
-			cdata[0] = 17;
-			cdata[1] = ESP_BLE_AD_TYPE_128SRV_PART;  // 0x06
-			addData(std::string(cdata, 2) + std::string((char *) &uuid.getNative()->uuid.uuid128, 16));
-			break;
-		}
-
-		default:
-			return;
-	}
-} // setPartialServices
-
+  char cdata[2];
+  switch (uuid.bitSize()) {
+    case 16:
+    {
+      // [Len] [0x02] [LL] [HH]
+      cdata[0] = 3;
+      cdata[1] = ESP_BLE_AD_TYPE_16SRV_PART;  // 0x02
+      addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid16, 2));
+      break;
+    }
+
+    case 32:
+    {
+      // [Len] [0x04] [LL] [LL] [HH] [HH]
+      cdata[0] = 5;
+      cdata[1] = ESP_BLE_AD_TYPE_32SRV_PART;  // 0x04
+      addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid32, 4));
+      break;
+    }
+
+    case 128:
+    {
+      // [Len] [0x06] [0] [1] ... [15]
+      cdata[0] = 17;
+      cdata[1] = ESP_BLE_AD_TYPE_128SRV_PART;  // 0x06
+      addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid128, 16));
+      break;
+    }
+
+    default: return;
+  }
+}  // setPartialServices
 
 /**
  * @brief Set the service data (UUID + data)
  * @param [in] uuid The UUID to set with the service data.  Size of UUID will be used.
  * @param [in] data The data to be associated with the service data advert.
  */
-void BLEAdvertisementData::setServiceData(BLEUUID uuid, std::string data) {
-	char cdata[2];
-	switch (uuid.bitSize()) {
-		case 16: {
-			// [Len] [0x16] [UUID16] data
-			cdata[0] = data.length() + 3;
-			cdata[1] = ESP_BLE_AD_TYPE_SERVICE_DATA;  // 0x16
-			addData(std::string(cdata, 2) + std::string((char*) &uuid.getNative()->uuid.uuid16, 2) + data);
-			break;
-		}
-
-		case 32: {
-			// [Len] [0x20] [UUID32] data
-			cdata[0] = data.length() + 5;
-			cdata[1] = ESP_BLE_AD_TYPE_32SERVICE_DATA; // 0x20
-			addData(std::string(cdata, 2) + std::string((char*) &uuid.getNative()->uuid.uuid32, 4) + data);
-			break;
-		}
-
-		case 128: {
-			// [Len] [0x21] [UUID128] data
-			cdata[0] = data.length() + 17;
-			cdata[1] = ESP_BLE_AD_TYPE_128SERVICE_DATA;  // 0x21
-			addData(std::string(cdata, 2) + std::string((char*) &uuid.getNative()->uuid.uuid128, 16) + data);
-			break;
-		}
-
-		default:
-			return;
-	}
-} // setServiceData
-
+void BLEAdvertisementData::setServiceData(BLEUUID uuid, String data) {
+  char cdata[2];
+  switch (uuid.bitSize()) {
+    case 16:
+    {
+      // [Len] [0x16] [UUID16] data
+      cdata[0] = data.length() + 3;
+      cdata[1] = ESP_BLE_AD_TYPE_SERVICE_DATA;  // 0x16
+      addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid16, 2) + data);
+      break;
+    }
+
+    case 32:
+    {
+      // [Len] [0x20] [UUID32] data
+      cdata[0] = data.length() + 5;
+      cdata[1] = ESP_BLE_AD_TYPE_32SERVICE_DATA;  // 0x20
+      addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid32, 4) + data);
+      break;
+    }
+
+    case 128:
+    {
+      // [Len] [0x21] [UUID128] data
+      cdata[0] = data.length() + 17;
+      cdata[1] = ESP_BLE_AD_TYPE_128SERVICE_DATA;  // 0x21
+      addData(String(cdata, 2) + String((char *)&uuid.getNative()->uuid.uuid128, 16) + data);
+      break;
+    }
+
+    default: return;
+  }
+}  // setServiceData
 
 /**
  * @brief Set the short name.
  * @param [in] The short name of the device.
  */
-void BLEAdvertisementData::setShortName(std::string name) {
-	log_d("BLEAdvertisementData", ">> setShortName: %s", name.c_str());
-	char cdata[2];
-	cdata[0] = name.length() + 1;
-	cdata[1] = ESP_BLE_AD_TYPE_NAME_SHORT;  // 0x08
-	addData(std::string(cdata, 2) + name);
-	log_d("BLEAdvertisementData", "<< setShortName");
-} // setShortName
-
+void BLEAdvertisementData::setShortName(String name) {
+  log_d("BLEAdvertisementData", ">> setShortName: %s", name.c_str());
+  char cdata[2];
+  cdata[0] = name.length() + 1;
+  cdata[1] = ESP_BLE_AD_TYPE_NAME_SHORT;  // 0x08
+  addData(String(cdata, 2) + name);
+  log_d("BLEAdvertisementData", "<< setShortName");
+}  // setShortName
 
 /**
  * @brief Retrieve the payload that is to be advertised.
  * @return The payload that is to be advertised.
  */
-std::string BLEAdvertisementData::getPayload() {
-	return m_payload;
-} // getPayload
-
-void BLEAdvertising::handleGAPEvent(
-		esp_gap_ble_cb_event_t  event,
-		esp_ble_gap_cb_param_t* param)  {
-
-	log_d("handleGAPEvent [event no: %d]", (int)event);
-
-	switch(event) {
-		case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT: {
-			// m_semaphoreSetAdv.give();
-			break;
-		}
-		case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT: {
-			// m_semaphoreSetAdv.give();
-			break;
-		}
-		case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: {
-			// m_semaphoreSetAdv.give();
-			break;
-		}
-		case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT: {
-			log_i("STOP advertising");
-			//start();
-			break;
-		}
-		default:
-			break;
-	}
+String BLEAdvertisementData::getPayload() {
+  return m_payload;
+}  // getPayload
+
+void BLEAdvertising::handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) {
+
+  log_d("handleGAPEvent [event no: %d]", (int)event);
+
+  switch (event) {
+    case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT:
+    {
+      // m_semaphoreSetAdv.give();
+      break;
+    }
+    case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT:
+    {
+      // m_semaphoreSetAdv.give();
+      break;
+    }
+    case ESP_GAP_BLE_ADV_START_COMPLETE_EVT:
+    {
+      // m_semaphoreSetAdv.give();
+      break;
+    }
+    case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT:
+    {
+      log_i("STOP advertising");
+      //start();
+      break;
+    }
+    default: break;
+  }
+}
+
+#ifdef SOC_BLE_50_SUPPORTED
+
+/**
+* @brief           Creator
+*
+* @param[in]       instance : number of multi advertising instances
+*
+*
+*/
+BLEMultiAdvertising::BLEMultiAdvertising(uint8_t num) {
+  params_arrays = (esp_ble_gap_ext_adv_params_t *)calloc(num, sizeof(esp_ble_gap_ext_adv_params_t));
+  ext_adv = (esp_ble_gap_ext_adv_t *)calloc(num, sizeof(esp_ble_gap_ext_adv_t));
+  count = num;
+}
+
+/**
+* @brief           This function is used by the Host to set the advertising parameters.
+*
+* @param[in]       instance : identifies the advertising set whose parameters are being configured.
+* @param[in]       params   : advertising parameters
+*
+* @return            - true : success
+*                    - false  : failed
+*
+*/
+bool BLEMultiAdvertising::setAdvertisingParams(uint8_t instance, const esp_ble_gap_ext_adv_params_t *params) {
+  if (params->type == ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_IND && params->primary_phy == ESP_BLE_GAP_PHY_2M) {
+    return false;
+  }
+  esp_err_t rc;
+  rc = esp_ble_gap_ext_adv_set_params(instance, params);
+
+  return ESP_OK == rc;
+}
+
+/**
+* @brief           This function is used to set the data used in advertising PDUs that have a data field
+*
+* @param[in]       instance : identifies the advertising set whose data are being configured
+* @param[in]       length   : data length
+* @param[in]       data     : data information
+*
+* @return            - true : success
+*                    - false  : failed
+*
+*/
+bool BLEMultiAdvertising::setAdvertisingData(uint8_t instance, uint16_t length, const uint8_t *data) {
+  esp_err_t rc;
+  rc = esp_ble_gap_config_ext_adv_data_raw(instance, length, data);
+  if (rc) {
+    log_e("set advertising data err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+bool BLEMultiAdvertising::setScanRspData(uint8_t instance, uint16_t length, const uint8_t *data) {
+  esp_err_t rc;
+  rc = esp_ble_gap_config_ext_scan_rsp_data_raw(instance, length, data);
+  if (rc) {
+    log_e("set scan resp data err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+/**
+* @brief           This function is used to request the Controller to enable one or more
+*                  advertising sets using the advertising sets identified by the instance parameter.
+*
+* @return            - true : success
+*                    - false  : failed
+*
+*/
+bool BLEMultiAdvertising::start() {
+  return start(count, 0);
+}
+
+/**
+* @brief           This function is used to request the Controller to enable one or more
+*                  advertising sets using the advertising sets identified by the instance parameter.
+*
+* @param[in]       num : Number of advertising sets to enable or disable
+* @param[in]       from : first sxt adv set to use
+*
+* @return            - true : success
+*                    - false  : failed
+*
+*/
+bool BLEMultiAdvertising::start(uint8_t num, uint8_t from) {
+  if (num > count || from >= count) {
+    return false;
+  }
+
+  esp_err_t rc;
+  rc = esp_ble_gap_ext_adv_start(num, &ext_adv[from]);
+  if (rc) {
+    log_e("start extended advertising err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+/**
+* @brief           This function is used to request the Controller to disable one or more
+*                  advertising sets using the advertising sets identified by the instance parameter.
+*
+* @param[in]       num_adv : Number of advertising sets to enable or disable
+* @param[in]       ext_adv_inst : ext adv instance
+*
+* @return            - ESP_OK : success
+*                    - other  : failed
+*
+*/
+bool BLEMultiAdvertising::stop(uint8_t num_adv, const uint8_t *ext_adv_inst) {
+  esp_err_t rc;
+  rc = esp_ble_gap_ext_adv_stop(num_adv, ext_adv_inst);
+  if (rc) {
+    log_e("stop extended advertising err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+/**
+* @brief           This function is used to remove an advertising set from the Controller.
+*
+* @param[in]       instance : Used to identify an advertising set
+*
+* @return            - ESP_OK : success
+*                    - other  : failed
+*
+*/
+bool BLEMultiAdvertising::remove(uint8_t instance) {
+  esp_err_t rc;
+  rc = esp_ble_gap_ext_adv_set_remove(instance);
+  if (rc) {
+    log_e("remove extended advertising err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+/**
+* @brief           This function is used to remove all existing advertising sets from the Controller.
+*
+*
+* @return            - ESP_OK : success
+*                    - other  : failed
+*
+*/
+bool BLEMultiAdvertising::clear() {
+  esp_err_t rc;
+  rc = esp_ble_gap_ext_adv_set_clear();
+  if (rc) {
+    log_e("clear extended advertising err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+/**
+* @brief           This function is used by the Host to set the random device address specified by the Random_Address parameter.
+*
+* @param[in]       instance  : Used to identify an advertising set
+* @param[in]       addr_legacy : Random Device Address
+*
+* @return            - true : success
+*                    - false  : failed
+*
+*/
+bool BLEMultiAdvertising::setInstanceAddress(uint8_t instance, uint8_t *addr_legacy) {
+  esp_err_t rc;
+  rc = esp_ble_gap_ext_adv_set_rand_addr(instance, addr_legacy);
+  if (rc) {
+    log_e("set random address err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+/**
+* @brief           This function is used by the Host to set the parameters for periodic advertising.
+*
+* @param[in]       instance : identifies the advertising set whose periodic advertising parameters are being configured.
+* @param[in]       params : periodic adv parameters
+*
+* @return            - true : success
+*                    - false  : failed
+*
+*/
+bool BLEMultiAdvertising::setPeriodicAdvertisingParams(uint8_t instance, const esp_ble_gap_periodic_adv_params_t *params) {
+  esp_err_t rc;
+  rc = esp_ble_gap_periodic_adv_set_params(instance, params);
+  if (rc) {
+    log_e("set periodic advertising params err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+/**
+* @brief           This function is used to set the data used in periodic advertising PDUs.
+*
+* @param[in]       instance : identifies the advertising set whose periodic advertising parameters are being configured.
+* @param[in]       length : the length of periodic data
+* @param[in]       data : periodic data information
+*
+* @return            - true : success
+*                    - false  : failed
+*
+*/
+bool BLEMultiAdvertising::setPeriodicAdvertisingData(uint8_t instance, uint16_t length, const uint8_t *data) {
+  esp_err_t rc;
+  rc = esp_ble_gap_config_periodic_adv_data_raw(instance, length, data);
+  if (rc) {
+    log_e("set periodic advertising raw data err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+/**
+* @brief           This function is used to request the Controller to enable the periodic advertising for the advertising set specified
+*
+* @param[in]       instance : Used to identify an advertising set
+*
+* @return            - true : success
+*                    - false  : failed
+*
+*/
+bool BLEMultiAdvertising::startPeriodicAdvertising(uint8_t instance) {
+  esp_err_t rc;
+  rc = esp_ble_gap_periodic_adv_start(instance);
+  if (rc) {
+    log_e("start periodic advertising err: %d", rc);
+  }
+
+  return ESP_OK == rc;
+}
+
+void BLEMultiAdvertising::setDuration(uint8_t instance, int duration, int max_events) {
+  ext_adv[instance] = {instance, duration, max_events};
 }
 
+#endif  // SOC_BLE_50_SUPPORTED
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEAdvertising.h b/libraries/BLE/src/BLEAdvertising.h
index f1f0c66498f..1e573ac814f 100644
--- a/libraries/BLE/src/BLEAdvertising.h
+++ b/libraries/BLE/src/BLEAdvertising.h
@@ -7,37 +7,39 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEADVERTISING_H_
 #define COMPONENTS_CPP_UTILS_BLEADVERTISING_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <esp_gap_ble_api.h>
 #include "BLEUUID.h"
 #include <vector>
-#include "FreeRTOS.h"
+#include "RTOS.h"
 
 /**
  * @brief Advertisement data set by the programmer to be published by the %BLE server.
  */
 class BLEAdvertisementData {
-	// Only a subset of the possible BLE architected advertisement fields are currently exposed.  Others will
-	// be exposed on demand/request or as time permits.
-	//
+  // Only a subset of the possible BLE architected advertisement fields are currently exposed.  Others will
+  // be exposed on demand/request or as time permits.
+  //
 public:
-	void setAppearance(uint16_t appearance);
-	void setCompleteServices(BLEUUID uuid);
-	void setFlags(uint8_t);
-	void setManufacturerData(std::string data);
-	void setName(std::string name);
-	void setPartialServices(BLEUUID uuid);
-	void setServiceData(BLEUUID uuid, std::string data);
-	void setShortName(std::string name);
-	void addData(std::string data);         // Add data to the payload.
-	std::string getPayload();               // Retrieve the current advert payload.
+  void setAppearance(uint16_t appearance);
+  void setCompleteServices(BLEUUID uuid);
+  void setFlags(uint8_t);
+  void setManufacturerData(String data);
+  void setName(String name);
+  void setPartialServices(BLEUUID uuid);
+  void setServiceData(BLEUUID uuid, String data);
+  void setShortName(String name);
+  void addData(String data);  // Add data to the payload.
+  String getPayload();        // Retrieve the current advert payload.
 
 private:
-	friend class BLEAdvertising;
-	std::string m_payload;   // The payload of the advertisement.
-};   // BLEAdvertisementData
-
+  friend class BLEAdvertising;
+  String m_payload;  // The payload of the advertisement.
+};  // BLEAdvertisementData
 
 /**
  * @brief Perform and manage %BLE advertising.
@@ -46,36 +48,70 @@ class BLEAdvertisementData {
  */
 class BLEAdvertising {
 public:
-	BLEAdvertising();
-	void addServiceUUID(BLEUUID serviceUUID);
-	void addServiceUUID(const char* serviceUUID);
-	void start();
-	void stop();
-	void setAppearance(uint16_t appearance);
-	void setAdvertisementType(esp_ble_adv_type_t adv_type);
-	void setMaxInterval(uint16_t maxinterval);
-	void setMinInterval(uint16_t mininterval);
-	void setAdvertisementData(BLEAdvertisementData& advertisementData);
-	void setScanFilter(bool scanRequertWhitelistOnly, bool connectWhitelistOnly);
-	void setScanResponseData(BLEAdvertisementData& advertisementData);
-	void setPrivateAddress(esp_ble_addr_type_t type = BLE_ADDR_TYPE_RANDOM);
-	void setDeviceAddress(esp_bd_addr_t addr, esp_ble_addr_type_t type = BLE_ADDR_TYPE_RANDOM);
+  BLEAdvertising();
+  void addServiceUUID(BLEUUID serviceUUID);
+  void addServiceUUID(const char *serviceUUID);
+  bool removeServiceUUID(int index);
+  bool removeServiceUUID(BLEUUID serviceUUID);
+  bool removeServiceUUID(const char *serviceUUID);
+  bool start();
+  bool stop();
+  void setAppearance(uint16_t appearance);
+  void setAdvertisementType(esp_ble_adv_type_t adv_type);
+  void setAdvertisementChannelMap(esp_ble_adv_channel_t channel_map);
+  void setMaxInterval(uint16_t maxinterval);
+  void setMinInterval(uint16_t mininterval);
+  bool setAdvertisementData(BLEAdvertisementData &advertisementData);
+  void setScanFilter(bool scanRequestWhitelistOnly, bool connectWhitelistOnly);
+  bool setScanResponseData(BLEAdvertisementData &advertisementData);
+  void setPrivateAddress(esp_ble_addr_type_t type = BLE_ADDR_TYPE_RANDOM);
+  bool setDeviceAddress(esp_bd_addr_t addr, esp_ble_addr_type_t type = BLE_ADDR_TYPE_RANDOM);
+
+  void handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param);
+  void setMinPreferred(uint16_t);
+  void setMaxPreferred(uint16_t);
+  void setScanResponse(bool);
+
+private:
+  esp_ble_adv_data_t m_advData;
+  esp_ble_adv_data_t m_scanRespData;  // Used for configuration of scan response data when m_scanResp is true
+  esp_ble_adv_params_t m_advParams;
+  std::vector<BLEUUID> m_serviceUUIDs;
+  bool m_customAdvData = false;           // Are we using custom advertising data?
+  bool m_customScanResponseData = false;  // Are we using custom scan response data?
+  FreeRTOS::Semaphore m_semaphoreSetAdv = FreeRTOS::Semaphore("startAdvert");
+  bool m_scanResp = true;
+};
 
-	void handleGAPEvent(esp_gap_ble_cb_event_t  event, esp_ble_gap_cb_param_t* param);
-	void setMinPreferred(uint16_t);
-	void setMaxPreferred(uint16_t);
-	void setScanResponse(bool);
+#ifdef SOC_BLE_50_SUPPORTED
 
+class BLEMultiAdvertising {
 private:
-	esp_ble_adv_data_t   m_advData;
-	esp_ble_adv_data_t   m_scanRespData; // Used for configuration of scan response data when m_scanResp is true
-	esp_ble_adv_params_t m_advParams;
-	std::vector<BLEUUID> m_serviceUUIDs;
-	bool                 m_customAdvData = false;  // Are we using custom advertising data?
-	bool                 m_customScanResponseData = false;  // Are we using custom scan response data?
-	FreeRTOS::Semaphore  m_semaphoreSetAdv = FreeRTOS::Semaphore("startAdvert");
-	bool                 m_scanResp = true;
+  esp_ble_gap_ext_adv_params_t *params_arrays;
+  esp_ble_gap_ext_adv_t *ext_adv;
+  uint8_t count;
+
+public:
+  BLEMultiAdvertising(uint8_t num = 1);
+  ~BLEMultiAdvertising() {}
 
+  bool setAdvertisingParams(uint8_t instance, const esp_ble_gap_ext_adv_params_t *params);
+  bool setAdvertisingData(uint8_t instance, uint16_t length, const uint8_t *data);
+  bool setScanRspData(uint8_t instance, uint16_t length, const uint8_t *data);
+  bool start();
+  bool start(uint8_t num, uint8_t from);
+  void setDuration(uint8_t instance, int duration = 0, int max_events = 0);
+  bool setInstanceAddress(uint8_t instance, esp_bd_addr_t rand_addr);
+  bool stop(uint8_t num_adv, const uint8_t *ext_adv_inst);
+  bool remove(uint8_t instance);
+  bool clear();
+  bool setPeriodicAdvertisingParams(uint8_t instance, const esp_ble_gap_periodic_adv_params_t *params);
+  bool setPeriodicAdvertisingData(uint8_t instance, uint16_t length, const uint8_t *data);
+  bool startPeriodicAdvertising(uint8_t instance);
 };
-#endif /* CONFIG_BT_ENABLED */
+
+#endif  // SOC_BLE_50_SUPPORTED
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEADVERTISING_H_ */
diff --git a/libraries/BLE/src/BLEBeacon.cpp b/libraries/BLE/src/BLEBeacon.cpp
index 1056cd54b04..43366a7b2d9 100644
--- a/libraries/BLE/src/BLEBeacon.cpp
+++ b/libraries/BLE/src/BLEBeacon.cpp
@@ -4,80 +4,81 @@
  *  Created on: Jan 4, 2018
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
-#include <string.h>
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include "BLEBeacon.h"
 #include "esp32-hal-log.h"
 
-#define ENDIAN_CHANGE_U16(x) ((((x)&0xFF00)>>8) + (((x)&0xFF)<<8))
-
+#define ENDIAN_CHANGE_U16(x) ((((x) & 0xFF00) >> 8) + (((x) & 0xFF) << 8))
 
 BLEBeacon::BLEBeacon() {
-	m_beaconData.manufacturerId = 0x4c00;
-	m_beaconData.subType        = 0x02;
-	m_beaconData.subTypeLength  = 0x15;
-	m_beaconData.major          = 0;
-	m_beaconData.minor          = 0;
-	m_beaconData.signalPower    = 0;
-	memset(m_beaconData.proximityUUID, 0, sizeof(m_beaconData.proximityUUID));
-} // BLEBeacon
-
-std::string BLEBeacon::getData() {
-	return std::string((char*) &m_beaconData, sizeof(m_beaconData));
-} // getData
+  m_beaconData.manufacturerId = 0x4c00;
+  m_beaconData.subType = 0x02;
+  m_beaconData.subTypeLength = 0x15;
+  m_beaconData.major = 0;
+  m_beaconData.minor = 0;
+  m_beaconData.signalPower = 0;
+  memset(m_beaconData.proximityUUID, 0, sizeof(m_beaconData.proximityUUID));
+}  // BLEBeacon
+
+String BLEBeacon::getData() {
+  return String((char *)&m_beaconData, sizeof(m_beaconData));
+}  // getData
 
 uint16_t BLEBeacon::getMajor() {
-	return m_beaconData.major;
+  return m_beaconData.major;
 }
 
 uint16_t BLEBeacon::getManufacturerId() {
-	return m_beaconData.manufacturerId;
+  return m_beaconData.manufacturerId;
 }
 
 uint16_t BLEBeacon::getMinor() {
-	return m_beaconData.minor;
+  return m_beaconData.minor;
 }
 
 BLEUUID BLEBeacon::getProximityUUID() {
-	return BLEUUID(m_beaconData.proximityUUID, 16, false);
+  return BLEUUID(m_beaconData.proximityUUID, 16, true);
 }
 
 int8_t BLEBeacon::getSignalPower() {
-	return m_beaconData.signalPower;
+  return m_beaconData.signalPower;
 }
 
 /**
  * Set the raw data for the beacon record.
  */
-void BLEBeacon::setData(std::string data) {
-	if (data.length() != sizeof(m_beaconData)) {
-		log_e("Unable to set the data ... length passed in was %d and expected %d", data.length(), sizeof(m_beaconData));
-		return;
-	}
-	memcpy(&m_beaconData, data.data(), sizeof(m_beaconData));
-} // setData
+void BLEBeacon::setData(String data) {
+  if (data.length() != sizeof(m_beaconData)) {
+    log_e("Unable to set the data ... length passed in was %d and expected %d", data.length(), sizeof(m_beaconData));
+    return;
+  }
+  memcpy(&m_beaconData, data.c_str(), sizeof(m_beaconData));
+}  // setData
 
 void BLEBeacon::setMajor(uint16_t major) {
-	m_beaconData.major = ENDIAN_CHANGE_U16(major);
-} // setMajor
+  m_beaconData.major = ENDIAN_CHANGE_U16(major);
+}  // setMajor
 
 void BLEBeacon::setManufacturerId(uint16_t manufacturerId) {
-	m_beaconData.manufacturerId = ENDIAN_CHANGE_U16(manufacturerId);
-} // setManufacturerId
+  m_beaconData.manufacturerId = ENDIAN_CHANGE_U16(manufacturerId);
+}  // setManufacturerId
 
 void BLEBeacon::setMinor(uint16_t minor) {
-	m_beaconData.minor = ENDIAN_CHANGE_U16(minor);
-} // setMinior
+  m_beaconData.minor = ENDIAN_CHANGE_U16(minor);
+}  // setMinior
 
 void BLEBeacon::setProximityUUID(BLEUUID uuid) {
-	uuid = uuid.to128();
-	memcpy(m_beaconData.proximityUUID, uuid.getNative()->uuid.uuid128, 16);
-} // setProximityUUID
+  uuid = uuid.to128();
+  memcpy(m_beaconData.proximityUUID, uuid.getNative()->uuid.uuid128, 16);
+}  // setProximityUUID
 
 void BLEBeacon::setSignalPower(int8_t signalPower) {
-	m_beaconData.signalPower = signalPower;
-} // setSignalPower
-
+  m_beaconData.signalPower = signalPower;
+}  // setSignalPower
 
 #endif
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEBeacon.h b/libraries/BLE/src/BLEBeacon.h
index 277bd670776..dcc41aafeb4 100644
--- a/libraries/BLE/src/BLEBeacon.h
+++ b/libraries/BLE/src/BLEBeacon.h
@@ -7,6 +7,9 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEBEACON_H_
 #define COMPONENTS_CPP_UTILS_BLEBEACON_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "BLEUUID.h"
 /**
  * @brief Representation of a beacon.
@@ -15,29 +18,31 @@
  */
 class BLEBeacon {
 private:
-	struct {
-		uint16_t manufacturerId;
-		uint8_t  subType;
-		uint8_t  subTypeLength;
-		uint8_t  proximityUUID[16];
-		uint16_t major;
-		uint16_t minor;
-		int8_t   signalPower;
-	} __attribute__((packed)) m_beaconData;
+  struct {
+    uint16_t manufacturerId;
+    uint8_t subType;
+    uint8_t subTypeLength;
+    uint8_t proximityUUID[16];
+    uint16_t major;
+    uint16_t minor;
+    int8_t signalPower;
+  } __attribute__((packed)) m_beaconData;
+
 public:
-	BLEBeacon();
-	std::string getData();
-	uint16_t    getMajor();
-	uint16_t    getMinor();
-	uint16_t    getManufacturerId();
-	BLEUUID     getProximityUUID();
-	int8_t      getSignalPower();
-	void        setData(std::string data);
-	void        setMajor(uint16_t major);
-	void        setMinor(uint16_t minor);
-	void        setManufacturerId(uint16_t manufacturerId);
-	void        setProximityUUID(BLEUUID uuid);
-	void        setSignalPower(int8_t signalPower);
-}; // BLEBeacon
+  BLEBeacon();
+  String getData();
+  uint16_t getMajor();
+  uint16_t getMinor();
+  uint16_t getManufacturerId();
+  BLEUUID getProximityUUID();
+  int8_t getSignalPower();
+  void setData(String data);
+  void setMajor(uint16_t major);
+  void setMinor(uint16_t minor);
+  void setManufacturerId(uint16_t manufacturerId);
+  void setProximityUUID(BLEUUID uuid);
+  void setSignalPower(int8_t signalPower);
+};  // BLEBeacon
 
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEBEACON_H_ */
diff --git a/libraries/BLE/src/BLECharacteristic.cpp b/libraries/BLE/src/BLECharacteristic.cpp
index 7daaa32a51d..b03d524a6a5 100644
--- a/libraries/BLE/src/BLECharacteristic.cpp
+++ b/libraries/BLE/src/BLECharacteristic.cpp
@@ -4,8 +4,11 @@
  *  Created on: Jun 22, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <sstream>
 #include <string.h>
 #include <iomanip>
@@ -22,15 +25,14 @@
 
 #define NULL_HANDLE (0xffff)
 
-static BLECharacteristicCallbacks defaultCallback; //null-object-pattern
+static BLECharacteristicCallbacks defaultCallback;  //null-object-pattern
 
 /**
  * @brief Construct a characteristic
  * @param [in] uuid - UUID (const char*) for the characteristic.
  * @param [in] properties - Properties for the characteristic.
  */
-BLECharacteristic::BLECharacteristic(const char* uuid, uint32_t properties) : BLECharacteristic(BLEUUID(uuid), properties) {
-}
+BLECharacteristic::BLECharacteristic(const char *uuid, uint32_t properties) : BLECharacteristic(BLEUUID(uuid), properties) {}
 
 /**
  * @brief Construct a characteristic
@@ -38,424 +40,417 @@ BLECharacteristic::BLECharacteristic(const char* uuid, uint32_t properties) : BL
  * @param [in] properties - Properties for the characteristic.
  */
 BLECharacteristic::BLECharacteristic(BLEUUID uuid, uint32_t properties) {
-	m_bleUUID    = uuid;
-	m_handle     = NULL_HANDLE;
-	m_properties = (esp_gatt_char_prop_t)0;
-	m_pCallbacks = &defaultCallback;
-
-	setBroadcastProperty((properties & PROPERTY_BROADCAST) != 0);
-	setReadProperty((properties & PROPERTY_READ) != 0);
-	setWriteProperty((properties & PROPERTY_WRITE) != 0);
-	setNotifyProperty((properties & PROPERTY_NOTIFY) != 0);
-	setIndicateProperty((properties & PROPERTY_INDICATE) != 0);
-	setWriteNoResponseProperty((properties & PROPERTY_WRITE_NR) != 0);
-} // BLECharacteristic
+  m_bleUUID = uuid;
+  m_handle = NULL_HANDLE;
+  m_properties = (esp_gatt_char_prop_t)0;
+  m_pCallbacks = &defaultCallback;
+
+  setBroadcastProperty((properties & PROPERTY_BROADCAST) != 0);
+  setReadProperty((properties & PROPERTY_READ) != 0);
+  setWriteProperty((properties & PROPERTY_WRITE) != 0);
+  setNotifyProperty((properties & PROPERTY_NOTIFY) != 0);
+  setIndicateProperty((properties & PROPERTY_INDICATE) != 0);
+  setWriteNoResponseProperty((properties & PROPERTY_WRITE_NR) != 0);
+}  // BLECharacteristic
 
 /**
  * @brief Destructor.
  */
 BLECharacteristic::~BLECharacteristic() {
-	//free(m_value.attr_value); // Release the storage for the value.
-} // ~BLECharacteristic
-
+  //free(m_value.attr_value); // Release the storage for the value.
+}  // ~BLECharacteristic
 
 /**
  * @brief Associate a descriptor with this characteristic.
  * @param [in] pDescriptor
  * @return N/A.
  */
-void BLECharacteristic::addDescriptor(BLEDescriptor* pDescriptor) {
-	log_v(">> addDescriptor(): Adding %s to %s", pDescriptor->toString().c_str(), toString().c_str());
-	m_descriptorMap.setByUUID(pDescriptor->getUUID(), pDescriptor);
-	log_v("<< addDescriptor()");
-} // addDescriptor
-
+void BLECharacteristic::addDescriptor(BLEDescriptor *pDescriptor) {
+  log_v(">> addDescriptor(): Adding %s to %s", pDescriptor->toString().c_str(), toString().c_str());
+  m_descriptorMap.setByUUID(pDescriptor->getUUID(), pDescriptor);
+  log_v("<< addDescriptor()");
+}  // addDescriptor
 
 /**
  * @brief Register a new characteristic with the ESP runtime.
  * @param [in] pService The service with which to associate this characteristic.
  */
-void BLECharacteristic::executeCreate(BLEService* pService) {
-	log_v(">> executeCreate()");
-
-	if (m_handle != NULL_HANDLE) {
-		log_e("Characteristic already has a handle.");
-		return;
-	}
+void BLECharacteristic::executeCreate(BLEService *pService) {
+  log_v(">> executeCreate()");
 
-	m_pService = pService; // Save the service to which this characteristic belongs.
+  if (m_handle != NULL_HANDLE) {
+    log_e("Characteristic already has a handle.");
+    return;
+  }
 
-	log_d("Registering characteristic (esp_ble_gatts_add_char): uuid: %s, service: %s",
-		getUUID().toString().c_str(),
-		m_pService->toString().c_str());
+  m_pService = pService;  // Save the service to which this characteristic belongs.
 
-	esp_attr_control_t control;
-	control.auto_rsp = ESP_GATT_RSP_BY_APP;
+  log_d("Registering characteristic (esp_ble_gatts_add_char): uuid: %s, service: %s", getUUID().toString().c_str(), m_pService->toString().c_str());
 
-	m_semaphoreCreateEvt.take("executeCreate");
-	esp_err_t errRc = ::esp_ble_gatts_add_char(
-		m_pService->getHandle(),
-		getUUID().getNative(),
-		static_cast<esp_gatt_perm_t>(m_permissions),
-		getProperties(),
-		nullptr,
-		&control); // Whether to auto respond or not.
+  esp_attr_control_t control;
+  control.auto_rsp = ESP_GATT_RSP_BY_APP;
 
-	if (errRc != ESP_OK) {
-		log_e("<< esp_ble_gatts_add_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
-	m_semaphoreCreateEvt.wait("executeCreate");
+  m_semaphoreCreateEvt.take("executeCreate");
+  esp_err_t errRc = ::esp_ble_gatts_add_char(
+    m_pService->getHandle(), getUUID().getNative(), static_cast<esp_gatt_perm_t>(m_permissions), getProperties(), nullptr,
+    &control
+  );  // Whether to auto respond or not.
 
-	BLEDescriptor* pDescriptor = m_descriptorMap.getFirst();
-	while (pDescriptor != nullptr) {
-		pDescriptor->executeCreate(this);
-		pDescriptor = m_descriptorMap.getNext();
-	} // End while
+  if (errRc != ESP_OK) {
+    log_e("<< esp_ble_gatts_add_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return;
+  }
+  m_semaphoreCreateEvt.wait("executeCreate");
 
-	log_v("<< executeCreate");
-} // executeCreate
+  BLEDescriptor *pDescriptor = m_descriptorMap.getFirst();
+  while (pDescriptor != nullptr) {
+    pDescriptor->executeCreate(this);
+    pDescriptor = m_descriptorMap.getNext();
+  }  // End while
 
+  log_v("<< executeCreate");
+}  // executeCreate
 
 /**
  * @brief Return the BLE Descriptor for the given UUID if associated with this characteristic.
  * @param [in] descriptorUUID The UUID of the descriptor that we wish to retrieve.
  * @return The BLE Descriptor.  If no such descriptor is associated with the characteristic, nullptr is returned.
  */
-BLEDescriptor* BLECharacteristic::getDescriptorByUUID(const char* descriptorUUID) {
-	return m_descriptorMap.getByUUID(BLEUUID(descriptorUUID));
-} // getDescriptorByUUID
-
+BLEDescriptor *BLECharacteristic::getDescriptorByUUID(const char *descriptorUUID) {
+  return m_descriptorMap.getByUUID(BLEUUID(descriptorUUID));
+}  // getDescriptorByUUID
 
 /**
  * @brief Return the BLE Descriptor for the given UUID if associated with this characteristic.
  * @param [in] descriptorUUID The UUID of the descriptor that we wish to retrieve.
  * @return The BLE Descriptor.  If no such descriptor is associated with the characteristic, nullptr is returned.
  */
-BLEDescriptor* BLECharacteristic::getDescriptorByUUID(BLEUUID descriptorUUID) {
-	return m_descriptorMap.getByUUID(descriptorUUID);
-} // getDescriptorByUUID
-
+BLEDescriptor *BLECharacteristic::getDescriptorByUUID(BLEUUID descriptorUUID) {
+  return m_descriptorMap.getByUUID(descriptorUUID);
+}  // getDescriptorByUUID
 
 /**
  * @brief Get the handle of the characteristic.
  * @return The handle of the characteristic.
  */
 uint16_t BLECharacteristic::getHandle() {
-	return m_handle;
-} // getHandle
+  return m_handle;
+}  // getHandle
 
 void BLECharacteristic::setAccessPermissions(esp_gatt_perm_t perm) {
-	m_permissions = perm;
+  m_permissions = perm;
 }
 
 esp_gatt_char_prop_t BLECharacteristic::getProperties() {
-	return m_properties;
-} // getProperties
-
+  return m_properties;
+}  // getProperties
 
 /**
  * @brief Get the service associated with this characteristic.
  */
-BLEService* BLECharacteristic::getService() {
-	return m_pService;
-} // getService
-
+BLEService *BLECharacteristic::getService() {
+  return m_pService;
+}  // getService
 
 /**
  * @brief Get the UUID of the characteristic.
  * @return The UUID of the characteristic.
  */
 BLEUUID BLECharacteristic::getUUID() {
-	return m_bleUUID;
-} // getUUID
-
+  return m_bleUUID;
+}  // getUUID
 
 /**
  * @brief Retrieve the current value of the characteristic.
  * @return A pointer to storage containing the current characteristic value.
  */
-std::string BLECharacteristic::getValue() {
-	return m_value.getValue();
-} // getValue
+String BLECharacteristic::getValue() {
+  return m_value.getValue();
+}  // getValue
 
 /**
  * @brief Retrieve the current raw data of the characteristic.
  * @return A pointer to storage containing the current characteristic data.
  */
-uint8_t* BLECharacteristic::getData() {
-	return m_value.getData();
-} // getData
+uint8_t *BLECharacteristic::getData() {
+  return m_value.getData();
+}  // getData
 
+/**
+ * @brief Retrieve the current length of the data of the characteristic.
+ * @return Amount of databytes of the characteristic.
+ */
+size_t BLECharacteristic::getLength() {
+  return m_value.getLength();
+}  // getLength
 
 /**
  * Handle a GATT server event.
  */
-void BLECharacteristic::handleGATTServerEvent(
-		esp_gatts_cb_event_t      event,
-		esp_gatt_if_t             gatts_if,
-		esp_ble_gatts_cb_param_t* param) {
-	log_v(">> handleGATTServerEvent: %s", BLEUtils::gattServerEventTypeToString(event).c_str());
-
-	switch(event) {
-	// Events handled:
-	//
-	// ESP_GATTS_ADD_CHAR_EVT
-	// ESP_GATTS_CONF_EVT
-	// ESP_GATTS_CONNECT_EVT
-	// ESP_GATTS_DISCONNECT_EVT
-	// ESP_GATTS_EXEC_WRITE_EVT
-	// ESP_GATTS_READ_EVT
-	// ESP_GATTS_WRITE_EVT
-
-		//
-		// ESP_GATTS_EXEC_WRITE_EVT
-		// When we receive this event it is an indication that a previous write long needs to be committed.
-		//
-		// exec_write:
-		// - uint16_t conn_id
-		// - uint32_t trans_id
-		// - esp_bd_addr_t bda
-		// - uint8_t exec_write_flag - Either ESP_GATT_PREP_WRITE_EXEC or ESP_GATT_PREP_WRITE_CANCEL
-		//
-		case ESP_GATTS_EXEC_WRITE_EVT: {
-			if(m_writeEvt){
-				m_writeEvt = false;
-				if (param->exec_write.exec_write_flag == ESP_GATT_PREP_WRITE_EXEC) {
-					m_value.commit();
-					m_pCallbacks->onWrite(this); // Invoke the onWrite callback handler.
-				} else {
-					m_value.cancel();
-				}
-	// ???
-				esp_err_t errRc = ::esp_ble_gatts_send_response(
-						gatts_if,
-						param->write.conn_id,
-						param->write.trans_id, ESP_GATT_OK, nullptr);
-				if (errRc != ESP_OK) {
-					log_e("esp_ble_gatts_send_response: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-				}
-			}
-			break;
-		} // ESP_GATTS_EXEC_WRITE_EVT
-
-
-		// ESP_GATTS_ADD_CHAR_EVT - Indicate that a characteristic was added to the service.
-		// add_char:
-		// - esp_gatt_status_t status
-		// - uint16_t attr_handle
-		// - uint16_t service_handle
-		// - esp_bt_uuid_t char_uuid
-		case ESP_GATTS_ADD_CHAR_EVT: {
-			if (getHandle() == param->add_char.attr_handle) {
-				// we have created characteristic, now we can create descriptors
-				// BLEDescriptor* pDescriptor = m_descriptorMap.getFirst();
-				// while (pDescriptor != nullptr) {
-				// 	pDescriptor->executeCreate(this);
-				// 	pDescriptor = m_descriptorMap.getNext();
-				// } // End while
-				m_semaphoreCreateEvt.give();
-			}
-			break;
-		} // ESP_GATTS_ADD_CHAR_EVT
-
-
-		// ESP_GATTS_WRITE_EVT - A request to write the value of a characteristic has arrived.
-		//
-		// write:
-		// - uint16_t      conn_id
-		// - uint16_t      trans_id
-		// - esp_bd_addr_t bda
-		// - uint16_t      handle
-		// - uint16_t      offset
-		// - bool          need_rsp
-		// - bool          is_prep
-		// - uint16_t      len
-		// - uint8_t      *value
-		//
-		case ESP_GATTS_WRITE_EVT: {
-// We check if this write request is for us by comparing the handles in the event.  If it is for us
-// we save the new value.  Next we look at the need_rsp flag which indicates whether or not we need
-// to send a response.  If we do, then we formulate a response and send it.
-			if (param->write.handle == m_handle) {
-				if (param->write.is_prep) {
-					m_value.addPart(param->write.value, param->write.len);
-					m_writeEvt = true;
-				} else {
-					setValue(param->write.value, param->write.len);
-				}
-
-				log_d(" - Response to write event: New value: handle: %.2x, uuid: %s",
-						getHandle(), getUUID().toString().c_str());
-
-				char* pHexData = BLEUtils::buildHexData(nullptr, param->write.value, param->write.len);
-				log_d(" - Data: length: %d, data: %s", param->write.len, pHexData);
-				free(pHexData);
-
-				if (param->write.need_rsp) {
-					esp_gatt_rsp_t rsp;
-
-					rsp.attr_value.len      = param->write.len;
-					rsp.attr_value.handle   = m_handle;
-					rsp.attr_value.offset   = param->write.offset;
-					rsp.attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE;
-					memcpy(rsp.attr_value.value, param->write.value, param->write.len);
-
-					esp_err_t errRc = ::esp_ble_gatts_send_response(
-							gatts_if,
-							param->write.conn_id,
-							param->write.trans_id, ESP_GATT_OK, &rsp);
-					if (errRc != ESP_OK) {
-						log_e("esp_ble_gatts_send_response: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-					}
-				} // Response needed
-
-				if (param->write.is_prep != true) {
-					m_pCallbacks->onWrite(this); // Invoke the onWrite callback handler.
-				}
-			} // Match on handles.
-			break;
-		} // ESP_GATTS_WRITE_EVT
-
-
-		// ESP_GATTS_READ_EVT - A request to read the value of a characteristic has arrived.
-		//
-		// read:
-		// - uint16_t      conn_id
-		// - uint32_t      trans_id
-		// - esp_bd_addr_t bda
-		// - uint16_t      handle
-		// - uint16_t      offset
-		// - bool          is_long
-		// - bool          need_rsp
-		//
-		case ESP_GATTS_READ_EVT: {
-			if (param->read.handle == m_handle) {
-
-
-
-// Here's an interesting thing.  The read request has the option of saying whether we need a response
-// or not.  What would it "mean" to receive a read request and NOT send a response back?  That feels like
-// a very strange read.
-//
-// We have to handle the case where the data we wish to send back to the client is greater than the maximum
-// packet size of 22 bytes.  In this case, we become responsible for chunking the data into units of 22 bytes.
-// The apparent algorithm is as follows:
-//
-// If the is_long flag is set then this is a follow on from an original read and we will already have sent at least 22 bytes.
-// If the is_long flag is not set then we need to check how much data we are going to send.  If we are sending LESS than
-// 22 bytes, then we "just" send it and thats the end of the story.
-// If we are sending 22 bytes exactly, we just send it BUT we will get a follow on request.
-// If we are sending more than 22 bytes, we send the first 22 bytes and we will get a follow on request.
-// Because of follow on request processing, we need to maintain an offset of how much data we have already sent
-// so that when a follow on request arrives, we know where to start in the data to send the next sequence.
-// Note that the indication that the client will send a follow on request is that we sent exactly 22 bytes as a response.
-// If our payload is divisible by 22 then the last response will be a response of 0 bytes in length.
-//
-// The following code has deliberately not been factored to make it fewer statements because this would cloud the
-// the logic flow comprehension.
-//
-
-				// get mtu for peer device that we are sending read request to
-				uint16_t maxOffset =  getService()->getServer()->getPeerMTU(param->read.conn_id) - 1;
-				log_d("mtu value: %d", maxOffset);
-				if (param->read.need_rsp) {
-					log_d("Sending a response (esp_ble_gatts_send_response)");
-					esp_gatt_rsp_t rsp;
-
-					if (param->read.is_long) {
-						std::string value = m_value.getValue();
-
-						if (value.length() - m_value.getReadOffset() < maxOffset) {
-							// This is the last in the chain
-							rsp.attr_value.len    = value.length() - m_value.getReadOffset();
-							rsp.attr_value.offset = m_value.getReadOffset();
-							memcpy(rsp.attr_value.value, value.data() + rsp.attr_value.offset, rsp.attr_value.len);
-							m_value.setReadOffset(0);
-						} else {
-							// There will be more to come.
-							rsp.attr_value.len    = maxOffset;
-							rsp.attr_value.offset = m_value.getReadOffset();
-							memcpy(rsp.attr_value.value, value.data() + rsp.attr_value.offset, rsp.attr_value.len);
-							m_value.setReadOffset(rsp.attr_value.offset + maxOffset);
-						}
-					} else { // read.is_long == false
-
-						// If is.long is false then this is the first (or only) request to read data, so invoke the callback
-						// Invoke the read callback.
-						m_pCallbacks->onRead(this);
-
-						std::string value = m_value.getValue();
-
-						if (value.length() + 1 > maxOffset) {
-							// Too big for a single shot entry.
-							m_value.setReadOffset(maxOffset);
-							rsp.attr_value.len    = maxOffset;
-							rsp.attr_value.offset = 0;
-							memcpy(rsp.attr_value.value, value.data(), rsp.attr_value.len);
-						} else {
-							// Will fit in a single packet with no callbacks required.
-							rsp.attr_value.len    = value.length();
-							rsp.attr_value.offset = 0;
-							memcpy(rsp.attr_value.value, value.data(), rsp.attr_value.len);
-						}
-					}
-					rsp.attr_value.handle   = param->read.handle;
-					rsp.attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE;
-
-					char *pHexData = BLEUtils::buildHexData(nullptr, rsp.attr_value.value, rsp.attr_value.len);
-					log_d(" - Data: length=%d, data=%s, offset=%d", rsp.attr_value.len, pHexData, rsp.attr_value.offset);
-					free(pHexData);
-
-					esp_err_t errRc = ::esp_ble_gatts_send_response(
-							gatts_if, param->read.conn_id,
-							param->read.trans_id,
-							ESP_GATT_OK,
-							&rsp);
-					if (errRc != ESP_OK) {
-						log_e("esp_ble_gatts_send_response: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-					}
-				} // Response needed
-			} // Handle matches this characteristic.
-			break;
-		} // ESP_GATTS_READ_EVT
-
-
-		// ESP_GATTS_CONF_EVT
-		//
-		// conf:
-		// - esp_gatt_status_t status  – The status code.
-		// - uint16_t          conn_id – The connection used.
-		//
-		case ESP_GATTS_CONF_EVT: {
-			// log_d("m_handle = %d, conf->handle = %d", m_handle, param->conf.handle);
-			if(param->conf.conn_id == getService()->getServer()->getConnId()) // && param->conf.handle == m_handle) // bug in esp-idf and not implemented in arduino yet
-				m_semaphoreConfEvt.give(param->conf.status);
-			break;
-		}
-
-		case ESP_GATTS_CONNECT_EVT: {
-			break;
-		}
-
-		case ESP_GATTS_DISCONNECT_EVT: {
-			m_semaphoreConfEvt.give();
-			break;
-		}
-
-		default: {
-			break;
-		} // default
-
-	} // switch event
-
-	// Give each of the descriptors associated with this characteristic the opportunity to handle the
-	// event.
-
-	m_descriptorMap.handleGATTServerEvent(event, gatts_if, param);
-	log_v("<< handleGATTServerEvent");
-} // handleGATTServerEvent
-
+void BLECharacteristic::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) {
+  log_v(">> handleGATTServerEvent: %s", BLEUtils::gattServerEventTypeToString(event).c_str());
+
+  switch (event) {
+      // Events handled:
+      //
+      // ESP_GATTS_ADD_CHAR_EVT
+      // ESP_GATTS_CONF_EVT
+      // ESP_GATTS_CONNECT_EVT
+      // ESP_GATTS_DISCONNECT_EVT
+      // ESP_GATTS_EXEC_WRITE_EVT
+      // ESP_GATTS_READ_EVT
+      // ESP_GATTS_WRITE_EVT
+
+    //
+    // ESP_GATTS_EXEC_WRITE_EVT
+    // When we receive this event it is an indication that a previous write long needs to be committed.
+    //
+    // exec_write:
+    // - uint16_t conn_id
+    // - uint32_t trans_id
+    // - esp_bd_addr_t bda
+    // - uint8_t exec_write_flag - Either ESP_GATT_PREP_WRITE_EXEC or ESP_GATT_PREP_WRITE_CANCEL
+    //
+    case ESP_GATTS_EXEC_WRITE_EVT:
+    {
+      if (m_writeEvt) {
+        m_writeEvt = false;
+        if (param->exec_write.exec_write_flag == ESP_GATT_PREP_WRITE_EXEC) {
+          m_value.commit();
+          // Invoke the onWrite callback handler.
+          m_pCallbacks->onWrite(this, param);
+        } else {
+          m_value.cancel();
+        }
+        // ???
+        esp_err_t errRc = ::esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, ESP_GATT_OK, nullptr);
+        if (errRc != ESP_OK) {
+          log_e("esp_ble_gatts_send_response: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+        }
+      }
+      break;
+    }  // ESP_GATTS_EXEC_WRITE_EVT
+
+    // ESP_GATTS_ADD_CHAR_EVT - Indicate that a characteristic was added to the service.
+    // add_char:
+    // - esp_gatt_status_t status
+    // - uint16_t attr_handle
+    // - uint16_t service_handle
+    // - esp_bt_uuid_t char_uuid
+    case ESP_GATTS_ADD_CHAR_EVT:
+    {
+      if (getHandle() == param->add_char.attr_handle) {
+        // we have created characteristic, now we can create descriptors
+        // BLEDescriptor* pDescriptor = m_descriptorMap.getFirst();
+        // while (pDescriptor != nullptr) {
+        // 	pDescriptor->executeCreate(this);
+        // 	pDescriptor = m_descriptorMap.getNext();
+        // } // End while
+        m_semaphoreCreateEvt.give();
+      }
+      break;
+    }  // ESP_GATTS_ADD_CHAR_EVT
+
+    // ESP_GATTS_WRITE_EVT - A request to write the value of a characteristic has arrived.
+    //
+    // write:
+    // - uint16_t      conn_id
+    // - uint16_t      trans_id
+    // - esp_bd_addr_t bda
+    // - uint16_t      handle
+    // - uint16_t      offset
+    // - bool          need_rsp
+    // - bool          is_prep
+    // - uint16_t      len
+    // - uint8_t      *value
+    //
+    case ESP_GATTS_WRITE_EVT:
+    {
+      // We check if this write request is for us by comparing the handles in the event.  If it is for us
+      // we save the new value.  Next we look at the need_rsp flag which indicates whether or not we need
+      // to send a response.  If we do, then we formulate a response and send it.
+      if (param->write.handle == m_handle) {
+        if (param->write.is_prep) {
+          m_value.addPart(param->write.value, param->write.len);
+          m_writeEvt = true;
+        } else {
+          setValue(param->write.value, param->write.len);
+        }
+
+        log_d(" - Response to write event: New value: handle: %.2x, uuid: %s", getHandle(), getUUID().toString().c_str());
+
+// The call to BLEUtils::buildHexData() doesn't output anything if the log level is not
+// "DEBUG". As it is quite CPU intensive, it is much better to not call it if not needed.
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+        char *pHexData = BLEUtils::buildHexData(nullptr, param->write.value, param->write.len);
+        log_d(" - Data: length: %d, data: %s", param->write.len, pHexData);
+        free(pHexData);
+#endif
+
+        if (param->write.need_rsp) {
+          esp_gatt_rsp_t rsp;
+
+          rsp.attr_value.len = param->write.len;
+          rsp.attr_value.handle = m_handle;
+          rsp.attr_value.offset = param->write.offset;
+          rsp.attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE;
+          memcpy(rsp.attr_value.value, param->write.value, param->write.len);
+
+          esp_err_t errRc = ::esp_ble_gatts_send_response(gatts_if, param->write.conn_id, param->write.trans_id, ESP_GATT_OK, &rsp);
+          if (errRc != ESP_OK) {
+            log_e("esp_ble_gatts_send_response: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+          }
+        }  // Response needed
+
+        if (param->write.is_prep != true) {
+          // Invoke the onWrite callback handler.
+          m_pCallbacks->onWrite(this, param);
+        }
+      }  // Match on handles.
+      break;
+    }  // ESP_GATTS_WRITE_EVT
+
+    // ESP_GATTS_READ_EVT - A request to read the value of a characteristic has arrived.
+    //
+    // read:
+    // - uint16_t      conn_id
+    // - uint32_t      trans_id
+    // - esp_bd_addr_t bda
+    // - uint16_t      handle
+    // - uint16_t      offset
+    // - bool          is_long
+    // - bool          need_rsp
+    //
+    case ESP_GATTS_READ_EVT:
+    {
+      if (param->read.handle == m_handle) {
+
+        // Here's an interesting thing.  The read request has the option of saying whether we need a response
+        // or not.  What would it "mean" to receive a read request and NOT send a response back?  That feels like
+        // a very strange read.
+        //
+        // We have to handle the case where the data we wish to send back to the client is greater than the maximum
+        // packet size of 22 bytes.  In this case, we become responsible for chunking the data into units of 22 bytes.
+        // The apparent algorithm is as follows:
+        //
+        // If the is_long flag is set then this is a follow on from an original read and we will already have sent at least 22 bytes.
+        // If the is_long flag is not set then we need to check how much data we are going to send.  If we are sending LESS than
+        // 22 bytes, then we "just" send it and that's the end of the story.
+        // If we are sending 22 bytes exactly, we just send it BUT we will get a follow on request.
+        // If we are sending more than 22 bytes, we send the first 22 bytes and we will get a follow on request.
+        // Because of follow on request processing, we need to maintain an offset of how much data we have already sent
+        // so that when a follow on request arrives, we know where to start in the data to send the next sequence.
+        // Note that the indication that the client will send a follow on request is that we sent exactly 22 bytes as a response.
+        // If our payload is divisible by 22 then the last response will be a response of 0 bytes in length.
+        //
+        // The following code has deliberately not been factored to make it fewer statements because this would cloud the
+        // the logic flow comprehension.
+        //
+
+        // get mtu for peer device that we are sending read request to
+        uint16_t maxOffset = getService()->getServer()->getPeerMTU(param->read.conn_id) - 1;
+        log_d("mtu value: %d", maxOffset);
+        if (param->read.need_rsp) {
+          log_d("Sending a response (esp_ble_gatts_send_response)");
+          esp_gatt_rsp_t rsp;
+
+          if (param->read.is_long) {
+            String value = m_value.getValue();
+
+            if (value.length() - m_value.getReadOffset() < maxOffset) {
+              // This is the last in the chain
+              rsp.attr_value.len = value.length() - m_value.getReadOffset();
+              rsp.attr_value.offset = m_value.getReadOffset();
+              memcpy(rsp.attr_value.value, value.c_str() + rsp.attr_value.offset, rsp.attr_value.len);
+              m_value.setReadOffset(0);
+            } else {
+              // There will be more to come.
+              rsp.attr_value.len = maxOffset;
+              rsp.attr_value.offset = m_value.getReadOffset();
+              memcpy(rsp.attr_value.value, value.c_str() + rsp.attr_value.offset, rsp.attr_value.len);
+              m_value.setReadOffset(rsp.attr_value.offset + maxOffset);
+            }
+          } else {  // read.is_long == false
+
+            // If is.long is false then this is the first (or only) request to read data, so invoke the callback
+            // Invoke the read callback.
+            m_pCallbacks->onRead(this, param);
+
+            String value = m_value.getValue();
+
+            if (value.length() + 1 > maxOffset) {
+              // Too big for a single shot entry.
+              m_value.setReadOffset(maxOffset);
+              rsp.attr_value.len = maxOffset;
+              rsp.attr_value.offset = 0;
+              memcpy(rsp.attr_value.value, value.c_str(), rsp.attr_value.len);
+            } else {
+              // Will fit in a single packet with no callbacks required.
+              rsp.attr_value.len = value.length();
+              rsp.attr_value.offset = 0;
+              memcpy(rsp.attr_value.value, value.c_str(), rsp.attr_value.len);
+            }
+          }
+          rsp.attr_value.handle = param->read.handle;
+          rsp.attr_value.auth_req = ESP_GATT_AUTH_REQ_NONE;
+
+// The call to BLEUtils::buildHexData() doesn't output anything if the log level is not
+// "DEBUG". As it is quite CPU intensive, it is much better to not call it if not needed.
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+          char *pHexData = BLEUtils::buildHexData(nullptr, rsp.attr_value.value, rsp.attr_value.len);
+          log_d(" - Data: length=%d, data=%s, offset=%d", rsp.attr_value.len, pHexData, rsp.attr_value.offset);
+          free(pHexData);
+#endif
+
+          esp_err_t errRc = ::esp_ble_gatts_send_response(gatts_if, param->read.conn_id, param->read.trans_id, ESP_GATT_OK, &rsp);
+          if (errRc != ESP_OK) {
+            log_e("esp_ble_gatts_send_response: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+          }
+        }  // Response needed
+      }  // Handle matches this characteristic.
+      break;
+    }  // ESP_GATTS_READ_EVT
+
+    // ESP_GATTS_CONF_EVT
+    //
+    // conf:
+    // - esp_gatt_status_t status  – The status code.
+    // - uint16_t          conn_id – The connection used.
+    //
+    case ESP_GATTS_CONF_EVT:
+    {
+      // log_d("m_handle = %d, conf->handle = %d", m_handle, param->conf.handle);
+      if (param->conf.conn_id
+          == getService()->getServer()->getConnId()) {  // && param->conf.handle == m_handle) // bug in esp-idf and not implemented in arduino yet
+        m_semaphoreConfEvt.give(param->conf.status);
+      }
+      break;
+    }
+
+    case ESP_GATTS_CONNECT_EVT:
+    {
+      break;
+    }
+
+    case ESP_GATTS_DISCONNECT_EVT:
+    {
+      m_semaphoreConfEvt.give();
+      break;
+    }
+
+    default:
+    {
+      break;
+    }  // default
+
+  }  // switch event
+
+  // Give each of the descriptors associated with this characteristic the opportunity to handle the
+  // event.
+
+  m_descriptorMap.handleGATTServerEvent(event, gatts_if, param);
+  log_v("<< handleGATTServerEvent");
+}  // handleGATTServerEvent
 
 /**
  * @brief Send an indication.
@@ -465,11 +460,10 @@ void BLECharacteristic::handleGATTServerEvent(
  */
 void BLECharacteristic::indicate() {
 
-	log_v(">> indicate: length: %d", m_value.getValue().length());
-	notify(false);
-	log_v("<< indicate");
-} // indicate
-
+  log_v(">> indicate: length: %d", m_value.getValue().length());
+  notify(false);
+  log_v("<< indicate");
+}  // indicate
 
 /**
  * @brief Send a notify.
@@ -478,76 +472,87 @@ void BLECharacteristic::indicate() {
  * @return N/A.
  */
 void BLECharacteristic::notify(bool is_notification) {
-	log_v(">> notify: length: %d", m_value.getValue().length());
-
-	assert(getService() != nullptr);
-	assert(getService()->getServer() != nullptr);
-
-	m_pCallbacks->onNotify(this);   // Invoke the notify callback.
-
-	GeneralUtils::hexDump((uint8_t*)m_value.getValue().data(), m_value.getValue().length());
-
-	if (getService()->getServer()->getConnectedCount() == 0) {
-		log_v("<< notify: No connected clients.");
-		m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_NO_CLIENT, 0);
-		return;
-	}
-
-	// Test to see if we have a 0x2902 descriptor.  If we do, then check to see if notification is enabled
-	// and, if not, prevent the notification.
-
-	BLE2902 *p2902 = (BLE2902*)getDescriptorByUUID((uint16_t)0x2902);
-	if(is_notification) {
-		if (p2902 != nullptr && !p2902->getNotifications()) {
-			log_v("<< notifications disabled; ignoring");
-			m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_NOTIFY_DISABLED, 0);   // Invoke the notify callback.
-			return;
-		}
-	}
-	else{
-		if (p2902 != nullptr && !p2902->getIndications()) {
-			log_v("<< indications disabled; ignoring");
-			m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_DISABLED, 0);   // Invoke the notify callback.
-			return;
-		}
-	}
-	for (auto &myPair : getService()->getServer()->getPeerDevices(false)) {
-		uint16_t _mtu = (myPair.second.mtu);
-		if (m_value.getValue().length() > _mtu - 3) {
-			log_w("- Truncating to %d bytes (maximum notify size)", _mtu - 3);
-		}
-
-		size_t length = m_value.getValue().length();
-		if(!is_notification) // is indication
-			m_semaphoreConfEvt.take("indicate");
-		esp_err_t errRc = ::esp_ble_gatts_send_indicate(
-				getService()->getServer()->getGattsIf(),
-				myPair.first,
-				getHandle(), length, (uint8_t*)m_value.getValue().data(), !is_notification); // The need_confirm = false makes this a notify.
-		if (errRc != ESP_OK) {
-			log_e("<< esp_ble_gatts_send_ %s: rc=%d %s",is_notification?"notify":"indicate", errRc, GeneralUtils::errorToString(errRc));
-			m_semaphoreConfEvt.give();
-			m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_GATT, errRc);   // Invoke the notify callback.
-			return;
-		}
-		if(!is_notification){ // is indication
-			if(!m_semaphoreConfEvt.timedWait("indicate", indicationTimeout)){
-				m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_TIMEOUT, 0);   // Invoke the notify callback.
-			} else {
-				auto code = (esp_gatt_status_t) m_semaphoreConfEvt.value();
-				if(code == ESP_GATT_OK) {
-					m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::SUCCESS_INDICATE, code);   // Invoke the notify callback.
-				} else {
-					m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_FAILURE, code);
-				}
-			}
-		} else {
-			m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::SUCCESS_NOTIFY, 0);   // Invoke the notify callback.
-		}
-	}
-	log_v("<< notify");
-} // Notify
-
+  log_v(">> notify: length: %d", m_value.getValue().length());
+
+  assert(getService() != nullptr);
+  assert(getService()->getServer() != nullptr);
+
+  m_pCallbacks->onNotify(this);  // Invoke the notify callback.
+
+  // GeneralUtils::hexDump() doesn't output anything if the log level is not
+  // "VERBOSE". Additionally, it is very CPU intensive, even when it doesn't
+  // output anything! So it is much better to *not* call it at all if not needed.
+  // In a simple program which calls BLECharacteristic::notify() every 50 ms,
+  // the performance gain of this little optimization is 37% in release mode
+  // (-O3) and 57% in debug mode.
+  // Of course, the "#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE" guard
+  // could also be put inside the GeneralUtils::hexDump() function itself. But
+  // it's better to put it here also, as it is clearer (indicating a verbose log
+  // thing) and it allows to remove the "m_value.getValue().c_str()" call, which
+  // is, in itself, quite CPU intensive.
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+  GeneralUtils::hexDump((uint8_t *)m_value.getValue().c_str(), m_value.getValue().length());
+#endif
+
+  if (getService()->getServer()->getConnectedCount() == 0) {
+    log_v("<< notify: No connected clients.");
+    m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_NO_CLIENT, 0);
+    return;
+  }
+
+  // Test to see if we have a 0x2902 descriptor.  If we do, then check to see if notification is enabled
+  // and, if not, prevent the notification.
+
+  BLE2902 *p2902 = (BLE2902 *)getDescriptorByUUID((uint16_t)0x2902);
+  if (is_notification) {
+    if (p2902 != nullptr && !p2902->getNotifications()) {
+      log_v("<< notifications disabled; ignoring");
+      m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_NOTIFY_DISABLED, 0);  // Invoke the notify callback.
+      return;
+    }
+  } else {
+    if (p2902 != nullptr && !p2902->getIndications()) {
+      log_v("<< indications disabled; ignoring");
+      m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_DISABLED, 0);  // Invoke the notify callback.
+      return;
+    }
+  }
+  for (auto &myPair : getService()->getServer()->getPeerDevices(false)) {
+    uint16_t _mtu = (myPair.second.mtu);
+    if (m_value.getValue().length() > _mtu - 3) {
+      log_w("- Truncating to %d bytes (maximum notify size)", _mtu - 3);
+    }
+
+    size_t length = m_value.getValue().length();
+    if (!is_notification) {  // is indication
+      m_semaphoreConfEvt.take("indicate");
+    }
+    esp_err_t errRc = ::esp_ble_gatts_send_indicate(
+      getService()->getServer()->getGattsIf(), myPair.first, getHandle(), length, (uint8_t *)m_value.getValue().c_str(), !is_notification
+    );  // The need_confirm = false makes this a notify.
+    if (errRc != ESP_OK) {
+      log_e("<< esp_ble_gatts_send_ %s: rc=%d %s", is_notification ? "notify" : "indicate", errRc, GeneralUtils::errorToString(errRc));
+      m_semaphoreConfEvt.give();
+      m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_GATT, errRc);  // Invoke the notify callback.
+      return;
+    }
+    if (!is_notification) {  // is indication
+      if (!m_semaphoreConfEvt.timedWait("indicate", indicationTimeout)) {
+        m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_TIMEOUT, 0);  // Invoke the notify callback.
+      } else {
+        auto code = (esp_gatt_status_t)m_semaphoreConfEvt.value();
+        if (code == ESP_GATT_OK) {
+          m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::SUCCESS_INDICATE, code);  // Invoke the notify callback.
+        } else {
+          m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::ERROR_INDICATE_FAILURE, code);
+        }
+      }
+    } else {
+      m_pCallbacks->onStatus(this, BLECharacteristicCallbacks::Status::SUCCESS_NOTIFY, 0);  // Invoke the notify callback.
+    }
+  }
+  log_v("<< notify");
+}  // Notify
 
 /**
  * @brief Set the permission to broadcast.
@@ -557,29 +562,27 @@ void BLECharacteristic::notify(bool is_notification) {
  * @return N/A
  */
 void BLECharacteristic::setBroadcastProperty(bool value) {
-	//log_d("setBroadcastProperty(%d)", value);
-	if (value) {
-		m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_BROADCAST);
-	} else {
-		m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_BROADCAST);
-	}
-} // setBroadcastProperty
-
+  //log_d("setBroadcastProperty(%d)", value);
+  if (value) {
+    m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_BROADCAST);
+  } else {
+    m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_BROADCAST);
+  }
+}  // setBroadcastProperty
 
 /**
  * @brief Set the callback handlers for this characteristic.
  * @param [in] pCallbacks An instance of a callbacks structure used to define any callbacks for the characteristic.
  */
-void BLECharacteristic::setCallbacks(BLECharacteristicCallbacks* pCallbacks) {
-	log_v(">> setCallbacks: 0x%x", (uint32_t)pCallbacks);
-	if (pCallbacks != nullptr){
-		m_pCallbacks = pCallbacks;
-	} else {
-		m_pCallbacks = &defaultCallback;
-	}
-	log_v("<< setCallbacks");
-} // setCallbacks
-
+void BLECharacteristic::setCallbacks(BLECharacteristicCallbacks *pCallbacks) {
+  log_v(">> setCallbacks: 0x%x", (uint32_t)pCallbacks);
+  if (pCallbacks != nullptr) {
+    m_pCallbacks = pCallbacks;
+  } else {
+    m_pCallbacks = &defaultCallback;
+  }
+  log_v("<< setCallbacks");
+}  // setCallbacks
 
 /**
  * @brief Set the BLE handle associated with this characteristic.
@@ -592,73 +595,72 @@ void BLECharacteristic::setCallbacks(BLECharacteristicCallbacks* pCallbacks) {
  * @param [in] handle The handle associated with this characteristic.
  */
 void BLECharacteristic::setHandle(uint16_t handle) {
-	log_v(">> setHandle: handle=0x%.2x, characteristic uuid=%s", handle, getUUID().toString().c_str());
-	m_handle = handle;
-	log_v("<< setHandle");
-} // setHandle
-
+  log_v(">> setHandle: handle=0x%.2x, characteristic uuid=%s", handle, getUUID().toString().c_str());
+  m_handle = handle;
+  log_v("<< setHandle");
+}  // setHandle
 
 /**
  * @brief Set the Indicate property value.
  * @param [in] value Set to true if we are to allow indicate messages.
  */
 void BLECharacteristic::setIndicateProperty(bool value) {
-	//log_d("setIndicateProperty(%d)", value);
-	if (value) {
-		m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_INDICATE);
-	} else {
-		m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_INDICATE);
-	}
-} // setIndicateProperty
-
+  //log_d("setIndicateProperty(%d)", value);
+  if (value) {
+    m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_INDICATE);
+  } else {
+    m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_INDICATE);
+  }
+}  // setIndicateProperty
 
 /**
  * @brief Set the Notify property value.
  * @param [in] value Set to true if we are to allow notification messages.
  */
 void BLECharacteristic::setNotifyProperty(bool value) {
-	//log_d("setNotifyProperty(%d)", value);
-	if (value) {
-		m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_NOTIFY);
-	} else {
-		m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_NOTIFY);
-	}
-} // setNotifyProperty
-
+  //log_d("setNotifyProperty(%d)", value);
+  if (value) {
+    m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_NOTIFY);
+  } else {
+    m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_NOTIFY);
+  }
+}  // setNotifyProperty
 
 /**
  * @brief Set the Read property value.
  * @param [in] value Set to true if we are to allow reads.
  */
 void BLECharacteristic::setReadProperty(bool value) {
-	//log_d("setReadProperty(%d)", value);
-	if (value) {
-		m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_READ);
-	} else {
-		m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_READ);
-	}
-} // setReadProperty
-
+  //log_d("setReadProperty(%d)", value);
+  if (value) {
+    m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_READ);
+  } else {
+    m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_READ);
+  }
+}  // setReadProperty
 
 /**
  * @brief Set the value of the characteristic.
  * @param [in] data The data to set for the characteristic.
  * @param [in] length The length of the data in bytes.
  */
-void BLECharacteristic::setValue(uint8_t* data, size_t length) {
-	char* pHex = BLEUtils::buildHexData(nullptr, data, length);
-	log_v(">> setValue: length=%d, data=%s, characteristic UUID=%s", length, pHex, getUUID().toString().c_str());
-	free(pHex);
-	if (length > ESP_GATT_MAX_ATTR_LEN) {
-		log_e("Size %d too large, must be no bigger than %d", length, ESP_GATT_MAX_ATTR_LEN);
-		return;
-	}
-	m_semaphoreSetValue.take();  
-	m_value.setValue(data, length);
-	m_semaphoreSetValue.give();  
-	log_v("<< setValue");
-} // setValue
-
+void BLECharacteristic::setValue(uint8_t *data, size_t length) {
+// The call to BLEUtils::buildHexData() doesn't output anything if the log level is not
+// "VERBOSE". As it is quite CPU intensive, it is much better to not call it if not needed.
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+  char *pHex = BLEUtils::buildHexData(nullptr, data, length);
+  log_v(">> setValue: length=%d, data=%s, characteristic UUID=%s", length, pHex, getUUID().toString().c_str());
+  free(pHex);
+#endif
+  if (length > ESP_GATT_MAX_ATTR_LEN) {
+    log_e("Size %d too large, must be no bigger than %d", length, ESP_GATT_MAX_ATTR_LEN);
+    return;
+  }
+  m_semaphoreSetValue.take();
+  m_value.setValue(data, length);
+  m_semaphoreSetValue.give();
+  log_v("<< setValue");
+}  // setValue
 
 /**
  * @brief Set the value of the characteristic from string data.
@@ -667,137 +669,131 @@ void BLECharacteristic::setValue(uint8_t* data, size_t length) {
  * @param [in] Set the value of the characteristic.
  * @return N/A.
  */
-void BLECharacteristic::setValue(std::string value) {
-	setValue((uint8_t*)(value.data()), value.length());
-} // setValue
-
-void BLECharacteristic::setValue(uint16_t& data16) {
-	uint8_t temp[2];
-	temp[0] = data16;
-	temp[1] = data16 >> 8;
-	setValue(temp, 2);
-} // setValue
-
-void BLECharacteristic::setValue(uint32_t& data32) {
-	uint8_t temp[4];
-	temp[0] = data32;
-	temp[1] = data32 >> 8;
-	temp[2] = data32 >> 16;
-	temp[3] = data32 >> 24;
-	setValue(temp, 4);
-} // setValue
-
-void BLECharacteristic::setValue(int& data32) {
-	uint8_t temp[4];
-	temp[0] = data32;
-	temp[1] = data32 >> 8;
-	temp[2] = data32 >> 16;
-	temp[3] = data32 >> 24;
-	setValue(temp, 4);
-} // setValue
-
-void BLECharacteristic::setValue(float& data32) {
-	float temp = data32;
-	setValue((uint8_t*)&temp, 4);
-} // setValue
-
-void BLECharacteristic::setValue(double& data64) {
-	double temp = data64;
-	setValue((uint8_t*)&temp, 8);
-} // setValue
-
+void BLECharacteristic::setValue(String value) {
+  setValue((uint8_t *)(value.c_str()), value.length());
+}  // setValue
+
+void BLECharacteristic::setValue(uint16_t &data16) {
+  uint8_t temp[2];
+  temp[0] = data16;
+  temp[1] = data16 >> 8;
+  setValue(temp, 2);
+}  // setValue
+
+void BLECharacteristic::setValue(uint32_t &data32) {
+  uint8_t temp[4];
+  temp[0] = data32;
+  temp[1] = data32 >> 8;
+  temp[2] = data32 >> 16;
+  temp[3] = data32 >> 24;
+  setValue(temp, 4);
+}  // setValue
+
+void BLECharacteristic::setValue(int &data32) {
+  uint8_t temp[4];
+  temp[0] = data32;
+  temp[1] = data32 >> 8;
+  temp[2] = data32 >> 16;
+  temp[3] = data32 >> 24;
+  setValue(temp, 4);
+}  // setValue
+
+void BLECharacteristic::setValue(float &data32) {
+  float temp = data32;
+  setValue((uint8_t *)&temp, 4);
+}  // setValue
+
+void BLECharacteristic::setValue(double &data64) {
+  double temp = data64;
+  setValue((uint8_t *)&temp, 8);
+}  // setValue
 
 /**
  * @brief Set the Write No Response property value.
  * @param [in] value Set to true if we are to allow writes with no response.
  */
 void BLECharacteristic::setWriteNoResponseProperty(bool value) {
-	//log_d("setWriteNoResponseProperty(%d)", value);
-	if (value) {
-		m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_WRITE_NR);
-	} else {
-		m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_WRITE_NR);
-	}
-} // setWriteNoResponseProperty
-
+  //log_d("setWriteNoResponseProperty(%d)", value);
+  if (value) {
+    m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_WRITE_NR);
+  } else {
+    m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_WRITE_NR);
+  }
+}  // setWriteNoResponseProperty
 
 /**
  * @brief Set the Write property value.
  * @param [in] value Set to true if we are to allow writes.
  */
 void BLECharacteristic::setWriteProperty(bool value) {
-	//log_d("setWriteProperty(%d)", value);
-	if (value) {
-		m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_WRITE);
-	} else {
-		m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_WRITE);
-	}
-} // setWriteProperty
-
+  //log_d("setWriteProperty(%d)", value);
+  if (value) {
+    m_properties = (esp_gatt_char_prop_t)(m_properties | ESP_GATT_CHAR_PROP_BIT_WRITE);
+  } else {
+    m_properties = (esp_gatt_char_prop_t)(m_properties & ~ESP_GATT_CHAR_PROP_BIT_WRITE);
+  }
+}  // setWriteProperty
 
 /**
  * @brief Return a string representation of the characteristic.
  * @return A string representation of the characteristic.
  */
-std::string BLECharacteristic::toString() {
-	std::string res = "UUID: " + m_bleUUID.toString() + ", handle : 0x";
-	char hex[5];
-	snprintf(hex, sizeof(hex), "%04x", m_handle);
-	res += hex;
-	res += " ";
-	if (m_properties & ESP_GATT_CHAR_PROP_BIT_READ) res += "Read ";
-	if (m_properties & ESP_GATT_CHAR_PROP_BIT_WRITE) res += "Write ";
-	if (m_properties & ESP_GATT_CHAR_PROP_BIT_WRITE_NR) res += "WriteNoResponse ";
-	if (m_properties & ESP_GATT_CHAR_PROP_BIT_BROADCAST) res += "Broadcast ";
-	if (m_properties & ESP_GATT_CHAR_PROP_BIT_NOTIFY) res += "Notify ";
-	if (m_properties & ESP_GATT_CHAR_PROP_BIT_INDICATE) res += "Indicate ";
-	return res;
-} // toString
-
+String BLECharacteristic::toString() {
+  String res = "UUID: " + m_bleUUID.toString() + ", handle : 0x";
+  char hex[5];
+  snprintf(hex, sizeof(hex), "%04x", m_handle);
+  res += hex;
+  res += " ";
+  if (m_properties & ESP_GATT_CHAR_PROP_BIT_READ) {
+    res += "Read ";
+  }
+  if (m_properties & ESP_GATT_CHAR_PROP_BIT_WRITE) {
+    res += "Write ";
+  }
+  if (m_properties & ESP_GATT_CHAR_PROP_BIT_WRITE_NR) {
+    res += "WriteNoResponse ";
+  }
+  if (m_properties & ESP_GATT_CHAR_PROP_BIT_BROADCAST) {
+    res += "Broadcast ";
+  }
+  if (m_properties & ESP_GATT_CHAR_PROP_BIT_NOTIFY) {
+    res += "Notify ";
+  }
+  if (m_properties & ESP_GATT_CHAR_PROP_BIT_INDICATE) {
+    res += "Indicate ";
+  }
+  return res;
+}  // toString
 
 BLECharacteristicCallbacks::~BLECharacteristicCallbacks() {}
 
+void BLECharacteristicCallbacks::onRead(BLECharacteristic *pCharacteristic, esp_ble_gatts_cb_param_t *param) {
+  onRead(pCharacteristic);
+}  // onRead
 
-/**
- * @brief Callback function to support a read request.
- * @param [in] pCharacteristic The characteristic that is the source of the event.
- */
-void BLECharacteristicCallbacks::onRead(BLECharacteristic* pCharacteristic) {
-	log_d("BLECharacteristicCallbacks", ">> onRead: default");
-	log_d("BLECharacteristicCallbacks", "<< onRead");
-} // onRead
-
-
-/**
- * @brief Callback function to support a write request.
- * @param [in] pCharacteristic The characteristic that is the source of the event.
- */
-void BLECharacteristicCallbacks::onWrite(BLECharacteristic* pCharacteristic) {
-	log_d("BLECharacteristicCallbacks", ">> onWrite: default");
-	log_d("BLECharacteristicCallbacks", "<< onWrite");
-} // onWrite
+void BLECharacteristicCallbacks::onRead(BLECharacteristic *pCharacteristic) {
+  log_d(">> onRead: default");
+  log_d("<< onRead");
+}  // onRead
 
+void BLECharacteristicCallbacks::onWrite(BLECharacteristic *pCharacteristic, esp_ble_gatts_cb_param_t *param) {
+  onWrite(pCharacteristic);
+}  // onWrite
 
-/**
- * @brief Callback function to support a Notify request.
- * @param [in] pCharacteristic The characteristic that is the source of the event.
- */
-void BLECharacteristicCallbacks::onNotify(BLECharacteristic* pCharacteristic) {
-	log_d("BLECharacteristicCallbacks", ">> onNotify: default");
-	log_d("BLECharacteristicCallbacks", "<< onNotify");
-} // onNotify
-
+void BLECharacteristicCallbacks::onWrite(BLECharacteristic *pCharacteristic) {
+  log_d(">> onWrite: default");
+  log_d("<< onWrite");
+}  // onWrite
 
-/**
- * @brief Callback function to support a Notify/Indicate Status report.
- * @param [in] pCharacteristic The characteristic that is the source of the event.
- * @param [in] s Status of the notification/indication
- * @param [in] code Additional code of underlying errors
- */
-void BLECharacteristicCallbacks::onStatus(BLECharacteristic* pCharacteristic, Status s, uint32_t code) {
-	log_d("BLECharacteristicCallbacks", ">> onStatus: default");
-	log_d("BLECharacteristicCallbacks", "<< onStatus");
-} // onStatus
+void BLECharacteristicCallbacks::onNotify(BLECharacteristic *pCharacteristic) {
+  log_d(">> onNotify: default");
+  log_d("<< onNotify");
+}  // onNotify
 
+void BLECharacteristicCallbacks::onStatus(BLECharacteristic *pCharacteristic, Status s, uint32_t code) {
+  log_d(">> onStatus: default");
+  log_d("<< onStatus");
+}  // onStatus
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLECharacteristic.h b/libraries/BLE/src/BLECharacteristic.h
index 12ef1ceaa7d..29f105868fd 100644
--- a/libraries/BLE/src/BLECharacteristic.h
+++ b/libraries/BLE/src/BLECharacteristic.h
@@ -7,8 +7,11 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLECHARACTERISTIC_H_
 #define COMPONENTS_CPP_UTILS_BLECHARACTERISTIC_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <string>
 #include <map>
 #include "BLEUUID.h"
@@ -16,7 +19,7 @@
 #include <esp_gap_ble_api.h>
 #include "BLEDescriptor.h"
 #include "BLEValue.h"
-#include "FreeRTOS.h"
+#include "RTOS.h"
 
 class BLEService;
 class BLEDescriptor;
@@ -27,23 +30,23 @@ class BLECharacteristicCallbacks;
  */
 class BLEDescriptorMap {
 public:
-	void setByUUID(const char* uuid, BLEDescriptor* pDescriptor);
-	void setByUUID(BLEUUID uuid, BLEDescriptor* pDescriptor);
-	void setByHandle(uint16_t handle, BLEDescriptor* pDescriptor);
-	BLEDescriptor* getByUUID(const char* uuid);
-	BLEDescriptor* getByUUID(BLEUUID uuid);
-	BLEDescriptor* getByHandle(uint16_t handle);
-	std::string	toString();
-	void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t* param);
-	BLEDescriptor* getFirst();
-	BLEDescriptor* getNext();
+  void setByUUID(const char *uuid, BLEDescriptor *pDescriptor);
+  void setByUUID(BLEUUID uuid, BLEDescriptor *pDescriptor);
+  void setByHandle(uint16_t handle, BLEDescriptor *pDescriptor);
+  BLEDescriptor *getByUUID(const char *uuid);
+  BLEDescriptor *getByUUID(BLEUUID uuid);
+  BLEDescriptor *getByHandle(uint16_t handle);
+  String toString();
+  void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
+  BLEDescriptor *getFirst();
+  BLEDescriptor *getNext();
+
 private:
-	std::map<BLEDescriptor*, std::string> m_uuidMap;
-	std::map<uint16_t, BLEDescriptor*> m_handleMap;
-	std::map<BLEDescriptor*, std::string>::iterator m_iterator;
+  std::map<BLEDescriptor *, String> m_uuidMap;
+  std::map<uint16_t, BLEDescriptor *> m_handleMap;
+  std::map<BLEDescriptor *, String>::iterator m_iterator;
 };
 
-
 /**
  * @brief The model of a %BLE Characteristic.
  *
@@ -52,77 +55,73 @@ class BLEDescriptorMap {
  */
 class BLECharacteristic {
 public:
-	BLECharacteristic(const char* uuid, uint32_t properties = 0);
-	BLECharacteristic(BLEUUID uuid, uint32_t properties = 0);
-	virtual ~BLECharacteristic();
-
-	void           addDescriptor(BLEDescriptor* pDescriptor);
-	BLEDescriptor* getDescriptorByUUID(const char* descriptorUUID);
-	BLEDescriptor* getDescriptorByUUID(BLEUUID descriptorUUID);
-	BLEUUID        getUUID();
-	std::string    getValue();
-	uint8_t*       getData();
-
-	void indicate();
-	void notify(bool is_notification = true);
-	void setBroadcastProperty(bool value);
-	void setCallbacks(BLECharacteristicCallbacks* pCallbacks);
-	void setIndicateProperty(bool value);
-	void setNotifyProperty(bool value);
-	void setReadProperty(bool value);
-	void setValue(uint8_t* data, size_t size);
-	void setValue(std::string value);
-	void setValue(uint16_t& data16);
-	void setValue(uint32_t& data32);
-	void setValue(int& data32);
-	void setValue(float& data32);
-	void setValue(double& data64); 
-	void setWriteProperty(bool value);
-	void setWriteNoResponseProperty(bool value);
-	std::string toString();
-	uint16_t getHandle();
-	void setAccessPermissions(esp_gatt_perm_t perm);
-
-	static const uint32_t PROPERTY_READ      = 1<<0;
-	static const uint32_t PROPERTY_WRITE     = 1<<1;
-	static const uint32_t PROPERTY_NOTIFY    = 1<<2;
-	static const uint32_t PROPERTY_BROADCAST = 1<<3;
-	static const uint32_t PROPERTY_INDICATE  = 1<<4;
-	static const uint32_t PROPERTY_WRITE_NR  = 1<<5;
-
-	static const uint32_t indicationTimeout = 1000;
+  BLECharacteristic(const char *uuid, uint32_t properties = 0);
+  BLECharacteristic(BLEUUID uuid, uint32_t properties = 0);
+  virtual ~BLECharacteristic();
+
+  void addDescriptor(BLEDescriptor *pDescriptor);
+  BLEDescriptor *getDescriptorByUUID(const char *descriptorUUID);
+  BLEDescriptor *getDescriptorByUUID(BLEUUID descriptorUUID);
+  BLEUUID getUUID();
+  String getValue();
+  uint8_t *getData();
+  size_t getLength();
+
+  void indicate();
+  void notify(bool is_notification = true);
+  void setBroadcastProperty(bool value);
+  void setCallbacks(BLECharacteristicCallbacks *pCallbacks);
+  void setIndicateProperty(bool value);
+  void setNotifyProperty(bool value);
+  void setReadProperty(bool value);
+  void setValue(uint8_t *data, size_t size);
+  void setValue(String value);
+  void setValue(uint16_t &data16);
+  void setValue(uint32_t &data32);
+  void setValue(int &data32);
+  void setValue(float &data32);
+  void setValue(double &data64);
+  void setWriteProperty(bool value);
+  void setWriteNoResponseProperty(bool value);
+  String toString();
+  uint16_t getHandle();
+  void setAccessPermissions(esp_gatt_perm_t perm);
+
+  static const uint32_t PROPERTY_READ = 1 << 0;
+  static const uint32_t PROPERTY_WRITE = 1 << 1;
+  static const uint32_t PROPERTY_NOTIFY = 1 << 2;
+  static const uint32_t PROPERTY_BROADCAST = 1 << 3;
+  static const uint32_t PROPERTY_INDICATE = 1 << 4;
+  static const uint32_t PROPERTY_WRITE_NR = 1 << 5;
+
+  static const uint32_t indicationTimeout = 1000;
 
 private:
-
-	friend class BLEServer;
-	friend class BLEService;
-	friend class BLEDescriptor;
-	friend class BLECharacteristicMap;
-
-	BLEUUID                     m_bleUUID;
-	BLEDescriptorMap            m_descriptorMap;
-	uint16_t                    m_handle;
-	esp_gatt_char_prop_t        m_properties;
-	BLECharacteristicCallbacks* m_pCallbacks;
-	BLEService*                 m_pService;
-	BLEValue                    m_value;
-	esp_gatt_perm_t             m_permissions = ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE;
-	bool						m_writeEvt = false; // If we have started a long write, this tells the commit code that we were the target
-
-	void handleGATTServerEvent(
-			esp_gatts_cb_event_t      event,
-			esp_gatt_if_t             gatts_if,
-			esp_ble_gatts_cb_param_t* param);
-
-	void                 executeCreate(BLEService* pService);
-	esp_gatt_char_prop_t getProperties();
-	BLEService*          getService();
-	void                 setHandle(uint16_t handle);
-	FreeRTOS::Semaphore m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt");
-	FreeRTOS::Semaphore m_semaphoreConfEvt   = FreeRTOS::Semaphore("ConfEvt");
-	FreeRTOS::Semaphore m_semaphoreSetValue  = FreeRTOS::Semaphore("SetValue");  
-}; // BLECharacteristic
-
+  friend class BLEServer;
+  friend class BLEService;
+  friend class BLEDescriptor;
+  friend class BLECharacteristicMap;
+
+  BLEUUID m_bleUUID;
+  BLEDescriptorMap m_descriptorMap;
+  uint16_t m_handle;
+  esp_gatt_char_prop_t m_properties;
+  BLECharacteristicCallbacks *m_pCallbacks;
+  BLEService *m_pService;
+  BLEValue m_value;
+  esp_gatt_perm_t m_permissions = ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE;
+  bool m_writeEvt = false;  // If we have started a long write, this tells the commit code that we were the target
+
+  void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
+
+  void executeCreate(BLEService *pService);
+  esp_gatt_char_prop_t getProperties();
+  BLEService *getService();
+  void setHandle(uint16_t handle);
+  FreeRTOS::Semaphore m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt");
+  FreeRTOS::Semaphore m_semaphoreConfEvt = FreeRTOS::Semaphore("ConfEvt");
+  FreeRTOS::Semaphore m_semaphoreSetValue = FreeRTOS::Semaphore("SetValue");
+};  // BLECharacteristic
 
 /**
  * @brief Callbacks that can be associated with a %BLE characteristic to inform of events.
@@ -133,22 +132,58 @@ class BLECharacteristic {
  */
 class BLECharacteristicCallbacks {
 public:
-	typedef enum {
-		SUCCESS_INDICATE,
-		SUCCESS_NOTIFY,
-		ERROR_INDICATE_DISABLED,
-		ERROR_NOTIFY_DISABLED,
-		ERROR_GATT,
-		ERROR_NO_CLIENT,
-		ERROR_INDICATE_TIMEOUT,
-		ERROR_INDICATE_FAILURE
-	}Status;
-
-	virtual ~BLECharacteristicCallbacks();
-	virtual void onRead(BLECharacteristic* pCharacteristic);
-	virtual void onWrite(BLECharacteristic* pCharacteristic);
-	virtual void onNotify(BLECharacteristic* pCharacteristic);
-	virtual void onStatus(BLECharacteristic* pCharacteristic, Status s, uint32_t code);
+  typedef enum {
+    SUCCESS_INDICATE,
+    SUCCESS_NOTIFY,
+    ERROR_INDICATE_DISABLED,
+    ERROR_NOTIFY_DISABLED,
+    ERROR_GATT,
+    ERROR_NO_CLIENT,
+    ERROR_INDICATE_TIMEOUT,
+    ERROR_INDICATE_FAILURE
+  } Status;
+
+  virtual ~BLECharacteristicCallbacks();
+
+  /**
+	 * @brief Callback function to support a read request.
+	 * @param [in] pCharacteristic The characteristic that is the source of the event.
+	 * @param [in] param The BLE GATTS param. Use param->read.
+	 */
+  virtual void onRead(BLECharacteristic *pCharacteristic, esp_ble_gatts_cb_param_t *param);
+  /**
+	 * @brief DEPRECATED! Callback function to support a read request. Called only if onRead(,) is not overridden
+	 * @param [in] pCharacteristic The characteristic that is the source of the event.
+	 */
+  virtual void onRead(BLECharacteristic *pCharacteristic);
+
+  /**
+	 * @brief Callback function to support a write request.
+	 * @param [in] pCharacteristic The characteristic that is the source of the event.
+	 * @param [in] param The BLE GATTS param. Use param->write.
+	 */
+  virtual void onWrite(BLECharacteristic *pCharacteristic, esp_ble_gatts_cb_param_t *param);
+  /**
+	 * @brief DEPRECATED! Callback function to support a write request. Called only if onWrite(,) is not overridden.
+	 * @param [in] pCharacteristic The characteristic that is the source of the event.
+	 */
+  virtual void onWrite(BLECharacteristic *pCharacteristic);
+
+  /**
+	 * @brief Callback function to support a Notify request.
+	 * @param [in] pCharacteristic The characteristic that is the source of the event.
+	 */
+  virtual void onNotify(BLECharacteristic *pCharacteristic);
+
+  /**
+	 * @brief Callback function to support a Notify/Indicate Status report.
+	 * @param [in] pCharacteristic The characteristic that is the source of the event.
+	 * @param [in] s Status of the notification/indication
+	 * @param [in] code Additional code of underlying errors
+	 */
+  virtual void onStatus(BLECharacteristic *pCharacteristic, Status s, uint32_t code);
 };
-#endif /* CONFIG_BT_ENABLED */
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLECHARACTERISTIC_H_ */
diff --git a/libraries/BLE/src/BLECharacteristicMap.cpp b/libraries/BLE/src/BLECharacteristicMap.cpp
index 6e648fc7cdc..6f2c0bb1154 100644
--- a/libraries/BLE/src/BLECharacteristicMap.cpp
+++ b/libraries/BLE/src/BLECharacteristicMap.cpp
@@ -4,8 +4,11 @@
  *  Created on: Jun 22, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <sstream>
 #include <iomanip>
 #include "BLEService.h"
@@ -13,67 +16,65 @@
 #include "esp32-hal-log.h"
 #endif
 
-
 /**
  * @brief Return the characteristic by handle.
  * @param [in] handle The handle to look up the characteristic.
  * @return The characteristic.
  */
-BLECharacteristic* BLECharacteristicMap::getByHandle(uint16_t handle) {
-	return m_handleMap.at(handle);
-} // getByHandle
-
+BLECharacteristic *BLECharacteristicMap::getByHandle(uint16_t handle) {
+  return m_handleMap.at(handle);
+}  // getByHandle
 
 /**
  * @brief Return the characteristic by UUID.
  * @param [in] UUID The UUID to look up the characteristic.
  * @return The characteristic.
  */
-BLECharacteristic* BLECharacteristicMap::getByUUID(const char* uuid) {
-    return getByUUID(BLEUUID(uuid));
+BLECharacteristic *BLECharacteristicMap::getByUUID(const char *uuid) {
+  return getByUUID(BLEUUID(uuid));
 }
 
-
 /**
  * @brief Return the characteristic by UUID.
  * @param [in] UUID The UUID to look up the characteristic.
  * @return The characteristic.
  */
-BLECharacteristic* BLECharacteristicMap::getByUUID(BLEUUID uuid) {
-	for (auto &myPair : m_uuidMap) {
-		if (myPair.first->getUUID().equals(uuid)) {
-			return myPair.first;
-		}
-	}
-	//return m_uuidMap.at(uuid.toString());
-	return nullptr;
-} // getByUUID
-
+BLECharacteristic *BLECharacteristicMap::getByUUID(BLEUUID uuid) {
+  for (auto &myPair : m_uuidMap) {
+    if (myPair.first->getUUID().equals(uuid)) {
+      return myPair.first;
+    }
+  }
+  //return m_uuidMap.at(uuid.toString());
+  return nullptr;
+}  // getByUUID
 
 /**
  * @brief Get the first characteristic in the map.
  * @return The first characteristic in the map.
  */
-BLECharacteristic* BLECharacteristicMap::getFirst() {
-	m_iterator = m_uuidMap.begin();
-	if (m_iterator == m_uuidMap.end()) return nullptr;
-	BLECharacteristic* pRet = m_iterator->first;
-	m_iterator++;
-	return pRet;
-} // getFirst
-
+BLECharacteristic *BLECharacteristicMap::getFirst() {
+  m_iterator = m_uuidMap.begin();
+  if (m_iterator == m_uuidMap.end()) {
+    return nullptr;
+  }
+  BLECharacteristic *pRet = m_iterator->first;
+  m_iterator++;
+  return pRet;
+}  // getFirst
 
 /**
  * @brief Get the next characteristic in the map.
  * @return The next characteristic in the map.
  */
-BLECharacteristic* BLECharacteristicMap::getNext() {
-	if (m_iterator == m_uuidMap.end()) return nullptr;
-	BLECharacteristic* pRet = m_iterator->first;
-	m_iterator++;
-	return pRet;
-} // getNext
-
+BLECharacteristic *BLECharacteristicMap::getNext() {
+  if (m_iterator == m_uuidMap.end()) {
+    return nullptr;
+  }
+  BLECharacteristic *pRet = m_iterator->first;
+  m_iterator++;
+  return pRet;
+}  // getNext
 
 /**
  * @brief Pass the GATT server event onwards to each of the characteristics found in the mapping
@@ -81,13 +82,12 @@ BLECharacteristic* BLECharacteristicMap::getNext() {
  * @param [in] gatts_if
  * @param [in] param
  */
-void BLECharacteristicMap::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t* param) {
-	// Invoke the handler for every Service we have.
-	for (auto& myPair : m_uuidMap) {
-		myPair.first->handleGATTServerEvent(event, gatts_if, param);
-	}
-} // handleGATTServerEvent
-
+void BLECharacteristicMap::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) {
+  // Invoke the handler for every Service we have.
+  for (auto &myPair : m_uuidMap) {
+    myPair.first->handleGATTServerEvent(event, gatts_if, param);
+  }
+}  // handleGATTServerEvent
 
 /**
  * @brief Set the characteristic by handle.
@@ -95,10 +95,9 @@ void BLECharacteristicMap::handleGATTServerEvent(esp_gatts_cb_event_t event, esp
  * @param [in] characteristic The characteristic to cache.
  * @return N/A.
  */
-void BLECharacteristicMap::setByHandle(uint16_t handle, BLECharacteristic* characteristic) {
-	m_handleMap.insert(std::pair<uint16_t, BLECharacteristic*>(handle, characteristic));
-} // setByHandle
-
+void BLECharacteristicMap::setByHandle(uint16_t handle, BLECharacteristic *characteristic) {
+  m_handleMap.insert(std::pair<uint16_t, BLECharacteristic *>(handle, characteristic));
+}  // setByHandle
 
 /**
  * @brief Set the characteristic by UUID.
@@ -106,29 +105,30 @@ void BLECharacteristicMap::setByHandle(uint16_t handle, BLECharacteristic* chara
  * @param [in] characteristic The characteristic to cache.
  * @return N/A.
  */
-void BLECharacteristicMap::setByUUID(BLECharacteristic* pCharacteristic, BLEUUID uuid) {
-	m_uuidMap.insert(std::pair<BLECharacteristic*, std::string>(pCharacteristic, uuid.toString()));
-} // setByUUID
-
+void BLECharacteristicMap::setByUUID(BLECharacteristic *pCharacteristic, BLEUUID uuid) {
+  m_uuidMap.insert(std::pair<BLECharacteristic *, String>(pCharacteristic, uuid.toString()));
+}  // setByUUID
 
 /**
  * @brief Return a string representation of the characteristic map.
  * @return A string representation of the characteristic map.
  */
-std::string BLECharacteristicMap::toString() {
-	std::string res;
-	int count = 0;
-	char hex[5];
-	for (auto &myPair: m_uuidMap) {
-		if (count > 0) {res += "\n";}
-		snprintf(hex, sizeof(hex), "%04x", myPair.first->getHandle());
-		count++;
-		res += "handle: 0x";
-		res += hex;
-		res += ", uuid: " + myPair.first->getUUID().toString();
-	}
-	return res;
-} // toString
-
-
-#endif /* CONFIG_BT_ENABLED */
+String BLECharacteristicMap::toString() {
+  String res;
+  int count = 0;
+  char hex[5];
+  for (auto &myPair : m_uuidMap) {
+    if (count > 0) {
+      res += "\n";
+    }
+    snprintf(hex, sizeof(hex), "%04x", myPair.first->getHandle());
+    count++;
+    res += "handle: 0x";
+    res += hex;
+    res += ", uuid: " + myPair.first->getUUID().toString();
+  }
+  return res;
+}  // toString
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEClient.cpp b/libraries/BLE/src/BLEClient.cpp
index 9d947710e94..29fa0fbc140 100644
--- a/libraries/BLE/src/BLEClient.cpp
+++ b/libraries/BLE/src/BLEClient.cpp
@@ -4,12 +4,16 @@
  *  Created on: Mar 22, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <esp_bt.h>
 #include <esp_bt_main.h>
 #include <esp_gap_ble_api.h>
 #include <esp_gattc_api.h>
+#include <esp_gatt_common_api.h>  // ESP32 BLE
 #include "BLEClient.h"
 #include "BLEUtils.h"
 #include "BLEService.h"
@@ -42,294 +46,328 @@
  */
 
 BLEClient::BLEClient() {
-	m_pClientCallbacks = nullptr;
-	m_conn_id          = ESP_GATT_IF_NONE;
-	m_gattc_if         = ESP_GATT_IF_NONE;
-	m_haveServices     = false;
-	m_isConnected      = false;  // Initially, we are flagged as not connected.
-} // BLEClient
-
+  m_pClientCallbacks = nullptr;
+  m_conn_id = ESP_GATT_IF_NONE;
+  m_gattc_if = ESP_GATT_IF_NONE;
+  m_haveServices = false;
+  m_isConnected = false;  // Initially, we are flagged as not connected.
+}  // BLEClient
 
 /**
  * @brief Destructor.
  */
 BLEClient::~BLEClient() {
-	// We may have allocated service references associated with this client.  Before we are finished
-	// with the client, we must release resources.
-	for (auto &myPair : m_servicesMap) {
-	   delete myPair.second;
-	}
-	m_servicesMap.clear();
-} // ~BLEClient
-
+  // We may have allocated service references associated with this client.  Before we are finished
+  // with the client, we must release resources.
+  for (auto &myPair : m_servicesMap) {
+    delete myPair.second;
+  }
+  m_servicesMap.clear();
+  m_servicesMapByInstID.clear();
+}  // ~BLEClient
 
 /**
  * @brief Clear any existing services.
  *
  */
 void BLEClient::clearServices() {
-	log_v(">> clearServices");
-	// Delete all the services.
-	for (auto &myPair : m_servicesMap) {
-	   delete myPair.second;
-	}
-	m_servicesMap.clear();
-	m_haveServices = false;
-	log_v("<< clearServices");
-} // clearServices
+  log_v(">> clearServices");
+  // Delete all the services.
+  for (auto &myPair : m_servicesMap) {
+    delete myPair.second;
+  }
+  m_servicesMap.clear();
+  m_haveServices = false;
+  log_v("<< clearServices");
+}  // clearServices
+
+/**
+ * Add overloaded function to ease connect to peer device with not public address
+ */
+bool BLEClient::connect(BLEAdvertisedDevice *device) {
+  BLEAddress address = device->getAddress();
+  esp_ble_addr_type_t type = device->getAddressType();
+  return connect(address, type);
+}
 
 /**
  * Add overloaded function to ease connect to peer device with not public address
  */
-bool BLEClient::connect(BLEAdvertisedDevice* device) {
-	BLEAddress address =  device->getAddress();
-	esp_ble_addr_type_t type = device->getAddressType();
-	return connect(address, type);
+bool BLEClient::connectTimeout(BLEAdvertisedDevice *device, uint32_t timeoutMs) {
+  BLEAddress address = device->getAddress();
+  esp_ble_addr_type_t type = device->getAddressType();
+  return connect(address, type, timeoutMs);
 }
 
 /**
  * @brief Connect to the partner (BLE Server).
  * @param [in] address The address of the partner.
+ * @param [in] type The type of the address.
+ * @param [in] timeoutMs The number of milliseconds to wait for the connection to complete.
  * @return True on success.
  */
-bool BLEClient::connect(BLEAddress address, esp_ble_addr_type_t type) {
-	log_v(">> connect(%s)", address.toString().c_str());
-
-// We need the connection handle that we get from registering the application.  We register the app
-// and then block on its completion.  When the event has arrived, we will have the handle.
-	m_appId = BLEDevice::m_appId++;
-	BLEDevice::addPeerDevice(this, true, m_appId);
-	m_semaphoreRegEvt.take("connect");
-
-	// clearServices(); // we dont need to delete services since every client is unique?
-	esp_err_t errRc = ::esp_ble_gattc_app_register(m_appId);
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gattc_app_register: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		BLEDevice::removePeerDevice(m_appId, true);
-		return false;
-	}
-
-	m_semaphoreRegEvt.wait("connect");
-
-	m_peerAddress = address;
-
-	// Perform the open connection request against the target BLE Server.
-	m_semaphoreOpenEvt.take("connect");
-	errRc = ::esp_ble_gattc_open(
-		m_gattc_if,
-		*getPeerAddress().getNative(), // address
-		type,          // Note: This was added on 2018-04-03 when the latest ESP-IDF was detected to have changed the signature.
-		1                              // direct connection <-- maybe needs to be changed in case of direct indirect connection???
-	);
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gattc_open: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		BLEDevice::removePeerDevice(m_appId, true);
-		return false;
-	}
-
-	uint32_t rc = m_semaphoreOpenEvt.wait("connect");   // Wait for the connection to complete.
-	log_v("<< connect(), rc=%d", rc==ESP_GATT_OK);
-	return rc == ESP_GATT_OK;
-} // connect
-
+bool BLEClient::connect(BLEAddress address, esp_ble_addr_type_t type, uint32_t timeoutMs) {
+  log_v(">> connect(%s)", address.toString().c_str());
+
+  // We need the connection handle that we get from registering the application.  We register the app
+  // and then block on its completion.  When the event has arrived, we will have the handle.
+  m_appId = BLEDevice::m_appId++;
+  BLEDevice::addPeerDevice(this, true, m_appId);
+  m_semaphoreRegEvt.take("connect");
+
+  // clearServices(); // we dont need to delete services since every client is unique?
+  esp_err_t errRc = ::esp_ble_gattc_app_register(m_appId);
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gattc_app_register: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    BLEDevice::removePeerDevice(m_appId, true);
+    return false;
+  }
+
+  uint32_t rc = m_semaphoreRegEvt.wait("connect");
+
+  if (rc != ESP_GATT_OK) {
+    // fixes ESP_GATT_NO_RESOURCES error mostly
+    log_e("esp_ble_gattc_app_register_error: rc=%d", rc);
+    BLEDevice::removePeerDevice(m_appId, true);
+    // not sure if this is needed here
+    // esp_ble_gattc_app_unregister(m_gattc_if);
+    // m_gattc_if = ESP_GATT_IF_NONE;
+    return false;
+  }
+
+  m_peerAddress = address;
+
+  // Perform the open connection request against the target BLE Server.
+  m_semaphoreOpenEvt.take("connect");
+  errRc = ::esp_ble_gattc_open(
+    m_gattc_if,
+    *getPeerAddress().getNative(),  // address
+    type,                           // Note: This was added on 2018-04-03 when the latest ESP-IDF was detected to have changed the signature.
+    1                               // direct connection <-- maybe needs to be changed in case of direct indirect connection???
+  );
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gattc_open: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    BLEDevice::removePeerDevice(m_appId, true);
+    return false;
+  }
+
+  bool got_sem = m_semaphoreOpenEvt.timedWait("connect", timeoutMs);  // Wait for the connection to complete.
+  rc = m_semaphoreOpenEvt.value();
+  // check the status of the connection and cleanup in case of failure
+  if (!got_sem || rc != ESP_GATT_OK) {
+    BLEDevice::removePeerDevice(m_appId, true);
+    esp_ble_gattc_app_unregister(m_gattc_if);
+    m_gattc_if = ESP_GATT_IF_NONE;
+  }
+  log_v("<< connect(), rc=%d", rc == ESP_GATT_OK);
+  return rc == ESP_GATT_OK;
+}  // connect
 
 /**
  * @brief Disconnect from the peer.
  * @return N/A.
  */
 void BLEClient::disconnect() {
-	log_v(">> disconnect()");
-	esp_err_t errRc = ::esp_ble_gattc_close(getGattcIf(), getConnId());
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gattc_close: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
-	log_v("<< disconnect()");
-} // disconnect
-
+  log_v(">> disconnect()");
+  esp_err_t errRc = ::esp_ble_gattc_close(getGattcIf(), getConnId());
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gattc_close: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return;
+  }
+  log_v("<< disconnect()");
+}  // disconnect
 
 /**
  * @brief Handle GATT Client events
  */
-void BLEClient::gattClientEventHandler(
-	esp_gattc_cb_event_t      event,
-	esp_gatt_if_t             gattc_if,
-	esp_ble_gattc_cb_param_t* evtParam) {
-
-	log_d("gattClientEventHandler [esp_gatt_if: %d] ... %s",
-		gattc_if, BLEUtils::gattClientEventTypeToString(event).c_str());
-
-	// Execute handler code based on the type of event received.
-	switch(event) {
-
-		case ESP_GATTC_SRVC_CHG_EVT:
-			log_i("SERVICE CHANGED");
-			break;
-
-		case ESP_GATTC_CLOSE_EVT: {
-				// esp_ble_gattc_app_unregister(m_appId);
-				// BLEDevice::removePeerDevice(m_gattc_if, true);
-			break;
-		}
-
-		//
-		// ESP_GATTC_DISCONNECT_EVT
-		//
-		// disconnect:
-		// - esp_gatt_status_t status
-		// - uint16_t          conn_id
-		// - esp_bd_addr_t     remote_bda
-		case ESP_GATTC_DISCONNECT_EVT: {
-				if (evtParam->disconnect.conn_id != getConnId()) break;
-				// If we receive a disconnect event, set the class flag that indicates that we are
-				// no longer connected.
-				if (m_isConnected && m_pClientCallbacks != nullptr) {
-					m_pClientCallbacks->onDisconnect(this);
-				}
-				m_isConnected = false;
-				esp_ble_gattc_app_unregister(m_gattc_if);
-				m_semaphoreOpenEvt.give(ESP_GATT_IF_NONE);
-				m_semaphoreRssiCmplEvt.give();
-				m_semaphoreSearchCmplEvt.give(1);
-				BLEDevice::removePeerDevice(m_appId, true);
-				break;
-		} // ESP_GATTC_DISCONNECT_EVT
-
-		//
-		// ESP_GATTC_OPEN_EVT
-		//
-		// open:
-		// - esp_gatt_status_t status
-		// - uint16_t          conn_id
-		// - esp_bd_addr_t     remote_bda
-		//
-		case ESP_GATTC_OPEN_EVT: {
-			m_conn_id = evtParam->open.conn_id;
-			if (evtParam->open.status == ESP_GATT_OK) {
-				m_isConnected = true;   // Flag us as connected.
-				if (m_pClientCallbacks != nullptr) {
-					m_pClientCallbacks->onConnect(this);
-				}
-			} else {
-				log_e("Failed to connect, status=%s", GeneralUtils::errorToString(evtParam->open.status));
-			}
-			m_semaphoreOpenEvt.give(evtParam->open.status);
-			break;
-		} // ESP_GATTC_OPEN_EVT
-
-
-		//
-		// ESP_GATTC_REG_EVT
-		//
-		// reg:
-		// esp_gatt_status_t status
-		// uint16_t          app_id
-		//
-		case ESP_GATTC_REG_EVT: {
-			m_gattc_if = gattc_if;
-			m_semaphoreRegEvt.give();
-			break;
-		} // ESP_GATTC_REG_EVT
-
-		case ESP_GATTC_CFG_MTU_EVT:
-			if (evtParam->cfg_mtu.conn_id != getConnId()) break;
-			if(evtParam->cfg_mtu.status != ESP_GATT_OK) {
-				log_e("Config mtu failed");
-			}
-			m_mtu = evtParam->cfg_mtu.mtu;
-			break;
-
-		case ESP_GATTC_CONNECT_EVT: {
-			if (evtParam->connect.conn_id != getConnId()) break;
-			BLEDevice::updatePeerDevice(this, true, m_appId);
-			esp_err_t errRc = esp_ble_gattc_send_mtu_req(gattc_if, evtParam->connect.conn_id);
-			if (errRc != ESP_OK) {
-				log_e("esp_ble_gattc_send_mtu_req: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			}
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-			if(BLEDevice::m_securityLevel){
-				esp_ble_set_encryption(evtParam->connect.remote_bda, BLEDevice::m_securityLevel);
-			}
-#endif	// CONFIG_BLE_SMP_ENABLE
-			break;
-		} // ESP_GATTC_CONNECT_EVT
-
-		//
-		// ESP_GATTC_SEARCH_CMPL_EVT
-		//
-		// search_cmpl:
-		// - esp_gatt_status_t status
-		// - uint16_t          conn_id
-		//
-		case ESP_GATTC_SEARCH_CMPL_EVT: {
-			if (evtParam->search_cmpl.conn_id != getConnId()) break;
-			esp_ble_gattc_cb_param_t* p_data = (esp_ble_gattc_cb_param_t*)evtParam;
-			if (p_data->search_cmpl.status != ESP_GATT_OK){
-				log_e("search service failed, error status = %x", p_data->search_cmpl.status);
-				break;
-			}
+void BLEClient::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) {
+
+  log_d("gattClientEventHandler [esp_gatt_if: %d] ... %s", gattc_if, BLEUtils::gattClientEventTypeToString(event).c_str());
+
+  // it is possible to receive events from other connections while waiting for registration
+  if (m_gattc_if == ESP_GATT_IF_NONE && event != ESP_GATTC_REG_EVT) {
+    return;
+  }
+
+  // Execute handler code based on the type of event received.
+  switch (event) {
+
+    case ESP_GATTC_SRVC_CHG_EVT: log_i("SERVICE CHANGED"); break;
+
+    case ESP_GATTC_CLOSE_EVT:
+    {
+      // esp_ble_gattc_app_unregister(m_appId);
+      // BLEDevice::removePeerDevice(m_gattc_if, true);
+      break;
+    }
+
+    //
+    // ESP_GATTC_DISCONNECT_EVT
+    //
+    // disconnect:
+    // - esp_gatt_status_t status
+    // - uint16_t          conn_id
+    // - esp_bd_addr_t     remote_bda
+    case ESP_GATTC_DISCONNECT_EVT:
+    {
+      if (evtParam->disconnect.conn_id != getConnId()) {
+        break;
+      }
+      // If we receive a disconnect event, set the class flag that indicates that we are
+      // no longer connected.
+      bool m_wasConnected = m_isConnected;
+      m_isConnected = false;
+      esp_ble_gattc_app_unregister(m_gattc_if);
+      m_gattc_if = ESP_GATT_IF_NONE;
+      m_semaphoreOpenEvt.give(ESP_GATT_IF_NONE);
+      m_semaphoreRssiCmplEvt.give();
+      m_semaphoreSearchCmplEvt.give(1);
+      BLEDevice::removePeerDevice(m_appId, true);
+      if (m_wasConnected && m_pClientCallbacks != nullptr) {
+        m_pClientCallbacks->onDisconnect(this);
+      }
+      break;
+    }  // ESP_GATTC_DISCONNECT_EVT
+
+    //
+    // ESP_GATTC_OPEN_EVT
+    //
+    // open:
+    // - esp_gatt_status_t status
+    // - uint16_t          conn_id
+    // - esp_bd_addr_t     remote_bda
+    //
+    case ESP_GATTC_OPEN_EVT:
+    {
+      m_conn_id = evtParam->open.conn_id;
+      if (evtParam->open.status == ESP_GATT_OK) {
+        m_isConnected = true;  // Flag us as connected.
+        if (m_pClientCallbacks != nullptr) {
+          m_pClientCallbacks->onConnect(this);
+        }
+      } else {
+        log_e("Failed to connect, status=%s", GeneralUtils::errorToString(evtParam->open.status));
+      }
+      m_semaphoreOpenEvt.give(evtParam->open.status);
+      break;
+    }  // ESP_GATTC_OPEN_EVT
+
+    //
+    // ESP_GATTC_REG_EVT
+    //
+    // reg:
+    // esp_gatt_status_t status
+    // uint16_t          app_id
+    //
+    case ESP_GATTC_REG_EVT:
+    {
+      m_gattc_if = gattc_if;
+      // pass on the registration status result, in case of failure
+      m_semaphoreRegEvt.give(evtParam->reg.status);
+      break;
+    }  // ESP_GATTC_REG_EVT
+
+    case ESP_GATTC_CFG_MTU_EVT:
+      if (evtParam->cfg_mtu.conn_id != getConnId()) {
+        break;
+      }
+      if (evtParam->cfg_mtu.status != ESP_GATT_OK) {
+        log_e("Config mtu failed");
+      }
+      m_mtu = evtParam->cfg_mtu.mtu;
+      break;
+
+    case ESP_GATTC_CONNECT_EVT:
+    {
+      if (evtParam->connect.conn_id != getConnId()) {
+        break;
+      }
+      BLEDevice::updatePeerDevice(this, true, m_appId);
+      esp_err_t errRc = esp_ble_gattc_send_mtu_req(gattc_if, evtParam->connect.conn_id);
+      if (errRc != ESP_OK) {
+        log_e("esp_ble_gattc_send_mtu_req: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      }
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+      if (BLEDevice::m_securityLevel) {
+        esp_ble_set_encryption(evtParam->connect.remote_bda, BLEDevice::m_securityLevel);
+      }
+#endif  // CONFIG_BLE_SMP_ENABLE
+      break;
+    }  // ESP_GATTC_CONNECT_EVT
+
+    //
+    // ESP_GATTC_SEARCH_CMPL_EVT
+    //
+    // search_cmpl:
+    // - esp_gatt_status_t status
+    // - uint16_t          conn_id
+    //
+    case ESP_GATTC_SEARCH_CMPL_EVT:
+    {
+      if (evtParam->search_cmpl.conn_id != getConnId()) {
+        break;
+      }
+      esp_ble_gattc_cb_param_t *p_data = (esp_ble_gattc_cb_param_t *)evtParam;
+      if (p_data->search_cmpl.status != ESP_GATT_OK) {
+        log_e("search service failed, error status = %x", p_data->search_cmpl.status);
+        break;
+      }
 #ifndef ARDUINO_ARCH_ESP32
-// commented out just for now to keep backward compatibility			
-			// if(p_data->search_cmpl.searched_service_source == ESP_GATT_SERVICE_FROM_REMOTE_DEVICE) {
-			// 	log_i("Get service information from remote device");
-			// } else if (p_data->search_cmpl.searched_service_source == ESP_GATT_SERVICE_FROM_NVS_FLASH) {
-			// 	log_i("Get service information from flash");
-			// } else {
-			// 	log_i("unknown service source");
-			// }
+// commented out just for now to keep backward compatibility
+// if(p_data->search_cmpl.searched_service_source == ESP_GATT_SERVICE_FROM_REMOTE_DEVICE) {
+//   log_i("Get service information from remote device");
+// } else if (p_data->search_cmpl.searched_service_source == ESP_GATT_SERVICE_FROM_NVS_FLASH) {
+//   log_i("Get service information from flash");
+// } else {
+//   log_i("unknown service source");
+// }
 #endif
-			m_semaphoreSearchCmplEvt.give(0);
-			break;
-		} // ESP_GATTC_SEARCH_CMPL_EVT
-
-
-		//
-		// ESP_GATTC_SEARCH_RES_EVT
-		//
-		// search_res:
-		// - uint16_t      conn_id
-		// - uint16_t      start_handle
-		// - uint16_t      end_handle
-		// - esp_gatt_id_t srvc_id
-		//
-		case ESP_GATTC_SEARCH_RES_EVT: {
-			if (evtParam->search_res.conn_id != getConnId()) break;
-			BLEUUID uuid = BLEUUID(evtParam->search_res.srvc_id);
-			BLERemoteService* pRemoteService = new BLERemoteService(
-				evtParam->search_res.srvc_id,
-				this,
-				evtParam->search_res.start_handle,
-				evtParam->search_res.end_handle
-			);
-			m_servicesMap.insert(std::pair<std::string, BLERemoteService*>(uuid.toString(), pRemoteService));
-			m_servicesMapByInstID.insert(std::pair<BLERemoteService *, uint16_t>(pRemoteService, evtParam->search_res.srvc_id.inst_id));
-			break;
-		} // ESP_GATTC_SEARCH_RES_EVT
-
-
-		default: {
-			break;
-		}
-	} // Switch
-
-	// Pass the request on to all services.
-	for (auto &myPair : m_servicesMap) {
-	   myPair.second->gattClientEventHandler(event, gattc_if, evtParam);
-	}
-
-} // gattClientEventHandler
-
+      m_semaphoreSearchCmplEvt.give(0);
+      break;
+    }  // ESP_GATTC_SEARCH_CMPL_EVT
+
+    //
+    // ESP_GATTC_SEARCH_RES_EVT
+    //
+    // search_res:
+    // - uint16_t      conn_id
+    // - uint16_t      start_handle
+    // - uint16_t      end_handle
+    // - esp_gatt_id_t srvc_id
+    //
+    case ESP_GATTC_SEARCH_RES_EVT:
+    {
+      if (evtParam->search_res.conn_id != getConnId()) {
+        break;
+      }
+      BLEUUID uuid = BLEUUID(evtParam->search_res.srvc_id);
+      BLERemoteService *pRemoteService =
+        new BLERemoteService(evtParam->search_res.srvc_id, this, evtParam->search_res.start_handle, evtParam->search_res.end_handle);
+      m_servicesMap.insert(std::pair<std::string, BLERemoteService *>(uuid.toString().c_str(), pRemoteService));
+      m_servicesMapByInstID.insert(std::pair<BLERemoteService *, uint16_t>(pRemoteService, evtParam->search_res.srvc_id.inst_id));
+      break;
+    }  // ESP_GATTC_SEARCH_RES_EVT
+
+    default:
+    {
+      break;
+    }
+  }  // Switch
+
+  // Pass the request on to all services.
+  for (auto &myPair : m_servicesMap) {
+    myPair.second->gattClientEventHandler(event, gattc_if, evtParam);
+  }
+
+}  // gattClientEventHandler
 
 uint16_t BLEClient::getConnId() {
-	return m_conn_id;
-} // getConnId
-
-
+  return m_conn_id;
+}  // getConnId
 
 esp_gatt_if_t BLEClient::getGattcIf() {
-	return m_gattc_if;
-} // getGattcIf
-
+  return m_gattc_if;
+}  // getGattcIf
 
 /**
  * @brief Retrieve the address of the peer.
@@ -337,44 +375,41 @@ esp_gatt_if_t BLEClient::getGattcIf() {
  * Returns the Bluetooth device address of the %BLE peer to which this client is connected.
  */
 BLEAddress BLEClient::getPeerAddress() {
-	return m_peerAddress;
-} // getAddress
-
+  return m_peerAddress;
+}  // getAddress
 
 /**
  * @brief Ask the BLE server for the RSSI value.
  * @return The RSSI value.
  */
 int BLEClient::getRssi() {
-	log_v(">> getRssi()");
-	if (!isConnected()) {
-		log_v("<< getRssi(): Not connected");
-		return 0;
-	}
-	// We make the API call to read the RSSI value which is an asynchronous operation.  We expect to receive
-	// an ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT to indicate completion.
-	//
-	m_semaphoreRssiCmplEvt.take("getRssi");
-	esp_err_t rc = ::esp_ble_gap_read_rssi(*getPeerAddress().getNative());
-	if (rc != ESP_OK) {
-		log_e("<< getRssi: esp_ble_gap_read_rssi: rc=%d %s", rc, GeneralUtils::errorToString(rc));
-		return 0;
-	}
-	int rssiValue = m_semaphoreRssiCmplEvt.wait("getRssi");
-	log_v("<< getRssi(): %d", rssiValue);
-	return rssiValue;
-} // getRssi
-
+  log_v(">> getRssi()");
+  if (!isConnected()) {
+    log_v("<< getRssi(): Not connected");
+    return 0;
+  }
+  // We make the API call to read the RSSI value which is an asynchronous operation.  We expect to receive
+  // an ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT to indicate completion.
+  //
+  m_semaphoreRssiCmplEvt.take("getRssi");
+  esp_err_t rc = ::esp_ble_gap_read_rssi(*getPeerAddress().getNative());
+  if (rc != ESP_OK) {
+    log_e("<< getRssi: esp_ble_gap_read_rssi: rc=%d %s", rc, GeneralUtils::errorToString(rc));
+    return 0;
+  }
+  int rssiValue = m_semaphoreRssiCmplEvt.wait("getRssi");
+  log_v("<< getRssi(): %d", rssiValue);
+  return rssiValue;
+}  // getRssi
 
 /**
  * @brief Get the service BLE Remote Service instance corresponding to the uuid.
  * @param [in] uuid The UUID of the service being sought.
  * @return A reference to the Service or nullptr if don't know about it.
  */
-BLERemoteService* BLEClient::getService(const char* uuid) {
-    return getService(BLEUUID(uuid));
-} // getService
-
+BLERemoteService *BLEClient::getService(const char *uuid) {
+  return getService(BLEUUID(uuid));
+}  // getService
 
 /**
  * @brief Get the service object corresponding to the uuid.
@@ -382,28 +417,27 @@ BLERemoteService* BLEClient::getService(const char* uuid) {
  * @return A reference to the Service or nullptr if don't know about it.
  * @throws BLEUuidNotFound
  */
-BLERemoteService* BLEClient::getService(BLEUUID uuid) {
-	log_v(">> getService: uuid: %s", uuid.toString().c_str());
-// Design
-// ------
-// We wish to retrieve the service given its UUID.  It is possible that we have not yet asked the
-// device what services it has in which case we have nothing to match against.  If we have not
-// asked the device about its services, then we do that now.  Once we get the results we can then
-// examine the services map to see if it has the service we are looking for.
-	if (!m_haveServices) {
-		getServices();
-	}
-	std::string uuidStr = uuid.toString();
-	for (auto &myPair : m_servicesMap) {
-		if (myPair.first == uuidStr) {
-			log_v("<< getService: found the service with uuid: %s", uuid.toString().c_str());
-			return myPair.second;
-		}
-	} // End of each of the services.
-	log_v("<< getService: not found");
-	return nullptr;
-} // getService
-
+BLERemoteService *BLEClient::getService(BLEUUID uuid) {
+  log_v(">> getService: uuid: %s", uuid.toString().c_str());
+  // Design
+  // ------
+  // We wish to retrieve the service given its UUID.  It is possible that we have not yet asked the
+  // device what services it has in which case we have nothing to match against.  If we have not
+  // asked the device about its services, then we do that now.  Once we get the results we can then
+  // examine the services map to see if it has the service we are looking for.
+  if (!m_haveServices) {
+    getServices();
+  }
+  std::string uuidStr = uuid.toString().c_str();
+  for (auto &myPair : m_servicesMap) {
+    if (myPair.first == uuidStr) {
+      log_v("<< getService: found the service with uuid: %s", uuid.toString().c_str());
+      return myPair.second;
+    }
+  }  // End of each of the services.
+  log_v("<< getService: not found");
+  return nullptr;
+}  // getService
 
 /**
  * @brief Ask the remote %BLE server for its services.
@@ -411,35 +445,33 @@ BLERemoteService* BLEClient::getService(BLEUUID uuid) {
  * services and wait until we have received them all.
  * @return N/A
  */
-std::map<std::string, BLERemoteService*>* BLEClient::getServices() {
-/*
+std::map<std::string, BLERemoteService *> *BLEClient::getServices() {
+  /*
  * Design
  * ------
  * We invoke esp_ble_gattc_search_service.  This will request a list of the service exposed by the
  * peer BLE partner to be returned as events.  Each event will be an an instance of ESP_GATTC_SEARCH_RES_EVT
  * and will culminate with an ESP_GATTC_SEARCH_CMPL_EVT when all have been received.
  */
-	log_v(">> getServices");
-// TODO implement retrieving services from cache
-	clearServices(); // Clear any services that may exist.
-
-	esp_err_t errRc = esp_ble_gattc_search_service(
-		getGattcIf(),
-		getConnId(),
-		NULL            // Filter UUID
-	);
-
-	m_semaphoreSearchCmplEvt.take("getServices");
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gattc_search_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return &m_servicesMap;
-	}
-	// If sucessfull, remember that we now have services.
-	m_haveServices = (m_semaphoreSearchCmplEvt.wait("getServices") == 0);
-	log_v("<< getServices");
-	return &m_servicesMap;
-} // getServices
-
+  log_v(">> getServices");
+  // TODO implement retrieving services from cache
+  clearServices();  // Clear any services that may exist.
+
+  esp_err_t errRc = esp_ble_gattc_search_service(
+    getGattcIf(), getConnId(),
+    NULL  // Filter UUID
+  );
+
+  m_semaphoreSearchCmplEvt.take("getServices");
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gattc_search_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return &m_servicesMap;
+  }
+  // If successful, remember that we now have services.
+  m_haveServices = (m_semaphoreSearchCmplEvt.wait("getServices") == 0);
+  log_v("<< getServices");
+  return &m_servicesMap;
+}  // getServices
 
 /**
  * @brief Get the value of a specific characteristic associated with a specific service.
@@ -447,13 +479,12 @@ std::map<std::string, BLERemoteService*>* BLEClient::getServices() {
  * @param [in] characteristicUUID The characteristic whose value we wish to read.
  * @throws BLEUuidNotFound
  */
-std::string BLEClient::getValue(BLEUUID serviceUUID, BLEUUID characteristicUUID) {
-	log_v(">> getValue: serviceUUID: %s, characteristicUUID: %s", serviceUUID.toString().c_str(), characteristicUUID.toString().c_str());
-	std::string ret = getService(serviceUUID)->getCharacteristic(characteristicUUID)->readValue();
-	log_v("<<getValue");
-	return ret;
-} // getValue
-
+String BLEClient::getValue(BLEUUID serviceUUID, BLEUUID characteristicUUID) {
+  log_v(">> getValue: serviceUUID: %s, characteristicUUID: %s", serviceUUID.toString().c_str(), characteristicUUID.toString().c_str());
+  String ret = getService(serviceUUID)->getCharacteristic(characteristicUUID)->readValue();
+  log_v("<<getValue");
+  return ret;
+}  // getValue
 
 /**
  * @brief Handle a received GAP event.
@@ -461,48 +492,41 @@ std::string BLEClient::getValue(BLEUUID serviceUUID, BLEUUID characteristicUUID)
  * @param [in] event
  * @param [in] param
  */
-void BLEClient::handleGAPEvent(
-		esp_gap_ble_cb_event_t  event,
-		esp_ble_gap_cb_param_t* param) {
-	log_d("BLEClient ... handling GAP event!");
-	switch (event) {
-		//
-		// ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT
-		//
-		// read_rssi_cmpl
-		// - esp_bt_status_t status
-		// - int8_t rssi
-		// - esp_bd_addr_t remote_addr
-		//
-		case ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT: {
-			m_semaphoreRssiCmplEvt.give((uint32_t) param->read_rssi_cmpl.rssi);
-			break;
-		} // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT
-
-		default:
-			break;
-	}
-} // handleGAPEvent
-
+void BLEClient::handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) {
+  log_d("BLEClient ... handling GAP event!");
+  switch (event) {
+    //
+    // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT
+    //
+    // read_rssi_cmpl
+    // - esp_bt_status_t status
+    // - int8_t rssi
+    // - esp_bd_addr_t remote_addr
+    //
+    case ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT:
+    {
+      m_semaphoreRssiCmplEvt.give((uint32_t)param->read_rssi_cmpl.rssi);
+      break;
+    }  // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT
+
+    default: break;
+  }
+}  // handleGAPEvent
 
 /**
  * @brief Are we connected to a partner?
  * @return True if we are connected and false if we are not connected.
  */
 bool BLEClient::isConnected() {
-	return m_isConnected;
-} // isConnected
-
-
-
+  return m_isConnected;
+}  // isConnected
 
 /**
  * @brief Set the callbacks that will be invoked.
  */
-void BLEClient::setClientCallbacks(BLEClientCallbacks* pClientCallbacks) {
-	m_pClientCallbacks = pClientCallbacks;
-} // setClientCallbacks
-
+void BLEClient::setClientCallbacks(BLEClientCallbacks *pClientCallbacks) {
+  m_pClientCallbacks = pClientCallbacks;
+}  // setClientCallbacks
 
 /**
  * @brief Set the value of a specific characteristic associated with a specific service.
@@ -510,29 +534,53 @@ void BLEClient::setClientCallbacks(BLEClientCallbacks* pClientCallbacks) {
  * @param [in] characteristicUUID The characteristic whose value we wish to write.
  * @throws BLEUuidNotFound
  */
-void BLEClient::setValue(BLEUUID serviceUUID, BLEUUID characteristicUUID, std::string value) {
-	log_v(">> setValue: serviceUUID: %s, characteristicUUID: %s", serviceUUID.toString().c_str(), characteristicUUID.toString().c_str());
-	getService(serviceUUID)->getCharacteristic(characteristicUUID)->writeValue(value);
-	log_v("<< setValue");
-} // setValue
+void BLEClient::setValue(BLEUUID serviceUUID, BLEUUID characteristicUUID, String value) {
+  log_v(">> setValue: serviceUUID: %s, characteristicUUID: %s", serviceUUID.toString().c_str(), characteristicUUID.toString().c_str());
+  getService(serviceUUID)->getCharacteristic(characteristicUUID)->writeValue(value);
+  log_v("<< setValue");
+}  // setValue
 
 uint16_t BLEClient::getMTU() {
-	return m_mtu;
+  return m_mtu;
+}
+
+/**
+  @brief Set the local and remote MTU size.
+         Should be called once after client connects if MTU size needs to be changed.
+  @return bool indicating if MTU was successfully set locally and on remote.
+*/
+bool BLEClient::setMTU(uint16_t mtu) {
+  esp_err_t err = esp_ble_gatt_set_local_mtu(mtu);  //First must set local MTU value.
+  if (err == ESP_OK) {
+    err = esp_ble_gattc_send_mtu_req(m_gattc_if, m_conn_id);  //Once local is set successfully set remote size
+    if (err != ESP_OK) {
+      log_e("Error setting send MTU request MTU: %d err=%d", mtu, err);
+      return false;
+    }
+  } else {
+    log_e("can't set local mtu value: %d", mtu);
+    return false;
+  }
+  log_v("<< setLocalMTU");
+
+  m_mtu = mtu;  //successfully changed
+
+  return true;
 }
 
 /**
  * @brief Return a string representation of this client.
  * @return A string representation of this client.
  */
-std::string BLEClient::toString() {
-	std::string res = "peer address: " + m_peerAddress.toString();
-	res += "\nServices:\n";
-	for (auto &myPair : m_servicesMap) {
-		res += myPair.second->toString() + "\n";
-	  // myPair.second is the value
-	}
-	return res;
-} // toString
-
-
-#endif // CONFIG_BT_ENABLED
+String BLEClient::toString() {
+  String res = "peer address: " + m_peerAddress.toString();
+  res += "\nServices:\n";
+  for (auto &myPair : m_servicesMap) {
+    res += myPair.second->toString() + "\n";
+    // myPair.second is the value
+  }
+  return res;
+}  // toString
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEClient.h b/libraries/BLE/src/BLEClient.h
index 75a288e4329..ddb932fcd95 100644
--- a/libraries/BLE/src/BLEClient.h
+++ b/libraries/BLE/src/BLEClient.h
@@ -8,8 +8,11 @@
 #ifndef MAIN_BLEDEVICE_H_
 #define MAIN_BLEDEVICE_H_
 
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include <esp_gattc_api.h>
 #include <string.h>
@@ -30,74 +33,71 @@ class BLEAdvertisedDevice;
  */
 class BLEClient {
 public:
-	BLEClient();
-	~BLEClient();
+  BLEClient();
+  ~BLEClient();
 
-	bool 									   connect(BLEAdvertisedDevice* device);
-	bool                                       connect(BLEAddress address, esp_ble_addr_type_t type = BLE_ADDR_TYPE_PUBLIC);   // Connect to the remote BLE Server
-	void                                       disconnect();                  // Disconnect from the remote BLE Server
-	BLEAddress                                 getPeerAddress();              // Get the address of the remote BLE Server
-	int                                        getRssi();                     // Get the RSSI of the remote BLE Server
-	std::map<std::string, BLERemoteService*>*  getServices();                 // Get a map of the services offered by the remote BLE Server
-	BLERemoteService*                          getService(const char* uuid);  // Get a reference to a specified service offered by the remote BLE server.
-	BLERemoteService*                          getService(BLEUUID uuid);      // Get a reference to a specified service offered by the remote BLE server.
-	std::string                                getValue(BLEUUID serviceUUID, BLEUUID characteristicUUID);   // Get the value of a given characteristic at a given service.
+  bool connect(BLEAdvertisedDevice *device);
+  bool connectTimeout(BLEAdvertisedDevice *device, uint32_t timeoutMS = portMAX_DELAY);
+  bool connect(BLEAddress address, esp_ble_addr_type_t type = BLE_ADDR_TYPE_PUBLIC, uint32_t timeoutMS = portMAX_DELAY);  // Connect to the remote BLE Server
+  void disconnect();                                                 // Disconnect from the remote BLE Server
+  BLEAddress getPeerAddress();                                       // Get the address of the remote BLE Server
+  int getRssi();                                                     // Get the RSSI of the remote BLE Server
+  std::map<std::string, BLERemoteService *> *getServices();          // Get a map of the services offered by the remote BLE Server
+  BLERemoteService *getService(const char *uuid);                    // Get a reference to a specified service offered by the remote BLE server.
+  BLERemoteService *getService(BLEUUID uuid);                        // Get a reference to a specified service offered by the remote BLE server.
+  String getValue(BLEUUID serviceUUID, BLEUUID characteristicUUID);  // Get the value of a given characteristic at a given service.
 
+  void handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param);
 
-	void                                       handleGAPEvent(
-		                                            esp_gap_ble_cb_event_t  event,
-                                                esp_ble_gap_cb_param_t* param);
+  bool isConnected();  // Return true if we are connected.
 
-	bool                                       isConnected();                 // Return true if we are connected.
+  void setClientCallbacks(BLEClientCallbacks *pClientCallbacks);
+  void setValue(BLEUUID serviceUUID, BLEUUID characteristicUUID, String value);  // Set the value of a given characteristic at a given service.
 
-	void                                       setClientCallbacks(BLEClientCallbacks *pClientCallbacks);
-	void                                       setValue(BLEUUID serviceUUID, BLEUUID characteristicUUID, std::string value);   // Set the value of a given characteristic at a given service.
+  String toString();  // Return a string representation of this client.
+  uint16_t getConnId();
+  esp_gatt_if_t getGattcIf();
+  uint16_t getMTU();
+  bool setMTU(uint16_t mtu);
 
-	std::string                                toString();                    // Return a string representation of this client.
-	uint16_t                                   getConnId();
-	esp_gatt_if_t                              getGattcIf();
-	uint16_t								   getMTU();
+  uint16_t m_appId;
 
-uint16_t m_appId;
 private:
-	friend class BLEDevice;
-	friend class BLERemoteService;
-	friend class BLERemoteCharacteristic;
-	friend class BLERemoteDescriptor;
-
-	void                                       gattClientEventHandler(
-		esp_gattc_cb_event_t event,
-		esp_gatt_if_t gattc_if,
-		esp_ble_gattc_cb_param_t* param);
-
-	BLEAddress    m_peerAddress = BLEAddress((uint8_t*)"\0\0\0\0\0\0");   // The BD address of the remote server.
-	uint16_t      m_conn_id;
-//	int           m_deviceType;
-	esp_gatt_if_t m_gattc_if;
-	bool          m_haveServices = false;    // Have we previously obtain the set of services from the remote server.
-	bool          m_isConnected = false;     // Are we currently connected.
-
-	BLEClientCallbacks* m_pClientCallbacks;
-	FreeRTOS::Semaphore m_semaphoreRegEvt        = FreeRTOS::Semaphore("RegEvt");
-	FreeRTOS::Semaphore m_semaphoreOpenEvt       = FreeRTOS::Semaphore("OpenEvt");
-	FreeRTOS::Semaphore m_semaphoreSearchCmplEvt = FreeRTOS::Semaphore("SearchCmplEvt");
-	FreeRTOS::Semaphore m_semaphoreRssiCmplEvt   = FreeRTOS::Semaphore("RssiCmplEvt");
-	std::map<std::string, BLERemoteService*> m_servicesMap;
-	std::map<BLERemoteService*, uint16_t> m_servicesMapByInstID;
-	void clearServices();   // Clear any existing services.
-	uint16_t m_mtu = 23;
-}; // class BLEDevice
-
+  friend class BLEDevice;
+  friend class BLERemoteService;
+  friend class BLERemoteCharacteristic;
+  friend class BLERemoteDescriptor;
+
+  void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *param);
+
+  BLEAddress m_peerAddress = BLEAddress((uint8_t *)"\0\0\0\0\0\0");  // The BD address of the remote server.
+  uint16_t m_conn_id;
+  //  int           m_deviceType;
+  esp_gatt_if_t m_gattc_if;
+  bool m_haveServices = false;  // Have we previously obtain the set of services from the remote server.
+  bool m_isConnected = false;   // Are we currently connected.
+
+  BLEClientCallbacks *m_pClientCallbacks;
+  FreeRTOS::Semaphore m_semaphoreRegEvt = FreeRTOS::Semaphore("RegEvt");
+  FreeRTOS::Semaphore m_semaphoreOpenEvt = FreeRTOS::Semaphore("OpenEvt");
+  FreeRTOS::Semaphore m_semaphoreSearchCmplEvt = FreeRTOS::Semaphore("SearchCmplEvt");
+  FreeRTOS::Semaphore m_semaphoreRssiCmplEvt = FreeRTOS::Semaphore("RssiCmplEvt");
+  std::map<std::string, BLERemoteService *> m_servicesMap;
+  std::map<BLERemoteService *, uint16_t> m_servicesMapByInstID;
+  void clearServices();  // Clear any existing services.
+  uint16_t m_mtu = 23;
+};  // class BLEDevice
 
 /**
  * @brief Callbacks associated with a %BLE client.
  */
 class BLEClientCallbacks {
 public:
-	virtual ~BLEClientCallbacks() {};
-	virtual void onConnect(BLEClient *pClient) = 0;
-	virtual void onDisconnect(BLEClient *pClient) = 0;
+  virtual ~BLEClientCallbacks(){};
+  virtual void onConnect(BLEClient *pClient) = 0;
+  virtual void onDisconnect(BLEClient *pClient) = 0;
 };
 
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* MAIN_BLEDEVICE_H_ */
diff --git a/libraries/BLE/src/BLEDescriptor.cpp b/libraries/BLE/src/BLEDescriptor.cpp
index 96b2de87c95..69a93e57201 100644
--- a/libraries/BLE/src/BLEDescriptor.cpp
+++ b/libraries/BLE/src/BLEDescriptor.cpp
@@ -4,8 +4,11 @@
  *  Created on: Jun 22, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <sstream>
 #include <string.h>
 #include <iomanip>
@@ -19,104 +22,90 @@
 
 #define NULL_HANDLE (0xffff)
 
-
 /**
  * @brief BLEDescriptor constructor.
  */
-BLEDescriptor::BLEDescriptor(const char* uuid, uint16_t len) : BLEDescriptor(BLEUUID(uuid), len) {
-}	
+BLEDescriptor::BLEDescriptor(const char *uuid, uint16_t len) : BLEDescriptor(BLEUUID(uuid), len) {}
 
 /**
  * @brief BLEDescriptor constructor.
  */
 BLEDescriptor::BLEDescriptor(BLEUUID uuid, uint16_t max_len) {
-	m_bleUUID            = uuid;
-	m_value.attr_len     = 0;                                         // Initial length is 0.
-	m_value.attr_max_len = max_len;                     // Maximum length of the data.
-	m_handle             = NULL_HANDLE;                               // Handle is initially unknown.
-	m_pCharacteristic    = nullptr;                                   // No initial characteristic.
-	m_pCallback          = nullptr;                                   // No initial callback.
-
-	m_value.attr_value   = (uint8_t*) malloc(max_len);  // Allocate storage for the value.
-} // BLEDescriptor
+  m_bleUUID = uuid;
+  m_value.attr_len = 0;            // Initial length is 0.
+  m_value.attr_max_len = max_len;  // Maximum length of the data.
+  m_handle = NULL_HANDLE;          // Handle is initially unknown.
+  m_pCharacteristic = nullptr;     // No initial characteristic.
+  m_pCallback = nullptr;           // No initial callback.
 
+  m_value.attr_value = (uint8_t *)malloc(max_len);  // Allocate storage for the value.
+}  // BLEDescriptor
 
 /**
  * @brief BLEDescriptor destructor.
  */
 BLEDescriptor::~BLEDescriptor() {
-	free(m_value.attr_value);   // Release the storage we created in the constructor.
-} // ~BLEDescriptor
-
+  free(m_value.attr_value);  // Release the storage we created in the constructor.
+}  // ~BLEDescriptor
 
 /**
  * @brief Execute the creation of the descriptor with the BLE runtime in ESP.
  * @param [in] pCharacteristic The characteristic to which to register this descriptor.
  */
-void BLEDescriptor::executeCreate(BLECharacteristic* pCharacteristic) {
-	log_v(">> executeCreate(): %s", toString().c_str());
-
-	if (m_handle != NULL_HANDLE) {
-		log_e("Descriptor already has a handle.");
-		return;
-	}
-
-	m_pCharacteristic = pCharacteristic; // Save the characteristic associated with this service.
-
-	esp_attr_control_t control;
-	control.auto_rsp = ESP_GATT_AUTO_RSP;
-	m_semaphoreCreateEvt.take("executeCreate");
-	esp_err_t errRc = ::esp_ble_gatts_add_char_descr(
-			pCharacteristic->getService()->getHandle(),
-			getUUID().getNative(),
-			(esp_gatt_perm_t)m_permissions,
-			&m_value,
-			&control);
-	if (errRc != ESP_OK) {
-		log_e("<< esp_ble_gatts_add_char_descr: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
-
-	m_semaphoreCreateEvt.wait("executeCreate");
-	log_v("<< executeCreate");
-} // executeCreate
-
+void BLEDescriptor::executeCreate(BLECharacteristic *pCharacteristic) {
+  log_v(">> executeCreate(): %s", toString().c_str());
+
+  if (m_handle != NULL_HANDLE) {
+    log_e("Descriptor already has a handle.");
+    return;
+  }
+
+  m_pCharacteristic = pCharacteristic;  // Save the characteristic associated with this service.
+
+  esp_attr_control_t control;
+  control.auto_rsp = ESP_GATT_AUTO_RSP;
+  m_semaphoreCreateEvt.take("executeCreate");
+  esp_err_t errRc =
+    ::esp_ble_gatts_add_char_descr(pCharacteristic->getService()->getHandle(), getUUID().getNative(), (esp_gatt_perm_t)m_permissions, &m_value, &control);
+  if (errRc != ESP_OK) {
+    log_e("<< esp_ble_gatts_add_char_descr: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return;
+  }
+
+  m_semaphoreCreateEvt.wait("executeCreate");
+  log_v("<< executeCreate");
+}  // executeCreate
 
 /**
  * @brief Get the BLE handle for this descriptor.
  * @return The handle for this descriptor.
  */
 uint16_t BLEDescriptor::getHandle() {
-	return m_handle;
-} // getHandle
-
+  return m_handle;
+}  // getHandle
 
 /**
  * @brief Get the length of the value of this descriptor.
  * @return The length (in bytes) of the value of this descriptor.
  */
 size_t BLEDescriptor::getLength() {
-	return m_value.attr_len;
-} // getLength
-
+  return m_value.attr_len;
+}  // getLength
 
 /**
  * @brief Get the UUID of the descriptor.
  */
 BLEUUID BLEDescriptor::getUUID() {
-	return m_bleUUID;
-} // getUUID
-
-
+  return m_bleUUID;
+}  // getUUID
 
 /**
  * @brief Get the value of this descriptor.
  * @return A pointer to the value of this descriptor.
  */
-uint8_t* BLEDescriptor::getValue() {
-	return m_value.attr_value;
-} // getValue
-
+uint8_t *BLEDescriptor::getValue() {
+  return m_value.attr_value;
+}  // getValue
 
 /**
  * @brief Handle GATT server events for the descripttor.
@@ -124,91 +113,87 @@ uint8_t* BLEDescriptor::getValue() {
  * @param [in] gatts_if
  * @param [in] param
  */
-void BLEDescriptor::handleGATTServerEvent(
-		esp_gatts_cb_event_t      event,
-		esp_gatt_if_t             gatts_if,
-		esp_ble_gatts_cb_param_t* param) {
-	switch (event) {
-		// ESP_GATTS_ADD_CHAR_DESCR_EVT
-		//
-		// add_char_descr:
-		// - esp_gatt_status_t status
-		// - uint16_t          attr_handle
-		// - uint16_t          service_handle
-		// - esp_bt_uuid_t     char_uuid
-		case ESP_GATTS_ADD_CHAR_DESCR_EVT: {
-			if (m_pCharacteristic != nullptr &&
-					m_bleUUID.equals(BLEUUID(param->add_char_descr.descr_uuid)) &&
-					m_pCharacteristic->getService()->getHandle() == param->add_char_descr.service_handle &&
-					m_pCharacteristic == m_pCharacteristic->getService()->getLastCreatedCharacteristic()) {
-				setHandle(param->add_char_descr.attr_handle);
-				m_semaphoreCreateEvt.give();
-			}
-			break;
-		} // ESP_GATTS_ADD_CHAR_DESCR_EVT
-
-		// ESP_GATTS_WRITE_EVT - A request to write the value of a descriptor has arrived.
-		//
-		// write:
-		// - uint16_t conn_id
-		// - uint16_t trans_id
-		// - esp_bd_addr_t bda
-		// - uint16_t handle
-		// - uint16_t offset
-		// - bool need_rsp
-		// - bool is_prep
-		// - uint16_t len
-		// - uint8_t *value
-		case ESP_GATTS_WRITE_EVT: {
-			if (param->write.handle == m_handle) {
-				setValue(param->write.value, param->write.len);   // Set the value of the descriptor.
-
-				if (m_pCallback != nullptr) {   // We have completed the write, if there is a user supplied callback handler, invoke it now.
-					m_pCallback->onWrite(this);   // Invoke the onWrite callback handler.
-				}
-			}  // End of ... this is our handle.
-
-			break;
-		} // ESP_GATTS_WRITE_EVT
-
-		// ESP_GATTS_READ_EVT - A request to read the value of a descriptor has arrived.
-		//
-		// read:
-		// - uint16_t conn_id
-		// - uint32_t trans_id
-		// - esp_bd_addr_t bda
-		// - uint16_t handle
-		// - uint16_t offset
-		// - bool is_long
-		// - bool need_rsp
-		//
-		case ESP_GATTS_READ_EVT: {
-			if (param->read.handle == m_handle) {  // If this event is for this descriptor ... process it
-
-				if (m_pCallback != nullptr) {   // If we have a user supplied callback, invoke it now.
-					m_pCallback->onRead(this);    // Invoke the onRead callback method in the callback handler.
-				}
-
-			} // End of this is our handle
-			break;
-		} // ESP_GATTS_READ_EVT
-
-		default:
-			break;
-	} // switch event
-} // handleGATTServerEvent
-
+void BLEDescriptor::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) {
+  switch (event) {
+    // ESP_GATTS_ADD_CHAR_DESCR_EVT
+    //
+    // add_char_descr:
+    // - esp_gatt_status_t status
+    // - uint16_t          attr_handle
+    // - uint16_t          service_handle
+    // - esp_bt_uuid_t     char_uuid
+    case ESP_GATTS_ADD_CHAR_DESCR_EVT:
+    {
+      if (m_pCharacteristic != nullptr && m_bleUUID.equals(BLEUUID(param->add_char_descr.descr_uuid))
+          && m_pCharacteristic->getService()->getHandle() == param->add_char_descr.service_handle
+          && m_pCharacteristic == m_pCharacteristic->getService()->getLastCreatedCharacteristic()) {
+        setHandle(param->add_char_descr.attr_handle);
+        m_semaphoreCreateEvt.give();
+      }
+      break;
+    }  // ESP_GATTS_ADD_CHAR_DESCR_EVT
+
+    // ESP_GATTS_WRITE_EVT - A request to write the value of a descriptor has arrived.
+    //
+    // write:
+    // - uint16_t conn_id
+    // - uint16_t trans_id
+    // - esp_bd_addr_t bda
+    // - uint16_t handle
+    // - uint16_t offset
+    // - bool need_rsp
+    // - bool is_prep
+    // - uint16_t len
+    // - uint8_t *value
+    case ESP_GATTS_WRITE_EVT:
+    {
+      if (param->write.handle == m_handle) {
+        setValue(param->write.value, param->write.len);  // Set the value of the descriptor.
+
+        if (m_pCallback != nullptr) {  // We have completed the write, if there is a user supplied callback handler, invoke it now.
+          m_pCallback->onWrite(this);  // Invoke the onWrite callback handler.
+        }
+      }  // End of ... this is our handle.
+
+      break;
+    }  // ESP_GATTS_WRITE_EVT
+
+    // ESP_GATTS_READ_EVT - A request to read the value of a descriptor has arrived.
+    //
+    // read:
+    // - uint16_t conn_id
+    // - uint32_t trans_id
+    // - esp_bd_addr_t bda
+    // - uint16_t handle
+    // - uint16_t offset
+    // - bool is_long
+    // - bool need_rsp
+    //
+    case ESP_GATTS_READ_EVT:
+    {
+      if (param->read.handle == m_handle) {  // If this event is for this descriptor ... process it
+
+        if (m_pCallback != nullptr) {  // If we have a user supplied callback, invoke it now.
+          m_pCallback->onRead(this);   // Invoke the onRead callback method in the callback handler.
+        }
+
+      }  // End of this is our handle
+      break;
+    }  // ESP_GATTS_READ_EVT
+
+    default: break;
+  }  // switch event
+}  // handleGATTServerEvent
 
 /**
  * @brief Set the callback handlers for this descriptor.
  * @param [in] pCallbacks An instance of a callback structure used to define any callbacks for the descriptor.
  */
-void BLEDescriptor::setCallbacks(BLEDescriptorCallbacks* pCallback) {
-	log_v(">> setCallbacks: 0x%x", (uint32_t) pCallback);
-	m_pCallback = pCallback;
-	log_v("<< setCallbacks");
-} // setCallbacks
-
+void BLEDescriptor::setCallbacks(BLEDescriptorCallbacks *pCallback) {
+  log_v(">> setCallbacks: 0x%x", (uint32_t)pCallback);
+  m_pCallback = pCallback;
+  log_v("<< setCallbacks");
+}  // setCallbacks
 
 /**
  * @brief Set the handle of this descriptor.
@@ -217,50 +202,51 @@ void BLEDescriptor::setCallbacks(BLEDescriptorCallbacks* pCallback) {
  * @return N/A.
  */
 void BLEDescriptor::setHandle(uint16_t handle) {
-	log_v(">> setHandle(0x%.2x): Setting descriptor handle to be 0x%.2x", handle, handle);
-	m_handle = handle;
-	log_v("<< setHandle()");
-} // setHandle
-
+  log_v(">> setHandle(0x%.2x): Setting descriptor handle to be 0x%.2x", handle, handle);
+  m_handle = handle;
+  log_v("<< setHandle()");
+}  // setHandle
 
 /**
  * @brief Set the value of the descriptor.
  * @param [in] data The data to set for the descriptor.
  * @param [in] length The length of the data in bytes.
  */
-void BLEDescriptor::setValue(uint8_t* data, size_t length) {
-	if (length > ESP_GATT_MAX_ATTR_LEN) {
-		log_e("Size %d too large, must be no bigger than %d", length, ESP_GATT_MAX_ATTR_LEN);
-		return;
-	}
-	m_value.attr_len = length;
-	memcpy(m_value.attr_value, data, length);
-} // setValue
-
+void BLEDescriptor::setValue(uint8_t *data, size_t length) {
+  if (length > ESP_GATT_MAX_ATTR_LEN) {
+    log_e("Size %d too large, must be no bigger than %d", length, ESP_GATT_MAX_ATTR_LEN);
+    return;
+  }
+  m_value.attr_len = length;
+  memcpy(m_value.attr_value, data, length);
+  if (m_handle != NULL_HANDLE) {
+    esp_ble_gatts_set_attr_value(m_handle, length, (const uint8_t *)data);
+    log_d("Set the value in the GATTS database using handle 0x%x", m_handle);
+  }
+}  // setValue
 
 /**
  * @brief Set the value of the descriptor.
  * @param [in] value The value of the descriptor in string form.
  */
-void BLEDescriptor::setValue(std::string value) {
-	setValue((uint8_t*) value.data(), value.length());
-} // setValue
+void BLEDescriptor::setValue(String value) {
+  setValue((uint8_t *)value.c_str(), value.length());
+}  // setValue
 
 void BLEDescriptor::setAccessPermissions(esp_gatt_perm_t perm) {
-	m_permissions = perm;
+  m_permissions = perm;
 }
 
 /**
  * @brief Return a string representation of the descriptor.
  * @return A string representation of the descriptor.
  */
-std::string BLEDescriptor::toString() {
-	char hex[5];
-	snprintf(hex, sizeof(hex), "%04x", m_handle);
-	std::string res = "UUID: " + m_bleUUID.toString() + ", handle: 0x" + hex;
-	return res;
-} // toString
-
+String BLEDescriptor::toString() {
+  char hex[5];
+  snprintf(hex, sizeof(hex), "%04x", m_handle);
+  String res = "UUID: " + m_bleUUID.toString() + ", handle: 0x" + hex;
+  return res;
+}  // toString
 
 BLEDescriptorCallbacks::~BLEDescriptorCallbacks() {}
 
@@ -268,20 +254,19 @@ BLEDescriptorCallbacks::~BLEDescriptorCallbacks() {}
  * @brief Callback function to support a read request.
  * @param [in] pDescriptor The descriptor that is the source of the event.
  */
-void BLEDescriptorCallbacks::onRead(BLEDescriptor* pDescriptor) {
-	log_d("BLEDescriptorCallbacks", ">> onRead: default");
-	log_d("BLEDescriptorCallbacks", "<< onRead");
-} // onRead
-
+void BLEDescriptorCallbacks::onRead(BLEDescriptor *pDescriptor) {
+  log_d("BLEDescriptorCallbacks", ">> onRead: default");
+  log_d("BLEDescriptorCallbacks", "<< onRead");
+}  // onRead
 
 /**
  * @brief Callback function to support a write request.
  * @param [in] pDescriptor The descriptor that is the source of the event.
  */
-void BLEDescriptorCallbacks::onWrite(BLEDescriptor* pDescriptor) {
-	log_d("BLEDescriptorCallbacks", ">> onWrite: default");
-	log_d("BLEDescriptorCallbacks", "<< onWrite");
-} // onWrite
-
+void BLEDescriptorCallbacks::onWrite(BLEDescriptor *pDescriptor) {
+  log_d("BLEDescriptorCallbacks", ">> onWrite: default");
+  log_d("BLEDescriptorCallbacks", "<< onWrite");
+}  // onWrite
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEDescriptor.h b/libraries/BLE/src/BLEDescriptor.h
index 03cc5791727..e155a1f2971 100644
--- a/libraries/BLE/src/BLEDescriptor.h
+++ b/libraries/BLE/src/BLEDescriptor.h
@@ -7,13 +7,16 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEDESCRIPTOR_H_
 #define COMPONENTS_CPP_UTILS_BLEDESCRIPTOR_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <string>
 #include "BLEUUID.h"
 #include "BLECharacteristic.h"
 #include <esp_gatts_api.h>
-#include "FreeRTOS.h"
+#include "RTOS.h"
 
 class BLEService;
 class BLECharacteristic;
@@ -24,41 +27,37 @@ class BLEDescriptorCallbacks;
  */
 class BLEDescriptor {
 public:
-	BLEDescriptor(const char* uuid, uint16_t max_len = 100);
-	BLEDescriptor(BLEUUID uuid, uint16_t max_len = 100);
-	virtual ~BLEDescriptor();
+  BLEDescriptor(const char *uuid, uint16_t max_len = 100);
+  BLEDescriptor(BLEUUID uuid, uint16_t max_len = 100);
+  virtual ~BLEDescriptor();
 
-	uint16_t getHandle();                                   // Get the handle of the descriptor.
-	size_t   getLength();                                   // Get the length of the value of the descriptor.
-	BLEUUID  getUUID();                                     // Get the UUID of the descriptor.
-	uint8_t* getValue();                                    // Get a pointer to the value of the descriptor.
-	void handleGATTServerEvent(
-			esp_gatts_cb_event_t      event,
-			esp_gatt_if_t             gatts_if,
-			esp_ble_gatts_cb_param_t* param);
+  uint16_t getHandle();  // Get the handle of the descriptor.
+  size_t getLength();    // Get the length of the value of the descriptor.
+  BLEUUID getUUID();     // Get the UUID of the descriptor.
+  uint8_t *getValue();   // Get a pointer to the value of the descriptor.
+  void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
 
-	void setAccessPermissions(esp_gatt_perm_t perm);	      // Set the permissions of the descriptor.
-	void setCallbacks(BLEDescriptorCallbacks* pCallbacks);  // Set callbacks to be invoked for the descriptor.
-	void setValue(uint8_t* data, size_t size);              // Set the value of the descriptor as a pointer to data.
-	void setValue(std::string value);                       // Set the value of the descriptor as a data buffer.
+  void setAccessPermissions(esp_gatt_perm_t perm);        // Set the permissions of the descriptor.
+  void setCallbacks(BLEDescriptorCallbacks *pCallbacks);  // Set callbacks to be invoked for the descriptor.
+  void setValue(uint8_t *data, size_t size);              // Set the value of the descriptor as a pointer to data.
+  void setValue(String value);                            // Set the value of the descriptor as a data buffer.
 
-	std::string toString();                                 // Convert the descriptor to a string representation.
+  String toString();  // Convert the descriptor to a string representation.
 
 private:
-	friend class BLEDescriptorMap;
-	friend class BLECharacteristic;
-	BLEUUID                 m_bleUUID;
-	uint16_t                m_handle;
-	BLEDescriptorCallbacks* m_pCallback;
-	BLECharacteristic*      m_pCharacteristic;
-	esp_gatt_perm_t				  m_permissions = ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE;
-	FreeRTOS::Semaphore     m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt");
-	esp_attr_value_t        m_value;
-
-	void executeCreate(BLECharacteristic* pCharacteristic);
-	void setHandle(uint16_t handle);
-}; // BLEDescriptor
+  friend class BLEDescriptorMap;
+  friend class BLECharacteristic;
+  BLEUUID m_bleUUID;
+  uint16_t m_handle;
+  BLEDescriptorCallbacks *m_pCallback;
+  BLECharacteristic *m_pCharacteristic;
+  esp_gatt_perm_t m_permissions = ESP_GATT_PERM_READ | ESP_GATT_PERM_WRITE;
+  FreeRTOS::Semaphore m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt");
+  esp_attr_value_t m_value;
 
+  void executeCreate(BLECharacteristic *pCharacteristic);
+  void setHandle(uint16_t handle);
+};  // BLEDescriptor
 
 /**
  * @brief Callbacks that can be associated with a %BLE descriptors to inform of events.
@@ -69,9 +68,11 @@ class BLEDescriptor {
  */
 class BLEDescriptorCallbacks {
 public:
-	virtual ~BLEDescriptorCallbacks();
-	virtual void onRead(BLEDescriptor* pDescriptor);
-	virtual void onWrite(BLEDescriptor* pDescriptor);
+  virtual ~BLEDescriptorCallbacks();
+  virtual void onRead(BLEDescriptor *pDescriptor);
+  virtual void onWrite(BLEDescriptor *pDescriptor);
 };
-#endif /* CONFIG_BT_ENABLED */
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEDESCRIPTOR_H_ */
diff --git a/libraries/BLE/src/BLEDescriptorMap.cpp b/libraries/BLE/src/BLEDescriptorMap.cpp
index 0b5d3175a9d..732fb62cdcf 100644
--- a/libraries/BLE/src/BLEDescriptorMap.cpp
+++ b/libraries/BLE/src/BLEDescriptorMap.cpp
@@ -4,13 +4,16 @@
  *  Created on: Jun 22, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <sstream>
 #include <iomanip>
 #include "BLECharacteristic.h"
 #include "BLEDescriptor.h"
-#include <esp_gatts_api.h>   // ESP32 BLE
+#include <esp_gatts_api.h>  // ESP32 BLE
 #ifdef ARDUINO_ARCH_ESP32
 #include "esp32-hal-log.h"
 #endif
@@ -20,36 +23,33 @@
  * @param [in] UUID The UUID to look up the descriptor.
  * @return The descriptor.  If not present, then nullptr is returned.
  */
-BLEDescriptor* BLEDescriptorMap::getByUUID(const char* uuid) {
-	return getByUUID(BLEUUID(uuid));
+BLEDescriptor *BLEDescriptorMap::getByUUID(const char *uuid) {
+  return getByUUID(BLEUUID(uuid));
 }
 
-
 /**
  * @brief Return the descriptor by UUID.
  * @param [in] UUID The UUID to look up the descriptor.
  * @return The descriptor.  If not present, then nullptr is returned.
  */
-BLEDescriptor* BLEDescriptorMap::getByUUID(BLEUUID uuid) {
-	for (auto &myPair : m_uuidMap) {
-		if (myPair.first->getUUID().equals(uuid)) {
-			return myPair.first;
-		}
-	}
-	//return m_uuidMap.at(uuid.toString());
-	return nullptr;
-} // getByUUID
-
+BLEDescriptor *BLEDescriptorMap::getByUUID(BLEUUID uuid) {
+  for (auto &myPair : m_uuidMap) {
+    if (myPair.first->getUUID().equals(uuid)) {
+      return myPair.first;
+    }
+  }
+  //return m_uuidMap.at(uuid.toString());
+  return nullptr;
+}  // getByUUID
 
 /**
  * @brief Return the descriptor by handle.
  * @param [in] handle The handle to look up the descriptor.
  * @return The descriptor.
  */
-BLEDescriptor* BLEDescriptorMap::getByHandle(uint16_t handle) {
-	return m_handleMap.at(handle);
-} // getByHandle
-
+BLEDescriptor *BLEDescriptorMap::getByHandle(uint16_t handle) {
+  return m_handleMap.at(handle);
+}  // getByHandle
 
 /**
  * @brief Set the descriptor by UUID.
@@ -57,11 +57,9 @@ BLEDescriptor* BLEDescriptorMap::getByHandle(uint16_t handle) {
  * @param [in] characteristic The descriptor to cache.
  * @return N/A.
  */
-void BLEDescriptorMap::setByUUID(const char* uuid, BLEDescriptor* pDescriptor){
-	m_uuidMap.insert(std::pair<BLEDescriptor*, std::string>(pDescriptor, uuid));
-} // setByUUID
-
-
+void BLEDescriptorMap::setByUUID(const char *uuid, BLEDescriptor *pDescriptor) {
+  m_uuidMap.insert(std::pair<BLEDescriptor *, String>(pDescriptor, uuid));
+}  // setByUUID
 
 /**
  * @brief Set the descriptor by UUID.
@@ -69,10 +67,9 @@ void BLEDescriptorMap::setByUUID(const char* uuid, BLEDescriptor* pDescriptor){
  * @param [in] characteristic The descriptor to cache.
  * @return N/A.
  */
-void BLEDescriptorMap::setByUUID(BLEUUID uuid, BLEDescriptor* pDescriptor) {
-	m_uuidMap.insert(std::pair<BLEDescriptor*, std::string>(pDescriptor, uuid.toString()));
-} // setByUUID
-
+void BLEDescriptorMap::setByUUID(BLEUUID uuid, BLEDescriptor *pDescriptor) {
+  m_uuidMap.insert(std::pair<BLEDescriptor *, String>(pDescriptor, uuid.toString()));
+}  // setByUUID
 
 /**
  * @brief Set the descriptor by handle.
@@ -80,69 +77,70 @@ void BLEDescriptorMap::setByUUID(BLEUUID uuid, BLEDescriptor* pDescriptor) {
  * @param [in] descriptor The descriptor to cache.
  * @return N/A.
  */
-void BLEDescriptorMap::setByHandle(uint16_t handle, BLEDescriptor* pDescriptor) {
-	m_handleMap.insert(std::pair<uint16_t, BLEDescriptor*>(handle, pDescriptor));
-} // setByHandle
-
+void BLEDescriptorMap::setByHandle(uint16_t handle, BLEDescriptor *pDescriptor) {
+  m_handleMap.insert(std::pair<uint16_t, BLEDescriptor *>(handle, pDescriptor));
+}  // setByHandle
 
 /**
  * @brief Return a string representation of the descriptor map.
  * @return A string representation of the descriptor map.
  */
-std::string BLEDescriptorMap::toString() {
-	std::string res;
-	char hex[5];
-	int count = 0;
-	for (auto &myPair : m_uuidMap) {
-		if (count > 0) {res += "\n";}
-		snprintf(hex, sizeof(hex), "%04x", myPair.first->getHandle());
-		count++;
-		res += "handle: 0x";
-		res += hex;
-		res += ", uuid: " + myPair.first->getUUID().toString();
-	}
-	return res;
-} // toString
-
+String BLEDescriptorMap::toString() {
+  String res;
+  char hex[5];
+  int count = 0;
+  for (auto &myPair : m_uuidMap) {
+    if (count > 0) {
+      res += "\n";
+    }
+    snprintf(hex, sizeof(hex), "%04x", myPair.first->getHandle());
+    count++;
+    res += "handle: 0x";
+    res += hex;
+    res += ", uuid: " + myPair.first->getUUID().toString();
+  }
+  return res;
+}  // toString
 
 /**
- * @breif Pass the GATT server event onwards to each of the descriptors found in the mapping
+ * @brief Pass the GATT server event onwards to each of the descriptors found in the mapping
  * @param [in] event
  * @param [in] gatts_if
  * @param [in] param
  */
-void BLEDescriptorMap::handleGATTServerEvent(
-		esp_gatts_cb_event_t      event,
-		esp_gatt_if_t             gatts_if,
-		esp_ble_gatts_cb_param_t* param) {
-	// Invoke the handler for every descriptor we have.
-	for (auto &myPair : m_uuidMap) {
-		myPair.first->handleGATTServerEvent(event, gatts_if, param);
-	}
-} // handleGATTServerEvent
-
+void BLEDescriptorMap::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) {
+  // Invoke the handler for every descriptor we have.
+  for (auto &myPair : m_uuidMap) {
+    myPair.first->handleGATTServerEvent(event, gatts_if, param);
+  }
+}  // handleGATTServerEvent
 
 /**
  * @brief Get the first descriptor in the map.
  * @return The first descriptor in the map.
  */
-BLEDescriptor* BLEDescriptorMap::getFirst() {
-	m_iterator = m_uuidMap.begin();
-	if (m_iterator == m_uuidMap.end()) return nullptr;
-	BLEDescriptor* pRet = m_iterator->first;
-	m_iterator++;
-	return pRet;
-} // getFirst
-
+BLEDescriptor *BLEDescriptorMap::getFirst() {
+  m_iterator = m_uuidMap.begin();
+  if (m_iterator == m_uuidMap.end()) {
+    return nullptr;
+  }
+  BLEDescriptor *pRet = m_iterator->first;
+  m_iterator++;
+  return pRet;
+}  // getFirst
 
 /**
  * @brief Get the next descriptor in the map.
  * @return The next descriptor in the map.
  */
-BLEDescriptor* BLEDescriptorMap::getNext() {
-	if (m_iterator == m_uuidMap.end()) return nullptr;
-	BLEDescriptor* pRet = m_iterator->first;
-	m_iterator++;
-	return pRet;
-} // getNext
-#endif /* CONFIG_BT_ENABLED */
+BLEDescriptor *BLEDescriptorMap::getNext() {
+  if (m_iterator == m_uuidMap.end()) {
+    return nullptr;
+  }
+  BLEDescriptor *pRet = m_iterator->first;
+  m_iterator++;
+  return pRet;
+}  // getNext
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEDevice.cpp b/libraries/BLE/src/BLEDevice.cpp
index 128ede98d84..186b36d6a33 100644
--- a/libraries/BLE/src/BLEDevice.cpp
+++ b/libraries/BLE/src/BLEDevice.cpp
@@ -4,24 +4,27 @@
  *  Created on: Mar 16, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <freertos/FreeRTOS.h>
 #include <freertos/event_groups.h>
 #include <freertos/task.h>
 #include <esp_err.h>
 #include <nvs_flash.h>
-#include <esp_bt.h>            // ESP32 BLE
-#include <esp_bt_device.h>     // ESP32 BLE
-#include <esp_bt_main.h>       // ESP32 BLE
-#include <esp_gap_ble_api.h>   // ESP32 BLE
-#include <esp_gatts_api.h>     // ESP32 BLE
-#include <esp_gattc_api.h>     // ESP32 BLE
-#include <esp_gatt_common_api.h>// ESP32 BLE
-#include <esp_err.h>           // ESP32 ESP-IDF
-#include <map>                 // Part of C++ Standard library
-#include <sstream>             // Part of C++ Standard library
-#include <iomanip>             // Part of C++ Standard library
+#include <esp_bt.h>               // ESP32 BLE
+#include <esp_bt_device.h>        // ESP32 BLE
+#include <esp_bt_main.h>          // ESP32 BLE
+#include <esp_gap_ble_api.h>      // ESP32 BLE
+#include <esp_gatts_api.h>        // ESP32 BLE
+#include <esp_gattc_api.h>        // ESP32 BLE
+#include <esp_gatt_common_api.h>  // ESP32 BLE
+#include <esp_err.h>              // ESP32 ESP-IDF
+#include <map>                    // Part of C++ Standard library
+#include <sstream>                // Part of C++ Standard library
+#include <iomanip>                // Part of C++ Standard library
 
 #include "BLEDevice.h"
 #include "BLEClient.h"
@@ -34,18 +37,17 @@
 
 #include "esp32-hal-log.h"
 
-
 /**
  * Singletons for the BLEDevice.
  */
-BLEServer* BLEDevice::m_pServer = nullptr;
-BLEScan*   BLEDevice::m_pScan   = nullptr;
-BLEClient* BLEDevice::m_pClient = nullptr;
-bool       initialized          = false;  
+BLEServer *BLEDevice::m_pServer = nullptr;
+BLEScan *BLEDevice::m_pScan = nullptr;
+BLEClient *BLEDevice::m_pClient = nullptr;
+bool initialized = false;
 esp_ble_sec_act_t BLEDevice::m_securityLevel = (esp_ble_sec_act_t)0;
-BLESecurityCallbacks* BLEDevice::m_securityCallbacks = nullptr;
-uint16_t   BLEDevice::m_localMTU = 23;  // not sure if this variable is useful
-BLEAdvertising* BLEDevice::m_bleAdvertising = nullptr;
+BLESecurityCallbacks *BLEDevice::m_securityCallbacks = nullptr;
+uint16_t BLEDevice::m_localMTU = 23;  // not sure if this variable is useful
+BLEAdvertising *BLEDevice::m_bleAdvertising = nullptr;
 uint16_t BLEDevice::m_appId = 0;
 std::map<uint16_t, conn_status_t> BLEDevice::m_connectedClientsMap;
 gap_event_handler BLEDevice::m_customGapHandler = nullptr;
@@ -56,34 +58,32 @@ gatts_event_handler BLEDevice::m_customGattsHandler = nullptr;
  * @brief Create a new instance of a client.
  * @return A new instance of the client.
  */
-/* STATIC */ BLEClient* BLEDevice::createClient() {
-	log_v(">> createClient");
+/* STATIC */ BLEClient *BLEDevice::createClient() {
+  log_v(">> createClient");
 #ifndef CONFIG_GATTC_ENABLE  // Check that BLE GATTC is enabled in make menuconfig
-	log_e("BLE GATTC is not enabled - CONFIG_GATTC_ENABLE not defined");
-	abort();
+  log_e("BLE GATTC is not enabled - CONFIG_GATTC_ENABLE not defined");
+  abort();
 #endif  // CONFIG_GATTC_ENABLE
-	m_pClient = new BLEClient();
-	log_v("<< createClient");
-	return m_pClient;
-} // createClient
-
+  m_pClient = new BLEClient();
+  log_v("<< createClient");
+  return m_pClient;
+}  // createClient
 
 /**
  * @brief Create a new instance of a server.
  * @return A new instance of the server.
  */
-/* STATIC */ BLEServer* BLEDevice::createServer() {
-	log_v(">> createServer");
+/* STATIC */ BLEServer *BLEDevice::createServer() {
+  log_v(">> createServer");
 #ifndef CONFIG_GATTS_ENABLE  // Check that BLE GATTS is enabled in make menuconfig
-	log_e("BLE GATTS is not enabled - CONFIG_GATTS_ENABLE not defined");
-	abort();
-#endif // CONFIG_GATTS_ENABLE
-	m_pServer = new BLEServer();
-	m_pServer->createApp(m_appId++);
-	log_v("<< createServer");
-	return m_pServer;
-} // createServer
-
+  log_e("BLE GATTS is not enabled - CONFIG_GATTS_ENABLE not defined");
+  abort();
+#endif  // CONFIG_GATTS_ENABLE
+  m_pServer = new BLEServer();
+  m_pServer->createApp(m_appId++);
+  log_v("<< createServer");
+  return m_pServer;
+}  // createServer
 
 /**
  * @brief Handle GATT server events.
@@ -92,43 +92,37 @@ gatts_event_handler BLEDevice::m_customGattsHandler = nullptr;
  * @param [in] gatts_if The connection to the GATT interface.
  * @param [in] param Parameters for the event.
  */
-/* STATIC */ void BLEDevice::gattServerEventHandler(
-   esp_gatts_cb_event_t      event,
-   esp_gatt_if_t             gatts_if,
-   esp_ble_gatts_cb_param_t* param
-) {
-	log_d("gattServerEventHandler [esp_gatt_if: %d] ... %s",
-		gatts_if,
-		BLEUtils::gattServerEventTypeToString(event).c_str());
-
-	BLEUtils::dumpGattServerEvent(event, gatts_if, param);
-
-	switch (event) {
-		case ESP_GATTS_CONNECT_EVT: {
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-			if(BLEDevice::m_securityLevel){
-				esp_ble_set_encryption(param->connect.remote_bda, BLEDevice::m_securityLevel);
-			}
-#endif	// CONFIG_BLE_SMP_ENABLE
-			break;
-		} // ESP_GATTS_CONNECT_EVT
-
-		default: {
-			break;
-		}
-	} // switch
-
-
-	if (BLEDevice::m_pServer != nullptr) {
-		BLEDevice::m_pServer->handleGATTServerEvent(event, gatts_if, param);
-	}
-
-	if(m_customGattsHandler != nullptr) {
-		m_customGattsHandler(event, gatts_if, param);
-	}
-
-} // gattServerEventHandler
-
+/* STATIC */ void BLEDevice::gattServerEventHandler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) {
+  log_d("gattServerEventHandler [esp_gatt_if: %d] ... %s", gatts_if, BLEUtils::gattServerEventTypeToString(event).c_str());
+
+  BLEUtils::dumpGattServerEvent(event, gatts_if, param);
+
+  switch (event) {
+    case ESP_GATTS_CONNECT_EVT:
+    {
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+      if (BLEDevice::m_securityLevel) {
+        esp_ble_set_encryption(param->connect.remote_bda, BLEDevice::m_securityLevel);
+      }
+#endif  // CONFIG_BLE_SMP_ENABLE
+      break;
+    }  // ESP_GATTS_CONNECT_EVT
+
+    default:
+    {
+      break;
+    }
+  }  // switch
+
+  if (BLEDevice::m_pServer != nullptr) {
+    BLEDevice::m_pServer->handleGATTServerEvent(event, gatts_if, param);
+  }
+
+  if (m_customGattsHandler != nullptr) {
+    m_customGattsHandler(event, gatts_if, param);
+  }
+
+}  // gattServerEventHandler
 
 /**
  * @brief Handle GATT client events.
@@ -139,175 +133,157 @@ gatts_event_handler BLEDevice::m_customGattsHandler = nullptr;
  * @param [in] gattc_if
  * @param [in] param
  */
-/* STATIC */ void BLEDevice::gattClientEventHandler(
-	esp_gattc_cb_event_t      event,
-	esp_gatt_if_t             gattc_if,
-	esp_ble_gattc_cb_param_t* param) {
-
-	log_d("gattClientEventHandler [esp_gatt_if: %d] ... %s",
-		gattc_if, BLEUtils::gattClientEventTypeToString(event).c_str());
-	BLEUtils::dumpGattClientEvent(event, gattc_if, param);
-
-	switch(event) {
-		case ESP_GATTC_CONNECT_EVT: {
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-			if(BLEDevice::m_securityLevel){
-				esp_ble_set_encryption(param->connect.remote_bda, BLEDevice::m_securityLevel);
-			}
-#endif	// CONFIG_BLE_SMP_ENABLE
-			break;
-		} // ESP_GATTS_CONNECT_EVT
-
-		default:
-			break;
-	} // switch
-	for(auto &myPair : BLEDevice::getPeerDevices(true)) {
-		conn_status_t conn_status = (conn_status_t)myPair.second;
-		if(((BLEClient*)conn_status.peer_device)->getGattcIf() == gattc_if || ((BLEClient*)conn_status.peer_device)->getGattcIf() == ESP_GATT_IF_NONE || gattc_if == ESP_GATT_IF_NONE){
-			((BLEClient*)conn_status.peer_device)->gattClientEventHandler(event, gattc_if, param);
-		}
-	}
-
-	if(m_customGattcHandler != nullptr) {
-		m_customGattcHandler(event, gattc_if, param);
-	}
-
-
-} // gattClientEventHandler
-
+/* STATIC */ void BLEDevice::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *param) {
+
+  log_d("gattClientEventHandler [esp_gatt_if: %d] ... %s", gattc_if, BLEUtils::gattClientEventTypeToString(event).c_str());
+  BLEUtils::dumpGattClientEvent(event, gattc_if, param);
+
+  switch (event) {
+    case ESP_GATTC_CONNECT_EVT:
+    {
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+      if (BLEDevice::m_securityLevel) {
+        esp_ble_set_encryption(param->connect.remote_bda, BLEDevice::m_securityLevel);
+      }
+#endif  // CONFIG_BLE_SMP_ENABLE
+      break;
+    }  // ESP_GATTS_CONNECT_EVT
+
+    default: break;
+  }  // switch
+  for (auto &myPair : BLEDevice::getPeerDevices(true)) {
+    conn_status_t conn_status = (conn_status_t)myPair.second;
+    if (((BLEClient *)conn_status.peer_device)->getGattcIf() == gattc_if || ((BLEClient *)conn_status.peer_device)->getGattcIf() == ESP_GATT_IF_NONE
+        || gattc_if == ESP_GATT_IF_NONE) {
+      ((BLEClient *)conn_status.peer_device)->gattClientEventHandler(event, gattc_if, param);
+    }
+  }
+
+  if (m_customGattcHandler != nullptr) {
+    m_customGattcHandler(event, gattc_if, param);
+  }
+
+}  // gattClientEventHandler
 
 /**
  * @brief Handle GAP events.
  */
-/* STATIC */ void BLEDevice::gapEventHandler(
-	esp_gap_ble_cb_event_t event,
-	esp_ble_gap_cb_param_t *param) {
-
-	BLEUtils::dumpGapEvent(event, param);
-
-	switch(event) {
-
-		 case ESP_GAP_BLE_OOB_REQ_EVT:                                /* OOB request event */
-			 log_i("ESP_GAP_BLE_OOB_REQ_EVT");
-			 break;
-		 case ESP_GAP_BLE_LOCAL_IR_EVT:                               /* BLE local IR event */
-			 log_i("ESP_GAP_BLE_LOCAL_IR_EVT");
-			 break;
-		 case ESP_GAP_BLE_LOCAL_ER_EVT:                               /* BLE local ER event */
-			 log_i("ESP_GAP_BLE_LOCAL_ER_EVT");
-			 break;
-		 case ESP_GAP_BLE_NC_REQ_EVT:								/*  NUMERIC CONFIRMATION  */
-			 log_i("ESP_GAP_BLE_NC_REQ_EVT");
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-			if(BLEDevice::m_securityCallbacks != nullptr){
-			 	 esp_ble_confirm_reply(param->ble_security.ble_req.bd_addr, BLEDevice::m_securityCallbacks->onConfirmPIN(param->ble_security.key_notif.passkey));
-			}
-#endif	// CONFIG_BLE_SMP_ENABLE
-			 break;
-		 case ESP_GAP_BLE_PASSKEY_REQ_EVT:                           /* passkey request event */
-			log_i("ESP_GAP_BLE_PASSKEY_REQ_EVT: ");
-			// esp_log_buffer_hex(m_remote_bda, sizeof(m_remote_bda));
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-			if(BLEDevice::m_securityCallbacks != nullptr){
-				esp_ble_passkey_reply(param->ble_security.ble_req.bd_addr, true, BLEDevice::m_securityCallbacks->onPassKeyRequest());
-			}
-#endif	// CONFIG_BLE_SMP_ENABLE
-			break;
-			/*
+/* STATIC */ void BLEDevice::gapEventHandler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) {
+
+  BLEUtils::dumpGapEvent(event, param);
+
+  switch (event) {
+
+    case ESP_GAP_BLE_OOB_REQ_EVT:  /* OOB request event */ log_i("ESP_GAP_BLE_OOB_REQ_EVT"); break;
+    case ESP_GAP_BLE_LOCAL_IR_EVT: /* BLE local IR event */ log_i("ESP_GAP_BLE_LOCAL_IR_EVT"); break;
+    case ESP_GAP_BLE_LOCAL_ER_EVT: /* BLE local ER event */ log_i("ESP_GAP_BLE_LOCAL_ER_EVT"); break;
+    case ESP_GAP_BLE_NC_REQ_EVT:   /*  NUMERIC CONFIRMATION  */ log_i("ESP_GAP_BLE_NC_REQ_EVT");
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+      if (BLEDevice::m_securityCallbacks != nullptr) {
+        esp_ble_confirm_reply(param->ble_security.ble_req.bd_addr, BLEDevice::m_securityCallbacks->onConfirmPIN(param->ble_security.key_notif.passkey));
+      }
+#endif  // CONFIG_BLE_SMP_ENABLE
+      break;
+    case ESP_GAP_BLE_PASSKEY_REQ_EVT: /* passkey request event */
+      log_i("ESP_GAP_BLE_PASSKEY_REQ_EVT: ");
+      // esp_log_buffer_hex(m_remote_bda, sizeof(m_remote_bda));
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+      if (BLEDevice::m_securityCallbacks != nullptr) {
+        esp_ble_passkey_reply(param->ble_security.ble_req.bd_addr, true, BLEDevice::m_securityCallbacks->onPassKeyRequest());
+      }
+#endif  // CONFIG_BLE_SMP_ENABLE
+      break;
+      /*
 			 * TODO should we add white/black list comparison?
 			 */
-		 case ESP_GAP_BLE_SEC_REQ_EVT:
-			 /* send the positive(true) security response to the peer device to accept the security request.
+    case ESP_GAP_BLE_SEC_REQ_EVT:
+      /* send the positive(true) security response to the peer device to accept the security request.
 			 If not accept the security request, should sent the security response with negative(false) accept value*/
-			 log_i("ESP_GAP_BLE_SEC_REQ_EVT");
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-			if(BLEDevice::m_securityCallbacks!=nullptr){
-				esp_ble_gap_security_rsp(param->ble_security.ble_req.bd_addr, BLEDevice::m_securityCallbacks->onSecurityRequest());
-			}
-			else{
-				esp_ble_gap_security_rsp(param->ble_security.ble_req.bd_addr, true);
-			}
-#endif	// CONFIG_BLE_SMP_ENABLE
-			break;
-			 /*
+      log_i("ESP_GAP_BLE_SEC_REQ_EVT");
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+      if (BLEDevice::m_securityCallbacks != nullptr) {
+        esp_ble_gap_security_rsp(param->ble_security.ble_req.bd_addr, BLEDevice::m_securityCallbacks->onSecurityRequest());
+      } else {
+        esp_ble_gap_security_rsp(param->ble_security.ble_req.bd_addr, true);
+      }
+#endif  // CONFIG_BLE_SMP_ENABLE
+      break;
+      /*
 			  *
 			  */
-		 case ESP_GAP_BLE_PASSKEY_NOTIF_EVT:  //the app will receive this evt when the IO  has Output capability and the peer device IO has Input capability.
-			 //display the passkey number to the user to input it in the peer deivce within 30 seconds
-			 log_i("ESP_GAP_BLE_PASSKEY_NOTIF_EVT");
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-			log_i("passKey = %d", param->ble_security.key_notif.passkey);
-			if(BLEDevice::m_securityCallbacks!=nullptr){
-				BLEDevice::m_securityCallbacks->onPassKeyNotify(param->ble_security.key_notif.passkey);
-			}
-#endif	// CONFIG_BLE_SMP_ENABLE
-			 break;
-		 case ESP_GAP_BLE_KEY_EVT:
-			 //shows the ble key type info share with peer device to the user.
-			 log_d("ESP_GAP_BLE_KEY_EVT");
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-			 log_i("key type = %s", BLESecurity::esp_key_type_to_str(param->ble_security.ble_key.key_type));
-#endif	// CONFIG_BLE_SMP_ENABLE
-			 break;
-		 case ESP_GAP_BLE_AUTH_CMPL_EVT:
-			 log_i("ESP_GAP_BLE_AUTH_CMPL_EVT");
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-			 if(BLEDevice::m_securityCallbacks != nullptr){
-				 BLEDevice::m_securityCallbacks->onAuthenticationComplete(param->ble_security.auth_cmpl);
-			 }
-#endif	// CONFIG_BLE_SMP_ENABLE
-			 break;
-		default: {
-			break;
-		}
-	} // switch
-
-	if (BLEDevice::m_pClient != nullptr) {
-		BLEDevice::m_pClient->handleGAPEvent(event, param);
-	}
-
-	if (BLEDevice::m_pScan != nullptr) {
-		BLEDevice::getScan()->handleGAPEvent(event, param);
-	}
-
-	if(m_bleAdvertising != nullptr) {
-		BLEDevice::getAdvertising()->handleGAPEvent(event, param);
-	}
-
-	if(m_customGapHandler != nullptr) {
-		BLEDevice::m_customGapHandler(event, param);
-	}
-
-} // gapEventHandler
-
+    case ESP_GAP_BLE_PASSKEY_NOTIF_EVT:  //the app will receive this evt when the IO  has Output capability and the peer device IO has Input capability.
+      //display the passkey number to the user to input it in the peer device within 30 seconds
+      log_i("ESP_GAP_BLE_PASSKEY_NOTIF_EVT");
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+      log_i("passKey = %d", param->ble_security.key_notif.passkey);
+      if (BLEDevice::m_securityCallbacks != nullptr) {
+        BLEDevice::m_securityCallbacks->onPassKeyNotify(param->ble_security.key_notif.passkey);
+      }
+#endif  // CONFIG_BLE_SMP_ENABLE
+      break;
+    case ESP_GAP_BLE_KEY_EVT:
+      //shows the ble key type info share with peer device to the user.
+      log_d("ESP_GAP_BLE_KEY_EVT");
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+      log_i("key type = %s", BLESecurity::esp_key_type_to_str(param->ble_security.ble_key.key_type));
+#endif  // CONFIG_BLE_SMP_ENABLE
+      break;
+    case ESP_GAP_BLE_AUTH_CMPL_EVT: log_i("ESP_GAP_BLE_AUTH_CMPL_EVT");
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+      if (BLEDevice::m_securityCallbacks != nullptr) {
+        BLEDevice::m_securityCallbacks->onAuthenticationComplete(param->ble_security.auth_cmpl);
+      }
+#endif  // CONFIG_BLE_SMP_ENABLE
+      break;
+    default:
+    {
+      break;
+    }
+  }  // switch
+
+  if (BLEDevice::m_pClient != nullptr) {
+    BLEDevice::m_pClient->handleGAPEvent(event, param);
+  }
+
+  if (BLEDevice::m_pScan != nullptr) {
+    BLEDevice::getScan()->handleGAPEvent(event, param);
+  }
+
+  if (m_bleAdvertising != nullptr) {
+    BLEDevice::getAdvertising()->handleGAPEvent(event, param);
+  }
+
+  if (m_customGapHandler != nullptr) {
+    BLEDevice::m_customGapHandler(event, param);
+  }
+
+}  // gapEventHandler
 
 /**
  * @brief Get the BLE device address.
  * @return The BLE device address.
  */
 /* STATIC*/ BLEAddress BLEDevice::getAddress() {
-	const uint8_t* bdAddr = esp_bt_dev_get_address();
-	esp_bd_addr_t addr;
-	memcpy(addr, bdAddr, sizeof(addr));
-	return BLEAddress(addr);
-} // getAddress
-
+  const uint8_t *bdAddr = esp_bt_dev_get_address();
+  esp_bd_addr_t addr;
+  memcpy(addr, bdAddr, sizeof(addr));
+  return BLEAddress(addr);
+}  // getAddress
 
 /**
  * @brief Retrieve the Scan object that we use for scanning.
  * @return The scanning object reference.  This is a singleton object.  The caller should not
  * try and release/delete it.
  */
-/* STATIC */ BLEScan* BLEDevice::getScan() {
-	//log_v(">> getScan");
-	if (m_pScan == nullptr) {
-		m_pScan = new BLEScan();
-		//log_d(" - creating a new scan object");
-	}
-	//log_v("<< getScan: Returning object at 0x%x", (uint32_t)m_pScan);
-	return m_pScan;
-} // getScan
-
+/* STATIC */ BLEScan *BLEDevice::getScan() {
+  //log_v(">> getScan");
+  if (m_pScan == nullptr) {
+    m_pScan = new BLEScan();
+    //log_d(" - creating a new scan object");
+  }
+  //log_v("<< getScan: Returning object at 0x%x", (uint32_t)m_pScan);
+  return m_pScan;
+}  // getScan
 
 /**
  * @brief Get the value of a characteristic of a service on a remote device.
@@ -315,120 +291,121 @@ gatts_event_handler BLEDevice::m_customGattsHandler = nullptr;
  * @param [in] serviceUUID
  * @param [in] characteristicUUID
  */
-/* STATIC */ std::string BLEDevice::getValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID) {
-	log_v(">> getValue: bdAddress: %s, serviceUUID: %s, characteristicUUID: %s", bdAddress.toString().c_str(), serviceUUID.toString().c_str(), characteristicUUID.toString().c_str());
-	BLEClient* pClient = createClient();
-	pClient->connect(bdAddress);
-	std::string ret = pClient->getValue(serviceUUID, characteristicUUID);
-	pClient->disconnect();
-	log_v("<< getValue");
-	return ret;
-} // getValue
-
+/* STATIC */ String BLEDevice::getValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID) {
+  log_v(
+    ">> getValue: bdAddress: %s, serviceUUID: %s, characteristicUUID: %s", bdAddress.toString().c_str(), serviceUUID.toString().c_str(),
+    characteristicUUID.toString().c_str()
+  );
+  BLEClient *pClient = createClient();
+  pClient->connect(bdAddress);
+  String ret = pClient->getValue(serviceUUID, characteristicUUID);
+  pClient->disconnect();
+  log_v("<< getValue");
+  return ret;
+}  // getValue
 
 /**
  * @brief Initialize the %BLE environment.
  * @param deviceName The device name of the device.
  */
-/* STATIC */ void BLEDevice::init(std::string deviceName) {
-	if(!initialized){
-		initialized = true; // Set the initialization flag to ensure we are only initialized once.
+/* STATIC */ void BLEDevice::init(String deviceName) {
+  if (!initialized) {
+    initialized = true;  // Set the initialization flag to ensure we are only initialized once.
 
-		esp_err_t errRc = ESP_OK;
+    esp_err_t errRc = ESP_OK;
 #ifdef ARDUINO_ARCH_ESP32
-		if (!btStart()) {
-			errRc = ESP_FAIL;
-			return;
-		}
+    if (!btStart()) {
+      errRc = ESP_FAIL;
+      return;
+    }
 #else
-		errRc = ::nvs_flash_init();
-		if (errRc != ESP_OK) {
-			log_e("nvs_flash_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		}
-
-#ifndef CLASSIC_BT_ENABLED
-		esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT);  
+    errRc = ::nvs_flash_init();
+    if (errRc != ESP_OK) {
+      log_e("nvs_flash_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return;
+    }
+
+#ifndef CONFIG_BT_CLASSIC_ENABLED
+    esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT);
 #endif
-		esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
-		errRc = esp_bt_controller_init(&bt_cfg);
-		if (errRc != ESP_OK) {
-			log_e("esp_bt_controller_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		}
-
-#ifndef CLASSIC_BT_ENABLED
-		errRc = esp_bt_controller_enable(ESP_BT_MODE_BLE);
-		if (errRc != ESP_OK) {
-			log_e("esp_bt_controller_enable: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		}
+    esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
+    errRc = esp_bt_controller_init(&bt_cfg);
+    if (errRc != ESP_OK) {
+      log_e("esp_bt_controller_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return;
+    }
+
+#ifndef CONFIG_BT_CLASSIC_ENABLED
+    errRc = esp_bt_controller_enable(ESP_BT_MODE_BLE);
+    if (errRc != ESP_OK) {
+      log_e("esp_bt_controller_enable: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return;
+    }
 #else
-		errRc = esp_bt_controller_enable(ESP_BT_MODE_BTDM);
-		if (errRc != ESP_OK) {
-			log_e("esp_bt_controller_enable: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		}
+    errRc = esp_bt_controller_enable(ESP_BT_MODE_BTDM);
+    if (errRc != ESP_OK) {
+      log_e("esp_bt_controller_enable: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return;
+    }
 #endif
 #endif
 
-		esp_bluedroid_status_t bt_state = esp_bluedroid_get_status();
-		if (bt_state == ESP_BLUEDROID_STATUS_UNINITIALIZED) {
-			errRc = esp_bluedroid_init();
-			if (errRc != ESP_OK) {
-				log_e("esp_bluedroid_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-				return;
-			}
-		}
-
-		if (bt_state != ESP_BLUEDROID_STATUS_ENABLED) {
-			errRc = esp_bluedroid_enable();
-			if (errRc != ESP_OK) {
-				log_e("esp_bluedroid_enable: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-				return;
-			}
-		}
-
-		errRc = esp_ble_gap_register_callback(BLEDevice::gapEventHandler);
-		if (errRc != ESP_OK) {
-			log_e("esp_ble_gap_register_callback: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		}
-
-#ifdef CONFIG_GATTC_ENABLE   // Check that BLE client is configured in make menuconfig
-		errRc = esp_ble_gattc_register_callback(BLEDevice::gattClientEventHandler);
-		if (errRc != ESP_OK) {
-			log_e("esp_ble_gattc_register_callback: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		}
-#endif   // CONFIG_GATTC_ENABLE
+    esp_bluedroid_status_t bt_state = esp_bluedroid_get_status();
+    if (bt_state == ESP_BLUEDROID_STATUS_UNINITIALIZED) {
+      errRc = esp_bluedroid_init();
+      if (errRc != ESP_OK) {
+        log_e("esp_bluedroid_init: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+        return;
+      }
+    }
+
+    if (bt_state != ESP_BLUEDROID_STATUS_ENABLED) {
+      errRc = esp_bluedroid_enable();
+      if (errRc != ESP_OK) {
+        log_e("esp_bluedroid_enable: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+        return;
+      }
+    }
+
+    errRc = esp_ble_gap_register_callback(BLEDevice::gapEventHandler);
+    if (errRc != ESP_OK) {
+      log_e("esp_ble_gap_register_callback: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return;
+    }
+
+#ifdef CONFIG_GATTC_ENABLE  // Check that BLE client is configured in make menuconfig
+    errRc = esp_ble_gattc_register_callback(BLEDevice::gattClientEventHandler);
+    if (errRc != ESP_OK) {
+      log_e("esp_ble_gattc_register_callback: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return;
+    }
+#endif  // CONFIG_GATTC_ENABLE
 
 #ifdef CONFIG_GATTS_ENABLE  // Check that BLE server is configured in make menuconfig
-		errRc = esp_ble_gatts_register_callback(BLEDevice::gattServerEventHandler);
-		if (errRc != ESP_OK) {
-			log_e("esp_ble_gatts_register_callback: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		}
-#endif   // CONFIG_GATTS_ENABLE
-
-		errRc = ::esp_ble_gap_set_device_name(deviceName.c_str());
-		if (errRc != ESP_OK) {
-			log_e("esp_ble_gap_set_device_name: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		};
-
-#ifdef CONFIG_BLE_SMP_ENABLE   // Check that BLE SMP (security) is configured in make menuconfig
-		esp_ble_io_cap_t iocap = ESP_IO_CAP_NONE;
-		errRc = ::esp_ble_gap_set_security_param(ESP_BLE_SM_IOCAP_MODE, &iocap, sizeof(uint8_t));
-		if (errRc != ESP_OK) {
-			log_e("esp_ble_gap_set_security_param: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-			return;
-		};
-#endif // CONFIG_BLE_SMP_ENABLE
-	}
-	vTaskDelay(200 / portTICK_PERIOD_MS); // Delay for 200 msecs as a workaround to an apparent Arduino environment issue.
-} // init
-
+    errRc = esp_ble_gatts_register_callback(BLEDevice::gattServerEventHandler);
+    if (errRc != ESP_OK) {
+      log_e("esp_ble_gatts_register_callback: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return;
+    }
+#endif  // CONFIG_GATTS_ENABLE
+
+    errRc = ::esp_ble_gap_set_device_name(deviceName.c_str());
+    if (errRc != ESP_OK) {
+      log_e("esp_ble_gap_set_device_name: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return;
+    };
+
+#ifdef CONFIG_BLE_SMP_ENABLE  // Check that BLE SMP (security) is configured in make menuconfig
+    esp_ble_io_cap_t iocap = ESP_IO_CAP_NONE;
+    errRc = ::esp_ble_gap_set_security_param(ESP_BLE_SM_IOCAP_MODE, &iocap, sizeof(uint8_t));
+    if (errRc != ESP_OK) {
+      log_e("esp_ble_gap_set_security_param: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+      return;
+    };
+#endif  // CONFIG_BLE_SMP_ENABLE
+  }
+  vTaskDelay(200 / portTICK_PERIOD_MS);  // Delay for 200 msecs as a workaround to an apparent Arduino environment issue.
+}  // init
 
 /**
  * @brief Set the transmission power.
@@ -459,14 +436,13 @@ gatts_event_handler BLEDevice::m_customGattsHandler = nullptr;
  * @param [in] powerLevel.
  */
 /* STATIC */ void BLEDevice::setPower(esp_power_level_t powerLevel, esp_ble_power_type_t powerType) {
-	log_v(">> setPower: %d (type: %d)", powerLevel, powerType);
-	esp_err_t errRc = ::esp_ble_tx_power_set(powerType, powerLevel);
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_tx_power_set: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-	};
-	log_v("<< setPower");
-} // setPower
-
+  log_v(">> setPower: %d (type: %d)", powerLevel, powerType);
+  esp_err_t errRc = ::esp_ble_tx_power_set(powerType, powerLevel);
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_tx_power_set: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+  };
+  log_v("<< setPower");
+}  // setPower
 
 /**
  * @brief Set the value of a characteristic of a service on a remote device.
@@ -474,66 +450,74 @@ gatts_event_handler BLEDevice::m_customGattsHandler = nullptr;
  * @param [in] serviceUUID
  * @param [in] characteristicUUID
  */
-/* STATIC */ void BLEDevice::setValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID, std::string value) {
-	log_v(">> setValue: bdAddress: %s, serviceUUID: %s, characteristicUUID: %s", bdAddress.toString().c_str(), serviceUUID.toString().c_str(), characteristicUUID.toString().c_str());
-	BLEClient* pClient = createClient();
-	pClient->connect(bdAddress);
-	pClient->setValue(serviceUUID, characteristicUUID, value);
-	pClient->disconnect();
-} // setValue
-
+/* STATIC */ void BLEDevice::setValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID, String value) {
+  log_v(
+    ">> setValue: bdAddress: %s, serviceUUID: %s, characteristicUUID: %s", bdAddress.toString().c_str(), serviceUUID.toString().c_str(),
+    characteristicUUID.toString().c_str()
+  );
+  BLEClient *pClient = createClient();
+  pClient->connect(bdAddress);
+  pClient->setValue(serviceUUID, characteristicUUID, value);
+  pClient->disconnect();
+}  // setValue
 
 /**
  * @brief Return a string representation of the nature of this device.
  * @return A string representation of the nature of this device.
  */
-/* STATIC */ std::string BLEDevice::toString() {
-	std::string res = "BD Address: " + getAddress().toString();
-	return res;
-} // toString
-
+/* STATIC */ String BLEDevice::toString() {
+  String res = "BD Address: " + getAddress().toString();
+  return res;
+}  // toString
 
 /**
  * @brief Add an entry to the BLE white list.
  * @param [in] address The address to add to the white list.
  */
 void BLEDevice::whiteListAdd(BLEAddress address) {
-	log_v(">> whiteListAdd: %s", address.toString().c_str());
-	esp_err_t errRc = esp_ble_gap_update_whitelist(true, *address.getNative());  // True to add an entry.
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gap_update_whitelist: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-	}
-	log_v("<< whiteListAdd");
-} // whiteListAdd
-
+  log_v(">> whiteListAdd: %s", address.toString().c_str());
+#ifdef ESP_IDF_VERSION_MAJOR
+  esp_err_t errRc = esp_ble_gap_update_whitelist(true, *address.getNative(), BLE_WL_ADDR_TYPE_PUBLIC);  // HACK!!! True to add an entry.
+#else
+  esp_err_t errRc = esp_ble_gap_update_whitelist(true, *address.getNative());  // True to add an entry.
+#endif
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gap_update_whitelist: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+  }
+  log_v("<< whiteListAdd");
+}  // whiteListAdd
 
 /**
  * @brief Remove an entry from the BLE white list.
  * @param [in] address The address to remove from the white list.
  */
 void BLEDevice::whiteListRemove(BLEAddress address) {
-	log_v(">> whiteListRemove: %s", address.toString().c_str());
-	esp_err_t errRc = esp_ble_gap_update_whitelist(false, *address.getNative());  // False to remove an entry.
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gap_update_whitelist: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-	}
-	log_v("<< whiteListRemove");
-} // whiteListRemove
+  log_v(">> whiteListRemove: %s", address.toString().c_str());
+#ifdef ESP_IDF_VERSION_MAJOR
+  esp_err_t errRc = esp_ble_gap_update_whitelist(false, *address.getNative(), BLE_WL_ADDR_TYPE_PUBLIC);  // HACK!!! False to remove an entry.
+#else
+  esp_err_t errRc = esp_ble_gap_update_whitelist(false, *address.getNative());  // False to remove an entry.
+#endif
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gap_update_whitelist: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+  }
+  log_v("<< whiteListRemove");
+}  // whiteListRemove
 
 /*
  * @brief Set encryption level that will be negotiated with peer device durng connection
  * @param [in] level Requested encryption level
  */
 void BLEDevice::setEncryptionLevel(esp_ble_sec_act_t level) {
-	BLEDevice::m_securityLevel = level;
+  BLEDevice::m_securityLevel = level;
 }
 
 /*
  * @brief Set callbacks that will be used to handle encryption negotiation events and authentication events
  * @param [in] cllbacks Pointer to BLESecurityCallbacks class callback
  */
-void BLEDevice::setSecurityCallbacks(BLESecurityCallbacks* callbacks) {
-	BLEDevice::m_securityCallbacks = callbacks;
+void BLEDevice::setSecurityCallbacks(BLESecurityCallbacks *callbacks) {
+  BLEDevice::m_securityCallbacks = callbacks;
 }
 
 /*
@@ -541,90 +525,92 @@ void BLEDevice::setSecurityCallbacks(BLESecurityCallbacks* callbacks) {
  * @param [in] mtu Value to set local mtu, should be larger than 23 and lower or equal to 517
  */
 esp_err_t BLEDevice::setMTU(uint16_t mtu) {
-	log_v(">> setLocalMTU: %d", mtu);
-	esp_err_t err = esp_ble_gatt_set_local_mtu(mtu);
-	if (err == ESP_OK) {
-		m_localMTU = mtu;
-	} else {
-		log_e("can't set local mtu value: %d", mtu);
-	}
-	log_v("<< setLocalMTU");
-	return err;
+  log_v(">> setLocalMTU: %d", mtu);
+  esp_err_t err = esp_ble_gatt_set_local_mtu(mtu);
+  if (err == ESP_OK) {
+    m_localMTU = mtu;
+  } else {
+    log_e("can't set local mtu value: %d", mtu);
+  }
+  log_v("<< setLocalMTU");
+  return err;
 }
 
 /*
  * @brief Get local MTU value set during mtu request or default value
  */
 uint16_t BLEDevice::getMTU() {
-	return m_localMTU;
+  return m_localMTU;
 }
 
 bool BLEDevice::getInitialized() {
-	return initialized;
+  return initialized;
 }
 
-BLEAdvertising* BLEDevice::getAdvertising() {
-	if(m_bleAdvertising == nullptr) {
-		m_bleAdvertising = new BLEAdvertising();
-		log_i("create advertising");
-	}
-	log_d("get advertising");
-	return m_bleAdvertising; 
+BLEAdvertising *BLEDevice::getAdvertising() {
+  if (m_bleAdvertising == nullptr) {
+    m_bleAdvertising = new BLEAdvertising();
+    log_i("create advertising");
+  }
+  log_d("get advertising");
+  return m_bleAdvertising;
 }
 
 void BLEDevice::startAdvertising() {
-	log_v(">> startAdvertising");
-	getAdvertising()->start();
-	log_v("<< startAdvertising");
-} // startAdvertising
+  log_v(">> startAdvertising");
+  getAdvertising()->start();
+  log_v("<< startAdvertising");
+}  // startAdvertising
 
 void BLEDevice::stopAdvertising() {
-    log_v(">> stopAdvertising");
-    getAdvertising()->stop();
-    log_v("<< stopAdvertising");
-} // stopAdvertising
+  log_v(">> stopAdvertising");
+  getAdvertising()->stop();
+  log_v("<< stopAdvertising");
+}  // stopAdvertising
 
 /* multi connect support */
 /* requires a little more work */
 std::map<uint16_t, conn_status_t> BLEDevice::getPeerDevices(bool _client) {
-	return m_connectedClientsMap;
+  return m_connectedClientsMap;
 }
 
-BLEClient* BLEDevice::getClientByGattIf(uint16_t conn_id) {
-	return (BLEClient*)m_connectedClientsMap.find(conn_id)->second.peer_device;
+BLEClient *BLEDevice::getClientByGattIf(uint16_t conn_id) {
+  return (BLEClient *)m_connectedClientsMap.find(conn_id)->second.peer_device;
 }
 
-void BLEDevice::updatePeerDevice(void* peer, bool _client, uint16_t conn_id) {
-	log_d("update conn_id: %d, GATT role: %s", conn_id, _client? "client":"server");
-	std::map<uint16_t, conn_status_t>::iterator it = m_connectedClientsMap.find(ESP_GATT_IF_NONE);
-	if (it != m_connectedClientsMap.end()) {
-		std::swap(m_connectedClientsMap[conn_id], it->second);
-		m_connectedClientsMap.erase(it);
-	}else{
-		it = m_connectedClientsMap.find(conn_id);
-		if (it != m_connectedClientsMap.end()) {
-			conn_status_t _st = it->second;
-			_st.peer_device = peer;
-			std::swap(m_connectedClientsMap[conn_id], _st);
-		}
-	}
+void BLEDevice::updatePeerDevice(void *peer, bool _client, uint16_t conn_id) {
+  log_d("update conn_id: %d, GATT role: %s", conn_id, _client ? "client" : "server");
+  std::map<uint16_t, conn_status_t>::iterator it = m_connectedClientsMap.find(ESP_GATT_IF_NONE);
+  if (it != m_connectedClientsMap.end()) {
+    std::swap(m_connectedClientsMap[conn_id], it->second);
+    m_connectedClientsMap.erase(it);
+  } else {
+    it = m_connectedClientsMap.find(conn_id);
+    if (it != m_connectedClientsMap.end()) {
+      conn_status_t _st = it->second;
+      _st.peer_device = peer;
+      std::swap(m_connectedClientsMap[conn_id], _st);
+    }
+  }
 }
 
-void BLEDevice::addPeerDevice(void* peer, bool _client, uint16_t conn_id) {
-	log_i("add conn_id: %d, GATT role: %s", conn_id, _client? "client":"server");
-	conn_status_t status = {
-		.peer_device = peer,
-		.connected = true,
-		.mtu = 23
-	};
+void BLEDevice::addPeerDevice(void *peer, bool _client, uint16_t conn_id) {
+  log_i("add conn_id: %d, GATT role: %s", conn_id, _client ? "client" : "server");
+  conn_status_t status = {.peer_device = peer, .connected = true, .mtu = 23};
 
-	m_connectedClientsMap.insert(std::pair<uint16_t, conn_status_t>(conn_id, status));
+  m_connectedClientsMap.insert(std::pair<uint16_t, conn_status_t>(conn_id, status));
 }
 
+//there may have some situation that invoking this function simultaneously, that will cause CORRUPT HEAP
+//let this function serializable
+portMUX_TYPE BLEDevice::mux = portMUX_INITIALIZER_UNLOCKED;
 void BLEDevice::removePeerDevice(uint16_t conn_id, bool _client) {
-	log_i("remove: %d, GATT role %s", conn_id, _client?"client":"server");
-	if(m_connectedClientsMap.find(conn_id) != m_connectedClientsMap.end())
-		m_connectedClientsMap.erase(conn_id);
+  portENTER_CRITICAL(&mux);
+  log_i("remove: %d, GATT role %s", conn_id, _client ? "client" : "server");
+  if (m_connectedClientsMap.find(conn_id) != m_connectedClientsMap.end()) {
+    m_connectedClientsMap.erase(conn_id);
+  }
+  portEXIT_CRITICAL(&mux);
 }
 
 /* multi connect support */
@@ -634,31 +620,35 @@ void BLEDevice::removePeerDevice(uint16_t conn_id, bool _client) {
  * @param release_memory release the internal BT stack memory
  */
 /* STATIC */ void BLEDevice::deinit(bool release_memory) {
-    if (!initialized) return;
-
-    esp_bluedroid_disable();
-    esp_bluedroid_deinit();
-    esp_bt_controller_disable();
-    esp_bt_controller_deinit();
+  if (!initialized) {
+    return;
+  }
+
+  esp_bluedroid_disable();
+  esp_bluedroid_deinit();
+  esp_bt_controller_disable();
+  esp_bt_controller_deinit();
 #ifdef ARDUINO_ARCH_ESP32
-    if (release_memory) {
-        esp_bt_controller_mem_release(ESP_BT_MODE_BTDM);  // <-- require tests because we released classic BT memory and this can cause crash (most likely not, esp-idf takes care of it)
-    } else {
-        initialized = false;   
-    } 
+  if (release_memory) {
+    esp_bt_controller_mem_release(ESP_BT_MODE_BTDM
+    );  // <-- require tests because we released classic BT memory and this can cause crash (most likely not, esp-idf takes care of it)
+  } else {
+    initialized = false;
+  }
 #endif
 }
 
 void BLEDevice::setCustomGapHandler(gap_event_handler handler) {
-	m_customGapHandler = handler;
+  m_customGapHandler = handler;
 }
 
 void BLEDevice::setCustomGattcHandler(gattc_event_handler handler) {
-	m_customGattcHandler = handler;
+  m_customGattcHandler = handler;
 }
 
 void BLEDevice::setCustomGattsHandler(gatts_event_handler handler) {
-	m_customGattsHandler = handler;
+  m_customGattsHandler = handler;
 }
 
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEDevice.h b/libraries/BLE/src/BLEDevice.h
index 4ecdf04c97c..01bf143c101 100644
--- a/libraries/BLE/src/BLEDevice.h
+++ b/libraries/BLE/src/BLEDevice.h
@@ -7,11 +7,14 @@
 
 #ifndef MAIN_BLEDevice_H_
 #define MAIN_BLEDevice_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
-#include <esp_gap_ble_api.h> // ESP32 BLE
-#include <esp_gattc_api.h>   // ESP32 BLE
-#include <map>               // Part of C++ STL
+#if defined(CONFIG_BLUEDROID_ENABLED)
+#include <esp_gap_ble_api.h>  // ESP32 BLE
+#include <esp_gattc_api.h>    // ESP32 BLE
+#include <map>                // Part of C++ STL
 #include <string>
 #include <esp_bt.h>
 
@@ -24,77 +27,72 @@
 /**
  * @brief BLE functions.
  */
-typedef void (*gap_event_handler)(esp_gap_ble_cb_event_t  event, esp_ble_gap_cb_param_t* param);
-typedef void (*gattc_event_handler)(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t* param);
-typedef void (*gatts_event_handler)(esp_gatts_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gatts_cb_param_t* param);
+typedef void (*gap_event_handler)(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param);
+typedef void (*gattc_event_handler)(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *param);
+typedef void (*gatts_event_handler)(esp_gatts_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gatts_cb_param_t *param);
 
 class BLEDevice {
 public:
-
-	static BLEClient*  createClient();    // Create a new BLE client.
-	static BLEServer*  createServer();    // Cretae a new BLE server.
-	static BLEAddress  getAddress();      // Retrieve our own local BD address.
-	static BLEScan*    getScan();         // Get the scan object
-	static std::string getValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID);	  // Get the value of a characteristic of a service on a server.
-	static void        init(std::string deviceName);   // Initialize the local BLE environment.
-	static void        setPower(esp_power_level_t powerLevel, esp_ble_power_type_t powerType=ESP_BLE_PWR_TYPE_DEFAULT);  // Set our power level.
-	static void        setValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID, std::string value);   // Set the value of a characteristic on a service on a server.
-	static std::string toString();        // Return a string representation of our device.
-	static void        whiteListAdd(BLEAddress address);    // Add an entry to the BLE white list.
-	static void        whiteListRemove(BLEAddress address); // Remove an entry from the BLE white list.
-	static void		   setEncryptionLevel(esp_ble_sec_act_t level);
-	static void		   setSecurityCallbacks(BLESecurityCallbacks* pCallbacks);
-	static esp_err_t   setMTU(uint16_t mtu);
-	static uint16_t	   getMTU();
-	static bool        getInitialized(); // Returns the state of the device, is it initialized or not?
-	/* move advertising to BLEDevice for saving ram and flash in beacons */
-	static BLEAdvertising* 	getAdvertising();
-	static void		   		startAdvertising();
-	static void		   		stopAdvertising();
-	static uint16_t 	m_appId;
-	/* multi connect */
-	static std::map<uint16_t, conn_status_t> getPeerDevices(bool client);
-	static void addPeerDevice(void* peer, bool is_client, uint16_t conn_id);
-	static void updatePeerDevice(void* peer, bool _client, uint16_t conn_id);
-	static void removePeerDevice(uint16_t conn_id, bool client);
-	static BLEClient* getClientByGattIf(uint16_t conn_id);
-	static void setCustomGapHandler(gap_event_handler handler);
-	static void setCustomGattcHandler(gattc_event_handler handler);
-	static void setCustomGattsHandler(gatts_event_handler handler);
-	static void deinit(bool release_memory = false);
-	static uint16_t		m_localMTU;
-	static esp_ble_sec_act_t 	m_securityLevel;
+  static BLEClient *createClient();                                                               // Create a new BLE client.
+  static BLEServer *createServer();                                                               // Create a new BLE server.
+  static BLEAddress getAddress();                                                                 // Retrieve our own local BD address.
+  static BLEScan *getScan();                                                                      // Get the scan object
+  static String getValue(BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID);  // Get the value of a characteristic of a service on a server.
+  static void init(String deviceName);                                                            // Initialize the local BLE environment.
+  static void setPower(esp_power_level_t powerLevel, esp_ble_power_type_t powerType = ESP_BLE_PWR_TYPE_DEFAULT);  // Set our power level.
+  static void setValue(
+    BLEAddress bdAddress, BLEUUID serviceUUID, BLEUUID characteristicUUID, String value
+  );                                                // Set the value of a characteristic on a service on a server.
+  static String toString();                         // Return a string representation of our device.
+  static void whiteListAdd(BLEAddress address);     // Add an entry to the BLE white list.
+  static void whiteListRemove(BLEAddress address);  // Remove an entry from the BLE white list.
+  static void setEncryptionLevel(esp_ble_sec_act_t level);
+  static void setSecurityCallbacks(BLESecurityCallbacks *pCallbacks);
+  static esp_err_t setMTU(uint16_t mtu);
+  static uint16_t getMTU();
+  static bool getInitialized();  // Returns the state of the device, is it initialized or not?
+  /* move advertising to BLEDevice for saving ram and flash in beacons */
+  static BLEAdvertising *getAdvertising();
+  static void startAdvertising();
+  static void stopAdvertising();
+  static uint16_t m_appId;
+  /* multi connect */
+  static std::map<uint16_t, conn_status_t> getPeerDevices(bool client);
+  static void addPeerDevice(void *peer, bool is_client, uint16_t conn_id);
+  static void updatePeerDevice(void *peer, bool _client, uint16_t conn_id);
+  static void removePeerDevice(uint16_t conn_id, bool client);
+  static BLEClient *getClientByGattIf(uint16_t conn_id);
+  static void setCustomGapHandler(gap_event_handler handler);
+  static void setCustomGattcHandler(gattc_event_handler handler);
+  static void setCustomGattsHandler(gatts_event_handler handler);
+  static void deinit(bool release_memory = false);
+  static uint16_t m_localMTU;
+  static esp_ble_sec_act_t m_securityLevel;
 
 private:
-	static BLEServer*	m_pServer;
-	static BLEScan*		m_pScan;
-	static BLEClient*	m_pClient;
-	static BLESecurityCallbacks* m_securityCallbacks;
-	static BLEAdvertising* m_bleAdvertising;
-	static esp_gatt_if_t getGattcIF();
-	static std::map<uint16_t, conn_status_t> m_connectedClientsMap;	
+  static BLEServer *m_pServer;
+  static BLEScan *m_pScan;
+  static BLEClient *m_pClient;
+  static BLESecurityCallbacks *m_securityCallbacks;
+  static BLEAdvertising *m_bleAdvertising;
+  static esp_gatt_if_t getGattcIF();
+  static std::map<uint16_t, conn_status_t> m_connectedClientsMap;
+  static portMUX_TYPE mux;
 
-	static void gattClientEventHandler(
-		esp_gattc_cb_event_t      event,
-		esp_gatt_if_t             gattc_if,
-		esp_ble_gattc_cb_param_t* param);
+  static void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *param);
 
-	static void gattServerEventHandler(
-	   esp_gatts_cb_event_t      event,
-	   esp_gatt_if_t             gatts_if,
-	   esp_ble_gatts_cb_param_t* param);
+  static void gattServerEventHandler(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
 
-	static void gapEventHandler(
-		esp_gap_ble_cb_event_t  event,
-		esp_ble_gap_cb_param_t* param);
+  static void gapEventHandler(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param);
 
 public:
-/* custom gap and gatt handlers for flexibility */
-	static gap_event_handler m_customGapHandler;
-	static gattc_event_handler m_customGattcHandler;
-	static gatts_event_handler m_customGattsHandler;
+  /* custom gap and gatt handlers for flexibility */
+  static gap_event_handler m_customGapHandler;
+  static gattc_event_handler m_customGattcHandler;
+  static gatts_event_handler m_customGattsHandler;
 
-}; // class BLE
+};  // class BLE
 
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* MAIN_BLEDevice_H_ */
diff --git a/libraries/BLE/src/BLEEddystoneTLM.cpp b/libraries/BLE/src/BLEEddystoneTLM.cpp
index accc4db1bb3..1a301f09011 100644
--- a/libraries/BLE/src/BLEEddystoneTLM.cpp
+++ b/libraries/BLE/src/BLEEddystoneTLM.cpp
@@ -7,140 +7,174 @@
  *  Fix temperature value (8.8 fixed format)
  *  Fix time stamp (0.1 second resolution)
  *  Fixes based on EddystoneTLM frame specification https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md
- * 
+ *
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <string.h>
 #include <stdio.h>
 #include "esp32-hal-log.h"
 #include "BLEEddystoneTLM.h"
 
 static const char LOG_TAG[] = "BLEEddystoneTLM";
-#define ENDIAN_CHANGE_U16(x) ((((x)&0xFF00)>>8) + (((x)&0xFF)<<8))
-#define ENDIAN_CHANGE_U32(x) ((((x)&0xFF000000)>>24) + (((x)&0x00FF0000)>>8)) + ((((x)&0xFF00)<<8) + (((x)&0xFF)<<24))
 
 BLEEddystoneTLM::BLEEddystoneTLM() {
-	beaconUUID = 0xFEAA;
-	m_eddystoneData.frameType = EDDYSTONE_TLM_FRAME_TYPE;
-	m_eddystoneData.version = 0;
-	m_eddystoneData.volt = 3300; // 3300mV = 3.3V
-	m_eddystoneData.temp = (uint16_t) ((float) 23.00)/256;
-	m_eddystoneData.advCount = 0;
-	m_eddystoneData.tmil = 0;
-} // BLEEddystoneTLM
-
-std::string BLEEddystoneTLM::getData() {
-	return std::string((char*) &m_eddystoneData, sizeof(m_eddystoneData));
-} // getData
+  m_eddystoneData.frameType = EDDYSTONE_TLM_FRAME_TYPE;
+  m_eddystoneData.version = 0;
+  m_eddystoneData.volt = 3300;  // 3300mV = 3.3V
+  m_eddystoneData.temp = (uint16_t)((float)23.00) / 256;
+  m_eddystoneData.advCount = 0;
+  m_eddystoneData.tmil = 0;
+}  // BLEEddystoneTLM
+
+BLEEddystoneTLM::BLEEddystoneTLM(BLEAdvertisedDevice *advertisedDevice) {
+  char *payload = (char *)advertisedDevice->getPayload();
+  for (int i = 0; i < advertisedDevice->getPayloadLength(); ++i) {
+    if (payload[i] == 0x16 && advertisedDevice->getPayloadLength() >= i + 2 + sizeof(m_eddystoneData) && payload[i + 1] == 0xAA && payload[i + 2] == 0xFE
+        && payload[i + 3] == 0x20) {
+      log_d("Eddystone TLM data frame starting at byte [%d]", i + 3);
+      setData(String(payload + i + 3, sizeof(m_eddystoneData)));
+      break;
+    }
+  }
+}
+
+String BLEEddystoneTLM::getData() {
+  return String((char *)&m_eddystoneData, sizeof(m_eddystoneData));
+}  // getData
 
 BLEUUID BLEEddystoneTLM::getUUID() {
-	return BLEUUID(beaconUUID);
-} // getUUID
+  return beaconUUID;
+}  // getUUID
 
 uint8_t BLEEddystoneTLM::getVersion() {
-	return m_eddystoneData.version;
-} // getVersion
+  return m_eddystoneData.version;
+}  // getVersion
 
 uint16_t BLEEddystoneTLM::getVolt() {
-	return ENDIAN_CHANGE_U16(m_eddystoneData.volt);
-} // getVolt
+  return ENDIAN_CHANGE_U16(m_eddystoneData.volt);
+}  // getVolt
 
 float BLEEddystoneTLM::getTemp() {
-	return ENDIAN_CHANGE_U16(m_eddystoneData.temp) / 256.0f;
-} // getTemp
+  return EDDYSTONE_TEMP_U16_TO_FLOAT(m_eddystoneData.temp);
+}  // getTemp
+
+uint16_t BLEEddystoneTLM::getRawTemp() {
+  return ENDIAN_CHANGE_U16(m_eddystoneData.temp);
+}  // getRawTemp
 
 uint32_t BLEEddystoneTLM::getCount() {
-	return ENDIAN_CHANGE_U32(m_eddystoneData.advCount);
-} // getCount
+  return ENDIAN_CHANGE_U32(m_eddystoneData.advCount);
+}  // getCount
 
 uint32_t BLEEddystoneTLM::getTime() {
-	return (ENDIAN_CHANGE_U32(m_eddystoneData.tmil)) / 10;
-} // getTime
+  return (ENDIAN_CHANGE_U32(m_eddystoneData.tmil)) / 10;
+}  // getTime
 
-std::string BLEEddystoneTLM::toString() {
-  std::string out = "";
+String BLEEddystoneTLM::toString() {
+  String out = "";
   uint32_t rawsec = ENDIAN_CHANGE_U32(m_eddystoneData.tmil);
   char val[12];
 
-  out += "Version "; // + std::string(m_eddystoneData.version);
-  snprintf(val, sizeof(val), "%d", m_eddystoneData.version);
-  out += val;
+  out += "Version " + String(m_eddystoneData.version);
+  //snprintf(val, sizeof(val), "%d", m_eddystoneData.version);
+  //out += val;
   out += "\n";
-  out += "Battery Voltage "; // + ENDIAN_CHANGE_U16(m_eddystoneData.volt);
+  out += "Battery Voltage ";  // + ENDIAN_CHANGE_U16(m_eddystoneData.volt);
   snprintf(val, sizeof(val), "%d", ENDIAN_CHANGE_U16(m_eddystoneData.volt));
   out += val;
   out += " mV\n";
 
   out += "Temperature ";
-  snprintf(val, sizeof(val), "%.2f", ENDIAN_CHANGE_U16(m_eddystoneData.temp) / 256.0f);
+  snprintf(val, sizeof(val), "%.2f", ((int16_t)ENDIAN_CHANGE_U16(m_eddystoneData.temp)) / 256.0f);
   out += val;
   out += " C\n";
 
   out += "Adv. Count ";
-  snprintf(val, sizeof(val), "%d", ENDIAN_CHANGE_U32(m_eddystoneData.advCount));
+  snprintf(val, sizeof(val), "%ld", ENDIAN_CHANGE_U32(m_eddystoneData.advCount));
   out += val;
   out += "\n";
 
   out += "Time in seconds ";
-  snprintf(val, sizeof(val), "%d", rawsec/10);
+  snprintf(val, sizeof(val), "%ld", rawsec / 10);
   out += val;
   out += "\n";
 
   out += "Time ";
 
-  snprintf(val, sizeof(val), "%04d", rawsec / 864000);
+  snprintf(val, sizeof(val), "%04ld", rawsec / 864000);
   out += val;
   out += ".";
 
-  snprintf(val, sizeof(val), "%02d", (rawsec / 36000) % 24);
+  snprintf(val, sizeof(val), "%02ld", (rawsec / 36000) % 24);
   out += val;
   out += ":";
 
-  snprintf(val, sizeof(val), "%02d", (rawsec / 600) % 60);
+  snprintf(val, sizeof(val), "%02ld", (rawsec / 600) % 60);
   out += val;
   out += ":";
 
-  snprintf(val, sizeof(val), "%02d", (rawsec / 10) % 60);
+  snprintf(val, sizeof(val), "%02ld", (rawsec / 10) % 60);
   out += val;
   out += "\n";
 
   return out;
-} // toString
+}  // toString
 
 /**
  * Set the raw data for the beacon record.
+ * Example:
+ * uint8_t *payload = advertisedDevice.getPayload();
+ * eddystoneTLM.setData(String((char*)payload+22, advertisedDevice.getPayloadLength() - 22));
+ * Note: the offset 22 works for current implementation of example BLE_EddystoneTLM Beacon.ino, however
+ *   the position is not static and it is programmers responsibility to align the data.
+ * Data frame:
+ * | Field  || Len | Type | UUID        | EddyStone TLM |
+ * | Offset || 0   | 1    | 2           | 4             |
+ * | Len    || 1 B | 1 B  | 2 B         | 14 B          |
+ * | Data   || ??  | ??   | 0xAA | 0xFE | ???           |
+ *
+ * EddyStone TLM frame:
+ * | Field  || Type  | Version | Batt mV     | Beacon temp | Cnt since boot | Time since boot |
+ * | Offset || 0     | 1       | 2           | 4           | 6              | 10              |
+ * | Len    || 1 B   | 1 B     | 2 B         | 2 B         | 4 B            | 4 B             |
+ * | Data   || 0x20  | ??      | ??   | ??   | ??    | ??  |   |   |   |    |   |   |   |     |
  */
-void BLEEddystoneTLM::setData(std::string data) {
-	if (data.length() != sizeof(m_eddystoneData)) {
-		log_e("Unable to set the data ... length passed in was %d and expected %d", data.length(), sizeof(m_eddystoneData));
-		return;
-	}
-  memcpy(&m_eddystoneData, data.data(), data.length());
-} // setData
+void BLEEddystoneTLM::setData(String data) {
+  if (data.length() != sizeof(m_eddystoneData)) {
+    log_e("Unable to set the data ... length passed in was %d and expected %d", data.length(), sizeof(m_eddystoneData));
+    return;
+  }
+  memcpy(&m_eddystoneData, data.c_str(), data.length());
+}  // setData
 
 void BLEEddystoneTLM::setUUID(BLEUUID l_uuid) {
-	beaconUUID = l_uuid.getNative()->uuid.uuid16;
-} // setUUID
+  beaconUUID = l_uuid;
+}  // setUUID
 
 void BLEEddystoneTLM::setVersion(uint8_t version) {
-	m_eddystoneData.version = version;
-} // setVersion
+  m_eddystoneData.version = version;
+}  // setVersion
 
+// Set voltage in ESP32 native Big endian and convert it to little endian used for BLE Frame
 void BLEEddystoneTLM::setVolt(uint16_t volt) {
-	m_eddystoneData.volt = volt;
-} // setVolt
+  m_eddystoneData.volt = ENDIAN_CHANGE_U16(volt);
+}  // setVolt
 
 void BLEEddystoneTLM::setTemp(float temp) {
-	m_eddystoneData.temp = (uint16_t)temp;
-} // setTemp
+  m_eddystoneData.temp = EDDYSTONE_TEMP_FLOAT_TO_U16(temp);
+}  // setTemp
 
 void BLEEddystoneTLM::setCount(uint32_t advCount) {
-	m_eddystoneData.advCount = advCount;
-} // setCount
+  m_eddystoneData.advCount = advCount;
+}  // setCount
 
 void BLEEddystoneTLM::setTime(uint32_t tmil) {
-	m_eddystoneData.tmil = tmil;
-} // setTime
+  m_eddystoneData.tmil = tmil;
+}  // setTime
 
-#endif
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEEddystoneTLM.cppwithheadder b/libraries/BLE/src/BLEEddystoneTLM.cppwithheadder
new file mode 100644
index 00000000000..07002dbab1f
--- /dev/null
+++ b/libraries/BLE/src/BLEEddystoneTLM.cppwithheadder
@@ -0,0 +1,202 @@
+/*
+ * BLEEddystoneTLM.cpp
+ *
+ *  Created on: Mar 12, 2018
+ *      Author: pcbreflux
+ *  Edited on: Mar 20, 2020 by beegee-tokyo
+ *  Fix temperature value (8.8 fixed format)
+ *  Fix time stamp (0.1 second resolution)
+ *  Fixes based on EddystoneTLM frame specification https://github.com/google/eddystone/blob/master/eddystone-tlm/tlm-plain.md
+ *
+ */
+#include "sdkconfig.h"
+#if defined(CONFIG_BLUEDROID_ENABLED)
+#include <string.h>
+#include <stdio.h>
+#include "esp32-hal-log.h"
+#include "BLEEddystoneTLM.h"
+
+static const char LOG_TAG[] = "BLEEddystoneTLM";
+
+BLEEddystoneTLM::BLEEddystoneTLM() {
+  m_eddystoneData.frameType = EDDYSTONE_TLM_FRAME_TYPE;
+  m_eddystoneData.version = 0;
+  m_eddystoneData.volt = 3300; // 3300mV = 3.3V
+  m_eddystoneData.temp = (uint16_t) ((float) 23.00)/256;
+  m_eddystoneData.advCount = 0;
+  m_eddystoneData.tmil = 0;
+  _initHeadder();
+} // BLEEddystoneTLM
+
+BLEEddystoneTLM::BLEEddystoneTLM(BLEAdvertisedDevice *advertisedDevice){
+  char* payload = (char*)advertisedDevice->getPayload();
+  for(int i = 0; i < advertisedDevice->getPayloadLength(); ++i){
+    if(payload[i] == 0x16 && advertisedDevice->getPayloadLength() >= i+2+sizeof(m_eddystoneData) && payload[i+1] == 0xAA && payload[i+2] == 0xFE && payload[i+3] == 0x20){
+      log_d("Eddystone TLM data frame starting at byte [%d]", i+3);
+      setData(std::string(payload+i+3, sizeof(m_eddystoneData)));
+      break;
+    }
+  }
+  _initHeadder();
+}
+
+String BLEEddystoneTLM::getData() {
+  return String((char*) &m_eddystoneData, sizeof(m_eddystoneData));
+} // getData
+
+BLEUUID BLEEddystoneTLM::getUUID() {
+  return beaconUUID;
+} // getUUID
+
+uint8_t BLEEddystoneTLM::getVersion() {
+  return m_eddystoneData.version;
+} // getVersion
+
+uint16_t BLEEddystoneTLM::getVolt() {
+  return ENDIAN_CHANGE_U16(m_eddystoneData.volt);
+} // getVolt
+
+float BLEEddystoneTLM::getTemp() {
+  return EDDYSTONE_TEMP_U16_TO_FLOAT(m_eddystoneData.temp);
+} // getTemp
+
+uint16_t BLEEddystoneTLM::getRawTemp() {
+  return ENDIAN_CHANGE_U16(m_eddystoneData.temp);
+} // getRawTemp
+
+uint32_t BLEEddystoneTLM::getCount() {
+  return ENDIAN_CHANGE_U32(m_eddystoneData.advCount);
+} // getCount
+
+uint32_t BLEEddystoneTLM::getTime() {
+  return (ENDIAN_CHANGE_U32(m_eddystoneData.tmil)) / 10;
+} // getTime
+
+String  BLEEddystoneTLM::getFrame(){
+  String frame(BLEHeadder);
+  frame += String((char*) &m_eddystoneData, sizeof(m_eddystoneData));
+  log_d("Compiled frame of length %d Bytes", frame.length());
+  for(int i = 0; i < frame.length(); ++i){
+    log_d("[%d]=0x%02X",i, frame[i]);
+  }
+  return frame;
+} // getServiceData
+
+String BLEEddystoneTLM::toString() {
+  String out = "";
+  uint32_t rawsec = ENDIAN_CHANGE_U32(m_eddystoneData.tmil);
+  char val[12];
+
+  out += "Version "; // + std::string(m_eddystoneData.version);
+  snprintf(val, sizeof(val), "%d", m_eddystoneData.version);
+  out += val;
+  out += "\n";
+  out += "Battery Voltage "; // + ENDIAN_CHANGE_U16(m_eddystoneData.volt);
+  snprintf(val, sizeof(val), "%d", ENDIAN_CHANGE_U16(m_eddystoneData.volt));
+  out += val;
+  out += " mV\n";
+
+  out += "Temperature ";
+  snprintf(val, sizeof(val), "%.2f", ((int16_t)ENDIAN_CHANGE_U16(m_eddystoneData.temp)) / 256.0f);
+  out += val;
+  out += " C\n";
+
+  out += "Adv. Count ";
+  snprintf(val, sizeof(val), "%d", ENDIAN_CHANGE_U32(m_eddystoneData.advCount));
+  out += val;
+  out += "\n";
+
+  out += "Time in seconds ";
+  snprintf(val, sizeof(val), "%d", rawsec/10);
+  out += val;
+  out += "\n";
+
+  out += "Time ";
+
+  snprintf(val, sizeof(val), "%04d", rawsec / 864000);
+  out += val;
+  out += ".";
+
+  snprintf(val, sizeof(val), "%02d", (rawsec / 36000) % 24);
+  out += val;
+  out += ":";
+
+  snprintf(val, sizeof(val), "%02d", (rawsec / 600) % 60);
+  out += val;
+  out += ":";
+
+  snprintf(val, sizeof(val), "%02d", (rawsec / 10) % 60);
+  out += val;
+  out += "\n";
+
+  return out;
+} // toString
+
+/**
+ * Set the raw data for the beacon record.
+ * Example:
+ * uint8_t *payload = advertisedDevice.getPayload();
+ * eddystoneTLM.setData(std::string((char*)payload+22, advertisedDevice.getPayloadLength() - 22));
+ * Note: the offset 22 works for current implementation of example BLE_EddystoneTLM Beacon.ino, however
+ *   the position is not static and it is programmers responsibility to align the data.
+ * Data frame:
+ * | Field  || Len | Type | UUID        | EddyStone TLM |
+ * | Offset || 0   | 1    | 2           | 4             |
+ * | Len    || 1 B | 1 B  | 2 B         | 14 B          |
+ * | Data   || ??  | ??   | 0xAA | 0xFE | ???           |
+ *
+ * EddyStone TLM frame:
+ * | Field  || Type  | Version | Batt mV     | Beacon temp | Cnt since boot | Time since boot |
+ * | Offset || 0     | 1       | 2           | 4           | 6              | 10              |
+ * | Len    || 1 B   | 1 B     | 2 B         | 2 B         | 4 B            | 4 B             |
+ * | Data   || 0x20  | ??      | ??   | ??   | ??    | ??  |   |   |   |    |   |   |   |     |
+ */
+void BLEEddystoneTLM::setData(std::string data) {
+  if (data.length() != sizeof(m_eddystoneData)) {
+    log_e("Unable to set the data ... length passed in was %d and expected %d", data.length(), sizeof(m_eddystoneData));
+    return;
+  }
+  memcpy(&m_eddystoneData, data.data(), data.length());
+} // setData
+
+void BLEEddystoneTLM::setUUID(BLEUUID l_uuid) {
+  beaconUUID = l_uuid;
+} // setUUID
+
+void BLEEddystoneTLM::setVersion(uint8_t version) {
+  m_eddystoneData.version = version;
+} // setVersion
+
+// Set voltage in ESP32 native Big endian and convert it to little endian used for BLE Frame
+void BLEEddystoneTLM::setVolt(uint16_t volt) {
+  m_eddystoneData.volt = ENDIAN_CHANGE_U16(volt);
+} // setVolt
+
+void BLEEddystoneTLM::setTemp(float temp) {
+  m_eddystoneData.temp = EDDYSTONE_TEMP_FLOAT_TO_U16(temp);
+} // setTemp
+
+void BLEEddystoneTLM::setCount(uint32_t advCount) {
+  m_eddystoneData.advCount = advCount;
+} // setCount
+
+void BLEEddystoneTLM::setTime(uint32_t tmil) {
+  m_eddystoneData.tmil = tmil;
+} // setTime
+
+void BLEEddystoneTLM::_initHeadder(){
+  BLEHeadder[0]  = 0x02; // Len
+  BLEHeadder[1]  = 0x01; // Type Flags
+  BLEHeadder[2]  = 0x06; // GENERAL_DISC_MODE 0x02 | BR_EDR_NOT_SUPPORTED 0x04
+  BLEHeadder[3]  = 0x03; // Len
+  BLEHeadder[4]  = 0x03; // Type 16-Bit UUID
+  BLEHeadder[5]  = 0xAA; // Eddystone UUID 2 -> 0xFEAA LSB
+  BLEHeadder[6]  = 0xFE; // Eddystone UUID 1 MSB
+  BLEHeadder[7]  = 0x11; // Length of TLM Beacon Data is constant 17 B (not counting the length field itself)
+  BLEHeadder[8]  = 0x16; // Type Service Data
+  BLEHeadder[9]  = 0xAA; // Eddystone UUID 2 -> 0xFEAA LSB
+  BLEHeadder[10] = 0xFE; // Eddystone UUID 1 MSB
+  BLEHeadder[11] = 0x20; // Eddystone Frame Type - TLM
+}
+
+#endif
diff --git a/libraries/BLE/src/BLEEddystoneTLM.h b/libraries/BLE/src/BLEEddystoneTLM.h
index a93e224fdf0..3981af4a4a9 100644
--- a/libraries/BLE/src/BLEEddystoneTLM.h
+++ b/libraries/BLE/src/BLEEddystoneTLM.h
@@ -7,9 +7,17 @@
 
 #ifndef _BLEEddystoneTLM_H_
 #define _BLEEddystoneTLM_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "BLEUUID.h"
+#include <BLEAdvertisedDevice.h>
 
-#define EDDYSTONE_TLM_FRAME_TYPE 0x20
+#define EDDYSTONE_TLM_FRAME_TYPE               0x20
+#define ENDIAN_CHANGE_U16(x)                   ((((x) & 0xFF00) >> 8) + (((x) & 0xFF) << 8))
+#define ENDIAN_CHANGE_U32(x)                   ((((x) & 0xFF000000) >> 24) + (((x) & 0x00FF0000) >> 8)) + ((((x) & 0xFF00) << 8) + (((x) & 0xFF) << 24))
+#define EDDYSTONE_TEMP_U16_TO_FLOAT(tempU16)   (((int16_t)ENDIAN_CHANGE_U16(tempU16)) / 256.0f)
+#define EDDYSTONE_TEMP_FLOAT_TO_U16(tempFloat) (ENDIAN_CHANGE_U16(((int)((tempFloat) * 256))))
 
 /**
  * @brief Representation of a beacon.
@@ -18,34 +26,36 @@
  */
 class BLEEddystoneTLM {
 public:
-	BLEEddystoneTLM();
-	std::string getData();
-	BLEUUID	 getUUID();
-	uint8_t	 getVersion();
-	uint16_t	getVolt();
-	float	   getTemp();
-	uint32_t	getCount();
-	uint32_t	getTime();
-	std::string toString();
-	void		setData(std::string data);
-	void		setUUID(BLEUUID l_uuid);
-	void		setVersion(uint8_t version);
-	void		setVolt(uint16_t volt);
-	void		setTemp(float temp);
-	void		setCount(uint32_t advCount);
-	void		setTime(uint32_t tmil);
+  BLEEddystoneTLM();
+  BLEEddystoneTLM(BLEAdvertisedDevice *advertisedDevice);
+  String getData();
+  BLEUUID getUUID();
+  uint8_t getVersion();
+  uint16_t getVolt();
+  float getTemp();
+  uint16_t getRawTemp();
+  uint32_t getCount();
+  uint32_t getTime();
+  String toString();
+  void setData(String data);
+  void setUUID(BLEUUID l_uuid);
+  void setVersion(uint8_t version);
+  void setVolt(uint16_t volt);
+  void setTemp(float temp);
+  void setCount(uint32_t advCount);
+  void setTime(uint32_t tmil);
 
 private:
-	uint16_t beaconUUID;
-	struct {
-		uint8_t frameType;
-		uint8_t version;
-		uint16_t volt;
-		uint16_t temp;
-		uint32_t advCount;
-		uint32_t tmil;
-	} __attribute__((packed)) m_eddystoneData;
-
-}; // BLEEddystoneTLM
+  BLEUUID beaconUUID;
+  struct {
+    uint8_t frameType;
+    uint8_t version;
+    uint16_t volt;
+    uint16_t temp;
+    uint32_t advCount;
+    uint32_t tmil;
+  } __attribute__((packed)) m_eddystoneData;
+};  // BLEEddystoneTLM
 
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* _BLEEddystoneTLM_H_ */
diff --git a/libraries/BLE/src/BLEEddystoneURL.cpp b/libraries/BLE/src/BLEEddystoneURL.cpp
index 19a56b28b79..ddee8af0b30 100644
--- a/libraries/BLE/src/BLEEddystoneURL.cpp
+++ b/libraries/BLE/src/BLEEddystoneURL.cpp
@@ -3,146 +3,291 @@
  *
  *  Created on: Mar 12, 2018
  *      Author: pcbreflux
+ *  Upgraded on: Feb 20, 2023
+ *      By: Tomas Pilny
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <string.h>
 #include "esp32-hal-log.h"
 #include "BLEEddystoneURL.h"
 
-static const char LOG_TAG[] = "BLEEddystoneURL";
+String EDDYSTONE_URL_PREFIX[] = {
+  "http://www.",   // 0x00
+  "https://www.",  // 0x01
+  "http://",       // 0x02
+  "https://",      // 0x03
+  ""               // Any other code number results in empty string
+};
+
+String EDDYSTONE_URL_SUFFIX[] = {
+  ".com/",   // 0x00
+  ".org/",   // 0x01
+  ".edu/",   // 0x02
+  ".net/",   // 0x03
+  ".info/",  // 0x04
+  ".biz/",   // 0x05
+  ".gov/",   // 0x06
+  ".com",    // 0x07
+  ".org",    // 0x08
+  ".edu",    // 0x09
+  ".net",    // 0x0A
+  ".info",   // 0x0B
+  ".biz",    // 0x0C
+  ".gov",    // 0x0D
+  ""         // Any other code number results in empty string
+};
 
 BLEEddystoneURL::BLEEddystoneURL() {
-	beaconUUID = 0xFEAA;
-	lengthURL = 0;
-	m_eddystoneData.frameType = EDDYSTONE_URL_FRAME_TYPE;
-	m_eddystoneData.advertisedTxPower = 0;
-	memset(m_eddystoneData.url, 0, sizeof(m_eddystoneData.url));
-} // BLEEddystoneURL
+  lengthURL = 0;
+  m_eddystoneData.advertisedTxPower = 0;
+  memset(m_eddystoneData.url, 0, sizeof(m_eddystoneData.url));
+  _initHeadder();
+}  // BLEEddystoneURL
+
+BLEEddystoneURL::BLEEddystoneURL(BLEAdvertisedDevice *advertisedDevice) {
+  const char *payload = (char *)advertisedDevice->getPayload();
+  memset(m_eddystoneData.url, 0, sizeof(m_eddystoneData.url));
+  lengthURL = 0;
+  m_eddystoneData.advertisedTxPower = 0;
+  for (int i = 0; i < advertisedDevice->getPayloadLength(); ++i) {
+    if (payload[i] == 0x16 && advertisedDevice->getPayloadLength() >= i + 2 + sizeof(m_eddystoneData) && payload[i + 1] == 0xAA && payload[i + 2] == 0xFE
+        && payload[i + 3] == 0x10) {
+      lengthURL = payload[i - 1] - 5;  // Subtracting 5 Bytes containing header and other data which are not actual URL data
+      m_eddystoneData.advertisedTxPower = payload[i + 1];
+      if (lengthURL <= 18) {
+        setData(String(payload + i + 4, lengthURL + 1));
+      } else {
+        log_e("Too long URL %d", lengthURL);
+      }
+    }
+  }
+  _initHeadder();
+}
+
+String BLEEddystoneURL::getData() {
+  return String((char *)&m_eddystoneData, sizeof(m_eddystoneData));
+}  // getData
+
+String BLEEddystoneURL::getFrame() {
+  BLEHeadder[7] = lengthURL + 5;  // Fill in real: Type + 2B UUID + Frame Type + Tx power + URL (note: the Byte holding the length does not count itself)
+  String frame(BLEHeadder, sizeof(BLEHeadder));
+  frame += String((char *)&m_eddystoneData, lengthURL + 1);  // + 1 for TX power
 
-std::string BLEEddystoneURL::getData() {
-	return std::string((char*) &m_eddystoneData, sizeof(m_eddystoneData));
-} // getData
+  return frame;
+}  // getFrame
 
 BLEUUID BLEEddystoneURL::getUUID() {
-	return BLEUUID(beaconUUID);
-} // getUUID
+  uint16_t uuid = (((uint16_t)BLEHeadder[10]) << 8) | BLEHeadder[9];
+  return BLEUUID(uuid);
+}  // getUUID
 
 int8_t BLEEddystoneURL::getPower() {
-	return m_eddystoneData.advertisedTxPower;
-} // getPower
-
-std::string BLEEddystoneURL::getURL() {
-	return std::string((char*) &m_eddystoneData.url, sizeof(m_eddystoneData.url));
-} // getURL
-
-std::string BLEEddystoneURL::getDecodedURL() {
-	std::string decodedURL = "";
-
-	switch (m_eddystoneData.url[0]) {
-		case 0x00:
-			decodedURL += "http://www.";
-			break;
-		case 0x01:
-			decodedURL += "https://www.";
-			break;
-		case 0x02:
-			decodedURL += "http://";
-			break;
-		case 0x03:
-			decodedURL += "https://";
-			break;
-		default:
-			decodedURL += m_eddystoneData.url[0];
-	}
-
-	for (int i = 1; i < lengthURL; i++) {
-		if (m_eddystoneData.url[i] > 33 && m_eddystoneData.url[i] < 127) {
-			decodedURL += m_eddystoneData.url[i];
-		} else {
-			switch (m_eddystoneData.url[i]) {
-				case 0x00:
-					decodedURL += ".com/";
-					break;
-				case 0x01:
-					decodedURL += ".org/";
-					break;
-				case 0x02:
-					decodedURL += ".edu/";
-					break;
-				case 0x03:
-					decodedURL += ".net/";
-					break;
-				case 0x04:
-					decodedURL += ".info/";
-					break;
-				case 0x05:
-					decodedURL += ".biz/";
-					break;
-				case 0x06:
-					decodedURL += ".gov/";
-					break;
-				case 0x07:
-					decodedURL += ".com";
-					break;
-				case 0x08:
-					decodedURL += ".org";
-					break;
-				case 0x09:
-					decodedURL += ".edu";
-					break;
-				case 0x0A:
-					decodedURL += ".net";
-					break;
-				case 0x0B:
-					decodedURL += ".info";
-					break;
-				case 0x0C:
-					decodedURL += ".biz";
-					break;
-				case 0x0D:
-					decodedURL += ".gov";
-					break;
-				default:
-					break;
-			}
-		}
-	}
-	return decodedURL;
-} // getDecodedURL
+  return m_eddystoneData.advertisedTxPower;
+}  // getPower
 
+String BLEEddystoneURL::getURL() {
+  return String((char *)&m_eddystoneData.url, lengthURL);
+}  // getURL
 
+String BLEEddystoneURL::getPrefix() {
+  if (m_eddystoneData.url[0] <= 0x03) {
+    return EDDYSTONE_URL_PREFIX[m_eddystoneData.url[0]];
+  } else {
+    return "";
+  }
+}
+
+String BLEEddystoneURL::getSuffix() {
+  if (m_eddystoneData.url[lengthURL - 1] <= 0x0D) {
+    return EDDYSTONE_URL_SUFFIX[m_eddystoneData.url[lengthURL - 1]];
+  } else {
+    return "";
+  }
+}
+
+String BLEEddystoneURL::getDecodedURL() {
+  std::string decodedURL = "";
+  decodedURL += getPrefix().c_str();
+  if (decodedURL.length() == 0) {  // No prefix extracted - interpret byte [0] as character
+    decodedURL += (char)m_eddystoneData.url[0];
+  }
+  for (int i = 1; i < lengthURL; i++) {
+    if (m_eddystoneData.url[i] >= 33 && m_eddystoneData.url[i] < 127) {
+      decodedURL += (char)m_eddystoneData.url[i];
+    } else {
+      if (i != lengthURL - 1 || m_eddystoneData.url[i] > 0x0D) {  // Ignore last Byte and values used for suffix
+        log_e("Unexpected unprintable char in URL 0x%02X: m_eddystoneData.url[%d]", m_eddystoneData.url[i], i);
+      }
+    }
+  }
+  decodedURL += getSuffix().c_str();
+  return String(decodedURL.c_str());
+}  // getDecodedURL
 
 /**
  * Set the raw data for the beacon record.
+ * Example:
+ * uint8_t *payload = advertisedDevice.getPayload();
+ * eddystoneTLM.setData(String((char*)payload+11, advertisedDevice.getPayloadLength() - 11));
+ * Note: the offset 11 works for current implementation of example BLE_EddystoneTLM Beacon.ino, however
+ *   the position is not static and it is programmers responsibility to align the data.
+ * Data frame:
+ * | Field  || Len | Type | UUID        | EddyStone URL |
+ * | Offset || 0   | 1    | 2           | 4             |
+ * | Len    || 1 B | 1 B  | 2 B         | up to 20 B    |
+ * | Data   || ??  | ??   | 0xAA | 0xFE | ???           |
+ *
+ * EddyStone TLM frame:
+ * | Field  || Type  | TX Power | URL prefix | URL    |
+ * | Offset || 0     | 1        | 2          | 3      |
+ * | Len    || 1 B   | 1 B      | 1 B        | 0-17 B |
+ * | Data   || 0x10  | ??       | ??         | ??     |
  */
-void BLEEddystoneURL::setData(std::string data) {
-	if (data.length() > sizeof(m_eddystoneData)) {
-		log_e("Unable to set the data ... length passed in was %d and max expected %d", data.length(), sizeof(m_eddystoneData));
-		return;
-	}
-	memset(&m_eddystoneData, 0, sizeof(m_eddystoneData));
-	memcpy(&m_eddystoneData, data.data(), data.length());
-	lengthURL = data.length() - (sizeof(m_eddystoneData) - sizeof(m_eddystoneData.url));
-} // setData
+void BLEEddystoneURL::setData(String data) {
+  if (data.length() > sizeof(m_eddystoneData)) {
+    log_e("Unable to set the data ... length passed in was %d and max expected %d", data.length(), sizeof(m_eddystoneData));
+    return;
+  }
+  memset(&m_eddystoneData, 0, sizeof(m_eddystoneData));
+  memcpy(&m_eddystoneData, data.c_str(), data.length());
+  lengthURL = data.length() - (sizeof(m_eddystoneData) - sizeof(m_eddystoneData.url));
+}  // setData
 
 void BLEEddystoneURL::setUUID(BLEUUID l_uuid) {
-	beaconUUID = l_uuid.getNative()->uuid.uuid16;
-} // setUUID
+  uint16_t beaconUUID = l_uuid.getNative()->uuid.uuid16;
+  BLEHeadder[10] = beaconUUID >> 8;
+  BLEHeadder[9] = beaconUUID & 0x00FF;
+}  // setUUID
+
+void BLEEddystoneURL::setPower(esp_power_level_t advertisedTxPower) {
+  int tx_power;
+  switch (advertisedTxPower) {
+    case ESP_PWR_LVL_N12:  // 12dbm
+      tx_power = -12;
+      break;
+    case ESP_PWR_LVL_N9:  // -9dbm
+      tx_power = -9;
+      break;
+    case ESP_PWR_LVL_N6:  // -6dbm
+      tx_power = -6;
+      break;
+    case ESP_PWR_LVL_N3:  // -3dbm
+      tx_power = -3;
+      break;
+    case ESP_PWR_LVL_N0:  //  0dbm
+      tx_power = 0;
+      break;
+    case ESP_PWR_LVL_P3:  // +3dbm
+      tx_power = +3;
+      break;
+    case ESP_PWR_LVL_P6:  // +6dbm
+      tx_power = +6;
+      break;
+    case ESP_PWR_LVL_P9:  // +9dbm
+      tx_power = +9;
+      break;
+    default: tx_power = 0;
+  }
+  m_eddystoneData.advertisedTxPower = int8_t((tx_power - -100) / 2);
+}  // setPower
 
 void BLEEddystoneURL::setPower(int8_t advertisedTxPower) {
-	m_eddystoneData.advertisedTxPower = advertisedTxPower;
-} // setPower
+  m_eddystoneData.advertisedTxPower = advertisedTxPower;
+}  // setPower
 
-void BLEEddystoneURL::setURL(std::string url) {
+// Set URL bytes including prefix and optional suffix
+// | Field   | Prefix  | URL + optional Suffix |
+// | Offset  | 0       | 1                     |
+// | Length  | 1 B     | 0 - 17 B              |
+// | Example | 0x02    | 0x676F6F676C65 0x07   |
+// | Decoded | http:// |   g o o g l e  .com   |
+void BLEEddystoneURL::setURL(String url) {
   if (url.length() > sizeof(m_eddystoneData.url)) {
-	log_e("Unable to set the url ... length passed in was %d and max expected %d", url.length(), sizeof(m_eddystoneData.url));
-	return;
+    log_e("Unable to set the url ... length passed in was %d and max expected %d", url.length(), sizeof(m_eddystoneData.url));
+    return;
   }
   memset(m_eddystoneData.url, 0, sizeof(m_eddystoneData.url));
-  memcpy(m_eddystoneData.url, url.data(), url.length());
+  memcpy(m_eddystoneData.url, url.c_str(), url.length());
   lengthURL = url.length();
-} // setURL
+}  // setURL
+
+int BLEEddystoneURL::setSmartURL(String url) {
+  if (url.length() == 0) {
+    log_e("URL String has 0 length");
+    return 0;  // ERROR
+  }
+  for (auto character : url) {
+    if (!isPrintable(character)) {
+      log_e("URL contains unprintable character(s)");
+      return 0;  // ERROR
+    }
+  }
+  bool hasPrefix = false;
+  bool hasSuffix = false;
+  m_eddystoneData.url[0] = 0x00;  // Init with default prefix "http://www."
+  uint8_t suffix = 0x0E;          // Init with empty string
+  log_d("Encode url \"%s\" with length %d", url.c_str(), url.length());
+  for (uint8_t i = 0; i < 4; ++i) {
+    if (url.substring(0, EDDYSTONE_URL_PREFIX[i].length()) == EDDYSTONE_URL_PREFIX[i]) {
+      m_eddystoneData.url[0] = i;
+      hasPrefix = true;
+      break;
+    }
+  }
+
+  if (hasPrefix == false) {
+    log_w("Prefix not found - using default prefix \"http://www.\" = 0x00\n\tNote: URL must contain one of the prefixes: \"http://www.\", \"https://www.\", "
+          "\"http://\", \"https://\"");
+  }
+
+  for (uint8_t i = 0; i < 0x0E; ++i) {
+    std::string std_url(url.c_str());
+    std::string std_suffix(EDDYSTONE_URL_SUFFIX[i].c_str());
+    size_t found_pos = std_url.find(std_suffix);
+    if (found_pos != std::string::npos) {
+      hasSuffix = true;
+      suffix = i;
+      break;
+    }
+  }
+
+  size_t baseUrlLen = url.length() - (hasPrefix ? EDDYSTONE_URL_PREFIX[m_eddystoneData.url[0]].length() : 0) - EDDYSTONE_URL_SUFFIX[suffix].length();
+  lengthURL = baseUrlLen + 1 + (hasSuffix ? 1 : 0);
+  if (lengthURL > 18) {
+    log_e("Encoded URL is too long %d B - max 18 B", lengthURL);
+    return 0;  // ERROR
+  }
+  String baseUrl = url.substring(
+    (hasPrefix ? EDDYSTONE_URL_PREFIX[m_eddystoneData.url[0]].length() : 0),
+    baseUrlLen + (hasPrefix ? EDDYSTONE_URL_PREFIX[m_eddystoneData.url[0]].length() : 0)
+  );
+  memcpy((void *)(m_eddystoneData.url + 1), (void *)baseUrl.c_str(), baseUrl.length());  // substr for Arduino String
+
+  if (hasSuffix) {
+    m_eddystoneData.url[1 + baseUrlLen] = suffix;
+  }
+
+  return 1;  // OK
+}  // setSmartURL
 
+void BLEEddystoneURL::_initHeadder() {
+  BLEHeadder[0] = 0x02;   // Len
+  BLEHeadder[1] = 0x01;   // Type Flags
+  BLEHeadder[2] = 0x06;   // GENERAL_DISC_MODE 0x02 | BR_EDR_NOT_SUPPORTED 0x04
+  BLEHeadder[3] = 0x03;   // Len
+  BLEHeadder[4] = 0x03;   // Type 16-Bit UUID
+  BLEHeadder[5] = 0xAA;   // Eddystone UUID 2 -> 0xFEAA LSB
+  BLEHeadder[6] = 0xFE;   // Eddystone UUID 1 MSB
+  BLEHeadder[7] = 0x00;   // Length of Beacon Data shall be calculated later
+  BLEHeadder[8] = 0x16;   // Type Service Data
+  BLEHeadder[9] = 0xAA;   // Eddystone UUID 2 -> 0xFEAA LSB
+  BLEHeadder[10] = 0xFE;  // Eddystone UUID 1 MSB
+  BLEHeadder[11] = 0x10;  // Eddystone Frame Type - URL
+}
 
 #endif
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEEddystoneURL.h b/libraries/BLE/src/BLEEddystoneURL.h
index 0b538c07d00..92668eb6855 100644
--- a/libraries/BLE/src/BLEEddystoneURL.h
+++ b/libraries/BLE/src/BLEEddystoneURL.h
@@ -3,14 +3,25 @@
  *
  *  Created on: Mar 12, 2018
  *      Author: pcbreflux
+ *  Upgraded on: Feb 20, 2023
+ *      By: Tomas Pilny
+ *
  */
 
 #ifndef _BLEEddystoneURL_H_
 #define _BLEEddystoneURL_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "BLEUUID.h"
+#include <BLEAdvertisedDevice.h>
+#include "esp_bt.h"
 
 #define EDDYSTONE_URL_FRAME_TYPE 0x10
 
+extern String EDDYSTONE_URL_PREFIX[];
+extern String EDDYSTONE_URL_SUFFIX[];
+
 /**
  * @brief Representation of a beacon.
  * See:
@@ -18,26 +29,33 @@
  */
 class BLEEddystoneURL {
 public:
-	BLEEddystoneURL();
-	std::string getData();
-	BLEUUID	 getUUID();
-	int8_t	  getPower();
-	std::string getURL();
-	std::string getDecodedURL();
-	void		setData(std::string data);
-	void		setUUID(BLEUUID l_uuid);
-	void		setPower(int8_t advertisedTxPower);
-	void		setURL(std::string url);
+  BLEEddystoneURL();
+  BLEEddystoneURL(BLEAdvertisedDevice *advertisedDevice);
+  String getData();
+  String getFrame();
+  BLEUUID getUUID();
+  int8_t getPower();
+  String getURL();
+  String getPrefix();
+  String getSuffix();
+  String getDecodedURL();
+  void setData(String data);
+  void setUUID(BLEUUID l_uuid);
+  void setPower(int8_t advertisedTxPower);
+  void setPower(esp_power_level_t advertisedTxPower);
+  void setURL(String url);
+  int setSmartURL(String url);
 
 private:
-	uint16_t beaconUUID;
-	uint8_t  lengthURL;
-	struct {
-		uint8_t frameType;
-		int8_t  advertisedTxPower;
-		uint8_t url[16];
-	} __attribute__((packed)) m_eddystoneData;
-
-}; // BLEEddystoneURL
+  uint8_t
+    lengthURL;  // Describes the length of the URL part including prefix and optional suffix - max 18 B (excluding TX power, frame type and preceding header)
+  struct {
+    int8_t advertisedTxPower;
+    uint8_t url[18];  // Byte [0] is for prefix. Last valid byte **can** contain suffix - i.e. the next byte after the URL
+  } __attribute__((packed)) m_eddystoneData;
+  void _initHeadder();
+  char BLEHeadder[12];
+};  // BLEEddystoneURL
 
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* _BLEEddystoneURL_H_ */
diff --git a/libraries/BLE/src/BLEEddystoneURL.h.orig b/libraries/BLE/src/BLEEddystoneURL.h.orig
new file mode 100644
index 00000000000..57722d0b769
--- /dev/null
+++ b/libraries/BLE/src/BLEEddystoneURL.h.orig
@@ -0,0 +1,66 @@
+/*
+ * BLEEddystoneURL.cpp
+ *
+ *  Created on: Mar 12, 2018
+ *      Author: pcbreflux
+ *  Upgraded on: Feb 17, 2023
+ *      By: Tomas Pilny
+ *
+ */
+
+#ifndef _BLEEddystoneURL_H_
+#define _BLEEddystoneURL_H_
+#include "BLEUUID.h"
+#include <BLEAdvertisedDevice.h>
+#include <Arduino.h>
+
+#define EDDYSTONE_URL_FRAME_TYPE 0x10
+
+extern String EDDYSTONE_URL_PREFIX[];
+extern String EDDYSTONE_URL_SUFFIX[];
+
+/**
+ * @brief Representation of a beacon.
+ * See:
+ * * https://github.com/google/eddystone
+ */
+class BLEEddystoneURL {
+public:
+  BLEEddystoneURL();
+  BLEEddystoneURL(BLEAdvertisedDevice *advertisedDevice);
+  std::string getData();
+  String      getFrame();
+  BLEUUID     getUUID();
+  int8_t      getPower();
+  std::string getURL();
+  String      getPrefix();
+  String      getSuffix();
+  std::string getDecodedURL();
+  void        setData(std::string data);
+  void        setUUID(BLEUUID l_uuid);
+  void        setPower(int8_t advertisedTxPower);
+  void        setURL(std::string url);
+  int         setSmartURL(String url);
+
+private:
+<<<<<<< Updated upstream
+	uint16_t beaconUUID;
+	uint8_t  lengthURL;
+	struct {
+		uint8_t frameType;
+		int8_t  advertisedTxPower;
+		uint8_t url[18];  // 18 bytes: 1 byte for URL scheme + up to 17 bytes of URL
+	} __attribute__((packed)) m_eddystoneData;
+
+=======
+  uint8_t lengthURL; // Describes length of URL part including prefix and suffix - max 18 B (excluding TX power, frame type and preceding header)
+  struct {
+    int8_t  advertisedTxPower;
+    uint8_t url[18]; // Byte [0] is for prefix. Last byte **can** contain suffix
+  } __attribute__((packed)) m_eddystoneData;
+  void _initHeadder();
+  char BLEHeadder[12];
+>>>>>>> Stashed changes
+}; // BLEEddystoneURL
+
+#endif /* _BLEEddystoneURL_H_ */
diff --git a/libraries/BLE/src/BLEExceptions.cpp b/libraries/BLE/src/BLEExceptions.cpp
index 549e4425bd8..4e6c31fca22 100644
--- a/libraries/BLE/src/BLEExceptions.cpp
+++ b/libraries/BLE/src/BLEExceptions.cpp
@@ -6,4 +6,3 @@
  */
 
 //#include "BLEExceptions.h"
-
diff --git a/libraries/BLE/src/BLEExceptions.h b/libraries/BLE/src/BLEExceptions.h
index ea9db8550bc..15b4ef93d84 100644
--- a/libraries/BLE/src/BLEExceptions.h
+++ b/libraries/BLE/src/BLEExceptions.h
@@ -7,6 +7,9 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEEXCEPTIONS_H_
 #define COMPONENTS_CPP_UTILS_BLEEXCEPTIONS_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
 
 #if CONFIG_CXX_EXCEPTIONS != 1
@@ -15,17 +18,17 @@
 
 #include <exception>
 
-
 class BLEDisconnectedException : public std::exception {
-	const char* what() const throw () {
-		return "BLE Disconnected";
-	}
+  const char *what() const throw() {
+    return "BLE Disconnected";
+  }
 };
 
 class BLEUuidNotFoundException : public std::exception {
-	const char* what() const throw () {
-		return "No such UUID";
-	}
+  const char *what() const throw() {
+    return "No such UUID";
+  }
 };
 
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEEXCEPTIONS_H_ */
diff --git a/libraries/BLE/src/BLEHIDDevice.cpp b/libraries/BLE/src/BLEHIDDevice.cpp
index 5354c0530c2..0873aa1049f 100644
--- a/libraries/BLE/src/BLEHIDDevice.cpp
+++ b/libraries/BLE/src/BLEHIDDevice.cpp
@@ -4,103 +4,108 @@
  *  Created on: Jan 03, 2018
  *      Author: chegewara
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include "BLEHIDDevice.h"
 #include "BLE2904.h"
 
-
-BLEHIDDevice::BLEHIDDevice(BLEServer* server) {
-	/*
+BLEHIDDevice::BLEHIDDevice(BLEServer *server) {
+  /*
 	 * Here we create mandatory services described in bluetooth specification
 	 */
-	m_deviceInfoService = server->createService(BLEUUID((uint16_t) 0x180a));
-	m_hidService = server->createService(BLEUUID((uint16_t) 0x1812), 40);
-	m_batteryService = server->createService(BLEUUID((uint16_t) 0x180f));
+  m_deviceInfoService = server->createService(BLEUUID((uint16_t)0x180a));
+  m_hidService = server->createService(BLEUUID((uint16_t)0x1812), 40);
+  m_batteryService = server->createService(BLEUUID((uint16_t)0x180f));
 
-	/*
+  /*
 	 * Mandatory characteristic for device info service
 	 */
-	m_pnpCharacteristic = m_deviceInfoService->createCharacteristic((uint16_t) 0x2a50, BLECharacteristic::PROPERTY_READ);
+  m_pnpCharacteristic = m_deviceInfoService->createCharacteristic((uint16_t)0x2a50, BLECharacteristic::PROPERTY_READ);
 
-	/*
+  /*
 	 * Mandatory characteristics for HID service
 	 */
-	m_hidInfoCharacteristic = m_hidService->createCharacteristic((uint16_t) 0x2a4a, BLECharacteristic::PROPERTY_READ);
-	m_reportMapCharacteristic = m_hidService->createCharacteristic((uint16_t) 0x2a4b, BLECharacteristic::PROPERTY_READ);
-	m_hidControlCharacteristic = m_hidService->createCharacteristic((uint16_t) 0x2a4c, BLECharacteristic::PROPERTY_WRITE_NR);
-	m_protocolModeCharacteristic = m_hidService->createCharacteristic((uint16_t) 0x2a4e, BLECharacteristic::PROPERTY_WRITE_NR | BLECharacteristic::PROPERTY_READ);
+  m_hidInfoCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4a, BLECharacteristic::PROPERTY_READ);
+  m_reportMapCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4b, BLECharacteristic::PROPERTY_READ);
+  m_hidControlCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4c, BLECharacteristic::PROPERTY_WRITE_NR);
+  m_protocolModeCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a4e, BLECharacteristic::PROPERTY_WRITE_NR | BLECharacteristic::PROPERTY_READ);
 
-	/*
+  /*
 	 * Mandatory battery level characteristic with notification and presence descriptor
 	 */
-	BLE2904* batteryLevelDescriptor = new BLE2904();
-	batteryLevelDescriptor->setFormat(BLE2904::FORMAT_UINT8);
-	batteryLevelDescriptor->setNamespace(1);
-	batteryLevelDescriptor->setUnit(0x27ad);
-
-	m_batteryLevelCharacteristic = m_batteryService->createCharacteristic((uint16_t) 0x2a19, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_NOTIFY);
-	m_batteryLevelCharacteristic->addDescriptor(batteryLevelDescriptor);
-	m_batteryLevelCharacteristic->addDescriptor(new BLE2902());
-
-	/*
+  BLE2904 *batteryLevelDescriptor = new BLE2904();
+  batteryLevelDescriptor->setFormat(BLE2904::FORMAT_UINT8);
+  batteryLevelDescriptor->setNamespace(1);
+  batteryLevelDescriptor->setUnit(0x27ad);
+
+  m_batteryLevelCharacteristic =
+    m_batteryService->createCharacteristic((uint16_t)0x2a19, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_NOTIFY);
+  m_batteryLevelCharacteristic->addDescriptor(batteryLevelDescriptor);
+  BLE2902 *batLevelIndicator = new BLE2902();
+  // Battery Level Notification is ON by default, making it work always on BLE Pairing and Bonding
+  batLevelIndicator->setNotifications(true);
+  m_batteryLevelCharacteristic->addDescriptor(batLevelIndicator);
+
+  /*
 	 * This value is setup here because its default value in most usage cases, its very rare to use boot mode
 	 * and we want to simplify library using as much as possible
 	 */
-	const uint8_t pMode[] = { 0x01 };
-	protocolMode()->setValue((uint8_t*) pMode, 1);
+  const uint8_t pMode[] = {0x01};
+  protocolMode()->setValue((uint8_t *)pMode, 1);
 }
 
-BLEHIDDevice::~BLEHIDDevice() {
-}
+BLEHIDDevice::~BLEHIDDevice() {}
 
 /*
  * @brief
  */
-void BLEHIDDevice::reportMap(uint8_t* map, uint16_t size) {
-	m_reportMapCharacteristic->setValue(map, size);
+void BLEHIDDevice::reportMap(uint8_t *map, uint16_t size) {
+  m_reportMapCharacteristic->setValue(map, size);
 }
 
 /*
  * @brief This function suppose to be called at the end, when we have created all characteristics we need to build HID service
  */
 void BLEHIDDevice::startServices() {
-	m_deviceInfoService->start();
-	m_hidService->start();
-	m_batteryService->start();
+  m_deviceInfoService->start();
+  m_hidService->start();
+  m_batteryService->start();
 }
 
 /*
  * @brief Create manufacturer characteristic (this characteristic is optional)
  */
-BLECharacteristic* BLEHIDDevice::manufacturer() {
-	m_manufacturerCharacteristic = m_deviceInfoService->createCharacteristic((uint16_t) 0x2a29, BLECharacteristic::PROPERTY_READ);
-	return m_manufacturerCharacteristic;
+BLECharacteristic *BLEHIDDevice::manufacturer() {
+  m_manufacturerCharacteristic = m_deviceInfoService->createCharacteristic((uint16_t)0x2a29, BLECharacteristic::PROPERTY_READ);
+  return m_manufacturerCharacteristic;
 }
 
 /*
  * @brief Set manufacturer name
  * @param [in] name manufacturer name
  */
-void BLEHIDDevice::manufacturer(std::string name) {
-	m_manufacturerCharacteristic->setValue(name);
+void BLEHIDDevice::manufacturer(String name) {
+  m_manufacturerCharacteristic->setValue(name);
 }
 
 /*
  * @brief
  */
 void BLEHIDDevice::pnp(uint8_t sig, uint16_t vid, uint16_t pid, uint16_t version) {
-	uint8_t pnp[] = { sig, (uint8_t) (vid >> 8), (uint8_t) vid, (uint8_t) (pid >> 8), (uint8_t) pid, (uint8_t) (version >> 8), (uint8_t) version };
-	m_pnpCharacteristic->setValue(pnp, sizeof(pnp));
+  uint8_t pnp[] = {sig, (uint8_t)(vid >> 8), (uint8_t)vid, (uint8_t)(pid >> 8), (uint8_t)pid, (uint8_t)(version >> 8), (uint8_t)version};
+  m_pnpCharacteristic->setValue(pnp, sizeof(pnp));
 }
 
 /*
  * @brief
  */
 void BLEHIDDevice::hidInfo(uint8_t country, uint8_t flags) {
-	uint8_t info[] = { 0x11, 0x1, country, flags };
-	m_hidInfoCharacteristic->setValue(info, sizeof(info));
+  uint8_t info[] = {0x11, 0x1, country, flags};
+  m_hidInfoCharacteristic->setValue(info, sizeof(info));
 }
 
 /*
@@ -108,20 +113,21 @@ void BLEHIDDevice::hidInfo(uint8_t country, uint8_t flags) {
  * @param [in] reportID input report ID, the same as in report map for input object related to created characteristic
  * @return pointer to new input report characteristic
  */
-BLECharacteristic* BLEHIDDevice::inputReport(uint8_t reportID) {
-	BLECharacteristic* inputReportCharacteristic = m_hidService->createCharacteristic((uint16_t) 0x2a4d, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_NOTIFY);
-	BLEDescriptor* inputReportDescriptor = new BLEDescriptor(BLEUUID((uint16_t) 0x2908));
-	BLE2902* p2902 = new BLE2902();
-	inputReportCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
-	inputReportDescriptor->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
-	p2902->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
-
-	uint8_t desc1_val[] = { reportID, 0x01 };
-	inputReportDescriptor->setValue((uint8_t*) desc1_val, 2);
-	inputReportCharacteristic->addDescriptor(p2902);
-	inputReportCharacteristic->addDescriptor(inputReportDescriptor);
-
-	return inputReportCharacteristic;
+BLECharacteristic *BLEHIDDevice::inputReport(uint8_t reportID) {
+  BLECharacteristic *inputReportCharacteristic =
+    m_hidService->createCharacteristic((uint16_t)0x2a4d, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_NOTIFY);
+  BLEDescriptor *inputReportDescriptor = new BLEDescriptor(BLEUUID((uint16_t)0x2908));
+  BLE2902 *p2902 = new BLE2902();
+  inputReportCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
+  inputReportDescriptor->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
+  p2902->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
+
+  uint8_t desc1_val[] = {reportID, 0x01};
+  inputReportDescriptor->setValue((uint8_t *)desc1_val, 2);
+  inputReportCharacteristic->addDescriptor(p2902);
+  inputReportCharacteristic->addDescriptor(inputReportDescriptor);
+
+  return inputReportCharacteristic;
 }
 
 /*
@@ -129,17 +135,19 @@ BLECharacteristic* BLEHIDDevice::inputReport(uint8_t reportID) {
  * @param [in] reportID Output report ID, the same as in report map for output object related to created characteristic
  * @return Pointer to new output report characteristic
  */
-BLECharacteristic* BLEHIDDevice::outputReport(uint8_t reportID) {
-	BLECharacteristic* outputReportCharacteristic = m_hidService->createCharacteristic((uint16_t) 0x2a4d, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_WRITE_NR);
-	BLEDescriptor* outputReportDescriptor = new BLEDescriptor(BLEUUID((uint16_t) 0x2908));
-	outputReportCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
-	outputReportDescriptor->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
-
-	uint8_t desc1_val[] = { reportID, 0x02 };
-	outputReportDescriptor->setValue((uint8_t*) desc1_val, 2);
-	outputReportCharacteristic->addDescriptor(outputReportDescriptor);
-
-	return outputReportCharacteristic;
+BLECharacteristic *BLEHIDDevice::outputReport(uint8_t reportID) {
+  BLECharacteristic *outputReportCharacteristic = m_hidService->createCharacteristic(
+    (uint16_t)0x2a4d, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_WRITE_NR
+  );
+  BLEDescriptor *outputReportDescriptor = new BLEDescriptor(BLEUUID((uint16_t)0x2908));
+  outputReportCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
+  outputReportDescriptor->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
+
+  uint8_t desc1_val[] = {reportID, 0x02};
+  outputReportDescriptor->setValue((uint8_t *)desc1_val, 2);
+  outputReportCharacteristic->addDescriptor(outputReportDescriptor);
+
+  return outputReportCharacteristic;
 }
 
 /*
@@ -147,59 +155,63 @@ BLECharacteristic* BLEHIDDevice::outputReport(uint8_t reportID) {
  * @param [in] reportID Feature report ID, the same as in report map for feature object related to created characteristic
  * @return Pointer to new feature report characteristic
  */
-BLECharacteristic* BLEHIDDevice::featureReport(uint8_t reportID) {
-	BLECharacteristic* featureReportCharacteristic = m_hidService->createCharacteristic((uint16_t) 0x2a4d, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE);
-	BLEDescriptor* featureReportDescriptor = new BLEDescriptor(BLEUUID((uint16_t) 0x2908));
+BLECharacteristic *BLEHIDDevice::featureReport(uint8_t reportID) {
+  BLECharacteristic *featureReportCharacteristic =
+    m_hidService->createCharacteristic((uint16_t)0x2a4d, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE);
+  BLEDescriptor *featureReportDescriptor = new BLEDescriptor(BLEUUID((uint16_t)0x2908));
 
-	featureReportCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
-	featureReportDescriptor->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
+  featureReportCharacteristic->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
+  featureReportDescriptor->setAccessPermissions(ESP_GATT_PERM_READ_ENCRYPTED | ESP_GATT_PERM_WRITE_ENCRYPTED);
 
-	uint8_t desc1_val[] = { reportID, 0x03 };
-	featureReportDescriptor->setValue((uint8_t*) desc1_val, 2);
-	featureReportCharacteristic->addDescriptor(featureReportDescriptor);
+  uint8_t desc1_val[] = {reportID, 0x03};
+  featureReportDescriptor->setValue((uint8_t *)desc1_val, 2);
+  featureReportCharacteristic->addDescriptor(featureReportDescriptor);
 
-	return featureReportCharacteristic;
+  return featureReportCharacteristic;
 }
 
 /*
  * @brief
  */
-BLECharacteristic* BLEHIDDevice::bootInput() {
-	BLECharacteristic* bootInputCharacteristic = m_hidService->createCharacteristic((uint16_t) 0x2a22, BLECharacteristic::PROPERTY_NOTIFY);
-	bootInputCharacteristic->addDescriptor(new BLE2902());
+BLECharacteristic *BLEHIDDevice::bootInput() {
+  BLECharacteristic *bootInputCharacteristic = m_hidService->createCharacteristic((uint16_t)0x2a22, BLECharacteristic::PROPERTY_NOTIFY);
+  bootInputCharacteristic->addDescriptor(new BLE2902());
 
-	return bootInputCharacteristic;
+  return bootInputCharacteristic;
 }
 
 /*
  * @brief
  */
-BLECharacteristic* BLEHIDDevice::bootOutput() {
-	return m_hidService->createCharacteristic((uint16_t) 0x2a32, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_WRITE_NR);
+BLECharacteristic *BLEHIDDevice::bootOutput() {
+  return m_hidService->createCharacteristic(
+    (uint16_t)0x2a32, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_WRITE_NR
+  );
 }
 
 /*
  * @brief
  */
-BLECharacteristic* BLEHIDDevice::hidControl() {
-	return m_hidControlCharacteristic;
+BLECharacteristic *BLEHIDDevice::hidControl() {
+  return m_hidControlCharacteristic;
 }
 
 /*
  * @brief
  */
-BLECharacteristic* BLEHIDDevice::protocolMode() {
-	return m_protocolModeCharacteristic;
+BLECharacteristic *BLEHIDDevice::protocolMode() {
+  return m_protocolModeCharacteristic;
 }
 
 void BLEHIDDevice::setBatteryLevel(uint8_t level) {
-	m_batteryLevelCharacteristic->setValue(&level, 1);
-	m_batteryLevelCharacteristic->notify();	
+  m_batteryLevelCharacteristic->setValue(&level, 1);
+  m_batteryLevelCharacteristic->notify();
 }
 /*
  * @brief Returns battery level characteristic
  * @ return battery level characteristic
- *//*
+ */
+/*
 BLECharacteristic* BLEHIDDevice::batteryLevel() {
 	return m_batteryLevelCharacteristic;
 }
@@ -222,23 +234,23 @@ BLECharacteristic*	BLEHIDDevice::hidInfo() {
 /*
  * @brief
  */
-BLEService* BLEHIDDevice::deviceInfo() {
-	return m_deviceInfoService;
+BLEService *BLEHIDDevice::deviceInfo() {
+  return m_deviceInfoService;
 }
 
 /*
  * @brief
  */
-BLEService* BLEHIDDevice::hidService() {
-	return m_hidService;
+BLEService *BLEHIDDevice::hidService() {
+  return m_hidService;
 }
 
 /*
  * @brief
  */
-BLEService* BLEHIDDevice::batteryService() {
-	return m_batteryService;
+BLEService *BLEHIDDevice::batteryService() {
+  return m_batteryService;
 }
 
-#endif // CONFIG_BT_ENABLED
-
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEHIDDevice.h b/libraries/BLE/src/BLEHIDDevice.h
index 33e6b46c540..a92a23c21d5 100644
--- a/libraries/BLE/src/BLEHIDDevice.h
+++ b/libraries/BLE/src/BLEHIDDevice.h
@@ -8,8 +8,11 @@
 #ifndef _BLEHIDDEVICE_H_
 #define _BLEHIDDEVICE_H_
 
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include "BLECharacteristic.h"
 #include "BLEService.h"
@@ -17,59 +20,61 @@
 #include "BLE2902.h"
 #include "HIDTypes.h"
 
-#define GENERIC_HID		0x03C0
-#define HID_KEYBOARD	   0x03C1
-#define HID_MOUSE		  0x03C2
-#define HID_JOYSTICK	   0x03C3
-#define HID_GAMEPAD		0x03C4
-#define HID_TABLET		 0x03C5
-#define HID_CARD_READER	0x03C6
-#define HID_DIGITAL_PEN	0x03C7
-#define HID_BARCODE		0x03C8
+#define GENERIC_HID         0x03C0
+#define HID_KEYBOARD        0x03C1
+#define HID_MOUSE           0x03C2
+#define HID_JOYSTICK        0x03C3
+#define HID_GAMEPAD         0x03C4
+#define HID_TABLET          0x03C5
+#define HID_CARD_READER     0x03C6
+#define HID_DIGITAL_PEN     0x03C7
+#define HID_BARCODE         0x03C8
+#define HID_BRAILLE_DISPLAY 0x03C9
 
 class BLEHIDDevice {
 public:
-	BLEHIDDevice(BLEServer*);
-	virtual ~BLEHIDDevice();
-
-	void reportMap(uint8_t* map, uint16_t);
-	void startServices();
+  BLEHIDDevice(BLEServer *);
+  virtual ~BLEHIDDevice();
 
-	BLEService* deviceInfo();
-	BLEService* hidService();
-	BLEService* batteryService();
+  void reportMap(uint8_t *map, uint16_t);
+  void startServices();
 
-	BLECharacteristic* 	manufacturer();
-	void 	manufacturer(std::string name);
-	//BLECharacteristic* 	pnp();
-	void	pnp(uint8_t sig, uint16_t vid, uint16_t pid, uint16_t version);
-	//BLECharacteristic*	hidInfo();
-	void	hidInfo(uint8_t country, uint8_t flags);
-	//BLECharacteristic* 	batteryLevel();
-	void 	setBatteryLevel(uint8_t level);
+  BLEService *deviceInfo();
+  BLEService *hidService();
+  BLEService *batteryService();
 
+  BLECharacteristic *manufacturer();
+  void manufacturer(String name);
+  //BLECharacteristic* 	pnp();
+  void pnp(uint8_t sig, uint16_t vid, uint16_t pid, uint16_t version);
+  //BLECharacteristic*	hidInfo();
+  void hidInfo(uint8_t country, uint8_t flags);
+  //BLECharacteristic* 	batteryLevel();
+  void setBatteryLevel(uint8_t level);
 
-	//BLECharacteristic* 	reportMap();
-	BLECharacteristic* 	hidControl();
-	BLECharacteristic* 	inputReport(uint8_t reportID);
-	BLECharacteristic* 	outputReport(uint8_t reportID);
-	BLECharacteristic* 	featureReport(uint8_t reportID);
-	BLECharacteristic* 	protocolMode();
-	BLECharacteristic* 	bootInput();
-	BLECharacteristic* 	bootOutput();
+  //BLECharacteristic* 	reportMap();
+  BLECharacteristic *hidControl();
+  BLECharacteristic *inputReport(uint8_t reportID);
+  BLECharacteristic *outputReport(uint8_t reportID);
+  BLECharacteristic *featureReport(uint8_t reportID);
+  BLECharacteristic *protocolMode();
+  BLECharacteristic *bootInput();
+  BLECharacteristic *bootOutput();
 
 private:
-	BLEService*			m_deviceInfoService;			//0x180a
-	BLEService*			m_hidService;					//0x1812
-	BLEService*			m_batteryService = 0;			//0x180f
+  BLEService *m_deviceInfoService;   //0x180a
+  BLEService *m_hidService;          //0x1812
+  BLEService *m_batteryService = 0;  //0x180f
 
-	BLECharacteristic* 	m_manufacturerCharacteristic;	//0x2a29
-	BLECharacteristic* 	m_pnpCharacteristic;			//0x2a50
-	BLECharacteristic* 	m_hidInfoCharacteristic;		//0x2a4a
-	BLECharacteristic* 	m_reportMapCharacteristic;		//0x2a4b
-	BLECharacteristic* 	m_hidControlCharacteristic;		//0x2a4c
-	BLECharacteristic* 	m_protocolModeCharacteristic;	//0x2a4e
-	BLECharacteristic*	m_batteryLevelCharacteristic;	//0x2a19
+  BLECharacteristic *m_manufacturerCharacteristic;  //0x2a29
+  BLECharacteristic *m_pnpCharacteristic;           //0x2a50
+  BLECharacteristic *m_hidInfoCharacteristic;       //0x2a4a
+  BLECharacteristic *m_reportMapCharacteristic;     //0x2a4b
+  BLECharacteristic *m_hidControlCharacteristic;    //0x2a4c
+  BLECharacteristic *m_protocolModeCharacteristic;  //0x2a4e
+  BLECharacteristic *m_batteryLevelCharacteristic;  //0x2a19
 };
-#endif // CONFIG_BT_ENABLED
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* _BLEHIDDEVICE_H_ */
diff --git a/libraries/BLE/src/BLERemoteCharacteristic.cpp b/libraries/BLE/src/BLERemoteCharacteristic.cpp
index d67710442ae..60d5108c1fc 100644
--- a/libraries/BLE/src/BLERemoteCharacteristic.cpp
+++ b/libraries/BLE/src/BLERemoteCharacteristic.cpp
@@ -7,8 +7,11 @@
 
 #include "BLERemoteCharacteristic.h"
 
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include <esp_gattc_api.h>
 #include <esp_err.h>
@@ -20,7 +23,6 @@
 #include "BLERemoteDescriptor.h"
 #include "esp32-hal-log.h"
 
-
 /**
  * @brief Constructor.
  * @param [in] handle The BLE server side handle of this characteristic.
@@ -28,86 +30,75 @@
  * @param [in] charProp The properties of this characteristic.
  * @param [in] pRemoteService A reference to the remote service to which this remote characteristic pertains.
  */
-BLERemoteCharacteristic::BLERemoteCharacteristic(
-		uint16_t             handle,
-		BLEUUID              uuid,
-		esp_gatt_char_prop_t charProp,
-		BLERemoteService*    pRemoteService) {
-	log_v(">> BLERemoteCharacteristic: handle: %d 0x%d, uuid: %s", handle, handle, uuid.toString().c_str());
-	m_handle         = handle;
-	m_uuid           = uuid;
-	m_charProp       = charProp;
-	m_pRemoteService = pRemoteService;
-	m_notifyCallback = nullptr;
-	m_rawData = nullptr;
-    m_auth           = ESP_GATT_AUTH_REQ_NONE;
-
-	retrieveDescriptors(); // Get the descriptors for this characteristic
-	log_v("<< BLERemoteCharacteristic");
-} // BLERemoteCharacteristic
-
+BLERemoteCharacteristic::BLERemoteCharacteristic(uint16_t handle, BLEUUID uuid, esp_gatt_char_prop_t charProp, BLERemoteService *pRemoteService) {
+  log_v(">> BLERemoteCharacteristic: handle: %d 0x%d, uuid: %s", handle, handle, uuid.toString().c_str());
+  m_handle = handle;
+  m_uuid = uuid;
+  m_charProp = charProp;
+  m_pRemoteService = pRemoteService;
+  m_notifyCallback = nullptr;
+  m_rawData = nullptr;
+  m_auth = ESP_GATT_AUTH_REQ_NONE;
+
+  retrieveDescriptors();  // Get the descriptors for this characteristic
+  log_v("<< BLERemoteCharacteristic");
+}  // BLERemoteCharacteristic
 
 /**
  *@brief Destructor.
  */
 BLERemoteCharacteristic::~BLERemoteCharacteristic() {
-	removeDescriptors();   // Release resources for any descriptor information we may have allocated.
-} // ~BLERemoteCharacteristic
-
+  removeDescriptors();  // Release resources for any descriptor information we may have allocated.
+  free(m_rawData);
+}  // ~BLERemoteCharacteristic
 
 /**
  * @brief Does the characteristic support broadcasting?
  * @return True if the characteristic supports broadcasting.
  */
 bool BLERemoteCharacteristic::canBroadcast() {
-	return (m_charProp & ESP_GATT_CHAR_PROP_BIT_BROADCAST) != 0;
-} // canBroadcast
-
+  return (m_charProp & ESP_GATT_CHAR_PROP_BIT_BROADCAST) != 0;
+}  // canBroadcast
 
 /**
  * @brief Does the characteristic support indications?
  * @return True if the characteristic supports indications.
  */
 bool BLERemoteCharacteristic::canIndicate() {
-	return (m_charProp & ESP_GATT_CHAR_PROP_BIT_INDICATE) != 0;
-} // canIndicate
-
+  return (m_charProp & ESP_GATT_CHAR_PROP_BIT_INDICATE) != 0;
+}  // canIndicate
 
 /**
  * @brief Does the characteristic support notifications?
  * @return True if the characteristic supports notifications.
  */
 bool BLERemoteCharacteristic::canNotify() {
-	return (m_charProp & ESP_GATT_CHAR_PROP_BIT_NOTIFY) != 0;
-} // canNotify
-
+  return (m_charProp & ESP_GATT_CHAR_PROP_BIT_NOTIFY) != 0;
+}  // canNotify
 
 /**
  * @brief Does the characteristic support reading?
  * @return True if the characteristic supports reading.
  */
 bool BLERemoteCharacteristic::canRead() {
-	return (m_charProp & ESP_GATT_CHAR_PROP_BIT_READ) != 0;
-} // canRead
-
+  return (m_charProp & ESP_GATT_CHAR_PROP_BIT_READ) != 0;
+}  // canRead
 
 /**
  * @brief Does the characteristic support writing?
  * @return True if the characteristic supports writing.
  */
 bool BLERemoteCharacteristic::canWrite() {
-	return (m_charProp & ESP_GATT_CHAR_PROP_BIT_WRITE) != 0;
-} // canWrite
-
+  return (m_charProp & ESP_GATT_CHAR_PROP_BIT_WRITE) != 0;
+}  // canWrite
 
 /**
  * @brief Does the characteristic support writing with no response?
  * @return True if the characteristic supports writing with no response.
  */
 bool BLERemoteCharacteristic::canWriteNoResponse() {
-	return (m_charProp & ESP_GATT_CHAR_PROP_BIT_WRITE_NR) != 0;
-} // canWriteNoResponse
-
+  return (m_charProp & ESP_GATT_CHAR_PROP_BIT_WRITE_NR) != 0;
+}  // canWriteNoResponse
 
 /*
 static bool compareSrvcId(esp_gatt_srvc_id_t id1, esp_gatt_srvc_id_t id2) {
@@ -133,7 +124,6 @@ static bool compareGattId(esp_gatt_id_t id1, esp_gatt_id_t id2) {
 } // compareCharId
 */
 
-
 /**
  * @brief Handle GATT Client events.
  * When an event arrives for a GATT client we give this characteristic the opportunity to
@@ -143,309 +133,314 @@ static bool compareGattId(esp_gatt_id_t id1, esp_gatt_id_t id2) {
  * @param [in] evtParam Payload data for the event.
  * @returns N/A
  */
-void BLERemoteCharacteristic::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t* evtParam) {
-	switch(event) {
-		// ESP_GATTC_NOTIFY_EVT
-		//
-		// notify
-		// - uint16_t           conn_id    - The connection identifier of the server.
-		// - esp_bd_addr_t      remote_bda - The device address of the BLE server.
-		// - uint16_t           handle     - The handle of the characteristic for which the event is being received.
-		// - uint16_t           value_len  - The length of the received data.
-		// - uint8_t*           value      - The received data.
-		// - bool               is_notify  - True if this is a notify, false if it is an indicate.
-		//
-		// We have received a notification event which means that the server wishes us to know about a notification
-		// piece of data.  What we must now do is find the characteristic with the associated handle and then
-		// invoke its notification callback (if it has one).
-		case ESP_GATTC_NOTIFY_EVT: {
-			if (evtParam->notify.handle != getHandle()) break;
-			if (m_notifyCallback != nullptr) {
-				log_d("Invoking callback for notification on characteristic %s", toString().c_str());
-				m_notifyCallback(this, evtParam->notify.value, evtParam->notify.value_len, evtParam->notify.is_notify);
-			} // End we have a callback function ...
-			break;
-		} // ESP_GATTC_NOTIFY_EVT
-
-		// ESP_GATTC_READ_CHAR_EVT
-		// This event indicates that the server has responded to the read request.
-		//
-		// read:
-		// - esp_gatt_status_t  status
-		// - uint16_t           conn_id
-		// - uint16_t           handle
-		// - uint8_t*           value
-		// - uint16_t           value_len
-		case ESP_GATTC_READ_CHAR_EVT: {
-			// If this event is not for us, then nothing further to do.
-			if (evtParam->read.handle != getHandle()) break;
-
-			// At this point, we have determined that the event is for us, so now we save the value
-			// and unlock the semaphore to ensure that the requestor of the data can continue.
-			if (evtParam->read.status == ESP_GATT_OK) {
-				m_value = std::string((char*) evtParam->read.value, evtParam->read.value_len);
-				if(m_rawData != nullptr) free(m_rawData);
-				m_rawData = (uint8_t*) calloc(evtParam->read.value_len, sizeof(uint8_t));
-				memcpy(m_rawData, evtParam->read.value, evtParam->read.value_len);
-			} else {
-				m_value = "";
-			}
-
-			m_semaphoreReadCharEvt.give();
-			break;
-		} // ESP_GATTC_READ_CHAR_EVT
-
-		// ESP_GATTC_REG_FOR_NOTIFY_EVT
-		//
-		// reg_for_notify:
-		// - esp_gatt_status_t status
-		// - uint16_t          handle
-		case ESP_GATTC_REG_FOR_NOTIFY_EVT: {
-			// If the request is not for this BLERemoteCharacteristic then move on to the next.
-			if (evtParam->reg_for_notify.handle != getHandle()) break;
-
-			// We have processed the notify registration and can unlock the semaphore.
-			m_semaphoreRegForNotifyEvt.give();
-			break;
-		} // ESP_GATTC_REG_FOR_NOTIFY_EVT
-
-		// ESP_GATTC_UNREG_FOR_NOTIFY_EVT
-		//
-		// unreg_for_notify:
-		// - esp_gatt_status_t status
-		// - uint16_t          handle
-		case ESP_GATTC_UNREG_FOR_NOTIFY_EVT: {
-			if (evtParam->unreg_for_notify.handle != getHandle()) break;
-			// We have processed the notify un-registration and can unlock the semaphore.
-			m_semaphoreRegForNotifyEvt.give();
-			break;
-		} // ESP_GATTC_UNREG_FOR_NOTIFY_EVT:
-
-		// ESP_GATTC_WRITE_CHAR_EVT
-		//
-		// write:
-		// - esp_gatt_status_t status
-		// - uint16_t          conn_id
-		// - uint16_t          handle
-		case ESP_GATTC_WRITE_CHAR_EVT: {
-			// Determine if this event is for us and, if not, pass onwards.
-			if (evtParam->write.handle != getHandle()) break;
-
-			// There is nothing further we need to do here.  This is merely an indication
-			// that the write has completed and we can unlock the caller.
-			m_semaphoreWriteCharEvt.give();
-			break;
-		} // ESP_GATTC_WRITE_CHAR_EVT
-
-		case ESP_GATTC_READ_DESCR_EVT:
-		case ESP_GATTC_WRITE_DESCR_EVT:
-			for (auto &myPair : m_descriptorMap) {
-				myPair.second->gattClientEventHandler(
-					event, gattc_if, evtParam);
-			}
-			break;
-
-		default:
-			break;
-	} // End switch
-}; // gattClientEventHandler
-
+void BLERemoteCharacteristic::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) {
+  switch (event) {
+    // ESP_GATTC_NOTIFY_EVT
+    //
+    // notify
+    // - uint16_t           conn_id    - The connection identifier of the server.
+    // - esp_bd_addr_t      remote_bda - The device address of the BLE server.
+    // - uint16_t           handle     - The handle of the characteristic for which the event is being received.
+    // - uint16_t           value_len  - The length of the received data.
+    // - uint8_t*           value      - The received data.
+    // - bool               is_notify  - True if this is a notify, false if it is an indicate.
+    //
+    // We have received a notification event which means that the server wishes us to know about a notification
+    // piece of data.  What we must now do is find the characteristic with the associated handle and then
+    // invoke its notification callback (if it has one).
+    case ESP_GATTC_NOTIFY_EVT:
+    {
+      if (evtParam->notify.handle != getHandle()) {
+        break;
+      }
+      if (m_notifyCallback != nullptr) {
+        log_d("Invoking callback for notification on characteristic %s", toString().c_str());
+        m_notifyCallback(this, evtParam->notify.value, evtParam->notify.value_len, evtParam->notify.is_notify);
+      }  // End we have a callback function ...
+      break;
+    }  // ESP_GATTC_NOTIFY_EVT
+
+    // ESP_GATTC_READ_CHAR_EVT
+    // This event indicates that the server has responded to the read request.
+    //
+    // read:
+    // - esp_gatt_status_t  status
+    // - uint16_t           conn_id
+    // - uint16_t           handle
+    // - uint8_t*           value
+    // - uint16_t           value_len
+    case ESP_GATTC_READ_CHAR_EVT:
+    {
+      // If this event is not for us, then nothing further to do.
+      if (evtParam->read.handle != getHandle()) {
+        break;
+      }
+
+      // At this point, we have determined that the event is for us, so now we save the value
+      // and unlock the semaphore to ensure that the requester of the data can continue.
+      if (evtParam->read.status == ESP_GATT_OK) {
+        m_value = String((char *)evtParam->read.value, evtParam->read.value_len);
+        if (m_rawData != nullptr) {
+          free(m_rawData);
+        }
+        m_rawData = (uint8_t *)calloc(evtParam->read.value_len, sizeof(uint8_t));
+        memcpy(m_rawData, evtParam->read.value, evtParam->read.value_len);
+      } else {
+        m_value = "";
+      }
+
+      m_semaphoreReadCharEvt.give();
+      break;
+    }  // ESP_GATTC_READ_CHAR_EVT
+
+    // ESP_GATTC_REG_FOR_NOTIFY_EVT
+    //
+    // reg_for_notify:
+    // - esp_gatt_status_t status
+    // - uint16_t          handle
+    case ESP_GATTC_REG_FOR_NOTIFY_EVT:
+    {
+      // If the request is not for this BLERemoteCharacteristic then move on to the next.
+      if (evtParam->reg_for_notify.handle != getHandle()) {
+        break;
+      }
+
+      // We have processed the notify registration and can unlock the semaphore.
+      m_semaphoreRegForNotifyEvt.give();
+      break;
+    }  // ESP_GATTC_REG_FOR_NOTIFY_EVT
+
+    // ESP_GATTC_UNREG_FOR_NOTIFY_EVT
+    //
+    // unreg_for_notify:
+    // - esp_gatt_status_t status
+    // - uint16_t          handle
+    case ESP_GATTC_UNREG_FOR_NOTIFY_EVT:
+    {
+      if (evtParam->unreg_for_notify.handle != getHandle()) {
+        break;
+      }
+      // We have processed the notify un-registration and can unlock the semaphore.
+      m_semaphoreRegForNotifyEvt.give();
+      break;
+    }  // ESP_GATTC_UNREG_FOR_NOTIFY_EVT:
+
+    // ESP_GATTC_WRITE_CHAR_EVT
+    //
+    // write:
+    // - esp_gatt_status_t status
+    // - uint16_t          conn_id
+    // - uint16_t          handle
+    case ESP_GATTC_WRITE_CHAR_EVT:
+    {
+      // Determine if this event is for us and, if not, pass onwards.
+      if (evtParam->write.handle != getHandle()) {
+        break;
+      }
+
+      // There is nothing further we need to do here.  This is merely an indication
+      // that the write has completed and we can unlock the caller.
+      m_semaphoreWriteCharEvt.give();
+      break;
+    }  // ESP_GATTC_WRITE_CHAR_EVT
+
+    case ESP_GATTC_READ_DESCR_EVT:
+    case ESP_GATTC_WRITE_DESCR_EVT:
+      for (auto &myPair : m_descriptorMap) {
+        myPair.second->gattClientEventHandler(event, gattc_if, evtParam);
+      }
+      break;
+
+    case ESP_GATTC_DISCONNECT_EVT:
+      // Cleanup semaphores to avoid deadlocks.
+      m_semaphoreReadCharEvt.give(1);
+      m_semaphoreWriteCharEvt.give(1);
+      break;
+
+    default: break;
+  }  // End switch
+};  // gattClientEventHandler
 
 /**
  * @brief Populate the descriptors (if any) for this characteristic.
  */
 void BLERemoteCharacteristic::retrieveDescriptors() {
-	log_v(">> retrieveDescriptors() for characteristic: %s", getUUID().toString().c_str());
-
-	removeDescriptors();   // Remove any existing descriptors.
-
-	// Loop over each of the descriptors within the service associated with this characteristic.
-	// For each descriptor we find, create a BLERemoteDescriptor instance.
-	uint16_t offset = 0;
-	esp_gattc_descr_elem_t result;
-	while(true) {
-		uint16_t count = 10;
-		esp_gatt_status_t status = ::esp_ble_gattc_get_all_descr(
-			getRemoteService()->getClient()->getGattcIf(),
-			getRemoteService()->getClient()->getConnId(),
-			getHandle(),
-			&result,
-			&count,
-			offset
-		);
-
-		if (status == ESP_GATT_INVALID_OFFSET) {   // We have reached the end of the entries.
-			break;
-		}
-
-		if (status != ESP_GATT_OK) {
-			log_e("esp_ble_gattc_get_all_descr: %s", BLEUtils::gattStatusToString(status).c_str());
-			break;
-		}
-
-		if (count == 0) break;
-
-		log_d("Found a descriptor: Handle: %d, UUID: %s", result.handle, BLEUUID(result.uuid).toString().c_str());
-
-		// We now have a new characteristic ... let us add that to our set of known characteristics
-		BLERemoteDescriptor* pNewRemoteDescriptor = new BLERemoteDescriptor(
-			result.handle,
-			BLEUUID(result.uuid),
-			this
-		);
-
-		m_descriptorMap.insert(std::pair<std::string, BLERemoteDescriptor*>(pNewRemoteDescriptor->getUUID().toString(), pNewRemoteDescriptor));
-
-		offset++;
-	} // while true
-	//m_haveCharacteristics = true; // Remember that we have received the characteristics.
-	log_v("<< retrieveDescriptors(): Found %d descriptors.", offset);
-} // getDescriptors
+  log_v(">> retrieveDescriptors() for characteristic: %s", getUUID().toString().c_str());
+
+  removeDescriptors();  // Remove any existing descriptors.
+
+  // Loop over each of the descriptors within the service associated with this characteristic.
+  // For each descriptor we find, create a BLERemoteDescriptor instance.
+  uint16_t offset = 0;
+  esp_gattc_descr_elem_t result;
+  while (true) {
+    uint16_t count = 10;
+    esp_gatt_status_t status = ::esp_ble_gattc_get_all_descr(
+      getRemoteService()->getClient()->getGattcIf(), getRemoteService()->getClient()->getConnId(), getHandle(), &result, &count, offset
+    );
+
+    if (status == ESP_GATT_INVALID_OFFSET) {  // We have reached the end of the entries.
+      break;
+    }
 
+    if (status != ESP_GATT_OK) {
+      log_e("esp_ble_gattc_get_all_descr: %s", BLEUtils::gattStatusToString(status).c_str());
+      break;
+    }
+
+    if (count == 0) {
+      break;
+    }
+
+    log_d("Found a descriptor: Handle: %d, UUID: %s", result.handle, BLEUUID(result.uuid).toString().c_str());
+
+    // We now have a new characteristic ... let us add that to our set of known characteristics
+    BLERemoteDescriptor *pNewRemoteDescriptor = new BLERemoteDescriptor(result.handle, BLEUUID(result.uuid), this);
+
+    m_descriptorMap.insert(std::pair<std::string, BLERemoteDescriptor *>(pNewRemoteDescriptor->getUUID().toString().c_str(), pNewRemoteDescriptor));
+
+    offset++;
+  }  // while true
+  //m_haveCharacteristics = true; // Remember that we have received the characteristics.
+  log_v("<< retrieveDescriptors(): Found %d descriptors.", offset);
+}  // getDescriptors
 
 /**
  * @brief Retrieve the map of descriptors keyed by UUID.
  */
-std::map<std::string, BLERemoteDescriptor*>* BLERemoteCharacteristic::getDescriptors() {
-	return &m_descriptorMap;
-} // getDescriptors
-
+std::map<std::string, BLERemoteDescriptor *> *BLERemoteCharacteristic::getDescriptors() {
+  return &m_descriptorMap;
+}  // getDescriptors
 
 /**
  * @brief Get the handle for this characteristic.
  * @return The handle for this characteristic.
  */
 uint16_t BLERemoteCharacteristic::getHandle() {
-	//log_v(">> getHandle: Characteristic: %s", getUUID().toString().c_str());
-	//log_v("<< getHandle: %d 0x%.2x", m_handle, m_handle);
-	return m_handle;
-} // getHandle
-
+  //log_v(">> getHandle: Characteristic: %s", getUUID().toString().c_str());
+  //log_v("<< getHandle: %d 0x%.2x", m_handle, m_handle);
+  return m_handle;
+}  // getHandle
 
 /**
  * @brief Get the descriptor instance with the given UUID that belongs to this characteristic.
  * @param [in] uuid The UUID of the descriptor to find.
  * @return The Remote descriptor (if present) or null if not present.
  */
-BLERemoteDescriptor* BLERemoteCharacteristic::getDescriptor(BLEUUID uuid) {
-	log_v(">> getDescriptor: uuid: %s", uuid.toString().c_str());
-	std::string v = uuid.toString();
-	for (auto &myPair : m_descriptorMap) {
-		if (myPair.first == v) {
-			log_v("<< getDescriptor: found");
-			return myPair.second;
-		}
-	}
-	log_v("<< getDescriptor: Not found");
-	return nullptr;
-} // getDescriptor
-
+BLERemoteDescriptor *BLERemoteCharacteristic::getDescriptor(BLEUUID uuid) {
+  log_v(">> getDescriptor: uuid: %s", uuid.toString().c_str());
+  std::string v = uuid.toString().c_str();
+  for (auto &myPair : m_descriptorMap) {
+    if (myPair.first == v) {
+      log_v("<< getDescriptor: found");
+      return myPair.second;
+    }
+  }
+  log_v("<< getDescriptor: Not found");
+  return nullptr;
+}  // getDescriptor
 
 /**
  * @brief Get the remote service associated with this characteristic.
  * @return The remote service associated with this characteristic.
  */
-BLERemoteService* BLERemoteCharacteristic::getRemoteService() {
-	return m_pRemoteService;
-} // getRemoteService
-
+BLERemoteService *BLERemoteCharacteristic::getRemoteService() {
+  return m_pRemoteService;
+}  // getRemoteService
 
 /**
  * @brief Get the UUID for this characteristic.
  * @return The UUID for this characteristic.
  */
 BLEUUID BLERemoteCharacteristic::getUUID() {
-	return m_uuid;
-} // getUUID
-
+  return m_uuid;
+}  // getUUID
 
 /**
  * @brief Read an unsigned 16 bit value
  * @return The unsigned 16 bit value.
  */
 uint16_t BLERemoteCharacteristic::readUInt16() {
-	std::string value = readValue();
-	if (value.length() >= 2) {
-		return *(uint16_t*)(value.data());
-	}
-	return 0;
-} // readUInt16
-
+  String value = readValue();
+  if (value.length() >= 2) {
+    return *(uint16_t *)(value.c_str());
+  }
+  return 0;
+}  // readUInt16
 
 /**
  * @brief Read an unsigned 32 bit value.
  * @return the unsigned 32 bit value.
  */
 uint32_t BLERemoteCharacteristic::readUInt32() {
-	std::string value = readValue();
-	if (value.length() >= 4) {
-		return *(uint32_t*)(value.data());
-	}
-	return 0;
-} // readUInt32
-
+  String value = readValue();
+  if (value.length() >= 4) {
+    return *(uint32_t *)(value.c_str());
+  }
+  return 0;
+}  // readUInt32
 
 /**
  * @brief Read a byte value
  * @return The value as a byte
  */
 uint8_t BLERemoteCharacteristic::readUInt8() {
-	std::string value = readValue();
-	if (value.length() >= 1) {
-		return (uint8_t)value[0];
-	}
-	return 0;
-} // readUInt8
+  String value = readValue();
+  if (value.length() >= 1) {
+    return (uint8_t)value[0];
+  }
+  return 0;
+}  // readUInt8
 
 /**
  * @brief Read a float value.
  * @return the float value.
  */
 float BLERemoteCharacteristic::readFloat() {
-	std::string value = readValue();
-	if (value.length() >= 4) {
-		return *(float*)(value.data());
-	}
-	return 0.0;
-} // readFloat
+  String value = readValue();
+  if (value.length() >= 4) {
+    return *(float *)(value.c_str());
+  }
+  return 0.0;
+}  // readFloat
 
 /**
  * @brief Read the value of the remote characteristic.
  * @return The value of the remote characteristic.
  */
-std::string BLERemoteCharacteristic::readValue() {
-	log_v(">> readValue(): uuid: %s, handle: %d 0x%.2x", getUUID().toString().c_str(), getHandle(), getHandle());
-
-	// Check to see that we are connected.
-	if (!getRemoteService()->getClient()->isConnected()) {
-		log_e("Disconnected");
-		return std::string();
-	}
-
-	m_semaphoreReadCharEvt.take("readValue");
-
-	// Ask the BLE subsystem to retrieve the value for the remote hosted characteristic.
-	// This is an asynchronous request which means that we must block waiting for the response
-	// to become available.
-	esp_err_t errRc = ::esp_ble_gattc_read_char(
-		m_pRemoteService->getClient()->getGattcIf(),
-		m_pRemoteService->getClient()->getConnId(),    // The connection ID to the BLE server
-		getHandle(),                                   // The handle of this characteristic
-		m_auth);                                         // Security
-
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gattc_read_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return "";
-	}
-
-	// Block waiting for the event that indicates that the read has completed.  When it has, the std::string found
-	// in m_value will contain our data.
-	m_semaphoreReadCharEvt.wait("readValue");
-
-	log_v("<< readValue(): length: %d", m_value.length());
-	return m_value;
-} // readValue
-
+String BLERemoteCharacteristic::readValue() {
+  log_v(">> readValue(): uuid: %s, handle: %d 0x%.2x", getUUID().toString().c_str(), getHandle(), getHandle());
+
+  // Check to see that we are connected.
+  if (!getRemoteService()->getClient()->isConnected()) {
+    log_e("Disconnected");
+    return String();
+  }
+
+  m_semaphoreReadCharEvt.take("readValue");
+
+  // Ask the BLE subsystem to retrieve the value for the remote hosted characteristic.
+  // This is an asynchronous request which means that we must block waiting for the response
+  // to become available.
+  esp_err_t errRc = ::esp_ble_gattc_read_char(
+    m_pRemoteService->getClient()->getGattcIf(),
+    m_pRemoteService->getClient()->getConnId(),  // The connection ID to the BLE server
+    getHandle(),                                 // The handle of this characteristic
+    m_auth
+  );  // Security
+
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gattc_read_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return "";
+  }
+
+  // Block waiting for the event that indicates that the read has completed.  When it has, the String found
+  // in m_value will contain our data.
+  m_semaphoreReadCharEvt.wait("readValue");
+
+  log_v("<< readValue(): length: %d", m_value.length());
+  return m_value;
+}  // readValue
 
 /**
  * @brief Register for notifications.
@@ -453,87 +448,83 @@ std::string BLERemoteCharacteristic::readValue() {
  * unregistering a notification.
  * @return N/A.
  */
-void BLERemoteCharacteristic::registerForNotify(notify_callback notifyCallback, bool notifications) {
-	log_v(">> registerForNotify(): %s", toString().c_str());
-
-	m_notifyCallback = notifyCallback;   // Save the notification callback.
-
-	m_semaphoreRegForNotifyEvt.take("registerForNotify");
-
-	if (notifyCallback != nullptr) {   // If we have a callback function, then this is a registration.
-		esp_err_t errRc = ::esp_ble_gattc_register_for_notify(
-			m_pRemoteService->getClient()->getGattcIf(),
-			*m_pRemoteService->getClient()->getPeerAddress().getNative(),
-			getHandle()
-		);
-
-		if (errRc != ESP_OK) {
-			log_e("esp_ble_gattc_register_for_notify: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		}
-
-		uint8_t val[] = {0x01, 0x00};
-		if(!notifications) val[0] = 0x02;
-		BLERemoteDescriptor* desc = getDescriptor(BLEUUID((uint16_t)0x2902));
-		if (desc != nullptr)
-			desc->writeValue(val, 2, true);
-	} // End Register
-	else {   // If we weren't passed a callback function, then this is an unregistration.
-		esp_err_t errRc = ::esp_ble_gattc_unregister_for_notify(
-			m_pRemoteService->getClient()->getGattcIf(),
-			*m_pRemoteService->getClient()->getPeerAddress().getNative(),
-			getHandle()
-		);
-
-		if (errRc != ESP_OK) {
-			log_e("esp_ble_gattc_unregister_for_notify: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		}
-
-		uint8_t val[] = {0x00, 0x00};
-		BLERemoteDescriptor* desc = getDescriptor((uint16_t)0x2902);
-		if (desc != nullptr)
-			desc->writeValue(val, 2, true);
-	} // End Unregister
-
-	m_semaphoreRegForNotifyEvt.wait("registerForNotify");
-
-	log_v("<< registerForNotify()");
-} // registerForNotify
-
+void BLERemoteCharacteristic::registerForNotify(notify_callback notifyCallback, bool notifications, bool descriptorRequiresRegistration) {
+  log_v(">> registerForNotify(): %s", toString().c_str());
+
+  m_notifyCallback = notifyCallback;  // Save the notification callback.
+
+  m_semaphoreRegForNotifyEvt.take("registerForNotify");
+
+  if (notifyCallback != nullptr) {  // If we have a callback function, then this is a registration.
+    esp_err_t errRc = ::esp_ble_gattc_register_for_notify(
+      m_pRemoteService->getClient()->getGattcIf(), *m_pRemoteService->getClient()->getPeerAddress().getNative(), getHandle()
+    );
+
+    if (errRc != ESP_OK) {
+      log_e("esp_ble_gattc_register_for_notify: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    }
+
+    uint8_t val[] = {0x01, 0x00};
+    if (!notifications) {
+      val[0] = 0x02;
+    }
+    BLERemoteDescriptor *desc = getDescriptor(BLEUUID((uint16_t)0x2902));
+    if (desc != nullptr && descriptorRequiresRegistration) {
+      desc->writeValue(val, 2, true);
+    }
+  }  // End Register
+  else {  // If we weren't passed a callback function, then this is an unregistration.
+    esp_err_t errRc = ::esp_ble_gattc_unregister_for_notify(
+      m_pRemoteService->getClient()->getGattcIf(), *m_pRemoteService->getClient()->getPeerAddress().getNative(), getHandle()
+    );
+
+    if (errRc != ESP_OK) {
+      log_e("esp_ble_gattc_unregister_for_notify: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    }
+
+    uint8_t val[] = {0x00, 0x00};
+    BLERemoteDescriptor *desc = getDescriptor((uint16_t)0x2902);
+    if (desc != nullptr && descriptorRequiresRegistration) {
+      desc->writeValue(val, 2, true);
+    }
+  }  // End Unregister
+
+  m_semaphoreRegForNotifyEvt.wait("registerForNotify");
+
+  log_v("<< registerForNotify()");
+}  // registerForNotify
 
 /**
  * @brief Delete the descriptors in the descriptor map.
  * We maintain a map called m_descriptorMap that contains pointers to BLERemoteDescriptors
- * object references.  Since we allocated these in this class, we are also responsible for deleteing
+ * object references.  Since we allocated these in this class, we are also responsible for deleting
  * them.  This method does just that.
  * @return N/A.
  */
 void BLERemoteCharacteristic::removeDescriptors() {
-	// Iterate through all the descriptors releasing their storage and erasing them from the map.
-	for (auto &myPair : m_descriptorMap) {
-	   m_descriptorMap.erase(myPair.first);
-	   delete myPair.second;
-	}
-	m_descriptorMap.clear();   // Technically not neeeded, but just to be sure.
-} // removeCharacteristics
-
+  // Iterate through all the descriptors releasing their storage and erasing them from the map.
+  for (auto &myPair : m_descriptorMap) {
+    delete myPair.second;
+  }
+  m_descriptorMap.clear();
+}  // removeCharacteristics
 
 /**
  * @brief Convert a BLERemoteCharacteristic to a string representation;
  * @return a String representation.
  */
-std::string BLERemoteCharacteristic::toString() {
-	std::string res = "Characteristic: uuid: " + m_uuid.toString();
-	char val[6];
-	res += ", handle: ";
-	snprintf(val, sizeof(val), "%d", getHandle());
-	res += val;
-	res += " 0x";
-	snprintf(val, sizeof(val), "%04x", getHandle());
-	res += val;
-	res += ", props: " + BLEUtils::characteristicPropertiesToString(m_charProp);
-	return res;
-} // toString
-
+String BLERemoteCharacteristic::toString() {
+  String res = "Characteristic: uuid: " + m_uuid.toString();
+  char val[6];
+  res += ", handle: ";
+  snprintf(val, sizeof(val), "%d", getHandle());
+  res += val;
+  res += " 0x";
+  snprintf(val, sizeof(val), "%04x", getHandle());
+  res += val;
+  res += ", props: " + BLEUtils::characteristicPropertiesToString(m_charProp);
+  return res;
+}  // toString
 
 /**
  * @brief Write the new value for the characteristic.
@@ -541,10 +532,9 @@ std::string BLERemoteCharacteristic::toString() {
  * @param [in] response Do we expect a response?
  * @return N/A.
  */
-void BLERemoteCharacteristic::writeValue(std::string newValue, bool response) {
-	writeValue((uint8_t*)newValue.data(), newValue.length(), response);
-} // writeValue
-
+void BLERemoteCharacteristic::writeValue(String newValue, bool response) {
+  writeValue((uint8_t *)newValue.c_str(), newValue.length(), response);
+}  // writeValue
 
 /**
  * @brief Write the new value for the characteristic.
@@ -555,9 +545,8 @@ void BLERemoteCharacteristic::writeValue(std::string newValue, bool response) {
  * @return N/A.
  */
 void BLERemoteCharacteristic::writeValue(uint8_t newValue, bool response) {
-	writeValue(&newValue, 1, response);
-} // writeValue
-
+  writeValue(&newValue, 1, response);
+}  // writeValue
 
 /**
  * @brief Write the new value for the characteristic from a data buffer.
@@ -565,44 +554,39 @@ void BLERemoteCharacteristic::writeValue(uint8_t newValue, bool response) {
  * @param [in] length The length of the data in the data buffer.
  * @param [in] response Whether we require a response from the write.
  */
-void BLERemoteCharacteristic::writeValue(uint8_t* data, size_t length, bool response) {
-	// writeValue(std::string((char*)data, length), response);
-	log_v(">> writeValue(), length: %d", length);
-
-	// Check to see that we are connected.
-	if (!getRemoteService()->getClient()->isConnected()) {
-		log_e("Disconnected");
-		return;
-	}
+void BLERemoteCharacteristic::writeValue(uint8_t *data, size_t length, bool response) {
+  // writeValue(String((char*)data, length), response);
+  log_v(">> writeValue(), length: %d", length);
 
-	m_semaphoreWriteCharEvt.take("writeValue");
-	// Invoke the ESP-IDF API to perform the write.
-	esp_err_t errRc = ::esp_ble_gattc_write_char(
-		m_pRemoteService->getClient()->getGattcIf(),
-		m_pRemoteService->getClient()->getConnId(),
-		getHandle(),
-		length,
-		data,
-		response?ESP_GATT_WRITE_TYPE_RSP:ESP_GATT_WRITE_TYPE_NO_RSP,
-        m_auth
-	);
-
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gattc_write_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
+  // Check to see that we are connected.
+  if (!getRemoteService()->getClient()->isConnected()) {
+    log_e("Disconnected");
+    return;
+  }
+
+  m_semaphoreWriteCharEvt.take("writeValue");
+  // Invoke the ESP-IDF API to perform the write.
+  esp_err_t errRc = ::esp_ble_gattc_write_char(
+    m_pRemoteService->getClient()->getGattcIf(), m_pRemoteService->getClient()->getConnId(), getHandle(), length, data,
+    response ? ESP_GATT_WRITE_TYPE_RSP : ESP_GATT_WRITE_TYPE_NO_RSP, m_auth
+  );
+
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gattc_write_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return;
+  }
 
-	m_semaphoreWriteCharEvt.wait("writeValue");
+  m_semaphoreWriteCharEvt.wait("writeValue");
 
-	log_v("<< writeValue");
-} // writeValue
+  log_v("<< writeValue");
+}  // writeValue
 
 /**
  * @brief Read raw data from remote characteristic as hex bytes
  * @return return pointer data read
  */
-uint8_t* BLERemoteCharacteristic::readRawData() {
-	return m_rawData;
+uint8_t *BLERemoteCharacteristic::readRawData() {
+  return m_rawData;
 }
 
 /**
@@ -610,7 +594,8 @@ uint8_t* BLERemoteCharacteristic::readRawData() {
  * @param [in] auth Authentication request type.
  */
 void BLERemoteCharacteristic::setAuth(esp_gatt_auth_req_t auth) {
-    m_auth = auth;
+  m_auth = auth;
 }
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLERemoteCharacteristic.h b/libraries/BLE/src/BLERemoteCharacteristic.h
index 5ba0f2c6381..dc63a3bc1a6 100644
--- a/libraries/BLE/src/BLERemoteCharacteristic.h
+++ b/libraries/BLE/src/BLERemoteCharacteristic.h
@@ -7,81 +7,84 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEREMOTECHARACTERISTIC_H_
 #define COMPONENTS_CPP_UTILS_BLEREMOTECHARACTERISTIC_H_
-#include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
 
-#include <string>
+#include "sdkconfig.h"
+#if defined(CONFIG_BLUEDROID_ENABLED)
+#include <functional>
 
 #include <esp_gattc_api.h>
 
 #include "BLERemoteService.h"
 #include "BLERemoteDescriptor.h"
 #include "BLEUUID.h"
-#include "FreeRTOS.h"
+#include "RTOS.h"
 
 class BLERemoteService;
 class BLERemoteDescriptor;
-typedef void (*notify_callback)(BLERemoteCharacteristic* pBLERemoteCharacteristic, uint8_t* pData, size_t length, bool isNotify);
-
+typedef std::function<void(BLERemoteCharacteristic *pBLERemoteCharacteristic, uint8_t *pData, size_t length, bool isNotify)> notify_callback;
 /**
  * @brief A model of a remote %BLE characteristic.
  */
 class BLERemoteCharacteristic {
 public:
-	~BLERemoteCharacteristic();
+  ~BLERemoteCharacteristic();
 
-	// Public member functions
-	bool        canBroadcast();
-	bool        canIndicate();
-	bool        canNotify();
-	bool        canRead();
-	bool        canWrite();
-	bool        canWriteNoResponse();
-	BLERemoteDescriptor* getDescriptor(BLEUUID uuid);
-	std::map<std::string, BLERemoteDescriptor*>* getDescriptors();
-	uint16_t    getHandle();
-	BLEUUID     getUUID();
-	std::string readValue();
-	uint8_t     readUInt8();
-	uint16_t    readUInt16();
-	uint32_t    readUInt32();
-	float       readFloat();
-	void        registerForNotify(notify_callback _callback, bool notifications = true);
-	void        writeValue(uint8_t* data, size_t length, bool response = false);
-	void        writeValue(std::string newValue, bool response = false);
-	void        writeValue(uint8_t newValue, bool response = false);
-	std::string toString();
-	uint8_t*	readRawData();
-    void        setAuth(esp_gatt_auth_req_t auth);
+  // Public member functions
+  bool canBroadcast();
+  bool canIndicate();
+  bool canNotify();
+  bool canRead();
+  bool canWrite();
+  bool canWriteNoResponse();
+  BLERemoteDescriptor *getDescriptor(BLEUUID uuid);
+  std::map<std::string, BLERemoteDescriptor *> *getDescriptors();
+  BLERemoteService *getRemoteService();
+  uint16_t getHandle();
+  BLEUUID getUUID();
+  String readValue();
+  uint8_t readUInt8();
+  uint16_t readUInt16();
+  uint32_t readUInt32();
+  float readFloat();
+  void registerForNotify(notify_callback _callback, bool notifications = true, bool descriptorRequiresRegistration = true);
+  void writeValue(uint8_t *data, size_t length, bool response = false);
+  void writeValue(String newValue, bool response = false);
+  void writeValue(uint8_t newValue, bool response = false);
+  String toString();
+  uint8_t *readRawData();
+  void setAuth(esp_gatt_auth_req_t auth);
 
 private:
-	BLERemoteCharacteristic(uint16_t handle, BLEUUID uuid, esp_gatt_char_prop_t charProp, BLERemoteService* pRemoteService);
-	friend class BLEClient;
-	friend class BLERemoteService;
-	friend class BLERemoteDescriptor;
+  BLERemoteCharacteristic(uint16_t handle, BLEUUID uuid, esp_gatt_char_prop_t charProp, BLERemoteService *pRemoteService);
+  friend class BLEClient;
+  friend class BLERemoteService;
+  friend class BLERemoteDescriptor;
+
+  // Private member functions
+  void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam);
 
-	// Private member functions
-	void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t* evtParam);
+  void removeDescriptors();
+  void retrieveDescriptors();
 
-	BLERemoteService* getRemoteService();
-	void              removeDescriptors();
-	void              retrieveDescriptors();
+  // Private properties
+  BLEUUID m_uuid;
+  esp_gatt_char_prop_t m_charProp;
+  esp_gatt_auth_req_t m_auth;
+  uint16_t m_handle;
+  BLERemoteService *m_pRemoteService;
+  FreeRTOS::Semaphore m_semaphoreReadCharEvt = FreeRTOS::Semaphore("ReadCharEvt");
+  FreeRTOS::Semaphore m_semaphoreRegForNotifyEvt = FreeRTOS::Semaphore("RegForNotifyEvt");
+  FreeRTOS::Semaphore m_semaphoreWriteCharEvt = FreeRTOS::Semaphore("WriteCharEvt");
+  String m_value;
+  uint8_t *m_rawData;
+  notify_callback m_notifyCallback;
 
-	// Private properties
-	BLEUUID              m_uuid;
-	esp_gatt_char_prop_t m_charProp;
-    esp_gatt_auth_req_t  m_auth;
-	uint16_t             m_handle;
-	BLERemoteService*    m_pRemoteService;
-	FreeRTOS::Semaphore  m_semaphoreReadCharEvt      = FreeRTOS::Semaphore("ReadCharEvt");
-	FreeRTOS::Semaphore  m_semaphoreRegForNotifyEvt  = FreeRTOS::Semaphore("RegForNotifyEvt");
-	FreeRTOS::Semaphore  m_semaphoreWriteCharEvt     = FreeRTOS::Semaphore("WriteCharEvt");
-	std::string          m_value;
-	uint8_t 			 *m_rawData;
-	notify_callback		 m_notifyCallback;
+  // We maintain a map of descriptors owned by this characteristic keyed by a string representation of the UUID.
+  std::map<std::string, BLERemoteDescriptor *> m_descriptorMap;
+};  // BLERemoteCharacteristic
 
-	// We maintain a map of descriptors owned by this characteristic keyed by a string representation of the UUID.
-	std::map<std::string, BLERemoteDescriptor*> m_descriptorMap;
-}; // BLERemoteCharacteristic
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEREMOTECHARACTERISTIC_H_ */
diff --git a/libraries/BLE/src/BLERemoteDescriptor.cpp b/libraries/BLE/src/BLERemoteDescriptor.cpp
index b1e0bef221b..b6d654cf9ec 100644
--- a/libraries/BLE/src/BLERemoteDescriptor.cpp
+++ b/libraries/BLE/src/BLERemoteDescriptor.cpp
@@ -4,141 +4,153 @@
  *  Created on: Jul 8, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <sstream>
 #include "BLERemoteDescriptor.h"
 #include "GeneralUtils.h"
 #include "esp32-hal-log.h"
 
-BLERemoteDescriptor::BLERemoteDescriptor(
-	uint16_t                 handle,
-	BLEUUID                  uuid,
-	BLERemoteCharacteristic* pRemoteCharacteristic) {
+BLERemoteDescriptor::BLERemoteDescriptor(uint16_t handle, BLEUUID uuid, BLERemoteCharacteristic *pRemoteCharacteristic) {
 
-	m_handle                = handle;
-	m_uuid                  = uuid;
-	m_pRemoteCharacteristic = pRemoteCharacteristic;
-    m_auth                  = ESP_GATT_AUTH_REQ_NONE;
+  m_handle = handle;
+  m_uuid = uuid;
+  m_pRemoteCharacteristic = pRemoteCharacteristic;
+  m_auth = ESP_GATT_AUTH_REQ_NONE;
 }
 
-
 /**
  * @brief Retrieve the handle associated with this remote descriptor.
  * @return The handle associated with this remote descriptor.
  */
 uint16_t BLERemoteDescriptor::getHandle() {
-	return m_handle;
-} // getHandle
-
+  return m_handle;
+}  // getHandle
 
 /**
  * @brief Get the characteristic that owns this descriptor.
  * @return The characteristic that owns this descriptor.
  */
-BLERemoteCharacteristic* BLERemoteDescriptor::getRemoteCharacteristic() {
-	return m_pRemoteCharacteristic;
-} // getRemoteCharacteristic
-
+BLERemoteCharacteristic *BLERemoteDescriptor::getRemoteCharacteristic() {
+  return m_pRemoteCharacteristic;
+}  // getRemoteCharacteristic
 
 /**
  * @brief Retrieve the UUID associated this remote descriptor.
  * @return The UUID associated this remote descriptor.
  */
 BLEUUID BLERemoteDescriptor::getUUID() {
-	return m_uuid;
-} // getUUID
-
-void BLERemoteDescriptor::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t* evtParam) {
-	switch(event) {
-		case ESP_GATTC_READ_DESCR_EVT:
-			if (evtParam->read.handle != getHandle())
-				break;
-			m_semaphoreReadDescrEvt.give();
-			break;
-
-		case ESP_GATTC_WRITE_DESCR_EVT:
-			if (evtParam->write.handle != getHandle())
-				break;
-			m_semaphoreWriteDescrEvt.give();
-			break;
-		default:
-			break;
-	}
+  return m_uuid;
+}  // getUUID
+
+void BLERemoteDescriptor::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) {
+  switch (event) {
+    // ESP_GATTC_READ_DESCR_EVT
+    // This event indicates that the server has responded to the read request.
+    //
+    // read:
+    // - esp_gatt_status_t  status
+    // - uint16_t           conn_id
+    // - uint16_t           handle
+    // - uint8_t*           value
+    // - uint16_t           value_len
+    case ESP_GATTC_READ_DESCR_EVT:
+      // If this event is not for us, then nothing further to do.
+      if (evtParam->read.handle != getHandle()) {
+        break;
+      }
+      // At this point, we have determined that the event is for us, so now we save the value
+      if (evtParam->read.status == ESP_GATT_OK) {
+        // it will read the cached value of the descriptor
+        m_value = String((char *)evtParam->read.value, evtParam->read.value_len);
+      } else {
+        m_value = "";
+      }
+      // Unlock the semaphore to ensure that the requester of the data can continue.
+      m_semaphoreReadDescrEvt.give();
+      break;
+
+    case ESP_GATTC_WRITE_DESCR_EVT:
+      if (evtParam->write.handle != getHandle()) {
+        break;
+      }
+      m_semaphoreWriteDescrEvt.give();
+      break;
+    default: break;
+  }
 }
 
-std::string BLERemoteDescriptor::readValue() {
-	log_v(">> readValue: %s", toString().c_str());
-
-	// Check to see that we are connected.
-	if (!getRemoteCharacteristic()->getRemoteService()->getClient()->isConnected()) {
-		log_e("Disconnected");
-		return std::string();
-	}
+String BLERemoteDescriptor::readValue() {
+  log_v(">> readValue: %s", toString().c_str());
 
-	m_semaphoreReadDescrEvt.take("readValue");
+  // Check to see that we are connected.
+  if (!getRemoteCharacteristic()->getRemoteService()->getClient()->isConnected()) {
+    log_e("Disconnected");
+    return String();
+  }
 
-	// Ask the BLE subsystem to retrieve the value for the remote hosted characteristic.
-	esp_err_t errRc = ::esp_ble_gattc_read_char_descr(
-		m_pRemoteCharacteristic->getRemoteService()->getClient()->getGattcIf(),
-		m_pRemoteCharacteristic->getRemoteService()->getClient()->getConnId(),    // The connection ID to the BLE server
-		getHandle(),                                   // The handle of this characteristic
-		m_auth);                       // Security
+  m_semaphoreReadDescrEvt.take("readValue");
 
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gattc_read_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return "";
-	}
+  // Ask the BLE subsystem to retrieve the value for the remote hosted characteristic.
+  esp_err_t errRc = ::esp_ble_gattc_read_char_descr(
+    m_pRemoteCharacteristic->getRemoteService()->getClient()->getGattcIf(),
+    m_pRemoteCharacteristic->getRemoteService()->getClient()->getConnId(),  // The connection ID to the BLE server
+    getHandle(),                                                            // The handle of this characteristic
+    m_auth
+  );  // Security
 
-	// Block waiting for the event that indicates that the read has completed.  When it has, the std::string found
-	// in m_value will contain our data.
-	m_semaphoreReadDescrEvt.wait("readValue");
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gattc_read_char: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return "";
+  }
 
-	log_v("<< readValue(): length: %d", m_value.length());
-	return m_value;
-} // readValue
+  // Block waiting for the event that indicates that the read has completed.  When it has, the String found
+  // in m_value will contain our data.
+  m_semaphoreReadDescrEvt.wait("readValue");
 
+  log_v("<< readValue(): length: %d", m_value.length());
+  return m_value;
+}  // readValue
 
 uint8_t BLERemoteDescriptor::readUInt8() {
-	std::string value = readValue();
-	if (value.length() >= 1) {
-		return (uint8_t) value[0];
-	}
-	return 0;
-} // readUInt8
-
+  String value = readValue();
+  if (value.length() >= 1) {
+    return (uint8_t)value[0];
+  }
+  return 0;
+}  // readUInt8
 
 uint16_t BLERemoteDescriptor::readUInt16() {
-	std::string value = readValue();
-	if (value.length() >= 2) {
-		return *(uint16_t*) value.data();
-	}
-	return 0;
-} // readUInt16
-
+  String value = readValue();
+  if (value.length() >= 2) {
+    return *(uint16_t *)value.c_str();
+  }
+  return 0;
+}  // readUInt16
 
 uint32_t BLERemoteDescriptor::readUInt32() {
-	std::string value = readValue();
-	if (value.length() >= 4) {
-		return *(uint32_t*) value.data();
-	}
-	return 0;
-} // readUInt32
-
+  String value = readValue();
+  if (value.length() >= 4) {
+    return *(uint32_t *)value.c_str();
+  }
+  return 0;
+}  // readUInt32
 
 /**
  * @brief Return a string representation of this BLE Remote Descriptor.
- * @retun A string representation of this BLE Remote Descriptor.
+ * @return A string representation of this BLE Remote Descriptor.
  */
-std::string BLERemoteDescriptor::toString() {
-	char val[6];
-	snprintf(val, sizeof(val), "%d", getHandle());
-	std::string res = "handle: ";
-	res += val;
-	res += ", uuid: " + getUUID().toString();
-	return res;
-} // toString
-
+String BLERemoteDescriptor::toString() {
+  char val[6];
+  snprintf(val, sizeof(val), "%d", getHandle());
+  String res = "handle: ";
+  res += val;
+  res += ", uuid: " + getUUID().toString();
+  return res;
+}  // toString
 
 /**
  * @brief Write data to the BLE Remote Descriptor.
@@ -146,43 +158,38 @@ std::string BLERemoteDescriptor::toString() {
  * @param [in] length The length of the data to send.
  * @param [in] response True if we expect a response.
  */
-void BLERemoteDescriptor::writeValue(uint8_t* data, size_t length, bool response) {
-	log_v(">> writeValue: %s", toString().c_str());
-	// Check to see that we are connected.
-	if (!getRemoteCharacteristic()->getRemoteService()->getClient()->isConnected()) {
-		log_e("Disconnected");
-		return;
-	}
-
-	m_semaphoreWriteDescrEvt.take("writeValue");
-
-	esp_err_t errRc = ::esp_ble_gattc_write_char_descr(
-		m_pRemoteCharacteristic->getRemoteService()->getClient()->getGattcIf(),
-		m_pRemoteCharacteristic->getRemoteService()->getClient()->getConnId(),
-		getHandle(),
-		length,                           // Data length
-		data,                             // Data
-		response ? ESP_GATT_WRITE_TYPE_RSP : ESP_GATT_WRITE_TYPE_NO_RSP,
-		m_auth
-	);
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gattc_write_char_descr: %d", errRc);
-	}
-
-	m_semaphoreWriteDescrEvt.wait("writeValue");
-	log_v("<< writeValue");
-} // writeValue
-
+void BLERemoteDescriptor::writeValue(uint8_t *data, size_t length, bool response) {
+  log_v(">> writeValue: %s", toString().c_str());
+  // Check to see that we are connected.
+  if (!getRemoteCharacteristic()->getRemoteService()->getClient()->isConnected()) {
+    log_e("Disconnected");
+    return;
+  }
+
+  m_semaphoreWriteDescrEvt.take("writeValue");
+
+  esp_err_t errRc = ::esp_ble_gattc_write_char_descr(
+    m_pRemoteCharacteristic->getRemoteService()->getClient()->getGattcIf(), m_pRemoteCharacteristic->getRemoteService()->getClient()->getConnId(), getHandle(),
+    length,  // Data length
+    data,    // Data
+    response ? ESP_GATT_WRITE_TYPE_RSP : ESP_GATT_WRITE_TYPE_NO_RSP, m_auth
+  );
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gattc_write_char_descr: %d", errRc);
+  }
+
+  m_semaphoreWriteDescrEvt.wait("writeValue");
+  log_v("<< writeValue");
+}  // writeValue
 
 /**
  * @brief Write data represented as a string to the BLE Remote Descriptor.
  * @param [in] newValue The data to send to the remote descriptor.
  * @param [in] response True if we expect a response.
  */
-void BLERemoteDescriptor::writeValue(std::string newValue, bool response) {
-	writeValue((uint8_t*) newValue.data(), newValue.length(), response);
-} // writeValue
-
+void BLERemoteDescriptor::writeValue(String newValue, bool response) {
+  writeValue((uint8_t *)newValue.c_str(), newValue.length(), response);
+}  // writeValue
 
 /**
  * @brief Write a byte value to the Descriptor.
@@ -190,15 +197,16 @@ void BLERemoteDescriptor::writeValue(std::string newValue, bool response) {
  * @param [in] True if we expect a response.
  */
 void BLERemoteDescriptor::writeValue(uint8_t newValue, bool response) {
-	writeValue(&newValue, 1, response);
-} // writeValue
+  writeValue(&newValue, 1, response);
+}  // writeValue
 
 /**
  * @brief Set authentication request type for characteristic
  * @param [in] auth Authentication request type.
  */
 void BLERemoteDescriptor::setAuth(esp_gatt_auth_req_t auth) {
-    m_auth = auth;
+  m_auth = auth;
 }
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLERemoteDescriptor.h b/libraries/BLE/src/BLERemoteDescriptor.h
index ebd847f2c24..94b11f1490a 100644
--- a/libraries/BLE/src/BLERemoteDescriptor.h
+++ b/libraries/BLE/src/BLERemoteDescriptor.h
@@ -7,15 +7,18 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEREMOTEDESCRIPTOR_H_
 #define COMPONENTS_CPP_UTILS_BLEREMOTEDESCRIPTOR_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <string>
 
 #include <esp_gattc_api.h>
 
 #include "BLERemoteCharacteristic.h"
 #include "BLEUUID.h"
-#include "FreeRTOS.h"
+#include "RTOS.h"
 
 class BLERemoteCharacteristic;
 /**
@@ -23,36 +26,32 @@ class BLERemoteCharacteristic;
  */
 class BLERemoteDescriptor {
 public:
-	uint16_t    getHandle();
-	BLERemoteCharacteristic* getRemoteCharacteristic();
-	BLEUUID     getUUID();
-	std::string readValue(void);
-	uint8_t     readUInt8(void);
-	uint16_t    readUInt16(void);
-	uint32_t    readUInt32(void);
-	std::string toString(void);
-	void        writeValue(uint8_t* data, size_t length, bool response = false);
-	void        writeValue(std::string newValue, bool response = false);
-	void        writeValue(uint8_t newValue, bool response = false);
-    void        setAuth(esp_gatt_auth_req_t auth);
-	void        gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t* evtParam);
+  uint16_t getHandle();
+  BLERemoteCharacteristic *getRemoteCharacteristic();
+  BLEUUID getUUID();
+  String readValue(void);
+  uint8_t readUInt8(void);
+  uint16_t readUInt16(void);
+  uint32_t readUInt32(void);
+  String toString(void);
+  void writeValue(uint8_t *data, size_t length, bool response = false);
+  void writeValue(String newValue, bool response = false);
+  void writeValue(uint8_t newValue, bool response = false);
+  void setAuth(esp_gatt_auth_req_t auth);
+  void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam);
 
 private:
-	friend class BLERemoteCharacteristic;
-	BLERemoteDescriptor(
-		uint16_t                 handle,
-		BLEUUID                  uuid,
-		BLERemoteCharacteristic* pRemoteCharacteristic
-	);
-	uint16_t                 m_handle;                  // Server handle of this descriptor.
-	BLEUUID                  m_uuid;                    // UUID of this descriptor.
-	std::string              m_value;                   // Last received value of the descriptor.
-	BLERemoteCharacteristic* m_pRemoteCharacteristic;   // Reference to the Remote characteristic of which this descriptor is associated.
-	FreeRTOS::Semaphore      m_semaphoreReadDescrEvt      = FreeRTOS::Semaphore("ReadDescrEvt");
-	FreeRTOS::Semaphore      m_semaphoreWriteDescrEvt      = FreeRTOS::Semaphore("WriteDescrEvt");
-    esp_gatt_auth_req_t      m_auth;
-
-
+  friend class BLERemoteCharacteristic;
+  BLERemoteDescriptor(uint16_t handle, BLEUUID uuid, BLERemoteCharacteristic *pRemoteCharacteristic);
+  uint16_t m_handle;                                 // Server handle of this descriptor.
+  BLEUUID m_uuid;                                    // UUID of this descriptor.
+  String m_value;                                    // Last received value of the descriptor.
+  BLERemoteCharacteristic *m_pRemoteCharacteristic;  // Reference to the Remote characteristic of which this descriptor is associated.
+  FreeRTOS::Semaphore m_semaphoreReadDescrEvt = FreeRTOS::Semaphore("ReadDescrEvt");
+  FreeRTOS::Semaphore m_semaphoreWriteDescrEvt = FreeRTOS::Semaphore("WriteDescrEvt");
+  esp_gatt_auth_req_t m_auth;
 };
-#endif /* CONFIG_BT_ENABLED */
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEREMOTEDESCRIPTOR_H_ */
diff --git a/libraries/BLE/src/BLERemoteService.cpp b/libraries/BLE/src/BLERemoteService.cpp
index dfd36a90401..e4cc31dbb33 100644
--- a/libraries/BLE/src/BLERemoteService.cpp
+++ b/libraries/BLE/src/BLERemoteService.cpp
@@ -4,8 +4,11 @@
  *  Created on: Jul 8, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include <sstream>
 #include "BLERemoteService.h"
@@ -16,105 +19,94 @@
 
 #pragma GCC diagnostic warning "-Wunused-but-set-parameter"
 
-BLERemoteService::BLERemoteService(
-		esp_gatt_id_t srvcId,
-		BLEClient*    pClient,
-		uint16_t      startHandle,
-		uint16_t      endHandle
-	) {
-
-	log_v(">> BLERemoteService()");
-	m_srvcId  = srvcId;
-	m_pClient = pClient;
-	m_uuid    = BLEUUID(m_srvcId);
-	m_haveCharacteristics = false;
-	m_startHandle = startHandle;
-	m_endHandle = endHandle;
-
-	log_v("<< BLERemoteService()");
-}
+BLERemoteService::BLERemoteService(esp_gatt_id_t srvcId, BLEClient *pClient, uint16_t startHandle, uint16_t endHandle) {
+
+  log_v(">> BLERemoteService()");
+  m_srvcId = srvcId;
+  m_pClient = pClient;
+  m_uuid = BLEUUID(m_srvcId);
+  m_haveCharacteristics = false;
+  m_startHandle = startHandle;
+  m_endHandle = endHandle;
 
+  log_v("<< BLERemoteService()");
+}
 
 BLERemoteService::~BLERemoteService() {
-	removeCharacteristics();
+  removeCharacteristics();
 }
 
 /*
 static bool compareSrvcId(esp_gatt_srvc_id_t id1, esp_gatt_srvc_id_t id2) {
-	if (id1.id.inst_id != id2.id.inst_id) {
-		return false;
-	}
-	if (!BLEUUID(id1.id.uuid).equals(BLEUUID(id2.id.uuid))) {
-		return false;
-	}
-	return true;
+  if (id1.id.inst_id != id2.id.inst_id) {
+    return false;
+  }
+  if (!BLEUUID(id1.id.uuid).equals(BLEUUID(id2.id.uuid))) {
+    return false;
+  }
+  return true;
 } // compareSrvcId
 */
 
 /**
  * @brief Handle GATT Client events
  */
-void BLERemoteService::gattClientEventHandler(
-	esp_gattc_cb_event_t      event,
-	esp_gatt_if_t             gattc_if,
-	esp_ble_gattc_cb_param_t* evtParam) {
-	switch (event) {
-		//
-		// ESP_GATTC_GET_CHAR_EVT
-		//
-		// get_char:
-		// - esp_gatt_status_t    status
-		// - uin1t6_t             conn_id
-		// - esp_gatt_srvc_id_t   srvc_id
-		// - esp_gatt_id_t        char_id
-		// - esp_gatt_char_prop_t char_prop
-		//
-	/*
-		case ESP_GATTC_GET_CHAR_EVT: {
-			// Is this event for this service?  If yes, then the local srvc_id and the event srvc_id will be
-			// the same.
-			if (compareSrvcId(m_srvcId, evtParam->get_char.srvc_id) == false) {
-				break;
-			}
-
-			// If the status is NOT OK then we have a problem and continue.
-			if (evtParam->get_char.status != ESP_GATT_OK) {
-				m_semaphoreGetCharEvt.give();
-				break;
-			}
-
-			// This is an indication that we now have the characteristic details for a characteristic owned
-			// by this service so remember it.
-			m_characteristicMap.insert(std::pair<std::string, BLERemoteCharacteristic*>(
-					BLEUUID(evtParam->get_char.char_id.uuid).toString(),
-					new BLERemoteCharacteristic(evtParam->get_char.char_id, evtParam->get_char.char_prop, this)	));
-
-
-			// Now that we have received a characteristic, lets ask for the next one.
-			esp_err_t errRc = ::esp_ble_gattc_get_characteristic(
-					m_pClient->getGattcIf(),
-					m_pClient->getConnId(),
-					&m_srvcId,
-					&evtParam->get_char.char_id);
-			if (errRc != ESP_OK) {
-				log_e("esp_ble_gattc_get_characteristic: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-				break;
-			}
-
-			//m_semaphoreGetCharEvt.give();
-			break;
-		} // ESP_GATTC_GET_CHAR_EVT
+void BLERemoteService::gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) {
+  switch (event) {
+      //
+      // ESP_GATTC_GET_CHAR_EVT
+      //
+      // get_char:
+      // - esp_gatt_status_t    status
+      // - uin1t6_t             conn_id
+      // - esp_gatt_srvc_id_t   srvc_id
+      // - esp_gatt_id_t        char_id
+      // - esp_gatt_char_prop_t char_prop
+      //
+      /*
+    case ESP_GATTC_GET_CHAR_EVT: {
+      // Is this event for this service?  If yes, then the local srvc_id and the event srvc_id will be
+      // the same.
+      if (compareSrvcId(m_srvcId, evtParam->get_char.srvc_id) == false) {
+        break;
+      }
+
+      // If the status is NOT OK then we have a problem and continue.
+      if (evtParam->get_char.status != ESP_GATT_OK) {
+        m_semaphoreGetCharEvt.give();
+        break;
+      }
+
+      // This is an indication that we now have the characteristic details for a characteristic owned
+      // by this service so remember it.
+      m_characteristicMap.insert(std::pair<std::string, BLERemoteCharacteristic*>(
+          BLEUUID(evtParam->get_char.char_id.uuid).toString().c_str(),
+          new BLERemoteCharacteristic(evtParam->get_char.char_id, evtParam->get_char.char_prop, this)  ));
+
+
+      // Now that we have received a characteristic, lets ask for the next one.
+      esp_err_t errRc = ::esp_ble_gattc_get_characteristic(
+          m_pClient->getGattcIf(),
+          m_pClient->getConnId(),
+          &m_srvcId,
+          &evtParam->get_char.char_id);
+      if (errRc != ESP_OK) {
+        log_e("esp_ble_gattc_get_characteristic: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+        break;
+      }
+
+      //m_semaphoreGetCharEvt.give();
+      break;
+    } // ESP_GATTC_GET_CHAR_EVT
 */
-		default:
-			break;
-	} // switch
-
-	// Send the event to each of the characteristics owned by this service.
-	for (auto &myPair : m_characteristicMapByHandle) {
-	   myPair.second->gattClientEventHandler(event, gattc_if, evtParam);
-	}
-} // gattClientEventHandler
+    default: break;
+  }  // switch
 
+  // Send the event to each of the characteristics owned by this service.
+  for (auto &myPair : m_characteristicMapByHandle) {
+    myPair.second->gattClientEventHandler(event, gattc_if, evtParam);
+  }
+}  // gattClientEventHandler
 
 /**
  * @brief Get the remote characteristic object for the characteristic UUID.
@@ -122,36 +114,35 @@ void BLERemoteService::gattClientEventHandler(
  * @return Reference to the remote characteristic object.
  * @throws BLEUuidNotFoundException
  */
-BLERemoteCharacteristic* BLERemoteService::getCharacteristic(const char* uuid) {
-    return getCharacteristic(BLEUUID(uuid));
-} // getCharacteristic
-	
+BLERemoteCharacteristic *BLERemoteService::getCharacteristic(const char *uuid) {
+  return getCharacteristic(BLEUUID(uuid));
+}  // getCharacteristic
+
 /**
  * @brief Get the characteristic object for the UUID.
  * @param [in] uuid Characteristic uuid.
  * @return Reference to the characteristic object.
  * @throws BLEUuidNotFoundException
  */
-BLERemoteCharacteristic* BLERemoteService::getCharacteristic(BLEUUID uuid) {
-// Design
-// ------
-// We wish to retrieve the characteristic given its UUID.  It is possible that we have not yet asked the
-// device what characteristics it has in which case we have nothing to match against.  If we have not
-// asked the device about its characteristics, then we do that now.  Once we get the results we can then
-// examine the characteristics map to see if it has the characteristic we are looking for.
-	if (!m_haveCharacteristics) {
-		retrieveCharacteristics();
-	}
-	std::string v = uuid.toString();
-	for (auto &myPair : m_characteristicMap) {
-		if (myPair.first == v) {
-			return myPair.second;
-		}
-	}
-	// throw new BLEUuidNotFoundException();  // <-- we dont want exception here, which will cause app crash, we want to search if any characteristic can be found one after another
-	return nullptr;
-} // getCharacteristic
-
+BLERemoteCharacteristic *BLERemoteService::getCharacteristic(BLEUUID uuid) {
+  // Design
+  // ------
+  // We wish to retrieve the characteristic given its UUID.  It is possible that we have not yet asked the
+  // device what characteristics it has in which case we have nothing to match against.  If we have not
+  // asked the device about its characteristics, then we do that now.  Once we get the results we can then
+  // examine the characteristics map to see if it has the characteristic we are looking for.
+  if (!m_haveCharacteristics) {
+    retrieveCharacteristics();
+  }
+  std::string v = uuid.toString().c_str();
+  for (auto &myPair : m_characteristicMap) {
+    if (myPair.first == v) {
+      return myPair.second;
+    }
+  }
+  // throw new BLEUuidNotFoundException();  // <-- we dont want exception here, which will cause app crash, we want to search if any characteristic can be found one after another
+  return nullptr;
+}  // getCharacteristic
 
 /**
  * @brief Retrieve all the characteristics for this service.
@@ -159,165 +150,147 @@ BLERemoteCharacteristic* BLERemoteService::getCharacteristic(BLEUUID uuid) {
  * @return N/A
  */
 void BLERemoteService::retrieveCharacteristics() {
-	log_v(">> getCharacteristics() for service: %s", getUUID().toString().c_str());
-
-	removeCharacteristics(); // Forget any previous characteristics.
-
-	uint16_t offset = 0;
-	esp_gattc_char_elem_t result;
-	while (true) {
-		uint16_t count = 1; // only room for 1 result allocated, so go one by one
-		esp_gatt_status_t status = ::esp_ble_gattc_get_all_char(
-			getClient()->getGattcIf(),
-			getClient()->getConnId(),
-			m_startHandle,
-			m_endHandle,
-			&result,
-			&count,
-			offset
-		);
-
-		if (status == ESP_GATT_INVALID_OFFSET) {   // We have reached the end of the entries.
-			break;
-		}
-
-		if (status != ESP_GATT_OK) {   // If we got an error, end.
-			log_e("esp_ble_gattc_get_all_char: %s", BLEUtils::gattStatusToString(status).c_str());
-			break;
-		}
-
-		if (count == 0) {   // If we failed to get any new records, end.
-			break;
-		}
-
-		log_d("Found a characteristic: Handle: %d, UUID: %s", result.char_handle, BLEUUID(result.uuid).toString().c_str());
-
-		// We now have a new characteristic ... let us add that to our set of known characteristics
-		BLERemoteCharacteristic *pNewRemoteCharacteristic = new BLERemoteCharacteristic(
-			result.char_handle,
-			BLEUUID(result.uuid),
-			result.properties,
-			this
-		);
-
-		m_characteristicMap.insert(std::pair<std::string, BLERemoteCharacteristic*>(pNewRemoteCharacteristic->getUUID().toString(), pNewRemoteCharacteristic));
-		m_characteristicMapByHandle.insert(std::pair<uint16_t, BLERemoteCharacteristic*>(result.char_handle, pNewRemoteCharacteristic));
-		offset++;   // Increment our count of number of descriptors found.
-	} // Loop forever (until we break inside the loop).
-
-	m_haveCharacteristics = true; // Remember that we have received the characteristics.
-	log_v("<< getCharacteristics()");
-} // getCharacteristics
+  log_v(">> getCharacteristics() for service: %s", getUUID().toString().c_str());
+
+  removeCharacteristics();  // Forget any previous characteristics.
+
+  uint16_t offset = 0;
+  esp_gattc_char_elem_t result;
+  while (true) {
+    uint16_t count = 1;  // only room for 1 result allocated, so go one by one
+    esp_gatt_status_t status =
+      ::esp_ble_gattc_get_all_char(getClient()->getGattcIf(), getClient()->getConnId(), m_startHandle, m_endHandle, &result, &count, offset);
+
+    if (status == ESP_GATT_INVALID_OFFSET) {  // We have reached the end of the entries.
+      break;
+    }
+
+    if (status != ESP_GATT_OK) {  // If we got an error, end.
+      log_e("esp_ble_gattc_get_all_char: %s", BLEUtils::gattStatusToString(status).c_str());
+      break;
+    }
+
+    if (count == 0) {  // If we failed to get any new records, end.
+      break;
+    }
 
+    log_d("Found a characteristic: Handle: %d, UUID: %s", result.char_handle, BLEUUID(result.uuid).toString().c_str());
+
+    // We now have a new characteristic ... let us add that to our set of known characteristics
+    BLERemoteCharacteristic *pNewRemoteCharacteristic = new BLERemoteCharacteristic(result.char_handle, BLEUUID(result.uuid), result.properties, this);
+
+    m_characteristicMap.insert(
+      std::pair<std::string, BLERemoteCharacteristic *>(pNewRemoteCharacteristic->getUUID().toString().c_str(), pNewRemoteCharacteristic)
+    );
+    m_characteristicMapByHandle.insert(std::pair<uint16_t, BLERemoteCharacteristic *>(result.char_handle, pNewRemoteCharacteristic));
+    offset++;  // Increment our count of number of descriptors found.
+  }  // Loop forever (until we break inside the loop).
+
+  m_haveCharacteristics = true;  // Remember that we have received the characteristics.
+  log_v("<< getCharacteristics()");
+}  // getCharacteristics
 
 /**
  * @brief Retrieve a map of all the characteristics of this service.
  * @return A map of all the characteristics of this service.
  */
-std::map<std::string, BLERemoteCharacteristic*>* BLERemoteService::getCharacteristics() {
-	log_v(">> getCharacteristics() for service: %s", getUUID().toString().c_str());
-	// If is possible that we have not read the characteristics associated with the service so do that
-	// now.  The request to retrieve the characteristics by calling "retrieveCharacteristics" is a blocking
-	// call and does not return until all the characteristics are available.
-	if (!m_haveCharacteristics) {
-		retrieveCharacteristics();
-	}
-	log_v("<< getCharacteristics() for service: %s", getUUID().toString().c_str());
-	return &m_characteristicMap;
-} // getCharacteristics
+std::map<std::string, BLERemoteCharacteristic *> *BLERemoteService::getCharacteristics() {
+  log_v(">> getCharacteristics() for service: %s", getUUID().toString().c_str());
+  // If is possible that we have not read the characteristics associated with the service so do that
+  // now.  The request to retrieve the characteristics by calling "retrieveCharacteristics" is a blocking
+  // call and does not return until all the characteristics are available.
+  if (!m_haveCharacteristics) {
+    retrieveCharacteristics();
+  }
+  log_v("<< getCharacteristics() for service: %s", getUUID().toString().c_str());
+  return &m_characteristicMap;
+}  // getCharacteristics
 
 /**
  * @brief Retrieve a map of all the characteristics of this service.
  * @return A map of all the characteristics of this service.
  */
-std::map<uint16_t, BLERemoteCharacteristic*>* BLERemoteService::getCharacteristicsByHandle() {
-	// If is possible that we have not read the characteristics associated with the service so do that
-	// now.  The request to retrieve the characteristics by calling "retrieveCharacteristics" is a blocking
-	// call and does not return until all the characteristics are available.
-	if (!m_haveCharacteristics) {
-		retrieveCharacteristics();
-	}
-	return &m_characteristicMapByHandle;
-} // getCharacteristicsByHandle
+std::map<uint16_t, BLERemoteCharacteristic *> *BLERemoteService::getCharacteristicsByHandle() {
+  // If is possible that we have not read the characteristics associated with the service so do that
+  // now.  The request to retrieve the characteristics by calling "retrieveCharacteristics" is a blocking
+  // call and does not return until all the characteristics are available.
+  if (!m_haveCharacteristics) {
+    retrieveCharacteristics();
+  }
+  return &m_characteristicMapByHandle;
+}  // getCharacteristicsByHandle
 
 /**
  * @brief This function is designed to get characteristics map when we have multiple characteristics with the same UUID
  */
-void BLERemoteService::getCharacteristics(std::map<uint16_t, BLERemoteCharacteristic*>* pCharacteristicMap) {
-	log_v(">> getCharacteristics() for service: %s", getUUID().toString().c_str());
-	// If is possible that we have not read the characteristics associated with the service so do that
-	// now.  The request to retrieve the characteristics by calling "retrieveCharacteristics" is a blocking
-	// call and does not return until all the characteristics are available.
-	if (!m_haveCharacteristics) {
-		retrieveCharacteristics();
-	}
-	log_v("<< getCharacteristics() for service: %s", getUUID().toString().c_str());
-	*pCharacteristicMap = m_characteristicMapByHandle;
+void BLERemoteService::getCharacteristics(std::map<uint16_t, BLERemoteCharacteristic *> **pCharacteristicMap) {
+  log_v(">> getCharacteristics() for service: %s", getUUID().toString().c_str());
+  (void)pCharacteristicMap;
+  // If is possible that we have not read the characteristics associated with the service so do that
+  // now.  The request to retrieve the characteristics by calling "retrieveCharacteristics" is a blocking
+  // call and does not return until all the characteristics are available.
+  if (!m_haveCharacteristics) {
+    retrieveCharacteristics();
+  }
+  log_v("<< getCharacteristics() for service: %s", getUUID().toString().c_str());
+  *pCharacteristicMap = &m_characteristicMapByHandle;
 }  // Get the characteristics map.
 
 /**
  * @brief Get the client associated with this service.
  * @return A reference to the client associated with this service.
  */
-BLEClient* BLERemoteService::getClient() {
-	return m_pClient;
-} // getClient
-
+BLEClient *BLERemoteService::getClient() {
+  return m_pClient;
+}  // getClient
 
 uint16_t BLERemoteService::getEndHandle() {
-	return m_endHandle;
-} // getEndHandle
-
-
-esp_gatt_id_t* BLERemoteService::getSrvcId() {
-	return &m_srvcId;
-} // getSrvcId
+  return m_endHandle;
+}  // getEndHandle
 
+esp_gatt_id_t *BLERemoteService::getSrvcId() {
+  return &m_srvcId;
+}  // getSrvcId
 
 uint16_t BLERemoteService::getStartHandle() {
-	return m_startHandle;
-} // getStartHandle
-
+  return m_startHandle;
+}  // getStartHandle
 
 uint16_t BLERemoteService::getHandle() {
-	log_v(">> getHandle: service: %s", getUUID().toString().c_str());
-	log_v("<< getHandle: %d 0x%.2x", getStartHandle(), getStartHandle());
-	return getStartHandle();
-} // getHandle
-
+  log_v(">> getHandle: service: %s", getUUID().toString().c_str());
+  log_v("<< getHandle: %d 0x%.2x", getStartHandle(), getStartHandle());
+  return getStartHandle();
+}  // getHandle
 
 BLEUUID BLERemoteService::getUUID() {
-	return m_uuid;
+  return m_uuid;
 }
 
 /**
  * @brief Read the value of a characteristic associated with this service.
  */
-std::string BLERemoteService::getValue(BLEUUID characteristicUuid) {
-	log_v(">> readValue: uuid: %s", characteristicUuid.toString().c_str());
-	std::string ret =  getCharacteristic(characteristicUuid)->readValue();
-	log_v("<< readValue");
-	return ret;
-} // readValue
-
-
+String BLERemoteService::getValue(BLEUUID characteristicUuid) {
+  log_v(">> readValue: uuid: %s", characteristicUuid.toString().c_str());
+  String ret = getCharacteristic(characteristicUuid)->readValue();
+  log_v("<< readValue");
+  return ret;
+}  // readValue
 
 /**
  * @brief Delete the characteristics in the characteristics map.
  * We maintain a map called m_characteristicsMap that contains pointers to BLERemoteCharacteristic
- * object references.  Since we allocated these in this class, we are also responsible for deleteing
+ * object references.  Since we allocated these in this class, we are also responsible for deleting
  * them.  This method does just that.
  * @return N/A.
  */
 void BLERemoteService::removeCharacteristics() {
-	m_characteristicMap.clear();   // Clear the map
-	for (auto &myPair : m_characteristicMapByHandle) {
-	   delete myPair.second;
-	   // delete the characteristics only once
-	}
-	m_characteristicMapByHandle.clear();   // Clear the map
-} // removeCharacteristics
-
+  m_characteristicMap.clear();  // Clear the map
+  for (auto &myPair : m_characteristicMapByHandle) {
+    delete myPair.second;
+    // delete the characteristics only once
+  }
+  m_characteristicMapByHandle.clear();  // Clear the map
+}  // removeCharacteristics
 
 /**
  * @brief Set the value of a characteristic.
@@ -325,38 +298,37 @@ void BLERemoteService::removeCharacteristics() {
  * @param [in] value The value to set.
  * @throws BLEUuidNotFound
  */
-void BLERemoteService::setValue(BLEUUID characteristicUuid, std::string value) {
-	log_v(">> setValue: uuid: %s", characteristicUuid.toString().c_str());
-	getCharacteristic(characteristicUuid)->writeValue(value);
-	log_v("<< setValue");
-} // setValue
-
+void BLERemoteService::setValue(BLEUUID characteristicUuid, String value) {
+  log_v(">> setValue: uuid: %s", characteristicUuid.toString().c_str());
+  getCharacteristic(characteristicUuid)->writeValue(value);
+  log_v("<< setValue");
+}  // setValue
 
 /**
  * @brief Create a string representation of this remote service.
  * @return A string representation of this remote service.
  */
-std::string BLERemoteService::toString() {
-	std::string res = "Service: uuid: " + m_uuid.toString();
-	char val[6];
-	res += ", start_handle: ";
-	snprintf(val, sizeof(val), "%d", m_startHandle);
-	res += val;
-	snprintf(val, sizeof(val), "%04x", m_startHandle);
-	res += " 0x";
-	res += val;
-	res += ", end_handle: ";
-	snprintf(val, sizeof(val), "%d", m_endHandle);
-	res += val;
-	snprintf(val, sizeof(val), "%04x", m_endHandle);
-	res += " 0x";
-	res += val;
-	for (auto &myPair : m_characteristicMap) {
-		res += "\n" + myPair.second->toString();
-	   // myPair.second is the value
-	}
-	return res;
-} // toString
-
-
-#endif /* CONFIG_BT_ENABLED */
+String BLERemoteService::toString() {
+  String res = "Service: uuid: " + m_uuid.toString();
+  char val[6];
+  res += ", start_handle: ";
+  snprintf(val, sizeof(val), "%d", m_startHandle);
+  res += val;
+  snprintf(val, sizeof(val), "%04x", m_startHandle);
+  res += " 0x";
+  res += val;
+  res += ", end_handle: ";
+  snprintf(val, sizeof(val), "%d", m_endHandle);
+  res += val;
+  snprintf(val, sizeof(val), "%04x", m_endHandle);
+  res += " 0x";
+  res += val;
+  for (auto &myPair : m_characteristicMap) {
+    res += "\n" + myPair.second->toString();
+    // myPair.second is the value
+  }
+  return res;
+}  // toString
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLERemoteService.h b/libraries/BLE/src/BLERemoteService.h
index 2ab86738452..49845a0a1e8 100644
--- a/libraries/BLE/src/BLERemoteService.h
+++ b/libraries/BLE/src/BLERemoteService.h
@@ -7,79 +7,79 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEREMOTESERVICE_H_
 #define COMPONENTS_CPP_UTILS_BLEREMOTESERVICE_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include <map>
 
 #include "BLEClient.h"
 #include "BLERemoteCharacteristic.h"
 #include "BLEUUID.h"
-#include "FreeRTOS.h"
+#include "RTOS.h"
 
 class BLEClient;
 class BLERemoteCharacteristic;
 
-
 /**
  * @brief A model of a remote %BLE service.
  */
 class BLERemoteService {
 public:
-	virtual ~BLERemoteService();
-
-	// Public methods
-	BLERemoteCharacteristic* getCharacteristic(const char* uuid);	  // Get the specified characteristic reference.
-	BLERemoteCharacteristic* getCharacteristic(BLEUUID uuid);       // Get the specified characteristic reference.
-	BLERemoteCharacteristic* getCharacteristic(uint16_t uuid);      // Get the specified characteristic reference.
-	std::map<std::string, BLERemoteCharacteristic*>* getCharacteristics();
-	std::map<uint16_t, BLERemoteCharacteristic*>* getCharacteristicsByHandle();  // Get the characteristics map.
-	void getCharacteristics(std::map<uint16_t, BLERemoteCharacteristic*>* pCharacteristicMap);
-
-	BLEClient*               getClient(void);                                           // Get a reference to the client associated with this service.
-	uint16_t                 getHandle();                                               // Get the handle of this service.
-	BLEUUID                  getUUID(void);                                             // Get the UUID of this service.
-	std::string              getValue(BLEUUID characteristicUuid);                      // Get the value of a characteristic.
-	void                     setValue(BLEUUID characteristicUuid, std::string value);   // Set the value of a characteristic.
-	std::string              toString(void);
+  virtual ~BLERemoteService();
+
+  // Public methods
+  BLERemoteCharacteristic *getCharacteristic(const char *uuid);  // Get the specified characteristic reference.
+  BLERemoteCharacteristic *getCharacteristic(BLEUUID uuid);      // Get the specified characteristic reference.
+  BLERemoteCharacteristic *getCharacteristic(uint16_t uuid);     // Get the specified characteristic reference.
+  std::map<std::string, BLERemoteCharacteristic *> *getCharacteristics();
+  std::map<uint16_t, BLERemoteCharacteristic *> *getCharacteristicsByHandle();  // Get the characteristics map.
+  void getCharacteristics(std::map<uint16_t, BLERemoteCharacteristic *> **pCharacteristicMap);
+
+  BLEClient *getClient(void);                               // Get a reference to the client associated with this service.
+  uint16_t getHandle();                                     // Get the handle of this service.
+  BLEUUID getUUID(void);                                    // Get the UUID of this service.
+  String getValue(BLEUUID characteristicUuid);              // Get the value of a characteristic.
+  void setValue(BLEUUID characteristicUuid, String value);  // Set the value of a characteristic.
+  String toString(void);
 
 private:
-	// Private constructor ... never meant to be created by a user application.
-	BLERemoteService(esp_gatt_id_t srvcId, BLEClient* pClient, uint16_t startHandle, uint16_t endHandle);
+  // Private constructor ... never meant to be created by a user application.
+  BLERemoteService(esp_gatt_id_t srvcId, BLEClient *pClient, uint16_t startHandle, uint16_t endHandle);
 
-	// Friends
-	friend class BLEClient;
-	friend class BLERemoteCharacteristic;
+  // Friends
+  friend class BLEClient;
+  friend class BLERemoteCharacteristic;
 
-	// Private methods
-	void                retrieveCharacteristics(void);   // Retrieve the characteristics from the BLE Server.
-	esp_gatt_id_t*      getSrvcId(void);
-	uint16_t            getStartHandle();                // Get the start handle for this service.
-	uint16_t            getEndHandle();                  // Get the end handle for this service.
+  // Private methods
+  void retrieveCharacteristics(void);  // Retrieve the characteristics from the BLE Server.
+  esp_gatt_id_t *getSrvcId(void);
+  uint16_t getStartHandle();  // Get the start handle for this service.
+  uint16_t getEndHandle();    // Get the end handle for this service.
 
-	void                gattClientEventHandler(
-		esp_gattc_cb_event_t      event,
-		esp_gatt_if_t             gattc_if,
-		esp_ble_gattc_cb_param_t* evtParam);
+  void gattClientEventHandler(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam);
 
-	void                removeCharacteristics();
+  void removeCharacteristics();
 
-	// Properties
+  // Properties
 
-	// We maintain a map of characteristics owned by this service keyed by a string representation of the UUID.
-	std::map<std::string, BLERemoteCharacteristic*> m_characteristicMap;
+  // We maintain a map of characteristics owned by this service keyed by a string representation of the UUID.
+  std::map<std::string, BLERemoteCharacteristic *> m_characteristicMap;
 
-	// We maintain a map of characteristics owned by this service keyed by a handle.
-	std::map<uint16_t, BLERemoteCharacteristic*> m_characteristicMapByHandle;
+  // We maintain a map of characteristics owned by this service keyed by a handle.
+  std::map<uint16_t, BLERemoteCharacteristic *> m_characteristicMapByHandle;
 
-	bool                m_haveCharacteristics; // Have we previously obtained the characteristics.
-	BLEClient*          m_pClient;
-	FreeRTOS::Semaphore m_semaphoreGetCharEvt = FreeRTOS::Semaphore("GetCharEvt");
-	esp_gatt_id_t       m_srvcId;
-	BLEUUID             m_uuid;             // The UUID of this service.
-	uint16_t            m_startHandle;      // The starting handle of this service.
-	uint16_t            m_endHandle;        // The ending handle of this service.
-}; // BLERemoteService
+  bool m_haveCharacteristics;  // Have we previously obtained the characteristics.
+  BLEClient *m_pClient;
+  FreeRTOS::Semaphore m_semaphoreGetCharEvt = FreeRTOS::Semaphore("GetCharEvt");
+  esp_gatt_id_t m_srvcId;
+  BLEUUID m_uuid;          // The UUID of this service.
+  uint16_t m_startHandle;  // The starting handle of this service.
+  uint16_t m_endHandle;    // The ending handle of this service.
+};  // BLERemoteService
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEREMOTESERVICE_H_ */
diff --git a/libraries/BLE/src/BLEScan.cpp b/libraries/BLE/src/BLEScan.cpp
index e6e962be61e..0a99b46c61d 100644
--- a/libraries/BLE/src/BLEScan.cpp
+++ b/libraries/BLE/src/BLEScan.cpp
@@ -3,10 +3,15 @@
  *
  *  Created on: Jul 1, 2017
  *      Author: kolban
+ *
+ * 	Update: April, 2021
+ * 		add BLE5 support
  */
-#include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
 
+#include "sdkconfig.h"
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include <esp_err.h>
 
@@ -22,133 +27,223 @@
  * Constructor
  */
 BLEScan::BLEScan() {
-	memset(&m_scan_params, 0, sizeof(m_scan_params)); // Initialize all params
-	m_scan_params.scan_type          = BLE_SCAN_TYPE_PASSIVE; // Default is a passive scan.
-	m_scan_params.own_addr_type      = BLE_ADDR_TYPE_PUBLIC;
-	m_scan_params.scan_filter_policy = BLE_SCAN_FILTER_ALLOW_ALL;
-	m_scan_params.scan_duplicate     = BLE_SCAN_DUPLICATE_DISABLE;
-	m_pAdvertisedDeviceCallbacks     = nullptr;
-	m_stopped                        = true;
-	m_wantDuplicates                 = false;
-	m_shouldParse                    = true;
-	setInterval(100);
-	setWindow(100);
-} // BLEScan
-
+  memset(&m_scan_params, 0, sizeof(m_scan_params));  // Initialize all params
+  m_scan_params.scan_type = BLE_SCAN_TYPE_PASSIVE;   // Default is a passive scan.
+  m_scan_params.own_addr_type = BLE_ADDR_TYPE_PUBLIC;
+  m_scan_params.scan_filter_policy = BLE_SCAN_FILTER_ALLOW_ALL;
+  m_scan_params.scan_duplicate = BLE_SCAN_DUPLICATE_DISABLE;
+  m_pAdvertisedDeviceCallbacks = nullptr;
+  m_stopped = true;
+  m_wantDuplicates = false;
+  m_shouldParse = true;
+  setInterval(100);
+  setWindow(100);
+}  // BLEScan
 
 /**
  * @brief Handle GAP events related to scans.
  * @param [in] event The event type for this event.
  * @param [in] param Parameter data for this event.
  */
-void BLEScan::handleGAPEvent(
-	esp_gap_ble_cb_event_t  event,
-	esp_ble_gap_cb_param_t* param) {
-
-	switch(event) {
-
-		// ---------------------------
-		// scan_rst:
-		// esp_gap_search_evt_t search_evt
-		// esp_bd_addr_t bda
-		// esp_bt_dev_type_t dev_type
-		// esp_ble_addr_type_t ble_addr_type
-		// esp_ble_evt_type_t ble_evt_type
-		// int rssi
-		// uint8_t ble_adv[ESP_BLE_ADV_DATA_LEN_MAX]
-		// int flag
-		// int num_resps
-		// uint8_t adv_data_len
-		// uint8_t scan_rsp_len
-		case ESP_GAP_BLE_SCAN_RESULT_EVT: {
-
-			switch(param->scan_rst.search_evt) {
-				//
-				// ESP_GAP_SEARCH_INQ_CMPL_EVT
-				//
-				// Event that indicates that the duration allowed for the search has completed or that we have been
-				// asked to stop.
-				case ESP_GAP_SEARCH_INQ_CMPL_EVT: {
-					log_w("ESP_GAP_SEARCH_INQ_CMPL_EVT");
-					m_stopped = true;
-					m_semaphoreScanEnd.give();
-					if (m_scanCompleteCB != nullptr) {
-						m_scanCompleteCB(m_scanResults);
-					}
-					break;
-				} // ESP_GAP_SEARCH_INQ_CMPL_EVT
-
-				//
-				// ESP_GAP_SEARCH_INQ_RES_EVT
-				//
-				// Result that has arrived back from a Scan inquiry.
-				case ESP_GAP_SEARCH_INQ_RES_EVT: {
-					if (m_stopped) { // If we are not scanning, nothing to do with the extra results.
-						break;
-					}
-
-// Examine our list of previously scanned addresses and, if we found this one already,
-// ignore it.
-					BLEAddress advertisedAddress(param->scan_rst.bda);
-					bool found = false;
-					bool shouldDelete = true;
-
-					if (!m_wantDuplicates) {
-						if (m_scanResults.m_vectorAdvertisedDevices.count(advertisedAddress.toString()) != 0) {
-							found = true;
-						}
-
-						if (found) {  // If we found a previous entry AND we don't want duplicates, then we are done.
-							log_d("Ignoring %s, already seen it.", advertisedAddress.toString().c_str());
-							vTaskDelay(1);  // <--- allow to switch task in case we scan infinity and dont have new devices to report, or we are blocked here
-							break;
-						}
-					}
-
-					// We now construct a model of the advertised device that we have just found for the first
-					// time.
-					// ESP_LOG_BUFFER_HEXDUMP((uint8_t*)param->scan_rst.ble_adv, param->scan_rst.adv_data_len + param->scan_rst.scan_rsp_len, ESP_LOG_DEBUG);
-					// log_w("bytes length: %d + %d, addr type: %d", param->scan_rst.adv_data_len, param->scan_rst.scan_rsp_len, param->scan_rst.ble_addr_type);
-					BLEAdvertisedDevice *advertisedDevice = new BLEAdvertisedDevice();
-					advertisedDevice->setAddress(advertisedAddress);
-					advertisedDevice->setRSSI(param->scan_rst.rssi);
-					advertisedDevice->setAdFlag(param->scan_rst.flag);
-					if (m_shouldParse) {
-						advertisedDevice->parseAdvertisement((uint8_t*)param->scan_rst.ble_adv, param->scan_rst.adv_data_len + param->scan_rst.scan_rsp_len);
-					} else {
-						advertisedDevice->setPayload((uint8_t*)param->scan_rst.ble_adv, param->scan_rst.adv_data_len + param->scan_rst.scan_rsp_len);
-					}
-					advertisedDevice->setScan(this);
-					advertisedDevice->setAddressType(param->scan_rst.ble_addr_type);
-
-					if (m_pAdvertisedDeviceCallbacks) { // if has callback, no need to record to vector
-						m_pAdvertisedDeviceCallbacks->onResult(*advertisedDevice);
-					} else if (!m_wantDuplicates && !found) {   // if no callback and not want duplicate, and not already in vector, record it
-						m_scanResults.m_vectorAdvertisedDevices.insert(std::pair<std::string, BLEAdvertisedDevice*>(advertisedAddress.toString(), advertisedDevice));
-						shouldDelete = false;
-					}
-					if (shouldDelete) {
-						delete advertisedDevice;
-					}
-
-					break;
-				} // ESP_GAP_SEARCH_INQ_RES_EVT
-
-				default: {
-					break;
-				}
-			} // switch - search_evt
-
-
-			break;
-		} // ESP_GAP_BLE_SCAN_RESULT_EVT
-
-		default: {
-			break;
-		} // default
-	} // End switch
-} // gapEventHandler
-
+void BLEScan::handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) {
+
+  switch (event) {
+
+    // ---------------------------
+    // scan_rst:
+    // esp_gap_search_evt_t search_evt
+    // esp_bd_addr_t bda
+    // esp_bt_dev_type_t dev_type
+    // esp_ble_addr_type_t ble_addr_type
+    // esp_ble_evt_type_t ble_evt_type
+    // int rssi
+    // uint8_t ble_adv[ESP_BLE_ADV_DATA_LEN_MAX]
+    // int flag
+    // int num_resps
+    // uint8_t adv_data_len
+    // uint8_t scan_rsp_len
+    case ESP_GAP_BLE_SCAN_RESULT_EVT:
+    {
+
+      switch (param->scan_rst.search_evt) {
+        //
+        // ESP_GAP_SEARCH_INQ_CMPL_EVT
+        //
+        // Event that indicates that the duration allowed for the search has completed or that we have been
+        // asked to stop.
+        case ESP_GAP_SEARCH_INQ_CMPL_EVT:
+        {
+          log_w("ESP_GAP_SEARCH_INQ_CMPL_EVT");
+          m_stopped = true;
+          m_semaphoreScanEnd.give();
+          if (m_scanCompleteCB != nullptr) {
+            m_scanCompleteCB(m_scanResults);
+          }
+          break;
+        }  // ESP_GAP_SEARCH_INQ_CMPL_EVT
+
+        //
+        // ESP_GAP_SEARCH_INQ_RES_EVT
+        //
+        // Result that has arrived back from a Scan inquiry.
+        case ESP_GAP_SEARCH_INQ_RES_EVT:
+        {
+          if (m_stopped) {  // If we are not scanning, nothing to do with the extra results.
+            break;
+          }
+
+          // Examine our list of previously scanned addresses and, if we found this one already,
+          // ignore it.
+          BLEAddress advertisedAddress(param->scan_rst.bda);
+          bool found = false;
+          bool shouldDelete = true;
+
+          if (!m_wantDuplicates) {
+            if (m_scanResults.m_vectorAdvertisedDevices.count(advertisedAddress.toString().c_str()) != 0) {
+              found = true;
+            }
+
+            if (found) {  // If we found a previous entry AND we don't want duplicates, then we are done.
+              log_d("Ignoring %s, already seen it.", advertisedAddress.toString().c_str());
+              vTaskDelay(1);  // <--- allow to switch task in case we scan infinity and dont have new devices to report, or we are blocked here
+              break;
+            }
+          }
+
+          // We now construct a model of the advertised device that we have just found for the first
+          // time.
+          // ESP_LOG_BUFFER_HEXDUMP((uint8_t*)param->scan_rst.ble_adv, param->scan_rst.adv_data_len + param->scan_rst.scan_rsp_len, ESP_LOG_DEBUG);
+          // log_w("bytes length: %d + %d, addr type: %d", param->scan_rst.adv_data_len, param->scan_rst.scan_rsp_len, param->scan_rst.ble_addr_type);
+          BLEAdvertisedDevice *advertisedDevice = new BLEAdvertisedDevice();
+          advertisedDevice->setAddress(advertisedAddress);
+          advertisedDevice->setRSSI(param->scan_rst.rssi);
+          advertisedDevice->setAdFlag(param->scan_rst.flag);
+          if (m_shouldParse) {
+            advertisedDevice->parseAdvertisement((uint8_t *)param->scan_rst.ble_adv, param->scan_rst.adv_data_len + param->scan_rst.scan_rsp_len);
+          } else {
+            advertisedDevice->setPayload((uint8_t *)param->scan_rst.ble_adv, param->scan_rst.adv_data_len + param->scan_rst.scan_rsp_len);
+          }
+          advertisedDevice->setScan(this);
+          advertisedDevice->setAddressType(param->scan_rst.ble_addr_type);
+
+          if (m_pAdvertisedDeviceCallbacks) {  // if has callback, no need to record to vector
+            m_pAdvertisedDeviceCallbacks->onResult(*advertisedDevice);
+          }
+          if (!m_wantDuplicates && !found) {  // if no callback and not want duplicate, and not already in vector, record it
+            m_scanResults.m_vectorAdvertisedDevices.insert(std::pair<std::string, BLEAdvertisedDevice *>(advertisedAddress.toString().c_str(), advertisedDevice)
+            );
+            shouldDelete = false;
+          }
+          if (shouldDelete) {
+            delete advertisedDevice;
+          }
+
+          break;
+        }  // ESP_GAP_SEARCH_INQ_RES_EVT
+
+        default:
+        {
+          break;
+        }
+      }  // switch - search_evt
+
+      break;
+    }  // ESP_GAP_BLE_SCAN_RESULT_EVT
+#ifdef SOC_BLE_50_SUPPORTED
+    case ESP_GAP_BLE_EXT_ADV_REPORT_EVT:
+    {
+      if (param->ext_adv_report.params.event_type & ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY) {
+        log_v("legacy adv, adv type 0x%x data len %d", param->ext_adv_report.params.event_type, param->ext_adv_report.params.adv_data_len);
+      } else {
+        log_v(
+          "extend adv, adv type 0x%x data len %d, data status: %d", param->ext_adv_report.params.event_type, param->ext_adv_report.params.adv_data_len,
+          param->ext_adv_report.params.data_status
+        );
+      }
+
+      if (m_pExtendedScanCb != nullptr) {
+        m_pExtendedScanCb->onResult(param->ext_adv_report.params);
+      }
+
+      break;
+    }
+
+    case ESP_GAP_BLE_SET_EXT_SCAN_PARAMS_COMPLETE_EVT:
+    {
+      if (param->set_ext_scan_params.status != ESP_BT_STATUS_SUCCESS) {
+        log_e("extend scan parameters set failed, error status = %x", param->set_ext_scan_params.status);
+        break;
+      }
+      log_v("extend scan params set successfully");
+      break;
+    }
+
+    case ESP_GAP_BLE_EXT_SCAN_START_COMPLETE_EVT:
+      if (param->ext_scan_start.status != ESP_BT_STATUS_SUCCESS) {
+        log_e("scan start failed, error status = %x", param->scan_start_cmpl.status);
+        break;
+      }
+      log_v("Scan start success");
+      break;
+
+    case ESP_GAP_BLE_EXT_SCAN_STOP_COMPLETE_EVT:
+      if (m_pPeriodicScanCb != nullptr) {
+        m_pPeriodicScanCb->onStop(param->ext_scan_stop.status);
+      }
+
+      if (param->ext_scan_stop.status != ESP_BT_STATUS_SUCCESS) {
+        log_e("extend Scan stop failed, error status = %x", param->ext_scan_stop.status);
+        break;
+      }
+      log_v("Stop extend scan successfully");
+      break;
+
+    case ESP_GAP_BLE_PERIODIC_ADV_CREATE_SYNC_COMPLETE_EVT:
+      if (m_pPeriodicScanCb != nullptr) {
+        m_pPeriodicScanCb->onCreateSync(param->period_adv_create_sync.status);
+      }
+
+      log_v("ESP_GAP_BLE_PERIODIC_ADV_CREATE_SYNC_COMPLETE_EVT, status %d", param->period_adv_create_sync.status);
+      break;
+    case ESP_GAP_BLE_PERIODIC_ADV_SYNC_CANCEL_COMPLETE_EVT:
+      if (m_pPeriodicScanCb != nullptr) {
+        m_pPeriodicScanCb->onCancelSync(param->period_adv_sync_cancel.status);
+      }
+      log_v("ESP_GAP_BLE_PERIODIC_ADV_SYNC_CANCEL_COMPLETE_EVT, status %d", param->period_adv_sync_cancel.status);
+      break;
+    case ESP_GAP_BLE_PERIODIC_ADV_SYNC_TERMINATE_COMPLETE_EVT:
+      if (m_pPeriodicScanCb != nullptr) {
+        m_pPeriodicScanCb->onTerminateSync(param->period_adv_sync_term.status);
+      }
+      log_v("ESP_GAP_BLE_PERIODIC_ADV_SYNC_TERMINATE_COMPLETE_EVT, status %d", param->period_adv_sync_term.status);
+      break;
+    case ESP_GAP_BLE_PERIODIC_ADV_SYNC_LOST_EVT:
+      if (m_pPeriodicScanCb != nullptr) {
+        m_pPeriodicScanCb->onLostSync(param->periodic_adv_sync_lost.sync_handle);
+      }
+      log_v("ESP_GAP_BLE_PERIODIC_ADV_SYNC_LOST_EVT, sync handle %d", param->periodic_adv_sync_lost.sync_handle);
+      break;
+    case ESP_GAP_BLE_PERIODIC_ADV_SYNC_ESTAB_EVT:
+      if (m_pPeriodicScanCb != nullptr) {
+        m_pPeriodicScanCb->onSync(*(esp_ble_periodic_adv_sync_estab_param_t *)&param->periodic_adv_sync_estab);
+      }
+      log_v("ESP_GAP_BLE_PERIODIC_ADV_SYNC_ESTAB_EVT, status %d", param->periodic_adv_sync_estab.status);
+      break;
+
+    case ESP_GAP_BLE_PERIODIC_ADV_REPORT_EVT:
+      if (m_pPeriodicScanCb != nullptr) {
+        m_pPeriodicScanCb->onReport(param->period_adv_report.params);
+      }
+      break;
+
+#endif  // SOC_BLE_50_SUPPORTED
+
+    default:
+    {
+      break;
+    }  // default
+  }  // End switch
+}  // gapEventHandler
 
 /**
  * @brief Should we perform an active or passive scan?
@@ -157,13 +252,12 @@ void BLEScan::handleGAPEvent(
  * @return N/A.
  */
 void BLEScan::setActiveScan(bool active) {
-	if (active) {
-		m_scan_params.scan_type = BLE_SCAN_TYPE_ACTIVE;
-	} else {
-		m_scan_params.scan_type = BLE_SCAN_TYPE_PASSIVE;
-	}
-} // setActiveScan
-
+  if (active) {
+    m_scan_params.scan_type = BLE_SCAN_TYPE_ACTIVE;
+  } else {
+    m_scan_params.scan_type = BLE_SCAN_TYPE_PASSIVE;
+  }
+}  // setActiveScan
 
 /**
  * @brief Set the call backs to be invoked.
@@ -171,29 +265,105 @@ void BLEScan::setActiveScan(bool active) {
  * @param [in] wantDuplicates  True if we wish to be called back with duplicates.  Default is false.
  * @param [in] shouldParse  True if we wish to parse advertised package or raw payload.  Default is true.
  */
-void BLEScan::setAdvertisedDeviceCallbacks(BLEAdvertisedDeviceCallbacks* pAdvertisedDeviceCallbacks, bool wantDuplicates, bool shouldParse) {
-	m_wantDuplicates = wantDuplicates;
-	m_pAdvertisedDeviceCallbacks = pAdvertisedDeviceCallbacks;
-	m_shouldParse = shouldParse;
-} // setAdvertisedDeviceCallbacks
+void BLEScan::setAdvertisedDeviceCallbacks(BLEAdvertisedDeviceCallbacks *pAdvertisedDeviceCallbacks, bool wantDuplicates, bool shouldParse) {
+  m_wantDuplicates = wantDuplicates;
+  m_pAdvertisedDeviceCallbacks = pAdvertisedDeviceCallbacks;
+  m_shouldParse = shouldParse;
+}  // setAdvertisedDeviceCallbacks
+
+#ifdef SOC_BLE_50_SUPPORTED
+
+void BLEScan::setExtendedScanCallback(BLEExtAdvertisingCallbacks *cb) {
+  m_pExtendedScanCb = cb;
+}
+
+/**
+* @brief           This function is used to set the extended scan parameters to be used on the advertising channels.
+*
+*
+* @return            - ESP_OK : success
+*                    - other  : failed
+*
+*/
+esp_err_t BLEScan::setExtScanParams() {
+  esp_ble_ext_scan_params_t ext_scan_params = {
+    .own_addr_type = BLE_ADDR_TYPE_PUBLIC,
+    .filter_policy = BLE_SCAN_FILTER_ALLOW_ALL,
+    .scan_duplicate = BLE_SCAN_DUPLICATE_DISABLE,
+    .cfg_mask = ESP_BLE_GAP_EXT_SCAN_CFG_UNCODE_MASK | ESP_BLE_GAP_EXT_SCAN_CFG_CODE_MASK,
+    .uncoded_cfg = {BLE_SCAN_TYPE_ACTIVE, 40, 40},
+    .coded_cfg = {BLE_SCAN_TYPE_ACTIVE, 40, 40},
+  };
+
+  esp_err_t rc = esp_ble_gap_set_ext_scan_params(&ext_scan_params);
+  if (rc) {
+    log_e("set extend scan params error, error code = %x", rc);
+  }
+  return rc;
+}
+
+/**
+* @brief           This function is used to set the extended scan parameters to be used on the advertising channels.
+*
+* @param[in]       params : scan parameters
+*
+* @return            - ESP_OK : success
+*                    - other  : failed
+*
+*/
+esp_err_t BLEScan::setExtScanParams(esp_ble_ext_scan_params_t *ext_scan_params) {
+  esp_err_t rc = esp_ble_gap_set_ext_scan_params(ext_scan_params);
+  if (rc) {
+    log_e("set extend scan params error, error code = %x", rc);
+  }
+  return rc;
+}
 
+/**
+* @brief           This function is used to enable scanning.
+*
+* @param[in]       duration : Scan duration
+* @param[in]       period  : Time interval from when the Controller started its last Scan Duration until it begins the subsequent Scan Duration.
+*
+* @return            - ESP_OK : success
+*                    - other  : failed
+*
+*/
+esp_err_t BLEScan::startExtScan(uint32_t duration, uint16_t period) {
+  esp_err_t rc = esp_ble_gap_start_ext_scan(duration, period);
+  if (rc) {
+    log_e("extended scan start failed: %d", rc);
+  }
+  return rc;
+}
+
+esp_err_t BLEScan::stopExtScan() {
+  esp_err_t rc;
+  rc = esp_ble_gap_stop_ext_scan();
+
+  return rc;
+}
+
+void BLEScan::setPeriodicScanCallback(BLEPeriodicScanCallbacks *cb) {
+  m_pPeriodicScanCb = cb;
+}
+
+#endif  // SOC_BLE_50_SUPPORTED
 /**
  * @brief Set the interval to scan.
  * @param [in] The interval in msecs.
  */
 void BLEScan::setInterval(uint16_t intervalMSecs) {
-	m_scan_params.scan_interval = intervalMSecs / 0.625;
-} // setInterval
-
+  m_scan_params.scan_interval = intervalMSecs / 0.625;
+}  // setInterval
 
 /**
  * @brief Set the window to actively scan.
  * @param [in] windowMSecs How long to actively scan.
  */
 void BLEScan::setWindow(uint16_t windowMSecs) {
-	m_scan_params.scan_window = windowMSecs / 0.625;
-} // setWindow
-
+  m_scan_params.scan_window = windowMSecs / 0.625;
+}  // setWindow
 
 /**
  * @brief Start scanning.
@@ -203,104 +373,99 @@ void BLEScan::setWindow(uint16_t windowMSecs) {
  * @return True if scan started or false if there was an error.
  */
 bool BLEScan::start(uint32_t duration, void (*scanCompleteCB)(BLEScanResults), bool is_continue) {
-	log_v(">> start(duration=%d)", duration);
+  log_v(">> start(duration=%d)", duration);
 
-	m_semaphoreScanEnd.take(std::string("start"));
-	m_scanCompleteCB = scanCompleteCB;                  // Save the callback to be invoked when the scan completes.
+  m_semaphoreScanEnd.take(String("start"));
+  m_scanCompleteCB = scanCompleteCB;  // Save the callback to be invoked when the scan completes.
 
-	//  if we are connecting to devices that are advertising even after being connected, multiconnecting peripherals
-	//  then we should not clear map or we will connect the same device few times
-	if(!is_continue) {  
-		for(auto _dev : m_scanResults.m_vectorAdvertisedDevices){
-			delete _dev.second;
-		}
-		m_scanResults.m_vectorAdvertisedDevices.clear();
-	}
+  //  if we are connecting to devices that are advertising even after being connected, multiconnecting peripherals
+  //  then we should not clear map or we will connect the same device few times
+  if (!is_continue) {
+    for (auto _dev : m_scanResults.m_vectorAdvertisedDevices) {
+      delete _dev.second;
+    }
+    m_scanResults.m_vectorAdvertisedDevices.clear();
+  }
 
-	esp_err_t errRc = ::esp_ble_gap_set_scan_params(&m_scan_params);
+  esp_err_t errRc = ::esp_ble_gap_set_scan_params(&m_scan_params);
 
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gap_set_scan_params: err: %d, text: %s", errRc, GeneralUtils::errorToString(errRc));
-		m_semaphoreScanEnd.give();
-		return false;
-	}
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gap_set_scan_params: err: %d, text: %s", errRc, GeneralUtils::errorToString(errRc));
+    m_semaphoreScanEnd.give();
+    return false;
+  }
 
-	errRc = ::esp_ble_gap_start_scanning(duration);
+  errRc = ::esp_ble_gap_start_scanning(duration);
 
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gap_start_scanning: err: %d, text: %s", errRc, GeneralUtils::errorToString(errRc));
-		m_semaphoreScanEnd.give();
-		return false;
-	}
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gap_start_scanning: err: %d, text: %s", errRc, GeneralUtils::errorToString(errRc));
+    m_semaphoreScanEnd.give();
+    return false;
+  }
 
-	m_stopped = false;
-
-	log_v("<< start()");
-	return true;
-} // start
+  m_stopped = false;
 
+  log_v("<< start()");
+  return true;
+}  // start
 
 /**
  * @brief Start scanning and block until scanning has been completed.
  * @param [in] duration The duration in seconds for which to scan.
  * @return The BLEScanResults.
  */
-BLEScanResults BLEScan::start(uint32_t duration, bool is_continue) {
-	if(start(duration, nullptr, is_continue)) {
-		m_semaphoreScanEnd.wait("start");   // Wait for the semaphore to release.
-	}
-	return m_scanResults;
-} // start
-
+BLEScanResults *BLEScan::start(uint32_t duration, bool is_continue) {
+  if (start(duration, nullptr, is_continue)) {
+    m_semaphoreScanEnd.wait("start");  // Wait for the semaphore to release.
+  }
+  return &m_scanResults;
+}  // start
 
 /**
  * @brief Stop an in progress scan.
  * @return N/A.
  */
 void BLEScan::stop() {
-	log_v(">> stop()");
+  log_v(">> stop()");
 
-	esp_err_t errRc = ::esp_ble_gap_stop_scanning();
+  esp_err_t errRc = ::esp_ble_gap_stop_scanning();
 
-	m_stopped = true;
-	m_semaphoreScanEnd.give();
+  m_stopped = true;
+  m_semaphoreScanEnd.give();
 
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gap_stop_scanning: err: %d, text: %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gap_stop_scanning: err: %d, text: %s", errRc, GeneralUtils::errorToString(errRc));
+    return;
+  }
 
-	log_v("<< stop()");
-} // stop
+  log_v("<< stop()");
+}  // stop
 
 // delete peer device from cache after disconnecting, it is required in case we are connecting to devices with not public address
 void BLEScan::erase(BLEAddress address) {
-	log_i("erase device: %s", address.toString().c_str());
-	BLEAdvertisedDevice *advertisedDevice = m_scanResults.m_vectorAdvertisedDevices.find(address.toString())->second;
-	m_scanResults.m_vectorAdvertisedDevices.erase(address.toString());
-	delete advertisedDevice;
+  log_i("erase device: %s", address.toString().c_str());
+  BLEAdvertisedDevice *advertisedDevice = m_scanResults.m_vectorAdvertisedDevices.find(address.toString().c_str())->second;
+  m_scanResults.m_vectorAdvertisedDevices.erase(address.toString().c_str());
+  delete advertisedDevice;
 }
 
-
 /**
  * @brief Dump the scan results to the log.
  */
 void BLEScanResults::dump() {
-	log_v(">> Dump scan results:");
-	for (int i=0; i<getCount(); i++) {
-		log_d("- %s", getDevice(i).toString().c_str());
-	}
-} // dump
-
+  log_v(">> Dump scan results:");
+  for (int i = 0; i < getCount(); i++) {
+    log_d("- %s", getDevice(i).toString().c_str());
+  }
+}  // dump
 
 /**
  * @brief Return the count of devices found in the last scan.
  * @return The number of devices found in the last scan.
  */
 int BLEScanResults::getCount() {
-	return m_vectorAdvertisedDevices.size();
-} // getCount
-
+  return m_vectorAdvertisedDevices.size();
+}  // getCount
 
 /**
  * @brief Return the specified device at the given index.
@@ -309,25 +474,28 @@ int BLEScanResults::getCount() {
  * @return The device at the specified index.
  */
 BLEAdvertisedDevice BLEScanResults::getDevice(uint32_t i) {
-	uint32_t x = 0;
-	BLEAdvertisedDevice dev = *m_vectorAdvertisedDevices.begin()->second;
-	for (auto it = m_vectorAdvertisedDevices.begin(); it != m_vectorAdvertisedDevices.end(); it++) {
-		dev = *it->second;
-		if (x==i)	break;
-		x++;
-	}
-	return dev;
+  uint32_t x = 0;
+  BLEAdvertisedDevice dev = *m_vectorAdvertisedDevices.begin()->second;
+  for (auto it = m_vectorAdvertisedDevices.begin(); it != m_vectorAdvertisedDevices.end(); it++) {
+    dev = *it->second;
+    if (x == i) {
+      break;
+    }
+    x++;
+  }
+  return dev;
 }
 
-BLEScanResults BLEScan::getResults() {
-	return m_scanResults;
+BLEScanResults *BLEScan::getResults() {
+  return &m_scanResults;
 }
 
 void BLEScan::clearResults() {
-	for(auto _dev : m_scanResults.m_vectorAdvertisedDevices){
-		delete _dev.second;
-	}
-	m_scanResults.m_vectorAdvertisedDevices.clear();
+  for (auto _dev : m_scanResults.m_vectorAdvertisedDevices) {
+    delete _dev.second;
+  }
+  m_scanResults.m_vectorAdvertisedDevices.clear();
 }
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEScan.h b/libraries/BLE/src/BLEScan.h
index 75cfdd71acc..080e3b803b2 100644
--- a/libraries/BLE/src/BLEScan.h
+++ b/libraries/BLE/src/BLEScan.h
@@ -7,21 +7,36 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLESCAN_H_
 #define COMPONENTS_CPP_UTILS_BLESCAN_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <esp_gap_ble_api.h>
 
 // #include <vector>
 #include <string>
 #include "BLEAdvertisedDevice.h"
 #include "BLEClient.h"
-#include "FreeRTOS.h"
+#include "RTOS.h"
 
 class BLEAdvertisedDevice;
 class BLEAdvertisedDeviceCallbacks;
+class BLEExtAdvertisingCallbacks;
 class BLEClient;
 class BLEScan;
+class BLEPeriodicScanCallbacks;
 
+struct esp_ble_periodic_adv_sync_estab_param_t {
+  uint8_t status;                    /*!< periodic advertising sync status */
+  uint16_t sync_handle;              /*!< periodic advertising sync handle */
+  uint8_t sid;                       /*!< periodic advertising sid */
+  esp_ble_addr_type_t adv_addr_type; /*!< periodic advertising address type */
+  esp_bd_addr_t adv_addr;            /*!< periodic advertising address */
+  esp_ble_gap_phy_t adv_phy;         /*!< periodic advertising phy type */
+  uint16_t period_adv_interval;      /*!< periodic advertising interval */
+  uint8_t adv_clk_accuracy;          /*!< periodic advertising clock accuracy */
+};
 
 /**
  * @brief The result of having performed a scan.
@@ -32,13 +47,13 @@ class BLEScan;
  */
 class BLEScanResults {
 public:
-	void                dump();
-	int                 getCount();
-	BLEAdvertisedDevice getDevice(uint32_t i);
+  void dump();
+  int getCount();
+  BLEAdvertisedDevice getDevice(uint32_t i);
 
 private:
-	friend BLEScan;
-	std::map<std::string, BLEAdvertisedDevice*> m_vectorAdvertisedDevices;
+  friend BLEScan;
+  std::map<std::string, BLEAdvertisedDevice *> m_vectorAdvertisedDevices;
 };
 
 /**
@@ -48,38 +63,59 @@ class BLEScanResults {
  */
 class BLEScan {
 public:
-	void           setActiveScan(bool active);
-	void           setAdvertisedDeviceCallbacks(
-			              BLEAdvertisedDeviceCallbacks* pAdvertisedDeviceCallbacks,
-										bool wantDuplicates = false,
-										bool shouldParse = true);
-	void           setInterval(uint16_t intervalMSecs);
-	void           setWindow(uint16_t windowMSecs);
-	bool           start(uint32_t duration, void (*scanCompleteCB)(BLEScanResults), bool is_continue = false);
-	BLEScanResults start(uint32_t duration, bool is_continue = false);
-	void           stop();
-	void 		   erase(BLEAddress address);
-	BLEScanResults getResults();
-	void			clearResults();
+  void setActiveScan(bool active);
+  void setAdvertisedDeviceCallbacks(BLEAdvertisedDeviceCallbacks *pAdvertisedDeviceCallbacks, bool wantDuplicates = false, bool shouldParse = true);
+  void setInterval(uint16_t intervalMSecs);
+  void setWindow(uint16_t windowMSecs);
+  bool start(uint32_t duration, void (*scanCompleteCB)(BLEScanResults), bool is_continue = false);
+  BLEScanResults *start(uint32_t duration, bool is_continue = false);
+  void stop();
+  void erase(BLEAddress address);
+  BLEScanResults *getResults();
+  void clearResults();
+
+#ifdef SOC_BLE_50_SUPPORTED
+  void setExtendedScanCallback(BLEExtAdvertisingCallbacks *cb);
+  void setPeriodicScanCallback(BLEPeriodicScanCallbacks *cb);
+
+  esp_err_t stopExtScan();
+  esp_err_t setExtScanParams();
+  esp_err_t setExtScanParams(esp_ble_ext_scan_params_t *ext_scan_params);
+  esp_err_t startExtScan(uint32_t duration, uint16_t period);
+
+private:
+  BLEExtAdvertisingCallbacks *m_pExtendedScanCb = nullptr;
+  BLEPeriodicScanCallbacks *m_pPeriodicScanCb = nullptr;
+#endif  // SOC_BLE_50_SUPPORTED
 
 private:
-	BLEScan();   // One doesn't create a new instance instead one asks the BLEDevice for the singleton.
-	friend class BLEDevice;
-	void         handleGAPEvent(
-		esp_gap_ble_cb_event_t  event,
-		esp_ble_gap_cb_param_t* param);
-	void parseAdvertisement(BLEClient* pRemoteDevice, uint8_t *payload);
-
-
-	esp_ble_scan_params_t         m_scan_params;
-	BLEAdvertisedDeviceCallbacks* m_pAdvertisedDeviceCallbacks = nullptr;
-	bool                          m_stopped = true;
-	bool                          m_shouldParse = true;
-	FreeRTOS::Semaphore           m_semaphoreScanEnd = FreeRTOS::Semaphore("ScanEnd");
-	BLEScanResults                m_scanResults;
-	bool                          m_wantDuplicates;
-	void                        (*m_scanCompleteCB)(BLEScanResults scanResults);
-}; // BLEScan
-
-#endif /* CONFIG_BT_ENABLED */
+  BLEScan();  // One doesn't create a new instance instead one asks the BLEDevice for the singleton.
+  friend class BLEDevice;
+  void handleGAPEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param);
+
+  esp_ble_scan_params_t m_scan_params;
+  BLEAdvertisedDeviceCallbacks *m_pAdvertisedDeviceCallbacks = nullptr;
+  bool m_stopped = true;
+  bool m_shouldParse = true;
+  FreeRTOS::Semaphore m_semaphoreScanEnd = FreeRTOS::Semaphore("ScanEnd");
+  BLEScanResults m_scanResults;
+  bool m_wantDuplicates;
+  void (*m_scanCompleteCB)(BLEScanResults scanResults);
+};  // BLEScan
+
+class BLEPeriodicScanCallbacks {
+public:
+  virtual ~BLEPeriodicScanCallbacks() {}
+
+  virtual void onCreateSync(esp_bt_status_t status) {}
+  virtual void onCancelSync(esp_bt_status_t status) {}
+  virtual void onTerminateSync(esp_bt_status_t status) {}
+  virtual void onLostSync(uint16_t sync_handle) {}
+  virtual void onSync(esp_ble_periodic_adv_sync_estab_param_t) {}
+  virtual void onReport(esp_ble_gap_periodic_adv_report_t params) {}
+  virtual void onStop(esp_bt_status_t status) {}
+};
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLESCAN_H_ */
diff --git a/libraries/BLE/src/BLESecurity.cpp b/libraries/BLE/src/BLESecurity.cpp
index f3b2cd3cbd3..34fc3e69e9e 100644
--- a/libraries/BLE/src/BLESecurity.cpp
+++ b/libraries/BLE/src/BLESecurity.cpp
@@ -5,21 +5,22 @@
  *      Author: chegewara
  */
 
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "BLESecurity.h"
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
-BLESecurity::BLESecurity() {
-}
+BLESecurity::BLESecurity() {}
 
-BLESecurity::~BLESecurity() {
-}
+BLESecurity::~BLESecurity() {}
 /*
  * @brief Set requested authentication mode
  */
 void BLESecurity::setAuthenticationMode(esp_ble_auth_req_t auth_req) {
-	m_authReq = auth_req;
-	esp_ble_gap_set_security_param(ESP_BLE_SM_AUTHEN_REQ_MODE, &m_authReq, sizeof(uint8_t));		  // <--- setup requested authentication mode
+  m_authReq = auth_req;
+  esp_ble_gap_set_security_param(ESP_BLE_SM_AUTHEN_REQ_MODE, &m_authReq, sizeof(uint8_t));  // <--- setup requested authentication mode
 }
 
 /**
@@ -27,89 +28,68 @@ void BLESecurity::setAuthenticationMode(esp_ble_auth_req_t auth_req) {
  * 			either by displaying or entering generated 6-digits pin code
  */
 void BLESecurity::setCapability(esp_ble_io_cap_t iocap) {
-	m_iocap = iocap;
-	esp_ble_gap_set_security_param(ESP_BLE_SM_IOCAP_MODE, &iocap, sizeof(uint8_t));
-} // setCapability
-
+  m_iocap = iocap;
+  esp_ble_gap_set_security_param(ESP_BLE_SM_IOCAP_MODE, &iocap, sizeof(uint8_t));
+}  // setCapability
 
 /**
  * @brief Init encryption key by server
  * @param key_size is value between 7 and 16
  */
 void BLESecurity::setInitEncryptionKey(uint8_t init_key) {
-	m_initKey = init_key;
-	esp_ble_gap_set_security_param(ESP_BLE_SM_SET_INIT_KEY, &m_initKey, sizeof(uint8_t));
-} // setInitEncryptionKey
-
+  m_initKey = init_key;
+  esp_ble_gap_set_security_param(ESP_BLE_SM_SET_INIT_KEY, &m_initKey, sizeof(uint8_t));
+}  // setInitEncryptionKey
 
 /**
  * @brief Init encryption key by client
  * @param key_size is value between 7 and 16
  */
 void BLESecurity::setRespEncryptionKey(uint8_t resp_key) {
-	m_respKey = resp_key;
-	esp_ble_gap_set_security_param(ESP_BLE_SM_SET_RSP_KEY, &m_respKey, sizeof(uint8_t));
-} // setRespEncryptionKey
-
+  m_respKey = resp_key;
+  esp_ble_gap_set_security_param(ESP_BLE_SM_SET_RSP_KEY, &m_respKey, sizeof(uint8_t));
+}  // setRespEncryptionKey
 
 /**
  *
  *
  */
 void BLESecurity::setKeySize(uint8_t key_size) {
-	m_keySize = key_size;
-	esp_ble_gap_set_security_param(ESP_BLE_SM_MAX_KEY_SIZE, &m_keySize, sizeof(uint8_t));
-} //setKeySize
+  m_keySize = key_size;
+  esp_ble_gap_set_security_param(ESP_BLE_SM_MAX_KEY_SIZE, &m_keySize, sizeof(uint8_t));
+}  //setKeySize
 
 /**
  * Setup for static PIN connection, call it first and then call setAuthenticationMode eventually to change it
  */
-void BLESecurity::setStaticPIN(uint32_t pin){
-    uint32_t passkey = pin;
-    esp_ble_gap_set_security_param(ESP_BLE_SM_SET_STATIC_PASSKEY, &passkey, sizeof(uint32_t));
-	setCapability(ESP_IO_CAP_OUT);
-	setKeySize();
-	setAuthenticationMode(ESP_LE_AUTH_REQ_SC_ONLY);
-	setInitEncryptionKey(ESP_BLE_ENC_KEY_MASK | ESP_BLE_ID_KEY_MASK);
+void BLESecurity::setStaticPIN(uint32_t pin) {
+  uint32_t passkey = pin;
+  esp_ble_gap_set_security_param(ESP_BLE_SM_SET_STATIC_PASSKEY, &passkey, sizeof(uint32_t));
+  setCapability(ESP_IO_CAP_OUT);
+  setKeySize();
+  setAuthenticationMode(ESP_LE_AUTH_REQ_SC_ONLY);
+  setInitEncryptionKey(ESP_BLE_ENC_KEY_MASK | ESP_BLE_ID_KEY_MASK);
 }
 
 /**
  * @brief Debug function to display what keys are exchanged by peers
  */
-char* BLESecurity::esp_key_type_to_str(esp_ble_key_type_t key_type) {
-	char* key_str = nullptr;
-	switch (key_type) {
-		case ESP_LE_KEY_NONE:
-			key_str = (char*) "ESP_LE_KEY_NONE";
-			break;
-		case ESP_LE_KEY_PENC:
-			key_str = (char*) "ESP_LE_KEY_PENC";
-			break;
-		case ESP_LE_KEY_PID:
-			key_str = (char*) "ESP_LE_KEY_PID";
-			break;
-		case ESP_LE_KEY_PCSRK:
-			key_str = (char*) "ESP_LE_KEY_PCSRK";
-			break;
-		case ESP_LE_KEY_PLK:
-			key_str = (char*) "ESP_LE_KEY_PLK";
-			break;
-		case ESP_LE_KEY_LLK:
-			key_str = (char*) "ESP_LE_KEY_LLK";
-			break;
-		case ESP_LE_KEY_LENC:
-			key_str = (char*) "ESP_LE_KEY_LENC";
-			break;
-		case ESP_LE_KEY_LID:
-			key_str = (char*) "ESP_LE_KEY_LID";
-			break;
-		case ESP_LE_KEY_LCSRK:
-			key_str = (char*) "ESP_LE_KEY_LCSRK";
-			break;
-		default:
-			key_str = (char*) "INVALID BLE KEY TYPE";
-			break;
-	}
-	return key_str;
-} // esp_key_type_to_str
-#endif // CONFIG_BT_ENABLED
+char *BLESecurity::esp_key_type_to_str(esp_ble_key_type_t key_type) {
+  char *key_str = nullptr;
+  switch (key_type) {
+    case ESP_LE_KEY_NONE:  key_str = (char *)"ESP_LE_KEY_NONE"; break;
+    case ESP_LE_KEY_PENC:  key_str = (char *)"ESP_LE_KEY_PENC"; break;
+    case ESP_LE_KEY_PID:   key_str = (char *)"ESP_LE_KEY_PID"; break;
+    case ESP_LE_KEY_PCSRK: key_str = (char *)"ESP_LE_KEY_PCSRK"; break;
+    case ESP_LE_KEY_PLK:   key_str = (char *)"ESP_LE_KEY_PLK"; break;
+    case ESP_LE_KEY_LLK:   key_str = (char *)"ESP_LE_KEY_LLK"; break;
+    case ESP_LE_KEY_LENC:  key_str = (char *)"ESP_LE_KEY_LENC"; break;
+    case ESP_LE_KEY_LID:   key_str = (char *)"ESP_LE_KEY_LID"; break;
+    case ESP_LE_KEY_LCSRK: key_str = (char *)"ESP_LE_KEY_LCSRK"; break;
+    default:               key_str = (char *)"INVALID BLE KEY TYPE"; break;
+  }
+  return key_str;
+}  // esp_key_type_to_str
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLESecurity.h b/libraries/BLE/src/BLESecurity.h
index dc6d6d715b9..2e3a44b42d1 100644
--- a/libraries/BLE/src/BLESecurity.h
+++ b/libraries/BLE/src/BLESecurity.h
@@ -7,67 +7,70 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLESECURITY_H_
 #define COMPONENTS_CPP_UTILS_BLESECURITY_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include <esp_gap_ble_api.h>
 
 class BLESecurity {
 public:
-	BLESecurity();
-	virtual ~BLESecurity();
-	void setAuthenticationMode(esp_ble_auth_req_t auth_req);
-	void setCapability(esp_ble_io_cap_t iocap);
-	void setInitEncryptionKey(uint8_t init_key);
-	void setRespEncryptionKey(uint8_t resp_key);
-	void setKeySize(uint8_t key_size = 16);
-	void setStaticPIN(uint32_t pin);
-	static char* esp_key_type_to_str(esp_ble_key_type_t key_type);
+  BLESecurity();
+  virtual ~BLESecurity();
+  void setAuthenticationMode(esp_ble_auth_req_t auth_req);
+  void setCapability(esp_ble_io_cap_t iocap);
+  void setInitEncryptionKey(uint8_t init_key);
+  void setRespEncryptionKey(uint8_t resp_key);
+  void setKeySize(uint8_t key_size = 16);
+  void setStaticPIN(uint32_t pin);
+  static char *esp_key_type_to_str(esp_ble_key_type_t key_type);
 
 private:
-	esp_ble_auth_req_t m_authReq;
-	esp_ble_io_cap_t m_iocap;
-	uint8_t m_initKey;
-	uint8_t m_respKey;
-	uint8_t m_keySize;
-
-}; // BLESecurity
+  esp_ble_auth_req_t m_authReq;
+  esp_ble_io_cap_t m_iocap;
+  uint8_t m_initKey;
+  uint8_t m_respKey;
+  uint8_t m_keySize;
 
+};  // BLESecurity
 
 /*
  * @brief Callbacks to handle GAP events related to authorization
  */
 class BLESecurityCallbacks {
 public:
-	virtual ~BLESecurityCallbacks() {};
+  virtual ~BLESecurityCallbacks(){};
 
-	/**
+  /**
 	 * @brief Its request from peer device to input authentication pin code displayed on peer device.
 	 * It requires that our device is capable to input 6-digits code by end user
 	 * @return Return 6-digits integer value from input device
 	 */
-	virtual uint32_t onPassKeyRequest() = 0;
+  virtual uint32_t onPassKeyRequest() = 0;
 
-	/**
+  /**
 	 * @brief Provide us 6-digits code to perform authentication.
 	 * It requires that our device is capable to display this code to end user
 	 * @param
 	 */
-	virtual void onPassKeyNotify(uint32_t pass_key) = 0;
+  virtual void onPassKeyNotify(uint32_t pass_key) = 0;
 
-	/**
+  /**
 	 * @brief Here we can make decision if we want to let negotiate authorization with peer device or not
 	 * return Return true if we accept this peer device request
 	 */
 
-	virtual bool onSecurityRequest() = 0 ;
-	/**
+  virtual bool onSecurityRequest() = 0;
+  /**
 	 * Provide us information when authentication process is completed
 	 */
-	virtual void onAuthenticationComplete(esp_ble_auth_cmpl_t) = 0;
+  virtual void onAuthenticationComplete(esp_ble_auth_cmpl_t) = 0;
 
-	virtual bool onConfirmPIN(uint32_t pin) = 0;
-}; // BLESecurityCallbacks
+  virtual bool onConfirmPIN(uint32_t pin) = 0;
+};  // BLESecurityCallbacks
 
-#endif // CONFIG_BT_ENABLED
-#endif // COMPONENTS_CPP_UTILS_BLESECURITY_H_
+#endif  /* CONFIG_BLUEDROID_ENABLED */
+#endif  /* SOC_BLE_SUPPORTED */
+#endif  // COMPONENTS_CPP_UTILS_BLESECURITY_H_
diff --git a/libraries/BLE/src/BLEServer.cpp b/libraries/BLE/src/BLEServer.cpp
index a63278c4756..a338cf61451 100644
--- a/libraries/BLE/src/BLEServer.cpp
+++ b/libraries/BLE/src/BLEServer.cpp
@@ -4,9 +4,11 @@
  *  Created on: Apr 16, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
 
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <esp_bt.h>
 #include <esp_bt_main.h>
 #include "GeneralUtils.h"
@@ -26,19 +28,17 @@
  * the BLEDevice class.
  */
 BLEServer::BLEServer() {
-	m_appId            = ESP_GATT_IF_NONE;
-	m_gatts_if         = ESP_GATT_IF_NONE;
-	m_connectedCount   = 0;
-	m_connId           = ESP_GATT_IF_NONE;
-	m_pServerCallbacks = nullptr;
-} // BLEServer
-
+  m_appId = ESP_GATT_IF_NONE;
+  m_gatts_if = ESP_GATT_IF_NONE;
+  m_connectedCount = 0;
+  m_connId = ESP_GATT_IF_NONE;
+  m_pServerCallbacks = nullptr;
+}  // BLEServer
 
 void BLEServer::createApp(uint16_t appId) {
-	m_appId = appId;
-	registerApp(appId);
-} // createApp
-
+  m_appId = appId;
+  registerApp(appId);
+}  // createApp
 
 /**
  * @brief Create a %BLE Service.
@@ -48,11 +48,10 @@ void BLEServer::createApp(uint16_t appId) {
  * @param [in] uuid The UUID of the new service.
  * @return A reference to the new service object.
  */
-BLEService* BLEServer::createService(const char* uuid) {
-	return createService(BLEUUID(uuid));
+BLEService *BLEServer::createService(const char *uuid) {
+  return createService(BLEUUID(uuid));
 }
 
-
 /**
  * @brief Create a %BLE Service.
  *
@@ -63,35 +62,33 @@ BLEService* BLEServer::createService(const char* uuid) {
  * @param [in] inst_id With multiple services with the same UUID we need to provide inst_id value different for each service.
  * @return A reference to the new service object.
  */
-BLEService* BLEServer::createService(BLEUUID uuid, uint32_t numHandles, uint8_t inst_id) {
-	log_v(">> createService - %s", uuid.toString().c_str());
-	m_semaphoreCreateEvt.take("createService");
+BLEService *BLEServer::createService(BLEUUID uuid, uint32_t numHandles, uint8_t inst_id) {
+  log_v(">> createService - %s", uuid.toString().c_str());
+  m_semaphoreCreateEvt.take("createService");
 
-	// Check that a service with the supplied UUID does not already exist.
-	if (m_serviceMap.getByUUID(uuid) != nullptr) {
-		log_w("<< Attempt to create a new service with uuid %s but a service with that UUID already exists.",
-			uuid.toString().c_str());
-	}
+  // Check that a service with the supplied UUID does not already exist.
+  if (m_serviceMap.getByUUID(uuid) != nullptr) {
+    log_w("<< Attempt to create a new service with uuid %s but a service with that UUID already exists.", uuid.toString().c_str());
+  }
 
-	BLEService* pService = new BLEService(uuid, numHandles);
-	pService->m_instId = inst_id;
-	m_serviceMap.setByUUID(uuid, pService); // Save a reference to this service being on this server.
-	pService->executeCreate(this);          // Perform the API calls to actually create the service.
+  BLEService *pService = new BLEService(uuid, numHandles);
+  pService->m_instId = inst_id;
+  m_serviceMap.setByUUID(uuid, pService);  // Save a reference to this service being on this server.
+  pService->executeCreate(this);           // Perform the API calls to actually create the service.
 
-	m_semaphoreCreateEvt.wait("createService");
-
-	log_v("<< createService");
-	return pService;
-} // createService
+  m_semaphoreCreateEvt.wait("createService");
 
+  log_v("<< createService");
+  return pService;
+}  // createService
 
 /**
  * @brief Get a %BLE Service by its UUID
  * @param [in] uuid The UUID of the new service.
  * @return A reference to the service object.
  */
-BLEService* BLEServer::getServiceByUUID(const char* uuid) {
-	return m_serviceMap.getByUUID(uuid);
+BLEService *BLEServer::getServiceByUUID(const char *uuid) {
+  return m_serviceMap.getByUUID(uuid);
 }
 
 /**
@@ -99,8 +96,8 @@ BLEService* BLEServer::getServiceByUUID(const char* uuid) {
  * @param [in] uuid The UUID of the new service.
  * @return A reference to the service object.
  */
-BLEService* BLEServer::getServiceByUUID(BLEUUID uuid) {
-	return m_serviceMap.getByUUID(uuid);
+BLEService *BLEServer::getServiceByUUID(BLEUUID uuid) {
+  return m_serviceMap.getByUUID(uuid);
 }
 
 /**
@@ -108,29 +105,26 @@ BLEService* BLEServer::getServiceByUUID(BLEUUID uuid) {
  *
  * @return An advertising object.
  */
-BLEAdvertising* BLEServer::getAdvertising() {
-	return BLEDevice::getAdvertising();
+BLEAdvertising *BLEServer::getAdvertising() {
+  return BLEDevice::getAdvertising();
 }
 
 uint16_t BLEServer::getConnId() {
-	return m_connId;
+  return m_connId;
 }
 
-
 /**
  * @brief Return the number of connected clients.
  * @return The number of connected clients.
  */
 uint32_t BLEServer::getConnectedCount() {
-	return m_connectedCount;
-} // getConnectedCount
-
+  return m_connectedCount;
+}  // getConnectedCount
 
 uint16_t BLEServer::getGattsIf() {
-	return m_gatts_if;
+  return m_gatts_if;
 }
 
-
 /**
  * @brief Handle a GATT Server Event.
  *
@@ -139,144 +133,147 @@ uint16_t BLEServer::getGattsIf() {
  * @param [in] param
  *
  */
-void BLEServer::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t* param) {
-	log_v(">> handleGATTServerEvent: %s",
-		BLEUtils::gattServerEventTypeToString(event).c_str());
-
-	switch(event) {
-		// ESP_GATTS_ADD_CHAR_EVT - Indicate that a characteristic was added to the service.
-		// add_char:
-		// - esp_gatt_status_t status
-		// - uint16_t          attr_handle
-		// - uint16_t          service_handle
-		// - esp_bt_uuid_t     char_uuid
-		//
-		case ESP_GATTS_ADD_CHAR_EVT: {
-			break;
-		} // ESP_GATTS_ADD_CHAR_EVT
-
-		case ESP_GATTS_MTU_EVT:
-			updatePeerMTU(param->mtu.conn_id, param->mtu.mtu);
-			break;
-
-		// ESP_GATTS_CONNECT_EVT
-		// connect:
-		// - uint16_t      conn_id
-		// - esp_bd_addr_t remote_bda
-		//
-		case ESP_GATTS_CONNECT_EVT: {
-			m_connId = param->connect.conn_id;
-			addPeerDevice((void*)this, false, m_connId);
-			if (m_pServerCallbacks != nullptr) {
-				m_pServerCallbacks->onConnect(this);
-				m_pServerCallbacks->onConnect(this, param);			
-			}
-			m_connectedCount++;   // Increment the number of connected devices count.	
-			break;
-		} // ESP_GATTS_CONNECT_EVT
-
-
-		// ESP_GATTS_CREATE_EVT
-		// Called when a new service is registered as having been created.
-		//
-		// create:
-		// * esp_gatt_status_t  status
-		// * uint16_t           service_handle
-		// * esp_gatt_srvc_id_t service_id
-		//
-		case ESP_GATTS_CREATE_EVT: {
-			BLEService* pService = m_serviceMap.getByUUID(param->create.service_id.id.uuid, param->create.service_id.id.inst_id);  // <--- very big bug for multi services with the same uuid
-			m_serviceMap.setByHandle(param->create.service_handle, pService);
-			m_semaphoreCreateEvt.give();
-			break;
-		} // ESP_GATTS_CREATE_EVT
-
-
-		// ESP_GATTS_DISCONNECT_EVT
-		//
-		// disconnect
-		// - uint16_t      					conn_id
-		// - esp_bd_addr_t 					remote_bda
-		// - esp_gatt_conn_reason_t         reason
-		//
-		// If we receive a disconnect event then invoke the callback for disconnects (if one is present).
-		// we also want to start advertising again.
-		case ESP_GATTS_DISCONNECT_EVT: {
-			if (m_pServerCallbacks != nullptr) {         // If we have callbacks, call now.
-				m_pServerCallbacks->onDisconnect(this);
-			}
-            if(m_connId == ESP_GATT_IF_NONE) {
-                return;
-            }
-
-            // only decrement if connection is found in map and removed
-            // sometimes this event triggers w/o a valid connection
-			if(removePeerDevice(param->disconnect.conn_id, false)) {
-                m_connectedCount--;                          // Decrement the number of connected devices count.
-            }
-            break;
-		} // ESP_GATTS_DISCONNECT_EVT
-
-
-		// ESP_GATTS_READ_EVT - A request to read the value of a characteristic has arrived.
-		//
-		// read:
-		// - uint16_t      conn_id
-		// - uint32_t      trans_id
-		// - esp_bd_addr_t bda
-		// - uint16_t      handle
-		// - uint16_t      offset
-		// - bool          is_long
-		// - bool          need_rsp
-		//
-		case ESP_GATTS_READ_EVT: {
-			break;
-		} // ESP_GATTS_READ_EVT
-
-
-		// ESP_GATTS_REG_EVT
-		// reg:
-		// - esp_gatt_status_t status
-		// - uint16_t app_id
-		//
-		case ESP_GATTS_REG_EVT: {
-			m_gatts_if = gatts_if;
-			m_semaphoreRegisterAppEvt.give(); // Unlock the mutex waiting for the registration of the app.
-			break;
-		} // ESP_GATTS_REG_EVT
-
-
-		// ESP_GATTS_WRITE_EVT - A request to write the value of a characteristic has arrived.
-		//
-		// write:
-		// - uint16_t      conn_id
-		// - uint16_t      trans_id
-		// - esp_bd_addr_t bda
-		// - uint16_t      handle
-		// - uint16_t      offset
-		// - bool          need_rsp
-		// - bool          is_prep
-		// - uint16_t      len
-		// - uint8_t*      value
-		//
-		case ESP_GATTS_WRITE_EVT: {
-			break;
-		}
-
-		case ESP_GATTS_OPEN_EVT:
-			m_semaphoreOpenEvt.give(param->open.status);
-			break;
-
-		default:
-			break;
-	}
-
-	// Invoke the handler for every Service we have.
-	m_serviceMap.handleGATTServerEvent(event, gatts_if, param);
-
-	log_v("<< handleGATTServerEvent");
-} // handleGATTServerEvent
-
+void BLEServer::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) {
+  log_v(">> handleGATTServerEvent: %s", BLEUtils::gattServerEventTypeToString(event).c_str());
+
+  switch (event) {
+    // ESP_GATTS_ADD_CHAR_EVT - Indicate that a characteristic was added to the service.
+    // add_char:
+    // - esp_gatt_status_t status
+    // - uint16_t          attr_handle
+    // - uint16_t          service_handle
+    // - esp_bt_uuid_t     char_uuid
+    //
+    case ESP_GATTS_ADD_CHAR_EVT:
+    {
+      break;
+    }  // ESP_GATTS_ADD_CHAR_EVT
+
+    case ESP_GATTS_MTU_EVT:
+      updatePeerMTU(param->mtu.conn_id, param->mtu.mtu);
+      if (m_pServerCallbacks != nullptr) {
+        m_pServerCallbacks->onMtuChanged(this, param);
+      }
+      break;
+
+    // ESP_GATTS_CONNECT_EVT
+    // connect:
+    // - uint16_t      conn_id
+    // - esp_bd_addr_t remote_bda
+    //
+    case ESP_GATTS_CONNECT_EVT:
+    {
+      m_connId = param->connect.conn_id;
+      addPeerDevice((void *)this, false, m_connId);
+      if (m_pServerCallbacks != nullptr) {
+        m_pServerCallbacks->onConnect(this);
+        m_pServerCallbacks->onConnect(this, param);
+      }
+      m_connectedCount++;  // Increment the number of connected devices count.
+      break;
+    }  // ESP_GATTS_CONNECT_EVT
+
+    // ESP_GATTS_CREATE_EVT
+    // Called when a new service is registered as having been created.
+    //
+    // create:
+    // * esp_gatt_status_t  status
+    // * uint16_t           service_handle
+    // * esp_gatt_srvc_id_t service_id
+    //
+    case ESP_GATTS_CREATE_EVT:
+    {
+      BLEService *pService = m_serviceMap.getByUUID(
+        param->create.service_id.id.uuid, param->create.service_id.id.inst_id
+      );  // <--- very big bug for multi services with the same uuid
+      m_serviceMap.setByHandle(param->create.service_handle, pService);
+      m_semaphoreCreateEvt.give();
+      break;
+    }  // ESP_GATTS_CREATE_EVT
+
+    // ESP_GATTS_DISCONNECT_EVT
+    //
+    // disconnect
+    // - uint16_t      					conn_id
+    // - esp_bd_addr_t 					remote_bda
+    // - esp_gatt_conn_reason_t         reason
+    //
+    // If we receive a disconnect event then invoke the callback for disconnects (if one is present).
+    // we also want to start advertising again.
+    case ESP_GATTS_DISCONNECT_EVT:
+    {
+      if (m_pServerCallbacks != nullptr) {  // If we have callbacks, call now.
+        m_pServerCallbacks->onDisconnect(this);
+        m_pServerCallbacks->onDisconnect(this, param);
+      }
+      if (m_connId == ESP_GATT_IF_NONE) {
+        return;
+      }
+
+      // only decrement if connection is found in map and removed
+      // sometimes this event triggers w/o a valid connection
+      if (removePeerDevice(param->disconnect.conn_id, false)) {
+        m_connectedCount--;  // Decrement the number of connected devices count.
+      }
+      break;
+    }  // ESP_GATTS_DISCONNECT_EVT
+
+    // ESP_GATTS_READ_EVT - A request to read the value of a characteristic has arrived.
+    //
+    // read:
+    // - uint16_t      conn_id
+    // - uint32_t      trans_id
+    // - esp_bd_addr_t bda
+    // - uint16_t      handle
+    // - uint16_t      offset
+    // - bool          is_long
+    // - bool          need_rsp
+    //
+    case ESP_GATTS_READ_EVT:
+    {
+      break;
+    }  // ESP_GATTS_READ_EVT
+
+    // ESP_GATTS_REG_EVT
+    // reg:
+    // - esp_gatt_status_t status
+    // - uint16_t app_id
+    //
+    case ESP_GATTS_REG_EVT:
+    {
+      m_gatts_if = gatts_if;
+      m_semaphoreRegisterAppEvt.give();  // Unlock the mutex waiting for the registration of the app.
+      break;
+    }  // ESP_GATTS_REG_EVT
+
+    // ESP_GATTS_WRITE_EVT - A request to write the value of a characteristic has arrived.
+    //
+    // write:
+    // - uint16_t      conn_id
+    // - uint16_t      trans_id
+    // - esp_bd_addr_t bda
+    // - uint16_t      handle
+    // - uint16_t      offset
+    // - bool          need_rsp
+    // - bool          is_prep
+    // - uint16_t      len
+    // - uint8_t*      value
+    //
+    case ESP_GATTS_WRITE_EVT:
+    {
+      break;
+    }
+
+    case ESP_GATTS_OPEN_EVT: m_semaphoreOpenEvt.give(param->open.status); break;
+
+    default: break;
+  }
+
+  // Invoke the handler for every Service we have.
+  m_serviceMap.handleGATTServerEvent(event, gatts_if, param);
+
+  log_v("<< handleGATTServerEvent");
+}  // handleGATTServerEvent
 
 /**
  * @brief Register the app.
@@ -284,13 +281,12 @@ void BLEServer::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t
  * @return N/A
  */
 void BLEServer::registerApp(uint16_t m_appId) {
-	log_v(">> registerApp - %d", m_appId);
-	m_semaphoreRegisterAppEvt.take("registerApp"); // Take the mutex, will be released by ESP_GATTS_REG_EVT event.
-	::esp_ble_gatts_app_register(m_appId);
-	m_semaphoreRegisterAppEvt.wait("registerApp");
-	log_v("<< registerApp");
-} // registerApp
-
+  log_v(">> registerApp - %d", m_appId);
+  m_semaphoreRegisterAppEvt.take("registerApp");  // Take the mutex, will be released by ESP_GATTS_REG_EVT event.
+  ::esp_ble_gatts_app_register(m_appId);
+  m_semaphoreRegisterAppEvt.wait("registerApp");
+  log_v("<< registerApp");
+}  // registerApp
 
 /**
  * @brief Set the server callbacks.
@@ -301,17 +297,17 @@ void BLEServer::registerApp(uint16_t m_appId) {
  *
  * @param [in] pCallbacks The callbacks to be invoked.
  */
-void BLEServer::setCallbacks(BLEServerCallbacks* pCallbacks) {
-	m_pServerCallbacks = pCallbacks;
-} // setCallbacks
+void BLEServer::setCallbacks(BLEServerCallbacks *pCallbacks) {
+  m_pServerCallbacks = pCallbacks;
+}  // setCallbacks
 
 /*
  * Remove service
  */
-void BLEServer::removeService(BLEService* service) {
-	service->stop();
-	service->executeDelete();	
-	m_serviceMap.removeService(service);
+void BLEServer::removeService(BLEService *service) {
+  service->stop();
+  service->executeDelete();
+  m_serviceMap.removeService(service);
 }
 
 /**
@@ -321,88 +317,92 @@ void BLEServer::removeService(BLEService* service) {
  * retrieving the advertising object and invoking start upon it.
  */
 void BLEServer::startAdvertising() {
-	log_v(">> startAdvertising");
-	BLEDevice::startAdvertising();
-	log_v("<< startAdvertising");
-} // startAdvertising
+  log_v(">> startAdvertising");
+  BLEDevice::startAdvertising();
+  log_v("<< startAdvertising");
+}  // startAdvertising
 
 /**
  * Allow to connect GATT server to peer device
  * Probably can be used in ANCS for iPhone
  */
 bool BLEServer::connect(BLEAddress address) {
-	esp_bd_addr_t addr;
-	memcpy(&addr, address.getNative(), 6);
-	// Perform the open connection request against the target BLE Server.
-	m_semaphoreOpenEvt.take("connect");
-	esp_err_t errRc = ::esp_ble_gatts_open(
-		getGattsIf(),
-		addr, // address
-		1                              // direct connection
-	);
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gattc_open: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return false;
-	}
-
-	uint32_t rc = m_semaphoreOpenEvt.wait("connect");   // Wait for the connection to complete.
-	log_v("<< connect(), rc=%d", rc==ESP_GATT_OK);
-	return rc == ESP_GATT_OK;
-} // connect
-
-
-
-void BLEServerCallbacks::onConnect(BLEServer* pServer) {
-	log_d("BLEServerCallbacks", ">> onConnect(): Default");
-	log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str());
-	log_d("BLEServerCallbacks", "<< onConnect()");
-} // onConnect
-
-void BLEServerCallbacks::onConnect(BLEServer* pServer, esp_ble_gatts_cb_param_t* param) {
-	log_d("BLEServerCallbacks", ">> onConnect(): Default");
-	log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str());
-	log_d("BLEServerCallbacks", "<< onConnect()");
-} // onConnect
-
-
-void BLEServerCallbacks::onDisconnect(BLEServer* pServer) {
-	log_d("BLEServerCallbacks", ">> onDisconnect(): Default");
-	log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str());
-	log_d("BLEServerCallbacks", "<< onDisconnect()");
-} // onDisconnect
+  esp_bd_addr_t addr;
+  memcpy(&addr, address.getNative(), 6);
+  // Perform the open connection request against the target BLE Server.
+  m_semaphoreOpenEvt.take("connect");
+  esp_err_t errRc = ::esp_ble_gatts_open(
+    getGattsIf(),
+    addr,  // address
+    1      // direct connection
+  );
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gattc_open: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return false;
+  }
+
+  uint32_t rc = m_semaphoreOpenEvt.wait("connect");  // Wait for the connection to complete.
+  log_v("<< connect(), rc=%d", rc == ESP_GATT_OK);
+  return rc == ESP_GATT_OK;
+}  // connect
+
+void BLEServerCallbacks::onConnect(BLEServer *pServer) {
+  log_d("BLEServerCallbacks", ">> onConnect(): Default");
+  log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str());
+  log_d("BLEServerCallbacks", "<< onConnect()");
+}  // onConnect
+
+void BLEServerCallbacks::onConnect(BLEServer *pServer, esp_ble_gatts_cb_param_t *param) {
+  log_d("BLEServerCallbacks", ">> onConnect(): Default");
+  log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str());
+  log_d("BLEServerCallbacks", "<< onConnect()");
+}  // onConnect
+
+void BLEServerCallbacks::onDisconnect(BLEServer *pServer) {
+  log_d("BLEServerCallbacks", ">> onDisconnect(): Default");
+  log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str());
+  log_d("BLEServerCallbacks", "<< onDisconnect()");
+}  // onDisconnect
+
+void BLEServerCallbacks::onDisconnect(BLEServer *pServer, esp_ble_gatts_cb_param_t *param) {
+  log_d("BLEServerCallbacks", ">> onDisconnect(): Default");
+  log_d("BLEServerCallbacks", "Device: %s", BLEDevice::toString().c_str());
+  log_d("BLEServerCallbacks", "<< onDisconnect()");
+}  // onDisconnect
+
+void BLEServerCallbacks::onMtuChanged(BLEServer *pServer, esp_ble_gatts_cb_param_t *param) {
+  log_d("BLEServerCallbacks", ">> onMtuChanged(): Default");
+  log_d("BLEServerCallbacks", "Device: %s MTU: %d", BLEDevice::toString().c_str(), param->mtu.mtu);
+  log_d("BLEServerCallbacks", "<< onMtuChanged()");
+}  // onMtuChanged
 
 /* multi connect support */
 /* TODO do some more tweaks */
 void BLEServer::updatePeerMTU(uint16_t conn_id, uint16_t mtu) {
-	// set mtu in conn_status_t
-	const std::map<uint16_t, conn_status_t>::iterator it = m_connectedServersMap.find(conn_id);
-	if (it != m_connectedServersMap.end()) {
-		it->second.mtu = mtu;
-		std::swap(m_connectedServersMap[conn_id], it->second);
-	}
+  // set mtu in conn_status_t
+  const std::map<uint16_t, conn_status_t>::iterator it = m_connectedServersMap.find(conn_id);
+  if (it != m_connectedServersMap.end()) {
+    it->second.mtu = mtu;
+    std::swap(m_connectedServersMap[conn_id], it->second);
+  }
 }
 
 std::map<uint16_t, conn_status_t> BLEServer::getPeerDevices(bool _client) {
-	return m_connectedServersMap;
+  return m_connectedServersMap;
 }
 
-
 uint16_t BLEServer::getPeerMTU(uint16_t conn_id) {
-	return m_connectedServersMap.find(conn_id)->second.mtu;
+  return m_connectedServersMap.find(conn_id)->second.mtu;
 }
 
-void BLEServer::addPeerDevice(void* peer, bool _client, uint16_t conn_id) {
-	conn_status_t status = {
-		.peer_device = peer,
-		.connected = true,
-		.mtu = 23
-	};
+void BLEServer::addPeerDevice(void *peer, bool _client, uint16_t conn_id) {
+  conn_status_t status = {.peer_device = peer, .connected = true, .mtu = 23};
 
-	m_connectedServersMap.insert(std::pair<uint16_t, conn_status_t>(conn_id, status));	
+  m_connectedServersMap.insert(std::pair<uint16_t, conn_status_t>(conn_id, status));
 }
 
 bool BLEServer::removePeerDevice(uint16_t conn_id, bool _client) {
-	return m_connectedServersMap.erase(conn_id) > 0;
+  return m_connectedServersMap.erase(conn_id) > 0;
 }
 /* multi connect support */
 
@@ -410,17 +410,18 @@ bool BLEServer::removePeerDevice(uint16_t conn_id, bool _client) {
  * Update connection parameters can be called only after connection has been established
  */
 void BLEServer::updateConnParams(esp_bd_addr_t remote_bda, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout) {
-	esp_ble_conn_update_params_t conn_params;
-	memcpy(conn_params.bda, remote_bda, sizeof(esp_bd_addr_t));
-	conn_params.latency = latency;
-	conn_params.max_int = maxInterval;    // max_int = 0x20*1.25ms = 40ms
-	conn_params.min_int = minInterval;    // min_int = 0x10*1.25ms = 20ms
-	conn_params.timeout = timeout;    // timeout = 400*10ms = 4000ms
-	esp_ble_gap_update_conn_params(&conn_params); 
+  esp_ble_conn_update_params_t conn_params;
+  memcpy(conn_params.bda, remote_bda, sizeof(esp_bd_addr_t));
+  conn_params.latency = latency;
+  conn_params.max_int = maxInterval;  // max_int = 0x20*1.25ms = 40ms
+  conn_params.min_int = minInterval;  // min_int = 0x10*1.25ms = 20ms
+  conn_params.timeout = timeout;      // timeout = 400*10ms = 4000ms
+  esp_ble_gap_update_conn_params(&conn_params);
 }
 
 void BLEServer::disconnect(uint16_t connId) {
-	esp_ble_gatts_close(m_gatts_if, connId);
+  esp_ble_gatts_close(m_gatts_if, connId);
 }
 
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEServer.h b/libraries/BLE/src/BLEServer.h
index c97f093eff2..aa10f2210fa 100644
--- a/libraries/BLE/src/BLEServer.h
+++ b/libraries/BLE/src/BLEServer.h
@@ -7,8 +7,11 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLESERVER_H_
 #define COMPONENTS_CPP_UTILS_BLESERVER_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <esp_gatts_api.h>
 
 #include <string>
@@ -20,122 +23,129 @@
 #include "BLECharacteristic.h"
 #include "BLEService.h"
 #include "BLESecurity.h"
-#include "FreeRTOS.h"
+#include "RTOS.h"
 #include "BLEAddress.h"
 
 class BLEServerCallbacks;
-/* TODO possibly refactor this struct */ 
+/* TODO possibly refactor this struct */
 typedef struct {
-	void *peer_device;		// peer device BLEClient or BLEServer - maybe its better to have 2 structures or union here
-	bool connected;			// do we need it?
-	uint16_t mtu;			// every peer device negotiate own mtu
+  void *peer_device;  // peer device BLEClient or BLEServer - maybe its better to have 2 structures or union here
+  bool connected;     // do we need it?
+  uint16_t mtu;       // every peer device negotiate own mtu
 } conn_status_t;
 
-
 /**
  * @brief A data structure that manages the %BLE servers owned by a BLE server.
  */
 class BLEServiceMap {
 public:
-	BLEService* getByHandle(uint16_t handle);
-	BLEService* getByUUID(const char* uuid);	
-	BLEService* getByUUID(BLEUUID uuid, uint8_t inst_id = 0);
-	void        handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t* param);
-	void        setByHandle(uint16_t handle, BLEService* service);
-	void        setByUUID(const char* uuid, BLEService* service);
-	void        setByUUID(BLEUUID uuid, BLEService* service);
-	std::string toString();
-	BLEService* getFirst();
-	BLEService* getNext();
-	void 		removeService(BLEService *service);
-	int 		getRegisteredServiceCount();
+  BLEService *getByHandle(uint16_t handle);
+  BLEService *getByUUID(const char *uuid);
+  BLEService *getByUUID(BLEUUID uuid, uint8_t inst_id = 0);
+  void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
+  void setByHandle(uint16_t handle, BLEService *service);
+  void setByUUID(const char *uuid, BLEService *service);
+  void setByUUID(BLEUUID uuid, BLEService *service);
+  String toString();
+  BLEService *getFirst();
+  BLEService *getNext();
+  void removeService(BLEService *service);
+  int getRegisteredServiceCount();
 
 private:
-	std::map<uint16_t, BLEService*>    m_handleMap;
-	std::map<BLEService*, std::string> m_uuidMap;
-	std::map<BLEService*, std::string>::iterator m_iterator;
+  std::map<uint16_t, BLEService *> m_handleMap;
+  std::map<BLEService *, String> m_uuidMap;
+  std::map<BLEService *, String>::iterator m_iterator;
 };
 
-
 /**
  * @brief The model of a %BLE server.
  */
 class BLEServer {
 public:
-	uint32_t        getConnectedCount();
-	BLEService*     createService(const char* uuid);	
-	BLEService*     createService(BLEUUID uuid, uint32_t numHandles=15, uint8_t inst_id=0);
-	BLEAdvertising* getAdvertising();
-	void            setCallbacks(BLEServerCallbacks* pCallbacks);
-	void            startAdvertising();
-	void 			removeService(BLEService* service);
-	BLEService* 	getServiceByUUID(const char* uuid);
-	BLEService* 	getServiceByUUID(BLEUUID uuid);
-	bool 			connect(BLEAddress address);
-	void 			disconnect(uint16_t connId);
-	uint16_t		m_appId;
-	void			updateConnParams(esp_bd_addr_t remote_bda, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout);
-
-	/* multi connection support */
-	std::map<uint16_t, conn_status_t> getPeerDevices(bool client);
-	void addPeerDevice(void* peer, bool is_client, uint16_t conn_id);
-	bool removePeerDevice(uint16_t conn_id, bool client);
-	BLEServer* getServerByConnId(uint16_t conn_id);
-	void updatePeerMTU(uint16_t connId, uint16_t mtu);
-	uint16_t getPeerMTU(uint16_t conn_id);
-	uint16_t        getConnId();
-
+  uint32_t getConnectedCount();
+  BLEService *createService(const char *uuid);
+  BLEService *createService(BLEUUID uuid, uint32_t numHandles = 15, uint8_t inst_id = 0);
+  BLEAdvertising *getAdvertising();
+  void setCallbacks(BLEServerCallbacks *pCallbacks);
+  void startAdvertising();
+  void removeService(BLEService *service);
+  BLEService *getServiceByUUID(const char *uuid);
+  BLEService *getServiceByUUID(BLEUUID uuid);
+  bool connect(BLEAddress address);
+  void disconnect(uint16_t connId);
+  uint16_t m_appId;
+  void updateConnParams(esp_bd_addr_t remote_bda, uint16_t minInterval, uint16_t maxInterval, uint16_t latency, uint16_t timeout);
+
+  /* multi connection support */
+  std::map<uint16_t, conn_status_t> getPeerDevices(bool client);
+  void addPeerDevice(void *peer, bool is_client, uint16_t conn_id);
+  bool removePeerDevice(uint16_t conn_id, bool client);
+  BLEServer *getServerByConnId(uint16_t conn_id);
+  void updatePeerMTU(uint16_t connId, uint16_t mtu);
+  uint16_t getPeerMTU(uint16_t conn_id);
+  uint16_t getConnId();
 
 private:
-	BLEServer();
-	friend class BLEService;
-	friend class BLECharacteristic;
-	friend class BLEDevice;
-	esp_ble_adv_data_t  m_adv_data;
-	// BLEAdvertising      m_bleAdvertising;
-	uint16_t			m_connId;
-	uint32_t            m_connectedCount;
-	uint16_t            m_gatts_if;
-  	std::map<uint16_t, conn_status_t> m_connectedServersMap;
-
-	FreeRTOS::Semaphore m_semaphoreRegisterAppEvt 	= FreeRTOS::Semaphore("RegisterAppEvt");
-	FreeRTOS::Semaphore m_semaphoreCreateEvt 		= FreeRTOS::Semaphore("CreateEvt");
-	FreeRTOS::Semaphore m_semaphoreOpenEvt   		= FreeRTOS::Semaphore("OpenEvt");
-	BLEServiceMap       m_serviceMap;
-	BLEServerCallbacks* m_pServerCallbacks = nullptr;
-
-	void            createApp(uint16_t appId);
-	uint16_t        getGattsIf();
-	void            handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
-	void            registerApp(uint16_t);
-}; // BLEServer
-
+  BLEServer();
+  friend class BLEService;
+  friend class BLECharacteristic;
+  friend class BLEDevice;
+  esp_ble_adv_data_t m_adv_data;
+  // BLEAdvertising      m_bleAdvertising;
+  uint16_t m_connId;
+  uint32_t m_connectedCount;
+  uint16_t m_gatts_if;
+  std::map<uint16_t, conn_status_t> m_connectedServersMap;
+
+  FreeRTOS::Semaphore m_semaphoreRegisterAppEvt = FreeRTOS::Semaphore("RegisterAppEvt");
+  FreeRTOS::Semaphore m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt");
+  FreeRTOS::Semaphore m_semaphoreOpenEvt = FreeRTOS::Semaphore("OpenEvt");
+  BLEServiceMap m_serviceMap;
+  BLEServerCallbacks *m_pServerCallbacks = nullptr;
+
+  void createApp(uint16_t appId);
+  uint16_t getGattsIf();
+  void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
+  void registerApp(uint16_t);
+};  // BLEServer
 
 /**
  * @brief Callbacks associated with the operation of a %BLE server.
  */
 class BLEServerCallbacks {
 public:
-	virtual ~BLEServerCallbacks() {};
-	/**
+  virtual ~BLEServerCallbacks(){};
+  /**
 	 * @brief Handle a new client connection.
 	 *
 	 * When a new client connects, we are invoked.
 	 *
 	 * @param [in] pServer A reference to the %BLE server that received the client connection.
 	 */
-	virtual void onConnect(BLEServer* pServer);
-	virtual void onConnect(BLEServer* pServer, esp_ble_gatts_cb_param_t *param);
-	/**
+  virtual void onConnect(BLEServer *pServer);
+  virtual void onConnect(BLEServer *pServer, esp_ble_gatts_cb_param_t *param);
+  /**
 	 * @brief Handle an existing client disconnection.
 	 *
 	 * When an existing client disconnects, we are invoked.
 	 *
 	 * @param [in] pServer A reference to the %BLE server that received the existing client disconnection.
 	 */
-	virtual void onDisconnect(BLEServer* pServer);
-}; // BLEServerCallbacks
+  virtual void onDisconnect(BLEServer *pServer);
+  virtual void onDisconnect(BLEServer *pServer, esp_ble_gatts_cb_param_t *param);
 
+  /**
+	 * @brief Handle a new client connection.
+	 *
+	 * When the MTU changes this method is invoked.
+	 *
+	 * @param [in] pServer A reference to the %BLE server that received the client connection.
+	 * @param [in] param A reference to esp_ble_gatts_cb_param_t.
+	 */
+  virtual void onMtuChanged(BLEServer *pServer, esp_ble_gatts_cb_param_t *param);
+};  // BLEServerCallbacks
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLESERVER_H_ */
diff --git a/libraries/BLE/src/BLEService.cpp b/libraries/BLE/src/BLEService.cpp
index 3ea6141c0d4..58c5d4eb9c3 100644
--- a/libraries/BLE/src/BLEService.cpp
+++ b/libraries/BLE/src/BLEService.cpp
@@ -7,8 +7,11 @@
 
 // A service is identified by a UUID.  A service is also the container for one or more characteristics.
 
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <esp_err.h>
 #include <esp_gatts_api.h>
 
@@ -24,15 +27,12 @@
 
 #define NULL_HANDLE (0xffff)
 
-
 /**
  * @brief Construct an instance of the BLEService
  * @param [in] uuid The UUID of the service.
  * @param [in] numHandles The maximum number of handles associated with the service.
  */
-BLEService::BLEService(const char* uuid, uint16_t numHandles) : BLEService(BLEUUID(uuid), numHandles) {
-}
-
+BLEService::BLEService(const char *uuid, uint16_t numHandles) : BLEService(BLEUUID(uuid), numHandles) {}
 
 /**
  * @brief Construct an instance of the BLEService
@@ -40,14 +40,13 @@ BLEService::BLEService(const char* uuid, uint16_t numHandles) : BLEService(BLEUU
  * @param [in] numHandles The maximum number of handles associated with the service.
  */
 BLEService::BLEService(BLEUUID uuid, uint16_t numHandles) {
-	m_uuid      = uuid;
-	m_handle    = NULL_HANDLE;
-	m_pServer   = nullptr;
-	//m_serializeMutex.setName("BLEService");
-	m_lastCreatedCharacteristic = nullptr;
-	m_numHandles = numHandles;
-} // BLEService
-
+  m_uuid = uuid;
+  m_handle = NULL_HANDLE;
+  m_pServer = nullptr;
+  //m_serializeMutex.setName("BLEService");
+  m_lastCreatedCharacteristic = nullptr;
+  m_numHandles = numHandles;
+}  // BLEService
 
 /**
  * @brief Create the service.
@@ -56,26 +55,26 @@ BLEService::BLEService(BLEUUID uuid, uint16_t numHandles) {
  * @return N/A.
  */
 
-void BLEService::executeCreate(BLEServer* pServer) {
-	log_v(">> executeCreate() - Creating service (esp_ble_gatts_create_service) service uuid: %s", getUUID().toString().c_str());
-	m_pServer          = pServer;
-	m_semaphoreCreateEvt.take("executeCreate"); // Take the mutex and release at event ESP_GATTS_CREATE_EVT
-
-	esp_gatt_srvc_id_t srvc_id;
-	srvc_id.is_primary = true;
-	srvc_id.id.inst_id = m_instId;
-	srvc_id.id.uuid    = *m_uuid.getNative();
-	esp_err_t errRc = ::esp_ble_gatts_create_service(getServer()->getGattsIf(), &srvc_id, m_numHandles); // The maximum number of handles associated with the service.
+void BLEService::executeCreate(BLEServer *pServer) {
+  log_v(">> executeCreate() - Creating service (esp_ble_gatts_create_service) service uuid: %s", getUUID().toString().c_str());
+  m_pServer = pServer;
+  m_semaphoreCreateEvt.take("executeCreate");  // Take the mutex and release at event ESP_GATTS_CREATE_EVT
 
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gatts_create_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
+  esp_gatt_srvc_id_t srvc_id;
+  srvc_id.is_primary = true;
+  srvc_id.id.inst_id = m_instId;
+  srvc_id.id.uuid = *m_uuid.getNative();
+  esp_err_t errRc =
+    ::esp_ble_gatts_create_service(getServer()->getGattsIf(), &srvc_id, m_numHandles);  // The maximum number of handles associated with the service.
 
-	m_semaphoreCreateEvt.wait("executeCreate");
-	log_v("<< executeCreate");
-} // executeCreate
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gatts_create_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return;
+  }
 
+  m_semaphoreCreateEvt.wait("executeCreate");
+  log_v("<< executeCreate");
+}  // executeCreate
 
 /**
  * @brief Delete the service.
@@ -84,41 +83,36 @@ void BLEService::executeCreate(BLEServer* pServer) {
  */
 
 void BLEService::executeDelete() {
-	log_v(">> executeDelete()");
-	m_semaphoreDeleteEvt.take("executeDelete"); // Take the mutex and release at event ESP_GATTS_DELETE_EVT
-
-	esp_err_t errRc = ::esp_ble_gatts_delete_service(getHandle());
+  log_v(">> executeDelete()");
+  m_semaphoreDeleteEvt.take("executeDelete");  // Take the mutex and release at event ESP_GATTS_DELETE_EVT
 
-	if (errRc != ESP_OK) {
-		log_e("esp_ble_gatts_delete_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
+  esp_err_t errRc = ::esp_ble_gatts_delete_service(getHandle());
 
-	m_semaphoreDeleteEvt.wait("executeDelete");
-	log_v("<< executeDelete");
-} // executeDelete
+  if (errRc != ESP_OK) {
+    log_e("esp_ble_gatts_delete_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return;
+  }
 
+  m_semaphoreDeleteEvt.wait("executeDelete");
+  log_v("<< executeDelete");
+}  // executeDelete
 
 /**
  * @brief Dump details of this BLE GATT service.
  * @return N/A.
  */
 void BLEService::dump() {
-	log_d("Service: uuid:%s, handle: 0x%.2x",
-		m_uuid.toString().c_str(),
-		m_handle);
-	log_d("Characteristics:\n%s", m_characteristicMap.toString().c_str());
-} // dump
-
+  log_d("Service: uuid:%s, handle: 0x%.2x", m_uuid.toString().c_str(), m_handle);
+  log_d("Characteristics:\n%s", m_characteristicMap.toString().c_str());
+}  // dump
 
 /**
  * @brief Get the UUID of the service.
  * @return the UUID of the service.
  */
 BLEUUID BLEService::getUUID() {
-	return m_uuid;
-} // getUUID
-
+  return m_uuid;
+}  // getUUID
 
 /**
  * @brief Start the service.
@@ -127,116 +121,109 @@ BLEUUID BLEService::getUUID() {
  * @return Start the service.
  */
 void BLEService::start() {
-// We ask the BLE runtime to start the service and then create each of the characteristics.
-// We start the service through its local handle which was returned in the ESP_GATTS_CREATE_EVT event
-// obtained as a result of calling esp_ble_gatts_create_service().
-//
-	log_v(">> start(): Starting service (esp_ble_gatts_start_service): %s", toString().c_str());
-	if (m_handle == NULL_HANDLE) {
-		log_e("<< !!! We attempted to start a service but don't know its handle!");
-		return;
-	}
-
-	BLECharacteristic *pCharacteristic = m_characteristicMap.getFirst();
-
-	while (pCharacteristic != nullptr) {
-		m_lastCreatedCharacteristic = pCharacteristic;
-		pCharacteristic->executeCreate(this);
-
-		pCharacteristic = m_characteristicMap.getNext();
-	}
-	// Start each of the characteristics ... these are found in the m_characteristicMap.
-
-	m_semaphoreStartEvt.take("start");
-	esp_err_t errRc = ::esp_ble_gatts_start_service(m_handle);
-
-	if (errRc != ESP_OK) {
-		log_e("<< esp_ble_gatts_start_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
-	m_semaphoreStartEvt.wait("start");
-
-	log_v("<< start()");
-} // start
-
+  // We ask the BLE runtime to start the service and then create each of the characteristics.
+  // We start the service through its local handle which was returned in the ESP_GATTS_CREATE_EVT event
+  // obtained as a result of calling esp_ble_gatts_create_service().
+  //
+  log_v(">> start(): Starting service (esp_ble_gatts_start_service): %s", toString().c_str());
+  if (m_handle == NULL_HANDLE) {
+    log_e("<< !!! We attempted to start a service but don't know its handle!");
+    return;
+  }
+
+  BLECharacteristic *pCharacteristic = m_characteristicMap.getFirst();
+
+  while (pCharacteristic != nullptr) {
+    m_lastCreatedCharacteristic = pCharacteristic;
+    pCharacteristic->executeCreate(this);
+
+    pCharacteristic = m_characteristicMap.getNext();
+  }
+  // Start each of the characteristics ... these are found in the m_characteristicMap.
+
+  m_semaphoreStartEvt.take("start");
+  esp_err_t errRc = ::esp_ble_gatts_start_service(m_handle);
+
+  if (errRc != ESP_OK) {
+    log_e("<< esp_ble_gatts_start_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return;
+  }
+  m_semaphoreStartEvt.wait("start");
+
+  log_v("<< start()");
+}  // start
 
 /**
  * @brief Stop the service.
  */
 void BLEService::stop() {
-// We ask the BLE runtime to start the service and then create each of the characteristics.
-// We start the service through its local handle which was returned in the ESP_GATTS_CREATE_EVT event
-// obtained as a result of calling esp_ble_gatts_create_service().
-	log_v(">> stop(): Stopping service (esp_ble_gatts_stop_service): %s", toString().c_str());
-	if (m_handle == NULL_HANDLE) {
-		log_e("<< !!! We attempted to stop a service but don't know its handle!");
-		return;
-	}
-
-	m_semaphoreStopEvt.take("stop");
-	esp_err_t errRc = ::esp_ble_gatts_stop_service(m_handle);
-
-	if (errRc != ESP_OK) {
-		log_e("<< esp_ble_gatts_stop_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
-		return;
-	}
-	m_semaphoreStopEvt.wait("stop");
-
-	log_v("<< stop()");
-} // start
-
+  // We ask the BLE runtime to start the service and then create each of the characteristics.
+  // We start the service through its local handle which was returned in the ESP_GATTS_CREATE_EVT event
+  // obtained as a result of calling esp_ble_gatts_create_service().
+  log_v(">> stop(): Stopping service (esp_ble_gatts_stop_service): %s", toString().c_str());
+  if (m_handle == NULL_HANDLE) {
+    log_e("<< !!! We attempted to stop a service but don't know its handle!");
+    return;
+  }
+
+  m_semaphoreStopEvt.take("stop");
+  esp_err_t errRc = ::esp_ble_gatts_stop_service(m_handle);
+
+  if (errRc != ESP_OK) {
+    log_e("<< esp_ble_gatts_stop_service: rc=%d %s", errRc, GeneralUtils::errorToString(errRc));
+    return;
+  }
+  m_semaphoreStopEvt.wait("stop");
+
+  log_v("<< stop()");
+}  // start
 
 /**
  * @brief Set the handle associated with this service.
  * @param [in] handle The handle associated with the service.
  */
 void BLEService::setHandle(uint16_t handle) {
-	log_v(">> setHandle - Handle=0x%.2x, service UUID=%s)", handle, getUUID().toString().c_str());
-	if (m_handle != NULL_HANDLE) {
-		log_e("!!! Handle is already set %.2x", m_handle);
-		return;
-	}
-	m_handle = handle;
-	log_v("<< setHandle");
-} // setHandle
-
+  log_v(">> setHandle - Handle=0x%.2x, service UUID=%s)", handle, getUUID().toString().c_str());
+  if (m_handle != NULL_HANDLE) {
+    log_e("!!! Handle is already set %.2x", m_handle);
+    return;
+  }
+  m_handle = handle;
+  log_v("<< setHandle");
+}  // setHandle
 
 /**
  * @brief Get the handle associated with this service.
  * @return The handle associated with this service.
  */
 uint16_t BLEService::getHandle() {
-	return m_handle;
-} // getHandle
-
+  return m_handle;
+}  // getHandle
 
 /**
  * @brief Add a characteristic to the service.
  * @param [in] pCharacteristic A pointer to the characteristic to be added.
  */
-void BLEService::addCharacteristic(BLECharacteristic* pCharacteristic) {
-	// We maintain a mapping of characteristics owned by this service.  These are managed by the
-	// BLECharacteristicMap class instance found in m_characteristicMap.  We add the characteristic
-	// to the map and then ask the service to add the characteristic at the BLE level (ESP-IDF).
-
-	log_v(">> addCharacteristic()");
-	log_d("Adding characteristic: uuid=%s to service: %s",
-		pCharacteristic->getUUID().toString().c_str(),
-		toString().c_str());
+void BLEService::addCharacteristic(BLECharacteristic *pCharacteristic) {
+  // We maintain a mapping of characteristics owned by this service.  These are managed by the
+  // BLECharacteristicMap class instance found in m_characteristicMap.  We add the characteristic
+  // to the map and then ask the service to add the characteristic at the BLE level (ESP-IDF).
 
-	// Check that we don't add the same characteristic twice.
-	if (m_characteristicMap.getByUUID(pCharacteristic->getUUID()) != nullptr) {
-		log_w("<< Adding a new characteristic with the same UUID as a previous one");
-		//return;
-	}
+  log_v(">> addCharacteristic()");
+  log_d("Adding characteristic: uuid=%s to service: %s", pCharacteristic->getUUID().toString().c_str(), toString().c_str());
 
-	// Remember this characteristic in our map of characteristics.  At this point, we can lookup by UUID
-	// but not by handle.  The handle is allocated to us on the ESP_GATTS_ADD_CHAR_EVT.
-	m_characteristicMap.setByUUID(pCharacteristic, pCharacteristic->getUUID());
+  // Check that we don't add the same characteristic twice.
+  if (m_characteristicMap.getByUUID(pCharacteristic->getUUID()) != nullptr) {
+    log_w("<< Adding a new characteristic with the same UUID as a previous one");
+    //return;
+  }
 
-	log_v("<< addCharacteristic()");
-} // addCharacteristic
+  // Remember this characteristic in our map of characteristics.  At this point, we can lookup by UUID
+  // but not by handle.  The handle is allocated to us on the ESP_GATTS_ADD_CHAR_EVT.
+  m_characteristicMap.setByUUID(pCharacteristic, pCharacteristic->getUUID());
 
+  log_v("<< addCharacteristic()");
+}  // addCharacteristic
 
 /**
  * @brief Create a new BLE Characteristic associated with this service.
@@ -244,10 +231,9 @@ void BLEService::addCharacteristic(BLECharacteristic* pCharacteristic) {
  * @param [in] properties - The properties of the characteristic.
  * @return The new BLE characteristic.
  */
-BLECharacteristic* BLEService::createCharacteristic(const char* uuid, uint32_t properties) {
-	return createCharacteristic(BLEUUID(uuid), properties);
+BLECharacteristic *BLEService::createCharacteristic(const char *uuid, uint32_t properties) {
+  return createCharacteristic(BLEUUID(uuid), properties);
 }
-	
 
 /**
  * @brief Create a new BLE Characteristic associated with this service.
@@ -255,124 +241,120 @@ BLECharacteristic* BLEService::createCharacteristic(const char* uuid, uint32_t p
  * @param [in] properties - The properties of the characteristic.
  * @return The new BLE characteristic.
  */
-BLECharacteristic* BLEService::createCharacteristic(BLEUUID uuid, uint32_t properties) {
-	BLECharacteristic* pCharacteristic = new BLECharacteristic(uuid, properties);
-	addCharacteristic(pCharacteristic);
-	return pCharacteristic;
-} // createCharacteristic
-
+BLECharacteristic *BLEService::createCharacteristic(BLEUUID uuid, uint32_t properties) {
+  BLECharacteristic *pCharacteristic = new BLECharacteristic(uuid, properties);
+  addCharacteristic(pCharacteristic);
+  return pCharacteristic;
+}  // createCharacteristic
 
 /**
  * @brief Handle a GATTS server event.
  */
-void BLEService::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t* param) {
-	switch (event) {
-		// ESP_GATTS_ADD_CHAR_EVT - Indicate that a characteristic was added to the service.
-		// add_char:
-		// - esp_gatt_status_t status
-		// - uint16_t attr_handle
-		// - uint16_t service_handle
-		// - esp_bt_uuid_t char_uuid
-
-		// If we have reached the correct service, then locate the characteristic and remember the handle
-		// for that characteristic.
-		case ESP_GATTS_ADD_CHAR_EVT: {
-			if (m_handle == param->add_char.service_handle) {
-				BLECharacteristic *pCharacteristic = getLastCreatedCharacteristic();
-				if (pCharacteristic == nullptr) {
-					log_e("Expected to find characteristic with UUID: %s, but didnt!",
-							BLEUUID(param->add_char.char_uuid).toString().c_str());
-					dump();
-					break;
-				}
-				pCharacteristic->setHandle(param->add_char.attr_handle);
-				m_characteristicMap.setByHandle(param->add_char.attr_handle, pCharacteristic);
-				break;
-			} // Reached the correct service.
-			break;
-		} // ESP_GATTS_ADD_CHAR_EVT
-
-
-		// ESP_GATTS_START_EVT
-		//
-		// start:
-		// esp_gatt_status_t status
-		// uint16_t service_handle
-		case ESP_GATTS_START_EVT: {
-			if (param->start.service_handle == getHandle()) {
-				m_semaphoreStartEvt.give();
-			}
-			break;
-		} // ESP_GATTS_START_EVT
-
-		// ESP_GATTS_STOP_EVT
-		//
-		// stop:
-		// esp_gatt_status_t status
-		// uint16_t service_handle
-		//
-		case ESP_GATTS_STOP_EVT: {
-			if (param->stop.service_handle == getHandle()) {
-				m_semaphoreStopEvt.give();
-			}
-			break;
-		} // ESP_GATTS_STOP_EVT
-
-
-		// ESP_GATTS_CREATE_EVT
-		// Called when a new service is registered as having been created.
-		//
-		// create:
-		// * esp_gatt_status_t status
-		// * uint16_t service_handle
-		// * esp_gatt_srvc_id_t service_id
-		// * - esp_gatt_id id
-		// *   - esp_bt_uuid uuid
-		// *   - uint8_t inst_id
-		// * - bool is_primary
-		//
-		case ESP_GATTS_CREATE_EVT: {
-			if (getUUID().equals(BLEUUID(param->create.service_id.id.uuid)) && m_instId == param->create.service_id.id.inst_id) {
-				setHandle(param->create.service_handle);
-				m_semaphoreCreateEvt.give();
-			}
-			break;
-		} // ESP_GATTS_CREATE_EVT
-
-
-		// ESP_GATTS_DELETE_EVT
-		// Called when a service is deleted.
-		//
-		// delete:
-		// * esp_gatt_status_t status
-		// * uint16_t service_handle
-		//
-		case ESP_GATTS_DELETE_EVT: {
-			if (param->del.service_handle == getHandle()) {
-				m_semaphoreDeleteEvt.give();
-			}
-			break;
-		} // ESP_GATTS_DELETE_EVT
-
-		default:
-			break;
-	} // Switch
-
-	// Invoke the GATTS handler in each of the associated characteristics.
-	m_characteristicMap.handleGATTServerEvent(event, gatts_if, param);
-} // handleGATTServerEvent
-
-
-BLECharacteristic* BLEService::getCharacteristic(const char* uuid) {
-	return getCharacteristic(BLEUUID(uuid));
+void BLEService::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) {
+  switch (event) {
+    // ESP_GATTS_ADD_CHAR_EVT - Indicate that a characteristic was added to the service.
+    // add_char:
+    // - esp_gatt_status_t status
+    // - uint16_t attr_handle
+    // - uint16_t service_handle
+    // - esp_bt_uuid_t char_uuid
+
+    // If we have reached the correct service, then locate the characteristic and remember the handle
+    // for that characteristic.
+    case ESP_GATTS_ADD_CHAR_EVT:
+    {
+      if (m_handle == param->add_char.service_handle) {
+        BLECharacteristic *pCharacteristic = getLastCreatedCharacteristic();
+        if (pCharacteristic == nullptr) {
+          log_e("Expected to find characteristic with UUID: %s, but didn't!", BLEUUID(param->add_char.char_uuid).toString().c_str());
+          dump();
+          break;
+        }
+        pCharacteristic->setHandle(param->add_char.attr_handle);
+        m_characteristicMap.setByHandle(param->add_char.attr_handle, pCharacteristic);
+        break;
+      }  // Reached the correct service.
+      break;
+    }  // ESP_GATTS_ADD_CHAR_EVT
+
+    // ESP_GATTS_START_EVT
+    //
+    // start:
+    // esp_gatt_status_t status
+    // uint16_t service_handle
+    case ESP_GATTS_START_EVT:
+    {
+      if (param->start.service_handle == getHandle()) {
+        m_semaphoreStartEvt.give();
+      }
+      break;
+    }  // ESP_GATTS_START_EVT
+
+    // ESP_GATTS_STOP_EVT
+    //
+    // stop:
+    // esp_gatt_status_t status
+    // uint16_t service_handle
+    //
+    case ESP_GATTS_STOP_EVT:
+    {
+      if (param->stop.service_handle == getHandle()) {
+        m_semaphoreStopEvt.give();
+      }
+      break;
+    }  // ESP_GATTS_STOP_EVT
+
+    // ESP_GATTS_CREATE_EVT
+    // Called when a new service is registered as having been created.
+    //
+    // create:
+    // * esp_gatt_status_t status
+    // * uint16_t service_handle
+    // * esp_gatt_srvc_id_t service_id
+    // * - esp_gatt_id id
+    // *   - esp_bt_uuid uuid
+    // *   - uint8_t inst_id
+    // * - bool is_primary
+    //
+    case ESP_GATTS_CREATE_EVT:
+    {
+      if (getUUID().equals(BLEUUID(param->create.service_id.id.uuid)) && m_instId == param->create.service_id.id.inst_id) {
+        setHandle(param->create.service_handle);
+        m_semaphoreCreateEvt.give();
+      }
+      break;
+    }  // ESP_GATTS_CREATE_EVT
+
+    // ESP_GATTS_DELETE_EVT
+    // Called when a service is deleted.
+    //
+    // delete:
+    // * esp_gatt_status_t status
+    // * uint16_t service_handle
+    //
+    case ESP_GATTS_DELETE_EVT:
+    {
+      if (param->del.service_handle == getHandle()) {
+        m_semaphoreDeleteEvt.give();
+      }
+      break;
+    }  // ESP_GATTS_DELETE_EVT
+
+    default: break;
+  }  // Switch
+
+  // Invoke the GATTS handler in each of the associated characteristics.
+  m_characteristicMap.handleGATTServerEvent(event, gatts_if, param);
+}  // handleGATTServerEvent
+
+BLECharacteristic *BLEService::getCharacteristic(const char *uuid) {
+  return getCharacteristic(BLEUUID(uuid));
 }
 
-
-BLECharacteristic* BLEService::getCharacteristic(BLEUUID uuid) {
-	return m_characteristicMap.getByUUID(uuid);
+BLECharacteristic *BLEService::getCharacteristic(BLEUUID uuid) {
+  return m_characteristicMap.getByUUID(uuid);
 }
 
-
 /**
  * @brief Return a string representation of this service.
  * A service is defined by:
@@ -380,15 +362,14 @@ BLECharacteristic* BLEService::getCharacteristic(BLEUUID uuid) {
  * * Its handle
  * @return A string representation of this service.
  */
-std::string BLEService::toString() {
-	std::string res = "UUID: " + getUUID().toString();
-	char hex[5];
-	snprintf(hex, sizeof(hex), "%04x", getHandle());
-	res += ", handle: 0x";
-	res += hex;
-	return res;
-} // toString
-
+String BLEService::toString() {
+  String res = "UUID: " + getUUID().toString();
+  char hex[5];
+  snprintf(hex, sizeof(hex), "%04x", getHandle());
+  res += ", handle: 0x";
+  res += hex;
+  return res;
+}  // toString
 
 /**
  * @brief Get the last created characteristic.
@@ -397,17 +378,17 @@ std::string BLEService::toString() {
  * is associated with the last characteristics created and we need that information.
  * @return The last created characteristic.
  */
-BLECharacteristic* BLEService::getLastCreatedCharacteristic() {
-	return m_lastCreatedCharacteristic;
-} // getLastCreatedCharacteristic
-
+BLECharacteristic *BLEService::getLastCreatedCharacteristic() {
+  return m_lastCreatedCharacteristic;
+}  // getLastCreatedCharacteristic
 
 /**
  * @brief Get the BLE server associated with this service.
  * @return The BLEServer associated with this service.
  */
-BLEServer* BLEService::getServer() {
-	return m_pServer;
-} // getServer
+BLEServer *BLEService::getServer() {
+  return m_pServer;
+}  // getServer
 
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEService.h b/libraries/BLE/src/BLEService.h
index b42d57f2afb..61f867b2a02 100644
--- a/libraries/BLE/src/BLEService.h
+++ b/libraries/BLE/src/BLEService.h
@@ -7,15 +7,18 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLESERVICE_H_
 #define COMPONENTS_CPP_UTILS_BLESERVICE_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 #include <esp_gatts_api.h>
 
 #include "BLECharacteristic.h"
 #include "BLEServer.h"
 #include "BLEUUID.h"
-#include "FreeRTOS.h"
+#include "RTOS.h"
 
 class BLEServer;
 
@@ -24,74 +27,73 @@ class BLEServer;
  */
 class BLECharacteristicMap {
 public:
-	void setByUUID(BLECharacteristic* pCharacteristic, const char* uuid);
-	void setByUUID(BLECharacteristic* pCharacteristic, BLEUUID uuid);
-	void setByHandle(uint16_t handle, BLECharacteristic* pCharacteristic);
-	BLECharacteristic* getByUUID(const char* uuid);	
-	BLECharacteristic* getByUUID(BLEUUID uuid);
-	BLECharacteristic* getByHandle(uint16_t handle);
-	BLECharacteristic* getFirst();
-	BLECharacteristic* getNext();
-	std::string toString();
-	void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t* param);
+  void setByUUID(BLECharacteristic *pCharacteristic, const char *uuid);
+  void setByUUID(BLECharacteristic *pCharacteristic, BLEUUID uuid);
+  void setByHandle(uint16_t handle, BLECharacteristic *pCharacteristic);
+  BLECharacteristic *getByUUID(const char *uuid);
+  BLECharacteristic *getByUUID(BLEUUID uuid);
+  BLECharacteristic *getByHandle(uint16_t handle);
+  BLECharacteristic *getFirst();
+  BLECharacteristic *getNext();
+  String toString();
+  void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
 
 private:
-	std::map<BLECharacteristic*, std::string> m_uuidMap;
-	std::map<uint16_t, BLECharacteristic*> m_handleMap;
-	std::map<BLECharacteristic*, std::string>::iterator m_iterator;
+  std::map<BLECharacteristic *, String> m_uuidMap;
+  std::map<uint16_t, BLECharacteristic *> m_handleMap;
+  std::map<BLECharacteristic *, String>::iterator m_iterator;
 };
 
-
 /**
  * @brief The model of a %BLE service.
  *
  */
 class BLEService {
 public:
-	void               addCharacteristic(BLECharacteristic* pCharacteristic);
-	BLECharacteristic* createCharacteristic(const char* uuid, uint32_t properties);
-	BLECharacteristic* createCharacteristic(BLEUUID uuid, uint32_t properties);
-	void               dump();
-	void               executeCreate(BLEServer* pServer);
-	void			   executeDelete();
-	BLECharacteristic* getCharacteristic(const char* uuid);
-	BLECharacteristic* getCharacteristic(BLEUUID uuid);
-	BLEUUID            getUUID();
-	BLEServer*         getServer();
-	void               start();
-	void			   stop();
-	std::string        toString();
-	uint16_t           getHandle();
-	uint8_t			   m_instId = 0;
+  void addCharacteristic(BLECharacteristic *pCharacteristic);
+  BLECharacteristic *createCharacteristic(const char *uuid, uint32_t properties);
+  BLECharacteristic *createCharacteristic(BLEUUID uuid, uint32_t properties);
+  void dump();
+  void executeCreate(BLEServer *pServer);
+  void executeDelete();
+  BLECharacteristic *getCharacteristic(const char *uuid);
+  BLECharacteristic *getCharacteristic(BLEUUID uuid);
+  BLEUUID getUUID();
+  BLEServer *getServer();
+  void start();
+  void stop();
+  String toString();
+  uint16_t getHandle();
+  uint8_t m_instId = 0;
 
 private:
-	BLEService(const char* uuid, uint16_t numHandles);
-	BLEService(BLEUUID uuid, uint16_t numHandles);
-	friend class BLEServer;
-	friend class BLEServiceMap;
-	friend class BLEDescriptor;
-	friend class BLECharacteristic;
-	friend class BLEDevice;
-
-	BLECharacteristicMap m_characteristicMap;
-	uint16_t             m_handle;
-	BLECharacteristic*   m_lastCreatedCharacteristic = nullptr;
-	BLEServer*           m_pServer = nullptr;
-	BLEUUID              m_uuid;
+  BLEService(const char *uuid, uint16_t numHandles);
+  BLEService(BLEUUID uuid, uint16_t numHandles);
+  friend class BLEServer;
+  friend class BLEServiceMap;
+  friend class BLEDescriptor;
+  friend class BLECharacteristic;
+  friend class BLEDevice;
 
-	FreeRTOS::Semaphore  m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt");
-	FreeRTOS::Semaphore  m_semaphoreDeleteEvt = FreeRTOS::Semaphore("DeleteEvt");
-	FreeRTOS::Semaphore  m_semaphoreStartEvt  = FreeRTOS::Semaphore("StartEvt");
-	FreeRTOS::Semaphore  m_semaphoreStopEvt   = FreeRTOS::Semaphore("StopEvt");
+  BLECharacteristicMap m_characteristicMap;
+  uint16_t m_handle;
+  BLECharacteristic *m_lastCreatedCharacteristic = nullptr;
+  BLEServer *m_pServer = nullptr;
+  BLEUUID m_uuid;
 
-	uint16_t             m_numHandles;
+  FreeRTOS::Semaphore m_semaphoreCreateEvt = FreeRTOS::Semaphore("CreateEvt");
+  FreeRTOS::Semaphore m_semaphoreDeleteEvt = FreeRTOS::Semaphore("DeleteEvt");
+  FreeRTOS::Semaphore m_semaphoreStartEvt = FreeRTOS::Semaphore("StartEvt");
+  FreeRTOS::Semaphore m_semaphoreStopEvt = FreeRTOS::Semaphore("StopEvt");
 
-	BLECharacteristic* getLastCreatedCharacteristic();
-	void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t* param);
-	void               setHandle(uint16_t handle);
-	//void               setService(esp_gatt_srvc_id_t srvc_id);
-}; // BLEService
+  uint16_t m_numHandles;
 
+  BLECharacteristic *getLastCreatedCharacteristic();
+  void handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
+  void setHandle(uint16_t handle);
+  //void               setService(esp_gatt_srvc_id_t srvc_id);
+};  // BLEService
 
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLESERVICE_H_ */
diff --git a/libraries/BLE/src/BLEServiceMap.cpp b/libraries/BLE/src/BLEServiceMap.cpp
index a8a1f8e567c..30a9db499f1 100644
--- a/libraries/BLE/src/BLEServiceMap.cpp
+++ b/libraries/BLE/src/BLEServiceMap.cpp
@@ -4,20 +4,22 @@
  *  Created on: Jun 22, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <stdio.h>
 #include <iomanip>
 #include "BLEService.h"
 
-
 /**
  * @brief Return the service by UUID.
  * @param [in] UUID The UUID to look up the service.
  * @return The characteristic.
  */
-BLEService* BLEServiceMap::getByUUID(const char* uuid) {
-	return getByUUID(BLEUUID(uuid));
+BLEService *BLEServiceMap::getByUUID(const char *uuid) {
+  return getByUUID(BLEUUID(uuid));
 }
 
 /**
@@ -25,26 +27,24 @@ BLEService* BLEServiceMap::getByUUID(const char* uuid) {
  * @param [in] UUID The UUID to look up the service.
  * @return The characteristic.
  */
-BLEService* BLEServiceMap::getByUUID(BLEUUID uuid, uint8_t inst_id) {
-	for (auto &myPair : m_uuidMap) {
-		if (myPair.first->getUUID().equals(uuid)) {
-			return myPair.first;
-		}
-	}
-	//return m_uuidMap.at(uuid.toString());
-	return nullptr;
-} // getByUUID
-
+BLEService *BLEServiceMap::getByUUID(BLEUUID uuid, uint8_t inst_id) {
+  for (auto &myPair : m_uuidMap) {
+    if (myPair.first->getUUID().equals(uuid)) {
+      return myPair.first;
+    }
+  }
+  //return m_uuidMap.at(uuid.toString());
+  return nullptr;
+}  // getByUUID
 
 /**
  * @brief Return the service by handle.
  * @param [in] handle The handle to look up the service.
  * @return The service.
  */
-BLEService* BLEServiceMap::getByHandle(uint16_t handle) {
-	return m_handleMap.at(handle);
-} // getByHandle
-
+BLEService *BLEServiceMap::getByHandle(uint16_t handle) {
+  return m_handleMap.at(handle);
+}  // getByHandle
 
 /**
  * @brief Set the service by UUID.
@@ -52,10 +52,9 @@ BLEService* BLEServiceMap::getByHandle(uint16_t handle) {
  * @param [in] characteristic The service to cache.
  * @return N/A.
  */
-void BLEServiceMap::setByUUID(BLEUUID uuid, BLEService* service) {
-	m_uuidMap.insert(std::pair<BLEService*, std::string>(service, uuid.toString()));
-} // setByUUID
-
+void BLEServiceMap::setByUUID(BLEUUID uuid, BLEService *service) {
+  m_uuidMap.insert(std::pair<BLEService *, String>(service, uuid.toString()));
+}  // setByUUID
 
 /**
  * @brief Set the service by handle.
@@ -63,75 +62,76 @@ void BLEServiceMap::setByUUID(BLEUUID uuid, BLEService* service) {
  * @param [in] service The service to cache.
  * @return N/A.
  */
-void BLEServiceMap::setByHandle(uint16_t handle, BLEService* service) {
-	m_handleMap.insert(std::pair<uint16_t, BLEService*>(handle, service));
-} // setByHandle
-
+void BLEServiceMap::setByHandle(uint16_t handle, BLEService *service) {
+  m_handleMap.insert(std::pair<uint16_t, BLEService *>(handle, service));
+}  // setByHandle
 
 /**
  * @brief Return a string representation of the service map.
  * @return A string representation of the service map.
  */
-std::string BLEServiceMap::toString() {
-	std::string res;
-	char hex[5];
-	for (auto &myPair: m_handleMap) {
-		res += "handle: 0x";
-		snprintf(hex, sizeof(hex), "%04x", myPair.first);
-		res += hex;
-		res += ", uuid: " + myPair.second->getUUID().toString() + "\n";
-	}
-	return res;
-} // toString
-
-void BLEServiceMap::handleGATTServerEvent(
-		esp_gatts_cb_event_t      event,
-		esp_gatt_if_t             gatts_if,
-		esp_ble_gatts_cb_param_t* param) {
-	// Invoke the handler for every Service we have.
-	for (auto &myPair : m_uuidMap) {
-		myPair.first->handleGATTServerEvent(event, gatts_if, param);
-	}
+String BLEServiceMap::toString() {
+  String res;
+  char hex[5];
+  for (auto &myPair : m_handleMap) {
+    res += "handle: 0x";
+    snprintf(hex, sizeof(hex), "%04x", myPair.first);
+    res += hex;
+    res += ", uuid: " + myPair.second->getUUID().toString() + "\n";
+  }
+  return res;
+}  // toString
+
+void BLEServiceMap::handleGATTServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param) {
+  // Invoke the handler for every Service we have.
+  for (auto &myPair : m_uuidMap) {
+    myPair.first->handleGATTServerEvent(event, gatts_if, param);
+  }
 }
 
 /**
  * @brief Get the first service in the map.
  * @return The first service in the map.
  */
-BLEService* BLEServiceMap::getFirst() {
-	m_iterator = m_uuidMap.begin();
-	if (m_iterator == m_uuidMap.end()) return nullptr;
-	BLEService* pRet = m_iterator->first;
-	m_iterator++;
-	return pRet;
-} // getFirst
+BLEService *BLEServiceMap::getFirst() {
+  m_iterator = m_uuidMap.begin();
+  if (m_iterator == m_uuidMap.end()) {
+    return nullptr;
+  }
+  BLEService *pRet = m_iterator->first;
+  m_iterator++;
+  return pRet;
+}  // getFirst
 
 /**
  * @brief Get the next service in the map.
  * @return The next service in the map.
  */
-BLEService* BLEServiceMap::getNext() {
-	if (m_iterator == m_uuidMap.end()) return nullptr;
-	BLEService* pRet = m_iterator->first;
-	m_iterator++;
-	return pRet;
-} // getNext
+BLEService *BLEServiceMap::getNext() {
+  if (m_iterator == m_uuidMap.end()) {
+    return nullptr;
+  }
+  BLEService *pRet = m_iterator->first;
+  m_iterator++;
+  return pRet;
+}  // getNext
 
 /**
  * @brief Removes service from maps.
  * @return N/A.
  */
-void BLEServiceMap::removeService(BLEService* service) {
-	m_handleMap.erase(service->getHandle());
-	m_uuidMap.erase(service);
-} // removeService
+void BLEServiceMap::removeService(BLEService *service) {
+  m_handleMap.erase(service->getHandle());
+  m_uuidMap.erase(service);
+}  // removeService
 
 /**
  * @brief Returns the amount of registered services
  * @return amount of registered services
  */
-int BLEServiceMap::getRegisteredServiceCount(){
-	return m_handleMap.size();
+int BLEServiceMap::getRegisteredServiceCount() {
+  return m_handleMap.size();
 }
 
-#endif /* CONFIG_BT_ENABLED */
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEUUID.cpp b/libraries/BLE/src/BLEUUID.cpp
index 1a9473678b2..8074ea82f8f 100644
--- a/libraries/BLE/src/BLEUUID.cpp
+++ b/libraries/BLE/src/BLEUUID.cpp
@@ -4,8 +4,11 @@
  *  Created on: Jun 21, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include <string.h>
 #include <sstream>
 #include <iomanip>
@@ -34,17 +37,16 @@
  * @param [in] source The source of the copy
  * @param [in] size The number of bytes to copy
  */
-static void memrcpy(uint8_t* target, uint8_t* source, uint32_t size) {
-	assert(size > 0);
-	target += (size - 1); // Point target to the last byte of the target data
-	while (size > 0) {
-		*target = *source;
-		target--;
-		source++;
-		size--;
-	}
-} // memrcpy
-
+static void memrcpy(uint8_t *target, uint8_t *source, uint32_t size) {
+  assert(size > 0);
+  target += (size - 1);  // Point target to the last byte of the target data
+  while (size > 0) {
+    *target = *source;
+    target--;
+    source++;
+    size--;
+  }
+}  // memrcpy
 
 /**
  * @brief Create a UUID from a string.
@@ -63,61 +65,78 @@ static void memrcpy(uint8_t* target, uint8_t* source, uint32_t size) {
  *
  * @param [in] value The string to build a UUID from.
  */
-BLEUUID::BLEUUID(std::string value) {
-	m_valueSet = true;
-	if (value.length() == 4) {
-		m_uuid.len         = ESP_UUID_LEN_16;
-		m_uuid.uuid.uuid16 = 0;
-		for(int i=0;i<value.length();){
-			uint8_t MSB = value.c_str()[i];
-			uint8_t LSB = value.c_str()[i+1];
-			
-			if(MSB > '9') MSB -= 7;
-			if(LSB > '9') LSB -= 7;
-			m_uuid.uuid.uuid16 += (((MSB&0x0F) <<4) | (LSB & 0x0F))<<(2-i)*4;
-			i+=2;	
-		}
-	}
-	else if (value.length() == 8) {
-		m_uuid.len         = ESP_UUID_LEN_32;
-		m_uuid.uuid.uuid32 = 0;
-		for(int i=0;i<value.length();){
-			uint8_t MSB = value.c_str()[i];
-			uint8_t LSB = value.c_str()[i+1];
-			
-			if(MSB > '9') MSB -= 7; 
-			if(LSB > '9') LSB -= 7;
-			m_uuid.uuid.uuid32 += (((MSB&0x0F) <<4) | (LSB & 0x0F))<<(6-i)*4;
-			i+=2;
-		}		
-	}
-	else if (value.length() == 16) {  // how we can have 16 byte length string reprezenting 128 bit uuid??? needs to be investigated (lack of time)
-		m_uuid.len = ESP_UUID_LEN_128;
-		memrcpy(m_uuid.uuid.uuid128, (uint8_t*)value.data(), 16);
-	}
-	else if (value.length() == 36) {
-		// If the length of the string is 36 bytes then we will assume it is a long hex string in
-		// UUID format.
-		m_uuid.len = ESP_UUID_LEN_128;
-		int n = 0;
-		for(int i=0;i<value.length();){
-			if(value.c_str()[i] == '-')
-				i++;
-			uint8_t MSB = value.c_str()[i];
-			uint8_t LSB = value.c_str()[i+1];
-			
-			if(MSB > '9') MSB -= 7; 
-			if(LSB > '9') LSB -= 7;
-			m_uuid.uuid.uuid128[15-n++] = ((MSB&0x0F) <<4) | (LSB & 0x0F);
-			i+=2;	
-		}
-	}
-	else {
-		log_e("ERROR: UUID value not 2, 4, 16 or 36 bytes");
-		m_valueSet = false;
-	}
-} //BLEUUID(std::string)
+BLEUUID::BLEUUID(String value) {
+  //Serial.printf("BLEUUID constructor from String=\"%s\"\n", value.c_str());
+  m_valueSet = true;
+  if (value.length() == 4) {
+    m_uuid.len = ESP_UUID_LEN_16;
+    m_uuid.uuid.uuid16 = 0;
+    for (int i = 0; i < value.length();) {
+      uint8_t MSB = value.c_str()[i];
+      uint8_t LSB = value.c_str()[i + 1];
+
+      if (MSB > '9') {
+        MSB -= 7;
+      }
+      if (LSB > '9') {
+        LSB -= 7;
+      }
+      m_uuid.uuid.uuid16 += (((MSB & 0x0F) << 4) | (LSB & 0x0F)) << (2 - i) * 4;
+      i += 2;
+    }
+  } else if (value.length() == 8) {
+    m_uuid.len = ESP_UUID_LEN_32;
+    m_uuid.uuid.uuid32 = 0;
+    for (int i = 0; i < value.length();) {
+      uint8_t MSB = value.c_str()[i];
+      uint8_t LSB = value.c_str()[i + 1];
+
+      if (MSB > '9') {
+        MSB -= 7;
+      }
+      if (LSB > '9') {
+        LSB -= 7;
+      }
+      m_uuid.uuid.uuid32 += (((MSB & 0x0F) << 4) | (LSB & 0x0F)) << (6 - i) * 4;
+      i += 2;
+    }
+  } else if (value.length()
+             == 16) {  // How we can have 16 byte length string representing 128 bit uuid??? needs to be investigated (lack of time) - maybe raw data encoded as String (128b==16B)?
+    m_uuid.len = ESP_UUID_LEN_128;
+    memrcpy(m_uuid.uuid.uuid128, (uint8_t *)value.c_str(), 16);
+  } else if (value.length() == 36) {
+    //log_d("36 characters:");
+    // If the length of the string is 36 bytes then we will assume it is a long hex string in
+    // UUID format.
+    m_uuid.len = ESP_UUID_LEN_128;
+    int n = 0;
+    for (int i = 0; i < value.length();) {
+      if (value.c_str()[i] == '-') {
+        i++;
+      }
+      uint8_t MSB = value.c_str()[i];
+      uint8_t LSB = value.c_str()[i + 1];
+
+      if (MSB > '9') {
+        MSB -= 7;
+      }
+      if (LSB > '9') {
+        LSB -= 7;
+      }
+      m_uuid.uuid.uuid128[15 - n++] = ((MSB & 0x0F) << 4) | (LSB & 0x0F);
+      i += 2;
+    }
+  } else {
+    log_e("ERROR: UUID value not 2, 4, 16 or 36 bytes");
+    m_valueSet = false;
+  }
+}  //BLEUUID(String)
 
+/*
+BLEUUID::BLEUUID(String value) {
+	this.BLEUUID(String(value.c_str(), value.length()));
+} //BLEUUID(String)
+*/
 
 /**
  * @brief Create a UUID from 16 bytes of memory.
@@ -126,20 +145,19 @@ BLEUUID::BLEUUID(std::string value) {
  * @param [in] size The size of the data.
  * @param [in] msbFirst Is the MSB first in pData memory?
  */
-BLEUUID::BLEUUID(uint8_t* pData, size_t size, bool msbFirst) {
-	if (size != 16) {
-		log_e("ERROR: UUID length not 16 bytes");
-		return;
-	}
-	m_uuid.len = ESP_UUID_LEN_128;
-	if (msbFirst) {
-		memrcpy(m_uuid.uuid.uuid128, pData, 16);
-	} else {
-		memcpy(m_uuid.uuid.uuid128, pData, 16);
-	}
-	m_valueSet = true;
-} // BLEUUID
-
+BLEUUID::BLEUUID(uint8_t *pData, size_t size, bool msbFirst) {
+  if (size != 16) {
+    log_e("ERROR: UUID length not 16 bytes");
+    return;
+  }
+  m_uuid.len = ESP_UUID_LEN_128;
+  if (msbFirst) {
+    memrcpy(m_uuid.uuid.uuid128, pData, 16);
+  } else {
+    memcpy(m_uuid.uuid.uuid128, pData, 16);
+  }
+  m_valueSet = true;
+}  // BLEUUID
 
 /**
  * @brief Create a UUID from the 16bit value.
@@ -147,11 +165,10 @@ BLEUUID::BLEUUID(uint8_t* pData, size_t size, bool msbFirst) {
  * @param [in] uuid The 16bit short form UUID.
  */
 BLEUUID::BLEUUID(uint16_t uuid) {
-	m_uuid.len         = ESP_UUID_LEN_16;
-	m_uuid.uuid.uuid16 = uuid;
-	m_valueSet         = true;
-} // BLEUUID
-
+  m_uuid.len = ESP_UUID_LEN_16;
+  m_uuid.uuid.uuid16 = uuid;
+  m_valueSet = true;
+}  // BLEUUID
 
 /**
  * @brief Create a UUID from the 32bit value.
@@ -159,11 +176,10 @@ BLEUUID::BLEUUID(uint16_t uuid) {
  * @param [in] uuid The 32bit short form UUID.
  */
 BLEUUID::BLEUUID(uint32_t uuid) {
-	m_uuid.len         = ESP_UUID_LEN_32;
-	m_uuid.uuid.uuid32 = uuid;
-	m_valueSet         = true;
-} // BLEUUID
-
+  m_uuid.len = ESP_UUID_LEN_32;
+  m_uuid.uuid.uuid32 = uuid;
+  m_valueSet = true;
+}  // BLEUUID
 
 /**
  * @brief Create a UUID from the native UUID.
@@ -171,44 +187,36 @@ BLEUUID::BLEUUID(uint32_t uuid) {
  * @param [in] uuid The native UUID.
  */
 BLEUUID::BLEUUID(esp_bt_uuid_t uuid) {
-	m_uuid     = uuid;
-	m_valueSet = true;
-} // BLEUUID
-
+  m_uuid = uuid;
+  m_valueSet = true;
+}  // BLEUUID
 
 /**
  * @brief Create a UUID from the ESP32 esp_gat_id_t.
  *
  * @param [in] gattId The data to create the UUID from.
  */
-BLEUUID::BLEUUID(esp_gatt_id_t gattId) : BLEUUID(gattId.uuid) {
-} // BLEUUID
-
+BLEUUID::BLEUUID(esp_gatt_id_t gattId) : BLEUUID(gattId.uuid) {}  // BLEUUID
 
 BLEUUID::BLEUUID() {
-	m_valueSet = false;
-} // BLEUUID
-
+  m_valueSet = false;
+}  // BLEUUID
 
 /**
  * @brief Get the number of bits in this uuid.
  * @return The number of bits in the UUID.  One of 16, 32 or 128.
  */
 uint8_t BLEUUID::bitSize() {
-	if (!m_valueSet) return 0;
-	switch (m_uuid.len) {
-		case ESP_UUID_LEN_16:
-			return 16;
-		case ESP_UUID_LEN_32:
-			return 32;
-		case ESP_UUID_LEN_128:
-			return 128;
-		default:
-			log_e("Unknown UUID length: %d", m_uuid.len);
-			return 0;
-	} // End of switch
-} // bitSize
-
+  if (!m_valueSet) {
+    return 0;
+  }
+  switch (m_uuid.len) {
+    case ESP_UUID_LEN_16:  return 16;
+    case ESP_UUID_LEN_32:  return 32;
+    case ESP_UUID_LEN_128: return 128;
+    default:               log_e("Unknown UUID length: %d", m_uuid.len); return 0;
+  }  // End of switch
+}  // bitSize
 
 /**
  * @brief Compare a UUID against this UUID.
@@ -217,24 +225,25 @@ uint8_t BLEUUID::bitSize() {
  * @return True if the UUIDs are equal and false otherwise.
  */
 bool BLEUUID::equals(BLEUUID uuid) {
-	//log_d("Comparing: %s to %s", toString().c_str(), uuid.toString().c_str());
-	if (!m_valueSet || !uuid.m_valueSet) return false;
-
-	if (uuid.m_uuid.len != m_uuid.len) {
-		return uuid.toString() == toString();
-	}
+  //log_d("Comparing: %s to %s", toString().c_str(), uuid.toString().c_str());
+  if (!m_valueSet || !uuid.m_valueSet) {
+    return false;
+  }
 
-	if (uuid.m_uuid.len == ESP_UUID_LEN_16) {
-		return uuid.m_uuid.uuid.uuid16 == m_uuid.uuid.uuid16;
-	}
+  if (uuid.m_uuid.len != m_uuid.len) {
+    return uuid.toString() == toString();
+  }
 
-	if (uuid.m_uuid.len == ESP_UUID_LEN_32) {
-		return uuid.m_uuid.uuid.uuid32 == m_uuid.uuid.uuid32;
-	}
+  if (uuid.m_uuid.len == ESP_UUID_LEN_16) {
+    return uuid.m_uuid.uuid.uuid16 == m_uuid.uuid.uuid16;
+  }
 
-	return memcmp(uuid.m_uuid.uuid.uuid128, m_uuid.uuid.uuid128, 16) == 0;
-} // equals
+  if (uuid.m_uuid.len == ESP_UUID_LEN_32) {
+    return uuid.m_uuid.uuid.uuid32 == m_uuid.uuid.uuid32;
+  }
 
+  return memcmp(uuid.m_uuid.uuid.uuid128, m_uuid.uuid.uuid128, 16) == 0;
+}  // equals
 
 /**
  * Create a BLEUUID from a string of the form:
@@ -245,41 +254,39 @@ bool BLEUUID::equals(BLEUUID uuid) {
  * NNNNNNNN
  * <UUID>
  */
-BLEUUID BLEUUID::fromString(std::string _uuid) {
-	uint8_t start = 0;
-	if (strstr(_uuid.c_str(), "0x") != nullptr) { // If the string starts with 0x, skip those characters.
-		start = 2;
-	}
-	uint8_t len = _uuid.length() - start; // Calculate the length of the string we are going to use.
-
-	if(len == 4) {
-		uint16_t x = strtoul(_uuid.substr(start, len).c_str(), NULL, 16);
-		return BLEUUID(x);
-	} else if (len == 8) {
-		uint32_t x = strtoul(_uuid.substr(start, len).c_str(), NULL, 16);
-		return BLEUUID(x);
-	} else if (len == 36) {
-		return BLEUUID(_uuid);
-	}
-	return BLEUUID();
-} // fromString
-
+BLEUUID BLEUUID::fromString(String _uuid) {
+  uint8_t start = 0;
+  if (strstr(_uuid.c_str(), "0x") != nullptr) {  // If the string starts with 0x, skip those characters.
+    start = 2;
+  }
+  uint8_t len = _uuid.length() - start;  // Calculate the length of the string we are going to use.
+
+  if (len == 4) {
+    uint16_t x = strtoul(_uuid.substring(start, start + len).c_str(), NULL, 16);
+    return BLEUUID(x);
+  } else if (len == 8) {
+    uint32_t x = strtoul(_uuid.substring(start, start + len).c_str(), NULL, 16);
+    return BLEUUID(x);
+  } else if (len == 36) {
+    return BLEUUID(_uuid);
+  }
+  return BLEUUID();
+}  // fromString
 
 /**
  * @brief Get the native UUID value.
  *
  * @return The native UUID value or NULL if not set.
  */
-esp_bt_uuid_t* BLEUUID::getNative() {
-	//log_d(">> getNative()")
-	if (m_valueSet == false) {
-		log_v("<< Return of un-initialized UUID!");
-		return nullptr;
-	}
-	//log_d("<< getNative()");
-	return &m_uuid;
-} // getNative
-
+esp_bt_uuid_t *BLEUUID::getNative() {
+  //log_d(">> getNative()")
+  if (m_valueSet == false) {
+    log_v("<< Return of un-initialized UUID!");
+    return nullptr;
+  }
+  //log_d("<< getNative()");
+  return &m_uuid;
+}  // getNative
 
 /**
  * @brief Convert a UUID to its 128 bit representation.
@@ -288,54 +295,50 @@ esp_bt_uuid_t* BLEUUID::getNative() {
  * will convert 16 or 32 bit representations to the full 128bit.
  */
 BLEUUID BLEUUID::to128() {
-	//log_v(">> toFull() - %s", toString().c_str());
-
-	// If we either don't have a value or are already a 128 bit UUID, nothing further to do.
-	if (!m_valueSet || m_uuid.len == ESP_UUID_LEN_128) {
-		return *this;
-	}
-
-	// If we are 16 bit or 32 bit, then set the 4 bytes of the variable part of the UUID.
-	if (m_uuid.len == ESP_UUID_LEN_16) {
-		uint16_t temp = m_uuid.uuid.uuid16;
-		m_uuid.uuid.uuid128[15] = 0;
-		m_uuid.uuid.uuid128[14] = 0;
-		m_uuid.uuid.uuid128[13] = (temp >> 8) & 0xff;
-		m_uuid.uuid.uuid128[12] = temp & 0xff;
-
-	}
-	else if (m_uuid.len == ESP_UUID_LEN_32) {
-		uint32_t temp = m_uuid.uuid.uuid32;
-		m_uuid.uuid.uuid128[15] = (temp >> 24) & 0xff;
-		m_uuid.uuid.uuid128[14] = (temp >> 16) & 0xff;
-		m_uuid.uuid.uuid128[13] = (temp >> 8) & 0xff;
-		m_uuid.uuid.uuid128[12] = temp & 0xff;
-	}
-
-	// Set the fixed parts of the UUID.
-	m_uuid.uuid.uuid128[11] = 0x00;
-	m_uuid.uuid.uuid128[10] = 0x00;
-
-	m_uuid.uuid.uuid128[9]  = 0x10;
-	m_uuid.uuid.uuid128[8]  = 0x00;
-
-	m_uuid.uuid.uuid128[7]  = 0x80;
-	m_uuid.uuid.uuid128[6]  = 0x00;
-
-	m_uuid.uuid.uuid128[5]  = 0x00;
-	m_uuid.uuid.uuid128[4]  = 0x80;
-	m_uuid.uuid.uuid128[3]  = 0x5f;
-	m_uuid.uuid.uuid128[2]  = 0x9b;
-	m_uuid.uuid.uuid128[1]  = 0x34;
-	m_uuid.uuid.uuid128[0]  = 0xfb;
-
-	m_uuid.len = ESP_UUID_LEN_128;
-	//log_d("<< toFull <-  %s", toString().c_str());
-	return *this;
-} // to128
-
-
-
+  //log_v(">> toFull() - %s", toString().c_str());
+
+  // If we either don't have a value or are already a 128 bit UUID, nothing further to do.
+  if (!m_valueSet || m_uuid.len == ESP_UUID_LEN_128) {
+    return *this;
+  }
+
+  // If we are 16 bit or 32 bit, then set the 4 bytes of the variable part of the UUID.
+  if (m_uuid.len == ESP_UUID_LEN_16) {
+    uint16_t temp = m_uuid.uuid.uuid16;
+    m_uuid.uuid.uuid128[15] = 0;
+    m_uuid.uuid.uuid128[14] = 0;
+    m_uuid.uuid.uuid128[13] = (temp >> 8) & 0xff;
+    m_uuid.uuid.uuid128[12] = temp & 0xff;
+
+  } else if (m_uuid.len == ESP_UUID_LEN_32) {
+    uint32_t temp = m_uuid.uuid.uuid32;
+    m_uuid.uuid.uuid128[15] = (temp >> 24) & 0xff;
+    m_uuid.uuid.uuid128[14] = (temp >> 16) & 0xff;
+    m_uuid.uuid.uuid128[13] = (temp >> 8) & 0xff;
+    m_uuid.uuid.uuid128[12] = temp & 0xff;
+  }
+
+  // Set the fixed parts of the UUID.
+  m_uuid.uuid.uuid128[11] = 0x00;
+  m_uuid.uuid.uuid128[10] = 0x00;
+
+  m_uuid.uuid.uuid128[9] = 0x10;
+  m_uuid.uuid.uuid128[8] = 0x00;
+
+  m_uuid.uuid.uuid128[7] = 0x80;
+  m_uuid.uuid.uuid128[6] = 0x00;
+
+  m_uuid.uuid.uuid128[5] = 0x00;
+  m_uuid.uuid.uuid128[4] = 0x80;
+  m_uuid.uuid.uuid128[3] = 0x5f;
+  m_uuid.uuid.uuid128[2] = 0x9b;
+  m_uuid.uuid.uuid128[1] = 0x34;
+  m_uuid.uuid.uuid128[0] = 0xfb;
+
+  m_uuid.len = ESP_UUID_LEN_128;
+  //log_d("<< toFull <-  %s", toString().c_str());
+  return *this;
+}  // to128
 
 /**
  * @brief Get a string representation of the UUID.
@@ -347,40 +350,40 @@ BLEUUID BLEUUID::to128() {
  *
  * @return A string representation of the UUID.
  */
-std::string BLEUUID::toString() {
-	if (!m_valueSet) return "<NULL>";   // If we have no value, nothing to format.
-	// If the UUIDs are 16 or 32 bit, pad correctly.
-
-	if (m_uuid.len == ESP_UUID_LEN_16) {  // If the UUID is 16bit, pad correctly.
-		char hex[9];
-		snprintf(hex, sizeof(hex), "%08x", m_uuid.uuid.uuid16);
-		return std::string(hex) + "-0000-1000-8000-00805f9b34fb";
-	} // End 16bit UUID
-
-	if (m_uuid.len == ESP_UUID_LEN_32) {  // If the UUID is 32bit, pad correctly.
-		char hex[9];
-		snprintf(hex, sizeof(hex), "%08x", m_uuid.uuid.uuid32);
-		return std::string(hex) + "-0000-1000-8000-00805f9b34fb";
-	} // End 32bit UUID
-
-	// The UUID is not 16bit or 32bit which means that it is 128bit.
-	//
-	// UUID string format:
-	// AABBCCDD-EEFF-GGHH-IIJJ-KKLLMMNNOOPP
-	auto size = 37; // 32 for UUID data, 4 for '-' delimiters and one for a terminator == 37 chars
-	char *hex = (char *)malloc(size);
-	snprintf(hex, size, "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x",
-			m_uuid.uuid.uuid128[15], m_uuid.uuid.uuid128[14],
-			m_uuid.uuid.uuid128[13], m_uuid.uuid.uuid128[12],
-			m_uuid.uuid.uuid128[11], m_uuid.uuid.uuid128[10],
-			m_uuid.uuid.uuid128[9], m_uuid.uuid.uuid128[8],
-			m_uuid.uuid.uuid128[7], m_uuid.uuid.uuid128[6],
-			m_uuid.uuid.uuid128[5], m_uuid.uuid.uuid128[4],
-			m_uuid.uuid.uuid128[3], m_uuid.uuid.uuid128[2],
-			m_uuid.uuid.uuid128[1], m_uuid.uuid.uuid128[0]);
-	std::string res(hex);
-	free(hex);
-	return res;
-} // toString
-
-#endif /* CONFIG_BT_ENABLED */
+String BLEUUID::toString() {
+  if (!m_valueSet) {
+    return "<NULL>";  // If we have no value, nothing to format.
+  }
+  // If the UUIDs are 16 or 32 bit, pad correctly.
+
+  if (m_uuid.len == ESP_UUID_LEN_16) {  // If the UUID is 16bit, pad correctly.
+    char hex[9];
+    snprintf(hex, sizeof(hex), "%08x", m_uuid.uuid.uuid16);
+    return String(hex) + "-0000-1000-8000-00805f9b34fb";
+  }  // End 16bit UUID
+
+  if (m_uuid.len == ESP_UUID_LEN_32) {  // If the UUID is 32bit, pad correctly.
+    char hex[9];
+    snprintf(hex, sizeof(hex), "%08lx", m_uuid.uuid.uuid32);
+    return String(hex) + "-0000-1000-8000-00805f9b34fb";
+  }  // End 32bit UUID
+
+  // The UUID is not 16bit or 32bit which means that it is 128bit.
+  //
+  // UUID string format:
+  // AABBCCDD-EEFF-GGHH-IIJJ-KKLLMMNNOOPP
+  auto size = 37;  // 32 for UUID data, 4 for '-' delimiters and one for a terminator == 37 chars
+  char *hex = (char *)malloc(size);
+  snprintf(
+    hex, size, "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x", m_uuid.uuid.uuid128[15], m_uuid.uuid.uuid128[14],
+    m_uuid.uuid.uuid128[13], m_uuid.uuid.uuid128[12], m_uuid.uuid.uuid128[11], m_uuid.uuid.uuid128[10], m_uuid.uuid.uuid128[9], m_uuid.uuid.uuid128[8],
+    m_uuid.uuid.uuid128[7], m_uuid.uuid.uuid128[6], m_uuid.uuid.uuid128[5], m_uuid.uuid.uuid128[4], m_uuid.uuid.uuid128[3], m_uuid.uuid.uuid128[2],
+    m_uuid.uuid.uuid128[1], m_uuid.uuid.uuid128[0]
+  );
+  String res(hex);
+  free(hex);
+  return res;
+}  // toString
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEUUID.h b/libraries/BLE/src/BLEUUID.h
index 700739bec81..1be013942e3 100644
--- a/libraries/BLE/src/BLEUUID.h
+++ b/libraries/BLE/src/BLEUUID.h
@@ -7,33 +7,38 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEUUID_H_
 #define COMPONENTS_CPP_UTILS_BLEUUID_H_
+#include "soc/soc_caps.h"
+#include "WString.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if CONFIG_BLUEDROID_ENABLED
 #include <esp_gatt_defs.h>
-#include <string>
 
 /**
  * @brief A model of a %BLE UUID.
  */
 class BLEUUID {
 public:
-	BLEUUID(std::string uuid);
-	BLEUUID(uint16_t uuid);
-	BLEUUID(uint32_t uuid);
-	BLEUUID(esp_bt_uuid_t uuid);
-	BLEUUID(uint8_t* pData, size_t size, bool msbFirst);
-	BLEUUID(esp_gatt_id_t gattId);
-	BLEUUID();
-	uint8_t        bitSize();   // Get the number of bits in this uuid.
-	bool           equals(BLEUUID uuid);
-	esp_bt_uuid_t* getNative();
-	BLEUUID        to128();
-	std::string    toString();
-	static BLEUUID fromString(std::string uuid);  // Create a BLEUUID from a string
+  BLEUUID(String uuid);
+  BLEUUID(uint16_t uuid);
+  BLEUUID(uint32_t uuid);
+  BLEUUID(esp_bt_uuid_t uuid);
+  BLEUUID(uint8_t *pData, size_t size, bool msbFirst);
+  BLEUUID(esp_gatt_id_t gattId);
+  BLEUUID();
+  uint8_t bitSize();  // Get the number of bits in this uuid.
+  bool equals(BLEUUID uuid);
+  esp_bt_uuid_t *getNative();
+  BLEUUID to128();
+  String toString();
+  static BLEUUID fromString(String uuid);  // Create a BLEUUID from a string
 
 private:
-	esp_bt_uuid_t m_uuid;       		// The underlying UUID structure that this class wraps.
-	bool          m_valueSet = false;   // Is there a value set for this instance.
-}; // BLEUUID
-#endif /* CONFIG_BT_ENABLED */
+  esp_bt_uuid_t m_uuid;     // The underlying UUID structure that this class wraps.
+  bool m_valueSet = false;  // Is there a value set for this instance.
+};  // BLEUUID
+
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEUUID_H_ */
diff --git a/libraries/BLE/src/BLEUtils.cpp b/libraries/BLE/src/BLEUtils.cpp
index b9cf591f426..05e1e32deed 100644
--- a/libraries/BLE/src/BLEUtils.cpp
+++ b/libraries/BLE/src/BLEUtils.cpp
@@ -4,8 +4,11 @@
  *  Created on: Mar 25, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include "BLEAddress.h"
 #include "BLEClient.h"
 #include "BLEUtils.h"
@@ -14,671 +17,656 @@
 
 #include <freertos/FreeRTOS.h>
 #include <freertos/event_groups.h>
-#include <esp_bt.h>              // ESP32 BLE
-#include <esp_bt_main.h>     // ESP32 BLE
-#include <esp_gap_ble_api.h> // ESP32 BLE
-#include <esp_gattc_api.h>   // ESP32 BLE
-#include <esp_err.h>         // ESP32 ESP-IDF
-#include <map>               // Part of C++ STL
+#include <esp_bt.h>           // ESP32 BLE
+#include <esp_bt_main.h>      // ESP32 BLE
+#include <esp_gap_ble_api.h>  // ESP32 BLE
+#include <esp_gattc_api.h>    // ESP32 BLE
+#include <esp_err.h>          // ESP32 ESP-IDF
+#include <map>                // Part of C++ STL
 #include <sstream>
 #include <iomanip>
 
 #include "esp32-hal-log.h"
 
-/*
-static std::map<std::string, BLEClient*> g_addressMap;
-static std::map<uint16_t, BLEClient*> g_connIdMap;
-*/
-
 typedef struct {
-	uint32_t    assignedNumber;
-	const char* name;
+  uint32_t assignedNumber;
+  const char *name;
 } member_t;
 
 static const member_t members_ids[] = {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-	{0xFE08, "Microsoft"},
-	{0xFE09, "Pillsy, Inc."},
-	{0xFE0A, "ruwido austria gmbh"},
-	{0xFE0B, "ruwido austria gmbh"},
-	{0xFE0C, "Procter & Gamble"},
-	{0xFE0D, "Procter & Gamble"},
-	{0xFE0E, "Setec Pty Ltd"},
-	{0xFE0F, "Philips Lighting B.V."},
-	{0xFE10, "Lapis Semiconductor Co., Ltd."},
-	{0xFE11, "GMC-I Messtechnik GmbH"},
-	{0xFE12, "M-Way Solutions GmbH"},
-	{0xFE13, "Apple Inc."},
-	{0xFE14, "Flextronics International USA Inc."},
-	{0xFE15, "Amazon Fulfillment Services, Inc."},
-	{0xFE16, "Footmarks, Inc."},
-	{0xFE17, "Telit Wireless Solutions GmbH"},
-	{0xFE18, "Runtime, Inc."},
-	{0xFE19, "Google Inc."},
-	{0xFE1A, "Tyto Life LLC"},
-	{0xFE1B, "Tyto Life LLC"},
-	{0xFE1C, "NetMedia, Inc."},
-	{0xFE1D, "Illuminati Instrument Corporation"},
-	{0xFE1E, "Smart Innovations Co., Ltd"},
-	{0xFE1F, "Garmin International, Inc."},
-	{0xFE20, "Emerson"},
-	{0xFE21, "Bose Corporation"},
-	{0xFE22, "Zoll Medical Corporation"},
-	{0xFE23, "Zoll Medical Corporation"},
-	{0xFE24, "August Home Inc"},
-	{0xFE25, "Apple, Inc. "},
-	{0xFE26, "Google Inc."},
-	{0xFE27, "Google Inc."},
-	{0xFE28, "Ayla Networks"},
-	{0xFE29, "Gibson Innovations"},
-	{0xFE2A, "DaisyWorks, Inc."},
-	{0xFE2B, "ITT Industries"},
-	{0xFE2C, "Google Inc."},
-	{0xFE2D, "SMART INNOVATION Co.,Ltd"},
-	{0xFE2E, "ERi,Inc."},
-	{0xFE2F, "CRESCO Wireless, Inc"},
-	{0xFE30, "Volkswagen AG"},
-	{0xFE31, "Volkswagen AG"},
-	{0xFE32, "Pro-Mark, Inc."},
-	{0xFE33, "CHIPOLO d.o.o."},
-	{0xFE34, "SmallLoop LLC"},
-	{0xFE35, "HUAWEI Technologies Co., Ltd"},
-	{0xFE36, "HUAWEI Technologies Co., Ltd"},
-	{0xFE37, "Spaceek LTD"},
-	{0xFE38, "Spaceek LTD"},
-	{0xFE39, "TTS Tooltechnic Systems AG & Co. KG"},
-	{0xFE3A, "TTS Tooltechnic Systems AG & Co. KG"},
-	{0xFE3B, "Dolby Laboratories"},
-	{0xFE3C, "Alibaba"},
-	{0xFE3D, "BD Medical"},
-	{0xFE3E, "BD Medical"},
-	{0xFE3F, "Friday Labs Limited"},
-	{0xFE40, "Inugo Systems Limited"},
-	{0xFE41, "Inugo Systems Limited"},
-	{0xFE42, "Nets A/S "},
-	{0xFE43, "Andreas Stihl AG & Co. KG"},
-	{0xFE44, "SK Telecom "},
-	{0xFE45, "Snapchat Inc"},
-	{0xFE46, "B&O Play A/S "},
-	{0xFE47, "General Motors"},
-	{0xFE48, "General Motors"},
-	{0xFE49, "SenionLab AB"},
-	{0xFE4A, "OMRON HEALTHCARE Co., Ltd."},
-	{0xFE4B, "Philips Lighting B.V."},
-	{0xFE4C, "Volkswagen AG"},
-	{0xFE4D, "Casambi Technologies Oy"},
-	{0xFE4E, "NTT docomo"},
-	{0xFE4F, "Molekule, Inc."},
-	{0xFE50, "Google Inc."},
-	{0xFE51, "SRAM"},
-	{0xFE52, "SetPoint Medical"},
-	{0xFE53, "3M"},
-	{0xFE54, "Motiv, Inc."},
-	{0xFE55, "Google Inc."},
-	{0xFE56, "Google Inc."},
-	{0xFE57, "Dotted Labs"},
-	{0xFE58, "Nordic Semiconductor ASA"},
-	{0xFE59, "Nordic Semiconductor ASA"},
-	{0xFE5A, "Chronologics Corporation"},
-	{0xFE5B, "GT-tronics HK Ltd"},
-	{0xFE5C, "million hunters GmbH"},
-	{0xFE5D, "Grundfos A/S"},
-	{0xFE5E, "Plastc Corporation"},
-	{0xFE5F, "Eyefi, Inc."},
-	{0xFE60, "Lierda Science & Technology Group Co., Ltd."},
-	{0xFE61, "Logitech International SA"},
-	{0xFE62, "Indagem Tech LLC"},
-	{0xFE63, "Connected Yard, Inc."},
-	{0xFE64, "Siemens AG"},
-	{0xFE65, "CHIPOLO d.o.o."},
-	{0xFE66, "Intel Corporation"},
-	{0xFE67, "Lab Sensor Solutions"},
-	{0xFE68, "Qualcomm Life Inc"},
-	{0xFE69, "Qualcomm Life Inc"},
-	{0xFE6A, "Kontakt Micro-Location Sp. z o.o."},
-	{0xFE6B, "TASER International, Inc."},
-	{0xFE6C, "TASER International, Inc."},
-	{0xFE6D, "The University of Tokyo"},
-	{0xFE6E, "The University of Tokyo"},
-	{0xFE6F, "LINE Corporation"},
-	{0xFE70, "Beijing Jingdong Century Trading Co., Ltd."},
-	{0xFE71, "Plume Design Inc"},
-	{0xFE72, "St. Jude Medical, Inc."},
-	{0xFE73, "St. Jude Medical, Inc."},
-	{0xFE74, "unwire"},
-	{0xFE75, "TangoMe"},
-	{0xFE76, "TangoMe"},
-	{0xFE77, "Hewlett-Packard Company"},
-	{0xFE78, "Hewlett-Packard Company"},
-	{0xFE79, "Zebra Technologies"},
-	{0xFE7A, "Bragi GmbH"},
-	{0xFE7B, "Orion Labs, Inc."},
-	{0xFE7C, "Telit Wireless Solutions (Formerly Stollmann E+V GmbH)"},
-	{0xFE7D, "Aterica Health Inc."},
-	{0xFE7E, "Awear Solutions Ltd"},
-	{0xFE7F, "Doppler Lab"},
-	{0xFE80, "Doppler Lab"},
-	{0xFE81, "Medtronic Inc."},
-	{0xFE82, "Medtronic Inc."},
-	{0xFE83, "Blue Bite"},
-	{0xFE84, "RF Digital Corp"},
-	{0xFE85, "RF Digital Corp"},
-	{0xFE86, "HUAWEI Technologies Co., Ltd. ( )"},
-	{0xFE87, "Qingdao Yeelink Information Technology Co., Ltd. ( )"},
-	{0xFE88, "SALTO SYSTEMS S.L."},
-	{0xFE89, "B&O Play A/S"},
-	{0xFE8A, "Apple, Inc."},
-	{0xFE8B, "Apple, Inc."},
-	{0xFE8C, "TRON Forum"},
-	{0xFE8D, "Interaxon Inc."},
-	{0xFE8E, "ARM Ltd"},
-	{0xFE8F, "CSR"},
-	{0xFE90, "JUMA"},
-	{0xFE91, "Shanghai Imilab Technology Co.,Ltd"},
-	{0xFE92, "Jarden Safety & Security"},
-	{0xFE93, "OttoQ Inc."},
-	{0xFE94, "OttoQ Inc."},
-	{0xFE95, "Xiaomi Inc."},
-	{0xFE96, "Tesla Motor Inc."},
-	{0xFE97, "Tesla Motor Inc."},
-	{0xFE98, "Currant, Inc."},
-	{0xFE99, "Currant, Inc."},
-	{0xFE9A, "Estimote"},
-	{0xFE9B, "Samsara Networks, Inc"},
-	{0xFE9C, "GSI Laboratories, Inc."},
-	{0xFE9D, "Mobiquity Networks Inc"},
-	{0xFE9E, "Dialog Semiconductor B.V."},
-	{0xFE9F, "Google Inc."},
-	{0xFEA0, "Google Inc."},
-	{0xFEA1, "Intrepid Control Systems, Inc."},
-	{0xFEA2, "Intrepid Control Systems, Inc."},
-	{0xFEA3, "ITT Industries"},
-	{0xFEA4, "Paxton Access Ltd"},
-	{0xFEA5, "GoPro, Inc."},
-	{0xFEA6, "GoPro, Inc."},
-	{0xFEA7, "UTC Fire and Security"},
-	{0xFEA8, "Savant Systems LLC"},
-	{0xFEA9, "Savant Systems LLC"},
-	{0xFEAA, "Google Inc."},
-	{0xFEAB, "Nokia Corporation"},
-	{0xFEAC, "Nokia Corporation"},
-	{0xFEAD, "Nokia Corporation"},
-	{0xFEAE, "Nokia Corporation"},
-	{0xFEAF, "Nest Labs Inc."},
-	{0xFEB0, "Nest Labs Inc."},
-	{0xFEB1, "Electronics Tomorrow Limited"},
-	{0xFEB2, "Microsoft Corporation"},
-	{0xFEB3, "Taobao"},
-	{0xFEB4, "WiSilica Inc."},
-	{0xFEB5, "WiSilica Inc."},
-	{0xFEB6, "Vencer Co, Ltd"},
-	{0xFEB7, "Facebook, Inc."},
-	{0xFEB8, "Facebook, Inc."},
-	{0xFEB9, "LG Electronics"},
-	{0xFEBA, "Tencent Holdings Limited"},
-	{0xFEBB, "adafruit industries"},
-	{0xFEBC, "Dexcom, Inc. "},
-	{0xFEBD, "Clover Network, Inc."},
-	{0xFEBE, "Bose Corporation"},
-	{0xFEBF, "Nod, Inc."},
-	{0xFEC0, "KDDI Corporation"},
-	{0xFEC1, "KDDI Corporation"},
-	{0xFEC2, "Blue Spark Technologies, Inc."},
-	{0xFEC3, "360fly, Inc."},
-	{0xFEC4, "PLUS Location Systems"},
-	{0xFEC5, "Realtek Semiconductor Corp."},
-	{0xFEC6, "Kocomojo, LLC"},
-	{0xFEC7, "Apple, Inc."},
-	{0xFEC8, "Apple, Inc."},
-	{0xFEC9, "Apple, Inc."},
-	{0xFECA, "Apple, Inc."},
-	{0xFECB, "Apple, Inc."},
-	{0xFECC, "Apple, Inc."},
-	{0xFECD, "Apple, Inc."},
-	{0xFECE, "Apple, Inc."},
-	{0xFECF, "Apple, Inc."},
-	{0xFED0, "Apple, Inc."},
-	{0xFED1, "Apple, Inc."},
-	{0xFED2, "Apple, Inc."},
-	{0xFED3, "Apple, Inc."},
-	{0xFED4, "Apple, Inc."},
-	{0xFED5, "Plantronics Inc."},
-	{0xFED6, "Broadcom Corporation"},
-	{0xFED7, "Broadcom Corporation"},
-	{0xFED8, "Google Inc."},
-	{0xFED9, "Pebble Technology Corporation"},
-	{0xFEDA, "ISSC Technologies Corporation"},
-	{0xFEDB, "Perka, Inc."},
-	{0xFEDC, "Jawbone"},
-	{0xFEDD, "Jawbone"},
-	{0xFEDE, "Coin, Inc."},
-	{0xFEDF, "Design SHIFT"},
-	{0xFEE0, "Anhui Huami Information Technology Co."},
-	{0xFEE1, "Anhui Huami Information Technology Co."},
-	{0xFEE2, "Anki, Inc."},
-	{0xFEE3, "Anki, Inc."},
-	{0xFEE4, "Nordic Semiconductor ASA"},
-	{0xFEE5, "Nordic Semiconductor ASA"},
-	{0xFEE6, "Silvair, Inc."},
-	{0xFEE7, "Tencent Holdings Limited"},
-	{0xFEE8, "Quintic Corp."},
-	{0xFEE9, "Quintic Corp."},
-	{0xFEEA, "Swirl Networks, Inc."},
-	{0xFEEB, "Swirl Networks, Inc."},
-	{0xFEEC, "Tile, Inc."},
-	{0xFEED, "Tile, Inc."},
-	{0xFEEE, "Polar Electro Oy"},
-	{0xFEEF, "Polar Electro Oy"},
-	{0xFEF0, "Intel"},
-	{0xFEF1, "CSR"},
-	{0xFEF2, "CSR"},
-	{0xFEF3, "Google Inc."},
-	{0xFEF4, "Google Inc."},
-	{0xFEF5, "Dialog Semiconductor GmbH"},
-	{0xFEF6, "Wicentric, Inc."},
-	{0xFEF7, "Aplix Corporation"},
-	{0xFEF8, "Aplix Corporation"},
-	{0xFEF9, "PayPal, Inc."},
-	{0xFEFA, "PayPal, Inc."},
-	{0xFEFB, "Telit Wireless Solutions (Formerly Stollmann E+V GmbH)"},
-	{0xFEFC, "Gimbal, Inc."},
-	{0xFEFD, "Gimbal, Inc."},
-	{0xFEFE, "GN ReSound A/S"},
-	{0xFEFF, "GN Netcom"},
-	{0xFFFF, "Reserved"}, /*for testing purposes only*/
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+  {0xFE08, "Microsoft"},
+  {0xFE09, "Pillsy, Inc."},
+  {0xFE0A, "ruwido austria gmbh"},
+  {0xFE0B, "ruwido austria gmbh"},
+  {0xFE0C, "Procter & Gamble"},
+  {0xFE0D, "Procter & Gamble"},
+  {0xFE0E, "Setec Pty Ltd"},
+  {0xFE0F, "Philips Lighting B.V."},
+  {0xFE10, "Lapis Semiconductor Co., Ltd."},
+  {0xFE11, "GMC-I Messtechnik GmbH"},
+  {0xFE12, "M-Way Solutions GmbH"},
+  {0xFE13, "Apple Inc."},
+  {0xFE14, "Flextronics International USA Inc."},
+  {0xFE15, "Amazon Fulfillment Services, Inc."},
+  {0xFE16, "Footmarks, Inc."},
+  {0xFE17, "Telit Wireless Solutions GmbH"},
+  {0xFE18, "Runtime, Inc."},
+  {0xFE19, "Google Inc."},
+  {0xFE1A, "Tyto Life LLC"},
+  {0xFE1B, "Tyto Life LLC"},
+  {0xFE1C, "NetMedia, Inc."},
+  {0xFE1D, "Illuminati Instrument Corporation"},
+  {0xFE1E, "Smart Innovations Co., Ltd"},
+  {0xFE1F, "Garmin International, Inc."},
+  {0xFE20, "Emerson"},
+  {0xFE21, "Bose Corporation"},
+  {0xFE22, "Zoll Medical Corporation"},
+  {0xFE23, "Zoll Medical Corporation"},
+  {0xFE24, "August Home Inc"},
+  {0xFE25, "Apple, Inc. "},
+  {0xFE26, "Google Inc."},
+  {0xFE27, "Google Inc."},
+  {0xFE28, "Ayla Networks"},
+  {0xFE29, "Gibson Innovations"},
+  {0xFE2A, "DaisyWorks, Inc."},
+  {0xFE2B, "ITT Industries"},
+  {0xFE2C, "Google Inc."},
+  {0xFE2D, "SMART INNOVATION Co.,Ltd"},
+  {0xFE2E, "ERi,Inc."},
+  {0xFE2F, "CRESCO Wireless, Inc"},
+  {0xFE30, "Volkswagen AG"},
+  {0xFE31, "Volkswagen AG"},
+  {0xFE32, "Pro-Mark, Inc."},
+  {0xFE33, "CHIPOLO d.o.o."},
+  {0xFE34, "SmallLoop LLC"},
+  {0xFE35, "HUAWEI Technologies Co., Ltd"},
+  {0xFE36, "HUAWEI Technologies Co., Ltd"},
+  {0xFE37, "Spaceek LTD"},
+  {0xFE38, "Spaceek LTD"},
+  {0xFE39, "TTS Tooltechnic Systems AG & Co. KG"},
+  {0xFE3A, "TTS Tooltechnic Systems AG & Co. KG"},
+  {0xFE3B, "Dolby Laboratories"},
+  {0xFE3C, "Alibaba"},
+  {0xFE3D, "BD Medical"},
+  {0xFE3E, "BD Medical"},
+  {0xFE3F, "Friday Labs Limited"},
+  {0xFE40, "Inugo Systems Limited"},
+  {0xFE41, "Inugo Systems Limited"},
+  {0xFE42, "Nets A/S "},
+  {0xFE43, "Andreas Stihl AG & Co. KG"},
+  {0xFE44, "SK Telecom "},
+  {0xFE45, "Snapchat Inc"},
+  {0xFE46, "B&O Play A/S "},
+  {0xFE47, "General Motors"},
+  {0xFE48, "General Motors"},
+  {0xFE49, "SenionLab AB"},
+  {0xFE4A, "OMRON HEALTHCARE Co., Ltd."},
+  {0xFE4B, "Philips Lighting B.V."},
+  {0xFE4C, "Volkswagen AG"},
+  {0xFE4D, "Casambi Technologies Oy"},
+  {0xFE4E, "NTT docomo"},
+  {0xFE4F, "Molekule, Inc."},
+  {0xFE50, "Google Inc."},
+  {0xFE51, "SRAM"},
+  {0xFE52, "SetPoint Medical"},
+  {0xFE53, "3M"},
+  {0xFE54, "Motiv, Inc."},
+  {0xFE55, "Google Inc."},
+  {0xFE56, "Google Inc."},
+  {0xFE57, "Dotted Labs"},
+  {0xFE58, "Nordic Semiconductor ASA"},
+  {0xFE59, "Nordic Semiconductor ASA"},
+  {0xFE5A, "Chronologics Corporation"},
+  {0xFE5B, "GT-tronics HK Ltd"},
+  {0xFE5C, "million hunters GmbH"},
+  {0xFE5D, "Grundfos A/S"},
+  {0xFE5E, "Plastc Corporation"},
+  {0xFE5F, "Eyefi, Inc."},
+  {0xFE60, "Lierda Science & Technology Group Co., Ltd."},
+  {0xFE61, "Logitech International SA"},
+  {0xFE62, "Indagem Tech LLC"},
+  {0xFE63, "Connected Yard, Inc."},
+  {0xFE64, "Siemens AG"},
+  {0xFE65, "CHIPOLO d.o.o."},
+  {0xFE66, "Intel Corporation"},
+  {0xFE67, "Lab Sensor Solutions"},
+  {0xFE68, "Qualcomm Life Inc"},
+  {0xFE69, "Qualcomm Life Inc"},
+  {0xFE6A, "Kontakt Micro-Location Sp. z o.o."},
+  {0xFE6B, "TASER International, Inc."},
+  {0xFE6C, "TASER International, Inc."},
+  {0xFE6D, "The University of Tokyo"},
+  {0xFE6E, "The University of Tokyo"},
+  {0xFE6F, "LINE Corporation"},
+  {0xFE70, "Beijing Jingdong Century Trading Co., Ltd."},
+  {0xFE71, "Plume Design Inc"},
+  {0xFE72, "St. Jude Medical, Inc."},
+  {0xFE73, "St. Jude Medical, Inc."},
+  {0xFE74, "unwire"},
+  {0xFE75, "TangoMe"},
+  {0xFE76, "TangoMe"},
+  {0xFE77, "Hewlett-Packard Company"},
+  {0xFE78, "Hewlett-Packard Company"},
+  {0xFE79, "Zebra Technologies"},
+  {0xFE7A, "Bragi GmbH"},
+  {0xFE7B, "Orion Labs, Inc."},
+  {0xFE7C, "Telit Wireless Solutions (Formerly Stollmann E+V GmbH)"},
+  {0xFE7D, "Aterica Health Inc."},
+  {0xFE7E, "Awear Solutions Ltd"},
+  {0xFE7F, "Doppler Lab"},
+  {0xFE80, "Doppler Lab"},
+  {0xFE81, "Medtronic Inc."},
+  {0xFE82, "Medtronic Inc."},
+  {0xFE83, "Blue Bite"},
+  {0xFE84, "RF Digital Corp"},
+  {0xFE85, "RF Digital Corp"},
+  {0xFE86, "HUAWEI Technologies Co., Ltd. ( )"},
+  {0xFE87, "Qingdao Yeelink Information Technology Co., Ltd. ( )"},
+  {0xFE88, "SALTO SYSTEMS S.L."},
+  {0xFE89, "B&O Play A/S"},
+  {0xFE8A, "Apple, Inc."},
+  {0xFE8B, "Apple, Inc."},
+  {0xFE8C, "TRON Forum"},
+  {0xFE8D, "Interaxon Inc."},
+  {0xFE8E, "ARM Ltd"},
+  {0xFE8F, "CSR"},
+  {0xFE90, "JUMA"},
+  {0xFE91, "Shanghai Imilab Technology Co.,Ltd"},
+  {0xFE92, "Jarden Safety & Security"},
+  {0xFE93, "OttoQ Inc."},
+  {0xFE94, "OttoQ Inc."},
+  {0xFE95, "Xiaomi Inc."},
+  {0xFE96, "Tesla Motor Inc."},
+  {0xFE97, "Tesla Motor Inc."},
+  {0xFE98, "Currant, Inc."},
+  {0xFE99, "Currant, Inc."},
+  {0xFE9A, "Estimote"},
+  {0xFE9B, "Samsara Networks, Inc"},
+  {0xFE9C, "GSI Laboratories, Inc."},
+  {0xFE9D, "Mobiquity Networks Inc"},
+  {0xFE9E, "Dialog Semiconductor B.V."},
+  {0xFE9F, "Google Inc."},
+  {0xFEA0, "Google Inc."},
+  {0xFEA1, "Intrepid Control Systems, Inc."},
+  {0xFEA2, "Intrepid Control Systems, Inc."},
+  {0xFEA3, "ITT Industries"},
+  {0xFEA4, "Paxton Access Ltd"},
+  {0xFEA5, "GoPro, Inc."},
+  {0xFEA6, "GoPro, Inc."},
+  {0xFEA7, "UTC Fire and Security"},
+  {0xFEA8, "Savant Systems LLC"},
+  {0xFEA9, "Savant Systems LLC"},
+  {0xFEAA, "Google Inc."},
+  {0xFEAB, "Nokia Corporation"},
+  {0xFEAC, "Nokia Corporation"},
+  {0xFEAD, "Nokia Corporation"},
+  {0xFEAE, "Nokia Corporation"},
+  {0xFEAF, "Nest Labs Inc."},
+  {0xFEB0, "Nest Labs Inc."},
+  {0xFEB1, "Electronics Tomorrow Limited"},
+  {0xFEB2, "Microsoft Corporation"},
+  {0xFEB3, "Taobao"},
+  {0xFEB4, "WiSilica Inc."},
+  {0xFEB5, "WiSilica Inc."},
+  {0xFEB6, "Vencer Co, Ltd"},
+  {0xFEB7, "Facebook, Inc."},
+  {0xFEB8, "Facebook, Inc."},
+  {0xFEB9, "LG Electronics"},
+  {0xFEBA, "Tencent Holdings Limited"},
+  {0xFEBB, "adafruit industries"},
+  {0xFEBC, "Dexcom, Inc. "},
+  {0xFEBD, "Clover Network, Inc."},
+  {0xFEBE, "Bose Corporation"},
+  {0xFEBF, "Nod, Inc."},
+  {0xFEC0, "KDDI Corporation"},
+  {0xFEC1, "KDDI Corporation"},
+  {0xFEC2, "Blue Spark Technologies, Inc."},
+  {0xFEC3, "360fly, Inc."},
+  {0xFEC4, "PLUS Location Systems"},
+  {0xFEC5, "Realtek Semiconductor Corp."},
+  {0xFEC6, "Kocomojo, LLC"},
+  {0xFEC7, "Apple, Inc."},
+  {0xFEC8, "Apple, Inc."},
+  {0xFEC9, "Apple, Inc."},
+  {0xFECA, "Apple, Inc."},
+  {0xFECB, "Apple, Inc."},
+  {0xFECC, "Apple, Inc."},
+  {0xFECD, "Apple, Inc."},
+  {0xFECE, "Apple, Inc."},
+  {0xFECF, "Apple, Inc."},
+  {0xFED0, "Apple, Inc."},
+  {0xFED1, "Apple, Inc."},
+  {0xFED2, "Apple, Inc."},
+  {0xFED3, "Apple, Inc."},
+  {0xFED4, "Apple, Inc."},
+  {0xFED5, "Plantronics Inc."},
+  {0xFED6, "Broadcom Corporation"},
+  {0xFED7, "Broadcom Corporation"},
+  {0xFED8, "Google Inc."},
+  {0xFED9, "Pebble Technology Corporation"},
+  {0xFEDA, "ISSC Technologies Corporation"},
+  {0xFEDB, "Perka, Inc."},
+  {0xFEDC, "Jawbone"},
+  {0xFEDD, "Jawbone"},
+  {0xFEDE, "Coin, Inc."},
+  {0xFEDF, "Design SHIFT"},
+  {0xFEE0, "Anhui Huami Information Technology Co."},
+  {0xFEE1, "Anhui Huami Information Technology Co."},
+  {0xFEE2, "Anki, Inc."},
+  {0xFEE3, "Anki, Inc."},
+  {0xFEE4, "Nordic Semiconductor ASA"},
+  {0xFEE5, "Nordic Semiconductor ASA"},
+  {0xFEE6, "Silvair, Inc."},
+  {0xFEE7, "Tencent Holdings Limited"},
+  {0xFEE8, "Quintic Corp."},
+  {0xFEE9, "Quintic Corp."},
+  {0xFEEA, "Swirl Networks, Inc."},
+  {0xFEEB, "Swirl Networks, Inc."},
+  {0xFEEC, "Tile, Inc."},
+  {0xFEED, "Tile, Inc."},
+  {0xFEEE, "Polar Electro Oy"},
+  {0xFEEF, "Polar Electro Oy"},
+  {0xFEF0, "Intel"},
+  {0xFEF1, "CSR"},
+  {0xFEF2, "CSR"},
+  {0xFEF3, "Google Inc."},
+  {0xFEF4, "Google Inc."},
+  {0xFEF5, "Dialog Semiconductor GmbH"},
+  {0xFEF6, "Wicentric, Inc."},
+  {0xFEF7, "Aplix Corporation"},
+  {0xFEF8, "Aplix Corporation"},
+  {0xFEF9, "PayPal, Inc."},
+  {0xFEFA, "PayPal, Inc."},
+  {0xFEFB, "Telit Wireless Solutions (Formerly Stollmann E+V GmbH)"},
+  {0xFEFC, "Gimbal, Inc."},
+  {0xFEFD, "Gimbal, Inc."},
+  {0xFEFE, "GN ReSound A/S"},
+  {0xFEFF, "GN Netcom"},
+  {0xFFFF, "Reserved"}, /*for testing purposes only*/
 #endif
-	{0, "" }
+  {0, ""}
 };
 
 typedef struct {
-	uint32_t    assignedNumber;
-	const char* name;
+  uint32_t assignedNumber;
+  const char *name;
 } gattdescriptor_t;
 
 static const gattdescriptor_t g_descriptor_ids[] = {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		{0x2905,"Characteristic Aggregate Format"},
-		{0x2900,"Characteristic Extended Properties"},
-		{0x2904,"Characteristic Presentation Format"},
-		{0x2901,"Characteristic User Description"},
-		{0x2902,"Client Characteristic Configuration"},
-		{0x290B,"Environmental Sensing Configuration"},
-		{0x290C,"Environmental Sensing Measurement"},
-		{0x290D,"Environmental Sensing Trigger Setting"},
-		{0x2907,"External Report Reference"},
-		{0x2909,"Number of Digitals"},
-		{0x2908,"Report Reference"},
-		{0x2903,"Server Characteristic Configuration"},
-		{0x290E,"Time Trigger Setting"},
-		{0x2906,"Valid Range"},
-		{0x290A,"Value Trigger Setting"},
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+  {0x2905, "Characteristic Aggregate Format"},
+  {0x2900, "Characteristic Extended Properties"},
+  {0x2904, "Characteristic Presentation Format"},
+  {0x2901, "Characteristic User Description"},
+  {0x2902, "Client Characteristic Configuration"},
+  {0x290B, "Environmental Sensing Configuration"},
+  {0x290C, "Environmental Sensing Measurement"},
+  {0x290D, "Environmental Sensing Trigger Setting"},
+  {0x2907, "External Report Reference"},
+  {0x2909, "Number of Digitals"},
+  {0x2908, "Report Reference"},
+  {0x2903, "Server Characteristic Configuration"},
+  {0x290E, "Time Trigger Setting"},
+  {0x2906, "Valid Range"},
+  {0x290A, "Value Trigger Setting"},
 #endif
-		{ 0, "" }
+  {0, ""}
 };
 
 typedef struct {
-	uint32_t    assignedNumber;
-	const char* name;
+  uint32_t assignedNumber;
+  const char *name;
 } characteristicMap_t;
 
 static const characteristicMap_t g_characteristicsMappings[] = {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		{0x2A7E,"Aerobic Heart Rate Lower Limit"},
-		{0x2A84,"Aerobic Heart Rate Upper Limit"},
-		{0x2A7F,"Aerobic Threshold"},
-		{0x2A80,"Age"},
-		{0x2A5A,"Aggregate"},
-		{0x2A43,"Alert Category ID"},
-		{0x2A42,"Alert Category ID Bit Mask"},
-		{0x2A06,"Alert Level"},
-		{0x2A44,"Alert Notification Control Point"},
-		{0x2A3F,"Alert Status"},
-		{0x2AB3,"Altitude"},
-		{0x2A81,"Anaerobic Heart Rate Lower Limit"},
-		{0x2A82,"Anaerobic Heart Rate Upper Limit"},
-		{0x2A83,"Anaerobic Threshold"},
-		{0x2A58,"Analog"},
-		{0x2A59,"Analog Output"},
-		{0x2A73,"Apparent Wind Direction"},
-		{0x2A72,"Apparent Wind Speed"},
-		{0x2A01,"Appearance"},
-		{0x2AA3,"Barometric Pressure Trend"},
-		{0x2A19,"Battery Level"},
-		{0x2A1B,"Battery Level State"},
-		{0x2A1A,"Battery Power State"},
-		{0x2A49,"Blood Pressure Feature"},
-		{0x2A35,"Blood Pressure Measurement"},
-		{0x2A9B,"Body Composition Feature"},
-		{0x2A9C,"Body Composition Measurement"},
-		{0x2A38,"Body Sensor Location"},
-		{0x2AA4,"Bond Management Control Point"},
-		{0x2AA5,"Bond Management Features"},
-		{0x2A22,"Boot Keyboard Input Report"},
-		{0x2A32,"Boot Keyboard Output Report"},
-		{0x2A33,"Boot Mouse Input Report"},
-		{0x2AA6,"Central Address Resolution"},
-		{0x2AA8,"CGM Feature"},
-		{0x2AA7,"CGM Measurement"},
-		{0x2AAB,"CGM Session Run Time"},
-		{0x2AAA,"CGM Session Start Time"},
-		{0x2AAC,"CGM Specific Ops Control Point"},
-		{0x2AA9,"CGM Status"},
-		{0x2ACE,"Cross Trainer Data"},
-		{0x2A5C,"CSC Feature"},
-		{0x2A5B,"CSC Measurement"},
-		{0x2A2B,"Current Time"},
-		{0x2A66,"Cycling Power Control Point"},
-		{0x2A66,"Cycling Power Control Point"},
-		{0x2A65,"Cycling Power Feature"},
-		{0x2A65,"Cycling Power Feature"},
-		{0x2A63,"Cycling Power Measurement"},
-		{0x2A64,"Cycling Power Vector"},
-		{0x2A99,"Database Change Increment"},
-		{0x2A85,"Date of Birth"},
-		{0x2A86,"Date of Threshold Assessment"},
-		{0x2A08,"Date Time"},
-		{0x2A0A,"Day Date Time"},
-		{0x2A09,"Day of Week"},
-		{0x2A7D,"Descriptor Value Changed"},
-		{0x2A00,"Device Name"},
-		{0x2A7B,"Dew Point"},
-		{0x2A56,"Digital"},
-		{0x2A57,"Digital Output"},
-		{0x2A0D,"DST Offset"},
-		{0x2A6C,"Elevation"},
-		{0x2A87,"Email Address"},
-		{0x2A0B,"Exact Time 100"},
-		{0x2A0C,"Exact Time 256"},
-		{0x2A88,"Fat Burn Heart Rate Lower Limit"},
-		{0x2A89,"Fat Burn Heart Rate Upper Limit"},
-		{0x2A26,"Firmware Revision String"},
-		{0x2A8A,"First Name"},
-		{0x2AD9,"Fitness Machine Control Point"},
-		{0x2ACC,"Fitness Machine Feature"},
-		{0x2ADA,"Fitness Machine Status"},
-		{0x2A8B,"Five Zone Heart Rate Limits"},
-		{0x2AB2,"Floor Number"},
-		{0x2A8C,"Gender"},
-		{0x2A51,"Glucose Feature"},
-		{0x2A18,"Glucose Measurement"},
-		{0x2A34,"Glucose Measurement Context"},
-		{0x2A74,"Gust Factor"},
-		{0x2A27,"Hardware Revision String"},
-		{0x2A39,"Heart Rate Control Point"},
-		{0x2A8D,"Heart Rate Max"},
-		{0x2A37,"Heart Rate Measurement"},
-		{0x2A7A,"Heat Index"},
-		{0x2A8E,"Height"},
-		{0x2A4C,"HID Control Point"},
-		{0x2A4A,"HID Information"},
-		{0x2A8F,"Hip Circumference"},
-		{0x2ABA,"HTTP Control Point"},
-		{0x2AB9,"HTTP Entity Body"},
-		{0x2AB7,"HTTP Headers"},
-		{0x2AB8,"HTTP Status Code"},
-		{0x2ABB,"HTTPS Security"},
-		{0x2A6F,"Humidity"},
-		{0x2A2A,"IEEE 11073-20601 Regulatory Certification Data List"},
-		{0x2AD2,"Indoor Bike Data"},
-		{0x2AAD,"Indoor Positioning Configuration"},
-		{0x2A36,"Intermediate Cuff Pressure"},
-		{0x2A1E,"Intermediate Temperature"},
-		{0x2A77,"Irradiance"},
-		{0x2AA2,"Language"},
-		{0x2A90,"Last Name"},
-		{0x2AAE,"Latitude"},
-		{0x2A6B,"LN Control Point"},
-		{0x2A6A,"LN Feature"},
-		{0x2AB1,"Local East Coordinate"},
-		{0x2AB0,"Local North Coordinate"},
-		{0x2A0F,"Local Time Information"},
-		{0x2A67,"Location and Speed Characteristic"},
-		{0x2AB5,"Location Name"},
-		{0x2AAF,"Longitude"},
-		{0x2A2C,"Magnetic Declination"},
-		{0x2AA0,"Magnetic Flux Density - 2D"},
-		{0x2AA1,"Magnetic Flux Density - 3D"},
-		{0x2A29,"Manufacturer Name String"},
-		{0x2A91,"Maximum Recommended Heart Rate"},
-		{0x2A21,"Measurement Interval"},
-		{0x2A24,"Model Number String"},
-		{0x2A68,"Navigation"},
-		{0x2A3E,"Network Availability"},
-		{0x2A46,"New Alert"},
-		{0x2AC5,"Object Action Control Point"},
-		{0x2AC8,"Object Changed"},
-		{0x2AC1,"Object First-Created"},
-		{0x2AC3,"Object ID"},
-		{0x2AC2,"Object Last-Modified"},
-		{0x2AC6,"Object List Control Point"},
-		{0x2AC7,"Object List Filter"},
-		{0x2ABE,"Object Name"},
-		{0x2AC4,"Object Properties"},
-		{0x2AC0,"Object Size"},
-		{0x2ABF,"Object Type"},
-		{0x2ABD,"OTS Feature"},
-		{0x2A04,"Peripheral Preferred Connection Parameters"},
-		{0x2A02,"Peripheral Privacy Flag"},
-		{0x2A5F,"PLX Continuous Measurement Characteristic"},
-		{0x2A60,"PLX Features"},
-		{0x2A5E,"PLX Spot-Check Measurement"},
-		{0x2A50,"PnP ID"},
-		{0x2A75,"Pollen Concentration"},
-		{0x2A2F,"Position 2D"},
-		{0x2A30,"Position 3D"},
-		{0x2A69,"Position Quality"},
-		{0x2A6D,"Pressure"},
-		{0x2A4E,"Protocol Mode"},
-		{0x2A62,"Pulse Oximetry Control Point"},
-		{0x2A60,"Pulse Oximetry Pulsatile Event Characteristic"},
-		{0x2A78,"Rainfall"},
-		{0x2A03,"Reconnection Address"},
-		{0x2A52,"Record Access Control Point"},
-		{0x2A14,"Reference Time Information"},
-		{0x2A3A,"Removable"},
-		{0x2A4D,"Report"},
-		{0x2A4B,"Report Map"},
-		{0x2AC9,"Resolvable Private Address Only"},
-		{0x2A92,"Resting Heart Rate"},
-		{0x2A40,"Ringer Control point"},
-		{0x2A41,"Ringer Setting"},
-		{0x2AD1,"Rower Data"},
-		{0x2A54,"RSC Feature"},
-		{0x2A53,"RSC Measurement"},
-		{0x2A55,"SC Control Point"},
-		{0x2A4F,"Scan Interval Window"},
-		{0x2A31,"Scan Refresh"},
-		{0x2A3C,"Scientific Temperature Celsius"},
-		{0x2A10,"Secondary Time Zone"},
-		{0x2A5D,"Sensor Location"},
-		{0x2A25,"Serial Number String"},
-		{0x2A05,"Service Changed"},
-		{0x2A3B,"Service Required"},
-		{0x2A28,"Software Revision String"},
-		{0x2A93,"Sport Type for Aerobic and Anaerobic Thresholds"},
-		{0x2AD0,"Stair Climber Data"},
-		{0x2ACF,"Step Climber Data"},
-		{0x2A3D,"String"},
-		{0x2AD7,"Supported Heart Rate Range"},
-		{0x2AD5,"Supported Inclination Range"},
-		{0x2A47,"Supported New Alert Category"},
-		{0x2AD8,"Supported Power Range"},
-		{0x2AD6,"Supported Resistance Level Range"},
-		{0x2AD4,"Supported Speed Range"},
-		{0x2A48,"Supported Unread Alert Category"},
-		{0x2A23,"System ID"},
-		{0x2ABC,"TDS Control Point"},
-		{0x2A6E,"Temperature"},
-		{0x2A1F,"Temperature Celsius"},
-		{0x2A20,"Temperature Fahrenheit"},
-		{0x2A1C,"Temperature Measurement"},
-		{0x2A1D,"Temperature Type"},
-		{0x2A94,"Three Zone Heart Rate Limits"},
-		{0x2A12,"Time Accuracy"},
-		{0x2A15,"Time Broadcast"},
-		{0x2A13,"Time Source"},
-		{0x2A16,"Time Update Control Point"},
-		{0x2A17,"Time Update State"},
-		{0x2A11,"Time with DST"},
-		{0x2A0E,"Time Zone"},
-		{0x2AD3,"Training Status"},
-		{0x2ACD,"Treadmill Data"},
-		{0x2A71,"True Wind Direction"},
-		{0x2A70,"True Wind Speed"},
-		{0x2A95,"Two Zone Heart Rate Limit"},
-		{0x2A07,"Tx Power Level"},
-		{0x2AB4,"Uncertainty"},
-		{0x2A45,"Unread Alert Status"},
-		{0x2AB6,"URI"},
-		{0x2A9F,"User Control Point"},
-		{0x2A9A,"User Index"},
-		{0x2A76,"UV Index"},
-		{0x2A96,"VO2 Max"},
-		{0x2A97,"Waist Circumference"},
-		{0x2A98,"Weight"},
-		{0x2A9D,"Weight Measurement"},
-		{0x2A9E,"Weight Scale Feature"},
-		{0x2A79,"Wind Chill"},
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+  {0x2A7E, "Aerobic Heart Rate Lower Limit"},
+  {0x2A84, "Aerobic Heart Rate Upper Limit"},
+  {0x2A7F, "Aerobic Threshold"},
+  {0x2A80, "Age"},
+  {0x2A5A, "Aggregate"},
+  {0x2A43, "Alert Category ID"},
+  {0x2A42, "Alert Category ID Bit Mask"},
+  {0x2A06, "Alert Level"},
+  {0x2A44, "Alert Notification Control Point"},
+  {0x2A3F, "Alert Status"},
+  {0x2AB3, "Altitude"},
+  {0x2A81, "Anaerobic Heart Rate Lower Limit"},
+  {0x2A82, "Anaerobic Heart Rate Upper Limit"},
+  {0x2A83, "Anaerobic Threshold"},
+  {0x2A58, "Analog"},
+  {0x2A59, "Analog Output"},
+  {0x2A73, "Apparent Wind Direction"},
+  {0x2A72, "Apparent Wind Speed"},
+  {0x2A01, "Appearance"},
+  {0x2AA3, "Barometric Pressure Trend"},
+  {0x2A19, "Battery Level"},
+  {0x2A1B, "Battery Level State"},
+  {0x2A1A, "Battery Power State"},
+  {0x2A49, "Blood Pressure Feature"},
+  {0x2A35, "Blood Pressure Measurement"},
+  {0x2A9B, "Body Composition Feature"},
+  {0x2A9C, "Body Composition Measurement"},
+  {0x2A38, "Body Sensor Location"},
+  {0x2AA4, "Bond Management Control Point"},
+  {0x2AA5, "Bond Management Features"},
+  {0x2A22, "Boot Keyboard Input Report"},
+  {0x2A32, "Boot Keyboard Output Report"},
+  {0x2A33, "Boot Mouse Input Report"},
+  {0x2AA6, "Central Address Resolution"},
+  {0x2AA8, "CGM Feature"},
+  {0x2AA7, "CGM Measurement"},
+  {0x2AAB, "CGM Session Run Time"},
+  {0x2AAA, "CGM Session Start Time"},
+  {0x2AAC, "CGM Specific Ops Control Point"},
+  {0x2AA9, "CGM Status"},
+  {0x2ACE, "Cross Trainer Data"},
+  {0x2A5C, "CSC Feature"},
+  {0x2A5B, "CSC Measurement"},
+  {0x2A2B, "Current Time"},
+  {0x2A66, "Cycling Power Control Point"},
+  {0x2A66, "Cycling Power Control Point"},
+  {0x2A65, "Cycling Power Feature"},
+  {0x2A65, "Cycling Power Feature"},
+  {0x2A63, "Cycling Power Measurement"},
+  {0x2A64, "Cycling Power Vector"},
+  {0x2A99, "Database Change Increment"},
+  {0x2A85, "Date of Birth"},
+  {0x2A86, "Date of Threshold Assessment"},
+  {0x2A08, "Date Time"},
+  {0x2A0A, "Day Date Time"},
+  {0x2A09, "Day of Week"},
+  {0x2A7D, "Descriptor Value Changed"},
+  {0x2A00, "Device Name"},
+  {0x2A7B, "Dew Point"},
+  {0x2A56, "Digital"},
+  {0x2A57, "Digital Output"},
+  {0x2A0D, "DST Offset"},
+  {0x2A6C, "Elevation"},
+  {0x2A87, "Email Address"},
+  {0x2A0B, "Exact Time 100"},
+  {0x2A0C, "Exact Time 256"},
+  {0x2A88, "Fat Burn Heart Rate Lower Limit"},
+  {0x2A89, "Fat Burn Heart Rate Upper Limit"},
+  {0x2A26, "Firmware Revision String"},
+  {0x2A8A, "First Name"},
+  {0x2AD9, "Fitness Machine Control Point"},
+  {0x2ACC, "Fitness Machine Feature"},
+  {0x2ADA, "Fitness Machine Status"},
+  {0x2A8B, "Five Zone Heart Rate Limits"},
+  {0x2AB2, "Floor Number"},
+  {0x2A8C, "Gender"},
+  {0x2A51, "Glucose Feature"},
+  {0x2A18, "Glucose Measurement"},
+  {0x2A34, "Glucose Measurement Context"},
+  {0x2A74, "Gust Factor"},
+  {0x2A27, "Hardware Revision String"},
+  {0x2A39, "Heart Rate Control Point"},
+  {0x2A8D, "Heart Rate Max"},
+  {0x2A37, "Heart Rate Measurement"},
+  {0x2A7A, "Heat Index"},
+  {0x2A8E, "Height"},
+  {0x2A4C, "HID Control Point"},
+  {0x2A4A, "HID Information"},
+  {0x2A8F, "Hip Circumference"},
+  {0x2ABA, "HTTP Control Point"},
+  {0x2AB9, "HTTP Entity Body"},
+  {0x2AB7, "HTTP Headers"},
+  {0x2AB8, "HTTP Status Code"},
+  {0x2ABB, "HTTPS Security"},
+  {0x2A6F, "Humidity"},
+  {0x2A2A, "IEEE 11073-20601 Regulatory Certification Data List"},
+  {0x2AD2, "Indoor Bike Data"},
+  {0x2AAD, "Indoor Positioning Configuration"},
+  {0x2A36, "Intermediate Cuff Pressure"},
+  {0x2A1E, "Intermediate Temperature"},
+  {0x2A77, "Irradiance"},
+  {0x2AA2, "Language"},
+  {0x2A90, "Last Name"},
+  {0x2AAE, "Latitude"},
+  {0x2A6B, "LN Control Point"},
+  {0x2A6A, "LN Feature"},
+  {0x2AB1, "Local East Coordinate"},
+  {0x2AB0, "Local North Coordinate"},
+  {0x2A0F, "Local Time Information"},
+  {0x2A67, "Location and Speed Characteristic"},
+  {0x2AB5, "Location Name"},
+  {0x2AAF, "Longitude"},
+  {0x2A2C, "Magnetic Declination"},
+  {0x2AA0, "Magnetic Flux Density - 2D"},
+  {0x2AA1, "Magnetic Flux Density - 3D"},
+  {0x2A29, "Manufacturer Name String"},
+  {0x2A91, "Maximum Recommended Heart Rate"},
+  {0x2A21, "Measurement Interval"},
+  {0x2A24, "Model Number String"},
+  {0x2A68, "Navigation"},
+  {0x2A3E, "Network Availability"},
+  {0x2A46, "New Alert"},
+  {0x2AC5, "Object Action Control Point"},
+  {0x2AC8, "Object Changed"},
+  {0x2AC1, "Object First-Created"},
+  {0x2AC3, "Object ID"},
+  {0x2AC2, "Object Last-Modified"},
+  {0x2AC6, "Object List Control Point"},
+  {0x2AC7, "Object List Filter"},
+  {0x2ABE, "Object Name"},
+  {0x2AC4, "Object Properties"},
+  {0x2AC0, "Object Size"},
+  {0x2ABF, "Object Type"},
+  {0x2ABD, "OTS Feature"},
+  {0x2A04, "Peripheral Preferred Connection Parameters"},
+  {0x2A02, "Peripheral Privacy Flag"},
+  {0x2A5F, "PLX Continuous Measurement Characteristic"},
+  {0x2A60, "PLX Features"},
+  {0x2A5E, "PLX Spot-Check Measurement"},
+  {0x2A50, "PnP ID"},
+  {0x2A75, "Pollen Concentration"},
+  {0x2A2F, "Position 2D"},
+  {0x2A30, "Position 3D"},
+  {0x2A69, "Position Quality"},
+  {0x2A6D, "Pressure"},
+  {0x2A4E, "Protocol Mode"},
+  {0x2A62, "Pulse Oximetry Control Point"},
+  {0x2A60, "Pulse Oximetry Pulsatile Event Characteristic"},
+  {0x2A78, "Rainfall"},
+  {0x2A03, "Reconnection Address"},
+  {0x2A52, "Record Access Control Point"},
+  {0x2A14, "Reference Time Information"},
+  {0x2A3A, "Removable"},
+  {0x2A4D, "Report"},
+  {0x2A4B, "Report Map"},
+  {0x2AC9, "Resolvable Private Address Only"},
+  {0x2A92, "Resting Heart Rate"},
+  {0x2A40, "Ringer Control point"},
+  {0x2A41, "Ringer Setting"},
+  {0x2AD1, "Rower Data"},
+  {0x2A54, "RSC Feature"},
+  {0x2A53, "RSC Measurement"},
+  {0x2A55, "SC Control Point"},
+  {0x2A4F, "Scan Interval Window"},
+  {0x2A31, "Scan Refresh"},
+  {0x2A3C, "Scientific Temperature Celsius"},
+  {0x2A10, "Secondary Time Zone"},
+  {0x2A5D, "Sensor Location"},
+  {0x2A25, "Serial Number String"},
+  {0x2A05, "Service Changed"},
+  {0x2A3B, "Service Required"},
+  {0x2A28, "Software Revision String"},
+  {0x2A93, "Sport Type for Aerobic and Anaerobic Thresholds"},
+  {0x2AD0, "Stair Climber Data"},
+  {0x2ACF, "Step Climber Data"},
+  {0x2A3D, "String"},
+  {0x2AD7, "Supported Heart Rate Range"},
+  {0x2AD5, "Supported Inclination Range"},
+  {0x2A47, "Supported New Alert Category"},
+  {0x2AD8, "Supported Power Range"},
+  {0x2AD6, "Supported Resistance Level Range"},
+  {0x2AD4, "Supported Speed Range"},
+  {0x2A48, "Supported Unread Alert Category"},
+  {0x2A23, "System ID"},
+  {0x2ABC, "TDS Control Point"},
+  {0x2A6E, "Temperature"},
+  {0x2A1F, "Temperature Celsius"},
+  {0x2A20, "Temperature Fahrenheit"},
+  {0x2A1C, "Temperature Measurement"},
+  {0x2A1D, "Temperature Type"},
+  {0x2A94, "Three Zone Heart Rate Limits"},
+  {0x2A12, "Time Accuracy"},
+  {0x2A15, "Time Broadcast"},
+  {0x2A13, "Time Source"},
+  {0x2A16, "Time Update Control Point"},
+  {0x2A17, "Time Update State"},
+  {0x2A11, "Time with DST"},
+  {0x2A0E, "Time Zone"},
+  {0x2AD3, "Training Status"},
+  {0x2ACD, "Treadmill Data"},
+  {0x2A71, "True Wind Direction"},
+  {0x2A70, "True Wind Speed"},
+  {0x2A95, "Two Zone Heart Rate Limit"},
+  {0x2A07, "Tx Power Level"},
+  {0x2AB4, "Uncertainty"},
+  {0x2A45, "Unread Alert Status"},
+  {0x2AB6, "URI"},
+  {0x2A9F, "User Control Point"},
+  {0x2A9A, "User Index"},
+  {0x2A76, "UV Index"},
+  {0x2A96, "VO2 Max"},
+  {0x2A97, "Waist Circumference"},
+  {0x2A98, "Weight"},
+  {0x2A9D, "Weight Measurement"},
+  {0x2A9E, "Weight Scale Feature"},
+  {0x2A79, "Wind Chill"},
 #endif
-		{0, ""}
+  {0, ""}
 };
 
 /**
  * @brief Mapping from service ids to names
  */
 typedef struct {
-	const char* name;
-	const char* type;
-	uint32_t    assignedNumber;
+  const char *name;
+  const char *type;
+  uint32_t assignedNumber;
 } gattService_t;
 
-
 /**
  * Definition of the service ids to names that we know about.
  */
 static const gattService_t g_gattServices[] = {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-	{"Alert Notification Service", "org.bluetooth.service.alert_notification", 0x1811},
-	{"Automation IO", "org.bluetooth.service.automation_io",	0x1815 },
-	{"Battery Service","org.bluetooth.service.battery_service",	0x180F},
-	{"Blood Pressure", "org.bluetooth.service.blood_pressure", 0x1810},
-	{"Body Composition", "org.bluetooth.service.body_composition", 0x181B},
-	{"Bond Management", "org.bluetooth.service.bond_management", 0x181E},
-	{"Continuous Glucose Monitoring", "org.bluetooth.service.continuous_glucose_monitoring", 0x181F},
-	{"Current Time Service", "org.bluetooth.service.current_time", 0x1805},
-	{"Cycling Power", "org.bluetooth.service.cycling_power", 0x1818},
-	{"Cycling Speed and Cadence", "org.bluetooth.service.cycling_speed_and_cadence", 0x1816},
-	{"Device Information", "org.bluetooth.service.device_information", 0x180A},
-	{"Environmental Sensing", "org.bluetooth.service.environmental_sensing", 0x181A},
-	{"Generic Access", "org.bluetooth.service.generic_access", 0x1800},
-	{"Generic Attribute", "org.bluetooth.service.generic_attribute", 0x1801},
-	{"Glucose", "org.bluetooth.service.glucose", 0x1808},
-	{"Health Thermometer", "org.bluetooth.service.health_thermometer", 0x1809},
-	{"Heart Rate", "org.bluetooth.service.heart_rate", 0x180D},
-	{"HTTP Proxy", "org.bluetooth.service.http_proxy", 0x1823},
-	{"Human Interface Device", "org.bluetooth.service.human_interface_device", 0x1812},
-	{"Immediate Alert", "org.bluetooth.service.immediate_alert", 0x1802},
-	{"Indoor Positioning", "org.bluetooth.service.indoor_positioning", 0x1821},
-	{"Internet Protocol Support", "org.bluetooth.service.internet_protocol_support", 0x1820},
-	{"Link Loss", "org.bluetooth.service.link_loss", 0x1803},
-	{"Location and Navigation", "org.bluetooth.service.location_and_navigation", 0x1819},
-	{"Next DST Change Service", "org.bluetooth.service.next_dst_change", 0x1807},
-	{"Object Transfer", "org.bluetooth.service.object_transfer", 0x1825},
-	{"Phone Alert Status Service", "org.bluetooth.service.phone_alert_status", 0x180E},
-	{"Pulse Oximeter", "org.bluetooth.service.pulse_oximeter", 0x1822},
-	{"Reference Time Update Service", "org.bluetooth.service.reference_time_update", 0x1806},
-	{"Running Speed and Cadence", "org.bluetooth.service.running_speed_and_cadence", 0x1814},
-	{"Scan Parameters", "org.bluetooth.service.scan_parameters", 0x1813},
-	{"Transport Discovery", "org.bluetooth.service.transport_discovery", 0x1824},
-	{"Tx Power", "org.bluetooth.service.tx_power", 0x1804},
-	{"User Data", "org.bluetooth.service.user_data", 0x181C},
-	{"Weight Scale", "org.bluetooth.service.weight_scale", 0x181D},
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+  {"Alert Notification Service", "org.bluetooth.service.alert_notification", 0x1811},
+  {"Automation IO", "org.bluetooth.service.automation_io", 0x1815},
+  {"Battery Service", "org.bluetooth.service.battery_service", 0x180F},
+  {"Blood Pressure", "org.bluetooth.service.blood_pressure", 0x1810},
+  {"Body Composition", "org.bluetooth.service.body_composition", 0x181B},
+  {"Bond Management", "org.bluetooth.service.bond_management", 0x181E},
+  {"Continuous Glucose Monitoring", "org.bluetooth.service.continuous_glucose_monitoring", 0x181F},
+  {"Current Time Service", "org.bluetooth.service.current_time", 0x1805},
+  {"Cycling Power", "org.bluetooth.service.cycling_power", 0x1818},
+  {"Cycling Speed and Cadence", "org.bluetooth.service.cycling_speed_and_cadence", 0x1816},
+  {"Device Information", "org.bluetooth.service.device_information", 0x180A},
+  {"Environmental Sensing", "org.bluetooth.service.environmental_sensing", 0x181A},
+  {"Generic Access", "org.bluetooth.service.generic_access", 0x1800},
+  {"Generic Attribute", "org.bluetooth.service.generic_attribute", 0x1801},
+  {"Glucose", "org.bluetooth.service.glucose", 0x1808},
+  {"Health Thermometer", "org.bluetooth.service.health_thermometer", 0x1809},
+  {"Heart Rate", "org.bluetooth.service.heart_rate", 0x180D},
+  {"HTTP Proxy", "org.bluetooth.service.http_proxy", 0x1823},
+  {"Human Interface Device", "org.bluetooth.service.human_interface_device", 0x1812},
+  {"Immediate Alert", "org.bluetooth.service.immediate_alert", 0x1802},
+  {"Indoor Positioning", "org.bluetooth.service.indoor_positioning", 0x1821},
+  {"Internet Protocol Support", "org.bluetooth.service.internet_protocol_support", 0x1820},
+  {"Link Loss", "org.bluetooth.service.link_loss", 0x1803},
+  {"Location and Navigation", "org.bluetooth.service.location_and_navigation", 0x1819},
+  {"Next DST Change Service", "org.bluetooth.service.next_dst_change", 0x1807},
+  {"Object Transfer", "org.bluetooth.service.object_transfer", 0x1825},
+  {"Phone Alert Status Service", "org.bluetooth.service.phone_alert_status", 0x180E},
+  {"Pulse Oximeter", "org.bluetooth.service.pulse_oximeter", 0x1822},
+  {"Reference Time Update Service", "org.bluetooth.service.reference_time_update", 0x1806},
+  {"Running Speed and Cadence", "org.bluetooth.service.running_speed_and_cadence", 0x1814},
+  {"Scan Parameters", "org.bluetooth.service.scan_parameters", 0x1813},
+  {"Transport Discovery", "org.bluetooth.service.transport_discovery", 0x1824},
+  {"Tx Power", "org.bluetooth.service.tx_power", 0x1804},
+  {"User Data", "org.bluetooth.service.user_data", 0x181C},
+  {"Weight Scale", "org.bluetooth.service.weight_scale", 0x181D},
 #endif
-	{"", "", 0 }
+  {"", "", 0}
 };
 
-
 /**
  * @brief Convert characteristic properties into a string representation.
  * @param [in] prop Characteristic properties.
  * @return A string representation of characteristic properties.
  */
-std::string BLEUtils::characteristicPropertiesToString(esp_gatt_char_prop_t prop) {
-	std::string res = "broadcast: ";
-	res += ((prop & ESP_GATT_CHAR_PROP_BIT_BROADCAST)?"1":"0");
-	res += ", read: ";
-	res += ((prop & ESP_GATT_CHAR_PROP_BIT_READ)?"1":"0");
-	res += ", write_nr: ";
-	res += ((prop & ESP_GATT_CHAR_PROP_BIT_WRITE_NR)?"1":"0");
-	res += ", write: ";
-	res += ((prop & ESP_GATT_CHAR_PROP_BIT_WRITE)?"1":"0");
-	res += ", notify: ";
-	res += ((prop & ESP_GATT_CHAR_PROP_BIT_NOTIFY)?"1":"0");
-	res += ", indicate: ";
-	res += ((prop & ESP_GATT_CHAR_PROP_BIT_INDICATE)?"1":"0");
-	res += ", auth: ";
-	res += ((prop & ESP_GATT_CHAR_PROP_BIT_AUTH)?"1":"0");
-	return res;
-} // characteristicPropertiesToString
+String BLEUtils::characteristicPropertiesToString(esp_gatt_char_prop_t prop) {
+  String res = "broadcast: ";
+  res += ((prop & ESP_GATT_CHAR_PROP_BIT_BROADCAST) ? "1" : "0");
+  res += ", read: ";
+  res += ((prop & ESP_GATT_CHAR_PROP_BIT_READ) ? "1" : "0");
+  res += ", write_nr: ";
+  res += ((prop & ESP_GATT_CHAR_PROP_BIT_WRITE_NR) ? "1" : "0");
+  res += ", write: ";
+  res += ((prop & ESP_GATT_CHAR_PROP_BIT_WRITE) ? "1" : "0");
+  res += ", notify: ";
+  res += ((prop & ESP_GATT_CHAR_PROP_BIT_NOTIFY) ? "1" : "0");
+  res += ", indicate: ";
+  res += ((prop & ESP_GATT_CHAR_PROP_BIT_INDICATE) ? "1" : "0");
+  res += ", auth: ";
+  res += ((prop & ESP_GATT_CHAR_PROP_BIT_AUTH) ? "1" : "0");
+  return res;
+}  // characteristicPropertiesToString
 
 /**
  * @brief Convert an esp_gatt_id_t to a string.
  */
-static std::string gattIdToString(esp_gatt_id_t gattId) {
-	std::string res = "uuid: " + BLEUUID(gattId.uuid).toString() + ", inst_id: ";
-	char val[8];
-	snprintf(val, sizeof(val), "%d", (int)gattId.inst_id);
-	res += val;
-	return res;
-} // gattIdToString
-
+static String gattIdToString(esp_gatt_id_t gattId) {
+  String res = "uuid: " + BLEUUID(gattId.uuid).toString() + ", inst_id: ";
+  char val[8];
+  snprintf(val, sizeof(val), "%d", (int)gattId.inst_id);
+  res += val;
+  return res;
+}  // gattIdToString
 
 /**
  * @brief Convert an esp_ble_addr_type_t to a string representation.
  */
-const char* BLEUtils::addressTypeToString(esp_ble_addr_type_t type) {
-	switch (type) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case BLE_ADDR_TYPE_PUBLIC:
-			return "BLE_ADDR_TYPE_PUBLIC";
-		case BLE_ADDR_TYPE_RANDOM:
-			return "BLE_ADDR_TYPE_RANDOM";
-		case BLE_ADDR_TYPE_RPA_PUBLIC:
-			return "BLE_ADDR_TYPE_RPA_PUBLIC";
-		case BLE_ADDR_TYPE_RPA_RANDOM:
-			return "BLE_ADDR_TYPE_RPA_RANDOM";
+const char *BLEUtils::addressTypeToString(esp_ble_addr_type_t type) {
+  switch (type) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case BLE_ADDR_TYPE_PUBLIC:     return "BLE_ADDR_TYPE_PUBLIC";
+    case BLE_ADDR_TYPE_RANDOM:     return "BLE_ADDR_TYPE_RANDOM";
+    case BLE_ADDR_TYPE_RPA_PUBLIC: return "BLE_ADDR_TYPE_RPA_PUBLIC";
+    case BLE_ADDR_TYPE_RPA_RANDOM: return "BLE_ADDR_TYPE_RPA_RANDOM";
 #endif
-		default:
-			return " esp_ble_addr_type_t";
-	}
-} // addressTypeToString
-
+    default: return " esp_ble_addr_type_t";
+  }
+}  // addressTypeToString
 
 /**
  * @brief Convert the BLE Advertising Data flags to a string.
  * @param adFlags The flags to convert
- * @return std::string A string representation of the advertising flags.
+ * @return String A string representation of the advertising flags.
  */
-std::string BLEUtils::adFlagsToString(uint8_t adFlags) {
-	std::string res;
-	if (adFlags & (1 << 0)) {
-		res += "[LE Limited Discoverable Mode] ";
-	}
-	if (adFlags & (1 << 1)) {
-		res += "[LE General Discoverable Mode] ";
-	}
-	if (adFlags & (1 << 2)) {
-		res += "[BR/EDR Not Supported] ";
-	}
-	if (adFlags & (1 << 3)) {
-		res += "[Simultaneous LE and BR/EDR to Same Device Capable (Controller)] ";
-	}
-	if (adFlags & (1 << 4)) {
-		res += "[Simultaneous LE and BR/EDR to Same Device Capable (Host)] ";
-	}
-	return res;
-} // adFlagsToString
-
+String BLEUtils::adFlagsToString(uint8_t adFlags) {
+  String res;
+  if (adFlags & (1 << 0)) {
+    res += "[LE Limited Discoverable Mode] ";
+  }
+  if (adFlags & (1 << 1)) {
+    res += "[LE General Discoverable Mode] ";
+  }
+  if (adFlags & (1 << 2)) {
+    res += "[BR/EDR Not Supported] ";
+  }
+  if (adFlags & (1 << 3)) {
+    res += "[Simultaneous LE and BR/EDR to Same Device Capable (Controller)] ";
+  }
+  if (adFlags & (1 << 4)) {
+    res += "[Simultaneous LE and BR/EDR to Same Device Capable (Host)] ";
+  }
+  return res;
+}  // adFlagsToString
 
 /**
  * @brief Given an advertising type, return a string representation of the type.
@@ -688,79 +676,75 @@ std::string BLEUtils::adFlagsToString(uint8_t adFlags) {
  *
  * @return A string representation of the type.
  */
-const char* BLEUtils::advTypeToString(uint8_t advType) {
-	switch (advType) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_BLE_AD_TYPE_FLAG:				   // 0x01
-			return "ESP_BLE_AD_TYPE_FLAG";
-		case ESP_BLE_AD_TYPE_16SRV_PART:			 // 0x02
-			return "ESP_BLE_AD_TYPE_16SRV_PART";
-		case ESP_BLE_AD_TYPE_16SRV_CMPL:			 // 0x03
-			return "ESP_BLE_AD_TYPE_16SRV_CMPL";
-		case ESP_BLE_AD_TYPE_32SRV_PART:			 // 0x04
-			return "ESP_BLE_AD_TYPE_32SRV_PART";
-		case ESP_BLE_AD_TYPE_32SRV_CMPL:			 // 0x05
-			return "ESP_BLE_AD_TYPE_32SRV_CMPL";
-		case ESP_BLE_AD_TYPE_128SRV_PART:			// 0x06
-			return "ESP_BLE_AD_TYPE_128SRV_PART";
-		case ESP_BLE_AD_TYPE_128SRV_CMPL:			// 0x07
-			return "ESP_BLE_AD_TYPE_128SRV_CMPL";
-		case ESP_BLE_AD_TYPE_NAME_SHORT:			 // 0x08
-			return "ESP_BLE_AD_TYPE_NAME_SHORT";
-		case ESP_BLE_AD_TYPE_NAME_CMPL:			  // 0x09
-			return "ESP_BLE_AD_TYPE_NAME_CMPL";
-		case ESP_BLE_AD_TYPE_TX_PWR:				 // 0x0a
-			return "ESP_BLE_AD_TYPE_TX_PWR";
-		case ESP_BLE_AD_TYPE_DEV_CLASS:			  // 0x0b
-			return "ESP_BLE_AD_TYPE_DEV_CLASS";
-		case ESP_BLE_AD_TYPE_SM_TK:				  // 0x10
-			return "ESP_BLE_AD_TYPE_SM_TK";
-		case ESP_BLE_AD_TYPE_SM_OOB_FLAG:			// 0x11
-			return "ESP_BLE_AD_TYPE_SM_OOB_FLAG";
-		case ESP_BLE_AD_TYPE_INT_RANGE:			  // 0x12
-			return "ESP_BLE_AD_TYPE_INT_RANGE";
-		case ESP_BLE_AD_TYPE_SOL_SRV_UUID:		   // 0x14
-			return "ESP_BLE_AD_TYPE_SOL_SRV_UUID";
-		case ESP_BLE_AD_TYPE_128SOL_SRV_UUID:		// 0x15
-			return "ESP_BLE_AD_TYPE_128SOL_SRV_UUID";
-		case ESP_BLE_AD_TYPE_SERVICE_DATA:		   // 0x16
-			return "ESP_BLE_AD_TYPE_SERVICE_DATA";
-		case ESP_BLE_AD_TYPE_PUBLIC_TARGET:		  // 0x17
-			return "ESP_BLE_AD_TYPE_PUBLIC_TARGET";
-		case ESP_BLE_AD_TYPE_RANDOM_TARGET:		  // 0x18
-			return "ESP_BLE_AD_TYPE_RANDOM_TARGET";
-		case ESP_BLE_AD_TYPE_APPEARANCE:			 // 0x19
-			return "ESP_BLE_AD_TYPE_APPEARANCE";
-		case ESP_BLE_AD_TYPE_ADV_INT:				// 0x1a
-			return "ESP_BLE_AD_TYPE_ADV_INT";
-		case ESP_BLE_AD_TYPE_32SOL_SRV_UUID:
-			return "ESP_BLE_AD_TYPE_32SOL_SRV_UUID";
-		case ESP_BLE_AD_TYPE_32SERVICE_DATA:		 // 0x20
-			return "ESP_BLE_AD_TYPE_32SERVICE_DATA";
-		case ESP_BLE_AD_TYPE_128SERVICE_DATA:		// 0x21
-			return "ESP_BLE_AD_TYPE_128SERVICE_DATA";
-		case ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE:  // 0xff
-			return "ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE";
+const char *BLEUtils::advTypeToString(uint8_t advType) {
+  switch (advType) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_BLE_AD_TYPE_FLAG:  // 0x01
+      return "ESP_BLE_AD_TYPE_FLAG";
+    case ESP_BLE_AD_TYPE_16SRV_PART:  // 0x02
+      return "ESP_BLE_AD_TYPE_16SRV_PART";
+    case ESP_BLE_AD_TYPE_16SRV_CMPL:  // 0x03
+      return "ESP_BLE_AD_TYPE_16SRV_CMPL";
+    case ESP_BLE_AD_TYPE_32SRV_PART:  // 0x04
+      return "ESP_BLE_AD_TYPE_32SRV_PART";
+    case ESP_BLE_AD_TYPE_32SRV_CMPL:  // 0x05
+      return "ESP_BLE_AD_TYPE_32SRV_CMPL";
+    case ESP_BLE_AD_TYPE_128SRV_PART:  // 0x06
+      return "ESP_BLE_AD_TYPE_128SRV_PART";
+    case ESP_BLE_AD_TYPE_128SRV_CMPL:  // 0x07
+      return "ESP_BLE_AD_TYPE_128SRV_CMPL";
+    case ESP_BLE_AD_TYPE_NAME_SHORT:  // 0x08
+      return "ESP_BLE_AD_TYPE_NAME_SHORT";
+    case ESP_BLE_AD_TYPE_NAME_CMPL:  // 0x09
+      return "ESP_BLE_AD_TYPE_NAME_CMPL";
+    case ESP_BLE_AD_TYPE_TX_PWR:  // 0x0a
+      return "ESP_BLE_AD_TYPE_TX_PWR";
+    case ESP_BLE_AD_TYPE_DEV_CLASS:  // 0x0b
+      return "ESP_BLE_AD_TYPE_DEV_CLASS";
+    case ESP_BLE_AD_TYPE_SM_TK:  // 0x10
+      return "ESP_BLE_AD_TYPE_SM_TK";
+    case ESP_BLE_AD_TYPE_SM_OOB_FLAG:  // 0x11
+      return "ESP_BLE_AD_TYPE_SM_OOB_FLAG";
+    case ESP_BLE_AD_TYPE_INT_RANGE:  // 0x12
+      return "ESP_BLE_AD_TYPE_INT_RANGE";
+    case ESP_BLE_AD_TYPE_SOL_SRV_UUID:  // 0x14
+      return "ESP_BLE_AD_TYPE_SOL_SRV_UUID";
+    case ESP_BLE_AD_TYPE_128SOL_SRV_UUID:  // 0x15
+      return "ESP_BLE_AD_TYPE_128SOL_SRV_UUID";
+    case ESP_BLE_AD_TYPE_SERVICE_DATA:  // 0x16
+      return "ESP_BLE_AD_TYPE_SERVICE_DATA";
+    case ESP_BLE_AD_TYPE_PUBLIC_TARGET:  // 0x17
+      return "ESP_BLE_AD_TYPE_PUBLIC_TARGET";
+    case ESP_BLE_AD_TYPE_RANDOM_TARGET:  // 0x18
+      return "ESP_BLE_AD_TYPE_RANDOM_TARGET";
+    case ESP_BLE_AD_TYPE_APPEARANCE:  // 0x19
+      return "ESP_BLE_AD_TYPE_APPEARANCE";
+    case ESP_BLE_AD_TYPE_ADV_INT:  // 0x1a
+      return "ESP_BLE_AD_TYPE_ADV_INT";
+    case ESP_BLE_AD_TYPE_32SOL_SRV_UUID: return "ESP_BLE_AD_TYPE_32SOL_SRV_UUID";
+    case ESP_BLE_AD_TYPE_32SERVICE_DATA:  // 0x20
+      return "ESP_BLE_AD_TYPE_32SERVICE_DATA";
+    case ESP_BLE_AD_TYPE_128SERVICE_DATA:  // 0x21
+      return "ESP_BLE_AD_TYPE_128SERVICE_DATA";
+    case ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE:  // 0xff
+      return "ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE";
 #endif
-		default:
-			log_v(" adv data type: 0x%x", advType);
-			return "";
-	} // End switch
-} // advTypeToString
-
+    default: log_v(" adv data type: 0x%x", advType); return "";
+  }  // End switch
+}  // advTypeToString
 
 esp_gatt_id_t BLEUtils::buildGattId(esp_bt_uuid_t uuid, uint8_t inst_id) {
-	esp_gatt_id_t retGattId;
-	retGattId.uuid = uuid;
-	retGattId.inst_id = inst_id;
-	return retGattId;
+  esp_gatt_id_t retGattId;
+  retGattId.uuid = uuid;
+  retGattId.inst_id = inst_id;
+  return retGattId;
 }
 
 esp_gatt_srvc_id_t BLEUtils::buildGattSrvcId(esp_gatt_id_t gattId, bool is_primary) {
-	esp_gatt_srvc_id_t retSrvcId;
-	retSrvcId.id = gattId;
-	retSrvcId.is_primary = is_primary;
-	return retSrvcId;
+  esp_gatt_srvc_id_t retSrvcId;
+  retSrvcId.id = gattId;
+  retSrvcId.is_primary = is_primary;
+  return retSrvcId;
 }
 
 /**
@@ -771,33 +755,34 @@ esp_gatt_srvc_id_t BLEUtils::buildGattSrvcId(esp_gatt_id_t gattId, bool is_prima
  * @param [in] length The length of the data to convert.
  * @return A pointer to the formatted buffer.
  */
-char* BLEUtils::buildHexData(uint8_t* target, uint8_t* source, uint8_t length) {
-	// Guard against too much data.
-	if (length > 100) length = 100;
-
-	if (target == nullptr) {
-		target = (uint8_t*) malloc(length * 2 + 1);
-		if (target == nullptr) {
-			log_e("buildHexData: malloc failed");
-			return nullptr;
-		}
-	}
-	char* startOfData = (char*) target;
-
-	for (int i = 0; i < length; i++) {
-		sprintf((char*) target, "%.2x", (char) *source);
-		source++;
-		target += 2;
-	}
-
-	// Handle the special case where there was no data.
-	if (length == 0) {
-		*startOfData = 0;
-	}
-
-	return startOfData;
-} // buildHexData
-
+char *BLEUtils::buildHexData(uint8_t *target, uint8_t *source, uint8_t length) {
+  // Guard against too much data.
+  if (length > 100) {
+    length = 100;
+  }
+
+  if (target == nullptr) {
+    target = (uint8_t *)malloc(length * 2 + 1);
+    if (target == nullptr) {
+      log_e("buildHexData: malloc failed");
+      return nullptr;
+    }
+  }
+  char *startOfData = (char *)target;
+
+  for (int i = 0; i < length; i++) {
+    sprintf((char *)target, "%.2x", (char)*source);
+    source++;
+    target += 2;
+  }
+
+  // Handle the special case where there was no data.
+  if (length == 0) {
+    *startOfData = 0;
+  }
+
+  return startOfData;
+}  // buildHexData
 
 /**
  * @brief Build a printable string of memory range.
@@ -807,466 +792,403 @@ char* BLEUtils::buildHexData(uint8_t* target, uint8_t* source, uint8_t length) {
  * @param [in] length Length of memory.
  * @return A string representation of a piece of memory.
  */
-std::string BLEUtils::buildPrintData(uint8_t* source, size_t length) {
-	std::string res;
-	for (int i = 0; i < length; i++) {
-		char c = *source;
-		res += (isprint(c) ? c : '.');
-		source++;
-	}
-	return res;
-} // buildPrintData
-
+String BLEUtils::buildPrintData(uint8_t *source, size_t length) {
+  String res;
+  for (int i = 0; i < length; i++) {
+    char c = *source;
+    res += (isprint(c) ? c : '.');
+    source++;
+  }
+  return res;
+}  // buildPrintData
 
 /**
  * @brief Convert a close/disconnect reason to a string.
  * @param [in] reason The close reason.
  * @return A string representation of the reason.
  */
-std::string BLEUtils::gattCloseReasonToString(esp_gatt_conn_reason_t reason) {
-	switch (reason) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_GATT_CONN_UNKNOWN: {
-			return "ESP_GATT_CONN_UNKNOWN";
-		}
-		case ESP_GATT_CONN_L2C_FAILURE: {
-			return "ESP_GATT_CONN_L2C_FAILURE";
-		}
-		case ESP_GATT_CONN_TIMEOUT: {
-			return "ESP_GATT_CONN_TIMEOUT";
-		}
-		case ESP_GATT_CONN_TERMINATE_PEER_USER: {
-			return "ESP_GATT_CONN_TERMINATE_PEER_USER";
-		}
-		case ESP_GATT_CONN_TERMINATE_LOCAL_HOST: {
-			return "ESP_GATT_CONN_TERMINATE_LOCAL_HOST";
-		}
-		case ESP_GATT_CONN_FAIL_ESTABLISH: {
-			return "ESP_GATT_CONN_FAIL_ESTABLISH";
-		}
-		case ESP_GATT_CONN_LMP_TIMEOUT: {
-			return "ESP_GATT_CONN_LMP_TIMEOUT";
-		}
-		case ESP_GATT_CONN_CONN_CANCEL: {
-			return "ESP_GATT_CONN_CONN_CANCEL";
-		}
-		case ESP_GATT_CONN_NONE: {
-			return "ESP_GATT_CONN_NONE";
-		}
+String BLEUtils::gattCloseReasonToString(esp_gatt_conn_reason_t reason) {
+  switch (reason) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_GATT_CONN_UNKNOWN:
+    {
+      return "ESP_GATT_CONN_UNKNOWN";
+    }
+    case ESP_GATT_CONN_L2C_FAILURE:
+    {
+      return "ESP_GATT_CONN_L2C_FAILURE";
+    }
+    case ESP_GATT_CONN_TIMEOUT:
+    {
+      return "ESP_GATT_CONN_TIMEOUT";
+    }
+    case ESP_GATT_CONN_TERMINATE_PEER_USER:
+    {
+      return "ESP_GATT_CONN_TERMINATE_PEER_USER";
+    }
+    case ESP_GATT_CONN_TERMINATE_LOCAL_HOST:
+    {
+      return "ESP_GATT_CONN_TERMINATE_LOCAL_HOST";
+    }
+    case ESP_GATT_CONN_FAIL_ESTABLISH:
+    {
+      return "ESP_GATT_CONN_FAIL_ESTABLISH";
+    }
+    case ESP_GATT_CONN_LMP_TIMEOUT:
+    {
+      return "ESP_GATT_CONN_LMP_TIMEOUT";
+    }
+    case ESP_GATT_CONN_CONN_CANCEL:
+    {
+      return "ESP_GATT_CONN_CONN_CANCEL";
+    }
+    case ESP_GATT_CONN_NONE:
+    {
+      return "ESP_GATT_CONN_NONE";
+    }
 #endif
-		default: {
-			return "Unknown";
-		}
-	}
-} // gattCloseReasonToString
-
-
-std::string BLEUtils::gattClientEventTypeToString(esp_gattc_cb_event_t eventType) {
-	switch (eventType) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_GATTC_ACL_EVT:
-			return "ESP_GATTC_ACL_EVT";
-		case ESP_GATTC_ADV_DATA_EVT:
-			return "ESP_GATTC_ADV_DATA_EVT";
-		case ESP_GATTC_ADV_VSC_EVT:
-			return "ESP_GATTC_ADV_VSC_EVT";
-		case ESP_GATTC_BTH_SCAN_CFG_EVT:
-			return "ESP_GATTC_BTH_SCAN_CFG_EVT";
-		case ESP_GATTC_BTH_SCAN_DIS_EVT:
-			return "ESP_GATTC_BTH_SCAN_DIS_EVT";
-		case ESP_GATTC_BTH_SCAN_ENB_EVT:
-			return "ESP_GATTC_BTH_SCAN_ENB_EVT";
-		case ESP_GATTC_BTH_SCAN_PARAM_EVT:
-			return "ESP_GATTC_BTH_SCAN_PARAM_EVT";
-		case ESP_GATTC_BTH_SCAN_RD_EVT:
-			return "ESP_GATTC_BTH_SCAN_RD_EVT";
-		case ESP_GATTC_BTH_SCAN_THR_EVT:
-			return "ESP_GATTC_BTH_SCAN_THR_EVT";
-		case ESP_GATTC_CANCEL_OPEN_EVT:
-			return "ESP_GATTC_CANCEL_OPEN_EVT";
-		case ESP_GATTC_CFG_MTU_EVT:
-			return "ESP_GATTC_CFG_MTU_EVT";
-		case ESP_GATTC_CLOSE_EVT:
-			return "ESP_GATTC_CLOSE_EVT";
-		case ESP_GATTC_CONGEST_EVT:
-			return "ESP_GATTC_CONGEST_EVT";
-		case ESP_GATTC_CONNECT_EVT:
-			return "ESP_GATTC_CONNECT_EVT";
-		case ESP_GATTC_DISCONNECT_EVT:
-			return "ESP_GATTC_DISCONNECT_EVT";
-		case ESP_GATTC_ENC_CMPL_CB_EVT:
-			return "ESP_GATTC_ENC_CMPL_CB_EVT";
-		case ESP_GATTC_EXEC_EVT:
-			return "ESP_GATTC_EXEC_EVT";
-		//case ESP_GATTC_GET_CHAR_EVT:
-//			return "ESP_GATTC_GET_CHAR_EVT";
-		//case ESP_GATTC_GET_DESCR_EVT:
-//			return "ESP_GATTC_GET_DESCR_EVT";
-		//case ESP_GATTC_GET_INCL_SRVC_EVT:
-//			return "ESP_GATTC_GET_INCL_SRVC_EVT";
-		case ESP_GATTC_MULT_ADV_DATA_EVT:
-			return "ESP_GATTC_MULT_ADV_DATA_EVT";
-		case ESP_GATTC_MULT_ADV_DIS_EVT:
-			return "ESP_GATTC_MULT_ADV_DIS_EVT";
-		case ESP_GATTC_MULT_ADV_ENB_EVT:
-			return "ESP_GATTC_MULT_ADV_ENB_EVT";
-		case ESP_GATTC_MULT_ADV_UPD_EVT:
-			return "ESP_GATTC_MULT_ADV_UPD_EVT";
-		case ESP_GATTC_NOTIFY_EVT:
-			return "ESP_GATTC_NOTIFY_EVT";
-		case ESP_GATTC_OPEN_EVT:
-			return "ESP_GATTC_OPEN_EVT";
-		case ESP_GATTC_PREP_WRITE_EVT:
-			return "ESP_GATTC_PREP_WRITE_EVT";
-		case ESP_GATTC_READ_CHAR_EVT:
-			return "ESP_GATTC_READ_CHAR_EVT";
-		case ESP_GATTC_REG_EVT:
-			return "ESP_GATTC_REG_EVT";
-		case ESP_GATTC_REG_FOR_NOTIFY_EVT:
-			return "ESP_GATTC_REG_FOR_NOTIFY_EVT";
-		case ESP_GATTC_SCAN_FLT_CFG_EVT:
-			return "ESP_GATTC_SCAN_FLT_CFG_EVT";
-		case ESP_GATTC_SCAN_FLT_PARAM_EVT:
-			return "ESP_GATTC_SCAN_FLT_PARAM_EVT";
-		case ESP_GATTC_SCAN_FLT_STATUS_EVT:
-			return "ESP_GATTC_SCAN_FLT_STATUS_EVT";
-		case ESP_GATTC_SEARCH_CMPL_EVT:
-			return "ESP_GATTC_SEARCH_CMPL_EVT";
-		case ESP_GATTC_SEARCH_RES_EVT:
-			return "ESP_GATTC_SEARCH_RES_EVT";
-		case ESP_GATTC_SRVC_CHG_EVT:
-			return "ESP_GATTC_SRVC_CHG_EVT";
-		case ESP_GATTC_READ_DESCR_EVT:
-			return "ESP_GATTC_READ_DESCR_EVT";
-		case ESP_GATTC_UNREG_EVT:
-			return "ESP_GATTC_UNREG_EVT";
-		case ESP_GATTC_UNREG_FOR_NOTIFY_EVT:
-			return "ESP_GATTC_UNREG_FOR_NOTIFY_EVT";
-		case ESP_GATTC_WRITE_CHAR_EVT:
-			return "ESP_GATTC_WRITE_CHAR_EVT";
-		case ESP_GATTC_WRITE_DESCR_EVT:
-			return "ESP_GATTC_WRITE_DESCR_EVT";
+    default:
+    {
+      return "Unknown";
+    }
+  }
+}  // gattCloseReasonToString
+
+String BLEUtils::gattClientEventTypeToString(esp_gattc_cb_event_t eventType) {
+  switch (eventType) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_GATTC_ACL_EVT:            return "ESP_GATTC_ACL_EVT";
+    case ESP_GATTC_ADV_DATA_EVT:       return "ESP_GATTC_ADV_DATA_EVT";
+    case ESP_GATTC_ADV_VSC_EVT:        return "ESP_GATTC_ADV_VSC_EVT";
+    case ESP_GATTC_BTH_SCAN_CFG_EVT:   return "ESP_GATTC_BTH_SCAN_CFG_EVT";
+    case ESP_GATTC_BTH_SCAN_DIS_EVT:   return "ESP_GATTC_BTH_SCAN_DIS_EVT";
+    case ESP_GATTC_BTH_SCAN_ENB_EVT:   return "ESP_GATTC_BTH_SCAN_ENB_EVT";
+    case ESP_GATTC_BTH_SCAN_PARAM_EVT: return "ESP_GATTC_BTH_SCAN_PARAM_EVT";
+    case ESP_GATTC_BTH_SCAN_RD_EVT:    return "ESP_GATTC_BTH_SCAN_RD_EVT";
+    case ESP_GATTC_BTH_SCAN_THR_EVT:   return "ESP_GATTC_BTH_SCAN_THR_EVT";
+    case ESP_GATTC_CANCEL_OPEN_EVT:    return "ESP_GATTC_CANCEL_OPEN_EVT";
+    case ESP_GATTC_CFG_MTU_EVT:        return "ESP_GATTC_CFG_MTU_EVT";
+    case ESP_GATTC_CLOSE_EVT:          return "ESP_GATTC_CLOSE_EVT";
+    case ESP_GATTC_CONGEST_EVT:        return "ESP_GATTC_CONGEST_EVT";
+    case ESP_GATTC_CONNECT_EVT:        return "ESP_GATTC_CONNECT_EVT";
+    case ESP_GATTC_DISCONNECT_EVT:     return "ESP_GATTC_DISCONNECT_EVT";
+    case ESP_GATTC_ENC_CMPL_CB_EVT:    return "ESP_GATTC_ENC_CMPL_CB_EVT";
+    case ESP_GATTC_EXEC_EVT:
+      return "ESP_GATTC_EXEC_EVT";
+      //case ESP_GATTC_GET_CHAR_EVT:
+      //			return "ESP_GATTC_GET_CHAR_EVT";
+      //case ESP_GATTC_GET_DESCR_EVT:
+      //			return "ESP_GATTC_GET_DESCR_EVT";
+      //case ESP_GATTC_GET_INCL_SRVC_EVT:
+      //			return "ESP_GATTC_GET_INCL_SRVC_EVT";
+    case ESP_GATTC_MULT_ADV_DATA_EVT:    return "ESP_GATTC_MULT_ADV_DATA_EVT";
+    case ESP_GATTC_MULT_ADV_DIS_EVT:     return "ESP_GATTC_MULT_ADV_DIS_EVT";
+    case ESP_GATTC_MULT_ADV_ENB_EVT:     return "ESP_GATTC_MULT_ADV_ENB_EVT";
+    case ESP_GATTC_MULT_ADV_UPD_EVT:     return "ESP_GATTC_MULT_ADV_UPD_EVT";
+    case ESP_GATTC_NOTIFY_EVT:           return "ESP_GATTC_NOTIFY_EVT";
+    case ESP_GATTC_OPEN_EVT:             return "ESP_GATTC_OPEN_EVT";
+    case ESP_GATTC_PREP_WRITE_EVT:       return "ESP_GATTC_PREP_WRITE_EVT";
+    case ESP_GATTC_READ_CHAR_EVT:        return "ESP_GATTC_READ_CHAR_EVT";
+    case ESP_GATTC_REG_EVT:              return "ESP_GATTC_REG_EVT";
+    case ESP_GATTC_REG_FOR_NOTIFY_EVT:   return "ESP_GATTC_REG_FOR_NOTIFY_EVT";
+    case ESP_GATTC_SCAN_FLT_CFG_EVT:     return "ESP_GATTC_SCAN_FLT_CFG_EVT";
+    case ESP_GATTC_SCAN_FLT_PARAM_EVT:   return "ESP_GATTC_SCAN_FLT_PARAM_EVT";
+    case ESP_GATTC_SCAN_FLT_STATUS_EVT:  return "ESP_GATTC_SCAN_FLT_STATUS_EVT";
+    case ESP_GATTC_SEARCH_CMPL_EVT:      return "ESP_GATTC_SEARCH_CMPL_EVT";
+    case ESP_GATTC_SEARCH_RES_EVT:       return "ESP_GATTC_SEARCH_RES_EVT";
+    case ESP_GATTC_SRVC_CHG_EVT:         return "ESP_GATTC_SRVC_CHG_EVT";
+    case ESP_GATTC_READ_DESCR_EVT:       return "ESP_GATTC_READ_DESCR_EVT";
+    case ESP_GATTC_UNREG_EVT:            return "ESP_GATTC_UNREG_EVT";
+    case ESP_GATTC_UNREG_FOR_NOTIFY_EVT: return "ESP_GATTC_UNREG_FOR_NOTIFY_EVT";
+    case ESP_GATTC_WRITE_CHAR_EVT:       return "ESP_GATTC_WRITE_CHAR_EVT";
+    case ESP_GATTC_WRITE_DESCR_EVT:      return "ESP_GATTC_WRITE_DESCR_EVT";
 #endif
-		default:
-			log_v("Unknown GATT Client event type: %d", eventType);
-			return "Unknown";
-	}
-} // gattClientEventTypeToString
-
+    default: log_v("Unknown GATT Client event type: %d", eventType); return "Unknown";
+  }
+}  // gattClientEventTypeToString
 
 /**
  * @brief Return a string representation of a GATT server event code.
  * @param [in] eventType A GATT server event code.
  * @return A string representation of the GATT server event code.
  */
-std::string BLEUtils::gattServerEventTypeToString(esp_gatts_cb_event_t eventType) {
-	switch (eventType) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_GATTS_REG_EVT:
-			return "ESP_GATTS_REG_EVT";
-		case ESP_GATTS_READ_EVT:
-			return "ESP_GATTS_READ_EVT";
-		case ESP_GATTS_WRITE_EVT:
-			return "ESP_GATTS_WRITE_EVT";
-		case ESP_GATTS_EXEC_WRITE_EVT:
-			return "ESP_GATTS_EXEC_WRITE_EVT";
-		case ESP_GATTS_MTU_EVT:
-			return "ESP_GATTS_MTU_EVT";
-		case ESP_GATTS_CONF_EVT:
-			return "ESP_GATTS_CONF_EVT";
-		case ESP_GATTS_UNREG_EVT:
-			return "ESP_GATTS_UNREG_EVT";
-		case ESP_GATTS_CREATE_EVT:
-			return "ESP_GATTS_CREATE_EVT";
-		case ESP_GATTS_ADD_INCL_SRVC_EVT:
-			return "ESP_GATTS_ADD_INCL_SRVC_EVT";
-		case ESP_GATTS_ADD_CHAR_EVT:
-			return "ESP_GATTS_ADD_CHAR_EVT";
-		case ESP_GATTS_ADD_CHAR_DESCR_EVT:
-			return "ESP_GATTS_ADD_CHAR_DESCR_EVT";
-		case ESP_GATTS_DELETE_EVT:
-			return "ESP_GATTS_DELETE_EVT";
-		case ESP_GATTS_START_EVT:
-			return "ESP_GATTS_START_EVT";
-		case ESP_GATTS_STOP_EVT:
-			return "ESP_GATTS_STOP_EVT";
-		case ESP_GATTS_CONNECT_EVT:
-			return "ESP_GATTS_CONNECT_EVT";
-		case ESP_GATTS_DISCONNECT_EVT:
-			return "ESP_GATTS_DISCONNECT_EVT";
-		case ESP_GATTS_OPEN_EVT:
-			return "ESP_GATTS_OPEN_EVT";
-		case ESP_GATTS_CANCEL_OPEN_EVT:
-			return "ESP_GATTS_CANCEL_OPEN_EVT";
-		case ESP_GATTS_CLOSE_EVT:
-			return "ESP_GATTS_CLOSE_EVT";
-		case ESP_GATTS_LISTEN_EVT:
-			return "ESP_GATTS_LISTEN_EVT";
-		case ESP_GATTS_CONGEST_EVT:
-			return "ESP_GATTS_CONGEST_EVT";
-		case ESP_GATTS_RESPONSE_EVT:
-			return "ESP_GATTS_RESPONSE_EVT";
-		case ESP_GATTS_CREAT_ATTR_TAB_EVT:
-			return "ESP_GATTS_CREAT_ATTR_TAB_EVT";
-		case ESP_GATTS_SET_ATTR_VAL_EVT:
-			return "ESP_GATTS_SET_ATTR_VAL_EVT";
-		case ESP_GATTS_SEND_SERVICE_CHANGE_EVT:
-			return "ESP_GATTS_SEND_SERVICE_CHANGE_EVT";
+String BLEUtils::gattServerEventTypeToString(esp_gatts_cb_event_t eventType) {
+  switch (eventType) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_GATTS_REG_EVT:                 return "ESP_GATTS_REG_EVT";
+    case ESP_GATTS_READ_EVT:                return "ESP_GATTS_READ_EVT";
+    case ESP_GATTS_WRITE_EVT:               return "ESP_GATTS_WRITE_EVT";
+    case ESP_GATTS_EXEC_WRITE_EVT:          return "ESP_GATTS_EXEC_WRITE_EVT";
+    case ESP_GATTS_MTU_EVT:                 return "ESP_GATTS_MTU_EVT";
+    case ESP_GATTS_CONF_EVT:                return "ESP_GATTS_CONF_EVT";
+    case ESP_GATTS_UNREG_EVT:               return "ESP_GATTS_UNREG_EVT";
+    case ESP_GATTS_CREATE_EVT:              return "ESP_GATTS_CREATE_EVT";
+    case ESP_GATTS_ADD_INCL_SRVC_EVT:       return "ESP_GATTS_ADD_INCL_SRVC_EVT";
+    case ESP_GATTS_ADD_CHAR_EVT:            return "ESP_GATTS_ADD_CHAR_EVT";
+    case ESP_GATTS_ADD_CHAR_DESCR_EVT:      return "ESP_GATTS_ADD_CHAR_DESCR_EVT";
+    case ESP_GATTS_DELETE_EVT:              return "ESP_GATTS_DELETE_EVT";
+    case ESP_GATTS_START_EVT:               return "ESP_GATTS_START_EVT";
+    case ESP_GATTS_STOP_EVT:                return "ESP_GATTS_STOP_EVT";
+    case ESP_GATTS_CONNECT_EVT:             return "ESP_GATTS_CONNECT_EVT";
+    case ESP_GATTS_DISCONNECT_EVT:          return "ESP_GATTS_DISCONNECT_EVT";
+    case ESP_GATTS_OPEN_EVT:                return "ESP_GATTS_OPEN_EVT";
+    case ESP_GATTS_CANCEL_OPEN_EVT:         return "ESP_GATTS_CANCEL_OPEN_EVT";
+    case ESP_GATTS_CLOSE_EVT:               return "ESP_GATTS_CLOSE_EVT";
+    case ESP_GATTS_LISTEN_EVT:              return "ESP_GATTS_LISTEN_EVT";
+    case ESP_GATTS_CONGEST_EVT:             return "ESP_GATTS_CONGEST_EVT";
+    case ESP_GATTS_RESPONSE_EVT:            return "ESP_GATTS_RESPONSE_EVT";
+    case ESP_GATTS_CREAT_ATTR_TAB_EVT:      return "ESP_GATTS_CREAT_ATTR_TAB_EVT";
+    case ESP_GATTS_SET_ATTR_VAL_EVT:        return "ESP_GATTS_SET_ATTR_VAL_EVT";
+    case ESP_GATTS_SEND_SERVICE_CHANGE_EVT: return "ESP_GATTS_SEND_SERVICE_CHANGE_EVT";
 #endif
-		default:
-			return "Unknown";
-	}
-} // gattServerEventTypeToString
-
-
+    default: return "Unknown";
+  }
+}  // gattServerEventTypeToString
 
 /**
  * @brief Convert a BLE device type to a string.
  * @param [in] type The device type.
  */
-const char* BLEUtils::devTypeToString(esp_bt_dev_type_t type) {
-	switch (type) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_BT_DEVICE_TYPE_BREDR:
-			return "ESP_BT_DEVICE_TYPE_BREDR";
-		case ESP_BT_DEVICE_TYPE_BLE:
-			return "ESP_BT_DEVICE_TYPE_BLE";
-		case ESP_BT_DEVICE_TYPE_DUMO:
-			return "ESP_BT_DEVICE_TYPE_DUMO";
+const char *BLEUtils::devTypeToString(esp_bt_dev_type_t type) {
+  switch (type) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_BT_DEVICE_TYPE_BREDR: return "ESP_BT_DEVICE_TYPE_BREDR";
+    case ESP_BT_DEVICE_TYPE_BLE:   return "ESP_BT_DEVICE_TYPE_BLE";
+    case ESP_BT_DEVICE_TYPE_DUMO:  return "ESP_BT_DEVICE_TYPE_DUMO";
 #endif
-		default:
-			return "Unknown";
-	}
-} // devTypeToString
-
+    default: return "Unknown";
+  }
+}  // devTypeToString
 
 /**
  * @brief Dump the GAP event to the log.
  */
-void BLEUtils::dumpGapEvent(
-	esp_gap_ble_cb_event_t  event,
-	esp_ble_gap_cb_param_t* param) {
-	log_v("Received a GAP event: %s", gapEventToString(event));
-	switch (event) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		// ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT
-		// adv_data_cmpl
-		// - esp_bt_status_t
-		case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT: {
-			log_v("[status: %d]", param->adv_data_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT
-
-		// ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT
-		//
-		// adv_data_raw_cmpl
-		// - esp_bt_status_t status
-		case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT: {
-			log_v("[status: %d]", param->adv_data_raw_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT
-
-		// ESP_GAP_BLE_ADV_START_COMPLETE_EVT
-		//
-		// adv_start_cmpl
-		// - esp_bt_status_t status
-		case ESP_GAP_BLE_ADV_START_COMPLETE_EVT: {
-			log_v("[status: %d]", param->adv_start_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_ADV_START_COMPLETE_EVT
-
-		// ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT
-		//
-		// adv_stop_cmpl
-		// - esp_bt_status_t status
-		case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT: {
-			log_v("[status: %d]", param->adv_stop_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT
-
-		// ESP_GAP_BLE_AUTH_CMPL_EVT
-		//
-		// auth_cmpl
-		// - esp_bd_addr_t bd_addr
-		// - bool key_present
-		// - esp_link_key key
-		// - bool success
-		// - uint8_t fail_reason
-		// - esp_bd_addr_type_t addr_type
-		// - esp_bt_dev_type_t dev_type
-		case ESP_GAP_BLE_AUTH_CMPL_EVT: {
-			log_v("[bd_addr: %s, key_present: %d, key: ***, key_type: %d, success: %d, fail_reason: %d, addr_type: ***, dev_type: %s]",
-				BLEAddress(param->ble_security.auth_cmpl.bd_addr).toString().c_str(),
-				param->ble_security.auth_cmpl.key_present,
-				param->ble_security.auth_cmpl.key_type,
-				param->ble_security.auth_cmpl.success,
-				param->ble_security.auth_cmpl.fail_reason,
-				BLEUtils::devTypeToString(param->ble_security.auth_cmpl.dev_type)
-			);
-			break;
-		} // ESP_GAP_BLE_AUTH_CMPL_EVT
-
-		// ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT
-		//
-		// clear_bond_dev_cmpl
-		// - esp_bt_status_t status
-		case ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT: {
-			log_v("[status: %d]", param->clear_bond_dev_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT
-
-		// ESP_GAP_BLE_LOCAL_IR_EVT
-		case ESP_GAP_BLE_LOCAL_IR_EVT: {
-			break;
-		} // ESP_GAP_BLE_LOCAL_IR_EVT
-
-		// ESP_GAP_BLE_LOCAL_ER_EVT
-		case ESP_GAP_BLE_LOCAL_ER_EVT: {
-			break;
-		} // ESP_GAP_BLE_LOCAL_ER_EVT
-
-		// ESP_GAP_BLE_NC_REQ_EVT
-		case ESP_GAP_BLE_NC_REQ_EVT: {
-			log_v("[bd_addr: %s, passkey: %d]",
-				BLEAddress(param->ble_security.key_notif.bd_addr).toString().c_str(),
-				param->ble_security.key_notif.passkey);
-			break;
-		} // ESP_GAP_BLE_NC_REQ_EVT
-
-		// ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT
-		//
-		// read_rssi_cmpl
-		// - esp_bt_status_t status
-		// - int8_t rssi
-		// - esp_bd_addr_t remote_addr
-		case ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT: {
-			log_v("[status: %d, rssi: %d, remote_addr: %s]",
-					param->read_rssi_cmpl.status,
-					param->read_rssi_cmpl.rssi,
-					BLEAddress(param->read_rssi_cmpl.remote_addr).toString().c_str()
-			);
-			break;
-		} // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT
-
-		// ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT
-		//
-		// scan_param_cmpl.
-		// - esp_bt_status_t status
-		case ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT: {
-			log_v("[status: %d]", param->scan_param_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT
-
-		// ESP_GAP_BLE_SCAN_RESULT_EVT
-		//
-		// scan_rst:
-		// - search_evt
-		// - bda
-		// - dev_type
-		// - ble_addr_type
-		// - ble_evt_type
-		// - rssi
-		// - ble_adv
-		// - flag
-		// - num_resps
-		// - adv_data_len
-		// - scan_rsp_len
-		case ESP_GAP_BLE_SCAN_RESULT_EVT: {
-			switch (param->scan_rst.search_evt) {
-				case ESP_GAP_SEARCH_INQ_RES_EVT: {
-					log_v("search_evt: %s, bda: %s, dev_type: %s, ble_addr_type: %s, ble_evt_type: %s, rssi: %d, ble_adv: ??, flag: %d (%s), num_resps: %d, adv_data_len: %d, scan_rsp_len: %d",
-						searchEventTypeToString(param->scan_rst.search_evt),
-						BLEAddress(param->scan_rst.bda).toString().c_str(),
-						devTypeToString(param->scan_rst.dev_type),
-						addressTypeToString(param->scan_rst.ble_addr_type),
-						eventTypeToString(param->scan_rst.ble_evt_type),
-						param->scan_rst.rssi,
-						param->scan_rst.flag,
-						adFlagsToString(param->scan_rst.flag).c_str(),
-						param->scan_rst.num_resps,
-						param->scan_rst.adv_data_len,
-						param->scan_rst.scan_rsp_len
-					);
-					break;
-				} // ESP_GAP_SEARCH_INQ_RES_EVT
-
-				default: {
-					log_v("search_evt: %s",searchEventTypeToString(param->scan_rst.search_evt));
-					break;
-				}
-			}
-			break;
-		} // ESP_GAP_BLE_SCAN_RESULT_EVT
-
-		// ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT
-		//
-		// scan_rsp_data_cmpl
-		// - esp_bt_status_t status
-		case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT: {
-			log_v("[status: %d]", param->scan_rsp_data_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT
-
-		// ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT
-		case ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT: {
-			log_v("[status: %d]", param->scan_rsp_data_raw_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT
-
-		// ESP_GAP_BLE_SCAN_START_COMPLETE_EVT
-		//
-		// scan_start_cmpl
-		// - esp_bt_status_t status
-		case ESP_GAP_BLE_SCAN_START_COMPLETE_EVT: {
-			log_v("[status: %d]", param->scan_start_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_SCAN_START_COMPLETE_EVT
-
-		// ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT
-		//
-		// scan_stop_cmpl
-		// - esp_bt_status_t status
-		case ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT: {
-			log_v("[status: %d]", param->scan_stop_cmpl.status);
-			break;
-		} // ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT
-
-		// ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT
-		//
-		// update_conn_params
-		// - esp_bt_status_t status
-		// - esp_bd_addr_t bda
-		// - uint16_t min_int
-		// - uint16_t max_int
-		// - uint16_t latency
-		// - uint16_t conn_int
-		// - uint16_t timeout
-		case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT: {
-			log_v("[status: %d, bd_addr: %s, min_int: %d, max_int: %d, latency: %d, conn_int: %d, timeout: %d]",
-				param->update_conn_params.status,
-				BLEAddress(param->update_conn_params.bda).toString().c_str(),
-				param->update_conn_params.min_int,
-				param->update_conn_params.max_int,
-				param->update_conn_params.latency,
-				param->update_conn_params.conn_int,
-				param->update_conn_params.timeout
-			);
-			break;
-		} // ESP_GAP_BLE_SCAN_UPDATE_CONN_PARAMS_EVT
-
-		// ESP_GAP_BLE_SEC_REQ_EVT
-		case ESP_GAP_BLE_SEC_REQ_EVT: {
-			log_v("[bd_addr: %s]", BLEAddress(param->ble_security.ble_req.bd_addr).toString().c_str());
-			break;
-		} // ESP_GAP_BLE_SEC_REQ_EVT
+void BLEUtils::dumpGapEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) {
+  log_v("Received a GAP event: %s", gapEventToString(event));
+  switch (event) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    // ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT
+    // adv_data_cmpl
+    // - esp_bt_status_t
+    case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->adv_data_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT
+
+    // ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT
+    //
+    // adv_data_raw_cmpl
+    // - esp_bt_status_t status
+    case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->adv_data_raw_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT
+
+    // ESP_GAP_BLE_ADV_START_COMPLETE_EVT
+    //
+    // adv_start_cmpl
+    // - esp_bt_status_t status
+    case ESP_GAP_BLE_ADV_START_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->adv_start_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_ADV_START_COMPLETE_EVT
+
+    // ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT
+    //
+    // adv_stop_cmpl
+    // - esp_bt_status_t status
+    case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->adv_stop_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT
+
+    // ESP_GAP_BLE_AUTH_CMPL_EVT
+    //
+    // auth_cmpl
+    // - esp_bd_addr_t bd_addr
+    // - bool key_present
+    // - esp_link_key key
+    // - bool success
+    // - uint8_t fail_reason
+    // - esp_bd_addr_type_t addr_type
+    // - esp_bt_dev_type_t dev_type
+    case ESP_GAP_BLE_AUTH_CMPL_EVT:
+    {
+      log_v(
+        "[bd_addr: %s, key_present: %d, key: ***, key_type: %d, success: %d, fail_reason: %d, addr_type: ***, dev_type: %s]",
+        BLEAddress(param->ble_security.auth_cmpl.bd_addr).toString().c_str(), param->ble_security.auth_cmpl.key_present, param->ble_security.auth_cmpl.key_type,
+        param->ble_security.auth_cmpl.success, param->ble_security.auth_cmpl.fail_reason, BLEUtils::devTypeToString(param->ble_security.auth_cmpl.dev_type)
+      );
+      break;
+    }  // ESP_GAP_BLE_AUTH_CMPL_EVT
+
+    // ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT
+    //
+    // clear_bond_dev_cmpl
+    // - esp_bt_status_t status
+    case ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->clear_bond_dev_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT
+
+    // ESP_GAP_BLE_LOCAL_IR_EVT
+    case ESP_GAP_BLE_LOCAL_IR_EVT:
+    {
+      break;
+    }  // ESP_GAP_BLE_LOCAL_IR_EVT
+
+    // ESP_GAP_BLE_LOCAL_ER_EVT
+    case ESP_GAP_BLE_LOCAL_ER_EVT:
+    {
+      break;
+    }  // ESP_GAP_BLE_LOCAL_ER_EVT
+
+    // ESP_GAP_BLE_NC_REQ_EVT
+    case ESP_GAP_BLE_NC_REQ_EVT:
+    {
+      log_v("[bd_addr: %s, passkey: %d]", BLEAddress(param->ble_security.key_notif.bd_addr).toString().c_str(), param->ble_security.key_notif.passkey);
+      break;
+    }  // ESP_GAP_BLE_NC_REQ_EVT
+
+    // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT
+    //
+    // read_rssi_cmpl
+    // - esp_bt_status_t status
+    // - int8_t rssi
+    // - esp_bd_addr_t remote_addr
+    case ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT:
+    {
+      log_v(
+        "[status: %d, rssi: %d, remote_addr: %s]", param->read_rssi_cmpl.status, param->read_rssi_cmpl.rssi,
+        BLEAddress(param->read_rssi_cmpl.remote_addr).toString().c_str()
+      );
+      break;
+    }  // ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT
+
+    // ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT
+    //
+    // scan_param_cmpl.
+    // - esp_bt_status_t status
+    case ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->scan_param_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT
+
+    // ESP_GAP_BLE_SCAN_RESULT_EVT
+    //
+    // scan_rst:
+    // - search_evt
+    // - bda
+    // - dev_type
+    // - ble_addr_type
+    // - ble_evt_type
+    // - rssi
+    // - ble_adv
+    // - flag
+    // - num_resps
+    // - adv_data_len
+    // - scan_rsp_len
+    case ESP_GAP_BLE_SCAN_RESULT_EVT:
+    {
+      switch (param->scan_rst.search_evt) {
+        case ESP_GAP_SEARCH_INQ_RES_EVT:
+        {
+          log_v(
+            "search_evt: %s, bda: %s, dev_type: %s, ble_addr_type: %s, ble_evt_type: %s, rssi: %d, ble_adv: ??, flag: %d (%s), num_resps: %d, adv_data_len: "
+            "%d, scan_rsp_len: %d",
+            searchEventTypeToString(param->scan_rst.search_evt), BLEAddress(param->scan_rst.bda).toString().c_str(), devTypeToString(param->scan_rst.dev_type),
+            addressTypeToString(param->scan_rst.ble_addr_type), eventTypeToString(param->scan_rst.ble_evt_type), param->scan_rst.rssi, param->scan_rst.flag,
+            adFlagsToString(param->scan_rst.flag).c_str(), param->scan_rst.num_resps, param->scan_rst.adv_data_len, param->scan_rst.scan_rsp_len
+          );
+          break;
+        }  // ESP_GAP_SEARCH_INQ_RES_EVT
+
+        default:
+        {
+          log_v("search_evt: %s", searchEventTypeToString(param->scan_rst.search_evt));
+          break;
+        }
+      }
+      break;
+    }  // ESP_GAP_BLE_SCAN_RESULT_EVT
+
+    // ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT
+    //
+    // scan_rsp_data_cmpl
+    // - esp_bt_status_t status
+    case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->scan_rsp_data_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT
+
+    // ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT
+    case ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->scan_rsp_data_raw_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT
+
+    // ESP_GAP_BLE_SCAN_START_COMPLETE_EVT
+    //
+    // scan_start_cmpl
+    // - esp_bt_status_t status
+    case ESP_GAP_BLE_SCAN_START_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->scan_start_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_SCAN_START_COMPLETE_EVT
+
+    // ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT
+    //
+    // scan_stop_cmpl
+    // - esp_bt_status_t status
+    case ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT:
+    {
+      log_v("[status: %d]", param->scan_stop_cmpl.status);
+      break;
+    }  // ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT
+
+    // ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT
+    //
+    // update_conn_params
+    // - esp_bt_status_t status
+    // - esp_bd_addr_t bda
+    // - uint16_t min_int
+    // - uint16_t max_int
+    // - uint16_t latency
+    // - uint16_t conn_int
+    // - uint16_t timeout
+    case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT:
+    {
+      log_v(
+        "[status: %d, bd_addr: %s, min_int: %d, max_int: %d, latency: %d, conn_int: %d, timeout: %d]", param->update_conn_params.status,
+        BLEAddress(param->update_conn_params.bda).toString().c_str(), param->update_conn_params.min_int, param->update_conn_params.max_int,
+        param->update_conn_params.latency, param->update_conn_params.conn_int, param->update_conn_params.timeout
+      );
+      break;
+    }  // ESP_GAP_BLE_SCAN_UPDATE_CONN_PARAMS_EVT
+
+    // ESP_GAP_BLE_SEC_REQ_EVT
+    case ESP_GAP_BLE_SEC_REQ_EVT:
+    {
+      log_v("[bd_addr: %s]", BLEAddress(param->ble_security.ble_req.bd_addr).toString().c_str());
+      break;
+    }  // ESP_GAP_BLE_SEC_REQ_EVT
 #endif
-		default: {
-			log_v("*** dumpGapEvent: Logger not coded ***");
-			break;
-		} // default
-	} // switch
-} // dumpGapEvent
-
+    default:
+    {
+      log_v("*** dumpGapEvent: Logger not coded ***");
+      break;
+    }  // default
+  }  // switch
+}  // dumpGapEvent
 
 /**
  * @brief Decode and dump a GATT client event
@@ -1274,74 +1196,70 @@ void BLEUtils::dumpGapEvent(
  * @param [in] event The type of event received.
  * @param [in] evtParam The data associated with the event.
  */
-void BLEUtils::dumpGattClientEvent(
-	esp_gattc_cb_event_t      event,
-	esp_gatt_if_t             gattc_if,
-	esp_ble_gattc_cb_param_t* evtParam) {
-
-	//esp_ble_gattc_cb_param_t* evtParam = (esp_ble_gattc_cb_param_t*) param;
-	log_v("GATT Event: %s", BLEUtils::gattClientEventTypeToString(event).c_str());
-	switch (event) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		// ESP_GATTC_CLOSE_EVT
-		//
-		// close:
-		// - esp_gatt_status_t      status
-		// - uint16_t               conn_id
-		// - esp_bd_addr_t          remote_bda
-		// - esp_gatt_conn_reason_t reason
-		case ESP_GATTC_CLOSE_EVT: {
-			log_v("[status: %s, reason:%s, conn_id: %d]",
-				BLEUtils::gattStatusToString(evtParam->close.status).c_str(),
-				BLEUtils::gattCloseReasonToString(evtParam->close.reason).c_str(),
-				evtParam->close.conn_id);
-			break;
-		}
-
-		// ESP_GATTC_CONNECT_EVT
-		//
-		// connect:
-		// - esp_gatt_status_t status
-		// - uint16_t          conn_id
-		// - esp_bd_addr_t     remote_bda
-		case ESP_GATTC_CONNECT_EVT: {
-			log_v("[conn_id: %d, remote_bda: %s]",
-				evtParam->connect.conn_id,
-				BLEAddress(evtParam->connect.remote_bda).toString().c_str()
-			);
-			break;
-		}
-
-		// ESP_GATTC_DISCONNECT_EVT
-		//
-		// disconnect:
-		// - esp_gatt_conn_reason_t reason
-		// - uint16_t               conn_id
-		// - esp_bd_addr_t          remote_bda
-		case ESP_GATTC_DISCONNECT_EVT: {
-			log_v("[reason: %s, conn_id: %d, remote_bda: %s]",
-				BLEUtils::gattCloseReasonToString(evtParam->disconnect.reason).c_str(),
-				evtParam->disconnect.conn_id,
-				BLEAddress(evtParam->disconnect.remote_bda).toString().c_str()
-			);
-			break;
-		} // ESP_GATTC_DISCONNECT_EVT
-
-		// ESP_GATTC_GET_CHAR_EVT
-		//
-		// get_char:
-		// - esp_gatt_status_t    status
-		// - uin1t6_t             conn_id
-		// - esp_gatt_srvc_id_t   srvc_id
-		// - esp_gatt_id_t        char_id
-		// - esp_gatt_char_prop_t char_prop
-		/*
+void BLEUtils::dumpGattClientEvent(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam) {
+
+  //esp_ble_gattc_cb_param_t* evtParam = (esp_ble_gattc_cb_param_t*) param;
+  log_v("GATT Event: %s", BLEUtils::gattClientEventTypeToString(event).c_str());
+  switch (event) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    // ESP_GATTC_CLOSE_EVT
+    //
+    // close:
+    // - esp_gatt_status_t      status
+    // - uint16_t               conn_id
+    // - esp_bd_addr_t          remote_bda
+    // - esp_gatt_conn_reason_t reason
+    case ESP_GATTC_CLOSE_EVT:
+    {
+      log_v(
+        "[status: %s, reason:%s, conn_id: %d]", BLEUtils::gattStatusToString(evtParam->close.status).c_str(),
+        BLEUtils::gattCloseReasonToString(evtParam->close.reason).c_str(), evtParam->close.conn_id
+      );
+      break;
+    }
+
+    // ESP_GATTC_CONNECT_EVT
+    //
+    // connect:
+    // - esp_gatt_status_t status
+    // - uint16_t          conn_id
+    // - esp_bd_addr_t     remote_bda
+    case ESP_GATTC_CONNECT_EVT:
+    {
+      log_v("[conn_id: %d, remote_bda: %s]", evtParam->connect.conn_id, BLEAddress(evtParam->connect.remote_bda).toString().c_str());
+      break;
+    }
+
+    // ESP_GATTC_DISCONNECT_EVT
+    //
+    // disconnect:
+    // - esp_gatt_conn_reason_t reason
+    // - uint16_t               conn_id
+    // - esp_bd_addr_t          remote_bda
+    case ESP_GATTC_DISCONNECT_EVT:
+    {
+      log_v(
+        "[reason: %s, conn_id: %d, remote_bda: %s]", BLEUtils::gattCloseReasonToString(evtParam->disconnect.reason).c_str(), evtParam->disconnect.conn_id,
+        BLEAddress(evtParam->disconnect.remote_bda).toString().c_str()
+      );
+      break;
+    }  // ESP_GATTC_DISCONNECT_EVT
+
+    // ESP_GATTC_GET_CHAR_EVT
+    //
+    // get_char:
+    // - esp_gatt_status_t    status
+    // - uin1t6_t             conn_id
+    // - esp_gatt_srvc_id_t   srvc_id
+    // - esp_gatt_id_t        char_id
+    // - esp_gatt_char_prop_t char_prop
+    /*
 		case ESP_GATTC_GET_CHAR_EVT: {
 
 			// If the status of the event shows that we have a value other than ESP_GATT_OK then the
 			// characteristic fields are not set to a usable value .. so don't try and log them.
 			if (evtParam->get_char.status == ESP_GATT_OK) {
-				std::string description = "Unknown";
+				String description = "Unknown";
 				if (evtParam->get_char.char_id.uuid.len == ESP_UUID_LEN_16) {
 					description = BLEUtils::gattCharacteristicUUIDToString(evtParam->get_char.char_id.uuid.uuid.uuid16);
 				}
@@ -1364,154 +1282,143 @@ void BLEUtils::dumpGattClientEvent(
 		} // ESP_GATTC_GET_CHAR_EVT
 		*/
 
-		// ESP_GATTC_NOTIFY_EVT
-		//
-		// notify
-		// uint16_t           conn_id
-		// esp_bd_addr_t      remote_bda
-		// handle             handle
-		// uint16_t           value_len
-		// uint8_t*           value
-		// bool               is_notify
-		//
-		case ESP_GATTC_NOTIFY_EVT: {
-			log_v("[conn_id: %d, remote_bda: %s, handle: %d 0x%.2x, value_len: %d, is_notify: %d]",
-				evtParam->notify.conn_id,
-				BLEAddress(evtParam->notify.remote_bda).toString().c_str(),
-				evtParam->notify.handle,
-				evtParam->notify.handle,
-				evtParam->notify.value_len,
-				evtParam->notify.is_notify
-			);
-			break;
-		}
-
-		// ESP_GATTC_OPEN_EVT
-		//
-		// open:
-		// - esp_gatt_status_t status
-		// - uint16_t          conn_id
-		// - esp_bd_addr_t     remote_bda
-		// - uint16_t          mtu
-		//
-		case ESP_GATTC_OPEN_EVT: {
-			log_v("[status: %s, conn_id: %d, remote_bda: %s, mtu: %d]",
-				BLEUtils::gattStatusToString(evtParam->open.status).c_str(),
-				evtParam->open.conn_id,
-				BLEAddress(evtParam->open.remote_bda).toString().c_str(),
-				evtParam->open.mtu);
-			break;
-		} // ESP_GATTC_OPEN_EVT
-
-		// ESP_GATTC_READ_CHAR_EVT
-		//
-		// Callback to indicate that requested data that we wanted to read is now available.
-		//
-		// read:
-		// esp_gatt_status_t  status
-		// uint16_t           conn_id
-		// uint16_t           handle
-		// uint8_t*           value
-		// uint16_t           value_type
-		// uint16_t           value_len
-		case ESP_GATTC_READ_CHAR_EVT: {
-			log_v("[status: %s, conn_id: %d, handle: %d 0x%.2x, value_len: %d]",
-				BLEUtils::gattStatusToString(evtParam->read.status).c_str(),
-				evtParam->read.conn_id,
-				evtParam->read.handle,
-				evtParam->read.handle,
-				evtParam->read.value_len
-			);
-			if (evtParam->read.status == ESP_GATT_OK) {
-				GeneralUtils::hexDump(evtParam->read.value, evtParam->read.value_len);
-				/*
+    // ESP_GATTC_NOTIFY_EVT
+    //
+    // notify
+    // uint16_t           conn_id
+    // esp_bd_addr_t      remote_bda
+    // handle             handle
+    // uint16_t           value_len
+    // uint8_t*           value
+    // bool               is_notify
+    //
+    case ESP_GATTC_NOTIFY_EVT:
+    {
+      log_v(
+        "[conn_id: %d, remote_bda: %s, handle: %d 0x%.2x, value_len: %d, is_notify: %d]", evtParam->notify.conn_id,
+        BLEAddress(evtParam->notify.remote_bda).toString().c_str(), evtParam->notify.handle, evtParam->notify.handle, evtParam->notify.value_len,
+        evtParam->notify.is_notify
+      );
+      break;
+    }
+
+    // ESP_GATTC_OPEN_EVT
+    //
+    // open:
+    // - esp_gatt_status_t status
+    // - uint16_t          conn_id
+    // - esp_bd_addr_t     remote_bda
+    // - uint16_t          mtu
+    //
+    case ESP_GATTC_OPEN_EVT:
+    {
+      log_v(
+        "[status: %s, conn_id: %d, remote_bda: %s, mtu: %d]", BLEUtils::gattStatusToString(evtParam->open.status).c_str(), evtParam->open.conn_id,
+        BLEAddress(evtParam->open.remote_bda).toString().c_str(), evtParam->open.mtu
+      );
+      break;
+    }  // ESP_GATTC_OPEN_EVT
+
+    // ESP_GATTC_READ_CHAR_EVT
+    //
+    // Callback to indicate that requested data that we wanted to read is now available.
+    //
+    // read:
+    // esp_gatt_status_t  status
+    // uint16_t           conn_id
+    // uint16_t           handle
+    // uint8_t*           value
+    // uint16_t           value_type
+    // uint16_t           value_len
+    case ESP_GATTC_READ_CHAR_EVT:
+    {
+      log_v(
+        "[status: %s, conn_id: %d, handle: %d 0x%.2x, value_len: %d]", BLEUtils::gattStatusToString(evtParam->read.status).c_str(), evtParam->read.conn_id,
+        evtParam->read.handle, evtParam->read.handle, evtParam->read.value_len
+      );
+      if (evtParam->read.status == ESP_GATT_OK) {
+        GeneralUtils::hexDump(evtParam->read.value, evtParam->read.value_len);
+        /*
 				char* pHexData = BLEUtils::buildHexData(nullptr, evtParam->read.value, evtParam->read.value_len);
 				log_v("value: %s \"%s\"", pHexData, BLEUtils::buildPrintData(evtParam->read.value, evtParam->read.value_len).c_str());
 				free(pHexData);
 				*/
-			}
-			break;
-		} // ESP_GATTC_READ_CHAR_EVT
-
-		// ESP_GATTC_REG_EVT
-		//
-		// reg:
-		// - esp_gatt_status_t status
-		// - uint16_t          app_id
-		case ESP_GATTC_REG_EVT: {
-			log_v("[status: %s, app_id: 0x%x]",
-				BLEUtils::gattStatusToString(evtParam->reg.status).c_str(),
-				evtParam->reg.app_id);
-			break;
-		} // ESP_GATTC_REG_EVT
-
-		// ESP_GATTC_REG_FOR_NOTIFY_EVT
-		//
-		// reg_for_notify:
-		// - esp_gatt_status_t status
-		// - uint16_t          handle
-		case ESP_GATTC_REG_FOR_NOTIFY_EVT: {
-			log_v("[status: %s, handle: %d 0x%.2x]",
-				BLEUtils::gattStatusToString(evtParam->reg_for_notify.status).c_str(),
-				evtParam->reg_for_notify.handle,
-				evtParam->reg_for_notify.handle
-			);
-			break;
-		} // ESP_GATTC_REG_FOR_NOTIFY_EVT
-
-		// ESP_GATTC_SEARCH_CMPL_EVT
-		//
-		// search_cmpl:
-		// - esp_gatt_status_t status
-		// - uint16_t          conn_id
-		case ESP_GATTC_SEARCH_CMPL_EVT: {
-			log_v("[status: %s, conn_id: %d]",
-				BLEUtils::gattStatusToString(evtParam->search_cmpl.status).c_str(),
-				evtParam->search_cmpl.conn_id);
-			break;
-		} // ESP_GATTC_SEARCH_CMPL_EVT
-
-		// ESP_GATTC_SEARCH_RES_EVT
-		//
-		// search_res:
-		// - uint16_t      conn_id
-		// - uint16_t      start_handle
-		// - uint16_t      end_handle
-		// - esp_gatt_id_t srvc_id
-		case ESP_GATTC_SEARCH_RES_EVT: {
-			log_v("[conn_id: %d, start_handle: %d 0x%.2x, end_handle: %d 0x%.2x, srvc_id: %s",
-				evtParam->search_res.conn_id,
-				evtParam->search_res.start_handle,
-				evtParam->search_res.start_handle,
-				evtParam->search_res.end_handle,
-				evtParam->search_res.end_handle,
-				gattIdToString(evtParam->search_res.srvc_id).c_str());
-			break;
-		} // ESP_GATTC_SEARCH_RES_EVT
-
-		// ESP_GATTC_WRITE_CHAR_EVT
-		//
-		// write:
-		// - esp_gatt_status_t status
-		// - uint16_t          conn_id
-		// - uint16_t          handle
-		// - uint16_t          offset
-		case ESP_GATTC_WRITE_CHAR_EVT: {
-			log_v("[status: %s, conn_id: %d, handle: %d 0x%.2x, offset: %d]",
-				BLEUtils::gattStatusToString(evtParam->write.status).c_str(),
-				evtParam->write.conn_id,
-				evtParam->write.handle,
-				evtParam->write.handle,
-				evtParam->write.offset
-			);
-			break;
-		} // ESP_GATTC_WRITE_CHAR_EVT
+      }
+      break;
+    }  // ESP_GATTC_READ_CHAR_EVT
+
+    // ESP_GATTC_REG_EVT
+    //
+    // reg:
+    // - esp_gatt_status_t status
+    // - uint16_t          app_id
+    case ESP_GATTC_REG_EVT:
+    {
+      log_v("[status: %s, app_id: 0x%x]", BLEUtils::gattStatusToString(evtParam->reg.status).c_str(), evtParam->reg.app_id);
+      break;
+    }  // ESP_GATTC_REG_EVT
+
+    // ESP_GATTC_REG_FOR_NOTIFY_EVT
+    //
+    // reg_for_notify:
+    // - esp_gatt_status_t status
+    // - uint16_t          handle
+    case ESP_GATTC_REG_FOR_NOTIFY_EVT:
+    {
+      log_v(
+        "[status: %s, handle: %d 0x%.2x]", BLEUtils::gattStatusToString(evtParam->reg_for_notify.status).c_str(), evtParam->reg_for_notify.handle,
+        evtParam->reg_for_notify.handle
+      );
+      break;
+    }  // ESP_GATTC_REG_FOR_NOTIFY_EVT
+
+    // ESP_GATTC_SEARCH_CMPL_EVT
+    //
+    // search_cmpl:
+    // - esp_gatt_status_t status
+    // - uint16_t          conn_id
+    case ESP_GATTC_SEARCH_CMPL_EVT:
+    {
+      log_v("[status: %s, conn_id: %d]", BLEUtils::gattStatusToString(evtParam->search_cmpl.status).c_str(), evtParam->search_cmpl.conn_id);
+      break;
+    }  // ESP_GATTC_SEARCH_CMPL_EVT
+
+    // ESP_GATTC_SEARCH_RES_EVT
+    //
+    // search_res:
+    // - uint16_t      conn_id
+    // - uint16_t      start_handle
+    // - uint16_t      end_handle
+    // - esp_gatt_id_t srvc_id
+    case ESP_GATTC_SEARCH_RES_EVT:
+    {
+      log_v(
+        "[conn_id: %d, start_handle: %d 0x%.2x, end_handle: %d 0x%.2x, srvc_id: %s", evtParam->search_res.conn_id, evtParam->search_res.start_handle,
+        evtParam->search_res.start_handle, evtParam->search_res.end_handle, evtParam->search_res.end_handle,
+        gattIdToString(evtParam->search_res.srvc_id).c_str()
+      );
+      break;
+    }  // ESP_GATTC_SEARCH_RES_EVT
+
+    // ESP_GATTC_WRITE_CHAR_EVT
+    //
+    // write:
+    // - esp_gatt_status_t status
+    // - uint16_t          conn_id
+    // - uint16_t          handle
+    // - uint16_t          offset
+    case ESP_GATTC_WRITE_CHAR_EVT:
+    {
+      log_v(
+        "[status: %s, conn_id: %d, handle: %d 0x%.2x, offset: %d]", BLEUtils::gattStatusToString(evtParam->write.status).c_str(), evtParam->write.conn_id,
+        evtParam->write.handle, evtParam->write.handle, evtParam->write.offset
+      );
+      break;
+    }  // ESP_GATTC_WRITE_CHAR_EVT
 #endif
-		default:
-			break;
-	}
-} // dumpGattClientEvent
-
+    default: break;
+  }
+}  // dumpGattClientEvent
 
 /**
  * @brief Dump the details of a GATT server event.
@@ -1523,375 +1430,303 @@ void BLEUtils::dumpGattClientEvent(
  * @param [in] event The event type that was posted.
  * @param [in] evtParam A union of structures only one of which is populated.
  */
-void BLEUtils::dumpGattServerEvent(
-		esp_gatts_cb_event_t      event,
-		esp_gatt_if_t             gatts_if,
-		esp_ble_gatts_cb_param_t* evtParam) {
-	log_v("GATT ServerEvent: %s", BLEUtils::gattServerEventTypeToString(event).c_str());
-	switch (event) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-
-		case ESP_GATTS_ADD_CHAR_DESCR_EVT: {
-			log_v("[status: %s, attr_handle: %d 0x%.2x, service_handle: %d 0x%.2x, char_uuid: %s]",
-				gattStatusToString(evtParam->add_char_descr.status).c_str(),
-				evtParam->add_char_descr.attr_handle,
-				evtParam->add_char_descr.attr_handle,
-				evtParam->add_char_descr.service_handle,
-				evtParam->add_char_descr.service_handle,
-				BLEUUID(evtParam->add_char_descr.descr_uuid).toString().c_str());
-			break;
-		} // ESP_GATTS_ADD_CHAR_DESCR_EVT
-
-		case ESP_GATTS_ADD_CHAR_EVT: {
-			if (evtParam->add_char.status == ESP_GATT_OK) {
-				log_v("[status: %s, attr_handle: %d 0x%.2x, service_handle: %d 0x%.2x, char_uuid: %s]",
-					gattStatusToString(evtParam->add_char.status).c_str(),
-					evtParam->add_char.attr_handle,
-					evtParam->add_char.attr_handle,
-					evtParam->add_char.service_handle,
-					evtParam->add_char.service_handle,
-					BLEUUID(evtParam->add_char.char_uuid).toString().c_str());
-			} else {
-				log_e("[status: %s, attr_handle: %d 0x%.2x, service_handle: %d 0x%.2x, char_uuid: %s]",
-					gattStatusToString(evtParam->add_char.status).c_str(),
-					evtParam->add_char.attr_handle,
-					evtParam->add_char.attr_handle,
-					evtParam->add_char.service_handle,
-					evtParam->add_char.service_handle,
-					BLEUUID(evtParam->add_char.char_uuid).toString().c_str());
-			}
-			break;
-		} // ESP_GATTS_ADD_CHAR_EVT
-
-
-		// ESP_GATTS_CONF_EVT
-		//
-		// conf:
-		// - esp_gatt_status_t status  – The status code.
-		// - uint16_t          conn_id – The connection used.
-		case ESP_GATTS_CONF_EVT: {
-			log_v("[status: %s, conn_id: 0x%.2x]",
-				gattStatusToString(evtParam->conf.status).c_str(),
-				evtParam->conf.conn_id);
-			break;
-		} // ESP_GATTS_CONF_EVT
-
-
-		case ESP_GATTS_CONGEST_EVT: {
-			log_v("[conn_id: %d, congested: %d]",
-				evtParam->congest.conn_id,
-				evtParam->congest.congested);
-			break;
-		} // ESP_GATTS_CONGEST_EVT
-
-		case ESP_GATTS_CONNECT_EVT: {
-			log_v("[conn_id: %d, remote_bda: %s]",
-				evtParam->connect.conn_id,
-				BLEAddress(evtParam->connect.remote_bda).toString().c_str());
-			break;
-		} // ESP_GATTS_CONNECT_EVT
-
-		case ESP_GATTS_CREATE_EVT: {
-			log_v("[status: %s, service_handle: %d 0x%.2x, service_id: [%s]]",
-				gattStatusToString(evtParam->create.status).c_str(),
-				evtParam->create.service_handle,
-				evtParam->create.service_handle,
-				gattServiceIdToString(evtParam->create.service_id).c_str());
-			break;
-		} // ESP_GATTS_CREATE_EVT
-
-		case ESP_GATTS_DISCONNECT_EVT: {
-			log_v("[conn_id: %d, remote_bda: %s]",
-				evtParam->connect.conn_id,
-				BLEAddress(evtParam->connect.remote_bda).toString().c_str());
-			break;
-		} // ESP_GATTS_DISCONNECT_EVT
-
-
-		// ESP_GATTS_EXEC_WRITE_EVT
-		// exec_write:
-		// - uint16_t conn_id
-		// - uint32_t trans_id
-		// - esp_bd_addr_t bda
-		// - uint8_t exec_write_flag
-		case ESP_GATTS_EXEC_WRITE_EVT: {
-			char* pWriteFlagText;
-			switch (evtParam->exec_write.exec_write_flag) {
-				case ESP_GATT_PREP_WRITE_EXEC: {
-					pWriteFlagText = (char*) "WRITE";
-					break;
-				}
-
-				case ESP_GATT_PREP_WRITE_CANCEL: {
-					pWriteFlagText = (char*) "CANCEL";
-					break;
-				}
-
-				default:
-					pWriteFlagText = (char*) "<Unknown>";
-					break;
-			}
-
-			log_v("[conn_id: %d, trans_id: %d, bda: %s, exec_write_flag: 0x%.2x=%s]",
-				evtParam->exec_write.conn_id,
-				evtParam->exec_write.trans_id,
-				BLEAddress(evtParam->exec_write.bda).toString().c_str(),
-				evtParam->exec_write.exec_write_flag,
-				pWriteFlagText);
-			break;
-		} // ESP_GATTS_DISCONNECT_EVT
-
-
-		case ESP_GATTS_MTU_EVT: {
-			log_v("[conn_id: %d, mtu: %d]",
-					evtParam->mtu.conn_id,
-					evtParam->mtu.mtu);
-			break;
-		} // ESP_GATTS_MTU_EVT
-
-		case ESP_GATTS_READ_EVT: {
-			log_v("[conn_id: %d, trans_id: %d, bda: %s, handle: 0x%.2x, is_long: %d, need_rsp:%d]",
-					evtParam->read.conn_id,
-					evtParam->read.trans_id,
-					BLEAddress(evtParam->read.bda).toString().c_str(),
-					evtParam->read.handle,
-					evtParam->read.is_long,
-					evtParam->read.need_rsp);
-			break;
-		} // ESP_GATTS_READ_EVT
-
-		case ESP_GATTS_RESPONSE_EVT: {
-			log_v("[status: %s, handle: 0x%.2x]",
-				gattStatusToString(evtParam->rsp.status).c_str(),
-				evtParam->rsp.handle);
-			break;
-		} // ESP_GATTS_RESPONSE_EVT
-
-		case ESP_GATTS_REG_EVT: {
-			log_v("[status: %s, app_id: %d]",
-				gattStatusToString(evtParam->reg.status).c_str(),
-				evtParam->reg.app_id);
-			break;
-		} // ESP_GATTS_REG_EVT
-
-
-		// ESP_GATTS_START_EVT
-		//
-		// start:
-		// - esp_gatt_status_t status
-		// - uint16_t          service_handle
-		case ESP_GATTS_START_EVT: {
-			log_v("[status: %s, service_handle: 0x%.2x]",
-				gattStatusToString(evtParam->start.status).c_str(),
-				evtParam->start.service_handle);
-			break;
-		} // ESP_GATTS_START_EVT
-
-
-		// ESP_GATTS_WRITE_EVT
-		//
-		// write:
-		// - uint16_t      conn_id  – The connection id.
-		// - uint16_t      trans_id – The transfer id.
-		// - esp_bd_addr_t bda      – The address of the partner.
-		// - uint16_t      handle   – The attribute handle.
-		// - uint16_t      offset   – The offset of the currently received within the whole value.
-		// - bool          need_rsp – Do we need a response?
-		// - bool          is_prep  – Is this a write prepare?  If set, then this is to be considered part of the received value and not the whole value.  A subsequent ESP_GATTS_EXEC_WRITE will mark the total.
-		// - uint16_t      len      – The length of the incoming value part.
-		// - uint8_t*      value    – The data for this value part.
-		case ESP_GATTS_WRITE_EVT: {
-			log_v("[conn_id: %d, trans_id: %d, bda: %s, handle: 0x%.2x, offset: %d, need_rsp: %d, is_prep: %d, len: %d]",
-					evtParam->write.conn_id,
-					evtParam->write.trans_id,
-					BLEAddress(evtParam->write.bda).toString().c_str(),
-					evtParam->write.handle,
-					evtParam->write.offset,
-					evtParam->write.need_rsp,
-					evtParam->write.is_prep,
-					evtParam->write.len);
-			char* pHex = buildHexData(nullptr, evtParam->write.value, evtParam->write.len);
-			log_v("[Data: %s]", pHex);
-			free(pHex);
-			break;
-		} // ESP_GATTS_WRITE_EVT
+void BLEUtils::dumpGattServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *evtParam) {
+  log_v("GATT ServerEvent: %s", BLEUtils::gattServerEventTypeToString(event).c_str());
+  switch (event) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+
+    case ESP_GATTS_ADD_CHAR_DESCR_EVT:
+    {
+      log_v(
+        "[status: %s, attr_handle: %d 0x%.2x, service_handle: %d 0x%.2x, char_uuid: %s]", gattStatusToString(evtParam->add_char_descr.status).c_str(),
+        evtParam->add_char_descr.attr_handle, evtParam->add_char_descr.attr_handle, evtParam->add_char_descr.service_handle,
+        evtParam->add_char_descr.service_handle, BLEUUID(evtParam->add_char_descr.descr_uuid).toString().c_str()
+      );
+      break;
+    }  // ESP_GATTS_ADD_CHAR_DESCR_EVT
+
+    case ESP_GATTS_ADD_CHAR_EVT:
+    {
+      if (evtParam->add_char.status == ESP_GATT_OK) {
+        log_v(
+          "[status: %s, attr_handle: %d 0x%.2x, service_handle: %d 0x%.2x, char_uuid: %s]", gattStatusToString(evtParam->add_char.status).c_str(),
+          evtParam->add_char.attr_handle, evtParam->add_char.attr_handle, evtParam->add_char.service_handle, evtParam->add_char.service_handle,
+          BLEUUID(evtParam->add_char.char_uuid).toString().c_str()
+        );
+      } else {
+        log_e(
+          "[status: %s, attr_handle: %d 0x%.2x, service_handle: %d 0x%.2x, char_uuid: %s]", gattStatusToString(evtParam->add_char.status).c_str(),
+          evtParam->add_char.attr_handle, evtParam->add_char.attr_handle, evtParam->add_char.service_handle, evtParam->add_char.service_handle,
+          BLEUUID(evtParam->add_char.char_uuid).toString().c_str()
+        );
+      }
+      break;
+    }  // ESP_GATTS_ADD_CHAR_EVT
+
+    // ESP_GATTS_CONF_EVT
+    //
+    // conf:
+    // - esp_gatt_status_t status  – The status code.
+    // - uint16_t          conn_id – The connection used.
+    case ESP_GATTS_CONF_EVT:
+    {
+      log_v("[status: %s, conn_id: 0x%.2x]", gattStatusToString(evtParam->conf.status).c_str(), evtParam->conf.conn_id);
+      break;
+    }  // ESP_GATTS_CONF_EVT
+
+    case ESP_GATTS_CONGEST_EVT:
+    {
+      log_v("[conn_id: %d, congested: %d]", evtParam->congest.conn_id, evtParam->congest.congested);
+      break;
+    }  // ESP_GATTS_CONGEST_EVT
+
+    case ESP_GATTS_CONNECT_EVT:
+    {
+      log_v("[conn_id: %d, remote_bda: %s]", evtParam->connect.conn_id, BLEAddress(evtParam->connect.remote_bda).toString().c_str());
+      break;
+    }  // ESP_GATTS_CONNECT_EVT
+
+    case ESP_GATTS_CREATE_EVT:
+    {
+      log_v(
+        "[status: %s, service_handle: %d 0x%.2x, service_id: [%s]]", gattStatusToString(evtParam->create.status).c_str(), evtParam->create.service_handle,
+        evtParam->create.service_handle, gattServiceIdToString(evtParam->create.service_id).c_str()
+      );
+      break;
+    }  // ESP_GATTS_CREATE_EVT
+
+    case ESP_GATTS_DISCONNECT_EVT:
+    {
+      log_v("[conn_id: %d, remote_bda: %s]", evtParam->connect.conn_id, BLEAddress(evtParam->connect.remote_bda).toString().c_str());
+      break;
+    }  // ESP_GATTS_DISCONNECT_EVT
+
+    // ESP_GATTS_EXEC_WRITE_EVT
+    // exec_write:
+    // - uint16_t conn_id
+    // - uint32_t trans_id
+    // - esp_bd_addr_t bda
+    // - uint8_t exec_write_flag
+#ifdef ARDUHAL_LOG_LEVEL_VERBOSE
+    case ESP_GATTS_EXEC_WRITE_EVT:
+    {
+      char *pWriteFlagText;
+      switch (evtParam->exec_write.exec_write_flag) {
+        case ESP_GATT_PREP_WRITE_EXEC:
+        {
+          pWriteFlagText = (char *)"WRITE";
+          break;
+        }
+
+        case ESP_GATT_PREP_WRITE_CANCEL:
+        {
+          pWriteFlagText = (char *)"CANCEL";
+          break;
+        }
+
+        default: pWriteFlagText = (char *)"<Unknown>"; break;
+      }
+
+      log_v(
+        "[conn_id: %d, trans_id: %d, bda: %s, exec_write_flag: 0x%.2x=%s]", evtParam->exec_write.conn_id, evtParam->exec_write.trans_id,
+        BLEAddress(evtParam->exec_write.bda).toString().c_str(), evtParam->exec_write.exec_write_flag, pWriteFlagText
+      );
+      break;
+    }  // ESP_GATTS_DISCONNECT_EVT
 #endif
-		default:
-			log_v("dumpGattServerEvent: *** NOT CODED ***");
-			break;
-		}
-} // dumpGattServerEvent
 
+    case ESP_GATTS_MTU_EVT:
+    {
+      log_v("[conn_id: %d, mtu: %d]", evtParam->mtu.conn_id, evtParam->mtu.mtu);
+      break;
+    }  // ESP_GATTS_MTU_EVT
+
+    case ESP_GATTS_READ_EVT:
+    {
+      log_v(
+        "[conn_id: %d, trans_id: %d, bda: %s, handle: 0x%.2x, is_long: %d, need_rsp:%d]", evtParam->read.conn_id, evtParam->read.trans_id,
+        BLEAddress(evtParam->read.bda).toString().c_str(), evtParam->read.handle, evtParam->read.is_long, evtParam->read.need_rsp
+      );
+      break;
+    }  // ESP_GATTS_READ_EVT
+
+    case ESP_GATTS_RESPONSE_EVT:
+    {
+      log_v("[status: %s, handle: 0x%.2x]", gattStatusToString(evtParam->rsp.status).c_str(), evtParam->rsp.handle);
+      break;
+    }  // ESP_GATTS_RESPONSE_EVT
+
+    case ESP_GATTS_REG_EVT:
+    {
+      log_v("[status: %s, app_id: %d]", gattStatusToString(evtParam->reg.status).c_str(), evtParam->reg.app_id);
+      break;
+    }  // ESP_GATTS_REG_EVT
+
+    // ESP_GATTS_START_EVT
+    //
+    // start:
+    // - esp_gatt_status_t status
+    // - uint16_t          service_handle
+    case ESP_GATTS_START_EVT:
+    {
+      log_v("[status: %s, service_handle: 0x%.2x]", gattStatusToString(evtParam->start.status).c_str(), evtParam->start.service_handle);
+      break;
+    }  // ESP_GATTS_START_EVT
+
+    // ESP_GATTS_WRITE_EVT
+    //
+    // write:
+    // - uint16_t      conn_id  – The connection id.
+    // - uint16_t      trans_id – The transfer id.
+    // - esp_bd_addr_t bda      – The address of the partner.
+    // - uint16_t      handle   – The attribute handle.
+    // - uint16_t      offset   – The offset of the currently received within the whole value.
+    // - bool          need_rsp – Do we need a response?
+    // - bool          is_prep  – Is this a write prepare?  If set, then this is to be considered part of the received value and not the whole value.  A subsequent ESP_GATTS_EXEC_WRITE will mark the total.
+    // - uint16_t      len      – The length of the incoming value part.
+    // - uint8_t*      value    – The data for this value part.
+    case ESP_GATTS_WRITE_EVT:
+    {
+      log_v(
+        "[conn_id: %d, trans_id: %d, bda: %s, handle: 0x%.2x, offset: %d, need_rsp: %d, is_prep: %d, len: %d]", evtParam->write.conn_id,
+        evtParam->write.trans_id, BLEAddress(evtParam->write.bda).toString().c_str(), evtParam->write.handle, evtParam->write.offset, evtParam->write.need_rsp,
+        evtParam->write.is_prep, evtParam->write.len
+      );
+      char *pHex = buildHexData(nullptr, evtParam->write.value, evtParam->write.len);
+      log_v("[Data: %s]", pHex);
+      free(pHex);
+      break;
+    }  // ESP_GATTS_WRITE_EVT
+#endif
+    default: log_v("dumpGattServerEvent: *** NOT CODED ***"); break;
+  }
+}  // dumpGattServerEvent
 
 /**
  * @brief Convert a BLE event type to a string.
  * @param [in] eventType The event type.
  * @return The event type as a string.
  */
-const char* BLEUtils::eventTypeToString(esp_ble_evt_type_t eventType) {
-	switch (eventType) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_BLE_EVT_CONN_ADV:
-			return "ESP_BLE_EVT_CONN_ADV";
-		case ESP_BLE_EVT_CONN_DIR_ADV:
-			return "ESP_BLE_EVT_CONN_DIR_ADV";
-		case ESP_BLE_EVT_DISC_ADV:
-			return "ESP_BLE_EVT_DISC_ADV";
-		case ESP_BLE_EVT_NON_CONN_ADV:
-			return "ESP_BLE_EVT_NON_CONN_ADV";
-		case ESP_BLE_EVT_SCAN_RSP:
-			return "ESP_BLE_EVT_SCAN_RSP";
+const char *BLEUtils::eventTypeToString(esp_ble_evt_type_t eventType) {
+  switch (eventType) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_BLE_EVT_CONN_ADV:     return "ESP_BLE_EVT_CONN_ADV";
+    case ESP_BLE_EVT_CONN_DIR_ADV: return "ESP_BLE_EVT_CONN_DIR_ADV";
+    case ESP_BLE_EVT_DISC_ADV:     return "ESP_BLE_EVT_DISC_ADV";
+    case ESP_BLE_EVT_NON_CONN_ADV: return "ESP_BLE_EVT_NON_CONN_ADV";
+    case ESP_BLE_EVT_SCAN_RSP:     return "ESP_BLE_EVT_SCAN_RSP";
 #endif
-		default:
-			log_v("Unknown esp_ble_evt_type_t: %d (0x%.2x)", eventType, eventType);
-			return "*** Unknown ***";
-	}
-} // eventTypeToString
-
-
+    default: log_v("Unknown esp_ble_evt_type_t: %d (0x%.2x)", eventType, eventType); return "*** Unknown ***";
+  }
+}  // eventTypeToString
 
 /**
  * @brief Convert a BT GAP event type to a string representation.
  * @param [in] eventType The type of event.
  * @return A string representation of the event type.
  */
-const char* BLEUtils::gapEventToString(uint32_t eventType) {
-	switch (eventType) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT:
-			return "ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT";
-		case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT:
-			return "ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT";
-		case ESP_GAP_BLE_ADV_START_COMPLETE_EVT:
-			return "ESP_GAP_BLE_ADV_START_COMPLETE_EVT";
-		case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT:					  /* !< When stop adv complete, the event comes */
-			return "ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT";
-		case ESP_GAP_BLE_AUTH_CMPL_EVT:							  /* Authentication complete indication. */
-			return "ESP_GAP_BLE_AUTH_CMPL_EVT";
-		case ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT:
-			return "ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT";
-		case ESP_GAP_BLE_GET_BOND_DEV_COMPLETE_EVT:
-			return "ESP_GAP_BLE_GET_BOND_DEV_COMPLETE_EVT";
-		case ESP_GAP_BLE_KEY_EVT:									/* BLE  key event for peer device keys */
-			return "ESP_GAP_BLE_KEY_EVT";
-		case ESP_GAP_BLE_LOCAL_IR_EVT:							   /* BLE local IR event */
-			return "ESP_GAP_BLE_LOCAL_IR_EVT";
-		case ESP_GAP_BLE_LOCAL_ER_EVT:							   /* BLE local ER event */
-			return "ESP_GAP_BLE_LOCAL_ER_EVT";
-		case ESP_GAP_BLE_NC_REQ_EVT:								 /* Numeric Comparison request event */
-			return "ESP_GAP_BLE_NC_REQ_EVT";
-		case ESP_GAP_BLE_OOB_REQ_EVT:								/* OOB request event */
-			return "ESP_GAP_BLE_OOB_REQ_EVT";
-		case ESP_GAP_BLE_PASSKEY_NOTIF_EVT:						  /* passkey notification event */
-			return "ESP_GAP_BLE_PASSKEY_NOTIF_EVT";
-		case ESP_GAP_BLE_PASSKEY_REQ_EVT:							/* passkey request event */
-			return "ESP_GAP_BLE_PASSKEY_REQ_EVT";
-		case ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT:
-			return "ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT";
-		case ESP_GAP_BLE_REMOVE_BOND_DEV_COMPLETE_EVT:
-			return "ESP_GAP_BLE_REMOVE_BOND_DEV_COMPLETE_EVT";
-		case ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT:
-			return "ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT";
-		case ESP_GAP_BLE_SCAN_RESULT_EVT:
-			return "ESP_GAP_BLE_SCAN_RESULT_EVT";
-		case ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT:
-			return "ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT";
-		case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT:
-			return "ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT";
-		case ESP_GAP_BLE_SCAN_START_COMPLETE_EVT:
-			return "ESP_GAP_BLE_SCAN_START_COMPLETE_EVT";
-		case ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT:
-			return "ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT";
-		case ESP_GAP_BLE_SEC_REQ_EVT:								/* BLE  security request */
-			return "ESP_GAP_BLE_SEC_REQ_EVT";
-		case ESP_GAP_BLE_SET_LOCAL_PRIVACY_COMPLETE_EVT:
-			return "ESP_GAP_BLE_SET_LOCAL_PRIVACY_COMPLETE_EVT";
-		case ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT:
-			return "ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT";
-		case ESP_GAP_BLE_SET_STATIC_RAND_ADDR_EVT:
-			return "ESP_GAP_BLE_SET_STATIC_RAND_ADDR_EVT";
-		case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT:
-			return "ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT";
+const char *BLEUtils::gapEventToString(uint32_t eventType) {
+  switch (eventType) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT:          return "ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT";
+    case ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT:      return "ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT";
+    case ESP_GAP_BLE_ADV_START_COMPLETE_EVT:             return "ESP_GAP_BLE_ADV_START_COMPLETE_EVT";
+    case ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT:              /* !< When stop adv complete, the event comes */ return "ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT";
+    case ESP_GAP_BLE_AUTH_CMPL_EVT:                      /* Authentication complete indication. */ return "ESP_GAP_BLE_AUTH_CMPL_EVT";
+    case ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT:        return "ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT";
+    case ESP_GAP_BLE_GET_BOND_DEV_COMPLETE_EVT:          return "ESP_GAP_BLE_GET_BOND_DEV_COMPLETE_EVT";
+    case ESP_GAP_BLE_KEY_EVT:                            /* BLE  key event for peer device keys */ return "ESP_GAP_BLE_KEY_EVT";
+    case ESP_GAP_BLE_LOCAL_IR_EVT:                       /* BLE local IR event */ return "ESP_GAP_BLE_LOCAL_IR_EVT";
+    case ESP_GAP_BLE_LOCAL_ER_EVT:                       /* BLE local ER event */ return "ESP_GAP_BLE_LOCAL_ER_EVT";
+    case ESP_GAP_BLE_NC_REQ_EVT:                         /* Numeric Comparison request event */ return "ESP_GAP_BLE_NC_REQ_EVT";
+    case ESP_GAP_BLE_OOB_REQ_EVT:                        /* OOB request event */ return "ESP_GAP_BLE_OOB_REQ_EVT";
+    case ESP_GAP_BLE_PASSKEY_NOTIF_EVT:                  /* passkey notification event */ return "ESP_GAP_BLE_PASSKEY_NOTIF_EVT";
+    case ESP_GAP_BLE_PASSKEY_REQ_EVT:                    /* passkey request event */ return "ESP_GAP_BLE_PASSKEY_REQ_EVT";
+    case ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT:             return "ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT";
+    case ESP_GAP_BLE_REMOVE_BOND_DEV_COMPLETE_EVT:       return "ESP_GAP_BLE_REMOVE_BOND_DEV_COMPLETE_EVT";
+    case ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT:        return "ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT";
+    case ESP_GAP_BLE_SCAN_RESULT_EVT:                    return "ESP_GAP_BLE_SCAN_RESULT_EVT";
+    case ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT: return "ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT";
+    case ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT:     return "ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT";
+    case ESP_GAP_BLE_SCAN_START_COMPLETE_EVT:            return "ESP_GAP_BLE_SCAN_START_COMPLETE_EVT";
+    case ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT:             return "ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT";
+    case ESP_GAP_BLE_SEC_REQ_EVT:                        /* BLE  security request */ return "ESP_GAP_BLE_SEC_REQ_EVT";
+    case ESP_GAP_BLE_SET_LOCAL_PRIVACY_COMPLETE_EVT:     return "ESP_GAP_BLE_SET_LOCAL_PRIVACY_COMPLETE_EVT";
+    case ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT:        return "ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT";
+    case ESP_GAP_BLE_SET_STATIC_RAND_ADDR_EVT:           return "ESP_GAP_BLE_SET_STATIC_RAND_ADDR_EVT";
+    case ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT:             return "ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT";
 #endif
-		default:
-			log_v("gapEventToString: Unknown event type %d 0x%.2x", eventType, eventType);
-			return "Unknown event type";
-	}
-} // gapEventToString
-
-
-std::string BLEUtils::gattCharacteristicUUIDToString(uint32_t characteristicUUID) {
-	const characteristicMap_t* p = g_characteristicsMappings;
-	while (strlen(p->name) > 0) {
-		if (p->assignedNumber == characteristicUUID) {
-			return std::string(p->name);
-		}
-		p++;
-	}
-	return "Unknown";
-} // gattCharacteristicUUIDToString
-
+    default: log_v("gapEventToString: Unknown event type %d 0x%.2x", eventType, eventType); return "Unknown event type";
+  }
+}  // gapEventToString
+
+String BLEUtils::gattCharacteristicUUIDToString(uint32_t characteristicUUID) {
+  const characteristicMap_t *p = g_characteristicsMappings;
+  while (strlen(p->name) > 0) {
+    if (p->assignedNumber == characteristicUUID) {
+      return String(p->name);
+    }
+    p++;
+  }
+  return "Unknown";
+}  // gattCharacteristicUUIDToString
 
 /**
  * @brief Given the UUID for a BLE defined descriptor, return its string representation.
  * @param [in] descriptorUUID UUID of the descriptor to be returned as a string.
  * @return The string representation of a descriptor UUID.
  */
-std::string BLEUtils::gattDescriptorUUIDToString(uint32_t descriptorUUID) {
-	gattdescriptor_t* p = (gattdescriptor_t*) g_descriptor_ids;
-	while (strlen(p->name) > 0) {
-		if (p->assignedNumber == descriptorUUID) {
-			return std::string(p->name);
-		}
-		p++;
-	}
-	return "";
-} // gattDescriptorUUIDToString
-
+String BLEUtils::gattDescriptorUUIDToString(uint32_t descriptorUUID) {
+  gattdescriptor_t *p = (gattdescriptor_t *)g_descriptor_ids;
+  while (strlen(p->name) > 0) {
+    if (p->assignedNumber == descriptorUUID) {
+      return String(p->name);
+    }
+    p++;
+  }
+  return "";
+}  // gattDescriptorUUIDToString
 
 /**
  * @brief Return a string representation of an esp_gattc_service_elem_t.
  * @return A string representation of an esp_gattc_service_elem_t.
  */
-std::string BLEUtils::gattcServiceElementToString(esp_gattc_service_elem_t* pGATTCServiceElement) {
-	std::string res;
-	char val[6];
-	res += "[uuid: " + BLEUUID(pGATTCServiceElement->uuid).toString() + ", start_handle: ";
-	snprintf(val, sizeof(val), "%d", pGATTCServiceElement->start_handle);
-	res += val;
-	res += " 0x";
-	snprintf(val, sizeof(val), "%04x", pGATTCServiceElement->start_handle);
-	res += val;
-	res += ", end_handle: ";
-	snprintf(val, sizeof(val), "%d", pGATTCServiceElement->end_handle);
-	res += val;
-	res += " 0x";
-	snprintf(val, sizeof(val), "%04x", pGATTCServiceElement->end_handle);
-	res += val;
-	res += "]";
-	return res;
-} // gattcServiceElementToString
-
+String BLEUtils::gattcServiceElementToString(esp_gattc_service_elem_t *pGATTCServiceElement) {
+  String res;
+  char val[6];
+  res += "[uuid: " + BLEUUID(pGATTCServiceElement->uuid).toString() + ", start_handle: ";
+  snprintf(val, sizeof(val), "%d", pGATTCServiceElement->start_handle);
+  res += val;
+  res += " 0x";
+  snprintf(val, sizeof(val), "%04x", pGATTCServiceElement->start_handle);
+  res += val;
+  res += ", end_handle: ";
+  snprintf(val, sizeof(val), "%d", pGATTCServiceElement->end_handle);
+  res += val;
+  res += " 0x";
+  snprintf(val, sizeof(val), "%04x", pGATTCServiceElement->end_handle);
+  res += val;
+  res += "]";
+  return res;
+}  // gattcServiceElementToString
 
 /**
  * @brief Convert an esp_gatt_srvc_id_t to a string.
  */
-std::string BLEUtils::gattServiceIdToString(esp_gatt_srvc_id_t srvcId) {
-	return gattIdToString(srvcId.id);
-} // gattServiceIdToString
-
-
-std::string BLEUtils::gattServiceToString(uint32_t serviceId) {
-	gattService_t* p = (gattService_t*) g_gattServices;
-	while (strlen(p->name) > 0) {
-		if (p->assignedNumber == serviceId) {
-			return std::string(p->name);
-		}
-		p++;
-	}
-	return "Unknown";
-} // gattServiceToString
-
+String BLEUtils::gattServiceIdToString(esp_gatt_srvc_id_t srvcId) {
+  return gattIdToString(srvcId.id);
+}  // gattServiceIdToString
+
+String BLEUtils::gattServiceToString(uint32_t serviceId) {
+  gattService_t *p = (gattService_t *)g_gattServices;
+  while (strlen(p->name) > 0) {
+    if (p->assignedNumber == serviceId) {
+      return String(p->name);
+    }
+    p++;
+  }
+  return "Unknown";
+}  // gattServiceToString
 
 /**
  * @brief Convert a GATT status to a string.
@@ -1899,113 +1734,67 @@ std::string BLEUtils::gattServiceToString(uint32_t serviceId) {
  * @param [in] status The status to convert.
  * @return A string representation of the status.
  */
-std::string BLEUtils::gattStatusToString(esp_gatt_status_t status) {
-	switch (status) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_GATT_OK:
-			return "ESP_GATT_OK";
-		case ESP_GATT_INVALID_HANDLE:
-			return "ESP_GATT_INVALID_HANDLE";
-		case ESP_GATT_READ_NOT_PERMIT:
-			return "ESP_GATT_READ_NOT_PERMIT";
-		case ESP_GATT_WRITE_NOT_PERMIT:
-			return "ESP_GATT_WRITE_NOT_PERMIT";
-		case ESP_GATT_INVALID_PDU:
-			return "ESP_GATT_INVALID_PDU";
-		case ESP_GATT_INSUF_AUTHENTICATION:
-			return "ESP_GATT_INSUF_AUTHENTICATION";
-		case ESP_GATT_REQ_NOT_SUPPORTED:
-			return "ESP_GATT_REQ_NOT_SUPPORTED";
-		case ESP_GATT_INVALID_OFFSET:
-			return "ESP_GATT_INVALID_OFFSET";
-		case ESP_GATT_INSUF_AUTHORIZATION:
-			return "ESP_GATT_INSUF_AUTHORIZATION";
-		case ESP_GATT_PREPARE_Q_FULL:
-			return "ESP_GATT_PREPARE_Q_FULL";
-		case ESP_GATT_NOT_FOUND:
-			return "ESP_GATT_NOT_FOUND";
-		case ESP_GATT_NOT_LONG:
-			return "ESP_GATT_NOT_LONG";
-		case ESP_GATT_INSUF_KEY_SIZE:
-			return "ESP_GATT_INSUF_KEY_SIZE";
-		case ESP_GATT_INVALID_ATTR_LEN:
-			return "ESP_GATT_INVALID_ATTR_LEN";
-		case ESP_GATT_ERR_UNLIKELY:
-			return "ESP_GATT_ERR_UNLIKELY";
-		case ESP_GATT_INSUF_ENCRYPTION:
-			return "ESP_GATT_INSUF_ENCRYPTION";
-		case ESP_GATT_UNSUPPORT_GRP_TYPE:
-			return "ESP_GATT_UNSUPPORT_GRP_TYPE";
-		case ESP_GATT_INSUF_RESOURCE:
-			return "ESP_GATT_INSUF_RESOURCE";
-		case ESP_GATT_NO_RESOURCES:
-			return "ESP_GATT_NO_RESOURCES";
-		case ESP_GATT_INTERNAL_ERROR:
-			return "ESP_GATT_INTERNAL_ERROR";
-		case ESP_GATT_WRONG_STATE:
-			return "ESP_GATT_WRONG_STATE";
-		case ESP_GATT_DB_FULL:
-			return "ESP_GATT_DB_FULL";
-		case ESP_GATT_BUSY:
-			return "ESP_GATT_BUSY";
-		case ESP_GATT_ERROR:
-			return "ESP_GATT_ERROR";
-		case ESP_GATT_CMD_STARTED:
-			return "ESP_GATT_CMD_STARTED";
-		case ESP_GATT_ILLEGAL_PARAMETER:
-			return "ESP_GATT_ILLEGAL_PARAMETER";
-		case ESP_GATT_PENDING:
-			return "ESP_GATT_PENDING";
-		case ESP_GATT_AUTH_FAIL:
-			return "ESP_GATT_AUTH_FAIL";
-		case ESP_GATT_MORE:
-			return "ESP_GATT_MORE";
-		case ESP_GATT_INVALID_CFG:
-			return "ESP_GATT_INVALID_CFG";
-		case ESP_GATT_SERVICE_STARTED:
-			return "ESP_GATT_SERVICE_STARTED";
-		case ESP_GATT_ENCRYPED_NO_MITM:
-			return "ESP_GATT_ENCRYPED_NO_MITM";
-		case ESP_GATT_NOT_ENCRYPTED:
-			return "ESP_GATT_NOT_ENCRYPTED";
-		case ESP_GATT_CONGESTED:
-			return "ESP_GATT_CONGESTED";
-		case ESP_GATT_DUP_REG:
-			return "ESP_GATT_DUP_REG";
-		case ESP_GATT_ALREADY_OPEN:
-			return "ESP_GATT_ALREADY_OPEN";
-		case ESP_GATT_CANCEL:
-			return "ESP_GATT_CANCEL";
-		case ESP_GATT_STACK_RSP:
-			return "ESP_GATT_STACK_RSP";
-		case ESP_GATT_APP_RSP:
-			return "ESP_GATT_APP_RSP";
-		case ESP_GATT_UNKNOWN_ERROR:
-			return "ESP_GATT_UNKNOWN_ERROR";
-		case ESP_GATT_CCC_CFG_ERR:
-			return "ESP_GATT_CCC_CFG_ERR";
-		case ESP_GATT_PRC_IN_PROGRESS:
-			return "ESP_GATT_PRC_IN_PROGRESS";
-		case ESP_GATT_OUT_OF_RANGE:
-			return "ESP_GATT_OUT_OF_RANGE";
+String BLEUtils::gattStatusToString(esp_gatt_status_t status) {
+  switch (status) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_GATT_OK:                   return "ESP_GATT_OK";
+    case ESP_GATT_INVALID_HANDLE:       return "ESP_GATT_INVALID_HANDLE";
+    case ESP_GATT_READ_NOT_PERMIT:      return "ESP_GATT_READ_NOT_PERMIT";
+    case ESP_GATT_WRITE_NOT_PERMIT:     return "ESP_GATT_WRITE_NOT_PERMIT";
+    case ESP_GATT_INVALID_PDU:          return "ESP_GATT_INVALID_PDU";
+    case ESP_GATT_INSUF_AUTHENTICATION: return "ESP_GATT_INSUF_AUTHENTICATION";
+    case ESP_GATT_REQ_NOT_SUPPORTED:    return "ESP_GATT_REQ_NOT_SUPPORTED";
+    case ESP_GATT_INVALID_OFFSET:       return "ESP_GATT_INVALID_OFFSET";
+    case ESP_GATT_INSUF_AUTHORIZATION:  return "ESP_GATT_INSUF_AUTHORIZATION";
+    case ESP_GATT_PREPARE_Q_FULL:       return "ESP_GATT_PREPARE_Q_FULL";
+    case ESP_GATT_NOT_FOUND:            return "ESP_GATT_NOT_FOUND";
+    case ESP_GATT_NOT_LONG:             return "ESP_GATT_NOT_LONG";
+    case ESP_GATT_INSUF_KEY_SIZE:       return "ESP_GATT_INSUF_KEY_SIZE";
+    case ESP_GATT_INVALID_ATTR_LEN:     return "ESP_GATT_INVALID_ATTR_LEN";
+    case ESP_GATT_ERR_UNLIKELY:         return "ESP_GATT_ERR_UNLIKELY";
+    case ESP_GATT_INSUF_ENCRYPTION:     return "ESP_GATT_INSUF_ENCRYPTION";
+    case ESP_GATT_UNSUPPORT_GRP_TYPE:   return "ESP_GATT_UNSUPPORT_GRP_TYPE";
+    case ESP_GATT_INSUF_RESOURCE:       return "ESP_GATT_INSUF_RESOURCE";
+    case ESP_GATT_NO_RESOURCES:         return "ESP_GATT_NO_RESOURCES";
+    case ESP_GATT_INTERNAL_ERROR:       return "ESP_GATT_INTERNAL_ERROR";
+    case ESP_GATT_WRONG_STATE:          return "ESP_GATT_WRONG_STATE";
+    case ESP_GATT_DB_FULL:              return "ESP_GATT_DB_FULL";
+    case ESP_GATT_BUSY:                 return "ESP_GATT_BUSY";
+    case ESP_GATT_ERROR:                return "ESP_GATT_ERROR";
+    case ESP_GATT_CMD_STARTED:          return "ESP_GATT_CMD_STARTED";
+    case ESP_GATT_ILLEGAL_PARAMETER:    return "ESP_GATT_ILLEGAL_PARAMETER";
+    case ESP_GATT_PENDING:              return "ESP_GATT_PENDING";
+    case ESP_GATT_AUTH_FAIL:            return "ESP_GATT_AUTH_FAIL";
+    case ESP_GATT_MORE:                 return "ESP_GATT_MORE";
+    case ESP_GATT_INVALID_CFG:          return "ESP_GATT_INVALID_CFG";
+    case ESP_GATT_SERVICE_STARTED:      return "ESP_GATT_SERVICE_STARTED";
+    case ESP_GATT_ENCRYPTED_NO_MITM:    return "ESP_GATT_ENCRYPTED_NO_MITM";
+    case ESP_GATT_NOT_ENCRYPTED:        return "ESP_GATT_NOT_ENCRYPTED";
+    case ESP_GATT_CONGESTED:            return "ESP_GATT_CONGESTED";
+    case ESP_GATT_DUP_REG:              return "ESP_GATT_DUP_REG";
+    case ESP_GATT_ALREADY_OPEN:         return "ESP_GATT_ALREADY_OPEN";
+    case ESP_GATT_CANCEL:               return "ESP_GATT_CANCEL";
+    case ESP_GATT_STACK_RSP:            return "ESP_GATT_STACK_RSP";
+    case ESP_GATT_APP_RSP:              return "ESP_GATT_APP_RSP";
+    case ESP_GATT_UNKNOWN_ERROR:        return "ESP_GATT_UNKNOWN_ERROR";
+    case ESP_GATT_CCC_CFG_ERR:          return "ESP_GATT_CCC_CFG_ERR";
+    case ESP_GATT_PRC_IN_PROGRESS:      return "ESP_GATT_PRC_IN_PROGRESS";
+    case ESP_GATT_OUT_OF_RANGE:         return "ESP_GATT_OUT_OF_RANGE";
 #endif
-		default:
-			return "Unknown";
-	}
-} // gattStatusToString
-
-
-
-std::string BLEUtils::getMember(uint32_t memberId) {
-	member_t* p = (member_t*) members_ids;
-
-	while (strlen(p->name) > 0) {
-		if (p->assignedNumber == memberId) {
-			return std::string(p->name);
-		}
-		p++;
-	}
-	return "Unknown";
+    default: return "Unknown";
+  }
+}  // gattStatusToString
+
+String BLEUtils::getMember(uint32_t memberId) {
+  member_t *p = (member_t *)members_ids;
+
+  while (strlen(p->name) > 0) {
+    if (p->assignedNumber == memberId) {
+      return String(p->name);
+    }
+    p++;
+  }
+  return "Unknown";
 }
 
 /**
@@ -2013,28 +1802,20 @@ std::string BLEUtils::getMember(uint32_t memberId) {
  * @param [in] searchEvt
  * @return The search event type as a string.
  */
-const char* BLEUtils::searchEventTypeToString(esp_gap_search_evt_t searchEvt) {
-	switch (searchEvt) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_GAP_SEARCH_INQ_RES_EVT:
-			return "ESP_GAP_SEARCH_INQ_RES_EVT";
-		case ESP_GAP_SEARCH_INQ_CMPL_EVT:
-			return "ESP_GAP_SEARCH_INQ_CMPL_EVT";
-		case ESP_GAP_SEARCH_DISC_RES_EVT:
-			return "ESP_GAP_SEARCH_DISC_RES_EVT";
-		case ESP_GAP_SEARCH_DISC_BLE_RES_EVT:
-			return "ESP_GAP_SEARCH_DISC_BLE_RES_EVT";
-		case ESP_GAP_SEARCH_DISC_CMPL_EVT:
-			return "ESP_GAP_SEARCH_DISC_CMPL_EVT";
-		case ESP_GAP_SEARCH_DI_DISC_CMPL_EVT:
-			return "ESP_GAP_SEARCH_DI_DISC_CMPL_EVT";
-		case ESP_GAP_SEARCH_SEARCH_CANCEL_CMPL_EVT:
-			return "ESP_GAP_SEARCH_SEARCH_CANCEL_CMPL_EVT";
+const char *BLEUtils::searchEventTypeToString(esp_gap_search_evt_t searchEvt) {
+  switch (searchEvt) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_GAP_SEARCH_INQ_RES_EVT:            return "ESP_GAP_SEARCH_INQ_RES_EVT";
+    case ESP_GAP_SEARCH_INQ_CMPL_EVT:           return "ESP_GAP_SEARCH_INQ_CMPL_EVT";
+    case ESP_GAP_SEARCH_DISC_RES_EVT:           return "ESP_GAP_SEARCH_DISC_RES_EVT";
+    case ESP_GAP_SEARCH_DISC_BLE_RES_EVT:       return "ESP_GAP_SEARCH_DISC_BLE_RES_EVT";
+    case ESP_GAP_SEARCH_DISC_CMPL_EVT:          return "ESP_GAP_SEARCH_DISC_CMPL_EVT";
+    case ESP_GAP_SEARCH_DI_DISC_CMPL_EVT:       return "ESP_GAP_SEARCH_DI_DISC_CMPL_EVT";
+    case ESP_GAP_SEARCH_SEARCH_CANCEL_CMPL_EVT: return "ESP_GAP_SEARCH_SEARCH_CANCEL_CMPL_EVT";
 #endif
-		default:
-			log_v("Unknown event type: 0x%x", searchEvt);
-			return "Unknown event type";
-	}
-} // searchEventTypeToString
+    default: log_v("Unknown event type: 0x%x", searchEvt); return "Unknown event type";
+  }
+}  // searchEventTypeToString
 
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEUtils.h b/libraries/BLE/src/BLEUtils.h
index 7981691cc84..7c6f58d284b 100644
--- a/libraries/BLE/src/BLEUtils.h
+++ b/libraries/BLE/src/BLEUtils.h
@@ -7,11 +7,14 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEUTILS_H_
 #define COMPONENTS_CPP_UTILS_BLEUTILS_H_
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
-#include <esp_gattc_api.h>   // ESP32 BLE
-#include <esp_gatts_api.h>   // ESP32 BLE
-#include <esp_gap_ble_api.h> // ESP32 BLE
+#if defined(CONFIG_BLUEDROID_ENABLED)
+#include <esp_gattc_api.h>    // ESP32 BLE
+#include <esp_gatts_api.h>    // ESP32 BLE
+#include <esp_gap_ble_api.h>  // ESP32 BLE
 #include <string>
 #include "BLEClient.h"
 
@@ -20,44 +23,37 @@
  */
 class BLEUtils {
 public:
-	static const char*        addressTypeToString(esp_ble_addr_type_t type);
-	static std::string        adFlagsToString(uint8_t adFlags);
-	static const char*        advTypeToString(uint8_t advType);
-	static char*              buildHexData(uint8_t* target, uint8_t* source, uint8_t length);
-	static std::string        buildPrintData(uint8_t* source, size_t length);
-	static std::string        characteristicPropertiesToString(esp_gatt_char_prop_t prop);
-	static const char*        devTypeToString(esp_bt_dev_type_t type);
-	static esp_gatt_id_t	  buildGattId(esp_bt_uuid_t uuid, uint8_t inst_id = 0);
-	static esp_gatt_srvc_id_t buildGattSrvcId(esp_gatt_id_t gattId, bool is_primary = true);
-	static void dumpGapEvent(
-		esp_gap_ble_cb_event_t  event,
-		esp_ble_gap_cb_param_t* param);
-	static void dumpGattClientEvent(
-		esp_gattc_cb_event_t      event,
-		esp_gatt_if_t             gattc_if,
-		esp_ble_gattc_cb_param_t* evtParam);
-	static void dumpGattServerEvent(
-		esp_gatts_cb_event_t      event,
-		esp_gatt_if_t             gatts_if,
-		esp_ble_gatts_cb_param_t* evtParam);
-	static const char* eventTypeToString(esp_ble_evt_type_t eventType);
-	static BLEClient*  findByAddress(BLEAddress address);
-	static BLEClient*  findByConnId(uint16_t conn_id);
-	static const char* gapEventToString(uint32_t eventType);
-	static std::string gattCharacteristicUUIDToString(uint32_t characteristicUUID);
-	static std::string gattClientEventTypeToString(esp_gattc_cb_event_t eventType);
-	static std::string gattCloseReasonToString(esp_gatt_conn_reason_t reason);
-	static std::string gattcServiceElementToString(esp_gattc_service_elem_t* pGATTCServiceElement);
-	static std::string gattDescriptorUUIDToString(uint32_t descriptorUUID);
-	static std::string gattServerEventTypeToString(esp_gatts_cb_event_t eventType);
-	static std::string gattServiceIdToString(esp_gatt_srvc_id_t srvcId);
-	static std::string gattServiceToString(uint32_t serviceId);
-	static std::string gattStatusToString(esp_gatt_status_t status);
-	static std::string getMember(uint32_t memberId);
-	static void        registerByAddress(BLEAddress address, BLEClient* pDevice);
-	static void        registerByConnId(uint16_t conn_id, BLEClient* pDevice);
-	static const char* searchEventTypeToString(esp_gap_search_evt_t searchEvt);
+  static const char *addressTypeToString(esp_ble_addr_type_t type);
+  static String adFlagsToString(uint8_t adFlags);
+  static const char *advTypeToString(uint8_t advType);
+  static char *buildHexData(uint8_t *target, uint8_t *source, uint8_t length);
+  static String buildPrintData(uint8_t *source, size_t length);
+  static String characteristicPropertiesToString(esp_gatt_char_prop_t prop);
+  static const char *devTypeToString(esp_bt_dev_type_t type);
+  static esp_gatt_id_t buildGattId(esp_bt_uuid_t uuid, uint8_t inst_id = 0);
+  static esp_gatt_srvc_id_t buildGattSrvcId(esp_gatt_id_t gattId, bool is_primary = true);
+  static void dumpGapEvent(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param);
+  static void dumpGattClientEvent(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *evtParam);
+  static void dumpGattServerEvent(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *evtParam);
+  static const char *eventTypeToString(esp_ble_evt_type_t eventType);
+  static BLEClient *findByAddress(BLEAddress address);
+  static BLEClient *findByConnId(uint16_t conn_id);
+  static const char *gapEventToString(uint32_t eventType);
+  static String gattCharacteristicUUIDToString(uint32_t characteristicUUID);
+  static String gattClientEventTypeToString(esp_gattc_cb_event_t eventType);
+  static String gattCloseReasonToString(esp_gatt_conn_reason_t reason);
+  static String gattcServiceElementToString(esp_gattc_service_elem_t *pGATTCServiceElement);
+  static String gattDescriptorUUIDToString(uint32_t descriptorUUID);
+  static String gattServerEventTypeToString(esp_gatts_cb_event_t eventType);
+  static String gattServiceIdToString(esp_gatt_srvc_id_t srvcId);
+  static String gattServiceToString(uint32_t serviceId);
+  static String gattStatusToString(esp_gatt_status_t status);
+  static String getMember(uint32_t memberId);
+  static void registerByAddress(BLEAddress address, BLEClient *pDevice);
+  static void registerByConnId(uint16_t conn_id, BLEClient *pDevice);
+  static const char *searchEventTypeToString(esp_gap_search_evt_t searchEvt);
 };
 
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEUTILS_H_ */
diff --git a/libraries/BLE/src/BLEValue.cpp b/libraries/BLE/src/BLEValue.cpp
index 40f6a20a656..26811c985ac 100644
--- a/libraries/BLE/src/BLEValue.cpp
+++ b/libraries/BLE/src/BLEValue.cpp
@@ -4,28 +4,29 @@
  *  Created on: Jul 17, 2017
  *      Author: kolban
  */
+#include "soc/soc_caps.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
+#if defined(CONFIG_BLUEDROID_ENABLED)
 #include "BLEValue.h"
 #include "esp32-hal-log.h"
 
 BLEValue::BLEValue() {
-	m_accumulation = "";
-	m_value        = "";
-	m_readOffset   = 0;
-} // BLEValue
-
+  m_accumulation = "";
+  m_value = "";
+  m_readOffset = 0;
+}  // BLEValue
 
 /**
  * @brief Add a message part to the accumulation.
  * The accumulation is a growing set of data that is added to until a commit or cancel.
  * @param [in] part A message part being added.
  */
-void BLEValue::addPart(std::string part) {
-	log_v(">> addPart: length=%d", part.length());
-	m_accumulation += part;
-} // addPart
-
+void BLEValue::addPart(String part) {
+  log_v(">> addPart: length=%d", part.length());
+  m_accumulation += part;
+}  // addPart
 
 /**
  * @brief Add a message part to the accumulation.
@@ -33,21 +34,19 @@ void BLEValue::addPart(std::string part) {
  * @param [in] pData A message part being added.
  * @param [in] length The number of bytes being added.
  */
-void BLEValue::addPart(uint8_t* pData, size_t length) {
-	log_v(">> addPart: length=%d", length);
-	m_accumulation += std::string((char*) pData, length);
-} // addPart
-
+void BLEValue::addPart(uint8_t *pData, size_t length) {
+  log_v(">> addPart: length=%d", length);
+  m_accumulation += String((char *)pData, length);
+}  // addPart
 
 /**
  * @brief Cancel the current accumulation.
  */
 void BLEValue::cancel() {
-	log_v(">> cancel");
-	m_accumulation = "";
-	m_readOffset   = 0;
-} // cancel
-
+  log_v(">> cancel");
+  m_accumulation = "";
+  m_readOffset = 0;
+}  // cancel
 
 /**
  * @brief Commit the current accumulation.
@@ -56,75 +55,70 @@ void BLEValue::cancel() {
  * we now have the complete message and commit the change as a unit.
  */
 void BLEValue::commit() {
-	log_v(">> commit");
-	// If there is nothing to commit, do nothing.
-	if (m_accumulation.length() == 0) return;
-	setValue(m_accumulation);
-	m_accumulation = "";
-	m_readOffset   = 0;
-} // commit
-
+  log_v(">> commit");
+  // If there is nothing to commit, do nothing.
+  if (m_accumulation.length() == 0) {
+    return;
+  }
+  setValue(m_accumulation);
+  m_accumulation = "";
+  m_readOffset = 0;
+}  // commit
 
 /**
  * @brief Get a pointer to the data.
  * @return A pointer to the data.
  */
-uint8_t* BLEValue::getData() {
-	return (uint8_t*) m_value.data();
+uint8_t *BLEValue::getData() {
+  return (uint8_t *)m_value.c_str();
 }
 
-
 /**
  * @brief Get the length of the data in bytes.
  * @return The length of the data in bytes.
  */
 size_t BLEValue::getLength() {
-	return m_value.length();
-} // getLength
-
+  return m_value.length();
+}  // getLength
 
 /**
  * @brief Get the read offset.
  * @return The read offset into the read.
  */
 uint16_t BLEValue::getReadOffset() {
-	return m_readOffset;
-} // getReadOffset
-
+  return m_readOffset;
+}  // getReadOffset
 
 /**
  * @brief Get the current value.
  */
-std::string BLEValue::getValue() {
-	return m_value;
-} // getValue
-
+String BLEValue::getValue() {
+  return m_value;
+}  // getValue
 
 /**
  * @brief Set the read offset
  * @param [in] readOffset The offset into the read.
  */
 void BLEValue::setReadOffset(uint16_t readOffset) {
-	m_readOffset = readOffset;
-} // setReadOffset
-
+  m_readOffset = readOffset;
+}  // setReadOffset
 
 /**
  * @brief Set the current value.
  */
-void BLEValue::setValue(std::string value) {
-	m_value = value;
-} // setValue
-
+void BLEValue::setValue(String value) {
+  m_value = value;
+}  // setValue
 
 /**
  * @brief Set the current value.
  * @param [in] pData The data for the current value.
  * @param [in] The length of the new current value.
  */
-void BLEValue::setValue(uint8_t* pData, size_t length) {
-	m_value = std::string((char*) pData, length);
-} // setValue
-
+void BLEValue::setValue(uint8_t *pData, size_t length) {
+  m_value = String((char *)pData, length);
+}  // setValue
 
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
diff --git a/libraries/BLE/src/BLEValue.h b/libraries/BLE/src/BLEValue.h
index 5df904c10bf..f9c91bdcd4e 100644
--- a/libraries/BLE/src/BLEValue.h
+++ b/libraries/BLE/src/BLEValue.h
@@ -7,33 +7,36 @@
 
 #ifndef COMPONENTS_CPP_UTILS_BLEVALUE_H_
 #define COMPONENTS_CPP_UTILS_BLEVALUE_H_
+#include "soc/soc_caps.h"
+#include "WString.h"
+#if SOC_BLE_SUPPORTED
+
 #include "sdkconfig.h"
-#if defined(CONFIG_BT_ENABLED)
-#include <string>
+#if defined(CONFIG_BLUEDROID_ENABLED)
 
 /**
  * @brief The model of a %BLE value.
  */
 class BLEValue {
 public:
-	BLEValue();
-	void		addPart(std::string part);
-	void		addPart(uint8_t* pData, size_t length);
-	void		cancel();
-	void		commit();
-	uint8_t*	getData();
-	size_t	  getLength();
-	uint16_t	getReadOffset();
-	std::string getValue();
-	void        setReadOffset(uint16_t readOffset);
-	void        setValue(std::string value);
-	void        setValue(uint8_t* pData, size_t length);
+  BLEValue();
+  void addPart(String part);
+  void addPart(uint8_t *pData, size_t length);
+  void cancel();
+  void commit();
+  uint8_t *getData();
+  size_t getLength();
+  uint16_t getReadOffset();
+  String getValue();
+  void setReadOffset(uint16_t readOffset);
+  void setValue(String value);
+  void setValue(uint8_t *pData, size_t length);
 
 private:
-	std::string m_accumulation;
-	uint16_t    m_readOffset;
-	std::string m_value;
-
+  String m_accumulation;
+  uint16_t m_readOffset;
+  String m_value;
 };
-#endif // CONFIG_BT_ENABLED
+#endif /* CONFIG_BLUEDROID_ENABLED */
+#endif /* SOC_BLE_SUPPORTED */
 #endif /* COMPONENTS_CPP_UTILS_BLEVALUE_H_ */
diff --git a/libraries/BLE/src/FreeRTOS.cpp b/libraries/BLE/src/FreeRTOS.cpp
index 7539e252a19..b1f87601813 100644
--- a/libraries/BLE/src/FreeRTOS.cpp
+++ b/libraries/BLE/src/FreeRTOS.cpp
@@ -4,13 +4,13 @@
  *  Created on: Feb 24, 2017
  *      Author: kolban
  */
-#include <freertos/FreeRTOS.h>   // Include the base FreeRTOS definitions
-#include <freertos/task.h>       // Include the task definitions
-#include <freertos/semphr.h>     // Include the semaphore definitions
+#include <freertos/FreeRTOS.h>  // Include the base FreeRTOS definitions
+#include <freertos/task.h>      // Include the task definitions
+#include <freertos/semphr.h>    // Include the semaphore definitions
 #include <string>
 #include <sstream>
 #include <iomanip>
-#include "FreeRTOS.h"
+#include "RTOS.h"
 #include "sdkconfig.h"
 #include "esp32-hal-log.h"
 
@@ -19,39 +19,35 @@
  * @param[in] ms The period in milliseconds for which to sleep.
  */
 void FreeRTOS::sleep(uint32_t ms) {
-	::vTaskDelay(ms / portTICK_PERIOD_MS);
-} // sleep
-
+  ::vTaskDelay(ms / portTICK_PERIOD_MS);
+}  // sleep
 
 /**
  * Start a new task.
  * @param[in] task The function pointer to the function to be run in the task.
  * @param[in] taskName A string identifier for the task.
  * @param[in] param An optional parameter to be passed to the started task.
- * @param[in] stackSize An optional paremeter supplying the size of the stack in which to run the task.
+ * @param[in] stackSize An optional parameter supplying the size of the stack in which to run the task.
  */
-void FreeRTOS::startTask(void task(void*), std::string taskName, void* param, uint32_t stackSize) {
-	::xTaskCreate(task, taskName.data(), stackSize, param, 5, NULL);
-} // startTask
-
+void FreeRTOS::startTask(void task(void *), String taskName, void *param, uint32_t stackSize) {
+  ::xTaskCreate(task, taskName.c_str(), stackSize, param, 5, NULL);
+}  // startTask
 
 /**
  * Delete the task.
  * @param[in] pTask An optional handle to the task to be deleted.  If not supplied the calling task will be deleted.
  */
 void FreeRTOS::deleteTask(TaskHandle_t pTask) {
-	::vTaskDelete(pTask);
-} // deleteTask
-
+  ::vTaskDelete(pTask);
+}  // deleteTask
 
 /**
  * Get the time in milliseconds since the %FreeRTOS scheduler started.
  * @return The time in milliseconds since the %FreeRTOS scheduler started.
  */
 uint32_t FreeRTOS::getTimeSinceStart() {
-	return (uint32_t) (xTaskGetTickCount() * portTICK_PERIOD_MS);
-} // getTimeSinceStart
-
+  return (uint32_t)(xTaskGetTickCount() * portTICK_PERIOD_MS);
+}  // getTimeSinceStart
 
 /**
  * @brief Wait for a semaphore to be released by trying to take it and
@@ -59,24 +55,24 @@ uint32_t FreeRTOS::getTimeSinceStart() {
  * @param [in] owner A debug tag.
  * @return The value associated with the semaphore.
  */
-uint32_t FreeRTOS::Semaphore::wait(std::string owner) {
-	log_v(">> wait: Semaphore waiting: %s for %s", toString().c_str(), owner.c_str());
-	
-	if (m_usePthreads) {
-		pthread_mutex_lock(&m_pthread_mutex);
-	} else {
-		xSemaphoreTake(m_semaphore, portMAX_DELAY);
-	}
+uint32_t FreeRTOS::Semaphore::wait(String owner) {
+  log_v(">> wait: Semaphore waiting: %s for %s", toString().c_str(), owner.c_str());
 
-	if (m_usePthreads) {
-		pthread_mutex_unlock(&m_pthread_mutex);
-	} else {
-		xSemaphoreGive(m_semaphore);
-	}
+  if (m_usePthreads) {
+    pthread_mutex_lock(&m_pthread_mutex);
+  } else {
+    xSemaphoreTake(m_semaphore, portMAX_DELAY);
+  }
 
-	log_v("<< wait: Semaphore released: %s", toString().c_str());
-	return m_value;
-} // wait
+  if (m_usePthreads) {
+    pthread_mutex_unlock(&m_pthread_mutex);
+  } else {
+    xSemaphoreGive(m_semaphore);
+  }
+
+  log_v("<< wait: Semaphore released: %s", toString().c_str());
+  return m_value;
+}  // wait
 
 /**
  * @brief Wait for a semaphore to be released in a given period of time by trying to take it and
@@ -85,75 +81,71 @@ uint32_t FreeRTOS::Semaphore::wait(std::string owner) {
  * @param [in] timeoutMs timeout to wait in ms.
  * @return True if we took the semaphore within timeframe.
  */
-bool FreeRTOS::Semaphore::timedWait(std::string owner, uint32_t timeoutMs) {
-	log_v(">> wait: Semaphore waiting: %s for %s", toString().c_str(), owner.c_str());
-
-	if (m_usePthreads && timeoutMs != portMAX_DELAY) {
-		assert(false);  // We apparently don't have a timed wait for pthreads.
-	}
-
-	auto ret = pdTRUE;
-
-	if (m_usePthreads) {
-		pthread_mutex_lock(&m_pthread_mutex);
-	} else {
-		ret = xSemaphoreTake(m_semaphore, timeoutMs);
-	}
-
-	if (m_usePthreads) {
-		pthread_mutex_unlock(&m_pthread_mutex);
-	} else {
-		xSemaphoreGive(m_semaphore);
-	}
-
-	log_v("<< wait: Semaphore %s released: %d", toString().c_str(), ret);
-	return ret;
-} // wait
-
-
-FreeRTOS::Semaphore::Semaphore(std::string name) {
-	m_usePthreads = false;   	// Are we using pThreads or FreeRTOS?
-	if (m_usePthreads) {
-		pthread_mutex_init(&m_pthread_mutex, nullptr);
-	} else {
-		m_semaphore = xSemaphoreCreateBinary();
-		xSemaphoreGive(m_semaphore);
-	}
-
-	m_name      = name;
-	m_owner     = std::string("<N/A>");
-	m_value     = 0;
+bool FreeRTOS::Semaphore::timedWait(String owner, uint32_t timeoutMs) {
+  log_v(">> wait: Semaphore waiting: %s for %s", toString().c_str(), owner.c_str());
+
+  if (m_usePthreads && timeoutMs != portMAX_DELAY) {
+    assert(false);  // We apparently don't have a timed wait for pthreads.
+  }
+
+  auto ret = pdTRUE;
+
+  if (m_usePthreads) {
+    pthread_mutex_lock(&m_pthread_mutex);
+  } else {
+    ret = xSemaphoreTake(m_semaphore, timeoutMs);
+  }
+
+  if (m_usePthreads) {
+    pthread_mutex_unlock(&m_pthread_mutex);
+  } else {
+    xSemaphoreGive(m_semaphore);
+  }
+
+  log_v("<< wait: Semaphore %s released: %d", toString().c_str(), ret);
+  return ret;
+}  // wait
+
+FreeRTOS::Semaphore::Semaphore(String name) {
+  m_usePthreads = false;  // Are we using pThreads or FreeRTOS?
+  if (m_usePthreads) {
+    pthread_mutex_init(&m_pthread_mutex, nullptr);
+  } else {
+    m_semaphore = xSemaphoreCreateBinary();
+    xSemaphoreGive(m_semaphore);
+  }
+
+  m_name = name;
+  m_owner = String("<N/A>");
+  m_value = 0;
 }
 
-
 FreeRTOS::Semaphore::~Semaphore() {
-	if (m_usePthreads) {
-		pthread_mutex_destroy(&m_pthread_mutex);
-	} else {
-		vSemaphoreDelete(m_semaphore);
-	}
+  if (m_usePthreads) {
+    pthread_mutex_destroy(&m_pthread_mutex);
+  } else {
+    vSemaphoreDelete(m_semaphore);
+  }
 }
 
-
 /**
  * @brief Give a semaphore.
  * The Semaphore is given.
  */
 void FreeRTOS::Semaphore::give() {
-	log_v("Semaphore giving: %s", toString().c_str());
-	m_owner = std::string("<N/A>");
-	
-	if (m_usePthreads) {
-		pthread_mutex_unlock(&m_pthread_mutex);
-	} else {
-		xSemaphoreGive(m_semaphore);
-	}
-// #ifdef ARDUINO_ARCH_ESP32
-// 	FreeRTOS::sleep(10);
-// #endif
+  log_v("Semaphore giving: %s", toString().c_str());
+  m_owner = String("<N/A>");
 
-} // Semaphore::give
+  if (m_usePthreads) {
+    pthread_mutex_unlock(&m_pthread_mutex);
+  } else {
+    xSemaphoreGive(m_semaphore);
+  }
+  // #ifdef ARDUINO_ARCH_ESP32
+  // 	FreeRTOS::sleep(10);
+  // #endif
 
+}  // Semaphore::give
 
 /**
  * @brief Give a semaphore.
@@ -161,23 +153,21 @@ void FreeRTOS::Semaphore::give() {
  * @param [in] value The value to associate with the semaphore.
  */
 void FreeRTOS::Semaphore::give(uint32_t value) {
-	m_value = value;
-	give();
-} // give
-
+  m_value = value;
+  give();
+}  // give
 
 /**
  * @brief Give a semaphore from an ISR.
  */
 void FreeRTOS::Semaphore::giveFromISR() {
-	BaseType_t higherPriorityTaskWoken;
-	if (m_usePthreads) {
-		assert(false);
-	} else {
-		xSemaphoreGiveFromISR(m_semaphore, &higherPriorityTaskWoken);
-	}
-} // giveFromISR
-
+  BaseType_t higherPriorityTaskWoken;
+  if (m_usePthreads) {
+    assert(false);
+  } else {
+    xSemaphoreGiveFromISR(m_semaphore, &higherPriorityTaskWoken);
+  }
+}  // giveFromISR
 
 /**
  * @brief Take a semaphore.
@@ -185,23 +175,22 @@ void FreeRTOS::Semaphore::giveFromISR() {
  * @param [in] owner The new owner (for debugging)
  * @return True if we took the semaphore.
  */
-bool FreeRTOS::Semaphore::take(std::string owner) {
-	log_v("Semaphore taking: %s for %s", toString().c_str(), owner.c_str());
-	bool rc = false;
-	if (m_usePthreads) {
-		pthread_mutex_lock(&m_pthread_mutex);
-	} else {
-		rc = ::xSemaphoreTake(m_semaphore, portMAX_DELAY) == pdTRUE;
-	}
-	if (rc) {
-		m_owner = owner;
-		log_v("Semaphore taken:  %s", toString().c_str());
-	} else {
-		log_e("Semaphore NOT taken:  %s", toString().c_str());
-	}
-	return rc;
-} // Semaphore::take
-
+bool FreeRTOS::Semaphore::take(String owner) {
+  log_v("Semaphore taking: %s for %s", toString().c_str(), owner.c_str());
+  bool rc = false;
+  if (m_usePthreads) {
+    pthread_mutex_lock(&m_pthread_mutex);
+  } else {
+    rc = ::xSemaphoreTake(m_semaphore, portMAX_DELAY) == pdTRUE;
+  }
+  if (rc) {
+    m_owner = owner;
+    log_v("Semaphore taken:  %s", toString().c_str());
+  } else {
+    log_e("Semaphore NOT taken:  %s", toString().c_str());
+  }
+  return rc;
+}  // Semaphore::take
 
 /**
  * @brief Take a semaphore.
@@ -210,62 +199,61 @@ bool FreeRTOS::Semaphore::take(std::string owner) {
  * @param [in] owner The new owner (for debugging)
  * @return True if we took the semaphore.
  */
-bool FreeRTOS::Semaphore::take(uint32_t timeoutMs, std::string owner) {
-	log_v("Semaphore taking: %s for %s", toString().c_str(), owner.c_str());
-	bool rc = false;
-	if (m_usePthreads) {
-		assert(false);  // We apparently don't have a timed wait for pthreads.
-	} else {
-		rc = ::xSemaphoreTake(m_semaphore, timeoutMs / portTICK_PERIOD_MS) == pdTRUE;
-	}
-	if (rc) {
-		m_owner = owner;
-		log_v("Semaphore taken:  %s", toString().c_str());
-	} else {
-		log_e("Semaphore NOT taken:  %s", toString().c_str());
-	}
-	return rc;
-} // Semaphore::take
-
-
+bool FreeRTOS::Semaphore::take(uint32_t timeoutMs, String owner) {
+  log_v("Semaphore taking: %s for %s", toString().c_str(), owner.c_str());
+  bool rc = false;
+  if (m_usePthreads) {
+    assert(false);  // We apparently don't have a timed wait for pthreads.
+  } else {
+    rc = ::xSemaphoreTake(m_semaphore, timeoutMs / portTICK_PERIOD_MS) == pdTRUE;
+  }
+  if (rc) {
+    m_owner = owner;
+    log_v("Semaphore taken:  %s", toString().c_str());
+  } else {
+    log_e("Semaphore NOT taken:  %s", toString().c_str());
+  }
+  return rc;
+}  // Semaphore::take
 
 /**
  * @brief Create a string representation of the semaphore.
  * @return A string representation of the semaphore.
  */
-std::string FreeRTOS::Semaphore::toString() {
-	char hex[9];
-	std::string res = "name: " + m_name + " (0x";
-	snprintf(hex, sizeof(hex), "%08x", (uint32_t)m_semaphore);
-	res += hex;
-	res += "), owner: " + m_owner;
-	return res;
-} // toString
-
+String FreeRTOS::Semaphore::toString() {
+  char hex[9];
+  String res = "name: " + m_name + " (0x";
+  snprintf(hex, sizeof(hex), "%08lx", (uint32_t)m_semaphore);
+  res += hex;
+  res += "), owner: " + m_owner;
+  return res;
+}  // toString
 
 /**
  * @brief Set the name of the semaphore.
  * @param [in] name The name of the semaphore.
  */
-void FreeRTOS::Semaphore::setName(std::string name) {
-	m_name = name;
-} // setName
-
+void FreeRTOS::Semaphore::setName(String name) {
+  m_name = name;
+}  // setName
 
 /**
  * @brief Create a ring buffer.
  * @param [in] length The amount of storage to allocate for the ring buffer.
  * @param [in] type The type of buffer.  One of RINGBUF_TYPE_NOSPLIT, RINGBUF_TYPE_ALLOWSPLIT, RINGBUF_TYPE_BYTEBUF.
  */
-Ringbuffer::Ringbuffer(size_t length, ringbuf_type_t type) {
-	m_handle = ::xRingbufferCreate(length, type);
-} // Ringbuffer
-
+#ifdef ESP_IDF_VERSION_MAJOR
+Ringbuffer::Ringbuffer(size_t length, RingbufferType_t type)
+#else
+Ringbuffer::Ringbuffer(size_t length, ringbuf_type_t type)
+#endif
+{
+  m_handle = ::xRingbufferCreate(length, type);
+}  // Ringbuffer
 
 Ringbuffer::~Ringbuffer() {
-	::vRingbufferDelete(m_handle);
-} // ~Ringbuffer
-
+  ::vRingbufferDelete(m_handle);
+}  // ~Ringbuffer
 
 /**
  * @brief Receive data from the buffer.
@@ -273,19 +261,17 @@ Ringbuffer::~Ringbuffer() {
  * @param [in] wait How long to wait.
  * @return A pointer to the storage retrieved.
  */
-void* Ringbuffer::receive(size_t* size, TickType_t wait) {
-	return ::xRingbufferReceive(m_handle, size, wait);
-} // receive
-
+void *Ringbuffer::receive(size_t *size, TickType_t wait) {
+  return ::xRingbufferReceive(m_handle, size, wait);
+}  // receive
 
 /**
  * @brief Return an item.
  * @param [in] item The item to be returned/released.
  */
-void Ringbuffer::returnItem(void* item) {
-	::vRingbufferReturnItem(m_handle, item);
-} // returnItem
-
+void Ringbuffer::returnItem(void *item) {
+  ::vRingbufferReturnItem(m_handle, item);
+}  // returnItem
 
 /**
  * @brief Send data to the buffer.
@@ -294,8 +280,6 @@ void Ringbuffer::returnItem(void* item) {
  * @param [in] wait How long to wait before giving up.  The default is to wait indefinitely.
  * @return
  */
-bool Ringbuffer::send(void* data, size_t length, TickType_t wait) {
-	return ::xRingbufferSend(m_handle, data, length, wait) == pdTRUE;
-} // send
-
-
+bool Ringbuffer::send(void *data, size_t length, TickType_t wait) {
+  return ::xRingbufferSend(m_handle, data, length, wait) == pdTRUE;
+}  // send
diff --git a/libraries/BLE/src/FreeRTOS.h b/libraries/BLE/src/FreeRTOS.h
deleted file mode 100644
index 4d089c81db6..00000000000
--- a/libraries/BLE/src/FreeRTOS.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * FreeRTOS.h
- *
- *  Created on: Feb 24, 2017
- *      Author: kolban
- */
-
-#ifndef MAIN_FREERTOS_H_
-#define MAIN_FREERTOS_H_
-#include <stdint.h>
-#include <string>
-#include <pthread.h>
-
-#include <freertos/FreeRTOS.h>   // Include the base FreeRTOS definitions.
-#include <freertos/task.h>       // Include the task definitions.
-#include <freertos/semphr.h>     // Include the semaphore definitions.
-#include <freertos/ringbuf.h>    // Include the ringbuffer definitions.
-
-
-/**
- * @brief Interface to %FreeRTOS functions.
- */
-class FreeRTOS {
-public:
-	static void sleep(uint32_t ms);
-	static void startTask(void task(void*), std::string taskName, void* param = nullptr, uint32_t stackSize = 2048);
-	static void deleteTask(TaskHandle_t pTask = nullptr);
-
-	static uint32_t getTimeSinceStart();
-
-	class Semaphore {
-	public:
-		Semaphore(std::string owner = "<Unknown>");
-		~Semaphore();
-		void        give();
-		void        give(uint32_t value);
-		void        giveFromISR();
-		void        setName(std::string name);
-		bool        take(std::string owner = "<Unknown>");
-		bool        take(uint32_t timeoutMs, std::string owner = "<Unknown>");
-		std::string toString();
-		uint32_t	wait(std::string owner = "<Unknown>");
-		bool		timedWait(std::string owner = "<Unknown>", uint32_t timeoutMs = portMAX_DELAY);
-		uint32_t	value(){ return m_value; };
-
-	private:
-		SemaphoreHandle_t m_semaphore;
-		pthread_mutex_t   m_pthread_mutex;
-		std::string       m_name;
-		std::string       m_owner;
-		uint32_t          m_value;
-		bool              m_usePthreads;
-
-	};
-};
-
-
-/**
- * @brief Ringbuffer.
- */
-class Ringbuffer {
-public:
-	Ringbuffer(size_t length, ringbuf_type_t type = RINGBUF_TYPE_NOSPLIT);
-	~Ringbuffer();
-
-	void*    receive(size_t* size, TickType_t wait = portMAX_DELAY);
-	void     returnItem(void* item);
-	bool     send(void* data, size_t length, TickType_t wait = portMAX_DELAY);
-private:
-	RingbufHandle_t m_handle;
-};
-
-#endif /* MAIN_FREERTOS_H_ */
diff --git a/libraries/BLE/src/GeneralUtils.cpp b/libraries/BLE/src/GeneralUtils.cpp
index 02736b81b1a..1bb474fba41 100644
--- a/libraries/BLE/src/GeneralUtils.cpp
+++ b/libraries/BLE/src/GeneralUtils.cpp
@@ -12,91 +12,89 @@
 #include <string>
 #include <sstream>
 #include <iomanip>
-#include "FreeRTOS.h"
+#include "RTOS.h"
 #include <esp_err.h>
 #include <nvs.h>
 #include <esp_wifi.h>
 #include <esp_heap_caps.h>
 #include <esp_system.h>
+#include "esp_chip_info.h"
 #include "esp32-hal-log.h"
 
 static const char kBase64Alphabet[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
-	"abcdefghijklmnopqrstuvwxyz"
-	"0123456789+/";
+                                      "abcdefghijklmnopqrstuvwxyz"
+                                      "0123456789+/";
 
 static int base64EncodedLength(size_t length) {
-	return (length + 2 - ((length + 2) % 3)) / 3 * 4;
-} // base64EncodedLength
-
-
-static int base64EncodedLength(const std::string& in) {
-	return base64EncodedLength(in.length());
-} // base64EncodedLength
-
-
-static void a3_to_a4(unsigned char* a4, unsigned char* a3) {
-	a4[0] = (a3[0] & 0xfc) >> 2;
-	a4[1] = ((a3[0] & 0x03) << 4) + ((a3[1] & 0xf0) >> 4);
-	a4[2] = ((a3[1] & 0x0f) << 2) + ((a3[2] & 0xc0) >> 6);
-	a4[3] = (a3[2] & 0x3f);
-} // a3_to_a4
-
-
-static void a4_to_a3(unsigned char* a3, unsigned char* a4) {
-	a3[0] = (a4[0] << 2) + ((a4[1] & 0x30) >> 4);
-	a3[1] = ((a4[1] & 0xf) << 4) + ((a4[2] & 0x3c) >> 2);
-	a3[2] = ((a4[2] & 0x3) << 6) + a4[3];
-} // a4_to_a3
-
+  return (length + 2 - ((length + 2) % 3)) / 3 * 4;
+}  // base64EncodedLength
+
+static int base64EncodedLength(const String &in) {
+  return base64EncodedLength(in.length());
+}  // base64EncodedLength
+
+static void a3_to_a4(unsigned char *a4, unsigned char *a3) {
+  a4[0] = (a3[0] & 0xfc) >> 2;
+  a4[1] = ((a3[0] & 0x03) << 4) + ((a3[1] & 0xf0) >> 4);
+  a4[2] = ((a3[1] & 0x0f) << 2) + ((a3[2] & 0xc0) >> 6);
+  a4[3] = (a3[2] & 0x3f);
+}  // a3_to_a4
+
+static void a4_to_a3(unsigned char *a3, unsigned char *a4) {
+  a3[0] = (a4[0] << 2) + ((a4[1] & 0x30) >> 4);
+  a3[1] = ((a4[1] & 0xf) << 4) + ((a4[2] & 0x3c) >> 2);
+  a3[2] = ((a4[2] & 0x3) << 6) + a4[3];
+}  // a4_to_a3
 
 /**
  * @brief Encode a string into base 64.
  * @param [in] in
  * @param [out] out
  */
-bool GeneralUtils::base64Encode(const std::string& in, std::string* out) {
-	int i = 0, j = 0;
-	size_t enc_len = 0;
-	unsigned char a3[3];
-	unsigned char a4[4];
-
-	out->resize(base64EncodedLength(in));
-
-	int input_len = in.size();
-	std::string::const_iterator input = in.begin();
-
-	while (input_len--) {
-		a3[i++] = *(input++);
-		if (i == 3) {
-			a3_to_a4(a4, a3);
-
-			for (i = 0; i < 4; i++) {
-				(*out)[enc_len++] = kBase64Alphabet[a4[i]];
-			}
-
-			i = 0;
-		}
-	}
-
-	if (i) {
-		for (j = i; j < 3; j++) {
-			a3[j] = '\0';
-		}
-
-		a3_to_a4(a4, a3);
-
-		for (j = 0; j < i + 1; j++) {
-			(*out)[enc_len++] = kBase64Alphabet[a4[j]];
-		}
-
-		while ((i++ < 3)) {
-			(*out)[enc_len++] = '=';
-		}
-	}
-
-	return (enc_len == out->size());
-} // base64Encode
-
+bool GeneralUtils::base64Encode(const String &in, String *out) {
+  std::string std_in(in.c_str());
+  std::string std_out(out->c_str());
+  int i = 0, j = 0;
+  size_t enc_len = 0;
+  unsigned char a3[3];
+  unsigned char a4[4];
+  std_out.resize(base64EncodedLength(in));
+
+  int input_len = std_in.length();
+  std::string::const_iterator input = std_in.begin();
+
+  while (input_len--) {
+    a3[i++] = *(input++);
+    if (i == 3) {
+      a3_to_a4(a4, a3);
+
+      for (i = 0; i < 4; i++) {
+        (std_out)[enc_len++] = kBase64Alphabet[a4[i]];
+      }
+
+      i = 0;
+    }
+  }
+
+  if (i) {
+    for (j = i; j < 3; j++) {
+      a3[j] = '\0';
+    }
+
+    a3_to_a4(a4, a3);
+
+    for (j = 0; j < i + 1; j++) {
+      (std_out)[enc_len++] = kBase64Alphabet[a4[j]];
+    }
+
+    while ((i++ < 3)) {
+      (std_out)[enc_len++] = '=';
+    }
+  }
+  *out = String(std_out.c_str());
+
+  return (enc_len == out->length());
+}  // base64Encode
 
 /**
  * @brief Dump general info to the log.
@@ -104,15 +102,14 @@ bool GeneralUtils::base64Encode(const std::string& in, std::string* out) {
  * * Amount of free RAM
  */
 void GeneralUtils::dumpInfo() {
-	esp_chip_info_t chipInfo;
-	esp_chip_info(&chipInfo);
-	log_v("--- dumpInfo ---");
-	log_v("Free heap: %d", heap_caps_get_free_size(MALLOC_CAP_8BIT));
-	log_v("Chip Info: Model: %d, cores: %d, revision: %d", chipInfo.model, chipInfo.cores, chipInfo.revision);
-	log_v("ESP-IDF version: %s", esp_get_idf_version());
-	log_v("---");
-} // dumpInfo
-
+  esp_chip_info_t chipInfo;
+  esp_chip_info(&chipInfo);
+  log_v("--- dumpInfo ---");
+  log_v("Free heap: %d", heap_caps_get_free_size(MALLOC_CAP_8BIT));
+  log_v("Chip Info: Model: %d, cores: %d, revision: %d", chipInfo.model, chipInfo.cores, chipInfo.revision);
+  log_v("ESP-IDF version: %s", esp_get_idf_version());
+  log_v("---");
+}  // dumpInfo
 
 /**
  * @brief Does the string end with a specific character?
@@ -120,99 +117,111 @@ void GeneralUtils::dumpInfo() {
  * @param [in] c The character to look form.
  * @return True if the string ends with the given character.
  */
-bool GeneralUtils::endsWith(std::string str, char c) {
-	if (str.empty()) {
-		return false;
-	}
-	if (str.at(str.length() - 1) == c) {
-		return true;
-	}
-	return false;
-} // endsWidth
-
+bool GeneralUtils::endsWith(String str, char c) {
+  if (str.length() == 0) {
+    return false;
+  }
+  if (str.charAt(str.length() - 1) == c) {
+    return true;
+  }
+  return false;
+}  // endsWidth
 
-static int DecodedLength(const std::string& in) {
+/*
+static int DecodedLength(const String& in) {
 	int numEq = 0;
-	int n = (int) in.size();
+	int n = (int) in.length();
 
-	for (std::string::const_reverse_iterator it = in.rbegin(); *it == '='; ++it) {
+	//for (String::const_reverse_iterator it = in.rbegin(); *it == '='; ++it) {
+	for (int it = in.length()-1; in.charAt(it) == '='; --it) {
 		++numEq;
 	}
 	return ((6 * n) / 8) - numEq;
 } // DecodedLength
-
+*/
 
 static unsigned char b64_lookup(unsigned char c) {
-	if(c >='A' && c <='Z') return c - 'A';
-	if(c >='a' && c <='z') return c - 71;
-	if(c >='0' && c <='9') return c + 4;
-	if(c == '+') return 62;
-	if(c == '/') return 63;
-	return 255;
-}; // b64_lookup
-
+  if (c >= 'A' && c <= 'Z') {
+    return c - 'A';
+  }
+  if (c >= 'a' && c <= 'z') {
+    return c - 71;
+  }
+  if (c >= '0' && c <= '9') {
+    return c + 4;
+  }
+  if (c == '+') {
+    return 62;
+  }
+  if (c == '/') {
+    return 63;
+  }
+  return 255;
+};  // b64_lookup
 
 /**
  * @brief Decode a chunk of data that is base64 encoded.
  * @param [in] in The string to be decoded.
  * @param [out] out The resulting data.
  */
-bool GeneralUtils::base64Decode(const std::string& in, std::string* out) {
-	int i = 0, j = 0;
-	size_t dec_len = 0;
-	unsigned char a3[3];
-	unsigned char a4[4];
+bool GeneralUtils::base64Decode(const String &in, String *out) {
+  int i = 0, j = 0;
+  size_t dec_len = 0;
+  unsigned char a3[3];
+  unsigned char a4[4];
 
-	int input_len = in.size();
-	std::string::const_iterator input = in.begin();
+  int input_len = in.length();
+  int input_iterator = 0;
 
-	out->resize(DecodedLength(in));
+  //out->resize(DecodedLength(in));
 
-	while (input_len--) {
-		if (*input == '=') {
-			break;
-		}
+  while (input_len--) {
+    //if (*input == '=') {
+    if (in[input_iterator] == '=') {
+      break;
+    }
 
-		a4[i++] = *(input++);
-		if (i == 4) {
-			for (i = 0; i <4; i++) {
-				a4[i] = b64_lookup(a4[i]);
-			}
+    a4[i++] = in[input_iterator++];
+    if (i == 4) {
+      for (i = 0; i < 4; i++) {
+        a4[i] = b64_lookup(a4[i]);
+      }
 
-			a4_to_a3(a3,a4);
+      a4_to_a3(a3, a4);
 
-			for (i = 0; i < 3; i++) {
-				(*out)[dec_len++] = a3[i];
-			}
+      for (i = 0; i < 3; i++) {
+        out->concat(a3[i]);
+        dec_len++;
+      }
 
-			i = 0;
-		}
-	}
+      i = 0;
+    }
+  }
 
-	if (i) {
-		for (j = i; j < 4; j++) {
-			a4[j] = '\0';
-		}
+  if (i) {
+    for (j = i; j < 4; j++) {
+      a4[j] = '\0';
+    }
 
-		for (j = 0; j < 4; j++) {
-			a4[j] = b64_lookup(a4[j]);
-		}
+    for (j = 0; j < 4; j++) {
+      a4[j] = b64_lookup(a4[j]);
+    }
 
-		a4_to_a3(a3,a4);
+    a4_to_a3(a3, a4);
 
-		for (j = 0; j < i - 1; j++) {
-			(*out)[dec_len++] = a3[j];
-		}
-	}
+    for (j = 0; j < i - 1; j++) {
+      (*out)[dec_len++] = a3[j];
+    }
+  }
 
-	return (dec_len == out->size());
- } // base64Decode
+  return (dec_len == out->length());
+}  // base64Decode
 
 /*
 void GeneralUtils::hexDump(uint8_t* pData, uint32_t length) {
 	uint32_t index=0;
-	std::stringstream ascii;
-	std::stringstream hex;
+	Stringstream ascii;
+	Stringstream hex;
 	char asciiBuf[80];
 	char hexBuf[80];
 	hex.str("");
@@ -250,8 +259,8 @@ void GeneralUtils::hexDump(uint8_t* pData, uint32_t length) {
 /*
 void GeneralUtils::hexDump(uint8_t* pData, uint32_t length) {
 	uint32_t index=0;
-	static std::stringstream ascii;
-	static std::stringstream hex;
+	static Stringstream ascii;
+	static Stringstream hex;
 	hex.str("");
 	ascii.str("");
 	while(index < length) {
@@ -279,7 +288,6 @@ void GeneralUtils::hexDump(uint8_t* pData, uint32_t length) {
 }
 */
 
-
 /**
  * @brief Dump a representation of binary data to the console.
  *
@@ -287,58 +295,56 @@ void GeneralUtils::hexDump(uint8_t* pData, uint32_t length) {
  * @param [in] length Length of the data (in bytes) to be logged.
  * @return N/A.
  */
-void GeneralUtils::hexDump(const uint8_t* pData, uint32_t length) {
-	char ascii[80];
-	char hex[80];
-	char tempBuf[80];
-	uint32_t lineNumber = 0;
-
-	log_v("     00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f");
-	log_v("     -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --");
-	strcpy(ascii, "");
-	strcpy(hex, "");
-	uint32_t index = 0;
-	while (index < length) {
-		sprintf(tempBuf, "%.2x ", pData[index]);
-		strcat(hex, tempBuf);
-		if (isprint(pData[index])) {
-			sprintf(tempBuf, "%c", pData[index]);
-		} else {
-			sprintf(tempBuf, ".");
-		}
-		strcat(ascii, tempBuf);
-		index++;
-		if (index % 16 == 0) {
-			log_v("%.4x %s %s", lineNumber * 16, hex, ascii);
-			strcpy(ascii, "");
-			strcpy(hex, "");
-			lineNumber++;
-		}
-	}
-	if (index %16 != 0) {
-		while (index % 16 != 0) {
-			strcat(hex, "   ");
-			index++;
-		}
-		log_v("%.4x %s %s", lineNumber * 16, hex, ascii);
-	}
-} // hexDump
-
+void GeneralUtils::hexDump(const uint8_t *pData, uint32_t length) {
+  char ascii[80];
+  char hex[80];
+  char tempBuf[80];
+  uint32_t lineNumber = 0;
+
+  log_v("     00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f");
+  log_v("     -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --");
+  strcpy(ascii, "");
+  strcpy(hex, "");
+  uint32_t index = 0;
+  while (index < length) {
+    sprintf(tempBuf, "%.2x ", pData[index]);
+    strcat(hex, tempBuf);
+    if (isprint(pData[index])) {
+      sprintf(tempBuf, "%c", pData[index]);
+    } else {
+      sprintf(tempBuf, ".");
+    }
+    strcat(ascii, tempBuf);
+    index++;
+    if (index % 16 == 0) {
+      log_v("%.4x %s %s", lineNumber * 16, hex, ascii);
+      strcpy(ascii, "");
+      strcpy(hex, "");
+      lineNumber++;
+    }
+  }
+  if (index % 16 != 0) {
+    while (index % 16 != 0) {
+      strcat(hex, "   ");
+      index++;
+    }
+    log_v("%.4x %s %s", lineNumber * 16, hex, ascii);
+  }
+}  // hexDump
 
 /**
  * @brief Convert an IP address to string.
  * @param ip The 4 byte IP address.
  * @return A string representation of the IP address.
  */
-std::string GeneralUtils::ipToString(uint8_t *ip) {
-	auto size = 16;
-	char *val = (char*)malloc(size);
-	snprintf(val, size, "%d.%d.%d.%d", ip[0], ip[1], ip[2], ip[3]);
-	std::string res(val);
-	free(val);
-	return res;
-} // ipToString
-
+String GeneralUtils::ipToString(uint8_t *ip) {
+  auto size = 16;
+  char *val = (char *)malloc(size);
+  snprintf(val, size, "%d.%d.%d.%d", ip[0], ip[1], ip[2], ip[3]);
+  String res(val);
+  free(val);
+  return res;
+}  // ipToString
 
 /**
  * @brief Split a string into parts based on a delimiter.
@@ -346,100 +352,67 @@ std::string GeneralUtils::ipToString(uint8_t *ip) {
  * @param [in] delimiter The delimiter characters.
  * @return A vector of strings that are the split of the input.
  */
-std::vector<std::string> GeneralUtils::split(std::string source, char delimiter) {
-	// See also: https://stackoverflow.com/questions/5167625/splitting-a-c-stdstring-using-tokens-e-g
-	std::vector<std::string> strings;
-	std::size_t current, previous = 0;
-	current = source.find(delimiter);
-	while (current != std::string::npos) {
-		strings.push_back(trim(source.substr(previous, current - previous)));
-		previous = current + 1;
-		current = source.find(delimiter, previous);
-	}
-	strings.push_back(trim(source.substr(previous, current - previous)));
-	return strings;
-} // split
-
+std::vector<String> GeneralUtils::split(String source, char delimiter) {
+  // See also: https://stackoverflow.com/questions/5167625/splitting-a-c-stdstring-using-tokens-e-g
+  std::vector<String> strings;
+  std::size_t current, previous = 0;
+  std::string std_source(source.c_str());
+  current = std_source.find(delimiter);
+  while (current != std::string::npos) {
+    strings.push_back(trim(source.substring(previous, current)));
+    previous = current + 1;
+    current = std_source.find(delimiter, previous);
+  }
+  strings.push_back(trim(source.substring(previous, current)));
+  return strings;
+}  // split
 
 /**
  * @brief Convert an ESP error code to a string.
  * @param [in] errCode The errCode to be converted.
  * @return A string representation of the error code.
  */
-const char* GeneralUtils::errorToString(esp_err_t errCode) {
-	switch (errCode) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case ESP_OK:
-			return "ESP_OK";
-		case ESP_FAIL:
-			return "ESP_FAIL";
-		case ESP_ERR_NO_MEM:
-			return "ESP_ERR_NO_MEM";
-		case ESP_ERR_INVALID_ARG:
-			return "ESP_ERR_INVALID_ARG";
-		case ESP_ERR_INVALID_SIZE:
-			return "ESP_ERR_INVALID_SIZE";
-		case ESP_ERR_INVALID_STATE:
-			return "ESP_ERR_INVALID_STATE";
-		case ESP_ERR_NOT_FOUND:
-			return "ESP_ERR_NOT_FOUND";
-		case ESP_ERR_NOT_SUPPORTED:
-			return "ESP_ERR_NOT_SUPPORTED";
-		case ESP_ERR_TIMEOUT:
-			return "ESP_ERR_TIMEOUT";
-		case ESP_ERR_NVS_NOT_INITIALIZED:
-			return "ESP_ERR_NVS_NOT_INITIALIZED";
-		case ESP_ERR_NVS_NOT_FOUND:
-			return "ESP_ERR_NVS_NOT_FOUND";
-		case ESP_ERR_NVS_TYPE_MISMATCH:
-			return "ESP_ERR_NVS_TYPE_MISMATCH";
-		case ESP_ERR_NVS_READ_ONLY:
-			return "ESP_ERR_NVS_READ_ONLY";
-		case ESP_ERR_NVS_NOT_ENOUGH_SPACE:
-			return "ESP_ERR_NVS_NOT_ENOUGH_SPACE";
-		case ESP_ERR_NVS_INVALID_NAME:
-			return "ESP_ERR_NVS_INVALID_NAME";
-		case ESP_ERR_NVS_INVALID_HANDLE:
-			return "ESP_ERR_NVS_INVALID_HANDLE";
-		case ESP_ERR_NVS_REMOVE_FAILED:
-			return "ESP_ERR_NVS_REMOVE_FAILED";
-		case ESP_ERR_NVS_KEY_TOO_LONG:
-			return "ESP_ERR_NVS_KEY_TOO_LONG";
-		case ESP_ERR_NVS_PAGE_FULL:
-			return "ESP_ERR_NVS_PAGE_FULL";
-		case ESP_ERR_NVS_INVALID_STATE:
-			return "ESP_ERR_NVS_INVALID_STATE";
-		case ESP_ERR_NVS_INVALID_LENGTH:
-			return "ESP_ERR_NVS_INVALID_LENGTH";
-		case ESP_ERR_WIFI_NOT_INIT:
-			return "ESP_ERR_WIFI_NOT_INIT";
-		//case ESP_ERR_WIFI_NOT_START:
-		//	return "ESP_ERR_WIFI_NOT_START";
-		case ESP_ERR_WIFI_IF:
-			return "ESP_ERR_WIFI_IF";
-		case ESP_ERR_WIFI_MODE:
-			return "ESP_ERR_WIFI_MODE";
-		case ESP_ERR_WIFI_STATE:
-			return "ESP_ERR_WIFI_STATE";
-		case ESP_ERR_WIFI_CONN:
-			return "ESP_ERR_WIFI_CONN";
-		case ESP_ERR_WIFI_NVS:
-			return "ESP_ERR_WIFI_NVS";
-		case ESP_ERR_WIFI_MAC:
-			return "ESP_ERR_WIFI_MAC";
-		case ESP_ERR_WIFI_SSID:
-			return "ESP_ERR_WIFI_SSID";
-		case ESP_ERR_WIFI_PASSWORD:
-			return "ESP_ERR_WIFI_PASSWORD";
-		case ESP_ERR_WIFI_TIMEOUT:
-			return "ESP_ERR_WIFI_TIMEOUT";
-		case ESP_ERR_WIFI_WAKE_FAIL:
-			return "ESP_ERR_WIFI_WAKE_FAIL";
+const char *GeneralUtils::errorToString(esp_err_t errCode) {
+  switch (errCode) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case ESP_OK:                       return "ESP_OK";
+    case ESP_FAIL:                     return "ESP_FAIL";
+    case ESP_ERR_NO_MEM:               return "ESP_ERR_NO_MEM";
+    case ESP_ERR_INVALID_ARG:          return "ESP_ERR_INVALID_ARG";
+    case ESP_ERR_INVALID_SIZE:         return "ESP_ERR_INVALID_SIZE";
+    case ESP_ERR_INVALID_STATE:        return "ESP_ERR_INVALID_STATE";
+    case ESP_ERR_NOT_FOUND:            return "ESP_ERR_NOT_FOUND";
+    case ESP_ERR_NOT_SUPPORTED:        return "ESP_ERR_NOT_SUPPORTED";
+    case ESP_ERR_TIMEOUT:              return "ESP_ERR_TIMEOUT";
+    case ESP_ERR_NVS_NOT_INITIALIZED:  return "ESP_ERR_NVS_NOT_INITIALIZED";
+    case ESP_ERR_NVS_NOT_FOUND:        return "ESP_ERR_NVS_NOT_FOUND";
+    case ESP_ERR_NVS_TYPE_MISMATCH:    return "ESP_ERR_NVS_TYPE_MISMATCH";
+    case ESP_ERR_NVS_READ_ONLY:        return "ESP_ERR_NVS_READ_ONLY";
+    case ESP_ERR_NVS_NOT_ENOUGH_SPACE: return "ESP_ERR_NVS_NOT_ENOUGH_SPACE";
+    case ESP_ERR_NVS_INVALID_NAME:     return "ESP_ERR_NVS_INVALID_NAME";
+    case ESP_ERR_NVS_INVALID_HANDLE:   return "ESP_ERR_NVS_INVALID_HANDLE";
+    case ESP_ERR_NVS_REMOVE_FAILED:    return "ESP_ERR_NVS_REMOVE_FAILED";
+    case ESP_ERR_NVS_KEY_TOO_LONG:     return "ESP_ERR_NVS_KEY_TOO_LONG";
+    case ESP_ERR_NVS_PAGE_FULL:        return "ESP_ERR_NVS_PAGE_FULL";
+    case ESP_ERR_NVS_INVALID_STATE:    return "ESP_ERR_NVS_INVALID_STATE";
+    case ESP_ERR_NVS_INVALID_LENGTH:   return "ESP_ERR_NVS_INVALID_LENGTH";
+    case ESP_ERR_WIFI_NOT_INIT:        return "ESP_ERR_WIFI_NOT_INIT";
+    //case ESP_ERR_WIFI_NOT_START:
+    //	return "ESP_ERR_WIFI_NOT_START";
+    case ESP_ERR_WIFI_IF:        return "ESP_ERR_WIFI_IF";
+    case ESP_ERR_WIFI_MODE:      return "ESP_ERR_WIFI_MODE";
+    case ESP_ERR_WIFI_STATE:     return "ESP_ERR_WIFI_STATE";
+    case ESP_ERR_WIFI_CONN:      return "ESP_ERR_WIFI_CONN";
+    case ESP_ERR_WIFI_NVS:       return "ESP_ERR_WIFI_NVS";
+    case ESP_ERR_WIFI_MAC:       return "ESP_ERR_WIFI_MAC";
+    case ESP_ERR_WIFI_SSID:      return "ESP_ERR_WIFI_SSID";
+    case ESP_ERR_WIFI_PASSWORD:  return "ESP_ERR_WIFI_PASSWORD";
+    case ESP_ERR_WIFI_TIMEOUT:   return "ESP_ERR_WIFI_TIMEOUT";
+    case ESP_ERR_WIFI_WAKE_FAIL: return "ESP_ERR_WIFI_WAKE_FAIL";
 #endif
-		default:
-			return "Unknown ESP_ERR error";
-		}
-} // errorToString
+    default: return "Unknown ESP_ERR error";
+  }
+}  // errorToString
 
 /**
  * @brief Convert a wifi_err_reason_t code to a string.
@@ -448,94 +421,70 @@ const char* GeneralUtils::errorToString(esp_err_t errCode) {
  *
  * @note: wifi_err_reason_t values as of April 2018 are: (1-24, 200-204) and are defined in ~/esp-idf/components/esp32/include/esp_wifi_types.h.
  */
-const char* GeneralUtils::wifiErrorToString(uint8_t errCode) {
-	if (errCode == ESP_OK) return "ESP_OK (received SYSTEM_EVENT_STA_GOT_IP event)";
-	if (errCode == UINT8_MAX) return "Not Connected (default value)";
-
-	switch ((wifi_err_reason_t) errCode) {
-#if CONFIG_LOG_DEFAULT_LEVEL > 4
-		case WIFI_REASON_UNSPECIFIED:
-			return "WIFI_REASON_UNSPECIFIED";
-		case WIFI_REASON_AUTH_EXPIRE:
-			return "WIFI_REASON_AUTH_EXPIRE";
-		case WIFI_REASON_AUTH_LEAVE:
-			return "WIFI_REASON_AUTH_LEAVE";
-		case WIFI_REASON_ASSOC_EXPIRE:
-			return "WIFI_REASON_ASSOC_EXPIRE";
-		case WIFI_REASON_ASSOC_TOOMANY:
-			return "WIFI_REASON_ASSOC_TOOMANY";
-		case WIFI_REASON_NOT_AUTHED:
-			return "WIFI_REASON_NOT_AUTHED";
-		case WIFI_REASON_NOT_ASSOCED:
-			return "WIFI_REASON_NOT_ASSOCED";
-		case WIFI_REASON_ASSOC_LEAVE:
-			return "WIFI_REASON_ASSOC_LEAVE";
-		case WIFI_REASON_ASSOC_NOT_AUTHED:
-			return "WIFI_REASON_ASSOC_NOT_AUTHED";
-		case WIFI_REASON_DISASSOC_PWRCAP_BAD:
-			return "WIFI_REASON_DISASSOC_PWRCAP_BAD";
-		case WIFI_REASON_DISASSOC_SUPCHAN_BAD:
-			return "WIFI_REASON_DISASSOC_SUPCHAN_BAD";
-		case WIFI_REASON_IE_INVALID:
-			return "WIFI_REASON_IE_INVALID";
-		case WIFI_REASON_MIC_FAILURE:
-			return "WIFI_REASON_MIC_FAILURE";
-		case WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT:
-			return "WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT";
-		case WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT:
-			return "WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT";
-		case WIFI_REASON_IE_IN_4WAY_DIFFERS:
-			return "WIFI_REASON_IE_IN_4WAY_DIFFERS";
-		case WIFI_REASON_GROUP_CIPHER_INVALID:
-			return "WIFI_REASON_GROUP_CIPHER_INVALID";
-		case WIFI_REASON_PAIRWISE_CIPHER_INVALID:
-			return "WIFI_REASON_PAIRWISE_CIPHER_INVALID";
-		case WIFI_REASON_AKMP_INVALID:
-			return "WIFI_REASON_AKMP_INVALID";
-		case WIFI_REASON_UNSUPP_RSN_IE_VERSION:
-			return "WIFI_REASON_UNSUPP_RSN_IE_VERSION";
-		case WIFI_REASON_INVALID_RSN_IE_CAP:
-			return "WIFI_REASON_INVALID_RSN_IE_CAP";
-		case WIFI_REASON_802_1X_AUTH_FAILED:
-			return "WIFI_REASON_802_1X_AUTH_FAILED";
-		case WIFI_REASON_CIPHER_SUITE_REJECTED:
-			return "WIFI_REASON_CIPHER_SUITE_REJECTED";
-		case WIFI_REASON_BEACON_TIMEOUT:
-			return "WIFI_REASON_BEACON_TIMEOUT";
-		case WIFI_REASON_NO_AP_FOUND:
-			return "WIFI_REASON_NO_AP_FOUND";
-		case WIFI_REASON_AUTH_FAIL:
-			return "WIFI_REASON_AUTH_FAIL";
-		case WIFI_REASON_ASSOC_FAIL:
-			return "WIFI_REASON_ASSOC_FAIL";
-		case WIFI_REASON_HANDSHAKE_TIMEOUT:
-			return "WIFI_REASON_HANDSHAKE_TIMEOUT";
+const char *GeneralUtils::wifiErrorToString(uint8_t errCode) {
+  if (errCode == ESP_OK) {
+    return "ESP_OK (received SYSTEM_EVENT_STA_GOT_IP event)";
+  }
+  if (errCode == UINT8_MAX) {
+    return "Not Connected (default value)";
+  }
+
+  switch ((wifi_err_reason_t)errCode) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+    case WIFI_REASON_UNSPECIFIED:              return "WIFI_REASON_UNSPECIFIED";
+    case WIFI_REASON_AUTH_EXPIRE:              return "WIFI_REASON_AUTH_EXPIRE";
+    case WIFI_REASON_AUTH_LEAVE:               return "WIFI_REASON_AUTH_LEAVE";
+    case WIFI_REASON_ASSOC_EXPIRE:             return "WIFI_REASON_ASSOC_EXPIRE";
+    case WIFI_REASON_ASSOC_TOOMANY:            return "WIFI_REASON_ASSOC_TOOMANY";
+    case WIFI_REASON_NOT_AUTHED:               return "WIFI_REASON_NOT_AUTHED";
+    case WIFI_REASON_NOT_ASSOCED:              return "WIFI_REASON_NOT_ASSOCED";
+    case WIFI_REASON_ASSOC_LEAVE:              return "WIFI_REASON_ASSOC_LEAVE";
+    case WIFI_REASON_ASSOC_NOT_AUTHED:         return "WIFI_REASON_ASSOC_NOT_AUTHED";
+    case WIFI_REASON_DISASSOC_PWRCAP_BAD:      return "WIFI_REASON_DISASSOC_PWRCAP_BAD";
+    case WIFI_REASON_DISASSOC_SUPCHAN_BAD:     return "WIFI_REASON_DISASSOC_SUPCHAN_BAD";
+    case WIFI_REASON_IE_INVALID:               return "WIFI_REASON_IE_INVALID";
+    case WIFI_REASON_MIC_FAILURE:              return "WIFI_REASON_MIC_FAILURE";
+    case WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT:   return "WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT";
+    case WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT: return "WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT";
+    case WIFI_REASON_IE_IN_4WAY_DIFFERS:       return "WIFI_REASON_IE_IN_4WAY_DIFFERS";
+    case WIFI_REASON_GROUP_CIPHER_INVALID:     return "WIFI_REASON_GROUP_CIPHER_INVALID";
+    case WIFI_REASON_PAIRWISE_CIPHER_INVALID:  return "WIFI_REASON_PAIRWISE_CIPHER_INVALID";
+    case WIFI_REASON_AKMP_INVALID:             return "WIFI_REASON_AKMP_INVALID";
+    case WIFI_REASON_UNSUPP_RSN_IE_VERSION:    return "WIFI_REASON_UNSUPP_RSN_IE_VERSION";
+    case WIFI_REASON_INVALID_RSN_IE_CAP:       return "WIFI_REASON_INVALID_RSN_IE_CAP";
+    case WIFI_REASON_802_1X_AUTH_FAILED:       return "WIFI_REASON_802_1X_AUTH_FAILED";
+    case WIFI_REASON_CIPHER_SUITE_REJECTED:    return "WIFI_REASON_CIPHER_SUITE_REJECTED";
+    case WIFI_REASON_BEACON_TIMEOUT:           return "WIFI_REASON_BEACON_TIMEOUT";
+    case WIFI_REASON_NO_AP_FOUND:              return "WIFI_REASON_NO_AP_FOUND";
+    case WIFI_REASON_AUTH_FAIL:                return "WIFI_REASON_AUTH_FAIL";
+    case WIFI_REASON_ASSOC_FAIL:               return "WIFI_REASON_ASSOC_FAIL";
+    case WIFI_REASON_HANDSHAKE_TIMEOUT:        return "WIFI_REASON_HANDSHAKE_TIMEOUT";
 #endif
-		default:
-			return "Unknown ESP_ERR error";
-	}
-} // wifiErrorToString
-
+    default: return "Unknown ESP_ERR error";
+  }
+}  // wifiErrorToString
 
 /**
  * @brief Convert a string to lower case.
  * @param [in] value The string to convert to lower case.
  * @return A lower case representation of the string.
  */
-std::string GeneralUtils::toLower(std::string& value) {
-	// Question: Could this be improved with a signature of:
-	// std::string& GeneralUtils::toLower(std::string& value)
-	std::transform(value.begin(), value.end(), value.begin(), ::tolower);
-	return value;
-} // toLower
-
+String GeneralUtils::toLower(String &value) {
+  // Question: Could this be improved with a signature of:
+  // String& GeneralUtils::toLower(String& value)
+  std::transform(value.begin(), value.end(), value.begin(), ::tolower);
+  return value;
+}  // toLower
 
 /**
  * @brief Remove white space from a string.
  */
-std::string GeneralUtils::trim(const std::string& str) {
-	size_t first = str.find_first_not_of(' ');
-	if (std::string::npos == first) return str;
-	size_t last = str.find_last_not_of(' ');
-	return str.substr(first, (last - first + 1));
-} // trim
+String GeneralUtils::trim(const String &str) {
+  std::string std_str(str.c_str());
+  size_t first = std_str.find_first_not_of(' ');
+  if (std::string::npos == first) {
+    return str;
+  }
+  size_t last = std_str.find_last_not_of(' ');
+  return str.substring(first, (last + 1));
+}  // trim
diff --git a/libraries/BLE/src/GeneralUtils.h b/libraries/BLE/src/GeneralUtils.h
index 8eecbd4d029..c22d6f98bdc 100644
--- a/libraries/BLE/src/GeneralUtils.h
+++ b/libraries/BLE/src/GeneralUtils.h
@@ -7,6 +7,7 @@
 
 #ifndef COMPONENTS_CPP_UTILS_GENERALUTILS_H_
 #define COMPONENTS_CPP_UTILS_GENERALUTILS_H_
+#include "Arduino.h"
 #include <stdint.h>
 #include <string>
 #include <esp_err.h>
@@ -18,18 +19,17 @@
  */
 class GeneralUtils {
 public:
-	static bool        base64Decode(const std::string& in, std::string* out);
-	static bool        base64Encode(const std::string& in, std::string* out);
-	static void        dumpInfo();
-	static bool        endsWith(std::string str, char c);
-	static const char* errorToString(esp_err_t errCode);
-	static const char* wifiErrorToString(uint8_t value);
-	static void        hexDump(const uint8_t* pData, uint32_t length);
-	static std::string ipToString(uint8_t* ip);
-	static std::vector<std::string> split(std::string source, char delimiter);
-	static std::string toLower(std::string& value);
-	static std::string trim(const std::string& str);
-
+  static bool base64Decode(const String &in, String *out);
+  static bool base64Encode(const String &in, String *out);
+  static void dumpInfo();
+  static bool endsWith(String str, char c);
+  static const char *errorToString(esp_err_t errCode);
+  static const char *wifiErrorToString(uint8_t value);
+  static void hexDump(const uint8_t *pData, uint32_t length);
+  static String ipToString(uint8_t *ip);
+  static std::vector<String> split(String source, char delimiter);
+  static String toLower(String &value);
+  static String trim(const String &str);
 };
 
 #endif /* COMPONENTS_CPP_UTILS_GENERALUTILS_H_ */
diff --git a/libraries/BLE/src/HIDKeyboardTypes.h b/libraries/BLE/src/HIDKeyboardTypes.h
index 4e221d57f8d..971d637f961 100644
--- a/libraries/BLE/src/HIDKeyboardTypes.h
+++ b/libraries/BLE/src/HIDKeyboardTypes.h
@@ -26,376 +26,381 @@
 
 /* Modifiers */
 enum MODIFIER_KEY {
-	KEY_CTRL = 1,
-	KEY_SHIFT = 2,
-	KEY_ALT = 4,
+  KEY_CTRL = 1,
+  KEY_SHIFT = 2,
+  KEY_ALT = 4,
 };
 
-
 enum MEDIA_KEY {
-    KEY_NEXT_TRACK,     /*!< next Track Button */
-    KEY_PREVIOUS_TRACK, /*!< Previous track Button */
-    KEY_STOP,           /*!< Stop Button */
-    KEY_PLAY_PAUSE,     /*!< Play/Pause Button */
-    KEY_MUTE,           /*!< Mute Button */
-    KEY_VOLUME_UP,      /*!< Volume Up Button */
-    KEY_VOLUME_DOWN,    /*!< Volume Down Button */
+  KEY_NEXT_TRACK,     /*!< next Track Button */
+  KEY_PREVIOUS_TRACK, /*!< Previous track Button */
+  KEY_STOP,           /*!< Stop Button */
+  KEY_PLAY_PAUSE,     /*!< Play/Pause Button */
+  KEY_MUTE,           /*!< Mute Button */
+  KEY_VOLUME_UP,      /*!< Volume Up Button */
+  KEY_VOLUME_DOWN,    /*!< Volume Down Button */
 };
 
 enum FUNCTION_KEY {
-	KEY_F1 = 128,   /* F1 key */
-	KEY_F2,		 /* F2 key */
-	KEY_F3,		 /* F3 key */
-	KEY_F4,		 /* F4 key */
-	KEY_F5,		 /* F5 key */
-	KEY_F6,		 /* F6 key */
-	KEY_F7,		 /* F7 key */
-	KEY_F8,		 /* F8 key */
-	KEY_F9,		 /* F9 key */
-	KEY_F10,		/* F10 key */
-	KEY_F11,		/* F11 key */
-	KEY_F12,		/* F12 key */
+  KEY_F1 = 128, /* F1 key */
+  KEY_F2,       /* F2 key */
+  KEY_F3,       /* F3 key */
+  KEY_F4,       /* F4 key */
+  KEY_F5,       /* F5 key */
+  KEY_F6,       /* F6 key */
+  KEY_F7,       /* F7 key */
+  KEY_F8,       /* F8 key */
+  KEY_F9,       /* F9 key */
+  KEY_F10,      /* F10 key */
+  KEY_F11,      /* F11 key */
+  KEY_F12,      /* F12 key */
 
-	KEY_PRINT_SCREEN,   /* Print Screen key */
-	KEY_SCROLL_LOCK,	/* Scroll lock */
-	KEY_CAPS_LOCK,	  /* caps lock */
-	KEY_NUM_LOCK,	   /* num lock */
-	KEY_INSERT,		 /* Insert key */
-	KEY_HOME,		   /* Home key */
-	KEY_PAGE_UP,		/* Page Up key */
-	KEY_PAGE_DOWN,	  /* Page Down key */
+  KEY_PRINT_SCREEN, /* Print Screen key */
+  KEY_SCROLL_LOCK,  /* Scroll lock */
+  KEY_CAPS_LOCK,    /* caps lock */
+  KEY_NUM_LOCK,     /* num lock */
+  KEY_INSERT,       /* Insert key */
+  KEY_HOME,         /* Home key */
+  KEY_PAGE_UP,      /* Page Up key */
+  KEY_PAGE_DOWN,    /* Page Down key */
 
-	RIGHT_ARROW,		/* Right arrow */
-	LEFT_ARROW,		 /* Left arrow */
-	DOWN_ARROW,		 /* Down arrow */
-	UP_ARROW,		   /* Up arrow */
+  RIGHT_ARROW, /* Right arrow */
+  LEFT_ARROW,  /* Left arrow */
+  DOWN_ARROW,  /* Down arrow */
+  UP_ARROW,    /* Up arrow */
 };
 
 typedef struct {
-	unsigned char usage;
-	unsigned char modifier;
+  unsigned char usage;
+  unsigned char modifier;
 } KEYMAP;
 
 #ifdef US_KEYBOARD
 /* US keyboard (as HID standard) */
 #define KEYMAP_SIZE (152)
 const KEYMAP keymap[KEYMAP_SIZE] = {
-    {0, 0},             /* NUL */
-    {0, 0},             /* SOH */
-    {0, 0},             /* STX */
-    {0, 0},             /* ETX */
-    {0, 0},             /* EOT */
-    {0, 0},             /* ENQ */
-    {0, 0},             /* ACK */
-    {0, 0},             /* BEL */
-    {0x2a, 0},          /* BS  */  /* Keyboard Delete (Backspace) */
-    {0x2b, 0},          /* TAB */  /* Keyboard Tab */
-    {0x28, 0},          /* LF  */  /* Keyboard Return (Enter) */
-    {0, 0},             /* VT  */
-    {0, 0},             /* FF  */
-    {0, 0},             /* CR  */
-    {0, 0},             /* SO  */
-    {0, 0},             /* SI  */
-    {0, 0},             /* DEL */
-    {0, 0},             /* DC1 */
-    {0, 0},             /* DC2 */
-    {0, 0},             /* DC3 */
-    {0, 0},             /* DC4 */
-    {0, 0},             /* NAK */
-    {0, 0},             /* SYN */
-    {0, 0},             /* ETB */
-    {0, 0},             /* CAN */
-    {0, 0},             /* EM  */
-    {0, 0},             /* SUB */
-    {0, 0},             /* ESC */
-    {0, 0},             /* FS  */
-    {0, 0},             /* GS  */
-    {0, 0},             /* RS  */
-    {0, 0},             /* US  */
-    {0x2c, 0},          /*   */
-    {0x1e, KEY_SHIFT},      /* ! */
-    {0x34, KEY_SHIFT},      /* " */
-    {0x20, KEY_SHIFT},      /* # */
-    {0x21, KEY_SHIFT},      /* $ */
-    {0x22, KEY_SHIFT},      /* % */
-    {0x24, KEY_SHIFT},      /* & */
-    {0x34, 0},          /* ' */
-    {0x26, KEY_SHIFT},      /* ( */
-    {0x27, KEY_SHIFT},      /* ) */
-    {0x25, KEY_SHIFT},      /* * */
-    {0x2e, KEY_SHIFT},      /* + */
-    {0x36, 0},          /* , */
-    {0x2d, 0},          /* - */
-    {0x37, 0},          /* . */
-    {0x38, 0},          /* / */
-    {0x27, 0},          /* 0 */
-    {0x1e, 0},          /* 1 */
-    {0x1f, 0},          /* 2 */
-    {0x20, 0},          /* 3 */
-    {0x21, 0},          /* 4 */
-    {0x22, 0},          /* 5 */
-    {0x23, 0},          /* 6 */
-    {0x24, 0},          /* 7 */
-    {0x25, 0},          /* 8 */
-    {0x26, 0},          /* 9 */
-    {0x33, KEY_SHIFT},      /* : */
-    {0x33, 0},          /* ; */
-    {0x36, KEY_SHIFT},      /* < */
-    {0x2e, 0},          /* = */
-    {0x37, KEY_SHIFT},      /* > */
-    {0x38, KEY_SHIFT},      /* ? */
-    {0x1f, KEY_SHIFT},      /* @ */
-    {0x04, KEY_SHIFT},      /* A */
-    {0x05, KEY_SHIFT},      /* B */
-    {0x06, KEY_SHIFT},      /* C */
-    {0x07, KEY_SHIFT},      /* D */
-    {0x08, KEY_SHIFT},      /* E */
-    {0x09, KEY_SHIFT},      /* F */
-    {0x0a, KEY_SHIFT},      /* G */
-    {0x0b, KEY_SHIFT},      /* H */
-    {0x0c, KEY_SHIFT},      /* I */
-    {0x0d, KEY_SHIFT},      /* J */
-    {0x0e, KEY_SHIFT},      /* K */
-    {0x0f, KEY_SHIFT},      /* L */
-    {0x10, KEY_SHIFT},      /* M */
-    {0x11, KEY_SHIFT},      /* N */
-    {0x12, KEY_SHIFT},      /* O */
-    {0x13, KEY_SHIFT},      /* P */
-    {0x14, KEY_SHIFT},      /* Q */
-    {0x15, KEY_SHIFT},      /* R */
-    {0x16, KEY_SHIFT},      /* S */
-    {0x17, KEY_SHIFT},      /* T */
-    {0x18, KEY_SHIFT},      /* U */
-    {0x19, KEY_SHIFT},      /* V */
-    {0x1a, KEY_SHIFT},      /* W */
-    {0x1b, KEY_SHIFT},      /* X */
-    {0x1c, KEY_SHIFT},      /* Y */
-    {0x1d, KEY_SHIFT},      /* Z */
-    {0x2f, 0},          /* [ */
-    {0x31, 0},          /* \ */
-    {0x30, 0},          /* ] */
-    {0x23, KEY_SHIFT},      /* ^ */
-    {0x2d, KEY_SHIFT},      /* _ */
-    {0x35, 0},          /* ` */
-    {0x04, 0},          /* a */
-    {0x05, 0},          /* b */
-    {0x06, 0},          /* c */
-    {0x07, 0},          /* d */
-    {0x08, 0},          /* e */
-    {0x09, 0},          /* f */
-    {0x0a, 0},          /* g */
-    {0x0b, 0},          /* h */
-    {0x0c, 0},          /* i */
-    {0x0d, 0},          /* j */
-    {0x0e, 0},          /* k */
-    {0x0f, 0},          /* l */
-    {0x10, 0},          /* m */
-    {0x11, 0},          /* n */
-    {0x12, 0},          /* o */
-    {0x13, 0},          /* p */
-    {0x14, 0},          /* q */
-    {0x15, 0},          /* r */
-    {0x16, 0},          /* s */
-    {0x17, 0},          /* t */
-    {0x18, 0},          /* u */
-    {0x19, 0},          /* v */
-    {0x1a, 0},          /* w */
-    {0x1b, 0},          /* x */
-    {0x1c, 0},          /* y */
-    {0x1d, 0},          /* z */
-    {0x2f, KEY_SHIFT},      /* { */
-    {0x31, KEY_SHIFT},      /* | */
-    {0x30, KEY_SHIFT},      /* } */
-    {0x35, KEY_SHIFT},      /* ~ */
-    {0,0},              /* DEL */
+  {0, 0}, /* NUL */
+  {0, 0}, /* SOH */
+  {0, 0}, /* STX */
+  {0, 0}, /* ETX */
+  {0, 0}, /* EOT */
+  {0, 0}, /* ENQ */
+  {0, 0}, /* ACK */
+  {0, 0}, /* BEL */
+  {0x2a, 0},
+  /* BS  */ /* Keyboard Delete (Backspace) */
+  {0x2b, 0},
+  /* TAB */ /* Keyboard Tab */
+  {0x28, 0},
+  /* LF  */          /* Keyboard Return (Enter) */
+  {0, 0},            /* VT  */
+  {0, 0},            /* FF  */
+  {0, 0},            /* CR  */
+  {0, 0},            /* SO  */
+  {0, 0},            /* SI  */
+  {0, 0},            /* DEL */
+  {0, 0},            /* DC1 */
+  {0, 0},            /* DC2 */
+  {0, 0},            /* DC3 */
+  {0, 0},            /* DC4 */
+  {0, 0},            /* NAK */
+  {0, 0},            /* SYN */
+  {0, 0},            /* ETB */
+  {0, 0},            /* CAN */
+  {0, 0},            /* EM  */
+  {0, 0},            /* SUB */
+  {0, 0},            /* ESC */
+  {0, 0},            /* FS  */
+  {0, 0},            /* GS  */
+  {0, 0},            /* RS  */
+  {0, 0},            /* US  */
+  {0x2c, 0},         /*   */
+  {0x1e, KEY_SHIFT}, /* ! */
+  {0x34, KEY_SHIFT}, /* " */
+  {0x20, KEY_SHIFT}, /* # */
+  {0x21, KEY_SHIFT}, /* $ */
+  {0x22, KEY_SHIFT}, /* % */
+  {0x24, KEY_SHIFT}, /* & */
+  {0x34, 0},         /* ' */
+  {0x26, KEY_SHIFT}, /* ( */
+  {0x27, KEY_SHIFT}, /* ) */
+  {0x25, KEY_SHIFT}, /* * */
+  {0x2e, KEY_SHIFT}, /* + */
+  {0x36, 0},         /* , */
+  {0x2d, 0},         /* - */
+  {0x37, 0},         /* . */
+  {0x38, 0},         /* / */
+  {0x27, 0},         /* 0 */
+  {0x1e, 0},         /* 1 */
+  {0x1f, 0},         /* 2 */
+  {0x20, 0},         /* 3 */
+  {0x21, 0},         /* 4 */
+  {0x22, 0},         /* 5 */
+  {0x23, 0},         /* 6 */
+  {0x24, 0},         /* 7 */
+  {0x25, 0},         /* 8 */
+  {0x26, 0},         /* 9 */
+  {0x33, KEY_SHIFT}, /* : */
+  {0x33, 0},         /* ; */
+  {0x36, KEY_SHIFT}, /* < */
+  {0x2e, 0},         /* = */
+  {0x37, KEY_SHIFT}, /* > */
+  {0x38, KEY_SHIFT}, /* ? */
+  {0x1f, KEY_SHIFT}, /* @ */
+  {0x04, KEY_SHIFT}, /* A */
+  {0x05, KEY_SHIFT}, /* B */
+  {0x06, KEY_SHIFT}, /* C */
+  {0x07, KEY_SHIFT}, /* D */
+  {0x08, KEY_SHIFT}, /* E */
+  {0x09, KEY_SHIFT}, /* F */
+  {0x0a, KEY_SHIFT}, /* G */
+  {0x0b, KEY_SHIFT}, /* H */
+  {0x0c, KEY_SHIFT}, /* I */
+  {0x0d, KEY_SHIFT}, /* J */
+  {0x0e, KEY_SHIFT}, /* K */
+  {0x0f, KEY_SHIFT}, /* L */
+  {0x10, KEY_SHIFT}, /* M */
+  {0x11, KEY_SHIFT}, /* N */
+  {0x12, KEY_SHIFT}, /* O */
+  {0x13, KEY_SHIFT}, /* P */
+  {0x14, KEY_SHIFT}, /* Q */
+  {0x15, KEY_SHIFT}, /* R */
+  {0x16, KEY_SHIFT}, /* S */
+  {0x17, KEY_SHIFT}, /* T */
+  {0x18, KEY_SHIFT}, /* U */
+  {0x19, KEY_SHIFT}, /* V */
+  {0x1a, KEY_SHIFT}, /* W */
+  {0x1b, KEY_SHIFT}, /* X */
+  {0x1c, KEY_SHIFT}, /* Y */
+  {0x1d, KEY_SHIFT}, /* Z */
+  {0x2f, 0},         /* [ */
+  {0x31, 0},         /* \ */
+  {0x30, 0},         /* ] */
+  {0x23, KEY_SHIFT}, /* ^ */
+  {0x2d, KEY_SHIFT}, /* _ */
+  {0x35, 0},         /* ` */
+  {0x04, 0},         /* a */
+  {0x05, 0},         /* b */
+  {0x06, 0},         /* c */
+  {0x07, 0},         /* d */
+  {0x08, 0},         /* e */
+  {0x09, 0},         /* f */
+  {0x0a, 0},         /* g */
+  {0x0b, 0},         /* h */
+  {0x0c, 0},         /* i */
+  {0x0d, 0},         /* j */
+  {0x0e, 0},         /* k */
+  {0x0f, 0},         /* l */
+  {0x10, 0},         /* m */
+  {0x11, 0},         /* n */
+  {0x12, 0},         /* o */
+  {0x13, 0},         /* p */
+  {0x14, 0},         /* q */
+  {0x15, 0},         /* r */
+  {0x16, 0},         /* s */
+  {0x17, 0},         /* t */
+  {0x18, 0},         /* u */
+  {0x19, 0},         /* v */
+  {0x1a, 0},         /* w */
+  {0x1b, 0},         /* x */
+  {0x1c, 0},         /* y */
+  {0x1d, 0},         /* z */
+  {0x2f, KEY_SHIFT}, /* { */
+  {0x31, KEY_SHIFT}, /* | */
+  {0x30, KEY_SHIFT}, /* } */
+  {0x35, KEY_SHIFT}, /* ~ */
+  {0, 0},            /* DEL */
 
-    {0x3a, 0},          /* F1 */
-    {0x3b, 0},          /* F2 */
-    {0x3c, 0},          /* F3 */
-    {0x3d, 0},          /* F4 */
-    {0x3e, 0},          /* F5 */
-    {0x3f, 0},          /* F6 */
-    {0x40, 0},          /* F7 */
-    {0x41, 0},          /* F8 */
-    {0x42, 0},          /* F9 */
-    {0x43, 0},          /* F10 */
-    {0x44, 0},          /* F11 */
-    {0x45, 0},          /* F12 */
+  {0x3a, 0}, /* F1 */
+  {0x3b, 0}, /* F2 */
+  {0x3c, 0}, /* F3 */
+  {0x3d, 0}, /* F4 */
+  {0x3e, 0}, /* F5 */
+  {0x3f, 0}, /* F6 */
+  {0x40, 0}, /* F7 */
+  {0x41, 0}, /* F8 */
+  {0x42, 0}, /* F9 */
+  {0x43, 0}, /* F10 */
+  {0x44, 0}, /* F11 */
+  {0x45, 0}, /* F12 */
 
-    {0x46, 0},          /* PRINT_SCREEN */
-    {0x47, 0},          /* SCROLL_LOCK */
-    {0x39, 0},          /* CAPS_LOCK */
-    {0x53, 0},          /* NUM_LOCK */
-    {0x49, 0},          /* INSERT */
-    {0x4a, 0},          /* HOME */
-    {0x4b, 0},          /* PAGE_UP */
-    {0x4e, 0},          /* PAGE_DOWN */
+  {0x46, 0}, /* PRINT_SCREEN */
+  {0x47, 0}, /* SCROLL_LOCK */
+  {0x39, 0}, /* CAPS_LOCK */
+  {0x53, 0}, /* NUM_LOCK */
+  {0x49, 0}, /* INSERT */
+  {0x4a, 0}, /* HOME */
+  {0x4b, 0}, /* PAGE_UP */
+  {0x4e, 0}, /* PAGE_DOWN */
 
-    {0x4f, 0},          /* RIGHT_ARROW */
-    {0x50, 0},          /* LEFT_ARROW */
-    {0x51, 0},          /* DOWN_ARROW */
-    {0x52, 0},          /* UP_ARROW */
+  {0x4f, 0}, /* RIGHT_ARROW */
+  {0x50, 0}, /* LEFT_ARROW */
+  {0x51, 0}, /* DOWN_ARROW */
+  {0x52, 0}, /* UP_ARROW */
 };
 
 #else
 /* UK keyboard */
 #define KEYMAP_SIZE (152)
 const KEYMAP keymap[KEYMAP_SIZE] = {
-    {0, 0},             /* NUL */
-    {0, 0},             /* SOH */
-    {0, 0},             /* STX */
-    {0, 0},             /* ETX */
-    {0, 0},             /* EOT */
-    {0, 0},             /* ENQ */
-    {0, 0},             /* ACK */
-    {0, 0},             /* BEL */
-    {0x2a, 0},          /* BS  */  /* Keyboard Delete (Backspace) */
-    {0x2b, 0},          /* TAB */  /* Keyboard Tab */
-    {0x28, 0},          /* LF  */  /* Keyboard Return (Enter) */
-    {0, 0},             /* VT  */
-    {0, 0},             /* FF  */
-    {0, 0},             /* CR  */
-    {0, 0},             /* SO  */
-    {0, 0},             /* SI  */
-    {0, 0},             /* DEL */
-    {0, 0},             /* DC1 */
-    {0, 0},             /* DC2 */
-    {0, 0},             /* DC3 */
-    {0, 0},             /* DC4 */
-    {0, 0},             /* NAK */
-    {0, 0},             /* SYN */
-    {0, 0},             /* ETB */
-    {0, 0},             /* CAN */
-    {0, 0},             /* EM  */
-    {0, 0},             /* SUB */
-    {0, 0},             /* ESC */
-    {0, 0},             /* FS  */
-    {0, 0},             /* GS  */
-    {0, 0},             /* RS  */
-    {0, 0},             /* US  */
-    {0x2c, 0},          /*   */
-    {0x1e, KEY_SHIFT},      /* ! */
-    {0x1f, KEY_SHIFT},      /* " */
-    {0x32, 0},          /* # */
-    {0x21, KEY_SHIFT},      /* $ */
-    {0x22, KEY_SHIFT},      /* % */
-    {0x24, KEY_SHIFT},      /* & */
-    {0x34, 0},          /* ' */
-    {0x26, KEY_SHIFT},      /* ( */
-    {0x27, KEY_SHIFT},      /* ) */
-    {0x25, KEY_SHIFT},      /* * */
-    {0x2e, KEY_SHIFT},      /* + */
-    {0x36, 0},          /* , */
-    {0x2d, 0},          /* - */
-    {0x37, 0},          /* . */
-    {0x38, 0},          /* / */
-    {0x27, 0},          /* 0 */
-    {0x1e, 0},          /* 1 */
-    {0x1f, 0},          /* 2 */
-    {0x20, 0},          /* 3 */
-    {0x21, 0},          /* 4 */
-    {0x22, 0},          /* 5 */
-    {0x23, 0},          /* 6 */
-    {0x24, 0},          /* 7 */
-    {0x25, 0},          /* 8 */
-    {0x26, 0},          /* 9 */
-    {0x33, KEY_SHIFT},      /* : */
-    {0x33, 0},          /* ; */
-    {0x36, KEY_SHIFT},      /* < */
-    {0x2e, 0},          /* = */
-    {0x37, KEY_SHIFT},      /* > */
-    {0x38, KEY_SHIFT},      /* ? */
-    {0x34, KEY_SHIFT},      /* @ */
-    {0x04, KEY_SHIFT},      /* A */
-    {0x05, KEY_SHIFT},      /* B */
-    {0x06, KEY_SHIFT},      /* C */
-    {0x07, KEY_SHIFT},      /* D */
-    {0x08, KEY_SHIFT},      /* E */
-    {0x09, KEY_SHIFT},      /* F */
-    {0x0a, KEY_SHIFT},      /* G */
-    {0x0b, KEY_SHIFT},      /* H */
-    {0x0c, KEY_SHIFT},      /* I */
-    {0x0d, KEY_SHIFT},      /* J */
-    {0x0e, KEY_SHIFT},      /* K */
-    {0x0f, KEY_SHIFT},      /* L */
-    {0x10, KEY_SHIFT},      /* M */
-    {0x11, KEY_SHIFT},      /* N */
-    {0x12, KEY_SHIFT},      /* O */
-    {0x13, KEY_SHIFT},      /* P */
-    {0x14, KEY_SHIFT},      /* Q */
-    {0x15, KEY_SHIFT},      /* R */
-    {0x16, KEY_SHIFT},      /* S */
-    {0x17, KEY_SHIFT},      /* T */
-    {0x18, KEY_SHIFT},      /* U */
-    {0x19, KEY_SHIFT},      /* V */
-    {0x1a, KEY_SHIFT},      /* W */
-    {0x1b, KEY_SHIFT},      /* X */
-    {0x1c, KEY_SHIFT},      /* Y */
-    {0x1d, KEY_SHIFT},      /* Z */
-    {0x2f, 0},          /* [ */
-    {0x64, 0},          /* \ */
-    {0x30, 0},          /* ] */
-    {0x23, KEY_SHIFT},      /* ^ */
-    {0x2d, KEY_SHIFT},      /* _ */
-    {0x35, 0},          /* ` */
-    {0x04, 0},          /* a */
-    {0x05, 0},          /* b */
-    {0x06, 0},          /* c */
-    {0x07, 0},          /* d */
-    {0x08, 0},          /* e */
-    {0x09, 0},          /* f */
-    {0x0a, 0},          /* g */
-    {0x0b, 0},          /* h */
-    {0x0c, 0},          /* i */
-    {0x0d, 0},          /* j */
-    {0x0e, 0},          /* k */
-    {0x0f, 0},          /* l */
-    {0x10, 0},          /* m */
-    {0x11, 0},          /* n */
-    {0x12, 0},          /* o */
-    {0x13, 0},          /* p */
-    {0x14, 0},          /* q */
-    {0x15, 0},          /* r */
-    {0x16, 0},          /* s */
-    {0x17, 0},          /* t */
-    {0x18, 0},          /* u */
-    {0x19, 0},          /* v */
-    {0x1a, 0},          /* w */
-    {0x1b, 0},          /* x */
-    {0x1c, 0},          /* y */
-    {0x1d, 0},          /* z */
-    {0x2f, KEY_SHIFT},      /* { */
-    {0x64, KEY_SHIFT},      /* | */
-    {0x30, KEY_SHIFT},      /* } */
-    {0x32, KEY_SHIFT},      /* ~ */
-    {0,0},             /* DEL */
+  {0, 0}, /* NUL */
+  {0, 0}, /* SOH */
+  {0, 0}, /* STX */
+  {0, 0}, /* ETX */
+  {0, 0}, /* EOT */
+  {0, 0}, /* ENQ */
+  {0, 0}, /* ACK */
+  {0, 0}, /* BEL */
+  {0x2a, 0},
+  /* BS  */ /* Keyboard Delete (Backspace) */
+  {0x2b, 0},
+  /* TAB */ /* Keyboard Tab */
+  {0x28, 0},
+  /* LF  */          /* Keyboard Return (Enter) */
+  {0, 0},            /* VT  */
+  {0, 0},            /* FF  */
+  {0, 0},            /* CR  */
+  {0, 0},            /* SO  */
+  {0, 0},            /* SI  */
+  {0, 0},            /* DEL */
+  {0, 0},            /* DC1 */
+  {0, 0},            /* DC2 */
+  {0, 0},            /* DC3 */
+  {0, 0},            /* DC4 */
+  {0, 0},            /* NAK */
+  {0, 0},            /* SYN */
+  {0, 0},            /* ETB */
+  {0, 0},            /* CAN */
+  {0, 0},            /* EM  */
+  {0, 0},            /* SUB */
+  {0, 0},            /* ESC */
+  {0, 0},            /* FS  */
+  {0, 0},            /* GS  */
+  {0, 0},            /* RS  */
+  {0, 0},            /* US  */
+  {0x2c, 0},         /*   */
+  {0x1e, KEY_SHIFT}, /* ! */
+  {0x1f, KEY_SHIFT}, /* " */
+  {0x32, 0},         /* # */
+  {0x21, KEY_SHIFT}, /* $ */
+  {0x22, KEY_SHIFT}, /* % */
+  {0x24, KEY_SHIFT}, /* & */
+  {0x34, 0},         /* ' */
+  {0x26, KEY_SHIFT}, /* ( */
+  {0x27, KEY_SHIFT}, /* ) */
+  {0x25, KEY_SHIFT}, /* * */
+  {0x2e, KEY_SHIFT}, /* + */
+  {0x36, 0},         /* , */
+  {0x2d, 0},         /* - */
+  {0x37, 0},         /* . */
+  {0x38, 0},         /* / */
+  {0x27, 0},         /* 0 */
+  {0x1e, 0},         /* 1 */
+  {0x1f, 0},         /* 2 */
+  {0x20, 0},         /* 3 */
+  {0x21, 0},         /* 4 */
+  {0x22, 0},         /* 5 */
+  {0x23, 0},         /* 6 */
+  {0x24, 0},         /* 7 */
+  {0x25, 0},         /* 8 */
+  {0x26, 0},         /* 9 */
+  {0x33, KEY_SHIFT}, /* : */
+  {0x33, 0},         /* ; */
+  {0x36, KEY_SHIFT}, /* < */
+  {0x2e, 0},         /* = */
+  {0x37, KEY_SHIFT}, /* > */
+  {0x38, KEY_SHIFT}, /* ? */
+  {0x34, KEY_SHIFT}, /* @ */
+  {0x04, KEY_SHIFT}, /* A */
+  {0x05, KEY_SHIFT}, /* B */
+  {0x06, KEY_SHIFT}, /* C */
+  {0x07, KEY_SHIFT}, /* D */
+  {0x08, KEY_SHIFT}, /* E */
+  {0x09, KEY_SHIFT}, /* F */
+  {0x0a, KEY_SHIFT}, /* G */
+  {0x0b, KEY_SHIFT}, /* H */
+  {0x0c, KEY_SHIFT}, /* I */
+  {0x0d, KEY_SHIFT}, /* J */
+  {0x0e, KEY_SHIFT}, /* K */
+  {0x0f, KEY_SHIFT}, /* L */
+  {0x10, KEY_SHIFT}, /* M */
+  {0x11, KEY_SHIFT}, /* N */
+  {0x12, KEY_SHIFT}, /* O */
+  {0x13, KEY_SHIFT}, /* P */
+  {0x14, KEY_SHIFT}, /* Q */
+  {0x15, KEY_SHIFT}, /* R */
+  {0x16, KEY_SHIFT}, /* S */
+  {0x17, KEY_SHIFT}, /* T */
+  {0x18, KEY_SHIFT}, /* U */
+  {0x19, KEY_SHIFT}, /* V */
+  {0x1a, KEY_SHIFT}, /* W */
+  {0x1b, KEY_SHIFT}, /* X */
+  {0x1c, KEY_SHIFT}, /* Y */
+  {0x1d, KEY_SHIFT}, /* Z */
+  {0x2f, 0},         /* [ */
+  {0x64, 0},         /* \ */
+  {0x30, 0},         /* ] */
+  {0x23, KEY_SHIFT}, /* ^ */
+  {0x2d, KEY_SHIFT}, /* _ */
+  {0x35, 0},         /* ` */
+  {0x04, 0},         /* a */
+  {0x05, 0},         /* b */
+  {0x06, 0},         /* c */
+  {0x07, 0},         /* d */
+  {0x08, 0},         /* e */
+  {0x09, 0},         /* f */
+  {0x0a, 0},         /* g */
+  {0x0b, 0},         /* h */
+  {0x0c, 0},         /* i */
+  {0x0d, 0},         /* j */
+  {0x0e, 0},         /* k */
+  {0x0f, 0},         /* l */
+  {0x10, 0},         /* m */
+  {0x11, 0},         /* n */
+  {0x12, 0},         /* o */
+  {0x13, 0},         /* p */
+  {0x14, 0},         /* q */
+  {0x15, 0},         /* r */
+  {0x16, 0},         /* s */
+  {0x17, 0},         /* t */
+  {0x18, 0},         /* u */
+  {0x19, 0},         /* v */
+  {0x1a, 0},         /* w */
+  {0x1b, 0},         /* x */
+  {0x1c, 0},         /* y */
+  {0x1d, 0},         /* z */
+  {0x2f, KEY_SHIFT}, /* { */
+  {0x64, KEY_SHIFT}, /* | */
+  {0x30, KEY_SHIFT}, /* } */
+  {0x32, KEY_SHIFT}, /* ~ */
+  {0, 0},            /* DEL */
 
-    {0x3a, 0},          /* F1 */
-    {0x3b, 0},          /* F2 */
-    {0x3c, 0},          /* F3 */
-    {0x3d, 0},          /* F4 */
-    {0x3e, 0},          /* F5 */
-    {0x3f, 0},          /* F6 */
-    {0x40, 0},          /* F7 */
-    {0x41, 0},          /* F8 */
-    {0x42, 0},          /* F9 */
-    {0x43, 0},          /* F10 */
-    {0x44, 0},          /* F11 */
-    {0x45, 0},          /* F12 */
+  {0x3a, 0}, /* F1 */
+  {0x3b, 0}, /* F2 */
+  {0x3c, 0}, /* F3 */
+  {0x3d, 0}, /* F4 */
+  {0x3e, 0}, /* F5 */
+  {0x3f, 0}, /* F6 */
+  {0x40, 0}, /* F7 */
+  {0x41, 0}, /* F8 */
+  {0x42, 0}, /* F9 */
+  {0x43, 0}, /* F10 */
+  {0x44, 0}, /* F11 */
+  {0x45, 0}, /* F12 */
 
-    {0x46, 0},          /* PRINT_SCREEN */
-    {0x47, 0},          /* SCROLL_LOCK */
-    {0x39, 0},          /* CAPS_LOCK */
-    {0x53, 0},          /* NUM_LOCK */
-    {0x49, 0},          /* INSERT */
-    {0x4a, 0},          /* HOME */
-    {0x4b, 0},          /* PAGE_UP */
-    {0x4e, 0},          /* PAGE_DOWN */
+  {0x46, 0}, /* PRINT_SCREEN */
+  {0x47, 0}, /* SCROLL_LOCK */
+  {0x39, 0}, /* CAPS_LOCK */
+  {0x53, 0}, /* NUM_LOCK */
+  {0x49, 0}, /* INSERT */
+  {0x4a, 0}, /* HOME */
+  {0x4b, 0}, /* PAGE_UP */
+  {0x4e, 0}, /* PAGE_DOWN */
 
-    {0x4f, 0},          /* RIGHT_ARROW */
-    {0x50, 0},          /* LEFT_ARROW */
-    {0x51, 0},          /* DOWN_ARROW */
-    {0x52, 0},          /* UP_ARROW */
+  {0x4f, 0}, /* RIGHT_ARROW */
+  {0x50, 0}, /* LEFT_ARROW */
+  {0x51, 0}, /* DOWN_ARROW */
+  {0x52, 0}, /* UP_ARROW */
 };
 #endif
 
diff --git a/libraries/BLE/src/HIDTypes.h b/libraries/BLE/src/HIDTypes.h
index 64850ef8a75..2dbdadc0654 100644
--- a/libraries/BLE/src/HIDTypes.h
+++ b/libraries/BLE/src/HIDTypes.h
@@ -22,17 +22,17 @@
 #include <stdint.h>
 
 /* */
-#define HID_VERSION_1_11    (0x0111)
+#define HID_VERSION_1_11 (0x0111)
 
 /* HID Class */
-#define HID_CLASS           (3)
-#define HID_SUBCLASS_NONE   (0)
-#define HID_PROTOCOL_NONE   (0)
+#define BLE_HID_CLASS         (3)
+#define BLE_HID_SUBCLASS_NONE (0)
+#define BLE_HID_PROTOCOL_NONE (0)
 
 /* Descriptors */
-#define HID_DESCRIPTOR          (33)
-#define HID_DESCRIPTOR_LENGTH   (0x09)
-#define REPORT_DESCRIPTOR       (34)
+#define HID_DESCRIPTOR        (33)
+#define HID_DESCRIPTOR_LENGTH (0x09)
+#define REPORT_DESCRIPTOR     (34)
 
 /* Class requests */
 #define GET_REPORT (0x1)
@@ -46,41 +46,41 @@
 
 /* Main items */
 #ifdef ARDUINO_ARCH_ESP32
-#define HIDINPUT(size)             (0x80 | size)
-#define HIDOUTPUT(size)            (0x90 | size)
+#define HIDINPUT(size)  (0x80 | size)
+#define HIDOUTPUT(size) (0x90 | size)
 #else
-#define INPUT(size)             (0x80 | size)
-#define OUTPUT(size)            (0x90 | size)
+#define INPUT(size)  (0x80 | size)
+#define OUTPUT(size) (0x90 | size)
 #endif
-#define FEATURE(size)           (0xb0 | size)
-#define COLLECTION(size)        (0xa0 | size)
-#define END_COLLECTION(size)    (0xc0 | size)
+#define FEATURE(size)        (0xb0 | size)
+#define COLLECTION(size)     (0xa0 | size)
+#define END_COLLECTION(size) (0xc0 | size)
 
 /* Global items */
-#define USAGE_PAGE(size)        (0x04 | size)
-#define LOGICAL_MINIMUM(size)   (0x14 | size)
-#define LOGICAL_MAXIMUM(size)   (0x24 | size)
-#define PHYSICAL_MINIMUM(size)  (0x34 | size)
-#define PHYSICAL_MAXIMUM(size)  (0x44 | size)
-#define UNIT_EXPONENT(size)     (0x54 | size)
-#define UNIT(size)              (0x64 | size)
-#define REPORT_SIZE(size)       (0x74 | size)  //bits
-#define REPORT_ID(size)         (0x84 | size)
-#define REPORT_COUNT(size)      (0x94 | size)  //bytes
-#define PUSH(size)              (0xa4 | size)
-#define POP(size)               (0xb4 | size)
+#define USAGE_PAGE(size)       (0x04 | size)
+#define LOGICAL_MINIMUM(size)  (0x14 | size)
+#define LOGICAL_MAXIMUM(size)  (0x24 | size)
+#define PHYSICAL_MINIMUM(size) (0x34 | size)
+#define PHYSICAL_MAXIMUM(size) (0x44 | size)
+#define UNIT_EXPONENT(size)    (0x54 | size)
+#define UNIT(size)             (0x64 | size)
+#define REPORT_SIZE(size)      (0x74 | size)  //bits
+#define REPORT_ID(size)        (0x84 | size)
+#define REPORT_COUNT(size)     (0x94 | size)  //bytes
+#define PUSH(size)             (0xa4 | size)
+#define POP(size)              (0xb4 | size)
 
 /* Local items */
-#define USAGE(size)                 (0x08 | size)
-#define USAGE_MINIMUM(size)         (0x18 | size)
-#define USAGE_MAXIMUM(size)         (0x28 | size)
-#define DESIGNATOR_INDEX(size)      (0x38 | size)
-#define DESIGNATOR_MINIMUM(size)    (0x48 | size)
-#define DESIGNATOR_MAXIMUM(size)    (0x58 | size)
-#define STRING_INDEX(size)          (0x78 | size)
-#define STRING_MINIMUM(size)        (0x88 | size)
-#define STRING_MAXIMUM(size)        (0x98 | size)
-#define DELIMITER(size)             (0xa8 | size)
+#define USAGE(size)              (0x08 | size)
+#define USAGE_MINIMUM(size)      (0x18 | size)
+#define USAGE_MAXIMUM(size)      (0x28 | size)
+#define DESIGNATOR_INDEX(size)   (0x38 | size)
+#define DESIGNATOR_MINIMUM(size) (0x48 | size)
+#define DESIGNATOR_MAXIMUM(size) (0x58 | size)
+#define STRING_INDEX(size)       (0x78 | size)
+#define STRING_MINIMUM(size)     (0x88 | size)
+#define STRING_MAXIMUM(size)     (0x98 | size)
+#define DELIMITER(size)          (0xa8 | size)
 
 /* HID Report */
 /* Where report IDs are used the first byte of 'data' will be the */
@@ -89,8 +89,8 @@
 #define MAX_HID_REPORT_SIZE (64)
 
 typedef struct {
-	uint32_t length;
-	uint8_t data[MAX_HID_REPORT_SIZE];
+  uint32_t length;
+  uint8_t data[MAX_HID_REPORT_SIZE];
 } HID_REPORT;
 
 #endif
diff --git a/libraries/BLE/src/RTOS.h b/libraries/BLE/src/RTOS.h
new file mode 100644
index 00000000000..0f798c5e97c
--- /dev/null
+++ b/libraries/BLE/src/RTOS.h
@@ -0,0 +1,81 @@
+/*
+ * FreeRTOS.h
+ *
+ *  Created on: Feb 24, 2017
+ *      Author: kolban
+ */
+
+#ifdef __cplusplus
+#ifndef MAIN_FREERTOS_H_
+#define MAIN_FREERTOS_H_
+#include "Arduino.h"
+#include <stdint.h>
+#include <pthread.h>
+
+#include <freertos/FreeRTOS.h>  // Include the base FreeRTOS definitions.
+#include <freertos/task.h>      // Include the task definitions.
+#include <freertos/semphr.h>    // Include the semaphore definitions.
+#include <freertos/ringbuf.h>   // Include the ringbuffer definitions.
+
+/**
+ * @brief Interface to %FreeRTOS functions.
+ */
+class FreeRTOS {
+public:
+  static void sleep(uint32_t ms);
+  static void startTask(void task(void *), String taskName, void *param = nullptr, uint32_t stackSize = 2048);
+  static void deleteTask(TaskHandle_t pTask = nullptr);
+
+  static uint32_t getTimeSinceStart();
+
+  class Semaphore {
+  public:
+    Semaphore(String owner = "<Unknown>");
+    ~Semaphore();
+    void give();
+    void give(uint32_t value);
+    void giveFromISR();
+    void setName(String name);
+    bool take(String owner = "<Unknown>");
+    bool take(uint32_t timeoutMs, String owner = "<Unknown>");
+    String toString();
+    uint32_t wait(String owner = "<Unknown>");
+    bool timedWait(String owner = "<Unknown>", uint32_t timeoutMs = portMAX_DELAY);
+    uint32_t value() {
+      return m_value;
+    };
+
+  private:
+    SemaphoreHandle_t m_semaphore;
+    pthread_mutex_t m_pthread_mutex;
+    String m_name;
+    String m_owner;
+    uint32_t m_value;
+    bool m_usePthreads;
+  };
+};
+
+/**
+ * @brief Ringbuffer.
+ */
+class Ringbuffer {
+public:
+#ifdef ESP_IDF_VERSION_MAJOR
+  Ringbuffer(size_t length, RingbufferType_t type = RINGBUF_TYPE_NOSPLIT);
+#else
+  Ringbuffer(size_t length, ringbuf_type_t type = RINGBUF_TYPE_NOSPLIT);
+#endif
+  ~Ringbuffer();
+
+  void *receive(size_t *size, TickType_t wait = portMAX_DELAY);
+  void returnItem(void *item);
+  bool send(void *data, size_t length, TickType_t wait = portMAX_DELAY);
+
+private:
+  RingbufHandle_t m_handle;
+};
+
+#endif /* MAIN_FREERTOS_H_ */
+#else
+#include "freertos/FreeRTOS.h"
+#endif
diff --git a/libraries/BluetoothSerial/README.md b/libraries/BluetoothSerial/README.md
index 9d25dbca0a9..218c147992e 100644
--- a/libraries/BluetoothSerial/README.md
+++ b/libraries/BluetoothSerial/README.md
@@ -1,19 +1,78 @@
-### Bluetooth Serial Library
+## Bluetooth Serial Library
 
-A simple Serial compatible library using ESP32 classical bluetooth (SPP)
+A simple Serial compatible library using ESP32 classical Bluetooth Serial Port Profile (SPP)
 
+Note: Since version 3.0.0 this library does not support legacy pairing (using fixed PIN consisting of 4 digits).
 
+### How to use it?
 
-#### How to use it?
+There are 3 basic use cases: phone, other ESP32 or any MCU with a Bluetooth serial module
 
-- Download one bluetooth terminal app in your smartphone<br>
-For Android: https://play.google.com/store/apps/details?id=de.kai_morich.serial_bluetooth_terminal <br>
-For iOS: https://itunes.apple.com/us/app/hm10-bluetooth-serial-lite/id1030454675
+#### Phone
+
+- Download one of the Bluetooth terminal apps to your smartphone
+
+    - For [Android](https://play.google.com/store/apps/details?id=de.kai_morich.serial_bluetooth_terminal)
+    - For [iOS](https://itunes.apple.com/us/app/hm10-bluetooth-serial-lite/id1030454675)
 
 - Flash an example sketch to your ESP32
 
-- Scan and pair the device in your smartphone
+- Scan and pair the device to your smartphone
 
-- Open the bluetooth terminal app
+- Open the Bluetooth terminal app and connect
 
 - Enjoy
+
+#### ESP32
+
+You can flash one of the ESP32 with the example [`SerialToSerialBTM`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino) (the Master) and another ESP32 with [`SerialToSerialBT`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino) (the Slave).
+Those examples are preset to work out-of-the-box but they should be scalable to connect multiple Slaves to the Master.
+
+#### 3rd party Serial Bluetooth module
+
+Using a 3rd party Serial Bluetooth module will require to study the documentation of the particular module in order to make it work, however, one side can utilize the mentioned [`SerialToSerialBTM`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino) (the Master) or [`SerialToSerialBT`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino) (the Slave).
+
+### Pairing options
+
+There are two easy options and one difficult.
+
+The easy options can be used as usual. These offer pairing with and without Secure Simple Pairing (SSP).
+
+The difficult option offers legacy pairing (using fixed PIN) however this must be compiled with Arduino as an IDF component with disabled sdkconfig option `CONFIG_BT_SSP_ENABLED`.
+
+#### Without SSP
+
+This method will authenticate automatically any attempt to pair and should not be used if security is a concern! This option is used for the examples [`SerialToSerialBTM`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino) and [`SerialToSerialBT`](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino).
+
+### With SSP
+
+The usage of SSP provides a secure connection. This option is demonstrated in the example `SerialToSerialBT_SSP``](https://github.com/espressif/arduino-esp32/blob/master/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/SerialToSerialBT_SSP.ino)
+
+The Secure Simple Pairing is enabled by calling method `enableSSP` which has two variants - one is backward compatible without parameter `enableSSP()` and second with parameters `enableSSP(bool inputCapability, bool outputCapability)`. Similarly, the SSP can be disabled by calling `disableSSP()`.
+
+Both options must be called before `begin()` or if it is called after `begin()` the driver needs to be restarted (call `end()` followed by `begin()`) in order to take in effect enabling or disabling the SSP.
+
+#### The parameters define the method of authentication:
+
+**inputCapability** - Defines if ESP32 device has input method (Serial terminal, keyboard or similar)
+
+**outputCapability** - Defines if ESP32 device has output method (Serial terminal, display or similar)
+
+* **inputCapability=true and outputCapability=true**
+    * Both devices display randomly generated code and if they match the user will authenticate pairing on both devices.
+    * This must be implemented by registering a callback via `onConfirmRequest()` and in this callback the user will input the response and call `confirmReply(true)` if the authenticated, otherwise call `confirmReply(false)` to reject the pairing.
+* **inputCapability=false and outputCapability=false**
+    * Only the other device authenticates pairing without any pin.
+* **inputCapability=false and outputCapability=true**
+    * Only the other device authenticates pairing without any pin.
+* **inputCapability=true and outputCapability=false**
+    * The user will be required to input the passkey to the ESP32 device to authenticate.
+    * This must be implemented by registering a callback via `onKeyRequest`()` and in this callback the entered passkey will be responded via `respondPasskey(passkey)`
+
+### Legacy Pairing (IDF component)
+
+To use Legacy pairing you will have to use [Arduino as an IDF component](https://espressif-docs.readthedocs-hosted.com/projects/arduino-esp32/en/latest/esp-idf_component.html) and disable option `CONFIG_BT_SSP_ENABLED`.
+Please refer to the documentation on how to setup Arduino as an IDF component and when you are done, run `idf.py menuconfig` navigate to `Component Config -> Bluetooth -> Bluedroid -> [ ] Secure Simple Pairing` and disable it.
+While in the menuconfig you will also need to change the partition scheme `Partition Table -> Partition Table -> (X) Single Factory app (large), no OTA`.
+After these changes save & quit menuconfig and you are ready to go: `idf.py  monitor flash`.
+Please note that to use the PIN in smartphones and computers you need to use characters `SerialBT.setPin("1234", 4);` not a number `SerialBT.setPin(1234, 4);` . Numbers CAN be used if the other side uses them too, but phones and computers use characters.
diff --git a/libraries/BluetoothSerial/examples/DiscoverConnect/DiscoverConnect.ino b/libraries/BluetoothSerial/examples/DiscoverConnect/DiscoverConnect.ino
new file mode 100644
index 00000000000..bd50c6b1d90
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/DiscoverConnect/DiscoverConnect.ino
@@ -0,0 +1,110 @@
+/**
+ * Bluetooth Classic Example
+ * Scan for devices - asynchronously, print device as soon as found
+ * query devices for SPP - SDP profile
+ * connect to first device offering a SPP connection
+ *
+ * Example python server:
+ * source: https://gist.github.com/ukBaz/217875c83c2535d22a16ba38fc8f2a91
+ *
+ * Tested with Raspberry Pi onboard Wifi/BT, USB BT 4.0 dongles, USB BT 1.1 dongles,
+ * 202202: does NOT work with USB BT 2.0 dongles when esp32 arduino lib is compiled with SSP support!
+ *         see https://github.com/espressif/esp-idf/issues/8394
+ *
+ * use ESP_SPP_SEC_ENCRYPT|ESP_SPP_SEC_AUTHENTICATE in connect() if remote side requests 'RequireAuthentication': dbus.Boolean(True),
+ * use ESP_SPP_SEC_NONE or ESP_SPP_SEC_ENCRYPT|ESP_SPP_SEC_AUTHENTICATE in connect() if remote side has Authentication: False
+ */
+
+#include <map>
+#include <BluetoothSerial.h>
+
+#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED)
+#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it
+#endif
+
+#if !defined(CONFIG_BT_SPP_ENABLED)
+#error Serial Bluetooth not available or not enabled. It is only available for the ESP32 chip.
+#endif
+
+BluetoothSerial SerialBT;
+
+#define BT_DISCOVER_TIME 10000
+esp_spp_sec_t sec_mask = ESP_SPP_SEC_NONE;  // or ESP_SPP_SEC_ENCRYPT|ESP_SPP_SEC_AUTHENTICATE to request pincode confirmation
+esp_spp_role_t role = ESP_SPP_ROLE_SLAVE;   // or ESP_SPP_ROLE_MASTER
+
+// std::map<BTAddress, BTAdvertisedDeviceSet> btDeviceList;
+
+void setup() {
+  Serial.begin(115200);
+  if (!SerialBT.begin("ESP32test", true)) {
+    Serial.println("========== serialBT failed!");
+    abort();
+  }
+  // SerialBT.setPin("1234"); // doesn't seem to change anything
+  // SerialBT.enableSSP(); // doesn't seem to change anything
+
+  Serial.println("Starting discoverAsync...");
+  BTScanResults *btDeviceList = SerialBT.getScanResults();  // maybe accessing from different threads!
+  if (SerialBT.discoverAsync([](BTAdvertisedDevice *pDevice) {
+        // BTAdvertisedDeviceSet*set = reinterpret_cast<BTAdvertisedDeviceSet*>(pDevice);
+        // btDeviceList[pDevice->getAddress()] = * set;
+        Serial.printf(">>>>>>>>>>>Found a new device asynchronously: %s\n", pDevice->toString().c_str());
+      })) {
+    delay(BT_DISCOVER_TIME);
+    Serial.print("Stopping discoverAsync... ");
+    SerialBT.discoverAsyncStop();
+    Serial.println("discoverAsync stopped");
+    delay(5000);
+    if (btDeviceList->getCount() > 0) {
+      BTAddress addr;
+      int channel = 0;
+      Serial.println("Found devices:");
+      for (int i = 0; i < btDeviceList->getCount(); i++) {
+        BTAdvertisedDevice *device = btDeviceList->getDevice(i);
+        Serial.printf(" ----- %s  %s %d\n", device->getAddress().toString().c_str(), device->getName().c_str(), device->getRSSI());
+        std::map<int, std::string> channels = SerialBT.getChannels(device->getAddress());
+        Serial.printf("scanned for services, found %d\n", channels.size());
+        for (auto const &entry : channels) {
+          Serial.printf("     channel %d (%s)\n", entry.first, entry.second.c_str());
+        }
+        if (channels.size() > 0) {
+          addr = device->getAddress();
+          channel = channels.begin()->first;
+        }
+      }
+      if (addr) {
+        Serial.printf("connecting to %s - %d\n", addr.toString().c_str(), channel);
+        SerialBT.connect(addr, channel, sec_mask, role);
+      }
+    } else {
+      Serial.println("Didn't find any devices");
+    }
+  } else {
+    Serial.println("Error on discoverAsync f.e. not working after a \"connect\"");
+  }
+}
+
+String sendData = "Hi from esp32!\n";
+
+void loop() {
+  if (!SerialBT.isClosed() && SerialBT.connected()) {
+    if (SerialBT.write((const uint8_t *)sendData.c_str(), sendData.length()) != sendData.length()) {
+      Serial.println("tx: error");
+    } else {
+      Serial.printf("tx: %s", sendData.c_str());
+    }
+    if (SerialBT.available()) {
+      Serial.print("rx: ");
+      while (SerialBT.available()) {
+        int c = SerialBT.read();
+        if (c >= 0) {
+          Serial.print((char)c);
+        }
+      }
+      Serial.println();
+    }
+  } else {
+    Serial.println("not connected");
+  }
+  delay(1000);
+}
diff --git a/libraries/BluetoothSerial/examples/DiscoverConnect/ci.json b/libraries/BluetoothSerial/examples/DiscoverConnect/ci.json
new file mode 100644
index 00000000000..b5097688f52
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/DiscoverConnect/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_BT_SPP_ENABLED=y"
+  ]
+}
diff --git a/libraries/BluetoothSerial/examples/GetLocalMAC/GetLocalMAC.ino b/libraries/BluetoothSerial/examples/GetLocalMAC/GetLocalMAC.ino
new file mode 100644
index 00000000000..32e782bef72
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/GetLocalMAC/GetLocalMAC.ino
@@ -0,0 +1,49 @@
+// This example demonstrates usage of BluetoothSerial method to retrieve MAC address of local BT device in various formats.
+// By Tomas Pilny - 2023
+
+#include "BluetoothSerial.h"
+
+String device_name = "ESP32-example";
+
+#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED)
+#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it
+#endif
+
+#if !defined(CONFIG_BT_SPP_ENABLED)
+#error Serial Bluetooth not available or not enabled. It is only available for the ESP32 chip.
+#endif
+
+BluetoothSerial SerialBT;
+
+void setup() {
+  Serial.begin(115200);
+  SerialBT.begin(device_name);  //Bluetooth device name
+
+  uint8_t mac_arr[6];  // Byte array to hold the MAC address from getBtAddress()
+  BTAddress mac_obj;   // Object holding instance of BTAddress with the MAC (for more details see libraries/BluetoothSerial/src/BTAddress.h)
+  String mac_str;      // String holding the text version of MAC in format AA:BB:CC:DD:EE:FF
+
+  SerialBT.getBtAddress(mac_arr);           // Fill in the array
+  mac_obj = SerialBT.getBtAddressObject();  // Instantiate the object
+  mac_str = SerialBT.getBtAddressString();  // Copy the string
+
+  Serial.print("This device is instantiated with name ");
+  Serial.println(device_name);
+
+  Serial.print("The mac address using byte array: ");
+  for (int i = 0; i < ESP_BD_ADDR_LEN - 1; i++) {
+    Serial.print(mac_arr[i], HEX);
+    Serial.print(":");
+  }
+  Serial.println(mac_arr[ESP_BD_ADDR_LEN - 1], HEX);
+
+  Serial.print("The mac address using BTAddress object using default method `toString()`: ");
+  Serial.println(mac_obj.toString().c_str());
+  Serial.print("The mac address using BTAddress object using method `toString(true)`\n\twhich prints the MAC with capital letters: ");
+  Serial.println(mac_obj.toString(true).c_str());  // This actually what is used inside the getBtAddressString()
+
+  Serial.print("The mac address using string: ");
+  Serial.println(mac_str.c_str());
+}
+
+void loop() {}
diff --git a/libraries/BluetoothSerial/examples/GetLocalMAC/ci.json b/libraries/BluetoothSerial/examples/GetLocalMAC/ci.json
new file mode 100644
index 00000000000..b5097688f52
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/GetLocalMAC/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_BT_SPP_ENABLED=y"
+  ]
+}
diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino b/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino
index 9a5fa0877bc..53579c73334 100644
--- a/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino
+++ b/libraries/BluetoothSerial/examples/SerialToSerialBT/SerialToSerialBT.ino
@@ -1,21 +1,31 @@
-//This example code is in the Public Domain (or CC0 licensed, at your option.)
-//By Evandro Copercini - 2018
+// This example code is in the Public Domain (or CC0 licensed, at your option.)
+// By Evandro Copercini - 2018
 //
-//This example creates a bridge between Serial and Classical Bluetooth (SPP)
-//and also demonstrate that SerialBT have the same functionalities of a normal Serial
+// This example creates a bridge between Serial and Classical Bluetooth (SPP)
+// and also demonstrate that SerialBT have the same functionalities of a normal Serial
+// Note: Pairing is authenticated automatically by this device
 
 #include "BluetoothSerial.h"
 
+String device_name = "ESP32-BT-Slave";
+
+// Check if Bluetooth is available
 #if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED)
 #error Bluetooth is not enabled! Please run `make menuconfig` to and enable it
 #endif
 
+// Check Serial Port Profile
+#if !defined(CONFIG_BT_SPP_ENABLED)
+#error Serial Port Profile for Bluetooth is not available or not enabled. It is only available for the ESP32 chip.
+#endif
+
 BluetoothSerial SerialBT;
 
 void setup() {
   Serial.begin(115200);
-  SerialBT.begin("ESP32test"); //Bluetooth device name
-  Serial.println("The device started, now you can pair it with bluetooth!");
+  SerialBT.begin(device_name);  //Bluetooth device name
+  //SerialBT.deleteAllBondedDevices(); // Uncomment this to delete paired devices; Must be called after begin
+  Serial.printf("The device with name \"%s\" is started.\nNow you can pair it with Bluetooth!\n", device_name.c_str());
 }
 
 void loop() {
@@ -26,4 +36,4 @@ void loop() {
     Serial.write(SerialBT.read());
   }
   delay(20);
-}
\ No newline at end of file
+}
diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT/ci.json b/libraries/BluetoothSerial/examples/SerialToSerialBT/ci.json
new file mode 100644
index 00000000000..b5097688f52
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/SerialToSerialBT/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_BT_SPP_ENABLED=y"
+  ]
+}
diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino b/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino
index 73f3dc058b4..64774d41708 100644
--- a/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino
+++ b/libraries/BluetoothSerial/examples/SerialToSerialBTM/SerialToSerialBTM.ino
@@ -1,48 +1,89 @@
-//This example code is in the Public Domain (or CC0 licensed, at your option.)
-//By Victor Tchistiak - 2019
+// This example code is in the Public Domain (or CC0 licensed, at your option.)
+// By Victor Tchistiak - 2019
 //
-//This example demostrates master mode bluetooth connection and pin 
-//it creates a bridge between Serial and Classical Bluetooth (SPP)
-//this is an extention of the SerialToSerialBT example by Evandro Copercini - 2018
+// This example demonstrates master mode Bluetooth connection to a slave BT device
+// defined either by String "slaveName" by default "ESP32-BT-Slave" or by MAC address
 //
+// This example creates a bridge between Serial and Classical Bluetooth (SPP)
+// This is an extension of the SerialToSerialBT example by Evandro Copercini - 2018
+//
+// DO NOT try to connect to phone or laptop - they are master
+// devices, same as the ESP using this code - you will be able
+// to pair, but the serial communication will NOT work!
+//
+// You can try to flash a second ESP32 with the example SerialToSerialBT - it should
+// automatically pair with ESP32 running this code
+// Note: Pairing is authenticated automatically by this device
 
 #include "BluetoothSerial.h"
 
+#define USE_NAME  // Comment this to use MAC address instead of a slaveName
+
+// Check if Bluetooth is available
+#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED)
+#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it
+#endif
+
+// Check Serial Port Profile
+#if !defined(CONFIG_BT_SPP_ENABLED)
+#error Serial Port Profile for Bluetooth is not available or not enabled. It is only available for the ESP32 chip.
+#endif
 BluetoothSerial SerialBT;
 
-String MACadd = "AA:BB:CC:11:22:33";
-uint8_t address[6]  = {0xAA, 0xBB, 0xCC, 0x11, 0x22, 0x33};
-//uint8_t address[6]  = {0x00, 0x1D, 0xA5, 0x02, 0xC3, 0x22};
-String name = "OBDII";
-char *pin = "1234"; //<- standard pin would be provided by default
-bool connected;
+#ifdef USE_NAME
+String slaveName = "ESP32-BT-Slave";  // Change this to reflect the real name of your slave BT device
+#else
+String MACadd = "AA:BB:CC:11:22:33";                        // This only for printing
+uint8_t address[6] = {0xAA, 0xBB, 0xCC, 0x11, 0x22, 0x33};  // Change this to reflect real MAC address of your slave BT device
+#endif
+
+String myName = "ESP32-BT-Master";
 
 void setup() {
+  bool connected;
   Serial.begin(115200);
-  //SerialBT.setPin(pin);
-  SerialBT.begin("ESP32test", true); 
-  //SerialBT.setPin(pin);
-  Serial.println("The device started in master mode, make sure remote BT device is on!");
-  
-  // connect(address) is fast (upto 10 secs max), connect(name) is slow (upto 30 secs max) as it needs
-  // to resolve name to address first, but it allows to connect to different devices with the same name.
-  // Set CoreDebugLevel to Info to view devices bluetooth address and device names
-  connected = SerialBT.connect(name);
-  //connected = SerialBT.connect(address);
-  
-  if(connected) {
-    Serial.println("Connected Succesfully!");
+
+  SerialBT.begin(myName, true);
+  //SerialBT.deleteAllBondedDevices(); // Uncomment this to delete paired devices; Must be called after begin
+  Serial.printf("The device \"%s\" started in master mode, make sure slave BT device is on!\n", myName.c_str());
+
+#ifndef USE_NAME
+  SerialBT.setPin(pin);
+  Serial.println("Using PIN");
+#endif
+
+// connect(address) is fast (up to 10 secs max), connect(slaveName) is slow (up to 30 secs max) as it needs
+// to resolve slaveName to address first, but it allows to connect to different devices with the same name.
+// Set CoreDebugLevel to Info to view devices Bluetooth address and device names
+#ifdef USE_NAME
+  connected = SerialBT.connect(slaveName);
+  Serial.printf("Connecting to slave BT device named \"%s\"\n", slaveName.c_str());
+#else
+  connected = SerialBT.connect(address);
+  Serial.print("Connecting to slave BT device with MAC ");
+  Serial.println(MACadd);
+#endif
+
+  if (connected) {
+    Serial.println("Connected Successfully!");
   } else {
-    while(!SerialBT.connected(10000)) {
-      Serial.println("Failed to connect. Make sure remote device is available and in range, then restart app."); 
+    while (!SerialBT.connected(10000)) {
+      Serial.println("Failed to connect. Make sure remote device is available and in range, then restart app.");
     }
   }
-  // disconnect() may take upto 10 secs max
+  // Disconnect() may take up to 10 secs max
   if (SerialBT.disconnect()) {
-    Serial.println("Disconnected Succesfully!");
+    Serial.println("Disconnected Successfully!");
   }
-  // this would reconnect to the name(will use address, if resolved) or address used with connect(name/address).
+  // This would reconnect to the slaveName(will use address, if resolved) or address used with connect(slaveName/address).
   SerialBT.connect();
+  if (connected) {
+    Serial.println("Reconnected Successfully!");
+  } else {
+    while (!SerialBT.connected(10000)) {
+      Serial.println("Failed to reconnect. Make sure remote device is available and in range, then restart app.");
+    }
+  }
 }
 
 void loop() {
diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBTM/ci.json b/libraries/BluetoothSerial/examples/SerialToSerialBTM/ci.json
new file mode 100644
index 00000000000..b5097688f52
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/SerialToSerialBTM/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_BT_SPP_ENABLED=y"
+  ]
+}
diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/SerialToSerialBT_Legacy.ino b/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/SerialToSerialBT_Legacy.ino
new file mode 100644
index 00000000000..d184a4ea769
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/SerialToSerialBT_Legacy.ino
@@ -0,0 +1,58 @@
+// This example code is in the Public Domain (or CC0 licensed, at your option.)
+//
+// This example creates a bridge between Serial and Classical Bluetooth (SPP with authentication)
+// and also demonstrate that SerialBT have the same functionalities of a normal Serial
+// Legacy pairing TODO
+// Must be run as idf component ... todo
+
+#include "BluetoothSerial.h"
+
+// Check if Bluetooth is available
+#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED)
+#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it
+#endif
+
+// Check Serial Port Profile
+#if !defined(CONFIG_BT_SPP_ENABLED)
+#error Serial Port Profile for Bluetooth is not available or not enabled. It is only available for the ESP32 chip.
+#endif
+
+const char *deviceName = "ESP32_Legacy_example";
+
+BluetoothSerial SerialBT;
+bool confirmRequestDone = false;
+
+void BTAuthCompleteCallback(boolean success) {
+  if (success) {
+    confirmRequestDone = true;
+    Serial.println("Pairing success!!");
+  } else {
+    Serial.println("Pairing failed, rejected by user!!");
+  }
+}
+
+void serial_response() {
+  if (Serial.available()) {
+    SerialBT.write(Serial.read());
+  }
+  if (SerialBT.available()) {
+    Serial.write(SerialBT.read());
+  }
+  delay(20);
+}
+
+void setup() {
+  Serial.begin(115200);
+  SerialBT.onAuthComplete(BTAuthCompleteCallback);
+  SerialBT.begin(deviceName);  // Initiate Bluetooth device with name in parameter
+  SerialBT.setPin("1234", 4);
+  Serial.printf("The device started with name \"%s\", now you can pair it with Bluetooth!\n", deviceName);
+}
+
+void loop() {
+  if (confirmRequestDone) {
+    serial_response();
+  } else {
+    delay(1);  // Feed the watchdog
+  }
+}
diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/ci.json b/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/ci.json
new file mode 100644
index 00000000000..b5097688f52
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/SerialToSerialBT_Legacy/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_BT_SPP_ENABLED=y"
+  ]
+}
diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/SerialToSerialBT_SSP.ino b/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/SerialToSerialBT_SSP.ino
new file mode 100644
index 00000000000..e5d05eed14e
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/SerialToSerialBT_SSP.ino
@@ -0,0 +1,131 @@
+// This example code is in the Public Domain (or CC0 licensed, at your option.)
+// By Richard Li - 2020
+//
+// This example creates a bridge between Serial and Classical Bluetooth (SPP with authentication)
+// and also demonstrate that SerialBT have the same functionalities of a normal Serial
+// SSP - Simple Secure Pairing - The device (ESP32) will display random number and the user is responsible of comparing it to the number
+// displayed on the other device (for example phone).
+// If the numbers match the user authenticates the pairing on both devices - on phone simply press "Pair" and in terminal for the sketch send 'Y' or 'y' to confirm.
+// Alternatively uncomment AUTO_PAIR to skip the terminal confirmation.
+
+#include "BluetoothSerial.h"
+
+//#define AUTO_PAIR // Uncomment to automatically authenticate ESP32 side
+
+// Check if Bluetooth is available
+#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED)
+#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it
+#endif
+
+// Check Serial Port Profile
+#if !defined(CONFIG_BT_SPP_ENABLED)
+#error Serial Port Profile for Bluetooth is not available or not enabled. It is only available for the ESP32 chip.
+#endif
+
+const char *deviceName = "ESP32_SSP_example";
+
+// The following lines defines the method of pairing
+// When both Input and Output are false only the other device authenticates pairing without any pin.
+// When Output is true and Input is false only the other device authenticates pairing without any pin.
+// When both Input and Output are true both devices display randomly generated code and if they match authenticate pairing on both devices
+//   - This must be implemented by registering callback via onConfirmRequest() and in this callback request user input and call confirmReply(true); if the authenticated
+//      otherwise call `confirmReply(false)` to reject the pairing.
+// When Input is true and Output is false User will be required to input the passkey to the ESP32 device to authenticate.
+//   - This must be implemented by registering callback via onKeyRequest() and in this callback the entered passkey will be responded via respondPasskey(passkey);
+const bool INPUT_CAPABILITY = false;  // Defines if ESP32 device has input method (Serial terminal, keyboard or similar)
+const bool OUTPUT_CAPABILITY = true;  // Defines if ESP32 device has output method (Serial terminal, display or similar)
+
+BluetoothSerial SerialBT;
+bool confirmRequestDone = false;
+
+void BTConfirmRequestCallback(uint32_t numVal) {
+  confirmRequestDone = false;
+#ifndef AUTO_PAIR
+  Serial.printf(
+    "The PIN is: %06lu. If it matches number displayed on the other device write \'Y\' or \'y\':\n", numVal
+  );  // Note the formatting "%06lu" - PIN can start with zero(s) which would be ignored with simple "%lu"
+  while (!Serial.available()) {
+    delay(1);  // Feed the watchdog
+    // Wait until data is available on the Serial port.
+  }
+  Serial.printf("Oh you sent %d Bytes, lets see...", Serial.available());
+  int dat = Serial.read();
+  if (dat == 'Y' || dat == 'y') {
+    SerialBT.confirmReply(true);
+  } else {
+    SerialBT.confirmReply(false);
+  }
+#else
+  SerialBT.confirmReply(true);
+#endif
+}
+
+void BTKeyRequestCallback() {
+  Serial.println("BTKeyRequestCallback");  // debug
+  char buffer[7] = {0};                    // 6 bytes for number, one for termination '0'
+  while (1) {
+    Serial.print("Enter the passkey displayed on the other device: ");
+    while (!Serial.available()) {
+      delay(1);  // Feed the watchdog
+      // Wait until data is available on the Serial port.
+    }
+    size_t len = Serial.readBytesUntil('\n', buffer, sizeof(buffer) - 1);
+    buffer[len] = '\0';  // Null-terminate the string.
+    try {
+      uint32_t passkey = std::stoi(buffer);
+      Serial.printf("Entered PIN: %lu\n", passkey);
+      SerialBT.respondPasskey(passkey);
+      return;
+    } catch (...) {
+      Serial.print("Wrong PIN! Try again.");
+    }  // try
+  }  // while(1)
+}
+
+void BTAuthCompleteCallback(boolean success) {
+  if (success) {
+    confirmRequestDone = true;
+    Serial.println("Pairing success!!");
+  } else {
+    Serial.println("Pairing failed, rejected by user!!");
+  }
+}
+
+void serial_response() {
+  if (Serial.available()) {
+    SerialBT.write(Serial.read());
+  }
+  if (SerialBT.available()) {
+    Serial.write(SerialBT.read());
+  }
+  delay(20);
+}
+
+void setup() {
+  Serial.begin(115200);
+  SerialBT.enableSSP(INPUT_CAPABILITY, OUTPUT_CAPABILITY);  // Must be called before begin
+  SerialBT.onConfirmRequest(BTConfirmRequestCallback);
+  SerialBT.onKeyRequest(BTKeyRequestCallback);
+  SerialBT.onAuthComplete(BTAuthCompleteCallback);
+  SerialBT.begin(deviceName);  // Initiate Bluetooth device with name in parameter
+  //SerialBT.deleteAllBondedDevices(); // Uncomment this to delete paired devices; Must be called after begin
+  Serial.printf("The device started with name \"%s\", now you can pair it with Bluetooth!\n", deviceName);
+  if (INPUT_CAPABILITY and OUTPUT_CAPABILITY) {
+    Serial.println("Both devices will display randomly generated code and if they match authenticate pairing on both devices");
+  } else if (not INPUT_CAPABILITY and not OUTPUT_CAPABILITY) {
+    Serial.println("Authenticate pairing on the other device. No PIN is used");
+  } else if (not INPUT_CAPABILITY and OUTPUT_CAPABILITY) {
+    Serial.println("Authenticate pairing on the other device. No PIN is used");
+  } else if (INPUT_CAPABILITY and not OUTPUT_CAPABILITY) {
+    Serial.println("After pairing is initiated you will be required to enter the passkey to the ESP32 device to authenticate\n > The Passkey will displayed on "
+                   "the other device");
+  }
+}
+
+void loop() {
+  if (confirmRequestDone) {
+    serial_response();
+  } else {
+    delay(1);  // Feed the watchdog
+  }
+}
diff --git a/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/ci.json b/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/ci.json
new file mode 100644
index 00000000000..b5097688f52
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/SerialToSerialBT_SSP/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_BT_SPP_ENABLED=y"
+  ]
+}
diff --git a/libraries/BluetoothSerial/examples/bt_classic_device_discovery/bt_classic_device_discovery.ino b/libraries/BluetoothSerial/examples/bt_classic_device_discovery/bt_classic_device_discovery.ino
new file mode 100644
index 00000000000..226cbd8da31
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/bt_classic_device_discovery/bt_classic_device_discovery.ino
@@ -0,0 +1,53 @@
+#include <BluetoothSerial.h>
+
+#if !defined(CONFIG_BT_ENABLED) || !defined(CONFIG_BLUEDROID_ENABLED)
+#error Bluetooth is not enabled! Please run `make menuconfig` to and enable it
+#endif
+
+#if !defined(CONFIG_BT_SPP_ENABLED)
+#error Serial Bluetooth not available or not enabled. It is only available for the ESP32 chip.
+#endif
+
+BluetoothSerial SerialBT;
+
+#define BT_DISCOVER_TIME 10000
+
+static bool btScanAsync = true;
+static bool btScanSync = true;
+
+void btAdvertisedDeviceFound(BTAdvertisedDevice *pDevice) {
+  Serial.printf("Found a device asynchronously: %s\n", pDevice->toString().c_str());
+}
+
+void setup() {
+  Serial.begin(115200);
+  SerialBT.begin("ESP32test");  //Bluetooth device name
+  Serial.println("The device started, now you can pair it with bluetooth!");
+
+  if (btScanAsync) {
+    Serial.print("Starting asynchronous discovery... ");
+    if (SerialBT.discoverAsync(btAdvertisedDeviceFound)) {
+      Serial.println("Findings will be reported in \"btAdvertisedDeviceFound\"");
+      delay(10000);
+      Serial.print("Stopping discoverAsync... ");
+      SerialBT.discoverAsyncStop();
+      Serial.println("stopped");
+    } else {
+      Serial.println("Error on discoverAsync f.e. not working after a \"connect\"");
+    }
+  }
+
+  if (btScanSync) {
+    Serial.println("Starting synchronous discovery... ");
+    BTScanResults *pResults = SerialBT.discover(BT_DISCOVER_TIME);
+    if (pResults) {
+      pResults->dump(&Serial);
+    } else {
+      Serial.println("Error on BT Scan, no result!");
+    }
+  }
+}
+
+void loop() {
+  delay(100);
+}
diff --git a/libraries/BluetoothSerial/examples/bt_classic_device_discovery/ci.json b/libraries/BluetoothSerial/examples/bt_classic_device_discovery/ci.json
new file mode 100644
index 00000000000..b5097688f52
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/bt_classic_device_discovery/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_BT_SPP_ENABLED=y"
+  ]
+}
diff --git a/libraries/BluetoothSerial/examples/bt_remove_paired_devices/bt_remove_paired_devices.ino b/libraries/BluetoothSerial/examples/bt_remove_paired_devices/bt_remove_paired_devices.ino
old mode 100755
new mode 100644
index c316a73b2bc..6f301bd28ba
--- a/libraries/BluetoothSerial/examples/bt_remove_paired_devices/bt_remove_paired_devices.ino
+++ b/libraries/BluetoothSerial/examples/bt_remove_paired_devices/bt_remove_paired_devices.ino
@@ -1,87 +1,73 @@
-//This example code is in the Public Domain (or CC0 licensed, at your option.)
-//By Victor Tchistiak - 2019
+// This example code is in the Public Domain (or CC0 licensed, at your option.)
+// Originally by Victor Tchistiak - 2019
+// Rewritten with new API by Tomas Pilny - 2023
 //
-//This example demonstrates reading and removing paired devices stored on the ESP32 flash memory
-//Sometimes you may find your ESP32 device could not connect to the remote device despite
-//many successful connections earlier. This is most likely a result of client replacing your paired
-//device info with new one from other device. The BT clients store connection info for paired devices,
-//but it is limited to a few devices only. When new device pairs and number of stored devices is exceeded,
-//one of the previously paired devices would be replaced with new one.
-//The only remedy is to delete this saved bound device from your device flash memory
-//and pair with the other device again.
-//
-#include "esp_bt_main.h"
-#include "esp_bt_device.h"
-#include"esp_gap_bt_api.h"
-#include "esp_err.h"
+// This example demonstrates reading and removing paired devices stored on the ESP32 flash memory
+// Sometimes you may find your ESP32 device could not connect to the remote device despite
+// many successful connections earlier. This is most likely a result of client replacing your paired
+// device info with new one from other device. The BT clients store connection info for paired devices,
+// but it is limited to a few devices only. When new device pairs and number of stored devices is exceeded,
+// one of the previously paired devices would be replaced with new one.
+// The only remedy is to delete this saved bound device from your device flash memory
+// and pair with the other device again.
 
-#define REMOVE_BONDED_DEVICES 0   // <- Set to 0 to view all bonded devices addresses, set to 1 to remove
+#include "BluetoothSerial.h"
+//#include "esp_bt_device.h"
 
-#define PAIR_MAX_DEVICES 20
-uint8_t pairedDeviceBtAddr[PAIR_MAX_DEVICES][6];
-char bda_str[18];
+#if !defined(CONFIG_BT_SPP_ENABLED)
+#error Serial Bluetooth not available or not enabled. It is only available for the ESP32 chip.
+#endif
 
-bool initBluetooth()
-{
-  if(!btStart()) {
-    Serial.println("Failed to initialize controller");
-    return false;
-  }
- 
-  if(esp_bluedroid_init() != ESP_OK) {
-    Serial.println("Failed to initialize bluedroid");
-    return false;
-  }
- 
-  if(esp_bluedroid_enable() != ESP_OK) {
-    Serial.println("Failed to enable bluedroid");
-    return false;
-  }
-  return true;
-}
+#define REMOVE_BONDED_DEVICES true  // <- Set to `false` to view all bonded devices addresses, set to `true` to remove
+#define PAIR_MAX_DEVICES      20
+BluetoothSerial SerialBT;
 
-char *bda2str(const uint8_t* bda, char *str, size_t size)
-{
+char *bda2str(const uint8_t *bda, char *str, size_t size) {
   if (bda == NULL || str == NULL || size < 18) {
     return NULL;
   }
-  sprintf(str, "%02x:%02x:%02x:%02x:%02x:%02x",
-          bda[0], bda[1], bda[2], bda[3], bda[4], bda[5]);
+  sprintf(str, "%02x:%02x:%02x:%02x:%02x:%02x", bda[0], bda[1], bda[2], bda[3], bda[4], bda[5]);
   return str;
 }
- 
+
 void setup() {
+  char bda_str[18];
+  uint8_t pairedDeviceBtAddr[PAIR_MAX_DEVICES][6];
   Serial.begin(115200);
- 
-  initBluetooth();
-  Serial.print("ESP32 bluetooth address: "); Serial.println(bda2str(esp_bt_dev_get_address(), bda_str, 18));
+
+  SerialBT.begin();
+  Serial.printf("ESP32 bluetooth address: %s\n", SerialBT.getBtAddressString().c_str());
+  // SerialBT.deleteAllBondedDevices(); // If you want just delete all, this is the way
   // Get the numbers of bonded/paired devices in the BT module
-  int count = esp_bt_gap_get_bond_device_num();
-  if(!count) {
-    Serial.println("No bonded device found.");
+  int count = SerialBT.getNumberOfBondedDevices();
+  if (!count) {
+    Serial.println("No bonded devices found.");
   } else {
-    Serial.print("Bonded device count: "); Serial.println(count);
-    if(PAIR_MAX_DEVICES < count) {
-      count = PAIR_MAX_DEVICES; 
-      Serial.print("Reset bonded device count: "); Serial.println(count);
+    Serial.printf("Bonded device count: %d\n", count);
+    if (PAIR_MAX_DEVICES < count) {
+      count = PAIR_MAX_DEVICES;
+      Serial.printf("Reset %d bonded devices\n", count);
     }
-    esp_err_t tError =  esp_bt_gap_get_bond_device_list(&count, pairedDeviceBtAddr);
-    if(ESP_OK == tError) {
-      for(int i = 0; i < count; i++) {
-        Serial.print("Found bonded device # "); Serial.print(i); Serial.print(" -> ");
-        Serial.println(bda2str(pairedDeviceBtAddr[i], bda_str, 18));     
-        if(REMOVE_BONDED_DEVICES) {
-          esp_err_t tError = esp_bt_gap_remove_bond_device(pairedDeviceBtAddr[i]);
-          if(ESP_OK == tError) {
-            Serial.print("Removed bonded device # "); 
-          } else {
-            Serial.print("Failed to remove bonded device # ");
-          }
-          Serial.println(i);
+    count = SerialBT.getBondedDevices(count, pairedDeviceBtAddr);
+    char rmt_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1];
+    if (count > 0) {
+      for (int i = 0; i < count; i++) {
+        SerialBT.requestRemoteName(pairedDeviceBtAddr[i]);
+        while (!SerialBT.readRemoteName(rmt_name)) {
+          delay(1);  // Wait for response with the device name
         }
-      }        
-    }
-  }
+        Serial.printf("Found bonded device #%d BDA:%s; Name:\"%s\"\n", i, bda2str(pairedDeviceBtAddr[i], bda_str, 18), rmt_name);
+        SerialBT.invalidateRemoteName();  // Allows waiting for next reading
+        if (REMOVE_BONDED_DEVICES) {
+          if (SerialBT.deleteBondedDevice(pairedDeviceBtAddr[i])) {
+            Serial.printf("Removed bonded device # %d\n", i);
+          } else {
+            Serial.printf("Failed to remove bonded device # %d", i);
+          }  // if(ESP_OK == tError)
+        }  // if(REMOVE_BONDED_DEVICES)
+      }  // for(int i = 0; i < count; i++)
+    }  // if(ESP_OK == tError)
+  }  // if(!count)
 }
- 
+
 void loop() {}
diff --git a/libraries/BluetoothSerial/examples/bt_remove_paired_devices/ci.json b/libraries/BluetoothSerial/examples/bt_remove_paired_devices/ci.json
new file mode 100644
index 00000000000..b5097688f52
--- /dev/null
+++ b/libraries/BluetoothSerial/examples/bt_remove_paired_devices/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_BT_SPP_ENABLED=y"
+  ]
+}
diff --git a/libraries/BluetoothSerial/library.properties b/libraries/BluetoothSerial/library.properties
index 20adb66c796..0a382410bba 100644
--- a/libraries/BluetoothSerial/library.properties
+++ b/libraries/BluetoothSerial/library.properties
@@ -1,5 +1,5 @@
 name=BluetoothSerial
-version=1.0
+version=3.2.0
 author=Evandro Copercini
 maintainer=Evandro Copercini
 sentence=Simple UART to Classical Bluetooth bridge for ESP32
diff --git a/libraries/BluetoothSerial/src/BTAddress.cpp b/libraries/BluetoothSerial/src/BTAddress.cpp
new file mode 100644
index 00000000000..6a6de6522bd
--- /dev/null
+++ b/libraries/BluetoothSerial/src/BTAddress.cpp
@@ -0,0 +1,112 @@
+/*
+ * BTAddress.cpp
+ *
+ *  Created on: Jul 2, 2017
+ *      Author: kolban
+ *  Ported  on: Feb 5, 2021
+ *      Author: Thomas M. (ArcticSnowSky)
+ */
+#include "sdkconfig.h"
+#if defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED)
+
+#include "BTAddress.h"
+#include <string>
+#include <sstream>
+#include <iomanip>
+#include <string.h>
+#include <stdio.h>
+#include <malloc.h>
+#ifdef ARDUINO_ARCH_ESP32
+#include "esp32-hal-log.h"
+#endif
+
+/**
+ * @brief Create an address from the native ESP32 representation.
+ * @param [in] address The native representation.
+ */
+BTAddress::BTAddress(esp_bd_addr_t address) {
+  memcpy(m_address, address, ESP_BD_ADDR_LEN);
+}  // BTAddress
+
+BTAddress::BTAddress() {
+  bzero(m_address, ESP_BD_ADDR_LEN);
+}  // BTAddress
+
+/**
+ * @brief Create an address from a hex string
+ *
+ * A hex string is of the format:
+ * ```
+ * 00:00:00:00:00:00
+ * ```
+ * which is 17 characters in length.
+ *
+ * @param [in] stringAddress The hex representation of the address.
+ */
+BTAddress::BTAddress(String stringAddress) {
+  if (stringAddress.length() != 17) {
+    return;
+  }
+
+  int data[6];
+  sscanf(stringAddress.c_str(), "%x:%x:%x:%x:%x:%x", &data[0], &data[1], &data[2], &data[3], &data[4], &data[5]);
+  m_address[0] = (uint8_t)data[0];
+  m_address[1] = (uint8_t)data[1];
+  m_address[2] = (uint8_t)data[2];
+  m_address[3] = (uint8_t)data[3];
+  m_address[4] = (uint8_t)data[4];
+  m_address[5] = (uint8_t)data[5];
+}  // BTAddress
+
+/**
+ * @brief Determine if this address equals another.
+ * @param [in] otherAddress The other address to compare against.
+ * @return True if the addresses are equal.
+ */
+bool BTAddress::equals(BTAddress otherAddress) {
+  return memcmp(otherAddress.getNative(), m_address, 6) == 0;
+}  // equals
+
+BTAddress::operator bool() const {
+  for (int i = 0; i < ESP_BD_ADDR_LEN; i++) {
+    if (this->m_address[i]) {
+      return true;
+    }
+  }
+  return false;
+}  // operator ()
+
+/**
+ * @brief Return the native representation of the address.
+ * @return The native representation of the address.
+ */
+esp_bd_addr_t *BTAddress::getNative() const {
+  return const_cast<esp_bd_addr_t *>(&m_address);
+}  // getNative
+
+/**
+ * @brief Convert a BT address to a string.
+ * @param [in] capital changes the letter size
+ * By default the parameter `capital` == false and the string representation of an address is in the format:
+ * ```
+ * xx:xx:xx:xx:xx:xx
+ * ```
+ * When the parameter `capital` == true the format uses capital letters:
+ * ```
+ * XX:XX:XX:XX:XX:XX
+ * ```
+ * @return The string representation of the address.
+ */
+String BTAddress::toString(bool capital) const {
+  auto size = 18;
+  char *res = (char *)malloc(size);
+  if (capital) {
+    snprintf(res, size, "%02X:%02X:%02X:%02X:%02X:%02X", m_address[0], m_address[1], m_address[2], m_address[3], m_address[4], m_address[5]);
+  } else {
+    snprintf(res, size, "%02x:%02x:%02x:%02x:%02x:%02x", m_address[0], m_address[1], m_address[2], m_address[3], m_address[4], m_address[5]);
+  }
+  String ret(res);
+  free(res);
+  return ret;
+}  // toString
+#endif
diff --git a/libraries/BluetoothSerial/src/BTAddress.h b/libraries/BluetoothSerial/src/BTAddress.h
new file mode 100644
index 00000000000..a2af9247fb0
--- /dev/null
+++ b/libraries/BluetoothSerial/src/BTAddress.h
@@ -0,0 +1,38 @@
+/*
+ * BTAddress.h
+ *
+ *  Created on: Jul 2, 2017
+ *      Author: kolban
+ *  Ported  on: Feb 5, 2021
+ *      Author: Thomas M. (ArcticSnowSky)
+ */
+
+#ifndef COMPONENTS_CPP_UTILS_BTADDRESS_H_
+#define COMPONENTS_CPP_UTILS_BTADDRESS_H_
+#include "sdkconfig.h"
+#if defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED)
+#include <esp_gap_bt_api.h>  // ESP32 BT
+#include <Arduino.h>
+
+/**
+ * @brief A %BT device address.
+ *
+ * Every %BT device has a unique address which can be used to identify it and form connections.
+ */
+class BTAddress {
+public:
+  BTAddress();
+  BTAddress(esp_bd_addr_t address);
+  BTAddress(String stringAddress);
+  bool equals(BTAddress otherAddress);
+  operator bool() const;
+
+  esp_bd_addr_t *getNative() const;
+  String toString(bool capital = false) const;
+
+private:
+  esp_bd_addr_t m_address;
+};
+
+#endif /* CONFIG_BT_ENABLED */
+#endif /* COMPONENTS_CPP_UTILS_BTADDRESS_H_ */
diff --git a/libraries/BluetoothSerial/src/BTAdvertisedDevice.h b/libraries/BluetoothSerial/src/BTAdvertisedDevice.h
new file mode 100644
index 00000000000..63c19c908b6
--- /dev/null
+++ b/libraries/BluetoothSerial/src/BTAdvertisedDevice.h
@@ -0,0 +1,61 @@
+/*
+ * BTAdvertisedDevice.h
+ *
+ *  Created on: Feb 5, 2021
+ *      Author: Thomas M. (ArcticSnowSky)
+ */
+
+#ifndef __BTADVERTISEDDEVICE_H__
+#define __BTADVERTISEDDEVICE_H__
+
+#include "BTAddress.h"
+#include <string>
+
+class BTAdvertisedDevice {
+public:
+  virtual ~BTAdvertisedDevice() = default;
+
+  virtual BTAddress getAddress() = 0;
+  virtual uint32_t getCOD() const = 0;
+  virtual std::string getName() const = 0;
+  virtual int8_t getRSSI() const = 0;
+
+  virtual bool haveCOD() const = 0;
+  virtual bool haveName() const = 0;
+  virtual bool haveRSSI() const = 0;
+
+  virtual std::string toString() = 0;
+};
+
+class BTAdvertisedDeviceSet : public virtual BTAdvertisedDevice {
+public:
+  BTAdvertisedDeviceSet();
+  //~BTAdvertisedDeviceSet() = default;
+
+  BTAddress getAddress();
+  uint32_t getCOD() const;
+  std::string getName() const;
+  int8_t getRSSI() const;
+
+  bool haveCOD() const;
+  bool haveName() const;
+  bool haveRSSI() const;
+
+  std::string toString();
+
+  void setAddress(BTAddress address);
+  void setCOD(uint32_t cod);
+  void setName(std::string name);
+  void setRSSI(int8_t rssi);
+
+  bool m_haveCOD;
+  bool m_haveName;
+  bool m_haveRSSI;
+
+  BTAddress m_address = BTAddress((uint8_t *)"\0\0\0\0\0\0");
+  uint32_t m_cod;
+  std::string m_name;
+  int8_t m_rssi;
+};
+
+#endif
diff --git a/libraries/BluetoothSerial/src/BTAdvertisedDeviceSet.cpp b/libraries/BluetoothSerial/src/BTAdvertisedDeviceSet.cpp
new file mode 100644
index 00000000000..ed6076a3103
--- /dev/null
+++ b/libraries/BluetoothSerial/src/BTAdvertisedDeviceSet.cpp
@@ -0,0 +1,89 @@
+/*
+ * BTAdvertisedDeviceSet.cpp
+ *
+ *  Created on: Feb 5, 2021
+ *      Author: Thomas M. (ArcticSnowSky)
+ */
+
+#include "sdkconfig.h"
+#if defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED)
+
+//#include <map>
+
+#include "BTAdvertisedDevice.h"
+//#include "BTScan.h"
+
+BTAdvertisedDeviceSet::BTAdvertisedDeviceSet() {
+  m_cod = 0;
+  m_name = "";
+  m_rssi = 0;
+
+  m_haveCOD = false;
+  m_haveName = false;
+  m_haveRSSI = false;
+}  // BTAdvertisedDeviceSet
+
+BTAddress BTAdvertisedDeviceSet::getAddress() {
+  return m_address;
+}
+uint32_t BTAdvertisedDeviceSet::getCOD() const {
+  return m_cod;
+}
+std::string BTAdvertisedDeviceSet::getName() const {
+  return m_name;
+}
+int8_t BTAdvertisedDeviceSet::getRSSI() const {
+  return m_rssi;
+}
+
+bool BTAdvertisedDeviceSet::haveCOD() const {
+  return m_haveCOD;
+}
+bool BTAdvertisedDeviceSet::haveName() const {
+  return m_haveName;
+}
+bool BTAdvertisedDeviceSet::haveRSSI() const {
+  return m_haveRSSI;
+}
+
+/**
+ * @brief Create a string representation of this device.
+ * @return A string representation of this device.
+ */
+std::string BTAdvertisedDeviceSet::toString() {
+  std::string res = "Name: " + getName() + ", Address: " + std::string(getAddress().toString().c_str(), getAddress().toString().length());
+  if (haveCOD()) {
+    char val[7];  //6 hex digits + null
+    snprintf(val, sizeof(val), "%06lx", getCOD() & 0xFFFFFF);
+    res += ", cod: 0x";
+    res += val;
+  }
+  if (haveRSSI()) {
+    char val[6];
+    snprintf(val, sizeof(val), "%d", (int8_t)getRSSI());
+    res += ", rssi: ";
+    res += val;
+  }
+  return res;
+}  // toString
+
+void BTAdvertisedDeviceSet::setAddress(BTAddress address) {
+  m_address = address;
+}
+
+void BTAdvertisedDeviceSet::setCOD(uint32_t cod) {
+  m_cod = cod;
+  m_haveCOD = true;
+}
+
+void BTAdvertisedDeviceSet::setName(std::string name) {
+  m_name = name;
+  m_haveName = true;
+}
+
+void BTAdvertisedDeviceSet::setRSSI(int8_t rssi) {
+  m_rssi = rssi;
+  m_haveRSSI = true;
+}
+
+#endif /* CONFIG_BT_ENABLED */
diff --git a/libraries/BluetoothSerial/src/BTScan.h b/libraries/BluetoothSerial/src/BTScan.h
new file mode 100644
index 00000000000..a08f68cd7c2
--- /dev/null
+++ b/libraries/BluetoothSerial/src/BTScan.h
@@ -0,0 +1,41 @@
+/*
+ * BTScan.h
+ *
+ *  Created on: Feb 5, 2021
+ *      Author: Thomas M. (ArcticSnowSky)
+ */
+
+#ifndef __BTSCAN_H__
+#define __BTSCAN_H__
+
+#include <map>
+#include <string>
+#include <Print.h>
+#include "BTAddress.h"
+#include "BTAdvertisedDevice.h"
+
+class BTAdvertisedDevice;
+class BTAdvertisedDeviceSet;
+
+class BTScanResults {
+public:
+  virtual ~BTScanResults() = default;
+
+  virtual void dump(Print *print = nullptr) = 0;
+  virtual int getCount() = 0;
+  virtual BTAdvertisedDevice *getDevice(int i) = 0;
+};
+
+class BTScanResultsSet : public BTScanResults {
+public:
+  void dump(Print *print = nullptr);
+  int getCount();
+  BTAdvertisedDevice *getDevice(int i);
+
+  bool add(BTAdvertisedDeviceSet advertisedDevice, bool unique = true);
+  void clear();
+
+  std::map<std::string, BTAdvertisedDeviceSet> m_vectorAdvertisedDevices;
+};
+
+#endif
diff --git a/libraries/BluetoothSerial/src/BTScanResultsSet.cpp b/libraries/BluetoothSerial/src/BTScanResultsSet.cpp
new file mode 100644
index 00000000000..3633c010eae
--- /dev/null
+++ b/libraries/BluetoothSerial/src/BTScanResultsSet.cpp
@@ -0,0 +1,97 @@
+/*
+ * BTScanResultsSet.cpp
+ *
+ *  Created on: Feb 5, 2021
+ *      Author: Thomas M. (ArcticSnowSky)
+ */
+
+#include "sdkconfig.h"
+#if defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED)
+
+#include <esp_err.h>
+
+#include "BTAdvertisedDevice.h"
+#include "BTScan.h"
+//#include "GeneralUtils.h"
+#include "esp32-hal-log.h"
+
+class BTAdvertisedDevice;
+
+/**
+ * @brief Dump the scan results to the log.
+ */
+void BTScanResultsSet::dump(Print *print) {
+  int cnt = getCount();
+  if (print == nullptr) {
+    log_v(">> Dump scan results : %d", cnt);
+    for (int i = 0; i < cnt; i++) {
+      BTAdvertisedDevice *dev = getDevice(i);
+      if (dev) {
+        log_d("- %d: %s\n", i + 1, dev->toString().c_str());
+      } else {
+        log_d("- %d is null\n", i + 1);
+      }
+    }
+    log_v("-- dump finished --");
+  } else {
+    print->printf(">> Dump scan results: %d\n", cnt);
+    for (int i = 0; i < cnt; i++) {
+      BTAdvertisedDevice *dev = getDevice(i);
+      if (dev) {
+        print->printf("- %d: %s\n", i + 1, dev->toString().c_str());
+      } else {
+        print->printf("- %d is null\n", i + 1);
+      }
+    }
+    print->println("-- Dump finished --");
+  }
+}  // dump
+
+/**
+ * @brief Return the count of devices found in the last scan.
+ * @return The number of devices found in the last scan.
+ */
+int BTScanResultsSet::getCount() {
+  return m_vectorAdvertisedDevices.size();
+}  // getCount
+
+/**
+ * @brief Return the specified device at the given index.
+ * The index should be between 0 and getCount()-1.
+ * @param [in] i The index of the device.
+ * @return The device at the specified index.
+ */
+BTAdvertisedDevice *BTScanResultsSet::getDevice(int i) {
+  if (i < 0) {
+    return nullptr;
+  }
+
+  int x = 0;
+  BTAdvertisedDeviceSet *pDev = &m_vectorAdvertisedDevices.begin()->second;
+  for (auto it = m_vectorAdvertisedDevices.begin(); it != m_vectorAdvertisedDevices.end(); it++) {
+    pDev = &it->second;
+    if (x == i) {
+      break;
+    }
+    x++;
+  }
+  return x == i ? pDev : nullptr;
+}
+
+void BTScanResultsSet::clear() {
+  //for(auto _dev : m_vectorAdvertisedDevices)
+  //	delete _dev.second;
+  m_vectorAdvertisedDevices.clear();
+}
+
+bool BTScanResultsSet::add(BTAdvertisedDeviceSet advertisedDevice, bool unique) {
+  std::string key = std::string(advertisedDevice.getAddress().toString().c_str(), advertisedDevice.getAddress().toString().length());
+  if (!unique || m_vectorAdvertisedDevices.count(key) == 0) {
+    m_vectorAdvertisedDevices.insert(std::pair<std::string, BTAdvertisedDeviceSet>(key, advertisedDevice));
+    return true;
+  } else {
+    return false;
+  }
+}
+
+#endif
diff --git a/libraries/BluetoothSerial/src/BluetoothSerial.cpp b/libraries/BluetoothSerial/src/BluetoothSerial.cpp
old mode 100755
new mode 100644
index a52e48d8615..3d00504c1b1
--- a/libraries/BluetoothSerial/src/BluetoothSerial.cpp
+++ b/libraries/BluetoothSerial/src/BluetoothSerial.cpp
@@ -20,7 +20,6 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 
-
 #if defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED)
 
 #ifdef ARDUINO_ARCH_ESP32
@@ -28,6 +27,7 @@
 #endif
 
 #include "BluetoothSerial.h"
+#include "BTAdvertisedDevice.h"
 
 #include "esp_bt.h"
 #include "esp_bt_main.h"
@@ -38,769 +38,1322 @@
 
 #include "esp32-hal-log.h"
 
-const char * _spp_server_name = "ESP32SPP";
+const char *_spp_server_name = "ESP32SPP";
+
+#define RX_QUEUE_SIZE         512
+#define TX_QUEUE_SIZE         32
+#define SPP_TX_QUEUE_TIMEOUT  1000
+#define SPP_TX_DONE_TIMEOUT   1000
+#define SPP_CONGESTED_TIMEOUT 1000
 
-#define RX_QUEUE_SIZE 512
-#define TX_QUEUE_SIZE 32
 static uint32_t _spp_client = 0;
-static xQueueHandle _spp_rx_queue = NULL;
-static xQueueHandle _spp_tx_queue = NULL;
+static QueueHandle_t _spp_rx_queue = NULL;
+static QueueHandle_t _spp_tx_queue = NULL;
 static SemaphoreHandle_t _spp_tx_done = NULL;
 static TaskHandle_t _spp_task_handle = NULL;
 static EventGroupHandle_t _spp_event_group = NULL;
+static EventGroupHandle_t _bt_event_group = NULL;
 static boolean secondConnectionAttempt;
-static esp_spp_cb_t * custom_spp_callback = NULL;
+static esp_spp_cb_t custom_spp_callback = NULL;
 static BluetoothSerialDataCb custom_data_callback = NULL;
-
-#define INQ_LEN 0x10
-#define INQ_NUM_RSPS 20
+static esp_bd_addr_t current_bd_addr;
+static ConfirmRequestCb confirm_request_callback = NULL;
+static KeyRequestCb key_request_callback = NULL;
+static AuthCompleteCb auth_complete_callback = NULL;
+static bool _rmt_name_valid = false;
+static uint8_t _rmt_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1] = {0};
+
+#define INQ_LEN       0x10
+#define INQ_NUM_RSPS  20
 #define READY_TIMEOUT (10 * 1000)
-#define SCAN_TIMEOUT (INQ_LEN * 2 * 1000)
+#define SCAN_TIMEOUT  (INQ_LEN * 2 * 1000)
 static esp_bd_addr_t _peer_bd_addr;
 static char _remote_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1];
 static bool _isRemoteAddressSet;
 static bool _isMaster;
-static esp_bt_pin_code_t _pin_code;
-static int _pin_len;
-static bool _isPinSet;
 static bool _enableSSP;
-
-#define SPP_RUNNING     0x01
-#define SPP_CONNECTED   0x02
-#define SPP_CONGESTED   0x04
+static bool _IO_CAP_INPUT;
+static bool _IO_CAP_OUTPUT;
+esp_bt_pin_code_t _pin_code = {0};
+uint8_t _pin_code_len = 0;  // Number of valid Bytes in the esp_bt_pin_code_t array
+static esp_spp_sec_t _sec_mask;
+static esp_spp_role_t _role;
+// start connect on ESP_SPP_DISCOVERY_COMP_EVT or save entry for getChannels
+static bool _doConnect;
+static std::map<int, std::string> sdpRecords;
+
+static BTScanResultsSet scanResults;
+static BTAdvertisedDeviceCb advertisedDeviceCb = nullptr;
+
+// _spp_event_group
+#define SPP_RUNNING   0x01
+#define SPP_CONNECTED 0x02
+#define SPP_CONGESTED 0x04
+// true until OPEN successful, changes to false on CLOSE
 #define SPP_DISCONNECTED 0x08
+// true until connect(), changes to true on CLOSE
+#define SPP_CLOSED 0x10
+
+// _bt_event_group
+#define BT_DISCOVERY_RUNNING   0x01
+#define BT_DISCOVERY_COMPLETED 0x02
+
+#define BT_SDP_RUNNING   0x04
+#define BT_SDP_COMPLETED 0x08
 
 typedef struct {
-        size_t len;
-        uint8_t data[];
+  size_t len;
+  uint8_t data[];
 } spp_packet_t;
 
 #if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)
-static char *bda2str(esp_bd_addr_t bda, char *str, size_t size)
-{
+static char *bda2str(esp_bd_addr_t bda, char *str, size_t size) {
   if (bda == NULL || str == NULL || size < 18) {
     return NULL;
   }
 
   uint8_t *p = bda;
-  sprintf(str, "%02x:%02x:%02x:%02x:%02x:%02x",
-          p[0], p[1], p[2], p[3], p[4], p[5]);
+  snprintf(str, size, "%02x:%02x:%02x:%02x:%02x:%02x", p[0], p[1], p[2], p[3], p[4], p[5]);
   return str;
 }
 #endif
 
-static bool get_name_from_eir(uint8_t *eir, char *bdname, uint8_t *bdname_len)
-{
-    if (!eir || !bdname || !bdname_len) {
-        return false;
-    }
-
-    uint8_t *rmt_bdname, rmt_bdname_len;
-    *bdname = *bdname_len = rmt_bdname_len = 0;
-
-    rmt_bdname = esp_bt_gap_resolve_eir_data(eir, ESP_BT_EIR_TYPE_CMPL_LOCAL_NAME, &rmt_bdname_len);
-    if (!rmt_bdname) {
-        rmt_bdname = esp_bt_gap_resolve_eir_data(eir, ESP_BT_EIR_TYPE_SHORT_LOCAL_NAME, &rmt_bdname_len);
-    }
-    if (rmt_bdname) {
-        rmt_bdname_len = rmt_bdname_len > ESP_BT_GAP_MAX_BDNAME_LEN ? ESP_BT_GAP_MAX_BDNAME_LEN : rmt_bdname_len;
-        memcpy(bdname, rmt_bdname, rmt_bdname_len);
-        bdname[rmt_bdname_len] = 0;
-        *bdname_len = rmt_bdname_len;
-        return true;
-    }
+static bool get_name_from_eir(uint8_t *eir, char *bdname, uint8_t *bdname_len) {
+  if (!eir || !bdname || !bdname_len) {
     return false;
-}
+  }
 
-static bool btSetPin() {
-    esp_bt_pin_type_t pin_type;
-    if (_isPinSet) {
-        if (_pin_len) {
-            log_i("pin set");
-            pin_type = ESP_BT_PIN_TYPE_FIXED;
-        } else {
-            _isPinSet = false;
-            log_i("pin reset");
-            pin_type = ESP_BT_PIN_TYPE_VARIABLE; // pin_code would be ignored (default)
-        }
-        return (esp_bt_gap_set_pin(pin_type, _pin_len, _pin_code) == ESP_OK);        
-    }
-    return false;
+  uint8_t *rmt_bdname, rmt_bdname_len;
+  *bdname = *bdname_len = rmt_bdname_len = 0;
+
+  rmt_bdname = esp_bt_gap_resolve_eir_data(eir, ESP_BT_EIR_TYPE_CMPL_LOCAL_NAME, &rmt_bdname_len);
+  if (!rmt_bdname) {
+    rmt_bdname = esp_bt_gap_resolve_eir_data(eir, ESP_BT_EIR_TYPE_SHORT_LOCAL_NAME, &rmt_bdname_len);
+  }
+  if (rmt_bdname) {
+    rmt_bdname_len = rmt_bdname_len > ESP_BT_GAP_MAX_BDNAME_LEN ? ESP_BT_GAP_MAX_BDNAME_LEN : rmt_bdname_len;
+    memcpy(bdname, rmt_bdname, rmt_bdname_len);
+    bdname[rmt_bdname_len] = 0;
+    *bdname_len = rmt_bdname_len;
+    return true;
+  }
+  return false;
 }
 
-static esp_err_t _spp_queue_packet(uint8_t *data, size_t len){
-    if(!data || !len){
-        log_w("No data provided");
-        return ESP_OK;
-    }
-    spp_packet_t * packet = (spp_packet_t*)malloc(sizeof(spp_packet_t) + len);
-    if(!packet){
-        log_e("SPP TX Packet Malloc Failed!");
-        return ESP_FAIL;
-    }
-    packet->len = len;
-    memcpy(packet->data, data, len);
-    if (xQueueSend(_spp_tx_queue, &packet, portMAX_DELAY) != pdPASS) {
-        log_e("SPP TX Queue Send Failed!");
-        free(packet);
-        return ESP_FAIL;
-    }
+static esp_err_t _spp_queue_packet(uint8_t *data, size_t len) {
+  if (!data || !len) {
+    log_w("No data provided");
     return ESP_OK;
+  }
+  spp_packet_t *packet = (spp_packet_t *)malloc(sizeof(spp_packet_t) + len);
+  if (!packet) {
+    log_e("SPP TX Packet Malloc Failed!");
+    return ESP_FAIL;
+  }
+  packet->len = len;
+  memcpy(packet->data, data, len);
+  if (!_spp_tx_queue || xQueueSend(_spp_tx_queue, &packet, SPP_TX_QUEUE_TIMEOUT) != pdPASS) {
+    log_e("SPP TX Queue Send Failed!");
+    free(packet);
+    return ESP_FAIL;
+  }
+  return ESP_OK;
 }
 
 const uint16_t SPP_TX_MAX = 330;
 static uint8_t _spp_tx_buffer[SPP_TX_MAX];
 static uint16_t _spp_tx_buffer_len = 0;
 
-static bool _spp_send_buffer(){
-    if((xEventGroupWaitBits(_spp_event_group, SPP_CONGESTED, pdFALSE, pdTRUE, portMAX_DELAY) & SPP_CONGESTED) != 0){
-        esp_err_t err = esp_spp_write(_spp_client, _spp_tx_buffer_len, _spp_tx_buffer);
-        if(err != ESP_OK){
-            log_e("SPP Write Failed! [0x%X]", err);
-            return false;
-        }
-        _spp_tx_buffer_len = 0;
-        if(xSemaphoreTake(_spp_tx_done, portMAX_DELAY) != pdTRUE){
-            log_e("SPP Ack Failed!");
-            return false;
-        }
-        return true;
+static bool _spp_send_buffer() {
+  if ((xEventGroupWaitBits(_spp_event_group, SPP_CONGESTED, pdFALSE, pdTRUE, SPP_CONGESTED_TIMEOUT) & SPP_CONGESTED) != 0) {
+    if (!_spp_client) {
+      log_v("SPP Client Gone!");
+      return false;
     }
-    return false;
+    log_v("SPP Write %u", _spp_tx_buffer_len);
+    esp_err_t err = esp_spp_write(_spp_client, _spp_tx_buffer_len, _spp_tx_buffer);
+    if (err != ESP_OK) {
+      log_e("SPP Write Failed! [0x%X]", err);
+      return false;
+    }
+    _spp_tx_buffer_len = 0;
+    if (xSemaphoreTake(_spp_tx_done, SPP_TX_DONE_TIMEOUT) != pdTRUE) {
+      log_e("SPP Ack Failed!");
+      return false;
+    }
+    return true;
+  }
+  log_e("SPP Write Congested!");
+  return false;
 }
 
-static void _spp_tx_task(void * arg){
-    spp_packet_t *packet = NULL;
-    size_t len = 0, to_send = 0;
-    uint8_t * data = NULL;
-    for (;;) {
-        if(_spp_tx_queue && xQueueReceive(_spp_tx_queue, &packet, portMAX_DELAY) == pdTRUE && packet){
-            if(packet->len <= (SPP_TX_MAX - _spp_tx_buffer_len)){
-                memcpy(_spp_tx_buffer+_spp_tx_buffer_len, packet->data, packet->len);
-                _spp_tx_buffer_len+=packet->len;
-                free(packet);
-                packet = NULL;
-                if(SPP_TX_MAX == _spp_tx_buffer_len || uxQueueMessagesWaiting(_spp_tx_queue) == 0){
-                    _spp_send_buffer();
-                }
-            } else {
-                len = packet->len;
-                data = packet->data;
-                to_send = SPP_TX_MAX - _spp_tx_buffer_len;
-                memcpy(_spp_tx_buffer+_spp_tx_buffer_len, data, to_send);
-                _spp_tx_buffer_len = SPP_TX_MAX;
-                data += to_send;
-                len -= to_send;
-                _spp_send_buffer();
-                while(len >= SPP_TX_MAX){
-                    memcpy(_spp_tx_buffer, data, SPP_TX_MAX);
-                    _spp_tx_buffer_len = SPP_TX_MAX;
-                    data += SPP_TX_MAX;
-                    len -= SPP_TX_MAX;
-                    _spp_send_buffer();
-                }
-                if(len){
-                    memcpy(_spp_tx_buffer, data, len);
-                    _spp_tx_buffer_len += len;
-                    if(uxQueueMessagesWaiting(_spp_tx_queue) == 0){
-                        _spp_send_buffer();
-                    }
-                }
-                free(packet);
-                packet = NULL;
-            }
-        } else {
-            log_e("Something went horribly wrong");
+static void _spp_tx_task(void *arg) {
+  spp_packet_t *packet = NULL;
+  size_t len = 0, to_send = 0;
+  uint8_t *data = NULL;
+  for (;;) {
+    if (_spp_tx_queue && xQueueReceive(_spp_tx_queue, &packet, portMAX_DELAY) == pdTRUE && packet) {
+      if (packet->len <= (SPP_TX_MAX - _spp_tx_buffer_len)) {
+        memcpy(_spp_tx_buffer + _spp_tx_buffer_len, packet->data, packet->len);
+        _spp_tx_buffer_len += packet->len;
+        free(packet);
+        packet = NULL;
+        if (SPP_TX_MAX == _spp_tx_buffer_len || uxQueueMessagesWaiting(_spp_tx_queue) == 0) {
+          _spp_send_buffer();
+        }
+      } else {
+        len = packet->len;
+        data = packet->data;
+        to_send = SPP_TX_MAX - _spp_tx_buffer_len;
+        memcpy(_spp_tx_buffer + _spp_tx_buffer_len, data, to_send);
+        _spp_tx_buffer_len = SPP_TX_MAX;
+        data += to_send;
+        len -= to_send;
+        if (!_spp_send_buffer()) {
+          len = 0;
+        }
+        while (len >= SPP_TX_MAX) {
+          memcpy(_spp_tx_buffer, data, SPP_TX_MAX);
+          _spp_tx_buffer_len = SPP_TX_MAX;
+          data += SPP_TX_MAX;
+          len -= SPP_TX_MAX;
+          if (!_spp_send_buffer()) {
+            len = 0;
+            break;
+          }
+        }
+        if (len) {
+          memcpy(_spp_tx_buffer, data, len);
+          _spp_tx_buffer_len += len;
+          if (uxQueueMessagesWaiting(_spp_tx_queue) == 0) {
+            _spp_send_buffer();
+          }
         }
+        free(packet);
+        packet = NULL;
+      }
+    } else {
+      log_e("Something went horribly wrong");
     }
-    vTaskDelete(NULL);
-    _spp_task_handle = NULL;
+  }
+  vTaskDelete(NULL);
+  _spp_task_handle = NULL;
 }
 
-static void esp_spp_cb(esp_spp_cb_event_t event, esp_spp_cb_param_t *param)
-{
-    switch (event)
-    {
-    case ESP_SPP_INIT_EVT:
-        log_i("ESP_SPP_INIT_EVT");
-        esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE);
-        if (!_isMaster) {
-            log_i("ESP_SPP_INIT_EVT: slave: start");
-            esp_spp_start_srv(ESP_SPP_SEC_NONE, ESP_SPP_ROLE_SLAVE, 0, _spp_server_name);
+static void esp_spp_cb(esp_spp_cb_event_t event, esp_spp_cb_param_t *param) {
+  switch (event) {
+    case ESP_SPP_INIT_EVT:  // Enum 0 - When SPP is initialized
+      log_i("ESP_SPP_INIT_EVT");
+#ifdef ESP_IDF_VERSION_MAJOR
+      esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE);
+#else
+      esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE);
+#endif
+      log_i("ESP_SPP_INIT_EVT: %s: start", _isMaster ? "master" : "slave");
+      esp_spp_start_srv(ESP_SPP_SEC_NONE, _isMaster ? ESP_SPP_ROLE_MASTER : ESP_SPP_ROLE_SLAVE, 0, _spp_server_name);
+      xEventGroupSetBits(_spp_event_group, SPP_RUNNING);
+      break;
+
+    case ESP_SPP_UNINIT_EVT:  // Enum 1 - When SPP is deinitialized
+      log_i("ESP_SPP_UNINIT_EVT: SPP is deinitialized");
+      break;
+
+    case ESP_SPP_DISCOVERY_COMP_EVT:  // Enum 8 - When SDP discovery complete
+      log_i("ESP_SPP_DISCOVERY_COMP_EVT num=%d", param->disc_comp.scn_num);
+      if (param->disc_comp.status == ESP_SPP_SUCCESS) {
+        for (int i = 0; i < param->disc_comp.scn_num; i++) {
+          log_d("ESP_SPP_DISCOVERY_COMP_EVT: spp [%d] channel: %d service name:%s", i, param->disc_comp.scn[i], param->disc_comp.service_name[0]);
         }
-        xEventGroupSetBits(_spp_event_group, SPP_RUNNING);
-        break;
-
-    case ESP_SPP_SRV_OPEN_EVT://Server connection open
-        log_i("ESP_SPP_SRV_OPEN_EVT");
-        if (!_spp_client){
-            _spp_client = param->open.handle;
+        if (_doConnect) {
+          if (param->disc_comp.scn_num > 0) {
+#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)
+            char bda_str[18];
+            log_i("ESP_SPP_DISCOVERY_COMP_EVT: spp connect to remote %s channel %d", bda2str(_peer_bd_addr, bda_str, sizeof(bda_str)), param->disc_comp.scn[0]);
+#endif
+            xEventGroupClearBits(_spp_event_group, SPP_CLOSED);
+            if (esp_spp_connect(_sec_mask, _role, param->disc_comp.scn[0], _peer_bd_addr) != ESP_OK) {
+              log_e("ESP_SPP_DISCOVERY_COMP_EVT connect failed");
+              xEventGroupSetBits(_spp_event_group, SPP_CLOSED);
+            }
+          } else {
+            log_e("ESP_SPP_DISCOVERY_COMP_EVT remote doesn't offer an SPP channel");
+            xEventGroupSetBits(_spp_event_group, SPP_CLOSED);
+          }
         } else {
-            secondConnectionAttempt = true;
-            esp_spp_disconnect(param->open.handle);
+          for (int i = 0; i < param->disc_comp.scn_num; i++) {
+            sdpRecords[param->disc_comp.scn[i]] = param->disc_comp.service_name[0];
+          }
         }
-        xEventGroupClearBits(_spp_event_group, SPP_DISCONNECTED);
-        xEventGroupSetBits(_spp_event_group, SPP_CONNECTED);
-        break;
-
-    case ESP_SPP_CLOSE_EVT://Client connection closed
-        log_i("ESP_SPP_CLOSE_EVT");
-        if(secondConnectionAttempt) {
-            secondConnectionAttempt = false;
-        } else {
-            _spp_client = 0;
-            xEventGroupSetBits(_spp_event_group, SPP_DISCONNECTED);
-        }        
-        xEventGroupClearBits(_spp_event_group, SPP_CONNECTED);
-        break;
-
-    case ESP_SPP_CONG_EVT://connection congestion status changed
-        if(param->cong.cong){
-            xEventGroupClearBits(_spp_event_group, SPP_CONGESTED);
+      } else {
+        log_e("ESP_SPP_DISCOVERY_COMP_EVT failed!, status:%d", param->disc_comp.status);
+      }
+      xEventGroupSetBits(_bt_event_group, BT_SDP_COMPLETED);
+      break;
+
+    case ESP_SPP_OPEN_EVT:  // Enum 26 - When SPP Client connection open
+      log_i("ESP_SPP_OPEN_EVT");
+      if (!_spp_client) {
+        _spp_client = param->open.handle;
+      } else {
+        secondConnectionAttempt = true;
+        esp_spp_disconnect(param->open.handle);
+      }
+      xEventGroupClearBits(_spp_event_group, SPP_DISCONNECTED);
+      xEventGroupSetBits(_spp_event_group, SPP_CONNECTED);
+      xEventGroupSetBits(_spp_event_group, SPP_CONGESTED);
+      break;
+
+    case ESP_SPP_CLOSE_EVT:  // Enum 27 - When SPP connection closed
+      if ((param->close.async == false && param->close.status == ESP_SPP_SUCCESS) || param->close.async) {
+        log_i(
+          "ESP_SPP_CLOSE_EVT status:%d handle:%d close_by_remote:%d attempt %u", param->close.status, param->close.handle, param->close.async,
+          secondConnectionAttempt
+        );
+        if (secondConnectionAttempt) {
+          secondConnectionAttempt = false;
         } else {
-            xEventGroupSetBits(_spp_event_group, SPP_CONGESTED);
+          _spp_client = 0;
+          xEventGroupSetBits(_spp_event_group, SPP_DISCONNECTED);
+          xEventGroupSetBits(_spp_event_group, SPP_CONGESTED);
+          xEventGroupSetBits(_spp_event_group, SPP_CLOSED);
+          xEventGroupClearBits(_spp_event_group, SPP_CONNECTED);
         }
-        log_v("ESP_SPP_CONG_EVT: %s", param->cong.cong?"CONGESTED":"FREE");
-        break;
-
-    case ESP_SPP_WRITE_EVT://write operation completed
-        if(param->write.cong){
-            xEventGroupClearBits(_spp_event_group, SPP_CONGESTED);
-        }
-        xSemaphoreGive(_spp_tx_done);//we can try to send another packet
-        log_v("ESP_SPP_WRITE_EVT: %u %s", param->write.len, param->write.cong?"CONGESTED":"FREE");
-        break;
-
-    case ESP_SPP_DATA_IND_EVT://connection received data
-        log_v("ESP_SPP_DATA_IND_EVT len=%d handle=%d", param->data_ind.len, param->data_ind.handle);
-        //esp_log_buffer_hex("",param->data_ind.data,param->data_ind.len); //for low level debug
-        //ets_printf("r:%u\n", param->data_ind.len);
-
-        if(custom_data_callback){
-            custom_data_callback(param->data_ind.data, param->data_ind.len);
-        } else if (_spp_rx_queue != NULL){
-            for (int i = 0; i < param->data_ind.len; i++){
-                if(xQueueSend(_spp_rx_queue, param->data_ind.data + i, (TickType_t)0) != pdTRUE){
-                    log_e("RX Full! Discarding %u bytes", param->data_ind.len - i);
-                    break;
-                }
-            }
+      } else {
+        log_e("ESP_SPP_CLOSE_EVT failed!, status:%d", param->close.status);
+      }
+      break;
+
+    case ESP_SPP_START_EVT:  // Enum 28 - When SPP server started
+      log_i("ESP_SPP_START_EVT");
+      break;
+
+    case ESP_SPP_CL_INIT_EVT:  // Enum 29 - When SPP client initiated a connection
+      if (param->cl_init.status == ESP_SPP_SUCCESS) {
+        log_i("ESP_SPP_CL_INIT_EVT handle:%d sec_id:%d", param->cl_init.handle, param->cl_init.sec_id);
+      } else {
+        log_i("ESP_SPP_CL_INIT_EVT status:%d", param->cl_init.status);
+      }
+      break;
+
+    case ESP_SPP_DATA_IND_EVT:  // Enum 30 - When SPP connection received data, only for ESP_SPP_MODE_CB
+      log_v("ESP_SPP_DATA_IND_EVT len=%d handle=%d", param->data_ind.len, param->data_ind.handle);
+      //esp_log_buffer_hex("",param->data_ind.data,param->data_ind.len); //for low level debug
+      //ets_printf("r:%u\n", param->data_ind.len);
+
+      if (custom_data_callback) {
+        custom_data_callback(param->data_ind.data, param->data_ind.len);
+      } else if (_spp_rx_queue != NULL) {
+        for (int i = 0; i < param->data_ind.len; i++) {
+          if (xQueueSend(_spp_rx_queue, param->data_ind.data + i, (TickType_t)0) != pdTRUE) {
+            log_e("RX Full! Discarding %u bytes", param->data_ind.len - i);
+            break;
+          }
         }
-        break;
+      }
+      break;
 
-    case ESP_SPP_DISCOVERY_COMP_EVT://discovery complete
-        log_i("ESP_SPP_DISCOVERY_COMP_EVT");
-        if (param->disc_comp.status == ESP_SPP_SUCCESS) {
-            log_i("ESP_SPP_DISCOVERY_COMP_EVT: spp connect to remote");
-            esp_spp_connect(ESP_SPP_SEC_AUTHENTICATE, ESP_SPP_ROLE_MASTER, param->disc_comp.scn[0], _peer_bd_addr);
+    case ESP_SPP_CONG_EVT:  // Enum 31 - When SPP connection congestion status changed, only for ESP_SPP_MODE_CB
+      if (param->cong.cong) {
+        xEventGroupClearBits(_spp_event_group, SPP_CONGESTED);
+      } else {
+        xEventGroupSetBits(_spp_event_group, SPP_CONGESTED);
+      }
+      log_v("ESP_SPP_CONG_EVT: %s", param->cong.cong ? "CONGESTED" : "FREE");
+      break;
+
+    case ESP_SPP_WRITE_EVT:  // Enum 33 - When SPP write operation completes, only for ESP_SPP_MODE_CB
+      if (param->write.status == ESP_SPP_SUCCESS) {
+        if (param->write.cong) {
+          xEventGroupClearBits(_spp_event_group, SPP_CONGESTED);
         }
-        break;
-
-    case ESP_SPP_OPEN_EVT://Client connection open
-        log_i("ESP_SPP_OPEN_EVT");
-        if (!_spp_client){
-                _spp_client = param->open.handle;
+        log_v("ESP_SPP_WRITE_EVT: %u %s", param->write.len, param->write.cong ? "CONGESTED" : "");
+      } else {
+        log_e("ESP_SPP_WRITE_EVT failed!, status:%d", param->write.status);
+      }
+      xSemaphoreGive(_spp_tx_done);  //we can try to send another packet
+      break;
+
+    case ESP_SPP_SRV_OPEN_EVT:  // Enum 34 - When SPP Server connection open
+      if (param->srv_open.status == ESP_SPP_SUCCESS) {
+        log_i("ESP_SPP_SRV_OPEN_EVT: %u", _spp_client);
+        if (!_spp_client) {
+          _spp_client = param->srv_open.handle;
+          _spp_tx_buffer_len = 0;
         } else {
-            secondConnectionAttempt = true;
-            esp_spp_disconnect(param->open.handle);
+          secondConnectionAttempt = true;
+          esp_spp_disconnect(param->srv_open.handle);
         }
         xEventGroupClearBits(_spp_event_group, SPP_DISCONNECTED);
         xEventGroupSetBits(_spp_event_group, SPP_CONNECTED);
-        break;
+      } else {
+        log_e("ESP_SPP_SRV_OPEN_EVT Failed!, status:%d", param->srv_open.status);
+      }
+      break;
 
-    case ESP_SPP_START_EVT://server started
-        log_i("ESP_SPP_START_EVT");
-        break;
+    case ESP_SPP_SRV_STOP_EVT:  // Enum 35 - When SPP server stopped
+      log_i("ESP_SPP_SRV_STOP_EVT");
+      break;
 
-    case ESP_SPP_CL_INIT_EVT://client initiated a connection
-        log_i("ESP_SPP_CL_INIT_EVT");
-        break;
+    case ESP_SPP_VFS_REGISTER_EVT:  // Enum 36 - When SPP VFS register
+      log_i("ESP_SPP_VFS_REGISTER_EVT");
+      break;
 
-    default:
-        break;
-    }
-    if(custom_spp_callback)(*custom_spp_callback)(event, param);
+    case ESP_SPP_VFS_UNREGISTER_EVT:  // Enum 37 - When SPP VFS unregister
+      log_i("ESP_SPP_VFS_UNREGISTER_EVT");
+      break;
+
+    default: log_i("ESP_SPP_* event #%d unhandled", event); break;
+  }
+  if (custom_spp_callback) {
+    (*custom_spp_callback)(event, param);
+  }
 }
 
-void BluetoothSerial::onData(BluetoothSerialDataCb cb){
-    custom_data_callback = cb;
+void BluetoothSerial::onData(BluetoothSerialDataCb cb) {
+  custom_data_callback = cb;
 }
 
-static void esp_bt_gap_cb(esp_bt_gap_cb_event_t event, esp_bt_gap_cb_param_t *param)
-{
-    switch(event){
-        case ESP_BT_GAP_DISC_RES_EVT:
-            log_i("ESP_BT_GAP_DISC_RES_EVT");
+static void esp_bt_gap_cb(esp_bt_gap_cb_event_t event, esp_bt_gap_cb_param_t *param) {
+  switch (event) {
+    case ESP_BT_GAP_DISC_RES_EVT:
+    {  // Enum 0 - Device discovery result event
+      log_i("ESP_BT_GAP_DISC_RES_EVT properties=%d", param->disc_res.num_prop);
 #if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)
-            char bda_str[18];
-            log_i("Scanned device: %s", bda2str(param->disc_res.bda, bda_str, 18));
+      char bda_str[18];
+      log_i("Scanned device: %s", bda2str(param->disc_res.bda, bda_str, 18));
 #endif
-            for (int i = 0; i < param->disc_res.num_prop; i++) {
-                uint8_t peer_bdname_len;
-                char peer_bdname[ESP_BT_GAP_MAX_BDNAME_LEN + 1];
-                switch(param->disc_res.prop[i].type) {
-                    case ESP_BT_GAP_DEV_PROP_EIR:  
-                        if (get_name_from_eir((uint8_t*)param->disc_res.prop[i].val, peer_bdname, &peer_bdname_len)) {
-                            log_i("ESP_BT_GAP_DISC_RES_EVT : EIR : %s : %d", peer_bdname, peer_bdname_len);
-                            if (strlen(_remote_name) == peer_bdname_len
-                                && strncmp(peer_bdname, _remote_name, peer_bdname_len) == 0) {
-                                log_v("ESP_BT_GAP_DISC_RES_EVT : SPP_START_DISCOVERY_EIR : %s", peer_bdname, peer_bdname_len);
-                                _isRemoteAddressSet = true;
-                                memcpy(_peer_bd_addr, param->disc_res.bda, ESP_BD_ADDR_LEN);
-                                esp_bt_gap_cancel_discovery();
-                                esp_spp_start_discovery(_peer_bd_addr);
-                            }
-                        }
-                        break;
-
-                    case ESP_BT_GAP_DEV_PROP_BDNAME:
-                        peer_bdname_len = param->disc_res.prop[i].len;
-                        memcpy(peer_bdname, param->disc_res.prop[i].val, peer_bdname_len);
-                        peer_bdname_len--; // len includes 0 terminator
-                        log_v("ESP_BT_GAP_DISC_RES_EVT : BDNAME :  %s : %d", peer_bdname, peer_bdname_len);
-                        if (strlen(_remote_name) == peer_bdname_len
-                            && strncmp(peer_bdname, _remote_name, peer_bdname_len) == 0) {
-                            log_i("ESP_BT_GAP_DISC_RES_EVT : SPP_START_DISCOVERY_BDNAME : %s", peer_bdname);
-                            _isRemoteAddressSet = true;
-                            memcpy(_peer_bd_addr, param->disc_res.bda, ESP_BD_ADDR_LEN);
-                            esp_bt_gap_cancel_discovery();
-                            esp_spp_start_discovery(_peer_bd_addr);
-                        } 
-                        break;
-
-                    case ESP_BT_GAP_DEV_PROP_COD:
-                        log_d("ESP_BT_GAP_DEV_PROP_COD");
-                        break;
-
-                    case ESP_BT_GAP_DEV_PROP_RSSI:
-                        log_d("ESP_BT_GAP_DEV_PROP_RSSI");
-                        break;
-                        
-                    default:
-                        break;
-                }
-                if (_isRemoteAddressSet)
-                    break;
+      BTAdvertisedDeviceSet advertisedDevice;
+      uint8_t peer_bdname_len = 0;
+      char peer_bdname[ESP_BT_GAP_MAX_BDNAME_LEN + 1];
+      for (int i = 0; i < param->disc_res.num_prop; i++) {
+        switch (param->disc_res.prop[i].type) {
+          case ESP_BT_GAP_DEV_PROP_BDNAME:  // Enum 1 - Bluetooth device name, value type is int8_t []
+            peer_bdname_len = param->disc_res.prop[i].len;
+            memcpy(peer_bdname, param->disc_res.prop[i].val, peer_bdname_len);
+            peer_bdname_len--;  // len includes 0 terminator
+            log_v("ESP_BT_GAP_DISC_RES_EVT : BDNAME :  %s : %d", peer_bdname, peer_bdname_len);
+            if (strlen(_remote_name) == peer_bdname_len && strncmp(peer_bdname, _remote_name, peer_bdname_len) == 0) {
+              log_i("ESP_BT_GAP_DISC_RES_EVT : SPP_START_DISCOVERY_BDNAME : %s", peer_bdname);
+              _isRemoteAddressSet = true;
+              memcpy(_peer_bd_addr, param->disc_res.bda, ESP_BD_ADDR_LEN);
+              esp_bt_gap_cancel_discovery();
+              esp_spp_start_discovery(_peer_bd_addr);
             }
             break;
-        case ESP_BT_GAP_DISC_STATE_CHANGED_EVT:
-            log_i("ESP_BT_GAP_DISC_STATE_CHANGED_EVT");
-            break;
-
-        case ESP_BT_GAP_RMT_SRVCS_EVT:
-            log_i( "ESP_BT_GAP_RMT_SRVCS_EVT");
-            break;
-
-        case ESP_BT_GAP_RMT_SRVC_REC_EVT:
-            log_i("ESP_BT_GAP_RMT_SRVC_REC_EVT");
-            break;
 
-        case ESP_BT_GAP_AUTH_CMPL_EVT:
-            if (param->auth_cmpl.stat == ESP_BT_STATUS_SUCCESS) {
-                log_v("authentication success: %s", param->auth_cmpl.device_name);
+          case ESP_BT_GAP_DEV_PROP_COD:  // Enum 2 - Class of Device, value type is uint32_t
+            if (param->disc_res.prop[i].len <= sizeof(int)) {
+              uint32_t cod = 0;
+              memcpy(&cod, param->disc_res.prop[i].val, param->disc_res.prop[i].len);
+              advertisedDevice.setCOD(cod);
+              log_d("ESP_BT_GAP_DEV_PROP_COD 0x%x", cod);
             } else {
-                log_e("authentication failed, status:%d", param->auth_cmpl.stat);
+              log_d("ESP_BT_GAP_DEV_PROP_COD invalid COD: Value size larger than integer");
             }
             break;
 
-        case ESP_BT_GAP_PIN_REQ_EVT:
-            // default pairing pins
-            log_i("ESP_BT_GAP_PIN_REQ_EVT min_16_digit:%d", param->pin_req.min_16_digit);
-            if (param->pin_req.min_16_digit) {
-                log_i("Input pin code: 0000 0000 0000 0000");
-                esp_bt_pin_code_t pin_code;
-                memset(pin_code, '0', ESP_BT_PIN_CODE_LEN);
-                esp_bt_gap_pin_reply(param->pin_req.bda, true, 16, pin_code);
+          case ESP_BT_GAP_DEV_PROP_RSSI:  // Enum 3 - Received Signal strength Indication, value type is int8_t, ranging from -128 to 127
+            if (param->disc_res.prop[i].len <= sizeof(int)) {
+              uint8_t rssi = 0;
+              memcpy(&rssi, param->disc_res.prop[i].val, param->disc_res.prop[i].len);
+              log_d("ESP_BT_GAP_DEV_PROP_RSSI %d", rssi);
+              advertisedDevice.setRSSI(rssi);
             } else {
-                log_i("Input pin code: 1234");
-                esp_bt_pin_code_t pin_code;
-                memcpy(pin_code, "1234", 4);
-                esp_bt_gap_pin_reply(param->pin_req.bda, true, 4, pin_code);
+              log_d("ESP_BT_GAP_DEV_PROP_RSSI invalid RSSI: Value size larger than integer");
             }
             break;
-       
-        case ESP_BT_GAP_CFM_REQ_EVT:
-            log_i("ESP_BT_GAP_CFM_REQ_EVT Please compare the numeric value: %d", param->cfm_req.num_val);
-            esp_bt_gap_ssp_confirm_reply(param->cfm_req.bda, true);
-            break;
-
-        case ESP_BT_GAP_KEY_NOTIF_EVT:
-            log_i("ESP_BT_GAP_KEY_NOTIF_EVT passkey:%d", param->key_notif.passkey);
-            break;
-
-        case ESP_BT_GAP_KEY_REQ_EVT:
-            log_i("ESP_BT_GAP_KEY_REQ_EVT Please enter passkey!");
-            break;
 
-        default:
+          case ESP_BT_GAP_DEV_PROP_EIR:  // Enum 4 - Extended Inquiry Response, value type is uint8_t []
+            if (get_name_from_eir((uint8_t *)param->disc_res.prop[i].val, peer_bdname, &peer_bdname_len)) {
+              log_i("ESP_BT_GAP_DISC_RES_EVT : EIR : %s : %d", peer_bdname, peer_bdname_len);
+              if (strlen(_remote_name) == peer_bdname_len && strncmp(peer_bdname, _remote_name, peer_bdname_len) == 0) {
+                log_v("ESP_BT_GAP_DISC_RES_EVT : SPP_START_DISCOVERY_EIR : %s", peer_bdname, peer_bdname_len);
+                _isRemoteAddressSet = true;
+                memcpy(_peer_bd_addr, param->disc_res.bda, ESP_BD_ADDR_LEN);
+                esp_bt_gap_cancel_discovery();
+                esp_spp_start_discovery(_peer_bd_addr);
+              }
+            }
             break;
-    }
-}
 
-static bool _init_bt(const char *deviceName)
-{
-    if(!_spp_event_group){
-        _spp_event_group = xEventGroupCreate();
-        if(!_spp_event_group){
-            log_e("SPP Event Group Create Failed!");
-            return false;
+          default: log_i("ESP_BT_GAP_DISC_RES_EVT unknown property [%d]:type:%d", i, param->disc_res.prop[i].type); break;
         }
-        xEventGroupClearBits(_spp_event_group, 0xFFFFFF);
-        xEventGroupSetBits(_spp_event_group, SPP_CONGESTED);
-        xEventGroupSetBits(_spp_event_group, SPP_DISCONNECTED);
-    }
-    if (_spp_rx_queue == NULL){
-        _spp_rx_queue = xQueueCreate(RX_QUEUE_SIZE, sizeof(uint8_t)); //initialize the queue
-        if (_spp_rx_queue == NULL){
-            log_e("RX Queue Create Failed");
-            return false;
+        if (_isRemoteAddressSet) {
+          break;
         }
-    }
-    if (_spp_tx_queue == NULL){
-        _spp_tx_queue = xQueueCreate(TX_QUEUE_SIZE, sizeof(spp_packet_t*)); //initialize the queue
-        if (_spp_tx_queue == NULL){
-            log_e("TX Queue Create Failed");
-            return false;
+      }
+      if (peer_bdname_len) {
+        advertisedDevice.setName(peer_bdname);
+      }
+      esp_bd_addr_t addr;
+      memcpy(addr, param->disc_res.bda, ESP_BD_ADDR_LEN);
+      advertisedDevice.setAddress(BTAddress(addr));
+      if (scanResults.add(advertisedDevice) && advertisedDeviceCb) {
+        advertisedDeviceCb(&advertisedDevice);
+      }
+    } break;
+
+    case ESP_BT_GAP_DISC_STATE_CHANGED_EVT:  // Enum 1 - Discovery state changed event
+      if (param->disc_st_chg.state == ESP_BT_GAP_DISCOVERY_STOPPED) {
+        log_i("ESP_BT_GAP_DISC_STATE_CHANGED_EVT stopped");
+        xEventGroupClearBits(_bt_event_group, BT_DISCOVERY_RUNNING);
+        xEventGroupSetBits(_bt_event_group, BT_DISCOVERY_COMPLETED);
+      } else {  // ESP_BT_GAP_DISCOVERY_STARTED
+        log_i("ESP_BT_GAP_DISC_STATE_CHANGED_EVT started");
+        xEventGroupClearBits(_bt_event_group, BT_DISCOVERY_COMPLETED);
+        xEventGroupSetBits(_bt_event_group, BT_DISCOVERY_RUNNING);
+      }
+      break;
+
+    case ESP_BT_GAP_RMT_SRVCS_EVT:  // Enum 2 - Get remote services event
+      log_i("ESP_BT_GAP_RMT_SRVCS_EVT: status = %d, num_uuids = %d", param->rmt_srvcs.stat, param->rmt_srvcs.num_uuids);
+      break;
+
+    case ESP_BT_GAP_RMT_SRVC_REC_EVT:  // Enum 3 - Get remote service record event
+      log_i("ESP_BT_GAP_RMT_SRVC_REC_EVT: status = %d", param->rmt_srvc_rec.stat);
+      break;
+
+    case ESP_BT_GAP_AUTH_CMPL_EVT:  // Enum 4 - Authentication complete event
+      if (param->auth_cmpl.stat == ESP_BT_STATUS_SUCCESS) {
+        log_v("authentication success: %s", param->auth_cmpl.device_name);
+        if (auth_complete_callback) {
+          auth_complete_callback(true);
         }
-    }
-    if(_spp_tx_done == NULL){
-        _spp_tx_done = xSemaphoreCreateBinary();
-        if (_spp_tx_done == NULL){
-            log_e("TX Semaphore Create Failed");
-            return false;
+      } else {
+        log_e("authentication failed, status:%d", param->auth_cmpl.stat);
+        if (auth_complete_callback) {
+          auth_complete_callback(false);
         }
-        xSemaphoreTake(_spp_tx_done, 0);
-    }
+      }
+      break;
+    case ESP_BT_GAP_PIN_REQ_EVT:  // Enum 5 - Legacy Pairing Pin code request
+      log_i("ESP_BT_GAP_PIN_REQ_EVT (min_16_digit=%d)", param->pin_req.min_16_digit);
+      if (param->pin_req.min_16_digit && _pin_code_len < 16) {
+        esp_bt_gap_pin_reply(param->pin_req.bda, false, 0, NULL);
+      } else {
+        //log_i("Input pin code: \"%s\"=0x%x", _pin_code);
+        log_i("Input pin code: \"%.*s\"=0x%x", _pin_code_len, _pin_code, *(int *)_pin_code);
+        esp_bt_gap_pin_reply(param->pin_req.bda, true, _pin_code_len, _pin_code);
+      }
+      break;
+    case ESP_BT_GAP_CFM_REQ_EVT:  // Enum 6 - Security Simple Pairing User Confirmation request.
+      log_i("ESP_BT_GAP_CFM_REQ_EVT Please compare the numeric value: %d", param->cfm_req.num_val);
+      if (confirm_request_callback) {
+        memcpy(current_bd_addr, param->cfm_req.bda, sizeof(esp_bd_addr_t));
+        confirm_request_callback(param->cfm_req.num_val);
+      } else {
+        log_w("ESP_BT_GAP_CFM_REQ_EVT: confirm_request_callback does not exist - refusing pairing");
+        esp_bt_gap_ssp_confirm_reply(param->cfm_req.bda, false);
+      }
+      break;
+
+    case ESP_BT_GAP_KEY_NOTIF_EVT:  // Enum 7 - Security Simple Pairing Passkey Notification
+      log_i("ESP_BT_GAP_KEY_NOTIF_EVT passkey:%d", param->key_notif.passkey);
+      break;
+    case ESP_BT_GAP_KEY_REQ_EVT:  // Enum 8 - Security Simple Pairing Passkey request
+      log_i("ESP_BT_GAP_KEY_REQ_EVT Please enter passkey!");
+      if (key_request_callback) {
+        memcpy(current_bd_addr, param->cfm_req.bda, sizeof(esp_bd_addr_t));
+        key_request_callback();
+      } else {
+        log_w("ESP_BT_GAP_KEY_REQ_EVT: key_request_callback does not exist - refuseing pairing");
+        esp_bt_gap_ssp_confirm_reply(param->cfm_req.bda, false);
+      }
+      break;
+
+    case ESP_BT_GAP_READ_RSSI_DELTA_EVT:  // Enum 9 - Read rssi event
+      log_i("ESP_BT_GAP_READ_RSSI_DELTA_EVT Read rssi event");
+      break;
+    case ESP_BT_GAP_CONFIG_EIR_DATA_EVT:  // Enum 10 - Config EIR data event
+      log_i("ESP_BT_GAP_CONFIG_EIR_DATA_EVT: stat:%d num:%d", param->config_eir_data.stat, param->config_eir_data.eir_type_num);
+      break;
+
+    case ESP_BT_GAP_SET_AFH_CHANNELS_EVT:  // Enum 11 - Set AFH channels event
+      log_i("ESP_BT_GAP_SET_AFH_CHANNELS_EVT Set AFH channels event");
+      break;
+
+    case ESP_BT_GAP_READ_REMOTE_NAME_EVT:  // Enum 12 - Read Remote Name event
+      if (param->read_rmt_name.stat == ESP_BT_STATUS_SUCCESS) {
+        log_i("ESP_BT_GAP_READ_REMOTE_NAME_EVT: %s", param->read_rmt_name.rmt_name);
+        memcpy(_rmt_name, param->read_rmt_name.rmt_name, ESP_BT_GAP_MAX_BDNAME_LEN + 1);
+        _rmt_name_valid = true;
+      } else {
+        log_i("ESP_BT_GAP_READ_REMOTE_NAME_EVT: no success stat:%d", param->read_rmt_name.stat);
+      }
+      break;
+
+    case ESP_BT_GAP_MODE_CHG_EVT:  // Enum 13
+      log_i("ESP_BT_GAP_MODE_CHG_EVT: mode: %d", param->mode_chg.mode);
+      break;
+
+    case ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT:  // Enum - 14 remove bond device complete event
+      log_i("ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT remove bond device complete event");
+      break;
+
+    case ESP_BT_GAP_QOS_CMPL_EVT:  // Enum 15 - QOS complete event
+      log_i("ESP_BT_GAP_QOS_CMPL_EVT QOS complete event");
+      break;
+
+    case ESP_BT_GAP_ACL_CONN_CMPL_STAT_EVT:  // Enum 16 - ACL connection complete status event
+      log_i("ESP_BT_GAP_ACL_CONN_CMPL_STAT_EVT ACL connection complete status event");
+      break;
+
+    case ESP_BT_GAP_ACL_DISCONN_CMPL_STAT_EVT:  // Enum 17 - ACL disconnection complete status event
+      log_i(
+        "ESP_BT_GAP_ACL_DISCONN_CMPL_STAT_EVT ACL disconnection complete status event: reason %d, handle %d", param->acl_disconn_cmpl_stat.reason,
+        param->acl_disconn_cmpl_stat.handle
+      );
+      break;
+
+    default: log_i("ESP-BT_GAP_* unknown message: %d", event); break;
+  }
+}
 
-    if(!_spp_task_handle){
-        xTaskCreatePinnedToCore(_spp_tx_task, "spp_tx", 4096, NULL, 2, &_spp_task_handle, 0);
-        if(!_spp_task_handle){
-            log_e("Network Event Task Start Failed!");
-            return false;
-        }
+static bool _init_bt(const char *deviceName, bt_mode mode) {
+  if (!_bt_event_group) {
+    _bt_event_group = xEventGroupCreate();
+    if (!_bt_event_group) {
+      log_e("BT Event Group Create Failed!");
+      return false;
     }
-
-    if (!btStarted() && !btStart()){
-        log_e("initialize controller failed");
-        return false;
+    xEventGroupClearBits(_bt_event_group, 0xFFFFFF);
+  }
+  if (!_spp_event_group) {
+    _spp_event_group = xEventGroupCreate();
+    if (!_spp_event_group) {
+      log_e("SPP Event Group Create Failed!");
+      return false;
     }
-    
-    esp_bluedroid_status_t bt_state = esp_bluedroid_get_status();
-    if (bt_state == ESP_BLUEDROID_STATUS_UNINITIALIZED){
-        if (esp_bluedroid_init()) {
-            log_e("initialize bluedroid failed");
-            return false;
-        }
+    xEventGroupClearBits(_spp_event_group, 0xFFFFFF);
+    xEventGroupSetBits(_spp_event_group, SPP_CONGESTED);
+    xEventGroupSetBits(_spp_event_group, SPP_DISCONNECTED);
+    xEventGroupSetBits(_spp_event_group, SPP_CLOSED);
+  }
+  if (_spp_rx_queue == NULL) {
+    _spp_rx_queue = xQueueCreate(RX_QUEUE_SIZE, sizeof(uint8_t));  //initialize the queue
+    if (_spp_rx_queue == NULL) {
+      log_e("RX Queue Create Failed");
+      return false;
     }
-    
-    if (bt_state != ESP_BLUEDROID_STATUS_ENABLED){
-        if (esp_bluedroid_enable()) {
-            log_e("enable bluedroid failed");
-            return false;
-        }
+  }
+  if (_spp_tx_queue == NULL) {
+    _spp_tx_queue = xQueueCreate(TX_QUEUE_SIZE, sizeof(spp_packet_t *));  //initialize the queue
+    if (_spp_tx_queue == NULL) {
+      log_e("TX Queue Create Failed");
+      return false;
     }
-
-    if (_isMaster && esp_bt_gap_register_callback(esp_bt_gap_cb) != ESP_OK) {
-        log_e("gap register failed");
-        return false;
+  }
+  if (_spp_tx_done == NULL) {
+    _spp_tx_done = xSemaphoreCreateBinary();
+    if (_spp_tx_done == NULL) {
+      log_e("TX Semaphore Create Failed");
+      return false;
     }
+    xSemaphoreTake(_spp_tx_done, 0);
+  }
 
-    if (esp_spp_register_callback(esp_spp_cb) != ESP_OK){
-        log_e("spp register failed");
-        return false;
+  if (!_spp_task_handle) {
+    xTaskCreatePinnedToCore(_spp_tx_task, "spp_tx", 4096, NULL, configMAX_PRIORITIES - 1, &_spp_task_handle, 0);
+    if (!_spp_task_handle) {
+      log_e("Network Event Task Start Failed!");
+      return false;
     }
+  }
+
+  if (!btStarted() && !btStartMode(mode)) {
+    log_e("initialize controller failed");
+    return false;
+  }
 
-    if (esp_spp_init(ESP_SPP_MODE_CB) != ESP_OK){
-        log_e("spp init failed");
-        return false;
+  esp_bluedroid_status_t bt_state = esp_bluedroid_get_status();
+  if (bt_state == ESP_BLUEDROID_STATUS_UNINITIALIZED) {
+    if (esp_bluedroid_init()) {
+      log_e("initialize bluedroid failed");
+      return false;
     }
+  }
 
-    if (esp_bt_sleep_disable() != ESP_OK){
-        log_e("esp_bt_sleep_disable failed");
+  if (bt_state != ESP_BLUEDROID_STATUS_ENABLED) {
+    if (esp_bluedroid_enable()) {
+      log_e("enable bluedroid failed");
+      return false;
     }
+  }
 
-    log_i("device name set");
-    esp_bt_dev_set_device_name(deviceName);
+  if (esp_bt_gap_register_callback(esp_bt_gap_cb) != ESP_OK) {
+    log_e("gap register failed");
+    return false;
+  }
 
-    if (_isPinSet) {
-        btSetPin();
-    }
+  if (esp_spp_register_callback(esp_spp_cb) != ESP_OK) {
+    log_e("spp register failed");
+    return false;
+  }
 
-    if (_enableSSP) {
-        log_i("Simple Secure Pairing");
-        esp_bt_sp_param_t param_type = ESP_BT_SP_IOCAP_MODE;
-        esp_bt_io_cap_t iocap = ESP_BT_IO_CAP_IO;
-        esp_bt_gap_set_security_param(param_type, &iocap, sizeof(uint8_t));
-    }
+  esp_spp_cfg_t cfg = BT_SPP_DEFAULT_CONFIG();
+  cfg.mode = ESP_SPP_MODE_CB;
+  if (esp_spp_enhanced_init(&cfg) != ESP_OK) {
+    log_e("spp init failed");
+    return false;
+  }
 
-    // the default BTA_DM_COD_LOUDSPEAKER does not work with the macOS BT stack
-    esp_bt_cod_t cod;
-    cod.major = 0b00001;
-    cod.minor = 0b000100;
-    cod.service = 0b00000010110;
-    if (esp_bt_gap_set_cod(cod, ESP_BT_INIT_COD) != ESP_OK) {
-        log_e("set cod failed");
-        return false;
+  log_i("device name set");
+  esp_bt_gap_set_device_name(deviceName);
+
+  if (_enableSSP) {
+    log_i("Simple Secure Pairing");
+    esp_bt_sp_param_t param_type = ESP_BT_SP_IOCAP_MODE;
+    esp_bt_io_cap_t iocap;
+    if (_IO_CAP_INPUT && _IO_CAP_OUTPUT) {
+      iocap = ESP_BT_IO_CAP_IO;  // Display with prompt
+    } else if (!_IO_CAP_INPUT && _IO_CAP_OUTPUT) {
+      iocap = ESP_BT_IO_CAP_OUT;  // DisplayOnly
+    } else if (_IO_CAP_INPUT && !_IO_CAP_OUTPUT) {
+      iocap = ESP_BT_IO_CAP_IN;  // Input only
+    } else if (!_IO_CAP_INPUT && !_IO_CAP_OUTPUT) {
+      iocap = ESP_BT_IO_CAP_NONE;  // No input/output
     }
-    return true;
+    esp_bt_gap_set_security_param(param_type, &iocap, sizeof(uint8_t));
+  }
+
+  // the default BTA_DM_COD_LOUDSPEAKER does not work with the macOS BT stack
+  esp_bt_cod_t cod;
+  cod.major = 0b00001;
+  cod.minor = 0b000100;
+  cod.service = 0b00000010110;
+  if (esp_bt_gap_set_cod(cod, ESP_BT_INIT_COD) != ESP_OK) {
+    log_e("set cod failed");
+    return false;
+  }
+  return true;
 }
 
-static bool _stop_bt()
-{
-    if (btStarted()){
-        if(_spp_client)
-            esp_spp_disconnect(_spp_client);
-        esp_spp_deinit();
-        esp_bluedroid_disable();
-        esp_bluedroid_deinit();
-        btStop();
-    }
-    _spp_client = 0;
-    if(_spp_task_handle){
-        vTaskDelete(_spp_task_handle);
-        _spp_task_handle = NULL;
-    }
-    if(_spp_event_group){
-        vEventGroupDelete(_spp_event_group);
-        _spp_event_group = NULL;
-    }
-    if(_spp_rx_queue){
-        vQueueDelete(_spp_rx_queue);
-        //ToDo: clear RX queue when in packet mode
-        _spp_rx_queue = NULL;
-    }
-    if(_spp_tx_queue){
-        spp_packet_t *packet = NULL;
-        while(xQueueReceive(_spp_tx_queue, &packet, 0) == pdTRUE){
-            free(packet);
-        }
-        vQueueDelete(_spp_tx_queue);
-        _spp_tx_queue = NULL;
+static bool _stop_bt() {
+  if (btStarted()) {
+    if (_spp_client) {
+      esp_spp_disconnect(_spp_client);
     }
-    if (_spp_tx_done) {
-        vSemaphoreDelete(_spp_tx_done);
-        _spp_tx_done = NULL;
+    esp_spp_deinit();
+    esp_bluedroid_disable();
+    esp_bluedroid_deinit();
+    btStop();
+  }
+  _spp_client = 0;
+  if (_spp_task_handle) {
+    vTaskDelete(_spp_task_handle);
+    _spp_task_handle = NULL;
+  }
+  if (_spp_event_group) {
+    vEventGroupDelete(_spp_event_group);
+    _spp_event_group = NULL;
+  }
+  if (_spp_rx_queue) {
+    vQueueDelete(_spp_rx_queue);
+    //ToDo: clear RX queue when in packet mode
+    _spp_rx_queue = NULL;
+  }
+  if (_spp_tx_queue) {
+    spp_packet_t *packet = NULL;
+    while (xQueueReceive(_spp_tx_queue, &packet, 0) == pdTRUE) {
+      free(packet);
     }
-    return true;
+    vQueueDelete(_spp_tx_queue);
+    _spp_tx_queue = NULL;
+  }
+  if (_spp_tx_done) {
+    vSemaphoreDelete(_spp_tx_done);
+    _spp_tx_done = NULL;
+  }
+  if (_bt_event_group) {
+    vEventGroupDelete(_bt_event_group);
+    _bt_event_group = NULL;
+  }
+  return true;
 }
 
 static bool waitForConnect(int timeout) {
-    TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS;
-    return (xEventGroupWaitBits(_spp_event_group, SPP_CONNECTED, pdFALSE, pdTRUE, xTicksToWait) & SPP_CONNECTED) != 0;
+  TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS;
+  // wait for connected or closed
+  EventBits_t rc = xEventGroupWaitBits(_spp_event_group, SPP_CONNECTED | SPP_CLOSED, pdFALSE, pdFALSE, xTicksToWait);
+  if ((rc & SPP_CONNECTED) != 0) {
+    return true;
+  } else if ((rc & SPP_CLOSED) != 0) {
+    log_d("connection closed!");
+    return false;
+  }
+  log_d("timeout");
+  return false;
+}
+
+static bool waitForDiscovered(int timeout) {
+  TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS;
+  return (xEventGroupWaitBits(_spp_event_group, BT_DISCOVERY_COMPLETED, pdFALSE, pdTRUE, xTicksToWait) & BT_DISCOVERY_COMPLETED) != 0;
+}
+
+static bool waitForSDPRecord(int timeout) {
+  TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS;
+  return (xEventGroupWaitBits(_bt_event_group, BT_SDP_COMPLETED, pdFALSE, pdTRUE, xTicksToWait) & BT_SDP_COMPLETED) != 0;
 }
 
-/*
+/**
  * Serial Bluetooth Arduino
  *
- * */
+ */
+BluetoothSerial::BluetoothSerial() {
+  local_name = "ESP32";  //default bluetooth name
+}
 
-BluetoothSerial::BluetoothSerial()
-{
-    local_name = "ESP32"; //default bluetooth name
+BluetoothSerial::~BluetoothSerial(void) {
+  _stop_bt();
 }
 
-BluetoothSerial::~BluetoothSerial(void)
-{
-    _stop_bt();
+/**
+ * @param isMaster set to true if you want to connect to an other device
+ * @param disableBLE if BLE is not used, its ram can be freed to get +10kB free ram
+ */
+bool BluetoothSerial::begin(String localName, bool isMaster, bool disableBLE) {
+  _isMaster = isMaster;
+  if (localName.length()) {
+    local_name = localName;
+  }
+  return _init_bt(local_name.c_str(), disableBLE ? BT_MODE_CLASSIC_BT : BT_MODE_BTDM);
 }
 
-bool BluetoothSerial::begin(String localName, bool isMaster)
-{
-    _isMaster = isMaster;
-    if (localName.length()){
-        local_name = localName;
-    }
-    return _init_bt(local_name.c_str());
+int BluetoothSerial::available(void) {
+  if (_spp_rx_queue == NULL) {
+    return 0;
+  }
+  return uxQueueMessagesWaiting(_spp_rx_queue);
 }
 
-int BluetoothSerial::available(void)
-{
-    if (_spp_rx_queue == NULL){
-        return 0;
-    }
-    return uxQueueMessagesWaiting(_spp_rx_queue);
+int BluetoothSerial::peek(void) {
+  uint8_t c;
+  if (_spp_rx_queue && xQueuePeek(_spp_rx_queue, &c, this->timeoutTicks)) {
+    return c;
+  }
+  return -1;
 }
 
-int BluetoothSerial::peek(void)
-{
-    uint8_t c;
-    if (_spp_rx_queue && xQueuePeek(_spp_rx_queue, &c, 0)){
-        return c;
-    }
-    return -1;
+bool BluetoothSerial::hasClient(void) {
+  return _spp_client > 0;
 }
 
-bool BluetoothSerial::hasClient(void)
-{
-    return _spp_client > 0;
+int BluetoothSerial::read() {
+
+  uint8_t c = 0;
+  if (_spp_rx_queue && xQueueReceive(_spp_rx_queue, &c, this->timeoutTicks)) {
+    return c;
+  }
+  return -1;
 }
 
-int BluetoothSerial::read(void)
-{
+/**
+ * Set timeout for read / peek
+ */
+void BluetoothSerial::setTimeout(int timeoutMS) {
+  Stream::setTimeout(timeoutMS);
+  this->timeoutTicks = timeoutMS / portTICK_PERIOD_MS;
+}
 
-    uint8_t c = 0;
-    if (_spp_rx_queue && xQueueReceive(_spp_rx_queue, &c, 0)){
-        return c;
-    }
-    return -1;
+size_t BluetoothSerial::write(uint8_t c) {
+  return write(&c, 1);
 }
 
-size_t BluetoothSerial::write(uint8_t c)
-{
-    return write(&c, 1);
+size_t BluetoothSerial::write(const uint8_t *buffer, size_t size) {
+  if (!_spp_client) {
+    return 0;
+  }
+  return (_spp_queue_packet((uint8_t *)buffer, size) == ESP_OK) ? size : 0;
 }
 
-size_t BluetoothSerial::write(const uint8_t *buffer, size_t size)
-{
-    if (!_spp_client){
-        return 0;
+void BluetoothSerial::flush() {
+  if (_spp_tx_queue != NULL) {
+    while (uxQueueMessagesWaiting(_spp_tx_queue) > 0) {
+      delay(2);
     }
-    return (_spp_queue_packet((uint8_t *)buffer, size) == ESP_OK) ? size : 0;
+  }
 }
 
-void BluetoothSerial::flush()
-{
-    if (_spp_tx_queue != NULL){
-        while(uxQueueMessagesWaiting(_spp_tx_queue) > 0){
-	    delay(5);
-        }
-    }
+void BluetoothSerial::end() {
+  _stop_bt();
 }
 
-void BluetoothSerial::end()
-{
-    _stop_bt();
+/**
+ * free additional ~30kB ram, reset is required to enable BT again
+ */
+void BluetoothSerial::memrelease() {
+  esp_bt_mem_release(ESP_BT_MODE_BTDM);
 }
 
-esp_err_t BluetoothSerial::register_callback(esp_spp_cb_t * callback)
-{
-    custom_spp_callback = callback;
-    return ESP_OK;
+void BluetoothSerial::onConfirmRequest(ConfirmRequestCb cb) {
+  confirm_request_callback = cb;
 }
 
-//Simple Secure Pairing
+void BluetoothSerial::onKeyRequest(KeyRequestCb cb) {
+  key_request_callback = cb;
+}
+
+void BluetoothSerial::respondPasskey(uint32_t passkey) {
+  esp_bt_gap_ssp_passkey_reply(current_bd_addr, true, passkey);
+}
+
+void BluetoothSerial::onAuthComplete(AuthCompleteCb cb) {
+  auth_complete_callback = cb;
+}
+
+void BluetoothSerial::confirmReply(boolean confirm) {
+  esp_bt_gap_ssp_confirm_reply(current_bd_addr, confirm);
+}
+
+esp_err_t BluetoothSerial::register_callback(esp_spp_cb_t callback) {
+  custom_spp_callback = callback;
+  return ESP_OK;
+}
+
+// Enable Simple Secure Pairing (using generated PIN)
+// This must be called before calling begin, otherwise has no effect!
 void BluetoothSerial::enableSSP() {
-    _enableSSP = true;
-}
-/*
-     * Set default parameters for Legacy Pairing
-     * Use fixed pin code
-*/
-bool BluetoothSerial::setPin(const char *pin) {
-    bool isEmpty =  !(pin  && *pin);
-    if (isEmpty && !_isPinSet) {
-        return true; // nothing to do
-    } else if (!isEmpty){
-        _pin_len = strlen(pin);
-        memcpy(_pin_code, pin, _pin_len);
+  if (isReady(false, READY_TIMEOUT)) {
+    log_i("Attempted to enable SSP for already initialized driver. Restart to take effect with end() followed by begin()");
+    return;
+  }
+  _enableSSP = true;
+  _IO_CAP_INPUT = true;
+  _IO_CAP_OUTPUT = true;
+}
+
+// Enable Simple Secure Pairing (using generated PIN)
+// This must be called before calling begin, otherwise has no effect!
+// Behavior description:
+// When both Input and Output are false only the other device authenticates pairing without any pin.
+// When Output is true and Input is false only the other device authenticates pairing without any pin.
+// When both Input and Output are true both devices display randomly generated code and if they match authenticate pairing on both devices
+//   - This must be implemented by registering callback via onConfirmRequest() and in this callback request user input and call confirmReply(true); if the authenticated
+//      otherwise call `confirmReply(false)` to reject the pairing.
+// When Input is true and Output is false User will be required to input the passkey to the ESP32 device to authenticate.
+//   - This must be implemented by registering callback via onKeyRequest() and in this callback the entered passkey will be responded via respondPasskey(passkey);
+void BluetoothSerial::enableSSP(bool inputCpability, bool outputCapability) {
+  log_i("Enabling SSP: input capability=%d; output capability=%d", inputCpability, outputCapability);
+  _enableSSP = true;
+  _IO_CAP_INPUT = inputCpability;
+  _IO_CAP_OUTPUT = outputCapability;
+}
+
+// Disable Simple Secure Pairing (using generated PIN)
+// This must be called before calling begin, otherwise has no effect!
+void BluetoothSerial::disableSSP() {
+  _enableSSP = false;
+}
+
+bool BluetoothSerial::setPin(const char *pin, uint8_t pin_code_len) {
+  if (pin_code_len == 0 || pin_code_len > 16) {
+    log_e("PIN code must be 1-16 Bytes long! Called with length %d", pin_code_len);
+    return false;
+  }
+  _pin_code_len = pin_code_len;
+  memcpy(_pin_code, pin, pin_code_len);
+  return (esp_bt_gap_set_pin(ESP_BT_PIN_TYPE_FIXED, _pin_code_len, _pin_code) == ESP_OK);
+}
+
+bool BluetoothSerial::connect(String remoteName) {
+  bool retval = false;
+
+  if (!isReady(true, READY_TIMEOUT)) {
+    return false;
+  }
+  if (remoteName && remoteName.length() < 1) {
+    log_e("No remote name is provided");
+    return false;
+  }
+  disconnect();
+  _doConnect = true;
+  _isRemoteAddressSet = true;
+  _sec_mask = ESP_SPP_SEC_ENCRYPT | ESP_SPP_SEC_AUTHENTICATE;
+  _role = ESP_SPP_ROLE_MASTER;
+  strncpy(_remote_name, remoteName.c_str(), ESP_BT_GAP_MAX_BDNAME_LEN);
+  _remote_name[ESP_BT_GAP_MAX_BDNAME_LEN] = 0;
+  log_i("master : remoteName");
+  // will first resolve name to address
+#ifdef ESP_IDF_VERSION_MAJOR
+  esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE);
+#else
+  esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE);
+#endif
+  xEventGroupClearBits(_spp_event_group, SPP_CLOSED);
+  if (esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, INQ_LEN, INQ_NUM_RSPS) == ESP_OK) {
+    retval = waitForConnect(SCAN_TIMEOUT);
+  }
+  if (retval == false) {
+    _isRemoteAddressSet = false;
+  }
+  return retval;
+}
+
+/**
+ * Connect to an other bluetooth device
+ *
+ * @param channel specify channel or 0 for auto-detect
+ * @param sec_mask
+ *           ESP_SPP_SEC_ENCRYPT|ESP_SPP_SEC_AUTHENTICATE
+ *           ESP_SPP_SEC_NONE
+ * @param role
+ *           ESP_SPP_ROLE_MASTER   master can handle up to 7 connections to slaves
+ *           ESP_SPP_ROLE_SLAVE    can only have one connection to a master
+ */
+bool BluetoothSerial::connect(uint8_t remoteAddress[], int channel, esp_spp_sec_t sec_mask, esp_spp_role_t role) {
+  bool retval = false;
+  if (!isReady(true, READY_TIMEOUT)) {
+    return false;
+  }
+  if (!remoteAddress) {
+    log_e("No remote address is provided");
+    return false;
+  }
+  disconnect();
+  _doConnect = true;
+  _remote_name[0] = 0;
+  _isRemoteAddressSet = true;
+  _sec_mask = sec_mask;
+  _role = role;
+  memcpy(_peer_bd_addr, remoteAddress, ESP_BD_ADDR_LEN);
+  log_i("master : remoteAddress");
+  xEventGroupClearBits(_spp_event_group, SPP_CLOSED);
+  if (channel > 0) {
+#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)
+    char bda_str[18];
+    log_i("spp connect to remote %s channel %d", bda2str(_peer_bd_addr, bda_str, sizeof(bda_str)), channel);
+#endif
+    if (esp_spp_connect(sec_mask, role, channel, _peer_bd_addr) != ESP_OK) {
+      log_e("spp connect failed");
+      retval = false;
     } else {
-        _pin_len = 0; // resetting pin to none (default)
-    }
-    _pin_code[_pin_len] = 0;
-    _isPinSet = true;
-    if (isReady(false, READY_TIMEOUT)) {
-        btSetPin();
+      retval = waitForConnect(READY_TIMEOUT);
+      if (retval) {
+        log_i("connected");
+      } else {
+        if (this->isClosed()) {
+          log_e("connect failed");
+        } else {
+          log_e("connect timed out after %dms", READY_TIMEOUT);
+        }
+      }
     }
-    return true;
+  } else if (esp_spp_start_discovery(_peer_bd_addr) == ESP_OK) {
+    retval = waitForConnect(READY_TIMEOUT);
+  }
+
+  if (!retval) {
+    _isRemoteAddressSet = false;
+  }
+  return retval;
 }
 
-bool BluetoothSerial::connect(String remoteName)
-{
-    if (!isReady(true, READY_TIMEOUT)) return false;
-    if (remoteName && remoteName.length() < 1) {
-        log_e("No remote name is provided");
-        return false; 
+bool BluetoothSerial::connect() {
+  if (!isReady(true, READY_TIMEOUT)) {
+    return false;
+  }
+  _doConnect = true;
+  if (_isRemoteAddressSet) {
+    disconnect();
+    // use resolved or set address first
+    log_i("master : remoteAddress");
+    if (esp_spp_start_discovery(_peer_bd_addr) == ESP_OK) {
+      return waitForConnect(READY_TIMEOUT);
     }
+    return false;
+  } else if (_remote_name[0]) {
     disconnect();
-    _isRemoteAddressSet = false;
-    strncpy(_remote_name, remoteName.c_str(), ESP_BT_GAP_MAX_BDNAME_LEN);
-    _remote_name[ESP_BT_GAP_MAX_BDNAME_LEN] = 0;
     log_i("master : remoteName");
-    // will first resolve name to address
+    // will resolve name to address first - it may take a while
+#ifdef ESP_IDF_VERSION_MAJOR
+    esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE);
+#else
     esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE);
+#endif
     if (esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, INQ_LEN, INQ_NUM_RSPS) == ESP_OK) {
-        return waitForConnect(SCAN_TIMEOUT);
+      return waitForConnect(SCAN_TIMEOUT);
     }
     return false;
+  }
+  log_e("Neither Remote name nor address was provided");
+  return false;
 }
 
-bool BluetoothSerial::connect(uint8_t remoteAddress[])
-{
-    if (!isReady(true, READY_TIMEOUT)) return false;
-    if (!remoteAddress) {
-        log_e("No remote address is provided");
-        return false; 
-    }
-    disconnect();
-    _remote_name[0] = 0;
-    _isRemoteAddressSet = true;
-    memcpy(_peer_bd_addr, remoteAddress, ESP_BD_ADDR_LEN);
-    log_i("master : remoteAddress");
-    if (esp_spp_start_discovery(_peer_bd_addr) == ESP_OK) {
-        return waitForConnect(READY_TIMEOUT);
+bool BluetoothSerial::disconnect() {
+  if (_spp_client) {
+    flush();
+    log_i("disconnecting");
+    if (esp_spp_disconnect(_spp_client) == ESP_OK) {
+      TickType_t xTicksToWait = READY_TIMEOUT / portTICK_PERIOD_MS;
+      return (xEventGroupWaitBits(_spp_event_group, SPP_DISCONNECTED, pdFALSE, pdTRUE, xTicksToWait) & SPP_DISCONNECTED) != 0;
     }
-    return false;
+  }
+  return false;
 }
 
-bool BluetoothSerial::connect()
-{
-    if (!isReady(true, READY_TIMEOUT)) return false;
-    if (_isRemoteAddressSet){
-        disconnect();
-        // use resolved or set address first
-        log_i("master : remoteAddress");
-        if (esp_spp_start_discovery(_peer_bd_addr) == ESP_OK) {
-            return waitForConnect(READY_TIMEOUT);
-        }
-        return false;
-    } else if (_remote_name[0]) {
-        disconnect();
-        log_i("master : remoteName");
-        // will resolve name to address first - it may take a while
-        esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE);
-        if (esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, INQ_LEN, INQ_NUM_RSPS) == ESP_OK) {
-            return waitForConnect(SCAN_TIMEOUT);
-        }
-        return false;
-    }
-    log_e("Neither Remote name nor address was provided");
+bool BluetoothSerial::unpairDevice(uint8_t remoteAddress[]) {
+  if (isReady(false, READY_TIMEOUT)) {
+    log_i("removing bonded device");
+    return (esp_bt_gap_remove_bond_device(remoteAddress) == ESP_OK);
+  }
+  return false;
+}
+
+bool BluetoothSerial::connected(int timeout) {
+  return waitForConnect(timeout);
+}
+
+/**
+ * true if a connection terminated or a connection attempt failed
+ */
+bool BluetoothSerial::isClosed() {
+  return xEventGroupGetBits(_spp_event_group) & SPP_CLOSED;
+}
+
+bool BluetoothSerial::isReady(bool checkMaster, int timeout) {
+  if (checkMaster && !_isMaster) {
+    log_e("Master mode is not active. Call begin(localName, true) to enable Master mode");
+    return false;
+  }
+  if (!btStarted()) {
+    log_e("BT is not initialized. Call begin() first");
     return false;
+  }
+  TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS;
+  return (xEventGroupWaitBits(_spp_event_group, SPP_RUNNING, pdFALSE, pdTRUE, xTicksToWait) & SPP_RUNNING) != 0;
 }
 
-bool BluetoothSerial::disconnect() {
-    if (_spp_client) {
-        flush();
-        log_i("disconnecting");
-        if (esp_spp_disconnect(_spp_client) == ESP_OK) {
-            TickType_t xTicksToWait = READY_TIMEOUT / portTICK_PERIOD_MS;
-            return (xEventGroupWaitBits(_spp_event_group, SPP_DISCONNECTED, pdFALSE, pdTRUE, xTicksToWait) & SPP_DISCONNECTED) != 0;
-        }
-    }
+/**
+ * @brief           RemoteName or address are not allowed to be set during discovery
+ *                  (otherwise it might connect automatically and stop discovery)
+ * @param[in]       timeoutMs can range from MIN_INQ_TIME to MAX_INQ_TIME
+ * @return          in case of Error immediately Empty ScanResults.
+ */
+BTScanResults *BluetoothSerial::discover(int timeoutMs) {
+  scanResults.clear();
+  if (timeoutMs < MIN_INQ_TIME || timeoutMs > MAX_INQ_TIME) {
+    log_e("Timeout out of bounds: MIN=%d; MAX=%d; requested=%d", MIN_INQ_TIME, MAX_INQ_TIME, timeoutMs);
+    return nullptr;
+  }
+  int timeout = timeoutMs / INQ_TIME;
+  log_i("discover::disconnect");
+  disconnect();
+  log_i("discovering");
+  // will resolve name to address first - it may take a while
+  esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE);
+  if (esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, timeout, 0) == ESP_OK) {
+    waitForDiscovered(timeoutMs);
+    log_i("gap_cancel_discovery()");
+    esp_bt_gap_cancel_discovery();
+  }
+  return &scanResults;
+}
+
+/**
+ * @brief           RemoteName or address are not allowed to be set during discovery
+ *                  (otherwise it might connect automatically and stop discovery)
+ * @param[in]       cb called when a [b]new[/b] device has been discovered
+ * @param[in]       timeoutMs can be 0 or range from MIN_INQ_TIME to MAX_INQ_TIME
+ *
+ * @return          Whether start was successful or problems with params
+ */
+bool BluetoothSerial::discoverAsync(BTAdvertisedDeviceCb cb, int timeoutMs) {
+  scanResults.clear();
+  if (strlen(_remote_name) || _isRemoteAddressSet) {
     return false;
+  }
+  int timeout = timeoutMs / INQ_TIME;
+  disconnect();
+  advertisedDeviceCb = cb;
+  log_i("discovering");
+  // will resolve name to address first - it may take a while
+  esp_bt_gap_set_scan_mode(ESP_BT_CONNECTABLE, ESP_BT_GENERAL_DISCOVERABLE);
+  if (timeout > 0) {
+    return esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, timeout, 0) == ESP_OK;
+  } else {
+    return esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, ESP_BT_GAP_MAX_INQ_LEN, 0) == ESP_OK;
+  }
 }
 
-bool BluetoothSerial::unpairDevice(uint8_t remoteAddress[]) {
-    if (isReady(false, READY_TIMEOUT)) {
-        log_i("removing bonded device");
-        return (esp_bt_gap_remove_bond_device(remoteAddress) == ESP_OK);
+/** @brief      Stops the asynchronous discovery and clears the callback */
+void BluetoothSerial::discoverAsyncStop() {
+  esp_bt_gap_cancel_discovery();
+  advertisedDeviceCb = nullptr;
+}
+
+/** @brief      Clears scanResult entries */
+void BluetoothSerial::discoverClear() {
+  scanResults.clear();
+}
+
+/** @brief      Can be used while discovering asynchronously
+ *              Will be returned also on synchronous discovery.
+ *
+ * @return      BTScanResults contains several information of found devices
+ */
+BTScanResults *BluetoothSerial::getScanResults() {
+  return &scanResults;
+}
+
+BluetoothSerial::operator bool() const {
+  return true;
+}
+
+/**
+ * SDP scan address
+ * esp_spp_start_discovery doesn't tell us the btAddress in the callback, so we have to wait until it's finished
+ */
+std::map<int, std::string> BluetoothSerial::getChannels(const BTAddress &remoteAddress) {
+  if (xEventGroupGetBits(_bt_event_group) & BT_SDP_RUNNING) {
+    log_e("getChannels failed - already running");
+  }
+  xEventGroupSetBits(_bt_event_group, BT_SDP_RUNNING);
+  xEventGroupClearBits(_bt_event_group, BT_SDP_COMPLETED);
+  _doConnect = false;
+  sdpRecords.clear();
+  log_d("esp_spp_start_discovery");
+  if (esp_spp_start_discovery(*remoteAddress.getNative()) != ESP_OK) {
+    log_e("esp_spp_start_discovery failed");
+  } else {
+    if (!waitForSDPRecord(READY_TIMEOUT)) {
+      log_e("getChannels failed timeout");
     }
-    return false;
+    log_d("esp_spp_start_discovery wait for BT_SDP_COMPLETED done (%dms)", READY_TIMEOUT);
+  }
+  log_d("esp_spp_start_discovery done, found %d services", sdpRecords.size());
+  xEventGroupClearBits(_bt_event_group, BT_SDP_RUNNING);
+  return sdpRecords;
 }
 
-bool BluetoothSerial::connected(int timeout) {
-    return waitForConnect(timeout);
+/**
+ * @brief      Gets the MAC address of local BT device in byte array.
+ *
+ * @param      mac [out]  The mac
+ */
+void BluetoothSerial::getBtAddress(uint8_t *mac) {
+  const uint8_t *dev_mac = esp_bt_dev_get_address();
+  memcpy(mac, dev_mac, ESP_BD_ADDR_LEN);
+}
+/**
+ * @brief      Gets the MAC address of local BT device as BTAddress object.
+ *
+ * @return     The BTAddress object.
+ */
+BTAddress BluetoothSerial::getBtAddressObject() {
+  uint8_t mac_arr[ESP_BD_ADDR_LEN];
+  getBtAddress(mac_arr);
+  return BTAddress(mac_arr);
+}
+/**
+ * @brief      Gets the MAC address of local BT device as string.
+ *
+ * @return     The BT MAC address string.
+ */
+String BluetoothSerial::getBtAddressString() {
+  return getBtAddressObject().toString(true);
 }
 
-bool BluetoothSerial::isReady(bool checkMaster, int timeout) {
-    if (checkMaster && !_isMaster) {
-        log_e("Master mode is not active. Call begin(localName, true) to enable Master mode");
-        return false;
+// Send a request to the remote device defined by the remoteAddress to send back its name.
+// The name will be read by background task and stored. It can be later read with radRemoteName()
+void BluetoothSerial::requestRemoteName(uint8_t remoteAddress[]) {
+  if (isReady(false, READY_TIMEOUT)) {
+    esp_bt_gap_read_remote_name(remoteAddress);
+  }
+}
+
+// If remote name is valid (was already received) this function will copy the name to the aprameter rmt_name
+// The buffer must have size at least ESP_BT_GAP_MAX_BDNAME_LEN + 1
+// If the name is valid the function will return true
+// If the name is not valid (was not read yet) returns false
+bool BluetoothSerial::readRemoteName(char rmt_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1]) {
+  if (_rmt_name_valid) {
+    memcpy(rmt_name, _rmt_name, ESP_BT_GAP_MAX_BDNAME_LEN + 1);
+    return true;
+  }
+  return false;
+}
+
+// Set validity of remote name before reading name from different device
+void BluetoothSerial::invalidateRemoteName() {
+  _rmt_name_valid = false;
+}
+
+int BluetoothSerial::getNumberOfBondedDevices() {
+  return esp_bt_gap_get_bond_device_num();
+}
+
+// Accepts the maximum number of devices that can fit in given array dev_list.
+// Create you list this way: esp_bd_addr_t dev_list[dev_num];
+// Returns number of retrieved devices (on error returns 0)
+int BluetoothSerial::getBondedDevices(uint dev_num, esp_bd_addr_t *dev_list) {
+  // typedef uint8_t esp_bd_addr_t[ESP_BD_ADDR_LEN]
+  if (dev_list == NULL) {
+    log_e("Device list is NULL");
+    return 0;
+  }
+  if (dev_num == 0) {
+    log_e("Device number must be larger than 0!");
+    return 0;
+  }
+  int _dev_num = dev_num;
+  esp_bt_gap_get_bond_device_list(&_dev_num, dev_list);
+  return _dev_num;
+}
+
+bool BluetoothSerial::deleteBondedDevice(uint8_t *remoteAddress) {
+  esp_err_t ret = esp_bt_gap_remove_bond_device(remoteAddress);
+  if (ret == ESP_OK) {
+    return true;
+  } else {
+    return false;
+  }
+}
+
+void BluetoothSerial::deleteAllBondedDevices() {
+  if (!isReady(false, READY_TIMEOUT)) {
+    log_w("Attempted to drop cache for uninitialized driver. First call begin()");
+    return;
+  }
+
+  int expected_dev_num = esp_bt_gap_get_bond_device_num();
+  if (expected_dev_num == 0) {
+    log_i("No devices in cache.");
+    return;
+  } else {
+    log_d("Found %d bonded devices", expected_dev_num);
+  }
+  esp_err_t ret;
+
+  // typedef uint8_t esp_bd_addr_t[ESP_BD_ADDR_LEN] // ESP_BD_ADDR_LEN = 6
+  esp_bd_addr_t *dev_list = NULL;
+  log_d("Allocate buffer: sizeof(esp_bd_addr_t)=%d * expected_dev_num=%d", sizeof(esp_bd_addr_t), expected_dev_num);
+  dev_list = (esp_bd_addr_t *)malloc(sizeof(esp_bd_addr_t) * expected_dev_num);
+  if (dev_list == NULL) {
+    log_e("Could not allocated BT device buffer!");
+    return;
+  }
+  //uint8_t dev_list [20][6];
+
+  int dev_num;
+  ret = esp_bt_gap_get_bond_device_list(&dev_num, dev_list);
+  log_d("esp_bt_gap_get_bond_device_list ret = %d", ret);
+  if (ret == ESP_OK) {
+    if (dev_num != expected_dev_num) {
+      log_w("Inconsistent number of bonded devices. Expected %d; returned %d", expected_dev_num, dev_num);
     }
-    if (!btStarted()) {
-        log_e("BT is not initialized. Call begin() first");
-        return false;
+    for (int i = 0; i < dev_num; ++i) {
+      ret = esp_bt_gap_remove_bond_device(dev_list[i]);
+      log_d("esp_bt_gap_remove_bond_device ret = %d", ret);
+      if (ret == ESP_OK) {
+        log_d("Removed bonded device #%d", i);
+      } else {
+        log_w("Failed to removed bonded device #%d", i);
+      }
+      //btc_storage_remove_bonded_device(dev_list[i]);
     }
-    TickType_t xTicksToWait = timeout / portTICK_PERIOD_MS;
-    return (xEventGroupWaitBits(_spp_event_group, SPP_RUNNING, pdFALSE, pdTRUE, xTicksToWait) & SPP_RUNNING) != 0;
+    log_d("device num after delete = %d", esp_bt_gap_get_bond_device_num());
+  } else {
+    log_w("Function esp_bt_gap_get_bond_device_list() returned code %d", ret);
+  }
 }
-#endif
+#endif  // defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED)
diff --git a/libraries/BluetoothSerial/src/BluetoothSerial.h b/libraries/BluetoothSerial/src/BluetoothSerial.h
old mode 100755
new mode 100644
index 6ccb9b49e2b..d59fbf1f714
--- a/libraries/BluetoothSerial/src/BluetoothSerial.h
+++ b/libraries/BluetoothSerial/src/BluetoothSerial.h
@@ -21,43 +21,97 @@
 
 #include "Arduino.h"
 #include "Stream.h"
+#include <esp_gap_bt_api.h>
 #include <esp_spp_api.h>
 #include <functional>
+#include <map>
+#include "BTScan.h"
+#include "BTAdvertisedDevice.h"
 
 typedef std::function<void(const uint8_t *buffer, size_t size)> BluetoothSerialDataCb;
+typedef std::function<void(uint32_t num_val)> ConfirmRequestCb;
+typedef std::function<void()> KeyRequestCb;
+typedef std::function<void(boolean success)> AuthCompleteCb;
+typedef std::function<void(BTAdvertisedDevice *pAdvertisedDevice)> BTAdvertisedDeviceCb;
 
-class BluetoothSerial: public Stream
-{
-    public:
-
-        BluetoothSerial(void);
-        ~BluetoothSerial(void);
-
-        bool begin(String localName=String(), bool isMaster=false);
-        int available(void);
-        int peek(void);
-        bool hasClient(void);
-        int read(void);
-        size_t write(uint8_t c);
-        size_t write(const uint8_t *buffer, size_t size);
-        void flush();
-        void end(void);
-        void onData(BluetoothSerialDataCb cb);
-        esp_err_t register_callback(esp_spp_cb_t * callback);
-
-        void enableSSP();
-        bool setPin(const char *pin);
-        bool connect(String remoteName);
-        bool connect(uint8_t remoteAddress[]);
-        bool connect();
-        bool connected(int timeout=0);
-        bool isReady(bool checkMaster=false, int timeout=0);
-        bool disconnect();
-        bool unpairDevice(uint8_t remoteAddress[]);
-
-    private:
-        String local_name;
+class BluetoothSerial : public Stream {
+public:
+  BluetoothSerial(void);
+  ~BluetoothSerial(void);
 
+  bool begin(String localName = String(), bool isMaster = false, bool disableBLE = false);
+  bool begin(unsigned long baud) {  //compatibility
+    return begin();
+  }
+  int available(void);
+  int peek(void);
+  bool hasClient(void);
+  int read(void);
+  size_t write(uint8_t c);
+  size_t write(const uint8_t *buffer, size_t size);
+  void flush();
+  void end(void);
+  void memrelease();
+  void setTimeout(int timeoutMS);
+  void onData(BluetoothSerialDataCb cb);
+  esp_err_t register_callback(esp_spp_cb_t callback);
+
+  void onConfirmRequest(ConfirmRequestCb cb);
+  void onKeyRequest(KeyRequestCb cb);
+  void respondPasskey(uint32_t passkey);
+  void onAuthComplete(AuthCompleteCb cb);
+  void confirmReply(boolean confirm);
+
+  void enableSSP();
+  void enableSSP(bool inputCapability, bool outputCapability);
+  void disableSSP();
+  bool setPin(const char *pin, uint8_t pin_code_len);
+  bool connect(String remoteName);
+  bool connect(
+    uint8_t remoteAddress[], int channel = 0, esp_spp_sec_t sec_mask = (ESP_SPP_SEC_ENCRYPT | ESP_SPP_SEC_AUTHENTICATE),
+    esp_spp_role_t role = ESP_SPP_ROLE_MASTER
+  );
+  bool connect(
+    const BTAddress &remoteAddress, int channel = 0, esp_spp_sec_t sec_mask = (ESP_SPP_SEC_ENCRYPT | ESP_SPP_SEC_AUTHENTICATE),
+    esp_spp_role_t role = ESP_SPP_ROLE_MASTER
+  ) {
+    return connect(*remoteAddress.getNative(), channel, sec_mask);
+  };
+  bool connect();
+  bool connected(int timeout = 0);
+  bool isClosed();
+  bool isReady(bool checkMaster = false, int timeout = 0);
+  bool disconnect();
+  bool unpairDevice(uint8_t remoteAddress[]);
+
+  BTScanResults *discover(int timeout = 0x30 * 1280);
+  bool discoverAsync(BTAdvertisedDeviceCb cb, int timeout = 0x30 * 1280);
+  void discoverAsyncStop();
+  void discoverClear();
+  BTScanResults *getScanResults();
+
+  std::map<int, std::string> getChannels(const BTAddress &remoteAddress);
+
+  const int INQ_TIME = 1280;  // Inquire Time unit 1280 ms
+  const int MIN_INQ_TIME = (ESP_BT_GAP_MIN_INQ_LEN * INQ_TIME);
+  const int MAX_INQ_TIME = (ESP_BT_GAP_MAX_INQ_LEN * INQ_TIME);
+
+  operator bool() const;
+  void getBtAddress(uint8_t *mac);
+  BTAddress getBtAddressObject();
+  String getBtAddressString();
+  //void dropCache(); // To be replaced
+  void requestRemoteName(uint8_t *remoteAddress);
+  bool readRemoteName(char rmt_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1]);
+  void invalidateRemoteName();
+  int getNumberOfBondedDevices();
+  int getBondedDevices(uint dev_num, esp_bd_addr_t *dev_list);
+  bool deleteBondedDevice(uint8_t *remoteAddress);
+  void deleteAllBondedDevices();
+
+private:
+  String local_name;
+  int timeoutTicks = 0;
 };
 
 #endif
diff --git a/libraries/DNSServer/examples/CaptivePortal/CaptivePortal.ino b/libraries/DNSServer/examples/CaptivePortal/CaptivePortal.ino
index 9221af1eaa2..d956dc14ad3 100644
--- a/libraries/DNSServer/examples/CaptivePortal/CaptivePortal.ino
+++ b/libraries/DNSServer/examples/CaptivePortal/CaptivePortal.ino
@@ -1,52 +1,64 @@
+/*
+This example enables catch-all Captive portal for ESP32 Access-Point
+It will allow modern devices/OSes to detect that WiFi connection is
+limited and offer a user to access a banner web-page.
+There is no need to find and open device's IP address/URL, i.e. http://192.168.4.1/
+This works for Android, Ubuntu, FireFox, Windows, maybe others...
+*/
+
+#include <Arduino.h>
 #include <WiFi.h>
 #include <DNSServer.h>
+#include <WebServer.h>
 
-const byte DNS_PORT = 53;
-IPAddress apIP(8,8,4,4); // The default android DNS
 DNSServer dnsServer;
-WiFiServer server(80);
+WebServer server(80);
+
+static const char responsePortal[] = R"===(
+<!DOCTYPE html><html><head><title>ESP32 CaptivePortal</title></head><body>
+<h1>Hello World!</h1><p>This is a captive portal example page. All unknown http requests will
+be redirected here.</p></body></html>
+)===";
 
-String responseHTML = ""
-  "<!DOCTYPE html><html><head><title>CaptivePortal</title></head><body>"
-  "<h1>Hello World!</h1><p>This is a captive portal example. All requests will "
-  "be redirected here.</p></body></html>";
+// index page handler
+void handleRoot() {
+  server.send(200, "text/plain", "Hello from esp32!");
+}
+
+// this will redirect unknown http req's to our captive portal page
+// based on this redirect various systems could detect that WiFi AP has a captive portal page
+void handleNotFound() {
+  server.sendHeader("Location", "/portal");
+  server.send(302, "text/plain", "redirect to captive portal");
+}
 
-void setup() { 
+void setup() {
+  Serial.begin(115200);
   WiFi.mode(WIFI_AP);
   WiFi.softAP("ESP32-DNSServer");
-  WiFi.softAPConfig(apIP, apIP, IPAddress(255, 255, 255, 0));
 
-  // if DNSServer is started with "*" for domain name, it will reply with
-  // provided IP to all DNS request
-  dnsServer.start(DNS_PORT, "*", apIP);
+  // by default DNSServer is started serving any "*" domain name. It will reply
+  // AccessPoint's IP to all DNS request (this is required for Captive Portal detection)
+  if (dnsServer.start()) {
+    Serial.println("Started DNS server in captive portal-mode");
+  } else {
+    Serial.println("Err: Can't start DNS server!");
+  }
+
+  // serve a simple root page
+  server.on("/", handleRoot);
 
+  // serve portal page
+  server.on("/portal", []() {
+    server.send(200, "text/html", responsePortal);
+  });
+
+  // all unknown pages are redirected to captive portal
+  server.onNotFound(handleNotFound);
   server.begin();
 }
 
 void loop() {
-  dnsServer.processNextRequest();
-  WiFiClient client = server.available();   // listen for incoming clients
-
-  if (client) {
-    String currentLine = "";
-    while (client.connected()) {
-      if (client.available()) {
-        char c = client.read();
-        if (c == '\n') {
-          if (currentLine.length() == 0) {
-            client.println("HTTP/1.1 200 OK");
-            client.println("Content-type:text/html");
-            client.println();
-            client.print(responseHTML);
-            break;
-          } else {
-            currentLine = "";
-          }
-        } else if (c != '\r') {
-          currentLine += c;
-        }
-      }
-    }
-    client.stop();
-  }
+  server.handleClient();
+  delay(5);  // give CPU some idle time
 }
diff --git a/libraries/DNSServer/examples/CaptivePortal/ci.json b/libraries/DNSServer/examples/CaptivePortal/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/DNSServer/examples/CaptivePortal/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/DNSServer/library.properties b/libraries/DNSServer/library.properties
index 8da8e6b3300..5e70a6ec03a 100644
--- a/libraries/DNSServer/library.properties
+++ b/libraries/DNSServer/library.properties
@@ -1,5 +1,5 @@
 name=DNSServer
-version=1.1.0
+version=3.2.0
 author=Kristijan Novoselić
 maintainer=Kristijan Novoselić, <kristijan.novoselic@gmail.com>
 sentence=A simple DNS server for ESP32.
diff --git a/libraries/DNSServer/src/DNSServer.cpp b/libraries/DNSServer/src/DNSServer.cpp
index a7f0d15eb62..28cf89d6ede 100644
--- a/libraries/DNSServer/src/DNSServer.cpp
+++ b/libraries/DNSServer/src/DNSServer.cpp
@@ -1,6 +1,7 @@
 #include "DNSServer.h"
 #include <lwip/def.h>
 #include <Arduino.h>
+#include <WiFi.h>
 
 // #define DEBUG_ESP_DNS
 #ifdef DEBUG_ESP_PORT
@@ -9,202 +10,180 @@
 #define DEBUG_OUTPUT Serial
 #endif
 
-DNSServer::DNSServer()
-{
-  _ttl = htonl(DNS_DEFAULT_TTL);
-  _errorReplyCode = DNSReplyCode::NonExistentDomain;
-  _dnsHeader    = (DNSHeader*) malloc( sizeof(DNSHeader) ) ;
-  _dnsQuestion  = (DNSQuestion*) malloc( sizeof(DNSQuestion) ) ;     
-  _buffer     = NULL;
-  _currentPacketSize = 0;
-  _port = 0;
+#define DNS_MIN_REQ_LEN 17  // minimal size for DNS request asking ROOT = DNS_HEADER_SIZE + 1 null byte for Name + 4 bytes type/class
+
+DNSServer::DNSServer() : _port(DNS_DEFAULT_PORT), _ttl(htonl(DNS_DEFAULT_TTL)), _errorReplyCode(DNSReplyCode::NonExistentDomain) {}
+
+DNSServer::DNSServer(const String &domainName)
+  : _port(DNS_DEFAULT_PORT), _ttl(htonl(DNS_DEFAULT_TTL)), _errorReplyCode(DNSReplyCode::NonExistentDomain), _domainName(domainName){};
+
+bool DNSServer::start() {
+  if (_resolvedIP.operator uint32_t() == 0) {  // no address is set, try to obtain AP interface's IP
+#if SOC_WIFI_SUPPORTED
+    if (WiFi.getMode() & WIFI_AP) {
+      _resolvedIP = WiFi.softAPIP();
+    } else {
+      return false;  // won't run if WiFi is not in AP mode, or no WiFi
+    }
+#else
+    return false;  // for other non WiFi-AP networking an overloaded method must be used to get device's IP
+                   // start(uint16_t port, const String &domainName, const IPAddress &resolvedIP)
+#endif
+  }
+
+  _udp.close();
+  _udp.onPacket([this](AsyncUDPPacket &pkt) {
+    this->_handleUDP(pkt);
+  });
+  return _udp.listen(_port);
 }
 
-bool DNSServer::start(const uint16_t &port, const String &domainName,
-                     const IPAddress &resolvedIP)
-{
+bool DNSServer::start(uint16_t port, const String &domainName, const IPAddress &resolvedIP) {
   _port = port;
-  _buffer = NULL;
-  _domainName = domainName;
-  _resolvedIP[0] = resolvedIP[0];
-  _resolvedIP[1] = resolvedIP[1];
-  _resolvedIP[2] = resolvedIP[2];
-  _resolvedIP[3] = resolvedIP[3];
-  downcaseAndRemoveWwwPrefix(_domainName);
-  return _udp.begin(_port) == 1;
+  if (domainName != "*") {
+    _domainName = domainName;
+    downcaseAndRemoveWwwPrefix(_domainName);
+  } else {
+    _domainName.clear();
+  }
+
+  _resolvedIP = resolvedIP;
+  _udp.close();
+  _udp.onPacket([this](AsyncUDPPacket &pkt) {
+    this->_handleUDP(pkt);
+  });
+  return _udp.listen(_port);
 }
 
-void DNSServer::setErrorReplyCode(const DNSReplyCode &replyCode)
-{
+void DNSServer::setErrorReplyCode(const DNSReplyCode &replyCode) {
   _errorReplyCode = replyCode;
 }
 
-void DNSServer::setTTL(const uint32_t &ttl)
-{
+void DNSServer::setTTL(const uint32_t &ttl) {
   _ttl = htonl(ttl);
 }
 
-void DNSServer::stop()
-{
-  _udp.stop();
-  free(_buffer);
-  _buffer = NULL;
+void DNSServer::stop() {
+  _udp.close();
 }
 
-void DNSServer::downcaseAndRemoveWwwPrefix(String &domainName)
-{
+void DNSServer::downcaseAndRemoveWwwPrefix(String &domainName) {
   domainName.toLowerCase();
   domainName.replace("www.", "");
 }
 
-void DNSServer::processNextRequest()
-{
-  _currentPacketSize = _udp.parsePacket();
-  if (_currentPacketSize)
-  {
-    // Allocate buffer for the DNS query
-    if (_buffer != NULL) 
-      free(_buffer);
-    _buffer = (unsigned char*)malloc(_currentPacketSize * sizeof(char));
-    if (_buffer == NULL) 
-      return;
-
-    // Put the packet received in the buffer and get DNS header (beginning of message)
-    // and the question
-    _udp.read(_buffer, _currentPacketSize);
-    memcpy( _dnsHeader, _buffer, DNS_HEADER_SIZE ) ; 
-    if ( requestIncludesOnlyOneQuestion() )
-    {
+void DNSServer::_handleUDP(AsyncUDPPacket &pkt) {
+  if (pkt.length() < DNS_MIN_REQ_LEN) {
+    return;  // truncated packet or not a DNS req
+  }
+
+  // get DNS header (beginning of message)
+  DNSHeader dnsHeader;
+  DNSQuestion dnsQuestion;
+  memcpy(&dnsHeader, pkt.data(), DNS_HEADER_SIZE);
+  if (dnsHeader.QR != DNS_QR_QUERY) {
+    return;  // ignore non-query messages
+  }
+
+  if (requestIncludesOnlyOneQuestion(dnsHeader)) {
+    /*
       // The QName has a variable length, maximum 255 bytes and is comprised of multiple labels.
-      // Each label contains a byte to describe its length and the label itself. The list of 
+      // Each label contains a byte to describe its length and the label itself. The list of
       // labels terminates with a zero-valued byte. In "github.com", we have two labels "github" & "com"
-      // Iterate through the labels and copy them as they come into a single buffer (for simplicity's sake)
-      _dnsQuestion->QNameLength = 0 ;
-      while ( _buffer[ DNS_HEADER_SIZE + _dnsQuestion->QNameLength ] != 0 )
-      {
-        memcpy( (void*) &_dnsQuestion->QName[_dnsQuestion->QNameLength], (void*) &_buffer[DNS_HEADER_SIZE + _dnsQuestion->QNameLength], _buffer[DNS_HEADER_SIZE + _dnsQuestion->QNameLength] + 1 ) ;
-        _dnsQuestion->QNameLength += _buffer[DNS_HEADER_SIZE + _dnsQuestion->QNameLength] + 1 ; 
-      }
-      _dnsQuestion->QName[_dnsQuestion->QNameLength] = 0 ; 
-      _dnsQuestion->QNameLength++ ;   
-
-      // Copy the QType and QClass 
-      memcpy( &_dnsQuestion->QType, (void*) &_buffer[DNS_HEADER_SIZE + _dnsQuestion->QNameLength], sizeof(_dnsQuestion->QType) ) ;
-      memcpy( &_dnsQuestion->QClass, (void*) &_buffer[DNS_HEADER_SIZE + _dnsQuestion->QNameLength + sizeof(_dnsQuestion->QType)], sizeof(_dnsQuestion->QClass) ) ;
-    }
-    
-
-    if (_dnsHeader->QR == DNS_QR_QUERY &&
-        _dnsHeader->OPCode == DNS_OPCODE_QUERY &&
-        requestIncludesOnlyOneQuestion() &&
-        (_domainName == "*" || getDomainNameWithoutWwwPrefix() == _domainName)
-       )
-    {
-      replyWithIP();
-    }
-    else if (_dnsHeader->QR == DNS_QR_QUERY)
-    {
-      replyWithCustomCode();
+*/
+    const char *enoflbls = strchr(reinterpret_cast<const char *>(pkt.data()) + DNS_HEADER_SIZE, 0);  // find end_of_label marker
+    ++enoflbls;                                                                                      // advance after null terminator
+    dnsQuestion.QName = pkt.data() + DNS_HEADER_SIZE;                                                // we can reference labels from the request
+    dnsQuestion.QNameLength = enoflbls - (char *)pkt.data() - DNS_HEADER_SIZE;
+    /*
+        check if we aint going out of pkt bounds
+        proper dns req should have label terminator at least 4 bytes before end of packet
+      */
+    if (dnsQuestion.QNameLength > pkt.length() - DNS_HEADER_SIZE - sizeof(dnsQuestion.QType) - sizeof(dnsQuestion.QClass)) {
+      return;  // malformed packet
     }
 
-    free(_buffer);
-    _buffer = NULL;
+    // Copy the QType and QClass
+    memcpy(&dnsQuestion.QType, enoflbls, sizeof(dnsQuestion.QType));
+    memcpy(&dnsQuestion.QClass, enoflbls + sizeof(dnsQuestion.QType), sizeof(dnsQuestion.QClass));
   }
+
+  // will reply with IP only to "*" or if domain matches without www. subdomain
+  if (dnsHeader.OPCode == DNS_OPCODE_QUERY && requestIncludesOnlyOneQuestion(dnsHeader)
+      && (_domainName.isEmpty() || getDomainNameWithoutWwwPrefix(static_cast<const unsigned char *>(dnsQuestion.QName), dnsQuestion.QNameLength) == _domainName)) {
+    replyWithIP(pkt, dnsHeader, dnsQuestion);
+    return;
+  }
+
+  // otherwise reply with custom code
+  replyWithCustomCode(pkt, dnsHeader);
 }
 
-bool DNSServer::requestIncludesOnlyOneQuestion()
-{
-  return ntohs(_dnsHeader->QDCount) == 1 &&
-         _dnsHeader->ANCount == 0 &&
-         _dnsHeader->NSCount == 0 &&
-         _dnsHeader->ARCount == 0;
+bool DNSServer::requestIncludesOnlyOneQuestion(DNSHeader &dnsHeader) {
+  return ntohs(dnsHeader.QDCount) == 1 && dnsHeader.ANCount == 0 && dnsHeader.NSCount == 0 && dnsHeader.ARCount == 0;
 }
 
-
-String DNSServer::getDomainNameWithoutWwwPrefix()
-{
-  // Error checking : if the buffer containing the DNS request is a null pointer, return an empty domain
-  String parsedDomainName = "";
-  if (_buffer == NULL) 
-    return parsedDomainName;
-  
-  // Set the start of the domain just after the header (12 bytes). If equal to null character, return an empty domain
-  unsigned char *start = _buffer + DNS_OFFSET_DOMAIN_NAME;
-  if (*start == 0)
-  {
-    return parsedDomainName;
-  }
+String DNSServer::getDomainNameWithoutWwwPrefix(const unsigned char *start, size_t len) {
+  String parsedDomainName(start, --len);  // exclude trailing null byte from labels length, String constructor will add it anyway
 
   int pos = 0;
-  while(true)
-  {
-    unsigned char labelLength = *(start + pos);
-    for(int i = 0; i < labelLength; i++)
-    {
-      pos++;
-      parsedDomainName += (char)*(start + pos);
-    }
-    pos++;
-    if (*(start + pos) == 0)
-    {
-      downcaseAndRemoveWwwPrefix(parsedDomainName);
-      return parsedDomainName;
-    }
-    else
-    {
-      parsedDomainName += ".";
-    }
+  while (pos < len) {
+    parsedDomainName.setCharAt(pos, 0x2e);  // replace label len byte with dot char "."
+    pos += *(start + pos);
+    ++pos;
   }
+  parsedDomainName.remove(0, 1);  // remove first "." char
+  downcaseAndRemoveWwwPrefix(parsedDomainName);
+  return parsedDomainName;
 }
 
-void DNSServer::replyWithIP()
-{
-  if (_buffer == NULL) return;
-  
-  _udp.beginPacket(_udp.remoteIP(), _udp.remotePort());
-  
-  // Change the type of message to a response and set the number of answers equal to 
+void DNSServer::replyWithIP(AsyncUDPPacket &req, DNSHeader &dnsHeader, DNSQuestion &dnsQuestion) {
+  AsyncUDPMessage rpl;
+
+  // Change the type of message to a response and set the number of answers equal to
   // the number of questions in the header
-  _dnsHeader->QR      = DNS_QR_RESPONSE;
-  _dnsHeader->ANCount = _dnsHeader->QDCount;
-  _udp.write( (unsigned char*) _dnsHeader, DNS_HEADER_SIZE ) ;
+  dnsHeader.QR = DNS_QR_RESPONSE;
+  dnsHeader.ANCount = dnsHeader.QDCount;
+  rpl.write((unsigned char *)&dnsHeader, DNS_HEADER_SIZE);
 
   // Write the question
-  _udp.write(_dnsQuestion->QName, _dnsQuestion->QNameLength) ;
-  _udp.write( (unsigned char*) &_dnsQuestion->QType, 2 ) ;
-  _udp.write( (unsigned char*) &_dnsQuestion->QClass, 2 ) ;
+  rpl.write(dnsQuestion.QName, dnsQuestion.QNameLength);
+  rpl.write((uint8_t *)&dnsQuestion.QType, 2);
+  rpl.write((uint8_t *)&dnsQuestion.QClass, 2);
 
-  // Write the answer 
-  // Use DNS name compression : instead of repeating the name in this RNAME occurence,
+  // Write the answer
+  // Use DNS name compression : instead of repeating the name in this RNAME occurrence,
   // set the two MSB of the byte corresponding normally to the length to 1. The following
-  // 14 bits must be used to specify the offset of the domain name in the message 
-  // (<255 here so the first byte has the 6 LSB at 0) 
-  _udp.write((uint8_t) 0xC0); 
-  _udp.write((uint8_t) DNS_OFFSET_DOMAIN_NAME);  
-
-  // DNS type A : host address, DNS class IN for INternet, returning an IPv4 address 
-  uint16_t answerType = htons(DNS_TYPE_A), answerClass = htons(DNS_CLASS_IN), answerIPv4 = htons(DNS_RDLENGTH_IPV4)  ; 
-  _udp.write((unsigned char*) &answerType, 2 );
-  _udp.write((unsigned char*) &answerClass, 2 );
-  _udp.write((unsigned char*) &_ttl, 4);        // DNS Time To Live
-  _udp.write((unsigned char*) &answerIPv4, 2 );
-  _udp.write(_resolvedIP, sizeof(_resolvedIP)); // The IP address to return
-  _udp.endPacket();
-
-  #ifdef DEBUG_ESP_DNS
-    DEBUG_OUTPUT.printf("DNS responds: %s for %s\n",
-            IPAddress(_resolvedIP).toString().c_str(), getDomainNameWithoutWwwPrefix().c_str() );
-  #endif  
+  // 14 bits must be used to specify the offset of the domain name in the message
+  // (<255 here so the first byte has the 6 LSB at 0)
+  rpl.write((uint8_t)0xC0);
+  rpl.write((uint8_t)DNS_OFFSET_DOMAIN_NAME);
+
+  // DNS type A : host address, DNS class IN for INternet, returning an IPv4 address
+  uint16_t answerType = htons(DNS_TYPE_A), answerClass = htons(DNS_CLASS_IN), answerIPv4 = htons(DNS_RDLENGTH_IPV4);
+  rpl.write((unsigned char *)&answerType, 2);
+  rpl.write((unsigned char *)&answerClass, 2);
+  rpl.write((unsigned char *)&_ttl, 4);  // DNS Time To Live
+  rpl.write((unsigned char *)&answerIPv4, 2);
+  uint32_t ip = _resolvedIP;
+  rpl.write(reinterpret_cast<uint8_t *>(&ip), sizeof(uint32_t));  // The IPv4 address to return
+
+  _udp.sendTo(rpl, req.remoteIP(), req.remotePort());
+
+#ifdef DEBUG_ESP_DNS
+  DEBUG_OUTPUT.printf(
+    "DNS responds: %s for %s\n", _resolvedIP.toString().c_str(),
+    getDomainNameWithoutWwwPrefix(static_cast<const unsigned char *>(dnsQuestion.QName), dnsQuestion.QNameLength).c_str()
+  );
+#endif
 }
 
-void DNSServer::replyWithCustomCode()
-{
-  if (_buffer == NULL) return;
-  _dnsHeader->QR = DNS_QR_RESPONSE;
-  _dnsHeader->RCode = (unsigned char)_errorReplyCode;
-  _dnsHeader->QDCount = 0;
+void DNSServer::replyWithCustomCode(AsyncUDPPacket &req, DNSHeader &dnsHeader) {
+  dnsHeader.QR = DNS_QR_RESPONSE;
+  dnsHeader.RCode = static_cast<uint16_t>(_errorReplyCode);
+  dnsHeader.QDCount = 0;
 
-  _udp.beginPacket(_udp.remoteIP(), _udp.remotePort());
-  _udp.write(_buffer, sizeof(DNSHeader));
-  _udp.endPacket();
+  AsyncUDPMessage rpl(sizeof(DNSHeader));
+  rpl.write(reinterpret_cast<const uint8_t *>(&dnsHeader), sizeof(DNSHeader));
+  _udp.sendTo(rpl, req.remoteIP(), req.remotePort());
 }
diff --git a/libraries/DNSServer/src/DNSServer.h b/libraries/DNSServer/src/DNSServer.h
index a10ef9eaaf1..dfd9a45604d 100644
--- a/libraries/DNSServer/src/DNSServer.h
+++ b/libraries/DNSServer/src/DNSServer.h
@@ -1,109 +1,183 @@
-#ifndef DNSServer_h
-#define DNSServer_h
-#include <WiFiUdp.h>
-
-#define DNS_QR_QUERY 0
-#define DNS_QR_RESPONSE 1
-#define DNS_OPCODE_QUERY 0
-#define DNS_DEFAULT_TTL 60        // Default Time To Live : time interval in seconds that the resource record should be cached before being discarded
-#define DNS_OFFSET_DOMAIN_NAME 12 // Offset in bytes to reach the domain name in the DNS message 
-#define DNS_HEADER_SIZE 12 
-
-enum class DNSReplyCode
-{
-  NoError   = 0,
+#pragma once
+#include <AsyncUDP.h>
+
+#define DNS_QR_QUERY           0
+#define DNS_QR_RESPONSE        1
+#define DNS_OPCODE_QUERY       0
+#define DNS_DEFAULT_TTL        60  // Default Time To Live : time interval in seconds that the resource record should be cached before being discarded
+#define DNS_HEADER_SIZE        12
+#define DNS_OFFSET_DOMAIN_NAME DNS_HEADER_SIZE  // Offset in bytes to reach the domain name labels in the DNS message
+#define DNS_DEFAULT_PORT       53
+
+enum class DNSReplyCode : uint16_t {
+  NoError = 0,
   FormError = 1,
-  ServerFailure     = 2,
+  ServerFailure = 2,
   NonExistentDomain = 3,
-  NotImplemented    = 4,
-  Refused   = 5,
-  YXDomain  = 6,
-  YXRRSet   = 7,
-  NXRRSet   = 8
+  NotImplemented = 4,
+  Refused = 5,
+  YXDomain = 6,
+  YXRRSet = 7,
+  NXRRSet = 8
+};
+
+enum DNSType {
+  DNS_TYPE_A = 1,      // Host Address
+  DNS_TYPE_AAAA = 28,  // IPv6 Address
+  DNS_TYPE_SOA = 6,    // Start Of a zone of Authority
+  DNS_TYPE_PTR = 12,   // Domain name PoinTeR
+  DNS_TYPE_DNAME = 39  // Delegation Name
 };
 
-enum DNSType
-{
-  DNS_TYPE_A      = 1,  // Host Address
-  DNS_TYPE_AAAA   = 28, // IPv6 Address
-  DNS_TYPE_SOA    = 6,  // Start Of a zone of Authority
-  DNS_TYPE_PTR    = 12, // Domain name PoinTeR
-  DNS_TYPE_DNAME  = 39  // Delegation Name
-} ; 
-
-enum DNSClass
-{
-  DNS_CLASS_IN = 1, // INternet
-  DNS_CLASS_CH = 3  // CHaos
-} ; 
-
-enum DNSRDLength
-{
-  DNS_RDLENGTH_IPV4 = 4 // 4 bytes for an IPv4 address 
-} ; 
-
-struct DNSHeader
-{
-  uint16_t ID;               // identification number
+enum DNSClass {
+  DNS_CLASS_IN = 1,  // INternet
+  DNS_CLASS_CH = 3   // CHaos
+};
+
+enum DNSRDLength {
+  DNS_RDLENGTH_IPV4 = 4  // 4 bytes for an IPv4 address
+};
+
+struct DNSHeader {
+  uint16_t ID;  // identification number
   union {
     struct {
-      uint16_t RD : 1;      // recursion desired
-      uint16_t TC : 1;      // truncated message
-      uint16_t AA : 1;      // authoritive answer
+      uint16_t RD     : 1;  // recursion desired
+      uint16_t TC     : 1;  // truncated message
+      uint16_t AA     : 1;  // authoritative answer
       uint16_t OPCode : 4;  // message_type
-      uint16_t QR : 1;      // query/response flag
-      uint16_t RCode : 4;   // response code
-      uint16_t Z : 3;       // its z! reserved
-      uint16_t RA : 1;      // recursion available
+      uint16_t QR     : 1;  // query/response flag
+      uint16_t RCode  : 4;  // response code
+      uint16_t Z      : 3;  // its z! reserved
+      uint16_t RA     : 1;  // recursion available
     };
     uint16_t Flags;
   };
-  uint16_t QDCount;          // number of question entries
-  uint16_t ANCount;          // number of answer entries
-  uint16_t NSCount;          // number of authority entries
-  uint16_t ARCount;          // number of resource entries
+  uint16_t QDCount;  // number of question entries
+  uint16_t ANCount;  // number of ANswer entries
+  uint16_t NSCount;  // number of authority entries
+  uint16_t ARCount;  // number of Additional Resource entries
+};
+
+struct DNSQuestion {
+  const uint8_t *QName;
+  uint16_t QNameLength;
+  uint16_t QType;
+  uint16_t QClass;
 };
 
-struct DNSQuestion
-{
-  uint8_t   QName[255] ;
-  int8_t    QNameLength ; 
-  uint16_t  QType ; 
-  uint16_t  QClass ; 
-} ; 
-
-class DNSServer
-{
-  public:
-    DNSServer();
-    void processNextRequest();
-    void setErrorReplyCode(const DNSReplyCode &replyCode);
-    void setTTL(const uint32_t &ttl);
-
-    // Returns true if successful, false if there are no sockets available
-    bool start(const uint16_t &port,
-              const String &domainName,
-              const IPAddress &resolvedIP);
-    // stops the DNS server
-    void stop();
-
-  private:
-    WiFiUDP _udp;
-    uint16_t _port;
-    String _domainName;
-    unsigned char _resolvedIP[4];
-    int _currentPacketSize;
-    unsigned char* _buffer;
-    DNSHeader* _dnsHeader;
-    uint32_t _ttl;
-    DNSReplyCode _errorReplyCode;
-    DNSQuestion*    _dnsQuestion ; 
-
-
-    void downcaseAndRemoveWwwPrefix(String &domainName);
-    String getDomainNameWithoutWwwPrefix();
-    bool requestIncludesOnlyOneQuestion();
-    void replyWithIP();
-    void replyWithCustomCode();
+class DNSServer {
+public:
+  /**
+     * @brief Construct a new DNSServer object
+     * by default server is configured to run in "Captive-portal" mode
+     * it must be started with start() call to establish a listening socket
+     *
+     */
+  DNSServer();
+
+  /**
+     * @brief Construct a new DNSServer object
+     * builds DNS server with default parameters
+     * @param domainName - domain name to serve
+     */
+  DNSServer(const String &domainName);
+  ~DNSServer(){};  // default d-tor
+
+  // Copy semantics not implemented (won't run on same UDP port anyway)
+  DNSServer(const DNSServer &) = delete;
+  DNSServer &operator=(const DNSServer &) = delete;
+
+  /**
+     * @brief stub, left for compatibility with an old version
+     * does nothing actually
+     *
+     */
+  void processNextRequest() {};
+
+  /**
+     * @brief Set the Error Reply Code for all req's not matching predefined domain
+     *
+     * @param replyCode
+     */
+  void setErrorReplyCode(const DNSReplyCode &replyCode);
+
+  /**
+     * @brief set TTL for successful replies
+     *
+     * @param ttl in seconds
+     */
+  void setTTL(const uint32_t &ttl);
+
+  /**
+     * @brief (re)Starts a server with current configuration or with default parameters
+     * if it's the first call.
+     * Defaults are:
+     * port: 53
+     * domainName: any
+     * ip: WiFi AP's IP address
+     *
+     * @return true on success
+     * @return false if IP or socket error
+     */
+  bool start();
+
+  /**
+     * @brief (re)Starts a server with provided configuration
+     *
+     * @return true on success
+     * @return false if IP or socket error
+     */
+  bool start(uint16_t port, const String &domainName, const IPAddress &resolvedIP);
+
+  /**
+     * @brief stops the server and close UDP socket
+     *
+     */
+  void stop();
+
+  /**
+     * @brief returns true if DNS server runs in captive-portal mode
+     * i.e. all requests are served with AP's ip address
+     *
+     * @return true if catch-all mode active
+     * @return false otherwise
+     */
+  inline bool isCaptive() const {
+    return _domainName.isEmpty();
+  };
+
+  /**
+     * @brief returns 'true' if server is up and UDP socket is listening for UDP req's
+     *
+     * @return true if server is up
+     * @return false otherwise
+     */
+  inline bool isUp() {
+    return _udp.connected();
+  };
+
+private:
+  AsyncUDP _udp;
+  uint16_t _port;
+  uint32_t _ttl;
+  DNSReplyCode _errorReplyCode;
+  String _domainName;
+  IPAddress _resolvedIP;
+
+  void downcaseAndRemoveWwwPrefix(String &domainName);
+
+  /**
+     * @brief Get the Domain Name Without Www Prefix object
+     * scan labels in DNS packet and build a string of a domain name
+     * truncate any www. label if found
+     * @param start a pointer to the start of labels records in DNS packet
+     * @param len labels length
+     * @return String
+     */
+  String getDomainNameWithoutWwwPrefix(const unsigned char *start, size_t len);
+  inline bool requestIncludesOnlyOneQuestion(DNSHeader &dnsHeader);
+  void replyWithIP(AsyncUDPPacket &req, DNSHeader &dnsHeader, DNSQuestion &dnsQuestion);
+  inline void replyWithCustomCode(AsyncUDPPacket &req, DNSHeader &dnsHeader);
+  void _handleUDP(AsyncUDPPacket &pkt);
 };
-#endif
\ No newline at end of file
diff --git a/libraries/EEPROM/README.md b/libraries/EEPROM/README.md
index 896ca5b3019..577e2ea4eae 100644
--- a/libraries/EEPROM/README.md
+++ b/libraries/EEPROM/README.md
@@ -1,4 +1,4 @@
 ## EEPROM
 
-EEPROM is deprecated.  For new applications on ESP32, use Preferences.  EEPROM is provided for backwards compatibility with existing Arduino applications.
-EEPROM is implemented using a single blob within NVS, so it is a container within a container. As such, it is not going to be a high performance storage method.  Preferences will directly use nvs, and store each entry as a single object therein.
+EEPROM is deprecated. For new applications on ESP32, use Preferences. EEPROM is provided for backwards compatibility with existing Arduino applications.
+EEPROM is implemented using a single blob within NVS, so it is a container within a container. As such, it is not going to be a high performance storage method. Preferences will directly use nvs, and store each entry as a single object therein.
diff --git a/libraries/EEPROM/examples/eeprom_class/eeprom_class.ino b/libraries/EEPROM/examples/eeprom_class/eeprom_class.ino
index 686f09d979e..386360ac6b3 100644
--- a/libraries/EEPROM/examples/eeprom_class/eeprom_class.ino
+++ b/libraries/EEPROM/examples/eeprom_class/eeprom_class.ino
@@ -2,7 +2,7 @@
   ESP32 eeprom_class example with EEPROM library
   This simple example demonstrates using EEPROM library to store different data in
   ESP32 Flash memory in a multiple user-defined EEPROM class objects.
-  
+
   Created for arduino-esp32 on 25 Dec, 2017
   by Elochukwu Ifediora (fedy0)
   converted to nvs by lbernstone - 06/22/2019
@@ -11,34 +11,34 @@
 #include "EEPROM.h"
 
 // Instantiate eeprom objects with parameter/argument names and sizes
-EEPROMClass  NAMES("eeprom0", 0x500);
-EEPROMClass  HEIGHT("eeprom1", 0x200);
-EEPROMClass  AGE("eeprom2", 0x100);
+EEPROMClass NAMES("eeprom0");
+EEPROMClass HEIGHT("eeprom1");
+EEPROMClass AGE("eeprom2");
 
 void setup() {
   Serial.begin(115200);
   delay(1000);
   Serial.println("Testing EEPROMClass\n");
-  if (!NAMES.begin(NAMES.length())) {
-    Serial.println("Failed to initialise NAMES");
+  if (!NAMES.begin(0x500)) {
+    Serial.println("Failed to initialize NAMES");
     Serial.println("Restarting...");
     delay(1000);
     ESP.restart();
   }
-  if (!HEIGHT.begin(HEIGHT.length())) {
-    Serial.println("Failed to initialise HEIGHT");
+  if (!HEIGHT.begin(0x200)) {
+    Serial.println("Failed to initialize HEIGHT");
     Serial.println("Restarting...");
     delay(1000);
     ESP.restart();
   }
-  if (!AGE.begin(AGE.length())) {
-    Serial.println("Failed to initialise AGE");
+  if (!AGE.begin(0x100)) {
+    Serial.println("Failed to initialize AGE");
     Serial.println("Restarting...");
     delay(1000);
     ESP.restart();
   }
 
-  const char* name = "Teo Swee Ann";
+  const char *name = "Teo Swee Ann";
   char rname[32];
   double height = 5.8;
   uint32_t age = 47;
@@ -47,28 +47,37 @@ void setup() {
   NAMES.writeString(0, name);
   HEIGHT.put(0, height);
   AGE.put(0, age);
-  Serial.print("name: ");   Serial.println(name);
-  Serial.print("height: "); Serial.println(height);
-  Serial.print("age: ");    Serial.println(age);
+  Serial.print("name: ");
+  Serial.println(name);
+  Serial.print("height: ");
+  Serial.println(height);
+  Serial.print("age: ");
+  Serial.println(age);
   Serial.println("------------------------------------\n");
 
   // Clear variables
-  name = '\0';
+  rname[0] = '\0';
   height = 0;
   age = 0;
-  Serial.print("name: ");   Serial.println(name);
-  Serial.print("height: "); Serial.println(height);
-  Serial.print("age: ");    Serial.println(age);
+  Serial.print("name: ");
+  Serial.println(rname);
+  Serial.print("height: ");
+  Serial.println(height);
+  Serial.print("age: ");
+  Serial.println(age);
   Serial.println("------------------------------------\n");
 
   // Read: Variables <--- EEPROM stores
   NAMES.get(0, rname);
   HEIGHT.get(0, height);
   AGE.get(0, age);
-  Serial.print("name: ");   Serial.println(rname);
-  Serial.print("height: "); Serial.println(height);
-  Serial.print("age: ");    Serial.println(age);
-  
+  Serial.print("name: ");
+  Serial.println(rname);
+  Serial.print("height: ");
+  Serial.println(height);
+  Serial.print("age: ");
+  Serial.println(age);
+
   Serial.println("Done!");
 }
 
diff --git a/libraries/EEPROM/examples/eeprom_extra/eeprom_extra.ino b/libraries/EEPROM/examples/eeprom_extra/eeprom_extra.ino
index 5ae01fb2268..78e8b269f96 100644
--- a/libraries/EEPROM/examples/eeprom_extra/eeprom_extra.ino
+++ b/libraries/EEPROM/examples/eeprom_extra/eeprom_extra.ino
@@ -14,7 +14,7 @@ void setup() {
   Serial.begin(115200);
   Serial.println("\nTesting EEPROM Library\n");
   if (!EEPROM.begin(1000)) {
-    Serial.println("Failed to initialise EEPROM");
+    Serial.println("Failed to initialize EEPROM");
     Serial.println("Restarting...");
     delay(1000);
     ESP.restart();
@@ -22,38 +22,38 @@ void setup() {
 
   int address = 0;
 
-  EEPROM.writeByte(address, -128);                  // -2^7
+  EEPROM.writeByte(address, -128);  // -2^7
   address += sizeof(byte);
 
-  EEPROM.writeChar(address, 'A');                   // Same as writyByte and readByte
+  EEPROM.writeChar(address, 'A');  // Same as writyByte and readByte
   address += sizeof(char);
 
-  EEPROM.writeUChar(address, 255);                  // 2^8 - 1
+  EEPROM.writeUChar(address, 255);  // 2^8 - 1
   address += sizeof(unsigned char);
 
-  EEPROM.writeShort(address, -32768);               // -2^15
+  EEPROM.writeShort(address, -32768);  // -2^15
   address += sizeof(short);
 
-  EEPROM.writeUShort(address, 65535);               // 2^16 - 1
+  EEPROM.writeUShort(address, 65535);  // 2^16 - 1
   address += sizeof(unsigned short);
 
-  EEPROM.writeInt(address, -2147483648);            // -2^31
+  EEPROM.writeInt(address, -2147483648);  // -2^31
   address += sizeof(int);
 
-  EEPROM.writeUInt(address, 4294967295);            // 2^32 - 1
+  EEPROM.writeUInt(address, 4294967295);  // 2^32 - 1
   address += sizeof(unsigned int);
 
-  EEPROM.writeLong(address, -2147483648);           // Same as writeInt and readInt
+  EEPROM.writeLong(address, -2147483648);  // Same as writeInt and readInt
   address += sizeof(long);
 
-  EEPROM.writeULong(address, 4294967295);           // Same as writeUInt and readUInt
+  EEPROM.writeULong(address, 4294967295);  // Same as writeUInt and readUInt
   address += sizeof(unsigned long);
 
-  int64_t value = -1223372036854775808LL;             // -2^63
+  int64_t value = -1223372036854775808LL;  // -2^63
   EEPROM.writeLong64(address, value);
   address += sizeof(int64_t);
 
-  uint64_t  Value = 18446744073709551615ULL;           // 2^64 - 1
+  uint64_t Value = 18446744073709551615ULL;  // 2^64 - 1
   EEPROM.writeULong64(address, Value);
   address += sizeof(uint64_t);
 
@@ -77,7 +77,7 @@ void setup() {
   // See also the general purpose writeBytes() and readBytes() for BLOB in EEPROM library
   EEPROM.commit();
   address = 0;
-  
+
   Serial.println(EEPROM.readByte(address));
   address += sizeof(byte);
 
@@ -107,14 +107,14 @@ void setup() {
 
   value = 0;
   value = EEPROM.readLong64(value);
-  Serial.printf("0x%08X", (uint32_t)(value >> 32)); // Print High 4 bytes in HEX
-  Serial.printf("%08X\n", (uint32_t)value);         // Print Low 4 bytes in HEX
+  Serial.printf("0x%08lX", (uint32_t)(value >> 32));  // Print High 4 bytes in HEX
+  Serial.printf("%08lX\n", (uint32_t)value);          // Print Low 4 bytes in HEX
   address += sizeof(int64_t);
 
-  Value = 0;                                        // Clear Value
+  Value = 0;  // Clear Value
   Value = EEPROM.readULong64(Value);
-  Serial.printf("0x%08X", (uint32_t)(Value >> 32)); // Print High 4 bytes in HEX
-  Serial.printf("%08X\n", (uint32_t)Value);         // Print Low 4 bytes in HEX
+  Serial.printf("0x%08lX", (uint32_t)(Value >> 32));  // Print High 4 bytes in HEX
+  Serial.printf("%08lX\n", (uint32_t)Value);          // Print Low 4 bytes in HEX
   address += sizeof(uint64_t);
 
   Serial.println(EEPROM.readFloat(address), 4);
@@ -135,5 +135,4 @@ void setup() {
 
 void loop() {
   // put your main code here, to run repeatedly:
-
 }
diff --git a/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino b/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino
index a4dbb8c3867..b93146793b0 100644
--- a/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino
+++ b/libraries/EEPROM/examples/eeprom_write/eeprom_write.ino
@@ -12,25 +12,23 @@
 // we're going to write to next)
 int addr = 0;
 #define EEPROM_SIZE 64
-void setup()
-{
+void setup() {
   Serial.begin(115200);
   Serial.println("start...");
-  if (!EEPROM.begin(EEPROM_SIZE))
-  {
-    Serial.println("failed to initialise EEPROM"); delay(1000000);
+  if (!EEPROM.begin(EEPROM_SIZE)) {
+    Serial.println("failed to initialize EEPROM");
+    delay(1000000);
   }
   Serial.println(" bytes read from Flash . Values are:");
-  for (int i = 0; i < EEPROM_SIZE; i++)
-  {
-    Serial.print(byte(EEPROM.read(i))); Serial.print(" ");
+  for (int i = 0; i < EEPROM_SIZE; i++) {
+    Serial.print(byte(EEPROM.read(i)));
+    Serial.print(" ");
   }
   Serial.println();
   Serial.println("writing random n. in memory");
 }
 
-void loop()
-{
+void loop() {
   // need to divide by 4 because analog inputs range from
   // 0 to 1023 and each byte of the EEPROM can only hold a
   // value from 0 to 255.
@@ -40,23 +38,24 @@ void loop()
   // these values will remain there when the board is
   // turned off.
   EEPROM.write(addr, val);
-  Serial.print(val); Serial.print(" ");
+  Serial.print(val);
+  Serial.print(" ");
   // advance to the next address.  there are 512 bytes in
   // the EEPROM, so go back to 0 when we hit 512.
   // save all changes to the flash.
   addr = addr + 1;
-  if (addr == EEPROM_SIZE)
-  {
+  if (addr == EEPROM_SIZE) {
     Serial.println();
     addr = 0;
     EEPROM.commit();
     Serial.print(EEPROM_SIZE);
     Serial.println(" bytes written on Flash . Values are:");
-    for (int i = 0; i < EEPROM_SIZE; i++)
-    {
-      Serial.print(byte(EEPROM.read(i))); Serial.print(" ");
+    for (int i = 0; i < EEPROM_SIZE; i++) {
+      Serial.print(byte(EEPROM.read(i)));
+      Serial.print(" ");
     }
-    Serial.println(); Serial.println("----------------------------------");
+    Serial.println();
+    Serial.println("----------------------------------");
   }
 
   delay(100);
diff --git a/libraries/EEPROM/keywords.txt b/libraries/EEPROM/keywords.txt
index 0e2552e12c4..d14b49729f8 100644
--- a/libraries/EEPROM/keywords.txt
+++ b/libraries/EEPROM/keywords.txt
@@ -16,4 +16,3 @@ EEPROMClass	KEYWORD1
 #######################################
 # Constants (LITERAL1)
 #######################################
-
diff --git a/libraries/EEPROM/library.properties b/libraries/EEPROM/library.properties
index e65520588de..c7e48501c04 100644
--- a/libraries/EEPROM/library.properties
+++ b/libraries/EEPROM/library.properties
@@ -1,5 +1,5 @@
 name=EEPROM
-version=1.0.3
+version=3.2.0
 author=Ivan Grokhotkov
 maintainer=Paolo Becchi <pbecchi@aerobusiness.it>
 sentence=Enables reading and writing data a sequential, addressable FLASH storage
diff --git a/libraries/EEPROM/src/EEPROM.cpp b/libraries/EEPROM/src/EEPROM.cpp
index 7f4ab090f1f..016e6843dd2 100644
--- a/libraries/EEPROM/src/EEPROM.cpp
+++ b/libraries/EEPROM/src/EEPROM.cpp
@@ -28,36 +28,13 @@
 #include <esp_partition.h>
 #include <esp_log.h>
 
-EEPROMClass::EEPROMClass(void)
-  : _handle(0)
-  , _data(0)
-  , _size(0)
-  , _dirty(false)
-  , _name("eeprom")
-  , _user_defined_size(0)
-{
-}
+EEPROMClass::EEPROMClass(void) : _handle(0), _data(0), _size(0), _dirty(false), _name("eeprom") {}
 
 EEPROMClass::EEPROMClass(uint32_t sector)
-// Only for compatiility, no sectors in nvs!
-  : _handle(0)
-  , _data(0)
-  , _size(0)
-  , _dirty(false)
-  , _name("eeprom")
-  , _user_defined_size(0)
-{
-}
-
-EEPROMClass::EEPROMClass(const char* name, uint32_t user_defined_size)
-  : _handle(0)
-  , _data(0)
-  , _size(0)
-  , _dirty(false)
-  , _name(name)
-  , _user_defined_size(user_defined_size)
-{
-}
+  // Only for compatiility, no sectors in nvs!
+  : _handle(0), _data(0), _size(0), _dirty(false), _name("eeprom") {}
+
+EEPROMClass::EEPROMClass(const char *name) : _handle(0), _data(0), _size(0), _dirty(false), _name(name) {}
 
 EEPROMClass::~EEPROMClass() {
   end();
@@ -65,75 +42,74 @@ EEPROMClass::~EEPROMClass() {
 
 bool EEPROMClass::begin(size_t size) {
   if (!size) {
-      return false;
+    return false;
   }
 
   esp_err_t res = nvs_open(_name, NVS_READWRITE, &_handle);
   if (res != ESP_OK) {
-      log_e("Unable to open NVS namespace: %d", res);
-      return false;
+    log_e("Unable to open NVS namespace: %d", res);
+    return false;
   }
 
   size_t key_size = 0;
   res = nvs_get_blob(_handle, _name, NULL, &key_size);
-  if(res != ESP_OK && res != ESP_ERR_NVS_NOT_FOUND) {
-      log_e("Unable to read NVS key: %d", res);
-      return false;
+  if (res != ESP_OK && res != ESP_ERR_NVS_NOT_FOUND) {
+    log_e("Unable to read NVS key: %d", res);
+    return false;
   }
-  if (size < key_size) { // truncate
-      log_w("truncating EEPROM from %d to %d", key_size, size);
-      uint8_t* key_data = (uint8_t*) malloc(key_size);
-      if(!key_data) {
-         log_e("Not enough memory to truncate EEPROM!");
-         return false;
-      }
-      nvs_get_blob(_handle, _name, key_data, &key_size);
-      nvs_set_blob(_handle, _name, key_data, size);
-      nvs_commit(_handle);
-      free(key_data);
-  }
-  else if (size > key_size) { // expand or new
-      size_t expand_size = size - key_size;
-      uint8_t* expand_key = (uint8_t*) malloc(expand_size);
-      if(!expand_key) {
-         log_e("Not enough memory to expand EEPROM!");
-         return false;
-      }
-      // check for adequate free space
-      if(nvs_set_blob(_handle, "expand", expand_key, expand_size)) {
-        log_e("Not enough space to expand EEPROM from %d to %d", key_size, size);
-        free(expand_key);
-        return false;
-      }
+  if (size < key_size) {  // truncate
+    log_w("truncating EEPROM from %d to %d", key_size, size);
+    uint8_t *key_data = (uint8_t *)malloc(key_size);
+    if (!key_data) {
+      log_e("Not enough memory to truncate EEPROM!");
+      return false;
+    }
+    nvs_get_blob(_handle, _name, key_data, &key_size);
+    nvs_set_blob(_handle, _name, key_data, size);
+    nvs_commit(_handle);
+    free(key_data);
+  } else if (size > key_size) {  // expand or new
+    size_t expand_size = size - key_size;
+    uint8_t *expand_key = (uint8_t *)malloc(expand_size);
+    if (!expand_key) {
+      log_e("Not enough memory to expand EEPROM!");
+      return false;
+    }
+    // check for adequate free space
+    if (nvs_set_blob(_handle, "expand", expand_key, expand_size)) {
+      log_e("Not enough space to expand EEPROM from %d to %d", key_size, size);
       free(expand_key);
-      nvs_erase_key(_handle, "expand");
-      uint8_t* key_data = (uint8_t*) malloc(size);
-      if(!key_data) {
-         log_e("Not enough memory to expand EEPROM!");
-         return false;
-      }
-      memset(key_data, 0xFF, size);
-      if(key_size) {
-        log_i("Expanding EEPROM from %d to %d", key_size, size);
-	// hold data while key is deleted
-        nvs_get_blob(_handle, _name, key_data, &key_size);
-        nvs_erase_key(_handle, _name);
-      } else {
-        log_i("New EEPROM of %d bytes", size);
-      }
-      nvs_commit(_handle);
-      nvs_set_blob(_handle, _name, key_data, size);
-      free(key_data);
-      nvs_commit(_handle);
+      return false;
+    }
+    free(expand_key);
+    nvs_erase_key(_handle, "expand");
+    uint8_t *key_data = (uint8_t *)malloc(size);
+    if (!key_data) {
+      log_e("Not enough memory to expand EEPROM!");
+      return false;
+    }
+    memset(key_data, 0xFF, size);
+    if (key_size) {
+      log_i("Expanding EEPROM from %d to %d", key_size, size);
+      // hold data while key is deleted
+      nvs_get_blob(_handle, _name, key_data, &key_size);
+      nvs_erase_key(_handle, _name);
+    } else {
+      log_i("New EEPROM of %d bytes", size);
+    }
+    nvs_commit(_handle);
+    nvs_set_blob(_handle, _name, key_data, size);
+    free(key_data);
+    nvs_commit(_handle);
   }
 
   if (_data) {
     delete[] _data;
   }
 
-  _data = (uint8_t*) malloc(size);
-  if(!_data) {
-    log_e("Not enough memory for %d bytes in EEPROM");
+  _data = (uint8_t *)malloc(size);
+  if (!_data) {
+    log_e("Not enough memory for %d bytes in EEPROM", size);
     return false;
   }
   _size = size;
@@ -157,6 +133,10 @@ void EEPROMClass::end() {
   _handle = 0;
 }
 
+bool EEPROMClass::isDirty() {
+  return _dirty;
+}
+
 uint8_t EEPROMClass::read(int address) {
   if (address < 0 || (size_t)address >= _size) {
     return 0;
@@ -169,15 +149,16 @@ uint8_t EEPROMClass::read(int address) {
 }
 
 void EEPROMClass::write(int address, uint8_t value) {
-  if (address < 0 || (size_t)address >= _size)
+  if (address < 0 || (size_t)address >= _size) {
     return;
-  if (!_data)
+  }
+  if (!_data) {
     return;
+  }
 
-  // Optimise _dirty. Only flagged if data written is different.
-  uint8_t* pData = &_data[address];
-  if (*pData != value)
-  {
+  // Optimize _dirty. Only flagged if data written is different.
+  uint8_t *pData = &_data[address];
+  if (*pData != value) {
     *pData = value;
     _dirty = true;
   }
@@ -186,26 +167,27 @@ void EEPROMClass::write(int address, uint8_t value) {
 bool EEPROMClass::commit() {
   bool ret = false;
   if (!_size) {
-      return false;
+    return false;
   }
   if (!_data) {
-      return false;
+    return false;
   }
   if (!_dirty) {
-      return true;
+    return true;
   }
 
-  if (ESP_OK != nvs_set_blob(_handle, _name, _data, _size)) {
-      log_e( "error in write");
+  esp_err_t err = nvs_set_blob(_handle, _name, _data, _size);
+  if (err != ESP_OK) {
+    log_e("error in write: %s", esp_err_to_name(err));
   } else {
-      _dirty = false;
-      ret = true;
+    _dirty = false;
+    ret = true;
   }
 
   return ret;
 }
 
-uint8_t * EEPROMClass::getDataPtr() {
+uint8_t *EEPROMClass::getDataPtr() {
   _dirty = true;
   return &_data[0];
 }
@@ -213,39 +195,37 @@ uint8_t * EEPROMClass::getDataPtr() {
 /*
    Get EEPROM total size in byte defined by the user
 */
-uint16_t EEPROMClass::length ()
-{
-  return _user_defined_size;
+uint16_t EEPROMClass::length() {
+  return _size;
 }
 
-/* 
+/*
    Convert EEPROM partition into nvs blob
    Call convert before you call begin
 */
-uint16_t EEPROMClass::convert (bool clear, const char* EEPROMname, const char* nvsname)
-{
+uint16_t EEPROMClass::convert(bool clear, const char *EEPROMname, const char *nvsname) {
   uint16_t result = 0;
-  const esp_partition_t* mypart = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, EEPROMname);
+  const esp_partition_t *mypart = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, EEPROMname);
   if (mypart == NULL) {
     log_i("EEPROM partition not found for conversion");
     return result;
   }
 
   size_t size = mypart->size;
-  uint8_t* data = (uint8_t*) malloc(size);
+  uint8_t *data = (uint8_t *)malloc(size);
   if (!data) {
     log_e("Not enough memory to convert EEPROM!");
     goto exit;
   }
 
-  if (esp_partition_read (mypart, 0, (void *) data, size) != ESP_OK) {
+  if (esp_partition_read(mypart, 0, (void *)data, size) != ESP_OK) {
     log_e("Unable to read EEPROM partition");
     goto exit;
   }
 
   bool empty;
   empty = true;
-  for (int x=0; x<size; x++) {
+  for (int x = 0; x < size; x++) {
     if (data[x] != 0xFF) {
       empty = false;
       break;
@@ -268,12 +248,12 @@ uint16_t EEPROMClass::convert (bool clear, const char* EEPROMname, const char* n
     goto exit;
   }
   result = size;
- 
+
   if (clear) {
-    if (esp_partition_erase_range (mypart, 0, size) != ESP_OK) {
+    if (esp_partition_erase_range(mypart, 0, size) != ESP_OK) {
       log_w("Unable to clear EEPROM partition");
     }
-  } 
+  }
 exit:
   free(data);
   return result;
@@ -282,274 +262,262 @@ uint16_t EEPROMClass::convert (bool clear, const char* EEPROMname, const char* n
 /*
    Read 'value' from 'address'
 */
-uint8_t EEPROMClass::readByte (int address)
-{
+uint8_t EEPROMClass::readByte(int address) {
   uint8_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-int8_t EEPROMClass::readChar (int address)
-{
+int8_t EEPROMClass::readChar(int address) {
   int8_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-uint8_t EEPROMClass::readUChar (int address)
-{
+uint8_t EEPROMClass::readUChar(int address) {
   uint8_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-int16_t EEPROMClass::readShort (int address)
-{
+int16_t EEPROMClass::readShort(int address) {
   int16_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-uint16_t EEPROMClass::readUShort (int address)
-{
+uint16_t EEPROMClass::readUShort(int address) {
   uint16_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-int32_t EEPROMClass::readInt (int address)
-{
+int32_t EEPROMClass::readInt(int address) {
   int32_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-uint32_t EEPROMClass::readUInt (int address)
-{
+uint32_t EEPROMClass::readUInt(int address) {
   uint32_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-int32_t EEPROMClass::readLong (int address)
-{
+int32_t EEPROMClass::readLong(int address) {
   int32_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-uint32_t EEPROMClass::readULong (int address)
-{
+uint32_t EEPROMClass::readULong(int address) {
   uint32_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-int64_t EEPROMClass::readLong64 (int address)
-{
+int64_t EEPROMClass::readLong64(int address) {
   int64_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-uint64_t EEPROMClass::readULong64 (int address)
-{
+uint64_t EEPROMClass::readULong64(int address) {
   uint64_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-float_t EEPROMClass::readFloat (int address)
-{
+float_t EEPROMClass::readFloat(int address) {
   float_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-double_t EEPROMClass::readDouble (int address)
-{
+double_t EEPROMClass::readDouble(int address) {
   double_t value = 0;
-  return EEPROMClass::readAll (address, value);
+  return EEPROMClass::readAll(address, value);
 }
 
-bool EEPROMClass::readBool (int address)
-{
+bool EEPROMClass::readBool(int address) {
   int8_t value = 0;
-  return EEPROMClass::readAll (address, value) ? 1 : 0;
+  return EEPROMClass::readAll(address, value) ? 1 : 0;
 }
 
-size_t EEPROMClass::readString (int address, char* value, size_t maxLen)
-{
-  if (!value)
+size_t EEPROMClass::readString(int address, char *value, size_t maxLen) {
+  if (!value) {
     return 0;
+  }
 
-  if (address < 0 || address + maxLen > _size)
+  if (address < 0 || address + maxLen > _size) {
     return 0;
+  }
 
   uint16_t len;
-  for (len = 0; len <= _size; len++)
-    if (_data[address + len] == 0)
+  for (len = 0; len <= _size; len++) {
+    if (_data[address + len] == 0) {
       break;
+    }
+  }
 
-  if (address + len > _size)
+  if (address + len > _size) {
     return 0;
+  }
 
-  memcpy((uint8_t*) value, _data + address, len);
+  if (len > maxLen) {
+    return 0;  //Maybe return part of the string instead?
+  }
+
+  memcpy((uint8_t *)value, _data + address, len);
   value[len] = 0;
   return len;
 }
 
-String EEPROMClass::readString (int address)
-{
-  if (address < 0 || address > _size)
+String EEPROMClass::readString(int address) {
+  if (address < 0 || address > _size) {
     return String();
+  }
 
   uint16_t len;
-  for (len = 0; len <= _size; len++)
-    if (_data[address + len] == 0)
+  for (len = 0; len <= _size; len++) {
+    if (_data[address + len] == 0) {
       break;
+    }
+  }
 
-  if (address + len > _size)
+  if (address + len > _size) {
     return String();
+  }
 
-  char value[len];
-  memcpy((uint8_t*) value, _data + address, len);
+  char value[len + 1];
+  memcpy((uint8_t *)value, _data + address, len);
   value[len] = 0;
   return String(value);
 }
 
-size_t EEPROMClass::readBytes (int address, void* value, size_t maxLen)
-{
-  if (!value || !maxLen)
+size_t EEPROMClass::readBytes(int address, void *value, size_t maxLen) {
+  if (!value || !maxLen) {
     return 0;
+  }
 
-  if (address < 0 || address + maxLen > _size)
+  if (address < 0 || address + maxLen > _size) {
     return 0;
+  }
 
-  memcpy((void*) value, _data + address, maxLen);
+  memcpy((void *)value, _data + address, maxLen);
   return maxLen;
 }
 
-template <class T> T EEPROMClass::readAll (int address, T &value)
-{
-  if (address < 0 || address + sizeof(T) > _size)
+template<class T> T EEPROMClass::readAll(int address, T &value) {
+  if (address < 0 || address + sizeof(T) > _size) {
     return value;
+  }
 
-  memcpy((uint8_t*) &value, _data + address, sizeof(T));
+  memcpy((uint8_t *)&value, _data + address, sizeof(T));
   return value;
 }
 
 /*
    Write 'value' to 'address'
 */
-size_t EEPROMClass::writeByte (int address, uint8_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeByte(int address, uint8_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeChar (int address, int8_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeChar(int address, int8_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeUChar (int address, uint8_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeUChar(int address, uint8_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeShort (int address, int16_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeShort(int address, int16_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeUShort (int address, uint16_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeUShort(int address, uint16_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeInt (int address, int32_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeInt(int address, int32_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeUInt (int address, uint32_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeUInt(int address, uint32_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeLong (int address, int32_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeLong(int address, int32_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeULong (int address, uint32_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeULong(int address, uint32_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeLong64 (int address, int64_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeLong64(int address, int64_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeULong64 (int address, uint64_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeULong64(int address, uint64_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeFloat (int address, float_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeFloat(int address, float_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeDouble (int address, double_t value)
-{
-  return EEPROMClass::writeAll (address, value);
+size_t EEPROMClass::writeDouble(int address, double_t value) {
+  return EEPROMClass::writeAll(address, value);
 }
 
-size_t EEPROMClass::writeBool (int address, bool value)
-{
+size_t EEPROMClass::writeBool(int address, bool value) {
   int8_t Bool;
   value ? Bool = 1 : Bool = 0;
-  return EEPROMClass::writeAll (address, Bool);
+  return EEPROMClass::writeAll(address, Bool);
 }
 
-size_t EEPROMClass::writeString (int address, const char* value)
-{
-  if (!value)
+size_t EEPROMClass::writeString(int address, const char *value) {
+  if (!value) {
     return 0;
+  }
 
-  if (address < 0 || address > _size)
+  if (address < 0 || address > _size) {
     return 0;
+  }
 
   uint16_t len;
-  for (len = 0; len <= _size; len++)
-    if (value[len] == 0)
+  for (len = 0; len <= _size; len++) {
+    if (value[len] == 0) {
       break;
+    }
+  }
 
-  if (address + len > _size)
+  if (address + len > _size) {
     return 0;
+  }
 
-  memcpy(_data + address, (const uint8_t*) value, len + 1);
+  memcpy(_data + address, (const uint8_t *)value, len + 1);
   _dirty = true;
   return strlen(value);
 }
 
-size_t EEPROMClass::writeString (int address, String value)
-{
-  return EEPROMClass::writeString (address, value.c_str());
+size_t EEPROMClass::writeString(int address, String value) {
+  return EEPROMClass::writeString(address, value.c_str());
 }
 
-size_t EEPROMClass::writeBytes (int address, const void* value, size_t len)
-{
-  if (!value || !len)
+size_t EEPROMClass::writeBytes(int address, const void *value, size_t len) {
+  if (!value || !len) {
     return 0;
+  }
 
-  if (address < 0 || address + len > _size)
+  if (address < 0 || address + len > _size) {
     return 0;
+  }
 
-  memcpy(_data + address, (const void*) value, len);
+  memcpy(_data + address, (const void *)value, len);
   _dirty = true;
   return len;
 }
 
-template <class T> T EEPROMClass::writeAll (int address, const T &value)
-{
-  if (address < 0 || address + sizeof(T) > _size)
+template<class T> T EEPROMClass::writeAll(int address, const T &value) {
+  if (address < 0 || address + sizeof(T) > _size) {
     return value;
+  }
 
-  memcpy(_data + address, (const uint8_t*) &value, sizeof(T));
+  memcpy(_data + address, (const uint8_t *)&value, sizeof(T));
   _dirty = true;
 
-  return sizeof (value);
+  return sizeof(value);
 }
 
 #if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_EEPROM)
diff --git a/libraries/EEPROM/src/EEPROM.h b/libraries/EEPROM/src/EEPROM.h
index 032e1f65f86..2bcc97a3a21 100644
--- a/libraries/EEPROM/src/EEPROM.h
+++ b/libraries/EEPROM/src/EEPROM.h
@@ -33,86 +33,86 @@
 typedef uint32_t nvs_handle;
 
 class EEPROMClass {
-  public:
-    EEPROMClass(uint32_t sector);
-    EEPROMClass(const char* name, uint32_t user_defined_size);
-    EEPROMClass(void);
-    ~EEPROMClass(void);
-
-    bool begin(size_t size);
-    uint8_t read(int address);
-    void write(int address, uint8_t val);
-    uint16_t length();
-    bool commit();
-    void end();
-
-    uint8_t * getDataPtr();
-    uint16_t convert(bool clear, const char* EEPROMname = "eeprom", const char* nvsname = "eeprom");
-
-    template<typename T>
-    T &get(int address, T &t) {
-      if (address < 0 || address + sizeof(T) > _size)
-        return t;
-
-      memcpy((uint8_t*) &t, _data + address, sizeof(T));
+public:
+  EEPROMClass(uint32_t sector);
+  EEPROMClass(const char *name);
+  EEPROMClass(void);
+  ~EEPROMClass(void);
+
+  bool begin(size_t size);
+  uint8_t read(int address);
+  void write(int address, uint8_t val);
+  uint16_t length();
+  bool commit();
+  void end();
+  bool isDirty();
+
+  uint8_t *getDataPtr();
+  uint16_t convert(bool clear, const char *EEPROMname = "eeprom", const char *nvsname = "eeprom");
+
+  template<typename T> T &get(int address, T &t) {
+    if (address < 0 || address + sizeof(T) > _size) {
       return t;
     }
 
-    template<typename T>
-    const T &put(int address, const T &t) {
-      if (address < 0 || address + sizeof(T) > _size)
-        return t;
+    memcpy((uint8_t *)&t, _data + address, sizeof(T));
+    return t;
+  }
 
-      memcpy(_data + address, (const uint8_t*) &t, sizeof(T));
-      _dirty = true;
+  template<typename T> const T &put(int address, const T &t) {
+    if (address < 0 || address + sizeof(T) > _size) {
       return t;
     }
 
-    uint8_t readByte(int address);
-    int8_t readChar(int address);
-    uint8_t readUChar(int address);
-    int16_t readShort(int address);
-    uint16_t readUShort(int address);
-    int32_t readInt(int address);
-    uint32_t readUInt(int address);
-    int32_t readLong(int address);
-    uint32_t readULong(int address);
-    int64_t readLong64(int address);
-    uint64_t readULong64(int address);
-    float_t readFloat(int address);
-    double_t readDouble(int address);
-    bool readBool(int address);
-    size_t readString(int address, char* value, size_t maxLen);
-    String readString(int address);
-    size_t readBytes(int address, void * value, size_t maxLen);
-    template <class T> T readAll (int address, T &);
-
-    size_t writeByte(int address, uint8_t value);
-    size_t writeChar(int address, int8_t value);
-    size_t writeUChar(int address, uint8_t value);
-    size_t writeShort(int address, int16_t value);
-    size_t writeUShort(int address, uint16_t value);
-    size_t writeInt(int address, int32_t value);
-    size_t writeUInt(int address, uint32_t value);
-    size_t writeLong(int address, int32_t value);
-    size_t writeULong(int address, uint32_t value);
-    size_t writeLong64(int address, int64_t value);
-    size_t writeULong64(int address, uint64_t value);
-    size_t writeFloat(int address, float_t value);
-    size_t writeDouble(int address, double_t value);
-    size_t writeBool(int address, bool value);
-    size_t writeString(int address, const char* value);
-    size_t writeString(int address, String value);
-    size_t writeBytes(int address, const void* value, size_t len);
-    template <class T> T writeAll (int address, const T &);
-
-  protected:
-    nvs_handle _handle;
-    uint8_t* _data;
-    size_t _size;
-    bool _dirty;
-    const char* _name;
-    uint32_t _user_defined_size;
+    memcpy(_data + address, (const uint8_t *)&t, sizeof(T));
+    _dirty = true;
+    return t;
+  }
+
+  uint8_t readByte(int address);
+  int8_t readChar(int address);
+  uint8_t readUChar(int address);
+  int16_t readShort(int address);
+  uint16_t readUShort(int address);
+  int32_t readInt(int address);
+  uint32_t readUInt(int address);
+  int32_t readLong(int address);
+  uint32_t readULong(int address);
+  int64_t readLong64(int address);
+  uint64_t readULong64(int address);
+  float_t readFloat(int address);
+  double_t readDouble(int address);
+  bool readBool(int address);
+  size_t readString(int address, char *value, size_t maxLen);
+  String readString(int address);
+  size_t readBytes(int address, void *value, size_t maxLen);
+  template<class T> T readAll(int address, T &);
+
+  size_t writeByte(int address, uint8_t value);
+  size_t writeChar(int address, int8_t value);
+  size_t writeUChar(int address, uint8_t value);
+  size_t writeShort(int address, int16_t value);
+  size_t writeUShort(int address, uint16_t value);
+  size_t writeInt(int address, int32_t value);
+  size_t writeUInt(int address, uint32_t value);
+  size_t writeLong(int address, int32_t value);
+  size_t writeULong(int address, uint32_t value);
+  size_t writeLong64(int address, int64_t value);
+  size_t writeULong64(int address, uint64_t value);
+  size_t writeFloat(int address, float_t value);
+  size_t writeDouble(int address, double_t value);
+  size_t writeBool(int address, bool value);
+  size_t writeString(int address, const char *value);
+  size_t writeString(int address, String value);
+  size_t writeBytes(int address, const void *value, size_t len);
+  template<class T> T writeAll(int address, const T &);
+
+protected:
+  nvs_handle _handle;
+  uint8_t *_data;
+  size_t _size;
+  bool _dirty;
+  const char *_name;
 };
 
 #if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_EEPROM)
diff --git a/libraries/ESP32/examples/AnalogOut/LEDCFade/LEDCFade.ino b/libraries/ESP32/examples/AnalogOut/LEDCFade/LEDCFade.ino
new file mode 100644
index 00000000000..ea190e4f140
--- /dev/null
+++ b/libraries/ESP32/examples/AnalogOut/LEDCFade/LEDCFade.ino
@@ -0,0 +1,66 @@
+/* LEDC Fade Arduino Example
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+
+// use 12 bit precision for LEDC timer
+#define LEDC_TIMER_12_BIT 12
+
+// use 5000 Hz as a LEDC base frequency
+#define LEDC_BASE_FREQ 5000
+
+// fade LED PIN (replace with LED_BUILTIN constant for built-in LED)
+#define LED_PIN 4
+
+// define starting duty, target duty and maximum fade time
+#define LEDC_START_DUTY  (0)
+#define LEDC_TARGET_DUTY (4095)
+#define LEDC_FADE_TIME   (3000)
+
+bool fade_ended = false;  // status of LED fade
+bool fade_in = true;
+
+void ARDUINO_ISR_ATTR LED_FADE_ISR() {
+  fade_ended = true;
+}
+
+void setup() {
+  // Initialize serial communication at 115200 bits per second:
+  Serial.begin(115200);
+
+  // Setup timer with given frequency, resolution and attach it to a led pin with auto-selected channel
+  ledcAttach(LED_PIN, LEDC_BASE_FREQ, LEDC_TIMER_12_BIT);
+
+  // Setup and start fade on led (duty from 0 to 4095)
+  ledcFade(LED_PIN, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME);
+  Serial.println("LED Fade on started.");
+
+  // Wait for fade to end
+  delay(LEDC_FADE_TIME);
+
+  // Setup and start fade off led and use ISR (duty from 4095 to 0)
+  ledcFadeWithInterrupt(LED_PIN, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR);
+  Serial.println("LED Fade off started.");
+}
+
+void loop() {
+  // Check if fade_ended flag was set to true in ISR
+  if (fade_ended) {
+    Serial.println("LED fade ended");
+    fade_ended = false;
+
+    // Check what fade should be started next
+    if (fade_in) {
+      ledcFadeWithInterrupt(LED_PIN, LEDC_START_DUTY, LEDC_TARGET_DUTY, LEDC_FADE_TIME, LED_FADE_ISR);
+      Serial.println("LED Fade in started.");
+      fade_in = false;
+    } else {
+      ledcFadeWithInterrupt(LED_PIN, LEDC_TARGET_DUTY, LEDC_START_DUTY, LEDC_FADE_TIME, LED_FADE_ISR);
+      Serial.println("LED Fade out started.");
+      fade_in = true;
+    }
+  }
+}
diff --git a/libraries/ESP32/examples/AnalogOut/LEDCSingleChannel/LEDCSingleChannel.ino b/libraries/ESP32/examples/AnalogOut/LEDCSingleChannel/LEDCSingleChannel.ino
new file mode 100644
index 00000000000..2317e32a11a
--- /dev/null
+++ b/libraries/ESP32/examples/AnalogOut/LEDCSingleChannel/LEDCSingleChannel.ino
@@ -0,0 +1,50 @@
+/*
+ LEDC Software Fade on shared channel with multiple pins
+
+ This example shows how to software fade LED
+ using the ledcWriteChannel function on multiple pins.
+ This example is useful if you need to control synchronously
+ multiple LEDs on different pins.
+
+ Code adapted from original Arduino Fade example:
+ https://www.arduino.cc/en/Tutorial/Fade
+
+ This example code is in the public domain.
+ */
+
+// use 8 bit precision for LEDC timer
+#define LEDC_TIMER_8_BIT 8
+
+// use 5000 Hz as a LEDC base frequency
+#define LEDC_BASE_FREQ 5000
+
+// LED pins
+#define LED_PIN_1 4
+#define LED_PIN_2 5
+
+// LED channel that will be used instead of automatic selection.
+#define LEDC_CHANNEL 0
+
+int brightness = 0;  // how bright the LED is
+int fadeAmount = 5;  // how many points to fade the LED by
+
+void setup() {
+  // Use single LEDC channel 0 for both pins
+  ledcAttachChannel(LED_PIN_1, LEDC_BASE_FREQ, LEDC_TIMER_8_BIT, LEDC_CHANNEL);
+  ledcAttachChannel(LED_PIN_2, LEDC_BASE_FREQ, LEDC_TIMER_8_BIT, LEDC_CHANNEL);
+}
+
+void loop() {
+  // set the brightness on LEDC channel 0
+  ledcWriteChannel(LEDC_CHANNEL, brightness);
+
+  // change the brightness for next time through the loop:
+  brightness = brightness + fadeAmount;
+
+  // reverse the direction of the fading at the ends of the fade:
+  if (brightness <= 0 || brightness >= 255) {
+    fadeAmount = -fadeAmount;
+  }
+  // wait for 30 milliseconds to see the dimming effect
+  delay(30);
+}
diff --git a/libraries/ESP32/examples/AnalogOut/LEDCSoftwareFade/LEDCSoftwareFade.ino b/libraries/ESP32/examples/AnalogOut/LEDCSoftwareFade/LEDCSoftwareFade.ino
index a4f2e5b41ba..c605a89bc0b 100644
--- a/libraries/ESP32/examples/AnalogOut/LEDCSoftwareFade/LEDCSoftwareFade.ino
+++ b/libraries/ESP32/examples/AnalogOut/LEDCSoftwareFade/LEDCSoftwareFade.ino
@@ -10,40 +10,36 @@
  This example code is in the public domain.
  */
 
-// use first channel of 16 channels (started from zero)
-#define LEDC_CHANNEL_0     0
-
-// use 13 bit precission for LEDC timer
-#define LEDC_TIMER_13_BIT  13
+// use 12 bit precision for LEDC timer
+#define LEDC_TIMER_12_BIT 12
 
 // use 5000 Hz as a LEDC base frequency
-#define LEDC_BASE_FREQ     5000
+#define LEDC_BASE_FREQ 5000
 
 // fade LED PIN (replace with LED_BUILTIN constant for built-in LED)
-#define LED_PIN            5
+#define LED_PIN 5
 
-int brightness = 0;    // how bright the LED is
-int fadeAmount = 5;    // how many points to fade the LED by
+int brightness = 0;  // how bright the LED is
+int fadeAmount = 5;  // how many points to fade the LED by
 
 // Arduino like analogWrite
 // value has to be between 0 and valueMax
-void ledcAnalogWrite(uint8_t channel, uint32_t value, uint32_t valueMax = 255) {
-  // calculate duty, 8191 from 2 ^ 13 - 1
-  uint32_t duty = (8191 / valueMax) * min(value, valueMax);
+void ledcAnalogWrite(uint8_t pin, uint32_t value, uint32_t valueMax = 255) {
+  // calculate duty, 4095 from 2 ^ 12 - 1
+  uint32_t duty = (4095 / valueMax) * min(value, valueMax);
 
   // write duty to LEDC
-  ledcWrite(channel, duty);
+  ledcWrite(pin, duty);
 }
 
 void setup() {
   // Setup timer and attach timer to a led pin
-  ledcSetup(LEDC_CHANNEL_0, LEDC_BASE_FREQ, LEDC_TIMER_13_BIT);
-  ledcAttachPin(LED_PIN, LEDC_CHANNEL_0);
+  ledcAttach(LED_PIN, LEDC_BASE_FREQ, LEDC_TIMER_12_BIT);
 }
 
 void loop() {
   // set the brightness on LEDC channel 0
-  ledcAnalogWrite(LEDC_CHANNEL_0, brightness);
+  ledcAnalogWrite(LED_PIN, brightness);
 
   // change the brightness for next time through the loop:
   brightness = brightness + fadeAmount;
diff --git a/libraries/ESP32/examples/AnalogOut/SigmaDelta/SigmaDelta.ino b/libraries/ESP32/examples/AnalogOut/SigmaDelta/SigmaDelta.ino
index 4a5c012bb86..d244a4ee61f 100644
--- a/libraries/ESP32/examples/AnalogOut/SigmaDelta/SigmaDelta.ino
+++ b/libraries/ESP32/examples/AnalogOut/SigmaDelta/SigmaDelta.ino
@@ -1,18 +1,14 @@
-void setup()
-{
-    //setup channel 0 with frequency 312500 Hz
-    sigmaDeltaSetup(0, 312500);
-    //attach pin 18 to channel 0
-    sigmaDeltaAttachPin(18,0);
-    //initialize channel 0 to off
-    sigmaDeltaWrite(0, 0);
+void setup() {
+  //setup on pin 18 with frequency 312500 Hz
+  sigmaDeltaAttach(18, 312500);
+  //set pin 18 to off
+  sigmaDeltaWrite(18, 0);
 }
 
-void loop()
-{
-    //slowly ramp-up the value
-    //will overflow at 256
-    static uint8_t i = 0;
-    sigmaDeltaWrite(0, i++);
-    delay(100);
+void loop() {
+  //slowly ramp-up the value
+  //will overflow at 256
+  static uint8_t i = 0;
+  sigmaDeltaWrite(18, i++);
+  delay(100);
 }
diff --git a/libraries/ESP32/examples/AnalogOut/ledcFrequency/ledcFrequency.ino b/libraries/ESP32/examples/AnalogOut/ledcFrequency/ledcFrequency.ino
new file mode 100644
index 00000000000..8e86c6662e8
--- /dev/null
+++ b/libraries/ESP32/examples/AnalogOut/ledcFrequency/ledcFrequency.ino
@@ -0,0 +1,77 @@
+/*
+ * This sketch will map the maximum frequency depending on the bit resolution for the current SoC.
+ * Run the sketch and wait for the Final report.
+ * Ignore the error messages from incorrect settings such as these:
+ *  "E (4190) ledc: requested frequency and duty resolution can not be achieved, try reducing freq_hz or duty_resolution. div_param=255"
+ *
+ * Date: 11 Nov 2022
+ * Author: Tomas Pilny
+ */
+
+#include "soc/soc_caps.h"
+#include <string>
+
+#define PIN 2
+
+void setup() {
+  ledcAttach(PIN, 1000, 8);
+
+  uint32_t min_frequency;
+  uint32_t max_frequency;
+  uint32_t frequency;
+  uint32_t successful_frequency;
+  uint32_t max_freq_array[SOC_LEDC_TIMER_BIT_WIDTH];
+  uint32_t min_freq_array[SOC_LEDC_TIMER_BIT_WIDTH];
+
+  // Find Max Frequency
+  for (uint8_t resolution = 1; resolution <= SOC_LEDC_TIMER_BIT_WIDTH; ++resolution) {
+    max_freq_array[resolution - 1] = 0;
+    min_frequency = 0;
+    max_frequency = UINT32_MAX;
+    successful_frequency = 0;
+    while (min_frequency != max_frequency && min_frequency + 1 != max_frequency) {
+      frequency = min_frequency + ((max_frequency - min_frequency) / 2);
+      if (ledcChangeFrequency(PIN, frequency, resolution)) {
+        min_frequency = frequency;
+        successful_frequency = frequency;
+      } else {
+        max_frequency = frequency;
+      }
+    }  // while not found the maximum
+    max_freq_array[resolution - 1] = successful_frequency;
+  }  // for all resolutions
+
+  // Find Min Frequency
+  for (uint8_t resolution = 1; resolution <= SOC_LEDC_TIMER_BIT_WIDTH; ++resolution) {
+    min_freq_array[resolution - 1] = 0;
+    min_frequency = 0;
+    max_frequency = max_freq_array[resolution - 1];
+    successful_frequency = max_frequency;
+    while (min_frequency != max_frequency && min_frequency + 1 != max_frequency) {
+      frequency = min_frequency + ((max_frequency - min_frequency) / 2);
+      if (ledcChangeFrequency(PIN, frequency, resolution)) {
+        max_frequency = frequency;
+        successful_frequency = frequency;
+      } else {
+        min_frequency = frequency;
+      }
+    }  // while not found the maximum
+    min_freq_array[resolution - 1] = successful_frequency;
+  }  // for all resolutions
+
+  printf("Bit resolution | Min Frequency [Hz] | Max Frequency [Hz]\n");
+  for (uint8_t r = 1; r <= SOC_LEDC_TIMER_BIT_WIDTH; ++r) {
+    size_t max_len = std::to_string(UINT32_MAX).length();
+    printf(
+      "            %s%d |         %s%lu |         %s%lu\n", std::string(2 - std::to_string(r).length(), ' ').c_str(), r,
+      std::string(max_len - std::to_string(min_freq_array[r - 1]).length(), ' ').c_str(), min_freq_array[r - 1],
+      std::string(max_len - std::to_string(max_freq_array[r - 1]).length(), ' ').c_str(), max_freq_array[r - 1]
+    );
+  }
+
+  ledcDetach(PIN);
+}
+
+void loop() {
+  delay(1000);
+}
diff --git a/libraries/ESP32/examples/AnalogOut/ledcWrite_RGB/ledcWrite_RGB.ino b/libraries/ESP32/examples/AnalogOut/ledcWrite_RGB/ledcWrite_RGB.ino
index 633d1c0896d..b7ea8943487 100644
--- a/libraries/ESP32/examples/AnalogOut/ledcWrite_RGB/ledcWrite_RGB.ino
+++ b/libraries/ESP32/examples/AnalogOut/ledcWrite_RGB/ledcWrite_RGB.ino
@@ -1,130 +1,117 @@
 /*
   ledcWrite_RGB.ino
-  Runs through the full 255 color spectrum for an rgb led 
+  Runs through the full 255 color spectrum for an rgb led
   Demonstrate ledcWrite functionality for driving leds with PWM on ESP32
- 
+
   This example code is in the public domain.
-  
+
   Some basic modifications were made by vseven, mostly commenting.
  */
- 
-// Set up the rgb led names
-uint8_t ledR = A4;
-uint8_t ledG = A5;
-uint8_t ledB = A18; 
 
-uint8_t ledArray[3] = {1, 2, 3}; // three led channels
+// Set up the rgb led names
+uint8_t ledR = 0;
+uint8_t ledG = 2;
+uint8_t ledB = 4;
 
-const boolean invert = true; // set true if common anode, false if common cathode
+const boolean invert = true;  // set true if common anode, false if common cathode
 
-uint8_t color = 0;          // a value from 0 to 255 representing the hue
-uint32_t R, G, B;           // the Red Green and Blue color components
+uint8_t color = 0;         // a value from 0 to 255 representing the hue
+uint32_t R, G, B;          // the Red Green and Blue color components
 uint8_t brightness = 255;  // 255 is maximum brightness, but can be changed.  Might need 256 for common anode to fully turn off.
 
 // the setup routine runs once when you press reset:
-void setup() 
-{            
+void setup() {
   Serial.begin(115200);
-  delay(10); 
-  
-  ledcAttachPin(ledR, 1); // assign RGB led pins to channels
-  ledcAttachPin(ledG, 2);
-  ledcAttachPin(ledB, 3);
-  
-  // Initialize channels 
-  // channels 0-15, resolution 1-16 bits, freq limits depend on resolution
-  // ledcSetup(uint8_t channel, uint32_t freq, uint8_t resolution_bits);
-  ledcSetup(1, 12000, 8); // 12 kHz PWM, 8-bit resolution
-  ledcSetup(2, 12000, 8);
-  ledcSetup(3, 12000, 8);
+  delay(10);
+
+  // Initialize pins as LEDC channels
+  // resolution 1-16 bits, freq limits depend on resolution, channel is automatically selected
+  ledcAttach(ledR, 12000, 8);  // 12 kHz PWM, 8-bit resolution
+  ledcAttach(ledG, 12000, 8);
+  ledcAttach(ledB, 12000, 8);
 }
 
 // void loop runs over and over again
-void loop() 
-{
+void loop() {
   Serial.println("Send all LEDs a 255 and wait 2 seconds.");
   // If your RGB LED turns off instead of on here you should check if the LED is common anode or cathode.
   // If it doesn't fully turn off and is common anode try using 256.
-  ledcWrite(1, 255);
-  ledcWrite(2, 255);
-  ledcWrite(3, 255);
+  ledcWrite(ledR, 255);
+  ledcWrite(ledG, 255);
+  ledcWrite(ledB, 255);
   delay(2000);
   Serial.println("Send all LEDs a 0 and wait 2 seconds.");
-  ledcWrite(1, 0);
-  ledcWrite(2, 0);
-  ledcWrite(3, 0);
+  ledcWrite(ledR, 0);
+  ledcWrite(ledG, 0);
+  ledcWrite(ledB, 0);
   delay(2000);
- 
+
   Serial.println("Starting color fade loop.");
-  
- for (color = 0; color < 255; color++) { // Slew through the color spectrum
-
-  hueToRGB(color, brightness);  // call function to convert hue to RGB
-
-  // write the RGB values to the pins
-  ledcWrite(1, R); // write red component to channel 1, etc.
-  ledcWrite(2, G);   
-  ledcWrite(3, B); 
- 
-  delay(100); // full cycle of rgb over 256 colors takes 26 seconds
- }
- 
+
+  for (color = 0; color < 255; color++) {  // Slew through the color spectrum
+
+    hueToRGB(color, brightness);  // call function to convert hue to RGB
+
+    // write the RGB values to the pins
+    ledcWrite(ledR, R);  // write red component to channel 1, etc.
+    ledcWrite(ledG, G);
+    ledcWrite(ledB, B);
+
+    delay(100);  // full cycle of rgb over 256 colors takes 26 seconds
+  }
 }
 
 // Courtesy http://www.instructables.com/id/How-to-Use-an-RGB-LED/?ALLSTEPS
 // function to convert a color to its Red, Green, and Blue components.
 
-void hueToRGB(uint8_t hue, uint8_t brightness)
-{
-    uint16_t scaledHue = (hue * 6);
-    uint8_t segment = scaledHue / 256; // segment 0 to 5 around the
-                                            // color wheel
-    uint16_t segmentOffset =
-      scaledHue - (segment * 256); // position within the segment
-
-    uint8_t complement = 0;
-    uint16_t prev = (brightness * ( 255 -  segmentOffset)) / 256;
-    uint16_t next = (brightness *  segmentOffset) / 256;
-
-    if(invert)
-    {
-      brightness = 255 - brightness;
-      complement = 255;
-      prev = 255 - prev;
-      next = 255 - next;
-    }
-
-    switch(segment ) {
-    case 0:      // red
-        R = brightness;
-        G = next;
-        B = complement;
-    break;
-    case 1:     // yellow
-        R = prev;
-        G = brightness;
-        B = complement;
-    break;
-    case 2:     // green
-        R = complement;
-        G = brightness;
-        B = next;
-    break;
-    case 3:    // cyan
-        R = complement;
-        G = prev;
-        B = brightness;
-    break;
-    case 4:    // blue
-        R = next;
-        G = complement;
-        B = brightness;
-    break;
-   case 5:      // magenta
+void hueToRGB(uint8_t hue, uint8_t brightness) {
+  uint16_t scaledHue = (hue * 6);
+  uint8_t segment = scaledHue / 256;                     // segment 0 to 5 around the
+                                                         // color wheel
+  uint16_t segmentOffset = scaledHue - (segment * 256);  // position within the segment
+
+  uint8_t complement = 0;
+  uint16_t prev = (brightness * (255 - segmentOffset)) / 256;
+  uint16_t next = (brightness * segmentOffset) / 256;
+
+  if (invert) {
+    brightness = 255 - brightness;
+    complement = 255;
+    prev = 255 - prev;
+    next = 255 - next;
+  }
+
+  switch (segment) {
+    case 0:  // red
+      R = brightness;
+      G = next;
+      B = complement;
+      break;
+    case 1:  // yellow
+      R = prev;
+      G = brightness;
+      B = complement;
+      break;
+    case 2:  // green
+      R = complement;
+      G = brightness;
+      B = next;
+      break;
+    case 3:  // cyan
+      R = complement;
+      G = prev;
+      B = brightness;
+      break;
+    case 4:  // blue
+      R = next;
+      G = complement;
+      B = brightness;
+      break;
+    case 5:  // magenta
     default:
-        R = brightness;
-        G = complement;
-        B = prev;
-    break;
-    }
+      R = brightness;
+      G = complement;
+      B = prev;
+      break;
+  }
 }
diff --git a/libraries/ESP32/examples/AnalogRead/AnalogRead.ino b/libraries/ESP32/examples/AnalogRead/AnalogRead.ino
new file mode 100644
index 00000000000..f887305bd31
--- /dev/null
+++ b/libraries/ESP32/examples/AnalogRead/AnalogRead.ino
@@ -0,0 +1,19 @@
+void setup() {
+  // initialize serial communication at 115200 bits per second:
+  Serial.begin(115200);
+
+  //set the resolution to 12 bits (0-4095)
+  analogReadResolution(12);
+}
+
+void loop() {
+  // read the analog / millivolts value for pin 2:
+  int analogValue = analogRead(2);
+  int analogVolts = analogReadMilliVolts(2);
+
+  // print out the values you read:
+  Serial.printf("ADC analog value = %d\n", analogValue);
+  Serial.printf("ADC millivolts value = %d\n", analogVolts);
+
+  delay(100);  // delay in between reads for clear read from serial
+}
diff --git a/libraries/ESP32/examples/AnalogReadContinuous/AnalogReadContinuous.ino b/libraries/ESP32/examples/AnalogReadContinuous/AnalogReadContinuous.ino
new file mode 100644
index 00000000000..5011bebe798
--- /dev/null
+++ b/libraries/ESP32/examples/AnalogReadContinuous/AnalogReadContinuous.ino
@@ -0,0 +1,70 @@
+// Define how many conversion per pin will happen and reading the data will be and average of all conversions
+#define CONVERSIONS_PER_PIN 5
+
+// Declare array of ADC pins that will be used for ADC Continuous mode - ONLY ADC1 pins are supported
+// Number of selected pins can be from 1 to ALL ADC1 pins.
+#ifdef CONFIG_IDF_TARGET_ESP32
+uint8_t adc_pins[] = {36, 39, 34, 35};  //some of ADC1 pins for ESP32
+#else
+uint8_t adc_pins[] = {1, 2, 3, 4};  //ADC1 common pins for ESP32S2/S3 + ESP32C3/C6 + ESP32H2
+#endif
+
+// Calculate how many pins are declared in the array - needed as input for the setup function of ADC Continuous
+uint8_t adc_pins_count = sizeof(adc_pins) / sizeof(uint8_t);
+
+// Flag which will be set in ISR when conversion is done
+volatile bool adc_coversion_done = false;
+
+// Result structure for ADC Continuous reading
+adc_continuous_data_t *result = NULL;
+
+// ISR Function that will be triggered when ADC conversion is done
+void ARDUINO_ISR_ATTR adcComplete() {
+  adc_coversion_done = true;
+}
+
+void setup() {
+  // Initialize serial communication at 115200 bits per second:
+  Serial.begin(115200);
+
+  // Optional for ESP32: Set the resolution to 9-12 bits (default is 12 bits)
+  analogContinuousSetWidth(12);
+
+  // Optional: Set different attenaution (default is ADC_11db)
+  analogContinuousSetAtten(ADC_11db);
+
+  // Setup ADC Continuous with following input:
+  // array of pins, count of the pins, how many conversions per pin in one cycle will happen, sampling frequency, callback function
+  analogContinuous(adc_pins, adc_pins_count, CONVERSIONS_PER_PIN, 20000, &adcComplete);
+
+  // Start ADC Continuous conversions
+  analogContinuousStart();
+}
+
+void loop() {
+  // Check if conversion is done and try to read data
+  if (adc_coversion_done == true) {
+    // Set ISR flag back to false
+    adc_coversion_done = false;
+    // Read data from ADC
+    if (analogContinuousRead(&result, 0)) {
+
+      // Optional: Stop ADC Continuous conversions to have more time to process (print) the data
+      analogContinuousStop();
+
+      for (int i = 0; i < adc_pins_count; i++) {
+        Serial.printf("\nADC PIN %d data:", result[i].pin);
+        Serial.printf("\n   Avg raw value = %d", result[i].avg_read_raw);
+        Serial.printf("\n   Avg millivolts value = %d", result[i].avg_read_mvolts);
+      }
+
+      // Delay for better readability of ADC data
+      delay(1000);
+
+      // Optional: If ADC was stopped, start ADC conversions and wait for callback function to set adc_coversion_done flag to true
+      analogContinuousStart();
+    } else {
+      Serial.println("Error occurred during reading data. Set Core Debug Level to error or lower for more information.");
+    }
+  }
+}
diff --git a/libraries/ESP32/examples/ArduinoStackSize/ArduinoStackSize.ino b/libraries/ESP32/examples/ArduinoStackSize/ArduinoStackSize.ino
new file mode 100644
index 00000000000..c326f0a224d
--- /dev/null
+++ b/libraries/ESP32/examples/ArduinoStackSize/ArduinoStackSize.ino
@@ -0,0 +1,35 @@
+/*
+    ESP32 Arduino creates a task to run setup() and then to execute loop() continuously
+    This task can be found at https://github.com/espressif/arduino-esp32/blob/master/cores/esp32/main.cpp
+
+    By default "loopTask" will be created with a stack size of 8KB.
+    This should be plenty for most general sketches.
+
+    There is a way to change the stack size of this task by using
+    SET_LOOP_TASK_STACK_SIZE(size);
+    It will bypass the default stack size of 8KB and allow the user to define a new size.
+
+    It is recommend this value to be higher than 8KB, for instance 16KB.
+    This increasing may be necessary for the sketches that use deep recursion for instance.
+
+    In this example, you can verify it by changing or just commenting out SET_LOOP_TASK_STACK_SIZE();
+*/
+
+// This sets Arduino Stack Size - comment this line to use default 8K stack size
+SET_LOOP_TASK_STACK_SIZE(16 * 1024);  // 16KB
+
+void setup() {
+  Serial.begin(115200);
+
+  Serial.printf("Arduino Stack was set to %d bytes", getArduinoLoopTaskStackSize());
+
+  // Print unused stack for the task that is running setup()
+  Serial.printf("\nSetup() - Free Stack Space: %d", uxTaskGetStackHighWaterMark(NULL));
+}
+
+void loop() {
+  delay(1000);
+
+  // Print unused stack for the task that is running loop() - the same as for setup()
+  Serial.printf("\nLoop() - Free Stack Space: %d", uxTaskGetStackHighWaterMark(NULL));
+}
diff --git a/libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino b/libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino
new file mode 100644
index 00000000000..748deaa4e99
--- /dev/null
+++ b/libraries/ESP32/examples/CI/CIBoardsTest/CIBoardsTest.ino
@@ -0,0 +1,45 @@
+#include <Wire.h>
+#include <SPI.h>
+
+void setup() {
+  // UART initialization
+  Serial.begin(9600);
+
+  // I2C initialization
+  Wire.begin();
+
+  // SPI initialization
+  SPI.begin();
+}
+
+void loop() {
+  // UART echo
+  if (Serial.available()) {
+    Serial.write(Serial.read());
+  }
+
+  // I2C read/write
+  Wire.beginTransmission(0x68);  // I2C address of device
+  Wire.write(0x00);              // register to read/write
+  Wire.write(0xFF);              // data to write (if writing)
+  Wire.endTransmission();
+
+  Wire.requestFrom(0x68, 1);  // number of bytes to read
+
+  while (Wire.available()) {
+    Serial.println(Wire.read());
+  }
+
+  // SPI read/write
+  digitalWrite(SS, LOW);   // select slave device
+  SPI.transfer(0x01);      // data to write
+  digitalWrite(SS, HIGH);  // deselect slave device
+
+  digitalWrite(SS, LOW);           // select slave device
+  byte data = SPI.transfer(0x00);  // data to read
+  digitalWrite(SS, HIGH);          // deselect slave device
+
+  Serial.println(data);
+
+  delay(1000);  // wait for 1 second before repeating loop
+}
diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino b/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino
index 1898fe7da01..d483e11b1df 100644
--- a/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino
+++ b/libraries/ESP32/examples/Camera/CameraWebServer/CameraWebServer.ino
@@ -6,23 +6,41 @@
 //            Ensure ESP32 Wrover Module or other board with PSRAM is selected
 //            Partial images will be transmitted if image exceeds buffer size
 //
+//            You must select partition scheme from the board menu that has at least 3MB APP space.
+//            Face Recognition is DISABLED for ESP32 and ESP32-S2, because it takes up from 15
+//            seconds to process single frame. Face Detection is ENABLED if PSRAM is enabled as well
 
+// ===================
 // Select camera model
-#define CAMERA_MODEL_WROVER_KIT // Has PSRAM
-//#define CAMERA_MODEL_ESP_EYE // Has PSRAM
+// ===================
+//#define CAMERA_MODEL_WROVER_KIT // Has PSRAM
+#define CAMERA_MODEL_ESP_EYE  // Has PSRAM
+//#define CAMERA_MODEL_ESP32S3_EYE // Has PSRAM
 //#define CAMERA_MODEL_M5STACK_PSRAM // Has PSRAM
 //#define CAMERA_MODEL_M5STACK_V2_PSRAM // M5Camera version B Has PSRAM
 //#define CAMERA_MODEL_M5STACK_WIDE // Has PSRAM
 //#define CAMERA_MODEL_M5STACK_ESP32CAM // No PSRAM
+//#define CAMERA_MODEL_M5STACK_UNITCAM // No PSRAM
+//#define CAMERA_MODEL_M5STACK_CAMS3_UNIT  // Has PSRAM
 //#define CAMERA_MODEL_AI_THINKER // Has PSRAM
 //#define CAMERA_MODEL_TTGO_T_JOURNAL // No PSRAM
-
+//#define CAMERA_MODEL_XIAO_ESP32S3 // Has PSRAM
+// ** Espressif Internal Boards **
+//#define CAMERA_MODEL_ESP32_CAM_BOARD
+//#define CAMERA_MODEL_ESP32S2_CAM_BOARD
+//#define CAMERA_MODEL_ESP32S3_CAM_LCD
+//#define CAMERA_MODEL_DFRobot_FireBeetle2_ESP32S3 // Has PSRAM
+//#define CAMERA_MODEL_DFRobot_Romeo_ESP32S3 // Has PSRAM
 #include "camera_pins.h"
 
-const char* ssid = "*********";
-const char* password = "*********";
+// ===========================
+// Enter your WiFi credentials
+// ===========================
+const char *ssid = "**********";
+const char *password = "**********";
 
 void startCameraServer();
+void setupLedFlash(int pin);
 
 void setup() {
   Serial.begin(115200);
@@ -44,23 +62,37 @@ void setup() {
   config.pin_pclk = PCLK_GPIO_NUM;
   config.pin_vsync = VSYNC_GPIO_NUM;
   config.pin_href = HREF_GPIO_NUM;
-  config.pin_sscb_sda = SIOD_GPIO_NUM;
-  config.pin_sscb_scl = SIOC_GPIO_NUM;
+  config.pin_sccb_sda = SIOD_GPIO_NUM;
+  config.pin_sccb_scl = SIOC_GPIO_NUM;
   config.pin_pwdn = PWDN_GPIO_NUM;
   config.pin_reset = RESET_GPIO_NUM;
   config.xclk_freq_hz = 20000000;
-  config.pixel_format = PIXFORMAT_JPEG;
-  
+  config.frame_size = FRAMESIZE_UXGA;
+  config.pixel_format = PIXFORMAT_JPEG;  // for streaming
+  //config.pixel_format = PIXFORMAT_RGB565; // for face detection/recognition
+  config.grab_mode = CAMERA_GRAB_WHEN_EMPTY;
+  config.fb_location = CAMERA_FB_IN_PSRAM;
+  config.jpeg_quality = 12;
+  config.fb_count = 1;
+
   // if PSRAM IC present, init with UXGA resolution and higher JPEG quality
   //                      for larger pre-allocated frame buffer.
-  if(psramFound()){
-    config.frame_size = FRAMESIZE_UXGA;
-    config.jpeg_quality = 10;
-    config.fb_count = 2;
+  if (config.pixel_format == PIXFORMAT_JPEG) {
+    if (psramFound()) {
+      config.jpeg_quality = 10;
+      config.fb_count = 2;
+      config.grab_mode = CAMERA_GRAB_LATEST;
+    } else {
+      // Limit the frame size when PSRAM is not available
+      config.frame_size = FRAMESIZE_SVGA;
+      config.fb_location = CAMERA_FB_IN_DRAM;
+    }
   } else {
-    config.frame_size = FRAMESIZE_SVGA;
-    config.jpeg_quality = 12;
-    config.fb_count = 1;
+    // Best option for face detection/recognition
+    config.frame_size = FRAMESIZE_240X240;
+#if CONFIG_IDF_TARGET_ESP32S3
+    config.fb_count = 2;
+#endif
   }
 
 #if defined(CAMERA_MODEL_ESP_EYE)
@@ -75,23 +107,36 @@ void setup() {
     return;
   }
 
-  sensor_t * s = esp_camera_sensor_get();
+  sensor_t *s = esp_camera_sensor_get();
   // initial sensors are flipped vertically and colors are a bit saturated
   if (s->id.PID == OV3660_PID) {
-    s->set_vflip(s, 1); // flip it back
-    s->set_brightness(s, 1); // up the brightness just a bit
-    s->set_saturation(s, -2); // lower the saturation
+    s->set_vflip(s, 1);        // flip it back
+    s->set_brightness(s, 1);   // up the brightness just a bit
+    s->set_saturation(s, -2);  // lower the saturation
   }
   // drop down frame size for higher initial frame rate
-  s->set_framesize(s, FRAMESIZE_QVGA);
+  if (config.pixel_format == PIXFORMAT_JPEG) {
+    s->set_framesize(s, FRAMESIZE_QVGA);
+  }
 
 #if defined(CAMERA_MODEL_M5STACK_WIDE) || defined(CAMERA_MODEL_M5STACK_ESP32CAM)
   s->set_vflip(s, 1);
   s->set_hmirror(s, 1);
 #endif
 
+#if defined(CAMERA_MODEL_ESP32S3_EYE)
+  s->set_vflip(s, 1);
+#endif
+
+// Setup LED FLash if LED pin is defined in camera_pins.h
+#if defined(LED_GPIO_NUM)
+  setupLedFlash(LED_GPIO_NUM);
+#endif
+
   WiFi.begin(ssid, password);
+  WiFi.setSleep(false);
 
+  Serial.print("WiFi connecting");
   while (WiFi.status() != WL_CONNECTED) {
     delay(500);
     Serial.print(".");
@@ -107,6 +152,6 @@ void setup() {
 }
 
 void loop() {
-  // put your main code here, to run repeatedly:
+  // Do nothing. Everything is done in another task by the web server
   delay(10000);
 }
diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/app_httpd.cpp b/libraries/ESP32/examples/Camera/CameraWebServer/app_httpd.cpp
index 5e33ec7c171..81d643e37ac 100644
--- a/libraries/ESP32/examples/Camera/CameraWebServer/app_httpd.cpp
+++ b/libraries/ESP32/examples/Camera/CameraWebServer/app_httpd.cpp
@@ -15,648 +15,837 @@
 #include "esp_timer.h"
 #include "esp_camera.h"
 #include "img_converters.h"
+#include "fb_gfx.h"
+#include "esp32-hal-ledc.h"
+#include "sdkconfig.h"
 #include "camera_index.h"
-#include "Arduino.h"
 
-#include "fb_gfx.h"
-#include "fd_forward.h"
-#include "fr_forward.h"
+#if defined(ARDUINO_ARCH_ESP32) && defined(CONFIG_ARDUHAL_ESP_LOG)
+#include "esp32-hal-log.h"
+#endif
 
-#define ENROLL_CONFIRM_TIMES 5
-#define FACE_ID_SAVE_NUMBER 7
+// Enable LED FLASH setting
+#define CONFIG_LED_ILLUMINATOR_ENABLED 1
 
-#define FACE_COLOR_WHITE  0x00FFFFFF
-#define FACE_COLOR_BLACK  0x00000000
-#define FACE_COLOR_RED    0x000000FF
-#define FACE_COLOR_GREEN  0x0000FF00
-#define FACE_COLOR_BLUE   0x00FF0000
-#define FACE_COLOR_YELLOW (FACE_COLOR_RED | FACE_COLOR_GREEN)
-#define FACE_COLOR_CYAN   (FACE_COLOR_BLUE | FACE_COLOR_GREEN)
-#define FACE_COLOR_PURPLE (FACE_COLOR_BLUE | FACE_COLOR_RED)
+// LED FLASH setup
+#if CONFIG_LED_ILLUMINATOR_ENABLED
 
-typedef struct {
-        size_t size; //number of values used for filtering
-        size_t index; //current value index
-        size_t count; //value count
-        int sum;
-        int * values; //array to be filled with values
-} ra_filter_t;
+#define LED_LEDC_GPIO            22  //configure LED pin
+#define CONFIG_LED_MAX_INTENSITY 255
+
+int led_duty = 0;
+bool isStreaming = false;
+
+#endif
 
 typedef struct {
-        httpd_req_t *req;
-        size_t len;
+  httpd_req_t *req;
+  size_t len;
 } jpg_chunking_t;
 
 #define PART_BOUNDARY "123456789000000000000987654321"
-static const char* _STREAM_CONTENT_TYPE = "multipart/x-mixed-replace;boundary=" PART_BOUNDARY;
-static const char* _STREAM_BOUNDARY = "\r\n--" PART_BOUNDARY "\r\n";
-static const char* _STREAM_PART = "Content-Type: image/jpeg\r\nContent-Length: %u\r\n\r\n";
+static const char *_STREAM_CONTENT_TYPE = "multipart/x-mixed-replace;boundary=" PART_BOUNDARY;
+static const char *_STREAM_BOUNDARY = "\r\n--" PART_BOUNDARY "\r\n";
+static const char *_STREAM_PART = "Content-Type: image/jpeg\r\nContent-Length: %u\r\nX-Timestamp: %d.%06d\r\n\r\n";
 
-static ra_filter_t ra_filter;
 httpd_handle_t stream_httpd = NULL;
 httpd_handle_t camera_httpd = NULL;
 
-static mtmn_config_t mtmn_config = {0};
-static int8_t detection_enabled = 0;
-static int8_t recognition_enabled = 0;
-static int8_t is_enrolling = 0;
-static face_id_list id_list = {0};
+typedef struct {
+  size_t size;   //number of values used for filtering
+  size_t index;  //current value index
+  size_t count;  //value count
+  int sum;
+  int *values;  //array to be filled with values
+} ra_filter_t;
 
-static ra_filter_t * ra_filter_init(ra_filter_t * filter, size_t sample_size){
-    memset(filter, 0, sizeof(ra_filter_t));
+static ra_filter_t ra_filter;
 
-    filter->values = (int *)malloc(sample_size * sizeof(int));
-    if(!filter->values){
-        return NULL;
-    }
-    memset(filter->values, 0, sample_size * sizeof(int));
+static ra_filter_t *ra_filter_init(ra_filter_t *filter, size_t sample_size) {
+  memset(filter, 0, sizeof(ra_filter_t));
 
-    filter->size = sample_size;
-    return filter;
-}
+  filter->values = (int *)malloc(sample_size * sizeof(int));
+  if (!filter->values) {
+    return NULL;
+  }
+  memset(filter->values, 0, sample_size * sizeof(int));
 
-static int ra_filter_run(ra_filter_t * filter, int value){
-    if(!filter->values){
-        return value;
-    }
-    filter->sum -= filter->values[filter->index];
-    filter->values[filter->index] = value;
-    filter->sum += filter->values[filter->index];
-    filter->index++;
-    filter->index = filter->index % filter->size;
-    if (filter->count < filter->size) {
-        filter->count++;
-    }
-    return filter->sum / filter->count;
+  filter->size = sample_size;
+  return filter;
 }
 
-static void rgb_print(dl_matrix3du_t *image_matrix, uint32_t color, const char * str){
-    fb_data_t fb;
-    fb.width = image_matrix->w;
-    fb.height = image_matrix->h;
-    fb.data = image_matrix->item;
-    fb.bytes_per_pixel = 3;
-    fb.format = FB_BGR888;
-    fb_gfx_print(&fb, (fb.width - (strlen(str) * 14)) / 2, 10, color, str);
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
+static int ra_filter_run(ra_filter_t *filter, int value) {
+  if (!filter->values) {
+    return value;
+  }
+  filter->sum -= filter->values[filter->index];
+  filter->values[filter->index] = value;
+  filter->sum += filter->values[filter->index];
+  filter->index++;
+  filter->index = filter->index % filter->size;
+  if (filter->count < filter->size) {
+    filter->count++;
+  }
+  return filter->sum / filter->count;
 }
+#endif
 
-static int rgb_printf(dl_matrix3du_t *image_matrix, uint32_t color, const char *format, ...){
-    char loc_buf[64];
-    char * temp = loc_buf;
-    int len;
-    va_list arg;
-    va_list copy;
-    va_start(arg, format);
-    va_copy(copy, arg);
-    len = vsnprintf(loc_buf, sizeof(loc_buf), format, arg);
-    va_end(copy);
-    if(len >= sizeof(loc_buf)){
-        temp = (char*)malloc(len+1);
-        if(temp == NULL) {
-            return 0;
-        }
-    }
-    vsnprintf(temp, len+1, format, arg);
-    va_end(arg);
-    rgb_print(image_matrix, color, temp);
-    if(len > 64){
-        free(temp);
-    }
-    return len;
+#if CONFIG_LED_ILLUMINATOR_ENABLED
+void enable_led(bool en) {  // Turn LED On or Off
+  int duty = en ? led_duty : 0;
+  if (en && isStreaming && (led_duty > CONFIG_LED_MAX_INTENSITY)) {
+    duty = CONFIG_LED_MAX_INTENSITY;
+  }
+  ledcWrite(LED_LEDC_GPIO, duty);
+  //ledc_set_duty(CONFIG_LED_LEDC_SPEED_MODE, CONFIG_LED_LEDC_CHANNEL, duty);
+  //ledc_update_duty(CONFIG_LED_LEDC_SPEED_MODE, CONFIG_LED_LEDC_CHANNEL);
+  log_i("Set LED intensity to %d", duty);
 }
+#endif
 
-static void draw_face_boxes(dl_matrix3du_t *image_matrix, box_array_t *boxes, int face_id){
-    int x, y, w, h, i;
-    uint32_t color = FACE_COLOR_YELLOW;
-    if(face_id < 0){
-        color = FACE_COLOR_RED;
-    } else if(face_id > 0){
-        color = FACE_COLOR_GREEN;
-    }
-    fb_data_t fb;
-    fb.width = image_matrix->w;
-    fb.height = image_matrix->h;
-    fb.data = image_matrix->item;
-    fb.bytes_per_pixel = 3;
-    fb.format = FB_BGR888;
-    for (i = 0; i < boxes->len; i++){
-        // rectangle box
-        x = (int)boxes->box[i].box_p[0];
-        y = (int)boxes->box[i].box_p[1];
-        w = (int)boxes->box[i].box_p[2] - x + 1;
-        h = (int)boxes->box[i].box_p[3] - y + 1;
-        fb_gfx_drawFastHLine(&fb, x, y, w, color);
-        fb_gfx_drawFastHLine(&fb, x, y+h-1, w, color);
-        fb_gfx_drawFastVLine(&fb, x, y, h, color);
-        fb_gfx_drawFastVLine(&fb, x+w-1, y, h, color);
-#if 0
-        // landmark
-        int x0, y0, j;
-        for (j = 0; j < 10; j+=2) {
-            x0 = (int)boxes->landmark[i].landmark_p[j];
-            y0 = (int)boxes->landmark[i].landmark_p[j+1];
-            fb_gfx_fillRect(&fb, x0, y0, 3, 3, color);
-        }
+static esp_err_t bmp_handler(httpd_req_t *req) {
+  camera_fb_t *fb = NULL;
+  esp_err_t res = ESP_OK;
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
+  uint64_t fr_start = esp_timer_get_time();
 #endif
-    }
+  fb = esp_camera_fb_get();
+  if (!fb) {
+    log_e("Camera capture failed");
+    httpd_resp_send_500(req);
+    return ESP_FAIL;
+  }
+
+  httpd_resp_set_type(req, "image/x-windows-bmp");
+  httpd_resp_set_hdr(req, "Content-Disposition", "inline; filename=capture.bmp");
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+
+  char ts[32];
+  snprintf(ts, 32, "%lld.%06ld", fb->timestamp.tv_sec, fb->timestamp.tv_usec);
+  httpd_resp_set_hdr(req, "X-Timestamp", (const char *)ts);
+
+  uint8_t *buf = NULL;
+  size_t buf_len = 0;
+  bool converted = frame2bmp(fb, &buf, &buf_len);
+  esp_camera_fb_return(fb);
+  if (!converted) {
+    log_e("BMP Conversion failed");
+    httpd_resp_send_500(req);
+    return ESP_FAIL;
+  }
+  res = httpd_resp_send(req, (const char *)buf, buf_len);
+  free(buf);
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
+  uint64_t fr_end = esp_timer_get_time();
+#endif
+  log_i("BMP: %llums, %uB", (uint64_t)((fr_end - fr_start) / 1000), buf_len);
+  return res;
 }
 
-static int run_face_recognition(dl_matrix3du_t *image_matrix, box_array_t *net_boxes){
-    dl_matrix3du_t *aligned_face = NULL;
-    int matched_id = 0;
+static size_t jpg_encode_stream(void *arg, size_t index, const void *data, size_t len) {
+  jpg_chunking_t *j = (jpg_chunking_t *)arg;
+  if (!index) {
+    j->len = 0;
+  }
+  if (httpd_resp_send_chunk(j->req, (const char *)data, len) != ESP_OK) {
+    return 0;
+  }
+  j->len += len;
+  return len;
+}
 
-    aligned_face = dl_matrix3du_alloc(1, FACE_WIDTH, FACE_HEIGHT, 3);
-    if(!aligned_face){
-        Serial.println("Could not allocate face recognition buffer");
-        return matched_id;
-    }
-    if (align_face(net_boxes, image_matrix, aligned_face) == ESP_OK){
-        if (is_enrolling == 1){
-            int8_t left_sample_face = enroll_face(&id_list, aligned_face);
-
-            if(left_sample_face == (ENROLL_CONFIRM_TIMES - 1)){
-                Serial.printf("Enrolling Face ID: %d\n", id_list.tail);
-            }
-            Serial.printf("Enrolling Face ID: %d sample %d\n", id_list.tail, ENROLL_CONFIRM_TIMES - left_sample_face);
-            rgb_printf(image_matrix, FACE_COLOR_CYAN, "ID[%u] Sample[%u]", id_list.tail, ENROLL_CONFIRM_TIMES - left_sample_face);
-            if (left_sample_face == 0){
-                is_enrolling = 0;
-                Serial.printf("Enrolled Face ID: %d\n", id_list.tail);
-            }
-        } else {
-            matched_id = recognize_face(&id_list, aligned_face);
-            if (matched_id >= 0) {
-                Serial.printf("Match Face ID: %u\n", matched_id);
-                rgb_printf(image_matrix, FACE_COLOR_GREEN, "Hello Subject %u", matched_id);
-            } else {
-                Serial.println("No Match Found");
-                rgb_print(image_matrix, FACE_COLOR_RED, "Intruder Alert!");
-                matched_id = -1;
-            }
-        }
-    } else {
-        Serial.println("Face Not Aligned");
-        //rgb_print(image_matrix, FACE_COLOR_YELLOW, "Human Detected");
-    }
+static esp_err_t capture_handler(httpd_req_t *req) {
+  camera_fb_t *fb = NULL;
+  esp_err_t res = ESP_OK;
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
+  int64_t fr_start = esp_timer_get_time();
+#endif
 
-    dl_matrix3du_free(aligned_face);
-    return matched_id;
-}
+#if CONFIG_LED_ILLUMINATOR_ENABLED
+  enable_led(true);
+  vTaskDelay(150 / portTICK_PERIOD_MS);  // The LED needs to be turned on ~150ms before the call to esp_camera_fb_get()
+  fb = esp_camera_fb_get();              // or it won't be visible in the frame. A better way to do this is needed.
+  enable_led(false);
+#else
+  fb = esp_camera_fb_get();
+#endif
 
-static size_t jpg_encode_stream(void * arg, size_t index, const void* data, size_t len){
-    jpg_chunking_t *j = (jpg_chunking_t *)arg;
-    if(!index){
-        j->len = 0;
-    }
-    if(httpd_resp_send_chunk(j->req, (const char *)data, len) != ESP_OK){
-        return 0;
-    }
-    j->len += len;
-    return len;
+  if (!fb) {
+    log_e("Camera capture failed");
+    httpd_resp_send_500(req);
+    return ESP_FAIL;
+  }
+
+  httpd_resp_set_type(req, "image/jpeg");
+  httpd_resp_set_hdr(req, "Content-Disposition", "inline; filename=capture.jpg");
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+
+  char ts[32];
+  snprintf(ts, 32, "%lld.%06ld", fb->timestamp.tv_sec, fb->timestamp.tv_usec);
+  httpd_resp_set_hdr(req, "X-Timestamp", (const char *)ts);
+
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
+  size_t fb_len = 0;
+#endif
+  if (fb->format == PIXFORMAT_JPEG) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
+    fb_len = fb->len;
+#endif
+    res = httpd_resp_send(req, (const char *)fb->buf, fb->len);
+  } else {
+    jpg_chunking_t jchunk = {req, 0};
+    res = frame2jpg_cb(fb, 80, jpg_encode_stream, &jchunk) ? ESP_OK : ESP_FAIL;
+    httpd_resp_send_chunk(req, NULL, 0);
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
+    fb_len = jchunk.len;
+#endif
+  }
+  esp_camera_fb_return(fb);
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
+  int64_t fr_end = esp_timer_get_time();
+#endif
+  log_i("JPG: %uB %ums", (uint32_t)(fb_len), (uint32_t)((fr_end - fr_start) / 1000));
+  return res;
 }
 
-static esp_err_t capture_handler(httpd_req_t *req){
-    camera_fb_t * fb = NULL;
-    esp_err_t res = ESP_OK;
-    int64_t fr_start = esp_timer_get_time();
+static esp_err_t stream_handler(httpd_req_t *req) {
+  camera_fb_t *fb = NULL;
+  struct timeval _timestamp;
+  esp_err_t res = ESP_OK;
+  size_t _jpg_buf_len = 0;
+  uint8_t *_jpg_buf = NULL;
+  char *part_buf[128];
+
+  static int64_t last_frame = 0;
+  if (!last_frame) {
+    last_frame = esp_timer_get_time();
+  }
+
+  res = httpd_resp_set_type(req, _STREAM_CONTENT_TYPE);
+  if (res != ESP_OK) {
+    return res;
+  }
+
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+  httpd_resp_set_hdr(req, "X-Framerate", "60");
 
+#if CONFIG_LED_ILLUMINATOR_ENABLED
+  isStreaming = true;
+  enable_led(true);
+#endif
+
+  while (true) {
     fb = esp_camera_fb_get();
     if (!fb) {
-        Serial.println("Camera capture failed");
-        httpd_resp_send_500(req);
-        return ESP_FAIL;
-    }
-
-    httpd_resp_set_type(req, "image/jpeg");
-    httpd_resp_set_hdr(req, "Content-Disposition", "inline; filename=capture.jpg");
-    httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
-
-    size_t out_len, out_width, out_height;
-    uint8_t * out_buf;
-    bool s;
-    bool detected = false;
-    int face_id = 0;
-    if(!detection_enabled || fb->width > 400){
-        size_t fb_len = 0;
-        if(fb->format == PIXFORMAT_JPEG){
-            fb_len = fb->len;
-            res = httpd_resp_send(req, (const char *)fb->buf, fb->len);
-        } else {
-            jpg_chunking_t jchunk = {req, 0};
-            res = frame2jpg_cb(fb, 80, jpg_encode_stream, &jchunk)?ESP_OK:ESP_FAIL;
-            httpd_resp_send_chunk(req, NULL, 0);
-            fb_len = jchunk.len;
-        }
+      log_e("Camera capture failed");
+      res = ESP_FAIL;
+    } else {
+      _timestamp.tv_sec = fb->timestamp.tv_sec;
+      _timestamp.tv_usec = fb->timestamp.tv_usec;
+      if (fb->format != PIXFORMAT_JPEG) {
+        bool jpeg_converted = frame2jpg(fb, 80, &_jpg_buf, &_jpg_buf_len);
         esp_camera_fb_return(fb);
-        int64_t fr_end = esp_timer_get_time();
-        Serial.printf("JPG: %uB %ums\n", (uint32_t)(fb_len), (uint32_t)((fr_end - fr_start)/1000));
-        return res;
+        fb = NULL;
+        if (!jpeg_converted) {
+          log_e("JPEG compression failed");
+          res = ESP_FAIL;
+        }
+      } else {
+        _jpg_buf_len = fb->len;
+        _jpg_buf = fb->buf;
+      }
     }
-
-    dl_matrix3du_t *image_matrix = dl_matrix3du_alloc(1, fb->width, fb->height, 3);
-    if (!image_matrix) {
-        esp_camera_fb_return(fb);
-        Serial.println("dl_matrix3du_alloc failed");
-        httpd_resp_send_500(req);
-        return ESP_FAIL;
+    if (res == ESP_OK) {
+      res = httpd_resp_send_chunk(req, _STREAM_BOUNDARY, strlen(_STREAM_BOUNDARY));
     }
-
-    out_buf = image_matrix->item;
-    out_len = fb->width * fb->height * 3;
-    out_width = fb->width;
-    out_height = fb->height;
-
-    s = fmt2rgb888(fb->buf, fb->len, fb->format, out_buf);
-    esp_camera_fb_return(fb);
-    if(!s){
-        dl_matrix3du_free(image_matrix);
-        Serial.println("to rgb888 failed");
-        httpd_resp_send_500(req);
-        return ESP_FAIL;
+    if (res == ESP_OK) {
+      size_t hlen = snprintf((char *)part_buf, 128, _STREAM_PART, _jpg_buf_len, _timestamp.tv_sec, _timestamp.tv_usec);
+      res = httpd_resp_send_chunk(req, (const char *)part_buf, hlen);
     }
-
-    box_array_t *net_boxes = face_detect(image_matrix, &mtmn_config);
-
-    if (net_boxes){
-        detected = true;
-        if(recognition_enabled){
-            face_id = run_face_recognition(image_matrix, net_boxes);
-        }
-        draw_face_boxes(image_matrix, net_boxes, face_id);
-        free(net_boxes->score);
-        free(net_boxes->box);
-        free(net_boxes->landmark);
-        free(net_boxes);
+    if (res == ESP_OK) {
+      res = httpd_resp_send_chunk(req, (const char *)_jpg_buf, _jpg_buf_len);
     }
-
-    jpg_chunking_t jchunk = {req, 0};
-    s = fmt2jpg_cb(out_buf, out_len, out_width, out_height, PIXFORMAT_RGB888, 90, jpg_encode_stream, &jchunk);
-    dl_matrix3du_free(image_matrix);
-    if(!s){
-        Serial.println("JPEG compression failed");
-        return ESP_FAIL;
+    if (fb) {
+      esp_camera_fb_return(fb);
+      fb = NULL;
+      _jpg_buf = NULL;
+    } else if (_jpg_buf) {
+      free(_jpg_buf);
+      _jpg_buf = NULL;
+    }
+    if (res != ESP_OK) {
+      log_e("Send frame failed");
+      break;
     }
-
     int64_t fr_end = esp_timer_get_time();
-    Serial.printf("FACE: %uB %ums %s%d\n", (uint32_t)(jchunk.len), (uint32_t)((fr_end - fr_start)/1000), detected?"DETECTED ":"", face_id);
-    return res;
+
+    int64_t frame_time = fr_end - last_frame;
+    last_frame = fr_end;
+
+    frame_time /= 1000;
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
+    uint32_t avg_frame_time = ra_filter_run(&ra_filter, frame_time);
+#endif
+    log_i(
+      "MJPG: %uB %ums (%.1ffps), AVG: %ums (%.1ffps)", (uint32_t)(_jpg_buf_len), (uint32_t)frame_time, 1000.0 / (uint32_t)frame_time, avg_frame_time,
+      1000.0 / avg_frame_time
+    );
+  }
+
+#if CONFIG_LED_ILLUMINATOR_ENABLED
+  isStreaming = false;
+  enable_led(false);
+#endif
+
+  return res;
 }
 
-static esp_err_t stream_handler(httpd_req_t *req){
-    camera_fb_t * fb = NULL;
-    esp_err_t res = ESP_OK;
-    size_t _jpg_buf_len = 0;
-    uint8_t * _jpg_buf = NULL;
-    char * part_buf[64];
-    dl_matrix3du_t *image_matrix = NULL;
-    bool detected = false;
-    int face_id = 0;
-    int64_t fr_start = 0;
-    int64_t fr_ready = 0;
-    int64_t fr_face = 0;
-    int64_t fr_recognize = 0;
-    int64_t fr_encode = 0;
-
-    static int64_t last_frame = 0;
-    if(!last_frame) {
-        last_frame = esp_timer_get_time();
-    }
+static esp_err_t parse_get(httpd_req_t *req, char **obuf) {
+  char *buf = NULL;
+  size_t buf_len = 0;
 
-    res = httpd_resp_set_type(req, _STREAM_CONTENT_TYPE);
-    if(res != ESP_OK){
-        return res;
+  buf_len = httpd_req_get_url_query_len(req) + 1;
+  if (buf_len > 1) {
+    buf = (char *)malloc(buf_len);
+    if (!buf) {
+      httpd_resp_send_500(req);
+      return ESP_FAIL;
+    }
+    if (httpd_req_get_url_query_str(req, buf, buf_len) == ESP_OK) {
+      *obuf = buf;
+      return ESP_OK;
     }
+    free(buf);
+  }
+  httpd_resp_send_404(req);
+  return ESP_FAIL;
+}
 
-    httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
-
-    while(true){
-        detected = false;
-        face_id = 0;
-        fb = esp_camera_fb_get();
-        if (!fb) {
-            Serial.println("Camera capture failed");
-            res = ESP_FAIL;
-        } else {
-            fr_start = esp_timer_get_time();
-            fr_ready = fr_start;
-            fr_face = fr_start;
-            fr_encode = fr_start;
-            fr_recognize = fr_start;
-            if(!detection_enabled || fb->width > 400){
-                if(fb->format != PIXFORMAT_JPEG){
-                    bool jpeg_converted = frame2jpg(fb, 80, &_jpg_buf, &_jpg_buf_len);
-                    esp_camera_fb_return(fb);
-                    fb = NULL;
-                    if(!jpeg_converted){
-                        Serial.println("JPEG compression failed");
-                        res = ESP_FAIL;
-                    }
-                } else {
-                    _jpg_buf_len = fb->len;
-                    _jpg_buf = fb->buf;
-                }
-            } else {
-
-                image_matrix = dl_matrix3du_alloc(1, fb->width, fb->height, 3);
-
-                if (!image_matrix) {
-                    Serial.println("dl_matrix3du_alloc failed");
-                    res = ESP_FAIL;
-                } else {
-                    if(!fmt2rgb888(fb->buf, fb->len, fb->format, image_matrix->item)){
-                        Serial.println("fmt2rgb888 failed");
-                        res = ESP_FAIL;
-                    } else {
-                        fr_ready = esp_timer_get_time();
-                        box_array_t *net_boxes = NULL;
-                        if(detection_enabled){
-                            net_boxes = face_detect(image_matrix, &mtmn_config);
-                        }
-                        fr_face = esp_timer_get_time();
-                        fr_recognize = fr_face;
-                        if (net_boxes || fb->format != PIXFORMAT_JPEG){
-                            if(net_boxes){
-                                detected = true;
-                                if(recognition_enabled){
-                                    face_id = run_face_recognition(image_matrix, net_boxes);
-                                }
-                                fr_recognize = esp_timer_get_time();
-                                draw_face_boxes(image_matrix, net_boxes, face_id);
-                                free(net_boxes->score);
-                                free(net_boxes->box);
-                                free(net_boxes->landmark);
-                                free(net_boxes);
-                            }
-                            if(!fmt2jpg(image_matrix->item, fb->width*fb->height*3, fb->width, fb->height, PIXFORMAT_RGB888, 90, &_jpg_buf, &_jpg_buf_len)){
-                                Serial.println("fmt2jpg failed");
-                                res = ESP_FAIL;
-                            }
-                            esp_camera_fb_return(fb);
-                            fb = NULL;
-                        } else {
-                            _jpg_buf = fb->buf;
-                            _jpg_buf_len = fb->len;
-                        }
-                        fr_encode = esp_timer_get_time();
-                    }
-                    dl_matrix3du_free(image_matrix);
-                }
-            }
-        }
-        if(res == ESP_OK){
-            res = httpd_resp_send_chunk(req, _STREAM_BOUNDARY, strlen(_STREAM_BOUNDARY));
-        }
-        if(res == ESP_OK){
-            size_t hlen = snprintf((char *)part_buf, 64, _STREAM_PART, _jpg_buf_len);
-            res = httpd_resp_send_chunk(req, (const char *)part_buf, hlen);
-        }
-        if(res == ESP_OK){
-            res = httpd_resp_send_chunk(req, (const char *)_jpg_buf, _jpg_buf_len);
-        }
-        if(fb){
-            esp_camera_fb_return(fb);
-            fb = NULL;
-            _jpg_buf = NULL;
-        } else if(_jpg_buf){
-            free(_jpg_buf);
-            _jpg_buf = NULL;
-        }
-        if(res != ESP_OK){
-            break;
-        }
-        int64_t fr_end = esp_timer_get_time();
-
-        int64_t ready_time = (fr_ready - fr_start)/1000;
-        int64_t face_time = (fr_face - fr_ready)/1000;
-        int64_t recognize_time = (fr_recognize - fr_face)/1000;
-        int64_t encode_time = (fr_encode - fr_recognize)/1000;
-        int64_t process_time = (fr_encode - fr_start)/1000;
-        
-        int64_t frame_time = fr_end - last_frame;
-        last_frame = fr_end;
-        frame_time /= 1000;
-        uint32_t avg_frame_time = ra_filter_run(&ra_filter, frame_time);
-        Serial.printf("MJPG: %uB %ums (%.1ffps), AVG: %ums (%.1ffps), %u+%u+%u+%u=%u %s%d\n",
-            (uint32_t)(_jpg_buf_len),
-            (uint32_t)frame_time, 1000.0 / (uint32_t)frame_time,
-            avg_frame_time, 1000.0 / avg_frame_time,
-            (uint32_t)ready_time, (uint32_t)face_time, (uint32_t)recognize_time, (uint32_t)encode_time, (uint32_t)process_time,
-            (detected)?"DETECTED ":"", face_id
-        );
+static esp_err_t cmd_handler(httpd_req_t *req) {
+  char *buf = NULL;
+  char variable[32];
+  char value[32];
+
+  if (parse_get(req, &buf) != ESP_OK) {
+    return ESP_FAIL;
+  }
+  if (httpd_query_key_value(buf, "var", variable, sizeof(variable)) != ESP_OK || httpd_query_key_value(buf, "val", value, sizeof(value)) != ESP_OK) {
+    free(buf);
+    httpd_resp_send_404(req);
+    return ESP_FAIL;
+  }
+  free(buf);
+
+  int val = atoi(value);
+  log_i("%s = %d", variable, val);
+  sensor_t *s = esp_camera_sensor_get();
+  int res = 0;
+
+  if (!strcmp(variable, "framesize")) {
+    if (s->pixformat == PIXFORMAT_JPEG) {
+      res = s->set_framesize(s, (framesize_t)val);
     }
+  } else if (!strcmp(variable, "quality")) {
+    res = s->set_quality(s, val);
+  } else if (!strcmp(variable, "contrast")) {
+    res = s->set_contrast(s, val);
+  } else if (!strcmp(variable, "brightness")) {
+    res = s->set_brightness(s, val);
+  } else if (!strcmp(variable, "saturation")) {
+    res = s->set_saturation(s, val);
+  } else if (!strcmp(variable, "gainceiling")) {
+    res = s->set_gainceiling(s, (gainceiling_t)val);
+  } else if (!strcmp(variable, "colorbar")) {
+    res = s->set_colorbar(s, val);
+  } else if (!strcmp(variable, "awb")) {
+    res = s->set_whitebal(s, val);
+  } else if (!strcmp(variable, "agc")) {
+    res = s->set_gain_ctrl(s, val);
+  } else if (!strcmp(variable, "aec")) {
+    res = s->set_exposure_ctrl(s, val);
+  } else if (!strcmp(variable, "hmirror")) {
+    res = s->set_hmirror(s, val);
+  } else if (!strcmp(variable, "vflip")) {
+    res = s->set_vflip(s, val);
+  } else if (!strcmp(variable, "awb_gain")) {
+    res = s->set_awb_gain(s, val);
+  } else if (!strcmp(variable, "agc_gain")) {
+    res = s->set_agc_gain(s, val);
+  } else if (!strcmp(variable, "aec_value")) {
+    res = s->set_aec_value(s, val);
+  } else if (!strcmp(variable, "aec2")) {
+    res = s->set_aec2(s, val);
+  } else if (!strcmp(variable, "dcw")) {
+    res = s->set_dcw(s, val);
+  } else if (!strcmp(variable, "bpc")) {
+    res = s->set_bpc(s, val);
+  } else if (!strcmp(variable, "wpc")) {
+    res = s->set_wpc(s, val);
+  } else if (!strcmp(variable, "raw_gma")) {
+    res = s->set_raw_gma(s, val);
+  } else if (!strcmp(variable, "lenc")) {
+    res = s->set_lenc(s, val);
+  } else if (!strcmp(variable, "special_effect")) {
+    res = s->set_special_effect(s, val);
+  } else if (!strcmp(variable, "wb_mode")) {
+    res = s->set_wb_mode(s, val);
+  } else if (!strcmp(variable, "ae_level")) {
+    res = s->set_ae_level(s, val);
+  }
+#if CONFIG_LED_ILLUMINATOR_ENABLED
+  else if (!strcmp(variable, "led_intensity")) {
+    led_duty = val;
+    if (isStreaming) {
+      enable_led(true);
+    }
+  }
+#endif
+  else {
+    log_i("Unknown command: %s", variable);
+    res = -1;
+  }
 
-    last_frame = 0;
-    return res;
+  if (res < 0) {
+    return httpd_resp_send_500(req);
+  }
+
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+  return httpd_resp_send(req, NULL, 0);
 }
 
-static esp_err_t cmd_handler(httpd_req_t *req){
-    char*  buf;
-    size_t buf_len;
-    char variable[32] = {0,};
-    char value[32] = {0,};
-
-    buf_len = httpd_req_get_url_query_len(req) + 1;
-    if (buf_len > 1) {
-        buf = (char*)malloc(buf_len);
-        if(!buf){
-            httpd_resp_send_500(req);
-            return ESP_FAIL;
-        }
-        if (httpd_req_get_url_query_str(req, buf, buf_len) == ESP_OK) {
-            if (httpd_query_key_value(buf, "var", variable, sizeof(variable)) == ESP_OK &&
-                httpd_query_key_value(buf, "val", value, sizeof(value)) == ESP_OK) {
-            } else {
-                free(buf);
-                httpd_resp_send_404(req);
-                return ESP_FAIL;
-            }
-        } else {
-            free(buf);
-            httpd_resp_send_404(req);
-            return ESP_FAIL;
-        }
-        free(buf);
-    } else {
-        httpd_resp_send_404(req);
-        return ESP_FAIL;
-    }
+static int print_reg(char *p, sensor_t *s, uint16_t reg, uint32_t mask) {
+  return sprintf(p, "\"0x%x\":%u,", reg, s->get_reg(s, reg, mask));
+}
 
-    int val = atoi(value);
-    sensor_t * s = esp_camera_sensor_get();
-    int res = 0;
+static esp_err_t status_handler(httpd_req_t *req) {
+  static char json_response[1024];
 
-    if(!strcmp(variable, "framesize")) {
-        if(s->pixformat == PIXFORMAT_JPEG) res = s->set_framesize(s, (framesize_t)val);
-    }
-    else if(!strcmp(variable, "quality")) res = s->set_quality(s, val);
-    else if(!strcmp(variable, "contrast")) res = s->set_contrast(s, val);
-    else if(!strcmp(variable, "brightness")) res = s->set_brightness(s, val);
-    else if(!strcmp(variable, "saturation")) res = s->set_saturation(s, val);
-    else if(!strcmp(variable, "gainceiling")) res = s->set_gainceiling(s, (gainceiling_t)val);
-    else if(!strcmp(variable, "colorbar")) res = s->set_colorbar(s, val);
-    else if(!strcmp(variable, "awb")) res = s->set_whitebal(s, val);
-    else if(!strcmp(variable, "agc")) res = s->set_gain_ctrl(s, val);
-    else if(!strcmp(variable, "aec")) res = s->set_exposure_ctrl(s, val);
-    else if(!strcmp(variable, "hmirror")) res = s->set_hmirror(s, val);
-    else if(!strcmp(variable, "vflip")) res = s->set_vflip(s, val);
-    else if(!strcmp(variable, "awb_gain")) res = s->set_awb_gain(s, val);
-    else if(!strcmp(variable, "agc_gain")) res = s->set_agc_gain(s, val);
-    else if(!strcmp(variable, "aec_value")) res = s->set_aec_value(s, val);
-    else if(!strcmp(variable, "aec2")) res = s->set_aec2(s, val);
-    else if(!strcmp(variable, "dcw")) res = s->set_dcw(s, val);
-    else if(!strcmp(variable, "bpc")) res = s->set_bpc(s, val);
-    else if(!strcmp(variable, "wpc")) res = s->set_wpc(s, val);
-    else if(!strcmp(variable, "raw_gma")) res = s->set_raw_gma(s, val);
-    else if(!strcmp(variable, "lenc")) res = s->set_lenc(s, val);
-    else if(!strcmp(variable, "special_effect")) res = s->set_special_effect(s, val);
-    else if(!strcmp(variable, "wb_mode")) res = s->set_wb_mode(s, val);
-    else if(!strcmp(variable, "ae_level")) res = s->set_ae_level(s, val);
-    else if(!strcmp(variable, "face_detect")) {
-        detection_enabled = val;
-        if(!detection_enabled) {
-            recognition_enabled = 0;
-        }
+  sensor_t *s = esp_camera_sensor_get();
+  char *p = json_response;
+  *p++ = '{';
+
+  if (s->id.PID == OV5640_PID || s->id.PID == OV3660_PID) {
+    for (int reg = 0x3400; reg < 0x3406; reg += 2) {
+      p += print_reg(p, s, reg, 0xFFF);  //12 bit
     }
-    else if(!strcmp(variable, "face_enroll")) is_enrolling = val;
-    else if(!strcmp(variable, "face_recognize")) {
-        recognition_enabled = val;
-        if(recognition_enabled){
-            detection_enabled = val;
-        }
+    p += print_reg(p, s, 0x3406, 0xFF);
+
+    p += print_reg(p, s, 0x3500, 0xFFFF0);  //16 bit
+    p += print_reg(p, s, 0x3503, 0xFF);
+    p += print_reg(p, s, 0x350a, 0x3FF);   //10 bit
+    p += print_reg(p, s, 0x350c, 0xFFFF);  //16 bit
+
+    for (int reg = 0x5480; reg <= 0x5490; reg++) {
+      p += print_reg(p, s, reg, 0xFF);
     }
-    else {
-        res = -1;
+
+    for (int reg = 0x5380; reg <= 0x538b; reg++) {
+      p += print_reg(p, s, reg, 0xFF);
     }
 
-    if(res){
-        return httpd_resp_send_500(req);
+    for (int reg = 0x5580; reg < 0x558a; reg++) {
+      p += print_reg(p, s, reg, 0xFF);
     }
+    p += print_reg(p, s, 0x558a, 0x1FF);  //9 bit
+  } else if (s->id.PID == OV2640_PID) {
+    p += print_reg(p, s, 0xd3, 0xFF);
+    p += print_reg(p, s, 0x111, 0xFF);
+    p += print_reg(p, s, 0x132, 0xFF);
+  }
+
+  p += sprintf(p, "\"xclk\":%u,", s->xclk_freq_hz / 1000000);
+  p += sprintf(p, "\"pixformat\":%u,", s->pixformat);
+  p += sprintf(p, "\"framesize\":%u,", s->status.framesize);
+  p += sprintf(p, "\"quality\":%u,", s->status.quality);
+  p += sprintf(p, "\"brightness\":%d,", s->status.brightness);
+  p += sprintf(p, "\"contrast\":%d,", s->status.contrast);
+  p += sprintf(p, "\"saturation\":%d,", s->status.saturation);
+  p += sprintf(p, "\"sharpness\":%d,", s->status.sharpness);
+  p += sprintf(p, "\"special_effect\":%u,", s->status.special_effect);
+  p += sprintf(p, "\"wb_mode\":%u,", s->status.wb_mode);
+  p += sprintf(p, "\"awb\":%u,", s->status.awb);
+  p += sprintf(p, "\"awb_gain\":%u,", s->status.awb_gain);
+  p += sprintf(p, "\"aec\":%u,", s->status.aec);
+  p += sprintf(p, "\"aec2\":%u,", s->status.aec2);
+  p += sprintf(p, "\"ae_level\":%d,", s->status.ae_level);
+  p += sprintf(p, "\"aec_value\":%u,", s->status.aec_value);
+  p += sprintf(p, "\"agc\":%u,", s->status.agc);
+  p += sprintf(p, "\"agc_gain\":%u,", s->status.agc_gain);
+  p += sprintf(p, "\"gainceiling\":%u,", s->status.gainceiling);
+  p += sprintf(p, "\"bpc\":%u,", s->status.bpc);
+  p += sprintf(p, "\"wpc\":%u,", s->status.wpc);
+  p += sprintf(p, "\"raw_gma\":%u,", s->status.raw_gma);
+  p += sprintf(p, "\"lenc\":%u,", s->status.lenc);
+  p += sprintf(p, "\"hmirror\":%u,", s->status.hmirror);
+  p += sprintf(p, "\"dcw\":%u,", s->status.dcw);
+  p += sprintf(p, "\"colorbar\":%u", s->status.colorbar);
+#if CONFIG_LED_ILLUMINATOR_ENABLED
+  p += sprintf(p, ",\"led_intensity\":%u", led_duty);
+#else
+  p += sprintf(p, ",\"led_intensity\":%d", -1);
+#endif
+  *p++ = '}';
+  *p++ = 0;
+  httpd_resp_set_type(req, "application/json");
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+  return httpd_resp_send(req, json_response, strlen(json_response));
+}
+
+static esp_err_t xclk_handler(httpd_req_t *req) {
+  char *buf = NULL;
+  char _xclk[32];
+
+  if (parse_get(req, &buf) != ESP_OK) {
+    return ESP_FAIL;
+  }
+  if (httpd_query_key_value(buf, "xclk", _xclk, sizeof(_xclk)) != ESP_OK) {
+    free(buf);
+    httpd_resp_send_404(req);
+    return ESP_FAIL;
+  }
+  free(buf);
+
+  int xclk = atoi(_xclk);
+  log_i("Set XCLK: %d MHz", xclk);
+
+  sensor_t *s = esp_camera_sensor_get();
+  int res = s->set_xclk(s, LEDC_TIMER_0, xclk);
+  if (res) {
+    return httpd_resp_send_500(req);
+  }
+
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+  return httpd_resp_send(req, NULL, 0);
+}
 
-    httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
-    return httpd_resp_send(req, NULL, 0);
+static esp_err_t reg_handler(httpd_req_t *req) {
+  char *buf = NULL;
+  char _reg[32];
+  char _mask[32];
+  char _val[32];
+
+  if (parse_get(req, &buf) != ESP_OK) {
+    return ESP_FAIL;
+  }
+  if (httpd_query_key_value(buf, "reg", _reg, sizeof(_reg)) != ESP_OK || httpd_query_key_value(buf, "mask", _mask, sizeof(_mask)) != ESP_OK
+      || httpd_query_key_value(buf, "val", _val, sizeof(_val)) != ESP_OK) {
+    free(buf);
+    httpd_resp_send_404(req);
+    return ESP_FAIL;
+  }
+  free(buf);
+
+  int reg = atoi(_reg);
+  int mask = atoi(_mask);
+  int val = atoi(_val);
+  log_i("Set Register: reg: 0x%02x, mask: 0x%02x, value: 0x%02x", reg, mask, val);
+
+  sensor_t *s = esp_camera_sensor_get();
+  int res = s->set_reg(s, reg, mask, val);
+  if (res) {
+    return httpd_resp_send_500(req);
+  }
+
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+  return httpd_resp_send(req, NULL, 0);
 }
 
-static esp_err_t status_handler(httpd_req_t *req){
-    static char json_response[1024];
-
-    sensor_t * s = esp_camera_sensor_get();
-    char * p = json_response;
-    *p++ = '{';
-
-    p+=sprintf(p, "\"framesize\":%u,", s->status.framesize);
-    p+=sprintf(p, "\"quality\":%u,", s->status.quality);
-    p+=sprintf(p, "\"brightness\":%d,", s->status.brightness);
-    p+=sprintf(p, "\"contrast\":%d,", s->status.contrast);
-    p+=sprintf(p, "\"saturation\":%d,", s->status.saturation);
-    p+=sprintf(p, "\"sharpness\":%d,", s->status.sharpness);
-    p+=sprintf(p, "\"special_effect\":%u,", s->status.special_effect);
-    p+=sprintf(p, "\"wb_mode\":%u,", s->status.wb_mode);
-    p+=sprintf(p, "\"awb\":%u,", s->status.awb);
-    p+=sprintf(p, "\"awb_gain\":%u,", s->status.awb_gain);
-    p+=sprintf(p, "\"aec\":%u,", s->status.aec);
-    p+=sprintf(p, "\"aec2\":%u,", s->status.aec2);
-    p+=sprintf(p, "\"ae_level\":%d,", s->status.ae_level);
-    p+=sprintf(p, "\"aec_value\":%u,", s->status.aec_value);
-    p+=sprintf(p, "\"agc\":%u,", s->status.agc);
-    p+=sprintf(p, "\"agc_gain\":%u,", s->status.agc_gain);
-    p+=sprintf(p, "\"gainceiling\":%u,", s->status.gainceiling);
-    p+=sprintf(p, "\"bpc\":%u,", s->status.bpc);
-    p+=sprintf(p, "\"wpc\":%u,", s->status.wpc);
-    p+=sprintf(p, "\"raw_gma\":%u,", s->status.raw_gma);
-    p+=sprintf(p, "\"lenc\":%u,", s->status.lenc);
-    p+=sprintf(p, "\"vflip\":%u,", s->status.vflip);
-    p+=sprintf(p, "\"hmirror\":%u,", s->status.hmirror);
-    p+=sprintf(p, "\"dcw\":%u,", s->status.dcw);
-    p+=sprintf(p, "\"colorbar\":%u,", s->status.colorbar);
-    p+=sprintf(p, "\"face_detect\":%u,", detection_enabled);
-    p+=sprintf(p, "\"face_enroll\":%u,", is_enrolling);
-    p+=sprintf(p, "\"face_recognize\":%u", recognition_enabled);
-    *p++ = '}';
-    *p++ = 0;
-    httpd_resp_set_type(req, "application/json");
-    httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
-    return httpd_resp_send(req, json_response, strlen(json_response));
+static esp_err_t greg_handler(httpd_req_t *req) {
+  char *buf = NULL;
+  char _reg[32];
+  char _mask[32];
+
+  if (parse_get(req, &buf) != ESP_OK) {
+    return ESP_FAIL;
+  }
+  if (httpd_query_key_value(buf, "reg", _reg, sizeof(_reg)) != ESP_OK || httpd_query_key_value(buf, "mask", _mask, sizeof(_mask)) != ESP_OK) {
+    free(buf);
+    httpd_resp_send_404(req);
+    return ESP_FAIL;
+  }
+  free(buf);
+
+  int reg = atoi(_reg);
+  int mask = atoi(_mask);
+  sensor_t *s = esp_camera_sensor_get();
+  int res = s->get_reg(s, reg, mask);
+  if (res < 0) {
+    return httpd_resp_send_500(req);
+  }
+  log_i("Get Register: reg: 0x%02x, mask: 0x%02x, value: 0x%02x", reg, mask, res);
+
+  char buffer[20];
+  const char *val = itoa(res, buffer, 10);
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+  return httpd_resp_send(req, val, strlen(val));
 }
 
-static esp_err_t index_handler(httpd_req_t *req){
-    httpd_resp_set_type(req, "text/html");
-    httpd_resp_set_hdr(req, "Content-Encoding", "gzip");
-    sensor_t * s = esp_camera_sensor_get();
+static int parse_get_var(char *buf, const char *key, int def) {
+  char _int[16];
+  if (httpd_query_key_value(buf, key, _int, sizeof(_int)) != ESP_OK) {
+    return def;
+  }
+  return atoi(_int);
+}
+
+static esp_err_t pll_handler(httpd_req_t *req) {
+  char *buf = NULL;
+
+  if (parse_get(req, &buf) != ESP_OK) {
+    return ESP_FAIL;
+  }
+
+  int bypass = parse_get_var(buf, "bypass", 0);
+  int mul = parse_get_var(buf, "mul", 0);
+  int sys = parse_get_var(buf, "sys", 0);
+  int root = parse_get_var(buf, "root", 0);
+  int pre = parse_get_var(buf, "pre", 0);
+  int seld5 = parse_get_var(buf, "seld5", 0);
+  int pclken = parse_get_var(buf, "pclken", 0);
+  int pclk = parse_get_var(buf, "pclk", 0);
+  free(buf);
+
+  log_i("Set Pll: bypass: %d, mul: %d, sys: %d, root: %d, pre: %d, seld5: %d, pclken: %d, pclk: %d", bypass, mul, sys, root, pre, seld5, pclken, pclk);
+  sensor_t *s = esp_camera_sensor_get();
+  int res = s->set_pll(s, bypass, mul, sys, root, pre, seld5, pclken, pclk);
+  if (res) {
+    return httpd_resp_send_500(req);
+  }
+
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+  return httpd_resp_send(req, NULL, 0);
+}
+
+static esp_err_t win_handler(httpd_req_t *req) {
+  char *buf = NULL;
+
+  if (parse_get(req, &buf) != ESP_OK) {
+    return ESP_FAIL;
+  }
+
+  int startX = parse_get_var(buf, "sx", 0);
+  int startY = parse_get_var(buf, "sy", 0);
+  int endX = parse_get_var(buf, "ex", 0);
+  int endY = parse_get_var(buf, "ey", 0);
+  int offsetX = parse_get_var(buf, "offx", 0);
+  int offsetY = parse_get_var(buf, "offy", 0);
+  int totalX = parse_get_var(buf, "tx", 0);
+  int totalY = parse_get_var(buf, "ty", 0);  // codespell:ignore totaly
+  int outputX = parse_get_var(buf, "ox", 0);
+  int outputY = parse_get_var(buf, "oy", 0);
+  bool scale = parse_get_var(buf, "scale", 0) == 1;
+  bool binning = parse_get_var(buf, "binning", 0) == 1;
+  free(buf);
+
+  log_i(
+    "Set Window: Start: %d %d, End: %d %d, Offset: %d %d, Total: %d %d, Output: %d %d, Scale: %u, Binning: %u", startX, startY, endX, endY, offsetX, offsetY,
+    totalX, totalY, outputX, outputY, scale, binning  // codespell:ignore totaly
+  );
+  sensor_t *s = esp_camera_sensor_get();
+  int res = s->set_res_raw(s, startX, startY, endX, endY, offsetX, offsetY, totalX, totalY, outputX, outputY, scale, binning);  // codespell:ignore totaly
+  if (res) {
+    return httpd_resp_send_500(req);
+  }
+
+  httpd_resp_set_hdr(req, "Access-Control-Allow-Origin", "*");
+  return httpd_resp_send(req, NULL, 0);
+}
+
+static esp_err_t index_handler(httpd_req_t *req) {
+  httpd_resp_set_type(req, "text/html");
+  httpd_resp_set_hdr(req, "Content-Encoding", "gzip");
+  sensor_t *s = esp_camera_sensor_get();
+  if (s != NULL) {
     if (s->id.PID == OV3660_PID) {
-        return httpd_resp_send(req, (const char *)index_ov3660_html_gz, index_ov3660_html_gz_len);
+      return httpd_resp_send(req, (const char *)index_ov3660_html_gz, index_ov3660_html_gz_len);
+    } else if (s->id.PID == OV5640_PID) {
+      return httpd_resp_send(req, (const char *)index_ov5640_html_gz, index_ov5640_html_gz_len);
+    } else {
+      return httpd_resp_send(req, (const char *)index_ov2640_html_gz, index_ov2640_html_gz_len);
     }
-    return httpd_resp_send(req, (const char *)index_ov2640_html_gz, index_ov2640_html_gz_len);
+  } else {
+    log_e("Camera sensor not found");
+    return httpd_resp_send_500(req);
+  }
 }
 
-void startCameraServer(){
-    httpd_config_t config = HTTPD_DEFAULT_CONFIG();
-
-    httpd_uri_t index_uri = {
-        .uri       = "/",
-        .method    = HTTP_GET,
-        .handler   = index_handler,
-        .user_ctx  = NULL
-    };
-
-    httpd_uri_t status_uri = {
-        .uri       = "/status",
-        .method    = HTTP_GET,
-        .handler   = status_handler,
-        .user_ctx  = NULL
-    };
-
-    httpd_uri_t cmd_uri = {
-        .uri       = "/control",
-        .method    = HTTP_GET,
-        .handler   = cmd_handler,
-        .user_ctx  = NULL
-    };
-
-    httpd_uri_t capture_uri = {
-        .uri       = "/capture",
-        .method    = HTTP_GET,
-        .handler   = capture_handler,
-        .user_ctx  = NULL
-    };
-
-   httpd_uri_t stream_uri = {
-        .uri       = "/stream",
-        .method    = HTTP_GET,
-        .handler   = stream_handler,
-        .user_ctx  = NULL
-    };
-
-
-    ra_filter_init(&ra_filter, 20);
-    
-    mtmn_config.type = FAST;
-    mtmn_config.min_face = 80;
-    mtmn_config.pyramid = 0.707;
-    mtmn_config.pyramid_times = 4;
-    mtmn_config.p_threshold.score = 0.6;
-    mtmn_config.p_threshold.nms = 0.7;
-    mtmn_config.p_threshold.candidate_number = 20;
-    mtmn_config.r_threshold.score = 0.7;
-    mtmn_config.r_threshold.nms = 0.7;
-    mtmn_config.r_threshold.candidate_number = 10;
-    mtmn_config.o_threshold.score = 0.7;
-    mtmn_config.o_threshold.nms = 0.7;
-    mtmn_config.o_threshold.candidate_number = 1;
-    
-    face_id_init(&id_list, FACE_ID_SAVE_NUMBER, ENROLL_CONFIRM_TIMES);
-    
-    Serial.printf("Starting web server on port: '%d'\n", config.server_port);
-    if (httpd_start(&camera_httpd, &config) == ESP_OK) {
-        httpd_register_uri_handler(camera_httpd, &index_uri);
-        httpd_register_uri_handler(camera_httpd, &cmd_uri);
-        httpd_register_uri_handler(camera_httpd, &status_uri);
-        httpd_register_uri_handler(camera_httpd, &capture_uri);
-    }
+void startCameraServer() {
+  httpd_config_t config = HTTPD_DEFAULT_CONFIG();
+  config.max_uri_handlers = 16;
+
+  httpd_uri_t index_uri = {
+    .uri = "/",
+    .method = HTTP_GET,
+    .handler = index_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t status_uri = {
+    .uri = "/status",
+    .method = HTTP_GET,
+    .handler = status_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t cmd_uri = {
+    .uri = "/control",
+    .method = HTTP_GET,
+    .handler = cmd_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t capture_uri = {
+    .uri = "/capture",
+    .method = HTTP_GET,
+    .handler = capture_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t stream_uri = {
+    .uri = "/stream",
+    .method = HTTP_GET,
+    .handler = stream_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t bmp_uri = {
+    .uri = "/bmp",
+    .method = HTTP_GET,
+    .handler = bmp_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t xclk_uri = {
+    .uri = "/xclk",
+    .method = HTTP_GET,
+    .handler = xclk_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t reg_uri = {
+    .uri = "/reg",
+    .method = HTTP_GET,
+    .handler = reg_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t greg_uri = {
+    .uri = "/greg",
+    .method = HTTP_GET,
+    .handler = greg_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t pll_uri = {
+    .uri = "/pll",
+    .method = HTTP_GET,
+    .handler = pll_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  httpd_uri_t win_uri = {
+    .uri = "/resolution",
+    .method = HTTP_GET,
+    .handler = win_handler,
+    .user_ctx = NULL
+#ifdef CONFIG_HTTPD_WS_SUPPORT
+    ,
+    .is_websocket = true,
+    .handle_ws_control_frames = false,
+    .supported_subprotocol = NULL
+#endif
+  };
+
+  ra_filter_init(&ra_filter, 20);
+
+  log_i("Starting web server on port: '%d'", config.server_port);
+  if (httpd_start(&camera_httpd, &config) == ESP_OK) {
+    httpd_register_uri_handler(camera_httpd, &index_uri);
+    httpd_register_uri_handler(camera_httpd, &cmd_uri);
+    httpd_register_uri_handler(camera_httpd, &status_uri);
+    httpd_register_uri_handler(camera_httpd, &capture_uri);
+    httpd_register_uri_handler(camera_httpd, &bmp_uri);
+
+    httpd_register_uri_handler(camera_httpd, &xclk_uri);
+    httpd_register_uri_handler(camera_httpd, &reg_uri);
+    httpd_register_uri_handler(camera_httpd, &greg_uri);
+    httpd_register_uri_handler(camera_httpd, &pll_uri);
+    httpd_register_uri_handler(camera_httpd, &win_uri);
+  }
+
+  config.server_port += 1;
+  config.ctrl_port += 1;
+  log_i("Starting stream server on port: '%d'", config.server_port);
+  if (httpd_start(&stream_httpd, &config) == ESP_OK) {
+    httpd_register_uri_handler(stream_httpd, &stream_uri);
+  }
+}
 
-    config.server_port += 1;
-    config.ctrl_port += 1;
-    Serial.printf("Starting stream server on port: '%d'\n", config.server_port);
-    if (httpd_start(&stream_httpd, &config) == ESP_OK) {
-        httpd_register_uri_handler(stream_httpd, &stream_uri);
-    }
+void setupLedFlash(int pin) {
+#if CONFIG_LED_ILLUMINATOR_ENABLED
+  ledcAttach(pin, 5000, 8);
+#else
+  log_i("LED flash is disabled -> CONFIG_LED_ILLUMINATOR_ENABLED = 0");
+#endif
 }
diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/camera_index.h b/libraries/ESP32/examples/Camera/CameraWebServer/camera_index.h
index 9e6e09bf13d..b38e2773af3 100644
--- a/libraries/ESP32/examples/Camera/CameraWebServer/camera_index.h
+++ b/libraries/ESP32/examples/Camera/CameraWebServer/camera_index.h
@@ -1,558 +1,949 @@
 
-//File: index_ov2640.html.gz, Size: 4316
-#define index_ov2640_html_gz_len 4316
-const uint8_t index_ov2640_html_gz[] = {
- 0x1F, 0x8B, 0x08, 0x08, 0x50, 0x5C, 0xAE, 0x5C, 0x00, 0x03, 0x69, 0x6E, 0x64, 0x65, 0x78, 0x5F,
- 0x6F, 0x76, 0x32, 0x36, 0x34, 0x30, 0x2E, 0x68, 0x74, 0x6D, 0x6C, 0x00, 0xE5, 0x5D, 0x7B, 0x73,
- 0xD3, 0xC6, 0x16, 0xFF, 0x9F, 0x4F, 0x21, 0x04, 0x25, 0xF6, 0x34, 0x76, 0x6C, 0xC7, 0x84, 0xE0,
- 0xDA, 0xE2, 0x42, 0x08, 0xD0, 0x19, 0x5E, 0x25, 0x2D, 0x74, 0xA6, 0xD3, 0x81, 0xB5, 0xB4, 0xB2,
- 0x55, 0x64, 0xC9, 0x95, 0x56, 0x76, 0x52, 0x26, 0x9F, 0xE3, 0x7E, 0xA0, 0xFB, 0xC5, 0xEE, 0xD9,
- 0x87, 0xA4, 0x95, 0xBC, 0x7A, 0xD8, 0x26, 0x36, 0x97, 0xEB, 0xCC, 0x14, 0xD9, 0xDA, 0x73, 0xF6,
- 0x9C, 0xF3, 0x3B, 0xAF, 0x5D, 0x3D, 0x3A, 0xBC, 0x6D, 0xF9, 0x26, 0xB9, 0x9A, 0x63, 0x6D, 0x4A,
- 0x66, 0xAE, 0x71, 0x6B, 0xC8, 0xFF, 0xD1, 0xE0, 0x33, 0x9C, 0x62, 0x64, 0xF1, 0x43, 0xF6, 0x75,
- 0x86, 0x09, 0xD2, 0xCC, 0x29, 0x0A, 0x42, 0x4C, 0x46, 0x7A, 0x44, 0xEC, 0xD6, 0xA9, 0x9E, 0x3F,
- 0xED, 0xA1, 0x19, 0x1E, 0xE9, 0x0B, 0x07, 0x2F, 0xE7, 0x7E, 0x40, 0x74, 0xCD, 0xF4, 0x3D, 0x82,
- 0x3D, 0x18, 0xBE, 0x74, 0x2C, 0x32, 0x1D, 0x59, 0x78, 0xE1, 0x98, 0xB8, 0xC5, 0xBE, 0x1C, 0x3A,
- 0x9E, 0x43, 0x1C, 0xE4, 0xB6, 0x42, 0x13, 0xB9, 0x78, 0xD4, 0x95, 0x79, 0x11, 0x87, 0xB8, 0xD8,
- 0x38, 0xBF, 0x78, 0x7B, 0xDC, 0xD3, 0xDE, 0xBC, 0xEF, 0xF5, 0x4F, 0x3A, 0xC3, 0x23, 0xFE, 0x5B,
- 0x3A, 0x26, 0x24, 0x57, 0xF2, 0x77, 0xFA, 0x19, 0xFB, 0xD6, 0x95, 0xF6, 0x25, 0xF3, 0x13, 0xFD,
- 0xD8, 0x20, 0x44, 0xCB, 0x46, 0x33, 0xC7, 0xBD, 0x1A, 0x68, 0x8F, 0x03, 0x98, 0xF3, 0xF0, 0x05,
- 0x76, 0x17, 0x98, 0x38, 0x26, 0x3A, 0x0C, 0x91, 0x17, 0xB6, 0x42, 0x1C, 0x38, 0xF6, 0x4F, 0x2B,
- 0x84, 0x63, 0x64, 0x7E, 0x9E, 0x04, 0x7E, 0xE4, 0x59, 0x03, 0xED, 0x4E, 0xF7, 0x94, 0xFE, 0xAD,
- 0x0E, 0x32, 0x7D, 0xD7, 0x0F, 0xE0, 0xFC, 0xF9, 0x33, 0xFA, 0xB7, 0x7A, 0x9E, 0xCD, 0x1E, 0x3A,
- 0xFF, 0xE0, 0x81, 0xD6, 0x3D, 0x99, 0x5F, 0x66, 0xCE, 0x5F, 0xDF, 0xCA, 0x7C, 0x9D, 0xF6, 0x8A,
- 0xA4, 0x17, 0xF4, 0xA7, 0xE5, 0xF4, 0x21, 0x36, 0x89, 0xE3, 0x7B, 0xED, 0x19, 0x72, 0x3C, 0x05,
- 0x27, 0xCB, 0x09, 0xE7, 0x2E, 0x02, 0x1B, 0xD8, 0x2E, 0x2E, 0xE5, 0x73, 0x67, 0x86, 0xBD, 0xE8,
- 0xB0, 0x82, 0x1B, 0x65, 0xD2, 0xB2, 0x9C, 0x80, 0x8F, 0x1A, 0x50, 0x3B, 0x44, 0x33, 0xAF, 0x92,
- 0x6D, 0x99, 0x5C, 0x9E, 0xEF, 0x61, 0x85, 0x01, 0xE9, 0x44, 0xCB, 0x00, 0xCD, 0xE9, 0x00, 0xFA,
- 0xEF, 0xEA, 0x90, 0x99, 0xE3, 0x71, 0xA7, 0x1A, 0x68, 0xC7, 0xFD, 0xCE, 0xFC, 0xB2, 0x02, 0xCA,
- 0xE3, 0x13, 0xFA, 0xB7, 0x3A, 0x68, 0x8E, 0x2C, 0xCB, 0xF1, 0x26, 0x03, 0xED, 0x54, 0xC9, 0xC2,
- 0x0F, 0x2C, 0x1C, 0xB4, 0x02, 0x64, 0x39, 0x51, 0x38, 0xD0, 0xFA, 0xAA, 0x31, 0x33, 0x14, 0x4C,
- 0x40, 0x16, 0xE2, 0x83, 0xB0, 0xAD, 0xAE, 0x52, 0x12, 0x31, 0x24, 0x70, 0x26, 0x53, 0x02, 0x90,
- 0xAE, 0x8C, 0xC9, 0x1B, 0x4D, 0x84, 0x50, 0x15, 0x9E, 0xA5, 0x76, 0x53, 0x5B, 0x0D, 0xB9, 0xCE,
- 0xC4, 0x6B, 0x39, 0x04, 0xCF, 0x40, 0x9D, 0x90, 0x04, 0x98, 0x98, 0xD3, 0x32, 0x51, 0x6C, 0x67,
- 0x12, 0x05, 0x58, 0x21, 0x48, 0x62, 0xB7, 0x12, 0x85, 0xE1, 0xE4, 0xEA, 0xA9, 0xD6, 0x12, 0x8F,
- 0x3F, 0x3B, 0xA4, 0x25, 0x6C, 0x32, 0xC6, 0xB6, 0x1F, 0x60, 0xE5, 0xC8, 0x78, 0x84, 0xEB, 0x9B,
- 0x9F, 0x5B, 0x21, 0x41, 0x01, 0xA9, 0xC3, 0x10, 0xD9, 0x04, 0x07, 0xD5, 0xFC, 0x30, 0xF5, 0x8A,
- 0x6A, 0x6E, 0xC5, 0xD3, 0x8A, 0x01, 0x8E, 0xE7, 0x3A, 0x1E, 0xAE, 0x2F, 0x5E, 0xD1, 0xBC, 0x59,
- 0x76, 0x7C, 0x54, 0x0D, 0x60, 0x9C, 0xD9, 0xA4, 0xCC, 0x4B, 0x98, 0xAE, 0xAB, 0x93, 0x89, 0xB8,
- 0xE9, 0x76, 0x3A, 0x3F, 0xAC, 0x9E, 0x9C, 0x62, 0xEE, 0xA6, 0x28, 0x22, 0xFE, 0xF6, 0x11, 0xB1,
- 0x12, 0x56, 0x39, 0x3D, 0xFE, 0x35, 0xC3, 0x96, 0x83, 0xB4, 0x86, 0x14, 0xCE, 0xA7, 0x1D, 0xF0,
- 0xA9, 0xA6, 0x86, 0x3C, 0x4B, 0x6B, 0xF8, 0x81, 0x03, 0x81, 0x80, 0x58, 0xBA, 0x71, 0xE1, 0x17,
- 0x28, 0x1C, 0x73, 0xDC, 0x54, 0xA8, 0x5C, 0x12, 0x33, 0xB2, 0x45, 0xD4, 0x61, 0x43, 0x3F, 0x35,
- 0x52, 0x0E, 0xFD, 0x54, 0x06, 0x90, 0x42, 0x47, 0xC6, 0xBE, 0x0C, 0x2F, 0x59, 0xC2, 0x22, 0xCC,
- 0xE8, 0x67, 0x86, 0x2E, 0x5B, 0xA5, 0xD8, 0xC5, 0x83, 0x62, 0x0C, 0xA1, 0xCC, 0x9A, 0x0D, 0x18,
- 0xBA, 0x98, 0x6A, 0x2D, 0x8D, 0x66, 0xC9, 0xA6, 0x9A, 0x46, 0x30, 0x55, 0x43, 0x4E, 0x3F, 0xB2,
- 0x53, 0xAC, 0xA1, 0xAE, 0x5A, 0xD5, 0x34, 0x77, 0xF0, 0x3F, 0x95, 0x0F, 0x71, 0x4D, 0x0A, 0xB3,
- 0x08, 0xFD, 0xD4, 0xCF, 0x24, 0x29, 0xB3, 0xCA, 0x6C, 0xA2, 0x60, 0x5C, 0x9C, 0x51, 0x56, 0xF8,
- 0x16, 0x45, 0xB7, 0x82, 0x6B, 0xB9, 0x08, 0x75, 0xB3, 0x8B, 0x82, 0x71, 0x99, 0x0C, 0x95, 0x59,
- 0x86, 0x7E, 0xAE, 0x6B, 0xF4, 0x1B, 0x77, 0xC6, 0x11, 0x21, 0xBE, 0x17, 0x6E, 0x55, 0xA2, 0x8A,
- 0xE2, 0xEC, 0xAF, 0x28, 0x24, 0x8E, 0x7D, 0xD5, 0x12, 0x21, 0x0D, 0x71, 0x36, 0x47, 0xD0, 0x42,
- 0x8E, 0x31, 0x59, 0x62, 0x5C, 0xDE, 0x6E, 0x78, 0x68, 0x01, 0x79, 0x67, 0x32, 0x71, 0x55, 0xBE,
- 0x67, 0x46, 0x41, 0x48, 0xFB, 0xB6, 0xB9, 0xEF, 0x00, 0xE3, 0x60, 0x75, 0xE2, 0x6C, 0x0C, 0xD6,
- 0x9C, 0xA8, 0x65, 0x8E, 0x15, 0x73, 0xF9, 0x11, 0xA1, 0x36, 0x56, 0x22, 0xE1, 0x83, 0x3A, 0x0E,
- 0xB9, 0x52, 0x9E, 0x13, 0x91, 0xA8, 0x38, 0x13, 0x87, 0x60, 0x69, 0x59, 0xC8, 0xCA, 0x35, 0x30,
- 0xA7, 0xD8, 0xFC, 0x8C, 0xAD, 0x1F, 0x2B, 0xDB, 0xB0, 0xAA, 0xF6, 0xB0, 0xED, 0x78, 0xF3, 0x88,
- 0xB4, 0x68, 0x3B, 0x35, 0xBF, 0x11, 0xCC, 0x99, 0x43, 0xC6, 0x2A, 0xF6, 0x7A, 0x65, 0x4D, 0xC5,
- 0xFD, 0xF9, 0x65, 0xB9, 0x11, 0x64, 0x61, 0x0D, 0x17, 0x8D, 0xB1, 0x5B, 0x26, 0xB2, 0x08, 0x86,
- 0x82, 0xB4, 0x2B, 0x72, 0x55, 0x71, 0xEF, 0xC6, 0x24, 0x4B, 0x8B, 0x57, 0xFF, 0xC1, 0x0F, 0xB5,
- 0xED, 0xC8, 0x8E, 0x0F, 0x33, 0x3F, 0x85, 0xD8, 0x85, 0x00, 0x2B, 0x6A, 0xBD, 0x61, 0xCC, 0x12,
- 0x64, 0x28, 0x9D, 0x20, 0x40, 0xDE, 0x04, 0x43, 0x2E, 0xB8, 0x3C, 0x8C, 0x0F, 0xCB, 0x17, 0x06,
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+#define index_ov2640_html_gz_len 6687
+const unsigned char index_ov2640_html_gz[] = {
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+  0x90, 0xBA, 0x01, 0xAD, 0xBD, 0x5E, 0xB3, 0x13, 0x28, 0x81, 0x29, 0x26, 0x5B, 0xB3, 0x40, 0x97, 0xA3, 0xB9, 0x9D, 0x8C, 0x28, 0x12, 0x80, 0x6D, 0x4C, 0xFA,
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+  0xCE, 0x4C, 0xC9, 0x08, 0x10, 0x62, 0x2E, 0x91, 0x83, 0x48, 0xCF, 0x26, 0x46, 0x33, 0x78, 0x69, 0xCF, 0x5C, 0x9D, 0xC2, 0xFA, 0xD5, 0x67, 0x28, 0x07, 0x04,
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+  0x3F, 0xC2, 0x4B, 0x8F, 0xC1, 0x14, 0xF2, 0x68, 0xBD, 0xB3, 0x42, 0x72, 0x09, 0xE9, 0x12, 0xEA, 0x7A, 0x65, 0x33, 0xF2, 0xAE, 0x4A, 0x02, 0x95, 0xB4, 0x3A,
+  0x80, 0xD3, 0x2B, 0x29, 0x40, 0xAB, 0x10, 0xC4, 0x6A, 0x90, 0xCA, 0x92, 0xC9, 0xCA, 0x11, 0x05, 0x06, 0x5F, 0x16, 0x52, 0x6F, 0xB6, 0x82, 0x67, 0x4D, 0x15,
+  0x25, 0xA8, 0xD5, 0x65, 0x53, 0x9B, 0xB9, 0x95, 0xF2, 0x5C, 0x73, 0xAB, 0x8B, 0xAB, 0xAB, 0x48, 0xD4, 0xDA, 0xB1, 0x28, 0xA5, 0x46, 0x08, 0x39, 0x5E, 0xFA,
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+  0x8C, 0x79, 0x8B, 0x8E, 0x74, 0x5A, 0x54, 0xEA, 0xA4, 0xA7, 0x18, 0xD4, 0xDD, 0xEC, 0x64, 0xE1, 0xD5, 0x98, 0x1F, 0xDD, 0xD2, 0xD6, 0x40, 0xBC, 0xEE, 0x63,
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+  0x88, 0x5A, 0x04, 0x97, 0x96, 0x0B, 0xFD, 0xF4, 0x03, 0xC9, 0xB8, 0x84, 0x1B, 0x7A, 0x90, 0x2F, 0x4A, 0xEA, 0xB4, 0xF9, 0x3A, 0xBA, 0xFD, 0xDF, 0x16, 0x34,
+  0xFB, 0x1A, 0xD9, 0x78, 0x85, 0x8C, 0xB4, 0x44, 0x8E, 0x48, 0x25, 0xB2, 0x47, 0x19, 0x38, 0x50, 0x24, 0xBB, 0x30, 0xD2, 0x24, 0xA9, 0x91, 0x9E, 0xA7, 0x8A,
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+  0x9C, 0x59, 0x67, 0x77, 0xEF, 0x70, 0x77, 0x97, 0x1E, 0xAC, 0x3E, 0x66, 0x9D, 0xDE, 0x20, 0xCA, 0x82, 0x1F, 0x9E, 0x47, 0x54, 0x52, 0x7C, 0xFF, 0xAD, 0x87,
+  0x67, 0x08, 0x97, 0x65, 0x78, 0x6F, 0xBB, 0xD4, 0x0D, 0x96, 0x65, 0xB9, 0x64, 0x20, 0xAC, 0x95, 0xCB, 0xD2, 0xE2, 0xEB, 0xFE, 0xA2, 0xC1, 0x17, 0x5F, 0x0E,
+  0x05, 0x7F, 0x5B, 0xF1, 0xB4, 0xA5, 0xB3, 0x87, 0x35, 0x50, 0x9E, 0x8F, 0x1B, 0x6A, 0x28, 0x43, 0x92, 0x3B, 0x71, 0xA7, 0xE4, 0xF0, 0x3B, 0xC7, 0xFF, 0x8C,
+  0xAD, 0x91, 0x0E, 0x4A, 0x2E, 0xAC, 0x5C, 0xC7, 0x07, 0xD4, 0x3A, 0x37, 0xA5, 0xCE, 0x60, 0x3A, 0xF6, 0x9A, 0x1D, 0x76, 0xA6, 0x1D, 0xBF, 0x57, 0x4B, 0xA8,
+  0xE7, 0x3C, 0x32, 0x86, 0x22, 0x8D, 0xC6, 0x60, 0xB1, 0xD5, 0xC6, 0x98, 0xAC, 0xAC, 0x2B, 0xC1, 0x6D, 0xA5, 0xF3, 0x91, 0x03, 0xB8, 0x8A, 0x02, 0xCA, 0x71,
+  0xBB, 0x4A, 0x59, 0x65, 0x60, 0x58, 0xDA, 0x59, 0x67, 0x0F, 0x88, 0xE5, 0x20, 0x00, 0x35, 0xDF, 0x72, 0x35, 0x6E, 0x21, 0xDB, 0x8F, 0x7C, 0x82, 0x00, 0x64,
+  0xAF, 0xA8, 0x90, 0x1C, 0x33, 0x29, 0xD6, 0xAA, 0x60, 0xA4, 0x9B, 0x1F, 0xE5, 0x66, 0xCC, 0x58, 0xD1, 0xE8, 0x36, 0x3F, 0xB2, 0x8D, 0xCD, 0x1B, 0x68, 0x1D,
+  0x1D, 0xBC, 0x9D, 0x90, 0x90, 0x95, 0xD3, 0x9B, 0xA9, 0xF4, 0x8E, 0x46, 0xF8, 0x15, 0x25, 0xD4, 0xF3, 0xC1, 0x05, 0xB9, 0x58, 0x4D, 0x72, 0x31, 0x49, 0x2E,
+  0x2A, 0x90, 0x0C, 0x2F, 0xAB, 0xC3, 0x0D, 0xB1, 0xFC, 0xFF, 0xF2, 0x32, 0x69, 0xD9, 0xF5, 0xA8, 0x14, 0x4F, 0x39, 0x9C, 0x57, 0x9A, 0x57, 0x5E, 0x20, 0xF5,
+  0x10, 0x11, 0xD1, 0xAC, 0xEB, 0x51, 0xBD, 0x66, 0x45, 0xE1, 0x00, 0x2A, 0x90, 0x34, 0x4B, 0x1F, 0x34, 0x88, 0x9A, 0xF2, 0x9A, 0x85, 0x72, 0x07, 0x9B, 0xE9,
+  0x5A, 0x46, 0xFC, 0xD8, 0xDB, 0x18, 0xD9, 0x38, 0xA5, 0x0C, 0xE7, 0x38, 0x93, 0xF0, 0xBC, 0xE2, 0xBF, 0xB5, 0xD0, 0x8E, 0x73, 0x27, 0x22, 0x9C, 0x00, 0x88,
+  0x42, 0x15, 0x98, 0x5B, 0x48, 0x07, 0x9C, 0x84, 0x0F, 0x6F, 0x71, 0xEC, 0x33, 0x9E, 0xBA, 0x9A, 0x01, 0x87, 0x56, 0x7A, 0x53, 0x17, 0x90, 0x52, 0x79, 0x84,
+  0xA8, 0x0A, 0x6B, 0x11, 0xAF, 0x29, 0x96, 0x2B, 0x88, 0xC5, 0x3F, 0xF1, 0xC0, 0x71, 0x1C, 0x4C, 0x11, 0xCE, 0x9D, 0xE1, 0x17, 0xFF, 0x06, 0x6E, 0xDA, 0x6F,
+  0xC1, 0x5F, 0xA4, 0x00, 0x00
 };
 
-
-//File: index_ov3660.html.gz, Size: 4408
-#define index_ov3660_html_gz_len 4408
-const uint8_t index_ov3660_html_gz[] = {
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+//File: index_ov3660.html.gz, Size: 8636
+#define index_ov3660_html_gz_len 8636
+const unsigned char index_ov3660_html_gz[] = {
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 };
 
+//File: index_ov5640.html.gz, Size: 8880
+#define index_ov5640_html_gz_len 8880
+const unsigned char index_ov5640_html_gz[] = {
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+  0xFF, 0x6C, 0x55, 0x3A, 0x1E, 0x39, 0x62, 0xFC, 0x8F, 0x45, 0x09, 0xF0, 0xF0, 0xD2, 0x88, 0x14, 0x1A, 0xFE, 0xA1, 0xA3, 0x54, 0x2C, 0x72, 0xC4, 0xF0, 0x6F,
+  0x0B, 0x89, 0x78, 0xE2, 0xA5, 0x18, 0x39, 0x9E, 0xF8, 0x27, 0x71, 0xD2, 0xF1, 0x48, 0xCA, 0x86, 0x7F, 0x86, 0x46, 0x64, 0x75, 0xAC, 0xF2, 0x93, 0xE9, 0x18,
+  0xAC, 0x09, 0x00, 0xF3, 0x54, 0xF5, 0xB9, 0x1A, 0xCD, 0xAC, 0x79, 0xA1, 0x28, 0x0B, 0x03, 0x6F, 0x92, 0xC4, 0xE0, 0x47, 0x87, 0x7B, 0x28, 0xD9, 0xDD, 0x47,
+  0x14, 0x7A, 0x6F, 0x9A, 0x72, 0x51, 0x68, 0x69, 0x9A, 0x7E, 0xF8, 0x09, 0x60, 0x52, 0xC2, 0x0F, 0x5D, 0x32, 0xA3, 0xF5, 0xD6, 0x4C, 0xF9, 0xD3, 0x16, 0x0C,
+  0xEF, 0xA6, 0x12, 0x11, 0xC7, 0x62, 0x65, 0x4A, 0x59, 0x12, 0xB4, 0xE3, 0x68, 0xA2, 0x86, 0x44, 0x97, 0xE3, 0x6E, 0x5D, 0xB9, 0xD0, 0x75, 0xEB, 0xA6, 0x60,
+  0xA0, 0x25, 0x61, 0xB9, 0xDC, 0x0C, 0x5A, 0xA6, 0x20, 0x59, 0x3A, 0x72, 0xE9, 0x1D, 0xB4, 0x4B, 0x63, 0x04, 0xEB, 0xCF, 0x72, 0xAC, 0xF8, 0x5F, 0x1D, 0x17,
+  0xD1, 0x41, 0xAB, 0xD6, 0x59, 0x4A, 0xE1, 0x5F, 0x77, 0x4E, 0xD3, 0xC8, 0x52, 0x76, 0xC8, 0xF5, 0xBF, 0x7F, 0x2C, 0x18, 0x76, 0x4B, 0x16, 0xFB, 0xF7, 0xEF,
+  0x1C, 0xDA, 0x35, 0x91, 0x70, 0x8D, 0x60, 0x65, 0x9E, 0x67, 0x77, 0x21, 0x58, 0x86, 0x77, 0x4C, 0x34, 0xEB, 0x5A, 0x8B, 0x79, 0xC7, 0x04, 0xA6, 0xBF, 0x1E,
+  0xE1, 0xA8, 0x1B, 0x35, 0xD6, 0xA0, 0xC6, 0x69, 0x64, 0x67, 0x6D, 0xBA, 0x65, 0x0D, 0x0B, 0x21, 0x06, 0x59, 0xB3, 0x93, 0xD8, 0xED, 0x39, 0xA1, 0xAF, 0x09,
+  0xE1, 0xF7, 0xD9, 0x19, 0x6B, 0x10, 0xF4, 0x32, 0xB6, 0xF5, 0xDB, 0xB6, 0xB6, 0x5C, 0x42, 0xF0, 0xBA, 0x98, 0x1B, 0xA6, 0xDE, 0x60, 0xA0, 0x11, 0x13, 0xC1,
+  0xBD, 0x09, 0x84, 0xAE, 0x5A, 0x71, 0xAC, 0xC0, 0xF0, 0x05, 0xBB, 0xD6, 0xA8, 0x77, 0x75, 0x7F, 0xCD, 0x88, 0x37, 0x6B, 0xEB, 0x8E, 0xB6, 0xFE, 0x1E, 0x37,
+  0x35, 0x34, 0xB0, 0xD3, 0x83, 0xCE, 0x41, 0x87, 0x37, 0xF0, 0x9C, 0xDB, 0x20, 0xCB, 0x44, 0xBC, 0xB8, 0xF8, 0xFB, 0xD3, 0x87, 0xB7, 0x21, 0x5E, 0xCF, 0x7E,
+  0xC5, 0x2E, 0x35, 0xEA, 0x74, 0x57, 0xC4, 0xE1, 0x9F, 0x4B, 0x9C, 0x0A, 0xF8, 0x4A, 0x89, 0x88, 0x11, 0x37, 0x3C, 0xA0, 0xA8, 0x58, 0xF3, 0x67, 0x51, 0xA4,
+  0x70, 0xD9, 0x22, 0x6B, 0x05, 0x30, 0x91, 0x86, 0x08, 0xD4, 0xDF, 0x0E, 0x81, 0xE0, 0xC8, 0xC9, 0x77, 0x2B, 0xD3, 0xFC, 0x95, 0x68, 0x0E, 0xE8, 0xE3, 0xA9,
+  0xD2, 0xA8, 0x75, 0x6A, 0x4F, 0x1B, 0xF4, 0xFA, 0x3B, 0x60, 0x67, 0xDE, 0x68, 0x3E, 0x55, 0x9B, 0xCD, 0xB6, 0x0B, 0x3A, 0x23, 0x8D, 0x56, 0xD7, 0x6F, 0x02,
+  0x7F, 0x68, 0x1B, 0xD6, 0x49, 0xFA, 0xFD, 0x37, 0xF6, 0xCA, 0x71, 0xB3, 0x1A, 0xBC, 0x33, 0x2C, 0x2C, 0xE2, 0x64, 0x35, 0xB9, 0x22, 0x20, 0x58, 0x7D, 0xA3,
+  0x49, 0x8D, 0xEE, 0xE2, 0xE0, 0xE5, 0x0F, 0x85, 0x2E, 0x6E, 0x2B, 0x8D, 0x68, 0x45, 0x87, 0x2F, 0x23, 0x12, 0x34, 0xF4, 0x86, 0xEF, 0xF1, 0x77, 0x51, 0xE3,
+  0x00, 0x97, 0x05, 0x03, 0xF8, 0x01, 0x3C, 0xA0, 0xED, 0x90, 0x85, 0x7D, 0x4D, 0x36, 0xF4, 0x8F, 0xCD, 0x03, 0xE3, 0x9F, 0x1B, 0x3A, 0x2B, 0xD3, 0x84, 0x76,
+  0x8B, 0x55, 0x21, 0xDC, 0x20, 0x82, 0x5B, 0x28, 0x70, 0x3F, 0x45, 0xA3, 0xCE, 0x76, 0xAF, 0xD0, 0x51, 0xE1, 0x2E, 0x74, 0x9B, 0xB9, 0xBD, 0xCE, 0x82, 0x64,
+  0xBD, 0x27, 0x80, 0x03, 0x68, 0xDD, 0x70, 0xB5, 0xB1, 0x99, 0xDF, 0x35, 0x6F, 0xA7, 0xF3, 0xF2, 0x37, 0x34, 0xF0, 0xAF, 0x00, 0xA8, 0xE7, 0xD0, 0x3A, 0x61,
+  0x04, 0x2D, 0xB1, 0xF2, 0xB0, 0xFA, 0x64, 0x65, 0x22, 0x9E, 0x6A, 0x30, 0x79, 0x8A, 0x63, 0x66, 0xC5, 0xE3, 0x02, 0x65, 0xE5, 0xE8, 0x65, 0x80, 0x88, 0x9F,
+  0x82, 0x39, 0x83, 0x85, 0x2A, 0xCF, 0x29, 0x0B, 0xCA, 0x69, 0xEC, 0x6E, 0x90, 0xDB, 0x44, 0x0B, 0xA6, 0x8F, 0x58, 0xFC, 0xFB, 0x0B, 0x56, 0x70, 0x03, 0xCA,
+  0x63, 0x12, 0x78, 0xF2, 0x24, 0x8E, 0x0D, 0xB7, 0xB1, 0xB0, 0x01, 0x24, 0xE8, 0x8D, 0xB5, 0x67, 0xAF, 0x0F, 0x0F, 0x57, 0x16, 0x38, 0x49, 0x30, 0x14, 0x3C,
+  0x8E, 0x09, 0x3E, 0x32, 0x46, 0x00, 0x21, 0x86, 0x4E, 0x05, 0x84, 0xBB, 0xD2, 0x6A, 0x1B, 0xEB, 0xFD, 0xCF, 0xA9, 0xD5, 0x37, 0x08, 0xDF, 0x94, 0xD8, 0x04,
+  0xF9, 0xA3, 0x31, 0x87, 0x17, 0xE2, 0x73, 0xE8, 0x04, 0xC6, 0x59, 0x0C, 0x23, 0x32, 0x96, 0xA0, 0x1B, 0x7F, 0x87, 0x87, 0x14, 0xE3, 0x4C, 0x33, 0xAC, 0x0B,
+  0x62, 0x60, 0xFA, 0xD7, 0x8C, 0xDC, 0xA5, 0xDD, 0x03, 0x22, 0xDC, 0x30, 0x18, 0x59, 0xCE, 0xD8, 0x5C, 0x0F, 0x39, 0x3C, 0xA4, 0x4D, 0x53, 0xD0, 0xD0, 0x2E,
+  0x36, 0xD1, 0x64, 0x52, 0xBF, 0x1E, 0x7F, 0x46, 0x6C, 0x22, 0xA1, 0x50, 0x74, 0xEB, 0x31, 0x8A, 0x83, 0xF6, 0x0A, 0x87, 0xF1, 0x81, 0xD3, 0x77, 0x88, 0x60,
+  0xC1, 0x3B, 0xAA, 0x21, 0x56, 0x90, 0x0F, 0xA7, 0xA5, 0xA1, 0x09, 0x6C, 0xA9, 0x3E, 0xAD, 0x62, 0x71, 0x3A, 0x68, 0x12, 0xAD, 0x22, 0x57, 0x2C, 0x4D, 0x67,
+  0xE0, 0x64, 0x5B, 0xEE, 0x92, 0x48, 0x57, 0xE3, 0x85, 0xE1, 0x09, 0x10, 0xD6, 0xD5, 0xBA, 0x10, 0x57, 0x4A, 0x95, 0x3B, 0xEA, 0x1F, 0x2C, 0xC6, 0xD0, 0x05,
+  0x40, 0x40, 0x14, 0x5B, 0xC0, 0x9F, 0xB0, 0x3D, 0xE4, 0xCF, 0x61, 0x1C, 0xC4, 0x65, 0x79, 0xD4, 0x65, 0x62, 0x63, 0x0E, 0x43, 0xC1, 0x76, 0x94, 0x51, 0x14,
+  0xF1, 0x3D, 0x65, 0xFE, 0x3E, 0xAE, 0xF8, 0x7A, 0x61, 0x74, 0x47, 0xCA, 0x1F, 0x0E, 0x01, 0x38, 0x17, 0x67, 0x99, 0xCA, 0xB7, 0x5F, 0x29, 0x8A, 0x3B, 0x65,
+  0x0A, 0xFE, 0xE9, 0xCE, 0x89, 0x4E, 0x67, 0x44, 0xDE, 0xCA, 0x3D, 0x55, 0x70, 0x33, 0x4E, 0x6C, 0x0F, 0xD9, 0xDD, 0x1F, 0x81, 0x85, 0x04, 0xE1, 0x3D, 0x5C,
+  0x05, 0xE5, 0x6C, 0x6F, 0xAC, 0x86, 0x3E, 0x92, 0x58, 0xF7, 0xE4, 0xB0, 0x52, 0x6B, 0x9F, 0xA2, 0x25, 0xC3, 0x64, 0xEC, 0xE0, 0x99, 0xDF, 0x23, 0x99, 0xBE,
+  0xE9, 0x5E, 0x48, 0x99, 0x2E, 0x05, 0x39, 0x1F, 0xFE, 0x58, 0x70, 0x31, 0x23, 0x23, 0x71, 0xC2, 0x8F, 0x9A, 0x5C, 0x4E, 0x60, 0x22, 0xBA, 0x1F, 0x05, 0x99,
+  0x11, 0xE1, 0x9A, 0x30, 0xD3, 0x63, 0xCC, 0x04, 0x98, 0xB4, 0xB9, 0xB0, 0xF3, 0x37, 0x0A, 0xF2, 0xC5, 0x90, 0x40, 0x59, 0x7F, 0xBA, 0x90, 0x4D, 0x07, 0x22,
+  0x10, 0xE1, 0xC0, 0x0E, 0x22, 0x08, 0x62, 0x22, 0x2A, 0xA4, 0xA2, 0x0C, 0x99, 0xB1, 0x5F, 0x64, 0x18, 0xA5, 0x63, 0x28, 0xED, 0xF9, 0x37, 0x6A, 0xD5, 0xBF,
+  0x1F, 0xB0, 0x71, 0x37, 0x12, 0xCA, 0x9A, 0x45, 0x08, 0xDA, 0x58, 0x2B, 0xCF, 0x25, 0x66, 0x6B, 0xAB, 0x86, 0xFE, 0x0F, 0x82, 0x2D, 0xC5, 0x77, 0xAE, 0x74,
+  0x36, 0x56, 0xCB, 0xA3, 0x4B, 0x5B, 0x01, 0x83, 0x02, 0xD9, 0x44, 0x96, 0xBA, 0x7D, 0xF1, 0x08, 0x97, 0xB5, 0x52, 0xC5, 0xC5, 0xEC, 0x8B, 0x45, 0x14, 0x4C,
+  0xD6, 0x33, 0x67, 0x35, 0x74, 0x1B, 0x2B, 0x95, 0x57, 0x08, 0x70, 0x11, 0x6C, 0x5B, 0xCE, 0x85, 0x0C, 0xB7, 0x38, 0x47, 0x70, 0xD0, 0x59, 0x92, 0xDC, 0xAA,
+  0x00, 0x9F, 0x50, 0x45, 0x40, 0x11, 0x6B, 0x3E, 0xAC, 0xFF, 0xEC, 0x4A, 0x92, 0x7C, 0xEA, 0xBB, 0xF9, 0xE0, 0xD1, 0xED, 0xCE, 0xF5, 0x88, 0xB8, 0x5C, 0xCF,
+  0x5E, 0x5E, 0xD1, 0xAB, 0x09, 0xBF, 0x5E, 0xD3, 0x22, 0x51, 0x1B, 0xEF, 0xFB, 0xF3, 0x8F, 0x28, 0xA9, 0xF1, 0xBA, 0xFA, 0x15, 0x56, 0x90, 0x14, 0x86, 0xA7,
+  0x9E, 0x98, 0x6B, 0xE2, 0x2D, 0x61, 0x0F, 0x74, 0x2E, 0xE7, 0x3A, 0x13, 0x16, 0xFE, 0x83, 0xED, 0xC5, 0xE8, 0xFC, 0x78, 0xF8, 0x07, 0xEB, 0x13, 0x87, 0xE8,
+  0x98, 0x8A, 0x9A, 0xB9, 0xB4, 0xD8, 0xCB, 0x24, 0x29, 0x61, 0x88, 0x66, 0xEE, 0xE2, 0x62, 0xDC, 0x67, 0x43, 0x1D, 0x06, 0xA0, 0x88, 0xFA, 0x52, 0xA2, 0x5C,
+  0x28, 0x26, 0x1E, 0x56, 0xE2, 0xC4, 0x47, 0xC6, 0x2E, 0xB6, 0x37, 0xFD, 0xF9, 0xE7, 0xC9, 0x18, 0x86, 0x2B, 0x9C, 0x58, 0x81, 0xF3, 0xAC, 0x1B, 0xCD, 0xBB,
+  0x2C, 0x76, 0x98, 0xB8, 0x42, 0x45, 0xCA, 0x12, 0x41, 0xE3, 0xAE, 0x18, 0x5B, 0x4C, 0x3E, 0x62, 0x74, 0x51, 0xFB, 0xBB, 0xB4, 0xFC, 0x89, 0x40, 0x9A, 0x60,
+  0xCF, 0x37, 0x45, 0xCB, 0x72, 0xC1, 0x18, 0x82, 0x30, 0xA2, 0x6E, 0x10, 0x9B, 0x48, 0xF6, 0x22, 0x76, 0xE1, 0x37, 0x88, 0x68, 0xEB, 0x62, 0x05, 0xF0, 0x0B,
+  0x5F, 0x5B, 0xEC, 0x1A, 0x26, 0x7D, 0x81, 0x59, 0x41, 0x12, 0x98, 0x65, 0xEE, 0x70, 0x3B, 0xE2, 0x23, 0x3C, 0x63, 0xCC, 0x01, 0xA0, 0x69, 0x22, 0x7B, 0x36,
+  0x84, 0xC2, 0xB2, 0x3D, 0xAC, 0x9E, 0x12, 0xC9, 0x45, 0x33, 0x9D, 0x1B, 0x9A, 0x4D, 0x58, 0xB3, 0x08, 0x12, 0xC0, 0xBB, 0x39, 0x56, 0x47, 0xA7, 0x4B, 0x7C,
+  0xC4, 0x86, 0x76, 0xCD, 0x40, 0xA4, 0x08, 0xC4, 0xD3, 0xC0, 0x50, 0xA0, 0xE9, 0x09, 0xF6, 0x66, 0x72, 0x9D, 0x90, 0x75, 0x7A, 0x52, 0xBD, 0x99, 0x50, 0x47,
+  0xB5, 0xE0, 0x3F, 0xC4, 0x14, 0x0A, 0x92, 0x64, 0x4B, 0x9D, 0x44, 0xA5, 0xEE, 0x4F, 0x2E, 0x72, 0x20, 0x3E, 0xD3, 0x3C, 0x20, 0x2A, 0x32, 0x22, 0x29, 0x32,
+  0xC2, 0x45, 0x86, 0x00, 0x61, 0xD6, 0x9C, 0x3F, 0xD3, 0x09, 0x42, 0xC2, 0xCF, 0x2F, 0x43, 0xCE, 0xD6, 0xE3, 0x4C, 0x3A, 0xF9, 0x2C, 0x22, 0xC2, 0x5E, 0x36,
+  0x00, 0xB4, 0x5F, 0xC0, 0xA0, 0x19, 0x65, 0x6B, 0x3D, 0x96, 0x63, 0xCB, 0x9F, 0x85, 0x20, 0x40, 0xC8, 0x96, 0x78, 0xAE, 0xE2, 0xB3, 0xF2, 0x8A, 0x78, 0xFC,
+  0x51, 0x47, 0xCD, 0xD2, 0x95, 0xA9, 0xA3, 0x2D, 0x08, 0x7E, 0xD9, 0x3E, 0x20, 0x36, 0xB8, 0x92, 0x45, 0x73, 0xD0, 0x88, 0x0D, 0x10, 0xC1, 0xA9, 0x14, 0xD9,
+  0x41, 0xEB, 0xD0, 0x8C, 0x43, 0x04, 0x6C, 0xBE, 0x30, 0x52, 0x06, 0xC9, 0xB9, 0x2E, 0x1B, 0xF7, 0x75, 0x4A, 0x7D, 0x62, 0x74, 0x8F, 0x36, 0x70, 0xC8, 0xC4,
+  0x9E, 0x59, 0x80, 0x29, 0xD6, 0x86, 0x99, 0x2A, 0x1B, 0xFC, 0xD9, 0xEF, 0xEC, 0xD0, 0x7F, 0x3C, 0x86, 0x9D, 0x61, 0x51, 0x70, 0xF4, 0xE8, 0xEC, 0x70, 0xEE,
+  0x2D, 0xCC, 0xD1, 0xA3, 0xFF, 0x05, 0xDF, 0x19, 0xEB, 0xA3, 0xC1, 0x08, 0x01, 0x00
+
+};
diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/camera_pins.h b/libraries/ESP32/examples/Camera/CameraWebServer/camera_pins.h
index f6ffd33b8d2..34085086769 100644
--- a/libraries/ESP32/examples/Camera/CameraWebServer/camera_pins.h
+++ b/libraries/ESP32/examples/Camera/CameraWebServer/camera_pins.h
@@ -1,155 +1,337 @@
 
 #if defined(CAMERA_MODEL_WROVER_KIT)
-#define PWDN_GPIO_NUM    -1
-#define RESET_GPIO_NUM   -1
-#define XCLK_GPIO_NUM    21
-#define SIOD_GPIO_NUM    26
-#define SIOC_GPIO_NUM    27
-
-#define Y9_GPIO_NUM      35
-#define Y8_GPIO_NUM      34
-#define Y7_GPIO_NUM      39
-#define Y6_GPIO_NUM      36
-#define Y5_GPIO_NUM      19
-#define Y4_GPIO_NUM      18
-#define Y3_GPIO_NUM       5
-#define Y2_GPIO_NUM       4
-#define VSYNC_GPIO_NUM   25
-#define HREF_GPIO_NUM    23
-#define PCLK_GPIO_NUM    22
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM -1
+#define XCLK_GPIO_NUM  21
+#define SIOD_GPIO_NUM  26
+#define SIOC_GPIO_NUM  27
+
+#define Y9_GPIO_NUM    35
+#define Y8_GPIO_NUM    34
+#define Y7_GPIO_NUM    39
+#define Y6_GPIO_NUM    36
+#define Y5_GPIO_NUM    19
+#define Y4_GPIO_NUM    18
+#define Y3_GPIO_NUM    5
+#define Y2_GPIO_NUM    4
+#define VSYNC_GPIO_NUM 25
+#define HREF_GPIO_NUM  23
+#define PCLK_GPIO_NUM  22
 
 #elif defined(CAMERA_MODEL_ESP_EYE)
-#define PWDN_GPIO_NUM    -1
-#define RESET_GPIO_NUM   -1
-#define XCLK_GPIO_NUM    4
-#define SIOD_GPIO_NUM    18
-#define SIOC_GPIO_NUM    23
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM -1
+#define XCLK_GPIO_NUM  4
+#define SIOD_GPIO_NUM  18
+#define SIOC_GPIO_NUM  23
+
+#define Y9_GPIO_NUM    36
+#define Y8_GPIO_NUM    37
+#define Y7_GPIO_NUM    38
+#define Y6_GPIO_NUM    39
+#define Y5_GPIO_NUM    35
+#define Y4_GPIO_NUM    14
+#define Y3_GPIO_NUM    13
+#define Y2_GPIO_NUM    34
+#define VSYNC_GPIO_NUM 5
+#define HREF_GPIO_NUM  27
+#define PCLK_GPIO_NUM  25
 
-#define Y9_GPIO_NUM      36
-#define Y8_GPIO_NUM      37
-#define Y7_GPIO_NUM      38
-#define Y6_GPIO_NUM      39
-#define Y5_GPIO_NUM      35
-#define Y4_GPIO_NUM      14
-#define Y3_GPIO_NUM      13
-#define Y2_GPIO_NUM      34
-#define VSYNC_GPIO_NUM   5
-#define HREF_GPIO_NUM    27
-#define PCLK_GPIO_NUM    25
+#define LED_GPIO_NUM 22
 
 #elif defined(CAMERA_MODEL_M5STACK_PSRAM)
-#define PWDN_GPIO_NUM     -1
-#define RESET_GPIO_NUM    15
-#define XCLK_GPIO_NUM     27
-#define SIOD_GPIO_NUM     25
-#define SIOC_GPIO_NUM     23
-
-#define Y9_GPIO_NUM       19
-#define Y8_GPIO_NUM       36
-#define Y7_GPIO_NUM       18
-#define Y6_GPIO_NUM       39
-#define Y5_GPIO_NUM        5
-#define Y4_GPIO_NUM       34
-#define Y3_GPIO_NUM       35
-#define Y2_GPIO_NUM       32
-#define VSYNC_GPIO_NUM    22
-#define HREF_GPIO_NUM     26
-#define PCLK_GPIO_NUM     21
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM 15
+#define XCLK_GPIO_NUM  27
+#define SIOD_GPIO_NUM  25
+#define SIOC_GPIO_NUM  23
+
+#define Y9_GPIO_NUM    19
+#define Y8_GPIO_NUM    36
+#define Y7_GPIO_NUM    18
+#define Y6_GPIO_NUM    39
+#define Y5_GPIO_NUM    5
+#define Y4_GPIO_NUM    34
+#define Y3_GPIO_NUM    35
+#define Y2_GPIO_NUM    32
+#define VSYNC_GPIO_NUM 22
+#define HREF_GPIO_NUM  26
+#define PCLK_GPIO_NUM  21
 
 #elif defined(CAMERA_MODEL_M5STACK_V2_PSRAM)
-#define PWDN_GPIO_NUM     -1
-#define RESET_GPIO_NUM    15
-#define XCLK_GPIO_NUM     27
-#define SIOD_GPIO_NUM     22
-#define SIOC_GPIO_NUM     23
-
-#define Y9_GPIO_NUM       19
-#define Y8_GPIO_NUM       36
-#define Y7_GPIO_NUM       18
-#define Y6_GPIO_NUM       39
-#define Y5_GPIO_NUM        5
-#define Y4_GPIO_NUM       34
-#define Y3_GPIO_NUM       35
-#define Y2_GPIO_NUM       32
-#define VSYNC_GPIO_NUM    25
-#define HREF_GPIO_NUM     26
-#define PCLK_GPIO_NUM     21
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM 15
+#define XCLK_GPIO_NUM  27
+#define SIOD_GPIO_NUM  22
+#define SIOC_GPIO_NUM  23
+
+#define Y9_GPIO_NUM    19
+#define Y8_GPIO_NUM    36
+#define Y7_GPIO_NUM    18
+#define Y6_GPIO_NUM    39
+#define Y5_GPIO_NUM    5
+#define Y4_GPIO_NUM    34
+#define Y3_GPIO_NUM    35
+#define Y2_GPIO_NUM    32
+#define VSYNC_GPIO_NUM 25
+#define HREF_GPIO_NUM  26
+#define PCLK_GPIO_NUM  21
 
 #elif defined(CAMERA_MODEL_M5STACK_WIDE)
-#define PWDN_GPIO_NUM     -1
-#define RESET_GPIO_NUM    15
-#define XCLK_GPIO_NUM     27
-#define SIOD_GPIO_NUM     22
-#define SIOC_GPIO_NUM     23
-
-#define Y9_GPIO_NUM       19
-#define Y8_GPIO_NUM       36
-#define Y7_GPIO_NUM       18
-#define Y6_GPIO_NUM       39
-#define Y5_GPIO_NUM        5
-#define Y4_GPIO_NUM       34
-#define Y3_GPIO_NUM       35
-#define Y2_GPIO_NUM       32
-#define VSYNC_GPIO_NUM    25
-#define HREF_GPIO_NUM     26
-#define PCLK_GPIO_NUM     21
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM 15
+#define XCLK_GPIO_NUM  27
+#define SIOD_GPIO_NUM  22
+#define SIOC_GPIO_NUM  23
+
+#define Y9_GPIO_NUM    19
+#define Y8_GPIO_NUM    36
+#define Y7_GPIO_NUM    18
+#define Y6_GPIO_NUM    39
+#define Y5_GPIO_NUM    5
+#define Y4_GPIO_NUM    34
+#define Y3_GPIO_NUM    35
+#define Y2_GPIO_NUM    32
+#define VSYNC_GPIO_NUM 25
+#define HREF_GPIO_NUM  26
+#define PCLK_GPIO_NUM  21
+
+#define LED_GPIO_NUM 2
 
 #elif defined(CAMERA_MODEL_M5STACK_ESP32CAM)
-#define PWDN_GPIO_NUM     -1
-#define RESET_GPIO_NUM    15
-#define XCLK_GPIO_NUM     27
-#define SIOD_GPIO_NUM     25
-#define SIOC_GPIO_NUM     23
-
-#define Y9_GPIO_NUM       19
-#define Y8_GPIO_NUM       36
-#define Y7_GPIO_NUM       18
-#define Y6_GPIO_NUM       39
-#define Y5_GPIO_NUM        5
-#define Y4_GPIO_NUM       34
-#define Y3_GPIO_NUM       35
-#define Y2_GPIO_NUM       17
-#define VSYNC_GPIO_NUM    22
-#define HREF_GPIO_NUM     26
-#define PCLK_GPIO_NUM     21
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM 15
+#define XCLK_GPIO_NUM  27
+#define SIOD_GPIO_NUM  25
+#define SIOC_GPIO_NUM  23
+
+#define Y9_GPIO_NUM    19
+#define Y8_GPIO_NUM    36
+#define Y7_GPIO_NUM    18
+#define Y6_GPIO_NUM    39
+#define Y5_GPIO_NUM    5
+#define Y4_GPIO_NUM    34
+#define Y3_GPIO_NUM    35
+#define Y2_GPIO_NUM    17
+#define VSYNC_GPIO_NUM 22
+#define HREF_GPIO_NUM  26
+#define PCLK_GPIO_NUM  21
+
+#elif defined(CAMERA_MODEL_M5STACK_UNITCAM)
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM 15
+#define XCLK_GPIO_NUM  27
+#define SIOD_GPIO_NUM  25
+#define SIOC_GPIO_NUM  23
+
+#define Y9_GPIO_NUM    19
+#define Y8_GPIO_NUM    36
+#define Y7_GPIO_NUM    18
+#define Y6_GPIO_NUM    39
+#define Y5_GPIO_NUM    5
+#define Y4_GPIO_NUM    34
+#define Y3_GPIO_NUM    35
+#define Y2_GPIO_NUM    32
+#define VSYNC_GPIO_NUM 22
+#define HREF_GPIO_NUM  26
+#define PCLK_GPIO_NUM  21
+
+#elif defined(CAMERA_MODEL_M5STACK_CAMS3_UNIT)
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM 21
+#define XCLK_GPIO_NUM  11
+#define SIOD_GPIO_NUM  17
+#define SIOC_GPIO_NUM  41
+
+#define Y9_GPIO_NUM    13
+#define Y8_GPIO_NUM    4
+#define Y7_GPIO_NUM    10
+#define Y6_GPIO_NUM    5
+#define Y5_GPIO_NUM    7
+#define Y4_GPIO_NUM    16
+#define Y3_GPIO_NUM    15
+#define Y2_GPIO_NUM    6
+#define VSYNC_GPIO_NUM 42
+#define HREF_GPIO_NUM  18
+#define PCLK_GPIO_NUM  12
+
+#define LED_GPIO_NUM 14
 
 #elif defined(CAMERA_MODEL_AI_THINKER)
-#define PWDN_GPIO_NUM     32
-#define RESET_GPIO_NUM    -1
-#define XCLK_GPIO_NUM      0
-#define SIOD_GPIO_NUM     26
-#define SIOC_GPIO_NUM     27
-
-#define Y9_GPIO_NUM       35
-#define Y8_GPIO_NUM       34
-#define Y7_GPIO_NUM       39
-#define Y6_GPIO_NUM       36
-#define Y5_GPIO_NUM       21
-#define Y4_GPIO_NUM       19
-#define Y3_GPIO_NUM       18
-#define Y2_GPIO_NUM        5
-#define VSYNC_GPIO_NUM    25
-#define HREF_GPIO_NUM     23
-#define PCLK_GPIO_NUM     22
+#define PWDN_GPIO_NUM  32
+#define RESET_GPIO_NUM -1
+#define XCLK_GPIO_NUM  0
+#define SIOD_GPIO_NUM  26
+#define SIOC_GPIO_NUM  27
+
+#define Y9_GPIO_NUM    35
+#define Y8_GPIO_NUM    34
+#define Y7_GPIO_NUM    39
+#define Y6_GPIO_NUM    36
+#define Y5_GPIO_NUM    21
+#define Y4_GPIO_NUM    19
+#define Y3_GPIO_NUM    18
+#define Y2_GPIO_NUM    5
+#define VSYNC_GPIO_NUM 25
+#define HREF_GPIO_NUM  23
+#define PCLK_GPIO_NUM  22
+
+// 4 for flash led or 33 for normal led
+#define LED_GPIO_NUM   4
 
 #elif defined(CAMERA_MODEL_TTGO_T_JOURNAL)
-#define PWDN_GPIO_NUM      0
-#define RESET_GPIO_NUM    15
-#define XCLK_GPIO_NUM     27
-#define SIOD_GPIO_NUM     25
-#define SIOC_GPIO_NUM     23
-
-#define Y9_GPIO_NUM       19
-#define Y8_GPIO_NUM       36
-#define Y7_GPIO_NUM       18
-#define Y6_GPIO_NUM       39
-#define Y5_GPIO_NUM        5
-#define Y4_GPIO_NUM       34
-#define Y3_GPIO_NUM       35
-#define Y2_GPIO_NUM       17
-#define VSYNC_GPIO_NUM    22
-#define HREF_GPIO_NUM     26
-#define PCLK_GPIO_NUM     21
+#define PWDN_GPIO_NUM  0
+#define RESET_GPIO_NUM 15
+#define XCLK_GPIO_NUM  27
+#define SIOD_GPIO_NUM  25
+#define SIOC_GPIO_NUM  23
+
+#define Y9_GPIO_NUM    19
+#define Y8_GPIO_NUM    36
+#define Y7_GPIO_NUM    18
+#define Y6_GPIO_NUM    39
+#define Y5_GPIO_NUM    5
+#define Y4_GPIO_NUM    34
+#define Y3_GPIO_NUM    35
+#define Y2_GPIO_NUM    17
+#define VSYNC_GPIO_NUM 22
+#define HREF_GPIO_NUM  26
+#define PCLK_GPIO_NUM  21
+
+#elif defined(CAMERA_MODEL_XIAO_ESP32S3)
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM -1
+#define XCLK_GPIO_NUM  10
+#define SIOD_GPIO_NUM  40
+#define SIOC_GPIO_NUM  39
+
+#define Y9_GPIO_NUM    48
+#define Y8_GPIO_NUM    11
+#define Y7_GPIO_NUM    12
+#define Y6_GPIO_NUM    14
+#define Y5_GPIO_NUM    16
+#define Y4_GPIO_NUM    18
+#define Y3_GPIO_NUM    17
+#define Y2_GPIO_NUM    15
+#define VSYNC_GPIO_NUM 38
+#define HREF_GPIO_NUM  47
+#define PCLK_GPIO_NUM  13
+
+#elif defined(CAMERA_MODEL_ESP32_CAM_BOARD)
+// The 18 pin header on the board has Y5 and Y3 swapped
+#define USE_BOARD_HEADER 0
+#define PWDN_GPIO_NUM    32
+#define RESET_GPIO_NUM   33
+#define XCLK_GPIO_NUM    4
+#define SIOD_GPIO_NUM    18
+#define SIOC_GPIO_NUM    23
+
+#define Y9_GPIO_NUM 36
+#define Y8_GPIO_NUM 19
+#define Y7_GPIO_NUM 21
+#define Y6_GPIO_NUM 39
+#if USE_BOARD_HEADER
+#define Y5_GPIO_NUM 13
+#else
+#define Y5_GPIO_NUM 35
+#endif
+#define Y4_GPIO_NUM 14
+#if USE_BOARD_HEADER
+#define Y3_GPIO_NUM 35
+#else
+#define Y3_GPIO_NUM 13
+#endif
+#define Y2_GPIO_NUM    34
+#define VSYNC_GPIO_NUM 5
+#define HREF_GPIO_NUM  27
+#define PCLK_GPIO_NUM  25
+
+#elif defined(CAMERA_MODEL_ESP32S3_CAM_LCD)
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM -1
+#define XCLK_GPIO_NUM  40
+#define SIOD_GPIO_NUM  17
+#define SIOC_GPIO_NUM  18
+
+#define Y9_GPIO_NUM    39
+#define Y8_GPIO_NUM    41
+#define Y7_GPIO_NUM    42
+#define Y6_GPIO_NUM    12
+#define Y5_GPIO_NUM    3
+#define Y4_GPIO_NUM    14
+#define Y3_GPIO_NUM    47
+#define Y2_GPIO_NUM    13
+#define VSYNC_GPIO_NUM 21
+#define HREF_GPIO_NUM  38
+#define PCLK_GPIO_NUM  11
+
+#elif defined(CAMERA_MODEL_ESP32S2_CAM_BOARD)
+// The 18 pin header on the board has Y5 and Y3 swapped
+#define USE_BOARD_HEADER 0
+#define PWDN_GPIO_NUM    1
+#define RESET_GPIO_NUM   2
+#define XCLK_GPIO_NUM    42
+#define SIOD_GPIO_NUM    41
+#define SIOC_GPIO_NUM    18
+
+#define Y9_GPIO_NUM 16
+#define Y8_GPIO_NUM 39
+#define Y7_GPIO_NUM 40
+#define Y6_GPIO_NUM 15
+#if USE_BOARD_HEADER
+#define Y5_GPIO_NUM 12
+#else
+#define Y5_GPIO_NUM 13
+#endif
+#define Y4_GPIO_NUM 5
+#if USE_BOARD_HEADER
+#define Y3_GPIO_NUM 13
+#else
+#define Y3_GPIO_NUM 12
+#endif
+#define Y2_GPIO_NUM    14
+#define VSYNC_GPIO_NUM 38
+#define HREF_GPIO_NUM  4
+#define PCLK_GPIO_NUM  3
+
+#elif defined(CAMERA_MODEL_ESP32S3_EYE)
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM -1
+#define XCLK_GPIO_NUM  15
+#define SIOD_GPIO_NUM  4
+#define SIOC_GPIO_NUM  5
+
+#define Y2_GPIO_NUM 11
+#define Y3_GPIO_NUM 9
+#define Y4_GPIO_NUM 8
+#define Y5_GPIO_NUM 10
+#define Y6_GPIO_NUM 12
+#define Y7_GPIO_NUM 18
+#define Y8_GPIO_NUM 17
+#define Y9_GPIO_NUM 16
+
+#define VSYNC_GPIO_NUM 6
+#define HREF_GPIO_NUM  7
+#define PCLK_GPIO_NUM  13
+
+#elif defined(CAMERA_MODEL_DFRobot_FireBeetle2_ESP32S3) || defined(CAMERA_MODEL_DFRobot_Romeo_ESP32S3)
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM -1
+#define XCLK_GPIO_NUM  45
+#define SIOD_GPIO_NUM  1
+#define SIOC_GPIO_NUM  2
+
+#define Y9_GPIO_NUM    48
+#define Y8_GPIO_NUM    46
+#define Y7_GPIO_NUM    8
+#define Y6_GPIO_NUM    7
+#define Y5_GPIO_NUM    4
+#define Y4_GPIO_NUM    41
+#define Y3_GPIO_NUM    40
+#define Y2_GPIO_NUM    39
+#define VSYNC_GPIO_NUM 6
+#define HREF_GPIO_NUM  42
+#define PCLK_GPIO_NUM  5
 
 #else
 #error "Camera model not selected"
diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/ci.json b/libraries/ESP32/examples/Camera/CameraWebServer/ci.json
new file mode 100644
index 00000000000..35c3056dda8
--- /dev/null
+++ b/libraries/ESP32/examples/Camera/CameraWebServer/ci.json
@@ -0,0 +1,20 @@
+{
+  "fqbn": {
+    "esp32": [
+      "espressif:esp32:esp32:PSRAM=enabled,PartitionScheme=custom,FlashMode=dio",
+      "espressif:esp32:esp32:PSRAM=disabled,PartitionScheme=custom,FlashMode=dio"
+    ],
+    "esp32s2": [
+      "espressif:esp32:esp32s2:PSRAM=enabled,PartitionScheme=custom,FlashMode=dio",
+      "espressif:esp32:esp32s2:PSRAM=disabled,PartitionScheme=custom,FlashMode=dio"
+    ],
+    "esp32s3": [
+      "espressif:esp32:esp32s3:PSRAM=opi,USBMode=default,PartitionScheme=custom,FlashMode=qio",
+      "espressif:esp32:esp32s3:PSRAM=enabled,USBMode=default,PartitionScheme=custom,FlashMode=qio",
+      "espressif:esp32:esp32s3:PSRAM=disabled,USBMode=default,PartitionScheme=custom,FlashMode=qio"
+    ]
+  },
+  "requires": [
+    "CONFIG_CAMERA_TASK_STACK_SIZE=[0-9]+"
+  ]
+}
diff --git a/libraries/ESP32/examples/Camera/CameraWebServer/partitions.csv b/libraries/ESP32/examples/Camera/CameraWebServer/partitions.csv
new file mode 100644
index 00000000000..b9f18c465a7
--- /dev/null
+++ b/libraries/ESP32/examples/Camera/CameraWebServer/partitions.csv
@@ -0,0 +1,6 @@
+# Name,   Type,  SubType, Offset,   Size,    Flags
+nvs,      data,  nvs,     0x9000,   0x5000,
+otadata,  data,  ota,     0xe000,   0x2000,
+app0,     app,   ota_0,   0x10000,  0x3c0000,
+fr,       data,        ,  0x3d0000, 0x20000,
+coredump, data,  coredump,0x3f0000, 0x10000,
diff --git a/libraries/ESP32/examples/ChipID/GetChipID/GetChipID.ino b/libraries/ESP32/examples/ChipID/GetChipID/GetChipID.ino
index d6288c89fad..89a195b972f 100644
--- a/libraries/ESP32/examples/ChipID/GetChipID/GetChipID.ino
+++ b/libraries/ESP32/examples/ChipID/GetChipID/GetChipID.ino
@@ -1,30 +1,30 @@
 /* The true ESP32 chip ID is essentially its MAC address.
-This sketch provides an alternate chip ID that matches 
-the output of the ESP.getChipId() function on ESP8266 
-(i.e. a 32-bit integer matching the last 3 bytes of 
-the MAC address. This is less unique than the 
-MAC address chip ID, but is helpful when you need 
-an identifier that can be no more than a 32-bit integer 
+This sketch provides an alternate chip ID that matches
+the output of the ESP.getChipId() function on ESP8266
+(i.e. a 32-bit integer matching the last 3 bytes of
+the MAC address. This is less unique than the
+MAC address chip ID, but is helpful when you need
+an identifier that can be no more than a 32-bit integer
 (like for switch...case).
 
 created 2020-06-07 by cweinhofer
 with help from Cicicok */
-	
+
 uint32_t chipId = 0;
 
 void setup() {
-	Serial.begin(115200);
+  Serial.begin(115200);
 }
 
 void loop() {
-	for(int i=0; i<17; i=i+8) {
-	  chipId |= ((ESP.getEfuseMac() >> (40 - i)) & 0xff) << i;
-	}
+  for (int i = 0; i < 17; i = i + 8) {
+    chipId |= ((ESP.getEfuseMac() >> (40 - i)) & 0xff) << i;
+  }
 
-	Serial.printf("ESP32 Chip model = %s Rev %d\n", ESP.getChipModel(), ESP.getChipRevision());
-	Serial.printf("This chip has %d cores\n", ESP.getChipCores());
-  Serial.print("Chip ID: "); Serial.println(chipId);
-  
-	delay(3000);
+  Serial.printf("ESP32 Chip model = %s Rev %d\n", ESP.getChipModel(), ESP.getChipRevision());
+  Serial.printf("This chip has %d cores\n", ESP.getChipCores());
+  Serial.print("Chip ID: ");
+  Serial.println(chipId);
 
+  delay(3000);
 }
diff --git a/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ExternalWakeUp.ino b/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ExternalWakeUp.ino
index 8a13b77196d..aed57c49047 100644
--- a/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ExternalWakeUp.ino
+++ b/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ExternalWakeUp.ino
@@ -1,53 +1,54 @@
 /*
-Deep Sleep with External Wake Up
-=====================================
-This code displays how to use deep sleep with
-an external trigger as a wake up source and how
-to store data in RTC memory to use it over reboots
-
-This code is under Public Domain License.
-
-Hardware Connections
-======================
-Push Button to GPIO 33 pulled down with a 10K Ohm
-resistor
-
-NOTE:
-======
-Only RTC IO can be used as a source for external wake
-source. They are pins: 0,2,4,12-15,25-27,32-39.
-
-Author:
-Pranav Cherukupalli <cherukupallip@gmail.com>
+  Deep Sleep with External Wake Up
+  =====================================
+  This code displays how to use deep sleep with
+  an external trigger as a wake up source and how
+  to store data in RTC memory to use it over reboots
+
+  This code is under Public Domain License.
+
+  Hardware Connections
+  ======================
+  Push Button to GPIO 33 pulled down with a 10K Ohm
+  resistor
+
+  NOTE:
+  ======
+  Only RTC IO can be used as a source for external wake
+  source. They are pins: 0,2,4,12-15,25-27,32-39.
+
+  Author:
+  Pranav Cherukupalli <cherukupallip@gmail.com>
 */
+#include "driver/rtc_io.h"
 
-#define BUTTON_PIN_BITMASK 0x200000000 // 2^33 in hex
-
+#define BUTTON_PIN_BITMASK(GPIO) (1ULL << GPIO)  // 2 ^ GPIO_NUMBER in hex
+#define USE_EXT0_WAKEUP          1               // 1 = EXT0 wakeup, 0 = EXT1 wakeup
+#define WAKEUP_GPIO              GPIO_NUM_33     // Only RTC IO are allowed - ESP32 Pin example
 RTC_DATA_ATTR int bootCount = 0;
 
 /*
-Method to print the reason by which ESP32
-has been awaken from sleep
+  Method to print the reason by which ESP32
+  has been awaken from sleep
 */
-void print_wakeup_reason(){
+void print_wakeup_reason() {
   esp_sleep_wakeup_cause_t wakeup_reason;
 
   wakeup_reason = esp_sleep_get_wakeup_cause();
 
-  switch(wakeup_reason)
-  {
-    case ESP_SLEEP_WAKEUP_EXT0 : Serial.println("Wakeup caused by external signal using RTC_IO"); break;
-    case ESP_SLEEP_WAKEUP_EXT1 : Serial.println("Wakeup caused by external signal using RTC_CNTL"); break;
-    case ESP_SLEEP_WAKEUP_TIMER : Serial.println("Wakeup caused by timer"); break;
-    case ESP_SLEEP_WAKEUP_TOUCHPAD : Serial.println("Wakeup caused by touchpad"); break;
-    case ESP_SLEEP_WAKEUP_ULP : Serial.println("Wakeup caused by ULP program"); break;
-    default : Serial.printf("Wakeup was not caused by deep sleep: %d\n",wakeup_reason); break;
+  switch (wakeup_reason) {
+    case ESP_SLEEP_WAKEUP_EXT0:     Serial.println("Wakeup caused by external signal using RTC_IO"); break;
+    case ESP_SLEEP_WAKEUP_EXT1:     Serial.println("Wakeup caused by external signal using RTC_CNTL"); break;
+    case ESP_SLEEP_WAKEUP_TIMER:    Serial.println("Wakeup caused by timer"); break;
+    case ESP_SLEEP_WAKEUP_TOUCHPAD: Serial.println("Wakeup caused by touchpad"); break;
+    case ESP_SLEEP_WAKEUP_ULP:      Serial.println("Wakeup caused by ULP program"); break;
+    default:                        Serial.printf("Wakeup was not caused by deep sleep: %d\n", wakeup_reason); break;
   }
 }
 
-void setup(){
+void setup() {
   Serial.begin(115200);
-  delay(1000); //Take some time to open up the Serial Monitor
+  delay(1000);  //Take some time to open up the Serial Monitor
 
   //Increment boot number and print it every reboot
   ++bootCount;
@@ -57,26 +58,41 @@ void setup(){
   print_wakeup_reason();
 
   /*
-  First we configure the wake up source
-  We set our ESP32 to wake up for an external trigger.
-  There are two types for ESP32, ext0 and ext1 .
-  ext0 uses RTC_IO to wakeup thus requires RTC peripherals
-  to be on while ext1 uses RTC Controller so doesnt need
-  peripherals to be powered on.
-  Note that using internal pullups/pulldowns also requires
-  RTC peripherals to be turned on.
+    First we configure the wake up source
+    We set our ESP32 to wake up for an external trigger.
+    There are two types for ESP32, ext0 and ext1 .
+    ext0 uses RTC_IO to wakeup thus requires RTC peripherals
+    to be on while ext1 uses RTC Controller so does not need
+    peripherals to be powered on.
+    Note that using internal pullups/pulldowns also requires
+    RTC peripherals to be turned on.
   */
-  esp_sleep_enable_ext0_wakeup(GPIO_NUM_33,1); //1 = High, 0 = Low
-
+#if USE_EXT0_WAKEUP
+  esp_sleep_enable_ext0_wakeup(WAKEUP_GPIO, 1);  //1 = High, 0 = Low
+  // Configure pullup/downs via RTCIO to tie wakeup pins to inactive level during deepsleep.
+  // EXT0 resides in the same power domain (RTC_PERIPH) as the RTC IO pullup/downs.
+  // No need to keep that power domain explicitly, unlike EXT1.
+  rtc_gpio_pullup_dis(WAKEUP_GPIO);
+  rtc_gpio_pulldown_en(WAKEUP_GPIO);
+
+#else  // EXT1 WAKEUP
   //If you were to use ext1, you would use it like
-  //esp_sleep_enable_ext1_wakeup(BUTTON_PIN_BITMASK,ESP_EXT1_WAKEUP_ANY_HIGH);
-
+  esp_sleep_enable_ext1_wakeup_io(BUTTON_PIN_BITMASK(WAKEUP_GPIO), ESP_EXT1_WAKEUP_ANY_HIGH);
+  /*
+    If there are no external pull-up/downs, tie wakeup pins to inactive level with internal pull-up/downs via RTC IO
+         during deepsleep. However, RTC IO relies on the RTC_PERIPH power domain. Keeping this power domain on will
+         increase some power consumption. However, if we turn off the RTC_PERIPH domain or if certain chips lack the RTC_PERIPH
+         domain, we will use the HOLD feature to maintain the pull-up and pull-down on the pins during sleep.
+  */
+  rtc_gpio_pulldown_en(WAKEUP_GPIO);  // GPIO33 is tie to GND in order to wake up in HIGH
+  rtc_gpio_pullup_dis(WAKEUP_GPIO);   // Disable PULL_UP in order to allow it to wakeup on HIGH
+#endif
   //Go to sleep now
   Serial.println("Going to sleep now");
   esp_deep_sleep_start();
   Serial.println("This will never be printed");
 }
 
-void loop(){
+void loop() {
   //This is not going to be called
 }
diff --git a/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ci.json b/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ci.json
new file mode 100644
index 00000000000..cd679adefad
--- /dev/null
+++ b/libraries/ESP32/examples/DeepSleep/ExternalWakeUp/ci.json
@@ -0,0 +1,8 @@
+{
+  "targets": {
+    "esp32c3": false,
+    "esp32c6": false,
+    "esp32h2": false,
+    "esp32p4": false
+  }
+}
diff --git a/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/SmoothBlink_ULP_Code.ino b/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/SmoothBlink_ULP_Code.ino
new file mode 100644
index 00000000000..789d9fa3dc9
--- /dev/null
+++ b/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/SmoothBlink_ULP_Code.ino
@@ -0,0 +1,161 @@
+/*
+  This example smothly blinks GPIO_2 using different frequencies changed after Deep Sleep Time
+  The PWM and control of blink frequency is done by ULP exclusively
+  This is an example about how to program the ULP using Arduino
+  It also demonstrates use of RTM MEMORY to persist data and states
+*/
+
+#include <Arduino.h>
+#include "esp32/ulp.h"
+#include "driver/rtc_io.h"
+#include "soc/rtc_io_reg.h"
+
+// RTC Memory used for ULP internal variable and Sketch interfacing
+#define RTC_dutyMeter 0
+#define RTC_dir       4
+#define RTC_fadeDelay 12
+// *fadeCycleDelay is used to pass values to ULP and change its behavior
+uint32_t *fadeCycleDelay = &RTC_SLOW_MEM[RTC_fadeDelay];
+#define ULP_START_OFFSET 32
+
+// For ESP32 Arduino, it is usually at offeset 512, defined in sdkconfig
+RTC_DATA_ATTR uint32_t ULP_Started = 0;  // 0 or 1
+
+//Time-to-Sleep
+#define uS_TO_S_FACTOR 1000000ULL /* Conversion factor for micro seconds to seconds */
+#define TIME_TO_SLEEP  5          /* Time ESP32 will go to sleep (in microseconds); multiplied by above conversion to achieve seconds*/
+
+void ulp_setup() {
+  if (ULP_Started) {
+    return;
+  }
+  *fadeCycleDelay = 5;  // 5..200 works fine for a full Fade In + Out cycle
+  ULP_Started = 1;
+
+  // GPIO2 initialization (set to output and initial value is 0)
+  const gpio_num_t MeterPWMPin = GPIO_NUM_2;
+  rtc_gpio_init(MeterPWMPin);
+  rtc_gpio_set_direction(MeterPWMPin, RTC_GPIO_MODE_OUTPUT_ONLY);
+  rtc_gpio_set_level(MeterPWMPin, 0);
+
+  // if LED is connected to GPIO2 (specify by +RTC_GPIO_OUT_DATA_S : ESP32 is 14, S2/S3 is 10)
+  const uint32_t MeterPWMBit = rtc_io_number_get(MeterPWMPin) + RTC_GPIO_OUT_DATA_S;
+
+  enum labels {
+    INIFINITE_LOOP,
+    RUN_PWM,
+    NEXT_PWM_CYCLE,
+    PWM_ON,
+    PWM_OFF,
+    END_PWM_CYCLE,
+    POSITIVE_DIR,
+    DEC_DUTY,
+    INC_DUTY,
+  };
+
+  // Define ULP program
+  const ulp_insn_t ulp_prog[] = {
+    // Initial Value setup
+    I_MOVI(R0, 0),                // R0 = 0
+    I_ST(R0, R0, RTC_dutyMeter),  // RTC_SLOW_MEM[RTC_dutyMeter] = 0
+    I_MOVI(R1, 1),                // R1 = 1
+    I_ST(R1, R0, RTC_dir),        // RTC_SLOW_MEM[RTC_dir] = 1
+
+    M_LABEL(INIFINITE_LOOP),  // while(1) {
+
+    // run certain PWM Duty for about (RTC_fadeDelay x 100) microseconds
+    I_MOVI(R3, 0),                //   R3 = 0
+    I_LD(R3, R3, RTC_fadeDelay),  //   R3 = RTC_SLOW_MEM[RTC_fadeDelay]
+    M_LABEL(RUN_PWM),             //   do {  // repeat RTC_fadeDelay times:
+
+    // execute about 10KHz PWM on GPIO2 using as duty cycle = RTC_SLOW_MEM[RTC_dutyMeter]
+    I_MOVI(R0, 0),                                                 //     R0 = 0
+    I_LD(R0, R0, RTC_dutyMeter),                                   //     R0 = RTC_SLOW_MEM[RTC_dutyMeter]
+    M_BL(NEXT_PWM_CYCLE, 1),                                       //     if (R0 > 0) turn on LED
+    I_WR_REG(RTC_GPIO_OUT_W1TS_REG, MeterPWMBit, MeterPWMBit, 1),  // W1TS set bit to clear GPIO - GPIO2 on
+    M_LABEL(PWM_ON),                                               //     while (R0 > 0) // repeat RTC_dutyMeter times:
+    M_BL(NEXT_PWM_CYCLE, 1),                                       //     {
+    //I_DELAY(8),                 //       // 8 is about 1 microsecond based on 8MHz
+    I_SUBI(R0, R0, 1),                                             //       R0 = R0 - 1
+    M_BX(PWM_ON),                                                  //     }
+    M_LABEL(NEXT_PWM_CYCLE),                                       //     // toggle GPIO_2
+    I_MOVI(R0, 0),                                                 //     R0 = 0
+    I_LD(R0, R0, RTC_dutyMeter),                                   //     R0 = RTC_SLOW_MEM[RTC_dutyMeter]
+    I_MOVI(R1, 100),                                               //     R1 = 100
+    I_SUBR(R0, R1, R0),                                            //     R0 = 100 - dutyMeter
+    M_BL(END_PWM_CYCLE, 1),                                        //     if (R0 > 0) turn off LED
+    I_WR_REG(RTC_GPIO_OUT_W1TC_REG, MeterPWMBit, MeterPWMBit, 1),  // W1TC set bit to clear GPIO - GPIO2 off
+    M_LABEL(PWM_OFF),                                              //     while (R0 > 0)  // repeat (100 - RTC_dutyMeter) times:
+    M_BL(END_PWM_CYCLE, 1),                                        //     {
+    //I_DELAY(8),                 //       // 8 is about 1us: ULP fetch+execution time
+    I_SUBI(R0, R0, 1),       //       R0 = R0 - 1
+    M_BX(PWM_OFF),           //     }
+    M_LABEL(END_PWM_CYCLE),  //
+
+    I_SUBI(R3, R3, 1),  //     R3 = R3 - 1  // RTC_fadeDelay
+    I_MOVR(R0, R3),     //     R0 = R3      // only R0 can be used to compare and branch
+    M_BGE(RUN_PWM, 1),  //   } while (R3 > 0)  // ESP32 repeatinf RTC_fadeDelay times
+
+    // increase/decrease DutyMeter to apply Fade In/Out loop
+    I_MOVI(R1, 0),                //   R1 = 0
+    I_LD(R1, R1, RTC_dutyMeter),  //   R1 = RTC_SLOW_MEM[RTC_dutyMeter]
+    I_MOVI(R0, 0),                //   R0 = 0
+    I_LD(R0, R0, RTC_dir),        //   R0 = RTC_SLOW_MEM[RTC_dir]
+
+    M_BGE(POSITIVE_DIR, 1),  //   if(dir == 0) { // decrease duty by 2
+    // Dir is 0, means decrease Duty by 2
+    I_MOVR(R0, R1),               //     R0 = Duty
+    M_BGE(DEC_DUTY, 1),           //     if (duty == 0) { // change direction and increase duty
+    I_MOVI(R3, 0),                //       R3 = 0
+    I_MOVI(R2, 1),                //       R2 = 1
+    I_ST(R2, R3, RTC_dir),        //       RTC_SLOW_MEM[RTC_dir] = 1   // increasing direction
+    M_BX(INC_DUTY),               //       goto "increase Duty"
+    M_LABEL(DEC_DUTY),            //     } "decrease Duty":
+    I_SUBI(R0, R0, 2),            //     Duty -= 2
+    I_MOVI(R2, 0),                //     R2 = 0
+    I_ST(R0, R2, RTC_dutyMeter),  //     RTC_SLOW_MEM[RTC_dutyMeter] += 2
+    M_BX(INIFINITE_LOOP),         // }
+
+    M_LABEL(POSITIVE_DIR),  //   else { // dir == 1 // increase duty by 2
+    // Dir is 1, means increase Duty by 2
+    I_MOVR(R0, R1),               //     R0 = Duty
+    M_BL(INC_DUTY, 100),          //     if (duty == 100) { // change direction and decrease duty
+    I_MOVI(R2, 0),                //       R2 = 0
+    I_ST(R2, R2, RTC_dir),        //       RTC_SLOW_MEM[RTC_dir] = 0  // decreasing direction
+    M_BX(DEC_DUTY),               //       goto "decrease Duty"
+    M_LABEL(INC_DUTY),            //     } "increase Duty":
+    I_ADDI(R0, R0, 2),            //     Duty += 2
+    I_MOVI(R2, 0),                //     R2 = 0
+    I_ST(R0, R2, RTC_dutyMeter),  //     RTC_SLOW_MEM[RTC_dutyMeter] -= 2
+                                  //   } // if (dir == 0)
+    M_BX(INIFINITE_LOOP),         // } // while(1)
+  };
+  // Run ULP program
+  size_t size = sizeof(ulp_prog) / sizeof(ulp_insn_t);
+  ulp_process_macros_and_load(ULP_START_OFFSET, ulp_prog, &size);
+  esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+  ulp_run(ULP_START_OFFSET);
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  ulp_setup();  // it really only runs on the first ESP32 boot
+  Serial.printf("\nStarted smooth blink with delay %ld\n", *fadeCycleDelay);
+
+  // *fadeCycleDelay resides in RTC_SLOW_MEM and persists along deep sleep waking up
+  // it is used as a delay time parameter for smooth blinking, in the ULP processing code
+  if (*fadeCycleDelay < 195) {
+    *fadeCycleDelay += 10;
+  } else {
+    *fadeCycleDelay = 5;  // 5..200 works fine for a full Fade In + Out cycle
+  }
+  Serial.println("Entering in Deep Sleep");
+  esp_sleep_enable_timer_wakeup(TIME_TO_SLEEP * uS_TO_S_FACTOR /*/ 4*/);  // time set with variable above
+  esp_deep_sleep_start();
+  // From this point on, no code is executed in DEEP SLEEP mode
+}
+
+void loop() {
+  // It never reaches this code because it enters in Deep Sleep mode at the end of setup()
+}
diff --git a/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/ci.json b/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/ci.json
new file mode 100644
index 00000000000..6afa60f44c4
--- /dev/null
+++ b/libraries/ESP32/examples/DeepSleep/SmoothBlink_ULP_Code/ci.json
@@ -0,0 +1,10 @@
+{
+  "targets": {
+    "esp32c3": false,
+    "esp32c6": false,
+    "esp32h2": false,
+    "esp32p4": false,
+    "esp32s2": false,
+    "esp32s3": false
+  }
+}
diff --git a/libraries/ESP32/examples/DeepSleep/TimerWakeUp/TimerWakeUp.ino b/libraries/ESP32/examples/DeepSleep/TimerWakeUp/TimerWakeUp.ino
index ec43cf72ea7..a6e88557b46 100644
--- a/libraries/ESP32/examples/DeepSleep/TimerWakeUp/TimerWakeUp.ino
+++ b/libraries/ESP32/examples/DeepSleep/TimerWakeUp/TimerWakeUp.ino
@@ -19,8 +19,8 @@ Author:
 Pranav Cherukupalli <cherukupallip@gmail.com>
 */
 
-#define uS_TO_S_FACTOR 1000000ULL  /* Conversion factor for micro seconds to seconds */
-#define TIME_TO_SLEEP  5        /* Time ESP32 will go to sleep (in seconds) */
+#define uS_TO_S_FACTOR 1000000ULL /* Conversion factor for micro seconds to seconds */
+#define TIME_TO_SLEEP  5          /* Time ESP32 will go to sleep (in seconds) */
 
 RTC_DATA_ATTR int bootCount = 0;
 
@@ -28,25 +28,24 @@ RTC_DATA_ATTR int bootCount = 0;
 Method to print the reason by which ESP32
 has been awaken from sleep
 */
-void print_wakeup_reason(){
+void print_wakeup_reason() {
   esp_sleep_wakeup_cause_t wakeup_reason;
 
   wakeup_reason = esp_sleep_get_wakeup_cause();
 
-  switch(wakeup_reason)
-  {
-    case ESP_SLEEP_WAKEUP_EXT0 : Serial.println("Wakeup caused by external signal using RTC_IO"); break;
-    case ESP_SLEEP_WAKEUP_EXT1 : Serial.println("Wakeup caused by external signal using RTC_CNTL"); break;
-    case ESP_SLEEP_WAKEUP_TIMER : Serial.println("Wakeup caused by timer"); break;
-    case ESP_SLEEP_WAKEUP_TOUCHPAD : Serial.println("Wakeup caused by touchpad"); break;
-    case ESP_SLEEP_WAKEUP_ULP : Serial.println("Wakeup caused by ULP program"); break;
-    default : Serial.printf("Wakeup was not caused by deep sleep: %d\n",wakeup_reason); break;
+  switch (wakeup_reason) {
+    case ESP_SLEEP_WAKEUP_EXT0:     Serial.println("Wakeup caused by external signal using RTC_IO"); break;
+    case ESP_SLEEP_WAKEUP_EXT1:     Serial.println("Wakeup caused by external signal using RTC_CNTL"); break;
+    case ESP_SLEEP_WAKEUP_TIMER:    Serial.println("Wakeup caused by timer"); break;
+    case ESP_SLEEP_WAKEUP_TOUCHPAD: Serial.println("Wakeup caused by touchpad"); break;
+    case ESP_SLEEP_WAKEUP_ULP:      Serial.println("Wakeup caused by ULP program"); break;
+    default:                        Serial.printf("Wakeup was not caused by deep sleep: %d\n", wakeup_reason); break;
   }
 }
 
-void setup(){
+void setup() {
   Serial.begin(115200);
-  delay(1000); //Take some time to open up the Serial Monitor
+  delay(1000);  //Take some time to open up the Serial Monitor
 
   //Increment boot number and print it every reboot
   ++bootCount;
@@ -60,8 +59,7 @@ void setup(){
   We set our ESP32 to wake up every 5 seconds
   */
   esp_sleep_enable_timer_wakeup(TIME_TO_SLEEP * uS_TO_S_FACTOR);
-  Serial.println("Setup ESP32 to sleep for every " + String(TIME_TO_SLEEP) +
-  " Seconds");
+  Serial.println("Setup ESP32 to sleep for every " + String(TIME_TO_SLEEP) + " Seconds");
 
   /*
   Next we decide what all peripherals to shut down/keep on
@@ -84,11 +82,11 @@ void setup(){
   reset occurs.
   */
   Serial.println("Going to sleep now");
-  Serial.flush(); 
+  Serial.flush();
   esp_deep_sleep_start();
   Serial.println("This will never be printed");
 }
 
-void loop(){
+void loop() {
   //This is not going to be called
 }
diff --git a/libraries/ESP32/examples/DeepSleep/TimerWakeUp/ci.json b/libraries/ESP32/examples/DeepSleep/TimerWakeUp/ci.json
new file mode 100644
index 00000000000..d8b3664bc65
--- /dev/null
+++ b/libraries/ESP32/examples/DeepSleep/TimerWakeUp/ci.json
@@ -0,0 +1,5 @@
+{
+  "targets": {
+    "esp32h2": false
+  }
+}
diff --git a/libraries/ESP32/examples/DeepSleep/TouchWakeUp/TouchWakeUp.ino b/libraries/ESP32/examples/DeepSleep/TouchWakeUp/TouchWakeUp.ino
index 76f48b757a4..9d2b248ba44 100644
--- a/libraries/ESP32/examples/DeepSleep/TouchWakeUp/TouchWakeUp.ino
+++ b/libraries/ESP32/examples/DeepSleep/TouchWakeUp/TouchWakeUp.ino
@@ -5,13 +5,22 @@ This code displays how to use deep sleep with
 a touch as a wake up source and how to store data in
 RTC memory to use it over reboots
 
+ESP32 can have multiple touch pads enabled as wakeup source
+ESP32-S2 and ESP32-S3 supports only 1 touch pad as wakeup source enabled
+
 This code is under Public Domain License.
 
 Author:
 Pranav Cherukupalli <cherukupallip@gmail.com>
 */
 
-#define Threshold 40 /* Greater the value, more the sensitivity */
+#if CONFIG_IDF_TARGET_ESP32
+#define THRESHOLD 40 /* Greater the value, more the sensitivity */
+#elif (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3)
+#define THRESHOLD 5000 /* Lower the value, more the sensitivity */
+#else                  // ESP32-P4 + default for other chips (to be adjusted) */
+#define THRESHOLD 500  /* Lower the value, more the sensitivity */
+#endif
 
 RTC_DATA_ATTR int bootCount = 0;
 touch_pad_t touchPin;
@@ -19,19 +28,18 @@ touch_pad_t touchPin;
 Method to print the reason by which ESP32
 has been awaken from sleep
 */
-void print_wakeup_reason(){
+void print_wakeup_reason() {
   esp_sleep_wakeup_cause_t wakeup_reason;
 
   wakeup_reason = esp_sleep_get_wakeup_cause();
 
-  switch(wakeup_reason)
-  {
-    case ESP_SLEEP_WAKEUP_EXT0 : Serial.println("Wakeup caused by external signal using RTC_IO"); break;
-    case ESP_SLEEP_WAKEUP_EXT1 : Serial.println("Wakeup caused by external signal using RTC_CNTL"); break;
-    case ESP_SLEEP_WAKEUP_TIMER : Serial.println("Wakeup caused by timer"); break;
-    case ESP_SLEEP_WAKEUP_TOUCHPAD : Serial.println("Wakeup caused by touchpad"); break;
-    case ESP_SLEEP_WAKEUP_ULP : Serial.println("Wakeup caused by ULP program"); break;
-    default : Serial.printf("Wakeup was not caused by deep sleep: %d\n",wakeup_reason); break;
+  switch (wakeup_reason) {
+    case ESP_SLEEP_WAKEUP_EXT0:     Serial.println("Wakeup caused by external signal using RTC_IO"); break;
+    case ESP_SLEEP_WAKEUP_EXT1:     Serial.println("Wakeup caused by external signal using RTC_CNTL"); break;
+    case ESP_SLEEP_WAKEUP_TIMER:    Serial.println("Wakeup caused by timer"); break;
+    case ESP_SLEEP_WAKEUP_TOUCHPAD: Serial.println("Wakeup caused by touchpad"); break;
+    case ESP_SLEEP_WAKEUP_ULP:      Serial.println("Wakeup caused by ULP program"); break;
+    default:                        Serial.printf("Wakeup was not caused by deep sleep: %d\n", wakeup_reason); break;
   }
 }
 
@@ -39,32 +47,35 @@ void print_wakeup_reason(){
 Method to print the touchpad by which ESP32
 has been awaken from sleep
 */
-void print_wakeup_touchpad(){
+void print_wakeup_touchpad() {
   touchPin = esp_sleep_get_touchpad_wakeup_status();
 
-  switch(touchPin)
-  {
-    case 0  : Serial.println("Touch detected on GPIO 4"); break;
-    case 1  : Serial.println("Touch detected on GPIO 0"); break;
-    case 2  : Serial.println("Touch detected on GPIO 2"); break;
-    case 3  : Serial.println("Touch detected on GPIO 15"); break;
-    case 4  : Serial.println("Touch detected on GPIO 13"); break;
-    case 5  : Serial.println("Touch detected on GPIO 12"); break;
-    case 6  : Serial.println("Touch detected on GPIO 14"); break;
-    case 7  : Serial.println("Touch detected on GPIO 27"); break;
-    case 8  : Serial.println("Touch detected on GPIO 33"); break;
-    case 9  : Serial.println("Touch detected on GPIO 32"); break;
-    default : Serial.println("Wakeup not by touchpad"); break;
+#if CONFIG_IDF_TARGET_ESP32
+  switch (touchPin) {
+    case 0:  Serial.println("Touch detected on GPIO 4"); break;
+    case 1:  Serial.println("Touch detected on GPIO 0"); break;
+    case 2:  Serial.println("Touch detected on GPIO 2"); break;
+    case 3:  Serial.println("Touch detected on GPIO 15"); break;
+    case 4:  Serial.println("Touch detected on GPIO 13"); break;
+    case 5:  Serial.println("Touch detected on GPIO 12"); break;
+    case 6:  Serial.println("Touch detected on GPIO 14"); break;
+    case 7:  Serial.println("Touch detected on GPIO 27"); break;
+    case 8:  Serial.println("Touch detected on GPIO 33"); break;
+    case 9:  Serial.println("Touch detected on GPIO 32"); break;
+    default: Serial.println("Wakeup not by touchpad"); break;
   }
+#else
+  if (touchPin < TOUCH_PAD_MAX) {
+    Serial.printf("Touch detected on GPIO %d\n", touchPin);
+  } else {
+    Serial.println("Wakeup not by touchpad");
+  }
+#endif
 }
 
-void callback(){
-  //placeholder callback function
-}
-
-void setup(){
+void setup() {
   Serial.begin(115200);
-  delay(1000); //Take some time to open up the Serial Monitor
+  delay(1000);  //Take some time to open up the Serial Monitor
 
   //Increment boot number and print it every reboot
   ++bootCount;
@@ -74,11 +85,16 @@ void setup(){
   print_wakeup_reason();
   print_wakeup_touchpad();
 
-  //Setup interrupt on Touch Pad 3 (GPIO15)
-  touchAttachInterrupt(T3, callback, Threshold);
+#if CONFIG_IDF_TARGET_ESP32
+  //Setup sleep wakeup on Touch Pad 3 + 7 (GPIO15 + GPIO 27)
+  touchSleepWakeUpEnable(T3, THRESHOLD);
+  touchSleepWakeUpEnable(T7, THRESHOLD);
+
+#else  //ESP32-S2 + ESP32-S3 + ESP32-P4
+  //Setup sleep wakeup on Touch Pad 3 (GPIO3)
+  touchSleepWakeUpEnable(T3, THRESHOLD);
 
-  //Configure Touchpad as wakeup source
-  esp_sleep_enable_touchpad_wakeup();
+#endif
 
   //Go to sleep now
   Serial.println("Going to sleep now");
@@ -86,6 +102,6 @@ void setup(){
   Serial.println("This will never be printed");
 }
 
-void loop(){
+void loop() {
   //This will never be reached
 }
diff --git a/libraries/ESP32/examples/DeepSleep/TouchWakeUp/ci.json b/libraries/ESP32/examples/DeepSleep/TouchWakeUp/ci.json
new file mode 100644
index 00000000000..25c42144223
--- /dev/null
+++ b/libraries/ESP32/examples/DeepSleep/TouchWakeUp/ci.json
@@ -0,0 +1,7 @@
+{
+  "targets": {
+    "esp32c3": false,
+    "esp32c6": false,
+    "esp32h2": false
+  }
+}
diff --git a/libraries/ESP32/examples/ESPNow/Basic/Master/Master.ino b/libraries/ESP32/examples/ESPNow/Basic/Master/Master.ino
deleted file mode 100644
index 1cb9fb98845..00000000000
--- a/libraries/ESP32/examples/ESPNow/Basic/Master/Master.ino
+++ /dev/null
@@ -1,259 +0,0 @@
-/**
-   ESPNOW - Basic communication - Master
-   Date: 26th September 2017
-   Author: Arvind Ravulavaru <https://github.com/arvindr21>
-   Purpose: ESPNow Communication between a Master ESP32 and a Slave ESP32
-   Description: This sketch consists of the code for the Master module.
-   Resources: (A bit outdated)
-   a. https://espressif.com/sites/default/files/documentation/esp-now_user_guide_en.pdf
-   b. http://www.esploradores.com/practica-6-conexion-esp-now/
-
-   << This Device Master >>
-
-   Flow: Master
-   Step 1 : ESPNow Init on Master and set it in STA mode
-   Step 2 : Start scanning for Slave ESP32 (we have added a prefix of `slave` to the SSID of slave for an easy setup)
-   Step 3 : Once found, add Slave as peer
-   Step 4 : Register for send callback
-   Step 5 : Start Transmitting data from Master to Slave
-
-   Flow: Slave
-   Step 1 : ESPNow Init on Slave
-   Step 2 : Update the SSID of Slave with a prefix of `slave`
-   Step 3 : Set Slave in AP mode
-   Step 4 : Register for receive callback and wait for data
-   Step 5 : Once data arrives, print it in the serial monitor
-
-   Note: Master and Slave have been defined to easily understand the setup.
-         Based on the ESPNOW API, there is no concept of Master and Slave.
-         Any devices can act as master or salve.
-*/
-
-#include <esp_now.h>
-#include <WiFi.h>
-
-// Global copy of slave
-esp_now_peer_info_t slave;
-#define CHANNEL 3
-#define PRINTSCANRESULTS 0
-#define DELETEBEFOREPAIR 0
-
-// Init ESP Now with fallback
-void InitESPNow() {
-  WiFi.disconnect();
-  if (esp_now_init() == ESP_OK) {
-    Serial.println("ESPNow Init Success");
-  }
-  else {
-    Serial.println("ESPNow Init Failed");
-    // Retry InitESPNow, add a counte and then restart?
-    // InitESPNow();
-    // or Simply Restart
-    ESP.restart();
-  }
-}
-
-// Scan for slaves in AP mode
-void ScanForSlave() {
-  int8_t scanResults = WiFi.scanNetworks();
-  // reset on each scan
-  bool slaveFound = 0;
-  memset(&slave, 0, sizeof(slave));
-
-  Serial.println("");
-  if (scanResults == 0) {
-    Serial.println("No WiFi devices in AP Mode found");
-  } else {
-    Serial.print("Found "); Serial.print(scanResults); Serial.println(" devices ");
-    for (int i = 0; i < scanResults; ++i) {
-      // Print SSID and RSSI for each device found
-      String SSID = WiFi.SSID(i);
-      int32_t RSSI = WiFi.RSSI(i);
-      String BSSIDstr = WiFi.BSSIDstr(i);
-
-      if (PRINTSCANRESULTS) {
-        Serial.print(i + 1);
-        Serial.print(": ");
-        Serial.print(SSID);
-        Serial.print(" (");
-        Serial.print(RSSI);
-        Serial.print(")");
-        Serial.println("");
-      }
-      delay(10);
-      // Check if the current device starts with `Slave`
-      if (SSID.indexOf("Slave") == 0) {
-        // SSID of interest
-        Serial.println("Found a Slave.");
-        Serial.print(i + 1); Serial.print(": "); Serial.print(SSID); Serial.print(" ["); Serial.print(BSSIDstr); Serial.print("]"); Serial.print(" ("); Serial.print(RSSI); Serial.print(")"); Serial.println("");
-        // Get BSSID => Mac Address of the Slave
-        int mac[6];
-        if ( 6 == sscanf(BSSIDstr.c_str(), "%x:%x:%x:%x:%x:%x",  &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5] ) ) {
-          for (int ii = 0; ii < 6; ++ii ) {
-            slave.peer_addr[ii] = (uint8_t) mac[ii];
-          }
-        }
-
-        slave.channel = CHANNEL; // pick a channel
-        slave.encrypt = 0; // no encryption
-
-        slaveFound = 1;
-        // we are planning to have only one slave in this example;
-        // Hence, break after we find one, to be a bit efficient
-        break;
-      }
-    }
-  }
-
-  if (slaveFound) {
-    Serial.println("Slave Found, processing..");
-  } else {
-    Serial.println("Slave Not Found, trying again.");
-  }
-
-  // clean up ram
-  WiFi.scanDelete();
-}
-
-// Check if the slave is already paired with the master.
-// If not, pair the slave with master
-bool manageSlave() {
-  if (slave.channel == CHANNEL) {
-    if (DELETEBEFOREPAIR) {
-      deletePeer();
-    }
-
-    Serial.print("Slave Status: ");
-    // check if the peer exists
-    bool exists = esp_now_is_peer_exist(slave.peer_addr);
-    if ( exists) {
-      // Slave already paired.
-      Serial.println("Already Paired");
-      return true;
-    } else {
-      // Slave not paired, attempt pair
-      esp_err_t addStatus = esp_now_add_peer(&slave);
-      if (addStatus == ESP_OK) {
-        // Pair success
-        Serial.println("Pair success");
-        return true;
-      } else if (addStatus == ESP_ERR_ESPNOW_NOT_INIT) {
-        // How did we get so far!!
-        Serial.println("ESPNOW Not Init");
-        return false;
-      } else if (addStatus == ESP_ERR_ESPNOW_ARG) {
-        Serial.println("Invalid Argument");
-        return false;
-      } else if (addStatus == ESP_ERR_ESPNOW_FULL) {
-        Serial.println("Peer list full");
-        return false;
-      } else if (addStatus == ESP_ERR_ESPNOW_NO_MEM) {
-        Serial.println("Out of memory");
-        return false;
-      } else if (addStatus == ESP_ERR_ESPNOW_EXIST) {
-        Serial.println("Peer Exists");
-        return true;
-      } else {
-        Serial.println("Not sure what happened");
-        return false;
-      }
-    }
-  } else {
-    // No slave found to process
-    Serial.println("No Slave found to process");
-    return false;
-  }
-}
-
-void deletePeer() {
-  esp_err_t delStatus = esp_now_del_peer(slave.peer_addr);
-  Serial.print("Slave Delete Status: ");
-  if (delStatus == ESP_OK) {
-    // Delete success
-    Serial.println("Success");
-  } else if (delStatus == ESP_ERR_ESPNOW_NOT_INIT) {
-    // How did we get so far!!
-    Serial.println("ESPNOW Not Init");
-  } else if (delStatus == ESP_ERR_ESPNOW_ARG) {
-    Serial.println("Invalid Argument");
-  } else if (delStatus == ESP_ERR_ESPNOW_NOT_FOUND) {
-    Serial.println("Peer not found.");
-  } else {
-    Serial.println("Not sure what happened");
-  }
-}
-
-uint8_t data = 0;
-// send data
-void sendData() {
-  data++;
-  const uint8_t *peer_addr = slave.peer_addr;
-  Serial.print("Sending: "); Serial.println(data);
-  esp_err_t result = esp_now_send(peer_addr, &data, sizeof(data));
-  Serial.print("Send Status: ");
-  if (result == ESP_OK) {
-    Serial.println("Success");
-  } else if (result == ESP_ERR_ESPNOW_NOT_INIT) {
-    // How did we get so far!!
-    Serial.println("ESPNOW not Init.");
-  } else if (result == ESP_ERR_ESPNOW_ARG) {
-    Serial.println("Invalid Argument");
-  } else if (result == ESP_ERR_ESPNOW_INTERNAL) {
-    Serial.println("Internal Error");
-  } else if (result == ESP_ERR_ESPNOW_NO_MEM) {
-    Serial.println("ESP_ERR_ESPNOW_NO_MEM");
-  } else if (result == ESP_ERR_ESPNOW_NOT_FOUND) {
-    Serial.println("Peer not found.");
-  } else {
-    Serial.println("Not sure what happened");
-  }
-}
-
-// callback when data is sent from Master to Slave
-void OnDataSent(const uint8_t *mac_addr, esp_now_send_status_t status) {
-  char macStr[18];
-  snprintf(macStr, sizeof(macStr), "%02x:%02x:%02x:%02x:%02x:%02x",
-           mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
-  Serial.print("Last Packet Sent to: "); Serial.println(macStr);
-  Serial.print("Last Packet Send Status: "); Serial.println(status == ESP_NOW_SEND_SUCCESS ? "Delivery Success" : "Delivery Fail");
-}
-
-void setup() {
-  Serial.begin(115200);
-  //Set device in STA mode to begin with
-  WiFi.mode(WIFI_STA);
-  Serial.println("ESPNow/Basic/Master Example");
-  // This is the mac address of the Master in Station Mode
-  Serial.print("STA MAC: "); Serial.println(WiFi.macAddress());
-  // Init ESPNow with a fallback logic
-  InitESPNow();
-  // Once ESPNow is successfully Init, we will register for Send CB to
-  // get the status of Trasnmitted packet
-  esp_now_register_send_cb(OnDataSent);
-}
-
-void loop() {
-  // In the loop we scan for slave
-  ScanForSlave();
-  // If Slave is found, it would be populate in `slave` variable
-  // We will check if `slave` is defined and then we proceed further
-  if (slave.channel == CHANNEL) { // check if slave channel is defined
-    // `slave` is defined
-    // Add slave as peer if it has not been added already
-    bool isPaired = manageSlave();
-    if (isPaired) {
-      // pair success or already paired
-      // Send data to device
-      sendData();
-    } else {
-      // slave pair failed
-      Serial.println("Slave pair failed!");
-    }
-  }
-  else {
-    // No slave found to process
-  }
-
-  // wait for 3seconds to run the logic again
-  delay(3000);
-}
diff --git a/libraries/ESP32/examples/ESPNow/Basic/Slave/Slave.ino b/libraries/ESP32/examples/ESPNow/Basic/Slave/Slave.ino
deleted file mode 100644
index d9029e961e3..00000000000
--- a/libraries/ESP32/examples/ESPNow/Basic/Slave/Slave.ino
+++ /dev/null
@@ -1,91 +0,0 @@
-/**
-   ESPNOW - Basic communication - Slave
-   Date: 26th September 2017
-   Author: Arvind Ravulavaru <https://github.com/arvindr21>
-   Purpose: ESPNow Communication between a Master ESP32 and a Slave ESP32
-   Description: This sketch consists of the code for the Slave module.
-   Resources: (A bit outdated)
-   a. https://espressif.com/sites/default/files/documentation/esp-now_user_guide_en.pdf
-   b. http://www.esploradores.com/practica-6-conexion-esp-now/
-
-   << This Device Slave >>
-
-   Flow: Master
-   Step 1 : ESPNow Init on Master and set it in STA mode
-   Step 2 : Start scanning for Slave ESP32 (we have added a prefix of `slave` to the SSID of slave for an easy setup)
-   Step 3 : Once found, add Slave as peer
-   Step 4 : Register for send callback
-   Step 5 : Start Transmitting data from Master to Slave
-
-   Flow: Slave
-   Step 1 : ESPNow Init on Slave
-   Step 2 : Update the SSID of Slave with a prefix of `slave`
-   Step 3 : Set Slave in AP mode
-   Step 4 : Register for receive callback and wait for data
-   Step 5 : Once data arrives, print it in the serial monitor
-
-   Note: Master and Slave have been defined to easily understand the setup.
-         Based on the ESPNOW API, there is no concept of Master and Slave.
-         Any devices can act as master or salve.
-*/
-
-#include <esp_now.h>
-#include <WiFi.h>
-
-#define CHANNEL 1
-
-// Init ESP Now with fallback
-void InitESPNow() {
-  WiFi.disconnect();
-  if (esp_now_init() == ESP_OK) {
-    Serial.println("ESPNow Init Success");
-  }
-  else {
-    Serial.println("ESPNow Init Failed");
-    // Retry InitESPNow, add a counte and then restart?
-    // InitESPNow();
-    // or Simply Restart
-    ESP.restart();
-  }
-}
-
-// config AP SSID
-void configDeviceAP() {
-  const char *SSID = "Slave_1";
-  bool result = WiFi.softAP(SSID, "Slave_1_Password", CHANNEL, 0);
-  if (!result) {
-    Serial.println("AP Config failed.");
-  } else {
-    Serial.println("AP Config Success. Broadcasting with AP: " + String(SSID));
-  }
-}
-
-void setup() {
-  Serial.begin(115200);
-  Serial.println("ESPNow/Basic/Slave Example");
-  //Set device in AP mode to begin with
-  WiFi.mode(WIFI_AP);
-  // configure device AP mode
-  configDeviceAP();
-  // This is the mac address of the Slave in AP Mode
-  Serial.print("AP MAC: "); Serial.println(WiFi.softAPmacAddress());
-  // Init ESPNow with a fallback logic
-  InitESPNow();
-  // Once ESPNow is successfully Init, we will register for recv CB to
-  // get recv packer info.
-  esp_now_register_recv_cb(OnDataRecv);
-}
-
-// callback when data is recv from Master
-void OnDataRecv(const uint8_t *mac_addr, const uint8_t *data, int data_len) {
-  char macStr[18];
-  snprintf(macStr, sizeof(macStr), "%02x:%02x:%02x:%02x:%02x:%02x",
-           mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
-  Serial.print("Last Packet Recv from: "); Serial.println(macStr);
-  Serial.print("Last Packet Recv Data: "); Serial.println(*data);
-  Serial.println("");
-}
-
-void loop() {
-  // Chill
-}
diff --git a/libraries/ESP32/examples/ESPNow/Multi-Slave/Master/Master.ino b/libraries/ESP32/examples/ESPNow/Multi-Slave/Master/Master.ino
deleted file mode 100644
index 6e212dd1121..00000000000
--- a/libraries/ESP32/examples/ESPNow/Multi-Slave/Master/Master.ino
+++ /dev/null
@@ -1,244 +0,0 @@
-/**
-   ESPNOW - Basic communication - Master
-   Date: 26th September 2017
-   Author: Arvind Ravulavaru <https://github.com/arvindr21>
-   Purpose: ESPNow Communication between a Master ESP32 and multiple ESP32 Slaves
-   Description: This sketch consists of the code for the Master module.
-   Resources: (A bit outdated)
-   a. https://espressif.com/sites/default/files/documentation/esp-now_user_guide_en.pdf
-   b. http://www.esploradores.com/practica-6-conexion-esp-now/
-
-   << This Device Master >>
-
-   Flow: Master
-   Step 1 : ESPNow Init on Master and set it in STA mode
-   Step 2 : Start scanning for Slave ESP32 (we have added a prefix of `slave` to the SSID of slave for an easy setup)
-   Step 3 : Once found, add Slave as peer
-   Step 4 : Register for send callback
-   Step 5 : Start Transmitting data from Master to Slave(s)
-
-   Flow: Slave
-   Step 1 : ESPNow Init on Slave
-   Step 2 : Update the SSID of Slave with a prefix of `slave`
-   Step 3 : Set Slave in AP mode
-   Step 4 : Register for receive callback and wait for data
-   Step 5 : Once data arrives, print it in the serial monitor
-
-   Note: Master and Slave have been defined to easily understand the setup.
-         Based on the ESPNOW API, there is no concept of Master and Slave.
-         Any devices can act as master or salve.
-
-
-  // Sample Serial log with 1 master & 2 slaves
-      Found 12 devices 
-      1: Slave:24:0A:C4:81:CF:A4 [24:0A:C4:81:CF:A5] (-44)
-      3: Slave:30:AE:A4:02:6D:CC [30:AE:A4:02:6D:CD] (-55)
-      2 Slave(s) found, processing..
-      Processing: 24:A:C4:81:CF:A5 Status: Already Paired
-      Processing: 30:AE:A4:2:6D:CD Status: Already Paired
-      Sending: 9
-      Send Status: Success
-      Last Packet Sent to: 24:0a:c4:81:cf:a5
-      Last Packet Send Status: Delivery Success
-      Send Status: Success
-      Last Packet Sent to: 30:ae:a4:02:6d:cd
-      Last Packet Send Status: Delivery Success
-
-*/
-
-#include <esp_now.h>
-#include <WiFi.h>
-
-// Global copy of slave
-#define NUMSLAVES 20
-esp_now_peer_info_t slaves[NUMSLAVES] = {};
-int SlaveCnt = 0;
-
-#define CHANNEL 3
-#define PRINTSCANRESULTS 0
-
-// Init ESP Now with fallback
-void InitESPNow() {
-  WiFi.disconnect();
-  if (esp_now_init() == ESP_OK) {
-    Serial.println("ESPNow Init Success");
-  }
-  else {
-    Serial.println("ESPNow Init Failed");
-    // Retry InitESPNow, add a counte and then restart?
-    // InitESPNow();
-    // or Simply Restart
-    ESP.restart();
-  }
-}
-
-// Scan for slaves in AP mode
-void ScanForSlave() {
-  int8_t scanResults = WiFi.scanNetworks();
-  //reset slaves
-  memset(slaves, 0, sizeof(slaves));
-  SlaveCnt = 0;
-  Serial.println("");
-  if (scanResults == 0) {
-    Serial.println("No WiFi devices in AP Mode found");
-  } else {
-    Serial.print("Found "); Serial.print(scanResults); Serial.println(" devices ");
-    for (int i = 0; i < scanResults; ++i) {
-      // Print SSID and RSSI for each device found
-      String SSID = WiFi.SSID(i);
-      int32_t RSSI = WiFi.RSSI(i);
-      String BSSIDstr = WiFi.BSSIDstr(i);
-
-      if (PRINTSCANRESULTS) {
-        Serial.print(i + 1); Serial.print(": "); Serial.print(SSID); Serial.print(" ["); Serial.print(BSSIDstr); Serial.print("]"); Serial.print(" ("); Serial.print(RSSI); Serial.print(")"); Serial.println("");
-      }
-      delay(10);
-      // Check if the current device starts with `Slave`
-      if (SSID.indexOf("Slave") == 0) {
-        // SSID of interest
-        Serial.print(i + 1); Serial.print(": "); Serial.print(SSID); Serial.print(" ["); Serial.print(BSSIDstr); Serial.print("]"); Serial.print(" ("); Serial.print(RSSI); Serial.print(")"); Serial.println("");
-        // Get BSSID => Mac Address of the Slave
-        int mac[6];
-
-        if ( 6 == sscanf(BSSIDstr.c_str(), "%x:%x:%x:%x:%x:%x",  &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5] ) ) {
-          for (int ii = 0; ii < 6; ++ii ) {
-            slaves[SlaveCnt].peer_addr[ii] = (uint8_t) mac[ii];
-          }
-        }
-        slaves[SlaveCnt].channel = CHANNEL; // pick a channel
-        slaves[SlaveCnt].encrypt = 0; // no encryption
-        SlaveCnt++;
-      }
-    }
-  }
-
-  if (SlaveCnt > 0) {
-    Serial.print(SlaveCnt); Serial.println(" Slave(s) found, processing..");
-  } else {
-    Serial.println("No Slave Found, trying again.");
-  }
-
-  // clean up ram
-  WiFi.scanDelete();
-}
-
-// Check if the slave is already paired with the master.
-// If not, pair the slave with master
-void manageSlave() {
-  if (SlaveCnt > 0) {
-    for (int i = 0; i < SlaveCnt; i++) {
-      Serial.print("Processing: ");
-      for (int ii = 0; ii < 6; ++ii ) {
-        Serial.print((uint8_t) slaves[i].peer_addr[ii], HEX);
-        if (ii != 5) Serial.print(":");
-      }
-      Serial.print(" Status: ");
-      // check if the peer exists
-      bool exists = esp_now_is_peer_exist(slaves[i].peer_addr);
-      if (exists) {
-        // Slave already paired.
-        Serial.println("Already Paired");
-      } else {
-        // Slave not paired, attempt pair
-        esp_err_t addStatus = esp_now_add_peer(&slaves[i]);
-        if (addStatus == ESP_OK) {
-          // Pair success
-          Serial.println("Pair success");
-        } else if (addStatus == ESP_ERR_ESPNOW_NOT_INIT) {
-          // How did we get so far!!
-          Serial.println("ESPNOW Not Init");
-        } else if (addStatus == ESP_ERR_ESPNOW_ARG) {
-          Serial.println("Add Peer - Invalid Argument");
-        } else if (addStatus == ESP_ERR_ESPNOW_FULL) {
-          Serial.println("Peer list full");
-        } else if (addStatus == ESP_ERR_ESPNOW_NO_MEM) {
-          Serial.println("Out of memory");
-        } else if (addStatus == ESP_ERR_ESPNOW_EXIST) {
-          Serial.println("Peer Exists");
-        } else {
-          Serial.println("Not sure what happened");
-        }
-        delay(100);
-      }
-    }
-  } else {
-    // No slave found to process
-    Serial.println("No Slave found to process");
-  }
-}
-
-
-uint8_t data = 0;
-// send data
-void sendData() {
-  data++;
-  for (int i = 0; i < SlaveCnt; i++) {
-    const uint8_t *peer_addr = slaves[i].peer_addr;
-    if (i == 0) { // print only for first slave
-      Serial.print("Sending: ");
-      Serial.println(data);
-    }
-    esp_err_t result = esp_now_send(peer_addr, &data, sizeof(data));
-    Serial.print("Send Status: ");
-    if (result == ESP_OK) {
-      Serial.println("Success");
-    } else if (result == ESP_ERR_ESPNOW_NOT_INIT) {
-      // How did we get so far!!
-      Serial.println("ESPNOW not Init.");
-    } else if (result == ESP_ERR_ESPNOW_ARG) {
-      Serial.println("Invalid Argument");
-    } else if (result == ESP_ERR_ESPNOW_INTERNAL) {
-      Serial.println("Internal Error");
-    } else if (result == ESP_ERR_ESPNOW_NO_MEM) {
-      Serial.println("ESP_ERR_ESPNOW_NO_MEM");
-    } else if (result == ESP_ERR_ESPNOW_NOT_FOUND) {
-      Serial.println("Peer not found.");
-    } else {
-      Serial.println("Not sure what happened");
-    }
-    delay(100);
-  }
-}
-
-// callback when data is sent from Master to Slave
-void OnDataSent(const uint8_t *mac_addr, esp_now_send_status_t status) {
-  char macStr[18];
-  snprintf(macStr, sizeof(macStr), "%02x:%02x:%02x:%02x:%02x:%02x",
-           mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
-  Serial.print("Last Packet Sent to: "); Serial.println(macStr);
-  Serial.print("Last Packet Send Status: "); Serial.println(status == ESP_NOW_SEND_SUCCESS ? "Delivery Success" : "Delivery Fail");
-}
-
-void setup() {
-  Serial.begin(115200);
-  //Set device in STA mode to begin with
-  WiFi.mode(WIFI_STA);
-  Serial.println("ESPNow/Multi-Slave/Master Example");
-  // This is the mac address of the Master in Station Mode
-  Serial.print("STA MAC: "); Serial.println(WiFi.macAddress());
-  // Init ESPNow with a fallback logic
-  InitESPNow();
-  // Once ESPNow is successfully Init, we will register for Send CB to
-  // get the status of Trasnmitted packet
-  esp_now_register_send_cb(OnDataSent);
-}
-
-void loop() {
-  // In the loop we scan for slave
-  ScanForSlave();
-  // If Slave is found, it would be populate in `slave` variable
-  // We will check if `slave` is defined and then we proceed further
-  if (SlaveCnt > 0) { // check if slave channel is defined
-    // `slave` is defined
-    // Add slave as peer if it has not been added already
-    manageSlave();
-    // pair success or already paired
-    // Send data to device
-    sendData();
-  } else {
-    // No slave found to process
-  }
-
-  // wait for 3seconds to run the logic again
-  delay(1000);
-}
diff --git a/libraries/ESP32/examples/ESPNow/Multi-Slave/Slave/Slave.ino b/libraries/ESP32/examples/ESPNow/Multi-Slave/Slave/Slave.ino
deleted file mode 100644
index 42ce40ba0d1..00000000000
--- a/libraries/ESP32/examples/ESPNow/Multi-Slave/Slave/Slave.ino
+++ /dev/null
@@ -1,94 +0,0 @@
-/**
-   ESPNOW - Basic communication - Slave
-   Date: 26th September 2017
-   Author: Arvind Ravulavaru <https://github.com/arvindr21>
-   Purpose: ESPNow Communication between a Master ESP32 and multiple ESP32 Slaves
-   Description: This sketch consists of the code for the Slave module.
-   Resources: (A bit outdated)
-   a. https://espressif.com/sites/default/files/documentation/esp-now_user_guide_en.pdf
-   b. http://www.esploradores.com/practica-6-conexion-esp-now/
-
-   << This Device Slave >>
-
-   Flow: Master
-   Step 1 : ESPNow Init on Master and set it in STA mode
-   Step 2 : Start scanning for Slave ESP32 (we have added a prefix of `slave` to the SSID of slave for an easy setup)
-   Step 3 : Once found, add Slave as peer
-   Step 4 : Register for send callback
-   Step 5 : Start Transmitting data from Master to Slave(s)
-
-   Flow: Slave
-   Step 1 : ESPNow Init on Slave
-   Step 2 : Update the SSID of Slave with a prefix of `slave`
-   Step 3 : Set Slave in AP mode
-   Step 4 : Register for receive callback and wait for data
-   Step 5 : Once data arrives, print it in the serial monitor
-
-   Note: Master and Slave have been defined to easily understand the setup.
-         Based on the ESPNOW API, there is no concept of Master and Slave.
-         Any devices can act as master or salve.
-*/
-
-#include <esp_now.h>
-#include <WiFi.h>
-
-#define CHANNEL 1
-
-// Init ESP Now with fallback
-void InitESPNow() {
-  WiFi.disconnect();
-  if (esp_now_init() == ESP_OK) {
-    Serial.println("ESPNow Init Success");
-  }
-  else {
-    Serial.println("ESPNow Init Failed");
-    // Retry InitESPNow, add a counte and then restart?
-    // InitESPNow();
-    // or Simply Restart
-    ESP.restart();
-  }
-}
-
-// config AP SSID
-void configDeviceAP() {
-  String Prefix = "Slave:";
-  String Mac = WiFi.macAddress();
-  String SSID = Prefix + Mac;
-  String Password = "123456789";
-  bool result = WiFi.softAP(SSID.c_str(), Password.c_str(), CHANNEL, 0);
-  if (!result) {
-    Serial.println("AP Config failed.");
-  } else {
-    Serial.println("AP Config Success. Broadcasting with AP: " + String(SSID));
-  }
-}
-
-void setup() {
-  Serial.begin(115200);
-  Serial.println("ESPNow/Basic/Slave Example");
-  //Set device in AP mode to begin with
-  WiFi.mode(WIFI_AP);
-  // configure device AP mode
-  configDeviceAP();
-  // This is the mac address of the Slave in AP Mode
-  Serial.print("AP MAC: "); Serial.println(WiFi.softAPmacAddress());
-  // Init ESPNow with a fallback logic
-  InitESPNow();
-  // Once ESPNow is successfully Init, we will register for recv CB to
-  // get recv packer info.
-  esp_now_register_recv_cb(OnDataRecv);
-}
-
-// callback when data is recv from Master
-void OnDataRecv(const uint8_t *mac_addr, const uint8_t *data, int data_len) {
-  char macStr[18];
-  snprintf(macStr, sizeof(macStr), "%02x:%02x:%02x:%02x:%02x:%02x",
-           mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
-  Serial.print("Last Packet Recv from: "); Serial.println(macStr);
-  Serial.print("Last Packet Recv Data: "); Serial.println(*data);
-  Serial.println("");
-}
-
-void loop() {
-  // Chill
-}
diff --git a/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/BasicMultiThreading.ino b/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/BasicMultiThreading.ino
new file mode 100644
index 00000000000..8704568dbeb
--- /dev/null
+++ b/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/BasicMultiThreading.ino
@@ -0,0 +1,122 @@
+/* Basic Multi Threading Arduino Example
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+// Please read file README.md in the folder containing this example.
+
+#if CONFIG_FREERTOS_UNICORE
+#define TASK_RUNNING_CORE 0
+#else
+#define TASK_RUNNING_CORE 1
+#endif
+
+#define ANALOG_INPUT_PIN A0
+
+#ifndef LED_BUILTIN
+#define LED_BUILTIN 13  // Specify the on which is your LED
+#endif
+
+// Define two tasks for Blink & AnalogRead.
+void TaskBlink(void *pvParameters);
+void TaskAnalogRead(void *pvParameters);
+TaskHandle_t analog_read_task_handle;  // You can (don't have to) use this to be able to manipulate a task from somewhere else.
+
+// The setup function runs once when you press reset or power on the board.
+void setup() {
+  // Initialize serial communication at 115200 bits per second:
+  Serial.begin(115200);
+  // Set up two tasks to run independently.
+  uint32_t blink_delay = 1000;  // Delay between changing state on LED pin
+  xTaskCreate(
+    TaskBlink, "Task Blink"  // A name just for humans
+    ,
+    2048  // The stack size can be checked by calling `uxHighWaterMark = uxTaskGetStackHighWaterMark(NULL);`
+    ,
+    (void *)&blink_delay  // Task parameter which can modify the task behavior. This must be passed as pointer to void.
+    ,
+    2  // Priority
+    ,
+    NULL  // Task handle is not used here - simply pass NULL
+  );
+
+  // This variant of task creation can also specify on which core it will be run (only relevant for multi-core ESPs)
+  xTaskCreatePinnedToCore(
+    TaskAnalogRead, "Analog Read", 2048  // Stack size
+    ,
+    NULL  // When no parameter is used, simply pass NULL
+    ,
+    1  // Priority
+    ,
+    &analog_read_task_handle  // With task handle we will be able to manipulate with this task.
+    ,
+    TASK_RUNNING_CORE  // Core on which the task will run
+  );
+
+  Serial.printf("Basic Multi Threading Arduino Example\n");
+  // Now the task scheduler, which takes over control of scheduling individual tasks, is automatically started.
+}
+
+void loop() {
+  if (analog_read_task_handle != NULL) {  // Make sure that the task actually exists
+    delay(10000);
+    vTaskDelete(analog_read_task_handle);  // Delete task
+    analog_read_task_handle = NULL;        // prevent calling vTaskDelete on non-existing task
+  }
+}
+
+/*--------------------------------------------------*/
+/*---------------------- Tasks ---------------------*/
+/*--------------------------------------------------*/
+
+void TaskBlink(void *pvParameters) {  // This is a task.
+  uint32_t blink_delay = *((uint32_t *)pvParameters);
+
+  /*
+  Blink
+  Turns on an LED on for one second, then off for one second, repeatedly.
+
+  If you want to know what pin the on-board LED is connected to on your ESP32 model, check
+  the Technical Specs of your board.
+*/
+
+  // initialize digital LED_BUILTIN on pin 13 as an output.
+  pinMode(LED_BUILTIN, OUTPUT);
+
+  for (;;) {                          // A Task shall never return or exit.
+    digitalWrite(LED_BUILTIN, HIGH);  // turn the LED on (HIGH is the voltage level)
+    // arduino-esp32 has FreeRTOS configured to have a tick-rate of 1000Hz and portTICK_PERIOD_MS
+    // refers to how many milliseconds the period between each ticks is, ie. 1ms.
+    delay(blink_delay);
+    digitalWrite(LED_BUILTIN, LOW);  // turn the LED off by making the voltage LOW
+    delay(blink_delay);
+  }
+}
+
+void TaskAnalogRead(void *pvParameters) {  // This is a task.
+  (void)pvParameters;
+  // Check if the given analog pin is usable - if not - delete this task
+  if (digitalPinToAnalogChannel(ANALOG_INPUT_PIN) == -1) {
+    Serial.printf("TaskAnalogRead cannot work because the given pin %d cannot be used for ADC - the task will delete itself.\n", ANALOG_INPUT_PIN);
+    analog_read_task_handle = NULL;  // Prevent calling vTaskDelete on non-existing task
+    vTaskDelete(NULL);               // Delete this task
+  }
+
+  /*
+  AnalogReadSerial
+  Reads an analog input on pin A3, prints the result to the serial monitor.
+  Graphical representation is available using serial plotter (Tools > Serial Plotter menu)
+  Attach the center pin of a potentiometer to pin A3, and the outside pins to +5V and ground.
+
+  This example code is in the public domain.
+*/
+
+  for (;;) {
+    // read the input on analog pin:
+    int sensorValue = analogRead(ANALOG_INPUT_PIN);
+    // print out the value you read:
+    Serial.println(sensorValue);
+    delay(100);  // 100ms delay
+  }
+}
diff --git a/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/README.md b/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/README.md
new file mode 100644
index 00000000000..f48e352dd45
--- /dev/null
+++ b/libraries/ESP32/examples/FreeRTOS/BasicMultiThreading/README.md
@@ -0,0 +1,85 @@
+# Basic Multi Threading Example
+
+This example demonstrates the basic usage of FreeRTOS Tasks for multi threading.
+
+Please refer to other examples in this folder to better utilize their full potential and safeguard potential problems.
+It is also advised to read the documentation on FreeRTOS web pages:
+[https://www.freertos.org/a00106.html](https://www.freertos.org/a00106.html)
+
+This example will blink the built-in LED and read analog data.
+Additionally, this example demonstrates the usage of the task handle, simply by deleting the analog
+read task after 10 seconds from the main loop by calling the function `vTaskDelete`.
+
+### Theory:
+A task is simply a function that runs when the operating system (FreeeRTOS) sees fit.
+This task can have an infinite loop inside if you want to do some work periodically for the entirety of the program run.
+This, however, can create a problem - no other task will ever run and also the Watch Dog will trigger and your program will restart.
+A nice behaving tasks know when it is useless to keep the processor for itself and give it away for other tasks to be used.
+This can be achieved in many ways, but the simplest is called `delay(`milliseconds)`.
+During that delay, any other task may run and do its job.
+When the delay runs out the Operating System gives the processor the task which can continue.
+For other ways to yield the CPU in a task please see other examples in this folder.
+It is also worth mentioning that two or more tasks running the same function will run them with separate stacks, so if you want to run the same code (which could be differentiated by the argument) there is no need to have multiple copies of the same function.
+
+**Task creation has a few parameters you should understand:**
+```
+  xTaskCreate(TaskFunction_t pxTaskCode,
+              const char * const pcName,
+              const uint16_t usStackDepth,
+              void * const pvParameters,
+              UBaseType_t uxPriority,
+              TaskHandle_t * const pxCreatedTask )
+```
+  - **pxTaskCode**      is the name of your function which will run as a task
+  - **pcName**          is a string of human-readable descriptions for your task
+  - **usStackDepth**    is the number of words (word = 4 B) available to the task. If you see an error similar to this "Debug exception reason: Stack canary watchpoint triggered (Task Blink)" you should increase it
+  - **pvParameters**    is a parameter that will be passed to the task function - it must be explicitly converted to (void*) and in your function explicitly converted back to the intended data type.
+  - **uxPriority**      is a number from 0 to configMAX_PRIORITIES which determines how the FreeRTOS will allow the tasks to run. 0 is the lowest priority.
+  - **pxCreatedTask**   task handle is a pointer to the task which allows you to manipulate the task - delete it, suspend and resume.
+                    If you don't need to do anything special with your task, simply pass NULL for this parameter.
+                    You can read more about task control here: https://www.freertos.org/a00112.html
+
+# Supported Targets
+
+This example supports all SoCs.
+
+### Hardware Connection
+
+If your board does not have a built-in LED, please connect one to the pin specified by the `LED_BUILTIN` in the code (you can also change the number and connect it to the pin you desire).
+
+Optionally you can connect the analog element to the pin. such as a variable resistor, analog input such as an audio signal, or any signal generator. However, if the pin is left unconnected it will receive background noise and you will also see a change in the signal when the pin is touched by a finger.
+Please refer to the ESP-IDF ADC documentation for specific SoC for info on which pins are available:
+[ESP32](https://docs.espressif.com/projects/esp-idf/en/v4.4/esp32/api-reference/peripherals/adc.html),
+ [ESP32-S2](https://docs.espressif.com/projects/esp-idf/en/v4.4/esp32s2/api-reference/peripherals/adc.html),
+ [ESP32-S3](https://docs.espressif.com/projects/esp-idf/en/v4.4/esp32s3/api-reference/peripherals/adc.html),
+ [ESP32-C3](https://docs.espressif.com/projects/esp-idf/en/v4.4/esp32c3/api-reference/peripherals/adc.html)
+
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Troubleshooting
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/ESP32/examples/FreeRTOS/FreeRTOS.ino b/libraries/ESP32/examples/FreeRTOS/FreeRTOS.ino
deleted file mode 100644
index 9f9fcdca349..00000000000
--- a/libraries/ESP32/examples/FreeRTOS/FreeRTOS.ino
+++ /dev/null
@@ -1,97 +0,0 @@
-#if CONFIG_FREERTOS_UNICORE
-#define ARDUINO_RUNNING_CORE 0
-#else
-#define ARDUINO_RUNNING_CORE 1
-#endif
-
-#ifndef LED_BUILTIN
-#define LED_BUILTIN 13
-#endif
-
-// define two tasks for Blink & AnalogRead
-void TaskBlink( void *pvParameters );
-void TaskAnalogReadA3( void *pvParameters );
-
-// the setup function runs once when you press reset or power the board
-void setup() {
-  
-  // initialize serial communication at 115200 bits per second:
-  Serial.begin(115200);
-  
-  // Now set up two tasks to run independently.
-  xTaskCreatePinnedToCore(
-    TaskBlink
-    ,  "TaskBlink"   // A name just for humans
-    ,  1024  // This stack size can be checked & adjusted by reading the Stack Highwater
-    ,  NULL
-    ,  2  // Priority, with 3 (configMAX_PRIORITIES - 1) being the highest, and 0 being the lowest.
-    ,  NULL 
-    ,  ARDUINO_RUNNING_CORE);
-
-  xTaskCreatePinnedToCore(
-    TaskAnalogReadA3
-    ,  "AnalogReadA3"
-    ,  1024  // Stack size
-    ,  NULL
-    ,  1  // Priority
-    ,  NULL 
-    ,  ARDUINO_RUNNING_CORE);
-
-  // Now the task scheduler, which takes over control of scheduling individual tasks, is automatically started.
-}
-
-void loop()
-{
-  // Empty. Things are done in Tasks.
-}
-
-/*--------------------------------------------------*/
-/*---------------------- Tasks ---------------------*/
-/*--------------------------------------------------*/
-
-void TaskBlink(void *pvParameters)  // This is a task.
-{
-  (void) pvParameters;
-
-/*
-  Blink
-  Turns on an LED on for one second, then off for one second, repeatedly.
-    
-  If you want to know what pin the on-board LED is connected to on your ESP32 model, check
-  the Technical Specs of your board.
-*/
-
-  // initialize digital LED_BUILTIN on pin 13 as an output.
-  pinMode(LED_BUILTIN, OUTPUT);
-
-  for (;;) // A Task shall never return or exit.
-  {
-    digitalWrite(LED_BUILTIN, HIGH);   // turn the LED on (HIGH is the voltage level)
-    vTaskDelay(100);  // one tick delay (15ms) in between reads for stability
-    digitalWrite(LED_BUILTIN, LOW);    // turn the LED off by making the voltage LOW
-    vTaskDelay(100);  // one tick delay (15ms) in between reads for stability
-  }
-}
-
-void TaskAnalogReadA3(void *pvParameters)  // This is a task.
-{
-  (void) pvParameters;
-  
-/*
-  AnalogReadSerial
-  Reads an analog input on pin A3, prints the result to the serial monitor.
-  Graphical representation is available using serial plotter (Tools > Serial Plotter menu)
-  Attach the center pin of a potentiometer to pin A3, and the outside pins to +5V and ground.
-
-  This example code is in the public domain.
-*/
-
-  for (;;)
-  {
-    // read the input on analog pin A3:
-    int sensorValueA3 = analogRead(A3);
-    // print out the value you read:
-    Serial.println(sensorValueA3);
-    vTaskDelay(10);  // one tick delay (15ms) in between reads for stability
-  }
-}
diff --git a/libraries/ESP32/examples/FreeRTOS/Mutex/Mutex.ino b/libraries/ESP32/examples/FreeRTOS/Mutex/Mutex.ino
new file mode 100644
index 00000000000..f368e0e864c
--- /dev/null
+++ b/libraries/ESP32/examples/FreeRTOS/Mutex/Mutex.ino
@@ -0,0 +1,102 @@
+/* Basic Multi Threading Arduino Example
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+// Please read file README.md in the folder containing this example.
+
+#define USE_MUTEX
+int shared_variable = 0;
+SemaphoreHandle_t shared_var_mutex = NULL;
+
+// Define a task function
+void Task(void *pvParameters);
+
+// The setup function runs once when you press reset or power on the board.
+void setup() {
+  // Initialize serial communication at 115200 bits per second:
+  Serial.begin(115200);
+
+  Serial.printf(" Task 0          | Task 1\n");
+
+#ifdef USE_MUTEX
+  shared_var_mutex = xSemaphoreCreateMutex();  // Create the mutex
+#endif
+
+  // Set up two tasks to run the same function independently.
+  static int task_number0 = 0;
+  xTaskCreate(
+    Task, "Task 0"  // A name just for humans
+    ,
+    2048  // The stack size
+    ,
+    (void *)&task_number0  // Pass reference to a variable describing the task number
+    //,  5  // High priority
+    ,
+    1  // priority
+    ,
+    NULL  // Task handle is not used here - simply pass NULL
+  );
+
+  static int task_number1 = 1;
+  xTaskCreate(
+    Task, "Task 1", 2048  // Stack size
+    ,
+    (void *)&task_number1  // Pass reference to a variable describing the task number
+    ,
+    1  // Low priority
+    ,
+    NULL  // Task handle is not used here - simply pass NULL
+  );
+
+  // Now the task scheduler, which takes over control of scheduling individual tasks, is automatically started.
+}
+
+void loop() {}
+
+/*--------------------------------------------------*/
+/*---------------------- Tasks ---------------------*/
+/*--------------------------------------------------*/
+
+void Task(void *pvParameters) {  // This is a task.
+  int task_num = *((int *)pvParameters);
+  Serial.printf("%s\n", task_num ? " Starting        |" : "                 | Starting");
+  for (;;) {  // A Task shall never return or exit.
+#ifdef USE_MUTEX
+    if (shared_var_mutex != NULL) {  // Sanity check if the mutex exists
+      // Try to take the mutex and wait indefinitely if needed
+      if (xSemaphoreTake(shared_var_mutex, portMAX_DELAY) == pdTRUE) {
+        // Mutex successfully taken
+#endif
+        int new_value = random(1000);
+
+        char str0[32];
+        sprintf(str0, " %d <- %d      |", shared_variable, new_value);
+        char str1[32];
+        sprintf(str1, "                 | %d <- %d", shared_variable, new_value);
+        Serial.printf("%s\n", task_num ? str0 : str1);
+
+        shared_variable = new_value;
+        delay(random(100));  // wait random time of max 100 ms - simulating some computation
+
+        sprintf(str0, " R: %d          |", shared_variable);
+        sprintf(str1, "                 | R: %d", shared_variable);
+        Serial.printf("%s\n", task_num ? str0 : str1);
+        //Serial.printf("Task %d after write: reading %d\n", task_num, shared_variable);
+
+        if (shared_variable != new_value) {
+          Serial.printf("%s\n", task_num ? " Mismatch!       |" : "                 | Mismatch!");
+          //Serial.printf("Task %d: detected race condition - the value changed!\n", task_num);
+        }
+
+#ifdef USE_MUTEX
+        xSemaphoreGive(shared_var_mutex);  // After accessing the shared resource give the mutex and allow other processes to access it
+      } else {
+        // We could not obtain the semaphore and can therefore not access the shared resource safely.
+      }  // mutex take
+    }  // sanity check
+#endif
+    delay(10);  // Allow other task to be scheduled
+  }  // Infinite loop
+}
diff --git a/libraries/ESP32/examples/FreeRTOS/Mutex/README.md b/libraries/ESP32/examples/FreeRTOS/Mutex/README.md
new file mode 100644
index 00000000000..435528bd771
--- /dev/null
+++ b/libraries/ESP32/examples/FreeRTOS/Mutex/README.md
@@ -0,0 +1,117 @@
+# Mutex Example
+
+This example demonstrates the basic usage of FreeRTOS Mutually Exclusive Locks (Mutex) for securing access to shared resources in multi-threading.
+Please refer to other examples in this folder to better understand the usage of tasks.
+It is also advised to read the documentation on FreeRTOS web pages:
+https://www.freertos.org/a00106.html
+
+This example creates 2 tasks with the same implementation - they write into a shared variable and then read it and check if it is the same as what they have written.
+In single-thread programming like on Arduino this is of no concern and will be always ok, however when multi-threading is used the execution of the task is switched by the FreeRTOS and the value can be rewritten from another task before reading again.
+The tasks print write and read operation - each in their column for better reading. Task 0 is on the left and Task 1 is on the right.
+Watch the writes and read in secure mode when using the mutex (default) as the results are as you would expect them.
+Then try to comment the USE_MUTEX and watch again - there will be a lot of mismatches!
+
+### Theory:
+Mutex is a specialized version of Semaphore (please see the Semaphore example for more info).
+In essence, the mutex is a variable whose value determines if the mute is taken (locked) or given (unlocked).
+When two or more processes access the same resource (variable, peripheral, etc) it might happen, for example, that when one task starts to read a variable and the operating system (FreeRTOS) will schedule the execution of another task
+which will write to this variable and when the previous task runs again it will read something different.
+
+Mutexes and binary semaphores are very similar but have some subtle differences:
+Mutexes include a priority inheritance mechanism, whereas binary semaphores do not.
+This makes binary semaphores the better choice for implementing synchronization (between tasks or between tasks and an interrupt), and mutexes the better
+choice for implementing simple mutual exclusion.
+What is priority inheritance?
+If a low-priority task holds the Mutex but gets interrupted by a Higher priority task, which
+then tries to take the Mutex, the low-priority task will temporarily ‘inherit’ the high priority so a middle-priority task can't block the low-priority task, and thus also block the high priority task.
+Semaphores don't have the logic to handle this, in part because Semaphores aren't 'owned' by the task that takes them.
+
+A mutex can also be recursive - if a task that holds the mutex takes it again, it will succeed, and the mutex will be released
+for other tasks only when it is given the same number of times that it was taken.
+
+You can check the danger by commenting on the definition of USE_MUTEX which will disable the mutex and present the danger of concurrent access.
+
+
+# Supported Targets
+
+This example supports all ESP32 SoCs.
+
+## How to Use Example
+
+Flash and observe the serial output.
+
+Comment the `USE_MUTEX` definition, save and flash again and observe the behavior of unprotected access to the shared variable.
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example Log Output
+
+The expected output of shared variables protected by mutex demonstrates mutually exclusive access from tasks - they do not interrupt each other and do not rewrite the value before the other task has read it back.
+
+```
+ Task 0          | Task 1
+                 | Starting
+                 | 0 <- 227
+ Starting        |
+                 | R: 227
+ 227 <- 737      |
+ R: 737          |
+                 | 737 <- 282
+                 | R: 282
+ 282 <- 267      |
+```
+
+The output of unprotected access to shared variable - it happens often that a task is interrupted after writing and before reading the other task write a different value - a corruption occurred!
+
+```
+ Task 0          | Task 1
+                 | Starting
+                 | 0 <- 333
+ Starting        |
+ 333 <- 620      |
+ R: 620          |
+ 620 <- 244      |
+                 | R: 244
+                 | Mismatch!
+                 | 244 <- 131
+ R: 131          |
+ Mismatch!       |
+ 131 <- 584      |
+                 | R: 584
+                 | Mismatch!
+                 | 584 <- 134
+                 | R: 134
+                 | 134 <- 554
+ R: 554          |
+ Mismatch!       |
+ 554 <- 313      |
+```
+
+## Troubleshooting
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/ESP32/examples/FreeRTOS/Queue/Queue.ino b/libraries/ESP32/examples/FreeRTOS/Queue/Queue.ino
new file mode 100644
index 00000000000..1ddecea30dc
--- /dev/null
+++ b/libraries/ESP32/examples/FreeRTOS/Queue/Queue.ino
@@ -0,0 +1,129 @@
+/* Basic Multi Threading Arduino Example
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+// Please read file README.md in the folder containing this example./*
+
+#define MAX_LINE_LENGTH (64)
+
+// Define two tasks for reading and writing from and to the serial port.
+void TaskWriteToSerial(void *pvParameters);
+void TaskReadFromSerial(void *pvParameters);
+
+// Define Queue handle
+QueueHandle_t QueueHandle;
+const int QueueElementSize = 10;
+typedef struct {
+  char line[MAX_LINE_LENGTH];
+  uint8_t line_length;
+} message_t;
+
+// The setup function runs once when you press reset or power on the board.
+void setup() {
+  // Initialize serial communication at 115200 bits per second:
+  Serial.begin(115200);
+
+  // Create the queue which will have <QueueElementSize> number of elements, each of size `message_t` and pass the address to <QueueHandle>.
+  QueueHandle = xQueueCreate(QueueElementSize, sizeof(message_t));
+
+  // Check if the queue was successfully created
+  if (QueueHandle == NULL) {
+    Serial.println("Queue could not be created. Halt.");
+    while (1) {
+      delay(1000);  // Halt at this point as is not possible to continue
+    }
+  }
+
+  // Set up two tasks to run independently.
+  xTaskCreate(
+    TaskWriteToSerial, "Task Write To Serial"  // A name just for humans
+    ,
+    2048  // The stack size can be checked by calling `uxHighWaterMark = uxTaskGetStackHighWaterMark(NULL);`
+    ,
+    NULL  // No parameter is used
+    ,
+    2  // Priority, with 3 (configMAX_PRIORITIES - 1) being the highest, and 0 being the lowest.
+    ,
+    NULL  // Task handle is not used here
+  );
+
+  xTaskCreate(
+    TaskReadFromSerial, "Task Read From Serial", 2048  // Stack size
+    ,
+    NULL  // No parameter is used
+    ,
+    1  // Priority
+    ,
+    NULL  // Task handle is not used here
+  );
+
+  // Now the task scheduler, which takes over control of scheduling individual tasks, is automatically started.
+  Serial.printf(
+    "\nAnything you write will return as echo.\nMaximum line length is %d characters (+ terminating '0').\nAnything longer will be sent as a separate "
+    "line.\n\n",
+    MAX_LINE_LENGTH - 1
+  );
+}
+
+void loop() {
+  // Loop is free to do any other work
+
+  delay(1000);  // While not being used yield the CPU to other tasks
+}
+
+/*--------------------------------------------------*/
+/*---------------------- Tasks ---------------------*/
+/*--------------------------------------------------*/
+
+void TaskWriteToSerial(void *pvParameters) {  // This is a task.
+  message_t message;
+  for (;;) {  // A Task shall never return or exit.
+    // One approach would be to poll the function (uxQueueMessagesWaiting(QueueHandle) and call delay if nothing is waiting.
+    // The other approach is to use infinite time to wait defined by constant `portMAX_DELAY`:
+    if (QueueHandle != NULL) {  // Sanity check just to make sure the queue actually exists
+      int ret = xQueueReceive(QueueHandle, &message, portMAX_DELAY);
+      if (ret == pdPASS) {
+        // The message was successfully received - send it back to Serial port and "Echo: "
+        Serial.printf("Echo line of size %d: \"%s\"\n", message.line_length, message.line);
+        // The item is queued by copy, not by reference, so lets free the buffer after use.
+      } else if (ret == pdFALSE) {
+        Serial.println("The `TaskWriteToSerial` was unable to receive data from the Queue");
+      }
+    }  // Sanity check
+  }  // Infinite loop
+}
+
+void TaskReadFromSerial(void *pvParameters) {  // This is a task.
+  message_t message;
+  for (;;) {
+    // Check if any data are waiting in the Serial buffer
+    message.line_length = Serial.available();
+    if (message.line_length > 0) {
+      // Check if the queue exists AND if there is any free space in the queue
+      if (QueueHandle != NULL && uxQueueSpacesAvailable(QueueHandle) > 0) {
+        int max_length = message.line_length < MAX_LINE_LENGTH ? message.line_length : MAX_LINE_LENGTH - 1;
+        for (int i = 0; i < max_length; ++i) {
+          message.line[i] = Serial.read();
+        }
+        message.line_length = max_length;
+        message.line[message.line_length] = 0;  // Add the terminating nul char
+
+        // The line needs to be passed as pointer to void.
+        // The last parameter states how many milliseconds should wait (keep trying to send) if is not possible to send right away.
+        // When the wait parameter is 0 it will not wait and if the send is not possible the function will return errQUEUE_FULL
+        int ret = xQueueSend(QueueHandle, (void *)&message, 0);
+        if (ret == pdTRUE) {
+          // The message was successfully sent.
+        } else if (ret == errQUEUE_FULL) {
+          // Since we are checking uxQueueSpacesAvailable this should not occur, however if more than one task should
+          //   write into the same queue it can fill-up between the test and actual send attempt
+          Serial.println("The `TaskReadFromSerial` was unable to send data into the Queue");
+        }  // Queue send check
+      }  // Queue sanity check
+    } else {
+      delay(100);  // Allow other tasks to run when there is nothing to read
+    }  // Serial buffer check
+  }  // Infinite loop
+}
diff --git a/libraries/ESP32/examples/FreeRTOS/Queue/README.md b/libraries/ESP32/examples/FreeRTOS/Queue/README.md
new file mode 100644
index 00000000000..e81d6741e2a
--- /dev/null
+++ b/libraries/ESP32/examples/FreeRTOS/Queue/README.md
@@ -0,0 +1,71 @@
+# Queue Example
+
+This example demonstrates the basic usage of FreeRTOS Queues which enables tasks to pass data between each other in a secure asynchronous way.
+Please refer to other examples in this folder to better understand the usage of tasks.
+It is also advised to read the documentation on FreeRTOS web pages:
+[https://www.freertos.org/a00106.html](https://www.freertos.org/a00106.html)
+
+This example reads data received on the serial port (sent by the user) pass it via queue to another task which will send it back on Serial Output.
+
+### Theory:
+A queue is a simple-to-use data structure (in the most basic way) controlled by `xQueueSend` and `xQueueReceive` functions.
+Usually, one task writes into the queue and the other task reads from it.
+Usage of queues enables the reading task to yield the CPU until there are data in the queue and therefore not waste precious computation time.
+
+# Supported Targets
+
+This example supports all ESP32 SoCs.
+
+## How to Use Example
+
+Flash and write anything to serial input.
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example Log Output
+
+```
+Anything you write will return as echo.
+Maximum line length is 63 characters (+ terminating '0').
+Anything longer will be sent as a separate line.
+
+```
+< Input text "Short input"
+
+``Echo line of size 11: "Short input"``
+
+< Input text "An example of very long input which is longer than default 63 characters will be split."
+
+```
+Echo line of size 63: "An example of very long input which is longer than default 63 c"
+Echo line of size 24: "haracters will be split."
+```
+
+## Troubleshooting
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/ESP32/examples/FreeRTOS/Semaphore/README.md b/libraries/ESP32/examples/FreeRTOS/Semaphore/README.md
new file mode 100644
index 00000000000..fcb38eed1d6
--- /dev/null
+++ b/libraries/ESP32/examples/FreeRTOS/Semaphore/README.md
@@ -0,0 +1,77 @@
+# Semaphore Example
+
+This example demonstrates the basic usage of FreeRTOS Semaphores and queue sets for coordination between tasks for multi-threading.
+Please refer to other examples in this folder to better understand the usage of tasks.
+It is also advised to read the documentation on FreeRTOS web pages:
+[https://www.freertos.org/a00106.html](https://www.freertos.org/a00106.html)
+
+### Theory:
+Semaphore is in essence a variable. Tasks can set the value, wait until one or more
+semaphores are set and thus communicate between each other their state.
+A binary semaphore is a semaphore that has a maximum count of 1, hence the 'binary' name.
+A task can only 'take' the semaphore if it is available, and the semaphore is only available if its count is 1.
+
+Semaphores can be controlled by any number of tasks. If you use semaphore as a one-way
+signalization with only one task giving and only one task taking there is a much faster option
+called Task Notifications - please see FreeRTOS documentation and read more about them: [https://www.freertos.org/RTOS-task-notifications.html](https://www.freertos.org/RTOS-task-notifications.html)
+
+This example uses a semaphore to signal when a package is delivered to a warehouse by multiple
+delivery trucks, and multiple workers are waiting to receive the package.
+
+# Supported Targets
+
+This example supports all ESP32 SoCs.
+
+## How to Use Example
+
+Read the code and try to understand it, then flash and observe the Serial output.
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example Log Output
+
+```
+Anything you write will return as echo.
+Maximum line length is 63 characters (+ terminating '0').
+Anything longer will be sent as a separate line.
+
+```
+< Input text "Short input"
+
+``Echo line of size 11: "Short input"``
+
+< Input text "An example of very long input which is longer than default 63 characters will be split."
+
+```
+Echo line of size 63: "An example of very long input which is longer than default 63 c"
+Echo line of size 24: "haracters will be split."
+```
+
+## Troubleshooting
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/ESP32/examples/FreeRTOS/Semaphore/Semaphore.ino b/libraries/ESP32/examples/FreeRTOS/Semaphore/Semaphore.ino
new file mode 100644
index 00000000000..077d20329e3
--- /dev/null
+++ b/libraries/ESP32/examples/FreeRTOS/Semaphore/Semaphore.ino
@@ -0,0 +1,56 @@
+/* Basic Multi Threading Arduino Example
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+// Please read file README.md in the folder containing this example.
+
+#include <Arduino.h>
+
+SemaphoreHandle_t package_delivered_semaphore;
+
+void delivery_truck_task(void *pvParameters) {
+  int truck_number = (int)pvParameters;
+  while (1) {
+    // Wait for a package to be delivered
+    // ...
+    // Notify the warehouse that a package has been delivered
+    xSemaphoreGive(package_delivered_semaphore);
+    Serial.printf("Package delivered by truck: %d\n", truck_number);
+    //wait for some time
+    vTaskDelay(1000 / portTICK_PERIOD_MS);
+  }
+}
+
+void warehouse_worker_task(void *pvParameters) {
+  int worker_number = (int)pvParameters;
+  while (1) {
+    // Wait for a package to be delivered
+    xSemaphoreTake(package_delivered_semaphore, portMAX_DELAY);
+    Serial.printf("Package received by worker: %d\n", worker_number);
+    // Receive the package
+    // ...
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  // Create the semaphore
+  package_delivered_semaphore = xSemaphoreCreateCounting(10, 0);
+
+  // Create multiple delivery truck tasks
+  for (int i = 0; i < 5; i++) {
+    xTaskCreate(delivery_truck_task, "Delivery Truck", 2048, (void *)i, tskIDLE_PRIORITY, NULL);
+  }
+
+  // Create multiple warehouse worker tasks
+  for (int i = 0; i < 3; i++) {
+    xTaskCreate(warehouse_worker_task, "Warehouse Worker", 2048, (void *)i, tskIDLE_PRIORITY, NULL);
+  }
+}
+
+void loop() {
+  // Empty loop
+}
diff --git a/libraries/ESP32/examples/GPIO/BlinkRGB/BlinkRGB.ino b/libraries/ESP32/examples/GPIO/BlinkRGB/BlinkRGB.ino
new file mode 100644
index 00000000000..9544ce7cc25
--- /dev/null
+++ b/libraries/ESP32/examples/GPIO/BlinkRGB/BlinkRGB.ino
@@ -0,0 +1,39 @@
+/*
+  BlinkRGB
+
+  Demonstrates usage of onboard RGB LED on some ESP dev boards.
+
+  Calling digitalWrite(RGB_BUILTIN, HIGH) will use hidden RGB driver.
+
+  RGBLedWrite demonstrates control of each channel:
+  void rgbLedWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val)
+
+  WARNING: After using digitalWrite to drive RGB LED it will be impossible to drive the same pin
+    with normal HIGH/LOW level
+*/
+//#define RGB_BRIGHTNESS 64 // Change white brightness (max 255)
+
+// the setup function runs once when you press reset or power the board
+
+void setup() {
+  // No need to initialize the RGB LED
+}
+
+// the loop function runs over and over again forever
+void loop() {
+#ifdef RGB_BUILTIN
+  digitalWrite(RGB_BUILTIN, HIGH);  // Turn the RGB LED white
+  delay(1000);
+  digitalWrite(RGB_BUILTIN, LOW);  // Turn the RGB LED off
+  delay(1000);
+
+  rgbLedWrite(RGB_BUILTIN, RGB_BRIGHTNESS, 0, 0);  // Red
+  delay(1000);
+  rgbLedWrite(RGB_BUILTIN, 0, RGB_BRIGHTNESS, 0);  // Green
+  delay(1000);
+  rgbLedWrite(RGB_BUILTIN, 0, 0, RGB_BRIGHTNESS);  // Blue
+  delay(1000);
+  rgbLedWrite(RGB_BUILTIN, 0, 0, 0);  // Off / black
+  delay(1000);
+#endif
+}
diff --git a/libraries/ESP32/examples/GPIO/FunctionalInterrupt/FunctionalInterrupt.ino b/libraries/ESP32/examples/GPIO/FunctionalInterrupt/FunctionalInterrupt.ino
index 0e9f97414bb..a38c6e6b5bc 100644
--- a/libraries/ESP32/examples/GPIO/FunctionalInterrupt/FunctionalInterrupt.ino
+++ b/libraries/ESP32/examples/GPIO/FunctionalInterrupt/FunctionalInterrupt.ino
@@ -1,47 +1,69 @@
+/*
+ * This example demonstrates usage of interrupt by detecting a button press.
+ *
+ * Setup: Connect first button between pin defined in BUTTON1 and GND
+ *        Similarly connect second button between pin defined in BUTTON2 and GND.
+ *        If you do not have a button simply connect a wire to those buttons
+ *        - touching GND pin with other end of the wire will behave same as pressing the connected button.
+ *        Wen using the bare wire be careful not to touch any other pin by accident.
+ *
+ * Note: There is no de-bounce implemented and the physical connection will normally
+ *       trigger many more button presses than actually happened.
+ *       This is completely normal and is not to be considered a fault.
+ */
+
 #include <Arduino.h>
 #include <FunctionalInterrupt.h>
 
 #define BUTTON1 16
 #define BUTTON2 17
 
-class Button
-{
+class Button {
 public:
-	Button(uint8_t reqPin) : PIN(reqPin){
-		pinMode(PIN, INPUT_PULLUP);
-		attachInterrupt(PIN, std::bind(&Button::isr,this), FALLING);
-	};
-	~Button() {
-		detachInterrupt(PIN);
-	}
-
-	void IRAM_ATTR isr() {
-		numberKeyPresses += 1;
-		pressed = true;
-	}
-
-	void checkPressed() {
-		if (pressed) {
-			Serial.printf("Button on pin %u has been pressed %u times\n", PIN, numberKeyPresses);
-			pressed = false;
-		}
-	}
+  Button(uint8_t reqPin) : PIN(reqPin) {
+    pinMode(PIN, INPUT_PULLUP);
+  };
+
+  void begin() {
+    attachInterrupt(PIN, std::bind(&Button::isr, this), FALLING);
+    Serial.printf("Started button interrupt on pin %d\n", PIN);
+  }
+
+  ~Button() {
+    detachInterrupt(PIN);
+  }
+
+  void ARDUINO_ISR_ATTR isr() {
+    numberKeyPresses = numberKeyPresses + 1;
+    pressed = true;
+  }
+
+  void checkPressed() {
+    if (pressed) {
+      Serial.printf("Button on pin %u has been pressed %lu times\n", PIN, numberKeyPresses);
+      pressed = false;
+    }
+  }
 
 private:
-	const uint8_t PIN;
-    volatile uint32_t numberKeyPresses;
-    volatile bool pressed;
+  const uint8_t PIN;
+  volatile uint32_t numberKeyPresses;
+  volatile bool pressed;
 };
 
 Button button1(BUTTON1);
 Button button2(BUTTON2);
 
-
 void setup() {
-    Serial.begin(115200);
+  Serial.begin(115200);
+
+  Serial.println("Starting Functional Interrupt example.");
+  button1.begin();
+  button2.begin();
+  Serial.println("Setup done.");
 }
 
 void loop() {
-	button1.checkPressed();
-	button2.checkPressed();
+  button1.checkPressed();
+  button2.checkPressed();
 }
diff --git a/libraries/ESP32/examples/GPIO/FunctionalInterruptStruct/FunctionalInterruptStruct.ino b/libraries/ESP32/examples/GPIO/FunctionalInterruptStruct/FunctionalInterruptStruct.ino
new file mode 100644
index 00000000000..1b4d549c53f
--- /dev/null
+++ b/libraries/ESP32/examples/GPIO/FunctionalInterruptStruct/FunctionalInterruptStruct.ino
@@ -0,0 +1,39 @@
+#include <Arduino.h>
+
+#define BUTTON1 16
+#define BUTTON2 17
+
+struct Button {
+  uint8_t PIN;
+  volatile uint32_t numberKeyPresses;
+  volatile int pressed;
+};
+
+void isr(void *param) {
+  struct Button *button = (struct Button *)param;
+  button->numberKeyPresses = button->numberKeyPresses + 1;
+  button->pressed = 1;
+}
+
+void checkPressed(struct Button *button) {
+  if (button->pressed) {
+    Serial.printf("Button on pin %u has been pressed %lu times\n", button->PIN, button->numberKeyPresses);
+    button->pressed = 0;
+  }
+}
+
+struct Button button1 = {BUTTON1, 0, 0};
+struct Button button2 = {BUTTON2, 0, 0};
+
+void setup() {
+  Serial.begin(115200);
+  pinMode(button1.PIN, INPUT_PULLUP);
+  pinMode(button2.PIN, INPUT_PULLUP);
+  attachInterruptArg(button1.PIN, isr, (void *)&button1, FALLING);
+  attachInterruptArg(button2.PIN, isr, (void *)&button2, FALLING);
+}
+
+void loop() {
+  checkPressed(&button1);
+  checkPressed(&button2);
+}
diff --git a/libraries/ESP32/examples/GPIO/GPIOInterrupt/GPIOInterrupt.ino b/libraries/ESP32/examples/GPIO/GPIOInterrupt/GPIOInterrupt.ino
index c3d1245fa0c..2e94176224e 100644
--- a/libraries/ESP32/examples/GPIO/GPIOInterrupt/GPIOInterrupt.ino
+++ b/libraries/ESP32/examples/GPIO/GPIOInterrupt/GPIOInterrupt.ino
@@ -1,45 +1,45 @@
 #include <Arduino.h>
 
 struct Button {
-    const uint8_t PIN;
-    uint32_t numberKeyPresses;
-    bool pressed;
+  const uint8_t PIN;
+  uint32_t numberKeyPresses;
+  bool pressed;
 };
 
 Button button1 = {23, 0, false};
 Button button2 = {18, 0, false};
 
-void IRAM_ATTR isr(void* arg) {
-    Button* s = static_cast<Button*>(arg);
-    s->numberKeyPresses += 1;
-    s->pressed = true;
+void ARDUINO_ISR_ATTR isr(void *arg) {
+  Button *s = static_cast<Button *>(arg);
+  s->numberKeyPresses += 1;
+  s->pressed = true;
 }
 
-void IRAM_ATTR isr() {
-    button2.numberKeyPresses += 1;
-    button2.pressed = true;
+void ARDUINO_ISR_ATTR isr() {
+  button2.numberKeyPresses += 1;
+  button2.pressed = true;
 }
 
 void setup() {
-    Serial.begin(115200);
-    pinMode(button1.PIN, INPUT_PULLUP);
-    attachInterruptArg(button1.PIN, isr, &button1, FALLING);
-    pinMode(button2.PIN, INPUT_PULLUP);
-    attachInterrupt(button2.PIN, isr, FALLING);
+  Serial.begin(115200);
+  pinMode(button1.PIN, INPUT_PULLUP);
+  attachInterruptArg(button1.PIN, isr, &button1, FALLING);
+  pinMode(button2.PIN, INPUT_PULLUP);
+  attachInterrupt(button2.PIN, isr, FALLING);
 }
 
 void loop() {
-    if (button1.pressed) {
-        Serial.printf("Button 1 has been pressed %u times\n", button1.numberKeyPresses);
-        button1.pressed = false;
-    }
-    if (button2.pressed) {
-        Serial.printf("Button 2 has been pressed %u times\n", button2.numberKeyPresses);
-        button2.pressed = false;
-    }
-    static uint32_t lastMillis = 0;
-    if (millis() - lastMillis > 10000) {
-      lastMillis = millis();
-      detachInterrupt(button1.PIN);
-    }
+  if (button1.pressed) {
+    Serial.printf("Button 1 has been pressed %lu times\n", button1.numberKeyPresses);
+    button1.pressed = false;
+  }
+  if (button2.pressed) {
+    Serial.printf("Button 2 has been pressed %lu times\n", button2.numberKeyPresses);
+    button2.pressed = false;
+  }
+  static uint32_t lastMillis = 0;
+  if (millis() - lastMillis > 10000) {
+    lastMillis = millis();
+    detachInterrupt(button1.PIN);
+  }
 }
diff --git a/libraries/ESP32/examples/HWCDC_Events/HWCDC_Events.ino b/libraries/ESP32/examples/HWCDC_Events/HWCDC_Events.ino
new file mode 100644
index 00000000000..77028897bc4
--- /dev/null
+++ b/libraries/ESP32/examples/HWCDC_Events/HWCDC_Events.ino
@@ -0,0 +1,87 @@
+/*
+ * This Example demonstrates how to receive Hardware Serial Events
+ * This USB interface is available for the ESP32-S3, ESP32-C3, ESP32-C6 and ESP32-H2
+ *
+ * It will log all events and USB status (plugged/unplugged) into UART0
+ * Any data read from UART0 will be sent to the USB CDC
+ * Any data read from USB CDC will be sent to the UART0
+ *
+ * A suggestion is to use Arduino Serial Monitor for the UART0 port
+ * and some other serial monitor application for the USB CDC port
+ * in order to see the exchanged data and the Hardware Serial Events
+ *
+ */
+
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 0
+#warning This sketch should be used when USB is in Hardware CDC and JTAG mode
+void setup() {}
+void loop() {}
+#else
+
+#if !ARDUINO_USB_CDC_ON_BOOT
+HWCDC HWCDCSerial;
+#endif
+
+// USB Event Callback Function that will log CDC events into UART0
+static void usbEventCallback(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == ARDUINO_HW_CDC_EVENTS) {
+    switch (event_id) {
+      case ARDUINO_HW_CDC_CONNECTED_EVENT: Serial0.println("CDC EVENT:: ARDUINO_HW_CDC_CONNECTED_EVENT"); break;
+      case ARDUINO_HW_CDC_BUS_RESET_EVENT: Serial0.println("CDC EVENT:: ARDUINO_HW_CDC_BUS_RESET_EVENT"); break;
+      case ARDUINO_HW_CDC_RX_EVENT:
+        Serial0.println("\nCDC EVENT:: ARDUINO_HW_CDC_RX_EVENT");
+        // sends all bytes read from USB Hardware Serial to UART0
+        while (HWCDCSerial.available()) {
+          Serial0.write(HWCDCSerial.read());
+        }
+        break;
+      case ARDUINO_HW_CDC_TX_EVENT: Serial0.println("CDC EVENT:: ARDUINO_HW_CDC_TX_EVENT"); break;
+
+      default: break;
+    }
+  }
+}
+
+const char *_hwcdc_status[] = {
+  " USB Plugged but CDC is NOT connected\r\n",
+  " USB Plugged and CDC is connected\r\n",
+  " USB Unplugged and CDC NOT connected\r\n",
+  " USB Unplugged BUT CDC is connected :: PROBLEM\r\n",
+};
+
+const char *HWCDC_Status() {
+  int i = HWCDCSerial.isPlugged() ? 0 : 2;
+  if (HWCDCSerial.isConnected()) {
+    i += 1;
+  }
+  return _hwcdc_status[i];
+}
+
+void setup() {
+  HWCDCSerial.onEvent(usbEventCallback);
+  HWCDCSerial.begin();
+
+  Serial0.begin(115200);
+  Serial0.setDebugOutput(true);
+  Serial0.println("Starting...");
+}
+
+void loop() {
+  static uint32_t counter = 0;
+
+  Serial0.print(counter);
+  Serial0.print(HWCDC_Status());
+
+  if (HWCDCSerial) {
+    HWCDCSerial.printf("  [%ld] connected\n\r", counter);
+  }
+  // sends all bytes read from UART0 to USB Hardware Serial
+  while (Serial0.available()) {
+    HWCDCSerial.write(Serial0.read());
+  }
+  delay(1000);
+  counter++;
+}
+#endif
diff --git a/libraries/ESP32/examples/HWCDC_Events/ci.json b/libraries/ESP32/examples/HWCDC_Events/ci.json
new file mode 100644
index 00000000000..56e38bbcdf2
--- /dev/null
+++ b/libraries/ESP32/examples/HWCDC_Events/ci.json
@@ -0,0 +1,10 @@
+{
+  "fqbn": {
+    "esp32s3": [
+      "espressif:esp32:esp32s3:USBMode=hwcdc,PartitionScheme=huge_app,FlashMode=dio"
+    ]
+  },
+  "requires": [
+    "CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP32/examples/HallSensor/HallSensor.ino b/libraries/ESP32/examples/HallSensor/HallSensor.ino
deleted file mode 100644
index 3db5951d4d8..00000000000
--- a/libraries/ESP32/examples/HallSensor/HallSensor.ino
+++ /dev/null
@@ -1,16 +0,0 @@
-//Simple sketch to access the internal hall effect detector on the esp32.
-//values can be quite low. 
-//Brian Degger / @sctv  
-
-int val = 0;
-void setup() {
-  Serial.begin(9600);
-    }
-
-void loop() {
-  // put your main code here, to run repeatedly:
-  val = hallRead();
-  // print the results to the serial monitor:
-  //Serial.print("sensor = ");
-  Serial.println(val);//to graph 
-}
diff --git a/libraries/ESP32/examples/I2S/HiFreq_ADC/HiFreq_ADC.ino b/libraries/ESP32/examples/I2S/HiFreq_ADC/HiFreq_ADC.ino
deleted file mode 100644
index df328d1d6b1..00000000000
--- a/libraries/ESP32/examples/I2S/HiFreq_ADC/HiFreq_ADC.ino
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * This is an example to read analog data at high frequency using the I2S peripheral
- * Run a wire between pins 27 & 32
- * The readings from the device will be 12bit (0-4096) 
- */
-#include <driver/i2s.h>
-
-#define I2S_SAMPLE_RATE 78125
-#define ADC_INPUT ADC1_CHANNEL_4 //pin 32
-#define OUTPUT_PIN 27
-#define OUTPUT_VALUE 3800
-#define READ_DELAY 9000 //microseconds
-
-uint16_t adc_reading;
-
-void i2sInit()
-{
-   i2s_config_t i2s_config = {
-    .mode = (i2s_mode_t)(I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_ADC_BUILT_IN),
-    .sample_rate =  I2S_SAMPLE_RATE,              // The format of the signal using ADC_BUILT_IN
-    .bits_per_sample = I2S_BITS_PER_SAMPLE_16BIT, // is fixed at 12bit, stereo, MSB
-    .channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
-    .communication_format = I2S_COMM_FORMAT_I2S_MSB,
-    .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
-    .dma_buf_count = 4,
-    .dma_buf_len = 8,
-    .use_apll = false,
-    .tx_desc_auto_clear = false,
-    .fixed_mclk = 0
-   };
-   i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL);
-   i2s_set_adc_mode(ADC_UNIT_1, ADC_INPUT);
-   i2s_adc_enable(I2S_NUM_0);
-}
-
-void reader(void *pvParameters) {
-  uint32_t read_counter = 0;
-  uint64_t read_sum = 0;
-// The 4 high bits are the channel, and the data is inverted
-  uint16_t offset = (int)ADC_INPUT * 0x1000 + 0xFFF;
-  size_t bytes_read;
-  while(1){
-    uint16_t buffer[2] = {0};
-    i2s_read(I2S_NUM_0, &buffer, sizeof(buffer), &bytes_read, 15);
-    //Serial.printf("%d  %d\n", offset - buffer[0], offset - buffer[1]);
-    if (bytes_read == sizeof(buffer)) {
-      read_sum += offset - buffer[0];
-      read_sum += offset - buffer[1];
-      read_counter++;
-    } else {
-      Serial.println("buffer empty");
-    }
-    if (read_counter == I2S_SAMPLE_RATE) {
-      adc_reading = read_sum / I2S_SAMPLE_RATE / 2;
-      //Serial.printf("avg: %d millis: ", adc_reading);
-      //Serial.println(millis());
-      read_counter = 0;
-      read_sum = 0;
-      i2s_adc_disable(I2S_NUM_0);
-      delay(READ_DELAY);
-      i2s_adc_enable(I2S_NUM_0);
-    }
-  }
-}
-
-void setup() {
-  Serial.begin(115200);
-  // Put a signal out on pin 
-  uint32_t freq = ledcSetup(0, I2S_SAMPLE_RATE, 10);
-  Serial.printf("Output frequency: %d\n", freq);
-  ledcWrite(0, OUTPUT_VALUE/4);
-  ledcAttachPin(OUTPUT_PIN, 0);
-  // Initialize the I2S peripheral
-  i2sInit();
-  // Create a task that will read the data
-  xTaskCreatePinnedToCore(reader, "ADC_reader", 2048, NULL, 1, NULL, 1);
-}
-
-void loop() {
-  delay(1020);
-  Serial.printf("ADC reading: %d\n", adc_reading);
-  delay(READ_DELAY);
-}
diff --git a/libraries/ESP32/examples/MacAddress/GetMacAddress/GetMacAddress.ino b/libraries/ESP32/examples/MacAddress/GetMacAddress/GetMacAddress.ino
new file mode 100644
index 00000000000..effcd0e5642
--- /dev/null
+++ b/libraries/ESP32/examples/MacAddress/GetMacAddress/GetMacAddress.ino
@@ -0,0 +1,86 @@
+/*
+ * GetMacAddress
+ *
+ * This sketch prints out the MAC addresses for different interfaces.
+ *
+ * Written by: Daniel Nebert
+ *
+ * The first printed MAC address is obtained by calling 'esp_efuse_mac_get_default'
+ * (https://docs.espressif.com/projects/esp-idf/en/release-v5.1/esp32/api-reference/system/misc_system_api.html#_CPPv425esp_efuse_mac_get_defaultP7uint8_t)
+ * which returns base MAC address which is factory-programmed by Espressif in EFUSE.
+ *
+ * The remaining printed MAC addresses is obtained by calling 'esp_read_mac'
+ * (https://docs.espressif.com/projects/esp-idf/en/release-v5.1/esp32/api-reference/system/misc_system_api.html#_CPPv412esp_read_macP7uint8_t14esp_mac_type_t)
+ * and passing in the 'esp_mac_type_t' type.
+ * (https://docs.espressif.com/projects/esp-idf/en/release-v5.1/esp32/api-reference/system/misc_system_api.html#esp__mac_8h_1a1b19aca597277a2179682869c140477a)
+ *
+
+esp_mac_type_t values:
+
+  ESP_MAC_WIFI_STA - MAC for WiFi Station (6 bytes)
+  ESP_MAC_WIFI_SOFTAP - MAC for WiFi Soft-AP (6 bytes)
+  ESP_MAC_BT - MAC for Bluetooth (6 bytes)
+  ESP_MAC_ETH - MAC for Ethernet (6 bytes)
+  ESP_MAC_IEEE802154 - if CONFIG_SOC_IEEE802154_SUPPORTED=y, MAC for IEEE802154 (8 bytes)
+  ESP_MAC_BASE - Base MAC for that used for other MAC types (6 bytes)
+  ESP_MAC_EFUSE_FACTORY - MAC_FACTORY eFuse which was burned by Espressif in production (6 bytes)
+  ESP_MAC_EFUSE_CUSTOM - MAC_CUSTOM eFuse which was can be burned by customer (6 bytes)
+  ESP_MAC_EFUSE_EXT - if CONFIG_SOC_IEEE802154_SUPPORTED=y, MAC_EXT eFuse which is used as an extender for IEEE802154 MAC (2 bytes)
+
+*/
+
+#include "esp_mac.h"  // required - exposes esp_mac_type_t values
+
+void setup() {
+
+  Serial.begin(115200);
+
+  Serial.println("Interface\t\t\t\t\t\tMAC address (6 bytes, 4 universally administered, default)");
+
+  Serial.print("Wi-Fi Station (using 'esp_efuse_mac_get_default')\t");
+  Serial.println(getDefaultMacAddress());
+
+  Serial.print("WiFi Station (using 'esp_read_mac')\t\t\t");
+  Serial.println(getInterfaceMacAddress(ESP_MAC_WIFI_STA));
+
+  Serial.print("WiFi Soft-AP (using 'esp_read_mac')\t\t\t");
+  Serial.println(getInterfaceMacAddress(ESP_MAC_WIFI_SOFTAP));
+
+  Serial.print("Bluetooth (using 'esp_read_mac')\t\t\t");
+  Serial.println(getInterfaceMacAddress(ESP_MAC_BT));
+
+  Serial.print("Ethernet (using 'esp_read_mac')\t\t\t\t");
+  Serial.println(getInterfaceMacAddress(ESP_MAC_ETH));
+}
+
+void loop() { /* Nothing in loop */ }
+
+String getDefaultMacAddress() {
+
+  String mac = "";
+
+  unsigned char mac_base[6] = {0};
+
+  if (esp_efuse_mac_get_default(mac_base) == ESP_OK) {
+    char buffer[18];  // 6*2 characters for hex + 5 characters for colons + 1 character for null terminator
+    sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X", mac_base[0], mac_base[1], mac_base[2], mac_base[3], mac_base[4], mac_base[5]);
+    mac = buffer;
+  }
+
+  return mac;
+}
+
+String getInterfaceMacAddress(esp_mac_type_t interface) {
+
+  String mac = "";
+
+  unsigned char mac_base[6] = {0};
+
+  if (esp_read_mac(mac_base, interface) == ESP_OK) {
+    char buffer[18];  // 6*2 characters for hex + 5 characters for colons + 1 character for null terminator
+    sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X", mac_base[0], mac_base[1], mac_base[2], mac_base[3], mac_base[4], mac_base[5]);
+    mac = buffer;
+  }
+
+  return mac;
+}
diff --git a/libraries/ESP32/examples/RMT/Legacy_RMT_Driver_Compatible/Legacy_RMT_Driver_Compatible.ino b/libraries/ESP32/examples/RMT/Legacy_RMT_Driver_Compatible/Legacy_RMT_Driver_Compatible.ino
new file mode 100644
index 00000000000..b42fe15f0cd
--- /dev/null
+++ b/libraries/ESP32/examples/RMT/Legacy_RMT_Driver_Compatible/Legacy_RMT_Driver_Compatible.ino
@@ -0,0 +1,37 @@
+/*
+ * This example demonstrates how to use the file build_opt.h to disable the new RMT Driver
+ * Note that this file shall be added the Arduino project
+ *
+ * If the content of this file changes, it is necessary to delete the compiled Arduino IDE cache
+ * It can be done by changing, for instance, the "Core Debug Level" option, forcing the system to rebuild the Arduino Core
+ *
+ */
+
+#ifndef ESP32_ARDUINO_NO_RGB_BUILTIN
+
+// add the file "build_opt.h" to your Arduino project folder with "-DESP32_ARDUINO_NO_RGB_BUILTIN" to use the RMT Legacy driver
+#error "ESP32_ARDUINO_NO_RGB_BUILTIN is not defined, this example is intended to demonstrate the RMT Legacy driver."
+#error "Please add the file 'build_opt.h' with '-DESP32_ARDUINO_NO_RGB_BUILTIN' to your Arduino project folder."
+
+#else
+
+// add the file "build_opt.h" to your Arduino project folder with "-DESP32_ARDUINO_NO_RGB_BUILTIN" to use the RMT Legacy driver
+// rgbLedWrite() is a function that writes to the RGB LED and it won't be available here
+#include "driver/rmt.h"
+
+bool installed = false;
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("This sketch is using the RMT Legacy driver.");
+  installed = rmt_driver_install(RMT_CHANNEL_0, 0, 0) == ESP_OK;
+}
+
+void loop() {
+  String msg = "RMT Legacy driver is installed: ";
+  msg += (char *)(installed ? "Yes." : "No.");
+  Serial.println(msg);
+  delay(5000);
+}
+
+#endif  // ESP32_ARDUINO_NO_RGB_BUILTIN
diff --git a/libraries/ESP32/examples/RMT/Legacy_RMT_Driver_Compatible/build_opt.h b/libraries/ESP32/examples/RMT/Legacy_RMT_Driver_Compatible/build_opt.h
new file mode 100644
index 00000000000..583b42d9880
--- /dev/null
+++ b/libraries/ESP32/examples/RMT/Legacy_RMT_Driver_Compatible/build_opt.h
@@ -0,0 +1 @@
+-DESP32_ARDUINO_NO_RGB_BUILTIN
diff --git a/libraries/ESP32/examples/RMT/RMTCallback/RMTCallback.ino b/libraries/ESP32/examples/RMT/RMTCallback/RMTCallback.ino
index 6a4c63bc7e5..5e65a5eabcd 100644
--- a/libraries/ESP32/examples/RMT/RMTCallback/RMTCallback.ino
+++ b/libraries/ESP32/examples/RMT/RMTCallback/RMTCallback.ino
@@ -1,64 +1,98 @@
-#include "Arduino.h"
-#include "esp32-hal.h"
+// Copyright 2023 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
 
-extern "C" void receive_trampoline(uint32_t *data, size_t len, void * arg);
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrate how to use a C++ Class to read several GPIO RMT signals
+ * calling a data processor when data is available in background, using tasks.
+ *
+ * The output is the last RMT data read in the GPIO, just to illustrate how it works.
+ *
+ */
 
 class MyProcessor {
-  private:
-    rmt_obj_t* rmt_recv = NULL;
-    float realNanoTick;
-    uint32_t buff; // rolling buffer of most recent 32 bits.
-    int at = 0;
+private:
+  uint32_t buff;  // rolling buffer of most recent 32 bits.
+  int at = 0;
+  size_t rx_num_symbols = RMT_MEM_NUM_BLOCKS_1 * RMT_SYMBOLS_PER_CHANNEL_BLOCK;
+  rmt_data_t rx_symbols[RMT_MEM_NUM_BLOCKS_1 * RMT_SYMBOLS_PER_CHANNEL_BLOCK];
 
-  public:
-    MyProcessor(uint8_t pin, float nanoTicks) {
-      assert((rmt_recv = rmtInit(21, false, RMT_MEM_192)));
+public:
+  int8_t gpio = -1;
 
-      realNanoTick = rmtSetTick(rmt_recv, nanoTicks);
-    };
-    void begin() {
-      rmtRead(rmt_recv, receive_trampoline, this);
-    };
+  MyProcessor(uint8_t pin, uint32_t rmtFreqHz) {
+    if (!rmtInit(pin, RMT_RX_MODE, RMT_MEM_NUM_BLOCKS_1, rmtFreqHz)) {
+      Serial.println("init receiver failed\n");
+      return;
+    }
+    gpio = pin;
+  }
 
-    void process(rmt_data_t *data, size_t len) {
-      for (int i = 0; len; len--) {
-        if (data[i].duration0 == 0)
-          break;
-        buff = (buff << 1) | (data[i].level0 ? 1 : 0);
-        i++;
+  void begin() {
+    // Creating RMT RX Callback Task
+    xTaskCreate(readTask, "MyProcessor", 2048, this, 4, NULL);
+  }
 
-        if (data[i].duration1 == 0)
-          break;
-        buff = (buff << 1) | (data[i].level1 ? 1 : 0);
-        i++;
-      };
-    };
-    uint32_t val() {
-      return buff;
+  static void readTask(void *args) {
+    MyProcessor *me = (MyProcessor *)args;
+
+    while (1) {
+      // blocks until RMT has read data
+      rmtRead(me->gpio, me->rx_symbols, &me->rx_num_symbols, RMT_WAIT_FOR_EVER);
+      // process the data like a callback whenever there is data available
+      process(me->rx_symbols, me->rx_num_symbols, me);
     }
-};
+    vTaskDelete(NULL);
+  }
 
-void receive_trampoline(uint32_t *data, size_t len, void * arg)
-{
-  MyProcessor * p = (MyProcessor *)arg;
-  p->process((rmt_data_t*) data, len);
-}
+  static void process(rmt_data_t *data, size_t len, void *args) {
+    MyProcessor *me = (MyProcessor *)args;
+    uint32_t *buff = &me->buff;
+
+    for (int i = 0; len; len--) {
+      if (data[i].duration0 == 0) {
+        break;
+      }
+      *buff = (*buff << 1) | (data[i].level0 ? 1 : 0);
+      i++;
+
+      if (data[i].duration1 == 0) {
+        break;
+      }
+      *buff = (*buff << 1) | (data[i].level1 ? 1 : 0);
+      i++;
+    };
+  }
+
+  uint32_t val() {
+    return buff;
+  }
+};
 
 // Attach 3 processors to GPIO 4, 5 and 10 with different tick/speeds.
-MyProcessor mp1 = MyProcessor(4, 1000);
-MyProcessor mp2 = MyProcessor(5, 1000);
-MyProcessor mp3 = MyProcessor(10, 500);
+MyProcessor mp1 = MyProcessor(4, 1000000);
+MyProcessor mp2 = MyProcessor(5, 1000000);
+MyProcessor mp3 = MyProcessor(10, 2000000);
 
-void setup()
-{
+void setup() {
   Serial.begin(115200);
   mp1.begin();
   mp2.begin();
   mp3.begin();
 }
 
-void loop()
-{
-  Serial.printf("GPIO 4: %08x 5: %08x 6: %08x\n", mp1.val(), mp2.val(), mp3.val());
+void loop() {
+  // The reading values will come from the 3 tasks started by setup()
+  Serial.printf("GPIO %d: %08lx | %d: %08lx | %d: %08lx\n", mp1.gpio, mp1.val(), mp2.gpio, mp2.val(), mp3.gpio, mp3.val());
   delay(500);
 }
diff --git a/libraries/ESP32/examples/RMT/RMTLoopback/RMTLoopback.ino b/libraries/ESP32/examples/RMT/RMTLoopback/RMTLoopback.ino
index 248aad3fa36..5d0406aee0e 100644
--- a/libraries/ESP32/examples/RMT/RMTLoopback/RMTLoopback.ino
+++ b/libraries/ESP32/examples/RMT/RMTLoopback/RMTLoopback.ino
@@ -1,62 +1,109 @@
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/event_groups.h"
-#include "Arduino.h"
+// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
 
-#include "esp32-hal.h"
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates usage of RMT for testing a circuit loopback
+ * using 2 GPIOs, one for sending RMT data and the other for receiving the data.
+ * Those 2 GPIO must be connected to each other.
+ *
+ * The output is the RMT data comparing what was sent and received
+ *
+ */
+
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+// ESP32 C3 has only 2 channels for RX and 2 for TX, thus MAX RMT_MEM is 128
+#define RMT_TX_PIN 4
+#define RMT_RX_PIN 5
+#define RMT_MEM_RX RMT_MEM_NUM_BLOCKS_2
+#else
+#define RMT_TX_PIN 18
+#define RMT_RX_PIN 21
+#define RMT_MEM_RX RMT_MEM_NUM_BLOCKS_3
+#endif
 
 rmt_data_t my_data[256];
 rmt_data_t data[256];
 
-rmt_obj_t* rmt_send = NULL;
-rmt_obj_t* rmt_recv = NULL;
+#define RMT_FREQ               10000000  // tick time is 100ns
+#define RMT_NUM_EXCHANGED_DATA 32
 
-static EventGroupHandle_t events;
+void setup() {
+  Serial.begin(115200);
 
-void setup() 
-{
-    Serial.begin(115200);
-    events = xEventGroupCreate();
-    
-    if ((rmt_send = rmtInit(18, true, RMT_MEM_64)) == NULL)
-    {
-        Serial.println("init sender failed\n");
-    }
-    if ((rmt_recv = rmtInit(21, false, RMT_MEM_192)) == NULL)
-    {
-        Serial.println("init receiver failed\n");
-    }
+  if (!rmtInit(RMT_TX_PIN, RMT_TX_MODE, RMT_MEM_NUM_BLOCKS_1, RMT_FREQ)) {
+    Serial.println("init sender failed\n");
+  }
+  if (!rmtInit(RMT_RX_PIN, RMT_RX_MODE, RMT_MEM_RX, RMT_FREQ)) {
+    Serial.println("init receiver failed\n");
+  }
+  Serial.println();
+  Serial.println("RMT tick set to: 100ns");
 
-    float realTick = rmtSetTick(rmt_send, 100);
-    printf("real tick set to: %fns\n", realTick);
+  // End of transmission shall be detected when line is idle for 2us = 20*100ns
+  rmtSetRxMaxThreshold(RMT_RX_PIN, 20);
+  // Disable Glitch  filter
+  rmtSetRxMinThreshold(RMT_RX_PIN, 0);
 
-}
+  // create multiple pulses with different width to be sent
+  for (int i = 0; i < 255; i++) {
+    data[i].level0 = 1;                     // HIGH
+    data[i].duration0 = 1 + 13 - (i % 13);  // number of Tick on High
+    data[i].level1 = 0;                     // LOW
+    data[i].duration1 = 1 + (i % 13);       // number of Ticks on Low
+    my_data[i].val = 0;
+  }
+  data[255].val = 0;
+  Serial.println();
+  Serial.println("====================================================================================================");
+  Serial.println("Preloaded Data that will sent (time in 0.1us):");
+  // Printout the received data plus the original values
+  for (int i = 0; i < RMT_NUM_EXCHANGED_DATA; i++) {
+    Serial.printf("%08lx=[%c 0x%02x|%c 0x%02x] ", data[i].val, data[i].level0 ? 'H' : 'L', data[i].duration0, data[i].level1 ? 'H' : 'L', data[i].duration1);
 
-void loop() 
-{
-    // Init data
-    int i;
-    for (i=0; i<255; i++) {
-        data[i].val = 0x80010001 + ((i%13)<<16) + 13-(i%13);
+    if (!((i + 1) % 4)) {
+      Serial.println();
     }
-    data[255].val = 0;
+  }
+  Serial.println("====================================================================================================");
+  Serial.printf("Please connect GPIO %d to GPIO %d, now.", RMT_TX_PIN, RMT_RX_PIN);
+  Serial.println();
+  Serial.println();
+}
+
+void loop() {
+  // Start an async data read
+  size_t rx_num_symbols = RMT_NUM_EXCHANGED_DATA;
+  rmtReadAsync(RMT_RX_PIN, my_data, &rx_num_symbols);
 
-    // Start receiving
-    rmtReadAsync(rmt_recv, my_data, 100, events, false, 0);
+  // Write blocking the data to the loopback
+  rmtWrite(RMT_TX_PIN, data, RMT_NUM_EXCHANGED_DATA, RMT_WAIT_FOR_EVER);
 
-    // Send in continous mode
-    rmtWrite(rmt_send, data, 100);
+  // Wait until data is read
+  while (!rmtReceiveCompleted(RMT_RX_PIN));
 
-    // Wait for data
-    xEventGroupWaitBits(events, RMT_FLAG_RX_DONE, 1, 1, portMAX_DELAY);
+  // Once data is available, the number of RMT Symbols is stored in rx_num_symbols
+  // and the received data is copied to my_data
+  Serial.printf("Got %d RMT symbols\n", rx_num_symbols);
 
-    // Printout the received data plus the original values
-    for (i=0; i<60; i++)
-    {
-        Serial.printf("%08x=%08x ", my_data[i].val, data[i].val );
-        if (!((i+1)%4)) Serial.println("\n");
+  // Printout the received data plus the original values
+  for (int i = 0; i < RMT_NUM_EXCHANGED_DATA; i++) {
+    Serial.printf("%08lx=%08lx ", my_data[i].val, data[i].val);
+    if (!((i + 1) % 4)) {
+      Serial.println();
     }
-    Serial.println("\n");
+  }
+  Serial.println();
 
-    delay(2000);
+  delay(2000);
 }
diff --git a/libraries/ESP32/examples/RMT/RMTReadXJT/RMTReadXJT.ino b/libraries/ESP32/examples/RMT/RMTReadXJT/RMTReadXJT.ino
index 39978d26dab..762225bcdf5 100644
--- a/libraries/ESP32/examples/RMT/RMTReadXJT/RMTReadXJT.ino
+++ b/libraries/ESP32/examples/RMT/RMTReadXJT/RMTReadXJT.ino
@@ -1,13 +1,27 @@
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/event_groups.h"
-#include "Arduino.h"
+// Copyright 2023 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
 
-#include "esp32-hal.h"
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates usage of RMT for receiving XJT D16 data
+ *
+ * The output is the RMT data read and processed
+ *
+ */
 
 //
-// Note: This example uses a FrSKY device communication 
-//          using XJT D12 protocol 
+// Note: This example uses a FrSKY device communication
+//          using XJT D16 protocol
 //
 // ; 0 bit = 6us low/10us high
 // ; 1 bit = 14us low/10us high
@@ -24,7 +38,7 @@
 // ;         |       16us       |            24us            |
 
 //  Typedef of received frame
-//  
+//
 // ; 0x00 - Sync, 0x7E (sync header ID)
 // ; 0x01 - Rx ID, 0x?? (receiver ID number, 0x00-0x??)
 // ; 0x02 - Flags 1, 0x?? (used for failsafe and binding)
@@ -38,166 +52,166 @@
 // ; 0x12 - CRC-16 Low
 // ; 0x13 - Tail, 0x7E (tail ID)
 typedef union {
-        struct {
-                uint8_t head;//0x7E
-                uint8_t rxid;//Receiver Number
-                uint8_t flags;//Range:0x20, Bind:0x01
-                uint8_t reserved0;//0x00
-                union {
-                        struct {
-                                uint8_t ch0_l;
-                                uint8_t ch0_h:4;
-                                uint8_t ch1_l:4;
-                                uint8_t ch1_h;
-                        };
-                        uint8_t bytes[3];
-                } channels[4];
-                uint8_t reserved1;//0x00
-                uint8_t crc_h;
-                uint8_t crc_l;
-                uint8_t tail;//0x7E
-        };
-        uint8_t buffer[20];
+  struct {
+    uint8_t head;       //0x7E
+    uint8_t rxid;       //Receiver Number
+    uint8_t flags;      //Range:0x20, Bind:0x01
+    uint8_t reserved0;  //0x00
+    union {
+      struct {
+        uint8_t ch0_l;
+        uint8_t ch0_h : 4;
+        uint8_t ch1_l : 4;
+        uint8_t ch1_h;
+      };
+      uint8_t bytes[3];
+    } channels[4];
+    uint8_t reserved1;  //0x00
+    uint8_t crc_h;
+    uint8_t crc_l;
+    uint8_t tail;  //0x7E
+  };
+  uint8_t buffer[20];
 } xjt_packet_t;
 
 #define XJT_VALID(i) (i->level0 && !i->level1 && i->duration0 >= 8 && i->duration0 <= 11)
 
-rmt_obj_t* rmt_recv = NULL;
-
 static uint32_t *s_channels;
 static uint32_t channels[16];
 static uint8_t xjt_flags = 0x0;
 static uint8_t xjt_rxid = 0x0;
 
-static bool xjtReceiveBit(size_t index, bool bit){
-    static xjt_packet_t xjt;
-    static uint8_t xjt_bit_index = 8;
-    static uint8_t xht_byte_index = 0;
-    static uint8_t xht_ones = 0;
-
-    if(!index){
-        xjt_bit_index = 8;
-        xht_byte_index = 0;
-        xht_ones = 0;
+static bool xjtReceiveBit(size_t index, bool bit) {
+  static xjt_packet_t xjt;
+  static uint8_t xjt_bit_index = 8;
+  static uint8_t xht_byte_index = 0;
+  static uint8_t xht_ones = 0;
+
+  if (!index) {
+    xjt_bit_index = 8;
+    xht_byte_index = 0;
+    xht_ones = 0;
+  }
+
+  if (xht_byte_index > 19) {
+    //fail!
+    return false;
+  }
+  if (bit) {
+    xht_ones++;
+    if (xht_ones > 5 && xht_byte_index && xht_byte_index < 19) {
+      //fail!
+      return false;
     }
-
-    if(xht_byte_index > 19){
+    //add bit
+    xjt.buffer[xht_byte_index] |= (1 << --xjt_bit_index);
+  } else if (xht_ones == 5 && xht_byte_index && xht_byte_index < 19) {
+    xht_ones = 0;
+    //skip bit
+    return true;
+  } else {
+    xht_ones = 0;
+    //add bit
+    xjt.buffer[xht_byte_index] &= ~(1 << --xjt_bit_index);
+  }
+  if ((!xjt_bit_index) || (xjt_bit_index == 1 && xht_byte_index == 19)) {
+    xjt_bit_index = 8;
+    if (!xht_byte_index && xjt.buffer[0] != 0x7E) {
+      //fail!
+      return false;
+    }
+    xht_byte_index++;
+    if (xht_byte_index == 20) {
+      //done
+      if (xjt.buffer[19] != 0x7E) {
         //fail!
         return false;
-    }
-    if(bit){
-        xht_ones++;
-        if(xht_ones > 5 && xht_byte_index && xht_byte_index < 19){
-            //fail!
-            return false;
-        }
-        //add bit
-        xjt.buffer[xht_byte_index] |= (1 << --xjt_bit_index);
-    } else if(xht_ones == 5 && xht_byte_index && xht_byte_index < 19){
-        xht_ones = 0;
-        //skip bit
-        return true;
-    } else {
-        xht_ones = 0;
-        //add bit
-        xjt.buffer[xht_byte_index] &= ~(1 << --xjt_bit_index);
-    }
-    if ((!xjt_bit_index) || (xjt_bit_index==1 && xht_byte_index==19) ) {
-        xjt_bit_index = 8;
-        if(!xht_byte_index && xjt.buffer[0] != 0x7E){
-            //fail!
-            return false;
+      }
+      //check crc?
+
+      xjt_flags = xjt.flags;
+      xjt_rxid = xjt.rxid;
+      for (int i = 0; i < 4; i++) {
+        uint16_t ch0 = xjt.channels[i].ch0_l | ((uint16_t)(xjt.channels[i].ch0_h & 0x7) << 8);
+        ch0 = ((ch0 * 2) + 2452) / 3;
+        uint16_t ch1 = xjt.channels[i].ch1_l | ((uint16_t)(xjt.channels[i].ch1_h & 0x7F) << 4);
+        ch1 = ((ch1 * 2) + 2452) / 3;
+        uint8_t c0n = i * 2;
+        if (xjt.channels[i].ch0_h & 0x8) {
+          c0n += 8;
         }
-        xht_byte_index++;
-        if(xht_byte_index == 20){
-            //done
-            if(xjt.buffer[19] != 0x7E){
-                //fail!
-                return false;
-            }
-            //check crc?
-
-            xjt_flags = xjt.flags;
-            xjt_rxid = xjt.rxid;
-            for(int i=0; i<4; i++){
-                uint16_t ch0 = xjt.channels[i].ch0_l | ((uint16_t)(xjt.channels[i].ch0_h & 0x7) << 8);
-                ch0 = ((ch0 * 2) + 2452) / 3;
-                uint16_t ch1 = xjt.channels[i].ch1_l | ((uint16_t)(xjt.channels[i].ch1_h & 0x7F) << 4);
-                ch1 = ((ch1 * 2) + 2452) / 3;
-                uint8_t c0n = i*2;
-                if(xjt.channels[i].ch0_h & 0x8){
-                    c0n += 8;
-                }
-                uint8_t c1n = i*2+1;
-                if(xjt.channels[i].ch1_h & 0x80){
-                    c1n += 8;
-                }
-                s_channels[c0n] = ch0;
-                s_channels[c1n] = ch1;
-            }
+        uint8_t c1n = i * 2 + 1;
+        if (xjt.channels[i].ch1_h & 0x80) {
+          c1n += 8;
         }
+        s_channels[c0n] = ch0;
+        s_channels[c1n] = ch1;
+      }
     }
-    return true;
+  }
+  return true;
 }
 
-void parseRmt(rmt_data_t* items, size_t len, uint32_t* channels){
-    bool valid = true;
-    rmt_data_t* it = NULL;
+void parseRmt(rmt_data_t *items, size_t len, uint32_t *channels) {
+  bool valid = true;
+  rmt_data_t *it = NULL;
 
-    if (!channels)  {
-        log_e("Please provide data block for storing channel info");
-        return;
-    }
-    s_channels = channels;
+  if (!channels) {
+    log_e("Please provide data block for storing channel info");
+    return;
+  }
+  s_channels = channels;
 
-    it = &items[0];
-    for(size_t i = 0; i<len; i++){
+  it = &items[0];
+  for (size_t i = 0; i < len; i++) {
 
-        if(!valid){
-            break;
-        }
-        it = &items[i];
-        if(XJT_VALID(it)){
-            if(it->duration1 >= 5 && it->duration1 <= 8){
-                valid = xjtReceiveBit(i, false);
-            } else if(it->duration1 >= 13 && it->duration1 <= 16){
-                valid = xjtReceiveBit(i, true);
-            } else {
-                valid = false;
-            }
-        } else if(!it->duration1 && !it->level1 && it->duration0 >= 5 && it->duration0 <= 8) {
-                    valid = xjtReceiveBit(i, false);
-
-        }
+    if (!valid) {
+      break;
     }
-}
-
-extern "C" void receive_data(uint32_t *data, size_t len, void * arg)
-{
-    parseRmt((rmt_data_t*) data, len, channels);
-}
-
-void setup() 
-{
-    Serial.begin(115200);
-    
-    // Initialize the channel to capture up to 192 items
-    if ((rmt_recv = rmtInit(21, false, RMT_MEM_192)) == NULL)
-    {
-        Serial.println("init receiver failed\n");
+    it = &items[i];
+    if (XJT_VALID(it)) {
+      if (it->duration1 >= 5 && it->duration1 <= 8) {
+        valid = xjtReceiveBit(i, false);
+      } else if (it->duration1 >= 13 && it->duration1 <= 16) {
+        valid = xjtReceiveBit(i, true);
+      } else {
+        valid = false;
+      }
+    } else if (!it->duration1 && !it->level1 && it->duration0 >= 5 && it->duration0 <= 8) {
+      valid = xjtReceiveBit(i, false);
     }
+  }
+}
 
-    // Setup 1us tick
-    float realTick = rmtSetTick(rmt_recv, 1000);
-    Serial.printf("real tick set to: %fns\n", realTick);
+// Change the RMT reading GPIO here:
+#define RMT_GPIO 21
 
-    // Ask to start reading
-    rmtRead(rmt_recv, receive_data, NULL);
+void setup() {
+  Serial.begin(115200);
+  // Initialize the channel to capture up to 64*2 or 48*2 items - 1us tick
+  if (!rmtInit(RMT_GPIO, RMT_RX_MODE, RMT_MEM_NUM_BLOCKS_2, 1000000)) {
+    Serial.println("init receiver failed\n");
+  }
+  Serial.println("real tick set to: 1us");
 }
 
-void loop() 
-{
-    // printout some of the channels
-    Serial.printf("%04x %04x %04x %04x\n", channels[0], channels[1], channels[2], channels[3]);
-    delay(500);
+void loop() {
+  static rmt_data_t data[RMT_MEM_NUM_BLOCKS_2 * RMT_SYMBOLS_PER_CHANNEL_BLOCK];
+  static size_t data_symbols = RMT_MEM_NUM_BLOCKS_2 * RMT_SYMBOLS_PER_CHANNEL_BLOCK;
+
+  // Blocking read with timeout of 500ms
+  // If data is read, data_symbols will have the number of RMT symbols effectively read
+  // to check if something was read and it didn't just timeout, use rmtReceiveCompleted()
+  rmtRead(RMT_GPIO, data, &data_symbols, 500);
+
+  // If read something, process the data
+  if (rmtReceiveCompleted(RMT_GPIO)) {
+    Serial.printf("Got %d RMT Symbols. Parsing data...\n", data_symbols);
+    parseRmt(data, data_symbols, channels);
+  } else {
+    Serial.println("No RMT data read...");
+  }
+
+  // printout some of the channels every 500ms
+  Serial.printf("%04lx %04lx %04lx %04lx\n", channels[0], channels[1], channels[2], channels[3]);
 }
diff --git a/libraries/ESP32/examples/RMT/RMTWriteNeoPixel/RMTWriteNeoPixel.ino b/libraries/ESP32/examples/RMT/RMTWriteNeoPixel/RMTWriteNeoPixel.ino
deleted file mode 100644
index 5067140fbd6..00000000000
--- a/libraries/ESP32/examples/RMT/RMTWriteNeoPixel/RMTWriteNeoPixel.ino
+++ /dev/null
@@ -1,89 +0,0 @@
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/event_groups.h"
-#include "Arduino.h"
-
-#include "esp32-hal.h"
-
-#define NR_OF_LEDS   8*4
-#define NR_OF_ALL_BITS 24*NR_OF_LEDS
-
-//
-// Note: This example uses Neopixel LED board, 32 LEDs chained one
-//      after another, each RGB LED has its 24 bit value 
-//      for color configuration (8b for each color)
-//
-//      Bits encoded as pulses as follows:
-//
-//      "0":
-//         +-------+              +--
-//         |       |              |
-//         |       |              |
-//         |       |              |
-//      ---|       |--------------|
-//         +       +              +
-//         | 0.4us |   0.85 0us   |
-//
-//      "1":
-//         +-------------+       +--
-//         |             |       |
-//         |             |       |
-//         |             |       |
-//         |             |       |
-//      ---+             +-------+
-//         |    0.8us    | 0.4us |
-
-rmt_data_t led_data[NR_OF_ALL_BITS];
-
-rmt_obj_t* rmt_send = NULL;
-
-void setup() 
-{
-    Serial.begin(115200);
-    
-    if ((rmt_send = rmtInit(18, true, RMT_MEM_64)) == NULL)
-    {
-        Serial.println("init sender failed\n");
-    }
-
-    float realTick = rmtSetTick(rmt_send, 100);
-    Serial.printf("real tick set to: %fns\n", realTick);
-
-}
-
-int color[] =  { 0x55, 0x11, 0x77 };  // RGB value
-int led_index = 0;
-
-void loop() 
-{
-    // Init data with only one led ON
-    int led, col, bit;
-    int i=0;
-    for (led=0; led<NR_OF_LEDS; led++) {
-        for (col=0; col<3; col++ ) {
-            for (bit=0; bit<8; bit++){
-                if ( (color[col] & (1<<(7-bit))) && (led == led_index) ) {
-                    led_data[i].level0 = 1;
-                    led_data[i].duration0 = 8;
-                    led_data[i].level1 = 0;
-                    led_data[i].duration1 = 4;
-                } else {
-                    led_data[i].level0 = 1;
-                    led_data[i].duration0 = 4;
-                    led_data[i].level1 = 0;
-                    led_data[i].duration1 = 8;
-                }
-                i++;
-            }
-        }
-    }
-    // make the led travel in the pannel
-    if ((++led_index)>=NR_OF_LEDS) {
-        led_index = 0;
-    }
-
-    // Send the data
-    rmtWrite(rmt_send, led_data, NR_OF_ALL_BITS);
-
-    delay(100);
-}
diff --git a/libraries/ESP32/examples/RMT/RMTWrite_RGB_LED/RMTWrite_RGB_LED.ino b/libraries/ESP32/examples/RMT/RMTWrite_RGB_LED/RMTWrite_RGB_LED.ino
new file mode 100644
index 00000000000..74f0ac4f6b1
--- /dev/null
+++ b/libraries/ESP32/examples/RMT/RMTWrite_RGB_LED/RMTWrite_RGB_LED.ino
@@ -0,0 +1,99 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates usage of RGB LED driven by RMT
+ *
+ * The output is a visual WS2812 RGB LED color moving in a 8 x 4 LED matrix
+ * Parameters can be changed by the user. In a single LED circuit, it will just blink.
+ */
+
+// The effect seen in (Espressif devkits) ESP32C6, ESP32H2, ESP32C3, ESP32S2 and ESP32S3 is like a Blink of RGB LED
+#ifdef PIN_LED_RGB
+#define BUILTIN_RGBLED_PIN PIN_LED_RGB
+#else
+#define BUILTIN_RGBLED_PIN 21  // ESP32 has no builtin RGB LED (PIN_LED_RGB)
+#endif
+
+#define NR_OF_LEDS     8 * 4
+#define NR_OF_ALL_BITS 24 * NR_OF_LEDS
+
+//
+// Note: This example uses a board with 32 WS2812b LEDs chained one
+//      after another, each RGB LED has its 24 bit value
+//      for color configuration (8b for each color)
+//
+//      Bits encoded as pulses as follows:
+//
+//      "0":
+//         +-------+              +--
+//         |       |              |
+//         |       |              |
+//         |       |              |
+//      ---|       |--------------|
+//         +       +              +
+//         | 0.4us |   0.85 0us   |
+//
+//      "1":
+//         +-------------+       +--
+//         |             |       |
+//         |             |       |
+//         |             |       |
+//         |             |       |
+//      ---+             +-------+
+//         |    0.8us    | 0.4us |
+
+rmt_data_t led_data[NR_OF_ALL_BITS];
+
+void setup() {
+  Serial.begin(115200);
+  if (!rmtInit(BUILTIN_RGBLED_PIN, RMT_TX_MODE, RMT_MEM_NUM_BLOCKS_1, 10000000)) {
+    Serial.println("init sender failed\n");
+  }
+  Serial.println("real tick set to: 100ns");
+}
+
+int color[] = {0x55, 0x11, 0x77};  // Green Red Blue values
+int led_index = 0;
+
+void loop() {
+  // Init data with only one led ON
+  int led, col, bit;
+  int i = 0;
+  for (led = 0; led < NR_OF_LEDS; led++) {
+    for (col = 0; col < 3; col++) {
+      for (bit = 0; bit < 8; bit++) {
+        if ((color[col] & (1 << (7 - bit))) && (led == led_index)) {
+          led_data[i].level0 = 1;
+          led_data[i].duration0 = 8;
+          led_data[i].level1 = 0;
+          led_data[i].duration1 = 4;
+        } else {
+          led_data[i].level0 = 1;
+          led_data[i].duration0 = 4;
+          led_data[i].level1 = 0;
+          led_data[i].duration1 = 8;
+        }
+        i++;
+      }
+    }
+  }
+  // make the led travel in the panel
+  if ((++led_index) >= NR_OF_LEDS) {
+    led_index = 0;
+  }
+  // Send the data and wait until it is done
+  rmtWrite(BUILTIN_RGBLED_PIN, led_data, NR_OF_ALL_BITS, RMT_WAIT_FOR_EVER);
+  delay(100);
+}
diff --git a/libraries/ESP32/examples/RMT/RMT_CPUFreq_Test/RMT_CPUFreq_Test.ino b/libraries/ESP32/examples/RMT/RMT_CPUFreq_Test/RMT_CPUFreq_Test.ino
new file mode 100644
index 00000000000..900f0f064f3
--- /dev/null
+++ b/libraries/ESP32/examples/RMT/RMT_CPUFreq_Test/RMT_CPUFreq_Test.ino
@@ -0,0 +1,86 @@
+// Copyright 2023 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates usage of RGB LED driven by RMT to verify
+ * that RMT works on any CPU/APB Frequency.
+ *
+ * It uses an ESP32 Arduino builtin RGB NeoLED function based on RMT:
+ * void rgbLedWrite(uint8_t pin, uint8_t red_val, uint8_t green_val, uint8_t blue_val)
+ *
+ * The output is a visual WS2812 RGB LED color change routine using each time a
+ * different CPU Frequency, just to illustrate how it works. Serial output indicates
+ * information about the CPU Frequency while controlling the RGB LED using RMT.
+ */
+
+// Default DevKit RGB LED GPIOs:
+// The effect seen in (Espressif devkits) ESP32C6, ESP32H2, ESP32C3, ESP32S2 and ESP32S3 is like a Blink of RGB LED
+#ifdef PIN_RGB_LED
+#define MY_LED_GPIO PIN_RGB_LED
+#else
+#define MY_LED_GPIO 21  // ESP32 has no builtin RGB LED (PIN_RGB_LED)
+#endif
+
+// Set the correct GPIO to any necessary by changing RGB_LED_GPIO value
+#define RGB_LED_GPIO MY_LED_GPIO  // Any GPIO valid in the board
+
+// Change the RGB Brightness to any value from 0 (off) to 255 (max)
+#define BRIGHTNESS 20  // Change color brightness (max 255)
+
+void setup() {
+  Serial.begin(115200);
+  delay(500);
+  Serial.printf("\nUsing GPIO %d attached to the RGB LED.\nInitial CPU setup:\n", RGB_LED_GPIO);
+
+  Serial.printf("CPU Freq = %lu MHz\n", getCpuFrequencyMhz());
+  Serial.printf("XTAL Freq = %lu MHz\n", getXtalFrequencyMhz());
+  Serial.printf("APB Freq = %lu Hz\n", getApbFrequency());
+}
+
+void loop() {
+  const uint8_t cpufreqs[] = {240, 160, 80, 40, 20, 10};
+  static uint8_t i = 0;
+
+  setCpuFrequencyMhz(cpufreqs[i]);
+  // moves to the next CPU freq for the next loop
+  i = (i + 1) % sizeof(cpufreqs);
+
+  // Changing the CPU Freq demands RMT to reset internals parameters setting it correctly
+  // This is fixed by reinitializing the RMT peripheral as done below
+  // 100ns RMT Tick for driving the NeoLED as in the code of esp32-hal-rgb-led.c (github)
+  rmtInit(RGB_LED_GPIO, RMT_TX_MODE, RMT_MEM_NUM_BLOCKS_1, 10000000);
+
+  // resets also UART to adapt to the new CPU Freq
+  Serial.updateBaudRate(115200);
+  Serial.printf("\n--changed CPU Frequency to %lu MHz\n", getCpuFrequencyMhz());
+
+  rgbLedWrite(RGB_LED_GPIO, BRIGHTNESS, BRIGHTNESS, BRIGHTNESS);  // White
+  Serial.println("White");
+  delay(1000);
+  rgbLedWrite(RGB_LED_GPIO, 0, 0, 0);  // Off
+  Serial.println("Off");
+  delay(1000);
+  rgbLedWrite(RGB_LED_GPIO, BRIGHTNESS, 0, 0);  // Red
+  Serial.println("Red");
+  delay(1000);
+  rgbLedWrite(RGB_LED_GPIO, 0, BRIGHTNESS, 0);  // Green
+  Serial.println("Green");
+  delay(1000);
+  rgbLedWrite(RGB_LED_GPIO, 0, 0, BRIGHTNESS);  // Blue
+  Serial.println("Blue");
+  delay(1000);
+  rgbLedWrite(RGB_LED_GPIO, 0, 0, 0);  // Off
+  Serial.println("Off");
+  delay(1000);
+}
diff --git a/libraries/ESP32/examples/RMT/RMT_EndOfTransmissionState/RMT_EndOfTransmissionState.ino b/libraries/ESP32/examples/RMT/RMT_EndOfTransmissionState/RMT_EndOfTransmissionState.ino
new file mode 100644
index 00000000000..9497e07d08f
--- /dev/null
+++ b/libraries/ESP32/examples/RMT/RMT_EndOfTransmissionState/RMT_EndOfTransmissionState.ino
@@ -0,0 +1,139 @@
+#define BLINK_GPIO                2
+#define EOT_INITIAL_STATE_TIME_MS 1000
+
+// BLINK_GPIO shall start at RMT_EOT (HIGH or LOW) as initial state for EOT_INITIAL_STATE_TIME_MS,
+// BLINK: 1 second ON, 1 second OFF and then return/stay to RMT_EOT level at the end.
+#define RMT_EOT HIGH
+
+// RMT is at 400KHz with a 2.5us tick
+// This RMT data sends a 0.5Hz pulse with 1s High and 1s Low signal
+rmt_data_t blink_1s_rmt_data[] = {
+  // 400,000 x 2.5us = 1 second ON
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  // 400,000 x 2.5us = 1 second OFF
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  // Looping mode needs a Zero ending data to mark the EOF
+  {0, 0, 0, 0}
+};
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Starting Blink testing...");
+  Serial.flush();
+
+  // 1 RMT Block has 64 RMT_SYMBOLS (ESP32|ESP32S2) or 48 RMT_SYMBOLS (ESP32C3|ESP32S3)
+  if (!rmtInit(BLINK_GPIO, RMT_TX_MODE, RMT_MEM_NUM_BLOCKS_1, 400000)) {  //2.5us tick
+    Serial.println("===> rmtInit Error!");
+  }
+
+  // sets the End of Transmission Level to HIGH, after writing to the pin. DEFAULT is LOW.
+  rmtSetEOT(BLINK_GPIO, RMT_EOT);
+  // set initial RMT state by writing a single RMT data
+  rmt_data_t initStateSetup_rmt_data[] = {{1, RMT_EOT, 0, 0}};
+  rmtWrite(BLINK_GPIO, initStateSetup_rmt_data, RMT_SYMBOLS_OF(initStateSetup_rmt_data), RMT_WAIT_FOR_EVER);
+  Serial.printf("\nLED GPIO%d start in the initial level %s\n", BLINK_GPIO, RMT_EOT == LOW ? "LOW" : "HIGH");
+  delay(EOT_INITIAL_STATE_TIME_MS);  // set initial state of the LED is set by RMT_EOT.
+
+  // Send the data and wait until it is done - set EOT level to HIGH
+  Serial.printf("\nLED GPIO%d Blinks 1 second HIGH - 1 second LOW.\n", BLINK_GPIO);
+  if (!rmtWrite(BLINK_GPIO, blink_1s_rmt_data, RMT_SYMBOLS_OF(blink_1s_rmt_data) - 2, RMT_WAIT_FOR_EVER)) {
+    Serial.println("===> rmtWrite Blink 1s Error!");
+  }
+  Serial.printf("\nLED GPIO%d goes to the EOT level %s\n", BLINK_GPIO, RMT_EOT == LOW ? "LOW" : "HIGH");
+}
+
+void loop() {}
diff --git a/libraries/ESP32/examples/RMT/RMT_LED_Blink/RMT_LED_Blink.ino b/libraries/ESP32/examples/RMT/RMT_LED_Blink/RMT_LED_Blink.ino
new file mode 100644
index 00000000000..8c2b8db3cd1
--- /dev/null
+++ b/libraries/ESP32/examples/RMT/RMT_LED_Blink/RMT_LED_Blink.ino
@@ -0,0 +1,360 @@
+// Copyright 2023 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrate how to use RMT to just blink a regular LED (GPIO)
+ * It uses all the different RMT Writing APIs to blink the LED by hardware, not being
+ * necessary the regular Blink code in Arduino.
+ *
+ * The output is the Blinking LED in the GPIO and a serial output describing what is
+ * going on, along the execution.
+ *
+ * The circuit is just a LED and a resistor of 270 ohms connected to the GPIO
+ * GPIO ---> resistor 270 ohms ---> + LED - ---> GND
+ */
+
+#define BLINK_GPIO 2
+
+// RMT is at 400KHz with a 2.5us tick
+// This RMT data sends a 0.5Hz pulse with 1s High and 1s Low signal
+rmt_data_t blink_1s_rmt_data[] = {
+  // 400,000 x 2.5us = 1 second ON
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  // 400,000 x 2.5us = 1 second OFF
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  // Looping mode needs a Zero ending data to mark the EOF
+  {0, 0, 0, 0}
+};
+
+// RMT is at 400KHz with a 2.5us tick
+// This RMT data sends a 1Hz pulse with 500ms High and 500ms Low signal
+rmt_data_t blink_500ms_rmt_data[] = {
+  // 200,000 x 2.5us = 0.5 second ON
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  // 200,000 x 2.5us = 0.5 second OFF
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  // Looping mode needs a Zero ending data to mark the EOF
+  {0, 0, 0, 0}
+};
+
+// RMT is at 400KHz with a 2.5us tick
+// This RMT data sends a 2Hz pulse with 250ms High and 250ms Low signal
+rmt_data_t blink_250ms_rmt_data[] = {
+  // 100,000 x 2.5us = 0.25 second ON
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  {
+    25000,
+    1,
+    25000,
+    1,
+  },
+  // 100,000 x 2.5us = 0.25 second OFF
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  {
+    25000,
+    0,
+    25000,
+    0,
+  },
+  // Looping mode needs a Zero ending data to mark the EOF
+  {0, 0, 0, 0}
+};
+
+void RMT_Mixed_Write_Blink() {
+  Serial.println("===> rmtWriteLooping() to Blink the LED.");
+  Serial.println("Blinking at 1s on + 1s off :: 3 blinks");
+  if (!rmtWriteLooping(BLINK_GPIO, blink_1s_rmt_data, RMT_SYMBOLS_OF(blink_1s_rmt_data))) {
+    Serial.println("===> rmtWriteLooping Blink 1s Error!");
+  }
+  delay(6000);  // blinking happens here, done by hardware!
+
+  Serial.println("===> rmtWrite() (Blocking Mode) to Blink the LED.");
+  Serial.println("Blinking at 500ms on + 500ms off :: 4 blinks");
+  for (uint8_t i = 0; i < 4; i++) {
+    if (!rmtWrite(BLINK_GPIO, blink_500ms_rmt_data, RMT_SYMBOLS_OF(blink_500ms_rmt_data) - 2, RMT_WAIT_FOR_EVER)) {
+      Serial.println("===> rmtWrite Blink 0.5s Error!");
+    }
+  }
+
+  Serial.println("===> rmtWriteAsync() (Non-Blocking Mode) to Blink the LED.");
+  Serial.println("Blinking at 250ms on + 250ms off :: 5 blinks");
+  for (uint8_t i = 0; i < 5; i++) {
+    if (!rmtWriteAsync(BLINK_GPIO, blink_250ms_rmt_data, RMT_SYMBOLS_OF(blink_250ms_rmt_data) - 2)) {
+      Serial.println("===> rmtWrite Blink 0.25s Error!");
+    }
+    // wait (blocks) until all the data is sent out
+    while (!rmtTransmitCompleted(BLINK_GPIO));
+  }
+  Serial.println("Blinking OFF for 1 seconds");
+  delay(1000);
+}
+
+void RMT_Loop_Write_Blink() {
+  Serial.println("Using RMT Writing loop to blink an LED.");
+  Serial.println("Blinking at 1s on + 1s off :: 3 blinks");
+  if (!rmtWriteLooping(BLINK_GPIO, blink_1s_rmt_data, RMT_SYMBOLS_OF(blink_1s_rmt_data))) {
+    Serial.println("===> rmtWriteLooping Blink 1s Error!");
+  }
+  delay(6000);
+  Serial.println("Blinking at 500ms on + 500ms off :: 5 blinks");
+  if (!rmtWriteLooping(BLINK_GPIO, blink_500ms_rmt_data, RMT_SYMBOLS_OF(blink_500ms_rmt_data))) {
+    Serial.println("===> rmtWriteLooping Blink 0.5s Error!");
+  }
+  delay(5000);
+  Serial.println("Blinking at 250ms on + 250ms off :: 10 blinks");
+  if (!rmtWriteLooping(BLINK_GPIO, blink_250ms_rmt_data, RMT_SYMBOLS_OF(blink_250ms_rmt_data))) {
+    Serial.println("===> rmtWriteLooping Blink 0.25s Error!");
+  }
+  delay(5000);
+  Serial.println("Blinking OFF for 2 seconds");
+  if (!rmtWriteLooping(BLINK_GPIO, NULL, 0)) {
+    Serial.println("===> rmtWriteLooping Blink OFF Error!");
+  }
+  delay(2000);
+}
+
+void RMT_Single_Write_Blocking_Blink() {
+  Serial.println("Using RMT Writing and its Completion to blink an LED.");
+  Serial.println("Blinking at 1s on + 1s off :: 2 blinks");
+  for (uint8_t i = 0; i < 2; i++) {
+    if (!rmtWrite(BLINK_GPIO, blink_1s_rmt_data, RMT_SYMBOLS_OF(blink_1s_rmt_data) - 2, RMT_WAIT_FOR_EVER)) {
+      Serial.println("===> rmtWrite Blink 1s Error!");
+    }
+  }
+  Serial.println("Blinking at 500ms on + 500ms off :: 4 blinks");
+  for (uint8_t i = 0; i < 4; i++) {
+    if (!rmtWrite(BLINK_GPIO, blink_500ms_rmt_data, RMT_SYMBOLS_OF(blink_500ms_rmt_data) - 2, RMT_WAIT_FOR_EVER)) {
+      Serial.println("===> rmtWrite Blink 0.5s Error!");
+    }
+  }
+  Serial.println("Blinking at 250ms on + 250ms off :: 8 blinks");
+  for (uint8_t i = 0; i < 8; i++) {
+    if (!rmtWrite(BLINK_GPIO, blink_250ms_rmt_data, RMT_SYMBOLS_OF(blink_250ms_rmt_data) - 2, RMT_WAIT_FOR_EVER)) {
+      Serial.println("===> rmtWrite Blink 0.25s Error!");
+    }
+  }
+  Serial.println("Blinking OFF for 3 seconds");
+  delay(3000);
+}
+
+void RMT_Write_Aync_Non_Blocking_Blink() {
+  Serial.println("Using RMT Async Writing and its Completion to blink an LED.");
+  Serial.println("Blinking at 1s on + 1s off :: 5 blinks");
+  for (uint8_t i = 0; i < 5; i++) {
+    if (!rmtWriteAsync(BLINK_GPIO, blink_1s_rmt_data, RMT_SYMBOLS_OF(blink_1s_rmt_data) - 2)) {
+      Serial.println("===> rmtWrite Blink 1s Error!");
+    }
+    // wait (blocks) until all the data is sent out
+    while (!rmtTransmitCompleted(BLINK_GPIO));
+  }
+  Serial.println("Blinking at 500ms on + 500ms off :: 5 blinks");
+  for (uint8_t i = 0; i < 5; i++) {
+    if (!rmtWriteAsync(BLINK_GPIO, blink_500ms_rmt_data, RMT_SYMBOLS_OF(blink_500ms_rmt_data) - 2)) {
+      Serial.println("===> rmtWrite Blink 0.5s Error!");
+    }
+    // wait (blocks) until all the data is sent out
+    while (!rmtTransmitCompleted(BLINK_GPIO));
+  }
+  Serial.println("Blinking at 250ms on + 250ms off :: 5 blinks");
+  for (uint8_t i = 0; i < 5; i++) {
+    if (!rmtWriteAsync(BLINK_GPIO, blink_250ms_rmt_data, RMT_SYMBOLS_OF(blink_250ms_rmt_data) - 2)) {
+      Serial.println("===> rmtWrite Blink 0.25s Error!");
+    }
+    // wait (blocks) until all the data is  sent out
+    while (!rmtTransmitCompleted(BLINK_GPIO));
+  }
+  Serial.println("Blinking OFF for 1 seconds");
+  delay(1000);
+}
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Starting Blink testing...");
+  Serial.flush();
+
+  // 1 RMT Block has 64 RMT_SYMBOLS (ESP32|ESP32S2) or 48 RMT_SYMBOLS (ESP32C3|ESP32S3)
+  if (!rmtInit(BLINK_GPIO, RMT_TX_MODE, RMT_MEM_NUM_BLOCKS_1, 400000)) {  //2.5us tick
+    Serial.println("===> rmtInit Error!");
+  } else {
+    Serial.println("===> rmtInit OK! Tick = 2.5us - OK for testing");
+  }
+  Serial.println("\n======================================");
+  Serial.println("All set. Starting RMT testing Routine.");
+  Serial.println("======================================\n");
+
+  RMT_Mixed_Write_Blink();
+  Serial.println("End of Mixed Calls testing");
+  delay(1000);
+
+  Serial.println("\n===============================");
+  Serial.println("Starting a Blinking sequence...");
+  Serial.println("===============================\n");
+}
+
+void loop() {
+  RMT_Write_Aync_Non_Blocking_Blink();
+  RMT_Loop_Write_Blink();
+  RMT_Single_Write_Blocking_Blink();
+  Serial.println("\nStarting OVER...\n");
+}
diff --git a/libraries/ESP32/examples/ResetReason/ResetReason.ino b/libraries/ESP32/examples/ResetReason/ResetReason.ino
deleted file mode 100644
index 3fc457d1f4a..00000000000
--- a/libraries/ESP32/examples/ResetReason/ResetReason.ino
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
-*  Print last reset reason of ESP32
-*  =================================
-*
-*  Use either of the methods print_reset_reason
-*  or verbose_print_reset_reason to display the
-*  cause for the last reset of this device.
-*
-*  Public Domain License.
-*
-*  Author:
-*  Evandro Luis Copercini - 2017
-*/
-
-#include <rom/rtc.h>
-
-#define uS_TO_S_FACTOR 1000000  /* Conversion factor for micro seconds to seconds */
-
-void print_reset_reason(RESET_REASON reason)
-{
-  switch ( reason)
-  {
-    case 1 : Serial.println ("POWERON_RESET");break;          /**<1,  Vbat power on reset*/
-    case 3 : Serial.println ("SW_RESET");break;               /**<3,  Software reset digital core*/
-    case 4 : Serial.println ("OWDT_RESET");break;             /**<4,  Legacy watch dog reset digital core*/
-    case 5 : Serial.println ("DEEPSLEEP_RESET");break;        /**<5,  Deep Sleep reset digital core*/
-    case 6 : Serial.println ("SDIO_RESET");break;             /**<6,  Reset by SLC module, reset digital core*/
-    case 7 : Serial.println ("TG0WDT_SYS_RESET");break;       /**<7,  Timer Group0 Watch dog reset digital core*/
-    case 8 : Serial.println ("TG1WDT_SYS_RESET");break;       /**<8,  Timer Group1 Watch dog reset digital core*/
-    case 9 : Serial.println ("RTCWDT_SYS_RESET");break;       /**<9,  RTC Watch dog Reset digital core*/
-    case 10 : Serial.println ("INTRUSION_RESET");break;       /**<10, Instrusion tested to reset CPU*/
-    case 11 : Serial.println ("TGWDT_CPU_RESET");break;       /**<11, Time Group reset CPU*/
-    case 12 : Serial.println ("SW_CPU_RESET");break;          /**<12, Software reset CPU*/
-    case 13 : Serial.println ("RTCWDT_CPU_RESET");break;      /**<13, RTC Watch dog Reset CPU*/
-    case 14 : Serial.println ("EXT_CPU_RESET");break;         /**<14, for APP CPU, reseted by PRO CPU*/
-    case 15 : Serial.println ("RTCWDT_BROWN_OUT_RESET");break;/**<15, Reset when the vdd voltage is not stable*/
-    case 16 : Serial.println ("RTCWDT_RTC_RESET");break;      /**<16, RTC Watch dog reset digital core and rtc module*/
-    default : Serial.println ("NO_MEAN");
-  }
-}
-
-void verbose_print_reset_reason(RESET_REASON reason)
-{
-  switch ( reason)
-  {
-    case 1  : Serial.println ("Vbat power on reset");break;
-    case 3  : Serial.println ("Software reset digital core");break;
-    case 4  : Serial.println ("Legacy watch dog reset digital core");break;
-    case 5  : Serial.println ("Deep Sleep reset digital core");break;
-    case 6  : Serial.println ("Reset by SLC module, reset digital core");break;
-    case 7  : Serial.println ("Timer Group0 Watch dog reset digital core");break;
-    case 8  : Serial.println ("Timer Group1 Watch dog reset digital core");break;
-    case 9  : Serial.println ("RTC Watch dog Reset digital core");break;
-    case 10 : Serial.println ("Instrusion tested to reset CPU");break;
-    case 11 : Serial.println ("Time Group reset CPU");break;
-    case 12 : Serial.println ("Software reset CPU");break;
-    case 13 : Serial.println ("RTC Watch dog Reset CPU");break;
-    case 14 : Serial.println ("for APP CPU, reseted by PRO CPU");break;
-    case 15 : Serial.println ("Reset when the vdd voltage is not stable");break;
-    case 16 : Serial.println ("RTC Watch dog reset digital core and rtc module");break;
-    default : Serial.println ("NO_MEAN");
-  }
-}
-
-void setup() {
-  // put your setup code here, to run once:
-  Serial.begin(115200);
-  delay(2000);
-
-  Serial.println("CPU0 reset reason:");
-  print_reset_reason(rtc_get_reset_reason(0));
-  verbose_print_reset_reason(rtc_get_reset_reason(0));
-
-  Serial.println("CPU1 reset reason:");
-  print_reset_reason(rtc_get_reset_reason(1));
-  verbose_print_reset_reason(rtc_get_reset_reason(1));
-
-  // Set ESP32 to go to deep sleep to see a variation
-  // in the reset reason. Device will sleep for 5 seconds.
-  esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_OFF);
-  Serial.println("Going to sleep");
-  esp_deep_sleep(5 * uS_TO_S_FACTOR);
-}
-
-void loop() {
-  // put your main code here, to run repeatedly:
-
-}
-
-/*
-  Example Serial Log:
-  ====================
-
-rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
-configsip: 0, SPIWP:0x00
-clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
-mode:DIO, clock div:1
-load:0x3fff0008,len:8
-load:0x3fff0010,len:160
-load:0x40078000,len:10632
-load:0x40080000,len:252
-entry 0x40080034
-CPU0 reset reason:
-RTCWDT_RTC_RESET
-RTC Watch dog reset digital core and rtc module
-CPU1 reset reason:
-EXT_CPU_RESET
-for APP CPU, reseted by PRO CPU
-Going to sleep
-ets Jun  8 2016 00:22:57
-
-rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
-configsip: 0, SPIWP:0x00
-clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
-mode:DIO, clock div:1
-load:0x3fff0008,len:8
-load:0x3fff0010,len:160
-load:0x40078000,len:10632
-load:0x40080000,len:252
-entry 0x40080034
-CPU0 reset reason:
-DEEPSLEEP_RESET
-Deep Sleep reset digital core
-CPU1 reset reason:
-EXT_CPU_RESET
-for APP CPU, reseted by PRO CPU
-Going to sleep
-ets Jun  8 2016 00:22:57
-
-rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
-configsip: 0, SPIWP:0x00
-clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
-mode:DIO, clock div:1
-load:0x3fff0008,len:8
-load:0x3fff0010,len:160
-load:0x40078000,len:10632
-load:0x40080000,len:252
-entry 0x40080034
-CPU0 reset reason:
-DEEPSLEEP_RESET
-Deep Sleep reset digital core
-CPU1 reset reason:
-EXT_CPU_RESET
-for APP CPU, reseted by PRO CPU
-Going to sleep
-
-*/
diff --git a/libraries/ESP32/examples/ResetReason/ResetReason/ResetReason.ino b/libraries/ESP32/examples/ResetReason/ResetReason/ResetReason.ino
new file mode 100644
index 00000000000..0104c6422f2
--- /dev/null
+++ b/libraries/ESP32/examples/ResetReason/ResetReason/ResetReason.ino
@@ -0,0 +1,166 @@
+/*
+*  Print last reset reason of ESP32
+*  =================================
+*
+*  Use either of the methods print_reset_reason
+*  or verbose_print_reset_reason to display the
+*  cause for the last reset of this device.
+*
+*  Public Domain License.
+*
+*  Author:
+*  Evandro Luis Copercini - 2017
+*/
+
+#if CONFIG_IDF_TARGET_ESP32  // ESP32/PICO-D4
+#include "esp32/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32P4
+#include "esp32p4/rom/rtc.h"
+#else
+#error Target CONFIG_IDF_TARGET is not supported
+#endif
+
+#define uS_TO_S_FACTOR 1000000 /* Conversion factor for micro seconds to seconds */
+
+void print_reset_reason(int reason) {
+  switch (reason) {
+    case 1:  Serial.println("POWERON_RESET"); break;          /**<1,  Vbat power on reset*/
+    case 3:  Serial.println("SW_RESET"); break;               /**<3,  Software reset digital core*/
+    case 4:  Serial.println("OWDT_RESET"); break;             /**<4,  Legacy watch dog reset digital core*/
+    case 5:  Serial.println("DEEPSLEEP_RESET"); break;        /**<5,  Deep Sleep reset digital core*/
+    case 6:  Serial.println("SDIO_RESET"); break;             /**<6,  Reset by SLC module, reset digital core*/
+    case 7:  Serial.println("TG0WDT_SYS_RESET"); break;       /**<7,  Timer Group0 Watch dog reset digital core*/
+    case 8:  Serial.println("TG1WDT_SYS_RESET"); break;       /**<8,  Timer Group1 Watch dog reset digital core*/
+    case 9:  Serial.println("RTCWDT_SYS_RESET"); break;       /**<9,  RTC Watch dog Reset digital core*/
+    case 10: Serial.println("INTRUSION_RESET"); break;        /**<10, Instrusion tested to reset CPU*/
+    case 11: Serial.println("TGWDT_CPU_RESET"); break;        /**<11, Time Group reset CPU*/
+    case 12: Serial.println("SW_CPU_RESET"); break;           /**<12, Software reset CPU*/
+    case 13: Serial.println("RTCWDT_CPU_RESET"); break;       /**<13, RTC Watch dog Reset CPU*/
+    case 14: Serial.println("EXT_CPU_RESET"); break;          /**<14, for APP CPU, reset by PRO CPU*/
+    case 15: Serial.println("RTCWDT_BROWN_OUT_RESET"); break; /**<15, Reset when the vdd voltage is not stable*/
+    case 16: Serial.println("RTCWDT_RTC_RESET"); break;       /**<16, RTC Watch dog reset digital core and rtc module*/
+    default: Serial.println("NO_MEAN");
+  }
+}
+
+void verbose_print_reset_reason(int reason) {
+  switch (reason) {
+    case 1:  Serial.println("Vbat power on reset"); break;
+    case 3:  Serial.println("Software reset digital core"); break;
+    case 4:  Serial.println("Legacy watch dog reset digital core"); break;
+    case 5:  Serial.println("Deep Sleep reset digital core"); break;
+    case 6:  Serial.println("Reset by SLC module, reset digital core"); break;
+    case 7:  Serial.println("Timer Group0 Watch dog reset digital core"); break;
+    case 8:  Serial.println("Timer Group1 Watch dog reset digital core"); break;
+    case 9:  Serial.println("RTC Watch dog Reset digital core"); break;
+    case 10: Serial.println("Instrusion tested to reset CPU"); break;
+    case 11: Serial.println("Time Group reset CPU"); break;
+    case 12: Serial.println("Software reset CPU"); break;
+    case 13: Serial.println("RTC Watch dog Reset CPU"); break;
+    case 14: Serial.println("for APP CPU, reset by PRO CPU"); break;
+    case 15: Serial.println("Reset when the vdd voltage is not stable"); break;
+    case 16: Serial.println("RTC Watch dog reset digital core and rtc module"); break;
+    default: Serial.println("NO_MEAN");
+  }
+}
+
+void setup() {
+  // put your setup code here, to run once:
+  Serial.begin(115200);
+  delay(2000);
+
+  Serial.println("CPU0 reset reason:");
+  print_reset_reason(rtc_get_reset_reason(0));
+  verbose_print_reset_reason(rtc_get_reset_reason(0));
+
+  Serial.println("CPU1 reset reason:");
+  print_reset_reason(rtc_get_reset_reason(1));
+  verbose_print_reset_reason(rtc_get_reset_reason(1));
+
+#ifndef CONFIG_IDF_TARGET_ESP32H2
+  // Set ESP32 to go to deep sleep to see a variation
+  // in the reset reason. Device will sleep for 5 seconds.
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+  esp_sleep_pd_config(ESP_PD_DOMAIN_RC_FAST, ESP_PD_OPTION_OFF);
+#else
+  esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_OFF);
+#endif
+  Serial.println("Going to sleep");
+  esp_deep_sleep(5 * uS_TO_S_FACTOR);
+#endif
+}
+
+void loop() {
+  // put your main code here, to run repeatedly:
+}
+
+/*
+  Example Serial Log:
+  ====================
+
+rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
+configsip: 0, SPIWP:0x00
+clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
+mode:DIO, clock div:1
+load:0x3fff0008,len:8
+load:0x3fff0010,len:160
+load:0x40078000,len:10632
+load:0x40080000,len:252
+entry 0x40080034
+CPU0 reset reason:
+RTCWDT_RTC_RESET
+RTC Watch dog reset digital core and rtc module
+CPU1 reset reason:
+EXT_CPU_RESET
+for APP CPU, reset by PRO CPU
+Going to sleep
+ets Jun  8 2016 00:22:57
+
+rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
+configsip: 0, SPIWP:0x00
+clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
+mode:DIO, clock div:1
+load:0x3fff0008,len:8
+load:0x3fff0010,len:160
+load:0x40078000,len:10632
+load:0x40080000,len:252
+entry 0x40080034
+CPU0 reset reason:
+DEEPSLEEP_RESET
+Deep Sleep reset digital core
+CPU1 reset reason:
+EXT_CPU_RESET
+for APP CPU, reset by PRO CPU
+Going to sleep
+ets Jun  8 2016 00:22:57
+
+rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
+configsip: 0, SPIWP:0x00
+clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
+mode:DIO, clock div:1
+load:0x3fff0008,len:8
+load:0x3fff0010,len:160
+load:0x40078000,len:10632
+load:0x40080000,len:252
+entry 0x40080034
+CPU0 reset reason:
+DEEPSLEEP_RESET
+Deep Sleep reset digital core
+CPU1 reset reason:
+EXT_CPU_RESET
+for APP CPU, reset by PRO CPU
+Going to sleep
+
+*/
diff --git a/libraries/ESP32/examples/ResetReason/ResetReason2/ResetReason2.ino b/libraries/ESP32/examples/ResetReason/ResetReason2/ResetReason2.ino
new file mode 100644
index 00000000000..9b59f6216f6
--- /dev/null
+++ b/libraries/ESP32/examples/ResetReason/ResetReason2/ResetReason2.ino
@@ -0,0 +1,64 @@
+//----------------------------------------------------------------------------------
+//  ResetReason2.ino
+//
+//  Prints last reset reason of ESP32
+//  This uses the mechanism in IDF that persists crash reasons across a reset.
+//  See https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/misc_system_api.html#software-reset
+//
+//  This example uses esp_reset_reason() instead of rtc_get_reset_reason(0).
+//  This example forces a WDT timeout in 10s.
+//
+//  Note enableLoopWDT() cannot be used here because it also takes care of
+//  resetting WDT.  See cores/esp32/main.cpp::loopTask().
+//
+//  Author: David McCurley
+//  Public Domain License
+//----------------------------------------------------------------------------------
+//  2023.04.21 r1.0 Initial release
+//----------------------------------------------------------------------------------
+
+#include "esp_task_wdt.h"
+
+//Converts reason type to a C string.
+//Type is located in /tools/sdk/esp32/include/esp_system/include/esp_system.h
+const char *resetReasonName(esp_reset_reason_t r) {
+  switch (r) {
+    case ESP_RST_UNKNOWN:   return "Unknown";
+    case ESP_RST_POWERON:   return "PowerOn";    //Power on or RST pin toggled
+    case ESP_RST_EXT:       return "ExtPin";     //External pin - not applicable for ESP32
+    case ESP_RST_SW:        return "Reboot";     //esp_restart()
+    case ESP_RST_PANIC:     return "Crash";      //Exception/panic
+    case ESP_RST_INT_WDT:   return "WDT_Int";    //Interrupt watchdog (software or hardware)
+    case ESP_RST_TASK_WDT:  return "WDT_Task";   //Task watchdog
+    case ESP_RST_WDT:       return "WDT_Other";  //Other watchdog
+    case ESP_RST_DEEPSLEEP: return "Sleep";      //Reset after exiting deep sleep mode
+    case ESP_RST_BROWNOUT:  return "BrownOut";   //Brownout reset (software or hardware)
+    case ESP_RST_SDIO:      return "SDIO";       //Reset over SDIO
+    default:                return "";
+  }
+}
+
+void PrintResetReason(void) {
+  esp_reset_reason_t r = esp_reset_reason();
+  if (r == ESP_RST_POWERON) {
+    delay(6000);  //Wait for serial monitor to connect
+  }
+  Serial.printf("\r\nReset reason %i - %s\r\n", r, resetReasonName(r));
+}
+
+void setup() {
+  Serial.begin(115200);
+  PrintResetReason();
+
+  //Start WDT monitor
+  if (esp_task_wdt_add(NULL) != ESP_OK) {
+    log_e("Failed to add current task to WDT");
+  }
+}
+
+//Enable esp_task_wdt_reset() below to prevent a WDT reset
+void loop() {
+  Serial.printf("Alive %lums\r\n", millis());
+  //esp_task_wdt_reset();
+  delay(1000);  //1s delay
+}
diff --git a/libraries/ESP32/examples/Serial/BaudRateDetect_Demo/BaudRateDetect_Demo.ino b/libraries/ESP32/examples/Serial/BaudRateDetect_Demo/BaudRateDetect_Demo.ino
new file mode 100644
index 00000000000..14cc59f4abc
--- /dev/null
+++ b/libraries/ESP32/examples/Serial/BaudRateDetect_Demo/BaudRateDetect_Demo.ino
@@ -0,0 +1,36 @@
+/*
+   This Sketch demonstrates how to detect and set the baud rate when the UART0 is connected to
+   some port that is sending data. It can be used with the Arduino IDE Serial Monitor to send the data.
+
+   Serial.begin(0) will start the baud rate detection. Valid range is 300 to 230400 baud.
+   It will try to detect for 20 seconds, by default, while reading RX.
+   This timeout of 20 seconds can be changed in the begin() function through <<timeout_ms>> parameter:
+
+   void HardwareSerial::begin(baud, config, rxPin, txPin, invert, <<timeout_ms>>, rxfifo_full_thrhd)
+
+   It is necessary that the other end sends some data within <<timeout_ms>>, otherwise the detection won't work.
+
+   IMPORTANT NOTE: baud rate detection seem to only work with ESP32 and ESP32-S2.
+   In other other SoCs, it doesn't work.
+
+*/
+
+// Open the Serial Monitor with testing baud start typing and sending characters
+void setup() {
+  Serial.begin(0);  // it will try to detect the baud rate for 20 seconds
+
+  Serial.print("\n==>The baud rate is ");
+  Serial.println(Serial.baudRate());
+
+  //after 20 seconds timeout, when not detected, it will return zero - in this case, we set it back to 115200.
+  if (Serial.baudRate() == 0) {
+    // Trying to set Serial to a safe state at 115200
+    Serial.end();
+    Serial.begin(115200);
+    Serial.setDebugOutput(true);
+    delay(1000);
+    log_e("Baud rate detection failed.");
+  }
+}
+
+void loop() {}
diff --git a/libraries/ESP32/examples/Serial/OnReceiveError_BREAK_Demo/OnReceiveError_BREAK_Demo.ino b/libraries/ESP32/examples/Serial/OnReceiveError_BREAK_Demo/OnReceiveError_BREAK_Demo.ino
new file mode 100644
index 00000000000..209cf8922be
--- /dev/null
+++ b/libraries/ESP32/examples/Serial/OnReceiveError_BREAK_Demo/OnReceiveError_BREAK_Demo.ino
@@ -0,0 +1,158 @@
+/*
+
+   This Sketch demonstrates how to use onReceiveError(callbackFunc) with HardwareSerial
+
+   void HardwareSerial::onReceiveError(OnReceiveErrorCb function)
+
+   It is possible to register a UART callback function that will be called
+   every time that UART detects an error which is also associated to an interrupt.
+
+   There are some possible UART errors:
+
+    UART_BREAK_ERROR - when a BREAK event is detected in the UART line. In that case, a BREAK may
+    be read as one or more bytes ZERO as part of the data received by the UART peripheral.
+
+    UART_BUFFER_FULL_ERROR - When the RX UART buffer is full. By default, Arduino will allocate a 256 bytes
+    RX buffer. As data is received, it is copied to the UART driver buffer, but when it is full and data can't
+    be copied anymore, this Error is issued. To prevent it the application can use
+    HardwareSerial::setRxBufferSize(size_t new_size), before using HardwareSerial::begin()
+
+    UART_FIFO_OVF_ERROR - When the UART peripheral RX FIFO is full and data is still arriving, this error is issued.
+    The UART driver will stash RX FIFO and the data will be lost. In order to prevent, the application shall set a
+    good buffer size using HardwareSerial::setRxBufferSize(size_t new_size), before using HardwareSerial::begin()
+
+    UART_FRAME_ERROR - When the UART peripheral detects a UART frame error, this error is issued. It may happen because
+    of line noise or bad impiedance.
+
+    UART_PARITY_ERROR - When the UART peripheral detects a parity bit error, this error will be issued.
+
+
+   In summary, HardwareSerial::onReceiveError() works like an UART Error Notification callback.
+
+   Errors have priority in the order of the callbacks, therefore, as soon as an error is detected,
+   the registered callback is executed first, and only after that, the OnReceive() registered
+   callback function will be executed. This will give opportunity for the Application to take action
+   before reading data, if necessary.
+
+   In long UART transmissions, some data will be received based on FIFO Full parameter, and whenever
+   an error occurs, it will raise the UART error interrupt.
+
+   This sketch produces BREAK UART error in the beginning of a transmission and also at the end of a
+   transmission. It will be possible to understand the order of the events in the logs.
+
+*/
+
+#include <Arduino.h>
+
+// There are two ways to make this sketch work:
+// By physically connecting the pins 4 and 5 and then create a physical UART loopback,
+// Or by using the internal IO_MUX to connect the TX signal to the RX pin, creating the
+// same loopback internally.
+#define USE_INTERNAL_PIN_LOOPBACK 1  // 1 uses the internal loopback, 0 for wiring pins 4 and 5 externally
+
+#define DATA_SIZE 26    // 26 bytes is a lower than RX FIFO size (127 bytes)
+#define BAUD      9600  // Any baudrate from 300 to 115200
+#define TEST_UART 1     // Serial1 will be used for the loopback testing with different RX FIFO FULL values
+#define RXPIN     4     // GPIO 4 => RX for Serial1
+#define TXPIN     5     // GPIO 5 => TX for Serial1
+
+#define BREAK_BEFORE_MSG 0
+#define BREAK_AT_END_MSG 1
+
+uint8_t fifoFullTestCases[] = {120, 20, 5, 1};
+// volatile declaration will avoid any compiler optimization when reading variable values
+volatile size_t sent_bytes = 0, received_bytes = 0;
+
+const char *uartErrorStrings[] = {"UART_NO_ERROR",       "UART_BREAK_ERROR", "UART_BUFFER_FULL_ERROR",
+                                  "UART_FIFO_OVF_ERROR", "UART_FRAME_ERROR", "UART_PARITY_ERROR"};
+
+// Callback function that will treat the UART errors
+void onReceiveErrorFunction(hardwareSerial_error_t err) {
+  // This is a callback function that will be activated on UART RX Error Events
+  Serial.printf("\n-- onReceiveError [ERR#%d:%s] \n", err, uartErrorStrings[err]);
+  Serial.printf("-- onReceiveError:: There are %d bytes available.\n", Serial1.available());
+}
+
+// Callback function that will deal with arriving UART data
+void onReceiveFunction() {
+  // This is a callback function that will be activated on UART RX events
+  size_t available = Serial1.available();
+  received_bytes = received_bytes + available;
+  Serial.printf("onReceive Callback:: There are %d bytes available: {", available);
+  while (available--) {
+    char c = Serial1.read();
+    Serial.printf("0x%x='%c'", c, c);
+    if (available) {
+      Serial.print(" ");
+    }
+  }
+  Serial.println("}");
+}
+
+void setup() {
+  // UART0 will be used to log information into Serial Monitor
+  Serial.begin(115200);
+
+  // UART1 will have its RX<->TX cross connected
+  // GPIO4 <--> GPIO5 using external wire
+  Serial1.begin(BAUD, SERIAL_8N1, RXPIN, TXPIN);  // Rx = 4, Tx = 5 will work for ESP32, S2, S3 and C3
+#if USE_INTERNAL_PIN_LOOPBACK
+  uart_internal_loopback(TEST_UART, RXPIN);
+#endif
+
+  for (uint8_t i = 0; i < sizeof(fifoFullTestCases); i++) {
+    Serial.printf("\n\n================================\nTest Case #%d BREAK at END\n================================\n", i + 1);
+    // First sending BREAK at the end of the UART data transmission
+    testAndReport(fifoFullTestCases[i], BREAK_AT_END_MSG);
+    Serial.printf("\n\n================================\nTest Case #%d BREAK at BEGINNING\n================================\n", i + 1);
+    // Now sending BREAK at the beginning of the UART data transmission
+    testAndReport(fifoFullTestCases[i], BREAK_BEFORE_MSG);
+    Serial.println("========================\nFinished!");
+  }
+}
+
+void loop() {}
+
+void testAndReport(uint8_t fifoFull, bool break_at_the_end) {
+  // Let's send 125 bytes from Serial1 rx<->tx and mesaure time using different FIFO Full configurations
+  received_bytes = 0;
+  sent_bytes = DATA_SIZE;  // 26 characters
+
+  uint8_t dataSent[DATA_SIZE + 1];
+  dataSent[DATA_SIZE] = '\0';  // string null terminator, for easy printing.
+
+  // initialize all data
+  for (uint8_t i = 0; i < DATA_SIZE; i++) {
+    dataSent[i] = 'A' + i;  // fill it with characters A..Z
+  }
+
+  Serial.printf("\nTesting onReceive for receiving %d bytes at %d baud, using RX FIFO Full = %d.\n", sent_bytes, BAUD, fifoFull);
+  Serial.println("onReceive is called on both FIFO Full and RX Timeout events.");
+  if (break_at_the_end) {
+    Serial.printf("BREAK event will be sent at the END of the %d bytes\n", sent_bytes);
+  } else {
+    Serial.printf("BREAK event will be sent at the BEGINNING of the %d bytes\n", sent_bytes);
+  }
+  Serial.flush();                                  // wait Serial FIFO to be empty and then spend almost no time processing it
+  Serial1.setRxFIFOFull(fifoFull);                 // testing different result based on FIFO Full setup
+  Serial1.onReceive(onReceiveFunction);            // sets a RX callback function for Serial 1
+  Serial1.onReceiveError(onReceiveErrorFunction);  // sets a RX callback function for Serial 1
+
+  if (break_at_the_end) {
+    sent_bytes = uart_send_msg_with_break(TEST_UART, dataSent, DATA_SIZE);
+  } else {
+    uart_send_break(TEST_UART);
+    sent_bytes = Serial1.write(dataSent, DATA_SIZE);
+  }
+
+  Serial.printf("\nSent String: %s\n", dataSent);
+  while (received_bytes < sent_bytes) {
+    // just wait for receiving all byte in the callback...
+  }
+
+  Serial.printf("\nIt has sent %d bytes from Serial1 TX to Serial1 RX\n", sent_bytes);
+  Serial.printf("onReceive() has read a total of %d bytes\n", received_bytes);
+
+  Serial1.onReceiveError(NULL);  // resets/disables the RX Error callback function for Serial 1
+  Serial1.onReceive(NULL);       // resets/disables the RX callback function for Serial 1
+}
diff --git a/libraries/ESP32/examples/Serial/OnReceive_Demo/OnReceive_Demo.ino b/libraries/ESP32/examples/Serial/OnReceive_Demo/OnReceive_Demo.ino
new file mode 100644
index 00000000000..cac59a50cd6
--- /dev/null
+++ b/libraries/ESP32/examples/Serial/OnReceive_Demo/OnReceive_Demo.ino
@@ -0,0 +1,130 @@
+/*
+
+   This Sketch demonstrates how to use onReceive(callbackFunc) with HardwareSerial
+
+   void HardwareSerial::onReceive(OnReceiveCb function, bool onlyOnTimeout = false)
+
+   It is possible to register a UART callback function that will be called
+   every time that UART receives data and an associated interrupt is generated.
+
+   The receiving data interrupt can occur because of two possible events:
+
+   1- UART FIFO FULL: it happens when internal UART FIFO reaches a certain number of bytes.
+      Its full capacity is 127 bytes. The FIFO Full threshold for the interrupt can be changed
+      using HardwareSerial::setRxFIFOFull(uint8_t fifoFull).
+      Default FIFO Full Threshold is set at the UART initialization using HardwareSerial::begin()
+      This will depend on the baud rate set with when begin() is executed.
+      For a baudrate of 115200 or lower, it it just 1 byte, mimicking original Arduino UART driver.
+      For a baudrate over 115200 it will be 120 bytes for higher performance.
+      Anyway it can be changed by the application at anytime.
+
+   2- UART RX Timeout: it happens, based on a timeout equivalent to a number of symbols at
+      the current baud rate. If the UART line is idle for this timeout, it will raise an interrupt.
+      This time can be changed by HardwareSerial::setRxTimeout(uint8_t rxTimeout)
+
+   When any of those two interrupts occur, IDF UART driver will copy FIFO data to its internal
+   RingBuffer and then Arduino can read such data. At the same time, Arduino Layer will execute
+   the callback function defined with HardwareSerial::onReceive().
+
+   <bool onlyOnTimeout> parameter (default false) can be used by the application to tell Arduino to
+   only execute the callback when the second event above happens (Rx Timeout). At this time all
+   received data will be available to be read by the Arduino application. But if the number of
+   received bytes is higher than the FIFO space, it will generate an error of FIFO overflow.
+   In order to avoid such problem, the application shall set an appropriate RX buffer size using
+   HardwareSerial::setRxBufferSize(size_t new_size) before executing begin() for the Serial port.
+
+   In summary, HardwareSerial::onReceive() works like an RX Interrupt callback, that can be adjusted
+   using HardwareSerial::setRxFIFOFull() and HardwareSerial::setRxTimeout().
+
+*/
+
+#include <Arduino.h>
+
+// There are two ways to make this sketch work:
+// By physically connecting the pins 4 and 5 and then create a physical UART loopback,
+// Or by using the internal IO_MUX to connect the TX signal to the RX pin, creating the
+// same loopback internally.
+#define USE_INTERNAL_PIN_LOOPBACK 1  // 1 uses the internal loopback, 0 for wiring pins 4 and 5 externally
+
+#define DATA_SIZE 26    // 26 bytes is a lower than RX FIFO size (127 bytes)
+#define BAUD      9600  // Any baudrate from 300 to 115200
+#define TEST_UART 1     // Serial1 will be used for the loopback testing with different RX FIFO FULL values
+#define RXPIN     4     // GPIO 4 => RX for Serial1
+#define TXPIN     5     // GPIO 5 => TX for Serial1
+
+uint8_t fifoFullTestCases[] = {120, 20, 5, 1};
+// volatile declaration will avoid any compiler optimization when reading variable values
+volatile size_t sent_bytes = 0, received_bytes = 0;
+
+void onReceiveFunction(void) {
+  // This is a callback function that will be activated on UART RX events
+  size_t available = Serial1.available();
+  received_bytes = received_bytes + available;
+  Serial.printf("onReceive Callback:: There are %d bytes available: ", available);
+  while (available--) {
+    Serial.print((char)Serial1.read());
+  }
+  Serial.println();
+}
+
+void setup() {
+  // UART0 will be used to log information into Serial Monitor
+  Serial.begin(115200);
+
+  // UART1 will have its RX<->TX cross connected
+  // GPIO4 <--> GPIO5 using external wire
+  Serial1.begin(BAUD, SERIAL_8N1, RXPIN, TXPIN);  // Rx = 4, Tx = 5 will work for ESP32, S2, S3 and C3
+#if USE_INTERNAL_PIN_LOOPBACK
+  uart_internal_loopback(TEST_UART, RXPIN);
+#endif
+
+  for (uint8_t i = 0; i < sizeof(fifoFullTestCases); i++) {
+    Serial.printf("\n\n================================\nTest Case #%d\n================================\n", i + 1);
+    // onReceive callback will be called on FIFO Full and RX timeout - default behavior
+    testAndReport(fifoFullTestCases[i], false);
+  }
+
+  Serial.printf("\n\n================================\nTest Case #6\n================================\n");
+  // onReceive callback will be called just on RX timeout - using onlyOnTimeout = true
+  // FIFO Full parameter (5 bytes) won't matter for the execution of this test case
+  // because onReceive() uses only RX Timeout to be activated
+  testAndReport(5, true);
+}
+
+void loop() {}
+
+void testAndReport(uint8_t fifoFull, bool onlyOnTimeOut) {
+  // Let's send 125 bytes from Serial1 rx<->tx and mesaure time using different FIFO Full configurations
+  received_bytes = 0;
+  sent_bytes = DATA_SIZE;  // 26 characters
+
+  uint8_t dataSent[DATA_SIZE + 1];
+  dataSent[DATA_SIZE] = '\0';  // string null terminator, for easy printing.
+
+  // initialize all data
+  for (uint8_t i = 0; i < DATA_SIZE; i++) {
+    dataSent[i] = 'A' + i;  // fill it with characters A..Z
+  }
+
+  Serial.printf("\nTesting onReceive for receiving %d bytes at %d baud, using RX FIFO Full = %d.\n", sent_bytes, BAUD, fifoFull);
+  if (onlyOnTimeOut) {
+    Serial.println("onReceive is called just on RX Timeout!");
+  } else {
+    Serial.println("onReceive is called on both FIFO Full and RX Timeout events.");
+  }
+  Serial.flush();                                       // wait Serial FIFO to be empty and then spend almost no time processing it
+  Serial1.setRxFIFOFull(fifoFull);                      // testing different result based on FIFO Full setup
+  Serial1.onReceive(onReceiveFunction, onlyOnTimeOut);  // sets a RX callback function for Serial 1
+
+  sent_bytes = Serial1.write(dataSent, DATA_SIZE);  // ESP32 TX FIFO is about 128 bytes, 125 bytes will fit fine
+  Serial.printf("\nSent String: %s\n", dataSent);
+  while (received_bytes < sent_bytes) {
+    // just wait for receiving all byte in the callback...
+  }
+
+  Serial.printf("\nIt has sent %d bytes from Serial1 TX to Serial1 RX\n", sent_bytes);
+  Serial.printf("onReceive() has read a total of %d bytes\n", received_bytes);
+  Serial.println("========================\nFinished!");
+
+  Serial1.onReceive(NULL);  // resets/disables the RX callback function for Serial 1
+}
diff --git a/libraries/ESP32/examples/Serial/RS485_Echo_Demo/RS485_Echo_Demo.ino b/libraries/ESP32/examples/Serial/RS485_Echo_Demo/RS485_Echo_Demo.ino
new file mode 100644
index 00000000000..50ee6f53fe2
--- /dev/null
+++ b/libraries/ESP32/examples/Serial/RS485_Echo_Demo/RS485_Echo_Demo.ino
@@ -0,0 +1,49 @@
+/*
+  This Sketch demonstrates how to use the Hardware Serial peripheral to communicate over an RS485 bus.
+
+  Data received on the primary serial port is relayed to the bus acting as an RS485 interface and vice versa.
+
+  UART to RS485 translation hardware (e.g., MAX485, MAX33046E, ADM483) is assumed to be configured in half-duplex
+  mode with collision detection as described in
+  https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/uart.html#circuit-a-collision-detection-circuit
+
+  To use the script open the Arduino serial monitor (or alternative serial monitor on the Arduino port). Then,
+  using an RS485 tranciver, connect another serial monitor to the RS485 port. Entering data on one terminal
+  should be displayed on the other terminal.
+*/
+#include "hal/uart_types.h"
+
+#define RS485_RX_PIN  16
+#define RS485_TX_PIN  5
+#define RS485_RTS_PIN 4
+
+#define RS485 Serial1
+
+void setup() {
+  Serial.begin(115200);
+
+  RS485.begin(9600, SERIAL_8N1, RS485_RX_PIN, RS485_TX_PIN);
+  while (!RS485) {
+    delay(10);
+  }
+  if (!RS485.setPins(-1, -1, -1, RS485_RTS_PIN)) {
+    Serial.print("Failed to set RS485 pins");
+  }
+
+  // Certain versions of Arduino core don't define MODE_RS485_HALF_DUPLEX and so fail to compile.
+  // By using UART_MODE_RS485_HALF_DUPLEX defined in hal/uart_types.h we work around this problem.
+  // If using a newer IDF and Arduino core you can omit including hal/uart_types.h and use MODE_RS485_HALF_DUPLEX
+  // defined in esp32-hal-uart.h (included during other build steps) instead.
+  if (!RS485.setMode(UART_MODE_RS485_HALF_DUPLEX)) {
+    Serial.print("Failed to set RS485 mode");
+  }
+}
+
+void loop() {
+  if (RS485.available()) {
+    Serial.write(RS485.read());
+  }
+  if (Serial.available()) {
+    RS485.write(Serial.read());
+  }
+}
diff --git a/libraries/ESP32/examples/Serial/RxFIFOFull_Demo/RxFIFOFull_Demo.ino b/libraries/ESP32/examples/Serial/RxFIFOFull_Demo/RxFIFOFull_Demo.ino
new file mode 100644
index 00000000000..7722ef6f47a
--- /dev/null
+++ b/libraries/ESP32/examples/Serial/RxFIFOFull_Demo/RxFIFOFull_Demo.ino
@@ -0,0 +1,106 @@
+/*
+ *
+ * This Sketch demonstrates the effect of changing RX FIFO Full parameter into HardwareSerial Class
+ * Serial.setRxFIFOFull(byte) is used to change it.
+ * By default, UART ISR will wait for 120 bytes to arrive into UART before making the data available
+ * to be read by an Arduino Sketch. It may also release fewer bytes after an RX Timeout equivalent by
+ * default to 2 UART symbols.
+ *
+ * The way we demonstrate the effect of this parameter is by measuring the time the Sketch takes
+ * to read data using Arduino HardwareSerial API.
+ *
+ * The higher RX FIFO Full is, the lower consumption of the core to process and make the data available.
+ * At the same time, it may take longer for the Sketch to be able to read it, because the data must first
+ * populate RX UART FIFO.
+ *
+ * The lower RX FIFO Full is, the higher consumption of the core to process and make the data available.
+ * This is because the core will be interrupted often and it will copy data from the RX FIFO to the Arduino
+ * internal buffer to be read by the sketch. By other hand, the data will be made available to the sketch
+ * faster, in a close to byte by byte communication.
+ *
+ * Therefore, it allows the decision of the architecture to be designed by the developer.
+ * Some application based on certain protocols may need the sketch to read the Serial Port byte by byte, for example.
+ *
+ */
+
+#include <Arduino.h>
+
+// There are two ways to make this sketch work:
+// By physically connecting the pins 4 and 5 and then create a physical UART loopback,
+// Or by using the internal IO_MUX to connect the TX signal to the RX pin, creating the
+// same loopback internally.
+#define USE_INTERNAL_PIN_LOOPBACK 1  // 1 uses the internal loopback, 0 for wiring pins 4 and 5 externally
+
+#define DATA_SIZE 125   // 125 bytes is a bit higher than the default 120 bytes of RX FIFO FULL
+#define BAUD      9600  // Any baudrate from 300 to 115200
+#define TEST_UART 1     // Serial1 will be used for the loopback testing with different RX FIFO FULL values
+#define RXPIN     4     // GPIO 4 => RX for Serial1
+#define TXPIN     5     // GPIO 5 => TX for Serial1
+
+uint8_t fifoFullTestCases[] = {120, 20, 5, 1};
+
+void setup() {
+  // UART0 will be used to log information into Serial Monitor
+  Serial.begin(115200);
+
+  // UART1 will have its RX<->TX cross connected
+  // GPIO4 <--> GPIO5 using external wire
+  Serial1.begin(BAUD, SERIAL_8N1, RXPIN, TXPIN);  // Rx = 4, Tx = 5 will work for ESP32, S2, S3 and C3
+#if USE_INTERNAL_PIN_LOOPBACK
+  uart_internal_loopback(TEST_UART, RXPIN);
+#endif
+
+  for (uint8_t i = 0; i < sizeof(fifoFullTestCases); i++) {
+    Serial.printf("\n\n================================\nTest Case #%d\n================================\n", i + 1);
+    testAndReport(fifoFullTestCases[i]);
+  }
+}
+
+void loop() {}
+
+void testAndReport(uint8_t fifoFull) {
+  // Let's send 125 bytes from Serial1 rx<->tx and mesaure time using different FIFO Full configurations
+  uint8_t bytesReceived = 0;
+  uint8_t dataSent[DATA_SIZE], dataReceived[DATA_SIZE];
+  uint32_t timeStamp[DATA_SIZE], bytesJustReceived[DATA_SIZE];
+  uint8_t i;
+  // initialize all data
+  for (i = 0; i < DATA_SIZE; i++) {
+    dataSent[i] = '0' + (i % 10);  // fill it with a repeated sequence of 0..9 characters
+    dataReceived[i] = 0;
+    timeStamp[i] = 0;
+    bytesJustReceived[i] = 0;
+  }
+
+  Serial.printf("Testing the time for receiving %d bytes at %d baud, using RX FIFO Full = %d:", DATA_SIZE, BAUD, fifoFull);
+  Serial.flush();                   // wait Serial FIFO to be empty and then spend almost no time processing it
+  Serial1.setRxFIFOFull(fifoFull);  // testing different result based on FIFO Full setup
+
+  size_t sentBytes = Serial1.write(dataSent, sizeof(dataSent));  // ESP32 TX FIFO is about 128 bytes, 125 bytes will fit fine
+  uint32_t now = millis();
+  i = 0;
+  while (bytesReceived < DATA_SIZE) {
+    bytesReceived += (bytesJustReceived[i] = Serial1.read(dataReceived + bytesReceived, DATA_SIZE));
+    timeStamp[i] = millis();
+    if (bytesJustReceived[i] > 0) {
+      i++;  // next data only when we read something from Serial1
+    }
+    // safety for array limit && timeout... in 5 seconds...
+    if (i == DATA_SIZE || millis() - now > 5000) {
+      break;
+    }
+  }
+
+  uint32_t pastTime = millis() - now;  // codespell:ignore pasttime
+  Serial.printf("\nIt has sent %d bytes from Serial1 TX to Serial1 RX\n", sentBytes);
+  Serial.printf("It took %lu milliseconds to read %d bytes\n", pastTime, bytesReceived);  // codespell:ignore pasttime
+  Serial.printf("Per execution Serial.read() number of bytes data and time information:\n");
+  for (i = 0; i < DATA_SIZE; i++) {
+    Serial.printf("#%03d - Received %03lu bytes after %lu ms.\n", i, bytesJustReceived[i], i > 0 ? timeStamp[i] - timeStamp[i - 1] : timeStamp[i] - now);
+    if (i != DATA_SIZE - 1 && bytesJustReceived[i + 1] == 0) {
+      break;
+    }
+  }
+
+  Serial.println("========================\nFinished!");
+}
diff --git a/libraries/ESP32/examples/Serial/RxTimeout_Demo/RxTimeout_Demo.ino b/libraries/ESP32/examples/Serial/RxTimeout_Demo/RxTimeout_Demo.ino
new file mode 100644
index 00000000000..35d2da5c199
--- /dev/null
+++ b/libraries/ESP32/examples/Serial/RxTimeout_Demo/RxTimeout_Demo.ino
@@ -0,0 +1,110 @@
+/*
+
+   This Sketch demonstrates the effect of changing RX Timeout parameter into HardwareSerial Class
+   Serial.setRxTimeout(byte) is used to change it.
+   By default, UART ISR will wait for an RX Timeout equivalent to 2 UART symbols to understand that a flow.
+   of UART data has ended. For example, if just one byte is received, UART will send about 10 to
+   11 bits depending of the configuration (parity, number of stopbits). The timeout is measured in
+   number of UART symbols, with 10 or 11 bits, in the current baudrate.
+   For 9600 baud, 1 bit takes 1/9600 of a second, equivalent to 104 microseconds, therefore, for 10 bits,
+   it takes about 1ms. A timeout of 2 UART symbols, with about 20 bits, would take about 2.1 milliseconds
+   for the ESP32 UART to trigger an IRQ telling the UART driver that the transmission has ended.
+   Just at this point, the data will be made available to Arduino HardwareSerial API (read(), available(), etc).
+
+   The way we demonstrate the effect of this parameter is by measuring the time the Sketch takes
+   to read data using Arduino HardwareSerial API.
+
+   The higher RX Timeout is, the longer it will take to make the data available, when a flow of data ends.
+   UART driver works copying data from UART FIFO to Arduino internal buffer.
+   The driver will copy data from FIFO when RX Timeout is detected or when FIFO is full.
+   ESP32 FIFO has 128 bytes and by default, the driver will copy the data when FIFO reaches 120 bytes.
+   If UART receives less than 120 bytes, it will wait RX Timeout to understand that the bus is IDLE and
+   then copy the data from the FIFO to the Arduino internal buffer, making it available to the Arduino API.
+
+   There is an important detail about how HardwareSerial works using ESP32 and ESP32-S2:
+   If the baud rate is lower than 250,000, it will select REF_TICK as clock source in order to avoid that
+   the baud rate may change when the CPU Frequency is changed. Default UART clock source is APB, which changes
+   when CPU clock source is also changed. But when it selects REF_TICK as UART clock source, RX Timeout is limited to 1.
+   Therefore, in order to change the ESP32/ESP32-S2 RX Timeout it is necessary to fix the UART Clock Source to APB.
+
+   In the case of the other SoC, such as ESP32-S3, C3, C6, H2 and P4, there is no such RX Timeout limitation.
+   Those will set the UART Source Clock as XTAL, which allows the baud rate to be high and it is steady, not
+   changing with the CPU Frequency.
+*/
+
+#include <Arduino.h>
+
+// There are two ways to make this sketch work:
+// By physically connecting the pins 4 and 5 and then create a physical UART loopback,
+// Or by using the internal IO_MUX to connect the TX signal to the RX pin, creating the
+// same loopback internally.
+#define USE_INTERNAL_PIN_LOOPBACK 1  // 1 uses the internal loopback, 0 for wiring pins 4 and 5 externally
+
+#define DATA_SIZE 10    // 10 bytes is lower than the default 120 bytes of RX FIFO FULL
+#define BAUD      9600  // Any baudrate from 300 to 115200
+#define TEST_UART 1     // Serial1 will be used for the loopback testing with different RX FIFO FULL values
+#define RXPIN     4     // GPIO 4 => RX for Serial1
+#define TXPIN     5     // GPIO 5 => TX for Serial1
+
+uint8_t rxTimeoutTestCases[] = {50, 20, 10, 5, 1};
+
+void setup() {
+  // UART0 will be used to log information into Serial Monitor
+  Serial.begin(115200);
+
+  // UART1 will have its RX<->TX cross connected
+  // GPIO4 <--> GPIO5 using external wire
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+  // UART_CLK_SRC_APB will allow higher values of RX Timeout
+  // default for ESP32 and ESP32-S2 is REF_TICK which limits the RX Timeout to 1
+  // setClockSource() must be called before begin()
+  Serial1.setClockSource(UART_CLK_SRC_APB);
+#endif
+  Serial1.begin(BAUD, SERIAL_8N1, RXPIN, TXPIN);  // Rx = 4, Tx = 5 will work for ESP32, S2, S3 and C3
+#if USE_INTERNAL_PIN_LOOPBACK
+  uart_internal_loopback(TEST_UART, RXPIN);
+#endif
+
+  for (uint8_t i = 0; i < sizeof(rxTimeoutTestCases); i++) {
+    Serial.printf("\n\n================================\nTest Case #%d\n================================\n", i + 1);
+    testAndReport(rxTimeoutTestCases[i]);
+  }
+}
+
+void loop() {}
+
+void testAndReport(uint8_t rxTimeout) {
+  // Let's send 10 bytes from Serial1 rx<->tx and mesaure time using different Rx Timeout configurations
+  uint8_t bytesReceived = 0;
+  uint8_t dataSent[DATA_SIZE], dataReceived[DATA_SIZE];
+  uint8_t i;
+  // initialize all data
+  for (i = 0; i < DATA_SIZE; i++) {
+    dataSent[i] = '0' + (i % 10);  // fill it with a repeated sequence of 0..9 characters
+    dataReceived[i] = 0;
+  }
+
+  Serial.printf("Testing the time for receiving %d bytes at %d baud, using RX Timeout = %d:", DATA_SIZE, BAUD, rxTimeout);
+  Serial.flush();                   // wait Serial FIFO to be empty and then spend almost no time processing it
+  Serial1.setRxTimeout(rxTimeout);  // testing different results based on Rx Timeout setup
+  // For baud rates lower or equal to 57600, ESP32 Arduino makes it get byte-by-byte from FIFO, thus we will change it here:
+  Serial1.setRxFIFOFull(120);  // forces it to wait receiving 120 bytes in FIFO before making it available to Arduino
+
+  size_t sentBytes = Serial1.write(dataSent, sizeof(dataSent));  // ESP32 TX FIFO is about 128 bytes, 10 bytes will fit fine
+  uint32_t now = millis();
+  while (bytesReceived < DATA_SIZE) {
+    bytesReceived += Serial1.read(dataReceived, DATA_SIZE);
+    // safety for array limit && timeout... in 5 seconds...
+    if (millis() - now > 5000) {
+      break;
+    }
+  }
+
+  uint32_t pastTime = millis() - now;  // codespell:ignore pasttime
+  Serial.printf("\nIt has sent %d bytes from Serial1 TX to Serial1 RX\n", sentBytes);
+  Serial.printf("It took %lu milliseconds to read %d bytes\n", pastTime, bytesReceived);  // codespell:ignore pasttime
+  Serial.print("Received data: [");
+  Serial.write(dataReceived, DATA_SIZE);
+  Serial.println("]");
+  Serial.println("========================\nFinished!");
+}
diff --git a/libraries/ESP32/examples/Serial/Serial_All_CPU_Freqs/Serial_All_CPU_Freqs.ino b/libraries/ESP32/examples/Serial/Serial_All_CPU_Freqs/Serial_All_CPU_Freqs.ino
new file mode 100644
index 00000000000..26a5125bbbc
--- /dev/null
+++ b/libraries/ESP32/examples/Serial/Serial_All_CPU_Freqs/Serial_All_CPU_Freqs.ino
@@ -0,0 +1,75 @@
+/*
+   Simple Sketch for testing HardwareSerial with different CPU Frequencies
+   Changing the CPU Frequency may affect peripherals and Wireless functionality
+   In ESP32 Arduino, UART shall work correctly in order to let the user see DGB info
+   and other application messages.
+
+   CPU Frequency is usually lowered in sleep modes
+   and some other Low Power configurations
+
+*/
+
+int cpufreqs[6] = {240, 160, 80, 40, 20, 10};
+#define NUM_CPU_FREQS (sizeof(cpufreqs) / sizeof(int))
+
+void setup() {
+
+  Serial.begin(115200);
+  delay(1000);
+  Serial.println("\n Starting...\n");
+  Serial.flush();
+
+  // initial information
+  uint32_t Freq = getCpuFrequencyMhz();
+  Serial.print("CPU Freq = ");
+  Serial.print(Freq);
+  Serial.println(" MHz");
+  Freq = getXtalFrequencyMhz();
+  Serial.print("XTAL Freq = ");
+  Serial.print(Freq);
+  Serial.println(" MHz");
+  Freq = getApbFrequency();
+  Serial.print("APB Freq = ");
+  Serial.print(Freq);
+  Serial.println(" Hz");
+  delay(500);
+
+  // ESP32-C3 and other RISC-V target may not support 240MHz
+#ifdef CONFIG_IDF_TARGET_ESP32C3
+  uint8_t firstFreq = 1;
+#else
+  uint8_t firstFreq = 0;
+#endif
+
+  // testing HardwareSerial for all possible CPU/APB Frequencies
+  for (uint8_t i = firstFreq; i < NUM_CPU_FREQS; i++) {
+    Serial.printf("\n------- Trying CPU Freq = %d ---------\n", cpufreqs[i]);
+    Serial.flush();  // wait to empty the UART FIFO before changing the CPU Freq.
+    setCpuFrequencyMhz(cpufreqs[i]);
+    Serial.updateBaudRate(115200);
+
+    Freq = getCpuFrequencyMhz();
+    Serial.print("CPU Freq = ");
+    Serial.print(Freq);
+    Serial.println(" MHz");
+    Freq = getXtalFrequencyMhz();
+    Serial.print("XTAL Freq = ");
+    Serial.print(Freq);
+    Serial.println(" MHz");
+    Freq = getApbFrequency();
+    Serial.print("APB Freq = ");
+    Serial.print(Freq);
+    Serial.println(" Hz");
+    if (i < NUM_CPU_FREQS - 1) {
+      Serial.println("Moving to the next frequency after a pause of 2 seconds.");
+      delay(2000);
+    }
+  }
+  Serial.println("\n-------------------\n");
+  Serial.println("End of testing...");
+  Serial.println("\n-------------------\n");
+}
+
+void loop() {
+  // Nothing here so far
+}
diff --git a/libraries/ESP32/examples/Serial/Serial_STD_Func_OnReceive/Serial_STD_Func_OnReceive.ino b/libraries/ESP32/examples/Serial/Serial_STD_Func_OnReceive/Serial_STD_Func_OnReceive.ino
new file mode 100644
index 00000000000..3c5ff0ba6fc
--- /dev/null
+++ b/libraries/ESP32/examples/Serial/Serial_STD_Func_OnReceive/Serial_STD_Func_OnReceive.ino
@@ -0,0 +1,123 @@
+/*
+ * This is C++ example that demonstrates the usage of a std::function as OnReceive Callback function to all the UARTs
+ * It basically defines a general onReceive function that receives an extra parameter, the Serial pointer that is
+ * executing the callback.
+ *
+ * For each HardwareSerial object (Serial, Serial1, Serial2), it is necessary to set the callback with
+ * the respective Serial pointer. It is done using lambda expression as a std::function.
+ * Example:
+ * Serial1.onReceive([]() { processOnReceiving(&Serial1); });
+ *
+ */
+
+// soc/soc_caps.h has information about each SoC target
+// in this example, we use SOC_UART_HP_NUM that goes from 1 to 3,
+// depending on the number of available UARTs in the ESP32xx
+// This makes the code transparent to what SoC is used.
+#include "soc/soc_caps.h"
+
+// This example shall use UART1 or UART2 for testing and UART0 for console messages
+// If UART0 is used for testing, it is necessary to manually send data to it, using the Serial Monitor/Terminal
+// In case that USB CDC is available, it may be used as console for messages.
+#define TEST_UART 1  // Serial# (0, 1 or 2) will be used for the loopback
+#define RXPIN     4  // GPIO 4 => RX for Serial1 or Serial2
+#define TXPIN     5  // GPIO 5 => TX for Serial1 or Serial2
+
+// declare testingSerial (as reference) related to TEST_UART number defined above (only for Serial1 and Serial2)
+#if SOC_UART_HP_NUM > 1 && TEST_UART == 1
+HardwareSerial &testingSerial = Serial1;
+#elif SOC_UART_HP_NUM > 2 && TEST_UART == 2
+HardwareSerial &testingSerial = Serial2;
+#endif
+
+// General callback function for any UART -- used with a lambda std::function within HardwareSerial::onReceive()
+void processOnReceiving(HardwareSerial &mySerial) {
+  // detects which Serial# is being used here
+  int8_t uart_num = -1;
+  if (&mySerial == &Serial0) {
+    uart_num = 0;
+#if SOC_UART_HP_NUM > 1
+  } else if (&mySerial == &Serial1) {
+    uart_num = 1;
+#endif
+#if SOC_UART_HP_NUM > 2
+  } else if (&mySerial == &Serial2) {
+    uart_num = 2;
+#endif
+  }
+
+  //Prints some information on the current Serial (UART0 or USB CDC)
+  if (uart_num == -1) {
+    Serial.println("This is not a know Arduino Serial# object...");
+    return;
+  }
+  Serial.printf("\nOnReceive Callback --> Received Data from UART%d\n", uart_num);
+  Serial.printf("Received %d bytes\n", mySerial.available());
+  Serial.printf("First byte is '%c' [0x%02x]\n", mySerial.peek(), mySerial.peek());
+  uint8_t charPerLine = 0;
+  while (mySerial.available()) {
+    char c = mySerial.read();
+    Serial.printf("'%c' [0x%02x] ", c, c);
+    if (++charPerLine == 10) {
+      charPerLine = 0;
+      Serial.println();
+    }
+  }
+}
+
+void setup() {
+  // Serial can be the USB or UART0, depending on the settings and which SoC is used
+  Serial.begin(115200);
+
+  // when data is received from UART0, it will call the general function
+  // passing Serial0 as parameter for processing
+#if TEST_UART == 0
+  Serial0.begin(115200);  // keeps default GPIOs
+  Serial0.onReceive([]() {
+    processOnReceiving(Serial0);
+  });
+#else
+  // and so on for the other UARTs (Serial1 and Serial2)
+  // Rx = 4, Tx = 5 will work for ESP32, S2, S3, C3, C6 and H2
+  testingSerial.begin(115200, SERIAL_8N1, RXPIN, TXPIN);
+  testingSerial.onReceive([]() {
+    processOnReceiving(testingSerial);
+  });
+#endif
+
+  // this helper function will connect TX pin (from TEST_UART number) to its RX pin
+  // creating a loopback that will allow to write to TEST_UART number
+  // and send it to RX with no need to physically connect both pins
+#if TEST_UART > 0
+  uart_internal_loopback(TEST_UART, RXPIN);
+#else
+  // when UART0 is used for testing, it is necessary to send data using the Serial Monitor/Terminal
+  // Data must be sent by the CP2102, manually using  the Serial Monitor/Terminal
+#endif
+
+  delay(500);
+  Serial.printf("\nSend bytes to UART%d in order to\n", TEST_UART);
+  Serial.println("see a single processing function display information about");
+  Serial.println("the received data.\n");
+}
+
+void loop() {
+  // All done by the UART callback functions
+  // just write a random number of bytes into the testing UART
+  char serial_data[24];
+  size_t len = random(sizeof(serial_data) - 1) + 1;  // at least 1 byte will be sent
+  for (uint8_t i = 0; i < len; i++) {
+    serial_data[i] = 'A' + i;
+  }
+
+#if TEST_UART > 0
+  Serial.println("\n\n==================================");
+  Serial.printf("Sending %d bytes to UART%d...\n", len, TEST_UART);
+  testingSerial.write(serial_data, len);
+#else
+  // when UART0 is used for testing, it is necessary to send data using the Serial Monitor/Terminal
+  Serial.println("Use the Serial Monitor/Terminal to send data to UART0");
+#endif
+  Serial.println("pausing for 15 seconds.");
+  delay(15000);
+}
diff --git a/libraries/ESP32/examples/Serial/onReceiveExample/onReceiveExample.ino b/libraries/ESP32/examples/Serial/onReceiveExample/onReceiveExample.ino
new file mode 100644
index 00000000000..fe66b07b875
--- /dev/null
+++ b/libraries/ESP32/examples/Serial/onReceiveExample/onReceiveExample.ino
@@ -0,0 +1,123 @@
+/*
+
+   This Sketch demonstrates how to use onReceive(callbackFunc) with HardwareSerial
+
+   void HardwareSerial::onReceive(OnReceiveCb function, bool onlyOnTimeout = false)
+
+   It is possible to register an UART callback function that will be called
+   every time that UART receives data and an associated interrupt is generated.
+
+   In summary, HardwareSerial::onReceive() works like an RX Interrupt callback, that can be adjusted
+   using HardwareSerial::setRxFIFOFull() and HardwareSerial::setRxTimeout().
+
+   OnReceive will be called, while receiving a stream of data, when every 120 bytes are received (default FIFO Full),
+   which may not help in case that the application needs to get all data at once before processing it.
+   Therefore, a way to make it work is by detecting the end of a stream transmission. This can be based on a protocol
+   or based on timeout with the UART line in idle (no data received - this is the case of this example).
+
+   In some cases, it is necessary to wait for receiving all the data before processing it and parsing the
+   UART input. This example demonstrates a way to create a String with all data received from UART0 and
+   signaling it using a Mutex for another task to process it. This example uses a timeout of 500ms as a way to
+   know when the reception of data has finished.
+
+   The onReceive() callback is called whenever the RX ISR is triggered.
+   It can occur because of two possible events:
+
+   1- UART FIFO FULL: it happens when internal UART FIFO reaches a certain number of bytes.
+      Its full capacity is 127 bytes. The FIFO Full threshold for the interrupt can be changed
+      using HardwareSerial::setRxFIFOFull(uint8_t fifoFull).
+      Default FIFO Full Threshold is set in the UART initialization using HardwareSerial::begin()
+      This will depend on the baud rate used when begin() is executed.
+      For a baud rate of 115200 or lower, it it just 1 byte, mimicking original Arduino UART driver.
+      For a baud rate over 115200 it will be 120 bytes for higher performance.
+      Anyway, it can be changed by the application at any time.
+
+   2- UART RX Timeout: it happens, based on a timeout equivalent to a number of symbols at
+      the current baud rate. If the UART line is idle for this timeout, it will raise an interrupt.
+      This time can be changed by HardwareSerial::setRxTimeout(uint8_t rxTimeout)
+
+   When any of those two interrupts occur, IDF UART driver will copy FIFO data to its internal
+   RingBuffer and then Arduino can read such data. At the same time, Arduino Layer will execute
+   the callback function defined with HardwareSerial::onReceive().
+
+   <bool onlyOnTimeout> parameter (default false) can be used by the application to tell Arduino to
+   only execute the callback when the second event above happens (Rx Timeout). At this time all
+   received data will be available to be read by the Arduino application. But if the number of
+   received bytes is higher than the FIFO space, it will generate an error of FIFO overflow.
+   In order to avoid such problem, the application shall set an appropriate RX buffer size using
+   HardwareSerial::setRxBufferSize(size_t new_size) before executing begin() for the Serial port.
+*/
+
+// this will make UART0 work in any case (using or not USB)
+#if ARDUINO_USB_CDC_ON_BOOT
+#define UART0 Serial0
+#else
+#define UART0 Serial
+#endif
+
+// global variable to keep the results from onReceive()
+String uart_buffer = "";
+// a pause of a half second in the UART transmission is considered the end of transmission.
+const uint32_t communicationTimeout_ms = 500;
+
+// Create a mutex for the access to uart_buffer
+// only one task can read/write it at a certain time
+SemaphoreHandle_t uart_buffer_Mutex = NULL;
+
+// UART_RX_IRQ will be executed as soon as data is received by the UART
+// This is a callback function executed from a high priority
+// task created when onReceive() is used
+void UART0_RX_CB() {
+  // take the mutex, waits forever until loop() finishes its processing
+  if (xSemaphoreTake(uart_buffer_Mutex, portMAX_DELAY)) {
+    uint32_t now = millis();  // tracks timeout
+    while ((millis() - now) < communicationTimeout_ms) {
+      if (UART0.available()) {
+        uart_buffer += (char)UART0.read();
+        now = millis();  // reset the timer
+      }
+    }
+    // releases the mutex for data processing
+    xSemaphoreGive(uart_buffer_Mutex);
+  }
+}
+
+// setup() and loop() are functions executed by a low priority task
+// Therefore, there are 2 tasks running when using onReceive()
+void setup() {
+  UART0.begin(115200);
+
+  // creates a mutex object to control access to uart_buffer
+  uart_buffer_Mutex = xSemaphoreCreateMutex();
+  if (uart_buffer_Mutex == NULL) {
+    log_e("Error creating Mutex. Sketch will fail.");
+    while (true) {
+      UART0.println("Mutex error (NULL). Program halted.");
+      delay(2000);
+    }
+  }
+
+  UART0.onReceive(UART0_RX_CB);  // sets the callback function
+  UART0.println("Send data to UART0 in order to activate the RX callback");
+}
+
+uint32_t counter = 0;
+void loop() {
+  if (uart_buffer.length() > 0) {
+    // signals that the onReceive function shall not change uart_buffer while processing
+    if (xSemaphoreTake(uart_buffer_Mutex, portMAX_DELAY)) {
+      // process the received data from UART0 - example, just print it beside a counter
+      UART0.print("[");
+      UART0.print(counter++);
+      UART0.print("] [");
+      UART0.print(uart_buffer.length());
+      UART0.print(" bytes] ");
+      UART0.println(uart_buffer);
+      uart_buffer = "";  // reset uart_buffer for the next UART reading
+      // releases the mutex for more data to be received
+      xSemaphoreGive(uart_buffer_Mutex);
+    }
+  }
+  UART0.println("Sleeping for 1 second...");
+  delay(1000);
+}
diff --git a/libraries/ESP32/examples/TWAI/TWAIreceive/TWAIreceive.ino b/libraries/ESP32/examples/TWAI/TWAIreceive/TWAIreceive.ino
new file mode 100644
index 00000000000..a1f906e9ba7
--- /dev/null
+++ b/libraries/ESP32/examples/TWAI/TWAIreceive/TWAIreceive.ino
@@ -0,0 +1,128 @@
+/* ESP32 TWAI receive example.
+  Receive messages and sends them over serial.
+
+  Connect a CAN bus transceiver to the RX/TX pins.
+  For example: SN65HVD230
+
+  TWAI_MODE_LISTEN_ONLY is used so that the TWAI controller will not influence the bus.
+
+  The API gives other possible speeds and alerts:
+  https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/twai.html
+
+  Example output from a can bus message:
+  -> Message received
+  -> Message is in Standard Format
+  -> ID: 604
+  -> Byte: 0 = 00, 1 = 0f, 2 = 13, 3 = 02, 4 = 00, 5 = 00, 6 = 08, 7 = 00
+
+  Example output with alerts:
+  -> Alert: A (Bit, Stuff, CRC, Form, ACK) error has occurred on the bus.
+  -> Bus error count: 171
+  -> Alert: The RX queue is full causing a received frame to be lost.
+  -> RX buffered: 4  RX missed: 46 RX overrun 0
+
+  created 05-11-2022 by Stephan Martin (designer2k2)
+*/
+
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
+#include "driver/twai.h"
+
+// Pins used to connect to CAN bus transceiver:
+#define RX_PIN 21
+#define TX_PIN 22
+
+// Interval:
+#define POLLING_RATE_MS 1000
+
+static bool driver_installed = false;
+
+void setup() {
+  // Start Serial:
+  Serial.begin(115200);
+
+  // Initialize configuration structures using macro initializers
+  twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT((gpio_num_t)TX_PIN, (gpio_num_t)RX_PIN, TWAI_MODE_LISTEN_ONLY);
+  twai_timing_config_t t_config = TWAI_TIMING_CONFIG_500KBITS();  //Look in the api-reference for other speed sets.
+  twai_filter_config_t f_config = TWAI_FILTER_CONFIG_ACCEPT_ALL();
+
+  // Install TWAI driver
+  if (twai_driver_install(&g_config, &t_config, &f_config) == ESP_OK) {
+    Serial.println("Driver installed");
+  } else {
+    Serial.println("Failed to install driver");
+    return;
+  }
+
+  // Start TWAI driver
+  if (twai_start() == ESP_OK) {
+    Serial.println("Driver started");
+  } else {
+    Serial.println("Failed to start driver");
+    return;
+  }
+
+  // Reconfigure alerts to detect frame receive, Bus-Off error and RX queue full states
+  uint32_t alerts_to_enable = TWAI_ALERT_RX_DATA | TWAI_ALERT_ERR_PASS | TWAI_ALERT_BUS_ERROR | TWAI_ALERT_RX_QUEUE_FULL;
+  if (twai_reconfigure_alerts(alerts_to_enable, NULL) == ESP_OK) {
+    Serial.println("CAN Alerts reconfigured");
+  } else {
+    Serial.println("Failed to reconfigure alerts");
+    return;
+  }
+
+  // TWAI driver is now successfully installed and started
+  driver_installed = true;
+}
+
+static void handle_rx_message(twai_message_t &message) {
+  // Process received message
+  if (message.extd) {
+    Serial.println("Message is in Extended Format");
+  } else {
+    Serial.println("Message is in Standard Format");
+  }
+  Serial.printf("ID: %lx\nByte:", message.identifier);
+  if (!(message.rtr)) {
+    for (int i = 0; i < message.data_length_code; i++) {
+      Serial.printf(" %d = %02x,", i, message.data[i]);
+    }
+    Serial.println("");
+  }
+}
+
+void loop() {
+  if (!driver_installed) {
+    // Driver not installed
+    delay(1000);
+    return;
+  }
+  // Check if alert happened
+  uint32_t alerts_triggered;
+  twai_read_alerts(&alerts_triggered, pdMS_TO_TICKS(POLLING_RATE_MS));
+  twai_status_info_t twaistatus;
+  twai_get_status_info(&twaistatus);
+
+  // Handle alerts
+  if (alerts_triggered & TWAI_ALERT_ERR_PASS) {
+    Serial.println("Alert: TWAI controller has become error passive.");
+  }
+  if (alerts_triggered & TWAI_ALERT_BUS_ERROR) {
+    Serial.println("Alert: A (Bit, Stuff, CRC, Form, ACK) error has occurred on the bus.");
+    Serial.printf("Bus error count: %lu\n", twaistatus.bus_error_count);
+  }
+  if (alerts_triggered & TWAI_ALERT_RX_QUEUE_FULL) {
+    Serial.println("Alert: The RX queue is full causing a received frame to be lost.");
+    Serial.printf("RX buffered: %lu\t", twaistatus.msgs_to_rx);
+    Serial.printf("RX missed: %lu\t", twaistatus.rx_missed_count);
+    Serial.printf("RX overrun %lu\n", twaistatus.rx_overrun_count);
+  }
+
+  // Check if message is received
+  if (alerts_triggered & TWAI_ALERT_RX_DATA) {
+    // One or more messages received. Handle all.
+    twai_message_t message;
+    while (twai_receive(&message, 0) == ESP_OK) {
+      handle_rx_message(message);
+    }
+  }
+}
diff --git a/libraries/ESP32/examples/TWAI/TWAItransmit/TWAItransmit.ino b/libraries/ESP32/examples/TWAI/TWAItransmit/TWAItransmit.ino
new file mode 100644
index 00000000000..1c65bcc2d3e
--- /dev/null
+++ b/libraries/ESP32/examples/TWAI/TWAItransmit/TWAItransmit.ino
@@ -0,0 +1,122 @@
+/* ESP32 TWAI transmit example.
+  This transmits a message every second.
+
+  Connect a CAN bus transceiver to the RX/TX pins.
+  For example: SN65HVD230
+
+  The API gives other possible speeds and alerts:
+  https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/twai.html
+
+  created 27-06-2023 by Stephan Martin (designer2k2)
+*/
+
+#include "driver/twai.h"
+
+// Pins used to connect to CAN bus transceiver:
+#define RX_PIN 21
+#define TX_PIN 22
+
+// Interval:
+#define TRANSMIT_RATE_MS 1000
+
+#define POLLING_RATE_MS 1000
+
+static bool driver_installed = false;
+
+unsigned long previousMillis = 0;  // will store last time a message was send
+
+void setup() {
+  // Start Serial:
+  Serial.begin(115200);
+
+  // Initialize configuration structures using macro initializers
+  twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT((gpio_num_t)TX_PIN, (gpio_num_t)RX_PIN, TWAI_MODE_NORMAL);
+  twai_timing_config_t t_config = TWAI_TIMING_CONFIG_500KBITS();  //Look in the api-reference for other speed sets.
+  twai_filter_config_t f_config = TWAI_FILTER_CONFIG_ACCEPT_ALL();
+
+  // Install TWAI driver
+  if (twai_driver_install(&g_config, &t_config, &f_config) == ESP_OK) {
+    Serial.println("Driver installed");
+  } else {
+    Serial.println("Failed to install driver");
+    return;
+  }
+
+  // Start TWAI driver
+  if (twai_start() == ESP_OK) {
+    Serial.println("Driver started");
+  } else {
+    Serial.println("Failed to start driver");
+    return;
+  }
+
+  // Reconfigure alerts to detect TX alerts and Bus-Off errors
+  uint32_t alerts_to_enable = TWAI_ALERT_TX_IDLE | TWAI_ALERT_TX_SUCCESS | TWAI_ALERT_TX_FAILED | TWAI_ALERT_ERR_PASS | TWAI_ALERT_BUS_ERROR;
+  if (twai_reconfigure_alerts(alerts_to_enable, NULL) == ESP_OK) {
+    Serial.println("CAN Alerts reconfigured");
+  } else {
+    Serial.println("Failed to reconfigure alerts");
+    return;
+  }
+
+  // TWAI driver is now successfully installed and started
+  driver_installed = true;
+}
+
+static void send_message() {
+  // Send message
+
+  // Configure message to transmit
+  twai_message_t message;
+  message.identifier = 0x0F6;
+  message.data_length_code = 4;
+  for (int i = 0; i < 4; i++) {
+    message.data[i] = 0;
+  }
+
+  // Queue message for transmission
+  if (twai_transmit(&message, pdMS_TO_TICKS(1000)) == ESP_OK) {
+    printf("Message queued for transmission\n");
+  } else {
+    printf("Failed to queue message for transmission\n");
+  }
+}
+
+void loop() {
+  if (!driver_installed) {
+    // Driver not installed
+    delay(1000);
+    return;
+  }
+  // Check if alert happened
+  uint32_t alerts_triggered;
+  twai_read_alerts(&alerts_triggered, pdMS_TO_TICKS(POLLING_RATE_MS));
+  twai_status_info_t twaistatus;
+  twai_get_status_info(&twaistatus);
+
+  // Handle alerts
+  if (alerts_triggered & TWAI_ALERT_ERR_PASS) {
+    Serial.println("Alert: TWAI controller has become error passive.");
+  }
+  if (alerts_triggered & TWAI_ALERT_BUS_ERROR) {
+    Serial.println("Alert: A (Bit, Stuff, CRC, Form, ACK) error has occurred on the bus.");
+    Serial.printf("Bus error count: %lu\n", twaistatus.bus_error_count);
+  }
+  if (alerts_triggered & TWAI_ALERT_TX_FAILED) {
+    Serial.println("Alert: The Transmission failed.");
+    Serial.printf("TX buffered: %lu\t", twaistatus.msgs_to_tx);
+    Serial.printf("TX error: %lu\t", twaistatus.tx_error_counter);
+    Serial.printf("TX failed: %lu\n", twaistatus.tx_failed_count);
+  }
+  if (alerts_triggered & TWAI_ALERT_TX_SUCCESS) {
+    Serial.println("Alert: The Transmission was successful.");
+    Serial.printf("TX buffered: %lu\t", twaistatus.msgs_to_tx);
+  }
+
+  // Send message
+  unsigned long currentMillis = millis();
+  if (currentMillis - previousMillis >= TRANSMIT_RATE_MS) {
+    previousMillis = currentMillis;
+    send_message();
+  }
+}
diff --git a/libraries/ESP32/examples/Template/ExampleTemplate/ExampleTemplate.ino b/libraries/ESP32/examples/Template/ExampleTemplate/ExampleTemplate.ino
new file mode 100644
index 00000000000..6d87de556b0
--- /dev/null
+++ b/libraries/ESP32/examples/Template/ExampleTemplate/ExampleTemplate.ino
@@ -0,0 +1,12 @@
+/* Arduino Example Template
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+
+void setup() {}
+
+void loop() {}
diff --git a/libraries/ESP32/examples/Template/ExampleTemplate/README.md b/libraries/ESP32/examples/Template/ExampleTemplate/README.md
new file mode 100644
index 00000000000..91b50967e9e
--- /dev/null
+++ b/libraries/ESP32/examples/Template/ExampleTemplate/README.md
@@ -0,0 +1,119 @@
+# Arduino-ESP32 Example/Library Name ==(REQUIRED)==
+
+==*Add a brief description of this example/library here!*==
+
+This example/library demonstrates how to create a new example README file.
+
+# Supported Targets ==(REQUIRED)==
+
+==*Add the supported devices here!*==
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 |
+| ----------------- | ----- | -------- | -------- |
+
+## How to Use Example/Library ==(OPTIONAL)==
+
+==*Add a brief description of how to use this example.*==
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+### Hardware Connection ==(OPTIONAL)==
+
+==*Add a brief description of wiring or any other hardware-specific connection.*==
+
+To use this example, you need to connect the LED to the `GPIOx`.
+
+SDCard GPIO connection scheme:
+
+| SDCard Pin  | Function | GPIO   |
+| ----------- | -------- | ------ |
+| 1           | CS       | GPIO5  |
+| 2           | DI/MOSI  | GPIO23 |
+| 3           | VSS/GND  | GND    |
+| 4           | VDD/3V3  | 3V3    |
+| 5           | SCLK     | GPIO18 |
+| 6           | VSS/GND  | GND    |
+| 7           | DO/MISO  | GPIO19 |
+
+To add images, please create a folder `_asset` inside the example folder to add the relevant images.
+
+### Configure the Project ==(OPTIONAL)==
+
+==*Add a brief description of this example here!*==
+
+Set the LED GPIO by changing the `LED_BUILTIN` value in the function `pinMode(LED_BUILTIN, OUTPUT);`. By default, the GPIO is: `GPIOx`.
+
+#### Example for the GPIO4:
+
+==*Add some code explanation if relevant to the example.*==
+
+```cpp
+// the setup function runs once when you press reset or power the board
+void setup() {
+// initialize digital pin 4 as an output.
+pinMode(4, OUTPUT);
+}
+```
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example/Log Output ==(OPTIONAL)==
+
+==*Add the log/serial output here!*==
+
+```
+ets Jul 29 2019 12:21:46
+
+rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
+configsip: 0, SPIWP:0xee
+clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
+mode:DIO, clock div:1
+load:0x3fff0030,len:1412
+load:0x40078000,len:13400
+load:0x40080400,len:3672
+entry 0x400805f8
+ESP32 Chip model = ESP32-D0WDQ5 Rev 3
+This chip has 2 cores
+Chip ID: 3957392
+```
+
+## Troubleshooting ==(REQUIRED)==
+
+==*Add specific issues you may find by using this example here!*==
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute ==(REQUIRED)==
+
+==*Do not change! Keep it as is.*==
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources ==(REQUIRED)==
+
+==*Do not change here! Keep it as is or add only relevant documents/info for this example. Do not add any purchase link/marketing stuff*==
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/ESP32/examples/Time/SimpleTime/SimpleTime.ino b/libraries/ESP32/examples/Time/SimpleTime/SimpleTime.ino
index 988c2a4d83b..d82e5f2977d 100644
--- a/libraries/ESP32/examples/Time/SimpleTime/SimpleTime.ino
+++ b/libraries/ESP32/examples/Time/SimpleTime/SimpleTime.ino
@@ -1,47 +1,74 @@
 #include <WiFi.h>
 #include "time.h"
+#include "esp_sntp.h"
 
-const char* ssid       = "YOUR_SSID";
-const char* password   = "YOUR_PASS";
+const char *ssid = "YOUR_SSID";
+const char *password = "YOUR_PASS";
 
-const char* ntpServer = "pool.ntp.org";
-const long  gmtOffset_sec = 3600;
-const int   daylightOffset_sec = 3600;
+const char *ntpServer1 = "pool.ntp.org";
+const char *ntpServer2 = "time.nist.gov";
+const long gmtOffset_sec = 3600;
+const int daylightOffset_sec = 3600;
 
-void printLocalTime()
-{
+const char *time_zone = "CET-1CEST,M3.5.0,M10.5.0/3";  // TimeZone rule for Europe/Rome including daylight adjustment rules (optional)
+
+void printLocalTime() {
   struct tm timeinfo;
-  if(!getLocalTime(&timeinfo)){
-    Serial.println("Failed to obtain time");
+  if (!getLocalTime(&timeinfo)) {
+    Serial.println("No time available (yet)");
     return;
   }
   Serial.println(&timeinfo, "%A, %B %d %Y %H:%M:%S");
 }
 
-void setup()
-{
+// Callback function (gets called when time adjusts via NTP)
+void timeavailable(struct timeval *t) {
+  Serial.println("Got time adjustment from NTP!");
+  printLocalTime();
+}
+
+void setup() {
   Serial.begin(115200);
-  
-  //connect to WiFi
+
+  // First step is to configure WiFi STA and connect in order to get the current time and date.
   Serial.printf("Connecting to %s ", ssid);
   WiFi.begin(ssid, password);
+
+  /**
+   * NTP server address could be acquired via DHCP,
+   *
+   * NOTE: This call should be made BEFORE esp32 acquires IP address via DHCP,
+   * otherwise SNTP option 42 would be rejected by default.
+   * NOTE: configTime() function call if made AFTER DHCP-client run
+   * will OVERRIDE acquired NTP server address
+   */
+  esp_sntp_servermode_dhcp(1);  // (optional)
+
   while (WiFi.status() != WL_CONNECTED) {
-      delay(500);
-      Serial.print(".");
+    delay(500);
+    Serial.print(".");
   }
   Serial.println(" CONNECTED");
-  
-  //init and get the time
-  configTime(gmtOffset_sec, daylightOffset_sec, ntpServer);
-  printLocalTime();
 
-  //disconnect WiFi as it's no longer needed
-  WiFi.disconnect(true);
-  WiFi.mode(WIFI_OFF);
+  // set notification call-back function
+  sntp_set_time_sync_notification_cb(timeavailable);
+
+  /**
+   * This will set configured ntp servers and constant TimeZone/daylightOffset
+   * should be OK if your time zone does not need to adjust daylightOffset twice a year,
+   * in such a case time adjustment won't be handled automagically.
+   */
+  configTime(gmtOffset_sec, daylightOffset_sec, ntpServer1, ntpServer2);
+
+  /**
+   * A more convenient approach to handle TimeZones with daylightOffset
+   * would be to specify a environment variable with TimeZone definition including daylight adjustmnet rules.
+   * A list of rules for your zone could be obtained from https://github.com/esp8266/Arduino/blob/master/cores/esp8266/TZ.h
+   */
+  //configTzTime(time_zone, ntpServer1, ntpServer2);
 }
 
-void loop()
-{
-  delay(1000);
-  printLocalTime();
+void loop() {
+  delay(5000);
+  printLocalTime();  // it will take some time to sync time :)
 }
diff --git a/libraries/ESP32/examples/Time/SimpleTime/ci.json b/libraries/ESP32/examples/Time/SimpleTime/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/ESP32/examples/Time/SimpleTime/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/ESP32/examples/Timer/RepeatTimer/RepeatTimer.ino b/libraries/ESP32/examples/Timer/RepeatTimer/RepeatTimer.ino
index 5efef9cec4f..e4ef7bc865b 100644
--- a/libraries/ESP32/examples/Timer/RepeatTimer/RepeatTimer.ino
+++ b/libraries/ESP32/examples/Timer/RepeatTimer/RepeatTimer.ino
@@ -9,19 +9,19 @@
  */
 
 // Stop button is attached to PIN 0 (IO0)
-#define BTN_STOP_ALARM    0
+#define BTN_STOP_ALARM 0
 
-hw_timer_t * timer = NULL;
+hw_timer_t *timer = NULL;
 volatile SemaphoreHandle_t timerSemaphore;
 portMUX_TYPE timerMux = portMUX_INITIALIZER_UNLOCKED;
 
 volatile uint32_t isrCounter = 0;
 volatile uint32_t lastIsrAt = 0;
 
-void IRAM_ATTR onTimer(){
+void ARDUINO_ISR_ATTR onTimer() {
   // Increment the counter and set the time of ISR
   portENTER_CRITICAL_ISR(&timerMux);
-  isrCounter++;
+  isrCounter = isrCounter + 1;
   lastIsrAt = millis();
   portEXIT_CRITICAL_ISR(&timerMux);
   // Give a semaphore that we can check in the loop
@@ -33,30 +33,25 @@ void setup() {
   Serial.begin(115200);
 
   // Set BTN_STOP_ALARM to input mode
-  pinMode(BTN_STOP_ALARM, INPUT);
+  pinMode(BTN_STOP_ALARM, INPUT_PULLUP);
 
   // Create semaphore to inform us when the timer has fired
   timerSemaphore = xSemaphoreCreateBinary();
 
-  // Use 1st timer of 4 (counted from zero).
-  // Set 80 divider for prescaler (see ESP32 Technical Reference Manual for more
-  // info).
-  timer = timerBegin(0, 80, true);
+  // Set timer frequency to 1Mhz
+  timer = timerBegin(1000000);
 
   // Attach onTimer function to our timer.
-  timerAttachInterrupt(timer, &onTimer, true);
+  timerAttachInterrupt(timer, &onTimer);
 
   // Set alarm to call onTimer function every second (value in microseconds).
-  // Repeat the alarm (third parameter)
-  timerAlarmWrite(timer, 1000000, true);
-
-  // Start an alarm
-  timerAlarmEnable(timer);
+  // Repeat the alarm (third parameter) with unlimited count = 0 (fourth parameter).
+  timerAlarm(timer, 1000000, true, 0);
 }
 
 void loop() {
   // If Timer has fired
-  if (xSemaphoreTake(timerSemaphore, 0) == pdTRUE){
+  if (xSemaphoreTake(timerSemaphore, 0) == pdTRUE) {
     uint32_t isrCount = 0, isrTime = 0;
     // Read the interrupt count and time
     portENTER_CRITICAL(&timerMux);
diff --git a/libraries/ESP32/examples/Timer/WatchdogTimer/WatchdogTimer.ino b/libraries/ESP32/examples/Timer/WatchdogTimer/WatchdogTimer.ino
index 056cab9640c..d7c9a38eb71 100644
--- a/libraries/ESP32/examples/Timer/WatchdogTimer/WatchdogTimer.ino
+++ b/libraries/ESP32/examples/Timer/WatchdogTimer/WatchdogTimer.ino
@@ -1,10 +1,11 @@
 #include "esp_system.h"
+#include "rom/ets_sys.h"
 
 const int button = 0;         //gpio to use to trigger delay
 const int wdtTimeout = 3000;  //time in ms to trigger the watchdog
 hw_timer_t *timer = NULL;
 
-void IRAM_ATTR resetModule() {
+void ARDUINO_ISR_ATTR resetModule() {
   ets_printf("reboot\n");
   esp_restart();
 }
@@ -14,26 +15,25 @@ void setup() {
   Serial.println();
   Serial.println("running setup");
 
-  pinMode(button, INPUT_PULLUP);                    //init control pin
-  timer = timerBegin(0, 80, true);                  //timer 0, div 80
-  timerAttachInterrupt(timer, &resetModule, true);  //attach callback
-  timerAlarmWrite(timer, wdtTimeout * 1000, false); //set time in us
-  timerAlarmEnable(timer);                          //enable interrupt
+  pinMode(button, INPUT_PULLUP);                   //init control pin
+  timer = timerBegin(1000000);                     //timer 1Mhz resolution
+  timerAttachInterrupt(timer, &resetModule);       //attach callback
+  timerAlarm(timer, wdtTimeout * 1000, false, 0);  //set time in us
 }
 
 void loop() {
   Serial.println("running main loop");
 
-  timerWrite(timer, 0); //reset timer (feed watchdog)
+  timerWrite(timer, 0);  //reset timer (feed watchdog)
   long loopTime = millis();
   //while button is pressed, delay up to 3 seconds to trigger the timer
   while (!digitalRead(button)) {
     Serial.println("button pressed");
     delay(500);
   }
-  delay(1000); //simulate work
+  delay(1000);  //simulate work
   loopTime = millis() - loopTime;
-  
+
   Serial.print("loop time is = ");
-  Serial.println(loopTime); //should be under 3000
+  Serial.println(loopTime);  //should be under 3000
 }
diff --git a/libraries/ESP32/examples/Touch/TouchButton/TouchButton.ino b/libraries/ESP32/examples/Touch/TouchButton/TouchButton.ino
new file mode 100644
index 00000000000..43f3bc36592
--- /dev/null
+++ b/libraries/ESP32/examples/Touch/TouchButton/TouchButton.ino
@@ -0,0 +1,46 @@
+/*
+
+This is an example how to use Touch Intrrerupts
+The sketch will tell when it is touched and then released as like a push-button
+
+This method based on touchInterruptSetThresholdDirection() is only available for ESP32
+*/
+
+#include "Arduino.h"
+
+int threshold = 40;
+bool touchActive = false;
+bool lastTouchActive = false;
+bool testingLower = true;
+
+void gotTouchEvent() {
+  if (lastTouchActive != testingLower) {
+    touchActive = !touchActive;
+    testingLower = !testingLower;
+    // Touch ISR will be inverted: Lower <--> Higher than the Threshold after ISR event is noticed
+    touchInterruptSetThresholdDirection(testingLower);
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  delay(1000);  // give me time to bring up serial monitor
+  Serial.println("ESP32 Touch Interrupt Test");
+  touchAttachInterrupt(T2, gotTouchEvent, threshold);
+
+  // Touch ISR will be activated when touchRead is lower than the Threshold
+  touchInterruptSetThresholdDirection(testingLower);
+}
+
+void loop() {
+  if (lastTouchActive != touchActive) {
+    lastTouchActive = touchActive;
+    if (touchActive) {
+      Serial.println("  ---- Touch was Pressed");
+    } else {
+      Serial.println("  ---- Touch was Released");
+    }
+  }
+  Serial.printf("T2 pin2 = %d \n", touchRead(T2));
+  delay(125);
+}
diff --git a/libraries/ESP32/examples/Touch/TouchButton/ci.json b/libraries/ESP32/examples/Touch/TouchButton/ci.json
new file mode 100644
index 00000000000..cec76a84f9d
--- /dev/null
+++ b/libraries/ESP32/examples/Touch/TouchButton/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_TOUCH_VERSION_1=y"
+  ]
+}
diff --git a/libraries/ESP32/examples/Touch/TouchButtonV2/TouchButtonV2.ino b/libraries/ESP32/examples/Touch/TouchButtonV2/TouchButtonV2.ino
new file mode 100644
index 00000000000..df9b3f41149
--- /dev/null
+++ b/libraries/ESP32/examples/Touch/TouchButtonV2/TouchButtonV2.ino
@@ -0,0 +1,51 @@
+/*
+
+This is an example how to use Touch Intrrerupts
+The sketch will tell when it is touched and then released as like a push-button
+
+This method based on touchInterruptGetLastStatus() is only available for ESP32 S2 and S3
+*/
+
+#include "Arduino.h"
+
+int threshold = 1500;  // ESP32S2
+bool touch1detected = false;
+bool touch2detected = false;
+
+void gotTouch1() {
+  touch1detected = true;
+}
+
+void gotTouch2() {
+  touch2detected = true;
+}
+
+void setup() {
+  Serial.begin(115200);
+  delay(1000);  // give me time to bring up serial monitor
+
+  Serial.println("\n ESP32 Touch Interrupt Test\n");
+  touchAttachInterrupt(T1, gotTouch1, threshold);
+  touchAttachInterrupt(T2, gotTouch2, threshold);
+}
+
+void loop() {
+  if (touch1detected) {
+    touch1detected = false;
+    if (touchInterruptGetLastStatus(T1)) {
+      Serial.println(" --- T1 Touched");
+    } else {
+      Serial.println(" --- T1 Released");
+    }
+  }
+  if (touch2detected) {
+    touch2detected = false;
+    if (touchInterruptGetLastStatus(T2)) {
+      Serial.println(" --- T2 Touched");
+    } else {
+      Serial.println(" --- T2 Released");
+    }
+  }
+
+  delay(80);
+}
diff --git a/libraries/ESP32/examples/Touch/TouchButtonV2/ci.json b/libraries/ESP32/examples/Touch/TouchButtonV2/ci.json
new file mode 100644
index 00000000000..2710fa7940e
--- /dev/null
+++ b/libraries/ESP32/examples/Touch/TouchButtonV2/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_TOUCH_VERSION_2=y"
+  ]
+}
diff --git a/libraries/ESP32/examples/Touch/TouchInterrupt/TouchInterrupt.ino b/libraries/ESP32/examples/Touch/TouchInterrupt/TouchInterrupt.ino
index 8f40382ca56..3b4e5f0b9e9 100644
--- a/libraries/ESP32/examples/Touch/TouchInterrupt/TouchInterrupt.ino
+++ b/libraries/ESP32/examples/Touch/TouchInterrupt/TouchInterrupt.ino
@@ -1,34 +1,39 @@
 /*
-This is un example howto use Touch Intrrerupts
+This is an example how to use Touch Intrrerupts
 The bigger the threshold, the more sensible is the touch
 */
 
+#if CONFIG_IDF_TARGET_ESP32P4
+int threshold = 0;  // when 0 is used, the benchmarked value will be used
+#else
 int threshold = 40;
+#endif
+
 bool touch1detected = false;
 bool touch2detected = false;
 
-void gotTouch1(){
- touch1detected = true;
+void gotTouch1() {
+  touch1detected = true;
 }
 
-void gotTouch2(){
- touch2detected = true;
+void gotTouch2() {
+  touch2detected = true;
 }
 
 void setup() {
   Serial.begin(115200);
-  delay(1000); // give me time to bring up serial monitor
+  delay(1000);  // give me time to bring up serial monitor
   Serial.println("ESP32 Touch Interrupt Test");
   touchAttachInterrupt(T2, gotTouch1, threshold);
   touchAttachInterrupt(T3, gotTouch2, threshold);
 }
 
-void loop(){
-  if(touch1detected){
+void loop() {
+  if (touch1detected) {
     touch1detected = false;
     Serial.println("Touch 1 detected");
   }
-  if(touch2detected){
+  if (touch2detected) {
     touch2detected = false;
     Serial.println("Touch 2 detected");
   }
diff --git a/libraries/ESP32/examples/Touch/TouchInterrupt/ci.json b/libraries/ESP32/examples/Touch/TouchInterrupt/ci.json
new file mode 100644
index 00000000000..c0ecf9fc0a5
--- /dev/null
+++ b/libraries/ESP32/examples/Touch/TouchInterrupt/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP32/examples/Touch/TouchRead/TouchRead.ino b/libraries/ESP32/examples/Touch/TouchRead/TouchRead.ino
index e217fc196d5..8e93ba44691 100644
--- a/libraries/ESP32/examples/Touch/TouchRead/TouchRead.ino
+++ b/libraries/ESP32/examples/Touch/TouchRead/TouchRead.ino
@@ -1,15 +1,13 @@
 // ESP32 Touch Test
 // Just test touch pin - Touch0 is T0 which is on GPIO 4.
 
-void setup()
-{
+void setup() {
   Serial.begin(115200);
-  delay(1000); // give me time to bring up serial monitor
+  delay(1000);  // give me time to bring up serial monitor
   Serial.println("ESP32 Touch Test");
 }
 
-void loop()
-{
-  Serial.println(touchRead(T0));  // get value using T0
+void loop() {
+  Serial.println(touchRead(T1));  // get value using T0
   delay(1000);
 }
diff --git a/libraries/ESP32/examples/Touch/TouchRead/ci.json b/libraries/ESP32/examples/Touch/TouchRead/ci.json
new file mode 100644
index 00000000000..c0ecf9fc0a5
--- /dev/null
+++ b/libraries/ESP32/examples/Touch/TouchRead/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP32/examples/Utilities/HEXBuilder/HEXBuilder.ino b/libraries/ESP32/examples/Utilities/HEXBuilder/HEXBuilder.ino
new file mode 100644
index 00000000000..f580a763b54
--- /dev/null
+++ b/libraries/ESP32/examples/Utilities/HEXBuilder/HEXBuilder.ino
@@ -0,0 +1,77 @@
+#include <HEXBuilder.h>
+
+void setup() {
+  Serial.begin(115200);
+
+  Serial.println("\n\n\nStart.");
+
+  // Convert a HEX string like 6c6c6f20576f726c64 to a binary buffer
+  {
+    const char *out = "Hello World";
+    const char *hexin = "48656c6c6f20576f726c6400";  // As the string above is \0 terminated too
+
+    unsigned char buff[256];
+    size_t len = HEXBuilder::hex2bytes(buff, sizeof(buff), hexin);
+
+    if (len != 1 + strlen(out)) {
+      Serial.println("Odd - length 1 is wrong");
+    }
+
+    if (memcmp(buff, out, len) != 0) {
+      Serial.println("Odd - decode 1 went wrong");
+    }
+
+    // Safe to print this binary buffer -- as we've included a \0 in the hex sequence.
+    Serial.printf("IN: <%s>\nOUT <%s\\0>\n", hexin, buff);
+  };
+
+  {
+    String helloHEX = "48656c6c6f20576f726c64";
+    const char hello[] = "Hello World";
+
+    unsigned char buff[256];
+    size_t len = HEXBuilder::hex2bytes(buff, sizeof(buff), helloHEX);
+
+    if (len != strlen(hello)) {
+      Serial.println("Odd - length 2 is wrong");
+    }
+
+    if (strcmp((char *)buff, hello) != 0) {
+      Serial.println("Odd - decode 2 went wrong");
+    }
+  }
+
+  {
+    const unsigned char helloBytes[] = {0x48, 0x56, 0x6c, 0x6c, 0x6f, 0x20, 0x57, 0x6f, 0x72, 0x6c, 0x64};
+    String helloHEX = "48566c6c6f20576f726c64";
+
+    String out = HEXBuilder::bytes2hex(helloBytes, sizeof(helloBytes));
+    if (out.length() != 2 * sizeof(helloBytes)) {
+      Serial.println("Odd - length 3 is wrong");
+    }
+
+    // we need to ignore case - as a hex string can be spelled in uppercase and lowercase
+    if (!out.equalsIgnoreCase(helloHEX)) {
+      Serial.println("Odd - decode 3 went wrong");
+    }
+  }
+
+  {
+    const unsigned char helloBytes[] = {0x6c, 0x6c, 0x6f, 0x20, 0x57, 0x6f, 0x72, 0x6c, 0x64};
+    const char helloHex[] = "6c6c6f20576f726c64";
+
+    char buff[256];
+    size_t len = HEXBuilder::bytes2hex(buff, sizeof(buff), helloBytes, sizeof(helloBytes));
+    if (len != 1 + 2 * sizeof(helloBytes)) {
+      Serial.println("Odd - length 4 is wrong");
+    }
+
+    // we need to ignore case - as a hex string can be spelled in uppercase and lowercase
+    if (strcasecmp(buff, helloHex)) {
+      Serial.println("Odd - decode 4 went wrong");
+    }
+  }
+  Serial.println("Done.");
+}
+
+void loop() {}
diff --git a/libraries/ESP32/examples/Utilities/MD5Builder/MD5Builder.ino b/libraries/ESP32/examples/Utilities/MD5Builder/MD5Builder.ino
new file mode 100644
index 00000000000..cb1b350d834
--- /dev/null
+++ b/libraries/ESP32/examples/Utilities/MD5Builder/MD5Builder.ino
@@ -0,0 +1,95 @@
+#include <MD5Builder.h>
+
+// Occasionally it is useful to compare a password that the user
+// has entered to a build in string. However this means that the
+// password ends up `in the clear' in the firmware and in your
+// source code.
+//
+// MD5Builder helps you obfuscate this (it is not terribly secure, MD5
+// has been phased out as insecure eons ago) by letting you create an
+// MD5 of the data the user entered; and then compare this to an MD5
+// string that you have put in your code.
+
+void setup() {
+  Serial.begin(115200);
+
+  Serial.println("\n\n\nStart.");
+
+  // Check if a password obfuscated in an MD5 actually
+  // matches the original string.
+  //
+  // echo -n "Hello World" | openssl md5
+  {
+    String md5 = "b10a8db164e0754105b7a99be72e3fe5";
+    String password = "Hello World";
+
+    MD5Builder md;
+
+    md.begin();
+    md.add(password);
+    md.calculate();
+
+    String result = md.toString();
+
+    if (!md5.equalsIgnoreCase(result)) {
+      Serial.println("Odd - failing MD5 on String");
+    } else {
+      Serial.println("OK!");
+    }
+  }
+
+  // Check that this also work if we add the password not as
+  // a normal string - but as a string with the HEX values.
+  {
+    String passwordAsHex = "48656c6c6f20576f726c64";
+    String md5 = "b10a8db164e0754105b7a99be72e3fe5";
+
+    MD5Builder md;
+
+    md.begin();
+    md.addHexString(passwordAsHex);
+    md.calculate();
+
+    String result = md.toString();
+
+    if (!md5.equalsIgnoreCase(result)) {
+      Serial.println("Odd - failing MD5 on hex string");
+      Serial.println(md5);
+      Serial.println(result);
+    } else {
+      Serial.println("OK!");
+    }
+  }
+
+  // Check that this also work if we add the password as
+  // an unsigned byte array.
+  {
+    uint8_t password[] = {0x48, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x57, 0x6f, 0x72, 0x6c, 0x64};
+    String md5 = "b10a8db164e0754105b7a99be72e3fe5";
+    MD5Builder md;
+
+    md.begin();
+    md.add(password, sizeof(password));
+    md.calculate();
+
+    String result = md.toString();
+
+    if (!md5.equalsIgnoreCase(result)) {
+      Serial.println("Odd - failing MD5 on byte array");
+    } else {
+      Serial.println("OK!");
+    }
+
+    // And also check that we can compare this as pure, raw, bytes
+    uint8_t raw[16] = {0xb1, 0x0a, 0x8d, 0xb1, 0x64, 0xe0, 0x75, 0x41, 0x05, 0xb7, 0xa9, 0x9b, 0xe7, 0x2e, 0x3f, 0xe5};
+    uint8_t res[16];
+    md.getBytes(res);
+    if (memcmp(raw, res, 16)) {
+      Serial.println("Odd - failing MD5 on byte array when compared as bytes");
+    } else {
+      Serial.println("OK!");
+    }
+  }
+}
+
+void loop() {}
diff --git a/libraries/ESP32/examples/Utilities/SHA1Builder/SHA1Builder.ino b/libraries/ESP32/examples/Utilities/SHA1Builder/SHA1Builder.ino
new file mode 100644
index 00000000000..251307c4016
--- /dev/null
+++ b/libraries/ESP32/examples/Utilities/SHA1Builder/SHA1Builder.ino
@@ -0,0 +1,96 @@
+#include <SHA1Builder.h>
+
+// Occasionally it is useful to compare a password that the user
+// has entered to a build in string. However this means that the
+// password ends up `in the clear' in the firmware and in your
+// source code.
+//
+// SHA1Builder helps you obfuscate this (This is not much more secure.
+// SHA1 is past its retirement age and long obsolete/insecure, but it helps
+// a little) by letting you create an (unsalted!) SHA1 of the data the
+// user entered; and then compare this to an SHA1 string that you have put
+// in your code.
+
+void setup() {
+  Serial.begin(115200);
+
+  Serial.println("\n\n\nStart.");
+
+  // Check if a password obfuscated in an SHA1 actually
+  // matches the original string.
+  //
+  // echo -n "Hello World" | openssl sha1
+  {
+    String sha1_str = "0a4d55a8d778e5022fab701977c5d840bbc486d0";
+    String password = "Hello World";
+
+    SHA1Builder sha;
+
+    sha.begin();
+    sha.add(password);
+    sha.calculate();
+
+    String result = sha.toString();
+
+    if (!sha1_str.equalsIgnoreCase(result)) {
+      Serial.println("Odd - failing SHA1 on String");
+    } else {
+      Serial.println("OK!");
+    }
+  }
+
+  // Check that this also work if we add the password not as
+  // a normal string - but as a string with the HEX values.
+  {
+    String passwordAsHex = "48656c6c6f20576f726c64";
+    String sha1_str = "0a4d55a8d778e5022fab701977c5d840bbc486d0";
+
+    SHA1Builder sha;
+
+    sha.begin();
+    sha.addHexString(passwordAsHex);
+    sha.calculate();
+
+    String result = sha.toString();
+
+    if (!sha1_str.equalsIgnoreCase(result)) {
+      Serial.println("Odd - failing SHA1 on hex string");
+      Serial.println(sha1_str);
+      Serial.println(result);
+    } else {
+      Serial.println("OK!");
+    }
+  }
+
+  // Check that this also work if we add the password as
+  // an unsigned byte array.
+  {
+    uint8_t password[] = {0x48, 0x65, 0x6c, 0x6c, 0x6f, 0x20, 0x57, 0x6f, 0x72, 0x6c, 0x64};
+    String sha1_str = "0a4d55a8d778e5022fab701977c5d840bbc486d0";
+    SHA1Builder sha;
+
+    sha.begin();
+    sha.add(password, sizeof(password));
+    sha.calculate();
+
+    String result = sha.toString();
+
+    if (!sha1_str.equalsIgnoreCase(result)) {
+      Serial.println("Odd - failing SHA1 on byte array");
+    } else {
+      Serial.println("OK!");
+    }
+
+    // And also check that we can compare this as pure, raw, bytes
+    uint8_t raw[20] = {0x0a, 0x4d, 0x55, 0xa8, 0xd7, 0x78, 0xe5, 0x02, 0x2f, 0xab, 0x70, 0x19, 0x77, 0xc5, 0xd8, 0x40, 0xbb, 0xc4, 0x86, 0xd0};
+    uint8_t res[20];
+    sha.getBytes(res);
+    if (memcmp(raw, res, 20)) {
+      Serial.println("Odd - failing SHA1 on byte array when compared as bytes");
+    } else {
+      Serial.println("OK!");
+    }
+  }
+}
+
+void loop() {}
diff --git a/libraries/ESP32/keywords.txt b/libraries/ESP32/keywords.txt
new file mode 100644
index 00000000000..866e76babd8
--- /dev/null
+++ b/libraries/ESP32/keywords.txt
@@ -0,0 +1,55 @@
+#######################################
+# Syntax Coloring Map
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+Serial4	KEYWORD1
+espCtColor_t	KEYWORD1
+espXyColor_t	KEYWORD1
+espHsvColor_t	KEYWORD1
+espRgbColor_t	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+espXYToRgbColor	KEYWORD2
+espXYColorToRgb	KEYWORD2
+espRgbColorToXYColor	KEYWORD2
+espRgbToXYColor	KEYWORD2
+espHsvColorToRgbColor	KEYWORD2
+espHsvToRgbColor	KEYWORD2
+espCTColorToRgbColor	KEYWORD2
+espCTToRgbColor	KEYWORD2
+espRgbColorToHsvColor	KEYWORD2
+espRgbToHsvColor	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+
+RGB_BUILTIN	LITERAL1
+HSV_BLACK	LITERAL1
+HSV_WHITE	LITERAL1
+HSV_RED	LITERAL1
+HSV_YELLOW	LITERAL1
+HSV_GREEN	LITERAL1
+HSV_CYAN	LITERAL1
+HSV_BLUE	LITERAL1
+HSV_MAGENTA	LITERAL1
+COOL_WHITE_COLOR_TEMPERATURE	LITERAL1
+DAYLIGHT_WHITE_COLOR_TEMPERATURE	LITERAL1
+WHITE_COLOR_TEMPERATURE	LITERAL1
+SOFT_WHITE_COLOR_TEMPERATURE	LITERAL1
+WARM_WHITE_COLOR_TEMPERATURE	LITERAL1
+RGB_BLACK	LITERAL1
+RGB_WHITE	LITERAL1
+RGB_RED	LITERAL1
+RGB_YELLOW	LITERAL1
+RGB_GREEN	LITERAL1
+RGB_CYAN	LITERAL1
+RGB_BLUE	LITERAL1
+RGB_MAGENTA	LITERAL1
diff --git a/libraries/ESP32/library.properties b/libraries/ESP32/library.properties
index 8e78c3f3b3d..7ebc69be71f 100644
--- a/libraries/ESP32/library.properties
+++ b/libraries/ESP32/library.properties
@@ -1,5 +1,5 @@
 name=ESP32
-version=1.0
+version=3.2.0
 author=Hristo Gochkov, Ivan Grokhtkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=ESP32 sketches examples
diff --git a/libraries/ESP_I2S/examples/ES8388_loopback/ES8388.cpp b/libraries/ESP_I2S/examples/ES8388_loopback/ES8388.cpp
new file mode 100644
index 00000000000..908d36fec8c
--- /dev/null
+++ b/libraries/ESP_I2S/examples/ES8388_loopback/ES8388.cpp
@@ -0,0 +1,704 @@
+/*
+  This is a very basic driver for the ES8388 based on the driver written by
+  me for NuttX. It is not complete and is missing master mode, mono mode, many
+  features and configuration options. You can use readReg and writeReg to
+  access the registers directly and configure missing features. Feel free to
+  contribute by adding missing features and improving the driver.
+  It is intended to be used only with arduino-esp32.
+
+  The default configuration can be found in the ES8388.h file.
+
+  This was only tested with the ESP32-LyraT board using 44100Hz 16-bit stereo
+  audio. It may not work with other configurations.
+
+  Created for arduino-esp32 on 20 Dec, 2023
+  by Lucas Saavedra Vaz (lucasssvaz)
+*/
+
+#include <cmath>
+
+#include "ESP_I2S.h"
+#include "Wire.h"
+
+#include "ES8388.h"
+
+/****************************************************************************
+ * Private Methods
+ ****************************************************************************/
+
+/*
+  Name: start
+
+  Description:
+    Unmute and start the ES8388 codec data transmission.
+*/
+
+void ES8388::start() {
+  uint8_t prev_regval = 0;
+  uint8_t regval = 0;
+
+  log_v("Starting ES8388 transmission...");
+  _running = true;
+  prev_regval = readReg(ES8388_DACCONTROL21);
+
+  if (_audio_mode == ES_MODULE_LINE) {
+    writeReg(ES8388_DACCONTROL16, ES8388_RMIXSEL_RIN2 | ES8388_LMIXSEL_LIN2);
+
+    writeReg(ES8388_DACCONTROL17, ES8388_LI2LOVOL(ES8388_MIXER_GAIN_0DB) | ES8388_LI2LO_ENABLE | ES8388_LD2LO_DISABLE);
+
+    writeReg(ES8388_DACCONTROL20, ES8388_RI2ROVOL(ES8388_MIXER_GAIN_0DB) | ES8388_RI2RO_ENABLE | ES8388_RD2RO_DISABLE);
+
+    writeReg(
+      ES8388_DACCONTROL21,
+      ES8388_DAC_DLL_PWD_NORMAL | ES8388_ADC_DLL_PWD_NORMAL | ES8388_MCLK_DIS_NORMAL | ES8388_OFFSET_DIS_DISABLE | ES8388_LRCK_SEL_ADC | ES8388_SLRCK_SAME
+    );
+  } else {
+    writeReg(
+      ES8388_DACCONTROL21,
+      ES8388_DAC_DLL_PWD_NORMAL | ES8388_ADC_DLL_PWD_NORMAL | ES8388_MCLK_DIS_NORMAL | ES8388_OFFSET_DIS_DISABLE | ES8388_LRCK_SEL_DAC | ES8388_SLRCK_SAME
+    );
+  }
+
+  regval = readReg(ES8388_DACCONTROL21);
+
+  if (regval != prev_regval) {
+    writeReg(
+      ES8388_CHIPPOWER, ES8388_DACVREF_PDN_PWRUP | ES8388_ADCVREF_PDN_PWRUP | ES8388_DACDLL_PDN_NORMAL | ES8388_ADCDLL_PDN_NORMAL | ES8388_DAC_STM_RST_RESET
+                          | ES8388_ADC_STM_RST_RESET | ES8388_DAC_DIGPDN_RESET | ES8388_ADC_DIGPDN_RESET
+    );
+
+    writeReg(
+      ES8388_CHIPPOWER, ES8388_DACVREF_PDN_PWRUP | ES8388_ADCVREF_PDN_PWRUP | ES8388_DACDLL_PDN_NORMAL | ES8388_ADCDLL_PDN_NORMAL | ES8388_DAC_STM_RST_NORMAL
+                          | ES8388_ADC_STM_RST_NORMAL | ES8388_DAC_DIGPDN_NORMAL | ES8388_ADC_DIGPDN_NORMAL
+    );
+  }
+
+  if (_audio_mode == ES_MODULE_LINE || _audio_mode == ES_MODULE_ADC_DAC || _audio_mode == ES_MODULE_ADC) {
+    writeReg(
+      ES8388_ADCPOWER, ES8388_INT1LP_NORMAL | ES8388_FLASHLP_NORMAL | ES8388_PDNADCBIASGEN_NORMAL | ES8388_PDNMICB_PWRON | ES8388_PDNADCR_PWRUP
+                         | ES8388_PDNADCL_PWRUP | ES8388_PDNAINR_NORMAL | ES8388_PDNAINL_NORMAL
+    );
+  }
+
+  if (_audio_mode == ES_MODULE_LINE || _audio_mode == ES_MODULE_ADC_DAC || _audio_mode == ES_MODULE_DAC) {
+    writeReg(
+      ES8388_DACPOWER, ES8388_ROUT2_ENABLE | ES8388_LOUT2_ENABLE | ES8388_ROUT1_ENABLE | ES8388_LOUT1_ENABLE | ES8388_PDNDACR_PWRUP | ES8388_PDNDACL_PWRUP
+    );
+  }
+
+  setmute(_audio_mode, false);
+  log_v("ES8388 transmission started.");
+}
+
+/*
+  Name: reset
+
+  Description:
+    Reset the ES8388 codec to a known state depending on the audio mode.
+*/
+
+void ES8388::reset() {
+  uint8_t regconfig;
+
+  log_v("Resetting ES8388...");
+  log_d(
+    "Current configuration: _bpsamp=%d, _samprate=%d, _nchannels=%d, _audio_mode=%d, _dac_output=%d, _adc_input=%d, _mic_gain=%d", _bpsamp, _samprate,
+    _nchannels, _audio_mode, _dac_output, _adc_input, _mic_gain
+  );
+
+  writeReg(ES8388_DACCONTROL3, ES8388_DACMUTE_MUTED | ES8388_DACLER_NORMAL | ES8388_DACSOFTRAMP_DISABLE | ES8388_DACRAMPRATE_4LRCK);
+
+  writeReg(
+    ES8388_CONTROL2,
+    ES8388_PDNVREFBUF_NORMAL | ES8388_VREFLO_NORMAL | ES8388_PDNIBIASGEN_NORMAL | ES8388_PDNANA_NORMAL | ES8388_LPVREFBUF_LP | ES8388_LPVCMMOD_NORMAL | (1 << 6)
+  ); /* Default value of undocumented bit */
+
+  writeReg(
+    ES8388_CHIPPOWER, ES8388_DACVREF_PDN_PWRUP | ES8388_ADCVREF_PDN_PWRUP | ES8388_DACDLL_PDN_NORMAL | ES8388_ADCDLL_PDN_NORMAL | ES8388_DAC_STM_RST_NORMAL
+                        | ES8388_ADC_STM_RST_NORMAL | ES8388_DAC_DIGPDN_NORMAL | ES8388_ADC_DIGPDN_NORMAL
+  );
+
+  /* Disable the internal DLL to improve 8K sample rate */
+
+  writeReg(0x35, 0xa0);
+  writeReg(0x37, 0xd0);
+  writeReg(0x39, 0xd0);
+
+  writeReg(ES8388_MASTERMODE, ES8388_BCLKDIV(ES_MCLK_DIV_AUTO) | ES8388_BCLK_INV_NORMAL | ES8388_MCLKDIV2_NODIV | ES8388_MSC_SLAVE);
+
+  writeReg(
+    ES8388_DACPOWER, ES8388_ROUT2_DISABLE | ES8388_LOUT2_DISABLE | ES8388_ROUT1_DISABLE | ES8388_LOUT1_DISABLE | ES8388_PDNDACR_PWRDN | ES8388_PDNDACL_PWRDN
+  );
+
+  writeReg(
+    ES8388_CONTROL1, ES8388_VMIDSEL_500K | ES8388_ENREF_DISABLE | ES8388_SEQEN_DISABLE | ES8388_SAMEFS_SAME | ES8388_DACMCLK_ADCMCLK | ES8388_LRCM_ISOLATED
+                       | ES8388_SCPRESET_NORMAL
+  );
+
+  setBitsPerSample(_bpsamp);
+  setSampleRate(_samprate);
+
+  writeReg(ES8388_DACCONTROL16, ES8388_RMIXSEL_RIN1 | ES8388_LMIXSEL_LIN1);
+
+  writeReg(ES8388_DACCONTROL17, ES8388_LI2LOVOL(ES8388_MIXER_GAIN_0DB) | ES8388_LI2LO_DISABLE | ES8388_LD2LO_ENABLE);
+
+  writeReg(ES8388_DACCONTROL20, ES8388_RI2ROVOL(ES8388_MIXER_GAIN_0DB) | ES8388_RI2RO_DISABLE | ES8388_RD2RO_ENABLE);
+
+  writeReg(
+    ES8388_DACCONTROL21,
+    ES8388_DAC_DLL_PWD_NORMAL | ES8388_ADC_DLL_PWD_NORMAL | ES8388_MCLK_DIS_NORMAL | ES8388_OFFSET_DIS_DISABLE | ES8388_LRCK_SEL_DAC | ES8388_SLRCK_SAME
+  );
+
+  writeReg(ES8388_DACCONTROL23, ES8388_VROI_1_5K);
+
+  writeReg(ES8388_DACCONTROL24, ES8388_LOUT1VOL(ES8388_DAC_CHVOL_DB(0)));
+
+  writeReg(ES8388_DACCONTROL25, ES8388_ROUT1VOL(ES8388_DAC_CHVOL_DB(0)));
+
+  writeReg(ES8388_DACCONTROL26, ES8388_LOUT2VOL(ES8388_DAC_CHVOL_DB(0)));
+
+  writeReg(ES8388_DACCONTROL27, ES8388_ROUT2VOL(ES8388_DAC_CHVOL_DB(0)));
+
+  setmute(ES_MODULE_DAC, ES8388_DEFAULT_MUTE);
+  setvolume(ES_MODULE_DAC, ES8388_DEFAULT_VOL_OUT, ES8388_DEFAULT_BALANCE);
+
+  if (_dac_output == ES8388_DAC_OUTPUT_LINE2) {
+    regconfig = ES_DAC_CHANNEL_LOUT1 | ES_DAC_CHANNEL_ROUT1;
+  } else if (_dac_output == ES8388_DAC_OUTPUT_LINE1) {
+    regconfig = ES_DAC_CHANNEL_LOUT2 | ES_DAC_CHANNEL_ROUT2;
+  } else {
+    regconfig = ES_DAC_CHANNEL_LOUT1 | ES_DAC_CHANNEL_ROUT1 | ES_DAC_CHANNEL_LOUT2 | ES_DAC_CHANNEL_ROUT2;
+  }
+
+  writeReg(ES8388_DACPOWER, regconfig);
+
+  writeReg(
+    ES8388_ADCPOWER, ES8388_INT1LP_LP | ES8388_FLASHLP_LP | ES8388_PDNADCBIASGEN_LP | ES8388_PDNMICB_PWRDN | ES8388_PDNADCR_PWRDN | ES8388_PDNADCL_PWRDN
+                       | ES8388_PDNAINR_PWRDN | ES8388_PDNAINL_PWRDN
+  );
+
+  setMicGain(24); /* +24 dB */
+
+  if (_adc_input == ES8388_ADC_INPUT_LINE1) {
+    regconfig = ES_ADC_CHANNEL_LINPUT1_RINPUT1;
+  } else if (_adc_input == ES8388_ADC_INPUT_LINE2) {
+    regconfig = ES_ADC_CHANNEL_LINPUT2_RINPUT2;
+  } else {
+    regconfig = ES_ADC_CHANNEL_DIFFERENCE;
+  }
+
+  writeReg(ES8388_ADCCONTROL2, regconfig);
+
+  writeReg(
+    ES8388_ADCCONTROL3, (1 << 1) | /* Default value of undocumented bit */
+                          ES8388_TRI_NORMAL | ES8388_MONOMIX_STEREO | ES8388_DS_LINPUT1_RINPUT1
+  );
+
+  setBitsPerSample(_bpsamp);
+  setSampleRate(_samprate);
+  setmute(ES_MODULE_ADC, ES8388_DEFAULT_MUTE);
+  setvolume(ES_MODULE_ADC, ES8388_DEFAULT_VOL_IN, ES8388_DEFAULT_BALANCE);
+
+  writeReg(
+    ES8388_ADCPOWER, ES8388_INT1LP_LP | ES8388_FLASHLP_NORMAL | ES8388_PDNADCBIASGEN_NORMAL | ES8388_PDNMICB_PWRDN | ES8388_PDNADCR_PWRUP | ES8388_PDNADCL_PWRUP
+                       | ES8388_PDNAINR_NORMAL | ES8388_PDNAINL_NORMAL
+  );
+
+  /* Stop sequence to avoid noise at boot */
+
+  stop();
+
+  log_v("ES8388 reset.");
+}
+
+/*
+  Name: stop
+
+  Description:
+    Mute and stop the ES8388 codec data transmission.
+*/
+
+void ES8388::stop() {
+  log_v("Stopping ES8388 transmission...");
+  _running = false;
+
+  if (_audio_mode == ES_MODULE_LINE) {
+    writeReg(
+      ES8388_DACCONTROL21,
+      ES8388_DAC_DLL_PWD_NORMAL | ES8388_ADC_DLL_PWD_NORMAL | ES8388_MCLK_DIS_NORMAL | ES8388_OFFSET_DIS_DISABLE | ES8388_LRCK_SEL_DAC | ES8388_SLRCK_SAME
+    );
+
+    writeReg(ES8388_DACCONTROL16, ES8388_RMIXSEL_RIN1 | ES8388_LMIXSEL_LIN1);
+
+    writeReg(ES8388_DACCONTROL17, ES8388_LI2LOVOL(ES8388_MIXER_GAIN_0DB) | ES8388_LI2LO_DISABLE | ES8388_LD2LO_ENABLE);
+
+    writeReg(ES8388_DACCONTROL20, ES8388_RI2ROVOL(ES8388_MIXER_GAIN_0DB) | ES8388_RI2RO_DISABLE | ES8388_RD2RO_ENABLE);
+
+    goto stop_msg;
+  }
+
+  if (_audio_mode == ES_MODULE_DAC || _audio_mode == ES_MODULE_ADC_DAC) {
+    writeReg(
+      ES8388_DACPOWER, ES8388_ROUT2_DISABLE | ES8388_LOUT2_DISABLE | ES8388_ROUT1_DISABLE | ES8388_LOUT1_DISABLE | ES8388_PDNDACR_PWRUP | ES8388_PDNDACL_PWRUP
+    );
+  }
+
+  if (_audio_mode == ES_MODULE_ADC || _audio_mode == ES_MODULE_ADC_DAC) {
+    writeReg(
+      ES8388_ADCPOWER, ES8388_INT1LP_LP | ES8388_FLASHLP_LP | ES8388_PDNADCBIASGEN_LP | ES8388_PDNMICB_PWRDN | ES8388_PDNADCR_PWRDN | ES8388_PDNADCL_PWRDN
+                         | ES8388_PDNAINR_PWRDN | ES8388_PDNAINL_PWRDN
+    );
+  }
+
+  if (_audio_mode == ES_MODULE_ADC_DAC) {
+    writeReg(
+      ES8388_DACCONTROL21,
+      ES8388_DAC_DLL_PWD_PWRDN | ES8388_ADC_DLL_PWD_PWRDN | ES8388_MCLK_DIS_DISABLE | ES8388_OFFSET_DIS_DISABLE | ES8388_LRCK_SEL_DAC | ES8388_SLRCK_SAME
+    );
+  }
+
+stop_msg:
+  setmute(_audio_mode, true);
+  log_v("ES8388 transmission stopped.");
+}
+
+/*
+  Name: setvolume
+
+  Description:
+    Set the volume of the ES8388 codec.
+
+  Input Parameters:
+    module - Module to set the volume for.
+    volume - Volume level {0..1000}.
+    balance - Balance level {0..1000}.
+*/
+
+void ES8388::setvolume(es_module_e module, uint16_t volume, uint16_t balance) {
+  uint16_t leftlvl;
+  int16_t dbleftlvl;
+  uint16_t rightlvl;
+  int16_t dbrightlvl;
+
+  log_d("Volume = %u, Balance = %u", volume, balance);
+
+  if (volume > 1000) {
+    log_w("Warning: Volume greater than 1000, setting to 1000.");
+    volume = 1000;
+  }
+
+  if (balance > 1000) {
+    log_w("Warning: Balance greater than 1000, setting to 1000.");
+    balance = 1000;
+  }
+
+  _balance = balance;
+
+  /* Calculate the left channel volume level {0..1000} */
+
+  if (_balance <= 500) {
+    leftlvl = volume;
+  } else if (_balance == 1000) {
+    leftlvl = 0;
+  } else {
+    leftlvl = ((((1000 - _balance) * 100) / 500) * volume) / 100;
+  }
+
+  /* Calculate the right channel volume level {0..1000} */
+
+  if (_balance >= 500) {
+    rightlvl = volume;
+  } else if (_balance == 0) {
+    rightlvl = 0;
+  } else {
+    rightlvl = (((_balance * 100) / 500) * volume) / 100;
+  }
+
+  /* Convert from (0..1000) to (-96..0) */
+
+  dbleftlvl = (int16_t)(leftlvl ? (20 * log10f((float)rightlvl / 1000)) : -96);
+  dbrightlvl = (int16_t)(rightlvl ? (20 * log10f((float)rightlvl / 1000)) : -96);
+
+  log_v("Volume: dbleftlvl = %d, dbrightlvl = %d", dbleftlvl, dbrightlvl);
+
+  /* Convert and truncate to 1 byte */
+
+  dbleftlvl = ((-dbleftlvl) << 1) & 0xff;
+  dbrightlvl = ((-dbrightlvl) << 1) & 0xff;
+
+  /* Set the volume */
+
+  if (module == ES_MODULE_DAC || module == ES_MODULE_ADC_DAC) {
+    writeReg(ES8388_DACCONTROL4, ES8388_LDACVOL(dbleftlvl));
+    writeReg(ES8388_DACCONTROL5, ES8388_RDACVOL(dbrightlvl));
+    _volume_out = volume;
+  }
+
+  if (module == ES_MODULE_ADC || module == ES_MODULE_ADC_DAC) {
+    writeReg(ES8388_ADCCONTROL8, ES8388_LADCVOL(dbleftlvl));
+    writeReg(ES8388_ADCCONTROL9, ES8388_RADCVOL(dbrightlvl));
+    _volume_in = volume;
+  }
+}
+
+/*
+  Name: setmute
+
+  Description:
+    Mute or unmute the selected ES8388 codec module.
+
+  Input Parameters:
+    module - Module to mute or unmute.
+    enable - Mute or unmute.
+*/
+
+void ES8388::setmute(es_module_e module, bool enable) {
+  uint8_t reg = 0;
+
+  log_d("module=%d, mute=%d", module, (int)enable);
+
+  _mute = enable;
+
+  if (module == ES_MODULE_DAC || module == ES_MODULE_ADC_DAC) {
+    reg = readReg(ES8388_DACCONTROL3) & (~ES8388_DACMUTE_BITMASK);
+    writeReg(ES8388_DACCONTROL3, reg | ES8388_DACMUTE(enable));
+  }
+
+  if (module == ES_MODULE_ADC || module == ES_MODULE_ADC_DAC) {
+    reg = readReg(ES8388_ADCCONTROL7) & (~ES8388_ADCMUTE_BITMASK);
+    writeReg(ES8388_ADCCONTROL7, reg | ES8388_ADCMUTE(enable));
+  }
+}
+
+/****************************************************************************
+ * Public Methods
+ ****************************************************************************/
+
+ES8388::~ES8388() {
+  end();
+}
+
+/*
+  Name: begin
+
+  Description:
+    Initialize the ES8388 codec. Requires the I2S and I2C buses to be initialized
+    before calling this function.
+
+  Input Parameters:
+    i2s - I2S bus instance.
+    i2c - I2C bus instance. Defaults to Wire.
+    addr - I2C address of the ES8388 codec. Defaults to 0x10.
+
+  Return:
+    true - Success.
+    false - Failure.
+*/
+bool ES8388::begin(I2SClass &i2s, TwoWire &i2c, uint8_t addr) {
+  log_v("Initializing ES8388...");
+
+  _i2c = &i2c;
+  _i2s = &i2s;
+  _addr = addr;
+  _fmt = ES8388_DEFAULT_FMT;
+  _mode = ES8388_DEFAULT_MODE;
+  _samprate = ES8388_DEFAULT_SAMPRATE;
+  _nchannels = ES8388_DEFAULT_NCHANNELS;
+  _bpsamp = ES8388_DEFAULT_BPSAMP;
+  _audio_mode = ES8388_DEFAULT_AUDIO_MODE;
+  _dac_output = ES8388_DEFAULT_DAC_OUTPUT;
+  _adc_input = ES8388_DEFAULT_ADC_INPUT;
+  _mic_gain = ES8388_DEFAULT_MIC_GAIN;
+  _running = false;
+  _lclk_div = ES_LCLK_DIV_256;
+  _word_length = ES_WORD_LENGTH_16BITS;
+
+  _i2c->beginTransmission(_addr);
+
+  if (_i2c->endTransmission() != 0) {
+    log_e("Device not found at address 0x%02x. Check if the I2C and I2S buses are initialized.", _addr);
+    return false;
+  }
+
+  reset();
+  log_v("ES8388 initialized.");
+  return true;
+}
+
+/*
+  Name: end
+
+  Description:
+    Stop the ES8388 codec and reset it to a known state.
+*/
+
+void ES8388::end() {
+  log_v("Ending ES8388...");
+
+  stop();
+  setmute(ES_MODULE_ADC_DAC, true);
+  _audio_mode = ES_MODULE_ADC_DAC;
+  reset();
+
+  log_v("ES8388 ended.");
+}
+
+/*
+  Name: readReg
+
+  Description:
+    Read a register from the ES8388 codec.
+
+  Input Parameters:
+    reg - Register address.
+
+  Return:
+    Register value.
+*/
+
+uint8_t ES8388::readReg(uint8_t reg) {
+  int data;
+
+  _i2c->beginTransmission(_addr);
+  if (_i2c->write(reg) == 0) {
+    log_e("Error writing register address 0x%02x.", reg);
+    return 0;
+  }
+
+  if (_i2c->endTransmission(false) != 0) {
+    log_e("Error ending transmission.");
+    return 0;
+  }
+
+  if (!_i2c->requestFrom(_addr, (uint8_t)1)) {
+    log_e("Error requesting data.");
+    return 0;
+  }
+
+  if ((data = _i2c->read()) < 0) {
+    log_e("Error reading data.");
+    return 0;
+  }
+
+  return (uint8_t)data;
+}
+
+/*
+  Name: writeReg
+
+  Description:
+    Write a register to the ES8388 codec.
+
+  Input Parameters:
+    reg - Register address.
+    data - Data to write.
+*/
+
+void ES8388::writeReg(uint8_t reg, uint8_t data) {
+  _i2c->beginTransmission(_addr);
+
+  if (_i2c->write(reg) == 0) {
+    log_e("Error writing register address 0x%02x.", reg);
+    return;
+  }
+
+  if (_i2c->write(data) == 0) {
+    log_e("Error writing data 0x%02x.", data);
+    return;
+  }
+
+  if (_i2c->endTransmission(true) != 0) {
+    log_e("Error ending transmission.");
+    return;
+  }
+}
+
+/*
+  Name: setMicGain
+
+  Description:
+    Set the microphone gain.
+
+  Input Parameters:
+    gain - Gain level in dB {0..24}.
+*/
+
+void ES8388::setMicGain(uint8_t gain) {
+  static const es_mic_gain_e gain_map[] = {
+    ES_MIC_GAIN_0DB,  ES_MIC_GAIN_3DB,  ES_MIC_GAIN_6DB,  ES_MIC_GAIN_9DB,  ES_MIC_GAIN_12DB,
+    ES_MIC_GAIN_15DB, ES_MIC_GAIN_18DB, ES_MIC_GAIN_21DB, ES_MIC_GAIN_24DB,
+  };
+
+  log_d("gain=%d", gain);
+
+  _mic_gain = gain_map[min(gain, (uint8_t)24) / 3];
+
+  writeReg(ES8388_ADCCONTROL1, ES8388_MICAMPR(_mic_gain) | ES8388_MICAMPL(_mic_gain));
+
+  log_v("Mic gain set to %d", _mic_gain);
+}
+
+/*
+  Name: setBitsPerSample
+
+  Description:
+    Set the number of bits per sample. This also configures the I2S bus.
+
+  Input Parameters:
+    bpsamp - Bits per sample {16, 24, 32}.
+*/
+
+void ES8388::setBitsPerSample(uint8_t bpsamp) {
+  /* ES8388 also supports 18 and 20 bits per sample, but the I2S bus does not */
+  switch (bpsamp) {
+    case 16: _word_length = ES_WORD_LENGTH_16BITS; break;
+
+    case 24: _word_length = ES_WORD_LENGTH_24BITS; break;
+
+    case 32: _word_length = ES_WORD_LENGTH_32BITS; break;
+
+    default: log_e("Data length not supported."); return;
+  }
+
+  _bpsamp = bpsamp;
+  _i2s->configureTX(_samprate, (i2s_data_bit_width_t)_bpsamp, I2S_SLOT_MODE_STEREO);
+  _i2s->configureRX(_samprate, (i2s_data_bit_width_t)_bpsamp, I2S_SLOT_MODE_STEREO);
+
+  if (_audio_mode == ES_MODULE_ADC || _audio_mode == ES_MODULE_ADC_DAC) {
+    writeReg(ES8388_ADCCONTROL4, ES8388_ADCFORMAT(ES_I2S_NORMAL) | ES8388_ADCWL(_word_length) | ES8388_ADCLRP_NORM_2ND | ES8388_DATSEL_LL);
+  }
+
+  if (_audio_mode == ES_MODULE_DAC || _audio_mode == ES_MODULE_ADC_DAC) {
+    writeReg(ES8388_DACCONTROL1, ES8388_DACFORMAT(ES_I2S_NORMAL) | ES8388_DACWL(_word_length) | ES8388_DACLRP_NORM_2ND | ES8388_DACLRSWAP_NORMAL);
+  }
+
+  log_v("Datawidth set to %u", _bpsamp);
+}
+
+/*
+  Name: setSampleRate
+
+  Description:
+    Set the sample rate. This also configures the I2S bus.
+    The divider depends on the sample rate and the MCLK frequency.
+    This needs to be re-implemented to properly support all cases.
+    ES8388 should also support 88100Hz and 96000Hz sample rates in
+    double speed mode but setting it makes the audio sound distorted.
+
+  Input Parameters:
+    rate - Sample rate {8000, 11025, 12000, 16000, 22050, 24000, 32000,
+           44100, 48000}.
+*/
+
+void ES8388::setSampleRate(uint32_t rate) {
+  /*
+    According to the datasheet, this should only matter for the master mode
+    but it seems to affect the slave mode as well.
+  */
+
+  switch (rate) {
+    case 8000: _lclk_div = ES_LCLK_DIV_1536; break;
+
+    case 11025:
+    case 12000: _lclk_div = ES_LCLK_DIV_1024; break;
+
+    case 16000: _lclk_div = ES_LCLK_DIV_768; break;
+
+    case 22050:
+    case 24000: _lclk_div = ES_LCLK_DIV_512; break;
+
+    case 32000: _lclk_div = ES_LCLK_DIV_384; break;
+
+    case 44100:
+    case 48000: _lclk_div = ES_LCLK_DIV_256; break;
+
+    default: log_e("Sample rate not supported."); return;
+  }
+
+  _samprate = rate;
+  _i2s->configureTX(_samprate, (i2s_data_bit_width_t)_bpsamp, I2S_SLOT_MODE_STEREO);
+  _i2s->configureRX(_samprate, (i2s_data_bit_width_t)_bpsamp, I2S_SLOT_MODE_STEREO);
+
+  if (_audio_mode == ES_MODULE_ADC || _audio_mode == ES_MODULE_ADC_DAC) {
+    writeReg(ES8388_ADCCONTROL5, ES8388_ADCFSRATIO(_lclk_div));
+  }
+
+  if (_audio_mode == ES_MODULE_DAC || _audio_mode == ES_MODULE_ADC_DAC) {
+    writeReg(ES8388_DACCONTROL2, ES8388_DACFSRATIO(_lclk_div));
+  }
+
+  log_v("Sample rate set to %d in single speed mode", _samprate);
+}
+
+/*
+  Name: playWAV
+
+  Description:
+    Wrapper for the I2SClass::playWAV() method. This method starts the ES8388
+    codec before playing the WAV file and stops it after the WAV file has been
+    played.
+
+  Input Parameters:
+    data - Pointer to the WAV file data.
+    len - Length of the WAV file data.
+*/
+
+void ES8388::playWAV(uint8_t *data, size_t len) {
+  _audio_mode = ES_MODULE_DAC;
+  reset();
+
+  log_v("Playing WAV file...");
+  start();
+  _i2s->playWAV(data, len);
+  stop();
+  log_v("WAV file played.");
+}
+
+/*
+  Name: recordWAV
+
+  Description:
+    Wrapper for the I2SClass::recordWAV() method. This method starts the ES8388
+    codec before recording the WAV file and stops it after the WAV file has been
+    recorded.
+
+  Input Parameters:
+    rec_seconds - Length of the WAV file to record in seconds.
+    out_size - Pointer to the variable that will hold the size of the WAV file.
+
+  Return:
+    Pointer to the WAV file data.
+*/
+
+uint8_t *ES8388::recordWAV(size_t rec_seconds, size_t *out_size) {
+  uint8_t *data;
+  size_t size;
+
+  _audio_mode = ES_MODULE_ADC;
+  reset();
+
+  log_v("Recording WAV file...");
+  start();
+  data = _i2s->recordWAV(rec_seconds, &size);
+  stop();
+  log_v("WAV file recorded.");
+
+  *out_size = size;
+  return data;
+}
+
+void ES8388::setOutputVolume(uint16_t volume, uint16_t balance) {
+  setvolume(ES_MODULE_DAC, volume, balance);
+}
+
+void ES8388::setInputVolume(uint16_t volume, uint16_t balance) {
+  setvolume(ES_MODULE_ADC, volume, balance);
+}
+
+void ES8388::setOutputMute(bool enable) {
+  setmute(ES_MODULE_DAC, enable);
+}
+
+void ES8388::setInputMute(bool enable) {
+  setmute(ES_MODULE_ADC, enable);
+}
diff --git a/libraries/ESP_I2S/examples/ES8388_loopback/ES8388.h b/libraries/ESP_I2S/examples/ES8388_loopback/ES8388.h
new file mode 100644
index 00000000000..372480613eb
--- /dev/null
+++ b/libraries/ESP_I2S/examples/ES8388_loopback/ES8388.h
@@ -0,0 +1,1079 @@
+/*
+  This is a very basic driver for the ES8388 based on the driver written by
+  me for NuttX. It is not complete and is missing master mode, mono mode,many
+  features and configuration options. You can use readReg and writeReg to
+  access the registers directly and configure missing features. Feel free to
+  contribute by adding missing features and improving the driver.
+  It is intended to be used only with arduino-esp32.
+
+  The default configuration can be found in the ES8388.h file.
+
+  This was only tested with the ESP32-LyraT board using 44100Hz 16-bit stereo
+  audio. It may not work with other configurations.
+
+  Created for arduino-esp32 on 20 Dec, 2023
+  by Lucas Saavedra Vaz (lucasssvaz)
+*/
+
+#pragma once
+
+#include "ESP_I2S.h"
+#include "Wire.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ES8388_DAC_CHVOL_DB(v) (2 * v / 3 + 30)
+
+/* Registers Addresses ******************************************************/
+
+#define ES8388_CONTROL1     0x00
+#define ES8388_CONTROL2     0x01
+#define ES8388_CHIPPOWER    0x02
+#define ES8388_ADCPOWER     0x03
+#define ES8388_DACPOWER     0x04
+#define ES8388_CHIPLOPOW1   0x05
+#define ES8388_CHIPLOPOW2   0x06
+#define ES8388_ANAVOLMANAG  0x07
+#define ES8388_MASTERMODE   0x08
+#define ES8388_ADCCONTROL1  0x09
+#define ES8388_ADCCONTROL2  0x0a
+#define ES8388_ADCCONTROL3  0x0b
+#define ES8388_ADCCONTROL4  0x0c
+#define ES8388_ADCCONTROL5  0x0d
+#define ES8388_ADCCONTROL6  0x0e
+#define ES8388_ADCCONTROL7  0x0f
+#define ES8388_ADCCONTROL8  0x10
+#define ES8388_ADCCONTROL9  0x11
+#define ES8388_ADCCONTROL10 0x12
+#define ES8388_ADCCONTROL11 0x13
+#define ES8388_ADCCONTROL12 0x14
+#define ES8388_ADCCONTROL13 0x15
+#define ES8388_ADCCONTROL14 0x16
+#define ES8388_DACCONTROL1  0x17
+#define ES8388_DACCONTROL2  0x18
+#define ES8388_DACCONTROL3  0x19
+#define ES8388_DACCONTROL4  0x1a
+#define ES8388_DACCONTROL5  0x1b
+#define ES8388_DACCONTROL6  0x1c
+#define ES8388_DACCONTROL7  0x1d
+#define ES8388_DACCONTROL8  0x1e
+#define ES8388_DACCONTROL9  0x1f
+#define ES8388_DACCONTROL10 0x20
+#define ES8388_DACCONTROL11 0x21
+#define ES8388_DACCONTROL12 0x22
+#define ES8388_DACCONTROL13 0x23
+#define ES8388_DACCONTROL14 0x24
+#define ES8388_DACCONTROL15 0x25
+#define ES8388_DACCONTROL16 0x26
+#define ES8388_DACCONTROL17 0x27
+#define ES8388_DACCONTROL18 0x28
+#define ES8388_DACCONTROL19 0x29
+#define ES8388_DACCONTROL20 0x2a
+#define ES8388_DACCONTROL21 0x2b
+#define ES8388_DACCONTROL22 0x2c
+#define ES8388_DACCONTROL23 0x2d
+#define ES8388_DACCONTROL24 0x2e
+#define ES8388_DACCONTROL25 0x2f
+#define ES8388_DACCONTROL26 0x30
+#define ES8388_DACCONTROL27 0x31
+#define ES8388_DACCONTROL28 0x32
+#define ES8388_DACCONTROL29 0x33
+#define ES8388_DACCONTROL30 0x34
+
+/* Register Power-up Default Values *****************************************/
+
+#define ES8388_CONTROL1_DEFAULT     0x06
+#define ES8388_CONTROL2_DEFAULT     0x5c
+#define ES8388_CHIPPOWER_DEFAULT    0xc3
+#define ES8388_ADCPOWER_DEFAULT     0xfc
+#define ES8388_DACPOWER_DEFAULT     0xc0
+#define ES8388_CHIPLOPOW1_DEFAULT   0x00
+#define ES8388_CHIPLOPOW2_DEFAULT   0x00
+#define ES8388_ANAVOLMANAG_DEFAULT  0x7c
+#define ES8388_MASTERMODE_DEFAULT   0x80
+#define ES8388_ADCCONTROL1_DEFAULT  0x00
+#define ES8388_ADCCONTROL2_DEFAULT  0x00
+#define ES8388_ADCCONTROL3_DEFAULT  0x02
+#define ES8388_ADCCONTROL4_DEFAULT  0x00
+#define ES8388_ADCCONTROL5_DEFAULT  0x06
+#define ES8388_ADCCONTROL6_DEFAULT  0x30
+#define ES8388_ADCCONTROL7_DEFAULT  0x20
+#define ES8388_ADCCONTROL8_DEFAULT  0xc0
+#define ES8388_ADCCONTROL9_DEFAULT  0xc0
+#define ES8388_ADCCONTROL10_DEFAULT 0x38
+#define ES8388_ADCCONTROL11_DEFAULT 0xb0
+#define ES8388_ADCCONTROL12_DEFAULT 0x32
+#define ES8388_ADCCONTROL13_DEFAULT 0x06
+#define ES8388_ADCCONTROL14_DEFAULT 0x00
+#define ES8388_DACCONTROL1_DEFAULT  0x00
+#define ES8388_DACCONTROL2_DEFAULT  0x06
+#define ES8388_DACCONTROL3_DEFAULT  0x22
+#define ES8388_DACCONTROL4_DEFAULT  0xc0
+#define ES8388_DACCONTROL5_DEFAULT  0xc0
+#define ES8388_DACCONTROL6_DEFAULT  0x08
+#define ES8388_DACCONTROL7_DEFAULT  0x00
+#define ES8388_DACCONTROL8_DEFAULT  0x1f
+#define ES8388_DACCONTROL9_DEFAULT  0xf7
+#define ES8388_DACCONTROL10_DEFAULT 0xfd
+#define ES8388_DACCONTROL11_DEFAULT 0xff
+#define ES8388_DACCONTROL12_DEFAULT 0x1f
+#define ES8388_DACCONTROL13_DEFAULT 0xf7
+#define ES8388_DACCONTROL14_DEFAULT 0xfd
+#define ES8388_DACCONTROL15_DEFAULT 0xff
+#define ES8388_DACCONTROL16_DEFAULT 0x00
+#define ES8388_DACCONTROL17_DEFAULT 0x38
+#define ES8388_DACCONTROL18_DEFAULT 0x28
+#define ES8388_DACCONTROL19_DEFAULT 0x28
+#define ES8388_DACCONTROL20_DEFAULT 0x38
+#define ES8388_DACCONTROL21_DEFAULT 0x00
+#define ES8388_DACCONTROL22_DEFAULT 0x00
+#define ES8388_DACCONTROL23_DEFAULT 0x00
+#define ES8388_DACCONTROL24_DEFAULT 0x00
+#define ES8388_DACCONTROL25_DEFAULT 0x00
+#define ES8388_DACCONTROL26_DEFAULT 0x00
+#define ES8388_DACCONTROL27_DEFAULT 0x00
+#define ES8388_DACCONTROL28_DEFAULT 0x00
+#define ES8388_DACCONTROL29_DEFAULT 0xaa
+#define ES8388_DACCONTROL30_DEFAULT 0xaa
+
+/* Register Bit Definitions *************************************************/
+
+/* 0x00 Chip Control 1 */
+
+#define ES8388_VMIDSEL_SHIFT   (0)
+#define ES8388_VMIDSEL_BITMASK (0x03 << ES8388_VMIDSEL_SHIFT)
+#define ES8388_VMIDSEL_DISABLE (0 << ES8388_VMIDSEL_SHIFT)
+#define ES8388_VMIDSEL_50K     (1 << ES8388_VMIDSEL_SHIFT)
+#define ES8388_VMIDSEL_500K    (2 << ES8388_VMIDSEL_SHIFT)
+#define ES8388_VMIDSEL_5K      (3 << ES8388_VMIDSEL_SHIFT)
+
+#define ES8388_ENREF_SHIFT   (2)
+#define ES8388_ENREF_BITMASK (0x01 << ES8388_ENREF_SHIFT)
+#define ES8388_ENREF_DISABLE (0 << ES8388_ENREF_SHIFT)
+#define ES8388_ENREF_ENABLE  (1 << ES8388_ENREF_SHIFT)
+
+#define ES8388_SEQEN_SHIFT   (3)
+#define ES8388_SEQEN_BITMASK (0x01 << ES8388_SEQEN_SHIFT)
+#define ES8388_SEQEN_DISABLE (0 << ES8388_SEQEN_SHIFT)
+#define ES8388_SEQEN_ENABLE  (1 << ES8388_SEQEN_SHIFT)
+
+#define ES8388_SAMEFS_SHIFT   (4)
+#define ES8388_SAMEFS_BITMASK (0x01 << ES8388_SAMEFS_SHIFT)
+#define ES8388_SAMEFS_DIFFER  (0 << ES8388_SAMEFS_SHIFT)
+#define ES8388_SAMEFS_SAME    (1 << ES8388_SAMEFS_SHIFT)
+
+#define ES8388_DACMCLK_SHIFT   (5)
+#define ES8388_DACMCLK_BITMASK (0x01 << ES8388_DACMCLK_SHIFT)
+#define ES8388_DACMCLK_ADCMCLK (0 << ES8388_DACMCLK_SHIFT)
+#define ES8388_DACMCLK_DACMCLK (1 << ES8388_DACMCLK_SHIFT)
+
+#define ES8388_LRCM_SHIFT    (6)
+#define ES8388_LRCM_BITMASK  (0x01 << ES8388_LRCM_SHIFT)
+#define ES8388_LRCM_ISOLATED (0 << ES8388_LRCM_SHIFT)
+#define ES8388_LRCM_ALL      (1 << ES8388_LRCM_SHIFT)
+
+#define ES8388_SCPRESET_SHIFT   (7)
+#define ES8388_SCPRESET_BITMASK (0x01 << ES8388_SCPRESET_SHIFT)
+#define ES8388_SCPRESET_NORMAL  (0 << ES8388_SCPRESET_SHIFT)
+#define ES8388_SCPRESET_RESET   (1 << ES8388_SCPRESET_SHIFT)
+
+/* 0x01 Chip Control 2 */
+
+#define ES8388_PDNVREFBUF_SHIFT   (0)
+#define ES8388_PDNVREFBUF_BITMASK (0x01 << ES8388_PDNVREFBUF_SHIFT)
+#define ES8388_PDNVREFBUF_NORMAL  (0 << ES8388_PDNVREFBUF_SHIFT)
+#define ES8388_PDNVREFBUF_PWRDN   (1 << ES8388_PDNVREFBUF_SHIFT)
+
+#define ES8388_VREFLO_SHIFT   (1)
+#define ES8388_VREFLO_BITMASK (0x01 << ES8388_VREFLO_SHIFT)
+#define ES8388_VREFLO_NORMAL  (0 << ES8388_VREFLO_SHIFT)
+#define ES8388_VREFLO_LP      (1 << ES8388_VREFLO_SHIFT)
+
+#define ES8388_PDNIBIASGEN_SHIFT   (2)
+#define ES8388_PDNIBIASGEN_BITMASK (0x01 << ES8388_PDNIBIASGEN_SHIFT)
+#define ES8388_PDNIBIASGEN_NORMAL  (0 << ES8388_PDNIBIASGEN_SHIFT)
+#define ES8388_PDNIBIASGEN_PWRDN   (1 << ES8388_PDNIBIASGEN_SHIFT)
+
+#define ES8388_PDNANA_SHIFT   (3)
+#define ES8388_PDNANA_BITMASK (0x01 << ES8388_PDNANA_SHIFT)
+#define ES8388_PDNANA_NORMAL  (0 << ES8388_PDNANA_SHIFT)
+#define ES8388_PDNANA_PWRDN   (1 << ES8388_PDNANA_SHIFT)
+
+#define ES8388_LPVREFBUF_SHIFT   (4)
+#define ES8388_LPVREFBUF_BITMASK (0x01 << ES8388_LPVREFBUF_SHIFT)
+#define ES8388_LPVREFBUF_NORMAL  (0 << ES8388_LPVREFBUF_SHIFT)
+#define ES8388_LPVREFBUF_LP      (1 << ES8388_LPVREFBUF_SHIFT)
+
+#define ES8388_LPVCMMOD_SHIFT   (5)
+#define ES8388_LPVCMMOD_BITMASK (0x01 << ES8388_LPVCMMOD_SHIFT)
+#define ES8388_LPVCMMOD_NORMAL  (0 << ES8388_LPVCMMOD_SHIFT)
+#define ES8388_LPVCMMOD_LP      (1 << ES8388_LPVCMMOD_SHIFT)
+
+/* 0x02 Chip Power Management */
+
+#define ES8388_DACVREF_PDN_SHIFT   (0)
+#define ES8388_DACVREF_PDN_BITMASK (0x01 << ES8388_DACVREF_PDN_SHIFT)
+#define ES8388_DACVREF_PDN_PWRUP   (0 << ES8388_DACVREF_PDN_SHIFT)
+#define ES8388_DACVREF_PDN_PWRDN   (1 << ES8388_DACVREF_PDN_SHIFT)
+
+#define ES8388_ADCVREF_PDN_SHIFT   (1)
+#define ES8388_ADCVREF_PDN_BITMASK (0x01 << ES8388_ADCVREF_PDN_SHIFT)
+#define ES8388_ADCVREF_PDN_PWRUP   (0 << ES8388_ADCVREF_PDN_SHIFT)
+#define ES8388_ADCVREF_PDN_PWRDN   (1 << ES8388_ADCVREF_PDN_SHIFT)
+
+#define ES8388_DACDLL_PDN_SHIFT   (2)
+#define ES8388_DACDLL_PDN_BITMASK (0x01 << ES8388_DACDLL_PDN_SHIFT)
+#define ES8388_DACDLL_PDN_NORMAL  (0 << ES8388_DACDLL_PDN_SHIFT)
+#define ES8388_DACDLL_PDN_PWRDN   (1 << ES8388_DACDLL_PDN_SHIFT)
+
+#define ES8388_ADCDLL_PDN_SHIFT   (3)
+#define ES8388_ADCDLL_PDN_BITMASK (0x01 << ES8388_ADCDLL_PDN_SHIFT)
+#define ES8388_ADCDLL_PDN_NORMAL  (0 << ES8388_ADCDLL_PDN_SHIFT)
+#define ES8388_ADCDLL_PDN_PWRDN   (1 << ES8388_ADCDLL_PDN_SHIFT)
+
+#define ES8388_DAC_STM_RST_SHIFT   (4)
+#define ES8388_DAC_STM_RST_BITMASK (0x01 << ES8388_DAC_STM_RST_SHIFT)
+#define ES8388_DAC_STM_RST_NORMAL  (0 << ES8388_DAC_STM_RST_SHIFT)
+#define ES8388_DAC_STM_RST_RESET   (1 << ES8388_DAC_STM_RST_SHIFT)
+
+#define ES8388_ADC_STM_RST_SHIFT   (5)
+#define ES8388_ADC_STM_RST_BITMASK (0x01 << ES8388_ADC_STM_RST_SHIFT)
+#define ES8388_ADC_STM_RST_NORMAL  (0 << ES8388_ADC_STM_RST_SHIFT)
+#define ES8388_ADC_STM_RST_RESET   (1 << ES8388_ADC_STM_RST_SHIFT)
+
+#define ES8388_DAC_DIGPDN_SHIFT   (6)
+#define ES8388_DAC_DIGPDN_BITMASK (0x01 << ES8388_DAC_DIGPDN_SHIFT)
+#define ES8388_DAC_DIGPDN_NORMAL  (0 << ES8388_DAC_DIGPDN_SHIFT)
+#define ES8388_DAC_DIGPDN_RESET   (1 << ES8388_DAC_DIGPDN_SHIFT)
+
+#define ES8388_ADC_DIGPDN_SHIFT   (7)
+#define ES8388_ADC_DIGPDN_BITMASK (0x01 << ES8388_ADC_DIGPDN_SHIFT)
+#define ES8388_ADC_DIGPDN_NORMAL  (0 << ES8388_ADC_DIGPDN_SHIFT)
+#define ES8388_ADC_DIGPDN_RESET   (1 << ES8388_ADC_DIGPDN_SHIFT)
+
+/* 0x03 ADC Power Management */
+
+#define ES8388_INT1LP_SHIFT   (0)
+#define ES8388_INT1LP_BITMASK (0x01 << ES8388_INT1LP_SHIFT)
+#define ES8388_INT1LP_NORMAL  (0 << ES8388_INT1LP_SHIFT)
+#define ES8388_INT1LP_LP      (1 << ES8388_INT1LP_SHIFT)
+
+#define ES8388_FLASHLP_SHIFT   (1)
+#define ES8388_FLASHLP_BITMASK (0x01 << ES8388_FLASHLP_SHIFT)
+#define ES8388_FLASHLP_NORMAL  (0 << ES8388_FLASHLP_SHIFT)
+#define ES8388_FLASHLP_LP      (1 << ES8388_FLASHLP_SHIFT)
+
+#define ES8388_PDNADCBIASGEN_SHIFT   (2)
+#define ES8388_PDNADCBIASGEN_BITMASK (0x01 << ES8388_PDNADCBIASGEN_SHIFT)
+#define ES8388_PDNADCBIASGEN_NORMAL  (0 << ES8388_PDNADCBIASGEN_SHIFT)
+#define ES8388_PDNADCBIASGEN_LP      (1 << ES8388_PDNADCBIASGEN_SHIFT)
+
+#define ES8388_PDNMICB_SHIFT   (3)
+#define ES8388_PDNMICB_BITMASK (0x01 << ES8388_PDNMICB_SHIFT)
+#define ES8388_PDNMICB_PWRON   (0 << ES8388_PDNMICB_SHIFT)
+#define ES8388_PDNMICB_PWRDN   (1 << ES8388_PDNMICB_SHIFT)
+
+#define ES8388_PDNADCR_SHIFT   (4)
+#define ES8388_PDNADCR_BITMASK (0x01 << ES8388_PDNADCR_SHIFT)
+#define ES8388_PDNADCR_PWRUP   (0 << ES8388_PDNADCR_SHIFT)
+#define ES8388_PDNADCR_PWRDN   (1 << ES8388_PDNADCR_SHIFT)
+
+#define ES8388_PDNADCL_SHIFT   (5)
+#define ES8388_PDNADCL_BITMASK (0x01 << ES8388_PDNADCL_SHIFT)
+#define ES8388_PDNADCL_PWRUP   (0 << ES8388_PDNADCL_SHIFT)
+#define ES8388_PDNADCL_PWRDN   (1 << ES8388_PDNADCL_SHIFT)
+
+#define ES8388_PDNAINR_SHIFT   (6)
+#define ES8388_PDNAINR_BITMASK (0x01 << ES8388_PDNAINR_SHIFT)
+#define ES8388_PDNAINR_NORMAL  (0 << ES8388_PDNAINR_SHIFT)
+#define ES8388_PDNAINR_PWRDN   (1 << ES8388_PDNAINR_SHIFT)
+
+#define ES8388_PDNAINL_SHIFT   (7)
+#define ES8388_PDNAINL_BITMASK (0x01 << ES8388_PDNAINL_SHIFT)
+#define ES8388_PDNAINL_NORMAL  (0 << ES8388_PDNAINL_SHIFT)
+#define ES8388_PDNAINL_PWRDN   (1 << ES8388_PDNAINL_SHIFT)
+
+/* 0x04 DAC Power Management */
+
+#define ES8388_ROUT2_SHIFT   (2)
+#define ES8388_ROUT2_BITMASK (0x01 << ES8388_ROUT2_SHIFT)
+#define ES8388_ROUT2_DISABLE (0 << ES8388_ROUT2_SHIFT)
+#define ES8388_ROUT2_ENABLE  (1 << ES8388_ROUT2_SHIFT)
+
+#define ES8388_LOUT2_SHIFT   (3)
+#define ES8388_LOUT2_BITMASK (0x01 << ES8388_LOUT2_SHIFT)
+#define ES8388_LOUT2_DISABLE (0 << ES8388_LOUT2_SHIFT)
+#define ES8388_LOUT2_ENABLE  (1 << ES8388_LOUT2_SHIFT)
+
+#define ES8388_ROUT1_SHIFT   (4)
+#define ES8388_ROUT1_BITMASK (0x01 << ES8388_ROUT1_SHIFT)
+#define ES8388_ROUT1_DISABLE (0 << ES8388_ROUT1_SHIFT)
+#define ES8388_ROUT1_ENABLE  (1 << ES8388_ROUT1_SHIFT)
+
+#define ES8388_LOUT1_SHIFT   (5)
+#define ES8388_LOUT1_BITMASK (0x01 << ES8388_LOUT1_SHIFT)
+#define ES8388_LOUT1_DISABLE (0 << ES8388_LOUT1_SHIFT)
+#define ES8388_LOUT1_ENABLE  (1 << ES8388_LOUT1_SHIFT)
+
+#define ES8388_PDNDACR_SHIFT   (6)
+#define ES8388_PDNDACR_BITMASK (0x01 << ES8388_PDNDACR_SHIFT)
+#define ES8388_PDNDACR_PWRUP   (0 << ES8388_PDNDACR_SHIFT)
+#define ES8388_PDNDACR_PWRDN   (1 << ES8388_PDNDACR_SHIFT)
+
+#define ES8388_PDNDACL_SHIFT   (7)
+#define ES8388_PDNDACL_BITMASK (0x01 << ES8388_PDNDACL_SHIFT)
+#define ES8388_PDNDACL_PWRUP   (0 << ES8388_PDNDACL_SHIFT)
+#define ES8388_PDNDACL_PWRDN   (1 << ES8388_PDNDACL_SHIFT)
+
+/* 0x05 Chip Low Power 1 */
+
+#define ES8388_LPLOUT2_SHIFT   (3)
+#define ES8388_LPLOUT2_BITMASK (0x01 << ES8388_LPLOUT2_SHIFT)
+#define ES8388_LPLOUT2_NORMAL  (0 << ES8388_LPLOUT2_SHIFT)
+#define ES8388_LPLOUT2_LP      (1 << ES8388_LPLOUT2_SHIFT)
+
+#define ES8388_LPLOUT1_SHIFT   (5)
+#define ES8388_LPLOUT1_BITMASK (0x01 << ES8388_LPLOUT1_SHIFT)
+#define ES8388_LPLOUT1_NORMAL  (0 << ES8388_LPLOUT1_SHIFT)
+#define ES8388_LPLOUT1_LP      (1 << ES8388_LPLOUT1_SHIFT)
+
+#define ES8388_LPDACR_SHIFT   (6)
+#define ES8388_LPDACR_BITMASK (0x01 << ES8388_LPDACR_SHIFT)
+#define ES8388_LPDACR_NORMAL  (0 << ES8388_LPDACR_SHIFT)
+#define ES8388_LPDACR_LP      (1 << ES8388_LPDACR_SHIFT)
+
+#define ES8388_LPDACL_SHIFT   (7)
+#define ES8388_LPDACL_BITMASK (0x01 << ES8388_LPDACL_SHIFT)
+#define ES8388_LPDACL_NORMAL  (0 << ES8388_LPDACL_SHIFT)
+#define ES8388_LPDACL_LP      (1 << ES8388_LPDACL_SHIFT)
+
+/* 0x06 Chip Low Power 2 */
+
+#define ES8388_LPDACVRP_SHIFT   (0)
+#define ES8388_LPDACVRP_BITMASK (0x01 << ES8388_LPDACVRP_SHIFT)
+#define ES8388_LPDACVRP_NORMAL  (0 << ES8388_LPDACVRP_SHIFT)
+#define ES8388_LPDACVRP_LP      (1 << ES8388_LPDACVRP_SHIFT)
+
+#define ES8388_LPADCVRP_SHIFT   (1)
+#define ES8388_LPADCVRP_BITMASK (0x01 << ES8388_LPDACVRP_SHIFT)
+#define ES8388_LPADCVRP_NORMAL  (0 << ES8388_LPDACVRP_SHIFT)
+#define ES8388_LPADCVRP_LP      (1 << ES8388_LPDACVRP_SHIFT)
+
+#define ES8388_LPLMIX_SHIFT   (6)
+#define ES8388_LPLMIX_BITMASK (0x01 << ES8388_LPLMIX_SHIFT)
+#define ES8388_LPLMIX_NORMAL  (0 << ES8388_LPLMIX_SHIFT)
+#define ES8388_LPLMIX_LP      (1 << ES8388_LPLMIX_SHIFT)
+
+#define ES8388_LPPGA_SHIFT   (7)
+#define ES8388_LPPGA_BITMASK (0x01 << ES8388_LPPGA_SHIFT)
+#define ES8388_LPPGA_NORMAL  (0 << ES8388_LPPGA_SHIFT)
+#define ES8388_LPPGA_LP      (1 << ES8388_LPPGA_SHIFT)
+
+/* 0x08 Master Mode Control */
+
+#define ES8388_BCLKDIV_SHIFT   (0)
+#define ES8388_BCLKDIV_BITMASK (0x1f << ES8388_BCLKDIV_SHIFT)
+#define ES8388_BCLKDIV(a)      (a << ES8388_BCLKDIV_SHIFT)
+
+#define ES8388_BCLK_INV_SHIFT    (5)
+#define ES8388_BCLK_INV_BITMASL  (0x01 << ES8388_BCLK_INV_SHIFT)
+#define ES8388_BCLK_INV_NORMAL   (0 << ES8388_BCLK_INV_SHIFT)
+#define ES8388_BCLK_INV_INVERTED (1 << ES8388_BCLK_INV_SHIFT)
+
+#define ES8388_MCLKDIV2_SHIFT   (6)
+#define ES8388_MCLKDIV2_BITMASK (0x01 << ES8388_MCLKDIV2_SHIFT)
+#define ES8388_MCLKDIV2_NODIV   (0 << ES8388_MCLKDIV2_SHIFT)
+#define ES8388_MCLKDIV2_DIV2    (1 << ES8388_MCLKDIV2_SHIFT)
+
+#define ES8388_MSC_SHIFT   (7)
+#define ES8388_MSC_BITMASK (0x01 << ES8388_MSC_SHIFT)
+#define ES8388_MSC_SLAVE   (0 << ES8388_MSC_SHIFT)
+#define ES8388_MSC_MASTER  (1 << ES8388_MSC_SHIFT)
+
+/* 0x09 ADC Control 1 */
+
+#define ES8388_MICAMPR_SHIFT   (0)
+#define ES8388_MICAMPR_BITMASK (0x0f << ES8388_MICAMPR_SHIFT)
+#define ES8388_MICAMPR(a)      (a << ES8388_MICAMPR_SHIFT)
+
+#define ES8388_MICAMPL_SHIFT   (4)
+#define ES8388_MICAMPL_BITMASK (0x0f << ES8388_MICAMPL_SHIFT)
+#define ES8388_MICAMPL(a)      (a << ES8388_MICAMPL_SHIFT)
+
+/* 0x0a ADC Control 2 */
+
+#define ES8388_DSR_SHIFT           (2)
+#define ES8388_DSR_BITMASK         (0x01 << ES8388_DSR_SHIFT)
+#define ES8388_DSR_LINPUT1_RINPUT1 (0 << ES8388_DSR_SHIFT)
+#define ES8388_DSR_LINPUT2_RINPUT2 (1 << ES8388_DSR_SHIFT)
+
+#define ES8388_DSSEL_SHIFT    (3)
+#define ES8388_DSSEL_BITMASK  (0x01 << ES8388_DSSEL_SHIFT)
+#define ES8388_DSSEL_ONE_REG  (0 << ES8388_DSSEL_SHIFT)
+#define ES8388_DSSEL_MULT_REG (1 << ES8388_DSSEL_SHIFT)
+
+#define ES8388_RINSEL_SHIFT   (4)
+#define ES8388_RINSEL_BITMASK (0x03 << ES8388_RINSEL_SHIFT)
+#define ES8388_RINSEL_RINPUT1 (0 << ES8388_RINSEL_SHIFT)
+#define ES8388_RINSEL_RINPUT2 (1 << ES8388_RINSEL_SHIFT)
+#define ES8388_RINSEL_DIFF    (3 << ES8388_RINSEL_SHIFT)
+
+#define ES8388_LINSEL_SHIFT   (6)
+#define ES8388_LINSEL_BITMASK (0x03 << ES8388_LINSEL_SHIFT)
+#define ES8388_LINSEL_LINPUT1 (0 << ES8388_LINSEL_SHIFT)
+#define ES8388_LINSEL_LINPUT2 (1 << ES8388_LINSEL_SHIFT)
+#define ES8388_LINSEL_DIFF    (3 << ES8388_LINSEL_SHIFT)
+
+/* 0x0b ADC Control 3 */
+
+#define ES8388_TRI_SHIFT     (2)
+#define ES8388_TRI_BITMASK   (0x01 << ES8388_TRI_SHIFT)
+#define ES8388_TRI_NORMAL    (0 << ES8388_TRI_SHIFT)
+#define ES8388_TRI_TRISTATED (1 << ES8388_TRI_SHIFT)
+
+#define ES8388_MONOMIX_SHIFT   (3)
+#define ES8388_MONOMIX_BITMASK (0x03 << ES8388_MONOMIX_SHIFT)
+#define ES8388_MONOMIX_STEREO  (0 << ES8388_MONOMIX_SHIFT)
+#define ES8388_MONOMIX_LADC    (1 << ES8388_MONOMIX_SHIFT)
+#define ES8388_MONOMIX_RADC    (2 << ES8388_MONOMIX_SHIFT)
+
+#define ES8388_DS_SHIFT           (7)
+#define ES8388_DS_BITMASK         (0x01 << ES8388_DS_SHIFT)
+#define ES8388_DS_LINPUT1_RINPUT1 (0 << ES8388_DS_SHIFT)
+#define ES8388_DS_LINPUT2_RINPUT2 (1 << ES8388_DS_SHIFT)
+
+/* 0x0c ADC Control 4 */
+
+#define ES8388_ADCFORMAT_SHIFT   (0)
+#define ES8388_ADCFORMAT_BITMASK (0x03 << ES8388_ADCFORMAT_SHIFT)
+#define ES8388_ADCFORMAT(a)      (a << ES8388_ADCFORMAT_SHIFT)
+
+#define ES8388_ADCWL_SHIFT   (2)
+#define ES8388_ADCWL_BITMASK (0x07 << ES8388_ADCWL_SHIFT)
+#define ES8388_ADCWL(a)      (a << ES8388_ADCWL_SHIFT)
+
+#define ES8388_ADCLRP_SHIFT    (5)
+#define ES8388_ADCLRP_BITMASK  (0x01 << ES8388_ADCLRP_SHIFT)
+#define ES8388_ADCLRP_NORM_2ND (0 << ES8388_ADCLRP_SHIFT)
+#define ES8388_ADCLRP_INV_1ST  (1 << ES8388_ADCLRP_SHIFT)
+
+#define ES8388_DATSEL_SHIFT   (6)
+#define ES8388_DATSEL_BITMASK (0x03 << ES8388_DATSEL_SHIFT)
+#define ES8388_DATSEL_LL      (0 << ES8388_DATSEL_SHIFT)
+#define ES8388_DATSEL_LR      (1 << ES8388_DATSEL_SHIFT)
+#define ES8388_DATSEL_RR      (2 << ES8388_DATSEL_SHIFT)
+#define ES8388_DATSEL_RL      (3 << ES8388_DATSEL_SHIFT)
+
+/* 0x0d ADC Control 5 */
+
+#define ES8388_ADCFSRATIO_SHIFT   (0)
+#define ES8388_ADCFSRATIO_BITMASK (0x1f << ES8388_ADCFSRATIO_SHIFT)
+#define ES8388_ADCFSRATIO(a)      (a << ES8388_ADCFSRATIO_SHIFT)
+
+#define ES8388_ADCFSMODE_SHIFT   (5)
+#define ES8388_ADCFSMODE_BITMASK (0x01 << ES8388_ADCFSMODE_SHIFT)
+#define ES8388_ADCFSMODE_SINGLE  (0 << ES8388_ADCFSMODE_SHIFT)
+#define ES8388_ADCFSMODE_DOUBLE  (1 << ES8388_ADCFSMODE_SHIFT)
+
+/* 0x0e ADC Control 6 */
+
+#define ES8388_ADC_HPF_R_SHIFT   (4)
+#define ES8388_ADC_HPF_R_BITMASK (0x01 << ES8388_ADC_HPF_R_SHIFT)
+#define ES8388_ADC_HPF_R_DISABLE (0 << ES8388_ADC_HPF_R_SHIFT)
+#define ES8388_ADC_HPF_R_ENABLE  (1 << ES8388_ADC_HPF_R_SHIFT)
+
+#define ES8388_ADC_HPF_L_SHIFT   (5)
+#define ES8388_ADC_HPF_L_BITMASK (0x01 << ES8388_ADC_HPF_L_SHIFT)
+#define ES8388_ADC_HPF_L_DISABLE (0 << ES8388_ADC_HPF_L_SHIFT)
+#define ES8388_ADC_HPF_L_ENABLE  (1 << ES8388_ADC_HPF_L_SHIFT)
+
+#define ES8388_ADC_INVR_SHIFT    (6)
+#define ES8388_ADC_INVR_BITMASK  (0x01 << ES8388_ADC_INVR_SHIFT)
+#define ES8388_ADC_INVR_NORMAL   (0 << ES8388_ADC_INVR_SHIFT)
+#define ES8388_ADC_INVR_INVERTED (1 << ES8388_ADC_INVR_SHIFT)
+
+#define ES8388_ADC_INVL_SHIFT    (7)
+#define ES8388_ADC_INVL_BITMASK  (0x01 << ES8388_ADC_INVL_SHIFT)
+#define ES8388_ADC_INVL_NORMAL   (0 << ES8388_ADC_INVL_SHIFT)
+#define ES8388_ADC_INVL_INVERTED (1 << ES8388_ADC_INVL_SHIFT)
+
+/* 0x0f ADC Control 7 */
+
+#define ES8388_ADCMUTE_SHIFT   (2)
+#define ES8388_ADCMUTE_BITMASK (0x01 << ES8388_ADCMUTE_SHIFT)
+#define ES8388_ADCMUTE(a)      (((int)a) << ES8388_ADCMUTE_SHIFT)
+#define ES8388_ADCMUTE_NORMAL  (0 << ES8388_ADCMUTE_SHIFT)
+#define ES8388_ADCMUTE_MUTED   (1 << ES8388_ADCMUTE_SHIFT)
+
+#define ES8388_ADCLER_SHIFT   (3)
+#define ES8388_ADCLER_BITMASK (0x01 << ES8388_ADCLER_SHIFT)
+#define ES8388_ADCLER_NORMAL  (0 << ES8388_ADCLER_SHIFT)
+#define ES8388_ADCLER_ADCLEFT (1 << ES8388_ADCLER_SHIFT)
+
+#define ES8388_ADCSOFTRAMP_SHIFT   (5)
+#define ES8388_ADCSOFTRAMP_BITMASK (0x01 << ES8388_ADCSOFTRAMP_SHIFT)
+#define ES8388_ADCSOFTRAMP_DISABLE (0 << ES8388_ADCSOFTRAMP_SHIFT)
+#define ES8388_ADCSOFTRAMP_ENABLE  (1 << ES8388_ADCSOFTRAMP_SHIFT)
+
+#define ES8388_ADCRAMPRATE_SHIFT   (6)
+#define ES8388_ADCRAMPRATE_BITMASK (0x03 << ES8388_ADCRAMPRATE_SHIFT)
+#define ES8388_ADCRAMPRATE_4LRCK   (0 << ES8388_ADCRAMPRATE_SHIFT)
+#define ES8388_ADCRAMPRATE_8LRCK   (1 << ES8388_ADCRAMPRATE_SHIFT)
+#define ES8388_ADCRAMPRATE_16LRCK  (2 << ES8388_ADCRAMPRATE_SHIFT)
+#define ES8388_ADCRAMPRATE_32LRCK  (3 << ES8388_ADCRAMPRATE_SHIFT)
+
+/* 0x10 ADC Control 8 */
+
+#define ES8388_LADCVOL_SHIFT   (0)
+#define ES8388_LADCVOL_BITMASK (0xff << ES8388_LADCVOL_SHIFT)
+#define ES8388_LADCVOL(a)      (a << ES8388_LADCVOL_SHIFT)
+
+/* 0x11 ADC Control 9 */
+
+#define ES8388_RADCVOL_SHIFT   (0)
+#define ES8388_RADCVOL_BITMASK (0xff << ES8388_RADCVOL_SHIFT)
+#define ES8388_RADCVOL(a)      (a << ES8388_RADCVOL_SHIFT)
+
+/* 0x12 ADC Control 10 */
+
+#define ES8388_MINGAIN_SHIFT   (0)
+#define ES8388_MINGAIN_BITMASK (0x07 << ES8388_MINGAIN_SHIFT)
+#define ES8388_MINGAIN(a)      (a << ES8388_MINGAIN_SHIFT)
+
+#define ES8388_MAXGAIN_SHIFT   (3)
+#define ES8388_MAXGAIN_BITMASK (0x07 << ES8388_MAXGAIN_SHIFT)
+#define ES8388_MAXGAIN(a)      (a << ES8388_MAXGAIN_SHIFT)
+
+#define ES8388_ADCSEL_SHIFT   (6)
+#define ES8388_ADCSEL_BITMASK (0x03 << ES8388_ADCSEL_SHIFT)
+#define ES8388_ADCSEL_OFF     (0 << ES8388_ADCSEL_SHIFT)
+#define ES8388_ADCSEL_RIGHT   (1 << ES8388_ADCSEL_SHIFT)
+#define ES8388_ADCSEL_LEFT    (2 << ES8388_ADCSEL_SHIFT)
+#define ES8388_ADCSEL_STEREO  (3 << ES8388_ADCSEL_SHIFT)
+
+/* 0x13 ADC Control 11 */
+
+#define ES8388_ALCHLD_SHIFT   (0)
+#define ES8388_ALCHLD_BITMASK (0x0f << ES8388_ALCHLD_SHIFT)
+#define ES8388_ALCHLD(a)      (a << ES8388_ALCHLD_SHIFT)
+
+#define ES8388_ALCLVL_SHIFT   (4)
+#define ES8388_ALCLVL_BITMASK (0x0f << ES8388_ALCLVL_SHIFT)
+#define ES8388_ALCLVL(a)      (a << ES8388_ALCLVL_SHIFT)
+
+/* 0x14 ADC Control 12 */
+
+#define ES8388_ALCATK_SHIFT   (0)
+#define ES8388_ALCATK_BITMASK (0x0f << ES8388_ALCATK_SHIFT)
+#define ES8388_ALCATK(a)      (a << ES8388_ALCATK_SHIFT)
+
+#define ES8388_ALCDCY_SHIFT   (4)
+#define ES8388_ALCDCY_BITMASK (0x0f << ES8388_ALCDCY_SHIFT)
+#define ES8388_ALCDCY(a)      (a << ES8388_ALCDCY_SHIFT)
+
+/* 0x15 ADC Control 13 */
+
+#define ES8388_WIN_SIZE_SHIFT   (0)
+#define ES8388_WIN_SIZE_BITMASK (0x1f << ES8388_WIN_SIZE_SHIFT)
+#define ES8388_WIN_SIZE(a)      (a << ES8388_WIN_SIZE_SHIFT)
+
+#define ES8388_TIME_OUT_SHIFT   (5)
+#define ES8388_TIME_OUT_BITMASK (0x01 << ES8388_TIME_OUT_SHIFT)
+#define ES8388_TIME_OUT_DISABLE (0 << ES8388_TIME_OUT_SHIFT)
+#define ES8388_TIME_OUT_ENABLE  (1 << ES8388_TIME_OUT_SHIFT)
+
+#define ES8388_ALCZC_SHIFT   (6)
+#define ES8388_ALCZC_BITMASK (0x01 << ES8388_ALCZC_SHIFT)
+#define ES8388_ALCZC_DISABLE (0 << ES8388_ALCZC_SHIFT)
+#define ES8388_ALCZC_ENABLE  (1 << ES8388_ALCZC_SHIFT)
+
+#define ES8388_ALCMODE_SHIFT   (7)
+#define ES8388_ALCMODE_BITMASK (0x01 << ES8388_ALCMODE_SHIFT)
+#define ES8388_ALCMODE_NORMAL  (0 << ES8388_ALCMODE_SHIFT)
+#define ES8388_ALCMODE_LIMITER (1 << ES8388_ALCMODE_SHIFT)
+
+/* 0x16 ADC Control 14 */
+
+#define ES8388_NGAT_SHIFT   (0)
+#define ES8388_NGAT_BITMASK (0x01 << ES8388_NGAT_SHIFT)
+#define ES8388_NGAT_DISABLE (0 << ES8388_NGAT_SHIFT)
+#define ES8388_NGAT_ENABLE  (1 << ES8388_NGAT_SHIFT)
+
+#define ES8388_NGG_SHIFT   (1)
+#define ES8388_NGG_BITMASK (0x01 << ES8388_NGG_SHIFT)
+#define ES8388_NGG_CONST   (0 << ES8388_NGG_SHIFT)
+#define ES8388_NGG_MUTE    (1 << ES8388_NGG_SHIFT)
+
+#define ES8388_NGTH_SHIFT   (3)
+#define ES8388_NGTH_BITMASK (0x1f << ES8388_NGTH_SHIFT)
+#define ES8388_NGTH(a)      (a << ES8388_NGTH_SHIFT)
+
+/* 0x17 DAC Control 1 */
+
+#define ES8388_DACFORMAT_SHIFT   (1)
+#define ES8388_DACFORMAT_BITMASK (0x03 << ES8388_DACFORMAT_SHIFT)
+#define ES8388_DACFORMAT(a)      (a << ES8388_DACFORMAT_SHIFT)
+
+#define ES8388_DACWL_SHIFT   (3)
+#define ES8388_DACWL_BITMASK (0x07 << ES8388_DACWL_SHIFT)
+#define ES8388_DACWL(a)      (a << ES8388_DACWL_SHIFT)
+
+#define ES8388_DACLRP_SHIFT    (6)
+#define ES8388_DACLRP_BITMASK  (0x01 << ES8388_DACLRP_SHIFT)
+#define ES8388_DACLRP_NORM_2ND (0 << ES8388_DACLRP_SHIFT)
+#define ES8388_DACLRP_INV_1ST  (1 << ES8388_DACLRP_SHIFT)
+
+#define ES8388_DACLRSWAP_SHIFT   (7)
+#define ES8388_DACLRSWAP_BITMASK (0x01 << ES8388_DACLRSWAP_SHIFT)
+#define ES8388_DACLRSWAP_NORMAL  (0 << ES8388_DACLRSWAP_SHIFT)
+#define ES8388_DACLRSWAP_SWAP    (1 << ES8388_DACLRSWAP_SHIFT)
+
+/* 0x18 DAC Control 2 */
+
+#define ES8388_DACFSRATIO_SHIFT   (0)
+#define ES8388_DACFSRATIO_BITMASK (0x1f << ES8388_DACFSRATIO_SHIFT)
+#define ES8388_DACFSRATIO(a)      (a << ES8388_DACFSRATIO_SHIFT)
+
+#define ES8388_DACFSMODE_SHIFT   (5)
+#define ES8388_DACFSMODE_BITMASK (0x01 << ES8388_DACFSMODE_SHIFT)
+#define ES8388_DACFSMODE_SINGLE  (0 << ES8388_DACFSMODE_SHIFT)
+#define ES8388_DACFSMODE_DOUBLE  (1 << ES8388_DACFSMODE_SHIFT)
+
+/* 0x19 DAC Control 3 */
+
+#define ES8388_DACMUTE_SHIFT   (2)
+#define ES8388_DACMUTE_BITMASK (0x01 << ES8388_DACMUTE_SHIFT)
+#define ES8388_DACMUTE(a)      (((int)a) << ES8388_DACMUTE_SHIFT)
+#define ES8388_DACMUTE_NORMAL  (0 << ES8388_DACMUTE_SHIFT)
+#define ES8388_DACMUTE_MUTED   (1 << ES8388_DACMUTE_SHIFT)
+
+#define ES8388_DACLER_SHIFT   (3)
+#define ES8388_DACLER_BITMASK (0x01 << ES8388_DACLER_SHIFT)
+#define ES8388_DACLER_NORMAL  (0 << ES8388_DACLER_SHIFT)
+#define ES8388_DACLER_ADCLEFT (1 << ES8388_DACLER_SHIFT)
+
+#define ES8388_DACSOFTRAMP_SHIFT   (5)
+#define ES8388_DACSOFTRAMP_BITMASK (0x01 << ES8388_DACSOFTRAMP_SHIFT)
+#define ES8388_DACSOFTRAMP_DISABLE (0 << ES8388_DACSOFTRAMP_SHIFT)
+#define ES8388_DACSOFTRAMP_ENABLE  (1 << ES8388_DACSOFTRAMP_SHIFT)
+
+#define ES8388_DACRAMPRATE_SHIFT   (6)
+#define ES8388_DACRAMPRATE_BITMASK (0x03 << ES8388_DACRAMPRATE_SHIFT)
+#define ES8388_DACRAMPRATE_4LRCK   (0 << ES8388_DACRAMPRATE_SHIFT)
+#define ES8388_DACRAMPRATE_32LRCK  (1 << ES8388_DACRAMPRATE_SHIFT)
+#define ES8388_DACRAMPRATE_64LRCK  (2 << ES8388_DACRAMPRATE_SHIFT)
+#define ES8388_DACRAMPRATE_128LRCK (3 << ES8388_DACRAMPRATE_SHIFT)
+
+/* 0x1a DAC Control 4 */
+
+#define ES8388_LDACVOL_SHIFT   (0)
+#define ES8388_LDACVOL_BITMASK (0xff << ES8388_LDACVOL_SHIFT)
+#define ES8388_LDACVOL(a)      (a << ES8388_LDACVOL_SHIFT)
+
+/* 0x1b DAC Control 5 */
+
+#define ES8388_RDACVOL_SHIFT   (0)
+#define ES8388_RDACVOL_BITMASK (0xff << ES8388_RDACVOL_SHIFT)
+#define ES8388_RDACVOL(a)      (a << ES8388_RDACVOL_SHIFT)
+
+/* 0x1c DAC Control 6 */
+
+#define ES8388_CLICKFREE_SHIFT   (3)
+#define ES8388_CLICKFREE_BITMASK (0x01 << ES8388_CLICKFREE_SHIFT)
+#define ES8388_CLICKFREE_DISABLE (0 << ES8388_CLICKFREE_SHIFT)
+#define ES8388_CLICKFREE_ENABLE  (1 << ES8388_CLICKFREE_SHIFT)
+
+#define ES8388_DAC_INVR_SHIFT   (4)
+#define ES8388_DAC_INVR_BITMASK (0x01 << ES8388_DAC_INVR_SHIFT)
+#define ES8388_DAC_INVR_NOINV   (0 << ES8388_DAC_INVR_SHIFT)
+#define ES8388_DAC_INVR_180INV  (1 << ES8388_DAC_INVR_SHIFT)
+
+#define ES8388_DAC_INVL_SHIFT   (5)
+#define ES8388_DAC_INVL_BITMASK (0x01 << ES8388_DAC_INVL_SHIFT)
+#define ES8388_DAC_INVL_NOINV   (0 << ES8388_DAC_INVL_SHIFT)
+#define ES8388_DAC_INVL_180INV  (1 << ES8388_DAC_INVL_SHIFT)
+
+#define ES8388_DEEMP_SHIFT   (6)
+#define ES8388_DEEMP_BITMASK (0x03 << ES8388_DEEMP_SHIFT)
+#define ES8388_DEEMP_DISABLE (0 << ES8388_DEEMP_SHIFT)
+#define ES8388_DEEMP_32KHZ   (1 << ES8388_DEEMP_SHIFT)
+#define ES8388_DEEMP_44KHZ   (2 << ES8388_DEEMP_SHIFT)
+#define ES8388_DEEMP_48KHZ   (3 << ES8388_DEEMP_SHIFT)
+
+/* 0x1d DAC Control 7 */
+
+#define ES8388_VPP_SCALE_SHIFT   (0)
+#define ES8388_VPP_SCALE_BITMASK (0x03 << ES8388_VPP_SCALE_SHIFT)
+#define ES8388_VPP_SCALE_3_5V    (0 << ES8388_VPP_SCALE_SHIFT)
+#define ES8388_VPP_SCALE_4_0V    (1 << ES8388_VPP_SCALE_SHIFT)
+#define ES8388_VPP_SCALE_3_0V    (2 << ES8388_VPP_SCALE_SHIFT)
+#define ES8388_VPP_SCALE_2_5V    (3 << ES8388_VPP_SCALE_SHIFT)
+
+#define ES8388_SE_SHIFT   (2)
+#define ES8388_SE_BITMASK (0x07 << ES8388_SE_SHIFT)
+#define ES8388_SE(a)      (a << ES8388_SE_SHIFT)
+
+#define ES8388_MONO_SHIFT   (5)
+#define ES8388_MONO_BITMASK (0x01 << ES8388_MONO_SHIFT)
+#define ES8388_MONO_STEREO  (0 << ES8388_MONO_SHIFT)
+#define ES8388_MONO_MONO    (1 << ES8388_MONO_SHIFT)
+
+#define ES8388_ZEROR_SHIFT   (6)
+#define ES8388_ZEROR_BITMASK (0x01 << ES8388_ZEROR_SHIFT)
+#define ES8388_ZEROR_NORMAL  (0 << ES8388_ZEROR_SHIFT)
+#define ES8388_ZEROR_ZERO    (1 << ES8388_ZEROR_SHIFT)
+
+#define ES8388_ZEROL_SHIFT   (7)
+#define ES8388_ZEROL_BITMASK (0x01 << ES8388_ZEROL_SHIFT)
+#define ES8388_ZEROL_NORMAL  (0 << ES8388_ZEROL_SHIFT)
+#define ES8388_ZEROL_ZERO    (1 << ES8388_ZEROL_SHIFT)
+
+/* 0x1e DAC Control 8
+ * 0x1f DAC Control 9
+ * 0x20 DAC Control 10
+ * 0x21 DAC Control 11
+ * 0x22 DAC Control 12
+ * 0x23 DAC Control 13
+ * 0x24 DAC Control 14
+ * 0x25 DAC Control 15
+ */
+
+#define ES8388_SHELVING_COEF_SHIFT   (0)
+#define ES8388_SHELVING_COEF_BITMASK (0xff << ES8388_SHELVING_COEF_SHIFT)
+#define ES8388_SHELVING_COEF(a)      (a << ES8388_SHELVING_COEF_SHIFT)
+
+/* 0x26 DAC Control 16 */
+
+#define ES8388_RMIXSEL_SHIFT   (0)
+#define ES8388_RMIXSEL_BITMASK (0x07 << ES8388_RMIXSEL_SHIFT)
+#define ES8388_RMIXSEL_RIN1    (0 << ES8388_RMIXSEL_SHIFT)
+#define ES8388_RMIXSEL_RIN2    (1 << ES8388_RMIXSEL_SHIFT)
+#define ES8388_RMIXSEL_PIN     (3 << ES8388_RMIXSEL_SHIFT)
+#define ES8388_RMIXSEL_NIN     (4 << ES8388_RMIXSEL_SHIFT)
+
+#define ES8388_LMIXSEL_SHIFT   (3)
+#define ES8388_LMIXSEL_BITMASK (0x07 << ES8388_LMIXSEL_SHIFT)
+#define ES8388_LMIXSEL_LIN1    (0 << ES8388_LMIXSEL_SHIFT)
+#define ES8388_LMIXSEL_LIN2    (1 << ES8388_LMIXSEL_SHIFT)
+#define ES8388_LMIXSEL_PIN     (3 << ES8388_LMIXSEL_SHIFT)
+#define ES8388_LMIXSEL_NIN     (4 << ES8388_LMIXSEL_SHIFT)
+
+/* 0x27 DAC Control 17 */
+
+#define ES8388_LI2LOVOL_SHIFT   (3)
+#define ES8388_LI2LOVOL_BITMASK (0x07 << ES8388_LI2LOVOL_SHIFT)
+#define ES8388_LI2LOVOL(a)      (a << ES8388_LI2LOVOL_SHIFT)
+
+#define ES8388_LI2LO_SHIFT   (6)
+#define ES8388_LI2LO_BITMASK (0x01 << ES8388_LI2LO_SHIFT)
+#define ES8388_LI2LO_DISABLE (0 << ES8388_LI2LO_SHIFT)
+#define ES8388_LI2LO_ENABLE  (1 << ES8388_LI2LO_SHIFT)
+
+#define ES8388_LD2LO_SHIFT   (7)
+#define ES8388_LD2LO_BITMASK (0x01 << ES8388_LD2LO_SHIFT)
+#define ES8388_LD2LO_DISABLE (0 << ES8388_LD2LO_SHIFT)
+#define ES8388_LD2LO_ENABLE  (1 << ES8388_LD2LO_SHIFT)
+
+/* 0x2a DAC Control 20 */
+
+#define ES8388_RI2ROVOL_SHIFT   (3)
+#define ES8388_RI2ROVOL_BITMASK (0x07 << ES8388_RI2ROVOL_SHIFT)
+#define ES8388_RI2ROVOL(a)      (a << ES8388_RI2ROVOL_SHIFT)
+
+#define ES8388_RI2RO_SHIFT   (6)
+#define ES8388_RI2RO_BITMASK (0x01 << ES8388_RI2RO_SHIFT)
+#define ES8388_RI2RO_DISABLE (0 << ES8388_RI2RO_SHIFT)
+#define ES8388_RI2RO_ENABLE  (1 << ES8388_RI2RO_SHIFT)
+
+#define ES8388_RD2RO_SHIFT   (7)
+#define ES8388_RD2RO_BITMASK (0x01 << ES8388_RD2RO_SHIFT)
+#define ES8388_RD2RO_DISABLE (0 << ES8388_RD2RO_SHIFT)
+#define ES8388_RD2RO_ENABLE  (1 << ES8388_RD2RO_SHIFT)
+
+/* 0x2b DAC Control 21 */
+
+#define ES8388_DAC_DLL_PWD_SHIFT   (2)
+#define ES8388_DAC_DLL_PWD_BITMASK (0x01 << ES8388_DAC_DLL_PWD_SHIFT)
+#define ES8388_DAC_DLL_PWD_NORMAL  (0 << ES8388_DAC_DLL_PWD_SHIFT)
+#define ES8388_DAC_DLL_PWD_PWRDN   (1 << ES8388_DAC_DLL_PWD_SHIFT)
+
+#define ES8388_ADC_DLL_PWD_SHIFT   (3)
+#define ES8388_ADC_DLL_PWD_BITMASK (0x01 << ES8388_ADC_DLL_PWD_SHIFT)
+#define ES8388_ADC_DLL_PWD_NORMAL  (0 << ES8388_ADC_DLL_PWD_SHIFT)
+#define ES8388_ADC_DLL_PWD_PWRDN   (1 << ES8388_ADC_DLL_PWD_SHIFT)
+
+#define ES8388_MCLK_DIS_SHIFT   (4)
+#define ES8388_MCLK_DIS_BITMASK (0x01 << ES8388_MCLK_DIS_SHIFT)
+#define ES8388_MCLK_DIS_NORMAL  (0 << ES8388_MCLK_DIS_SHIFT)
+#define ES8388_MCLK_DIS_DISABLE (1 << ES8388_MCLK_DIS_SHIFT)
+
+#define ES8388_OFFSET_DIS_SHIFT   (5)
+#define ES8388_OFFSET_DIS_BITMASK (0x01 << ES8388_OFFSET_DIS_SHIFT)
+#define ES8388_OFFSET_DIS_DISABLE (0 << ES8388_OFFSET_DIS_SHIFT)
+#define ES8388_OFFSET_DIS_ENABLE  (1 << ES8388_OFFSET_DIS_SHIFT)
+
+#define ES8388_LRCK_SEL_SHIFT   (6)
+#define ES8388_LRCK_SEL_BITMASK (0x01 << ES8388_LRCK_SEL_SHIFT)
+#define ES8388_LRCK_SEL_DAC     (0 << ES8388_LRCK_SEL_SHIFT)
+#define ES8388_LRCK_SEL_ADC     (1 << ES8388_LRCK_SEL_SHIFT)
+
+#define ES8388_SLRCK_SHIFT    (7)
+#define ES8388_SLRCK_BITMASK  (0x01 << ES8388_SLRCK_SHIFT)
+#define ES8388_SLRCK_SEPARATE (0 << ES8388_SLRCK_SHIFT)
+#define ES8388_SLRCK_SAME     (1 << ES8388_SLRCK_SHIFT)
+
+/* 0x2c DAC Control 22 */
+
+#define ES8388_OFFSET_SHIFT   (0)
+#define ES8388_OFFSET_BITMASK (0xff << ES8388_OFFSET_SHIFT)
+#define ES8388_OFFSET(a)      (a << ES8388_OFFSET_SHIFT)
+
+/* 0x2d DAC Control 23 */
+
+#define ES8388_VROI_SHIFT   (4)
+#define ES8388_VROI_BITMASK (0x01 << ES8388_VROI_SHIFT)
+#define ES8388_VROI_1_5K    (0 << ES8388_VROI_SHIFT)
+#define ES8388_VROI_40K     (1 << ES8388_VROI_SHIFT)
+
+/* 0x2e DAC Control 24 */
+
+#define ES8388_LOUT1VOL_SHIFT   (0)
+#define ES8388_LOUT1VOL_BITMASK (0x3f << ES8388_LOUT1VOL_SHIFT)
+#define ES8388_LOUT1VOL(a)      (a << ES8388_LOUT1VOL_SHIFT)
+
+/* 0x2f DAC Control 25 */
+
+#define ES8388_ROUT1VOL_SHIFT   (0)
+#define ES8388_ROUT1VOL_BITMASK (0x3f << ES8388_ROUT1VOL_SHIFT)
+#define ES8388_ROUT1VOL(a)      (a << ES8388_ROUT1VOL_SHIFT)
+
+/* 0x30 DAC Control 26 */
+
+#define ES8388_LOUT2VOL_SHIFT   (0)
+#define ES8388_LOUT2VOL_BITMASK (0x3f << ES8388_LOUT2VOL_SHIFT)
+#define ES8388_LOUT2VOL(a)      (a << ES8388_LOUT2VOL_SHIFT)
+
+/* 0x31 DAC Control 27 */
+
+#define ES8388_ROUT2VOL_SHIFT   (0)
+#define ES8388_ROUT2VOL_BITMASK (0x3f << ES8388_ROUT2VOL_SHIFT)
+#define ES8388_ROUT2VOL(a)      (a << ES8388_ROUT2VOL_SHIFT)
+
+/* Codec Default Parameters *************************************************/
+
+#define ES8388_DEFAULT_SAMPRATE   44100
+#define ES8388_DEFAULT_NCHANNELS  2
+#define ES8388_DEFAULT_BPSAMP     16
+#define ES8388_DEFAULT_VOL_OUT    250
+#define ES8388_DEFAULT_VOL_IN     1000
+#define ES8388_DEFAULT_BALANCE    500
+#define ES8388_DEFAULT_MUTE       true
+#define ES8388_DEFAULT_AUDIO_MODE ES_MODULE_ADC_DAC
+#define ES8388_DEFAULT_DAC_OUTPUT ES8388_DAC_OUTPUT_ALL
+#define ES8388_DEFAULT_ADC_INPUT  ES8388_ADC_INPUT_LINE1
+#define ES8388_DEFAULT_MIC_GAIN   ES_MIC_GAIN_24DB
+#define ES8388_DEFAULT_MODE       ES_MODE_SLAVE
+#define ES8388_DEFAULT_FMT        ES_I2S_NORMAL
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+typedef enum {
+  ES8388_DAC_OUTPUT_LINE1,
+  ES8388_DAC_OUTPUT_LINE2,
+  ES8388_DAC_OUTPUT_ALL,
+} es8388_dac_output_e;
+
+typedef enum {
+  ES8388_ADC_INPUT_LINE1,
+  ES8388_ADC_INPUT_LINE2,
+  ES8388_ADC_INPUT_ALL,
+  ES8388_ADC_INPUT_DIFFERENCE,
+} es8388_adc_input_e;
+
+typedef enum {
+  ES8388_MIXER_GAIN_6DB,
+  ES8388_MIXER_GAIN_3DB,
+  ES8388_MIXER_GAIN_0DB,
+  ES8388_MIXER_GAIN_N3DB,
+  ES8388_MIXER_GAIN_N6DB,
+  ES8388_MIXER_GAIN_N9DB,
+  ES8388_MIXER_GAIN_N12DB,
+  ES8388_MIXER_GAIN_N15DB,
+} es8388_mixer_gain_e;
+
+typedef enum {
+  ES_WORD_LENGTH_16BITS = 0x03,
+  ES_WORD_LENGTH_18BITS = 0x02,
+  ES_WORD_LENGTH_20BITS = 0x01,
+  ES_WORD_LENGTH_24BITS = 0x00,
+  ES_WORD_LENGTH_32BITS = 0x04
+} es_word_length_e;
+
+typedef enum {
+  ES_MCLK_DIV_AUTO,
+  ES_MCLK_DIV_1,
+  ES_MCLK_DIV_2,
+  ES_MCLK_DIV_3,
+  ES_MCLK_DIV_4,
+  ES_MCLK_DIV_6,
+  ES_MCLK_DIV_8,
+  ES_MCLK_DIV_9,
+  ES_MCLK_DIV_11,
+  ES_MCLK_DIV_12,
+  ES_MCLK_DIV_16,
+  ES_MCLK_DIV_18,
+  ES_MCLK_DIV_22,
+  ES_MCLK_DIV_24,
+  ES_MCLK_DIV_33,
+  ES_MCLK_DIV_36,
+  ES_MCLK_DIV_44,
+  ES_MCLK_DIV_48,
+  ES_MCLK_DIV_66,
+  ES_MCLK_DIV_72,
+  ES_MCLK_DIV_5,
+  ES_MCLK_DIV_10,
+  ES_MCLK_DIV_15,
+  ES_MCLK_DIV_17,
+  ES_MCLK_DIV_20,
+  ES_MCLK_DIV_25,
+  ES_MCLK_DIV_30,
+  ES_MCLK_DIV_32,
+  ES_MCLK_DIV_34,
+  ES_MCLK_DIV_7,
+  ES_MCLK_DIV_13,
+  ES_MCLK_DIV_14
+} es_sclk_div_e;
+
+typedef enum {
+  ES_LCLK_DIV_128 = 0,
+  ES_LCLK_DIV_192 = 1,
+  ES_LCLK_DIV_256 = 2,
+  ES_LCLK_DIV_384 = 3,
+  ES_LCLK_DIV_512 = 4,
+  ES_LCLK_DIV_576 = 5,
+  ES_LCLK_DIV_768 = 6,
+  ES_LCLK_DIV_1024 = 7,
+  ES_LCLK_DIV_1152 = 8,
+  ES_LCLK_DIV_1408 = 9,
+  ES_LCLK_DIV_1536 = 10,
+  ES_LCLK_DIV_2112 = 11,
+  ES_LCLK_DIV_2304 = 12,
+  ES_LCLK_DIV_125 = 16,
+  ES_LCLK_DIV_136 = 17,
+  ES_LCLK_DIV_250 = 18,
+  ES_LCLK_DIV_272 = 19,
+  ES_LCLK_DIV_375 = 20,
+  ES_LCLK_DIV_500 = 21,
+  ES_LCLK_DIV_544 = 22,
+  ES_LCLK_DIV_750 = 23,
+  ES_LCLK_DIV_1000 = 24,
+  ES_LCLK_DIV_1088 = 25,
+  ES_LCLK_DIV_1496 = 26,
+  ES_LCLK_DIV_1500 = 27
+} es_lclk_div_e;
+
+typedef enum {
+  ES_D2SE_PGA_GAIN_DIS,
+  ES_D2SE_PGA_GAIN_EN
+} es_d2se_pga_e;
+
+typedef enum {
+  ES_ADC_CHANNEL_LINPUT1_RINPUT1 = 0x00,
+  ES_ADC_CHANNEL_MIC1 = 0x05,
+  ES_ADC_CHANNEL_MIC2 = 0x06,
+  ES_ADC_CHANNEL_LINPUT2_RINPUT2 = 0x50,
+  ES_ADC_CHANNEL_DIFFERENCE = 0xf0
+} es_adc_channel_e;
+
+typedef enum {
+  ES_DAC_CHANNEL_LOUT1 = 0x04,
+  ES_DAC_CHANNEL_LOUT2 = 0x08,
+  ES_DAC_CHANNEL_SPK = 0x09,
+  ES_DAC_CHANNEL_ROUT1 = 0x10,
+  ES_DAC_CHANNEL_ROUT2 = 0x20,
+  ES_DAC_CHANNEL_ALL = 0x3c
+} es_dac_channel_e;
+
+typedef enum {
+  ES_MIC_GAIN_0DB,
+  ES_MIC_GAIN_3DB,
+  ES_MIC_GAIN_6DB,
+  ES_MIC_GAIN_9DB,
+  ES_MIC_GAIN_12DB,
+  ES_MIC_GAIN_15DB,
+  ES_MIC_GAIN_18DB,
+  ES_MIC_GAIN_21DB,
+  ES_MIC_GAIN_24DB
+} es_mic_gain_e;
+
+typedef enum {
+  ES_MODULE_ADC = 1,
+  ES_MODULE_DAC,
+  ES_MODULE_ADC_DAC,
+  ES_MODULE_LINE
+} es_module_e;
+
+typedef enum {
+  ES_MODE_SLAVE,
+  ES_MODE_MASTER
+} es_mode_e;
+
+typedef enum {
+  ES_I2S_NORMAL,
+  ES_I2S_LEFT,
+  ES_I2S_RIGHT,
+  ES_I2S_DSP
+} es_i2s_fmt_e;
+
+/****************************************************************************
+ * Class Definitions
+ ****************************************************************************/
+
+class ES8388 {
+private:
+  TwoWire *_i2c;                   /* The I2C bus */
+  I2SClass *_i2s;                  /* The I2S bus */
+  uint8_t _addr;                   /* The I2C address */
+  es_i2s_fmt_e _fmt;               /* The current I2S format */
+  es_mode_e _mode;                 /* The current codec mode */
+  uint32_t _samprate;              /* Configured samprate (samples/sec) */
+  uint16_t _balance;               /* Current balance level {0..1000} */
+  uint16_t _volume_out;            /* Current output volume level {0..1000} */
+  uint16_t _volume_in;             /* Current input volume level {0..1000} */
+  uint8_t _nchannels;              /* Number of channels (1 or 2) */
+  uint8_t _bpsamp;                 /* Bits per sample */
+  bool _mute;                      /* True: Output is muted */
+  es_module_e _audio_mode;         /* The current audio mode of the ES8388 chip */
+  es8388_dac_output_e _dac_output; /* The current output of the ES8388 DAC */
+  es8388_adc_input_e _adc_input;   /* The current input of the ES8388 ADC */
+  es_mic_gain_e _mic_gain;         /* The current microphone gain */
+  bool _running;                   /* True: The ES8388 is running */
+  es_lclk_div_e _lclk_div;         /* The current LCLK divider */
+  es_word_length_e _word_length;   /* The current word length (enum of _bpsamp) */
+
+  void reset();
+  void start();
+  void stop();
+  void setvolume(es_module_e module, uint16_t volume, uint16_t balance);
+  void setmute(es_module_e module, bool enable);
+
+public:
+  ~ES8388();
+  bool begin(I2SClass &i2s, TwoWire &i2c = Wire, uint8_t addr = 0x10);
+  void end();
+  void playWAV(uint8_t *data, size_t len);
+  uint8_t *recordWAV(size_t rec_seconds, size_t *out_size);
+  uint8_t readReg(uint8_t reg);
+  void writeReg(uint8_t reg, uint8_t data);
+  void setOutputVolume(uint16_t volume, uint16_t balance);
+  void setInputVolume(uint16_t volume, uint16_t balance);
+  void setOutputMute(bool enable);
+  void setInputMute(bool enable);
+  void setBitsPerSample(uint8_t bpsamp);
+  void setSampleRate(uint32_t rate);
+  void setMicGain(uint8_t gain);
+};
diff --git a/libraries/ESP_I2S/examples/ES8388_loopback/ES8388_loopback.ino b/libraries/ESP_I2S/examples/ES8388_loopback/ES8388_loopback.ino
new file mode 100644
index 00000000000..43232be8354
--- /dev/null
+++ b/libraries/ESP_I2S/examples/ES8388_loopback/ES8388_loopback.ino
@@ -0,0 +1,85 @@
+/*
+  ESP32-LyraT I2S ES8388 loopback example
+  This simple example demonstrates using the I2S library in combination
+  with the ES8388 codec on the ESP32-LyraT board to record and play back
+  audio data.
+
+  Don't forget to enable the PSRAM in the Tools menu!
+
+  Created for arduino-esp32 on 20 Dec, 2023
+  by Lucas Saavedra Vaz (lucasssvaz)
+*/
+
+#include "ESP_I2S.h"
+#include "Wire.h"
+
+#include "ES8388.h"
+
+/* Pin definitions */
+
+/* I2C */
+const uint8_t I2C_SCL = 23;
+const uint8_t I2C_SDA = 18;
+const uint32_t I2C_FREQ = 400000;
+
+/* I2S */
+const uint8_t I2S_MCLK = 0;   /* Master clock */
+const uint8_t I2S_SCK = 5;    /* Audio data bit clock */
+const uint8_t I2S_WS = 25;    /* Audio data left and right clock */
+const uint8_t I2S_SDOUT = 26; /* ESP32 audio data output (to speakers) */
+const uint8_t I2S_SDIN = 35;  /* ESP32 audio data input (from microphone) */
+
+/* PA */
+const uint8_t PA_ENABLE = 21; /* Power amplifier enable */
+
+void setup() {
+  I2SClass i2s;
+  ES8388 codec;
+  uint8_t *wav_buffer;
+  size_t wav_size;
+
+  // Initialize the serial port
+  Serial.begin(115200);
+
+  pinMode(PA_ENABLE, OUTPUT);
+  digitalWrite(PA_ENABLE, HIGH);
+
+  Serial.println("Initializing I2C bus...");
+
+  // Initialize the I2C bus
+  Wire.begin(I2C_SDA, I2C_SCL, I2C_FREQ);
+
+  Serial.println("Initializing I2S bus...");
+
+  // Set up the pins used for audio input
+  i2s.setPins(I2S_SCK, I2S_WS, I2S_SDOUT, I2S_SDIN, I2S_MCLK);
+
+  // Initialize the I2S bus in standard mode
+  if (!i2s.begin(I2S_MODE_STD, 44100, I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO, I2S_STD_SLOT_BOTH)) {
+    Serial.println("Failed to initialize I2S bus!");
+    return;
+  }
+
+  Serial.println("Initializing ES8388...");
+
+  if (!codec.begin(i2s)) {
+    Serial.println("Failed to initialize ES8388!");
+    return;
+  }
+
+  Serial.println("Recording 10 seconds of audio data...");
+
+  // Record 10 seconds of audio data
+  wav_buffer = codec.recordWAV(10, &wav_size);
+
+  Serial.println("Recording complete. Playing audio data in 3 seconds.");
+  delay(3000);
+
+  // Play the audio data
+  Serial.println("Playing audio data...");
+  codec.playWAV(wav_buffer, wav_size);
+
+  Serial.println("Application complete.");
+}
+
+void loop() {}
diff --git a/libraries/ESP_I2S/examples/ES8388_loopback/ci.json b/libraries/ESP_I2S/examples/ES8388_loopback/ci.json
new file mode 100644
index 00000000000..e0f64e28943
--- /dev/null
+++ b/libraries/ESP_I2S/examples/ES8388_loopback/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_SOC_I2S_SUPPORTED=y",
+    "CONFIG_SOC_I2C_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP_I2S/examples/Record_to_WAV/Record_to_WAV.ino b/libraries/ESP_I2S/examples/Record_to_WAV/Record_to_WAV.ino
new file mode 100644
index 00000000000..e8f09554cb8
--- /dev/null
+++ b/libraries/ESP_I2S/examples/Record_to_WAV/Record_to_WAV.ino
@@ -0,0 +1,89 @@
+/*
+  ESP32-S2-EYE I2S record to WAV example
+  This simple example demonstrates using the I2S library to record
+  5 seconds of audio data and write it to a WAV file on the SD card.
+
+  Don't forget to select the OPI PSRAM, 8MB flash size and Enable USB CDC
+  on boot in the Tools menu!
+
+  Created for arduino-esp32 on 18 Dec, 2023
+  by Lucas Saavedra Vaz (lucasssvaz)
+*/
+
+#include "ESP_I2S.h"
+#include "FS.h"
+#include "SD_MMC.h"
+
+const uint8_t I2S_SCK = 41;
+const uint8_t I2S_WS = 42;
+const uint8_t I2S_DIN = 2;
+
+const uint8_t SD_CMD = 38;
+const uint8_t SD_CLK = 39;
+const uint8_t SD_DATA0 = 40;
+
+void setup() {
+  // Create an instance of the I2SClass
+  I2SClass i2s;
+
+  // Create variables to store the audio data
+  uint8_t *wav_buffer;
+  size_t wav_size;
+
+  // Initialize the serial port
+  Serial.begin(115200);
+
+  Serial.println("Initializing I2S bus...");
+
+  // Set up the pins used for audio input
+  i2s.setPins(I2S_SCK, I2S_WS, -1, I2S_DIN);
+
+  // Initialize the I2S bus in standard mode
+  if (!i2s.begin(I2S_MODE_STD, 16000, I2S_DATA_BIT_WIDTH_32BIT, I2S_SLOT_MODE_MONO, I2S_STD_SLOT_LEFT)) {
+    Serial.println("Failed to initialize I2S bus!");
+    return;
+  }
+
+  Serial.println("I2S bus initialized.");
+  Serial.println("Initializing SD card...");
+
+  // Set up the pins used for SD card access
+  if (!SD_MMC.setPins(SD_CLK, SD_CMD, SD_DATA0)) {
+    Serial.println("Failed to set SD pins!");
+    return;
+  }
+
+  // Mount the SD card
+  if (!SD_MMC.begin("/sdcard", true)) {
+    Serial.println("Failed to initialize SD card!");
+    return;
+  }
+
+  Serial.println("SD card initialized.");
+  Serial.println("Recording 5 seconds of audio data...");
+
+  // Record 5 seconds of audio data
+  wav_buffer = i2s.recordWAV(5, &wav_size);
+
+  // Create a file on the SD card
+  File file = SD_MMC.open("/test.wav", FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing!");
+    return;
+  }
+
+  Serial.println("Writing audio data to file...");
+
+  // Write the audio data to the file
+  if (file.write(wav_buffer, wav_size) != wav_size) {
+    Serial.println("Failed to write audio data to file!");
+    return;
+  }
+
+  // Close the file
+  file.close();
+
+  Serial.println("Application complete.");
+}
+
+void loop() {}
diff --git a/libraries/ESP_I2S/examples/Record_to_WAV/ci.json b/libraries/ESP_I2S/examples/Record_to_WAV/ci.json
new file mode 100644
index 00000000000..a45dc2f0120
--- /dev/null
+++ b/libraries/ESP_I2S/examples/Record_to_WAV/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_SOC_SDMMC_HOST_SUPPORTED=y",
+    "CONFIG_SOC_I2S_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP_I2S/examples/Simple_tone/Simple_tone.ino b/libraries/ESP_I2S/examples/Simple_tone/Simple_tone.ino
new file mode 100644
index 00000000000..935aa4bc50f
--- /dev/null
+++ b/libraries/ESP_I2S/examples/Simple_tone/Simple_tone.ino
@@ -0,0 +1,68 @@
+/*
+ This example generates a square wave based tone at a specified frequency
+ and sample rate. Then outputs the data using the I2S interface to a
+ MAX08357 I2S Amp Breakout board.
+ I2S Circuit:
+ * Arduino/Genuino Zero, MKR family and Nano 33 IoT
+ * MAX08357:
+   * GND connected GND
+   * VIN connected 5V
+   * LRC connected to pin 0 (Zero) or 3 (MKR), A2 (Nano) or 25 (ESP32)
+   * BCLK connected to pin 1 (Zero) or 2 (MKR), A3 (Nano) or 5 (ESP32)
+   * DIN connected to pin 9 (Zero) or A6 (MKR), 4 (Nano) or 26 (ESP32)
+ DAC Circuit:
+ * ESP32 or ESP32-S2
+ * Audio amplifier
+   - Note:
+     - ESP32 has DAC on GPIO pins 25 and 26.
+     - ESP32-S2 has DAC on GPIO pins 17 and 18.
+  - Connect speaker(s) or headphones.
+ created 17 November 2016
+ by Sandeep Mistry
+ For ESP extended
+ Tomas Pilny
+ 2nd September 2021
+ Lucas Saavedra Vaz (lucasssvaz)
+ 22nd December 2023
+ */
+
+#include <ESP_I2S.h>
+
+const int frequency = 440;    // frequency of square wave in Hz
+const int amplitude = 500;    // amplitude of square wave
+const int sampleRate = 8000;  // sample rate in Hz
+
+i2s_data_bit_width_t bps = I2S_DATA_BIT_WIDTH_16BIT;
+i2s_mode_t mode = I2S_MODE_STD;
+i2s_slot_mode_t slot = I2S_SLOT_MODE_STEREO;
+
+const int halfWavelength = (sampleRate / frequency);  // half wavelength of square wave
+
+int32_t sample = amplitude;  // current sample value
+int count = 0;
+
+I2SClass i2s;
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("I2S simple tone");
+
+  // start I2S at the sample rate with 16-bits per sample
+  if (!i2s.begin(mode, sampleRate, bps, slot)) {
+    Serial.println("Failed to initialize I2S!");
+    while (1);  // do nothing
+  }
+}
+
+void loop() {
+  if (count % halfWavelength == 0) {
+    // invert the sample every half wavelength count multiple to generate square wave
+    sample = -1 * sample;
+  }
+
+  i2s.write(sample);  // Right channel
+  i2s.write(sample);  // Left channel
+
+  // increment the counter for the next sample
+  count++;
+}
diff --git a/libraries/ESP_I2S/examples/Simple_tone/ci.json b/libraries/ESP_I2S/examples/Simple_tone/ci.json
new file mode 100644
index 00000000000..9842f2f9b2a
--- /dev/null
+++ b/libraries/ESP_I2S/examples/Simple_tone/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_I2S_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP_I2S/keywords.txt b/libraries/ESP_I2S/keywords.txt
new file mode 100644
index 00000000000..f30b7ad1d9a
--- /dev/null
+++ b/libraries/ESP_I2S/keywords.txt
@@ -0,0 +1,21 @@
+#######################################
+# Syntax Coloring Map For ESP_I2S
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+ESP_I2S	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+onEvent	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+
+SR_EVENT_WAKEWORD	LITERAL1
diff --git a/libraries/ESP_I2S/library.properties b/libraries/ESP_I2S/library.properties
new file mode 100644
index 00000000000..263e9823275
--- /dev/null
+++ b/libraries/ESP_I2S/library.properties
@@ -0,0 +1,9 @@
+name=ESP_I2S
+version=3.2.0
+author=me-no-dev
+maintainer=me-no-dev
+sentence=Library for ESP I2S communication
+paragraph=Supports ESP32 Arduino platforms.
+category=Sound
+url=https://github.com/espressif/arduino-esp32/
+architectures=esp32
diff --git a/libraries/ESP_I2S/src/ESP_I2S.cpp b/libraries/ESP_I2S/src/ESP_I2S.cpp
new file mode 100644
index 00000000000..6bf8089e48a
--- /dev/null
+++ b/libraries/ESP_I2S/src/ESP_I2S.cpp
@@ -0,0 +1,1071 @@
+// Disable the automatic pin remapping of the API calls in this file
+#define ARDUINO_CORE_BUILD
+
+#include "ESP_I2S.h"
+
+#if SOC_I2S_SUPPORTED
+
+#include "esp32-hal-periman.h"
+#include "wav_header.h"
+#if ARDUINO_HAS_MP3_DECODER
+#include "mp3dec.h"
+#endif
+
+#if SOC_I2S_HW_VERSION_2
+#undef I2S_STD_CLK_DEFAULT_CONFIG
+#define I2S_STD_CLK_DEFAULT_CONFIG(rate) \
+  { .sample_rate_hz = rate, .clk_src = I2S_CLK_SRC_DEFAULT, .ext_clk_freq_hz = 0, .mclk_multiple = I2S_MCLK_MULTIPLE_256, }
+#endif
+
+#define I2S_READ_CHUNK_SIZE 1920
+
+#define I2S_DEFAULT_CFG()                                                                                                                    \
+  {                                                                                                                                          \
+    .id = I2S_NUM_AUTO, .role = I2S_ROLE_MASTER, .dma_desc_num = 6, .dma_frame_num = 240, .auto_clear = true, .auto_clear_before_cb = false, \
+    .intr_priority = 0                                                                                                                       \
+  }
+
+#define I2S_STD_CHAN_CFG(_sample_rate, _data_bit_width, _slot_mode)                                                                   \
+  {                                                                                                                                   \
+    .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(_sample_rate), .slot_cfg = I2S_STD_PHILIP_SLOT_DEFAULT_CONFIG(_data_bit_width, _slot_mode), \
+    .gpio_cfg = {                                                                                                                     \
+      .mclk = (gpio_num_t)_mclk,                                                                                                      \
+      .bclk = (gpio_num_t)_bclk,                                                                                                      \
+      .ws = (gpio_num_t)_ws,                                                                                                          \
+      .dout = (gpio_num_t)_dout,                                                                                                      \
+      .din = (gpio_num_t)_din,                                                                                                        \
+      .invert_flags =                                                                                                                 \
+        {                                                                                                                             \
+          .mclk_inv = _mclk_inv,                                                                                                      \
+          .bclk_inv = _bclk_inv,                                                                                                      \
+          .ws_inv = _ws_inv,                                                                                                          \
+        },                                                                                                                            \
+    },                                                                                                                                \
+  }
+
+#if SOC_I2S_SUPPORTS_TDM
+#define I2S_TDM_CHAN_CFG(_sample_rate, _data_bit_width, _slot_mode, _mask)                                                                   \
+  {                                                                                                                                          \
+    .clk_cfg = I2S_TDM_CLK_DEFAULT_CONFIG(_sample_rate), .slot_cfg = I2S_TDM_PHILIP_SLOT_DEFAULT_CONFIG(_data_bit_width, _slot_mode, _mask), \
+    .gpio_cfg = {                                                                                                                            \
+      .mclk = (gpio_num_t)_mclk,                                                                                                             \
+      .bclk = (gpio_num_t)_bclk,                                                                                                             \
+      .ws = (gpio_num_t)_ws,                                                                                                                 \
+      .dout = (gpio_num_t)_dout,                                                                                                             \
+      .din = (gpio_num_t)_din,                                                                                                               \
+      .invert_flags =                                                                                                                        \
+        {                                                                                                                                    \
+          .mclk_inv = _mclk_inv,                                                                                                             \
+          .bclk_inv = _bclk_inv,                                                                                                             \
+          .ws_inv = _ws_inv,                                                                                                                 \
+        },                                                                                                                                   \
+    },                                                                                                                                       \
+  }
+#endif
+#if SOC_I2S_SUPPORTS_PDM_TX
+#if (SOC_I2S_PDM_MAX_TX_LINES > 1)
+#define I2S_PDM_TX_CHAN_CFG(_sample_rate, _data_bit_width, _slot_mode)                                                               \
+  {                                                                                                                                  \
+    .clk_cfg = I2S_PDM_TX_CLK_DEFAULT_CONFIG(_sample_rate), .slot_cfg = I2S_PDM_TX_SLOT_DEFAULT_CONFIG(_data_bit_width, _slot_mode), \
+    .gpio_cfg = {                                                                                                                    \
+      .clk = (gpio_num_t)_tx_clk,                                                                                                    \
+      .dout = (gpio_num_t)_tx_dout0,                                                                                                 \
+      .dout2 = (gpio_num_t)_tx_dout1,                                                                                                \
+      .invert_flags =                                                                                                                \
+        {                                                                                                                            \
+          .clk_inv = _tx_clk_inv,                                                                                                    \
+        },                                                                                                                           \
+    },                                                                                                                               \
+  }
+#else
+#define I2S_PDM_TX_CHAN_CFG(_sample_rate, _data_bit_width, _slot_mode)                                                               \
+  {                                                                                                                                  \
+    .clk_cfg = I2S_PDM_TX_CLK_DEFAULT_CONFIG(_sample_rate), .slot_cfg = I2S_PDM_TX_SLOT_DEFAULT_CONFIG(_data_bit_width, _slot_mode), \
+    .gpio_cfg = {                                                                                                                    \
+      .clk = (gpio_num_t)_tx_clk,                                                                                                    \
+      .dout = (gpio_num_t)_tx_dout0,                                                                                                 \
+      .invert_flags =                                                                                                                \
+        {                                                                                                                            \
+          .clk_inv = _tx_clk_inv,                                                                                                    \
+        },                                                                                                                           \
+    },                                                                                                                               \
+  }
+#endif
+#endif
+
+#if SOC_I2S_SUPPORTS_PDM_RX
+#if (SOC_I2S_PDM_MAX_RX_LINES > 1)
+#define I2S_PDM_RX_CHAN_CFG(_sample_rate, _data_bit_width, _slot_mode)                                                               \
+  {                                                                                                                                  \
+    .clk_cfg = I2S_PDM_RX_CLK_DEFAULT_CONFIG(_sample_rate), .slot_cfg = I2S_PDM_RX_SLOT_DEFAULT_CONFIG(_data_bit_width, _slot_mode), \
+    .gpio_cfg = {                                                                                                                    \
+      .clk = (gpio_num_t)_rx_clk,                                                                                                    \
+      .dins =                                                                                                                        \
+        {                                                                                                                            \
+          (gpio_num_t)_rx_din0,                                                                                                      \
+          (gpio_num_t)_rx_din1,                                                                                                      \
+          (gpio_num_t)_rx_din2,                                                                                                      \
+          (gpio_num_t)_rx_din3,                                                                                                      \
+        },                                                                                                                           \
+      .invert_flags =                                                                                                                \
+        {                                                                                                                            \
+          .clk_inv = _rx_clk_inv,                                                                                                    \
+        },                                                                                                                           \
+    },                                                                                                                               \
+  }
+#else
+#define I2S_PDM_RX_CHAN_CFG(_sample_rate, _data_bit_width, _slot_mode)                                                               \
+  {                                                                                                                                  \
+    .clk_cfg = I2S_PDM_RX_CLK_DEFAULT_CONFIG(_sample_rate), .slot_cfg = I2S_PDM_RX_SLOT_DEFAULT_CONFIG(_data_bit_width, _slot_mode), \
+    .gpio_cfg = {                                                                                                                    \
+      .clk = (gpio_num_t)_rx_clk,                                                                                                    \
+      .din = (gpio_num_t)_rx_din0,                                                                                                   \
+      .invert_flags =                                                                                                                \
+        {                                                                                                                            \
+          .clk_inv = _rx_clk_inv,                                                                                                    \
+        },                                                                                                                           \
+    },                                                                                                                               \
+  }
+#endif
+#endif
+
+#define I2S_ERROR_CHECK_RETURN(x, r)                   \
+  do {                                                 \
+    last_error = (x);                                  \
+    if (unlikely(last_error != ESP_OK)) {              \
+      log_e("ERROR: %s", esp_err_to_name(last_error)); \
+      return (r);                                      \
+    }                                                  \
+  } while (0)
+#define I2S_ERROR_CHECK_RETURN_FALSE(x) I2S_ERROR_CHECK_RETURN(x, false)
+
+// Default read, no resmpling and temp buffer necessary
+static esp_err_t i2s_channel_read_default(i2s_chan_handle_t handle, char *tmp_buf, void *dst, size_t len, size_t *bytes_read, uint32_t timeout_ms) {
+  return i2s_channel_read(handle, (char *)dst, len, bytes_read, timeout_ms);
+}
+
+// Resample the 32bit SPH0645 microphone data into 16bit. SPH0645 is actually 18 bit, but this trick helps save some space
+static esp_err_t i2s_channel_read_32_to_16(i2s_chan_handle_t handle, char *read_buff, void *dst, size_t len, size_t *bytes_read, uint32_t timeout_ms) {
+  size_t out_len = 0;
+  size_t read_buff_len = len * 2;
+  if (read_buff == NULL) {
+    log_e("Temp buffer is NULL!");
+    return ESP_FAIL;
+  }
+  esp_err_t err = i2s_channel_read(handle, read_buff, read_buff_len, &out_len, timeout_ms);
+  if (err != ESP_OK) {
+    *bytes_read = 0;
+    return err;
+  }
+  out_len /= 4;
+  uint16_t *ds = (uint16_t *)dst;
+  uint32_t *src = (uint32_t *)read_buff;
+  for (size_t i = 0; i < out_len; i++) {
+    ds[i] = src[i] >> 16;
+  }
+  *bytes_read = out_len * 2;
+  return ESP_OK;
+}
+
+// Resample the 16bit stereo microphone data into 16bit mono.
+static esp_err_t i2s_channel_read_16_stereo_to_mono(i2s_chan_handle_t handle, char *read_buff, void *dst, size_t len, size_t *bytes_read, uint32_t timeout_ms) {
+  size_t out_len = 0;
+  size_t read_buff_len = len * 2;
+  if (read_buff == NULL) {
+    log_e("Temp buffer is NULL!");
+    return ESP_FAIL;
+  }
+  esp_err_t err = i2s_channel_read(handle, read_buff, read_buff_len, &out_len, timeout_ms);
+  if (err != ESP_OK) {
+    *bytes_read = 0;
+    return err;
+  }
+  out_len /= 2;
+  uint16_t *ds = (uint16_t *)dst;
+  uint16_t *src = (uint16_t *)read_buff;
+  for (size_t i = 0; i < out_len; i += 2) {
+    *ds++ = src[i];
+  }
+  *bytes_read = out_len;
+  return ESP_OK;
+}
+
+I2SClass::I2SClass() {
+  last_error = ESP_OK;
+
+  tx_chan = NULL;
+  tx_sample_rate = 0;
+  tx_data_bit_width = I2S_DATA_BIT_WIDTH_16BIT;
+  tx_slot_mode = I2S_SLOT_MODE_STEREO;
+
+  rx_fn = i2s_channel_read_default;
+  rx_transform = I2S_RX_TRANSFORM_NONE;
+  rx_transform_buf = NULL;
+  rx_transform_buf_len = 0;
+
+  rx_chan = NULL;
+  rx_sample_rate = 0;
+  rx_data_bit_width = I2S_DATA_BIT_WIDTH_16BIT;
+  rx_slot_mode = I2S_SLOT_MODE_STEREO;
+
+  _mclk = -1;
+  _bclk = -1;
+  _ws = -1;
+  _dout = -1;
+  _din = -1;
+  _mclk_inv = false;
+  _bclk_inv = false;
+  _ws_inv = false;
+
+#if SOC_I2S_SUPPORTS_PDM_TX
+  _tx_clk = -1;
+  _tx_dout0 = -1;
+  _tx_dout1 = -1;
+  _tx_clk_inv = false;
+#endif
+#if SOC_I2S_SUPPORTS_PDM_RX
+  _rx_clk = -1;
+  _rx_din0 = -1;
+  _rx_din1 = -1;
+  _rx_din2 = -1;
+  _rx_din3 = -1;
+  _rx_clk_inv = false;
+#endif
+}
+
+I2SClass::~I2SClass() {
+  end();
+}
+
+bool I2SClass::i2sDetachBus(void *bus_pointer) {
+  I2SClass *bus = (I2SClass *)bus_pointer;
+  if (bus->tx_chan != NULL || bus->tx_chan != NULL) {
+    bus->end();
+  }
+  return true;
+}
+
+// Set pins for STD and TDM mode
+void I2SClass::setPins(int8_t bclk, int8_t ws, int8_t dout, int8_t din, int8_t mclk) {
+  _mclk = digitalPinToGPIONumber(mclk);
+  _bclk = digitalPinToGPIONumber(bclk);
+  _ws = digitalPinToGPIONumber(ws);
+  _dout = digitalPinToGPIONumber(dout);
+  _din = digitalPinToGPIONumber(din);
+}
+
+void I2SClass::setInverted(bool bclk, bool ws, bool mclk) {
+  _mclk_inv = mclk;
+  _bclk_inv = bclk;
+  _ws_inv = ws;
+}
+
+// Set pins for PDM TX mode
+#if SOC_I2S_SUPPORTS_PDM_TX
+void I2SClass::setPinsPdmTx(int8_t clk, int8_t dout0, int8_t dout1) {
+  _tx_clk = digitalPinToGPIONumber(clk);
+  _tx_dout0 = digitalPinToGPIONumber(dout0);
+#if (SOC_I2S_PDM_MAX_TX_LINES > 1)
+  _tx_dout1 = digitalPinToGPIONumber(dout1);
+#endif
+}
+#endif
+
+// Set pins for PDM RX mode
+#if SOC_I2S_SUPPORTS_PDM_RX
+void I2SClass::setPinsPdmRx(int8_t clk, int8_t din0, int8_t din1, int8_t din2, int8_t din3) {
+  _rx_clk = digitalPinToGPIONumber(clk);
+  _rx_din0 = digitalPinToGPIONumber(din0);
+#if (SOC_I2S_PDM_MAX_RX_LINES > 1)
+  _rx_din1 = digitalPinToGPIONumber(din1);
+  _rx_din2 = digitalPinToGPIONumber(din2);
+  _rx_din3 = digitalPinToGPIONumber(din3);
+#endif
+}
+#endif
+
+#if SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX
+void I2SClass::setInvertedPdm(bool clk) {
+#if SOC_I2S_SUPPORTS_PDM_TX
+  _tx_clk_inv = clk;
+#endif
+#if SOC_I2S_SUPPORTS_PDM_RX
+  _rx_clk_inv = clk;
+#endif
+}
+#endif
+
+bool I2SClass::initSTD(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask) {
+  // Peripheral manager deinit previous peripheral if pin was used
+  if (_mclk >= 0) {
+    if (!perimanClearPinBus(_mclk)) {
+      return false;
+    }
+  }
+  if (_bclk >= 0) {
+    if (!perimanClearPinBus(_bclk)) {
+      return false;
+    }
+  }
+  if (_ws >= 0) {
+    if (!perimanClearPinBus(_ws)) {
+      return false;
+    }
+  }
+  if (_dout >= 0) {
+    if (!perimanClearPinBus(_dout)) {
+      return false;
+    }
+  }
+  if (_din >= 0) {
+    if (!perimanClearPinBus(_din)) {
+      return false;
+    }
+  }
+
+  // Set peripheral manager detach function for I2S
+  if (_mclk >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_STD_MCLK, I2SClass::i2sDetachBus);
+  }
+  if (_bclk >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_STD_BCLK, I2SClass::i2sDetachBus);
+  }
+  if (_ws >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_STD_WS, I2SClass::i2sDetachBus);
+  }
+  if (_dout >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_STD_DOUT, I2SClass::i2sDetachBus);
+  }
+  if (_din >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_STD_DIN, I2SClass::i2sDetachBus);
+  }
+
+  // I2S configuration
+  i2s_chan_config_t chan_cfg = I2S_DEFAULT_CFG();
+  if (_dout >= 0 && _din >= 0) {
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_new_channel(&chan_cfg, &tx_chan, &rx_chan));
+  } else if (_dout >= 0) {
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_new_channel(&chan_cfg, &tx_chan, NULL));
+  } else if (_din >= 0) {
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_new_channel(&chan_cfg, NULL, &rx_chan));
+  }
+
+  i2s_std_config_t i2s_config = I2S_STD_CHAN_CFG(rate, bits_cfg, ch);
+  if (slot_mask >= 0 && (i2s_std_slot_mask_t)slot_mask <= I2S_STD_SLOT_BOTH) {
+    i2s_config.slot_cfg.slot_mask = (i2s_std_slot_mask_t)slot_mask;
+  }
+  if (tx_chan != NULL) {
+    tx_sample_rate = rate;
+    tx_data_bit_width = bits_cfg;
+    tx_slot_mode = ch;
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_init_std_mode(tx_chan, &i2s_config));
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_enable(tx_chan));
+  }
+  if (rx_chan != NULL) {
+    rx_sample_rate = rate;
+    rx_data_bit_width = bits_cfg;
+    rx_slot_mode = ch;
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_init_std_mode(rx_chan, &i2s_config));
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_enable(rx_chan));
+  }
+
+  // Peripheral manager set bus type to I2S
+  if (_mclk >= 0) {
+    if (!perimanSetPinBus(_mclk, ESP32_BUS_TYPE_I2S_STD_MCLK, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_bclk >= 0) {
+    if (!perimanSetPinBus(_bclk, ESP32_BUS_TYPE_I2S_STD_BCLK, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_ws >= 0) {
+    if (!perimanSetPinBus(_ws, ESP32_BUS_TYPE_I2S_STD_WS, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_dout >= 0) {
+    if (!perimanSetPinBus(_dout, ESP32_BUS_TYPE_I2S_STD_DOUT, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_din >= 0) {
+    if (!perimanSetPinBus(_din, ESP32_BUS_TYPE_I2S_STD_DIN, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+
+  return true;
+err:
+  log_e("Failed to set all pins bus to I2S_STD");
+  I2SClass::i2sDetachBus((void *)(this));
+  return false;
+}
+
+#if SOC_I2S_SUPPORTS_TDM
+bool I2SClass::initTDM(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask) {
+  // Peripheral manager deinit previous peripheral if pin was used
+  if (_mclk >= 0) {
+    if (!perimanClearPinBus(_mclk)) {
+      return false;
+    }
+  }
+  if (_bclk >= 0) {
+    if (!perimanClearPinBus(_bclk)) {
+      return false;
+    }
+  }
+  if (_ws >= 0) {
+    if (!perimanClearPinBus(_ws)) {
+      return false;
+    }
+  }
+  if (_dout >= 0) {
+    if (!perimanClearPinBus(_dout)) {
+      return false;
+    }
+  }
+  if (_din >= 0) {
+    if (!perimanClearPinBus(_din)) {
+      return false;
+    }
+  }
+
+  // Set peripheral manager detach function for I2S
+  if (_mclk >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_TDM_MCLK, I2SClass::i2sDetachBus);
+  }
+  if (_bclk >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_TDM_BCLK, I2SClass::i2sDetachBus);
+  }
+  if (_ws >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_TDM_WS, I2SClass::i2sDetachBus);
+  }
+  if (_dout >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_TDM_DOUT, I2SClass::i2sDetachBus);
+  }
+  if (_din >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_TDM_DIN, I2SClass::i2sDetachBus);
+  }
+
+  // I2S configuration
+  i2s_chan_config_t chan_cfg = I2S_DEFAULT_CFG();
+  if (_dout >= 0 && _din >= 0) {
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_new_channel(&chan_cfg, &tx_chan, &rx_chan));
+  } else if (_dout >= 0) {
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_new_channel(&chan_cfg, &tx_chan, NULL));
+  } else if (_din >= 0) {
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_new_channel(&chan_cfg, NULL, &rx_chan));
+  }
+
+  i2s_tdm_config_t i2s_tdm_config = I2S_TDM_CHAN_CFG(rate, bits_cfg, ch, (i2s_tdm_slot_mask_t)slot_mask);
+  if (tx_chan != NULL) {
+    tx_sample_rate = rate;
+    tx_data_bit_width = bits_cfg;
+    tx_slot_mode = ch;
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_init_tdm_mode(tx_chan, &i2s_tdm_config));
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_enable(tx_chan));
+  }
+  if (rx_chan != NULL) {
+    rx_sample_rate = rate;
+    rx_data_bit_width = bits_cfg;
+    rx_slot_mode = ch;
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_init_tdm_mode(rx_chan, &i2s_tdm_config));
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_enable(rx_chan));
+  }
+
+  // Peripheral manager set bus type to I2S
+  if (_mclk >= 0) {
+    if (!perimanSetPinBus(_mclk, ESP32_BUS_TYPE_I2S_TDM_MCLK, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_bclk >= 0) {
+    if (!perimanSetPinBus(_bclk, ESP32_BUS_TYPE_I2S_TDM_BCLK, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_ws >= 0) {
+    if (!perimanSetPinBus(_ws, ESP32_BUS_TYPE_I2S_TDM_WS, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_dout >= 0) {
+    if (!perimanSetPinBus(_dout, ESP32_BUS_TYPE_I2S_TDM_DOUT, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_din >= 0) {
+    if (!perimanSetPinBus(_din, ESP32_BUS_TYPE_I2S_TDM_DIN, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+
+  return true;
+err:
+  log_e("Failed to set all pins bus to I2S_TDM");
+  I2SClass::i2sDetachBus((void *)(this));
+  return false;
+}
+#endif
+
+#if SOC_I2S_SUPPORTS_PDM_TX
+bool I2SClass::initPDMtx(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch) {
+  // Peripheral manager deinit previous peripheral if pin was used
+  if (_tx_clk >= 0) {
+    if (!perimanClearPinBus(_tx_clk)) {
+      return false;
+    }
+  }
+  if (_tx_dout0 >= 0) {
+    if (!perimanClearPinBus(_tx_dout0)) {
+      return false;
+    }
+  }
+  if (_tx_dout1 >= 0) {
+    if (!perimanClearPinBus(_tx_dout1)) {
+      return false;
+    }
+  }
+
+  // Set peripheral manager detach function for I2S
+  if (_tx_clk >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_PDM_TX_CLK, I2SClass::i2sDetachBus);
+  }
+  if (_tx_dout0 >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_PDM_TX_DOUT0, I2SClass::i2sDetachBus);
+  }
+  if (_tx_dout1 >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_PDM_TX_DOUT1, I2SClass::i2sDetachBus);
+  }
+
+  // I2S configuration
+  i2s_chan_config_t chan_cfg = I2S_DEFAULT_CFG();
+  I2S_ERROR_CHECK_RETURN_FALSE(i2s_new_channel(&chan_cfg, &tx_chan, NULL));
+
+  i2s_pdm_tx_config_t i2s_pdm_tx_config = I2S_PDM_TX_CHAN_CFG(rate, bits_cfg, ch);
+  if (tx_chan != NULL) {
+    tx_sample_rate = rate;
+    tx_data_bit_width = bits_cfg;
+    tx_slot_mode = ch;
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_init_pdm_tx_mode(tx_chan, &i2s_pdm_tx_config));
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_enable(tx_chan));
+  }
+
+  // Peripheral manager set bus type to I2S
+  if (_tx_clk >= 0) {
+    if (!perimanSetPinBus(_tx_clk, ESP32_BUS_TYPE_I2S_PDM_TX_CLK, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_tx_dout0 >= 0) {
+    if (!perimanSetPinBus(_tx_dout0, ESP32_BUS_TYPE_I2S_PDM_TX_DOUT0, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_tx_dout1 >= 0) {
+    if (!perimanSetPinBus(_tx_dout1, ESP32_BUS_TYPE_I2S_PDM_TX_DOUT1, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+
+  return true;
+err:
+  log_e("Failed to set all pins bus to I2S_TDM");
+  I2SClass::i2sDetachBus((void *)(this));
+  return false;
+}
+#endif
+
+#if SOC_I2S_SUPPORTS_PDM_RX
+bool I2SClass::initPDMrx(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch) {
+  // Peripheral manager deinit previous peripheral if pin was used
+  if (_rx_clk >= 0) {
+    if (!perimanClearPinBus(_rx_clk)) {
+      return false;
+    }
+  }
+  if (_rx_din0 >= 0) {
+    if (!perimanClearPinBus(_rx_din0)) {
+      return false;
+    }
+  }
+  if (_rx_din1 >= 0) {
+    if (!perimanClearPinBus(_rx_din1)) {
+      return false;
+    }
+  }
+  if (_rx_din2 >= 0) {
+    if (!perimanClearPinBus(_rx_din2)) {
+      return false;
+    }
+  }
+  if (_rx_din3 >= 0) {
+    if (!perimanClearPinBus(_rx_din3)) {
+      return false;
+    }
+  }
+
+  // Set peripheral manager detach function for I2S
+  if (_rx_clk >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_PDM_RX_CLK, I2SClass::i2sDetachBus);
+  }
+  if (_rx_din0 >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_PDM_RX_DIN0, I2SClass::i2sDetachBus);
+  }
+  if (_rx_din1 >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_PDM_RX_DIN1, I2SClass::i2sDetachBus);
+  }
+  if (_rx_din2 >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_PDM_RX_DIN2, I2SClass::i2sDetachBus);
+  }
+  if (_rx_din3 >= 0) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_I2S_PDM_RX_DIN3, I2SClass::i2sDetachBus);
+  }
+
+  // I2S configuration
+  i2s_chan_config_t chan_cfg = I2S_DEFAULT_CFG();
+  I2S_ERROR_CHECK_RETURN_FALSE(i2s_new_channel(&chan_cfg, NULL, &rx_chan));
+
+  i2s_pdm_rx_config_t i2s_pdf_rx_config = I2S_PDM_RX_CHAN_CFG(rate, bits_cfg, ch);
+  if (rx_chan != NULL) {
+    rx_sample_rate = rate;
+    rx_data_bit_width = bits_cfg;
+    rx_slot_mode = ch;
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_init_pdm_rx_mode(rx_chan, &i2s_pdf_rx_config));
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_enable(rx_chan));
+  }
+
+  // Peripheral manager set bus type to I2S
+  if (_rx_clk >= 0) {
+    if (!perimanSetPinBus(_rx_clk, ESP32_BUS_TYPE_I2S_PDM_RX_CLK, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_rx_din0 >= 0) {
+    if (!perimanSetPinBus(_rx_din0, ESP32_BUS_TYPE_I2S_PDM_RX_DIN0, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_rx_din1 >= 0) {
+    if (!perimanSetPinBus(_rx_din1, ESP32_BUS_TYPE_I2S_PDM_RX_DIN1, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_rx_din2 >= 0) {
+    if (!perimanSetPinBus(_rx_din2, ESP32_BUS_TYPE_I2S_PDM_RX_DIN2, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  if (_rx_din3 >= 0) {
+    if (!perimanSetPinBus(_rx_din3, ESP32_BUS_TYPE_I2S_PDM_RX_DIN3, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+
+  return true;
+err:
+  log_e("Failed to set all pins bus to I2S_TDM");
+  I2SClass::i2sDetachBus((void *)(this));
+  return false;
+}
+#endif
+
+bool I2SClass::begin(i2s_mode_t mode, uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask) {
+  /* Setup I2S peripheral */
+  if (mode >= I2S_MODE_MAX) {
+    log_e("Invalid I2S mode selected.");
+    return false;
+  }
+  _mode = mode;
+
+  bool init = false;
+  switch (_mode) {
+    case I2S_MODE_STD: init = initSTD(rate, bits_cfg, ch, slot_mask); break;
+#if SOC_I2S_SUPPORTS_TDM
+    case I2S_MODE_TDM: init = initTDM(rate, bits_cfg, ch, slot_mask); break;
+#endif
+#if SOC_I2S_SUPPORTS_PDM_TX
+    case I2S_MODE_PDM_TX: init = initPDMtx(rate, bits_cfg, ch); break;
+#endif
+#if SOC_I2S_SUPPORTS_PDM_RX
+    case I2S_MODE_PDM_RX: init = initPDMrx(rate, bits_cfg, ch); break;
+#endif
+    default: break;
+  }
+
+  if (init == false) {
+    log_e("I2S initialization failed.");
+    return false;
+  }
+  return true;
+}
+
+bool I2SClass::end() {
+  if (tx_chan != NULL) {
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_disable(tx_chan));
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_del_channel(tx_chan));
+    tx_chan = NULL;
+  }
+  if (rx_chan != NULL) {
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_disable(rx_chan));
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_del_channel(rx_chan));
+    rx_chan = NULL;
+  }
+  if (rx_transform_buf != NULL) {
+    free(rx_transform_buf);
+    rx_transform_buf = NULL;
+    rx_transform_buf_len = 0;
+  }
+
+  //Peripheral manager deinit used pins
+  switch (_mode) {
+    case I2S_MODE_STD:
+#if SOC_I2S_SUPPORTS_TDM
+    case I2S_MODE_TDM:
+#endif
+      if (_mclk >= 0) {
+        perimanClearPinBus(_mclk);
+      }
+      if (_bclk >= 0) {
+        perimanClearPinBus(_bclk);
+      }
+      if (_ws >= 0) {
+        perimanClearPinBus(_ws);
+      }
+      if (_dout >= 0) {
+        perimanClearPinBus(_dout);
+      }
+      if (_din >= 0) {
+        perimanClearPinBus(_din);
+      }
+      break;
+#if SOC_I2S_SUPPORTS_PDM_TX
+    case I2S_MODE_PDM_TX:
+      perimanClearPinBus(_tx_clk);
+      if (_tx_dout0 >= 0) {
+        perimanClearPinBus(_tx_dout0);
+      }
+      if (_tx_dout1 >= 0) {
+        perimanClearPinBus(_tx_dout1);
+      }
+      break;
+#endif
+#if SOC_I2S_SUPPORTS_PDM_RX
+    case I2S_MODE_PDM_RX:
+      perimanClearPinBus(_rx_clk);
+      if (_rx_din0 >= 0) {
+        perimanClearPinBus(_rx_din0);
+      }
+      if (_rx_din1 >= 0) {
+        perimanClearPinBus(_rx_din1);
+      }
+      if (_rx_din2 >= 0) {
+        perimanClearPinBus(_rx_din2);
+      }
+      if (_rx_din3 >= 0) {
+        perimanClearPinBus(_rx_din3);
+      }
+      break;
+#endif
+    default: break;
+  }
+  return true;
+}
+
+bool I2SClass::configureTX(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask) {
+  /* Setup I2S channels */
+  if (tx_chan != NULL) {
+    if (tx_sample_rate == rate && tx_data_bit_width == bits_cfg && tx_slot_mode == ch) {
+      return true;
+    }
+    i2s_std_config_t i2s_config = I2S_STD_CHAN_CFG(rate, bits_cfg, ch);
+    if (slot_mask >= 0 && (i2s_std_slot_mask_t)slot_mask <= I2S_STD_SLOT_BOTH) {
+      i2s_config.slot_cfg.slot_mask = (i2s_std_slot_mask_t)slot_mask;
+    }
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_disable(tx_chan));
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_reconfig_std_clock(tx_chan, &i2s_config.clk_cfg));
+    tx_sample_rate = rate;
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_reconfig_std_slot(tx_chan, &i2s_config.slot_cfg));
+    tx_data_bit_width = bits_cfg;
+    tx_slot_mode = ch;
+    I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_enable(tx_chan));
+    return true;
+  }
+  return false;
+}
+
+bool I2SClass::configureRX(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, i2s_rx_transform_t transform) {
+  /* Setup I2S channels */
+  if (rx_chan != NULL) {
+    if (rx_sample_rate != rate || rx_data_bit_width != bits_cfg || rx_slot_mode != ch) {
+      i2s_std_config_t i2s_config = I2S_STD_CHAN_CFG(rate, bits_cfg, ch);
+      I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_disable(rx_chan));
+      I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_reconfig_std_clock(rx_chan, &i2s_config.clk_cfg));
+      rx_sample_rate = rate;
+      I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_reconfig_std_slot(rx_chan, &i2s_config.slot_cfg));
+      rx_data_bit_width = bits_cfg;
+      rx_slot_mode = ch;
+      I2S_ERROR_CHECK_RETURN_FALSE(i2s_channel_enable(rx_chan));
+      return transformRX(transform);
+    }
+    if (rx_transform != transform) {
+      return transformRX(transform);
+    }
+    return true;
+  }
+  return false;
+}
+
+size_t I2SClass::readBytes(char *buffer, size_t size) {
+  size_t bytes_read = 0;
+  size_t bytes_to_read = 0;
+  size_t total_size = 0;
+  last_error = ESP_FAIL;
+  if (rx_chan == NULL) {
+    return total_size;
+  }
+  while (total_size < size) {
+    bytes_read = 0;
+    bytes_to_read = size - total_size;
+    if (rx_transform_buf != NULL && bytes_to_read > I2S_READ_CHUNK_SIZE) {
+      bytes_to_read = I2S_READ_CHUNK_SIZE;
+    }
+    I2S_ERROR_CHECK_RETURN(rx_fn(rx_chan, rx_transform_buf, (char *)(buffer + total_size), bytes_to_read, &bytes_read, _timeout), 0);
+    total_size += bytes_read;
+  }
+  return total_size;
+}
+
+size_t I2SClass::write(const uint8_t *buffer, size_t size) {
+  size_t written = 0;
+  size_t bytes_sent = 0;
+  size_t bytes_to_send = 0;
+  last_error = ESP_FAIL;
+  if (tx_chan == NULL) {
+    return written;
+  }
+  while (written < size) {
+    bytes_sent = 0;
+    bytes_to_send = size - written;
+    esp_err_t err = i2s_channel_write(tx_chan, (char *)(buffer + written), bytes_to_send, &bytes_sent, _timeout);
+    setWriteError(err);
+    I2S_ERROR_CHECK_RETURN(err, written);
+    written += bytes_sent;
+  }
+  return written;
+}
+
+i2s_chan_handle_t I2SClass::txChan() {
+  return tx_chan;
+}
+uint32_t I2SClass::txSampleRate() {
+  return tx_sample_rate;
+}
+i2s_data_bit_width_t I2SClass::txDataWidth() {
+  return tx_data_bit_width;
+}
+i2s_slot_mode_t I2SClass::txSlotMode() {
+  return tx_slot_mode;
+}
+
+i2s_chan_handle_t I2SClass::rxChan() {
+  return rx_chan;
+}
+uint32_t I2SClass::rxSampleRate() {
+  return rx_sample_rate;
+}
+i2s_data_bit_width_t I2SClass::rxDataWidth() {
+  return rx_data_bit_width;
+}
+i2s_slot_mode_t I2SClass::rxSlotMode() {
+  return rx_slot_mode;
+}
+
+int I2SClass::lastError() {
+  return (int)last_error;
+}
+
+int I2SClass::available() {
+  if (rx_chan == NULL) {
+    return -1;
+  }
+  return I2S_READ_CHUNK_SIZE;  // / (rx_data_bit_width/8);
+};
+
+int I2SClass::peek() {
+  return -1;
+};
+
+int I2SClass::read() {
+  int out = 0;
+  if (readBytes((char *)&out, rx_data_bit_width / 8) == (rx_data_bit_width / 8)) {
+    return out;
+  }
+  return -1;
+};
+
+size_t I2SClass::write(uint8_t d) {
+  return write(&d, 1);
+}
+
+bool I2SClass::transformRX(i2s_rx_transform_t transform) {
+  switch (transform) {
+    case I2S_RX_TRANSFORM_NONE:
+      allocTranformRX(0);
+      rx_fn = i2s_channel_read_default;
+      break;
+
+    case I2S_RX_TRANSFORM_32_TO_16:
+      if (rx_data_bit_width != I2S_DATA_BIT_WIDTH_32BIT) {
+        log_e("Wrong data width. Should be 32bit");
+        return false;
+      }
+      if (!allocTranformRX(I2S_READ_CHUNK_SIZE * 2)) {
+        return false;
+      }
+      rx_fn = i2s_channel_read_32_to_16;
+      rx_data_bit_width = I2S_DATA_BIT_WIDTH_16BIT;
+      break;
+
+    case I2S_RX_TRANSFORM_16_STEREO_TO_MONO:
+      if (rx_slot_mode != I2S_SLOT_MODE_STEREO) {
+        log_e("Wrong slot mode. Should be Stereo");
+        return false;
+      }
+      if (!allocTranformRX(I2S_READ_CHUNK_SIZE * 2)) {
+        return false;
+      }
+      rx_fn = i2s_channel_read_16_stereo_to_mono;
+      rx_slot_mode = I2S_SLOT_MODE_MONO;
+      break;
+
+    default: log_e("Unknown RX Transform %d", transform); return false;
+  }
+  rx_transform = transform;
+  return true;
+}
+
+bool I2SClass::allocTranformRX(size_t buf_len) {
+  char *buf = NULL;
+  if (buf_len == 0) {
+    if (rx_transform_buf != NULL) {
+      free(rx_transform_buf);
+      rx_transform_buf = NULL;
+      rx_transform_buf_len = 0;
+    }
+    return true;
+  }
+  if (rx_transform_buf == NULL || rx_transform_buf_len != buf_len) {
+    buf = (char *)malloc(buf_len);
+    if (buf == NULL) {
+      log_e("malloc %u failed!", buf_len);
+      return false;
+    }
+    if (rx_transform_buf != NULL) {
+      free(rx_transform_buf);
+    }
+    rx_transform_buf = buf;
+    rx_transform_buf_len = buf_len;
+  }
+  return true;
+}
+
+const int WAVE_HEADER_SIZE = PCM_WAV_HEADER_SIZE;
+
+//Record PCM WAV with current RX settings
+uint8_t *I2SClass::recordWAV(size_t rec_seconds, size_t *out_size) {
+  uint32_t sample_rate = rxSampleRate();
+  uint16_t sample_width = (uint16_t)rxDataWidth();
+  uint16_t num_channels = (uint16_t)rxSlotMode();
+  size_t rec_size = rec_seconds * ((sample_rate * (sample_width / 8)) * num_channels);
+  const pcm_wav_header_t wav_header = PCM_WAV_HEADER_DEFAULT(rec_size, sample_width, sample_rate, num_channels);
+  *out_size = 0;
+
+  log_d("Record WAV: rate:%lu, bits:%u, channels:%u, size:%lu", sample_rate, sample_width, num_channels, rec_size);
+
+  uint8_t *wav_buf = (uint8_t *)malloc(rec_size + WAVE_HEADER_SIZE);
+  if (wav_buf == NULL) {
+    log_e("Failed to allocate WAV buffer with size %u", rec_size + WAVE_HEADER_SIZE);
+    return NULL;
+  }
+  memcpy(wav_buf, &wav_header, WAVE_HEADER_SIZE);
+  size_t wav_size = readBytes((char *)(wav_buf + WAVE_HEADER_SIZE), rec_size);
+  if (wav_size < rec_size) {
+    log_e("Recorded %u bytes from %u", wav_size, rec_size);
+  } else if (lastError()) {
+    log_e("Read Failed! %d", lastError());
+  } else {
+    *out_size = rec_size + WAVE_HEADER_SIZE;
+    return wav_buf;
+  }
+  free(wav_buf);
+  return NULL;
+}
+
+void I2SClass::playWAV(uint8_t *data, size_t len) {
+  pcm_wav_header_t *header = (pcm_wav_header_t *)data;
+  if (header->fmt_chunk.audio_format != 1) {
+    log_e("Audio format is not PCM!");
+    return;
+  }
+  wav_data_chunk_t *data_chunk = &header->data_chunk;
+  size_t data_offset = 0;
+  while (memcmp(data_chunk->subchunk_id, "data", 4) != 0) {
+    log_d(
+      "Skip chunk: %c%c%c%c, len: %lu", data_chunk->subchunk_id[0], data_chunk->subchunk_id[1], data_chunk->subchunk_id[2], data_chunk->subchunk_id[3],
+      data_chunk->subchunk_size + 8
+    );
+    data_offset += data_chunk->subchunk_size + 8;
+    data_chunk = (wav_data_chunk_t *)(data + WAVE_HEADER_SIZE + data_offset - 8);
+  }
+  log_d(
+    "Play WAV: rate:%lu, bits:%d, channels:%d, size:%lu", header->fmt_chunk.sample_rate, header->fmt_chunk.bits_per_sample, header->fmt_chunk.num_of_channels,
+    data_chunk->subchunk_size
+  );
+  configureTX(header->fmt_chunk.sample_rate, (i2s_data_bit_width_t)header->fmt_chunk.bits_per_sample, (i2s_slot_mode_t)header->fmt_chunk.num_of_channels);
+  write(data + WAVE_HEADER_SIZE + data_offset, data_chunk->subchunk_size);
+}
+
+#if ARDUINO_HAS_MP3_DECODER
+bool I2SClass::playMP3(uint8_t *src, size_t src_len) {
+  int16_t outBuf[MAX_NCHAN * MAX_NGRAN * MAX_NSAMP];
+  uint8_t *readPtr = NULL;
+  int bytesAvailable = 0, err = 0, offset = 0;
+  MP3FrameInfo frameInfo;
+  HMP3Decoder decoder = NULL;
+
+  bytesAvailable = src_len;
+  readPtr = src;
+
+  decoder = MP3InitDecoder();
+  if (decoder == NULL) {
+    log_e("Could not allocate decoder");
+    return false;
+  }
+
+  do {
+    offset = MP3FindSyncWord(readPtr, bytesAvailable);
+    if (offset < 0) {
+      break;
+    }
+    readPtr += offset;
+    bytesAvailable -= offset;
+    err = MP3Decode(decoder, &readPtr, &bytesAvailable, outBuf, 0);
+    if (err) {
+      log_e("Decode ERROR: %d", err);
+      MP3FreeDecoder(decoder);
+      return false;
+    } else {
+      MP3GetLastFrameInfo(decoder, &frameInfo);
+      configureTX(frameInfo.samprate, (i2s_data_bit_width_t)frameInfo.bitsPerSample, (i2s_slot_mode_t)frameInfo.nChans);
+      write((uint8_t *)outBuf, (size_t)((frameInfo.bitsPerSample / 8) * frameInfo.outputSamps));
+    }
+  } while (true);
+  MP3FreeDecoder(decoder);
+  return true;
+}
+#endif
+
+#endif /* SOC_I2S_SUPPORTED */
diff --git a/libraries/ESP_I2S/src/ESP_I2S.h b/libraries/ESP_I2S/src/ESP_I2S.h
new file mode 100644
index 00000000000..b5c076bed04
--- /dev/null
+++ b/libraries/ESP_I2S/src/ESP_I2S.h
@@ -0,0 +1,146 @@
+#pragma once
+
+#if defined __has_include && __has_include("mp3dec.h")
+#define ARDUINO_HAS_MP3_DECODER 1
+#endif
+
+#include "soc/soc_caps.h"
+#if SOC_I2S_SUPPORTED
+
+#include "Arduino.h"
+#include "esp_err.h"
+#include "driver/i2s_std.h"
+#if SOC_I2S_SUPPORTS_TDM
+#include "driver/i2s_tdm.h"
+#endif
+#if SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX
+#include "driver/i2s_pdm.h"
+#endif
+
+typedef esp_err_t (*i2s_channel_read_fn)(i2s_chan_handle_t handle, char *tmp_buf, void *dest, size_t size, size_t *bytes_read, uint32_t timeout_ms);
+
+typedef enum {
+  I2S_MODE_STD,
+#if SOC_I2S_SUPPORTS_TDM
+  I2S_MODE_TDM,
+#endif
+#if SOC_I2S_SUPPORTS_PDM_TX
+  I2S_MODE_PDM_TX,
+#endif
+#if SOC_I2S_SUPPORTS_PDM_RX
+  I2S_MODE_PDM_RX,
+#endif
+  I2S_MODE_MAX
+} i2s_mode_t;
+
+typedef enum {
+  I2S_RX_TRANSFORM_NONE,
+  I2S_RX_TRANSFORM_32_TO_16,
+  I2S_RX_TRANSFORM_16_STEREO_TO_MONO,
+  I2S_RX_TRANSFORM_MAX
+} i2s_rx_transform_t;
+
+class I2SClass : public Stream {
+public:
+  I2SClass();
+  ~I2SClass();
+
+  //STD + TDM mode
+  void setPins(int8_t bclk, int8_t ws, int8_t dout, int8_t din = -1, int8_t mclk = -1);
+  void setInverted(bool bclk, bool ws, bool mclk = false);
+
+  //PDM TX + PDM RX mode
+#if SOC_I2S_SUPPORTS_PDM_TX
+  void setPinsPdmTx(int8_t clk, int8_t dout0, int8_t dout1 = -1);
+#endif
+#if SOC_I2S_SUPPORTS_PDM_RX
+  void setPinsPdmRx(int8_t clk, int8_t din0, int8_t din1 = -1, int8_t din2 = -1, int8_t din3 = -1);
+#endif
+#if SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX
+  void setInvertedPdm(bool clk);
+#endif
+
+  bool begin(i2s_mode_t mode, uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask = -1);
+  bool configureTX(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask = -1);
+  bool configureRX(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, i2s_rx_transform_t transform = I2S_RX_TRANSFORM_NONE);
+  bool end();
+
+  size_t readBytes(char *buffer, size_t size);
+  size_t write(const uint8_t *buffer, size_t size);
+
+  i2s_chan_handle_t txChan();
+  uint32_t txSampleRate();
+  i2s_data_bit_width_t txDataWidth();
+  i2s_slot_mode_t txSlotMode();
+
+  i2s_chan_handle_t rxChan();
+  uint32_t rxSampleRate();
+  i2s_data_bit_width_t rxDataWidth();
+  i2s_slot_mode_t rxSlotMode();
+
+  int lastError();
+
+  int available();
+  int peek();
+  int read();
+  size_t write(uint8_t d);
+
+  // Record short PCM WAV to memory with current RX settings. Returns buffer that must be freed by the user.
+  uint8_t *recordWAV(size_t rec_seconds, size_t *out_size);
+  // Play short PCM WAV from memory
+  void playWAV(uint8_t *data, size_t len);
+#if ARDUINO_HAS_MP3_DECODER
+  // Play short MP3 from memory
+  bool playMP3(uint8_t *src, size_t src_len);
+#endif
+
+private:
+  esp_err_t last_error;
+  i2s_mode_t _mode;
+
+  i2s_chan_handle_t tx_chan;
+  uint32_t tx_sample_rate;
+  i2s_data_bit_width_t tx_data_bit_width;
+  i2s_slot_mode_t tx_slot_mode;
+
+  i2s_channel_read_fn rx_fn;
+  i2s_rx_transform_t rx_transform;
+  char *rx_transform_buf;
+  size_t rx_transform_buf_len;
+
+  i2s_chan_handle_t rx_chan;
+  uint32_t rx_sample_rate;
+  i2s_data_bit_width_t rx_data_bit_width;
+  i2s_slot_mode_t rx_slot_mode;
+
+  //STD and TDM mode
+  int8_t _mclk, _bclk, _ws, _dout, _din;
+  bool _mclk_inv, _bclk_inv, _ws_inv;
+
+  //PDM mode
+#if SOC_I2S_SUPPORTS_PDM_RX
+  int8_t _rx_clk, _rx_din0, _rx_din1, _rx_din2, _rx_din3;  //TODO: soc_caps.h 1/4
+  bool _rx_clk_inv;
+#endif
+#if SOC_I2S_SUPPORTS_PDM_TX
+  int8_t _tx_clk, _tx_dout0, _tx_dout1;
+  bool _tx_clk_inv;
+#endif
+
+  bool allocTranformRX(size_t buf_len);
+  bool transformRX(i2s_rx_transform_t transform);
+
+  static bool i2sDetachBus(void *bus_pointer);
+  bool initSTD(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask);
+#if SOC_I2S_SUPPORTS_TDM
+  bool initTDM(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch, int8_t slot_mask);
+#endif
+#if SOC_I2S_SUPPORTS_PDM_TX
+  bool initPDMtx(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch);
+#endif
+#if SOC_I2S_SUPPORTS_PDM_RX
+  bool initPDMrx(uint32_t rate, i2s_data_bit_width_t bits_cfg, i2s_slot_mode_t ch);
+#endif
+};
+
+#endif /* SOC_I2S_SUPPORTED */
diff --git a/libraries/ESP_I2S/src/wav_header.h b/libraries/ESP_I2S/src/wav_header.h
new file mode 100644
index 00000000000..7b5164f9bfc
--- /dev/null
+++ b/libraries/ESP_I2S/src/wav_header.h
@@ -0,0 +1,88 @@
+#pragma once
+#include <stdint.h>
+
+/**
+ * @brief Header structure for WAV file with only one data chunk
+ *
+ * @note See this for reference: http://soundfile.sapp.org/doc/WaveFormat/
+ *
+ * @note Assignment to variables in this struct directly is only possible for little endian architectures
+ *       (including Xtensa & RISC-V)
+ */
+
+typedef struct {
+  char chunk_id[4];                               /*!< Contains the letters "RIFF" in ASCII form */
+  uint32_t chunk_size;                            /*!< This is the size of the rest of the chunk following this number */
+  char chunk_format[4];                           /*!< Contains the letters "WAVE" */
+} __attribute__((packed)) wav_descriptor_chunk_t; /*!< Canonical WAVE format starts with the RIFF header */
+
+typedef struct {
+  char subchunk_id[4];                         /*!< Contains the letters "fmt " */
+  uint32_t subchunk_size;                      /*!< PCM = 16, This is the size of the rest of the Subchunk which follows this number */
+  uint16_t audio_format;                       /*!< PCM = 1, values other than 1 indicate some form of compression */
+  uint16_t num_of_channels;                    /*!< Mono = 1, Stereo = 2, etc. */
+  uint32_t sample_rate;                        /*!< 8000, 44100, etc. */
+  uint32_t byte_rate;                          /*!< ==SampleRate * NumChannels * BitsPerSample s/ 8 */
+  uint16_t block_align;                        /*!< ==NumChannels * BitsPerSample / 8 */
+  uint16_t bits_per_sample;                    /*!< 8 bits = 8, 16 bits = 16, etc. */
+} __attribute__((packed)) pcm_wav_fmt_chunk_t; /*!< The "fmt " subchunk describes the sound data's format */
+
+typedef struct {
+  char subchunk_id[4];                             /*!< Contains the letters "fmt " */
+  uint32_t subchunk_size;                          /*!< ALAW/MULAW = 18, This is the size of the rest of the Subchunk which follows this number */
+  uint16_t audio_format;                           /*!< ALAW = 6, MULAW = 7, values other than 1 indicate some form of compression */
+  uint16_t num_of_channels;                        /*!< ALAW/MULAW = 1, Mono = 1, Stereo = 2, etc. */
+  uint32_t sample_rate;                            /*!< ALAW/MULAW = 8000, 8000, 44100, etc. */
+  uint32_t byte_rate;                              /*!< ALAW/MULAW = 8000, ==SampleRate * NumChannels * BitsPerSample s/ 8 */
+  uint16_t block_align;                            /*!< ALAW/MULAW = 1, ==NumChannels * BitsPerSample / 8 */
+  uint16_t bits_per_sample;                        /*!< ALAW/MULAW = 8, 8 bits = 8, 16 bits = 16, etc. */
+  uint16_t ext_size;                               /*!< ALAW/MULAW = 0, Size of the extension (0 or 22) */
+} __attribute__((packed)) non_pcm_wav_fmt_chunk_t; /*!< The "fmt " subchunk describes the sound data's format */
+
+typedef struct {
+  char subchunk_id[4];                      /*!< Contains the letters "data" */
+  uint32_t subchunk_size;                   /*!< ==NumSamples * NumChannels * BitsPerSample / 8 */
+} __attribute__((packed)) wav_data_chunk_t; /*!< The "data" subchunk contains the size of the data and the actual sound */
+
+typedef struct {
+  wav_descriptor_chunk_t descriptor_chunk; /*!< Canonical WAVE format starts with the RIFF header */
+  pcm_wav_fmt_chunk_t fmt_chunk;           /*!< The "fmt " subchunk describes the sound data's format */
+  wav_data_chunk_t data_chunk;             /*!< The "data" subchunk contains the size of the data and the actual sound */
+} __attribute__((packed)) pcm_wav_header_t;
+
+typedef struct {
+  wav_descriptor_chunk_t descriptor_chunk; /*!< Canonical WAVE format starts with the RIFF header */
+  non_pcm_wav_fmt_chunk_t fmt_chunk;       /*!< The "fmt " subchunk describes the sound data's format */
+  wav_data_chunk_t data_chunk;             /*!< The "data" subchunk contains the size of the data and the actual sound */
+} __attribute__((packed)) non_pcm_wav_header_t;
+
+#define WAVE_FORMAT_PCM        1  // PCM
+#define WAVE_FORMAT_IEEE_FLOAT 3  // IEEE float
+#define WAVE_FORMAT_ALAW       6  // 8-bit ITU-T G.711 A-law
+#define WAVE_FORMAT_MULAW      7  // 8-bit ITU-T G.711 µ-law
+
+#define PCM_WAV_HEADER_SIZE     44
+#define NON_PCM_WAV_HEADER_SIZE 46
+
+/**
+ * @brief Default header for PCM format WAV files
+ *
+ */
+#define PCM_WAV_HEADER_DEFAULT(wav_sample_size, wav_sample_bits, wav_sample_rate, wav_channel_num)                                              \
+  {                                                                                                                                             \
+    .descriptor_chunk =                                                                                                                         \
+      {.chunk_id = {'R', 'I', 'F', 'F'}, .chunk_size = (wav_sample_size) + sizeof(pcm_wav_header_t) - 8, .chunk_format = {'W', 'A', 'V', 'E'}}, \
+    .fmt_chunk =                                                                                                                                \
+      {.subchunk_id = {'f', 'm', 't', ' '},                                                                                                     \
+       .subchunk_size = 16,             /* 16 for PCM */                                                                                        \
+       .audio_format = WAVE_FORMAT_PCM, /* 1 for PCM */                                                                                         \
+       .num_of_channels = (uint16_t)(wav_channel_num),                                                                                          \
+       .sample_rate = (wav_sample_rate),                                                                                                        \
+       .byte_rate = (wav_sample_bits) * (wav_sample_rate) * (wav_channel_num) / 8,                                                              \
+       .block_align = (uint16_t)((wav_sample_bits) * (wav_channel_num) / 8),                                                                    \
+       .bits_per_sample = (uint16_t)(wav_sample_bits)},                                                                                         \
+    .data_chunk = {                                                                                                                             \
+      .subchunk_id = {'d', 'a', 't', 'a'},                                                                                                      \
+      .subchunk_size = (wav_sample_size)                                                                                                        \
+    }                                                                                                                                           \
+  }
diff --git a/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Master/ESP_NOW_Broadcast_Master.ino b/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Master/ESP_NOW_Broadcast_Master.ino
new file mode 100644
index 00000000000..6ee7dc6f846
--- /dev/null
+++ b/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Master/ESP_NOW_Broadcast_Master.ino
@@ -0,0 +1,104 @@
+/*
+    ESP-NOW Broadcast Master
+    Lucas Saavedra Vaz - 2024
+
+    This sketch demonstrates how to broadcast messages to all devices within the ESP-NOW network.
+    This example is intended to be used with the ESP-NOW Broadcast Slave example.
+
+    The master device will broadcast a message every 5 seconds to all devices within the network.
+    This will be done using by registering a peer object with the broadcast address.
+
+    The slave devices will receive the broadcasted messages and print them to the Serial Monitor.
+*/
+
+#include "ESP32_NOW.h"
+#include "WiFi.h"
+
+#include <esp_mac.h>  // For the MAC2STR and MACSTR macros
+
+/* Definitions */
+
+#define ESPNOW_WIFI_CHANNEL 6
+
+/* Classes */
+
+// Creating a new class that inherits from the ESP_NOW_Peer class is required.
+
+class ESP_NOW_Broadcast_Peer : public ESP_NOW_Peer {
+public:
+  // Constructor of the class using the broadcast address
+  ESP_NOW_Broadcast_Peer(uint8_t channel, wifi_interface_t iface, const uint8_t *lmk) : ESP_NOW_Peer(ESP_NOW.BROADCAST_ADDR, channel, iface, lmk) {}
+
+  // Destructor of the class
+  ~ESP_NOW_Broadcast_Peer() {
+    remove();
+  }
+
+  // Function to properly initialize the ESP-NOW and register the broadcast peer
+  bool begin() {
+    if (!ESP_NOW.begin() || !add()) {
+      log_e("Failed to initialize ESP-NOW or register the broadcast peer");
+      return false;
+    }
+    return true;
+  }
+
+  // Function to send a message to all devices within the network
+  bool send_message(const uint8_t *data, size_t len) {
+    if (!send(data, len)) {
+      log_e("Failed to broadcast message");
+      return false;
+    }
+    return true;
+  }
+};
+
+/* Global Variables */
+
+uint32_t msg_count = 0;
+
+// Create a broadcast peer object
+ESP_NOW_Broadcast_Peer broadcast_peer(ESPNOW_WIFI_CHANNEL, WIFI_IF_STA, NULL);
+
+/* Main */
+
+void setup() {
+  Serial.begin(115200);
+
+  // Initialize the Wi-Fi module
+  WiFi.mode(WIFI_STA);
+  WiFi.setChannel(ESPNOW_WIFI_CHANNEL);
+  while (!WiFi.STA.started()) {
+    delay(100);
+  }
+
+  Serial.println("ESP-NOW Example - Broadcast Master");
+  Serial.println("Wi-Fi parameters:");
+  Serial.println("  Mode: STA");
+  Serial.println("  MAC Address: " + WiFi.macAddress());
+  Serial.printf("  Channel: %d\n", ESPNOW_WIFI_CHANNEL);
+
+  // Register the broadcast peer
+  if (!broadcast_peer.begin()) {
+    Serial.println("Failed to initialize broadcast peer");
+    Serial.println("Reebooting in 5 seconds...");
+    delay(5000);
+    ESP.restart();
+  }
+
+  Serial.println("Setup complete. Broadcasting messages every 5 seconds.");
+}
+
+void loop() {
+  // Broadcast a message to all devices within the network
+  char data[32];
+  snprintf(data, sizeof(data), "Hello, World! #%lu", msg_count++);
+
+  Serial.printf("Broadcasting message: %s\n", data);
+
+  if (!broadcast_peer.send_message((uint8_t *)data, sizeof(data))) {
+    Serial.println("Failed to broadcast message");
+  }
+
+  delay(5000);
+}
diff --git a/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Master/ci.json b/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Master/ci.json
new file mode 100644
index 00000000000..36babb82730
--- /dev/null
+++ b/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Master/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Slave/ESP_NOW_Broadcast_Slave.ino b/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Slave/ESP_NOW_Broadcast_Slave.ino
new file mode 100644
index 00000000000..5f1a8bd8807
--- /dev/null
+++ b/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Slave/ESP_NOW_Broadcast_Slave.ino
@@ -0,0 +1,113 @@
+/*
+    ESP-NOW Broadcast Slave
+    Lucas Saavedra Vaz - 2024
+
+    This sketch demonstrates how to receive broadcast messages from a master device using the ESP-NOW protocol.
+
+    The master device will broadcast a message every 5 seconds to all devices within the network.
+
+    The slave devices will receive the broadcasted messages. If they are not from a known master, they will be registered as a new master
+    using a callback function.
+*/
+
+#include "ESP32_NOW.h"
+#include "WiFi.h"
+
+#include <esp_mac.h>  // For the MAC2STR and MACSTR macros
+
+#include <vector>
+
+/* Definitions */
+
+#define ESPNOW_WIFI_CHANNEL 6
+
+/* Classes */
+
+// Creating a new class that inherits from the ESP_NOW_Peer class is required.
+
+class ESP_NOW_Peer_Class : public ESP_NOW_Peer {
+public:
+  // Constructor of the class
+  ESP_NOW_Peer_Class(const uint8_t *mac_addr, uint8_t channel, wifi_interface_t iface, const uint8_t *lmk) : ESP_NOW_Peer(mac_addr, channel, iface, lmk) {}
+
+  // Destructor of the class
+  ~ESP_NOW_Peer_Class() {}
+
+  // Function to register the master peer
+  bool add_peer() {
+    if (!add()) {
+      log_e("Failed to register the broadcast peer");
+      return false;
+    }
+    return true;
+  }
+
+  // Function to print the received messages from the master
+  void onReceive(const uint8_t *data, size_t len, bool broadcast) {
+    Serial.printf("Received a message from master " MACSTR " (%s)\n", MAC2STR(addr()), broadcast ? "broadcast" : "unicast");
+    Serial.printf("  Message: %s\n", (char *)data);
+  }
+};
+
+/* Global Variables */
+
+// List of all the masters. It will be populated when a new master is registered
+std::vector<ESP_NOW_Peer_Class> masters;
+
+/* Callbacks */
+
+// Callback called when an unknown peer sends a message
+void register_new_master(const esp_now_recv_info_t *info, const uint8_t *data, int len, void *arg) {
+  if (memcmp(info->des_addr, ESP_NOW.BROADCAST_ADDR, 6) == 0) {
+    Serial.printf("Unknown peer " MACSTR " sent a broadcast message\n", MAC2STR(info->src_addr));
+    Serial.println("Registering the peer as a master");
+
+    ESP_NOW_Peer_Class new_master(info->src_addr, ESPNOW_WIFI_CHANNEL, WIFI_IF_STA, NULL);
+
+    masters.push_back(new_master);
+    if (!masters.back().add_peer()) {
+      Serial.println("Failed to register the new master");
+      return;
+    }
+  } else {
+    // The slave will only receive broadcast messages
+    log_v("Received a unicast message from " MACSTR, MAC2STR(info->src_addr));
+    log_v("Igorning the message");
+  }
+}
+
+/* Main */
+
+void setup() {
+  Serial.begin(115200);
+
+  // Initialize the Wi-Fi module
+  WiFi.mode(WIFI_STA);
+  WiFi.setChannel(ESPNOW_WIFI_CHANNEL);
+  while (!WiFi.STA.started()) {
+    delay(100);
+  }
+
+  Serial.println("ESP-NOW Example - Broadcast Slave");
+  Serial.println("Wi-Fi parameters:");
+  Serial.println("  Mode: STA");
+  Serial.println("  MAC Address: " + WiFi.macAddress());
+  Serial.printf("  Channel: %d\n", ESPNOW_WIFI_CHANNEL);
+
+  // Initialize the ESP-NOW protocol
+  if (!ESP_NOW.begin()) {
+    Serial.println("Failed to initialize ESP-NOW");
+    Serial.println("Reeboting in 5 seconds...");
+    delay(5000);
+    ESP.restart();
+  }
+
+  // Register the new peer callback
+  ESP_NOW.onNewPeer(register_new_master, NULL);
+
+  Serial.println("Setup complete. Waiting for a master to broadcast a message...");
+}
+
+void loop() {
+  delay(1000);
+}
diff --git a/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Slave/ci.json b/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Slave/ci.json
new file mode 100644
index 00000000000..36babb82730
--- /dev/null
+++ b/libraries/ESP_NOW/examples/ESP_NOW_Broadcast_Slave/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP_NOW/examples/ESP_NOW_Network/ESP_NOW_Network.ino b/libraries/ESP_NOW/examples/ESP_NOW_Network/ESP_NOW_Network.ino
new file mode 100644
index 00000000000..48ea6b731ce
--- /dev/null
+++ b/libraries/ESP_NOW/examples/ESP_NOW_Network/ESP_NOW_Network.ino
@@ -0,0 +1,370 @@
+/*
+    ESP-NOW Network Example
+    Lucas Saavedra Vaz - 2024
+
+    This example is based on the ESP-NOW example from the ESP-IDF framework.
+
+    The aim of this example is to demonstrate how to create a network of devices using the ESP-NOW protocol.
+    The slave devices will broadcast random data to the master device every 5 seconds and from time to time
+    they will ping the other slave devices with a "Hello!" message.
+
+    The master device will receive the data from the slave devices and print it to the Serial Monitor. From time
+    to time, the master device will calculate the average of the priorities of the slave devices and send it to
+    all the slave devices.
+
+    Each device will have a priority that will be used to decide which device will be the master.
+    The device with the highest priority will be the master.
+
+    Flow:
+    1. Each device will generate a priority based on its MAC address.
+    2. The devices will broadcast their priority on the network.
+    3. The devices will listen to the broadcast messages and register the priorities of the other devices.
+    4. After all devices have been registered, the device with the highest priority will be the master.
+    5. The slave devices will send random data to the master every 5 seconds.
+      - Every "REPORT_INTERVAL" messages, the slaves will send a message to the other slaves.
+    6. The master device will calculate the average of the data and send it to the slave devices every "REPORT_INTERVAL" messages.
+
+*/
+
+#include "ESP32_NOW.h"
+#include "WiFi.h"
+
+#include <esp_mac.h>  // For the MAC2STR and MACSTR macros
+
+#include <vector>
+
+/* Definitions */
+
+// Wi-Fi interface to be used by the ESP-NOW protocol
+#define ESPNOW_WIFI_IFACE WIFI_IF_STA
+
+// Channel to be used by the ESP-NOW protocol
+#define ESPNOW_WIFI_CHANNEL 4
+
+// Delay between sending messages
+#define ESPNOW_SEND_INTERVAL_MS 5000
+
+// Number of peers to wait for (excluding this device)
+#define ESPNOW_PEER_COUNT 2
+
+// Report to other devices every 5 messages
+#define REPORT_INTERVAL 5
+
+/*
+    ESP-NOW uses the CCMP method, which is described in IEEE Std. 802.11-2012, to protect the vendor-specific action frame.
+    The Wi-Fi device maintains a Primary Master Key (PMK) and several Local Master Keys (LMK).
+    The lengths of both PMK and LMK need to be 16 bytes.
+
+    PMK is used to encrypt LMK with the AES-128 algorithm. If PMK is not set, a default PMK will be used.
+
+    LMK of the paired device is used to encrypt the vendor-specific action frame with the CCMP method.
+    The maximum number of different LMKs is six. If the LMK of the paired device is not set, the vendor-specific
+    action frame will not be encrypted.
+
+    Encrypting multicast (broadcast address) vendor-specific action frame is not supported.
+
+    PMK needs to be the same for all devices in the network. LMK only needs to be the same between paired devices.
+*/
+
+// Primary Master Key (PMK) and Local Master Key (LMK)
+#define ESPNOW_EXAMPLE_PMK "pmk1234567890123"
+#define ESPNOW_EXAMPLE_LMK "lmk1234567890123"
+
+/* Structs */
+
+// The following struct is used to send data to the peer device.
+// We use the attribute "packed" to ensure that the struct is not padded (all data
+// is contiguous in the memory and without gaps).
+// The maximum size of the complete message is 250 bytes (ESP_NOW_MAX_DATA_LEN).
+
+typedef struct {
+  uint32_t count;
+  uint32_t priority;
+  uint32_t data;
+  bool ready;
+  char str[7];
+} __attribute__((packed)) esp_now_data_t;
+
+/* Global Variables */
+
+uint32_t self_priority = 0;          // Priority of this device
+uint8_t current_peer_count = 0;      // Number of peers that have been found
+bool device_is_master = false;       // Flag to indicate if this device is the master
+bool master_decided = false;         // Flag to indicate if the master has been decided
+uint32_t sent_msg_count = 0;         // Counter for the messages sent. Only starts counting after all peers have been found
+uint32_t recv_msg_count = 0;         // Counter for the messages received. Only starts counting after all peers have been found
+esp_now_data_t new_msg;              // Message that will be sent to the peers
+std::vector<uint32_t> last_data(5);  // Vector that will store the last 5 data received
+
+/* Classes */
+
+// We need to create a class that inherits from ESP_NOW_Peer and implement the _onReceive and _onSent methods.
+// This class will be used to store the priority of the device and to send messages to the peers.
+// For more information about the ESP_NOW_Peer class, see the ESP_NOW_Peer class in the ESP32_NOW.h file.
+
+class ESP_NOW_Network_Peer : public ESP_NOW_Peer {
+public:
+  uint32_t priority;
+  bool peer_is_master = false;
+  bool peer_ready = false;
+
+  ESP_NOW_Network_Peer(const uint8_t *mac_addr, uint32_t priority = 0, const uint8_t *lmk = (const uint8_t *)ESPNOW_EXAMPLE_LMK)
+    : ESP_NOW_Peer(mac_addr, ESPNOW_WIFI_CHANNEL, ESPNOW_WIFI_IFACE, lmk), priority(priority) {}
+
+  ~ESP_NOW_Network_Peer() {}
+
+  bool begin() {
+    // In this example the ESP-NOW protocol will already be initialized as we require it to receive broadcast messages.
+    if (!add()) {
+      log_e("Failed to initialize ESP-NOW or register the peer");
+      return false;
+    }
+    return true;
+  }
+
+  bool send_message(const uint8_t *data, size_t len) {
+    if (data == NULL || len == 0) {
+      log_e("Data to be sent is NULL or has a length of 0");
+      return false;
+    }
+
+    // Call the parent class method to send the data
+    return send(data, len);
+  }
+
+  void onReceive(const uint8_t *data, size_t len, bool broadcast) {
+    esp_now_data_t *msg = (esp_now_data_t *)data;
+
+    if (peer_ready == false && msg->ready == true) {
+      Serial.printf("Peer " MACSTR " reported ready\n", MAC2STR(addr()));
+      peer_ready = true;
+    }
+
+    if (!broadcast) {
+      recv_msg_count++;
+      if (device_is_master) {
+        Serial.printf("Received a message from peer " MACSTR "\n", MAC2STR(addr()));
+        Serial.printf("  Count: %lu\n", msg->count);
+        Serial.printf("  Random data: %lu\n", msg->data);
+        last_data.push_back(msg->data);
+        last_data.erase(last_data.begin());
+      } else if (peer_is_master) {
+        Serial.println("Received a message from the master");
+        Serial.printf("  Average data: %lu\n", msg->data);
+      } else {
+        Serial.printf("Peer " MACSTR " says: %s\n", MAC2STR(addr()), msg->str);
+      }
+    }
+  }
+
+  void onSent(bool success) {
+    bool broadcast = memcmp(addr(), ESP_NOW.BROADCAST_ADDR, ESP_NOW_ETH_ALEN) == 0;
+    if (broadcast) {
+      log_i("Broadcast message reported as sent %s", success ? "successfully" : "unsuccessfully");
+    } else {
+      log_i("Unicast message reported as sent %s to peer " MACSTR, success ? "successfully" : "unsuccessfully", MAC2STR(addr()));
+    }
+  }
+};
+
+/* Peers */
+
+std::vector<ESP_NOW_Network_Peer *> peers;                             // Create a vector to store the peer pointers
+ESP_NOW_Network_Peer broadcast_peer(ESP_NOW.BROADCAST_ADDR, 0, NULL);  // Register the broadcast peer (no encryption support for the broadcast address)
+ESP_NOW_Network_Peer *master_peer = nullptr;                           // Pointer to peer that is the master
+
+/* Helper functions */
+
+// Function to reboot the device
+void fail_reboot() {
+  Serial.println("Rebooting in 5 seconds...");
+  delay(5000);
+  ESP.restart();
+}
+
+// Function to check which device has the highest priority
+uint32_t check_highest_priority() {
+  uint32_t highest_priority = 0;
+  for (auto &peer : peers) {
+    if (peer->priority > highest_priority) {
+      highest_priority = peer->priority;
+    }
+  }
+  return std::max(highest_priority, self_priority);
+}
+
+// Function to calculate the average of the data received
+uint32_t calc_average() {
+  uint32_t avg = 0;
+  for (auto &d : last_data) {
+    avg += d;
+  }
+  avg /= last_data.size();
+  return avg;
+}
+
+// Function to check if all peers are ready
+bool check_all_peers_ready() {
+  for (auto &peer : peers) {
+    if (!peer->peer_ready) {
+      return false;
+    }
+  }
+  return true;
+}
+
+/* Callbacks */
+
+// Callback called when a new peer is found
+void register_new_peer(const esp_now_recv_info_t *info, const uint8_t *data, int len, void *arg) {
+  esp_now_data_t *msg = (esp_now_data_t *)data;
+  int priority = msg->priority;
+
+  if (priority == self_priority) {
+    Serial.println("ERROR! Device has the same priority as this device. Unsupported behavior.");
+    fail_reboot();
+  }
+
+  if (current_peer_count < ESPNOW_PEER_COUNT) {
+    Serial.printf("New peer found: " MACSTR " with priority %d\n", MAC2STR(info->src_addr), priority);
+    ESP_NOW_Network_Peer *new_peer = new ESP_NOW_Network_Peer(info->src_addr, priority);
+    if (new_peer == nullptr || !new_peer->begin()) {
+      Serial.println("Failed to create or register the new peer");
+      delete new_peer;
+      return;
+    }
+    peers.push_back(new_peer);
+    current_peer_count++;
+    if (current_peer_count == ESPNOW_PEER_COUNT) {
+      Serial.println("All peers have been found");
+      new_msg.ready = true;
+    }
+  }
+}
+
+/* Main */
+
+void setup() {
+  uint8_t self_mac[6];
+
+  Serial.begin(115200);
+
+  // Initialize the Wi-Fi module
+  WiFi.mode(WIFI_STA);
+  WiFi.setChannel(ESPNOW_WIFI_CHANNEL);
+  while (!WiFi.STA.started()) {
+    delay(100);
+  }
+
+  Serial.println("ESP-NOW Network Example");
+  Serial.println("Wi-Fi parameters:");
+  Serial.println("  Mode: STA");
+  Serial.println("  MAC Address: " + WiFi.macAddress());
+  Serial.printf("  Channel: %d\n", ESPNOW_WIFI_CHANNEL);
+
+  // Generate yhis device's priority based on the 3 last bytes of the MAC address
+  WiFi.macAddress(self_mac);
+  self_priority = self_mac[3] << 16 | self_mac[4] << 8 | self_mac[5];
+  Serial.printf("This device's priority: %lu\n", self_priority);
+
+  // Initialize the ESP-NOW protocol
+  if (!ESP_NOW.begin((const uint8_t *)ESPNOW_EXAMPLE_PMK)) {
+    Serial.println("Failed to initialize ESP-NOW");
+    fail_reboot();
+  }
+
+  if (!broadcast_peer.begin()) {
+    Serial.println("Failed to initialize broadcast peer");
+    fail_reboot();
+  }
+
+  // Register the callback to be called when a new peer is found
+  ESP_NOW.onNewPeer(register_new_peer, NULL);
+
+  Serial.println("Setup complete. Broadcasting own priority to find the master...");
+  memset(&new_msg, 0, sizeof(new_msg));
+  strncpy(new_msg.str, "Hello!", sizeof(new_msg.str));
+  new_msg.priority = self_priority;
+}
+
+void loop() {
+  if (!master_decided) {
+    // Broadcast the priority to find the master
+    if (!broadcast_peer.send_message((const uint8_t *)&new_msg, sizeof(new_msg))) {
+      Serial.println("Failed to broadcast message");
+    }
+
+    // Check if all peers have been found
+    if (current_peer_count == ESPNOW_PEER_COUNT) {
+      // Wait until all peers are ready
+      if (check_all_peers_ready()) {
+        Serial.println("All peers are ready");
+        // Check which device has the highest priority
+        master_decided = true;
+        uint32_t highest_priority = check_highest_priority();
+        if (highest_priority == self_priority) {
+          device_is_master = true;
+          Serial.println("This device is the master");
+        } else {
+          for (int i = 0; i < ESPNOW_PEER_COUNT; i++) {
+            if (peers[i]->priority == highest_priority) {
+              peers[i]->peer_is_master = true;
+              master_peer = peers[i];
+              Serial.printf("Peer " MACSTR " is the master with priority %lu\n", MAC2STR(peers[i]->addr()), highest_priority);
+              break;
+            }
+          }
+        }
+        Serial.println("The master has been decided");
+      } else {
+        Serial.println("Waiting for all peers to be ready...");
+      }
+    }
+  } else {
+    if (!device_is_master) {
+      // Send a message to the master
+      new_msg.count = sent_msg_count + 1;
+      new_msg.data = random(10000);
+      if (!master_peer->send_message((const uint8_t *)&new_msg, sizeof(new_msg))) {
+        Serial.println("Failed to send message to the master");
+      } else {
+        Serial.printf("Sent message to the master. Count: %lu, Data: %lu\n", new_msg.count, new_msg.data);
+        sent_msg_count++;
+      }
+
+      // Check if it is time to report to peers
+      if (sent_msg_count % REPORT_INTERVAL == 0) {
+        // Send a message to the peers
+        for (auto &peer : peers) {
+          if (!peer->peer_is_master) {
+            if (!peer->send_message((const uint8_t *)&new_msg, sizeof(new_msg))) {
+              Serial.printf("Failed to send message to peer " MACSTR "\n", MAC2STR(peer->addr()));
+            } else {
+              Serial.printf("Sent message \"%s\" to peer " MACSTR "\n", new_msg.str, MAC2STR(peer->addr()));
+            }
+          }
+        }
+      }
+    } else {
+      // Check if it is time to report to peers
+      if (recv_msg_count % REPORT_INTERVAL == 0) {
+        // Report average data to the peers
+        uint32_t avg = calc_average();
+        new_msg.data = avg;
+        for (auto &peer : peers) {
+          new_msg.count = sent_msg_count + 1;
+          if (!peer->send_message((const uint8_t *)&new_msg, sizeof(new_msg))) {
+            Serial.printf("Failed to send message to peer " MACSTR "\n", MAC2STR(peer->addr()));
+          } else {
+            Serial.printf(
+              "Sent message to peer " MACSTR ". Recv: %lu, Sent: %lu, Avg: %lu\n", MAC2STR(peer->addr()), recv_msg_count, new_msg.count, new_msg.data
+            );
+            sent_msg_count++;
+          }
+        }
+      }
+    }
+  }
+
+  delay(ESPNOW_SEND_INTERVAL_MS);
+}
diff --git a/libraries/ESP_NOW/examples/ESP_NOW_Network/ci.json b/libraries/ESP_NOW/examples/ESP_NOW_Network/ci.json
new file mode 100644
index 00000000000..36babb82730
--- /dev/null
+++ b/libraries/ESP_NOW/examples/ESP_NOW_Network/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP_NOW/examples/ESP_NOW_Serial/ESP_NOW_Serial.ino b/libraries/ESP_NOW/examples/ESP_NOW_Serial/ESP_NOW_Serial.ino
new file mode 100644
index 00000000000..e1f28382fe2
--- /dev/null
+++ b/libraries/ESP_NOW/examples/ESP_NOW_Serial/ESP_NOW_Serial.ino
@@ -0,0 +1,83 @@
+/*
+    ESP-NOW Serial Example - Unicast transmission
+    Lucas Saavedra Vaz - 2024
+    Send data between two ESP32s using the ESP-NOW protocol in one-to-one (unicast) configuration.
+    Note that different MAC addresses are used for different interfaces.
+    The devices can be in different modes (AP or Station) and still communicate using ESP-NOW.
+    The only requirement is that the devices are on the same Wi-Fi channel.
+    Set the peer MAC address according to the device that will receive the data.
+
+    Example setup:
+    - Device 1: AP mode with MAC address F6:12:FA:42:B6:E8
+                Peer MAC address set to the Station MAC address of Device 2 (F4:12:FA:40:64:4C)
+    - Device 2: Station mode with MAC address F4:12:FA:40:64:4C
+                Peer MAC address set to the AP MAC address of Device 1 (F6:12:FA:42:B6:E8)
+
+    The device running this sketch will also receive and print data from any device that has its MAC address set as the peer MAC address.
+    To properly visualize the data being sent, set the line ending in the Serial Monitor to "Both NL & CR".
+*/
+
+#include "ESP32_NOW_Serial.h"
+#include "MacAddress.h"
+#include "WiFi.h"
+
+#include "esp_wifi.h"
+
+// 0: AP mode, 1: Station mode
+#define ESPNOW_WIFI_MODE_STATION 1
+
+// Channel to be used by the ESP-NOW protocol
+#define ESPNOW_WIFI_CHANNEL 1
+
+#if ESPNOW_WIFI_MODE_STATION          // ESP-NOW using WiFi Station mode
+#define ESPNOW_WIFI_MODE WIFI_STA     // WiFi Mode
+#define ESPNOW_WIFI_IF   WIFI_IF_STA  // WiFi Interface
+#else                                 // ESP-NOW using WiFi AP mode
+#define ESPNOW_WIFI_MODE WIFI_AP      // WiFi Mode
+#define ESPNOW_WIFI_IF   WIFI_IF_AP   // WiFi Interface
+#endif
+
+// Set the MAC address of the device that will receive the data
+// For example: F4:12:FA:40:64:4C
+const MacAddress peer_mac({0xF4, 0x12, 0xFA, 0x40, 0x64, 0x4C});
+
+ESP_NOW_Serial_Class NowSerial(peer_mac, ESPNOW_WIFI_CHANNEL, ESPNOW_WIFI_IF);
+
+void setup() {
+  Serial.begin(115200);
+
+  Serial.print("WiFi Mode: ");
+  Serial.println(ESPNOW_WIFI_MODE == WIFI_AP ? "AP" : "Station");
+  WiFi.mode(ESPNOW_WIFI_MODE);
+
+  Serial.print("Channel: ");
+  Serial.println(ESPNOW_WIFI_CHANNEL);
+  WiFi.setChannel(ESPNOW_WIFI_CHANNEL, WIFI_SECOND_CHAN_NONE);
+
+  while (!(WiFi.STA.started() || WiFi.AP.started())) {
+    delay(100);
+  }
+
+  Serial.print("MAC Address: ");
+  Serial.println(ESPNOW_WIFI_MODE == WIFI_AP ? WiFi.softAPmacAddress() : WiFi.macAddress());
+
+  // Start the ESP-NOW communication
+  Serial.println("ESP-NOW communication starting...");
+  NowSerial.begin(115200);
+  Serial.println("You can now send data to the peer device using the Serial Monitor.\n");
+}
+
+void loop() {
+  while (NowSerial.available()) {
+    Serial.write(NowSerial.read());
+  }
+
+  while (Serial.available() && NowSerial.availableForWrite()) {
+    if (NowSerial.write(Serial.read()) <= 0) {
+      Serial.println("Failed to send data");
+      break;
+    }
+  }
+
+  delay(1);
+}
diff --git a/libraries/ESP_NOW/examples/ESP_NOW_Serial/ci.json b/libraries/ESP_NOW/examples/ESP_NOW_Serial/ci.json
new file mode 100644
index 00000000000..36babb82730
--- /dev/null
+++ b/libraries/ESP_NOW/examples/ESP_NOW_Serial/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/ESP_NOW/library.properties b/libraries/ESP_NOW/library.properties
new file mode 100644
index 00000000000..f3e5c109a9b
--- /dev/null
+++ b/libraries/ESP_NOW/library.properties
@@ -0,0 +1,9 @@
+name=ESP_NOW
+version=3.2.0
+author=me-no-dev
+maintainer=P-R-O-C-H-Y
+sentence=Library for ESP_NOW
+paragraph=Supports ESP32 Arduino platforms.
+category=Sensor
+url=https://github.com/espressif/arduino-esp32/
+architectures=esp32
diff --git a/libraries/ESP_NOW/src/ESP32_NOW.cpp b/libraries/ESP_NOW/src/ESP32_NOW.cpp
new file mode 100644
index 00000000000..6fd3ff0a0b1
--- /dev/null
+++ b/libraries/ESP_NOW/src/ESP32_NOW.cpp
@@ -0,0 +1,415 @@
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#warning "ESP-NOW is only supported in SoCs with native Wi-Fi support"
+#else
+
+#include "ESP32_NOW.h"
+#include <string.h>
+#include "esp_system.h"
+#include "esp32-hal.h"
+#include "esp_wifi.h"
+
+static void (*new_cb)(const esp_now_recv_info_t *info, const uint8_t *data, int len, void *arg) = NULL;
+static void *new_arg = NULL;  // * tx_arg = NULL, * rx_arg = NULL,
+static bool _esp_now_has_begun = false;
+static ESP_NOW_Peer *_esp_now_peers[ESP_NOW_MAX_TOTAL_PEER_NUM];
+
+static esp_err_t _esp_now_add_peer(const uint8_t *mac_addr, uint8_t channel, wifi_interface_t iface, const uint8_t *lmk, ESP_NOW_Peer *_peer = NULL) {
+  log_v(MACSTR, MAC2STR(mac_addr));
+  if (esp_now_is_peer_exist(mac_addr)) {
+    log_e("Peer Already Exists");
+    return ESP_ERR_ESPNOW_EXIST;
+  }
+
+  esp_now_peer_info_t peer;
+  memset(&peer, 0, sizeof(esp_now_peer_info_t));
+  memcpy(peer.peer_addr, mac_addr, ESP_NOW_ETH_ALEN);
+  peer.channel = channel;
+  peer.ifidx = iface;
+  peer.encrypt = lmk != NULL;
+  if (lmk) {
+    memcpy(peer.lmk, lmk, ESP_NOW_KEY_LEN);
+  }
+
+  esp_err_t result = esp_now_add_peer(&peer);
+  if (result == ESP_OK) {
+    if (_peer != NULL) {
+      for (uint8_t i = 0; i < ESP_NOW_MAX_TOTAL_PEER_NUM; i++) {
+        if (_esp_now_peers[i] == NULL) {
+          _esp_now_peers[i] = _peer;
+          return ESP_OK;
+        }
+      }
+      return ESP_FAIL;
+    }
+  } else if (result == ESP_ERR_ESPNOW_NOT_INIT) {
+    log_e("ESPNOW Not Init");
+  } else if (result == ESP_ERR_ESPNOW_ARG) {
+    log_e("Invalid Argument");
+  } else if (result == ESP_ERR_ESPNOW_FULL) {
+    log_e("Peer list full");
+  } else if (result == ESP_ERR_ESPNOW_NO_MEM) {
+    log_e("Out of memory");
+  } else if (result == ESP_ERR_ESPNOW_EXIST) {
+    log_e("Peer already exists");
+  }
+  return result;
+}
+
+static esp_err_t _esp_now_del_peer(const uint8_t *mac_addr) {
+  esp_err_t result = esp_now_del_peer(mac_addr);
+  if (result == ESP_ERR_ESPNOW_NOT_INIT) {
+    log_e("ESPNOW Not Init");
+  } else if (result == ESP_ERR_ESPNOW_ARG) {
+    log_e("Invalid Argument");
+  } else if (result == ESP_ERR_ESPNOW_NOT_FOUND) {
+    log_e("Peer Not Found");
+  }
+
+  for (uint8_t i = 0; i < ESP_NOW_MAX_TOTAL_PEER_NUM; i++) {
+    if (_esp_now_peers[i] != NULL && memcmp(mac_addr, _esp_now_peers[i]->addr(), ESP_NOW_ETH_ALEN) == 0) {
+      _esp_now_peers[i] = NULL;
+      break;
+    }
+  }
+  return result;
+}
+
+static esp_err_t _esp_now_modify_peer(const uint8_t *mac_addr, uint8_t channel, wifi_interface_t iface, const uint8_t *lmk) {
+  log_v(MACSTR, MAC2STR(mac_addr));
+  if (!esp_now_is_peer_exist(mac_addr)) {
+    log_e("Peer not found");
+    return ESP_ERR_ESPNOW_NOT_FOUND;
+  }
+
+  esp_now_peer_info_t peer;
+  memset(&peer, 0, sizeof(esp_now_peer_info_t));
+  memcpy(peer.peer_addr, mac_addr, ESP_NOW_ETH_ALEN);
+  peer.channel = channel;
+  peer.ifidx = iface;
+  peer.encrypt = lmk != NULL;
+  if (lmk) {
+    memcpy(peer.lmk, lmk, ESP_NOW_KEY_LEN);
+  }
+
+  esp_err_t result = esp_now_mod_peer(&peer);
+  if (result == ESP_OK) {
+    return result;
+  } else if (result == ESP_ERR_ESPNOW_NOT_INIT) {
+    log_e("ESPNOW Not Init");
+  } else if (result == ESP_ERR_ESPNOW_ARG) {
+    log_e("Invalid Argument");
+  } else if (result == ESP_ERR_ESPNOW_FULL) {
+    log_e("Peer list full");
+  } else if (result == ESP_ERR_ESPNOW_NO_MEM) {
+    log_e("Out of memory");
+  }
+  return result;
+}
+
+static void _esp_now_rx_cb(const esp_now_recv_info_t *info, const uint8_t *data, int len) {
+  bool broadcast = memcmp(info->des_addr, ESP_NOW.BROADCAST_ADDR, ESP_NOW_ETH_ALEN) == 0;
+  log_v("%s from " MACSTR ", data length : %u", broadcast ? "Broadcast" : "Unicast", MAC2STR(info->src_addr), len);
+  log_buf_v(data, len);
+  if (!esp_now_is_peer_exist(info->src_addr) && new_cb != NULL) {
+    log_v("Calling new_cb, peer not found.");
+    new_cb(info, data, len, new_arg);
+    return;
+  }
+  //find the peer and call it's callback
+  for (uint8_t i = 0; i < ESP_NOW_MAX_TOTAL_PEER_NUM; i++) {
+    if (_esp_now_peers[i] != NULL) {
+      log_v("Checking peer " MACSTR, MAC2STR(_esp_now_peers[i]->addr()));
+    }
+    if (_esp_now_peers[i] != NULL && memcmp(info->src_addr, _esp_now_peers[i]->addr(), ESP_NOW_ETH_ALEN) == 0) {
+      log_v("Calling onReceive");
+      _esp_now_peers[i]->onReceive(data, len, broadcast);
+      return;
+    }
+  }
+}
+
+static void _esp_now_tx_cb(const uint8_t *mac_addr, esp_now_send_status_t status) {
+  log_v(MACSTR " : %s", MAC2STR(mac_addr), (status == ESP_NOW_SEND_SUCCESS) ? "SUCCESS" : "FAILED");
+  //find the peer and call it's callback
+  for (uint8_t i = 0; i < ESP_NOW_MAX_TOTAL_PEER_NUM; i++) {
+    if (_esp_now_peers[i] != NULL && memcmp(mac_addr, _esp_now_peers[i]->addr(), ESP_NOW_ETH_ALEN) == 0) {
+      _esp_now_peers[i]->onSent(status == ESP_NOW_SEND_SUCCESS);
+      return;
+    }
+  }
+}
+
+ESP_NOW_Class::ESP_NOW_Class() {}
+
+ESP_NOW_Class::~ESP_NOW_Class() {}
+
+bool ESP_NOW_Class::begin(const uint8_t *pmk) {
+  if (_esp_now_has_begun) {
+    return true;
+  }
+
+  esp_err_t err = esp_wifi_start();
+  if (err != ESP_OK) {
+    log_e("WiFi not started! 0x%x)", err);
+    return false;
+  }
+
+  _esp_now_has_begun = true;
+
+  memset(_esp_now_peers, 0, sizeof(ESP_NOW_Peer *) * ESP_NOW_MAX_TOTAL_PEER_NUM);
+
+  err = esp_now_init();
+  if (err != ESP_OK) {
+    log_e("esp_now_init failed! 0x%x", err);
+    _esp_now_has_begun = false;
+    return false;
+  }
+
+  if (pmk) {
+    err = esp_now_set_pmk(pmk);
+    if (err != ESP_OK) {
+      log_e("esp_now_set_pmk failed! 0x%x", err);
+      _esp_now_has_begun = false;
+      return false;
+    }
+  }
+
+  err = esp_now_register_recv_cb(_esp_now_rx_cb);
+  if (err != ESP_OK) {
+    log_e("esp_now_register_recv_cb failed! 0x%x", err);
+    _esp_now_has_begun = false;
+    return false;
+  }
+
+  err = esp_now_register_send_cb(_esp_now_tx_cb);
+  if (err != ESP_OK) {
+    log_e("esp_now_register_send_cb failed! 0x%x", err);
+    _esp_now_has_begun = false;
+    return false;
+  }
+  return true;
+}
+
+bool ESP_NOW_Class::end() {
+  if (!_esp_now_has_begun) {
+    return true;
+  }
+  //remove all peers
+  for (uint8_t i = 0; i < ESP_NOW_MAX_TOTAL_PEER_NUM; i++) {
+    if (_esp_now_peers[i] != NULL) {
+      removePeer(*_esp_now_peers[i]);
+    }
+  }
+  esp_err_t err = esp_now_deinit();
+  if (err != ESP_OK) {
+    log_e("esp_now_deinit failed! 0x%x", err);
+    return false;
+  }
+  _esp_now_has_begun = false;
+  //clear the peer list
+  memset(_esp_now_peers, 0, sizeof(ESP_NOW_Peer *) * ESP_NOW_MAX_TOTAL_PEER_NUM);
+  return true;
+}
+
+int ESP_NOW_Class::getTotalPeerCount() {
+  if (!_esp_now_has_begun) {
+    return -1;
+  }
+  esp_now_peer_num_t num;
+  esp_err_t err = esp_now_get_peer_num(&num);
+  if (err != ESP_OK) {
+    log_e("esp_now_get_peer_num failed! 0x%x", err);
+    return -1;
+  }
+  return num.total_num;
+}
+
+int ESP_NOW_Class::getEncryptedPeerCount() {
+  if (!_esp_now_has_begun) {
+    return -1;
+  }
+  esp_now_peer_num_t num;
+  esp_err_t err = esp_now_get_peer_num(&num);
+  if (err != ESP_OK) {
+    log_e("esp_now_get_peer_num failed! 0x%x", err);
+    return -1;
+  }
+  return num.encrypt_num;
+}
+
+int ESP_NOW_Class::availableForWrite() {
+  return ESP_NOW_MAX_DATA_LEN;
+}
+
+size_t ESP_NOW_Class::write(const uint8_t *data, size_t len) {
+  if (!_esp_now_has_begun) {
+    return 0;
+  }
+  if (len > ESP_NOW_MAX_DATA_LEN) {
+    len = ESP_NOW_MAX_DATA_LEN;
+  }
+  esp_err_t result = esp_now_send(NULL, data, len);
+  if (result == ESP_OK) {
+    return len;
+  } else if (result == ESP_ERR_ESPNOW_NOT_INIT) {
+    log_e("ESPNOW not init.");
+  } else if (result == ESP_ERR_ESPNOW_ARG) {
+    log_e("Invalid argument");
+  } else if (result == ESP_ERR_ESPNOW_INTERNAL) {
+    log_e("Internal Error");
+  } else if (result == ESP_ERR_ESPNOW_NO_MEM) {
+    log_e("Our of memory");
+  } else if (result == ESP_ERR_ESPNOW_NOT_FOUND) {
+    log_e("Peer not found.");
+  } else if (result == ESP_ERR_ESPNOW_IF) {
+    log_e("Interface does not match.");
+  }
+  return 0;
+}
+
+void ESP_NOW_Class::onNewPeer(void (*cb)(const esp_now_recv_info_t *info, const uint8_t *data, int len, void *arg), void *arg) {
+  new_cb = cb;
+  new_arg = arg;
+}
+
+bool ESP_NOW_Class::removePeer(ESP_NOW_Peer &peer) {
+  return peer.remove();
+}
+
+ESP_NOW_Class ESP_NOW;
+
+/*
+ *
+ *    Inheritable Peer Class
+ *
+*/
+
+ESP_NOW_Peer::ESP_NOW_Peer(const uint8_t *mac_addr, uint8_t channel, wifi_interface_t iface, const uint8_t *lmk) {
+  added = false;
+  if (mac_addr) {
+    memcpy(mac, mac_addr, 6);
+  }
+  chan = channel;
+  ifc = iface;
+  encrypt = lmk != NULL;
+  if (encrypt) {
+    memcpy(key, lmk, 16);
+  }
+}
+
+bool ESP_NOW_Peer::add() {
+  if (!_esp_now_has_begun) {
+    return false;
+  }
+  if (added) {
+    return true;
+  }
+  if (_esp_now_add_peer(mac, chan, ifc, encrypt ? key : NULL, this) != ESP_OK) {
+    return false;
+  }
+  log_v("Peer added - " MACSTR, MAC2STR(mac));
+  added = true;
+  return true;
+}
+
+bool ESP_NOW_Peer::remove() {
+  if (!_esp_now_has_begun) {
+    return false;
+  }
+  if (!added) {
+    return true;
+  }
+  log_v("Peer removed - " MACSTR, MAC2STR(mac));
+  esp_err_t err = _esp_now_del_peer(mac);
+  if (err == ESP_OK) {
+    added = false;
+    return true;
+  }
+  return false;
+}
+
+const uint8_t *ESP_NOW_Peer::addr() const {
+  return mac;
+}
+
+bool ESP_NOW_Peer::addr(const uint8_t *mac_addr) {
+  if (!_esp_now_has_begun || !added) {
+    memcpy(mac, mac_addr, 6);
+    return true;
+  }
+  return false;
+}
+
+uint8_t ESP_NOW_Peer::getChannel() const {
+  return chan;
+}
+
+bool ESP_NOW_Peer::setChannel(uint8_t channel) {
+  chan = channel;
+  if (!_esp_now_has_begun || !added) {
+    return true;
+  }
+  return _esp_now_modify_peer(mac, chan, ifc, encrypt ? key : NULL) == ESP_OK;
+}
+
+wifi_interface_t ESP_NOW_Peer::getInterface() const {
+  return ifc;
+}
+
+bool ESP_NOW_Peer::setInterface(wifi_interface_t iface) {
+  ifc = iface;
+  if (!_esp_now_has_begun || !added) {
+    return true;
+  }
+  return _esp_now_modify_peer(mac, chan, ifc, encrypt ? key : NULL) == ESP_OK;
+}
+
+bool ESP_NOW_Peer::isEncrypted() const {
+  return encrypt;
+}
+
+bool ESP_NOW_Peer::setKey(const uint8_t *lmk) {
+  encrypt = lmk != NULL;
+  if (encrypt) {
+    memcpy(key, lmk, 16);
+  }
+  if (!_esp_now_has_begun || !added) {
+    return true;
+  }
+  return _esp_now_modify_peer(mac, chan, ifc, encrypt ? key : NULL) == ESP_OK;
+}
+
+size_t ESP_NOW_Peer::send(const uint8_t *data, int len) {
+  log_v(MACSTR ", data length %d", MAC2STR(mac), len);
+  if (!_esp_now_has_begun || !added) {
+    log_e("Peer not added.");
+    return 0;
+  }
+  if (len > ESP_NOW_MAX_DATA_LEN) {
+    len = ESP_NOW_MAX_DATA_LEN;
+  }
+  esp_err_t result = esp_now_send(mac, data, len);
+  if (result == ESP_OK) {
+    return len;
+  } else if (result == ESP_ERR_ESPNOW_NOT_INIT) {
+    log_e("ESPNOW not init.");
+  } else if (result == ESP_ERR_ESPNOW_ARG) {
+    log_e("Invalid argument");
+  } else if (result == ESP_ERR_ESPNOW_INTERNAL) {
+    log_e("Internal Error");
+  } else if (result == ESP_ERR_ESPNOW_NO_MEM) {
+    log_e("Our of memory");
+  } else if (result == ESP_ERR_ESPNOW_NOT_FOUND) {
+    log_e("Peer not found.");
+  } else if (result == ESP_ERR_ESPNOW_IF) {
+    log_e("Interface does not match.");
+  }
+  return 0;
+}
+
+ESP_NOW_Peer::operator bool() const {
+  return added;
+}
+
+#endif
diff --git a/libraries/ESP_NOW/src/ESP32_NOW.h b/libraries/ESP_NOW/src/ESP32_NOW.h
new file mode 100644
index 00000000000..efba9243aee
--- /dev/null
+++ b/libraries/ESP_NOW/src/ESP32_NOW.h
@@ -0,0 +1,86 @@
+#pragma once
+
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#warning "ESP-NOW is only supported in SoCs with native Wi-Fi support"
+#else
+
+#include "esp_wifi_types.h"
+#include "Print.h"
+#include "esp_now.h"
+#include "esp32-hal-log.h"
+#include "esp_mac.h"
+
+class ESP_NOW_Peer;  //forward declaration for friend function
+
+class ESP_NOW_Class : public Print {
+public:
+  const uint8_t BROADCAST_ADDR[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+
+  ESP_NOW_Class();
+  ~ESP_NOW_Class();
+
+  bool begin(const uint8_t *pmk = NULL /* 16 bytes */);
+  bool end();
+
+  int getTotalPeerCount();
+  int getEncryptedPeerCount();
+
+  int availableForWrite();
+  size_t write(const uint8_t *data, size_t len);
+  size_t write(uint8_t data) {
+    return write(&data, 1);
+  }
+
+  void onNewPeer(void (*cb)(const esp_now_recv_info_t *info, const uint8_t *data, int len, void *arg), void *arg);
+  bool removePeer(ESP_NOW_Peer &peer);
+};
+
+class ESP_NOW_Peer {
+private:
+  uint8_t mac[6];
+  uint8_t chan;
+  wifi_interface_t ifc;
+  bool encrypt;
+  uint8_t key[16];
+
+protected:
+  bool added;
+  bool add();
+  bool remove();
+  size_t send(const uint8_t *data, int len);
+
+  ESP_NOW_Peer(const uint8_t *mac_addr, uint8_t channel = 0, wifi_interface_t iface = WIFI_IF_AP, const uint8_t *lmk = NULL);
+
+public:
+  virtual ~ESP_NOW_Peer() {}
+
+  const uint8_t *addr() const;
+  bool addr(const uint8_t *mac_addr);
+
+  uint8_t getChannel() const;
+  bool setChannel(uint8_t channel);
+
+  wifi_interface_t getInterface() const;
+  bool setInterface(wifi_interface_t iface);
+
+  bool isEncrypted() const;
+  bool setKey(const uint8_t *lmk);
+
+  operator bool() const;
+
+  //optional callbacks to be implemented by the upper class
+  virtual void onReceive(const uint8_t *data, size_t len, bool broadcast) {
+    log_i("Received %d bytes from " MACSTR " %s", len, MAC2STR(mac), broadcast ? "(broadcast)" : "");
+  }
+
+  virtual void onSent(bool success) {
+    log_i("Message transmission to peer " MACSTR " %s", MAC2STR(mac), success ? "successful" : "failed");
+  }
+
+  friend bool ESP_NOW_Class::removePeer(ESP_NOW_Peer &);
+};
+
+extern ESP_NOW_Class ESP_NOW;
+
+#endif
diff --git a/libraries/ESP_NOW/src/ESP32_NOW_Serial.cpp b/libraries/ESP_NOW/src/ESP32_NOW_Serial.cpp
new file mode 100644
index 00000000000..5603da2ba13
--- /dev/null
+++ b/libraries/ESP_NOW/src/ESP32_NOW_Serial.cpp
@@ -0,0 +1,286 @@
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#warning "ESP-NOW is only supported in SoCs with native Wi-Fi support"
+#else
+
+#include "ESP32_NOW_Serial.h"
+#include <string.h>
+#include "esp_now.h"
+#include "esp_system.h"
+#include "esp32-hal.h"
+#include "esp_mac.h"
+
+/*
+ *
+ *    Serial Port Implementation Class
+ *
+*/
+
+ESP_NOW_Serial_Class::ESP_NOW_Serial_Class(const uint8_t *mac_addr, uint8_t channel, wifi_interface_t iface, const uint8_t *lmk, bool remove_on_fail)
+  : ESP_NOW_Peer(mac_addr, channel, iface, lmk) {
+  tx_ring_buf = NULL;
+  rx_queue = NULL;
+  tx_sem = NULL;
+  queued_size = 0;
+  queued_buff = NULL;
+  resend_count = 0;
+  _remove_on_fail = remove_on_fail;
+}
+
+ESP_NOW_Serial_Class::~ESP_NOW_Serial_Class() {
+  end();
+}
+
+size_t ESP_NOW_Serial_Class::setTxBufferSize(size_t tx_queue_len) {
+  if (tx_ring_buf) {
+    vRingbufferDelete(tx_ring_buf);
+    tx_ring_buf = NULL;
+  }
+  if (!tx_queue_len) {
+    return 0;
+  }
+  tx_ring_buf = xRingbufferCreate(tx_queue_len, RINGBUF_TYPE_BYTEBUF);
+  if (!tx_ring_buf) {
+    return 0;
+  }
+  return tx_queue_len;
+}
+
+size_t ESP_NOW_Serial_Class::setRxBufferSize(size_t rx_queue_len) {
+  if (rx_queue) {
+    vQueueDelete(rx_queue);
+    rx_queue = NULL;
+  }
+  if (!rx_queue_len) {
+    return 0;
+  }
+  rx_queue = xQueueCreate(rx_queue_len, sizeof(uint8_t));
+  if (!rx_queue) {
+    return 0;
+  }
+  return rx_queue_len;
+}
+
+bool ESP_NOW_Serial_Class::begin(unsigned long baud) {
+  if (!ESP_NOW.begin() || !add()) {
+    return false;
+  }
+  if (tx_sem == NULL) {
+    tx_sem = xSemaphoreCreateBinary();
+    //xSemaphoreTake(tx_sem, 0);
+    xSemaphoreGive(tx_sem);
+  }
+  setRxBufferSize(1024);  //default if not preset
+  setTxBufferSize(1024);  //default if not preset
+  return true;
+}
+
+void ESP_NOW_Serial_Class::end() {
+  remove();
+  setRxBufferSize(0);
+  setTxBufferSize(0);
+  if (tx_sem != NULL) {
+    vSemaphoreDelete(tx_sem);
+    tx_sem = NULL;
+  }
+}
+
+//Stream
+int ESP_NOW_Serial_Class::available(void) {
+  if (rx_queue == NULL) {
+    return 0;
+  }
+  return uxQueueMessagesWaiting(rx_queue);
+}
+
+int ESP_NOW_Serial_Class::peek(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c;
+  if (xQueuePeek(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+int ESP_NOW_Serial_Class::read(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  if (xQueueReceive(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+size_t ESP_NOW_Serial_Class::read(uint8_t *buffer, size_t size) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  size_t count = 0;
+  while (count < size && xQueueReceive(rx_queue, &c, 0)) {
+    buffer[count++] = c;
+  }
+  return count;
+}
+
+void ESP_NOW_Serial_Class::flush() {
+  if (tx_ring_buf == NULL) {
+    return;
+  }
+  UBaseType_t uxItemsWaiting = 0;
+  vRingbufferGetInfo(tx_ring_buf, NULL, NULL, NULL, NULL, &uxItemsWaiting);
+  if (uxItemsWaiting) {
+    // Now trigger the ISR to read data from the ring buffer.
+    if (xSemaphoreTake(tx_sem, 0) == pdTRUE) {
+      checkForTxData();
+    }
+  }
+  while (uxItemsWaiting) {
+    delay(5);
+    vRingbufferGetInfo(tx_ring_buf, NULL, NULL, NULL, NULL, &uxItemsWaiting);
+  }
+}
+
+//RX callback
+void ESP_NOW_Serial_Class::onReceive(const uint8_t *data, size_t len, bool broadcast) {
+  if (rx_queue == NULL) {
+    return;
+  }
+  for (uint32_t i = 0; i < len; i++) {
+    if (!xQueueSend(rx_queue, data + i, 0)) {
+      log_e("RX Overflow!");
+      return;
+    }
+  }
+  // Now trigger the ISR to read data from the ring buffer.
+  if (xSemaphoreTake(tx_sem, 0) == pdTRUE) {
+    checkForTxData();
+  }
+}
+
+//Print
+int ESP_NOW_Serial_Class::availableForWrite() {
+  //return ESP_NOW_MAX_DATA_LEN;
+  if (tx_ring_buf == NULL) {
+    return 0;
+  }
+  return xRingbufferGetCurFreeSize(tx_ring_buf);
+}
+
+size_t ESP_NOW_Serial_Class::tryToSend() {
+  //log_d(MACSTR ": %u", MAC2STR(addr()), queued_size);
+  size_t sent = send(queued_buff, queued_size);
+  if (!sent) {
+    //_onSent will not be called anymore
+    //the data is lost in this case
+    vRingbufferReturnItem(tx_ring_buf, queued_buff);
+    queued_buff = NULL;
+    xSemaphoreGive(tx_sem);
+    end();
+  }
+  return sent;
+}
+
+bool ESP_NOW_Serial_Class::checkForTxData() {
+  //do we have something that failed the last time?
+  resend_count = 0;
+  if (queued_buff == NULL) {
+    queued_buff = (uint8_t *)xRingbufferReceiveUpTo(tx_ring_buf, &queued_size, 0, ESP_NOW_MAX_DATA_LEN);
+  } else {
+    log_d(MACSTR " : PREVIOUS", MAC2STR(addr()));
+  }
+  if (queued_buff != NULL) {
+    return tryToSend() > 0;
+  }
+  //log_d(MACSTR ": EMPTY", MAC2STR(addr()));
+  xSemaphoreGive(tx_sem);
+  return false;
+}
+
+size_t ESP_NOW_Serial_Class::write(const uint8_t *buffer, size_t size, uint32_t timeout) {
+  log_v(MACSTR ", size %u", MAC2STR(addr()), size);
+  if (tx_sem == NULL || tx_ring_buf == NULL || !added) {
+    return 0;
+  }
+  size_t space = availableForWrite();
+  size_t left = size;
+
+  if (space) {
+    if (left < space) {
+      space = left;
+    }
+    if (xRingbufferSend(tx_ring_buf, (void *)(buffer), space, 0) == pdTRUE) {
+      buffer += space;
+      left -= space;
+      if (xSemaphoreTake(tx_sem, 0) == pdTRUE) {
+        if (checkForTxData()) {
+          if (!left) {
+            //we are done
+            return size;
+          }
+        } else {
+          //send failed
+          return 0;
+        }
+      }
+    } else {
+      log_e("RingbufferFastSend Failed");
+      return 0;
+    }
+  } else if (xSemaphoreTake(tx_sem, timeout) == pdTRUE) {
+    checkForTxData();
+  }
+  // Blocking method, Sending data to ringbuffer, and handle the data in ISR.
+  if (xRingbufferSend(tx_ring_buf, (void *)(buffer), left, timeout / portTICK_PERIOD_MS) != pdTRUE) {
+    log_e("RingbufferSend Failed");
+    return size - left;
+  }
+  // Now trigger the ISR to read data from the ring buffer.
+  if (xSemaphoreTake(tx_sem, 0) == pdTRUE) {
+    checkForTxData();
+  }
+
+  return size;
+}
+//TX Done Callback
+void ESP_NOW_Serial_Class::onSent(bool success) {
+  log_v(MACSTR " : %s", MAC2STR(addr()), success ? "OK" : "FAIL");
+  if (tx_sem == NULL || tx_ring_buf == NULL || !added) {
+    return;
+  }
+  if (success) {
+    vRingbufferReturnItem(tx_ring_buf, queued_buff);
+    queued_buff = NULL;
+    //send next packet?
+    //log_d(MACSTR ": NEXT", MAC2STR(addr()));
+    checkForTxData();
+  } else {
+    //send failed
+    //resend
+    if (resend_count < 5) {
+      resend_count++;
+      //log_d(MACSTR ": RE-SENDING[%u]", MAC2STR(addr()), resend_count);
+      tryToSend();
+    } else {
+      //resend limit reached
+      //the data is lost in this case
+      vRingbufferReturnItem(tx_ring_buf, queued_buff);
+      queued_buff = NULL;
+      log_e(MACSTR " : RE-SEND_MAX[%u]", MAC2STR(addr()), resend_count);
+      //if we are not able to send the data and remove_on_fail is set, remove the peer
+      if (_remove_on_fail) {
+        xSemaphoreGive(tx_sem);
+        end();
+        return;
+      }
+      //log_d(MACSTR ": NEXT", MAC2STR(addr()));
+      checkForTxData();
+    }
+  }
+}
+
+#endif
diff --git a/libraries/ESP_NOW/src/ESP32_NOW_Serial.h b/libraries/ESP_NOW/src/ESP32_NOW_Serial.h
new file mode 100644
index 00000000000..7cc43d85ef8
--- /dev/null
+++ b/libraries/ESP_NOW/src/ESP32_NOW_Serial.h
@@ -0,0 +1,57 @@
+#pragma once
+
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#warning "ESP-NOW is only supported in SoCs with native Wi-Fi support"
+#else
+
+#include "esp_wifi_types.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+#include "freertos/ringbuf.h"
+#include "Stream.h"
+#include "ESP32_NOW.h"
+
+class ESP_NOW_Serial_Class : public Stream, public ESP_NOW_Peer {
+private:
+  RingbufHandle_t tx_ring_buf;
+  QueueHandle_t rx_queue;
+  SemaphoreHandle_t tx_sem;
+  size_t queued_size;
+  uint8_t *queued_buff;
+  size_t resend_count;
+  bool _remove_on_fail;
+
+  bool checkForTxData();
+  size_t tryToSend();
+
+public:
+  ESP_NOW_Serial_Class(const uint8_t *mac_addr, uint8_t channel, wifi_interface_t iface = WIFI_IF_AP, const uint8_t *lmk = NULL, bool remove_on_fail = false);
+  ~ESP_NOW_Serial_Class();
+  size_t setRxBufferSize(size_t);
+  size_t setTxBufferSize(size_t);
+  bool begin(unsigned long baud = 0);
+  void end();
+  //Stream
+  int available();
+  int read();
+  size_t read(uint8_t *buffer, size_t size);
+  int peek();
+  void flush();
+  //Print
+  int availableForWrite();
+  size_t write(const uint8_t *buffer, size_t size, uint32_t timeout_ms);
+  size_t write(const uint8_t *buffer, size_t size) {
+    return write(buffer, size, 1000);
+  }
+  size_t write(uint8_t data) {
+    return write(&data, 1);
+  }
+  //ESP_NOW_Peer
+  void onReceive(const uint8_t *data, size_t len, bool broadcast);
+  void onSent(bool success);
+};
+
+#endif
diff --git a/libraries/ESP_SR/examples/Basic/Basic.ino b/libraries/ESP_SR/examples/Basic/Basic.ino
new file mode 100644
index 00000000000..30aab69d79b
--- /dev/null
+++ b/libraries/ESP_SR/examples/Basic/Basic.ino
@@ -0,0 +1,75 @@
+
+#include "ESP_I2S.h"
+#include "ESP_SR.h"
+
+#define I2S_PIN_BCK 17
+#define I2S_PIN_WS  47
+#define I2S_PIN_DIN 16
+
+#define LIGHT_PIN 40
+#define FAN_PIN   41
+
+I2SClass i2s;
+
+// Generated using the following command:
+// python3 tools/gen_sr_commands.py "Turn on the light,Switch on the light;Turn off the light,Switch off the light,Go dark;Start fan;Stop fan"
+enum {
+  SR_CMD_TURN_ON_THE_LIGHT,
+  SR_CMD_TURN_OFF_THE_LIGHT,
+  SR_CMD_START_FAN,
+  SR_CMD_STOP_FAN,
+};
+static const sr_cmd_t sr_commands[] = {
+  {0, "Turn on the light", "TkN nN jc LiT"},
+  {0, "Switch on the light", "SWgp nN jc LiT"},
+  {1, "Turn off the light", "TkN eF jc LiT"},
+  {1, "Switch off the light", "SWgp eF jc LiT"},
+  {1, "Go dark", "Gb DnRK"},
+  {2, "Start fan", "STnRT FaN"},
+  {3, "Stop fan", "STnP FaN"},
+};
+
+void onSrEvent(sr_event_t event, int command_id, int phrase_id) {
+  switch (event) {
+    case SR_EVENT_WAKEWORD: Serial.println("WakeWord Detected!"); break;
+    case SR_EVENT_WAKEWORD_CHANNEL:
+      Serial.printf("WakeWord Channel %d Verified!\n", command_id);
+      ESP_SR.setMode(SR_MODE_COMMAND);  // Switch to Command detection
+      break;
+    case SR_EVENT_TIMEOUT:
+      Serial.println("Timeout Detected!");
+      ESP_SR.setMode(SR_MODE_WAKEWORD);  // Switch back to WakeWord detection
+      break;
+    case SR_EVENT_COMMAND:
+      Serial.printf("Command %d Detected! %s\n", command_id, sr_commands[phrase_id].str);
+      switch (command_id) {
+        case SR_CMD_TURN_ON_THE_LIGHT:  digitalWrite(LIGHT_PIN, HIGH); break;
+        case SR_CMD_TURN_OFF_THE_LIGHT: digitalWrite(LIGHT_PIN, LOW); break;
+        case SR_CMD_START_FAN:          digitalWrite(FAN_PIN, HIGH); break;
+        case SR_CMD_STOP_FAN:           digitalWrite(FAN_PIN, LOW); break;
+        default:                        Serial.println("Unknown Command!"); break;
+      }
+      ESP_SR.setMode(SR_MODE_COMMAND);  // Allow for more commands to be given, before timeout
+      // ESP_SR.setMode(SR_MODE_WAKEWORD); // Switch back to WakeWord detection
+      break;
+    default: Serial.println("Unknown Event!"); break;
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  pinMode(LIGHT_PIN, OUTPUT);
+  digitalWrite(LIGHT_PIN, LOW);
+  pinMode(FAN_PIN, OUTPUT);
+  digitalWrite(FAN_PIN, LOW);
+
+  i2s.setPins(I2S_PIN_BCK, I2S_PIN_WS, -1, I2S_PIN_DIN);
+  i2s.setTimeout(1000);
+  i2s.begin(I2S_MODE_STD, 16000, I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO);
+
+  ESP_SR.onEvent(onSrEvent);
+  ESP_SR.begin(i2s, sr_commands, sizeof(sr_commands) / sizeof(sr_cmd_t), SR_CHANNELS_STEREO, SR_MODE_WAKEWORD);
+}
+
+void loop() {}
diff --git a/libraries/ESP_SR/examples/Basic/ci.json b/libraries/ESP_SR/examples/Basic/ci.json
new file mode 100644
index 00000000000..c395378f45e
--- /dev/null
+++ b/libraries/ESP_SR/examples/Basic/ci.json
@@ -0,0 +1,18 @@
+{
+  "fqbn": {
+    "esp32s3": [
+      "espressif:esp32:esp32s3:USBMode=default,PartitionScheme=esp_sr_16,FlashSize=16M,FlashMode=dio"
+    ]
+  },
+  "requires": [
+    "CONFIG_SOC_I2S_SUPPORTED=y"
+  ],
+  "targets": {
+    "esp32": false,
+    "esp32c3": false,
+    "esp32c6": false,
+    "esp32h2": false,
+    "esp32p4": false,
+    "esp32s2": false
+  }
+}
diff --git a/libraries/ESP_SR/keywords.txt b/libraries/ESP_SR/keywords.txt
new file mode 100644
index 00000000000..30a3925187c
--- /dev/null
+++ b/libraries/ESP_SR/keywords.txt
@@ -0,0 +1,40 @@
+#######################################
+# Syntax Coloring Map For ESP_SR
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+ESP_SR	KEYWORD1
+ESP_SR_Class	KEYWORD1
+sr_cmd_t	KEYWORD1
+sr_event_t	KEYWORD1
+sr_mode_t	KEYWORD1
+sr_channels_t	KEYWORD1
+sr_cb	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+onEvent	KEYWORD2
+setMode	KEYWORD2
+pause	KEYWORD2
+resume	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+
+SR_EVENT_WAKEWORD	LITERAL1
+SR_EVENT_WAKEWORD_CHANNEL	LITERAL1
+SR_EVENT_COMMAND	LITERAL1
+SR_EVENT_TIMEOUT	LITERAL1
+SR_MODE_OFF	LITERAL1
+SR_MODE_WAKEWORD	LITERAL1
+SR_MODE_COMMAND	LITERAL1
+SR_MODE_MAX	LITERAL1
+SR_CHANNELS_MONO	LITERAL1
+SR_CHANNELS_STEREO	LITERAL1
+SR_CHANNELS_MAX	LITERAL1
diff --git a/libraries/ESP_SR/library.properties b/libraries/ESP_SR/library.properties
new file mode 100644
index 00000000000..295761bd9fb
--- /dev/null
+++ b/libraries/ESP_SR/library.properties
@@ -0,0 +1,9 @@
+name=ESP_SR
+version=3.2.0
+author=me-no-dev
+maintainer=me-no-dev
+sentence=Library for ESP Sound Recognition
+paragraph=Supports ESP32 Arduino platforms.
+category=Sound
+url=https://github.com/espressif/arduino-esp32/
+architectures=esp32
diff --git a/libraries/ESP_SR/src/ESP_SR.cpp b/libraries/ESP_SR/src/ESP_SR.cpp
new file mode 100644
index 00000000000..a149c1490e1
--- /dev/null
+++ b/libraries/ESP_SR/src/ESP_SR.cpp
@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include "sdkconfig.h"
+#if CONFIG_IDF_TARGET_ESP32S3 && (CONFIG_USE_WAKENET || CONFIG_USE_MULTINET)
+#include "ESP_SR.h"
+
+static esp_err_t on_sr_fill(void *arg, void *out, size_t len, size_t *bytes_read, uint32_t timeout_ms) {
+  return ((ESP_SR_Class *)arg)->_fill(out, len, bytes_read, timeout_ms);
+}
+
+static void on_sr_event(void *arg, sr_event_t event, int command_id, int phrase_id) {
+  ((ESP_SR_Class *)arg)->_sr_event(event, command_id, phrase_id);
+}
+
+ESP_SR_Class::ESP_SR_Class() : cb(NULL), i2s(NULL) {}
+
+ESP_SR_Class::~ESP_SR_Class() {
+  end();
+}
+
+void ESP_SR_Class::onEvent(sr_cb event_cb) {
+  cb = event_cb;
+}
+
+bool ESP_SR_Class::begin(I2SClass &_i2s, const sr_cmd_t *sr_commands, size_t sr_commands_len, sr_channels_t rx_chan, sr_mode_t mode) {
+  i2s = &_i2s;
+  esp_err_t err = sr_start(on_sr_fill, this, rx_chan, mode, sr_commands, sr_commands_len, on_sr_event, this);
+  return (err == ESP_OK);
+}
+
+bool ESP_SR_Class::end(void) {
+  return sr_stop() == ESP_OK;
+}
+
+bool ESP_SR_Class::setMode(sr_mode_t mode) {
+  return sr_set_mode(mode) == ESP_OK;
+}
+
+bool ESP_SR_Class::pause(void) {
+  return sr_pause() == ESP_OK;
+}
+
+bool ESP_SR_Class::resume(void) {
+  return sr_resume() == ESP_OK;
+}
+
+void ESP_SR_Class::_sr_event(sr_event_t event, int command_id, int phrase_id) {
+  if (cb) {
+    cb(event, command_id, phrase_id);
+  }
+}
+
+esp_err_t ESP_SR_Class::_fill(void *out, size_t len, size_t *bytes_read, uint32_t timeout_ms) {
+  if (i2s == NULL) {
+    return ESP_FAIL;
+  }
+  i2s->setTimeout(timeout_ms);
+  *bytes_read = i2s->readBytes((char *)out, len);
+  return (esp_err_t)i2s->lastError();
+}
+
+ESP_SR_Class ESP_SR;
+
+#endif  // CONFIG_IDF_TARGET_ESP32S3
diff --git a/libraries/ESP_SR/src/ESP_SR.h b/libraries/ESP_SR/src/ESP_SR.h
new file mode 100644
index 00000000000..d637f686f42
--- /dev/null
+++ b/libraries/ESP_SR/src/ESP_SR.h
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#pragma once
+#include "sdkconfig.h"
+#if CONFIG_IDF_TARGET_ESP32S3 && (CONFIG_USE_WAKENET || CONFIG_USE_MULTINET)
+
+#include "ESP_I2S.h"
+#include "esp32-hal-sr.h"
+
+typedef void (*sr_cb)(sr_event_t event, int command_id, int phrase_id);
+
+class ESP_SR_Class {
+private:
+  sr_cb cb;
+  I2SClass *i2s;
+
+public:
+  ESP_SR_Class();
+  ~ESP_SR_Class();
+
+  void onEvent(sr_cb cb);
+  bool begin(I2SClass &i2s, const sr_cmd_t *sr_commands, size_t sr_commands_len, sr_channels_t rx_chan = SR_CHANNELS_STEREO, sr_mode_t mode = SR_MODE_WAKEWORD);
+  bool end(void);
+  bool setMode(sr_mode_t mode);
+  bool pause(void);
+  bool resume(void);
+
+  void _sr_event(sr_event_t event, int command_id, int phrase_id);
+  esp_err_t _fill(void *out, size_t len, size_t *bytes_read, uint32_t timeout_ms);
+};
+
+extern ESP_SR_Class ESP_SR;
+
+#endif  // CONFIG_IDF_TARGET_ESP32S3
diff --git a/libraries/ESP_SR/src/esp32-hal-sr.c b/libraries/ESP_SR/src/esp32-hal-sr.c
new file mode 100644
index 00000000000..06db7236541
--- /dev/null
+++ b/libraries/ESP_SR/src/esp32-hal-sr.c
@@ -0,0 +1,439 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include "sdkconfig.h"
+#if CONFIG_IDF_TARGET_ESP32S3 && (CONFIG_USE_WAKENET || CONFIG_USE_MULTINET)
+
+#if !defined(ARDUINO_PARTITION_esp_sr_32) && !defined(ARDUINO_PARTITION_esp_sr_16) && !defined(ARDUINO_PARTITION_esp_sr_8)
+#warning Compatible partition must be selected for ESP_SR to work
+#endif
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+#include <sys/queue.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/queue.h"
+#include "freertos/event_groups.h"
+#include "freertos/task.h"
+#include "esp_task_wdt.h"
+#include "esp_check.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp_mn_speech_commands.h"
+#include "esp_process_sdkconfig.h"
+#include "esp_afe_sr_models.h"
+#include "esp_mn_models.h"
+#include "esp_wn_iface.h"
+#include "esp_wn_models.h"
+#include "esp_afe_sr_iface.h"
+#include "esp_mn_iface.h"
+#include "model_path.h"
+
+#include "driver/i2s_common.h"
+#include "esp32-hal-sr.h"
+#include "esp32-hal-log.h"
+
+#undef ESP_GOTO_ON_FALSE
+#define ESP_GOTO_ON_FALSE(a, err_code, goto_tag, format, ...) \
+  do {                                                        \
+    if (unlikely(!(a))) {                                     \
+      log_e(format, ##__VA_ARGS__);                           \
+      ret = err_code;                                         \
+      goto goto_tag;                                          \
+    }                                                         \
+  } while (0)
+
+#undef ESP_RETURN_ON_FALSE
+#define ESP_RETURN_ON_FALSE(a, err_code, format, ...) \
+  do {                                                \
+    if (unlikely(!(a))) {                             \
+      log_e(format, ##__VA_ARGS__);                   \
+      return err_code;                                \
+    }                                                 \
+  } while (0)
+
+#define NEED_DELETE    BIT0
+#define FEED_DELETED   BIT1
+#define DETECT_DELETED BIT2
+#define PAUSE_FEED     BIT3
+#define PAUSE_DETECT   BIT4
+#define RESUME_FEED    BIT5
+#define RESUME_DETECT  BIT6
+
+typedef struct {
+  wakenet_state_t wakenet_mode;
+  esp_mn_state_t state;
+  int command_id;
+  int phrase_id;
+} sr_result_t;
+
+typedef struct {
+  model_iface_data_t *model_data;
+  const esp_mn_iface_t *multinet;
+  const esp_afe_sr_iface_t *afe_handle;
+  esp_afe_sr_data_t *afe_data;
+  int16_t *afe_in_buffer;
+  sr_mode_t mode;
+  uint8_t i2s_rx_chan_num;
+  sr_event_cb user_cb;
+  void *user_cb_arg;
+  sr_fill_cb fill_cb;
+  void *fill_cb_arg;
+  TaskHandle_t feed_task;
+  TaskHandle_t detect_task;
+  TaskHandle_t handle_task;
+  QueueHandle_t result_que;
+  EventGroupHandle_t event_group;
+} sr_data_t;
+
+static int SR_CHANNEL_NUM = 3;
+
+static srmodel_list_t *models = NULL;
+static sr_data_t *g_sr_data = NULL;
+
+esp_err_t sr_set_mode(sr_mode_t mode);
+
+void sr_handler_task(void *pvParam) {
+  while (true) {
+    sr_result_t result;
+    if (xQueueReceive(g_sr_data->result_que, &result, portMAX_DELAY) != pdTRUE) {
+      continue;
+    }
+
+    if (WAKENET_DETECTED == result.wakenet_mode) {
+      if (g_sr_data->user_cb) {
+        g_sr_data->user_cb(g_sr_data->user_cb_arg, SR_EVENT_WAKEWORD, -1, -1);
+      }
+      continue;
+    }
+
+    if (WAKENET_CHANNEL_VERIFIED == result.wakenet_mode) {
+      if (g_sr_data->user_cb) {
+        g_sr_data->user_cb(g_sr_data->user_cb_arg, SR_EVENT_WAKEWORD_CHANNEL, result.command_id, -1);
+      }
+      continue;
+    }
+
+    if (ESP_MN_STATE_DETECTED == result.state) {
+      if (g_sr_data->user_cb) {
+        g_sr_data->user_cb(g_sr_data->user_cb_arg, SR_EVENT_COMMAND, result.command_id, result.phrase_id);
+      }
+      continue;
+    }
+
+    if (ESP_MN_STATE_TIMEOUT == result.state) {
+      if (g_sr_data->user_cb) {
+        g_sr_data->user_cb(g_sr_data->user_cb_arg, SR_EVENT_TIMEOUT, -1, -1);
+      }
+      continue;
+    }
+  }
+  vTaskDelete(NULL);
+}
+
+static void audio_feed_task(void *arg) {
+  size_t bytes_read = 0;
+  int audio_chunksize = g_sr_data->afe_handle->get_feed_chunksize(g_sr_data->afe_data);
+  log_i("audio_chunksize=%d, feed_channel=%d", audio_chunksize, SR_CHANNEL_NUM);
+
+  /* Allocate audio buffer and check for result */
+  int16_t *audio_buffer = heap_caps_malloc(audio_chunksize * sizeof(int16_t) * SR_CHANNEL_NUM, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+  if (NULL == audio_buffer) {
+    esp_system_abort("No mem for audio buffer");
+  }
+  g_sr_data->afe_in_buffer = audio_buffer;
+
+  while (true) {
+    EventBits_t bits = xEventGroupGetBits(g_sr_data->event_group);
+    if (NEED_DELETE & bits) {
+      xEventGroupSetBits(g_sr_data->event_group, FEED_DELETED);
+      break;
+    }
+    if (PAUSE_FEED & bits) {
+      xEventGroupWaitBits(g_sr_data->event_group, PAUSE_FEED | RESUME_FEED, 1, 1, portMAX_DELAY);
+    }
+
+    /* Read audio data from I2S bus */
+    //ToDo: handle error
+    if (g_sr_data->fill_cb == NULL) {
+      vTaskDelay(100);
+      continue;
+    }
+    esp_err_t err = g_sr_data->fill_cb(
+      g_sr_data->fill_cb_arg, (char *)audio_buffer, audio_chunksize * g_sr_data->i2s_rx_chan_num * sizeof(int16_t), &bytes_read, portMAX_DELAY
+    );
+    if (err != ESP_OK) {
+      vTaskDelay(100);
+      continue;
+    }
+
+    /* Channel Adjust */
+    if (g_sr_data->i2s_rx_chan_num == 1) {
+      for (int i = audio_chunksize - 1; i >= 0; i--) {
+        audio_buffer[i * SR_CHANNEL_NUM + 2] = 0;
+        audio_buffer[i * SR_CHANNEL_NUM + 1] = 0;
+        audio_buffer[i * SR_CHANNEL_NUM + 0] = audio_buffer[i];
+      }
+    } else if (g_sr_data->i2s_rx_chan_num == 2) {
+      for (int i = audio_chunksize - 1; i >= 0; i--) {
+        audio_buffer[i * SR_CHANNEL_NUM + 2] = 0;
+        audio_buffer[i * SR_CHANNEL_NUM + 1] = audio_buffer[i * 2 + 1];
+        audio_buffer[i * SR_CHANNEL_NUM + 0] = audio_buffer[i * 2 + 0];
+      }
+    } else {
+      vTaskDelay(100);
+      continue;
+    }
+
+    /* Feed samples of an audio stream to the AFE_SR */
+    g_sr_data->afe_handle->feed(g_sr_data->afe_data, audio_buffer);
+  }
+  vTaskDelete(NULL);
+}
+
+static void audio_detect_task(void *arg) {
+  int afe_chunksize = g_sr_data->afe_handle->get_fetch_chunksize(g_sr_data->afe_data);
+  int mu_chunksize = g_sr_data->multinet->get_samp_chunksize(g_sr_data->model_data);
+  assert(mu_chunksize == afe_chunksize);
+  log_i("------------detect start------------");
+
+  while (true) {
+    EventBits_t bits = xEventGroupGetBits(g_sr_data->event_group);
+    if (NEED_DELETE & bits) {
+      xEventGroupSetBits(g_sr_data->event_group, DETECT_DELETED);
+      break;
+    }
+    if (PAUSE_DETECT & bits) {
+      xEventGroupWaitBits(g_sr_data->event_group, PAUSE_DETECT | RESUME_DETECT, 1, 1, portMAX_DELAY);
+    }
+
+    afe_fetch_result_t *res = g_sr_data->afe_handle->fetch(g_sr_data->afe_data);
+    if (!res || res->ret_value == ESP_FAIL) {
+      continue;
+    }
+
+    if (g_sr_data->mode == SR_MODE_WAKEWORD) {
+      if (res->wakeup_state == WAKENET_DETECTED) {
+        log_d("wakeword detected");
+        sr_result_t result = {
+          .wakenet_mode = WAKENET_DETECTED,
+          .state = ESP_MN_STATE_DETECTING,
+          .command_id = 0,
+          .phrase_id = 0,
+        };
+        xQueueSend(g_sr_data->result_que, &result, 0);
+      } else if (res->wakeup_state == WAKENET_CHANNEL_VERIFIED) {
+        sr_set_mode(SR_MODE_OFF);
+        log_d("AFE_FETCH_CHANNEL_VERIFIED, channel index: %d", res->trigger_channel_id);
+        sr_result_t result = {
+          .wakenet_mode = WAKENET_CHANNEL_VERIFIED,
+          .state = ESP_MN_STATE_DETECTING,
+          .command_id = res->trigger_channel_id,
+          .phrase_id = 0,
+        };
+        xQueueSend(g_sr_data->result_que, &result, 0);
+      }
+    }
+
+    if (g_sr_data->mode == SR_MODE_COMMAND) {
+
+      esp_mn_state_t mn_state = ESP_MN_STATE_DETECTING;
+      mn_state = g_sr_data->multinet->detect(g_sr_data->model_data, res->data);
+
+      if (ESP_MN_STATE_DETECTING == mn_state) {
+        continue;
+      }
+
+      if (ESP_MN_STATE_TIMEOUT == mn_state) {
+        sr_set_mode(SR_MODE_OFF);
+        log_d("Time out");
+        sr_result_t result = {
+          .wakenet_mode = WAKENET_NO_DETECT,
+          .state = mn_state,
+          .command_id = 0,
+          .phrase_id = 0,
+        };
+        xQueueSend(g_sr_data->result_que, &result, 0);
+        continue;
+      }
+
+      if (ESP_MN_STATE_DETECTED == mn_state) {
+        sr_set_mode(SR_MODE_OFF);
+        esp_mn_results_t *mn_result = g_sr_data->multinet->get_results(g_sr_data->model_data);
+        for (int i = 0; i < mn_result->num; i++) {
+          log_d("TOP %d, command_id: %d, phrase_id: %d, prob: %f", i + 1, mn_result->command_id[i], mn_result->phrase_id[i], mn_result->prob[i]);
+        }
+
+        int sr_command_id = mn_result->command_id[0];
+        int sr_phrase_id = mn_result->phrase_id[0];
+        log_d("Detected command : %d, phrase: %d", sr_command_id, sr_phrase_id);
+        sr_result_t result = {
+          .wakenet_mode = WAKENET_NO_DETECT,
+          .state = mn_state,
+          .command_id = sr_command_id,
+          .phrase_id = sr_phrase_id,
+        };
+        xQueueSend(g_sr_data->result_que, &result, 0);
+        continue;
+      }
+      log_e("Exception unhandled");
+    }
+  }
+  vTaskDelete(NULL);
+}
+
+esp_err_t sr_set_mode(sr_mode_t mode) {
+  ESP_RETURN_ON_FALSE(NULL != g_sr_data, ESP_ERR_INVALID_STATE, "SR is not running");
+  switch (mode) {
+    case SR_MODE_OFF:
+      if (g_sr_data->mode == SR_MODE_WAKEWORD) {
+        g_sr_data->afe_handle->disable_wakenet(g_sr_data->afe_data);
+      }
+      break;
+    case SR_MODE_WAKEWORD:
+      if (g_sr_data->mode != SR_MODE_WAKEWORD) {
+        g_sr_data->afe_handle->enable_wakenet(g_sr_data->afe_data);
+      }
+      break;
+    case SR_MODE_COMMAND:
+      if (g_sr_data->mode == SR_MODE_WAKEWORD) {
+        g_sr_data->afe_handle->disable_wakenet(g_sr_data->afe_data);
+      }
+      break;
+    default: return ESP_FAIL;
+  }
+  g_sr_data->mode = mode;
+  return ESP_OK;
+}
+
+esp_err_t sr_start(
+  sr_fill_cb fill_cb, void *fill_cb_arg, sr_channels_t rx_chan, sr_mode_t mode, const sr_cmd_t sr_commands[], size_t cmd_number, sr_event_cb cb, void *cb_arg
+) {
+  esp_err_t ret = ESP_OK;
+  ESP_RETURN_ON_FALSE(NULL == g_sr_data, ESP_ERR_INVALID_STATE, "SR already running");
+
+  g_sr_data = heap_caps_calloc(1, sizeof(sr_data_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
+  ESP_RETURN_ON_FALSE(NULL != g_sr_data, ESP_ERR_NO_MEM, "Failed create sr data");
+
+  g_sr_data->result_que = xQueueCreate(3, sizeof(sr_result_t));
+  ESP_GOTO_ON_FALSE(NULL != g_sr_data->result_que, ESP_ERR_NO_MEM, err, "Failed create result queue");
+
+  g_sr_data->event_group = xEventGroupCreate();
+  ESP_GOTO_ON_FALSE(NULL != g_sr_data->event_group, ESP_ERR_NO_MEM, err, "Failed create event_group");
+
+  BaseType_t ret_val;
+  g_sr_data->user_cb = cb;
+  g_sr_data->user_cb_arg = cb_arg;
+  g_sr_data->fill_cb = fill_cb;
+  g_sr_data->fill_cb_arg = fill_cb_arg;
+  g_sr_data->i2s_rx_chan_num = rx_chan + 1;
+  g_sr_data->mode = mode;
+
+  // Init Model
+  log_d("init model");
+  models = esp_srmodel_init("model");
+
+  // Load WakeWord Detection
+  g_sr_data->afe_handle = (esp_afe_sr_iface_t *)&ESP_AFE_SR_HANDLE;
+  afe_config_t afe_config = AFE_CONFIG_DEFAULT();
+  afe_config.wakenet_model_name = esp_srmodel_filter(models, ESP_WN_PREFIX, "hiesp");
+  afe_config.aec_init = false;
+  log_d("load wakenet '%s'", afe_config.wakenet_model_name);
+  g_sr_data->afe_data = g_sr_data->afe_handle->create_from_config(&afe_config);
+
+  // Load Custom Command Detection
+  char *mn_name = esp_srmodel_filter(models, ESP_MN_PREFIX, ESP_MN_ENGLISH);
+  log_d("load multinet '%s'", mn_name);
+  g_sr_data->multinet = esp_mn_handle_from_name(mn_name);
+  log_d("load model_data '%s'", mn_name);
+  g_sr_data->model_data = g_sr_data->multinet->create(mn_name, 5760);
+
+  // Add commands
+  esp_mn_commands_alloc((esp_mn_iface_t *)g_sr_data->multinet, (model_iface_data_t *)g_sr_data->model_data);
+  log_i("add %d commands", cmd_number);
+  for (size_t i = 0; i < cmd_number; i++) {
+    esp_mn_commands_add(sr_commands[i].command_id, (char *)(sr_commands[i].phoneme));
+    log_i("  cmd[%d] phrase[%d]:'%s'", sr_commands[i].command_id, i, sr_commands[i].str);
+  }
+
+  // Load commands
+  esp_mn_error_t *err_id = esp_mn_commands_update();
+  if (err_id) {
+    for (int i = 0; i < err_id->num; i++) {
+      log_e("err cmd id:%d", err_id->phrases[i]->command_id);
+    }
+  }
+
+  //Start tasks
+  log_d("start tasks");
+  ret_val = xTaskCreatePinnedToCore(&audio_feed_task, "SR Feed Task", 4 * 1024, NULL, 5, &g_sr_data->feed_task, 0);
+  ESP_GOTO_ON_FALSE(pdPASS == ret_val, ESP_FAIL, err, "Failed create audio feed task");
+  vTaskDelay(10);
+  ret_val = xTaskCreatePinnedToCore(&audio_detect_task, "SR Detect Task", 8 * 1024, NULL, 5, &g_sr_data->detect_task, 1);
+  ESP_GOTO_ON_FALSE(pdPASS == ret_val, ESP_FAIL, err, "Failed create audio detect task");
+  ret_val = xTaskCreatePinnedToCore(&sr_handler_task, "SR Handler Task", 6 * 1024, NULL, configMAX_PRIORITIES - 1, &g_sr_data->handle_task, 1);
+  //ret_val = xTaskCreatePinnedToCore(&sr_handler_task, "SR Handler Task", 6 * 1024, NULL, configMAX_PRIORITIES - 1, &g_sr_data->handle_task, 0);
+  ESP_GOTO_ON_FALSE(pdPASS == ret_val, ESP_FAIL, err, "Failed create audio handler task");
+
+  return ESP_OK;
+err:
+  sr_stop();
+  return ret;
+}
+
+esp_err_t sr_stop(void) {
+  ESP_RETURN_ON_FALSE(NULL != g_sr_data, ESP_ERR_INVALID_STATE, "SR is not running");
+
+  /**
+     * Waiting for all task stopped
+     * TODO: A task creation failure cannot be handled correctly now
+     * */
+  vTaskDelete(g_sr_data->handle_task);
+  xEventGroupSetBits(g_sr_data->event_group, NEED_DELETE);
+  xEventGroupWaitBits(g_sr_data->event_group, NEED_DELETE | FEED_DELETED | DETECT_DELETED, 1, 1, portMAX_DELAY);
+
+  if (g_sr_data->result_que) {
+    vQueueDelete(g_sr_data->result_que);
+    g_sr_data->result_que = NULL;
+  }
+
+  if (g_sr_data->event_group) {
+    vEventGroupDelete(g_sr_data->event_group);
+    g_sr_data->event_group = NULL;
+  }
+
+  if (g_sr_data->model_data) {
+    g_sr_data->multinet->destroy(g_sr_data->model_data);
+  }
+
+  if (g_sr_data->afe_data) {
+    g_sr_data->afe_handle->destroy(g_sr_data->afe_data);
+  }
+
+  if (g_sr_data->afe_in_buffer) {
+    heap_caps_free(g_sr_data->afe_in_buffer);
+  }
+
+  heap_caps_free(g_sr_data);
+  g_sr_data = NULL;
+  return ESP_OK;
+}
+
+esp_err_t sr_pause(void) {
+  ESP_RETURN_ON_FALSE(NULL != g_sr_data, ESP_ERR_INVALID_STATE, "SR is not running");
+  xEventGroupSetBits(g_sr_data->event_group, PAUSE_FEED | PAUSE_DETECT);
+  return ESP_OK;
+}
+
+esp_err_t sr_resume(void) {
+  ESP_RETURN_ON_FALSE(NULL != g_sr_data, ESP_ERR_INVALID_STATE, "SR is not running");
+  xEventGroupSetBits(g_sr_data->event_group, RESUME_FEED | RESUME_DETECT);
+  return ESP_OK;
+}
+
+#endif  // CONFIG_IDF_TARGET_ESP32S3
diff --git a/libraries/ESP_SR/src/esp32-hal-sr.h b/libraries/ESP_SR/src/esp32-hal-sr.h
new file mode 100644
index 00000000000..894390634e0
--- /dev/null
+++ b/libraries/ESP_SR/src/esp32-hal-sr.h
@@ -0,0 +1,78 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#pragma once
+#include "sdkconfig.h"
+#if CONFIG_IDF_TARGET_ESP32S3 && (CONFIG_USE_WAKENET || CONFIG_USE_MULTINET)
+
+#include "driver/i2s_types.h"
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SR_CMD_STR_LEN_MAX     64
+#define SR_CMD_PHONEME_LEN_MAX 64
+
+typedef struct sr_cmd_t {
+  int command_id;
+  char str[SR_CMD_STR_LEN_MAX];
+  char phoneme[SR_CMD_PHONEME_LEN_MAX];
+} sr_cmd_t;
+
+typedef enum {
+  SR_EVENT_WAKEWORD,          //WakeWord Detected
+  SR_EVENT_WAKEWORD_CHANNEL,  //WakeWord Channel Verified
+  SR_EVENT_COMMAND,           //Command Detected
+  SR_EVENT_TIMEOUT,           //Command Timeout
+  SR_EVENT_MAX
+} sr_event_t;
+
+typedef enum {
+  SR_MODE_OFF,       //Detection Off
+  SR_MODE_WAKEWORD,  //WakeWord Detection
+  SR_MODE_COMMAND,   //Command Detection
+  SR_MODE_MAX
+} sr_mode_t;
+
+typedef enum {
+  SR_CHANNELS_MONO,
+  SR_CHANNELS_STEREO,
+  SR_CHANNELS_MAX
+} sr_channels_t;
+
+typedef void (*sr_event_cb)(void *arg, sr_event_t event, int command_id, int phrase_id);
+typedef esp_err_t (*sr_fill_cb)(void *arg, void *out, size_t len, size_t *bytes_read, uint32_t timeout_ms);
+
+esp_err_t sr_start(
+  sr_fill_cb fill_cb, void *fill_cb_arg, sr_channels_t rx_chan, sr_mode_t mode, const sr_cmd_t *sr_commands, size_t cmd_number, sr_event_cb cb, void *cb_arg
+);
+esp_err_t sr_stop(void);
+esp_err_t sr_pause(void);
+esp_err_t sr_resume(void);
+esp_err_t sr_set_mode(sr_mode_t mode);
+
+// static const sr_cmd_t sr_commands[] = {
+//     {0, "Turn On the Light", "TkN nN jc LiT"},
+//     {0, "Switch On the Light", "SWgp nN jc LiT"},
+//     {1, "Switch Off the Light", "SWgp eF jc LiT"},
+//     {1, "Turn Off the Light", "TkN eF jc LiT"},
+//     {2, "Turn Red", "TkN RfD"},
+//     {3, "Turn Green", "TkN GRmN"},
+//     {4, "Turn Blue", "TkN BLo"},
+//     {5, "Customize Color", "KcSTcMiZ KcLk"},
+//     {6, "Sing a song", "Sgl c Sel"},
+//     {7, "Play Music", "PLd MYoZgK"},
+//     {8, "Next Song", "NfKST Sel"},
+//     {9, "Pause Playing", "PeZ PLdgl"},
+// };
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // CONFIG_IDF_TARGET_ESP32S3
diff --git a/libraries/ESP_SR/tools/gen_sr_commands.py b/libraries/ESP_SR/tools/gen_sr_commands.py
new file mode 100644
index 00000000000..3ac08cc6e44
--- /dev/null
+++ b/libraries/ESP_SR/tools/gen_sr_commands.py
@@ -0,0 +1,146 @@
+# pip3 install g2p_en
+from g2p_en import G2p
+import argparse
+
+# python3 gen_sr_commands.py "Turn on the light,Switch on the light;Turn off the light,Switch off the light,Go dark;\
+# Start fan;Stop fan;Volume down,Turn down;Mute sound;Next song;Pause playback"
+# enum {
+#   SR_CMD_TURN_ON_THE_LIGHT,
+#   SR_CMD_TURN_OFF_THE_LIGHT,
+#   SR_CMD_START_FAN,
+#   SR_CMD_STOP_FAN,
+#   SR_CMD_VOLUME_DOWN,
+#   SR_CMD_MUTE_SOUND,
+#   SR_CMD_NEXT_SONG,
+#   SR_CMD_PAUSE_PLAYBACK,
+# };
+# static const sr_cmd_t sr_commands[] = {
+#   { 0, "Turn on the light", "TkN nN jc LiT"},
+#   { 0, "Switch on the light", "SWgp nN jc LiT"},
+#   { 1, "Turn off the light", "TkN eF jc LiT"},
+#   { 1, "Switch off the light", "SWgp eF jc LiT"},
+#   { 1, "Go dark", "Gb DnRK"},
+#   { 2, "Start fan", "STnRT FaN"},
+#   { 3, "Stop fan", "STnP FaN"},
+#   { 4, "Volume down", "VnLYoM DtN"},
+#   { 4, "Turn down", "TkN DtN"},
+#   { 5, "Mute sound", "MYoT StND"},
+#   { 6, "Next song", "NfKST Sel"},
+#   { 7, "Pause playback", "PeZ PLdBaK"},
+# };
+
+
+def english_g2p(text):
+    g2p = G2p()
+    out = "static const sr_cmd_t sr_commands[] = {\n"
+    enum = "enum {\n"
+    alphabet = {
+        "AE1": "a",
+        "N": "N",
+        " ": " ",
+        "OW1": "b",
+        "V": "V",
+        "AH0": "c",
+        "L": "L",
+        "F": "F",
+        "EY1": "d",
+        "S": "S",
+        "B": "B",
+        "R": "R",
+        "AO1": "e",
+        "D": "D",
+        "AH1": "c",
+        "EH1": "f",
+        "OW0": "b",
+        "IH0": "g",
+        "G": "G",
+        "HH": "h",
+        "K": "K",
+        "IH1": "g",
+        "W": "W",
+        "AY1": "i",
+        "T": "T",
+        "M": "M",
+        "Z": "Z",
+        "DH": "j",
+        "ER0": "k",
+        "P": "P",
+        "NG": "l",
+        "IY1": "m",
+        "AA1": "n",
+        "Y": "Y",
+        "UW1": "o",
+        "IY0": "m",
+        "EH2": "f",
+        "CH": "p",
+        "AE0": "a",
+        "JH": "q",
+        "ZH": "r",
+        "AA2": "n",
+        "SH": "s",
+        "AW1": "t",
+        "OY1": "u",
+        "AW2": "t",
+        "IH2": "g",
+        "AE2": "a",
+        "EY2": "d",
+        "ER1": "k",
+        "TH": "v",
+        "UH1": "w",
+        "UW2": "o",
+        "OW2": "b",
+        "AY2": "i",
+        "UW0": "o",
+        "AH2": "c",
+        "EH0": "f",
+        "AW0": "t",
+        "AO2": "e",
+        "AO0": "e",
+        "UH0": "w",
+        "UH2": "w",
+        "AA0": "n",
+        "AY0": "i",
+        "IY2": "m",
+        "EY0": "d",
+        "ER2": "k",
+        "OY2": "u",
+        "OY0": "u",
+    }
+
+    cmd_id = 0
+    phrase_id = 0
+    text_list = text.split(";")
+    for item in text_list:
+        item = item.split(",")
+        phrase_id = 0
+        for phrase in item:
+            labels = g2p(phrase)
+            phoneme = ""
+            for char in labels:
+                if char not in alphabet:
+                    print("skip %s, not found in alphabet")
+                    continue
+                else:
+                    phoneme += alphabet[char]
+            out += "  { " + str(cmd_id) + ', "' + phrase + '", "' + phoneme + '"},\n'
+            if phrase_id == 0:
+                enum += "  SR_CMD_" + phrase.upper().replace(" ", "_") + ",\n"
+            phrase_id += 1
+        cmd_id += 1
+    out += "};"
+    enum += "};"
+    # print(text)
+    print(enum)
+    print(out)
+
+    return out
+
+
+if __name__ == "__main__":
+
+    parser = argparse.ArgumentParser(prog="English Speech Commands G2P")
+    parser.add_argument("text", type=str, default=None, help="input text")
+    args = parser.parse_args()
+
+    if args.text is not None:
+        english_g2p(args.text)
diff --git a/libraries/ESPmDNS/examples/mDNS-SD_Extended/ci.json b/libraries/ESPmDNS/examples/mDNS-SD_Extended/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/ESPmDNS/examples/mDNS-SD_Extended/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/ESPmDNS/examples/mDNS-SD_Extended/mDNS-SD_Extended.ino b/libraries/ESPmDNS/examples/mDNS-SD_Extended/mDNS-SD_Extended.ino
index 6f2dfddfb3b..e630d668cea 100644
--- a/libraries/ESPmDNS/examples/mDNS-SD_Extended/mDNS-SD_Extended.ino
+++ b/libraries/ESPmDNS/examples/mDNS-SD_Extended/mDNS-SD_Extended.ino
@@ -2,7 +2,7 @@
   ESP8266 mDNS-SD responder and query sample
 
   This is an example of announcing and finding services.
-  
+
   Instructions:
   - Update WiFi SSID and password as necessary.
   - Flash the sketch to two ESP8266 boards
@@ -12,69 +12,71 @@
 #include <WiFi.h>
 #include <ESPmDNS.h>
 
-const char* ssid     = "...";
-const char* password = "...";
+const char *ssid = "...";
+const char *password = "...";
 
 void setup() {
-    Serial.begin(115200);
-    WiFi.begin(ssid, password);
-    while (WiFi.status() != WL_CONNECTED) {
-        delay(250);
-        Serial.print(".");
-    }
-    Serial.println("");
-    Serial.print("Connected to ");
-    Serial.println(ssid);
-    Serial.print("IP address: ");
-    Serial.println(WiFi.localIP());
+  Serial.begin(115200);
+  WiFi.begin(ssid, password);
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(250);
+    Serial.print(".");
+  }
+  Serial.println("");
+  Serial.print("Connected to ");
+  Serial.println(ssid);
+  Serial.print("IP address: ");
+  Serial.println(WiFi.localIP());
 
-    if (!MDNS.begin("ESP32_Browser")) {
-        Serial.println("Error setting up MDNS responder!");
-        while(1){
-            delay(1000);
-        }
+  if (!MDNS.begin("ESP32_Browser")) {
+    Serial.println("Error setting up MDNS responder!");
+    while (1) {
+      delay(1000);
     }
+  }
 }
 
 void loop() {
-    browseService("http", "tcp");
-    delay(1000);
-    browseService("arduino", "tcp");
-    delay(1000);
-    browseService("workstation", "tcp");
-    delay(1000);
-    browseService("smb", "tcp");
-    delay(1000);
-    browseService("afpovertcp", "tcp");
-    delay(1000);
-    browseService("ftp", "tcp");
-    delay(1000);
-    browseService("ipp", "tcp");
-    delay(1000);
-    browseService("printer", "tcp");
-    delay(10000);
+  browseService("http", "tcp");
+  delay(1000);
+  browseService("arduino", "tcp");
+  delay(1000);
+  browseService("workstation", "tcp");
+  delay(1000);
+  browseService("smb", "tcp");
+  delay(1000);
+  browseService("afpovertcp", "tcp");
+  delay(1000);
+  browseService("ftp", "tcp");
+  delay(1000);
+  browseService("ipp", "tcp");
+  delay(1000);
+  browseService("printer", "tcp");
+  delay(10000);
 }
 
-void browseService(const char * service, const char * proto){
-    Serial.printf("Browsing for service _%s._%s.local. ... ", service, proto);
-    int n = MDNS.queryService(service, proto);
-    if (n == 0) {
-        Serial.println("no services found");
-    } else {
-        Serial.print(n);
-        Serial.println(" service(s) found");
-        for (int i = 0; i < n; ++i) {
-            // Print details for each service found
-            Serial.print("  ");
-            Serial.print(i + 1);
-            Serial.print(": ");
-            Serial.print(MDNS.hostname(i));
-            Serial.print(" (");
-            Serial.print(MDNS.IP(i));
-            Serial.print(":");
-            Serial.print(MDNS.port(i));
-            Serial.println(")");
-        }
+void browseService(const char *service, const char *proto) {
+  Serial.printf("Browsing for service _%s._%s.local. ... ", service, proto);
+  int n = MDNS.queryService(service, proto);
+  if (n == 0) {
+    Serial.println("no services found");
+  } else {
+    Serial.print(n);
+    Serial.println(" service(s) found");
+    for (int i = 0; i < n; ++i) {
+      // Print details for each service found
+      Serial.print("  ");
+      Serial.print(i + 1);
+      Serial.print(": ");
+      Serial.print(MDNS.instanceName(i));
+      Serial.print(" - ");
+      Serial.print(MDNS.hostname(i));
+      Serial.print(" (");
+      Serial.print(MDNS.address(i));
+      Serial.print(":");
+      Serial.print(MDNS.port(i));
+      Serial.println(")");
     }
-    Serial.println();
+  }
+  Serial.println();
 }
diff --git a/libraries/ESPmDNS/examples/mDNS_Web_Server/ci.json b/libraries/ESPmDNS/examples/mDNS_Web_Server/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/ESPmDNS/examples/mDNS_Web_Server/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/ESPmDNS/examples/mDNS_Web_Server/mDNS_Web_Server.ino b/libraries/ESPmDNS/examples/mDNS_Web_Server/mDNS_Web_Server.ino
index 946f51aacc1..759a62d5693 100644
--- a/libraries/ESPmDNS/examples/mDNS_Web_Server/mDNS_Web_Server.ino
+++ b/libraries/ESPmDNS/examples/mDNS_Web_Server/mDNS_Web_Server.ino
@@ -15,106 +15,99 @@
 
  */
 
-
 #include <WiFi.h>
 #include <ESPmDNS.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 
-const char* ssid = "............";
-const char* password = "..............";
+const char *ssid = "............";
+const char *password = "..............";
 
 // TCP server at port 80 will respond to HTTP requests
-WiFiServer server(80);
-
-void setup(void)
-{  
-    Serial.begin(115200);
-
-    // Connect to WiFi network
-    WiFi.begin(ssid, password);
-    Serial.println("");
-
-    // Wait for connection
-    while (WiFi.status() != WL_CONNECTED) {
-        delay(500);
-        Serial.print(".");
+NetworkServer server(80);
+
+void setup(void) {
+  Serial.begin(115200);
+
+  // Connect to WiFi network
+  WiFi.begin(ssid, password);
+  Serial.println("");
+
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("");
+  Serial.print("Connected to ");
+  Serial.println(ssid);
+  Serial.print("IP address: ");
+  Serial.println(WiFi.localIP());
+
+  // Set up mDNS responder:
+  // - first argument is the domain name, in this example
+  //   the fully-qualified domain name is "esp32.local"
+  // - second argument is the IP address to advertise
+  //   we send our IP address on the WiFi network
+  if (!MDNS.begin("esp32")) {
+    Serial.println("Error setting up MDNS responder!");
+    while (1) {
+      delay(1000);
     }
-    Serial.println("");
-    Serial.print("Connected to ");
-    Serial.println(ssid);
-    Serial.print("IP address: ");
-    Serial.println(WiFi.localIP());
-
-    // Set up mDNS responder:
-    // - first argument is the domain name, in this example
-    //   the fully-qualified domain name is "esp32.local"
-    // - second argument is the IP address to advertise
-    //   we send our IP address on the WiFi network
-    if (!MDNS.begin("esp32")) {
-        Serial.println("Error setting up MDNS responder!");
-        while(1) {
-            delay(1000);
-        }
-    }
-    Serial.println("mDNS responder started");
+  }
+  Serial.println("mDNS responder started");
 
-    // Start TCP (HTTP) server
-    server.begin();
-    Serial.println("TCP server started");
+  // Start TCP (HTTP) server
+  server.begin();
+  Serial.println("TCP server started");
 
-    // Add service to MDNS-SD
-    MDNS.addService("http", "tcp", 80);
+  // Add service to MDNS-SD
+  MDNS.addService("http", "tcp", 80);
 }
 
-void loop(void)
-{
-    // Check if a client has connected
-    WiFiClient client = server.available();
-    if (!client) {
-        return;
-    }
-    Serial.println("");
-    Serial.println("New client");
-
-    // Wait for data from client to become available
-    while(client.connected() && !client.available()){
-        delay(1);
-    }
-
-    // Read the first line of HTTP request
-    String req = client.readStringUntil('\r');
-
-    // First line of HTTP request looks like "GET /path HTTP/1.1"
-    // Retrieve the "/path" part by finding the spaces
-    int addr_start = req.indexOf(' ');
-    int addr_end = req.indexOf(' ', addr_start + 1);
-    if (addr_start == -1 || addr_end == -1) {
-        Serial.print("Invalid request: ");
-        Serial.println(req);
-        return;
-    }
-    req = req.substring(addr_start + 1, addr_end);
-    Serial.print("Request: ");
+void loop(void) {
+  // Check if a client has connected
+  NetworkClient client = server.accept();
+  if (!client) {
+    return;
+  }
+  Serial.println("");
+  Serial.println("New client");
+
+  // Wait for data from client to become available
+  while (client.connected() && !client.available()) {
+    delay(1);
+  }
+
+  // Read the first line of HTTP request
+  String req = client.readStringUntil('\r');
+
+  // First line of HTTP request looks like "GET /path HTTP/1.1"
+  // Retrieve the "/path" part by finding the spaces
+  int addr_start = req.indexOf(' ');
+  int addr_end = req.indexOf(' ', addr_start + 1);
+  if (addr_start == -1 || addr_end == -1) {
+    Serial.print("Invalid request: ");
     Serial.println(req);
-
-    String s;
-    if (req == "/")
-    {
-        IPAddress ip = WiFi.localIP();
-        String ipStr = String(ip[0]) + '.' + String(ip[1]) + '.' + String(ip[2]) + '.' + String(ip[3]);
-        s = "HTTP/1.1 200 OK\r\nContent-Type: text/html\r\n\r\n<!DOCTYPE HTML>\r\n<html>Hello from ESP32 at ";
-        s += ipStr;
-        s += "</html>\r\n\r\n";
-        Serial.println("Sending 200");
-    }
-    else
-    {
-        s = "HTTP/1.1 404 Not Found\r\n\r\n";
-        Serial.println("Sending 404");
-    }
-    client.print(s);
-
-    client.stop();
-    Serial.println("Done with client");
+    return;
+  }
+  req = req.substring(addr_start + 1, addr_end);
+  Serial.print("Request: ");
+  Serial.println(req);
+
+  String s;
+  if (req == "/") {
+    IPAddress ip = WiFi.localIP();
+    String ipStr = String(ip[0]) + '.' + String(ip[1]) + '.' + String(ip[2]) + '.' + String(ip[3]);
+    s = "HTTP/1.1 200 OK\r\nContent-Type: text/html\r\n\r\n<!DOCTYPE HTML>\r\n<html>Hello from ESP32 at ";
+    s += ipStr;
+    s += "</html>\r\n\r\n";
+    Serial.println("Sending 200");
+  } else {
+    s = "HTTP/1.1 404 Not Found\r\n\r\n";
+    Serial.println("Sending 404");
+  }
+  client.print(s);
+
+  client.stop();
+  Serial.println("Done with client");
 }
-
diff --git a/libraries/ESPmDNS/keywords.txt b/libraries/ESPmDNS/keywords.txt
index c012cb59bd7..10bdb4f9e4f 100644
--- a/libraries/ESPmDNS/keywords.txt
+++ b/libraries/ESPmDNS/keywords.txt
@@ -22,4 +22,3 @@ disableArduino	KEYWORD2
 #######################################
 # Constants (LITERAL1)
 #######################################
-
diff --git a/libraries/ESPmDNS/library.properties b/libraries/ESPmDNS/library.properties
index 4f9561961b9..6d36d61b783 100644
--- a/libraries/ESPmDNS/library.properties
+++ b/libraries/ESPmDNS/library.properties
@@ -1,5 +1,5 @@
 name=ESPmDNS
-version=1.0
+version=3.2.0
 author=Hristo Gochkov, Ivan Grokhtkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=ESP32 mDNS Library
diff --git a/libraries/ESPmDNS/src/ESPmDNS.cpp b/libraries/ESPmDNS/src/ESPmDNS.cpp
index 9a76f623c91..5d422513bbd 100644
--- a/libraries/ESPmDNS/src/ESPmDNS.cpp
+++ b/libraries/ESPmDNS/src/ESPmDNS.cpp
@@ -4,7 +4,7 @@ ESP8266 Multicast DNS (port of CC3000 Multicast DNS library)
 Version 1.1
 Copyright (c) 2013 Tony DiCola (tony@tonydicola.com)
 ESP8266 port (c) 2015 Ivan Grokhotkov (ivan@esp8266.com)
-MDNS-SD Suport 2015 Hristo Gochkov (hristo@espressif.com)
+MDNS-SD Support 2015 Hristo Gochkov (hristo@espressif.com)
 Extended MDNS-SD support 2016 Lars Englund (lars.englund@gmail.com)
 
 
@@ -39,307 +39,367 @@ License (MIT license):
 #endif
 
 #include "ESPmDNS.h"
-#include "WiFi.h"
+#ifdef CONFIG_MDNS_MAX_INTERFACES
 #include <functional>
-#include "esp_wifi.h"
+#include "esp_mac.h"
+#include "soc/soc_caps.h"
 
 // Add quotes around defined value
 #ifdef __IN_ECLIPSE__
 #define STR_EXPAND(tok) #tok
-#define STR(tok) STR_EXPAND(tok)
+#define STR(tok)        STR_EXPAND(tok)
 #else
 #define STR(tok) tok
 #endif
 
-static void _on_sys_event(system_event_t *event){
-    mdns_handle_system_event(NULL, event);
-}
-
-MDNSResponder::MDNSResponder() :results(NULL) {}
+// static void addInterface(NetworkInterface * iface){
+// #if defined(CONFIG_MDNS_ADD_CUSTOM_NETIF) && !defined(CONFIG_MDNS_PREDEF_NETIF_STA) && !defined(CONFIG_MDNS_PREDEF_NETIF_ETH)
+//     /* Demonstration of adding a custom netif to mdns service, but we're adding the default example one,
+//      * so we must disable all predefined interfaces (PREDEF_NETIF_STA, AP and ETH) first
+//      */
+//     ESP_ERROR_CHECK(mdns_register_netif(iface->netif()));
+//     /* It is not enough to just register the interface, we have to enable is manually.
+//      * This is typically performed in "GOT_IP" event handler, but we call it here directly
+//      * since the `EXAMPLE_INTERFACE` netif is connected already, to keep the example simple.
+//      */
+//     ESP_ERROR_CHECK(mdns_netif_action(iface->netif(), MDNS_EVENT_ENABLE_IP4 | MDNS_EVENT_ENABLE_IP6));
+//     ESP_ERROR_CHECK(mdns_netif_action(iface->netif(), MDNS_EVENT_ANNOUNCE_IP4 | MDNS_EVENT_ANNOUNCE_IP6));
+
+// #if defined(CONFIG_MDNS_RESPOND_REVERSE_QUERIES)
+//     ESP_ERROR_CHECK(mdns_netif_action(iface->netif(), MDNS_EVENT_IP4_REVERSE_LOOKUP | MDNS_EVENT_IP6_REVERSE_LOOKUP));
+// #endif
+// #endif // CONFIG_MDNS_ADD_CUSTOM_NETIF
+// }
+
+// static void _on_sys_event(arduino_event_t *event){
+//     mdns_handle_system_event(NULL, event);
+// }
+
+MDNSResponder::MDNSResponder() : results(NULL) {}
 MDNSResponder::~MDNSResponder() {
-    end();
+  end();
 }
 
-bool MDNSResponder::begin(const char* hostName){
-    if(mdns_init()){
-        log_e("Failed starting MDNS");
-        return false;
-    }
-    WiFi.onEvent(_on_sys_event);
-    _hostname = hostName;
-	_hostname.toLowerCase();
-    if(mdns_hostname_set(hostName)) {
-        log_e("Failed setting MDNS hostname");
-        return false;
-    }
-    return true;
+bool MDNSResponder::begin(const String &hostName) {
+  if (mdns_init()) {
+    log_e("Failed starting MDNS");
+    return false;
+  }
+  //WiFi.onEvent(_on_sys_event);
+  _hostname = hostName;
+  _hostname.toLowerCase();
+  if (mdns_hostname_set(hostName.c_str())) {
+    log_e("Failed setting MDNS hostname");
+    return false;
+  }
+  return true;
 }
 
 void MDNSResponder::end() {
-    mdns_free();
+  mdns_free();
 }
 
 void MDNSResponder::setInstanceName(String name) {
-    if (name.length() > 63) return;
-    if(mdns_instance_name_set(name.c_str())){
-        log_e("Failed setting MDNS instance");
-        return;
-    }
+  if (name.length() > 63) {
+    return;
+  }
+  if (mdns_instance_name_set(name.c_str())) {
+    log_e("Failed setting MDNS instance");
+    return;
+  }
 }
 
-
-void MDNSResponder::enableArduino(uint16_t port, bool auth){
-    mdns_txt_item_t arduTxtData[4] = {
-        {(char*)"board"         ,(char*)STR(ARDUINO_VARIANT)},
-        {(char*)"tcp_check"     ,(char*)"no"},
-        {(char*)"ssh_upload"    ,(char*)"no"},
-        {(char*)"auth_upload"   ,(char*)"no"}
-    };
-
-    if(mdns_service_add(NULL, "_arduino", "_tcp", port, arduTxtData, 4)) {
-        log_e("Failed adding Arduino service");
-    }
-
-    if(auth && mdns_service_txt_item_set("_arduino", "_tcp", "auth_upload", "yes")){
-        log_e("Failed setting Arduino txt item");
-    }
+void MDNSResponder::enableArduino(uint16_t port, bool auth) {
+  mdns_txt_item_t arduTxtData[4] = {
+    {(char *)"board", (char *)STR(ARDUINO_VARIANT)},
+    {(char *)"tcp_check", (char *)"no"},
+    {(char *)"ssh_upload", (char *)"no"},
+    {(char *)"auth_upload", (char *)"no"}
+  };
+
+  if (mdns_service_add(NULL, "_arduino", "_tcp", port, arduTxtData, 4)) {
+    log_e("Failed adding Arduino service");
+  }
+
+  if (auth && mdns_service_txt_item_set("_arduino", "_tcp", "auth_upload", "yes")) {
+    log_e("Failed setting Arduino txt item");
+  }
 }
 
-void MDNSResponder::disableArduino(){
-    if(mdns_service_remove("_arduino", "_tcp")) {
-        log_w("Failed removing Arduino service");
-    }
+void MDNSResponder::disableArduino() {
+  if (mdns_service_remove("_arduino", "_tcp")) {
+    log_w("Failed removing Arduino service");
+  }
 }
 
-void MDNSResponder::enableWorkstation(wifi_interface_t interface){
-    char winstance[21+_hostname.length()];
-    uint8_t mac[6];
-    esp_wifi_get_mac(interface, mac);
-    sprintf(winstance, "%s [%02x:%02x:%02x:%02x:%02x:%02x]", _hostname.c_str(), mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-
-    if(mdns_service_add(NULL, "_workstation", "_tcp", 9, NULL, 0)) {
-        log_e("Failed adding Workstation service");
-    } else if(mdns_service_instance_name_set("_workstation", "_tcp", winstance)) {
-        log_e("Failed setting Workstation service instance name");
-    }
+void MDNSResponder::enableWorkstation(esp_interface_t interface) {
+  char winstance[21 + _hostname.length()];
+  uint8_t mac[6];
+
+  esp_mac_type_t mtype = ESP_MAC_ETH;
+#if SOC_WIFI_SUPPORTED
+  switch (interface) {
+    case ESP_IF_WIFI_STA: mtype = ESP_MAC_WIFI_STA; break;
+    case ESP_IF_WIFI_AP:  mtype = ESP_MAC_WIFI_SOFTAP; break;
+    default:              break;
+  }
+#endif
+  if (esp_read_mac(mac, mtype) != ESP_OK) {
+    log_e("Failed to read the MAC address");
+    return;
+  }
+
+  sprintf(winstance, "%s [%02x:%02x:%02x:%02x:%02x:%02x]", _hostname.c_str(), mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+  if (mdns_service_add(NULL, "_workstation", "_tcp", 9, NULL, 0)) {
+    log_e("Failed adding Workstation service");
+  } else if (mdns_service_instance_name_set("_workstation", "_tcp", winstance)) {
+    log_e("Failed setting Workstation service instance name");
+  }
 }
 
-void MDNSResponder::disableWorkstation(){
-    if(mdns_service_remove("_workstation", "_tcp")) {
-        log_w("Failed removing Workstation service");
-    }
+void MDNSResponder::disableWorkstation() {
+  if (mdns_service_remove("_workstation", "_tcp")) {
+    log_w("Failed removing Workstation service");
+  }
 }
 
-bool MDNSResponder::addService(char *name, char *proto, uint16_t port){
-    char _name[strlen(name)+2];
-    char _proto[strlen(proto)+2];
-	if (name[0] == '_') {
-		sprintf(_name, "%s", name);
-	} else {
-		sprintf(_name, "_%s", name);
-	}
-	if (proto[0] == '_') {
-		sprintf(_proto, "%s", proto);
-	} else {
-		sprintf(_proto, "_%s", proto);
-	}
-
-    if(mdns_service_add(NULL, _name, _proto, port, NULL, 0)) {
-        log_e("Failed adding service %s.%s.\n", name, proto);
-	return false;
-    }
-    return true;
+bool MDNSResponder::addService(char *name, char *proto, uint16_t port) {
+  char _name[strlen(name) + 2];
+  char _proto[strlen(proto) + 2];
+  if (name[0] == '_') {
+    sprintf(_name, "%s", name);
+  } else {
+    sprintf(_name, "_%s", name);
+  }
+  if (proto[0] == '_') {
+    sprintf(_proto, "%s", proto);
+  } else {
+    sprintf(_proto, "_%s", proto);
+  }
+
+  if (mdns_service_add(NULL, _name, _proto, port, NULL, 0)) {
+    log_e("Failed adding service %s.%s.\n", name, proto);
+    return false;
+  }
+  return true;
 }
 
-bool MDNSResponder::addServiceTxt(char *name, char *proto, char *key, char *value){
-    char _name[strlen(name)+2];
-    char _proto[strlen(proto)+2];
-	if (name[0] == '_') {
-		sprintf(_name, "%s", name);
-	} else {
-		sprintf(_name, "_%s", name);
-	}
-	if (proto[0] == '_') {
-		sprintf(_proto, "%s", proto);
-	} else {
-		sprintf(_proto, "_%s", proto);
-	}
-
-    if(mdns_service_txt_item_set(_name, _proto, key, value)) {
-        log_e("Failed setting service TXT");
-        return false;
-    }
-    return true;
+bool MDNSResponder::addServiceTxt(char *name, char *proto, char *key, char *value) {
+  char _name[strlen(name) + 2];
+  char _proto[strlen(proto) + 2];
+  if (name[0] == '_') {
+    sprintf(_name, "%s", name);
+  } else {
+    sprintf(_name, "_%s", name);
+  }
+  if (proto[0] == '_') {
+    sprintf(_proto, "%s", proto);
+  } else {
+    sprintf(_proto, "_%s", proto);
+  }
+
+  if (mdns_service_txt_item_set(_name, _proto, key, value)) {
+    log_e("Failed setting service TXT");
+    return false;
+  }
+  return true;
 }
 
-IPAddress MDNSResponder::queryHost(char *host, uint32_t timeout){
-    struct ip4_addr addr;
-    addr.addr = 0;
-
-    esp_err_t err = mdns_query_a(host, timeout,  &addr);
-    if(err){
-        if(err == ESP_ERR_NOT_FOUND){
-            log_w("Host was not found!");
-            return IPAddress();
-        }
-        log_e("Query Failed");
-        return IPAddress();
+IPAddress MDNSResponder::queryHost(char *host, uint32_t timeout) {
+  esp_ip4_addr_t addr;
+  addr.addr = 0;
+
+  esp_err_t err = mdns_query_a(host, timeout, &addr);
+  if (err) {
+    if (err == ESP_ERR_NOT_FOUND) {
+      log_w("Host was not found!");
+      return IPAddress();
     }
-    return IPAddress(addr.addr);
+    log_e("Query Failed");
+    return IPAddress();
+  }
+  return IPAddress(addr.addr);
 }
 
-
 int MDNSResponder::queryService(char *service, char *proto) {
-    if(!service || !service[0] || !proto || !proto[0]){
-        log_e("Bad Parameters");
-        return 0;
-    }
-
-    if(results){
-        mdns_query_results_free(results);
-        results = NULL;
-    }
-
-    char srv[strlen(service)+2];
-    char prt[strlen(proto)+2];
-	if (service[0] == '_') {
-		sprintf(srv, "%s", service);
-	} else {
-		sprintf(srv, "_%s", service);
-	}
-	if (proto[0] == '_') {
-		sprintf(prt, "%s", proto);
-	} else {
-		sprintf(prt, "_%s", proto);
-	}
-
-    esp_err_t err = mdns_query_ptr(srv, prt, 3000, 20,  &results);
-    if(err){
-        log_e("Query Failed");
-        return 0;
-    }
-    if(!results){
-        log_w("No results found!");
-        return 0;
-    }
+  if (!service || !service[0] || !proto || !proto[0]) {
+    log_e("Bad Parameters");
+    return 0;
+  }
+
+  if (results) {
+    mdns_query_results_free(results);
+    results = NULL;
+  }
+
+  char srv[strlen(service) + 2];
+  char prt[strlen(proto) + 2];
+  if (service[0] == '_') {
+    sprintf(srv, "%s", service);
+  } else {
+    sprintf(srv, "_%s", service);
+  }
+  if (proto[0] == '_') {
+    sprintf(prt, "%s", proto);
+  } else {
+    sprintf(prt, "_%s", proto);
+  }
+
+  esp_err_t err = mdns_query_ptr(srv, prt, 3000, 20, &results);
+  if (err) {
+    log_e("Query Failed");
+    return 0;
+  }
+  if (!results) {
+    log_w("No results found!");
+    return 0;
+  }
+
+  mdns_result_t *r = results;
+  int i = 0;
+  while (r) {
+    i++;
+    r = r->next;
+  }
+  return i;
+}
 
-    mdns_result_t * r = results;
-    int i = 0;
-    while(r){
-        i++;
-        r = r->next;
+mdns_result_t *MDNSResponder::_getResult(int idx) {
+  mdns_result_t *result = results;
+  int i = 0;
+  while (result) {
+    if (i == idx) {
+      break;
     }
-    return i;
+    i++;
+    result = result->next;
+  }
+  return result;
 }
 
-mdns_result_t * MDNSResponder::_getResult(int idx){
-    mdns_result_t * result = results;
-    int i = 0;
-    while(result){
-        if(i == idx){
-            break;
-        }
-        i++;
-        result = result->next;
-    }
-    return result;
+mdns_txt_item_t *MDNSResponder::_getResultTxt(int idx, int txtIdx) {
+  mdns_result_t *result = _getResult(idx);
+  if (!result) {
+    log_e("Result %d not found", idx);
+    return NULL;
+  }
+  if (txtIdx >= result->txt_count) {
+    return NULL;
+  }
+  return &result->txt[txtIdx];
 }
 
 String MDNSResponder::hostname(int idx) {
-    mdns_result_t * result = _getResult(idx);
-    if(!result){
-        log_e("Result %d not found", idx);
-        return String();
-    }
-    return String(result->hostname);
+  mdns_result_t *result = _getResult(idx);
+  if (!result) {
+    log_e("Result %d not found", idx);
+    return String();
+  }
+  return String(result->hostname);
 }
 
-IPAddress MDNSResponder::IP(int idx) {
-    mdns_result_t * result = _getResult(idx);
-    if(!result){
-        log_e("Result %d not found", idx);
-        return IPAddress();
-    }
-    mdns_ip_addr_t * addr = result->addr;
-    while(addr){
-        if(addr->addr.type == MDNS_IP_PROTOCOL_V4){
-            return IPAddress(addr->addr.u_addr.ip4.addr);
-        }
-        addr = addr->next;
-    }
-    return IPAddress();
+String MDNSResponder::instanceName(int idx) {
+  mdns_result_t *result = _getResult(idx);
+  if (!result) {
+    log_e("Result %d not found", idx);
+    return String();
+  }
+  return String(result->instance_name);
 }
 
-IPv6Address MDNSResponder::IPv6(int idx) {
-    mdns_result_t * result = _getResult(idx);
-    if(!result){
-        log_e("Result %d not found", idx);
-        return IPv6Address();
+IPAddress MDNSResponder::address(int idx) {
+  mdns_result_t *result = _getResult(idx);
+  if (!result) {
+    log_e("Result %d not found", idx);
+    return IPAddress();
+  }
+  mdns_ip_addr_t *addr = result->addr;
+  while (addr) {
+    if (addr->addr.type == MDNS_IP_PROTOCOL_V4) {
+      return IPAddress(addr->addr.u_addr.ip4.addr);
     }
-    mdns_ip_addr_t * addr = result->addr;
-    while(addr){
-        if(addr->addr.type == MDNS_IP_PROTOCOL_V6){
-            return IPv6Address(addr->addr.u_addr.ip6.addr);
-        }
-        addr = addr->next;
+    addr = addr->next;
+  }
+  return IPAddress();
+}
+
+IPAddress MDNSResponder::addressV6(int idx) {
+  mdns_result_t *result = _getResult(idx);
+  if (!result) {
+    log_e("Result %d not found", idx);
+    return IPAddress(IPv6);
+  }
+  mdns_ip_addr_t *addr = result->addr;
+  while (addr) {
+    if (addr->addr.type == MDNS_IP_PROTOCOL_V6) {
+      return IPAddress(IPv6, (const uint8_t *)addr->addr.u_addr.ip6.addr, addr->addr.u_addr.ip6.zone);
     }
-    return IPv6Address();
+    addr = addr->next;
+  }
+  return IPAddress(IPv6);
 }
 
 uint16_t MDNSResponder::port(int idx) {
-    mdns_result_t * result = _getResult(idx);
-    if(!result){
-        log_e("Result %d not found", idx);
-        return 0;
-    }
-    return result->port;
+  mdns_result_t *result = _getResult(idx);
+  if (!result) {
+    log_e("Result %d not found", idx);
+    return 0;
+  }
+  return result->port;
 }
 
 int MDNSResponder::numTxt(int idx) {
-    mdns_result_t * result = _getResult(idx);
-    if(!result){
-        log_e("Result %d not found", idx);
-        return 0;
-    }
-    return result->txt_count;
+  mdns_result_t *result = _getResult(idx);
+  if (!result) {
+    log_e("Result %d not found", idx);
+    return 0;
+  }
+  return result->txt_count;
 }
 
-bool MDNSResponder::hasTxt(int idx, const char * key) {
-    mdns_result_t * result = _getResult(idx);
-    if(!result){
-        log_e("Result %d not found", idx);
-        return false;
-    }
-    int i = 0;
-    while(i < result->txt_count) {
-        if (strcmp(result->txt[i].key, key) == 0) return true;
-        i++;
-    }
+bool MDNSResponder::hasTxt(int idx, const char *key) {
+  mdns_result_t *result = _getResult(idx);
+  if (!result) {
+    log_e("Result %d not found", idx);
     return false;
+  }
+  int i = 0;
+  while (i < result->txt_count) {
+    if (strcmp(result->txt[i].key, key) == 0) {
+      return true;
+    }
+    i++;
+  }
+  return false;
 }
 
-String MDNSResponder::txt(int idx, const char * key) {
-    mdns_result_t * result = _getResult(idx);
-    if(!result){
-        log_e("Result %d not found", idx);
-        return "";
-    }
-    int i = 0;
-    while(i < result->txt_count) {
-        if (strcmp(result->txt[i].key, key) == 0) return result->txt[i].value;
-        i++;
-    }
+String MDNSResponder::txt(int idx, const char *key) {
+  mdns_result_t *result = _getResult(idx);
+  if (!result) {
+    log_e("Result %d not found", idx);
     return "";
+  }
+  int i = 0;
+  while (i < result->txt_count) {
+    if (strcmp(result->txt[i].key, key) == 0) {
+      return result->txt[i].value;
+    }
+    i++;
+  }
+  return "";
 }
 
 String MDNSResponder::txt(int idx, int txtIdx) {
-    mdns_result_t * result = _getResult(idx);
-    if(!result){
-        log_e("Result %d not found", idx);
-        return "";
-    }
-    if (txtIdx >= result->txt_count) return "";
-    return result->txt[txtIdx].value;
+  mdns_txt_item_t *resultTxt = _getResultTxt(idx, txtIdx);
+  return !resultTxt ? "" : resultTxt->value;
+}
+
+String MDNSResponder::txtKey(int idx, int txtIdx) {
+  mdns_txt_item_t *resultTxt = _getResultTxt(idx, txtIdx);
+  return !resultTxt ? "" : resultTxt->key;
 }
 
 MDNSResponder MDNS;
+
+#endif /* CONFIG_MDNS_MAX_INTERFACES */
diff --git a/libraries/ESPmDNS/src/ESPmDNS.h b/libraries/ESPmDNS/src/ESPmDNS.h
index 8f56ea42fde..1fb90bbf454 100644
--- a/libraries/ESPmDNS/src/ESPmDNS.h
+++ b/libraries/ESPmDNS/src/ESPmDNS.h
@@ -3,12 +3,12 @@ ESP8266 Multicast DNS (port of CC3000 Multicast DNS library)
 Version 1.1
 Copyright (c) 2013 Tony DiCola (tony@tonydicola.com)
 ESP8266 port (c) 2015 Ivan Grokhotkov (ivan@esp8266.com)
-MDNS-SD Suport 2015 Hristo Gochkov (hristo@espressif.com)
+MDNS-SD Support 2015 Hristo Gochkov (hristo@espressif.com)
 Extended MDNS-SD support 2016 Lars Englund (lars.englund@gmail.com)
 Rewritten for ESP32 by Hristo Gochkov (hristo@espressif.com)
 
 This is a simple implementation of multicast DNS query support for an Arduino
-running on ESP32 chip. 
+running on ESP32 chip.
 
 Usage:
 - Include the ESP32 Multicast DNS library in the sketch.
@@ -41,9 +41,12 @@ License (MIT license):
 #ifndef ESP32MDNS_H
 #define ESP32MDNS_H
 
+#include "sdkconfig.h"
+#ifdef CONFIG_MDNS_MAX_INTERFACES
+
 #include "Arduino.h"
-#include "IPv6Address.h"
 #include "mdns.h"
+#include "esp_interface.h"
 
 //this should be defined at build time
 #ifndef ARDUINO_VARIANT
@@ -54,70 +57,77 @@ class MDNSResponder {
 public:
   MDNSResponder();
   ~MDNSResponder();
-  bool begin(const char* hostName);
+  bool begin(const String &hostName);
+  bool begin(const char *hostName) {
+    return begin(String(hostName));
+  }
   void end();
 
   void setInstanceName(String name);
-  void setInstanceName(const char * name){
+  void setInstanceName(const char *name) {
     setInstanceName(String(name));
   }
-  void setInstanceName(char * name){
+  void setInstanceName(char *name) {
     setInstanceName(String(name));
   }
 
   bool addService(char *service, char *proto, uint16_t port);
-  bool addService(const char *service, const char *proto, uint16_t port){
+  bool addService(const char *service, const char *proto, uint16_t port) {
     return addService((char *)service, (char *)proto, port);
   }
-  bool addService(String service, String proto, uint16_t port){
+  bool addService(String service, String proto, uint16_t port) {
     return addService(service.c_str(), proto.c_str(), port);
   }
-  
-  bool addServiceTxt(char *name, char *proto, char * key, char * value);
-  void addServiceTxt(const char *name, const char *proto, const char *key,const char * value){
+
+  bool addServiceTxt(char *name, char *proto, char *key, char *value);
+  void addServiceTxt(const char *name, const char *proto, const char *key, const char *value) {
     addServiceTxt((char *)name, (char *)proto, (char *)key, (char *)value);
   }
-  void addServiceTxt(String name, String proto, String key, String value){
+  void addServiceTxt(String name, String proto, String key, String value) {
     addServiceTxt(name.c_str(), proto.c_str(), key.c_str(), value.c_str());
   }
 
-  void enableArduino(uint16_t port=3232, bool auth=false);
+  void enableArduino(uint16_t port = 3232, bool auth = false);
   void disableArduino();
 
-  void enableWorkstation(wifi_interface_t interface=ESP_IF_WIFI_STA);
+  void enableWorkstation(esp_interface_t interface = ESP_IF_WIFI_STA);
   void disableWorkstation();
 
-  IPAddress queryHost(char *host, uint32_t timeout=2000);
-  IPAddress queryHost(const char *host, uint32_t timeout=2000){
+  IPAddress queryHost(char *host, uint32_t timeout = 2000);
+  IPAddress queryHost(const char *host, uint32_t timeout = 2000) {
     return queryHost((char *)host, timeout);
   }
-  IPAddress queryHost(String host, uint32_t timeout=2000){
+  IPAddress queryHost(String host, uint32_t timeout = 2000) {
     return queryHost(host.c_str(), timeout);
   }
-  
+
   int queryService(char *service, char *proto);
-  int queryService(const char *service, const char *proto){
+  int queryService(const char *service, const char *proto) {
     return queryService((char *)service, (char *)proto);
   }
-  int queryService(String service, String proto){
+  int queryService(String service, String proto) {
     return queryService(service.c_str(), proto.c_str());
   }
 
   String hostname(int idx);
-  IPAddress IP(int idx);
-  IPv6Address IPv6(int idx);
+  String instanceName(int idx);
+  IPAddress address(int idx);
+  IPAddress addressV6(int idx);
   uint16_t port(int idx);
   int numTxt(int idx);
-  bool hasTxt(int idx, const char * key);
-  String txt(int idx, const char * key);
+  bool hasTxt(int idx, const char *key);
+  String txt(int idx, const char *key);
   String txt(int idx, int txtIdx);
-  
+  String txtKey(int idx, int txtIdx);
+
 private:
   String _hostname;
-  mdns_result_t * results;
-  mdns_result_t * _getResult(int idx);
+  mdns_result_t *results;
+  mdns_result_t *_getResult(int idx);
+  mdns_txt_item_t *_getResultTxt(int idx, int txtIdx);
 };
 
 extern MDNSResponder MDNS;
 
-#endif //ESP32MDNS_H
+#endif  /* CONFIG_MDNS_MAX_INTERFACES */
+#endif  //ESP32MDNS_H
diff --git a/libraries/Ethernet/examples/ETH_LAN8720/ETH_LAN8720.ino b/libraries/Ethernet/examples/ETH_LAN8720/ETH_LAN8720.ino
new file mode 100644
index 00000000000..59a32750bf6
--- /dev/null
+++ b/libraries/Ethernet/examples/ETH_LAN8720/ETH_LAN8720.ino
@@ -0,0 +1,90 @@
+/*
+    This sketch shows the Ethernet event usage
+
+*/
+
+// Important to be defined BEFORE including ETH.h for ETH.begin() to work.
+// Example RMII LAN8720 (Olimex, etc.)
+#ifndef ETH_PHY_MDC
+#define ETH_PHY_TYPE ETH_PHY_LAN8720
+#if CONFIG_IDF_TARGET_ESP32
+#define ETH_PHY_ADDR  0
+#define ETH_PHY_MDC   23
+#define ETH_PHY_MDIO  18
+#define ETH_PHY_POWER -1
+#define ETH_CLK_MODE  ETH_CLOCK_GPIO0_IN
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define ETH_PHY_ADDR  0
+#define ETH_PHY_MDC   31
+#define ETH_PHY_MDIO  52
+#define ETH_PHY_POWER 51
+#define ETH_CLK_MODE  EMAC_CLK_EXT_IN
+#endif
+#endif
+
+#include <ETH.h>
+
+static bool eth_connected = false;
+
+// WARNING: onEvent is called from a separate FreeRTOS task (thread)!
+void onEvent(arduino_event_id_t event) {
+  switch (event) {
+    case ARDUINO_EVENT_ETH_START:
+      Serial.println("ETH Started");
+      // The hostname must be set after the interface is started, but needs
+      // to be set before DHCP, so set it from the event handler thread.
+      ETH.setHostname("esp32-ethernet");
+      break;
+    case ARDUINO_EVENT_ETH_CONNECTED: Serial.println("ETH Connected"); break;
+    case ARDUINO_EVENT_ETH_GOT_IP:
+      Serial.println("ETH Got IP");
+      Serial.println(ETH);
+      eth_connected = true;
+      break;
+    case ARDUINO_EVENT_ETH_LOST_IP:
+      Serial.println("ETH Lost IP");
+      eth_connected = false;
+      break;
+    case ARDUINO_EVENT_ETH_DISCONNECTED:
+      Serial.println("ETH Disconnected");
+      eth_connected = false;
+      break;
+    case ARDUINO_EVENT_ETH_STOP:
+      Serial.println("ETH Stopped");
+      eth_connected = false;
+      break;
+    default: break;
+  }
+}
+
+void testClient(const char *host, uint16_t port) {
+  Serial.print("\nconnecting to ");
+  Serial.println(host);
+
+  NetworkClient client;
+  if (!client.connect(host, port)) {
+    Serial.println("connection failed");
+    return;
+  }
+  client.printf("GET / HTTP/1.1\r\nHost: %s\r\n\r\n", host);
+  while (client.connected() && !client.available());
+  while (client.available()) {
+    Serial.write(client.read());
+  }
+
+  Serial.println("closing connection\n");
+  client.stop();
+}
+
+void setup() {
+  Serial.begin(115200);
+  Network.onEvent(onEvent);
+  ETH.begin();
+}
+
+void loop() {
+  if (eth_connected) {
+    testClient("google.com", 80);
+  }
+  delay(10000);
+}
diff --git a/libraries/Ethernet/examples/ETH_LAN8720/ci.json b/libraries/Ethernet/examples/ETH_LAN8720/ci.json
new file mode 100644
index 00000000000..0eab13b8841
--- /dev/null
+++ b/libraries/Ethernet/examples/ETH_LAN8720/ci.json
@@ -0,0 +1,8 @@
+{
+  "requires": [
+    "CONFIG_ETH_USE_ESP32_EMAC=y"
+  ],
+  "targets": {
+    "esp32p4": false
+  }
+}
diff --git a/libraries/Ethernet/examples/ETH_TLK110/ETH_TLK110.ino b/libraries/Ethernet/examples/ETH_TLK110/ETH_TLK110.ino
new file mode 100644
index 00000000000..242281c3997
--- /dev/null
+++ b/libraries/Ethernet/examples/ETH_TLK110/ETH_TLK110.ino
@@ -0,0 +1,88 @@
+/*
+    This sketch shows the Ethernet event usage
+
+*/
+
+#include <ETH.h>
+
+#ifndef ETH_PHY_MDC
+#define ETH_PHY_TYPE ETH_PHY_TLK110
+#if CONFIG_IDF_TARGET_ESP32
+#define ETH_PHY_ADDR  31
+#define ETH_PHY_MDC   23
+#define ETH_PHY_MDIO  18
+#define ETH_PHY_POWER 17
+#define ETH_CLK_MODE  ETH_CLOCK_GPIO0_IN
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define ETH_PHY_ADDR  1
+#define ETH_PHY_MDC   31
+#define ETH_PHY_MDIO  52
+#define ETH_PHY_POWER 51
+#define ETH_CLK_MODE  EMAC_CLK_EXT_IN
+#endif
+#endif
+
+static bool eth_connected = false;
+
+// WARNING: onEvent is called from a separate FreeRTOS task (thread)!
+void onEvent(arduino_event_id_t event) {
+  switch (event) {
+    case ARDUINO_EVENT_ETH_START:
+      Serial.println("ETH Started");
+      // The hostname must be set after the interface is started, but needs
+      // to be set before DHCP, so set it from the event handler thread.
+      ETH.setHostname("esp32-ethernet");
+      break;
+    case ARDUINO_EVENT_ETH_CONNECTED: Serial.println("ETH Connected"); break;
+    case ARDUINO_EVENT_ETH_GOT_IP:
+      Serial.println("ETH Got IP");
+      Serial.println(ETH);
+      eth_connected = true;
+      break;
+    case ARDUINO_EVENT_ETH_LOST_IP:
+      Serial.println("ETH Lost IP");
+      eth_connected = false;
+      break;
+    case ARDUINO_EVENT_ETH_DISCONNECTED:
+      Serial.println("ETH Disconnected");
+      eth_connected = false;
+      break;
+    case ARDUINO_EVENT_ETH_STOP:
+      Serial.println("ETH Stopped");
+      eth_connected = false;
+      break;
+    default: break;
+  }
+}
+
+void testClient(const char *host, uint16_t port) {
+  Serial.print("\nconnecting to ");
+  Serial.println(host);
+
+  NetworkClient client;
+  if (!client.connect(host, port)) {
+    Serial.println("connection failed");
+    return;
+  }
+  client.printf("GET / HTTP/1.1\r\nHost: %s\r\n\r\n", host);
+  while (client.connected() && !client.available());
+  while (client.available()) {
+    Serial.write(client.read());
+  }
+
+  Serial.println("closing connection\n");
+  client.stop();
+}
+
+void setup() {
+  Serial.begin(115200);
+  Network.onEvent(onEvent);  // Will call onEvent() from another thread.
+  ETH.begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_MDC, ETH_PHY_MDIO, ETH_PHY_POWER, ETH_CLK_MODE);
+}
+
+void loop() {
+  if (eth_connected) {
+    testClient("google.com", 80);
+  }
+  delay(10000);
+}
diff --git a/libraries/Ethernet/examples/ETH_TLK110/ci.json b/libraries/Ethernet/examples/ETH_TLK110/ci.json
new file mode 100644
index 00000000000..dcdfd06db51
--- /dev/null
+++ b/libraries/Ethernet/examples/ETH_TLK110/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_ETH_USE_ESP32_EMAC=y"
+  ]
+}
diff --git a/libraries/Ethernet/examples/ETH_W5500_Arduino_SPI/ETH_W5500_Arduino_SPI.ino b/libraries/Ethernet/examples/ETH_W5500_Arduino_SPI/ETH_W5500_Arduino_SPI.ino
new file mode 100644
index 00000000000..d5d57333a55
--- /dev/null
+++ b/libraries/Ethernet/examples/ETH_W5500_Arduino_SPI/ETH_W5500_Arduino_SPI.ino
@@ -0,0 +1,104 @@
+/*
+    This sketch shows the Ethernet event usage
+
+*/
+
+#include <ETH.h>
+#include <SPI.h>
+
+// Set this to 1 to enable dual Ethernet support
+#define USE_TWO_ETH_PORTS 0
+
+#ifndef ETH_PHY_CS
+#define ETH_PHY_TYPE ETH_PHY_W5500
+#define ETH_PHY_ADDR 1
+#define ETH_PHY_CS   15
+#define ETH_PHY_IRQ  4
+#define ETH_PHY_RST  5
+#endif
+
+// SPI pins
+#define ETH_SPI_SCK  14
+#define ETH_SPI_MISO 12
+#define ETH_SPI_MOSI 13
+
+#if USE_TWO_ETH_PORTS
+// Second port on shared SPI bus
+#ifndef ETH1_PHY_CS
+#define ETH1_PHY_TYPE ETH_PHY_W5500
+#define ETH1_PHY_ADDR 1
+#define ETH1_PHY_CS   32
+#define ETH1_PHY_IRQ  33
+#define ETH1_PHY_RST  18
+#endif
+ETHClass ETH1(1);
+#endif
+
+static bool eth_connected = false;
+
+void onEvent(arduino_event_id_t event, arduino_event_info_t info) {
+  switch (event) {
+    case ARDUINO_EVENT_ETH_START:
+      Serial.println("ETH Started");
+      //set eth hostname here
+      ETH.setHostname("esp32-eth0");
+      break;
+    case ARDUINO_EVENT_ETH_CONNECTED: Serial.println("ETH Connected"); break;
+    case ARDUINO_EVENT_ETH_GOT_IP:    Serial.printf("ETH Got IP: '%s'\n", esp_netif_get_desc(info.got_ip.esp_netif)); Serial.println(ETH);
+#if USE_TWO_ETH_PORTS
+      Serial.println(ETH1);
+#endif
+      eth_connected = true;
+      break;
+    case ARDUINO_EVENT_ETH_LOST_IP:
+      Serial.println("ETH Lost IP");
+      eth_connected = false;
+      break;
+    case ARDUINO_EVENT_ETH_DISCONNECTED:
+      Serial.println("ETH Disconnected");
+      eth_connected = false;
+      break;
+    case ARDUINO_EVENT_ETH_STOP:
+      Serial.println("ETH Stopped");
+      eth_connected = false;
+      break;
+    default: break;
+  }
+}
+
+void testClient(const char *host, uint16_t port) {
+  Serial.print("\nconnecting to ");
+  Serial.println(host);
+
+  NetworkClient client;
+  if (!client.connect(host, port)) {
+    Serial.println("connection failed");
+    return;
+  }
+  client.printf("GET / HTTP/1.1\r\nHost: %s\r\n\r\n", host);
+  while (client.connected() && !client.available());
+  while (client.available()) {
+    Serial.write(client.read());
+  }
+
+  Serial.println("closing connection\n");
+  client.stop();
+}
+
+void setup() {
+  Serial.begin(115200);
+  Network.onEvent(onEvent);
+
+  SPI.begin(ETH_SPI_SCK, ETH_SPI_MISO, ETH_SPI_MOSI);
+  ETH.begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_CS, ETH_PHY_IRQ, ETH_PHY_RST, SPI);
+#if USE_TWO_ETH_PORTS
+  ETH1.begin(ETH1_PHY_TYPE, ETH1_PHY_ADDR, ETH1_PHY_CS, ETH1_PHY_IRQ, ETH1_PHY_RST, SPI);
+#endif
+}
+
+void loop() {
+  if (eth_connected) {
+    testClient("google.com", 80);
+  }
+  delay(10000);
+}
diff --git a/libraries/Ethernet/examples/ETH_W5500_IDF_SPI/ETH_W5500_IDF_SPI.ino b/libraries/Ethernet/examples/ETH_W5500_IDF_SPI/ETH_W5500_IDF_SPI.ino
new file mode 100644
index 00000000000..dad54a745b7
--- /dev/null
+++ b/libraries/Ethernet/examples/ETH_W5500_IDF_SPI/ETH_W5500_IDF_SPI.ino
@@ -0,0 +1,101 @@
+/*
+    This sketch shows the Ethernet event usage
+
+*/
+
+#include <ETH.h>
+
+// Set this to 1 to enable dual Ethernet support
+#define USE_TWO_ETH_PORTS 0
+
+#ifndef ETH_PHY_CS
+#define ETH_PHY_TYPE     ETH_PHY_W5500
+#define ETH_PHY_ADDR     1
+#define ETH_PHY_CS       15
+#define ETH_PHY_IRQ      4
+#define ETH_PHY_RST      5
+#define ETH_PHY_SPI_HOST SPI2_HOST
+#define ETH_PHY_SPI_SCK  14
+#define ETH_PHY_SPI_MISO 12
+#define ETH_PHY_SPI_MOSI 13
+#endif
+
+#if USE_TWO_ETH_PORTS
+// Second port on shared SPI bus
+#ifndef ETH1_PHY_CS
+#define ETH1_PHY_TYPE ETH_PHY_W5500
+#define ETH1_PHY_ADDR 1
+#define ETH1_PHY_CS   32
+#define ETH1_PHY_IRQ  33
+#define ETH1_PHY_RST  18
+#endif
+ETHClass ETH1(1);
+#endif
+
+static bool eth_connected = false;
+
+void onEvent(arduino_event_id_t event, arduino_event_info_t info) {
+  switch (event) {
+    case ARDUINO_EVENT_ETH_START:
+      Serial.println("ETH Started");
+      //set eth hostname here
+      ETH.setHostname("esp32-eth0");
+      break;
+    case ARDUINO_EVENT_ETH_CONNECTED: Serial.println("ETH Connected"); break;
+    case ARDUINO_EVENT_ETH_GOT_IP:    Serial.printf("ETH Got IP: '%s'\n", esp_netif_get_desc(info.got_ip.esp_netif)); Serial.println(ETH);
+#if USE_TWO_ETH_PORTS
+      Serial.println(ETH1);
+#endif
+      eth_connected = true;
+      break;
+    case ARDUINO_EVENT_ETH_LOST_IP:
+      Serial.println("ETH Lost IP");
+      eth_connected = false;
+      break;
+    case ARDUINO_EVENT_ETH_DISCONNECTED:
+      Serial.println("ETH Disconnected");
+      eth_connected = false;
+      break;
+    case ARDUINO_EVENT_ETH_STOP:
+      Serial.println("ETH Stopped");
+      eth_connected = false;
+      break;
+    default: break;
+  }
+}
+
+void testClient(const char *host, uint16_t port) {
+  Serial.print("\nconnecting to ");
+  Serial.println(host);
+
+  NetworkClient client;
+  if (!client.connect(host, port)) {
+    Serial.println("connection failed");
+    return;
+  }
+  client.printf("GET / HTTP/1.1\r\nHost: %s\r\n\r\n", host);
+  while (client.connected() && !client.available());
+  while (client.available()) {
+    Serial.write(client.read());
+  }
+
+  Serial.println("closing connection\n");
+  client.stop();
+}
+
+void setup() {
+  Serial.begin(115200);
+  Network.onEvent(onEvent);
+  ETH.begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_CS, ETH_PHY_IRQ, ETH_PHY_RST, ETH_PHY_SPI_HOST, ETH_PHY_SPI_SCK, ETH_PHY_SPI_MISO, ETH_PHY_SPI_MOSI);
+#if USE_TWO_ETH_PORTS
+  // Since SPI bus is shared, we should skip the SPI pins when calling ETH1.begin()
+  ETH1.begin(ETH1_PHY_TYPE, ETH1_PHY_ADDR, ETH1_PHY_CS, ETH1_PHY_IRQ, ETH1_PHY_RST, ETH_PHY_SPI_HOST);
+#endif
+}
+
+void loop() {
+  if (eth_connected) {
+    testClient("google.com", 80);
+  }
+  delay(10000);
+}
diff --git a/libraries/Ethernet/examples/ETH_WIFI_BRIDGE/ETH_WIFI_BRIDGE.ino b/libraries/Ethernet/examples/ETH_WIFI_BRIDGE/ETH_WIFI_BRIDGE.ino
new file mode 100644
index 00000000000..ba89d5de607
--- /dev/null
+++ b/libraries/Ethernet/examples/ETH_WIFI_BRIDGE/ETH_WIFI_BRIDGE.ino
@@ -0,0 +1,78 @@
+#include <WiFi.h>
+#include <ETH.h>
+#include <SPI.h>
+
+#define ETH_TYPE     ETH_PHY_W5500
+#define ETH_ADDR     1
+#define ETH_CS       15
+#define ETH_IRQ      4
+#define ETH_RST      5
+#define ETH_SPI_SCK  14
+#define ETH_SPI_MISO 12
+#define ETH_SPI_MOSI 13
+
+#define AP_SSID "ESP32-ETH-WIFI-BRIDGE"
+#define AP_PASS "password"
+
+IPAddress ap_ip(192, 168, 4, 1);
+IPAddress ap_mask(255, 255, 255, 0);
+IPAddress ap_leaseStart(192, 168, 4, 2);
+IPAddress ap_dns(8, 8, 4, 4);
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+  Network.onEvent(onEvent);
+
+  WiFi.AP.begin();
+  WiFi.AP.config(ap_ip, ap_ip, ap_mask, ap_leaseStart, ap_dns);
+  WiFi.AP.create(AP_SSID, AP_PASS);
+  if (!WiFi.AP.waitStatusBits(ESP_NETIF_STARTED_BIT, 1000)) {
+    Serial.println("Failed to start AP!");
+    return;
+  }
+  delay(100);
+
+  SPI.begin(ETH_SPI_SCK, ETH_SPI_MISO, ETH_SPI_MOSI);
+  ETH.begin(ETH_TYPE, ETH_ADDR, ETH_CS, ETH_IRQ, ETH_RST, SPI);
+}
+
+void loop() {
+  delay(20000);
+}
+
+void onEvent(arduino_event_id_t event, arduino_event_info_t info) {
+  switch (event) {
+    case ARDUINO_EVENT_ETH_START:     Serial.println("ETH Started"); break;
+    case ARDUINO_EVENT_ETH_CONNECTED: Serial.println("ETH Connected"); break;
+    case ARDUINO_EVENT_ETH_GOT_IP:
+      Serial.println("ETH Got IP");
+      Serial.println(ETH);
+      WiFi.AP.enableNAPT(true);
+      break;
+    case ARDUINO_EVENT_ETH_LOST_IP:
+      Serial.println("ETH Lost IP");
+      WiFi.AP.enableNAPT(false);
+      break;
+    case ARDUINO_EVENT_ETH_DISCONNECTED:
+      Serial.println("ETH Disconnected");
+      WiFi.AP.enableNAPT(false);
+      break;
+    case ARDUINO_EVENT_ETH_STOP: Serial.println("ETH Stopped"); break;
+
+    case ARDUINO_EVENT_WIFI_AP_START:
+      Serial.println("AP Started");
+      Serial.println(WiFi.AP);
+      break;
+    case ARDUINO_EVENT_WIFI_AP_STACONNECTED:    Serial.println("AP STA Connected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STADISCONNECTED: Serial.println("AP STA Disconnected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED:
+      Serial.print("AP STA IP Assigned: ");
+      Serial.println(IPAddress(info.wifi_ap_staipassigned.ip.addr));
+      break;
+    case ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED: Serial.println("AP Probe Request Received"); break;
+    case ARDUINO_EVENT_WIFI_AP_STOP:           Serial.println("AP Stopped"); break;
+
+    default: break;
+  }
+}
diff --git a/libraries/Ethernet/examples/ETH_WIFI_BRIDGE/ci.json b/libraries/Ethernet/examples/ETH_WIFI_BRIDGE/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/Ethernet/examples/ETH_WIFI_BRIDGE/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/Ethernet/library.properties b/libraries/Ethernet/library.properties
new file mode 100644
index 00000000000..d34ae036417
--- /dev/null
+++ b/libraries/Ethernet/library.properties
@@ -0,0 +1,9 @@
+name=Ethernet
+version=3.2.0
+author=Hristo Gochkov
+maintainer=Hristo Gochkov <hristo@espressif.com>
+sentence=Enables network connection (local and Internet) using the ESP32 Ethernet.
+paragraph=With this library you can instantiate Servers, Clients and send/receive UDP packets through Ethernet. The IP address can be assigned statically or through a DHCP. The library can also manage DNS.
+category=Communication
+url=
+architectures=esp32
diff --git a/libraries/Ethernet/src/ETH.cpp b/libraries/Ethernet/src/ETH.cpp
new file mode 100644
index 00000000000..3dfba37c684
--- /dev/null
+++ b/libraries/Ethernet/src/ETH.cpp
@@ -0,0 +1,1170 @@
+/*
+ ETH.h - espre ETH PHY support.
+ Based on WiFi.h from Arduino WiFi shield library.
+ Copyright (c) 2011-2014 Arduino.  All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+// Disable the automatic pin remapping of the API calls in this file
+#define ARDUINO_CORE_BUILD
+
+#include "ETH.h"
+#if CONFIG_ETH_ENABLED
+#include "esp_system.h"
+#include "esp_event.h"
+#include "esp_eth.h"
+#include "esp_eth_mac.h"
+#include "esp_eth_com.h"
+#include "driver/gpio.h"
+#include "driver/spi_master.h"
+#if CONFIG_ETH_USE_ESP32_EMAC
+#if defined __has_include && __has_include("soc/emac_ext_struct.h")
+#include "soc/emac_ext_struct.h"
+#endif /* __has_include("soc/emac_ext_struct.h" */
+#include "soc/rtc.h"
+#endif /* CONFIG_ETH_USE_ESP32_EMAC */
+#include "esp32-hal-periman.h"
+#include "lwip/err.h"
+#include "lwip/dns.h"
+#include "esp_mac.h"
+#include "esp_netif.h"
+#include "esp_netif_types.h"
+#include "esp_netif_defaults.h"
+#include "esp_eth_phy.h"
+
+#define NUM_SUPPORTED_ETH_PORTS 3
+static ETHClass *_ethernets[NUM_SUPPORTED_ETH_PORTS] = {NULL, NULL, NULL};
+static esp_event_handler_instance_t _eth_ev_instance = NULL;
+
+static void _eth_event_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+
+  if (event_base == ETH_EVENT) {
+    esp_eth_handle_t eth_handle = *((esp_eth_handle_t *)event_data);
+    for (int i = 0; i < NUM_SUPPORTED_ETH_PORTS; ++i) {
+      if (_ethernets[i] != NULL && _ethernets[i]->handle() == eth_handle) {
+        _ethernets[i]->_onEthEvent(event_id, event_data);
+      }
+    }
+  }
+}
+
+// This callback needs to be aware of which interface it should match against
+static void onEthConnected(arduino_event_id_t event, arduino_event_info_t info) {
+  if (event == ARDUINO_EVENT_ETH_CONNECTED) {
+    uint8_t index = NUM_SUPPORTED_ETH_PORTS;
+    for (int i = 0; i < NUM_SUPPORTED_ETH_PORTS; ++i) {
+      if (_ethernets[i] != NULL && _ethernets[i]->handle() == info.eth_connected) {
+        index = i;
+        break;
+      }
+    }
+    if (index == NUM_SUPPORTED_ETH_PORTS) {
+      log_e("Could not find ETH interface with that handle!");
+      return;
+    }
+#if CONFIG_LWIP_IPV6
+    if (_ethernets[index]->getStatusBits() & ESP_NETIF_WANT_IP6_BIT) {
+      esp_err_t err = esp_netif_create_ip6_linklocal(_ethernets[index]->netif());
+      if (err != ESP_OK) {
+        log_e("Failed to enable IPv6 Link Local on ETH: [%d] %s", err, esp_err_to_name(err));
+      } else {
+        log_v("Enabled IPv6 Link Local on %s", _ethernets[index]->desc());
+      }
+    }
+#endif
+  }
+}
+
+esp_eth_handle_t ETHClass::handle() const {
+  return _eth_handle;
+}
+
+void ETHClass::_onEthEvent(int32_t event_id, void *event_data) {
+  arduino_event_t arduino_event;
+  arduino_event.event_id = ARDUINO_EVENT_MAX;
+
+  if (event_id == ETHERNET_EVENT_CONNECTED) {
+    log_v("%s Connected", desc());
+    arduino_event.event_id = ARDUINO_EVENT_ETH_CONNECTED;
+    arduino_event.event_info.eth_connected = handle();
+    setStatusBits(ESP_NETIF_CONNECTED_BIT);
+  } else if (event_id == ETHERNET_EVENT_DISCONNECTED) {
+    log_v("%s Disconnected", desc());
+    arduino_event.event_id = ARDUINO_EVENT_ETH_DISCONNECTED;
+    clearStatusBits(ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT);
+  } else if (event_id == ETHERNET_EVENT_START) {
+    log_v("%s Started", desc());
+    arduino_event.event_id = ARDUINO_EVENT_ETH_START;
+    setStatusBits(ESP_NETIF_STARTED_BIT);
+  } else if (event_id == ETHERNET_EVENT_STOP) {
+    log_v("%s Stopped", desc());
+    arduino_event.event_id = ARDUINO_EVENT_ETH_STOP;
+    clearStatusBits(
+      ESP_NETIF_STARTED_BIT | ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT
+      | ESP_NETIF_HAS_STATIC_IP_BIT
+    );
+  }
+
+  if (arduino_event.event_id < ARDUINO_EVENT_MAX) {
+    Network.postEvent(&arduino_event);
+  }
+}
+
+ETHClass::ETHClass(uint8_t eth_index)
+  : _eth_handle(NULL), _eth_index(eth_index), _phy_type(ETH_PHY_MAX), _glue_handle(NULL), _mac(NULL), _phy(NULL), _eth_started(false), _link_speed(100),
+    _full_duplex(true), _auto_negotiation(true)
+#if ETH_SPI_SUPPORTS_CUSTOM
+    ,
+    _spi(NULL)
+#endif
+    ,
+    _spi_freq_mhz(20), _pin_cs(-1), _pin_irq(-1), _pin_rst(-1), _pin_sck(-1), _pin_miso(-1), _pin_mosi(-1)
+#if CONFIG_ETH_USE_ESP32_EMAC
+    ,
+    _pin_mcd(-1), _pin_mdio(-1), _pin_power(-1), _pin_rmii_clock(-1)
+#endif /* CONFIG_ETH_USE_ESP32_EMAC */
+    ,
+    _task_stack_size(4096), _eth_connected_event_handle(0) {
+}
+
+ETHClass::~ETHClass() {}
+
+bool ETHClass::ethDetachBus(void *bus_pointer) {
+  ETHClass *bus = (ETHClass *)bus_pointer;
+  bus->end();
+  return true;
+}
+
+void ETHClass::setTaskStackSize(size_t size) {
+  _task_stack_size = size;
+}
+
+#if CONFIG_ETH_USE_ESP32_EMAC
+#if CONFIG_IDF_TARGET_ESP32
+#define ETH_EMAC_DEFAULT_CONFIG() ETH_ESP32_EMAC_DEFAULT_CONFIG()
+#elif CONFIG_IDF_TARGET_ESP32P4
+// clang-format off
+#define ETH_EMAC_DEFAULT_CONFIG()                                                  \
+  {                                                                                \
+    .smi_gpio = {.mdc_num = 31, .mdio_num = 52},                                   \
+    .interface = EMAC_DATA_INTERFACE_RMII,                                         \
+    .clock_config = {                                                              \
+      .rmii = {                                                                    \
+        .clock_mode = EMAC_CLK_EXT_IN,                                             \
+        .clock_gpio = (emac_rmii_clock_gpio_t)ETH_RMII_CLK                         \
+      }                                                                            \
+    },                                                                             \
+    .dma_burst_len = ETH_DMA_BURST_LEN_32,                                         \
+    .intr_priority = 0,                                                            \
+    .emac_dataif_gpio = {                                                          \
+      .rmii = {                                                                    \
+        .tx_en_num = ETH_RMII_TX_EN,                                               \
+        .txd0_num = ETH_RMII_TX0,                                                  \
+        .txd1_num = ETH_RMII_TX1,                                                  \
+        .crs_dv_num = ETH_RMII_CRS_DV,                                             \
+        .rxd0_num = ETH_RMII_RX0,                                                  \
+        .rxd1_num = ETH_RMII_RX1_EN                                                \
+      }                                                                            \
+    },                                                                             \
+    .clock_config_out_in = {                                                       \
+      .rmii = {                                                                    \
+        .clock_mode = EMAC_CLK_EXT_IN,                                             \
+        .clock_gpio = (emac_rmii_clock_gpio_t) - 1                                 \
+      }                                                                            \
+    },                                                                             \
+  }
+#endif
+// clang-format on
+
+bool ETHClass::begin(eth_phy_type_t type, int32_t phy_addr, int mdc, int mdio, int power, eth_clock_mode_t clock_mode) {
+  esp_err_t ret = ESP_OK;
+  if (_eth_index > 2) {
+    return false;
+  }
+  if (_esp_netif != NULL) {
+    return true;
+  }
+  if (phy_addr < ETH_PHY_ADDR_AUTO) {
+    log_e("Invalid PHY address: %d, set to ETH_PHY_ADDR_AUTO for auto detection", phy_addr);
+    return false;
+  }
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_RMII, ETHClass::ethDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_CLK, ETHClass::ethDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_MCD, ETHClass::ethDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_MDIO, ETHClass::ethDetachBus);
+  if (power != -1) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_PWR, ETHClass::ethDetachBus);
+  }
+
+  Network.begin();
+  _ethernets[_eth_index] = this;
+
+#if CONFIG_IDF_TARGET_ESP32
+#undef DEFAULT_RMII_CLK_GPIO
+#define DEFAULT_RMII_CLK_GPIO (emac_rmii_clock_gpio_t)(0)
+#endif
+
+  eth_esp32_emac_config_t mac_config = ETH_EMAC_DEFAULT_CONFIG();
+#if CONFIG_IDF_TARGET_ESP32
+  mac_config.clock_config.rmii.clock_mode = (clock_mode) ? EMAC_CLK_OUT : EMAC_CLK_EXT_IN;
+  mac_config.clock_config.rmii.clock_gpio = (1 == clock_mode)   ? EMAC_APPL_CLK_OUT_GPIO
+                                            : (2 == clock_mode) ? EMAC_CLK_OUT_GPIO
+                                            : (3 == clock_mode) ? EMAC_CLK_OUT_180_GPIO
+                                                                : EMAC_CLK_IN_GPIO;
+#elif CONFIG_IDF_TARGET_ESP32P4
+  mac_config.clock_config.rmii.clock_mode = (emac_rmii_clock_mode_t)clock_mode;
+#endif
+  mac_config.smi_gpio.mdc_num = digitalPinToGPIONumber(mdc);
+  mac_config.smi_gpio.mdio_num = digitalPinToGPIONumber(mdio);
+
+  _pin_mcd = digitalPinToGPIONumber(mdc);
+  _pin_mdio = digitalPinToGPIONumber(mdio);
+  _pin_rmii_clock = mac_config.clock_config.rmii.clock_gpio;
+  _pin_power = digitalPinToGPIONumber(power);
+
+  if (!perimanClearPinBus(_pin_rmii_clock)) {
+    return false;
+  }
+  if (!perimanClearPinBus(_pin_mcd)) {
+    return false;
+  }
+  if (!perimanClearPinBus(_pin_mdio)) {
+    return false;
+  }
+  if (!perimanClearPinBus(ETH_RMII_TX_EN)) {
+    return false;
+  }
+  if (!perimanClearPinBus(ETH_RMII_TX0)) {
+    return false;
+  }
+  if (!perimanClearPinBus(ETH_RMII_TX1)) {
+    return false;
+  }
+  if (!perimanClearPinBus(ETH_RMII_RX0)) {
+    return false;
+  }
+  if (!perimanClearPinBus(ETH_RMII_RX1_EN)) {
+    return false;
+  }
+  if (!perimanClearPinBus(ETH_RMII_CRS_DV)) {
+    return false;
+  }
+  if (_pin_power != -1) {
+    if (!perimanClearPinBus(_pin_power)) {
+      return false;
+    }
+  }
+
+  eth_mac_config_t eth_mac_config = ETH_MAC_DEFAULT_CONFIG();
+  eth_mac_config.sw_reset_timeout_ms = 1000;
+  eth_mac_config.rx_task_stack_size = _task_stack_size;
+
+  _mac = esp_eth_mac_new_esp32(&mac_config, &eth_mac_config);
+  if (_mac == NULL) {
+    log_e("esp_eth_mac_new_esp32 failed");
+    return false;
+  }
+
+  eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG();
+  phy_config.phy_addr = phy_addr;
+  phy_config.reset_gpio_num = _pin_power;
+
+  switch (type) {
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
+    case ETH_PHY_GENERIC: _phy = esp_eth_phy_new_generic(&phy_config); break;
+#endif
+    case ETH_PHY_LAN8720: _phy = esp_eth_phy_new_lan87xx(&phy_config); break;
+    case ETH_PHY_TLK110:  _phy = esp_eth_phy_new_ip101(&phy_config); break;
+    case ETH_PHY_RTL8201: _phy = esp_eth_phy_new_rtl8201(&phy_config); break;
+    case ETH_PHY_DP83848: _phy = esp_eth_phy_new_dp83848(&phy_config); break;
+    case ETH_PHY_KSZ8041: _phy = esp_eth_phy_new_ksz80xx(&phy_config); break;
+    case ETH_PHY_KSZ8081: _phy = esp_eth_phy_new_ksz80xx(&phy_config); break;
+    default:              log_e("Unsupported PHY %d", type); break;
+  }
+  if (_phy == NULL) {
+    log_e("esp_eth_phy_new failed");
+    return false;
+  }
+
+  _eth_handle = NULL;
+  esp_eth_config_t eth_config = ETH_DEFAULT_CONFIG(_mac, _phy);
+  ret = esp_eth_driver_install(&eth_config, &_eth_handle);
+  if (ret != ESP_OK) {
+    log_e("Ethernet driver install failed: %d", ret);
+    return false;
+  }
+  if (_eth_handle == NULL) {
+    log_e("esp_eth_driver_install failed! eth_handle is NULL");
+    return false;
+  }
+
+  esp_netif_config_t cfg = ESP_NETIF_DEFAULT_ETH();
+
+  // Use ESP_NETIF_INHERENT_DEFAULT_ETH when multiple Ethernet interfaces are used and so you need to modify
+  // esp-netif configuration parameters for each interface (name, priority, etc.).
+  char if_key_str[10];
+  char if_desc_str[10];
+  char num_str[3];
+  itoa(_eth_index, num_str, 10);
+  if (_eth_index == 0) {
+    strcpy(if_key_str, "ETH_DEF");
+  } else {
+    strcat(strcpy(if_key_str, "ETH_"), num_str);
+  }
+  strcat(strcpy(if_desc_str, "eth"), num_str);
+
+  esp_netif_inherent_config_t esp_netif_config = ESP_NETIF_INHERENT_DEFAULT_ETH();
+  esp_netif_config.if_key = if_key_str;
+  esp_netif_config.if_desc = if_desc_str;
+  esp_netif_config.route_prio -= _eth_index * 5;
+
+  cfg.base = &esp_netif_config;
+
+  _esp_netif = esp_netif_new(&cfg);
+  if (_esp_netif == NULL) {
+    log_e("esp_netif_new failed");
+    return false;
+  }
+
+  _glue_handle = esp_eth_new_netif_glue(_eth_handle);
+  if (_glue_handle == NULL) {
+    log_e("esp_eth_new_netif_glue failed");
+    return false;
+  }
+
+  /* attach Ethernet driver to TCP/IP stack */
+  ret = esp_netif_attach(_esp_netif, _glue_handle);
+  if (ret != ESP_OK) {
+    log_e("esp_netif_attach failed: %d", ret);
+    return false;
+  }
+
+  // auto negotiation needs to be disabled to change duplex mode and link speed
+  if (!_auto_negotiation) {
+    if (!_setAutoNegotiation(_auto_negotiation)) {
+      return false;
+    }
+    if (!_setFullDuplex(_full_duplex)) {
+      return false;
+    }
+    if (!_setLinkSpeed(_link_speed)) {
+      return false;
+    }
+  }
+
+  if (_eth_ev_instance == NULL && esp_event_handler_instance_register(ETH_EVENT, ESP_EVENT_ANY_ID, &_eth_event_cb, NULL, &_eth_ev_instance)) {
+    log_e("event_handler_instance_register for ETH_EVENT Failed!");
+    return false;
+  }
+
+  /* attach to receive events */
+  initNetif((Network_Interface_ID)(ESP_NETIF_ID_ETH + _eth_index));
+
+  _eth_connected_event_handle = Network.onSysEvent(onEthConnected, ARDUINO_EVENT_ETH_CONNECTED);
+
+  ret = esp_eth_start(_eth_handle);
+  if (ret != ESP_OK) {
+    log_e("esp_eth_start failed: %d", ret);
+    return false;
+  }
+
+  _eth_started = true;
+
+  if (!perimanSetPinBus(_pin_rmii_clock, ESP32_BUS_TYPE_ETHERNET_CLK, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!perimanSetPinBus(_pin_mcd, ESP32_BUS_TYPE_ETHERNET_MCD, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!perimanSetPinBus(_pin_mdio, ESP32_BUS_TYPE_ETHERNET_MDIO, (void *)(this), -1, -1)) {
+    goto err;
+  }
+
+  if (!perimanSetPinBus(ETH_RMII_TX_EN, ESP32_BUS_TYPE_ETHERNET_RMII, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!perimanSetPinBus(ETH_RMII_TX0, ESP32_BUS_TYPE_ETHERNET_RMII, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!perimanSetPinBus(ETH_RMII_TX1, ESP32_BUS_TYPE_ETHERNET_RMII, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!perimanSetPinBus(ETH_RMII_RX0, ESP32_BUS_TYPE_ETHERNET_RMII, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!perimanSetPinBus(ETH_RMII_RX1_EN, ESP32_BUS_TYPE_ETHERNET_RMII, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!perimanSetPinBus(ETH_RMII_CRS_DV, ESP32_BUS_TYPE_ETHERNET_RMII, (void *)(this), -1, -1)) {
+    goto err;
+  }
+
+  if (_pin_power != -1) {
+    if (!perimanSetPinBus(_pin_power, ESP32_BUS_TYPE_ETHERNET_PWR, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+
+  // holds a few milliseconds to let DHCP start and enter into a good state
+  // FIX ME -- addresses issue https://github.com/espressif/arduino-esp32/issues/5733
+  delay(50);
+
+  return true;
+
+err:
+  log_e("Failed to set all pins bus to ETHERNET");
+  ETHClass::ethDetachBus((void *)(this));
+  return false;
+}
+#endif /* CONFIG_ETH_USE_ESP32_EMAC */
+
+#if ETH_SPI_SUPPORTS_CUSTOM
+__unused static void *_eth_spi_init(const void *ctx) {
+  return (void *)ctx;
+}
+
+__unused static esp_err_t _eth_spi_deinit(void *ctx) {
+  return ESP_OK;
+}
+
+esp_err_t ETHClass::_eth_spi_read(void *ctx, uint32_t cmd, uint32_t addr, void *data, uint32_t data_len) {
+  return ((ETHClass *)ctx)->eth_spi_read(cmd, addr, data, data_len);
+}
+
+esp_err_t ETHClass::_eth_spi_write(void *ctx, uint32_t cmd, uint32_t addr, const void *data, uint32_t data_len) {
+  return ((ETHClass *)ctx)->eth_spi_write(cmd, addr, data, data_len);
+}
+
+esp_err_t ETHClass::eth_spi_read(uint32_t cmd, uint32_t addr, void *data, uint32_t data_len) {
+  if (_spi == NULL) {
+    return ESP_FAIL;
+  }
+  // log_i(" 0x%04lx 0x%04lx %lu", cmd, addr, data_len);
+  _spi->beginTransaction(SPISettings(_spi_freq_mhz * 1000 * 1000, MSBFIRST, SPI_MODE0));
+  digitalWrite(_pin_cs, LOW);
+
+#if CONFIG_ETH_SPI_ETHERNET_DM9051
+  if (_phy_type == ETH_PHY_DM9051) {
+    _spi->write(((cmd & 0x01) << 7) | (addr & 0x7F));
+  } else
+#endif
+#if CONFIG_ETH_SPI_ETHERNET_W5500
+    if (_phy_type == ETH_PHY_W5500) {
+    _spi->write16(cmd);
+    _spi->write(addr);
+  } else
+#endif
+#if CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL
+    if (_phy_type == ETH_PHY_KSZ8851) {
+    if (cmd > 1) {
+      _spi->write(cmd << 6 | addr);
+    } else {
+      _spi->write16(cmd << 14 | addr);
+    }
+  } else
+#endif
+  {
+    log_e("Unsupported PHY module: %d", _phy_type);
+    digitalWrite(_pin_cs, HIGH);
+    _spi->endTransaction();
+    return ESP_FAIL;
+  }
+  _spi->transferBytes(NULL, (uint8_t *)data, data_len);
+
+  digitalWrite(_pin_cs, HIGH);
+  _spi->endTransaction();
+  return ESP_OK;
+}
+
+esp_err_t ETHClass::eth_spi_write(uint32_t cmd, uint32_t addr, const void *data, uint32_t data_len) {
+  if (_spi == NULL) {
+    return ESP_FAIL;
+  }
+  // log_i("0x%04lx 0x%04lx %lu", cmd, addr, data_len);
+  _spi->beginTransaction(SPISettings(_spi_freq_mhz * 1000 * 1000, MSBFIRST, SPI_MODE0));
+  digitalWrite(_pin_cs, LOW);
+
+#if CONFIG_ETH_SPI_ETHERNET_DM9051
+  if (_phy_type == ETH_PHY_DM9051) {
+    _spi->write(((cmd & 0x01) << 7) | (addr & 0x7F));
+  } else
+#endif
+#if CONFIG_ETH_SPI_ETHERNET_W5500
+    if (_phy_type == ETH_PHY_W5500) {
+    _spi->write16(cmd);
+    _spi->write(addr);
+  } else
+#endif
+#if CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL
+    if (_phy_type == ETH_PHY_KSZ8851) {
+    if (cmd > 1) {
+      _spi->write(cmd << 6 | addr);
+    } else {
+      _spi->write16(cmd << 14 | addr);
+    }
+  } else
+#endif
+  {
+    log_e("Unsupported PHY module: %d", _phy_type);
+    digitalWrite(_pin_cs, HIGH);
+    _spi->endTransaction();
+    return ESP_FAIL;
+  }
+  _spi->writeBytes((const uint8_t *)data, data_len);
+
+  digitalWrite(_pin_cs, HIGH);
+  _spi->endTransaction();
+  return ESP_OK;
+}
+#endif
+
+bool ETHClass::beginSPI(
+  eth_phy_type_t type, int32_t phy_addr, uint8_t *mac_addr_p, int cs, int irq, int rst,
+#if ETH_SPI_SUPPORTS_CUSTOM
+  SPIClass *spi,
+#endif
+  int sck, int miso, int mosi, spi_host_device_t spi_host, uint8_t spi_freq_mhz
+) {
+  esp_err_t ret = ESP_OK;
+
+  if (_esp_netif != NULL || _eth_handle != NULL) {
+    log_w("ETH Already Started");
+    return true;
+  }
+#if ETH_SPI_SUPPORTS_NO_IRQ
+  if (cs < 0) {
+    log_e("CS pin must be defined!");
+#else
+  if (cs < 0 || irq < 0) {
+    log_e("CS and IRQ pins must be defined!");
+#endif
+    return false;
+  }
+  if (phy_addr < ETH_PHY_ADDR_AUTO) {
+    log_e("Invalid PHY address: %d, set to ETH_PHY_ADDR_AUTO for auto detection", phy_addr);
+    return false;
+  }
+
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_SPI, ETHClass::ethDetachBus);
+
+  if (_pin_cs != -1) {
+    if (!perimanClearPinBus(_pin_cs)) {
+      return false;
+    }
+  }
+  if (_pin_rst != -1) {
+    if (!perimanClearPinBus(_pin_rst)) {
+      return false;
+    }
+  }
+  if (_pin_irq != -1) {
+    if (!perimanClearPinBus(_pin_irq)) {
+      return false;
+    }
+  }
+  if (_pin_sck != -1) {
+    if (!perimanClearPinBus(_pin_sck)) {
+      return false;
+    }
+  }
+  if (_pin_miso != -1) {
+    if (!perimanClearPinBus(_pin_miso)) {
+      return false;
+    }
+  }
+  if (_pin_mosi != -1) {
+    if (!perimanClearPinBus(_pin_mosi)) {
+      return false;
+    }
+  }
+
+#if ETH_SPI_SUPPORTS_CUSTOM
+  _spi = spi;
+#endif
+  if (spi_freq_mhz) {
+    _spi_freq_mhz = spi_freq_mhz;
+  }
+  _phy_type = type;
+  _pin_cs = digitalPinToGPIONumber(cs);
+  _pin_irq = digitalPinToGPIONumber(irq);
+  _pin_rst = digitalPinToGPIONumber(rst);
+  _pin_sck = digitalPinToGPIONumber(sck);
+  _pin_miso = digitalPinToGPIONumber(miso);
+  _pin_mosi = digitalPinToGPIONumber(mosi);
+
+#if ETH_SPI_SUPPORTS_CUSTOM
+  if (_spi != NULL) {
+    pinMode(_pin_cs, OUTPUT);
+    digitalWrite(_pin_cs, HIGH);
+    char cs_num_str[3];
+    itoa(_eth_index, cs_num_str, 10);
+    strcat(strcpy(_cs_str, "ETH_CS["), cs_num_str);
+    strcat(_cs_str, "]");
+    perimanSetPinBusExtraType(_pin_cs, _cs_str);
+  }
+#endif
+
+  // Init SPI bus
+  if (_pin_sck >= 0 && _pin_miso >= 0 && _pin_mosi >= 0) {
+    spi_bus_config_t buscfg;
+    memset(&buscfg, 0, sizeof(spi_bus_config_t));
+    buscfg.mosi_io_num = _pin_mosi;
+    buscfg.miso_io_num = _pin_miso;
+    buscfg.sclk_io_num = _pin_sck;
+    buscfg.quadwp_io_num = -1;
+    buscfg.quadhd_io_num = -1;
+    buscfg.data4_io_num = -1;
+    buscfg.data5_io_num = -1;
+    buscfg.data6_io_num = -1;
+    buscfg.data7_io_num = -1;
+    buscfg.max_transfer_sz = -1;
+    ret = spi_bus_initialize(spi_host, &buscfg, SPI_DMA_CH_AUTO);
+    if (ret != ESP_OK && ret != ESP_ERR_INVALID_STATE) {
+      log_e("SPI bus initialize failed: %d", ret);
+      return false;
+    }
+  }
+
+  Network.begin();
+  _ethernets[_eth_index] = this;
+
+  // Install GPIO ISR handler to be able to service SPI Eth modules interrupts
+  ret = gpio_install_isr_service(0);
+  if (ret != ESP_OK && ret != ESP_ERR_INVALID_STATE) {
+    log_e("GPIO ISR handler install failed: %d", ret);
+    return false;
+  }
+
+  // Init common MAC and PHY configs to default
+  __unused eth_mac_config_t eth_mac_config = ETH_MAC_DEFAULT_CONFIG();
+  __unused eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG();
+
+  // Set RX Task Stack Size
+  eth_mac_config.rx_task_stack_size = _task_stack_size;
+
+  // Update PHY config based on board specific configuration
+  phy_config.phy_addr = phy_addr;
+  phy_config.reset_gpio_num = _pin_rst;
+
+  // Configure SPI interface for specific SPI module
+  spi_device_interface_config_t spi_devcfg;
+  memset(&spi_devcfg, 0, sizeof(spi_device_interface_config_t));
+  spi_devcfg.mode = 0;
+  spi_devcfg.clock_speed_hz = _spi_freq_mhz * 1000 * 1000;
+  spi_devcfg.input_delay_ns = 20;
+  spi_devcfg.spics_io_num = _pin_cs;
+  spi_devcfg.queue_size = 20;
+
+#if CONFIG_ETH_SPI_ETHERNET_W5500
+  if (type == ETH_PHY_W5500) {
+    eth_w5500_config_t mac_config = ETH_W5500_DEFAULT_CONFIG(spi_host, &spi_devcfg);
+    mac_config.int_gpio_num = _pin_irq;
+#if ETH_SPI_SUPPORTS_NO_IRQ
+    if (_pin_irq < 0) {
+      mac_config.poll_period_ms = 10;
+    }
+#endif
+#if ETH_SPI_SUPPORTS_CUSTOM
+    if (_spi != NULL) {
+      mac_config.custom_spi_driver.config = this;
+      mac_config.custom_spi_driver.init = _eth_spi_init;
+      mac_config.custom_spi_driver.deinit = _eth_spi_deinit;
+      mac_config.custom_spi_driver.read = _eth_spi_read;
+      mac_config.custom_spi_driver.write = _eth_spi_write;
+    }
+#endif
+    _mac = esp_eth_mac_new_w5500(&mac_config, &eth_mac_config);
+    _phy = esp_eth_phy_new_w5500(&phy_config);
+  } else
+#endif
+#if CONFIG_ETH_SPI_ETHERNET_DM9051
+    if (type == ETH_PHY_DM9051) {
+    eth_dm9051_config_t mac_config = ETH_DM9051_DEFAULT_CONFIG(spi_host, &spi_devcfg);
+    mac_config.int_gpio_num = _pin_irq;
+#if ETH_SPI_SUPPORTS_CUSTOM
+    if (_spi != NULL) {
+      mac_config.custom_spi_driver.config = this;
+      mac_config.custom_spi_driver.init = _eth_spi_init;
+      mac_config.custom_spi_driver.deinit = _eth_spi_deinit;
+      mac_config.custom_spi_driver.read = _eth_spi_read;
+      mac_config.custom_spi_driver.write = _eth_spi_write;
+    }
+#endif
+    _mac = esp_eth_mac_new_dm9051(&mac_config, &eth_mac_config);
+    _phy = esp_eth_phy_new_dm9051(&phy_config);
+  } else
+#endif
+#if CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL
+    if (type == ETH_PHY_KSZ8851) {
+    eth_ksz8851snl_config_t mac_config = ETH_KSZ8851SNL_DEFAULT_CONFIG(spi_host, &spi_devcfg);
+    mac_config.int_gpio_num = _pin_irq;
+#if ETH_SPI_SUPPORTS_CUSTOM
+    if (_spi != NULL) {
+      mac_config.custom_spi_driver.config = this;
+      mac_config.custom_spi_driver.init = _eth_spi_init;
+      mac_config.custom_spi_driver.deinit = _eth_spi_deinit;
+      mac_config.custom_spi_driver.read = _eth_spi_read;
+      mac_config.custom_spi_driver.write = _eth_spi_write;
+    }
+#endif
+    _mac = esp_eth_mac_new_ksz8851snl(&mac_config, &eth_mac_config);
+    _phy = esp_eth_phy_new_ksz8851snl(&phy_config);
+  } else
+#endif
+  {
+    log_e("Unsupported PHY module: %d", (int)type);
+    return false;
+  }
+
+  // Init Ethernet driver to default and install it
+  esp_eth_config_t eth_config = ETH_DEFAULT_CONFIG(_mac, _phy);
+  ret = esp_eth_driver_install(&eth_config, &_eth_handle);
+  if (ret != ESP_OK) {
+    log_e("SPI Ethernet driver install failed: %d", ret);
+    return false;
+  }
+  if (_eth_handle == NULL) {
+    log_e("esp_eth_driver_install failed! eth_handle is NULL");
+    return false;
+  }
+
+  uint8_t mac_addr[ETH_ADDR_LEN];
+  if (mac_addr_p != nullptr) {
+    memcpy(mac_addr, mac_addr_p, ETH_ADDR_LEN);
+  } else {
+    // Derive a new MAC address for this interface
+    uint8_t base_mac_addr[ETH_ADDR_LEN];
+    ret = esp_efuse_mac_get_default(base_mac_addr);
+    if (ret != ESP_OK) {
+      log_e("Get EFUSE MAC failed: %d", ret);
+      return false;
+    }
+    base_mac_addr[ETH_ADDR_LEN - 1] += _eth_index;  //Increment by the ETH number
+    esp_derive_local_mac(mac_addr, base_mac_addr);
+  }
+
+  ret = esp_eth_ioctl(_eth_handle, ETH_CMD_S_MAC_ADDR, mac_addr);
+  if (ret != ESP_OK) {
+    log_e("SPI Ethernet MAC address config failed: %d", ret);
+    return false;
+  }
+
+  // Use ESP_NETIF_DEFAULT_ETH when just one Ethernet interface is used and you don't need to modify
+  // default esp-netif configuration parameters.
+  esp_netif_config_t cfg = ESP_NETIF_DEFAULT_ETH();
+
+  // Use ESP_NETIF_INHERENT_DEFAULT_ETH when multiple Ethernet interfaces are used and so you need to modify
+  // esp-netif configuration parameters for each interface (name, priority, etc.).
+  char if_key_str[10];
+  char if_desc_str[10];
+  char num_str[3];
+  itoa(_eth_index, num_str, 10);
+  if (_eth_index == 0) {
+    strcpy(if_key_str, "ETH_DEF");
+  } else {
+    strcat(strcpy(if_key_str, "ETH_"), num_str);
+  }
+  strcat(strcpy(if_desc_str, "eth"), num_str);
+
+  esp_netif_inherent_config_t esp_netif_config = ESP_NETIF_INHERENT_DEFAULT_ETH();
+  esp_netif_config.if_key = if_key_str;
+  esp_netif_config.if_desc = if_desc_str;
+  esp_netif_config.route_prio -= _eth_index * 5;
+
+  cfg.base = &esp_netif_config;
+
+  _esp_netif = esp_netif_new(&cfg);
+  if (_esp_netif == NULL) {
+    log_e("esp_netif_new failed");
+    return false;
+  }
+  // Attach Ethernet driver to TCP/IP stack
+  _glue_handle = esp_eth_new_netif_glue(_eth_handle);
+  if (_glue_handle == NULL) {
+    log_e("esp_eth_new_netif_glue failed");
+    return false;
+  }
+
+  ret = esp_netif_attach(_esp_netif, _glue_handle);
+  if (ret != ESP_OK) {
+    log_e("esp_netif_attach failed: %d", ret);
+    return false;
+  }
+
+  // auto negotiation needs to be disabled to change duplex mode and link speed
+  if (!_auto_negotiation) {
+    if (!_setAutoNegotiation(_auto_negotiation)) {
+      return false;
+    }
+    if (!_setFullDuplex(_full_duplex)) {
+      return false;
+    }
+    if (!_setLinkSpeed(_link_speed)) {
+      return false;
+    }
+  }
+
+  if (_eth_ev_instance == NULL && esp_event_handler_instance_register(ETH_EVENT, ESP_EVENT_ANY_ID, &_eth_event_cb, NULL, &_eth_ev_instance)) {
+    log_e("event_handler_instance_register for ETH_EVENT Failed!");
+    return false;
+  }
+
+  /* attach to receive events */
+  initNetif((Network_Interface_ID)(ESP_NETIF_ID_ETH + _eth_index));
+
+  // Start Ethernet driver state machine
+  ret = esp_eth_start(_eth_handle);
+  if (ret != ESP_OK) {
+    log_e("esp_eth_start failed: %d", ret);
+    return false;
+  }
+
+  _eth_started = true;
+
+  // If Arduino's SPI is used, cs pin is in GPIO mode
+#if ETH_SPI_SUPPORTS_CUSTOM
+  if (_spi == NULL) {
+#endif
+    if (!perimanSetPinBus(_pin_cs, ESP32_BUS_TYPE_ETHERNET_SPI, (void *)(this), _eth_index, -1)) {
+      goto err;
+    }
+    perimanSetPinBusExtraType(_pin_cs, "ETH_SPI_CS");
+#if ETH_SPI_SUPPORTS_CUSTOM
+  }
+#endif
+#if ETH_SPI_SUPPORTS_NO_IRQ
+  if (_pin_irq != -1) {
+#endif
+    if (!perimanSetPinBus(_pin_irq, ESP32_BUS_TYPE_ETHERNET_SPI, (void *)(this), _eth_index, -1)) {
+      goto err;
+    }
+    perimanSetPinBusExtraType(_pin_irq, "ETH_IRQ");
+#if ETH_SPI_SUPPORTS_NO_IRQ
+  }
+#endif
+  if (_pin_sck != -1) {
+    if (!perimanSetPinBus(_pin_sck, ESP32_BUS_TYPE_ETHERNET_SPI, (void *)(this), _eth_index, -1)) {
+      goto err;
+    }
+    perimanSetPinBusExtraType(_pin_sck, "ETH_SPI_SCK");
+  }
+  if (_pin_miso != -1) {
+    if (!perimanSetPinBus(_pin_miso, ESP32_BUS_TYPE_ETHERNET_SPI, (void *)(this), _eth_index, -1)) {
+      goto err;
+    }
+    perimanSetPinBusExtraType(_pin_miso, "ETH_SPI_MISO");
+  }
+  if (_pin_mosi != -1) {
+    if (!perimanSetPinBus(_pin_mosi, ESP32_BUS_TYPE_ETHERNET_SPI, (void *)(this), _eth_index, -1)) {
+      goto err;
+    }
+    perimanSetPinBusExtraType(_pin_mosi, "ETH_SPI_MOSI");
+  }
+  if (_pin_rst != -1) {
+    if (!perimanSetPinBus(_pin_rst, ESP32_BUS_TYPE_ETHERNET_SPI, (void *)(this), _eth_index, -1)) {
+      goto err;
+    }
+    perimanSetPinBusExtraType(_pin_rst, "ETH_RST");
+  }
+
+  _eth_connected_event_handle = Network.onSysEvent(onEthConnected, ARDUINO_EVENT_ETH_CONNECTED);
+
+  return true;
+
+err:
+  log_e("Failed to set all pins bus to ETHERNET");
+  ETHClass::ethDetachBus((void *)(this));
+  return false;
+}
+
+#if ETH_SPI_SUPPORTS_CUSTOM
+bool ETHClass::begin(eth_phy_type_t type, int32_t phy_addr, int cs, int irq, int rst, SPIClass &spi, uint8_t spi_freq_mhz) {
+
+  return beginSPI(type, phy_addr, nullptr, cs, irq, rst, &spi, -1, -1, -1, SPI2_HOST, spi_freq_mhz);
+}
+#endif
+
+bool ETHClass::begin(
+  eth_phy_type_t type, int32_t phy_addr, int cs, int irq, int rst, spi_host_device_t spi_host, int sck, int miso, int mosi, uint8_t spi_freq_mhz
+) {
+
+  return beginSPI(
+    type, phy_addr, nullptr, cs, irq, rst,
+#if ETH_SPI_SUPPORTS_CUSTOM
+    NULL,
+#endif
+    sck, miso, mosi, spi_host, spi_freq_mhz
+  );
+}
+
+static bool empty_ethDetachBus(void *bus_pointer) {
+  return true;
+}
+
+void ETHClass::end(void) {
+
+  Network.removeEvent(_eth_connected_event_handle);
+  _eth_connected_event_handle = 0;
+
+  if (_eth_handle != NULL) {
+    if (esp_eth_stop(_eth_handle) != ESP_OK) {
+      log_e("Failed to stop Ethernet");
+      return;
+    }
+    //wait for stop
+    while (getStatusBits() & ESP_NETIF_STARTED_BIT) {
+      delay(10);
+    }
+
+    _eth_started = false;
+
+    //delete glue first
+    if (_glue_handle != NULL) {
+      if (esp_eth_del_netif_glue(_glue_handle) != ESP_OK) {
+        log_e("Failed to del_netif_glue Ethernet");
+        return;
+      }
+      _glue_handle = NULL;
+    }
+    //uninstall driver
+    if (esp_eth_driver_uninstall(_eth_handle) != ESP_OK) {
+      log_e("Failed to uninstall Ethernet");
+      return;
+    }
+    _eth_handle = NULL;
+    //delete mac
+    if (_mac != NULL) {
+      _mac->del(_mac);
+      _mac = NULL;
+    }
+    //delete phy
+    if (_phy != NULL) {
+      _phy->del(_phy);
+      _phy = NULL;
+    }
+  }
+
+  if (_eth_ev_instance != NULL) {
+    bool do_not_unreg_ev_handler = false;
+    for (int i = 0; i < NUM_SUPPORTED_ETH_PORTS; ++i) {
+      if (_ethernets[i] != NULL && _ethernets[i]->netif() != NULL && _ethernets[i]->netif() != _esp_netif) {
+        do_not_unreg_ev_handler = true;
+        break;
+      }
+    }
+    if (!do_not_unreg_ev_handler) {
+      if (esp_event_handler_unregister(ETH_EVENT, ESP_EVENT_ANY_ID, &_eth_event_cb) == ESP_OK) {
+        _eth_ev_instance = NULL;
+        log_v("Unregistered event handler");
+      } else {
+        log_e("Failed to unregister event handler");
+      }
+    }
+  }
+
+  destroyNetif();
+
+#if ETH_SPI_SUPPORTS_CUSTOM
+  _spi = NULL;
+#endif
+#if (CONFIG_ETH_USE_ESP32_EMAC && !defined(CONFIG_IDF_TARGET_ESP32P4))
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_RMII, empty_ethDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_CLK, empty_ethDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_MCD, empty_ethDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_MDIO, empty_ethDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_PWR, empty_ethDetachBus);
+  if (_pin_rmii_clock != -1 && _pin_mcd != -1 && _pin_mdio != -1) {
+    perimanClearPinBus(_pin_rmii_clock);
+    perimanClearPinBus(_pin_mcd);
+    perimanClearPinBus(_pin_mdio);
+
+    perimanClearPinBus(ETH_RMII_TX_EN);
+    perimanClearPinBus(ETH_RMII_TX0);
+    perimanClearPinBus(ETH_RMII_TX1);
+    perimanClearPinBus(ETH_RMII_RX0);
+    perimanClearPinBus(ETH_RMII_RX1_EN);
+    perimanClearPinBus(ETH_RMII_CRS_DV);
+
+    _pin_rmii_clock = -1;
+    _pin_mcd = -1;
+    _pin_mdio = -1;
+  }
+
+  if (_pin_power != -1) {
+    perimanClearPinBus(_pin_power);
+    _pin_power = -1;
+  }
+#endif /* CONFIG_ETH_USE_ESP32_EMAC */
+  perimanSetBusDeinit(ESP32_BUS_TYPE_ETHERNET_SPI, empty_ethDetachBus);
+  if (_pin_cs != -1) {
+    perimanClearPinBus(_pin_cs);
+    _pin_cs = -1;
+  }
+  if (_pin_irq != -1) {
+    perimanClearPinBus(_pin_irq);
+    _pin_irq = -1;
+  }
+  if (_pin_sck != -1) {
+    perimanClearPinBus(_pin_sck);
+    _pin_sck = -1;
+  }
+  if (_pin_miso != -1) {
+    perimanClearPinBus(_pin_miso);
+    _pin_miso = -1;
+  }
+  if (_pin_mosi != -1) {
+    perimanClearPinBus(_pin_mosi);
+    _pin_mosi = -1;
+  }
+  if (_pin_rst != -1) {
+    perimanClearPinBus(_pin_rst);
+    _pin_rst = -1;
+  }
+}
+
+bool ETHClass::fullDuplex() const {
+  if (_eth_handle == NULL) {
+    return false;
+  }
+  eth_duplex_t link_duplex;
+  esp_eth_ioctl(_eth_handle, ETH_CMD_G_DUPLEX_MODE, &link_duplex);
+  return (link_duplex == ETH_DUPLEX_FULL);
+}
+
+bool ETHClass::_setFullDuplex(bool on) {
+  if (_eth_handle == NULL) {
+    return false;
+  }
+  eth_duplex_t link_duplex = on ? ETH_DUPLEX_FULL : ETH_DUPLEX_HALF;
+  esp_err_t err = esp_eth_ioctl(_eth_handle, ETH_CMD_S_DUPLEX_MODE, &link_duplex);
+  if (err != ESP_OK) {
+    log_e("Failed to set duplex mode: 0x%x: %s", err, esp_err_to_name(err));
+  }
+  return err == ESP_OK;
+}
+
+bool ETHClass::setFullDuplex(bool on) {
+  if (_eth_started) {
+    log_e("This method must be called before ETH.begin()");
+    return false;
+  }
+  if (_auto_negotiation) {
+    log_w("Auto Negotiation MUST be OFF for this setting to be applied");
+  }
+  _full_duplex = on;
+  return true;
+}
+
+bool ETHClass::autoNegotiation() const {
+  if (_eth_handle == NULL) {
+    return false;
+  }
+  bool auto_nego;
+  esp_eth_ioctl(_eth_handle, ETH_CMD_G_AUTONEGO, &auto_nego);
+  return auto_nego;
+}
+
+bool ETHClass::_setAutoNegotiation(bool on) {
+  if (_eth_handle == NULL) {
+    return false;
+  }
+  esp_err_t err = esp_eth_ioctl(_eth_handle, ETH_CMD_S_AUTONEGO, &on);
+  if (err != ESP_OK) {
+    log_e("Failed to set auto negotiation: 0x%x: %s", err, esp_err_to_name(err));
+  }
+  return err == ESP_OK;
+}
+
+bool ETHClass::setAutoNegotiation(bool on) {
+  if (_eth_started) {
+    log_e("This method must be called before ETH.begin()");
+    return false;
+  }
+  _auto_negotiation = on;
+  return true;
+}
+
+uint32_t ETHClass::phyAddr() const {
+  if (_eth_handle == NULL) {
+    return 0;
+  }
+  uint32_t phy_addr;
+  esp_eth_ioctl(_eth_handle, ETH_CMD_G_PHY_ADDR, &phy_addr);
+  return phy_addr;
+}
+
+uint16_t ETHClass::linkSpeed() const {
+  if (_eth_handle == NULL) {
+    return 0;
+  }
+  eth_speed_t link_speed;
+  esp_eth_ioctl(_eth_handle, ETH_CMD_G_SPEED, &link_speed);
+  return (link_speed == ETH_SPEED_10M) ? 10 : 100;
+}
+
+bool ETHClass::_setLinkSpeed(uint16_t speed) {
+  if (_eth_handle == NULL) {
+    return false;
+  }
+  eth_speed_t link_speed = (speed == 10) ? ETH_SPEED_10M : ETH_SPEED_100M;
+  esp_err_t err = esp_eth_ioctl(_eth_handle, ETH_CMD_S_SPEED, &link_speed);
+  if (err != ESP_OK) {
+    log_e("Failed to set link speed: 0x%x: %s", err, esp_err_to_name(err));
+  }
+  return err == ESP_OK;
+}
+
+bool ETHClass::setLinkSpeed(uint16_t speed) {
+  if (speed != 10 && speed != 100) {
+    log_e("Ethernet currently supports only 10 or 100 Mbps link speed");
+    return false;
+  }
+  if (_eth_started) {
+    log_e("This method must be called before ETH.begin()");
+    return false;
+  }
+  if (_auto_negotiation) {
+    log_w("Auto Negotiation MUST be OFF for this setting to be applied");
+  }
+  _link_speed = speed;
+  return true;
+}
+
+// void ETHClass::getMac(uint8_t* mac)
+// {
+//     if(_eth_handle != NULL && mac != NULL){
+//         esp_eth_ioctl(_eth_handle, ETH_CMD_G_MAC_ADDR, mac);
+//     }
+// }
+
+size_t ETHClass::printDriverInfo(Print &out) const {
+  size_t bytes = 0;
+  bytes += out.print(",");
+  bytes += out.print(linkSpeed());
+  bytes += out.print("M");
+  if (fullDuplex()) {
+    bytes += out.print(",FULL_DUPLEX");
+  }
+  if (autoNegotiation()) {
+    bytes += out.print(",AUTO");
+  }
+  bytes += out.printf(",ADDR:0x%lX", phyAddr());
+  return bytes;
+}
+
+ETHClass ETH;
+
+#endif /* CONFIG_ETH_ENABLED */
diff --git a/libraries/Ethernet/src/ETH.h b/libraries/Ethernet/src/ETH.h
new file mode 100644
index 00000000000..c52aac6ec6f
--- /dev/null
+++ b/libraries/Ethernet/src/ETH.h
@@ -0,0 +1,274 @@
+/*
+ ETH.h - espre ETH PHY support.
+ Based on WiFi.h from Ardiono WiFi shield library.
+ Copyright (c) 2011-2014 Arduino.  All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include "sdkconfig.h"
+#if CONFIG_ETH_ENABLED
+
+#ifndef _ETH_H_
+#define _ETH_H_
+#include "esp_idf_version.h"
+
+//
+// Example configurations for pins_arduino.h to allow starting with ETH.begin();
+//
+
+// // Example RMII LAN8720 (Olimex, etc.)
+// #define ETH_PHY_TYPE        ETH_PHY_LAN8720
+// #define ETH_PHY_ADDR         0
+// #define ETH_PHY_MDC         23
+// #define ETH_PHY_MDIO        18
+// #define ETH_PHY_POWER       -1
+// #define ETH_CLK_MODE        ETH_CLOCK_GPIO0_IN
+
+// // Example RMII ESP32_Ethernet_V4
+// #define ETH_PHY_TYPE        ETH_PHY_TLK110
+// #define ETH_PHY_ADDR         1
+// #define ETH_PHY_MDC         23
+// #define ETH_PHY_MDIO        18
+// #define ETH_PHY_POWER       -1
+// #define ETH_CLK_MODE        ETH_CLOCK_GPIO0_OUT
+
+// // Example SPI using ESP-IDF's driver
+// #define ETH_PHY_TYPE        ETH_PHY_W5500
+// #define ETH_PHY_ADDR         1
+// #define ETH_PHY_CS          15
+// #define ETH_PHY_IRQ          4
+// #define ETH_PHY_RST          5
+// #define ETH_PHY_SPI_HOST    SPI2_HOST
+// #define ETH_PHY_SPI_SCK     14
+// #define ETH_PHY_SPI_MISO    12
+// #define ETH_PHY_SPI_MOSI    13
+
+// // Example SPI using Arduino's driver
+// #define ETH_PHY_TYPE        ETH_PHY_W5500
+// #define ETH_PHY_ADDR         1
+// #define ETH_PHY_CS          15
+// #define ETH_PHY_IRQ          4
+// #define ETH_PHY_RST          5
+// #define ETH_PHY_SPI         SPI
+
+// This will be uncommented once custom SPI support is available in ESP-IDF
+#define ETH_SPI_SUPPORTS_CUSTOM 1
+#define ETH_SPI_SUPPORTS_NO_IRQ 1
+
+#include "Network.h"
+
+#if ETH_SPI_SUPPORTS_CUSTOM
+#include "SPI.h"
+#endif
+#include "esp_system.h"
+#include "esp_eth.h"
+#include "esp_netif.h"
+
+#if CONFIG_ETH_USE_ESP32_EMAC
+#define ETH_PHY_IP101 ETH_PHY_TLK110
+#if CONFIG_IDF_TARGET_ESP32
+typedef enum {
+  ETH_CLOCK_GPIO0_IN,
+  ETH_CLOCK_GPIO0_OUT,
+  ETH_CLOCK_GPIO16_OUT,
+  ETH_CLOCK_GPIO17_OUT
+} eth_clock_mode_t;
+//Dedicated GPIOs for RMII
+#define ETH_RMII_TX_EN  21
+#define ETH_RMII_TX0    19
+#define ETH_RMII_TX1    22
+#define ETH_RMII_RX0    25
+#define ETH_RMII_RX1_EN 26
+#define ETH_RMII_CRS_DV 27
+#elif CONFIG_IDF_TARGET_ESP32P4
+typedef emac_rmii_clock_mode_t eth_clock_mode_t;
+#include "pins_arduino.h"
+#ifndef ETH_RMII_TX_EN
+#define ETH_RMII_TX_EN 49
+#endif
+#ifndef ETH_RMII_TX0
+#define ETH_RMII_TX0 34
+#endif
+#ifndef ETH_RMII_TX1
+#define ETH_RMII_TX1 35
+#endif
+#ifndef ETH_RMII_RX0
+#define ETH_RMII_RX0 29
+#endif
+#ifndef ETH_RMII_RX1_EN
+#define ETH_RMII_RX1_EN 30
+#endif
+#ifndef ETH_RMII_CRS_DV
+#define ETH_RMII_CRS_DV 28
+#endif
+#ifndef ETH_RMII_CLK
+#define ETH_RMII_CLK 50
+#endif
+#endif
+#endif /* CONFIG_ETH_USE_ESP32_EMAC */
+
+#ifndef ETH_PHY_SPI_FREQ_MHZ
+#define ETH_PHY_SPI_FREQ_MHZ 20
+#endif /* ETH_PHY_SPI_FREQ_MHZ */
+
+#define ETH_PHY_ADDR_AUTO ESP_ETH_PHY_ADDR_AUTO
+
+typedef enum {
+#if CONFIG_ETH_USE_ESP32_EMAC
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
+  ETH_PHY_GENERIC,
+#define ETH_PHY_JL1101 ETH_PHY_GENERIC
+#endif
+  ETH_PHY_LAN8720,
+  ETH_PHY_TLK110,
+  ETH_PHY_RTL8201,
+  ETH_PHY_DP83848,
+  ETH_PHY_KSZ8041,
+  ETH_PHY_KSZ8081,
+#endif /* CONFIG_ETH_USE_ESP32_EMAC */
+#if CONFIG_ETH_SPI_ETHERNET_DM9051
+  ETH_PHY_DM9051,
+#endif
+#if CONFIG_ETH_SPI_ETHERNET_W5500
+  ETH_PHY_W5500,
+#endif
+#if CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL
+  ETH_PHY_KSZ8851,
+#endif
+  ETH_PHY_MAX
+} eth_phy_type_t;
+
+class ETHClass : public NetworkInterface {
+public:
+  ETHClass(uint8_t eth_index = 0);
+  ~ETHClass();
+
+#if CONFIG_ETH_USE_ESP32_EMAC
+  bool begin(eth_phy_type_t type, int32_t phy_addr, int mdc, int mdio, int power, eth_clock_mode_t clk_mode);
+#endif /* CONFIG_ETH_USE_ESP32_EMAC */
+#if ETH_SPI_SUPPORTS_CUSTOM
+  bool begin(eth_phy_type_t type, int32_t phy_addr, int cs, int irq, int rst, SPIClass &spi, uint8_t spi_freq_mhz = ETH_PHY_SPI_FREQ_MHZ);
+#endif
+  bool begin(
+    eth_phy_type_t type, int32_t phy_addr, int cs, int irq, int rst, spi_host_device_t spi_host, int sck = -1, int miso = -1, int mosi = -1,
+    uint8_t spi_freq_mhz = ETH_PHY_SPI_FREQ_MHZ
+  );
+
+  bool begin() {
+#if defined(ETH_PHY_TYPE) && defined(ETH_PHY_ADDR)
+#if defined(CONFIG_ETH_USE_ESP32_EMAC) && defined(ETH_PHY_POWER) && defined(ETH_PHY_MDC) && defined(ETH_PHY_MDIO) && defined(ETH_CLK_MODE)
+    return begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_MDC, ETH_PHY_MDIO, ETH_PHY_POWER, ETH_CLK_MODE);
+#elif defined(ETH_PHY_CS) && defined(ETH_PHY_IRQ) && defined(ETH_PHY_RST)
+#if ETH_SPI_SUPPORTS_CUSTOM && defined(ETH_PHY_SPI)
+    return begin(ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_CS, ETH_PHY_IRQ, ETH_PHY_RST, ETH_PHY_SPI, ETH_PHY_SPI_FREQ_MHZ);
+#elif defined(ETH_PHY_SPI_HOST) && defined(ETH_PHY_SPI_SCK) && defined(ETH_PHY_SPI_MISO) && defined(ETH_PHY_SPI_MOSI)
+    return begin(
+      ETH_PHY_TYPE, ETH_PHY_ADDR, ETH_PHY_CS, ETH_PHY_IRQ, ETH_PHY_RST, ETH_PHY_SPI_HOST, ETH_PHY_SPI_SCK, ETH_PHY_SPI_MISO, ETH_PHY_SPI_MOSI,
+      ETH_PHY_SPI_FREQ_MHZ
+    );
+#endif
+#endif
+#endif
+    return false;
+  }
+
+  void end();
+
+  // This function must be called before `begin()`
+  void setTaskStackSize(size_t size);
+
+  // ETH Handle APIs
+  bool fullDuplex() const;
+  bool setFullDuplex(bool on);
+
+  uint16_t linkSpeed() const;
+  bool setLinkSpeed(uint16_t speed);  //10 or 100
+
+  bool autoNegotiation() const;
+  bool setAutoNegotiation(bool on);
+
+  uint32_t phyAddr() const;
+
+  esp_eth_handle_t handle() const;
+
+#if ETH_SPI_SUPPORTS_CUSTOM
+  static esp_err_t _eth_spi_read(void *ctx, uint32_t cmd, uint32_t addr, void *data, uint32_t data_len);
+  static esp_err_t _eth_spi_write(void *ctx, uint32_t cmd, uint32_t addr, const void *data, uint32_t data_len);
+#endif
+
+protected:
+#if ETH_SPI_SUPPORTS_CUSTOM
+  esp_err_t eth_spi_read(uint32_t cmd, uint32_t addr, void *data, uint32_t data_len);
+  esp_err_t eth_spi_write(uint32_t cmd, uint32_t addr, const void *data, uint32_t data_len);
+#endif
+
+  // void getMac(uint8_t* mac);
+  size_t printDriverInfo(Print &out) const;
+  // static void eth_event_handler(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data);
+
+public:
+  void _onEthEvent(int32_t event_id, void *event_data);
+
+private:
+  esp_eth_handle_t _eth_handle;
+  uint8_t _eth_index;
+  eth_phy_type_t _phy_type;
+  esp_eth_netif_glue_handle_t _glue_handle;
+  esp_eth_mac_t *_mac;
+  esp_eth_phy_t *_phy;
+  bool _eth_started;
+  uint16_t _link_speed;
+  bool _full_duplex;
+  bool _auto_negotiation;
+#if ETH_SPI_SUPPORTS_CUSTOM
+  SPIClass *_spi;
+  char _cs_str[10];
+#endif
+  uint8_t _spi_freq_mhz;
+  int8_t _pin_cs;
+  int8_t _pin_irq;
+  int8_t _pin_rst;
+  int8_t _pin_sck;
+  int8_t _pin_miso;
+  int8_t _pin_mosi;
+#if CONFIG_ETH_USE_ESP32_EMAC
+  int8_t _pin_mcd;
+  int8_t _pin_mdio;
+  int8_t _pin_power;
+  int8_t _pin_rmii_clock;
+#endif /* CONFIG_ETH_USE_ESP32_EMAC */
+  size_t _task_stack_size;
+  network_event_handle_t _eth_connected_event_handle;
+
+  static bool ethDetachBus(void *bus_pointer);
+  bool beginSPI(
+    eth_phy_type_t type, int32_t phy_addr, uint8_t *mac_addr, int cs, int irq, int rst,
+#if ETH_SPI_SUPPORTS_CUSTOM
+    SPIClass *spi,
+#endif
+    int sck, int miso, int mosi, spi_host_device_t spi_host, uint8_t spi_freq_mhz
+  );
+  bool _setFullDuplex(bool on);
+  bool _setLinkSpeed(uint16_t speed);
+  bool _setAutoNegotiation(bool on);
+
+  friend class EthernetClass;  // to access beginSPI
+};
+
+extern ETHClass ETH;
+
+#endif /* _ETH_H_ */
+#endif /* CONFIG_ETH_ENABLED */
diff --git a/libraries/FFat/examples/FFat_Test/FFat_Test.ino b/libraries/FFat/examples/FFat_Test/FFat_Test.ino
index 26a0bcac3bd..e12ba459d28 100644
--- a/libraries/FFat/examples/FFat_Test/FFat_Test.ino
+++ b/libraries/FFat/examples/FFat_Test/FFat_Test.ino
@@ -8,181 +8,181 @@
 // You only need to format FFat the first time you run a test
 #define FORMAT_FFAT true
 
-void listDir(fs::FS &fs, const char * dirname, uint8_t levels){
-    Serial.printf("Listing directory: %s\r\n", dirname);
-
-    File root = fs.open(dirname);
-    if(!root){
-        Serial.println("- failed to open directory");
-        return;
-    }
-    if(!root.isDirectory()){
-        Serial.println(" - not a directory");
-        return;
-    }
-
-    File file = root.openNextFile();
-    while(file){
-        if(file.isDirectory()){
-            Serial.print("  DIR : ");
-            Serial.println(file.name());
-            if(levels){
-                listDir(fs, file.name(), levels -1);
-            }
-        } else {
-            Serial.print("  FILE: ");
-            Serial.print(file.name());
-            Serial.print("\tSIZE: ");
-            Serial.println(file.size());
-        }
-        file = root.openNextFile();
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\r\n", dirname);
+
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("- failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println(" - not a directory");
+    return;
+  }
+
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.println(file.name());
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
+    } else {
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("\tSIZE: ");
+      Serial.println(file.size());
     }
+    file = root.openNextFile();
+  }
 }
 
-void readFile(fs::FS &fs, const char * path){
-    Serial.printf("Reading file: %s\r\n", path);
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\r\n", path);
 
-    File file = fs.open(path);
-    if(!file || file.isDirectory()){
-        Serial.println("- failed to open file for reading");
-        return;
-    }
+  File file = fs.open(path);
+  if (!file || file.isDirectory()) {
+    Serial.println("- failed to open file for reading");
+    return;
+  }
 
-    Serial.println("- read from file:");
-    while(file.available()){
-        Serial.write(file.read());
-    }
-    file.close();
+  Serial.println("- read from file:");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
+  file.close();
 }
 
-void writeFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Writing file: %s\r\n", path);
-
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("- failed to open file for writing");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("- file written");
-    } else {
-        Serial.println("- write failed");
-    }
-    file.close();
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\r\n", path);
+
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("- failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("- file written");
+  } else {
+    Serial.println("- write failed");
+  }
+  file.close();
 }
 
-void appendFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Appending to file: %s\r\n", path);
-
-    File file = fs.open(path, FILE_APPEND);
-    if(!file){
-        Serial.println("- failed to open file for appending");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("- message appended");
-    } else {
-        Serial.println("- append failed");
-    }
-    file.close();
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\r\n", path);
+
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("- failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("- message appended");
+  } else {
+    Serial.println("- append failed");
+  }
+  file.close();
 }
 
-void renameFile(fs::FS &fs, const char * path1, const char * path2){
-    Serial.printf("Renaming file %s to %s\r\n", path1, path2);
-    if (fs.rename(path1, path2)) {
-        Serial.println("- file renamed");
-    } else {
-        Serial.println("- rename failed");
-    }
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\r\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("- file renamed");
+  } else {
+    Serial.println("- rename failed");
+  }
 }
 
-void deleteFile(fs::FS &fs, const char * path){
-    Serial.printf("Deleting file: %s\r\n", path);
-    if(fs.remove(path)){
-        Serial.println("- file deleted");
-    } else {
-        Serial.println("- delete failed");
-    }
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\r\n", path);
+  if (fs.remove(path)) {
+    Serial.println("- file deleted");
+  } else {
+    Serial.println("- delete failed");
+  }
 }
 
-void testFileIO(fs::FS &fs, const char * path){
-    Serial.printf("Testing file I/O with %s\r\n", path);
-
-    static uint8_t buf[512];
-    size_t len = 0;
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("- failed to open file for writing");
-        return;
+void testFileIO(fs::FS &fs, const char *path) {
+  Serial.printf("Testing file I/O with %s\r\n", path);
+
+  static uint8_t buf[512];
+  size_t len = 0;
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("- failed to open file for writing");
+    return;
+  }
+
+  size_t i;
+  Serial.print("- writing");
+  uint32_t start = millis();
+  for (i = 0; i < 2048; i++) {
+    if ((i & 0x001F) == 0x001F) {
+      Serial.print(".");
     }
-
-    size_t i;
-    Serial.print("- writing" );
-    uint32_t start = millis();
-    for(i=0; i<2048; i++){
-        if ((i & 0x001F) == 0x001F){
-          Serial.print(".");
-        }
-        file.write(buf, 512);
+    file.write(buf, 512);
+  }
+  Serial.println("");
+  uint32_t end = millis() - start;
+  Serial.printf(" - %u bytes written in %lu ms\r\n", 2048 * 512, end);
+  file.close();
+
+  file = fs.open(path);
+  start = millis();
+  end = start;
+  i = 0;
+  if (file && !file.isDirectory()) {
+    len = file.size();
+    size_t flen = len;
+    start = millis();
+    Serial.print("- reading");
+    while (len) {
+      size_t toRead = len;
+      if (toRead > 512) {
+        toRead = 512;
+      }
+      file.read(buf, toRead);
+      if ((i++ & 0x001F) == 0x001F) {
+        Serial.print(".");
+      }
+      len -= toRead;
     }
     Serial.println("");
-    uint32_t end = millis() - start;
-    Serial.printf(" - %u bytes written in %u ms\r\n", 2048 * 512, end);
+    end = millis() - start;
+    Serial.printf("- %u bytes read in %lu ms\r\n", flen, end);
     file.close();
-
-    file = fs.open(path);
-    start = millis();
-    end = start;
-    i = 0;
-    if(file && !file.isDirectory()){
-        len = file.size();
-        size_t flen = len;
-        start = millis();
-        Serial.print("- reading" );
-        while(len){
-            size_t toRead = len;
-            if(toRead > 512){
-                toRead = 512;
-            }
-            file.read(buf, toRead);
-            if ((i++ & 0x001F) == 0x001F){
-              Serial.print(".");
-            }
-            len -= toRead;
-        }
-        Serial.println("");
-        end = millis() - start;
-        Serial.printf("- %u bytes read in %u ms\r\n", flen, end);
-        file.close();
-    } else {
-        Serial.println("- failed to open file for reading");
-    }
+  } else {
+    Serial.println("- failed to open file for reading");
+  }
 }
 
-void setup(){
-    Serial.begin(115200);
-    Serial.setDebugOutput(true);
-    if (FORMAT_FFAT) FFat.format();
-    if(!FFat.begin()){
-        Serial.println("FFat Mount Failed");
-        return;
-    }
-
-    Serial.printf("Total space: %10u\n", FFat.totalBytes());
-    Serial.printf("Free space: %10u\n", FFat.freeBytes());
-    listDir(FFat, "/", 0);
-    writeFile(FFat, "/hello.txt", "Hello ");
-    appendFile(FFat, "/hello.txt", "World!\r\n");
-    readFile(FFat, "/hello.txt");
-    renameFile(FFat, "/hello.txt", "/foo.txt");
-    readFile(FFat, "/foo.txt");
-    deleteFile(FFat, "/foo.txt");
-    testFileIO(FFat, "/test.txt");
-    Serial.printf("Free space: %10u\n", FFat.freeBytes());
-    deleteFile(FFat, "/test.txt");
-    Serial.println( "Test complete" );
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+  if (FORMAT_FFAT) {
+    FFat.format();
+  }
+  if (!FFat.begin()) {
+    Serial.println("FFat Mount Failed");
+    return;
+  }
+
+  Serial.printf("Total space: %10u\n", FFat.totalBytes());
+  Serial.printf("Free space: %10u\n", FFat.freeBytes());
+  listDir(FFat, "/", 0);
+  writeFile(FFat, "/hello.txt", "Hello ");
+  appendFile(FFat, "/hello.txt", "World!\r\n");
+  readFile(FFat, "/hello.txt");
+  renameFile(FFat, "/hello.txt", "/foo.txt");
+  readFile(FFat, "/foo.txt");
+  deleteFile(FFat, "/foo.txt");
+  testFileIO(FFat, "/test.txt");
+  Serial.printf("Free space: %10u\n", FFat.freeBytes());
+  deleteFile(FFat, "/test.txt");
+  Serial.println("Test complete");
 }
 
-void loop(){
-
-}
+void loop() {}
diff --git a/libraries/FFat/examples/FFat_time/FFat_time.ino b/libraries/FFat/examples/FFat_time/FFat_time.ino
index 1e3794514c5..392647c9923 100644
--- a/libraries/FFat/examples/FFat_time/FFat_time.ino
+++ b/libraries/FFat/examples/FFat_time/FFat_time.ino
@@ -1,177 +1,182 @@
 #include "FS.h"
 #include "FFat.h"
-#include <time.h> 
+#include <time.h>
 #include <WiFi.h>
 
-const char* ssid     = "your-ssid";
-const char* password = "your-password";
+const char *ssid = "your-ssid";
+const char *password = "your-password";
 
-long timezone = 1; 
+long timezone = 1;
 byte daysavetime = 1;
 
-void listDir(fs::FS &fs, const char * dirname, uint8_t levels){
-    Serial.printf("Listing directory: %s\n", dirname);
-
-    File root = fs.open(dirname);
-    if(!root){
-        Serial.println("Failed to open directory");
-        return;
-    }
-    if(!root.isDirectory()){
-        Serial.println("Not a directory");
-        return;
-    }
-
-    File file = root.openNextFile();
-    while(file){
-        if(file.isDirectory()){
-            Serial.print("  DIR : ");
-            Serial.print (file.name());
-            time_t t= file.getLastWrite();
-            struct tm * tmstruct = localtime(&t);
-            Serial.printf("  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct->tm_year)+1900,( tmstruct->tm_mon)+1, tmstruct->tm_mday,tmstruct->tm_hour , tmstruct->tm_min, tmstruct->tm_sec);
-            if(levels){
-                listDir(fs, file.name(), levels -1);
-            }
-        } else {
-            Serial.print("  FILE: ");
-            Serial.print(file.name());
-            Serial.print("  SIZE: ");
-            Serial.print(file.size());
-            time_t t= file.getLastWrite();
-            struct tm * tmstruct = localtime(&t);
-            Serial.printf("  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct->tm_year)+1900,( tmstruct->tm_mon)+1, tmstruct->tm_mday,tmstruct->tm_hour , tmstruct->tm_min, tmstruct->tm_sec);
-        }
-        file = root.openNextFile();
-    }
-}
-
-void createDir(fs::FS &fs, const char * path){
-    Serial.printf("Creating Dir: %s\n", path);
-    if(fs.mkdir(path)){
-        Serial.println("Dir created");
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\n", dirname);
+
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("Failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println("Not a directory");
+    return;
+  }
+
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.print(file.name());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
     } else {
-        Serial.println("mkdir failed");
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("  SIZE: ");
+      Serial.print(file.size());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
     }
+    file = root.openNextFile();
+  }
 }
 
-void removeDir(fs::FS &fs, const char * path){
-    Serial.printf("Removing Dir: %s\n", path);
-    if(fs.rmdir(path)){
-        Serial.println("Dir removed");
-    } else {
-        Serial.println("rmdir failed");
-    }
+void createDir(fs::FS &fs, const char *path) {
+  Serial.printf("Creating Dir: %s\n", path);
+  if (fs.mkdir(path)) {
+    Serial.println("Dir created");
+  } else {
+    Serial.println("mkdir failed");
+  }
 }
 
-void readFile(fs::FS &fs, const char * path){
-    Serial.printf("Reading file: %s\n", path);
-
-    File file = fs.open(path);
-    if(!file){
-        Serial.println("Failed to open file for reading");
-        return;
-    }
-
-    Serial.print("Read from file: ");
-    while(file.available()){
-        Serial.write(file.read());
-    }
-    file.close();
+void removeDir(fs::FS &fs, const char *path) {
+  Serial.printf("Removing Dir: %s\n", path);
+  if (fs.rmdir(path)) {
+    Serial.println("Dir removed");
+  } else {
+    Serial.println("rmdir failed");
+  }
 }
 
-void writeFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Writing file: %s\n", path);
-
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("Failed to open file for writing");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("File written");
-    } else {
-        Serial.println("Write failed");
-    }
-    file.close();
-}
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\n", path);
 
-void appendFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Appending to file: %s\n", path);
+  File file = fs.open(path);
+  if (!file) {
+    Serial.println("Failed to open file for reading");
+    return;
+  }
 
-    File file = fs.open(path, FILE_APPEND);
-    if(!file){
-        Serial.println("Failed to open file for appending");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("Message appended");
-    } else {
-        Serial.println("Append failed");
-    }
-    file.close();
+  Serial.print("Read from file: ");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
+  file.close();
 }
 
-void renameFile(fs::FS &fs, const char * path1, const char * path2){
-    Serial.printf("Renaming file %s to %s\n", path1, path2);
-    if (fs.rename(path1, path2)) {
-        Serial.println("File renamed");
-    } else {
-        Serial.println("Rename failed");
-    }
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\n", path);
+
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("File written");
+  } else {
+    Serial.println("Write failed");
+  }
+  file.close();
 }
 
-void deleteFile(fs::FS &fs, const char * path){
-    Serial.printf("Deleting file: %s\n", path);
-    if(fs.remove(path)){
-        Serial.println("File deleted");
-    } else {
-        Serial.println("Delete failed");
-    }
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\n", path);
+
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("Failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("Message appended");
+  } else {
+    Serial.println("Append failed");
+  }
+  file.close();
 }
 
-void setup(){
-    Serial.begin(115200);
-    // We start by connecting to a WiFi network
-    Serial.println();
-    Serial.println();
-    Serial.print("Connecting to ");
-    Serial.println(ssid);
-
-    WiFi.begin(ssid, password);
-
-    while (WiFi.status() != WL_CONNECTED) {
-        delay(500);
-        Serial.print(".");
-    }
-    Serial.println("WiFi connected");
-    Serial.println("IP address: ");
-    Serial.println(WiFi.localIP());
-    Serial.println("Contacting Time Server");
-	configTime(3600*timezone, daysavetime*3600, "time.nist.gov", "0.pool.ntp.org", "1.pool.ntp.org");
-	struct tm tmstruct ;
-    delay(2000);
-    tmstruct.tm_year = 0;
-    getLocalTime(&tmstruct, 5000);
-	Serial.printf("\nNow is : %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct.tm_year)+1900,( tmstruct.tm_mon)+1, tmstruct.tm_mday,tmstruct.tm_hour , tmstruct.tm_min, tmstruct.tm_sec);
-    Serial.println("");
-    
-    if(!FFat.begin(true)){
-        Serial.println("FFat Mount Failed");
-        return;
-    }
-
-    listDir(FFat, "/", 0);
-    removeDir(FFat, "/mydir");
-    createDir(FFat, "/mydir");
-    deleteFile(FFat, "/hello.txt");
-    writeFile(FFat, "/hello.txt", "Hello ");
-    appendFile(FFat, "/hello.txt", "World!\n");
-	listDir(FFat, "/", 0);
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("File renamed");
+  } else {
+    Serial.println("Rename failed");
+  }
 }
 
-void loop(){
-
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\n", path);
+  if (fs.remove(path)) {
+    Serial.println("File deleted");
+  } else {
+    Serial.println("Delete failed");
+  }
 }
 
+void setup() {
+  Serial.begin(115200);
+  // We start by connecting to a WiFi network
+  Serial.println();
+  Serial.println();
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+
+  WiFi.begin(ssid, password);
+
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  Serial.println("Contacting Time Server");
+  configTime(3600 * timezone, daysavetime * 3600, "time.nist.gov", "0.pool.ntp.org", "1.pool.ntp.org");
+  struct tm tmstruct;
+  delay(2000);
+  tmstruct.tm_year = 0;
+  getLocalTime(&tmstruct, 5000);
+  Serial.printf(
+    "\nNow is : %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct.tm_year) + 1900, (tmstruct.tm_mon) + 1, tmstruct.tm_mday, tmstruct.tm_hour, tmstruct.tm_min,
+    tmstruct.tm_sec
+  );
+  Serial.println("");
+
+  if (!FFat.begin(true)) {
+    Serial.println("FFat Mount Failed");
+    return;
+  }
+
+  listDir(FFat, "/", 0);
+  removeDir(FFat, "/mydir");
+  createDir(FFat, "/mydir");
+  deleteFile(FFat, "/hello.txt");
+  writeFile(FFat, "/hello.txt", "Hello ");
+  appendFile(FFat, "/hello.txt", "World!\n");
+  listDir(FFat, "/", 0);
+}
 
+void loop() {}
diff --git a/libraries/FFat/examples/FFat_time/ci.json b/libraries/FFat/examples/FFat_time/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/FFat/examples/FFat_time/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/FFat/library.properties b/libraries/FFat/library.properties
index aebca39d950..35940fd5472 100644
--- a/libraries/FFat/library.properties
+++ b/libraries/FFat/library.properties
@@ -1,5 +1,5 @@
 name=FFat
-version=1.0
+version=3.2.0
 author=Hristo Gochkov, Ivan Grokhtkov, Larry Bernstone
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=ESP32 FAT on Flash File System
diff --git a/libraries/FFat/src/FFat.cpp b/libraries/FFat/src/FFat.cpp
index 6441dfca4e4..4a2274b2fdb 100644
--- a/libraries/FFat/src/FFat.cpp
+++ b/libraries/FFat/src/FFat.cpp
@@ -23,159 +23,137 @@ extern "C" {
 
 using namespace fs;
 
-F_Fat::F_Fat(FSImplPtr impl)
-    : FS(impl)
-{}
-
-const esp_partition_t *check_ffat_partition(const char* label)
-{
-    const esp_partition_t* ck_part = esp_partition_find_first(
-       ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, label);
-    if (!ck_part) {
-        log_e("No FAT partition found with label %s", label);
-        return NULL;
-    }
-    return ck_part;
+F_Fat::F_Fat(FSImplPtr impl) : FS(impl) {}
+
+const esp_partition_t *check_ffat_partition(const char *label) {
+  const esp_partition_t *ck_part = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, label);
+  if (!ck_part) {
+    log_e("No FAT partition found with label %s", label);
+    return NULL;
+  }
+  return ck_part;
 }
 
-bool F_Fat::begin(bool formatOnFail, const char * basePath, uint8_t maxOpenFiles, const char * partitionLabel)
-{
-    if(_wl_handle != WL_INVALID_HANDLE){
-        log_w("Already Mounted!");
-        return true;
-    }     
-
-    if (!check_ffat_partition(partitionLabel)){
-        log_e("No fat partition found on flash");
-        return false;
-    }
-
-    esp_vfs_fat_mount_config_t conf = {
-      .format_if_mount_failed = formatOnFail,
-      .max_files = maxOpenFiles,
-      .allocation_unit_size = CONFIG_WL_SECTOR_SIZE
-    };
-    esp_err_t err = esp_vfs_fat_spiflash_mount(basePath, partitionLabel, &conf, &_wl_handle);
-    if(err){
-        log_e("Mounting FFat partition failed! Error: %d", err);
-        esp_vfs_fat_spiflash_unmount(basePath, _wl_handle);
-        _wl_handle = WL_INVALID_HANDLE;
-        return false;
-    }
-    _impl->mountpoint(basePath);
+bool F_Fat::begin(bool formatOnFail, const char *basePath, uint8_t maxOpenFiles, const char *partitionLabel) {
+  if (_wl_handle != WL_INVALID_HANDLE) {
+    log_w("Already Mounted!");
     return true;
+  }
+
+  if (!check_ffat_partition(partitionLabel)) {
+    log_e("No fat partition found on flash");
+    return false;
+  }
+
+  esp_vfs_fat_mount_config_t conf = {
+    .format_if_mount_failed = formatOnFail,
+    .max_files = maxOpenFiles,
+    .allocation_unit_size = CONFIG_WL_SECTOR_SIZE,
+    .disk_status_check_enable = false,
+    .use_one_fat = false
+  };
+  esp_err_t err = esp_vfs_fat_spiflash_mount_rw_wl(basePath, partitionLabel, &conf, &_wl_handle);
+  if (err) {
+    log_e("Mounting FFat partition failed! Error: %d", err);
+    esp_vfs_fat_spiflash_unmount_rw_wl(basePath, _wl_handle);
+    _wl_handle = WL_INVALID_HANDLE;
+    return false;
+  }
+  _impl->mountpoint(basePath);
+  return true;
 }
 
-void F_Fat::end()
-{
-    if(_wl_handle != WL_INVALID_HANDLE){
-        esp_err_t err = esp_vfs_fat_spiflash_unmount(_impl->mountpoint(), _wl_handle);
-        if(err){
-            log_e("Unmounting FFat partition failed! Error: %d", err);
-            return;
-        }
-        _wl_handle = WL_INVALID_HANDLE;
-        _impl->mountpoint(NULL);
+void F_Fat::end() {
+  if (_wl_handle != WL_INVALID_HANDLE) {
+    esp_err_t err = esp_vfs_fat_spiflash_unmount_rw_wl(_impl->mountpoint(), _wl_handle);
+    if (err) {
+      log_e("Unmounting FFat partition failed! Error: %d", err);
+      return;
     }
+    _wl_handle = WL_INVALID_HANDLE;
+    _impl->mountpoint(NULL);
+  }
 }
 
-bool F_Fat::format(bool full_wipe, char* partitionLabel)
-{
-    esp_err_t result;
-    bool res = true;
-    if(_wl_handle != WL_INVALID_HANDLE){
-        log_w("Already Mounted!");
-        return false;
-    }
-    wl_handle_t temp_handle;
-// Attempt to mount to see if there is already data
-    const esp_partition_t *ffat_partition = check_ffat_partition(partitionLabel);
-    if (!ffat_partition){
-        log_w("No partition!");
-        return false;
-    } 
-    result = wl_mount(ffat_partition, &temp_handle);
-
-    if (result == ESP_OK) {
-// Wipe disk- quick just wipes the FAT. Full zeroes the whole disk
-        uint32_t wipe_size = full_wipe ? wl_size(temp_handle) : 16384;
-        wl_erase_range(temp_handle, 0, wipe_size);
-        wl_unmount(temp_handle);
-    } else {
-        res = false;
-        log_w("wl_mount failed!");
-    }
-// Now do a mount with format_if_fail (which it will)
-    esp_vfs_fat_mount_config_t conf = {
-      .format_if_mount_failed = true,
-      .max_files = 1,
-      .allocation_unit_size = CONFIG_WL_SECTOR_SIZE
-    };
-    result = esp_vfs_fat_spiflash_mount("/format_ffat", partitionLabel, &conf, &temp_handle);
-    esp_vfs_fat_spiflash_unmount("/format_ffat", temp_handle);
-    if (result != ESP_OK){
-        res = false;
-        log_w("esp_vfs_fat_spiflash_mount failed!");
-    }
-    return res;
+bool F_Fat::format(bool full_wipe, char *partitionLabel) {
+  esp_err_t result;
+  bool res = true;
+  if (_wl_handle != WL_INVALID_HANDLE) {
+    log_w("Already Mounted!");
+    return false;
+  }
+  wl_handle_t temp_handle;
+  // Attempt to mount to see if there is already data
+  const esp_partition_t *ffat_partition = check_ffat_partition(partitionLabel);
+  if (!ffat_partition) {
+    log_w("No partition!");
+    return false;
+  }
+  result = wl_mount(ffat_partition, &temp_handle);
+
+  if (result == ESP_OK) {
+    // Wipe disk- quick just wipes the FAT. Full zeroes the whole disk
+    uint32_t wipe_size = full_wipe ? wl_size(temp_handle) : 16384;
+    wl_erase_range(temp_handle, 0, wipe_size);
+    wl_unmount(temp_handle);
+  } else {
+    res = false;
+    log_w("wl_mount failed!");
+  }
+  // Now do a mount with format_if_fail (which it will)
+  esp_vfs_fat_mount_config_t conf = {
+    .format_if_mount_failed = true, .max_files = 1, .allocation_unit_size = CONFIG_WL_SECTOR_SIZE, .disk_status_check_enable = false, .use_one_fat = false
+  };
+  result = esp_vfs_fat_spiflash_mount_rw_wl("/format_ffat", partitionLabel, &conf, &temp_handle);
+  esp_vfs_fat_spiflash_unmount_rw_wl("/format_ffat", temp_handle);
+  if (result != ESP_OK) {
+    res = false;
+    log_w("esp_vfs_fat_spiflash_mount_rw_wl failed!");
+  }
+  return res;
 }
 
-size_t F_Fat::totalBytes()
-{
-    FATFS *fs;
-    DWORD free_clust, tot_sect, sect_size;
-
-    BYTE pdrv = ff_diskio_get_pdrv_wl(_wl_handle);
-    char drv[3] = {(char)(48+pdrv), ':', 0};
-    if ( f_getfree(drv, &free_clust, &fs) != FR_OK){
-        return 0;
-    }
-    tot_sect = (fs->n_fatent - 2) * fs->csize;
-    sect_size = CONFIG_WL_SECTOR_SIZE;
-    return tot_sect * sect_size;
+size_t F_Fat::totalBytes() {
+  FATFS *fs;
+  DWORD free_clust, tot_sect, sect_size;
+
+  BYTE pdrv = ff_diskio_get_pdrv_wl(_wl_handle);
+  char drv[3] = {(char)(48 + pdrv), ':', 0};
+  if (f_getfree(drv, &free_clust, &fs) != FR_OK) {
+    return 0;
+  }
+  tot_sect = (fs->n_fatent - 2) * fs->csize;
+  sect_size = CONFIG_WL_SECTOR_SIZE;
+  return tot_sect * sect_size;
 }
 
-size_t F_Fat::usedBytes()
-{
-    FATFS *fs;
-    DWORD free_clust, used_sect, sect_size;
-
-    BYTE pdrv = ff_diskio_get_pdrv_wl(_wl_handle);
-    char drv[3] = {(char)(48+pdrv), ':', 0};
-    if ( f_getfree(drv, &free_clust, &fs) != FR_OK){
-        return 0;
-    }
-    used_sect = (fs->n_fatent - 2 - free_clust) * fs->csize;
-    sect_size = CONFIG_WL_SECTOR_SIZE;
-    return used_sect * sect_size;
+size_t F_Fat::usedBytes() {
+  FATFS *fs;
+  DWORD free_clust, used_sect, sect_size;
+
+  BYTE pdrv = ff_diskio_get_pdrv_wl(_wl_handle);
+  char drv[3] = {(char)(48 + pdrv), ':', 0};
+  if (f_getfree(drv, &free_clust, &fs) != FR_OK) {
+    return 0;
+  }
+  used_sect = (fs->n_fatent - 2 - free_clust) * fs->csize;
+  sect_size = CONFIG_WL_SECTOR_SIZE;
+  return used_sect * sect_size;
 }
 
-size_t F_Fat::freeBytes()
-{
+size_t F_Fat::freeBytes() {
 
-    FATFS *fs;
-    DWORD free_clust, free_sect, sect_size;
+  FATFS *fs;
+  DWORD free_clust, free_sect, sect_size;
 
-    BYTE pdrv = ff_diskio_get_pdrv_wl(_wl_handle);
-    char drv[3] = {(char)(48+pdrv), ':', 0};
-    if ( f_getfree(drv, &free_clust, &fs) != FR_OK){
-        return 0;
-    }
-    free_sect = free_clust * fs->csize;
-    sect_size = CONFIG_WL_SECTOR_SIZE;
-    return free_sect * sect_size;
+  BYTE pdrv = ff_diskio_get_pdrv_wl(_wl_handle);
+  char drv[3] = {(char)(48 + pdrv), ':', 0};
+  if (f_getfree(drv, &free_clust, &fs) != FR_OK) {
+    return 0;
+  }
+  free_sect = free_clust * fs->csize;
+  sect_size = CONFIG_WL_SECTOR_SIZE;
+  return free_sect * sect_size;
 }
 
-bool F_Fat::exists(const char* path)
-{
-    File f = open(path, "r");
-    return (f == true) && !f.isDirectory();
-}
-
-bool F_Fat::exists(const String& path)
-{
-    return exists(path.c_str());
-}
-
-
 F_Fat FFat = F_Fat(FSImplPtr(new VFSImpl()));
diff --git a/libraries/FFat/src/FFat.h b/libraries/FFat/src/FFat.h
index ed20e23b294..3f700396777 100644
--- a/libraries/FFat/src/FFat.h
+++ b/libraries/FFat/src/FFat.h
@@ -17,31 +17,27 @@
 #include "FS.h"
 #include "wear_levelling.h"
 
-#define FFAT_WIPE_QUICK 0
-#define FFAT_WIPE_FULL 1
+#define FFAT_WIPE_QUICK      0
+#define FFAT_WIPE_FULL       1
 #define FFAT_PARTITION_LABEL "ffat"
 
-namespace fs
-{
+namespace fs {
 
-class F_Fat : public FS
-{
+class F_Fat : public FS {
 public:
-    F_Fat(FSImplPtr impl);
-    bool begin(bool formatOnFail=false, const char * basePath="/ffat", uint8_t maxOpenFiles=10, const char * partitionLabel = (char*)FFAT_PARTITION_LABEL);
-    bool format(bool full_wipe = FFAT_WIPE_QUICK, char* partitionLabel = (char*)FFAT_PARTITION_LABEL);
-    size_t totalBytes();
-    size_t usedBytes();
-    size_t freeBytes();
-    void end();
-    bool exists(const char* path);
-    bool exists(const String& path);
+  F_Fat(FSImplPtr impl);
+  bool begin(bool formatOnFail = false, const char *basePath = "/ffat", uint8_t maxOpenFiles = 10, const char *partitionLabel = (char *)FFAT_PARTITION_LABEL);
+  bool format(bool full_wipe = FFAT_WIPE_QUICK, char *partitionLabel = (char *)FFAT_PARTITION_LABEL);
+  size_t totalBytes();
+  size_t usedBytes();
+  size_t freeBytes();
+  void end();
 
 private:
-    wl_handle_t _wl_handle = WL_INVALID_HANDLE;
+  wl_handle_t _wl_handle = WL_INVALID_HANDLE;
 };
 
-}
+}  // namespace fs
 
 extern fs::F_Fat FFat;
 
diff --git a/libraries/FS/library.properties b/libraries/FS/library.properties
index fb35385ba24..07bd296bb83 100644
--- a/libraries/FS/library.properties
+++ b/libraries/FS/library.properties
@@ -1,5 +1,5 @@
 name=FS
-version=1.0
+version=3.2.0
 author=Hristo Gochkov, Ivan Grokhtkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=ESP32 File System
diff --git a/libraries/FS/src/FS.cpp b/libraries/FS/src/FS.cpp
index ab4f5d5289a..252fc3e3944 100644
--- a/libraries/FS/src/FS.cpp
+++ b/libraries/FS/src/FS.cpp
@@ -23,247 +23,258 @@
 
 using namespace fs;
 
-size_t File::write(uint8_t c)
-{
-    if (!_p) {
-        return 0;
-    }
+size_t File::write(uint8_t c) {
+  if (!*this) {
+    return 0;
+  }
 
-    return _p->write(&c, 1);
+  return _p->write(&c, 1);
 }
 
-time_t File::getLastWrite()
-{
-    if (!_p) {
-        return 0;
-    }
+time_t File::getLastWrite() {
+  if (!*this) {
+    return 0;
+  }
 
-    return _p->getLastWrite();
+  return _p->getLastWrite();
 }
 
-size_t File::write(const uint8_t *buf, size_t size)
-{
-    if (!_p) {
-        return 0;
-    }
+size_t File::write(const uint8_t *buf, size_t size) {
+  if (!*this) {
+    return 0;
+  }
 
-    return _p->write(buf, size);
+  return _p->write(buf, size);
 }
 
-int File::available()
-{
-    if (!_p) {
-        return false;
-    }
+int File::available() {
+  if (!*this) {
+    return false;
+  }
 
-    return _p->size() - _p->position();
+  return _p->size() - _p->position();
 }
 
-int File::read()
-{
-    if (!_p) {
-        return -1;
-    }
+int File::read() {
+  if (!*this) {
+    return -1;
+  }
 
-    uint8_t result;
-    if (_p->read(&result, 1) != 1) {
-        return -1;
-    }
+  uint8_t result;
+  if (_p->read(&result, 1) != 1) {
+    return -1;
+  }
 
-    return result;
+  return result;
 }
 
-size_t File::read(uint8_t* buf, size_t size)
-{
-    if (!_p) {
-        return -1;
-    }
+size_t File::read(uint8_t *buf, size_t size) {
+  if (!*this) {
+    return -1;
+  }
 
-    return _p->read(buf, size);
+  return _p->read(buf, size);
 }
 
-int File::peek()
-{
-    if (!_p) {
-        return -1;
-    }
+int File::peek() {
+  if (!*this) {
+    return -1;
+  }
 
-    size_t curPos = _p->position();
-    int result = read();
-    seek(curPos, SeekSet);
-    return result;
+  size_t curPos = _p->position();
+  int result = read();
+  seek(curPos, SeekSet);
+  return result;
 }
 
-void File::flush()
-{
-    if (!_p) {
-        return;
-    }
+void File::flush() {
+  if (!*this) {
+    return;
+  }
 
-    _p->flush();
+  _p->flush();
 }
 
-bool File::seek(uint32_t pos, SeekMode mode)
-{
-    if (!_p) {
-        return false;
-    }
+bool File::seek(uint32_t pos, SeekMode mode) {
+  if (!*this) {
+    return false;
+  }
 
-    return _p->seek(pos, mode);
+  return _p->seek(pos, mode);
 }
 
-size_t File::position() const
-{
-    if (!_p) {
-        return 0;
-    }
+size_t File::position() const {
+  if (!*this) {
+    return (size_t)-1;
+  }
 
-    return _p->position();
+  return _p->position();
 }
 
-size_t File::size() const
-{
-    if (!_p) {
-        return 0;
-    }
+size_t File::size() const {
+  if (!*this) {
+    return 0;
+  }
 
-    return _p->size();
+  return _p->size();
 }
 
-void File::close()
-{
-    if (_p) {
-        _p->close();
-        _p = nullptr;
-    }
+bool File::setBufferSize(size_t size) {
+  if (!*this) {
+    return 0;
+  }
+
+  return _p->setBufferSize(size);
+}
+
+void File::close() {
+  if (_p) {
+    _p->close();
+    _p = nullptr;
+  }
 }
 
-File::operator bool() const
-{
-    return !!_p;
+File::operator bool() const {
+  return _p != nullptr && *_p != false;
+}
+
+const char *File::path() const {
+  if (!*this) {
+    return nullptr;
+  }
+
+  return _p->path();
 }
 
-const char* File::name() const
-{
-    if (!_p) {
-        return nullptr;
-    }
+const char *File::name() const {
+  if (!*this) {
+    return nullptr;
+  }
 
-    return _p->name();
+  return _p->name();
 }
 
 //to implement
-boolean File::isDirectory(void)
-{
-    if (!_p) {
-        return false;
-    }
-    return _p->isDirectory();
+boolean File::isDirectory(void) {
+  if (!*this) {
+    return false;
+  }
+  return _p->isDirectory();
 }
 
-File File::openNextFile(const char* mode)
-{
-    if (!_p) {
-        return File();
-    }
-    return _p->openNextFile(mode);
+File File::openNextFile(const char *mode) {
+  if (!*this) {
+    return File();
+  }
+  return _p->openNextFile(mode);
 }
 
-void File::rewindDirectory(void)
-{
-    if (!_p) {
-        return;
-    }
-    _p->rewindDirectory();
+boolean File::seekDir(long position) {
+  if (!_p) {
+    return false;
+  }
+  return _p->seekDir(position);
 }
 
-File FS::open(const String& path, const char* mode)
-{
-    return open(path.c_str(), mode);
+String File::getNextFileName(void) {
+  if (!_p) {
+    return "";
+  }
+  return _p->getNextFileName();
 }
 
-File FS::open(const char* path, const char* mode)
-{
-    if (!_impl) {
-        return File();
-    }
+String File::getNextFileName(bool *isDir) {
+  if (!_p) {
+    return "";
+  }
+  return _p->getNextFileName(isDir);
+}
+
+void File::rewindDirectory(void) {
+  if (!*this) {
+    return;
+  }
+  _p->rewindDirectory();
+}
 
-    return File(_impl->open(path, mode));
+File FS::open(const String &path, const char *mode, const bool create) {
+  return open(path.c_str(), mode, create);
 }
 
-bool FS::exists(const char* path)
-{
-    if (!_impl) {
-        return false;
-    }
-    return _impl->exists(path);
+File FS::open(const char *path, const char *mode, const bool create) {
+  if (!_impl) {
+    return File();
+  }
+
+  return File(_impl->open(path, mode, create));
 }
 
-bool FS::exists(const String& path)
-{
-    return exists(path.c_str());
+bool FS::exists(const char *path) {
+  if (!_impl) {
+    return false;
+  }
+  return _impl->exists(path);
 }
 
-bool FS::remove(const char* path)
-{
-    if (!_impl) {
-        return false;
-    }
-    return _impl->remove(path);
+bool FS::exists(const String &path) {
+  return exists(path.c_str());
 }
 
-bool FS::remove(const String& path)
-{
-    return remove(path.c_str());
+bool FS::remove(const char *path) {
+  if (!_impl) {
+    return false;
+  }
+  return _impl->remove(path);
 }
 
-bool FS::rename(const char* pathFrom, const char* pathTo)
-{
-    if (!_impl) {
-        return false;
-    }
-    return _impl->rename(pathFrom, pathTo);
+bool FS::remove(const String &path) {
+  return remove(path.c_str());
 }
 
-bool FS::rename(const String& pathFrom, const String& pathTo)
-{
-    return rename(pathFrom.c_str(), pathTo.c_str());
+bool FS::rename(const char *pathFrom, const char *pathTo) {
+  if (!_impl) {
+    return false;
+  }
+  return _impl->rename(pathFrom, pathTo);
 }
 
+bool FS::rename(const String &pathFrom, const String &pathTo) {
+  return rename(pathFrom.c_str(), pathTo.c_str());
+}
 
-bool FS::mkdir(const char *path)
-{
-    if (!_impl) {
-        return false;
-    }
-    return _impl->mkdir(path);
+bool FS::mkdir(const char *path) {
+  if (!_impl) {
+    return false;
+  }
+  return _impl->mkdir(path);
 }
 
-bool FS::mkdir(const String &path)
-{
-    return mkdir(path.c_str());
+bool FS::mkdir(const String &path) {
+  return mkdir(path.c_str());
 }
 
-bool FS::rmdir(const char *path)
-{
-    if (!_impl) {
-        return false;
-    }
-    return _impl->rmdir(path);
+bool FS::rmdir(const char *path) {
+  if (!_impl) {
+    return false;
+  }
+  return _impl->rmdir(path);
 }
 
-bool FS::rmdir(const String &path)
-{
-    return rmdir(path.c_str());
+bool FS::rmdir(const String &path) {
+  return rmdir(path.c_str());
 }
 
+const char *FS::mountpoint() {
+  if (!_impl) {
+    return NULL;
+  }
+  return _impl->mountpoint();
+}
 
-void FSImpl::mountpoint(const char * mp)
-{
-    _mountpoint = mp;
+void FSImpl::mountpoint(const char *mp) {
+  _mountpoint = mp;
 }
 
-const char * FSImpl::mountpoint()
-{
-    return _mountpoint;
+const char *FSImpl::mountpoint() {
+  return _mountpoint;
 }
diff --git a/libraries/FS/src/FS.h b/libraries/FS/src/FS.h
index d63fc5da305..6572ad987b3 100644
--- a/libraries/FS/src/FS.h
+++ b/libraries/FS/src/FS.h
@@ -24,12 +24,11 @@
 #include <memory>
 #include <Arduino.h>
 
-namespace fs
-{
+namespace fs {
 
-#define FILE_READ       "r"
-#define FILE_WRITE      "w"
-#define FILE_APPEND     "a"
+#define FILE_READ   "r"
+#define FILE_WRITE  "w"
+#define FILE_APPEND "a"
 
 class File;
 
@@ -39,87 +38,89 @@ class FSImpl;
 typedef std::shared_ptr<FSImpl> FSImplPtr;
 
 enum SeekMode {
-    SeekSet = 0,
-    SeekCur = 1,
-    SeekEnd = 2
+  SeekSet = 0,
+  SeekCur = 1,
+  SeekEnd = 2
 };
 
-class File : public Stream
-{
+class File : public Stream {
 public:
-    File(FileImplPtr p = FileImplPtr()) : _p(p) {
-        _timeout = 0;
-    }
-
-    size_t write(uint8_t) override;
-    size_t write(const uint8_t *buf, size_t size) override;
-    int available() override;
-    int read() override;
-    int peek() override;
-    void flush() override;
-    size_t read(uint8_t* buf, size_t size);
-    size_t readBytes(char *buffer, size_t length)
-    {
-        return read((uint8_t*)buffer, length);
-    }
-
-    bool seek(uint32_t pos, SeekMode mode);
-    bool seek(uint32_t pos)
-    {
-        return seek(pos, SeekSet);
-    }
-    size_t position() const;
-    size_t size() const;
-    void close();
-    operator bool() const;
-    time_t getLastWrite();
-    const char* name() const;
-
-    boolean isDirectory(void);
-    File openNextFile(const char* mode = FILE_READ);
-    void rewindDirectory(void);
+  File(FileImplPtr p = FileImplPtr()) : _p(p) {
+    _timeout = 0;
+  }
+
+  size_t write(uint8_t) override;
+  size_t write(const uint8_t *buf, size_t size) override;
+  int available() override;
+  int read() override;
+  int peek() override;
+  void flush() override;
+  size_t read(uint8_t *buf, size_t size);
+  size_t readBytes(char *buffer, size_t length) {
+    return read((uint8_t *)buffer, length);
+  }
+
+  bool seek(uint32_t pos, SeekMode mode);
+  bool seek(uint32_t pos) {
+    return seek(pos, SeekSet);
+  }
+  size_t position() const;  // returns (size_t)-1 on error
+  size_t size() const;
+  bool setBufferSize(size_t size);
+  void close();
+  operator bool() const;
+  time_t getLastWrite();
+  const char *path() const;
+  const char *name() const;
+
+  boolean isDirectory(void);
+  boolean seekDir(long position);
+  File openNextFile(const char *mode = FILE_READ);
+  String getNextFileName(void);
+  String getNextFileName(boolean *isDir);
+  void rewindDirectory(void);
 
 protected:
-    FileImplPtr _p;
+  FileImplPtr _p;
 };
 
-class FS
-{
+class FS {
 public:
-    FS(FSImplPtr impl) : _impl(impl) { }
+  FS(FSImplPtr impl) : _impl(impl) {}
 
-    File open(const char* path, const char* mode = FILE_READ);
-    File open(const String& path, const char* mode = FILE_READ);
+  File open(const char *path, const char *mode = FILE_READ, const bool create = false);
+  File open(const String &path, const char *mode = FILE_READ, const bool create = false);
 
-    bool exists(const char* path);
-    bool exists(const String& path);
+  bool exists(const char *path);
+  bool exists(const String &path);
 
-    bool remove(const char* path);
-    bool remove(const String& path);
+  bool remove(const char *path);
+  bool remove(const String &path);
 
-    bool rename(const char* pathFrom, const char* pathTo);
-    bool rename(const String& pathFrom, const String& pathTo);
+  bool rename(const char *pathFrom, const char *pathTo);
+  bool rename(const String &pathFrom, const String &pathTo);
 
-    bool mkdir(const char *path);
-    bool mkdir(const String &path);
+  bool mkdir(const char *path);
+  bool mkdir(const String &path);
 
-    bool rmdir(const char *path);
-    bool rmdir(const String &path);
+  bool rmdir(const char *path);
+  bool rmdir(const String &path);
 
+  const char *mountpoint();
 
 protected:
-    FSImplPtr _impl;
+  FSImplPtr _impl;
 };
 
-} // namespace fs
+}  // namespace fs
 
 #ifndef FS_NO_GLOBALS
-using fs::FS;
 using fs::File;
-using fs::SeekMode;
-using fs::SeekSet;
+using fs::FS;
 using fs::SeekCur;
 using fs::SeekEnd;
-#endif //FS_NO_GLOBALS
+using fs::SeekMode;
+using fs::SeekSet;
+#endif  //FS_NO_GLOBALS
 
-#endif //FS_H
+#endif  //FS_H
diff --git a/libraries/FS/src/FSImpl.h b/libraries/FS/src/FSImpl.h
index 70e5cb1e3cb..c7a6fe150c7 100644
--- a/libraries/FS/src/FSImpl.h
+++ b/libraries/FS/src/FSImpl.h
@@ -23,45 +23,48 @@
 #include <stddef.h>
 #include <stdint.h>
 
-namespace fs
-{
+namespace fs {
 
-class FileImpl
-{
+class FileImpl {
 public:
-    virtual ~FileImpl() { }
-    virtual size_t write(const uint8_t *buf, size_t size) = 0;
-    virtual size_t read(uint8_t* buf, size_t size) = 0;
-    virtual void flush() = 0;
-    virtual bool seek(uint32_t pos, SeekMode mode) = 0;
-    virtual size_t position() const = 0;
-    virtual size_t size() const = 0;
-    virtual void close() = 0;
-    virtual time_t getLastWrite() = 0;
-    virtual const char* name() const = 0;
-    virtual boolean isDirectory(void) = 0;
-    virtual FileImplPtr openNextFile(const char* mode) = 0;
-    virtual void rewindDirectory(void) = 0;
-    virtual operator bool() = 0;
+  virtual ~FileImpl() {}
+  virtual size_t write(const uint8_t *buf, size_t size) = 0;
+  virtual size_t read(uint8_t *buf, size_t size) = 0;
+  virtual void flush() = 0;
+  virtual bool seek(uint32_t pos, SeekMode mode) = 0;
+  virtual size_t position() const = 0;
+  virtual size_t size() const = 0;
+  virtual bool setBufferSize(size_t size) = 0;
+  virtual void close() = 0;
+  virtual time_t getLastWrite() = 0;
+  virtual const char *path() const = 0;
+  virtual const char *name() const = 0;
+  virtual boolean isDirectory(void) = 0;
+  virtual FileImplPtr openNextFile(const char *mode) = 0;
+  virtual boolean seekDir(long position) = 0;
+  virtual String getNextFileName(void) = 0;
+  virtual String getNextFileName(bool *isDir) = 0;
+  virtual void rewindDirectory(void) = 0;
+  virtual operator bool() = 0;
 };
 
-class FSImpl
-{
+class FSImpl {
 protected:
-    const char * _mountpoint;
+  const char *_mountpoint;
+
 public:
-    FSImpl() : _mountpoint(NULL) { }
-    virtual ~FSImpl() { }
-    virtual FileImplPtr open(const char* path, const char* mode) = 0;
-    virtual bool exists(const char* path) = 0;
-    virtual bool rename(const char* pathFrom, const char* pathTo) = 0;
-    virtual bool remove(const char* path) = 0;
-    virtual bool mkdir(const char *path) = 0;
-    virtual bool rmdir(const char *path) = 0;
-    void mountpoint(const char *);
-    const char * mountpoint();
+  FSImpl() : _mountpoint(NULL) {}
+  virtual ~FSImpl() {}
+  virtual FileImplPtr open(const char *path, const char *mode, const bool create) = 0;
+  virtual bool exists(const char *path) = 0;
+  virtual bool rename(const char *pathFrom, const char *pathTo) = 0;
+  virtual bool remove(const char *path) = 0;
+  virtual bool mkdir(const char *path) = 0;
+  virtual bool rmdir(const char *path) = 0;
+  void mountpoint(const char *);
+  const char *mountpoint();
 };
 
-} // namespace fs
+}  // namespace fs
 
-#endif //FSIMPL_H
+#endif  //FSIMPL_H
diff --git a/libraries/FS/src/vfs_api.cpp b/libraries/FS/src/vfs_api.cpp
index 346b7a93248..616f37ac611 100644
--- a/libraries/FS/src/vfs_api.cpp
+++ b/libraries/FS/src/vfs_api.cpp
@@ -16,404 +16,517 @@
 
 using namespace fs;
 
-FileImplPtr VFSImpl::open(const char* path, const char* mode)
-{
-    if(!_mountpoint) {
-        log_e("File system is not mounted");
-        return FileImplPtr();
-    }
+#define DEFAULT_FILE_BUFFER_SIZE 4096
 
-    if(!path || path[0] != '/') {
-        log_e("%s does not start with /", path);
-        return FileImplPtr();
-    }
+FileImplPtr VFSImpl::open(const char *fpath, const char *mode, const bool create) {
+  if (!_mountpoint) {
+    log_e("File system is not mounted");
+    return FileImplPtr();
+  }
 
-    char * temp = (char *)malloc(strlen(path)+strlen(_mountpoint)+2);
-    if(!temp) {
-        log_e("malloc failed");
-        return FileImplPtr();
-    }
+  if (!fpath || fpath[0] != '/') {
+    log_e("%s does not start with /", fpath);
+    return FileImplPtr();
+  }
 
-    sprintf(temp,"%s%s", _mountpoint, path);
+  char *temp = (char *)malloc(strlen(fpath) + strlen(_mountpoint) + 2);
+  if (!temp) {
+    log_e("malloc failed");
+    return FileImplPtr();
+  }
 
-    struct stat st;
-    //file lound
-    if(!stat(temp, &st)) {
-        free(temp);
-        if (S_ISREG(st.st_mode) || S_ISDIR(st.st_mode)) {
-            return std::make_shared<VFSFileImpl>(this, path, mode);
-        }
-        log_e("%s has wrong mode 0x%08X", path, st.st_mode);
-        return FileImplPtr();
-    }
+  strcpy(temp, _mountpoint);
+  strcat(temp, fpath);
 
-    //file not found but mode permits creation
-    if(mode && mode[0] != 'r') {
-        free(temp);
-        return std::make_shared<VFSFileImpl>(this, path, mode);
+  struct stat st;
+  //file found
+  if (!stat(temp, &st)) {
+    free(temp);
+    if (S_ISREG(st.st_mode) || S_ISDIR(st.st_mode)) {
+      return std::make_shared<VFSFileImpl>(this, fpath, mode);
     }
+    log_e("%s has wrong mode 0x%08X", fpath, st.st_mode);
+    return FileImplPtr();
+  }
 
-    //try to open this as directory (might be mount point)
-    DIR * d = opendir(temp);
-    if(d) {
-        closedir(d);
-        free(temp);
-        return std::make_shared<VFSFileImpl>(this, path, mode);
-    }
+  //try to open this as directory (might be mount point)
+  DIR *d = opendir(temp);
+  if (d) {
+    closedir(d);
+    free(temp);
+    return std::make_shared<VFSFileImpl>(this, fpath, mode);
+  }
 
-    log_e("%s does not exist", temp);
+  //file not found but mode permits file creation without folder creation
+  if ((mode && mode[0] != 'r') && (!create)) {
     free(temp);
-    return FileImplPtr();
-}
+    return std::make_shared<VFSFileImpl>(this, fpath, mode);
+  }
 
-bool VFSImpl::exists(const char* path)
-{
-    if(!_mountpoint) {
-        log_e("File system is not mounted");
-        return false;
-    }
+  ////file not found but mode permits file creation and folder creation
+  if ((mode && mode[0] != 'r') && create) {
+
+    char *token;
+    char *folder = (char *)malloc(strlen(fpath));
+
+    int start_index = 0;
+    int end_index = 0;
+
+    token = strchr(fpath + 1, '/');
+    end_index = (token - fpath);
+
+    while (token != NULL) {
+      memcpy(folder, fpath + start_index, end_index - start_index);
+      folder[end_index - start_index] = '\0';
+
+      if (!VFSImpl::mkdir(folder)) {
+        log_e("Creating folder: %s failed!", folder);
+        return FileImplPtr();
+      }
 
-    VFSFileImpl f(this, path, "r");
-    if(f) {
-        f.close();
-        return true;
+      token = strchr(token + 1, '/');
+      if (token != NULL) {
+        end_index = (token - fpath);
+        memset(folder, 0, strlen(folder));
+      }
     }
+
+    free(folder);
+    free(temp);
+    return std::make_shared<VFSFileImpl>(this, fpath, mode);
+  }
+
+  log_e("%s does not exist, no permits for creation", temp);
+  free(temp);
+  return FileImplPtr();
+}
+
+bool VFSImpl::exists(const char *fpath) {
+  if (!_mountpoint) {
+    log_e("File system is not mounted");
     return false;
+  }
+
+  VFSFileImpl f(this, fpath, "r");
+  if (f) {
+    f.close();
+    return true;
+  }
+  return false;
 }
 
-bool VFSImpl::rename(const char* pathFrom, const char* pathTo)
-{
-    if(!_mountpoint) {
-        log_e("File system is not mounted");
-        return false;
-    }
+bool VFSImpl::rename(const char *pathFrom, const char *pathTo) {
+  if (!_mountpoint) {
+    log_e("File system is not mounted");
+    return false;
+  }
 
-    if(!pathFrom || pathFrom[0] != '/' || !pathTo || pathTo[0] != '/') {
-        log_e("bad arguments");
-        return false;
-    }
-    if(!exists(pathFrom)) {
-        log_e("%s does not exists", pathFrom);
-        return false;
-    }
-    char * temp1 = (char *)malloc(strlen(pathFrom)+strlen(_mountpoint)+1);
-    if(!temp1) {
-        log_e("malloc failed");
-        return false;
-    }
-    char * temp2 = (char *)malloc(strlen(pathTo)+strlen(_mountpoint)+1);
-    if(!temp2) {
-        free(temp1);
-        log_e("malloc failed");
-        return false;
-    }
-    sprintf(temp1,"%s%s", _mountpoint, pathFrom);
-    sprintf(temp2,"%s%s", _mountpoint, pathTo);
-    auto rc = ::rename(temp1, temp2);
+  if (!pathFrom || pathFrom[0] != '/' || !pathTo || pathTo[0] != '/') {
+    log_e("bad arguments");
+    return false;
+  }
+  if (!exists(pathFrom)) {
+    log_e("%s does not exists", pathFrom);
+    return false;
+  }
+  size_t mountpointLen = strlen(_mountpoint);
+  char *temp1 = (char *)malloc(strlen(pathFrom) + mountpointLen + 1);
+  if (!temp1) {
+    log_e("malloc failed");
+    return false;
+  }
+  char *temp2 = (char *)malloc(strlen(pathTo) + mountpointLen + 1);
+  if (!temp2) {
     free(temp1);
-    free(temp2);
-    return rc == 0;
+    log_e("malloc failed");
+    return false;
+  }
+
+  strcpy(temp1, _mountpoint);
+  strcat(temp1, pathFrom);
+
+  strcpy(temp2, _mountpoint);
+  strcat(temp2, pathTo);
+
+  auto rc = ::rename(temp1, temp2);
+  free(temp1);
+  free(temp2);
+  return rc == 0;
 }
 
-bool VFSImpl::remove(const char* path)
-{
-    if(!_mountpoint) {
-        log_e("File system is not mounted");
-        return false;
-    }
+bool VFSImpl::remove(const char *fpath) {
+  if (!_mountpoint) {
+    log_e("File system is not mounted");
+    return false;
+  }
 
-    if(!path || path[0] != '/') {
-        log_e("bad arguments");
-        return false;
-    }
+  if (!fpath || fpath[0] != '/') {
+    log_e("bad arguments");
+    return false;
+  }
 
-    VFSFileImpl f(this, path, "r");
-    if(!f || f.isDirectory()) {
-        if(f) {
-            f.close();
-        }
-        log_e("%s does not exists or is directory", path);
-        return false;
+  VFSFileImpl f(this, fpath, "r");
+  if (!f || f.isDirectory()) {
+    if (f) {
+      f.close();
     }
-    f.close();
+    log_e("%s does not exists or is directory", fpath);
+    return false;
+  }
+  f.close();
 
-    char * temp = (char *)malloc(strlen(path)+strlen(_mountpoint)+1);
-    if(!temp) {
-        log_e("malloc failed");
-        return false;
-    }
-    sprintf(temp,"%s%s", _mountpoint, path);
-    auto rc = unlink(temp);
-    free(temp);
-    return rc == 0;
+  char *temp = (char *)malloc(strlen(fpath) + strlen(_mountpoint) + 1);
+  if (!temp) {
+    log_e("malloc failed");
+    return false;
+  }
+
+  strcpy(temp, _mountpoint);
+  strcat(temp, fpath);
+
+  auto rc = unlink(temp);
+  free(temp);
+  return rc == 0;
 }
 
-bool VFSImpl::mkdir(const char *path)
-{
-    if(!_mountpoint) {
-        log_e("File system is not mounted");
-        return false;
-    }
+bool VFSImpl::mkdir(const char *fpath) {
+  if (!_mountpoint) {
+    log_e("File system is not mounted");
+    return false;
+  }
 
-    VFSFileImpl f(this, path, "r");
-    if(f && f.isDirectory()) {
-        f.close();
-        //log_w("%s already exists", path);
-        return true;
-    } else if(f) {
-        f.close();
-        log_e("%s is a file", path);
-        return false;
-    }
+  VFSFileImpl f(this, fpath, "r");
+  if (f && f.isDirectory()) {
+    f.close();
+    //log_w("%s already exists", fpath);
+    return true;
+  } else if (f) {
+    f.close();
+    log_e("%s is a file", fpath);
+    return false;
+  }
 
-    char * temp = (char *)malloc(strlen(path)+strlen(_mountpoint)+1);
-    if(!temp) {
-        log_e("malloc failed");
-        return false;
-    }
-    sprintf(temp,"%s%s", _mountpoint, path);
-    auto rc = ::mkdir(temp, ACCESSPERMS);
-    free(temp);
-    return rc == 0;
-}
+  char *temp = (char *)malloc(strlen(fpath) + strlen(_mountpoint) + 1);
+  if (!temp) {
+    log_e("malloc failed");
+    return false;
+  }
 
-bool VFSImpl::rmdir(const char *path)
-{
-    if(!_mountpoint) {
-        log_e("File system is not mounted");
-        return false;
-    }
+  strcpy(temp, _mountpoint);
+  strcat(temp, fpath);
 
-    if (strcmp(_mountpoint, "/spiffs") == 0) {
-        log_e("rmdir is unnecessary in SPIFFS");
-        return false;
-    }
+  auto rc = ::mkdir(temp, ACCESSPERMS);
+  free(temp);
+  return rc == 0;
+}
 
-    VFSFileImpl f(this, path, "r");
-    if(!f || !f.isDirectory()) {
-        if(f) {
-            f.close();
-        }
-        log_e("%s does not exists or is a file", path);
-        return false;
-    }
-    f.close();
+bool VFSImpl::rmdir(const char *fpath) {
+  if (!_mountpoint) {
+    log_e("File system is not mounted");
+    return false;
+  }
 
-    char * temp = (char *)malloc(strlen(path)+strlen(_mountpoint)+1);
-    if(!temp) {
-        log_e("malloc failed");
-        return false;
+  if (strcmp(_mountpoint, "/spiffs") == 0) {
+    log_e("rmdir is unnecessary in SPIFFS");
+    return false;
+  }
+
+  VFSFileImpl f(this, fpath, "r");
+  if (!f || !f.isDirectory()) {
+    if (f) {
+      f.close();
     }
-    sprintf(temp,"%s%s", _mountpoint, path);
-    auto rc = ::rmdir(temp);
-    free(temp);
-    return rc == 0;
-}
+    log_e("%s does not exists or is a file", fpath);
+    return false;
+  }
+  f.close();
 
+  char *temp = (char *)malloc(strlen(fpath) + strlen(_mountpoint) + 1);
+  if (!temp) {
+    log_e("malloc failed");
+    return false;
+  }
 
+  strcpy(temp, _mountpoint);
+  strcat(temp, fpath);
 
+  auto rc = ::rmdir(temp);
+  free(temp);
+  return rc == 0;
+}
 
-VFSFileImpl::VFSFileImpl(VFSImpl* fs, const char* path, const char* mode)
-    : _fs(fs)
-    , _f(NULL)
-    , _d(NULL)
-    , _path(NULL)
-    , _isDirectory(false)
-    , _written(false)
-{
-    char * temp = (char *)malloc(strlen(path)+strlen(_fs->_mountpoint)+1);
-    if(!temp) {
-        return;
-    }
-    sprintf(temp,"%s%s", _fs->_mountpoint, path);
+VFSFileImpl::VFSFileImpl(VFSImpl *fs, const char *fpath, const char *mode) : _fs(fs), _f(NULL), _d(NULL), _path(NULL), _isDirectory(false), _written(false) {
+  char *temp = (char *)malloc(strlen(fpath) + strlen(_fs->_mountpoint) + 1);
+  if (!temp) {
+    return;
+  }
 
-    _path = strdup(path);
-    if(!_path) {
-        log_e("strdup(%s) failed", path);
-        free(temp);
-        return;
-    }
+  strcpy(temp, _fs->_mountpoint);
+  strcat(temp, fpath);
 
-    if(!stat(temp, &_stat)) {
-        //file found
-        if (S_ISREG(_stat.st_mode)) {
-            _isDirectory = false;
-            _f = fopen(temp, mode);
-            if(!_f) {
-                log_e("fopen(%s) failed", temp);
-            }
-        } else if(S_ISDIR(_stat.st_mode)) {
-            _isDirectory = true;
-            _d = opendir(temp);
-            if(!_d) {
-                log_e("opendir(%s) failed", temp);
-            }
-        } else {
-            log_e("Unknown type 0x%08X for file %s", ((_stat.st_mode)&_IFMT), temp);
-        }
-    } else {
-        //file not found
-        if(!mode || mode[0] == 'r') {
-            //try to open as directory
-            _d = opendir(temp);
-            if(_d) {
-                _isDirectory = true;
-            } else {
-                _isDirectory = false;
-                //log_w("stat(%s) failed", temp);
-            }
-        } else {
-            //lets create this new file
-            _isDirectory = false;
-            _f = fopen(temp, mode);
-            if(!_f) {
-                log_e("fopen(%s) failed", temp);
-            }
-        }
-    }
+  _path = strdup(fpath);
+  if (!_path) {
+    log_e("strdup(%s) failed", fpath);
     free(temp);
+    return;
+  }
+
+  if (!stat(temp, &_stat)) {
+    //file found
+    if (S_ISREG(_stat.st_mode)) {
+      _isDirectory = false;
+      _f = fopen(temp, mode);
+      if (!_f) {
+        log_e("fopen(%s) failed", temp);
+      }
+      if (_f && (_stat.st_blksize == 0)) {
+        setvbuf(_f, NULL, _IOFBF, DEFAULT_FILE_BUFFER_SIZE);
+      }
+    } else if (S_ISDIR(_stat.st_mode)) {
+      _isDirectory = true;
+      _d = opendir(temp);
+      if (!_d) {
+        log_e("opendir(%s) failed", temp);
+      }
+    } else {
+      log_e("Unknown type 0x%08X for file %s", ((_stat.st_mode) & _IFMT), temp);
+    }
+  } else {
+    //file not found
+    if (!mode || mode[0] == 'r') {
+      //try to open as directory
+      _d = opendir(temp);
+      if (_d) {
+        _isDirectory = true;
+      } else {
+        _isDirectory = false;
+        //log_w("stat(%s) failed", temp);
+      }
+    } else {
+      //lets create this new file
+      _isDirectory = false;
+      _f = fopen(temp, mode);
+      if (!_f) {
+        log_e("fopen(%s) failed", temp);
+      }
+      if (_f && (_stat.st_blksize == 0)) {
+        setvbuf(_f, NULL, _IOFBF, DEFAULT_FILE_BUFFER_SIZE);
+      }
+    }
+  }
+  free(temp);
 }
 
-VFSFileImpl::~VFSFileImpl()
-{
-    close();
+VFSFileImpl::~VFSFileImpl() {
+  close();
 }
 
-void VFSFileImpl::close()
-{
-    if(_path) {
-        free(_path);
-        _path = NULL;
-    }
-    if(_isDirectory && _d) {
-        closedir(_d);
-        _d = NULL;
-        _isDirectory = false;
-    } else if(_f) {
-        fclose(_f);
-        _f = NULL;
-    }
+void VFSFileImpl::close() {
+  if (_path) {
+    free(_path);
+    _path = NULL;
+  }
+  if (_isDirectory && _d) {
+    closedir(_d);
+    _d = NULL;
+    _isDirectory = false;
+  } else if (_f) {
+    fclose(_f);
+    _f = NULL;
+  }
 }
 
-VFSFileImpl::operator bool()
-{
-    return (_isDirectory && _d != NULL) || _f != NULL;
+VFSFileImpl::operator bool() {
+  return (_isDirectory && _d != NULL) || _f != NULL;
 }
 
 time_t VFSFileImpl::getLastWrite() {
-    _getStat() ;
-    return _stat.st_mtime;
+  _getStat();
+  return _stat.st_mtime;
 }
 
-void VFSFileImpl::_getStat() const
-{
-    if(!_path) {
-        return;
-    }
-    char * temp = (char *)malloc(strlen(_path)+strlen(_fs->_mountpoint)+1);
-    if(!temp) {
-        return;
-    }
-    sprintf(temp,"%s%s", _fs->_mountpoint, _path);
-    if(!stat(temp, &_stat)) {
-        _written = false;
-    }
-    free(temp);
+void VFSFileImpl::_getStat() const {
+  if (!_path) {
+    return;
+  }
+  char *temp = (char *)malloc(strlen(_path) + strlen(_fs->_mountpoint) + 1);
+  if (!temp) {
+    return;
+  }
+
+  strcpy(temp, _fs->_mountpoint);
+  strcat(temp, _path);
+
+  if (!stat(temp, &_stat)) {
+    _written = false;
+  }
+  free(temp);
 }
 
-size_t VFSFileImpl::write(const uint8_t *buf, size_t size)
-{
-    if(_isDirectory || !_f || !buf || !size) {
-        return 0;
-    }
-    _written = true;
-    return fwrite(buf, 1, size, _f);
+size_t VFSFileImpl::write(const uint8_t *buf, size_t size) {
+  if (_isDirectory || !_f || !buf || !size) {
+    return 0;
+  }
+  _written = true;
+  return fwrite(buf, 1, size, _f);
 }
 
-size_t VFSFileImpl::read(uint8_t* buf, size_t size)
-{
-    if(_isDirectory || !_f || !buf || !size) {
-        return 0;
-    }
+size_t VFSFileImpl::read(uint8_t *buf, size_t size) {
+  if (_isDirectory || !_f || !buf || !size) {
+    return 0;
+  }
 
-    return fread(buf, 1, size, _f);
+  return fread(buf, 1, size, _f);
 }
 
-void VFSFileImpl::flush()
-{
-    if(_isDirectory || !_f) {
-        return;
-    }
-    fflush(_f);
-    // workaround for https://github.com/espressif/arduino-esp32/issues/1293
-    fsync(fileno(_f));
+void VFSFileImpl::flush() {
+  if (_isDirectory || !_f) {
+    return;
+  }
+  fflush(_f);
+  // workaround for https://github.com/espressif/arduino-esp32/issues/1293
+  fsync(fileno(_f));
 }
 
-bool VFSFileImpl::seek(uint32_t pos, SeekMode mode)
-{
-    if(_isDirectory || !_f) {
-        return false;
-    }
-    auto rc = fseek(_f, pos, mode);
-    return rc == 0;
+bool VFSFileImpl::seek(uint32_t pos, SeekMode mode) {
+  if (_isDirectory || !_f) {
+    return false;
+  }
+  auto rc = fseek(_f, pos, mode);
+  return rc == 0;
 }
 
-size_t VFSFileImpl::position() const
-{
-    if(_isDirectory || !_f) {
-        return 0;
-    }
-    return ftell(_f);
+size_t VFSFileImpl::position() const {
+  if (_isDirectory || !_f) {
+    return 0;
+  }
+  return ftell(_f);
 }
 
-size_t VFSFileImpl::size() const
-{
-    if(_isDirectory || !_f) {
-        return 0;
-    }
-    if (_written) {
-        _getStat();
-    }
-    return _stat.st_size;
+size_t VFSFileImpl::size() const {
+  if (_isDirectory || !_f) {
+    return 0;
+  }
+  if (_written) {
+    _getStat();
+  }
+  return _stat.st_size;
+}
+
+/*
+* Change size of files internal buffer used for read / write operations.
+* Need to be called right after opening file before any other operation!
+*/
+bool VFSFileImpl::setBufferSize(size_t size) {
+  if (_isDirectory || !_f) {
+    return 0;
+  }
+  int res = setvbuf(_f, NULL, _IOFBF, size);
+  return res == 0;
+}
+
+const char *VFSFileImpl::path() const {
+  return (const char *)_path;
 }
 
-const char* VFSFileImpl::name() const
-{
-    return (const char*) _path;
+const char *VFSFileImpl::name() const {
+  return pathToFileName(path());
 }
 
 //to implement
-boolean VFSFileImpl::isDirectory(void)
-{
-    return _isDirectory;
+boolean VFSFileImpl::isDirectory(void) {
+  return _isDirectory;
 }
 
-FileImplPtr VFSFileImpl::openNextFile(const char* mode)
-{
-    if(!_isDirectory || !_d) {
-        return FileImplPtr();
-    }
-    struct dirent *file = readdir(_d);
-    if(file == NULL) {
-        return FileImplPtr();
-    }
-    if(file->d_type != DT_REG && file->d_type != DT_DIR) {
-        return openNextFile(mode);
-    }
-    String fname = String(file->d_name);
-    String name = String(_path);
-    if(!fname.startsWith("/") && !name.endsWith("/")) {
-        name += "/";
-    }
-    name += fname;
+FileImplPtr VFSFileImpl::openNextFile(const char *mode) {
+  if (!_isDirectory || !_d) {
+    return FileImplPtr();
+  }
+  struct dirent *file = readdir(_d);
+  if (file == NULL) {
+    return FileImplPtr();
+  }
+  if (file->d_type != DT_REG && file->d_type != DT_DIR) {
+    return openNextFile(mode);
+  }
+
+  size_t pathLen = strlen(_path);
+  size_t fileNameLen = strlen(file->d_name);
+  char *name = (char *)malloc(pathLen + fileNameLen + 2);
+
+  if (name == NULL) {
+    return FileImplPtr();
+  }
 
-    return std::make_shared<VFSFileImpl>(_fs, name.c_str(), mode);
+  strcpy(name, _path);
+
+  if ((file->d_name[0] != '/') && (_path[pathLen - 1] != '/')) {
+    strcat(name, "/");
+  }
+
+  strcat(name, file->d_name);
+
+  FileImplPtr fileImplPtr = std::make_shared<VFSFileImpl>(_fs, name, mode);
+  free(name);
+  return fileImplPtr;
 }
 
-void VFSFileImpl::rewindDirectory(void)
-{
-    if(!_isDirectory || !_d) {
-        return;
-    }
-    rewinddir(_d);
+boolean VFSFileImpl::seekDir(long position) {
+  if (!_d) {
+    return false;
+  }
+  seekdir(_d, position);
+  return true;
+}
+
+String VFSFileImpl::getNextFileName() {
+  if (!_isDirectory || !_d) {
+    return "";
+  }
+  struct dirent *file = readdir(_d);
+  if (file == NULL) {
+    return "";
+  }
+  if (file->d_type != DT_REG && file->d_type != DT_DIR) {
+    return "";
+  }
+  String fname = String(file->d_name);
+  String name = String(_path);
+  if (!fname.startsWith("/") && !name.endsWith("/")) {
+    name += "/";
+  }
+  name += fname;
+  return name;
+}
+
+String VFSFileImpl::getNextFileName(bool *isDir) {
+  if (!_isDirectory || !_d) {
+    return "";
+  }
+  struct dirent *file = readdir(_d);
+  if (file == NULL) {
+    return "";
+  }
+  if (file->d_type != DT_REG && file->d_type != DT_DIR) {
+    return "";
+  }
+  String fname = String(file->d_name);
+  String name = String(_path);
+  if (!fname.startsWith("/") && !name.endsWith("/")) {
+    name += "/";
+  }
+  name += fname;
+
+  // check entry is a directory
+  if (isDir) {
+    *isDir = (file->d_type == DT_DIR);
+  }
+  return name;
+}
+
+void VFSFileImpl::rewindDirectory(void) {
+  if (!_isDirectory || !_d) {
+    return;
+  }
+  rewinddir(_d);
 }
diff --git a/libraries/FS/src/vfs_api.h b/libraries/FS/src/vfs_api.h
index c5649130f60..90b95c52566 100644
--- a/libraries/FS/src/vfs_api.h
+++ b/libraries/FS/src/vfs_api.h
@@ -28,50 +28,53 @@ using namespace fs;
 
 class VFSFileImpl;
 
-class VFSImpl : public FSImpl
-{
+class VFSImpl : public FSImpl {
 
 protected:
-    friend class VFSFileImpl;
+  friend class VFSFileImpl;
 
 public:
-    FileImplPtr open(const char* path, const char* mode) override;
-    bool        exists(const char* path) override;
-    bool        rename(const char* pathFrom, const char* pathTo) override;
-    bool        remove(const char* path) override;
-    bool        mkdir(const char *path) override;
-    bool        rmdir(const char *path) override;
+  FileImplPtr open(const char *path, const char *mode, const bool create) override;
+  bool exists(const char *path) override;
+  bool rename(const char *pathFrom, const char *pathTo) override;
+  bool remove(const char *path) override;
+  bool mkdir(const char *path) override;
+  bool rmdir(const char *path) override;
 };
 
-class VFSFileImpl : public FileImpl
-{
+class VFSFileImpl : public FileImpl {
 protected:
-    VFSImpl*            _fs;
-    FILE *              _f;
-    DIR *               _d;
-    char *              _path;
-    bool                _isDirectory;
-    mutable struct stat _stat;
-    mutable bool        _written;
+  VFSImpl *_fs;
+  FILE *_f;
+  DIR *_d;
+  char *_path;
+  bool _isDirectory;
+  mutable struct stat _stat;
+  mutable bool _written;
 
-    void _getStat() const;
+  void _getStat() const;
 
 public:
-    VFSFileImpl(VFSImpl* fs, const char* path, const char* mode);
-    ~VFSFileImpl() override;
-    size_t      write(const uint8_t *buf, size_t size) override;
-    size_t      read(uint8_t* buf, size_t size) override;
-    void        flush() override;
-    bool        seek(uint32_t pos, SeekMode mode) override;
-    size_t      position() const override;
-    size_t      size() const override;
-    void        close() override;
-    const char* name() const override;
-    time_t getLastWrite()  override;
-    boolean     isDirectory(void) override;
-    FileImplPtr openNextFile(const char* mode) override;
-    void        rewindDirectory(void) override;
-    operator    bool();
+  VFSFileImpl(VFSImpl *fs, const char *path, const char *mode);
+  ~VFSFileImpl() override;
+  size_t write(const uint8_t *buf, size_t size) override;
+  size_t read(uint8_t *buf, size_t size) override;
+  void flush() override;
+  bool seek(uint32_t pos, SeekMode mode) override;
+  size_t position() const override;
+  size_t size() const override;
+  bool setBufferSize(size_t size);
+  void close() override;
+  const char *path() const override;
+  const char *name() const override;
+  time_t getLastWrite() override;
+  boolean isDirectory(void) override;
+  boolean seekDir(long position) override;
+  String getNextFileName(void) override;
+  String getNextFileName(bool *isDir) override;
+  FileImplPtr openNextFile(const char *mode) override;
+  void rewindDirectory(void) override;
+  operator bool();
 };
 
 #endif
diff --git a/libraries/HTTPClient/examples/Authorization/Authorization.ino b/libraries/HTTPClient/examples/Authorization/Authorization.ino
index 400f93cc8e1..02bf9ae93c7 100644
--- a/libraries/HTTPClient/examples/Authorization/Authorization.ino
+++ b/libraries/HTTPClient/examples/Authorization/Authorization.ino
@@ -18,35 +18,33 @@ WiFiMulti wifiMulti;
 
 void setup() {
 
-    USE_SERIAL.begin(115200);
+  USE_SERIAL.begin(115200);
 
-    USE_SERIAL.println();
-    USE_SERIAL.println();
-    USE_SERIAL.println();
+  USE_SERIAL.println();
+  USE_SERIAL.println();
+  USE_SERIAL.println();
 
-    for(uint8_t t = 4; t > 0; t--) {
-        USE_SERIAL.printf("[SETUP] WAIT %d...\n", t);
-        USE_SERIAL.flush();
-        delay(1000);
-    }
-
-    wifiMulti.addAP("SSID", "PASSWORD");
+  for (uint8_t t = 4; t > 0; t--) {
+    USE_SERIAL.printf("[SETUP] WAIT %d...\n", t);
+    USE_SERIAL.flush();
+    delay(1000);
+  }
 
+  wifiMulti.addAP("SSID", "PASSWORD");
 }
 
 void loop() {
-    // wait for WiFi connection
-    if((wifiMulti.run() == WL_CONNECTED)) {
-
-        HTTPClient http;
+  // wait for WiFi connection
+  if ((wifiMulti.run() == WL_CONNECTED)) {
 
-        USE_SERIAL.print("[HTTP] begin...\n");
-        // configure traged server and url
+    HTTPClient http;
 
+    USE_SERIAL.print("[HTTP] begin...\n");
+    // configure traged server and url
 
-        http.begin("http://user:password@192.168.1.12/test.html");
+    http.begin("http://user:password@192.168.1.12/test.html");
 
-        /*
+    /*
           // or
           http.begin("http://192.168.1.12/test.html");
           http.setAuthorization("user", "password");
@@ -56,28 +54,26 @@ void loop() {
           http.setAuthorization("dXNlcjpwYXN3b3Jk");
          */
 
-
-        USE_SERIAL.print("[HTTP] GET...\n");
-        // start connection and send HTTP header
-        int httpCode = http.GET();
-
-        // httpCode will be negative on error
-        if(httpCode > 0) {
-            // HTTP header has been send and Server response header has been handled
-            USE_SERIAL.printf("[HTTP] GET... code: %d\n", httpCode);
-
-            // file found at server
-            if(httpCode == HTTP_CODE_OK) {
-                String payload = http.getString();
-                USE_SERIAL.println(payload);
-            }
-        } else {
-            USE_SERIAL.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
-        }
-
-        http.end();
+    USE_SERIAL.print("[HTTP] GET...\n");
+    // start connection and send HTTP header
+    int httpCode = http.GET();
+
+    // httpCode will be negative on error
+    if (httpCode > 0) {
+      // HTTP header has been send and Server response header has been handled
+      USE_SERIAL.printf("[HTTP] GET... code: %d\n", httpCode);
+
+      // file found at server
+      if (httpCode == HTTP_CODE_OK) {
+        String payload = http.getString();
+        USE_SERIAL.println(payload);
+      }
+    } else {
+      USE_SERIAL.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
     }
 
-    delay(10000);
-}
+    http.end();
+  }
 
+  delay(10000);
+}
diff --git a/libraries/HTTPClient/examples/Authorization/ci.json b/libraries/HTTPClient/examples/Authorization/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/HTTPClient/examples/Authorization/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/HTTPClient/examples/BasicHttpClient/BasicHttpClient.ino b/libraries/HTTPClient/examples/BasicHttpClient/BasicHttpClient.ino
index 9ee620ab5a5..e8f5be62438 100644
--- a/libraries/HTTPClient/examples/BasicHttpClient/BasicHttpClient.ino
+++ b/libraries/HTTPClient/examples/BasicHttpClient/BasicHttpClient.ino
@@ -17,85 +17,84 @@
 WiFiMulti wifiMulti;
 
 /*
-const char* ca = \ 
-"-----BEGIN CERTIFICATE-----\n" \  
-"MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n" \  
-"MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n" \  
-"DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n" \  
-"SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n" \  
-"GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n" \  
-"AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n" \  
-"q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n" \  
-"SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n" \  
-"Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n" \  
-"a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n" \  
-"/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n" \  
-"AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n" \  
-"CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n" \  
-"bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n" \  
-"c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n" \  
-"VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n" \  
-"ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n" \  
-"MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n" \  
-"Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n" \  
-"AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n" \  
-"uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n" \  
-"wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n" \  
-"X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n" \  
-"PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n" \  
-"KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n" \  
+const char* ca = \
+"-----BEGIN CERTIFICATE-----\n" \
+"MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n" \
+"MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n" \
+"DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n" \
+"SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n" \
+"GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n" \
+"AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n" \
+"q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n" \
+"SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n" \
+"Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n" \
+"a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n" \
+"/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n" \
+"AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n" \
+"CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n" \
+"bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n" \
+"c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n" \
+"VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n" \
+"ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n" \
+"MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n" \
+"Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n" \
+"AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n" \
+"uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n" \
+"wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n" \
+"X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n" \
+"PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n" \
+"KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n" \
 "-----END CERTIFICATE-----\n";
 */
 
 void setup() {
 
-    USE_SERIAL.begin(115200);
+  USE_SERIAL.begin(115200);
 
-    USE_SERIAL.println();
-    USE_SERIAL.println();
-    USE_SERIAL.println();
+  USE_SERIAL.println();
+  USE_SERIAL.println();
+  USE_SERIAL.println();
 
-    for(uint8_t t = 4; t > 0; t--) {
-        USE_SERIAL.printf("[SETUP] WAIT %d...\n", t);
-        USE_SERIAL.flush();
-        delay(1000);
-    }
-
-    wifiMulti.addAP("SSID", "PASSWORD");
+  for (uint8_t t = 4; t > 0; t--) {
+    USE_SERIAL.printf("[SETUP] WAIT %d...\n", t);
+    USE_SERIAL.flush();
+    delay(1000);
+  }
 
+  wifiMulti.addAP("SSID", "PASSWORD");
 }
 
 void loop() {
-    // wait for WiFi connection
-    if((wifiMulti.run() == WL_CONNECTED)) {
-
-        HTTPClient http;
-
-        USE_SERIAL.print("[HTTP] begin...\n");
-        // configure traged server and url
-        //http.begin("https://www.howsmyssl.com/a/check", ca); //HTTPS
-        http.begin("http://example.com/index.html"); //HTTP
-
-        USE_SERIAL.print("[HTTP] GET...\n");
-        // start connection and send HTTP header
-        int httpCode = http.GET();
-
-        // httpCode will be negative on error
-        if(httpCode > 0) {
-            // HTTP header has been send and Server response header has been handled
-            USE_SERIAL.printf("[HTTP] GET... code: %d\n", httpCode);
-
-            // file found at server
-            if(httpCode == HTTP_CODE_OK) {
-                String payload = http.getString();
-                USE_SERIAL.println(payload);
-            }
-        } else {
-            USE_SERIAL.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
-        }
-
-        http.end();
+  // wait for WiFi connection
+  if ((wifiMulti.run() == WL_CONNECTED)) {
+
+    HTTPClient http;
+
+    USE_SERIAL.print("[HTTP] begin...\n");
+    // configure traged server and url
+    //http.begin("https://www.howsmyssl.com/a/check", ca); //HTTPS
+    http.begin("http://example.com/index.html");  //HTTP
+
+    USE_SERIAL.print("[HTTP] GET...\n");
+    // start connection and send HTTP header
+    int httpCode = http.GET();
+
+    // httpCode will be negative on error
+    if (httpCode > 0) {
+      // HTTP header has been send and Server response header has been handled
+      USE_SERIAL.printf("[HTTP] GET... code: %d\n", httpCode);
+
+      // file found at server
+      if (httpCode == HTTP_CODE_OK) {
+        String payload = http.getString();
+        USE_SERIAL.println(payload);
+      }
+    } else {
+      USE_SERIAL.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
     }
 
-    delay(5000);
+    http.end();
+  }
+
+  delay(5000);
 }
diff --git a/libraries/HTTPClient/examples/BasicHttpClient/ci.json b/libraries/HTTPClient/examples/BasicHttpClient/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/HTTPClient/examples/BasicHttpClient/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/HTTPClient/examples/BasicHttpsClient/BasicHttpsClient.ino b/libraries/HTTPClient/examples/BasicHttpsClient/BasicHttpsClient.ino
index 9ef2b44eadf..73e127d1261 100644
--- a/libraries/HTTPClient/examples/BasicHttpsClient/BasicHttpsClient.ino
+++ b/libraries/HTTPClient/examples/BasicHttpsClient/BasicHttpsClient.ino
@@ -12,51 +12,39 @@
 
 #include <HTTPClient.h>
 
-#include <WiFiClientSecure.h>
-
-// This is GandiStandardSSLCA2.pem, the root Certificate Authority that signed 
-// the server certifcate for the demo server https://jigsaw.w3.org in this
-// example. This certificate is valid until Sep 11 23:59:59 2024 GMT
-const char* rootCACertificate = \
-"-----BEGIN CERTIFICATE-----\n" \
-"MIIF6TCCA9GgAwIBAgIQBeTcO5Q4qzuFl8umoZhQ4zANBgkqhkiG9w0BAQwFADCB\n" \
-"iDELMAkGA1UEBhMCVVMxEzARBgNVBAgTCk5ldyBKZXJzZXkxFDASBgNVBAcTC0pl\n" \
-"cnNleSBDaXR5MR4wHAYDVQQKExVUaGUgVVNFUlRSVVNUIE5ldHdvcmsxLjAsBgNV\n" \
-"BAMTJVVTRVJUcnVzdCBSU0EgQ2VydGlmaWNhdGlvbiBBdXRob3JpdHkwHhcNMTQw\n" \
-"OTEyMDAwMDAwWhcNMjQwOTExMjM1OTU5WjBfMQswCQYDVQQGEwJGUjEOMAwGA1UE\n" \
-"CBMFUGFyaXMxDjAMBgNVBAcTBVBhcmlzMQ4wDAYDVQQKEwVHYW5kaTEgMB4GA1UE\n" \
-"AxMXR2FuZGkgU3RhbmRhcmQgU1NMIENBIDIwggEiMA0GCSqGSIb3DQEBAQUAA4IB\n" \
-"DwAwggEKAoIBAQCUBC2meZV0/9UAPPWu2JSxKXzAjwsLibmCg5duNyj1ohrP0pIL\n" \
-"m6jTh5RzhBCf3DXLwi2SrCG5yzv8QMHBgyHwv/j2nPqcghDA0I5O5Q1MsJFckLSk\n" \
-"QFEW2uSEEi0FXKEfFxkkUap66uEHG4aNAXLy59SDIzme4OFMH2sio7QQZrDtgpbX\n" \
-"bmq08j+1QvzdirWrui0dOnWbMdw+naxb00ENbLAb9Tr1eeohovj0M1JLJC0epJmx\n" \
-"bUi8uBL+cnB89/sCdfSN3tbawKAyGlLfOGsuRTg/PwSWAP2h9KK71RfWJ3wbWFmV\n" \
-"XooS/ZyrgT5SKEhRhWvzkbKGPym1bgNi7tYFAgMBAAGjggF1MIIBcTAfBgNVHSME\n" \
-"GDAWgBRTeb9aqitKz1SA4dibwJ3ysgNmyzAdBgNVHQ4EFgQUs5Cn2MmvTs1hPJ98\n" \
-"rV1/Qf1pMOowDgYDVR0PAQH/BAQDAgGGMBIGA1UdEwEB/wQIMAYBAf8CAQAwHQYD\n" \
-"VR0lBBYwFAYIKwYBBQUHAwEGCCsGAQUFBwMCMCIGA1UdIAQbMBkwDQYLKwYBBAGy\n" \
-"MQECAhowCAYGZ4EMAQIBMFAGA1UdHwRJMEcwRaBDoEGGP2h0dHA6Ly9jcmwudXNl\n" \
-"cnRydXN0LmNvbS9VU0VSVHJ1c3RSU0FDZXJ0aWZpY2F0aW9uQXV0aG9yaXR5LmNy\n" \
-"bDB2BggrBgEFBQcBAQRqMGgwPwYIKwYBBQUHMAKGM2h0dHA6Ly9jcnQudXNlcnRy\n" \
-"dXN0LmNvbS9VU0VSVHJ1c3RSU0FBZGRUcnVzdENBLmNydDAlBggrBgEFBQcwAYYZ\n" \
-"aHR0cDovL29jc3AudXNlcnRydXN0LmNvbTANBgkqhkiG9w0BAQwFAAOCAgEAWGf9\n" \
-"crJq13xhlhl+2UNG0SZ9yFP6ZrBrLafTqlb3OojQO3LJUP33WbKqaPWMcwO7lWUX\n" \
-"zi8c3ZgTopHJ7qFAbjyY1lzzsiI8Le4bpOHeICQW8owRc5E69vrOJAKHypPstLbI\n" \
-"FhfFcvwnQPYT/pOmnVHvPCvYd1ebjGU6NSU2t7WKY28HJ5OxYI2A25bUeo8tqxyI\n" \
-"yW5+1mUfr13KFj8oRtygNeX56eXVlogMT8a3d2dIhCe2H7Bo26y/d7CQuKLJHDJd\n" \
-"ArolQ4FCR7vY4Y8MDEZf7kYzawMUgtN+zY+vkNaOJH1AQrRqahfGlZfh8jjNp+20\n" \
-"J0CT33KpuMZmYzc4ZCIwojvxuch7yPspOqsactIGEk72gtQjbz7Dk+XYtsDe3CMW\n" \
-"1hMwt6CaDixVBgBwAc/qOR2A24j3pSC4W/0xJmmPLQphgzpHphNULB7j7UTKvGof\n" \
-"KA5R2d4On3XNDgOVyvnFqSot/kGkoUeuDcL5OWYzSlvhhChZbH2UF3bkRYKtcCD9\n" \
-"0m9jqNf6oDP6N8v3smWe2lBvP+Sn845dWDKXcCMu5/3EFZucJ48y7RetWIExKREa\n" \
-"m9T8bJUox04FB6b9HbwZ4ui3uRGKLXASUoWNjDNKD/yZkuBjcNqllEdjB+dYxzFf\n" \
-"BT02Vf6Dsuimrdfp5gJ0iHRc2jTbkNJtUQoj1iM=\n" \
-"-----END CERTIFICATE-----\n";
-
-// Not sure if WiFiClientSecure checks the validity date of the certificate. 
+#include <NetworkClientSecure.h>
+
+// This is a Google Trust Services cert, the root Certificate Authority that
+// signed the server certificate for the demo server https://jigsaw.w3.org in this
+// example. This certificate is valid until Jan 28 00:00:42 2028 GMT
+const char *rootCACertificate = R"string_literal(
+-----BEGIN CERTIFICATE-----
+MIIDejCCAmKgAwIBAgIQf+UwvzMTQ77dghYQST2KGzANBgkqhkiG9w0BAQsFADBX
+MQswCQYDVQQGEwJCRTEZMBcGA1UEChMQR2xvYmFsU2lnbiBudi1zYTEQMA4GA1UE
+CxMHUm9vdCBDQTEbMBkGA1UEAxMSR2xvYmFsU2lnbiBSb290IENBMB4XDTIzMTEx
+NTAzNDMyMVoXDTI4MDEyODAwMDA0MlowRzELMAkGA1UEBhMCVVMxIjAgBgNVBAoT
+GUdvb2dsZSBUcnVzdCBTZXJ2aWNlcyBMTEMxFDASBgNVBAMTC0dUUyBSb290IFI0
+MHYwEAYHKoZIzj0CAQYFK4EEACIDYgAE83Rzp2iLYK5DuDXFgTB7S0md+8Fhzube
+Rr1r1WEYNa5A3XP3iZEwWus87oV8okB2O6nGuEfYKueSkWpz6bFyOZ8pn6KY019e
+WIZlD6GEZQbR3IvJx3PIjGov5cSr0R2Ko4H/MIH8MA4GA1UdDwEB/wQEAwIBhjAd
+BgNVHSUEFjAUBggrBgEFBQcDAQYIKwYBBQUHAwIwDwYDVR0TAQH/BAUwAwEB/zAd
+BgNVHQ4EFgQUgEzW63T/STaj1dj8tT7FavCUHYwwHwYDVR0jBBgwFoAUYHtmGkUN
+l8qJUC99BM00qP/8/UswNgYIKwYBBQUHAQEEKjAoMCYGCCsGAQUFBzAChhpodHRw
+Oi8vaS5wa2kuZ29vZy9nc3IxLmNydDAtBgNVHR8EJjAkMCKgIKAehhxodHRwOi8v
+Yy5wa2kuZ29vZy9yL2dzcjEuY3JsMBMGA1UdIAQMMAowCAYGZ4EMAQIBMA0GCSqG
+SIb3DQEBCwUAA4IBAQAYQrsPBtYDh5bjP2OBDwmkoWhIDDkic574y04tfzHpn+cJ
+odI2D4SseesQ6bDrarZ7C30ddLibZatoKiws3UL9xnELz4ct92vID24FfVbiI1hY
++SW6FoVHkNeWIP0GCbaM4C6uVdF5dTUsMVs/ZbzNnIdCp5Gxmx5ejvEau8otR/Cs
+kGN+hr/W5GvT1tMBjgWKZ1i4//emhA1JG1BbPzoLJQvyEotc03lXjTaCzv8mEbep
+8RqZ7a2CPsgRbuvTPBwcOMBBmuFeU88+FSBX6+7iP0il8b4Z0QFqIwwMHfs/L6K1
+vepuoxtGzi4CZ68zJpiq1UvSqTbFJjtbD4seiMHl
+-----END CERTIFICATE-----
+)string_literal";
+
+// Not sure if NetworkClientSecure checks the validity date of the certificate.
 // Setting clock just to be sure...
 void setClock() {
-  configTime(0, 0, "pool.ntp.org", "time.nist.gov");
+  configTime(0, 0, "pool.ntp.org");
 
   Serial.print(F("Waiting for NTP time sync: "));
   time_t nowSecs = time(nullptr);
@@ -74,7 +62,6 @@ void setClock() {
   Serial.print(asctime(&timeinfo));
 }
 
-
 WiFiMulti WiFiMulti;
 
 void setup() {
@@ -96,29 +83,29 @@ void setup() {
   }
   Serial.println(" connected");
 
-  setClock();  
+  setClock();
 }
 
 void loop() {
-  WiFiClientSecure *client = new WiFiClientSecure;
-  if(client) {
-    client -> setCACert(rootCACertificate);
+  NetworkClientSecure *client = new NetworkClientSecure;
+  if (client) {
+    client->setCACert(rootCACertificate);
 
     {
-      // Add a scoping block for HTTPClient https to make sure it is destroyed before WiFiClientSecure *client is 
+      // Add a scoping block for HTTPClient https to make sure it is destroyed before NetworkClientSecure *client is
       HTTPClient https;
-  
+
       Serial.print("[HTTPS] begin...\n");
       if (https.begin(*client, "https://jigsaw.w3.org/HTTP/connection.html")) {  // HTTPS
         Serial.print("[HTTPS] GET...\n");
         // start connection and send HTTP header
         int httpCode = https.GET();
-  
+
         // httpCode will be negative on error
         if (httpCode > 0) {
           // HTTP header has been send and Server response header has been handled
           Serial.printf("[HTTPS] GET... code: %d\n", httpCode);
-  
+
           // file found at server
           if (httpCode == HTTP_CODE_OK || httpCode == HTTP_CODE_MOVED_PERMANENTLY) {
             String payload = https.getString();
@@ -127,7 +114,7 @@ void loop() {
         } else {
           Serial.printf("[HTTPS] GET... failed, error: %s\n", https.errorToString(httpCode).c_str());
         }
-  
+
         https.end();
       } else {
         Serial.printf("[HTTPS] Unable to connect\n");
@@ -135,7 +122,7 @@ void loop() {
 
       // End extra scoping block
     }
-  
+
     delete client;
   } else {
     Serial.println("Unable to create client");
diff --git a/libraries/HTTPClient/examples/BasicHttpsClient/ci.json b/libraries/HTTPClient/examples/BasicHttpsClient/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/HTTPClient/examples/BasicHttpsClient/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/HTTPClient/examples/HTTPClientEnterprise/HTTPClientEnterprise.ino b/libraries/HTTPClient/examples/HTTPClientEnterprise/HTTPClientEnterprise.ino
index b28501bb3ea..d8b66ac19d9 100644
--- a/libraries/HTTPClient/examples/HTTPClientEnterprise/HTTPClientEnterprise.ino
+++ b/libraries/HTTPClient/examples/HTTPClientEnterprise/HTTPClientEnterprise.ino
@@ -3,37 +3,46 @@
 /*|TESTED BOARDS: Devkit v1 DOIT, Devkitc v4                 |*/
 /*|CORE: June 2018                                           |*/
 /*|----------------------------------------------------------|*/
+
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#error "WPA-Enterprise is only supported in SoCs with native Wi-Fi support"
+#endif
+
 #include <WiFi.h>
 #include <HTTPClient.h>
+#if __has_include("esp_eap_client.h")
+#include "esp_eap_client.h"
+#else
 #include "esp_wpa2.h"
+#endif
 #include <Wire.h>
-#define EAP_IDENTITY "identity" //if connecting from another corporation, use identity@organisation.domain in Eduroam 
-#define EAP_PASSWORD "password" //your Eduroam password
-const char* ssid = "eduroam"; // Eduroam SSID
+#define EAP_IDENTITY "identity"  //if connecting from another corporation, use identity@organization.domain in Eduroam
+#define EAP_PASSWORD "password"  //your Eduroam password
+const char *ssid = "eduroam";    // Eduroam SSID
 int counter = 0;
-const char* test_root_ca= \
-"-----BEGIN CERTIFICATE-----\n" \
-"MIIDrzCCApegAwIBAgIQCDvgVpBCRrGhdWrJWZHHSjANBgkqhkiG9w0BAQUFADBh\n" \
-"MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3\n" \
-"d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBD\n" \
-"QTAeFw0wNjExMTAwMDAwMDBaFw0zMTExMTAwMDAwMDBaMGExCzAJBgNVBAYTAlVT\n" \
-"MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j\n" \
-"b20xIDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IENBMIIBIjANBgkqhkiG\n" \
-"9w0BAQEFAAOCAQ8AMIIBCgKCAQEA4jvhEXLeqKTTo1eqUKKPC3eQyaKl7hLOllsB\n" \
-"CSDMAZOnTjC3U/dDxGkAV53ijSLdhwZAAIEJzs4bg7/fzTtxRuLWZscFs3YnFo97\n" \
-"nh6Vfe63SKMI2tavegw5BmV/Sl0fvBf4q77uKNd0f3p4mVmFaG5cIzJLv07A6Fpt\n" \
-"43C/dxC//AH2hdmoRBBYMql1GNXRor5H4idq9Joz+EkIYIvUX7Q6hL+hqkpMfT7P\n" \
-"T19sdl6gSzeRntwi5m3OFBqOasv+zbMUZBfHWymeMr/y7vrTC0LUq7dBMtoM1O/4\n" \
-"gdW7jVg/tRvoSSiicNoxBN33shbyTApOB6jtSj1etX+jkMOvJwIDAQABo2MwYTAO\n" \
-"BgNVHQ8BAf8EBAMCAYYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUA95QNVbR\n" \
-"TLtm8KPiGxvDl7I90VUwHwYDVR0jBBgwFoAUA95QNVbRTLtm8KPiGxvDl7I90VUw\n" \
-"DQYJKoZIhvcNAQEFBQADggEBAMucN6pIExIK+t1EnE9SsPTfrgT1eXkIoyQY/Esr\n" \
-"hMAtudXH/vTBH1jLuG2cenTnmCmrEbXjcKChzUyImZOMkXDiqw8cvpOp/2PV5Adg\n" \
-"06O/nVsJ8dWO41P0jmP6P6fbtGbfYmbW0W5BjfIttep3Sp+dWOIrWcBAI+0tKIJF\n" \
-"PnlUkiaY4IBIqDfv8NZ5YBberOgOzW6sRBc4L0na4UU+Krk2U886UAb3LujEV0ls\n" \
-"YSEY1QSteDwsOoBrp+uvFRTp2InBuThs4pFsiv9kuXclVzDAGySj4dzp30d8tbQk\n" \
-"CAUw7C29C79Fv1C5qfPrmAESrciIxpg0X40KPMbp1ZWVbd4=\n" \
-"-----END CERTIFICATE-----\n";
+const char *test_root_ca = "-----BEGIN CERTIFICATE-----\n"
+                           "MIIDrzCCApegAwIBAgIQCDvgVpBCRrGhdWrJWZHHSjANBgkqhkiG9w0BAQUFADBh\n"
+                           "MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3\n"
+                           "d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBD\n"
+                           "QTAeFw0wNjExMTAwMDAwMDBaFw0zMTExMTAwMDAwMDBaMGExCzAJBgNVBAYTAlVT\n"
+                           "MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j\n"
+                           "b20xIDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IENBMIIBIjANBgkqhkiG\n"
+                           "9w0BAQEFAAOCAQ8AMIIBCgKCAQEA4jvhEXLeqKTTo1eqUKKPC3eQyaKl7hLOllsB\n"
+                           "CSDMAZOnTjC3U/dDxGkAV53ijSLdhwZAAIEJzs4bg7/fzTtxRuLWZscFs3YnFo97\n"
+                           "nh6Vfe63SKMI2tavegw5BmV/Sl0fvBf4q77uKNd0f3p4mVmFaG5cIzJLv07A6Fpt\n"
+                           "43C/dxC//AH2hdmoRBBYMql1GNXRor5H4idq9Joz+EkIYIvUX7Q6hL+hqkpMfT7P\n"
+                           "T19sdl6gSzeRntwi5m3OFBqOasv+zbMUZBfHWymeMr/y7vrTC0LUq7dBMtoM1O/4\n"
+                           "gdW7jVg/tRvoSSiicNoxBN33shbyTApOB6jtSj1etX+jkMOvJwIDAQABo2MwYTAO\n"
+                           "BgNVHQ8BAf8EBAMCAYYwDwYDVR0TAQH/BAUwAwEB/zAdBgNVHQ4EFgQUA95QNVbR\n"
+                           "TLtm8KPiGxvDl7I90VUwHwYDVR0jBBgwFoAUA95QNVbRTLtm8KPiGxvDl7I90VUw\n"
+                           "DQYJKoZIhvcNAQEFBQADggEBAMucN6pIExIK+t1EnE9SsPTfrgT1eXkIoyQY/Esr\n"
+                           "hMAtudXH/vTBH1jLuG2cenTnmCmrEbXjcKChzUyImZOMkXDiqw8cvpOp/2PV5Adg\n"
+                           "06O/nVsJ8dWO41P0jmP6P6fbtGbfYmbW0W5BjfIttep3Sp+dWOIrWcBAI+0tKIJF\n"
+                           "PnlUkiaY4IBIqDfv8NZ5YBberOgOzW6sRBc4L0na4UU+Krk2U886UAb3LujEV0ls\n"
+                           "YSEY1QSteDwsOoBrp+uvFRTp2InBuThs4pFsiv9kuXclVzDAGySj4dzp30d8tbQk\n"
+                           "CAUw7C29C79Fv1C5qfPrmAESrciIxpg0X40KPMbp1ZWVbd4=\n"
+                           "-----END CERTIFICATE-----\n";
 void setup() {
   Serial.begin(115200);
   delay(10);
@@ -41,58 +50,64 @@ void setup() {
   Serial.print("Connecting to network: ");
   Serial.println(ssid);
   WiFi.disconnect(true);  //disconnect form wifi to set new wifi connection
-  WiFi.mode(WIFI_STA); //init wifi mode
-  esp_wifi_sta_wpa2_ent_set_identity((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY)); //provide identity
-  esp_wifi_sta_wpa2_ent_set_username((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY)); //provide username --> identity and username is same
-  esp_wifi_sta_wpa2_ent_set_password((uint8_t *)EAP_PASSWORD, strlen(EAP_PASSWORD)); //provide password
-  esp_wpa2_config_t config = WPA2_CONFIG_INIT_DEFAULT(); //set config settings to default
-  esp_wifi_sta_wpa2_ent_enable(&config); //set config settings to enable function
-  WiFi.begin(ssid); //connect to wifi
+  WiFi.mode(WIFI_STA);    //init wifi mode
+#if __has_include("esp_eap_client.h")
+  esp_eap_client_set_identity((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY));  //provide identity
+  esp_eap_client_set_username((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY));  //provide username
+  esp_eap_client_set_password((uint8_t *)EAP_PASSWORD, strlen(EAP_PASSWORD));  //provide password
+  esp_wifi_sta_enterprise_enable();
+#else
+  esp_wifi_sta_wpa2_ent_set_identity((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY));  //provide identity
+  esp_wifi_sta_wpa2_ent_set_username((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY));  //provide username --> identity and username is same
+  esp_wifi_sta_wpa2_ent_set_password((uint8_t *)EAP_PASSWORD, strlen(EAP_PASSWORD));  //provide password
+  esp_wifi_sta_wpa2_ent_enable();
+#endif
+  WiFi.begin(ssid);  //connect to wifi
   while (WiFi.status() != WL_CONNECTED) {
     delay(500);
     Serial.print(".");
     counter++;
-    if(counter>=60){ //after 30 seconds timeout - reset board
+    if (counter >= 60) {  //after 30 seconds timeout - reset board
       ESP.restart();
     }
   }
   Serial.println("");
   Serial.println("WiFi connected");
-  Serial.println("IP address set: "); 
-  Serial.println(WiFi.localIP()); //print LAN IP
+  Serial.println("IP address set: ");
+  Serial.println(WiFi.localIP());  //print LAN IP
 }
 void loop() {
-  if (WiFi.status() == WL_CONNECTED) { //if we are connected to Eduroam network
-    counter = 0; //reset counter
-    Serial.println("Wifi is still connected with IP: "); 
-    Serial.println(WiFi.localIP());   //inform user about his IP address
-  }else if (WiFi.status() != WL_CONNECTED) { //if we lost connection, retry
-    WiFi.begin(ssid);      
+  if (WiFi.status() == WL_CONNECTED) {  //if we are connected to Eduroam network
+    counter = 0;                        //reset counter
+    Serial.println("Wifi is still connected with IP: ");
+    Serial.println(WiFi.localIP());            //inform user about his IP address
+  } else if (WiFi.status() != WL_CONNECTED) {  //if we lost connection, retry
+    WiFi.begin(ssid);
   }
-  while (WiFi.status() != WL_CONNECTED) { //during lost connection, print dots
+  while (WiFi.status() != WL_CONNECTED) {  //during lost connection, print dots
     delay(500);
     Serial.print(".");
     counter++;
-    if(counter>=60){ //30 seconds timeout - reset board
-    ESP.restart();
+    if (counter >= 60) {  //30 seconds timeout - reset board
+      ESP.restart();
     }
   }
   Serial.print("Connecting to website: ");
-    HTTPClient http;
-    http.begin("https://arduino.php5.sk/rele/rele1.txt", test_root_ca); //HTTPS example connection
-    //http.begin("http://www.arduino.php5.sk/rele/rele1.txt"); //HTTP example connection
-    //if uncomment HTTP example, you can comment root CA certificate too!
-    int httpCode = http.GET();
-    if(httpCode > 0) {
-      Serial.printf("[HTTP] GET... code: %d\n", httpCode);
-      //file found at server --> on unsucessful connection code will be -1
-      if(httpCode == HTTP_CODE_OK) {
-        String payload = http.getString();
-        Serial.println(payload);
-      }
-     }else{
-      Serial.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
-      }
-  http.end();  
+  HTTPClient http;
+  http.begin("https://arduino.php5.sk/rele/rele1.txt", test_root_ca);  //HTTPS example connection
+  //http.begin("http://www.arduino.php5.sk/rele/rele1.txt"); //HTTP example connection
+  //if uncomment HTTP example, you can comment root CA certificate too!
+  int httpCode = http.GET();
+  if (httpCode > 0) {
+    Serial.printf("[HTTP] GET... code: %d\n", httpCode);
+    //file found at server --> on unsuccessful connection code will be -1
+    if (httpCode == HTTP_CODE_OK) {
+      String payload = http.getString();
+      Serial.println(payload);
+    }
+  } else {
+    Serial.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
+  }
+  http.end();
   delay(2000);
 }
diff --git a/libraries/HTTPClient/examples/HTTPClientEnterprise/ci.json b/libraries/HTTPClient/examples/HTTPClientEnterprise/ci.json
new file mode 100644
index 00000000000..04eb62b977a
--- /dev/null
+++ b/libraries/HTTPClient/examples/HTTPClientEnterprise/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/HTTPClient/examples/ReuseConnection/ReuseConnection.ino b/libraries/HTTPClient/examples/ReuseConnection/ReuseConnection.ino
index d3bcefbeb17..5b3137a0179 100644
--- a/libraries/HTTPClient/examples/ReuseConnection/ReuseConnection.ino
+++ b/libraries/HTTPClient/examples/ReuseConnection/ReuseConnection.ino
@@ -5,7 +5,6 @@
  *
  */
 
-
 #include <Arduino.h>
 
 #include <WiFi.h>
@@ -21,48 +20,45 @@ HTTPClient http;
 
 void setup() {
 
-    USE_SERIAL.begin(115200);
+  USE_SERIAL.begin(115200);
 
-    USE_SERIAL.println();
-    USE_SERIAL.println();
-    USE_SERIAL.println();
+  USE_SERIAL.println();
+  USE_SERIAL.println();
+  USE_SERIAL.println();
 
-    for(uint8_t t = 4; t > 0; t--) {
-        USE_SERIAL.printf("[SETUP] WAIT %d...\n", t);
-        USE_SERIAL.flush();
-        delay(1000);
-    }
+  for (uint8_t t = 4; t > 0; t--) {
+    USE_SERIAL.printf("[SETUP] WAIT %d...\n", t);
+    USE_SERIAL.flush();
+    delay(1000);
+  }
 
-    wifiMulti.addAP("SSID", "PASSWORD");
+  wifiMulti.addAP("SSID", "PASSWORD");
 
-    // allow reuse (if server supports it)
-    http.setReuse(true);
+  // allow reuse (if server supports it)
+  http.setReuse(true);
 }
 
 void loop() {
-    // wait for WiFi connection
-    if((wifiMulti.run() == WL_CONNECTED)) {
-
-        http.begin("http://192.168.1.12/test.html");
-        //http.begin("192.168.1.12", 80, "/test.html");
-
-        int httpCode = http.GET();
-        if(httpCode > 0) {
-            USE_SERIAL.printf("[HTTP] GET... code: %d\n", httpCode);
-
-            // file found at server
-            if(httpCode == HTTP_CODE_OK) {
-                http.writeToStream(&USE_SERIAL);
-            }
-        } else {
-            USE_SERIAL.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
-        }
-
-        http.end();
+  // wait for WiFi connection
+  if ((wifiMulti.run() == WL_CONNECTED)) {
+
+    http.begin("http://192.168.1.12/test.html");
+    //http.begin("192.168.1.12", 80, "/test.html");
+
+    int httpCode = http.GET();
+    if (httpCode > 0) {
+      USE_SERIAL.printf("[HTTP] GET... code: %d\n", httpCode);
+
+      // file found at server
+      if (httpCode == HTTP_CODE_OK) {
+        http.writeToStream(&USE_SERIAL);
+      }
+    } else {
+      USE_SERIAL.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
     }
 
-    delay(1000);
-}
-
-
+    http.end();
+  }
 
+  delay(1000);
+}
diff --git a/libraries/HTTPClient/examples/ReuseConnection/ci.json b/libraries/HTTPClient/examples/ReuseConnection/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/HTTPClient/examples/ReuseConnection/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/HTTPClient/examples/StreamHttpClient/StreamHttpClient.ino b/libraries/HTTPClient/examples/StreamHttpClient/StreamHttpClient.ino
index 6ea07f660c1..187526f6300 100644
--- a/libraries/HTTPClient/examples/StreamHttpClient/StreamHttpClient.ino
+++ b/libraries/HTTPClient/examples/StreamHttpClient/StreamHttpClient.ino
@@ -18,83 +18,80 @@ WiFiMulti wifiMulti;
 
 void setup() {
 
-    USE_SERIAL.begin(115200);
+  USE_SERIAL.begin(115200);
 
-    USE_SERIAL.println();
-    USE_SERIAL.println();
-    USE_SERIAL.println();
+  USE_SERIAL.println();
+  USE_SERIAL.println();
+  USE_SERIAL.println();
 
-    for(uint8_t t = 4; t > 0; t--) {
-        USE_SERIAL.printf("[SETUP] WAIT %d...\n", t);
-        USE_SERIAL.flush();
-        delay(1000);
-    }
-
-    wifiMulti.addAP("SSID", "PASSWORD");
+  for (uint8_t t = 4; t > 0; t--) {
+    USE_SERIAL.printf("[SETUP] WAIT %d...\n", t);
+    USE_SERIAL.flush();
+    delay(1000);
+  }
 
+  wifiMulti.addAP("SSID", "PASSWORD");
 }
 
 void loop() {
-    // wait for WiFi connection
-    if((wifiMulti.run() == WL_CONNECTED)) {
-
-        HTTPClient http;
+  // wait for WiFi connection
+  if ((wifiMulti.run() == WL_CONNECTED)) {
 
-        USE_SERIAL.print("[HTTP] begin...\n");
+    HTTPClient http;
 
-        // configure server and url
-        http.begin("http://192.168.1.12/test.html");
-        //http.begin("192.168.1.12", 80, "/test.html");
+    USE_SERIAL.print("[HTTP] begin...\n");
 
-        USE_SERIAL.print("[HTTP] GET...\n");
-        // start connection and send HTTP header
-        int httpCode = http.GET();
-        if(httpCode > 0) {
-            // HTTP header has been send and Server response header has been handled
-            USE_SERIAL.printf("[HTTP] GET... code: %d\n", httpCode);
+    // configure server and url
+    http.begin("http://192.168.1.12/test.html");
+    //http.begin("192.168.1.12", 80, "/test.html");
 
-            // file found at server
-            if(httpCode == HTTP_CODE_OK) {
+    USE_SERIAL.print("[HTTP] GET...\n");
+    // start connection and send HTTP header
+    int httpCode = http.GET();
+    if (httpCode > 0) {
+      // HTTP header has been send and Server response header has been handled
+      USE_SERIAL.printf("[HTTP] GET... code: %d\n", httpCode);
 
-                // get lenght of document (is -1 when Server sends no Content-Length header)
-                int len = http.getSize();
+      // file found at server
+      if (httpCode == HTTP_CODE_OK) {
 
-                // create buffer for read
-                uint8_t buff[128] = { 0 };
+        // get length of document (is -1 when Server sends no Content-Length header)
+        int len = http.getSize();
 
-                // get tcp stream
-                WiFiClient * stream = http.getStreamPtr();
+        // create buffer for read
+        uint8_t buff[128] = {0};
 
-                // read all data from server
-                while(http.connected() && (len > 0 || len == -1)) {
-                    // get available data size
-                    size_t size = stream->available();
+        // get tcp stream
+        NetworkClient *stream = http.getStreamPtr();
 
-                    if(size) {
-                        // read up to 128 byte
-                        int c = stream->readBytes(buff, ((size > sizeof(buff)) ? sizeof(buff) : size));
+        // read all data from server
+        while (http.connected() && (len > 0 || len == -1)) {
+          // get available data size
+          size_t size = stream->available();
 
-                        // write it to Serial
-                        USE_SERIAL.write(buff, c);
+          if (size) {
+            // read up to 128 byte
+            int c = stream->readBytes(buff, ((size > sizeof(buff)) ? sizeof(buff) : size));
 
-                        if(len > 0) {
-                            len -= c;
-                        }
-                    }
-                    delay(1);
-                }
-
-                USE_SERIAL.println();
-                USE_SERIAL.print("[HTTP] connection closed or file end.\n");
+            // write it to Serial
+            USE_SERIAL.write(buff, c);
 
+            if (len > 0) {
+              len -= c;
             }
-        } else {
-            USE_SERIAL.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
+          }
+          delay(1);
         }
 
-        http.end();
+        USE_SERIAL.println();
+        USE_SERIAL.print("[HTTP] connection closed or file end.\n");
+      }
+    } else {
+      USE_SERIAL.printf("[HTTP] GET... failed, error: %s\n", http.errorToString(httpCode).c_str());
     }
 
-    delay(10000);
-}
+    http.end();
+  }
 
+  delay(10000);
+}
diff --git a/libraries/HTTPClient/examples/StreamHttpClient/ci.json b/libraries/HTTPClient/examples/StreamHttpClient/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/HTTPClient/examples/StreamHttpClient/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/HTTPClient/library.properties b/libraries/HTTPClient/library.properties
index 153a2e2575d..f2dafc36d1b 100644
--- a/libraries/HTTPClient/library.properties
+++ b/libraries/HTTPClient/library.properties
@@ -1,5 +1,5 @@
 name=HTTPClient
-version=1.2
+version=3.2.0
 author=Markus Sattler
 maintainer=Markus Sattler
 sentence=HTTP Client for ESP32
diff --git a/libraries/HTTPClient/src/HTTPClient.cpp b/libraries/HTTPClient/src/HTTPClient.cpp
index 49b941696f0..ec812f07201 100644
--- a/libraries/HTTPClient/src/HTTPClient.cpp
+++ b/libraries/HTTPClient/src/HTTPClient.cpp
@@ -6,8 +6,8 @@
  *
  * Copyright (c) 2015 Markus Sattler. All rights reserved.
  * This file is part of the HTTPClient for Arduino.
- * Port to ESP32 by Evandro Luis Copercini (2017), 
- * changed fingerprints to CA verification. 												 
+ * Port to ESP32 by Evandro Luis Copercini (2017),
+ * changed fingerprints to CA verification.
  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public
@@ -27,94 +27,86 @@
  */
 
 #include <Arduino.h>
-#include <esp32-hal-log.h>  
-
-#ifdef HTTPCLIENT_1_1_COMPATIBLE
-#include <WiFi.h>
-#include <WiFiClientSecure.h>
-#endif
-
+#include <esp32-hal-log.h>
 #include <StreamString.h>
 #include <base64.h>
-
 #include "HTTPClient.h"
 
+/// Cookie jar support
+#include <time.h>
+
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-class TransportTraits
-{
+class TransportTraits {
 public:
-    virtual ~TransportTraits()
-    {
-    }
+  virtual ~TransportTraits() {}
 
-    virtual std::unique_ptr<WiFiClient> create()
-    {
-        return std::unique_ptr<WiFiClient>(new WiFiClient());
-    }
+  virtual std::unique_ptr<NetworkClient> create() {
+    return std::unique_ptr<NetworkClient>(new NetworkClient());
+  }
 
-    virtual bool verify(WiFiClient& client, const char* host)
-    {
-        return true;
-    }
+  virtual bool verify(NetworkClient &client, const char *host) {
+    return true;
+  }
 };
 
-class TLSTraits : public TransportTraits
-{
+#ifndef HTTPCLIENT_NOSECURE
+class TLSTraits : public TransportTraits {
 public:
-    TLSTraits(const char* CAcert, const char* clicert = nullptr, const char* clikey = nullptr) :
-        _cacert(CAcert), _clicert(clicert), _clikey(clikey)
-    {
-    }
+  TLSTraits(const char *CAcert, const char *clicert = nullptr, const char *clikey = nullptr) : _cacert(CAcert), _clicert(clicert), _clikey(clikey) {}
 
-    std::unique_ptr<WiFiClient> create() override
-    {
-        return std::unique_ptr<WiFiClient>(new WiFiClientSecure());
-    }
+  std::unique_ptr<NetworkClient> create() override {
+    return std::unique_ptr<NetworkClient>(new NetworkClientSecure());
+  }
 
-    bool verify(WiFiClient& client, const char* host) override
-    {
-         WiFiClientSecure& wcs = static_cast<WiFiClientSecure&>(client);
-         wcs.setCACert(_cacert);
-         wcs.setCertificate(_clicert);
-         wcs.setPrivateKey(_clikey);
-         return true;
+  bool verify(NetworkClient &client, const char *host) override {
+    NetworkClientSecure &wcs = static_cast<NetworkClientSecure &>(client);
+    if (_cacert == nullptr) {
+      wcs.setInsecure();
+    } else {
+      wcs.setCACert(_cacert);
+      wcs.setCertificate(_clicert);
+      wcs.setPrivateKey(_clikey);
     }
+    return true;
+  }
 
 protected:
-    const char* _cacert;
-    const char* _clicert;
-    const char* _clikey;
+  const char *_cacert;
+  const char *_clicert;
+  const char *_clikey;
 };
-#endif // HTTPCLIENT_1_1_COMPATIBLE
+#endif  // HTTPCLIENT_NOSECURE
+#endif  // HTTPCLIENT_1_1_COMPATIBLE
 
 /**
  * constructor
  */
-HTTPClient::HTTPClient()
-{
-}
+HTTPClient::HTTPClient() {}
 
 /**
  * destructor
  */
-HTTPClient::~HTTPClient()
-{
-    if(_client) {
-        _client->stop();
-    }
-    if(_currentHeaders) {
-        delete[] _currentHeaders;
-    }
+HTTPClient::~HTTPClient() {
+  if (_client) {
+    _client->stop();
+  }
+  if (_currentHeaders) {
+    delete[] _currentHeaders;
+  }
+  if (_tcpDeprecated) {
+    _tcpDeprecated.reset(nullptr);
+  }
+  if (_transportTraits) {
+    _transportTraits.reset(nullptr);
+  }
 }
 
-void HTTPClient::clear()
-{
-    _returnCode = 0;
-    _size = -1;
-    _headers = "";
+void HTTPClient::clear() {
+  _returnCode = 0;
+  _size = -1;
+  _headers = "";
 }
 
-
 /**
  * parsing the url for all needed parameters
  * @param client Client&
@@ -122,34 +114,40 @@ void HTTPClient::clear()
  * @param https bool
  * @return success bool
  */
-bool HTTPClient::begin(WiFiClient &client, String url) {
+bool HTTPClient::begin(NetworkClient &client, String url) {
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-    if(_tcpDeprecated) {
-        log_d("mix up of new and deprecated api");
-        _canReuse = false;
-        end();
-    }
+  if (_tcpDeprecated) {
+    log_d("mix up of new and deprecated api");
+    _canReuse = false;
+    end();
+  }
 #endif
 
-    _client = &client;
+  _client = &client;
 
-    // check for : (http: or https:)
-    int index = url.indexOf(':');
-    if(index < 0) {
-        log_d("failed to parse protocol");
-        return false;
-    }
+  // check for : (http: or https:)
+  int index = url.indexOf(':');
+  if (index < 0) {
+    log_d("failed to parse protocol");
+    return false;
+  }
 
-    String protocol = url.substring(0, index);
-    if(protocol != "http" && protocol != "https") {
-        log_d("unknown protocol '%s'", protocol.c_str());
-        return false;
-    }
+  String protocol = url.substring(0, index);
+  if (protocol != "http" && protocol != "https") {
+    log_d("unknown protocol '%s'", protocol.c_str());
+    return false;
+  }
 
-    _port = (protocol == "https" ? 443 : 80);
-    return beginInternal(url, protocol.c_str());
-}
+  _port = (protocol == "https" ? 443 : 80);
+  _secure = (protocol == "https");
 
+#ifdef HTTPCLIENT_NOSECURE
+  if (_secure) {
+    return false;
+  }
+#endif  // HTTPCLIENT_NOSECURE
+  return beginInternal(url, protocol.c_str());
+}
 
 /**
  * directly supply all needed parameters
@@ -160,241 +158,251 @@ bool HTTPClient::begin(WiFiClient &client, String url) {
  * @param https bool
  * @return success bool
  */
-bool HTTPClient::begin(WiFiClient &client, String host, uint16_t port, String uri, bool https)
-{
+bool HTTPClient::begin(NetworkClient &client, String host, uint16_t port, String uri, bool https) {
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-    if(_tcpDeprecated) {
-        log_d("mix up of new and deprecated api");
-        _canReuse = false;
-        end();
-    }
+  if (_tcpDeprecated) {
+    log_d("mix up of new and deprecated api");
+    _canReuse = false;
+    end();
+  }
 #endif
 
-    _client = &client;
+  _client = &client;
 
-     clear();
-    _host = host;
-    _port = port;
-    _uri = uri;
-    _protocol = (https ? "https" : "http");
-    return true;
-}
+  clear();
+  _host = host;
+  _port = port;
+  _uri = uri;
+  _protocol = (https ? "https" : "http");
+  _secure = https;
 
+#ifdef HTTPCLIENT_NOSECURE
+  return _secure ? false : true;
+#else
+  return true;
+#endif  // HTTPCLIENT_NOSECURE
+}
 
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-bool HTTPClient::begin(String url, const char* CAcert)
-{
-    if(_client && !_tcpDeprecated) {
-        log_d("mix up of new and deprecated api");
-        _canReuse = false;
-        end();
-    }
-
-    _port = 443;
-    if (!beginInternal(url, "https")) {
-        return false;
-    }
-    _secure = true;
-    _transportTraits = TransportTraitsPtr(new TLSTraits(CAcert));
-    if(!_transportTraits) {
-        log_e("could not create transport traits");
-        return false;
-    }
+#ifndef HTTPCLIENT_NOSECURE
+bool HTTPClient::begin(String url, const char *CAcert) {
+  if (_client && !_tcpDeprecated) {
+    log_d("mix up of new and deprecated api");
+    _canReuse = false;
+    end();
+  }
+
+  clear();
+  _port = 443;
+  if (!beginInternal(url, "https")) {
+    return false;
+  }
+  _secure = true;
+  _transportTraits = TransportTraitsPtr(new TLSTraits(CAcert));
+  if (!_transportTraits) {
+    log_e("could not create transport traits");
+    return false;
+  }
 
-    return true;
+  return true;
 }
+#endif  // HTTPCLIENT_NOSECURE
 
 /**
  * parsing the url for all needed parameters
  * @param url String
  */
-bool HTTPClient::begin(String url)
-{
-    if(_client && !_tcpDeprecated) {
-        log_d("mix up of new and deprecated api");
-        _canReuse = false;
-        end();
-    }
-
-    _port = 80;
-    if (!beginInternal(url, "http")) {
-        return begin(url, (const char*)NULL);
-    }
-    _transportTraits = TransportTraitsPtr(new TransportTraits());
-    if(!_transportTraits) {
-        log_e("could not create transport traits");
-        return false;
-    }
+bool HTTPClient::begin(String url) {
+  if (_client && !_tcpDeprecated) {
+    log_d("mix up of new and deprecated api");
+    _canReuse = false;
+    end();
+  }
+
+  clear();
+  _port = 80;
+  if (!beginInternal(url, "http")) {
+#ifdef HTTPCLIENT_NOSECURE
+    return false;
+#else
+    return begin(url, (const char *)NULL);
+#endif  // HTTPCLIENT_NOSECURE
+  }
+  _transportTraits = TransportTraitsPtr(new TransportTraits());
+  if (!_transportTraits) {
+    log_e("could not create transport traits");
+    return false;
+  }
 
-    return true;
+  return true;
 }
-#endif // HTTPCLIENT_1_1_COMPATIBLE
-
-bool HTTPClient::beginInternal(String url, const char* expectedProtocol)
-{
-    log_v("url: %s", url.c_str());
-    clear();
-
-    // check for : (http: or https:
-    int index = url.indexOf(':');
-    if(index < 0) {
-        log_e("failed to parse protocol");
-        return false;
-    }
-
-    _protocol = url.substring(0, index);
-    if (_protocol != expectedProtocol) {
-        log_w("unexpected protocol: %s, expected %s", _protocol.c_str(), expectedProtocol);
-        return false;
-    }
-
-    url.remove(0, (index + 3)); // remove http:// or https://
+#endif  // HTTPCLIENT_1_1_COMPATIBLE
 
-    index = url.indexOf('/');
-    String host = url.substring(0, index);
-    url.remove(0, index); // remove host part
+bool HTTPClient::beginInternal(String url, const char *expectedProtocol) {
+  log_v("url: %s", url.c_str());
 
-    // get Authorization
-    index = host.indexOf('@');
-    if(index >= 0) {
-        // auth info
-        String auth = host.substring(0, index);
-        host.remove(0, index + 1); // remove auth part including @
-        _base64Authorization = base64::encode(auth);
-    }
+  // check for : (http: or https:
+  int index = url.indexOf(':');
+  if (index < 0) {
+    log_e("failed to parse protocol");
+    return false;
+  }
 
-    // get port
-    index = host.indexOf(':');
-    if(index >= 0) {
-        _host = host.substring(0, index); // hostname
-        host.remove(0, (index + 1)); // remove hostname + :
-        _port = host.toInt(); // get port
-    } else {
-        _host = host;
-    }
-    _uri = url;
-    log_d("host: %s port: %d url: %s", _host.c_str(), _port, _uri.c_str());
-    return true;
+  _protocol = url.substring(0, index);
+  if (_protocol != expectedProtocol) {
+    log_d("unexpected protocol: %s, expected %s", _protocol.c_str(), expectedProtocol);
+    return false;
+  }
+
+  url.remove(0, (index + 3));  // remove http:// or https://
+
+  index = url.indexOf('/');
+  if (index == -1) {
+    index = url.length();
+    url += '/';
+  }
+  String host = url.substring(0, index);
+  url.remove(0, index);  // remove host part
+
+  // get Authorization
+  index = host.indexOf('@');
+  if (index >= 0) {
+    // auth info
+    String auth = host.substring(0, index);
+    host.remove(0, index + 1);  // remove auth part including @
+    _base64Authorization = base64::encode(auth);
+  }
+
+  // get port
+  index = host.indexOf(':');
+  String the_host;
+  if (index >= 0) {
+    the_host = host.substring(0, index);  // hostname
+    host.remove(0, (index + 1));          // remove hostname + :
+    _port = host.toInt();                 // get port
+  } else {
+    the_host = host;
+  }
+  if (_host != the_host && connected()) {
+    log_d("switching host from '%s' to '%s'. disconnecting first", _host.c_str(), the_host.c_str());
+    _canReuse = false;
+    disconnect(true);
+  }
+  _host = the_host;
+  _uri = url;
+  log_d("protocol: %s, host: %s port: %d url: %s", _protocol.c_str(), _host.c_str(), _port, _uri.c_str());
+  return true;
 }
 
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-bool HTTPClient::begin(String host, uint16_t port, String uri)
-{
-    if(_client && !_tcpDeprecated) {
-        log_d("mix up of new and deprecated api");
-        _canReuse = false;
-        end();
-    }
-
-    clear();
-    _host = host;
-    _port = port;
-    _uri = uri;
-    _transportTraits = TransportTraitsPtr(new TransportTraits());
-    log_d("host: %s port: %d uri: %s", host.c_str(), port, uri.c_str());
-    return true;
+bool HTTPClient::begin(String host, uint16_t port, String uri) {
+  if (_client && !_tcpDeprecated) {
+    log_d("mix up of new and deprecated api");
+    _canReuse = false;
+    end();
+  }
+
+  clear();
+  _host = host;
+  _port = port;
+  _uri = uri;
+  _transportTraits = TransportTraitsPtr(new TransportTraits());
+  log_d("host: %s port: %d uri: %s", host.c_str(), port, uri.c_str());
+  return true;
 }
 
-bool HTTPClient::begin(String host, uint16_t port, String uri, const char* CAcert)
-{
-    if(_client && !_tcpDeprecated) {
-        log_d("mix up of new and deprecated api");
-        _canReuse = false;
-        end();
-    }
+#ifndef HTTPCLIENT_NOSECURE
+bool HTTPClient::begin(String host, uint16_t port, String uri, const char *CAcert) {
+  if (_client && !_tcpDeprecated) {
+    log_d("mix up of new and deprecated api");
+    _canReuse = false;
+    end();
+  }
 
-    clear();
-    _host = host;
-    _port = port;
-    _uri = uri;
+  clear();
+  _host = host;
+  _port = port;
+  _uri = uri;
 
-    if (strlen(CAcert) == 0) {
-        return false;
-    }
-    _secure = true;
-    _transportTraits = TransportTraitsPtr(new TLSTraits(CAcert));
-    return true;
+  if (strlen(CAcert) == 0) {
+    return false;
+  }
+  _secure = true;
+  _transportTraits = TransportTraitsPtr(new TLSTraits(CAcert));
+  return true;
 }
 
-bool HTTPClient::begin(String host, uint16_t port, String uri, const char* CAcert, const char* cli_cert, const char* cli_key)
-{
-    if(_client && !_tcpDeprecated) {
-        log_d("mix up of new and deprecated api");
-        _canReuse = false;
-        end();
-    }
+bool HTTPClient::begin(String host, uint16_t port, String uri, const char *CAcert, const char *cli_cert, const char *cli_key) {
+  if (_client && !_tcpDeprecated) {
+    log_d("mix up of new and deprecated api");
+    _canReuse = false;
+    end();
+  }
 
-    clear();
-    _host = host;
-    _port = port;
-    _uri = uri;
+  clear();
+  _host = host;
+  _port = port;
+  _uri = uri;
 
-    if (strlen(CAcert) == 0) {
-        return false;
-    }
-    _secure = true;
-    _transportTraits = TransportTraitsPtr(new TLSTraits(CAcert, cli_cert, cli_key));
-    return true;
+  if (strlen(CAcert) == 0) {
+    return false;
+  }
+  _secure = true;
+  _transportTraits = TransportTraitsPtr(new TLSTraits(CAcert, cli_cert, cli_key));
+  return true;
 }
-#endif // HTTPCLIENT_1_1_COMPATIBLE
+#endif  // HTTPCLIENT_NOSECURE
+#endif  // HTTPCLIENT_1_1_COMPATIBLE
 
 /**
  * end
  * called after the payload is handled
  */
-void HTTPClient::end(void)
-{
-    disconnect(false);
-    clear();
+void HTTPClient::end(void) {
+  disconnect(false);
+  clear();
 }
 
-
-
 /**
  * disconnect
  * close the TCP socket
  */
-void HTTPClient::disconnect(bool preserveClient)
-{
-    if(connected()) {
-        if(_client->available() > 0) {
-            log_d("still data in buffer (%d), clean up.\n", _client->available());
-            while(_client->available() > 0) {
-                _client->read();
-            }
-        }
+void HTTPClient::disconnect(bool preserveClient) {
+  if (connected()) {
+    if (_client->available() > 0) {
+      log_d("still data in buffer (%d), clean up.\n", _client->available());
+      _client->clear();
+    }
 
-        if(_reuse && _canReuse) {
-            log_d("tcp keep open for reuse\n");
-        } else {
-            log_d("tcp stop\n");
-            _client->stop();
-            if(!preserveClient) {
-                _client = nullptr;
-            }
+    if (_reuse && _canReuse) {
+      log_d("tcp keep open for reuse");
+    } else {
+      log_d("tcp stop");
+      _client->stop();
+      if (!preserveClient) {
+        _client = nullptr;
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-            if(_tcpDeprecated) {
-                _transportTraits.reset(nullptr);
-                _tcpDeprecated.reset(nullptr);
-            }
-#endif
+        if (_tcpDeprecated) {
+          _transportTraits.reset(nullptr);
+          _tcpDeprecated.reset(nullptr);
         }
-    } else {
-        log_d("tcp is closed\n");
+#endif
+      }
     }
+  } else {
+    log_d("tcp is closed\n");
+  }
 }
 
-
 /**
  * connected
  * @return connected status
  */
-bool HTTPClient::connected()
-{
-    if(_client) {
-        return ((_client->available() > 0) || _client->connected());
-    }
-    return false;
+bool HTTPClient::connected() {
+  if (_client) {
+    return ((_client->available() > 0) || _client->connected());
+  }
+  return false;
 }
 
 /**
@@ -402,18 +410,24 @@ bool HTTPClient::connected()
  * keep-alive
  * @param reuse bool
  */
-void HTTPClient::setReuse(bool reuse)
-{
-    _reuse = reuse;
+void HTTPClient::setReuse(bool reuse) {
+  _reuse = reuse;
 }
 
 /**
  * set User Agent
  * @param userAgent const char *
  */
-void HTTPClient::setUserAgent(const String& userAgent)
-{
-    _userAgent = userAgent;
+void HTTPClient::setUserAgent(const String &userAgent) {
+  _userAgent = userAgent;
+}
+
+/**
+ * set Accept Encoding Header
+ * @param acceptEncoding const char *
+ */
+void HTTPClient::setAcceptEncoding(const String &acceptEncoding) {
+  _acceptEncoding = acceptEncoding;
 }
 
 /**
@@ -421,65 +435,69 @@ void HTTPClient::setUserAgent(const String& userAgent)
  * @param user const char *
  * @param password const char *
  */
-void HTTPClient::setAuthorization(const char * user, const char * password)
-{
-    if(user && password) {
-        String auth = user;
-        auth += ":";
-        auth += password;
-        _base64Authorization = base64::encode(auth);
-    }
+void HTTPClient::setAuthorization(const char *user, const char *password) {
+  if (user && password) {
+    String auth = user;
+    auth += ":";
+    auth += password;
+    _base64Authorization = base64::encode(auth);
+  }
 }
 
 /**
  * set the Authorizatio for the http request
  * @param auth const char * base64
  */
-void HTTPClient::setAuthorization(const char * auth)
-{
-    if(auth) {
-        _base64Authorization = auth;
-    }
+void HTTPClient::setAuthorization(const char *auth) {
+  if (auth) {
+    _base64Authorization = auth;
+  }
+}
+
+/**
+ * set the Authorization type for the http request
+ * @param authType const char *
+ */
+void HTTPClient::setAuthorizationType(const char *authType) {
+  if (authType) {
+    _authorizationType = authType;
+  }
 }
 
 /**
  * set the timeout (ms) for establishing a connection to the server
  * @param connectTimeout int32_t
  */
-void HTTPClient::setConnectTimeout(int32_t connectTimeout)
-{
-    _connectTimeout = connectTimeout;
+void HTTPClient::setConnectTimeout(int32_t connectTimeout) {
+  _connectTimeout = connectTimeout;
 }
 
 /**
  * set the timeout for the TCP connection
  * @param timeout unsigned int
  */
-void HTTPClient::setTimeout(uint16_t timeout)
-{
-    _tcpTimeout = timeout;
-    if(connected()) {
-        _client->setTimeout((timeout + 500) / 1000);
-    }
+void HTTPClient::setTimeout(uint16_t timeout) {
+  _tcpTimeout = timeout;
+  if (connected()) {
+    _client->setTimeout(timeout);
+  }
 }
 
 /**
  * use HTTP1.0
  * @param use
  */
-void HTTPClient::useHTTP10(bool useHTTP10)
-{
-    _useHTTP10 = useHTTP10;
-    _reuse = !useHTTP10;
+void HTTPClient::useHTTP10(bool useHTTP10) {
+  _useHTTP10 = useHTTP10;
+  _reuse = !useHTTP10;
 }
 
 /**
  * send a GET request
  * @return http code
  */
-int HTTPClient::GET()
-{
-    return sendRequest("GET");
+int HTTPClient::GET() {
+  return sendRequest("GET");
 }
 
 /**
@@ -488,14 +506,12 @@ int HTTPClient::GET()
  * @param size size_t
  * @return http code
  */
-int HTTPClient::POST(uint8_t * payload, size_t size)
-{
-    return sendRequest("POST", payload, size);
+int HTTPClient::POST(uint8_t *payload, size_t size) {
+  return sendRequest("POST", payload, size);
 }
 
-int HTTPClient::POST(String payload)
-{
-    return POST((uint8_t *) payload.c_str(), payload.length());
+int HTTPClient::POST(String payload) {
+  return POST((uint8_t *)payload.c_str(), payload.length());
 }
 
 /**
@@ -504,14 +520,12 @@ int HTTPClient::POST(String payload)
  * @param size size_t
  * @return http code
  */
-int HTTPClient::PATCH(uint8_t * payload, size_t size)
-{
-    return sendRequest("PATCH", payload, size);
+int HTTPClient::PATCH(uint8_t *payload, size_t size) {
+  return sendRequest("PATCH", payload, size);
 }
 
-int HTTPClient::PATCH(String payload)
-{
-    return PATCH((uint8_t *) payload.c_str(), payload.length());
+int HTTPClient::PATCH(String payload) {
+  return PATCH((uint8_t *)payload.c_str(), payload.length());
 }
 
 /**
@@ -520,12 +534,12 @@ int HTTPClient::PATCH(String payload)
  * @param size size_t
  * @return http code
  */
-int HTTPClient::PUT(uint8_t * payload, size_t size) {
-    return sendRequest("PUT", payload, size);
+int HTTPClient::PUT(uint8_t *payload, size_t size) {
+  return sendRequest("PUT", payload, size);
 }
 
 int HTTPClient::PUT(String payload) {
-    return PUT((uint8_t *) payload.c_str(), payload.length());
+  return PUT((uint8_t *)payload.c_str(), payload.length());
 }
 
 /**
@@ -534,9 +548,8 @@ int HTTPClient::PUT(String payload) {
  * @param payload String        data for the message body
  * @return
  */
-int HTTPClient::sendRequest(const char * type, String payload)
-{
-    return sendRequest(type, (uint8_t *) payload.c_str(), payload.length());
+int HTTPClient::sendRequest(const char *type, String payload) {
+  return sendRequest(type, (uint8_t *)payload.c_str(), payload.length());
 }
 
 /**
@@ -546,108 +559,122 @@ int HTTPClient::sendRequest(const char * type, String payload)
  * @param size size_t           size for the message body if 0 not send
  * @return -1 if no info or > 0 when Content-Length is set by server
  */
-int HTTPClient::sendRequest(const char * type, uint8_t * payload, size_t size)
-{
-    int code;
-    bool redirect = false;
-    uint16_t redirectCount = 0;
-    do {
-        // wipe out any existing headers from previous request
-        for(size_t i = 0; i < _headerKeysCount; i++) {
-            if (_currentHeaders[i].value.length() > 0) {
-                _currentHeaders[i].value.clear();
-            }
-        }
+int HTTPClient::sendRequest(const char *type, uint8_t *payload, size_t size) {
+  int code;
+  bool redirect = false;
+  uint16_t redirectCount = 0;
+  do {
+    // wipe out any existing headers from previous request
+    for (size_t i = 0; i < _headerKeysCount; i++) {
+      if (_currentHeaders[i].value.length() > 0) {
+        _currentHeaders[i].value.clear();
+      }
+    }
 
-        log_d("request type: '%s' redirCount: %d\n", type, redirectCount);
-        
-        // connect to server
-        if(!connect()) {
-            return returnError(HTTPC_ERROR_CONNECTION_REFUSED);
-        }
+    log_d("request type: '%s' redirCount: %d\n", type, redirectCount);
 
-        if(payload && size > 0) {
-            addHeader(F("Content-Length"), String(size));
-        }
+    // connect to server
+    if (!connect()) {
+      return returnError(HTTPC_ERROR_CONNECTION_REFUSED);
+    }
 
-        // send Header
-        if(!sendHeader(type)) {
-            return returnError(HTTPC_ERROR_SEND_HEADER_FAILED);
-        }
+    if (payload && size > 0) {
+      addHeader(F("Content-Length"), String(size));
+    }
 
-        // send Payload if needed
-        if(payload && size > 0) {
-            if(_client->write(&payload[0], size) != size) {
-                return returnError(HTTPC_ERROR_SEND_PAYLOAD_FAILED);
-            }
-        }
+    // add cookies to header, if present
+    String cookie_string;
+    if (generateCookieString(&cookie_string)) {
+      addHeader("Cookie", cookie_string);
+    }
 
-        code = handleHeaderResponse();
-        log_d("sendRequest code=%d\n", code);
-
-        // Handle redirections as stated in RFC document:
-        // https://www.w3.org/Protocols/rfc2616/rfc2616-sec10.html
-        //
-        // Implementing HTTP_CODE_FOUND as redirection with GET method,
-        // to follow most of existing user agent implementations.
-        //
-        redirect = false;
-        if (
-            _followRedirects != HTTPC_DISABLE_FOLLOW_REDIRECTS && 
-            redirectCount < _redirectLimit &&
-            _location.length() > 0
-        ) {
-            switch (code) {
-                // redirecting using the same method
-                case HTTP_CODE_MOVED_PERMANENTLY:
-                case HTTP_CODE_TEMPORARY_REDIRECT: {
-                    if (
-                        // allow to force redirections on other methods
-                        // (the RFC require user to accept the redirection)
-                        _followRedirects == HTTPC_FORCE_FOLLOW_REDIRECTS ||
-                        // allow GET and HEAD methods without force
-                        !strcmp(type, "GET") || 
-                        !strcmp(type, "HEAD")
-                    ) {
-                        redirectCount += 1;
-                        log_d("following redirect (the same method): '%s' redirCount: %d\n", _location.c_str(), redirectCount);
-                        if (!setURL(_location)) {
-                            log_d("failed setting URL for redirection\n");
-                            // no redirection
-                            break;
-                        }
-                        // redirect using the same request method and payload, diffrent URL
-                        redirect = true;
-                    }
-                    break;
-                }
-                // redirecting with method dropped to GET or HEAD
-                // note: it does not need `HTTPC_FORCE_FOLLOW_REDIRECTS` for any method
-                case HTTP_CODE_FOUND:
-                case HTTP_CODE_SEE_OTHER: {
-                    redirectCount += 1;
-                    log_d("following redirect (dropped to GET/HEAD): '%s' redirCount: %d\n", _location.c_str(), redirectCount);
-                    if (!setURL(_location)) {
-                        log_d("failed setting URL for redirection\n");
-                        // no redirection
-                        break;
-                    }
-                    // redirect after changing method to GET/HEAD and dropping payload
-                    type = "GET";
-                    payload = nullptr;
-                    size = 0;
-                    redirect = true;
-                    break;
-                }
-
-                default:
-                    break;
+    // send Header
+    if (!sendHeader(type)) {
+      return returnError(HTTPC_ERROR_SEND_HEADER_FAILED);
+    }
+
+    // send Payload if needed
+    if (payload && size > 0) {
+      size_t sent_bytes = 0;
+      while (sent_bytes < size) {
+        size_t sent = _client->write(&payload[sent_bytes], size - sent_bytes);
+        if (sent == 0) {
+          log_w("Failed to send chunk! Lets wait a bit");
+          delay(100);
+          sent = _client->write(&payload[sent_bytes], size - sent_bytes);
+          if (sent == 0) {
+            log_e("Failed to send chunk!");
+            break;
+          }
+        }
+        sent_bytes += sent;
+      }
+      if (sent_bytes != size) {
+        return returnError(HTTPC_ERROR_SEND_PAYLOAD_FAILED);
+      }
+    }
+
+    code = handleHeaderResponse();
+    log_d("sendRequest code=%d\n", code);
+
+    // Handle redirections as stated in RFC document:
+    // https://www.w3.org/Protocols/rfc2616/rfc2616-sec10.html
+    //
+    // Implementing HTTP_CODE_FOUND as redirection with GET method,
+    // to follow most of existing user agent implementations.
+    //
+    redirect = false;
+    if (_followRedirects != HTTPC_DISABLE_FOLLOW_REDIRECTS && redirectCount < _redirectLimit && _location.length() > 0) {
+      switch (code) {
+        // redirecting using the same method
+        case HTTP_CODE_MOVED_PERMANENTLY:
+        case HTTP_CODE_TEMPORARY_REDIRECT:
+        {
+          if (
+              // allow to force redirections on other methods
+              // (the RFC require user to accept the redirection)
+              _followRedirects == HTTPC_FORCE_FOLLOW_REDIRECTS ||
+              // allow GET and HEAD methods without force
+              !strcmp(type, "GET") || !strcmp(type, "HEAD")) {
+            redirectCount += 1;
+            log_d("following redirect (the same method): '%s' redirCount: %d\n", _location.c_str(), redirectCount);
+            if (!setURL(_location)) {
+              log_d("failed setting URL for redirection\n");
+              // no redirection
+              break;
             }
+            // redirect using the same request method and payload, different URL
+            redirect = true;
+          }
+          break;
+        }
+        // redirecting with method dropped to GET or HEAD
+        // note: it does not need `HTTPC_FORCE_FOLLOW_REDIRECTS` for any method
+        case HTTP_CODE_FOUND:
+        case HTTP_CODE_SEE_OTHER:
+        {
+          redirectCount += 1;
+          log_d("following redirect (dropped to GET/HEAD): '%s' redirCount: %d\n", _location.c_str(), redirectCount);
+          if (!setURL(_location)) {
+            log_d("failed setting URL for redirection\n");
+            // no redirection
+            break;
+          }
+          // redirect after changing method to GET/HEAD and dropping payload
+          type = "GET";
+          payload = nullptr;
+          size = 0;
+          redirect = true;
+          break;
         }
 
-    } while (redirect);
-    // handle Server Response (Header)
-    return returnError(code);
+        default: break;
+      }
+    }
+
+  } while (redirect);
+  // handle Server Response (Header)
+  return returnError(code);
 }
 
 /**
@@ -657,174 +684,176 @@ int HTTPClient::sendRequest(const char * type, uint8_t * payload, size_t size)
  * @param size size_t           size for the message body if 0 not Content-Length is send
  * @return -1 if no info or > 0 when Content-Length is set by server
  */
-int HTTPClient::sendRequest(const char * type, Stream * stream, size_t size)
-{
+int HTTPClient::sendRequest(const char *type, Stream *stream, size_t size) {
 
-    if(!stream) {
-        return returnError(HTTPC_ERROR_NO_STREAM);
-    }
+  if (!stream) {
+    return returnError(HTTPC_ERROR_NO_STREAM);
+  }
 
-    // connect to server
-    if(!connect()) {
-        return returnError(HTTPC_ERROR_CONNECTION_REFUSED);
-    }
+  // connect to server
+  if (!connect()) {
+    return returnError(HTTPC_ERROR_CONNECTION_REFUSED);
+  }
 
-    if(size > 0) {
-        addHeader("Content-Length", String(size));
-    }
+  if (size > 0) {
+    addHeader("Content-Length", String(size));
+  }
 
-    // send Header
-    if(!sendHeader(type)) {
-        return returnError(HTTPC_ERROR_SEND_HEADER_FAILED);
-    }
+  // add cookies to header, if present
+  String cookie_string;
+  if (generateCookieString(&cookie_string)) {
+    addHeader("Cookie", cookie_string);
+  }
 
-    int buff_size = HTTP_TCP_BUFFER_SIZE;
+  // send Header
+  if (!sendHeader(type)) {
+    return returnError(HTTPC_ERROR_SEND_HEADER_FAILED);
+  }
 
-    int len = size;
-    int bytesWritten = 0;
+  int buff_size = HTTP_TCP_TX_BUFFER_SIZE;
 
-    if(len == 0) {
-        len = -1;
-    }
+  int len = size;
+  int bytesWritten = 0;
 
-    // if possible create smaller buffer then HTTP_TCP_BUFFER_SIZE
-    if((len > 0) && (len < HTTP_TCP_BUFFER_SIZE)) {
-        buff_size = len;
-    }
+  if (len == 0) {
+    len = -1;
+  }
 
-    // create buffer for read
-    uint8_t * buff = (uint8_t *) malloc(buff_size);
+  // if possible create smaller buffer then HTTP_TCP_TX_BUFFER_SIZE
+  if ((len > 0) && (len < buff_size)) {
+    buff_size = len;
+  }
 
-    if(buff) {
-        // read all data from stream and send it to server
-        while(connected() && (stream->available() > -1) && (len > 0 || len == -1)) {
+  // create buffer for read
+  uint8_t *buff = (uint8_t *)malloc(buff_size);
 
-            // get available data size
-            int sizeAvailable = stream->available();
+  if (buff) {
+    // read all data from stream and send it to server
+    while (connected() && (stream->available() > -1) && (len > 0 || len == -1)) {
 
-            if(sizeAvailable) {
+      // get available data size
+      int sizeAvailable = stream->available();
 
-                int readBytes = sizeAvailable;
+      if (sizeAvailable) {
 
-                // read only the asked bytes
-                if(len > 0 && readBytes > len) {
-                    readBytes = len;
-                }
+        int readBytes = sizeAvailable;
 
-                // not read more the buffer can handle
-                if(readBytes > buff_size) {
-                    readBytes = buff_size;
-                }
+        // read only the asked bytes
+        if (len > 0 && readBytes > len) {
+          readBytes = len;
+        }
 
-                // read data
-                int bytesRead = stream->readBytes(buff, readBytes);
+        // not read more the buffer can handle
+        if (readBytes > buff_size) {
+          readBytes = buff_size;
+        }
 
-                // write it to Stream
-                int bytesWrite = _client->write((const uint8_t *) buff, bytesRead);
-                bytesWritten += bytesWrite;
+        // read data
+        int bytesRead = stream->readBytes(buff, readBytes);
 
-                // are all Bytes a writen to stream ?
-                if(bytesWrite != bytesRead) {
-                    log_d("short write, asked for %d but got %d retry...", bytesRead, bytesWrite);
+        // write it to Stream
+        int bytesWrite = _client->write((const uint8_t *)buff, bytesRead);
+        bytesWritten += bytesWrite;
 
-                    // check for write error
-                    if(_client->getWriteError()) {
-                        log_d("stream write error %d", _client->getWriteError());
+        // are all Bytes a written to stream ?
+        if (bytesWrite != bytesRead) {
+          log_d("short write, asked for %d but got %d retry...", bytesRead, bytesWrite);
 
-                        //reset write error for retry
-                        _client->clearWriteError();
-                    }
+          // check for write error
+          if (_client->getWriteError()) {
+            log_d("stream write error %d", _client->getWriteError());
 
-                    // some time for the stream
-                    delay(1);
+            //reset write error for retry
+            _client->clearWriteError();
+          }
 
-                    int leftBytes = (readBytes - bytesWrite);
+          // some time for the stream
+          delay(1);
 
-                    // retry to send the missed bytes
-                    bytesWrite = _client->write((const uint8_t *) (buff + bytesWrite), leftBytes);
-                    bytesWritten += bytesWrite;
+          int leftBytes = (readBytes - bytesWrite);
 
-                    if(bytesWrite != leftBytes) {
-                        // failed again
-                        log_d("short write, asked for %d but got %d failed.", leftBytes, bytesWrite);
-                        free(buff);
-                        return returnError(HTTPC_ERROR_SEND_PAYLOAD_FAILED);
-                    }
-                }
+          // retry to send the missed bytes
+          bytesWrite = _client->write((const uint8_t *)(buff + bytesWrite), leftBytes);
+          bytesWritten += bytesWrite;
 
-                // check for write error
-                if(_client->getWriteError()) {
-                    log_d("stream write error %d", _client->getWriteError());
-                    free(buff);
-                    return returnError(HTTPC_ERROR_SEND_PAYLOAD_FAILED);
-                }
+          if (bytesWrite != leftBytes) {
+            // failed again
+            log_d("short write, asked for %d but got %d failed.", leftBytes, bytesWrite);
+            free(buff);
+            return returnError(HTTPC_ERROR_SEND_PAYLOAD_FAILED);
+          }
+        }
 
-                // count bytes to read left
-                if(len > 0) {
-                    len -= readBytes;
-                }
+        // check for write error
+        if (_client->getWriteError()) {
+          log_d("stream write error %d", _client->getWriteError());
+          free(buff);
+          return returnError(HTTPC_ERROR_SEND_PAYLOAD_FAILED);
+        }
 
-                delay(0);
-            } else {
-                delay(1);
-            }
+        // count bytes to read left
+        if (len > 0) {
+          len -= readBytes;
         }
 
-        free(buff);
+        delay(0);
+      } else {
+        delay(1);
+      }
+    }
 
-        if(size && (int) size != bytesWritten) {
-            log_d("Stream payload bytesWritten %d and size %d mismatch!.", bytesWritten, size);
-            log_d("ERROR SEND PAYLOAD FAILED!");
-            return returnError(HTTPC_ERROR_SEND_PAYLOAD_FAILED);
-        } else {
-            log_d("Stream payload written: %d", bytesWritten);
-        }
+    free(buff);
 
+    if (size && (int)size != bytesWritten) {
+      log_d("Stream payload bytesWritten %d and size %d mismatch!.", bytesWritten, size);
+      log_d("ERROR SEND PAYLOAD FAILED!");
+      return returnError(HTTPC_ERROR_SEND_PAYLOAD_FAILED);
     } else {
-        log_d("too less ram! need %d", HTTP_TCP_BUFFER_SIZE);
-        return returnError(HTTPC_ERROR_TOO_LESS_RAM);
+      log_d("Stream payload written: %d", bytesWritten);
     }
 
-    // handle Server Response (Header)
-    return returnError(handleHeaderResponse());
+  } else {
+    log_d("too less ram! need %d", buff_size);
+    return returnError(HTTPC_ERROR_TOO_LESS_RAM);
+  }
+
+  // handle Server Response (Header)
+  return returnError(handleHeaderResponse());
 }
 
 /**
  * size of message body / payload
  * @return -1 if no info or > 0 when Content-Length is set by server
  */
-int HTTPClient::getSize(void)
-{
-    return _size;
+int HTTPClient::getSize(void) {
+  return _size;
 }
 
 /**
  * returns the stream of the tcp connection
- * @return WiFiClient
+ * @return NetworkClient
  */
-WiFiClient& HTTPClient::getStream(void)
-{
-    if (connected()) {
-        return *_client;
-    }
-
-    log_w("getStream: not connected");
-    static WiFiClient empty;
-    return empty;
+NetworkClient &HTTPClient::getStream(void) {
+  if (connected()) {
+    return *_client;
+  }
+
+  log_w("getStream: not connected");
+  static NetworkClient empty;
+  return empty;
 }
 
 /**
  * returns a pointer to the stream of the tcp connection
- * @return WiFiClient*
+ * @return NetworkClient*
  */
-WiFiClient* HTTPClient::getStreamPtr(void)
-{
-    if(connected()) {
-        return _client;
-    }
+NetworkClient *HTTPClient::getStreamPtr(void) {
+  if (connected()) {
+    return _client;
+  }
 
-    log_w("getStreamPtr: not connected");
-    return nullptr;
+  log_w("getStreamPtr: not connected");
+  return nullptr;
 }
 
 /**
@@ -832,106 +861,104 @@ WiFiClient* HTTPClient::getStreamPtr(void)
  * @param stream Stream *
  * @return bytes written ( negative values are error codes )
  */
-int HTTPClient::writeToStream(Stream * stream)
-{
-
-    if(!stream) {
-        return returnError(HTTPC_ERROR_NO_STREAM);
-    }
-
-    if(!connected()) {
-        return returnError(HTTPC_ERROR_NOT_CONNECTED);
-    }
-
-    // get length of document (is -1 when Server sends no Content-Length header)
-    int len = _size;
-    int ret = 0;
-
-    if(_transferEncoding == HTTPC_TE_IDENTITY) {
-        ret = writeToStreamDataBlock(stream, len);
-
-        // have we an error?
-        if(ret < 0) {
-            return returnError(ret);
+int HTTPClient::writeToStream(Stream *stream) {
+
+  if (!stream) {
+    return returnError(HTTPC_ERROR_NO_STREAM);
+  }
+
+  if (!connected()) {
+    return returnError(HTTPC_ERROR_NOT_CONNECTED);
+  }
+
+  // get length of document (is -1 when Server sends no Content-Length header)
+  int len = _size;
+  int ret = 0;
+
+  if (_transferEncoding == HTTPC_TE_IDENTITY) {
+    ret = writeToStreamDataBlock(stream, len);
+
+    // have we an error?
+    if (ret < 0) {
+      return returnError(ret);
+    }
+  } else if (_transferEncoding == HTTPC_TE_CHUNKED) {
+    int size = 0;
+    while (1) {
+      if (!connected()) {
+        return returnError(HTTPC_ERROR_CONNECTION_LOST);
+      }
+      String chunkHeader = _client->readStringUntil('\n');
+
+      if (chunkHeader.length() <= 0) {
+        return returnError(HTTPC_ERROR_READ_TIMEOUT);
+      }
+
+      chunkHeader.trim();  // remove \r
+
+      // read size of chunk
+      len = (uint32_t)strtol((const char *)chunkHeader.c_str(), NULL, 16);
+      size += len;
+      log_v(" read chunk len: %d", len);
+
+      // data left?
+      if (len > 0) {
+        int r = writeToStreamDataBlock(stream, len);
+        if (r < 0) {
+          // error in writeToStreamDataBlock
+          return returnError(r);
         }
-    } else if(_transferEncoding == HTTPC_TE_CHUNKED) {
-        int size = 0;
-        while(1) {
-            if(!connected()) {
-                return returnError(HTTPC_ERROR_CONNECTION_LOST);
-            }
-            String chunkHeader = _client->readStringUntil('\n');
+        ret += r;
+      } else {
 
-            if(chunkHeader.length() <= 0) {
-                return returnError(HTTPC_ERROR_READ_TIMEOUT);
-            }
+        // if no length Header use global chunk size
+        if (_size <= 0) {
+          _size = size;
+        }
 
-            chunkHeader.trim(); // remove \r
-
-            // read size of chunk
-            len = (uint32_t) strtol((const char *) chunkHeader.c_str(), NULL, 16);
-            size += len;
-            log_d(" read chunk len: %d", len);
-
-            // data left?
-            if(len > 0) {
-                int r = writeToStreamDataBlock(stream, len);
-                if(r < 0) {
-                    // error in writeToStreamDataBlock
-                    return returnError(r);
-                }
-                ret += r;
-            } else {
-
-                // if no length Header use global chunk size
-                if(_size <= 0) {
-                    _size = size;
-                }
-
-                // check if we have write all data out
-                if(ret != _size) {
-                    return returnError(HTTPC_ERROR_STREAM_WRITE);
-                }
-                break;
-            }
+        // check if we have write all data out
+        if (ret != _size) {
+          return returnError(HTTPC_ERROR_STREAM_WRITE);
+        }
+        break;
+      }
 
-            // read trailing \r\n at the end of the chunk
-            char buf[2];
-            auto trailing_seq_len = _client->readBytes((uint8_t*)buf, 2);
-            if (trailing_seq_len != 2 || buf[0] != '\r' || buf[1] != '\n') {
-                return returnError(HTTPC_ERROR_READ_TIMEOUT);
-            }
+      // read trailing \r\n at the end of the chunk
+      char buf[2];
+      auto trailing_seq_len = _client->readBytes((uint8_t *)buf, 2);
+      if (trailing_seq_len != 2 || buf[0] != '\r' || buf[1] != '\n') {
+        return returnError(HTTPC_ERROR_READ_TIMEOUT);
+      }
 
-            delay(0);
-        }
-    } else {
-        return returnError(HTTPC_ERROR_ENCODING);
+      delay(0);
     }
+  } else {
+    return returnError(HTTPC_ERROR_ENCODING);
+  }
 
-//    end();
-    disconnect(true);
-    return ret;
+  //    end();
+  disconnect(true);
+  return ret;
 }
 
 /**
  * return all payload as String (may need lot of ram or trigger out of memory!)
  * @return String
  */
-String HTTPClient::getString(void)
-{
-    // _size can be -1 when Server sends no Content-Length header
-    if(_size > 0 || _size == -1) {
-        StreamString sstring;
-        // try to reserve needed memory (noop if _size == -1)
-        if(sstring.reserve((_size + 1))) {
-            writeToStream(&sstring);
-            return sstring;            
-        } else {
-            log_d("not enough memory to reserve a string! need: %d", (_size + 1));
-        }
+String HTTPClient::getString(void) {
+  // _size can be -1 when Server sends no Content-Length header
+  if (_size > 0 || _size == -1) {
+    StreamString sstring;
+    // try to reserve needed memory (noop if _size == -1)
+    if (sstring.reserve((_size + 1))) {
+      writeToStream(&sstring);
+      return sstring;
+    } else {
+      log_d("not enough memory to reserve a string! need: %d", (_size + 1));
     }
+  }
 
-    return "";
+  return "";
 }
 
 /**
@@ -939,34 +966,21 @@ String HTTPClient::getString(void)
  * @param error int
  * @return String
  */
-String HTTPClient::errorToString(int error)
-{
-    switch(error) {
-    case HTTPC_ERROR_CONNECTION_REFUSED:
-        return F("connection refused");
-    case HTTPC_ERROR_SEND_HEADER_FAILED:
-        return F("send header failed");
-    case HTTPC_ERROR_SEND_PAYLOAD_FAILED:
-        return F("send payload failed");
-    case HTTPC_ERROR_NOT_CONNECTED:
-        return F("not connected");
-    case HTTPC_ERROR_CONNECTION_LOST:
-        return F("connection lost");
-    case HTTPC_ERROR_NO_STREAM:
-        return F("no stream");
-    case HTTPC_ERROR_NO_HTTP_SERVER:
-        return F("no HTTP server");
-    case HTTPC_ERROR_TOO_LESS_RAM:
-        return F("too less ram");
-    case HTTPC_ERROR_ENCODING:
-        return F("Transfer-Encoding not supported");
-    case HTTPC_ERROR_STREAM_WRITE:
-        return F("Stream write error");
-    case HTTPC_ERROR_READ_TIMEOUT:
-        return F("read Timeout");
-    default:
-        return String();
-    }
+String HTTPClient::errorToString(int error) {
+  switch (error) {
+    case HTTPC_ERROR_CONNECTION_REFUSED:  return F("connection refused");
+    case HTTPC_ERROR_SEND_HEADER_FAILED:  return F("send header failed");
+    case HTTPC_ERROR_SEND_PAYLOAD_FAILED: return F("send payload failed");
+    case HTTPC_ERROR_NOT_CONNECTED:       return F("not connected");
+    case HTTPC_ERROR_CONNECTION_LOST:     return F("connection lost");
+    case HTTPC_ERROR_NO_STREAM:           return F("no stream");
+    case HTTPC_ERROR_NO_HTTP_SERVER:      return F("no HTTP server");
+    case HTTPC_ERROR_TOO_LESS_RAM:        return F("too less ram");
+    case HTTPC_ERROR_ENCODING:            return F("Transfer-Encoding not supported");
+    case HTTPC_ERROR_STREAM_WRITE:        return F("Stream write error");
+    case HTTPC_ERROR_READ_TIMEOUT:        return F("read Timeout");
+    default:                              return String();
+  }
 }
 
 /**
@@ -975,145 +989,134 @@ String HTTPClient::errorToString(int error)
  * @param value
  * @param first
  */
-void HTTPClient::addHeader(const String& name, const String& value, bool first, bool replace)
-{
-    // not allow set of Header handled by code
-    if(!name.equalsIgnoreCase(F("Connection")) &&
-       !name.equalsIgnoreCase(F("User-Agent")) &&
-       !name.equalsIgnoreCase(F("Host")) &&
-       !(name.equalsIgnoreCase(F("Authorization")) && _base64Authorization.length())){
-
-        String headerLine = name;
-        headerLine += ": ";
-
-        if (replace) {
-            int headerStart = _headers.indexOf(headerLine);
-            if (headerStart != -1 && (headerStart == 0 || _headers[headerStart - 1] == '\n')) {
-                int headerEnd = _headers.indexOf('\n', headerStart);
-                _headers = _headers.substring(0, headerStart) + _headers.substring(headerEnd + 1);
-            }
-        }
-
-        headerLine += value;
-        headerLine += "\r\n";
-        if(first) {
-            _headers = headerLine + _headers;
-        } else {
-            _headers += headerLine;
-        }
+void HTTPClient::addHeader(const String &name, const String &value, bool first, bool replace) {
+  // not allow set of Header handled by code
+  if (!name.equalsIgnoreCase(F("Connection")) && !name.equalsIgnoreCase(F("User-Agent")) && !name.equalsIgnoreCase(F("Accept-Encoding"))
+      && !name.equalsIgnoreCase(F("Host")) && !(name.equalsIgnoreCase(F("Authorization")) && _base64Authorization.length())) {
+
+    String headerLine = name;
+    headerLine += ": ";
+
+    if (replace) {
+      int headerStart = _headers.indexOf(headerLine);
+      if (headerStart != -1 && (headerStart == 0 || _headers[headerStart - 1] == '\n')) {
+        int headerEnd = _headers.indexOf('\n', headerStart);
+        _headers = _headers.substring(0, headerStart) + _headers.substring(headerEnd + 1);
+      }
+    }
+
+    headerLine += value;
+    headerLine += "\r\n";
+    if (first) {
+      _headers = headerLine + _headers;
+    } else {
+      _headers += headerLine;
     }
+  }
 }
 
-void HTTPClient::collectHeaders(const char* headerKeys[], const size_t headerKeysCount)
-{
-    _headerKeysCount = headerKeysCount;
-    if(_currentHeaders) {
-        delete[] _currentHeaders;
-    }
-    _currentHeaders = new RequestArgument[_headerKeysCount];
-    for(size_t i = 0; i < _headerKeysCount; i++) {
-        _currentHeaders[i].key = headerKeys[i];
-    }
+void HTTPClient::collectHeaders(const char *headerKeys[], const size_t headerKeysCount) {
+  _headerKeysCount = headerKeysCount;
+  if (_currentHeaders) {
+    delete[] _currentHeaders;
+  }
+  _currentHeaders = new RequestArgument[_headerKeysCount];
+  for (size_t i = 0; i < _headerKeysCount; i++) {
+    _currentHeaders[i].key = headerKeys[i];
+  }
 }
 
-String HTTPClient::header(const char* name)
-{
-    for(size_t i = 0; i < _headerKeysCount; ++i) {
-        if(_currentHeaders[i].key == name) {
-            return _currentHeaders[i].value;
-        }
+String HTTPClient::header(const char *name) {
+  for (size_t i = 0; i < _headerKeysCount; ++i) {
+    if (_currentHeaders[i].key.equalsIgnoreCase(name)) {
+      return _currentHeaders[i].value;
     }
-    return String();
+  }
+  return String();
 }
 
-String HTTPClient::header(size_t i)
-{
-    if(i < _headerKeysCount) {
-        return _currentHeaders[i].value;
-    }
-    return String();
+String HTTPClient::header(size_t i) {
+  if (i < _headerKeysCount) {
+    return _currentHeaders[i].value;
+  }
+  return String();
 }
 
-String HTTPClient::headerName(size_t i)
-{
-    if(i < _headerKeysCount) {
-        return _currentHeaders[i].key;
-    }
-    return String();
+String HTTPClient::headerName(size_t i) {
+  if (i < _headerKeysCount) {
+    return _currentHeaders[i].key;
+  }
+  return String();
 }
 
-int HTTPClient::headers()
-{
-    return _headerKeysCount;
+int HTTPClient::headers() {
+  return _headerKeysCount;
 }
 
-bool HTTPClient::hasHeader(const char* name)
-{
-    for(size_t i = 0; i < _headerKeysCount; ++i) {
-        if((_currentHeaders[i].key == name) && (_currentHeaders[i].value.length() > 0)) {
-            return true;
-        }
+bool HTTPClient::hasHeader(const char *name) {
+  for (size_t i = 0; i < _headerKeysCount; ++i) {
+    if ((_currentHeaders[i].key.equalsIgnoreCase(name)) && (_currentHeaders[i].value.length() > 0)) {
+      return true;
     }
-    return false;
+  }
+  return false;
 }
 
 /**
  * init TCP connection and handle ssl verify if needed
  * @return true if connection is ok
  */
-bool HTTPClient::connect(void)
-{
-    if(connected()) {
-        if(_reuse) {
-            log_d("already connected, reusing connection");
-        } else {
-            log_d("already connected, try reuse!");
-        }
-        while(_client->available() > 0) {
-            _client->read();
-        }
-        return true;
+bool HTTPClient::connect(void) {
+  if (connected()) {
+    if (_reuse) {
+      log_d("already connected, reusing connection");
+    } else {
+      log_d("already connected, try reuse!");
+    }
+    while (_client->available() > 0) {
+      _client->read();
     }
+    return true;
+  }
 
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-     if(_transportTraits && !_client) {
-        _tcpDeprecated = _transportTraits->create();
-        if(!_tcpDeprecated) {
-            log_e("failed to create client");
-            return false;
-        }
-        _client = _tcpDeprecated.get();
-     }
+  if (_transportTraits && !_client) {
+    _tcpDeprecated = _transportTraits->create();
+    if (!_tcpDeprecated) {
+      log_e("failed to create client");
+      return false;
+    }
+    _client = _tcpDeprecated.get();
+  }
 #endif
 
-    if (!_client) {
-        log_d("HTTPClient::begin was not called or returned error");
-        return false;
-    }
+  if (!_client) {
+    log_d("HTTPClient::begin was not called or returned error");
+    return false;
+  }
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-    if (_tcpDeprecated && !_transportTraits->verify(*_client, _host.c_str())) {
-        log_d("transport level verify failed");
-        _client->stop();
-        return false;
-    }	
+  if (_tcpDeprecated && !_transportTraits->verify(*_client, _host.c_str())) {
+    log_d("transport level verify failed");
+    _client->stop();
+    return false;
+  }
 #endif
-    if(!_client->connect(_host.c_str(), _port, _connectTimeout)) {
-        log_d("failed connect to %s:%u", _host.c_str(), _port);
-        return false;
-    }
-
-    // set Timeout for WiFiClient and for Stream::readBytesUntil() and Stream::readStringUntil()
-    _client->setTimeout((_tcpTimeout + 500) / 1000);	
+  if (!_client->connect(_host.c_str(), _port, _connectTimeout)) {
+    log_d("failed connect to %s:%u", _host.c_str(), _port);
+    return false;
+  }
 
-    log_d(" connected to %s:%u", _host.c_str(), _port);
+  // set Timeout for NetworkClient and for Stream::readBytesUntil() and Stream::readStringUntil()
+  _client->setTimeout(_tcpTimeout);
 
+  log_d(" connected to %s:%u", _host.c_str(), _port);
 
-/*
+  /*
 #ifdef ESP8266
     _client->setNoDelay(true);
 #endif
  */
- return connected();
+  return connected();
 }
 
 /**
@@ -1121,156 +1124,172 @@ bool HTTPClient::connect(void)
  * @param type (GET, POST, ...)
  * @return status
  */
-bool HTTPClient::sendHeader(const char * type)
-{
-    if(!connected()) {
-        return false;
-    }
-
-    String header = String(type) + " " + _uri + F(" HTTP/1.");
-
-    if(_useHTTP10) {
-        header += "0";
-    } else {
-        header += "1";
-    }
-
-    header += String(F("\r\nHost: ")) + _host;
-    if (_port != 80 && _port != 443)
-    {
-        header += ':';
-        header += String(_port);
-    }
-    header += String(F("\r\nUser-Agent: ")) + _userAgent +
-              F("\r\nConnection: ");
-
-    if(_reuse) {
-        header += F("keep-alive");
-    } else {
-        header += F("close");
-    }
+bool HTTPClient::sendHeader(const char *type) {
+  if (!connected()) {
+    return false;
+  }
+
+  String header = String(type) + " " + _uri + F(" HTTP/1.");
+
+  if (_useHTTP10) {
+    header += "0";
+  } else {
+    header += "1";
+  }
+
+  header += String(F("\r\nHost: ")) + _host;
+  if (_port != 80 && _port != 443) {
+    header += ':';
+    header += String(_port);
+  }
+  header += String(F("\r\nUser-Agent: ")) + _userAgent + F("\r\nConnection: ");
+
+  if (_reuse) {
+    header += F("keep-alive");
+  } else {
+    header += F("close");
+  }
+  header += "\r\n";
+
+  if (!_useHTTP10) {
+    header += String(F("Accept-Encoding: ")) + _acceptEncoding + F("\r\n");
+  }
+
+  if (_base64Authorization.length()) {
+    _base64Authorization.replace("\n", "");
+    header += F("Authorization: ");
+    header += _authorizationType;
+    header += " ";
+    header += _base64Authorization;
     header += "\r\n";
+  }
 
-    if(!_useHTTP10) {
-        header += F("Accept-Encoding: identity;q=1,chunked;q=0.1,*;q=0\r\n");
-    }
-
-    if(_base64Authorization.length()) {
-        _base64Authorization.replace("\n", "");
-        header += F("Authorization: Basic ");
-        header += _base64Authorization;
-        header += "\r\n";
-    }
-
-    header += _headers + "\r\n";
+  header += _headers + "\r\n";
 
-    return (_client->write((const uint8_t *) header.c_str(), header.length()) == header.length());
+  return (_client->write((const uint8_t *)header.c_str(), header.length()) == header.length());
 }
 
 /**
  * reads the response from the server
  * @return int http code
  */
-int HTTPClient::handleHeaderResponse()
-{
+int HTTPClient::handleHeaderResponse() {
 
-    if(!connected()) {
-        return HTTPC_ERROR_NOT_CONNECTED;
-    }
+  if (!connected()) {
+    return HTTPC_ERROR_NOT_CONNECTED;
+  }
 
-    clear();
+  _returnCode = 0;
+  _size = -1;
+  _canReuse = _reuse;
 
-    _canReuse = _reuse;
-
-    String transferEncoding;
-
-    _transferEncoding = HTTPC_TE_IDENTITY;
-    unsigned long lastDataTime = millis();
-    bool firstLine = true;
-
-    while(connected()) {
-        size_t len = _client->available();
-        if(len > 0) {
-            String headerLine = _client->readStringUntil('\n');
-            headerLine.trim(); // remove \r
-
-            lastDataTime = millis();
-
-            log_v("RX: '%s'", headerLine.c_str());
-
-            if(firstLine) {
-		firstLine = false;
-                if(_canReuse && headerLine.startsWith("HTTP/1.")) {
-                    _canReuse = (headerLine[sizeof "HTTP/1." - 1] != '0');
-                }
-                int codePos = headerLine.indexOf(' ') + 1;
-                _returnCode = headerLine.substring(codePos, headerLine.indexOf(' ', codePos)).toInt();
-            } else if(headerLine.indexOf(':')) {
-                String headerName = headerLine.substring(0, headerLine.indexOf(':'));
-                String headerValue = headerLine.substring(headerLine.indexOf(':') + 1);
-                headerValue.trim();
-
-                if(headerName.equalsIgnoreCase("Content-Length")) {
-                    _size = headerValue.toInt();
-                }
-
-                if(_canReuse && headerName.equalsIgnoreCase("Connection")) {
-                    if(headerValue.indexOf("close") >= 0 && headerValue.indexOf("keep-alive") < 0) {
-                        _canReuse = false;
-                    }
-                }
-
-                if(headerName.equalsIgnoreCase("Transfer-Encoding")) {
-                    transferEncoding = headerValue;
-                }
-
-                if (headerName.equalsIgnoreCase("Location")) {
-                    _location = headerValue;
-                }
-
-                for(size_t i = 0; i < _headerKeysCount; i++) {
-                    if(_currentHeaders[i].key.equalsIgnoreCase(headerName)) {
-                        _currentHeaders[i].value = headerValue;
-                        break;
-                    }
-                }
-            }
+  String transferEncoding;
 
-            if(headerLine == "") {
-                log_d("code: %d", _returnCode);
-
-                if(_size > 0) {
-                    log_d("size: %d", _size);
-                }
-
-                if(transferEncoding.length() > 0) {
-                    log_d("Transfer-Encoding: %s", transferEncoding.c_str());
-                    if(transferEncoding.equalsIgnoreCase("chunked")) {
-                        _transferEncoding = HTTPC_TE_CHUNKED;
-                    } else {
-                        return HTTPC_ERROR_ENCODING;
-                    }
-                } else {
-                    _transferEncoding = HTTPC_TE_IDENTITY;
-                }
-
-                if(_returnCode) {
-                    return _returnCode;
-                } else {
-                    log_d("Remote host is not an HTTP Server!");
-                    return HTTPC_ERROR_NO_HTTP_SERVER;
-                }
-            }
+  _transferEncoding = HTTPC_TE_IDENTITY;
+  unsigned long lastDataTime = millis();
+  bool firstLine = true;
+  String date;
+
+  while (connected()) {
+    size_t len = _client->available();
+    if (len > 0) {
+      String headerLine = _client->readStringUntil('\n');
+      headerLine.trim();  // remove \r
+
+      lastDataTime = millis();
+
+      log_v("RX: '%s'", headerLine.c_str());
+
+      if (firstLine) {
+        firstLine = false;
+        if (_canReuse && headerLine.startsWith("HTTP/1.")) {
+          _canReuse = (headerLine[sizeof "HTTP/1." - 1] != '0');
+        }
+        int codePos = headerLine.indexOf(' ') + 1;
+        _returnCode = headerLine.substring(codePos, headerLine.indexOf(' ', codePos)).toInt();
+      } else if (headerLine.indexOf(':')) {
+        String headerName = headerLine.substring(0, headerLine.indexOf(':'));
+        String headerValue = headerLine.substring(headerLine.indexOf(':') + 1);
+        headerValue.trim();
+
+        if (headerName.equalsIgnoreCase("Date")) {
+          date = headerValue;
+        }
+
+        if (headerName.equalsIgnoreCase("Content-Length")) {
+          _size = headerValue.toInt();
+        }
+
+        if (_canReuse && headerName.equalsIgnoreCase("Connection")) {
+          if (headerValue.indexOf("close") >= 0 && headerValue.indexOf("keep-alive") < 0) {
+            _canReuse = false;
+          }
+        }
 
+        if (headerName.equalsIgnoreCase("Transfer-Encoding")) {
+          transferEncoding = headerValue;
+        }
+
+        if (headerName.equalsIgnoreCase("Location")) {
+          _location = headerValue;
+        }
+
+        if (headerName.equalsIgnoreCase("Set-Cookie")) {
+          setCookie(date, headerValue);
+        }
+
+        for (size_t i = 0; i < _headerKeysCount; i++) {
+          if (_currentHeaders[i].key.equalsIgnoreCase(headerName)) {
+            // Uncomment the following lines if you need to add support for multiple headers with the same key:
+            // if (!_currentHeaders[i].value.isEmpty()) {
+            //     // Existing value, append this one with a comma
+            //     _currentHeaders[i].value += ',';
+            //     _currentHeaders[i].value += headerValue;
+            // } else {
+            _currentHeaders[i].value = headerValue;
+            // }
+            break;  // We found a match, stop looking
+          }
+        }
+      }
+
+      if (headerLine == "") {
+        log_d("code: %d", _returnCode);
+
+        if (_size > 0) {
+          log_d("size: %d", _size);
+        }
+
+        if (transferEncoding.length() > 0) {
+          log_d("Transfer-Encoding: %s", transferEncoding.c_str());
+          if (transferEncoding.equalsIgnoreCase("chunked")) {
+            _transferEncoding = HTTPC_TE_CHUNKED;
+          } else if (transferEncoding.equalsIgnoreCase("identity")) {
+            _transferEncoding = HTTPC_TE_IDENTITY;
+          } else {
+            return HTTPC_ERROR_ENCODING;
+          }
         } else {
-            if((millis() - lastDataTime) > _tcpTimeout) {
-                return HTTPC_ERROR_READ_TIMEOUT;
-            }
-            delay(10);
+          _transferEncoding = HTTPC_TE_IDENTITY;
+        }
+
+        if (_returnCode) {
+          return _returnCode;
+        } else {
+          log_d("Remote host is not an HTTP Server!");
+          return HTTPC_ERROR_NO_HTTP_SERVER;
         }
+      }
+
+    } else {
+      if ((millis() - lastDataTime) > _tcpTimeout) {
+        return HTTPC_ERROR_READ_TIMEOUT;
+      }
+      delay(10);
     }
+  }
 
-    return HTTPC_ERROR_CONNECTION_LOST;
+  return HTTPC_ERROR_CONNECTION_LOST;
 }
 
 /**
@@ -1279,114 +1298,117 @@ int HTTPClient::handleHeaderResponse()
  * @param size int
  * @return < 0 = error >= 0 = size written
  */
-int HTTPClient::writeToStreamDataBlock(Stream * stream, int size)
-{
-    int buff_size = HTTP_TCP_BUFFER_SIZE;
-    int len = size;
-    int bytesWritten = 0;
-
-    // if possible create smaller buffer then HTTP_TCP_BUFFER_SIZE
-    if((len > 0) && (len < HTTP_TCP_BUFFER_SIZE)) {
-        buff_size = len;
-    }
+int HTTPClient::writeToStreamDataBlock(Stream *stream, int size) {
+  int buff_size = HTTP_TCP_RX_BUFFER_SIZE;
+  int len = size;
+  int bytesWritten = 0;
 
-    // create buffer for read
-    uint8_t * buff = (uint8_t *) malloc(buff_size);
-
-    if(buff) {
-        // read all data from server
-        while(connected() && (len > 0 || len == -1)) {
-
-            // get available data size
-            size_t sizeAvailable = _client->available();
-
-            if(sizeAvailable) {
-
-                int readBytes = sizeAvailable;
-
-                // read only the asked bytes
-                if(len > 0 && readBytes > len) {
-                    readBytes = len;
-                }
-
-                // not read more the buffer can handle
-                if(readBytes > buff_size) {
-                    readBytes = buff_size;
-                }
-		    
-		// stop if no more reading    
-		if (readBytes == 0)
-			break;
-
-                // read data
-                int bytesRead = _client->readBytes(buff, readBytes);
-
-                // write it to Stream
-                int bytesWrite = stream->write(buff, bytesRead);
-                bytesWritten += bytesWrite;
-
-                // are all Bytes a writen to stream ?
-                if(bytesWrite != bytesRead) {
-                    log_d("short write asked for %d but got %d retry...", bytesRead, bytesWrite);
-
-                    // check for write error
-                    if(stream->getWriteError()) {
-                        log_d("stream write error %d", stream->getWriteError());
-
-                        //reset write error for retry
-                        stream->clearWriteError();
-                    }
-
-                    // some time for the stream
-                    delay(1);
-
-                    int leftBytes = (readBytes - bytesWrite);
-
-                    // retry to send the missed bytes
-                    bytesWrite = stream->write((buff + bytesWrite), leftBytes);
-                    bytesWritten += bytesWrite;
-
-                    if(bytesWrite != leftBytes) {
-                        // failed again
-                        log_w("short write asked for %d but got %d failed.", leftBytes, bytesWrite);
-                        free(buff);
-                        return HTTPC_ERROR_STREAM_WRITE;
-                    }
-                }
-
-                // check for write error
-                if(stream->getWriteError()) {
-                    log_w("stream write error %d", stream->getWriteError());
-                    free(buff);
-                    return HTTPC_ERROR_STREAM_WRITE;
-                }
-
-                // count bytes to read left
-                if(len > 0) {
-                    len -= readBytes;
-                }
-
-                delay(0);
-            } else {
-                delay(1);
-            }
+  // if possible create smaller buffer then HTTP_TCP_RX_BUFFER_SIZE
+  if ((len > 0) && (len < buff_size)) {
+    buff_size = len;
+  }
+
+  // create buffer for read
+  uint8_t *buff = (uint8_t *)malloc(buff_size);
+
+  if (buff) {
+    // read all data from server
+    while (connected() && (len > 0 || len == -1)) {
+
+      // get available data size
+      size_t sizeAvailable = buff_size;
+      if (len < 0) {
+        sizeAvailable = _client->available();
+      }
+
+      if (sizeAvailable) {
+
+        int readBytes = sizeAvailable;
+
+        // read only the asked bytes
+        if (len > 0 && readBytes > len) {
+          readBytes = len;
+        }
+
+        // not read more the buffer can handle
+        if (readBytes > buff_size) {
+          readBytes = buff_size;
+        }
+
+        // stop if no more reading
+        if (readBytes == 0) {
+          break;
         }
 
-        free(buff);
+        // read data
+        int bytesRead = _client->readBytes(buff, readBytes);
 
-        log_d("connection closed or file end (written: %d).", bytesWritten);
+        // write it to Stream
+        int bytesWrite = stream->write(buff, bytesRead);
+        bytesWritten += bytesWrite;
 
-        if((size > 0) && (size != bytesWritten)) {
-            log_d("bytesWritten %d and size %d mismatch!.", bytesWritten, size);
+        // are all Bytes a written to stream ?
+        if (bytesWrite != bytesRead) {
+          log_d("short write asked for %d but got %d retry...", bytesRead, bytesWrite);
+
+          // check for write error
+          if (stream->getWriteError()) {
+            log_d("stream write error %d", stream->getWriteError());
+
+            //reset write error for retry
+            stream->clearWriteError();
+          }
+
+          // some time for the stream
+          delay(1);
+
+          int leftBytes = (bytesRead - bytesWrite);
+
+          // retry to send the missed bytes
+          bytesWrite = stream->write((buff + bytesWrite), leftBytes);
+          bytesWritten += bytesWrite;
+
+          if (bytesWrite != leftBytes) {
+            // failed again
+            log_w("short write asked for %d but got %d failed.", leftBytes, bytesWrite);
+            free(buff);
             return HTTPC_ERROR_STREAM_WRITE;
+          }
         }
 
-    } else {
-        log_w("too less ram! need %d", HTTP_TCP_BUFFER_SIZE);
-        return HTTPC_ERROR_TOO_LESS_RAM;
+        // check for write error
+        if (stream->getWriteError()) {
+          log_w("stream write error %d", stream->getWriteError());
+          free(buff);
+          return HTTPC_ERROR_STREAM_WRITE;
+        }
+
+        // count bytes to read left
+        if (len > 0) {
+          len -= bytesRead;
+        }
+
+        delay(0);
+      } else {
+        delay(1);
+      }
+    }
+
+    free(buff);
+
+    log_v("connection closed or file end (written: %d).", bytesWritten);
+
+    if ((size > 0) && (size != bytesWritten)) {
+      log_d("bytesWritten %d and size %d mismatch!.", bytesWritten, size);
+      return HTTPC_ERROR_STREAM_WRITE;
     }
 
-    return bytesWritten;
+  } else {
+    log_w("too less ram! need %d", buff_size);
+    return HTTPC_ERROR_TOO_LESS_RAM;
+  }
+
+  return bytesWritten;
 }
 
 /**
@@ -1394,63 +1416,230 @@ int HTTPClient::writeToStreamDataBlock(Stream * stream, int size)
  * @param error
  * @return error
  */
-int HTTPClient::returnError(int error)
-{
-    if(error < 0) {
-        log_w("error(%d): %s", error, errorToString(error).c_str());
-        if(connected()) {
-            log_d("tcp stop");
-            _client->stop();
-        }
+int HTTPClient::returnError(int error) {
+  if (error < 0) {
+    log_w("error(%d): %s", error, errorToString(error).c_str());
+    if (connected()) {
+      log_d("tcp stop");
+      _client->stop();
     }
-    return error;
+  }
+  return error;
 }
 
-void HTTPClient::setFollowRedirects(followRedirects_t follow)
-{
-    _followRedirects = follow;
+void HTTPClient::setFollowRedirects(followRedirects_t follow) {
+  _followRedirects = follow;
 }
 
-void HTTPClient::setRedirectLimit(uint16_t limit)
-{
-    _redirectLimit = limit;
+void HTTPClient::setRedirectLimit(uint16_t limit) {
+  _redirectLimit = limit;
 }
 
 /**
  * set the URL to a new value. Handy for following redirects.
  * @param url
  */
-bool HTTPClient::setURL(const String& url)
-{
-    // if the new location is only a path then only update the URI
-    if (url && url[0] == '/') {
-        _uri = url;
-        clear();
-        return true;
+bool HTTPClient::setURL(const String &url) {
+  // if the new location is only a path then only update the URI
+  if (url && url[0] == '/') {
+    _uri = url;
+    clear();
+    return true;
+  }
+
+  if (!url.startsWith(_protocol + ':')) {
+    log_d("new URL not the same protocol, expected '%s', URL: '%s'\n", _protocol.c_str(), url.c_str());
+    return false;
+  }
+
+  // check if the port is specified
+  int indexPort = url.indexOf(':', 6);  // find the first ':' excluding the one from the protocol
+  int indexURI = url.indexOf('/', 7);   // find where the URI starts to make sure the ':' is not part of it
+  if (indexPort == -1 || indexPort > indexURI) {
+    // the port is not specified
+    _port = (_protocol == "https" ? 443 : 80);
+  }
+
+  // disconnect but preserve _client.
+  // Also have to keep the connection otherwise it will free some of the memory used by _client
+  // and will blow up later when trying to do _client->available() or similar
+  _canReuse = true;
+  disconnect(true);
+  return beginInternal(url, _protocol.c_str());
+}
+
+const String &HTTPClient::getLocation(void) {
+  return _location;
+}
+
+void HTTPClient::setCookieJar(CookieJar *cookieJar) {
+  _cookieJar = cookieJar;
+}
+
+void HTTPClient::resetCookieJar() {
+  _cookieJar = nullptr;
+}
+
+void HTTPClient::clearAllCookies() {
+  if (_cookieJar) {
+    _cookieJar->clear();
+  }
+}
+
+void HTTPClient::setCookie(String date, String headerValue) {
+  if (!_cookieJar) {
+    return;
+  }
+#define HTTP_TIME_PATTERN "%a, %d %b %Y %H:%M:%S"
+
+  Cookie cookie;
+  String value;
+  int pos1, pos2;
+
+  struct tm tm;
+  strptime(date.c_str(), HTTP_TIME_PATTERN, &tm);
+  cookie.date = mktime(&tm);
+
+  pos1 = headerValue.indexOf('=');
+  pos2 = headerValue.indexOf(';');
+
+  if (pos1 >= 0 && pos2 > pos1) {
+    cookie.name = headerValue.substring(0, pos1);
+    cookie.value = headerValue.substring(pos1 + 1, pos2);
+  } else {
+    return;  // invalid cookie header
+  }
+
+  // only Cookie Attributes are case insensitive from this point on
+  headerValue.toLowerCase();
+
+  // expires
+  if (headerValue.indexOf("expires=") >= 0) {
+    pos1 = headerValue.indexOf("expires=") + strlen("expires=");
+    pos2 = headerValue.indexOf(';', pos1);
+
+    if (pos2 > pos1) {
+      value = headerValue.substring(pos1, pos2);
+    } else {
+      value = headerValue.substring(pos1);
     }
 
-    if (!url.startsWith(_protocol + ':')) {
-        log_d("new URL not the same protocol, expected '%s', URL: '%s'\n", _protocol.c_str(), url.c_str());
-        return false;
+    strptime(value.c_str(), HTTP_TIME_PATTERN, &tm);
+    cookie.expires.date = mktime(&tm);
+    cookie.expires.valid = true;
+  }
+
+  // max-age
+  if (headerValue.indexOf("max-age=") >= 0) {
+    pos1 = headerValue.indexOf("max-age=") + strlen("max-age=");
+    pos2 = headerValue.indexOf(';', pos1);
+
+    if (pos2 > pos1) {
+      value = headerValue.substring(pos1, pos2);
+    } else {
+      value = headerValue.substring(pos1);
     }
 
-    // check if the port is specified
-    int indexPort = url.indexOf(':', 6); // find the first ':' excluding the one from the protocol
-    int indexURI = url.indexOf('/', 7); // find where the URI starts to make sure the ':' is not part of it
-    if (indexPort == -1 || indexPort > indexURI) {
-        // the port is not specified
-        _port = (_protocol == "https" ? 443 : 80);
+    cookie.max_age.duration = value.toInt();
+    cookie.max_age.valid = true;
+  }
+
+  // domain
+  if (headerValue.indexOf("domain=") >= 0) {
+    pos1 = headerValue.indexOf("domain=") + strlen("domain=");
+    pos2 = headerValue.indexOf(';', pos1);
+
+    if (pos2 > pos1) {
+      value = headerValue.substring(pos1, pos2);
+    } else {
+      value = headerValue.substring(pos1);
     }
 
-    // disconnect but preserve _client. 
-    // Also have to keep the connection otherwise it will free some of the memory used by _client 
-    // and will blow up later when trying to do _client->available() or similar
-    _canReuse = true;
-    disconnect(true);
-    return beginInternal(url, _protocol.c_str());
+    if (value.startsWith(".")) {
+      value.remove(0, 1);
+    }
+
+    if (_host.indexOf(value) >= 0) {
+      cookie.domain = value;
+    } else {
+      return;  // server tries to set a cookie on a different domain; ignore it
+    }
+  } else {
+    pos1 = _host.lastIndexOf('.', _host.lastIndexOf('.') - 1);
+    if (pos1 >= 0) {
+      cookie.domain = _host.substring(pos1 + 1);
+    } else {
+      cookie.domain = _host;
+    }
+  }
+
+  // path
+  if (headerValue.indexOf("path=") >= 0) {
+    pos1 = headerValue.indexOf("path=") + strlen("path=");
+    pos2 = headerValue.indexOf(';', pos1);
+
+    if (pos2 > pos1) {
+      cookie.path = headerValue.substring(pos1, pos2);
+    } else {
+      cookie.path = headerValue.substring(pos1);
+    }
+  }
+
+  // HttpOnly
+  cookie.http_only = (headerValue.indexOf("httponly") >= 0);
+
+  // secure
+  cookie.secure = (headerValue.indexOf("secure") >= 0);
+
+  // overwrite or delete cookie in/from cookie jar
+  time_t now_local = time(NULL);
+  time_t now_gmt = mktime(gmtime(&now_local));
+
+  bool found = false;
+
+  for (auto c = _cookieJar->begin(); c != _cookieJar->end(); ++c) {
+    if (c->domain == cookie.domain && c->name == cookie.name) {
+      // when evaluating, max-age takes precedence over expires if both are defined
+      if ((cookie.max_age.valid && ((cookie.date + cookie.max_age.duration) < now_gmt)) || cookie.max_age.duration <= 0
+          || (!cookie.max_age.valid && cookie.expires.valid && cookie.expires.date < now_gmt)) {
+        _cookieJar->erase(c);
+        c--;
+      } else {
+        *c = cookie;
+      }
+      found = true;
+    }
+  }
+
+  // add cookie to jar
+  if (!found && !(cookie.max_age.valid && cookie.max_age.duration <= 0)) {
+    _cookieJar->push_back(cookie);
+  }
 }
 
-const String &HTTPClient::getLocation(void)
-{
-    return _location;
+bool HTTPClient::generateCookieString(String *cookieString) {
+  time_t now_local = time(NULL);
+  time_t now_gmt = mktime(gmtime(&now_local));
+
+  *cookieString = "";
+  bool found = false;
+
+  if (!_cookieJar) {
+    return false;
+  }
+  for (auto c = _cookieJar->begin(); c != _cookieJar->end(); ++c) {
+    if ((c->max_age.valid && ((c->date + c->max_age.duration) < now_gmt)) || (!c->max_age.valid && c->expires.valid && c->expires.date < now_gmt)) {
+      _cookieJar->erase(c);
+      c--;
+    } else if (_host.indexOf(c->domain) >= 0 && (!c->secure || _secure)) {
+      if (*cookieString == "") {
+        *cookieString = c->name + "=" + c->value;
+      } else {
+        *cookieString += " ;" + c->name + "=" + c->value;
+      }
+      found = true;
+    }
+  }
+
+  return found;
 }
diff --git a/libraries/HTTPClient/src/HTTPClient.h b/libraries/HTTPClient/src/HTTPClient.h
index 1b454e332a9..80f6da28599 100644
--- a/libraries/HTTPClient/src/HTTPClient.h
+++ b/libraries/HTTPClient/src/HTTPClient.h
@@ -5,8 +5,8 @@
  *
  * Copyright (c) 2015 Markus Sattler. All rights reserved.
  * This file is part of the HTTPClient for Arduino.
- * Port to ESP32 by Evandro Luis Copercini (2017), 
- * changed fingerprints to CA verification. 	
+ * Port to ESP32 by Evandro Luis Copercini (2017),
+ * changed fingerprints to CA verification.
  *
  * This library is free software; you can redistribute it and/or
  * modify it under the terms of the GNU Lesser General Public
@@ -27,12 +27,19 @@
 #ifndef HTTPClient_H_
 #define HTTPClient_H_
 
+#ifndef HTTPCLIENT_1_1_COMPATIBLE
 #define HTTPCLIENT_1_1_COMPATIBLE
+#endif
 
 #include <memory>
 #include <Arduino.h>
-#include <WiFiClient.h>
-#include <WiFiClientSecure.h>
+#include <NetworkClient.h>
+#ifndef HTTPCLIENT_NOSECURE
+#include <NetworkClientSecure.h>
+#endif  // HTTPCLIENT_NOSECURE
+
+/// Cookie jar support
+#include <vector>
 
 #define HTTPCLIENT_DEFAULT_TCP_TIMEOUT (5000)
 
@@ -50,73 +57,74 @@
 #define HTTPC_ERROR_READ_TIMEOUT        (-11)
 
 /// size for the stream handling
-#define HTTP_TCP_BUFFER_SIZE (1460)
+#define HTTP_TCP_RX_BUFFER_SIZE (4096)
+#define HTTP_TCP_TX_BUFFER_SIZE (1460)
 
 /// HTTP codes see RFC7231
 typedef enum {
-    HTTP_CODE_CONTINUE = 100,
-    HTTP_CODE_SWITCHING_PROTOCOLS = 101,
-    HTTP_CODE_PROCESSING = 102,
-    HTTP_CODE_OK = 200,
-    HTTP_CODE_CREATED = 201,
-    HTTP_CODE_ACCEPTED = 202,
-    HTTP_CODE_NON_AUTHORITATIVE_INFORMATION = 203,
-    HTTP_CODE_NO_CONTENT = 204,
-    HTTP_CODE_RESET_CONTENT = 205,
-    HTTP_CODE_PARTIAL_CONTENT = 206,
-    HTTP_CODE_MULTI_STATUS = 207,
-    HTTP_CODE_ALREADY_REPORTED = 208,
-    HTTP_CODE_IM_USED = 226,
-    HTTP_CODE_MULTIPLE_CHOICES = 300,
-    HTTP_CODE_MOVED_PERMANENTLY = 301,
-    HTTP_CODE_FOUND = 302,
-    HTTP_CODE_SEE_OTHER = 303,
-    HTTP_CODE_NOT_MODIFIED = 304,
-    HTTP_CODE_USE_PROXY = 305,
-    HTTP_CODE_TEMPORARY_REDIRECT = 307,
-    HTTP_CODE_PERMANENT_REDIRECT = 308,
-    HTTP_CODE_BAD_REQUEST = 400,
-    HTTP_CODE_UNAUTHORIZED = 401,
-    HTTP_CODE_PAYMENT_REQUIRED = 402,
-    HTTP_CODE_FORBIDDEN = 403,
-    HTTP_CODE_NOT_FOUND = 404,
-    HTTP_CODE_METHOD_NOT_ALLOWED = 405,
-    HTTP_CODE_NOT_ACCEPTABLE = 406,
-    HTTP_CODE_PROXY_AUTHENTICATION_REQUIRED = 407,
-    HTTP_CODE_REQUEST_TIMEOUT = 408,
-    HTTP_CODE_CONFLICT = 409,
-    HTTP_CODE_GONE = 410,
-    HTTP_CODE_LENGTH_REQUIRED = 411,
-    HTTP_CODE_PRECONDITION_FAILED = 412,
-    HTTP_CODE_PAYLOAD_TOO_LARGE = 413,
-    HTTP_CODE_URI_TOO_LONG = 414,
-    HTTP_CODE_UNSUPPORTED_MEDIA_TYPE = 415,
-    HTTP_CODE_RANGE_NOT_SATISFIABLE = 416,
-    HTTP_CODE_EXPECTATION_FAILED = 417,
-    HTTP_CODE_MISDIRECTED_REQUEST = 421,
-    HTTP_CODE_UNPROCESSABLE_ENTITY = 422,
-    HTTP_CODE_LOCKED = 423,
-    HTTP_CODE_FAILED_DEPENDENCY = 424,
-    HTTP_CODE_UPGRADE_REQUIRED = 426,
-    HTTP_CODE_PRECONDITION_REQUIRED = 428,
-    HTTP_CODE_TOO_MANY_REQUESTS = 429,
-    HTTP_CODE_REQUEST_HEADER_FIELDS_TOO_LARGE = 431,
-    HTTP_CODE_INTERNAL_SERVER_ERROR = 500,
-    HTTP_CODE_NOT_IMPLEMENTED = 501,
-    HTTP_CODE_BAD_GATEWAY = 502,
-    HTTP_CODE_SERVICE_UNAVAILABLE = 503,
-    HTTP_CODE_GATEWAY_TIMEOUT = 504,
-    HTTP_CODE_HTTP_VERSION_NOT_SUPPORTED = 505,
-    HTTP_CODE_VARIANT_ALSO_NEGOTIATES = 506,
-    HTTP_CODE_INSUFFICIENT_STORAGE = 507,
-    HTTP_CODE_LOOP_DETECTED = 508,
-    HTTP_CODE_NOT_EXTENDED = 510,
-    HTTP_CODE_NETWORK_AUTHENTICATION_REQUIRED = 511
+  HTTP_CODE_CONTINUE = 100,
+  HTTP_CODE_SWITCHING_PROTOCOLS = 101,
+  HTTP_CODE_PROCESSING = 102,
+  HTTP_CODE_OK = 200,
+  HTTP_CODE_CREATED = 201,
+  HTTP_CODE_ACCEPTED = 202,
+  HTTP_CODE_NON_AUTHORITATIVE_INFORMATION = 203,
+  HTTP_CODE_NO_CONTENT = 204,
+  HTTP_CODE_RESET_CONTENT = 205,
+  HTTP_CODE_PARTIAL_CONTENT = 206,
+  HTTP_CODE_MULTI_STATUS = 207,
+  HTTP_CODE_ALREADY_REPORTED = 208,
+  HTTP_CODE_IM_USED = 226,
+  HTTP_CODE_MULTIPLE_CHOICES = 300,
+  HTTP_CODE_MOVED_PERMANENTLY = 301,
+  HTTP_CODE_FOUND = 302,
+  HTTP_CODE_SEE_OTHER = 303,
+  HTTP_CODE_NOT_MODIFIED = 304,
+  HTTP_CODE_USE_PROXY = 305,
+  HTTP_CODE_TEMPORARY_REDIRECT = 307,
+  HTTP_CODE_PERMANENT_REDIRECT = 308,
+  HTTP_CODE_BAD_REQUEST = 400,
+  HTTP_CODE_UNAUTHORIZED = 401,
+  HTTP_CODE_PAYMENT_REQUIRED = 402,
+  HTTP_CODE_FORBIDDEN = 403,
+  HTTP_CODE_NOT_FOUND = 404,
+  HTTP_CODE_METHOD_NOT_ALLOWED = 405,
+  HTTP_CODE_NOT_ACCEPTABLE = 406,
+  HTTP_CODE_PROXY_AUTHENTICATION_REQUIRED = 407,
+  HTTP_CODE_REQUEST_TIMEOUT = 408,
+  HTTP_CODE_CONFLICT = 409,
+  HTTP_CODE_GONE = 410,
+  HTTP_CODE_LENGTH_REQUIRED = 411,
+  HTTP_CODE_PRECONDITION_FAILED = 412,
+  HTTP_CODE_PAYLOAD_TOO_LARGE = 413,
+  HTTP_CODE_URI_TOO_LONG = 414,
+  HTTP_CODE_UNSUPPORTED_MEDIA_TYPE = 415,
+  HTTP_CODE_RANGE_NOT_SATISFIABLE = 416,
+  HTTP_CODE_EXPECTATION_FAILED = 417,
+  HTTP_CODE_MISDIRECTED_REQUEST = 421,
+  HTTP_CODE_UNPROCESSABLE_ENTITY = 422,
+  HTTP_CODE_LOCKED = 423,
+  HTTP_CODE_FAILED_DEPENDENCY = 424,
+  HTTP_CODE_UPGRADE_REQUIRED = 426,
+  HTTP_CODE_PRECONDITION_REQUIRED = 428,
+  HTTP_CODE_TOO_MANY_REQUESTS = 429,
+  HTTP_CODE_REQUEST_HEADER_FIELDS_TOO_LARGE = 431,
+  HTTP_CODE_INTERNAL_SERVER_ERROR = 500,
+  HTTP_CODE_NOT_IMPLEMENTED = 501,
+  HTTP_CODE_BAD_GATEWAY = 502,
+  HTTP_CODE_SERVICE_UNAVAILABLE = 503,
+  HTTP_CODE_GATEWAY_TIMEOUT = 504,
+  HTTP_CODE_HTTP_VERSION_NOT_SUPPORTED = 505,
+  HTTP_CODE_VARIANT_ALSO_NEGOTIATES = 506,
+  HTTP_CODE_INSUFFICIENT_STORAGE = 507,
+  HTTP_CODE_LOOP_DETECTED = 508,
+  HTTP_CODE_NOT_EXTENDED = 510,
+  HTTP_CODE_NETWORK_AUTHENTICATION_REQUIRED = 511
 } t_http_codes;
 
 typedef enum {
-    HTTPC_TE_IDENTITY,
-    HTTPC_TE_CHUNKED
+  HTTPC_TE_IDENTITY,
+  HTTPC_TE_CHUNKED
 } transferEncoding_t;
 
 /**
@@ -131,140 +139,184 @@ typedef enum {
  *      In the sense of the RFC, it's just like every redirection is confirmed.
  */
 typedef enum {
-    HTTPC_DISABLE_FOLLOW_REDIRECTS,
-    HTTPC_STRICT_FOLLOW_REDIRECTS,
-    HTTPC_FORCE_FOLLOW_REDIRECTS
+  HTTPC_DISABLE_FOLLOW_REDIRECTS,
+  HTTPC_STRICT_FOLLOW_REDIRECTS,
+  HTTPC_FORCE_FOLLOW_REDIRECTS
 } followRedirects_t;
 
-
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
 class TransportTraits;
 typedef std::unique_ptr<TransportTraits> TransportTraitsPtr;
 #endif
 
-class HTTPClient
-{
+// cookie jar support
+typedef struct {
+  String host;  // host which tries to set the cookie
+  time_t date;  // timestamp of the response that set the cookie
+  String name;
+  String value;
+  String domain;
+  String path = "";
+  struct {
+    time_t date = 0;
+    bool valid = false;
+  } expires;
+  struct {
+    time_t duration = 0;
+    bool valid = false;
+  } max_age;
+  bool http_only = false;
+  bool secure = false;
+} Cookie;
+typedef std::vector<Cookie> CookieJar;
+
+class HTTPClient {
 public:
-    HTTPClient();
-    ~HTTPClient();
+  HTTPClient();
+  ~HTTPClient();
 
-/*
- * Since both begin() functions take a reference to client as a parameter, you need to 
+  /*
+ * Since both begin() functions take a reference to client as a parameter, you need to
  * ensure the client object lives the entire time of the HTTPClient
  */
-    bool begin(WiFiClient &client, String url);
-    bool begin(WiFiClient &client, String host, uint16_t port, String uri = "/", bool https = false);
+  bool begin(NetworkClient &client, String url);
+  bool begin(NetworkClient &client, String host, uint16_t port, String uri = "/", bool https = false);
 
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-    bool begin(String url);
-    bool begin(String url, const char* CAcert);
-    bool begin(String host, uint16_t port, String uri = "/");
-    bool begin(String host, uint16_t port, String uri, const char* CAcert);
-    bool begin(String host, uint16_t port, String uri, const char* CAcert, const char* cli_cert, const char* cli_key);
-#endif
-
-    void end(void);
-
-    bool connected(void);
-
-    void setReuse(bool reuse); /// keep-alive
-    void setUserAgent(const String& userAgent);
-    void setAuthorization(const char * user, const char * password);
-    void setAuthorization(const char * auth);
-    void setConnectTimeout(int32_t connectTimeout);
-    void setTimeout(uint16_t timeout);
-
-    // Redirections
-    void setFollowRedirects(followRedirects_t follow);
-    void setRedirectLimit(uint16_t limit); // max redirects to follow for a single request
-
-    bool setURL(const String &url);
-    void useHTTP10(bool usehttp10 = true);
-
-    /// request handling
-    int GET();
-    int PATCH(uint8_t * payload, size_t size);
-    int PATCH(String payload);
-    int POST(uint8_t * payload, size_t size);
-    int POST(String payload);
-    int PUT(uint8_t * payload, size_t size);
-    int PUT(String payload);
-    int sendRequest(const char * type, String payload);
-    int sendRequest(const char * type, uint8_t * payload = NULL, size_t size = 0);
-    int sendRequest(const char * type, Stream * stream, size_t size = 0);
+  bool begin(String url);
+  bool begin(String host, uint16_t port, String uri = "/");
+#ifndef HTTPCLIENT_NOSECURE
+  bool begin(String url, const char *CAcert);
+  bool begin(String host, uint16_t port, String uri, const char *CAcert);
+  bool begin(String host, uint16_t port, String uri, const char *CAcert, const char *cli_cert, const char *cli_key);
+#else
+  bool begin(String url, const char *CAcert) {
+    return false;
+  };
+  bool begin(String host, uint16_t port, String uri, const char *CAcert) {
+    return false;
+  };
+  bool begin(String host, uint16_t port, String uri, const char *CAcert, const char *cli_cert, const char *cli_key) {
+    return false;
+  };
+#endif  // HTTPCLIENT_NOSECURE
 
-    void addHeader(const String& name, const String& value, bool first = false, bool replace = true);
-
-    /// Response handling
-    void collectHeaders(const char* headerKeys[], const size_t headerKeysCount);
-    String header(const char* name);   // get request header value by name
-    String header(size_t i);              // get request header value by number
-    String headerName(size_t i);          // get request header name by number
-    int headers();                     // get header count
-    bool hasHeader(const char* name);  // check if header exists
-
-
-    int getSize(void);
-    const String &getLocation(void);
-
-    WiFiClient& getStream(void);
-    WiFiClient* getStreamPtr(void);
-    int writeToStream(Stream* stream);
-    String getString(void);
+#endif
 
-    static String errorToString(int error);
+  void end(void);
+
+  bool connected(void);
+
+  void setReuse(bool reuse);  /// keep-alive
+  void setUserAgent(const String &userAgent);
+  void setAcceptEncoding(const String &acceptEncoding);
+  void setAuthorization(const char *user, const char *password);
+  void setAuthorization(const char *auth);
+  void setAuthorizationType(const char *authType);
+  void setConnectTimeout(int32_t connectTimeout);
+  void setTimeout(uint16_t timeout);
+
+  // Redirections
+  void setFollowRedirects(followRedirects_t follow);
+  void setRedirectLimit(uint16_t limit);  // max redirects to follow for a single request
+
+  bool setURL(const String &url);
+  void useHTTP10(bool usehttp10 = true);
+
+  /// request handling
+  int GET();
+  int PATCH(uint8_t *payload, size_t size);
+  int PATCH(String payload);
+  int POST(uint8_t *payload, size_t size);
+  int POST(String payload);
+  int PUT(uint8_t *payload, size_t size);
+  int PUT(String payload);
+  int sendRequest(const char *type, String payload);
+  int sendRequest(const char *type, uint8_t *payload = NULL, size_t size = 0);
+  int sendRequest(const char *type, Stream *stream, size_t size = 0);
+
+  void addHeader(const String &name, const String &value, bool first = false, bool replace = true);
+
+  /// Response handling
+  void collectHeaders(const char *headerKeys[], const size_t headerKeysCount);
+  String header(const char *name);   // get request header value by name
+  String header(size_t i);           // get request header value by number
+  String headerName(size_t i);       // get request header name by number
+  int headers();                     // get header count
+  bool hasHeader(const char *name);  // check if header exists
+
+  int getSize(void);
+  const String &getLocation(void);
+
+  NetworkClient &getStream(void);
+  NetworkClient *getStreamPtr(void);
+  int writeToStream(Stream *stream);
+  String getString(void);
+
+  static String errorToString(int error);
+
+  /// Cookie jar support
+  void setCookieJar(CookieJar *cookieJar);
+  void resetCookieJar();
+  void clearAllCookies();
 
 protected:
-    struct RequestArgument {
-        String key;
-        String value;
-    };
-
-    bool beginInternal(String url, const char* expectedProtocol);
-    void disconnect(bool preserveClient = false);
-    void clear();
-    int returnError(int error);
-    bool connect(void);
-    bool sendHeader(const char * type);
-    int handleHeaderResponse();
-    int writeToStreamDataBlock(Stream * stream, int len);
-
+  struct RequestArgument {
+    String key;
+    String value;
+  };
+
+  bool beginInternal(String url, const char *expectedProtocol);
+  void disconnect(bool preserveClient = false);
+  void clear();
+  int returnError(int error);
+  bool connect(void);
+  bool sendHeader(const char *type);
+  int handleHeaderResponse();
+  int writeToStreamDataBlock(Stream *stream, int len);
+
+  /// Cookie jar support
+  void setCookie(String date, String headerValue);
+  bool generateCookieString(String *cookieString);
 
 #ifdef HTTPCLIENT_1_1_COMPATIBLE
-    TransportTraitsPtr _transportTraits;
-    std::unique_ptr<WiFiClient> _tcpDeprecated;
+  TransportTraitsPtr _transportTraits;
+  std::unique_ptr<NetworkClient> _tcpDeprecated;
 #endif
 
-    WiFiClient* _client = nullptr;
-
-    /// request handling
-    String _host;
-    uint16_t _port = 0;
-    int32_t _connectTimeout = -1;
-    bool _reuse = true;
-    uint16_t _tcpTimeout = HTTPCLIENT_DEFAULT_TCP_TIMEOUT;
-    bool _useHTTP10 = false;
-    bool _secure = false;
-
-    String _uri;
-    String _protocol;
-    String _headers;
-    String _userAgent = "ESP32HTTPClient";
-    String _base64Authorization;
-
-    /// Response handling
-    RequestArgument* _currentHeaders = nullptr;
-    size_t           _headerKeysCount = 0;
-
-    int _returnCode = 0;
-    int _size = -1;
-    bool _canReuse = false;
-    followRedirects_t _followRedirects = HTTPC_DISABLE_FOLLOW_REDIRECTS;
-    uint16_t _redirectLimit = 10;
-    String _location;
-    transferEncoding_t _transferEncoding = HTTPC_TE_IDENTITY;
+  NetworkClient *_client = nullptr;
+
+  /// request handling
+  String _host;
+  uint16_t _port = 0;
+  int32_t _connectTimeout = HTTPCLIENT_DEFAULT_TCP_TIMEOUT;
+  bool _reuse = true;
+  uint16_t _tcpTimeout = HTTPCLIENT_DEFAULT_TCP_TIMEOUT;
+  bool _useHTTP10 = false;
+  bool _secure = false;
+
+  String _uri;
+  String _protocol;
+  String _headers;
+  String _userAgent = "ESP32HTTPClient";
+  String _base64Authorization;
+  String _authorizationType = "Basic";
+  String _acceptEncoding = "identity;q=1,chunked;q=0.1,*;q=0";
+
+  /// Response handling
+  RequestArgument *_currentHeaders = nullptr;
+  size_t _headerKeysCount = 0;
+
+  int _returnCode = 0;
+  int _size = -1;
+  bool _canReuse = false;
+  followRedirects_t _followRedirects = HTTPC_DISABLE_FOLLOW_REDIRECTS;
+  uint16_t _redirectLimit = 10;
+  String _location;
+  transferEncoding_t _transferEncoding = HTTPC_TE_IDENTITY;
+
+  /// Cookie jar support
+  CookieJar *_cookieJar = nullptr;
 };
 
-
-
 #endif /* HTTPClient_H_ */
diff --git a/libraries/HTTPUpdate/examples/httpUpdate/ci.json b/libraries/HTTPUpdate/examples/httpUpdate/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/HTTPUpdate/examples/httpUpdate/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/HTTPUpdate/examples/httpUpdate/httpUpdate.ino b/libraries/HTTPUpdate/examples/httpUpdate/httpUpdate.ino
index e98a5851366..0cead8c86d4 100644
--- a/libraries/HTTPUpdate/examples/httpUpdate/httpUpdate.ino
+++ b/libraries/HTTPUpdate/examples/httpUpdate/httpUpdate.ino
@@ -32,15 +32,29 @@ void setup() {
 
   WiFi.mode(WIFI_STA);
   WiFiMulti.addAP("SSID", "PASSWORD");
+}
+
+void update_started() {
+  Serial.println("CALLBACK:  HTTP update process started");
+}
+
+void update_finished() {
+  Serial.println("CALLBACK:  HTTP update process finished");
+}
 
+void update_progress(int cur, int total) {
+  Serial.printf("CALLBACK:  HTTP update process at %d of %d bytes...\n", cur, total);
+}
 
+void update_error(int err) {
+  Serial.printf("CALLBACK:  HTTP update fatal error code %d\n", err);
 }
 
 void loop() {
   // wait for WiFi connection
   if ((WiFiMulti.run() == WL_CONNECTED)) {
 
-    WiFiClient client;
+    NetworkClient client;
 
     // The line below is optional. It can be used to blink the LED on the board during flashing
     // The LED will be on during download of one buffer of data from the network. The LED will
@@ -50,23 +64,21 @@ void loop() {
     // value is used to put the LED on. If the LED is on with HIGH, that value should be passed
     // httpUpdate.setLedPin(LED_BUILTIN, LOW);
 
+    httpUpdate.onStart(update_started);
+    httpUpdate.onEnd(update_finished);
+    httpUpdate.onProgress(update_progress);
+    httpUpdate.onError(update_error);
+
     t_httpUpdate_return ret = httpUpdate.update(client, "http://server/file.bin");
     // Or:
     //t_httpUpdate_return ret = httpUpdate.update(client, "server", 80, "/file.bin");
 
     switch (ret) {
-      case HTTP_UPDATE_FAILED:
-        Serial.printf("HTTP_UPDATE_FAILED Error (%d): %s\n", httpUpdate.getLastError(), httpUpdate.getLastErrorString().c_str());
-        break;
+      case HTTP_UPDATE_FAILED: Serial.printf("HTTP_UPDATE_FAILED Error (%d): %s\n", httpUpdate.getLastError(), httpUpdate.getLastErrorString().c_str()); break;
 
-      case HTTP_UPDATE_NO_UPDATES:
-        Serial.println("HTTP_UPDATE_NO_UPDATES");
-        break;
+      case HTTP_UPDATE_NO_UPDATES: Serial.println("HTTP_UPDATE_NO_UPDATES"); break;
 
-      case HTTP_UPDATE_OK:
-        Serial.println("HTTP_UPDATE_OK");
-        break;
+      case HTTP_UPDATE_OK: Serial.println("HTTP_UPDATE_OK"); break;
     }
   }
 }
-
diff --git a/libraries/HTTPUpdate/examples/httpUpdateSPIFFS/ci.json b/libraries/HTTPUpdate/examples/httpUpdateSPIFFS/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/HTTPUpdate/examples/httpUpdateSPIFFS/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/HTTPUpdate/examples/httpUpdateSPIFFS/httpUpdateSPIFFS.ino b/libraries/HTTPUpdate/examples/httpUpdateSPIFFS/httpUpdateSPIFFS.ino
index a07e6d2f4aa..9706e576757 100644
--- a/libraries/HTTPUpdate/examples/httpUpdateSPIFFS/httpUpdateSPIFFS.ino
+++ b/libraries/HTTPUpdate/examples/httpUpdateSPIFFS/httpUpdateSPIFFS.ino
@@ -32,7 +32,6 @@ void setup() {
 
   WiFi.mode(WIFI_STA);
   WiFiMulti.addAP("SSID", "PASSWORD");
-
 }
 
 void loop() {
@@ -41,7 +40,7 @@ void loop() {
 
     Serial.println("Update SPIFFS...");
 
-    WiFiClient client;
+    NetworkClient client;
 
     // The line below is optional. It can be used to blink the LED on the board during flashing
     // The LED will be on during download of one buffer of data from the network. The LED will
@@ -57,19 +56,12 @@ void loop() {
       ret = httpUpdate.update(client, "http://server/file.bin");
 
       switch (ret) {
-        case HTTP_UPDATE_FAILED:
-          Serial.printf("HTTP_UPDATE_FAILED Error (%d): %s", httpUpdate.getLastError(), httpUpdate.getLastErrorString().c_str());
-          break;
+        case HTTP_UPDATE_FAILED: Serial.printf("HTTP_UPDATE_FAILED Error (%d): %s", httpUpdate.getLastError(), httpUpdate.getLastErrorString().c_str()); break;
 
-        case HTTP_UPDATE_NO_UPDATES:
-          Serial.println("HTTP_UPDATE_NO_UPDATES");
-          break;
+        case HTTP_UPDATE_NO_UPDATES: Serial.println("HTTP_UPDATE_NO_UPDATES"); break;
 
-        case HTTP_UPDATE_OK:
-          Serial.println("HTTP_UPDATE_OK");
-          break;
+        case HTTP_UPDATE_OK: Serial.println("HTTP_UPDATE_OK"); break;
       }
     }
   }
 }
-
diff --git a/libraries/HTTPUpdate/examples/httpUpdateSecure/ci.json b/libraries/HTTPUpdate/examples/httpUpdateSecure/ci.json
new file mode 100644
index 00000000000..cbdd28f773d
--- /dev/null
+++ b/libraries/HTTPUpdate/examples/httpUpdateSecure/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/HTTPUpdate/examples/httpUpdateSecure/httpUpdateSecure.ino b/libraries/HTTPUpdate/examples/httpUpdateSecure/httpUpdateSecure.ino
index 1c85ace02a5..d349c6983c1 100644
--- a/libraries/HTTPUpdate/examples/httpUpdateSecure/httpUpdateSecure.ino
+++ b/libraries/HTTPUpdate/examples/httpUpdateSecure/httpUpdateSecure.ino
@@ -38,34 +38,33 @@ void setClock() {
 /**
  * This is lets-encrypt-x3-cross-signed.pem
  */
-const char* rootCACertificate = \
-"-----BEGIN CERTIFICATE-----\n" \
-"MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n" \
-"MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n" \
-"DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n" \
-"SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n" \
-"GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n" \
-"AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n" \
-"q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n" \
-"SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n" \
-"Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n" \
-"a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n" \
-"/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n" \
-"AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n" \
-"CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n" \
-"bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n" \
-"c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n" \
-"VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n" \
-"ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n" \
-"MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n" \
-"Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n" \
-"AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n" \
-"uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n" \
-"wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n" \
-"X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n" \
-"PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n" \
-"KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n" \
-"-----END CERTIFICATE-----\n";
+const char *rootCACertificate = "-----BEGIN CERTIFICATE-----\n"
+                                "MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n"
+                                "MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n"
+                                "DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n"
+                                "SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n"
+                                "GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n"
+                                "AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n"
+                                "q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n"
+                                "SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n"
+                                "Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n"
+                                "a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n"
+                                "/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n"
+                                "AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n"
+                                "CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n"
+                                "bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n"
+                                "c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n"
+                                "VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n"
+                                "ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n"
+                                "MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n"
+                                "Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n"
+                                "AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n"
+                                "uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n"
+                                "wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n"
+                                "X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n"
+                                "PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n"
+                                "KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n"
+                                "-----END CERTIFICATE-----\n";
 
 void setup() {
 
@@ -92,11 +91,11 @@ void loop() {
 
     setClock();
 
-    WiFiClientSecure client;
+    NetworkClientSecure client;
     client.setCACert(rootCACertificate);
 
     // Reading data over SSL may be slow, use an adequate timeout
-    client.setTimeout(12000 / 1000); // timeout argument is defined in seconds for setTimeout
+    client.setTimeout(12000);  // timeout argument is defined in milliseconds for setTimeout
 
     // The line below is optional. It can be used to blink the LED on the board during flashing
     // The LED will be on during download of one buffer of data from the network. The LED will
@@ -106,23 +105,18 @@ void loop() {
     // value is used to put the LED on. If the LED is on with HIGH, that value should be passed
     // httpUpdate.setLedPin(LED_BUILTIN, HIGH);
 
-    t_httpUpdate_return ret = httpUpdate.update(client, "https://server/file.bin");
+    t_httpUpdate_return ret = httpUpdate.update(client, "https://server/file.bin", "", [](HTTPClient *client) {
+      client->setAuthorization("test", "password");
+    });
     // Or:
     //t_httpUpdate_return ret = httpUpdate.update(client, "server", 443, "/file.bin");
 
-
     switch (ret) {
-      case HTTP_UPDATE_FAILED:
-        Serial.printf("HTTP_UPDATE_FAILED Error (%d): %s\n", httpUpdate.getLastError(), httpUpdate.getLastErrorString().c_str());
-        break;
+      case HTTP_UPDATE_FAILED: Serial.printf("HTTP_UPDATE_FAILED Error (%d): %s\n", httpUpdate.getLastError(), httpUpdate.getLastErrorString().c_str()); break;
 
-      case HTTP_UPDATE_NO_UPDATES:
-        Serial.println("HTTP_UPDATE_NO_UPDATES");
-        break;
+      case HTTP_UPDATE_NO_UPDATES: Serial.println("HTTP_UPDATE_NO_UPDATES"); break;
 
-      case HTTP_UPDATE_OK:
-        Serial.println("HTTP_UPDATE_OK");
-        break;
+      case HTTP_UPDATE_OK: Serial.println("HTTP_UPDATE_OK"); break;
     }
   }
 }
diff --git a/libraries/HTTPUpdate/keywords.txt b/libraries/HTTPUpdate/keywords.txt
index 78be600d420..a882d8ce1a8 100644
--- a/libraries/HTTPUpdate/keywords.txt
+++ b/libraries/HTTPUpdate/keywords.txt
@@ -1,19 +1,19 @@
 #######################################
-# Syntax Coloring Map For ESP8266httpUpdate
+# Syntax Coloring Map For HTTPUpdate
 #######################################
 
 #######################################
 # Library (KEYWORD3)
 #######################################
 
-ESP8266httpUpdate	KEYWORD3		RESERVED_WORD
+ESP32httpUpdate	KEYWORD3		RESERVED_WORD
 
 #######################################
 # Datatypes (KEYWORD1)
 #######################################
 
 HTTPUpdateResult	KEYWORD1		DATA_TYPE
-ESPhttpUpdate	KEYWORD1		DATA_TYPE
+httpUpdate	KEYWORD1		DATA_TYPE
 
 #######################################
 # Methods and Functions (KEYWORD2)
diff --git a/libraries/HTTPUpdate/library.properties b/libraries/HTTPUpdate/library.properties
index 5147ddec2c9..419f3b97b3f 100644
--- a/libraries/HTTPUpdate/library.properties
+++ b/libraries/HTTPUpdate/library.properties
@@ -1,5 +1,5 @@
 name=HTTPUpdate
-version=1.3
+version=3.2.0
 author=Markus Sattler
 maintainer=Markus Sattler
 sentence=Http Update for ESP32
diff --git a/libraries/HTTPUpdate/src/HTTPUpdate.cpp b/libraries/HTTPUpdate/src/HTTPUpdate.cpp
index f4c3d250fa7..1eda0a4f7e5 100644
--- a/libraries/HTTPUpdate/src/HTTPUpdate.cpp
+++ b/libraries/HTTPUpdate/src/HTTPUpdate.cpp
@@ -25,126 +25,117 @@
 
 #include "HTTPUpdate.h"
 #include <StreamString.h>
+#if SOC_WIFI_SUPPORTED
+#include "WiFi.h"
+#endif
 
 #include <esp_partition.h>
-#include <esp_ota_ops.h>                // get running partition
+#include <esp_ota_ops.h>  // get running partition
 
 // To do extern "C" uint32_t _SPIFFS_start;
 // To do extern "C" uint32_t _SPIFFS_end;
 
-HTTPUpdate::HTTPUpdate(void)
-        : _httpClientTimeout(8000), _ledPin(-1)
-{
+HTTPUpdate::HTTPUpdate(void) : HTTPUpdate(8000) {}
+
+HTTPUpdate::HTTPUpdate(int httpClientTimeout) : _httpClientTimeout(httpClientTimeout), _ledPin(-1) {
+  _followRedirects = HTTPC_DISABLE_FOLLOW_REDIRECTS;
+  _md5Sum = String();
+  _user = String();
+  _password = String();
+  _auth = String();
 }
 
-HTTPUpdate::HTTPUpdate(int httpClientTimeout)
-        : _httpClientTimeout(httpClientTimeout), _ledPin(-1)
-{
+HTTPUpdate::~HTTPUpdate(void) {}
+
+HTTPUpdateResult HTTPUpdate::update(NetworkClient &client, const String &url, const String &currentVersion, HTTPUpdateRequestCB requestCB) {
+  HTTPClient http;
+  if (!http.begin(client, url)) {
+    return HTTP_UPDATE_FAILED;
+  }
+  return handleUpdate(http, currentVersion, false, requestCB);
 }
 
-HTTPUpdate::~HTTPUpdate(void)
-{
+HTTPUpdateResult HTTPUpdate::updateSpiffs(HTTPClient &httpClient, const String &currentVersion, HTTPUpdateRequestCB requestCB) {
+  return handleUpdate(httpClient, currentVersion, true, requestCB);
 }
 
-HTTPUpdateResult HTTPUpdate::update(WiFiClient& client, const String& url, const String& currentVersion)
-{
-    HTTPClient http;
-    if(!http.begin(client, url))
-    {
-        return HTTP_UPDATE_FAILED;
-    }
-    return handleUpdate(http, currentVersion, false);
+HTTPUpdateResult HTTPUpdate::updateSpiffs(NetworkClient &client, const String &url, const String &currentVersion, HTTPUpdateRequestCB requestCB) {
+  HTTPClient http;
+  if (!http.begin(client, url)) {
+    return HTTP_UPDATE_FAILED;
+  }
+  return handleUpdate(http, currentVersion, true, requestCB);
 }
 
-HTTPUpdateResult HTTPUpdate::updateSpiffs(WiFiClient& client, const String& url, const String& currentVersion)
-{
-    HTTPClient http;
-    if(!http.begin(client, url))
-    {
-        return HTTP_UPDATE_FAILED;
-    }
-    return handleUpdate(http, currentVersion, true);
+HTTPUpdateResult HTTPUpdate::update(HTTPClient &httpClient, const String &currentVersion, HTTPUpdateRequestCB requestCB) {
+  return handleUpdate(httpClient, currentVersion, false, requestCB);
 }
 
-HTTPUpdateResult HTTPUpdate::update(WiFiClient& client, const String& host, uint16_t port, const String& uri,
-        const String& currentVersion)
-{
-    HTTPClient http;
-    if(!http.begin(client, host, port, uri))
-    {
-        return HTTP_UPDATE_FAILED;
-    }
-    return handleUpdate(http, currentVersion, false);
+HTTPUpdateResult
+  HTTPUpdate::update(NetworkClient &client, const String &host, uint16_t port, const String &uri, const String &currentVersion, HTTPUpdateRequestCB requestCB) {
+  HTTPClient http;
+  if (!http.begin(client, host, port, uri)) {
+    return HTTP_UPDATE_FAILED;
+  }
+  return handleUpdate(http, currentVersion, false, requestCB);
 }
 
 /**
  * return error code as int
  * @return int error code
  */
-int HTTPUpdate::getLastError(void)
-{
-    return _lastError;
+int HTTPUpdate::getLastError(void) {
+  return _lastError;
 }
 
 /**
  * return error code as String
  * @return String error
  */
-String HTTPUpdate::getLastErrorString(void)
-{
+String HTTPUpdate::getLastErrorString(void) {
 
-    if(_lastError == 0) {
-        return String(); // no error
-    }
+  if (_lastError == 0) {
+    return String();  // no error
+  }
 
-    // error from Update class
-    if(_lastError > 0) {
-        StreamString error;
-        Update.printError(error);
-        error.trim(); // remove line ending
-        return String("Update error: ") + error;
-    }
+  // error from Update class
+  if (_lastError > 0) {
+    StreamString error;
+    Update.printError(error);
+    error.trim();  // remove line ending
+    return String("Update error: ") + error;
+  }
 
-    // error from http client
-    if(_lastError > -100) {
-        return String("HTTP error: ") + HTTPClient::errorToString(_lastError);
-    }
+  // error from http client
+  if (_lastError > -100) {
+    return String("HTTP error: ") + HTTPClient::errorToString(_lastError);
+  }
 
-    switch(_lastError) {
-    case HTTP_UE_TOO_LESS_SPACE:
-        return "Not Enough space";
-    case HTTP_UE_SERVER_NOT_REPORT_SIZE:
-        return "Server Did Not Report Size";
-    case HTTP_UE_SERVER_FILE_NOT_FOUND:
-        return "File Not Found (404)";
-    case HTTP_UE_SERVER_FORBIDDEN:
-        return "Forbidden (403)";
-    case HTTP_UE_SERVER_WRONG_HTTP_CODE:
-        return "Wrong HTTP Code";
-    case HTTP_UE_SERVER_FAULTY_MD5:
-        return "Wrong MD5";
-    case HTTP_UE_BIN_VERIFY_HEADER_FAILED:
-        return "Verify Bin Header Failed";
-    case HTTP_UE_BIN_FOR_WRONG_FLASH:
-        return "New Binary Does Not Fit Flash Size";
-    case HTTP_UE_NO_PARTITION:
-        return "Partition Could Not be Found";
-    }
+  switch (_lastError) {
+    case HTTP_UE_TOO_LESS_SPACE:           return "Not Enough space";
+    case HTTP_UE_SERVER_NOT_REPORT_SIZE:   return "Server Did Not Report Size";
+    case HTTP_UE_SERVER_FILE_NOT_FOUND:    return "File Not Found (404)";
+    case HTTP_UE_SERVER_FORBIDDEN:         return "Forbidden (403)";
+    case HTTP_UE_SERVER_WRONG_HTTP_CODE:   return "Wrong HTTP Code";
+    case HTTP_UE_SERVER_FAULTY_MD5:        return "Wrong MD5";
+    case HTTP_UE_BIN_VERIFY_HEADER_FAILED: return "Verify Bin Header Failed";
+    case HTTP_UE_BIN_FOR_WRONG_FLASH:      return "New Binary Does Not Fit Flash Size";
+    case HTTP_UE_NO_PARTITION:             return "Partition Could Not be Found";
+  }
 
-    return String();
+  return String();
 }
 
-
 String getSketchSHA256() {
-  const size_t HASH_LEN = 32; // SHA-256 digest length
+  const size_t HASH_LEN = 32;  // SHA-256 digest length
 
-  uint8_t sha_256[HASH_LEN] = { 0 };
+  uint8_t sha_256[HASH_LEN] = {0};
 
-// get sha256 digest for running partition
-  if(esp_partition_get_sha256(esp_ota_get_running_partition(), sha_256) == 0) {
+  // get sha256 digest for running partition
+  if (esp_partition_get_sha256(esp_ota_get_running_partition(), sha_256) == 0) {
     char buffer[2 * HASH_LEN + 1];
 
-    for(size_t index = 0; index < HASH_LEN; index++) {
+    for (size_t index = 0; index < HASH_LEN; index++) {
       uint8_t nibble = (sha_256[index] & 0xf0) >> 4;
       buffer[2 * index] = nibble < 10 ? char(nibble + '0') : char(nibble - 10 + 'A');
 
@@ -167,129 +158,151 @@ String getSketchSHA256() {
  * @param currentVersion const char *
  * @return HTTPUpdateResult
  */
-HTTPUpdateResult HTTPUpdate::handleUpdate(HTTPClient& http, const String& currentVersion, bool spiffs)
-{
-
-    HTTPUpdateResult ret = HTTP_UPDATE_FAILED;
-
-    // use HTTP/1.0 for update since the update handler not support any transfer Encoding
-    http.useHTTP10(true);
-    http.setTimeout(_httpClientTimeout);
-    http.setUserAgent("ESP32-http-Update");
-    http.addHeader("Cache-Control", "no-cache");
-    http.addHeader("x-ESP32-STA-MAC", WiFi.macAddress());
-    http.addHeader("x-ESP32-AP-MAC", WiFi.softAPmacAddress());
-    http.addHeader("x-ESP32-free-space", String(ESP.getFreeSketchSpace()));
-    http.addHeader("x-ESP32-sketch-size", String(ESP.getSketchSize()));
-    String sketchMD5 = ESP.getSketchMD5();
-    if(sketchMD5.length() != 0) {
-        http.addHeader("x-ESP32-sketch-md5", sketchMD5);
-    }
-    // Add also a SHA256
-    String sketchSHA256 = getSketchSHA256();
-    if(sketchSHA256.length() != 0) {
-      http.addHeader("x-ESP32-sketch-sha256", sketchSHA256);
-    }
-    http.addHeader("x-ESP32-chip-size", String(ESP.getFlashChipSize()));
-    http.addHeader("x-ESP32-sdk-version", ESP.getSdkVersion());
+HTTPUpdateResult HTTPUpdate::handleUpdate(HTTPClient &http, const String &currentVersion, bool spiffs, HTTPUpdateRequestCB requestCB) {
+
+  HTTPUpdateResult ret = HTTP_UPDATE_FAILED;
+
+  // use HTTP/1.0 for update since the update handler not support any transfer Encoding
+  http.useHTTP10(true);
+  http.setTimeout(_httpClientTimeout);
+  http.setFollowRedirects(_followRedirects);
+  http.setUserAgent("ESP32-http-Update");
+  http.addHeader("Cache-Control", "no-cache");
+  http.addHeader("x-ESP32-BASE-MAC", Network.macAddress());
+#if SOC_WIFI_SUPPORTED
+  http.addHeader("x-ESP32-STA-MAC", WiFi.macAddress());
+  http.addHeader("x-ESP32-AP-MAC", WiFi.softAPmacAddress());
+#endif
+  http.addHeader("x-ESP32-free-space", String(ESP.getFreeSketchSpace()));
+  http.addHeader("x-ESP32-sketch-size", String(ESP.getSketchSize()));
+  String sketchMD5 = ESP.getSketchMD5();
+  if (sketchMD5.length() != 0) {
+    http.addHeader("x-ESP32-sketch-md5", sketchMD5);
+  }
+  // Add also a SHA256
+  String sketchSHA256 = getSketchSHA256();
+  if (sketchSHA256.length() != 0) {
+    http.addHeader("x-ESP32-sketch-sha256", sketchSHA256);
+  }
+  http.addHeader("x-ESP32-chip-size", String(ESP.getFlashChipSize()));
+  http.addHeader("x-ESP32-sdk-version", ESP.getSdkVersion());
 
-    if(spiffs) {
-        http.addHeader("x-ESP32-mode", "spiffs");
-    } else {
-        http.addHeader("x-ESP32-mode", "sketch");
-    }
+  if (spiffs) {
+    http.addHeader("x-ESP32-mode", "spiffs");
+  } else {
+    http.addHeader("x-ESP32-mode", "sketch");
+  }
 
-    if(currentVersion && currentVersion[0] != 0x00) {
-        http.addHeader("x-ESP32-version", currentVersion);
-    }
+  if (currentVersion && currentVersion[0] != 0x00) {
+    http.addHeader("x-ESP32-version", currentVersion);
+  }
+  if (requestCB) {
+    requestCB(&http);
+  }
 
-    const char * headerkeys[] = { "x-MD5" };
-    size_t headerkeyssize = sizeof(headerkeys) / sizeof(char*);
+  if (!_user.isEmpty() && !_password.isEmpty()) {
+    http.setAuthorization(_user.c_str(), _password.c_str());
+  }
 
-    // track these headers
-    http.collectHeaders(headerkeys, headerkeyssize);
+  if (!_auth.isEmpty()) {
+    http.setAuthorization(_auth.c_str());
+  }
 
+  const char *headerkeys[] = {"x-MD5"};
+  size_t headerkeyssize = sizeof(headerkeys) / sizeof(char *);
 
-    int code = http.GET();
-    int len = http.getSize();
+  // track these headers
+  http.collectHeaders(headerkeys, headerkeyssize);
 
-    if(code <= 0) {
-        log_e("HTTP error: %s\n", http.errorToString(code).c_str());
-        _lastError = code;
-        http.end();
-        return HTTP_UPDATE_FAILED;
-    }
+  int code = http.GET();
+  int len = http.getSize();
 
+  if (code <= 0) {
+    log_e("HTTP error: %s\n", http.errorToString(code).c_str());
+    _lastError = code;
+    http.end();
+    return HTTP_UPDATE_FAILED;
+  }
 
-    log_d("Header read fin.\n");
-    log_d("Server header:\n");
-    log_d(" - code: %d\n", code);
-    log_d(" - len: %d\n", len);
+  log_d("Header read fin.\n");
+  log_d("Server header:\n");
+  log_d(" - code: %d\n", code);
+  log_d(" - len: %d\n", len);
 
-    if(http.hasHeader("x-MD5")) {
-        log_d(" - MD5: %s\n", http.header("x-MD5").c_str());
-    }
+  String md5;
+  if (_md5Sum.length()) {
+    md5 = _md5Sum;
+  } else if (http.hasHeader("x-MD5")) {
+    md5 = http.header("x-MD5");
+  }
+  if (md5.length()) {
+    log_d(" - MD5: %s\n", md5.c_str());
+  }
 
-    log_d("ESP32 info:\n");
-    log_d(" - free Space: %d\n", ESP.getFreeSketchSpace());
-    log_d(" - current Sketch Size: %d\n", ESP.getSketchSize());
+  log_d("ESP32 info:\n");
+  log_d(" - free Space: %d\n", ESP.getFreeSketchSpace());
+  log_d(" - current Sketch Size: %d\n", ESP.getSketchSize());
 
-    if(currentVersion && currentVersion[0] != 0x00) {
-        log_d(" - current version: %s\n", currentVersion.c_str() );
-    }
+  if (currentVersion && currentVersion[0] != 0x00) {
+    log_d(" - current version: %s\n", currentVersion.c_str());
+  }
 
-    switch(code) {
+  switch (code) {
     case HTTP_CODE_OK:  ///< OK (Start Update)
-        if(len > 0) {
-            bool startUpdate = true;
-            if(spiffs) {
-                const esp_partition_t* _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, NULL);
-                if(!_partition){
-                    _lastError = HTTP_UE_NO_PARTITION;
-                    return HTTP_UPDATE_FAILED;
-                }
-
-                if(len > _partition->size) {
-                    log_e("spiffsSize to low (%d) needed: %d\n", _partition->size, len);
-                    startUpdate = false;
-                }
-            } else {
-                int sketchFreeSpace = ESP.getFreeSketchSpace();
-                if(!sketchFreeSpace){
-                    _lastError = HTTP_UE_NO_PARTITION;
-                    return HTTP_UPDATE_FAILED;
-                }
-
-                if(len > sketchFreeSpace) {
-                    log_e("FreeSketchSpace to low (%d) needed: %d\n", sketchFreeSpace, len);
-                    startUpdate = false;
-                }
-            }
+      if (len > 0) {
+        bool startUpdate = true;
+        if (spiffs) {
+          const esp_partition_t *_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, NULL);
+          if (!_partition) {
+            _lastError = HTTP_UE_NO_PARTITION;
+            return HTTP_UPDATE_FAILED;
+          }
+
+          if (len > _partition->size) {
+            log_e("spiffsSize to low (%d) needed: %d\n", _partition->size, len);
+            startUpdate = false;
+          }
+        } else {
+          int sketchFreeSpace = ESP.getFreeSketchSpace();
+          if (!sketchFreeSpace) {
+            _lastError = HTTP_UE_NO_PARTITION;
+            return HTTP_UPDATE_FAILED;
+          }
+
+          if (len > sketchFreeSpace) {
+            log_e("FreeSketchSpace to low (%d) needed: %d\n", sketchFreeSpace, len);
+            startUpdate = false;
+          }
+        }
 
-            if(!startUpdate) {
-                _lastError = HTTP_UE_TOO_LESS_SPACE;
-                ret = HTTP_UPDATE_FAILED;
-            } else {
+        if (!startUpdate) {
+          _lastError = HTTP_UE_TOO_LESS_SPACE;
+          ret = HTTP_UPDATE_FAILED;
+        } else {
+          // Warn main app we're starting up...
+          if (_cbStart) {
+            _cbStart();
+          }
 
-                WiFiClient * tcp = http.getStreamPtr();
+          NetworkClient *tcp = http.getStreamPtr();
 
-// To do?                WiFiUDP::stopAll();
-// To do?                WiFiClient::stopAllExcept(tcp);
+          // To do?                NetworkUDP::stopAll();
+          // To do?                NetworkClient::stopAllExcept(tcp);
 
-                delay(100);
+          delay(100);
 
-                int command;
+          int command;
 
-                if(spiffs) {
-                    command = U_SPIFFS;
-                    log_d("runUpdate spiffs...\n");
-                } else {
-                    command = U_FLASH;
-                    log_d("runUpdate flash...\n");
-                }
+          if (spiffs) {
+            command = U_SPIFFS;
+            log_d("runUpdate spiffs...\n");
+          } else {
+            command = U_FLASH;
+            log_d("runUpdate flash...\n");
+          }
 
-                if(!spiffs) {
-/* To do
+          if (!spiffs) {
+            /* To do
                     uint8_t buf[4];
                     if(tcp->peekBytes(&buf[0], 4) != 4) {
                         log_e("peekBytes magic header failed\n");
@@ -299,16 +312,15 @@ HTTPUpdateResult HTTPUpdate::handleUpdate(HTTPClient& http, const String& curren
                     }
 */
 
-                    // check for valid first magic byte
-//                    if(buf[0] != 0xE9) {
-                    if(tcp->peek() != 0xE9) {
-                        log_e("Magic header does not start with 0xE9\n");
-                        _lastError = HTTP_UE_BIN_VERIFY_HEADER_FAILED;
-                        http.end();
-                        return HTTP_UPDATE_FAILED;
-
-                    }
-/* To do
+            // check for valid first magic byte
+            //                    if(buf[0] != 0xE9) {
+            if (tcp->peek() != 0xE9) {
+              log_e("Magic header does not start with 0xE9\n");
+              _lastError = HTTP_UE_BIN_VERIFY_HEADER_FAILED;
+              http.end();
+              return HTTP_UPDATE_FAILED;
+            }
+            /* To do
                     uint32_t bin_flash_size = ESP.magicFlashChipSize((buf[3] & 0xf0) >> 4);
 
                     // check if new bin fits to SPI flash
@@ -319,48 +331,52 @@ HTTPUpdateResult HTTPUpdate::handleUpdate(HTTPClient& http, const String& curren
                         return HTTP_UPDATE_FAILED;
                     }
 */
-                }
-                if(runUpdate(*tcp, len, http.header("x-MD5"), command)) {
-                    ret = HTTP_UPDATE_OK;
-                    log_d("Update ok\n");
-                    http.end();
-
-                    if(_rebootOnUpdate && !spiffs) {
-                        ESP.restart();
-                    }
+          }
+          if (runUpdate(*tcp, len, md5, command)) {
+            ret = HTTP_UPDATE_OK;
+            log_d("Update ok\n");
+            http.end();
+            // Warn main app we're all done
+            if (_cbEnd) {
+              _cbEnd();
+            }
 
-                } else {
-                    ret = HTTP_UPDATE_FAILED;
-                    log_e("Update failed\n");
-                }
+            if (_rebootOnUpdate && !spiffs) {
+              ESP.restart();
             }
-        } else {
-            _lastError = HTTP_UE_SERVER_NOT_REPORT_SIZE;
+
+          } else {
             ret = HTTP_UPDATE_FAILED;
-            log_e("Content-Length was 0 or wasn't set by Server?!\n");
+            log_e("Update failed\n");
+          }
         }
-        break;
+      } else {
+        _lastError = HTTP_UE_SERVER_NOT_REPORT_SIZE;
+        ret = HTTP_UPDATE_FAILED;
+        log_e("Content-Length was 0 or wasn't set by Server?!\n");
+      }
+      break;
     case HTTP_CODE_NOT_MODIFIED:
-        ///< Not Modified (No updates)
-        ret = HTTP_UPDATE_NO_UPDATES;
-        break;
+      ///< Not Modified (No updates)
+      ret = HTTP_UPDATE_NO_UPDATES;
+      break;
     case HTTP_CODE_NOT_FOUND:
-        _lastError = HTTP_UE_SERVER_FILE_NOT_FOUND;
-        ret = HTTP_UPDATE_FAILED;
-        break;
+      _lastError = HTTP_UE_SERVER_FILE_NOT_FOUND;
+      ret = HTTP_UPDATE_FAILED;
+      break;
     case HTTP_CODE_FORBIDDEN:
-        _lastError = HTTP_UE_SERVER_FORBIDDEN;
-        ret = HTTP_UPDATE_FAILED;
-        break;
+      _lastError = HTTP_UE_SERVER_FORBIDDEN;
+      ret = HTTP_UPDATE_FAILED;
+      break;
     default:
-        _lastError = HTTP_UE_SERVER_WRONG_HTTP_CODE;
-        ret = HTTP_UPDATE_FAILED;
-        log_e("HTTP Code is (%d)\n", code);
-        break;
-    }
+      _lastError = HTTP_UE_SERVER_WRONG_HTTP_CODE;
+      ret = HTTP_UPDATE_FAILED;
+      log_e("HTTP Code is (%d)\n", code);
+      break;
+  }
 
-    http.end();
-    return ret;
+  http.end();
+  return ret;
 }
 
 /**
@@ -370,46 +386,57 @@ HTTPUpdateResult HTTPUpdate::handleUpdate(HTTPClient& http, const String& curren
  * @param md5 String
  * @return true if Update ok
  */
-bool HTTPUpdate::runUpdate(Stream& in, uint32_t size, String md5, int command)
-{
+bool HTTPUpdate::runUpdate(Stream &in, uint32_t size, String md5, int command) {
 
-    StreamString error;
+  StreamString error;
 
-    if(!Update.begin(size, command, _ledPin, _ledOn)) {
-        _lastError = Update.getError();
-        Update.printError(error);
-        error.trim(); // remove line ending
-        log_e("Update.begin failed! (%s)\n", error.c_str());
-        return false;
-    }
+  if (_cbProgress) {
+    Update.onProgress(_cbProgress);
+  }
 
-    if(md5.length()) {
-        if(!Update.setMD5(md5.c_str())) {
-            _lastError = HTTP_UE_SERVER_FAULTY_MD5;
-            log_e("Update.setMD5 failed! (%s)\n", md5.c_str());
-            return false;
-        }
-    }
+  if (!Update.begin(size, command, _ledPin, _ledOn)) {
+    _lastError = Update.getError();
+    Update.printError(error);
+    error.trim();  // remove line ending
+    log_e("Update.begin failed! (%s)\n", error.c_str());
+    return false;
+  }
 
-// To do: the SHA256 could be checked if the server sends it
+  if (_cbProgress) {
+    _cbProgress(0, size);
+  }
 
-    if(Update.writeStream(in) != size) {
-        _lastError = Update.getError();
-        Update.printError(error);
-        error.trim(); // remove line ending
-        log_e("Update.writeStream failed! (%s)\n", error.c_str());
-        return false;
+  if (md5.length()) {
+    if (!Update.setMD5(md5.c_str())) {
+      _lastError = HTTP_UE_SERVER_FAULTY_MD5;
+      log_e("Update.setMD5 failed! (%s)\n", md5.c_str());
+      return false;
     }
+  }
 
-    if(!Update.end()) {
-        _lastError = Update.getError();
-        Update.printError(error);
-        error.trim(); // remove line ending
-        log_e("Update.end failed! (%s)\n", error.c_str());
-        return false;
-    }
+  // To do: the SHA256 could be checked if the server sends it
+
+  if (Update.writeStream(in) != size) {
+    _lastError = Update.getError();
+    Update.printError(error);
+    error.trim();  // remove line ending
+    log_e("Update.writeStream failed! (%s)\n", error.c_str());
+    return false;
+  }
+
+  if (_cbProgress) {
+    _cbProgress(size, size);
+  }
+
+  if (!Update.end()) {
+    _lastError = Update.getError();
+    Update.printError(error);
+    error.trim();  // remove line ending
+    log_e("Update.end failed! (%s)\n", error.c_str());
+    return false;
+  }
 
-    return true;
+  return true;
 }
 
 #if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_HTTPUPDATE)
diff --git a/libraries/HTTPUpdate/src/HTTPUpdate.h b/libraries/HTTPUpdate/src/HTTPUpdate.h
index f126cba0639..a48d1a89a3e 100644
--- a/libraries/HTTPUpdate/src/HTTPUpdate.h
+++ b/libraries/HTTPUpdate/src/HTTPUpdate.h
@@ -27,71 +27,130 @@
 #define ___HTTP_UPDATE_H___
 
 #include <Arduino.h>
-#include <WiFi.h>
-#include <WiFiClient.h>
-#include <WiFiUdp.h>
+#include <Network.h>
 #include <HTTPClient.h>
 #include <Update.h>
 
 /// note we use HTTP client errors too so we start at 100
-#define HTTP_UE_TOO_LESS_SPACE              (-100)
-#define HTTP_UE_SERVER_NOT_REPORT_SIZE      (-101)
-#define HTTP_UE_SERVER_FILE_NOT_FOUND       (-102)
-#define HTTP_UE_SERVER_FORBIDDEN            (-103)
-#define HTTP_UE_SERVER_WRONG_HTTP_CODE      (-104)
-#define HTTP_UE_SERVER_FAULTY_MD5           (-105)
-#define HTTP_UE_BIN_VERIFY_HEADER_FAILED    (-106)
-#define HTTP_UE_BIN_FOR_WRONG_FLASH         (-107)
-#define HTTP_UE_NO_PARTITION                (-108)
+#define HTTP_UE_TOO_LESS_SPACE           (-100)
+#define HTTP_UE_SERVER_NOT_REPORT_SIZE   (-101)
+#define HTTP_UE_SERVER_FILE_NOT_FOUND    (-102)
+#define HTTP_UE_SERVER_FORBIDDEN         (-103)
+#define HTTP_UE_SERVER_WRONG_HTTP_CODE   (-104)
+#define HTTP_UE_SERVER_FAULTY_MD5        (-105)
+#define HTTP_UE_BIN_VERIFY_HEADER_FAILED (-106)
+#define HTTP_UE_BIN_FOR_WRONG_FLASH      (-107)
+#define HTTP_UE_NO_PARTITION             (-108)
 
 enum HTTPUpdateResult {
-    HTTP_UPDATE_FAILED,
-    HTTP_UPDATE_NO_UPDATES,
-    HTTP_UPDATE_OK
+  HTTP_UPDATE_FAILED,
+  HTTP_UPDATE_NO_UPDATES,
+  HTTP_UPDATE_OK
 };
 
-typedef HTTPUpdateResult t_httpUpdate_return; // backward compatibility
+typedef HTTPUpdateResult t_httpUpdate_return;  // backward compatibility
 
-class HTTPUpdate
-{
-public:
-    HTTPUpdate(void);
-    HTTPUpdate(int httpClientTimeout);
-    ~HTTPUpdate(void);
-
-    void rebootOnUpdate(bool reboot)
-    {
-        _rebootOnUpdate = reboot;
-    }
-
-    void setLedPin(int ledPin = -1, uint8_t ledOn = HIGH)
-    {
-        _ledPin = ledPin;
-        _ledOn = ledOn;
-    }
-
-    t_httpUpdate_return update(WiFiClient& client, const String& url, const String& currentVersion = "");
+using HTTPUpdateStartCB = std::function<void()>;
+using HTTPUpdateRequestCB = std::function<void(HTTPClient *)>;
+using HTTPUpdateEndCB = std::function<void()>;
+using HTTPUpdateErrorCB = std::function<void(int)>;
+using HTTPUpdateProgressCB = std::function<void(int, int)>;
 
-    t_httpUpdate_return update(WiFiClient& client, const String& host, uint16_t port, const String& uri = "/",
-                               const String& currentVersion = "");
-
-    t_httpUpdate_return updateSpiffs(WiFiClient& client, const String& url, const String& currentVersion = "");
-
-
-    int getLastError(void);
-    String getLastErrorString(void);
+class HTTPUpdate {
+public:
+  HTTPUpdate(void);
+  HTTPUpdate(int httpClientTimeout);
+  ~HTTPUpdate(void);
+
+  void rebootOnUpdate(bool reboot) {
+    _rebootOnUpdate = reboot;
+  }
+
+  /**
+      * set redirect follow mode. See `followRedirects_t` enum for available modes.
+      * @param follow
+      */
+  void setFollowRedirects(followRedirects_t follow) {
+    _followRedirects = follow;
+  }
+
+  void setLedPin(int ledPin = -1, uint8_t ledOn = HIGH) {
+    _ledPin = ledPin;
+    _ledOn = ledOn;
+  }
+
+  void setMD5sum(const String &md5Sum) {
+    _md5Sum = md5Sum;
+  }
+
+  void setAuthorization(const String &user, const String &password) {
+    _user = user;
+    _password = password;
+  }
+
+  void setAuthorization(const String &auth) {
+    _auth = auth;
+  }
+
+  t_httpUpdate_return update(NetworkClient &client, const String &url, const String &currentVersion = "", HTTPUpdateRequestCB requestCB = NULL);
+
+  t_httpUpdate_return update(
+    NetworkClient &client, const String &host, uint16_t port, const String &uri = "/", const String &currentVersion = "", HTTPUpdateRequestCB requestCB = NULL
+  );
+
+  t_httpUpdate_return updateSpiffs(NetworkClient &client, const String &url, const String &currentVersion = "", HTTPUpdateRequestCB requestCB = NULL);
+
+  t_httpUpdate_return update(HTTPClient &httpClient, const String &currentVersion = "", HTTPUpdateRequestCB requestCB = NULL);
+
+  t_httpUpdate_return updateSpiffs(HTTPClient &httpClient, const String &currentVersion = "", HTTPUpdateRequestCB requestCB = NULL);
+
+  // Notification callbacks
+  void onStart(HTTPUpdateStartCB cbOnStart) {
+    _cbStart = cbOnStart;
+  }
+  void onEnd(HTTPUpdateEndCB cbOnEnd) {
+    _cbEnd = cbOnEnd;
+  }
+  void onError(HTTPUpdateErrorCB cbOnError) {
+    _cbError = cbOnError;
+  }
+  void onProgress(HTTPUpdateProgressCB cbOnProgress) {
+    _cbProgress = cbOnProgress;
+  }
+
+  int getLastError(void);
+  String getLastErrorString(void);
 
 protected:
-    t_httpUpdate_return handleUpdate(HTTPClient& http, const String& currentVersion, bool spiffs = false);
-    bool runUpdate(Stream& in, uint32_t size, String md5, int command = U_FLASH);
+  t_httpUpdate_return handleUpdate(HTTPClient &http, const String &currentVersion, bool spiffs = false, HTTPUpdateRequestCB requestCB = NULL);
+  bool runUpdate(Stream &in, uint32_t size, String md5, int command = U_FLASH);
+
+  // Set the error and potentially use a CB to notify the application
+  void _setLastError(int err) {
+    _lastError = err;
+    if (_cbError) {
+      _cbError(err);
+    }
+  }
+  int _lastError;
+  bool _rebootOnUpdate = true;
 
-    int _lastError;
-    bool _rebootOnUpdate = true;
 private:
-    int _httpClientTimeout;
-
-    int _ledPin;
-    uint8_t _ledOn;
+  int _httpClientTimeout;
+  followRedirects_t _followRedirects;
+  String _user;
+  String _password;
+  String _auth;
+  String _md5Sum;
+
+  // Callbacks
+  HTTPUpdateStartCB _cbStart;
+  HTTPUpdateEndCB _cbEnd;
+  HTTPUpdateErrorCB _cbError;
+  HTTPUpdateProgressCB _cbProgress;
+
+  int _ledPin;
+  uint8_t _ledOn;
 };
 
 #if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_HTTPUPDATE)
diff --git a/libraries/HTTPUpdateServer/examples/WebUpdater/WebUpdater.ino b/libraries/HTTPUpdateServer/examples/WebUpdater/WebUpdater.ino
index f2503a7efe1..08747fa3e0c 100644
--- a/libraries/HTTPUpdateServer/examples/WebUpdater/WebUpdater.ino
+++ b/libraries/HTTPUpdateServer/examples/WebUpdater/WebUpdater.ino
@@ -3,7 +3,7 @@
 */
 
 #include <WiFi.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 #include <WebServer.h>
 #include <ESPmDNS.h>
 #include <HTTPUpdateServer.h>
@@ -13,9 +13,9 @@
 #define STAPSK  "your-password"
 #endif
 
-const char* host = "esp32-webupdate";
-const char* ssid = STASSID;
-const char* password = STAPSK;
+const char *host = "esp32-webupdate";
+const char *ssid = STASSID;
+const char *password = STAPSK;
 
 WebServer httpServer(80);
 HTTPUpdateServer httpUpdater;
@@ -33,12 +33,10 @@ void setup(void) {
     Serial.println("WiFi failed, retrying.");
   }
 
-  MDNS.begin(host);
-  if (MDNS.begin("esp32")) {
+  if (MDNS.begin(host)) {
     Serial.println("mDNS responder started");
   }
 
-
   httpUpdater.setup(&httpServer);
   httpServer.begin();
 
@@ -48,4 +46,4 @@ void setup(void) {
 
 void loop(void) {
   httpServer.handleClient();
-}
\ No newline at end of file
+}
diff --git a/libraries/HTTPUpdateServer/examples/WebUpdater/ci.json b/libraries/HTTPUpdateServer/examples/WebUpdater/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/HTTPUpdateServer/examples/WebUpdater/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/HTTPUpdateServer/keywords.txt b/libraries/HTTPUpdateServer/keywords.txt
index a6f8a0c191c..210c80ac9c0 100644
--- a/libraries/HTTPUpdateServer/keywords.txt
+++ b/libraries/HTTPUpdateServer/keywords.txt
@@ -17,4 +17,4 @@ setup	KEYWORD2
 
 #######################################
 # Constants (LITERAL1)
-#######################################
\ No newline at end of file
+#######################################
diff --git a/libraries/HTTPUpdateServer/library.properties b/libraries/HTTPUpdateServer/library.properties
index 0601fd57ced..9c793a26ac8 100644
--- a/libraries/HTTPUpdateServer/library.properties
+++ b/libraries/HTTPUpdateServer/library.properties
@@ -1,9 +1,9 @@
 name=HTTPUpdateServer
-version=1.0
+version=3.2.0
 author=Hristo Kapanakov
 maintainer=
 sentence=Simple HTTP Update server based on the WebServer
 paragraph=The library accepts HTTP post requests to the /update url, and updates the ESP32 firmware.
 category=Communication
 url=
-architectures=esp32
\ No newline at end of file
+architectures=esp32
diff --git a/libraries/HTTPUpdateServer/src/HTTPUpdateServer.h b/libraries/HTTPUpdateServer/src/HTTPUpdateServer.h
index aa53ce6b0fe..bb32bc03fdb 100644
--- a/libraries/HTTPUpdateServer/src/HTTPUpdateServer.h
+++ b/libraries/HTTPUpdateServer/src/HTTPUpdateServer.h
@@ -1,14 +1,13 @@
 #ifndef __HTTP_UPDATE_SERVER_H
 #define __HTTP_UPDATE_SERVER_H
 
-#include<SPIFFS.h>
+#include <SPIFFS.h>
 #include <StreamString.h>
 #include <Update.h>
 #include <WebServer.h>
 
-
 static const char serverIndex[] PROGMEM =
-R"(<!DOCTYPE html>
+  R"(<!DOCTYPE html>
      <html lang='en'>
      <head>
          <meta charset='utf-8'>
@@ -27,140 +26,146 @@ R"(<!DOCTYPE html>
      </form>
      </body>
      </html>)";
-static const char successResponse[] PROGMEM =
-"<META http-equiv=\"refresh\" content=\"15;URL=/\">Update Success! Rebooting...";
+static const char successResponse[] PROGMEM = "<META http-equiv=\"refresh\" content=\"15;URL=/\">Update Success! Rebooting...";
 
-class HTTPUpdateServer
-{
+class HTTPUpdateServer {
 public:
-    HTTPUpdateServer(bool serial_debug=false) {
-        _serial_output = serial_debug;
-        _server = NULL;
-        _username = emptyString;
-        _password = emptyString;
-        _authenticated = false;
-    }
-
-    void setup(WebServer *server)
-    {
-        setup(server, emptyString, emptyString);
-    }
-
-    void setup(WebServer *server, const String& path)
-    {
-        setup(server, path, emptyString, emptyString);
-    }
-
-    void setup(WebServer *server, const String& username, const String& password)
-    {
-        setup(server, "/update", username, password);
-    }
-
-    void setup(WebServer *server, const String& path, const String& username, const String& password)
-    {
-
-        _server = server;
-        _username = username;
-        _password = password;
-
-        // handler for the /update form page
-        _server->on(path.c_str(), HTTP_GET, [&]() {
-            if (_username != emptyString && _password != emptyString && !_server->authenticate(_username.c_str(), _password.c_str()))
-                return _server->requestAuthentication();
-            _server->send_P(200, PSTR("text/html"), serverIndex);
-            });
-
-        // handler for the /update form POST (once file upload finishes)
-        _server->on(path.c_str(), HTTP_POST, [&]() {
-            if (!_authenticated)
-                return _server->requestAuthentication();
-            if (Update.hasError()) {
-                _server->send(200, F("text/html"), String(F("Update error: ")) + _updaterError);
+  HTTPUpdateServer(bool serial_debug = false) {
+    _serial_output = serial_debug;
+    _server = NULL;
+    _username = emptyString;
+    _password = emptyString;
+    _authenticated = false;
+  }
+
+  void setup(WebServer *server) {
+    setup(server, emptyString, emptyString);
+  }
+
+  void setup(WebServer *server, const String &path) {
+    setup(server, path, emptyString, emptyString);
+  }
+
+  void setup(WebServer *server, const String &username, const String &password) {
+    setup(server, "/update", username, password);
+  }
+
+  void setup(WebServer *server, const String &path, const String &username, const String &password) {
+
+    _server = server;
+    _username = username;
+    _password = password;
+
+    // handler for the /update form page
+    _server->on(path.c_str(), HTTP_GET, [&]() {
+      if (_username != emptyString && _password != emptyString && !_server->authenticate(_username.c_str(), _password.c_str())) {
+        return _server->requestAuthentication();
+      }
+      _server->send_P(200, PSTR("text/html"), serverIndex);
+    });
+
+    // handler for the /update form POST (once file upload finishes)
+    _server->on(
+      path.c_str(), HTTP_POST,
+      [&]() {
+        if (!_authenticated) {
+          return _server->requestAuthentication();
+        }
+        if (Update.hasError()) {
+          _server->send(200, F("text/html"), String(F("Update error: ")) + _updaterError);
+        } else {
+          _server->client().setNoDelay(true);
+          _server->send_P(200, PSTR("text/html"), successResponse);
+          delay(100);
+          _server->client().stop();
+          ESP.restart();
+        }
+      },
+      [&]() {
+        // handler for the file upload, gets the sketch bytes, and writes
+        // them through the Update object
+        HTTPUpload &upload = _server->upload();
+
+        if (upload.status == UPLOAD_FILE_START) {
+          _updaterError.clear();
+          if (_serial_output) {
+            Serial.setDebugOutput(true);
+          }
+
+          _authenticated = (_username == emptyString || _password == emptyString || _server->authenticate(_username.c_str(), _password.c_str()));
+          if (!_authenticated) {
+            if (_serial_output) {
+              Serial.printf("Unauthenticated Update\n");
             }
-            else {
-                _server->client().setNoDelay(true);
-                _server->send_P(200, PSTR("text/html"), successResponse);
-                delay(100);
-                _server->client().stop();
-                ESP.restart();
+            return;
+          }
+
+          if (_serial_output) {
+            Serial.printf("Update: %s\n", upload.filename.c_str());
+          }
+          if (upload.name == "filesystem") {
+            if (!Update.begin(SPIFFS.totalBytes(), U_SPIFFS)) {  //start with max available size
+              if (_serial_output) {
+                Update.printError(Serial);
+              }
             }
-            }, [&]() {
-                // handler for the file upload, get's the sketch bytes, and writes
-                // them through the Update object
-                HTTPUpload& upload = _server->upload();
-
-                if (upload.status == UPLOAD_FILE_START) {
-                    _updaterError.clear();
-                    if (_serial_output)
-                        Serial.setDebugOutput(true);
-
-                    _authenticated = (_username == emptyString || _password == emptyString || _server->authenticate(_username.c_str(), _password.c_str()));
-                    if (!_authenticated) {
-                        if (_serial_output)
-                            Serial.printf("Unauthenticated Update\n");
-                        return;
-                    }
-
-                    if (_serial_output)
-                        Serial.printf("Update: %s\n", upload.filename.c_str());
-                    if (upload.name == "filesystem") {
-                        if (!Update.begin(SPIFFS.totalBytes(), U_SPIFFS)) {//start with max available size
-                            if (_serial_output) Update.printError(Serial);
-                        }
-                    }
-                    else {
-                        uint32_t maxSketchSpace = (ESP.getFreeSketchSpace() - 0x1000) & 0xFFFFF000;
-                        if (!Update.begin(maxSketchSpace, U_FLASH)) {//start with max available size
-                            _setUpdaterError();
-                        }
-                    }
-                }
-                else if (_authenticated && upload.status == UPLOAD_FILE_WRITE && !_updaterError.length()) {
-                    if (_serial_output) Serial.printf(".");
-                    if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) {
-                        _setUpdaterError();
-                    }
-                }
-                else if (_authenticated && upload.status == UPLOAD_FILE_END && !_updaterError.length()) {
-                    if (Update.end(true)) { //true to set the size to the current progress
-                        if (_serial_output) Serial.printf("Update Success: %u\nRebooting...\n", upload.totalSize);
-                    }
-                    else {
-                        _setUpdaterError();
-                    }
-                    if (_serial_output) Serial.setDebugOutput(false);
-                }
-                else if (_authenticated && upload.status == UPLOAD_FILE_ABORTED) {
-                    Update.end();
-                    if (_serial_output) Serial.println("Update was aborted");
-                }
-                delay(0);
-            });
-    }
-
-    void updateCredentials(const String& username, const String& password)
-    {
-        _username = username;
-        _password = password;
-    }
+          } else {
+            uint32_t maxSketchSpace = (ESP.getFreeSketchSpace() - 0x1000) & 0xFFFFF000;
+            if (!Update.begin(maxSketchSpace, U_FLASH)) {  //start with max available size
+              _setUpdaterError();
+            }
+          }
+        } else if (_authenticated && upload.status == UPLOAD_FILE_WRITE && !_updaterError.length()) {
+          if (_serial_output) {
+            Serial.printf(".");
+          }
+          if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) {
+            _setUpdaterError();
+          }
+        } else if (_authenticated && upload.status == UPLOAD_FILE_END && !_updaterError.length()) {
+          if (Update.end(true)) {  //true to set the size to the current progress
+            if (_serial_output) {
+              Serial.printf("Update Success: %u\nRebooting...\n", upload.totalSize);
+            }
+          } else {
+            _setUpdaterError();
+          }
+          if (_serial_output) {
+            Serial.setDebugOutput(false);
+          }
+        } else if (_authenticated && upload.status == UPLOAD_FILE_ABORTED) {
+          Update.end();
+          if (_serial_output) {
+            Serial.println("Update was aborted");
+          }
+        }
+        delay(0);
+      }
+    );
+  }
+
+  void updateCredentials(const String &username, const String &password) {
+    _username = username;
+    _password = password;
+  }
 
 protected:
-    void _setUpdaterError()
-    {
-        if (_serial_output) Update.printError(Serial);
-        StreamString str;
-        Update.printError(str);
-        _updaterError = str.c_str();
+  void _setUpdaterError() {
+    if (_serial_output) {
+      Update.printError(Serial);
     }
+    StreamString str;
+    Update.printError(str);
+    _updaterError = str.c_str();
+  }
 
 private:
-    bool _serial_output;
-    WebServer *_server;
-    String _username;
-    String _password;
-    bool _authenticated;
-    String _updaterError;
+  bool _serial_output;
+  WebServer *_server;
+  String _username;
+  String _password;
+  bool _authenticated;
+  String _updaterError;
 };
 
-
-#endif
\ No newline at end of file
+#endif
diff --git a/libraries/Insights/examples/DiagnosticsSmokeTest/DiagnosticsSmokeTest.ino b/libraries/Insights/examples/DiagnosticsSmokeTest/DiagnosticsSmokeTest.ino
new file mode 100644
index 00000000000..7102dfb19af
--- /dev/null
+++ b/libraries/Insights/examples/DiagnosticsSmokeTest/DiagnosticsSmokeTest.ino
@@ -0,0 +1,96 @@
+#include "Insights.h"
+#include "WiFi.h"
+#include "inttypes.h"
+#include "esp_err.h"
+#include "esp_random.h"
+
+const char insights_auth_key[] = "<ENTER YOUR AUTH KEY>";
+
+#define WIFI_SSID       "<ENTER YOUR SSID>"
+#define WIFI_PASSPHRASE "<ENTER YOUR PASSWORD>"
+
+#define MAX_CRASHES 5
+#define MAX_PTRS    30
+#define TAG         "sketch"
+
+RTC_NOINIT_ATTR static uint32_t s_reset_count;
+static void *s_ptrs[MAX_PTRS];
+
+static void smoke_test() {
+  int dice;
+  int count = 0;
+  bool allocating = false;
+
+  while (1) {
+    dice = esp_random() % 500;
+    log_i("dice=%d", dice);
+    if (dice > 0 && dice < 150) {
+      log_e("[count][%d]", count);
+    } else if (dice > 150 && dice < 300) {
+      log_w("[count][%d]", count);
+    } else if (dice > 300 && dice < 470) {
+      Insights.event(TAG, "[count][%d]", count);
+    } else {
+      /* 30 in 500 probability to crash */
+      if (s_reset_count > MAX_CRASHES) {
+        Insights.event(TAG, "[count][%d]", count);
+      } else {
+        log_e("[count][%d] [crash_count][%" PRIu32 "] [excvaddr][0x0f] Crashing...", count, s_reset_count);
+        //ToDo: find better way to crash
+        abort();
+      }
+    }
+
+    Insights.metrics.dumpHeap();
+    if (count % MAX_PTRS == 0) {
+      allocating = !allocating;
+      log_i("Allocating:%s\n", allocating ? "true" : "false");
+    }
+    if (allocating) {
+      uint32_t size = 1024 * (esp_random() % 8);
+      void *p = malloc(size);
+      if (p) {
+        memset(p, size, 'A' + (esp_random() % 26));
+        log_i("Allocated %" PRIu32 " bytes", size);
+      }
+      s_ptrs[count % MAX_PTRS] = p;
+    } else {
+      free(s_ptrs[count % MAX_PTRS]);
+      s_ptrs[count % MAX_PTRS] = NULL;
+      log_i("Freeing some memory...");
+    }
+
+    count++;
+    delay(1000);
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(WIFI_SSID, WIFI_PASSPHRASE);
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("");
+  Serial.println("WiFi connected");
+
+  if (!Insights.begin(insights_auth_key)) {
+    return;
+  }
+  Serial.println("=========================================");
+  Serial.printf("ESP Insights enabled Node ID %s\n", Insights.nodeID());
+  Serial.println("=========================================");
+
+  if (esp_reset_reason() == ESP_RST_POWERON) {
+    s_reset_count = 1;
+  } else {
+    s_reset_count++;
+  }
+}
+
+void loop() {
+  smoke_test();
+  delay(100);
+}
diff --git a/libraries/Insights/examples/DiagnosticsSmokeTest/README.md b/libraries/Insights/examples/DiagnosticsSmokeTest/README.md
new file mode 100644
index 00000000000..268e0704b09
--- /dev/null
+++ b/libraries/Insights/examples/DiagnosticsSmokeTest/README.md
@@ -0,0 +1,45 @@
+# Smoke Test App
+
+## What to expect in this example?
+
+- This example is expected to exercise the various features of the ESP Insights framework
+- As a smoke test, this allows you to validate, by a quick perusal of the ESP Insights dashboard, the functioning of all the high-level features
+
+
+## End-to-End Tests
+
+### Lifecycle of the test (Hard reset resets the cycle)
+* Device boots up and logs errors/warnings/events in random order every 10 seconds
+* Every error/warning/event log with "diag_smoke" tag is associated with an incremental counter
+* There's a 30/500 probability that device will crash, this is done for verification of crash
+* Device will crash only five times and hard reset will reset the counter to 1
+* On sixth boot onwards device will not crash and logs errors/warnings/events and adds heap metrics
+
+### Facilitate the Auth Key
+In this example we will be using the auth key that we downloaded while [setting up ESP Insights account](https://github.com/espressif/esp-insights/tree/main/examples#set-up-esp-insights-account).
+
+Copy Auth Key to the example
+```
+const char insights_auth_key[] = "<ENTER YOUR AUTH KEY>";
+```
+
+### Enter Wi-Fi Credentials
+Inside the example sketch, enter your Wi-Fi credentials in `WIFI_SSID` and `WIFI_PASSPHRASE` macros.
+
+### Setup
+* Build and flash the sketch and monitor the console
+* Device will eventually crash after some time
+* Before every crash you will see below log print
+```
+E (75826) diag_smoke: [count][7] [crash_count][1] [excvaddr][0x0f] Crashing...
+// [count][7]: count associated with the log
+// [crash_count][1]: This is the first crash since device boot up, this number will increment as the crash count increases
+// [excvaddr][0x0f]: Exception vaddr, will see this in crash verification part below
+```
+* You'll see five crashes([crash_count][5]) and after that device will not crash and will keep on logging and adding metrics
+* Onwards this point keep device running for more than 30 minutes
+* Now we are all set to visit the [dashboard](https://dashboard.insights.espressif.com)
+* Select the node-id printed on the console, look for the below log. It is printed early when device boots up
+```
+ESP Insights enabled for Node ID ----- wx3vEoGgJPk7Rn5JvRUFs9
+```
diff --git a/libraries/Insights/examples/DiagnosticsSmokeTest/ci.json b/libraries/Insights/examples/DiagnosticsSmokeTest/ci.json
new file mode 100644
index 00000000000..cbd69d50029
--- /dev/null
+++ b/libraries/Insights/examples/DiagnosticsSmokeTest/ci.json
@@ -0,0 +1,9 @@
+{
+  "requires": [
+    "CONFIG_ESP_INSIGHTS_ENABLED=y"
+  ],
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/Insights/examples/MinimalDiagnostics/MinimalDiagnostics.ino b/libraries/Insights/examples/MinimalDiagnostics/MinimalDiagnostics.ino
new file mode 100644
index 00000000000..0e13e930be8
--- /dev/null
+++ b/libraries/Insights/examples/MinimalDiagnostics/MinimalDiagnostics.ino
@@ -0,0 +1,29 @@
+#include "Insights.h"
+#include "WiFi.h"
+
+const char insights_auth_key[] = "<ENTER YOUR AUTH KEY>";
+
+#define WIFI_SSID       "<ENTER YOUR SSID>"
+#define WIFI_PASSPHRASE "<ENTER YOUR PASSWORD>"
+
+void setup() {
+  Serial.begin(115200);
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(WIFI_SSID, WIFI_PASSPHRASE);
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("");
+  Serial.println("WiFi connected");
+  if (!Insights.begin(insights_auth_key)) {
+    return;
+  }
+  Serial.println("=========================================");
+  Serial.printf("ESP Insights enabled Node ID %s\n", Insights.nodeID());
+  Serial.println("=========================================");
+}
+
+void loop() {
+  delay(1000);
+}
diff --git a/libraries/Insights/examples/MinimalDiagnostics/README.md b/libraries/Insights/examples/MinimalDiagnostics/README.md
new file mode 100644
index 00000000000..65a631d1236
--- /dev/null
+++ b/libraries/Insights/examples/MinimalDiagnostics/README.md
@@ -0,0 +1,43 @@
+# Minimal Diagnostics example
+- [What to expect in this example](#what-to-expect-in-this-example)
+- [Try out the example](#try-out-the-example)
+- [Insights Dashboard](#insights-dashboard)
+
+## What to expect in this example?
+- This example demonstrates the use of ESP Insights framework in minimal way
+- Device will try to connect with the configured Wi-Fi network
+- ESP Insights is enabled in this example, so any error/warning logs, crashes will be reported to cloud
+- This example collects heap and Wi-Fi metrics every 10 minutes and network variables are collected when they change
+
+## Try out the example
+
+### Facilitate the Auth Key
+In this example we will be using the auth key that we downloaded while [setting up ESP Insights account](https://github.com/espressif/esp-insights/tree/main/examples#set-up-esp-insights-account).
+
+Copy Auth Key to the example
+```
+const char insights_auth_key[] = "<ENTER YOUR AUTH KEY>";
+```
+
+### Enter Wi-Fi Credentials
+Inside the example sketch, enter your Wi-Fi credentials in `WIFI_SSID` and `WIFI_PASSPHRASE` macros.
+
+### Get the Node ID
+- Start the Serial monitor
+
+- Once the device boots, it will connect to the Wi-Fi network, look for logs similar to below and make a note of Node ID.
+```
+I (4161) esp_insights: =========================================
+I (4171) esp_insights: Insights enabled for Node ID 246F2880371C
+I (4181) esp_insights: =========================================
+```
+
+
+## Insights Dashboard
+Once everything is set up, any diagnostics information reported will show up on the [Insights Dashboard](https://dashboard.insights.espressif.com). Sign in using the your credentials.
+
+
+### Monitor the device diagnostics
+Visit [Nodes](https://dashboard.insights.espressif.com/home/nodes) section on the dashboard and click on the Node ID to monitor device diagnostics information.
+
+> Note: Diagnostics data is reported dynamically or when the buffers are filled to configured threshold. So, it can take some time for the logs to reflect on the dashboard. Moreover, if a large number of logs are generated then data will be sent to cloud but, if it fails(eg reasons: Wi-Fi failure, No internet) then any newer logs will be dropped.
diff --git a/libraries/Insights/examples/MinimalDiagnostics/ci.json b/libraries/Insights/examples/MinimalDiagnostics/ci.json
new file mode 100644
index 00000000000..cbd69d50029
--- /dev/null
+++ b/libraries/Insights/examples/MinimalDiagnostics/ci.json
@@ -0,0 +1,9 @@
+{
+  "requires": [
+    "CONFIG_ESP_INSIGHTS_ENABLED=y"
+  ],
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/Insights/library.properties b/libraries/Insights/library.properties
new file mode 100644
index 00000000000..fefe5aab177
--- /dev/null
+++ b/libraries/Insights/library.properties
@@ -0,0 +1,8 @@
+name=ESP Insights
+version=3.2.0
+author=Sanket Wadekar <sanket.wadekar@espressif.com>
+maintainer=Sanket Wadekar <sanket.wadekar@espressif.com>
+sentence=ESP Insights
+paragraph=With this library you can remotely monitor your device error logs, Network variables, WiFi/Heap Metrics, and also custom variables / metrics.
+url=https://insights.espressif.com
+architectures=esp32
diff --git a/libraries/Insights/src/Insights.cpp b/libraries/Insights/src/Insights.cpp
new file mode 100644
index 00000000000..d7ae8b77817
--- /dev/null
+++ b/libraries/Insights/src/Insights.cpp
@@ -0,0 +1,288 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "Insights.h"
+#ifdef CONFIG_ESP_INSIGHTS_ENABLED
+#include "esp_insights.h"
+#include "esp_diagnostics.h"
+#include "esp_diagnostics_metrics.h"
+#include "esp_diagnostics_system_metrics.h"
+#include "esp_diagnostics_variables.h"
+#include "esp_diagnostics_network_variables.h"
+
+const char *ERROR_INSIGHTS_NOT_INIT = "ESP Insights not initialized";
+
+#define BOOL_FN_OR_ERROR(f, e)                  \
+  if (!initialized) {                           \
+    log_e("%s", ERROR_INSIGHTS_NOT_INIT);       \
+    return false;                               \
+  }                                             \
+  esp_err_t err = f;                            \
+  if (err != ESP_OK) {                          \
+    log_e("ESP Insights " e ", err:0x%x", err); \
+  }                                             \
+  return err == ESP_OK;
+
+#define BOOL_FN_OR_ERROR_ARG(f, e, a)              \
+  if (!initialized) {                              \
+    log_e("%s", ERROR_INSIGHTS_NOT_INIT);          \
+    return false;                                  \
+  }                                                \
+  esp_err_t err = f;                               \
+  if (err != ESP_OK) {                             \
+    log_e("ESP Insights " e ", err:0x%x", a, err); \
+  }                                                \
+  return err == ESP_OK;
+
+#define VOID_FN_OR_ERROR(f)               \
+  if (!initialized) {                     \
+    log_e("%s", ERROR_INSIGHTS_NOT_INIT); \
+    return;                               \
+  }                                       \
+  f;
+
+ESPInsightsClass::ESPInsightsClass() : initialized(false) {}
+
+ESPInsightsClass::~ESPInsightsClass() {
+  end();
+}
+
+bool ESPInsightsClass::begin(const char *auth_key, const char *node_id, uint32_t log_type, bool alloc_ext_ram, bool use_default_transport) {
+  if (!initialized) {
+    if (log_type == 0xFFFFFFFF) {
+      log_type = (ESP_DIAG_LOG_TYPE_ERROR | ESP_DIAG_LOG_TYPE_WARNING | ESP_DIAG_LOG_TYPE_EVENT);
+    }
+    esp_insights_config_t config = {.log_type = log_type, .node_id = node_id, .auth_key = auth_key, .alloc_ext_ram = alloc_ext_ram};
+    esp_err_t err = ESP_OK;
+    if (use_default_transport) {
+      err = esp_insights_init(&config);
+    } else {
+      err = esp_insights_enable(&config);
+    }
+    if (err != ESP_OK) {
+      log_e("Failed to initialize ESP Insights, err:0x%x", err);
+    }
+    initialized = err == ESP_OK;
+    metrics.setInitialized(initialized);
+    variables.setInitialized(initialized);
+  } else {
+    log_i("ESP Insights already initialized");
+  }
+  return initialized;
+}
+
+void ESPInsightsClass::end() {
+  if (initialized) {
+    esp_insights_deinit();
+    initialized = false;
+    metrics.setInitialized(initialized);
+    variables.setInitialized(initialized);
+  }
+}
+
+const char *ESPInsightsClass::nodeID() {
+  if (!initialized) {
+    log_e("%s", ERROR_INSIGHTS_NOT_INIT);
+    return "";
+  }
+  return esp_insights_get_node_id();
+}
+
+bool ESPInsightsClass::event(const char *tag, const char *format, ...) {
+  if (!initialized) {
+    log_e("%s", ERROR_INSIGHTS_NOT_INIT);
+    return false;
+  }
+
+  char loc_buf[64];
+  char *temp = loc_buf;
+  va_list arg;
+  va_list copy;
+  va_start(arg, format);
+  va_copy(copy, arg);
+  int len = vsnprintf(temp, sizeof(loc_buf), format, copy);
+  va_end(copy);
+  if (len < 0) {
+    va_end(arg);
+    return false;
+  };
+  if (len >= (int)sizeof(loc_buf)) {  // comparison of same sign type for the compiler
+    temp = (char *)malloc(len + 1);
+    if (temp == NULL) {
+      va_end(arg);
+      return false;
+    }
+    len = vsnprintf(temp, len + 1, format, arg);
+  }
+  va_end(arg);
+  esp_err_t err = esp_diag_log_event(tag, "%s", temp);
+  if (temp != loc_buf) {
+    free(temp);
+  }
+  if (err != ESP_OK) {
+    log_e("Failed to send ESP Insights event, err:0x%x", err);
+  }
+  return err == ESP_OK;
+}
+
+bool ESPInsightsClass::send() {
+  BOOL_FN_OR_ERROR(esp_insights_send_data(), "Failed to send");
+}
+
+void ESPInsightsClass::dumpTasksStatus() {
+  VOID_FN_OR_ERROR(esp_diag_task_snapshot_dump());
+}
+
+// ESPInsightsMetricsClass
+
+bool ESPInsightsMetricsClass::addBool(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_BOOL), "Failed to add metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::addInt(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_INT), "Failed to add metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::addUint(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_UINT), "Failed to add metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::addFloat(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_FLOAT), "Failed to add metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::addString(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_STR), "Failed to add metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::addIPv4(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_IPv4), "Failed to add metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::addMAC(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_MAC), "Failed to add metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::setBool(const char *key, bool b) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_add_bool(key, b), "Failed to set metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::setInt(const char *key, int32_t i) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_add_int(key, i), "Failed to set metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::setUint(const char *key, uint32_t u) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_add_uint(key, u), "Failed to set metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::setFloat(const char *key, float f) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_add_float(key, f), "Failed to set metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::setString(const char *key, const char *str) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_add_str(key, str), "Failed to set metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::setIPv4(const char *key, uint32_t ip) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_add_ipv4(key, ip), "Failed to set metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::setMAC(const char *key, uint8_t *mac) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_add_mac(key, mac), "Failed to set metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::remove(const char *key) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_metrics_unregister(key), "Failed to remove metric '%s'", key);
+}
+
+bool ESPInsightsMetricsClass::removeAll() {
+  BOOL_FN_OR_ERROR(esp_diag_metrics_unregister_all(), "Failed to remove metrics");
+}
+
+void ESPInsightsMetricsClass::setHeapPeriod(uint32_t seconds) {
+  VOID_FN_OR_ERROR(esp_diag_heap_metrics_reset_interval(seconds));
+}
+
+bool ESPInsightsMetricsClass::dumpHeap() {
+  BOOL_FN_OR_ERROR(esp_diag_heap_metrics_dump(), "Failed to send heap metrics");
+}
+
+void ESPInsightsMetricsClass::setWiFiPeriod(uint32_t seconds) {
+  VOID_FN_OR_ERROR(esp_diag_wifi_metrics_reset_interval(seconds));
+}
+
+bool ESPInsightsMetricsClass::dumpWiFi() {
+  BOOL_FN_OR_ERROR(esp_diag_wifi_metrics_dump(), "Failed to send wifi metrics");
+}
+
+// ESPInsightsVariablesClass
+
+bool ESPInsightsVariablesClass::addBool(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_BOOL), "Failed to add variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::addInt(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_INT), "Failed to add variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::addUint(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_UINT), "Failed to add variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::addFloat(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_FLOAT), "Failed to add variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::addString(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_STR), "Failed to add variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::addIPv4(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_IPv4), "Failed to add variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::addMAC(const char *tag, const char *key, const char *label, const char *path) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_register(tag, key, label, path, ESP_DIAG_DATA_TYPE_MAC), "Failed to add variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::setBool(const char *key, bool b) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_add_bool(key, b), "Failed to set variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::setInt(const char *key, int32_t i) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_add_int(key, i), "Failed to set variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::setUint(const char *key, uint32_t u) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_add_uint(key, u), "Failed to set variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::setFloat(const char *key, float f) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_add_float(key, f), "Failed to set variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::setString(const char *key, const char *str) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_add_str(key, str), "Failed to set variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::setIPv4(const char *key, uint32_t ip) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_add_ipv4(key, ip), "Failed to set variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::setMAC(const char *key, uint8_t *mac) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_add_mac(key, mac), "Failed to set variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::remove(const char *key) {
+  BOOL_FN_OR_ERROR_ARG(esp_diag_variable_unregister(key), "Failed to remove variable '%s'", key);
+}
+
+bool ESPInsightsVariablesClass::removeAll() {
+  BOOL_FN_OR_ERROR(esp_diag_variable_unregister_all(), "Failed to remove variables");
+}
+
+ESPInsightsClass Insights;
+
+#endif
diff --git a/libraries/Insights/src/Insights.h b/libraries/Insights/src/Insights.h
new file mode 100644
index 00000000000..2e09818be94
--- /dev/null
+++ b/libraries/Insights/src/Insights.h
@@ -0,0 +1,119 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_INSIGHTS_ENABLED
+#include "Arduino.h"
+
+#ifdef __cplusplus
+
+class ESPInsightsMetricsClass {
+private:
+  bool initialized;
+
+public:
+  ESPInsightsMetricsClass() : initialized(false) {}
+
+  bool addBool(const char *tag, const char *key, const char *label, const char *path);
+  bool addInt(const char *tag, const char *key, const char *label, const char *path);
+  bool addUint(const char *tag, const char *key, const char *label, const char *path);
+  bool addFloat(const char *tag, const char *key, const char *label, const char *path);
+  bool addString(const char *tag, const char *key, const char *label, const char *path);
+  bool addIPv4(const char *tag, const char *key, const char *label, const char *path);
+  bool addMAC(const char *tag, const char *key, const char *label, const char *path);
+
+  bool setBool(const char *key, bool b);
+  bool setInt(const char *key, int32_t i);
+  bool setUint(const char *key, uint32_t u);
+  bool setFloat(const char *key, float f);
+  bool setString(const char *key, const char *str);
+  bool setIPv4(const char *key, uint32_t ip);
+  bool setMAC(const char *key, uint8_t *mac);
+
+  bool remove(const char *key);
+  bool removeAll();
+
+  void setHeapPeriod(uint32_t seconds);
+  void setWiFiPeriod(uint32_t seconds);
+
+  bool dumpHeap();
+  bool dumpWiFi();
+
+  //internal use
+  void setInitialized(bool init) {
+    initialized = init;
+  }
+};
+
+class ESPInsightsVariablesClass {
+private:
+  bool initialized;
+
+public:
+  ESPInsightsVariablesClass() : initialized(false) {}
+
+  bool addBool(const char *tag, const char *key, const char *label, const char *path);
+  bool addInt(const char *tag, const char *key, const char *label, const char *path);
+  bool addUint(const char *tag, const char *key, const char *label, const char *path);
+  bool addFloat(const char *tag, const char *key, const char *label, const char *path);
+  bool addString(const char *tag, const char *key, const char *label, const char *path);
+  bool addIPv4(const char *tag, const char *key, const char *label, const char *path);
+  bool addMAC(const char *tag, const char *key, const char *label, const char *path);
+
+  bool setBool(const char *key, bool b);
+  bool setInt(const char *key, int32_t i);
+  bool setUint(const char *key, uint32_t u);
+  bool setFloat(const char *key, float f);
+  bool setString(const char *key, const char *str);
+  bool setIPv4(const char *key, uint32_t ip);
+  bool setMAC(const char *key, uint8_t *mac);
+
+  bool remove(const char *key);
+  bool removeAll();
+
+  //internal use
+  void setInitialized(bool init) {
+    initialized = init;
+  }
+};
+
+class ESPInsightsClass {
+private:
+  bool initialized;
+
+public:
+  ESPInsightsMetricsClass metrics;
+  ESPInsightsVariablesClass variables;
+
+  ESPInsightsClass();
+  ~ESPInsightsClass();
+
+  bool begin(const char *auth_key, const char *node_id = NULL, uint32_t log_type = 0xFFFFFFFF, bool alloc_ext_ram = false, bool use_default_transport = true);
+  void end();
+  bool send();
+  const char *nodeID();
+
+  void dumpTasksStatus();
+
+  bool event(const char *tag, const char *format, ...);
+};
+
+extern ESPInsightsClass Insights;
+
+extern "C" {
+#endif
+
+#include "esp_err.h"
+#include "esp_log.h"
+esp_err_t esp_diag_log_event(const char *tag, const char *format, ...) __attribute__((format(printf, 2, 3)));
+#define insightsEvent(tag, format, ...) \
+  { esp_diag_log_event(tag, "EV (%" PRIu32 ") %s: " format, esp_log_timestamp(), tag, ##__VA_ARGS__); }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/LittleFS/examples/LITTLEFS_test/LITTLEFS_test.ino b/libraries/LittleFS/examples/LITTLEFS_test/LITTLEFS_test.ino
new file mode 100644
index 00000000000..f3d0ec60501
--- /dev/null
+++ b/libraries/LittleFS/examples/LITTLEFS_test/LITTLEFS_test.ino
@@ -0,0 +1,286 @@
+#include <Arduino.h>
+#include "FS.h"
+#include <LittleFS.h>
+
+/* You only need to format LittleFS the first time you run a
+   test or else use the LITTLEFS plugin to create a partition
+   https://github.com/lorol/arduino-esp32littlefs-plugin
+
+   If you test two partitions, you need to use a custom
+   partition.csv file, see in the sketch folder */
+
+//#define TWOPART
+
+#define FORMAT_LITTLEFS_IF_FAILED true
+
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\r\n", dirname);
+
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("- failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println(" - not a directory");
+    return;
+  }
+
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.println(file.name());
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
+    } else {
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("\tSIZE: ");
+      Serial.println(file.size());
+    }
+    file = root.openNextFile();
+  }
+}
+
+void createDir(fs::FS &fs, const char *path) {
+  Serial.printf("Creating Dir: %s\n", path);
+  if (fs.mkdir(path)) {
+    Serial.println("Dir created");
+  } else {
+    Serial.println("mkdir failed");
+  }
+}
+
+void removeDir(fs::FS &fs, const char *path) {
+  Serial.printf("Removing Dir: %s\n", path);
+  if (fs.rmdir(path)) {
+    Serial.println("Dir removed");
+  } else {
+    Serial.println("rmdir failed");
+  }
+}
+
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\r\n", path);
+
+  File file = fs.open(path);
+  if (!file || file.isDirectory()) {
+    Serial.println("- failed to open file for reading");
+    return;
+  }
+
+  Serial.println("- read from file:");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
+  file.close();
+}
+
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\r\n", path);
+
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("- failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("- file written");
+  } else {
+    Serial.println("- write failed");
+  }
+  file.close();
+}
+
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\r\n", path);
+
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("- failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("- message appended");
+  } else {
+    Serial.println("- append failed");
+  }
+  file.close();
+}
+
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\r\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("- file renamed");
+  } else {
+    Serial.println("- rename failed");
+  }
+}
+
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\r\n", path);
+  if (fs.remove(path)) {
+    Serial.println("- file deleted");
+  } else {
+    Serial.println("- delete failed");
+  }
+}
+
+// SPIFFS-like write and delete file, better use #define CONFIG_LITTLEFS_SPIFFS_COMPAT 1
+
+void writeFile2(fs::FS &fs, const char *path, const char *message) {
+  if (!fs.exists(path)) {
+    if (strchr(path, '/')) {
+      Serial.printf("Create missing folders of: %s\r\n", path);
+      char *pathStr = strdup(path);
+      if (pathStr) {
+        char *ptr = strchr(pathStr, '/');
+        while (ptr) {
+          *ptr = 0;
+          fs.mkdir(pathStr);
+          *ptr = '/';
+          ptr = strchr(ptr + 1, '/');
+        }
+      }
+      free(pathStr);
+    }
+  }
+
+  Serial.printf("Writing file to: %s\r\n", path);
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("- failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("- file written");
+  } else {
+    Serial.println("- write failed");
+  }
+  file.close();
+}
+
+void deleteFile2(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file and empty folders on path: %s\r\n", path);
+
+  if (fs.remove(path)) {
+    Serial.println("- file deleted");
+  } else {
+    Serial.println("- delete failed");
+  }
+
+  char *pathStr = strdup(path);
+  if (pathStr) {
+    char *ptr = strrchr(pathStr, '/');
+    if (ptr) {
+      Serial.printf("Removing all empty folders on path: %s\r\n", path);
+    }
+    while (ptr) {
+      *ptr = 0;
+      fs.rmdir(pathStr);
+      ptr = strrchr(pathStr, '/');
+    }
+    free(pathStr);
+  }
+}
+
+void testFileIO(fs::FS &fs, const char *path) {
+  Serial.printf("Testing file I/O with %s\r\n", path);
+
+  static uint8_t buf[512];
+  size_t len = 0;
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("- failed to open file for writing");
+    return;
+  }
+
+  size_t i;
+  Serial.print("- writing");
+  uint32_t start = millis();
+  for (i = 0; i < 2048; i++) {
+    if ((i & 0x001F) == 0x001F) {
+      Serial.print(".");
+    }
+    file.write(buf, 512);
+  }
+  Serial.println("");
+  uint32_t end = millis() - start;
+  Serial.printf(" - %u bytes written in %lu ms\r\n", 2048 * 512, end);
+  file.close();
+
+  file = fs.open(path);
+  start = millis();
+  end = start;
+  i = 0;
+  if (file && !file.isDirectory()) {
+    len = file.size();
+    size_t flen = len;
+    start = millis();
+    Serial.print("- reading");
+    while (len) {
+      size_t toRead = len;
+      if (toRead > 512) {
+        toRead = 512;
+      }
+      file.read(buf, toRead);
+      if ((i++ & 0x001F) == 0x001F) {
+        Serial.print(".");
+      }
+      len -= toRead;
+    }
+    Serial.println("");
+    end = millis() - start;
+    Serial.printf("- %u bytes read in %lu ms\r\n", flen, end);
+    file.close();
+  } else {
+    Serial.println("- failed to open file for reading");
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+
+#ifdef TWOPART
+  if (!LittleFS.begin(FORMAT_LITTLEFS_IF_FAILED, "/lfs2", 5, "part2")) {
+    Serial.println("part2 Mount Failed");
+    return;
+  }
+  appendFile(LittleFS, "/hello0.txt", "World0!\r\n");
+  readFile(LittleFS, "/hello0.txt");
+  LittleFS.end();
+
+  Serial.println("Done with part2, work with the first lfs partition...");
+#endif
+
+  if (!LittleFS.begin(FORMAT_LITTLEFS_IF_FAILED)) {
+    Serial.println("LittleFS Mount Failed");
+    return;
+  }
+  Serial.println("SPIFFS-like write file to new path and delete it w/folders");
+  writeFile2(LittleFS, "/new1/new2/new3/hello3.txt", "Hello3");
+  listDir(LittleFS, "/", 3);
+  deleteFile2(LittleFS, "/new1/new2/new3/hello3.txt");
+
+  listDir(LittleFS, "/", 3);
+  createDir(LittleFS, "/mydir");
+  writeFile(LittleFS, "/mydir/hello2.txt", "Hello2");
+  listDir(LittleFS, "/", 1);
+  deleteFile(LittleFS, "/mydir/hello2.txt");
+  removeDir(LittleFS, "/mydir");
+  listDir(LittleFS, "/", 1);
+  writeFile(LittleFS, "/hello.txt", "Hello ");
+  appendFile(LittleFS, "/hello.txt", "World!\r\n");
+  readFile(LittleFS, "/hello.txt");
+  renameFile(LittleFS, "/hello.txt", "/foo.txt");
+  readFile(LittleFS, "/foo.txt");
+  deleteFile(LittleFS, "/foo.txt");
+  testFileIO(LittleFS, "/test.txt");
+  deleteFile(LittleFS, "/test.txt");
+
+  Serial.println("Test complete");
+}
+
+void loop() {}
diff --git a/libraries/LittleFS/examples/LITTLEFS_test/partitions.csv b/libraries/LittleFS/examples/LITTLEFS_test/partitions.csv
new file mode 100644
index 00000000000..04f4a78a11f
--- /dev/null
+++ b/libraries/LittleFS/examples/LITTLEFS_test/partitions.csv
@@ -0,0 +1,8 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0x100000,
+app1,     app,  ota_1,           ,0x100000,
+spiffs,   data, spiffs,          ,0x1D0000,
+part2,    data, spiffs,          ,0x20000,
+#1048576
diff --git a/libraries/LittleFS/examples/LITTLEFS_time/LITTLEFS_time.ino b/libraries/LittleFS/examples/LITTLEFS_time/LITTLEFS_time.ino
new file mode 100644
index 00000000000..f169ac24954
--- /dev/null
+++ b/libraries/LittleFS/examples/LITTLEFS_time/LITTLEFS_time.ino
@@ -0,0 +1,220 @@
+#include "FS.h"
+//#include "SPIFFS.h"
+#include "LittleFS.h"
+#include <time.h>
+#include <WiFi.h>
+
+#define SPIFFS LittleFS
+
+/* This examples uses "quick re-define" of SPIFFS to run
+   an existing sketch with LittleFS instead of SPIFFS
+
+   You only need to format LittleFS the first time you run a
+   test or else use the LittleFS plugin to create a partition
+   https://github.com/lorol/arduino-esp32littlefs-plugin */
+
+#define FORMAT_LITTLEFS_IF_FAILED true
+
+const char *ssid = "yourssid";
+const char *password = "yourpass";
+
+long timezone = 1;
+byte daysavetime = 1;
+
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\n", dirname);
+
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("Failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println("Not a directory");
+    return;
+  }
+
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.print(file.name());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
+    } else {
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("  SIZE: ");
+      Serial.print(file.size());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
+    }
+    file = root.openNextFile();
+  }
+}
+
+void createDir(fs::FS &fs, const char *path) {
+  Serial.printf("Creating Dir: %s\n", path);
+  if (fs.mkdir(path)) {
+    Serial.println("Dir created");
+  } else {
+    Serial.println("mkdir failed");
+  }
+}
+
+void removeDir(fs::FS &fs, const char *path) {
+  Serial.printf("Removing Dir: %s\n", path);
+  if (fs.rmdir(path)) {
+    Serial.println("Dir removed");
+  } else {
+    Serial.println("rmdir failed");
+  }
+}
+
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\n", path);
+
+  File file = fs.open(path);
+  if (!file) {
+    Serial.println("Failed to open file for reading");
+    return;
+  }
+
+  Serial.print("Read from file: ");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
+  file.close();
+}
+
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\n", path);
+
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("File written");
+  } else {
+    Serial.println("Write failed");
+  }
+  file.close();
+}
+
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\n", path);
+
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("Failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("Message appended");
+  } else {
+    Serial.println("Append failed");
+  }
+  file.close();
+}
+
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("File renamed");
+  } else {
+    Serial.println("Rename failed");
+  }
+}
+
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\n", path);
+  if (fs.remove(path)) {
+    Serial.println("File deleted");
+  } else {
+    Serial.println("Delete failed");
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  // We start by connecting to a WiFi network
+  Serial.println();
+  Serial.println();
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+
+  WiFi.begin(ssid, password);
+
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  Serial.println("Contacting Time Server");
+  configTime(3600 * timezone, daysavetime * 3600, "time.nist.gov", "0.pool.ntp.org", "1.pool.ntp.org");
+  struct tm tmstruct;
+  delay(2000);
+  tmstruct.tm_year = 0;
+  getLocalTime(&tmstruct, 5000);
+  Serial.printf(
+    "\nNow is : %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct.tm_year) + 1900, (tmstruct.tm_mon) + 1, tmstruct.tm_mday, tmstruct.tm_hour, tmstruct.tm_min,
+    tmstruct.tm_sec
+  );
+  Serial.println("");
+
+  if (!SPIFFS.begin(FORMAT_LITTLEFS_IF_FAILED)) {
+    Serial.println("LittleFS Mount Failed");
+    return;
+  }
+
+  Serial.println("----list 1----");
+  listDir(SPIFFS, "/", 1);
+
+  Serial.println("----remove old dir----");
+  removeDir(SPIFFS, "/mydir");
+
+  Serial.println("----create a new dir----");
+  createDir(SPIFFS, "/mydir");
+
+  Serial.println("----remove the new dir----");
+  removeDir(SPIFFS, "/mydir");
+
+  Serial.println("----create the new again----");
+  createDir(SPIFFS, "/mydir");
+
+  Serial.println("----create and work with file----");
+  writeFile(SPIFFS, "/mydir/hello.txt", "Hello ");
+  appendFile(SPIFFS, "/mydir/hello.txt", "World!\n");
+
+  Serial.println("----list 2----");
+  listDir(SPIFFS, "/", 1);
+
+  Serial.println("----attempt to remove dir w/ file----");
+  removeDir(SPIFFS, "/mydir");
+
+  Serial.println("----remove dir after deleting file----");
+  deleteFile(SPIFFS, "/mydir/hello.txt");
+  removeDir(SPIFFS, "/mydir");
+
+  Serial.println("----list 3----");
+  listDir(SPIFFS, "/", 1);
+
+  Serial.println("Test complete");
+}
+
+void loop() {}
diff --git a/libraries/LittleFS/examples/LITTLEFS_time/ci.json b/libraries/LittleFS/examples/LITTLEFS_time/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/LittleFS/examples/LITTLEFS_time/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/LittleFS/library.properties b/libraries/LittleFS/library.properties
new file mode 100644
index 00000000000..a9dae69b7f8
--- /dev/null
+++ b/libraries/LittleFS/library.properties
@@ -0,0 +1,9 @@
+name=LittleFS
+version=3.2.0
+author=
+maintainer=
+sentence=LittleFS for esp32
+paragraph=LittleFS for esp32
+category=Data Storage
+url=
+architectures=esp32
diff --git a/libraries/LittleFS/src/LittleFS.cpp b/libraries/LittleFS/src/LittleFS.cpp
new file mode 100644
index 00000000000..761d1ba4c24
--- /dev/null
+++ b/libraries/LittleFS/src/LittleFS.cpp
@@ -0,0 +1,127 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "LittleFS.h"
+
+#ifdef CONFIG_LITTLEFS_PAGE_SIZE
+#include "vfs_api.h"
+
+extern "C" {
+#include <sys/unistd.h>
+#include <sys/stat.h>
+#include <dirent.h>
+#include "esp_littlefs.h"
+}
+
+using namespace fs;
+
+class LittleFSImpl : public VFSImpl {
+public:
+  LittleFSImpl();
+  virtual ~LittleFSImpl() {}
+};
+
+LittleFSImpl::LittleFSImpl() {}
+
+LittleFSFS::LittleFSFS() : FS(FSImplPtr(new LittleFSImpl())), partitionLabel_(NULL) {}
+
+LittleFSFS::~LittleFSFS() {
+  if (partitionLabel_) {
+    free(partitionLabel_);
+    partitionLabel_ = NULL;
+  }
+}
+
+bool LittleFSFS::begin(bool formatOnFail, const char *basePath, uint8_t maxOpenFiles, const char *partitionLabel) {
+
+  if (partitionLabel_) {
+    free(partitionLabel_);
+    partitionLabel_ = NULL;
+  }
+
+  if (partitionLabel) {
+    partitionLabel_ = strdup(partitionLabel);
+  }
+
+  if (esp_littlefs_mounted(partitionLabel_)) {
+    log_w("LittleFS Already Mounted!");
+    return true;
+  }
+
+  esp_vfs_littlefs_conf_t conf = {
+    .base_path = basePath,
+    .partition_label = partitionLabel_,
+    .partition = NULL,
+    .format_if_mount_failed = false,
+    .read_only = false,
+    .dont_mount = false,
+    .grow_on_mount = true
+  };
+
+  esp_err_t err = esp_vfs_littlefs_register(&conf);
+  if (err == ESP_FAIL && formatOnFail) {
+    if (format()) {
+      err = esp_vfs_littlefs_register(&conf);
+    }
+  }
+  if (err != ESP_OK) {
+    log_e("Mounting LittleFS failed! Error: %d", err);
+    return false;
+  }
+  _impl->mountpoint(basePath);
+  return true;
+}
+
+void LittleFSFS::end() {
+  if (esp_littlefs_mounted(partitionLabel_)) {
+    esp_err_t err = esp_vfs_littlefs_unregister(partitionLabel_);
+    if (err) {
+      log_e("Unmounting LittleFS failed! Error: %d", err);
+      return;
+    }
+    _impl->mountpoint(NULL);
+  }
+}
+
+bool LittleFSFS::format() {
+  bool wdt_active = disableCore0WDT();
+  esp_err_t err = esp_littlefs_format(partitionLabel_);
+  if (wdt_active) {
+    enableCore0WDT();
+  }
+  if (err) {
+    log_e("Formatting LittleFS failed! Error: %d", err);
+    return false;
+  }
+  return true;
+}
+
+size_t LittleFSFS::totalBytes() {
+  size_t total, used;
+  if (esp_littlefs_info(partitionLabel_, &total, &used)) {
+    return 0;
+  }
+  return total;
+}
+
+size_t LittleFSFS::usedBytes() {
+  size_t total, used;
+  if (esp_littlefs_info(partitionLabel_, &total, &used)) {
+    return 0;
+  }
+  return used;
+}
+
+LittleFSFS LittleFS;
+#endif /* CONFIG_LITTLEFS_PAGE_SIZE */
diff --git a/libraries/LittleFS/src/LittleFS.h b/libraries/LittleFS/src/LittleFS.h
new file mode 100644
index 00000000000..da4ab7d1f6f
--- /dev/null
+++ b/libraries/LittleFS/src/LittleFS.h
@@ -0,0 +1,44 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _LITTLEFS_H_
+#define _LITTLEFS_H_
+
+#include "sdkconfig.h"
+
+#ifdef CONFIG_LITTLEFS_PAGE_SIZE
+
+#include "FS.h"
+
+namespace fs {
+
+class LittleFSFS : public FS {
+public:
+  LittleFSFS();
+  ~LittleFSFS();
+  bool begin(bool formatOnFail = false, const char *basePath = "/littlefs", uint8_t maxOpenFiles = 10, const char *partitionLabel = "spiffs");
+  bool format();
+  size_t totalBytes();
+  size_t usedBytes();
+  void end();
+
+private:
+  char *partitionLabel_;
+};
+
+}  // namespace fs
+
+extern fs::LittleFSFS LittleFS;
+
+#endif /* CONFIG_LITTLEFS_PAGE_SIZE */
+#endif
diff --git a/libraries/Matter/examples/MatterColorLight/MatterColorLight.ino b/libraries/Matter/examples/MatterColorLight/MatterColorLight.ino
new file mode 100644
index 00000000000..f3e45887576
--- /dev/null
+++ b/libraries/Matter/examples/MatterColorLight/MatterColorLight.ino
@@ -0,0 +1,184 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+#include <Preferences.h>
+
+// List of Matter Endpoints for this Node
+// Color Light Endpoint
+MatterColorLight ColorLight;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// it will keep last OnOff & HSV Color state stored, using Preferences
+Preferences matterPref;
+const char *onOffPrefKey = "OnOff";
+const char *hsvColorPrefKey = "HSV";
+
+// set your board RGB LED pin here
+#ifdef RGB_BUILTIN
+const uint8_t ledPin = RGB_BUILTIN;
+#else
+const uint8_t ledPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#warning "Do not forget to set the RGB LED pin"
+#endif
+
+// set your board USER BUTTON pin here
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t debouceTime = 250;              // button debouncing time (ms)
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Set the RGB LED Light based on the current state of the Color Light
+bool setLightState(bool state, espHsvColor_t colorHSV) {
+
+  if (state) {
+#ifdef RGB_BUILTIN
+    espRgbColor_t rgbColor = espHsvColorToRgbColor(colorHSV);
+    // set the RGB LED
+    rgbLedWrite(ledPin, rgbColor.r, rgbColor.g, rgbColor.b);
+#else
+    // No Color RGB LED, just use the HSV value (brightness) to control the LED
+    analogWrite(ledPin, colorHSV.v);
+#endif
+  } else {
+#ifndef RGB_BUILTIN
+    // after analogWrite(), it is necessary to set the GPIO to digital mode first
+    pinMode(ledPin, OUTPUT);
+#endif
+    digitalWrite(ledPin, LOW);
+  }
+  // store last HSV Color and OnOff state for when the Light is restarted / power goes off
+  matterPref.putBool(onOffPrefKey, state);
+  matterPref.putUInt(hsvColorPrefKey, colorHSV.h << 16 | colorHSV.s << 8 | colorHSV.v);
+  // This callback must return the success state to Matter core
+  return true;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) GPIO that will act as a toggle switch
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the LED (light) GPIO and Matter End Point
+  pinMode(ledPin, OUTPUT);
+
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("\r\nWiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // Initialize Matter EndPoint
+  matterPref.begin("MatterPrefs", false);
+  // default OnOff state is ON if not stored before
+  bool lastOnOffState = matterPref.getBool(onOffPrefKey, true);
+  // default HSV color is blue HSV(169, 254, 254)
+  uint32_t prefHsvColor = matterPref.getUInt(hsvColorPrefKey, 169 << 16 | 254 << 8 | 254);
+  espHsvColor_t lastHsvColor = {uint8_t(prefHsvColor >> 16), uint8_t(prefHsvColor >> 8), uint8_t(prefHsvColor)};
+  ColorLight.begin(lastOnOffState, lastHsvColor);
+  // set the callback function to handle the Light state change
+  ColorLight.onChange(setLightState);
+
+  // lambda functions are used to set the attribute change callbacks
+  ColorLight.onChangeOnOff([](bool state) {
+    Serial.printf("Light OnOff changed to %s\r\n", state ? "ON" : "OFF");
+    return true;
+  });
+  ColorLight.onChangeColorHSV([](HsvColor_t hsvColor) {
+    Serial.printf("Light HSV Color changed to (%d,%d,%d)\r\n", hsvColor.h, hsvColor.s, hsvColor.v);
+    return true;
+  });
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+  // This may be a restart of a already commissioned Matter accessory
+  if (Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+    Serial.printf(
+      "Initial state: %s | RGB Color: (%d,%d,%d) \r\n", ColorLight ? "ON" : "OFF", ColorLight.getColorRGB().r, ColorLight.getColorRGB().g,
+      ColorLight.getColorRGB().b
+    );
+    // configure the Light based on initial on-off state and its color
+    ColorLight.updateAccessory();
+  }
+}
+
+void loop() {
+  // Check Matter Light Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Light Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.printf(
+      "Initial state: %s | RGB Color: (%d,%d,%d) \r\n", ColorLight ? "ON" : "OFF", ColorLight.getColorRGB().r, ColorLight.getColorRGB().g,
+      ColorLight.getColorRGB().b
+    );
+    // configure the Light based on initial on-off state and its color
+    ColorLight.updateAccessory();
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+
+  // A button is also used to control the light
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  // Onboard User Button is used as a Light toggle switch or to decommission it
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (digitalRead(buttonPin) == HIGH && button_state && time_diff > debouceTime) {
+    // Toggle button is released - toggle the light
+    Serial.println("User button released. Toggling Light!");
+    ColorLight.toggle();   // Matter Controller also can see the change
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Light Matter Accessory. It shall be commissioned again.");
+    ColorLight = false;  // turn the light off
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+}
diff --git a/libraries/Matter/examples/MatterColorLight/ci.json b/libraries/Matter/examples/MatterColorLight/ci.json
new file mode 100644
index 00000000000..d5f63487506
--- /dev/null
+++ b/libraries/Matter/examples/MatterColorLight/ci.json
@@ -0,0 +1,7 @@
+{
+    "fqbn_append": "PartitionScheme=huge_app",
+    "requires": [
+      "CONFIG_SOC_WIFI_SUPPORTED=y",
+      "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+    ]
+  }
diff --git a/libraries/Matter/examples/MatterCommissionTest/MatterCommissionTest.ino b/libraries/Matter/examples/MatterCommissionTest/MatterCommissionTest.ino
new file mode 100644
index 00000000000..0e93ed6d155
--- /dev/null
+++ b/libraries/Matter/examples/MatterCommissionTest/MatterCommissionTest.ino
@@ -0,0 +1,72 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// On/Off Light Endpoint
+MatterOnOffLight OnOffLight;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+void setup() {
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("\r\nWiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // Initialize at least one Matter EndPoint
+  OnOffLight.begin();
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+}
+
+void loop() {
+  // Check Matter Commissioning state
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Light Commissioning.
+    while (!Matter.isDeviceCommissioned()) {
+      delay(5000);
+      Serial.println("Matter Fabric not commissioned yet. Waiting for commissioning.");
+    }
+  }
+  Serial.println("Matter Node is commissioned and connected to Wi-Fi.");
+  Serial.println("====> Decommissioning in 30 seconds. <====");
+  delay(30000);
+  Matter.decommission();
+  Serial.println("Matter Node is decommissioned. Commsssioning widget shall start over.");
+}
diff --git a/libraries/Matter/examples/MatterCommissionTest/ci.json b/libraries/Matter/examples/MatterCommissionTest/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterCommissionTest/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterComposedLights/MatterComposedLights.ino b/libraries/Matter/examples/MatterComposedLights/MatterComposedLights.ino
new file mode 100644
index 00000000000..b98cc8e19c9
--- /dev/null
+++ b/libraries/Matter/examples/MatterComposedLights/MatterComposedLights.ino
@@ -0,0 +1,137 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// There will be 3 On/Off Light Endpoints in the same Node
+MatterOnOffLight Light1;
+MatterDimmableLight Light2;
+MatterColorLight Light3;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// set your board USER BUTTON pin here -  USED to decommission the Matter Node
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Matter Protocol Endpoint Callback for each Light Accessory
+bool setLightOnOff1(bool state) {
+  Serial.printf("Light1 changed state to: %s\r\n", state ? "ON" : "OFF");
+  return true;
+}
+
+bool setLightOnOff2(bool state) {
+  Serial.printf("Light2 changed state to: %s\r\n", state ? "ON" : "OFF");
+  return true;
+}
+
+bool setLightOnOff3(bool state) {
+  Serial.printf("Light3 changed state to: %s\r\n", state ? "ON" : "OFF");
+  return true;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println();
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // Initialize all 3 Matter EndPoints
+  Light1.begin();
+  Light2.begin();
+  Light3.begin();
+  Light1.onChangeOnOff(setLightOnOff1);
+  Light2.onChangeOnOff(setLightOnOff2);
+  Light3.onChangeOnOff(setLightOnOff3);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+}
+
+void loop() {
+  static uint32_t timeCounter = 0;
+
+  // Check Matter Light Commissioning state
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Light Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+
+  //displays the Light state every 5 seconds
+  if (!(timeCounter++ % 10)) {  // delaying for 500ms x 10 = 5s
+    Serial.println("======================");
+    Serial.printf("Matter Light #1 is %s\r\n", Light1.getOnOff() ? "ON" : "OFF");
+    Serial.printf("Matter Light #2 is %s\r\n", Light2.getOnOff() ? "ON" : "OFF");
+    Serial.printf("Matter Light #3 is %s\r\n", Light3.getOnOff() ? "ON" : "OFF");
+  }
+
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  if (digitalRead(buttonPin) == HIGH && button_state) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Composed Light Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+
+  delay(500);
+}
diff --git a/libraries/Matter/examples/MatterComposedLights/ci.json b/libraries/Matter/examples/MatterComposedLights/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterComposedLights/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterContactSensor/MatterContactSensor.ino b/libraries/Matter/examples/MatterContactSensor/MatterContactSensor.ino
new file mode 100644
index 00000000000..e4c41460d3a
--- /dev/null
+++ b/libraries/Matter/examples/MatterContactSensor/MatterContactSensor.ino
@@ -0,0 +1,152 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * This example is an example code that will create a Matter Device which can be
+ * commissioned and controlled from a Matter Environment APP.
+ * Additionally the ESP32 will send debug messages indicating the Matter activity.
+ * Turning DEBUG Level ON may be useful to following Matter Accessory and Controller messages.
+ *
+ * The example will create a Matter Contact Sensor Device.
+ * The Contact Sensor state can be toggled by pressing the onboard button.
+ * The Contact Sensor state will be indicated by the onboard LED.
+ * The Contact Sensor state will be simulated to change every 20 seconds.
+ *
+ * The onboard button can be kept pressed for 5 seconds to decommission the Matter Node.
+ * The example will also show the manual commissioning code and QR code to be used in the Matter environment.
+ *
+ */
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Matter Contact Sensor Endpoint
+MatterContactSensor ContactSensor;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// LED will be used to indicate the Contact Sensor state
+// set your board RGB LED pin here
+#ifdef RGB_BUILTIN
+const uint8_t ledPin = RGB_BUILTIN;
+#else
+const uint8_t ledPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#warning "Do not forget to set the RGB LED pin"
+#endif
+
+// set your board USER BUTTON pin here - decommissioning and Manual Contact Sensor toggle button
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t debouceTime = 250;              // button debouncing time (ms)
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  // The button will also be used to manually toggle the Contact Sensor state
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the LED (light) GPIO and Matter End Point
+  pinMode(ledPin, OUTPUT);
+
+  Serial.begin(115200);
+
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println();
+
+  // set initial contact sensor state as false (default)
+  ContactSensor.begin();
+  digitalWrite(ledPin, LOW);  // LED OFF
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+
+  // Check Matter Accessory Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Contact Sensor Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+}
+
+bool simulatedHWContactSensor() {
+  // Simulated Contact Sensor
+  static bool contactState = false;
+  static uint32_t lastTime = 0;
+
+  // Simulate a Contact Sensor state change every 20 seconds
+  if (millis() - lastTime > 20000) {
+    contactState = !contactState;
+    lastTime = millis();
+  }
+  return contactState;
+}
+
+void loop() {
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > debouceTime && digitalRead(buttonPin) == HIGH) {
+    button_state = false;  // released
+    // button is released - toggle Contact State (Open/Closed)
+    ContactSensor.setContact(!ContactSensor.getContact());  // same as ContactSensor = !ContactSensor;
+    Serial.printf("User button released. Setting the Contact Sensor to %s.\r\n", ContactSensor ? "Closed" : "Open");
+    // LED will indicate the Contact Sensor state
+    if (ContactSensor) {
+      digitalWrite(ledPin, HIGH);  // LED ON
+    } else {
+      digitalWrite(ledPin, LOW);  // LED OFF
+    }
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning Contact Sensor Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+
+  // Simulated Contact Sensor
+  ContactSensor.setContact(simulatedHWContactSensor());
+
+  delay(50);
+}
diff --git a/libraries/Matter/examples/MatterContactSensor/ci.json b/libraries/Matter/examples/MatterContactSensor/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterContactSensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterDimmableLight/MatterDimmableLight.ino b/libraries/Matter/examples/MatterDimmableLight/MatterDimmableLight.ino
new file mode 100644
index 00000000000..79751905c20
--- /dev/null
+++ b/libraries/Matter/examples/MatterDimmableLight/MatterDimmableLight.ino
@@ -0,0 +1,173 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+#include <Preferences.h>
+
+// List of Matter Endpoints for this Node
+// Dimmable Light Endpoint
+MatterDimmableLight DimmableLight;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// it will keep last OnOff & Brightness state stored, using Preferences
+Preferences matterPref;
+const char *onOffPrefKey = "OnOff";
+const char *brightnessPrefKey = "Brightness";
+
+// set your board RGB LED pin here
+#ifdef RGB_BUILTIN
+const uint8_t ledPin = RGB_BUILTIN;
+#else
+const uint8_t ledPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#warning "Do not forget to set the RGB LED pin"
+#endif
+
+// set your board USER BUTTON pin here
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t debouceTime = 250;              // button debouncing time (ms)
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Set the RGB LED Light based on the current state of the Dimmable Light
+bool setLightState(bool state, uint8_t brightness) {
+  if (state) {
+#ifdef RGB_BUILTIN
+    rgbLedWrite(ledPin, brightness, brightness, brightness);
+#else
+    analogWrite(ledPin, brightness);
+#endif
+  } else {
+#ifndef RGB_BUILTIN
+    // after analogWrite(), it is necessary to set the GPIO to digital mode first
+    pinMode(ledPin, OUTPUT);
+#endif
+    digitalWrite(ledPin, LOW);
+  }
+  // store last Brightness and OnOff state for when the Light is restarted / power goes off
+  matterPref.putUChar(brightnessPrefKey, brightness);
+  matterPref.putBool(onOffPrefKey, state);
+  // This callback must return the success state to Matter core
+  return true;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) GPIO that will act as a toggle switch
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the LED (light) GPIO and Matter End Point
+  pinMode(ledPin, OUTPUT);
+
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("\r\nWiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // Initialize Matter EndPoint
+  matterPref.begin("MatterPrefs", false);
+  // default OnOff state is ON if not stored before
+  bool lastOnOffState = matterPref.getBool(onOffPrefKey, true);
+  // default brightness ~= 6% (15/255)
+  uint8_t lastBrightness = matterPref.getUChar(brightnessPrefKey, 15);
+  DimmableLight.begin(lastOnOffState, lastBrightness);
+  // set the callback function to handle the Light state change
+  DimmableLight.onChange(setLightState);
+
+  // lambda functions are used to set the attribute change callbacks
+  DimmableLight.onChangeOnOff([](bool state) {
+    Serial.printf("Light OnOff changed to %s\r\n", state ? "ON" : "OFF");
+    return true;
+  });
+  DimmableLight.onChangeBrightness([](uint8_t level) {
+    Serial.printf("Light Brightness changed to %d\r\n", level);
+    return true;
+  });
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+  // This may be a restart of a already commissioned Matter accessory
+  if (Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+    Serial.printf("Initial state: %s | brightness: %d\r\n", DimmableLight ? "ON" : "OFF", DimmableLight.getBrightness());
+    // configure the Light based on initial on-off state and brightness
+    DimmableLight.updateAccessory();
+  }
+}
+
+void loop() {
+  // Check Matter Light Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Light Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.printf("Initial state: %s | brightness: %d\r\n", DimmableLight ? "ON" : "OFF", DimmableLight.getBrightness());
+    // configure the Light based on initial on-off state and brightness
+    DimmableLight.updateAccessory();
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+
+  // A button is also used to control the light
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  // Onboard User Button is used as a Light toggle switch or to decommission it
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (digitalRead(buttonPin) == HIGH && button_state && time_diff > debouceTime) {
+    // Toggle button is released - toggle the light
+    Serial.println("User button released. Toggling Light!");
+    DimmableLight.toggle();  // Matter Controller also can see the change
+    button_state = false;    // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Light Matter Accessory. It shall be commissioned again.");
+    DimmableLight = false;  // turn the light off
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+}
diff --git a/libraries/Matter/examples/MatterDimmableLight/ci.json b/libraries/Matter/examples/MatterDimmableLight/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterDimmableLight/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterEnhancedColorLight/MatterEnhancedColorLight.ino b/libraries/Matter/examples/MatterEnhancedColorLight/MatterEnhancedColorLight.ino
new file mode 100644
index 00000000000..8e12581fdf2
--- /dev/null
+++ b/libraries/Matter/examples/MatterEnhancedColorLight/MatterEnhancedColorLight.ino
@@ -0,0 +1,206 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+#include <Preferences.h>
+
+// List of Matter Endpoints for this Node
+// Color Light Endpoint
+MatterEnhancedColorLight EnhancedColorLight;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// It will use HSV color to control all Matter Attribute Changes
+HsvColor_t currentHSVColor = {0, 0, 0};
+
+// it will keep last OnOff & HSV Color state stored, using Preferences
+Preferences matterPref;
+const char *onOffPrefKey = "OnOff";
+const char *hsvColorPrefKey = "HSV";
+
+// set your board RGB LED pin here
+#ifdef RGB_BUILTIN
+const uint8_t ledPin = RGB_BUILTIN;
+#else
+const uint8_t ledPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#warning "Do not forget to set the RGB LED pin"
+#endif
+
+// set your board USER BUTTON pin here
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t debouceTime = 250;              // button debouncing time (ms)
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Set the RGB LED Light based on the current state of the Enhanced Color Light
+bool setLightState(bool state, espHsvColor_t colorHSV, uint8_t brighteness, uint16_t temperature_Mireds) {
+
+  if (state) {
+#ifdef RGB_BUILTIN
+    // currentHSVColor keeps final color result
+    espRgbColor_t rgbColor = espHsvColorToRgbColor(currentHSVColor);
+    // set the RGB LED
+    rgbLedWrite(ledPin, rgbColor.r, rgbColor.g, rgbColor.b);
+#else
+    // No Color RGB LED, just use the HSV value (brightness) to control the LED
+    analogWrite(ledPin, colorHSV.v);
+#endif
+  } else {
+#ifndef RGB_BUILTIN
+    // after analogWrite(), it is necessary to set the GPIO to digital mode first
+    pinMode(ledPin, OUTPUT);
+#endif
+    digitalWrite(ledPin, LOW);
+  }
+  // store last HSV Color and OnOff state for when the Light is restarted / power goes off
+  matterPref.putBool(onOffPrefKey, state);
+  matterPref.putUInt(hsvColorPrefKey, currentHSVColor.h << 16 | currentHSVColor.s << 8 | currentHSVColor.v);
+  // This callback must return the success state to Matter core
+  return true;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) GPIO that will act as a toggle switch
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the LED (light) GPIO and Matter End Point
+  pinMode(ledPin, OUTPUT);
+
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("\r\nWiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // Initialize Matter EndPoint
+  matterPref.begin("MatterPrefs", false);
+  // default OnOff state is ON if not stored before
+  bool lastOnOffState = matterPref.getBool(onOffPrefKey, true);
+  // default HSV color is (21, 216, 25) - Warm White Color at 10% intensity
+  uint32_t prefHsvColor = matterPref.getUInt(hsvColorPrefKey, 21 << 16 | 216 << 8 | 25);
+  currentHSVColor = {uint8_t(prefHsvColor >> 16), uint8_t(prefHsvColor >> 8), uint8_t(prefHsvColor)};
+  EnhancedColorLight.begin(lastOnOffState, currentHSVColor);
+  // set the callback function to handle the Light state change
+  EnhancedColorLight.onChange(setLightState);
+
+  // lambda functions are used to set the attribute change callbacks
+  EnhancedColorLight.onChangeOnOff([](bool state) {
+    Serial.printf("Light OnOff changed to %s\r\n", state ? "ON" : "OFF");
+    return true;
+  });
+  EnhancedColorLight.onChangeColorTemperature([](uint16_t colorTemperature) {
+    Serial.printf("Light Color Temperature changed to %d\r\n", colorTemperature);
+    // get correspondent Hue and Saturation of the color temperature
+    HsvColor_t hsvTemperature = espRgbColorToHsvColor(espCTToRgbColor(colorTemperature));
+    // keep previous the brightness and just change the Hue and Saturation
+    currentHSVColor.h = hsvTemperature.h;
+    currentHSVColor.s = hsvTemperature.s;
+    return true;
+  });
+  EnhancedColorLight.onChangeBrightness([](uint8_t brightness) {
+    Serial.printf("Light brightness changed to %d\r\n", brightness);
+    // change current brightness (HSV value)
+    currentHSVColor.v = brightness;
+    return true;
+  });
+  EnhancedColorLight.onChangeColorHSV([](HsvColor_t hsvColor) {
+    Serial.printf("Light HSV Color changed to (%d,%d,%d)\r\n", hsvColor.h, hsvColor.s, hsvColor.v);
+    // keep the current brightness and just change Hue and Saturation
+    currentHSVColor.h = hsvColor.h;
+    currentHSVColor.s = hsvColor.s;
+    return true;
+  });
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+  // This may be a restart of a already commissioned Matter accessory
+  if (Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+    Serial.printf(
+      "Initial state: %s | RGB Color: (%d,%d,%d) \r\n", EnhancedColorLight ? "ON" : "OFF", EnhancedColorLight.getColorRGB().r,
+      EnhancedColorLight.getColorRGB().g, EnhancedColorLight.getColorRGB().b
+    );
+    // configure the Light based on initial on-off state and its color
+    EnhancedColorLight.updateAccessory();
+  }
+}
+
+void loop() {
+  // Check Matter Light Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Light Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.printf(
+      "Initial state: %s | RGB Color: (%d,%d,%d) \r\n", EnhancedColorLight ? "ON" : "OFF", EnhancedColorLight.getColorRGB().r,
+      EnhancedColorLight.getColorRGB().g, EnhancedColorLight.getColorRGB().b
+    );
+    // configure the Light based on initial on-off state and its color
+    EnhancedColorLight.updateAccessory();
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+
+  // A button is also used to control the light
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  // Onboard User Button is used as a Light toggle switch or to decommission it
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > debouceTime && digitalRead(buttonPin) == HIGH) {
+    button_state = false;  // released
+    // Toggle button is released - toggle the light
+    Serial.println("User button released. Toggling Light!");
+    EnhancedColorLight.toggle();  // Matter Controller also can see the change
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Light Matter Accessory. It shall be commissioned again.");
+    EnhancedColorLight = false;  // turn the light off
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+}
diff --git a/libraries/Matter/examples/MatterEnhancedColorLight/ci.json b/libraries/Matter/examples/MatterEnhancedColorLight/ci.json
new file mode 100644
index 00000000000..0665800b12b
--- /dev/null
+++ b/libraries/Matter/examples/MatterEnhancedColorLight/ci.json
@@ -0,0 +1,7 @@
+{
+    "fqbn_append": "PartitionScheme=huge_app",
+    "requires": [
+      "CONFIG_SOC_WIFI_SUPPORTED=y",
+      "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+    ]
+}
diff --git a/libraries/Matter/examples/MatterFan/MatterFan.ino b/libraries/Matter/examples/MatterFan/MatterFan.ino
new file mode 100644
index 00000000000..705aa4853da
--- /dev/null
+++ b/libraries/Matter/examples/MatterFan/MatterFan.ino
@@ -0,0 +1,202 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Fan Endpoint - On/Off control + Speed Percent Control + Fan Modes
+MatterFan Fan;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// set your board USER BUTTON pin here - used for toggling On/Off and decommission the Matter Node
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t debouceTime = 250;              // button debouncing time (ms)
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// set your board Analog Pin here - used for changing the Fan speed
+const uint8_t analogPin = A0;  // Analog Pin depends on each board
+
+// set your board PWM Pin here - used for controlling the Fan speed (DC motor example)
+// for this example, it will use the builtin board RGB LED to simulate the Fan DC motor using its brightness
+#ifdef RGB_BUILTIN
+const uint8_t dcMotorPin = RGB_BUILTIN;
+#else
+const uint8_t dcMotorPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#warning "Do not forget to set the RGB LED pin"
+#endif
+
+void fanDCMotorDrive(bool fanState, uint8_t speedPercent) {
+  // drive the Fan DC motor
+  if (fanState == false) {
+    // turn off the Fan
+#ifndef RGB_BUILTIN
+    // after analogWrite(), it is necessary to set the GPIO to digital mode first
+    pinMode(dcMotorPin, OUTPUT);
+#endif
+    digitalWrite(dcMotorPin, LOW);
+  } else {
+    // set the Fan speed
+    uint8_t fanDCMotorPWM = map(speedPercent, 0, 100, 0, 255);
+#ifdef RGB_BUILTIN
+    rgbLedWrite(dcMotorPin, fanDCMotorPWM, fanDCMotorPWM, fanDCMotorPWM);
+#else
+    analogWrite(dcMotorPin, fanDCMotorPWM);
+#endif
+  }
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) GPIO that will toggle the Fan (On/Off) and decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the Analog Pin A0 used to read input voltage and to set the Fan speed accordingly
+  pinMode(analogPin, INPUT);
+  analogReadResolution(10);  // 10 bits resolution reading 0..1023
+  // Initialize the PWM output pin for a Fan DC motor
+  pinMode(dcMotorPin, OUTPUT);
+
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("\r\nWiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // On Boot or Reset, Fan is set at 0% speed, OFF, changing between OFF, ON, SMART and HIGH
+  Fan.begin(0, MatterFan::FAN_MODE_OFF, MatterFan::FAN_MODE_SEQ_OFF_HIGH);
+
+  // callback functions would control Fan motor
+  // the Matter Controller will send new data whenever the User APP or Automation request
+
+  // single feature callbacks take place before the generic (all features) callback
+  // This callback will be executed whenever the speed percent matter attribute is updated
+  Fan.onChangeSpeedPercent([](uint8_t speedPercent) {
+    // setting speed to Zero, while the Fan is ON, shall turn the Fan OFF
+    if (speedPercent == MatterFan::OFF_SPEED && Fan.getMode() != MatterFan::FAN_MODE_OFF) {
+      // ATTR_SET do not update the attribute, just SET it to avoid infinite loop
+      return Fan.setOnOff(false, Fan.ATTR_SET);
+    }
+    // changing the speed to higher than Zero, while the Fan is OFF, shall turn the Fan ON
+    if (speedPercent > MatterFan::OFF_SPEED && Fan.getMode() == MatterFan::FAN_MODE_OFF) {
+      // ATTR_SET do not update the attribute, just SET it to avoid infinite loop
+      return Fan.setOnOff(true, Fan.ATTR_SET);
+    }
+    // for other case, just return true
+    return true;
+  });
+
+  // This callback will be executed whenever the fan mode matter attribute is updated
+  // This will take action when user APP starts the Fan by changing the mode
+  Fan.onChangeMode([](MatterFan::FanMode_t fanMode) {
+    // when the Fan is turned ON using Mode Selection, while it is OFF, shall start it by setting the speed to 50%
+    if (Fan.getSpeedPercent() == MatterFan::OFF_SPEED && fanMode != MatterFan::FAN_MODE_OFF) {
+      Serial.printf("Fan set to %s mode -- speed percentage will go to 50%%\r\n", Fan.getFanModeString(fanMode));
+      // ATTR_SET do not update the attribute, just SET it to avoid infinite loop
+      return Fan.setSpeedPercent(50, Fan.ATTR_SET);
+    }
+    return true;
+  });
+
+  // Generic callback will be executed as soon as a single feature callback is done
+  // In this example, it will just print status messages
+  Fan.onChange([](MatterFan::FanMode_t fanMode, uint8_t speedPercent) {
+    // just report state
+    Serial.printf("Fan State: Mode %s | %d%% speed.\r\n", Fan.getFanModeString(fanMode), speedPercent);
+    // drive the Fan DC motor
+    fanDCMotorDrive(fanMode != MatterFan::FAN_MODE_OFF, speedPercent);
+    // returns success
+    return true;
+  });
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+  // This may be a restart of a already commissioned Matter accessory
+  if (Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+}
+
+void loop() {
+  // Check Matter Accessory Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Generic Switch Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+
+  // A builtin button is used to trigger and send a command to the Matter Controller
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  // Onboard User Button is used as a smart button or to decommission it
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > debouceTime && digitalRead(buttonPin) == HIGH) {
+    button_state = false;  // released
+    // button is released - toggle Fan On/Off
+    Fan.toggle();
+    Serial.printf("User button released. Setting the Fan %s.\r\n", Fan > 0 ? "ON" : "OFF");
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning Fan Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+
+  // checks Analog pin and adjust the speed only if it has changed
+  static int lastRead = 0;
+  // analog values (0..1023) / 103 => mapped into 10 steps (0..9)
+  int anaVal = analogRead(analogPin) / 103;
+  if (lastRead != anaVal) {
+    // speed percent moves in steps of 10. Range is 10..100
+    if (Fan.setSpeedPercent((anaVal + 1) * 10)) {
+      lastRead = anaVal;
+    }
+  }
+}
diff --git a/libraries/Matter/examples/MatterFan/ci.json b/libraries/Matter/examples/MatterFan/ci.json
new file mode 100644
index 00000000000..0665800b12b
--- /dev/null
+++ b/libraries/Matter/examples/MatterFan/ci.json
@@ -0,0 +1,7 @@
+{
+    "fqbn_append": "PartitionScheme=huge_app",
+    "requires": [
+      "CONFIG_SOC_WIFI_SUPPORTED=y",
+      "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+    ]
+}
diff --git a/libraries/Matter/examples/MatterHumiditySensor/MatterHumiditySensor.ino b/libraries/Matter/examples/MatterHumiditySensor/MatterHumiditySensor.ino
new file mode 100644
index 00000000000..1c7889db849
--- /dev/null
+++ b/libraries/Matter/examples/MatterHumiditySensor/MatterHumiditySensor.ino
@@ -0,0 +1,130 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * This example is an example code that will create a Matter Device which can be
+ * commissioned and controlled from a Matter Environment APP.
+ * Additionally the ESP32 will send debug messages indicating the Matter activity.
+ * Turning DEBUG Level ON may be useful to following Matter Accessory and Controller messages.
+ */
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Matter Humidity Sensor Endpoint
+MatterHumiditySensor SimulatedHumiditySensor;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// set your board USER BUTTON pin here - decommissioning button
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control - decommision the Matter Node
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Simulate a humidity sensor - add your preferred humidity sensor library code here
+float getSimulatedHumidity() {
+  // The Endpoint implementation keeps an uint16_t as internal value information,
+  // which stores data in 1/100th of humidity percent
+  static float simulatedHumidityHWSensor = 10.0;
+
+  // it will increase from 10% to 30% in 0.5% steps to simulate a humidity sensor
+  simulatedHumidityHWSensor = simulatedHumidityHWSensor + 0.5;
+  if (simulatedHumidityHWSensor > 30) {
+    simulatedHumidityHWSensor = 10;
+  }
+
+  return simulatedHumidityHWSensor;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+
+  Serial.begin(115200);
+
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println();
+
+  // set initial humidity sensor measurement
+  // Simulated Sensor - it shall initially print 95% and then move to the 10% to 30% humidity range
+  SimulatedHumiditySensor.begin(95.00);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+
+  // Check Matter Accessory Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Humidity Sensor Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+}
+
+void loop() {
+  static uint32_t timeCounter = 0;
+
+  // Print the current humidity value every 5s
+  if (!(timeCounter++ % 10)) {  // delaying for 500ms x 10 = 5s
+    // Print the current humidity value
+    Serial.printf("Current Humidity is %.02f%%\r\n", SimulatedHumiditySensor.getHumidity());
+    // Update Humidity from the (Simulated) Hardware Sensor
+    // Matter APP shall display the updated humidity percent
+    SimulatedHumiditySensor.setHumidity(getSimulatedHumidity());
+  }
+
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  if (digitalRead(buttonPin) == HIGH && button_state) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning Humidity Sensor Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+  }
+
+  delay(500);
+}
diff --git a/libraries/Matter/examples/MatterHumiditySensor/ci.json b/libraries/Matter/examples/MatterHumiditySensor/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterHumiditySensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterMinimum/MatterMinimum.ino b/libraries/Matter/examples/MatterMinimum/MatterMinimum.ino
new file mode 100644
index 00000000000..db591ee2226
--- /dev/null
+++ b/libraries/Matter/examples/MatterMinimum/MatterMinimum.ino
@@ -0,0 +1,116 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * This example is the smallest code that will create a Matter Device which can be
+ * commissioned and controlled from a Matter Environment APP.
+ * It controls a GPIO that could be attached to a LED for visualization.
+ * Additionally the ESP32 will send debug messages indicating the Matter activity.
+ * Turning DEBUG Level ON may be useful to following Matter Accessory and Controller messages.
+ */
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Single On/Off Light Endpoint - at least one per node
+MatterOnOffLight OnOffLight;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// Light GPIO that can be controlled by Matter APP
+#ifdef LED_BUILTIN
+const uint8_t ledPin = LED_BUILTIN;
+#else
+const uint8_t ledPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#endif
+
+// set your board USER BUTTON pin here - decommissioning button
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control - decommision the Matter Node
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Matter Protocol Endpoint (On/OFF Light) Callback
+bool onOffLightCallback(bool state) {
+  digitalWrite(ledPin, state ? HIGH : LOW);
+  // This callback must return the success state to Matter core
+  return true;
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the LED GPIO
+  pinMode(ledPin, OUTPUT);
+
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  Serial.println();
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  while (WiFi.status() != WL_CONNECTED) {
+    Serial.print('.');
+    delay(500);
+  }
+  Serial.println();
+
+  // Initialize at least one Matter EndPoint
+  OnOffLight.begin();
+
+  // Associate a callback to the Matter Controller
+  OnOffLight.onChange(onOffLightCallback);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+  }
+}
+
+void loop() {
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  if (digitalRead(buttonPin) == HIGH && button_state) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Light Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+
+  delay(500);
+}
diff --git a/libraries/Matter/examples/MatterMinimum/ci.json b/libraries/Matter/examples/MatterMinimum/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterMinimum/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterOccupancySensor/MatterOccupancySensor.ino b/libraries/Matter/examples/MatterOccupancySensor/MatterOccupancySensor.ino
new file mode 100644
index 00000000000..333f178e9de
--- /dev/null
+++ b/libraries/Matter/examples/MatterOccupancySensor/MatterOccupancySensor.ino
@@ -0,0 +1,128 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * This example is an example code that will create a Matter Device which can be
+ * commissioned and controlled from a Matter Environment APP.
+ * Additionally the ESP32 will send debug messages indicating the Matter activity.
+ * Turning DEBUG Level ON may be useful to following Matter Accessory and Controller messages.
+ *
+ * The example will create a Matter Occupancy Sensor Device.
+ * The Occupancy Sensor will be simulated to change its state every 2 minutes.
+ *
+ * The onboard button can be kept pressed for 5 seconds to decommission the Matter Node.
+ * The example will also show the manual commissioning code and QR code to be used in the Matter environment.
+ *
+ */
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Matter Occupancy Sensor Endpoint
+MatterOccupancySensor OccupancySensor;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// set your board USER BUTTON pin here - decommissioning only
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+
+  Serial.begin(115200);
+
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println();
+
+  // set initial occupancy sensor state as false and connected to a PIR sensor type (default)
+  OccupancySensor.begin();
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+
+  // Check Matter Accessory Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Occupancy Sensor Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+}
+
+bool simulatedHWOccupancySensor() {
+  // Simulated Occupancy Sensor
+  static bool occupancyState = false;
+  static uint32_t lastTime = millis();
+  const uint32_t occupancyTimeout = 120000;  // 2 minutes to toggle the state
+
+  // Simulate a Occupancy Sensor state change every 2 minutes
+  if (millis() - lastTime > occupancyTimeout) {
+    occupancyState = !occupancyState;
+    lastTime = millis();
+  }
+  return occupancyState;
+}
+
+void loop() {
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  if (button_state && digitalRead(buttonPin) == HIGH) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning Occupancy Sensor Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+
+  // Check Simulated Occupancy Sensor and set Matter Attribute
+  OccupancySensor.setOccupancy(simulatedHWOccupancySensor());
+
+  delay(50);
+}
diff --git a/libraries/Matter/examples/MatterOccupancySensor/ci.json b/libraries/Matter/examples/MatterOccupancySensor/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterOccupancySensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterOnIdentify/MatterOnIdentify.ino b/libraries/Matter/examples/MatterOnIdentify/MatterOnIdentify.ino
new file mode 100644
index 00000000000..b2e77900e95
--- /dev/null
+++ b/libraries/Matter/examples/MatterOnIdentify/MatterOnIdentify.ino
@@ -0,0 +1,164 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * This example is the smallest code that will create a Matter Device which can be
+ * commissioned and controlled from a Matter Environment APP.
+ * It controls a GPIO that could be attached to a LED for visualization.
+ * Additionally the ESP32 will send debug messages indicating the Matter activity.
+ * Turning DEBUG Level ON may be useful to following Matter Accessory and Controller messages.
+ *
+ * This example is a simple Matter On/Off Light that can be controlled by a Matter Controller.
+ * It demonstrates how to use On Identify callback when the Identify Cluster is called.
+ * The Matter user APP can be used to request the device to identify itself by blinking the LED.
+ */
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Single On/Off Light Endpoint - at least one per node
+MatterOnOffLight OnOffLight;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// Light GPIO that can be controlled by Matter APP
+#ifdef LED_BUILTIN
+const uint8_t ledPin = LED_BUILTIN;
+#else
+const uint8_t ledPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#endif
+
+// set your board USER BUTTON pin here - decommissioning button
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control - decommision the Matter Node
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Identify Flag and blink time - Blink the LED
+const uint8_t identifyLedPin = ledPin;  // uses the same LED as the Light - change if needed
+volatile bool identifyFlag = false;     // Flag to start the Blink when in Identify state
+bool identifyBlink = false;             // Blink state when in Identify state
+
+// Matter Protocol Endpoint (On/OFF Light) Callback
+bool onOffLightCallback(bool state) {
+  digitalWrite(ledPin, state ? HIGH : LOW);
+  // This callback must return the success state to Matter core
+  return true;
+}
+
+// Identification shall be done by Blink in Red or just the GPIO when no LED_BUILTIN is not defined
+bool onIdentifyLightCallback(bool identifyIsActive) {
+  Serial.printf("Identify Cluster is %s\r\n", identifyIsActive ? "Active" : "Inactive");
+  if (identifyIsActive) {
+    // Start Blinking the light in loop()
+    identifyFlag = true;
+    identifyBlink = !OnOffLight;  // Start with the inverted light state
+  } else {
+    // Stop Blinking and restore the light to the its last state
+    identifyFlag = false;
+    // force returning to the original state by toggling the light twice
+    OnOffLight.toggle();
+    OnOffLight.toggle();
+  }
+  return true;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the LED GPIO
+  pinMode(ledPin, OUTPUT);
+
+  Serial.begin(115200);
+
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println();
+
+  // Initialize at least one Matter EndPoint
+  OnOffLight.begin();
+
+  // On Identify Callback - Blink the LED
+  OnOffLight.onIdentify(onIdentifyLightCallback);
+
+  // Associate a callback to the Matter Controller
+  OnOffLight.onChange(onOffLightCallback);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+
+  // Check Matter Accessory Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Occupancy Sensor Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+}
+
+void loop() {
+  // check if the Light is in  identify state and blink it every 500ms (delay loop time)
+  if (identifyFlag) {
+#ifdef LED_BUILTIN
+    uint8_t brightness = 32 * identifyBlink;
+    rgbLedWrite(identifyLedPin, brightness, 0, 0);
+#else
+    digitalWrite(identifyLedPin, identifyBlink ? HIGH : LOW);
+#endif
+    identifyBlink = !identifyBlink;
+  }
+
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  if (digitalRead(buttonPin) == HIGH && button_state) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Light Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+
+  delay(500);  // works as a debounce for the button and also for the LED blink
+}
diff --git a/libraries/Matter/examples/MatterOnIdentify/ci.json b/libraries/Matter/examples/MatterOnIdentify/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterOnIdentify/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterOnOffLight/MatterOnOffLight.ino b/libraries/Matter/examples/MatterOnOffLight/MatterOnOffLight.ino
new file mode 100644
index 00000000000..5faa0a385b0
--- /dev/null
+++ b/libraries/Matter/examples/MatterOnOffLight/MatterOnOffLight.ino
@@ -0,0 +1,148 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+#include <Preferences.h>
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// List of Matter Endpoints for this Node
+// On/Off Light Endpoint
+MatterOnOffLight OnOffLight;
+
+// it will keep last OnOff state stored, using Preferences
+Preferences matterPref;
+const char *onOffPrefKey = "OnOff";
+
+// set your board LED pin here
+#ifdef LED_BUILTIN
+const uint8_t ledPin = LED_BUILTIN;
+#else
+const uint8_t ledPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#warning "Do not forget to set the LED pin"
+#endif
+
+// set your board USER BUTTON pin here
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t debouceTime = 250;              // button debouncing time (ms)
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Matter Protocol Endpoint Callback
+bool setLightOnOff(bool state) {
+  Serial.printf("User Callback :: New Light State = %s\r\n", state ? "ON" : "OFF");
+  if (state) {
+    digitalWrite(ledPin, HIGH);
+  } else {
+    digitalWrite(ledPin, LOW);
+  }
+  // store last OnOff state for when the Light is restarted / power goes off
+  matterPref.putBool(onOffPrefKey, state);
+  // This callback must return the success state to Matter core
+  return true;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) GPIO that will act as a toggle switch
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the LED (light) GPIO and Matter End Point
+  pinMode(ledPin, OUTPUT);
+
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("\r\nWiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // Initialize Matter EndPoint
+  matterPref.begin("MatterPrefs", false);
+  bool lastOnOffState = matterPref.getBool(onOffPrefKey, true);
+  OnOffLight.begin(lastOnOffState);
+  OnOffLight.onChange(setLightOnOff);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+  // This may be a restart of a already commissioned Matter accessory
+  if (Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+    Serial.printf("Initial state: %s\r\n", OnOffLight.getOnOff() ? "ON" : "OFF");
+    OnOffLight.updateAccessory();  // configure the Light based on initial state
+  }
+}
+
+void loop() {
+  // Check Matter Light Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Light Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.printf("Initial state: %s\r\n", OnOffLight.getOnOff() ? "ON" : "OFF");
+    OnOffLight.updateAccessory();  // configure the Light based on initial state
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+
+  // A button is also used to control the light
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  // Onboard User Button is used as a Light toggle switch or to decommission it
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > debouceTime && digitalRead(buttonPin) == HIGH) {
+    button_state = false;  // released
+    // Toggle button is released - toggle the light
+    Serial.println("User button released. Toggling Light!");
+    OnOffLight.toggle();  // Matter Controller also can see the change
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Light Matter Accessory. It shall be commissioned again.");
+    OnOffLight.setOnOff(false);  // turn the light off
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+}
diff --git a/libraries/Matter/examples/MatterOnOffLight/ci.json b/libraries/Matter/examples/MatterOnOffLight/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterOnOffLight/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterOnOffPlugin/MatterOnOffPlugin.ino b/libraries/Matter/examples/MatterOnOffPlugin/MatterOnOffPlugin.ino
new file mode 100644
index 00000000000..d14e2189ec1
--- /dev/null
+++ b/libraries/Matter/examples/MatterOnOffPlugin/MatterOnOffPlugin.ino
@@ -0,0 +1,142 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+#include <Preferences.h>
+
+// List of Matter Endpoints for this Node
+// On/Off Plugin Endpoint
+MatterOnOffPlugin OnOffPlugin;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// it will keep last OnOff state stored, using Preferences
+Preferences matterPref;
+const char *onOffPrefKey = "OnOff";
+
+// set your board Power Relay pin here - this example uses the built-in LED for easy visualization
+#ifdef LED_BUILTIN
+const uint8_t onoffPin = LED_BUILTIN;
+#else
+const uint8_t onoffPin = 2;  // Set your pin here - usually a power relay
+#warning "Do not forget to set the Power Relay pin"
+#endif
+
+// board USER BUTTON pin necessary for Decommissioning
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Matter Protocol Endpoint Callback
+bool setPluginOnOff(bool state) {
+  Serial.printf("User Callback :: New Plugin State = %s\r\n", state ? "ON" : "OFF");
+  if (state) {
+    digitalWrite(onoffPin, HIGH);
+  } else {
+    digitalWrite(onoffPin, LOW);
+  }
+  // store last OnOff state for when the Plugin is restarted / power goes off
+  matterPref.putBool(onOffPrefKey, state);
+  // This callback must return the success state to Matter core
+  return true;
+}
+
+void setup() {
+  // Initialize the USER BUTTON
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the Power Relay (plugin) GPIO
+  pinMode(onoffPin, OUTPUT);
+
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("\r\nWiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // Initialize Matter EndPoint
+  matterPref.begin("MatterPrefs", false);
+  bool lastOnOffState = matterPref.getBool(onOffPrefKey, false);
+  OnOffPlugin.begin(lastOnOffState);
+  OnOffPlugin.onChange(setPluginOnOff);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+  // This may be a restart of a already commissioned Matter accessory
+  if (Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+    Serial.printf("Initial state: %s\r\n", OnOffPlugin.getOnOff() ? "ON" : "OFF");
+    OnOffPlugin.updateAccessory();  // configure the Plugin based on initial state
+  }
+}
+
+void loop() {
+  // Check Matter Plugin Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Plugin Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.printf("Initial state: %s\r\n", OnOffPlugin.getOnOff() ? "ON" : "OFF");
+    OnOffPlugin.updateAccessory();  // configure the Plugin based on initial state
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  // Onboard User Button is used to decommission the Matter Node
+  if (button_state && digitalRead(buttonPin) == HIGH) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Plugin Matter Accessory. It shall be commissioned again.");
+    OnOffPlugin.setOnOff(false);  // turn the plugin off
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+}
diff --git a/libraries/Matter/examples/MatterOnOffPlugin/ci.json b/libraries/Matter/examples/MatterOnOffPlugin/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterOnOffPlugin/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterPressureSensor/MatterPressureSensor.ino b/libraries/Matter/examples/MatterPressureSensor/MatterPressureSensor.ino
new file mode 100644
index 00000000000..db035e951c9
--- /dev/null
+++ b/libraries/Matter/examples/MatterPressureSensor/MatterPressureSensor.ino
@@ -0,0 +1,131 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * This example is an example code that will create a Matter Device which can be
+ * commissioned and controlled from a Matter Environment APP.
+ * Additionally the ESP32 will send debug messages indicating the Matter activity.
+ * Turning DEBUG Level ON may be useful to following Matter Accessory and Controller messages.
+ */
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Matter Pressure Sensor Endpoint
+MatterPressureSensor SimulatedPressureSensor;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// set your board USER BUTTON pin here - decommissioning button
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control - decommision the Matter Node
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Simulate a pressure sensor - add your preferred pressure sensor library code here
+float getSimulatedPressure() {
+  // The Endpoint implementation keeps an uint16_t as internal value information,
+  // which stores data in hPa (pressure measurement unit)
+  static float simulatedPressureHWSensor = 950;
+
+  // it will increase from 950 to 1100 hPa in steps of 10 hPa to simulate a pressure sensor
+  simulatedPressureHWSensor = simulatedPressureHWSensor + 10;
+  if (simulatedPressureHWSensor > 1100) {
+    simulatedPressureHWSensor = 950;
+  }
+
+  return simulatedPressureHWSensor;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+
+  Serial.begin(115200);
+
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println();
+
+  // set initial pressure sensor measurement
+  // Simulated Sensor - it shall initially print 900hPa and then move to the 950 to 1100 hPa as pressure range
+  SimulatedPressureSensor.begin(900.00);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+
+  // Check Matter Accessory Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Pressure Sensor Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+}
+
+void loop() {
+  static uint32_t timeCounter = 0;
+
+  // Print the current pressure value every 5s
+  if (!(timeCounter++ % 10)) {  // delaying for 500ms x 10 = 5s
+    // Print the current pressure value
+    Serial.printf("Current Pressure is %.02fhPa\r\n", SimulatedPressureSensor.getPressure());
+    // Update Pressure from the (Simulated) Hardware Sensor
+    // Matter APP shall display the updated pressure percent
+    SimulatedPressureSensor.setPressure(getSimulatedPressure());
+  }
+
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  if (digitalRead(buttonPin) == HIGH && button_state) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    // Factory reset is triggered if the button is pressed longer than 5 seconds
+    Serial.println("Decommissioning Pressure Sensor Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+  }
+
+  delay(500);
+}
diff --git a/libraries/Matter/examples/MatterPressureSensor/ci.json b/libraries/Matter/examples/MatterPressureSensor/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterPressureSensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterSmartButon/MatterSmartButon.ino b/libraries/Matter/examples/MatterSmartButon/MatterSmartButon.ino
new file mode 100644
index 00000000000..f8da970595d
--- /dev/null
+++ b/libraries/Matter/examples/MatterSmartButon/MatterSmartButon.ino
@@ -0,0 +1,113 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Generic Switch Endpoint - works as a smart button with a single click
+MatterGenericSwitch SmartButton;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// set your board USER BUTTON pin here
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t debouceTime = 250;              // button debouncing time (ms)
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) GPIO that will act as a smart button or to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("\r\nWiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // Initialize the Matter EndPoint
+  SmartButton.begin();
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+  // This may be a restart of a already commissioned Matter accessory
+  if (Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+}
+
+void loop() {
+  // Check Matter Accessory Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Generic Switch Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+
+  // A builtin button is used to trigger a command to the Matter Controller
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  // Onboard User Button is used as a smart button or to decommission it
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > debouceTime && digitalRead(buttonPin) == HIGH) {
+    button_state = false;  // released
+    // builtin button is released - send a click event to the Matter Controller
+    Serial.println("User button released. Sending Click to the Matter Controller!");
+    // Matter Controller will receive an event and, if programmed, it will trigger an action
+    SmartButton.click();
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Generic Switch Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+}
diff --git a/libraries/Matter/examples/MatterSmartButon/ci.json b/libraries/Matter/examples/MatterSmartButon/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterSmartButon/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterTemperatureLight/MatterTemperatureLight.ino b/libraries/Matter/examples/MatterTemperatureLight/MatterTemperatureLight.ino
new file mode 100644
index 00000000000..d46427591ab
--- /dev/null
+++ b/libraries/Matter/examples/MatterTemperatureLight/MatterTemperatureLight.ino
@@ -0,0 +1,196 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+#include <Preferences.h>
+
+// List of Matter Endpoints for this Node
+// Color Temperature CW/WW Light Endpoint
+MatterColorTemperatureLight CW_WW_Light;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// it will keep last OnOff & Brightness state stored, using Preferences
+Preferences matterPref;
+const char *onOffPrefKey = "OnOff";
+const char *brightnessPrefKey = "Brightness";
+const char *temperaturePrefKey = "Temperature";
+
+// set your board RGB LED pin here
+#ifdef RGB_BUILTIN
+const uint8_t ledPin = RGB_BUILTIN;
+#else
+const uint8_t ledPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#warning "Do not forget to set the RGB LED pin"
+#endif
+
+// set your board USER BUTTON pin here
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t debouceTime = 250;              // button debouncing time (ms)
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Set the RGB LED Light based on the current state of the Color Temperature Light
+bool setLightState(bool state, uint8_t brightness, uint16_t temperature_Mireds) {
+
+  if (state) {
+#ifdef RGB_BUILTIN
+    espRgbColor_t rgb_ct = espCTToRgbColor(temperature_Mireds);
+    // simple intensity correction
+    float brightnessPercent = (float)brightness / MatterColorTemperatureLight::MAX_BRIGHTNESS;
+    rgb_ct.r = brightnessPercent * rgb_ct.r;
+    rgb_ct.g = brightnessPercent * rgb_ct.g;
+    rgb_ct.b = brightnessPercent * rgb_ct.b;
+    // set the RGB LED
+    rgbLedWrite(ledPin, rgb_ct.r, rgb_ct.g, rgb_ct.b);
+#else
+    // No Color RGB LED, just use the brightness to control the LED
+    analogWrite(ledPin, brightness);
+#endif
+  } else {
+#ifndef RGB_BUILTIN
+    // after analogWrite(), it is necessary to set the GPIO to digital mode first
+    pinMode(ledPin, OUTPUT);
+#endif
+    digitalWrite(ledPin, LOW);
+  }
+  // store last Brightness and OnOff state for when the Light is restarted / power goes off
+  matterPref.putUChar(brightnessPrefKey, brightness);
+  matterPref.putBool(onOffPrefKey, state);
+  matterPref.putUShort(temperaturePrefKey, temperature_Mireds);
+  // This callback must return the success state to Matter core
+  return true;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) GPIO that will act as a toggle switch
+  pinMode(buttonPin, INPUT_PULLUP);
+  // Initialize the LED (light) GPIO and Matter End Point
+  pinMode(ledPin, OUTPUT);
+
+  Serial.begin(115200);
+
+  // We start by connecting to a WiFi network
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("\r\nWiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  delay(500);
+
+  // Initialize Matter EndPoint
+  matterPref.begin("MatterPrefs", false);
+  // default OnOff state is ON if not stored before
+  bool lastOnOffState = matterPref.getBool(onOffPrefKey, true);
+  // default brightness ~= 6% (15/255)
+  uint8_t lastBrightness = matterPref.getUChar(brightnessPrefKey, 15);
+  // default temperature ~= 454 Mireds (Warm White)
+  uint16_t lastTemperature = matterPref.getUShort(temperaturePrefKey, WARM_WHITE_COLOR_TEMPERATURE.ctMireds);
+  CW_WW_Light.begin(lastOnOffState, lastBrightness, lastTemperature);
+  // set the callback function to handle the Light state change
+  CW_WW_Light.onChange(setLightState);
+
+  // lambda functions are used to set the attribute change callbacks
+  CW_WW_Light.onChangeOnOff([](bool state) {
+    Serial.printf("Light OnOff changed to %s\r\n", state ? "ON" : "OFF");
+    return true;
+  });
+  CW_WW_Light.onChangeBrightness([](uint8_t level) {
+    Serial.printf("Light Brightness changed to %d\r\n", level);
+    return true;
+  });
+  CW_WW_Light.onChangeColorTemperature([](uint16_t temperature) {
+    Serial.printf("Light Color Temperature changed to %d\r\n", temperature);
+    return true;
+  });
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+  // This may be a restart of a already commissioned Matter accessory
+  if (Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+    Serial.printf(
+      "Initial state: %s | brightness: %d | Color Temperature: %d mireds \r\n", CW_WW_Light ? "ON" : "OFF", CW_WW_Light.getBrightness(),
+      CW_WW_Light.getColorTemperature()
+    );
+    // configure the Light based on initial on-off state and brightness
+    CW_WW_Light.updateAccessory();
+  }
+}
+
+void loop() {
+  // Check Matter Light Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Light Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.printf(
+      "Initial state: %s | brightness: %d | Color Temperature: %d mireds \r\n", CW_WW_Light ? "ON" : "OFF", CW_WW_Light.getBrightness(),
+      CW_WW_Light.getColorTemperature()
+    );
+    // configure the Light based on initial on-off state and brightness
+    CW_WW_Light.updateAccessory();
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+
+  // A button is also used to control the light
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  // Onboard User Button is used as a Light toggle switch or to decommission it
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > debouceTime && digitalRead(buttonPin) == HIGH) {
+    button_state = false;  // released
+    // Toggle button is released - toggle the light
+    Serial.println("User button released. Toggling Light!");
+    CW_WW_Light.toggle();  // Matter Controller also can see the change
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Light Matter Accessory. It shall be commissioned again.");
+    CW_WW_Light = false;  // turn the light off
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+}
diff --git a/libraries/Matter/examples/MatterTemperatureLight/ci.json b/libraries/Matter/examples/MatterTemperatureLight/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterTemperatureLight/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterTemperatureSensor/MatterTemperatureSensor.ino b/libraries/Matter/examples/MatterTemperatureSensor/MatterTemperatureSensor.ino
new file mode 100644
index 00000000000..086155aeffe
--- /dev/null
+++ b/libraries/Matter/examples/MatterTemperatureSensor/MatterTemperatureSensor.ino
@@ -0,0 +1,131 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * This example is an example code that will create a Matter Device which can be
+ * commissioned and controlled from a Matter Environment APP.
+ * Additionally the ESP32 will send debug messages indicating the Matter activity.
+ * Turning DEBUG Level ON may be useful to following Matter Accessory and Controller messages.
+ */
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Matter Temperature Sensor Endpoint
+MatterTemperatureSensor SimulatedTemperatureSensor;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// set your board USER BUTTON pin here - decommissioning button
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control - decommision the Matter Node
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Simulate a temperature sensor - add your preferred temperature sensor library code here
+float getSimulatedTemperature() {
+  // The Endpoint implementation keeps an int16_t as internal value information,
+  // which stores data in 1/100th Celsius.
+  static float simulatedTempHWSensor = -10.0;
+
+  // it will increase from -10C to 10C in 0.5C steps to simulate a temperature sensor
+  simulatedTempHWSensor = simulatedTempHWSensor + 0.5;
+  if (simulatedTempHWSensor > 10) {
+    simulatedTempHWSensor = -10;
+  }
+
+  return simulatedTempHWSensor;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+
+  Serial.begin(115200);
+
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println();
+
+  // set initial temperature sensor measurement
+  // Simulated Sensor - it shall initially print -25C and then move to the -10C to 10C range
+  SimulatedTemperatureSensor.begin(-25.00);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+
+  // Check Matter Accessory Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Temperature Sensor Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+  }
+}
+
+void loop() {
+  static uint32_t timeCounter = 0;
+
+  // Print the current temperature value every 5s
+  if (!(timeCounter++ % 10)) {  // delaying for 500ms x 10 = 5s
+    // Print the current temperature value
+    Serial.printf("Current Temperature is %.02fC\r\n", SimulatedTemperatureSensor.getTemperature());
+    // Update Temperature from the (Simulated) Hardware Sensor
+    // Matter APP shall display the updated temperature percent
+    SimulatedTemperatureSensor.setTemperature(getSimulatedTemperature());
+  }
+
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  if (digitalRead(buttonPin) == HIGH && button_state) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning Temperature Sensor Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+
+  delay(500);
+}
diff --git a/libraries/Matter/examples/MatterTemperatureSensor/ci.json b/libraries/Matter/examples/MatterTemperatureSensor/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterTemperatureSensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/MatterThermostat/MatterThermostat.ino b/libraries/Matter/examples/MatterThermostat/MatterThermostat.ino
new file mode 100644
index 00000000000..bf76477c846
--- /dev/null
+++ b/libraries/Matter/examples/MatterThermostat/MatterThermostat.ino
@@ -0,0 +1,243 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+   This example is an example code that will create a Matter Device which can be
+   commissioned and controlled from a Matter Environment APP.
+   Additionally the ESP32 will send debug messages indicating the Matter activity.
+   Turning DEBUG Level ON may be useful to following Matter Accessory and Controller messages.
+*/
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFi.h>
+
+// List of Matter Endpoints for this Node
+// Matter Thermostat Endpoint
+MatterThermostat SimulatedThermostat;
+
+// WiFi is manually set and started
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
+
+// set your board USER BUTTON pin here - decommissioning button
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control - decommision the Matter Node
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Simulate a system that will activate heating/cooling in addition to a temperature sensor - add your preferred code here
+float getSimulatedTemperature(bool isHeating, bool isCooling) {
+  // read sensor temperature and apply heating/cooling
+  float simulatedTempHWSensor = SimulatedThermostat.getLocalTemperature();
+
+  if (isHeating) {
+    // it will increase to simulate a heating system
+    simulatedTempHWSensor = simulatedTempHWSensor + 0.5;
+  }
+  if (isCooling) {
+    // it will decrease to simulate a colling system
+    simulatedTempHWSensor = simulatedTempHWSensor - 0.5;
+  }
+  // otherwise, it will keep the temperature stable
+  return simulatedTempHWSensor;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+
+  Serial.begin(115200);
+
+  // Manually connect to WiFi
+  WiFi.begin(ssid, password);
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println();
+
+  // Simulated Thermostat in COOLING and HEATING mode with Auto Mode to keep the temperature between setpoints
+  // Auto Mode can only be used when the control sequence of operation is Cooling & Heating
+  SimulatedThermostat.begin(MatterThermostat::THERMOSTAT_SEQ_OP_COOLING_HEATING, MatterThermostat::THERMOSTAT_AUTO_MODE_ENABLED);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+
+  // Check Matter Accessory Commissioning state, which may change during execution of loop()
+  if (!Matter.isDeviceCommissioned()) {
+    Serial.println("");
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    // waits for Matter Thermostat Commissioning.
+    uint32_t timeCount = 0;
+    while (!Matter.isDeviceCommissioned()) {
+      delay(100);
+      if ((timeCount++ % 50) == 0) {  // 50*100ms = 5 sec
+        Serial.println("Matter Node not commissioned yet. Waiting for commissioning.");
+      }
+    }
+    Serial.println("Matter Node is commissioned and connected to Wi-Fi. Ready for use.");
+
+    // after commissioning, set initial thermostat parameters
+    // start the thermostat in AUTO mode
+    SimulatedThermostat.setMode(MatterThermostat::THERMOSTAT_MODE_AUTO);
+    // cooling setpoint must be lower than heating setpoint by at least 2.5C (deadband), in auto mode
+    SimulatedThermostat.setCoolingHeatingSetpoints(20.0, 23.00);  // the target cooler and heating setpoint
+    // set the local temperature sensor in Celsius
+    SimulatedThermostat.setLocalTemperature(12.50);
+
+    Serial.println();
+    Serial.printf(
+      "Initial Setpoints are %.01fC to %.01fC with a minimum 2.5C difference\r\n", SimulatedThermostat.getHeatingSetpoint(),
+      SimulatedThermostat.getCoolingSetpoint()
+    );
+    Serial.printf("Auto mode is ON. Initial Temperature of %.01fC \r\n", SimulatedThermostat.getLocalTemperature());
+    Serial.println("Local Temperature Sensor will be simulated every 10 seconds and changed by a simulated heater and cooler to move in between setpoints.");
+  }
+}
+
+// This will simulate the thermostat control system (heating and cooling)
+// User can set a local temperature using the Serial input (type a number and press Enter)
+// New temperature can be an positive or negative temperature in Celsius, between -50C and 50C
+// Initial local temperature is 10C as defined in getSimulatedTemperature() function
+void readSerialForNewTemperature() {
+  static String newTemperatureStr;
+
+  while (Serial.available()) {
+    char c = Serial.read();
+    if (c == '\n' || c == '\r') {
+      if (newTemperatureStr.length() > 0) {
+        // convert the string to a float value
+        float newTemperature = newTemperatureStr.toFloat();
+        // check if the new temperature is valid
+        if (newTemperature >= -50.0 && newTemperature <= 50.0) {
+          // set the new temperature
+          SimulatedThermostat.setLocalTemperature(newTemperature);
+          Serial.printf("New Temperature is %.01fC\r\n", newTemperature);
+        } else {
+          Serial.println("Invalid Temperature value. Please type a number between -50 and 50");
+        }
+        newTemperatureStr = "";
+      }
+    } else {
+      if (c == '+' || c == '-' || (c >= '0' && c <= '9') || c == '.') {
+        newTemperatureStr += c;
+      } else {
+        Serial.println("Invalid character. Please type a number between -50 and 50");
+        newTemperatureStr = "";
+      }
+    }
+  }
+}
+
+// loop will simulate the thermostat control system
+// User can set a local temperature using the Serial input (type a number and press Enter)
+// User can change the thermostat mode using the Matter APP (smartphone)
+// The loop will simulate a heating and cooling system and the associated local temperature change
+void loop() {
+  static uint32_t timeCounter = 0;
+
+  // Simulate the heating and cooling systems
+  static bool isHeating = false;
+  static bool isCooling = false;
+
+  // check if a new temperature is typed in the Serial Monitor
+  readSerialForNewTemperature();
+
+  // simulate thermostat with heating/cooling system and the associated local temperature change, every 10s
+  if (!(timeCounter++ % 20)) {  // delaying for 500ms x 20 = 10s
+    float localTemperature = getSimulatedTemperature(isHeating, isCooling);
+    // Print the current thermostat local temperature value
+    Serial.printf("Current Local Temperature is %.01fC\r\n", localTemperature);
+    SimulatedThermostat.setLocalTemperature(localTemperature);  // publish the new temperature value
+
+    // Simulate the thermostat control system - User has 4 modes: OFF, HEAT, COOL, AUTO
+    switch (SimulatedThermostat.getMode()) {
+      case MatterThermostat::THERMOSTAT_MODE_OFF:
+        // turn off the heating and cooling systems
+        isHeating = false;
+        isCooling = false;
+        break;
+      case MatterThermostat::THERMOSTAT_MODE_AUTO:
+        // User APP has set the thermostat to AUTO mode -- keeping the tempeature between both setpoints
+        // check if the heating system should be turned on or off
+        if (localTemperature < SimulatedThermostat.getHeatingSetpoint() + SimulatedThermostat.getDeadBand()) {
+          // turn on the heating system and turn off the cooling system
+          isHeating = true;
+          isCooling = false;
+        }
+        if (localTemperature > SimulatedThermostat.getCoolingSetpoint() - SimulatedThermostat.getDeadBand()) {
+          // turn off the heating system and turn on the cooling system
+          isHeating = false;
+          isCooling = true;
+        }
+        break;
+      case MatterThermostat::THERMOSTAT_MODE_HEAT:
+        // Simulate the heating system - User has turned the heating system ON
+        isHeating = true;
+        isCooling = false;  // keep the cooling system off as it is in heating mode
+        // when the heating system is in HEATING mode, it will be turned off as soon as the local temperature is above the setpoint
+        if (localTemperature > SimulatedThermostat.getHeatingSetpoint()) {
+          // turn off the heating system
+          isHeating = false;
+        }
+        break;
+      case MatterThermostat::THERMOSTAT_MODE_COOL:
+        // Simulate the cooling system - User has turned the cooling system ON
+        if (SimulatedThermostat.getMode() == MatterThermostat::THERMOSTAT_MODE_COOL) {
+          isCooling = true;
+          isHeating = false;  // keep the heating system off as it is in cooling mode
+          // when the cooling system is in COOLING mode, it will be turned off as soon as the local temperature is bellow the setpoint
+          if (localTemperature < SimulatedThermostat.getCoolingSetpoint()) {
+            // turn off the cooling system
+            isCooling = false;
+          }
+        }
+        break;
+      default: log_e("Invalid Thermostat Mode %d", SimulatedThermostat.getMode());
+    }
+    // Reporting Heating and Cooling status
+    Serial.printf(
+      "\tThermostat Mode: %s >>> Heater is %s -- Cooler is %s\r\n", MatterThermostat::getThermostatModeString(SimulatedThermostat.getMode()),
+      isHeating ? "ON" : "OFF", isCooling ? "ON" : "OFF"
+    );
+  }
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  if (digitalRead(buttonPin) == HIGH && button_state) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning Thermostat Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+
+  delay(500);
+}
diff --git a/libraries/Matter/examples/MatterThermostat/ci.json b/libraries/Matter/examples/MatterThermostat/ci.json
new file mode 100644
index 00000000000..556a8a9ee6b
--- /dev/null
+++ b/libraries/Matter/examples/MatterThermostat/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+  ]
+}
diff --git a/libraries/Matter/examples/WiFiProvWithinMatter/WiFiProvWithinMatter.ino b/libraries/Matter/examples/WiFiProvWithinMatter/WiFiProvWithinMatter.ino
new file mode 100644
index 00000000000..3434217624d
--- /dev/null
+++ b/libraries/Matter/examples/WiFiProvWithinMatter/WiFiProvWithinMatter.ino
@@ -0,0 +1,152 @@
+/*
+  Please read README.md file in this folder, or on the web:
+  https://github.com/espressif/arduino-esp32/tree/master/libraries/WiFiProv/examples/WiFiProv
+
+  Note: This sketch takes up a lot of space for the app and may not be able to flash with default setting on some chips.
+  If you see Error like this: "Sketch too big"
+  In Arduino IDE go to: Tools > Partition scheme > chose anything that has more than 1.4MB APP
+   - for example "No OTA (2MB APP/2MB SPIFFS)"
+
+  This example demonstrates that it is possible to provision WiFi using BLE or Software AP using
+  the ESP BLE Prov APP or ESP SoftAP Provisioning APP from Android Play or/and iOS APP Store
+
+  Once the WiFi is provisioned, Matter will start its process as usual.
+
+  This same Example could be used for any other WiFi Provisioning method.
+*/
+
+// Matter Manager
+#include <Matter.h>
+#include <WiFiProv.h>
+#include <WiFi.h>
+
+#if !CONFIG_BLUEDROID_ENABLED
+#define USE_SOFT_AP  // ESP32-S2 has no BLE, therefore, it shall use SoftAP Provisioning
+#endif
+//#define USE_SOFT_AP // Uncomment if you want to enforce using the Soft AP method instead of BLE
+
+const char *pop = "abcd1234";           // Proof of possession - otherwise called a PIN - string provided by the device, entered by the user in the phone app
+const char *service_name = "PROV_123";  // Name of your device (the Espressif apps expects by default device name starting with "Prov_")
+const char *service_key = NULL;         // Password used for SofAP method (NULL = no password needed)
+bool reset_provisioned = true;          // When true the library will automatically delete previously provisioned data.
+
+// List of Matter Endpoints for this Node
+// Single On/Off Light Endpoint - at least one per node
+MatterOnOffLight OnOffLight;
+
+// Light GPIO that can be controlled by Matter APP
+#ifdef LED_BUILTIN
+const uint8_t ledPin = LED_BUILTIN;
+#else
+const uint8_t ledPin = 2;  // Set your pin here if your board has not defined LED_BUILTIN
+#endif
+
+// set your board USER BUTTON pin here - decommissioning button
+const uint8_t buttonPin = BOOT_PIN;  // Set your pin here. Using BOOT Button.
+
+// Button control - decommision the Matter Node
+uint32_t button_time_stamp = 0;                // debouncing control
+bool button_state = false;                     // false = released | true = pressed
+const uint32_t decommissioningTimeout = 5000;  // keep the button pressed for 5s, or longer, to decommission
+
+// Matter Protocol Endpoint (On/OFF Light) Callback
+bool matterCB(bool state) {
+  digitalWrite(ledPin, state ? HIGH : LOW);
+  // This callback must return the success state to Matter core
+  return true;
+}
+
+void setup() {
+  // Initialize the USER BUTTON (Boot button) that will be used to decommission the Matter Node
+  pinMode(buttonPin, INPUT_PULLUP);
+
+  Serial.begin(115200);
+  // Initialize the LED GPIO
+  pinMode(ledPin, OUTPUT);
+
+  WiFi.begin();  // no SSID/PWD - get it from the Provisioning APP or from NVS (last successful connection)
+
+  // BLE Provisioning using the ESP SoftAP Prov works fine for any BLE SoC, including ESP32, ESP32S3 and ESP32C3.
+#if CONFIG_BLUEDROID_ENABLED && !defined(USE_SOFT_AP)
+  Serial.println("Begin Provisioning using BLE");
+  // Sample uuid that user can pass during provisioning using BLE
+  uint8_t uuid[16] = {0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf, 0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02};
+  WiFiProv.beginProvision(
+    NETWORK_PROV_SCHEME_BLE, NETWORK_PROV_SCHEME_HANDLER_FREE_BLE, NETWORK_PROV_SECURITY_1, pop, service_name, service_key, uuid, reset_provisioned
+  );
+  Serial.println("You may use this BLE QRCode:");
+  WiFiProv.printQR(service_name, pop, "ble");
+#else
+  Serial.println("Begin Provisioning using Soft AP");
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_SOFTAP, NETWORK_PROV_SCHEME_HANDLER_NONE, NETWORK_PROV_SECURITY_1, pop, service_name, service_key);
+  Serial.println("You may use this WiFi QRCode:");
+  WiFiProv.printQR(service_name, pop, "softap");
+#endif
+
+  // Wait for WiFi connection
+  uint32_t counter = 0;
+  while (WiFi.status() != WL_CONNECTED) {
+    // resets the device after 10 minutes
+    if (counter > 2 * 60 * 10) {
+      Serial.println("\r\n================================================");
+      Serial.println("Already 10 minutes past. The device will reboot.");
+      Serial.println("================================================\r\n");
+      Serial.flush();  // wait until the Serial has sent the whole message.
+      ESP.restart();
+    }
+    // WiFi searching feedback
+    Serial.print(".");
+    delay(500);
+    // adds a new line every 30 seconds
+    counter++;
+    if (!(counter % 60)) {
+      Serial.println();
+    }
+  }
+
+  // WiFi shall be connected by now
+  Serial.println();
+
+  // Initialize at least one Matter EndPoint
+  OnOffLight.begin();
+
+  // Associate a callback to the Matter Controller
+  OnOffLight.onChange(matterCB);
+
+  // Matter beginning - Last step, after all EndPoints are initialized
+  Matter.begin();
+
+  while (!Matter.isDeviceCommissioned()) {
+    Serial.println("Matter Node is not commissioned yet.");
+    Serial.println("Initiate the device discovery in your Matter environment.");
+    Serial.println("Commission it to your Matter hub with the manual pairing code or QR code");
+    Serial.printf("Manual pairing code: %s\r\n", Matter.getManualPairingCode().c_str());
+    Serial.printf("QR code URL: %s\r\n", Matter.getOnboardingQRCodeUrl().c_str());
+    Serial.println();
+    // waits 30 seconds for Matter Commissioning, keeping it blocked until done
+    delay(30000);
+  }
+}
+
+void loop() {
+  // Check if the button has been pressed
+  if (digitalRead(buttonPin) == LOW && !button_state) {
+    // deals with button debouncing
+    button_time_stamp = millis();  // record the time while the button is pressed.
+    button_state = true;           // pressed.
+  }
+
+  if (digitalRead(buttonPin) == HIGH && button_state) {
+    button_state = false;  // released
+  }
+
+  // Onboard User Button is kept pressed for longer than 5 seconds in order to decommission matter node
+  uint32_t time_diff = millis() - button_time_stamp;
+  if (button_state && time_diff > decommissioningTimeout) {
+    Serial.println("Decommissioning the Light Matter Accessory. It shall be commissioned again.");
+    Matter.decommission();
+    button_time_stamp = millis();  // avoid running decommissining again, reboot takes a second or so
+  }
+
+  delay(500);
+}
diff --git a/libraries/Matter/examples/WiFiProvWithinMatter/ci.json b/libraries/Matter/examples/WiFiProvWithinMatter/ci.json
new file mode 100644
index 00000000000..0665800b12b
--- /dev/null
+++ b/libraries/Matter/examples/WiFiProvWithinMatter/ci.json
@@ -0,0 +1,7 @@
+{
+    "fqbn_append": "PartitionScheme=huge_app",
+    "requires": [
+      "CONFIG_SOC_WIFI_SUPPORTED=y",
+      "CONFIG_ESP_MATTER_ENABLE_DATA_MODEL=y"
+    ]
+}
diff --git a/libraries/Matter/keywords.txt b/libraries/Matter/keywords.txt
new file mode 100644
index 00000000000..a63d9a65acb
--- /dev/null
+++ b/libraries/Matter/keywords.txt
@@ -0,0 +1,148 @@
+#######################################
+# Syntax Coloring Map For Matter
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+Matter	KEYWORD1
+ArduinoMatter	KEYWORD1
+MatterGenericSwitch	KEYWORD1
+MatterOnOffLight	KEYWORD1
+MatterDimmableLight	KEYWORD1
+MatterColorTemperatureLight	KEYWORD1
+MatterColorLight	KEYWORD1
+MatterEnhancedColorLight	KEYWORD1
+MatterEndPoint	KEYWORD1
+MatterFan	KEYWORD1
+FanMode_t	KEYWORD1
+FanModeSequence_t	KEYWORD1
+MatterTemperatureSensor	KEYWORD1
+MatterHumiditySensor	KEYWORD1
+MatterContactSensor	KEYWORD1
+MatterPressureSensor	KEYWORD1
+MatterOccupancySensor	KEYWORD1
+MatterOnOffPlugin	KEYWORD1
+MatterThermostat	KEYWORD1
+ControlSequenceOfOperation_t	KEYWORD1
+ThermostatMode_t	KEYWORD1
+EndPointCB	KEYWORD1
+EndPointHeatingSetpointCB	KEYWORD1
+EndPointCoolingSetpointCB	KEYWORD1
+EndPointTemperatureCB	KEYWORD1
+EndPointModeCB	KEYWORD1
+EndPointSpeedCB	KEYWORD1
+EndPointOnOffCB	KEYWORD1
+EndPointBrightnessCB	KEYWORD1
+EndPointRGBColorCB	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+begin	KEYWORD2
+end	KEYWORD2
+getManualPairingCode	KEYWORD2
+getOnboardingQRCodeUrl	KEYWORD2
+isDeviceCommissioned	KEYWORD2
+isWiFiConnected	KEYWORD2
+isThreadConnected	KEYWORD2
+isDeviceConnected	KEYWORD2
+decommission	KEYWORD2
+attributeChangeCB	KEYWORD2
+setOnOff	KEYWORD2
+getOnOff	KEYWORD2
+toggle	KEYWORD2
+setBrightness	KEYWORD2
+getBrightness	KEYWORD2
+setColorTemperature	KEYWORD2
+getColorTemperature	KEYWORD2
+setColorRGB	KEYWORD2
+getColorRGB	KEYWORD2
+setColorHSV	KEYWORD2
+getColorHSV	KEYWORD2
+updateAccessory	KEYWORD2
+onChange	KEYWORD2
+onChangeOnOff	KEYWORD2
+onChangeBrightness	KEYWORD2
+onChangeColorTemperature	KEYWORD2
+onChangeColorHSV	KEYWORD2
+click	KEYWORD2
+getAttribute	KEYWORD2
+getAttributeVal	KEYWORD2
+setAttributeVal	KEYWORD2
+updateAttributeVal	KEYWORD2
+getFanModeString	KEYWORD2
+setSpeedPercent	KEYWORD2
+getSpeedPercent	KEYWORD2
+setMode	KEYWORD2
+getMode	KEYWORD2
+onChangeMode	KEYWORD2
+onChangeSpeedPercent	KEYWORD2
+setTemperature	KEYWORD2
+getTemperature	KEYWORD2
+setHumidity	KEYWORD2
+getHumidity	KEYWORD2
+setContact	KEYWORD2
+getContact	KEYWORD2
+setPressure	KEYWORD2
+getPressure	KEYWORD2
+setOccupancy	KEYWORD2
+getOccupancy	KEYWORD2
+getControlSequence	KEYWORD2
+getMinHeatSetpoint	KEYWORD2
+getMaxHeatSetpoint	KEYWORD2
+getMinCoolSetpoint	KEYWORD2
+getMaxCoolSetpoint	KEYWORD2
+getDeadBand	KEYWORD2
+setCoolingSetpoint	KEYWORD2
+getCoolingSetpoint	KEYWORD2
+setHeatingSetpoint	KEYWORD2
+getHeatingSetpoint	KEYWORD2
+setCoolingHeatingSetpoints	KEYWORD2
+setLocalTemperature	KEYWORD2
+getLocalTemperature	KEYWORD2
+getThermostatModeString	KEYWORD2
+onChangeMode	KEYWORD2
+onChangeLocalTemperature	KEYWORD2
+onChangeCoolingSetpoint	KEYWORD2
+onChangeHeatingSetpoint	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+
+MAX_BRIGHTNESS	LITERAL1
+MAX_COLOR_TEMPERATURE	LITERAL1
+MIN_COLOR_TEMPERATURE	LITERAL1
+ATTR_SET	LITERAL1
+ATTR_UPDATE	LITERAL1
+MAX_SPEED	LITERAL1
+MIN_SPEED	LITERAL1
+OFF_SPEED	LITERAL1
+FAN_MODE_OFF	LITERAL1
+FAN_MODE_LOW	LITERAL1
+FAN_MODE_MEDIUM	LITERAL1
+FAN_MODE_HIGH	LITERAL1
+FAN_MODE_ON	LITERAL1
+FAN_MODE_AUTO	LITERAL1
+FAN_MODE_SMART	LITERAL1
+FAN_MODE_SEQ_OFF_LOW_MED_HIGH	LITERAL1
+FAN_MODE_SEQ_OFF_LOW_HIGH	LITERAL1
+FAN_MODE_SEQ_OFF_LOW_MED_HIGH_AUTO	LITERAL1
+FAN_MODE_SEQ_OFF_LOW_HIGH_AUTO	LITERAL1
+FAN_MODE_SEQ_OFF_HIGH_AUTO	LITERAL1
+FAN_MODE_SEQ_OFF_HIGH	LITERAL1
+THERMOSTAT_SEQ_OP_COOLING	LITERAL1
+THERMOSTAT_SEQ_OP_COOLING_REHEAT	LITERAL1
+THERMOSTAT_SEQ_OP_HEATING	LITERAL1
+THERMOSTAT_SEQ_OP_HEATING_REHEAT	LITERAL1
+THERMOSTAT_SEQ_OP_COOLING_HEATING	LITERAL1
+THERMOSTAT_SEQ_OP_COOLING_HEATING_REHEAT	LITERAL1
+THERMOSTAT_MODE_OFF	LITERAL1
+THERMOSTAT_MODE_AUTO	LITERAL1
+THERMOSTAT_MODE_COOL	LITERAL1
+THERMOSTAT_MODE_HEAT	LITERAL1
+THERMOSTAT_AUTO_MODE_DISABLED	LITERAL1
+THERMOSTAT_AUTO_MODE_ENABLED	LITERAL1
diff --git a/libraries/Matter/library.properties b/libraries/Matter/library.properties
new file mode 100644
index 00000000000..ac9e0964ab5
--- /dev/null
+++ b/libraries/Matter/library.properties
@@ -0,0 +1,9 @@
+name=Matter
+version=3.2.0
+author=Rodrigo Garcia | GitHub @SuGlider
+maintainer=Rodrigo Garcia <Rodrigo.Garcia@espressif.com>
+sentence=Library for supporting Matter environment on ESP32.
+paragraph=This library implements Matter accessories using WiFi network.
+category=Communication
+url=https://github.com/espressif/arduino-esp32/
+architectures=esp32
diff --git a/libraries/Matter/src/Matter.cpp b/libraries/Matter/src/Matter.cpp
new file mode 100644
index 00000000000..af7c4c8657e
--- /dev/null
+++ b/libraries/Matter/src/Matter.cpp
@@ -0,0 +1,191 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+
+using namespace esp_matter;
+using namespace esp_matter::attribute;
+using namespace esp_matter::endpoint;
+using namespace esp_matter::identification;
+using namespace chip::app::Clusters;
+
+constexpr auto k_timeout_seconds = 300;
+
+static bool _matter_has_started = false;
+static node::config_t node_config;
+static node_t *deviceNode = NULL;
+
+// This callback is called for every attribute update. The callback implementation shall
+// handle the desired attributes and return an appropriate error code. If the attribute
+// is not of your interest, please do not return an error code and strictly return ESP_OK.
+static esp_err_t app_attribute_update_cb(
+  attribute::callback_type_t type, uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val, void *priv_data
+) {
+  log_d("Attribute update callback: type: %u, endpoint: %u, cluster: %u, attribute: %u, val: %u", type, endpoint_id, cluster_id, attribute_id, val->val.u32);
+  esp_err_t err = ESP_OK;
+  MatterEndPoint *ep = (MatterEndPoint *)priv_data;  // endpoint pointer to base class
+  switch (type) {
+    case PRE_UPDATE:  // Callback before updating the value in the database
+      log_v("Attribute update callback: PRE_UPDATE");
+      if (ep != NULL) {
+        err = ep->attributeChangeCB(endpoint_id, cluster_id, attribute_id, val) ? ESP_OK : ESP_FAIL;
+      }
+      break;
+    case POST_UPDATE:  // Callback after updating the value in the database
+      log_v("Attribute update callback: POST_UPDATE");
+      break;
+    case READ:  // Callback for reading the attribute value. This is used when the `ATTRIBUTE_FLAG_OVERRIDE` is set.
+      log_v("Attribute update callback: READ");
+      break;
+    case WRITE:  // Callback for writing the attribute value. This is used when the `ATTRIBUTE_FLAG_OVERRIDE` is set.
+      log_v("Attribute update callback: WRITE");
+      break;
+    default: log_v("Attribute update callback: Unknown type %d", type);
+  }
+  return err;
+}
+
+// This callback is invoked when clients interact with the Identify Cluster.
+// In the callback implementation, an endpoint can identify itself. (e.g., by flashing an LED or light).
+static esp_err_t app_identification_cb(identification::callback_type_t type, uint16_t endpoint_id, uint8_t effect_id, uint8_t effect_variant, void *priv_data) {
+  log_d("Identification callback to endpoint %d: type: %u, effect: %u, variant: %u", endpoint_id, type, effect_id, effect_variant);
+  esp_err_t err = ESP_OK;
+  MatterEndPoint *ep = (MatterEndPoint *)priv_data;  // endpoint pointer to base class
+  // Identify the endpoint sending a counter to the application
+  bool identifyIsActive = false;
+
+  if (type == identification::callback_type_t::START) {
+    log_v("Identification callback: START");
+    identifyIsActive = true;
+  } else if (type == identification::callback_type_t::EFFECT) {
+    log_v("Identification callback: EFFECT");
+  } else if (type == identification::callback_type_t::STOP) {
+    identifyIsActive = false;
+    log_v("Identification callback: STOP");
+  }
+  if (ep != NULL) {
+    err = ep->endpointIdentifyCB(endpoint_id, identifyIsActive) ? ESP_OK : ESP_FAIL;
+  }
+
+  return err;
+}
+
+// This callback is invoked for all Matter events. The application can handle the events as required.
+static void app_event_cb(const ChipDeviceEvent *event, intptr_t arg) {
+  switch (event->Type) {
+    case chip::DeviceLayer::DeviceEventType::kInterfaceIpAddressChanged:
+      log_i(
+        "Interface %s Address changed", event->InterfaceIpAddressChanged.Type == chip::DeviceLayer::InterfaceIpChangeType::kIpV4_Assigned ? "IPv4" : "IPV6"
+      );
+      break;
+    case chip::DeviceLayer::DeviceEventType::kCommissioningComplete:       log_i("Commissioning complete"); break;
+    case chip::DeviceLayer::DeviceEventType::kFailSafeTimerExpired:        log_i("Commissioning failed, fail safe timer expired"); break;
+    case chip::DeviceLayer::DeviceEventType::kCommissioningSessionStarted: log_i("Commissioning session started"); break;
+    case chip::DeviceLayer::DeviceEventType::kCommissioningSessionStopped: log_i("Commissioning session stopped"); break;
+    case chip::DeviceLayer::DeviceEventType::kCommissioningWindowOpened:   log_i("Commissioning window opened"); break;
+    case chip::DeviceLayer::DeviceEventType::kCommissioningWindowClosed:   log_i("Commissioning window closed"); break;
+    case chip::DeviceLayer::DeviceEventType::kFabricRemoved:
+    {
+      log_i("Fabric removed successfully");
+      if (chip::Server::GetInstance().GetFabricTable().FabricCount() == 0) {
+        log_i("No fabric left, opening commissioning window");
+        chip::CommissioningWindowManager &commissionMgr = chip::Server::GetInstance().GetCommissioningWindowManager();
+        constexpr auto kTimeoutSeconds = chip::System::Clock::Seconds16(k_timeout_seconds);
+        if (!commissionMgr.IsCommissioningWindowOpen()) {
+          // After removing last fabric, it does not remove the Wi-Fi credentials and still has IP connectivity so, only advertising on DNS-SD.
+          CHIP_ERROR err = commissionMgr.OpenBasicCommissioningWindow(kTimeoutSeconds, chip::CommissioningWindowAdvertisement::kDnssdOnly);
+          if (err != CHIP_NO_ERROR) {
+            log_e("Failed to open commissioning window, err:%" CHIP_ERROR_FORMAT, err.Format());
+          }
+        }
+      }
+      break;
+    }
+    case chip::DeviceLayer::DeviceEventType::kFabricWillBeRemoved: log_i("Fabric will be removed"); break;
+    case chip::DeviceLayer::DeviceEventType::kFabricUpdated:       log_i("Fabric is updated"); break;
+    case chip::DeviceLayer::DeviceEventType::kFabricCommitted:     log_i("Fabric is committed"); break;
+    case chip::DeviceLayer::DeviceEventType::kBLEDeinitialized:    log_i("BLE deinitialized and memory reclaimed"); break;
+    default:                                                       break;
+  }
+}
+
+void ArduinoMatter::_init() {
+  if (_matter_has_started) {
+    return;
+  }
+
+  // Create a Matter node and add the mandatory Root Node device type on endpoint 0
+  // node handle can be used to add/modify other endpoints.
+  deviceNode = node::create(&node_config, app_attribute_update_cb, app_identification_cb);
+  if (deviceNode == nullptr) {
+    log_e("Failed to create Matter node");
+    return;
+  }
+
+  _matter_has_started = true;
+}
+
+void ArduinoMatter::begin() {
+  if (!_matter_has_started) {
+    log_e("No Matter endpoint has been created. Please create an endpoint first.");
+    return;
+  }
+
+  /* Matter start */
+  esp_err_t err = esp_matter::start(app_event_cb);
+  if (err != ESP_OK) {
+    log_e("Failed to start Matter, err:%d", err);
+    _matter_has_started = false;
+  }
+}
+
+#if CHIP_DEVICE_CONFIG_ENABLE_THREAD
+bool ArduinoMatter::isThreadConnected() {
+  return false;  // Thread Network TBD
+}
+#endif
+
+bool ArduinoMatter::isDeviceCommissioned() {
+  return chip::Server::GetInstance().GetFabricTable().FabricCount() > 0;
+}
+
+#if CHIP_DEVICE_CONFIG_ENABLE_WIFI_STATION
+bool ArduinoMatter::isWiFiConnected() {
+  return chip::DeviceLayer::ConnectivityMgr().IsWiFiStationConnected();
+}
+#endif
+
+bool ArduinoMatter::isDeviceConnected() {
+  bool retCode = false;
+#if CHIP_DEVICE_CONFIG_ENABLE_THREAD
+  retCode |= ArduinoMatter::isThreadConnected();
+#endif
+#if CHIP_DEVICE_CONFIG_ENABLE_WIFI_STATION
+  retCode |= ArduinoMatter::isWiFiConnected();
+#endif
+  return retCode;
+}
+
+void ArduinoMatter::decommission() {
+  esp_matter::factory_reset();
+}
+
+// Global Matter Object
+ArduinoMatter Matter;
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/Matter.h b/libraries/Matter/src/Matter.h
new file mode 100644
index 00000000000..e54ceb47e5e
--- /dev/null
+++ b/libraries/Matter/src/Matter.h
@@ -0,0 +1,82 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Arduino.h>
+#include <esp_matter.h>
+#include <ColorFormat.h>
+#include <MatterEndpoints/MatterGenericSwitch.h>
+#include <MatterEndpoints/MatterOnOffLight.h>
+#include <MatterEndpoints/MatterDimmableLight.h>
+#include <MatterEndpoints/MatterColorTemperatureLight.h>
+#include <MatterEndpoints/MatterColorLight.h>
+#include <MatterEndpoints/MatterEnhancedColorLight.h>
+#include <MatterEndpoints/MatterFan.h>
+#include <MatterEndpoints/MatterTemperatureSensor.h>
+#include <MatterEndpoints/MatterHumiditySensor.h>
+#include <MatterEndpoints/MatterContactSensor.h>
+#include <MatterEndpoints/MatterPressureSensor.h>
+#include <MatterEndpoints/MatterOccupancySensor.h>
+#include <MatterEndpoints/MatterOnOffPlugin.h>
+#include <MatterEndpoints/MatterThermostat.h>
+
+using namespace esp_matter;
+
+class ArduinoMatter {
+public:
+  static inline String getManualPairingCode() {
+    // return the pairing code for manual pairing
+    return String("34970112332");
+  }
+  static inline String getOnboardingQRCodeUrl() {
+    // return the URL for the QR code for onboarding
+    return String("https://project-chip.github.io/connectedhomeip/qrcode.html?data=MT:Y.K9042C00KA0648G00");
+  }
+  static void begin();
+  static bool isDeviceCommissioned();
+#if CHIP_DEVICE_CONFIG_ENABLE_WIFI_STATION
+  static bool isWiFiConnected();
+#endif
+#if CHIP_DEVICE_CONFIG_ENABLE_THREAD
+  static bool isThreadConnected();
+#endif
+  static bool isDeviceConnected();
+  static void decommission();
+
+  // list of Matter EndPoints Friend Classes
+  friend class MatterGenericSwitch;
+  friend class MatterOnOffLight;
+  friend class MatterDimmableLight;
+  friend class MatterColorTemperatureLight;
+  friend class MatterColorLight;
+  friend class MatterEnhancedColorLight;
+  friend class MatterFan;
+  friend class MatterTemperatureSensor;
+  friend class MatterHumiditySensor;
+  friend class MatterContactSensor;
+  friend class MatterPressureSensor;
+  friend class MatterOccupancySensor;
+  friend class MatterOnOffPlugin;
+  friend class MatterThermostat;
+
+protected:
+  static void _init();
+};
+
+extern ArduinoMatter Matter;
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndPoint.h b/libraries/Matter/src/MatterEndPoint.h
new file mode 100644
index 00000000000..5baa4747d18
--- /dev/null
+++ b/libraries/Matter/src/MatterEndPoint.h
@@ -0,0 +1,122 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <functional>
+
+using namespace esp_matter;
+
+// Matter Endpoint Base Class. Controls the endpoint ID and allows the child class to overwrite attribute change call
+class MatterEndPoint {
+public:
+  enum attrOperation_t {
+    ATTR_SET = false,
+    ATTR_UPDATE = true
+  };
+
+  uint16_t getEndPointId() {
+    return endpoint_id;
+  }
+
+  void setEndPointId(uint16_t ep) {
+    endpoint_id = ep;
+  }
+
+  // helper functions for attribute manipulation
+  esp_matter::attribute_t *getAttribute(uint32_t cluster_id, uint32_t attribute_id) {
+    if (endpoint_id == 0) {
+      log_e("Endpoint ID is not set");
+      return NULL;
+    }
+    endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+    if (endpoint == NULL) {
+      log_e("Endpoint [%d] not found", endpoint_id);
+      return NULL;
+    }
+    cluster_t *cluster = cluster::get(endpoint, cluster_id);
+    if (cluster == NULL) {
+      log_e("Cluster [%d] not found", cluster_id);
+      return NULL;
+    }
+    esp_matter::attribute_t *attribute = attribute::get(cluster, attribute_id);
+    if (attribute == NULL) {
+      log_e("Attribute [%d] not found", attribute_id);
+      return NULL;
+    }
+    return attribute;
+  }
+
+  // get the value of an attribute from its cluster id and attribute it
+  bool getAttributeVal(uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *attrVal) {
+    esp_matter::attribute_t *attribute = getAttribute(cluster_id, attribute_id);
+    if (attribute == NULL) {
+      return false;
+    }
+    if (attribute::get_val(attribute, attrVal) == ESP_OK) {
+      log_v("GET_VAL Success for cluster %d, attribute %d with value %d", cluster_id, attribute_id, attrVal->val.u32);
+      return true;
+    }
+    log_e("GET_VAL FAILED! for cluster %d, attribute %d with value %d", cluster_id, attribute_id, attrVal->val.u32);
+    return false;
+  }
+
+  // set the value of an attribute from its cluster id and attribute it
+  bool setAttributeVal(uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *attrVal) {
+    esp_matter::attribute_t *attribute = getAttribute(cluster_id, attribute_id);
+    if (attribute == NULL) {
+      return false;
+    }
+    if (attribute::set_val(attribute, attrVal) == ESP_OK) {
+      log_v("SET_VAL Success for cluster %d, attribute %d with value %d", cluster_id, attribute_id, attrVal->val.u32);
+      return true;
+    }
+    log_e("SET_VAL FAILED! for cluster %d, attribute %d with value %d", cluster_id, attribute_id, attrVal->val.u32);
+    return false;
+  }
+
+  // update the value of an attribute from its cluster id and attribute it
+  bool updateAttributeVal(uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *attrVal) {
+    if (attribute::update(endpoint_id, cluster_id, attribute_id, attrVal) == ESP_OK) {
+      log_v("Update Success for cluster %d, attribute %d with value %d", cluster_id, attribute_id, attrVal->val.u32);
+      return true;
+    }
+    log_e("Update FAILED! for cluster %d, attribute %d with value %d", cluster_id, attribute_id, attrVal->val.u32);
+    return false;
+  }
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  virtual bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) = 0;
+
+  // This callback is invoked when clients interact with the Identify Cluster of an specific endpoint.
+  bool endpointIdentifyCB(uint16_t endpoint_id, bool identifyIsEnabled) {
+    if (_onEndPointIdentifyCB) {
+      return _onEndPointIdentifyCB(identifyIsEnabled);
+    }
+    return true;
+  }
+  // User callaback for the Identify Cluster functionality
+  using EndPointIdentifyCB = std::function<bool(bool)>;
+  void onIdentify(EndPointIdentifyCB onEndPointIdentifyCB) {
+    _onEndPointIdentifyCB = onEndPointIdentifyCB;
+  }
+
+protected:
+  uint16_t endpoint_id = 0;
+  EndPointIdentifyCB _onEndPointIdentifyCB = NULL;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterColorLight.cpp b/libraries/Matter/src/MatterEndpoints/MatterColorLight.cpp
new file mode 100644
index 00000000000..39d79e86325
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterColorLight.cpp
@@ -0,0 +1,312 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterColorLight.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+// endpoint for color light device
+namespace esp_matter {
+using namespace cluster;
+namespace endpoint {
+namespace rgb_color_light {
+typedef struct config {
+  cluster::descriptor::config_t descriptor;
+  cluster::identify::config_t identify;
+  cluster::groups::config_t groups;
+  cluster::scenes_management::config_t scenes_management;
+  cluster::on_off::config_t on_off;
+  cluster::level_control::config_t level_control;
+  cluster::color_control::config_t color_control;
+} config_t;
+
+uint32_t get_device_type_id() {
+  return ESP_MATTER_EXTENDED_COLOR_LIGHT_DEVICE_TYPE_ID;
+}
+
+uint8_t get_device_type_version() {
+  return ESP_MATTER_EXTENDED_COLOR_LIGHT_DEVICE_TYPE_VERSION;
+}
+
+esp_err_t add(endpoint_t *endpoint, config_t *config) {
+  if (!endpoint) {
+    log_e("Endpoint cannot be NULL");
+    return ESP_ERR_INVALID_ARG;
+  }
+  esp_err_t err = add_device_type(endpoint, get_device_type_id(), get_device_type_version());
+  if (err != ESP_OK) {
+    log_e("Failed to add device type id:%" PRIu32 ",err: %d", get_device_type_id(), err);
+    return err;
+  }
+
+  descriptor::create(endpoint, &(config->descriptor), CLUSTER_FLAG_SERVER);
+  cluster_t *identify_cluster = identify::create(endpoint, &(config->identify), CLUSTER_FLAG_SERVER);
+  identify::command::create_trigger_effect(identify_cluster);
+  groups::create(endpoint, &(config->groups), CLUSTER_FLAG_SERVER);
+  cluster_t *scenes_cluster = scenes_management::create(endpoint, &(config->scenes_management), CLUSTER_FLAG_SERVER);
+  scenes_management::command::create_copy_scene(scenes_cluster);
+  scenes_management::command::create_copy_scene_response(scenes_cluster);
+
+  on_off::create(endpoint, &(config->on_off), CLUSTER_FLAG_SERVER, on_off::feature::lighting::get_id());
+  level_control::create(
+    endpoint, &(config->level_control), CLUSTER_FLAG_SERVER, level_control::feature::on_off::get_id() | level_control::feature::lighting::get_id()
+  );
+  color_control::create(endpoint, &(config->color_control), CLUSTER_FLAG_SERVER, color_control::feature::hue_saturation::get_id());
+  return ESP_OK;
+}
+
+endpoint_t *create(node_t *node, config_t *config, uint8_t flags, void *priv_data) {
+  endpoint_t *endpoint = endpoint::create(node, flags, priv_data);
+  add(endpoint, config);
+  return endpoint;
+}
+}  // namespace rgb_color_light
+}  // namespace endpoint
+}  // namespace esp_matter
+
+bool MatterColorLight::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter RGB Color Light device has not begun.");
+    return false;
+  }
+
+  log_d(
+    "RGB Color Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u, type: %u", endpoint_id, cluster_id, attribute_id, val->val.u32,
+    val->type
+  );
+
+  if (endpoint_id == getEndPointId()) {
+    switch (cluster_id) {
+      case OnOff::Id:
+        if (attribute_id == OnOff::Attributes::OnOff::Id) {
+          log_d("RGB Color Light On/Off State changed to %d", val->val.b);
+          if (_onChangeOnOffCB != NULL) {
+            ret &= _onChangeOnOffCB(val->val.b);
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(val->val.b, colorHSV);
+          }
+          if (ret == true) {
+            onOffState = val->val.b;
+          }
+        }
+        break;
+      case LevelControl::Id:
+        if (attribute_id == LevelControl::Attributes::CurrentLevel::Id) {
+          log_d("RGB Color Light Brightness changed to %d", val->val.u8);
+          if (_onChangeColorCB != NULL) {
+            ret &= _onChangeColorCB({colorHSV.h, colorHSV.s, val->val.u8});
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(onOffState, {colorHSV.h, colorHSV.s, val->val.u8});
+          }
+          if (ret == true) {
+            colorHSV.v = val->val.u8;
+          }
+        }
+        break;
+      case ColorControl::Id:
+      {
+        if (attribute_id != ColorControl::Attributes::CurrentHue::Id && attribute_id != ColorControl::Attributes::CurrentSaturation::Id) {
+          log_i("Color Control Attribute ID [%x] not processed.", attribute_id);
+          break;
+        }
+        espHsvColor_t hsvColor = {colorHSV.h, colorHSV.s, colorHSV.v};
+        if (attribute_id == ColorControl::Attributes::CurrentHue::Id) {
+          log_d("RGB Light Hue changed to %d", val->val.u8);
+          hsvColor.h = val->val.u8;
+        } else {  // attribute_id == ColorControl::Attributes::CurrentSaturation::Id)
+          log_d("RGB Light Saturation changed to %d", val->val.u8);
+          hsvColor.s = val->val.u8;
+        }
+        if (_onChangeColorCB != NULL) {
+          ret &= _onChangeColorCB(hsvColor);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB(onOffState, hsvColor);
+        }
+        if (ret == true) {
+          colorHSV = {hsvColor.h, hsvColor.s, hsvColor.v};
+        }
+        break;
+      }
+    }
+  }
+  return ret;
+}
+
+MatterColorLight::MatterColorLight() {}
+
+MatterColorLight::~MatterColorLight() {
+  end();
+}
+
+bool MatterColorLight::begin(bool initialState, espHsvColor_t _colorHSV) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter RGB Color Light with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  rgb_color_light::config_t light_config;
+  light_config.on_off.on_off = initialState;
+  light_config.on_off.lighting.start_up_on_off = nullptr;
+  onOffState = initialState;
+
+  light_config.level_control.current_level = _colorHSV.v;
+  light_config.level_control.lighting.start_up_current_level = nullptr;
+
+  light_config.color_control.color_mode = (uint8_t)ColorControl::ColorMode::kCurrentHueAndCurrentSaturation;
+  light_config.color_control.enhanced_color_mode = (uint8_t)ColorControl::ColorMode::kCurrentHueAndCurrentSaturation;
+  light_config.color_control.hue_saturation.current_hue = _colorHSV.h;
+  light_config.color_control.hue_saturation.current_saturation = _colorHSV.s;
+  colorHSV = {_colorHSV.h, _colorHSV.s, _colorHSV.v};
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = rgb_color_light::create(node::get(), &light_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create RGB Color light endpoint");
+    return false;
+  }
+
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("RGB Color Light created with endpoint_id %d", getEndPointId());
+
+  /* Mark deferred persistence for some attributes that might be changed rapidly */
+  cluster_t *level_control_cluster = cluster::get(endpoint, LevelControl::Id);
+  esp_matter::attribute_t *current_level_attribute = attribute::get(level_control_cluster, LevelControl::Attributes::CurrentLevel::Id);
+  attribute::set_deferred_persistence(current_level_attribute);
+
+  started = true;
+  return true;
+}
+
+void MatterColorLight::end() {
+  started = false;
+}
+
+bool MatterColorLight::setOnOff(bool newState) {
+  if (!started) {
+    log_e("Matter RGB Color Light device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (onOffState == newState) {
+    return true;
+  }
+
+  onOffState = newState;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, OnOff::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, OnOff::Attributes::OnOff::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.b != onOffState) {
+    val.val.b = onOffState;
+    attribute::update(endpoint_id, OnOff::Id, OnOff::Attributes::OnOff::Id, &val);
+  }
+  return true;
+}
+
+void MatterColorLight::updateAccessory() {
+  if (_onChangeCB != NULL) {
+    _onChangeCB(onOffState, colorHSV);
+  }
+}
+
+bool MatterColorLight::getOnOff() {
+  return onOffState;
+}
+
+bool MatterColorLight::toggle() {
+  return setOnOff(!onOffState);
+}
+
+bool MatterColorLight::setColorRGB(espRgbColor_t _rgbColor) {
+  return setColorHSV(espRgbColorToHsvColor(_rgbColor));
+}
+
+espRgbColor_t MatterColorLight::getColorRGB() {
+  return espHsvColorToRgbColor(colorHSV);
+}
+
+bool MatterColorLight::setColorHSV(espHsvColor_t _hsvColor) {
+
+  if (!started) {
+    log_w("Matter RGB Color Light device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (colorHSV.h == _hsvColor.h && colorHSV.s == _hsvColor.s && colorHSV.v == _hsvColor.v) {
+    return true;
+  }
+
+  colorHSV = {_hsvColor.h, _hsvColor.s, _hsvColor.v};
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, ColorControl::Id);
+  // update hue
+  esp_matter::attribute_t *attribute = attribute::get(cluster, ColorControl::Attributes::CurrentHue::Id);
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+  if (val.val.u8 != colorHSV.h) {
+    val.val.u8 = colorHSV.h;
+    attribute::update(endpoint_id, ColorControl::Id, ColorControl::Attributes::CurrentHue::Id, &val);
+  }
+  // update saturation
+  attribute = attribute::get(cluster, ColorControl::Attributes::CurrentSaturation::Id);
+  val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+  if (val.val.u8 != colorHSV.s) {
+    val.val.u8 = colorHSV.s;
+    attribute::update(endpoint_id, ColorControl::Id, ColorControl::Attributes::CurrentSaturation::Id, &val);
+  }
+  // update value (brightness)
+  cluster = cluster::get(endpoint, LevelControl::Id);
+  attribute = attribute::get(cluster, LevelControl::Attributes::CurrentLevel::Id);
+  val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+  if (val.val.u8 != colorHSV.v) {
+    val.val.u8 = colorHSV.v;
+    attribute::update(endpoint_id, LevelControl::Id, LevelControl::Attributes::CurrentLevel::Id, &val);
+  }
+  return true;
+}
+
+espHsvColor_t MatterColorLight::getColorHSV() {
+  return colorHSV;
+}
+
+MatterColorLight::operator bool() {
+  return getOnOff();
+}
+
+void MatterColorLight::operator=(bool newState) {
+  setOnOff(newState);
+}
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterColorLight.h b/libraries/Matter/src/MatterEndpoints/MatterColorLight.h
new file mode 100644
index 00000000000..99449addd50
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterColorLight.h
@@ -0,0 +1,75 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterColorLight : public MatterEndPoint {
+public:
+  MatterColorLight();
+  ~MatterColorLight();
+  // default initial state is off, color is red 12% intensity HSV(0, 254, 31)
+  virtual bool begin(bool initialState = false, espHsvColor_t colorHSV = {0, 254, 31});
+  // this will just stop processing Light Matter events
+  void end();
+
+  bool setOnOff(bool newState);  // returns true if successful
+  bool getOnOff();               // returns current light state
+  bool toggle();                 // returns true if successful
+
+  bool setColorRGB(espRgbColor_t rgbColor);  // returns true if successful
+  espRgbColor_t getColorRGB();               // returns current RGB Color
+  bool setColorHSV(espHsvColor_t hsvColor);  // returns true if successful
+  espHsvColor_t getColorHSV();               // returns current HSV Color
+
+  // User Callback for whenever the Light On/Off state is changed by the Matter Controller
+  using EndPointOnOffCB = std::function<bool(bool)>;
+  void onChangeOnOff(EndPointOnOffCB onChangeCB) {
+    _onChangeOnOffCB = onChangeCB;
+  }
+  // User Callback for whenever the HSV Color value is changed by the Matter Controller
+  using EndPointRGBColorCB = std::function<bool(espHsvColor_t)>;
+  void onChangeColorHSV(EndPointRGBColorCB onChangeCB) {
+    _onChangeColorCB = onChangeCB;
+  }
+
+  // User Callback for whenever any parameter is changed by the Matter Controller
+  using EndPointCB = std::function<bool(bool, espHsvColor_t)>;
+  void onChange(EndPointCB onChangeCB) {
+    _onChangeCB = onChangeCB;
+  }
+
+  // used to update the state of the light using the current Matter Light internal state
+  // It is necessary to set a user callback function using onChange() to handle the physical light state
+  void updateAccessory();
+
+  operator bool();             // returns current on/off light state
+  void operator=(bool state);  // turns light on or off
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  bool onOffState = false;             // default initial state is off, but it can be changed by begin(bool)
+  espHsvColor_t colorHSV = {0, 0, 0};  // default initial color HSV is black, but it can be changed by begin(bool, espHsvColor_t)
+  EndPointOnOffCB _onChangeOnOffCB = NULL;
+  EndPointRGBColorCB _onChangeColorCB = NULL;
+  EndPointCB _onChangeCB = NULL;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterColorTemperatureLight.cpp b/libraries/Matter/src/MatterEndpoints/MatterColorTemperatureLight.cpp
new file mode 100644
index 00000000000..3c4fccfa046
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterColorTemperatureLight.cpp
@@ -0,0 +1,250 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterColorTemperatureLight.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+bool MatterColorTemperatureLight::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter Temperature Light device has not begun.");
+    return false;
+  }
+
+  log_d("Temperature Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+
+  if (endpoint_id == getEndPointId()) {
+    switch (cluster_id) {
+      case OnOff::Id:
+        if (attribute_id == OnOff::Attributes::OnOff::Id) {
+          log_d("Temperature Light On/Off State changed to %d", val->val.b);
+          if (_onChangeOnOffCB != NULL) {
+            ret &= _onChangeOnOffCB(val->val.b);
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(val->val.b, brightnessLevel, colorTemperatureLevel);
+          }
+          if (ret == true) {
+            onOffState = val->val.b;
+          }
+        }
+        break;
+      case LevelControl::Id:
+        if (attribute_id == LevelControl::Attributes::CurrentLevel::Id) {
+          log_d("Temperature Light Brightness changed to %d", val->val.u8);
+          if (_onChangeBrightnessCB != NULL) {
+            ret &= _onChangeBrightnessCB(val->val.u8);
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(onOffState, val->val.u8, colorTemperatureLevel);
+          }
+          if (ret == true) {
+            brightnessLevel = val->val.u8;
+          }
+        }
+        break;
+      case ColorControl::Id:
+        if (attribute_id == ColorControl::Attributes::ColorTemperatureMireds::Id) {
+          log_d("Temperature Light Temperature changed to %d", val->val.u16);
+          if (_onChangeTemperatureCB != NULL) {
+            ret &= _onChangeTemperatureCB(val->val.u16);
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(onOffState, brightnessLevel, val->val.u16);
+          }
+          if (ret == true) {
+            colorTemperatureLevel = val->val.u16;
+          }
+        }
+        break;
+    }
+  }
+  return ret;
+}
+
+MatterColorTemperatureLight::MatterColorTemperatureLight() {}
+
+MatterColorTemperatureLight::~MatterColorTemperatureLight() {
+  end();
+}
+
+bool MatterColorTemperatureLight::begin(bool initialState, uint8_t brightness, uint16_t ColorTemperature) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter Temperature Light with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  color_temperature_light::config_t light_config;
+  light_config.on_off.on_off = initialState;
+  light_config.on_off.lighting.start_up_on_off = nullptr;
+  onOffState = initialState;
+
+  light_config.level_control.current_level = brightness;
+  light_config.level_control.lighting.start_up_current_level = nullptr;
+  brightnessLevel = brightness;
+
+  light_config.color_control.color_mode = (uint8_t)ColorControl::ColorMode::kColorTemperature;
+  light_config.color_control.enhanced_color_mode = (uint8_t)ColorControl::ColorMode::kColorTemperature;
+  light_config.color_control.color_temperature.color_temperature_mireds = ColorTemperature;
+  light_config.color_control.color_temperature.startup_color_temperature_mireds = nullptr;
+  colorTemperatureLevel = ColorTemperature;
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = color_temperature_light::create(node::get(), &light_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create Temperature Light endpoint");
+    return false;
+  }
+
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Temperature Light created with endpoint_id %d", getEndPointId());
+
+  /* Mark deferred persistence for some attributes that might be changed rapidly */
+  cluster_t *level_control_cluster = cluster::get(endpoint, LevelControl::Id);
+  esp_matter::attribute_t *current_level_attribute = attribute::get(level_control_cluster, LevelControl::Attributes::CurrentLevel::Id);
+  attribute::set_deferred_persistence(current_level_attribute);
+
+  cluster_t *color_control_cluster = cluster::get(endpoint, ColorControl::Id);
+  esp_matter::attribute_t *color_temp_attribute = attribute::get(color_control_cluster, ColorControl::Attributes::ColorTemperatureMireds::Id);
+  attribute::set_deferred_persistence(color_temp_attribute);
+
+  started = true;
+  return true;
+}
+
+void MatterColorTemperatureLight::end() {
+  started = false;
+}
+
+bool MatterColorTemperatureLight::setOnOff(bool newState) {
+  if (!started) {
+    log_e("Matter Temperature Light device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (onOffState == newState) {
+    return true;
+  }
+
+  onOffState = newState;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, OnOff::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, OnOff::Attributes::OnOff::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.b != onOffState) {
+    val.val.b = onOffState;
+    attribute::update(endpoint_id, OnOff::Id, OnOff::Attributes::OnOff::Id, &val);
+  }
+  return true;
+}
+
+void MatterColorTemperatureLight::updateAccessory() {
+  if (_onChangeCB != NULL) {
+    _onChangeCB(onOffState, brightnessLevel, colorTemperatureLevel);
+  }
+}
+
+bool MatterColorTemperatureLight::getOnOff() {
+  return onOffState;
+}
+
+bool MatterColorTemperatureLight::toggle() {
+  return setOnOff(!onOffState);
+}
+
+bool MatterColorTemperatureLight::setBrightness(uint8_t newBrightness) {
+  if (!started) {
+    log_w("Matter Temperature Light device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (brightnessLevel == newBrightness) {
+    return true;
+  }
+
+  brightnessLevel = newBrightness;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, LevelControl::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, LevelControl::Attributes::CurrentLevel::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.u8 != brightnessLevel) {
+    val.val.u8 = brightnessLevel;
+    attribute::update(endpoint_id, LevelControl::Id, LevelControl::Attributes::CurrentLevel::Id, &val);
+  }
+  return true;
+}
+
+uint8_t MatterColorTemperatureLight::getBrightness() {
+  return brightnessLevel;
+}
+
+bool MatterColorTemperatureLight::setColorTemperature(uint16_t newTemperature) {
+  if (!started) {
+    log_w("Matter Temperature Light device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (colorTemperatureLevel == newTemperature) {
+    return true;
+  }
+
+  colorTemperatureLevel = newTemperature;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, ColorControl::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, ColorControl::Attributes::ColorTemperatureMireds::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.u16 != colorTemperatureLevel) {
+    val.val.u16 = colorTemperatureLevel;
+    attribute::update(endpoint_id, ColorControl::Id, ColorControl::Attributes::ColorTemperatureMireds::Id, &val);
+  }
+  return true;
+}
+
+uint16_t MatterColorTemperatureLight::getColorTemperature() {
+  return colorTemperatureLevel;
+}
+
+MatterColorTemperatureLight::operator bool() {
+  return getOnOff();
+}
+
+void MatterColorTemperatureLight::operator=(bool newState) {
+  setOnOff(newState);
+}
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterColorTemperatureLight.h b/libraries/Matter/src/MatterEndpoints/MatterColorTemperatureLight.h
new file mode 100644
index 00000000000..539bc386e92
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterColorTemperatureLight.h
@@ -0,0 +1,89 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterColorTemperatureLight : public MatterEndPoint {
+public:
+  static const uint8_t MAX_BRIGHTNESS = 255;
+  static const uint16_t MAX_COLOR_TEMPERATURE = 500;
+  static const uint16_t MIN_COLOR_TEMPERATURE = 100;
+
+  MatterColorTemperatureLight();
+  ~MatterColorTemperatureLight();
+  // default initial state is off, brightness is 64 (25%) and temperature is 370 (Soft White)
+  virtual bool begin(bool initialState = false, uint8_t brightness = 64, uint16_t colorTemperature = 370);
+  // this will just stop processing Light Matter events
+  void end();
+
+  bool setOnOff(bool newState);  // returns true if successful
+  bool getOnOff();               // returns current light state
+  bool toggle();                 // returns true if successful
+
+  bool setBrightness(uint8_t newBrightness);  // returns true if successful
+  uint8_t getBrightness();                    // returns current brightness
+
+  bool setColorTemperature(uint16_t newTemperature);  // returns true if successful
+  uint16_t getColorTemperature();                     // returns current temperature
+
+  // User Callback for whenever the Light On/Off state is changed by the Matter Controller
+  using EndPointOnOffCB = std::function<bool(bool)>;
+  void onChangeOnOff(EndPointOnOffCB onChangeCB) {
+    _onChangeOnOffCB = onChangeCB;
+  }
+
+  // User Callback for whenever the Light brightness value [0..255] is changed by the Matter Controller
+  using EndPointBrightnessCB = std::function<bool(uint8_t)>;
+  void onChangeBrightness(EndPointBrightnessCB onChangeCB) {
+    _onChangeBrightnessCB = onChangeCB;
+  }
+
+  // User Callbqck for whenever the Light temperature value is changed by the Matter Controller
+  using EndPointTemperatureCB = std::function<bool(uint16_t)>;
+  void onChangeColorTemperature(EndPointTemperatureCB onChangeCB) {
+    _onChangeTemperatureCB = onChangeCB;
+  }
+
+  // User Callback for whenever any parameter is changed by the Matter Controller
+  using EndPointCB = std::function<bool(bool, uint8_t, uint16_t)>;
+  void onChange(EndPointCB onChangeCB) {
+    _onChangeCB = onChangeCB;
+  }
+
+  // used to update the state of the light using the current Matter Light internal state
+  // It is necessary to set a user callback function using onChange() to handle the physical light state
+  void updateAccessory();
+
+  operator bool();             // returns current on/off light state
+  void operator=(bool state);  // turns light on or off
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  bool onOffState = false;             // default initial state is off, but it can be changed by begin(bool)
+  uint8_t brightnessLevel = 0;         // default initial brightness is 0, but it can be changed by begin(bool, uint8_t)
+  uint16_t colorTemperatureLevel = 0;  // default initial color temperature is 0, but it can be changed by begin(bool, uint8_t, uint16_t)
+  EndPointOnOffCB _onChangeOnOffCB = NULL;
+  EndPointBrightnessCB _onChangeBrightnessCB = NULL;
+  EndPointTemperatureCB _onChangeTemperatureCB = NULL;
+  EndPointCB _onChangeCB = NULL;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterContactSensor.cpp b/libraries/Matter/src/MatterEndpoints/MatterContactSensor.cpp
new file mode 100644
index 00000000000..17b0fe7a247
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterContactSensor.cpp
@@ -0,0 +1,103 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterContactSensor.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+bool MatterContactSensor::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter Contact Sensor device has not begun.");
+    return false;
+  }
+
+  log_d("Contact Sensor Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+  return ret;
+}
+
+MatterContactSensor::MatterContactSensor() {}
+
+MatterContactSensor::~MatterContactSensor() {
+  end();
+}
+
+bool MatterContactSensor::begin(bool _contactState) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter Contact Sensor with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  contact_sensor::config_t contact_sensor_config;
+  contact_sensor_config.boolean_state.state_value = _contactState;
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = contact_sensor::create(node::get(), &contact_sensor_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create Contact Sensor endpoint");
+    return false;
+  }
+  contactState = _contactState;
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Contact Sensor created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterContactSensor::end() {
+  started = false;
+}
+
+bool MatterContactSensor::setContact(bool _contactState) {
+  if (!started) {
+    log_e("Matter Contact Sensor device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (contactState == _contactState) {
+    return true;
+  }
+
+  esp_matter_attr_val_t contactVal = esp_matter_invalid(NULL);
+
+  if (!getAttributeVal(BooleanState::Id, BooleanState::Attributes::StateValue::Id, &contactVal)) {
+    log_e("Failed to get Contact Sensor Attribute.");
+    return false;
+  }
+  if (contactVal.val.u8 != _contactState) {
+    contactVal.val.u8 = _contactState;
+    bool ret;
+    ret = updateAttributeVal(BooleanState::Id, BooleanState::Attributes::StateValue::Id, &contactVal);
+    if (!ret) {
+      log_e("Failed to update Contact Sensor Attribute.");
+      return false;
+    }
+    contactState = _contactState;
+  }
+  log_v("Contact Sensor set to %s", _contactState ? "Closed" : "Open");
+
+  return true;
+}
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterContactSensor.h b/libraries/Matter/src/MatterEndpoints/MatterContactSensor.h
new file mode 100644
index 00000000000..257da785e53
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterContactSensor.h
@@ -0,0 +1,54 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterContactSensor : public MatterEndPoint {
+public:
+  MatterContactSensor();
+  ~MatterContactSensor();
+  // begin Matter Contact Sensor endpoint with initial contact state
+  bool begin(bool _contactState = false);
+  // this will just stop processing Contact Sensor Matter events
+  void end();
+
+  // set the contact state
+  bool setContact(bool _contactState);
+  // returns the contact state
+  bool getContact() {
+    return contactState;
+  }
+
+  // bool conversion operator
+  void operator=(bool _contactState) {
+    setContact(_contactState);
+  }
+  // bool conversion operator
+  operator bool() {
+    return getContact();
+  }
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  bool contactState = false;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterDimmableLight.cpp b/libraries/Matter/src/MatterEndpoints/MatterDimmableLight.cpp
new file mode 100644
index 00000000000..5167cf1f21c
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterDimmableLight.cpp
@@ -0,0 +1,194 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterDimmableLight.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+bool MatterDimmableLight::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter DimmableLight device has not begun.");
+    return false;
+  }
+
+  log_d("Dimmable Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+
+  if (endpoint_id == getEndPointId()) {
+    switch (cluster_id) {
+      case OnOff::Id:
+        if (attribute_id == OnOff::Attributes::OnOff::Id) {
+          log_d("DimmableLight On/Off State changed to %d", val->val.b);
+          if (_onChangeOnOffCB != NULL) {
+            ret &= _onChangeOnOffCB(val->val.b);
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(val->val.b, brightnessLevel);
+          }
+          if (ret == true) {
+            onOffState = val->val.b;
+          }
+        }
+        break;
+      case LevelControl::Id:
+        if (attribute_id == LevelControl::Attributes::CurrentLevel::Id) {
+          log_d("DimmableLight Brightness changed to %d", val->val.u8);
+          if (_onChangeBrightnessCB != NULL) {
+            ret &= _onChangeBrightnessCB(val->val.u8);
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(onOffState, val->val.u8);
+          }
+          if (ret == true) {
+            brightnessLevel = val->val.u8;
+          }
+        }
+        break;
+    }
+  }
+  return ret;
+}
+
+MatterDimmableLight::MatterDimmableLight() {}
+
+MatterDimmableLight::~MatterDimmableLight() {
+  end();
+}
+
+bool MatterDimmableLight::begin(bool initialState, uint8_t brightness) {
+  ArduinoMatter::_init();
+  if (getEndPointId() != 0) {
+    log_e("Matter Dimmable Light with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  dimmable_light::config_t light_config;
+  light_config.on_off.on_off = initialState;
+  light_config.on_off.lighting.start_up_on_off = nullptr;
+  onOffState = initialState;
+
+  light_config.level_control.current_level = brightness;
+  light_config.level_control.lighting.start_up_current_level = nullptr;
+  brightnessLevel = brightness;
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = dimmable_light::create(node::get(), &light_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create dimmable light endpoint");
+    return false;
+  }
+
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Dimmable Light created with endpoint_id %d", getEndPointId());
+
+  /* Mark deferred persistence for some attributes that might be changed rapidly */
+  cluster_t *level_control_cluster = cluster::get(endpoint, LevelControl::Id);
+  esp_matter::attribute_t *current_level_attribute = attribute::get(level_control_cluster, LevelControl::Attributes::CurrentLevel::Id);
+  attribute::set_deferred_persistence(current_level_attribute);
+
+  started = true;
+  return true;
+}
+
+void MatterDimmableLight::end() {
+  started = false;
+}
+
+bool MatterDimmableLight::setOnOff(bool newState) {
+  if (!started) {
+    log_e("Matter Dimmable Light device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (onOffState == newState) {
+    return true;
+  }
+
+  onOffState = newState;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, OnOff::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, OnOff::Attributes::OnOff::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.b != onOffState) {
+    val.val.b = onOffState;
+    attribute::update(endpoint_id, OnOff::Id, OnOff::Attributes::OnOff::Id, &val);
+  }
+  return true;
+}
+
+void MatterDimmableLight::updateAccessory() {
+  if (_onChangeCB != NULL) {
+    _onChangeCB(onOffState, brightnessLevel);
+  }
+}
+
+bool MatterDimmableLight::getOnOff() {
+  return onOffState;
+}
+
+bool MatterDimmableLight::toggle() {
+  return setOnOff(!onOffState);
+}
+
+bool MatterDimmableLight::setBrightness(uint8_t newBrightness) {
+  if (!started) {
+    log_w("Matter Dimmable Light device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (brightnessLevel == newBrightness) {
+    return true;
+  }
+
+  brightnessLevel = newBrightness;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, LevelControl::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, LevelControl::Attributes::CurrentLevel::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.u8 != brightnessLevel) {
+    val.val.u8 = brightnessLevel;
+    attribute::update(endpoint_id, LevelControl::Id, LevelControl::Attributes::CurrentLevel::Id, &val);
+  }
+  return true;
+}
+
+uint8_t MatterDimmableLight::getBrightness() {
+  return brightnessLevel;
+}
+
+MatterDimmableLight::operator bool() {
+  return getOnOff();
+}
+
+void MatterDimmableLight::operator=(bool newState) {
+  setOnOff(newState);
+}
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterDimmableLight.h b/libraries/Matter/src/MatterEndpoints/MatterDimmableLight.h
new file mode 100644
index 00000000000..4497edd2fe2
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterDimmableLight.h
@@ -0,0 +1,75 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterDimmableLight : public MatterEndPoint {
+public:
+  static const uint8_t MAX_BRIGHTNESS = 255;
+
+  MatterDimmableLight();
+  ~MatterDimmableLight();
+  // default initial state is off and brightness is 64 (25%)
+  virtual bool begin(bool initialState = false, uint8_t brightness = 64);
+  // this will just stop processing Light Matter events
+  void end();
+
+  bool setOnOff(bool newState);  // returns true if successful
+  bool getOnOff();               // returns current light state
+  bool toggle();                 // returns true if successful
+
+  bool setBrightness(uint8_t newBrightness);  // returns true if successful
+  uint8_t getBrightness();                    // returns current brightness
+
+  // User Callback for whenever the Light On/Off state is changed by the Matter Controller
+  using EndPointOnOffCB = std::function<bool(bool)>;
+  void onChangeOnOff(EndPointOnOffCB onChangeCB) {
+    _onChangeOnOffCB = onChangeCB;
+  }
+
+  // User Callback for whenever the Light brightness value [0..255] is changed by the Matter Controller
+  using EndPointBrightnessCB = std::function<bool(uint8_t)>;
+  void onChangeBrightness(EndPointBrightnessCB onChangeCB) {
+    _onChangeBrightnessCB = onChangeCB;
+  }
+
+  // User Callback for whenever any parameter is changed by the Matter Controller
+  using EndPointCB = std::function<bool(bool, uint8_t)>;
+  void onChange(EndPointCB onChangeCB) {
+    _onChangeCB = onChangeCB;
+  }
+
+  // used to update the state of the light using the current Matter Light internal state
+  // It is necessary to set a user callback function using onChange() to handle the physical light state
+  void updateAccessory();
+
+  operator bool();             // returns current on/off light state
+  void operator=(bool state);  // turns light on or off
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  bool onOffState = false;      // default initial state is off, but it can be changed by begin(bool)
+  uint8_t brightnessLevel = 0;  // default initial brightness is 0, but it can be changed by begin(bool, uint8_t)
+  EndPointOnOffCB _onChangeOnOffCB = NULL;
+  EndPointBrightnessCB _onChangeBrightnessCB = NULL;
+  EndPointCB _onChangeCB = NULL;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterEnhancedColorLight.cpp b/libraries/Matter/src/MatterEndpoints/MatterEnhancedColorLight.cpp
new file mode 100644
index 00000000000..9b245fb9408
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterEnhancedColorLight.cpp
@@ -0,0 +1,394 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterEnhancedColorLight.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+// endpoint for enhanced color light device
+namespace esp_matter {
+using namespace cluster;
+namespace endpoint {
+namespace enhanced_color_light {
+typedef struct config {
+  cluster::descriptor::config_t descriptor;
+  cluster::identify::config_t identify;
+  cluster::groups::config_t groups;
+  cluster::scenes_management::config_t scenes_management;
+  cluster::on_off::config_t on_off;
+  cluster::level_control::config_t level_control;
+  cluster::color_control::config_t color_control;
+} config_t;
+
+uint32_t get_device_type_id() {
+  return ESP_MATTER_EXTENDED_COLOR_LIGHT_DEVICE_TYPE_ID;
+}
+
+uint8_t get_device_type_version() {
+  return ESP_MATTER_EXTENDED_COLOR_LIGHT_DEVICE_TYPE_VERSION;
+}
+
+esp_err_t add(endpoint_t *endpoint, config_t *config) {
+  if (!endpoint) {
+    log_e("Endpoint cannot be NULL");
+    return ESP_ERR_INVALID_ARG;
+  }
+  esp_err_t err = add_device_type(endpoint, get_device_type_id(), get_device_type_version());
+  if (err != ESP_OK) {
+    log_e("Failed to add device type id:%" PRIu32 ",err: %d", get_device_type_id(), err);
+    return err;
+  }
+
+  descriptor::create(endpoint, &(config->descriptor), CLUSTER_FLAG_SERVER);
+  cluster_t *identify_cluster = identify::create(endpoint, &(config->identify), CLUSTER_FLAG_SERVER);
+  identify::command::create_trigger_effect(identify_cluster);
+  groups::create(endpoint, &(config->groups), CLUSTER_FLAG_SERVER);
+  cluster_t *scenes_cluster = scenes_management::create(endpoint, &(config->scenes_management), CLUSTER_FLAG_SERVER);
+  scenes_management::command::create_copy_scene(scenes_cluster);
+  scenes_management::command::create_copy_scene_response(scenes_cluster);
+
+  on_off::create(endpoint, &(config->on_off), CLUSTER_FLAG_SERVER, on_off::feature::lighting::get_id());
+  level_control::create(
+    endpoint, &(config->level_control), CLUSTER_FLAG_SERVER, level_control::feature::on_off::get_id() | level_control::feature::lighting::get_id()
+  );
+  color_control::create(
+    endpoint, &(config->color_control), CLUSTER_FLAG_SERVER,
+    color_control::feature::hue_saturation::get_id() | color_control::feature::color_temperature::get_id()
+  );
+  return ESP_OK;
+}
+
+endpoint_t *create(node_t *node, config_t *config, uint8_t flags, void *priv_data) {
+  endpoint_t *endpoint = endpoint::create(node, flags, priv_data);
+  add(endpoint, config);
+  return endpoint;
+}
+}  // namespace enhanced_color_light
+}  // namespace endpoint
+}  // namespace esp_matter
+
+bool MatterEnhancedColorLight::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter Enhanced ColorLight device has not begun.");
+    return false;
+  }
+
+  log_d(
+    "Enhanced ColorAttr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u, type: %u", endpoint_id, cluster_id, attribute_id, val->val.u32,
+    val->type
+  );
+
+  if (endpoint_id == getEndPointId()) {
+    switch (cluster_id) {
+      case OnOff::Id:
+        if (attribute_id == OnOff::Attributes::OnOff::Id) {
+          log_d("Enhanced ColorLight On/Off State changed to %d", val->val.b);
+          if (_onChangeOnOffCB != NULL) {
+            ret &= _onChangeOnOffCB(val->val.b);
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(val->val.b, colorHSV, brightnessLevel, colorTemperatureLevel);
+          }
+          if (ret == true) {
+            onOffState = val->val.b;
+          }
+        }
+        break;
+      case LevelControl::Id:
+        if (attribute_id == LevelControl::Attributes::CurrentLevel::Id) {
+          log_d("Enhanced ColorLight Brightness changed to %d", val->val.u8);
+          if (_onChangeBrightnessCB != NULL) {
+            ret &= _onChangeBrightnessCB(val->val.u8);
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(onOffState, colorHSV, val->val.u8, colorTemperatureLevel);
+          }
+          if (ret == true) {
+            colorHSV.v = val->val.u8;
+          }
+        }
+        break;
+      case ColorControl::Id:
+      {
+        if (attribute_id == ColorControl::Attributes::ColorTemperatureMireds::Id) {
+          log_d("Enhanced ColorLight Temperature changed to %d", val->val.u16);
+          if (_onChangeTemperatureCB != NULL) {
+            ret &= _onChangeTemperatureCB(val->val.u16);
+          }
+          if (_onChangeCB != NULL) {
+            ret &= _onChangeCB(onOffState, colorHSV, brightnessLevel, val->val.u16);
+          }
+          if (ret == true) {
+            colorTemperatureLevel = val->val.u16;
+          }
+          break;
+        }
+        if (attribute_id != ColorControl::Attributes::CurrentHue::Id && attribute_id != ColorControl::Attributes::CurrentSaturation::Id) {
+          log_i("Color Control Attribute ID [%x] not processed.", attribute_id);
+          break;
+        }
+        espHsvColor_t hsvColor = {colorHSV.h, colorHSV.s, colorHSV.v};
+        if (attribute_id == ColorControl::Attributes::CurrentHue::Id) {
+          log_d("Enhanced ColorLight Hue changed to %d", val->val.u8);
+          hsvColor.h = val->val.u8;
+        } else {  // attribute_id == ColorControl::Attributes::CurrentSaturation::Id)
+          log_d("Enhanced ColorLight Saturation changed to %d", val->val.u8);
+          hsvColor.s = val->val.u8;
+        }
+        if (_onChangeColorCB != NULL) {
+          ret &= _onChangeColorCB(hsvColor);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB(onOffState, hsvColor, brightnessLevel, colorTemperatureLevel);
+        }
+        if (ret == true) {
+          colorHSV = {hsvColor.h, hsvColor.s, hsvColor.v};
+        }
+        break;
+      }
+    }
+  }
+  return ret;
+}
+
+MatterEnhancedColorLight::MatterEnhancedColorLight() {}
+
+MatterEnhancedColorLight::~MatterEnhancedColorLight() {
+  end();
+}
+
+bool MatterEnhancedColorLight::begin(bool initialState, espHsvColor_t _colorHSV, uint8_t brightness, uint16_t ColorTemperature) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter Enhanced ColorLight with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  enhanced_color_light::config_t light_config;
+  light_config.on_off.on_off = initialState;
+  light_config.on_off.lighting.start_up_on_off = nullptr;
+  onOffState = initialState;
+
+  light_config.level_control.current_level = brightness;
+  light_config.level_control.lighting.start_up_current_level = nullptr;
+
+  light_config.color_control.enhanced_color_mode = (uint8_t)ColorControl::ColorMode::kColorTemperature;
+  light_config.color_control.color_temperature.color_temperature_mireds = ColorTemperature;
+  light_config.color_control.color_temperature.startup_color_temperature_mireds = nullptr;
+  colorTemperatureLevel = ColorTemperature;
+
+  light_config.color_control.color_mode = (uint8_t)ColorControl::ColorMode::kCurrentHueAndCurrentSaturation;
+  light_config.color_control.hue_saturation.current_hue = _colorHSV.h;
+  light_config.color_control.hue_saturation.current_saturation = _colorHSV.s;
+  colorHSV = {_colorHSV.h, _colorHSV.s, _colorHSV.v};
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = enhanced_color_light::create(node::get(), &light_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create Enhanced ColorLight endpoint");
+    return false;
+  }
+
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Enhanced ColorLight created with endpoint_id %d", getEndPointId());
+
+  /* Mark deferred persistence for some attributes that might be changed rapidly */
+  cluster_t *level_control_cluster = cluster::get(endpoint, LevelControl::Id);
+  esp_matter::attribute_t *current_level_attribute = attribute::get(level_control_cluster, LevelControl::Attributes::CurrentLevel::Id);
+  attribute::set_deferred_persistence(current_level_attribute);
+
+  started = true;
+  return true;
+}
+
+void MatterEnhancedColorLight::end() {
+  started = false;
+}
+
+bool MatterEnhancedColorLight::setOnOff(bool newState) {
+  if (!started) {
+    log_e("Matter Enhanced ColorLight device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (onOffState == newState) {
+    return true;
+  }
+
+  onOffState = newState;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, OnOff::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, OnOff::Attributes::OnOff::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.b != onOffState) {
+    val.val.b = onOffState;
+    attribute::update(endpoint_id, OnOff::Id, OnOff::Attributes::OnOff::Id, &val);
+  }
+  return true;
+}
+
+void MatterEnhancedColorLight::updateAccessory() {
+  if (_onChangeCB != NULL) {
+    _onChangeCB(onOffState, colorHSV, brightnessLevel, colorTemperatureLevel);
+  }
+}
+
+bool MatterEnhancedColorLight::getOnOff() {
+  return onOffState;
+}
+
+bool MatterEnhancedColorLight::toggle() {
+  return setOnOff(!onOffState);
+}
+
+bool MatterEnhancedColorLight::setBrightness(uint8_t newBrightness) {
+  if (!started) {
+    log_w("Matter Enhanced ColorLight device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (brightnessLevel == newBrightness) {
+    return true;
+  }
+
+  brightnessLevel = newBrightness;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, LevelControl::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, LevelControl::Attributes::CurrentLevel::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.u8 != brightnessLevel) {
+    val.val.u8 = brightnessLevel;
+    attribute::update(endpoint_id, LevelControl::Id, LevelControl::Attributes::CurrentLevel::Id, &val);
+  }
+  return true;
+}
+
+uint8_t MatterEnhancedColorLight::getBrightness() {
+  return brightnessLevel;
+}
+
+bool MatterEnhancedColorLight::setColorTemperature(uint16_t newTemperature) {
+  if (!started) {
+    log_w("Matter Enhanced ColorLight device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (colorTemperatureLevel == newTemperature) {
+    return true;
+  }
+
+  colorTemperatureLevel = newTemperature;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, ColorControl::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, ColorControl::Attributes::ColorTemperatureMireds::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.u16 != colorTemperatureLevel) {
+    val.val.u16 = colorTemperatureLevel;
+    attribute::update(endpoint_id, ColorControl::Id, ColorControl::Attributes::ColorTemperatureMireds::Id, &val);
+  }
+  return true;
+}
+
+uint16_t MatterEnhancedColorLight::getColorTemperature() {
+  return colorTemperatureLevel;
+}
+
+bool MatterEnhancedColorLight::setColorRGB(espRgbColor_t _rgbColor) {
+  return setColorHSV(espRgbColorToHsvColor(_rgbColor));
+}
+
+espRgbColor_t MatterEnhancedColorLight::getColorRGB() {
+  return espHsvColorToRgbColor(colorHSV);
+}
+
+bool MatterEnhancedColorLight::setColorHSV(espHsvColor_t _hsvColor) {
+
+  if (!started) {
+    log_w("Matter Enhanced ColorLight device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (colorHSV.h == _hsvColor.h && colorHSV.s == _hsvColor.s && colorHSV.v == _hsvColor.v) {
+    return true;
+  }
+
+  colorHSV = {_hsvColor.h, _hsvColor.s, _hsvColor.v};
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, ColorControl::Id);
+  // update hue
+  esp_matter::attribute_t *attribute = attribute::get(cluster, ColorControl::Attributes::CurrentHue::Id);
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+  if (val.val.u8 != colorHSV.h) {
+    val.val.u8 = colorHSV.h;
+    attribute::update(endpoint_id, ColorControl::Id, ColorControl::Attributes::CurrentHue::Id, &val);
+  }
+  // update saturation
+  attribute = attribute::get(cluster, ColorControl::Attributes::CurrentSaturation::Id);
+  val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+  if (val.val.u8 != colorHSV.s) {
+    val.val.u8 = colorHSV.s;
+    attribute::update(endpoint_id, ColorControl::Id, ColorControl::Attributes::CurrentSaturation::Id, &val);
+  }
+  // update value (brightness)
+  cluster = cluster::get(endpoint, LevelControl::Id);
+  attribute = attribute::get(cluster, LevelControl::Attributes::CurrentLevel::Id);
+  val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+  if (val.val.u8 != colorHSV.v) {
+    val.val.u8 = colorHSV.v;
+    attribute::update(endpoint_id, LevelControl::Id, LevelControl::Attributes::CurrentLevel::Id, &val);
+  }
+  return true;
+}
+
+espHsvColor_t MatterEnhancedColorLight::getColorHSV() {
+  return colorHSV;
+}
+
+MatterEnhancedColorLight::operator bool() {
+  return getOnOff();
+}
+
+void MatterEnhancedColorLight::operator=(bool newState) {
+  setOnOff(newState);
+}
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterEnhancedColorLight.h b/libraries/Matter/src/MatterEndpoints/MatterEnhancedColorLight.h
new file mode 100644
index 00000000000..a4baef968a4
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterEnhancedColorLight.h
@@ -0,0 +1,102 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterEnhancedColorLight : public MatterEndPoint {
+public:
+  static const uint8_t MAX_BRIGHTNESS = 255;
+  static const uint16_t MAX_COLOR_TEMPERATURE = 500;
+  static const uint16_t MIN_COLOR_TEMPERATURE = 100;
+
+  MatterEnhancedColorLight();
+  ~MatterEnhancedColorLight();
+  // default initial state is off, brightness = 25 (10%), HSV(21, 216, 25), color temperature is 454 (Warm White)
+  virtual bool begin(bool initialState = false, espHsvColor_t colorHSV = {21, 216, 25}, uint8_t newBrightness = 25, uint16_t colorTemperature = 454);
+  // this will just stop processing Light Matter events
+  void end();
+
+  bool setOnOff(bool newState);  // returns true if successful
+  bool getOnOff();               // returns current light state
+  bool toggle();                 // returns true if successful
+
+  bool setColorTemperature(uint16_t newTemperature);  // returns true if successful
+  uint16_t getColorTemperature();                     // returns current temperature
+
+  bool setBrightness(uint8_t newBrightness);  // returns true if successful
+  uint8_t getBrightness();                    // returns current brightness
+
+  bool setColorRGB(espRgbColor_t rgbColor);  // returns true if successful
+  espRgbColor_t getColorRGB();               // returns current RGB Color
+  bool setColorHSV(espHsvColor_t hsvColor);  // returns true if successful
+  espHsvColor_t getColorHSV();               // returns current HSV Color
+
+  // User Callback for whenever the Light On/Off state is changed by the Matter Controller
+  using EndPointOnOffCB = std::function<bool(bool)>;
+  void onChangeOnOff(EndPointOnOffCB onChangeCB) {
+    _onChangeOnOffCB = onChangeCB;
+  }
+
+  // User Callback for whenever the Light brightness value [0..255] is changed by the Matter Controller
+  using EndPointBrightnessCB = std::function<bool(uint8_t)>;
+  void onChangeBrightness(EndPointBrightnessCB onChangeCB) {
+    _onChangeBrightnessCB = onChangeCB;
+  }
+
+  // User Callback for whenever the HSV Color value is changed by the Matter Controller
+  using EndPointRGBColorCB = std::function<bool(espHsvColor_t)>;
+  void onChangeColorHSV(EndPointRGBColorCB onChangeCB) {
+    _onChangeColorCB = onChangeCB;
+  }
+
+  // User Callbqck for whenever the Light temperature value is changed by the Matter Controller
+  using EndPointTemperatureCB = std::function<bool(uint16_t)>;
+  void onChangeColorTemperature(EndPointTemperatureCB onChangeCB) {
+    _onChangeTemperatureCB = onChangeCB;
+  }
+
+  // User Callback for whenever any parameter is changed by the Matter Controller
+  using EndPointCB = std::function<bool(bool, espHsvColor_t, uint8_t, uint16_t)>;
+  void onChange(EndPointCB onChangeCB) {
+    _onChangeCB = onChangeCB;
+  }
+
+  // used to update the state of the light using the current Matter Light internal state
+  // It is necessary to set a user callback function using onChange() to handle the physical light state
+  void updateAccessory();
+
+  operator bool();             // returns current on/off light state
+  void operator=(bool state);  // turns light on or off
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  bool onOffState = false;             // default initial state is off, but it can be changed by begin(bool)
+  uint8_t brightnessLevel = 0;         // default initial brightness is 0, but it can be changed by begin(bool, uint8_t)
+  espHsvColor_t colorHSV = {0, 0, 0};  // default initial color HSV is black, but it can be changed by begin(bool, uint8_t, espHsvColor_t)
+  uint16_t colorTemperatureLevel = 0;  // default initial color temperature is 0, but it can be changed by begin(bool, uint8_t, espHsvColor_t, uint16_t)
+  EndPointOnOffCB _onChangeOnOffCB = NULL;
+  EndPointBrightnessCB _onChangeBrightnessCB = NULL;
+  EndPointRGBColorCB _onChangeColorCB = NULL;
+  EndPointTemperatureCB _onChangeTemperatureCB = NULL;
+  EndPointCB _onChangeCB = NULL;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterFan.cpp b/libraries/Matter/src/MatterEndpoints/MatterFan.cpp
new file mode 100644
index 00000000000..1647490aa05
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterFan.cpp
@@ -0,0 +1,235 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndpoints/MatterFan.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace esp_matter::cluster;
+using namespace chip::app::Clusters;
+
+// string helper for the FAN MODE
+const char *MatterFan::fanModeString[7] = {"OFF", "LOW", "MEDIUM", "HIGH", "ON", "AUTO", "SMART"};
+// bitmap for valid Fan Modes based on order defined in Zap Generated Cluster Enums
+const uint8_t MatterFan::fanModeSequence[6] = {fanSeqModeOffLowMedHigh,  fanSeqModeOffLowHigh,  fanSeqModeOffLowMedHighAuto,
+                                               fanSeqModeOffLowHighAuto, fanSeqModeOffHighAuto, fanSeqModeOffHigh};
+
+// Constructor and Method Definitions
+MatterFan::MatterFan() {}
+
+MatterFan::~MatterFan() {
+  end();
+}
+
+bool MatterFan::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+
+  if (!started) {
+    log_e("Matter Fan device has not begun.");
+    return false;
+  }
+
+  log_d("Fan Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+
+  if (endpoint_id == getEndPointId() && cluster_id == FanControl::Id) {
+    switch (attribute_id) {
+      case FanControl::Attributes::FanMode::Id:
+        log_v("FanControl Fan Mode changed to %s (%x)", val->val.u8 < 7 ? fanModeString[val->val.u8] : "Unknown", val->val.u8);
+        if (_onChangeModeCB != NULL) {
+          ret &= _onChangeModeCB((FanMode_t)val->val.u8);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB((FanMode_t)val->val.u8, currentPercent);
+        }
+        if (ret == true) {
+          currentFanMode = (FanMode_t)val->val.u8;
+        }
+        break;
+      case FanControl::Attributes::PercentSetting::Id:
+      case FanControl::Attributes::PercentCurrent::Id:
+        log_v("FanControl Percent %s changed to %d", attribute_id == FanControl::Attributes::PercentSetting::Id ? "SETTING" : "CURRENT", val->val.u8);
+        if (_onChangeSpeedCB != NULL) {
+          ret &= _onChangeSpeedCB(val->val.u8);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB(currentFanMode, val->val.u8);
+        }
+        if (ret == true) {
+          // change setting speed percent
+          currentPercent = val->val.u8;
+          setAttributeVal(FanControl::Id, FanControl::Attributes::PercentSetting::Id, val);
+          setAttributeVal(FanControl::Id, FanControl::Attributes::PercentCurrent::Id, val);
+        }
+        break;
+    }
+  }
+
+  return ret;
+}
+
+bool MatterFan::begin(uint8_t percent, FanMode_t fanMode, FanModeSequence_t fanModeSeq) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter Fan with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  // endpoint handles can be used to add/modify clusters.
+  fan::config_t fan_config;
+  fan_config.fan_control.fan_mode = fanMode;
+  fan_config.fan_control.percent_current = percent;
+  fan_config.fan_control.percent_setting = percent;
+  fan_config.fan_control.fan_mode_sequence = fanModeSeq;
+  validFanModes = fanModeSequence[fanModeSeq];
+
+  endpoint_t *endpoint = fan::create(node::get(), &fan_config, ENDPOINT_FLAG_NONE, (void *)this);
+
+  if (endpoint == nullptr) {
+    log_e("Failed to create Fan endpoint");
+    return false;
+  }
+
+  currentFanMode = fanMode;
+  currentPercent = percent;
+
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Fan created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterFan::end() {
+  started = false;
+}
+
+bool MatterFan::setMode(FanMode_t newMode, bool performUpdate) {
+  if (!started) {
+    log_w("Matter Fan device has not begun.");
+    return false;
+  }
+  // avoid processing if there was no change
+  if (currentFanMode == newMode) {
+    return true;
+  }
+
+  // check if the mode is valid based on the sequence used in its creation
+  if (!(validFanModes & (1 << newMode))) {
+    log_e("Invalid Fan Mode %s for the current Fan Mode Sequence.", fanModeString[newMode]);
+    return false;
+  }
+
+  esp_matter_attr_val_t modeVal = esp_matter_invalid(NULL);
+  if (!getAttributeVal(FanControl::Id, FanControl::Attributes::FanMode::Id, &modeVal)) {
+    log_e("Failed to get Fan Mode Attribute.");
+    return false;
+  }
+  if (modeVal.val.u8 != (uint8_t)newMode) {
+    modeVal.val.u8 = (uint8_t)newMode;
+    bool ret;
+    if (performUpdate) {
+      ret = updateAttributeVal(FanControl::Id, FanControl::Attributes::FanMode::Id, &modeVal);
+    } else {
+      ret = setAttributeVal(FanControl::Id, FanControl::Attributes::FanMode::Id, &modeVal);
+    }
+    if (!ret) {
+      log_e("Failed to %s Fan Mode Attribute.", performUpdate ? "update" : "set");
+      return false;
+    }
+  }
+  currentFanMode = newMode;
+  log_v("Fan Mode %s to %s ==> onOffState[%s]", performUpdate ? "updated" : "set", fanModeString[currentFanMode], getOnOff() ? "ON" : "OFF");
+  return true;
+}
+
+// this function will change the Fan Speed by calling the user application callback
+// it is up to the application to decide to turn on, off or change the speed of the fan
+bool MatterFan::setSpeedPercent(uint8_t newPercent, bool performUpdate) {
+  if (!started) {
+    log_w("Matter Fan device has not begun.");
+    return false;
+  }
+  // avoid processing if there was no change
+  if (currentPercent == newPercent) {
+    return true;
+  }
+
+  esp_matter_attr_val_t speedVal = esp_matter_invalid(NULL);
+  if (!getAttributeVal(FanControl::Id, FanControl::Attributes::PercentSetting::Id, &speedVal)) {
+    log_e("Failed to get Fan Speed Percent Attribute.");
+    return false;
+  }
+  if (speedVal.val.u8 != newPercent) {
+    speedVal.val.u8 = newPercent;
+    bool ret;
+    if (performUpdate) {
+      ret = updateAttributeVal(FanControl::Id, FanControl::Attributes::PercentSetting::Id, &speedVal);
+    } else {
+      ret = setAttributeVal(FanControl::Id, FanControl::Attributes::PercentSetting::Id, &speedVal);
+      ret = setAttributeVal(FanControl::Id, FanControl::Attributes::PercentCurrent::Id, &speedVal);
+    }
+    if (!ret) {
+      log_e("Failed to %s Fan Speed Percent Attribute.", performUpdate ? "update" : "set");
+      return false;
+    }
+  }
+  currentPercent = newPercent;
+  log_v("Fan Speed %s to %d ==> onOffState[%s]", performUpdate ? "updated" : "set", currentPercent, getOnOff() ? "ON" : "OFF");
+  return true;
+}
+
+bool MatterFan::setOnOff(bool newState, bool performUpdate) {
+  if (!started) {
+    log_w("Matter Fan device has not begun.");
+    return false;
+  }
+  // avoid processing if there was no change
+  if (getOnOff() == newState) {
+    return true;
+  }
+
+  esp_matter_attr_val_t modeVal = esp_matter_invalid(NULL);
+  if (!getAttributeVal(FanControl::Id, FanControl::Attributes::FanMode::Id, &modeVal)) {
+    log_e("Failed to get Fan Mode Attribute.");
+    return false;
+  }
+  if (modeVal.val.u8 != (uint8_t)newState) {
+    FanMode_t newMode = newState ? FAN_MODE_ON : FAN_MODE_OFF;
+    if (!setMode(newMode, performUpdate)) {
+      return false;
+    }
+  }
+  log_v(
+    "Fan State %s to %s :: Mode[%s]|Speed[%d]", performUpdate ? "updated" : "set", getOnOff() ? "ON" : "OFF", fanModeString[currentFanMode], currentPercent
+  );
+  return true;
+}
+
+bool MatterFan::getOnOff() {
+  return currentFanMode == FAN_MODE_OFF ? false : true;
+}
+
+bool MatterFan::toggle(bool performUpdate) {
+  if (getOnOff() == true) {
+    return setOnOff(false, performUpdate);
+  } else {
+    return setOnOff(true, performUpdate);
+  }
+}
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterFan.h b/libraries/Matter/src/MatterEndpoints/MatterFan.h
new file mode 100644
index 00000000000..a1cd6e42423
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterFan.h
@@ -0,0 +1,164 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+#include <app-common/zap-generated/cluster-objects.h>
+
+using namespace chip::app::Clusters::FanControl;
+
+// Matter Fan endpoint with On/Off, Mode and Speed control
+
+class MatterFan : public MatterEndPoint {
+public:
+  // Fan feature constants
+  static const uint8_t MAX_SPEED = 100;  // maximum High speed
+  static const uint8_t MIN_SPEED = 1;    // minimum Low speed
+  static const uint8_t OFF_SPEED = 0;    // speed set by Matter when FAN_MODE_OFF
+
+  // Default Fan Modes: ON, SMART, HIGH and OFF
+
+  // Other mode will depend on what is the configured Fan Mode Sequence
+  enum FanMode_t {
+    FAN_MODE_OFF = (uint8_t)FanModeEnum::kOff,
+    FAN_MODE_LOW = (uint8_t)FanModeEnum::kLow,
+    FAN_MODE_MEDIUM = (uint8_t)FanModeEnum::kMedium,
+    FAN_MODE_HIGH = (uint8_t)FanModeEnum::kHigh,
+    FAN_MODE_ON = (uint8_t)FanModeEnum::kOn,
+    FAN_MODE_AUTO = (uint8_t)FanModeEnum::kAuto,
+    FAN_MODE_SMART = (uint8_t)FanModeEnum::kSmart
+  };
+
+  // Menu will always have ON, OFF, HIGH and SMART.
+  // AUTO will show up only when a AUTO SEQ is CONFIGURED
+  // LOW and MEDIUM depend on the SEQ MODE configuration
+  enum FanModeSequence_t {
+    FAN_MODE_SEQ_OFF_LOW_MED_HIGH = (uint8_t)FanModeSequenceEnum::kOffLowMedHigh,
+    FAN_MODE_SEQ_OFF_LOW_HIGH = (uint8_t)FanModeSequenceEnum::kOffLowHigh,
+    FAN_MODE_SEQ_OFF_LOW_MED_HIGH_AUTO = (uint8_t)FanModeSequenceEnum::kOffLowMedHighAuto,
+    FAN_MODE_SEQ_OFF_LOW_HIGH_AUTO = (uint8_t)FanModeSequenceEnum::kOffLowHighAuto,
+    FAN_MODE_SEQ_OFF_HIGH_AUTO = (uint8_t)FanModeSequenceEnum::kOffHighAuto,
+    FAN_MODE_SEQ_OFF_HIGH = (uint8_t)FanModeSequenceEnum::kOffHigh
+  };
+
+  MatterFan();
+  ~MatterFan();
+  virtual bool begin(uint8_t percent = 0, FanMode_t fanMode = FAN_MODE_OFF, FanModeSequence_t fanModeSeq = FAN_MODE_SEQ_OFF_HIGH);
+  void end();  // this will just stop processing Matter events
+
+  // returns a friendly string for the Fan Mode
+  static const char *getFanModeString(uint8_t mode) {
+    return fanModeString[mode];
+  }
+
+  // Fan Control of current On/Off state
+
+  bool setOnOff(bool newState, bool performUpdate = true);  // sets Fan On/Off state
+  bool getOnOff();                                          // returns current Fan state
+  bool toggle(bool performUpdate = true);                   // toggle Fun On/Off state
+
+  // Fan Control of current speed percent
+
+  bool setSpeedPercent(uint8_t newPercent, bool performUpdate = true);  // returns true if successful
+  uint8_t getSpeedPercent() {                                           // returns current Fan Speed Percent
+    return currentPercent;
+  }
+
+  // Fan Control of current Fan Mode
+
+  bool setMode(FanMode_t newMode, bool performUpdate = true);  // returns true if successful
+  FanMode_t getMode() {                                        // returns current Fan Mode
+    return currentFanMode;
+  }
+  // used to update the state of the Fan using the current Matter Fan internal state
+  // It is necessary to set a user callback function using onChange() to handle the physical Fan motor state
+
+  void updateAccessory() {
+    if (_onChangeCB != NULL) {
+      _onChangeCB(currentFanMode, currentPercent);
+    }
+  }
+
+  // returns current Fan speed percent
+  operator uint8_t() {
+    return getSpeedPercent();
+  }
+
+  // User Callback for whenever the Fan Mode (state) is changed by the Matter Controller
+  using EndPointModeCB = std::function<bool(FanMode_t)>;
+  void onChangeMode(EndPointModeCB onChangeCB) {
+    _onChangeModeCB = onChangeCB;
+  }
+
+  // User Callback for whenever the Fan Speed Percentage value [0..100] is changed by the Matter Controller
+  using EndPointSpeedCB = std::function<bool(uint8_t)>;
+  void onChangeSpeedPercent(EndPointSpeedCB onChangeCB) {
+    _onChangeSpeedCB = onChangeCB;
+  }
+
+  // User Callback for whenever any parameter is changed by the Matter Controller
+  using EndPointCB = std::function<bool(FanMode_t, uint8_t)>;
+  void onChange(EndPointCB onChangeCB) {
+    _onChangeCB = onChangeCB;
+  }
+
+  // sets Fan speed percent
+  void operator=(uint8_t speedPercent) {
+    setSpeedPercent(speedPercent);
+  }
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  uint8_t validFanModes = 0;  // bitmap for valid Fan Modes - index of fanModeSequence[]
+
+  uint8_t currentPercent = 0;               // current speed percent
+  FanMode_t currentFanMode = FAN_MODE_OFF;  // current Fan Mode
+  EndPointModeCB _onChangeModeCB = NULL;
+  EndPointSpeedCB _onChangeSpeedCB = NULL;
+  EndPointCB _onChangeCB = NULL;
+
+  // bitmap for Fan Sequence Modes (OFF, LOW, MEDIUM, HIGH, AUTO)
+  static const uint8_t fanSeqModeOff = 0x01;
+  static const uint8_t fanSeqModeLow = 0x02;
+  static const uint8_t fanSeqModeMedium = 0x04;
+  static const uint8_t fanSeqModeHigh = 0x08;
+  static const uint8_t fanSeqModeOn = 0x10;
+  static const uint8_t fanSeqModeAuto = 0x20;
+  static const uint8_t fanSeqModeSmart = 0x40;
+
+  // bitmap for common modes: ON, OFF, HIGH and SMART
+  static const uint8_t fanSeqCommonModes = fanSeqModeOff | fanSeqModeOn | fanSeqModeHigh | fanSeqModeSmart;
+
+  static const uint8_t fanSeqModeOffLowMedHigh = fanSeqCommonModes | fanSeqModeLow | fanSeqModeMedium;
+  static const uint8_t fanSeqModeOffLowHigh = fanSeqCommonModes | fanSeqModeLow;
+  static const uint8_t fanSeqModeOffLowMedHighAuto = fanSeqCommonModes | fanSeqModeLow | fanSeqModeMedium | fanSeqModeAuto;
+  static const uint8_t fanSeqModeOffLowHighAuto = fanSeqCommonModes | fanSeqModeLow | fanSeqModeAuto;
+  static const uint8_t fanSeqModeOffHighAuto = fanSeqCommonModes | fanSeqModeAuto;
+  static const uint8_t fanSeqModeOffHigh = fanSeqCommonModes;
+
+  // bitmap for valid Fan Modes based on order defined in Zap Generated Cluster Enums
+  static const uint8_t fanModeSequence[6];
+
+  // string helper for the FAN MODE
+  static const char *fanModeString[7];
+};
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterGenericSwitch.cpp b/libraries/Matter/src/MatterEndpoints/MatterGenericSwitch.cpp
new file mode 100644
index 00000000000..e20479af088
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterGenericSwitch.cpp
@@ -0,0 +1,105 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterGenericSwitch.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace esp_matter::cluster;
+using namespace chip::app::Clusters;
+
+MatterGenericSwitch::MatterGenericSwitch() {}
+
+MatterGenericSwitch::~MatterGenericSwitch() {
+  end();
+}
+
+bool MatterGenericSwitch::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  if (!started) {
+    log_e("Matter Generic Switch device has not begun.");
+    return false;
+  }
+
+  log_d("Generic Switch Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+  return true;
+}
+
+bool MatterGenericSwitch::begin() {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter Generic Switch with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  generic_switch::config_t switch_config;
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = generic_switch::create(node::get(), &switch_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create Generic Switch endpoint");
+    return false;
+  }
+  // Add group cluster to the switch endpoint
+  cluster::groups::config_t groups_config;
+  cluster::groups::create(endpoint, &groups_config, CLUSTER_FLAG_SERVER | CLUSTER_FLAG_CLIENT);
+
+  cluster_t *aCluster = cluster::get(endpoint, Descriptor::Id);
+  esp_matter::cluster::descriptor::feature::taglist::add(aCluster);
+
+  cluster::fixed_label::config_t fl_config;
+  cluster::fixed_label::create(endpoint, &fl_config, CLUSTER_FLAG_SERVER);
+
+  cluster::user_label::config_t ul_config;
+  cluster::user_label::create(endpoint, &ul_config, CLUSTER_FLAG_SERVER);
+
+  aCluster = cluster::get(endpoint, Switch::Id);
+  switch_cluster::feature::momentary_switch::add(aCluster);
+  switch_cluster::event::create_initial_press(aCluster);
+
+  switch_cluster::feature::momentary_switch::add(aCluster);
+
+  switch_cluster::attribute::create_current_position(aCluster, 0);
+  switch_cluster::attribute::create_number_of_positions(aCluster, 2);
+
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Generic Switch created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterGenericSwitch::end() {
+  started = false;
+}
+
+void MatterGenericSwitch::click() {
+  if (!started) {
+    log_e("Matter Generic Switch device has not begun.");
+    return;
+  }
+
+  int switch_endpoint_id = getEndPointId();
+  uint8_t newPosition = 1;
+  // Press moves Position from 0 (off) to 1 (on)
+  chip::DeviceLayer::SystemLayer().ScheduleLambda([switch_endpoint_id, newPosition]() {
+    // InitialPress event takes newPosition as event data
+    switch_cluster::event::send_initial_press(switch_endpoint_id, newPosition);
+  });
+}
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterGenericSwitch.h b/libraries/Matter/src/MatterEndpoints/MatterGenericSwitch.h
new file mode 100644
index 00000000000..14118462932
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterGenericSwitch.h
@@ -0,0 +1,39 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+// Matter Generic Switch Endpoint that works as a single click smart button
+class MatterGenericSwitch : public MatterEndPoint {
+public:
+  MatterGenericSwitch();
+  ~MatterGenericSwitch();
+  virtual bool begin();
+  void end();  // this will just stop processing Matter events
+
+  // send a simple click event to the Matter Controller
+  void click();
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterHumiditySensor.cpp b/libraries/Matter/src/MatterEndpoints/MatterHumiditySensor.cpp
new file mode 100644
index 00000000000..d31d0e43728
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterHumiditySensor.cpp
@@ -0,0 +1,116 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterHumiditySensor.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+bool MatterHumiditySensor::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter Humidity Sensor device has not begun.");
+    return false;
+  }
+
+  log_d("Humidity Sensor Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+  return ret;
+}
+
+MatterHumiditySensor::MatterHumiditySensor() {}
+
+MatterHumiditySensor::~MatterHumiditySensor() {
+  end();
+}
+
+bool MatterHumiditySensor::begin(uint16_t _rawHumidity) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter Humidity Sensor with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  // is it a valid percentage value?
+  if (_rawHumidity > 10000) {
+    log_e("Humidity Sensor Percentage value out of range [0..100].");
+    return false;
+  }
+
+  humidity_sensor::config_t humidity_sensor_config;
+  humidity_sensor_config.relative_humidity_measurement.measured_value = _rawHumidity;
+  humidity_sensor_config.relative_humidity_measurement.min_measured_value = nullptr;
+  humidity_sensor_config.relative_humidity_measurement.max_measured_value = nullptr;
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = humidity_sensor::create(node::get(), &humidity_sensor_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create Humidity Sensor endpoint");
+    return false;
+  }
+  rawHumidity = _rawHumidity;
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Humidity Sensor created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterHumiditySensor::end() {
+  started = false;
+}
+
+bool MatterHumiditySensor::setRawHumidity(uint16_t _rawHumidity) {
+  if (!started) {
+    log_e("Matter Humidity Sensor device has not begun.");
+    return false;
+  }
+  // is it a valid percentage value?
+  if (_rawHumidity > 10000) {
+    log_e("Humidity Sensor Percentage value out of range [0..100].");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (rawHumidity == _rawHumidity) {
+    return true;
+  }
+
+  esp_matter_attr_val_t humidityVal = esp_matter_invalid(NULL);
+
+  if (!getAttributeVal(RelativeHumidityMeasurement::Id, RelativeHumidityMeasurement::Attributes::MeasuredValue::Id, &humidityVal)) {
+    log_e("Failed to get Humidity Sensor Attribute.");
+    return false;
+  }
+  if (humidityVal.val.u16 != _rawHumidity) {
+    humidityVal.val.u16 = _rawHumidity;
+    bool ret;
+    ret = updateAttributeVal(RelativeHumidityMeasurement::Id, RelativeHumidityMeasurement::Attributes::MeasuredValue::Id, &humidityVal);
+    if (!ret) {
+      log_e("Failed to update Humidity Sensor Attribute.");
+      return false;
+    }
+    rawHumidity = _rawHumidity;
+  }
+  log_v("Humidity Sensor set to %.02f Percent", (float)_rawHumidity / 100.00);
+
+  return true;
+}
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterHumiditySensor.h b/libraries/Matter/src/MatterEndpoints/MatterHumiditySensor.h
new file mode 100644
index 00000000000..aed758b7b7a
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterHumiditySensor.h
@@ -0,0 +1,69 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterHumiditySensor : public MatterEndPoint {
+public:
+  MatterHumiditySensor();
+  ~MatterHumiditySensor();
+  // begin Matter Humidity Sensor endpoint with initial float humidity percent
+  bool begin(double humidityPercent = 0.00) {
+    if (humidityPercent < 0.0 || humidityPercent > 100.0) {
+      log_e("Humidity Sensor Percentage value out of range [0..100].");
+      return false;
+    }
+    return begin(static_cast<uint16_t>(humidityPercent * 100.0f));
+  }
+  // this will just stop processing Humidity Sensor Matter events
+  void end();
+
+  // set the humidity percent with 1/100th of a percent precision
+  bool setHumidity(double humidityPercent) {
+    if (humidityPercent < 0.0 || humidityPercent > 100.0) {
+      log_e("Humidity Sensor Percentage value out of range [0..100].");
+      return false;
+    }
+    return setRawHumidity(static_cast<uint16_t>(humidityPercent * 100.0f));
+  }
+  // returns the reported float humidity percent with 1/100th of precision
+  double getHumidity() {
+    return (double)rawHumidity / 100.0;
+  }
+  // double conversion operator
+  void operator=(double humidityPercent) {
+    setHumidity(humidityPercent);
+  }
+  // double conversion operator
+  operator double() {
+    return (double)getHumidity();
+  }
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  // implementation keeps humidity relative percentage with 1/100th of a percent precision
+  uint16_t rawHumidity = 0;
+  // internal function to set the raw humidity value (Matter Cluster)
+  bool begin(uint16_t _rawHumidity);
+  bool setRawHumidity(uint16_t _rawHumidity);
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterOccupancySensor.cpp b/libraries/Matter/src/MatterEndpoints/MatterOccupancySensor.cpp
new file mode 100644
index 00000000000..0d55c37708a
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterOccupancySensor.cpp
@@ -0,0 +1,114 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterOccupancySensor.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+// clang-format off
+const uint8_t MatterOccupancySensor::occupancySensorTypeBitmap[4] = {
+  MatterOccupancySensor::occupancySensorTypePir,
+  MatterOccupancySensor::occupancySensorTypePir | MatterOccupancySensor::occupancySensorTypeUltrasonic,
+  MatterOccupancySensor::occupancySensorTypeUltrasonic,
+  MatterOccupancySensor::occupancySensorTypePhysicalContact
+};
+// clang-format on
+
+bool MatterOccupancySensor::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter Occupancy Sensor device has not begun.");
+    return false;
+  }
+
+  log_d("Occupancy Sensor Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+  return ret;
+}
+
+MatterOccupancySensor::MatterOccupancySensor() {}
+
+MatterOccupancySensor::~MatterOccupancySensor() {
+  end();
+}
+
+bool MatterOccupancySensor::begin(bool _occupancyState, OccupancySensorType_t _occupancySensorType) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter Occupancy Sensor with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  occupancy_sensor::config_t occupancy_sensor_config;
+  occupancy_sensor_config.occupancy_sensing.occupancy = _occupancyState;
+  occupancy_sensor_config.occupancy_sensing.occupancy_sensor_type = _occupancySensorType;
+  occupancy_sensor_config.occupancy_sensing.occupancy_sensor_type_bitmap = occupancySensorTypeBitmap[_occupancySensorType];
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = occupancy_sensor::create(node::get(), &occupancy_sensor_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create Occupancy Sensor endpoint");
+    return false;
+  }
+  occupancyState = _occupancyState;
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Occupancy Sensor created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterOccupancySensor::end() {
+  started = false;
+}
+
+bool MatterOccupancySensor::setOccupancy(bool _occupancyState) {
+  if (!started) {
+    log_e("Matter Occupancy Sensor device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (occupancyState == _occupancyState) {
+    return true;
+  }
+
+  esp_matter_attr_val_t occupancyVal = esp_matter_invalid(NULL);
+
+  if (!getAttributeVal(OccupancySensing::Id, OccupancySensing::Attributes::Occupancy::Id, &occupancyVal)) {
+    log_e("Failed to get Occupancy Sensor Attribute.");
+    return false;
+  }
+  if (occupancyVal.val.u8 != _occupancyState) {
+    occupancyVal.val.u8 = _occupancyState;
+    bool ret;
+    ret = updateAttributeVal(OccupancySensing::Id, OccupancySensing::Attributes::Occupancy::Id, &occupancyVal);
+    if (!ret) {
+      log_e("Failed to update Occupancy Sensor Attribute.");
+      return false;
+    }
+    occupancyState = _occupancyState;
+  }
+  log_v("Occupancy Sensor set to %s", _occupancyState ? "Occupied" : "Vacant");
+
+  return true;
+}
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterOccupancySensor.h b/libraries/Matter/src/MatterEndpoints/MatterOccupancySensor.h
new file mode 100644
index 00000000000..30f312a9841
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterOccupancySensor.h
@@ -0,0 +1,73 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+#include <app-common/zap-generated/cluster-objects.h>
+
+using namespace chip::app::Clusters::OccupancySensing;
+
+class MatterOccupancySensor : public MatterEndPoint {
+public:
+  // Different Occupancy Sensor Types
+  enum OccupancySensorType_t {
+    OCCUPANCY_SENSOR_TYPE_PIR = (uint8_t)OccupancySensorTypeEnum::kPir,
+    OCCUPANCY_SENSOR_TYPE_ULTRASONIC = (uint8_t)OccupancySensorTypeEnum::kUltrasonic,
+    OCCUPANCY_SENSOR_TYPE_PIR_AND_ULTRASONIC = (uint8_t)OccupancySensorTypeEnum::kPIRAndUltrasonic,
+    OCCUPANCY_SENSOR_TYPE_PHYSICAL_CONTACT = (uint8_t)OccupancySensorTypeEnum::kPhysicalContact
+  };
+
+  MatterOccupancySensor();
+  ~MatterOccupancySensor();
+  // begin Matter Occupancy Sensor endpoint with initial occupancy state and default PIR sensor type
+  bool begin(bool _occupancyState = false, OccupancySensorType_t _occupancySensorType = OCCUPANCY_SENSOR_TYPE_PIR);
+  // this will just stop processing Occupancy Sensor Matter events
+  void end();
+
+  // set the occupancy state
+  bool setOccupancy(bool _occupancyState);
+  // returns the occupancy state
+  bool getOccupancy() {
+    return occupancyState;
+  }
+
+  // bool conversion operator
+  void operator=(bool _occupancyState) {
+    setOccupancy(_occupancyState);
+  }
+  // bool conversion operator
+  operator bool() {
+    return getOccupancy();
+  }
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  // bitmap for Occupancy Sensor Types
+  static const uint8_t occupancySensorTypePir = 0x01;
+  static const uint8_t occupancySensorTypeUltrasonic = 0x02;
+  static const uint8_t occupancySensorTypePhysicalContact = 0x04;
+
+  // bitmap for Occupancy Sensor Type Bitmap mapped array
+  static const uint8_t occupancySensorTypeBitmap[4];
+
+  bool started = false;
+  bool occupancyState = false;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterOnOffLight.cpp b/libraries/Matter/src/MatterEndpoints/MatterOnOffLight.cpp
new file mode 100644
index 00000000000..f400390f9a7
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterOnOffLight.cpp
@@ -0,0 +1,138 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterOnOffLight.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+bool MatterOnOffLight::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter On-Off Light device has not begun.");
+    return false;
+  }
+
+  log_d("OnOff Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+
+  if (endpoint_id == getEndPointId()) {
+    log_d("OnOffLight state changed to %d", val->val.b);
+    if (cluster_id == OnOff::Id) {
+      if (attribute_id == OnOff::Attributes::OnOff::Id) {
+        if (_onChangeOnOffCB != NULL) {
+          ret &= _onChangeOnOffCB(val->val.b);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB(val->val.b);
+        }
+        if (ret == true) {
+          onOffState = val->val.b;
+        }
+      }
+    }
+  }
+  return ret;
+}
+
+MatterOnOffLight::MatterOnOffLight() {}
+
+MatterOnOffLight::~MatterOnOffLight() {
+  end();
+}
+
+bool MatterOnOffLight::begin(bool initialState) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter On-Off Light with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  on_off_light::config_t light_config;
+  light_config.on_off.on_off = initialState;
+  light_config.on_off.lighting.start_up_on_off = nullptr;
+  onOffState = initialState;
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = on_off_light::create(node::get(), &light_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create on-off light endpoint");
+    return false;
+  }
+
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("On-Off Light created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterOnOffLight::end() {
+  started = false;
+}
+
+void MatterOnOffLight::updateAccessory() {
+  if (_onChangeCB != NULL) {
+    _onChangeCB(onOffState);
+  }
+}
+
+bool MatterOnOffLight::setOnOff(bool newState) {
+  if (!started) {
+    log_e("Matter On-Off Light device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (onOffState == newState) {
+    return true;
+  }
+
+  onOffState = newState;
+
+  endpoint_t *endpoint = endpoint::get(node::get(), endpoint_id);
+  cluster_t *cluster = cluster::get(endpoint, OnOff::Id);
+  esp_matter::attribute_t *attribute = attribute::get(cluster, OnOff::Attributes::OnOff::Id);
+
+  esp_matter_attr_val_t val = esp_matter_invalid(NULL);
+  attribute::get_val(attribute, &val);
+
+  if (val.val.b != onOffState) {
+    val.val.b = onOffState;
+    attribute::update(endpoint_id, OnOff::Id, OnOff::Attributes::OnOff::Id, &val);
+  }
+  return true;
+}
+
+bool MatterOnOffLight::getOnOff() {
+  return onOffState;
+}
+
+bool MatterOnOffLight::toggle() {
+  return setOnOff(!onOffState);
+}
+
+MatterOnOffLight::operator bool() {
+  return getOnOff();
+}
+
+void MatterOnOffLight::operator=(bool newState) {
+  setOnOff(newState);
+}
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterOnOffLight.h b/libraries/Matter/src/MatterEndpoints/MatterOnOffLight.h
new file mode 100644
index 00000000000..ec524d2c300
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterOnOffLight.h
@@ -0,0 +1,60 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterOnOffLight : public MatterEndPoint {
+public:
+  MatterOnOffLight();
+  ~MatterOnOffLight();
+  virtual bool begin(bool initialState = false);  // default initial state is off
+  void end();                                     // this will just stop processing Light Matter events
+
+  bool setOnOff(bool newState);  // returns true if successful
+  bool getOnOff();               // returns current light state
+  bool toggle();                 // returns true if successful
+
+  // User Callback for whenever the Light state is changed by the Matter Controller
+  using EndPointCB = std::function<bool(bool)>;
+  void onChange(EndPointCB onChangeCB) {
+    _onChangeCB = onChangeCB;
+  }
+
+  // User Callback for whenever the Light On/Off state is changed by the Matter Controller
+  void onChangeOnOff(EndPointCB onChangeCB) {
+    _onChangeOnOffCB = onChangeCB;
+  }
+
+  // used to update the state of the light using the current Matter Light internal state
+  // It is necessary to set a user callback function using onChange() to handle the physical light state
+  void updateAccessory();
+
+  operator bool();             // returns current light state
+  void operator=(bool state);  // turns light on or off
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  bool onOffState = false;  // default initial state is off, but it can be changed by begin(bool)
+  EndPointCB _onChangeCB = NULL;
+  EndPointCB _onChangeOnOffCB = NULL;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterOnOffPlugin.cpp b/libraries/Matter/src/MatterEndpoints/MatterOnOffPlugin.cpp
new file mode 100644
index 00000000000..9b08958684c
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterOnOffPlugin.cpp
@@ -0,0 +1,141 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <app/server/Server.h>
+#include <MatterEndpoints/MatterOnOffPlugin.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+bool MatterOnOffPlugin::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter On-Off Plugin device has not begun.");
+    return false;
+  }
+
+  log_d("OnOff Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+
+  if (endpoint_id == getEndPointId()) {
+    log_d("OnOffPlugin state changed to %d", val->val.b);
+    if (cluster_id == OnOff::Id) {
+      if (attribute_id == OnOff::Attributes::OnOff::Id) {
+        if (_onChangeOnOffCB != NULL) {
+          ret &= _onChangeOnOffCB(val->val.b);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB(val->val.b);
+        }
+        if (ret == true) {
+          onOffState = val->val.b;
+        }
+      }
+    }
+  }
+  return ret;
+}
+
+MatterOnOffPlugin::MatterOnOffPlugin() {}
+
+MatterOnOffPlugin::~MatterOnOffPlugin() {
+  end();
+}
+
+bool MatterOnOffPlugin::begin(bool initialState) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter On-Off Plugin with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  on_off_plugin_unit::config_t plugin_config;
+  plugin_config.on_off.on_off = initialState;
+  plugin_config.on_off.lighting.start_up_on_off = nullptr;
+
+  // endpoint handles can be used to add/modify clusters.
+  endpoint_t *endpoint = on_off_plugin_unit::create(node::get(), &plugin_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create on-off plugin endpoint");
+    return false;
+  }
+  onOffState = initialState;
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("On-Off Plugin created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterOnOffPlugin::end() {
+  started = false;
+}
+
+void MatterOnOffPlugin::updateAccessory() {
+  if (_onChangeCB != NULL) {
+    _onChangeCB(onOffState);
+  }
+}
+
+bool MatterOnOffPlugin::setOnOff(bool newState) {
+  if (!started) {
+    log_e("Matter On-Off Plugin device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (onOffState == newState) {
+    return true;
+  }
+
+  esp_matter_attr_val_t onoffVal = esp_matter_invalid(NULL);
+
+  if (!getAttributeVal(OnOff::Id, OnOff::Attributes::OnOff::Id, &onoffVal)) {
+    log_e("Failed to get Pressure Sensor Attribute.");
+    return false;
+  }
+  if (onoffVal.val.b != newState) {
+    onoffVal.val.b = newState;
+    bool ret;
+    ret = updateAttributeVal(OnOff::Id, OnOff::Attributes::OnOff::Id, &onoffVal);
+    if (!ret) {
+      log_e("Failed to update Pressure Sensor Measurement Attribute.");
+      return false;
+    }
+    onOffState = newState;
+  }
+  log_v("Plugin OnOff state set to %s", newState ? "ON" : "OFF");
+  return true;
+}
+
+bool MatterOnOffPlugin::getOnOff() {
+  return onOffState;
+}
+
+bool MatterOnOffPlugin::toggle() {
+  return setOnOff(!onOffState);
+}
+
+MatterOnOffPlugin::operator bool() {
+  return getOnOff();
+}
+
+void MatterOnOffPlugin::operator=(bool newState) {
+  setOnOff(newState);
+}
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterOnOffPlugin.h b/libraries/Matter/src/MatterEndpoints/MatterOnOffPlugin.h
new file mode 100644
index 00000000000..0b05c0944c4
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterOnOffPlugin.h
@@ -0,0 +1,60 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterOnOffPlugin : public MatterEndPoint {
+public:
+  MatterOnOffPlugin();
+  ~MatterOnOffPlugin();
+  virtual bool begin(bool initialState = false);  // default initial state is off
+  void end();                                     // this will just stop processing Plugin Matter events
+
+  bool setOnOff(bool newState);  // returns true if successful
+  bool getOnOff();               // returns current plugin state
+  bool toggle();                 // returns true if successful
+
+  // User Callback for whenever the Plugin state is changed by the Matter Controller
+  using EndPointCB = std::function<bool(bool)>;
+  void onChange(EndPointCB onChangeCB) {
+    _onChangeCB = onChangeCB;
+  }
+
+  // User Callback for whenever the On/Off state is changed by the Matter Controller
+  void onChangeOnOff(EndPointCB onChangeCB) {
+    _onChangeOnOffCB = onChangeCB;
+  }
+
+  // used to update the state of the plugin using the current Matter Plugin internal state
+  // It is necessary to set a user callback function using onChange() to handle the physical plugin state
+  void updateAccessory();
+
+  operator bool();             // returns current plugin state
+  void operator=(bool state);  // turns plugin on or off
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  bool onOffState = false;  // default initial state is off, but it can be changed by begin(bool)
+  EndPointCB _onChangeCB = NULL;
+  EndPointCB _onChangeOnOffCB = NULL;
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterPressureSensor.cpp b/libraries/Matter/src/MatterEndpoints/MatterPressureSensor.cpp
new file mode 100644
index 00000000000..86d245d4041
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterPressureSensor.cpp
@@ -0,0 +1,104 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndpoints/MatterPressureSensor.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+bool MatterPressureSensor::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter Pressure Sensor device has not begun.");
+    return false;
+  }
+
+  log_d("Pressure Sensor Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+  return ret;
+}
+
+MatterPressureSensor::MatterPressureSensor() {}
+
+MatterPressureSensor::~MatterPressureSensor() {
+  end();
+}
+
+bool MatterPressureSensor::begin(int16_t _rawPressure) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter Pressure Sensor with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  pressure_sensor::config_t pressure_sensor_config;
+  pressure_sensor_config.pressure_measurement.pressure_measured_value = _rawPressure;
+  pressure_sensor_config.pressure_measurement.pressure_min_measured_value = nullptr;
+  pressure_sensor_config.pressure_measurement.pressure_max_measured_value = nullptr;
+
+  // endpoint handles can be used to add/modify clusters
+  endpoint_t *endpoint = pressure_sensor::create(node::get(), &pressure_sensor_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create Pressure Sensor endpoint");
+    return false;
+  }
+  rawPressure = _rawPressure;
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Pressure Sensor created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterPressureSensor::end() {
+  started = false;
+}
+
+bool MatterPressureSensor::setRawPressure(int16_t _rawPressure) {
+  if (!started) {
+    log_e("Matter Pressure Sensor device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (rawPressure == _rawPressure) {
+    return true;
+  }
+
+  esp_matter_attr_val_t pressureVal = esp_matter_invalid(NULL);
+
+  if (!getAttributeVal(PressureMeasurement::Id, PressureMeasurement::Attributes::MeasuredValue::Id, &pressureVal)) {
+    log_e("Failed to get Pressure Sensor Attribute.");
+    return false;
+  }
+  if (pressureVal.val.i16 != _rawPressure) {
+    pressureVal.val.i16 = _rawPressure;
+    bool ret;
+    ret = updateAttributeVal(PressureMeasurement::Id, PressureMeasurement::Attributes::MeasuredValue::Id, &pressureVal);
+    if (!ret) {
+      log_e("Failed to update Pressure Sensor Measurement Attribute.");
+      return false;
+    }
+    rawPressure = _rawPressure;
+  }
+  log_v("Pressure Sensor set to %.02f Degrees", (float)_rawPressure / 100.00);
+
+  return true;
+}
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterPressureSensor.h b/libraries/Matter/src/MatterEndpoints/MatterPressureSensor.h
new file mode 100644
index 00000000000..0715c05609d
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterPressureSensor.h
@@ -0,0 +1,63 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterPressureSensor : public MatterEndPoint {
+public:
+  MatterPressureSensor();
+  ~MatterPressureSensor();
+  // begin Matter Pressure Sensor endpoint with initial float pressure
+  bool begin(double pressure = 0.00) {
+    return begin(static_cast<int16_t>(pressure));
+  }
+  // this will stop processing Pressure Sensor Matter events
+  void end();
+
+  // set the reported raw pressure in hPa
+  bool setPressure(double pressure) {
+    int16_t rawValue = static_cast<int16_t>(pressure);
+    return setRawPressure(rawValue);
+  }
+  // returns the reported float pressure in hPa
+  double getPressure() {
+    return (double)rawPressure;
+  }
+
+  // double conversion operator
+  void operator=(double pressure) {
+    setPressure(pressure);
+  }
+  // double conversion operator
+  operator double() {
+    return (double)getPressure();
+  }
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  // implementation keeps pressure in hPa
+  int16_t rawPressure = 0;
+  // internal function to set the raw pressure value (Matter Cluster)
+  bool setRawPressure(int16_t _rawPressure);
+  bool begin(int16_t _rawPressure);
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterTemperatureSensor.cpp b/libraries/Matter/src/MatterEndpoints/MatterTemperatureSensor.cpp
new file mode 100644
index 00000000000..863f86386c1
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterTemperatureSensor.cpp
@@ -0,0 +1,104 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndpoints/MatterTemperatureSensor.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+bool MatterTemperatureSensor::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter Temperature Sensor device has not begun.");
+    return false;
+  }
+
+  log_d("Temperature Sensor Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+  return ret;
+}
+
+MatterTemperatureSensor::MatterTemperatureSensor() {}
+
+MatterTemperatureSensor::~MatterTemperatureSensor() {
+  end();
+}
+
+bool MatterTemperatureSensor::begin(int16_t _rawTemperature) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Temperature Sensor with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  temperature_sensor::config_t temperature_sensor_config;
+  temperature_sensor_config.temperature_measurement.measured_value = _rawTemperature;
+  temperature_sensor_config.temperature_measurement.min_measured_value = nullptr;
+  temperature_sensor_config.temperature_measurement.max_measured_value = nullptr;
+
+  // endpoint handles can be used to add/modify clusters
+  endpoint_t *endpoint = temperature_sensor::create(node::get(), &temperature_sensor_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create Temperature Sensor endpoint");
+    return false;
+  }
+  rawTemperature = _rawTemperature;
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Temperature Sensor created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterTemperatureSensor::end() {
+  started = false;
+}
+
+bool MatterTemperatureSensor::setRawTemperature(int16_t _rawTemperature) {
+  if (!started) {
+    log_e("Matter Temperature Sensor device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (rawTemperature == _rawTemperature) {
+    return true;
+  }
+
+  esp_matter_attr_val_t temperatureVal = esp_matter_invalid(NULL);
+
+  if (!getAttributeVal(TemperatureMeasurement::Id, TemperatureMeasurement::Attributes::MeasuredValue::Id, &temperatureVal)) {
+    log_e("Failed to get Temperature Sensor Attribute.");
+    return false;
+  }
+  if (temperatureVal.val.i16 != _rawTemperature) {
+    temperatureVal.val.i16 = _rawTemperature;
+    bool ret;
+    ret = updateAttributeVal(TemperatureMeasurement::Id, TemperatureMeasurement::Attributes::MeasuredValue::Id, &temperatureVal);
+    if (!ret) {
+      log_e("Failed to update Temperature Sensor Attribute.");
+      return false;
+    }
+    rawTemperature = _rawTemperature;
+  }
+  log_v("Temperature Sensor set to %.02fC", (float)_rawTemperature / 100.00);
+
+  return true;
+}
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterTemperatureSensor.h b/libraries/Matter/src/MatterEndpoints/MatterTemperatureSensor.h
new file mode 100644
index 00000000000..3be6101166c
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterTemperatureSensor.h
@@ -0,0 +1,64 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+
+class MatterTemperatureSensor : public MatterEndPoint {
+public:
+  MatterTemperatureSensor();
+  ~MatterTemperatureSensor();
+  // begin Matter Temperature Sensor endpoint with initial float temperature in Celsius
+  bool begin(double temperature = 0.00) {
+    return begin(static_cast<int16_t>(temperature * 100.0f));
+  }
+  // this will stop processing Temperature Sensor Matter events
+  void end();
+
+  // set the reported raw temperature
+  bool setTemperature(double temperature) {
+    // stores up to 1/100th Celsius precision
+    int16_t rawValue = static_cast<int16_t>(temperature * 100.0f);
+    return setRawTemperature(rawValue);
+  }
+  // returns the reported float temperature with 1/100th Celsius precision
+  double getTemperature() {
+    return (double)rawTemperature / 100.0;
+  }
+
+  // double conversion operator
+  void operator=(double temperature) {
+    setTemperature(temperature);
+  }
+  // double conversion operator
+  operator double() {
+    return (double)getTemperature();
+  }
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  // implementation keeps temperature in 1/100th Celsius x 100 (int16_t) normalized value
+  int16_t rawTemperature = 0;
+  // internal function to set the raw temperature value (Matter Cluster)
+  bool setRawTemperature(int16_t _rawTemperature);
+  bool begin(int16_t _rawTemperature);
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterThermostat.cpp b/libraries/Matter/src/MatterEndpoints/MatterThermostat.cpp
new file mode 100644
index 00000000000..5a68421bd8a
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterThermostat.cpp
@@ -0,0 +1,370 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndpoints/MatterThermostat.h>
+
+using namespace esp_matter;
+using namespace esp_matter::endpoint;
+using namespace chip::app::Clusters;
+
+// string helper for the THERMOSTAT MODE
+const char *MatterThermostat::thermostatModeString[5] = {"OFF", "AUTO", "UNKNOWN", "COOL", "HEAT"};
+
+// endpoint for color light device
+namespace esp_matter {
+using namespace cluster;
+namespace endpoint {
+namespace multi_mode_thermostat {
+typedef struct config {
+  cluster::descriptor::config_t descriptor;
+  cluster::identify::config_t identify;
+  cluster::scenes_management::config_t scenes_management;
+  cluster::groups::config_t groups;
+  cluster::thermostat::config_t thermostat;
+} config_t;
+
+uint32_t get_device_type_id() {
+  return ESP_MATTER_THERMOSTAT_DEVICE_TYPE_ID;
+}
+
+uint8_t get_device_type_version() {
+  return ESP_MATTER_THERMOSTAT_DEVICE_TYPE_VERSION;
+}
+
+esp_err_t add(endpoint_t *endpoint, config_t *config) {
+  if (!endpoint) {
+    log_e("Endpoint cannot be NULL");
+    return ESP_ERR_INVALID_ARG;
+  }
+  esp_err_t err = add_device_type(endpoint, get_device_type_id(), get_device_type_version());
+  if (err != ESP_OK) {
+    log_e("Failed to add device type id:%" PRIu32 ",err: %d", get_device_type_id(), err);
+    return err;
+  }
+
+  descriptor::create(endpoint, &(config->descriptor), CLUSTER_FLAG_SERVER);
+  identify::create(endpoint, &(config->identify), CLUSTER_FLAG_SERVER);
+  groups::create(endpoint, &(config->groups), CLUSTER_FLAG_SERVER);
+  uint32_t thermostatFeatures = 0;
+  switch (config->thermostat.control_sequence_of_operation) {
+    case MatterThermostat::THERMOSTAT_SEQ_OP_COOLING:
+    case MatterThermostat::THERMOSTAT_SEQ_OP_COOLING_REHEAT: thermostatFeatures = cluster::thermostat::feature::cooling::get_id(); break;
+    case MatterThermostat::THERMOSTAT_SEQ_OP_HEATING:
+    case MatterThermostat::THERMOSTAT_SEQ_OP_HEATING_REHEAT: thermostatFeatures = cluster::thermostat::feature::heating::get_id(); break;
+    case MatterThermostat::THERMOSTAT_SEQ_OP_COOLING_HEATING:
+    case MatterThermostat::THERMOSTAT_SEQ_OP_COOLING_HEATING_REHEAT:
+      thermostatFeatures = cluster::thermostat::feature::cooling::get_id() | cluster::thermostat::feature::heating::get_id();
+      break;
+  }
+  cluster::thermostat::create(endpoint, &(config->thermostat), CLUSTER_FLAG_SERVER, thermostatFeatures);
+  return ESP_OK;
+}
+
+endpoint_t *create(node_t *node, config_t *config, uint8_t flags, void *priv_data) {
+  endpoint_t *endpoint = endpoint::create(node, flags, priv_data);
+  add(endpoint, config);
+  return endpoint;
+}
+}  // namespace multi_mode_thermostat
+}  // namespace endpoint
+}  // namespace esp_matter
+
+bool MatterThermostat::attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val) {
+  bool ret = true;
+  if (!started) {
+    log_e("Matter Thermostat device has not begun.");
+    return false;
+  }
+  log_d("Thermostat Attr update callback: endpoint: %u, cluster: %u, attribute: %u, val: %u", endpoint_id, cluster_id, attribute_id, val->val.u32);
+
+  if (cluster_id == Thermostat::Id) {
+    switch (attribute_id) {
+      case Thermostat::Attributes::SystemMode::Id:
+        if (_onChangeModeCB != NULL) {
+          ret &= _onChangeModeCB((ThermostatMode_t)val->val.u8);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB();
+        }
+        if (ret == true) {
+          currentMode = (ThermostatMode_t)val->val.u8;
+          log_v("Thermostat Mode updated to %d", val->val.u8);
+        }
+        break;
+      case Thermostat::Attributes::LocalTemperature::Id:
+        if (_onChangeTemperatureCB != NULL) {
+          ret &= _onChangeTemperatureCB((float)val->val.i16 / 100.00);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB();
+        }
+        if (ret == true) {
+          localTemperature = val->val.i16;
+          log_v("Local Temperature updated to %.01fC", (float)val->val.i16 / 100.00);
+        }
+        break;
+      case Thermostat::Attributes::OccupiedCoolingSetpoint::Id:
+        if (_onChangeCoolingSetpointCB != NULL) {
+          ret &= _onChangeCoolingSetpointCB((float)val->val.i16 / 100.00);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB();
+        }
+        if (ret == true) {
+          coolingSetpointTemperature = val->val.i16;
+          log_v("Cooling Setpoint updated to %.01fC", (float)val->val.i16 / 100.00);
+        }
+        break;
+      case Thermostat::Attributes::OccupiedHeatingSetpoint::Id:
+        if (_onChangeHeatingSetpointCB != NULL) {
+          ret &= _onChangeHeatingSetpointCB((float)val->val.i16 / 100.00);
+        }
+        if (_onChangeCB != NULL) {
+          ret &= _onChangeCB();
+        }
+        if (ret == true) {
+          heatingSetpointTemperature = val->val.i16;
+          log_v("Heating Setpoint updated to %.01fC", (float)val->val.i16 / 100.00);
+        }
+        break;
+      default: log_w("Unhandled Thermostat Attribute ID: %u", attribute_id); break;
+    }
+  }
+  return ret;
+}
+
+MatterThermostat::MatterThermostat() {}
+
+MatterThermostat::~MatterThermostat() {
+  end();
+}
+
+bool MatterThermostat::begin(ControlSequenceOfOperation_t _controlSequence, ThermostatAutoMode_t _autoMode) {
+  ArduinoMatter::_init();
+
+  if (getEndPointId() != 0) {
+    log_e("Matter Thermostat with Endpoint Id %d device has already been created.", getEndPointId());
+    return false;
+  }
+
+  // check if auto mode is allowed with the control sequence of operation - only allowed for Cooling & Heating
+  if (_autoMode == THERMOSTAT_AUTO_MODE_ENABLED && _controlSequence != THERMOSTAT_SEQ_OP_COOLING_HEATING
+      && _controlSequence != THERMOSTAT_SEQ_OP_COOLING_HEATING_REHEAT) {
+    log_e("Thermostat in Auto Mode requires a Cooling & Heating Control Sequence of Operation.");
+    return false;
+  }
+
+  const int16_t _localTemperature = 2000;            // initial value to be automatically changed by the Matter Thermostat
+  const int16_t _coolingSetpointTemperature = 2400;  // 24C cooling setpoint
+  const int16_t _heatingSetpointTemperature = 1600;  // 16C heating setpoint
+  const ThermostatMode_t _currentMode = THERMOSTAT_MODE_OFF;
+
+  multi_mode_thermostat::config_t thermostat_config;
+  thermostat_config.thermostat.control_sequence_of_operation = (uint8_t)_controlSequence;
+  thermostat_config.thermostat.cooling.occupied_cooling_setpoint = _coolingSetpointTemperature;
+  thermostat_config.thermostat.heating.occupied_heating_setpoint = _heatingSetpointTemperature;
+  thermostat_config.thermostat.system_mode = (uint8_t)_currentMode;
+  thermostat_config.thermostat.local_temperature = _localTemperature;
+
+  // endpoint handles can be used to add/modify clusters
+  endpoint_t *endpoint = multi_mode_thermostat::create(node::get(), &thermostat_config, ENDPOINT_FLAG_NONE, (void *)this);
+  if (endpoint == nullptr) {
+    log_e("Failed to create Thermostat endpoint");
+    return false;
+  }
+  if (_autoMode == THERMOSTAT_AUTO_MODE_ENABLED) {
+    cluster_t *cluster = cluster::get(endpoint, Thermostat::Id);
+    thermostat_config.thermostat.auto_mode.min_setpoint_dead_band = kDefaultDeadBand;  // fixed by default to 2.5C
+    cluster::thermostat::feature::auto_mode::add(cluster, &thermostat_config.thermostat.auto_mode);
+  }
+
+  controlSequence = _controlSequence;
+  autoMode = _autoMode;
+  coolingSetpointTemperature = _coolingSetpointTemperature;
+  heatingSetpointTemperature = _heatingSetpointTemperature;
+  localTemperature = _localTemperature;
+  currentMode = _currentMode;
+
+  setEndPointId(endpoint::get_id(endpoint));
+  log_i("Thermostat created with endpoint_id %d", getEndPointId());
+  started = true;
+  return true;
+}
+
+void MatterThermostat::end() {
+  started = false;
+}
+
+bool MatterThermostat::setMode(ThermostatMode_t _mode) {
+  if (!started) {
+    log_e("Matter Thermostat device has not begun.");
+    return false;
+  }
+
+  if (autoMode == THERMOSTAT_AUTO_MODE_DISABLED && _mode == THERMOSTAT_MODE_AUTO) {
+    log_e("Thermostat can't set Auto Mode.");
+    return false;
+  }
+  // check if the requested mode is valid based on the control sequence of operation
+  // no restrictions for OFF mode
+  if (_mode != THERMOSTAT_MODE_OFF) {
+    // check HEAT, COOL and AUTO modes
+    switch (controlSequence) {
+      case THERMOSTAT_SEQ_OP_COOLING:
+      case THERMOSTAT_SEQ_OP_COOLING_REHEAT:
+        if (_mode == THERMOSTAT_MODE_HEAT || _mode == THERMOSTAT_MODE_AUTO) {
+          break;
+        }
+        log_e("Invalid Thermostat Mode for Cooling Control Sequence of Operation.");
+        return false;
+      case THERMOSTAT_SEQ_OP_HEATING:
+      case THERMOSTAT_SEQ_OP_HEATING_REHEAT:
+        if (_mode == THERMOSTAT_MODE_COOL || _mode == THERMOSTAT_MODE_AUTO) {
+          break;
+        }
+        log_e("Invalid Thermostat Mode for Heating Control Sequence of Operation.");
+        return false;
+      default:
+        // compiler warning about not handling all enum values
+        break;
+    }
+  }
+
+  // avoid processing if there was no change
+  if (currentMode == _mode) {
+    return true;
+  }
+
+  esp_matter_attr_val_t modeVal = esp_matter_invalid(NULL);
+  if (!getAttributeVal(Thermostat::Id, Thermostat::Attributes::SystemMode::Id, &modeVal)) {
+    log_e("Failed to get Thermostat Mode Attribute.");
+    return false;
+  }
+  if (modeVal.val.u8 != _mode) {
+    modeVal.val.u8 = _mode;
+    bool ret;
+    ret = updateAttributeVal(Thermostat::Id, Thermostat::Attributes::SystemMode::Id, &modeVal);
+    if (!ret) {
+      log_e("Failed to update Thermostat Mode Attribute.");
+      return false;
+    }
+    currentMode = _mode;
+  }
+  log_v("Thermostat Mode set to %d", _mode);
+
+  return true;
+}
+
+bool MatterThermostat::setRawTemperature(int16_t _rawTemperature, uint32_t attribute_id, int16_t *internalValue) {
+  if (!started) {
+    log_e("Matter Thermostat device has not begun.");
+    return false;
+  }
+
+  // avoid processing if there was no change
+  if (*internalValue == _rawTemperature) {
+    return true;
+  }
+
+  esp_matter_attr_val_t temperatureVal = esp_matter_invalid(NULL);
+  if (!getAttributeVal(Thermostat::Id, attribute_id, &temperatureVal)) {
+    log_e("Failed to get Thermostat Temperature or Setpoint Attribute.");
+    return false;
+  }
+  if (temperatureVal.val.i16 != _rawTemperature) {
+    temperatureVal.val.i16 = _rawTemperature;
+    bool ret;
+    ret = updateAttributeVal(Thermostat::Id, attribute_id, &temperatureVal);
+    if (!ret) {
+      log_e("Failed to update Thermostat Temperature or Setpoint Attribute.");
+      return false;
+    }
+    *internalValue = _rawTemperature;
+  }
+  log_v("Temperature set to %.01fC", (float)_rawTemperature / 100.00);
+
+  return true;
+}
+
+bool MatterThermostat::setCoolingHeatingSetpoints(double _setpointHeatingTemperature, double _setpointCollingTemperature) {
+  // at least one of the setpoints must be valid
+  bool settingCooling = _setpointCollingTemperature != (float)0xffff;
+  bool settingHeating = _setpointHeatingTemperature != (float)0xffff;
+  if (!settingCooling && !settingHeating) {
+    log_e("Invalid Setpoints values. Set correctly at least one of them in Celsius.");
+    return false;
+  }
+  int16_t _rawHeatValue = static_cast<int16_t>(_setpointHeatingTemperature * 100.0f);
+  int16_t _rawCoolValue = static_cast<int16_t>(_setpointCollingTemperature * 100.0f);
+
+  // check limits for the setpoints
+  if (settingHeating && (_rawHeatValue < kDefaultMinHeatSetpointLimit || _rawHeatValue > kDefaultMaxHeatSetpointLimit)) {
+    log_e(
+      "Invalid Heating Setpoint value: %.01fC - valid range %d..%d", _setpointHeatingTemperature, kDefaultMinHeatSetpointLimit / 100,
+      kDefaultMaxHeatSetpointLimit / 100
+    );
+    return false;
+  }
+  if (settingCooling && (_rawCoolValue < kDefaultMinCoolSetpointLimit || _rawCoolValue > kDefaultMaxCoolSetpointLimit)) {
+    log_e(
+      "Invalid Cooling Setpoint value: %.01fC - valid range %d..%d", _setpointCollingTemperature, kDefaultMinCoolSetpointLimit / 100,
+      kDefaultMaxCoolSetpointLimit / 100
+    );
+    return false;
+  }
+
+  // AUTO mode requires both setpoints to be valid to each other and respect the deadband
+  if (currentMode == THERMOSTAT_MODE_AUTO) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
+    float deadband = getDeadBand();
+#endif
+    // only setting Cooling Setpoint
+    if (settingCooling && !settingHeating && _rawCoolValue < (heatingSetpointTemperature + (kDefaultDeadBand * 10))) {
+      log_e(
+        "AutoMode :: Invalid Cooling Setpoint value: %.01fC - must be higher or equal than %.01fC", _setpointCollingTemperature, getHeatingSetpoint() + deadband
+      );
+      return false;
+    }
+    // only setting Heating Setpoint
+    if (!settingCooling && settingHeating && _rawHeatValue > (coolingSetpointTemperature - (kDefaultDeadBand * 10))) {
+      log_e(
+        "AutoMode :: Invalid Heating Setpoint value: %.01fC - must be lower or equal than %.01fC", _setpointHeatingTemperature, getCoolingSetpoint() - deadband
+      );
+      return false;
+    }
+    // setting both setpoints
+    if (settingCooling && settingHeating && (_rawCoolValue <= _rawHeatValue || _rawCoolValue - _rawHeatValue < kDefaultDeadBand * 10.0)) {
+      log_e(
+        "AutoMode :: Error - Heating Setpoint %.01fC must be lower than Cooling Setpoint %.01fC with a minimum difference of %0.1fC",
+        _setpointHeatingTemperature, _setpointCollingTemperature, deadband
+      );
+      return false;
+    }
+  }
+
+  bool ret = true;
+  if (settingCooling) {
+    ret &= setRawTemperature(_rawCoolValue, Thermostat::Attributes::OccupiedCoolingSetpoint::Id, &coolingSetpointTemperature);
+  }
+  if (settingHeating) {
+    ret &= setRawTemperature(_rawHeatValue, Thermostat::Attributes::OccupiedHeatingSetpoint::Id, &heatingSetpointTemperature);
+  }
+  return ret;
+}
+
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/Matter/src/MatterEndpoints/MatterThermostat.h b/libraries/Matter/src/MatterEndpoints/MatterThermostat.h
new file mode 100644
index 00000000000..2d64bdf3b01
--- /dev/null
+++ b/libraries/Matter/src/MatterEndpoints/MatterThermostat.h
@@ -0,0 +1,207 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <sdkconfig.h>
+#ifdef CONFIG_ESP_MATTER_ENABLE_DATA_MODEL
+
+#include <Matter.h>
+#include <MatterEndPoint.h>
+#include <app-common/zap-generated/cluster-enums.h>
+
+using namespace chip::app::Clusters;
+
+class MatterThermostat : public MatterEndPoint {
+public:
+  // clang-format off
+  enum ControlSequenceOfOperation_t {
+    THERMOSTAT_SEQ_OP_COOLING                = (uint8_t) Thermostat::ControlSequenceOfOperationEnum::kCoolingOnly,
+    THERMOSTAT_SEQ_OP_COOLING_REHEAT         = (uint8_t) Thermostat::ControlSequenceOfOperationEnum::kCoolingWithReheat,
+    THERMOSTAT_SEQ_OP_HEATING                = (uint8_t) Thermostat::ControlSequenceOfOperationEnum::kHeatingOnly,
+    THERMOSTAT_SEQ_OP_HEATING_REHEAT         = (uint8_t) Thermostat::ControlSequenceOfOperationEnum::kHeatingWithReheat,
+    THERMOSTAT_SEQ_OP_COOLING_HEATING        = (uint8_t) Thermostat::ControlSequenceOfOperationEnum::kCoolingAndHeating,
+    THERMOSTAT_SEQ_OP_COOLING_HEATING_REHEAT = (uint8_t) Thermostat::ControlSequenceOfOperationEnum::kCoolingAndHeatingWithReheat,
+  };
+
+  enum ThermostatMode_t {
+    THERMOSTAT_MODE_OFF            = (uint8_t) Thermostat::SystemModeEnum::kOff,
+    THERMOSTAT_MODE_AUTO           = (uint8_t) Thermostat::SystemModeEnum::kAuto,
+    THERMOSTAT_MODE_COOL           = (uint8_t) Thermostat::SystemModeEnum::kCool,
+    THERMOSTAT_MODE_HEAT           = (uint8_t) Thermostat::SystemModeEnum::kHeat,
+    THERMOSTAT_MODE_EMERGENCY_HEAT = (uint8_t) Thermostat::SystemModeEnum::kEmergencyHeat,
+    THERMOSTAT_MODE_PRECOOLING     = (uint8_t) Thermostat::SystemModeEnum::kPrecooling,
+    THERMOSTAT_MODE_FAN_ONLY       = (uint8_t) Thermostat::SystemModeEnum::kFanOnly,
+    THERMOSTAT_MODE_DRY            = (uint8_t) Thermostat::SystemModeEnum::kDry,
+    THERMOSTAT_MODE_SLEEP          = (uint8_t) Thermostat::SystemModeEnum::kSleep
+  };
+
+  enum ThermostatAutoMode_t {
+    THERMOSTAT_AUTO_MODE_DISABLED = (uint8_t) Thermostat::SystemModeEnum::kOff,
+    THERMOSTAT_AUTO_MODE_ENABLED  = (uint8_t) Thermostat::SystemModeEnum::kAuto,
+  };
+  // clang-format on
+
+  MatterThermostat();
+  ~MatterThermostat();
+  // begin Matter Thermostat endpoint with initial Operation Mode
+  bool begin(ControlSequenceOfOperation_t controlSequence = THERMOSTAT_SEQ_OP_COOLING, ThermostatAutoMode_t autoMode = THERMOSTAT_AUTO_MODE_DISABLED);
+  // this will stop processing Thermostat Matter events
+  void end();
+
+  // set the Thermostat Mode
+  bool setMode(ThermostatMode_t mode);
+  // get the Thermostat Mode
+  ThermostatMode_t getMode() {
+    return currentMode;
+  }
+  // returns a friendly string for the Fan Mode
+  static const char *getThermostatModeString(uint8_t mode) {
+    return thermostatModeString[mode];
+  }
+
+  // get the Thermostat Control Sequence of Operation
+  ControlSequenceOfOperation_t getControlSequence() {
+    return controlSequence;
+  }
+
+  // get the minimum heating setpoint in 1/100th of a Celsio degree
+  float getMinHeatSetpoint() {
+    return (float)kDefaultMinHeatSetpointLimit / 100.00;
+  }
+  // get the maximum heating setpoint in 1/100th of a Celsio degree
+  float getMaxHeatSetpoint() {
+    return (float)kDefaultMaxHeatSetpointLimit / 100.00;
+  }
+  // get the minimum cooling setpoint in 1/100th of a Celsio degree
+  float getMinCoolSetpoint() {
+    return (float)kDefaultMinCoolSetpointLimit / 100.00;
+  }
+  // get the maximum cooling setpoint in 1/100th of a Celsio degree
+  float getMaxCoolSetpoint() {
+    return (float)kDefaultMaxCoolSetpointLimit / 100.00;
+  }
+  // get the deadband in 1/10th of a Celsio degree
+  float getDeadBand() {
+    return (float)kDefaultDeadBand / 10.00;
+  }
+
+  // generic function for setting the cooling and heating setpoints - checks if the setpoints are valid
+  // it can be used to set both setpoints at the same time or only one of them, by setting the other to (float)0xffff
+  // Heating Setpoint must be lower than Cooling Setpoint
+  // When using AUTO mode the Cooling Setpoint must be higher than Heating Setpoint by at least the 2.5C (deadband)
+  // Thermostat Matter Server will enforce those rules and the Max/Min setpoints limits as in the Matter Specification
+  bool setCoolingHeatingSetpoints(double _setpointHeatingTemperature, double _setpointCollingTemperature);
+
+  // set the heating setpoint in 1/100th of a Celsio degree
+  bool setHeatingSetpoint(double _setpointHeatingTemperature) {
+    return setCoolingHeatingSetpoints((double)0xffff, _setpointHeatingTemperature);
+  }
+  // get the heating setpoint in 1/100th of a Celsio degree
+  double getHeatingSetpoint() {
+    return heatingSetpointTemperature / 100.0;
+  }
+  // set the cooling setpoint in 1/100th of a Celsio degree
+  bool setCoolingSetpoint(double _setpointCollingTemperature) {
+    return setCoolingHeatingSetpoints(_setpointCollingTemperature, (double)0xffff);
+  }
+  // get the cooling setpoint in 1/100th of a Celsio degree
+  double getCoolingSetpoint() {
+    return coolingSetpointTemperature / 100.0;
+  }
+
+  // set the local Thermostat temperature in  Celsio degrees
+  bool setLocalTemperature(double temperature) {
+    // stores up to 1/100th of a Celsio degree precision
+    int16_t rawValue = static_cast<int16_t>(temperature * 100.0f);
+    return setRawTemperature(rawValue, Thermostat::Attributes::LocalTemperature::Id, &localTemperature);
+  }
+  // returns the local Thermostat float temperature with 1/100th of a Celsio degree precision
+  double getLocalTemperature() {
+    return (double)localTemperature / 100.0;
+  }
+
+  // User Callback for whenever the Thermostat Mode is changed by the Matter Controller
+  using EndPointModeCB = std::function<bool(ThermostatMode_t)>;
+  void onChangeMode(EndPointModeCB onChangeCB) {
+    _onChangeModeCB = onChangeCB;
+  }
+
+  // User Callback for whenever the Local Temperature is changed by the Matter Controller
+  using EndPointTemperatureCB = std::function<bool(float)>;
+  void onChangeLocalTemperature(EndPointTemperatureCB onChangeCB) {
+    _onChangeTemperatureCB = onChangeCB;
+  }
+
+  // User Callback for whenever the Cooling or Heating Setpoint is changed by the Matter Controller
+  using EndPointCoolingSetpointCB = std::function<bool(double)>;
+  void onChangeCoolingSetpoint(EndPointCoolingSetpointCB onChangeCB) {
+    _onChangeCoolingSetpointCB = onChangeCB;
+  }
+
+  // User Callback for whenever the Cooling or Heating Setpoint is changed by the Matter Controller
+  using EndPointHeatingSetpointCB = std::function<bool(double)>;
+  void onChangeHeatingSetpoint(EndPointHeatingSetpointCB onChangeCB) {
+    _onChangeHeatingSetpointCB = onChangeCB;
+  }
+
+  // User Callback for whenever any parameter is changed by the Matter Controller
+  // Main parameters are Thermostat Mode, Local Temperature, Cooling Setpoint and Heating Setpoint
+  // Those can be obtained using getMode(), getTemperature(), getCoolingSetpoint() and getHeatingSetpoint()
+  using EndPointCB = std::function<bool(void)>;
+  void onChange(EndPointCB onChangeCB) {
+    _onChangeCB = onChangeCB;
+  }
+
+  // this function is called by Matter internal event processor. It could be overwritten by the application, if necessary.
+  bool attributeChangeCB(uint16_t endpoint_id, uint32_t cluster_id, uint32_t attribute_id, esp_matter_attr_val_t *val);
+
+protected:
+  bool started = false;
+  // implementation keeps temperature in 1/100th of a Celsio degree
+  int16_t coolingSetpointTemperature = 2400;  // 24C cooling setpoint
+  int16_t localTemperature = 2000;            // 20C local temperature
+  int16_t heatingSetpointTemperature = 1600;  // 16C heating setpoint
+
+  ThermostatMode_t currentMode = THERMOSTAT_MODE_OFF;
+  ControlSequenceOfOperation_t controlSequence = THERMOSTAT_SEQ_OP_COOLING;
+  ThermostatAutoMode_t autoMode = THERMOSTAT_AUTO_MODE_DISABLED;
+
+  EndPointModeCB _onChangeModeCB = NULL;
+  EndPointTemperatureCB _onChangeTemperatureCB = NULL;
+  EndPointCoolingSetpointCB _onChangeCoolingSetpointCB = NULL;
+  EndPointHeatingSetpointCB _onChangeHeatingSetpointCB = NULL;
+  EndPointCB _onChangeCB = NULL;
+
+  // internal function to set the raw temperature value (Matter Cluster)
+  bool setRawTemperature(int16_t _rawTemperature, uint32_t attribute_id, int16_t *internalValue);
+
+  // clang-format off
+  // Default Thermostat values - can't be changed - defined in the Thermostat Cluster Server code
+  static const int16_t kDefaultAbsMinHeatSetpointLimit = 700;  // 7C (44.5 F)
+  static const int16_t kDefaultMinHeatSetpointLimit    = 700;  // 7C (44.5 F)
+  static const int16_t kDefaultAbsMaxHeatSetpointLimit = 3000; // 30C (86 F)
+  static const int16_t kDefaultMaxHeatSetpointLimit    = 3000; // 30C (86 F)
+
+  static const int16_t kDefaultAbsMinCoolSetpointLimit = 1600; // 16C (61 F)
+  static const int16_t kDefaultMinCoolSetpointLimit    = 1600; // 16C (61 F)
+  static const int16_t kDefaultAbsMaxCoolSetpointLimit = 3200; // 32C (90 F)
+  static const int16_t kDefaultMaxCoolSetpointLimit    = 3200; // 32C (90 F)
+
+  static const int8_t  kDefaultDeadBand                = 25; // 2.5C when in AUTO mode
+  // clang-format on
+
+  // string helper for the THERMOSTAT MODE
+  static const char *thermostatModeString[5];
+};
+#endif /* CONFIG_ESP_MATTER_ENABLE_DATA_MODEL */
diff --git a/libraries/NetBIOS/examples/ESP_NBNST/ESP_NBNST.ino b/libraries/NetBIOS/examples/ESP_NBNST/ESP_NBNST.ino
old mode 100755
new mode 100644
index 0f49e5aad6c..219901a7e27
--- a/libraries/NetBIOS/examples/ESP_NBNST/ESP_NBNST.ino
+++ b/libraries/NetBIOS/examples/ESP_NBNST/ESP_NBNST.ino
@@ -1,8 +1,8 @@
 #include <WiFi.h>
 #include <NetBIOS.h>
 
-const char* ssid = "............";
-const char* password = "..............";
+const char *ssid = "............";
+const char *password = "..............";
 
 void setup() {
   Serial.begin(115200);
@@ -26,6 +26,4 @@ void setup() {
   NBNS.begin("ESP");
 }
 
-void loop() {
-  
-}
+void loop() {}
diff --git a/libraries/NetBIOS/examples/ESP_NBNST/ci.json b/libraries/NetBIOS/examples/ESP_NBNST/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/NetBIOS/examples/ESP_NBNST/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/NetBIOS/library.properties b/libraries/NetBIOS/library.properties
index 50e6e79c099..5f134bfdc55 100644
--- a/libraries/NetBIOS/library.properties
+++ b/libraries/NetBIOS/library.properties
@@ -1,5 +1,5 @@
 name=NetBIOS
-version=1.0
+version=3.2.0
 author=Pablo@xpablo.cz
 maintainer=Hristo Gochkov<hristo@espressif.com>
 sentence=Enables NBNS (NetBIOS) name resolution.
diff --git a/libraries/NetBIOS/src/NetBIOS.cpp b/libraries/NetBIOS/src/NetBIOS.cpp
old mode 100755
new mode 100644
index 22d3deca43b..647f0940898
--- a/libraries/NetBIOS/src/NetBIOS.cpp
+++ b/libraries/NetBIOS/src/NetBIOS.cpp
@@ -1,131 +1,146 @@
-#include "NetBIOS.h"
-
-#include <functional>
-
-#define NBNS_PORT 137
-#define NBNS_MAX_HOSTNAME_LEN 32
-
-typedef struct {
-    uint16_t id;
-    uint8_t flags1;
-    uint8_t flags2;
-    uint16_t qcount;
-    uint16_t acount;
-    uint16_t nscount;
-    uint16_t adcount;
-    uint8_t name_len;
-    char name[NBNS_MAX_HOSTNAME_LEN + 1];
-    uint16_t type;
-    uint16_t clas;
-} __attribute__((packed)) nbns_question_t;
-
-typedef struct {
-    uint16_t id;
-    uint8_t flags1;
-    uint8_t flags2;
-    uint16_t qcount;
-    uint16_t acount;
-    uint16_t nscount;
-    uint16_t adcount;
-    uint8_t name_len;
-    char name[NBNS_MAX_HOSTNAME_LEN + 1];
-    uint16_t type;
-    uint16_t clas;
-    uint32_t ttl;
-    uint16_t data_len;
-    uint16_t flags;
-    uint32_t addr;
-} __attribute__((packed)) nbns_answer_t;
-
-static void _getnbname(const char *nbname, char *name, uint8_t maxlen){
-    uint8_t b;
-    uint8_t c = 0;
-
-    while ((*nbname) && (c < maxlen)) {
-        b = (*nbname++ - 'A') << 4;
-        c++;
-        if (*nbname) {
-            b |= *nbname++ - 'A';
-            c++;
-        }
-        if(!b || b == ' '){
-            break;
-        }
-        *name++ = b;
-    }
-    *name = 0;
-}
-
-static void append_16(void * dst, uint16_t value){
-    uint8_t * d = (uint8_t *)dst;
-    *d++ = (value >> 8) & 0xFF;
-    *d++ = value & 0xFF;
-}
-
-static void append_32(void * dst, uint32_t value){
-    uint8_t * d = (uint8_t *)dst;
-    *d++ = (value >> 24) & 0xFF;
-    *d++ = (value >> 16) & 0xFF;
-    *d++ = (value >> 8) & 0xFF;
-    *d++ = value & 0xFF;
-}
-
-void NetBIOS::_onPacket(AsyncUDPPacket& packet){
-    if (packet.length() >= sizeof(nbns_question_t)) {
-        nbns_question_t * question = (nbns_question_t *)packet.data();
-        if (0 == (question->flags1 & 0x80)) {
-            char name[ NBNS_MAX_HOSTNAME_LEN + 1 ];
-            _getnbname(&question->name[0], (char *)&name, question->name_len);
-            if (_name.equals(name)) {
-                nbns_answer_t nbnsa;
-                nbnsa.id = question->id;
-                nbnsa.flags1 = 0x85;
-                nbnsa.flags2 = 0;
-                append_16((void *)&nbnsa.qcount, 0);
-                append_16((void *)&nbnsa.acount, 1);
-                append_16((void *)&nbnsa.nscount, 0);
-                append_16((void *)&nbnsa.adcount, 0);
-                nbnsa.name_len = question->name_len;
-                memcpy(&nbnsa.name[0], &question->name[0], question->name_len + 1);
-                append_16((void *)&nbnsa.type, 0x20);
-                append_16((void *)&nbnsa.clas, 1);
-                append_32((void *)&nbnsa.ttl, 300000);
-                append_16((void *)&nbnsa.data_len, 6);
-                append_16((void *)&nbnsa.flags, 0);
-                nbnsa.addr = WiFi.localIP();
-                _udp.writeTo((uint8_t *)&nbnsa, sizeof(nbnsa), packet.remoteIP(), NBNS_PORT);
-            }
-        }
-    }
-}
-
-NetBIOS::NetBIOS(){
-
-}
-NetBIOS::~NetBIOS(){
-    end();
-}
-
-bool NetBIOS::begin(const char *name){
-    _name = name;
-    _name.toUpperCase();
-
-    if(_udp.connected()){
-        return true;
-    }
-
-    _udp.onPacket([](void * arg, AsyncUDPPacket& packet){ ((NetBIOS*)(arg))->_onPacket(packet); }, this);
-    return _udp.listen(NBNS_PORT);
-}
-
-void NetBIOS::end(){
-    if(_udp.connected()){
-        _udp.close();
-    }
-}
-
-#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_NETBIOS)
-NetBIOS NBNS;
-#endif
-
-// EOF
+#include "NetBIOS.h"
+#include <functional>
+extern "C" {
+#include <lwip/netif.h>
+};  // extern "C"
+
+#define NBNS_PORT             137
+#define NBNS_MAX_HOSTNAME_LEN 32
+
+typedef struct {
+  uint16_t id;
+  uint8_t flags1;
+  uint8_t flags2;
+  uint16_t qcount;
+  uint16_t acount;  // codespell:ignore acount
+  uint16_t nscount;
+  uint16_t adcount;
+  uint8_t name_len;
+  char name[NBNS_MAX_HOSTNAME_LEN + 1];
+  uint16_t type;
+  uint16_t clas;
+} __attribute__((packed)) nbns_question_t;
+
+typedef struct {
+  uint16_t id;
+  uint8_t flags1;
+  uint8_t flags2;
+  uint16_t qcount;
+  uint16_t acount;  // codespell:ignore acount
+  uint16_t nscount;
+  uint16_t adcount;
+  uint8_t name_len;
+  char name[NBNS_MAX_HOSTNAME_LEN + 1];
+  uint16_t type;
+  uint16_t clas;
+  uint32_t ttl;
+  uint16_t data_len;
+  uint16_t flags;
+  uint32_t addr;
+} __attribute__((packed)) nbns_answer_t;
+
+static void _getnbname(const char *nbname, char *name, uint8_t maxlen) {
+  uint8_t b;
+  uint8_t c = 0;
+
+  while ((*nbname) && (c < maxlen)) {
+    b = (*nbname++ - 'A') << 4;
+    c++;
+    if (*nbname) {
+      b |= *nbname++ - 'A';
+      c++;
+    }
+    if (!b || b == ' ') {
+      break;
+    }
+    *name++ = b;
+  }
+  *name = 0;
+}
+
+static void append_16(void *dst, uint16_t value) {
+  uint8_t *d = (uint8_t *)dst;
+  *d++ = (value >> 8) & 0xFF;
+  *d++ = value & 0xFF;
+}
+
+static void append_32(void *dst, uint32_t value) {
+  uint8_t *d = (uint8_t *)dst;
+  *d++ = (value >> 24) & 0xFF;
+  *d++ = (value >> 16) & 0xFF;
+  *d++ = (value >> 8) & 0xFF;
+  *d++ = value & 0xFF;
+}
+
+void NetBIOS::_onPacket(AsyncUDPPacket &packet) {
+  if (packet.length() >= sizeof(nbns_question_t)) {
+    nbns_question_t *question = (nbns_question_t *)packet.data();
+    if (0 == (question->flags1 & 0x80)) {
+      char name[NBNS_MAX_HOSTNAME_LEN + 1];
+      _getnbname(&question->name[0], (char *)&name, question->name_len);
+      if (_name.equals(name)) {
+        nbns_answer_t nbnsa;
+        nbnsa.id = question->id;
+        nbnsa.flags1 = 0x85;
+        nbnsa.flags2 = 0;
+        append_16((void *)&nbnsa.qcount, 0);
+        append_16((void *)&nbnsa.acount, 1);  // codespell:ignore acount
+        append_16((void *)&nbnsa.nscount, 0);
+        append_16((void *)&nbnsa.adcount, 0);
+        nbnsa.name_len = question->name_len;
+        memcpy(&nbnsa.name[0], &question->name[0], question->name_len + 1);
+        append_16((void *)&nbnsa.type, 0x20);
+        append_16((void *)&nbnsa.clas, 1);
+        append_32((void *)&nbnsa.ttl, 300000);
+        append_16((void *)&nbnsa.data_len, 6);
+        append_16((void *)&nbnsa.flags, 0);
+        nbnsa.addr = packet.localIP();  // By default, should be overridden below
+        // Iterate over all netifs, see if the incoming address matches one of the netmaskes networks
+        for (auto netif = netif_list; netif; netif = netif->next) {
+          auto maskedip = ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif));
+          auto maskedin = ((uint32_t)packet.localIP()) & ip4_addr_get_u32(netif_ip4_netmask(netif));
+          if (maskedip == maskedin) {
+            nbnsa.addr = ip4_addr_get_u32(netif_ip4_addr(netif));
+            break;
+          }
+        }
+        _udp.writeTo((uint8_t *)&nbnsa, sizeof(nbnsa), packet.remoteIP(), NBNS_PORT);
+      }
+    }
+  }
+}
+
+NetBIOS::NetBIOS() {}
+
+NetBIOS::~NetBIOS() {
+  end();
+}
+
+bool NetBIOS::begin(const char *name) {
+  _name = name;
+  _name.toUpperCase();
+
+  if (_udp.connected()) {
+    return true;
+  }
+
+  _udp.onPacket(
+    [](void *arg, AsyncUDPPacket &packet) {
+      ((NetBIOS *)(arg))->_onPacket(packet);
+    },
+    this
+  );
+  return _udp.listen(NBNS_PORT);
+}
+
+void NetBIOS::end() {
+  if (_udp.connected()) {
+    _udp.close();
+  }
+}
+
+#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_NETBIOS)
+NetBIOS NBNS;
+#endif
+
+// EOF
diff --git a/libraries/NetBIOS/src/NetBIOS.h b/libraries/NetBIOS/src/NetBIOS.h
old mode 100755
new mode 100644
index 0321f6b8b91..caa03c96ddb
--- a/libraries/NetBIOS/src/NetBIOS.h
+++ b/libraries/NetBIOS/src/NetBIOS.h
@@ -1,26 +1,25 @@
-//
-#ifndef __ESPNBNS_h__
-#define __ESPNBNS_h__
-
-#include <WiFi.h>
-#include "AsyncUDP.h"
-
-class NetBIOS
-{
-protected:
-    AsyncUDP _udp;
-    String _name;
-    void _onPacket(AsyncUDPPacket& packet);
-
-public:
-    NetBIOS();
-    ~NetBIOS();
-    bool begin(const char *name);
-    void end();
-};
-
-#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_NETBIOS)
-extern NetBIOS NBNS;
-#endif
-
-#endif
+//
+#ifndef __ESPNBNS_h__
+#define __ESPNBNS_h__
+
+#include "Arduino.h"
+#include "AsyncUDP.h"
+
+class NetBIOS {
+protected:
+  AsyncUDP _udp;
+  String _name;
+  void _onPacket(AsyncUDPPacket &packet);
+
+public:
+  NetBIOS();
+  ~NetBIOS();
+  bool begin(const char *name);
+  void end();
+};
+
+#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_NETBIOS)
+extern NetBIOS NBNS;
+#endif
+
+#endif
diff --git a/libraries/Network/library.properties b/libraries/Network/library.properties
new file mode 100644
index 00000000000..0b821e08d77
--- /dev/null
+++ b/libraries/Network/library.properties
@@ -0,0 +1,9 @@
+name=Networking
+version=3.2.0
+author=Hristo Gochkov
+maintainer=Hristo Gochkov <hristo@espressif.com>
+sentence=General network management library.
+paragraph=This library holds all common functionality of the different network interfaces.
+category=Communication
+url=
+architectures=esp32
diff --git a/libraries/Network/src/Network.h b/libraries/Network/src/Network.h
new file mode 100644
index 00000000000..935cd1a275c
--- /dev/null
+++ b/libraries/Network/src/Network.h
@@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "NetworkInterface.h"
+#include "NetworkEvents.h"
+#include "NetworkManager.h"
+
+#include "NetworkClient.h"
+#include "NetworkServer.h"
+#include "NetworkUdp.h"
diff --git a/libraries/Network/src/NetworkClient.cpp b/libraries/Network/src/NetworkClient.cpp
new file mode 100644
index 00000000000..89411a42453
--- /dev/null
+++ b/libraries/Network/src/NetworkClient.cpp
@@ -0,0 +1,692 @@
+/*
+  Client.h - Client class for Raspberry Pi
+  Copyright (c) 2016 Hristo Gochkov  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "NetworkClient.h"
+#include "NetworkManager.h"
+#include <lwip/sockets.h>
+#include <lwip/netdb.h>
+#include <errno.h>
+
+// It is already defined in IDF as:
+//#define IN6_IS_ADDR_V4MAPPED(a)     ip6_addr_isipv4mappedipv6((ip6_addr_t*)(a))
+//#define ip6_addr_isipv4mappedipv6(ip6addr) (((ip6addr)->addr[0] == 0) && ((ip6addr)->addr[1] == 0) && (((ip6addr)->addr[2]) == PP_HTONL(0x0000FFFFUL)))
+// Keeping as a memory of the change.
+//#define _IN6_IS_ADDR_V4MAPPED(a) ((((__const uint32_t *)(a))[0] == 0) && (((__const uint32_t *)(a))[1] == 0) && (((__const uint32_t *)(a))[2] == htonl(0xffff)))
+
+#define WIFI_CLIENT_DEF_CONN_TIMEOUT_MS (3000)
+#define WIFI_CLIENT_MAX_WRITE_RETRY     (10)
+#define WIFI_CLIENT_SELECT_TIMEOUT_US   (1000000)
+#define WIFI_CLIENT_FLUSH_BUFFER_SIZE   (1024)
+
+#undef connect
+#undef write
+#undef read
+
+class NetworkClientRxBuffer {
+private:
+  size_t _size;
+  uint8_t *_buffer;
+  size_t _pos;
+  size_t _fill;
+  int _fd;
+  bool _failed;
+
+  size_t r_available() {
+    if (_fd < 0) {
+      return 0;
+    }
+    int count;
+#ifdef ESP_IDF_VERSION_MAJOR
+    int res = lwip_ioctl(_fd, FIONREAD, &count);
+#else
+    int res = lwip_ioctl_r(_fd, FIONREAD, &count);
+#endif
+    if (res < 0) {
+      _failed = true;
+      return 0;
+    }
+    return count;
+  }
+
+  size_t fillBuffer() {
+    if (!_buffer) {
+      _buffer = (uint8_t *)malloc(_size);
+      if (!_buffer) {
+        log_e("Not enough memory to allocate buffer");
+        _failed = true;
+        return 0;
+      }
+    }
+    if (_fill && _pos == _fill) {
+      _fill = 0;
+      _pos = 0;
+    }
+    if (!_buffer || _size <= _fill || !r_available()) {
+      return 0;
+    }
+    int res = recv(_fd, _buffer + _fill, _size - _fill, MSG_DONTWAIT);
+    if (res < 0) {
+      if (errno != EWOULDBLOCK) {
+        _failed = true;
+      }
+      return 0;
+    }
+    _fill += res;
+    return res;
+  }
+
+public:
+  NetworkClientRxBuffer(int fd, size_t size = 1436) : _size(size), _buffer(NULL), _pos(0), _fill(0), _fd(fd), _failed(false) {
+    //_buffer = (uint8_t *)malloc(_size);
+  }
+
+  ~NetworkClientRxBuffer() {
+    free(_buffer);
+  }
+
+  bool failed() {
+    return _failed;
+  }
+
+  int read(uint8_t *dst, size_t len) {
+    if (!dst || !len || (_pos == _fill && !fillBuffer())) {
+      return _failed ? -1 : 0;
+    }
+    size_t a = _fill - _pos;
+    if (len <= a || ((len - a) <= (_size - _fill) && fillBuffer() >= (len - a))) {
+      if (len == 1) {
+        *dst = _buffer[_pos];
+      } else {
+        memcpy(dst, _buffer + _pos, len);
+      }
+      _pos += len;
+      return len;
+    }
+    size_t left = len;
+    size_t toRead = a;
+    uint8_t *buf = dst;
+    memcpy(buf, _buffer + _pos, toRead);
+    _pos += toRead;
+    left -= toRead;
+    buf += toRead;
+    while (left) {
+      if (!fillBuffer()) {
+        return len - left;
+      }
+      a = _fill - _pos;
+      toRead = (a > left) ? left : a;
+      memcpy(buf, _buffer + _pos, toRead);
+      _pos += toRead;
+      left -= toRead;
+      buf += toRead;
+    }
+    return len;
+  }
+
+  int peek() {
+    if (_pos == _fill && !fillBuffer()) {
+      return -1;
+    }
+    return _buffer[_pos];
+  }
+
+  size_t available() {
+    return _fill - _pos + r_available();
+  }
+
+  void clear() {
+    if (r_available()) {
+      _pos = _fill;
+      while (fillBuffer()) {
+        _pos = _fill;
+      }
+    }
+    _pos = 0;
+    _fill = 0;
+  }
+};
+
+class NetworkClientSocketHandle {
+private:
+  int sockfd;
+
+public:
+  NetworkClientSocketHandle(int fd) : sockfd(fd) {}
+
+  ~NetworkClientSocketHandle() {
+    close();
+  }
+
+  void close() {
+    if (sockfd >= 0) {
+      ::close(sockfd);
+      sockfd = -1;
+    }
+  }
+
+  int fd() {
+    return sockfd;
+  }
+};
+
+NetworkClient::NetworkClient() : _rxBuffer(nullptr), _connected(false), _sse(false), _timeout(WIFI_CLIENT_DEF_CONN_TIMEOUT_MS), next(NULL) {}
+
+NetworkClient::NetworkClient(int fd) : _connected(true), _timeout(WIFI_CLIENT_DEF_CONN_TIMEOUT_MS), next(NULL) {
+  clientSocketHandle.reset(new NetworkClientSocketHandle(fd));
+  _rxBuffer.reset(new NetworkClientRxBuffer(fd));
+}
+
+NetworkClient::~NetworkClient() {}
+
+void NetworkClient::stop() {
+  if (clientSocketHandle) {
+    clientSocketHandle->close();
+  }
+  clientSocketHandle = NULL;
+  _rxBuffer = NULL;
+  _connected = false;
+  _lastReadTimeout = 0;
+  _lastWriteTimeout = 0;
+}
+
+int NetworkClient::connect(IPAddress ip, uint16_t port) {
+  return connect(ip, port, _timeout);
+}
+
+int NetworkClient::connect(IPAddress ip, uint16_t port, int32_t timeout_ms) {
+  struct sockaddr_storage serveraddr = {};
+  _timeout = timeout_ms;
+  int sockfd = -1;
+
+#if CONFIG_LWIP_IPV6
+  if (ip.type() == IPv6) {
+    struct sockaddr_in6 *tmpaddr = (struct sockaddr_in6 *)&serveraddr;
+    sockfd = socket(AF_INET6, SOCK_STREAM, 0);
+    tmpaddr->sin6_family = AF_INET6;
+    memcpy(tmpaddr->sin6_addr.un.u8_addr, &ip[0], 16);
+    tmpaddr->sin6_port = htons(port);
+    tmpaddr->sin6_scope_id = ip.zone();
+  } else {
+#endif
+    struct sockaddr_in *tmpaddr = (struct sockaddr_in *)&serveraddr;
+    sockfd = socket(AF_INET, SOCK_STREAM, 0);
+    tmpaddr->sin_family = AF_INET;
+    tmpaddr->sin_addr.s_addr = ip;
+    tmpaddr->sin_port = htons(port);
+#if CONFIG_LWIP_IPV6
+  }
+#endif
+  if (sockfd < 0) {
+    log_e("socket: %d", errno);
+    return 0;
+  }
+  fcntl(sockfd, F_SETFL, fcntl(sockfd, F_GETFL, 0) | O_NONBLOCK);
+
+  fd_set fdset;
+  struct timeval tv;
+  FD_ZERO(&fdset);
+  FD_SET(sockfd, &fdset);
+  tv.tv_sec = _timeout / 1000;
+  tv.tv_usec = (_timeout % 1000) * 1000;
+
+#ifdef ESP_IDF_VERSION_MAJOR
+  int res = lwip_connect(sockfd, (struct sockaddr *)&serveraddr, sizeof(serveraddr));
+#else
+  int res = lwip_connect_r(sockfd, (struct sockaddr *)&serveraddr, sizeof(serveraddr));
+#endif
+  if (res < 0 && errno != EINPROGRESS) {
+    log_e("connect on fd %d, errno: %d, \"%s\"", sockfd, errno, strerror(errno));
+    close(sockfd);
+    return 0;
+  }
+
+  res = select(sockfd + 1, nullptr, &fdset, nullptr, _timeout < 0 ? nullptr : &tv);
+  if (res < 0) {
+    log_e("select on fd %d, errno: %d, \"%s\"", sockfd, errno, strerror(errno));
+    close(sockfd);
+    return 0;
+  } else if (res == 0) {
+    log_i("select returned due to timeout %d ms for fd %d", _timeout, sockfd);
+    close(sockfd);
+    return 0;
+  } else {
+    int sockerr;
+    socklen_t len = (socklen_t)sizeof(int);
+    res = getsockopt(sockfd, SOL_SOCKET, SO_ERROR, &sockerr, &len);
+
+    if (res < 0) {
+      log_e("getsockopt on fd %d, errno: %d, \"%s\"", sockfd, errno, strerror(errno));
+      close(sockfd);
+      return 0;
+    }
+
+    if (sockerr != 0) {
+      log_e("socket error on fd %d, errno: %d, \"%s\"", sockfd, sockerr, strerror(sockerr));
+      close(sockfd);
+      return 0;
+    }
+  }
+
+#define ROE_WIFICLIENT(x, msg)                                                                           \
+  {                                                                                                      \
+    if (((x) < 0)) {                                                                                     \
+      log_e("Setsockopt '" msg "'' on fd %d failed. errno: %d, \"%s\"", sockfd, errno, strerror(errno)); \
+      return 0;                                                                                          \
+    }                                                                                                    \
+  }
+  ROE_WIFICLIENT(setsockopt(sockfd, SOL_SOCKET, SO_SNDTIMEO, &tv, sizeof(tv)), "SO_SNDTIMEO");
+  ROE_WIFICLIENT(setsockopt(sockfd, SOL_SOCKET, SO_RCVTIMEO, &tv, sizeof(tv)), "SO_RCVTIMEO");
+
+  // These are also set in NetworkClientSecure, should be set here too?
+  //ROE_WIFICLIENT(setsockopt(sockfd, IPPROTO_TCP, TCP_NODELAY, &enable, sizeof(enable)),"TCP_NODELAY");
+  //ROE_WIFICLIENT (setsockopt(sockfd, SOL_SOCKET, SO_KEEPALIVE, &enable, sizeof(enable)),"SO_KEEPALIVE");
+
+  fcntl(sockfd, F_SETFL, fcntl(sockfd, F_GETFL, 0) & (~O_NONBLOCK));
+  clientSocketHandle.reset(new NetworkClientSocketHandle(sockfd));
+  _rxBuffer.reset(new NetworkClientRxBuffer(sockfd));
+
+  _connected = true;
+  return 1;
+}
+
+int NetworkClient::connect(const char *host, uint16_t port) {
+  return connect(host, port, _timeout);
+}
+
+int NetworkClient::connect(const char *host, uint16_t port, int32_t timeout_ms) {
+  IPAddress srv((uint32_t)0);
+  if (!Network.hostByName(host, srv)) {
+    return 0;
+  }
+  return connect(srv, port, timeout_ms);
+}
+
+int NetworkClient::setSocketOption(int option, char *value, size_t len) {
+  return setSocketOption(SOL_SOCKET, option, (const void *)value, len);
+}
+
+int NetworkClient::setSocketOption(int level, int option, const void *value, size_t len) {
+  int res = setsockopt(fd(), level, option, value, len);
+  if (res < 0) {
+    log_e("fail on %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
+  }
+  return res;
+}
+
+int NetworkClient::getSocketOption(int level, int option, const void *value, size_t size) {
+  int res = getsockopt(fd(), level, option, (char *)value, (socklen_t *)&size);
+  if (res < 0) {
+    log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
+  }
+  return res;
+}
+
+int NetworkClient::setOption(int option, int *value) {
+  return setSocketOption(IPPROTO_TCP, option, (const void *)value, sizeof(int));
+}
+
+int NetworkClient::getOption(int option, int *value) {
+  socklen_t size = sizeof(int);
+  int res = getsockopt(fd(), IPPROTO_TCP, option, (char *)value, &size);
+  if (res < 0) {
+    log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
+  }
+  return res;
+}
+
+void NetworkClient::setConnectionTimeout(uint32_t milliseconds) {
+  _timeout = milliseconds;
+}
+
+int NetworkClient::setNoDelay(bool nodelay) {
+  int flag = nodelay;
+  return setOption(TCP_NODELAY, &flag);
+}
+
+bool NetworkClient::getNoDelay() {
+  int flag = 0;
+  getOption(TCP_NODELAY, &flag);
+  return flag;
+}
+
+size_t NetworkClient::write(uint8_t data) {
+  return write(&data, 1);
+}
+
+int NetworkClient::read() {
+  uint8_t data = 0;
+  int res = read(&data, 1);
+  if (res < 0) {
+    return res;
+  }
+  if (res == 0) {  //  No data available.
+    return -1;
+  }
+  return data;
+}
+
+void NetworkClient::flush() {
+  clear();
+}
+
+size_t NetworkClient::write(const uint8_t *buf, size_t size) {
+  int res = 0;
+  int retry = WIFI_CLIENT_MAX_WRITE_RETRY;
+  int socketFileDescriptor = fd();
+  size_t totalBytesSent = 0;
+  size_t bytesRemaining = size;
+
+  if (!_connected || (socketFileDescriptor < 0)) {
+    return 0;
+  }
+
+  while (retry) {
+    //use select to make sure the socket is ready for writing
+    fd_set set;
+    struct timeval tv;
+    FD_ZERO(&set);                       // empties the set
+    FD_SET(socketFileDescriptor, &set);  // adds FD to the set
+    tv.tv_sec = 0;
+    tv.tv_usec = WIFI_CLIENT_SELECT_TIMEOUT_US;
+    retry--;
+
+    if (_lastWriteTimeout != _timeout) {
+      if (fd() >= 0) {
+        struct timeval timeout_tv;
+        timeout_tv.tv_sec = _timeout / 1000;
+        timeout_tv.tv_usec = (_timeout % 1000) * 1000;
+        if (setSocketOption(SO_SNDTIMEO, (char *)&timeout_tv, sizeof(struct timeval)) >= 0) {
+          _lastWriteTimeout = _timeout;
+        }
+      }
+    }
+
+    if (select(socketFileDescriptor + 1, NULL, &set, NULL, &tv) < 0) {
+      return 0;
+    }
+
+    if (FD_ISSET(socketFileDescriptor, &set)) {
+      res = send(socketFileDescriptor, (void *)buf, bytesRemaining, MSG_DONTWAIT);
+      if (res > 0) {
+        totalBytesSent += res;
+        if (totalBytesSent >= size) {
+          //completed successfully
+          retry = 0;
+        } else {
+          buf += res;
+          bytesRemaining -= res;
+          retry = WIFI_CLIENT_MAX_WRITE_RETRY;
+        }
+      } else if (res < 0) {
+        log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
+        if (errno != EAGAIN) {
+          //if resource was busy, can try again, otherwise give up
+          stop();
+          res = 0;
+          retry = 0;
+        }
+      } else {
+        // Try again
+      }
+    }
+  }
+  return totalBytesSent;
+}
+
+size_t NetworkClient::write_P(PGM_P buf, size_t size) {
+  return write(buf, size);
+}
+
+size_t NetworkClient::write(Stream &stream) {
+  uint8_t *buf = (uint8_t *)malloc(1360);
+  if (!buf) {
+    return 0;
+  }
+  size_t toRead = 0, toWrite = 0, written = 0;
+  size_t available = stream.available();
+  while (available) {
+    toRead = (available > 1360) ? 1360 : available;
+    toWrite = stream.readBytes(buf, toRead);
+    written += write(buf, toWrite);
+    available = stream.available();
+  }
+  free(buf);
+  return written;
+}
+
+int NetworkClient::read(uint8_t *buf, size_t size) {
+  if (_lastReadTimeout != _timeout) {
+    if (fd() >= 0) {
+      struct timeval timeout_tv;
+      timeout_tv.tv_sec = _timeout / 1000;
+      timeout_tv.tv_usec = (_timeout % 1000) * 1000;
+      if (setSocketOption(SO_RCVTIMEO, (char *)&timeout_tv, sizeof(struct timeval)) >= 0) {
+        _lastReadTimeout = _timeout;
+      }
+    }
+  }
+
+  int res = -1;
+  if (_rxBuffer) {
+    res = _rxBuffer->read(buf, size);
+    if (_rxBuffer->failed()) {
+      log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
+      stop();
+    }
+  }
+  return res;
+}
+
+size_t NetworkClient::readBytes(char *buffer, size_t length) {
+  size_t left = length, sofar = 0;
+  int r = 0, to = millis() + getTimeout();
+  while (left) {
+    r = read((uint8_t *)buffer + sofar, left);
+    if (r < 0) {
+      // Error has occurred
+      break;
+    }
+    if (r > 0) {
+      // We got some data
+      left -= r;
+      sofar += r;
+      to = millis() + getTimeout();
+    } else {
+      // We got no data
+      if (millis() >= to) {
+        // We have waited for data enough
+        log_w("Timeout waiting for data on fd %d", fd());
+        break;
+      }
+      // Allow other tasks to run
+      delay(2);
+    }
+  }
+  return sofar;
+}
+
+int NetworkClient::peek() {
+  int res = -1;
+  if (fd() >= 0 && _rxBuffer) {
+    res = _rxBuffer->peek();
+    if (_rxBuffer->failed()) {
+      log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
+      stop();
+    }
+  }
+  return res;
+}
+
+int NetworkClient::available() {
+  if (fd() < 0 || !_rxBuffer) {
+    return 0;
+  }
+  int res = _rxBuffer->available();
+  if (_rxBuffer->failed()) {
+    log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
+    stop();
+  }
+  return res;
+}
+
+void NetworkClient::clear() {
+  if (_rxBuffer != nullptr) {
+    _rxBuffer->clear();
+  }
+}
+
+uint8_t NetworkClient::connected() {
+  if (fd() == -1 && _connected) {
+    stop();
+  }
+  if (_connected) {
+    uint8_t dummy;
+    int res = recv(fd(), &dummy, 1, MSG_DONTWAIT | MSG_PEEK);
+    // avoid unused var warning by gcc
+    (void)res;
+    // recv only sets errno if res is <= 0
+    if (res <= 0) {
+      switch (errno) {
+        case EWOULDBLOCK:
+        case ENOENT:  //caused by vfs
+          _connected = true;
+          break;
+        case ENOTCONN:
+        case EPIPE:
+        case ECONNRESET:
+        case ECONNREFUSED:
+        case ECONNABORTED:
+          _connected = false;
+          log_d("Disconnected: RES: %d, ERR: %d", res, errno);
+          break;
+        default:
+          log_i("Unexpected: RES: %d, ERR: %d", res, errno);
+          _connected = true;
+          break;
+      }
+    } else {
+      _connected = true;
+    }
+  }
+  return _connected;
+}
+
+IPAddress NetworkClient::remoteIP(int fd) const {
+  struct sockaddr_storage addr;
+  socklen_t len = sizeof addr;
+  getpeername(fd, (struct sockaddr *)&addr, &len);
+
+  // IPv4 socket, old way
+  if (((struct sockaddr *)&addr)->sa_family == AF_INET) {
+    struct sockaddr_in *s = (struct sockaddr_in *)&addr;
+    return IPAddress((uint32_t)(s->sin_addr.s_addr));
+  }
+
+#if CONFIG_LWIP_IPV6
+  // IPv6, but it might be IPv4 mapped address
+  if (((struct sockaddr *)&addr)->sa_family == AF_INET6) {
+    struct sockaddr_in6 *saddr6 = (struct sockaddr_in6 *)&addr;
+    if (IN6_IS_ADDR_V4MAPPED(saddr6->sin6_addr.un.u32_addr)) {
+      return IPAddress(IPv4, (uint8_t *)saddr6->sin6_addr.s6_addr + IPADDRESS_V4_BYTES_INDEX);
+    } else {
+      return IPAddress(IPv6, (uint8_t *)(saddr6->sin6_addr.s6_addr), saddr6->sin6_scope_id);
+    }
+  }
+  log_e("NetworkClient::remoteIP Not AF_INET or AF_INET6?");
+#endif
+  return (IPAddress(0, 0, 0, 0));
+}
+
+uint16_t NetworkClient::remotePort(int fd) const {
+  struct sockaddr_storage addr;
+  socklen_t len = sizeof addr;
+  getpeername(fd, (struct sockaddr *)&addr, &len);
+  struct sockaddr_in *s = (struct sockaddr_in *)&addr;
+  return ntohs(s->sin_port);
+}
+
+IPAddress NetworkClient::remoteIP() const {
+  return remoteIP(fd());
+}
+
+uint16_t NetworkClient::remotePort() const {
+  return remotePort(fd());
+}
+
+IPAddress NetworkClient::localIP(int fd) const {
+  struct sockaddr_storage addr;
+  socklen_t len = sizeof addr;
+  getsockname(fd, (struct sockaddr *)&addr, &len);
+
+  // IPv4 socket, old way
+  if (((struct sockaddr *)&addr)->sa_family == AF_INET) {
+    struct sockaddr_in *s = (struct sockaddr_in *)&addr;
+    return IPAddress((uint32_t)(s->sin_addr.s_addr));
+  }
+
+#if CONFIG_LWIP_IPV6
+  // IPv6, but it might be IPv4 mapped address
+  if (((struct sockaddr *)&addr)->sa_family == AF_INET6) {
+    struct sockaddr_in6 *saddr6 = (struct sockaddr_in6 *)&addr;
+    if (IN6_IS_ADDR_V4MAPPED(saddr6->sin6_addr.un.u32_addr)) {
+      return IPAddress(IPv4, (uint8_t *)saddr6->sin6_addr.s6_addr + IPADDRESS_V4_BYTES_INDEX);
+    } else {
+      return IPAddress(IPv6, (uint8_t *)(saddr6->sin6_addr.s6_addr), saddr6->sin6_scope_id);
+    }
+  }
+  log_e("NetworkClient::localIP Not AF_INET or AF_INET6?");
+#endif
+  return (IPAddress(0, 0, 0, 0));
+}
+
+uint16_t NetworkClient::localPort(int fd) const {
+  struct sockaddr_storage addr;
+  socklen_t len = sizeof addr;
+  getsockname(fd, (struct sockaddr *)&addr, &len);
+  struct sockaddr_in *s = (struct sockaddr_in *)&addr;
+  return ntohs(s->sin_port);
+}
+
+IPAddress NetworkClient::localIP() const {
+  return localIP(fd());
+}
+
+uint16_t NetworkClient::localPort() const {
+  return localPort(fd());
+}
+
+bool NetworkClient::operator==(const NetworkClient &rhs) {
+  return clientSocketHandle == rhs.clientSocketHandle && remotePort() == rhs.remotePort() && remoteIP() == rhs.remoteIP();
+}
+
+int NetworkClient::fd() const {
+  if (clientSocketHandle == NULL) {
+    return -1;
+  } else {
+    return clientSocketHandle->fd();
+  }
+}
+
+void NetworkClient::setSSE(bool sse) {
+  _sse = sse;
+}
+
+bool NetworkClient::isSSE() {
+  return _sse;
+}
diff --git a/libraries/Network/src/NetworkClient.h b/libraries/Network/src/NetworkClient.h
new file mode 100644
index 00000000000..52df868a0b0
--- /dev/null
+++ b/libraries/Network/src/NetworkClient.h
@@ -0,0 +1,112 @@
+/*
+  Client.h - Base class that provides Client
+  Copyright (c) 2011 Adrian McEwen.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include "Arduino.h"
+#include "Client.h"
+#include <memory>
+
+class NetworkClientSocketHandle;
+class NetworkClientRxBuffer;
+
+class ESPLwIPClient : public Client {
+public:
+  virtual void setConnectionTimeout(uint32_t milliseconds) = 0;
+  using Client::connect;
+  virtual int connect(IPAddress ip, uint16_t port, int32_t timeout) = 0;
+  virtual int connect(const char *host, uint16_t port, int32_t timeout) = 0;
+};
+
+class NetworkClient : public ESPLwIPClient {
+protected:
+  std::shared_ptr<NetworkClientSocketHandle> clientSocketHandle = nullptr;
+  std::shared_ptr<NetworkClientRxBuffer> _rxBuffer = nullptr;
+  bool _connected = false;
+  bool _sse = false;
+  int _timeout;
+  int _lastWriteTimeout = 0;
+  int _lastReadTimeout = 0;
+
+public:
+  NetworkClient *next;
+  NetworkClient();
+  NetworkClient(int fd);
+  ~NetworkClient();
+  int connect(IPAddress ip, uint16_t port);
+  int connect(IPAddress ip, uint16_t port, int32_t timeout_ms);
+  int connect(const char *host, uint16_t port);
+  int connect(const char *host, uint16_t port, int32_t timeout_ms);
+  size_t write(uint8_t data);
+  size_t write(const uint8_t *buf, size_t size);
+  size_t write_P(PGM_P buf, size_t size);
+  size_t write(Stream &stream);
+  [[deprecated("Use clear() instead.")]]
+  void flush();  // Print::flush tx
+  int available();
+  int read();
+  int read(uint8_t *buf, size_t size);
+  size_t readBytes(char *buffer, size_t length);
+  size_t readBytes(uint8_t *buffer, size_t length) {
+    return readBytes((char *)buffer, length);
+  }
+  int peek();
+  void clear();  // clear rx
+  void stop();
+  uint8_t connected();
+  void setSSE(bool sse);
+  bool isSSE();
+
+  operator bool() {
+    return connected();
+  }
+  bool operator==(const bool value) {
+    return bool() == value;
+  }
+  bool operator!=(const bool value) {
+    return bool() != value;
+  }
+  bool operator==(const NetworkClient &);
+  bool operator!=(const NetworkClient &rhs) {
+    return !this->operator==(rhs);
+  };
+
+  virtual int fd() const;
+
+  int setSocketOption(int option, char *value, size_t len);
+  int setSocketOption(int level, int option, const void *value, size_t len);
+  int getSocketOption(int level, int option, const void *value, size_t size);
+  int setOption(int option, int *value);
+  int getOption(int option, int *value);
+  void setConnectionTimeout(uint32_t milliseconds);
+  int setNoDelay(bool nodelay);
+  bool getNoDelay();
+
+  IPAddress remoteIP() const;
+  IPAddress remoteIP(int fd) const;
+  uint16_t remotePort() const;
+  uint16_t remotePort(int fd) const;
+  IPAddress localIP() const;
+  IPAddress localIP(int fd) const;
+  uint16_t localPort() const;
+  uint16_t localPort(int fd) const;
+
+  //friend class NetworkServer;
+  using Print::write;
+};
diff --git a/libraries/Network/src/NetworkEvents.cpp b/libraries/Network/src/NetworkEvents.cpp
new file mode 100644
index 00000000000..161e55c5d01
--- /dev/null
+++ b/libraries/Network/src/NetworkEvents.cpp
@@ -0,0 +1,414 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "NetworkEvents.h"
+#include "NetworkManager.h"
+#include "esp_task.h"
+#include "esp32-hal.h"
+
+#ifndef ARDUINO_NETWORK_EVENT_TASK_STACK_SIZE
+#define ARDUINO_NETWORK_EVENT_TASK_STACK_SIZE 4096
+#endif
+
+NetworkEvents::NetworkEvents() : _arduino_event_group(NULL), _arduino_event_queue(NULL), _arduino_event_task_handle(NULL) {}
+
+NetworkEvents::~NetworkEvents() {
+  if (_arduino_event_task_handle != NULL) {
+    vTaskDelete(_arduino_event_task_handle);
+    _arduino_event_task_handle = NULL;
+  }
+  if (_arduino_event_group != NULL) {
+    vEventGroupDelete(_arduino_event_group);
+    _arduino_event_group = NULL;
+  }
+  if (_arduino_event_queue != NULL) {
+    arduino_event_t *event = NULL;
+    // consume queue
+    while (xQueueReceive(_arduino_event_queue, &event, 0) == pdTRUE) {
+      delete event;
+    }
+    vQueueDelete(_arduino_event_queue);
+    _arduino_event_queue = NULL;
+  }
+}
+
+static uint32_t _initial_bits = 0;
+
+bool NetworkEvents::initNetworkEvents() {
+  if (!_arduino_event_group) {
+    _arduino_event_group = xEventGroupCreate();
+    if (!_arduino_event_group) {
+      log_e("Network Event Group Create Failed!");
+      return false;
+    }
+    xEventGroupSetBits(_arduino_event_group, _initial_bits);
+  }
+
+  if (!_arduino_event_queue) {
+    _arduino_event_queue = xQueueCreate(32, sizeof(arduino_event_t *));
+    if (!_arduino_event_queue) {
+      log_e("Network Event Queue Create Failed!");
+      return false;
+    }
+  }
+
+  esp_err_t err = esp_event_loop_create_default();
+  if (err != ESP_OK && err != ESP_ERR_INVALID_STATE) {
+    log_e("esp_event_loop_create_default failed!");
+    return err;
+  }
+
+  if (!_arduino_event_task_handle) {
+    xTaskCreateUniversal(
+      [](void *self) {
+        static_cast<NetworkEvents *>(self)->_checkForEvent();
+      },
+      "arduino_events",                       // label
+      ARDUINO_NETWORK_EVENT_TASK_STACK_SIZE,  // event task's stack size
+      this, ESP_TASKD_EVENT_PRIO - 1, &_arduino_event_task_handle, ARDUINO_EVENT_RUNNING_CORE
+    );
+    if (!_arduino_event_task_handle) {
+      log_e("Network Event Task Start Failed!");
+      return false;
+    }
+  }
+
+  return true;
+}
+
+bool NetworkEvents::postEvent(const arduino_event_t *data) {
+  if (data == NULL || _arduino_event_queue == NULL) {
+    return false;
+  }
+  arduino_event_t *event = new arduino_event_t();
+  if (event == NULL) {
+    log_e("Arduino Event Malloc Failed!");
+    return false;
+  }
+
+  memcpy(event, data, sizeof(arduino_event_t));
+  if (xQueueSend(_arduino_event_queue, &event, portMAX_DELAY) != pdPASS) {
+    log_e("Arduino Event Send Failed!");
+    delete event;  // release mem on error
+    return false;
+  }
+  return true;
+}
+
+void NetworkEvents::_checkForEvent() {
+  // this task can't run without the queue
+  if (_arduino_event_queue == NULL) {
+    _arduino_event_task_handle = NULL;
+    vTaskDelete(NULL);
+    return;
+  }
+
+  for (;;) {
+    arduino_event_t *event = NULL;
+    // wait for an event on a queue
+    if (xQueueReceive(_arduino_event_queue, &event, portMAX_DELAY) != pdTRUE) {
+      continue;
+    }
+    if (event == NULL) {
+      continue;
+    }
+    log_v("Network Event: %d - %s", event->event_id, eventName(event->event_id));
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+    std::unique_lock<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+    // iterate over registered callbacks
+    for (auto &i : _cbEventList) {
+      if (i.cb || i.fcb || i.scb) {
+        if (i.event == (arduino_event_id_t)event->event_id || i.event == ARDUINO_EVENT_MAX) {
+          if (i.cb) {
+            i.cb((arduino_event_id_t)event->event_id);
+            continue;
+          }
+
+          if (i.fcb) {
+            i.fcb((arduino_event_id_t)event->event_id, (arduino_event_info_t)event->event_info);
+            continue;
+          }
+
+          i.scb(event);
+        }
+      }
+    }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+    lock.unlock();
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+    // release the event object's memory
+    delete event;
+  }
+
+  vTaskDelete(NULL);
+}
+
+template<typename T, typename... U> static size_t getStdFunctionAddress(std::function<T(U...)> f) {
+  typedef T(fnType)(U...);
+  fnType **fnPointer = f.template target<fnType *>();
+  if (fnPointer != nullptr) {
+    return (size_t)*fnPointer;
+  }
+  return (size_t)fnPointer;
+}
+
+network_event_handle_t NetworkEvents::onEvent(NetworkEventCb cbEvent, arduino_event_id_t event) {
+  if (!cbEvent) {
+    return 0;
+  }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.emplace_back(++_current_id, cbEvent, nullptr, nullptr, event);
+  return _cbEventList.back().id;
+}
+
+network_event_handle_t NetworkEvents::onEvent(NetworkEventFuncCb cbEvent, arduino_event_id_t event) {
+  if (!cbEvent) {
+    return 0;
+  }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.emplace_back(++_current_id, nullptr, cbEvent, nullptr, event);
+  return _cbEventList.back().id;
+}
+
+network_event_handle_t NetworkEvents::onEvent(NetworkEventSysCb cbEvent, arduino_event_id_t event) {
+  if (!cbEvent) {
+    return 0;
+  }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.emplace_back(++_current_id, nullptr, nullptr, cbEvent, event);
+  return _cbEventList.back().id;
+}
+
+network_event_handle_t NetworkEvents::onSysEvent(NetworkEventCb cbEvent, arduino_event_id_t event) {
+  if (!cbEvent) {
+    return 0;
+  }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.emplace(_cbEventList.begin(), ++_current_id, cbEvent, nullptr, nullptr, event);
+  return _cbEventList.front().id;
+}
+
+network_event_handle_t NetworkEvents::onSysEvent(NetworkEventFuncCb cbEvent, arduino_event_id_t event) {
+  if (!cbEvent) {
+    return 0;
+  }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.emplace(_cbEventList.begin(), ++_current_id, nullptr, cbEvent, nullptr, event);
+  return _cbEventList.front().id;
+}
+
+network_event_handle_t NetworkEvents::onSysEvent(NetworkEventSysCb cbEvent, arduino_event_id_t event) {
+  if (!cbEvent) {
+    return 0;
+  }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.emplace(_cbEventList.begin(), ++_current_id, nullptr, nullptr, cbEvent, event);
+  return _cbEventList.front().id;
+}
+
+void NetworkEvents::removeEvent(NetworkEventCb cbEvent, arduino_event_id_t event) {
+  if (!cbEvent) {
+    return;
+  }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.erase(
+    std::remove_if(
+      _cbEventList.begin(), _cbEventList.end(),
+      [cbEvent, event](const NetworkEventCbList_t &e) {
+        return e.cb == cbEvent && e.event == event;
+      }
+    ),
+    _cbEventList.end()
+  );
+}
+
+void NetworkEvents::removeEvent(NetworkEventFuncCb cbEvent, arduino_event_id_t event) {
+  if (!cbEvent) {
+    return;
+  }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.erase(
+    std::remove_if(
+      _cbEventList.begin(), _cbEventList.end(),
+      [cbEvent, event](const NetworkEventCbList_t &e) {
+        return getStdFunctionAddress(e.fcb) == getStdFunctionAddress(cbEvent) && e.event == event;
+      }
+    ),
+    _cbEventList.end()
+  );
+}
+
+void NetworkEvents::removeEvent(NetworkEventSysCb cbEvent, arduino_event_id_t event) {
+  if (!cbEvent) {
+    return;
+  }
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.erase(
+    std::remove_if(
+      _cbEventList.begin(), _cbEventList.end(),
+      [cbEvent, event](const NetworkEventCbList_t &e) {
+        return e.scb == cbEvent && e.event == event;
+      }
+    ),
+    _cbEventList.end()
+  );
+}
+
+void NetworkEvents::removeEvent(network_event_handle_t id) {
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  std::lock_guard<std::mutex> lock(_mtx);
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  _cbEventList.erase(
+    std::remove_if(
+      _cbEventList.begin(), _cbEventList.end(),
+      [id](const NetworkEventCbList_t &e) {
+        return e.id == id;
+      }
+    ),
+    _cbEventList.end()
+  );
+}
+
+int NetworkEvents::setStatusBits(int bits) {
+  if (!_arduino_event_group) {
+    _initial_bits |= bits;
+    return _initial_bits;
+  }
+  return xEventGroupSetBits(_arduino_event_group, bits);
+}
+
+int NetworkEvents::clearStatusBits(int bits) {
+  if (!_arduino_event_group) {
+    _initial_bits &= ~bits;
+    return _initial_bits;
+  }
+  return xEventGroupClearBits(_arduino_event_group, bits);
+}
+
+int NetworkEvents::getStatusBits() const {
+  if (!_arduino_event_group) {
+    return _initial_bits;
+  }
+  return xEventGroupGetBits(_arduino_event_group);
+}
+
+int NetworkEvents::waitStatusBits(int bits, uint32_t timeout_ms) {
+  if (!_arduino_event_group) {
+    return 0;
+  }
+  return xEventGroupWaitBits(
+           _arduino_event_group,  // The event group being tested.
+           bits,                  // The bits within the event group to wait for.
+           pdFALSE,               // bits should be cleared before returning.
+           pdTRUE,                // Don't wait for all bits, any bit will do.
+           timeout_ms / portTICK_PERIOD_MS
+         )
+         & bits;  // Wait a maximum of timeout_ms for any bit to be set.
+}
+
+/**
+ * @brief Convert arduino_event_id_t to a C string.
+ * @param [in] id The event id to be converted.
+ * @return A string representation of the event id.
+ * @note: arduino_event_id_t values as of Mar 2023 (arduino-esp32 r2.0.7) are: 0-39 (ARDUINO_EVENT_MAX=40) and are defined in WiFiGeneric.h.
+ */
+const char *NetworkEvents::eventName(arduino_event_id_t id) {
+  switch (id) {
+    case ARDUINO_EVENT_ETH_START:        return "ETH_START";
+    case ARDUINO_EVENT_ETH_STOP:         return "ETH_STOP";
+    case ARDUINO_EVENT_ETH_CONNECTED:    return "ETH_CONNECTED";
+    case ARDUINO_EVENT_ETH_DISCONNECTED: return "ETH_DISCONNECTED";
+    case ARDUINO_EVENT_ETH_GOT_IP:       return "ETH_GOT_IP";
+    case ARDUINO_EVENT_ETH_LOST_IP:      return "ETH_LOST_IP";
+    case ARDUINO_EVENT_ETH_GOT_IP6:      return "ETH_GOT_IP6";
+    case ARDUINO_EVENT_PPP_START:        return "PPP_START";
+    case ARDUINO_EVENT_PPP_STOP:         return "PPP_STOP";
+    case ARDUINO_EVENT_PPP_CONNECTED:    return "PPP_CONNECTED";
+    case ARDUINO_EVENT_PPP_DISCONNECTED: return "PPP_DISCONNECTED";
+    case ARDUINO_EVENT_PPP_GOT_IP:       return "PPP_GOT_IP";
+    case ARDUINO_EVENT_PPP_LOST_IP:      return "PPP_LOST_IP";
+    case ARDUINO_EVENT_PPP_GOT_IP6:      return "PPP_GOT_IP6";
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+    case ARDUINO_EVENT_WIFI_OFF:                 return "WIFI_OFF";
+    case ARDUINO_EVENT_WIFI_READY:               return "WIFI_READY";
+    case ARDUINO_EVENT_WIFI_SCAN_DONE:           return "SCAN_DONE";
+    case ARDUINO_EVENT_WIFI_STA_START:           return "STA_START";
+    case ARDUINO_EVENT_WIFI_STA_STOP:            return "STA_STOP";
+    case ARDUINO_EVENT_WIFI_STA_CONNECTED:       return "STA_CONNECTED";
+    case ARDUINO_EVENT_WIFI_STA_DISCONNECTED:    return "STA_DISCONNECTED";
+    case ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE: return "STA_AUTHMODE_CHANGE";
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP:          return "STA_GOT_IP";
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP6:         return "STA_GOT_IP6";
+    case ARDUINO_EVENT_WIFI_STA_LOST_IP:         return "STA_LOST_IP";
+    case ARDUINO_EVENT_WIFI_AP_START:            return "AP_START";
+    case ARDUINO_EVENT_WIFI_AP_STOP:             return "AP_STOP";
+    case ARDUINO_EVENT_WIFI_AP_STACONNECTED:     return "AP_STACONNECTED";
+    case ARDUINO_EVENT_WIFI_AP_STADISCONNECTED:  return "AP_STADISCONNECTED";
+    case ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED:    return "AP_STAIPASSIGNED";
+    case ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED:   return "AP_PROBEREQRECVED";
+    case ARDUINO_EVENT_WIFI_AP_GOT_IP6:          return "AP_GOT_IP6";
+    case ARDUINO_EVENT_WIFI_FTM_REPORT:          return "FTM_REPORT";
+    case ARDUINO_EVENT_WPS_ER_SUCCESS:           return "WPS_ER_SUCCESS";
+    case ARDUINO_EVENT_WPS_ER_FAILED:            return "WPS_ER_FAILED";
+    case ARDUINO_EVENT_WPS_ER_TIMEOUT:           return "WPS_ER_TIMEOUT";
+    case ARDUINO_EVENT_WPS_ER_PIN:               return "WPS_ER_PIN";
+    case ARDUINO_EVENT_WPS_ER_PBC_OVERLAP:       return "WPS_ER_PBC_OVERLAP";
+    case ARDUINO_EVENT_SC_SCAN_DONE:             return "SC_SCAN_DONE";
+    case ARDUINO_EVENT_SC_FOUND_CHANNEL:         return "SC_FOUND_CHANNEL";
+    case ARDUINO_EVENT_SC_GOT_SSID_PSWD:         return "SC_GOT_SSID_PSWD";
+    case ARDUINO_EVENT_SC_SEND_ACK_DONE:         return "SC_SEND_ACK_DONE";
+    case ARDUINO_EVENT_PROV_INIT:                return "PROV_INIT";
+    case ARDUINO_EVENT_PROV_DEINIT:              return "PROV_DEINIT";
+    case ARDUINO_EVENT_PROV_START:               return "PROV_START";
+    case ARDUINO_EVENT_PROV_END:                 return "PROV_END";
+    case ARDUINO_EVENT_PROV_CRED_RECV:           return "PROV_CRED_RECV";
+    case ARDUINO_EVENT_PROV_CRED_FAIL:           return "PROV_CRED_FAIL";
+    case ARDUINO_EVENT_PROV_CRED_SUCCESS:        return "PROV_CRED_SUCCESS";
+#endif
+    default: return "";
+  }
+}
diff --git a/libraries/Network/src/NetworkEvents.h b/libraries/Network/src/NetworkEvents.h
new file mode 100644
index 00000000000..34a54cab092
--- /dev/null
+++ b/libraries/Network/src/NetworkEvents.h
@@ -0,0 +1,308 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "sdkconfig.h"
+#include "soc/soc_caps.h"
+#include "esp_err.h"
+#include "esp_event.h"
+#include "esp_netif_types.h"
+#if CONFIG_ETH_ENABLED
+#include "esp_eth_driver.h"
+#endif
+#include <functional>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+#include "freertos/event_groups.h"
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+#include <mutex>
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+#include "esp_wifi_types.h"
+#include "esp_smartconfig.h"
+#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI
+#include "network_provisioning/network_config.h"
+#endif
+#endif
+
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+constexpr int WIFI_SCANNING_BIT = BIT0;
+constexpr int WIFI_SCAN_DONE_BIT = BIT1;
+#endif
+
+#define NET_HAS_IP6_GLOBAL_BIT 0
+
+ESP_EVENT_DECLARE_BASE(ARDUINO_EVENTS);
+
+typedef enum {
+  ARDUINO_EVENT_NONE = 0,
+  ARDUINO_EVENT_ETH_START,
+  ARDUINO_EVENT_ETH_STOP,
+  ARDUINO_EVENT_ETH_CONNECTED,
+  ARDUINO_EVENT_ETH_DISCONNECTED,
+  ARDUINO_EVENT_ETH_GOT_IP,
+  ARDUINO_EVENT_ETH_LOST_IP,
+  ARDUINO_EVENT_ETH_GOT_IP6,
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+  ARDUINO_EVENT_WIFI_OFF = 100,
+  ARDUINO_EVENT_WIFI_READY,
+  ARDUINO_EVENT_WIFI_SCAN_DONE,
+  ARDUINO_EVENT_WIFI_FTM_REPORT,
+  ARDUINO_EVENT_WIFI_STA_START = 110,
+  ARDUINO_EVENT_WIFI_STA_STOP,
+  ARDUINO_EVENT_WIFI_STA_CONNECTED,
+  ARDUINO_EVENT_WIFI_STA_DISCONNECTED,
+  ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE,
+  ARDUINO_EVENT_WIFI_STA_GOT_IP,
+  ARDUINO_EVENT_WIFI_STA_GOT_IP6,
+  ARDUINO_EVENT_WIFI_STA_LOST_IP,
+  ARDUINO_EVENT_WIFI_AP_START = 130,
+  ARDUINO_EVENT_WIFI_AP_STOP,
+  ARDUINO_EVENT_WIFI_AP_STACONNECTED,
+  ARDUINO_EVENT_WIFI_AP_STADISCONNECTED,
+  ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED,
+  ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED,
+  ARDUINO_EVENT_WIFI_AP_GOT_IP6,
+  ARDUINO_EVENT_WPS_ER_SUCCESS = 140,
+  ARDUINO_EVENT_WPS_ER_FAILED,
+  ARDUINO_EVENT_WPS_ER_TIMEOUT,
+  ARDUINO_EVENT_WPS_ER_PIN,
+  ARDUINO_EVENT_WPS_ER_PBC_OVERLAP,
+  ARDUINO_EVENT_SC_SCAN_DONE = 150,
+  ARDUINO_EVENT_SC_FOUND_CHANNEL,
+  ARDUINO_EVENT_SC_GOT_SSID_PSWD,
+  ARDUINO_EVENT_SC_SEND_ACK_DONE,
+  ARDUINO_EVENT_PROV_INIT = 160,
+  ARDUINO_EVENT_PROV_DEINIT,
+  ARDUINO_EVENT_PROV_START,
+  ARDUINO_EVENT_PROV_END,
+  ARDUINO_EVENT_PROV_CRED_RECV,
+  ARDUINO_EVENT_PROV_CRED_FAIL,
+  ARDUINO_EVENT_PROV_CRED_SUCCESS,
+#endif
+  ARDUINO_EVENT_PPP_START = 200,
+  ARDUINO_EVENT_PPP_STOP,
+  ARDUINO_EVENT_PPP_CONNECTED,
+  ARDUINO_EVENT_PPP_DISCONNECTED,
+  ARDUINO_EVENT_PPP_GOT_IP,
+  ARDUINO_EVENT_PPP_LOST_IP,
+  ARDUINO_EVENT_PPP_GOT_IP6,
+  ARDUINO_EVENT_MAX
+} arduino_event_id_t;
+
+typedef union {
+  ip_event_ap_staipassigned_t wifi_ap_staipassigned;
+  ip_event_got_ip_t got_ip;
+  ip_event_got_ip6_t got_ip6;
+#if CONFIG_ETH_ENABLED
+  esp_eth_handle_t eth_connected;
+#endif
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+  wifi_event_sta_scan_done_t wifi_scan_done;
+  wifi_event_sta_authmode_change_t wifi_sta_authmode_change;
+  wifi_event_sta_connected_t wifi_sta_connected;
+  wifi_event_sta_disconnected_t wifi_sta_disconnected;
+  wifi_event_sta_wps_er_pin_t wps_er_pin;
+  wifi_event_sta_wps_fail_reason_t wps_fail_reason;
+  wifi_event_ap_probe_req_rx_t wifi_ap_probereqrecved;
+  wifi_event_ap_staconnected_t wifi_ap_staconnected;
+  wifi_event_ap_stadisconnected_t wifi_ap_stadisconnected;
+  wifi_event_ftm_report_t wifi_ftm_report;
+#endif
+#if SOC_WIFI_SUPPORTED
+  wifi_sta_config_t prov_cred_recv;
+#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI
+  network_prov_wifi_sta_fail_reason_t prov_fail_reason;
+#endif
+  smartconfig_event_got_ssid_pswd_t sc_got_ssid_pswd;
+#endif
+} arduino_event_info_t;
+
+/**
+ * @brief struct combines arduino event id and event's data object
+ *
+ */
+struct arduino_event_t {
+  arduino_event_id_t event_id;
+  arduino_event_info_t event_info;
+};
+
+// type aliases
+using NetworkEventCb = void (*)(arduino_event_id_t event);
+using NetworkEventFuncCb = std::function<void(arduino_event_id_t event, arduino_event_info_t info)>;
+using NetworkEventSysCb = void (*)(arduino_event_t *event);
+using network_event_handle_t = size_t;
+
+/**
+ * @brief Class that provides network events callback handling
+ * it registers user callback functions for event handling,
+ * maintains the queue of events and propagates the event among subscribed callbacks
+ * callback are called in the context of a dedicated task consuming the queue
+ *
+ */
+class NetworkEvents {
+public:
+  NetworkEvents();
+  ~NetworkEvents();
+
+  /**
+   * @brief register callback function to be executed on arduino event(s)
+   * @note if same handler is registered twice or more than same handler would be called twice or more times
+   *
+   * @param cbEvent static callback function
+   * @param event event to process, any event by default
+   * @return network_event_handle_t
+   */
+  network_event_handle_t onEvent(NetworkEventCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+
+  /**
+   * @brief register functional callback to be executed on arduino event(s)
+   * also used for lambda callbacks
+   * @note if same handler is registered twice or more than same handler would be called twice or more times
+   *
+   * @param cbEvent static callback function
+   * @param event event to process, any event by default
+   * @return network_event_handle_t
+   */
+  network_event_handle_t onEvent(NetworkEventFuncCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+
+  /**
+   * @brief register static system callback to be executed on arduino event(s)
+   * callback function would be supplied with a pointer to arduino_event_t structure as an argument
+   *
+   * @note if same handler is registered twice or more than same handler would be called twice or more times
+   *
+   * @param cbEvent static callback function
+   * @param event event to process, any event by default
+   * @return network_event_handle_t
+   */
+  network_event_handle_t onEvent(NetworkEventSysCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+
+  /**
+   * @brief unregister static function callback
+   * @note a better way to unregister callbacks is to save/unregister via network_event_handle_t
+   *
+   * @param cbEvent static callback function
+   * @param event event to process, any event by default
+   */
+  void removeEvent(NetworkEventCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+
+  /**
+   * @brief unregister functional callback
+   * @note a better way to unregister callbacks is to save/unregister via network_event_handle_t
+   * @note this does not work for lambda's! Do unregister via network_event_handle_t
+   *
+   * @param cbEvent functional callback
+   * @param event event to process, any event by default
+   */
+  void removeEvent(NetworkEventFuncCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX)
+    __attribute__((deprecated("removing functional callbacks via pointer is deprecated, use removeEvent(network_event_handle_t) instead")));
+
+  /**
+   * @brief unregister static system function callback
+   * @note a better way to unregister callbacks is to save/unregister via network_event_handle_t
+   *
+   * @param cbEvent static callback function
+   * @param event event to process, any event by default
+   */
+  void removeEvent(NetworkEventSysCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+
+  /**
+   * @brief unregister event callback via handler
+   *
+   * @param cbEvent static callback function
+   * @param event event to process, any event by default
+   */
+  void removeEvent(network_event_handle_t event_handle);
+
+  /**
+   * @brief get a human-readable name of an event by it's id
+   *
+   * @param id event id code
+   * @return const char* event name string
+   */
+  static const char *eventName(arduino_event_id_t id);
+
+  /**
+   * @brief post an event to the queue
+   * and propagade and event to subscribed handlers
+   * @note posting an event will trigger context switch from a lower priority task
+   *
+   * @param event a pointer to arduino_event_t struct
+   * @return true if event was queued susccessfuly
+   * @return false on memrory allocation error or queue is full
+   */
+  bool postEvent(const arduino_event_t *event);
+
+  int getStatusBits() const;
+  int waitStatusBits(int bits, uint32_t timeout_ms);
+  int setStatusBits(int bits);
+  int clearStatusBits(int bits);
+
+  friend class ESP_NetworkInterface;
+  friend class ETHClass;
+  friend class PPPClass;
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+  friend class STAClass;
+  friend class APClass;
+  friend class WiFiGenericClass;
+#endif
+
+protected:
+  bool initNetworkEvents();
+  // same as onEvent() but places newly added handler at the beginning of registered events list
+  network_event_handle_t onSysEvent(NetworkEventCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+  // same as onEvent() but places newly added handler at the beginning of registered events list
+  network_event_handle_t onSysEvent(NetworkEventFuncCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+  // same as onEvent() but places newly added handler at the beginning of registered events list
+  network_event_handle_t onSysEvent(NetworkEventSysCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+
+private:
+  /**
+   * @brief an object holds callback's definitions:
+   * - callback id
+   * - callback function pointers
+   * - binded event id
+   *
+   */
+  struct NetworkEventCbList_t {
+    network_event_handle_t id;
+    NetworkEventCb cb;
+    NetworkEventFuncCb fcb;
+    NetworkEventSysCb scb;
+    arduino_event_id_t event;
+
+    explicit NetworkEventCbList_t(
+      network_event_handle_t id, NetworkEventCb cb = nullptr, NetworkEventFuncCb fcb = nullptr, NetworkEventSysCb scb = nullptr,
+      arduino_event_id_t event = ARDUINO_EVENT_MAX
+    )
+      : id(id), cb(cb), fcb(fcb), scb(scb), event(event) {}
+  };
+
+  // define initial id's value
+  network_event_handle_t _current_id{0};
+
+  EventGroupHandle_t _arduino_event_group;
+  QueueHandle_t _arduino_event_queue;
+  TaskHandle_t _arduino_event_task_handle;
+
+  // registered events callbacks container
+  std::vector<NetworkEventCbList_t> _cbEventList;
+
+#if defined NETWORK_EVENTS_MUTEX && SOC_CPU_CORES_NUM > 1
+  // container access mutex
+  std::mutex _mtx;
+#endif  // defined NETWORK_EVENTS_MUTEX &&  SOC_CPU_CORES_NUM > 1
+
+  /**
+   * @brief task function that picks events from an event queue and calls registered callbacks
+   *
+   */
+  void _checkForEvent();
+};
diff --git a/libraries/Network/src/NetworkInterface.cpp b/libraries/Network/src/NetworkInterface.cpp
new file mode 100644
index 00000000000..01790ec2493
--- /dev/null
+++ b/libraries/Network/src/NetworkInterface.cpp
@@ -0,0 +1,860 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "NetworkInterface.h"
+#include "NetworkManager.h"
+#include "esp_netif.h"
+#include "esp_netif_defaults.h"
+#include "esp_system.h"
+#include "lwip/ip_addr.h"
+#include "lwip/err.h"
+#include "lwip/netif.h"
+#include "dhcpserver/dhcpserver.h"
+#include "dhcpserver/dhcpserver_options.h"
+#include "esp32-hal-log.h"
+
+static NetworkInterface *_interfaces[ESP_NETIF_ID_MAX] = {NULL, NULL, NULL, NULL, NULL, NULL};
+static esp_event_handler_instance_t _ip_ev_instance = NULL;
+
+static NetworkInterface *getNetifByEspNetif(esp_netif_t *esp_netif) {
+  for (int i = 0; i < ESP_NETIF_ID_MAX; ++i) {
+    if (_interfaces[i] != NULL && _interfaces[i]->netif() == esp_netif) {
+      return _interfaces[i];
+    }
+  }
+  return NULL;
+}
+
+NetworkInterface *getNetifByID(Network_Interface_ID id) {
+  if (id < ESP_NETIF_ID_MAX) {
+    return _interfaces[id];
+  }
+  return NULL;
+}
+
+#if CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM
+extern "C" int lwip_hook_ip6_input(struct pbuf *p, struct netif *inp) __attribute__((weak));
+extern "C" int lwip_hook_ip6_input(struct pbuf *p, struct netif *inp) {
+  if (ip6_addr_isany_val(inp->ip6_addr[0].u_addr.ip6)) {
+    // We don't have an LL address -> eat this packet here, so it won't get accepted on input netif
+    pbuf_free(p);
+    return 1;
+  }
+  return 0;
+}
+#endif
+
+static void _ip_event_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == IP_EVENT) {
+    NetworkInterface *netif = NULL;
+    if (event_id == IP_EVENT_STA_GOT_IP || event_id == IP_EVENT_ETH_GOT_IP || event_id == IP_EVENT_PPP_GOT_IP) {
+      ip_event_got_ip_t *event = (ip_event_got_ip_t *)event_data;
+      netif = getNetifByEspNetif(event->esp_netif);
+    } else if (event_id == IP_EVENT_STA_LOST_IP || event_id == IP_EVENT_PPP_LOST_IP || event_id == IP_EVENT_ETH_LOST_IP) {
+      ip_event_got_ip_t *event = (ip_event_got_ip_t *)event_data;
+      netif = getNetifByEspNetif(event->esp_netif);
+    } else if (event_id == IP_EVENT_GOT_IP6) {
+      ip_event_got_ip6_t *event = (ip_event_got_ip6_t *)event_data;
+      netif = getNetifByEspNetif(event->esp_netif);
+    } else if (event_id == IP_EVENT_AP_STAIPASSIGNED) {
+      ip_event_ap_staipassigned_t *event = (ip_event_ap_staipassigned_t *)event_data;
+      netif = getNetifByEspNetif(event->esp_netif);
+    }
+    if (netif != NULL) {
+      netif->_onIpEvent(event_id, event_data);
+    }
+  }
+}
+
+void NetworkInterface::_onIpEvent(int32_t event_id, void *event_data) {
+  arduino_event_t arduino_event;
+  arduino_event.event_id = ARDUINO_EVENT_MAX;
+  if (event_id == _got_ip_event_id) {
+    setStatusBits(ESP_NETIF_HAS_IP_BIT);
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    ip_event_got_ip_t *event = (ip_event_got_ip_t *)event_data;
+    log_v(
+      "%s Got %sIP: " IPSTR " MASK: " IPSTR " GW: " IPSTR, desc(), event->ip_changed ? "New " : "Same ", IP2STR(&event->ip_info.ip),
+      IP2STR(&event->ip_info.netmask), IP2STR(&event->ip_info.gw)
+    );
+#endif
+    memcpy(&arduino_event.event_info.got_ip, event_data, sizeof(ip_event_got_ip_t));
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+    if (_interface_id == ESP_NETIF_ID_STA) {
+      arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_GOT_IP;
+    } else
+#endif
+      if (_interface_id == ESP_NETIF_ID_PPP) {
+      arduino_event.event_id = ARDUINO_EVENT_PPP_GOT_IP;
+    } else if (_interface_id >= ESP_NETIF_ID_ETH && _interface_id < ESP_NETIF_ID_MAX) {
+      arduino_event.event_id = ARDUINO_EVENT_ETH_GOT_IP;
+    }
+  } else if (event_id == _lost_ip_event_id) {
+    clearStatusBits(ESP_NETIF_HAS_IP_BIT);
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    log_v("%s Lost IP", desc());
+#endif
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+    if (_interface_id == ESP_NETIF_ID_STA) {
+      arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_LOST_IP;
+    } else
+#endif
+      if (_interface_id == ESP_NETIF_ID_PPP) {
+      arduino_event.event_id = ARDUINO_EVENT_PPP_LOST_IP;
+    } else if (_interface_id >= ESP_NETIF_ID_ETH && _interface_id < ESP_NETIF_ID_MAX) {
+      arduino_event.event_id = ARDUINO_EVENT_ETH_LOST_IP;
+    }
+#if CONFIG_LWIP_IPV6
+  } else if (event_id == IP_EVENT_GOT_IP6) {
+    ip_event_got_ip6_t *event = (ip_event_got_ip6_t *)event_data;
+    esp_ip6_addr_type_t addr_type = esp_netif_ip6_get_addr_type(&event->ip6_info.ip);
+    if (addr_type == ESP_IP6_ADDR_IS_GLOBAL) {
+      setStatusBits(ESP_NETIF_HAS_GLOBAL_IP6_BIT);
+    } else if (addr_type == ESP_IP6_ADDR_IS_LINK_LOCAL) {
+      setStatusBits(ESP_NETIF_HAS_LOCAL_IP6_BIT);
+    }
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    static const char *addr_types[] = {"UNKNOWN", "GLOBAL", "LINK_LOCAL", "SITE_LOCAL", "UNIQUE_LOCAL", "IPV4_MAPPED_IPV6"};
+    log_v(
+      "IF %s Got IPv6: Interface: %d, IP Index: %d, Type: %s, Zone: %d, Address: " IPV6STR, desc(), _interface_id, event->ip_index, addr_types[addr_type],
+      event->ip6_info.ip.zone, IPV62STR(event->ip6_info.ip)
+    );
+#endif
+    memcpy(&arduino_event.event_info.got_ip6, event_data, sizeof(ip_event_got_ip6_t));
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+    if (_interface_id == ESP_NETIF_ID_STA) {
+      arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_GOT_IP6;
+    } else if (_interface_id == ESP_NETIF_ID_AP) {
+      arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_GOT_IP6;
+    } else
+#endif
+      if (_interface_id == ESP_NETIF_ID_PPP) {
+      arduino_event.event_id = ARDUINO_EVENT_PPP_GOT_IP6;
+    } else if (_interface_id >= ESP_NETIF_ID_ETH && _interface_id < ESP_NETIF_ID_MAX) {
+      arduino_event.event_id = ARDUINO_EVENT_ETH_GOT_IP6;
+    }
+#endif /* CONFIG_LWIP_IPV6 */
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+  } else if (event_id == IP_EVENT_AP_STAIPASSIGNED && _interface_id == ESP_NETIF_ID_AP) {
+    setStatusBits(ESP_NETIF_HAS_IP_BIT);
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    ip_event_ap_staipassigned_t *event = (ip_event_ap_staipassigned_t *)event_data;
+    log_v(
+      "%s Assigned IP: " IPSTR " to MAC: %02X:%02X:%02X:%02X:%02X:%02X", desc(), IP2STR(&event->ip), event->mac[0], event->mac[1], event->mac[2], event->mac[3],
+      event->mac[4], event->mac[5]
+    );
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED;
+    memcpy(&arduino_event.event_info.wifi_ap_staipassigned, event_data, sizeof(ip_event_ap_staipassigned_t));
+#endif
+  }
+
+  if (arduino_event.event_id < ARDUINO_EVENT_MAX) {
+    Network.postEvent(&arduino_event);
+  }
+}
+
+NetworkInterface::NetworkInterface()
+  : _esp_netif(NULL), _interface_event_group(NULL), _initial_bits(0), _got_ip_event_id(-1), _lost_ip_event_id(-1), _interface_id(ESP_NETIF_ID_MAX) {}
+
+NetworkInterface::~NetworkInterface() {
+  destroyNetif();
+}
+
+IPAddress NetworkInterface::calculateNetworkID(IPAddress ip, IPAddress subnet) const {
+  IPAddress networkID;
+
+  for (size_t i = 0; i < 4; i++) {
+    networkID[i] = subnet[i] & ip[i];
+  }
+
+  return networkID;
+}
+
+IPAddress NetworkInterface::calculateBroadcast(IPAddress ip, IPAddress subnet) const {
+  IPAddress broadcastIp;
+
+  for (int i = 0; i < 4; i++) {
+    broadcastIp[i] = ~subnet[i] | ip[i];
+  }
+
+  return broadcastIp;
+}
+
+uint8_t NetworkInterface::calculateSubnetCIDR(IPAddress subnetMask) const {
+  uint8_t CIDR = 0;
+
+  for (uint8_t i = 0; i < 4; i++) {
+    if (subnetMask[i] == 0x80) {  // 128
+      CIDR += 1;
+    } else if (subnetMask[i] == 0xC0) {  // 192
+      CIDR += 2;
+    } else if (subnetMask[i] == 0xE0) {  // 224
+      CIDR += 3;
+    } else if (subnetMask[i] == 0xF0) {  // 242
+      CIDR += 4;
+    } else if (subnetMask[i] == 0xF8) {  // 248
+      CIDR += 5;
+    } else if (subnetMask[i] == 0xFC) {  // 252
+      CIDR += 6;
+    } else if (subnetMask[i] == 0xFE) {  // 254
+      CIDR += 7;
+    } else if (subnetMask[i] == 0xFF) {  // 255
+      CIDR += 8;
+    }
+  }
+
+  return CIDR;
+}
+
+int NetworkInterface::setStatusBits(int bits) {
+  if (!_interface_event_group) {
+    _initial_bits |= bits;
+    return _initial_bits;
+  }
+  return xEventGroupSetBits(_interface_event_group, bits);
+}
+
+int NetworkInterface::clearStatusBits(int bits) {
+  if (!_interface_event_group) {
+    _initial_bits &= ~bits;
+    return _initial_bits;
+  }
+  return xEventGroupClearBits(_interface_event_group, bits);
+}
+
+int NetworkInterface::getStatusBits() const {
+  if (!_interface_event_group) {
+    return _initial_bits;
+  }
+  return xEventGroupGetBits(_interface_event_group);
+}
+
+int NetworkInterface::waitStatusBits(int bits, uint32_t timeout_ms) const {
+  if (!_interface_event_group) {
+    return 0;
+  }
+  bits = xEventGroupWaitBits(
+           _interface_event_group,  // The event group being tested.
+           bits,                    // The bits within the event group to wait for.
+           pdFALSE,                 // bits should be cleared before returning.
+           pdTRUE,                  // Don't wait for all bits, any bit will do.
+           timeout_ms / portTICK_PERIOD_MS
+         )
+         & bits;  // Wait a maximum of timeout_ms for any bit to be set.
+  return bits;
+}
+
+void NetworkInterface::destroyNetif() {
+  if (_ip_ev_instance != NULL) {
+    bool do_not_unreg_ev_handler = false;
+    for (int i = 0; i < ESP_NETIF_ID_MAX; ++i) {
+      if (_interfaces[i] != NULL && _interfaces[i] != this) {
+        do_not_unreg_ev_handler = true;
+        break;
+      }
+    }
+    if (!do_not_unreg_ev_handler) {
+      if (esp_event_handler_unregister(IP_EVENT, ESP_EVENT_ANY_ID, &_ip_event_cb) == ESP_OK) {
+        _ip_ev_instance = NULL;
+        log_v("Unregistered event handler");
+      } else {
+        log_e("Failed to unregister event handler");
+      }
+    }
+  }
+  if (_esp_netif != NULL) {
+    esp_netif_destroy(_esp_netif);
+    _esp_netif = NULL;
+  }
+  if (_interface_event_group != NULL) {
+    vEventGroupDelete(_interface_event_group);
+    _interface_event_group = NULL;
+    _initial_bits = 0;
+  }
+  for (int i = 0; i < ESP_NETIF_ID_MAX; ++i) {
+    if (_interfaces[i] != NULL && _interfaces[i] == this) {
+      _interfaces[i] = NULL;
+      break;
+    }
+  }
+}
+
+bool NetworkInterface::initNetif(Network_Interface_ID interface_id) {
+  if (_esp_netif == NULL || interface_id >= ESP_NETIF_ID_MAX) {
+    return false;
+  }
+  _interface_id = interface_id;
+  _got_ip_event_id = esp_netif_get_event_id(_esp_netif, ESP_NETIF_IP_EVENT_GOT_IP);
+  _lost_ip_event_id = esp_netif_get_event_id(_esp_netif, ESP_NETIF_IP_EVENT_LOST_IP);
+  _interfaces[_interface_id] = this;
+
+  if (_interface_event_group == NULL) {
+    _interface_event_group = xEventGroupCreate();
+    if (!_interface_event_group) {
+      log_e("Interface Event Group Create Failed!");
+      return false;
+    }
+    setStatusBits(_initial_bits);
+  }
+
+  if (_ip_ev_instance == NULL && esp_event_handler_instance_register(IP_EVENT, ESP_EVENT_ANY_ID, &_ip_event_cb, NULL, &_ip_ev_instance)) {
+    log_e("event_handler_instance_register for IP_EVENT Failed!");
+    return false;
+  }
+  return true;
+}
+
+bool NetworkInterface::started() const {
+  return (getStatusBits() & ESP_NETIF_STARTED_BIT) != 0;
+}
+
+bool NetworkInterface::connected() const {
+  return (getStatusBits() & ESP_NETIF_CONNECTED_BIT) != 0;
+}
+
+bool NetworkInterface::hasIP() const {
+  return (getStatusBits() & (ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_STATIC_IP_BIT)) != 0;
+}
+
+bool NetworkInterface::hasLinkLocalIPv6() const {
+  return (getStatusBits() & ESP_NETIF_HAS_LOCAL_IP6_BIT) != 0;
+}
+
+bool NetworkInterface::hasGlobalIPv6() const {
+  return (getStatusBits() & ESP_NETIF_HAS_GLOBAL_IP6_BIT) != 0;
+}
+
+bool NetworkInterface::enableIPv6(bool en) {
+#if CONFIG_LWIP_IPV6
+  if (en) {
+    setStatusBits(ESP_NETIF_WANT_IP6_BIT);
+    if (_esp_netif != NULL && connected()) {
+      // If we are already connected, try to enable IPv6 immediately
+      esp_err_t err = esp_netif_create_ip6_linklocal(_esp_netif);
+      if (err != ESP_OK) {
+        log_e("Failed to enable IPv6 Link Local on %s: [%d] %s", desc(), err, esp_err_to_name(err));
+      } else {
+        log_v("Enabled IPv6 Link Local on %s", desc());
+      }
+    }
+  } else {
+    clearStatusBits(ESP_NETIF_WANT_IP6_BIT);
+  }
+  return true;
+#else
+  return false;
+#endif
+}
+
+bool NetworkInterface::dnsIP(uint8_t dns_no, IPAddress ip) {
+  if (_esp_netif == NULL || dns_no > 2) {
+    return false;
+  }
+  esp_netif_flags_t flags = esp_netif_get_flags(_esp_netif);
+  if (flags & ESP_NETIF_DHCP_SERVER && dns_no > 0) {
+    log_e("Server interfaces can have only one DNS server.");
+    return false;
+  }
+  esp_netif_dns_info_t d;
+  // ToDo: can this work with IPv6 addresses?
+  d.ip.type = IPADDR_TYPE_V4;
+  if (static_cast<uint32_t>(ip) != 0) {
+    d.ip.u_addr.ip4.addr = static_cast<uint32_t>(ip);
+  } else {
+    d.ip.u_addr.ip4.addr = 0;
+  }
+  if (esp_netif_set_dns_info(_esp_netif, (esp_netif_dns_type_t)dns_no, &d) != ESP_OK) {
+    return false;
+  }
+  return true;
+}
+
+bool NetworkInterface::config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1, IPAddress dns2, IPAddress dns3) {
+  if (_esp_netif == NULL) {
+    return false;
+  }
+  esp_err_t err = ESP_OK;
+  esp_netif_ip_info_t info;
+  esp_netif_dns_info_t d1;
+  esp_netif_dns_info_t d2;
+  esp_netif_dns_info_t d3;
+  d1.ip.type = IPADDR_TYPE_V4;
+  d2.ip.type = IPADDR_TYPE_V4;
+  d3.ip.type = IPADDR_TYPE_V4;
+
+  if (static_cast<uint32_t>(local_ip) != 0) {
+    info.ip.addr = static_cast<uint32_t>(local_ip);
+    info.gw.addr = static_cast<uint32_t>(gateway);
+    info.netmask.addr = static_cast<uint32_t>(subnet);
+    d1.ip.u_addr.ip4.addr = static_cast<uint32_t>(dns1);
+    d2.ip.u_addr.ip4.addr = static_cast<uint32_t>(dns2);
+    d3.ip.u_addr.ip4.addr = static_cast<uint32_t>(dns3);
+  } else {
+    info.ip.addr = 0;
+    info.gw.addr = 0;
+    info.netmask.addr = 0;
+    d1.ip.u_addr.ip4.addr = 0;
+    d2.ip.u_addr.ip4.addr = 0;
+    d3.ip.u_addr.ip4.addr = 0;
+  }
+
+  esp_netif_flags_t flags = esp_netif_get_flags(_esp_netif);
+  if (flags & ESP_NETIF_DHCP_SERVER) {
+
+    // Set DNS Server
+    if (d2.ip.u_addr.ip4.addr != 0) {
+      err = esp_netif_set_dns_info(_esp_netif, ESP_NETIF_DNS_MAIN, &d2);
+      if (err) {
+        log_e("Netif Set DNS Info Failed! 0x%04x: %s", err, esp_err_to_name(err));
+        return false;
+      }
+    }
+
+    // Stop DHCPS
+    err = esp_netif_dhcps_stop(_esp_netif);
+    if (err && err != ESP_ERR_ESP_NETIF_DHCP_ALREADY_STOPPED) {
+      log_e("DHCPS Stop Failed! 0x%04x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+
+    // Set IPv4, Netmask, Gateway
+    err = esp_netif_set_ip_info(_esp_netif, &info);
+    if (err) {
+      log_e("Netif Set IP Failed! 0x%04x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+
+    dhcps_lease_t lease;
+    lease.enable = true;
+    uint8_t CIDR = calculateSubnetCIDR(subnet);
+    log_v(
+      "SoftAP: %s | Gateway: %s | DHCP Start: %s | Netmask: %s", local_ip.toString().c_str(), gateway.toString().c_str(), dns1.toString().c_str(),
+      subnet.toString().c_str()
+    );
+    // netmask must have room for at least 12 IP addresses (AP + GW + 10 DHCP Leasing addresses)
+    // netmask also must be limited to the last 8 bits of IPv4, otherwise this function won't work
+    // IDF NETIF checks netmask for the 3rd byte: https://github.com/espressif/esp-idf/blob/master/components/esp_netif/lwip/esp_netif_lwip.c#L1857-L1862
+    if (CIDR > 28 || CIDR < 24) {
+      log_e("Bad netmask. It must be from /24 to /28 (255.255.255. 0<->240)");
+      return false;  //  ESP_FAIL if initializing failed
+    }
+#define _byte_swap32(num) (((num >> 24) & 0xff) | ((num << 8) & 0xff0000) | ((num >> 8) & 0xff00) | ((num << 24) & 0xff000000))
+    // The code below is ready for any netmask, not limited to 255.255.255.0
+    uint32_t netmask = _byte_swap32(info.netmask.addr);
+    uint32_t ap_ipaddr = _byte_swap32(info.ip.addr);
+    uint32_t dhcp_ipaddr = _byte_swap32(static_cast<uint32_t>(dns1));
+    dhcp_ipaddr = dhcp_ipaddr == 0 ? ap_ipaddr + 1 : dhcp_ipaddr;
+    uint32_t leaseStartMax = ~netmask - 10;
+    // there will be 10 addresses for DHCP to lease
+    lease.start_ip.addr = dhcp_ipaddr;
+    lease.end_ip.addr = lease.start_ip.addr + 10;
+    // Check if local_ip is in the same subnet as the dhcp leasing range initial address
+    if ((ap_ipaddr & netmask) != (dhcp_ipaddr & netmask)) {
+      log_e(
+        "The AP IP address (%s) and the DHCP start address (%s) must be in the same subnet", local_ip.toString().c_str(),
+        IPAddress(_byte_swap32(dhcp_ipaddr)).toString().c_str()
+      );
+      return false;  //  ESP_FAIL if initializing failed
+    }
+    // prevents DHCP lease range to overflow subnet range
+    if ((dhcp_ipaddr & ~netmask) >= leaseStartMax) {
+      // make first DHCP lease addr stay in the beginning of the netmask range
+      lease.start_ip.addr = (dhcp_ipaddr & netmask) + 1;
+      lease.end_ip.addr = lease.start_ip.addr + 10;
+      log_w("DHCP Lease out of range - Changing DHCP leasing start to %s", IPAddress(_byte_swap32(lease.start_ip.addr)).toString().c_str());
+    }
+    // Check if local_ip is within DHCP range
+    if (ap_ipaddr >= lease.start_ip.addr && ap_ipaddr <= lease.end_ip.addr) {
+      log_e(
+        "The AP IP address (%s) can't be within the DHCP range (%s -- %s)", local_ip.toString().c_str(),
+        IPAddress(_byte_swap32(lease.start_ip.addr)).toString().c_str(), IPAddress(_byte_swap32(lease.end_ip.addr)).toString().c_str()
+      );
+      return false;  //  ESP_FAIL if initializing failed
+    }
+    // Check if gateway is within DHCP range
+    uint32_t gw_ipaddr = _byte_swap32(info.gw.addr);
+    bool gw_in_same_subnet = (gw_ipaddr & netmask) == (ap_ipaddr & netmask);
+    if (gw_in_same_subnet && gw_ipaddr >= lease.start_ip.addr && gw_ipaddr <= lease.end_ip.addr) {
+      log_e(
+        "The GatewayP address (%s) can't be within the DHCP range (%s -- %s)", gateway.toString().c_str(),
+        IPAddress(_byte_swap32(lease.start_ip.addr)).toString().c_str(), IPAddress(_byte_swap32(lease.end_ip.addr)).toString().c_str()
+      );
+      return false;  //  ESP_FAIL if initializing failed
+    }
+    // all done, just revert back byte order of DHCP lease range
+    lease.start_ip.addr = _byte_swap32(lease.start_ip.addr);
+    lease.end_ip.addr = _byte_swap32(lease.end_ip.addr);
+    log_v("DHCP Server Range: %s to %s", IPAddress(lease.start_ip.addr).toString().c_str(), IPAddress(lease.end_ip.addr).toString().c_str());
+    err = esp_netif_dhcps_option(_esp_netif, ESP_NETIF_OP_SET, ESP_NETIF_REQUESTED_IP_ADDRESS, (void *)&lease, sizeof(dhcps_lease_t));
+    if (err) {
+      log_e("DHCPS Set Lease Failed! 0x%04x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+
+    // Offer DNS to DHCP clients
+    if (d2.ip.u_addr.ip4.addr != 0) {
+      dhcps_offer_t dhcps_dns_value = OFFER_DNS;
+      err = esp_netif_dhcps_option(_esp_netif, ESP_NETIF_OP_SET, ESP_NETIF_DOMAIN_NAME_SERVER, &dhcps_dns_value, sizeof(dhcps_dns_value));
+      if (err) {
+        log_e("Netif Set DHCP Option Failed! 0x%04x: %s", err, esp_err_to_name(err));
+        return false;
+      }
+    }
+
+    // Start DHCPS
+    err = esp_netif_dhcps_start(_esp_netif);
+    if (err) {
+      log_e("DHCPS Start Failed! 0x%04x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+  } else {
+    // Stop DHCPC
+    err = esp_netif_dhcpc_stop(_esp_netif);
+    if (err != ESP_OK && err != ESP_ERR_ESP_NETIF_DHCP_ALREADY_STOPPED) {
+      log_e("DHCP could not be stopped! Error: 0x%04x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+
+    clearStatusBits(ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_STATIC_IP_BIT);
+
+    // Set IPv4, Netmask, Gateway
+    err = esp_netif_set_ip_info(_esp_netif, &info);
+    if (err != ERR_OK) {
+      log_e("ETH IP could not be configured! Error: 0x%04x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+
+    // Set DNS Servers
+    esp_netif_set_dns_info(_esp_netif, ESP_NETIF_DNS_MAIN, &d1);
+    esp_netif_set_dns_info(_esp_netif, ESP_NETIF_DNS_BACKUP, &d2);
+    esp_netif_set_dns_info(_esp_netif, ESP_NETIF_DNS_FALLBACK, &d3);
+
+    // Start DHCPC if static IP was set
+    if (info.ip.addr == 0) {
+      err = esp_netif_dhcpc_start(_esp_netif);
+      if (err != ESP_OK && err != ESP_ERR_ESP_NETIF_DHCP_ALREADY_STARTED) {
+        log_w("DHCP could not be started! Error: 0x%04x: %s", err, esp_err_to_name(err));
+        return false;
+      }
+    } else {
+      setStatusBits(ESP_NETIF_HAS_STATIC_IP_BIT);
+    }
+  }
+
+  return true;
+}
+
+const char *NetworkInterface::getHostname() const {
+  if (_esp_netif == NULL) {
+    return "";
+  }
+  const char *hostname;
+  if (esp_netif_get_hostname(_esp_netif, &hostname)) {
+    return NULL;
+  }
+  return hostname;
+}
+
+bool NetworkInterface::setHostname(const char *hostname) const {
+  if (_esp_netif == NULL) {
+    return false;
+  }
+  return esp_netif_set_hostname(_esp_netif, hostname) == 0;
+}
+
+bool NetworkInterface::linkUp() const {
+  if (_esp_netif == NULL) {
+    return false;
+  }
+  return esp_netif_is_netif_up(_esp_netif);
+}
+
+const char *NetworkInterface::ifkey(void) const {
+  if (_esp_netif == NULL) {
+    return "";
+  }
+  return esp_netif_get_ifkey(_esp_netif);
+}
+
+const char *NetworkInterface::desc(void) const {
+  if (_esp_netif == NULL) {
+    return "";
+  }
+  return esp_netif_get_desc(_esp_netif);
+}
+
+String NetworkInterface::impl_name(void) const {
+  if (_esp_netif == NULL) {
+    return String("");
+  }
+  char netif_name[8];
+  esp_err_t err = esp_netif_get_netif_impl_name(_esp_netif, netif_name);
+  if (err != ESP_OK) {
+    log_e("Failed to get netif impl_name: 0x%04x %s", err, esp_err_to_name(err));
+    return String("");
+  }
+  return String(netif_name);
+}
+
+int NetworkInterface::impl_index() const {
+  if (_esp_netif == NULL) {
+    return -1;
+  }
+  return esp_netif_get_netif_impl_index(_esp_netif);
+}
+
+int NetworkInterface::route_prio() const {
+  if (_esp_netif == NULL) {
+    return -1;
+  }
+  return esp_netif_get_route_prio(_esp_netif);
+}
+
+bool NetworkInterface::setDefault() {
+  if (_esp_netif == NULL) {
+    return false;
+  }
+  esp_err_t err = esp_netif_set_default_netif(_esp_netif);
+  if (err != ESP_OK) {
+    log_e("Failed to set default netif: 0x%04x %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return true;
+}
+
+bool NetworkInterface::isDefault() const {
+  if (_esp_netif == NULL) {
+    return false;
+  }
+  return esp_netif_get_default_netif() == _esp_netif;
+}
+
+uint8_t *NetworkInterface::macAddress(uint8_t *mac) const {
+  if (!mac || _esp_netif == NULL || _interface_id == ESP_NETIF_ID_PPP) {
+    return NULL;
+  }
+  esp_err_t err = esp_netif_get_mac(_esp_netif, mac);
+  if (err != ESP_OK) {
+    log_e("Failed to get netif mac: 0x%04x %s", err, esp_err_to_name(err));
+    return NULL;
+  }
+  return mac;
+}
+
+String NetworkInterface::macAddress(void) const {
+  uint8_t mac[6] = {0, 0, 0, 0, 0, 0};
+  char macStr[18] = {0};
+  macAddress(mac);
+  sprintf(macStr, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  return String(macStr);
+}
+
+IPAddress NetworkInterface::localIP() const {
+  if (_esp_netif == NULL) {
+    return IPAddress();
+  }
+  esp_netif_ip_info_t ip;
+  if (esp_netif_get_ip_info(_esp_netif, &ip)) {
+    return IPAddress();
+  }
+  return IPAddress(ip.ip.addr);
+}
+
+IPAddress NetworkInterface::subnetMask() const {
+  if (_esp_netif == NULL) {
+    return IPAddress();
+  }
+  esp_netif_ip_info_t ip;
+  if (esp_netif_get_ip_info(_esp_netif, &ip)) {
+    return IPAddress();
+  }
+  return IPAddress(ip.netmask.addr);
+}
+
+IPAddress NetworkInterface::gatewayIP() const {
+  if (_esp_netif == NULL) {
+    return IPAddress();
+  }
+  esp_netif_ip_info_t ip;
+  if (esp_netif_get_ip_info(_esp_netif, &ip)) {
+    return IPAddress();
+  }
+  return IPAddress(ip.gw.addr);
+}
+
+IPAddress NetworkInterface::dnsIP(uint8_t dns_no) const {
+  if (_esp_netif == NULL) {
+    return IPAddress();
+  }
+  esp_netif_dns_info_t d;
+  if (esp_netif_get_dns_info(_esp_netif, dns_no ? ESP_NETIF_DNS_BACKUP : ESP_NETIF_DNS_MAIN, &d) != ESP_OK) {
+    return IPAddress();
+  }
+  if (d.ip.type == ESP_IPADDR_TYPE_V6) {
+    // IPv6 from 4x uint32_t; byte order based on IPV62STR() in esp_netif_ip_addr.h
+    // log_v("DNS got IPv6: " IPV6STR, IPV62STR(d.ip.u_addr.ip6));
+    uint32_t addr0 esp_netif_htonl(d.ip.u_addr.ip6.addr[0]);
+    uint32_t addr1 esp_netif_htonl(d.ip.u_addr.ip6.addr[1]);
+    uint32_t addr2 esp_netif_htonl(d.ip.u_addr.ip6.addr[2]);
+    uint32_t addr3 esp_netif_htonl(d.ip.u_addr.ip6.addr[3]);
+    return IPAddress(
+      (uint8_t)(addr0 >> 24) & 0xFF, (uint8_t)(addr0 >> 16) & 0xFF, (uint8_t)(addr0 >> 8) & 0xFF, (uint8_t)addr0 & 0xFF, (uint8_t)(addr1 >> 24) & 0xFF,
+      (uint8_t)(addr1 >> 16) & 0xFF, (uint8_t)(addr1 >> 8) & 0xFF, (uint8_t)addr1 & 0xFF, (uint8_t)(addr2 >> 24) & 0xFF, (uint8_t)(addr2 >> 16) & 0xFF,
+      (uint8_t)(addr2 >> 8) & 0xFF, (uint8_t)addr2 & 0xFF, (uint8_t)(addr3 >> 24) & 0xFF, (uint8_t)(addr3 >> 16) & 0xFF, (uint8_t)(addr3 >> 8) & 0xFF,
+      (uint8_t)addr3 & 0xFF, d.ip.u_addr.ip6.zone
+    );
+  }
+  // IPv4 from single uint32_t
+  // log_v("DNS IPv4: " IPSTR, IP2STR(&d.ip.u_addr.ip4));
+  return IPAddress(d.ip.u_addr.ip4.addr);
+}
+
+IPAddress NetworkInterface::broadcastIP() const {
+  if (_esp_netif == NULL) {
+    return IPAddress();
+  }
+  esp_netif_ip_info_t ip;
+  if (esp_netif_get_ip_info(_esp_netif, &ip)) {
+    return IPAddress();
+  }
+  return calculateBroadcast(IPAddress(ip.gw.addr), IPAddress(ip.netmask.addr));
+}
+
+IPAddress NetworkInterface::networkID() const {
+  if (_esp_netif == NULL) {
+    return IPAddress();
+  }
+  esp_netif_ip_info_t ip;
+  if (esp_netif_get_ip_info(_esp_netif, &ip)) {
+    return IPAddress();
+  }
+  return calculateNetworkID(IPAddress(ip.gw.addr), IPAddress(ip.netmask.addr));
+}
+
+uint8_t NetworkInterface::subnetCIDR() const {
+  if (_esp_netif == NULL) {
+    return (uint8_t)0;
+  }
+  esp_netif_ip_info_t ip;
+  if (esp_netif_get_ip_info(_esp_netif, &ip)) {
+    return (uint8_t)0;
+  }
+  return calculateSubnetCIDR(IPAddress(ip.netmask.addr));
+}
+
+#if CONFIG_LWIP_IPV6
+IPAddress NetworkInterface::linkLocalIPv6() const {
+  if (_esp_netif == NULL) {
+    return IPAddress(IPv6);
+  }
+  static esp_ip6_addr_t addr;
+  if (esp_netif_get_ip6_linklocal(_esp_netif, &addr)) {
+    return IPAddress(IPv6);
+  }
+  return IPAddress(IPv6, (const uint8_t *)addr.addr, addr.zone);
+}
+
+IPAddress NetworkInterface::globalIPv6() const {
+  if (_esp_netif == NULL) {
+    return IPAddress(IPv6);
+  }
+  static esp_ip6_addr_t addr;
+  if (esp_netif_get_ip6_global(_esp_netif, &addr)) {
+    return IPAddress(IPv6);
+  }
+  return IPAddress(IPv6, (const uint8_t *)addr.addr, addr.zone);
+}
+#endif
+
+size_t NetworkInterface::printTo(Print &out) const {
+  size_t bytes = 0;
+  if (_esp_netif == NULL) {
+    return bytes;
+  }
+  if (isDefault()) {
+    bytes += out.print("*");
+  }
+  const char *dscr = esp_netif_get_desc(_esp_netif);
+  if (dscr != NULL) {
+    bytes += out.print(dscr);
+  }
+  bytes += out.print(":");
+  if (esp_netif_is_netif_up(_esp_netif)) {
+    bytes += out.print(" <UP");
+  } else {
+    bytes += out.print(" <DOWN");
+  }
+  bytes += printDriverInfo(out);
+  bytes += out.print(">");
+
+  bytes += out.print(" (");
+  esp_netif_flags_t flags = esp_netif_get_flags(_esp_netif);
+  if (flags & ESP_NETIF_DHCP_CLIENT) {
+    bytes += out.print("DHCPC");
+    if (getStatusBits() & ESP_NETIF_HAS_STATIC_IP_BIT) {
+      bytes += out.print("_OFF");
+    }
+  }
+  if (flags & ESP_NETIF_DHCP_SERVER) {
+    bytes += out.print("DHCPS");
+  }
+  if (flags & ESP_NETIF_FLAG_AUTOUP) {
+    bytes += out.print(",AUTOUP");
+  }
+  if (flags & ESP_NETIF_FLAG_GARP) {
+    bytes += out.print(",GARP");
+  }
+  if (flags & ESP_NETIF_FLAG_EVENT_IP_MODIFIED) {
+    bytes += out.print(",IP_MOD");
+  }
+  if (flags & ESP_NETIF_FLAG_IS_PPP) {
+    bytes += out.print(",PPP");
+  }
+  if (flags & ESP_NETIF_FLAG_IS_BRIDGE) {
+    bytes += out.print(",BRIDGE");
+  }
+  if (flags & ESP_NETIF_FLAG_MLDV6_REPORT) {
+    bytes += out.print(",V6_REP");
+  }
+  bytes += out.println(")");
+
+  bytes += out.print("      ");
+  bytes += out.print("ether ");
+  bytes += out.print(macAddress());
+  bytes += out.println();
+
+  bytes += out.print("      ");
+  bytes += out.print("inet ");
+  bytes += out.print(localIP());
+  bytes += out.print(" netmask ");
+  bytes += out.print(subnetMask());
+  bytes += out.print(" broadcast ");
+  bytes += out.print(broadcastIP());
+  bytes += out.println();
+
+  bytes += out.print("      ");
+  bytes += out.print("gateway ");
+  bytes += out.print(gatewayIP());
+  bytes += out.print(" dns ");
+  bytes += out.print(dnsIP());
+  bytes += out.println();
+
+#if CONFIG_LWIP_IPV6
+  static const char *types[] = {"UNKNOWN", "GLOBAL", "LINK_LOCAL", "SITE_LOCAL", "UNIQUE_LOCAL", "IPV4_MAPPED_IPV6"};
+  esp_ip6_addr_t if_ip6[CONFIG_LWIP_IPV6_NUM_ADDRESSES];
+  int v6addrs = esp_netif_get_all_ip6(_esp_netif, if_ip6);
+  for (int i = 0; i < v6addrs; ++i) {
+    bytes += out.print("      ");
+    bytes += out.print("inet6 ");
+    bytes += IPAddress(IPv6, (const uint8_t *)if_ip6[i].addr, if_ip6[i].zone).printTo(out, true);
+    bytes += out.print(" type ");
+    bytes += out.print(types[esp_netif_ip6_get_addr_type(&if_ip6[i])]);
+    bytes += out.println();
+  }
+#endif
+
+  return bytes;
+}
diff --git a/libraries/Network/src/NetworkInterface.h b/libraries/Network/src/NetworkInterface.h
new file mode 100644
index 00000000000..4f97181d4fd
--- /dev/null
+++ b/libraries/Network/src/NetworkInterface.h
@@ -0,0 +1,109 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "esp_netif_types.h"
+#include "esp_event.h"
+#include "Arduino.h"
+#include "Printable.h"
+
+typedef enum {
+  ESP_NETIF_ID_STA,
+  ESP_NETIF_ID_AP,
+  ESP_NETIF_ID_PPP,
+  ESP_NETIF_ID_ETH0,
+  ESP_NETIF_ID_ETH1,
+  ESP_NETIF_ID_ETH2,
+  ESP_NETIF_ID_MAX
+} Network_Interface_ID;
+
+static const int ESP_NETIF_STARTED_BIT = BIT0;
+static const int ESP_NETIF_CONNECTED_BIT = BIT1;
+static const int ESP_NETIF_HAS_IP_BIT = BIT2;
+static const int ESP_NETIF_HAS_LOCAL_IP6_BIT = BIT3;
+static const int ESP_NETIF_HAS_GLOBAL_IP6_BIT = BIT4;
+static const int ESP_NETIF_WANT_IP6_BIT = BIT5;
+static const int ESP_NETIF_HAS_STATIC_IP_BIT = BIT6;
+
+#define ESP_NETIF_ID_ETH ESP_NETIF_ID_ETH0
+
+class NetworkInterface : public Printable {
+public:
+  NetworkInterface();
+  virtual ~NetworkInterface();
+
+  // For server interfaces (WiFi AP), dns1 is the DHCP lease range start and dns2 is the DNS. dns3 is not used
+  bool config(
+    IPAddress local_ip = (uint32_t)0x00000000, IPAddress gateway = (uint32_t)0x00000000, IPAddress subnet = (uint32_t)0x00000000,
+    IPAddress dns1 = (uint32_t)0x00000000, IPAddress dns2 = (uint32_t)0x00000000, IPAddress dns3 = (uint32_t)0x00000000
+  );
+  bool dnsIP(uint8_t dns_no, IPAddress ip);
+
+  const char *getHostname() const;
+  bool setHostname(const char *hostname) const;
+
+  bool started() const;
+  bool connected() const;
+  bool hasIP() const;
+  bool hasLinkLocalIPv6() const;
+  bool hasGlobalIPv6() const;
+  bool enableIPv6(bool en = true);
+
+  bool linkUp() const;
+  const char *ifkey() const;
+  const char *desc() const;
+  String impl_name() const;
+  int impl_index() const;
+  int route_prio() const;
+  bool setDefault();
+  bool isDefault() const;
+
+  uint8_t *macAddress(uint8_t *mac) const;
+  String macAddress() const;
+  IPAddress localIP() const;
+  IPAddress subnetMask() const;
+  IPAddress gatewayIP() const;
+  IPAddress dnsIP(uint8_t dns_no = 0) const;
+  IPAddress broadcastIP() const;
+  IPAddress networkID() const;
+  uint8_t subnetCIDR() const;
+#if CONFIG_LWIP_IPV6
+  IPAddress linkLocalIPv6() const;
+  IPAddress globalIPv6() const;
+#endif
+
+  size_t printTo(Print &out) const;
+
+  esp_netif_t *netif() {
+    return _esp_netif;
+  }
+  int getStatusBits() const;
+  int waitStatusBits(int bits, uint32_t timeout_ms) const;
+
+protected:
+  esp_netif_t *_esp_netif;
+  EventGroupHandle_t _interface_event_group;
+  int _initial_bits;
+  int32_t _got_ip_event_id;
+  int32_t _lost_ip_event_id;
+  Network_Interface_ID _interface_id;
+
+  bool initNetif(Network_Interface_ID interface_id);
+  void destroyNetif();
+  int setStatusBits(int bits);
+  int clearStatusBits(int bits);
+
+  // virtual void getMac(uint8_t* mac) = 0;
+  virtual size_t printDriverInfo(Print &out) const = 0;
+
+public:
+  void _onIpEvent(int32_t event_id, void *event_data);
+
+private:
+  IPAddress calculateNetworkID(IPAddress ip, IPAddress subnet) const;
+  IPAddress calculateBroadcast(IPAddress ip, IPAddress subnet) const;
+  uint8_t calculateSubnetCIDR(IPAddress subnetMask) const;
+};
diff --git a/libraries/Network/src/NetworkManager.cpp b/libraries/Network/src/NetworkManager.cpp
new file mode 100644
index 00000000000..12276b2e242
--- /dev/null
+++ b/libraries/Network/src/NetworkManager.cpp
@@ -0,0 +1,200 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "NetworkManager.h"
+#include "IPAddress.h"
+#include "esp_netif.h"
+#include "lwip/dns.h"
+#include "esp_mac.h"
+#include "netdb.h"
+
+NetworkManager::NetworkManager() {}
+
+NetworkInterface *getNetifByID(Network_Interface_ID id);
+
+bool NetworkManager::begin() {
+  static bool initialized = false;
+  if (!initialized) {
+    initialized = true;
+#if CONFIG_IDF_TARGET_ESP32
+    uint8_t mac[8];
+    if (esp_efuse_mac_get_default(mac) == ESP_OK) {
+      esp_base_mac_addr_set(mac);
+    }
+#endif
+    initialized = esp_netif_init() == ESP_OK;
+    if (!initialized) {
+      log_e("esp_netif_init failed!");
+    }
+  }
+  if (initialized) {
+    initNetworkEvents();
+  }
+  return initialized;
+}
+
+/**
+ * Resolve the given hostname to an IP address.
+ * @param aHostname     Name to be resolved
+ * @param aResult       IPAddress structure to store the returned IP address
+ * @return 1 if aIPAddrString was successfully converted to an IP address,
+ *          else error code
+ */
+int NetworkManager::hostByName(const char *aHostname, IPAddress &aResult) {
+  static bool hasGlobalV6 = false;
+  static bool hasGlobalV4 = false;
+  err_t err = ERR_OK;
+  const char *servname = "0";
+  struct addrinfo *res;
+
+  aResult = static_cast<uint32_t>(0);
+
+  // First check if the host parses as a literal address
+  if (aResult.fromString(aHostname)) {
+    return 1;
+  }
+
+  // This should generally check if we have a global address assigned to one of the interfaces.
+  // If such address is not assigned, there is no point in trying to get V6 from DNS as we will not be able to reach it.
+  bool hasGlobalV6Now = false;
+  bool hasGlobalV4Now = false;
+  for (int i = 0; i < ESP_NETIF_ID_MAX; ++i) {
+    NetworkInterface *iface = getNetifByID((Network_Interface_ID)i);
+    if (iface != NULL) {
+      if (iface->hasGlobalIPv6()) {
+        hasGlobalV6Now = true;
+      }
+      if (iface->hasIP()) {
+        hasGlobalV4Now = true;
+      }
+    }
+    if (hasGlobalV6Now && hasGlobalV4Now) {
+      break;
+    }
+  }
+
+  // If the state of IP addresses has changed, clear the DNS cache
+  if (hasGlobalV6 != hasGlobalV6Now || hasGlobalV4 != hasGlobalV4Now) {
+    hasGlobalV6 = hasGlobalV6Now;
+    hasGlobalV4 = hasGlobalV4Now;
+    dns_clear_cache();
+    log_d("Clearing DNS cache");
+  }
+
+  struct addrinfo hints;
+  memset(&hints, 0, sizeof(hints));
+  hints.ai_socktype = SOCK_STREAM;
+
+#if CONFIG_LWIP_IPV6
+  // **Workaround**
+  // LWIP AF_UNSPEC always prefers IPv4 and doesn't check what network is
+  // available. See https://github.com/espressif/esp-idf/issues/13255
+  // Until that is fixed, as a work around if we have a global scope IPv6,
+  // then we check IPv6 only first.
+  if (hasGlobalV6) {
+    hints.ai_family = AF_INET6;
+    err = lwip_getaddrinfo(aHostname, servname, &hints, &res);
+
+    if (err == ERR_OK) {
+      struct sockaddr_in6 *ipv6 = (struct sockaddr_in6 *)res->ai_addr;
+      // As an array of u8_t
+      aResult = IPAddress(IPv6, ipv6->sin6_addr.s6_addr);
+      log_d("DNS found IPv6 first %s", aResult.toString().c_str());
+      lwip_freeaddrinfo(res);
+      return 1;
+    }
+  }
+  // **End Workaround**
+#endif
+
+  hints.ai_family = AF_UNSPEC;
+  err = lwip_getaddrinfo(aHostname, servname, &hints, &res);
+
+  if (err == ERR_OK) {
+#if CONFIG_LWIP_IPV6
+    if (res->ai_family == AF_INET6) {
+      struct sockaddr_in6 *ipv6 = (struct sockaddr_in6 *)res->ai_addr;
+      // As an array of u8_t
+      aResult = IPAddress(IPv6, ipv6->sin6_addr.s6_addr);
+      log_d("DNS found IPv6 %s", aResult.toString().c_str());
+    } else {
+#endif
+      struct sockaddr_in *ipv4 = (struct sockaddr_in *)res->ai_addr;
+      // As a single u32_t
+      aResult = IPAddress(ipv4->sin_addr.s_addr);
+      log_d("DNS found IPv4 %s", aResult.toString().c_str());
+#if CONFIG_LWIP_IPV6
+    }
+#endif
+
+    lwip_freeaddrinfo(res);
+    return 1;
+  }
+
+  log_e("DNS Failed for '%s' with error '%d'", aHostname, err);
+  return err;
+}
+
+uint8_t *NetworkManager::macAddress(uint8_t *mac) {
+  esp_base_mac_addr_get(mac);
+  return mac;
+}
+
+String NetworkManager::macAddress(void) {
+  uint8_t mac[6];
+  char macStr[18] = {0};
+  macAddress(mac);
+  sprintf(macStr, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+  return String(macStr);
+}
+
+static char default_hostname[32] = {
+  0,
+};
+
+const char *NetworkManager::getHostname() {
+  if (default_hostname[0] == 0) {
+    uint8_t eth_mac[6];
+    esp_base_mac_addr_get(eth_mac);
+    snprintf(default_hostname, 32, "%s%02X%02X%02X", CONFIG_IDF_TARGET "-", eth_mac[3], eth_mac[4], eth_mac[5]);
+  }
+  return (const char *)default_hostname;
+}
+
+bool NetworkManager::setHostname(const char *name) {
+  if (name) {
+    snprintf(default_hostname, 32, "%s", name);
+  }
+  return true;
+}
+
+bool NetworkManager::setDefaultInterface(NetworkInterface &ifc) {
+  return ifc.setDefault();
+}
+
+NetworkInterface *NetworkManager::getDefaultInterface() {
+  esp_netif_t *netif = esp_netif_get_default_netif();
+  for (int i = 0; i < ESP_NETIF_ID_MAX; ++i) {
+    NetworkInterface *iface = getNetifByID((Network_Interface_ID)i);
+    if (iface != NULL && iface->netif() == netif) {
+      return iface;
+    }
+  }
+  return NULL;
+}
+
+size_t NetworkManager::printTo(Print &out) const {
+  size_t bytes = 0;
+
+  for (int i = 0; i < ESP_NETIF_ID_MAX; ++i) {
+    NetworkInterface *iface = getNetifByID((Network_Interface_ID)i);
+    if (iface != NULL && iface->netif() != NULL) {
+      bytes += out.println(*iface);
+    }
+  }
+  return bytes;
+}
+
+NetworkManager Network;
diff --git a/libraries/Network/src/NetworkManager.h b/libraries/Network/src/NetworkManager.h
new file mode 100644
index 00000000000..6b9d5e16cfc
--- /dev/null
+++ b/libraries/Network/src/NetworkManager.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "NetworkEvents.h"
+#include "NetworkInterface.h"
+#include "IPAddress.h"
+#include "WString.h"
+
+class NetworkManager : public NetworkEvents, public Printable {
+public:
+  NetworkManager();
+
+  bool begin();
+  int hostByName(const char *aHostname, IPAddress &aResult);
+  uint8_t *macAddress(uint8_t *mac);
+  String macAddress();
+
+  bool setDefaultInterface(NetworkInterface &ifc);
+  NetworkInterface *getDefaultInterface();
+
+  size_t printTo(Print &out) const;
+
+  static const char *getHostname();
+  static bool setHostname(const char *hostname);
+  static bool hostname(const String &aHostname) {
+    return setHostname(aHostname.c_str());
+  }
+};
+
+extern NetworkManager Network;
diff --git a/libraries/Network/src/NetworkServer.cpp b/libraries/Network/src/NetworkServer.cpp
new file mode 100644
index 00000000000..ce8ef952ea7
--- /dev/null
+++ b/libraries/Network/src/NetworkServer.cpp
@@ -0,0 +1,172 @@
+/*
+  Server.cpp - Server class for Raspberry Pi
+  Copyright (c) 2016 Hristo Gochkov  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+#include "NetworkServer.h"
+#include <lwip/sockets.h>
+#include <lwip/netdb.h>
+
+#undef write
+#undef close
+
+int NetworkServer::setTimeout(uint32_t seconds) {
+  struct timeval tv;
+  tv.tv_sec = seconds;
+  tv.tv_usec = 0;
+  if (setsockopt(sockfd, SOL_SOCKET, SO_RCVTIMEO, (char *)&tv, sizeof(struct timeval)) < 0) {
+    return -1;
+  }
+  return setsockopt(sockfd, SOL_SOCKET, SO_SNDTIMEO, (char *)&tv, sizeof(struct timeval));
+}
+
+NetworkClient NetworkServer::available() {
+  return accept();
+}
+
+NetworkClient NetworkServer::accept() {
+  if (!_listening) {
+    return NetworkClient();
+  }
+  int client_sock;
+  if (_accepted_sockfd >= 0) {
+    client_sock = _accepted_sockfd;
+    _accepted_sockfd = -1;
+  } else {
+#if CONFIG_LWIP_IPV6
+    struct sockaddr_in6 _client;
+    int cs = sizeof(struct sockaddr_in6);
+#else
+    struct sockaddr_in _client;
+    int cs = sizeof(struct sockaddr_in);
+#endif
+#ifdef ESP_IDF_VERSION_MAJOR
+    client_sock = lwip_accept(sockfd, (struct sockaddr *)&_client, (socklen_t *)&cs);
+#else
+    client_sock = lwip_accept_r(sockfd, (struct sockaddr *)&_client, (socklen_t *)&cs);
+#endif
+  }
+  if (client_sock >= 0) {
+    int val = 1;
+    if (setsockopt(client_sock, SOL_SOCKET, SO_KEEPALIVE, (char *)&val, sizeof(int)) == ESP_OK) {
+      val = _noDelay;
+      if (setsockopt(client_sock, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(int)) == ESP_OK) {
+        return NetworkClient(client_sock);
+      }
+    }
+  }
+  return NetworkClient();
+}
+
+void NetworkServer::begin(uint16_t port) {
+  begin(port, 1);
+}
+
+void NetworkServer::begin(uint16_t port, int enable) {
+  if (_listening) {
+    return;
+  }
+  if (port) {
+    _port = port;
+  }
+#if CONFIG_LWIP_IPV6
+  struct sockaddr_in6 server;
+  sockfd = socket(AF_INET6, SOCK_STREAM, 0);
+  if (sockfd < 0) {
+    return;
+  }
+  setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &enable, sizeof(int));
+  server.sin6_family = AF_INET6;
+  if (_addr.type() == IPv4) {
+    memcpy(server.sin6_addr.s6_addr + 11, (uint8_t *)&_addr[0], 4);
+    server.sin6_addr.s6_addr[10] = 0xFF;
+    server.sin6_addr.s6_addr[11] = 0xFF;
+  } else {
+    memcpy(server.sin6_addr.s6_addr, (uint8_t *)&_addr[0], 16);
+  }
+  memset(server.sin6_addr.s6_addr, 0x0, 16);
+  server.sin6_port = htons(_port);
+#else
+  struct sockaddr_in server;
+  memset(&server, 0x0, sizeof(sockaddr_in));
+  server.sin_family = AF_INET;
+  sockfd = socket(AF_INET, SOCK_STREAM, 0);
+  if (sockfd < 0) {
+    return;
+  }
+  setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &enable, sizeof(int));
+  memcpy((uint8_t *)&(server.sin_addr.s_addr), (uint8_t *)&_addr[0], 4);
+  server.sin_port = htons(_port);
+#endif
+  if (bind(sockfd, (struct sockaddr *)&server, sizeof(server)) < 0) {
+    return;
+  }
+  if (listen(sockfd, _max_clients) < 0) {
+    return;
+  }
+  fcntl(sockfd, F_SETFL, O_NONBLOCK);
+  _listening = true;
+  _noDelay = false;
+  _accepted_sockfd = -1;
+}
+
+void NetworkServer::setNoDelay(bool nodelay) {
+  _noDelay = nodelay;
+}
+
+bool NetworkServer::getNoDelay() {
+  return _noDelay;
+}
+
+bool NetworkServer::hasClient() {
+  if (_accepted_sockfd >= 0) {
+    return true;
+  }
+#if CONFIG_LWIP_IPV6
+  struct sockaddr_in6 _client;
+  int cs = sizeof(struct sockaddr_in6);
+#else
+  struct sockaddr _client;
+  int cs = sizeof(struct sockaddr);
+#endif
+#ifdef ESP_IDF_VERSION_MAJOR
+  _accepted_sockfd = lwip_accept(sockfd, (struct sockaddr *)&_client, (socklen_t *)&cs);
+#else
+  _accepted_sockfd = lwip_accept_r(sockfd, (struct sockaddr *)&_client, (socklen_t *)&cs);
+#endif
+  if (_accepted_sockfd >= 0) {
+    return true;
+  }
+  return false;
+}
+
+void NetworkServer::end() {
+#ifdef ESP_IDF_VERSION_MAJOR
+  lwip_close(sockfd);
+#else
+  lwip_close_r(sockfd);
+#endif
+  sockfd = -1;
+  _listening = false;
+}
+
+void NetworkServer::close() {
+  end();
+}
+
+void NetworkServer::stop() {
+  end();
+}
diff --git a/libraries/Network/src/NetworkServer.h b/libraries/Network/src/NetworkServer.h
new file mode 100644
index 00000000000..18a74df58a3
--- /dev/null
+++ b/libraries/Network/src/NetworkServer.h
@@ -0,0 +1,65 @@
+/*
+  Server.h - Server class for Raspberry Pi
+  Copyright (c) 2016 Hristo Gochkov  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+#pragma once
+
+#include "Arduino.h"
+#include "Server.h"
+#include "NetworkClient.h"
+#include "IPAddress.h"
+
+class NetworkServer {
+private:
+  int sockfd;
+  int _accepted_sockfd = -1;
+  IPAddress _addr;
+  uint16_t _port;
+  uint8_t _max_clients;
+  bool _listening;
+  bool _noDelay = false;
+
+public:
+  void listenOnLocalhost() {}
+
+  NetworkServer(uint16_t port = 80, uint8_t max_clients = 4)
+    : sockfd(-1), _accepted_sockfd(-1), _addr(), _port(port), _max_clients(max_clients), _listening(false), _noDelay(false) {
+    log_v("NetworkServer::NetworkServer(port=%d, ...)", port);
+  }
+  NetworkServer(const IPAddress &addr, uint16_t port = 80, uint8_t max_clients = 4)
+    : sockfd(-1), _accepted_sockfd(-1), _addr(addr), _port(port), _max_clients(max_clients), _listening(false), _noDelay(false) {
+    log_v("NetworkServer::NetworkServer(addr=%s, port=%d, ...)", addr.toString().c_str(), port);
+  }
+  ~NetworkServer() {
+    end();
+  }
+  NetworkClient available() __attribute__((deprecated("Renamed to accept().")));
+  NetworkClient accept();
+  void begin(uint16_t port = 0);
+  void begin(uint16_t port, int reuse_enable);
+  void setNoDelay(bool nodelay);
+  bool getNoDelay();
+  bool hasClient();
+
+  void end();
+  void close();
+  void stop();
+  operator bool() {
+    return _listening;
+  }
+  int setTimeout(uint32_t seconds);
+};
diff --git a/libraries/Network/src/NetworkUdp.cpp b/libraries/Network/src/NetworkUdp.cpp
new file mode 100644
index 00000000000..51579910ded
--- /dev/null
+++ b/libraries/Network/src/NetworkUdp.cpp
@@ -0,0 +1,418 @@
+/*
+  Udp.cpp - UDP class for Raspberry Pi
+  Copyright (c) 2016 Hristo Gochkov  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "NetworkUdp.h"
+#include <new>  //std::nothrow
+#include <lwip/sockets.h>
+#include <lwip/netdb.h>
+#include <errno.h>
+
+#undef write
+#undef read
+
+NetworkUDP::NetworkUDP() : udp_server(-1), server_port(0), remote_port(0), tx_buffer(0), tx_buffer_len(0), rx_buffer(0) {}
+
+NetworkUDP::~NetworkUDP() {
+  stop();
+}
+
+uint8_t NetworkUDP::begin(IPAddress address, uint16_t port) {
+  stop();
+
+  server_port = port;
+
+  tx_buffer = (char *)malloc(1460);
+  if (!tx_buffer) {
+    log_e("could not create tx buffer: %d", errno);
+    return 0;
+  }
+  tx_buffer_len = 0;
+
+#if LWIP_IPV6
+  if ((udp_server = socket((address.type() == IPv6) ? AF_INET6 : AF_INET, SOCK_DGRAM, 0)) == -1) {
+#else
+  if ((udp_server = socket(AF_INET, SOCK_DGRAM, 0)) == -1) {
+#endif
+    log_e("could not create socket: %d", errno);
+    return 0;
+  }
+
+  int yes = 1;
+  if (setsockopt(udp_server, SOL_SOCKET, SO_REUSEADDR, &yes, sizeof(yes)) < 0) {
+    log_e("could not set socket option: %d", errno);
+    stop();
+    return 0;
+  }
+
+  struct sockaddr_storage serveraddr = {};
+  size_t sock_size = 0;
+#if LWIP_IPV6
+  if (address.type() == IPv6) {
+    struct sockaddr_in6 *tmpaddr = (struct sockaddr_in6 *)&serveraddr;
+    ip_addr_t addr;
+    address.to_ip_addr_t(&addr);
+    memset((char *)tmpaddr, 0, sizeof(struct sockaddr_in));
+    tmpaddr->sin6_family = AF_INET6;
+    tmpaddr->sin6_port = htons(server_port);
+    tmpaddr->sin6_scope_id = addr.u_addr.ip6.zone;
+    inet6_addr_from_ip6addr(&tmpaddr->sin6_addr, ip_2_ip6(&addr));
+    tmpaddr->sin6_flowinfo = 0;
+    sock_size = sizeof(sockaddr_in6);
+  } else
+#endif
+  {
+    struct sockaddr_in *tmpaddr = (struct sockaddr_in *)&serveraddr;
+    memset((char *)tmpaddr, 0, sizeof(struct sockaddr_in));
+    tmpaddr->sin_family = AF_INET;
+    tmpaddr->sin_port = htons(server_port);
+    tmpaddr->sin_addr.s_addr = (in_addr_t)address;
+    sock_size = sizeof(sockaddr_in);
+  }
+  if (bind(udp_server, (sockaddr *)&serveraddr, sock_size) == -1) {
+    log_e("could not bind socket: %d", errno);
+    stop();
+    return 0;
+  }
+  fcntl(udp_server, F_SETFL, O_NONBLOCK);
+  return 1;
+}
+
+uint8_t NetworkUDP::begin(uint16_t p) {
+  return begin(IPAddress(), p);
+}
+
+uint8_t NetworkUDP::beginMulticast(IPAddress address, uint16_t p) {
+  if (begin(IPAddress(), p)) {
+    ip_addr_t addr;
+    address.to_ip_addr_t(&addr);
+    if (ip_addr_ismulticast(&addr)) {
+#if LWIP_IPV6
+      if (address.type() == IPv6) {
+        struct ipv6_mreq mreq;
+        bool joined = false;
+        inet6_addr_from_ip6addr(&mreq.ipv6mr_multiaddr, ip_2_ip6(&addr));
+
+        // iterate on each interface
+        for (netif *intf = netif_list; intf != nullptr; intf = intf->next) {
+          mreq.ipv6mr_interface = intf->num + 1;
+          if (intf->name[0] != 'l' || intf->name[1] != 'o') {  // skip 'lo' local interface
+            int ret = setsockopt(udp_server, IPPROTO_IPV6, IPV6_JOIN_GROUP, &mreq, sizeof(mreq));
+            if (ret >= 0) {
+              joined = true;
+            }
+          }
+        }
+        if (!joined) {
+          log_e("could not join igmp: %d", errno);
+          stop();
+          return 0;
+        }
+      } else
+#endif
+      {
+        struct ip_mreq mreq;
+        mreq.imr_multiaddr.s_addr = (in_addr_t)address;
+        mreq.imr_interface.s_addr = INADDR_ANY;
+        if (setsockopt(udp_server, IPPROTO_IP, IP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)) < 0) {
+          log_e("could not join igmp: %d", errno);
+          stop();
+          return 0;
+        }
+      }
+      multicast_ip = address;
+      return 1;
+    }
+  }
+  return 0;
+}
+
+void NetworkUDP::stop() {
+  if (tx_buffer) {
+    free(tx_buffer);
+    tx_buffer = NULL;
+  }
+  tx_buffer_len = 0;
+  if (rx_buffer) {
+    cbuf *b = rx_buffer;
+    rx_buffer = NULL;
+    delete b;
+  }
+  if (udp_server == -1) {
+    return;
+  }
+  ip_addr_t addr;
+  multicast_ip.to_ip_addr_t(&addr);
+  if (!ip_addr_isany(&addr)) {
+#if LWIP_IPV6
+    if (multicast_ip.type() == IPv6) {
+      struct ipv6_mreq mreq;
+      inet6_addr_from_ip6addr(&mreq.ipv6mr_multiaddr, ip_2_ip6(&addr));
+
+      // iterate on each interface
+      for (netif *intf = netif_list; intf != nullptr; intf = intf->next) {
+        mreq.ipv6mr_interface = intf->num + 1;
+        if (intf->name[0] != 'l' || intf->name[1] != 'o') {  // skip 'lo' local interface
+          setsockopt(udp_server, IPPROTO_IPV6, IPV6_LEAVE_GROUP, &mreq, sizeof(mreq));
+        }
+      }
+    } else
+#endif
+    {
+      struct ip_mreq mreq;
+      mreq.imr_multiaddr.s_addr = (in_addr_t)multicast_ip;
+      mreq.imr_interface.s_addr = (in_addr_t)0;
+      setsockopt(udp_server, IPPROTO_IP, IP_DROP_MEMBERSHIP, &mreq, sizeof(mreq));
+    }
+    // now common code for v4/v6
+    multicast_ip = IPAddress();
+  }
+  close(udp_server);
+  udp_server = -1;
+}
+
+int NetworkUDP::beginMulticastPacket() {
+  if (!server_port || multicast_ip == IPAddress()) {
+    return 0;
+  }
+  remote_ip = multicast_ip;
+  remote_port = server_port;
+  return beginPacket();
+}
+
+int NetworkUDP::beginPacket() {
+  if (!remote_port) {
+    return 0;
+  }
+
+  // allocate tx_buffer if is necessary
+  if (!tx_buffer) {
+    tx_buffer = (char *)malloc(1460);
+    if (!tx_buffer) {
+      log_e("could not create tx buffer: %d", errno);
+      return 0;
+    }
+  }
+  tx_buffer_len = 0;
+
+  // check whereas socket is already open
+  if (udp_server != -1) {
+    return 1;
+  }
+
+  if ((udp_server = socket(AF_INET, SOCK_DGRAM, 0)) == -1) {
+    log_e("could not create socket: %d", errno);
+    return 0;
+  }
+
+  fcntl(udp_server, F_SETFL, O_NONBLOCK);
+
+  return 1;
+}
+
+int NetworkUDP::beginPacket(IPAddress ip, uint16_t port) {
+  remote_ip = ip;
+  remote_port = port;
+  return beginPacket();
+}
+
+int NetworkUDP::beginPacket(const char *host, uint16_t port) {
+  struct hostent *server;
+  server = gethostbyname(host);
+  if (server == NULL) {
+    log_e("could not get host from dns: %d", errno);
+    return 0;
+  }
+  return beginPacket(IPAddress((const uint8_t *)(server->h_addr_list[0])), port);
+}
+
+int NetworkUDP::endPacket() {
+  ip_addr_t addr;
+  remote_ip.to_ip_addr_t(&addr);
+
+  if (remote_ip.type() == IPv4) {
+    struct sockaddr_in recipient;
+    recipient.sin_addr.s_addr = (uint32_t)remote_ip;
+    recipient.sin_family = AF_INET;
+    recipient.sin_port = htons(remote_port);
+    int sent = sendto(udp_server, tx_buffer, tx_buffer_len, 0, (struct sockaddr *)&recipient, sizeof(recipient));
+    if (sent < 0) {
+      log_e("could not send data: %d", errno);
+      return 0;
+    }
+#if LWIP_IPV6
+  } else {
+    struct sockaddr_in6 recipient;
+    recipient.sin6_flowinfo = 0;
+    recipient.sin6_addr = *(in6_addr *)(ip_addr_t *)(&addr);
+    recipient.sin6_family = AF_INET6;
+    recipient.sin6_port = htons(remote_port);
+    recipient.sin6_scope_id = remote_ip.zone();
+    int sent = sendto(udp_server, tx_buffer, tx_buffer_len, 0, (struct sockaddr *)&recipient, sizeof(recipient));
+    if (sent < 0) {
+      log_e("could not send data: %d", errno);
+      return 0;
+    }
+#endif
+  }
+  return 1;
+}
+
+size_t NetworkUDP::write(uint8_t data) {
+  if (tx_buffer_len == 1460) {
+    endPacket();
+    tx_buffer_len = 0;
+  }
+  tx_buffer[tx_buffer_len++] = data;
+  return 1;
+}
+
+size_t NetworkUDP::write(const uint8_t *buffer, size_t size) {
+  size_t i;
+  for (i = 0; i < size; i++) {
+    write(buffer[i]);
+  }
+  return i;
+}
+
+void NetworkUDP::flush() {
+  clear();
+}
+
+int NetworkUDP::parsePacket() {
+  if (rx_buffer) {
+    return 0;
+  }
+  struct sockaddr_storage si_other_storage;  // enough storage for v4 and v6
+  socklen_t slen = sizeof(sockaddr_storage);
+  int len = 0;
+  if (ioctl(udp_server, FIONREAD, &len) == -1) {
+    log_e("could not check for data in buffer length: %d", errno);
+    return 0;
+  }
+  if (!len) {
+    return 0;
+  }
+  char *buf = (char *)malloc(1460);
+  if (!buf) {
+    return 0;
+  }
+  if ((len = recvfrom(udp_server, buf, 1460, MSG_DONTWAIT, (struct sockaddr *)&si_other_storage, (socklen_t *)&slen)) == -1) {
+    free(buf);
+    if (errno == EWOULDBLOCK) {
+      return 0;
+    }
+    log_e("could not receive data: %d", errno);
+    return 0;
+  }
+  if (si_other_storage.ss_family == AF_INET) {
+    struct sockaddr_in &si_other = (sockaddr_in &)si_other_storage;
+    remote_ip = IPAddress(si_other.sin_addr.s_addr);
+    remote_port = ntohs(si_other.sin_port);
+  }
+#if LWIP_IPV6
+  else if (si_other_storage.ss_family == AF_INET6) {
+    struct sockaddr_in6 &si_other = (sockaddr_in6 &)si_other_storage;
+    remote_ip = IPAddress(IPv6, (uint8_t *)&si_other.sin6_addr, si_other.sin6_scope_id);  // force IPv6
+    ip_addr_t addr;
+    remote_ip.to_ip_addr_t(&addr);
+    /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */
+    if (remote_ip.type() == IPv6 && ip6_addr_isipv4mappedipv6(ip_2_ip6(&addr))) {
+      unmap_ipv4_mapped_ipv6(ip_2_ip4(&addr), ip_2_ip6(&addr));
+      IP_SET_TYPE_VAL(addr, IPADDR_TYPE_V4);
+      remote_ip.from_ip_addr_t(&addr);
+    }
+    remote_port = ntohs(si_other.sin6_port);
+  } else {
+    remote_ip = ip_addr_any.u_addr.ip4.addr;
+    remote_port = 0;
+  }
+#else
+  else {
+    remote_ip = ip_addr_any.addr;
+    remote_port = 0;
+  }
+#endif  // LWIP_IPV6=1
+  if (len > 0) {
+    rx_buffer = new (std::nothrow) cbuf(len);
+    rx_buffer->write(buf, len);
+  }
+  free(buf);
+  return len;
+}
+
+int NetworkUDP::available() {
+  if (!rx_buffer) {
+    return 0;
+  }
+  return rx_buffer->available();
+}
+
+int NetworkUDP::read() {
+  if (!rx_buffer) {
+    return -1;
+  }
+  int out = rx_buffer->read();
+  if (!rx_buffer->available()) {
+    cbuf *b = rx_buffer;
+    rx_buffer = 0;
+    delete b;
+  }
+  return out;
+}
+
+int NetworkUDP::read(unsigned char *buffer, size_t len) {
+  return read((char *)buffer, len);
+}
+
+int NetworkUDP::read(char *buffer, size_t len) {
+  if (!rx_buffer) {
+    return 0;
+  }
+  int out = rx_buffer->read(buffer, len);
+  if (!rx_buffer->available()) {
+    cbuf *b = rx_buffer;
+    rx_buffer = 0;
+    delete b;
+  }
+  return out;
+}
+
+int NetworkUDP::peek() {
+  if (!rx_buffer) {
+    return -1;
+  }
+  return rx_buffer->peek();
+}
+
+void NetworkUDP::clear() {
+  if (!rx_buffer) {
+    return;
+  }
+  cbuf *b = rx_buffer;
+  rx_buffer = 0;
+  delete b;
+}
+
+IPAddress NetworkUDP::remoteIP() {
+  return remote_ip;
+}
+
+uint16_t NetworkUDP::remotePort() {
+  return remote_port;
+}
diff --git a/libraries/Network/src/NetworkUdp.h b/libraries/Network/src/NetworkUdp.h
new file mode 100644
index 00000000000..e70ec9b2127
--- /dev/null
+++ b/libraries/Network/src/NetworkUdp.h
@@ -0,0 +1,80 @@
+/*
+ *  Udp.cpp: Library to send/receive UDP packets.
+ *
+ * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray for mentioning these)
+ * 1) UDP does not guarantee the order in which assembled UDP packets are received. This
+ * might not happen often in practice, but in larger network topologies, a UDP
+ * packet can be received out of sequence.
+ * 2) UDP does not guard against lost packets - so packets *can* disappear without the sender being
+ * aware of it. Again, this may not be a concern in practice on small local networks.
+ * For more information, see http://www.cafeaulait.org/course/week12/35.html
+ *
+ * MIT License:
+ * Copyright (c) 2008 Bjoern Hartmann
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * bjoern@cs.stanford.edu 12/30/2008
+ */
+
+#ifndef _NETWORKUDP_H_
+#define _NETWORKUDP_H_
+
+#include <Arduino.h>
+#include <Udp.h>
+#include <cbuf.h>
+
+class NetworkUDP : public UDP {
+private:
+  int udp_server;
+  IPAddress multicast_ip;
+  IPAddress remote_ip;
+  uint16_t server_port;
+  uint16_t remote_port;
+  char *tx_buffer;
+  size_t tx_buffer_len;
+  cbuf *rx_buffer;
+
+public:
+  NetworkUDP();
+  ~NetworkUDP();
+  uint8_t begin(IPAddress a, uint16_t p);
+  uint8_t begin(uint16_t p);
+  uint8_t beginMulticast(IPAddress a, uint16_t p);
+  void stop();
+  int beginMulticastPacket();
+  int beginPacket();
+  int beginPacket(IPAddress ip, uint16_t port);
+  int beginPacket(const char *host, uint16_t port);
+  int endPacket();
+  size_t write(uint8_t);
+  size_t write(const uint8_t *buffer, size_t size);
+  [[deprecated("Use clear() instead.")]]
+  void flush();  // Print::flush tx
+  int parsePacket();
+  int available();
+  int read();
+  int read(unsigned char *buffer, size_t len);
+  int read(char *buffer, size_t len);
+  int peek();
+  void clear();  // clear rx
+  IPAddress remoteIP();
+  uint16_t remotePort();
+};
+
+#endif /* _NETWORKUDP_H_ */
diff --git a/libraries/NetworkClientSecure/README.md b/libraries/NetworkClientSecure/README.md
new file mode 100644
index 00000000000..f83cf246287
--- /dev/null
+++ b/libraries/NetworkClientSecure/README.md
@@ -0,0 +1,119 @@
+NetworkClientSecure
+================
+
+The NetworkClientSecure class implements support for secure connections using TLS (SSL).
+It inherits from NetworkClient and thus implements a superset of that class' interface.
+There are three ways to establish a secure connection using the NetworkClientSecure class:
+using a root certificate authority (CA) cert, using a root CA cert plus a client cert and key,
+and using a pre-shared key (PSK).
+
+Using a root certificate authority cert
+---------------------------------------
+This method authenticates the server and negotiates an encrypted connection.
+It is the same functionality as implemented in your web browser when you connect to HTTPS sites.
+
+If you are accessing your own server:
+- Generate a root certificate for your own certificate authority
+- Generate a cert & private key using your root certificate ("self-signed cert") for your server
+
+If you are accessing a public server:
+- Obtain the cert of the public CA that signed that server's cert
+Then:
+- In NetworkClientSecure use setCACert (or the appropriate connect method) to set the root cert of your
+  CA or of the public CA
+- When NetworkClientSecure connects to the target server it uses the CA cert to verify the certificate
+  presented by the server, and then negotiates encryption for the connection
+
+Please see the NetworkClientSecure example.
+
+Using a bundle of root certificate authority certificates
+---------------------------------------------------------
+This method is similar to the single root certificate verification above, but it uses a standard set of
+root certificates from Mozilla to authenticate against, while the previous method only accepts a single
+certificate for a given server. This allows the client to connect to all public SSL servers.
+
+To use this feature in Arduino IDE:
+If the Arduino IDE added support for embedding files in the meantime, then follow the instructions above.
+If not, you have two choices:
+1. create a makefile where you can add the idf_component_register() declaration to include the certificate bundle
+2. Store the bundle as a SPIFFS file, but then you have to load it into RAM in runtime and waste 64k of precious memory
+
+Using a root CA cert and client cert/keys
+-----------------------------------------
+This method authenticates the server and additionally also authenticates
+the client to the server, then negotiates an encrypted connection.
+
+- Follow steps above
+- Using your root CA generate cert/key for your client
+- Register the keys with the server you will be accessing so the server can authenticate your client
+- In NetworkClientSecure use setCACert (or the appropriate connect method) to set the root cert of your
+  CA or of the public CA, this is used to authenticate the server
+- In NetworkClientSecure use setCertificate, and setPrivateKey (or the appropriate connect method) to
+  set your client's cert & key, this will be used to authenticate your client to the server
+- When NetworkClientSecure connects to the target server it uses the CA cert to verify the certificate
+  presented by the server, it will use the cert/key to authenticate your client to the server, and
+  it will then negotiate encryption for the connection
+
+Using Pre-Shared Keys (PSK)
+---------------------------
+
+TLS supports authentication and encryption using a pre-shared key (i.e. a key that both client and
+server know) as an alternative to the public key cryptography commonly used on the web for HTTPS.
+PSK is starting to be used for MQTT, e.g. in mosquitto, to simplify the set-up and avoid having to
+go through the whole CA, cert, and private key process.
+
+A pre-shared key is a binary string of up to 32 bytes and is commonly represented in hex form. In
+addition to the key, clients can also present an id and typically the server allows a different key
+to be associated with each client id. In effect this is very similar to username and password pairs,
+except that unlike a password the key is not directly transmitted to the server, thus a connection to a
+malicious server does not divulge the password. Plus the server is also authenticated to the client.
+
+To use PSK:
+- Generate a random hex string (generating an MD5 or SHA for some file is one way to do this)
+- Come up with a string id for your client and configure your server to accept the id/key pair
+- In NetworkClientSecure use setPreSharedKey (or the appropriate connect method) to
+  set the id/key combo
+- When NetworkClientSecure connects to the target server it uses the id/key combo to authenticate the
+  server (it must prove that it has the key too), authenticate the client and then negotiate
+  encryption for the connection
+
+Please see the NetworkClientPSK example.
+
+Specifying the ALPN Protocol
+----------------------------
+
+Application-Layer Protocol Negotiation (ALPN) is a Transport Layer Security (TLS) extension that allows
+the application layer to negotiate which protocol should be performed over a secure connection in a manner
+that avoids additional round trips and which is independent of the application-layer protocols.
+
+For example, this is used with AWS IoT Custom Authorizers where an MQTT client must set the ALPN protocol to ```mqtt```:
+
+```
+const char *aws_protos[] = {"mqtt", NULL};
+...
+wiFiClient.setAlpnProtocols(aws_protos);
+```
+
+Examples
+--------
+#### NetworkClientInsecure
+Demonstrates usage of insecure connection using `NetworkClientSecure::setInsecure()`
+#### NetworkClientPSK
+Wi-Fi secure connection example for ESP32 using a pre-shared key (PSK)
+This is useful with MQTT servers instead of using a self-signed cert, tested with mosquitto.
+Running on TLS 1.2 using mbedTLS
+#### NetworkClientSecure
+Wi-Fi secure connection example for ESP32
+Running on TLS 1.2 using mbedTLS
+#### NetworkClientSecureEnterprise
+This example demonstrates a secure connection to a Wi-Fi network using WPA/WPA2 Enterprise (for example eduroam),
+and establishing a secure HTTPS connection with an external server (for example arduino.php5.sk) using the defined anonymous identity, user identity, and password.
+
+.. note::
+  This example is outdated and might not work. For more examples see [https://github.com/martinius96/ESP32-eduroam](https://github.com/martinius96/ESP32-eduroam)
+
+#### NetworkClientShowPeerCredentials
+Example of a establishing a secure connection and then showing the fingerprint of the certificate.
+This can be useful in an IoT setting to know for sure that you are connecting to the right server.
+Especially in situations where you cannot hardcode a trusted root certificate for long
+periods of time (as they tend to get replaced more often than the lifecycle of IoT hardware).
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientInsecure/WiFiClientInsecure.ino b/libraries/NetworkClientSecure/examples/WiFiClientInsecure/WiFiClientInsecure.ino
new file mode 100644
index 00000000000..95009c819ef
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientInsecure/WiFiClientInsecure.ino
@@ -0,0 +1,70 @@
+#include <NetworkClientSecure.h>
+#include <WiFi.h>
+
+/* This is a very INSECURE approach.
+ * If for some reason the secure, proper example NetworkClientSecure
+ * does not work for you; then you may want to check the
+ * NetworkClientTrustOnFirstUse example first. It is less secure than
+ * NetworkClientSecure, but a lot better than this totally insecure
+ * approach shown below.
+ */
+
+const char *ssid = "your-ssid";          // your network SSID (name of wifi network)
+const char *password = "your-password";  // your network password
+
+const char *server = "www.howsmyssl.com";  // Server URL
+
+NetworkClientSecure client;
+
+void setup() {
+  //Initialize serial and wait for port to open:
+  Serial.begin(115200);
+  delay(100);
+
+  Serial.print("Attempting to connect to SSID: ");
+  Serial.println(ssid);
+  WiFi.begin(ssid, password);
+
+  // attempt to connect to Wifi network:
+  while (WiFi.status() != WL_CONNECTED) {
+    Serial.print(".");
+    // wait 1 second for re-trying
+    delay(1000);
+  }
+
+  Serial.print("Connected to ");
+  Serial.println(ssid);
+
+  Serial.println("\nStarting connection to server...");
+  client.setInsecure();  //skip verification
+  if (!client.connect(server, 443)) {
+    Serial.println("Connection failed!");
+  } else {
+    Serial.println("Connected to server!");
+    // Make a HTTP request:
+    client.println("GET https://www.howsmyssl.com/a/check HTTP/1.0");
+    client.println("Host: www.howsmyssl.com");
+    client.println("Connection: close");
+    client.println();
+
+    while (client.connected()) {
+      String line = client.readStringUntil('\n');
+      if (line == "\r") {
+        Serial.println("headers received");
+        break;
+      }
+    }
+    // if there are incoming bytes available
+    // from the server, read them and print them:
+    while (client.available()) {
+      char c = client.read();
+      Serial.write(c);
+    }
+
+    client.stop();
+  }
+}
+
+void loop() {
+  // do nothing
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientInsecure/ci.json b/libraries/NetworkClientSecure/examples/WiFiClientInsecure/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientInsecure/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFiClientSecure/examples/WiFiClientPSK/WiFiClientPSK.ino b/libraries/NetworkClientSecure/examples/WiFiClientPSK/WiFiClientPSK.ino
similarity index 80%
rename from libraries/WiFiClientSecure/examples/WiFiClientPSK/WiFiClientPSK.ino
rename to libraries/NetworkClientSecure/examples/WiFiClientPSK/WiFiClientPSK.ino
index bd3ffbeda05..42bc8865b98 100644
--- a/libraries/WiFiClientSecure/examples/WiFiClientPSK/WiFiClientPSK.ino
+++ b/libraries/NetworkClientSecure/examples/WiFiClientPSK/WiFiClientPSK.ino
@@ -10,24 +10,25 @@
   2018 - Adapted for PSK by Thorsten von Eicken
 */
 
-#include <WiFiClientSecure.h>
+#include <NetworkClientSecure.h>
+#include <WiFi.h>
 
 #if 0
 const char* ssid     = "your-ssid";     // your network SSID (name of wifi network)
 const char* password = "your-password"; // your network password
 #else
-const char* ssid     = "test";     // your network SSID (name of wifi network)
-const char* password = "securetest"; // your network password
+const char *ssid = "test";            // your network SSID (name of wifi network)
+const char *password = "securetest";  // your network password
 #endif
 
 //const char*  server = "server.local";  // Server hostname
 const IPAddress server = IPAddress(192, 168, 0, 14);  // Server IP address
-const int    port = 8443; // server's port (8883 for MQTT)
+const int port = 8443;                                // server's port (8883 for MQTT)
 
-const char*  pskIdent = "Client_identity"; // PSK identity (sometimes called key hint)
-const char*  psKey = "1a2b3c4d"; // PSK Key (must be hex string without 0x)
+const char *pskIdent = "Client_identity";  // PSK identity (sometimes called key hint)
+const char *psKey = "1a2b3c4d";            // PSK Key (must be hex string without 0x)
 
-WiFiClientSecure client;
+NetworkClientSecure client;
 
 void setup() {
   //Initialize serial and wait for port to open:
@@ -51,9 +52,9 @@ void setup() {
   client.setPreSharedKey(pskIdent, psKey);
 
   Serial.println("\nStarting connection to server...");
-  if (!client.connect(server, port))
+  if (!client.connect(server, port)) {
     Serial.println("Connection failed!");
-  else {
+  } else {
     Serial.println("Connected to server!");
     // Make a HTTP request:
     client.println("GET /a/check HTTP/1.0");
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientPSK/ci.json b/libraries/NetworkClientSecure/examples/WiFiClientPSK/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientPSK/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino b/libraries/NetworkClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino
new file mode 100644
index 00000000000..0f95826decb
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino
@@ -0,0 +1,112 @@
+/*
+  Wifi secure connection example for ESP32
+  Running on TLS 1.2 using mbedTLS
+  Supporting the following ciphersuites:
+  "TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384","TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384","TLS_DHE_RSA_WITH_AES_256_GCM_SHA384","TLS_ECDHE_ECDSA_WITH_AES_256_CCM","TLS_DHE_RSA_WITH_AES_256_CCM","TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384","TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384","TLS_DHE_RSA_WITH_AES_256_CBC_SHA256","TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA","TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA","TLS_DHE_RSA_WITH_AES_256_CBC_SHA","TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8","TLS_DHE_RSA_WITH_AES_256_CCM_8","TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384","TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384","TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256","TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA","TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256","TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256","TLS_DHE_RSA_WITH_AES_128_GCM_SHA256","TLS_ECDHE_ECDSA_WITH_AES_128_CCM","TLS_DHE_RSA_WITH_AES_128_CCM","TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256","TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256","TLS_DHE_RSA_WITH_AES_128_CBC_SHA256","TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA","TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA","TLS_DHE_RSA_WITH_AES_128_CBC_SHA","TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8","TLS_DHE_RSA_WITH_AES_128_CCM_8","TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA","TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA","TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA","TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA","TLS_DHE_PSK_WITH_AES_256_GCM_SHA384","TLS_DHE_PSK_WITH_AES_256_CCM","TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384","TLS_DHE_PSK_WITH_AES_256_CBC_SHA384","TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA","TLS_DHE_PSK_WITH_AES_256_CBC_SHA","TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384","TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384","TLS_PSK_DHE_WITH_AES_256_CCM_8","TLS_DHE_PSK_WITH_AES_128_GCM_SHA256","TLS_DHE_PSK_WITH_AES_128_CCM","TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256","TLS_DHE_PSK_WITH_AES_128_CBC_SHA256","TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA","TLS_DHE_PSK_WITH_AES_128_CBC_SHA","TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256","TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256","TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256","TLS_PSK_DHE_WITH_AES_128_CCM_8","TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA","TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA","TLS_RSA_WITH_AES_256_GCM_SHA384","TLS_RSA_WITH_AES_256_CCM","TLS_RSA_WITH_AES_256_CBC_SHA256","TLS_RSA_WITH_AES_256_CBC_SHA","TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384","TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384","TLS_ECDH_RSA_WITH_AES_256_CBC_SHA","TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384","TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384","TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA","TLS_RSA_WITH_AES_256_CCM_8","TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256","TLS_RSA_WITH_CAMELLIA_256_CBC_SHA","TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384","TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384","TLS_RSA_WITH_AES_128_GCM_SHA256","TLS_RSA_WITH_AES_128_CCM","TLS_RSA_WITH_AES_128_CBC_SHA256","TLS_RSA_WITH_AES_128_CBC_SHA","TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256","TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256","TLS_ECDH_RSA_WITH_AES_128_CBC_SHA","TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256","TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256","TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA","TLS_RSA_WITH_AES_128_CCM_8","TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_RSA_WITH_CAMELLIA_128_CBC_SHA","TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_RSA_WITH_3DES_EDE_CBC_SHA","TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA","TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA","TLS_RSA_PSK_WITH_AES_256_GCM_SHA384","TLS_RSA_PSK_WITH_AES_256_CBC_SHA384","TLS_RSA_PSK_WITH_AES_256_CBC_SHA","TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384","TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384","TLS_RSA_PSK_WITH_AES_128_GCM_SHA256","TLS_RSA_PSK_WITH_AES_128_CBC_SHA256","TLS_RSA_PSK_WITH_AES_128_CBC_SHA","TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256","TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256","TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA","TLS_PSK_WITH_AES_256_GCM_SHA384","TLS_PSK_WITH_AES_256_CCM","TLS_PSK_WITH_AES_256_CBC_SHA384","TLS_PSK_WITH_AES_256_CBC_SHA","TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384","TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384","TLS_PSK_WITH_AES_256_CCM_8","TLS_PSK_WITH_AES_128_GCM_SHA256","TLS_PSK_WITH_AES_128_CCM","TLS_PSK_WITH_AES_128_CBC_SHA256","TLS_PSK_WITH_AES_128_CBC_SHA","TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256","TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256","TLS_PSK_WITH_AES_128_CCM_8","TLS_PSK_WITH_3DES_EDE_CBC_SHA","TLS_EMPTY_RENEGOTIATION_INFO_SCSV"]
+  2017 - Evandro Copercini - Apache 2.0 License.
+*/
+
+#include <NetworkClientSecure.h>
+#include <WiFi.h>
+
+const char *ssid = "your-ssid";          // your network SSID (name of wifi network)
+const char *password = "your-password";  // your network password
+
+const char *server = "www.howsmyssl.com";  // Server URL
+
+// www.howsmyssl.com root certificate authority, to verify the server
+// change it to your server root CA
+// SHA1 fingerprint is broken now!
+
+const char *test_root_ca = R"literal(
+-----BEGIN CERTIFICATE-----
+MIIFBTCCAu2gAwIBAgIQS6hSk/eaL6JzBkuoBI110DANBgkqhkiG9w0BAQsFADBP
+MQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJuZXQgU2VjdXJpdHkgUmVzZWFy
+Y2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBYMTAeFw0yNDAzMTMwMDAwMDBa
+Fw0yNzAzMTIyMzU5NTlaMDMxCzAJBgNVBAYTAlVTMRYwFAYDVQQKEw1MZXQncyBF
+bmNyeXB0MQwwCgYDVQQDEwNSMTAwggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEK
+AoIBAQDPV+XmxFQS7bRH/sknWHZGUCiMHT6I3wWd1bUYKb3dtVq/+vbOo76vACFL
+YlpaPAEvxVgD9on/jhFD68G14BQHlo9vH9fnuoE5CXVlt8KvGFs3Jijno/QHK20a
+/6tYvJWuQP/py1fEtVt/eA0YYbwX51TGu0mRzW4Y0YCF7qZlNrx06rxQTOr8IfM4
+FpOUurDTazgGzRYSespSdcitdrLCnF2YRVxvYXvGLe48E1KGAdlX5jgc3421H5KR
+mudKHMxFqHJV8LDmowfs/acbZp4/SItxhHFYyTr6717yW0QrPHTnj7JHwQdqzZq3
+DZb3EoEmUVQK7GH29/Xi8orIlQ2NAgMBAAGjgfgwgfUwDgYDVR0PAQH/BAQDAgGG
+MB0GA1UdJQQWMBQGCCsGAQUFBwMCBggrBgEFBQcDATASBgNVHRMBAf8ECDAGAQH/
+AgEAMB0GA1UdDgQWBBS7vMNHpeS8qcbDpHIMEI2iNeHI6DAfBgNVHSMEGDAWgBR5
+tFnme7bl5AFzgAiIyBpY9umbbjAyBggrBgEFBQcBAQQmMCQwIgYIKwYBBQUHMAKG
+Fmh0dHA6Ly94MS5pLmxlbmNyLm9yZy8wEwYDVR0gBAwwCjAIBgZngQwBAgEwJwYD
+VR0fBCAwHjAcoBqgGIYWaHR0cDovL3gxLmMubGVuY3Iub3JnLzANBgkqhkiG9w0B
+AQsFAAOCAgEAkrHnQTfreZ2B5s3iJeE6IOmQRJWjgVzPw139vaBw1bGWKCIL0vIo
+zwzn1OZDjCQiHcFCktEJr59L9MhwTyAWsVrdAfYf+B9haxQnsHKNY67u4s5Lzzfd
+u6PUzeetUK29v+PsPmI2cJkxp+iN3epi4hKu9ZzUPSwMqtCceb7qPVxEbpYxY1p9
+1n5PJKBLBX9eb9LU6l8zSxPWV7bK3lG4XaMJgnT9x3ies7msFtpKK5bDtotij/l0
+GaKeA97pb5uwD9KgWvaFXMIEt8jVTjLEvwRdvCn294GPDF08U8lAkIv7tghluaQh
+1QnlE4SEN4LOECj8dsIGJXpGUk3aU3KkJz9icKy+aUgA+2cP21uh6NcDIS3XyfaZ
+QjmDQ993ChII8SXWupQZVBiIpcWO4RqZk3lr7Bz5MUCwzDIA359e57SSq5CCkY0N
+4B6Vulk7LktfwrdGNVI5BsC9qqxSwSKgRJeZ9wygIaehbHFHFhcBaMDKpiZlBHyz
+rsnnlFXCb5s8HKn5LsUgGvB24L7sGNZP2CX7dhHov+YhD+jozLW2p9W4959Bz2Ei
+RmqDtmiXLnzqTpXbI+suyCsohKRg6Un0RC47+cpiVwHiXZAW+cn8eiNIjqbVgXLx
+KPpdzvvtTnOPlC7SQZSYmdunr3Bf9b77AiC/ZidstK36dRILKz7OA54=
+-----END CERTIFICATE-----
+)literal";
+// You can use x.509 client certificates if you want
+//const char* test_client_key = "";   //to verify the client
+//const char* test_client_cert = "";  //to verify the client
+
+NetworkClientSecure client;
+
+void setup() {
+  //Initialize serial and wait for port to open:
+  Serial.begin(115200);
+  delay(100);
+
+  Serial.print("Attempting to connect to SSID: ");
+  Serial.println(ssid);
+  WiFi.begin(ssid, password);
+
+  // attempt to connect to Wifi network:
+  while (WiFi.status() != WL_CONNECTED) {
+    Serial.print(".");
+    // wait 1 second for re-trying
+    delay(1000);
+  }
+
+  Serial.print("Connected to ");
+  Serial.println(ssid);
+
+  client.setCACert(test_root_ca);
+  //client.setCertificate(test_client_cert); // for client verification
+  //client.setPrivateKey(test_client_key);	// for client verification
+
+  Serial.println("\nStarting connection to server...");
+  if (!client.connect(server, 443)) {
+    Serial.println("Connection failed!");
+  } else {
+    Serial.println("Connected to server!");
+    // Make a HTTP request:
+    client.println("GET https://www.howsmyssl.com/a/check HTTP/1.0");
+    client.println("Host: www.howsmyssl.com");
+    client.println("Connection: close");
+    client.println();
+
+    while (client.connected()) {
+      String line = client.readStringUntil('\n');
+      if (line == "\r") {
+        Serial.println("headers received");
+        break;
+      }
+    }
+    // if there are incoming bytes available
+    // from the server, read them and print them:
+    while (client.available()) {
+      char c = client.read();
+      Serial.write(c);
+    }
+
+    client.stop();
+  }
+}
+
+void loop() {
+  // do nothing
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientSecure/ci.json b/libraries/NetworkClientSecure/examples/WiFiClientSecure/ci.json
new file mode 100644
index 00000000000..cbdd28f773d
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientSecure/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientSecureEnterprise/WiFiClientSecureEnterprise.ino b/libraries/NetworkClientSecure/examples/WiFiClientSecureEnterprise/WiFiClientSecureEnterprise.ino
new file mode 100644
index 00000000000..b9e01d15682
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientSecureEnterprise/WiFiClientSecureEnterprise.ino
@@ -0,0 +1,137 @@
+/*|-----------------------------------------------------------|*/
+/*|WORKING EXAMPLE FOR HTTPS CONNECTION                       |*/
+/*|Author: Bc. Martin Chlebovec                               |*/
+/*|Technical University of Košice                             |*/
+/*|TESTED BOARDS: Devkit v1 DOIT, Devkitc v4                  |*/
+/*|CORE: 0.9x, 1.0.0, 1.0.1 tested, working (newer not tested)|*/
+/*|Supported methods: PEAP + MsCHAPv2, EAP-TTLS + MsCHAPv2    |*/
+/*|-----------------------------------------------------------|*/
+
+// This example demonstrates a secure connection to a WiFi network using WPA/WPA2 Enterprise (for example eduroam),
+// and establishing a secure HTTPS connection with an external server (for example arduino.php5.sk) using the defined anonymous identity, user identity, and password.
+
+// Note: this example is outdated and may not work!
+// For more examples see https://github.com/martinius96/ESP32-eduroam
+
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#error "WPA-Enterprise is only supported in SoCs with native Wi-Fi support"
+#endif
+
+#include <WiFi.h>
+#include <NetworkClientSecure.h>
+#if __has_include("esp_eap_client.h")
+#include "esp_eap_client.h"
+#else
+#include "esp_wpa2.h"
+#endif
+#include <Wire.h>
+#define EAP_ANONYMOUS_IDENTITY "anonymous@example.com"  //anonymous identity
+#define EAP_IDENTITY           "id@example.com"         //user identity
+#define EAP_PASSWORD           "password"               //eduroam user password
+const char *ssid = "eduroam";                           // eduroam SSID
+const char *host = "arduino.php5.sk";                   //external server domain for HTTPS connection
+int counter = 0;
+const char *test_root_ca = "-----BEGIN CERTIFICATE-----\n"
+                           "MIIEsTCCA5mgAwIBAgIQCKWiRs1LXIyD1wK0u6tTSTANBgkqhkiG9w0BAQsFADBh\n"
+                           "MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3\n"
+                           "d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBD\n"
+                           "QTAeFw0xNzExMDYxMjIzMzNaFw0yNzExMDYxMjIzMzNaMF4xCzAJBgNVBAYTAlVT\n"
+                           "MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j\n"
+                           "b20xHTAbBgNVBAMTFFJhcGlkU1NMIFJTQSBDQSAyMDE4MIIBIjANBgkqhkiG9w0B\n"
+                           "AQEFAAOCAQ8AMIIBCgKCAQEA5S2oihEo9nnpezoziDtx4WWLLCll/e0t1EYemE5n\n"
+                           "+MgP5viaHLy+VpHP+ndX5D18INIuuAV8wFq26KF5U0WNIZiQp6mLtIWjUeWDPA28\n"
+                           "OeyhTlj9TLk2beytbtFU6ypbpWUltmvY5V8ngspC7nFRNCjpfnDED2kRyJzO8yoK\n"
+                           "MFz4J4JE8N7NA1uJwUEFMUvHLs0scLoPZkKcewIRm1RV2AxmFQxJkdf7YN9Pckki\n"
+                           "f2Xgm3b48BZn0zf0qXsSeGu84ua9gwzjzI7tbTBjayTpT+/XpWuBVv6fvarI6bik\n"
+                           "KB859OSGQuw73XXgeuFwEPHTIRoUtkzu3/EQ+LtwznkkdQIDAQABo4IBZjCCAWIw\n"
+                           "HQYDVR0OBBYEFFPKF1n8a8ADIS8aruSqqByCVtp1MB8GA1UdIwQYMBaAFAPeUDVW\n"
+                           "0Uy7ZvCj4hsbw5eyPdFVMA4GA1UdDwEB/wQEAwIBhjAdBgNVHSUEFjAUBggrBgEF\n"
+                           "BQcDAQYIKwYBBQUHAwIwEgYDVR0TAQH/BAgwBgEB/wIBADA0BggrBgEFBQcBAQQo\n"
+                           "MCYwJAYIKwYBBQUHMAGGGGh0dHA6Ly9vY3NwLmRpZ2ljZXJ0LmNvbTBCBgNVHR8E\n"
+                           "OzA5MDegNaAzhjFodHRwOi8vY3JsMy5kaWdpY2VydC5jb20vRGlnaUNlcnRHbG9i\n"
+                           "YWxSb290Q0EuY3JsMGMGA1UdIARcMFowNwYJYIZIAYb9bAECMCowKAYIKwYBBQUH\n"
+                           "AgEWHGh0dHBzOi8vd3d3LmRpZ2ljZXJ0LmNvbS9DUFMwCwYJYIZIAYb9bAEBMAgG\n"
+                           "BmeBDAECATAIBgZngQwBAgIwDQYJKoZIhvcNAQELBQADggEBAH4jx/LKNW5ZklFc\n"
+                           "YWs8Ejbm0nyzKeZC2KOVYR7P8gevKyslWm4Xo4BSzKr235FsJ4aFt6yAiv1eY0tZ\n"
+                           "/ZN18bOGSGStoEc/JE4ocIzr8P5Mg11kRYHbmgYnr1Rxeki5mSeb39DGxTpJD4kG\n"
+                           "hs5lXNoo4conUiiJwKaqH7vh2baryd8pMISag83JUqyVGc2tWPpO0329/CWq2kry\n"
+                           "qv66OSMjwulUz0dXf4OHQasR7CNfIr+4KScc6ABlQ5RDF86PGeE6kdwSQkFiB/cQ\n"
+                           "ysNyq0jEDQTkfa2pjmuWtMCNbBnhFXBYejfubIhaUbEv2FOQB3dCav+FPg5eEveX\n"
+                           "TVyMnGo=\n"
+                           "-----END CERTIFICATE-----\n";
+// You can use x.509 client certificates if you want
+//const char* test_client_key = "";   //to verify the client
+//const char* test_client_cert = "";  //to verify the client
+NetworkClientSecure client;
+void setup() {
+  Serial.begin(115200);
+  delay(10);
+  Serial.println();
+  Serial.print("Connecting to network: ");
+  Serial.println(ssid);
+  WiFi.disconnect(true);  //disconnect form wifi to set new wifi connection
+  WiFi.mode(WIFI_STA);    //init wifi mode
+#if __has_include("esp_eap_client.h")
+  esp_eap_client_set_identity((uint8_t *)EAP_ANONYMOUS_IDENTITY, strlen(EAP_ANONYMOUS_IDENTITY));  //provide identity
+  esp_eap_client_set_username((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY));                      //provide username
+  esp_eap_client_set_password((uint8_t *)EAP_PASSWORD, strlen(EAP_PASSWORD));                      //provide password
+  esp_wifi_sta_enterprise_enable();
+#else
+  esp_wifi_sta_wpa2_ent_set_identity((uint8_t *)EAP_ANONYMOUS_IDENTITY, strlen(EAP_ANONYMOUS_IDENTITY));  //provide identity
+  esp_wifi_sta_wpa2_ent_set_username((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY));                      //provide username
+  esp_wifi_sta_wpa2_ent_set_password((uint8_t *)EAP_PASSWORD, strlen(EAP_PASSWORD));                      //provide password
+  esp_wifi_sta_wpa2_ent_enable();
+#endif
+  WiFi.begin(ssid);  //connect to wifi
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+    counter++;
+    if (counter >= 60) {  //after 30 seconds timeout - reset board (on unsuccessful connection)
+      ESP.restart();
+    }
+  }
+  client.setCACert(test_root_ca);
+  //client.setCertificate(test_client_cert); // for client verification - certificate
+  //client.setPrivateKey(test_client_key);  // for client verification - private key
+  Serial.println("");
+  Serial.println("WiFi connected");
+  Serial.println("IP address set: ");
+  Serial.println(WiFi.localIP());  //print LAN IP
+}
+void loop() {
+  if (WiFi.status() == WL_CONNECTED) {  //if we are connected to eduroam network
+    counter = 0;                        //reset counter
+    Serial.println("Wifi is still connected with IP: ");
+    Serial.println(WiFi.localIP());            //inform user about his IP address
+  } else if (WiFi.status() != WL_CONNECTED) {  //if we lost connection, retry
+    WiFi.begin(ssid);
+  }
+  while (WiFi.status() != WL_CONNECTED) {  //during lost connection, print dots
+    delay(500);
+    Serial.print(".");
+    counter++;
+    if (counter >= 60) {  //30 seconds timeout - reset board
+      ESP.restart();
+    }
+  }
+  Serial.print("Connecting to website: ");
+  Serial.println(host);
+  if (client.connect(host, 443)) {
+    String url = "/rele/rele1.txt";
+    client.print(String("GET ") + url + " HTTP/1.1\r\n" + "Host: " + host + "\r\n" + "User-Agent: ESP32\r\n" + "Connection: close\r\n\r\n");
+    while (client.connected()) {
+      String header = client.readStringUntil('\n');
+      Serial.println(header);
+      if (header == "\r") {
+        break;
+      }
+    }
+    String line = client.readStringUntil('\n');
+    Serial.println(line);
+  } else {
+    Serial.println("Connection unsuccessful");
+  }
+  delay(5000);
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientSecureEnterprise/ci.json b/libraries/NetworkClientSecure/examples/WiFiClientSecureEnterprise/ci.json
new file mode 100644
index 00000000000..04eb62b977a
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientSecureEnterprise/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientSecureProtocolUpgrade/WiFiClientSecureProtocolUpgrade.ino b/libraries/NetworkClientSecure/examples/WiFiClientSecureProtocolUpgrade/WiFiClientSecureProtocolUpgrade.ino
new file mode 100644
index 00000000000..a6f76cb8aa9
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientSecureProtocolUpgrade/WiFiClientSecureProtocolUpgrade.ino
@@ -0,0 +1,190 @@
+/* STARTSSL example
+
+   Inline upgrading from a clear-text connection to an SSL/TLS connection.
+
+   Some protocols such as SMTP, XMPP, Mysql, Postgresql and others allow, or require,
+   that you start the connection without encryption; and then send a command to switch
+   over to encryption.
+
+   E.g. a typical SMTP submission would entail a dialog such as this:
+
+   1. client connects to server in the clear
+   2. server says hello
+   3. client sents a EHLO
+   4. server tells the client that it supports SSL/TLS
+   5. client sends a 'STARTTLS' to make use of this faciltiy
+   6. client/server negiotiate a SSL or TLS connection.
+   7. client sends another EHLO
+   8. server now tells the client what (else) is supported; such as additional authentication options.
+   ... conversation continues encrypted.
+
+   This can be enabled in NetworkClientSecure by telling it to start in plaintext:
+
+          client.setPlainStart();
+
+   and client is than a plain, TCP, connection (just as NetworkClient would be); until the client calls
+   the method:
+
+          client.startTLS(); // returns zero on error; non zero on success.
+
+    After which things switch to TLS/SSL.
+*/
+
+#include <WiFi.h>
+#include <NetworkClientSecure.h>
+
+#ifndef WIFI_NETWORK
+#define WIFI_NETWORK "YOUR Wifi SSID"
+#endif
+
+#ifndef WIFI_PASSWD
+#define WIFI_PASSWD "your-secret-password"
+#endif
+
+#ifndef SMTP_HOST
+#define SMTP_HOST "smtp.gmail.com"
+#endif
+
+#ifndef SMTP_PORT
+#define SMTP_PORT (587)  // Standard (plaintext) submission port
+#endif
+
+const char *ssid = WIFI_NETWORK;        // your network SSID (name of wifi network)
+const char *password = WIFI_PASSWD;     // your network password
+const char *server = SMTP_HOST;         // Server URL
+const int submission_port = SMTP_PORT;  // submission port.
+
+NetworkClientSecure client;
+
+static bool readAllSMTPLines();
+
+void setup() {
+  int ret;
+  //Initialize serial and wait for port to open:
+  Serial.begin(115200);
+  delay(100);
+
+  Serial.print("Attempting to connect to SSID: ");
+  Serial.print(ssid);
+  WiFi.begin(ssid, password);
+
+  // attempt to connect to Wifi network:
+  while (WiFi.status() != WL_CONNECTED) {
+    Serial.print(".");
+    // wait 1 second for re-trying
+    delay(1000);
+  }
+
+  Serial.print("Connected to ");
+  Serial.println(ssid);
+
+  Serial.printf("\nStarting connection to server: %s:%d\n", server, submission_port);
+
+  // skip verification for this demo. In production one should at the very least
+  // enable TOFU; or ideally hardcode a (CA) certificate that is trusted.
+  client.setInsecure();
+
+  // Enable a plain-test start.
+  client.setPlainStart();
+
+  if (!client.connect(server, SMTP_PORT)) {
+    Serial.println("Connection failed!");
+    return;
+  };
+
+  Serial.println("Connected to server (in the clear, in plaintest)");
+
+  if (!readAllSMTPLines()) {
+    goto err;
+  }
+
+  Serial.println("Sending  : EHLO\t\tin the clear");
+  client.print("EHLO there\r\n");
+
+  if (!readAllSMTPLines()) {
+    goto err;
+  }
+
+  Serial.println("Sending  : STARTTLS\t\tin the clear");
+  client.print("STARTTLS\r\n");
+
+  if (!readAllSMTPLines()) {
+    goto err;
+  }
+
+  Serial.println("Upgrading connection to TLS");
+  if ((ret = client.startTLS()) <= 0) {
+    Serial.printf("Upgrade connection failed: err %d\n", ret);
+    goto err;
+  }
+
+  Serial.println("Sending  : EHLO again\t\tover the now encrypted connection");
+  client.print("EHLO again\r\n");
+
+  if (!readAllSMTPLines()) {
+    goto err;
+  }
+
+  // normally, as this point - we'd be authenticating and then be submitting
+  // an email. This has been left out of this example.
+
+  Serial.println("Sending  : QUIT\t\t\tover the now encrypted connection");
+  client.print("QUIT\r\n");
+
+  if (!readAllSMTPLines()) {
+    goto err;
+  }
+
+  Serial.println("Completed OK\n");
+err:
+  Serial.println("Closing connection");
+  client.stop();
+}
+
+// SMTP command repsponse start with three digits and a space;
+// or, for continuation, with three digits and a '-'.
+static bool readAllSMTPLines() {
+  String s = "";
+  int i;
+
+  // blocking read; we cannot rely on a timeout
+  // of a NetworkClientSecure read; as it is non
+  // blocking.
+  const unsigned long timeout = 15 * 1000;
+  unsigned long start = millis();  // the timeout is for the entire CMD block response; not per character/line.
+  while (1) {
+    while ((i = client.available()) == 0 && millis() - start < timeout) {
+      /* .. wait */
+    };
+    if (i == 0) {
+      Serial.println("Timeout reading SMTP response");
+      return false;
+    };
+    if (i < 0) {
+      break;
+    }
+
+    i = client.read();
+    if (i < 0) {
+      break;
+    }
+
+    if (i > 31 && i < 128) {
+      s += (char)i;
+    }
+    if (i == 0x0A) {
+      Serial.print("Receiving: ");
+      Serial.println(s);
+      if (s.charAt(3) == ' ') {
+        return true;
+      }
+      s = "";
+    }
+  }
+  Serial.printf("Error reading SMTP command response line: %d\n", i);
+  return false;
+}
+
+void loop() {
+  // do nothing
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientSecureProtocolUpgrade/ci.json b/libraries/NetworkClientSecure/examples/WiFiClientSecureProtocolUpgrade/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientSecureProtocolUpgrade/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientShowPeerCredentials/WiFiClientShowPeerCredentials.ino b/libraries/NetworkClientSecure/examples/WiFiClientShowPeerCredentials/WiFiClientShowPeerCredentials.ino
new file mode 100644
index 00000000000..be120501d16
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientShowPeerCredentials/WiFiClientShowPeerCredentials.ino
@@ -0,0 +1,98 @@
+// NetworkClientShowPeerCredentials
+//
+// Example of a establishing a secure connection and then
+// showing the fingerprint of the certificate. This can
+// be useful in an IoT setting to know for sure that you
+// are connecting to the right server. Especially in
+// situations where you cannot hardcode a trusted root
+// certificate for long periods of time (as they tend to
+// get replaced more often than the lifecycle of IoT
+// hardware).
+//
+
+#include <WiFi.h>
+#include <HTTPClient.h>
+#include <NetworkClientSecure.h>
+
+#ifndef WIFI_NETWORK
+#define WIFI_NETWORK "MyWifiNetwork"
+#endif
+
+#ifndef WIFI_PASSWD
+#define WIFI_PASSWD "MySecretWifiPassword"
+#endif
+
+#define URL "https://arduino.cc"
+
+void demo() {
+  NetworkClientSecure *client = new NetworkClientSecure;
+  client->setInsecure();  //
+
+  HTTPClient https;
+  if (!https.begin(*client, URL)) {
+    Serial.println("HTTPS setup failed");
+    return;
+  };
+
+  https.setTimeout(5000);
+
+  int httpCode = https.GET();
+  if (httpCode != 200) {
+    Serial.print("Connect failed: ");
+    Serial.println(https.errorToString(httpCode));
+    return;
+  }
+
+  const mbedtls_x509_crt *peer = client->getPeerCertificate();
+
+  // Show general output / certificate information
+  //
+  char buf[1024];
+  int l = mbedtls_x509_crt_info(buf, sizeof(buf), "", peer);
+  if (l <= 0) {
+    Serial.println("Peer conversion to printable buffer failed");
+    return;
+  };
+  Serial.println();
+  Serial.println(buf);
+
+  uint8_t fingerprint_remote[32];
+  if (!client->getFingerprintSHA256(fingerprint_remote)) {
+    Serial.println("Failed to get the fingerprint");
+    return;
+  }
+  // Fingerprint late 2021
+  Serial.println("Expecting Fingerprint (SHA256): 70 CF A4 B7 5D 09 E9 2A 52 A8 B6 85 B5 0B D6 BE 83 47 83 5B 3A 4D 3C 3E 32 30 EC 1D 61 98 D7 0F");
+  Serial.print(" Received Fingerprint (SHA256): ");
+
+  for (int i = 0; i < 32; i++) {
+    Serial.print(fingerprint_remote[i], HEX);
+    Serial.print(" ");
+  };
+  Serial.println("");
+};
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Started " __FILE__ " build " __DATE__ " " __TIME__);
+
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(WIFI_NETWORK, WIFI_PASSWD);
+
+  while (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("Wifi fail - rebooting");
+    delay(5000);
+    ESP.restart();
+  }
+}
+
+void loop() {
+  bool already_tried = false;
+  if ((millis() < 1000) || already_tried) {
+    return;
+  }
+  already_tried = true;
+
+  // Run the test just once.
+  demo();
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientShowPeerCredentials/ci.json b/libraries/NetworkClientSecure/examples/WiFiClientShowPeerCredentials/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientShowPeerCredentials/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientTrustOnFirstUse/WiFiClientTrustOnFirstUse.ino b/libraries/NetworkClientSecure/examples/WiFiClientTrustOnFirstUse/WiFiClientTrustOnFirstUse.ino
new file mode 100644
index 00000000000..afc588af76c
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientTrustOnFirstUse/WiFiClientTrustOnFirstUse.ino
@@ -0,0 +1,270 @@
+/* For any secure connection - it is (at least) essential for the
+   the client to verify that it is talking with the server it
+   thinks it is talking to. And not some (invisible) man in the middle.
+
+   See https://en.wikipedia.org/wiki/Man-in-the-middle_attack,
+   https://www.ai.rug.nl/mas/finishedprojects/2011/TLS/hermsencomputerservices.nl/mas/mitm.html or
+   https://medium.com/@munteanu210/ssl-certificates-vs-man-in-the-middle-attacks-3fb7846fa5db
+   for some background on this.
+
+   Unfortunately this means that one needs to hardcode a server
+   public key, certificate or some cryptographically strong hash
+   thereoff into the code, to verify that you are indeed talking to
+   the right server. This is sometimes somewhat impractical. Especially
+   if you do not know the server in advance; or if your code needs to be
+   stable ovr very long times - during which the server may change.
+
+   However completely dispensing with any checks (See the WifiClientInSecure
+   example) is also not a good idea either.
+
+   This example gives you some middle ground; "Trust on First Use" --
+   TOFU - see https://developer.mozilla.org/en-US/docs/Glossary/TOFU or
+   https://en.wikipedia.org/wiki/Trust_on_first_use).
+
+   In this scheme; we start the very first time without any security checks
+   but once we have our first connection; we store the public cryptographic
+   details (or a proxy, such as a sha256 of this). And then we use this for
+   any subsequent connections.
+
+   The assumption here is that we do our very first connection in a somewhat
+   trusted network environment; where the chance of a man in the middle is
+   very low; or one where the person doing the first run can check the
+   details manually.
+
+   So this is not quite as good as building a CA certificate into your
+   code (as per the WifiClientSecure example). But not as bad as something
+   with no trust management at all.
+
+   To make it possible for the enduser to 'reset' this trust; the
+   startup sequence checks if a certain GPIO is low (assumed to be wired
+   to some physical button or jumper on the PCB). And we only allow
+   the TOFU to be configured when this pin is LOW.
+*/
+#ifndef WIFI_NETWORK
+#define WIFI_NETWORK "Your Wifi SSID"
+#endif
+
+#ifndef WIFI_PASSWD
+#define WIFI_PASSWD "your-secret-wifi-password"
+#endif
+
+const char *ssid = WIFI_NETWORK;           // your network SSID (name of wifi network)
+const char *password = WIFI_PASSWD;        // your network password
+const char *server = "www.howsmyssl.com";  // Server to test with.
+
+const int TOFU_RESET_BUTTON = 35; /* Trust reset button wired between GPIO 35 and GND (pulldown) */
+
+#include <WiFi.h>
+#include <NetworkClientSecure.h>
+#include <EEPROM.h>
+
+/* Set aside some persistent memory (i.e. memory that is preserved on reboots and
+  power cycling; and will generally survive software updates as well.
+*/
+EEPROMClass TOFU("tofu0");
+
+// Utility function; checks if a given buffer is entirely
+// with with 0 bytes over its full length. Returns 0 on
+// success; a non zero value on fail.
+//
+static int memcmpzero(unsigned char *ptr, size_t len) {
+  while (len--) {
+    if (0xff != *ptr++) {
+      return -1;
+    }
+  }
+  return 0;
+};
+
+static void printSHA256(unsigned char *ptr) {
+  for (int i = 0; i < 32; i++) {
+    Serial.printf("%s%02x", i ? ":" : "", ptr[i]);
+  }
+  Serial.println("");
+};
+
+NetworkClientSecure client;
+
+bool get_tofu();
+bool doTOFU_Protected_Connection(uint8_t *fingerprint_tofu);
+
+void setup() {
+  bool tofu_reset = false;
+  //Initialize serial and wait for port to open:
+  Serial.begin(115200);
+  delay(100);
+
+  if (!TOFU.begin(32)) {
+    Serial.println("Could not initialsize the EEPROM");
+    return;
+  }
+  uint8_t fingerprint_tofu[32];
+
+  // reset the trust if the tofu reset button is pressed.
+  //
+  pinMode(TOFU_RESET_BUTTON, INPUT_PULLUP);
+  if (digitalRead(TOFU_RESET_BUTTON) == LOW) {
+    Serial.println("The TOFU reset button is pressed.");
+    tofu_reset = true;
+  }
+  /* if the button is not pressed; see if we can get the TOFU
+      fingerprint from the EEPROM.
+  */
+  else if (32 != TOFU.readBytes(0, fingerprint_tofu, 32)) {
+    Serial.println("Failed to get the fingerprint from memory.");
+    tofu_reset = true;
+  }
+  /* And check that the EEPROM value is not all 0's; in which
+      case we also need to do a TOFU.
+  */
+  else if (!memcmpzero(fingerprint_tofu, 32)) {
+    Serial.println("TOFU fingerprint in memory all zero.");
+    tofu_reset = true;
+  };
+  if (!tofu_reset) {
+    Serial.print("TOFU pegged to fingerprint: SHA256=");
+    printSHA256(fingerprint_tofu);
+    Serial.print("Note: You can check this fingerprint by going to the URL\n"
+                 "<https://");
+    Serial.print(server);
+    Serial.println("> and then click on the lock icon.\n");
+  };
+
+  // attempt to connect to Wifi network:
+  Serial.print("Attempting to connect to SSID: ");
+  Serial.println(ssid);
+  WiFi.begin(ssid, password);
+  while (WiFi.status() != WL_CONNECTED) {
+    Serial.print(".");
+    // wait 1 second for re-trying
+    delay(1000);
+  }
+
+  Serial.print("Connected to ");
+  Serial.println(ssid);
+
+  if (tofu_reset) {
+    Serial.println("Resetting trust fingerprint.");
+    if (!get_tofu()) {
+      Serial.println("Trust reset failed. Giving up");
+      return;
+    }
+    Serial.println("(New) Trust of First used configured. Rebooting in 3 seconds");
+    delay(3 * 1000);
+    ESP.restart();
+  };
+
+  Serial.println("Trying to connect to a server; using TOFU details from the eeprom");
+
+  if (doTOFU_Protected_Connection(fingerprint_tofu)) {
+    Serial.println("ALL OK");
+  }
+}
+
+bool get_tofu() {
+  Serial.println("\nStarting our insecure connection to server...");
+  client.setInsecure();  //skip verification
+
+  if (!client.connect(server, 443)) {
+    Serial.println("Connection failed!");
+    client.stop();
+    return false;
+  };
+
+  Serial.println("Connected to server. Extracting trust data.");
+
+  // Now extract the data of the certificate and show it to
+  // the user over the serial connection for optional
+  // verification.
+  const mbedtls_x509_crt *peer = client.getPeerCertificate();
+  char buf[1024];
+  int l = mbedtls_x509_crt_info(buf, sizeof(buf), "", peer);
+  if (l <= 0) {
+    Serial.println("Peer conversion to printable buffer failed");
+    client.stop();
+    return false;
+  };
+  Serial.println();
+  Serial.println(buf);
+
+  // Extract the fingerprint - and store this in our EEPROM
+  // to be used for future validation.
+
+  uint8_t fingerprint_remote[32];
+  if (!client.getFingerprintSHA256(fingerprint_remote)) {
+    Serial.println("Failed to get the fingerprint");
+    client.stop();
+    return false;
+  }
+  if ((32 != TOFU.writeBytes(0, fingerprint_remote, 32)) || (!TOFU.commit())) {
+    Serial.println("Could not write the fingerprint to the EEPROM");
+    client.stop();
+    return false;
+  };
+  TOFU.end();
+  client.stop();
+
+  Serial.print("TOFU pegged to fingerprint: SHA256=");
+  printSHA256(fingerprint_remote);
+
+  return true;
+};
+
+bool doTOFU_Protected_Connection(uint8_t *fingerprint_tofu) {
+
+  // As we're not using a (CA) certificate to check the
+  // connection; but the hash of the peer - we need to initially
+  // allow the connection to be set up without the CA check.
+  client.setInsecure();  //skip verification
+
+  if (!client.connect(server, 443)) {
+    Serial.println("Connection failed!");
+    client.stop();
+    return false;
+  };
+
+  // Now that we're connected - we can check that we have
+  // end to end trust - by comparing the fingerprint we (now)
+  // see (of the server certificate) to the one we have stored
+  // in our EEPROM as part of an earlier trust-on-first use.
+  uint8_t fingerprint_remote[32];
+  if (!client.getFingerprintSHA256(fingerprint_remote)) {
+    Serial.println("Failed to get the fingerprint of the server");
+    client.stop();
+    return false;
+  }
+  if (memcmp(fingerprint_remote, fingerprint_tofu, 32)) {
+    Serial.println("TOFU fingerprint not the same as the one from the server.");
+    Serial.print("TOFU  : SHA256=");
+    printSHA256(fingerprint_tofu);
+    Serial.print("Remote: SHA256=");
+    printSHA256(fingerprint_remote);
+    Serial.println("       : NOT identical -- Aborting!");
+    client.stop();
+    return false;
+  };
+
+  Serial.println("All well - you are talking to the same server as\n"
+                 "when you set up TOFU. So we can now do a GET.\n\n");
+
+  client.println("GET /a/check HTTP/1.0");
+  client.print("Host: ");
+  client.println(server);
+  client.println("Connection: close");
+  client.println();
+
+  bool inhdr = true;
+  while (client.connected()) {
+    String line = client.readStringUntil('\n');
+    Serial.println(line);
+    if (inhdr && line == "\r") {
+      inhdr = false;
+      Serial.println("-- headers received. Payload follows\n\n");
+    }
+  }
+  Serial.println("\n\n-- Payload ended.");
+  client.stop();
+  return true;
+}
+
+void loop() {}
diff --git a/libraries/NetworkClientSecure/examples/WiFiClientTrustOnFirstUse/ci.json b/libraries/NetworkClientSecure/examples/WiFiClientTrustOnFirstUse/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/NetworkClientSecure/examples/WiFiClientTrustOnFirstUse/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/NetworkClientSecure/keywords.txt b/libraries/NetworkClientSecure/keywords.txt
new file mode 100644
index 00000000000..7b62f1728dd
--- /dev/null
+++ b/libraries/NetworkClientSecure/keywords.txt
@@ -0,0 +1,36 @@
+#######################################
+# Syntax Coloring Map For WiFi
+#######################################
+
+#######################################
+# Library (KEYWORD3)
+#######################################
+
+NetworkClientSecure	KEYWORD3
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+NetworkClientSecure	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+connect	KEYWORD2
+write	KEYWORD2
+available	KEYWORD2
+config	KEYWORD2
+read	KEYWORD2
+flush	KEYWORD2
+stop	KEYWORD2
+connected	KEYWORD2
+setCACert	KEYWORD2
+setCertificate	KEYWORD2
+setPrivateKey	KEYWORD2
+setAlpnProtocols	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
diff --git a/libraries/NetworkClientSecure/library.properties b/libraries/NetworkClientSecure/library.properties
new file mode 100644
index 00000000000..455dea6a2bf
--- /dev/null
+++ b/libraries/NetworkClientSecure/library.properties
@@ -0,0 +1,9 @@
+name=NetworkClientSecure
+version=3.2.0
+author=Evandro Luis Copercini
+maintainer=Github Community
+sentence=Enables secure network connection (local and Internet) using the ESP32 built-in WiFi.
+paragraph=With this library you can make a TLS or SSL connection to a remote server.
+category=Communication
+url=
+architectures=esp32
diff --git a/libraries/NetworkClientSecure/src/NetworkClientSecure.cpp b/libraries/NetworkClientSecure/src/NetworkClientSecure.cpp
new file mode 100644
index 00000000000..87917e58b8f
--- /dev/null
+++ b/libraries/NetworkClientSecure/src/NetworkClientSecure.cpp
@@ -0,0 +1,455 @@
+/*
+  NetworkClientSecure.cpp - Client Secure class for ESP32
+  Copyright (c) 2016 Hristo Gochkov  All right reserved.
+  Additions Copyright (C) 2017 Evandro Luis Copercini.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include "NetworkClientSecure.h"
+#include "esp_crt_bundle.h"
+#include <lwip/sockets.h>
+#include <lwip/netdb.h>
+#include <errno.h>
+
+#undef connect
+#undef write
+#undef read
+
+NetworkClientSecure::NetworkClientSecure() {
+  _connected = false;
+  _timeout = 30000;  // Same default as ssl_client
+
+  sslclient.reset(new sslclient_context, [](struct sslclient_context *sslclient) {
+    stop_ssl_socket(sslclient);
+    delete sslclient;
+  });
+  ssl_init(sslclient.get());
+  sslclient->socket = -1;
+  sslclient->handshake_timeout = 120000;
+  _use_insecure = false;
+  _stillinPlainStart = false;
+  _ca_cert_free = false;
+  _cert_free = false;
+  _private_key_free = false;
+  _CA_cert = NULL;
+  _cert = NULL;
+  _private_key = NULL;
+  _pskIdent = NULL;
+  _psKey = NULL;
+  next = NULL;
+  _alpn_protos = NULL;
+  _use_ca_bundle = false;
+}
+
+NetworkClientSecure::NetworkClientSecure(int sock) {
+  _connected = false;
+  _timeout = 30000;  // Same default as ssl_client
+  _lastReadTimeout = 0;
+  _lastWriteTimeout = 0;
+
+  sslclient.reset(new sslclient_context, [](struct sslclient_context *sslclient) {
+    stop_ssl_socket(sslclient);
+    delete sslclient;
+  });
+  ssl_init(sslclient.get());
+  sslclient->socket = sock;
+  sslclient->handshake_timeout = 120000;
+
+  if (sock >= 0) {
+    _connected = true;
+  }
+
+  _use_insecure = false;
+  _stillinPlainStart = false;
+  _ca_cert_free = false;
+  _cert_free = false;
+  _private_key_free = false;
+  _CA_cert = NULL;
+  _cert = NULL;
+  _private_key = NULL;
+  _pskIdent = NULL;
+  _psKey = NULL;
+  next = NULL;
+  _alpn_protos = NULL;
+}
+
+NetworkClientSecure::~NetworkClientSecure() {
+  if (_ca_cert_free && _CA_cert) {
+    free((void *)_CA_cert);
+  }
+  if (_cert_free && _cert) {
+    free((void *)_cert);
+  }
+  if (_private_key_free && _private_key) {
+    free((void *)_private_key);
+  }
+}
+
+void NetworkClientSecure::stop() {
+  stop_ssl_socket(sslclient.get());
+
+  _connected = false;
+  sslclient->peek_buf = -1;
+  _lastReadTimeout = 0;
+  _lastWriteTimeout = 0;
+}
+
+int NetworkClientSecure::connect(IPAddress ip, uint16_t port) {
+  if (_pskIdent && _psKey) {
+    return connect(ip, port, _pskIdent, _psKey);
+  }
+  return connect(ip, port, _CA_cert, _cert, _private_key);
+}
+
+int NetworkClientSecure::connect(IPAddress ip, uint16_t port, int32_t timeout) {
+  _timeout = timeout;
+  return connect(ip, port);
+}
+
+int NetworkClientSecure::connect(const char *host, uint16_t port) {
+  if (_pskIdent && _psKey) {
+    return connect(host, port, _pskIdent, _psKey);
+  }
+  return connect(host, port, _CA_cert, _cert, _private_key);
+}
+
+int NetworkClientSecure::connect(const char *host, uint16_t port, int32_t timeout) {
+  _timeout = timeout;
+  return connect(host, port);
+}
+
+int NetworkClientSecure::connect(IPAddress ip, uint16_t port, const char *CA_cert, const char *cert, const char *private_key) {
+  return connect(ip, port, NULL, CA_cert, cert, private_key);
+}
+
+int NetworkClientSecure::connect(const char *host, uint16_t port, const char *CA_cert, const char *cert, const char *private_key) {
+  IPAddress address;
+  if (!Network.hostByName(host, address)) {
+    return 0;
+  }
+
+  return connect(address, port, host, CA_cert, cert, private_key);
+}
+
+int NetworkClientSecure::connect(IPAddress ip, uint16_t port, const char *host, const char *CA_cert, const char *cert, const char *private_key) {
+  int ret = start_ssl_client(sslclient.get(), ip, port, host, _timeout, CA_cert, _use_ca_bundle, cert, private_key, NULL, NULL, _use_insecure, _alpn_protos);
+
+  if (ret >= 0 && !_stillinPlainStart) {
+    ret = ssl_starttls_handshake(sslclient.get());
+  } else {
+    log_i("Actual TLS start postponed.");
+  }
+
+  sslclient->last_error = ret;
+
+  if (ret < 0) {
+    log_e("start_ssl_client: connect failed: %d", ret);
+    stop();
+    return 0;
+  }
+  _connected = true;
+  return 1;
+}
+
+int NetworkClientSecure::startTLS() {
+  int ret = 1;
+  if (_stillinPlainStart) {
+    log_i("startTLS: starting TLS/SSL on this dplain connection");
+    ret = ssl_starttls_handshake(sslclient.get());
+    if (ret < 0) {
+      log_e("startTLS: %d", ret);
+      stop();
+      return 0;
+    };
+    _stillinPlainStart = false;
+  } else {
+    log_i("startTLS: ignoring StartTLS - as we should be secure already");
+  }
+  return 1;
+}
+
+int NetworkClientSecure::connect(IPAddress ip, uint16_t port, const char *pskIdent, const char *psKey) {
+  return connect(ip.toString().c_str(), port, pskIdent, psKey);
+}
+
+int NetworkClientSecure::connect(const char *host, uint16_t port, const char *pskIdent, const char *psKey) {
+  log_v("start_ssl_client with PSK");
+
+  IPAddress address;
+  if (!Network.hostByName(host, address)) {
+    return 0;
+  }
+
+  int ret = start_ssl_client(sslclient.get(), address, port, host, _timeout, NULL, false, NULL, NULL, pskIdent, psKey, _use_insecure, _alpn_protos);
+  sslclient->last_error = ret;
+  if (ret < 0) {
+    log_e("start_ssl_client: connect failed %d", ret);
+    stop();
+    return 0;
+  }
+  _connected = true;
+  return 1;
+}
+
+int NetworkClientSecure::peek() {
+  if (sslclient->peek_buf >= 0) {
+    return sslclient->peek_buf;
+  }
+  sslclient->peek_buf = timedRead();
+  return sslclient->peek_buf;
+}
+
+size_t NetworkClientSecure::write(uint8_t data) {
+  return write(&data, 1);
+}
+
+int NetworkClientSecure::read() {
+  uint8_t data = -1;
+  int res = read(&data, 1);
+  return res < 0 ? res : data;
+}
+
+size_t NetworkClientSecure::write(const uint8_t *buf, size_t size) {
+  if (!_connected) {
+    return 0;
+  }
+
+  if (_stillinPlainStart) {
+    return send_net_data(sslclient.get(), buf, size);
+  }
+
+  if (_lastWriteTimeout != _timeout) {
+    struct timeval timeout_tv;
+    timeout_tv.tv_sec = _timeout / 1000;
+    timeout_tv.tv_usec = (_timeout % 1000) * 1000;
+    if (setSocketOption(SO_SNDTIMEO, (char *)&timeout_tv, sizeof(struct timeval)) >= 0) {
+      _lastWriteTimeout = _timeout;
+    }
+  }
+  int res = send_ssl_data(sslclient.get(), buf, size);
+  if (res < 0) {
+    log_e("Closing connection on failed write");
+    stop();
+    res = 0;
+  }
+  return res;
+}
+
+int NetworkClientSecure::read(uint8_t *buf, size_t size) {
+  if (_stillinPlainStart) {
+    return get_net_receive(sslclient.get(), buf, size);
+  }
+
+  if (_lastReadTimeout != _timeout) {
+    if (fd() >= 0) {
+      struct timeval timeout_tv;
+      timeout_tv.tv_sec = _timeout / 1000;
+      timeout_tv.tv_usec = (_timeout % 1000) * 1000;
+      if (setSocketOption(SO_RCVTIMEO, (char *)&timeout_tv, sizeof(struct timeval)) >= 0) {
+        _lastReadTimeout = _timeout;
+      }
+    }
+  }
+
+  int peeked = 0, res = -1;
+  int avail = available();
+  if ((!buf && size) || avail <= 0) {
+    return -1;
+  }
+  if (!size) {
+    return 0;
+  }
+  if (sslclient->peek_buf >= 0) {
+    buf[0] = sslclient->peek_buf;
+    sslclient->peek_buf = -1;
+    size--;
+    avail--;
+    if (!size || !avail) {
+      return 1;
+    }
+    buf++;
+    peeked = 1;
+  }
+  res = get_ssl_receive(sslclient.get(), buf, size);
+
+  if (res < 0) {
+    log_e("Closing connection on failed read");
+    stop();
+    return peeked ? peeked : res;
+  }
+  return res + peeked;
+}
+
+int NetworkClientSecure::available() {
+  if (_stillinPlainStart) {
+    return peek_net_receive(sslclient.get(), 0);
+  }
+
+  int peeked = (sslclient->peek_buf >= 0), res = -1;
+  if (!_connected) {
+    return peeked;
+  }
+  res = data_to_read(sslclient.get());
+
+  if (res < 0 && !_stillinPlainStart) {
+    if (res != MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY) {
+      log_e("Closing connection on failed available check");
+    }
+    stop();
+    return peeked;
+  }
+  return res + peeked;
+}
+
+uint8_t NetworkClientSecure::connected() {
+  uint8_t dummy = 0;
+  read(&dummy, 0);
+
+  return _connected;
+}
+
+void NetworkClientSecure::setInsecure() {
+  _CA_cert = NULL;
+  _cert = NULL;
+  _private_key = NULL;
+  _pskIdent = NULL;
+  _psKey = NULL;
+  _use_insecure = true;
+}
+
+void NetworkClientSecure::setCACert(const char *rootCA) {
+  if (_ca_cert_free && _CA_cert) {
+    free((void *)_CA_cert);
+    _ca_cert_free = false;
+  }
+  _CA_cert = rootCA;
+  _use_insecure = false;
+}
+
+void NetworkClientSecure::setCACertBundle(const uint8_t *bundle, size_t size) {
+  if (bundle != NULL && size > 0) {
+    esp_crt_bundle_set(bundle, size);
+    attach_ssl_certificate_bundle(sslclient.get(), true);
+    _use_ca_bundle = true;
+  } else {
+    esp_crt_bundle_detach(NULL);
+    attach_ssl_certificate_bundle(sslclient.get(), false);
+    _use_ca_bundle = false;
+  }
+}
+
+void NetworkClientSecure::setCertificate(const char *client_ca) {
+  if (_cert_free && _cert) {
+    free((void *)_cert);
+    _cert_free = false;
+  }
+  _cert = client_ca;
+}
+
+void NetworkClientSecure::setPrivateKey(const char *private_key) {
+  if (_private_key_free && _private_key) {
+    free((void *)_private_key);
+    _private_key_free = false;
+  }
+  _private_key = private_key;
+}
+
+void NetworkClientSecure::setPreSharedKey(const char *pskIdent, const char *psKey) {
+  _pskIdent = pskIdent;
+  _psKey = psKey;
+}
+
+bool NetworkClientSecure::verify(const char *fp, const char *domain_name) {
+  if (!sslclient) {
+    return false;
+  }
+
+  return verify_ssl_fingerprint(sslclient.get(), fp, domain_name);
+}
+
+char *NetworkClientSecure::_streamLoad(Stream &stream, size_t size) {
+  char *dest = (char *)malloc(size + 1);
+  if (!dest) {
+    return nullptr;
+  }
+  if (size != stream.readBytes(dest, size)) {
+    free(dest);
+    dest = nullptr;
+    return nullptr;
+  }
+  dest[size] = '\0';
+  return dest;
+}
+
+bool NetworkClientSecure::loadCACert(Stream &stream, size_t size) {
+  if (_CA_cert != NULL) {
+    free(const_cast<char *>(_CA_cert));
+  }
+  char *dest = _streamLoad(stream, size);
+  bool ret = false;
+  if (dest) {
+    setCACert(dest);
+    _ca_cert_free = true;
+    ret = true;
+  }
+  return ret;
+}
+
+bool NetworkClientSecure::loadCertificate(Stream &stream, size_t size) {
+  if (_cert != NULL) {
+    free(const_cast<char *>(_cert));
+  }
+  char *dest = _streamLoad(stream, size);
+  bool ret = false;
+  if (dest) {
+    setCertificate(dest);
+    _cert_free = true;
+    ret = true;
+  }
+  return ret;
+}
+
+bool NetworkClientSecure::loadPrivateKey(Stream &stream, size_t size) {
+  if (_private_key != NULL) {
+    free(const_cast<char *>(_private_key));
+  }
+  char *dest = _streamLoad(stream, size);
+  bool ret = false;
+  if (dest) {
+    setPrivateKey(dest);
+    _private_key_free = true;
+    ret = true;
+  }
+  return ret;
+}
+
+int NetworkClientSecure::lastError(char *buf, const size_t size) {
+  int lastError = sslclient->last_error;
+  mbedtls_strerror(lastError, buf, size);
+  return lastError;
+}
+
+void NetworkClientSecure::setHandshakeTimeout(unsigned long handshake_timeout) {
+  sslclient->handshake_timeout = handshake_timeout * 1000;
+}
+
+void NetworkClientSecure::setAlpnProtocols(const char **alpn_protos) {
+  _alpn_protos = alpn_protos;
+}
+
+int NetworkClientSecure::fd() const {
+  return sslclient->socket;
+}
diff --git a/libraries/NetworkClientSecure/src/NetworkClientSecure.h b/libraries/NetworkClientSecure/src/NetworkClientSecure.h
new file mode 100644
index 00000000000..46f725d5633
--- /dev/null
+++ b/libraries/NetworkClientSecure/src/NetworkClientSecure.h
@@ -0,0 +1,131 @@
+/*
+  NetworkClientSecure.h - Base class that provides Client SSL to ESP32
+  Copyright (c) 2011 Adrian McEwen.  All right reserved.
+  Additions Copyright (C) 2017 Evandro Luis Copercini.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef NetworkClientSecure_h
+#define NetworkClientSecure_h
+#include "Arduino.h"
+#include "IPAddress.h"
+#include "Network.h"
+#include "ssl_client.h"
+#include <memory>
+
+class NetworkClientSecure : public NetworkClient {
+protected:
+  std::shared_ptr<sslclient_context> sslclient;
+
+  bool _use_insecure;
+  bool _stillinPlainStart;
+  bool _ca_cert_free;
+  bool _cert_free;
+  bool _private_key_free;
+  const char *_CA_cert;
+  const char *_cert;
+  const char *_private_key;
+  const char *_pskIdent;  // identity for PSK cipher suites
+  const char *_psKey;     // key in hex for PSK cipher suites
+  const char **_alpn_protos;
+  bool _use_ca_bundle;
+
+public:
+  NetworkClientSecure *next;
+  NetworkClientSecure();
+  NetworkClientSecure(int socket);
+  ~NetworkClientSecure();
+  int connect(IPAddress ip, uint16_t port);
+  int connect(IPAddress ip, uint16_t port, int32_t timeout);
+  int connect(const char *host, uint16_t port);
+  int connect(const char *host, uint16_t port, int32_t timeout);
+  int connect(IPAddress ip, uint16_t port, const char *rootCABuff, const char *cli_cert, const char *cli_key);
+  int connect(const char *host, uint16_t port, const char *rootCABuff, const char *cli_cert, const char *cli_key);
+  int connect(IPAddress ip, uint16_t port, const char *pskIdent, const char *psKey);
+  int connect(const char *host, uint16_t port, const char *pskIdent, const char *psKey);
+  int connect(IPAddress ip, uint16_t port, const char *host, const char *CA_cert, const char *cert, const char *private_key);
+  int peek();
+  size_t write(uint8_t data);
+  size_t write(const uint8_t *buf, size_t size);
+  int available();
+  int read();
+  int read(uint8_t *buf, size_t size);
+  void flush() {}
+  void stop();
+  uint8_t connected();
+  int lastError(char *buf, const size_t size);
+  void setInsecure();                                             // Don't validate the chain, just accept whatever is given.  VERY INSECURE!
+  void setPreSharedKey(const char *pskIdent, const char *psKey);  // psKey in Hex
+  void setCACert(const char *rootCA);
+  void setCertificate(const char *client_ca);
+  void setPrivateKey(const char *private_key);
+  bool loadCACert(Stream &stream, size_t size);
+  void setCACertBundle(const uint8_t *bundle, size_t size);
+  bool loadCertificate(Stream &stream, size_t size);
+  bool loadPrivateKey(Stream &stream, size_t size);
+  bool verify(const char *fingerprint, const char *domain_name);
+  void setHandshakeTimeout(unsigned long handshake_timeout);
+  void setAlpnProtocols(const char **alpn_protos);
+
+  // Certain protocols start in plain-text; and then have the client
+  // give some STARTSSL command to `upgrade' the connection to TLS
+  // or SSL. Setting PlainStart to true (the default is false) enables
+  // this. It is up to the application code to then call 'startTLS()'
+  // at the right point to initialize the SSL or TLS upgrade.
+
+  void setPlainStart() {
+    _stillinPlainStart = true;
+  };
+  bool stillInPlainStart() {
+    return _stillinPlainStart;
+  };
+  int startTLS();
+
+  const mbedtls_x509_crt *getPeerCertificate() {
+    return mbedtls_ssl_get_peer_cert(&sslclient->ssl_ctx);
+  };
+  bool getFingerprintSHA256(uint8_t sha256_result[32]) {
+    return get_peer_fingerprint(sslclient.get(), sha256_result);
+  };
+  int fd() const;
+
+  operator bool() {
+    return connected();
+  }
+
+  bool operator==(const bool value) {
+    return bool() == value;
+  }
+  bool operator!=(const bool value) {
+    return bool() != value;
+  }
+  bool operator==(const NetworkClientSecure &);
+  bool operator!=(const NetworkClientSecure &rhs) {
+    return !this->operator==(rhs);
+  };
+
+  int socket() {
+    return sslclient->socket = -1;
+  }
+
+private:
+  char *_streamLoad(Stream &stream, size_t size);
+
+  //friend class NetworkServer;
+  using Print::write;
+};
+
+#endif /* _WIFICLIENT_H_ */
diff --git a/libraries/NetworkClientSecure/src/WiFiClientSecure.h b/libraries/NetworkClientSecure/src/WiFiClientSecure.h
new file mode 100644
index 00000000000..56e7f28aa52
--- /dev/null
+++ b/libraries/NetworkClientSecure/src/WiFiClientSecure.h
@@ -0,0 +1,3 @@
+#pragma once
+#include "NetworkClientSecure.h"
+typedef NetworkClientSecure WiFiClientSecure;
diff --git a/libraries/NetworkClientSecure/src/ssl_client.cpp b/libraries/NetworkClientSecure/src/ssl_client.cpp
new file mode 100644
index 00000000000..19f75673133
--- /dev/null
+++ b/libraries/NetworkClientSecure/src/ssl_client.cpp
@@ -0,0 +1,637 @@
+/* Provide SSL/TLS functions to ESP32 with Arduino IDE
+*
+* Adapted from the ssl_client1 example of mbedtls.
+*
+* Original Copyright (C) 2006-2015, ARM Limited, All Rights Reserved, Apache 2.0 License.
+* Additions Copyright (C) 2017 Evandro Luis Copercini, Apache 2.0 License.
+*/
+
+#include "Arduino.h"
+#include <esp32-hal-log.h>
+#include <lwip/err.h>
+#include <lwip/sockets.h>
+#include <lwip/sys.h>
+#include <lwip/netdb.h>
+#include <mbedtls/sha256.h>
+#include <mbedtls/oid.h>
+#include <algorithm>
+#include <string>
+#include "ssl_client.h"
+#include "esp_crt_bundle.h"
+
+#if !defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) && !defined(MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED)
+#warning \
+  "Please call `idf.py menuconfig` then go to Component config -> mbedTLS -> TLS Key Exchange Methods -> Enable pre-shared-key ciphersuites and then check `Enable PSK based ciphersuite modes`. Save and Quit."
+#else
+
+const char *pers = "esp32-tls";
+
+static int _handle_error(int err, const char *function, int line) {
+  if (err == MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY) {
+    return err;
+  }
+#ifdef MBEDTLS_ERROR_C
+  char error_buf[100];
+  mbedtls_strerror(err, error_buf, 100);
+  log_e("[%s():%d]: (%d) %s", function, line, err, error_buf);
+#else
+  log_e("[%s():%d]: code %d", function, line, err);
+#endif
+  return err;
+}
+
+#define handle_error(e) _handle_error(e, __FUNCTION__, __LINE__)
+
+void ssl_init(sslclient_context *ssl_client) {
+  // reset embedded pointers to zero
+  memset(ssl_client, 0, sizeof(sslclient_context));
+  mbedtls_ssl_init(&ssl_client->ssl_ctx);
+  mbedtls_ssl_config_init(&ssl_client->ssl_conf);
+  mbedtls_ctr_drbg_init(&ssl_client->drbg_ctx);
+  ssl_client->peek_buf = -1;
+}
+
+void attach_ssl_certificate_bundle(sslclient_context *ssl_client, bool att) {
+  if (att) {
+    ssl_client->bundle_attach_cb = &esp_crt_bundle_attach;
+  } else {
+    ssl_client->bundle_attach_cb = NULL;
+  }
+}
+
+int start_ssl_client(
+  sslclient_context *ssl_client, const IPAddress &ip, uint32_t port, const char *hostname, int timeout, const char *rootCABuff, bool useRootCABundle,
+  const char *cli_cert, const char *cli_key, const char *pskIdent, const char *psKey, bool insecure, const char **alpn_protos
+) {
+  int ret;
+  int enable = 1;
+  log_v("Free internal heap before TLS %u", ESP.getFreeHeap());
+
+  if (rootCABuff == NULL && pskIdent == NULL && psKey == NULL && !insecure && !useRootCABundle) {
+    return -1;
+  }
+
+  int domain = ip.type() == IPv6 ? AF_INET6 : AF_INET;
+  log_v("Starting socket (domain %d)", domain);
+  ssl_client->socket = -1;
+
+  ssl_client->socket = lwip_socket(domain, SOCK_STREAM, IPPROTO_TCP);
+  if (ssl_client->socket < 0) {
+    log_e("ERROR opening socket");
+    return ssl_client->socket;
+  }
+
+  fcntl(ssl_client->socket, F_SETFL, fcntl(ssl_client->socket, F_GETFL, 0) | O_NONBLOCK);
+  struct sockaddr_storage serv_addr = {};
+#if CONFIG_LWIP_IPV6
+  if (domain == AF_INET6) {
+    struct sockaddr_in6 *tmpaddr = (struct sockaddr_in6 *)&serv_addr;
+    tmpaddr->sin6_family = AF_INET6;
+    for (int index = 0; index < 16; index++) {
+      tmpaddr->sin6_addr.s6_addr[index] = ip[index];
+    }
+    tmpaddr->sin6_port = htons(port);
+    tmpaddr->sin6_scope_id = ip.zone();
+  } else {
+#endif
+    struct sockaddr_in *tmpaddr = (struct sockaddr_in *)&serv_addr;
+    tmpaddr->sin_family = AF_INET;
+    tmpaddr->sin_addr.s_addr = ip;
+    tmpaddr->sin_port = htons(port);
+#if CONFIG_LWIP_IPV6
+  }
+#endif
+
+  if (timeout <= 0) {
+    timeout = 30000;  // Milli seconds.
+  }
+
+  ssl_client->socket_timeout = timeout;
+
+  fd_set fdset;
+  struct timeval tv;
+  FD_ZERO(&fdset);
+  FD_SET(ssl_client->socket, &fdset);
+  tv.tv_sec = timeout / 1000;
+  tv.tv_usec = (timeout % 1000) * 1000;
+
+  int res = lwip_connect(ssl_client->socket, (struct sockaddr *)&serv_addr, sizeof(serv_addr));
+  if (res < 0 && errno != EINPROGRESS) {
+    log_e("connect on fd %d, errno: %d, \"%s\"", ssl_client->socket, errno, strerror(errno));
+    lwip_close(ssl_client->socket);
+    ssl_client->socket = -1;
+    return -1;
+  }
+
+  res = select(ssl_client->socket + 1, nullptr, &fdset, nullptr, timeout < 0 ? nullptr : &tv);
+  if (res < 0) {
+    log_e("select on fd %d, errno: %d, \"%s\"", ssl_client->socket, errno, strerror(errno));
+    lwip_close(ssl_client->socket);
+    ssl_client->socket = -1;
+    return -1;
+  } else if (res == 0) {
+    log_i("select returned due to timeout %d ms for fd %d", timeout, ssl_client->socket);
+    lwip_close(ssl_client->socket);
+    ssl_client->socket = -1;
+    return -1;
+  } else {
+    int sockerr;
+    socklen_t len = (socklen_t)sizeof(int);
+    res = getsockopt(ssl_client->socket, SOL_SOCKET, SO_ERROR, &sockerr, &len);
+
+    if (res < 0) {
+      log_e("getsockopt on fd %d, errno: %d, \"%s\"", ssl_client->socket, errno, strerror(errno));
+      lwip_close(ssl_client->socket);
+      ssl_client->socket = -1;
+      return -1;
+    }
+
+    if (sockerr != 0) {
+      log_e("socket error on fd %d, errno: %d, \"%s\"", ssl_client->socket, sockerr, strerror(sockerr));
+      lwip_close(ssl_client->socket);
+      ssl_client->socket = -1;
+      return -1;
+    }
+  }
+
+#define ROE(x, msg)                                   \
+  {                                                   \
+    if (((x) < 0)) {                                  \
+      log_e("LWIP Socket config of " msg " failed."); \
+      return -1;                                      \
+    }                                                 \
+  }
+  ROE(lwip_setsockopt(ssl_client->socket, SOL_SOCKET, SO_RCVTIMEO, &tv, sizeof(tv)), "SO_RCVTIMEO");
+  ROE(lwip_setsockopt(ssl_client->socket, SOL_SOCKET, SO_SNDTIMEO, &tv, sizeof(tv)), "SO_SNDTIMEO");
+
+  ROE(lwip_setsockopt(ssl_client->socket, IPPROTO_TCP, TCP_NODELAY, &enable, sizeof(enable)), "TCP_NODELAY");
+  ROE(lwip_setsockopt(ssl_client->socket, SOL_SOCKET, SO_KEEPALIVE, &enable, sizeof(enable)), "SO_KEEPALIVE");
+
+  log_v("Seeding the random number generator");
+  mbedtls_entropy_init(&ssl_client->entropy_ctx);
+
+  ret = mbedtls_ctr_drbg_seed(&ssl_client->drbg_ctx, mbedtls_entropy_func, &ssl_client->entropy_ctx, (const unsigned char *)pers, strlen(pers));
+  if (ret < 0) {
+    return handle_error(ret);
+  }
+
+  log_v("Setting up the SSL/TLS structure...");
+
+  if ((ret = mbedtls_ssl_config_defaults(&ssl_client->ssl_conf, MBEDTLS_SSL_IS_CLIENT, MBEDTLS_SSL_TRANSPORT_STREAM, MBEDTLS_SSL_PRESET_DEFAULT)) != 0) {
+    return handle_error(ret);
+  }
+
+  if (alpn_protos != NULL) {
+    log_v("Setting ALPN protocols");
+    if ((ret = mbedtls_ssl_conf_alpn_protocols(&ssl_client->ssl_conf, alpn_protos)) != 0) {
+      return handle_error(ret);
+    }
+  }
+
+  // MBEDTLS_SSL_VERIFY_REQUIRED if a CA certificate is defined on Arduino IDE and
+  // MBEDTLS_SSL_VERIFY_NONE if not.
+
+  if (insecure) {
+    mbedtls_ssl_conf_authmode(&ssl_client->ssl_conf, MBEDTLS_SSL_VERIFY_NONE);
+    log_d("WARNING: Skipping SSL Verification. INSECURE!");
+  } else if (rootCABuff != NULL) {
+    log_v("Loading CA cert");
+    mbedtls_x509_crt_init(&ssl_client->ca_cert);
+    mbedtls_ssl_conf_authmode(&ssl_client->ssl_conf, MBEDTLS_SSL_VERIFY_REQUIRED);
+    ret = mbedtls_x509_crt_parse(&ssl_client->ca_cert, (const unsigned char *)rootCABuff, strlen(rootCABuff) + 1);
+    mbedtls_ssl_conf_ca_chain(&ssl_client->ssl_conf, &ssl_client->ca_cert, NULL);
+    //mbedtls_ssl_conf_verify(&ssl_client->ssl_ctx, my_verify, NULL );
+    if (ret < 0) {
+      // free the ca_cert in the case parse failed, otherwise, the old ca_cert still in the heap memory, that lead to "out of memory" crash.
+      mbedtls_x509_crt_free(&ssl_client->ca_cert);
+      return handle_error(ret);
+    }
+  } else if (useRootCABundle) {
+    if (ssl_client->bundle_attach_cb != NULL) {
+      log_v("Attaching root CA cert bundle");
+      ret = ssl_client->bundle_attach_cb(&ssl_client->ssl_conf);
+      if (ret < 0) {
+        return handle_error(ret);
+      }
+    } else {
+      log_e("useRootCABundle is set, but attach_ssl_certificate_bundle(ssl, true); was not called!");
+    }
+  } else if (pskIdent != NULL && psKey != NULL) {
+    log_v("Setting up PSK");
+    // convert PSK from hex to binary
+    if ((strlen(psKey) & 1) != 0 || strlen(psKey) > 2 * MBEDTLS_PSK_MAX_LEN) {
+      log_e("pre-shared key not valid hex or too long");
+      return -1;
+    }
+    unsigned char psk[MBEDTLS_PSK_MAX_LEN];
+    size_t psk_len = strlen(psKey) / 2;
+    for (int j = 0; j < strlen(psKey); j += 2) {
+      char c = psKey[j];
+      if (c >= '0' && c <= '9') {
+        c -= '0';
+      } else if (c >= 'A' && c <= 'F') {
+        c -= 'A' - 10;
+      } else if (c >= 'a' && c <= 'f') {
+        c -= 'a' - 10;
+      } else {
+        return -1;
+      }
+      psk[j / 2] = c << 4;
+      c = psKey[j + 1];
+      if (c >= '0' && c <= '9') {
+        c -= '0';
+      } else if (c >= 'A' && c <= 'F') {
+        c -= 'A' - 10;
+      } else if (c >= 'a' && c <= 'f') {
+        c -= 'a' - 10;
+      } else {
+        return -1;
+      }
+      psk[j / 2] |= c;
+    }
+    // set mbedtls config
+    ret = mbedtls_ssl_conf_psk(&ssl_client->ssl_conf, psk, psk_len, (const unsigned char *)pskIdent, strlen(pskIdent));
+    if (ret != 0) {
+      log_e("mbedtls_ssl_conf_psk returned %d", ret);
+      return handle_error(ret);
+    }
+  } else {
+    return -1;
+  }
+
+  // Note - this check for BOTH key and cert is relied on
+  // later during cleanup.
+
+  if (!insecure && cli_cert != NULL && cli_key != NULL) {
+    mbedtls_x509_crt_init(&ssl_client->client_cert);
+    mbedtls_pk_init(&ssl_client->client_key);
+
+    log_v("Loading CRT cert");
+
+    ret = mbedtls_x509_crt_parse(&ssl_client->client_cert, (const unsigned char *)cli_cert, strlen(cli_cert) + 1);
+    if (ret < 0) {
+      // free the client_cert in the case parse failed, otherwise, the old client_cert still in the heap memory, that lead to "out of memory" crash.
+      mbedtls_x509_crt_free(&ssl_client->client_cert);
+      return handle_error(ret);
+    }
+
+    log_v("Loading private key");
+    mbedtls_ctr_drbg_context ctr_drbg;
+    mbedtls_ctr_drbg_init(&ctr_drbg);
+    ret = mbedtls_pk_parse_key(&ssl_client->client_key, (const unsigned char *)cli_key, strlen(cli_key) + 1, NULL, 0, mbedtls_ctr_drbg_random, &ctr_drbg);
+    mbedtls_ctr_drbg_free(&ctr_drbg);
+
+    if (ret != 0) {
+      mbedtls_x509_crt_free(&ssl_client->client_cert);  // cert+key are free'd in pair
+      return handle_error(ret);
+    }
+
+    mbedtls_ssl_conf_own_cert(&ssl_client->ssl_conf, &ssl_client->client_cert, &ssl_client->client_key);
+  }
+
+  log_v("Setting hostname for TLS session...");
+
+  // Hostname set here should match CN in server certificate
+  if ((ret = mbedtls_ssl_set_hostname(&ssl_client->ssl_ctx, hostname != NULL ? hostname : ip.toString().c_str())) != 0) {
+    return handle_error(ret);
+  }
+
+  mbedtls_ssl_conf_rng(&ssl_client->ssl_conf, mbedtls_ctr_drbg_random, &ssl_client->drbg_ctx);
+
+  if ((ret = mbedtls_ssl_setup(&ssl_client->ssl_ctx, &ssl_client->ssl_conf)) != 0) {
+    return handle_error(ret);
+  }
+
+  mbedtls_ssl_set_bio(&ssl_client->ssl_ctx, &ssl_client->socket, mbedtls_net_send, mbedtls_net_recv, NULL);
+  return ssl_client->socket;
+}
+
+int ssl_starttls_handshake(sslclient_context *ssl_client) {
+  char buf[512];
+  int ret, flags;
+
+  log_v("Performing the SSL/TLS handshake...");
+  unsigned long handshake_start_time = millis();
+  while ((ret = mbedtls_ssl_handshake(&ssl_client->ssl_ctx)) != 0) {
+    if (ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE) {
+      return handle_error(ret);
+    }
+    if ((millis() - handshake_start_time) > ssl_client->handshake_timeout) {
+      return -1;
+    }
+    vTaskDelay(2);  //2 ticks
+  }
+
+  if (ssl_client->client_cert.version) {
+    log_d("Protocol is %s Ciphersuite is %s", mbedtls_ssl_get_version(&ssl_client->ssl_ctx), mbedtls_ssl_get_ciphersuite(&ssl_client->ssl_ctx));
+    if ((ret = mbedtls_ssl_get_record_expansion(&ssl_client->ssl_ctx)) >= 0) {
+      log_d("Record expansion is %d", ret);
+    } else {
+      log_w("Record expansion is unknown (compression)");
+    }
+  }
+
+  log_v("Verifying peer X.509 certificate...");
+
+  if ((flags = mbedtls_ssl_get_verify_result(&ssl_client->ssl_ctx)) != 0) {
+    memset(buf, 0, sizeof(buf));
+    mbedtls_x509_crt_verify_info(buf, sizeof(buf), "  ! ", flags);
+    log_e("Failed to verify peer certificate! verification info: %s", buf);
+    return handle_error(ret);
+  } else {
+    log_v("Certificate verified.");
+  }
+
+  if (ssl_client->ca_cert.version) {
+    mbedtls_x509_crt_free(&ssl_client->ca_cert);
+  }
+
+  // We know that we always have a client cert/key pair -- and we
+  // cannot look into the private client_key pk struct for newer
+  // versions of mbedtls. So rely on a public field of the cert
+  // and infer that there is a key too.
+  if (ssl_client->client_cert.version) {
+    mbedtls_x509_crt_free(&ssl_client->client_cert);
+    mbedtls_pk_free(&ssl_client->client_key);
+  }
+
+  log_v("Free internal heap after TLS %u", ESP.getFreeHeap());
+
+  return ssl_client->socket;
+}
+
+void stop_ssl_socket(sslclient_context *ssl_client) {
+  log_v("Cleaning SSL connection.");
+
+  if (ssl_client->socket >= 0) {
+    lwip_close(ssl_client->socket);
+    ssl_client->socket = -1;
+  }
+
+  // avoid memory leak if ssl connection attempt failed
+  // if (ssl_client->ssl_conf.ca_chain != NULL) {
+  mbedtls_x509_crt_free(&ssl_client->ca_cert);
+  // }
+  // if (ssl_client->ssl_conf.key_cert != NULL) {
+  mbedtls_x509_crt_free(&ssl_client->client_cert);
+  mbedtls_pk_free(&ssl_client->client_key);
+  // }
+  mbedtls_ssl_free(&ssl_client->ssl_ctx);
+  mbedtls_ssl_config_free(&ssl_client->ssl_conf);
+  mbedtls_ctr_drbg_free(&ssl_client->drbg_ctx);
+  mbedtls_entropy_free(&ssl_client->entropy_ctx);
+
+  // save only interesting fields
+  int handshake_timeout = ssl_client->handshake_timeout;
+  int socket_timeout = ssl_client->socket_timeout;
+  int last_err = ssl_client->last_error;
+
+  // reset embedded pointers to zero
+  memset(ssl_client, 0, sizeof(sslclient_context));
+
+  ssl_client->handshake_timeout = handshake_timeout;
+  ssl_client->socket_timeout = socket_timeout;
+  ssl_client->last_error = last_err;
+  ssl_client->peek_buf = -1;
+}
+
+int data_to_read(sslclient_context *ssl_client) {
+  int ret, res;
+  ret = mbedtls_ssl_read(&ssl_client->ssl_ctx, NULL, 0);
+  //log_e("RET: %i",ret);   //for low level debug
+  res = mbedtls_ssl_get_bytes_avail(&ssl_client->ssl_ctx);
+  //log_e("RES: %i",res);    //for low level debug
+  if (ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE && ret < 0) {
+    return handle_error(ret);
+  }
+
+  return res;
+}
+
+int send_ssl_data(sslclient_context *ssl_client, const uint8_t *data, size_t len) {
+  unsigned long write_start_time = millis();
+  int ret = -1;
+
+  while ((ret = mbedtls_ssl_write(&ssl_client->ssl_ctx, data, len)) <= 0) {
+    if ((millis() - write_start_time) > ssl_client->socket_timeout) {
+      log_v("SSL write timed out.");
+      return -1;
+    }
+
+    if (ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE && ret < 0) {
+      log_v("Handling error %d", ret);  //for low level debug
+      return handle_error(ret);
+    }
+
+    //wait for space to become available
+    vTaskDelay(2);
+  }
+
+  return ret;
+}
+
+// Some protocols, such as SMTP, XMPP, MySQL/Posgress and various others
+// do a 'in-line' upgrade from plaintext to SSL or TLS (usually with some
+// sort of 'STARTTLS' textual command from client to sever). For this
+// we need to have access to the 'raw' socket; i.e. without TLS/SSL state
+// handling before the handshake starts; but after setting up the TLS
+// connection.
+//
+int peek_net_receive(sslclient_context *ssl_client, int timeout) {
+#if MBEDTLS_FIXED_LINKING_NET_POLL
+  int ret = mbedtls_net_poll((mbedtls_net_context *)ssl_client, MBEDTLS_NET_POLL_READ, timeout);
+  ret == MBEDTLS_NET_POLL_READ ? 1 : ret;
+#else
+  // We should be using mbedtls_net_poll(); which is part of mbedtls and
+  // included in the EspressifSDK. Unfortunately - it did not make it into
+  // the statically linked library file. So, for now, we replace it by
+  // substancially similar code.
+  //
+  struct timeval tv = {.tv_sec = timeout / 1000, .tv_usec = (timeout % 1000) * 1000};
+
+  fd_set fdset;
+  FD_SET(ssl_client->socket, &fdset);
+
+  int ret = select(ssl_client->socket + 1, &fdset, nullptr, nullptr, timeout < 0 ? nullptr : &tv);
+  if (ret < 0) {
+    log_e("select on read fd %d, errno: %d, \"%s\"", ssl_client->socket, errno, strerror(errno));
+    lwip_close(ssl_client->socket);
+    ssl_client->socket = -1;
+    return -1;
+  };
+#endif
+  return ret;
+};
+
+int get_net_receive(sslclient_context *ssl_client, uint8_t *data, int length) {
+  int ret = peek_net_receive(ssl_client, ssl_client->socket_timeout);
+  if (ret > 0) {
+    ret = mbedtls_net_recv(ssl_client, data, length);
+  }
+
+  // log_v( "%d bytes NET read of %d", ret, length);   //for low level debug
+  return ret;
+}
+
+int send_net_data(sslclient_context *ssl_client, const uint8_t *data, size_t len) {
+  int ret = mbedtls_net_send(ssl_client, data, len);
+  // log_v("Net sending %d btes->ret %d", len, ret); //for low level debug
+  return ret;
+}
+
+int get_ssl_receive(sslclient_context *ssl_client, uint8_t *data, int length) {
+  int ret = mbedtls_ssl_read(&ssl_client->ssl_ctx, data, length);
+  // log_v( "%d bytes SSL read", ret);   //for low level debug
+  return ret;
+}
+
+static bool parseHexNibble(char pb, uint8_t *res) {
+  if (pb >= '0' && pb <= '9') {
+    *res = (uint8_t)(pb - '0');
+    return true;
+  } else if (pb >= 'a' && pb <= 'f') {
+    *res = (uint8_t)(pb - 'a' + 10);
+    return true;
+  } else if (pb >= 'A' && pb <= 'F') {
+    *res = (uint8_t)(pb - 'A' + 10);
+    return true;
+  }
+  return false;
+}
+
+// Compare a name from certificate and domain name, return true if they match
+static bool matchName(const std::string &name, const std::string &domainName) {
+  size_t wildcardPos = name.find('*');
+  if (wildcardPos == std::string::npos) {
+    // Not a wildcard, expect an exact match
+    return name == domainName;
+  }
+
+  size_t firstDotPos = name.find('.');
+  if (wildcardPos > firstDotPos) {
+    // Wildcard is not part of leftmost component of domain name
+    // Do not attempt to match (rfc6125 6.4.3.1)
+    return false;
+  }
+  if (wildcardPos != 0 || firstDotPos != 1) {
+    // Matching of wildcards such as baz*.example.com and b*z.example.com
+    // is optional. Maybe implement this in the future?
+    return false;
+  }
+  size_t domainNameFirstDotPos = domainName.find('.');
+  if (domainNameFirstDotPos == std::string::npos) {
+    return false;
+  }
+  return domainName.substr(domainNameFirstDotPos) == name.substr(firstDotPos);
+}
+
+// Verifies certificate provided by the peer to match specified SHA256 fingerprint
+bool verify_ssl_fingerprint(sslclient_context *ssl_client, const char *fp, const char *domain_name) {
+  // Convert hex string to byte array
+  uint8_t fingerprint_local[32];
+  int len = strlen(fp);
+  int pos = 0;
+  for (size_t i = 0; i < sizeof(fingerprint_local); ++i) {
+    while (pos < len && ((fp[pos] == ' ') || (fp[pos] == ':'))) {
+      ++pos;
+    }
+    if (pos > len - 2) {
+      log_d("pos:%d len:%d fingerprint too short", pos, len);
+      return false;
+    }
+    uint8_t high, low;
+    if (!parseHexNibble(fp[pos], &high) || !parseHexNibble(fp[pos + 1], &low)) {
+      log_d("pos:%d len:%d invalid hex sequence: %c%c", pos, len, fp[pos], fp[pos + 1]);
+      return false;
+    }
+    pos += 2;
+    fingerprint_local[i] = low | (high << 4);
+  }
+
+  // Calculate certificate's SHA256 fingerprint
+  uint8_t fingerprint_remote[32];
+  if (!get_peer_fingerprint(ssl_client, fingerprint_remote)) {
+    return false;
+  }
+
+  // Check if fingerprints match
+  if (memcmp(fingerprint_local, fingerprint_remote, 32)) {
+    log_d("fingerprint doesn't match");
+    return false;
+  }
+
+  // Additionally check if certificate has domain name if provided
+  if (domain_name) {
+    return verify_ssl_dn(ssl_client, domain_name);
+  } else {
+    return true;
+  }
+}
+
+bool get_peer_fingerprint(sslclient_context *ssl_client, uint8_t sha256[32]) {
+  if (!ssl_client) {
+    log_d("Invalid ssl_client pointer");
+    return false;
+  };
+
+  const mbedtls_x509_crt *crt = mbedtls_ssl_get_peer_cert(&ssl_client->ssl_ctx);
+  if (!crt) {
+    log_d("Failed to get peer cert.");
+    return false;
+  };
+
+  mbedtls_sha256_context sha256_ctx;
+  mbedtls_sha256_init(&sha256_ctx);
+  mbedtls_sha256_starts(&sha256_ctx, false);
+  mbedtls_sha256_update(&sha256_ctx, crt->raw.p, crt->raw.len);
+  mbedtls_sha256_finish(&sha256_ctx, sha256);
+
+  return true;
+}
+
+// Checks if peer certificate has specified domain in CN or SANs
+bool verify_ssl_dn(sslclient_context *ssl_client, const char *domain_name) {
+  log_d("domain name: '%s'", (domain_name) ? domain_name : "(null)");
+  std::string domain_name_str(domain_name);
+  std::transform(domain_name_str.begin(), domain_name_str.end(), domain_name_str.begin(), ::tolower);
+
+  // Get certificate provided by the peer
+  const mbedtls_x509_crt *crt = mbedtls_ssl_get_peer_cert(&ssl_client->ssl_ctx);
+
+  // Check for domain name in SANs
+  const mbedtls_x509_sequence *san = &crt->subject_alt_names;
+  while (san != nullptr) {
+    std::string san_str((const char *)san->buf.p, san->buf.len);
+    std::transform(san_str.begin(), san_str.end(), san_str.begin(), ::tolower);
+
+    if (matchName(san_str, domain_name_str)) {
+      return true;
+    }
+
+    log_d("SAN '%s': no match", san_str.c_str());
+
+    // Fetch next SAN
+    san = san->next;
+  }
+
+  // Check for domain name in CN
+  const mbedtls_asn1_named_data *common_name = &crt->subject;
+  while (common_name != nullptr) {
+    // While iterating through DN objects, check for CN object
+    if (!MBEDTLS_OID_CMP(MBEDTLS_OID_AT_CN, &common_name->oid)) {
+      std::string common_name_str((const char *)common_name->val.p, common_name->val.len);
+
+      if (matchName(common_name_str, domain_name_str)) {
+        return true;
+      }
+
+      log_d("CN '%s': not match", common_name_str.c_str());
+    }
+
+    // Fetch next DN object
+    common_name = common_name->next;
+  }
+
+  return false;
+}
+#endif
diff --git a/libraries/NetworkClientSecure/src/ssl_client.h b/libraries/NetworkClientSecure/src/ssl_client.h
new file mode 100644
index 00000000000..892adc86a95
--- /dev/null
+++ b/libraries/NetworkClientSecure/src/ssl_client.h
@@ -0,0 +1,56 @@
+/* Provide SSL/TLS functions to ESP32 with Arduino IDE
+ * by Evandro Copercini - 2017 - Apache 2.0 License
+ */
+
+#ifndef ARD_SSL_H
+#define ARD_SSL_H
+#include "mbedtls/platform.h"
+#include "mbedtls/net_sockets.h"
+#include "mbedtls/debug.h"
+#include "mbedtls/ssl.h"
+#include "mbedtls/entropy.h"
+#include "mbedtls/ctr_drbg.h"
+#include "mbedtls/error.h"
+
+typedef esp_err_t (*crt_bundle_attach_cb)(void *conf);
+
+typedef struct sslclient_context {
+  int socket;
+  mbedtls_ssl_context ssl_ctx;
+  mbedtls_ssl_config ssl_conf;
+
+  mbedtls_ctr_drbg_context drbg_ctx;
+  mbedtls_entropy_context entropy_ctx;
+
+  mbedtls_x509_crt ca_cert;
+  mbedtls_x509_crt client_cert;
+  mbedtls_pk_context client_key;
+
+  crt_bundle_attach_cb bundle_attach_cb;
+
+  unsigned long socket_timeout;
+  unsigned long handshake_timeout;
+
+  int last_error;
+  int peek_buf;
+
+} sslclient_context;
+
+void ssl_init(sslclient_context *ssl_client);
+int start_ssl_client(
+  sslclient_context *ssl_client, const IPAddress &ip, uint32_t port, const char *hostname, int timeout, const char *rootCABuff, bool useRootCABundle,
+  const char *cli_cert, const char *cli_key, const char *pskIdent, const char *psKey, bool insecure, const char **alpn_protos
+);
+void attach_ssl_certificate_bundle(sslclient_context *ssl_client, bool att);
+int ssl_starttls_handshake(sslclient_context *ssl_client);
+void stop_ssl_socket(sslclient_context *ssl_client);
+int data_to_read(sslclient_context *ssl_client);
+int send_ssl_data(sslclient_context *ssl_client, const uint8_t *data, size_t len);
+int get_ssl_receive(sslclient_context *ssl_client, uint8_t *data, int length);
+int send_net_data(sslclient_context *ssl_client, const uint8_t *data, size_t len);
+int get_net_receive(sslclient_context *ssl_client, uint8_t *data, int length);
+int peek_net_receive(sslclient_context *ssl_client, int timeout);
+bool verify_ssl_fingerprint(sslclient_context *ssl_client, const char *fp, const char *domain_name);
+bool verify_ssl_dn(sslclient_context *ssl_client, const char *domain_name);
+bool get_peer_fingerprint(sslclient_context *ssl_client, uint8_t sha256[32]);
+#endif
diff --git a/libraries/OpenThread/README.md b/libraries/OpenThread/README.md
new file mode 100644
index 00000000000..cd9deb9ebf6
--- /dev/null
+++ b/libraries/OpenThread/README.md
@@ -0,0 +1,72 @@
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+# ESP32 Arduino OpenThreadCLI
+
+The `OpenThreadCLI` class is an Arduino API for interacting with the OpenThread Command Line Interface (CLI). It allows you to manage and configure the Thread stack using a command-line interface.
+
+There is one main class called `OpenThreadCLI` and a global object used to operate OpenThread CLI, called `OThreadCLI`.\
+Some [helper functions](helper_functions.md) were made available for working with the OpenThread CLI environment.
+
+The available OpenThread Commands are documented in the [OpenThread CLI Reference Page](https://openthread.io/reference/cli/commands)
+
+It is important to note that the current implementation can only be used with Espressif SoC that has support to IEEE 802.15.4, such as **ESP32-C6** and **ESP32-H2**.
+
+Below are the details of the class:
+
+## Class Definition
+
+```cpp
+class OpenThreadCLI : public Stream {
+private:
+  static size_t setBuffer(QueueHandle_t &queue, size_t len);
+  bool otStarted = false;
+
+public:
+  OpenThreadCLI();
+  ~OpenThreadCLI();
+  operator bool() const;
+
+  // Starts a task to read/write otStream. Default prompt is "ot> ". Set it to NULL to make it invisible.
+  void startConsole(Stream& otStream, bool echoback = true, const char* prompt = "ot> ");
+  void stopConsole();
+  void setPrompt(char* prompt);      // Changes the console prompt. NULL is an empty prompt.
+  void setEchoBack(bool echoback);   // Changes the console echoback option
+  void setStream(Stream& otStream);  // Changes the console Stream object
+  void onReceive(OnReceiveCb_t func);  // Called on a complete line of output from OT CLI, as OT Response
+
+  void begin(bool OThreadAutoStart = true);
+  void end();
+
+  // Default size is 256 bytes
+  size_t setTxBufferSize(size_t tx_queue_len);
+  // Default size is 1024 bytes
+  size_t setRxBufferSize(size_t rx_queue_len);
+
+  size_t write(uint8_t);
+  int available();
+  int read();
+  int peek();
+  void flush();
+};
+
+extern OpenThreadCLI OThreadCLI;
+```
+
+## Class Overview
+- The `OpenThreadCLI` class inherits from the `Stream` class, making it compatible with Arduino's standard I/O functions.
+- It provides methods for managing the OpenThread CLI, including starting and stopping the console, setting prompts, and handling received data.
+- You can customize the console behavior by adjusting parameters such as echoback and buffer sizes.
+
+## Public Methods
+- `startConsole(Stream& otStream, bool echoback = true, const char* prompt = "ot> ")`: Starts the OpenThread console with the specified stream, echoback option, and prompt.
+- `stopConsole()`: Stops the OpenThread console.
+- `setPrompt(char* prompt)`: Changes the console prompt (set to NULL for an empty prompt).
+- `setEchoBack(bool echoback)`: Changes the console echoback option.
+- `setStream(Stream& otStream)`: Changes the console Stream object.
+- `onReceive(OnReceiveCb_t func)`: Sets a callback function to handle complete lines of output from the OT CLI.
+- `begin(bool OThreadAutoStart = true)`: Initializes the OpenThread stack (optional auto-start).
+- `end()`: Deinitializes the OpenThread stack.
+- `setTxBufferSize(size_t tx_queue_len)`: Sets the transmit buffer size (default is 256 bytes).
+- `setRxBufferSize(size_t rx_queue_len)`: Sets the receive buffer size (default is 1024 bytes).
+- `write(uint8_t)`, `available()`, `read()`, `peek()`, `flush()`: Standard Stream methods implementation for OpenThread CLI object.
diff --git a/libraries/OpenThread/examples/COAP/coap_lamp/ci.json b/libraries/OpenThread/examples/COAP/coap_lamp/ci.json
new file mode 100644
index 00000000000..2ee6af3490e
--- /dev/null
+++ b/libraries/OpenThread/examples/COAP/coap_lamp/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_OPENTHREAD_ENABLED=y",
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/OpenThread/examples/COAP/coap_lamp/coap_lamp.ino b/libraries/OpenThread/examples/COAP/coap_lamp/coap_lamp.ino
new file mode 100644
index 00000000000..51483bb4c7c
--- /dev/null
+++ b/libraries/OpenThread/examples/COAP/coap_lamp/coap_lamp.ino
@@ -0,0 +1,163 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "OThreadCLI.h"
+#include "OThreadCLI_Util.h"
+
+#define OT_CHANNEL            "24"
+#define OT_NETWORK_KEY        "00112233445566778899aabbccddeeff"
+#define OT_MCAST_ADDR         "ff05::abcd"
+#define OT_COAP_RESOURCE_NAME "Lamp"
+
+const char *otSetupLeader[] = {
+  // -- clear/disable all
+  // stop CoAP
+  "coap", "stop",
+  // stop Thread
+  "thread", "stop",
+  // stop the interface
+  "ifconfig", "down",
+  // clear the dataset
+  "dataset", "clear",
+  // -- set dataset
+  // create a new complete dataset with random data
+  "dataset", "init new",
+  // set the channel
+  "dataset channel", OT_CHANNEL,
+  // set the network key
+  "dataset networkkey", OT_NETWORK_KEY,
+  // commit the dataset
+  "dataset", "commit active",
+  // -- network start
+  // start the interface
+  "ifconfig", "up",
+  // start the Thread network
+  "thread", "start"
+};
+
+const char *otCoapLamp[] = {
+  // -- create a multicast IPv6 Address for this device
+  "ipmaddr add", OT_MCAST_ADDR,
+  // -- start and create a CoAP resource
+  // start CoAP as server
+  "coap", "start",
+  // create a CoAP resource
+  "coap resource", OT_COAP_RESOURCE_NAME,
+  // set the CoAP resource initial value
+  "coap set", "0"
+};
+
+bool otDeviceSetup(const char **otSetupCmds, uint8_t nCmds1, const char **otCoapCmds, uint8_t nCmds2, ot_device_role_t expectedRole) {
+  Serial.println("Starting OpenThread.");
+  Serial.println("Running as Lamp (RGB LED) - use the other C6/H2 as a Switch");
+  uint8_t i;
+  for (i = 0; i < nCmds1; i++) {
+    if (!otExecCommand(otSetupCmds[i * 2], otSetupCmds[i * 2 + 1])) {
+      break;
+    }
+  }
+  if (i != nCmds1) {
+    log_e("Sorry, OpenThread Network setup failed!");
+    rgbLedWrite(RGB_BUILTIN, 255, 0, 0);  // RED ... failed!
+    return false;
+  }
+  Serial.println("OpenThread started.\r\nWaiting for activating correct Device Role.");
+  // wait for the expected Device Role to start
+  uint8_t tries = 24;  // 24 x 2.5 sec = 1 min
+  while (tries && otGetDeviceRole() != expectedRole) {
+    Serial.print(".");
+    delay(2500);
+    tries--;
+  }
+  Serial.println();
+  if (!tries) {
+    log_e("Sorry, Device Role failed by timeout! Current Role: %s.", otGetStringDeviceRole());
+    rgbLedWrite(RGB_BUILTIN, 255, 0, 0);  // RED ... failed!
+    return false;
+  }
+  Serial.printf("Device is %s.\r\n", otGetStringDeviceRole());
+  for (i = 0; i < nCmds2; i++) {
+    if (!otExecCommand(otCoapCmds[i * 2], otCoapCmds[i * 2 + 1])) {
+      break;
+    }
+  }
+  if (i != nCmds2) {
+    log_e("Sorry, OpenThread CoAP setup failed!");
+    rgbLedWrite(RGB_BUILTIN, 255, 0, 0);  // RED ... failed!
+    return false;
+  }
+  Serial.println("OpenThread setup done. Node is ready.");
+  // all fine! LED goes Green
+  rgbLedWrite(RGB_BUILTIN, 0, 64, 8);  // GREEN ... Lamp is ready!
+  return true;
+}
+
+void setupNode() {
+  // tries to set the Thread Network node and only returns when succeeded
+  bool startedCorrectly = false;
+  while (!startedCorrectly) {
+    startedCorrectly |=
+      otDeviceSetup(otSetupLeader, sizeof(otSetupLeader) / sizeof(char *) / 2, otCoapLamp, sizeof(otCoapLamp) / sizeof(char *) / 2, OT_ROLE_LEADER);
+    if (!startedCorrectly) {
+      Serial.println("Setup Failed...\r\nTrying again...");
+    }
+  }
+}
+
+// this function is used by the Lamp mode to listen for CoAP frames from the Switch Node
+void otCOAPListen() {
+  // waits for the client to send a CoAP request
+  char cliResp[256] = {0};
+  size_t len = OThreadCLI.readBytesUntil('\n', cliResp, sizeof(cliResp));
+  cliResp[len - 1] = '\0';
+  if (strlen(cliResp)) {
+    String sResp(cliResp);
+    // cliResp shall be something like:
+    // "coap request from fd0c:94df:f1ae:b39a:ec47:ec6d:15e8:804a PUT with payload: 30"
+    // payload may be 30 or 31 (HEX) '0' or '1' (ASCII)
+    log_d("Msg[%s]", cliResp);
+    if (sResp.startsWith("coap request from") && sResp.indexOf("PUT") > 0) {
+      char payload = sResp.charAt(sResp.length() - 1);  //  last character in the payload
+      log_i("CoAP PUT [%s]\r\n", payload == '0' ? "OFF" : "ON");
+      if (payload == '0') {
+        for (int16_t c = 248; c > 16; c -= 8) {
+          rgbLedWrite(RGB_BUILTIN, c, c, c);  // ramp down
+          delay(5);
+        }
+        rgbLedWrite(RGB_BUILTIN, 0, 0, 0);  // Lamp Off
+      } else {
+        for (int16_t c = 16; c < 248; c += 8) {
+          rgbLedWrite(RGB_BUILTIN, c, c, c);  // ramp up
+          delay(5);
+        }
+        rgbLedWrite(RGB_BUILTIN, 255, 255, 255);  // Lamp On
+      }
+    }
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  // LED starts RED, indicating not connected to Thread network.
+  rgbLedWrite(RGB_BUILTIN, 64, 0, 0);
+  OThreadCLI.begin(false);     // No AutoStart is necessary
+  OThreadCLI.setTimeout(250);  // waits 250ms for the OpenThread CLI response
+  setupNode();
+  // LED goes Green when all is ready and Red when failed.
+}
+
+void loop() {
+  otCOAPListen();
+  delay(10);
+}
diff --git a/libraries/OpenThread/examples/COAP/coap_switch/ci.json b/libraries/OpenThread/examples/COAP/coap_switch/ci.json
new file mode 100644
index 00000000000..2ee6af3490e
--- /dev/null
+++ b/libraries/OpenThread/examples/COAP/coap_switch/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_OPENTHREAD_ENABLED=y",
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/OpenThread/examples/COAP/coap_switch/coap_switch.ino b/libraries/OpenThread/examples/COAP/coap_switch/coap_switch.ino
new file mode 100644
index 00000000000..aac5db0bc82
--- /dev/null
+++ b/libraries/OpenThread/examples/COAP/coap_switch/coap_switch.ino
@@ -0,0 +1,188 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "OThreadCLI.h"
+#include "OThreadCLI_Util.h"
+
+#define USER_BUTTON           9  // C6/H2 Boot button
+#define OT_CHANNEL            "24"
+#define OT_NETWORK_KEY        "00112233445566778899aabbccddeeff"
+#define OT_MCAST_ADDR         "ff05::abcd"
+#define OT_COAP_RESOURCE_NAME "Lamp"
+
+const char *otSetupChild[] = {
+  // -- clear/disable all
+  // stop CoAP
+  "coap", "stop",
+  // stop Thread
+  "thread", "stop",
+  // stop the interface
+  "ifconfig", "down",
+  // clear the dataset
+  "dataset", "clear",
+  // -- set dataset
+  // set the channel
+  "dataset channel", OT_CHANNEL,
+  // set the network key
+  "dataset networkkey", OT_NETWORK_KEY,
+  // commit the dataset
+  "dataset", "commit active",
+  // -- network start
+  // start the interface
+  "ifconfig", "up",
+  // start the Thread network
+  "thread", "start"
+};
+
+const char *otCoapSwitch[] = {
+  // -- start CoAP as client
+  "coap", "start"
+};
+
+bool otDeviceSetup(
+  const char **otSetupCmds, uint8_t nCmds1, const char **otCoapCmds, uint8_t nCmds2, ot_device_role_t expectedRole1, ot_device_role_t expectedRole2
+) {
+  Serial.println("Starting OpenThread.");
+  Serial.println("Running as Switch - use the BOOT button to toggle the other C6/H2 as a Lamp");
+  uint8_t i;
+  for (i = 0; i < nCmds1; i++) {
+    if (!otExecCommand(otSetupCmds[i * 2], otSetupCmds[i * 2 + 1])) {
+      break;
+    }
+  }
+  if (i != nCmds1) {
+    log_e("Sorry, OpenThread Network setup failed!");
+    rgbLedWrite(RGB_BUILTIN, 255, 0, 0);  // RED ... failed!
+    return false;
+  }
+  Serial.println("OpenThread started.\r\nWaiting for activating correct Device Role.");
+  // wait for the expected Device Role to start
+  uint8_t tries = 24;  // 24 x 2.5 sec = 1 min
+  while (tries && otGetDeviceRole() != expectedRole1 && otGetDeviceRole() != expectedRole2) {
+    Serial.print(".");
+    delay(2500);
+    tries--;
+  }
+  Serial.println();
+  if (!tries) {
+    log_e("Sorry, Device Role failed by timeout! Current Role: %s.", otGetStringDeviceRole());
+    rgbLedWrite(RGB_BUILTIN, 255, 0, 0);  // RED ... failed!
+    return false;
+  }
+  Serial.printf("Device is %s.\r\n", otGetStringDeviceRole());
+  for (i = 0; i < nCmds2; i++) {
+    if (!otExecCommand(otCoapCmds[i * 2], otCoapCmds[i * 2 + 1])) {
+      break;
+    }
+  }
+  if (i != nCmds2) {
+    log_e("Sorry, OpenThread CoAP setup failed!");
+    rgbLedWrite(RGB_BUILTIN, 255, 0, 0);  // RED ... failed!
+    return false;
+  }
+  Serial.println("OpenThread setup done. Node is ready.");
+  // all fine! LED goes and stays Blue
+  rgbLedWrite(RGB_BUILTIN, 0, 0, 64);  // BLUE ... Switch is ready!
+  return true;
+}
+
+void setupNode() {
+  // tries to set the Thread Network node and only returns when succeeded
+  bool startedCorrectly = false;
+  while (!startedCorrectly) {
+    startedCorrectly |= otDeviceSetup(
+      otSetupChild, sizeof(otSetupChild) / sizeof(char *) / 2, otCoapSwitch, sizeof(otCoapSwitch) / sizeof(char *) / 2, OT_ROLE_CHILD, OT_ROLE_ROUTER
+    );
+    if (!startedCorrectly) {
+      Serial.println("Setup Failed...\r\nTrying again...");
+    }
+  }
+}
+
+// Sends the CoAP frame to the Lamp node
+bool otCoapPUT(bool lampState) {
+  bool gotDone = false, gotConfirmation = false;
+  String coapMsg = "coap put ";
+  coapMsg += OT_MCAST_ADDR;
+  coapMsg += " ";
+  coapMsg += OT_COAP_RESOURCE_NAME;
+  coapMsg += " con 0";
+
+  // final command is "coap put ff05::abcd Lamp con 1" or "coap put ff05::abcd Lamp con 0"
+  if (lampState) {
+    coapMsg[coapMsg.length() - 1] = '1';
+  }
+  OThreadCLI.println(coapMsg.c_str());
+  log_d("Send CLI CMD:[%s]", coapMsg.c_str());
+
+  char cliResp[256];
+  // waits for the CoAP confirmation and Done message for about 1.25 seconds
+  // timeout is based on Stream::setTimeout()
+  // Example of the expected confirmation response: "coap response from fdae:3289:1783:5c3f:fd84:c714:7e83:6122"
+  uint8_t tries = 5;
+  *cliResp = '\0';
+  while (tries && !(gotDone && gotConfirmation)) {
+    size_t len = OThreadCLI.readBytesUntil('\n', cliResp, sizeof(cliResp));
+    cliResp[len - 1] = '\0';
+    log_d("Try[%d]::MSG[%s]", tries, cliResp);
+    if (strlen(cliResp)) {
+      if (!strncmp(cliResp, "coap response from", 18)) {
+        gotConfirmation = true;
+      }
+      if (!strncmp(cliResp, "Done", 4)) {
+        gotDone = true;
+      }
+    }
+    tries--;
+  }
+  if (gotDone && gotConfirmation) {
+    return true;
+  }
+  return false;
+}
+
+// this function is used by the Switch mode to check the BOOT Button and send the user action to the Lamp node
+void checkUserButton() {
+  static long unsigned int lastPress = 0;
+  const long unsigned int debounceTime = 500;
+  static bool lastLampState = true;  // first button press will turn the Lamp OFF from initial Green
+
+  pinMode(USER_BUTTON, INPUT_PULLUP);  // C6/H2 User Button
+  if (millis() > lastPress + debounceTime && digitalRead(USER_BUTTON) == LOW) {
+    lastLampState = !lastLampState;
+    if (!otCoapPUT(lastLampState)) {  // failed: Lamp Node is not responding due to be off or unreachable
+      // timeout from the CoAP PUT message... restart the node.
+      rgbLedWrite(RGB_BUILTIN, 255, 0, 0);  // RED ... something failed!
+      Serial.println("Resetting the Node as Switch... wait.");
+      // start over...
+      setupNode();
+    }
+    lastPress = millis();
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  // LED starts RED, indicating not connected to Thread network.
+  rgbLedWrite(RGB_BUILTIN, 64, 0, 0);
+  OThreadCLI.begin(false);     // No AutoStart is necessary
+  OThreadCLI.setTimeout(250);  // waits 250ms for the OpenThread CLI response
+  setupNode();
+  // LED goes and keeps Blue when all is ready and Red when failed.
+}
+
+void loop() {
+  checkUserButton();
+  delay(10);
+}
diff --git a/libraries/OpenThread/examples/SimpleCLI/SimpleCLI.ino b/libraries/OpenThread/examples/SimpleCLI/SimpleCLI.ino
new file mode 100644
index 00000000000..feef800c0fa
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleCLI/SimpleCLI.ino
@@ -0,0 +1,34 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * OpenThread.begin(false) will not automatically start a node in a Thread Network
+ * The user will need to start it manually using the OpenThread CLI commands
+ * Use the Serial Monitor to interact with the OpenThread CLI
+ *
+ * Type 'help' for a list of commands.
+ * Documentation: https://openthread.io/reference/cli/commands
+ *
+ */
+
+#include "OThreadCLI.h"
+
+void setup() {
+  Serial.begin(115200);
+  OThreadCLI.begin(false);  // No AutoStart - fresh start
+  Serial.println("OpenThread CLI started - type 'help' for a list of commands.");
+  OThreadCLI.startConsole(Serial);
+}
+
+void loop() {}
diff --git a/libraries/OpenThread/examples/SimpleCLI/ci.json b/libraries/OpenThread/examples/SimpleCLI/ci.json
new file mode 100644
index 00000000000..2ee6af3490e
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleCLI/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_OPENTHREAD_ENABLED=y",
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/OpenThread/examples/SimpleNode/SimpleNode.ino b/libraries/OpenThread/examples/SimpleNode/SimpleNode.ino
new file mode 100644
index 00000000000..95bf7a2401a
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleNode/SimpleNode.ino
@@ -0,0 +1,46 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * OpenThread.begin() will automatically start a node in a Thread Network
+ * If NVS is empty, default configuration will be as follow:
+ *
+ *   NETWORK_NAME "OpenThread-ESP"
+ *   MESH_LOCAL_PREFIX "fd00:db8:a0:0::/64"
+ *   NETWORK_CHANNEL 15
+ *   NETWORK_PANID 0x1234
+ *   NETWORK_EXTPANID "dead00beef00cafe"
+ *   NETWORK_KEY "00112233445566778899aabbccddeeff"
+ *   NETWORK_PSKC "104810e2315100afd6bc9215a6bfac53"
+ *
+ * If NVS has already a dataset information, it will load it from there.
+ */
+
+#include "OThreadCLI.h"
+#include "OThreadCLI_Util.h"
+
+// The first device to start Thread will be the Leader
+// Next devices will be Router or Child
+
+void setup() {
+  Serial.begin(115200);
+  OThreadCLI.begin();                 // AutoStart using Thread default settings
+  otPrintNetworkInformation(Serial);  // Print Current Thread Network Information
+}
+
+void loop() {
+  Serial.print("Thread Node State: ");
+  Serial.println(otGetStringDeviceRole());
+  delay(5000);
+}
diff --git a/libraries/OpenThread/examples/SimpleNode/ci.json b/libraries/OpenThread/examples/SimpleNode/ci.json
new file mode 100644
index 00000000000..2ee6af3490e
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleNode/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_OPENTHREAD_ENABLED=y",
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/OpenThread/examples/SimpleThreadNetwork/ExtendedRouterNode/ExtendedRouterNode.ino b/libraries/OpenThread/examples/SimpleThreadNetwork/ExtendedRouterNode/ExtendedRouterNode.ino
new file mode 100644
index 00000000000..4fc8a921584
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleThreadNetwork/ExtendedRouterNode/ExtendedRouterNode.ino
@@ -0,0 +1,79 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "OThreadCLI.h"
+#include "OThreadCLI_Util.h"
+
+// Leader node shall use the same Network Key and channel
+#define CLI_NETWORK_KEY    "00112233445566778899aabbccddeeff"
+#define CLI_NETWORK_CHANEL "24"
+bool otStatus = true;
+
+void setup() {
+  Serial.begin(115200);
+  OThreadCLI.begin(false);  // No AutoStart - fresh start
+  Serial.println("Setting up OpenThread Node as Router/Child");
+  Serial.println("Make sure the Leader Node is already running");
+
+  otStatus &= otExecCommand("dataset", "clear");
+  otStatus &= otExecCommand("dataset networkkey", CLI_NETWORK_KEY);
+  otStatus &= otExecCommand("dataset channel", CLI_NETWORK_CHANEL);
+  otStatus &= otExecCommand("dataset", "commit active");
+  otStatus &= otExecCommand("ifconfig", "up");
+  otStatus &= otExecCommand("thread", "start");
+
+  if (!otStatus) {
+    Serial.println("\r\n\t===> Failed starting Thread Network!");
+    return;
+  }
+  // wait for the node to enter in the router state
+  uint32_t timeout = millis() + 90000;  // waits 90 seconds to
+  while (otGetDeviceRole() != OT_ROLE_CHILD && otGetDeviceRole() != OT_ROLE_ROUTER) {
+    Serial.print(".");
+    if (millis() > timeout) {
+      Serial.println("\r\n\t===> Timeout! Failed.");
+      otStatus = false;
+      break;
+    }
+    delay(500);
+  }
+
+  if (otStatus) {
+    // print the PanID using 2 methods
+
+    // CLI
+    char resp[256];
+    if (otGetRespCmd("panid", resp)) {
+      Serial.printf("\r\nPanID[using CLI]: %s\r\n", resp);
+    } else {
+      Serial.printf("\r\nPanID[using CLI]: FAILED!\r\n");
+    }
+
+    // OpenThread API
+    Serial.printf("PanID[using OT API]: 0x%x\r\n", (uint16_t)otLinkGetPanId(esp_openthread_get_instance()));
+  }
+  Serial.println("\r\n");
+}
+
+void loop() {
+  if (otStatus) {
+    Serial.println("Thread NetworkInformation: ");
+    Serial.println("---------------------------");
+    otPrintNetworkInformation(Serial);
+    Serial.println("---------------------------");
+  } else {
+    Serial.println("Some OpenThread operation has failed...");
+  }
+  delay(10000);
+}
diff --git a/libraries/OpenThread/examples/SimpleThreadNetwork/ExtendedRouterNode/ci.json b/libraries/OpenThread/examples/SimpleThreadNetwork/ExtendedRouterNode/ci.json
new file mode 100644
index 00000000000..2ee6af3490e
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleThreadNetwork/ExtendedRouterNode/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_OPENTHREAD_ENABLED=y",
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/OpenThread/examples/SimpleThreadNetwork/LeaderNode/LeaderNode.ino b/libraries/OpenThread/examples/SimpleThreadNetwork/LeaderNode/LeaderNode.ino
new file mode 100644
index 00000000000..7b709717692
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleThreadNetwork/LeaderNode/LeaderNode.ino
@@ -0,0 +1,101 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+   OpenThread.begin(false) will not automatically start a node in a Thread Network
+   A Leader node is the first device, that has a complete dataset, to start Thread
+   A complete dataset is easily achieved by using the OpenThread CLI command "dataset init new"
+
+   In order to allow other node to join the network,
+   all of them shall use the same network master key
+   The network master key is a 16-byte key that is used to secure the network
+
+   Using the same channel will make the process faster
+
+*/
+
+#include "OThreadCLI.h"
+#include "OThreadCLI_Util.h"
+
+#define CLI_NETWORK_KEY    "dataset networkkey 00112233445566778899aabbccddeeff"
+#define CLI_NETWORK_CHANEL "dataset channel 24"
+
+otInstance *aInstance = NULL;
+
+void setup() {
+  Serial.begin(115200);
+  OThreadCLI.begin(false);  // No AutoStart - fresh start
+  Serial.println();
+  Serial.println("Setting up OpenThread Node as Leader");
+  aInstance = esp_openthread_get_instance();
+
+  OThreadCLI.println("dataset init new");
+  OThreadCLI.println(CLI_NETWORK_KEY);
+  OThreadCLI.println(CLI_NETWORK_CHANEL);
+  OThreadCLI.println("dataset commit active");
+  OThreadCLI.println("ifconfig up");
+  OThreadCLI.println("thread start");
+}
+
+void loop() {
+  Serial.println("=============================================");
+  Serial.print("Thread Node State: ");
+  Serial.println(otGetStringDeviceRole());
+
+  // Native OpenThread API calls:
+  // wait until the node become Child or Router
+  if (otGetDeviceRole() == OT_ROLE_LEADER) {
+    // Network Name
+    const char *networkName = otThreadGetNetworkName(aInstance);
+    Serial.printf("Network Name: %s\r\n", networkName);
+    // Channel
+    uint8_t channel = otLinkGetChannel(aInstance);
+    Serial.printf("Channel: %d\r\n", channel);
+    // PAN ID
+    uint16_t panId = otLinkGetPanId(aInstance);
+    Serial.printf("PanID: 0x%04x\r\n", panId);
+    // Extended PAN ID
+    const otExtendedPanId *extPanId = otThreadGetExtendedPanId(aInstance);
+    Serial.printf("Extended PAN ID: ");
+    for (int i = 0; i < OT_EXT_PAN_ID_SIZE; i++) {
+      Serial.printf("%02x", extPanId->m8[i]);
+    }
+    Serial.println();
+    // Network Key
+    otNetworkKey networkKey;
+    otThreadGetNetworkKey(aInstance, &networkKey);
+    Serial.printf("Network Key: ");
+    for (int i = 0; i < OT_NETWORK_KEY_SIZE; i++) {
+      Serial.printf("%02x", networkKey.m8[i]);
+    }
+    Serial.println();
+    // IP Addresses
+    char buf[OT_IP6_ADDRESS_STRING_SIZE];
+    const otNetifAddress *address = otIp6GetUnicastAddresses(aInstance);
+    while (address != NULL) {
+      otIp6AddressToString(&address->mAddress, buf, sizeof(buf));
+      Serial.printf("IP Address: %s\r\n", buf);
+      address = address->mNext;
+    }
+    // Multicast IP Addresses
+    const otNetifMulticastAddress *mAddress = otIp6GetMulticastAddresses(aInstance);
+    while (mAddress != NULL) {
+      otIp6AddressToString(&mAddress->mAddress, buf, sizeof(buf));
+      printf("Multicast IP Address: %s\n", buf);
+      mAddress = mAddress->mNext;
+    }
+  }
+
+  delay(5000);
+}
diff --git a/libraries/OpenThread/examples/SimpleThreadNetwork/LeaderNode/ci.json b/libraries/OpenThread/examples/SimpleThreadNetwork/LeaderNode/ci.json
new file mode 100644
index 00000000000..2ee6af3490e
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleThreadNetwork/LeaderNode/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_OPENTHREAD_ENABLED=y",
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/OpenThread/examples/SimpleThreadNetwork/RouterNode/RouterNode.ino b/libraries/OpenThread/examples/SimpleThreadNetwork/RouterNode/RouterNode.ino
new file mode 100644
index 00000000000..45475fa0c6a
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleThreadNetwork/RouterNode/RouterNode.ino
@@ -0,0 +1,101 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+   OpenThread.begin(false) will not automatically start a node in a Thread Network
+   A Router/Child node is the device that will join an existing Thread Network
+
+   In order to allow this node to join the network,
+   it shall use the same network master key as used by the Leader Node
+   The network master key is a 16-byte key that is used to secure the network
+
+   Using the same channel will make the process faster
+
+*/
+
+#include "OThreadCLI.h"
+#include "OThreadCLI_Util.h"
+
+#define CLI_NETWORK_KEY    "dataset networkkey 00112233445566778899aabbccddeeff"
+#define CLI_NETWORK_CHANEL "dataset channel 24"
+
+otInstance *aInstance = NULL;
+
+void setup() {
+  Serial.begin(115200);
+  OThreadCLI.begin(false);  // No AutoStart - fresh start
+  Serial.println();
+  Serial.println("Setting up OpenThread Node as Router/Child");
+  Serial.println("Make sure the Leader Node is already running");
+  aInstance = esp_openthread_get_instance();
+
+  OThreadCLI.println("dataset clear");
+  OThreadCLI.println(CLI_NETWORK_KEY);
+  OThreadCLI.println(CLI_NETWORK_CHANEL);
+  OThreadCLI.println("dataset commit active");
+  OThreadCLI.println("ifconfig up");
+  OThreadCLI.println("thread start");
+}
+
+void loop() {
+  Serial.println("=============================================");
+  Serial.print("Thread Node State: ");
+  Serial.println(otGetStringDeviceRole());
+
+  // Native OpenThread API calls:
+  // wait until the node become Child or Router
+  if (otGetDeviceRole() == OT_ROLE_CHILD || otGetDeviceRole() == OT_ROLE_ROUTER) {
+    // Network Name
+    const char *networkName = otThreadGetNetworkName(aInstance);
+    Serial.printf("Network Name: %s\r\n", networkName);
+    // Channel
+    uint8_t channel = otLinkGetChannel(aInstance);
+    Serial.printf("Channel: %d\r\n", channel);
+    // PAN ID
+    uint16_t panId = otLinkGetPanId(aInstance);
+    Serial.printf("PanID: 0x%04x\r\n", panId);
+    // Extended PAN ID
+    const otExtendedPanId *extPanId = otThreadGetExtendedPanId(aInstance);
+    Serial.printf("Extended PAN ID: ");
+    for (int i = 0; i < OT_EXT_PAN_ID_SIZE; i++) {
+      Serial.printf("%02x", extPanId->m8[i]);
+    }
+    Serial.println();
+    // Network Key
+    otNetworkKey networkKey;
+    otThreadGetNetworkKey(aInstance, &networkKey);
+    Serial.printf("Network Key: ");
+    for (int i = 0; i < OT_NETWORK_KEY_SIZE; i++) {
+      Serial.printf("%02x", networkKey.m8[i]);
+    }
+    Serial.println();
+    // IP Addresses
+    char buf[OT_IP6_ADDRESS_STRING_SIZE];
+    const otNetifAddress *address = otIp6GetUnicastAddresses(aInstance);
+    while (address != NULL) {
+      otIp6AddressToString(&address->mAddress, buf, sizeof(buf));
+      Serial.printf("IP Address: %s\r\n", buf);
+      address = address->mNext;
+    }
+    // Multicast IP Addresses
+    const otNetifMulticastAddress *mAddress = otIp6GetMulticastAddresses(aInstance);
+    while (mAddress != NULL) {
+      otIp6AddressToString(&mAddress->mAddress, buf, sizeof(buf));
+      printf("Multicast IP Address: %s\n", buf);
+      mAddress = mAddress->mNext;
+    }
+  }
+
+  delay(5000);
+}
diff --git a/libraries/OpenThread/examples/SimpleThreadNetwork/RouterNode/ci.json b/libraries/OpenThread/examples/SimpleThreadNetwork/RouterNode/ci.json
new file mode 100644
index 00000000000..2ee6af3490e
--- /dev/null
+++ b/libraries/OpenThread/examples/SimpleThreadNetwork/RouterNode/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_OPENTHREAD_ENABLED=y",
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/OpenThread/examples/ThreadScan/ThreadScan.ino b/libraries/OpenThread/examples/ThreadScan/ThreadScan.ino
new file mode 100644
index 00000000000..9d0074bb180
--- /dev/null
+++ b/libraries/OpenThread/examples/ThreadScan/ThreadScan.ino
@@ -0,0 +1,55 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+   OpenThread.begin(true) will automatically start a node in a Thread Network
+   Full scanning requires the thread node to be at least in Child state.
+
+   This will scan the IEEE 802.14.5 devices in the local area using CLI "scan" command
+   As soon as this device turns into a Child, Router or Leader, it will be able to
+   scan for Local Thread Networks as well.
+
+*/
+
+#include "OThreadCLI.h"
+#include "OThreadCLI_Util.h"
+
+void setup() {
+  Serial.begin(115200);
+  OThreadCLI.begin(true);      // For scanning, AutoStart must be active, any setup
+  OThreadCLI.setTimeout(100);  // Set a timeout for the CLI response
+  Serial.println();
+  Serial.println("This sketch will continuously scan the Thread Local Network and all devices IEEE 802.15.4 compatible");
+}
+
+void loop() {
+  Serial.println();
+  Serial.println("Scanning for nearby IEEE 802.15.4 devices:");
+  // 802.15.4 Scan just needs a previous OThreadCLI.begin()
+  if (!otPrintRespCLI("scan", Serial, 3000)) {
+    Serial.println("Scan Failed...");
+  }
+  delay(5000);
+  if (otGetDeviceRole() < OT_ROLE_CHILD) {
+    Serial.println();
+    Serial.println("This device has not started Thread yet, bypassing Discovery Scan");
+    return;
+  }
+  Serial.println();
+  Serial.println("Scanning MLE Discover:");
+  if (!otPrintRespCLI("discover", Serial, 3000)) {
+    Serial.println("Discover Failed...");
+  }
+  delay(5000);
+}
diff --git a/libraries/OpenThread/examples/ThreadScan/ci.json b/libraries/OpenThread/examples/ThreadScan/ci.json
new file mode 100644
index 00000000000..2ee6af3490e
--- /dev/null
+++ b/libraries/OpenThread/examples/ThreadScan/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_OPENTHREAD_ENABLED=y",
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/OpenThread/examples/onReceive/ci.json b/libraries/OpenThread/examples/onReceive/ci.json
new file mode 100644
index 00000000000..2ee6af3490e
--- /dev/null
+++ b/libraries/OpenThread/examples/onReceive/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_OPENTHREAD_ENABLED=y",
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/OpenThread/examples/onReceive/onReceive.ino b/libraries/OpenThread/examples/onReceive/onReceive.ino
new file mode 100644
index 00000000000..b37c2fc7931
--- /dev/null
+++ b/libraries/OpenThread/examples/onReceive/onReceive.ino
@@ -0,0 +1,51 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+   OpenThread.begin() will automatically start a node in a Thread Network
+   This will demonstrate how to capture the CLI response in a callback function
+   The device state shall change from "disabled" to valid Thread states along time
+*/
+
+#include "OThreadCLI.h"
+
+// reads all the lines sent by CLI, one by one
+// ignores some lines that are just a sequence of \r\n
+void otReceivedLine() {
+  String line = "";
+  while (OThreadCLI.available() > 0) {
+    char ch = OThreadCLI.read();
+    if (ch != '\r' && ch != '\n') {
+      line += ch;
+    }
+  }
+  // ignores empty lines, usually EOL sequence
+  if (line.length() > 0) {
+    Serial.print("OpenThread CLI RESP===> ");
+    Serial.println(line.c_str());
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  OThreadCLI.begin();  // AutoStart
+  OThreadCLI.onReceive(otReceivedLine);
+}
+
+void loop() {
+  // sends the "state" command to the CLI every second
+  // the onReceive() Callback Function will read and process the response
+  OThreadCLI.println("state");
+  delay(1000);
+}
diff --git a/libraries/OpenThread/helper_functions.md b/libraries/OpenThread/helper_functions.md
new file mode 100644
index 00000000000..db8b7db29e9
--- /dev/null
+++ b/libraries/OpenThread/helper_functions.md
@@ -0,0 +1,59 @@
+# OpenThread Helper Functions and Types
+
+The following helper functions and types are designed to simplify writing Arduino sketches for OpenThread.\
+They provide useful utilities for managing OpenThread stack behavior and interacting with the Thread network.
+
+### Enumerated Type: `ot_device_role_t`
+
+This enumeration defines the possible roles of a Thread device within the network:
+
+- `OT_ROLE_DISABLED`: The Thread stack is disabled.
+- `OT_ROLE_DETACHED`: The device is not currently participating in a Thread network/partition.
+- `OT_ROLE_CHILD`: The device operates as a Thread Child.
+- `OT_ROLE_ROUTER`: The device operates as a Thread Router.
+- `OT_ROLE_LEADER`: The device operates as a Thread Leader.
+
+### Struct: `ot_cmd_return_t`
+
+This structure represents the return status of an OpenThread CLI command:
+
+- `errorCode`: An integer representing the error code (if any).
+- `errorMessage`: A string containing an error message (if applicable).
+
+### Function: `otGetDeviceRole()`
+
+- Returns the current role of the device as an `ot_device_role_t` value.
+
+### Function: `otGetStringDeviceRole()`
+
+- Returns a human-readable string representation of the device role (e.g., "Child," "Router," etc.).
+
+### Function: `otGetRespCmd(const char* cmd, char* resp = NULL, uint32_t respTimeout = 5000)`
+
+- Executes an OpenThread CLI command and retrieves the response.
+- Parameters:
+  - `cmd`: The OpenThread CLI command to execute.
+  - `resp`: Optional buffer to store the response (if provided).
+  - `respTimeout`: Timeout (in milliseconds) for waiting for the response.
+
+### Function: `otExecCommand(const char* cmd, const char* arg, ot_cmd_return_t* returnCode = NULL)`
+
+- Executes an OpenThread CLI command with an argument.
+- Parameters:
+  - `cmd`: The OpenThread CLI command to execute.
+  - `arg`: The argument for the command.
+  - `returnCode`: Optional pointer to an `ot_cmd_return_t` structure to store the return status.
+
+### Function: `otPrintRespCLI(const char* cmd, Stream& output, uint32_t respTimeout)`
+
+- Executes an OpenThread CLI command and prints the response to the specified output stream.
+- Parameters:
+  - `cmd`: The OpenThread CLI command to execute.
+  - `output`: The output stream (e.g., Serial) to print the response.
+  - `respTimeout`: Timeout (in milliseconds) for waiting for the response.
+
+### Function: `otPrintNetworkInformation(Stream& output)`
+
+- Prints information about the current Thread network to the specified output stream.
+- Parameters:
+  - `output`: The output stream (e.g., Serial) to print the network information.
diff --git a/libraries/OpenThread/keywords.txt b/libraries/OpenThread/keywords.txt
new file mode 100644
index 00000000000..d7193de188d
--- /dev/null
+++ b/libraries/OpenThread/keywords.txt
@@ -0,0 +1,47 @@
+#######################################
+# Syntax Coloring Map For OpenThread
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+OThreadCLI	KEYWORD1
+OpenThreadCLI	KEYWORD1
+ot_cmd_return_t	KEYWORD1
+ot_device_role_t	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+startConsole	KEYWORD2
+stopConsole	KEYWORD2
+setPrompt	KEYWORD2
+setEchoBack	KEYWORD2
+setStream	KEYWORD2
+onReceive	KEYWORD2
+begin	KEYWORD2
+setTxBufferSize	KEYWORD2
+setRxBufferSize	KEYWORD2
+write	KEYWORD2
+available	KEYWORD2
+read	KEYWORD2
+peek	KEYWORD2
+flush	KEYWORD2
+otGetDeviceRole	KEYWORD2
+otGetStringDeviceRole	KEYWORD2
+otGetRespCmd	KEYWORD2
+otExecCommand	KEYWORD2
+otPrintRespCLI	KEYWORD2
+otPrintNetworkInformation	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+
+OT_ROLE_DISABLED	LITERAL1
+OT_ROLE_DETACHED	LITERAL1
+OT_ROLE_CHILD	LITERAL1
+OT_ROLE_ROUTER	LITERAL1
+OT_ROLE_LEADER	LITERAL1
diff --git a/libraries/OpenThread/library.properties b/libraries/OpenThread/library.properties
new file mode 100644
index 00000000000..0e547d188aa
--- /dev/null
+++ b/libraries/OpenThread/library.properties
@@ -0,0 +1,9 @@
+name=OpenThread
+version=3.2.0
+author=Rodrigo Garcia | GitHub @SuGlider
+maintainer=Rodrigo Garcia <Rodrigo.Garcia@espressif.com>
+sentence=Library for OpenThread Network on ESP32.
+paragraph=This library is a wrapper for OpenThread CLI. It provides a simple way to interact with OpenThread Network.
+category=Communication
+url=https://github.com/espressif/arduino-esp32/
+architectures=esp32
diff --git a/libraries/OpenThread/src/OThreadCLI.cpp b/libraries/OpenThread/src/OThreadCLI.cpp
new file mode 100644
index 00000000000..85ba03563e8
--- /dev/null
+++ b/libraries/OpenThread/src/OThreadCLI.cpp
@@ -0,0 +1,469 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "OThreadCLI.h"
+#if SOC_IEEE802154_SUPPORTED
+#if CONFIG_OPENTHREAD_ENABLED
+
+#include "Arduino.h"
+#include "OThreadCLI.h"
+
+#include "esp_err.h"
+#include "esp_event.h"
+#include "esp_netif.h"
+#include "esp_netif_types.h"
+#include "esp_vfs_eventfd.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "freertos/queue.h"
+
+#include "esp_netif_net_stack.h"
+#include "lwip/netif.h"
+
+static TaskHandle_t s_cli_task = NULL;
+static TaskHandle_t s_console_cli_task = NULL;
+static QueueHandle_t rx_queue = NULL;
+static QueueHandle_t tx_queue = NULL;
+
+static esp_openthread_platform_config_t ot_native_config;
+static TaskHandle_t s_ot_task = NULL;
+static esp_netif_t *openthread_netif = NULL;
+#if CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM
+static struct netif *ot_lwip_netif = NULL;
+#endif
+
+#define OT_CLI_MAX_LINE_LENGTH 512
+
+typedef struct {
+  Stream *cliStream;
+  bool echoback;
+  String prompt;
+  OnReceiveCb_t responseCallBack;
+} ot_cli_console_t;
+static ot_cli_console_t otConsole = {NULL, false, (const char *)NULL, NULL};
+
+#if CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM
+extern "C" int lwip_hook_ip6_input(struct pbuf *p, struct netif *inp) {
+  if (ot_lwip_netif && ot_lwip_netif == inp) {
+    return 0;
+  }
+  if (ip6_addr_isany_val(inp->ip6_addr[0].u_addr.ip6)) {
+    // We don't have an LL address -> eat this packet here, so it won't get accepted on input netif
+    pbuf_free(p);
+    return 1;
+  }
+  return 0;
+}
+#endif
+
+// process the CLI commands sent to the OpenThread stack
+static void ot_cli_loop(void *context) {
+  String sTxString("");
+
+  while (true) {
+    if (tx_queue != NULL) {
+      uint8_t c;
+      if (xQueueReceive(tx_queue, &c, portMAX_DELAY)) {
+        // avoids sending a empty command, specially when the terminal send "\r\n" together
+        if (sTxString.length() > 0 && (c == '\r' || c == '\n')) {
+          esp_openthread_cli_input(sTxString.c_str());
+          xTaskNotifyWait(0, 0, NULL, portMAX_DELAY);
+          sTxString = "";
+        } else {
+          if (c == '\b' || c == 127) {
+            if (sTxString.length() > 0) {
+              sTxString.remove(sTxString.length() - 1);
+            }
+          } else {
+            // only allow printable characters
+            if (c > 31 && c < 127) {
+              sTxString += (char)c;
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+// process the CLI responses received from the OpenThread stack
+static int ot_cli_output_callback(void *context, const char *format, va_list args) {
+  char prompt_check[3];
+  int ret = 0;
+
+  vsnprintf(prompt_check, sizeof(prompt_check), format, args);
+  if (!strncmp(prompt_check, "> ", sizeof(prompt_check))) {
+    if (s_cli_task) {
+      xTaskNotifyGive(s_cli_task);
+    }
+    if (s_console_cli_task) {
+      xTaskNotifyGive(s_console_cli_task);
+    }
+  } else {
+    char buf[OT_CLI_MAX_LINE_LENGTH];
+    ret = vsnprintf(buf, sizeof(buf), format, args);
+    if (ret) {
+      // store received data in the RX buffer
+      if (rx_queue != NULL) {
+        size_t freeSpace = uxQueueSpacesAvailable(rx_queue);
+        if (freeSpace < ret) {
+          // Drop the oldest data to make room for the new data
+          for (int i = 0; i < (ret - freeSpace); i++) {
+            uint8_t c;
+            xQueueReceive(rx_queue, &c, 0);
+          }
+        }
+        for (int i = 0; i < ret; i++) {
+          xQueueSend(rx_queue, &buf[i], 0);
+        }
+        // if there is a user callback function in place, it shall have the priority
+        // to process/consume the Stream data received from OpenThread CLI, which is available in its RX Buffer
+        if (otConsole.responseCallBack != NULL) {
+          otConsole.responseCallBack();
+        }
+      }
+    }
+  }
+  return ret;
+}
+
+// helper task to process CLI from a Stream (e.g. Serial)
+static void ot_cli_console_worker(void *context) {
+  ot_cli_console_t *cli = (ot_cli_console_t *)context;
+
+  // prints the prompt as first action
+  if (cli->prompt && cli->echoback) {
+    cli->cliStream->print(cli->prompt.c_str());
+  }
+  // manages and synchronizes the Stream flow with OpenThread CLI response
+  char lastReadChar;
+  char c = '\n';
+  while (true) {
+    if (cli->cliStream->available() > 0) {
+      lastReadChar = c;
+      c = cli->cliStream->read();
+      // if EOL is received, it may contain a combination of '\n'
+      // and/or '\r' depending on the Host OS and Terminal used.
+      // remove all leading '\r' '\n'
+      if (c == '\r') {
+        c = '\n';  // just mark it as New Line
+      }
+      if (c == '\n' && lastReadChar == '\n') {
+        continue;
+      }
+
+      // echo it back to the console
+      if (cli->echoback) {
+        if (c == '\n') {
+          cli->cliStream->println();  // follows whatever is defined as EOL in Arduino
+        } else {
+          cli->cliStream->write(c);
+        }
+      }
+      // send it to be processed by Open Thread CLI
+      OThreadCLI.write(c);
+      // if EOL, it shall wait for the command to be processed in background
+      if (c == '\n' && lastReadChar != '\n') {
+        // wait for the OpenThread CLI to finish processing the command
+        xTaskNotifyWait(0, 0, NULL, portMAX_DELAY);
+        // read response from OpenThread CLI and send it to the Stream
+        while (OThreadCLI.available() > 0) {
+          char c = OThreadCLI.read();
+          // echo it back to the console
+          if (cli->echoback) {
+            if (c == '\n') {
+              cli->cliStream->println();  // follows whatever is defined as EOL in Arduino
+            } else {
+              cli->cliStream->write(c);
+            }
+          }
+        }
+        // print the prompt
+        if (cli->prompt && cli->echoback) {
+          cli->cliStream->printf(cli->prompt.c_str());
+        }
+      }
+    }
+  }
+}
+
+void OpenThreadCLI::setEchoBack(bool echoback) {
+  otConsole.echoback = echoback;
+}
+
+void OpenThreadCLI::setPrompt(char *prompt) {
+  otConsole.prompt = prompt;  // NULL will make the prompt not visible
+}
+
+void OpenThreadCLI::setStream(Stream &otStream) {
+  otConsole.cliStream = &otStream;
+}
+
+void OpenThreadCLI::onReceive(OnReceiveCb_t func) {
+  otConsole.responseCallBack = func;  // NULL will set it off
+}
+
+// Stream object shall be already started and configured before calling this function
+void OpenThreadCLI::startConsole(Stream &otStream, bool echoback, const char *prompt) {
+  if (!otStarted) {
+    log_e("OpenThread CLI has not started. Please begin() it before starting the console.");
+    return;
+  }
+
+  if (s_console_cli_task == NULL) {
+    otConsole.cliStream = &otStream;
+    otConsole.echoback = echoback;
+    otConsole.prompt = prompt;  // NULL will invalidate the String
+    // it will run in the same priority (1) as the Arduino setup()/loop() task
+    xTaskCreate(ot_cli_console_worker, "ot_cli_console", 4096, &otConsole, 1, &s_console_cli_task);
+  } else {
+    log_w("A console is already running. Please stop it before starting a new one.");
+  }
+}
+
+void OpenThreadCLI::stopConsole() {
+  if (s_console_cli_task) {
+    vTaskDelete(s_console_cli_task);
+    s_console_cli_task = NULL;
+  }
+}
+
+OpenThreadCLI::OpenThreadCLI() {
+  memset(&ot_native_config, 0, sizeof(esp_openthread_platform_config_t));
+  ot_native_config.radio_config.radio_mode = RADIO_MODE_NATIVE;
+  ot_native_config.host_config.host_connection_mode = HOST_CONNECTION_MODE_NONE;
+  ot_native_config.port_config.storage_partition_name = "nvs";
+  ot_native_config.port_config.netif_queue_size = 10;
+  ot_native_config.port_config.task_queue_size = 10;
+  //sTxString = "";
+}
+
+OpenThreadCLI::~OpenThreadCLI() {
+  end();
+}
+
+OpenThreadCLI::operator bool() const {
+  return otStarted;
+}
+
+static void ot_task_worker(void *aContext) {
+  esp_vfs_eventfd_config_t eventfd_config = {
+    .max_fds = 3,
+  };
+  bool err = false;
+  if (ESP_OK != esp_event_loop_create_default()) {
+    log_e("Failed to create OpentThread event loop");
+    err = true;
+  }
+  if (!err && ESP_OK != esp_netif_init()) {
+    log_e("Failed to initialize OpentThread netif");
+    err = true;
+  }
+  if (!err && ESP_OK != esp_vfs_eventfd_register(&eventfd_config)) {
+    log_e("Failed to register OpentThread eventfd");
+    err = true;
+  }
+
+  // Initialize the OpenThread stack
+  if (!err && ESP_OK != esp_openthread_init(&ot_native_config)) {
+    log_e("Failed to initialize OpenThread stack");
+    err = true;
+  }
+  if (!err) {
+    // Initialize the OpenThread cli
+    otCliInit(esp_openthread_get_instance(), ot_cli_output_callback, NULL);
+
+    // Initialize the esp_netif bindings
+    esp_netif_config_t cfg = ESP_NETIF_DEFAULT_OPENTHREAD();
+    openthread_netif = esp_netif_new(&cfg);
+#if CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM
+    // Get LwIP Netif
+    if (openthread_netif != NULL) {
+      ot_lwip_netif = (struct netif *)esp_netif_get_netif_impl(openthread_netif);
+      if (ot_lwip_netif == NULL) {
+        log_e("Failed to get OpenThread LwIP netif");
+      }
+    }
+#endif
+  }
+  if (!err && openthread_netif == NULL) {
+    log_e("Failed to create OpenThread esp_netif");
+    err = true;
+  }
+  if (!err && ESP_OK != esp_netif_attach(openthread_netif, esp_openthread_netif_glue_init(&ot_native_config))) {
+    log_e("Failed to attach OpenThread esp_netif");
+    err = true;
+  }
+  if (!err && ESP_OK != esp_netif_set_default_netif(openthread_netif)) {
+    log_e("Failed to set default OpenThread esp_netif");
+    err = true;
+  }
+  if (!err) {
+    // only returns in case there is an OpenThread Stack failure...
+    esp_openthread_launch_mainloop();
+  }
+  // Clean up
+  esp_openthread_netif_glue_deinit();
+  esp_netif_destroy(openthread_netif);
+  esp_vfs_eventfd_unregister();
+  vTaskDelete(NULL);
+}
+
+void OpenThreadCLI::begin(bool OThreadAutoStart) {
+  if (otStarted) {
+    log_w("OpenThread CLI already started. Please end() it before starting again.");
+    return;
+  }
+
+  xTaskCreate(ot_task_worker, "ot_main_loop", 10240, NULL, 20, &s_ot_task);
+
+  //RX Buffer default has 1024 bytes if not preset
+  if (rx_queue == NULL) {
+    if (!setRxBufferSize(1024)) {
+      log_e("HW CDC RX Buffer error");
+    }
+  }
+  //TX Buffer default has 256 bytes if not preset
+  if (tx_queue == NULL) {
+    if (!setTxBufferSize(256)) {
+      log_e("HW CDC RX Buffer error");
+    }
+  }
+  xTaskCreate(ot_cli_loop, "ot_cli", 4096, xTaskGetCurrentTaskHandle(), 2, &s_cli_task);
+
+  // starts Thread with default dataset from NVS or from IDF default settings
+  if (OThreadAutoStart) {
+    otOperationalDatasetTlvs dataset;
+    otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset);
+    //    error = OT_ERROR_FAILED; // teste para forçar NULL dataset
+    if (error != OT_ERROR_NONE) {
+      log_i("Failed to get active NVS dataset from OpenThread");
+    } else {
+      log_i("Got active NVS dataset from OpenThread");
+    }
+    esp_err_t err = esp_openthread_auto_start((error == OT_ERROR_NONE) ? &dataset : NULL);
+    if (err != ESP_OK) {
+      log_i("Failed to AUTO start OpenThread");
+    } else {
+      log_i("AUTO start OpenThread done");
+    }
+  }
+  otStarted = true;
+  return;
+}
+
+void OpenThreadCLI::end() {
+  if (!otStarted) {
+    log_w("OpenThread CLI already stopped. Please begin() it before stopping again.");
+    return;
+  }
+  if (s_ot_task != NULL) {
+    vTaskDelete(s_ot_task);
+    // Clean up
+    esp_openthread_deinit();
+    esp_openthread_netif_glue_deinit();
+#if CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM
+    ot_lwip_netif = NULL;
+#endif
+    esp_netif_destroy(openthread_netif);
+    esp_vfs_eventfd_unregister();
+  }
+  if (s_cli_task != NULL) {
+    vTaskDelete(s_cli_task);
+  }
+  if (s_console_cli_task != NULL) {
+    vTaskDelete(s_console_cli_task);
+  }
+  esp_event_loop_delete_default();
+  setRxBufferSize(0);
+  setTxBufferSize(0);
+  otStarted = false;
+}
+
+size_t OpenThreadCLI::write(uint8_t c) {
+  if (tx_queue == NULL) {
+    return 0;
+  }
+  if (xQueueSend(tx_queue, &c, 0) != pdPASS) {
+    return 0;
+  }
+  return 1;
+}
+
+size_t OpenThreadCLI::setBuffer(QueueHandle_t &queue, size_t queue_len) {
+  if (queue) {
+    vQueueDelete(queue);
+    queue = NULL;
+  }
+  if (!queue_len) {
+    return 0;
+  }
+  queue = xQueueCreate(queue_len, sizeof(uint8_t));
+  if (!queue) {
+    return 0;
+  }
+  return queue_len;
+}
+
+size_t OpenThreadCLI::setTxBufferSize(size_t tx_queue_len) {
+  return setBuffer(tx_queue, tx_queue_len);
+}
+
+size_t OpenThreadCLI::setRxBufferSize(size_t rx_queue_len) {
+  return setBuffer(rx_queue, rx_queue_len);
+}
+
+int OpenThreadCLI::available(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  return uxQueueMessagesWaiting(rx_queue);
+}
+
+int OpenThreadCLI::peek(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c;
+  if (xQueuePeek(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+int OpenThreadCLI::read(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  if (xQueueReceive(rx_queue, &c, 0) == pdTRUE) {
+    return c;
+  }
+  return -1;
+}
+
+void OpenThreadCLI::flush() {
+  if (tx_queue == NULL) {
+    return;
+  }
+  // wait for the TX Queue to be empty
+  while (uxQueueMessagesWaiting(tx_queue));
+}
+
+OpenThreadCLI OThreadCLI;
+
+#endif /* CONFIG_OPENTHREAD_ENABLED */
+#endif /* SOC_IEEE802154_SUPPORTED */
diff --git a/libraries/OpenThread/src/OThreadCLI.h b/libraries/OpenThread/src/OThreadCLI.h
new file mode 100644
index 00000000000..bc8dc5d2b19
--- /dev/null
+++ b/libraries/OpenThread/src/OThreadCLI.h
@@ -0,0 +1,74 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_IEEE802154_SUPPORTED
+#if CONFIG_OPENTHREAD_ENABLED
+
+#include "esp_openthread.h"
+#include "esp_openthread_cli.h"
+#include "esp_openthread_lock.h"
+#include "esp_openthread_netif_glue.h"
+#include "esp_openthread_types.h"
+
+#include "openthread/cli.h"
+#include "openthread/instance.h"
+#include "openthread/logging.h"
+#include "openthread/tasklet.h"
+#include "openthread/dataset_ftd.h"
+
+#include "Arduino.h"
+
+typedef std::function<void(void)> OnReceiveCb_t;
+
+class OpenThreadCLI : public Stream {
+private:
+  static size_t setBuffer(QueueHandle_t &queue, size_t len);
+  bool otStarted = false;
+
+public:
+  OpenThreadCLI();
+  ~OpenThreadCLI();
+  // returns true if OpenThread CLI is running
+  operator bool() const;
+
+  // starts a task to read/write otStream. Default prompt is "ot> ". Set it to NULL to make it invisible.
+  void startConsole(Stream &otStream, bool echoback = true, const char *prompt = "ot> ");
+  void stopConsole();
+  void setPrompt(char *prompt);        // changes the console prompt. NULL is an empty prompt.
+  void setEchoBack(bool echoback);     // changes the console echoback option
+  void setStream(Stream &otStream);    // changes the console Stream object
+  void onReceive(OnReceiveCb_t func);  // called on a complete line of output from OT CLI, as OT Response
+
+  void begin(bool OThreadAutoStart = true);
+  void end();
+
+  // default size is 256 bytes
+  size_t setTxBufferSize(size_t tx_queue_len);
+  // default size is 1024 bytes
+  size_t setRxBufferSize(size_t rx_queue_len);
+
+  size_t write(uint8_t);
+  int available();
+  int read();
+  int peek();
+  void flush();
+};
+
+extern OpenThreadCLI OThreadCLI;
+
+#endif /* CONFIG_OPENTHREAD_ENABLED */
+#endif /* SOC_IEEE802154_SUPPORTED */
diff --git a/libraries/OpenThread/src/OThreadCLI_Util.cpp b/libraries/OpenThread/src/OThreadCLI_Util.cpp
new file mode 100644
index 00000000000..d21daa1effc
--- /dev/null
+++ b/libraries/OpenThread/src/OThreadCLI_Util.cpp
@@ -0,0 +1,212 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "OThreadCLI.h"
+#if SOC_IEEE802154_SUPPORTED
+#if CONFIG_OPENTHREAD_ENABLED
+
+#include "OThreadCLI_Util.h"
+#include <StreamString.h>
+
+static const char *otRoleString[] = {
+  "Disabled",  ///< The Thread stack is disabled.
+  "Detached",  ///< Not currently participating in a Thread network/partition.
+  "Child",     ///< The Thread Child role.
+  "Router",    ///< The Thread Router role.
+  "Leader",    ///< The Thread Leader role.
+};
+
+ot_device_role_t otGetDeviceRole() {
+  if (!OThreadCLI) {
+    return OT_ROLE_DISABLED;
+  }
+  otInstance *instance = esp_openthread_get_instance();
+  return (ot_device_role_t)otThreadGetDeviceRole(instance);
+}
+
+const char *otGetStringDeviceRole() {
+  return otRoleString[otGetDeviceRole()];
+}
+
+bool otGetRespCmd(const char *cmd, char *resp, uint32_t respTimeout) {
+  if (!OThreadCLI) {
+    return false;
+  }
+  StreamString cliRespAllLines;
+  char cliResp[256] = {0};
+  if (resp != NULL) {
+    *resp = '\0';
+  }
+  if (cmd == NULL) {
+    return true;
+  }
+  OThreadCLI.println(cmd);
+  log_d("CMD[%s]", cmd);
+  uint32_t timeout = millis() + respTimeout;
+  while (millis() < timeout) {
+    size_t len = OThreadCLI.readBytesUntil('\n', cliResp, sizeof(cliResp));
+    // clip it on EOL
+    for (int i = 0; i < len; i++) {
+      if (cliResp[i] == '\r' || cliResp[i] == '\n') {
+        cliResp[i] = '\0';
+      }
+    }
+    log_d("Resp[%s]", cliResp);
+    if (strncmp(cliResp, "Done", 4) && strncmp(cliResp, "Error", 4)) {
+      cliRespAllLines += cliResp;
+      cliRespAllLines.println();  // Adds whatever EOL is for the OS
+    } else {
+      break;
+    }
+  }
+  if (!strncmp(cliResp, "Error", 4) || millis() > timeout) {
+    return false;
+  }
+  if (resp != NULL) {
+    strcpy(resp, cliRespAllLines.c_str());
+  }
+  return true;
+}
+
+bool otExecCommand(const char *cmd, const char *arg, ot_cmd_return_t *returnCode) {
+  if (!OThreadCLI) {
+    return false;
+  }
+  char cliResp[256] = {0};
+  if (cmd == NULL) {
+    return true;
+  }
+  if (arg == NULL) {
+    OThreadCLI.println(cmd);
+  } else {
+    OThreadCLI.print(cmd);
+    OThreadCLI.print(" ");
+    OThreadCLI.println(arg);
+  }
+  size_t len = OThreadCLI.readBytesUntil('\n', cliResp, sizeof(cliResp));
+  // clip it on EOL
+  for (int i = 0; i < len; i++) {
+    if (cliResp[i] == '\r' || cliResp[i] == '\n') {
+      cliResp[i] = '\0';
+    }
+  }
+  log_d("CMD[%s %s] Resp[%s]", cmd, arg, cliResp);
+  // initial returnCode is success values
+  if (returnCode) {
+    returnCode->errorCode = 0;
+    returnCode->errorMessage = "Done";
+  }
+  if (!strncmp(cliResp, "Done", 4)) {
+    return true;
+  } else {
+    if (returnCode) {
+      // initial setting is a bad error message or it is something else...
+      // return -1 and the full returned message
+      returnCode->errorCode = -1;
+      returnCode->errorMessage = cliResp;
+      // parse cliResp looking for errorCode and errorMessage
+      // OT CLI error message format is "Error ##: msg\n" - Example:
+      //Error 35: InvalidCommand
+      //Error 7: InvalidArgs
+      char *i = cliResp;
+      char *m = cliResp;
+      while (*i && *i != ':') {
+        i++;
+      }
+      if (*i) {
+        *i = '\0';
+        m = i + 2;  // message is 2 characters after ':'
+        while (i > cliResp && *i != ' ') {
+          i--;  // search for ' ' before ":'
+        }
+        if (*i == ' ') {
+          i++;  // move it forward to the number beginning
+          returnCode->errorCode = atoi(i);
+          returnCode->errorMessage = m;
+        }  // otherwise, it will keep the "bad error message" information
+      }  // otherwise, it will keep the "bad error message" information
+    }  // returnCode is NULL pointer
+    return false;
+  }
+}
+
+bool otPrintRespCLI(const char *cmd, Stream &output, uint32_t respTimeout) {
+  char cliResp[256] = {0};
+  if (cmd == NULL) {
+    return true;
+  }
+  OThreadCLI.println(cmd);
+  uint32_t timeout = millis() + respTimeout;
+  while (millis() < timeout) {
+    size_t len = OThreadCLI.readBytesUntil('\n', cliResp, sizeof(cliResp));
+    if (cliResp[0] == '\0') {
+      // Straem has timed out and it should try again using parameter respTimeout
+      continue;
+    }
+    // clip it on EOL
+    for (int i = 0; i < len; i++) {
+      if (cliResp[i] == '\r' || cliResp[i] == '\n') {
+        cliResp[i] = '\0';
+      }
+    }
+    if (strncmp(cliResp, "Done", 4) && strncmp(cliResp, "Error", 4)) {
+      output.println(cliResp);
+      memset(cliResp, 0, sizeof(cliResp));
+      timeout = millis() + respTimeout;  // renew timeout, line per line
+    } else {
+      break;
+    }
+  }
+  if (!strncmp(cliResp, "Error", 4) || millis() > timeout) {
+    return false;
+  }
+  return true;
+}
+
+void otPrintNetworkInformation(Stream &output) {
+  if (!OThreadCLI) {
+    return;
+  }
+  char resp[512];
+  output.println("Thread Setup:");
+  if (otGetRespCmd("state", resp)) {
+    output.printf("Node State: \t%s", resp);
+  }
+  if (otGetRespCmd("networkname", resp)) {
+    output.printf("Network Name: \t%s", resp);
+  }
+  if (otGetRespCmd("channel", resp)) {
+    output.printf("Channel: \t%s", resp);
+  }
+  if (otGetRespCmd("panid", resp)) {
+    output.printf("Pan ID: \t%s", resp);
+  }
+  if (otGetRespCmd("extpanid", resp)) {
+    output.printf("Ext Pan ID: \t%s", resp);
+  }
+  if (otGetRespCmd("networkkey", resp)) {
+    output.printf("Network Key: \t%s", resp);
+  }
+  if (otGetRespCmd("ipaddr", resp)) {
+    output.println("Node IP Addresses are:");
+    output.printf("%s", resp);
+  }
+  if (otGetRespCmd("ipmaddr", resp)) {
+    output.println("Node Multicast Addresses are:");
+    output.printf("%s", resp);
+  }
+}
+
+#endif /* CONFIG_OPENTHREAD_ENABLED */
+#endif /* SOC_IEEE802154_SUPPORTED */
diff --git a/libraries/OpenThread/src/OThreadCLI_Util.h b/libraries/OpenThread/src/OThreadCLI_Util.h
new file mode 100644
index 00000000000..1ab2e061dfc
--- /dev/null
+++ b/libraries/OpenThread/src/OThreadCLI_Util.h
@@ -0,0 +1,42 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_IEEE802154_SUPPORTED
+#if CONFIG_OPENTHREAD_ENABLED
+
+typedef enum {
+  OT_ROLE_DISABLED = 0,  ///< The Thread stack is disabled.
+  OT_ROLE_DETACHED = 1,  ///< Not currently participating in a Thread network/partition.
+  OT_ROLE_CHILD = 2,     ///< The Thread Child role.
+  OT_ROLE_ROUTER = 3,    ///< The Thread Router role.
+  OT_ROLE_LEADER = 4,    ///< The Thread Leader role.
+} ot_device_role_t;
+
+typedef struct {
+  int errorCode;
+  String errorMessage;
+} ot_cmd_return_t;
+
+ot_device_role_t otGetDeviceRole();
+const char *otGetStringDeviceRole();
+bool otGetRespCmd(const char *cmd, char *resp = NULL, uint32_t respTimeout = 5000);
+bool otExecCommand(const char *cmd, const char *arg, ot_cmd_return_t *returnCode = NULL);
+bool otPrintRespCLI(const char *cmd, Stream &output, uint32_t respTimeout);
+void otPrintNetworkInformation(Stream &output);
+
+#endif /* CONFIG_OPENTHREAD_ENABLED */
+#endif /* SOC_IEEE802154_SUPPORTED */
diff --git a/libraries/PPP/examples/PPP_Basic/PPP_Basic.ino b/libraries/PPP/examples/PPP_Basic/PPP_Basic.ino
new file mode 100644
index 00000000000..1b5776d18ed
--- /dev/null
+++ b/libraries/PPP/examples/PPP_Basic/PPP_Basic.ino
@@ -0,0 +1,128 @@
+#include <PPP.h>
+
+#define PPP_MODEM_APN "internet"
+#define PPP_MODEM_PIN "0000"  // or NULL
+
+// WaveShare SIM7600 HW Flow Control
+#define PPP_MODEM_RST       25
+#define PPP_MODEM_RST_LOW   false  //active HIGH
+#define PPP_MODEM_RST_DELAY 200
+#define PPP_MODEM_TX        21
+#define PPP_MODEM_RX        22
+#define PPP_MODEM_RTS       26
+#define PPP_MODEM_CTS       27
+#define PPP_MODEM_FC        ESP_MODEM_FLOW_CONTROL_HW
+#define PPP_MODEM_MODEL     PPP_MODEM_SIM7600
+
+// SIM800 basic module with just TX,RX and RST
+// #define PPP_MODEM_RST     0
+// #define PPP_MODEM_RST_LOW true //active LOW
+// #define PPP_MODEM_TX      2
+// #define PPP_MODEM_RX      19
+// #define PPP_MODEM_RTS     -1
+// #define PPP_MODEM_CTS     -1
+// #define PPP_MODEM_FC      ESP_MODEM_FLOW_CONTROL_NONE
+// #define PPP_MODEM_MODEL   PPP_MODEM_SIM800
+
+void onEvent(arduino_event_id_t event, arduino_event_info_t info) {
+  switch (event) {
+    case ARDUINO_EVENT_PPP_START:        Serial.println("PPP Started"); break;
+    case ARDUINO_EVENT_PPP_CONNECTED:    Serial.println("PPP Connected"); break;
+    case ARDUINO_EVENT_PPP_GOT_IP:       Serial.println("PPP Got IP"); break;
+    case ARDUINO_EVENT_PPP_LOST_IP:      Serial.println("PPP Lost IP"); break;
+    case ARDUINO_EVENT_PPP_DISCONNECTED: Serial.println("PPP Disconnected"); break;
+    case ARDUINO_EVENT_PPP_STOP:         Serial.println("PPP Stopped"); break;
+    default:                             break;
+  }
+}
+
+void testClient(const char *host, uint16_t port) {
+  NetworkClient client;
+  if (!client.connect(host, port)) {
+    Serial.println("Connection Failed");
+    return;
+  }
+  client.printf("GET / HTTP/1.1\r\nHost: %s\r\n\r\n", host);
+  while (client.connected() && !client.available());
+  while (client.available()) {
+    client.read();  //Serial.write(client.read());
+  }
+
+  Serial.println("Connection Success");
+  client.stop();
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  // Listen for modem events
+  Network.onEvent(onEvent);
+
+  // Configure the modem
+  PPP.setApn(PPP_MODEM_APN);
+  PPP.setPin(PPP_MODEM_PIN);
+  PPP.setResetPin(PPP_MODEM_RST, PPP_MODEM_RST_LOW, PPP_MODEM_RST_DELAY);
+  PPP.setPins(PPP_MODEM_TX, PPP_MODEM_RX, PPP_MODEM_RTS, PPP_MODEM_CTS, PPP_MODEM_FC);
+
+  Serial.println("Starting the modem. It might take a while!");
+  PPP.begin(PPP_MODEM_MODEL);
+
+  Serial.print("Manufacturer: ");
+  Serial.println(PPP.cmd("AT+CGMI", 10000));
+  Serial.print("Model: ");
+  Serial.println(PPP.moduleName());
+  Serial.print("IMEI: ");
+  Serial.println(PPP.IMEI());
+
+  bool attached = PPP.attached();
+  if (!attached) {
+    int i = 0;
+    unsigned int s = millis();
+    Serial.print("Waiting to connect to network");
+    while (!attached && ((++i) < 600)) {
+      Serial.print(".");
+      delay(100);
+      attached = PPP.attached();
+    }
+    Serial.print((millis() - s) / 1000.0, 1);
+    Serial.println("s");
+    attached = PPP.attached();
+  }
+
+  Serial.print("Attached: ");
+  Serial.println(attached);
+  Serial.print("State: ");
+  Serial.println(PPP.radioState());
+  if (attached) {
+    Serial.print("Operator: ");
+    Serial.println(PPP.operatorName());
+    Serial.print("IMSI: ");
+    Serial.println(PPP.IMSI());
+    Serial.print("RSSI: ");
+    Serial.println(PPP.RSSI());
+    int ber = PPP.BER();
+    if (ber > 0) {
+      Serial.print("BER: ");
+      Serial.println(ber);
+      Serial.print("NetMode: ");
+      Serial.println(PPP.networkMode());
+    }
+
+    Serial.println("Switching to data mode...");
+    PPP.mode(ESP_MODEM_MODE_CMUX);  // Data and Command mixed mode
+    if (!PPP.waitStatusBits(ESP_NETIF_CONNECTED_BIT, 1000)) {
+      Serial.println("Failed to connect to internet!");
+    } else {
+      Serial.println("Connected to internet!");
+    }
+  } else {
+    Serial.println("Failed to connect to network!");
+  }
+}
+
+void loop() {
+  if (PPP.connected()) {
+    testClient("google.com", 80);
+  }
+  delay(20000);
+}
diff --git a/libraries/PPP/examples/PPP_Basic/ci.json b/libraries/PPP/examples/PPP_Basic/ci.json
new file mode 100644
index 00000000000..314587edcf6
--- /dev/null
+++ b/libraries/PPP/examples/PPP_Basic/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_LWIP_PPP_SUPPORT=y"
+  ]
+}
diff --git a/libraries/PPP/examples/PPP_WIFI_BRIDGE/PPP_WIFI_BRIDGE.ino b/libraries/PPP/examples/PPP_WIFI_BRIDGE/PPP_WIFI_BRIDGE.ino
new file mode 100644
index 00000000000..1e3f9f9bb98
--- /dev/null
+++ b/libraries/PPP/examples/PPP_WIFI_BRIDGE/PPP_WIFI_BRIDGE.ino
@@ -0,0 +1,153 @@
+#include <PPP.h>
+#include <WiFi.h>
+
+#define PPP_MODEM_APN "internet"
+#define PPP_MODEM_PIN "0000"  // or NULL
+
+// WaveShare SIM7600 HW Flow Control
+#define PPP_MODEM_RST       25
+#define PPP_MODEM_RST_LOW   false  //active HIGH
+#define PPP_MODEM_RST_DELAY 200
+#define PPP_MODEM_TX        21
+#define PPP_MODEM_RX        22
+#define PPP_MODEM_RTS       26
+#define PPP_MODEM_CTS       27
+#define PPP_MODEM_FC        ESP_MODEM_FLOW_CONTROL_HW
+#define PPP_MODEM_MODEL     PPP_MODEM_SIM7600
+
+// SIM800 basic module with just TX,RX and RST
+// #define PPP_MODEM_RST     0
+// #define PPP_MODEM_RST_LOW true //active LOW
+// #define PPP_MODEM_TX      2
+// #define PPP_MODEM_RX      19
+// #define PPP_MODEM_RTS     -1
+// #define PPP_MODEM_CTS     -1
+// #define PPP_MODEM_FC      ESP_MODEM_FLOW_CONTROL_NONE
+// #define PPP_MODEM_MODEL   PPP_MODEM_SIM800
+
+// WiFi Access Point Config
+#define AP_SSID "ESP32-ETH-WIFI-BRIDGE"
+#define AP_PASS "password"
+
+IPAddress ap_ip(192, 168, 4, 1);
+IPAddress ap_mask(255, 255, 255, 0);
+IPAddress ap_leaseStart(192, 168, 4, 2);
+IPAddress ap_dns(8, 8, 4, 4);
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+
+  // Listen for modem events
+  Network.onEvent(onEvent);
+
+  // Start the Access Point
+  WiFi.AP.begin();
+  WiFi.AP.config(ap_ip, ap_ip, ap_mask, ap_leaseStart, ap_dns);
+  WiFi.AP.create(AP_SSID, AP_PASS);
+  if (!WiFi.AP.waitStatusBits(ESP_NETIF_STARTED_BIT, 1000)) {
+    Serial.println("Failed to start AP!");
+    return;
+  }
+
+  // Configure the modem
+  PPP.setApn(PPP_MODEM_APN);
+  PPP.setPin(PPP_MODEM_PIN);
+  PPP.setResetPin(PPP_MODEM_RST, PPP_MODEM_RST_LOW, PPP_MODEM_RST_DELAY);
+  PPP.setPins(PPP_MODEM_TX, PPP_MODEM_RX, PPP_MODEM_RTS, PPP_MODEM_CTS, PPP_MODEM_FC);
+
+  Serial.println("Starting the modem. It might take a while!");
+  PPP.begin(PPP_MODEM_MODEL);
+
+  Serial.print("Manufacturer: ");
+  Serial.println(PPP.cmd("AT+CGMI", 10000));
+  Serial.print("Model: ");
+  Serial.println(PPP.moduleName());
+  Serial.print("IMEI: ");
+  Serial.println(PPP.IMEI());
+
+  bool attached = PPP.attached();
+  if (!attached) {
+    int i = 0;
+    unsigned int s = millis();
+    Serial.print("Waiting to connect to network");
+    while (!attached && ((++i) < 600)) {
+      Serial.print(".");
+      delay(100);
+      attached = PPP.attached();
+    }
+    Serial.print((millis() - s) / 1000.0, 1);
+    Serial.println("s");
+    attached = PPP.attached();
+  }
+
+  Serial.print("Attached: ");
+  Serial.println(attached);
+  Serial.print("State: ");
+  Serial.println(PPP.radioState());
+  if (attached) {
+    Serial.print("Operator: ");
+    Serial.println(PPP.operatorName());
+    Serial.print("IMSI: ");
+    Serial.println(PPP.IMSI());
+    Serial.print("RSSI: ");
+    Serial.println(PPP.RSSI());
+    int ber = PPP.BER();
+    if (ber > 0) {
+      Serial.print("BER: ");
+      Serial.println(ber);
+      Serial.print("NetMode: ");
+      Serial.println(PPP.networkMode());
+    }
+
+    Serial.println("Switching to data mode...");
+    PPP.mode(ESP_MODEM_MODE_CMUX);  // Data and Command mixed mode
+    if (!PPP.waitStatusBits(ESP_NETIF_CONNECTED_BIT, 1000)) {
+      Serial.println("Failed to connect to internet!");
+    } else {
+      Serial.println("Connected to internet!");
+    }
+  } else {
+    Serial.println("Failed to connect to network!");
+  }
+}
+
+void loop() {
+  delay(20000);
+}
+
+void onEvent(arduino_event_id_t event, arduino_event_info_t info) {
+  switch (event) {
+    case ARDUINO_EVENT_PPP_START:     Serial.println("PPP Started"); break;
+    case ARDUINO_EVENT_PPP_CONNECTED: Serial.println("PPP Connected"); break;
+    case ARDUINO_EVENT_PPP_GOT_IP:
+      Serial.println("PPP Got IP");
+      Serial.println(PPP);
+      WiFi.AP.enableNAPT(true);
+      break;
+    case ARDUINO_EVENT_PPP_LOST_IP:
+      Serial.println("PPP Lost IP");
+      WiFi.AP.enableNAPT(false);
+      break;
+    case ARDUINO_EVENT_PPP_DISCONNECTED:
+      Serial.println("PPP Disconnected");
+      WiFi.AP.enableNAPT(false);
+      break;
+    case ARDUINO_EVENT_PPP_STOP: Serial.println("PPP Stopped"); break;
+
+    case ARDUINO_EVENT_WIFI_AP_START:
+      Serial.println("AP Started");
+      Serial.println(WiFi.AP);
+      break;
+    case ARDUINO_EVENT_WIFI_AP_STACONNECTED:    Serial.println("AP STA Connected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STADISCONNECTED: Serial.println("AP STA Disconnected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED:
+      Serial.print("AP STA IP Assigned: ");
+      Serial.println(IPAddress(info.wifi_ap_staipassigned.ip.addr));
+      break;
+    case ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED: Serial.println("AP Probe Request Received"); break;
+    case ARDUINO_EVENT_WIFI_AP_STOP:           Serial.println("AP Stopped"); break;
+
+    default: break;
+  }
+}
diff --git a/libraries/PPP/examples/PPP_WIFI_BRIDGE/ci.json b/libraries/PPP/examples/PPP_WIFI_BRIDGE/ci.json
new file mode 100644
index 00000000000..ccc62161c85
--- /dev/null
+++ b/libraries/PPP/examples/PPP_WIFI_BRIDGE/ci.json
@@ -0,0 +1,9 @@
+{
+  "requires": [
+    "CONFIG_LWIP_PPP_SUPPORT=y"
+  ],
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/PPP/library.properties b/libraries/PPP/library.properties
new file mode 100644
index 00000000000..7158a027b0a
--- /dev/null
+++ b/libraries/PPP/library.properties
@@ -0,0 +1,9 @@
+name=PPP
+version=3.2.0
+author=Hristo Gochkov
+maintainer=Hristo Gochkov <hristo@espressif.com>
+sentence=Enables network connection using GSM Modem.
+paragraph=With this library you can instantiate Servers, Clients and send/receive UDP packets through GSM Modem.
+category=Communication
+url=
+architectures=esp32
diff --git a/libraries/PPP/src/PPP.cpp b/libraries/PPP/src/PPP.cpp
new file mode 100644
index 00000000000..87fee6920c3
--- /dev/null
+++ b/libraries/PPP/src/PPP.cpp
@@ -0,0 +1,763 @@
+#define ARDUINO_CORE_BUILD
+#include "PPP.h"
+#if CONFIG_LWIP_PPP_SUPPORT && ARDUINO_HAS_ESP_MODEM
+#include "esp32-hal-periman.h"
+#include "esp_netif.h"
+#include "esp_netif_ppp.h"
+#include <string>
+#include "driver/uart.h"
+#include "hal/uart_ll.h"
+#include "esp_private/uart_share_hw_ctrl.h"
+
+#define PPP_CMD_MODE_CHECK(x)                                    \
+  if (_dce == NULL) {                                            \
+    return x;                                                    \
+  }                                                              \
+  if (_mode == ESP_MODEM_MODE_DATA) {                            \
+    log_e("Wrong modem mode. Should be ESP_MODEM_MODE_COMMAND"); \
+    return x;                                                    \
+  }
+
+typedef struct {
+  void *arg;
+} PdpContext;
+#include "esp_modem_api.h"
+
+// Because of how esp_modem functions are declared, we need to workaround some APIs that take strings as input (output works OK)
+// Following APIs work only when called through this interface
+extern "C" {
+esp_err_t _esp_modem_at(esp_modem_dce_t *dce_wrap, const char *at, char *p_out, int timeout);
+esp_err_t _esp_modem_at_raw(esp_modem_dce_t *dce_wrap, const char *cmd, char *p_out, const char *pass, const char *fail, int timeout);
+esp_err_t _esp_modem_send_sms(esp_modem_dce_t *dce_wrap, const char *number, const char *message);
+esp_err_t _esp_modem_set_pin(esp_modem_dce_t *dce_wrap, const char *pin);
+esp_err_t _esp_modem_set_operator(esp_modem_dce_t *dce_wrap, int mode, int format, const char *oper);
+esp_err_t _esp_modem_set_network_bands(esp_modem_dce_t *dce_wrap, const char *mode, const int *bands, int size);
+};
+
+static PPPClass *_esp_modem = NULL;
+static esp_event_handler_instance_t _ppp_ev_instance = NULL;
+
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+static const char *_ppp_event_name(int32_t event_id) {
+  switch (event_id) {
+    case NETIF_PPP_ERRORNONE:          return "No error.";
+    case NETIF_PPP_ERRORPARAM:         return "Invalid parameter.";
+    case NETIF_PPP_ERROROPEN:          return "Unable to open PPP session.";
+    case NETIF_PPP_ERRORDEVICE:        return "Invalid I/O device for PPP.";
+    case NETIF_PPP_ERRORALLOC:         return "Unable to allocate resources.";
+    case NETIF_PPP_ERRORUSER:          return "User interrupt.";
+    case NETIF_PPP_ERRORCONNECT:       return "Connection lost.";
+    case NETIF_PPP_ERRORAUTHFAIL:      return "Failed authentication challenge.";
+    case NETIF_PPP_ERRORPROTOCOL:      return "Failed to meet protocol.";
+    case NETIF_PPP_ERRORPEERDEAD:      return "Connection timeout";
+    case NETIF_PPP_ERRORIDLETIMEOUT:   return "Idle Timeout";
+    case NETIF_PPP_ERRORCONNECTTIME:   return "Max connect time reached";
+    case NETIF_PPP_ERRORLOOPBACK:      return "Loopback detected";
+    case NETIF_PPP_PHASE_DEAD:         return "Phase Dead";
+    case NETIF_PPP_PHASE_MASTER:       return "Phase Master";
+    case NETIF_PPP_PHASE_HOLDOFF:      return "Phase Hold Off";
+    case NETIF_PPP_PHASE_INITIALIZE:   return "Phase Initialize";
+    case NETIF_PPP_PHASE_SERIALCONN:   return "Phase Serial Conn";
+    case NETIF_PPP_PHASE_DORMANT:      return "Phase Dormant";
+    case NETIF_PPP_PHASE_ESTABLISH:    return "Phase Establish";
+    case NETIF_PPP_PHASE_AUTHENTICATE: return "Phase Authenticate";
+    case NETIF_PPP_PHASE_CALLBACK:     return "Phase Callback";
+    case NETIF_PPP_PHASE_NETWORK:      return "Phase Network";
+    case NETIF_PPP_PHASE_RUNNING:      return "Phase Running";
+    case NETIF_PPP_PHASE_TERMINATE:    return "Phase Terminate";
+    case NETIF_PPP_PHASE_DISCONNECT:   return "Phase Disconnect";
+    case NETIF_PPP_CONNECT_FAILED:     return "Connect Failed";
+    default:                           break;
+  }
+  return "UNKNOWN";
+}
+
+static const char *_ppp_terminal_error_name(esp_modem_terminal_error_t err) {
+  switch (err) {
+    case ESP_MODEM_TERMINAL_BUFFER_OVERFLOW:         return "Buffer Overflow";
+    case ESP_MODEM_TERMINAL_CHECKSUM_ERROR:          return "Checksum Error";
+    case ESP_MODEM_TERMINAL_UNEXPECTED_CONTROL_FLOW: return "Unexpected Control Flow";
+    case ESP_MODEM_TERMINAL_DEVICE_GONE:             return "Device Gone";
+    case ESP_MODEM_TERMINAL_UNKNOWN_ERROR:           return "Unknown Error";
+    default:                                         break;
+  }
+  return "UNKNOWN";
+}
+#endif
+
+static void _ppp_event_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == NETIF_PPP_STATUS) {
+    if (_esp_modem != NULL) {
+      _esp_modem->_onPppEvent(event_id, event_data);
+    }
+  }
+}
+
+static void onPppArduinoEvent(arduino_event_id_t event, arduino_event_info_t info) {
+  if (event >= ARDUINO_EVENT_PPP_START && event <= ARDUINO_EVENT_PPP_GOT_IP6) {
+    _esp_modem->_onPppArduinoEvent(event, info);
+  }
+}
+
+// PPP Error Callback
+static void _ppp_error_cb(esp_modem_terminal_error_t err) {
+  log_v("PPP Driver Error %ld: %s", err, _ppp_terminal_error_name(err));
+}
+
+// PPP Arduino Events Callback
+void PPPClass::_onPppArduinoEvent(arduino_event_id_t event, arduino_event_info_t info) {
+  log_v("PPP Arduino Event %ld: %s", event, Network.eventName(event));
+  // if(event == ARDUINO_EVENT_PPP_GOT_IP){
+  //     if((getStatusBits() & ESP_NETIF_CONNECTED_BIT) == 0){
+  //         setStatusBits(ESP_NETIF_CONNECTED_BIT);
+  //         arduino_event_t arduino_event;
+  //         arduino_event.event_id = ARDUINO_EVENT_PPP_CONNECTED;
+  //         Network.postEvent(&arduino_event);
+  //     }
+  // } else
+  if (event == ARDUINO_EVENT_PPP_LOST_IP) {
+    if ((getStatusBits() & ESP_NETIF_CONNECTED_BIT) != 0) {
+      clearStatusBits(ESP_NETIF_CONNECTED_BIT);
+      arduino_event_t arduino_event;
+      arduino_event.event_id = ARDUINO_EVENT_PPP_DISCONNECTED;
+      Network.postEvent(&arduino_event);
+    }
+  }
+}
+
+// PPP Driver Events Callback
+void PPPClass::_onPppEvent(int32_t event, void *event_data) {
+  arduino_event_t arduino_event;
+  arduino_event.event_id = ARDUINO_EVENT_MAX;
+
+  log_v("PPP Driver Event %ld: %s", event, _ppp_event_name(event));
+
+  if (event == NETIF_PPP_ERRORNONE) {
+    if ((getStatusBits() & ESP_NETIF_CONNECTED_BIT) == 0) {
+      setStatusBits(ESP_NETIF_CONNECTED_BIT);
+      arduino_event_t arduino_event;
+      arduino_event.event_id = ARDUINO_EVENT_PPP_CONNECTED;
+      Network.postEvent(&arduino_event);
+    }
+  }
+
+  if (arduino_event.event_id < ARDUINO_EVENT_MAX) {
+    Network.postEvent(&arduino_event);
+  }
+}
+
+esp_modem_dce_t *PPPClass::handle() const {
+  return _dce;
+}
+
+PPPClass::PPPClass()
+  : _dce(NULL), _pin_tx(-1), _pin_rx(-1), _pin_rts(-1), _pin_cts(-1), _flow_ctrl(ESP_MODEM_FLOW_CONTROL_NONE), _pin_rst(-1), _pin_rst_act_low(true),
+    _pin_rst_delay(200), _pin(NULL), _apn(NULL), _rx_buffer_size(4096), _tx_buffer_size(512), _mode(ESP_MODEM_MODE_COMMAND), _uart_num(UART_NUM_1),
+    _ppp_event_handle(0) {}
+
+PPPClass::~PPPClass() {}
+
+bool PPPClass::pppDetachBus(void *bus_pointer) {
+  PPPClass *bus = (PPPClass *)bus_pointer;
+  bus->end();
+  return true;
+}
+
+void PPPClass::setResetPin(int8_t rst, bool active_low, uint32_t reset_delay) {
+  _pin_rst = digitalPinToGPIONumber(rst);
+  _pin_rst_act_low = active_low;
+  _pin_rst_delay = reset_delay;
+}
+
+bool PPPClass::setPins(int8_t tx, int8_t rx, int8_t rts, int8_t cts, esp_modem_flow_ctrl_t flow_ctrl) {
+  perimanSetBusDeinit(ESP32_BUS_TYPE_PPP_TX, PPPClass::pppDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_PPP_RX, PPPClass::pppDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_PPP_RTS, PPPClass::pppDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_PPP_CTS, PPPClass::pppDetachBus);
+
+  if (_pin_tx >= 0) {
+    if (!perimanClearPinBus(_pin_tx)) {
+      return false;
+    }
+  }
+  if (_pin_rx >= 0) {
+    if (!perimanClearPinBus(_pin_rx)) {
+      return false;
+    }
+  }
+  if (_pin_rts >= 0) {
+    if (!perimanClearPinBus(_pin_rts)) {
+      return false;
+    }
+  }
+  if (_pin_cts >= 0) {
+    if (!perimanClearPinBus(_pin_cts)) {
+      return false;
+    }
+  }
+
+  _flow_ctrl = flow_ctrl;
+  _pin_tx = digitalPinToGPIONumber(tx);
+  _pin_rx = digitalPinToGPIONumber(rx);
+  _pin_rts = digitalPinToGPIONumber(rts);
+  _pin_cts = digitalPinToGPIONumber(cts);
+
+  if (_pin_tx >= 0) {
+    if (!perimanSetPinBus(_pin_tx, ESP32_BUS_TYPE_PPP_TX, (void *)(this), -1, -1)) {
+      return false;
+    }
+  }
+  if (_pin_rx >= 0) {
+    if (!perimanSetPinBus(_pin_rx, ESP32_BUS_TYPE_PPP_RX, (void *)(this), -1, -1)) {
+      return false;
+    }
+  }
+  if (_pin_rts >= 0) {
+    if (!perimanSetPinBus(_pin_rts, ESP32_BUS_TYPE_PPP_RTS, (void *)(this), -1, -1)) {
+      return false;
+    }
+  }
+  if (_pin_cts >= 0) {
+    if (!perimanSetPinBus(_pin_cts, ESP32_BUS_TYPE_PPP_CTS, (void *)(this), -1, -1)) {
+      return false;
+    }
+  }
+  return true;
+}
+
+bool PPPClass::begin(ppp_modem_model_t model, uint8_t uart_num, int baud_rate) {
+  esp_err_t ret = ESP_OK;
+  bool pin_ok = false;
+  int tries = 0;
+
+  if (_esp_netif != NULL || _dce != NULL) {
+    log_w("PPP Already Started");
+    return true;
+  }
+
+  if (_apn == NULL) {
+    log_e("APN is not set. Call 'PPP.setApn()' first");
+    return false;
+  }
+
+  if (_pin_tx < 0 || _pin_rx < 0) {
+    log_e("UART pins not set. Call 'PPP.setPins()' first");
+    return false;
+  }
+
+  if ((_pin_rts < 0 || _pin_cts < 0) && (_flow_ctrl != ESP_MODEM_FLOW_CONTROL_NONE)) {
+    log_e("UART CTS/RTS pins not set, but flow control is enabled!");
+    return false;
+  }
+
+  _uart_num = uart_num;
+  _esp_modem = this;
+
+  Network.begin();
+
+  /* Listen for PPP status events */
+  if (_ppp_ev_instance == NULL && esp_event_handler_instance_register(NETIF_PPP_STATUS, ESP_EVENT_ANY_ID, &_ppp_event_cb, NULL, &_ppp_ev_instance)) {
+    log_e("event_handler_instance_register for NETIF_PPP_STATUS Failed!");
+    return false;
+  }
+
+  /* Configure the PPP netif */
+  esp_netif_config_t cfg = ESP_NETIF_DEFAULT_PPP();
+  _esp_netif = esp_netif_new(&cfg);
+  if (_esp_netif == NULL) {
+    log_e("esp_netif_new failed");
+    return false;
+  }
+
+  /* Attach to receive IP events */
+  initNetif(ESP_NETIF_ID_PPP);
+
+  /* Configure the DTE */
+  esp_modem_dte_config_t dte_config = ESP_MODEM_DTE_DEFAULT_CONFIG();
+  dte_config.uart_config.tx_io_num = _pin_tx;
+  dte_config.uart_config.rx_io_num = _pin_rx;
+  dte_config.uart_config.rts_io_num = _pin_rts;
+  dte_config.uart_config.cts_io_num = _pin_cts;
+  dte_config.uart_config.flow_control = _flow_ctrl;
+  dte_config.uart_config.rx_buffer_size = _rx_buffer_size;
+  dte_config.uart_config.tx_buffer_size = _tx_buffer_size;
+  dte_config.uart_config.port_num = (uart_port_t)_uart_num;
+  dte_config.uart_config.baud_rate = baud_rate;
+
+  /* Configure the DCE */
+  esp_modem_dce_config_t dce_config = ESP_MODEM_DCE_DEFAULT_CONFIG(_apn);
+
+  /* Reset the Modem */
+  if (_pin_rst >= 0) {
+    log_v("Resetting the modem");
+    if (_pin_rst_act_low) {
+      pinMode(_pin_rst, OUTPUT_OPEN_DRAIN);
+    } else {
+      pinMode(_pin_rst, OUTPUT);
+    }
+    perimanSetPinBusExtraType(_pin_rst, "PPP_MODEM_RST");
+    digitalWrite(_pin_rst, !_pin_rst_act_low);
+    delay(_pin_rst_delay);
+    digitalWrite(_pin_rst, _pin_rst_act_low);
+    delay(100);
+  }
+
+  /* Start the DCE */
+  _dce = esp_modem_new_dev((esp_modem_dce_device_t)model, &dte_config, &dce_config, _esp_netif);
+  if (_dce == NULL) {
+    log_e("esp_modem_new_dev failed");
+    goto err;
+  }
+
+  esp_modem_set_error_cb(_dce, _ppp_error_cb);
+
+  /* Wait for Modem to respond */
+  if (_pin_rst >= 0) {
+    // wait to be able to talk to the modem
+    log_v("Waiting for response from the modem");
+    while (esp_modem_sync(_dce) != ESP_OK && tries < 100) {
+      tries++;
+      delay(500);
+    }
+    if (tries >= 100) {
+      log_e("Failed to wait for communication");
+      goto err;
+    }
+  } else {
+    // try to communicate with the modem
+    if (esp_modem_sync(_dce) != ESP_OK) {
+      log_v("Modem does not respond to AT! Switching to COMMAND mode.");
+      esp_modem_set_mode(_dce, ESP_MODEM_MODE_COMMAND);
+      if (esp_modem_sync(_dce) != ESP_OK) {
+        log_v("Modem does not respond to AT! Switching to CMUX mode.");
+        if (esp_modem_set_mode(_dce, ESP_MODEM_MODE_CMUX) != ESP_OK) {
+          log_v("Modem failed to switch to CMUX mode!");
+        } else {
+          log_v("Switching back to COMMAND mode");
+          esp_modem_set_mode(_dce, ESP_MODEM_MODE_COMMAND);
+        }
+      }
+      if (esp_modem_sync(_dce) != ESP_OK) {
+        log_e("Modem failed to respond to AT!");
+        goto err;
+      }
+    }
+  }
+
+  /* enable flow control */
+  if (dte_config.uart_config.flow_control == ESP_MODEM_FLOW_CONTROL_HW) {
+    ret = esp_modem_set_flow_control(_dce, 2, 2);  //2/2 means HW Flow Control.
+    if (ret != ESP_OK) {
+      log_e("Failed to set the hardware flow control: [%d] %s", ret, esp_err_to_name(ret));
+      goto err;
+    }
+  }
+
+  /* check if PIN needed */
+  if (esp_modem_read_pin(_dce, pin_ok) == ESP_OK && pin_ok == false) {
+    if (_pin == NULL || _esp_modem_set_pin(_dce, _pin) != ESP_OK) {
+      log_e("PIN verification failed!");
+      goto err;
+    }
+  }
+
+  _ppp_event_handle = Network.onSysEvent(onPppArduinoEvent);
+
+  setStatusBits(ESP_NETIF_STARTED_BIT);
+  arduino_event_t arduino_event;
+  arduino_event.event_id = ARDUINO_EVENT_PPP_START;
+  Network.postEvent(&arduino_event);
+
+  return true;
+
+err:
+  PPPClass::pppDetachBus((void *)(this));
+  return false;
+}
+
+void PPPClass::end(void) {
+  if (_esp_modem && _esp_netif && _dce) {
+
+    if ((getStatusBits() & ESP_NETIF_CONNECTED_BIT) != 0) {
+      clearStatusBits(ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT);
+      arduino_event_t disconnect_event;
+      disconnect_event.event_id = ARDUINO_EVENT_PPP_DISCONNECTED;
+      Network.postEvent(&disconnect_event);
+    }
+
+    clearStatusBits(
+      ESP_NETIF_STARTED_BIT | ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT
+      | ESP_NETIF_HAS_STATIC_IP_BIT
+    );
+    arduino_event_t arduino_event;
+    arduino_event.event_id = ARDUINO_EVENT_PPP_STOP;
+    Network.postEvent(&arduino_event);
+  }
+
+  destroyNetif();
+
+  if (_ppp_ev_instance != NULL) {
+    if (esp_event_handler_unregister(NETIF_PPP_STATUS, ESP_EVENT_ANY_ID, &_ppp_event_cb) == ESP_OK) {
+      _ppp_ev_instance = NULL;
+    }
+  }
+  _esp_modem = NULL;
+
+  Network.removeEvent(_ppp_event_handle);
+  _ppp_event_handle = 0;
+
+  if (_dce != NULL) {
+    esp_modem_destroy(_dce);
+    _dce = NULL;
+  }
+
+  int8_t pin = -1;
+  if (_pin_tx != -1) {
+    pin = _pin_tx;
+    _pin_tx = -1;
+    perimanClearPinBus(pin);
+  }
+  if (_pin_rx != -1) {
+    pin = _pin_rx;
+    _pin_rx = -1;
+    perimanClearPinBus(pin);
+  }
+  if (_pin_rts != -1) {
+    pin = _pin_rts;
+    _pin_rts = -1;
+    perimanClearPinBus(pin);
+  }
+  if (_pin_cts != -1) {
+    pin = _pin_cts;
+    _pin_cts = -1;
+    perimanClearPinBus(pin);
+  }
+
+  _mode = ESP_MODEM_MODE_COMMAND;
+}
+
+bool PPPClass::sync() const {
+  PPP_CMD_MODE_CHECK(false);
+
+  return esp_modem_sync(_dce) == ESP_OK;
+}
+
+bool PPPClass::attached() const {
+  PPP_CMD_MODE_CHECK(false);
+
+  int m = 0;
+  esp_err_t err = esp_modem_get_network_attachment_state(_dce, m);
+  if (err != ESP_OK) {
+    // log_e("esp_modem_get_network_attachment_state failed with %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return m != 0;
+}
+
+bool PPPClass::mode(esp_modem_dce_mode_t m) {
+  if (_dce == NULL) {
+    return 0;
+  }
+
+  if (_mode == m) {
+    return true;
+  }
+  esp_err_t err = esp_modem_set_mode(_dce, m);
+  if (err != ESP_OK) {
+    log_e("esp_modem_set_mode failed with %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+  _mode = m;
+  return true;
+}
+
+bool PPPClass::setApn(const char *apn) {
+  if (_apn != NULL) {
+    free((void *)_apn);
+    _apn = NULL;
+  }
+  if (apn != NULL) {
+    _apn = strdup(apn);
+    if (_apn == NULL) {
+      log_e("Failed to strdup APN");
+      return false;
+    }
+  }
+  return true;
+}
+
+bool PPPClass::setPin(const char *pin) {
+  if (_pin != NULL) {
+    free((void *)_pin);
+    _pin = NULL;
+  }
+  if (pin != NULL) {
+    for (int i = 0; i < strlen(pin); i++) {
+      if (pin[i] < 0x30 || pin[i] > 0x39) {
+        log_e("Bad character '%c' in PIN. Should be only digits", pin[i]);
+        return false;
+      }
+    }
+    _pin = strdup(pin);
+    if (_pin == NULL) {
+      log_e("Failed to strdup PIN");
+      return false;
+    }
+  }
+  return true;
+}
+
+int PPPClass::RSSI() const {
+  PPP_CMD_MODE_CHECK(-1);
+
+  int rssi, ber;
+  esp_err_t err = esp_modem_get_signal_quality(_dce, rssi, ber);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_signal_quality failed with %d %s", err, esp_err_to_name(err));
+    return -1;
+  }
+  return rssi;
+}
+
+int PPPClass::BER() const {
+  PPP_CMD_MODE_CHECK(-1);
+
+  int rssi, ber;
+  esp_err_t err = esp_modem_get_signal_quality(_dce, rssi, ber);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_signal_quality failed with %d %s", err, esp_err_to_name(err));
+    return -1;
+  }
+  return ber;
+}
+
+String PPPClass::IMSI() const {
+  PPP_CMD_MODE_CHECK(String());
+
+  char imsi[32];
+  esp_err_t err = esp_modem_get_imsi(_dce, (std::string &)imsi);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_imsi failed with %d %s", err, esp_err_to_name(err));
+    return String();
+  }
+
+  return String(imsi);
+}
+
+String PPPClass::IMEI() const {
+  PPP_CMD_MODE_CHECK(String());
+
+  char imei[32];
+  esp_err_t err = esp_modem_get_imei(_dce, (std::string &)imei);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_imei failed with %d %s", err, esp_err_to_name(err));
+    return String();
+  }
+
+  return String(imei);
+}
+
+String PPPClass::moduleName() const {
+  PPP_CMD_MODE_CHECK(String());
+
+  char name[32];
+  esp_err_t err = esp_modem_get_module_name(_dce, (std::string &)name);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_module_name failed with %d %s", err, esp_err_to_name(err));
+    return String();
+  }
+
+  return String(name);
+}
+
+String PPPClass::operatorName() const {
+  PPP_CMD_MODE_CHECK(String());
+
+  char oper[32];
+  int act = 0;
+  esp_err_t err = esp_modem_get_operator_name(_dce, (std::string &)oper, act);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_operator_name failed with %d %s", err, esp_err_to_name(err));
+    return String();
+  }
+
+  return String(oper);
+}
+
+int PPPClass::networkMode() const {
+  PPP_CMD_MODE_CHECK(-1);
+
+  int m = 0;
+  esp_err_t err = esp_modem_get_network_system_mode(_dce, m);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_network_system_mode failed with %d %s", err, esp_err_to_name(err));
+    return -1;
+  }
+  return m;
+}
+
+int PPPClass::radioState() const {
+  PPP_CMD_MODE_CHECK(-1);
+
+  int m = 0;
+  esp_err_t err = esp_modem_get_radio_state(_dce, m);
+  if (err != ESP_OK) {
+    // log_e("esp_modem_get_radio_state failed with %d %s", err, esp_err_to_name(err));
+    return -1;
+  }
+  return m;
+}
+
+bool PPPClass::powerDown() {
+  PPP_CMD_MODE_CHECK(false);
+
+  esp_err_t err = esp_modem_power_down(_dce);
+  if (err != ESP_OK) {
+    log_e("esp_modem_power_down failed with %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return true;
+}
+
+bool PPPClass::reset() {
+  PPP_CMD_MODE_CHECK(false);
+
+  esp_err_t err = esp_modem_reset(_dce);
+  if (err != ESP_OK) {
+    log_e("esp_modem_reset failed with %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return true;
+}
+
+bool PPPClass::storeProfile() {
+  PPP_CMD_MODE_CHECK(false);
+
+  esp_err_t err = esp_modem_store_profile(_dce);
+  if (err != ESP_OK) {
+    log_e("esp_modem_store_profile failed with %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return true;
+}
+
+bool PPPClass::setBaudrate(int baudrate) {
+  PPP_CMD_MODE_CHECK(false);
+
+  esp_err_t err = esp_modem_set_baud(_dce, baudrate);
+  if (err != ESP_OK) {
+    log_e("esp_modem_set_baud failed with %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  uint32_t sclk_freq;
+  err = uart_get_sclk_freq(UART_SCLK_DEFAULT, &sclk_freq);
+  if (err != ESP_OK) {
+    log_e("uart_get_sclk_freq failed with %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  HP_UART_SRC_CLK_ATOMIC() {
+    uart_ll_set_baudrate(UART_LL_GET_HW(_uart_num), (uint32_t)baudrate, sclk_freq);
+  }
+
+  return true;
+}
+
+int PPPClass::batteryVoltage() const {
+  PPP_CMD_MODE_CHECK(-1);
+
+  int volt, bcs, bcl;
+  esp_err_t err = esp_modem_get_battery_status(_dce, volt, bcs, bcl);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_battery_status failed with %d %s", err, esp_err_to_name(err));
+    return -1;
+  }
+  return volt;
+}
+
+int PPPClass::batteryLevel() const {
+  PPP_CMD_MODE_CHECK(-1);
+
+  int volt, bcs, bcl;
+  esp_err_t err = esp_modem_get_battery_status(_dce, volt, bcs, bcl);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_battery_status failed with %d %s", err, esp_err_to_name(err));
+    return -1;
+  }
+  return bcl;
+}
+
+int PPPClass::batteryStatus() const {
+  PPP_CMD_MODE_CHECK(-1);
+
+  int volt, bcs, bcl;
+  esp_err_t err = esp_modem_get_battery_status(_dce, volt, bcs, bcl);
+  if (err != ESP_OK) {
+    log_e("esp_modem_get_battery_status failed with %d %s", err, esp_err_to_name(err));
+    return -1;
+  }
+  return bcs;
+}
+
+bool PPPClass::sms(const char *num, const char *message) {
+  PPP_CMD_MODE_CHECK(false);
+
+  for (int i = 0; i < strlen(num); i++) {
+    if (num[i] != '+' && num[i] != '#' && num[i] != '*' && (num[i] < 0x30 || num[i] > 0x39)) {
+      log_e("Bad character '%c' in SMS Number. Should be only digits and +, # or *", num[i]);
+      return false;
+    }
+  }
+
+  esp_err_t err = esp_modem_sms_txt_mode(_dce, true);
+  if (err != ESP_OK) {
+    log_e("Setting text mode failed %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  err = esp_modem_sms_character_set(_dce);
+  if (err != ESP_OK) {
+    log_e("Setting GSM character set failed %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  err = _esp_modem_send_sms(_dce, num, message);
+  if (err != ESP_OK) {
+    log_e("esp_modem_send_sms() failed with %d %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return true;
+}
+
+String PPPClass::cmd(const char *at_command, int timeout) {
+  PPP_CMD_MODE_CHECK(String());
+
+  char out[128] = {0};
+  esp_err_t err = _esp_modem_at(_dce, at_command, out, timeout);
+  if (err != ESP_OK) {
+    log_e("esp_modem_at failed %d %s", err, esp_err_to_name(err));
+    return String();
+  }
+  return String(out);
+}
+
+size_t PPPClass::printDriverInfo(Print &out) const {
+  size_t bytes = 0;
+  if (_dce == NULL || _mode == ESP_MODEM_MODE_DATA) {
+    return bytes;
+  }
+  if (attached()) {
+    bytes += out.print(",");
+    bytes += out.print(operatorName());
+  }
+  bytes += out.print(",RSSI:");
+  bytes += out.print(RSSI());
+  bytes += out.print(",BER:");
+  bytes += out.print(BER());
+  return bytes;
+}
+
+PPPClass PPP;
+
+#endif /* CONFIG_LWIP_PPP_SUPPORT */
diff --git a/libraries/PPP/src/PPP.h b/libraries/PPP/src/PPP.h
new file mode 100644
index 00000000000..b317f52aefc
--- /dev/null
+++ b/libraries/PPP/src/PPP.h
@@ -0,0 +1,117 @@
+#pragma once
+
+#include "sdkconfig.h"
+#if defined __has_include && __has_include("esp_modem_c_api_types.h")
+#define ARDUINO_HAS_ESP_MODEM 1
+#endif
+
+#if CONFIG_LWIP_PPP_SUPPORT && ARDUINO_HAS_ESP_MODEM
+#include "Network.h"
+#include "esp_modem_c_api_types.h"
+
+typedef enum {
+  PPP_MODEM_GENERIC = ESP_MODEM_DCE_GENETIC,
+  PPP_MODEM_SIM7600 = ESP_MODEM_DCE_SIM7600,
+  PPP_MODEM_SIM7070 = ESP_MODEM_DCE_SIM7070,
+  PPP_MODEM_SIM7000 = ESP_MODEM_DCE_SIM7000,
+  PPP_MODEM_BG96 = ESP_MODEM_DCE_BG96,
+  PPP_MODEM_SIM800 = ESP_MODEM_DCE_SIM800,
+#if CONFIG_ESP_MODEM_ADD_CUSTOM_MODULE
+  PPP_MODEM_CUSTOM = ESP_MODEM_DCE_CUSTOM,
+#endif
+  PPP_MODEM_MAX
+} ppp_modem_model_t;
+
+class PPPClass : public NetworkInterface {
+public:
+  PPPClass();
+  ~PPPClass();
+
+  bool begin(ppp_modem_model_t model, uint8_t uart_num = 1, int baud_rate = 115200);
+  void end();
+
+  // Required for connecting to internet
+  bool setApn(const char *apn);
+
+  // Required only if the SIM card is protected by PIN
+  bool setPin(const char *pin);
+
+  // If the modem supports hardware flow control, it's best to use it
+  bool setPins(int8_t tx, int8_t rx, int8_t rts = -1, int8_t cts = -1, esp_modem_flow_ctrl_t flow_ctrl = ESP_MODEM_FLOW_CONTROL_NONE);
+
+  // Using the reset pin of the module ensures that proper communication can be achieved
+  void setResetPin(int8_t rst, bool active_low = true, uint32_t reset_delay = 200);
+
+  // Modem DCE APIs
+  int RSSI() const;
+  int BER() const;
+  String IMSI() const;
+  String IMEI() const;
+  String moduleName() const;    // modem module name
+  String operatorName() const;  // network operator name
+  int networkMode() const;      // network type (GSM, LTE, etc.)
+  int radioState() const;       // 0:minimal, 1:full
+  bool attached() const;        // true is attached to network
+  bool sync() const;            // true if responds to 'AT'
+  int batteryVoltage() const;
+  int batteryLevel() const;
+  int batteryStatus() const;
+
+  // Switch the communication mode
+  bool mode(esp_modem_dce_mode_t m);
+  esp_modem_dce_mode_t mode() const {
+    return _mode;
+  }
+
+  // Change temporary the baud rate of communication
+  bool setBaudrate(int baudrate);
+
+  // Sens SMS message to a number
+  bool sms(const char *num, const char *message);
+  bool sms(String num, String message) {
+    return sms(num.c_str(), message.c_str());
+  }
+
+  // Send AT command with timeout in milliseconds
+  String cmd(const char *at_command, int timeout);
+  String cmd(String at_command, int timeout) {
+    return cmd(at_command.c_str(), timeout);
+  }
+
+  // untested
+  bool powerDown();
+  bool reset();
+  bool storeProfile();
+
+  esp_modem_dce_t *handle() const;
+
+protected:
+  size_t printDriverInfo(Print &out) const;
+
+public:
+  void _onPppEvent(int32_t event_id, void *event_data);
+  void _onPppArduinoEvent(arduino_event_id_t event, arduino_event_info_t info);
+
+private:
+  esp_modem_dce_t *_dce;
+  int8_t _pin_tx;
+  int8_t _pin_rx;
+  int8_t _pin_rts;
+  int8_t _pin_cts;
+  esp_modem_flow_ctrl_t _flow_ctrl;
+  int8_t _pin_rst;
+  bool _pin_rst_act_low;
+  uint32_t _pin_rst_delay;
+  const char *_pin;
+  const char *_apn;
+  int _rx_buffer_size;
+  int _tx_buffer_size;
+  esp_modem_dce_mode_t _mode;
+  uint8_t _uart_num;
+  network_event_handle_t _ppp_event_handle;
+
+  static bool pppDetachBus(void *bus_pointer);
+};
+
+extern PPPClass PPP;
+#endif /* CONFIG_LWIP_PPP_SUPPORT && ARDUINO_HAS_ESP_MODEM */
diff --git a/libraries/PPP/src/ppp.c b/libraries/PPP/src/ppp.c
new file mode 100644
index 00000000000..52896e76c8e
--- /dev/null
+++ b/libraries/PPP/src/ppp.c
@@ -0,0 +1,28 @@
+#include "sdkconfig.h"
+#if CONFIG_LWIP_PPP_SUPPORT && defined __has_include && __has_include("esp_modem_api.h")
+#include "esp_modem_api.h"
+
+esp_err_t _esp_modem_at(esp_modem_dce_t *dce_wrap, const char *at, char *p_out, int timeout) {
+  return esp_modem_at(dce_wrap, at, p_out, timeout);
+}
+
+esp_err_t _esp_modem_send_sms(esp_modem_dce_t *dce_wrap, const char *number, const char *message) {
+  return esp_modem_send_sms(dce_wrap, number, message);
+}
+
+esp_err_t _esp_modem_set_pin(esp_modem_dce_t *dce_wrap, const char *pin) {
+  return esp_modem_set_pin(dce_wrap, pin);
+}
+
+esp_err_t _esp_modem_at_raw(esp_modem_dce_t *dce_wrap, const char *cmd, char *p_out, const char *pass, const char *fail, int timeout) {
+  return esp_modem_at_raw(dce_wrap, cmd, p_out, pass, fail, timeout);
+}
+
+esp_err_t _esp_modem_set_operator(esp_modem_dce_t *dce_wrap, int mode, int format, const char *oper) {
+  return esp_modem_set_operator(dce_wrap, mode, format, oper);
+}
+
+esp_err_t _esp_modem_set_network_bands(esp_modem_dce_t *dce_wrap, const char *mode, const int *bands, int size) {
+  return esp_modem_set_network_bands(dce_wrap, mode, bands, size);
+}
+#endif  // CONFIG_LWIP_PPP_SUPPORT
diff --git a/libraries/Preferences/examples/Prefs2Struct/Prefs2Struct.ino b/libraries/Preferences/examples/Prefs2Struct/Prefs2Struct.ino
index 7ed2a73bcbe..3b519249362 100644
--- a/libraries/Preferences/examples/Prefs2Struct/Prefs2Struct.ino
+++ b/libraries/Preferences/examples/Prefs2Struct/Prefs2Struct.ino
@@ -1,9 +1,9 @@
 /*
 This example shows how to use Preferences (nvs) to store a
 structure.  Note that the maximum size of a putBytes is 496K
-or 97% of the nvs partition size.  nvs has signifcant overhead,
+or 97% of the nvs partition size.  nvs has significant overhead,
 so should not be used for data that will change often.
-*/ 
+*/
 #include <Preferences.h>
 Preferences prefs;
 
@@ -16,28 +16,28 @@ typedef struct {
 
 void setup() {
   Serial.begin(115200);
-  prefs.begin("schedule"); // use "schedule" namespace
-  uint8_t content[] = {9, 30, 235, 255, 20, 15, 0, 1}; // two entries
+  prefs.begin("schedule");                              // use "schedule" namespace
+  uint8_t content[] = {9, 30, 235, 255, 20, 15, 0, 1};  // two entries
   prefs.putBytes("schedule", content, sizeof(content));
   size_t schLen = prefs.getBytesLength("schedule");
-  char buffer[schLen]; // prepare a buffer for the data
+  char buffer[schLen];  // prepare a buffer for the data
   prefs.getBytes("schedule", buffer, schLen);
-  if (schLen % sizeof(schedule_t)) { // simple check that data fits
+  if (schLen % sizeof(schedule_t)) {  // simple check that data fits
     log_e("Data is not correct size!");
     return;
   }
-  schedule_t *schedule = (schedule_t *) buffer; // cast the bytes into a struct ptr
-  Serial.printf("%02d:%02d %d/%d\n", 
-    schedule[1].hour, schedule[1].minute,
-    schedule[1].setting1, schedule[1].setting2);
-  schedule[2] = {8, 30, 20, 21}; // add a third entry (unsafely)
-// force the struct array into a byte array
-  prefs.putBytes("schedule", schedule, 3*sizeof(schedule_t)); 
+  schedule_t *schedule = (schedule_t *)buffer;  // cast the bytes into a struct ptr
+  Serial.printf("%02d:%02d %d/%d\n", schedule[1].hour, schedule[1].minute, schedule[1].setting1, schedule[1].setting2);
+  schedule[2] = {8, 30, 20, 21};  // add a third entry (unsafely)
+                                  // force the struct array into a byte array
+  prefs.putBytes("schedule", schedule, 3 * sizeof(schedule_t));
   schLen = prefs.getBytesLength("schedule");
   char buffer2[schLen];
   prefs.getBytes("schedule", buffer2, schLen);
-  for (int x=0; x<schLen; x++) Serial.printf("%02X ", buffer[x]);
-  Serial.println(); 
+  for (int x = 0; x < schLen; x++) {
+    Serial.printf("%02X ", buffer[x]);
+  }
+  Serial.println();
 }
 
 void loop() {}
diff --git a/libraries/Preferences/library.properties b/libraries/Preferences/library.properties
index 11675a58cac..eb0158e4932 100644
--- a/libraries/Preferences/library.properties
+++ b/libraries/Preferences/library.properties
@@ -1,5 +1,5 @@
 name=Preferences
-version=1.0
+version=3.2.0
 author=Hristo Gochkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=Provides friendly access to ESP32's Non-Volatile Storage
diff --git a/libraries/Preferences/src/Preferences.cpp b/libraries/Preferences/src/Preferences.cpp
index 6b45d2c7db1..d093c72dd56 100644
--- a/libraries/Preferences/src/Preferences.cpp
+++ b/libraries/Preferences/src/Preferences.cpp
@@ -1,8 +1,9 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
+
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -14,499 +15,543 @@
 #include "Preferences.h"
 
 #include "nvs.h"
-
-const char * nvs_errors[] = { "OTHER", "NOT_INITIALIZED", "NOT_FOUND", "TYPE_MISMATCH", "READ_ONLY", "NOT_ENOUGH_SPACE", "INVALID_NAME", "INVALID_HANDLE", "REMOVE_FAILED", "KEY_TOO_LONG", "PAGE_FULL", "INVALID_STATE", "INVALID_LENGTH"};
-#define nvs_error(e) (((e)>ESP_ERR_NVS_BASE)?nvs_errors[(e)&~(ESP_ERR_NVS_BASE)]:nvs_errors[0])
-
-Preferences::Preferences()
-    :_handle(0)
-    ,_started(false)
-    ,_readOnly(false)
-{}
-
-Preferences::~Preferences(){
-    end();
-}
-
-bool Preferences::begin(const char * name, bool readOnly){
-    if(_started){
-        return false;
-    }
-    _readOnly = readOnly;
-    esp_err_t err = nvs_open(name, readOnly?NVS_READONLY:NVS_READWRITE, &_handle);
-    if(err){
-        log_e("nvs_open failed: %s", nvs_error(err));
-        return false;
-    }
-    _started = true;
-    return true;
-}
-
-void Preferences::end(){
-    if(!_started){
-        return;
-    }
-    nvs_close(_handle);
-    _started = false;
+#include "nvs_flash.h"
+
+const char *nvs_errors[] = {"OTHER",          "NOT_INITIALIZED", "NOT_FOUND",    "TYPE_MISMATCH", "READ_ONLY",     "NOT_ENOUGH_SPACE", "INVALID_NAME",
+                            "INVALID_HANDLE", "REMOVE_FAILED",   "KEY_TOO_LONG", "PAGE_FULL",     "INVALID_STATE", "INVALID_LENGTH"};
+#define nvs_error(e) (((e) > ESP_ERR_NVS_BASE) ? nvs_errors[(e) & ~(ESP_ERR_NVS_BASE)] : nvs_errors[0])
+
+Preferences::Preferences() : _handle(0), _started(false), _readOnly(false) {}
+
+Preferences::~Preferences() {
+  end();
+}
+
+bool Preferences::begin(const char *name, bool readOnly, const char *partition_label) {
+  if (_started) {
+    return false;
+  }
+  _readOnly = readOnly;
+  esp_err_t err = ESP_OK;
+  if (partition_label != NULL) {
+    err = nvs_flash_init_partition(partition_label);
+    if (err) {
+      log_e("nvs_flash_init_partition failed: %s", nvs_error(err));
+      return false;
+    }
+    err = nvs_open_from_partition(partition_label, name, readOnly ? NVS_READONLY : NVS_READWRITE, &_handle);
+  } else {
+    err = nvs_open(name, readOnly ? NVS_READONLY : NVS_READWRITE, &_handle);
+  }
+  if (err) {
+    log_e("nvs_open failed: %s", nvs_error(err));
+    return false;
+  }
+  _started = true;
+  return true;
+}
+
+void Preferences::end() {
+  if (!_started) {
+    return;
+  }
+  nvs_close(_handle);
+  _started = false;
 }
 
 /*
  * Clear all keys in opened preferences
  * */
 
-bool Preferences::clear(){
-    if(!_started || _readOnly){
-        return false;
-    }
-    esp_err_t err = nvs_erase_all(_handle);
-    if(err){
-        log_e("nvs_erase_all fail: %s", nvs_error(err));
-        return false;
-    }
-    return true;
+bool Preferences::clear() {
+  if (!_started || _readOnly) {
+    return false;
+  }
+  esp_err_t err = nvs_erase_all(_handle);
+  if (err) {
+    log_e("nvs_erase_all fail: %s", nvs_error(err));
+    return false;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s", nvs_error(err));
+    return false;
+  }
+  return true;
 }
 
 /*
  * Remove a key
  * */
 
-bool Preferences::remove(const char * key){
-    if(!_started || !key || _readOnly){
-        return false;
-    }
-    esp_err_t err = nvs_erase_key(_handle, key);
-    if(err){
-        log_e("nvs_erase_key fail: %s %s", key, nvs_error(err));
-        return false;
-    }
-    return true;
+bool Preferences::remove(const char *key) {
+  if (!_started || !key || _readOnly) {
+    return false;
+  }
+  esp_err_t err = nvs_erase_key(_handle, key);
+  if (err) {
+    log_e("nvs_erase_key fail: %s %s", key, nvs_error(err));
+    return false;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return false;
+  }
+  return true;
 }
 
 /*
  * Put a key value
  * */
 
-size_t Preferences::putChar(const char* key, int8_t value){
-    if(!_started || !key || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_i8(_handle, key, value);
-    if(err){
-        log_e("nvs_set_i8 fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return 1;
-}
-
-size_t Preferences::putUChar(const char* key, uint8_t value){
-    if(!_started || !key || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_u8(_handle, key, value);
-    if(err){
-        log_e("nvs_set_u8 fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return 1;
-}
-
-size_t Preferences::putShort(const char* key, int16_t value){
-    if(!_started || !key || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_i16(_handle, key, value);
-    if(err){
-        log_e("nvs_set_i16 fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return 2;
-}
-
-size_t Preferences::putUShort(const char* key, uint16_t value){
-    if(!_started || !key || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_u16(_handle, key, value);
-    if(err){
-        log_e("nvs_set_u16 fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return 2;
-}
-
-size_t Preferences::putInt(const char* key, int32_t value){
-    if(!_started || !key || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_i32(_handle, key, value);
-    if(err){
-        log_e("nvs_set_i32 fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return 4;
-}
-
-size_t Preferences::putUInt(const char* key, uint32_t value){
-    if(!_started || !key || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_u32(_handle, key, value);
-    if(err){
-        log_e("nvs_set_u32 fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return 4;
-}
-
-size_t Preferences::putLong(const char* key, int32_t value){
-    return putInt(key, value);
-}
-
-size_t Preferences::putULong(const char* key, uint32_t value){
-    return putUInt(key, value);
-}
-
-size_t Preferences::putLong64(const char* key, int64_t value){
-    if(!_started || !key || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_i64(_handle, key, value);
-    if(err){
-        log_e("nvs_set_i64 fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return 8;
-}
-
-size_t Preferences::putULong64(const char* key, uint64_t value){
-    if(!_started || !key || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_u64(_handle, key, value);
-    if(err){
-        log_e("nvs_set_u64 fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return 8;
-}
-
-size_t Preferences::putFloat(const char* key, const float_t value){
-    return putBytes(key, (void*)&value, sizeof(float_t));
-}
-
-size_t Preferences::putDouble(const char* key, const double_t value){
-    return putBytes(key, (void*)&value, sizeof(double_t));
-}
-
-size_t Preferences::putBool(const char* key, const bool value){
-    return putUChar(key, (uint8_t) (value ? 1 : 0));
-}
-
-size_t Preferences::putString(const char* key, const char* value){
-    if(!_started || !key || !value || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_str(_handle, key, value);
-    if(err){
-        log_e("nvs_set_str fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return strlen(value);
-}
-
-size_t Preferences::putString(const char* key, const String value){
-    return putString(key, value.c_str());
-}
-
-size_t Preferences::putBytes(const char* key, const void* value, size_t len){
-    if(!_started || !key || !value || !len || _readOnly){
-        return 0;
-    }
-    esp_err_t err = nvs_set_blob(_handle, key, value, len);
-    if(err){
-        log_e("nvs_set_blob fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    err = nvs_commit(_handle);
-    if(err){
-        log_e("nvs_commit fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return len;
-}
-
-PreferenceType Preferences::getType(const char* key) {
-    if(!_started || !key || strlen(key)>15){
-        return PT_INVALID;
-    }
-    int8_t mt1; uint8_t mt2; int16_t mt3; uint16_t mt4;
-    int32_t mt5; uint32_t mt6; int64_t mt7; uint64_t mt8;
-    size_t len = 0;
-    if(nvs_get_i8(_handle, key, &mt1) == ESP_OK) return PT_I8;
-    if(nvs_get_u8(_handle, key, &mt2) == ESP_OK) return PT_U8;
-    if(nvs_get_i16(_handle, key, &mt3) == ESP_OK) return PT_I16;
-    if(nvs_get_u16(_handle, key, &mt4) == ESP_OK) return PT_U16;
-    if(nvs_get_i32(_handle, key, &mt5) == ESP_OK) return PT_I32;
-    if(nvs_get_u32(_handle, key, &mt6) == ESP_OK) return PT_U32;
-    if(nvs_get_i64(_handle, key, &mt7) == ESP_OK) return PT_I64;
-    if(nvs_get_u64(_handle, key, &mt8) == ESP_OK) return PT_U64;
-    if(nvs_get_str(_handle, key, NULL, &len) == ESP_OK) return PT_STR;
-    if(nvs_get_blob(_handle, key, NULL, &len) == ESP_OK) return PT_BLOB;
+size_t Preferences::putChar(const char *key, int8_t value) {
+  if (!_started || !key || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_i8(_handle, key, value);
+  if (err) {
+    log_e("nvs_set_i8 fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return 1;
+}
+
+size_t Preferences::putUChar(const char *key, uint8_t value) {
+  if (!_started || !key || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_u8(_handle, key, value);
+  if (err) {
+    log_e("nvs_set_u8 fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return 1;
+}
+
+size_t Preferences::putShort(const char *key, int16_t value) {
+  if (!_started || !key || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_i16(_handle, key, value);
+  if (err) {
+    log_e("nvs_set_i16 fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return 2;
+}
+
+size_t Preferences::putUShort(const char *key, uint16_t value) {
+  if (!_started || !key || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_u16(_handle, key, value);
+  if (err) {
+    log_e("nvs_set_u16 fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return 2;
+}
+
+size_t Preferences::putInt(const char *key, int32_t value) {
+  if (!_started || !key || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_i32(_handle, key, value);
+  if (err) {
+    log_e("nvs_set_i32 fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return 4;
+}
+
+size_t Preferences::putUInt(const char *key, uint32_t value) {
+  if (!_started || !key || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_u32(_handle, key, value);
+  if (err) {
+    log_e("nvs_set_u32 fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return 4;
+}
+
+size_t Preferences::putLong(const char *key, int32_t value) {
+  return putInt(key, value);
+}
+
+size_t Preferences::putULong(const char *key, uint32_t value) {
+  return putUInt(key, value);
+}
+
+size_t Preferences::putLong64(const char *key, int64_t value) {
+  if (!_started || !key || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_i64(_handle, key, value);
+  if (err) {
+    log_e("nvs_set_i64 fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return 8;
+}
+
+size_t Preferences::putULong64(const char *key, uint64_t value) {
+  if (!_started || !key || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_u64(_handle, key, value);
+  if (err) {
+    log_e("nvs_set_u64 fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return 8;
+}
+
+size_t Preferences::putFloat(const char *key, const float_t value) {
+  return putBytes(key, (void *)&value, sizeof(float_t));
+}
+
+size_t Preferences::putDouble(const char *key, const double_t value) {
+  return putBytes(key, (void *)&value, sizeof(double_t));
+}
+
+size_t Preferences::putBool(const char *key, const bool value) {
+  return putUChar(key, (uint8_t)(value ? 1 : 0));
+}
+
+size_t Preferences::putString(const char *key, const char *value) {
+  if (!_started || !key || !value || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_str(_handle, key, value);
+  if (err) {
+    log_e("nvs_set_str fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return strlen(value);
+}
+
+size_t Preferences::putString(const char *key, const String value) {
+  return putString(key, value.c_str());
+}
+
+size_t Preferences::putBytes(const char *key, const void *value, size_t len) {
+  if (!_started || !key || !value || !len || _readOnly) {
+    return 0;
+  }
+  esp_err_t err = nvs_set_blob(_handle, key, value, len);
+  if (err) {
+    log_e("nvs_set_blob fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  err = nvs_commit(_handle);
+  if (err) {
+    log_e("nvs_commit fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return len;
+}
+
+PreferenceType Preferences::getType(const char *key) {
+  if (!_started || !key || strlen(key) > 15) {
     return PT_INVALID;
-}
-
-bool Preferences::isKey(const char* key) {
-    return getType(key) != PT_INVALID;
+  }
+  int8_t mt1;
+  uint8_t mt2;
+  int16_t mt3;
+  uint16_t mt4;
+  int32_t mt5;
+  uint32_t mt6;
+  int64_t mt7;
+  uint64_t mt8;
+  size_t len = 0;
+  if (nvs_get_i8(_handle, key, &mt1) == ESP_OK) {
+    return PT_I8;
+  }
+  if (nvs_get_u8(_handle, key, &mt2) == ESP_OK) {
+    return PT_U8;
+  }
+  if (nvs_get_i16(_handle, key, &mt3) == ESP_OK) {
+    return PT_I16;
+  }
+  if (nvs_get_u16(_handle, key, &mt4) == ESP_OK) {
+    return PT_U16;
+  }
+  if (nvs_get_i32(_handle, key, &mt5) == ESP_OK) {
+    return PT_I32;
+  }
+  if (nvs_get_u32(_handle, key, &mt6) == ESP_OK) {
+    return PT_U32;
+  }
+  if (nvs_get_i64(_handle, key, &mt7) == ESP_OK) {
+    return PT_I64;
+  }
+  if (nvs_get_u64(_handle, key, &mt8) == ESP_OK) {
+    return PT_U64;
+  }
+  if (nvs_get_str(_handle, key, NULL, &len) == ESP_OK) {
+    return PT_STR;
+  }
+  if (nvs_get_blob(_handle, key, NULL, &len) == ESP_OK) {
+    return PT_BLOB;
+  }
+  return PT_INVALID;
+}
+
+bool Preferences::isKey(const char *key) {
+  return getType(key) != PT_INVALID;
 }
 
 /*
  * Get a key value
  * */
 
-int8_t Preferences::getChar(const char* key, const int8_t defaultValue){
-    int8_t value = defaultValue;
-    if(!_started || !key){
-        return value;
-    }
-    esp_err_t err = nvs_get_i8(_handle, key, &value);
-    if(err){
-        log_v("nvs_get_i8 fail: %s %s", key, nvs_error(err));
-    }
+int8_t Preferences::getChar(const char *key, const int8_t defaultValue) {
+  int8_t value = defaultValue;
+  if (!_started || !key) {
     return value;
+  }
+  esp_err_t err = nvs_get_i8(_handle, key, &value);
+  if (err) {
+    log_v("nvs_get_i8 fail: %s %s", key, nvs_error(err));
+  }
+  return value;
 }
 
-uint8_t Preferences::getUChar(const char* key, const uint8_t defaultValue){
-    uint8_t value = defaultValue;
-    if(!_started || !key){
-        return value;
-    }
-    esp_err_t err = nvs_get_u8(_handle, key, &value);
-    if(err){
-        log_v("nvs_get_u8 fail: %s %s", key, nvs_error(err));
-    }
+uint8_t Preferences::getUChar(const char *key, const uint8_t defaultValue) {
+  uint8_t value = defaultValue;
+  if (!_started || !key) {
     return value;
+  }
+  esp_err_t err = nvs_get_u8(_handle, key, &value);
+  if (err) {
+    log_v("nvs_get_u8 fail: %s %s", key, nvs_error(err));
+  }
+  return value;
 }
 
-int16_t Preferences::getShort(const char* key, const int16_t defaultValue){
-    int16_t value = defaultValue;
-    if(!_started || !key){
-        return value;
-    }
-    esp_err_t err = nvs_get_i16(_handle, key, &value);
-    if(err){
-        log_v("nvs_get_i16 fail: %s %s", key, nvs_error(err));
-    }
+int16_t Preferences::getShort(const char *key, const int16_t defaultValue) {
+  int16_t value = defaultValue;
+  if (!_started || !key) {
     return value;
+  }
+  esp_err_t err = nvs_get_i16(_handle, key, &value);
+  if (err) {
+    log_v("nvs_get_i16 fail: %s %s", key, nvs_error(err));
+  }
+  return value;
 }
 
-uint16_t Preferences::getUShort(const char* key, const uint16_t defaultValue){
-    uint16_t value = defaultValue;
-    if(!_started || !key){
-        return value;
-    }
-    esp_err_t err = nvs_get_u16(_handle, key, &value);
-    if(err){
-        log_v("nvs_get_u16 fail: %s %s", key, nvs_error(err));
-    }
+uint16_t Preferences::getUShort(const char *key, const uint16_t defaultValue) {
+  uint16_t value = defaultValue;
+  if (!_started || !key) {
     return value;
+  }
+  esp_err_t err = nvs_get_u16(_handle, key, &value);
+  if (err) {
+    log_v("nvs_get_u16 fail: %s %s", key, nvs_error(err));
+  }
+  return value;
 }
 
-int32_t Preferences::getInt(const char* key, const int32_t defaultValue){
-    int32_t value = defaultValue;
-    if(!_started || !key){
-        return value;
-    }
-    esp_err_t err = nvs_get_i32(_handle, key, &value);
-    if(err){
-        log_v("nvs_get_i32 fail: %s %s", key, nvs_error(err));
-    }
+int32_t Preferences::getInt(const char *key, const int32_t defaultValue) {
+  int32_t value = defaultValue;
+  if (!_started || !key) {
     return value;
+  }
+  esp_err_t err = nvs_get_i32(_handle, key, &value);
+  if (err) {
+    log_v("nvs_get_i32 fail: %s %s", key, nvs_error(err));
+  }
+  return value;
 }
 
-uint32_t Preferences::getUInt(const char* key, const uint32_t defaultValue){
-    uint32_t value = defaultValue;
-    if(!_started || !key){
-        return value;
-    }
-    esp_err_t err = nvs_get_u32(_handle, key, &value);
-    if(err){
-        log_v("nvs_get_u32 fail: %s %s", key, nvs_error(err));
-    }
+uint32_t Preferences::getUInt(const char *key, const uint32_t defaultValue) {
+  uint32_t value = defaultValue;
+  if (!_started || !key) {
     return value;
+  }
+  esp_err_t err = nvs_get_u32(_handle, key, &value);
+  if (err) {
+    log_v("nvs_get_u32 fail: %s %s", key, nvs_error(err));
+  }
+  return value;
 }
 
-int32_t Preferences::getLong(const char* key, const int32_t defaultValue){
-    return getInt(key, defaultValue);
-}
-
-uint32_t Preferences::getULong(const char* key, const uint32_t defaultValue){
-    return getUInt(key, defaultValue);
-}
-
-int64_t Preferences::getLong64(const char* key, const int64_t defaultValue){
-    int64_t value = defaultValue;
-    if(!_started || !key){
-        return value;
-    }
-    esp_err_t err = nvs_get_i64(_handle, key, &value);
-    if(err){
-        log_v("nvs_get_i64 fail: %s %s", key, nvs_error(err));
-    }
-    return value;
+int32_t Preferences::getLong(const char *key, const int32_t defaultValue) {
+  return getInt(key, defaultValue);
 }
 
-uint64_t Preferences::getULong64(const char* key, const uint64_t defaultValue){
-    uint64_t value = defaultValue;
-    if(!_started || !key){
-        return value;
-    }
-    esp_err_t err = nvs_get_u64(_handle, key, &value);
-    if(err){
-        log_v("nvs_get_u64 fail: %s %s", key, nvs_error(err));
-    }
-    return value;
+uint32_t Preferences::getULong(const char *key, const uint32_t defaultValue) {
+  return getUInt(key, defaultValue);
 }
 
-float_t Preferences::getFloat(const char* key, const float_t defaultValue) {
-    float_t value = defaultValue;
-    getBytes(key, (void*) &value, sizeof(float_t));
+int64_t Preferences::getLong64(const char *key, const int64_t defaultValue) {
+  int64_t value = defaultValue;
+  if (!_started || !key) {
     return value;
+  }
+  esp_err_t err = nvs_get_i64(_handle, key, &value);
+  if (err) {
+    log_v("nvs_get_i64 fail: %s %s", key, nvs_error(err));
+  }
+  return value;
 }
 
-double_t Preferences::getDouble(const char* key, const double_t defaultValue) {
-    double_t value = defaultValue;
-    getBytes(key, (void*) &value, sizeof(double_t));
+uint64_t Preferences::getULong64(const char *key, const uint64_t defaultValue) {
+  uint64_t value = defaultValue;
+  if (!_started || !key) {
     return value;
-}
-
-bool Preferences::getBool(const char* key, const bool defaultValue) {
-    return getUChar(key, defaultValue ? 1 : 0) == 1;
-}
-
-size_t Preferences::getString(const char* key, char* value, const size_t maxLen){
-    size_t len = 0;
-    if(!_started || !key || !value || !maxLen){
-        return 0;
-    }
-    esp_err_t err = nvs_get_str(_handle, key, NULL, &len);
-    if(err){
-        log_e("nvs_get_str len fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    if(len > maxLen){
-        log_e("not enough space in value: %u < %u", maxLen, len);
-        return 0;
-    }
-    err = nvs_get_str(_handle, key, value, &len);
-    if(err){
-        log_e("nvs_get_str fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return len;
-}
-
-String Preferences::getString(const char* key, const String defaultValue){
-    char * value = NULL;
-    size_t len = 0;
-    if(!_started || !key){
-        return String(defaultValue);
-    }
-    esp_err_t err = nvs_get_str(_handle, key, value, &len);
-    if(err){
-        log_e("nvs_get_str len fail: %s %s", key, nvs_error(err));
-        return String(defaultValue);
-    }
-    char buf[len];
-    value = buf;
-    err = nvs_get_str(_handle, key, value, &len);
-    if(err){
-        log_e("nvs_get_str fail: %s %s", key, nvs_error(err));
-        return String(defaultValue);
-    }
-    return String(buf);
-}
-
-size_t Preferences::getBytesLength(const char* key){
-    size_t len = 0;
-    if(!_started || !key){
-        return 0;
-    }
-    esp_err_t err = nvs_get_blob(_handle, key, NULL, &len);
-    if(err){
-        log_e("nvs_get_blob len fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
-    return len;
-}
-
-size_t Preferences::getBytes(const char* key, void * buf, size_t maxLen){
-    size_t len = getBytesLength(key);
-    if(!len || !buf || !maxLen){
-        return len;
-    }
-    if(len > maxLen){
-        log_e("not enough space in buffer: %u < %u", maxLen, len);
-        return 0;
-    }
-    esp_err_t err = nvs_get_blob(_handle, key, buf, &len);
-    if(err){
-        log_e("nvs_get_blob fail: %s %s", key, nvs_error(err));
-        return 0;
-    }
+  }
+  esp_err_t err = nvs_get_u64(_handle, key, &value);
+  if (err) {
+    log_v("nvs_get_u64 fail: %s %s", key, nvs_error(err));
+  }
+  return value;
+}
+
+float_t Preferences::getFloat(const char *key, const float_t defaultValue) {
+  float_t value = defaultValue;
+  getBytes(key, (void *)&value, sizeof(float_t));
+  return value;
+}
+
+double_t Preferences::getDouble(const char *key, const double_t defaultValue) {
+  double_t value = defaultValue;
+  getBytes(key, (void *)&value, sizeof(double_t));
+  return value;
+}
+
+bool Preferences::getBool(const char *key, const bool defaultValue) {
+  return getUChar(key, defaultValue ? 1 : 0) == 1;
+}
+
+size_t Preferences::getString(const char *key, char *value, const size_t maxLen) {
+  size_t len = 0;
+  if (!_started || !key || !value || !maxLen) {
+    return 0;
+  }
+  esp_err_t err = nvs_get_str(_handle, key, NULL, &len);
+  if (err) {
+    log_e("nvs_get_str len fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  if (len > maxLen) {
+    log_e("not enough space in value: %u < %u", maxLen, len);
+    return 0;
+  }
+  err = nvs_get_str(_handle, key, value, &len);
+  if (err) {
+    log_e("nvs_get_str fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return len;
+}
+
+String Preferences::getString(const char *key, const String defaultValue) {
+  char *value = NULL;
+  size_t len = 0;
+  if (!_started || !key) {
+    return String(defaultValue);
+  }
+  esp_err_t err = nvs_get_str(_handle, key, value, &len);
+  if (err) {
+    log_e("nvs_get_str len fail: %s %s", key, nvs_error(err));
+    return String(defaultValue);
+  }
+  char buf[len];
+  value = buf;
+  err = nvs_get_str(_handle, key, value, &len);
+  if (err) {
+    log_e("nvs_get_str fail: %s %s", key, nvs_error(err));
+    return String(defaultValue);
+  }
+  return String(buf);
+}
+
+size_t Preferences::getBytesLength(const char *key) {
+  size_t len = 0;
+  if (!_started || !key) {
+    return 0;
+  }
+  esp_err_t err = nvs_get_blob(_handle, key, NULL, &len);
+  if (err) {
+    log_e("nvs_get_blob len fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return len;
+}
+
+size_t Preferences::getBytes(const char *key, void *buf, size_t maxLen) {
+  size_t len = getBytesLength(key);
+  if (!len || !buf || !maxLen) {
     return len;
+  }
+  if (len > maxLen) {
+    log_e("not enough space in buffer: %u < %u", maxLen, len);
+    return 0;
+  }
+  esp_err_t err = nvs_get_blob(_handle, key, buf, &len);
+  if (err) {
+    log_e("nvs_get_blob fail: %s %s", key, nvs_error(err));
+    return 0;
+  }
+  return len;
 }
 
 size_t Preferences::freeEntries() {
-    nvs_stats_t nvs_stats;
-    esp_err_t err = nvs_get_stats(NULL, &nvs_stats);
-    if(err){
-        log_e("Failed to get nvs statistics");
-        return 0;
-    }
-    return nvs_stats.free_entries;
+  nvs_stats_t nvs_stats;
+  esp_err_t err = nvs_get_stats(NULL, &nvs_stats);
+  if (err) {
+    log_e("Failed to get nvs statistics");
+    return 0;
+  }
+  return nvs_stats.free_entries;
 }
diff --git a/libraries/Preferences/src/Preferences.h b/libraries/Preferences/src/Preferences.h
index 1b8be270dd4..d56aef02921 100644
--- a/libraries/Preferences/src/Preferences.h
+++ b/libraries/Preferences/src/Preferences.h
@@ -17,61 +17,72 @@
 #include "Arduino.h"
 
 typedef enum {
-    PT_I8, PT_U8, PT_I16, PT_U16, PT_I32, PT_U32, PT_I64, PT_U64, PT_STR, PT_BLOB, PT_INVALID
+  PT_I8,
+  PT_U8,
+  PT_I16,
+  PT_U16,
+  PT_I32,
+  PT_U32,
+  PT_I64,
+  PT_U64,
+  PT_STR,
+  PT_BLOB,
+  PT_INVALID
 } PreferenceType;
 
 class Preferences {
-    protected:
-        uint32_t _handle;
-        bool _started;
-        bool _readOnly;
-    public:
-        Preferences();
-        ~Preferences();
+protected:
+  uint32_t _handle;
+  bool _started;
+  bool _readOnly;
 
-        bool begin(const char * name, bool readOnly=false);
-        void end();
+public:
+  Preferences();
+  ~Preferences();
 
-        bool clear();
-        bool remove(const char * key);
+  bool begin(const char *name, bool readOnly = false, const char *partition_label = NULL);
+  void end();
 
-        size_t putChar(const char* key, int8_t value);
-        size_t putUChar(const char* key, uint8_t value);
-        size_t putShort(const char* key, int16_t value);
-        size_t putUShort(const char* key, uint16_t value);
-        size_t putInt(const char* key, int32_t value);
-        size_t putUInt(const char* key, uint32_t value);
-        size_t putLong(const char* key, int32_t value);
-        size_t putULong(const char* key, uint32_t value);
-        size_t putLong64(const char* key, int64_t value);
-        size_t putULong64(const char* key, uint64_t value);
-        size_t putFloat(const char* key, float_t value);
-        size_t putDouble(const char* key, double_t value);
-        size_t putBool(const char* key, bool value);
-        size_t putString(const char* key, const char* value);
-        size_t putString(const char* key, String value);
-        size_t putBytes(const char* key, const void* value, size_t len);
+  bool clear();
+  bool remove(const char *key);
 
-        bool isKey(const char* key);
-        PreferenceType getType(const char* key);
-        int8_t getChar(const char* key, int8_t defaultValue = 0);
-        uint8_t getUChar(const char* key, uint8_t defaultValue = 0);
-        int16_t getShort(const char* key, int16_t defaultValue = 0);
-        uint16_t getUShort(const char* key, uint16_t defaultValue = 0);
-        int32_t getInt(const char* key, int32_t defaultValue = 0);
-        uint32_t getUInt(const char* key, uint32_t defaultValue = 0);
-        int32_t getLong(const char* key, int32_t defaultValue = 0);
-        uint32_t getULong(const char* key, uint32_t defaultValue = 0);
-        int64_t getLong64(const char* key, int64_t defaultValue = 0);
-        uint64_t getULong64(const char* key, uint64_t defaultValue = 0);
-        float_t getFloat(const char* key, float_t defaultValue = NAN);
-        double_t getDouble(const char* key, double_t defaultValue = NAN);
-        bool getBool(const char* key, bool defaultValue = false);
-        size_t getString(const char* key, char* value, size_t maxLen);
-        String getString(const char* key, String defaultValue = String());
-        size_t getBytesLength(const char* key);
-        size_t getBytes(const char* key, void * buf, size_t maxLen);
-        size_t freeEntries();
+  size_t putChar(const char *key, int8_t value);
+  size_t putUChar(const char *key, uint8_t value);
+  size_t putShort(const char *key, int16_t value);
+  size_t putUShort(const char *key, uint16_t value);
+  size_t putInt(const char *key, int32_t value);
+  size_t putUInt(const char *key, uint32_t value);
+  size_t putLong(const char *key, int32_t value);
+  size_t putULong(const char *key, uint32_t value);
+  size_t putLong64(const char *key, int64_t value);
+  size_t putULong64(const char *key, uint64_t value);
+  size_t putFloat(const char *key, float_t value);
+  size_t putDouble(const char *key, double_t value);
+  size_t putBool(const char *key, bool value);
+  size_t putString(const char *key, const char *value);
+  size_t putString(const char *key, String value);
+  size_t putBytes(const char *key, const void *value, size_t len);
+
+  bool isKey(const char *key);
+  PreferenceType getType(const char *key);
+  int8_t getChar(const char *key, int8_t defaultValue = 0);
+  uint8_t getUChar(const char *key, uint8_t defaultValue = 0);
+  int16_t getShort(const char *key, int16_t defaultValue = 0);
+  uint16_t getUShort(const char *key, uint16_t defaultValue = 0);
+  int32_t getInt(const char *key, int32_t defaultValue = 0);
+  uint32_t getUInt(const char *key, uint32_t defaultValue = 0);
+  int32_t getLong(const char *key, int32_t defaultValue = 0);
+  uint32_t getULong(const char *key, uint32_t defaultValue = 0);
+  int64_t getLong64(const char *key, int64_t defaultValue = 0);
+  uint64_t getULong64(const char *key, uint64_t defaultValue = 0);
+  float_t getFloat(const char *key, float_t defaultValue = NAN);
+  double_t getDouble(const char *key, double_t defaultValue = NAN);
+  bool getBool(const char *key, bool defaultValue = false);
+  size_t getString(const char *key, char *value, size_t maxLen);
+  String getString(const char *key, String defaultValue = String());
+  size_t getBytesLength(const char *key);
+  size_t getBytes(const char *key, void *buf, size_t maxLen);
+  size_t freeEntries();
 };
 
 #endif
diff --git a/libraries/README.md b/libraries/README.md
index 89da3568ff0..aee5bb07614 100644
--- a/libraries/README.md
+++ b/libraries/README.md
@@ -1,21 +1,20 @@
 # ESP32 Libraries
 
-arduino-esp32 includes libraries for Arduino compatibility along with some object wrappers around hardware specific devices.  Examples are included in the examples folder under each library folder.  The ESP32 includes additional examples which need no special drivers.
+arduino-esp32 includes libraries for Arduino compatibility along with some object wrappers around hardware specific devices. Examples are included in the examples folder under each library folder. The ESP32 includes additional examples which need no special drivers.
 
 ### ArduinoOTA
-  Over The Air firmware update daemon.  Use espota.py to upload to the device.
+  Over The Air firmware update daemon. Use espota.py to upload to the device.
 
 ### AsyncUDP
   Asynchronous task driven UDP datagram client/server
 
-### AzureIoT
-  Library to interact with Microsoft Azure IoT services
-
 ### BLE
   Bluetooth Low Energy v4.2 client/server framework
 
 ### BluetoothSerial
-  Serial to Bluetooth redirection server
+  Serial to Bluetooth redirection server\
+  Note: This library depends on Bluetooth Classic which is only available for ESP32\
+  (Bluetoothserial is **not available** for ESP32-S2, ESP32-C3, ESP32-S3).
 
 ### DNSServer
   A basic UDP DNS daemon (includes captive portal demo)
@@ -34,6 +33,7 @@ arduino-esp32 includes libraries for Arduino compatibility along with some objec
   * GPIO
   * HallSensor
   * I2S
+  * MacAddress
   * ResetReason
   * RMT
   * Time
@@ -43,6 +43,9 @@ arduino-esp32 includes libraries for Arduino compatibility along with some objec
 ### ESPmDNS
   mDNS service advertising
 
+### Ethernet
+  Ethernet networking
+
 ### FFat
   FAT indexed filesystem on SPI flash
 
@@ -50,17 +53,26 @@ arduino-esp32 includes libraries for Arduino compatibility along with some objec
   Filesystem virtualization framework
 
 ### HTTPClient
-  A simple HTTP client, compatible with WiFiClientSecure
+  A simple HTTP client, compatible with NetworkClientSecure
 
 ### HTTPUpdate
   Download a firmware update from HTTPd and apply it using Update
 
+### HTTPUpdateServer
+  Upload a firmware for the update from HTTPd
+
+### LittleFS
+  LittleFS (File System)
+
 ### NetBIOS
   NetBIOS name advertiser
 
 ### Preferences
   Flash keystore using ESP32 NVS
 
+### ESP RainMaker
+  End-to-end platform by Espressif that enables Makers to realize their IoT ideas faster
+
 ### SD
   Secure Digital card filesystem using SPI access
 
@@ -76,20 +88,28 @@ arduino-esp32 includes libraries for Arduino compatibility along with some objec
 ### SPIFFS
   SPI Flash Filesystem (see [spiffs-plugin](https://github.com/me-no-dev/arduino-esp32fs-plugin) to upload to device)
 
+### SR
+  ESP-SR helps users build AI speech solutions based on ESP32-S3 or ESP32-P4 chips
+
 ### Ticker
   A timer to call functions on an interval
 
 ### Update
   Sketch Update using ESP32 OTA functionality
 
+### USB
+  Universal Serial Bus driver (device only)
+
 ### WebServer
   A simple HTTP daemon
 
+<!-- vale off -->
 ### WiFi
-  Arduino compatible WiFi driver (includes Ethernet driver)
+<!-- vale on -->
+  Arduino compatible Wi-Fi driver
 
-### WiFiClientSecure
-  Arduino compatible WiFi client object using embedded encryption
+### NetworkClientSecure
+  Arduino compatible Wi-Fi client object using embedded encryption
 
 ### Wire
-  Arduino compatible I2C driver (master only)
+  Arduino compatible I2C driver
diff --git a/libraries/RainMaker/README.md b/libraries/RainMaker/README.md
new file mode 100644
index 00000000000..2bfe7dd1a06
--- /dev/null
+++ b/libraries/RainMaker/README.md
@@ -0,0 +1,483 @@
+# ESP RainMaker library for Arduino
+This library allows to work with ESP RainMaker.
+
+ESP RainMaker is an end-to-end solution offered by Espressif to enable remote control and monitoring for ESP32-S2 and ESP32 based products without any configuration required in the Cloud. The primary components of this solution are:
+
+- Claiming Service (to get the Cloud connectivity credentials)
+- RainMaker library (i.e. this library, to develop the firmware)
+- RainMaker Cloud (backend, offering remote connectivity)
+- RainMaker Phone App/CLI (Client utilities for remote access)
+
+The key features of ESP RainMaker are:
+
+1. Ability to define own devices and parameters, of any type, in the firmware.
+2. Zero configuration required on the Cloud.
+3. Phone apps that dynamically render the UI as per the device information.
+
+This ESP RainMaker library is built using esp-rainmaker component.
+
+#### Repository Source
+
+- [ESP RainMaker](https://github.com/espressif/esp-rainmaker)
+
+## Phone Apps
+
+#### Android
+
+- [Google PlayStore](https://play.google.com/store/apps/details?id=com.espressif.rainmaker)
+- [Direct APK](https://github.com/espressif/esp-rainmaker/wiki)
+- [Source Code](https://github.com/espressif/esp-rainmaker-android)
+
+#### iOS
+- [Apple App Store](https://apps.apple.com/app/esp-rainmaker/id1497491540)
+- [Source Code](https://github.com/espressif/esp-rainmaker-ios)
+
+## Documentation
+
+Additional information about ESP RainMaker can be found [here](https://rainmaker.espressif.com/)
+
+NOTE : ESP RainMaker library is currently supported for ESP32 board only.
+
+## ESP RainMaker Agent API
+
+### RMaker.initNode()
+This initializes the ESP RainMaker agent, Wi-Fi and creates the node.
+```
+Node initNode(const char *name, const char *type);
+```
+* **Parameters**
+1. `name`: Name of the node
+2. `type`: Type of the node
+
+* **Return**
+1. Object of Node.
+
+* You can also set the configuration of the node using the following API
+ 1. RMaker.setTimeSync(bool val)
+> NOTE: If you want to set the configuration for the node then these configuration API must be called before `RMaker.initNode()`.
+
+### RMaker.start()
+It starts the ESP RainMaker agent.
+```
+esp_err_t start()
+```
+* **Return**
+1. ESP_OK : On success
+2. Error in case of failure
+
+> NOTE :
+> 1. ESP RainMaker agent should be initialized before this call.
+> 2. Once ESP RainMaker agent starts, compulsorily call `WiFi.beginProvision()` API.
+
+### RMaker.stop()
+It stops the ESP RainMaker agent which was started using `RMaker.start()`.
+```
+esp_err_t stop()
+```
+* **Return**
+1. ESP_OK : On success
+2. Error in case of failure
+
+### RMaker.deinitNode()
+It deinitializes the ESP RainMaker agent and the node created using `RMaker.initNode()`.
+```
+esp_err_t deinitNode(Node node)
+```
+* **Parameter**
+1. `node` : Node object created using `RMaker.initNode()`
+* **Return**
+1. ESP_OK : On success
+2. Error in case of failure
+
+### RMaker.enableOTA()
+It enables OTA as per the ESP RainMaker Specification. For more details refer ESP RainMaker documentation. check [here](https://rainmaker.espressif.com/docs/ota.html)
+```
+esp_err_t enableOTA(ota_type_t type);
+```
+* **Parameter**
+1. `type` : The OTA workflow type.
+    - OTA_USING_PARAMS
+    - OTA_USING_TOPICS
+* **Return**
+1. ESP_OK : On success
+2. Error in case of failure
+
+### RMaker.enableSchedule()
+This API enables the scheduling service for the node. For more information, check [here](https://rainmaker.espressif.com/docs/scheduling.html).
+```
+esp_err_t enableSchedule();
+```
+* **Return**
+1. ESP_OK : On success
+2. Error in case of failure
+
+### RMaker.setTimeZone()
+This API set's the timezone as a user friendly location string. Check [here](https://rainmaker.espressif.com/docs/time-service.html) for a list of valid values.
+```
+esp_err_t setTimeZone(const char *tz);
+```
+* **Parameter**
+1. `tz' : Valid values as specified in documentation.
+
+* **Return**
+1. ESP_OK : On success
+2. Error in case of failure
+> NOTE : default value is "Asia/Shanghai".
+> This API comes into picture only when working with scheduling.
+
+## ESP RainMaker NODE APIs
+`Node` class expose API's for node.
+> NOTE : my_node is the object of Node class.
+
+### my_node.getNodeID()
+It returns the unique node_id assigned to the node. This node_id is usually the MAC address of the board.
+```
+char * getNodeID()
+```
+* **Return**
+1. `char * ` : Pointer to a NULL terminated node_id string.
+
+### my_node.getNodeInfo()
+It returns pointer to the node_info_t as configured during node initialization.
+```
+node_info_t * getNodeInfo();
+```
+* **Return**
+1. `node_info_t` : Pointer to the structure node_info_t on success.
+2. `NULL` : On failure.
+
+* **ESP RainMaker node info**
+It has following data member
+1. char * name
+2. char * type
+3. char * fw_version
+4. char * model
+
+### my_node.addNodeAttr()
+It adds a new attribute as the metadata to the node.
+```
+esp_err_t addNodeAttr(const char *attr_name, const char *val);
+```
+* **Parameters**
+1. `attr_name` : Name of the attribute
+2. `val` : Value of the attribute
+
+* **Return**
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+> NOTE : Only string values are allowed.
+
+### my_node.addDevice()
+It adds a device to the node.
+```
+esp_err_t addDevice(Device device);
+```
+* **Parameter**
+1. `device` : Device object
+
+* **Return**
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+> NOTE :
+> - This is the mandatory API to register device to node.
+> - Single Node can have multiple devices.
+> - Device name should be unique for each device.
+
+### my_node.removeDevice()
+It removes a device from the node.
+```
+esp_err_t removeDevice(Device device);
+```
+* **Parameter**
+1. `device` : Device object
+
+* **Return**
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+## ESP RainMaker DEVICE API's
+`Device` class expose API's for virtual devices on the node.
+Parameterized constructor is defined which creates the virtual device on the node. Using Device class object you can create your own device.
+> NOTE : my_device is the object of Device class
+```
+Device my_device(const char *dev_name, const char *dev_type, void *priv_data);
+```
+* **Parameters**
+1. `dev_name` : Unique device name
+2. `dev_type` : Optional device type. It can be kept NULL.
+    * Standard Device Types
+        * ESP_RMAKER_DEVICE_SWITCH
+        * ESP_RMAKER_DEVICE_LIGHTBULB
+        * ESP_RMAKER_DEVICE_FAN
+        * ESP_RMAKER_DEVICE_TEMP_SENSOR
+3. `priv_data` : Private data associated with the device. This will be passed to the callbacks.
+
+> NOTE : This created device should be added to the node using `my_node.addDevice(my_device)`.
+
+- Sample example
+```
+Device my_device("Switch");
+Device my_device("Switch1", NULL, NULL);
+```
+> Here, dev_name is compulsory, rest are optional.
+> Node can have multiple device, each device should have unique device name.
+
+### Standard Device
+- Classes are defined for the standard devices.
+- Creating object of these class creates the standard device with default parameters to it.
+- Class for standard devices
+    * Switch
+    * LightBulb
+    * TemperatureSensor
+    * Fan
+```
+Switch my_switch(const char *dev_name, void *priv_data, bool power);
+```
+* **Parameters**
+1. `dev_name` : Unique device name by default it is "switch" for switch device.
+2. `priv_data` : Private data associated with the device. This will be passed to the callbacks.
+3. `power` : It is the value that can be set for primary parameter.
+
+- Sample example for standard device.
+```
+Switch switch1;
+Switch switch2("switch2", NULL, true);
+```
+`"switch2"` : Name for standard device.
+
+`NULL` : Private data for the device, which will be used in callback.
+
+`true` : Default value for the primary param, in case of switch it is power.
+
+> NOTE : No parameter are compulsory for standard devices. However if you are creating two objects of same standard class then in that case you will have to set the device name, if not then both device will have same name which is set by default, hence device will not get create. Device name should be unique for each device.
+
+### my_device.getDeviceName()
+It returns the name of the Device.
+```
+const char * getDeviceName();
+```
+* **Return**
+1. `char *`: Returns Device name.
+
+> NOTE : Each device on the node should have unique device name.
+
+### my_device.addDeviceAttr()
+It adds attribute to the device. Device attributes are reported only once after a boot-up as part of the node configuration. Eg. Serial Number
+```
+esp_err_t addDeviceAttr(const char *attr_name, const char *val);
+```
+* **Parameters**
+1. `attr_name` : Name of the attribute
+2. `val` : Value of the attribute
+
+* **Return**
+1. `ESP_OK` : On success
+2. Error in case  of failure
+
+### my_device.deleteDevice()
+It deletes the device created using parameterized constructor. This device should be first removed from the node using `my_node.removeDevice(my_device)`.
+```
+esp_err_t deleteDevice();
+```
+* **Return**
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+### my_device.addXParam()
+It adds standard parameter to the device.
+> NOTE : X is the default name by which parameter is referred, you can specify your own name to each parameter.
+
+> Default
+
+> Eg. `my_device.addPowerParam(true)` here power parameter is referred with name Power.
+> Eg. `my_device.addHueParam(12)` here hue parameter is referred with name Hue.
+
+> You can specify your own name to each parameter
+
+> Eg. `my_device.addNameParam("NickName")` here name parameter is referred with name NickName.
+> Eg. `my_device.addPowerParam(true, "FanPower")` here power parameter is referred with name FanPower.
+
+```
+esp_err_t addNameParam(const char *param_name = ESP_RMAKER_DEF_NAME_PARAM);
+esp_err_t addPowerParam(bool val, const char *param_name = ESP_RMAKER_DEF_POWER_NAME);
+esp_err_t addBrightnessParam(int val, const char *param_name = ESP_RMAKER_DEF_BRIGHTNESS_NAME);
+esp_err_t addHueParam(int val, const char *param_name = ESP_RMAKER_DEF_HUE_NAME);
+esp_err_t addSaturationParam(int val, const char *param_name = ESP_RMAKER_DEF_SATURATION_NAME);
+esp_err_t addIntensityParam(int val, const char *param_name = ESP_RMAKER_DEF_INTENSITY_NAME);
+esp_err_t addCCTParam(int val, const char *param_name = ESP_RMAKER_DEF_CCT_NAME);
+esp_err_t addDirectionParam(int val, const char *param_name = ESP_RMAKER_DEF_DIRECTION_NAME);
+esp_err_t addSpeedParam(int val, const char *param_name = ESP_RMAKER_DEF_SPEED_NAME);
+esp_err_t addTemperatureParam(float val, const char *param_name = ESP_RMAKER_DEF_TEMPERATURE_NAME);
+```
+* **Standard Parameters**
+
+* These are the standard parameters.
+    * Name : ESP_RMAKER_DEF_NAME_PARAM
+    * Power : ESP_RMAKER_DEF_POWER_NAME
+    * Brightness : ESP_RMAKER_DEF_BRIGHTNESS_NAME
+    * Hue : ESP_RMAKER_DEF_HUE_NAME
+    * Saturation : ESP_RMAKER_DEF_SATURATION_NAME
+    * Intensity : ESP_RMAKER_DEF_INTENSITY_NAME
+    * CCT : ESP_RMAKER_DEF_CCT_NAME
+    * Direction : ESP_RMAKER_DEF_DIRECTION_NAME
+    * Speed : ESP_RMAKER_DEF_SPEED_NAME
+    * Temperature : ESP_RMAKER_DEF_TEMPERATURE_NAME
+> NOTE : Care should be taken while accessing name of parameter. Above mentioned are the two ways using which default name of parameters can be accessed. Either LHS or RHS.
+
+### my_device.assignPrimaryParam()
+It assigns a parameter (already added using addXParam() or addParam()) as a primary parameter, which can be used by clients (phone apps specifically) to give prominence to it.
+```
+esp_err_t assignPrimaryParam(param_handle_t *param);
+```
+* **Parameter**
+1. `param` : Handle of the parameter. It is obtained using `my_device.getParamByName()`.
+```
+param_handle_t * getParamByName(const char *param_name);
+```
+> NOTE :
+> `param_name` : It is the name of the parameter which was added using addXparam() or addParam().
+
+### my_device.addParam()
+It allows user to add custom parameter to the device created using `Param` class.
+```
+esp_err_t addParam(Param parameter);
+```
+* **Parameter**
+1. `parameter` : Object of Param
+
+* **Return**
+1. ESP_OK : On success
+2. Error in case of failure
+> NOTE : Param class exposes API's to create the custom parameter.
+
+### my_device.updateAndReportParam()
+It updates the parameter assosicated with particular device on ESP RainMaker cloud.
+```
+esp_err_t updateAndReportParam(const char *param_name, value);
+```
+* **Parameters**
+1. `param_name` : Name of the parameter
+2. `value` : Value to be updated. It can be int, bool, char * , float.
+
+* **Return**
+1. `ESP_OK` : On success
+2. Error in case of failure
+
+### my_device.addCb()
+It registers read and write callback for the device which will be invoked as per requests received from the cloud (or other paths as may be added in future).
+```
+void addCb(deviceWriteCb write_cb, deviceReadCb read_cb);
+```
+* **Parameters**
+1. `write_cb` : Function with signature [ func_name(Device *device, Param *param, const param_val_t val, void *priv_data, write_ctx_t *ctx); ]
+2. `read_cb` : Function with signature [ func_name(Device *device, Param *param, void *priv_data, read_ctx_t *ctx); ]
+
+* **param_val_t val**
+Value can be accessed as below
+1. `bool` : val.val.b
+2. `integer` : val.val.i
+3. `float` : val.val.f
+4. `char *` : val.val.s
+
+## ESP RainMaker PARAM API's
+`Param` class expose API's for creating custom parameters for the devices and report and update values associated with parameter to the ESP RainMaker cloud. Parameterized constructor is defined which creates custom parameter.
+> NOTE : my_param is the object of Param class.
+
+```
+Param my_param(const char *param_name, const char *param_type, param_val_t val, uint8_t properties);
+```
+* **Parameters**
+1. `param_name` : Name of the parameter
+2. `param_type` : Type of the parameter. It is optional can be kept NULL.
+3. `val` : Define the default value for the parameter. It should be defined using `value(int ival)` , `value(bool bval)` , `value(float fval)` , `value(char *sval)`.
+4. `properties` : Properties of the parameter, which will be a logical OR of flags.
+    * Flags
+        * PROP_FLAG_WRITE
+        * PROP_FLAG_READ
+        * PROP_FLAG_TIME_SERIES
+        * PROP_FLAG_PERSIST
+
+`Sample example : Param my_param("bright", NULL, value(30), PROP_FLAG_READ | PROP_FLAG_WRITE | PROP_FLAG_PERSIST);`
+> NOTE : Parameter created using Param class should be added to the device using `my_device.addParam(my_param);`
+
+### my_param.addUIType()
+Add a UI type to the parameter. This will be used by the Phone apps (or other clients) to render appropriate UI for the given parameter. Please refer the RainMaker documentation [here](https://rainmaker.espressif.com/docs/standard-types.html#ui-elements) for supported UI Types.
+```
+esp_err_t addUIType(const char *ui_type);
+```
+* **Parameter**
+1. `ui_type` : String describing the UI Type.
+    * Standard UI Types
+     * ESP_RMAKER_UI_TOGGLE
+     * ESP_RMAKER_UI_SLIDER
+     * ESP_RMAKER_UI_DROPDOWN
+     * ESP_RMAKER_UI_TEXT
+
+* **Returns**
+1. ESP_OK : On success.
+2. Error in case of failure.
+
+### my_param.addBounds()
+Add bounds for an integer/float parameter. This can be used to add bounds (min/max values) for a given integer/float parameter. Eg. brightness will have bounds as 0 and 100 if it is a percentage.
+```
+esp_err_t addBounds(param_val_t min, param_val_t max, param_val_t step);
+```
+* **Parameters**
+1. `min` : Minimum value
+2. `max` : Maximum value
+3. `step` : step Minimum stepping
+
+* **Returns**
+1. ESP_OK : On success.
+2. Error in case of failure.
+
+`Sample example : my_param.addBounds(value(0), value(100), value(5));`
+
+### my_param.updateAndReport()
+It updates the parameter and report it to ESP RainMaker cloud. This is called in callback.
+```
+esp_err_t updateAndReport(param_val_t val);
+```
+* **Parameters**
+1. `val` : New value of the parameter
+
+* **Return**
+1. ESP_OK : On success.
+2. Error in case of failure.
+
+> NOTE :
+> - This API should always be called inside device write callback, if you aimed at updating n reporting parameter values, changed via RainMaker Client (Phone App), to the ESP RainMaker cloud.
+> - If not called then parameter values will not be updated to the ESP RainMaker cloud.
+
+### printQR()
+This API displays QR code, which is used in provisioning.
+```
+printQR(const char *serv_name, const char *pop, const char *transport);
+```
+* **Parameters**
+1. `name` : Service name used in provisioning API.
+2. `pop` : Proof of possession used in provisioning API.
+3. `transport` :
+    1. `softap` : In case of provisioning using SOFTAP.
+    2. `ble` : In case of provisioning using BLE.
+
+### RMakerFactoryReset()
+Reset the device to factory defaults.
+
+```
+RMakerFactoryReset(2);
+```
+* **Parameters**
+1. `seconds` : Time in seconds after which the chip should reboot after doing a factory reset.
+
+
+### RMakerWiFiReset()
+Reset Wi-Fi credentials.
+```
+RMakerWiFiReset(2);
+```
+
+* **Parameters**
+1. `seconds` : Time in seconds after which the chip should reboot after doing a Wi-Fi reset.
diff --git a/libraries/RainMaker/examples/README.md b/libraries/RainMaker/examples/README.md
new file mode 100644
index 00000000000..f838736dad8
--- /dev/null
+++ b/libraries/RainMaker/examples/README.md
@@ -0,0 +1,14 @@
+# ESP RainMaker Examples
+
+While building any examples for ESP RainMaker, take care of the following:
+
+1. Change the partition scheme that fits your flash size in Arduino IDE to `RainMaker 4MB`, `RainMaker 4MB no OTA` or `RainMaker 8MB` (Tools -> Partition Scheme -> RainMaker).
+2. Once ESP RainMaker gets started, compulsorily call `WiFi.beginProvision()` which is responsible for user-node mapping.
+3. Use the appropriate provisioning scheme as per the board.
+    - ESP32 Board: BLE Provisioning
+    - ESP32-C3 Board: BLE Provisioning
+    - ESP32-S3 Board: BLE Provisioning
+    - ESP32-S2 Board: SoftAP Provisioning
+    - ESP32-C6 Board: BLE Provisioning
+    - ESP32-H2 Board: BLE Provisioning
+4. Set debug level to Info (Tools -> Core Debug Level -> Info). This is the recommended debug level but not mandatory to run RainMaker.
diff --git a/libraries/RainMaker/examples/RMakerCustom/README.md b/libraries/RainMaker/examples/RMakerCustom/README.md
new file mode 100644
index 00000000000..b6b17052827
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerCustom/README.md
@@ -0,0 +1,29 @@
+# ESP RainMaker Custom Device
+
+This example demonstrates how to build a custom device to be used with ESP RainMaker.
+
+## What to expect in this example?
+
+- This example sketch uses the on board Boot button and GPIO16 to demonstrate an ESP RainMaker AC dimmer device.
+- After compiling and flashing the example, add your device using the [ESP RainMaker phone apps](https://rainmaker.espressif.com/docs/quick-links.html#phone-apps) by scanning the QR code.
+- Toggling the state from the phone app will toggle the dimmer state (GPIO16).
+- Pressing the Boot button will toggle the dimmer state (GPIO16) and the same will reflect on the phone app.
+- You can also change the Level from the phone app and see it reflect on the device as a print message.
+
+### Output
+
+```
+[    87][I][RMaker.cpp:13] event_handler(): RainMaker Initialized.
+[    94][I][WiFiProv.cpp:158] beginProvision(): Already Provisioned
+[    95][I][WiFiProv.cpp:162] beginProvision(): Attempting connect to AP: Viking007_2GEXT
+
+Received value = false for Dimmer - Power
+Toggle State to true.
+[ 22532][I][RMakerDevice.cpp:162] updateAndReportParam(): Device : Dimmer, Param Name : Power, Val : true
+
+Received value = 73 for Dimmer - Level
+```
+
+### Resetting the device
+- Press and Hold the Boot button for more than 3 seconds and then release to reset Wi-Fi configuration.
+- Press and Hold the Boot button for more than 10 seconds and then release to reset to factory defaults.
diff --git a/libraries/RainMaker/examples/RMakerCustom/RMakerCustom.ino b/libraries/RainMaker/examples/RMakerCustom/RMakerCustom.ino
new file mode 100644
index 00000000000..a652f55ac34
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerCustom/RMakerCustom.ino
@@ -0,0 +1,140 @@
+//This example demonstrates the ESP RainMaker with a custom device
+#include "RMaker.h"
+#include "WiFi.h"
+#include "WiFiProv.h"
+
+#define DEFAULT_POWER_MODE   true
+#define DEFAULT_DIMMER_LEVEL 50
+const char *service_name = "PROV_1234";
+const char *pop = "abcd1234";
+
+//GPIO for push button
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6
+static int gpio_0 = 9;
+static int gpio_dimmer = 7;
+#else
+//GPIO for virtual device
+static int gpio_0 = 0;
+static int gpio_dimmer = 16;
+#endif
+
+bool dimmer_state = true;
+
+// The framework provides some standard device types like switch, lightbulb, fan, temperature sensor.
+// But, you can also define custom devices using the 'Device' base class object, as shown here
+static Device *my_device = NULL;
+
+// WARNING: sysProvEvent is called from a separate FreeRTOS task (thread)!
+void sysProvEvent(arduino_event_t *sys_event) {
+  switch (sys_event->event_id) {
+    case ARDUINO_EVENT_PROV_START:
+#if CONFIG_IDF_TARGET_ESP32S2
+      Serial.printf("\nProvisioning Started with name \"%s\" and PoP \"%s\" on SoftAP\n", service_name, pop);
+      WiFiProv.printQR(service_name, pop, "softap");
+#else
+      Serial.printf("\nProvisioning Started with name \"%s\" and PoP \"%s\" on BLE\n", service_name, pop);
+      WiFiProv.printQR(service_name, pop, "ble");
+#endif
+      break;
+    case ARDUINO_EVENT_PROV_INIT:         WiFiProv.disableAutoStop(10000); break;
+    case ARDUINO_EVENT_PROV_CRED_SUCCESS: WiFiProv.endProvision(); break;
+    default:                              ;
+  }
+}
+
+void write_callback(Device *device, Param *param, const param_val_t val, void *priv_data, write_ctx_t *ctx) {
+  const char *device_name = device->getDeviceName();
+  const char *param_name = param->getParamName();
+
+  if (strcmp(param_name, "Power") == 0) {
+    Serial.printf("Received value = %s for %s - %s\n", val.val.b ? "true" : "false", device_name, param_name);
+    dimmer_state = val.val.b;
+    (dimmer_state == false) ? digitalWrite(gpio_dimmer, LOW) : digitalWrite(gpio_dimmer, HIGH);
+    param->updateAndReport(val);
+  } else if (strcmp(param_name, "Level") == 0) {
+    Serial.printf("\nReceived value = %d for %s - %s\n", val.val.i, device_name, param_name);
+    param->updateAndReport(val);
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  pinMode(gpio_0, INPUT);
+  pinMode(gpio_dimmer, OUTPUT);
+  digitalWrite(gpio_dimmer, DEFAULT_POWER_MODE);
+
+  Node my_node;
+  my_node = RMaker.initNode("ESP RainMaker Node");
+  my_device = new Device("Dimmer", "custom.device.dimmer", &gpio_dimmer);
+  if (!my_device) {
+    return;
+  }
+  //Create custom dimmer device
+  my_device->addNameParam();
+  my_device->addPowerParam(DEFAULT_POWER_MODE);
+  my_device->assignPrimaryParam(my_device->getParamByName(ESP_RMAKER_DEF_POWER_NAME));
+
+  //Create and add a custom level parameter
+  Param level_param("Level", "custom.param.level", value(DEFAULT_DIMMER_LEVEL), PROP_FLAG_READ | PROP_FLAG_WRITE);
+  level_param.addBounds(value(0), value(100), value(1));
+  level_param.addUIType(ESP_RMAKER_UI_SLIDER);
+  my_device->addParam(level_param);
+
+  my_device->addCb(write_callback);
+
+  //Add custom dimmer device to the node
+  my_node.addDevice(*my_device);
+
+  //This is optional
+  RMaker.enableOTA(OTA_USING_TOPICS);
+  //If you want to enable scheduling, set time zone for your region using setTimeZone().
+  //The list of available values are provided here https://rainmaker.espressif.com/docs/time-service.html
+  // RMaker.setTimeZone("Asia/Shanghai");
+  // Alternatively, enable the Timezone service and let the phone apps set the appropriate timezone
+  RMaker.enableTZService();
+
+  RMaker.enableSchedule();
+
+  RMaker.enableScenes();
+
+  RMaker.start();
+
+  WiFi.onEvent(sysProvEvent);  // Will call sysProvEvent() from another thread.
+#if CONFIG_IDF_TARGET_ESP32S2
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_SOFTAP, NETWORK_PROV_SCHEME_HANDLER_NONE, NETWORK_PROV_SECURITY_1, pop, service_name);
+#else
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_BLE, NETWORK_PROV_SCHEME_HANDLER_FREE_BTDM, NETWORK_PROV_SECURITY_1, pop, service_name);
+#endif
+}
+
+void loop() {
+  if (digitalRead(gpio_0) == LOW) {  //Push button pressed
+
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(gpio_0) == LOW) {
+      delay(50);
+    }
+    int endTime = millis();
+
+    if ((endTime - startTime) > 10000) {
+      // If key pressed for more than 10secs, reset all
+      Serial.printf("Reset to factory.\n");
+      RMakerFactoryReset(2);
+    } else if ((endTime - startTime) > 3000) {
+      Serial.printf("Reset Wi-Fi.\n");
+      // If key pressed for more than 3secs, but less than 10, reset Wi-Fi
+      RMakerWiFiReset(2);
+    } else {
+      // Toggle device state
+      dimmer_state = !dimmer_state;
+      Serial.printf("Toggle State to %s.\n", dimmer_state ? "true" : "false");
+      if (my_device) {
+        my_device->updateAndReportParam(ESP_RMAKER_DEF_POWER_NAME, dimmer_state);
+      }
+      (dimmer_state == false) ? digitalWrite(gpio_dimmer, LOW) : digitalWrite(gpio_dimmer, HIGH);
+    }
+  }
+  delay(100);
+}
diff --git a/libraries/RainMaker/examples/RMakerCustom/ci.json b/libraries/RainMaker/examples/RMakerCustom/ci.json
new file mode 100644
index 00000000000..ce63fe9ccf0
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerCustom/ci.json
@@ -0,0 +1,13 @@
+{
+  "targets": {
+    "esp32": false
+  },
+  "fqbn_append": "PartitionScheme=rainmaker_4MB",
+  "requires": [
+    "CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK=[1-9][0-9]*"
+  ],
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/RainMaker/examples/RMakerCustomAirCooler/README.md b/libraries/RainMaker/examples/RMakerCustomAirCooler/README.md
new file mode 100644
index 00000000000..2f20e45bfec
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerCustomAirCooler/README.md
@@ -0,0 +1,34 @@
+# ESP RainMaker Custom Device
+
+This example demonstrates how to build a custom device to be used with ESP RainMaker using Mode, Range and Toggle Parameters.
+
+## What to expect in this example?
+
+- This example sketch uses the on board Boot button and GPIOs 16, 17, 18, 19, 21, 22 to demonstrate an ESP RainMaker AirCooler device.
+- After compiling and flashing the example, add your device using the [ESP RainMaker phone apps](https://rainmaker.espressif.com/docs/quick-links.html#phone-apps) by scanning the QR code.
+- Toggling the power state from the phone app will toggle GPIO 16.
+- Pressing the Boot button will toggle the power state (GPIO 16) and the same will reflect on the phone app.
+- Toggling the swing state from the phone app will toggle GPIO 17.
+- Changing the mode from the phone app will toggle the GPIOs 18 (auto), 19 (cool) and 21 (heat)
+- Changing the Speed slider from the phone app will dimming GPIO 22
+- You can also change the Level from the phone app and see it reflect on the device as a print message.
+
+### Output
+
+```
+Received value = true for Air Cooler - Power
+Received value = false for Air Cooler - Power
+Received value = true for Air Cooler - Swing
+Received value = false for Air Cooler - Swing
+Received value = 0 for Air Cooler - Speed
+Received value = 255 for Air Cooler - Speed
+Received value = Auto for Air Cooler - Mode
+Received value = Cool for Air Cooler - Mode
+Received value = Heat for Air Cooler - Mode
+Toggle power state to false.
+Toggle power state to false.
+```
+
+### Resetting the device
+- Press and Hold the Boot button for more than 3 seconds and then release to reset Wi-Fi configuration.
+- Press and Hold the Boot button for more than 10 seconds and then release to reset to factory defaults.
diff --git a/libraries/RainMaker/examples/RMakerCustomAirCooler/RMakerCustomAirCooler.ino b/libraries/RainMaker/examples/RMakerCustomAirCooler/RMakerCustomAirCooler.ino
new file mode 100644
index 00000000000..559d73e771c
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerCustomAirCooler/RMakerCustomAirCooler.ino
@@ -0,0 +1,205 @@
+//This example demonstrates the ESP RainMaker with a custom Air Cooler device
+#include "RMaker.h"
+#include "WiFi.h"
+#include "WiFiProv.h"
+
+#define DEFAULT_POWER_MODE true
+#define DEFAULT_SWING      false
+#define DEFAULT_SPEED      0
+#define DEFAULT_MODE       "Auto"
+
+const char *service_name = "PROV_1234";
+const char *pop = "abcd1234";
+
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6
+//GPIO for push button
+static int gpio_reset = 9;
+//GPIO for virtual device
+static int gpio_power = 7;
+static int gpio_swing = 3;
+static int gpio_mode_auto = 4;
+static int gpio_mode_cool = 5;
+static int gpio_mode_heat = 6;
+static int gpio_speed = 10;
+
+#else
+//GPIO for push button
+static int gpio_reset = 0;
+//GPIO for virtual device
+static int gpio_power = 16;
+static int gpio_swing = 17;
+static int gpio_mode_auto = 18;
+static int gpio_mode_cool = 19;
+static int gpio_mode_heat = 21;
+static int gpio_speed = 22;
+#endif
+
+bool power_state = true;
+
+// The framework provides some standard device types like switch, lightbulb, fan, temperature sensor.
+// But, you can also define custom devices using the 'Device' base class object, as shown here
+static Device *my_device = NULL;
+
+// WARNING: sysProvEvent is called from a separate FreeRTOS task (thread)!
+void sysProvEvent(arduino_event_t *sys_event) {
+  switch (sys_event->event_id) {
+    case ARDUINO_EVENT_PROV_START:
+#if CONFIG_IDF_TARGET_ESP32S2
+      Serial.printf("\nProvisioning Started with name \"%s\" and PoP \"%s\" on SoftAP\n", service_name, pop);
+      WiFiProv.printQR(service_name, pop, "softap");
+#else
+      Serial.printf("\nProvisioning Started with name \"%s\" and PoP \"%s\" on BLE\n", service_name, pop);
+      WiFiProv.printQR(service_name, pop, "ble");
+#endif
+      break;
+    case ARDUINO_EVENT_PROV_INIT:         WiFiProv.disableAutoStop(10000); break;
+    case ARDUINO_EVENT_PROV_CRED_SUCCESS: WiFiProv.endProvision(); break;
+    default:                              ;
+  }
+}
+
+void write_callback(Device *device, Param *param, const param_val_t val, void *priv_data, write_ctx_t *ctx) {
+  const char *device_name = device->getDeviceName();
+  const char *param_name = param->getParamName();
+
+  if (strcmp(param_name, "Power") == 0) {
+    Serial.printf("Received value = %s for %s - %s\n", val.val.b ? "true" : "false", device_name, param_name);
+    power_state = val.val.b;
+    (power_state == false) ? digitalWrite(gpio_power, LOW) : digitalWrite(gpio_power, HIGH);
+    param->updateAndReport(val);
+  } else if (strcmp(param_name, "Swing") == 0) {
+    Serial.printf("\nReceived value = %s for %s - %s\n", val.val.b ? "true" : "false", device_name, param_name);
+    bool swing = val.val.b;
+    (swing == false) ? digitalWrite(gpio_swing, LOW) : digitalWrite(gpio_swing, HIGH);
+    param->updateAndReport(val);
+  } else if (strcmp(param_name, "Speed") == 0) {
+    Serial.printf("\nReceived value = %d for %s - %s\n", val.val.i, device_name, param_name);
+    int speed = val.val.i;
+    analogWrite(gpio_speed, speed);
+    param->updateAndReport(val);
+  } else if (strcmp(param_name, "Mode") == 0) {
+    const char *mode = val.val.s;
+    if (strcmp(mode, "Auto") == 0) {
+      digitalWrite(gpio_mode_auto, HIGH);
+      digitalWrite(gpio_mode_heat, LOW);
+      digitalWrite(gpio_mode_cool, LOW);
+    } else if (strcmp(mode, "Heat") == 0) {
+      digitalWrite(gpio_mode_auto, LOW);
+      digitalWrite(gpio_mode_heat, HIGH);
+      digitalWrite(gpio_mode_cool, LOW);
+    } else if (strcmp(mode, "Cool") == 0) {
+      digitalWrite(gpio_mode_auto, LOW);
+      digitalWrite(gpio_mode_heat, LOW);
+      digitalWrite(gpio_mode_cool, HIGH);
+    }
+    Serial.printf("\nReceived value = %s for %s - %s\n", val.val.s, device_name, param_name);
+    param->updateAndReport(val);
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  pinMode(gpio_reset, INPUT_PULLUP);
+  pinMode(gpio_power, OUTPUT);
+  digitalWrite(gpio_power, DEFAULT_POWER_MODE);
+  pinMode(gpio_swing, OUTPUT);
+  digitalWrite(gpio_swing, DEFAULT_SWING);
+  pinMode(gpio_mode_auto, OUTPUT);
+  if (strcmp(DEFAULT_MODE, "Auto") == 0) {
+    digitalWrite(gpio_mode_auto, HIGH);
+  }
+  pinMode(gpio_mode_cool, OUTPUT);
+  if (strcmp(DEFAULT_MODE, "Cool") == 0) {
+    digitalWrite(gpio_mode_auto, HIGH);
+  }
+  pinMode(gpio_mode_heat, OUTPUT);
+  if (strcmp(DEFAULT_MODE, "Heat") == 0) {
+    digitalWrite(gpio_mode_auto, HIGH);
+  }
+  pinMode(gpio_speed, OUTPUT);
+  analogWrite(gpio_speed, DEFAULT_SPEED);
+
+  Node my_node;
+  my_node = RMaker.initNode("ESP RainMaker Node");
+  my_device = new Device("Air Cooler", "my.device.air-cooler", NULL);
+  if (!my_device) {
+    return;
+  }
+  //Create custom air cooler device
+  my_device->addNameParam();
+  my_device->addPowerParam(DEFAULT_POWER_MODE);
+  my_device->assignPrimaryParam(my_device->getParamByName(ESP_RMAKER_DEF_POWER_NAME));
+
+  Param swing("Swing", ESP_RMAKER_PARAM_TOGGLE, value(DEFAULT_SWING), PROP_FLAG_READ | PROP_FLAG_WRITE);
+  swing.addUIType(ESP_RMAKER_UI_TOGGLE);
+  my_device->addParam(swing);
+
+  Param speed("Speed", ESP_RMAKER_PARAM_RANGE, value(DEFAULT_SPEED), PROP_FLAG_READ | PROP_FLAG_WRITE);
+  speed.addUIType(ESP_RMAKER_UI_SLIDER);
+  speed.addBounds(value(0), value(255), value(1));
+  my_device->addParam(speed);
+
+  static const char *modes[] = {"Auto", "Cool", "Heat"};
+  Param mode_param("Mode", ESP_RMAKER_PARAM_MODE, value("Auto"), PROP_FLAG_READ | PROP_FLAG_WRITE);
+  mode_param.addValidStrList(modes, 3);
+  mode_param.addUIType(ESP_RMAKER_UI_DROPDOWN);
+  my_device->addParam(mode_param);
+
+  my_device->addCb(write_callback);
+
+  //Add custom Air Cooler device to the node
+  my_node.addDevice(*my_device);
+
+  //This is optional
+  // RMaker.enableOTA(OTA_USING_TOPICS);
+  //If you want to enable scheduling, set time zone for your region using setTimeZone().
+  //The list of available values are provided here https://rainmaker.espressif.com/docs/time-service.html
+  // RMaker.setTimeZone("Asia/Shanghai");
+  //Alternatively, enable the Timezone service and let the phone apps set the appropriate timezone
+  // RMaker.enableTZService();
+
+  RMaker.enableSchedule();
+
+  RMaker.enableScenes();
+
+  RMaker.start();
+
+  WiFi.onEvent(sysProvEvent);  // Will call sysProvEvent() from another thread.
+#if CONFIG_IDF_TARGET_ESP32S2
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_SOFTAP, NETWORK_PROV_SCHEME_HANDLER_NONE, NETWORK_PROV_SECURITY_1, pop, service_name);
+#else
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_BLE, NETWORK_PROV_SCHEME_HANDLER_FREE_BTDM, NETWORK_PROV_SECURITY_1, pop, service_name);
+#endif
+}
+
+void loop() {
+  if (digitalRead(gpio_reset) == LOW) {  //Push button pressed
+
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(gpio_reset) == LOW) {
+      delay(50);
+    }
+    int press_duration = millis() - startTime;
+
+    if (press_duration > 10000) {
+      // If key pressed for more than 10secs, reset all
+      Serial.printf("Reset to factory.\n");
+      RMakerFactoryReset(2);
+    } else if (press_duration > 3000) {
+      Serial.printf("Reset Wi-Fi.\n");
+      // If key pressed for more than 3secs, but less than 10, reset Wi-Fi
+      RMakerWiFiReset(2);
+    } else {
+      // Toggle device state
+      power_state = !power_state;
+      Serial.printf("Toggle power state to %s.\n", power_state ? "true" : "false");
+      if (my_device) {
+        my_device->updateAndReportParam(ESP_RMAKER_DEF_POWER_NAME, power_state);
+      }
+      (power_state == false) ? digitalWrite(gpio_power, LOW) : digitalWrite(gpio_power, HIGH);
+    }
+  }
+  delay(100);
+}
diff --git a/libraries/RainMaker/examples/RMakerCustomAirCooler/ci.json b/libraries/RainMaker/examples/RMakerCustomAirCooler/ci.json
new file mode 100644
index 00000000000..ce63fe9ccf0
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerCustomAirCooler/ci.json
@@ -0,0 +1,13 @@
+{
+  "targets": {
+    "esp32": false
+  },
+  "fqbn_append": "PartitionScheme=rainmaker_4MB",
+  "requires": [
+    "CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK=[1-9][0-9]*"
+  ],
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/RainMaker/examples/RMakerSonoffDualR3/RMakerSonoffDualR3.ino b/libraries/RainMaker/examples/RMakerSonoffDualR3/RMakerSonoffDualR3.ino
new file mode 100644
index 00000000000..014da25c8f6
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerSonoffDualR3/RMakerSonoffDualR3.ino
@@ -0,0 +1,206 @@
+//This example demonstrates the ESP RainMaker with a standard Switch device.
+#include "RMaker.h"
+#include "WiFi.h"
+#include "WiFiProv.h"
+
+#define DEFAULT_POWER_MODE false
+const char *service_name = "PROV_SONOFF_DUALR3";
+const char *pop = "123456";
+
+// GPIO for push button
+static uint8_t gpio_reset = 0;
+// GPIO for switch
+static uint8_t gpio_switch1 = 32;
+static uint8_t gpio_switch2 = 33;
+// GPIO for virtual device
+static uint8_t gpio_relay1 = 27;
+static uint8_t gpio_relay2 = 14;
+/* Variable for reading pin status*/
+bool switch_state_ch1 = true;
+bool switch_state_ch2 = true;
+// GPIO for link status LED
+static uint8_t gpio_led = 13;
+
+struct LightSwitch {
+  const uint8_t pin;
+  bool pressed;
+};
+
+// Define the light switches for channel 1 and 2
+LightSwitch switch_ch1 = {gpio_switch1, false};
+LightSwitch switch_ch2 = {gpio_switch2, false};
+
+//The framework provides some standard device types like switch, lightbulb, fan, temperature sensor.
+static Switch *my_switch1 = NULL;
+static Switch *my_switch2 = NULL;
+
+// WARNING: sysProvEvent is called from a separate FreeRTOS task (thread)!
+void sysProvEvent(arduino_event_t *sys_event) {
+  switch (sys_event->event_id) {
+    case ARDUINO_EVENT_PROV_START:
+#if CONFIG_IDF_TARGET_ESP32
+      Serial.printf("\nProvisioning Started with name \"%s\" and PoP \"%s\" on BLE\n", service_name, pop);
+      WiFiProv.printQR(service_name, pop, "ble");
+#else
+      Serial.printf("\nProvisioning Started with name \"%s\" and PoP \"%s\" on SoftAP\n", service_name, pop);
+      WiFiProv.printQR(service_name, pop, "softap");
+#endif
+      break;
+    case ARDUINO_EVENT_WIFI_STA_CONNECTED:
+      Serial.printf("\nConnected to Wi-Fi!\n");
+      digitalWrite(gpio_led, true);
+      break;
+    case ARDUINO_EVENT_PROV_INIT:         WiFiProv.disableAutoStop(10000); break;
+    case ARDUINO_EVENT_PROV_CRED_SUCCESS: WiFiProv.endProvision(); break;
+    default:                              ;
+  }
+}
+
+void write_callback(Device *device, Param *param, const param_val_t val, void *priv_data, write_ctx_t *ctx) {
+  const char *device_name = device->getDeviceName();
+  const char *param_name = param->getParamName();
+
+  if (strcmp(device_name, "Switch_ch1") == 0) {
+
+    Serial.printf("Lightbulb = %s\n", val.val.b ? "true" : "false");
+
+    if (strcmp(param_name, "Power") == 0) {
+      Serial.printf("Received value = %s for %s - %s\n", val.val.b ? "true" : "false", device_name, param_name);
+      switch_state_ch1 = val.val.b;
+      (switch_state_ch1 == false) ? digitalWrite(gpio_relay1, LOW) : digitalWrite(gpio_relay1, HIGH);
+      param->updateAndReport(val);
+    }
+
+  } else if (strcmp(device_name, "Switch_ch2") == 0) {
+
+    Serial.printf("Switch value = %s\n", val.val.b ? "true" : "false");
+
+    if (strcmp(param_name, "Power") == 0) {
+      Serial.printf("Received value = %s for %s - %s\n", val.val.b ? "true" : "false", device_name, param_name);
+      switch_state_ch2 = val.val.b;
+      (switch_state_ch2 == false) ? digitalWrite(gpio_relay2, LOW) : digitalWrite(gpio_relay2, HIGH);
+      param->updateAndReport(val);
+    }
+  }
+}
+
+void ARDUINO_ISR_ATTR isr(void *arg) {
+  LightSwitch *s = static_cast<LightSwitch *>(arg);
+  s->pressed = true;
+}
+
+void setup() {
+
+  uint32_t chipId = 0;
+
+  Serial.begin(115200);
+
+  // Configure the input GPIOs
+  pinMode(gpio_reset, INPUT);
+  pinMode(switch_ch1.pin, INPUT_PULLUP);
+  attachInterruptArg(switch_ch1.pin, isr, &switch_ch1, CHANGE);
+  pinMode(switch_ch2.pin, INPUT_PULLUP);
+  attachInterruptArg(switch_ch2.pin, isr, &switch_ch2, CHANGE);
+
+  // Set the Relays GPIOs as output mode
+  pinMode(gpio_relay1, OUTPUT);
+  pinMode(gpio_relay2, OUTPUT);
+  pinMode(gpio_led, OUTPUT);
+  // Write to the GPIOs the default state on booting
+  digitalWrite(gpio_relay1, DEFAULT_POWER_MODE);
+  digitalWrite(gpio_relay2, DEFAULT_POWER_MODE);
+  digitalWrite(gpio_led, false);
+
+  Node my_node;
+  my_node = RMaker.initNode("Sonoff Dual R3");
+
+  //Initialize switch device
+  my_switch1 = new Switch("Switch_ch1", &gpio_relay1);
+  my_switch2 = new Switch("Switch_ch2", &gpio_relay2);
+
+  if (!my_switch1 || !my_switch2) {
+    return;
+  }
+  //Standard switch device
+  my_switch1->addCb(write_callback);
+  my_switch2->addCb(write_callback);
+
+  //Add switch device to the node
+  my_node.addDevice(*my_switch1);
+  my_node.addDevice(*my_switch2);
+
+  //This is optional
+  RMaker.enableOTA(OTA_USING_TOPICS);
+  //If you want to enable scheduling, set time zone for your region using setTimeZone().
+  //The list of available values are provided here https://rainmaker.espressif.com/docs/time-service.html
+  // RMaker.setTimeZone("Asia/Shanghai");
+  // Alternatively, enable the Timezone service and let the phone apps set the appropriate timezone
+  RMaker.enableTZService();
+  RMaker.enableSchedule();
+  RMaker.enableScenes();
+
+  //Service Name
+  for (int i = 0; i < 17; i = i + 8) {
+    chipId |= ((ESP.getEfuseMac() >> (40 - i)) & 0xff) << i;
+  }
+
+  Serial.printf("\nChip ID:  %lu Service Name: %s\n", chipId, service_name);
+
+  Serial.printf("\nStarting ESP-RainMaker\n");
+  RMaker.start();
+
+  WiFi.onEvent(sysProvEvent);  // Will call sysProvEvent() from another thread.
+#if CONFIG_IDF_TARGET_ESP32
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_BLE, NETWORK_PROV_SCHEME_HANDLER_FREE_BTDM, NETWORK_PROV_SECURITY_1, pop, service_name);
+#else
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_SOFTAP, NETWORK_PROV_SCHEME_HANDLER_NONE, NETWORK_PROV_SECURITY_1, pop, service_name);
+#endif
+}
+
+void loop() {
+
+  if (switch_ch1.pressed) {
+    Serial.printf("Switch 1 has been changed\n");
+    switch_ch1.pressed = false;
+    // Toggle switch 1 device state
+    switch_state_ch1 = !switch_state_ch1;
+    Serial.printf("Toggle State to %s.\n", switch_state_ch1 ? "true" : "false");
+    if (my_switch1) {
+      my_switch1->updateAndReportParam(ESP_RMAKER_DEF_POWER_NAME, switch_state_ch1);
+    }
+    (switch_state_ch1 == false) ? digitalWrite(gpio_relay1, LOW) : digitalWrite(gpio_relay1, HIGH);
+  } else if (switch_ch2.pressed) {
+    Serial.printf("Switch 2 has been changed\n");
+    switch_ch2.pressed = false;
+    // Toggle switch 2 device state
+    switch_state_ch2 = !switch_state_ch2;
+    Serial.printf("Toggle State to %s.\n", switch_state_ch2 ? "true" : "false");
+    if (my_switch2) {
+      my_switch2->updateAndReportParam(ESP_RMAKER_DEF_POWER_NAME, switch_state_ch2);
+    }
+    (switch_state_ch2 == false) ? digitalWrite(gpio_relay2, LOW) : digitalWrite(gpio_relay2, HIGH);
+  }
+
+  // Read GPIO0 (external button to reset device
+  if (digitalRead(gpio_reset) == LOW) {  //Push button pressed
+    Serial.printf("Reset Button Pressed!\n");
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(gpio_reset) == LOW) {
+      delay(50);
+    }
+    int endTime = millis();
+
+    if ((endTime - startTime) > 10000) {
+      // If key pressed for more than 10secs, reset all
+      Serial.printf("Reset to factory.\n");
+      RMakerFactoryReset(2);
+    } else if ((endTime - startTime) > 3000) {
+      Serial.printf("Reset Wi-Fi.\n");
+      // If key pressed for more than 3secs, but less than 10, reset Wi-Fi
+      RMakerWiFiReset(2);
+    }
+  }
+  delay(100);
+}
diff --git a/libraries/RainMaker/examples/RMakerSonoffDualR3/ci.json b/libraries/RainMaker/examples/RMakerSonoffDualR3/ci.json
new file mode 100644
index 00000000000..ce63fe9ccf0
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerSonoffDualR3/ci.json
@@ -0,0 +1,13 @@
+{
+  "targets": {
+    "esp32": false
+  },
+  "fqbn_append": "PartitionScheme=rainmaker_4MB",
+  "requires": [
+    "CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK=[1-9][0-9]*"
+  ],
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/RainMaker/examples/RMakerSwitch/README.md b/libraries/RainMaker/examples/RMakerSwitch/README.md
new file mode 100644
index 00000000000..4d8a38d8ad0
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerSwitch/README.md
@@ -0,0 +1,31 @@
+# ESP RainMaker Switch
+
+This example demonstrates how to build a switch device to be used with ESP RainMaker.
+
+## What to expect in this example?
+
+- This example sketch uses the on board Boot button and GPIO16 to demonstrate an ESP RainMaker switch device.
+- After compiling and flashing the example, add your device using the [ESP RainMaker phone apps](https://rainmaker.espressif.com/docs/quick-links.html#phone-apps) by scanning the QR code.
+- Toggling the state from the phone app will toggle the switch state (GPIO16).
+- Pressing the Boot button will toggle the switch state (GPIO16) and the same will reflect on the phone app.
+
+### Output
+
+```
+[    63][I][RMaker.cpp:13] event_handler(): RainMaker Initialized.
+[    69][I][WiFiProv.cpp:158] beginProvision(): Already Provisioned
+[    69][I][WiFiProv.cpp:162] beginProvision(): Attempting connect to AP: Viking007_2GEXT
+
+Toggle State to false.
+[  8182][I][RMakerDevice.cpp:162] updateAndReportParam(): Device : Switch, Param Name : Power, Val : false
+Toggle State to true.
+[  9835][I][RMakerDevice.cpp:162] updateAndReportParam(): Device : Switch, Param Name : Power, Val : true
+Received value = false for Switch - Power
+Received value = true for Switch - Power
+Toggle State to false.
+[ 29937][I][RMakerDevice.cpp:162] updateAndReportParam(): Device : Switch, Param Name : Power, Val : false
+```
+
+### Resetting the device
+- Press and Hold the Boot button for more than 3 seconds and then release to reset Wi-Fi configuration.
+- Press and Hold the Boot button for more than 10 seconds and then release to reset to factory defaults.
diff --git a/libraries/RainMaker/examples/RMakerSwitch/RMakerSwitch.ino b/libraries/RainMaker/examples/RMakerSwitch/RMakerSwitch.ino
new file mode 100644
index 00000000000..21fe9cb064b
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerSwitch/RMakerSwitch.ino
@@ -0,0 +1,143 @@
+// This example demonstrates the ESP RainMaker with a standard Switch device.
+#include "RMaker.h"
+#include "WiFi.h"
+#include "WiFiProv.h"
+#include "AppInsights.h"
+
+#define DEFAULT_POWER_MODE true
+const char *service_name = "PROV_1234";
+const char *pop = "abcd1234";
+
+// GPIO for push button
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6
+static int gpio_0 = 9;
+static int gpio_switch = 7;
+#else
+// GPIO for virtual device
+static int gpio_0 = 0;
+static int gpio_switch = 16;
+#endif
+
+/* Variable for reading pin status*/
+bool switch_state = true;
+
+// The framework provides some standard device types like switch, lightbulb,
+// fan, temperaturesensor.
+static Switch *my_switch = NULL;
+
+// WARNING: sysProvEvent is called from a separate FreeRTOS task (thread)!
+void sysProvEvent(arduino_event_t *sys_event) {
+  switch (sys_event->event_id) {
+    case ARDUINO_EVENT_PROV_START:
+#if CONFIG_IDF_TARGET_ESP32S2
+      Serial.printf("\nProvisioning Started with name \"%s\" and PoP \"%s\" on SoftAP\n", service_name, pop);
+      WiFiProv.printQR(service_name, pop, "softap");
+#else
+      Serial.printf("\nProvisioning Started with name \"%s\" and PoP \"%s\" on BLE\n", service_name, pop);
+      WiFiProv.printQR(service_name, pop, "ble");
+#endif
+      break;
+    case ARDUINO_EVENT_PROV_INIT:         WiFiProv.disableAutoStop(10000); break;
+    case ARDUINO_EVENT_PROV_CRED_SUCCESS: WiFiProv.endProvision(); break;
+    default:                              ;
+  }
+}
+
+void write_callback(Device *device, Param *param, const param_val_t val, void *priv_data, write_ctx_t *ctx) {
+  const char *device_name = device->getDeviceName();
+  const char *param_name = param->getParamName();
+
+  if (strcmp(param_name, "Power") == 0) {
+    Serial.printf("Received value = %s for %s - %s\n", val.val.b ? "true" : "false", device_name, param_name);
+    switch_state = val.val.b;
+    (switch_state == false) ? digitalWrite(gpio_switch, LOW) : digitalWrite(gpio_switch, HIGH);
+    param->updateAndReport(val);
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  pinMode(gpio_0, INPUT);
+  pinMode(gpio_switch, OUTPUT);
+  digitalWrite(gpio_switch, DEFAULT_POWER_MODE);
+
+  Node my_node;
+  my_node = RMaker.initNode("ESP RainMaker Node");
+
+  // Initialize switch device
+  my_switch = new Switch("Switch", &gpio_switch);
+  if (!my_switch) {
+    return;
+  }
+  // Standard switch device
+  my_switch->addCb(write_callback);
+
+  // Add switch device to the node
+  my_node.addDevice(*my_switch);
+
+  // This is optional
+  RMaker.enableOTA(OTA_USING_TOPICS);
+  // If you want to enable scheduling, set time zone for your region using
+  // setTimeZone(). The list of available values are provided here
+  // https://rainmaker.espressif.com/docs/time-service.html
+  //  RMaker.setTimeZone("Asia/Shanghai");
+  //  Alternatively, enable the Timezone service and let the phone apps set the
+  //  appropriate timezone
+  RMaker.enableTZService();
+
+  RMaker.enableSchedule();
+
+  RMaker.enableScenes();
+  // Enable ESP Insights. Insteads of using the default http transport, this function will
+  // reuse the existing MQTT connection of Rainmaker, thereby saving memory space.
+  initAppInsights();
+
+  RMaker.enableSystemService(SYSTEM_SERV_FLAGS_ALL, 2, 2, 2);
+
+#if CONFIG_IDF_TARGET_ESP32S2
+  WiFiProv.initProvision(NETWORK_PROV_SCHEME_SOFTAP, NETWORK_PROV_SCHEME_HANDLER_NONE);
+#else
+  WiFiProv.initProvision(NETWORK_PROV_SCHEME_BLE, NETWORK_PROV_SCHEME_HANDLER_FREE_BTDM);
+#endif
+
+  RMaker.start();
+
+  WiFi.onEvent(sysProvEvent);  // Will call sysProvEvent() from another thread.
+#if CONFIG_IDF_TARGET_ESP32S2
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_SOFTAP, NETWORK_PROV_SCHEME_HANDLER_NONE, NETWORK_PROV_SECURITY_1, pop, service_name);
+#else
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_BLE, NETWORK_PROV_SCHEME_HANDLER_FREE_BTDM, NETWORK_PROV_SECURITY_1, pop, service_name);
+#endif
+}
+
+void loop() {
+  if (digitalRead(gpio_0) == LOW) {  // Push button pressed
+
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(gpio_0) == LOW) {
+      delay(50);
+    }
+    int endTime = millis();
+
+    if ((endTime - startTime) > 10000) {
+      // If key pressed for more than 10secs, reset all
+      Serial.printf("Reset to factory.\n");
+      RMakerFactoryReset(2);
+    } else if ((endTime - startTime) > 3000) {
+      Serial.printf("Reset Wi-Fi.\n");
+      // If key pressed for more than 3secs, but less than 10, reset Wi-Fi
+      RMakerWiFiReset(2);
+    } else {
+      // Toggle device state
+      switch_state = !switch_state;
+      Serial.printf("Toggle State to %s.\n", switch_state ? "true" : "false");
+      if (my_switch) {
+        my_switch->updateAndReportParam(ESP_RMAKER_DEF_POWER_NAME, switch_state);
+      }
+      (switch_state == false) ? digitalWrite(gpio_switch, LOW) : digitalWrite(gpio_switch, HIGH);
+    }
+  }
+  delay(100);
+}
diff --git a/libraries/RainMaker/examples/RMakerSwitch/ci.json b/libraries/RainMaker/examples/RMakerSwitch/ci.json
new file mode 100644
index 00000000000..ce63fe9ccf0
--- /dev/null
+++ b/libraries/RainMaker/examples/RMakerSwitch/ci.json
@@ -0,0 +1,13 @@
+{
+  "targets": {
+    "esp32": false
+  },
+  "fqbn_append": "PartitionScheme=rainmaker_4MB",
+  "requires": [
+    "CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK=[1-9][0-9]*"
+  ],
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/RainMaker/library.properties b/libraries/RainMaker/library.properties
new file mode 100644
index 00000000000..95ce14d6708
--- /dev/null
+++ b/libraries/RainMaker/library.properties
@@ -0,0 +1,8 @@
+name=ESP RainMaker
+version=3.2.0
+author=Sweety Mhaiske <switi.mhaiske@espressif.com>
+maintainer=Hristo Gochkov <hristo@espressif.com>
+sentence=ESP RainMaker Support
+paragraph=With this library you can build connected devices and access them via phone apps without having to manage the infrastructure.
+url=https://rainmaker.espressif.com
+architectures=esp32,esp32s2
diff --git a/libraries/RainMaker/src/AppInsights.cpp b/libraries/RainMaker/src/AppInsights.cpp
new file mode 100644
index 00000000000..85361b93873
--- /dev/null
+++ b/libraries/RainMaker/src/AppInsights.cpp
@@ -0,0 +1,76 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+#include <inttypes.h>
+#if defined(CONFIG_ESP_INSIGHTS_ENABLED) && defined(CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK)
+#include "Arduino.h"
+#include "AppInsights.h"
+#include "Insights.h"
+#include <esp_rmaker_mqtt.h>
+#include <esp_insights.h>
+#include <esp_diagnostics.h>
+#include <esp_rmaker_core.h>
+#include <esp_rmaker_common_events.h>
+
+extern "C" {
+bool esp_rmaker_mqtt_is_budget_available();
+}
+
+#define INSIGHTS_TOPIC_SUFFIX "diagnostics/from-node"
+#define INSIGHTS_TOPIC_RULE   "insights_message_delivery"
+
+static void _rmakerCommonEventHandler(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base != RMAKER_COMMON_EVENT) {
+    return;
+  }
+  esp_insights_transport_event_data_t data;
+  switch (event_id) {
+    case RMAKER_MQTT_EVENT_PUBLISHED:
+      memset(&data, 0, sizeof(data));
+      data.msg_id = *(int *)event_data;
+      esp_event_post(INSIGHTS_EVENT, INSIGHTS_EVENT_TRANSPORT_SEND_SUCCESS, &data, sizeof(data), portMAX_DELAY);
+      break;
+    default: break;
+  }
+}
+
+static int _appInsightsDataSend(void *data, size_t len) {
+  char topic[128];
+  int msg_id = -1;
+  if (data == NULL) {
+    return 0;
+  }
+  char *node_id = esp_rmaker_get_node_id();
+  if (!node_id) {
+    return -1;
+  }
+  if (esp_rmaker_mqtt_is_budget_available() == false) {
+    return ESP_FAIL;
+  }
+  esp_rmaker_create_mqtt_topic(topic, sizeof(topic), INSIGHTS_TOPIC_SUFFIX, INSIGHTS_TOPIC_RULE);
+  esp_rmaker_mqtt_publish(topic, data, len, RMAKER_MQTT_QOS1, &msg_id);
+  return msg_id;
+}
+
+bool initAppInsights(uint32_t log_type, bool alloc_ext_ram) {
+  char *node_id = esp_rmaker_get_node_id();
+  esp_insights_transport_config_t transport;
+  transport.userdata = NULL;
+  transport.callbacks.data_send = _appInsightsDataSend;
+  transport.callbacks.init = NULL;
+  transport.callbacks.deinit = NULL;
+  transport.callbacks.connect = NULL;
+  transport.callbacks.disconnect = NULL;
+  esp_insights_transport_register(&transport);
+  esp_event_handler_register(RMAKER_COMMON_EVENT, ESP_EVENT_ANY_ID, _rmakerCommonEventHandler, NULL);
+  return Insights.begin(NULL, node_id, log_type, alloc_ext_ram, false);
+}
+#else
+bool initAppInsights(uint32_t log_type, bool alloc_ext_ram) {
+  return false;
+}
+#endif
diff --git a/libraries/RainMaker/src/AppInsights.h b/libraries/RainMaker/src/AppInsights.h
new file mode 100644
index 00000000000..ddb32f1e266
--- /dev/null
+++ b/libraries/RainMaker/src/AppInsights.h
@@ -0,0 +1,12 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include "sdkconfig.h"
+#include "Arduino.h"
+#include <inttypes.h>
+
+bool initAppInsights(uint32_t log_type = 0xffffffff, bool alloc_ext_ram = false);
diff --git a/libraries/RainMaker/src/RMaker.cpp b/libraries/RainMaker/src/RMaker.cpp
new file mode 100644
index 00000000000..0f8f276cbb9
--- /dev/null
+++ b/libraries/RainMaker/src/RMaker.cpp
@@ -0,0 +1,144 @@
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "RMaker.h"
+#include <esp_rmaker_schedule.h>
+#include <esp_rmaker_utils.h>
+#include <esp_rmaker_scenes.h>
+#include <esp_rmaker_common_events.h>
+bool wifiLowLevelInit(bool persistent);
+static esp_err_t err;
+
+extern "C" bool verifyRollbackLater() {
+  return true;
+}
+
+static void event_handler(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == RMAKER_EVENT) {
+    switch (event_id) {
+      case RMAKER_EVENT_INIT_DONE:        log_i("RainMaker Initialized."); break;
+      case RMAKER_EVENT_CLAIM_STARTED:    log_i("RainMaker Claim Started."); break;
+      case RMAKER_EVENT_CLAIM_SUCCESSFUL: log_i("RainMaker Claim Successful."); break;
+      case RMAKER_EVENT_CLAIM_FAILED:     log_i("RainMaker Claim Failed."); break;
+      default:                            log_i("Unhandled RainMaker Event:");
+    }
+  } else if (event_base == RMAKER_COMMON_EVENT) {
+    switch (event_id) {
+      case RMAKER_EVENT_REBOOT:            log_i("Rebooting in %d seconds.", *((uint8_t *)event_data)); break;
+      case RMAKER_EVENT_WIFI_RESET:        log_i("Wi-Fi credentials reset."); break;
+      case RMAKER_EVENT_FACTORY_RESET:     log_i("Node reset to factory defaults."); break;
+      case RMAKER_MQTT_EVENT_CONNECTED:    log_i("MQTT Connected."); break;
+      case RMAKER_MQTT_EVENT_DISCONNECTED: log_i("MQTT Disconnected."); break;
+      case RMAKER_MQTT_EVENT_PUBLISHED:    log_i("MQTT Published. Msg id: %d.", *((int *)event_data)); break;
+      default:                             log_w("Unhandled RainMaker Common Event: %" PRIi32, event_id);
+    }
+  } else if (event_base == RMAKER_OTA_EVENT) {
+    if (event_data == NULL) {
+      event_data = (void *)"";
+    }
+    switch (event_id) {
+      case RMAKER_OTA_EVENT_STARTING:    log_i("Starting OTA"); break;
+      case RMAKER_OTA_EVENT_IN_PROGRESS: log_i("OTA in progress : %s", (char *)event_data); break;
+      case RMAKER_OTA_EVENT_SUCCESSFUL:  log_i("OTA Successful : %s", (char *)event_data); break;
+      case RMAKER_OTA_EVENT_FAILED:      log_i("OTA Failed : %s", (char *)event_data); break;
+      case RMAKER_OTA_EVENT_DELAYED:     log_i("OTA Delayed : %s", (char *)event_data); break;
+      case RMAKER_OTA_EVENT_REJECTED:    log_i("OTA Rejected : %s", (char *)event_data); break;
+      default:                           log_i("Unhandled OTA Event"); break;
+    }
+  }
+}
+
+void RMakerClass::setTimeSync(bool val) {
+  rainmaker_cfg.enable_time_sync = val;
+}
+
+Node RMakerClass::initNode(const char *name, const char *type) {
+  wifiLowLevelInit(true);
+  Node node;
+  esp_rmaker_node_t *rnode = NULL;
+  esp_event_handler_register(RMAKER_EVENT, ESP_EVENT_ANY_ID, &event_handler, NULL);
+  esp_event_handler_register(RMAKER_OTA_EVENT, ESP_EVENT_ANY_ID, &event_handler, NULL);
+  esp_event_handler_register(RMAKER_COMMON_EVENT, ESP_EVENT_ANY_ID, &event_handler, NULL);
+  rnode = esp_rmaker_node_init(&rainmaker_cfg, name, type);
+  if (!rnode) {
+    log_e("Node init failed");
+    return node;
+  }
+  node.setNodeHandle(rnode);
+  return node;
+}
+
+esp_err_t RMakerClass::start() {
+  err = esp_rmaker_start();
+  if (err != ESP_OK) {
+    log_e("ESP RainMaker core task failed");
+  }
+  return err;
+}
+
+esp_err_t RMakerClass::stop() {
+  err = esp_rmaker_stop();
+  if (err != ESP_OK) {
+    log_e("ESP RainMaker stop error");
+  }
+  return err;
+}
+
+esp_err_t RMakerClass::deinitNode(Node rnode) {
+  err = esp_rmaker_node_deinit(rnode.getNodeHandle());
+  if (err != ESP_OK) {
+    log_e("Node deinit failed");
+  }
+  return err;
+}
+
+esp_err_t RMakerClass::setTimeZone(const char *tz) {
+  err = esp_rmaker_time_set_timezone(tz);
+  if (err != ESP_OK) {
+    log_e("Setting time zone error");
+  }
+  return err;
+}
+
+esp_err_t RMakerClass::enableSchedule() {
+  err = esp_rmaker_schedule_enable();
+  if (err != ESP_OK) {
+    log_e("Schedule enable failed");
+  }
+  return err;
+}
+
+esp_err_t RMakerClass::enableTZService() {
+  err = esp_rmaker_timezone_service_enable();
+  if (err != ESP_OK) {
+    log_e("Timezone service enable failed");
+  }
+  return err;
+}
+
+esp_err_t RMakerClass::enableOTA(ota_type_t type, const char *cert) {
+  esp_rmaker_ota_config_t ota_config = {.ota_cb = NULL, .ota_diag = NULL, .server_cert = cert, .priv = NULL};
+  err = esp_rmaker_ota_enable(&ota_config, type);
+  if (err != ESP_OK) {
+    log_e("OTA enable failed");
+  }
+  return err;
+}
+
+esp_err_t RMakerClass::enableScenes() {
+  err = esp_rmaker_scenes_enable();
+  if (err != ESP_OK) {
+    log_e("Scenes enable failed");
+  }
+  return err;
+}
+
+esp_err_t RMakerClass::enableSystemService(uint16_t flags, int8_t reboot_seconds, int8_t reset_seconds, int8_t reset_reboot_seconds) {
+  esp_rmaker_system_serv_config_t config = {
+    .flags = flags, .reboot_seconds = reboot_seconds, .reset_seconds = reset_seconds, .reset_reboot_seconds = reset_reboot_seconds
+  };
+  err = esp_rmaker_system_service_enable(&config);
+  return err;
+}
+
+RMakerClass RMaker;
+#endif
diff --git a/libraries/RainMaker/src/RMaker.h b/libraries/RainMaker/src/RMaker.h
new file mode 100644
index 00000000000..21c5b0d1832
--- /dev/null
+++ b/libraries/RainMaker/src/RMaker.h
@@ -0,0 +1,43 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "esp_system.h"
+#include "Arduino.h"
+#include "RMakerNode.h"
+#include "RMakerQR.h"
+#include "RMakerUtils.h"
+#include <esp_rmaker_standard_types.h>
+
+class RMakerClass {
+private:
+  esp_rmaker_config_t rainmaker_cfg = {false};
+
+public:
+  void setTimeSync(bool val);
+  Node initNode(const char *name, const char *type = "ESP RainMaker with Arduino");
+  esp_err_t deinitNode(Node node);
+  esp_err_t setTimeZone(const char *tz = "Asia/Shanghai");
+  esp_err_t enableSchedule();
+  esp_err_t enableTZService();
+  esp_err_t enableOTA(ota_type_t type, const char *cert = ESP_RMAKER_OTA_DEFAULT_SERVER_CERT);
+  esp_err_t enableScenes();
+  esp_err_t enableSystemService(uint16_t flags, int8_t reboot_seconds = 2, int8_t reset_seconds = 2, int8_t reset_reboot_seconds = 2);
+  esp_err_t start();
+  esp_err_t stop();
+};
+
+extern RMakerClass RMaker;
+#endif
diff --git a/libraries/RainMaker/src/RMakerDevice.cpp b/libraries/RainMaker/src/RMakerDevice.cpp
new file mode 100644
index 00000000000..db431ba10c1
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerDevice.cpp
@@ -0,0 +1,190 @@
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "RMakerDevice.h"
+
+static esp_err_t err;
+typedef void (*deviceWriteCb)(Device *, Param *, const param_val_t val, void *priv_data, write_ctx_t *ctx);
+typedef void (*deviceReadCb)(Device *, Param *, void *priv_data, read_ctx_t *ctx);
+typedef struct {
+  void *priv_data;
+  deviceWriteCb write_cb;
+  deviceReadCb read_cb;
+} RMakerDevicePrivT;
+
+static esp_err_t write_callback(const device_handle_t *dev_handle, const param_handle_t *par_handle, const param_val_t val, void *priv_data, write_ctx_t *ctx) {
+  Device device;
+  Param param;
+  device.setDeviceHandle(dev_handle);
+  param.setParamHandle(par_handle);
+  deviceWriteCb cb = ((RMakerDevicePrivT *)priv_data)->write_cb;
+  cb(&device, &param, val, ((RMakerDevicePrivT *)priv_data)->priv_data, ctx);
+  return ESP_OK;
+}
+
+static esp_err_t read_callback(const device_handle_t *dev_handle, const param_handle_t *par_handle, void *priv_data, read_ctx_t *ctx) {
+  Device device;
+  Param param;
+  device.setDeviceHandle(dev_handle);
+  param.setParamHandle(par_handle);
+  deviceReadCb cb = ((RMakerDevicePrivT *)priv_data)->read_cb;
+  cb(&device, &param, ((RMakerDevicePrivT *)priv_data)->priv_data, ctx);
+  return ESP_OK;
+}
+
+esp_err_t Device::deleteDevice() {
+  err = esp_rmaker_device_delete(getDeviceHandle());
+  if (err != ESP_OK) {
+    log_e("Failed to delete device");
+    return err;
+  }
+  return ESP_OK;
+}
+
+void Device::addCb(deviceWriteCb writeCb, deviceReadCb readCb) {
+  this->private_data.write_cb = writeCb;
+  this->private_data.read_cb = readCb;
+  err = esp_rmaker_device_add_cb(getDeviceHandle(), write_callback, read_callback);
+  if (err != ESP_OK) {
+    log_e("Failed to register callback");
+  }
+}
+
+esp_err_t Device::addDeviceAttr(const char *attr_name, const char *val) {
+  err = esp_rmaker_device_add_attribute(getDeviceHandle(), attr_name, val);
+  if (err != ESP_OK) {
+    log_e("Failed to add attribute to the device");
+    return err;
+  }
+  return ESP_OK;
+}
+
+//Generic Parameter
+esp_err_t Device::addParam(Param parameter) {
+  err = esp_rmaker_device_add_param(getDeviceHandle(), parameter.getParamHandle());
+  if (err != ESP_OK) {
+    log_e("Failed to add custom parameter");
+    return err;
+  }
+  return ESP_OK;
+}
+
+//Standard Device Parameter
+esp_err_t Device::addNameParam(const char *param_name) {
+  param_handle_t *param = esp_rmaker_name_param_create(param_name, getDeviceName());
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+esp_err_t Device::addPowerParam(bool val, const char *param_name) {
+  param_handle_t *param = esp_rmaker_power_param_create(param_name, val);
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+esp_err_t Device::addBrightnessParam(int val, const char *param_name) {
+  param_handle_t *param = esp_rmaker_brightness_param_create(param_name, val);
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+esp_err_t Device::addHueParam(int val, const char *param_name) {
+  param_handle_t *param = esp_rmaker_hue_param_create(param_name, val);
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+esp_err_t Device::addSaturationParam(int val, const char *param_name) {
+  param_handle_t *param = esp_rmaker_saturation_param_create(param_name, val);
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+esp_err_t Device::addIntensityParam(int val, const char *param_name) {
+  param_handle_t *param = esp_rmaker_intensity_param_create(param_name, val);
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+esp_err_t Device::addCCTParam(int val, const char *param_name) {
+  param_handle_t *param = esp_rmaker_cct_param_create(param_name, val);
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+esp_err_t Device::addDirectionParam(int val, const char *param_name) {
+  param_handle_t *param = esp_rmaker_direction_param_create(param_name, val);
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+esp_err_t Device::addSpeedParam(int val, const char *param_name) {
+  param_handle_t *param = esp_rmaker_speed_param_create(param_name, val);
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+esp_err_t Device::addTemperatureParam(float val, const char *param_name) {
+  param_handle_t *param = esp_rmaker_temperature_param_create(param_name, val);
+  return esp_rmaker_device_add_param(getDeviceHandle(), param);
+}
+
+param_handle_t *Device::getParamByName(const char *param_name) {
+  return esp_rmaker_device_get_param_by_name(getDeviceHandle(), param_name);
+}
+
+esp_err_t Device::assignPrimaryParam(param_handle_t *param) {
+  err = esp_rmaker_device_assign_primary_param(getDeviceHandle(), param);
+  if (err != ESP_OK) {
+    log_e("Failed to assign primary parameter");
+  }
+  return err;
+}
+
+const param_handle_t *getParamHandlebyName(const esp_rmaker_device_t *device_handle, const char *param_name) {
+  const param_handle_t *param = esp_rmaker_device_get_param_by_name(device_handle, param_name);
+  return param;
+}
+
+esp_err_t Device::updateAndReportParam(const char *param_name, bool my_val) {
+  const param_handle_t *param = getParamHandlebyName(getDeviceHandle(), param_name);
+  param_val_t val = esp_rmaker_bool(my_val);
+  err = esp_rmaker_param_update_and_report(param, val);
+  if (err != ESP_OK) {
+    log_e("Update parameter failed");
+    return err;
+  } else {
+    log_i("Device : %s, Param Name : %s, Val : %s", getDeviceName(), param_name, my_val ? "true" : "false");
+  }
+  return ESP_OK;
+}
+
+esp_err_t Device::updateAndReportParam(const char *param_name, int my_val) {
+  const param_handle_t *param = getParamHandlebyName(getDeviceHandle(), param_name);
+  param_val_t val = esp_rmaker_int(my_val);
+  esp_err_t err = esp_rmaker_param_update_and_report(param, val);
+  if (err != ESP_OK) {
+    log_e("Update parameter failed");
+    return err;
+  } else {
+    log_i("Device : %s, Param Name : %s, Val : %d", getDeviceName(), param_name, my_val);
+  }
+  return ESP_OK;
+}
+
+esp_err_t Device::updateAndReportParam(const char *param_name, float my_val) {
+  const param_handle_t *param = getParamHandlebyName(getDeviceHandle(), param_name);
+  param_val_t val = esp_rmaker_float(my_val);
+  esp_err_t err = esp_rmaker_param_update_and_report(param, val);
+  if (err != ESP_OK) {
+    log_e("Update parameter failed");
+    return err;
+  } else {
+    log_i("Device : %s, Param Name : %s, Val : %f", getDeviceName(), param_name, my_val);
+  }
+  return ESP_OK;
+}
+
+esp_err_t Device::updateAndReportParam(const char *param_name, const char *my_val) {
+  const param_handle_t *param = getParamHandlebyName(getDeviceHandle(), param_name);
+  param_val_t val = esp_rmaker_str(my_val);
+  esp_err_t err = esp_rmaker_param_update_and_report(param, val);
+  if (err != ESP_OK) {
+    log_e("Update parameter failed");
+    return err;
+  } else {
+    log_i("Device : %s, Param Name : %s, Val : %s", getDeviceName(), param_name, my_val);
+  }
+  return ESP_OK;
+}
+#endif
diff --git a/libraries/RainMaker/src/RMakerDevice.h b/libraries/RainMaker/src/RMakerDevice.h
new file mode 100644
index 00000000000..29f9f1950e6
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerDevice.h
@@ -0,0 +1,170 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "esp_system.h"
+#include "RMakerParam.h"
+#include <esp_rmaker_standard_devices.h>
+#include <esp_rmaker_standard_params.h>
+
+class Device {
+public:
+  typedef void (*deviceWriteCb)(Device *, Param *, const param_val_t val, void *priv_data, write_ctx_t *ctx);
+  typedef void (*deviceReadCb)(Device *, Param *, void *priv_data, read_ctx_t *ctx);
+  typedef struct {
+    void *priv_data;
+    deviceWriteCb write_cb;
+    deviceReadCb read_cb;
+  } RMakerDevicePrivT;
+
+private:
+  const device_handle_t *device_handle;
+  RMakerDevicePrivT private_data;
+
+protected:
+  void setPrivateData(void *priv_data) {
+    this->private_data.priv_data = priv_data;
+  }
+
+  const RMakerDevicePrivT *getDevicePrivateData() {
+    return &this->private_data;
+  }
+
+public:
+  Device() {
+    device_handle = NULL;
+    this->private_data.priv_data = NULL;
+    this->private_data.write_cb = NULL;
+    this->private_data.read_cb = NULL;
+  }
+
+  Device(const char *dev_name, const char *dev_type = NULL, void *priv_data = NULL) {
+    this->private_data.priv_data = priv_data;
+    this->private_data.write_cb = NULL;
+    this->private_data.read_cb = NULL;
+    device_handle = esp_rmaker_device_create(dev_name, dev_type, &this->private_data);
+    if (device_handle == NULL) {
+      log_e("Device create error");
+    }
+  }
+  void setDeviceHandle(const esp_rmaker_device_t *device_handle) {
+    this->device_handle = device_handle;
+  }
+  const char *getDeviceName() {
+    return esp_rmaker_device_get_name(device_handle);
+  }
+  const esp_rmaker_device_t *getDeviceHandle() {
+    return device_handle;
+  }
+
+  esp_err_t deleteDevice();
+  void addCb(deviceWriteCb write_cb, deviceReadCb read_cb = NULL);
+  esp_err_t addDeviceAttr(const char *attr_name, const char *val);
+  param_handle_t *getParamByName(const char *param_name);
+  esp_err_t assignPrimaryParam(param_handle_t *param);
+
+  //Generic Device Parameter
+  esp_err_t addParam(Param parameter);
+
+  //Standard Device Parameter
+  esp_err_t addNameParam(const char *param_name = ESP_RMAKER_DEF_NAME_PARAM);
+  esp_err_t addPowerParam(bool val, const char *param_name = ESP_RMAKER_DEF_POWER_NAME);
+  esp_err_t addBrightnessParam(int val, const char *param_name = ESP_RMAKER_DEF_BRIGHTNESS_NAME);
+  esp_err_t addHueParam(int val, const char *param_name = ESP_RMAKER_DEF_HUE_NAME);
+  esp_err_t addSaturationParam(int val, const char *param_name = ESP_RMAKER_DEF_SATURATION_NAME);
+  esp_err_t addIntensityParam(int val, const char *param_name = ESP_RMAKER_DEF_INTENSITY_NAME);
+  esp_err_t addCCTParam(int val, const char *param_name = ESP_RMAKER_DEF_CCT_NAME);
+  esp_err_t addDirectionParam(int val, const char *param_name = ESP_RMAKER_DEF_DIRECTION_NAME);
+  esp_err_t addSpeedParam(int val, const char *param_name = ESP_RMAKER_DEF_SPEED_NAME);
+  esp_err_t addTemperatureParam(float val, const char *param_name = ESP_RMAKER_DEF_TEMPERATURE_NAME);
+
+  //Update Parameter
+  esp_err_t updateAndReportParam(const char *param_name, bool val);
+  esp_err_t updateAndReportParam(const char *param_name, int val);
+  esp_err_t updateAndReportParam(const char *param_name, float val);
+  esp_err_t updateAndReportParam(const char *param_name, const char *val);
+};
+
+class Switch : public Device {
+public:
+  Switch() {
+    standardSwitchDevice("Switch", NULL, true);
+  }
+  Switch(const char *dev_name, void *priv_data = NULL, bool power = true) {
+    standardSwitchDevice(dev_name, priv_data, power);
+  }
+  void standardSwitchDevice(const char *dev_name, void *priv_data, bool power) {
+    this->setPrivateData(priv_data);
+    esp_rmaker_device_t *dev_handle = esp_rmaker_switch_device_create(dev_name, (void *)this->getDevicePrivateData(), power);
+    setDeviceHandle(dev_handle);
+    if (dev_handle == NULL) {
+      log_e("Switch device not created");
+    }
+  }
+};
+
+class LightBulb : public Device {
+public:
+  LightBulb() {
+    standardLightBulbDevice("Light", NULL, true);
+  }
+  LightBulb(const char *dev_name, void *priv_data = NULL, bool power = true) {
+    standardLightBulbDevice(dev_name, priv_data, power);
+  }
+  void standardLightBulbDevice(const char *dev_name, void *priv_data, bool power) {
+    this->setPrivateData(priv_data);
+    esp_rmaker_device_t *dev_handle = esp_rmaker_lightbulb_device_create(dev_name, (void *)this->getDevicePrivateData(), power);
+    setDeviceHandle(dev_handle);
+    if (dev_handle == NULL) {
+      log_e("Light device not created");
+    }
+  }
+};
+
+class Fan : public Device {
+public:
+  Fan() {
+    standardFanDevice("Fan", NULL, true);
+  }
+  Fan(const char *dev_name, void *priv_data = NULL, bool power = true) {
+    standardFanDevice(dev_name, priv_data, power);
+  }
+  void standardFanDevice(const char *dev_name, void *priv_data, bool power) {
+    esp_rmaker_device_t *dev_handle = esp_rmaker_fan_device_create(dev_name, priv_data, power);
+    setDeviceHandle(dev_handle);
+    if (dev_handle == NULL) {
+      log_e("Fan device not created");
+    }
+  }
+};
+
+class TemperatureSensor : public Device {
+public:
+  TemperatureSensor() {
+    standardTemperatureSensorDevice("Temperature-Sensor", NULL, 25.0);
+  }
+  TemperatureSensor(const char *dev_name, void *priv_data = NULL, float temp = 25.0) {
+    standardTemperatureSensorDevice(dev_name, priv_data, temp);
+  }
+  void standardTemperatureSensorDevice(const char *dev_name, void *priv_data, float temp) {
+    this->setPrivateData(priv_data);
+    esp_rmaker_device_t *dev_handle = esp_rmaker_temp_sensor_device_create(dev_name, (void *)this->getDevicePrivateData(), temp);
+    setDeviceHandle(dev_handle);
+    if (dev_handle == NULL) {
+      log_e("Temperature Sensor device not created");
+    }
+  }
+};
+#endif
diff --git a/libraries/RainMaker/src/RMakerNode.cpp b/libraries/RainMaker/src/RMakerNode.cpp
new file mode 100644
index 00000000000..9c237fa5999
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerNode.cpp
@@ -0,0 +1,37 @@
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "RMakerNode.h"
+static esp_err_t err;
+
+esp_err_t Node::addDevice(Device device) {
+  err = esp_rmaker_node_add_device(node, device.getDeviceHandle());
+  if (err != ESP_OK) {
+    log_e("Device was not added to the Node");
+  }
+  return err;
+}
+
+esp_err_t Node::removeDevice(Device device) {
+  err = esp_rmaker_node_remove_device(node, device.getDeviceHandle());
+  if (err != ESP_OK) {
+    log_e("Device was not removed from the Node");
+  }
+  return err;
+}
+
+char *Node::getNodeID() {
+  return esp_rmaker_get_node_id();
+}
+
+node_info_t *Node::getNodeInfo() {
+  return esp_rmaker_node_get_info(node);
+}
+
+esp_err_t Node::addNodeAttr(const char *attr_name, const char *val) {
+  err = esp_rmaker_node_add_attribute(node, attr_name, val);
+  if (err != ESP_OK) {
+    log_e("Failed to add attribute to the Node");
+  }
+  return err;
+}
+#endif
diff --git a/libraries/RainMaker/src/RMakerNode.h b/libraries/RainMaker/src/RMakerNode.h
new file mode 100644
index 00000000000..a2236a6f7c4
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerNode.h
@@ -0,0 +1,42 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "esp_system.h"
+#include "RMakerDevice.h"
+
+class Node {
+private:
+  esp_rmaker_node_t *node;
+
+public:
+  Node() {
+    node = NULL;
+  }
+  void setNodeHandle(esp_rmaker_node_t *rnode) {
+    node = rnode;
+  }
+  esp_rmaker_node_t *getNodeHandle() {
+    return node;
+  }
+
+  esp_err_t addDevice(Device device);
+  esp_err_t removeDevice(Device device);
+
+  char *getNodeID();
+  node_info_t *getNodeInfo();
+  esp_err_t addNodeAttr(const char *attr_name, const char *val);
+};
+#endif
diff --git a/libraries/RainMaker/src/RMakerParam.cpp b/libraries/RainMaker/src/RMakerParam.cpp
new file mode 100644
index 00000000000..1b30a77782e
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerParam.cpp
@@ -0,0 +1,38 @@
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "RMakerParam.h"
+
+static esp_err_t err;
+
+esp_err_t Param::addUIType(const char *ui_type) {
+  err = esp_rmaker_param_add_ui_type(param_handle, ui_type);
+  if (err != ESP_OK) {
+    log_e("Add UI type error");
+  }
+  return err;
+}
+
+esp_err_t Param::addBounds(param_val_t min, param_val_t max, param_val_t step) {
+  err = esp_rmaker_param_add_bounds(param_handle, min, max, step);
+  if (err != ESP_OK) {
+    log_e("Add Bounds error");
+  }
+  return err;
+}
+
+esp_err_t Param::updateAndReport(param_val_t val) {
+  err = esp_rmaker_param_update_and_report(getParamHandle(), val);
+  if (err != ESP_OK) {
+    log_e("Update and Report param failed");
+  }
+  return err;
+}
+
+esp_err_t Param::addValidStrList(const char **string_list, uint8_t count) {
+  esp_err_t err = esp_rmaker_param_add_valid_str_list(getParamHandle(), string_list, count);
+  if (err != ESP_OK) {
+    log_e("Add valid string list error");
+  }
+  return err;
+}
+#endif
diff --git a/libraries/RainMaker/src/RMakerParam.h b/libraries/RainMaker/src/RMakerParam.h
new file mode 100644
index 00000000000..55bb03cb6ec
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerParam.h
@@ -0,0 +1,46 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "esp_system.h"
+#include "RMakerType.h"
+
+class Param {
+private:
+  const param_handle_t *param_handle;
+
+public:
+  Param() {
+    param_handle = NULL;
+  }
+  Param(const char *param_name, const char *param_type, param_val_t val, uint8_t properties) {
+    param_handle = esp_rmaker_param_create(param_name, param_type, val, properties);
+  }
+  void setParamHandle(const param_handle_t *param_handle) {
+    this->param_handle = param_handle;
+  }
+  const char *getParamName() {
+    return esp_rmaker_param_get_name(param_handle);
+  }
+  const param_handle_t *getParamHandle() {
+    return param_handle;
+  }
+
+  esp_err_t addUIType(const char *ui_type);
+  esp_err_t addBounds(param_val_t min, param_val_t max, param_val_t step);
+  esp_err_t updateAndReport(param_val_t val);
+  esp_err_t addValidStrList(const char **string_list, uint8_t count);
+};
+#endif
diff --git a/libraries/RainMaker/src/RMakerQR.cpp b/libraries/RainMaker/src/RMakerQR.cpp
new file mode 100644
index 00000000000..1b6b010dd4b
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerQR.cpp
@@ -0,0 +1,25 @@
+#include "RMakerQR.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+void printQR(const char *name, const char *pop, const char *transport) {
+  if (!name || !pop || !transport) {
+    log_w("Cannot generate QR code payload. Data missing.");
+    return;
+  }
+  char payload[150] = {0};
+  snprintf(
+    payload, sizeof(payload),
+    "{\"ver\":\"%s\",\"name\":\"%s\""
+    ",\"pop\":\"%s\",\"transport\":\"%s\"}",
+    PROV_QR_VERSION, name, pop, transport
+  );
+  if (Serial) {
+    Serial.printf("Scan this QR code from the ESP RainMaker phone app.\n");
+  }
+  //qrcode_display(payload);  // deprecated!
+  esp_qrcode_config_t cfg = ESP_QRCODE_CONFIG_DEFAULT();
+  esp_qrcode_generate(&cfg, payload);
+  if (Serial) {
+    Serial.printf("If QR code is not visible, copy paste the below URL in a browser.\n%s?data=%s\n", QRCODE_BASE_URL, payload);
+  }
+}
+#endif
diff --git a/libraries/RainMaker/src/RMakerQR.h b/libraries/RainMaker/src/RMakerQR.h
new file mode 100644
index 00000000000..a2e12e410d2
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerQR.h
@@ -0,0 +1,25 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "RMaker.h"
+#include "esp_system.h"
+#include <qrcode.h>
+
+#define PROV_QR_VERSION "v1"
+#define QRCODE_BASE_URL "https://rainmaker.espressif.com/qrcode.html"
+
+void printQR(const char *name, const char *pop, const char *transport);
+#endif
diff --git a/libraries/RainMaker/src/RMakerType.cpp b/libraries/RainMaker/src/RMakerType.cpp
new file mode 100644
index 00000000000..a2846fc782a
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerType.cpp
@@ -0,0 +1,24 @@
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "RMakerType.h"
+
+param_val_t value(int ival) {
+  return esp_rmaker_int(ival);
+}
+
+param_val_t value(bool bval) {
+  return esp_rmaker_bool(bval);
+}
+
+param_val_t value(char *sval) {
+  return esp_rmaker_str(sval);
+}
+
+param_val_t value(float fval) {
+  return esp_rmaker_float(fval);
+}
+
+param_val_t value(const char *sval) {
+  return esp_rmaker_str(sval);
+}
+#endif
diff --git a/libraries/RainMaker/src/RMakerType.h b/libraries/RainMaker/src/RMakerType.h
new file mode 100644
index 00000000000..daf9b193881
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerType.h
@@ -0,0 +1,37 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "esp_system.h"
+#include <esp_rmaker_core.h>
+#include <esp_rmaker_ota.h>
+#include <esp_err.h>
+#include <esp32-hal.h>
+
+typedef esp_rmaker_node_t *node_t;
+typedef esp_rmaker_node_info_t node_info_t;
+typedef esp_rmaker_param_val_t param_val_t;
+typedef esp_rmaker_write_ctx_t write_ctx_t;
+typedef esp_rmaker_read_ctx_t read_ctx_t;
+typedef esp_rmaker_device_t device_handle_t;
+typedef esp_rmaker_param_t param_handle_t;
+typedef esp_rmaker_ota_type_t ota_type_t;
+
+param_val_t value(int);
+param_val_t value(bool);
+param_val_t value(char *);
+param_val_t value(float);
+param_val_t value(const char *);
+#endif
diff --git a/libraries/RainMaker/src/RMakerUtils.cpp b/libraries/RainMaker/src/RMakerUtils.cpp
new file mode 100644
index 00000000000..7027686fb14
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerUtils.cpp
@@ -0,0 +1,11 @@
+#include "RMakerUtils.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#define RESET_DELAY_SEC 2
+void RMakerFactoryReset(int reboot_seconds) {
+  esp_rmaker_factory_reset(RESET_DELAY_SEC, reboot_seconds);
+}
+
+void RMakerWiFiReset(int reboot_seconds) {
+  esp_rmaker_wifi_reset(RESET_DELAY_SEC, reboot_seconds);
+}
+#endif
diff --git a/libraries/RainMaker/src/RMakerUtils.h b/libraries/RainMaker/src/RMakerUtils.h
new file mode 100644
index 00000000000..5896a825b9f
--- /dev/null
+++ b/libraries/RainMaker/src/RMakerUtils.h
@@ -0,0 +1,23 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+#include "sdkconfig.h"
+#ifdef CONFIG_ESP_RMAKER_WORK_QUEUE_TASK_STACK
+#include "RMaker.h"
+#include "esp_system.h"
+#include <esp_rmaker_utils.h>
+
+void RMakerFactoryReset(int seconds);
+void RMakerWiFiReset(int seconds);
+#endif
diff --git a/libraries/SD/README.md b/libraries/SD/README.md
index 2cc472dc809..eef61d8176c 100644
--- a/libraries/SD/README.md
+++ b/libraries/SD/README.md
@@ -1,42 +1,47 @@
-
 # SD library
 
-This library provides the integration of ESP32 and SD (Secure Digital) cards without additional modules.
-
+This library provides the integration of ESP32 and SD (Secure Digital) and MMC (Multi Media Card) cards without additional modules. This library is using SPI to interface with the cards. Please note that SPI mode is slower than the intended SD or MMC mode, however, provides more flexibility as the SPI module is available on all ESP SoCs and can be routed to any GPIO through GPIO matrix.
 
 ## Sample wiring diagram:
 
+![Connections](http://i.imgur.com/4CoXOuR.png)
 
-![SD card pins](http://i.imgur.com/4CoXOuR.png)
-
-For others SD formats:
-
+For other SD formats:
 
 ![Other SD card formats](https://upload.wikimedia.org/wikipedia/commons/thumb/a/ab/MMC-SD-miniSD-microSD-Color-Numbers-Names.gif/330px-MMC-SD-miniSD-microSD-Color-Numbers-Names.gif)
 
-
 Image source: [Wikipedia](https://upload.wikimedia.org/wikipedia/commons/thumb/a/ab/MMC-SD-miniSD-microSD-Color-Numbers-Names.gif/330px-MMC-SD-miniSD-microSD-Color-Numbers-Names.gif)
 
-```diff
-- Warning: Some ESP32 modules have different pinouts!
-```
+> **Warning**
+Some ESP32 modules have different pin outs!
 
+## Default SPI pins:
+Note that SPI pins can be configured by using `SPI.begin(sck, miso, mosi, cs);` alternatively, you can change only the CS pin with `SD.begin(CSpin)`
 
+| SPI Pin Name | ESP8266 | ESP32 | ESP32‑S2 | ESP32‑S3 | ESP32‑C3 | ESP32‑C6 | ESP32‑H2 |
+|--------------|---------|-------|----------|----------|----------|----------|----------|
+| CS (SS)      | GPIO15  | GPIO5 | GPIO34   | GPIO10   | GPIO7    | GPIO18   | GPIO0    |
+| DI (MOSI)    | GPIO13  | GPIO23| GPIO35   | GPIO11   | GPIO6    | GPIO19   | GPIO25    |
+| DO (MISO)    | GPIO12  | GPIO19| GPIO37   | GPIO13   | GPIO5    | GPIO20   | GPIO11    |
+| SCK (SCLK)   | GPIO14  | GPIO18| GPIO36   | GPIO12   | GPIO4    | GPIO21   | GPIO10    |
 
 ## FAQ:
 
-**Do I need any additional modules, like Arduino SD module?**
+**Do I need any additional modules**, like **the **Arduino**** SD module**?**
 
 No, just wire your SD card directly to ESP32.
 
+Tip: If you are using a microSD card and have a spare adapter to full-sized SD, you can solder Dupont pins on the adapter.
 
 
 **What is the difference between SD and SD_MMC libraries?**
 
 SD runs on SPI, and SD_MMC uses the SDMMC hardware bus on the ESP32.
-
-
-
-**Can I change the CS pin?**
-
-Yes, just use: `SD.begin(CSpin)`
+The SPI uses 4 communication pins + 2 power connections and operates on up to 80 MHz. The SPI option offers flexibility on pin connection because the data connections can be routed through GPIO matrix to any data pin.
+SD-SPI speed is approximately half of the SD-MMC even when used on 1-bit line.
+You can read more about SD SPI in the [documentation](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/sdspi_host.html)
+
+SD_MMC is supported only by ESP32 and ESP32-S3 and can be connected only to dedicated pins. SD_MMC allows to use of 1, 4 or 8 data pins + 2 additional communication pins and 2 power pins. The data pins need to be pulled up externally.
+You can read more about SD_MMC in the [documentation](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/sdmmc_host.html)
+1-bit: SD_MMC_ speed is approximately two-times faster than SPI mode
+4-bit: SD_MMC speed is approximately three-times faster than SPI mode.
diff --git a/libraries/SD/examples/SD_Test/SD_Test.ino b/libraries/SD/examples/SD_Test/SD_Test.ino
index 6059446e600..c22e6c3a933 100644
--- a/libraries/SD/examples/SD_Test/SD_Test.ino
+++ b/libraries/SD/examples/SD_Test/SD_Test.ino
@@ -1,221 +1,259 @@
 /*
- * Connect the SD card to the following pins:
+ * pin 1 - not used          |  Micro SD card     |
+ * pin 2 - CS (SS)           |                   /
+ * pin 3 - DI (MOSI)         |                  |__
+ * pin 4 - VDD (3.3V)        |                    |
+ * pin 5 - SCK (SCLK)        | 8 7 6 5 4 3 2 1   /
+ * pin 6 - VSS (GND)         | ▄ ▄ ▄ ▄ ▄ ▄ ▄ ▄  /
+ * pin 7 - DO (MISO)         | ▀ ▀ █ ▀ █ ▀ ▀ ▀ |
+ * pin 8 - not used          |_________________|
+ *                             ║ ║ ║ ║ ║ ║ ║ ║
+ *                     ╔═══════╝ ║ ║ ║ ║ ║ ║ ╚═════════╗
+ *                     ║         ║ ║ ║ ║ ║ ╚══════╗    ║
+ *                     ║   ╔═════╝ ║ ║ ║ ╚═════╗  ║    ║
+ * Connections for     ║   ║   ╔═══╩═║═║═══╗   ║  ║    ║
+ * full-sized          ║   ║   ║   ╔═╝ ║   ║   ║  ║    ║
+ * SD card             ║   ║   ║   ║   ║   ║   ║  ║    ║
+ * Pin name         |  -  DO  VSS SCK VDD VSS DI CS    -  |
+ * SD pin number    |  8   7   6   5   4   3   2   1   9 /
+ *                  |                                  █/
+ *                  |__▍___▊___█___█___█___█___█___█___/
  *
- * SD Card | ESP32
- *    D2       -
- *    D3       SS
- *    CMD      MOSI
- *    VSS      GND
- *    VDD      3.3V
- *    CLK      SCK
- *    VSS      GND
- *    D0       MISO
- *    D1       -
+ * Note:  The SPI pins can be manually configured by using `SPI.begin(sck, miso, mosi, cs).`
+ *        Alternatively, you can change the CS pin and use the other default settings by using `SD.begin(cs)`.
+ *
+ * +--------------+---------+-------+----------+----------+----------+----------+----------+
+ * | SPI Pin Name | ESP8266 | ESP32 | ESP32‑S2 | ESP32‑S3 | ESP32‑C3 | ESP32‑C6 | ESP32‑H2 |
+ * +==============+=========+=======+==========+==========+==========+==========+==========+
+ * | CS (SS)      | GPIO15  | GPIO5 | GPIO34   | GPIO10   | GPIO7    | GPIO18   | GPIO0    |
+ * +--------------+---------+-------+----------+----------+----------+----------+----------+
+ * | DI (MOSI)    | GPIO13  | GPIO23| GPIO35   | GPIO11   | GPIO6    | GPIO19   | GPIO25   |
+ * +--------------+---------+-------+----------+----------+----------+----------+----------+
+ * | DO (MISO)    | GPIO12  | GPIO19| GPIO37   | GPIO13   | GPIO5    | GPIO20   | GPIO11   |
+ * +--------------+---------+-------+----------+----------+----------+----------+----------+
+ * | SCK (SCLK)   | GPIO14  | GPIO18| GPIO36   | GPIO12   | GPIO4    | GPIO21   | GPIO10   |
+ * +--------------+---------+-------+----------+----------+----------+----------+----------+
+ *
+ * For more info see file README.md in this library or on URL:
+ * https://github.com/espressif/arduino-esp32/tree/master/libraries/SD
  */
+
 #include "FS.h"
 #include "SD.h"
 #include "SPI.h"
 
-void listDir(fs::FS &fs, const char * dirname, uint8_t levels){
-    Serial.printf("Listing directory: %s\n", dirname);
+/*
+Uncomment and set up if you want to use custom pins for the SPI communication
+#define REASSIGN_PINS
+int sck = -1;
+int miso = -1;
+int mosi = -1;
+int cs = -1;
+*/
 
-    File root = fs.open(dirname);
-    if(!root){
-        Serial.println("Failed to open directory");
-        return;
-    }
-    if(!root.isDirectory()){
-        Serial.println("Not a directory");
-        return;
-    }
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\n", dirname);
 
-    File file = root.openNextFile();
-    while(file){
-        if(file.isDirectory()){
-            Serial.print("  DIR : ");
-            Serial.println(file.name());
-            if(levels){
-                listDir(fs, file.name(), levels -1);
-            }
-        } else {
-            Serial.print("  FILE: ");
-            Serial.print(file.name());
-            Serial.print("  SIZE: ");
-            Serial.println(file.size());
-        }
-        file = root.openNextFile();
-    }
-}
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("Failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println("Not a directory");
+    return;
+  }
 
-void createDir(fs::FS &fs, const char * path){
-    Serial.printf("Creating Dir: %s\n", path);
-    if(fs.mkdir(path)){
-        Serial.println("Dir created");
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.println(file.name());
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
     } else {
-        Serial.println("mkdir failed");
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("  SIZE: ");
+      Serial.println(file.size());
     }
+    file = root.openNextFile();
+  }
 }
 
-void removeDir(fs::FS &fs, const char * path){
-    Serial.printf("Removing Dir: %s\n", path);
-    if(fs.rmdir(path)){
-        Serial.println("Dir removed");
-    } else {
-        Serial.println("rmdir failed");
-    }
+void createDir(fs::FS &fs, const char *path) {
+  Serial.printf("Creating Dir: %s\n", path);
+  if (fs.mkdir(path)) {
+    Serial.println("Dir created");
+  } else {
+    Serial.println("mkdir failed");
+  }
 }
 
-void readFile(fs::FS &fs, const char * path){
-    Serial.printf("Reading file: %s\n", path);
+void removeDir(fs::FS &fs, const char *path) {
+  Serial.printf("Removing Dir: %s\n", path);
+  if (fs.rmdir(path)) {
+    Serial.println("Dir removed");
+  } else {
+    Serial.println("rmdir failed");
+  }
+}
 
-    File file = fs.open(path);
-    if(!file){
-        Serial.println("Failed to open file for reading");
-        return;
-    }
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\n", path);
 
-    Serial.print("Read from file: ");
-    while(file.available()){
-        Serial.write(file.read());
-    }
-    file.close();
+  File file = fs.open(path);
+  if (!file) {
+    Serial.println("Failed to open file for reading");
+    return;
+  }
+
+  Serial.print("Read from file: ");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
+  file.close();
 }
 
-void writeFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Writing file: %s\n", path);
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\n", path);
 
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("Failed to open file for writing");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("File written");
-    } else {
-        Serial.println("Write failed");
-    }
-    file.close();
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("File written");
+  } else {
+    Serial.println("Write failed");
+  }
+  file.close();
 }
 
-void appendFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Appending to file: %s\n", path);
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\n", path);
 
-    File file = fs.open(path, FILE_APPEND);
-    if(!file){
-        Serial.println("Failed to open file for appending");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("Message appended");
-    } else {
-        Serial.println("Append failed");
-    }
-    file.close();
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("Failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("Message appended");
+  } else {
+    Serial.println("Append failed");
+  }
+  file.close();
 }
 
-void renameFile(fs::FS &fs, const char * path1, const char * path2){
-    Serial.printf("Renaming file %s to %s\n", path1, path2);
-    if (fs.rename(path1, path2)) {
-        Serial.println("File renamed");
-    } else {
-        Serial.println("Rename failed");
-    }
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("File renamed");
+  } else {
+    Serial.println("Rename failed");
+  }
 }
 
-void deleteFile(fs::FS &fs, const char * path){
-    Serial.printf("Deleting file: %s\n", path);
-    if(fs.remove(path)){
-        Serial.println("File deleted");
-    } else {
-        Serial.println("Delete failed");
-    }
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\n", path);
+  if (fs.remove(path)) {
+    Serial.println("File deleted");
+  } else {
+    Serial.println("Delete failed");
+  }
 }
 
-void testFileIO(fs::FS &fs, const char * path){
-    File file = fs.open(path);
-    static uint8_t buf[512];
-    size_t len = 0;
-    uint32_t start = millis();
-    uint32_t end = start;
-    if(file){
-        len = file.size();
-        size_t flen = len;
-        start = millis();
-        while(len){
-            size_t toRead = len;
-            if(toRead > 512){
-                toRead = 512;
-            }
-            file.read(buf, toRead);
-            len -= toRead;
-        }
-        end = millis() - start;
-        Serial.printf("%u bytes read for %u ms\n", flen, end);
-        file.close();
-    } else {
-        Serial.println("Failed to open file for reading");
-    }
-
-
-    file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("Failed to open file for writing");
-        return;
-    }
-
-    size_t i;
+void testFileIO(fs::FS &fs, const char *path) {
+  File file = fs.open(path);
+  static uint8_t buf[512];
+  size_t len = 0;
+  uint32_t start = millis();
+  uint32_t end = start;
+  if (file) {
+    len = file.size();
+    size_t flen = len;
     start = millis();
-    for(i=0; i<2048; i++){
-        file.write(buf, 512);
+    while (len) {
+      size_t toRead = len;
+      if (toRead > 512) {
+        toRead = 512;
+      }
+      file.read(buf, toRead);
+      len -= toRead;
     }
     end = millis() - start;
-    Serial.printf("%u bytes written for %u ms\n", 2048 * 512, end);
+    Serial.printf("%u bytes read for %lu ms\n", flen, end);
     file.close();
+  } else {
+    Serial.println("Failed to open file for reading");
+  }
+
+  file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing");
+    return;
+  }
+
+  size_t i;
+  start = millis();
+  for (i = 0; i < 2048; i++) {
+    file.write(buf, 512);
+  }
+  end = millis() - start;
+  Serial.printf("%u bytes written for %lu ms\n", 2048 * 512, end);
+  file.close();
 }
 
-void setup(){
-    Serial.begin(115200);
-    if(!SD.begin()){
-        Serial.println("Card Mount Failed");
-        return;
-    }
-    uint8_t cardType = SD.cardType();
+void setup() {
+  Serial.begin(115200);
 
-    if(cardType == CARD_NONE){
-        Serial.println("No SD card attached");
-        return;
-    }
+#ifdef REASSIGN_PINS
+  SPI.begin(sck, miso, mosi, cs);
+  if (!SD.begin(cs)) {
+#else
+  if (!SD.begin()) {
+#endif
+    Serial.println("Card Mount Failed");
+    return;
+  }
+  uint8_t cardType = SD.cardType();
 
-    Serial.print("SD Card Type: ");
-    if(cardType == CARD_MMC){
-        Serial.println("MMC");
-    } else if(cardType == CARD_SD){
-        Serial.println("SDSC");
-    } else if(cardType == CARD_SDHC){
-        Serial.println("SDHC");
-    } else {
-        Serial.println("UNKNOWN");
-    }
+  if (cardType == CARD_NONE) {
+    Serial.println("No SD card attached");
+    return;
+  }
 
-    uint64_t cardSize = SD.cardSize() / (1024 * 1024);
-    Serial.printf("SD Card Size: %lluMB\n", cardSize);
-
-    listDir(SD, "/", 0);
-    createDir(SD, "/mydir");
-    listDir(SD, "/", 0);
-    removeDir(SD, "/mydir");
-    listDir(SD, "/", 2);
-    writeFile(SD, "/hello.txt", "Hello ");
-    appendFile(SD, "/hello.txt", "World!\n");
-    readFile(SD, "/hello.txt");
-    deleteFile(SD, "/foo.txt");
-    renameFile(SD, "/hello.txt", "/foo.txt");
-    readFile(SD, "/foo.txt");
-    testFileIO(SD, "/test.txt");
-    Serial.printf("Total space: %lluMB\n", SD.totalBytes() / (1024 * 1024));
-    Serial.printf("Used space: %lluMB\n", SD.usedBytes() / (1024 * 1024));
-}
+  Serial.print("SD Card Type: ");
+  if (cardType == CARD_MMC) {
+    Serial.println("MMC");
+  } else if (cardType == CARD_SD) {
+    Serial.println("SDSC");
+  } else if (cardType == CARD_SDHC) {
+    Serial.println("SDHC");
+  } else {
+    Serial.println("UNKNOWN");
+  }
 
-void loop(){
+  uint64_t cardSize = SD.cardSize() / (1024 * 1024);
+  Serial.printf("SD Card Size: %lluMB\n", cardSize);
 
+  listDir(SD, "/", 0);
+  createDir(SD, "/mydir");
+  listDir(SD, "/", 0);
+  removeDir(SD, "/mydir");
+  listDir(SD, "/", 2);
+  writeFile(SD, "/hello.txt", "Hello ");
+  appendFile(SD, "/hello.txt", "World!\n");
+  readFile(SD, "/hello.txt");
+  deleteFile(SD, "/foo.txt");
+  renameFile(SD, "/hello.txt", "/foo.txt");
+  readFile(SD, "/foo.txt");
+  testFileIO(SD, "/test.txt");
+  Serial.printf("Total space: %lluMB\n", SD.totalBytes() / (1024 * 1024));
+  Serial.printf("Used space: %lluMB\n", SD.usedBytes() / (1024 * 1024));
 }
+
+void loop() {}
diff --git a/libraries/SD/examples/SD_time/SD_time.ino b/libraries/SD/examples/SD_time/SD_time.ino
index 5fc871627b5..cc65d21ae20 100644
--- a/libraries/SD/examples/SD_time/SD_time.ino
+++ b/libraries/SD/examples/SD_time/SD_time.ino
@@ -1,213 +1,257 @@
 /*
- * Connect the SD card to the following pins:
+ * pin 1 - not used          |  Micro SD card     |
+ * pin 2 - CS (SS)           |                   /
+ * pin 3 - DI (MOSI)         |                  |__
+ * pin 4 - VDD (3.3V)        |                    |
+ * pin 5 - SCK (SCLK)        | 8 7 6 5 4 3 2 1   /
+ * pin 6 - VSS (GND)         | ▄ ▄ ▄ ▄ ▄ ▄ ▄ ▄  /
+ * pin 7 - DO (MISO)         | ▀ ▀ █ ▀ █ ▀ ▀ ▀ |
+ * pin 8 - not used          |_________________|
+ *                             ║ ║ ║ ║ ║ ║ ║ ║
+ *                     ╔═══════╝ ║ ║ ║ ║ ║ ║ ╚═════════╗
+ *                     ║         ║ ║ ║ ║ ║ ╚══════╗    ║
+ *                     ║   ╔═════╝ ║ ║ ║ ╚═════╗  ║    ║
+ * Connections for     ║   ║   ╔═══╩═║═║═══╗   ║  ║    ║
+ * full-sized          ║   ║   ║   ╔═╝ ║   ║   ║  ║    ║
+ * SD card             ║   ║   ║   ║   ║   ║   ║  ║    ║
+ * Pin name         |  -  DO  VSS SCK VDD VSS DI CS    -  |
+ * SD pin number    |  8   7   6   5   4   3   2   1   9 /
+ *                  |                                  █/
+ *                  |__▍___▊___█___█___█___█___█___█___/
  *
- * SD Card | ESP32
- *    D2       -
- *    D3       SS
- *    CMD      MOSI
- *    VSS      GND
- *    VDD      3.3V
- *    CLK      SCK
- *    VSS      GND
- *    D0       MISO
- *    D1       -
+ * Note:  The SPI pins can be manually configured by using `SPI.begin(sck, miso, mosi, cs);`.
+ *        Alternatively you can change only the CS pin with `SD.begin(CSpin)` and keep the default settings for other pins.
+ *
++----------+
+ * | SPI Pin Name | ESP8266 | ESP32 | ESP32‑S2 | ESP32‑S3 | ESP32‑C3 | ESP32‑C6 | ESP32‑H2 |
+ * +==============+=========+=======+==========+==========+==========+==========+==========+
+ * | CS (SS)      | GPIO15  | GPIO5 | GPIO34   | GPIO10   | GPIO7    | GPIO18   | GPIO0    |
+ * +--------------+---------+-------+----------+----------+----------+----------+----------+
+ * | DI (MOSI)    | GPIO13  | GPIO23| GPIO35   | GPIO11   | GPIO6    | GPIO19   | GPIO25   |
+ * +--------------+---------+-------+----------+----------+----------+----------+----------+
+ * | DO (MISO)    | GPIO12  | GPIO19| GPIO37   | GPIO13   | GPIO5    | GPIO20   | GPIO11   |
+ * +--------------+---------+-------+----------+----------+----------+----------+----------+
+ * | SCK (SCLK)   | GPIO14  | GPIO18| GPIO36   | GPIO12   | GPIO4    | GPIO21   | GPIO10   |
+ * +--------------+---------+-------+----------+----------+----------+----------+----------+
+ *
+ * For more info see file README.md in this library or on URL:
+ * https://github.com/espressif/arduino-esp32/tree/master/libraries/SD
  */
 
 #include "FS.h"
 #include "SD.h"
 #include "SPI.h"
-#include <time.h> 
+#include <time.h>
 #include <WiFi.h>
 
-const char* ssid     = "your-ssid";
-const char* password = "your-password";
+const char *ssid = "your-ssid";
+const char *password = "your-password";
 
-long timezone = 1; 
+long timezone = 1;
 byte daysavetime = 1;
 
-void listDir(fs::FS &fs, const char * dirname, uint8_t levels){
-    Serial.printf("Listing directory: %s\n", dirname);
+/*
+Uncomment and setup pins you want to use for the SPI communication
+#define REASSIGN_PINS
+int sck = -1;
+int miso = -1;
+int mosi = -1;
+int cs = -1;
+*/
 
-    File root = fs.open(dirname);
-    if(!root){
-        Serial.println("Failed to open directory");
-        return;
-    }
-    if(!root.isDirectory()){
-        Serial.println("Not a directory");
-        return;
-    }
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\n", dirname);
 
-    File file = root.openNextFile();
-    while(file){
-        if(file.isDirectory()){
-            Serial.print("  DIR : ");
-            Serial.print (file.name());
-            time_t t= file.getLastWrite();
-            struct tm * tmstruct = localtime(&t);
-            Serial.printf("  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct->tm_year)+1900,( tmstruct->tm_mon)+1, tmstruct->tm_mday,tmstruct->tm_hour , tmstruct->tm_min, tmstruct->tm_sec);
-            if(levels){
-                listDir(fs, file.name(), levels -1);
-            }
-        } else {
-            Serial.print("  FILE: ");
-            Serial.print(file.name());
-            Serial.print("  SIZE: ");
-            Serial.print(file.size());
-            time_t t= file.getLastWrite();
-            struct tm * tmstruct = localtime(&t);
-            Serial.printf("  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct->tm_year)+1900,( tmstruct->tm_mon)+1, tmstruct->tm_mday,tmstruct->tm_hour , tmstruct->tm_min, tmstruct->tm_sec);
-        }
-        file = root.openNextFile();
-    }
-}
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("Failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println("Not a directory");
+    return;
+  }
 
-void createDir(fs::FS &fs, const char * path){
-    Serial.printf("Creating Dir: %s\n", path);
-    if(fs.mkdir(path)){
-        Serial.println("Dir created");
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.print(file.name());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
     } else {
-        Serial.println("mkdir failed");
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("  SIZE: ");
+      Serial.print(file.size());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
     }
+    file = root.openNextFile();
+  }
 }
 
-void removeDir(fs::FS &fs, const char * path){
-    Serial.printf("Removing Dir: %s\n", path);
-    if(fs.rmdir(path)){
-        Serial.println("Dir removed");
-    } else {
-        Serial.println("rmdir failed");
-    }
+void createDir(fs::FS &fs, const char *path) {
+  Serial.printf("Creating Dir: %s\n", path);
+  if (fs.mkdir(path)) {
+    Serial.println("Dir created");
+  } else {
+    Serial.println("mkdir failed");
+  }
 }
 
-void readFile(fs::FS &fs, const char * path){
-    Serial.printf("Reading file: %s\n", path);
+void removeDir(fs::FS &fs, const char *path) {
+  Serial.printf("Removing Dir: %s\n", path);
+  if (fs.rmdir(path)) {
+    Serial.println("Dir removed");
+  } else {
+    Serial.println("rmdir failed");
+  }
+}
 
-    File file = fs.open(path);
-    if(!file){
-        Serial.println("Failed to open file for reading");
-        return;
-    }
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\n", path);
 
-    Serial.print("Read from file: ");
-    while(file.available()){
-        Serial.write(file.read());
-    }
-    file.close();
+  File file = fs.open(path);
+  if (!file) {
+    Serial.println("Failed to open file for reading");
+    return;
+  }
+
+  Serial.print("Read from file: ");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
+  file.close();
 }
 
-void writeFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Writing file: %s\n", path);
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\n", path);
 
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("Failed to open file for writing");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("File written");
-    } else {
-        Serial.println("Write failed");
-    }
-    file.close();
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("File written");
+  } else {
+    Serial.println("Write failed");
+  }
+  file.close();
 }
 
-void appendFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Appending to file: %s\n", path);
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\n", path);
 
-    File file = fs.open(path, FILE_APPEND);
-    if(!file){
-        Serial.println("Failed to open file for appending");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("Message appended");
-    } else {
-        Serial.println("Append failed");
-    }
-    file.close();
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("Failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("Message appended");
+  } else {
+    Serial.println("Append failed");
+  }
+  file.close();
 }
 
-void renameFile(fs::FS &fs, const char * path1, const char * path2){
-    Serial.printf("Renaming file %s to %s\n", path1, path2);
-    if (fs.rename(path1, path2)) {
-        Serial.println("File renamed");
-    } else {
-        Serial.println("Rename failed");
-    }
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("File renamed");
+  } else {
+    Serial.println("Rename failed");
+  }
 }
 
-void deleteFile(fs::FS &fs, const char * path){
-    Serial.printf("Deleting file: %s\n", path);
-    if(fs.remove(path)){
-        Serial.println("File deleted");
-    } else {
-        Serial.println("Delete failed");
-    }
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\n", path);
+  if (fs.remove(path)) {
+    Serial.println("File deleted");
+  } else {
+    Serial.println("Delete failed");
+  }
 }
 
-void setup(){
-    Serial.begin(115200);
-    // We start by connecting to a WiFi network
-    Serial.println();
-    Serial.println();
-    Serial.print("Connecting to ");
-    Serial.println(ssid);
+void setup() {
+  Serial.begin(115200);
+  // We start by connecting to a WiFi network
+  Serial.println();
+  Serial.println();
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
 
-    WiFi.begin(ssid, password);
+  WiFi.begin(ssid, password);
 
-    while (WiFi.status() != WL_CONNECTED) {
-        delay(500);
-        Serial.print(".");
-    }
-    Serial.println("WiFi connected");
-    Serial.println("IP address: ");
-    Serial.println(WiFi.localIP());
-    Serial.println("Contacting Time Server");
-	configTime(3600*timezone, daysavetime*3600, "time.nist.gov", "0.pool.ntp.org", "1.pool.ntp.org");
-	struct tm tmstruct ;
-    delay(2000);
-    tmstruct.tm_year = 0;
-    getLocalTime(&tmstruct, 5000);
-	Serial.printf("\nNow is : %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct.tm_year)+1900,( tmstruct.tm_mon)+1, tmstruct.tm_mday,tmstruct.tm_hour , tmstruct.tm_min, tmstruct.tm_sec);
-    Serial.println("");
-    
-    if(!SD.begin()){
-        Serial.println("Card Mount Failed");
-        return;
-    }
-    uint8_t cardType = SD.cardType();
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  Serial.println("Contacting Time Server");
+  configTime(3600 * timezone, daysavetime * 3600, "time.nist.gov", "0.pool.ntp.org", "1.pool.ntp.org");
+  struct tm tmstruct;
+  delay(2000);
+  tmstruct.tm_year = 0;
+  getLocalTime(&tmstruct, 5000);
+  Serial.printf(
+    "\nNow is : %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct.tm_year) + 1900, (tmstruct.tm_mon) + 1, tmstruct.tm_mday, tmstruct.tm_hour, tmstruct.tm_min,
+    tmstruct.tm_sec
+  );
+  Serial.println("");
 
-    if(cardType == CARD_NONE){
-        Serial.println("No SD card attached");
-        return;
-    }
+#ifdef REASSIGN_PINS
+  SPI.begin(sck, miso, mosi, cs);
+  if (!SD.begin(cs)) {
+#else
+  if (!SD.begin()) {
+#endif
+    Serial.println("Card Mount Failed");
+    return;
+  }
+  uint8_t cardType = SD.cardType();
 
-    Serial.print("SD Card Type: ");
-    if(cardType == CARD_MMC){
-        Serial.println("MMC");
-    } else if(cardType == CARD_SD){
-        Serial.println("SDSC");
-    } else if(cardType == CARD_SDHC){
-        Serial.println("SDHC");
-    } else {
-        Serial.println("UNKNOWN");
-    }
+  if (cardType == CARD_NONE) {
+    Serial.println("No SD card attached");
+    return;
+  }
 
-    uint64_t cardSize = SD.cardSize() / (1024 * 1024);
-    Serial.printf("SD Card Size: %lluMB\n", cardSize);
+  Serial.print("SD Card Type: ");
+  if (cardType == CARD_MMC) {
+    Serial.println("MMC");
+  } else if (cardType == CARD_SD) {
+    Serial.println("SDSC");
+  } else if (cardType == CARD_SDHC) {
+    Serial.println("SDHC");
+  } else {
+    Serial.println("UNKNOWN");
+  }
 
-    listDir(SD, "/", 0);
-    removeDir(SD, "/mydir");
-    createDir(SD, "/mydir");
-    deleteFile(SD, "/hello.txt");
-    writeFile(SD, "/hello.txt", "Hello ");
-    appendFile(SD, "/hello.txt", "World!\n");
-	listDir(SD, "/", 0);
-}
-
-void loop(){
+  uint64_t cardSize = SD.cardSize() / (1024 * 1024);
+  Serial.printf("SD Card Size: %lluMB\n", cardSize);
 
+  listDir(SD, "/", 0);
+  removeDir(SD, "/mydir");
+  createDir(SD, "/mydir");
+  deleteFile(SD, "/hello.txt");
+  writeFile(SD, "/hello.txt", "Hello ");
+  appendFile(SD, "/hello.txt", "World!\n");
+  listDir(SD, "/", 0);
 }
 
-
+void loop() {}
diff --git a/libraries/SD/examples/SD_time/ci.json b/libraries/SD/examples/SD_time/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/SD/examples/SD_time/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/SD/library.properties b/libraries/SD/library.properties
index 63183b735f9..66c4f5cfafd 100644
--- a/libraries/SD/library.properties
+++ b/libraries/SD/library.properties
@@ -1,5 +1,5 @@
-name=SD(esp32)
-version=1.0.5
+name=SD
+version=3.2.0
 author=Arduino, SparkFun
 maintainer=Arduino <info@arduino.cc>
 sentence=Enables reading and writing on SD cards. For all Arduino boards.
diff --git a/libraries/SD/src/SD.cpp b/libraries/SD/src/SD.cpp
index d268aa0fb97..eaec2483053 100644
--- a/libraries/SD/src/SD.cpp
+++ b/libraries/SD/src/SD.cpp
@@ -20,87 +20,109 @@
 
 using namespace fs;
 
-SDFS::SDFS(FSImplPtr impl): FS(impl), _pdrv(0xFF) {}
+SDFS::SDFS(FSImplPtr impl) : FS(impl), _pdrv(0xFF) {}
 
-bool SDFS::begin(uint8_t ssPin, SPIClass &spi, uint32_t frequency, const char * mountpoint, uint8_t max_files)
-{
-    if(_pdrv != 0xFF) {
-        return true;
-    }
+bool SDFS::begin(uint8_t ssPin, SPIClass &spi, uint32_t frequency, const char *mountpoint, uint8_t max_files, bool format_if_empty) {
+  if (_pdrv != 0xFF) {
+    return true;
+  }
 
-    spi.begin();
+  spi.begin();
 
-    _pdrv = sdcard_init(ssPin, &spi, frequency);
-    if(_pdrv == 0xFF) {
-        return false;
-    }
+  _pdrv = sdcard_init(ssPin, &spi, frequency);
+  if (_pdrv == 0xFF) {
+    return false;
+  }
 
-    if(!sdcard_mount(_pdrv, mountpoint, max_files)){
-        sdcard_unmount(_pdrv);
-        sdcard_uninit(_pdrv);
-        _pdrv = 0xFF;
-        return false;
-    }
+  if (!sdcard_mount(_pdrv, mountpoint, max_files, format_if_empty)) {
+    sdcard_unmount(_pdrv);
+    sdcard_uninit(_pdrv);
+    _pdrv = 0xFF;
+    return false;
+  }
 
-    _impl->mountpoint(mountpoint);
-    return true;
+  _impl->mountpoint(mountpoint);
+  return true;
+}
+
+void SDFS::end() {
+  if (_pdrv != 0xFF) {
+    _impl->mountpoint(NULL);
+    sdcard_unmount(_pdrv);
+
+    sdcard_uninit(_pdrv);
+    _pdrv = 0xFF;
+  }
 }
 
-void SDFS::end()
-{
-    if(_pdrv != 0xFF) {
-        _impl->mountpoint(NULL);
-        sdcard_unmount(_pdrv);
+sdcard_type_t SDFS::cardType() {
+  if (_pdrv == 0xFF) {
+    return CARD_NONE;
+  }
+  return sdcard_type(_pdrv);
+}
 
-        sdcard_uninit(_pdrv);
-        _pdrv = 0xFF;
-    }
+uint64_t SDFS::cardSize() {
+  if (_pdrv == 0xFF) {
+    return 0;
+  }
+  size_t sectors = sdcard_num_sectors(_pdrv);
+  size_t sectorSize = sdcard_sector_size(_pdrv);
+  return (uint64_t)sectors * sectorSize;
 }
 
-sdcard_type_t SDFS::cardType()
-{
-    if(_pdrv == 0xFF) {
-        return CARD_NONE;
-    }
-    return sdcard_type(_pdrv);
+size_t SDFS::numSectors() {
+  if (_pdrv == 0xFF) {
+    return 0;
+  }
+  return sdcard_num_sectors(_pdrv);
 }
 
-uint64_t SDFS::cardSize()
-{
-    if(_pdrv == 0xFF) {
-        return 0;
-    }
-    size_t sectors = sdcard_num_sectors(_pdrv);
-    size_t sectorSize = sdcard_sector_size(_pdrv);
-    return (uint64_t)sectors * sectorSize;
+size_t SDFS::sectorSize() {
+  if (_pdrv == 0xFF) {
+    return 0;
+  }
+  return sdcard_sector_size(_pdrv);
 }
 
-uint64_t SDFS::totalBytes()
-{
-	FATFS* fsinfo;
-	DWORD fre_clust;
-	if(f_getfree("0:",&fre_clust,&fsinfo)!= 0) return 0;
-    uint64_t size = ((uint64_t)(fsinfo->csize))*(fsinfo->n_fatent - 2)
+uint64_t SDFS::totalBytes() {
+  FATFS *fsinfo;
+  DWORD fre_clust;
+  char drv[3] = {(char)(48 + _pdrv), ':', 0};
+  if (f_getfree(drv, &fre_clust, &fsinfo) != 0) {
+    return 0;
+  }
+  uint64_t size = ((uint64_t)(fsinfo->csize)) * (fsinfo->n_fatent - 2)
 #if _MAX_SS != 512
-        *(fsinfo->ssize);
+                  * (fsinfo->ssize);
 #else
-        *512;
+                  * 512;
 #endif
-	return size;
+  return size;
 }
 
-uint64_t SDFS::usedBytes()
-{
-	FATFS* fsinfo;
-	DWORD fre_clust;
-	if(f_getfree("0:",&fre_clust,&fsinfo)!= 0) return 0;
-	uint64_t size = ((uint64_t)(fsinfo->csize))*((fsinfo->n_fatent - 2) - (fsinfo->free_clst))
+uint64_t SDFS::usedBytes() {
+  FATFS *fsinfo;
+  DWORD fre_clust;
+  char drv[3] = {(char)(48 + _pdrv), ':', 0};
+  if (f_getfree(drv, &fre_clust, &fsinfo) != 0) {
+    return 0;
+  }
+  uint64_t size = ((uint64_t)(fsinfo->csize)) * ((fsinfo->n_fatent - 2) - (fsinfo->free_clst))
 #if _MAX_SS != 512
-        *(fsinfo->ssize);
+                  * (fsinfo->ssize);
 #else
-        *512;
+                  * 512;
 #endif
-	return size;
+  return size;
+}
+
+bool SDFS::readRAW(uint8_t *buffer, uint32_t sector) {
+  return sd_read_raw(_pdrv, buffer, sector);
+}
+
+bool SDFS::writeRAW(uint8_t *buffer, uint32_t sector) {
+  return sd_write_raw(_pdrv, buffer, sector);
 }
 
 SDFS SD = SDFS(FSImplPtr(new VFSImpl()));
diff --git a/libraries/SD/src/SD.h b/libraries/SD/src/SD.h
index da66c386c88..aebc781a5e3 100644
--- a/libraries/SD/src/SD.h
+++ b/libraries/SD/src/SD.h
@@ -18,31 +18,35 @@
 #include "SPI.h"
 #include "sd_defines.h"
 
-namespace fs
-{
+namespace fs {
 
-class SDFS : public FS
-{
+class SDFS : public FS {
 protected:
-    uint8_t _pdrv;
+  uint8_t _pdrv;
 
 public:
-    SDFS(FSImplPtr impl);
-    bool begin(uint8_t ssPin=SS, SPIClass &spi=SPI, uint32_t frequency=4000000, const char * mountpoint="/sd", uint8_t max_files=5);
-    void end();
-    sdcard_type_t cardType();
-    uint64_t cardSize();
-    uint64_t totalBytes();
-    uint64_t usedBytes();
+  SDFS(FSImplPtr impl);
+  bool begin(
+    uint8_t ssPin = SS, SPIClass &spi = SPI, uint32_t frequency = 4000000, const char *mountpoint = "/sd", uint8_t max_files = 5, bool format_if_empty = false
+  );
+  void end();
+  sdcard_type_t cardType();
+  uint64_t cardSize();
+  size_t numSectors();
+  size_t sectorSize();
+  uint64_t totalBytes();
+  uint64_t usedBytes();
+  bool readRAW(uint8_t *buffer, uint32_t sector);
+  bool writeRAW(uint8_t *buffer, uint32_t sector);
 };
 
-}
+}  // namespace fs
 
 extern fs::SDFS SD;
 
 using namespace fs;
-typedef fs::File        SDFile;
-typedef fs::SDFS        SDFileSystemClass;
-#define SDFileSystem    SD
+typedef fs::File SDFile;
+typedef fs::SDFS SDFileSystemClass;
+#define SDFileSystem SD
 
 #endif /* _SD_H_ */
diff --git a/libraries/SD/src/sd_defines.h b/libraries/SD/src/sd_defines.h
index 6e42855ac61..9a6b8399165 100644
--- a/libraries/SD/src/sd_defines.h
+++ b/libraries/SD/src/sd_defines.h
@@ -15,11 +15,11 @@
 #define _SD_DEFINES_H_
 
 typedef enum {
-    CARD_NONE,
-    CARD_MMC,
-    CARD_SD,
-    CARD_SDHC,
-    CARD_UNKNOWN
+  CARD_NONE,
+  CARD_MMC,
+  CARD_SD,
+  CARD_SDHC,
+  CARD_UNKNOWN
 } sdcard_type_t;
 
 #endif /* _SD_DISKIO_H_ */
diff --git a/libraries/SD/src/sd_diskio.cpp b/libraries/SD/src/sd_diskio.cpp
index b43b3a31fe7..40d6ede9f81 100644
--- a/libraries/SD/src/sd_diskio.cpp
+++ b/libraries/SD/src/sd_diskio.cpp
@@ -11,764 +11,804 @@
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 // See the License for the specific language governing permissions and
 // limitations under the License.
+
+// Disable the automatic pin remapping of the API calls in this file
+#define ARDUINO_CORE_BUILD
+
 #include "sd_diskio.h"
+#include "esp_system.h"
+#include "esp32-hal-periman.h"
+
 extern "C" {
-    #include "diskio.h"
-    #include "ffconf.h"
-    #include "ff.h"
-    //#include "esp_vfs.h"
-    #include "esp_vfs_fat.h"
-    char CRC7(const char* data, int length);
-    unsigned short CRC16(const char* data, int length);
+#include "ff.h"
+#include "diskio.h"
+#if ESP_IDF_VERSION_MAJOR > 3
+#include "diskio_impl.h"
+#endif
+//#include "esp_vfs.h"
+#include "esp_vfs_fat.h"
+char CRC7(const char *data, int length);
+unsigned short CRC16(const char *data, int length);
 }
 
 typedef enum {
-    GO_IDLE_STATE           = 0,
-    SEND_OP_COND            = 1,
-    SEND_CID                = 2,
-    SEND_RELATIVE_ADDR      = 3,
-    SEND_SWITCH_FUNC        = 6,
-    SEND_IF_COND            = 8,
-    SEND_CSD                = 9,
-    STOP_TRANSMISSION       = 12,
-    SEND_STATUS             = 13,
-    SET_BLOCKLEN            = 16,
-    READ_BLOCK_SINGLE       = 17,
-    READ_BLOCK_MULTIPLE     = 18,
-    SEND_NUM_WR_BLOCKS      = 22,
-    SET_WR_BLK_ERASE_COUNT  = 23,
-    WRITE_BLOCK_SINGLE      = 24,
-    WRITE_BLOCK_MULTIPLE    = 25,
-    APP_OP_COND             = 41,
-    APP_CLR_CARD_DETECT     = 42,
-    APP_CMD                 = 55,
-    READ_OCR                = 58,
-    CRC_ON_OFF              = 59
+  GO_IDLE_STATE = 0,
+  SEND_OP_COND = 1,
+  SEND_CID = 2,
+  SEND_RELATIVE_ADDR = 3,
+  SEND_SWITCH_FUNC = 6,
+  SEND_IF_COND = 8,
+  SEND_CSD = 9,
+  STOP_TRANSMISSION = 12,
+  SEND_STATUS = 13,
+  SET_BLOCKLEN = 16,
+  READ_BLOCK_SINGLE = 17,
+  READ_BLOCK_MULTIPLE = 18,
+  SEND_NUM_WR_BLOCKS = 22,
+  SET_WR_BLK_ERASE_COUNT = 23,
+  WRITE_BLOCK_SINGLE = 24,
+  WRITE_BLOCK_MULTIPLE = 25,
+  APP_OP_COND = 41,
+  APP_CLR_CARD_DETECT = 42,
+  APP_CMD = 55,
+  READ_OCR = 58,
+  CRC_ON_OFF = 59
 } ardu_sdcard_command_t;
 
 typedef struct {
-    uint8_t ssPin;
-    SPIClass * spi;
-    int frequency;
-    char * base_path;
-    sdcard_type_t type;
-    unsigned long sectors;
-    bool supports_crc;
-    int status;
+  uint8_t ssPin;
+  SPIClass *spi;
+  int frequency;
+  char *base_path;
+  sdcard_type_t type;
+  unsigned long sectors;
+  bool supports_crc;
+  int status;
 } ardu_sdcard_t;
 
-static ardu_sdcard_t* s_cards[FF_VOLUMES] = { NULL };
+static ardu_sdcard_t *s_cards[FF_VOLUMES] = {NULL};
+
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
+const char *fferr2str[] = {
+  "(0) Succeeded",
+  "(1) A hard error occurred in the low level disk I/O layer",
+  "(2) Assertion failed",
+  "(3) The physical drive cannot work",
+  "(4) Could not find the file",
+  "(5) Could not find the path",
+  "(6) The path name format is invalid",
+  "(7) Access denied due to prohibited access or directory full",
+  "(8) Access denied due to prohibited access",
+  "(9) The file/directory object is invalid",
+  "(10) The physical drive is write protected",
+  "(11) The logical drive number is invalid",
+  "(12) The volume has no work area",
+  "(13) There is no valid FAT volume",
+  "(14) The f_mkfs() aborted due to any problem",
+  "(15) Could not get a grant to access the volume within defined period",
+  "(16) The operation is rejected according to the file sharing policy",
+  "(17) LFN working buffer could not be allocated",
+  "(18) Number of open files > FF_FS_LOCK",
+  "(19) Given parameter is invalid"
+};
+#endif
 
 /*
  * SD SPI
  * */
 
-bool sdWait(uint8_t pdrv, int timeout)
-{
-    char resp;
-    uint32_t start = millis();
+bool sdWait(uint8_t pdrv, int timeout) {
+  char resp;
+  uint32_t start = millis();
 
-    do {
-        resp = s_cards[pdrv]->spi->transfer(0xFF);
-    } while (resp == 0x00 && (millis() - start) < (unsigned int)timeout);
+  do {
+    resp = s_cards[pdrv]->spi->transfer(0xFF);
+  } while (resp == 0x00 && (millis() - start) < (unsigned int)timeout);
 
-    return (resp > 0x00);
+  if (!resp) {
+    log_w("Wait Failed");
+  }
+  return (resp > 0x00);
 }
 
-void sdStop(uint8_t pdrv)
-{
-    s_cards[pdrv]->spi->write(0xFD);
+void sdStop(uint8_t pdrv) {
+  s_cards[pdrv]->spi->write(0xFD);
 }
 
-void sdDeselectCard(uint8_t pdrv)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    digitalWrite(card->ssPin, HIGH);
+void sdDeselectCard(uint8_t pdrv) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  digitalWrite(card->ssPin, HIGH);
 }
 
-bool sdSelectCard(uint8_t pdrv)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    digitalWrite(card->ssPin, LOW);
-    sdWait(pdrv, 300);
-    return true;
+bool sdSelectCard(uint8_t pdrv) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  digitalWrite(card->ssPin, LOW);
+  bool s = sdWait(pdrv, 500);
+  if (!s) {
+    log_e("Select Failed");
+    digitalWrite(card->ssPin, HIGH);
+    return false;
+  }
+  return true;
 }
 
-char sdCommand(uint8_t pdrv, char cmd, unsigned int arg, unsigned int* resp)
-{
-    char token;
-    ardu_sdcard_t * card = s_cards[pdrv];
-
-    for (int f = 0; f < 3; f++) {
-        if (cmd == SEND_NUM_WR_BLOCKS || cmd == SET_WR_BLK_ERASE_COUNT || cmd == APP_OP_COND || cmd == APP_CLR_CARD_DETECT) {
-            token = sdCommand(pdrv, APP_CMD, 0, NULL);
-            sdDeselectCard(pdrv);
-            if (token > 1) {
-                return token;
-            }
-            if(!sdSelectCard(pdrv)) {
-                return 0xFF;
-            }
-        }
+char sdCommand(uint8_t pdrv, char cmd, unsigned int arg, unsigned int *resp) {
+  char token;
+  ardu_sdcard_t *card = s_cards[pdrv];
 
-        char cmdPacket[7];
-        cmdPacket[0] = cmd | 0x40;
-        cmdPacket[1] = arg >> 24;
-        cmdPacket[2] = arg >> 16;
-        cmdPacket[3] = arg >> 8;
-        cmdPacket[4] = arg;
-        if(card->supports_crc || cmd == GO_IDLE_STATE || cmd == SEND_IF_COND) {
-            cmdPacket[5] = (CRC7(cmdPacket, 5) << 1) | 0x01;
-        } else {
-            cmdPacket[5] = 0x01;
-        }
-        cmdPacket[6] = 0xFF;
-
-        card->spi->writeBytes((uint8_t*)cmdPacket, (cmd == STOP_TRANSMISSION)?7:6);
-
-        for (int i = 0; i < 9; i++) {
-            token = card->spi->transfer(0xFF);
-            if (!(token & 0x80)) {
-                break;
-            }
-        }
+  for (int f = 0; f < 3; f++) {
+    if (cmd == SEND_NUM_WR_BLOCKS || cmd == SET_WR_BLK_ERASE_COUNT || cmd == APP_OP_COND || cmd == APP_CLR_CARD_DETECT) {
+      token = sdCommand(pdrv, APP_CMD, 0, NULL);
+      sdDeselectCard(pdrv);
+      if (token > 1) {
+        break;
+      }
+      if (!sdSelectCard(pdrv)) {
+        token = 0xFF;
+        break;
+      }
+    }
 
-        if (token == 0xFF) {
-            log_w("no token received");
-            sdDeselectCard(pdrv);
-            delay(100);
-            sdSelectCard(pdrv);
-            continue;
-        } else if (token & 0x08) {
-            log_w("crc error");
-            sdDeselectCard(pdrv);
-            delay(100);
-            sdSelectCard(pdrv);
-            continue;
-        } else if (token > 1) {
-            log_w("token error [%u] 0x%x", cmd, token);
-            break;
-        }
+    char cmdPacket[7];
+    cmdPacket[0] = cmd | 0x40;
+    cmdPacket[1] = arg >> 24;
+    cmdPacket[2] = arg >> 16;
+    cmdPacket[3] = arg >> 8;
+    cmdPacket[4] = arg;
+    if (card->supports_crc || cmd == GO_IDLE_STATE || cmd == SEND_IF_COND) {
+      cmdPacket[5] = (CRC7(cmdPacket, 5) << 1) | 0x01;
+    } else {
+      cmdPacket[5] = 0x01;
+    }
+    cmdPacket[6] = 0xFF;
 
-        if (cmd == SEND_STATUS && resp) {
-            *resp = card->spi->transfer(0xFF);
-        } else if ((cmd == SEND_IF_COND || cmd == READ_OCR) && resp) {
-            *resp = card->spi->transfer32(0xFFFFFFFF);
-        }
+    card->spi->writeBytes((uint8_t *)cmdPacket, (cmd == STOP_TRANSMISSION) ? 7 : 6);
 
+    for (int i = 0; i < 9; i++) {
+      token = card->spi->transfer(0xFF);
+      if (!(token & 0x80)) {
         break;
-    }
-
-    return token;
+      }
+    }
+
+    if (token == 0xFF) {
+      log_w("no token received");
+      sdDeselectCard(pdrv);
+      delay(100);
+      sdSelectCard(pdrv);
+      continue;
+    } else if (token & 0x08) {
+      log_w("crc error");
+      sdDeselectCard(pdrv);
+      delay(100);
+      sdSelectCard(pdrv);
+      continue;
+    } else if (token > 1) {
+      log_w("token error [%u] 0x%x", cmd, token);
+      break;
+    }
+
+    if (cmd == SEND_STATUS && resp) {
+      *resp = card->spi->transfer(0xFF);
+    } else if ((cmd == SEND_IF_COND || cmd == READ_OCR) && resp) {
+      *resp = card->spi->transfer32(0xFFFFFFFF);
+    }
+
+    break;
+  }
+  if (token == 0xFF) {
+    log_e("Card Failed! cmd: 0x%02x", cmd);
+    card->status = STA_NOINIT;
+  }
+  return token;
 }
 
-bool sdReadBytes(uint8_t pdrv, char* buffer, int length)
-{
-    char token;
-    unsigned short crc;
-    ardu_sdcard_t * card = s_cards[pdrv];
+bool sdReadBytes(uint8_t pdrv, char *buffer, int length) {
+  char token;
+  unsigned short crc;
+  ardu_sdcard_t *card = s_cards[pdrv];
 
-    uint32_t start = millis();
-    do {
-        token = card->spi->transfer(0xFF);
-    } while (token == 0xFF && (millis() - start) < 500);
+  uint32_t start = millis();
+  do {
+    token = card->spi->transfer(0xFF);
+  } while (token == 0xFF && (millis() - start) < 500);
 
-    if (token != 0xFE) {
-        return false;
-    }
+  if (token != 0xFE) {
+    return false;
+  }
 
-    card->spi->transferBytes(NULL, (uint8_t*)buffer, length);
-    crc = card->spi->transfer16(0xFFFF);
-    return (!card->supports_crc || crc == CRC16(buffer, length));
+  card->spi->transferBytes(NULL, (uint8_t *)buffer, length);
+  crc = card->spi->transfer16(0xFFFF);
+  return (!card->supports_crc || crc == CRC16(buffer, length));
 }
 
-char sdWriteBytes(uint8_t pdrv, const char* buffer, char token)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    unsigned short crc = (card->supports_crc)?CRC16(buffer, 512):0xFFFF;
-    if (!sdWait(pdrv, 500)) {
-        return false;
-    }
+char sdWriteBytes(uint8_t pdrv, const char *buffer, char token) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  unsigned short crc = (card->supports_crc) ? CRC16(buffer, 512) : 0xFFFF;
+  if (!sdWait(pdrv, 500)) {
+    return 0;
+  }
 
-    card->spi->write(token);
-    card->spi->writeBytes((uint8_t*)buffer, 512);
-    card->spi->write16(crc);
-    return (card->spi->transfer(0xFF) & 0x1F);
+  card->spi->write(token);
+  card->spi->writeBytes((uint8_t *)buffer, 512);
+  card->spi->write16(crc);
+  return (card->spi->transfer(0xFF) & 0x1F);
 }
 
 /*
  * SPI SDCARD Communication
  * */
 
-char sdTransaction(uint8_t pdrv, char cmd, unsigned int arg, unsigned int* resp)
-{
-    if(!sdSelectCard(pdrv)) {
-        return 0xFF;
-    }
-    char token = sdCommand(pdrv, cmd, arg, resp);
-    sdDeselectCard(pdrv);
-    return token;
+char sdTransaction(uint8_t pdrv, char cmd, unsigned int arg, unsigned int *resp) {
+  if (!sdSelectCard(pdrv)) {
+    return 0xFF;
+  }
+  char token = sdCommand(pdrv, cmd, arg, resp);
+  sdDeselectCard(pdrv);
+  return token;
 }
 
-bool sdReadSector(uint8_t pdrv, char* buffer, unsigned long long sector)
-{
-    for (int f = 0; f < 3; f++) {
-        if(!sdSelectCard(pdrv)) {
-            break;
-        }
-        if (!sdCommand(pdrv, READ_BLOCK_SINGLE, (s_cards[pdrv]->type == CARD_SDHC) ? sector : sector << 9, NULL)) {
-            bool success = sdReadBytes(pdrv, buffer, 512);
-            sdDeselectCard(pdrv);
-            if (success) {
-                return true;
-            }
-        } else {
-            break;
-        }
+bool sdReadSector(uint8_t pdrv, char *buffer, unsigned long long sector) {
+  for (int f = 0; f < 3; f++) {
+    if (!sdSelectCard(pdrv)) {
+      return false;
+    }
+    if (!sdCommand(pdrv, READ_BLOCK_SINGLE, (s_cards[pdrv]->type == CARD_SDHC) ? sector : sector << 9, NULL)) {
+      bool success = sdReadBytes(pdrv, buffer, 512);
+      sdDeselectCard(pdrv);
+      if (success) {
+        return true;
+      }
+    } else {
+      break;
     }
-    sdDeselectCard(pdrv);
-    return false;
+  }
+  sdDeselectCard(pdrv);
+  return false;
 }
 
-bool sdReadSectors(uint8_t pdrv, char* buffer, unsigned long long sector, int count)
-{
-    for (int f = 0; f < 3;) {
-        if(!sdSelectCard(pdrv)) {
-            break;
+bool sdReadSectors(uint8_t pdrv, char *buffer, unsigned long long sector, int count) {
+  for (int f = 0; f < 3;) {
+    if (!sdSelectCard(pdrv)) {
+      return false;
+    }
+
+    if (!sdCommand(pdrv, READ_BLOCK_MULTIPLE, (s_cards[pdrv]->type == CARD_SDHC) ? sector : sector << 9, NULL)) {
+      do {
+        if (!sdReadBytes(pdrv, buffer, 512)) {
+          f++;
+          break;
         }
 
-        if (!sdCommand(pdrv, READ_BLOCK_MULTIPLE, (s_cards[pdrv]->type == CARD_SDHC) ? sector : sector << 9, NULL)) {
-            do {
-                if (!sdReadBytes(pdrv, buffer, 512)) {
-                    f++;
-                    break;
-                }
-
-                sector++;
-                buffer += 512;
-                f = 0;
-            } while (--count);
-
-            if (sdCommand(pdrv, STOP_TRANSMISSION, 0, NULL)) {
-                log_e("command failed");
-                break;
-            }
+        sector++;
+        buffer += 512;
+        f = 0;
+      } while (--count);
 
-            sdDeselectCard(pdrv);
-            if (count == 0) {
-                return true;
-            }
-        } else {
-            break;
-        }
+      if (sdCommand(pdrv, STOP_TRANSMISSION, 0, NULL)) {
+        log_e("command failed");
+        break;
+      }
+
+      sdDeselectCard(pdrv);
+      if (count == 0) {
+        return true;
+      }
+    } else {
+      break;
     }
-    sdDeselectCard(pdrv);
-    return false;
+  }
+  sdDeselectCard(pdrv);
+  return false;
 }
 
-bool sdWriteSector(uint8_t pdrv, const char* buffer, unsigned long long sector)
-{
-    for (int f = 0; f < 3; f++) {
-        if(!sdSelectCard(pdrv)) {
-            break;
-        }
-        if (!sdCommand(pdrv, WRITE_BLOCK_SINGLE, (s_cards[pdrv]->type == CARD_SDHC) ? sector : sector << 9, NULL)) {
-            char token = sdWriteBytes(pdrv, buffer, 0xFE);
-            sdDeselectCard(pdrv);
+bool sdWriteSector(uint8_t pdrv, const char *buffer, unsigned long long sector) {
+  for (int f = 0; f < 3; f++) {
+    if (!sdSelectCard(pdrv)) {
+      return false;
+    }
+    if (!sdCommand(pdrv, WRITE_BLOCK_SINGLE, (s_cards[pdrv]->type == CARD_SDHC) ? sector : sector << 9, NULL)) {
+      char token = sdWriteBytes(pdrv, buffer, 0xFE);
+      sdDeselectCard(pdrv);
 
-            if (token == 0x0A) {
-                continue;
-            } else if (token == 0x0C) {
-                return false;
-            }
+      if (token == 0x0A) {
+        continue;
+      } else if (token == 0x0C) {
+        return false;
+      }
 
-            unsigned int resp;
-            if (sdTransaction(pdrv, SEND_STATUS, 0, &resp) || resp) {
-                return false;
-            }
-            return true;
-        } else {
-            break;
-        }
+      unsigned int resp;
+      if (sdTransaction(pdrv, SEND_STATUS, 0, &resp) || resp) {
+        return false;
+      }
+      return true;
+    } else {
+      break;
     }
-    sdDeselectCard(pdrv);
-    return false;
+  }
+  sdDeselectCard(pdrv);
+  return false;
 }
 
-bool sdWriteSectors(uint8_t pdrv, const char* buffer, unsigned long long sector, int count)
-{
-    char token;
-    const char* currentBuffer = buffer;
-    unsigned long long currentSector = sector;
-    int currentCount = count;
-    ardu_sdcard_t * card = s_cards[pdrv];
-
-    for (int f = 0; f < 3;) {
-        if (card->type != CARD_MMC) {
-            if (sdTransaction(pdrv, SET_WR_BLK_ERASE_COUNT, currentCount, NULL)) {
-                break;
-            }
-        }
+bool sdWriteSectors(uint8_t pdrv, const char *buffer, unsigned long long sector, int count) {
+  char token;
+  const char *currentBuffer = buffer;
+  unsigned long long currentSector = sector;
+  int currentCount = count;
+  ardu_sdcard_t *card = s_cards[pdrv];
+
+  for (int f = 0; f < 3;) {
+    if (card->type != CARD_MMC) {
+      if (sdTransaction(pdrv, SET_WR_BLK_ERASE_COUNT, currentCount, NULL)) {
+        return false;
+      }
+    }
+
+    if (!sdSelectCard(pdrv)) {
+      return false;
+    }
 
-        if(!sdSelectCard(pdrv)) {
-            break;
+    if (!sdCommand(pdrv, WRITE_BLOCK_MULTIPLE, (card->type == CARD_SDHC) ? currentSector : currentSector << 9, NULL)) {
+      do {
+        token = sdWriteBytes(pdrv, currentBuffer, 0xFC);
+        if (token != 0x05) {
+          f++;
+          break;
         }
+        currentBuffer += 512;
+        f = 0;
+      } while (--currentCount);
 
-        if (!sdCommand(pdrv, WRITE_BLOCK_MULTIPLE, (card->type == CARD_SDHC) ? currentSector : currentSector << 9, NULL)) {
-            do {
-                token = sdWriteBytes(pdrv, currentBuffer, 0xFC);
-                if (token != 0x05) {
-                    f++;
-                    break;
-                }
-                currentBuffer += 512;
-                f = 0;
-            } while (--currentCount);
-
-            if (!sdWait(pdrv, 500)) {
-                break;
-            }
+      if (!sdWait(pdrv, 500)) {
+        break;
+      }
+
+      if (currentCount == 0) {
+        sdStop(pdrv);
+        sdDeselectCard(pdrv);
+
+        unsigned int resp;
+        if (sdTransaction(pdrv, SEND_STATUS, 0, &resp) || resp) {
+          return false;
+        }
+        return true;
+      } else {
+        if (sdCommand(pdrv, STOP_TRANSMISSION, 0, NULL)) {
+          break;
+        }
 
-            if (currentCount == 0) {
-                sdStop(pdrv);
-                sdDeselectCard(pdrv);
-
-                unsigned int resp;
-                if (sdTransaction(pdrv, SEND_STATUS, 0, &resp) || resp) {
-                    return false;
-                }
-                return true;
-            } else {
-                if (sdCommand(pdrv, STOP_TRANSMISSION, 0, NULL)) {
-                    break;
-                }
-
-                sdDeselectCard(pdrv);
-
-                if (token == 0x0A) {
-                    unsigned int writtenBlocks = 0;
-                    if (card->type != CARD_MMC && sdSelectCard(pdrv)) {
-                        if (!sdCommand(pdrv, SEND_NUM_WR_BLOCKS, 0, NULL)) {
-                            char acmdData[4];
-                            if (sdReadBytes(pdrv, acmdData, 4)) {
-                                writtenBlocks = acmdData[0] << 24;
-                                writtenBlocks |= acmdData[1] << 16;
-                                writtenBlocks |= acmdData[2] << 8;
-                                writtenBlocks |= acmdData[3];
-                            }
-                        }
-                        sdDeselectCard(pdrv);
-                    }
-                    currentBuffer = buffer + (writtenBlocks << 9);
-                    currentSector = sector + writtenBlocks;
-                    currentCount = count - writtenBlocks;
-                    continue;
-                } else {
-                    return false;
-                }
+        if (token == 0x0A) {
+          sdDeselectCard(pdrv);
+          unsigned int writtenBlocks = 0;
+          if (card->type != CARD_MMC && sdSelectCard(pdrv)) {
+            if (!sdCommand(pdrv, SEND_NUM_WR_BLOCKS, 0, NULL)) {
+              char acmdData[4];
+              if (sdReadBytes(pdrv, acmdData, 4)) {
+                writtenBlocks = acmdData[0] << 24;
+                writtenBlocks |= acmdData[1] << 16;
+                writtenBlocks |= acmdData[2] << 8;
+                writtenBlocks |= acmdData[3];
+              }
             }
+            sdDeselectCard(pdrv);
+          }
+          currentBuffer = buffer + (writtenBlocks << 9);
+          currentSector = sector + writtenBlocks;
+          currentCount = count - writtenBlocks;
+          continue;
         } else {
-            break;
+          break;
         }
+      }
+    } else {
+      break;
     }
-    sdDeselectCard(pdrv);
-    return false;
+  }
+  sdDeselectCard(pdrv);
+  return false;
 }
 
-unsigned long sdGetSectorsCount(uint8_t pdrv)
-{
-    for (int f = 0; f < 3; f++) {
-        if(!sdSelectCard(pdrv)) {
-            break;
-        }
+unsigned long sdGetSectorsCount(uint8_t pdrv) {
+  for (int f = 0; f < 3; f++) {
+    if (!sdSelectCard(pdrv)) {
+      return 0;
+    }
 
-        if (!sdCommand(pdrv, SEND_CSD, 0, NULL)) {
-            char csd[16];
-            bool success = sdReadBytes(pdrv, csd, 16);
-            sdDeselectCard(pdrv);
-            if (success) {
-                if ((csd[0] >> 6) == 0x01) {
-                    unsigned long size = (
-                         ((unsigned long)(csd[7] & 0x3F) << 16)
-                         | ((unsigned long)csd[8] << 8)
-                         | csd[9]
-                     ) + 1;
-                    return size << 10;
-                }
-                unsigned long size = (
-                     ((unsigned long)(csd[6] & 0x03) << 10)
-                     | ((unsigned long)csd[7] << 2)
-                     | ((csd[8] & 0xC0) >> 6)
-                 ) + 1;
-                size <<= ((
-                     ((csd[9] & 0x03) << 1)
-                     | ((csd[10] & 0x80) >> 7)
-                 ) + 2);
-                size <<= (csd[5] & 0x0F);
-                return size >> 9;
-            }
-        } else {
-            break;
+    if (!sdCommand(pdrv, SEND_CSD, 0, NULL)) {
+      char csd[16];
+      bool success = sdReadBytes(pdrv, csd, 16);
+      sdDeselectCard(pdrv);
+      if (success) {
+        if ((csd[0] >> 6) == 0x01) {
+          unsigned long size = (((unsigned long)(csd[7] & 0x3F) << 16) | ((unsigned long)csd[8] << 8) | csd[9]) + 1;
+          return size << 10;
         }
+        unsigned long size = (((unsigned long)(csd[6] & 0x03) << 10) | ((unsigned long)csd[7] << 2) | ((csd[8] & 0xC0) >> 6)) + 1;
+        size <<= ((((csd[9] & 0x03) << 1) | ((csd[10] & 0x80) >> 7)) + 2);
+        size <<= (csd[5] & 0x0F);
+        return size >> 9;
+      }
+    } else {
+      break;
     }
+  }
 
-    sdDeselectCard(pdrv);
-    return 0;
+  sdDeselectCard(pdrv);
+  return 0;
 }
 
+namespace {
 
-namespace
-{
+struct AcquireSPI {
+  ardu_sdcard_t *card;
+  explicit AcquireSPI(ardu_sdcard_t *card) : card(card) {
+    card->spi->beginTransaction(SPISettings(card->frequency, MSBFIRST, SPI_MODE0));
+  }
+  AcquireSPI(ardu_sdcard_t *card, int frequency) : card(card) {
+    card->spi->beginTransaction(SPISettings(frequency, MSBFIRST, SPI_MODE0));
+  }
+  ~AcquireSPI() {
+    card->spi->endTransaction();
+  }
 
-struct AcquireSPI
-{
-    ardu_sdcard_t *card;
-    explicit AcquireSPI(ardu_sdcard_t* card)
-        : card(card)
-    {
-        card->spi->beginTransaction(SPISettings(card->frequency, MSBFIRST, SPI_MODE0));
-    }
-    AcquireSPI(ardu_sdcard_t* card, int frequency)
-        : card(card)
-    {
-        card->spi->beginTransaction(SPISettings(frequency, MSBFIRST, SPI_MODE0));
-    }
-    ~AcquireSPI()
-    {
-        card->spi->endTransaction();
-    }
 private:
-    AcquireSPI(AcquireSPI const&);
-    AcquireSPI& operator=(AcquireSPI const&);
+  AcquireSPI(AcquireSPI const &);
+  AcquireSPI &operator=(AcquireSPI const &);
 };
 
-}
-
+}  // namespace
 
 /*
  * FATFS API
  * */
 
-DSTATUS ff_sd_initialize(uint8_t pdrv)
-{
-    char token;
-    unsigned int resp;
-    unsigned int start;
-    ardu_sdcard_t * card = s_cards[pdrv];
+DSTATUS ff_sd_initialize(uint8_t pdrv) {
+  char token;
+  unsigned int resp;
+  unsigned int start;
+  ardu_sdcard_t *card = s_cards[pdrv];
 
-    if (!(card->status & STA_NOINIT)) {
-        return card->status;
-    }
+  if (!(card->status & STA_NOINIT)) {
+    return card->status;
+  }
 
-    AcquireSPI card_locked(card, 400000);
+  AcquireSPI card_locked(card, 400000);
 
-    digitalWrite(card->ssPin, HIGH);
-    for (uint8_t i = 0; i < 20; i++) {
-        card->spi->transfer(0XFF);
-    }
+  digitalWrite(card->ssPin, HIGH);
+  for (uint8_t i = 0; i < 20; i++) {
+    card->spi->transfer(0XFF);
+  }
 
-    if (sdTransaction(pdrv, GO_IDLE_STATE, 0, NULL) != 1) {
-        log_w("GO_IDLE_STATE failed");
-        goto unknown_card;
-    }
+  // Fix mount issue - sdWait fail ignored before command GO_IDLE_STATE
+  digitalWrite(card->ssPin, LOW);
+  if (!sdWait(pdrv, 500)) {
+    log_w("sdWait fail ignored, card initialize continues");
+  }
+  if (sdCommand(pdrv, GO_IDLE_STATE, 0, NULL) != 1) {
+    sdDeselectCard(pdrv);
+    log_w("GO_IDLE_STATE failed");
+    goto unknown_card;
+  }
+  sdDeselectCard(pdrv);
 
-    token = sdTransaction(pdrv, CRC_ON_OFF, 1, NULL);
-    if (token == 0x5) {
-        //old card maybe
-        card->supports_crc = false;
-    } else if (token != 1) {
-        log_w("CRC_ON_OFF failed: %u", token);
-        goto unknown_card;
-    }
+  token = sdTransaction(pdrv, CRC_ON_OFF, 1, NULL);
+  if (token == 0x5) {
+    //old card maybe
+    card->supports_crc = false;
+  } else if (token != 1) {
+    log_w("CRC_ON_OFF failed: %u", token);
+    goto unknown_card;
+  }
 
-    if (sdTransaction(pdrv, SEND_IF_COND, 0x1AA, &resp) == 1) {
-        if ((resp & 0xFFF) != 0x1AA) {
-            log_w("SEND_IF_COND failed: %03X", resp & 0xFFF);
-            goto unknown_card;
-        }
+  if (sdTransaction(pdrv, SEND_IF_COND, 0x1AA, &resp) == 1) {
+    if ((resp & 0xFFF) != 0x1AA) {
+      log_w("SEND_IF_COND failed: %03X", resp & 0xFFF);
+      goto unknown_card;
+    }
 
-        if (sdTransaction(pdrv, READ_OCR, 0, &resp) != 1 || !(resp & (1 << 20))) {
-            log_w("READ_OCR failed: %X", resp);
-            goto unknown_card;
-        }
+    if (sdTransaction(pdrv, READ_OCR, 0, &resp) != 1 || !(resp & (1 << 20))) {
+      log_w("READ_OCR failed: %X", resp);
+      goto unknown_card;
+    }
 
-        start = millis();
-        do {
-            token = sdTransaction(pdrv, APP_OP_COND, 0x40100000, NULL);
-        } while (token == 1 && (millis() - start) < 1000);
+    start = millis();
+    do {
+      token = sdTransaction(pdrv, APP_OP_COND, 0x40100000, NULL);
+    } while (token == 1 && (millis() - start) < 1000);
 
-        if (token) {
-            log_w("APP_OP_COND failed: %u", token);
-            goto unknown_card;
-        }
+    if (token) {
+      log_w("APP_OP_COND failed: %u", token);
+      goto unknown_card;
+    }
 
-        if (!sdTransaction(pdrv, READ_OCR, 0, &resp)) {
-            if (resp & (1 << 30)) {
-                card->type = CARD_SDHC;
-            } else {
-                card->type = CARD_SD;
-            }
-        } else {
-            log_w("READ_OCR failed: %X", resp);
-            goto unknown_card;
-        }
+    if (!sdTransaction(pdrv, READ_OCR, 0, &resp)) {
+      if (resp & (1 << 30)) {
+        card->type = CARD_SDHC;
+      } else {
+        card->type = CARD_SD;
+      }
     } else {
-        if (sdTransaction(pdrv, READ_OCR, 0, &resp) != 1 || !(resp & (1 << 20))) {
-            log_w("READ_OCR failed: %X", resp);
-            goto unknown_card;
-        }
+      log_w("READ_OCR failed: %X", resp);
+      goto unknown_card;
+    }
+  } else {
+    if (sdTransaction(pdrv, READ_OCR, 0, &resp) != 1 || !(resp & (1 << 20))) {
+      log_w("READ_OCR failed: %X", resp);
+      goto unknown_card;
+    }
 
-        start = millis();
-        do {
-            token = sdTransaction(pdrv, APP_OP_COND, 0x100000, NULL);
-        } while (token == 0x01 && (millis() - start) < 1000);
+    start = millis();
+    do {
+      token = sdTransaction(pdrv, APP_OP_COND, 0x100000, NULL);
+    } while (token == 0x01 && (millis() - start) < 1000);
 
-        if (!token) {
-            card->type = CARD_SD;
-        } else {
-            start = millis();
-            do {
-                token = sdTransaction(pdrv, SEND_OP_COND, 0x100000, NULL);
-            } while (token != 0x00 && (millis() - start) < 1000);
-
-            if (token == 0x00) {
-                card->type = CARD_MMC;
-            } else {
-                log_w("SEND_OP_COND failed: %u", token);
-                goto unknown_card;
-            }
-        }
+    if (!token) {
+      card->type = CARD_SD;
+    } else {
+      start = millis();
+      do {
+        token = sdTransaction(pdrv, SEND_OP_COND, 0x100000, NULL);
+      } while (token != 0x00 && (millis() - start) < 1000);
+
+      if (token == 0x00) {
+        card->type = CARD_MMC;
+      } else {
+        log_w("SEND_OP_COND failed: %u", token);
+        goto unknown_card;
+      }
     }
+  }
 
-    if (card->type != CARD_MMC) {
-        if (sdTransaction(pdrv, APP_CLR_CARD_DETECT, 0, NULL)) {
-            log_w("APP_CLR_CARD_DETECT failed");
-            goto unknown_card;
-        }
+  if (card->type != CARD_MMC) {
+    if (sdTransaction(pdrv, APP_CLR_CARD_DETECT, 0, NULL)) {
+      log_w("APP_CLR_CARD_DETECT failed");
+      goto unknown_card;
     }
+  }
 
-    if (card->type != CARD_SDHC) {
-        if (sdTransaction(pdrv, SET_BLOCKLEN, 512, NULL) != 0x00) {
-            log_w("SET_BLOCKLEN failed");
-            goto unknown_card;
-        }
+  if (card->type != CARD_SDHC) {
+    if (sdTransaction(pdrv, SET_BLOCKLEN, 512, NULL) != 0x00) {
+      log_w("SET_BLOCKLEN failed");
+      goto unknown_card;
     }
+  }
 
-    card->sectors = sdGetSectorsCount(pdrv);
+  card->sectors = sdGetSectorsCount(pdrv);
 
-    if (card->frequency > 25000000) {
-        card->frequency = 25000000;
-    }
+  if (card->frequency > 25000000) {
+    card->frequency = 25000000;
+  }
 
-    card->status &= ~STA_NOINIT;
-    return card->status;
+  card->status &= ~STA_NOINIT;
+  return card->status;
 
 unknown_card:
-    card->type = CARD_UNKNOWN;
-    return card->status;
+  card->type = CARD_UNKNOWN;
+  return card->status;
 }
 
-DSTATUS ff_sd_status(uint8_t pdrv)
-{
-    return s_cards[pdrv]->status;
-}
-
-DRESULT ff_sd_read(uint8_t pdrv, uint8_t* buffer, DWORD sector, UINT count)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    if (card->status & STA_NOINIT) {
-        return RES_NOTRDY;
-    }
-    DRESULT res = RES_OK;
+DSTATUS ff_sd_status(uint8_t pdrv) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  AcquireSPI lock(card);
 
-    AcquireSPI lock(card);
-
-    if (count > 1) {
-        res = sdReadSectors(pdrv, (char*)buffer, sector, count) ? RES_OK : RES_ERROR;
-    } else {
-        res = sdReadSector(pdrv, (char*)buffer, sector) ? RES_OK : RES_ERROR;
-    }
-    return res;
+  if (sdTransaction(pdrv, SEND_STATUS, 0, NULL)) {
+    log_e("Check status failed");
+    return STA_NOINIT;
+  }
+  return s_cards[pdrv]->status;
 }
 
-DRESULT ff_sd_write(uint8_t pdrv, const uint8_t* buffer, DWORD sector, UINT count)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    if (card->status & STA_NOINIT) {
-        return RES_NOTRDY;
-    }
-
-    if (card->status & STA_PROTECT) {
-        return RES_WRPRT;
-    }
-    DRESULT res = RES_OK;
-
-    AcquireSPI lock(card);
+DRESULT ff_sd_read(uint8_t pdrv, uint8_t *buffer, DWORD sector, UINT count) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  if (card->status & STA_NOINIT) {
+    return RES_NOTRDY;
+  }
+  DRESULT res = RES_OK;
+
+  AcquireSPI lock(card);
+
+  if (count > 1) {
+    res = sdReadSectors(pdrv, (char *)buffer, sector, count) ? RES_OK : RES_ERROR;
+  } else {
+    res = sdReadSector(pdrv, (char *)buffer, sector) ? RES_OK : RES_ERROR;
+  }
+  return res;
+}
 
-    if (count > 1) {
-        res = sdWriteSectors(pdrv, (const char*)buffer, sector, count) ? RES_OK : RES_ERROR;
-    } else {
-        res = sdWriteSector(pdrv, (const char*)buffer, sector) ? RES_OK : RES_ERROR;
-    }
-    return res;
+DRESULT ff_sd_write(uint8_t pdrv, const uint8_t *buffer, DWORD sector, UINT count) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  if (card->status & STA_NOINIT) {
+    return RES_NOTRDY;
+  }
+
+  if (card->status & STA_PROTECT) {
+    return RES_WRPRT;
+  }
+  DRESULT res = RES_OK;
+
+  AcquireSPI lock(card);
+
+  if (count > 1) {
+    res = sdWriteSectors(pdrv, (const char *)buffer, sector, count) ? RES_OK : RES_ERROR;
+  } else {
+    res = sdWriteSector(pdrv, (const char *)buffer, sector) ? RES_OK : RES_ERROR;
+  }
+  return res;
 }
 
-DRESULT ff_sd_ioctl(uint8_t pdrv, uint8_t cmd, void* buff)
-{
-    switch(cmd) {
+DRESULT ff_sd_ioctl(uint8_t pdrv, uint8_t cmd, void *buff) {
+  switch (cmd) {
     case CTRL_SYNC:
-        {
-            AcquireSPI lock(s_cards[pdrv]);
-            if (sdSelectCard(pdrv)) {
-                sdDeselectCard(pdrv);
-                return RES_OK;
-            }
-        }
-        return RES_ERROR;
-    case GET_SECTOR_COUNT:
-        *((unsigned long*) buff) = s_cards[pdrv]->sectors;
-        return RES_OK;
-    case GET_SECTOR_SIZE:
-        *((WORD*) buff) = 512;
-        return RES_OK;
-    case GET_BLOCK_SIZE:
-        *((uint32_t*)buff) = 1;
+    {
+      AcquireSPI lock(s_cards[pdrv]);
+      if (sdSelectCard(pdrv)) {
+        sdDeselectCard(pdrv);
         return RES_OK;
-    }
-    return RES_PARERR;
+      }
+    }
+      return RES_ERROR;
+    case GET_SECTOR_COUNT: *((unsigned long *)buff) = s_cards[pdrv]->sectors; return RES_OK;
+    case GET_SECTOR_SIZE:  *((WORD *)buff) = 512; return RES_OK;
+    case GET_BLOCK_SIZE:   *((uint32_t *)buff) = 1; return RES_OK;
+  }
+  return RES_PARERR;
 }
 
+bool sd_read_raw(uint8_t pdrv, uint8_t *buffer, DWORD sector) {
+  return ff_sd_read(pdrv, buffer, sector, 1) == ESP_OK;
+}
+
+bool sd_write_raw(uint8_t pdrv, uint8_t *buffer, DWORD sector) {
+  return ff_sd_write(pdrv, buffer, sector, 1) == ESP_OK;
+}
 
 /*
  * Public methods
  * */
 
-uint8_t sdcard_uninit(uint8_t pdrv)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    if (pdrv >= FF_VOLUMES || card == NULL) {
-        return 1;
-    }
+uint8_t sdcard_uninit(uint8_t pdrv) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  if (pdrv >= FF_VOLUMES || card == NULL) {
+    return 1;
+  }
+  {
+    AcquireSPI lock(card);
     sdTransaction(pdrv, GO_IDLE_STATE, 0, NULL);
-    ff_diskio_register(pdrv, NULL);
-    s_cards[pdrv] = NULL;
-    esp_err_t err = ESP_OK;
-    if (card->base_path) {
-        err = esp_vfs_fat_unregister_path(card->base_path);
-    }
-    free(card);
-    return err;
+  }  // lock is destructed here
+  ff_diskio_register(pdrv, NULL);
+  s_cards[pdrv] = NULL;
+  esp_err_t err = ESP_OK;
+  if (card->base_path) {
+    err = esp_vfs_fat_unregister_path(card->base_path);
+    free(card->base_path);
+  }
+  free(card);
+  return err;
 }
 
-uint8_t sdcard_init(uint8_t cs, SPIClass * spi, int hz)
-{
+uint8_t sdcard_init(uint8_t cs, SPIClass *spi, int hz) {
 
-    uint8_t pdrv = 0xFF;
-    if (ff_diskio_get_drive(&pdrv) != ESP_OK || pdrv == 0xFF) {
-        return pdrv;
-    }
+  uint8_t pdrv = 0xFF;
+  if (ff_diskio_get_drive(&pdrv) != ESP_OK || pdrv == 0xFF) {
+    return pdrv;
+  }
 
-    ardu_sdcard_t * card = (ardu_sdcard_t *)malloc(sizeof(ardu_sdcard_t));
-    if (!card) {
-        return 0xFF;
-    }
+  ardu_sdcard_t *card = (ardu_sdcard_t *)malloc(sizeof(ardu_sdcard_t));
+  if (!card) {
+    return 0xFF;
+  }
 
-    card->base_path = NULL;
-    card->frequency = hz;
-    card->spi = spi;
-    card->ssPin = cs;
+  card->base_path = NULL;
+  card->frequency = hz;
+  card->spi = spi;
+  card->ssPin = digitalPinToGPIONumber(cs);
 
-    card->supports_crc = true;
-    card->type = CARD_NONE;
-    card->status = STA_NOINIT;
+  card->supports_crc = true;
+  card->type = CARD_NONE;
+  card->status = STA_NOINIT;
 
-    pinMode(card->ssPin, OUTPUT);
-    digitalWrite(card->ssPin, HIGH);
+  pinMode(card->ssPin, OUTPUT);
+  digitalWrite(card->ssPin, HIGH);
+  perimanSetPinBusExtraType(card->ssPin, "SD_SS");
 
-    s_cards[pdrv] = card;
+  s_cards[pdrv] = card;
 
-    static const ff_diskio_impl_t sd_impl = {
-        .init = &ff_sd_initialize,
-        .status = &ff_sd_status,
-        .read = &ff_sd_read,
-        .write = &ff_sd_write,
-        .ioctl = &ff_sd_ioctl
-    };
-    ff_diskio_register(pdrv, &sd_impl);
+  static const ff_diskio_impl_t sd_impl = {
+    .init = &ff_sd_initialize, .status = &ff_sd_status, .read = &ff_sd_read, .write = &ff_sd_write, .ioctl = &ff_sd_ioctl
+  };
+  ff_diskio_register(pdrv, &sd_impl);
 
-    return pdrv;
+  return pdrv;
 }
 
-uint8_t sdcard_unmount(uint8_t pdrv)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    if (pdrv >= FF_VOLUMES || card == NULL) {
-        return 1;
-    }
-    card->status |= STA_NOINIT;
-    card->type = CARD_NONE;
-
-    char drv[3] = {(char)('0' + pdrv), ':', 0};
-    f_mount(NULL, drv, 0);
-    return 0;
+uint8_t sdcard_unmount(uint8_t pdrv) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  if (pdrv >= FF_VOLUMES || card == NULL) {
+    return 1;
+  }
+  card->status |= STA_NOINIT;
+  card->type = CARD_NONE;
+
+  char drv[3] = {(char)('0' + pdrv), ':', 0};
+  f_mount(NULL, drv, 0);
+  return 0;
 }
 
-bool sdcard_mount(uint8_t pdrv, const char* path, uint8_t max_files)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    if(pdrv >= FF_VOLUMES || card == NULL){
-        return false;
-    }
-
-    if(card->base_path){
-        free(card->base_path);
-    }
-    card->base_path = strdup(path);
-
-    FATFS* fs;
-    char drv[3] = {(char)('0' + pdrv), ':', 0};
-    esp_err_t err = esp_vfs_fat_register(path, drv, max_files, &fs);
-    if (err == ESP_ERR_INVALID_STATE) {
-        log_e("esp_vfs_fat_register failed 0x(%x): SD is registered.", err);
+bool sdcard_mount(uint8_t pdrv, const char *path, uint8_t max_files, bool format_if_empty) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  if (pdrv >= FF_VOLUMES || card == NULL) {
+    return false;
+  }
+
+  if (card->base_path) {
+    free(card->base_path);
+  }
+  card->base_path = strdup(path);
+
+  FATFS *fs;
+  char drv[3] = {(char)('0' + pdrv), ':', 0};
+  esp_err_t err = esp_vfs_fat_register(path, drv, max_files, &fs);
+  if (err == ESP_ERR_INVALID_STATE) {
+    log_e("esp_vfs_fat_register failed 0x(%x): SD is registered.", err);
+    return false;
+  } else if (err != ESP_OK) {
+    log_e("esp_vfs_fat_register failed 0x(%x)", err);
+    return false;
+  }
+
+  FRESULT res = f_mount(fs, drv, 1);
+  if (res != FR_OK) {
+    log_e("f_mount failed: %s", fferr2str[res]);
+    if (res == 13 && format_if_empty) {
+      BYTE *work = (BYTE *)malloc(sizeof(BYTE) * FF_MAX_SS);
+      if (!work) {
+        log_e("alloc for f_mkfs failed");
         return false;
-    } else if (err != ESP_OK) {
-        log_e("esp_vfs_fat_register failed 0x(%x)", err);
+      }
+      //FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len);
+      const MKFS_PARM opt = {(BYTE)FM_ANY, 0, 0, 0, 0};
+      res = f_mkfs(drv, &opt, work, sizeof(BYTE) * FF_MAX_SS);
+      free(work);
+      if (res != FR_OK) {
+        log_e("f_mkfs failed: %s", fferr2str[res]);
+        esp_vfs_fat_unregister_path(path);
         return false;
-    }
-
-    FRESULT res = f_mount(fs, drv, 1);
-    if (res != FR_OK) {
-        log_e("f_mount failed 0x(%x)", res);
+      }
+      res = f_mount(fs, drv, 1);
+      if (res != FR_OK) {
+        log_e("f_mount failed: %s", fferr2str[res]);
         esp_vfs_fat_unregister_path(path);
         return false;
+      }
+    } else {
+      esp_vfs_fat_unregister_path(path);
+      return false;
     }
-    AcquireSPI lock(card);
-    card->sectors = sdGetSectorsCount(pdrv);
-    return true;
+  }
+  AcquireSPI lock(card);
+  card->sectors = sdGetSectorsCount(pdrv);
+  return true;
 }
 
-uint32_t sdcard_num_sectors(uint8_t pdrv)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    if(pdrv >= FF_VOLUMES || card == NULL){
-        return 0;
-    }
-    return card->sectors;
+uint32_t sdcard_num_sectors(uint8_t pdrv) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  if (pdrv >= FF_VOLUMES || card == NULL) {
+    return 0;
+  }
+  return card->sectors;
 }
 
-uint32_t sdcard_sector_size(uint8_t pdrv)
-{
-    if(pdrv >= FF_VOLUMES || s_cards[pdrv] == NULL){
-        return 0;
-    }
-    return 512;
+uint32_t sdcard_sector_size(uint8_t pdrv) {
+  if (pdrv >= FF_VOLUMES || s_cards[pdrv] == NULL) {
+    return 0;
+  }
+  return 512;
 }
 
-sdcard_type_t sdcard_type(uint8_t pdrv)
-{
-    ardu_sdcard_t * card = s_cards[pdrv];
-    if(pdrv >= FF_VOLUMES || card == NULL){
-        return CARD_NONE;
-    }
-    return card->type;
+sdcard_type_t sdcard_type(uint8_t pdrv) {
+  ardu_sdcard_t *card = s_cards[pdrv];
+  if (pdrv >= FF_VOLUMES || card == NULL) {
+    return CARD_NONE;
+  }
+  return card->type;
 }
diff --git a/libraries/SD/src/sd_diskio.h b/libraries/SD/src/sd_diskio.h
index 143be683e63..762cb6ed19a 100644
--- a/libraries/SD/src/sd_diskio.h
+++ b/libraries/SD/src/sd_diskio.h
@@ -17,15 +17,18 @@
 #include "Arduino.h"
 #include "SPI.h"
 #include "sd_defines.h"
+// #include "diskio.h"
 
-uint8_t sdcard_init(uint8_t cs, SPIClass * spi, int hz);
+uint8_t sdcard_init(uint8_t cs, SPIClass *spi, int hz);
 uint8_t sdcard_uninit(uint8_t pdrv);
 
-bool sdcard_mount(uint8_t pdrv, const char* path, uint8_t max_files);
+bool sdcard_mount(uint8_t pdrv, const char *path, uint8_t max_files, bool format_if_empty);
 uint8_t sdcard_unmount(uint8_t pdrv);
 
 sdcard_type_t sdcard_type(uint8_t pdrv);
 uint32_t sdcard_num_sectors(uint8_t pdrv);
 uint32_t sdcard_sector_size(uint8_t pdrv);
+bool sd_read_raw(uint8_t pdrv, uint8_t *buffer, uint32_t sector);
+bool sd_write_raw(uint8_t pdrv, uint8_t *buffer, uint32_t sector);
 
 #endif /* _SD_DISKIO_H_ */
diff --git a/libraries/SD/src/sd_diskio_crc.c b/libraries/SD/src/sd_diskio_crc.c
index 0372df82d09..9c839a58300 100644
--- a/libraries/SD/src/sd_diskio_crc.c
+++ b/libraries/SD/src/sd_diskio_crc.c
@@ -14,90 +14,48 @@
  * limitations under the License.
  */
 
-const char m_CRC7Table[] = {
-    0x00, 0x09, 0x12, 0x1B, 0x24, 0x2D, 0x36, 0x3F,
-    0x48, 0x41, 0x5A, 0x53, 0x6C, 0x65, 0x7E, 0x77,
-    0x19, 0x10, 0x0B, 0x02, 0x3D, 0x34, 0x2F, 0x26,
-    0x51, 0x58, 0x43, 0x4A, 0x75, 0x7C, 0x67, 0x6E,
-    0x32, 0x3B, 0x20, 0x29, 0x16, 0x1F, 0x04, 0x0D,
-    0x7A, 0x73, 0x68, 0x61, 0x5E, 0x57, 0x4C, 0x45,
-    0x2B, 0x22, 0x39, 0x30, 0x0F, 0x06, 0x1D, 0x14,
-    0x63, 0x6A, 0x71, 0x78, 0x47, 0x4E, 0x55, 0x5C,
-    0x64, 0x6D, 0x76, 0x7F, 0x40, 0x49, 0x52, 0x5B,
-    0x2C, 0x25, 0x3E, 0x37, 0x08, 0x01, 0x1A, 0x13,
-    0x7D, 0x74, 0x6F, 0x66, 0x59, 0x50, 0x4B, 0x42,
-    0x35, 0x3C, 0x27, 0x2E, 0x11, 0x18, 0x03, 0x0A,
-    0x56, 0x5F, 0x44, 0x4D, 0x72, 0x7B, 0x60, 0x69,
-    0x1E, 0x17, 0x0C, 0x05, 0x3A, 0x33, 0x28, 0x21,
-    0x4F, 0x46, 0x5D, 0x54, 0x6B, 0x62, 0x79, 0x70,
-    0x07, 0x0E, 0x15, 0x1C, 0x23, 0x2A, 0x31, 0x38,
-    0x41, 0x48, 0x53, 0x5A, 0x65, 0x6C, 0x77, 0x7E,
-    0x09, 0x00, 0x1B, 0x12, 0x2D, 0x24, 0x3F, 0x36,
-    0x58, 0x51, 0x4A, 0x43, 0x7C, 0x75, 0x6E, 0x67,
-    0x10, 0x19, 0x02, 0x0B, 0x34, 0x3D, 0x26, 0x2F,
-    0x73, 0x7A, 0x61, 0x68, 0x57, 0x5E, 0x45, 0x4C,
-    0x3B, 0x32, 0x29, 0x20, 0x1F, 0x16, 0x0D, 0x04,
-    0x6A, 0x63, 0x78, 0x71, 0x4E, 0x47, 0x5C, 0x55,
-    0x22, 0x2B, 0x30, 0x39, 0x06, 0x0F, 0x14, 0x1D,
-    0x25, 0x2C, 0x37, 0x3E, 0x01, 0x08, 0x13, 0x1A,
-    0x6D, 0x64, 0x7F, 0x76, 0x49, 0x40, 0x5B, 0x52,
-    0x3C, 0x35, 0x2E, 0x27, 0x18, 0x11, 0x0A, 0x03,
-    0x74, 0x7D, 0x66, 0x6F, 0x50, 0x59, 0x42, 0x4B,
-    0x17, 0x1E, 0x05, 0x0C, 0x33, 0x3A, 0x21, 0x28,
-    0x5F, 0x56, 0x4D, 0x44, 0x7B, 0x72, 0x69, 0x60,
-    0x0E, 0x07, 0x1C, 0x15, 0x2A, 0x23, 0x38, 0x31,
-    0x46, 0x4F, 0x54, 0x5D, 0x62, 0x6B, 0x70, 0x79
-};
+const char m_CRC7Table[] = {0x00, 0x09, 0x12, 0x1B, 0x24, 0x2D, 0x36, 0x3F, 0x48, 0x41, 0x5A, 0x53, 0x6C, 0x65, 0x7E, 0x77, 0x19, 0x10, 0x0B, 0x02, 0x3D, 0x34,
+                            0x2F, 0x26, 0x51, 0x58, 0x43, 0x4A, 0x75, 0x7C, 0x67, 0x6E, 0x32, 0x3B, 0x20, 0x29, 0x16, 0x1F, 0x04, 0x0D, 0x7A, 0x73, 0x68, 0x61,
+                            0x5E, 0x57, 0x4C, 0x45, 0x2B, 0x22, 0x39, 0x30, 0x0F, 0x06, 0x1D, 0x14, 0x63, 0x6A, 0x71, 0x78, 0x47, 0x4E, 0x55, 0x5C, 0x64, 0x6D,
+                            0x76, 0x7F, 0x40, 0x49, 0x52, 0x5B, 0x2C, 0x25, 0x3E, 0x37, 0x08, 0x01, 0x1A, 0x13, 0x7D, 0x74, 0x6F, 0x66, 0x59, 0x50, 0x4B, 0x42,
+                            0x35, 0x3C, 0x27, 0x2E, 0x11, 0x18, 0x03, 0x0A, 0x56, 0x5F, 0x44, 0x4D, 0x72, 0x7B, 0x60, 0x69, 0x1E, 0x17, 0x0C, 0x05, 0x3A, 0x33,
+                            0x28, 0x21, 0x4F, 0x46, 0x5D, 0x54, 0x6B, 0x62, 0x79, 0x70, 0x07, 0x0E, 0x15, 0x1C, 0x23, 0x2A, 0x31, 0x38, 0x41, 0x48, 0x53, 0x5A,
+                            0x65, 0x6C, 0x77, 0x7E, 0x09, 0x00, 0x1B, 0x12, 0x2D, 0x24, 0x3F, 0x36, 0x58, 0x51, 0x4A, 0x43, 0x7C, 0x75, 0x6E, 0x67, 0x10, 0x19,
+                            0x02, 0x0B, 0x34, 0x3D, 0x26, 0x2F, 0x73, 0x7A, 0x61, 0x68, 0x57, 0x5E, 0x45, 0x4C, 0x3B, 0x32, 0x29, 0x20, 0x1F, 0x16, 0x0D, 0x04,
+                            0x6A, 0x63, 0x78, 0x71, 0x4E, 0x47, 0x5C, 0x55, 0x22, 0x2B, 0x30, 0x39, 0x06, 0x0F, 0x14, 0x1D, 0x25, 0x2C, 0x37, 0x3E, 0x01, 0x08,
+                            0x13, 0x1A, 0x6D, 0x64, 0x7F, 0x76, 0x49, 0x40, 0x5B, 0x52, 0x3C, 0x35, 0x2E, 0x27, 0x18, 0x11, 0x0A, 0x03, 0x74, 0x7D, 0x66, 0x6F,
+                            0x50, 0x59, 0x42, 0x4B, 0x17, 0x1E, 0x05, 0x0C, 0x33, 0x3A, 0x21, 0x28, 0x5F, 0x56, 0x4D, 0x44, 0x7B, 0x72, 0x69, 0x60, 0x0E, 0x07,
+                            0x1C, 0x15, 0x2A, 0x23, 0x38, 0x31, 0x46, 0x4F, 0x54, 0x5D, 0x62, 0x6B, 0x70, 0x79};
 
-char CRC7(const char* data, int length)
-{
-    char crc = 0;
-    for (int i = 0; i < length; i++) {
-        crc = m_CRC7Table[(crc << 1) ^ data[i]];
-    }
-    return crc;
+char CRC7(const char *data, int length) {
+  char crc = 0;
+  for (int i = 0; i < length; i++) {
+    crc = m_CRC7Table[(crc << 1) ^ data[i]];
+  }
+  return crc;
 }
 
 const unsigned short m_CRC16Table[256] = {
-    0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
-    0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
-    0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
-    0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
-    0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
-    0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
-    0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
-    0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
-    0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
-    0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
-    0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
-    0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
-    0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
-    0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
-    0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
-    0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
-    0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
-    0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
-    0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
-    0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
-    0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
-    0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
-    0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
-    0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
-    0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
-    0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
-    0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
-    0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
-    0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
-    0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
-    0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
-    0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
+  0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, 0x1231, 0x0210, 0x3273,
+  0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6, 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE, 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7,
+  0x44A4, 0x5485, 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D, 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4, 0xB75B,
+  0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC, 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823, 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF,
+  0x8948, 0x9969, 0xA90A, 0xB92B, 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12, 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B,
+  0xAB1A, 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41, 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49, 0x7E97, 0x6EB6,
+  0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70, 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78, 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C,
+  0xC12D, 0xF14E, 0xE16F, 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067, 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
+  0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256, 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D, 0x34E2, 0x24C3, 0x14A0,
+  0x0481, 0x7466, 0x6447, 0x5424, 0x4405, 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C, 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676,
+  0x4615, 0x5634, 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB, 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3, 0xCB7D,
+  0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A, 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92, 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D,
+  0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9, 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1, 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9,
+  0x9FF8, 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
 };
 
-unsigned short CRC16(const char* data, int length)
-{
-    unsigned short crc = 0;
-    for (int i = 0; i < length; i++) {
-        crc = (crc << 8) ^ m_CRC16Table[((crc >> 8) ^ data[i]) & 0x00FF];
-    }
-    return crc;
+unsigned short CRC16(const char *data, int length) {
+  unsigned short crc = 0;
+  for (int i = 0; i < length; i++) {
+    crc = (crc << 8) ^ m_CRC16Table[((crc >> 8) ^ data[i]) & 0x00FF];
+  }
+  return crc;
 }
diff --git a/libraries/SD_MMC/README.md b/libraries/SD_MMC/README.md
new file mode 100644
index 00000000000..a41295c1228
--- /dev/null
+++ b/libraries/SD_MMC/README.md
@@ -0,0 +1,112 @@
+# SD_MMC library
+
+This library provides the integration of ESP32 and ESP32-S3 with SD (Secure Digital) and MMC (Multi Media Card) cards using a built-in SDMMC module.
+
+Please note that SD_MMC is only available for ESP32 and ESP32-S3. For other SoCs please use the SD library based on SPI.
+
+## Wiring:
+
+![SD cards pins](https://upload.wikimedia.org/wikipedia/commons/thumb/a/ab/MMC-SD-miniSD-microSD-Color-Numbers-Names.gif/330px-MMC-SD-miniSD-microSD-Color-Numbers-Names.gif)
+
+Image source: [Wikipedia](https://upload.wikimedia.org/wikipedia/commons/thumb/a/ab/MMC-SD-miniSD-microSD-Color-Numbers-Names.gif/330px-MMC-SD-miniSD-microSD-Color-Numbers-Names.gif)
+
+![SD and MMC pins](https://upload.wikimedia.org/wikipedia/commons/f/ff/15-04-29-MMC-Karte-dscf4734-e.jpg)
+
+Image source: [Wikipedia](https://commons.wikimedia.org/wiki/File:15-04-29-MMC-Karte-dscf4734-e.jpg)
+
+pin number (refer to the picture) | micro SD - SD mode | micro SD - SPI mode | mini SD - SD mode | mini SD - SPI mode | SD - SD mode | SD - SPI mode | MMC (MMC3) - MMC mode | MMC (MMC3) - SPI mode | MMCplus / MMCmobile (MMC4) - MMC mode | MMCplus / MMCmobile (MMC4) - SPI mode
+----------------------------------|--------------------|---------------------|-------------------|--------------------|--------------|---------------|-----------------------|-----------------------|-----------------------------------------|--------------------------------------
+1                                 | D2                 | not used            | D3                | CS                 | D3           | CS            | RES                   | CS                    | D3                                    | CS
+2                                 | D3                 | CS                  | CMD               | DI                 | CMD          | DI            | CMD                   | DI                    | CMD                                   | DI
+3                                 | CMD                | DI                  | VSS1 (GND)        | VSS1 (GND)         | VSS1 (GND)   | VSS1 (GND)    | VSS1 (GND)            | VSS1 (GND)            | VSS1 (GND)                            | VSS1 (GND)
+4                                 | VDD (3.3V)         | VDD (3.3V)          | VDD (3.3V)        | VDD (3.3V)         | VDD (3.3V)   | VDD (3.3V)    | VDD (3.3V)            | VDD (3.3V)            | VDD (3.3V)                            | VDD (3.3V)
+5                                 | CLK                | SCLK                | CLK               | SCLK               | CLK          | SCLK          | CLK                   | SCLK                  | CLK                                   | SCLK
+6                                 | VSS (GND)          | VSS (GND)           | VSS2 (GND)        | VSS2 (GND)         | VSS2 (GND)   | VSS2 (GND)    | VSS2 (GND)            | VSS2 (GND)            | VSS2 (GND)                            | VSS2 (GND)
+7                                 | D0                 | DO                  | D0                | DO                 | D0           | DO            | DAT                   | DO                    | D0                                    | DO
+8                                 | D1                 | not used            | D1                | not used           | D1           | not used      | -                     | -                     | D1                                    | not used
+9                                 | -                  | -                   | D2                | not used           | D2           | not used      | -                     | -                     | D2                                    | not used
+10                                | -                  | -                   | For future use    | For future use     | -            | -             | -                     | -                     | D3                                    | not used
+11                                | -                  | -                   | For future use    | For future use     | -            | -             | -                     | -                     | D4                                    | not used
+12                                | -                  | -                   | -                 | -                  | -            | -             | -                     | -                     | D5                                    | not used
+13                                | -                  | -                   |  -                | -                  | -            | -             | -                     | -                     | D6                                    | not used
+
+### Pin assignments for ESP32
+
+On ESP32, SD_MMC peripheral is connected to specific GPIO pins and cannot be changed (rerouted). Please see the table below for the pin connections.
+
+When using an ESP-WROVER-KIT board, this example runs without any extra modifications required. Only an SD card needs to be inserted into the slot.
+
+ESP32 pin     | SD card pin | Notes
+--------------|-------------|------------
+GPIO14 (MTMS) | CLK         | 10k pullup in SD mode
+GPIO15 (MTDO) | CMD         | 10k pullup in SD mode
+GPIO2         | D0          | 10k pullup in SD mode, pull low to go into download mode (see Note about GPIO2 below!)
+GPIO4         | D1          | not used in 1-line SD mode; 10k pullup in 4-line SD mode
+GPIO12 (MTDI) | D2          | not used in 1-line SD mode; 10k pullup in 4-line SD mode (see Note about GPIO12 below!)
+GPIO13 (MTCK) | D3          | not used in 1-line SD mode, but card's D3 pin must have a 10k pullup
+
+
+### Pin assignments for ESP32-S3
+
+On ESP32-S3, SDMMC peripheral is connected to GPIO pins using GPIO matrix. This allows arbitrary GPIOs to be used to connect an SD card or MMC. The GPIOs can be configured with the following commands:
+```
+  setPins(int clk, int cmd, int d0))
+  setPins(int clk, int cmd, int d0, int d1, int d2, int d3))
+```
+
+The table below lists the default pin assignments.
+
+When using an ESP32-S3-USB-OTG board, this example runs without any extra modifications required. Only an SD card needs to be inserted into the slot.
+
+ESP32-S3 pin  | SD card pin | Notes
+--------------|-------------|------------
+GPIO36        | CLK         | 10k pullup
+GPIO35        | CMD         | 10k pullup
+GPIO37        | D0          | 10k pullup
+GPIO38        | D1          | not used in 1-line SD mode; 10k pullup in 4-line mode
+GPIO33        | D2          | not used in 1-line SD mode; 10k pullup in 4-line mode
+GPIO34        | D3          | not used in 1-line SD mode, but card's D3 pin must have a 10k pullup
+
+Warning: ESP32-S3-WROOM-2 is using most of the default GPIOs (33-37) to interface with on-board OPI flash. If the SD_MMC is initialized with default pins it will result in rebooting loop - please reassign the pins elsewhere using the mentioned command `setPins`.
+
+> **Note:**  ESP32-S3-DevKitC-1 v1.1 does NOT have GPIOs 33 and 34 broken out, so it will be necessary to change at least the pin for D2 and D3.
+
+### 4-line and 1-line SD modes
+
+By default, this library uses 4-bit line mode, utilizing 6 pins: CLK, CMD, D0 - D3 and 2 power lines (3.3V and GND). It is possible to use 1-bit line mode (CLK, CMD, D0, 3.3V, GND) by passing the second argument `mode1bit==true`:
+```
+  SD_MMC.begin("/sdcard", true);
+```
+
+> **Note:**  Even if card's D3 line is not connected to the ESP chip, it still has to be pulled up, otherwise the card will go into SPI protocol mode.
+
+### Note about GPIO2 (ESP32 only)
+
+GPIO2 pin is used as a bootstrapping pin, and should be low to enter UART download mode. One way to do this is to connect GPIO0 and GPIO2 using a jumper, and then the auto-reset circuit on most development boards will pull GPIO2 low along with GPIO0, when entering download mode.
+
+- Some boards have pulldown and/or LED on GPIO2. LED is usually ok, but pulldown will interfere with D0 signals and must be removed. Check the schematic of your development board for anything connected to GPIO2.
+
+### Note about GPIO12 (ESP32 only)
+
+GPIO12 is used as a bootstrapping pin to select output voltage of an internal regulator which powers the flash chip (VDD_SDIO). This pin has an internal pulldown so if left unconnected it will read low at reset (selecting default 3.3V operation). When adding a pullup to this pin for SD card operation, consider the following:
+
+## FAQ:
+
+#### Do I need any additional modules, like the Arduino SD module?
+
+No, just wire your SD card directly to ESP32.
+
+Tip: If you are using a microSD card and have a spare adapter to full-sized SD, you can solder Dupont pins on the adapter.
+
+
+#### What is the difference between SD and SD_MMC libraries?
+
+SD runs on SPI, and SD_MMC uses the SDMMC hardware bus on the ESP32.
+The SPI uses 4 communication pins + 2 power connections and operates on up to 80 MHz. The SPI option offers flexibility on pin connection because the data connections can be routed through GPIO matrix to any data pin.
+SD-SPI speed is approximately half of the SD-MMC even when used on 1-bit line.
+You can read more about SD SPI in the [documentation](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/sdspi_host.html)
+
+SD_MMC is supported only by ESP32 and ESP32-S3 and can be connected only to dedicated pins. SD_MMC allows to use of 1, 4 or 8 data pins + 2 additional communication pins and 2 power pins. The data pins need to be pulled up externally.
+You can read more about SD_MMC in the [documentation](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/peripherals/sdmmc_host.html)
+1-bit: SD_MMC_ speed is approximately two-times faster than SPI mode
+4-bit: SD_MMC speed is approximately three-times faster than SPI mode.
diff --git a/libraries/SD_MMC/examples/SD2USBMSC/SD2USBMSC.ino b/libraries/SD_MMC/examples/SD2USBMSC/SD2USBMSC.ino
new file mode 100644
index 00000000000..d379e409960
--- /dev/null
+++ b/libraries/SD_MMC/examples/SD2USBMSC/SD2USBMSC.ino
@@ -0,0 +1,102 @@
+#if !SOC_USB_OTG_SUPPORTED || ARDUINO_USB_MODE
+#error Device does not support USB_OTG or native USB CDC/JTAG is selected
+#endif
+
+#include <USB.h>
+#include <USBMSC.h>
+#include <SD_MMC.h>
+
+// USB Mass Storage Class (MSC) object
+USBMSC msc;
+
+int clk = 36;
+int cmd = 35;
+int d0 = 37;
+int d1 = 38;
+int d2 = 33;
+int d3 = 34;
+bool onebit = true;  // set to false for 4-bit. 1-bit will ignore the d1-d3 pins (but d3 must be pulled high)
+
+static int32_t onWrite(uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize) {
+  uint32_t secSize = SD_MMC.sectorSize();
+  if (!secSize) {
+    return false;  // disk error
+  }
+  log_v("Write lba: %ld\toffset: %ld\tbufsize: %ld", lba, offset, bufsize);
+  for (int x = 0; x < bufsize / secSize; x++) {
+    uint8_t blkbuffer[secSize];
+    memcpy(blkbuffer, (uint8_t *)buffer + secSize * x, secSize);
+    if (!SD_MMC.writeRAW(blkbuffer, lba + x)) {
+      return false;
+    }
+  }
+  return bufsize;
+}
+
+static int32_t onRead(uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize) {
+  uint32_t secSize = SD_MMC.sectorSize();
+  if (!secSize) {
+    return false;  // disk error
+  }
+  log_v("Read lba: %ld\toffset: %ld\tbufsize: %ld\tsector: %lu", lba, offset, bufsize, secSize);
+  for (int x = 0; x < bufsize / secSize; x++) {
+    if (!SD_MMC.readRAW((uint8_t *)buffer + (x * secSize), lba + x)) {
+      return false;  // outside of volume boundary
+    }
+  }
+  return bufsize;
+}
+
+static bool onStartStop(uint8_t power_condition, bool start, bool load_eject) {
+  log_i("Start/Stop power: %u\tstart: %d\teject: %d", power_condition, start, load_eject);
+  return true;
+}
+
+static void usbEventCallback(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == ARDUINO_USB_EVENTS) {
+    arduino_usb_event_data_t *data = (arduino_usb_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_STARTED_EVENT: Serial.println("USB PLUGGED"); break;
+      case ARDUINO_USB_STOPPED_EVENT: Serial.println("USB UNPLUGGED"); break;
+      case ARDUINO_USB_SUSPEND_EVENT: Serial.printf("USB SUSPENDED: remote_wakeup_en: %u\n", data->suspend.remote_wakeup_en); break;
+      case ARDUINO_USB_RESUME_EVENT:  Serial.println("USB RESUMED"); break;
+
+      default: break;
+    }
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Starting Serial");
+
+  Serial.println("Mounting SDcard");
+  SD_MMC.setPins(clk, cmd, d0, d1, d2, d3);
+  if (!SD_MMC.begin("/sdcard", onebit)) {
+    Serial.println("Mount Failed");
+    return;
+  }
+
+  Serial.println("Initializing MSC");
+  // Initialize USB metadata and callbacks for MSC (Mass Storage Class)
+  msc.vendorID("ESP32");
+  msc.productID("USB_MSC");
+  msc.productRevision("1.0");
+  msc.onRead(onRead);
+  msc.onWrite(onWrite);
+  msc.onStartStop(onStartStop);
+  msc.mediaPresent(true);
+  msc.begin(SD_MMC.numSectors(), SD_MMC.sectorSize());
+
+  Serial.println("Initializing USB");
+
+  USB.begin();
+  USB.onEvent(usbEventCallback);
+
+  Serial.printf("Card Size: %lluMB\n", SD_MMC.totalBytes() / 1024 / 1024);
+  Serial.printf("Sector: %d\tCount: %d\n", SD_MMC.sectorSize(), SD_MMC.numSectors());
+}
+
+void loop() {
+  delay(-1);
+}
diff --git a/libraries/SD_MMC/examples/SD2USBMSC/ci.json b/libraries/SD_MMC/examples/SD2USBMSC/ci.json
new file mode 100644
index 00000000000..125eed2e476
--- /dev/null
+++ b/libraries/SD_MMC/examples/SD2USBMSC/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_SOC_SDMMC_HOST_SUPPORTED=y",
+    "CONFIG_TINYUSB_MSC_ENABLED=y"
+  ]
+}
diff --git a/libraries/SD_MMC/examples/SDMMC_Test/SDMMC_Test.ino b/libraries/SD_MMC/examples/SDMMC_Test/SDMMC_Test.ino
index b9e872850a0..e03f5ceb25e 100644
--- a/libraries/SD_MMC/examples/SDMMC_Test/SDMMC_Test.ino
+++ b/libraries/SD_MMC/examples/SDMMC_Test/SDMMC_Test.ino
@@ -1,5 +1,29 @@
 /*
- * Connect the SD card to the following pins:
+ * pin 1 - D2                |  Micro SD card     |
+ * pin 2 - D3                |                   /
+ * pin 3 - CMD               |                  |__
+ * pin 4 - VDD (3.3V)        |                    |
+ * pin 5 - CLK               | 8 7 6 5 4 3 2 1   /
+ * pin 6 - VSS (GND)         | ▄ ▄ ▄ ▄ ▄ ▄ ▄ ▄  /
+ * pin 7 - D0                | ▀ ▀ █ ▀ █ ▀ ▀ ▀ |
+ * pin 8 - D1                |_________________|
+ *                             ║ ║ ║ ║ ║ ║ ║ ║
+ *                     ╔═══════╝ ║ ║ ║ ║ ║ ║ ╚═════════╗
+ *                     ║         ║ ║ ║ ║ ║ ╚══════╗    ║
+ *                     ║   ╔═════╝ ║ ║ ║ ╚═════╗  ║    ║
+ * Connections for     ║   ║   ╔═══╩═║═║═══╗   ║  ║    ║
+ * full-sized          ║   ║   ║   ╔═╝ ║   ║   ║  ║    ║
+ * SD card             ║   ║   ║   ║   ║   ║   ║  ║    ║
+ * ESP32-P4 Func EV | 40  39  GND  43 3V3 GND  44 43  42  | SLOT 0 (IO_MUX)
+ * ESP32-S3 DevKit  | 21  47  GND  39 3V3 GND  40 41  42  |
+ * ESP32-S3-USB-OTG | 38  37  GND  36 3V3 GND  35 34  33  |
+ * ESP32            |  4   2  GND  14 3V3 GND  15 13  12  |
+ * Pin name         | D1  D0  VSS CLK VDD VSS CMD D3  D2  |
+ * SD pin number    |  8   7   6   5   4   3   2   1   9 /
+ *                  |                                  █/
+ *                  |__▍___▊___█___█___█___█___█___█___/
+ * WARNING: ALL data pins must be pulled up to 3.3V with an external 10k Ohm resistor!
+ * Note to ESP32 pin 2 (D0): Add a 1K Ohm pull-up resistor to 3.3V after flashing
  *
  * SD Card | ESP32
  *    D2       12
@@ -11,208 +35,237 @@
  *    VSS      GND
  *    D0       2  (add 1K pull up after flashing)
  *    D1       4
+ *
+ *    For more info see file README.md in this library or on URL:
+ *    https://github.com/espressif/arduino-esp32/tree/master/libraries/SD_MMC
  */
 
 #include "FS.h"
 #include "SD_MMC.h"
 
-void listDir(fs::FS &fs, const char * dirname, uint8_t levels){
-    Serial.printf("Listing directory: %s\n", dirname);
+#ifdef CONFIG_IDF_TARGET_ESP32S3
+// Default pins for ESP-S3
+// Warning: ESP32-S3-WROOM-2 is using most of the default GPIOs (33-37) to interface with on-board OPI flash.
+//   If the SD_MMC is initialized with default pins it will result in rebooting loop - please
+//   reassign the pins elsewhere using the mentioned command `setPins`.
+// Note: ESP32-S3-WROOM-1 does not have GPIO 33 and 34 broken out.
+// Note: if it's ok to use default pins, you do not need to call the setPins
+int clk = 36;
+int cmd = 35;
+int d0 = 37;
+int d1 = 38;
+int d2 = 33;
+int d3 = 39;  // GPIO 34 is not broken-out on ESP32-S3-DevKitC-1 v1.1
+#endif
 
-    File root = fs.open(dirname);
-    if(!root){
-        Serial.println("Failed to open directory");
-        return;
-    }
-    if(!root.isDirectory()){
-        Serial.println("Not a directory");
-        return;
-    }
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\n", dirname);
 
-    File file = root.openNextFile();
-    while(file){
-        if(file.isDirectory()){
-            Serial.print("  DIR : ");
-            Serial.println(file.name());
-            if(levels){
-                listDir(fs, file.name(), levels -1);
-            }
-        } else {
-            Serial.print("  FILE: ");
-            Serial.print(file.name());
-            Serial.print("  SIZE: ");
-            Serial.println(file.size());
-        }
-        file = root.openNextFile();
-    }
-}
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("Failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println("Not a directory");
+    return;
+  }
 
-void createDir(fs::FS &fs, const char * path){
-    Serial.printf("Creating Dir: %s\n", path);
-    if(fs.mkdir(path)){
-        Serial.println("Dir created");
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.println(file.name());
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
     } else {
-        Serial.println("mkdir failed");
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("  SIZE: ");
+      Serial.println(file.size());
     }
+    file = root.openNextFile();
+  }
 }
 
-void removeDir(fs::FS &fs, const char * path){
-    Serial.printf("Removing Dir: %s\n", path);
-    if(fs.rmdir(path)){
-        Serial.println("Dir removed");
-    } else {
-        Serial.println("rmdir failed");
-    }
+void createDir(fs::FS &fs, const char *path) {
+  Serial.printf("Creating Dir: %s\n", path);
+  if (fs.mkdir(path)) {
+    Serial.println("Dir created");
+  } else {
+    Serial.println("mkdir failed");
+  }
 }
 
-void readFile(fs::FS &fs, const char * path){
-    Serial.printf("Reading file: %s\n", path);
+void removeDir(fs::FS &fs, const char *path) {
+  Serial.printf("Removing Dir: %s\n", path);
+  if (fs.rmdir(path)) {
+    Serial.println("Dir removed");
+  } else {
+    Serial.println("rmdir failed");
+  }
+}
 
-    File file = fs.open(path);
-    if(!file){
-        Serial.println("Failed to open file for reading");
-        return;
-    }
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\n", path);
 
-    Serial.print("Read from file: ");
-    while(file.available()){
-        Serial.write(file.read());
-    }
+  File file = fs.open(path);
+  if (!file) {
+    Serial.println("Failed to open file for reading");
+    return;
+  }
+
+  Serial.print("Read from file: ");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
 }
 
-void writeFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Writing file: %s\n", path);
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\n", path);
 
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("Failed to open file for writing");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("File written");
-    } else {
-        Serial.println("Write failed");
-    }
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("File written");
+  } else {
+    Serial.println("Write failed");
+  }
 }
 
-void appendFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Appending to file: %s\n", path);
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\n", path);
 
-    File file = fs.open(path, FILE_APPEND);
-    if(!file){
-        Serial.println("Failed to open file for appending");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("Message appended");
-    } else {
-        Serial.println("Append failed");
-    }
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("Failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("Message appended");
+  } else {
+    Serial.println("Append failed");
+  }
 }
 
-void renameFile(fs::FS &fs, const char * path1, const char * path2){
-    Serial.printf("Renaming file %s to %s\n", path1, path2);
-    if (fs.rename(path1, path2)) {
-        Serial.println("File renamed");
-    } else {
-        Serial.println("Rename failed");
-    }
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("File renamed");
+  } else {
+    Serial.println("Rename failed");
+  }
 }
 
-void deleteFile(fs::FS &fs, const char * path){
-    Serial.printf("Deleting file: %s\n", path);
-    if(fs.remove(path)){
-        Serial.println("File deleted");
-    } else {
-        Serial.println("Delete failed");
-    }
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\n", path);
+  if (fs.remove(path)) {
+    Serial.println("File deleted");
+  } else {
+    Serial.println("Delete failed");
+  }
 }
 
-void testFileIO(fs::FS &fs, const char * path){
-    File file = fs.open(path);
-    static uint8_t buf[512];
-    size_t len = 0;
-    uint32_t start = millis();
-    uint32_t end = start;
-    if(file){
-        len = file.size();
-        size_t flen = len;
-        start = millis();
-        while(len){
-            size_t toRead = len;
-            if(toRead > 512){
-                toRead = 512;
-            }
-            file.read(buf, toRead);
-            len -= toRead;
-        }
-        end = millis() - start;
-        Serial.printf("%u bytes read for %u ms\n", flen, end);
-        file.close();
-    } else {
-        Serial.println("Failed to open file for reading");
-    }
-
-
-    file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("Failed to open file for writing");
-        return;
-    }
-
-    size_t i;
+void testFileIO(fs::FS &fs, const char *path) {
+  File file = fs.open(path);
+  static uint8_t buf[512];
+  size_t len = 0;
+  uint32_t start = millis();
+  uint32_t end = start;
+  if (file) {
+    len = file.size();
+    size_t flen = len;
     start = millis();
-    for(i=0; i<2048; i++){
-        file.write(buf, 512);
+    while (len) {
+      size_t toRead = len;
+      if (toRead > 512) {
+        toRead = 512;
+      }
+      file.read(buf, toRead);
+      len -= toRead;
     }
     end = millis() - start;
-    Serial.printf("%u bytes written for %u ms\n", 2048 * 512, end);
+    Serial.printf("%u bytes read for %lu ms\n", flen, end);
     file.close();
+  } else {
+    Serial.println("Failed to open file for reading");
+  }
+
+  file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing");
+    return;
+  }
+
+  size_t i;
+  start = millis();
+  for (i = 0; i < 2048; i++) {
+    file.write(buf, 512);
+  }
+  end = millis() - start;
+  Serial.printf("%u bytes written for %lu ms\n", 2048 * 512, end);
+  file.close();
 }
 
-void setup(){
-    Serial.begin(115200);
-    if(!SD_MMC.begin()){
-        Serial.println("Card Mount Failed");
-        return;
-    }
-    uint8_t cardType = SD_MMC.cardType();
+void setup() {
+  Serial.begin(115200);
+  /*
+    // If you want to change the pin assignment or you get an error that some pins
+    // are not assigned on ESP32-S3/ESP32-P4 uncomment this block and the appropriate
+    // line depending if you want to use 1-bit or 4-bit line.
+    // Please note that ESP32 does not allow pin change and setPins() will always fail.
+    //if(! SD_MMC.setPins(clk, cmd, d0)){
+    //if(! SD_MMC.setPins(clk, cmd, d0, d1, d2, d3)){
+    //    Serial.println("Pin change failed!");
+    //    return;
+    //}
+  */
 
-    if(cardType == CARD_NONE){
-        Serial.println("No SD_MMC card attached");
-        return;
-    }
+  if (!SD_MMC.begin()) {
+    Serial.println("Card Mount Failed");
+    return;
+  }
+  uint8_t cardType = SD_MMC.cardType();
 
-    Serial.print("SD_MMC Card Type: ");
-    if(cardType == CARD_MMC){
-        Serial.println("MMC");
-    } else if(cardType == CARD_SD){
-        Serial.println("SDSC");
-    } else if(cardType == CARD_SDHC){
-        Serial.println("SDHC");
-    } else {
-        Serial.println("UNKNOWN");
-    }
+  if (cardType == CARD_NONE) {
+    Serial.println("No SD_MMC card attached");
+    return;
+  }
 
-    uint64_t cardSize = SD_MMC.cardSize() / (1024 * 1024);
-    Serial.printf("SD_MMC Card Size: %lluMB\n", cardSize);
-
-    listDir(SD_MMC, "/", 0);
-    createDir(SD_MMC, "/mydir");
-    listDir(SD_MMC, "/", 0);
-    removeDir(SD_MMC, "/mydir");
-    listDir(SD_MMC, "/", 2);
-    writeFile(SD_MMC, "/hello.txt", "Hello ");
-    appendFile(SD_MMC, "/hello.txt", "World!\n");
-    readFile(SD_MMC, "/hello.txt");
-    deleteFile(SD_MMC, "/foo.txt");
-    renameFile(SD_MMC, "/hello.txt", "/foo.txt");
-    readFile(SD_MMC, "/foo.txt");
-    testFileIO(SD_MMC, "/test.txt");
-    Serial.printf("Total space: %lluMB\n", SD_MMC.totalBytes() / (1024 * 1024));
-    Serial.printf("Used space: %lluMB\n", SD_MMC.usedBytes() / (1024 * 1024));
-}
+  Serial.print("SD_MMC Card Type: ");
+  if (cardType == CARD_MMC) {
+    Serial.println("MMC");
+  } else if (cardType == CARD_SD) {
+    Serial.println("SDSC");
+  } else if (cardType == CARD_SDHC) {
+    Serial.println("SDHC");
+  } else {
+    Serial.println("UNKNOWN");
+  }
 
-void loop(){
+  uint64_t cardSize = SD_MMC.cardSize() / (1024 * 1024);
+  Serial.printf("SD_MMC Card Size: %lluMB\n", cardSize);
+
+  listDir(SD_MMC, "/", 0);
+  createDir(SD_MMC, "/mydir");
+  listDir(SD_MMC, "/", 0);
+  removeDir(SD_MMC, "/mydir");
+  listDir(SD_MMC, "/", 2);
+  writeFile(SD_MMC, "/hello.txt", "Hello ");
+  appendFile(SD_MMC, "/hello.txt", "World!\n");
+  readFile(SD_MMC, "/hello.txt");
+  deleteFile(SD_MMC, "/foo.txt");
+  renameFile(SD_MMC, "/hello.txt", "/foo.txt");
+  readFile(SD_MMC, "/foo.txt");
+  testFileIO(SD_MMC, "/test.txt");
+  Serial.printf("Total space: %lluMB\n", SD_MMC.totalBytes() / (1024 * 1024));
+  Serial.printf("Used space: %lluMB\n", SD_MMC.usedBytes() / (1024 * 1024));
+}
 
+void loop() {
+  delay(10);
 }
diff --git a/libraries/SD_MMC/examples/SDMMC_Test/ci.json b/libraries/SD_MMC/examples/SDMMC_Test/ci.json
new file mode 100644
index 00000000000..a5221dae538
--- /dev/null
+++ b/libraries/SD_MMC/examples/SDMMC_Test/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_SDMMC_HOST_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/SD_MMC/examples/SDMMC_time/SDMMC_time.ino b/libraries/SD_MMC/examples/SDMMC_time/SDMMC_time.ino
index 43dad45427f..d1e933e4f4b 100644
--- a/libraries/SD_MMC/examples/SDMMC_time/SDMMC_time.ino
+++ b/libraries/SD_MMC/examples/SDMMC_time/SDMMC_time.ino
@@ -1,213 +1,280 @@
 /*
- * Connect the SD card to the following pins:
+ * pin 1 - D2                |  Micro SD card     |
+ * pin 2 - D3                |                   /
+ * pin 3 - CMD               |                  |__
+ * pin 4 - VDD (3.3V)        |                    |
+ * pin 5 - CLK               | 8 7 6 5 4 3 2 1   /
+ * pin 6 - VSS (GND)         | ▄ ▄ ▄ ▄ ▄ ▄ ▄ ▄  /
+ * pin 7 - D0                | ▀ ▀ █ ▀ █ ▀ ▀ ▀ |
+ * pin 8 - D1                |_________________|
+ *                             ║ ║ ║ ║ ║ ║ ║ ║
+ *                     ╔═══════╝ ║ ║ ║ ║ ║ ║ ╚═════════╗
+ *                     ║         ║ ║ ║ ║ ║ ╚══════╗    ║
+ *                     ║   ╔═════╝ ║ ║ ║ ╚═════╗  ║    ║
+ * Connections for     ║   ║   ╔═══╩═║═║═══╗   ║  ║    ║
+ * full-sized          ║   ║   ║   ╔═╝ ║   ║   ║  ║    ║
+ * SD card             ║   ║   ║   ║   ║   ║   ║  ║    ║
+ * ESP32-P4 Func EV | 40  39  GND  43 3V3 GND  44 43  42  | SLOT 0 (IO_MUX)
+ * ESP32-S3 DevKit  | 21  47  GND  39 3V3 GND  40 41  42  |
+ * ESP32-S3-USB-OTG | 38  37  GND  36 3V3 GND  35 34  33  |
+ * ESP32            |  4   2  GND  14 3V3 GND  15 13  12  |
+ * Pin name         | D1  D0  VSS CLK VDD VSS CMD D3  D2  |
+ * SD pin number    |  8   7   6   5   4   3   2   1   9 /
+ *                  |                                  █/
+ *                  |__▍___▊___█___█___█___█___█___█___/
+ * WARNING: ALL data pins must be pulled up to 3.3V with external 10k Ohm resistor!
+ * Note to ESP32 pin 2 (D0): Add 1K Ohm pull-up resistor to 3.3V after flashing
  *
- * SD Card | ESP32
- *    D2       -
- *    D3       SS
- *    CMD      MOSI
- *    VSS      GND
- *    VDD      3.3V
- *    CLK      SCK
- *    VSS      GND
- *    D0       MISO
- *    D1       -
+ * For more info see file README.md in this library or on URL:
+ * https://github.com/espressif/arduino-esp32/tree/master/libraries/SD_MMC
  */
 
 #include "FS.h"
 #include "SD_MMC.h"
 #include "SPI.h"
-#include <time.h> 
+#include <time.h>
 #include <WiFi.h>
 
-const char* ssid     = "your-ssid";
-const char* password = "your-password";
+const char *ssid = "your-ssid";
+const char *password = "your-password";
 
-long timezone = 1; 
+long timezone = 1;
 byte daysavetime = 1;
 
-void listDir(fs::FS &fs, const char * dirname, uint8_t levels){
-    Serial.printf("Listing directory: %s\n", dirname);
+// Default pins for ESP-S3
+// Warning: ESP32-S3-WROOM-2 is using most of the default SD_MMC GPIOs (33-37) to interface with on-board OPI flash.
+//   If the SD_MMC is initialized with default pins it will result in rebooting loop - please
+//   reassign the pins elsewhere using the mentioned command `setPins`.
+// Note: ESP32-S3-WROOM-1 does not have GPIO 33 and 34 broken out.
+// Note: The board ESP32-S3-USB-OTG has predefined default pins and the following definitions with the setPins() call will not be compiled.
+// Note: Pins in this definition block are ordered from top down in order in which they are on the full-sized SD card
+//   from left to right when facing the pins down (when connected to a breadboard)
 
-    File root = fs.open(dirname);
-    if(!root){
-        Serial.println("Failed to open directory");
-        return;
-    }
-    if(!root.isDirectory()){
-        Serial.println("Not a directory");
-        return;
-    }
+#if defined(SOC_SDMMC_USE_GPIO_MATRIX) && not defined(BOARD_HAS_SDMMC)
+int d1 = 21;  // SD pin 8 - Add a 10k Ohm pull-up resistor to 3.3V if using 4-bit mode (use_1_bit_mode = false)
+int d0 = 47;  // SD pin 7 - Add a 10k Ohm pull-up resistor to 3.3V
+//     GND pin - SD pin 6
+int clk = 39;  // SD pin 5 - Add a 10k Ohm pull-up resistor to 3.3V
+//    3.3V pin - SD pin 4
+//     GND pin - SD pin 3
+int cmd = 40;  // SD pin 2 - Add a 10k Ohm pull-up resistor to 3.3V
+int d3 = 41;   // SD pin 1 - Add a 10k Ohm pull-up resistor to 3.3V to card's pin even when using 1-bit mode
+int d2 = 42;   // SD pin 9 - Add a 10k Ohm pull-up resistor to 3.3V if using 4-bit mode (use_1_bit_mode = false)
+#endif
 
-    File file = root.openNextFile();
-    while(file){
-        if(file.isDirectory()){
-            Serial.print("  DIR : ");
-            Serial.print (file.name());
-            time_t t= file.getLastWrite();
-            struct tm * tmstruct = localtime(&t);
-            Serial.printf("  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct->tm_year)+1900,( tmstruct->tm_mon)+1, tmstruct->tm_mday,tmstruct->tm_hour , tmstruct->tm_min, tmstruct->tm_sec);
-            if(levels){
-                listDir(fs, file.name(), levels -1);
-            }
-        } else {
-            Serial.print("  FILE: ");
-            Serial.print(file.name());
-            Serial.print("  SIZE: ");
-            Serial.print(file.size());
-            time_t t= file.getLastWrite();
-            struct tm * tmstruct = localtime(&t);
-            Serial.printf("  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct->tm_year)+1900,( tmstruct->tm_mon)+1, tmstruct->tm_mday,tmstruct->tm_hour , tmstruct->tm_min, tmstruct->tm_sec);
-        }
-        file = root.openNextFile();
-    }
-}
+bool use_1_bit_mode = false;  // Change the value to `true` to use 1-bit mode instead of the 4-bit mode
 
-void createDir(fs::FS &fs, const char * path){
-    Serial.printf("Creating Dir: %s\n", path);
-    if(fs.mkdir(path)){
-        Serial.println("Dir created");
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\n", dirname);
+
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("Failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println("Not a directory");
+    return;
+  }
+
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.print(file.name());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
     } else {
-        Serial.println("mkdir failed");
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("  SIZE: ");
+      Serial.print(file.size());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
     }
+    file = root.openNextFile();
+  }
 }
 
-void removeDir(fs::FS &fs, const char * path){
-    Serial.printf("Removing Dir: %s\n", path);
-    if(fs.rmdir(path)){
-        Serial.println("Dir removed");
-    } else {
-        Serial.println("rmdir failed");
-    }
+void createDir(fs::FS &fs, const char *path) {
+  Serial.printf("Creating Dir: %s\n", path);
+  if (fs.mkdir(path)) {
+    Serial.println("Dir created");
+  } else {
+    Serial.println("mkdir failed");
+  }
 }
 
-void readFile(fs::FS &fs, const char * path){
-    Serial.printf("Reading file: %s\n", path);
+void removeDir(fs::FS &fs, const char *path) {
+  Serial.printf("Removing Dir: %s\n", path);
+  if (fs.rmdir(path)) {
+    Serial.println("Dir removed");
+  } else {
+    Serial.println("rmdir failed");
+  }
+}
 
-    File file = fs.open(path);
-    if(!file){
-        Serial.println("Failed to open file for reading");
-        return;
-    }
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\n", path);
 
-    Serial.print("Read from file: ");
-    while(file.available()){
-        Serial.write(file.read());
-    }
-    file.close();
+  File file = fs.open(path);
+  if (!file) {
+    Serial.println("Failed to open file for reading");
+    return;
+  }
+
+  Serial.print("Read from file: ");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
+  file.close();
 }
 
-void writeFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Writing file: %s\n", path);
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\n", path);
 
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("Failed to open file for writing");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("File written");
-    } else {
-        Serial.println("Write failed");
-    }
-    file.close();
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("File written");
+  } else {
+    Serial.println("Write failed");
+  }
+  file.close();
 }
 
-void appendFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Appending to file: %s\n", path);
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\n", path);
 
-    File file = fs.open(path, FILE_APPEND);
-    if(!file){
-        Serial.println("Failed to open file for appending");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("Message appended");
-    } else {
-        Serial.println("Append failed");
-    }
-    file.close();
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("Failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("Message appended");
+  } else {
+    Serial.println("Append failed");
+  }
+  file.close();
 }
 
-void renameFile(fs::FS &fs, const char * path1, const char * path2){
-    Serial.printf("Renaming file %s to %s\n", path1, path2);
-    if (fs.rename(path1, path2)) {
-        Serial.println("File renamed");
-    } else {
-        Serial.println("Rename failed");
-    }
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("File renamed");
+  } else {
+    Serial.println("Rename failed");
+  }
 }
 
-void deleteFile(fs::FS &fs, const char * path){
-    Serial.printf("Deleting file: %s\n", path);
-    if(fs.remove(path)){
-        Serial.println("File deleted");
-    } else {
-        Serial.println("Delete failed");
-    }
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\n", path);
+  if (fs.remove(path)) {
+    Serial.println("File deleted");
+  } else {
+    Serial.println("Delete failed");
+  }
 }
 
-void setup(){
-    Serial.begin(115200);
-    // We start by connecting to a WiFi network
-    Serial.println();
-    Serial.println();
-    Serial.print("Connecting to ");
-    Serial.println(ssid);
+void setup() {
+  Serial.begin(115200);
+  // We start by connecting to a WiFi network
+  Serial.println();
+  Serial.println();
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
 
-    WiFi.begin(ssid, password);
+  WiFi.begin(ssid, password);
 
-    while (WiFi.status() != WL_CONNECTED) {
-        delay(500);
-        Serial.print(".");
-    }
-    Serial.println("WiFi connected");
-    Serial.println("IP address: ");
-    Serial.println(WiFi.localIP());
-    Serial.println("Contacting Time Server");
-	configTime(3600*timezone, daysavetime*3600, "time.nist.gov", "0.pool.ntp.org", "1.pool.ntp.org");
-	struct tm tmstruct ;
-    delay(2000);
-    tmstruct.tm_year = 0;
-    getLocalTime(&tmstruct, 5000);
-	Serial.printf("\nNow is : %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct.tm_year)+1900,( tmstruct.tm_mon)+1, tmstruct.tm_mday,tmstruct.tm_hour , tmstruct.tm_min, tmstruct.tm_sec);
-    Serial.println("");
-    
-    if(!SD_MMC.begin()){
-        Serial.println("Card Mount Failed");
-        return;
-    }
-    uint8_t cardType = SD_MMC.cardType();
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  Serial.println("Contacting Time Server");
+  configTime(3600 * timezone, daysavetime * 3600, "time.nist.gov", "0.pool.ntp.org", "1.pool.ntp.org");
+  struct tm tmstruct;
+  delay(2000);
+  tmstruct.tm_year = 0;
+  getLocalTime(&tmstruct, 5000);
+  Serial.printf(
+    "\nNow is : %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct.tm_year) + 1900, (tmstruct.tm_mon) + 1, tmstruct.tm_mday, tmstruct.tm_hour, tmstruct.tm_min,
+    tmstruct.tm_sec
+  );
+  Serial.println("");
 
-    if(cardType == CARD_NONE){
-        Serial.println("No SD card attached");
-        return;
+  // If you are using any other ESP32-S3 board than ESP32-S3-USB-OTG which has preset default pins, you will
+  // need to specify the pins with the following example of SD_MMC.setPins()
+  // If you want to use only 1-bit mode, you can use the line with only one data pin (d0) begin changed.
+  // Please note that ESP32 does not allow pin changes and will fail unless you enter the same pin config as is the hardwired.
+#if defined(SOC_SDMMC_USE_GPIO_MATRIX) && not defined(BOARD_HAS_SDMMC)
+  if (use_1_bit_mode) {
+    if (!SD_MMC.setPins(clk, cmd, d0)) {  // 1-bit line version
+      Serial.println("Pin change failed!");
+      return;
     }
-
-    Serial.print("SD Card Type: ");
-    if(cardType == CARD_MMC){
-        Serial.println("MMC");
-    } else if(cardType == CARD_SD){
-        Serial.println("SDSC");
-    } else if(cardType == CARD_SDHC){
-        Serial.println("SDHC");
-    } else {
-        Serial.println("UNKNOWN");
+  } else {
+    if (!SD_MMC.setPins(clk, cmd, d0, d1, d2, d3)) {  // 4-bit line version
+      Serial.println("Pin change failed!");
+      return;
     }
+  }
+#endif
 
-    uint64_t cardSize = SD_MMC.cardSize() / (1024 * 1024);
-    Serial.printf("SD Card Size: %lluMB\n", cardSize);
+  if (!SD_MMC.begin("/sdcard", use_1_bit_mode)) {
+    Serial.println("Card Mount Failed.");
+    Serial.println("Increase log level to see more info: Tools > Core Debug Level > Verbose");
+    Serial.println("Make sure that all data pins have a 10k Ohm pull-up resistor to 3.3V");
+#ifdef SOC_SDMMC_USE_GPIO_MATRIX
+    Serial.println("Make sure that when using generic ESP32-S3 board the pins are setup using SD_MMC.setPins()");
+#endif
+    return;
+  }
+  uint8_t cardType = SD_MMC.cardType();
 
-    listDir(SD_MMC, "/", 0);
-    removeDir(SD_MMC, "/mydir");
-    createDir(SD_MMC, "/mydir");
-    deleteFile(SD_MMC, "/hello.txt");
-    writeFile(SD_MMC, "/hello.txt", "Hello ");
-    appendFile(SD_MMC, "/hello.txt", "World!\n");
-	listDir(SD_MMC, "/", 0);
-}
+  if (cardType == CARD_NONE) {
+    Serial.println("No SD card attached");
+    return;
+  }
 
-void loop(){
+  Serial.print("SD Card Type: ");
+  if (cardType == CARD_MMC) {
+    Serial.println("MMC");
+  } else if (cardType == CARD_SD) {
+    Serial.println("SDSC");
+  } else if (cardType == CARD_SDHC) {
+    Serial.println("SDHC");
+  } else {
+    Serial.println("UNKNOWN");
+  }
 
-}
+  uint64_t cardSize = SD_MMC.cardSize() / (1024 * 1024);
+  Serial.printf("SD Card Size: %lluMB\n", cardSize);
 
+  listDir(SD_MMC, "/", 0);
+  removeDir(SD_MMC, "/mydir");
+  createDir(SD_MMC, "/mydir");
+  deleteFile(SD_MMC, "/hello.txt");
+  writeFile(SD_MMC, "/hello.txt", "Hello ");
+  appendFile(SD_MMC, "/hello.txt", "World!\n");
+  listDir(SD_MMC, "/", 0);
+}
 
+void loop() {}
diff --git a/libraries/SD_MMC/examples/SDMMC_time/ci.json b/libraries/SD_MMC/examples/SDMMC_time/ci.json
new file mode 100644
index 00000000000..5552b63d32a
--- /dev/null
+++ b/libraries/SD_MMC/examples/SDMMC_time/ci.json
@@ -0,0 +1,9 @@
+{
+  "requires": [
+    "CONFIG_SOC_SDMMC_HOST_SUPPORTED=y"
+  ],
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/SD_MMC/library.properties b/libraries/SD_MMC/library.properties
index 9e47a6ee4be..855390e5057 100644
--- a/libraries/SD_MMC/library.properties
+++ b/libraries/SD_MMC/library.properties
@@ -1,5 +1,5 @@
 name=SD_MMC
-version=1.0
+version=3.2.0
 author=Hristo Gochkov, Ivan Grokhtkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=ESP32 SDMMC File System
diff --git a/libraries/SD_MMC/src/SD_MMC.cpp b/libraries/SD_MMC/src/SD_MMC.cpp
index 5db7d1a0c91..4665198c4ae 100644
--- a/libraries/SD_MMC/src/SD_MMC.cpp
+++ b/libraries/SD_MMC/src/SD_MMC.cpp
@@ -1,4 +1,4 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -12,136 +12,406 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+// Disable the automatic pin remapping of the API calls in this file
+#define ARDUINO_CORE_BUILD
+
+#include "pins_arduino.h"
+#include "io_pin_remap.h"
+#include "SD_MMC.h"
+#ifdef SOC_SDMMC_HOST_SUPPORTED
 #include "vfs_api.h"
 
-extern "C" {
-#include <sys/unistd.h>
-#include <sys/stat.h>
 #include <dirent.h>
 #include "esp_vfs_fat.h"
 #include "driver/sdmmc_host.h"
 #include "driver/sdmmc_defs.h"
 #include "sdmmc_cmd.h"
-}
+#include "diskio_sdmmc.h"
+#include "diskio.h"
+#include "soc/sdmmc_pins.h"
 #include "ff.h"
-#include "SD_MMC.h"
+#include "esp32-hal-periman.h"
+
+#if SOC_SDMMC_IO_POWER_EXTERNAL
+#include "sd_pwr_ctrl_by_on_chip_ldo.h"
+#endif
 
 using namespace fs;
-/*
 
-*/
+SDMMCFS::SDMMCFS(FSImplPtr impl) : FS(impl), _card(nullptr) {
+#if defined(SOC_SDMMC_USE_GPIO_MATRIX) && defined(BOARD_HAS_SDMMC) && !defined(CONFIG_IDF_TARGET_ESP32P4)
+  _pin_clk = SDMMC_CLK;
+  _pin_cmd = SDMMC_CMD;
+  _pin_d0 = SDMMC_D0;
+#ifndef BOARD_HAS_1BIT_SDMMC
+  _pin_d1 = SDMMC_D1;
+  _pin_d2 = SDMMC_D2;
+  _pin_d3 = SDMMC_D3;
+#endif  // BOARD_HAS_1BIT_SDMMC
+
+#elif defined(SOC_SDMMC_USE_IOMUX) && defined(CONFIG_IDF_TARGET_ESP32)
+  _pin_clk = SDMMC_SLOT1_IOMUX_PIN_NUM_CLK;
+  _pin_cmd = SDMMC_SLOT1_IOMUX_PIN_NUM_CMD;
+  _pin_d0 = SDMMC_SLOT1_IOMUX_PIN_NUM_D0;
+#ifndef BOARD_HAS_1BIT_SDMMC
+  _pin_d1 = SDMMC_SLOT1_IOMUX_PIN_NUM_D1;
+  _pin_d2 = SDMMC_SLOT1_IOMUX_PIN_NUM_D2;
+  _pin_d3 = SDMMC_SLOT1_IOMUX_PIN_NUM_D3;
+#endif  // BOARD_HAS_1BIT_SDMMC
+
+// ESP32-P4 can use either IOMUX or GPIO matrix
+#elif defined(BOARD_HAS_SDMMC) && defined(CONFIG_IDF_TARGET_ESP32P4)
+#if defined(BOARD_SDMMC_SLOT) && (BOARD_SDMMC_SLOT == 0)
+  _pin_clk = SDMMC_SLOT0_IOMUX_PIN_NUM_CLK;
+  _pin_cmd = SDMMC_SLOT0_IOMUX_PIN_NUM_CMD;
+  _pin_d0 = SDMMC_SLOT0_IOMUX_PIN_NUM_D0;
+#ifndef BOARD_HAS_1BIT_SDMMC
+  _pin_d1 = SDMMC_SLOT0_IOMUX_PIN_NUM_D1;
+  _pin_d2 = SDMMC_SLOT0_IOMUX_PIN_NUM_D2;
+  _pin_d3 = SDMMC_SLOT0_IOMUX_PIN_NUM_D3;
+#endif  // BOARD_HAS_1BIT_SDMMC
+#else
+  _pin_clk = SDMMC_CLK;
+  _pin_cmd = SDMMC_CMD;
+  _pin_d0 = SDMMC_D0;
+#ifndef BOARD_HAS_1BIT_SDMMC
+  _pin_d1 = SDMMC_D1;
+  _pin_d2 = SDMMC_D2;
+  _pin_d3 = SDMMC_D3;
+#endif  // BOARD_HAS_1BIT_SDMMC
+#endif  // BOARD_SDMMC_SLOT_NO
+#endif
+#if defined(SOC_SDMMC_IO_POWER_EXTERNAL) && defined(BOARD_SDMMC_POWER_CHANNEL)
+  _power_channel = BOARD_SDMMC_POWER_CHANNEL;
+#endif
+}
+
+bool SDMMCFS::sdmmcDetachBus(void *bus_pointer) {
+  SDMMCFS *bus = (SDMMCFS *)bus_pointer;
+  if (bus->_card) {
+    bus->end();
+  }
+  return true;
+}
+
+bool SDMMCFS::setPins(int clk, int cmd, int d0) {
+  return setPins(clk, cmd, d0, GPIO_NUM_NC, GPIO_NUM_NC, GPIO_NUM_NC);
+}
+
+bool SDMMCFS::setPins(int clk, int cmd, int d0, int d1, int d2, int d3) {
+  if (_card != nullptr) {
+    log_e("SD_MMC.setPins must be called before SD_MMC.begin");
+    return false;
+  }
 
-SDMMCFS::SDMMCFS(FSImplPtr impl)
-    : FS(impl), _card(NULL)
-{}
+  // map logical pins to GPIO numbers
+  clk = digitalPinToGPIONumber(clk);
+  cmd = digitalPinToGPIONumber(cmd);
+  d0 = digitalPinToGPIONumber(d0);
+  d1 = digitalPinToGPIONumber(d1);
+  d2 = digitalPinToGPIONumber(d2);
+  d3 = digitalPinToGPIONumber(d3);
+
+#if defined(SOC_SDMMC_USE_GPIO_MATRIX) && !defined(CONFIG_IDF_TARGET_ESP32P4)
+  // SoC supports SDMMC pin configuration via GPIO matrix. Save the pins for later use in SDMMCFS::begin.
+  _pin_clk = (int8_t)clk;
+  _pin_cmd = (int8_t)cmd;
+  _pin_d0 = (int8_t)d0;
+  _pin_d1 = (int8_t)d1;
+  _pin_d2 = (int8_t)d2;
+  _pin_d3 = (int8_t)d3;
+  return true;
+#elif CONFIG_IDF_TARGET_ESP32
+  // ESP32 doesn't support SDMMC pin configuration via GPIO matrix.
+  // Since SDMMCFS::begin hardcodes the usage of slot 1, only check if
+  // the pins match slot 1 pins.
+  bool pins_ok =
+    (clk == (int)SDMMC_SLOT1_IOMUX_PIN_NUM_CLK) && (cmd == (int)SDMMC_SLOT1_IOMUX_PIN_NUM_CMD) && (d0 == (int)SDMMC_SLOT1_IOMUX_PIN_NUM_D0)
+    && (((d1 == -1) && (d2 == -1) && (d3 == -1)) || ((d1 == (int)SDMMC_SLOT1_IOMUX_PIN_NUM_D1) && (d2 == (int)SDMMC_SLOT1_IOMUX_PIN_NUM_D2) && (d3 == (int)SDMMC_SLOT1_IOMUX_PIN_NUM_D3)));
+  if (!pins_ok) {
+    log_e("SDMMCFS: specified pins are not supported by this chip.");
+    return false;
+  }
+  return true;
+#elif defined(CONFIG_IDF_TARGET_ESP32P4)
+#if defined(BOARD_SDMMC_SLOT) && (BOARD_SDMMC_SLOT == 0)
+  // ESP32-P4 can use either IOMUX or GPIO matrix
+  bool pins_ok =
+    (clk == (int)SDMMC_SLOT0_IOMUX_PIN_NUM_CLK) && (cmd == (int)SDMMC_SLOT0_IOMUX_PIN_NUM_CMD) && (d0 == (int)SDMMC_SLOT0_IOMUX_PIN_NUM_D0)
+    && (((d1 == -1) && (d2 == -1) && (d3 == -1)) || ((d1 == (int)SDMMC_SLOT0_IOMUX_PIN_NUM_D1) && (d2 == (int)SDMMC_SLOT0_IOMUX_PIN_NUM_D2) && (d3 == (int)SDMMC_SLOT0_IOMUX_PIN_NUM_D3)));
+  if (!pins_ok) {
+    log_e("SDMMCFS: specified pins are not supported when using IOMUX (SDMMC SLOT 0).");
+    return false;
+  }
+  return true;
+#else
+  _pin_clk = (int8_t)clk;
+  _pin_cmd = (int8_t)cmd;
+  _pin_d0 = (int8_t)d0;
+  _pin_d1 = (int8_t)d1;
+  _pin_d2 = (int8_t)d2;
+  _pin_d3 = (int8_t)d3;
+  return true;
+#endif
+#else
+#error SoC not supported
+#endif
+}
 
-bool SDMMCFS::begin(const char * mountpoint, bool mode1bit)
-{
-    if(_card) {
-        return true;
+#ifdef SOC_SDMMC_IO_POWER_EXTERNAL
+bool SDMMCFS::setPowerChannel(int power_channel) {
+  if (_card != nullptr) {
+    log_e("SD_MMC.setPowerChannel must be called before SD_MMC.begin");
+    return false;
+  }
+  _power_channel = power_channel;
+  return true;
+}
+#endif
+
+bool SDMMCFS::begin(const char *mountpoint, bool mode1bit, bool format_if_mount_failed, int sdmmc_frequency, uint8_t maxOpenFiles) {
+  if (_card) {
+    return true;
+  }
+  perimanSetBusDeinit(ESP32_BUS_TYPE_SDMMC_CLK, SDMMCFS::sdmmcDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_SDMMC_CMD, SDMMCFS::sdmmcDetachBus);
+  perimanSetBusDeinit(ESP32_BUS_TYPE_SDMMC_D0, SDMMCFS::sdmmcDetachBus);
+  if (!mode1bit) {
+    perimanSetBusDeinit(ESP32_BUS_TYPE_SDMMC_D1, SDMMCFS::sdmmcDetachBus);
+    perimanSetBusDeinit(ESP32_BUS_TYPE_SDMMC_D2, SDMMCFS::sdmmcDetachBus);
+    perimanSetBusDeinit(ESP32_BUS_TYPE_SDMMC_D3, SDMMCFS::sdmmcDetachBus);
+  }
+  //mount
+  sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT();
+#if (defined(SOC_SDMMC_USE_GPIO_MATRIX) && !defined(CONFIG_IDF_TARGET_ESP32P4)) \
+  || (defined(CONFIG_IDF_TARGET_ESP32P4) && ((defined(BOARD_SDMMC_SLOT) && (BOARD_SDMMC_SLOT == 1)) || !defined(BOARD_HAS_SDMMC)))
+  log_d("pin_cmd: %d, pin_clk: %d, pin_d0: %d, pin_d1: %d, pin_d2: %d, pin_d3: %d", _pin_cmd, _pin_clk, _pin_d0, _pin_d1, _pin_d2, _pin_d3);
+  // SoC supports SDMMC pin configuration via GPIO matrix.
+  // Check that the pins have been set either in the constructor or setPins function.
+  if (_pin_cmd == -1 || _pin_clk == -1 || _pin_d0 == -1 || (!mode1bit && (_pin_d1 == -1 || _pin_d2 == -1 || _pin_d3 == -1))) {
+    log_e("SDMMCFS: some SD pins are not set");
+    return false;
+  }
+
+  slot_config.clk = (gpio_num_t)_pin_clk;
+  slot_config.cmd = (gpio_num_t)_pin_cmd;
+  slot_config.d0 = (gpio_num_t)_pin_d0;
+  slot_config.d1 = (gpio_num_t)_pin_d1;
+  slot_config.d2 = (gpio_num_t)_pin_d2;
+  slot_config.d3 = (gpio_num_t)_pin_d3;
+  slot_config.width = 4;
+#endif  // SOC_SDMMC_USE_GPIO_MATRIX
+
+  if (!perimanClearPinBus(_pin_cmd)) {
+    return false;
+  }
+  if (!perimanClearPinBus(_pin_clk)) {
+    return false;
+  }
+  if (!perimanClearPinBus(_pin_d0)) {
+    return false;
+  }
+  if (!mode1bit) {
+    if (!perimanClearPinBus(_pin_d1)) {
+      return false;
     }
-    //mount
-    sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT();
-    sdmmc_host_t host = {
-        .flags = SDMMC_HOST_FLAG_4BIT,
-        .slot = SDMMC_HOST_SLOT_1,
-        .max_freq_khz = SDMMC_FREQ_DEFAULT,
-        .io_voltage = 3.3f,
-        .init = &sdmmc_host_init,
-        .set_bus_width = &sdmmc_host_set_bus_width,
-        .get_bus_width = &sdmmc_host_get_slot_width,
-        .set_bus_ddr_mode = &sdmmc_host_set_bus_ddr_mode,
-        .set_card_clk = &sdmmc_host_set_card_clk,
-        .do_transaction = &sdmmc_host_do_transaction,
-        .deinit = &sdmmc_host_deinit,
-        .io_int_enable = &sdmmc_host_io_int_enable,
-        .io_int_wait = &sdmmc_host_io_int_wait,
-        .command_timeout_ms = 0
-    };
-    host.max_freq_khz = SDMMC_FREQ_HIGHSPEED;
+    if (!perimanClearPinBus(_pin_d2)) {
+      return false;
+    }
+    if (!perimanClearPinBus(_pin_d3)) {
+      return false;
+    }
+  }
+
+  sdmmc_host_t host = SDMMC_HOST_DEFAULT();
+  host.flags = SDMMC_HOST_FLAG_4BIT;
+#if defined(CONFIG_IDF_TARGET_ESP32P4) && defined(BOARD_SDMMC_SLOT) && (BOARD_SDMMC_SLOT == 0)
+  host.slot = SDMMC_HOST_SLOT_0;
+  // reconfigure slot_config to remove all pins in order to use IO_MUX
+  slot_config = {
+    .cd = SDMMC_SLOT_NO_CD,
+    .wp = SDMMC_SLOT_NO_WP,
+    .width = 4,
+    .flags = 0,
+  };
+#else
+  host.slot = SDMMC_HOST_SLOT_1;
+#endif
+  host.max_freq_khz = sdmmc_frequency;
 #ifdef BOARD_HAS_1BIT_SDMMC
-    mode1bit = true;
+  mode1bit = true;
 #endif
-    if(mode1bit) {
-        host.flags = SDMMC_HOST_FLAG_1BIT; //use 1-line SD mode
-	slot_config.width = 1;
-    }
+  if (mode1bit) {
+    host.flags = SDMMC_HOST_FLAG_1BIT;  //use 1-line SD mode
+    slot_config.width = 1;
+  }
+  _mode1bit = mode1bit;
 
-    esp_vfs_fat_sdmmc_mount_config_t mount_config = {
-        .format_if_mount_failed = false,
-        .max_files = 5,
-        .allocation_unit_size = 0
+#ifdef SOC_SDMMC_IO_POWER_EXTERNAL
+  if (_power_channel == -1) {
+    log_i("On-chip power channel specified, use external power for SDMMC");
+  } else {
+    sd_pwr_ctrl_ldo_config_t ldo_config = {
+      .ldo_chan_id = _power_channel,
     };
+    sd_pwr_ctrl_handle_t pwr_ctrl_handle = NULL;
 
-    esp_err_t ret = esp_vfs_fat_sdmmc_mount(mountpoint, &host, &slot_config, &mount_config, &_card);
-    if (ret != ESP_OK) {
-        if (ret == ESP_FAIL) {
-            log_e("Failed to mount filesystem. If you want the card to be formatted, set format_if_mount_failed = true.");
-        } else if (ret == ESP_ERR_INVALID_STATE) {
-            _impl->mountpoint(mountpoint);
-            log_w("SD Already mounted");
-            return true;
-        } else {
-            log_e("Failed to initialize the card (%d). Make sure SD card lines have pull-up resistors in place.", ret);
-        }
-        _card = NULL;
-        return false;
+    if (sd_pwr_ctrl_new_on_chip_ldo(&ldo_config, &pwr_ctrl_handle) != ESP_OK) {
+      log_e("Failed to create a new on-chip LDO power control driver");
+      return false;
     }
-    _impl->mountpoint(mountpoint);
-    return true;
-}
+    host.pwr_ctrl_handle = pwr_ctrl_handle;
+  }
+#endif
+
+#if defined(BOARD_SDMMC_POWER_PIN)
+#ifndef BOARD_SDMMC_POWER_ON_LEVEL
+#error "BOARD_SDMMC_POWER_ON_LEVEL not defined, please define it in pins_arduino.h"
+#endif
+  pinMode(BOARD_SDMMC_POWER_PIN, OUTPUT);
+  digitalWrite(BOARD_SDMMC_POWER_PIN, !BOARD_SDMMC_POWER_ON_LEVEL);
+  delay(200);
+  digitalWrite(BOARD_SDMMC_POWER_PIN, BOARD_SDMMC_POWER_ON_LEVEL);
+  perimanSetPinBusExtraType(BOARD_SDMMC_POWER_PIN, "SDMMC_POWER");
+#endif
 
-void SDMMCFS::end()
-{
-    if(_card) {
-        esp_vfs_fat_sdmmc_unmount();
-        _impl->mountpoint(NULL);
-        _card = NULL;
+  esp_vfs_fat_sdmmc_mount_config_t mount_config = {
+    .format_if_mount_failed = format_if_mount_failed,
+    .max_files = maxOpenFiles,
+    .allocation_unit_size = 0,
+    .disk_status_check_enable = false,
+    .use_one_fat = false
+  };
+
+  esp_err_t ret = esp_vfs_fat_sdmmc_mount(mountpoint, &host, &slot_config, &mount_config, &_card);
+  if (ret != ESP_OK) {
+    if (ret == ESP_FAIL) {
+      log_e("Failed to mount filesystem. If you want the card to be formatted, set format_if_mount_failed = true.");
+    } else if (ret == ESP_ERR_INVALID_STATE) {
+      _impl->mountpoint(mountpoint);
+      log_w("SD Already mounted");
+      return true;
+    } else {
+      log_e("Failed to initialize the card (0x%x). Make sure SD card lines have pull-up resistors in place.", ret);
     }
-}
+    _card = NULL;
+    return false;
+  }
+  _impl->mountpoint(mountpoint);
+  _pdrv = ff_diskio_get_pdrv_card(_card);
 
-sdcard_type_t SDMMCFS::cardType()
-{
-    if(!_card) {
-        return CARD_NONE;
+  if (!perimanSetPinBus(_pin_cmd, ESP32_BUS_TYPE_SDMMC_CMD, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!perimanSetPinBus(_pin_clk, ESP32_BUS_TYPE_SDMMC_CLK, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!perimanSetPinBus(_pin_d0, ESP32_BUS_TYPE_SDMMC_D0, (void *)(this), -1, -1)) {
+    goto err;
+  }
+  if (!mode1bit) {
+    if (!perimanSetPinBus(_pin_d1, ESP32_BUS_TYPE_SDMMC_D1, (void *)(this), -1, -1)) {
+      goto err;
+    }
+    if (!perimanSetPinBus(_pin_d2, ESP32_BUS_TYPE_SDMMC_D2, (void *)(this), -1, -1)) {
+      goto err;
     }
-    return (_card->ocr & SD_OCR_SDHC_CAP)?CARD_SDHC:CARD_SD;
+    if (!perimanSetPinBus(_pin_d3, ESP32_BUS_TYPE_SDMMC_D3, (void *)(this), -1, -1)) {
+      goto err;
+    }
+  }
+  return true;
+
+err:
+  log_e("Failed to set all pins bus to SDMMC");
+  SDMMCFS::sdmmcDetachBus((void *)(this));
+  return false;
 }
 
-uint64_t SDMMCFS::cardSize()
-{
-    if(!_card) {
-        return 0;
+void SDMMCFS::end() {
+  if (_card) {
+    esp_vfs_fat_sdcard_unmount(_impl->mountpoint(), _card);
+    _impl->mountpoint(NULL);
+    _card = NULL;
+    perimanClearPinBus(_pin_cmd);
+    perimanClearPinBus(_pin_clk);
+    perimanClearPinBus(_pin_d0);
+    if (!_mode1bit) {
+      perimanClearPinBus(_pin_d1);
+      perimanClearPinBus(_pin_d2);
+      perimanClearPinBus(_pin_d3);
     }
-    return (uint64_t)_card->csd.capacity * _card->csd.sector_size;
+#if defined(BOARD_SDMMC_POWER_PIN)
+    perimanClearPinBus(BOARD_SDMMC_POWER_PIN);
+#endif
+  }
+}
+
+sdcard_type_t SDMMCFS::cardType() {
+  if (!_card) {
+    return CARD_NONE;
+  }
+  return (_card->ocr & SD_OCR_SDHC_CAP) ? CARD_SDHC : CARD_SD;
+}
+
+uint64_t SDMMCFS::cardSize() {
+  if (!_card) {
+    return 0;
+  }
+  return (uint64_t)_card->csd.capacity * _card->csd.sector_size;
 }
 
-uint64_t SDMMCFS::totalBytes()
-{
-	FATFS* fsinfo;
-	DWORD fre_clust;
-	if(f_getfree("0:",&fre_clust,&fsinfo)!= 0) return 0;
-    uint64_t size = ((uint64_t)(fsinfo->csize))*(fsinfo->n_fatent - 2)
+uint64_t SDMMCFS::totalBytes() {
+  FATFS *fsinfo;
+  DWORD fre_clust;
+  if (f_getfree("0:", &fre_clust, &fsinfo) != 0) {
+    return 0;
+  }
+  uint64_t size = ((uint64_t)(fsinfo->csize)) * (fsinfo->n_fatent - 2)
 #if _MAX_SS != 512
-        *(fsinfo->ssize);
+                  * (fsinfo->ssize);
 #else
-        *512;
+                  * 512;
 #endif
-	return size;
+  return size;
 }
 
-uint64_t SDMMCFS::usedBytes()
-{
-	FATFS* fsinfo;
-	DWORD fre_clust;
-	if(f_getfree("0:",&fre_clust,&fsinfo)!= 0) return 0;
-	uint64_t size = ((uint64_t)(fsinfo->csize))*((fsinfo->n_fatent - 2) - (fsinfo->free_clst))
+uint64_t SDMMCFS::usedBytes() {
+  FATFS *fsinfo;
+  DWORD fre_clust;
+  if (f_getfree("0:", &fre_clust, &fsinfo) != 0) {
+    return 0;
+  }
+  uint64_t size = ((uint64_t)(fsinfo->csize)) * ((fsinfo->n_fatent - 2) - (fsinfo->free_clst))
 #if _MAX_SS != 512
-        *(fsinfo->ssize);
+                  * (fsinfo->ssize);
 #else
-        *512;
+                  * 512;
 #endif
-	return size;
+  return size;
+}
+
+int SDMMCFS::sectorSize() {
+  if (!_card) {
+    return 0;
+  }
+  return _card->csd.sector_size;
+}
+
+int SDMMCFS::numSectors() {
+  if (!_card) {
+    return 0;
+  }
+  return (totalBytes() / _card->csd.sector_size);
+}
+
+bool SDMMCFS::readRAW(uint8_t *buffer, uint32_t sector) {
+  return (disk_read(_pdrv, buffer, sector, 1) == 0);
+}
+
+bool SDMMCFS::writeRAW(uint8_t *buffer, uint32_t sector) {
+  return (disk_write(_pdrv, buffer, sector, 1) == 0);
 }
 
 SDMMCFS SD_MMC = SDMMCFS(FSImplPtr(new VFSImpl()));
+#endif /* SOC_SDMMC_HOST_SUPPORTED */
diff --git a/libraries/SD_MMC/src/SD_MMC.h b/libraries/SD_MMC/src/SD_MMC.h
index e3dc15432a5..b6fe13a0d24 100644
--- a/libraries/SD_MMC/src/SD_MMC.h
+++ b/libraries/SD_MMC/src/SD_MMC.h
@@ -14,30 +14,70 @@
 #ifndef _SDMMC_H_
 #define _SDMMC_H_
 
+#include "sdkconfig.h"
+#include "soc/soc_caps.h"
+#ifndef SOC_SDMMC_HOST_SUPPORTED
+#ifdef ARDUINO
+#warning The SDMMC library requires a device with an SDIO Host
+#endif
+#else
+
 #include "FS.h"
 #include "driver/sdmmc_types.h"
 #include "sd_defines.h"
 
-namespace fs
-{
+// If reading/writing to the SD card is unstable,
+// you can define BOARD_MAX_SDMMC_FREQ with lower value (Ex. SDMMC_FREQ_DEFAULT)
+// in pins_arduino.h for your board variant.
+#ifndef BOARD_MAX_SDMMC_FREQ
+#define BOARD_MAX_SDMMC_FREQ SDMMC_FREQ_HIGHSPEED
+#endif
+
+namespace fs {
 
-class SDMMCFS : public FS
-{
+class SDMMCFS : public FS {
 protected:
-    sdmmc_card_t* _card;
+  sdmmc_card_t *_card;
+  int8_t _pin_clk = -1;
+  int8_t _pin_cmd = -1;
+  int8_t _pin_d0 = -1;
+  int8_t _pin_d1 = -1;
+  int8_t _pin_d2 = -1;
+  int8_t _pin_d3 = -1;
+#ifdef SOC_SDMMC_IO_POWER_EXTERNAL
+  int8_t _power_channel = -1;
+#endif
+  uint8_t _pdrv = 0xFF;
+  bool _mode1bit = false;
 
 public:
-    SDMMCFS(FSImplPtr impl);
-    bool begin(const char * mountpoint="/sdcard", bool mode1bit=false);
-    void end();
-    sdcard_type_t cardType();
-    uint64_t cardSize();
-    uint64_t totalBytes();
-    uint64_t usedBytes();
+  SDMMCFS(FSImplPtr impl);
+  bool setPins(int clk, int cmd, int d0);
+  bool setPins(int clk, int cmd, int d0, int d1, int d2, int d3);
+#ifdef SOC_SDMMC_IO_POWER_EXTERNAL
+  bool setPowerChannel(int power_channel);
+#endif
+  bool begin(
+    const char *mountpoint = "/sdcard", bool mode1bit = false, bool format_if_mount_failed = false, int sdmmc_frequency = BOARD_MAX_SDMMC_FREQ,
+    uint8_t maxOpenFiles = 5
+  );
+  void end();
+  sdcard_type_t cardType();
+  uint64_t cardSize();
+  uint64_t totalBytes();
+  uint64_t usedBytes();
+  int sectorSize();
+  int numSectors();
+  bool readRAW(uint8_t *buffer, uint32_t sector);
+  bool writeRAW(uint8_t *buffer, uint32_t sector);
+
+private:
+  static bool sdmmcDetachBus(void *bus_pointer);
 };
 
-}
+}  // namespace fs
 
 extern fs::SDMMCFS SD_MMC;
 
+#endif /* SOC_SDMMC_HOST_SUPPORTED */
 #endif /* _SDMMC_H_ */
diff --git a/libraries/SD_MMC/src/sd_defines.h b/libraries/SD_MMC/src/sd_defines.h
index 6e42855ac61..9a6b8399165 100644
--- a/libraries/SD_MMC/src/sd_defines.h
+++ b/libraries/SD_MMC/src/sd_defines.h
@@ -15,11 +15,11 @@
 #define _SD_DEFINES_H_
 
 typedef enum {
-    CARD_NONE,
-    CARD_MMC,
-    CARD_SD,
-    CARD_SDHC,
-    CARD_UNKNOWN
+  CARD_NONE,
+  CARD_MMC,
+  CARD_SD,
+  CARD_SDHC,
+  CARD_UNKNOWN
 } sdcard_type_t;
 
 #endif /* _SD_DISKIO_H_ */
diff --git a/libraries/SPI/examples/SPI_Multiple_Buses/SPI_Multiple_Buses.ino b/libraries/SPI/examples/SPI_Multiple_Buses/SPI_Multiple_Buses.ino
index 3d46aadf025..06765c64fd2 100644
--- a/libraries/SPI/examples/SPI_Multiple_Buses/SPI_Multiple_Buses.ino
+++ b/libraries/SPI/examples/SPI_Multiple_Buses/SPI_Multiple_Buses.ino
@@ -1,16 +1,16 @@
 
 
 /* The ESP32 has four SPi buses, however as of right now only two of
- * them are available to use, HSPI and VSPI. Simply using the SPI API 
+ * them are available to use, HSPI and VSPI. Simply using the SPI API
  * as illustrated in Arduino examples will use VSPI, leaving HSPI unused.
- * 
- * However if we simply intialise two instance of the SPI class for both
+ *
+ * However if we simply initialize two instance of the SPI class for both
  * of these buses both can be used. However when just using these the Arduino
  * way only will actually be outputting at a time.
- * 
- * Logic analyser capture is in the same folder as this example as
+ *
+ * Logic analyzer capture is in the same folder as this example as
  * "multiple_bus_output.png"
- * 
+ *
  * created 30/04/2018 by Alistair Symonds
  */
 #include <SPI.h>
@@ -18,90 +18,81 @@
 // Define ALTERNATE_PINS to use non-standard GPIO pins for SPI bus
 
 #ifdef ALTERNATE_PINS
-  #define VSPI_MISO   2
-  #define VSPI_MOSI   4
-  #define VSPI_SCLK   0
-  #define VSPI_SS     33
-
-  #define HSPI_MISO   26
-  #define HSPI_MOSI   27
-  #define HSPI_SCLK   25
-  #define HSPI_SS     32
+#define VSPI_MISO 2
+#define VSPI_MOSI 4
+#define VSPI_SCLK 0
+#define VSPI_SS   33
+
+#define HSPI_MISO 26
+#define HSPI_MOSI 27
+#define HSPI_SCLK 25
+#define HSPI_SS   32
 #else
-  #define VSPI_MISO   MISO
-  #define VSPI_MOSI   MOSI
-  #define VSPI_SCLK   SCK
-  #define VSPI_SS     SS
-
-  #define HSPI_MISO   12
-  #define HSPI_MOSI   13
-  #define HSPI_SCLK   14
-  #define HSPI_SS     15
+#define VSPI_MISO MISO
+#define VSPI_MOSI MOSI
+#define VSPI_SCLK SCK
+#define VSPI_SS   SS
+
+#define HSPI_MISO 12
+#define HSPI_MOSI 13
+#define HSPI_SCLK 14
+#define HSPI_SS   15
 #endif
 
-static const int spiClk = 1000000; // 1 MHz
+#if !defined(CONFIG_IDF_TARGET_ESP32)
+#define VSPI FSPI
+#endif
+
+static const int spiClk = 1000000;  // 1 MHz
 
-//uninitalised pointers to SPI objects
-SPIClass * vspi = NULL;
-SPIClass * hspi = NULL;
+//uninitialized pointers to SPI objects
+SPIClass *vspi = NULL;
+SPIClass *hspi = NULL;
 
 void setup() {
-  //initialise two instances of the SPIClass attached to VSPI and HSPI respectively
+  //initialize two instances of the SPIClass attached to VSPI and HSPI respectively
   vspi = new SPIClass(VSPI);
   hspi = new SPIClass(HSPI);
-  
+
   //clock miso mosi ss
 
 #ifndef ALTERNATE_PINS
-  //initialise vspi with default pins
+  //initialize vspi with default pins
   //SCLK = 18, MISO = 19, MOSI = 23, SS = 5
   vspi->begin();
 #else
   //alternatively route through GPIO pins of your choice
-  vspi->begin(VSPI_SCLK, VSPI_MISO, VSPI_MOSI, VSPI_SS); //SCLK, MISO, MOSI, SS
+  vspi->begin(VSPI_SCLK, VSPI_MISO, VSPI_MOSI, VSPI_SS);  //SCLK, MISO, MOSI, SS
 #endif
 
 #ifndef ALTERNATE_PINS
-  //initialise hspi with default pins
+  //initialize hspi with default pins
   //SCLK = 14, MISO = 12, MOSI = 13, SS = 15
   hspi->begin();
 #else
   //alternatively route through GPIO pins
-  hspi->begin(HSPI_SCLK, HSPI_MISO, HSPI_MOSI, HSPI_SS); //SCLK, MISO, MOSI, SS
+  hspi->begin(HSPI_SCLK, HSPI_MISO, HSPI_MOSI, HSPI_SS);  //SCLK, MISO, MOSI, SS
 #endif
 
   //set up slave select pins as outputs as the Arduino API
   //doesn't handle automatically pulling SS low
-  pinMode(VSPI_SS, OUTPUT); //VSPI SS
-  pinMode(HSPI_SS, OUTPUT); //HSPI SS
-
+  pinMode(vspi->pinSS(), OUTPUT);  //VSPI SS
+  pinMode(hspi->pinSS(), OUTPUT);  //HSPI SS
 }
 
 // the loop function runs over and over again until power down or reset
 void loop() {
   //use the SPI buses
-  vspiCommand();
-  hspiCommand();
+  spiCommand(vspi, 0b01010101);  // junk data to illustrate usage
+  spiCommand(hspi, 0b11001100);
   delay(100);
 }
 
-void vspiCommand() {
-  byte data = 0b01010101; // junk data to illustrate usage
-
+void spiCommand(SPIClass *spi, byte data) {
   //use it as you would the regular arduino SPI API
-  vspi->beginTransaction(SPISettings(spiClk, MSBFIRST, SPI_MODE0));
-  digitalWrite(VSPI_SS, LOW); //pull SS slow to prep other end for transfer
-  vspi->transfer(data);  
-  digitalWrite(VSPI_SS, HIGH); //pull ss high to signify end of data transfer
-  vspi->endTransaction();
-}
-
-void hspiCommand() {
-  byte stuff = 0b11001100;
-  
-  hspi->beginTransaction(SPISettings(spiClk, MSBFIRST, SPI_MODE0));
-  digitalWrite(HSPI_SS, LOW);
-  hspi->transfer(stuff);
-  digitalWrite(HSPI_SS, HIGH);
-  hspi->endTransaction();
+  spi->beginTransaction(SPISettings(spiClk, MSBFIRST, SPI_MODE0));
+  digitalWrite(spi->pinSS(), LOW);  //pull SS slow to prep other end for transfer
+  spi->transfer(data);
+  digitalWrite(spi->pinSS(), HIGH);  //pull ss high to signify end of data transfer
+  spi->endTransaction();
 }
diff --git a/libraries/SPI/examples/SPI_Multiple_Buses/ci.json b/libraries/SPI/examples/SPI_Multiple_Buses/ci.json
new file mode 100644
index 00000000000..cd27a02724b
--- /dev/null
+++ b/libraries/SPI/examples/SPI_Multiple_Buses/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_SPI_PERIPH_NUM=[2-9]"
+  ]
+}
diff --git a/libraries/SPI/keywords.txt b/libraries/SPI/keywords.txt
index fa7616581aa..492c2647781 100644
--- a/libraries/SPI/keywords.txt
+++ b/libraries/SPI/keywords.txt
@@ -33,4 +33,4 @@ SPI_CLOCK_DIV64	LITERAL1
 SPI_MODE0	LITERAL1
 SPI_MODE1	LITERAL1
 SPI_MODE2	LITERAL1
-SPI_MODE3	LITERAL1
\ No newline at end of file
+SPI_MODE3	LITERAL1
diff --git a/libraries/SPI/library.properties b/libraries/SPI/library.properties
index 9e8f805da75..64db93aceeb 100644
--- a/libraries/SPI/library.properties
+++ b/libraries/SPI/library.properties
@@ -1,8 +1,8 @@
 name=SPI
-version=1.0
+version=3.2.0
 author=Hristo Gochkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
-sentence=Enables the communication with devices that use the Serial Peripheral Interface (SPI) Bus. For all Arduino boards, BUT Arduino DUE. 
+sentence=Enables the communication with devices that use the Serial Peripheral Interface (SPI) Bus. For all Arduino boards, BUT Arduino DUE.
 paragraph=
 category=Signal Input/Output
 url=http://arduino.cc/en/Reference/SPI
diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp
index beebe0ea5a3..35e52f43e4d 100644
--- a/libraries/SPI/src/SPI.cpp
+++ b/libraries/SPI/src/SPI.cpp
@@ -1,9 +1,9 @@
-/* 
+/*
  SPI.cpp - SPI library for esp8266
 
  Copyright (c) 2015 Hristo Gochkov. All rights reserved.
  This file is part of the esp8266 core for Arduino environment.
- 
+
  This library is free software; you can redistribute it and/or
  modify it under the terms of the GNU Lesser General Public
  License as published by the Free Software Foundation; either
@@ -20,217 +20,258 @@
  */
 
 #include "SPI.h"
+#if SOC_GPSPI_SUPPORTED
 
-SPIClass::SPIClass(uint8_t spi_bus)
-    :_spi_num(spi_bus)
-    ,_spi(NULL)
-    ,_use_hw_ss(false)
-    ,_sck(-1)
-    ,_miso(-1)
-    ,_mosi(-1)
-    ,_ss(-1)
-    ,_div(0)
-    ,_freq(1000000)
-    ,_inTransaction(false)
-{}
-
-void SPIClass::begin(int8_t sck, int8_t miso, int8_t mosi, int8_t ss)
-{
-    if(_spi) {
-        return;
-    }
-
-    if(!_div) {
-        _div = spiFrequencyToClockDiv(_freq);
-    }
+#include "io_pin_remap.h"
+#include "esp32-hal-log.h"
 
-    _spi = spiStartBus(_spi_num, _div, SPI_MODE0, SPI_MSBFIRST);
-    if(!_spi) {
-        return;
-    }
+#if !CONFIG_DISABLE_HAL_LOCKS
+#define SPI_PARAM_LOCK() \
+  do {                   \
+  } while (xSemaphoreTake(paramLock, portMAX_DELAY) != pdPASS)
+#define SPI_PARAM_UNLOCK() xSemaphoreGive(paramLock)
+#else
+#define SPI_PARAM_LOCK()
+#define SPI_PARAM_UNLOCK()
+#endif
 
-    if(sck == -1 && miso == -1 && mosi == -1 && ss == -1) {
-        _sck = (_spi_num == VSPI) ? SCK : 14;
-        _miso = (_spi_num == VSPI) ? MISO : 12;
-        _mosi = (_spi_num == VSPI) ? MOSI : 13;
-        _ss = (_spi_num == VSPI) ? SS : 15;
-    } else {
-        _sck = sck;
-        _miso = miso;
-        _mosi = mosi;
-        _ss = ss;
+SPIClass::SPIClass(uint8_t spi_bus)
+  : _spi_num(spi_bus), _spi(NULL), _use_hw_ss(false), _sck(-1), _miso(-1), _mosi(-1), _ss(-1), _div(0), _freq(1000000), _inTransaction(false)
+#if !CONFIG_DISABLE_HAL_LOCKS
+    ,
+    paramLock(NULL) {
+  if (paramLock == NULL) {
+    paramLock = xSemaphoreCreateMutex();
+    if (paramLock == NULL) {
+      log_e("xSemaphoreCreateMutex failed");
+      return;
     }
+  }
+}
+#else
+{
+}
+#endif
+
+SPIClass::~SPIClass() {
+  end();
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (paramLock != NULL) {
+    vSemaphoreDelete(paramLock);
+    paramLock = NULL;
+  }
+#endif
+}
 
-    spiAttachSCK(_spi, _sck);
-    spiAttachMISO(_spi, _miso);
-    spiAttachMOSI(_spi, _mosi);
-
+void SPIClass::begin(int8_t sck, int8_t miso, int8_t mosi, int8_t ss) {
+  if (_spi) {
+    return;
+  }
+
+  if (!_div) {
+    _div = spiFrequencyToClockDiv(_freq);
+  }
+
+  _spi = spiStartBus(_spi_num, _div, SPI_MODE0, SPI_MSBFIRST);
+  if (!_spi) {
+    return;
+  }
+
+  if (sck == -1 && miso == -1 && mosi == -1 && ss == -1) {
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+    _sck = (_spi_num == FSPI) ? SCK : -1;
+    _miso = (_spi_num == FSPI) ? MISO : -1;
+    _mosi = (_spi_num == FSPI) ? MOSI : -1;
+    _ss = (_spi_num == FSPI) ? SS : -1;
+#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+    _sck = SCK;
+    _miso = MISO;
+    _mosi = MOSI;
+    _ss = SS;
+#else
+    _sck = (_spi_num == VSPI) ? SCK : 14;
+    _miso = (_spi_num == VSPI) ? MISO : 12;
+    _mosi = (_spi_num == VSPI) ? MOSI : 13;
+    _ss = (_spi_num == VSPI) ? SS : 15;
+#endif
+  } else {
+    _sck = sck;
+    _miso = miso;
+    _mosi = mosi;
+    _ss = ss;
+  }
+
+  if (!spiAttachSCK(_spi, _sck)) {
+    goto err;
+  }
+  if (_miso >= 0 && !spiAttachMISO(_spi, _miso)) {
+    goto err;
+  }
+  if (_mosi >= 0 && !spiAttachMOSI(_spi, _mosi)) {
+    goto err;
+  }
+  return;
+
+err:
+  log_e("Attaching pins to SPI failed.");
 }
 
-void SPIClass::end()
-{
-    if(!_spi) {
-        return;
-    }
-    spiDetachSCK(_spi, _sck);
-    spiDetachMISO(_spi, _miso);
-    spiDetachMOSI(_spi, _mosi);
-    setHwCs(false);
+void SPIClass::end() {
+  if (!_spi) {
+    return;
+  }
+  spiDetachSCK(_spi);
+  spiDetachMISO(_spi);
+  spiDetachMOSI(_spi);
+  setHwCs(false);
+  if (spiGetClockDiv(_spi) != 0) {
     spiStopBus(_spi);
-    _spi = NULL;
+  }
+  _spi = NULL;
 }
 
-void SPIClass::setHwCs(bool use)
-{
-    if(use && !_use_hw_ss) {
-        spiAttachSS(_spi, 0, _ss);
-        spiSSEnable(_spi);
-    } else if(_use_hw_ss) {
-        spiSSDisable(_spi);
-        spiDetachSS(_spi, _ss);
-    }
-    _use_hw_ss = use;
+void SPIClass::setHwCs(bool use) {
+  if (_ss < 0) {
+    return;
+  }
+  if (use && !_use_hw_ss) {
+    spiAttachSS(_spi, 0, _ss);
+    spiSSEnable(_spi);
+  } else if (!use && _use_hw_ss) {
+    spiSSDisable(_spi);
+    spiDetachSS(_spi);
+  }
+  _use_hw_ss = use;
 }
 
-void SPIClass::setFrequency(uint32_t freq)
-{
-    //check if last freq changed
-    uint32_t cdiv = spiGetClockDiv(_spi);
-    if(_freq != freq || _div != cdiv) {
-        _freq = freq;
-        _div = spiFrequencyToClockDiv(_freq);
-        spiSetClockDiv(_spi, _div);
-    }
+void SPIClass::setFrequency(uint32_t freq) {
+  SPI_PARAM_LOCK();
+  //check if last freq changed
+  uint32_t cdiv = spiGetClockDiv(_spi);
+  if (_freq != freq || _div != cdiv) {
+    _freq = freq;
+    _div = spiFrequencyToClockDiv(_freq);
+    spiSetClockDiv(_spi, _div);
+  }
+  SPI_PARAM_UNLOCK();
 }
 
-void SPIClass::setClockDivider(uint32_t clockDiv)
-{
-    _div = clockDiv;
-    spiSetClockDiv(_spi, _div);
+void SPIClass::setClockDivider(uint32_t clockDiv) {
+  SPI_PARAM_LOCK();
+  _div = clockDiv;
+  spiSetClockDiv(_spi, _div);
+  SPI_PARAM_UNLOCK();
 }
 
-uint32_t SPIClass::getClockDivider()
-{
-    return spiGetClockDiv(_spi);
+uint32_t SPIClass::getClockDivider() {
+  return spiGetClockDiv(_spi);
 }
 
-void SPIClass::setDataMode(uint8_t dataMode)
-{
-    spiSetDataMode(_spi, dataMode);
+void SPIClass::setDataMode(uint8_t dataMode) {
+  spiSetDataMode(_spi, dataMode);
 }
 
-void SPIClass::setBitOrder(uint8_t bitOrder)
-{
-    spiSetBitOrder(_spi, bitOrder);
+void SPIClass::setBitOrder(uint8_t bitOrder) {
+  spiSetBitOrder(_spi, bitOrder);
 }
 
-void SPIClass::beginTransaction(SPISettings settings)
-{
-    //check if last freq changed
-    uint32_t cdiv = spiGetClockDiv(_spi);
-    if(_freq != settings._clock || _div != cdiv) {
-        _freq = settings._clock;
-        _div = spiFrequencyToClockDiv(_freq);
-    }
-    spiTransaction(_spi, _div, settings._dataMode, settings._bitOrder);
-    _inTransaction = true;
+void SPIClass::beginTransaction(SPISettings settings) {
+  SPI_PARAM_LOCK();
+  //check if last freq changed
+  uint32_t cdiv = spiGetClockDiv(_spi);
+  if (_freq != settings._clock || _div != cdiv) {
+    _freq = settings._clock;
+    _div = spiFrequencyToClockDiv(_freq);
+  }
+  spiTransaction(_spi, _div, settings._dataMode, settings._bitOrder);
+  _inTransaction = true;
 }
 
-void SPIClass::endTransaction()
-{
-    if(_inTransaction){
-        _inTransaction = false;
-        spiEndTransaction(_spi);
-    }
+void SPIClass::endTransaction() {
+  if (_inTransaction) {
+    _inTransaction = false;
+    spiEndTransaction(_spi);
+    SPI_PARAM_UNLOCK();  // <-- Im not sure should it be here or right after spiTransaction()
+  }
 }
 
-void SPIClass::write(uint8_t data)
-{
-    if(_inTransaction){
-        return spiWriteByteNL(_spi, data);
-    }
-    spiWriteByte(_spi, data);
+void SPIClass::write(uint8_t data) {
+  if (_inTransaction) {
+    return spiWriteByteNL(_spi, data);
+  }
+  spiWriteByte(_spi, data);
 }
 
-uint8_t SPIClass::transfer(uint8_t data)
-{
-    if(_inTransaction){
-        return spiTransferByteNL(_spi, data);
-    }
-    return spiTransferByte(_spi, data);
+uint8_t SPIClass::transfer(uint8_t data) {
+  if (_inTransaction) {
+    return spiTransferByteNL(_spi, data);
+  }
+  return spiTransferByte(_spi, data);
 }
 
-void SPIClass::write16(uint16_t data)
-{
-    if(_inTransaction){
-        return spiWriteShortNL(_spi, data);
-    }
-    spiWriteWord(_spi, data);
+void SPIClass::write16(uint16_t data) {
+  if (_inTransaction) {
+    return spiWriteShortNL(_spi, data);
+  }
+  spiWriteWord(_spi, data);
 }
 
-uint16_t SPIClass::transfer16(uint16_t data)
-{
-    if(_inTransaction){
-        return spiTransferShortNL(_spi, data);
-    }
-    return spiTransferWord(_spi, data);
+uint16_t SPIClass::transfer16(uint16_t data) {
+  if (_inTransaction) {
+    return spiTransferShortNL(_spi, data);
+  }
+  return spiTransferWord(_spi, data);
 }
 
-void SPIClass::write32(uint32_t data)
-{
-    if(_inTransaction){
-        return spiWriteLongNL(_spi, data);
-    }
-    spiWriteLong(_spi, data);
+void SPIClass::write32(uint32_t data) {
+  if (_inTransaction) {
+    return spiWriteLongNL(_spi, data);
+  }
+  spiWriteLong(_spi, data);
 }
 
-uint32_t SPIClass::transfer32(uint32_t data)
-{
-    if(_inTransaction){
-        return spiTransferLongNL(_spi, data);
-    }
-    return spiTransferLong(_spi, data);
+uint32_t SPIClass::transfer32(uint32_t data) {
+  if (_inTransaction) {
+    return spiTransferLongNL(_spi, data);
+  }
+  return spiTransferLong(_spi, data);
 }
 
-void SPIClass::transferBits(uint32_t data, uint32_t * out, uint8_t bits)
-{
-    if(_inTransaction){
-        return spiTransferBitsNL(_spi, data, out, bits);
-    }
-    spiTransferBits(_spi, data, out, bits);
+void SPIClass::transferBits(uint32_t data, uint32_t *out, uint8_t bits) {
+  if (_inTransaction) {
+    return spiTransferBitsNL(_spi, data, out, bits);
+  }
+  spiTransferBits(_spi, data, out, bits);
 }
 
 /**
  * @param data uint8_t *
  * @param size uint32_t
  */
-void SPIClass::writeBytes(const uint8_t * data, uint32_t size)
-{
-    if(_inTransaction){
-        return spiWriteNL(_spi, data, size);
-    }
-    spiSimpleTransaction(_spi);
-    spiWriteNL(_spi, data, size);
-    spiEndTransaction(_spi);
+void SPIClass::writeBytes(const uint8_t *data, uint32_t size) {
+  if (_inTransaction) {
+    return spiWriteNL(_spi, data, size);
+  }
+  spiSimpleTransaction(_spi);
+  spiWriteNL(_spi, data, size);
+  spiEndTransaction(_spi);
 }
 
-void SPIClass::transfer(uint8_t * data, uint32_t size) 
-{ 
-	transferBytes(data, data, size); 
+void SPIClass::transfer(void *data, uint32_t size) {
+  transferBytes((const uint8_t *)data, (uint8_t *)data, size);
 }
 
 /**
  * @param data void *
  * @param size uint32_t
  */
-void SPIClass::writePixels(const void * data, uint32_t size)
-{
-    if(_inTransaction){
-        return spiWritePixelsNL(_spi, data, size);
-    }
-    spiSimpleTransaction(_spi);
-    spiWritePixelsNL(_spi, data, size);
-    spiEndTransaction(_spi);
+void SPIClass::writePixels(const void *data, uint32_t size) {
+  if (_inTransaction) {
+    return spiWritePixelsNL(_spi, data, size);
+  }
+  spiSimpleTransaction(_spi);
+  spiWritePixelsNL(_spi, data, size);
+  spiEndTransaction(_spi);
 }
 
 /**
@@ -238,12 +279,11 @@ void SPIClass::writePixels(const void * data, uint32_t size)
  * @param out  uint8_t * output buffer. can be NULL for Write Only operation
  * @param size uint32_t
  */
-void SPIClass::transferBytes(const uint8_t * data, uint8_t * out, uint32_t size)
-{
-    if(_inTransaction){
-        return spiTransferBytesNL(_spi, data, out, size);
-    }
-    spiTransferBytes(_spi, data, out, size);
+void SPIClass::transferBytes(const uint8_t *data, uint8_t *out, uint32_t size) {
+  if (_inTransaction) {
+    return spiTransferBytesNL(_spi, data, out, size);
+  }
+  spiTransferBytes(_spi, data, out, size);
 }
 
 /**
@@ -251,45 +291,49 @@ void SPIClass::transferBytes(const uint8_t * data, uint8_t * out, uint32_t size)
  * @param size uint8_t  max for size is 64Byte
  * @param repeat uint32_t
  */
-void SPIClass::writePattern(const uint8_t * data, uint8_t size, uint32_t repeat)
-{
-    if(size > 64) {
-        return;    //max Hardware FIFO
-    }
-
-    uint32_t byte = (size * repeat);
-    uint8_t r = (64 / size);
-    const uint8_t max_bytes_FIFO = r * size;    // Max number of whole patterns (in bytes) that can fit into the hardware FIFO
-
-    while(byte) {
-        if(byte > max_bytes_FIFO) {
-            writePattern_(data, size, r);
-            byte -= max_bytes_FIFO;
-        } else {
-            writePattern_(data, size, (byte / size));
-            byte = 0;
-        }
+void SPIClass::writePattern(const uint8_t *data, uint8_t size, uint32_t repeat) {
+  if (size > 64) {
+    return;  //max Hardware FIFO
+  }
+
+  uint32_t byte = (size * repeat);
+  uint8_t r = (64 / size);
+  const uint8_t max_bytes_FIFO = r * size;  // Max number of whole patterns (in bytes) that can fit into the hardware FIFO
+
+  while (byte) {
+    if (byte > max_bytes_FIFO) {
+      writePattern_(data, size, r);
+      byte -= max_bytes_FIFO;
+    } else {
+      writePattern_(data, size, (byte / size));
+      byte = 0;
     }
+  }
 }
 
-void SPIClass::writePattern_(const uint8_t * data, uint8_t size, uint8_t repeat)
-{
-    uint8_t bytes = (size * repeat);
-    uint8_t buffer[64];
-    uint8_t * bufferPtr = &buffer[0];
-    const uint8_t * dataPtr;
-    uint8_t dataSize = bytes;
-    for(uint8_t i = 0; i < repeat; i++) {
-        dataSize = size;
-        dataPtr = data;
-        while(dataSize--) {
-            *bufferPtr = *dataPtr;
-            dataPtr++;
-            bufferPtr++;
-        }
+void SPIClass::writePattern_(const uint8_t *data, uint8_t size, uint8_t repeat) {
+  uint8_t bytes = (size * repeat);
+  uint8_t buffer[64];
+  uint8_t *bufferPtr = &buffer[0];
+  const uint8_t *dataPtr;
+  uint8_t dataSize = bytes;
+  for (uint8_t i = 0; i < repeat; i++) {
+    dataSize = size;
+    dataPtr = data;
+    while (dataSize--) {
+      *bufferPtr = *dataPtr;
+      dataPtr++;
+      bufferPtr++;
     }
+  }
 
-    writeBytes(&buffer[0], bytes);
+  writeBytes(&buffer[0], bytes);
 }
 
+#if CONFIG_IDF_TARGET_ESP32
 SPIClass SPI(VSPI);
+#else
+SPIClass SPI(FSPI);
+#endif
+
+#endif /* SOC_GPSPI_SUPPORTED */
diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h
index 33bf5886acb..adb3d1bc11f 100644
--- a/libraries/SPI/src/SPI.h
+++ b/libraries/SPI/src/SPI.h
@@ -1,9 +1,9 @@
-/* 
+/*
   SPI.h - SPI library for esp32
 
   Copyright (c) 2015 Hristo Gochkov. All rights reserved.
   This file is part of the esp8266 core for Arduino environment.
- 
+
   This library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
@@ -21,70 +21,83 @@
 #ifndef _SPI_H_INCLUDED
 #define _SPI_H_INCLUDED
 
+#include "soc/soc_caps.h"
+#if SOC_GPSPI_SUPPORTED
+
 #include <stdlib.h>
 #include "pins_arduino.h"
 #include "esp32-hal-spi.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
 
 #define SPI_HAS_TRANSACTION
 
-class SPISettings
-{
+class SPISettings {
 public:
-    SPISettings() :_clock(1000000), _bitOrder(SPI_MSBFIRST), _dataMode(SPI_MODE0) {}
-    SPISettings(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) :_clock(clock), _bitOrder(bitOrder), _dataMode(dataMode) {}
-    uint32_t _clock;
-    uint8_t  _bitOrder;
-    uint8_t  _dataMode;
+  SPISettings() : _clock(1000000), _bitOrder(SPI_MSBFIRST), _dataMode(SPI_MODE0) {}
+  SPISettings(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) : _clock(clock), _bitOrder(bitOrder), _dataMode(dataMode) {}
+  uint32_t _clock;
+  uint8_t _bitOrder;
+  uint8_t _dataMode;
 };
 
-class SPIClass
-{
+class SPIClass {
 private:
-    int8_t _spi_num;
-    spi_t * _spi;
-    bool _use_hw_ss;
-    int8_t _sck;
-    int8_t _miso;
-    int8_t _mosi;
-    int8_t _ss;
-    uint32_t _div;
-    uint32_t _freq;
-    bool _inTransaction;
-    void writePattern_(const uint8_t * data, uint8_t size, uint8_t repeat);
+  int8_t _spi_num;
+  spi_t *_spi;
+  bool _use_hw_ss;
+  int8_t _sck;
+  int8_t _miso;
+  int8_t _mosi;
+  int8_t _ss;
+  uint32_t _div;
+  uint32_t _freq;
+  bool _inTransaction;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  SemaphoreHandle_t paramLock = NULL;
+#endif
+  void writePattern_(const uint8_t *data, uint8_t size, uint8_t repeat);
 
 public:
-    SPIClass(uint8_t spi_bus=HSPI);
-    void begin(int8_t sck=-1, int8_t miso=-1, int8_t mosi=-1, int8_t ss=-1);
-    void end();
-
-    void setHwCs(bool use);
-    void setBitOrder(uint8_t bitOrder);
-    void setDataMode(uint8_t dataMode);
-    void setFrequency(uint32_t freq);
-    void setClockDivider(uint32_t clockDiv);
-    
-    uint32_t getClockDivider();
-
-    void beginTransaction(SPISettings settings);
-    void endTransaction(void);
-    void transfer(uint8_t * data, uint32_t size);
-    uint8_t transfer(uint8_t data);
-    uint16_t transfer16(uint16_t data);
-    uint32_t transfer32(uint32_t data);
-  
-    void transferBytes(const uint8_t * data, uint8_t * out, uint32_t size);
-    void transferBits(uint32_t data, uint32_t * out, uint8_t bits);
-
-    void write(uint8_t data);
-    void write16(uint16_t data);
-    void write32(uint32_t data);
-    void writeBytes(const uint8_t * data, uint32_t size);
-    void writePixels(const void * data, uint32_t size);//ili9341 compatible
-    void writePattern(const uint8_t * data, uint8_t size, uint32_t repeat);
-
-    spi_t * bus(){ return _spi; }
+  SPIClass(uint8_t spi_bus = HSPI);
+  ~SPIClass();
+  void begin(int8_t sck = -1, int8_t miso = -1, int8_t mosi = -1, int8_t ss = -1);
+  void end();
+
+  void setHwCs(bool use);
+  void setBitOrder(uint8_t bitOrder);
+  void setDataMode(uint8_t dataMode);
+  void setFrequency(uint32_t freq);
+  void setClockDivider(uint32_t clockDiv);
+
+  uint32_t getClockDivider();
+
+  void beginTransaction(SPISettings settings);
+  void endTransaction(void);
+  void transfer(void *data, uint32_t size);
+  uint8_t transfer(uint8_t data);
+  uint16_t transfer16(uint16_t data);
+  uint32_t transfer32(uint32_t data);
+
+  void transferBytes(const uint8_t *data, uint8_t *out, uint32_t size);
+  void transferBits(uint32_t data, uint32_t *out, uint8_t bits);
+
+  void write(uint8_t data);
+  void write16(uint16_t data);
+  void write32(uint32_t data);
+  void writeBytes(const uint8_t *data, uint32_t size);
+  void writePixels(const void *data, uint32_t size);  //ili9341 compatible
+  void writePattern(const uint8_t *data, uint8_t size, uint32_t repeat);
+
+  spi_t *bus() {
+    return _spi;
+  }
+  int8_t pinSS() {
+    return _ss;
+  }
 };
 
 extern SPIClass SPI;
 
-#endif
+#endif /* SOC_GPSPI_SUPPORTED */
+#endif /* _SPI_H_INCLUDED */
diff --git a/libraries/SPIFFS/examples/SPIFFS_Test/SPIFFS_Test.ino b/libraries/SPIFFS/examples/SPIFFS_Test/SPIFFS_Test.ino
index 15a71245d07..638171e359e 100644
--- a/libraries/SPIFFS/examples/SPIFFS_Test/SPIFFS_Test.ino
+++ b/libraries/SPIFFS/examples/SPIFFS_Test/SPIFFS_Test.ino
@@ -6,176 +6,174 @@
    https://github.com/me-no-dev/arduino-esp32fs-plugin */
 #define FORMAT_SPIFFS_IF_FAILED true
 
-void listDir(fs::FS &fs, const char * dirname, uint8_t levels){
-    Serial.printf("Listing directory: %s\r\n", dirname);
-
-    File root = fs.open(dirname);
-    if(!root){
-        Serial.println("- failed to open directory");
-        return;
-    }
-    if(!root.isDirectory()){
-        Serial.println(" - not a directory");
-        return;
-    }
-
-    File file = root.openNextFile();
-    while(file){
-        if(file.isDirectory()){
-            Serial.print("  DIR : ");
-            Serial.println(file.name());
-            if(levels){
-                listDir(fs, file.name(), levels -1);
-            }
-        } else {
-            Serial.print("  FILE: ");
-            Serial.print(file.name());
-            Serial.print("\tSIZE: ");
-            Serial.println(file.size());
-        }
-        file = root.openNextFile();
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\r\n", dirname);
+
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("- failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println(" - not a directory");
+    return;
+  }
+
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.println(file.name());
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
+    } else {
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("\tSIZE: ");
+      Serial.println(file.size());
     }
+    file = root.openNextFile();
+  }
 }
 
-void readFile(fs::FS &fs, const char * path){
-    Serial.printf("Reading file: %s\r\n", path);
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\r\n", path);
 
-    File file = fs.open(path);
-    if(!file || file.isDirectory()){
-        Serial.println("- failed to open file for reading");
-        return;
-    }
+  File file = fs.open(path);
+  if (!file || file.isDirectory()) {
+    Serial.println("- failed to open file for reading");
+    return;
+  }
 
-    Serial.println("- read from file:");
-    while(file.available()){
-        Serial.write(file.read());
-    }
-    file.close();
+  Serial.println("- read from file:");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
+  file.close();
 }
 
-void writeFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Writing file: %s\r\n", path);
-
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("- failed to open file for writing");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("- file written");
-    } else {
-        Serial.println("- write failed");
-    }
-    file.close();
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\r\n", path);
+
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("- failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("- file written");
+  } else {
+    Serial.println("- write failed");
+  }
+  file.close();
 }
 
-void appendFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Appending to file: %s\r\n", path);
-
-    File file = fs.open(path, FILE_APPEND);
-    if(!file){
-        Serial.println("- failed to open file for appending");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("- message appended");
-    } else {
-        Serial.println("- append failed");
-    }
-    file.close();
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\r\n", path);
+
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("- failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("- message appended");
+  } else {
+    Serial.println("- append failed");
+  }
+  file.close();
 }
 
-void renameFile(fs::FS &fs, const char * path1, const char * path2){
-    Serial.printf("Renaming file %s to %s\r\n", path1, path2);
-    if (fs.rename(path1, path2)) {
-        Serial.println("- file renamed");
-    } else {
-        Serial.println("- rename failed");
-    }
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\r\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("- file renamed");
+  } else {
+    Serial.println("- rename failed");
+  }
 }
 
-void deleteFile(fs::FS &fs, const char * path){
-    Serial.printf("Deleting file: %s\r\n", path);
-    if(fs.remove(path)){
-        Serial.println("- file deleted");
-    } else {
-        Serial.println("- delete failed");
-    }
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\r\n", path);
+  if (fs.remove(path)) {
+    Serial.println("- file deleted");
+  } else {
+    Serial.println("- delete failed");
+  }
 }
 
-void testFileIO(fs::FS &fs, const char * path){
-    Serial.printf("Testing file I/O with %s\r\n", path);
-
-    static uint8_t buf[512];
-    size_t len = 0;
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("- failed to open file for writing");
-        return;
+void testFileIO(fs::FS &fs, const char *path) {
+  Serial.printf("Testing file I/O with %s\r\n", path);
+
+  static uint8_t buf[512];
+  size_t len = 0;
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("- failed to open file for writing");
+    return;
+  }
+
+  size_t i;
+  Serial.print("- writing");
+  uint32_t start = millis();
+  for (i = 0; i < 2048; i++) {
+    if ((i & 0x001F) == 0x001F) {
+      Serial.print(".");
     }
-
-    size_t i;
-    Serial.print("- writing" );
-    uint32_t start = millis();
-    for(i=0; i<2048; i++){
-        if ((i & 0x001F) == 0x001F){
-          Serial.print(".");
-        }
-        file.write(buf, 512);
+    file.write(buf, 512);
+  }
+  Serial.println("");
+  uint32_t end = millis() - start;
+  Serial.printf(" - %u bytes written in %lu ms\r\n", 2048 * 512, end);
+  file.close();
+
+  file = fs.open(path);
+  start = millis();
+  end = start;
+  i = 0;
+  if (file && !file.isDirectory()) {
+    len = file.size();
+    size_t flen = len;
+    start = millis();
+    Serial.print("- reading");
+    while (len) {
+      size_t toRead = len;
+      if (toRead > 512) {
+        toRead = 512;
+      }
+      file.read(buf, toRead);
+      if ((i++ & 0x001F) == 0x001F) {
+        Serial.print(".");
+      }
+      len -= toRead;
     }
     Serial.println("");
-    uint32_t end = millis() - start;
-    Serial.printf(" - %u bytes written in %u ms\r\n", 2048 * 512, end);
+    end = millis() - start;
+    Serial.printf("- %u bytes read in %lu ms\r\n", flen, end);
     file.close();
-
-    file = fs.open(path);
-    start = millis();
-    end = start;
-    i = 0;
-    if(file && !file.isDirectory()){
-        len = file.size();
-        size_t flen = len;
-        start = millis();
-        Serial.print("- reading" );
-        while(len){
-            size_t toRead = len;
-            if(toRead > 512){
-                toRead = 512;
-            }
-            file.read(buf, toRead);
-            if ((i++ & 0x001F) == 0x001F){
-              Serial.print(".");
-            }
-            len -= toRead;
-        }
-        Serial.println("");
-        end = millis() - start;
-        Serial.printf("- %u bytes read in %u ms\r\n", flen, end);
-        file.close();
-    } else {
-        Serial.println("- failed to open file for reading");
-    }
+  } else {
+    Serial.println("- failed to open file for reading");
+  }
 }
 
-void setup(){
-    Serial.begin(115200);
-    if(!SPIFFS.begin(FORMAT_SPIFFS_IF_FAILED)){
-        Serial.println("SPIFFS Mount Failed");
-        return;
-    }
-    
-    listDir(SPIFFS, "/", 0);
-    writeFile(SPIFFS, "/hello.txt", "Hello ");
-    appendFile(SPIFFS, "/hello.txt", "World!\r\n");
-    readFile(SPIFFS, "/hello.txt");
-    renameFile(SPIFFS, "/hello.txt", "/foo.txt");
-    readFile(SPIFFS, "/foo.txt");
-    deleteFile(SPIFFS, "/foo.txt");
-    testFileIO(SPIFFS, "/test.txt");
-    deleteFile(SPIFFS, "/test.txt");
-    Serial.println( "Test complete" );
+void setup() {
+  Serial.begin(115200);
+  if (!SPIFFS.begin(FORMAT_SPIFFS_IF_FAILED)) {
+    Serial.println("SPIFFS Mount Failed");
+    return;
+  }
+
+  listDir(SPIFFS, "/", 0);
+  writeFile(SPIFFS, "/hello.txt", "Hello ");
+  appendFile(SPIFFS, "/hello.txt", "World!\r\n");
+  readFile(SPIFFS, "/hello.txt");
+  renameFile(SPIFFS, "/hello.txt", "/foo.txt");
+  readFile(SPIFFS, "/foo.txt");
+  deleteFile(SPIFFS, "/foo.txt");
+  testFileIO(SPIFFS, "/test.txt");
+  deleteFile(SPIFFS, "/test.txt");
+  Serial.println("Test complete");
 }
 
-void loop(){
-
-}
+void loop() {}
diff --git a/libraries/SPIFFS/examples/SPIFFS_time/SPIFFS_time.ino b/libraries/SPIFFS/examples/SPIFFS_time/SPIFFS_time.ino
index 958e805ee95..78a66a94e75 100644
--- a/libraries/SPIFFS/examples/SPIFFS_time/SPIFFS_time.ino
+++ b/libraries/SPIFFS/examples/SPIFFS_time/SPIFFS_time.ino
@@ -1,177 +1,182 @@
 #include "FS.h"
 #include "SPIFFS.h"
-#include <time.h> 
+#include <time.h>
 #include <WiFi.h>
 
-const char* ssid     = "your-ssid";
-const char* password = "your-password";
+const char *ssid = "your-ssid";
+const char *password = "your-password";
 
-long timezone = 1; 
+long timezone = 1;
 byte daysavetime = 1;
 
-void listDir(fs::FS &fs, const char * dirname, uint8_t levels){
-    Serial.printf("Listing directory: %s\n", dirname);
-
-    File root = fs.open(dirname);
-    if(!root){
-        Serial.println("Failed to open directory");
-        return;
-    }
-    if(!root.isDirectory()){
-        Serial.println("Not a directory");
-        return;
-    }
-
-    File file = root.openNextFile();
-    while(file){
-        if(file.isDirectory()){
-            Serial.print("  DIR : ");
-            Serial.print (file.name());
-            time_t t= file.getLastWrite();
-            struct tm * tmstruct = localtime(&t);
-            Serial.printf("  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct->tm_year)+1900,( tmstruct->tm_mon)+1, tmstruct->tm_mday,tmstruct->tm_hour , tmstruct->tm_min, tmstruct->tm_sec);
-            if(levels){
-                listDir(fs, file.name(), levels -1);
-            }
-        } else {
-            Serial.print("  FILE: ");
-            Serial.print(file.name());
-            Serial.print("  SIZE: ");
-            Serial.print(file.size());
-            time_t t= file.getLastWrite();
-            struct tm * tmstruct = localtime(&t);
-            Serial.printf("  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct->tm_year)+1900,( tmstruct->tm_mon)+1, tmstruct->tm_mday,tmstruct->tm_hour , tmstruct->tm_min, tmstruct->tm_sec);
-        }
-        file = root.openNextFile();
-    }
-}
-
-void createDir(fs::FS &fs, const char * path){
-    Serial.printf("Creating Dir: %s\n", path);
-    if(fs.mkdir(path)){
-        Serial.println("Dir created");
+void listDir(fs::FS &fs, const char *dirname, uint8_t levels) {
+  Serial.printf("Listing directory: %s\n", dirname);
+
+  File root = fs.open(dirname);
+  if (!root) {
+    Serial.println("Failed to open directory");
+    return;
+  }
+  if (!root.isDirectory()) {
+    Serial.println("Not a directory");
+    return;
+  }
+
+  File file = root.openNextFile();
+  while (file) {
+    if (file.isDirectory()) {
+      Serial.print("  DIR : ");
+      Serial.print(file.name());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
+      if (levels) {
+        listDir(fs, file.path(), levels - 1);
+      }
     } else {
-        Serial.println("mkdir failed");
+      Serial.print("  FILE: ");
+      Serial.print(file.name());
+      Serial.print("  SIZE: ");
+      Serial.print(file.size());
+      time_t t = file.getLastWrite();
+      struct tm *tmstruct = localtime(&t);
+      Serial.printf(
+        "  LAST WRITE: %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct->tm_year) + 1900, (tmstruct->tm_mon) + 1, tmstruct->tm_mday, tmstruct->tm_hour,
+        tmstruct->tm_min, tmstruct->tm_sec
+      );
     }
+    file = root.openNextFile();
+  }
 }
 
-void removeDir(fs::FS &fs, const char * path){
-    Serial.printf("Removing Dir: %s\n", path);
-    if(fs.rmdir(path)){
-        Serial.println("Dir removed");
-    } else {
-        Serial.println("rmdir failed");
-    }
+void createDir(fs::FS &fs, const char *path) {
+  Serial.printf("Creating Dir: %s\n", path);
+  if (fs.mkdir(path)) {
+    Serial.println("Dir created");
+  } else {
+    Serial.println("mkdir failed");
+  }
 }
 
-void readFile(fs::FS &fs, const char * path){
-    Serial.printf("Reading file: %s\n", path);
-
-    File file = fs.open(path);
-    if(!file){
-        Serial.println("Failed to open file for reading");
-        return;
-    }
-
-    Serial.print("Read from file: ");
-    while(file.available()){
-        Serial.write(file.read());
-    }
-    file.close();
+void removeDir(fs::FS &fs, const char *path) {
+  Serial.printf("Removing Dir: %s\n", path);
+  if (fs.rmdir(path)) {
+    Serial.println("Dir removed");
+  } else {
+    Serial.println("rmdir failed");
+  }
 }
 
-void writeFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Writing file: %s\n", path);
-
-    File file = fs.open(path, FILE_WRITE);
-    if(!file){
-        Serial.println("Failed to open file for writing");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("File written");
-    } else {
-        Serial.println("Write failed");
-    }
-    file.close();
-}
+void readFile(fs::FS &fs, const char *path) {
+  Serial.printf("Reading file: %s\n", path);
 
-void appendFile(fs::FS &fs, const char * path, const char * message){
-    Serial.printf("Appending to file: %s\n", path);
+  File file = fs.open(path);
+  if (!file) {
+    Serial.println("Failed to open file for reading");
+    return;
+  }
 
-    File file = fs.open(path, FILE_APPEND);
-    if(!file){
-        Serial.println("Failed to open file for appending");
-        return;
-    }
-    if(file.print(message)){
-        Serial.println("Message appended");
-    } else {
-        Serial.println("Append failed");
-    }
-    file.close();
+  Serial.print("Read from file: ");
+  while (file.available()) {
+    Serial.write(file.read());
+  }
+  file.close();
 }
 
-void renameFile(fs::FS &fs, const char * path1, const char * path2){
-    Serial.printf("Renaming file %s to %s\n", path1, path2);
-    if (fs.rename(path1, path2)) {
-        Serial.println("File renamed");
-    } else {
-        Serial.println("Rename failed");
-    }
+void writeFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Writing file: %s\n", path);
+
+  File file = fs.open(path, FILE_WRITE);
+  if (!file) {
+    Serial.println("Failed to open file for writing");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("File written");
+  } else {
+    Serial.println("Write failed");
+  }
+  file.close();
 }
 
-void deleteFile(fs::FS &fs, const char * path){
-    Serial.printf("Deleting file: %s\n", path);
-    if(fs.remove(path)){
-        Serial.println("File deleted");
-    } else {
-        Serial.println("Delete failed");
-    }
+void appendFile(fs::FS &fs, const char *path, const char *message) {
+  Serial.printf("Appending to file: %s\n", path);
+
+  File file = fs.open(path, FILE_APPEND);
+  if (!file) {
+    Serial.println("Failed to open file for appending");
+    return;
+  }
+  if (file.print(message)) {
+    Serial.println("Message appended");
+  } else {
+    Serial.println("Append failed");
+  }
+  file.close();
 }
 
-void setup(){
-    Serial.begin(115200);
-    // We start by connecting to a WiFi network
-    Serial.println();
-    Serial.println();
-    Serial.print("Connecting to ");
-    Serial.println(ssid);
-
-    WiFi.begin(ssid, password);
-
-    while (WiFi.status() != WL_CONNECTED) {
-        delay(500);
-        Serial.print(".");
-    }
-    Serial.println("WiFi connected");
-    Serial.println("IP address: ");
-    Serial.println(WiFi.localIP());
-    Serial.println("Contacting Time Server");
-	configTime(3600*timezone, daysavetime*3600, "time.nist.gov", "0.pool.ntp.org", "1.pool.ntp.org");
-	struct tm tmstruct ;
-    delay(2000);
-    tmstruct.tm_year = 0;
-    getLocalTime(&tmstruct, 5000);
-	Serial.printf("\nNow is : %d-%02d-%02d %02d:%02d:%02d\n",(tmstruct.tm_year)+1900,( tmstruct.tm_mon)+1, tmstruct.tm_mday,tmstruct.tm_hour , tmstruct.tm_min, tmstruct.tm_sec);
-    Serial.println("");
-    
-    if(!SPIFFS.begin()){
-        Serial.println("Card Mount Failed");
-        return;
-    }
-
-    listDir(SPIFFS, "/", 0);
-    removeDir(SPIFFS, "/mydir");
-    createDir(SPIFFS, "/mydir");
-    deleteFile(SPIFFS, "/hello.txt");
-    writeFile(SPIFFS, "/hello.txt", "Hello ");
-    appendFile(SPIFFS, "/hello.txt", "World!\n");
-	listDir(SPIFFS, "/", 0);
+void renameFile(fs::FS &fs, const char *path1, const char *path2) {
+  Serial.printf("Renaming file %s to %s\n", path1, path2);
+  if (fs.rename(path1, path2)) {
+    Serial.println("File renamed");
+  } else {
+    Serial.println("Rename failed");
+  }
 }
 
-void loop(){
-
+void deleteFile(fs::FS &fs, const char *path) {
+  Serial.printf("Deleting file: %s\n", path);
+  if (fs.remove(path)) {
+    Serial.println("File deleted");
+  } else {
+    Serial.println("Delete failed");
+  }
 }
 
+void setup() {
+  Serial.begin(115200);
+  // We start by connecting to a WiFi network
+  Serial.println();
+  Serial.println();
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+
+  WiFi.begin(ssid, password);
+
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+  Serial.println("Contacting Time Server");
+  configTime(3600 * timezone, daysavetime * 3600, "time.nist.gov", "0.pool.ntp.org", "1.pool.ntp.org");
+  struct tm tmstruct;
+  delay(2000);
+  tmstruct.tm_year = 0;
+  getLocalTime(&tmstruct, 5000);
+  Serial.printf(
+    "\nNow is : %d-%02d-%02d %02d:%02d:%02d\n", (tmstruct.tm_year) + 1900, (tmstruct.tm_mon) + 1, tmstruct.tm_mday, tmstruct.tm_hour, tmstruct.tm_min,
+    tmstruct.tm_sec
+  );
+  Serial.println("");
+
+  if (!SPIFFS.begin()) {
+    Serial.println("Card Mount Failed");
+    return;
+  }
+
+  listDir(SPIFFS, "/", 0);
+  removeDir(SPIFFS, "/mydir");
+  createDir(SPIFFS, "/mydir");
+  deleteFile(SPIFFS, "/hello.txt");
+  writeFile(SPIFFS, "/hello.txt", "Hello ");
+  appendFile(SPIFFS, "/hello.txt", "World!\n");
+  listDir(SPIFFS, "/", 0);
+}
 
+void loop() {}
diff --git a/libraries/SPIFFS/examples/SPIFFS_time/ci.json b/libraries/SPIFFS/examples/SPIFFS_time/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/SPIFFS/examples/SPIFFS_time/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/SPIFFS/library.properties b/libraries/SPIFFS/library.properties
index 9b011e50cc7..78f77fe9794 100644
--- a/libraries/SPIFFS/library.properties
+++ b/libraries/SPIFFS/library.properties
@@ -1,5 +1,5 @@
 name=SPIFFS
-version=1.0
+version=3.2.0
 author=Hristo Gochkov, Ivan Grokhtkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=ESP32 SPIFFS File System
diff --git a/libraries/SPIFFS/src/SPIFFS.cpp b/libraries/SPIFFS/src/SPIFFS.cpp
index d3e1665491a..0b2cc0d462d 100644
--- a/libraries/SPIFFS/src/SPIFFS.cpp
+++ b/libraries/SPIFFS/src/SPIFFS.cpp
@@ -25,115 +25,98 @@ extern "C" {
 
 using namespace fs;
 
-class SPIFFSImpl : public VFSImpl
-{
+class SPIFFSImpl : public VFSImpl {
 public:
-    SPIFFSImpl();
-    virtual ~SPIFFSImpl() { }
-    virtual bool exists(const char* path);
+  SPIFFSImpl();
+  virtual ~SPIFFSImpl() {}
+  virtual bool exists(const char *path);
 };
 
-SPIFFSImpl::SPIFFSImpl()
-{
-}
+SPIFFSImpl::SPIFFSImpl() {}
 
-bool SPIFFSImpl::exists(const char* path)
-{
-    File f = open(path, "r");
-    return (f == true) && !f.isDirectory();
+bool SPIFFSImpl::exists(const char *path) {
+  File f = open(path, "r", false);
+  return (f == true) && !f.isDirectory();
 }
 
-SPIFFSFS::SPIFFSFS() : FS(FSImplPtr(new SPIFFSImpl())), partitionLabel_(NULL)
-{
+SPIFFSFS::SPIFFSFS() : FS(FSImplPtr(new SPIFFSImpl())), partitionLabel_(NULL) {}
 
+SPIFFSFS::~SPIFFSFS() {
+  if (partitionLabel_) {
+    free(partitionLabel_);
+    partitionLabel_ = NULL;
+  }
 }
 
-SPIFFSFS::~SPIFFSFS()
-{
-    if (partitionLabel_){
-        free(partitionLabel_);
-        partitionLabel_ = NULL;
-    }
-}
+bool SPIFFSFS::begin(bool formatOnFail, const char *basePath, uint8_t maxOpenFiles, const char *partitionLabel) {
+  if (partitionLabel_) {
+    free(partitionLabel_);
+    partitionLabel_ = NULL;
+  }
 
-bool SPIFFSFS::begin(bool formatOnFail, const char * basePath, uint8_t maxOpenFiles, const char * partitionLabel)
-{
-    if (partitionLabel_){
-        free(partitionLabel_);
-        partitionLabel_ = NULL;
-    }
+  if (partitionLabel) {
+    partitionLabel_ = strdup(partitionLabel);
+  }
 
-    if (partitionLabel){
-        partitionLabel_ = strdup(partitionLabel);
-    }
+  if (esp_spiffs_mounted(partitionLabel_)) {
+    log_w("SPIFFS Already Mounted!");
+    return true;
+  }
 
-    if(esp_spiffs_mounted(partitionLabel_)){
-        log_w("SPIFFS Already Mounted!");
-        return true;
-    }
+  esp_vfs_spiffs_conf_t conf = {.base_path = basePath, .partition_label = partitionLabel_, .max_files = maxOpenFiles, .format_if_mount_failed = false};
 
-    esp_vfs_spiffs_conf_t conf = {
-      .base_path = basePath,
-      .partition_label = partitionLabel_,
-      .max_files = maxOpenFiles,
-      .format_if_mount_failed = false
-    };
-
-    esp_err_t err = esp_vfs_spiffs_register(&conf);
-    if(err == ESP_FAIL && formatOnFail){
-        if(format()){
-            err = esp_vfs_spiffs_register(&conf);
-        }
+  esp_err_t err = esp_vfs_spiffs_register(&conf);
+  if (err == ESP_FAIL && formatOnFail) {
+    if (format()) {
+      err = esp_vfs_spiffs_register(&conf);
     }
-    if(err != ESP_OK){
-        log_e("Mounting SPIFFS failed! Error: %d", err);
-        return false;
-    }
-    _impl->mountpoint(basePath);
-    return true;
+  }
+  if (err != ESP_OK) {
+    log_e("Mounting SPIFFS failed! Error: %d", err);
+    return false;
+  }
+  _impl->mountpoint(basePath);
+  return true;
 }
 
-void SPIFFSFS::end()
-{
-    if(esp_spiffs_mounted(partitionLabel_)){
-        esp_err_t err = esp_vfs_spiffs_unregister(partitionLabel_);
-        if(err){
-            log_e("Unmounting SPIFFS failed! Error: %d", err);
-            return;
-        }
-        _impl->mountpoint(NULL);
+void SPIFFSFS::end() {
+  if (esp_spiffs_mounted(partitionLabel_)) {
+    esp_err_t err = esp_vfs_spiffs_unregister(partitionLabel_);
+    if (err) {
+      log_e("Unmounting SPIFFS failed! Error: %d", err);
+      return;
     }
+    _impl->mountpoint(NULL);
+  }
 }
 
-bool SPIFFSFS::format()
-{
-    disableCore0WDT();
-    esp_err_t err = esp_spiffs_format(partitionLabel_);
+bool SPIFFSFS::format() {
+  bool wdt_active = disableCore0WDT();
+  esp_err_t err = esp_spiffs_format(partitionLabel_);
+  if (wdt_active) {
     enableCore0WDT();
-    if(err){
-        log_e("Formatting SPIFFS failed! Error: %d", err);
-        return false;
-    }
-    return true;
+  }
+  if (err) {
+    log_e("Formatting SPIFFS failed! Error: %d", err);
+    return false;
+  }
+  return true;
 }
 
-size_t SPIFFSFS::totalBytes()
-{
-    size_t total,used;
-    if(esp_spiffs_info(partitionLabel_, &total, &used)){
-        return 0;
-    }
-    return total;
+size_t SPIFFSFS::totalBytes() {
+  size_t total, used;
+  if (esp_spiffs_info(partitionLabel_, &total, &used)) {
+    return 0;
+  }
+  return total;
 }
 
-size_t SPIFFSFS::usedBytes()
-{
-    size_t total,used;
-    if(esp_spiffs_info(partitionLabel_, &total, &used)){
-        return 0;
-    }
-    return used;
+size_t SPIFFSFS::usedBytes() {
+  size_t total, used;
+  if (esp_spiffs_info(partitionLabel_, &total, &used)) {
+    return 0;
+  }
+  return used;
 }
 
 SPIFFSFS SPIFFS;
-
diff --git a/libraries/SPIFFS/src/SPIFFS.h b/libraries/SPIFFS/src/SPIFFS.h
index 4d7eb5da688..2e7bf6de7d8 100644
--- a/libraries/SPIFFS/src/SPIFFS.h
+++ b/libraries/SPIFFS/src/SPIFFS.h
@@ -16,27 +16,24 @@
 
 #include "FS.h"
 
-namespace fs
-{
+namespace fs {
 
-class SPIFFSFS : public FS
-{
+class SPIFFSFS : public FS {
 public:
-    SPIFFSFS();
-    ~SPIFFSFS();
-    bool begin(bool formatOnFail=false, const char * basePath="/spiffs", uint8_t maxOpenFiles=10, const char * partitionLabel=NULL);
-    bool format();
-    size_t totalBytes();
-    size_t usedBytes();
-    void end();
+  SPIFFSFS();
+  ~SPIFFSFS();
+  bool begin(bool formatOnFail = false, const char *basePath = "/spiffs", uint8_t maxOpenFiles = 10, const char *partitionLabel = NULL);
+  bool format();
+  size_t totalBytes();
+  size_t usedBytes();
+  void end();
 
 private:
-    char * partitionLabel_;
+  char *partitionLabel_;
 };
 
-}
+}  // namespace fs
 
 extern fs::SPIFFSFS SPIFFS;
 
-
 #endif
diff --git a/libraries/SimpleBLE/examples/SimpleBleDevice/SimpleBleDevice.ino b/libraries/SimpleBLE/examples/SimpleBleDevice/SimpleBleDevice.ino
index 3a9825a6b84..a92e576196d 100644
--- a/libraries/SimpleBLE/examples/SimpleBleDevice/SimpleBleDevice.ino
+++ b/libraries/SimpleBLE/examples/SimpleBleDevice/SimpleBleDevice.ino
@@ -24,29 +24,31 @@
 
 SimpleBLE ble;
 
-void onButton(){
-    String out = "BLE32 name: ";
-    out += String(millis() / 1000);
-    Serial.println(out);
-    ble.begin(out);
+void onButton() {
+  String out = "BLE32 name: ";
+  out += String(millis() / 1000);
+  Serial.println(out);
+  ble.begin(out);
 }
 
 void setup() {
-    Serial.begin(115200);
-    Serial.setDebugOutput(true);
-    pinMode(0, INPUT_PULLUP);
-    Serial.print("ESP32 SDK: ");
-    Serial.println(ESP.getSdkVersion());
-    ble.begin("ESP32 SimpleBLE");
-    Serial.println("Press the button to change the device's name");
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+  pinMode(0, INPUT_PULLUP);
+  Serial.print("ESP32 SDK: ");
+  Serial.println(ESP.getSdkVersion());
+  ble.begin("ESP32 SimpleBLE");
+  Serial.println("Press the button to change the device's name");
 }
 
 void loop() {
-    static uint8_t lastPinState = 1;
-    uint8_t pinState = digitalRead(0);
-    if(!pinState && lastPinState){
-        onButton();
-    }
-    lastPinState = pinState;
-    while(Serial.available()) Serial.write(Serial.read());
+  static uint8_t lastPinState = 1;
+  uint8_t pinState = digitalRead(0);
+  if (!pinState && lastPinState) {
+    onButton();
+  }
+  lastPinState = pinState;
+  while (Serial.available()) {
+    Serial.write(Serial.read());
+  }
 }
diff --git a/libraries/SimpleBLE/examples/SimpleBleDevice/ci.json b/libraries/SimpleBLE/examples/SimpleBleDevice/ci.json
new file mode 100644
index 00000000000..d33a23f332e
--- /dev/null
+++ b/libraries/SimpleBLE/examples/SimpleBleDevice/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires": [
+    "CONFIG_BT_ENABLED=y",
+    "CONFIG_BLUEDROID_ENABLED=y"
+  ]
+}
diff --git a/libraries/SimpleBLE/library.properties b/libraries/SimpleBLE/library.properties
index ec28494cdbb..ad5e10d3acb 100644
--- a/libraries/SimpleBLE/library.properties
+++ b/libraries/SimpleBLE/library.properties
@@ -1,5 +1,5 @@
 name=SimpleBLE
-version=1.0
+version=3.2.0
 author=Hristo Gochkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=Provides really simple BLE advertizer with just on and off
diff --git a/libraries/SimpleBLE/src/SimpleBLE.cpp b/libraries/SimpleBLE/src/SimpleBLE.cpp
index d30a177fdf2..3c4ed915c05 100644
--- a/libraries/SimpleBLE/src/SimpleBLE.cpp
+++ b/libraries/SimpleBLE/src/SimpleBLE.cpp
@@ -26,79 +26,81 @@
 #include "esp_bt_main.h"
 
 static esp_ble_adv_data_t _adv_config = {
-        .set_scan_rsp        = false,
-        .include_name        = true,
-        .include_txpower     = true,
-        .min_interval        = 512,
-        .max_interval        = 1024,
-        .appearance          = 0,
-        .manufacturer_len    = 0,
-        .p_manufacturer_data = NULL,
-        .service_data_len    = 0,
-        .p_service_data      = NULL,
-        .service_uuid_len    = 0,
-        .p_service_uuid      = NULL,
-        .flag                = (ESP_BLE_ADV_FLAG_GEN_DISC|ESP_BLE_ADV_FLAG_BREDR_NOT_SPT)
+  .set_scan_rsp = false,
+  .include_name = true,
+  .include_txpower = true,
+  .min_interval = 512,
+  .max_interval = 1024,
+  .appearance = 0,
+  .manufacturer_len = 0,
+  .p_manufacturer_data = NULL,
+  .service_data_len = 0,
+  .p_service_data = NULL,
+  .service_uuid_len = 0,
+  .p_service_uuid = NULL,
+  .flag = (ESP_BLE_ADV_FLAG_GEN_DISC | ESP_BLE_ADV_FLAG_BREDR_NOT_SPT)
 };
 
 static esp_ble_adv_params_t _adv_params = {
-        .adv_int_min         = 512,
-        .adv_int_max         = 1024,
-        .adv_type            = ADV_TYPE_NONCONN_IND,
-        .own_addr_type       = BLE_ADDR_TYPE_PUBLIC,
-        .peer_addr           = {0x00, },
-        .peer_addr_type      = BLE_ADDR_TYPE_PUBLIC,
-        .channel_map         = ADV_CHNL_ALL,
-        .adv_filter_policy   = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY,
+  .adv_int_min = 512,
+  .adv_int_max = 1024,
+  .adv_type = ADV_TYPE_NONCONN_IND,
+  .own_addr_type = BLE_ADDR_TYPE_PUBLIC,
+  .peer_addr =
+    {
+      0x00,
+    },
+  .peer_addr_type = BLE_ADDR_TYPE_PUBLIC,
+  .channel_map = ADV_CHNL_ALL,
+  .adv_filter_policy = ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY,
 };
 
-static void _on_gap(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param){
-    if(event == ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT){
-        esp_ble_gap_start_advertising(&_adv_params);
-    }
+static void _on_gap(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param) {
+  if (event == ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT) {
+    esp_ble_gap_start_advertising(&_adv_params);
+  }
 }
 
-static bool _init_gap(const char * name){
-    if(!btStarted() && !btStart()){
-        log_e("btStart failed");
-        return false;
-    }
-    esp_bluedroid_status_t bt_state = esp_bluedroid_get_status();
-    if(bt_state == ESP_BLUEDROID_STATUS_UNINITIALIZED){
-        if (esp_bluedroid_init()) {
-            log_e("esp_bluedroid_init failed");
-            return false;
-        }
-    }
-    if(bt_state != ESP_BLUEDROID_STATUS_ENABLED){
-        if (esp_bluedroid_enable()) {
-            log_e("esp_bluedroid_enable failed");
-            return false;
-        }
-    }
-    if(esp_ble_gap_set_device_name(name)){
-        log_e("gap_set_device_name failed");
-        return false;
+static bool _init_gap(const char *name) {
+  if (!btStarted() && !btStart()) {
+    log_e("btStart failed");
+    return false;
+  }
+  esp_bluedroid_status_t bt_state = esp_bluedroid_get_status();
+  if (bt_state == ESP_BLUEDROID_STATUS_UNINITIALIZED) {
+    if (esp_bluedroid_init()) {
+      log_e("esp_bluedroid_init failed");
+      return false;
     }
-    if(esp_ble_gap_config_adv_data(&_adv_config)){
-        log_e("gap_config_adv_data failed");
-        return false;
+  }
+  if (bt_state != ESP_BLUEDROID_STATUS_ENABLED) {
+    if (esp_bluedroid_enable()) {
+      log_e("esp_bluedroid_enable failed");
+      return false;
     }
-    if(esp_ble_gap_register_callback(_on_gap)){
-        log_e("gap_register_callback failed");
-        return false;
-    }
-    return true;
+  }
+  if (esp_ble_gap_set_device_name(name)) {
+    log_e("gap_set_device_name failed");
+    return false;
+  }
+  if (esp_ble_gap_config_adv_data(&_adv_config)) {
+    log_e("gap_config_adv_data failed");
+    return false;
+  }
+  if (esp_ble_gap_register_callback(_on_gap)) {
+    log_e("gap_register_callback failed");
+    return false;
+  }
+  return true;
 }
 
-static bool _stop_gap()
-{
-    if(btStarted()){
-        esp_bluedroid_disable();
-        esp_bluedroid_deinit();
-        btStop();
-    }
-    return true;
+static bool _stop_gap() {
+  if (btStarted()) {
+    esp_bluedroid_disable();
+    esp_bluedroid_deinit();
+    btStop();
+  }
+  return true;
 }
 
 /*
@@ -106,27 +108,23 @@ static bool _stop_gap()
  *
  * */
 
-SimpleBLE::SimpleBLE()
-{
-    local_name = "esp32";
+SimpleBLE::SimpleBLE() {
+  local_name = "esp32";
 }
 
-SimpleBLE::~SimpleBLE(void)
-{
-    _stop_gap();
+SimpleBLE::~SimpleBLE(void) {
+  _stop_gap();
 }
 
-bool SimpleBLE::begin(String localName)
-{
-    if(localName.length()){
-        local_name = localName;
-    }
-    return _init_gap(local_name.c_str());
+bool SimpleBLE::begin(String localName) {
+  if (localName.length()) {
+    local_name = localName;
+  }
+  return _init_gap(local_name.c_str());
 }
 
-void SimpleBLE::end()
-{
-    _stop_gap();
+void SimpleBLE::end() {
+  _stop_gap();
 }
 
 #endif
diff --git a/libraries/SimpleBLE/src/SimpleBLE.h b/libraries/SimpleBLE/src/SimpleBLE.h
index 6e7b702da5a..23c1cdb593f 100644
--- a/libraries/SimpleBLE/src/SimpleBLE.h
+++ b/libraries/SimpleBLE/src/SimpleBLE.h
@@ -32,12 +32,11 @@
 struct ble_gap_adv_params_s;
 
 class SimpleBLE {
-    public:
+public:
+  SimpleBLE(void);
+  ~SimpleBLE(void);
 
-        SimpleBLE(void);
-        ~SimpleBLE(void);
-
-        /**
+  /**
          * Start BLE Advertising
          *
          * @param[in] localName  local name to advertise
@@ -45,19 +44,19 @@ class SimpleBLE {
          * @return true on success
          *
          */
-        bool begin(String localName=String());
+  bool begin(String localName = String());
 
-        /**
+  /**
          * Stop BLE Advertising
          *
          * @return none
          */
-        void end(void);
+  void end(void);
 
-    private:
-        String local_name;
-    private:
+private:
+  String local_name;
 
+private:
 };
 
 #endif
diff --git a/libraries/TFLiteMicro/examples/hello_world/README.md b/libraries/TFLiteMicro/examples/hello_world/README.md
new file mode 100644
index 00000000000..6fadc59a176
--- /dev/null
+++ b/libraries/TFLiteMicro/examples/hello_world/README.md
@@ -0,0 +1,18 @@
+# Hello World Example
+
+This example is designed to demonstrate the absolute basics of using [TensorFlow
+Lite for Microcontrollers](https://www.tensorflow.org/lite/microcontrollers).
+It includes the full end-to-end workflow of training a model, converting it for
+use with TensorFlow Lite for Microcontrollers for running inference on a
+microcontroller.
+
+The model is trained to replicate a `sine` function and generates a pattern of
+data to either blink LEDs or control an animation, depending on the capabilities
+of the device.
+
+## Deploy to ESP32
+
+The sample has been tested on ESP-IDF version `release/v4.2` and `release/v4.4` with the following devices:
+- [ESP32-DevKitC](http://esp-idf.readthedocs.io/en/latest/get-started/get-started-devkitc.html)
+- [ESP32-S3-DevKitC](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html)
+- [ESP-EYE](https://github.com/espressif/esp-who/blob/master/docs/en/get-started/ESP-EYE_Getting_Started_Guide.md)
diff --git a/libraries/TFLiteMicro/examples/hello_world/constants.cpp b/libraries/TFLiteMicro/examples/hello_world/constants.cpp
new file mode 100644
index 00000000000..bc32fc3f9c0
--- /dev/null
+++ b/libraries/TFLiteMicro/examples/hello_world/constants.cpp
@@ -0,0 +1,19 @@
+/* Copyright 2019 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#include "constants.h"
+
+// This is a small number so that it's easy to read the logs
+const int kInferencesPerCycle = 20;
diff --git a/libraries/TFLiteMicro/examples/hello_world/constants.h b/libraries/TFLiteMicro/examples/hello_world/constants.h
new file mode 100644
index 00000000000..f452893209d
--- /dev/null
+++ b/libraries/TFLiteMicro/examples/hello_world/constants.h
@@ -0,0 +1,32 @@
+/* Copyright 2019 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#ifndef TENSORFLOW_LITE_MICRO_EXAMPLES_HELLO_WORLD_CONSTANTS_H_
+#define TENSORFLOW_LITE_MICRO_EXAMPLES_HELLO_WORLD_CONSTANTS_H_
+
+// This constant represents the range of x values our model was trained on,
+// which is from 0 to (2 * Pi). We approximate Pi to avoid requiring additional
+// libraries.
+const float kXrange = 2.f * 3.14159265359f;
+
+// This constant determines the number of inferences to perform across the range
+// of x values defined above. Since each inference takes time, the higher this
+// number, the more time it will take to run through the entire range. The value
+// of this constant can be tuned so that one full cycle takes a desired amount
+// of time. Since different devices take different amounts of time to perform
+// inference, this value should be defined per-device.
+extern const int kInferencesPerCycle;
+
+#endif  // TENSORFLOW_LITE_MICRO_EXAMPLES_HELLO_WORLD_CONSTANTS_H_
diff --git a/libraries/TFLiteMicro/examples/hello_world/hello_world.ino b/libraries/TFLiteMicro/examples/hello_world/hello_world.ino
new file mode 100644
index 00000000000..90dc91b9383
--- /dev/null
+++ b/libraries/TFLiteMicro/examples/hello_world/hello_world.ino
@@ -0,0 +1,112 @@
+/* Copyright 2020 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#include "tensorflow/lite/micro/micro_mutable_op_resolver.h"
+#include "tensorflow/lite/micro/micro_interpreter.h"
+#include "tensorflow/lite/micro/system_setup.h"
+#include "tensorflow/lite/schema/schema_generated.h"
+
+#include "model.h"
+#include "constants.h"
+#include "output_handler.h"
+
+// Globals, used for compatibility with Arduino-style sketches.
+namespace {
+const tflite::Model *model = nullptr;
+tflite::MicroInterpreter *interpreter = nullptr;
+TfLiteTensor *input = nullptr;
+TfLiteTensor *output = nullptr;
+int inference_count = 0;
+
+constexpr int kTensorArenaSize = 2000;
+uint8_t tensor_arena[kTensorArenaSize];
+}  // namespace
+
+// The name of this function is important for Arduino compatibility.
+void setup() {
+  // Map the model into a usable data structure. This doesn't involve any
+  // copying or parsing, it's a very lightweight operation.
+  model = tflite::GetModel(g_model);
+  if (model->version() != TFLITE_SCHEMA_VERSION) {
+    MicroPrintf(
+      "Model provided is schema version %d not equal to supported "
+      "version %d.",
+      model->version(), TFLITE_SCHEMA_VERSION
+    );
+    return;
+  }
+
+  // Pull in only the operation implementations we need.
+  static tflite::MicroMutableOpResolver<1> resolver;
+  if (resolver.AddFullyConnected() != kTfLiteOk) {
+    return;
+  }
+
+  // Build an interpreter to run the model with.
+  static tflite::MicroInterpreter static_interpreter(model, resolver, tensor_arena, kTensorArenaSize);
+  interpreter = &static_interpreter;
+
+  // Allocate memory from the tensor_arena for the model's tensors.
+  TfLiteStatus allocate_status = interpreter->AllocateTensors();
+  if (allocate_status != kTfLiteOk) {
+    MicroPrintf("AllocateTensors() failed");
+    return;
+  }
+
+  // Obtain pointers to the model's input and output tensors.
+  input = interpreter->input(0);
+  output = interpreter->output(0);
+
+  // Keep track of how many inferences we have performed.
+  inference_count = 0;
+}
+
+// The name of this function is important for Arduino compatibility.
+void loop() {
+  // Calculate an x value to feed into the model. We compare the current
+  // inference_count to the number of inferences per cycle to determine
+  // our position within the range of possible x values the model was
+  // trained on, and use this to calculate a value.
+  float position = static_cast<float>(inference_count) / static_cast<float>(kInferencesPerCycle);
+  float x = position * kXrange;
+
+  // Quantize the input from floating-point to integer
+  int8_t x_quantized = x / input->params.scale + input->params.zero_point;
+  // Place the quantized input in the model's input tensor
+  input->data.int8[0] = x_quantized;
+
+  // Run inference, and report any error
+  TfLiteStatus invoke_status = interpreter->Invoke();
+  if (invoke_status != kTfLiteOk) {
+    MicroPrintf("Invoke failed on x: %f\n", static_cast<double>(x));
+    return;
+  }
+
+  // Obtain the quantized output from model's output tensor
+  int8_t y_quantized = output->data.int8[0];
+  // Dequantize the output from integer to floating-point
+  float y = (y_quantized - output->params.zero_point) * output->params.scale;
+
+  // Output the results. A custom HandleOutput function can be implemented
+  // for each supported hardware target.
+  HandleOutput(x, y);
+
+  // Increment the inference_counter, and reset it if we have reached
+  // the total number per cycle
+  inference_count += 1;
+  if (inference_count >= kInferencesPerCycle) {
+    inference_count = 0;
+  }
+}
diff --git a/libraries/TFLiteMicro/examples/hello_world/model.cpp b/libraries/TFLiteMicro/examples/hello_world/model.cpp
new file mode 100644
index 00000000000..8dc169724c3
--- /dev/null
+++ b/libraries/TFLiteMicro/examples/hello_world/model.cpp
@@ -0,0 +1,126 @@
+/* Copyright 2020 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// Automatically created from a TensorFlow Lite flatbuffer using the command:
+// xxd -i model.tflite > model.cc
+
+// This is a standard TensorFlow Lite model file that has been converted into a
+// C data array, so it can be easily compiled into a binary for devices that
+// don't have a file system.
+
+// See train/README.md for a full description of the creation process.
+
+#include "model.h"
+
+// Keep model aligned to 8 bytes to guarantee aligned 64-bit accesses.
+alignas(8) const unsigned char g_model[] = {
+  0x1c, 0x00, 0x00, 0x00, 0x54, 0x46, 0x4c, 0x33, 0x14, 0x00, 0x20, 0x00, 0x1c, 0x00, 0x18, 0x00, 0x14, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x08, 0x00,
+  0x04, 0x00, 0x14, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x98, 0x00, 0x00, 0x00, 0xc8, 0x00, 0x00, 0x00, 0x1c, 0x03, 0x00, 0x00, 0x2c, 0x03, 0x00, 0x00,
+  0x30, 0x09, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x60, 0xf7, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00, 0x18, 0x00,
+  0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x73, 0x65, 0x72, 0x76, 0x65, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+  0x73, 0x65, 0x72, 0x76, 0x69, 0x6e, 0x67, 0x5f, 0x64, 0x65, 0x66, 0x61, 0x75, 0x6c, 0x74, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xbc, 0xff,
+  0xff, 0xff, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x64, 0x65, 0x6e, 0x73, 0x65, 0x5f, 0x34, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x04, 0x00, 0x00, 0x00, 0x76, 0xfd, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x64, 0x65, 0x6e, 0x73, 0x65, 0x5f, 0x32, 0x5f, 0x69, 0x6e,
+  0x70, 0x75, 0x74, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00,
+  0x0b, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x6d, 0x69, 0x6e, 0x5f, 0x72, 0x75, 0x6e, 0x74, 0x69, 0x6d, 0x65, 0x5f, 0x76, 0x65,
+  0x72, 0x73, 0x69, 0x6f, 0x6e, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x50, 0x02, 0x00, 0x00, 0x48, 0x02, 0x00, 0x00, 0x34, 0x02, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00,
+  0x8c, 0x01, 0x00, 0x00, 0x6c, 0x01, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x24, 0x00,
+  0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xfa, 0xfd, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x31, 0x2e, 0x35, 0x2e, 0x30, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0xfd, 0xff, 0xff, 0x88, 0xfd, 0xff, 0xff, 0x8c, 0xfd, 0xff, 0xff, 0x22, 0xfe, 0xff, 0xff, 0x04, 0x00,
+  0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x21, 0xa5, 0x8b, 0xca, 0x5e, 0x1d, 0xce, 0x42, 0x9d, 0xce, 0x1f, 0xb0, 0xdf, 0x54, 0x2f, 0x81, 0x3e, 0xfe, 0xff, 0xff,
+  0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xee, 0xfc, 0x00, 0xec, 0x05, 0x17, 0xef, 0xec, 0xe6, 0xf8, 0x03, 0x01, 0x00, 0xfa, 0xf8, 0xf5, 0xdc, 0xeb,
+  0x27, 0x14, 0xf1, 0xde, 0xe2, 0xdb, 0xf0, 0xde, 0x31, 0x06, 0x02, 0xe6, 0xee, 0xf9, 0x00, 0x16, 0x07, 0xe0, 0xfe, 0xff, 0xe9, 0x06, 0xe7, 0xef, 0x81, 0x1b,
+  0x18, 0xea, 0xc9, 0x01, 0x0f, 0x00, 0xda, 0xf7, 0x0e, 0xec, 0x13, 0x1f, 0x04, 0x13, 0xb4, 0xe6, 0xfd, 0x06, 0xb9, 0xe0, 0x0d, 0xec, 0xf0, 0xde, 0xeb, 0xf7,
+  0x05, 0x26, 0x1a, 0xe4, 0x6f, 0x1a, 0xea, 0x1e, 0x35, 0xdf, 0x1a, 0xf3, 0xf1, 0x19, 0x0f, 0x03, 0x1b, 0xe1, 0xde, 0x13, 0xf6, 0x19, 0xff, 0xf6, 0x1b, 0x18,
+  0xf0, 0x1c, 0xda, 0x1b, 0x1b, 0x20, 0xe5, 0x1a, 0xf5, 0xff, 0x96, 0x0b, 0x00, 0x01, 0xcd, 0xde, 0x0d, 0xf6, 0x16, 0xe3, 0xed, 0xfc, 0x0e, 0xe9, 0xfa, 0xeb,
+  0x5c, 0xfc, 0x1d, 0x02, 0x5b, 0xe2, 0xe1, 0xf5, 0x15, 0xec, 0xf4, 0x00, 0x13, 0x05, 0xec, 0x0c, 0x1d, 0x14, 0x0e, 0xe7, 0x0b, 0xf4, 0x19, 0x00, 0xd7, 0x05,
+  0x27, 0x02, 0x15, 0xea, 0xea, 0x02, 0x9b, 0x00, 0x0c, 0xfa, 0xe8, 0xea, 0xfd, 0x00, 0x14, 0xfd, 0x0b, 0x02, 0xef, 0xee, 0x06, 0xee, 0x01, 0x0d, 0x06, 0xe6,
+  0xf7, 0x11, 0xf7, 0x09, 0xf8, 0xf1, 0x21, 0xff, 0x0e, 0xf3, 0xec, 0x12, 0x26, 0x1d, 0xf2, 0xe9, 0x28, 0x18, 0xe0, 0xfb, 0xf3, 0xf4, 0x05, 0x1d, 0x1d, 0xfb,
+  0xfd, 0x1e, 0xfc, 0x11, 0xe8, 0x07, 0x09, 0x03, 0x12, 0xf2, 0x36, 0xfb, 0xdc, 0x1c, 0xf9, 0xef, 0xf3, 0xe7, 0x6f, 0x0c, 0x1d, 0x00, 0x45, 0xfd, 0x0e, 0xf0,
+  0x0b, 0x19, 0x1a, 0xfa, 0xe0, 0x19, 0x1f, 0x13, 0x36, 0x1c, 0x12, 0xeb, 0x3b, 0x0c, 0xb4, 0xcb, 0xe6, 0x13, 0xfa, 0xeb, 0xf1, 0x06, 0x1c, 0xfa, 0x18, 0xe5,
+  0xeb, 0xcb, 0x0c, 0xf4, 0x4a, 0xff, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x75, 0x1c, 0x11, 0xe1, 0x0c, 0x81, 0xa5, 0x42, 0xfe, 0xd5,
+  0xd4, 0xb2, 0x61, 0x78, 0x19, 0xdf, 0x66, 0xff, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x77, 0x0b, 0x00, 0x00,
+  0x53, 0xf6, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x77, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd3, 0x06, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2f, 0x07, 0x00, 0x00, 0x67, 0xf5, 0xff, 0xff, 0x34, 0xf0, 0xff, 0xff,
+  0x00, 0x00, 0x00, 0x00, 0xb2, 0xff, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb5, 0x04, 0x00, 0x00, 0x78, 0x0a,
+  0x00, 0x00, 0x2d, 0x06, 0x00, 0x00, 0x71, 0xf8, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x9a, 0x0a, 0x00, 0x00, 0xfe, 0xf7, 0xff, 0xff, 0x0e, 0x05, 0x00, 0x00,
+  0xd4, 0x09, 0x00, 0x00, 0x47, 0xfe, 0xff, 0xff, 0xb6, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0xf7, 0xff, 0xff, 0x4b, 0xf9, 0xff, 0xff, 0x4a, 0x05,
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+  0xff, 0xff, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00, 0x6c, 0xfc, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x20, 0x00,
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+  0xc2, 0x0f, 0xc0, 0x3f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x74, 0x66, 0x6c, 0x2e, 0x66, 0x75, 0x6c, 0x6c, 0x79, 0x5f,
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+  0x08, 0xfd, 0xff, 0xff, 0x18, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x64, 0x00,
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00, 0xf4, 0xfc, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00,
+  0x20, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  0x00, 0x00, 0xe0, 0xdb, 0x47, 0x3c, 0x01, 0x00, 0x00, 0x00, 0x04, 0x14, 0x47, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00,
+  0x74, 0x66, 0x6c, 0x2e, 0x66, 0x75, 0x6c, 0x6c, 0x79, 0x5f, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x65, 0x64, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00,
+  0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x02, 0xfe, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09,
+  0x50, 0x00, 0x00, 0x00, 0x6c, 0xfd, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xfb, 0x4b, 0x0b, 0x3c, 0x01, 0x00, 0x00, 0x00, 0x40, 0x84, 0x4b, 0x3f,
+  0x01, 0x00, 0x00, 0x00, 0x63, 0x35, 0x8a, 0xbf, 0x0d, 0x00, 0x00, 0x00, 0x73, 0x74, 0x64, 0x2e, 0x63, 0x6f, 0x6e, 0x73, 0x74, 0x61, 0x6e, 0x74, 0x32, 0x00,
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x72, 0xfe, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00,
+  0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x50, 0x00, 0x00, 0x00, 0xdc, 0xfd, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x1c, 0x00,
+  0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x60, 0x01, 0x4f, 0x3c,
+  0x01, 0x00, 0x00, 0x00, 0x47, 0x6d, 0xb3, 0x3f, 0x01, 0x00, 0x00, 0x00, 0x5d, 0x63, 0xcd, 0xbf, 0x0d, 0x00, 0x00, 0x00, 0x73, 0x74, 0x64, 0x2e, 0x63, 0x6f,
+  0x6e, 0x73, 0x74, 0x61, 0x6e, 0x74, 0x31, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0xe2, 0xfe, 0xff, 0xff,
+  0x14, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x50, 0x00, 0x00, 0x00, 0x4c, 0xfe, 0xff, 0xff, 0x10, 0x00,
+  0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0xd5, 0x6b, 0x8a, 0x3b, 0x01, 0x00, 0x00, 0x00, 0xab, 0x49, 0x01, 0x3f, 0x01, 0x00, 0x00, 0x00, 0xfd, 0x56, 0x09, 0xbf, 0x0c, 0x00,
+  0x00, 0x00, 0x73, 0x74, 0x64, 0x2e, 0x63, 0x6f, 0x6e, 0x73, 0x74, 0x61, 0x6e, 0x74, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x52, 0xff, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x3c, 0x00,
+  0x00, 0x00, 0x44, 0xff, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x28, 0xb3, 0xd9, 0x38, 0x0c, 0x00, 0x00, 0x00, 0x64, 0x65, 0x6e, 0x73, 0x65, 0x5f, 0x32, 0x2f, 0x62, 0x69,
+  0x61, 0x73, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0xaa, 0xff, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00,
+  0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x38, 0x00, 0x00, 0x00, 0x9c, 0xff, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xdd, 0x9b, 0x21, 0x39, 0x0c, 0x00, 0x00, 0x00, 0x64, 0x65, 0x6e, 0x73,
+  0x65, 0x5f, 0x33, 0x2f, 0x62, 0x69, 0x61, 0x73, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x18, 0x00,
+  0x14, 0x00, 0x13, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x02, 0x48, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x08, 0x00,
+  0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0xf4, 0xd4, 0x51, 0x38, 0x0c, 0x00, 0x00, 0x00, 0x64, 0x65, 0x6e, 0x73, 0x65, 0x5f, 0x34, 0x2f, 0x62, 0x69, 0x61, 0x73, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x14, 0x00, 0x1c, 0x00, 0x18, 0x00, 0x17, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00,
+  0x14, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x84, 0x00,
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x14, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00,
+  0x0c, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x5d, 0x4f, 0xc9, 0x3c, 0x01, 0x00, 0x00, 0x00, 0x0e, 0x86, 0xc8, 0x40,
+  0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x73, 0x65, 0x72, 0x76, 0x69, 0x6e, 0x67, 0x5f, 0x64, 0x65, 0x66, 0x61, 0x75, 0x6c,
+  0x74, 0x5f, 0x64, 0x65, 0x6e, 0x73, 0x65, 0x5f, 0x32, 0x5f, 0x69, 0x6e, 0x70, 0x75, 0x74, 0x3a, 0x30, 0x5f, 0x69, 0x6e, 0x74, 0x38, 0x00, 0x00, 0x00, 0x00,
+  0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x04, 0x00,
+  0x00, 0x00, 0xd8, 0xff, 0xff, 0xff, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0c, 0x00, 0x0c, 0x00, 0x0b, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x0c, 0x00, 0x10, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x08, 0x00,
+  0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09
+};
+const int g_model_len = 2488;
diff --git a/libraries/TFLiteMicro/examples/hello_world/model.h b/libraries/TFLiteMicro/examples/hello_world/model.h
new file mode 100644
index 00000000000..488f47b3afd
--- /dev/null
+++ b/libraries/TFLiteMicro/examples/hello_world/model.h
@@ -0,0 +1,31 @@
+/* Copyright 2020 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// Automatically created from a TensorFlow Lite flatbuffer using the command:
+// xxd -i model.tflite > model.cc
+
+// This is a standard TensorFlow Lite model file that has been converted into a
+// C data array, so it can be easily compiled into a binary for devices that
+// don't have a file system.
+
+// See train/README.md for a full description of the creation process.
+
+#ifndef TENSORFLOW_LITE_MICRO_EXAMPLES_HELLO_WORLD_MODEL_H_
+#define TENSORFLOW_LITE_MICRO_EXAMPLES_HELLO_WORLD_MODEL_H_
+
+extern const unsigned char g_model[];
+extern const int g_model_len;
+
+#endif  // TENSORFLOW_LITE_MICRO_EXAMPLES_HELLO_WORLD_MODEL_H_
diff --git a/libraries/TFLiteMicro/examples/hello_world/output_handler.cpp b/libraries/TFLiteMicro/examples/hello_world/output_handler.cpp
new file mode 100644
index 00000000000..bddccd00af9
--- /dev/null
+++ b/libraries/TFLiteMicro/examples/hello_world/output_handler.cpp
@@ -0,0 +1,22 @@
+/* Copyright 2019 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#include "output_handler.h"
+#include "tensorflow/lite/micro/micro_log.h"
+
+void HandleOutput(float x_value, float y_value) {
+  // Log the current X and Y values
+  MicroPrintf("x_value: %f, y_value: %f\n", static_cast<double>(x_value), static_cast<double>(y_value));
+}
diff --git a/libraries/TFLiteMicro/examples/hello_world/output_handler.h b/libraries/TFLiteMicro/examples/hello_world/output_handler.h
new file mode 100644
index 00000000000..a16846043b3
--- /dev/null
+++ b/libraries/TFLiteMicro/examples/hello_world/output_handler.h
@@ -0,0 +1,24 @@
+/* Copyright 2019 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#ifndef TENSORFLOW_LITE_MICRO_EXAMPLES_HELLO_WORLD_OUTPUT_HANDLER_H_
+#define TENSORFLOW_LITE_MICRO_EXAMPLES_HELLO_WORLD_OUTPUT_HANDLER_H_
+
+#include "tensorflow/lite/c/common.h"
+
+// Called by the main loop to produce some output based on the x and y values
+void HandleOutput(float x_value, float y_value);
+
+#endif  // TENSORFLOW_LITE_MICRO_EXAMPLES_HELLO_WORLD_OUTPUT_HANDLER_H_
diff --git a/libraries/TFLiteMicro/library.properties b/libraries/TFLiteMicro/library.properties
new file mode 100644
index 00000000000..1e8db045610
--- /dev/null
+++ b/libraries/TFLiteMicro/library.properties
@@ -0,0 +1,8 @@
+name=TFLite Micro
+version=3.2.0
+author=Sanket Wadekar
+maintainer=Sanket Wadekar
+sentence=TensorFlow Lite for Microcontrollers
+paragraph=With this library you can train and deploy Machine Learning models on esp32 series of microcontrollers.
+url=https://www.tensorflow.org/lite/microcontrollers
+architectures=esp32,esp32s3
diff --git a/libraries/TFLiteMicro/src/TFLIteMicro.h b/libraries/TFLiteMicro/src/TFLIteMicro.h
new file mode 100644
index 00000000000..4f278f65879
--- /dev/null
+++ b/libraries/TFLiteMicro/src/TFLIteMicro.h
@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+// This header file is kept to avoid Invalid library error prints while compiling TFLite Micro examples.
diff --git a/libraries/TFLiteMicro/src/utility.h b/libraries/TFLiteMicro/src/utility.h
new file mode 100644
index 00000000000..90596c155da
--- /dev/null
+++ b/libraries/TFLiteMicro/src/utility.h
@@ -0,0 +1,10 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+#include <utility>
+/*
+The example sketches include "tensorflow/lite/micro/micro_interpreter.h" which internally include "utility.h" header file when compiling examples for Arduino (when -DARDUINO flag is passed to the compiler). This header file does not exist in esp32-arduino core. Hence, keeping this file here as a workaround and including an alternate header file.
+*/
diff --git a/libraries/Ticker/examples/Arguments/Arguments.ino b/libraries/Ticker/examples/Arguments/Arguments.ino
deleted file mode 100644
index cde8acbfa09..00000000000
--- a/libraries/Ticker/examples/Arguments/Arguments.ino
+++ /dev/null
@@ -1,27 +0,0 @@
-#include <Arduino.h>
-#include <Ticker.h>
-
-// attach a LED to GPIO 21
-#define LED_PIN 21
-
-Ticker tickerSetHigh;
-Ticker tickerSetLow;
-
-void setPin(int state) {
-  digitalWrite(LED_PIN, state);
-}
-
-void setup() {
-  pinMode(LED_PIN, OUTPUT);
-  digitalWrite(1, LOW);
-  
-  // every 25 ms, call setPin(0) 
-  tickerSetLow.attach_ms(25, setPin, 0);
-  
-  // every 26 ms, call setPin(1)
-  tickerSetHigh.attach_ms(26, setPin, 1);
-}
-
-void loop() {
-
-}
diff --git a/libraries/Ticker/examples/Blinker/Blinker.ino b/libraries/Ticker/examples/Blinker/Blinker.ino
index aca1f450cca..0afd2828cad 100644
--- a/libraries/Ticker/examples/Blinker/Blinker.ino
+++ b/libraries/Ticker/examples/Blinker/Blinker.ino
@@ -7,8 +7,8 @@
 Ticker blinker;
 Ticker toggler;
 Ticker changer;
-float blinkerPace = 0.1;  //seconds
-const float togglePeriod = 5; //seconds
+float blinkerPace = 0.1;       //seconds
+const float togglePeriod = 5;  //seconds
 
 void change() {
   blinkerPace = 0.5;
@@ -23,8 +23,7 @@ void toggle() {
   if (isBlinking) {
     blinker.detach();
     isBlinking = false;
-  }
-  else {
+  } else {
     blinker.attach(blinkerPace, blink);
     isBlinking = true;
   }
@@ -37,6 +36,4 @@ void setup() {
   changer.once(30, change);
 }
 
-void loop() {
-  
-}
+void loop() {}
diff --git a/libraries/Ticker/examples/TickerBasic/TickerBasic.ino b/libraries/Ticker/examples/TickerBasic/TickerBasic.ino
new file mode 100644
index 00000000000..eb25922613b
--- /dev/null
+++ b/libraries/Ticker/examples/TickerBasic/TickerBasic.ino
@@ -0,0 +1,48 @@
+/*
+  Basic Ticker usage
+
+  Ticker is an object that will call a given function with a certain period.
+  Each Ticker calls one function. You can have as many Tickers as you like,
+  memory being the only limitation.
+
+  A function may be attached to a ticker and detached from the ticker.
+  There are two variants of the attach function: attach and attach_ms.
+  The first one takes period in seconds, the second one in milliseconds.
+
+  The built-in LED will be blinking.
+*/
+
+#include <Ticker.h>
+
+#ifndef LED_BUILTIN
+#define LED_BUILTIN 13
+#endif
+
+Ticker flipper;
+
+int count = 0;
+
+void flip() {
+  int state = digitalRead(LED_BUILTIN);  // get the current state of GPIO1 pin
+  digitalWrite(LED_BUILTIN, !state);     // set pin to the opposite state
+
+  ++count;
+  // when the counter reaches a certain value, start blinking like crazy
+  if (count == 20) {
+    flipper.attach(0.1, flip);
+  }
+  // when the counter reaches yet another value, stop blinking
+  else if (count == 120) {
+    flipper.detach();
+  }
+}
+
+void setup() {
+  pinMode(LED_BUILTIN, OUTPUT);
+  digitalWrite(LED_BUILTIN, LOW);
+
+  // flip the pin every 0.3s
+  flipper.attach(0.3, flip);
+}
+
+void loop() {}
diff --git a/libraries/Ticker/examples/TickerParameter/TickerParameter.ino b/libraries/Ticker/examples/TickerParameter/TickerParameter.ino
new file mode 100644
index 00000000000..439d0ab8932
--- /dev/null
+++ b/libraries/Ticker/examples/TickerParameter/TickerParameter.ino
@@ -0,0 +1,53 @@
+/*
+  Passing parameters to Ticker callbacks
+
+  Apart from void(void) functions, the Ticker library supports
+  functions taking one argument. This argument's size has to be less or
+  equal to 4 bytes (so char, short, int, float, void*, char* types will do).
+
+  This sample runs two tickers that both call one callback function,
+  but with different arguments.
+
+  The built-in LED will be pulsing.
+*/
+
+#include <Ticker.h>
+
+#ifndef LED_BUILTIN
+#define LED_BUILTIN 13
+#endif
+
+Ticker tickerSetLow;
+Ticker tickerSetHigh;
+Ticker tickerSetChar;
+
+void setPinLow() {
+  digitalWrite(LED_BUILTIN, 0);
+}
+
+void setPinHigh() {
+  digitalWrite(LED_BUILTIN, 1);
+}
+
+void setPin(int state) {
+  digitalWrite(LED_BUILTIN, state);
+}
+
+void setPinChar(char state) {
+  digitalWrite(LED_BUILTIN, state);
+}
+
+void setup() {
+  pinMode(LED_BUILTIN, OUTPUT);
+
+  // every 25 ms, call setPinLow()
+  tickerSetLow.attach_ms(25, setPinLow);
+
+  // every 26 ms, call setPinHigh()
+  tickerSetHigh.attach_ms(26, setPinHigh);
+
+  // every 54 ms, call setPinChar(1)
+  tickerSetChar.attach_ms(26, setPinChar, (char)1);
+}
+
+void loop() {}
diff --git a/libraries/Ticker/keywords.txt b/libraries/Ticker/keywords.txt
index 81cce2c8ea5..f5f1266516d 100644
--- a/libraries/Ticker/keywords.txt
+++ b/libraries/Ticker/keywords.txt
@@ -10,5 +10,9 @@ Ticker	KEYWORD1
 
 attach	KEYWORD2
 attach_ms	KEYWORD2
+attach_us	KEYWORD2
 once	KEYWORD2
+once_ms	KEYWORD2
+once_us	KEYWORD2
 detach	KEYWORD2
+active	KEYWORD2
diff --git a/libraries/Ticker/library.properties b/libraries/Ticker/library.properties
index 0f399447d4d..975db96d1ad 100644
--- a/libraries/Ticker/library.properties
+++ b/libraries/Ticker/library.properties
@@ -1,5 +1,5 @@
 name=Ticker
-version=1.1
+version=3.2.0
 author=Bert Melis
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=Allows to call functions with a given interval.
diff --git a/libraries/Ticker/src/Ticker.cpp b/libraries/Ticker/src/Ticker.cpp
index 1deeb7fb69f..93cc0f393f4 100644
--- a/libraries/Ticker/src/Ticker.cpp
+++ b/libraries/Ticker/src/Ticker.cpp
@@ -1,8 +1,8 @@
-/* 
+/*
   Ticker.cpp - esp32 library that calls functions periodically
 
   Copyright (c) 2017 Bert Melis. All rights reserved.
-  
+
   Based on the original work of:
   Copyright (c) 2014 Ivan Grokhotkov. All rights reserved.
   The original version is part of the esp8266 core for Arduino environment.
@@ -24,16 +24,15 @@
 
 #include "Ticker.h"
 
-Ticker::Ticker() :
-  _timer(nullptr) {}
+Ticker::Ticker() : _timer(nullptr) {}
 
 Ticker::~Ticker() {
   detach();
 }
 
-void Ticker::_attach_ms(uint32_t milliseconds, bool repeat, callback_with_arg_t callback, uint32_t arg) {
+void Ticker::_attach_us(uint64_t micros, bool repeat, callback_with_arg_t callback, void *arg) {
   esp_timer_create_args_t _timerConfig;
-  _timerConfig.arg = reinterpret_cast<void*>(arg);
+  _timerConfig.arg = reinterpret_cast<void *>(arg);
   _timerConfig.callback = callback;
   _timerConfig.dispatch_method = ESP_TIMER_TASK;
   _timerConfig.name = "Ticker";
@@ -43,9 +42,9 @@ void Ticker::_attach_ms(uint32_t milliseconds, bool repeat, callback_with_arg_t
   }
   esp_timer_create(&_timerConfig, &_timer);
   if (repeat) {
-    esp_timer_start_periodic(_timer, milliseconds * 1000ULL);
+    esp_timer_start_periodic(_timer, micros);
   } else {
-    esp_timer_start_once(_timer, milliseconds * 1000ULL);
+    esp_timer_start_once(_timer, micros);
   }
 }
 
@@ -54,5 +53,20 @@ void Ticker::detach() {
     esp_timer_stop(_timer);
     esp_timer_delete(_timer);
     _timer = nullptr;
+    _callback_function = nullptr;
+  }
+}
+
+bool Ticker::active() const {
+  if (!_timer) {
+    return false;
+  }
+  return esp_timer_is_active(_timer);
+}
+
+void Ticker::_static_callback(void *arg) {
+  Ticker *_this = reinterpret_cast<Ticker *>(arg);
+  if (_this && _this->_callback_function) {
+    _this->_callback_function();
   }
 }
diff --git a/libraries/Ticker/src/Ticker.h b/libraries/Ticker/src/Ticker.h
index 82804e0f37d..f86da178a74 100644
--- a/libraries/Ticker/src/Ticker.h
+++ b/libraries/Ticker/src/Ticker.h
@@ -1,8 +1,8 @@
-/* 
+/*
   Ticker.h - esp32 library that calls functions periodically
 
   Copyright (c) 2017 Bert Melis. All rights reserved.
-  
+
   Based on the original work of:
   Copyright (c) 2014 Ivan Grokhotkov. All rights reserved.
   The original version is part of the esp8266 core for Arduino environment.
@@ -26,82 +26,93 @@
 #define TICKER_H
 
 extern "C" {
-  #include "esp_timer.h"
+#include "esp_timer.h"
 }
+#include <functional>
 
-class Ticker
-{
+class Ticker {
 public:
   Ticker();
   ~Ticker();
-  typedef void (*callback_t)(void);
-  typedef void (*callback_with_arg_t)(void*);
 
-  void attach(float seconds, callback_t callback)
-  {
-    _attach_ms(seconds * 1000, true, reinterpret_cast<callback_with_arg_t>(callback), 0);
+  typedef void (*callback_with_arg_t)(void *);
+  typedef std::function<void(void)> callback_function_t;
+
+  void attach(float seconds, callback_function_t callback) {
+    _callback_function = std::move(callback);
+    _attach_us(1000000ULL * seconds, true, _static_callback, this);
+  }
+
+  void attach_ms(uint64_t milliseconds, callback_function_t callback) {
+    _callback_function = std::move(callback);
+    _attach_us(1000ULL * milliseconds, true, _static_callback, this);
   }
 
-  void attach_ms(uint32_t milliseconds, callback_t callback)
-  {
-    _attach_ms(milliseconds, true, reinterpret_cast<callback_with_arg_t>(callback), 0);
+  void attach_us(uint64_t micros, callback_function_t callback) {
+    _callback_function = std::move(callback);
+    _attach_us(micros, true, _static_callback, this);
   }
 
-  template<typename TArg>
-  void attach(float seconds, void (*callback)(TArg), TArg arg)
-  {
-    static_assert(sizeof(TArg) <= sizeof(uint32_t), "attach() callback argument size must be <= 4 bytes");
+  template<typename TArg> void attach(float seconds, void (*callback)(TArg), TArg arg) {
+    static_assert(sizeof(TArg) <= sizeof(void *), "attach() callback argument size must be <= sizeof(void*)");
     // C-cast serves two purposes:
     // static_cast for smaller integer types,
     // reinterpret_cast + const_cast for pointer types
-    uint32_t arg32 = (uint32_t)arg;
-    _attach_ms(seconds * 1000, true, reinterpret_cast<callback_with_arg_t>(callback), arg32);
+    _attach_us(1000000ULL * seconds, true, reinterpret_cast<callback_with_arg_t>(callback), reinterpret_cast<void *>(arg));
   }
 
-  template<typename TArg>
-  void attach_ms(uint32_t milliseconds, void (*callback)(TArg), TArg arg)
-  {
-    static_assert(sizeof(TArg) <= sizeof(uint32_t), "attach_ms() callback argument size must be <= 4 bytes");
-    uint32_t arg32 = (uint32_t)arg;
-    _attach_ms(milliseconds, true, reinterpret_cast<callback_with_arg_t>(callback), arg32);
+  template<typename TArg> void attach_ms(uint64_t milliseconds, void (*callback)(TArg), TArg arg) {
+    static_assert(sizeof(TArg) <= sizeof(void *), "attach() callback argument size must be <= sizeof(void*)");
+    _attach_us(1000ULL * milliseconds, true, reinterpret_cast<callback_with_arg_t>(callback), reinterpret_cast<void *>(arg));
   }
 
-  void once(float seconds, callback_t callback)
-  {
-    _attach_ms(seconds * 1000, false, reinterpret_cast<callback_with_arg_t>(callback), 0);
+  template<typename TArg> void attach_us(uint64_t micros, void (*callback)(TArg), TArg arg) {
+    static_assert(sizeof(TArg) <= sizeof(void *), "attach() callback argument size must be <= sizeof(void*)");
+    _attach_us(micros, true, reinterpret_cast<callback_with_arg_t>(callback), reinterpret_cast<void *>(arg));
   }
 
-  void once_ms(uint32_t milliseconds, callback_t callback)
-  {
-    _attach_ms(milliseconds, false, reinterpret_cast<callback_with_arg_t>(callback), 0);	
+  void once(float seconds, callback_function_t callback) {
+    _callback_function = std::move(callback);
+    _attach_us(1000000ULL * seconds, false, _static_callback, this);
   }
 
-  template<typename TArg>
-  void once(float seconds, void (*callback)(TArg), TArg arg)
-  {
-    static_assert(sizeof(TArg) <= sizeof(uint32_t), "attach() callback argument size must be <= 4 bytes");
-    uint32_t arg32 = (uint32_t)(arg);
-    _attach_ms(seconds * 1000, false, reinterpret_cast<callback_with_arg_t>(callback), arg32);
+  void once_ms(uint64_t milliseconds, callback_function_t callback) {
+    _callback_function = std::move(callback);
+    _attach_us(1000ULL * milliseconds, false, _static_callback, this);
   }
 
-  template<typename TArg>
-  void once_ms(uint32_t milliseconds, void (*callback)(TArg), TArg arg)
-  {
-    static_assert(sizeof(TArg) <= sizeof(uint32_t), "attach_ms() callback argument size must be <= 4 bytes");
-    uint32_t arg32 = (uint32_t)(arg);
-    _attach_ms(milliseconds, false, reinterpret_cast<callback_with_arg_t>(callback), arg32);
+  void once_us(uint64_t micros, callback_function_t callback) {
+    _callback_function = std::move(callback);
+    _attach_us(micros, false, _static_callback, this);
   }
 
-  void detach();
-  bool active();
+  template<typename TArg> void once(float seconds, void (*callback)(TArg), TArg arg) {
+    static_assert(sizeof(TArg) <= sizeof(void *), "attach() callback argument size must be <= sizeof(void*)");
+    _attach_us(1000000ULL * seconds, false, reinterpret_cast<callback_with_arg_t>(callback), reinterpret_cast<void *>(arg));
+  }
+
+  template<typename TArg> void once_ms(uint64_t milliseconds, void (*callback)(TArg), TArg arg) {
+    static_assert(sizeof(TArg) <= sizeof(void *), "attach() callback argument size must be <= sizeof(void*)");
+    _attach_us(1000ULL * milliseconds, false, reinterpret_cast<callback_with_arg_t>(callback), reinterpret_cast<void *>(arg));
+  }
 
-protected:	
-  void _attach_ms(uint32_t milliseconds, bool repeat, callback_with_arg_t callback, uint32_t arg);
+  template<typename TArg> void once_us(uint64_t micros, void (*callback)(TArg), TArg arg) {
+    static_assert(sizeof(TArg) <= sizeof(void *), "attach() callback argument size must be <= sizeof(void*)");
+    _attach_us(micros, false, reinterpret_cast<callback_with_arg_t>(callback), reinterpret_cast<void *>(arg));
+  }
 
+  void detach();
+  bool active() const;
 
 protected:
+  static void _static_callback(void *arg);
+
+  callback_function_t _callback_function = nullptr;
+
   esp_timer_handle_t _timer;
-};
 
+private:
+  void _attach_us(uint64_t micros, bool repeat, callback_with_arg_t callback, void *arg);
+};
 
 #endif  // TICKER_H
diff --git a/libraries/USB/examples/CompositeDevice/CompositeDevice.ino b/libraries/USB/examples/CompositeDevice/CompositeDevice.ino
new file mode 100644
index 00000000000..5032f5c8136
--- /dev/null
+++ b/libraries/USB/examples/CompositeDevice/CompositeDevice.ino
@@ -0,0 +1,198 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+#include "USBHIDMouse.h"
+#include "USBHIDKeyboard.h"
+#include "USBHIDGamepad.h"
+#include "USBHIDConsumerControl.h"
+#include "USBHIDSystemControl.h"
+#include "USBHIDVendor.h"
+#include "FirmwareMSC.h"
+
+#if !ARDUINO_USB_MSC_ON_BOOT
+FirmwareMSC MSC_Update;
+#endif
+
+#if !ARDUINO_USB_CDC_ON_BOOT
+USBCDC USBSerial;
+#endif
+
+USBHID HID;
+USBHIDKeyboard Keyboard;
+USBHIDMouse Mouse;
+USBHIDGamepad Gamepad;
+USBHIDConsumerControl ConsumerControl;
+USBHIDSystemControl SystemControl;
+USBHIDVendor Vendor;
+
+const int buttonPin = 0;
+int previousButtonState = HIGH;
+
+static void usbEventCallback(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == ARDUINO_USB_EVENTS) {
+    arduino_usb_event_data_t *data = (arduino_usb_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_STARTED_EVENT: Serial.println("USB PLUGGED"); break;
+      case ARDUINO_USB_STOPPED_EVENT: Serial.println("USB UNPLUGGED"); break;
+      case ARDUINO_USB_SUSPEND_EVENT: Serial.printf("USB SUSPENDED: remote_wakeup_en: %u\n", data->suspend.remote_wakeup_en); break;
+      case ARDUINO_USB_RESUME_EVENT:  Serial.println("USB RESUMED"); break;
+
+      default: break;
+    }
+  } else if (event_base == ARDUINO_USB_CDC_EVENTS) {
+    arduino_usb_cdc_event_data_t *data = (arduino_usb_cdc_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_CDC_CONNECTED_EVENT:    Serial.println("CDC CONNECTED"); break;
+      case ARDUINO_USB_CDC_DISCONNECTED_EVENT: Serial.println("CDC DISCONNECTED"); break;
+      case ARDUINO_USB_CDC_LINE_STATE_EVENT:   Serial.printf("CDC LINE STATE: dtr: %u, rts: %u\n", data->line_state.dtr, data->line_state.rts); break;
+      case ARDUINO_USB_CDC_LINE_CODING_EVENT:
+        Serial.printf(
+          "CDC LINE CODING: bit_rate: %lu, data_bits: %u, stop_bits: %u, parity: %u\n", data->line_coding.bit_rate, data->line_coding.data_bits,
+          data->line_coding.stop_bits, data->line_coding.parity
+        );
+        break;
+      case ARDUINO_USB_CDC_RX_EVENT:
+        Serial.printf("CDC RX [%u]:", data->rx.len);
+        {
+          uint8_t buf[data->rx.len];
+          size_t len = USBSerial.read(buf, data->rx.len);
+          Serial.write(buf, len);
+        }
+        Serial.println();
+        break;
+      case ARDUINO_USB_CDC_RX_OVERFLOW_EVENT: Serial.printf("CDC RX Overflow of %d bytes", data->rx_overflow.dropped_bytes); break;
+
+      default: break;
+    }
+  } else if (event_base == ARDUINO_FIRMWARE_MSC_EVENTS) {
+    arduino_firmware_msc_event_data_t *data = (arduino_firmware_msc_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_FIRMWARE_MSC_START_EVENT: Serial.println("MSC Update Start"); break;
+      case ARDUINO_FIRMWARE_MSC_WRITE_EVENT:
+        //Serial.printf("MSC Update Write %u bytes at offset %u\n", data->write.size, data->write.offset);
+        Serial.print(".");
+        break;
+      case ARDUINO_FIRMWARE_MSC_END_EVENT:   Serial.printf("\nMSC Update End: %u bytes\n", data->end.size); break;
+      case ARDUINO_FIRMWARE_MSC_ERROR_EVENT: Serial.printf("MSC Update ERROR! Progress: %u bytes\n", data->error.size); break;
+      case ARDUINO_FIRMWARE_MSC_POWER_EVENT:
+        Serial.printf("MSC Update Power: power: %u, start: %u, eject: %u\n", data->power.power_condition, data->power.start, data->power.load_eject);
+        break;
+
+      default: break;
+    }
+  } else if (event_base == ARDUINO_USB_HID_EVENTS) {
+    arduino_usb_hid_event_data_t *data = (arduino_usb_hid_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_HID_SET_PROTOCOL_EVENT: Serial.printf("HID SET PROTOCOL: %s\n", data->set_protocol.protocol ? "REPORT" : "BOOT"); break;
+      case ARDUINO_USB_HID_SET_IDLE_EVENT:     Serial.printf("HID SET IDLE: %u\n", data->set_idle.idle_rate); break;
+
+      default: break;
+    }
+  } else if (event_base == ARDUINO_USB_HID_KEYBOARD_EVENTS) {
+    arduino_usb_hid_keyboard_event_data_t *data = (arduino_usb_hid_keyboard_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_HID_KEYBOARD_LED_EVENT:
+        Serial.printf("HID KEYBOARD LED: NumLock:%u, CapsLock:%u, ScrollLock:%u\n", data->numlock, data->capslock, data->scrolllock);
+        break;
+
+      default: break;
+    }
+  } else if (event_base == ARDUINO_USB_HID_VENDOR_EVENTS) {
+    arduino_usb_hid_vendor_event_data_t *data = (arduino_usb_hid_vendor_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_HID_VENDOR_GET_FEATURE_EVENT:
+        Serial.printf("HID VENDOR GET FEATURE: len:%u\n", data->len);
+        for (uint16_t i = 0; i < data->len; i++) {
+          Serial.write(data->buffer[i] ? data->buffer[i] : '.');
+        }
+        Serial.println();
+        break;
+      case ARDUINO_USB_HID_VENDOR_SET_FEATURE_EVENT:
+        Serial.printf("HID VENDOR SET FEATURE: len:%u\n", data->len);
+        for (uint16_t i = 0; i < data->len; i++) {
+          Serial.write(data->buffer[i] ? data->buffer[i] : '.');
+        }
+        Serial.println();
+        break;
+      case ARDUINO_USB_HID_VENDOR_OUTPUT_EVENT:
+        Serial.printf("HID VENDOR OUTPUT: len:%u\n", data->len);
+        for (uint16_t i = 0; i < data->len; i++) {
+          Serial.write(Vendor.read());
+        }
+        Serial.println();
+        break;
+
+      default: break;
+    }
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+
+  pinMode(buttonPin, INPUT_PULLUP);
+
+  USB.onEvent(usbEventCallback);
+  USBSerial.onEvent(usbEventCallback);
+  MSC_Update.onEvent(usbEventCallback);
+  HID.onEvent(usbEventCallback);
+  Keyboard.onEvent(usbEventCallback);
+  Vendor.onEvent(usbEventCallback);
+
+  USBSerial.begin();
+  MSC_Update.begin();
+  Vendor.begin();
+  Mouse.begin();
+  Keyboard.begin();
+  Gamepad.begin();
+  ConsumerControl.begin();
+  SystemControl.begin();
+  USB.begin();
+}
+
+void loop() {
+  int buttonState = digitalRead(buttonPin);
+  if (HID.ready() && buttonState != previousButtonState) {
+    previousButtonState = buttonState;
+    if (buttonState == LOW) {
+      if (Serial != USBSerial) {
+        Serial.println("Button Pressed");
+      }
+      USBSerial.println("Button Pressed");
+      Vendor.println("Button Pressed");
+      Mouse.move(10, 10);
+      Keyboard.pressRaw(HID_KEY_CAPS_LOCK);
+      Gamepad.leftStick(100, 100);
+      ConsumerControl.press(CONSUMER_CONTROL_VOLUME_INCREMENT);
+      //SystemControl.press(SYSTEM_CONTROL_POWER_OFF);
+    } else {
+      Keyboard.releaseRaw(HID_KEY_CAPS_LOCK);
+      Gamepad.leftStick(0, 0);
+      ConsumerControl.release();
+      //SystemControl.release();
+      Vendor.println("Button Released");
+      USBSerial.println("Button Released");
+      if (Serial != USBSerial) {
+        Serial.println("Button Released");
+      }
+    }
+    delay(100);
+  }
+
+  while (Serial.available()) {
+    size_t l = Serial.available();
+    uint8_t b[l];
+    l = Serial.read(b, l);
+    USBSerial.write(b, l);
+    if (HID.ready()) {
+      Vendor.write(b, l);
+    }
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/CompositeDevice/ci.json b/libraries/USB/examples/CompositeDevice/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/CompositeDevice/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/ConsumerControl/ConsumerControl.ino b/libraries/USB/examples/ConsumerControl/ConsumerControl.ino
new file mode 100644
index 00000000000..11b4d2c6af2
--- /dev/null
+++ b/libraries/USB/examples/ConsumerControl/ConsumerControl.ino
@@ -0,0 +1,29 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+#include "USBHIDConsumerControl.h"
+USBHIDConsumerControl ConsumerControl;
+
+const int buttonPin = 0;
+int previousButtonState = HIGH;
+
+void setup() {
+  pinMode(buttonPin, INPUT_PULLUP);
+  ConsumerControl.begin();
+  USB.begin();
+}
+
+void loop() {
+  int buttonState = digitalRead(buttonPin);
+  if ((buttonState != previousButtonState) && (buttonState == LOW)) {
+    ConsumerControl.press(CONSUMER_CONTROL_VOLUME_INCREMENT);
+    ConsumerControl.release();
+  }
+  previousButtonState = buttonState;
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/ConsumerControl/ci.json b/libraries/USB/examples/ConsumerControl/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/ConsumerControl/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/CustomHIDDevice/CustomHIDDevice.ino b/libraries/USB/examples/CustomHIDDevice/CustomHIDDevice.ino
new file mode 100644
index 00000000000..1b1038e4754
--- /dev/null
+++ b/libraries/USB/examples/CustomHIDDevice/CustomHIDDevice.ino
@@ -0,0 +1,88 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+#include "USBHID.h"
+USBHID HID;
+
+static const uint8_t report_descriptor[] = {
+  // 8 axis
+  0x05, 0x01,  // Usage Page (Generic Desktop Ctrls)
+  0x09, 0x04,  // Usage (Joystick)
+  0xa1, 0x01,  // Collection (Application)
+  0xa1, 0x00,  //   Collection (Physical)
+  0x05, 0x01,  //   Usage Page (Generic Desktop Ctrls)
+  0x09, 0x30,  //     Usage (X)
+  0x09, 0x31,  //     Usage (Y)
+  0x09, 0x32,  //     Usage (Z)
+  0x09, 0x33,  //     Usage (Rx)
+  0x09, 0x34,  //     Usage (Ry)
+  0x09, 0x35,  //     Usage (Rz)
+  0x09, 0x36,  //     Usage (Slider)
+  0x09, 0x36,  //     Usage (Slider)
+  0x15, 0x81,  //     Logical Minimum (-127)
+  0x25, 0x7f,  //     Logical Maximum (127)
+  0x75, 0x08,  //     Report Size (8)
+  0x95, 0x08,  //     Report Count (8)
+  0x81, 0x02,  //     Input (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)
+  0xC0,        //   End Collection
+  0xC0,        // End Collection
+};
+
+class CustomHIDDevice : public USBHIDDevice {
+public:
+  CustomHIDDevice(void) {
+    static bool initialized = false;
+    if (!initialized) {
+      initialized = true;
+      HID.addDevice(this, sizeof(report_descriptor));
+    }
+  }
+
+  void begin(void) {
+    HID.begin();
+  }
+
+  uint16_t _onGetDescriptor(uint8_t *buffer) {
+    memcpy(buffer, report_descriptor, sizeof(report_descriptor));
+    return sizeof(report_descriptor);
+  }
+
+  bool send(uint8_t *value) {
+    return HID.SendReport(0, value, 8);
+  }
+};
+
+CustomHIDDevice Device;
+
+const int buttonPin = 0;
+int previousButtonState = HIGH;
+uint8_t axis[8];
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+  pinMode(buttonPin, INPUT_PULLUP);
+  Device.begin();
+  USB.begin();
+}
+
+void loop() {
+  int buttonState = digitalRead(buttonPin);
+  if (HID.ready() && buttonState != previousButtonState) {
+    previousButtonState = buttonState;
+    if (buttonState == LOW) {
+      Serial.println("Button Pressed");
+      axis[0] = random() & 0xFF;
+      Device.send(axis);
+    } else {
+      Serial.println("Button Released");
+    }
+    delay(100);
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/CustomHIDDevice/ci.json b/libraries/USB/examples/CustomHIDDevice/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/CustomHIDDevice/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/FirmwareMSC/FirmwareMSC.ino b/libraries/USB/examples/FirmwareMSC/FirmwareMSC.ino
new file mode 100644
index 00000000000..1dbed3b2e53
--- /dev/null
+++ b/libraries/USB/examples/FirmwareMSC/FirmwareMSC.ino
@@ -0,0 +1,58 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+#include "FirmwareMSC.h"
+
+#if !ARDUINO_USB_MSC_ON_BOOT
+FirmwareMSC MSC_Update;
+#endif
+
+static void usbEventCallback(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == ARDUINO_USB_EVENTS) {
+    arduino_usb_event_data_t *data = (arduino_usb_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_STARTED_EVENT: Serial.println("USB PLUGGED"); break;
+      case ARDUINO_USB_STOPPED_EVENT: Serial.println("USB UNPLUGGED"); break;
+      case ARDUINO_USB_SUSPEND_EVENT: Serial.printf("USB SUSPENDED: remote_wakeup_en: %u\n", data->suspend.remote_wakeup_en); break;
+      case ARDUINO_USB_RESUME_EVENT:  Serial.println("USB RESUMED"); break;
+
+      default: break;
+    }
+  } else if (event_base == ARDUINO_FIRMWARE_MSC_EVENTS) {
+    arduino_firmware_msc_event_data_t *data = (arduino_firmware_msc_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_FIRMWARE_MSC_START_EVENT: Serial.println("MSC Update Start"); break;
+      case ARDUINO_FIRMWARE_MSC_WRITE_EVENT:
+        //Serial.printf("MSC Update Write %u bytes at offset %u\n", data->write.size, data->write.offset);
+        Serial.print(".");
+        break;
+      case ARDUINO_FIRMWARE_MSC_END_EVENT:   Serial.printf("\nMSC Update End: %u bytes\n", data->end.size); break;
+      case ARDUINO_FIRMWARE_MSC_ERROR_EVENT: Serial.printf("MSC Update ERROR! Progress: %u bytes\n", data->error.size); break;
+      case ARDUINO_FIRMWARE_MSC_POWER_EVENT:
+        Serial.printf("MSC Update Power: power: %u, start: %u, eject: %u", data->power.power_condition, data->power.start, data->power.load_eject);
+        break;
+
+      default: break;
+    }
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+
+  USB.onEvent(usbEventCallback);
+  MSC_Update.onEvent(usbEventCallback);
+  MSC_Update.begin();
+  USB.begin();
+}
+
+void loop() {
+  // put your main code here, to run repeatedly
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/FirmwareMSC/ci.json b/libraries/USB/examples/FirmwareMSC/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/FirmwareMSC/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/Gamepad/Gamepad.ino b/libraries/USB/examples/Gamepad/Gamepad.ino
new file mode 100644
index 00000000000..395f068580b
--- /dev/null
+++ b/libraries/USB/examples/Gamepad/Gamepad.ino
@@ -0,0 +1,57 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+#include "USBHIDGamepad.h"
+USBHIDGamepad Gamepad;
+
+const int buttonPin = 0;
+int previousButtonState = HIGH;
+
+void setup() {
+  pinMode(buttonPin, INPUT_PULLUP);
+  Gamepad.begin();
+  USB.begin();
+  Serial.begin(115200);
+  Serial.println("\n==================\nUSB Gamepad Testing\n==================\n");
+  Serial.println("Press BOOT Button to activate the USB gamepad.");
+  Serial.println("Longer press will change the affected button and controls.");
+  Serial.println("Shorter press/release just activates the button and controls.");
+}
+
+void loop() {
+  static uint8_t padID = 0;
+  static long lastPress = 0;
+
+  int buttonState = digitalRead(buttonPin);
+  if (buttonState != previousButtonState) {
+    if (buttonState == LOW) {                         // BOOT Button pressed
+      Gamepad.pressButton(padID);                     // Buttons 1 to 32
+      Gamepad.leftStick(padID << 3, padID << 3);      // X Axis, Y Axis
+      Gamepad.rightStick(-(padID << 2), padID << 2);  // Z Axis, Z Rotation
+      Gamepad.leftTrigger(padID << 4);                // X Rotation
+      Gamepad.rightTrigger(-(padID << 4));            // Y Rotation
+      Gamepad.hat((padID & 0x7) + 1);                 // Point of View Hat
+      log_d("Pressed PadID [%d]", padID);
+      lastPress = millis();
+    } else {
+      Gamepad.releaseButton(padID);
+      Gamepad.leftStick(0, 0);
+      Gamepad.rightStick(0, 0);
+      Gamepad.leftTrigger(0);
+      Gamepad.rightTrigger(0);
+      Gamepad.hat(HAT_CENTER);
+      log_d("Released PadID [%d]\n", padID);
+      if (millis() - lastPress > 300) {
+        padID = (padID + 1) & 0x1F;
+        log_d("Changed padID to %d\n", padID);
+      }
+    }
+  }
+  previousButtonState = buttonState;
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/Gamepad/ci.json b/libraries/USB/examples/Gamepad/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/Gamepad/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/HIDVendor/HIDVendor.ino b/libraries/USB/examples/HIDVendor/HIDVendor.ino
new file mode 100644
index 00000000000..f55abeb1589
--- /dev/null
+++ b/libraries/USB/examples/HIDVendor/HIDVendor.ino
@@ -0,0 +1,57 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+#include "USBHIDVendor.h"
+USBHIDVendor Vendor;
+
+const int buttonPin = 0;
+int previousButtonState = HIGH;
+
+static void vendorEventCallback(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == ARDUINO_USB_HID_VENDOR_EVENTS) {
+    arduino_usb_hid_vendor_event_data_t *data = (arduino_usb_hid_vendor_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_HID_VENDOR_GET_FEATURE_EVENT: Serial.printf("HID VENDOR GET FEATURE: len:%u\n", data->len); break;
+      case ARDUINO_USB_HID_VENDOR_SET_FEATURE_EVENT:
+        Serial.printf("HID VENDOR SET FEATURE: len:%u\n", data->len);
+        for (uint16_t i = 0; i < data->len; i++) {
+          Serial.printf("0x%02X ", *(data->buffer));
+        }
+        Serial.println();
+        break;
+      case ARDUINO_USB_HID_VENDOR_OUTPUT_EVENT:
+        Serial.printf("HID VENDOR OUTPUT: len:%u\n", data->len);
+        // for(uint16_t i=0; i<data->len; i++){
+        //   Serial.write(Vendor.read());
+        // }
+        break;
+
+      default: break;
+    }
+  }
+}
+
+void setup() {
+  pinMode(buttonPin, INPUT_PULLUP);
+  Serial.begin(115200);
+  Vendor.onEvent(vendorEventCallback);
+  Vendor.begin();
+  USB.begin();
+}
+
+void loop() {
+  int buttonState = digitalRead(buttonPin);
+  if ((buttonState != previousButtonState) && (buttonState == LOW)) {
+    Vendor.println("Hello World!");
+  }
+  previousButtonState = buttonState;
+  while (Vendor.available()) {
+    Serial.write(Vendor.read());
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/HIDVendor/ci.json b/libraries/USB/examples/HIDVendor/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/HIDVendor/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/Keyboard/KeyboardLogout/KeyboardLogout.ino b/libraries/USB/examples/Keyboard/KeyboardLogout/KeyboardLogout.ino
new file mode 100644
index 00000000000..3a3e7f2e3a9
--- /dev/null
+++ b/libraries/USB/examples/Keyboard/KeyboardLogout/KeyboardLogout.ino
@@ -0,0 +1,104 @@
+/*
+  Keyboard logout
+
+  This sketch demonstrates the Keyboard library.
+
+  When you connect pin 2 to ground, it performs a logout.
+  It uses keyboard combinations to do this, as follows:
+
+  On Windows, CTRL-ALT-DEL followed by ALT-l
+  On Ubuntu, CTRL-ALT-DEL, and ENTER
+  On OSX, CMD-SHIFT-q
+
+  To wake: Spacebar.
+
+  Circuit:
+  - Arduino Leonardo or Micro
+  - wire to connect D2 to ground
+
+  created 6 Mar 2012
+  modified 27 Mar 2012
+  by Tom Igoe
+
+  This example is in the public domain.
+
+  http://www.arduino.cc/en/Tutorial/KeyboardLogout
+*/
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#define OSX     0
+#define WINDOWS 1
+#define UBUNTU  2
+
+#include "USB.h"
+#include "USBHIDKeyboard.h"
+USBHIDKeyboard Keyboard;
+
+// change this to match your platform:
+int platform = OSX;
+
+const int buttonPin = 0;  // input pin for pushbutton
+
+void setup() {
+  // make pin 0 an input and turn on the pull-up resistor so it goes high unless
+  // connected to ground:
+  pinMode(buttonPin, INPUT_PULLUP);
+  Keyboard.begin();
+  USB.begin();
+}
+
+void loop() {
+  while (digitalRead(buttonPin) == HIGH) {
+    // do nothing until pin 2 goes low
+    delay(500);
+  }
+  delay(1000);
+
+  switch (platform) {
+    case OSX:
+      Keyboard.press(KEY_LEFT_GUI);
+      // Shift-Q logs out:
+      Keyboard.press(KEY_LEFT_SHIFT);
+      Keyboard.press('Q');
+      delay(100);
+      Keyboard.releaseAll();
+      // enter:
+      Keyboard.write(KEY_RETURN);
+      break;
+    case WINDOWS:
+      // CTRL-ALT-DEL:
+      Keyboard.press(KEY_LEFT_CTRL);
+      Keyboard.press(KEY_LEFT_ALT);
+      Keyboard.press(KEY_DELETE);
+      delay(100);
+      Keyboard.releaseAll();
+      // ALT-l:
+      delay(2000);
+      Keyboard.press(KEY_LEFT_ALT);
+      Keyboard.press('l');
+      Keyboard.releaseAll();
+      break;
+    case UBUNTU:
+      // CTRL-ALT-DEL:
+      Keyboard.press(KEY_LEFT_CTRL);
+      Keyboard.press(KEY_LEFT_ALT);
+      Keyboard.press(KEY_DELETE);
+      delay(1000);
+      Keyboard.releaseAll();
+      // Enter to confirm logout:
+      Keyboard.write(KEY_RETURN);
+      break;
+  }
+
+  // do nothing:
+  while (true) {
+    delay(1000);
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/Keyboard/KeyboardLogout/ci.json b/libraries/USB/examples/Keyboard/KeyboardLogout/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/Keyboard/KeyboardLogout/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/Keyboard/KeyboardMessage/KeyboardMessage.ino b/libraries/USB/examples/Keyboard/KeyboardMessage/KeyboardMessage.ino
new file mode 100644
index 00000000000..359e9c52834
--- /dev/null
+++ b/libraries/USB/examples/Keyboard/KeyboardMessage/KeyboardMessage.ino
@@ -0,0 +1,63 @@
+/*
+  Keyboard Message test
+
+  For the Arduino Leonardo and Micro.
+
+  Sends a text string when a button is pressed.
+
+  The circuit:
+  - pushbutton attached from pin 0 to ground
+  - 10 kilohm resistor attached from pin 0 to +5V
+
+  created 24 Oct 2011
+  modified 27 Mar 2012
+  by Tom Igoe
+  modified 11 Nov 2013
+  by Scott Fitzgerald
+
+  This example code is in the public domain.
+
+  http://www.arduino.cc/en/Tutorial/KeyboardMessage
+*/
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#include "USB.h"
+#include "USBHIDKeyboard.h"
+USBHIDKeyboard Keyboard;
+
+const int buttonPin = 0;         // input pin for pushbutton
+int previousButtonState = HIGH;  // for checking the state of a pushButton
+int counter = 0;                 // button push counter
+
+void setup() {
+  // make the pushButton pin an input:
+  pinMode(buttonPin, INPUT_PULLUP);
+  // initialize control over the keyboard:
+  Keyboard.begin();
+  USB.begin();
+}
+
+void loop() {
+  // read the pushbutton:
+  int buttonState = digitalRead(buttonPin);
+  // if the button state has changed,
+  if ((buttonState != previousButtonState)
+      // and it's currently pressed:
+      && (buttonState == LOW)) {
+    // increment the button counter
+    counter++;
+    // type out a message
+    Keyboard.print("You pressed the button ");
+    Keyboard.print(counter);
+    Keyboard.println(" times.");
+  }
+  // save the current button state for comparison next time:
+  previousButtonState = buttonState;
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/Keyboard/KeyboardMessage/ci.json b/libraries/USB/examples/Keyboard/KeyboardMessage/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/Keyboard/KeyboardMessage/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/Keyboard/KeyboardReprogram/KeyboardReprogram.ino b/libraries/USB/examples/Keyboard/KeyboardReprogram/KeyboardReprogram.ino
new file mode 100644
index 00000000000..a2401086a9a
--- /dev/null
+++ b/libraries/USB/examples/Keyboard/KeyboardReprogram/KeyboardReprogram.ino
@@ -0,0 +1,117 @@
+/*
+  Arduino Programs Blink
+
+  This sketch demonstrates the Keyboard library.
+
+  For Leonardo and Due boards only.
+
+  When you connect pin 2 to ground, it creates a new window with a key
+  combination (CTRL-N), then types in the Blink sketch, then auto-formats the
+  text using another key combination (CTRL-T), then uploads the sketch to the
+  currently selected Arduino using a final key combination (CTRL-U).
+
+  Circuit:
+  - Arduino Leonardo, Micro, Due, LilyPad USB, or Yún
+  - wire to connect D2 to ground
+
+  created 5 Mar 2012
+  modified 29 Mar 2012
+  by Tom Igoe
+  modified 3 May 2014
+  by Scott Fitzgerald
+
+  This example is in the public domain.
+
+  http://www.arduino.cc/en/Tutorial/KeyboardReprogram
+*/
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#include "USB.h"
+#include "USBHIDKeyboard.h"
+USBHIDKeyboard Keyboard;
+
+const int buttonPin = 0;  // input pin for pushbutton
+
+// use this option for OSX.
+// Comment it out if using Windows or Linux:
+char ctrlKey = KEY_LEFT_GUI;
+// use this option for Windows and Linux.
+// leave commented out if using OSX:
+//  char ctrlKey = KEY_LEFT_CTRL;
+
+void setup() {
+  // make pin 0 an input and turn on the pull-up resistor so it goes high unless
+  // connected to ground:
+  pinMode(buttonPin, INPUT_PULLUP);
+  // initialize control over the keyboard:
+  Keyboard.begin();
+  USB.begin();
+}
+
+void loop() {
+  while (digitalRead(buttonPin) == HIGH) {
+    // do nothing until pin 0 goes low
+    delay(500);
+  }
+  delay(1000);
+  // new document:
+  Keyboard.press(ctrlKey);
+  Keyboard.press('n');
+  delay(100);
+  Keyboard.releaseAll();
+  // wait for new window to open:
+  delay(1000);
+
+  // versions of the Arduino IDE after 1.5 pre-populate new sketches with
+  // setup() and loop() functions let's clear the window before typing anything new
+  // select all
+  Keyboard.press(ctrlKey);
+  Keyboard.press('a');
+  delay(500);
+  Keyboard.releaseAll();
+  // delete the selected text
+  Keyboard.write(KEY_BACKSPACE);
+  delay(500);
+
+  // Type out "blink":
+  Keyboard.println("void setup() {");
+  Keyboard.println("pinMode(13, OUTPUT);");
+  Keyboard.println("}");
+  Keyboard.println();
+  Keyboard.println("void loop() {");
+  Keyboard.println("digitalWrite(13, HIGH);");
+  Keyboard.print("delay(3000);");
+  // 3000 ms is too long. Delete it:
+  for (int keystrokes = 0; keystrokes < 6; keystrokes++) {
+    delay(500);
+    Keyboard.write(KEY_BACKSPACE);
+  }
+  // make it 1000 instead:
+  Keyboard.println("1000);");
+  Keyboard.println("digitalWrite(13, LOW);");
+  Keyboard.println("delay(1000);");
+  Keyboard.println("}");
+  // tidy up:
+  Keyboard.press(ctrlKey);
+  Keyboard.press('t');
+  delay(100);
+  Keyboard.releaseAll();
+  delay(3000);
+  // upload code:
+  Keyboard.press(ctrlKey);
+  Keyboard.press('u');
+  delay(100);
+  Keyboard.releaseAll();
+
+  // wait for the sweet oblivion of reprogramming:
+  while (true) {
+    delay(1000);
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/Keyboard/KeyboardReprogram/ci.json b/libraries/USB/examples/Keyboard/KeyboardReprogram/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/Keyboard/KeyboardReprogram/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/Keyboard/KeyboardSerial/KeyboardSerial.ino b/libraries/USB/examples/Keyboard/KeyboardSerial/KeyboardSerial.ino
new file mode 100644
index 00000000000..46da87d2ce3
--- /dev/null
+++ b/libraries/USB/examples/Keyboard/KeyboardSerial/KeyboardSerial.ino
@@ -0,0 +1,48 @@
+/*
+  Keyboard test
+
+  Reads a byte from the serial port, sends a keystroke back.
+  The sent keystroke is one higher than what's received, e.g. if you send a,
+  you get b, send A you get B, and so forth.
+
+  The circuit:
+  - none
+
+  created 21 Oct 2011
+  modified 27 Mar 2012
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  http://www.arduino.cc/en/Tutorial/KeyboardSerial
+*/
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#include "USB.h"
+#include "USBHIDKeyboard.h"
+USBHIDKeyboard Keyboard;
+
+void setup() {
+  // open the serial port:
+  Serial.begin(115200);
+  // initialize control over the keyboard:
+  Keyboard.begin();
+  USB.begin();
+}
+
+void loop() {
+  // check for incoming serial data:
+  if (Serial.available() > 0) {
+    // read incoming serial data:
+    char inChar = Serial.read();
+    // Type the next ASCII value from what you received:
+    Keyboard.write(inChar + 1);
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/Keyboard/KeyboardSerial/ci.json b/libraries/USB/examples/Keyboard/KeyboardSerial/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/Keyboard/KeyboardSerial/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/KeyboardAndMouseControl/KeyboardAndMouseControl.ino b/libraries/USB/examples/KeyboardAndMouseControl/KeyboardAndMouseControl.ino
new file mode 100644
index 00000000000..02cb4f57da5
--- /dev/null
+++ b/libraries/USB/examples/KeyboardAndMouseControl/KeyboardAndMouseControl.ino
@@ -0,0 +1,103 @@
+/*
+  KeyboardAndMouseControl
+
+  Hardware:
+  - five pushbuttons attached to D12, D13, D14, D15, D0
+
+  The mouse movement is always relative. This sketch reads four pushbuttons, and
+  uses them to set the movement of the mouse.
+
+  WARNING: When you use the Mouse.move() command, the Arduino takes over your
+  mouse! Make sure you have control before you use the mouse commands.
+
+  created 15 Mar 2012
+  modified 27 Mar 2012
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  http://www.arduino.cc/en/Tutorial/KeyboardAndMouseControl
+*/
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#include "USB.h"
+#include "USBHIDMouse.h"
+#include "USBHIDKeyboard.h"
+USBHIDMouse Mouse;
+USBHIDKeyboard Keyboard;
+
+// set pin numbers for the five buttons:
+const int upButton = 12;
+const int downButton = 13;
+const int leftButton = 14;
+const int rightButton = 15;
+const int mouseButton = 0;
+
+void setup() {  // initialize the buttons' inputs:
+  pinMode(upButton, INPUT_PULLUP);
+  pinMode(downButton, INPUT_PULLUP);
+  pinMode(leftButton, INPUT_PULLUP);
+  pinMode(rightButton, INPUT_PULLUP);
+  pinMode(mouseButton, INPUT_PULLUP);
+
+  Serial.begin(115200);
+  // initialize mouse control:
+  Mouse.begin();
+  Keyboard.begin();
+  USB.begin();
+}
+
+void loop() {
+  // use serial input to control the mouse:
+  if (Serial.available() > 0) {
+    char inChar = Serial.read();
+
+    switch (inChar) {
+      case 'u':
+        // move mouse up
+        Mouse.move(0, -40);
+        break;
+      case 'd':
+        // move mouse down
+        Mouse.move(0, 40);
+        break;
+      case 'l':
+        // move mouse left
+        Mouse.move(-40, 0);
+        break;
+      case 'r':
+        // move mouse right
+        Mouse.move(40, 0);
+        break;
+      case 'm':
+        // perform mouse left click
+        Mouse.click(MOUSE_LEFT);
+        break;
+    }
+  }
+
+  // use the pushbuttons to control the keyboard:
+  if (digitalRead(upButton) == LOW) {
+    Keyboard.write('u');
+  }
+  if (digitalRead(downButton) == LOW) {
+    Keyboard.write('d');
+  }
+  if (digitalRead(leftButton) == LOW) {
+    Keyboard.write('l');
+  }
+  if (digitalRead(rightButton) == LOW) {
+    Keyboard.write('r');
+  }
+  if (digitalRead(mouseButton) == LOW) {
+    Keyboard.write('m');
+  }
+  delay(5);
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/KeyboardAndMouseControl/ci.json b/libraries/USB/examples/KeyboardAndMouseControl/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/KeyboardAndMouseControl/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/MIDI/MidiController/MidiController.ino b/libraries/USB/examples/MIDI/MidiController/MidiController.ino
new file mode 100644
index 00000000000..2871d3b1a52
--- /dev/null
+++ b/libraries/USB/examples/MIDI/MidiController/MidiController.ino
@@ -0,0 +1,111 @@
+/*
+This is an example of a Simple MIDI Controller using an ESP32 with a native USB support stack (S2, S3,
+etc.).
+
+For a hookup guide and more information on reading the ADC, please see:
+https://randomnerdtutorials.com/esp32-adc-analog-read-arduino-ide/ (Note: This sketch uses GPIO05)
+
+For best results, it is recommended to add an extra offset resistor between VCC and the potentiometer.
+(For a standard 10kOhm potentiometer, 3kOhm - 4kOhm will do.)
+
+View this sketch in action on YouTube: https://youtu.be/Y9TLXs_3w1M
+*/
+#if ARDUINO_USB_MODE
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#include <math.h>
+
+#include "USB.h"
+#include "USBMIDI.h"
+USBMIDI MIDI;
+
+#define MIDI_NOTE_C4 60
+
+#define MIDI_CC_CUTOFF 74
+
+///// ADC & Controller Input Handling /////
+
+#define CONTROLLER_PIN  5
+
+// ESP32 ADC needs a ton of smoothing
+#define SMOOTHING_VALUE 1000
+static double controllerInputValue = 0;
+
+void updateControllerInputValue() {
+  controllerInputValue = (controllerInputValue * (SMOOTHING_VALUE - 1) + analogRead(CONTROLLER_PIN)) / SMOOTHING_VALUE;
+}
+
+void primeControllerInputValue() {
+  for (int i = 0; i < SMOOTHING_VALUE; i++) {
+    updateControllerInputValue();
+  }
+}
+
+uint16_t readControllerValue() {
+  // Lower ADC input amplitude to get a stable value
+  return round(controllerInputValue / 12);
+}
+
+///// Button Handling /////
+
+#define BUTTON_PIN 0
+
+// Simple button state transition function with debounce
+// (See also: https://tinyurl.com/simple-debounce)
+#define PRESSED    0xff00
+#define RELEASED   0xfe1f
+uint16_t getButtonEvent() {
+  static uint16_t state = 0;
+  state = (state << 1) | digitalRead(BUTTON_PIN) | 0xfe00;
+  return state;
+}
+
+///// Arduino Hooks /////
+
+void setup() {
+  Serial.begin(115200);
+  MIDI.begin();
+  USB.begin();
+  pinMode(BUTTON_PIN, INPUT_PULLUP);
+  primeControllerInputValue();
+}
+
+void loop() {
+  uint16_t newControllerValue = readControllerValue();
+  static uint16_t lastControllerValue = 0;
+
+  // Auto-calibrate the controller range
+  static uint16_t maxControllerValue = 0;
+  static uint16_t minControllerValue = 0xFFFF;
+
+  if (newControllerValue < minControllerValue) {
+    minControllerValue = newControllerValue;
+  }
+  if (newControllerValue > maxControllerValue) {
+    maxControllerValue = newControllerValue;
+  }
+
+  // Send update if the controller value has changed
+  if (lastControllerValue != newControllerValue) {
+    lastControllerValue = newControllerValue;
+
+    // Can't map if the range is zero
+    if (minControllerValue != maxControllerValue) {
+      MIDI.controlChange(MIDI_CC_CUTOFF, map(newControllerValue, minControllerValue, maxControllerValue, 0, 127));
+    }
+  }
+
+  updateControllerInputValue();
+
+  // Hook Button0 to a MIDI note so that we can observe
+  // the CC effect without the need for a MIDI keyboard.
+  switch (getButtonEvent()) {
+    case PRESSED:  MIDI.noteOn(MIDI_NOTE_C4, 64); break;
+    case RELEASED: MIDI.noteOff(MIDI_NOTE_C4, 0); break;
+    default:       break;
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/MIDI/MidiController/ci.json b/libraries/USB/examples/MIDI/MidiController/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/MIDI/MidiController/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/MIDI/MidiInterface/MidiInterface.ino b/libraries/USB/examples/MIDI/MidiInterface/MidiInterface.ino
new file mode 100644
index 00000000000..e3ad1c4e028
--- /dev/null
+++ b/libraries/USB/examples/MIDI/MidiInterface/MidiInterface.ino
@@ -0,0 +1,70 @@
+/*
+This is an example of using an ESP32 with a native USB support stack (S2, S3, etc.) as a Serial MIDI to
+USB MIDI bridge (AKA "A MIDI Interface").
+
+View this sketch in action on YouTube: https://youtu.be/BXG5i55I9s0
+
+Receiving and decoding USB MIDI 1.0 packets is a more advanced topic than sending MIDI over USB,
+please refer to the other examples in this library for a more basic example of sending MIDI over USB.
+
+This example should still be self explanatory, please refer to the USB MIDI 1.0 specification (the spec)
+for a more in-depth explanation of the packet format.
+
+For the spec please visit: https://www.midi.org/specifications-old/item/usb-midi-1-0-specification
+
+Note: Because ESP32 works at VCC=3.3v normal schematics for Serial MIDI connections will not suffice,
+      Please refer to the Updated MIDI 1.1 Electrical Specification [1] for information on how to hookup
+      Serial MIDI for 3.3v devices.
+
+[1] - https://www.midi.org/specifications/midi-transports-specifications/5-pin-din-electrical-specs
+*/
+#if ARDUINO_USB_MODE
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#include "USB.h"
+#include "USBMIDI.h"
+USBMIDI MIDI;
+
+#define MIDI_RX 39
+#define MIDI_TX 40
+
+void setup() {
+  // USBCDC Serial
+  Serial.begin(115200);
+
+  // HW UART Serial
+  Serial1.begin(31250, SERIAL_8N1, MIDI_RX, MIDI_TX);
+
+  MIDI.begin();
+  USB.begin();
+}
+
+void loop() {
+  // MIDI Serial 1.0 to USB MIDI 1.0
+  if (Serial1.available()) {
+    byte data = Serial1.read();
+    MIDI.write(data);
+  }
+
+  // USB MIDI 1.0 to MIDI Serial 1.0
+  midiEventPacket_t midi_packet_in = {0, 0, 0, 0};
+  // See Chapter 4: USB-MIDI Event Packets (page 16) of the spec.
+  int8_t cin_to_midix_size[16] = {-1, -1, 2, 3, 3, 1, 2, 3, 3, 3, 3, 3, 2, 2, 3, 1};
+
+  if (MIDI.readPacket(&midi_packet_in)) {
+    midi_code_index_number_t code_index_num = MIDI_EP_HEADER_CIN_GET(midi_packet_in.header);
+    int8_t midix_size = cin_to_midix_size[code_index_num];
+
+    // We skip Misc and Cable Events for simplicity
+    if (code_index_num >= 0x2) {
+      for (int i = 0; i < midix_size; i++) {
+        Serial1.write(((uint8_t *)&midi_packet_in)[i + 1]);
+      }
+      Serial1.flush();
+    }
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/MIDI/MidiInterface/ci.json b/libraries/USB/examples/MIDI/MidiInterface/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/MIDI/MidiInterface/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/MIDI/MidiMusicBox/MidiMusicBox.ino b/libraries/USB/examples/MIDI/MidiMusicBox/MidiMusicBox.ino
new file mode 100644
index 00000000000..6a31d9a37eb
--- /dev/null
+++ b/libraries/USB/examples/MIDI/MidiMusicBox/MidiMusicBox.ino
@@ -0,0 +1,59 @@
+/*
+This is an example of a MIDI Music Box using an ESP32 with a native USB support stack (S2, S3, etc.).
+
+Every time the button on the ESP32 board (attached to pin 0) is pressed the next note of a melody is
+played. It is up to the user to get the timing of the button presses right.
+
+One simple way of running this sketch is to download the Pianoteq evaluation version, because upon
+application start it automatically listens to the first MIDI Input on Channel 1, which is the case,
+if the ESP32 is the only MIDI device attached.
+
+View this sketch in action on YouTube: https://youtu.be/JFrc-wSmcus
+*/
+#if ARDUINO_USB_MODE
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#include "USB.h"
+#include "USBMIDI.h"
+USBMIDI MIDI;
+
+#define END_OF_SONG 255
+uint8_t notes[] = {END_OF_SONG, 71, 76, 79, 78, 76, 83, 81, 78, 76, 79, 78, 75, 77, 71};
+uint8_t noteIndex = 0;  // From 0 to sizeof(notes)
+#define SONG_LENGTH (sizeof(notes) - 1)  // END_OF_SONG does not attribute to the length.
+
+#define BUTTON_PIN 0
+
+// Simple button press check with debounce
+// (See also: https://tinyurl.com/simple-debounce)
+bool isButtonPressed() {
+  static uint16_t state = 0;
+  state = (state << 1) | digitalRead(BUTTON_PIN) | 0xfe00;
+  return (state == 0xff00);
+}
+
+void setup() {
+  Serial.begin(115200);
+  // Make the BUTTON_PIN an input:
+  pinMode(BUTTON_PIN, INPUT_PULLUP);
+
+  MIDI.begin();
+  USB.begin();
+}
+
+void loop() {
+  if (isButtonPressed()) {
+    // Stop current note
+    MIDI.noteOff(notes[noteIndex]);
+
+    // Play next note
+    noteIndex = noteIndex < SONG_LENGTH ? noteIndex + 1 : 0;
+    if (notes[noteIndex] != END_OF_SONG) {
+      MIDI.noteOn(notes[noteIndex], 64);
+    }
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/MIDI/MidiMusicBox/ci.json b/libraries/USB/examples/MIDI/MidiMusicBox/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/MIDI/MidiMusicBox/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/MIDI/ReceiveMidi/ReceiveMidi.ino b/libraries/USB/examples/MIDI/ReceiveMidi/ReceiveMidi.ino
new file mode 100644
index 00000000000..09a3e2a7b5c
--- /dev/null
+++ b/libraries/USB/examples/MIDI/ReceiveMidi/ReceiveMidi.ino
@@ -0,0 +1,84 @@
+/*
+This is an example of receiving USB MIDI 1.0 messages using an ESP32 with a native USB support stack
+(S2, S3, etc.).
+
+Receiving and decoding USB MIDI 1.0 packets is a more advanced topic than sending MIDI over USB,
+please refer to the other examples in this library for a more basic example of sending MIDI over USB.
+
+This example should still be self explanatory, please refer to the USB MIDI 1.0 specification (the spec)
+for a more in-depth explanation of the packet format.
+
+For the spec please visit: https://www.midi.org/specifications-old/item/usb-midi-1-0-specification
+*/
+#if ARDUINO_USB_MODE
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#include "USB.h"
+#include "USBMIDI.h"
+USBMIDI MIDI;
+
+void setup() {
+  Serial.begin(115200);
+
+  MIDI.begin();
+  USB.begin();
+}
+
+void loop() {
+  midiEventPacket_t midi_packet_in = {0, 0, 0, 0};
+
+  if (MIDI.readPacket(&midi_packet_in)) {
+    printDetails(midi_packet_in);
+  }
+}
+
+void printDetails(midiEventPacket_t &midi_packet_in) {
+  // See Chapter 4: USB-MIDI Event Packets (page 16) of the spec.
+  uint8_t cable_num = MIDI_EP_HEADER_CN_GET(midi_packet_in.header);
+  midi_code_index_number_t code_index_num = MIDI_EP_HEADER_CIN_GET(midi_packet_in.header);
+
+  Serial.println("Received a USB MIDI packet:");
+  Serial.println(".----.-----.--------.--------.--------.");
+  Serial.println("| CN | CIN | STATUS | DATA 0 | DATA 1 |");
+  Serial.println("+----+-----+--------+--------+--------+");
+  Serial.printf("| %d  |  %X  |   %X   |   %X   |   %X   |\n", cable_num, code_index_num, midi_packet_in.byte1, midi_packet_in.byte2, midi_packet_in.byte3);
+  Serial.println("'----'-----'--------.--------'--------'\n");
+  Serial.print("Description: ");
+
+  switch (code_index_num) {
+    case MIDI_CIN_MISC:        Serial.println("This a Miscellaneous event"); break;
+    case MIDI_CIN_CABLE_EVENT: Serial.println("This a Cable event"); break;
+    case MIDI_CIN_SYSCOM_2BYTE:  // 2 byte system common message e.g MTC, SongSelect
+    case MIDI_CIN_SYSCOM_3BYTE:  // 3 byte system common message e.g SPP
+      Serial.println("This a System Common (SysCom) event");
+      break;
+    case MIDI_CIN_SYSEX_START:      // SysEx starts or continue
+    case MIDI_CIN_SYSEX_END_1BYTE:  // SysEx ends with 1 data, or 1 byte system common message
+    case MIDI_CIN_SYSEX_END_2BYTE:  // SysEx ends with 2 data
+    case MIDI_CIN_SYSEX_END_3BYTE:  // SysEx ends with 3 data
+      Serial.println("This a system exclusive (SysEx) event");
+      break;
+    case MIDI_CIN_NOTE_ON:       Serial.printf("This a Note-On event of Note %d with a Velocity of %d\n", midi_packet_in.byte2, midi_packet_in.byte3); break;
+    case MIDI_CIN_NOTE_OFF:      Serial.printf("This a Note-Off event of Note %d with a Velocity of %d\n", midi_packet_in.byte2, midi_packet_in.byte3); break;
+    case MIDI_CIN_POLY_KEYPRESS: Serial.printf("This a Poly Aftertouch event for Note %d and Value %d\n", midi_packet_in.byte2, midi_packet_in.byte3); break;
+    case MIDI_CIN_CONTROL_CHANGE:
+      Serial.printf(
+        "This a Control Change/Continuous Controller (CC) event of Controller %d "
+        "with a Value of %d\n",
+        midi_packet_in.byte2, midi_packet_in.byte3
+      );
+      break;
+    case MIDI_CIN_PROGRAM_CHANGE:   Serial.printf("This a Program Change event with a Value of %d\n", midi_packet_in.byte2); break;
+    case MIDI_CIN_CHANNEL_PRESSURE: Serial.printf("This a Channel Pressure event with a Value of %d\n", midi_packet_in.byte2); break;
+    case MIDI_CIN_PITCH_BEND_CHANGE:
+      Serial.printf("This a Pitch Bend Change event with a Value of %d\n", ((uint16_t)midi_packet_in.byte2) << 7 | midi_packet_in.byte3);
+      break;
+    case MIDI_CIN_1BYTE_DATA: Serial.printf("This an embedded Serial MIDI event byte with Value %X\n", midi_packet_in.byte1); break;
+  }
+
+  Serial.println();
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/MIDI/ReceiveMidi/ci.json b/libraries/USB/examples/MIDI/ReceiveMidi/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/MIDI/ReceiveMidi/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/Mouse/ButtonMouseControl/ButtonMouseControl.ino b/libraries/USB/examples/Mouse/ButtonMouseControl/ButtonMouseControl.ino
new file mode 100644
index 00000000000..5821e780ee8
--- /dev/null
+++ b/libraries/USB/examples/Mouse/ButtonMouseControl/ButtonMouseControl.ino
@@ -0,0 +1,92 @@
+/*
+  ButtonMouseControl
+
+  Controls the mouse from five pushbuttons on an Arduino Leonardo, Micro or Due.
+
+  Hardware:
+  - five pushbuttons attached to D12, D13, D14, D15, D0
+
+  The mouse movement is always relative. This sketch reads four pushbuttons,
+  and uses them to set the movement of the mouse.
+
+  WARNING: When you use the Mouse.move() command, the Arduino takes over your
+  mouse! Make sure you have control before you use the mouse commands.
+
+  created 15 Mar 2012
+  modified 27 Mar 2012
+  by Tom Igoe
+
+  This example code is in the public domain.
+
+  http://www.arduino.cc/en/Tutorial/ButtonMouseControl
+*/
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+
+#include "USB.h"
+#include "USBHIDMouse.h"
+USBHIDMouse Mouse;
+
+// set pin numbers for the five buttons:
+const int upButton = 12;
+const int downButton = 13;
+const int leftButton = 14;
+const int rightButton = 15;
+const int mouseButton = 0;
+
+int range = 5;           // output range of X or Y movement; affects movement speed
+int responseDelay = 10;  // response delay of the mouse, in ms
+
+void setup() {
+  // initialize the buttons' inputs:
+  pinMode(upButton, INPUT_PULLUP);
+  pinMode(downButton, INPUT_PULLUP);
+  pinMode(leftButton, INPUT_PULLUP);
+  pinMode(rightButton, INPUT_PULLUP);
+  pinMode(mouseButton, INPUT_PULLUP);
+  // initialize mouse control:
+  Mouse.begin();
+  USB.begin();
+}
+
+void loop() {
+  // read the buttons:
+  int upState = digitalRead(upButton);
+  int downState = digitalRead(downButton);
+  int rightState = digitalRead(rightButton);
+  int leftState = digitalRead(leftButton);
+  int clickState = digitalRead(mouseButton);
+
+  // calculate the movement distance based on the button states:
+  int xDistance = (leftState - rightState) * range;
+  int yDistance = (upState - downState) * range;
+
+  // if X or Y is non-zero, move:
+  if ((xDistance != 0) || (yDistance != 0)) {
+    Mouse.move(xDistance, yDistance, 0);
+  }
+
+  // if the mouse button is pressed:
+  if (clickState == LOW) {
+    // if the mouse is not pressed, press it:
+    if (!Mouse.isPressed(MOUSE_LEFT)) {
+      Mouse.press(MOUSE_LEFT);
+    }
+  }
+  // else the mouse button is not pressed:
+  else {
+    // if the mouse is pressed, release it:
+    if (Mouse.isPressed(MOUSE_LEFT)) {
+      Mouse.release(MOUSE_LEFT);
+    }
+  }
+
+  // a delay so the mouse doesn't move too fast:
+  delay(responseDelay);
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/Mouse/ButtonMouseControl/ci.json b/libraries/USB/examples/Mouse/ButtonMouseControl/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/Mouse/ButtonMouseControl/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/SystemControl/SystemControl.ino b/libraries/USB/examples/SystemControl/SystemControl.ino
new file mode 100644
index 00000000000..019ed032812
--- /dev/null
+++ b/libraries/USB/examples/SystemControl/SystemControl.ino
@@ -0,0 +1,29 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+#include "USBHIDSystemControl.h"
+USBHIDSystemControl SystemControl;
+
+const int buttonPin = 0;
+int previousButtonState = HIGH;
+
+void setup() {
+  pinMode(buttonPin, INPUT_PULLUP);
+  SystemControl.begin();
+  USB.begin();
+}
+
+void loop() {
+  int buttonState = digitalRead(buttonPin);
+  if ((buttonState != previousButtonState) && (buttonState == LOW)) {
+    SystemControl.press(SYSTEM_CONTROL_POWER_OFF);
+    SystemControl.release();
+  }
+  previousButtonState = buttonState;
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/SystemControl/ci.json b/libraries/USB/examples/SystemControl/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/SystemControl/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/USBMSC/USBMSC.ino b/libraries/USB/examples/USBMSC/USBMSC.ino
new file mode 100644
index 00000000000..532691ba63d
--- /dev/null
+++ b/libraries/USB/examples/USBMSC/USBMSC.ino
@@ -0,0 +1,166 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+#include "USBMSC.h"
+
+USBMSC MSC;
+
+#define FAT_U8(v)          ((v) & 0xFF)
+#define FAT_U16(v)         FAT_U8(v), FAT_U8((v) >> 8)
+#define FAT_U32(v)         FAT_U8(v), FAT_U8((v) >> 8), FAT_U8((v) >> 16), FAT_U8((v) >> 24)
+#define FAT_MS2B(s, ms)    FAT_U8(((((s) & 0x1) * 1000) + (ms)) / 10)
+#define FAT_HMS2B(h, m, s) FAT_U8(((s) >> 1) | (((m) & 0x7) << 5)), FAT_U8((((m) >> 3) & 0x7) | ((h) << 3))
+#define FAT_YMD2B(y, m, d) FAT_U8(((d) & 0x1F) | (((m) & 0x7) << 5)), FAT_U8((((m) >> 3) & 0x1) | ((((y) - 1980) & 0x7F) << 1))
+#define FAT_TBL2B(l, h)    FAT_U8(l), FAT_U8(((l >> 8) & 0xF) | ((h << 4) & 0xF0)), FAT_U8(h >> 4)
+
+#define README_CONTENTS \
+  "This is tinyusb's MassStorage Class demo.\r\n\r\nIf you find any bugs or get any questions, feel free to file an\r\nissue at github.com/hathach/tinyusb"
+
+static const uint32_t DISK_SECTOR_COUNT = 2 * 8;   // 8KB is the smallest size that windows allow to mount
+static const uint16_t DISK_SECTOR_SIZE = 512;      // Should be 512
+static const uint16_t DISC_SECTORS_PER_TABLE = 1;  //each table sector can fit 170KB (340 sectors)
+
+static uint8_t msc_disk[DISK_SECTOR_COUNT][DISK_SECTOR_SIZE] = {
+  //------------- Block0: Boot Sector -------------//
+  {                                                        // Header (62 bytes)
+   0xEB, 0x3C, 0x90,                                       //jump_instruction
+   'M', 'S', 'D', 'O', 'S', '5', '.', '0',                 //oem_name
+   FAT_U16(DISK_SECTOR_SIZE),                              //bytes_per_sector
+   FAT_U8(1),                                              //sectors_per_cluster
+   FAT_U16(1),                                             //reserved_sectors_count
+   FAT_U8(1),                                              //file_alloc_tables_num
+   FAT_U16(16),                                            //max_root_dir_entries
+   FAT_U16(DISK_SECTOR_COUNT),                             //fat12_sector_num
+   0xF8,                                                   //media_descriptor
+   FAT_U16(DISC_SECTORS_PER_TABLE),                        //sectors_per_alloc_table;//FAT12 and FAT16
+   FAT_U16(1),                                             //sectors_per_track;//A value of 0 may indicate LBA-only access
+   FAT_U16(1),                                             //num_heads
+   FAT_U32(0),                                             //hidden_sectors_count
+   FAT_U32(0),                                             //total_sectors_32
+   0x00,                                                   //physical_drive_number;0x00 for (first) removable media, 0x80 for (first) fixed disk
+   0x00,                                                   //reserved
+   0x29,                                                   //extended_boot_signature;//should be 0x29
+   FAT_U32(0x1234),                                        //serial_number: 0x1234 => 1234
+   'T', 'i', 'n', 'y', 'U', 'S', 'B', ' ', 'M', 'S', 'C',  //volume_label padded with spaces (0x20)
+   'F', 'A', 'T', '1', '2', ' ', ' ', ' ',                 //file_system_type padded with spaces (0x20)
+
+   // Zero up to 2 last bytes of FAT magic code (448 bytes)
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+   //boot signature (2 bytes)
+   0x55, 0xAA
+  },
+
+  //------------- Block1: FAT12 Table -------------//
+  {
+    FAT_TBL2B(0xFF8, 0xFFF), FAT_TBL2B(0xFFF, 0x000)  // first 2 entries must be 0xFF8 0xFFF, third entry is cluster end of readme file
+  },
+
+  //------------- Block2: Root Directory -------------//
+  {
+    // first entry is volume label
+    'E', 'S', 'P', '3', '2', 'S', '2', ' ', 'M', 'S', 'C',
+    0x08,                                                                                                                 //FILE_ATTR_VOLUME_LABEL
+    0x00, FAT_MS2B(0, 0), FAT_HMS2B(0, 0, 0), FAT_YMD2B(0, 0, 0), FAT_YMD2B(0, 0, 0), FAT_U16(0), FAT_HMS2B(13, 42, 30),  //last_modified_hms
+    FAT_YMD2B(2018, 11, 5),                                                                                               //last_modified_ymd
+    FAT_U16(0), FAT_U32(0),
+
+    // second entry is readme file
+    'R', 'E', 'A', 'D', 'M', 'E', ' ', ' ',  //file_name[8]; padded with spaces (0x20)
+    'T', 'X', 'T',                           //file_extension[3]; padded with spaces (0x20)
+    0x20,                                    //file attributes: FILE_ATTR_ARCHIVE
+    0x00,                                    //ignore
+    FAT_MS2B(1, 980),                        //creation_time_10_ms (max 199x10 = 1s 990ms)
+    FAT_HMS2B(13, 42, 36),                   //create_time_hms [5:6:5] => h:m:(s/2)
+    FAT_YMD2B(2018, 11, 5),                  //create_time_ymd [7:4:5] => (y+1980):m:d
+    FAT_YMD2B(2020, 11, 5),                  //last_access_ymd
+    FAT_U16(0),                              //extended_attributes
+    FAT_HMS2B(13, 44, 16),                   //last_modified_hms
+    FAT_YMD2B(2019, 11, 5),                  //last_modified_ymd
+    FAT_U16(2),                              //start of file in cluster
+    FAT_U32(sizeof(README_CONTENTS) - 1)     //file size
+  },
+
+  //------------- Block3: Readme Content -------------//
+  README_CONTENTS
+};
+
+static int32_t onWrite(uint32_t lba, uint32_t offset, uint8_t *buffer, uint32_t bufsize) {
+  Serial.printf("MSC WRITE: lba: %lu, offset: %lu, bufsize: %lu\n", lba, offset, bufsize);
+  memcpy(msc_disk[lba] + offset, buffer, bufsize);
+  return bufsize;
+}
+
+static int32_t onRead(uint32_t lba, uint32_t offset, void *buffer, uint32_t bufsize) {
+  Serial.printf("MSC READ: lba: %lu, offset: %lu, bufsize: %lu\n", lba, offset, bufsize);
+  memcpy(buffer, msc_disk[lba] + offset, bufsize);
+  return bufsize;
+}
+
+static bool onStartStop(uint8_t power_condition, bool start, bool load_eject) {
+  Serial.printf("MSC START/STOP: power: %u, start: %u, eject: %u\n", power_condition, start, load_eject);
+  return true;
+}
+
+static void usbEventCallback(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == ARDUINO_USB_EVENTS) {
+    arduino_usb_event_data_t *data = (arduino_usb_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_STARTED_EVENT: Serial.println("USB PLUGGED"); break;
+      case ARDUINO_USB_STOPPED_EVENT: Serial.println("USB UNPLUGGED"); break;
+      case ARDUINO_USB_SUSPEND_EVENT: Serial.printf("USB SUSPENDED: remote_wakeup_en: %u\n", data->suspend.remote_wakeup_en); break;
+      case ARDUINO_USB_RESUME_EVENT:  Serial.println("USB RESUMED"); break;
+
+      default: break;
+    }
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+
+  USB.onEvent(usbEventCallback);
+  MSC.vendorID("ESP32");       //max 8 chars
+  MSC.productID("USB_MSC");    //max 16 chars
+  MSC.productRevision("1.0");  //max 4 chars
+  MSC.onStartStop(onStartStop);
+  MSC.onRead(onRead);
+  MSC.onWrite(onWrite);
+
+  MSC.mediaPresent(true);
+  MSC.isWritable(true);  // true if writable, false if read-only
+
+  MSC.begin(DISK_SECTOR_COUNT, DISK_SECTOR_SIZE);
+  USB.begin();
+}
+
+void loop() {
+  // put your main code here, to run repeatedly:
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/USBMSC/ci.json b/libraries/USB/examples/USBMSC/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/USBMSC/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/USBSerial/USBSerial.ino b/libraries/USB/examples/USBSerial/USBSerial.ino
new file mode 100644
index 00000000000..427b2f7d116
--- /dev/null
+++ b/libraries/USB/examples/USBSerial/USBSerial.ino
@@ -0,0 +1,72 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+
+#if !ARDUINO_USB_CDC_ON_BOOT
+USBCDC USBSerial;
+#endif
+
+static void usbEventCallback(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == ARDUINO_USB_EVENTS) {
+    arduino_usb_event_data_t *data = (arduino_usb_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_STARTED_EVENT: Serial.println("USB PLUGGED"); break;
+      case ARDUINO_USB_STOPPED_EVENT: Serial.println("USB UNPLUGGED"); break;
+      case ARDUINO_USB_SUSPEND_EVENT: Serial.printf("USB SUSPENDED: remote_wakeup_en: %u\n", data->suspend.remote_wakeup_en); break;
+      case ARDUINO_USB_RESUME_EVENT:  Serial.println("USB RESUMED"); break;
+
+      default: break;
+    }
+  } else if (event_base == ARDUINO_USB_CDC_EVENTS) {
+    arduino_usb_cdc_event_data_t *data = (arduino_usb_cdc_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_CDC_CONNECTED_EVENT:    Serial.println("CDC CONNECTED"); break;
+      case ARDUINO_USB_CDC_DISCONNECTED_EVENT: Serial.println("CDC DISCONNECTED"); break;
+      case ARDUINO_USB_CDC_LINE_STATE_EVENT:   Serial.printf("CDC LINE STATE: dtr: %u, rts: %u\n", data->line_state.dtr, data->line_state.rts); break;
+      case ARDUINO_USB_CDC_LINE_CODING_EVENT:
+        Serial.printf(
+          "CDC LINE CODING: bit_rate: %lu, data_bits: %u, stop_bits: %u, parity: %u\n", data->line_coding.bit_rate, data->line_coding.data_bits,
+          data->line_coding.stop_bits, data->line_coding.parity
+        );
+        break;
+      case ARDUINO_USB_CDC_RX_EVENT:
+        Serial.printf("CDC RX [%u]:", data->rx.len);
+        {
+          uint8_t buf[data->rx.len];
+          size_t len = USBSerial.read(buf, data->rx.len);
+          Serial.write(buf, len);
+        }
+        Serial.println();
+        break;
+      case ARDUINO_USB_CDC_RX_OVERFLOW_EVENT: Serial.printf("CDC RX Overflow of %d bytes", data->rx_overflow.dropped_bytes); break;
+
+      default: break;
+    }
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+
+  USB.onEvent(usbEventCallback);
+  USBSerial.onEvent(usbEventCallback);
+
+  USBSerial.begin();
+  USB.begin();
+}
+
+void loop() {
+  while (Serial.available()) {
+    size_t l = Serial.available();
+    uint8_t b[l];
+    l = Serial.read(b, l);
+    USBSerial.write(b, l);
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/USBSerial/ci.json b/libraries/USB/examples/USBSerial/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/USBSerial/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/USBVendor/USBVendor.ino b/libraries/USB/examples/USBVendor/USBVendor.ino
new file mode 100644
index 00000000000..43a6a66ea37
--- /dev/null
+++ b/libraries/USB/examples/USBVendor/USBVendor.ino
@@ -0,0 +1,186 @@
+#ifndef ARDUINO_USB_MODE
+#error This ESP32 SoC has no Native USB interface
+#elif ARDUINO_USB_MODE == 1
+#warning This sketch should be used when USB is in OTG mode
+void setup() {}
+void loop() {}
+#else
+#include "USB.h"
+#include "USBVendor.h"
+
+USBVendor Vendor;
+const int buttonPin = 0;
+
+//CDC Control Requests
+#define REQUEST_SET_LINE_CODING        0x20
+#define REQUEST_GET_LINE_CODING        0x21
+#define REQUEST_SET_CONTROL_LINE_STATE 0x22
+
+//CDC Line Coding Control Request Structure
+typedef struct __attribute__((packed)) {
+  uint32_t bit_rate;
+  uint8_t stop_bits;  //0: 1 stop bit, 1: 1.5 stop bits, 2: 2 stop bits
+  uint8_t parity;     //0: None, 1: Odd, 2: Even, 3: Mark, 4: Space
+  uint8_t data_bits;  //5, 6, 7, 8 or 16
+} request_line_coding_t;
+
+static request_line_coding_t vendor_line_coding = {9600, 0, 0, 8};
+
+// Bit 0:  DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
+static uint8_t vendor_line_state = 0;
+
+//USB and Vendor events
+static void usbEventCallback(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == ARDUINO_USB_EVENTS) {
+    arduino_usb_event_data_t *data = (arduino_usb_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_STARTED_EVENT: Serial.println("USB PLUGGED"); break;
+      case ARDUINO_USB_STOPPED_EVENT: Serial.println("USB UNPLUGGED"); break;
+      case ARDUINO_USB_SUSPEND_EVENT: Serial.printf("USB SUSPENDED: remote_wakeup_en: %u\n", data->suspend.remote_wakeup_en); break;
+      case ARDUINO_USB_RESUME_EVENT:  Serial.println("USB RESUMED"); break;
+
+      default: break;
+    }
+  } else if (event_base == ARDUINO_USB_VENDOR_EVENTS) {
+    arduino_usb_vendor_event_data_t *data = (arduino_usb_vendor_event_data_t *)event_data;
+    switch (event_id) {
+      case ARDUINO_USB_VENDOR_DATA_EVENT:
+        Serial.printf("Vendor RX: len:%u\n", data->data.len);
+        for (uint16_t i = 0; i < data->data.len; i++) {
+          Serial.write(Vendor.read());
+        }
+        Serial.println();
+        break;
+
+      default: break;
+    }
+  }
+}
+
+static const char *strRequestDirections[] = {"OUT", "IN"};
+static const char *strRequestTypes[] = {"STANDARD", "CLASS", "VENDOR", "INVALID"};
+static const char *strRequestRecipients[] = {"DEVICE", "INTERFACE", "ENDPOINT", "OTHER"};
+static const char *strRequestStages[] = {"SETUP", "DATA", "ACK"};
+
+//Handle USB requests to the vendor interface
+bool vendorRequestCallback(uint8_t rhport, uint8_t requestStage, arduino_usb_control_request_t const *request) {
+  Serial.printf(
+    "Vendor Request: Stage: %5s, Direction: %3s, Type: %8s, Recipient: %9s, bRequest: 0x%02x, wValue: 0x%04x, wIndex: %u, wLength: %u\n",
+    strRequestStages[requestStage], strRequestDirections[request->bmRequestDirection], strRequestTypes[request->bmRequestType],
+    strRequestRecipients[request->bmRequestRecipient], request->bRequest, request->wValue, request->wIndex, request->wLength
+  );
+
+  bool result = false;
+
+  if (request->bmRequestDirection == REQUEST_DIRECTION_OUT && request->bmRequestType == REQUEST_TYPE_STANDARD
+      && request->bmRequestRecipient == REQUEST_RECIPIENT_INTERFACE && request->bRequest == 0x0b) {
+    if (requestStage == REQUEST_STAGE_SETUP) {
+      // response with status OK
+      result = Vendor.sendResponse(rhport, request);
+    } else {
+      result = true;
+    }
+  } else
+    //Implement CDC Control Requests
+    if (request->bmRequestType == REQUEST_TYPE_CLASS && request->bmRequestRecipient == REQUEST_RECIPIENT_DEVICE) {
+      switch (request->bRequest) {
+
+        case REQUEST_SET_LINE_CODING:  //0x20
+          // Accept only direction OUT with data size 7
+          if (request->wLength != sizeof(request_line_coding_t) || request->bmRequestDirection != REQUEST_DIRECTION_OUT) {
+            break;
+          }
+          if (requestStage == REQUEST_STAGE_SETUP) {
+            //Send the response in setup stage (it will write the data to vendor_line_coding in the DATA stage)
+            result = Vendor.sendResponse(rhport, request, (void *)&vendor_line_coding, sizeof(request_line_coding_t));
+          } else if (requestStage == REQUEST_STAGE_ACK) {
+            //In the ACK stage the response is complete
+            Serial.printf(
+              "Vendor Line Coding: bit_rate: %lu, data_bits: %u, stop_bits: %u, parity: %u\n", vendor_line_coding.bit_rate, vendor_line_coding.data_bits,
+              vendor_line_coding.stop_bits, vendor_line_coding.parity
+            );
+          }
+          result = true;
+          break;
+
+        case REQUEST_GET_LINE_CODING:  //0x21
+          // Accept only direction IN with data size 7
+          if (request->wLength != sizeof(request_line_coding_t) || request->bmRequestDirection != REQUEST_DIRECTION_IN) {
+            break;
+          }
+          if (requestStage == REQUEST_STAGE_SETUP) {
+            //Send the response in setup stage (it will write the data to vendor_line_coding in the DATA stage)
+            result = Vendor.sendResponse(rhport, request, (void *)&vendor_line_coding, sizeof(request_line_coding_t));
+          }
+          result = true;
+          break;
+
+        case REQUEST_SET_CONTROL_LINE_STATE:  //0x22
+          // Accept only direction OUT with data size 0
+          if (request->wLength != 0 || request->bmRequestDirection != REQUEST_DIRECTION_OUT) {
+            break;
+          }
+          if (requestStage == REQUEST_STAGE_SETUP) {
+            //Send the response in setup stage
+            vendor_line_state = request->wValue;
+            result = Vendor.sendResponse(rhport, request);
+          } else if (requestStage == REQUEST_STAGE_ACK) {
+            //In the ACK stage the response is complete
+            bool dtr = (vendor_line_state & 1) != 0;
+            bool rts = (vendor_line_state & 2) != 0;
+            Serial.printf("Vendor Line State: dtr: %u, rts: %u\n", dtr, rts);
+          }
+          result = true;
+          break;
+
+        default:
+          // stall unknown request
+          break;
+      }
+    }
+
+  return result;
+}
+
+void setup() {
+  pinMode(buttonPin, INPUT_PULLUP);
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+
+  Vendor.onEvent(usbEventCallback);
+  Vendor.onRequest(vendorRequestCallback);
+  Vendor.begin();
+
+  USB.onEvent(usbEventCallback);
+  USB.webUSB(true);
+  // Set the URL for your WebUSB landing page
+  USB.webUSBURL("https://docs.espressif.com/projects/arduino-esp32/en/latest/_static/webusb.html");
+  USB.begin();
+}
+
+void loop() {
+  static int previousButtonState = HIGH;
+  int buttonState = digitalRead(buttonPin);
+  if (buttonState != previousButtonState) {
+    previousButtonState = buttonState;
+    if (buttonState == LOW) {
+      Serial.println("Button Pressed");
+      Vendor.println("Button Pressed");
+      Vendor.flush();  //Without flushing the data will only be sent when the buffer is full (64 bytes)
+    } else {
+      Serial.println("Button Released");
+      Vendor.println("Button Released");
+      Vendor.flush();  //Without flushing the data will only be sent when the buffer is full (64 bytes)
+    }
+    delay(100);
+  }
+
+  while (Serial.available()) {
+    size_t l = Serial.available();
+    uint8_t b[l];
+    l = Serial.read(b, l);
+    Vendor.write(b, l);
+    Vendor.flush();  //Without flushing the data will only be sent when the buffer is full (64 bytes)
+  }
+}
+#endif /* ARDUINO_USB_MODE */
diff --git a/libraries/USB/examples/USBVendor/ci.json b/libraries/USB/examples/USBVendor/ci.json
new file mode 100644
index 00000000000..f9ac7d0bec9
--- /dev/null
+++ b/libraries/USB/examples/USBVendor/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_USB_OTG_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/USB/examples/USBVendor/index.html b/libraries/USB/examples/USBVendor/index.html
new file mode 100644
index 00000000000..23831bb4582
--- /dev/null
+++ b/libraries/USB/examples/USBVendor/index.html
@@ -0,0 +1,133 @@
+<!-- Based on https://github.com/zephyrproject-rtos/zephyr/tree/main/samples/subsys/usb/webusb -->
+
+<!--
+  Example of WebUSB web page to communicate with a USB device.
+  This can be used as a starting point for your self-hosted WebUSB landing page.
+-->
+
+<!DOCTYPE html>
+<html lang="en">
+  <head>
+    <title>Espressif WebUSB Console Example</title>
+  </head>
+
+<body>
+  <script>
+    var serial = {};
+
+    (function() {
+      'use strict';
+
+      serial.getPorts = function() {
+        return navigator.usb.getDevices().then(devices => {
+          return devices.map(device => new serial.Port(device));
+        });
+      };
+
+      serial.requestPort = function() {
+        const filters = [
+          { 'vendorId': 0x10c4, 'productId': 0xea60 },
+          { 'vendorId': 0x303a, 'productId': 0x1001 },
+          { 'vendorId': 0x303a, 'productId': 0x0002 },
+        ];
+        return navigator.usb.requestDevice({ 'filters': filters }).then(
+          device => new serial.Port(device)
+        );
+      }
+
+      serial.Port = function(device) {
+        this.device_ = device;
+      };
+
+      serial.Port.prototype.connect = function() {
+        let readLoop = () => {
+          const {
+            endpointNumber
+          } = this.device_.configuration.interfaces[0].alternate.endpoints[0]
+          this.device_.transferIn(endpointNumber, 64).then(result => {
+            this.onReceive(result.data);
+            readLoop();
+          }, error => {
+            this.onReceiveError(error);
+          });
+        };
+
+        return this.device_.open()
+            .then(() => {
+              if (this.device_.configuration === null) {
+                return this.device_.selectConfiguration(1);
+              }
+            })
+            .then(() => this.device_.claimInterface(0))
+            .then(() => {
+              readLoop();
+            });
+      };
+
+      serial.Port.prototype.disconnect = function() {
+        return this.device_.close();
+      };
+
+      serial.Port.prototype.send = function(data) {
+        const {
+          endpointNumber
+        } = this.device_.configuration.interfaces[0].alternate.endpoints[1]
+        return this.device_.transferOut(endpointNumber, data);
+      };
+    })();
+
+    let port;
+
+    function connect() {
+      port.connect().then(() => {
+        port.onReceive = data => {
+          let textDecoder = new TextDecoder();
+          console.log("Received:", textDecoder.decode(data));
+          document.getElementById('output').value += textDecoder.decode(data);
+        }
+        port.onReceiveError = error => {
+          console.error(error);
+          document.querySelector("#connect").style = "visibility: initial";
+          port.disconnect();
+        };
+      });
+    }
+
+    function send(string) {
+      console.log("sending to serial:" + string.length);
+      if (string.length === 0)
+        return;
+      console.log("sending to serial: [" + string +"]\n");
+
+      let view = new TextEncoder('utf-8').encode(string);
+      console.log(view);
+      if (port) {
+        port.send(view);
+      }
+    };
+
+    window.onload = _ => {
+      document.querySelector("#connect").onclick = function() {
+        serial.requestPort().then(selectedPort => {
+          port = selectedPort;
+          this.style = "visibility: hidden";
+          connect();
+        });
+      }
+
+      document.querySelector("#submit").onclick = () => {
+        let source = document.querySelector("#input").value;
+        send(source);
+      }
+    }
+  </script>
+
+  <button id="connect" style="visibility: initial">Connect To ESP Device</button>
+  <br><br><label for="input">Sender: </label> <br>
+  <textarea id="input" rows="25" cols="80">Send to ESP Device</textarea>
+  <br><button id="submit">Send</button>
+  <br><br>
+  <label for="output">Receiver: </label> <br>
+  <textarea id="output" rows="25" cols="80"></textarea>
+</body>
+</html>
diff --git a/libraries/USB/keywords.txt b/libraries/USB/keywords.txt
new file mode 100644
index 00000000000..e7ebc8fee2c
--- /dev/null
+++ b/libraries/USB/keywords.txt
@@ -0,0 +1,32 @@
+#######################################
+# Syntax Coloring Map
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+USB	KEYWORD1
+USBCDC	KEYWORD1
+USBMSC	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+begin	KEYWORD2
+end	KEYWORD2
+onEvent	KEYWORD2
+enableReset	KEYWORD2
+
+vendorID	KEYWORD2
+productID	KEYWORD2
+productRevision	KEYWORD2
+mediaPresent	KEYWORD2
+onStartStop	KEYWORD2
+onRead	KEYWORD2
+onWrite	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
diff --git a/libraries/USB/library.properties b/libraries/USB/library.properties
new file mode 100644
index 00000000000..9d47dfc6719
--- /dev/null
+++ b/libraries/USB/library.properties
@@ -0,0 +1,9 @@
+name=USB
+version=3.2.0
+author=Hristo Gochkov
+maintainer=Hristo Gochkov <hristo@espressif.com>
+sentence=ESP32S2 USB Library
+paragraph=
+category=Communication
+url=
+architectures=esp32
diff --git a/libraries/USB/src/USBHID.cpp b/libraries/USB/src/USBHID.cpp
new file mode 100644
index 00000000000..1d5d86fb3a3
--- /dev/null
+++ b/libraries/USB/src/USBHID.cpp
@@ -0,0 +1,390 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include "USBHID.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#include "esp32-hal-tinyusb.h"
+#include "USB.h"
+#include "esp_hid_common.h"
+
+#define USB_HID_DEVICES_MAX 10
+
+ESP_EVENT_DEFINE_BASE(ARDUINO_USB_HID_EVENTS);
+esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait);
+esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg);
+
+typedef struct {
+  USBHIDDevice *device;
+  uint8_t reports_num;
+  uint8_t *report_ids;
+} tinyusb_hid_device_t;
+
+static tinyusb_hid_device_t tinyusb_hid_devices[USB_HID_DEVICES_MAX];
+
+static uint8_t tinyusb_hid_devices_num = 0;
+static bool tinyusb_hid_devices_is_initialized = false;
+static SemaphoreHandle_t tinyusb_hid_device_input_sem = NULL;
+static SemaphoreHandle_t tinyusb_hid_device_input_mutex = NULL;
+
+static bool tinyusb_hid_is_initialized = false;
+static hid_interface_protocol_enum_t tinyusb_interface_protocol = HID_ITF_PROTOCOL_NONE;
+static uint8_t tinyusb_loaded_hid_devices_num = 0;
+static uint16_t tinyusb_hid_device_descriptor_len = 0;
+static uint8_t *tinyusb_hid_device_descriptor = NULL;
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
+static const char *tinyusb_hid_device_report_types[4] = {"INVALID", "INPUT", "OUTPUT", "FEATURE"};
+#endif
+
+static bool tinyusb_enable_hid_device(uint16_t descriptor_len, USBHIDDevice *device) {
+  if (tinyusb_hid_is_initialized) {
+    log_e("TinyUSB HID has already started! Device not enabled");
+    return false;
+  }
+  if (tinyusb_loaded_hid_devices_num >= USB_HID_DEVICES_MAX) {
+    log_e("Maximum devices already enabled! Device not enabled");
+    return false;
+  }
+  tinyusb_hid_device_descriptor_len += descriptor_len;
+  tinyusb_hid_devices[tinyusb_loaded_hid_devices_num++].device = device;
+
+  log_d("Device[%u] len: %u", tinyusb_loaded_hid_devices_num - 1, descriptor_len);
+  return true;
+}
+
+USBHIDDevice *tinyusb_get_device_by_report_id(uint8_t report_id) {
+  for (uint8_t i = 0; i < tinyusb_loaded_hid_devices_num; i++) {
+    tinyusb_hid_device_t *device = &tinyusb_hid_devices[i];
+    if (device->device && device->reports_num) {
+      for (uint8_t r = 0; r < device->reports_num; r++) {
+        if (report_id == device->report_ids[r]) {
+          return device->device;
+        }
+      }
+    }
+  }
+  return NULL;
+}
+
+static uint16_t tinyusb_on_get_feature(uint8_t report_id, uint8_t *buffer, uint16_t reqlen) {
+  USBHIDDevice *device = tinyusb_get_device_by_report_id(report_id);
+  if (device) {
+    return device->_onGetFeature(report_id, buffer, reqlen);
+  }
+  return 0;
+}
+
+static bool tinyusb_on_set_feature(uint8_t report_id, const uint8_t *buffer, uint16_t reqlen) {
+  USBHIDDevice *device = tinyusb_get_device_by_report_id(report_id);
+  if (device) {
+    device->_onSetFeature(report_id, buffer, reqlen);
+    return true;
+  }
+  return false;
+}
+
+static bool tinyusb_on_set_output(uint8_t report_id, const uint8_t *buffer, uint16_t reqlen) {
+  USBHIDDevice *device = tinyusb_get_device_by_report_id(report_id);
+  if (device) {
+    device->_onOutput(report_id, buffer, reqlen);
+    return true;
+  }
+  return false;
+}
+
+static uint16_t tinyusb_on_add_descriptor(uint8_t device_index, uint8_t *dst) {
+  uint16_t res = 0;
+  uint8_t report_id = 0, reports_num = 0;
+  tinyusb_hid_device_t *device = &tinyusb_hid_devices[device_index];
+  if (device->device) {
+    res = device->device->_onGetDescriptor(dst);
+    if (res) {
+
+      esp_hid_report_map_t *hid_report_map = esp_hid_parse_report_map(dst, res);
+      if (hid_report_map) {
+        if (device->report_ids) {
+          free(device->report_ids);
+        }
+        device->reports_num = hid_report_map->reports_len;
+        device->report_ids = (uint8_t *)malloc(device->reports_num);
+        memset(device->report_ids, 0, device->reports_num);
+        reports_num = device->reports_num;
+
+        for (uint8_t i = 0; i < device->reports_num; i++) {
+          if (hid_report_map->reports[i].protocol_mode == ESP_HID_PROTOCOL_MODE_REPORT) {
+            report_id = hid_report_map->reports[i].report_id;
+            for (uint8_t r = 0; r < device->reports_num; r++) {
+              if (!report_id) {
+                //todo: handle better when device has no report ID set
+                break;
+              } else if (report_id == device->report_ids[r]) {
+                //already added
+                reports_num--;
+                break;
+              } else if (!device->report_ids[r]) {
+                //empty slot
+                device->report_ids[r] = report_id;
+                break;
+              }
+            }
+          } else {
+            reports_num--;
+          }
+        }
+        device->reports_num = reports_num;
+        esp_hid_free_report_map(hid_report_map);
+      }
+    }
+  }
+  return res;
+}
+
+static bool tinyusb_load_enabled_hid_devices() {
+  if (tinyusb_hid_device_descriptor != NULL) {
+    return true;
+  }
+  tinyusb_hid_device_descriptor = (uint8_t *)malloc(tinyusb_hid_device_descriptor_len);
+  if (tinyusb_hid_device_descriptor == NULL) {
+    log_e("HID Descriptor Malloc Failed");
+    return false;
+  }
+  uint8_t *dst = tinyusb_hid_device_descriptor;
+
+  for (uint8_t i = 0; i < tinyusb_loaded_hid_devices_num; i++) {
+    uint16_t len = tinyusb_on_add_descriptor(i, dst);
+    if (!len) {
+      break;
+    } else {
+      dst += len;
+    }
+  }
+
+  esp_hid_report_map_t *hid_report_map = esp_hid_parse_report_map(tinyusb_hid_device_descriptor, tinyusb_hid_device_descriptor_len);
+  if (hid_report_map) {
+    log_d("Loaded HID Descriptor with the following reports:");
+    for (uint8_t i = 0; i < hid_report_map->reports_len; i++) {
+      if (hid_report_map->reports[i].protocol_mode == ESP_HID_PROTOCOL_MODE_REPORT) {
+        log_d(
+          "  ID: %3u, Type: %7s, Size: %2u, Usage: %8s", hid_report_map->reports[i].report_id, esp_hid_report_type_str(hid_report_map->reports[i].report_type),
+          hid_report_map->reports[i].value_len, esp_hid_usage_str(hid_report_map->reports[i].usage)
+        );
+      }
+    }
+    esp_hid_free_report_map(hid_report_map);
+  } else {
+    log_e("Failed to parse the hid report descriptor!");
+    return false;
+  }
+
+  return true;
+}
+
+extern "C" uint16_t tusb_hid_load_descriptor(uint8_t *dst, uint8_t *itf) {
+  if (tinyusb_hid_is_initialized) {
+    return 0;
+  }
+  tinyusb_hid_is_initialized = true;
+
+  uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB HID");
+  // For keyboard boot protocol, we've already called tinyusb_enable_interface2(reserve_endpoints=true)
+  uint8_t ep_in = tinyusb_interface_protocol == HID_ITF_PROTOCOL_KEYBOARD ? 1 : tinyusb_get_free_in_endpoint();
+  TU_VERIFY(ep_in != 0);
+  uint8_t ep_out = tinyusb_interface_protocol == HID_ITF_PROTOCOL_KEYBOARD ? 1 : tinyusb_get_free_out_endpoint();
+  TU_VERIFY(ep_out != 0);
+  uint8_t descriptor[TUD_HID_INOUT_DESC_LEN] = {
+    // HID Input & Output descriptor
+    // Interface number, string index, protocol, report descriptor len, EP OUT & IN address, size & polling interval
+    TUD_HID_INOUT_DESCRIPTOR(
+      *itf, str_index, tinyusb_interface_protocol, tinyusb_hid_device_descriptor_len, ep_out, (uint8_t)(0x80 | ep_in), CFG_TUD_ENDOINT_SIZE, 1
+    )
+  };
+  *itf += 1;
+  memcpy(dst, descriptor, TUD_HID_INOUT_DESC_LEN);
+  return TUD_HID_INOUT_DESC_LEN;
+}
+
+// Invoked when received GET HID REPORT DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint8_t const *tud_hid_descriptor_report_cb(uint8_t instance) {
+  log_v("instance: %u", instance);
+  if (!tinyusb_load_enabled_hid_devices()) {
+    return NULL;
+  }
+  return tinyusb_hid_device_descriptor;
+}
+
+// Invoked when received SET_PROTOCOL request
+// protocol is either HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
+void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol) {
+  log_v("instance: %u, protocol:%u", instance, protocol);
+  arduino_usb_hid_event_data_t p;
+  p.instance = instance;
+  p.set_protocol.protocol = protocol;
+  arduino_usb_event_post(ARDUINO_USB_HID_EVENTS, ARDUINO_USB_HID_SET_PROTOCOL_EVENT, &p, sizeof(arduino_usb_hid_event_data_t), portMAX_DELAY);
+}
+
+// Invoked when received SET_IDLE request. return false will stall the request
+// - Idle Rate = 0 : only send report if there is changes, i.e skip duplication
+// - Idle Rate > 0 : skip duplication, but send at least 1 report every idle rate (in unit of 4 ms).
+bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate) {
+  log_v("instance: %u, idle_rate:%u", instance, idle_rate);
+  arduino_usb_hid_event_data_t p;
+  p.instance = instance;
+  p.set_idle.idle_rate = idle_rate;
+  arduino_usb_event_post(ARDUINO_USB_HID_EVENTS, ARDUINO_USB_HID_SET_IDLE_EVENT, &p, sizeof(arduino_usb_hid_event_data_t), portMAX_DELAY);
+  return true;
+}
+
+// Invoked when received GET_REPORT control request
+// Application must fill buffer report's content and return its length.
+// Return zero will cause the stack to STALL request
+uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t *buffer, uint16_t reqlen) {
+  uint16_t res = tinyusb_on_get_feature(report_id, buffer, reqlen);
+  if (!res) {
+    log_d("instance: %u, report_id: %u, report_type: %s, reqlen: %u", instance, report_id, tinyusb_hid_device_report_types[report_type], reqlen);
+  }
+  return res;
+}
+
+// Invoked when received SET_REPORT control request or
+// received data on OUT endpoint ( Report ID = 0, Type = 0 )
+void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const *buffer, uint16_t bufsize) {
+  if (!report_id && (!report_type || report_type == HID_REPORT_TYPE_OUTPUT)) {
+    if (!tinyusb_on_set_output(0, buffer, bufsize) && !tinyusb_on_set_output(buffer[0], buffer + 1, bufsize - 1)) {
+      log_d(
+        "instance: %u, report_id: %u, report_type: %s, bufsize: %u", instance, buffer[0], tinyusb_hid_device_report_types[HID_REPORT_TYPE_OUTPUT], bufsize - 1
+      );
+    }
+  } else {
+    if (!tinyusb_on_set_feature(report_id, buffer, bufsize)) {
+      log_d("instance: %u, report_id: %u, report_type: %s, bufsize: %u", instance, report_id, tinyusb_hid_device_report_types[report_type], bufsize);
+    }
+  }
+}
+
+USBHID::USBHID(hid_interface_protocol_enum_t itf_protocol) {
+  if (!tinyusb_hid_devices_is_initialized) {
+    tinyusb_hid_devices_is_initialized = true;
+    for (uint8_t i = 0; i < USB_HID_DEVICES_MAX; i++) {
+      memset(&tinyusb_hid_devices[i], 0, sizeof(tinyusb_hid_device_t));
+    }
+    tinyusb_hid_devices_num = 0;
+    tinyusb_interface_protocol = itf_protocol;
+    tinyusb_enable_interface2(USB_INTERFACE_HID, TUD_HID_INOUT_DESC_LEN, tusb_hid_load_descriptor, itf_protocol == HID_ITF_PROTOCOL_KEYBOARD);
+  }
+}
+
+void USBHID::begin() {
+  if (tinyusb_hid_device_input_sem == NULL) {
+    tinyusb_hid_device_input_sem = xSemaphoreCreateBinary();
+  }
+  if (tinyusb_hid_device_input_mutex == NULL) {
+    tinyusb_hid_device_input_mutex = xSemaphoreCreateMutex();
+  }
+}
+
+void USBHID::end() {
+  if (tinyusb_hid_device_input_sem != NULL) {
+    vSemaphoreDelete(tinyusb_hid_device_input_sem);
+    tinyusb_hid_device_input_sem = NULL;
+  }
+  if (tinyusb_hid_device_input_mutex != NULL) {
+    vSemaphoreDelete(tinyusb_hid_device_input_mutex);
+    tinyusb_hid_device_input_mutex = NULL;
+  }
+}
+
+bool USBHID::ready(void) {
+  return tud_hid_n_ready(0);
+}
+
+// TinyUSB is in the process of changing the type of the last argument to
+// tud_hid_report_complete_cb(), so extract the type from the version of TinyUSB that we're
+// compiled with.
+template<class F> struct ArgType;
+
+template<class R, class T1, class T2, class T3> struct ArgType<R (*)(T1, T2, T3)> {
+  typedef T1 type1;
+  typedef T2 type2;
+  typedef T3 type3;
+};
+
+typedef ArgType<decltype(&tud_hid_report_complete_cb)>::type3 tud_hid_report_complete_cb_len_t;
+
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const *report, tud_hid_report_complete_cb_len_t len) {
+  if (tinyusb_hid_device_input_sem) {
+    xSemaphoreGive(tinyusb_hid_device_input_sem);
+  }
+}
+
+bool USBHID::SendReport(uint8_t id, const void *data, size_t len, uint32_t timeout_ms) {
+  if (!tinyusb_hid_device_input_sem || !tinyusb_hid_device_input_mutex) {
+    log_e("TX Semaphore is NULL. You must call USBHID::begin() before you can send reports");
+    return false;
+  }
+
+  if (xSemaphoreTake(tinyusb_hid_device_input_mutex, timeout_ms / portTICK_PERIOD_MS) != pdTRUE) {
+    log_e("report %u mutex failed", id);
+    return false;
+  }
+
+  // If we're configured to support boot protocol, and the host has requested boot protocol, prevent
+  // sending of report ID, by passing report ID of 0 to tud_hid_n_report().
+  uint8_t effective_id = ((tinyusb_interface_protocol != HID_ITF_PROTOCOL_NONE) && (tud_hid_n_get_protocol(0) == HID_PROTOCOL_BOOT)) ? 0 : id;
+
+  bool res = ready();
+  if (!res) {
+    log_e("not ready");
+  } else {
+    // The semaphore may be given if the last SendReport() timed out waiting for the report to
+    // be sent. Or, tud_hid_report_complete_cb() may be called an extra time, causing the
+    // semaphore to be given. In these cases, take the semaphore to clear its state so that
+    // we can wait for it to be given after calling tud_hid_n_report().
+    xSemaphoreTake(tinyusb_hid_device_input_sem, 0);
+
+    res = tud_hid_n_report(0, effective_id, data, len);
+    if (!res) {
+      log_e("report %u failed", id);
+    } else {
+      if (xSemaphoreTake(tinyusb_hid_device_input_sem, timeout_ms / portTICK_PERIOD_MS) != pdTRUE) {
+        log_e("report %u wait failed", id);
+        res = false;
+      }
+    }
+  }
+
+  xSemaphoreGive(tinyusb_hid_device_input_mutex);
+  return res;
+}
+
+bool USBHID::addDevice(USBHIDDevice *device, uint16_t descriptor_len) {
+  if (device && tinyusb_loaded_hid_devices_num < USB_HID_DEVICES_MAX) {
+    if (!tinyusb_enable_hid_device(descriptor_len, device)) {
+      return false;
+    }
+    return true;
+  }
+  return false;
+}
+
+void USBHID::onEvent(esp_event_handler_t callback) {
+  onEvent(ARDUINO_USB_HID_ANY_EVENT, callback);
+}
+void USBHID::onEvent(arduino_usb_hid_event_t event, esp_event_handler_t callback) {
+  arduino_usb_event_handler_register_with(ARDUINO_USB_HID_EVENTS, event, callback, this);
+}
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHID.h b/libraries/USB/src/USBHID.h
new file mode 100644
index 00000000000..3b9f8115bee
--- /dev/null
+++ b/libraries/USB/src/USBHID.h
@@ -0,0 +1,86 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "sdkconfig.h"
+
+#if CONFIG_TINYUSB_HID_ENABLED
+#include "esp_event.h"
+#include "class/hid/hid.h"
+#include "class/hid/hid_device.h"
+
+// Used by the included TinyUSB drivers
+enum {
+  HID_REPORT_ID_NONE,
+  HID_REPORT_ID_KEYBOARD,
+  HID_REPORT_ID_MOUSE,
+  HID_REPORT_ID_GAMEPAD,
+  HID_REPORT_ID_CONSUMER_CONTROL,
+  HID_REPORT_ID_SYSTEM_CONTROL,
+  HID_REPORT_ID_VENDOR
+};
+
+ESP_EVENT_DECLARE_BASE(ARDUINO_USB_HID_EVENTS);
+
+typedef enum {
+  ARDUINO_USB_HID_ANY_EVENT = ESP_EVENT_ANY_ID,
+  ARDUINO_USB_HID_SET_PROTOCOL_EVENT = 0,
+  ARDUINO_USB_HID_SET_IDLE_EVENT,
+  ARDUINO_USB_HID_MAX_EVENT,
+} arduino_usb_hid_event_t;
+
+typedef struct {
+  uint8_t instance;
+  union {
+    struct {
+      uint8_t protocol;
+    } set_protocol;
+    struct {
+      uint8_t idle_rate;
+    } set_idle;
+  };
+} arduino_usb_hid_event_data_t;
+
+class USBHIDDevice {
+public:
+  virtual uint16_t _onGetDescriptor(uint8_t *buffer) {
+    return 0;
+  }
+  virtual uint16_t _onGetFeature(uint8_t report_id, uint8_t *buffer, uint16_t len) {
+    return 0;
+  }
+  virtual void _onSetFeature(uint8_t report_id, const uint8_t *buffer, uint16_t len) {}
+  virtual void _onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len) {}
+};
+
+class USBHID {
+public:
+  USBHID(hid_interface_protocol_enum_t itf_protocol = HID_ITF_PROTOCOL_NONE);
+  void begin(void);
+  void end(void);
+  bool ready(void);
+  bool SendReport(uint8_t report_id, const void *data, size_t len, uint32_t timeout_ms = 100);
+  void onEvent(esp_event_handler_t callback);
+  void onEvent(arduino_usb_hid_event_t event, esp_event_handler_t callback);
+  static bool addDevice(USBHIDDevice *device, uint16_t descriptor_len);
+};
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDConsumerControl.cpp b/libraries/USB/src/USBHIDConsumerControl.cpp
new file mode 100644
index 00000000000..136cfb5ba43
--- /dev/null
+++ b/libraries/USB/src/USBHIDConsumerControl.cpp
@@ -0,0 +1,55 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include "USBHID.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#include "USBHIDConsumerControl.h"
+
+static const uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_CONSUMER(HID_REPORT_ID(HID_REPORT_ID_CONSUMER_CONTROL))};
+
+USBHIDConsumerControl::USBHIDConsumerControl() : hid() {
+  static bool initialized = false;
+  if (!initialized) {
+    initialized = true;
+    hid.addDevice(this, sizeof(report_descriptor));
+  }
+}
+
+uint16_t USBHIDConsumerControl::_onGetDescriptor(uint8_t *dst) {
+  memcpy(dst, report_descriptor, sizeof(report_descriptor));
+  return sizeof(report_descriptor);
+}
+
+void USBHIDConsumerControl::begin() {
+  hid.begin();
+}
+
+void USBHIDConsumerControl::end() {}
+
+bool USBHIDConsumerControl::send(uint16_t value) {
+  return hid.SendReport(HID_REPORT_ID_CONSUMER_CONTROL, &value, 2);
+}
+
+size_t USBHIDConsumerControl::press(uint16_t k) {
+  return send(k);
+}
+
+size_t USBHIDConsumerControl::release() {
+  return send(0);
+}
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDConsumerControl.h b/libraries/USB/src/USBHIDConsumerControl.h
new file mode 100644
index 00000000000..7a59c70b6b1
--- /dev/null
+++ b/libraries/USB/src/USBHIDConsumerControl.h
@@ -0,0 +1,95 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "USBHID.h"
+#if CONFIG_TINYUSB_HID_ENABLED
+
+// Power Control
+#define CONSUMER_CONTROL_POWER 0x0030
+#define CONSUMER_CONTROL_RESET 0x0031
+#define CONSUMER_CONTROL_SLEEP 0x0032
+
+// Screen Brightness
+#define CONSUMER_CONTROL_BRIGHTNESS_INCREMENT 0x006F
+#define CONSUMER_CONTROL_BRIGHTNESS_DECREMENT 0x0070
+
+// These HID usages operate only on mobile systems (battery powered) and
+// require Windows 8 (build 8302 or greater).
+#define CONSUMER_CONTROL_WIRELESS_RADIO_CONTROLS      0x000C
+#define CONSUMER_CONTROL_WIRELESS_RADIO_BUTTONS       0x00C6
+#define CONSUMER_CONTROL_WIRELESS_RADIO_LED           0x00C7
+#define CONSUMER_CONTROL_WIRELESS_RADIO_SLIDER_SWITCH 0x00C8
+
+// Media Control
+#define CONSUMER_CONTROL_RECORD           0x00B2
+#define CONSUMER_CONTROL_FAST_FORWARD     0x00B3
+#define CONSUMER_CONTROL_REWIND           0x00B4
+#define CONSUMER_CONTROL_SCAN_NEXT        0x00B5
+#define CONSUMER_CONTROL_SCAN_PREVIOUS    0x00B6
+#define CONSUMER_CONTROL_STOP             0x00B7
+#define CONSUMER_CONTROL_EJECT            0x00B8
+#define CONSUMER_CONTROL_PLAY_PAUSE       0x00CD
+#define CONSUMER_CONTROL_VOLUME           0x00E0
+#define CONSUMER_CONTROL_MUTE             0x00E2
+#define CONSUMER_CONTROL_BASS             0x00E3
+#define CONSUMER_CONTROL_TREBLE           0x00E4
+#define CONSUMER_CONTROL_BASS_BOOST       0x00E5
+#define CONSUMER_CONTROL_VOLUME_INCREMENT 0x00E9
+#define CONSUMER_CONTROL_VOLUME_DECREMENT 0x00EA
+#define CONSUMER_CONTROL_BASS_INCREMENT   0x0152
+#define CONSUMER_CONTROL_BASS_DECREMENT   0x0153
+#define CONSUMER_CONTROL_TREBLE_INCREMENT 0x0154
+#define CONSUMER_CONTROL_TREBLE_DECREMENT 0x0155
+
+// Application Launcher
+#define CONSUMER_CONTROL_CONFIGURATION 0x0183
+#define CONSUMER_CONTROL_EMAIL_READER  0x018A
+#define CONSUMER_CONTROL_CALCULATOR    0x0192
+#define CONSUMER_CONTROL_LOCAL_BROWSER 0x0194
+
+// Browser/Explorer Specific
+#define CONSUMER_CONTROL_SEARCH    0x0221
+#define CONSUMER_CONTROL_HOME      0x0223
+#define CONSUMER_CONTROL_BACK      0x0224
+#define CONSUMER_CONTROL_FORWARD   0x0225
+#define CONSUMER_CONTROL_BR_STOP   0x0226
+#define CONSUMER_CONTROL_REFRESH   0x0227
+#define CONSUMER_CONTROL_BOOKMARKS 0x022A
+
+// Mouse Horizontal scroll
+#define CONSUMER_CONTROL_PAN 0x0238
+
+class USBHIDConsumerControl : public USBHIDDevice {
+private:
+  USBHID hid;
+  bool send(uint16_t value);
+
+public:
+  USBHIDConsumerControl(void);
+  void begin(void);
+  void end(void);
+  size_t press(uint16_t k);
+  size_t release();
+
+  // internal use
+  uint16_t _onGetDescriptor(uint8_t *buffer);
+};
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDGamepad.cpp b/libraries/USB/src/USBHIDGamepad.cpp
new file mode 100644
index 00000000000..a82e162bc9b
--- /dev/null
+++ b/libraries/USB/src/USBHIDGamepad.cpp
@@ -0,0 +1,109 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include "USBHID.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#include "USBHIDGamepad.h"
+
+static const uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_GAMEPAD(HID_REPORT_ID(HID_REPORT_ID_GAMEPAD))};
+
+USBHIDGamepad::USBHIDGamepad() : hid(), _x(0), _y(0), _z(0), _rz(0), _rx(0), _ry(0), _hat(0), _buttons(0) {
+  static bool initialized = false;
+  if (!initialized) {
+    initialized = true;
+    hid.addDevice(this, sizeof(report_descriptor));
+  }
+}
+
+uint16_t USBHIDGamepad::_onGetDescriptor(uint8_t *dst) {
+  memcpy(dst, report_descriptor, sizeof(report_descriptor));
+  return sizeof(report_descriptor);
+}
+
+void USBHIDGamepad::begin() {
+  hid.begin();
+}
+
+void USBHIDGamepad::end() {}
+
+bool USBHIDGamepad::write() {
+  hid_gamepad_report_t report = {.x = _x, .y = _y, .z = _z, .rz = _rz, .rx = _rx, .ry = _ry, .hat = _hat, .buttons = _buttons};
+  return hid.SendReport(HID_REPORT_ID_GAMEPAD, &report, sizeof(report));
+}
+
+bool USBHIDGamepad::leftStick(int8_t x, int8_t y) {
+  _x = x;
+  _y = y;
+  return write();
+}
+
+bool USBHIDGamepad::rightStick(int8_t z, int8_t rz) {
+  _z = z;
+  _rz = rz;
+  return write();
+}
+
+bool USBHIDGamepad::leftTrigger(int8_t rx) {
+  _rx = rx;
+  return write();
+}
+
+bool USBHIDGamepad::rightTrigger(int8_t ry) {
+  _ry = ry;
+  return write();
+}
+
+bool USBHIDGamepad::hat(uint8_t hat) {
+  if (hat > 9) {
+    return false;
+  }
+  _hat = hat;
+  return write();
+}
+
+bool USBHIDGamepad::pressButton(uint8_t button) {
+  if (button > 31) {
+    return false;
+  }
+  _buttons |= (1 << button);
+  return write();
+}
+
+bool USBHIDGamepad::releaseButton(uint8_t button) {
+  if (button > 31) {
+    return false;
+  }
+  _buttons &= ~(1 << button);
+  return write();
+}
+
+bool USBHIDGamepad::send(int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) {
+  if (hat > 9) {
+    return false;
+  }
+  _x = x;
+  _y = y;
+  _z = z;
+  _rz = rz;
+  _rx = rx;
+  _ry = ry;
+  _hat = hat;
+  _buttons = buttons;
+  return write();
+}
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDGamepad.h b/libraries/USB/src/USBHIDGamepad.h
new file mode 100644
index 00000000000..7e1ff2cee1f
--- /dev/null
+++ b/libraries/USB/src/USBHIDGamepad.h
@@ -0,0 +1,93 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "USBHID.h"
+#if CONFIG_TINYUSB_HID_ENABLED
+
+/// Standard Gamepad Buttons Naming from Linux input event codes
+/// https://github.com/torvalds/linux/blob/master/include/uapi/linux/input-event-codes.h
+#define BUTTON_A      0
+#define BUTTON_B      1
+#define BUTTON_C      2
+#define BUTTON_X      3
+#define BUTTON_Y      4
+#define BUTTON_Z      5
+#define BUTTON_TL     6
+#define BUTTON_TR     7
+#define BUTTON_TL2    8
+#define BUTTON_TR2    9
+#define BUTTON_SELECT 10
+#define BUTTON_START  11
+#define BUTTON_MODE   12
+#define BUTTON_THUMBL 13
+#define BUTTON_THUMBR 14
+
+#define BUTTON_SOUTH BUTTON_A
+#define BUTTON_EAST  BUTTON_B
+#define BUTTON_NORTH BUTTON_X
+#define BUTTON_WEST  BUTTON_Y
+
+/// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes)
+#define HAT_CENTER     0
+#define HAT_UP         1
+#define HAT_UP_RIGHT   2
+#define HAT_RIGHT      3
+#define HAT_DOWN_RIGHT 4
+#define HAT_DOWN       5
+#define HAT_DOWN_LEFT  6
+#define HAT_LEFT       7
+#define HAT_UP_LEFT    8
+
+class USBHIDGamepad : public USBHIDDevice {
+private:
+  USBHID hid;
+  int8_t _x;          ///< Delta x  movement of left analog-stick
+  int8_t _y;          ///< Delta y  movement of left analog-stick
+  int8_t _z;          ///< Delta z  movement of right analog-joystick
+  int8_t _rz;         ///< Delta Rz movement of right analog-joystick
+  int8_t _rx;         ///< Delta Rx movement of analog left trigger
+  int8_t _ry;         ///< Delta Ry movement of analog right trigger
+  uint8_t _hat;       ///< Buttons mask for currently pressed buttons in the DPad/hat
+  uint32_t _buttons;  ///< Buttons mask for currently pressed buttons
+  bool write();
+
+public:
+  USBHIDGamepad(void);
+  void begin(void);
+  void end(void);
+
+  bool leftStick(int8_t x, int8_t y);
+  bool rightStick(int8_t z, int8_t rz);
+
+  bool leftTrigger(int8_t rx);
+  bool rightTrigger(int8_t ry);
+
+  bool hat(uint8_t hat);
+
+  bool pressButton(uint8_t button);
+  bool releaseButton(uint8_t button);
+
+  bool send(int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons);
+
+  // internal use
+  uint16_t _onGetDescriptor(uint8_t *buffer);
+};
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDKeyboard.cpp b/libraries/USB/src/USBHIDKeyboard.cpp
new file mode 100644
index 00000000000..9f371b2e099
--- /dev/null
+++ b/libraries/USB/src/USBHIDKeyboard.cpp
@@ -0,0 +1,235 @@
+/*
+  Keyboard.cpp
+
+  Copyright (c) 2015, Arduino LLC
+  Original code (pre-library): Copyright (c) 2011, Peter Barrett
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+#include "USBHID.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#include "USBHIDKeyboard.h"
+#include "keyboardLayout/KeyboardLayout.h"
+
+ESP_EVENT_DEFINE_BASE(ARDUINO_USB_HID_KEYBOARD_EVENTS);
+esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait);
+esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg);
+
+static const uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_KEYBOARD(HID_REPORT_ID(HID_REPORT_ID_KEYBOARD))};
+
+USBHIDKeyboard::USBHIDKeyboard() : hid(HID_ITF_PROTOCOL_KEYBOARD), _asciimap(KeyboardLayout_en_US), shiftKeyReports(false) {
+  static bool initialized = false;
+  if (!initialized) {
+    initialized = true;
+    memset(&_keyReport, 0, sizeof(KeyReport));
+    hid.addDevice(this, sizeof(report_descriptor));
+  }
+}
+
+uint16_t USBHIDKeyboard::_onGetDescriptor(uint8_t *dst) {
+  memcpy(dst, report_descriptor, sizeof(report_descriptor));
+  return sizeof(report_descriptor);
+}
+
+void USBHIDKeyboard::begin(const uint8_t *layout) {
+  _asciimap = layout;
+  hid.begin();
+}
+
+void USBHIDKeyboard::end() {}
+
+void USBHIDKeyboard::onEvent(esp_event_handler_t callback) {
+  onEvent(ARDUINO_USB_HID_KEYBOARD_ANY_EVENT, callback);
+}
+void USBHIDKeyboard::onEvent(arduino_usb_hid_keyboard_event_t event, esp_event_handler_t callback) {
+  arduino_usb_event_handler_register_with(ARDUINO_USB_HID_KEYBOARD_EVENTS, event, callback, this);
+}
+
+void USBHIDKeyboard::_onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len) {
+  if (report_id == HID_REPORT_ID_KEYBOARD) {
+    arduino_usb_hid_keyboard_event_data_t p;
+    p.leds = buffer[0];
+    arduino_usb_event_post(
+      ARDUINO_USB_HID_KEYBOARD_EVENTS, ARDUINO_USB_HID_KEYBOARD_LED_EVENT, &p, sizeof(arduino_usb_hid_keyboard_event_data_t), portMAX_DELAY
+    );
+  }
+}
+
+void USBHIDKeyboard::sendReport(KeyReport *keys) {
+  hid_keyboard_report_t report;
+  report.reserved = 0;
+  report.modifier = keys->modifiers;
+  memcpy(report.keycode, keys->keys, 6);
+  hid.SendReport(HID_REPORT_ID_KEYBOARD, &report, sizeof(report));
+}
+
+void USBHIDKeyboard::setShiftKeyReports(bool set) {
+  shiftKeyReports = set;
+}
+
+size_t USBHIDKeyboard::pressRaw(uint8_t k) {
+  uint8_t i;
+  if (k >= 0xE0 && k < 0xE8) {
+    // it's a modifier key
+    _keyReport.modifiers |= (1 << (k - 0xE0));
+  } else if (k && k < 0xA5) {
+    // Add k to the key report only if it's not already present
+    // and if there is an empty slot.
+    if (_keyReport.keys[0] != k && _keyReport.keys[1] != k && _keyReport.keys[2] != k && _keyReport.keys[3] != k && _keyReport.keys[4] != k
+        && _keyReport.keys[5] != k) {
+
+      for (i = 0; i < 6; i++) {
+        if (_keyReport.keys[i] == 0x00) {
+          _keyReport.keys[i] = k;
+          break;
+        }
+      }
+      if (i == 6) {
+        return 0;
+      }
+    }
+  } else if (_keyReport.modifiers == 0) {
+    //not a modifier and not a key
+    return 0;
+  }
+  sendReport(&_keyReport);
+  return 1;
+}
+
+size_t USBHIDKeyboard::releaseRaw(uint8_t k) {
+  uint8_t i;
+  if (k >= 0xE0 && k < 0xE8) {
+    // it's a modifier key
+    _keyReport.modifiers &= ~(1 << (k - 0xE0));
+  } else if (k && k < 0xA5) {
+    // Test the key report to see if k is present.  Clear it if it exists.
+    // Check all positions in case the key is present more than once (which it shouldn't be)
+    for (i = 0; i < 6; i++) {
+      if (0 != k && _keyReport.keys[i] == k) {
+        _keyReport.keys[i] = 0x00;
+      }
+    }
+  }
+  // Allowing for the release of a modifier key without a corresponding press
+  sendReport(&_keyReport);
+  return 1;
+}
+
+// press() adds the specified key (printing, non-printing, or modifier)
+// to the persistent key report and sends the report.  Because of the way
+// USB HID works, the host acts like the key remains pressed until we
+// call release(), releaseAll(), or otherwise clear the report and resend.
+size_t USBHIDKeyboard::press(uint8_t k) {
+  if (k >= 0x88) {  // it's a non-printing key (not a modifier)
+    k = k - 0x88;
+  } else if (k >= 0x80) {  // it's a modifier key
+    _keyReport.modifiers |= (1 << (k - 0x80));
+    k = 0;
+  } else {  // it's a printing key (k is a ASCII 0..127)
+    k = _asciimap[k];
+    if (!k) {
+      return 0;
+    }
+    if ((k & SHIFT) == SHIFT) {  // it's a capital letter or other character reached with shift
+      // At boot, some PCs need a separate report with the shift key down like a real keyboard.
+      if (shiftKeyReports) {
+        pressRaw(HID_KEY_SHIFT_LEFT);
+      } else {
+        _keyReport.modifiers |= 0x02;  // the left shift modifier
+      }
+      k &= ~SHIFT;
+    }
+    if ((k & ALT_GR) == ALT_GR) {
+      _keyReport.modifiers |= 0x40;  // AltGr = right Alt
+      k &= ~ALT_GR;
+    }
+    if (k == ISO_REPLACEMENT) {
+      k = ISO_KEY;
+    }
+  }
+  return pressRaw(k);
+}
+
+// release() takes the specified key out of the persistent key report and
+// sends the report.  This tells the OS the key is no longer pressed and that
+// it shouldn't be repeated any more.
+size_t USBHIDKeyboard::release(uint8_t k) {
+  if (k >= 0x88) {  // it's a non-printing key (not a modifier)
+    k = k - 0x88;
+  } else if (k >= 0x80) {  // it's a modifier key
+    _keyReport.modifiers &= ~(1 << (k - 0x80));
+    k = 0;
+  } else {  // it's a printing key
+    k = _asciimap[k];
+    if (!k) {
+      return 0;
+    }
+    if ((k & SHIFT) == SHIFT) {  // it's a capital letter or other character reached with shift
+      if (shiftKeyReports) {
+        releaseRaw(k & 0x7F);    // Release key without shift modifier
+        k = HID_KEY_SHIFT_LEFT;  // Below, release shift modifier
+      } else {
+        _keyReport.modifiers &= ~(0x02);  // the left shift modifier
+        k &= ~SHIFT;
+      }
+    }
+    if ((k & ALT_GR) == ALT_GR) {
+      _keyReport.modifiers &= ~(0x40);  // AltGr = right Alt
+      k &= ~ALT_GR;
+    }
+    if (k == ISO_REPLACEMENT) {
+      k = ISO_KEY;
+    }
+  }
+  return releaseRaw(k);
+}
+
+void USBHIDKeyboard::releaseAll(void) {
+  _keyReport.keys[0] = 0;
+  _keyReport.keys[1] = 0;
+  _keyReport.keys[2] = 0;
+  _keyReport.keys[3] = 0;
+  _keyReport.keys[4] = 0;
+  _keyReport.keys[5] = 0;
+  _keyReport.modifiers = 0;
+  sendReport(&_keyReport);
+}
+
+size_t USBHIDKeyboard::write(uint8_t c) {
+  uint8_t p = press(c);  // Keydown
+  release(c);            // Keyup
+  return p;              // just return the result of press() since release() almost always returns 1
+}
+
+size_t USBHIDKeyboard::write(const uint8_t *buffer, size_t size) {
+  size_t n = 0;
+  while (size--) {
+    if (*buffer != '\r') {
+      if (write(*buffer)) {
+        n++;
+      } else {
+        break;
+      }
+    }
+    buffer++;
+  }
+  return n;
+}
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDKeyboard.h b/libraries/USB/src/USBHIDKeyboard.h
new file mode 100644
index 00000000000..d78b7fcc031
--- /dev/null
+++ b/libraries/USB/src/USBHIDKeyboard.h
@@ -0,0 +1,183 @@
+/*
+  Keyboard.h
+
+  Copyright (c) 2015, Arduino LLC
+  Original code (pre-library): Copyright (c) 2011, Peter Barrett
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "Print.h"
+#include "USBHID.h"
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#include "esp_event.h"
+
+ESP_EVENT_DECLARE_BASE(ARDUINO_USB_HID_KEYBOARD_EVENTS);
+
+typedef enum {
+  ARDUINO_USB_HID_KEYBOARD_ANY_EVENT = ESP_EVENT_ANY_ID,
+  ARDUINO_USB_HID_KEYBOARD_LED_EVENT = 0,
+  ARDUINO_USB_HID_KEYBOARD_MAX_EVENT,
+} arduino_usb_hid_keyboard_event_t;
+
+typedef union {
+  struct {
+    uint8_t numlock    : 1;
+    uint8_t capslock   : 1;
+    uint8_t scrolllock : 1;
+    uint8_t compose    : 1;
+    uint8_t kana       : 1;
+    uint8_t reserved   : 3;
+  };
+  uint8_t leds;
+} arduino_usb_hid_keyboard_event_data_t;
+
+// Supported keyboard layouts
+extern const uint8_t KeyboardLayout_de_DE[];
+extern const uint8_t KeyboardLayout_en_US[];
+extern const uint8_t KeyboardLayout_es_ES[];
+extern const uint8_t KeyboardLayout_fr_FR[];
+extern const uint8_t KeyboardLayout_it_IT[];
+extern const uint8_t KeyboardLayout_pt_PT[];
+extern const uint8_t KeyboardLayout_sv_SE[];
+extern const uint8_t KeyboardLayout_da_DK[];
+extern const uint8_t KeyboardLayout_hu_HU[];
+extern const uint8_t KeyboardLayout_pt_BR[];
+
+#define KEY_LEFT_CTRL   0x80
+#define KEY_LEFT_SHIFT  0x81
+#define KEY_LEFT_ALT    0x82
+#define KEY_LEFT_GUI    0x83
+#define KEY_RIGHT_CTRL  0x84
+#define KEY_RIGHT_SHIFT 0x85
+#define KEY_RIGHT_ALT   0x86  // AltGr (Right Alt) Key
+#define KEY_RIGHT_GUI   0x87
+
+#define KEY_UP_ARROW     0xDA
+#define KEY_DOWN_ARROW   0xD9
+#define KEY_LEFT_ARROW   0xD8
+#define KEY_RIGHT_ARROW  0xD7
+#define KEY_MENU         0xED  //  "Keyboard Application" in USB standard
+#define KEY_SPACE        0x20
+#define KEY_BACKSPACE    0xB2
+#define KEY_TAB          0xB3
+#define KEY_RETURN       0xB0
+#define KEY_ESC          0xB1
+#define KEY_INSERT       0xD1
+#define KEY_DELETE       0xD4
+#define KEY_PAGE_UP      0xD3
+#define KEY_PAGE_DOWN    0xD6
+#define KEY_HOME         0xD2
+#define KEY_END          0xD5
+#define KEY_NUM_LOCK     0xDB
+#define KEY_CAPS_LOCK    0xC1
+#define KEY_F1           0xC2
+#define KEY_F2           0xC3
+#define KEY_F3           0xC4
+#define KEY_F4           0xC5
+#define KEY_F5           0xC6
+#define KEY_F6           0xC7
+#define KEY_F7           0xC8
+#define KEY_F8           0xC9
+#define KEY_F9           0xCA
+#define KEY_F10          0xCB
+#define KEY_F11          0xCC
+#define KEY_F12          0xCD
+#define KEY_F13          0xF0
+#define KEY_F14          0xF1
+#define KEY_F15          0xF2
+#define KEY_F16          0xF3
+#define KEY_F17          0xF4
+#define KEY_F18          0xF5
+#define KEY_F19          0xF6
+#define KEY_F20          0xF7
+#define KEY_F21          0xF8
+#define KEY_F22          0xF9
+#define KEY_F23          0xFA
+#define KEY_F24          0xFB
+#define KEY_PRINT_SCREEN 0xCE
+#define KEY_SCROLL_LOCK  0xCF
+#define KEY_PAUSE        0xD0
+
+#define LED_NUMLOCK    0x01
+#define LED_CAPSLOCK   0x02
+#define LED_SCROLLLOCK 0x04
+#define LED_COMPOSE    0x08
+#define LED_KANA       0x10
+
+// Numeric keypad
+#define KEY_KP_SLASH    0xDC
+#define KEY_KP_ASTERISK 0xDD
+#define KEY_KP_MINUS    0xDE
+#define KEY_KP_PLUS     0xDF
+#define KEY_KP_ENTER    0xE0
+#define KEY_KP_1        0xE1
+#define KEY_KP_2        0xE2
+#define KEY_KP_3        0xE3
+#define KEY_KP_4        0xE4
+#define KEY_KP_5        0xE5
+#define KEY_KP_6        0xE6
+#define KEY_KP_7        0xE7
+#define KEY_KP_8        0xE8
+#define KEY_KP_9        0xE9
+#define KEY_KP_0        0xEA
+#define KEY_KP_DOT      0xEB
+
+//  Low level key report: up to 6 keys and shift, ctrl etc at once
+typedef struct {
+  uint8_t modifiers;
+  uint8_t reserved;
+  uint8_t keys[6];
+} KeyReport;
+
+class USBHIDKeyboard : public USBHIDDevice, public Print {
+private:
+  USBHID hid;
+  KeyReport _keyReport;
+  const uint8_t *_asciimap;
+  bool shiftKeyReports;
+
+public:
+  USBHIDKeyboard(void);
+  void begin(const uint8_t *layout = KeyboardLayout_en_US);
+  void end(void);
+  size_t write(uint8_t k);
+  size_t write(const uint8_t *buffer, size_t size);
+  size_t press(uint8_t k);
+  size_t release(uint8_t k);
+  void releaseAll(void);
+  void sendReport(KeyReport *keys);
+  void setShiftKeyReports(bool set);
+
+  //raw functions work with TinyUSB's HID_KEY_* macros
+  size_t pressRaw(uint8_t k);
+  size_t releaseRaw(uint8_t k);
+
+  void onEvent(esp_event_handler_t callback);
+  void onEvent(arduino_usb_hid_keyboard_event_t event, esp_event_handler_t callback);
+
+  // internal use
+  uint16_t _onGetDescriptor(uint8_t *buffer);
+  void _onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len);
+};
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDMouse.cpp b/libraries/USB/src/USBHIDMouse.cpp
new file mode 100644
index 00000000000..885075c189d
--- /dev/null
+++ b/libraries/USB/src/USBHIDMouse.cpp
@@ -0,0 +1,120 @@
+/*
+  Mouse.cpp
+
+  Copyright (c) 2015, Arduino LLC
+  Original code (pre-library): Copyright (c) 2011, Peter Barrett
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+#include "USBHID.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#include "USBHIDMouse.h"
+
+USBHIDMouseBase::USBHIDMouseBase(HIDMouseType_t *type) : hid(), _buttons(0), _type(type) {
+  static bool initialized = false;
+  if (!initialized) {
+    initialized = true;
+    hid.addDevice(this, _type->descriptor_size);
+  }
+};
+
+uint16_t USBHIDMouseBase::_onGetDescriptor(uint8_t *dst) {
+  memcpy(dst, _type->report_descriptor, _type->descriptor_size);
+  return _type->descriptor_size;
+}
+
+void USBHIDMouseBase::buttons(uint8_t b) {
+  if (b != _buttons) {
+    _buttons = b;
+  }
+}
+
+void USBHIDMouseBase::begin() {
+  hid.begin();
+}
+
+void USBHIDMouseBase::end() {}
+
+void USBHIDMouseBase::press(uint8_t b) {
+  this->buttons(_buttons | b);
+}
+
+void USBHIDMouseBase::release(uint8_t b) {
+  this->buttons(_buttons & ~b);
+}
+
+bool USBHIDMouseBase::isPressed(uint8_t b) {
+  if ((b & _buttons) > 0) {
+    return true;
+  }
+  return false;
+}
+
+static const uint8_t abs_mouse_report_descriptor[] = {TUD_HID_REPORT_DESC_ABSMOUSE(HID_REPORT_ID(HID_REPORT_ID_MOUSE))};
+
+HIDMouseType_t HIDMouseAbs = {HID_MOUSE_ABSOLUTE, abs_mouse_report_descriptor, sizeof(abs_mouse_report_descriptor), sizeof(hid_abs_mouse_report_t)};
+
+void USBHIDAbsoluteMouse::move(int16_t x, int16_t y, int8_t wheel, int8_t pan) {
+  hid_abs_mouse_report_t report;
+  report.buttons = _buttons;
+  report.x = _lastx = x;
+  report.y = _lasty = y;
+  report.wheel = wheel;
+  report.pan = pan;
+  sendReport(report);
+}
+
+void USBHIDAbsoluteMouse::click(uint8_t b) {
+  _buttons = b;
+  move(_lastx, _lasty);
+  _buttons = 0;
+  move(_lastx, _lasty);
+}
+
+void USBHIDAbsoluteMouse::buttons(uint8_t b) {
+  if (b != _buttons) {
+    _buttons = b;
+    move(_lastx, _lasty);
+  }
+}
+
+static const uint8_t rel_mouse_report_descriptor[] = {TUD_HID_REPORT_DESC_MOUSE(HID_REPORT_ID(HID_REPORT_ID_MOUSE))};
+
+HIDMouseType_t HIDMouseRel = {HID_MOUSE_RELATIVE, rel_mouse_report_descriptor, sizeof(rel_mouse_report_descriptor), sizeof(hid_mouse_report_t)};
+
+void USBHIDRelativeMouse::move(int8_t x, int8_t y, int8_t wheel, int8_t pan) {
+  hid_mouse_report_t report = {.buttons = _buttons, .x = x, .y = y, .wheel = wheel, .pan = pan};
+  sendReport(report);
+}
+
+void USBHIDRelativeMouse::click(uint8_t b) {
+  _buttons = b;
+  move(0, 0);
+  _buttons = 0;
+  move(0, 0);
+}
+
+void USBHIDRelativeMouse::buttons(uint8_t b) {
+  if (b != _buttons) {
+    _buttons = b;
+    move(0, 0);
+  }
+}
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDMouse.h b/libraries/USB/src/USBHIDMouse.h
new file mode 100644
index 00000000000..9b9e348bb14
--- /dev/null
+++ b/libraries/USB/src/USBHIDMouse.h
@@ -0,0 +1,98 @@
+/*
+  Mouse.h
+
+  Copyright (c) 2015, Arduino LLC
+  Original code (pre-library): Copyright (c) 2011, Peter Barrett
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "USBHID.h"
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#define MOUSE_LEFT     0x01
+#define MOUSE_RIGHT    0x02
+#define MOUSE_MIDDLE   0x04
+#define MOUSE_BACKWARD 0x08
+#define MOUSE_FORWARD  0x10
+#define MOUSE_ALL      0x1F
+
+enum MousePositioning_t {
+  HID_MOUSE_RELATIVE,
+  HID_MOUSE_ABSOLUTE
+};
+
+struct HIDMouseType_t {
+  MousePositioning_t positioning;
+  const uint8_t *report_descriptor;
+  size_t descriptor_size;
+  size_t report_size;
+};
+
+extern HIDMouseType_t HIDMouseRel;
+extern HIDMouseType_t HIDMouseAbs;
+
+class USBHIDMouseBase : public USBHIDDevice {
+public:
+  USBHIDMouseBase(HIDMouseType_t *type);
+  void begin(void);
+  void end(void);
+  void press(uint8_t b = MOUSE_LEFT);      // press LEFT by default
+  void release(uint8_t b = MOUSE_LEFT);    // release LEFT by default
+  bool isPressed(uint8_t b = MOUSE_LEFT);  // check LEFT by default
+  template<typename T> bool sendReport(T report) {
+    return hid.SendReport(HID_REPORT_ID_MOUSE, &report, _type->report_size);
+  };
+  // internal use
+  uint16_t _onGetDescriptor(uint8_t *buffer);
+  virtual void click(uint8_t b) = 0;
+  virtual void buttons(uint8_t b) = 0;
+
+protected:
+  USBHID hid;
+  uint8_t _buttons;
+  HIDMouseType_t *_type;
+};
+
+class USBHIDRelativeMouse : public USBHIDMouseBase {
+public:
+  USBHIDRelativeMouse(void) : USBHIDMouseBase(&HIDMouseRel) {}
+  void move(int8_t x, int8_t y, int8_t wheel = 0, int8_t pan = 0);
+  void click(uint8_t b = MOUSE_LEFT) override;
+  void buttons(uint8_t b) override;
+};
+
+class USBHIDAbsoluteMouse : public USBHIDMouseBase {
+public:
+  USBHIDAbsoluteMouse(void) : USBHIDMouseBase(&HIDMouseAbs) {}
+  void move(int16_t x, int16_t y, int8_t wheel = 0, int8_t pan = 0);
+  void click(uint8_t b = MOUSE_LEFT) override;
+  void buttons(uint8_t b) override;
+
+private:
+  int16_t _lastx = 0;
+  int16_t _lasty = 0;
+};
+
+// don't break examples and old sketches
+typedef USBHIDRelativeMouse USBHIDMouse;
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDSystemControl.cpp b/libraries/USB/src/USBHIDSystemControl.cpp
new file mode 100644
index 00000000000..97442bc3128
--- /dev/null
+++ b/libraries/USB/src/USBHIDSystemControl.cpp
@@ -0,0 +1,58 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include "USBHID.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#include "USBHIDSystemControl.h"
+
+static const uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_SYSTEM_CONTROL(HID_REPORT_ID(HID_REPORT_ID_SYSTEM_CONTROL))};
+
+USBHIDSystemControl::USBHIDSystemControl() : hid() {
+  static bool initialized = false;
+  if (!initialized) {
+    initialized = true;
+    hid.addDevice(this, sizeof(report_descriptor));
+  }
+}
+
+uint16_t USBHIDSystemControl::_onGetDescriptor(uint8_t *dst) {
+  memcpy(dst, report_descriptor, sizeof(report_descriptor));
+  return sizeof(report_descriptor);
+}
+
+void USBHIDSystemControl::begin() {
+  hid.begin();
+}
+
+void USBHIDSystemControl::end() {}
+
+bool USBHIDSystemControl::send(uint8_t value) {
+  return hid.SendReport(HID_REPORT_ID_SYSTEM_CONTROL, &value, 1);
+}
+
+size_t USBHIDSystemControl::press(uint8_t k) {
+  if (k > 3) {
+    return 0;
+  }
+  return send(k);
+}
+
+size_t USBHIDSystemControl::release() {
+  return send(0);
+}
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDSystemControl.h b/libraries/USB/src/USBHIDSystemControl.h
new file mode 100644
index 00000000000..c88f29b8922
--- /dev/null
+++ b/libraries/USB/src/USBHIDSystemControl.h
@@ -0,0 +1,45 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "USBHID.h"
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#define SYSTEM_CONTROL_NONE      0
+#define SYSTEM_CONTROL_POWER_OFF 1
+#define SYSTEM_CONTROL_STANDBY   2
+#define SYSTEM_CONTROL_WAKE_HOST 3
+
+class USBHIDSystemControl : public USBHIDDevice {
+private:
+  USBHID hid;
+  bool send(uint8_t value);
+
+public:
+  USBHIDSystemControl(void);
+  void begin(void);
+  void end(void);
+  size_t press(uint8_t k);
+  size_t release();
+
+  // internal use
+  uint16_t _onGetDescriptor(uint8_t *buffer);
+};
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDVendor.cpp b/libraries/USB/src/USBHIDVendor.cpp
new file mode 100644
index 00000000000..20a46e73c23
--- /dev/null
+++ b/libraries/USB/src/USBHIDVendor.cpp
@@ -0,0 +1,221 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include "USBHID.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#if CONFIG_TINYUSB_HID_ENABLED
+
+#include "esp32-hal-log.h"
+#include "USBHIDVendor.h"
+
+ESP_EVENT_DEFINE_BASE(ARDUINO_USB_HID_VENDOR_EVENTS);
+esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait);
+esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg);
+
+// HID Generic Input, Output & Feature
+// - 1st parameter is report size (mandatory)
+// - 2nd parameter is report id HID_REPORT_ID(n) (optional)
+#define TUD_HID_REPORT_DESC_GENERIC_INOUT_FEATURE(report_size, ...)                                                               \
+  HID_USAGE_PAGE_N(HID_USAGE_PAGE_VENDOR, 2), HID_USAGE(0x01), HID_COLLECTION(HID_COLLECTION_APPLICATION), /* Report ID if any */ \
+    __VA_ARGS__                                                                                            /* Input */            \
+      HID_USAGE(0x02),                                                                                                            \
+    HID_LOGICAL_MIN(0x00), HID_LOGICAL_MAX(0xff), HID_REPORT_SIZE(8), HID_REPORT_COUNT(report_size),                              \
+    HID_INPUT(HID_DATA | HID_VARIABLE | HID_ABSOLUTE), /* Output */                                                               \
+    HID_USAGE(0x03), HID_LOGICAL_MIN(0x00), HID_LOGICAL_MAX(0xff), HID_REPORT_SIZE(8), HID_REPORT_COUNT(report_size),             \
+    HID_OUTPUT(HID_DATA | HID_VARIABLE | HID_ABSOLUTE), /* Feature */                                                             \
+    HID_USAGE(0x04), HID_LOGICAL_MIN(0x00), HID_LOGICAL_MAX(0xff), HID_REPORT_SIZE(8), HID_REPORT_COUNT(report_size),             \
+    HID_FEATURE(HID_DATA | HID_VARIABLE | HID_ABSOLUTE), HID_COLLECTION_END
+
+#define TUD_HID_REPORT_DESC_GENERIC_INOUT_FEATURE_LEN 46
+
+// max size is 64 and we need one byte for the report ID
+static uint8_t HID_VENDOR_REPORT_SIZE = 63;
+static uint8_t feature[64];
+static QueueHandle_t rx_queue = NULL;
+static bool prepend_size = false;
+
+USBHIDVendor::USBHIDVendor(uint8_t report_size, bool prepend) : hid() {
+  static bool initialized = false;
+  if (!initialized) {
+    initialized = true;
+    hid.addDevice(this, TUD_HID_REPORT_DESC_GENERIC_INOUT_FEATURE_LEN);
+    memset(feature, 0, 64);
+    if (report_size < 64) {
+      HID_VENDOR_REPORT_SIZE = report_size;
+    }
+    prepend_size = prepend;
+  }
+}
+
+uint16_t USBHIDVendor::_onGetDescriptor(uint8_t *dst) {
+  uint8_t report_descriptor[] = {TUD_HID_REPORT_DESC_GENERIC_INOUT_FEATURE(HID_VENDOR_REPORT_SIZE, HID_REPORT_ID(HID_REPORT_ID_VENDOR))};
+  memcpy(dst, report_descriptor, sizeof(report_descriptor));
+  return sizeof(report_descriptor);
+}
+
+void USBHIDVendor::prependInputPacketsWithSize(bool enable) {
+  prepend_size = enable;
+}
+
+size_t USBHIDVendor::setRxBufferSize(size_t rx_queue_len) {
+  if (rx_queue) {
+    if (!rx_queue_len) {
+      vQueueDelete(rx_queue);
+      rx_queue = NULL;
+    }
+    return 0;
+  }
+  rx_queue = xQueueCreate(rx_queue_len, sizeof(uint8_t));
+  if (!rx_queue) {
+    return 0;
+  }
+  return rx_queue_len;
+}
+
+void USBHIDVendor::begin() {
+  hid.begin();
+  setRxBufferSize(256);  //default if not preset
+}
+
+void USBHIDVendor::end() {
+  setRxBufferSize(0);
+}
+
+void USBHIDVendor::onEvent(esp_event_handler_t callback) {
+  onEvent(ARDUINO_USB_HID_VENDOR_ANY_EVENT, callback);
+}
+
+void USBHIDVendor::onEvent(arduino_usb_hid_vendor_event_t event, esp_event_handler_t callback) {
+  arduino_usb_event_handler_register_with(ARDUINO_USB_HID_VENDOR_EVENTS, event, callback, this);
+}
+
+uint16_t USBHIDVendor::_onGetFeature(uint8_t report_id, uint8_t *buffer, uint16_t len) {
+  if (report_id != HID_REPORT_ID_VENDOR) {
+    return 0;
+  }
+  memcpy(buffer, feature, len);
+  arduino_usb_hid_vendor_event_data_t p;
+  p.buffer = feature;
+  p.len = len;
+  arduino_usb_event_post(
+    ARDUINO_USB_HID_VENDOR_EVENTS, ARDUINO_USB_HID_VENDOR_GET_FEATURE_EVENT, &p, sizeof(arduino_usb_hid_vendor_event_data_t), portMAX_DELAY
+  );
+  return len;
+}
+
+void USBHIDVendor::_onSetFeature(uint8_t report_id, const uint8_t *buffer, uint16_t len) {
+  if (report_id != HID_REPORT_ID_VENDOR) {
+    return;
+  }
+  memcpy(feature, buffer, len);
+  arduino_usb_hid_vendor_event_data_t p;
+  p.buffer = feature;
+  p.len = len;
+  arduino_usb_event_post(
+    ARDUINO_USB_HID_VENDOR_EVENTS, ARDUINO_USB_HID_VENDOR_SET_FEATURE_EVENT, &p, sizeof(arduino_usb_hid_vendor_event_data_t), portMAX_DELAY
+  );
+}
+
+void USBHIDVendor::_onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len) {
+  if (report_id != HID_REPORT_ID_VENDOR) {
+    return;
+  }
+  for (uint32_t i = 0; i < len; i++) {
+    if (rx_queue == NULL || !xQueueSend(rx_queue, buffer + i, 0)) {
+      len = i + 1;
+      log_e("RX Queue Overflow");
+      break;
+    }
+  }
+  arduino_usb_hid_vendor_event_data_t p;
+  p.buffer = buffer;
+  p.len = len;
+  arduino_usb_event_post(ARDUINO_USB_HID_VENDOR_EVENTS, ARDUINO_USB_HID_VENDOR_OUTPUT_EVENT, &p, sizeof(arduino_usb_hid_vendor_event_data_t), portMAX_DELAY);
+}
+
+size_t USBHIDVendor::write(const uint8_t *buffer, size_t len) {
+  uint8_t hid_in[HID_VENDOR_REPORT_SIZE];
+  const uint8_t *data = (const uint8_t *)buffer;
+  uint8_t size_offset = prepend_size ? 1 : 0;
+  size_t to_send = len, max_send = HID_VENDOR_REPORT_SIZE - size_offset, will_send = 0;
+  while (to_send) {
+    will_send = to_send;
+    if (will_send > max_send) {
+      will_send = max_send;
+    }
+    if (prepend_size) {
+      hid_in[0] = will_send;
+    }
+    // We can get INPUT only when data length equals the input report size
+    memcpy(hid_in + size_offset, data, will_send);
+    // pad with zeroes
+    memset(hid_in + size_offset + will_send, 0, max_send - will_send);
+    if (!hid.SendReport(HID_REPORT_ID_VENDOR, hid_in, HID_VENDOR_REPORT_SIZE)) {
+      return len - to_send;
+    }
+    to_send -= will_send;
+    data += will_send;
+  }
+  return len;
+}
+
+size_t USBHIDVendor::write(uint8_t c) {
+  return write(&c, 1);
+}
+
+int USBHIDVendor::available(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  return uxQueueMessagesWaiting(rx_queue);
+}
+
+int USBHIDVendor::peek(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c;
+  if (xQueuePeek(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+int USBHIDVendor::read(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  if (xQueueReceive(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+size_t USBHIDVendor::read(uint8_t *buffer, size_t size) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  size_t count = 0;
+  while (count < size && xQueueReceive(rx_queue, &c, 0)) {
+    buffer[count++] = c;
+  }
+  return count;
+}
+
+void USBHIDVendor::flush(void) {}
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBHIDVendor.h b/libraries/USB/src/USBHIDVendor.h
new file mode 100644
index 00000000000..404f0fbf2f6
--- /dev/null
+++ b/libraries/USB/src/USBHIDVendor.h
@@ -0,0 +1,73 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "Stream.h"
+#include "USBHID.h"
+#if CONFIG_TINYUSB_HID_ENABLED
+
+ESP_EVENT_DECLARE_BASE(ARDUINO_USB_HID_VENDOR_EVENTS);
+
+typedef enum {
+  ARDUINO_USB_HID_VENDOR_ANY_EVENT = ESP_EVENT_ANY_ID,
+  ARDUINO_USB_HID_VENDOR_SET_FEATURE_EVENT = 0,
+  ARDUINO_USB_HID_VENDOR_GET_FEATURE_EVENT,
+  ARDUINO_USB_HID_VENDOR_OUTPUT_EVENT,
+  ARDUINO_USB_HID_VENDOR_MAX_EVENT,
+} arduino_usb_hid_vendor_event_t;
+
+typedef struct {
+  const uint8_t *buffer;
+  uint16_t len;
+} arduino_usb_hid_vendor_event_data_t;
+
+class USBHIDVendor : public USBHIDDevice, public Stream {
+private:
+  USBHID hid;
+
+public:
+  // Max report size is 64, but we need one byte for report ID, so in reality max is 63.
+  // Because input packets are always with length equal to the report size
+  // it will not be known how many bytes actually matter. Setting 'prepend_size' to 'true' will
+  // make the first byte of each packet to be the length of data in that packet.
+  // This comes with penalty of one byte, but is very useful when using Vendor for streaming
+  USBHIDVendor(uint8_t report_size = 63, bool prepend_size = false);
+  void begin(void);
+  void end(void);
+  void prependInputPacketsWithSize(bool enable);
+  size_t setRxBufferSize(size_t);
+  size_t write(const uint8_t *buffer, size_t len);
+  size_t write(uint8_t);
+  int available(void);
+  int peek(void);
+  int read(void);
+  size_t read(uint8_t *buffer, size_t size);
+  void flush(void);
+
+  void onEvent(esp_event_handler_t callback);
+  void onEvent(arduino_usb_hid_vendor_event_t event, esp_event_handler_t callback);
+
+  // internal use
+  uint16_t _onGetDescriptor(uint8_t *buffer);
+  uint16_t _onGetFeature(uint8_t report_id, uint8_t *buffer, uint16_t len);
+  void _onSetFeature(uint8_t report_id, const uint8_t *buffer, uint16_t len);
+  void _onOutput(uint8_t report_id, const uint8_t *buffer, uint16_t len);
+};
+
+#endif /* CONFIG_TINYUSB_HID_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBMIDI.cpp b/libraries/USB/src/USBMIDI.cpp
new file mode 100644
index 00000000000..8a9571855e1
--- /dev/null
+++ b/libraries/USB/src/USBMIDI.cpp
@@ -0,0 +1,134 @@
+#include "USBMIDI.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#if CONFIG_TINYUSB_MIDI_ENABLED
+
+#include "Arduino.h"
+#include "esp32-hal-tinyusb.h"
+
+// Default Cable Number (for simplified APIs that do not expose this)
+#define DEFAULT_CN 0
+
+static bool tinyusb_midi_descriptor_loaded = false;
+static bool tinyusb_midi_interface_enabled = false;
+
+extern "C" uint16_t tusb_midi_load_descriptor(uint8_t *dst, uint8_t *itf) {
+  if (tinyusb_midi_descriptor_loaded) {
+    return 0;
+  }
+  tinyusb_midi_descriptor_loaded = true;
+
+  uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB MIDI");
+  uint8_t ep_in = tinyusb_get_free_in_endpoint();
+  TU_VERIFY(ep_in != 0);
+  uint8_t ep_out = tinyusb_get_free_out_endpoint();
+  TU_VERIFY(ep_out != 0);
+  uint8_t descriptor[TUD_MIDI_DESC_LEN] = {
+    TUD_MIDI_DESCRIPTOR(*itf, str_index, ep_out, (uint8_t)(0x80 | ep_in), CFG_TUD_ENDOINT_SIZE),
+  };
+  *itf += 2;
+  memcpy(dst, descriptor, TUD_MIDI_DESC_LEN);
+
+  return TUD_MIDI_DESC_LEN;
+}
+
+USBMIDI::USBMIDI() {
+  if (!tinyusb_midi_interface_enabled) {
+    tinyusb_midi_interface_enabled = true;
+    tinyusb_enable_interface(USB_INTERFACE_MIDI, TUD_MIDI_DESC_LEN, tusb_midi_load_descriptor);
+  } else {
+    log_e("USBMIDI: Multiple instances of USBMIDI not supported!");
+  }
+}
+
+void USBMIDI::begin() {}
+void USBMIDI::end() {}
+
+// uint compatible version of constrain
+#define uconstrain(amt, low, high) ((amt) <= (low) ? (low) : ((amt) > (high) ? (high) : (amt)))
+
+#define STATUS(CIN, CHANNEL) static_cast<uint8_t>(((CIN & 0x7F) << 4) | (uconstrain(CHANNEL - 1, 0, 15) & 0x7F))
+
+// Note: All the user-level API calls do extensive input constraining to prevent easy to make mistakes.
+// (You can thank me later.)
+#define _(x) static_cast<uint8_t>(uconstrain(x, 0, 127))
+
+// Note On
+void USBMIDI::noteOn(uint8_t note, uint8_t velocity, uint8_t channel) {
+  midiEventPacket_t event = {MIDI_CIN_NOTE_ON, STATUS(MIDI_CIN_NOTE_ON, channel), _(note), _(velocity)};
+  writePacket(&event);
+}
+
+// Note Off
+void USBMIDI::noteOff(uint8_t note, uint8_t velocity, uint8_t channel) {
+  midiEventPacket_t event = {MIDI_CIN_NOTE_OFF, STATUS(MIDI_CIN_NOTE_OFF, channel), _(note), _(velocity)};
+  writePacket(&event);
+}
+
+// Program Change
+void USBMIDI::programChange(uint8_t program, uint8_t channel) {
+  midiEventPacket_t event = {MIDI_CIN_PROGRAM_CHANGE, STATUS(MIDI_CIN_PROGRAM_CHANGE, channel), _(program), 0x0};
+  writePacket(&event);
+}
+
+// Control Change (Continuous Controller)
+void USBMIDI::controlChange(uint8_t control, uint8_t value, uint8_t channel) {
+  midiEventPacket_t event = {MIDI_CIN_CONTROL_CHANGE, STATUS(MIDI_CIN_CONTROL_CHANGE, channel), _(control), _(value)};
+  writePacket(&event);
+}
+
+// Polyphonic Key Pressure (Aftertouch)
+void USBMIDI::polyPressure(uint8_t note, uint8_t pressure, uint8_t channel) {
+  midiEventPacket_t event = {MIDI_CIN_POLY_KEYPRESS, STATUS(MIDI_CIN_POLY_KEYPRESS, channel), _(note), _(pressure)};
+  writePacket(&event);
+}
+
+// Channel Pressure (Aftertouch)
+void USBMIDI::channelPressure(uint8_t pressure, uint8_t channel) {
+  midiEventPacket_t event = {MIDI_CIN_CHANNEL_PRESSURE, STATUS(MIDI_CIN_CHANNEL_PRESSURE, channel), _(pressure), 0x0};
+  writePacket(&event);
+}
+
+// Pitch Bend Change [-8192,0,8191]
+void USBMIDI::pitchBend(int16_t value, uint8_t channel) {
+  uint16_t pitchBendValue = constrain(value, -8192, 8191) + 8192;
+  pitchBend(pitchBendValue);
+}
+
+// Pitch Bend Change [0,8192,16383]
+void USBMIDI::pitchBend(uint16_t value, uint8_t channel) {
+  uint16_t pitchBendValue = static_cast<uint16_t>(uconstrain(value, 0, 16383));
+  // Split the 14-bit integer into two 7-bit values
+  uint8_t lsb = pitchBendValue & 0x7F;         // Lower 7 bits
+  uint8_t msb = (pitchBendValue >> 7) & 0x7F;  // Upper 7 bits
+
+  midiEventPacket_t event = {MIDI_CIN_PITCH_BEND_CHANGE, STATUS(MIDI_CIN_PITCH_BEND_CHANGE, channel), lsb, msb};
+  writePacket(&event);
+}
+
+// Pitch Bend Change [-1.0,0,1.0]
+void USBMIDI::pitchBend(double value, uint8_t channel) {
+  // Multiply by 8191 and round to nearest integer
+  int16_t pitchBendValue = static_cast<int16_t>(round(constrain(value, -1.0, 1.0) * 8191.0));
+
+  pitchBend(pitchBendValue, channel);
+}
+
+bool USBMIDI::readPacket(midiEventPacket_t *packet) {
+  return tud_midi_packet_read((uint8_t *)packet);
+}
+
+bool USBMIDI::writePacket(midiEventPacket_t *packet) {
+  return tud_midi_packet_write((uint8_t *)packet);
+}
+
+size_t USBMIDI::write(uint8_t c) {
+  // MIDI_CIN_1BYTE_DATA => Verbatim MIDI byte-stream copy
+  // (See also Table 4-1 of USB MIDI spec 1.0)
+  midiEventPacket_t packet = {DEFAULT_CN | MIDI_CIN_1BYTE_DATA, c, 0, 0};
+
+  return tud_midi_packet_write((uint8_t *)&packet);
+}
+
+#endif /* CONFIG_TINYUSB_MIDI_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBMIDI.h b/libraries/USB/src/USBMIDI.h
new file mode 100644
index 00000000000..91a1bfa4be1
--- /dev/null
+++ b/libraries/USB/src/USBMIDI.h
@@ -0,0 +1,61 @@
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+#include "esp32-hal-tinyusb.h"
+#include "sdkconfig.h"
+
+#if CONFIG_TINYUSB_MIDI_ENABLED
+
+#pragma once
+
+#define MIDI_EP_HEADER_CN_GET(x)  (x >> 4)
+#define MIDI_EP_HEADER_CIN_GET(x) ((midi_code_index_number_t)((x) & 0xF))
+
+typedef struct {
+  uint8_t header;
+  uint8_t byte1;
+  uint8_t byte2;
+  uint8_t byte3;
+} midiEventPacket_t;
+
+class USBMIDI {
+public:
+  USBMIDI(void);
+  void begin(void);
+  void end(void);
+
+  /* User-level API */
+
+  // Note On
+  void noteOn(uint8_t note, uint8_t velocity = 0, uint8_t channel = 1);
+  // Note Off
+  void noteOff(uint8_t note, uint8_t velocity = 0, uint8_t channel = 1);
+  // Program Change
+  void programChange(uint8_t inProgramNumber, uint8_t channel = 1);
+  // Control Change (Continuous Controller)
+  void controlChange(uint8_t inControlNumber, uint8_t inControlValue = 0, uint8_t channel = 1);
+  // Polyphonic Key Pressure (Aftertouch)
+  void polyPressure(uint8_t note, uint8_t pressure, uint8_t channel = 1);
+  // Channel Pressure (Aftertouch)
+  void channelPressure(uint8_t pressure, uint8_t channel = 1);
+  // Pitch Bend Change [-8192,0,8191]
+  void pitchBend(int16_t pitchBendValue, uint8_t channel = 1);
+  // Pitch Bend Change [0,8192,16383]
+  void pitchBend(uint16_t pitchBendValue, uint8_t channel = 1);
+  // Pitch Bend Change [-1.0,0,1.0]
+  void pitchBend(double pitchBendValue, uint8_t channel = 1);
+
+  /* USB MIDI 1.0 interface */
+
+  // Attempt to read a USB MIDI packet from the USB Bus
+  bool readPacket(midiEventPacket_t *packet);
+  // Attempt to write a USB MIDI packet to the USB Bus
+  bool writePacket(midiEventPacket_t *packet);
+
+  /* Serial MIDI 1.0 interface */
+
+  // Write a Serial MIDI byte (status or data) to the USB Bus
+  size_t write(uint8_t c);
+};
+
+#endif /* CONFIG_TINYUSB_MIDI_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBVendor.cpp b/libraries/USB/src/USBVendor.cpp
new file mode 100644
index 00000000000..70fac5770ae
--- /dev/null
+++ b/libraries/USB/src/USBVendor.cpp
@@ -0,0 +1,222 @@
+// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include "USBVendor.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#if CONFIG_TINYUSB_VENDOR_ENABLED
+
+#include "esp32-hal-tinyusb.h"
+
+ESP_EVENT_DEFINE_BASE(ARDUINO_USB_VENDOR_EVENTS);
+esp_err_t arduino_usb_event_post(esp_event_base_t event_base, int32_t event_id, void *event_data, size_t event_data_size, TickType_t ticks_to_wait);
+esp_err_t arduino_usb_event_handler_register_with(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler, void *event_handler_arg);
+
+static USBVendor *_Vendor = NULL;
+static QueueHandle_t rx_queue = NULL;
+static uint16_t USB_VENDOR_ENDPOINT_SIZE = CFG_TUD_ENDOINT_SIZE;
+
+uint16_t tusb_vendor_load_descriptor(uint8_t *dst, uint8_t *itf) {
+  uint8_t str_index = tinyusb_add_string_descriptor("TinyUSB Vendor");
+  uint8_t ep_num = tinyusb_get_free_duplex_endpoint();
+  TU_VERIFY(ep_num != 0);
+  uint8_t descriptor[TUD_VENDOR_DESC_LEN] = {// Interface number, string index, EP Out & IN address, EP size
+                                             TUD_VENDOR_DESCRIPTOR(*itf, str_index, ep_num, (uint8_t)(0x80 | ep_num), USB_VENDOR_ENDPOINT_SIZE)
+  };
+  *itf += 1;
+  memcpy(dst, descriptor, TUD_VENDOR_DESC_LEN);
+  return TUD_VENDOR_DESC_LEN;
+}
+
+void tud_vendor_rx_cb(uint8_t itf) {
+  size_t len = tud_vendor_n_available(itf);
+  log_v("%u", len);
+  if (len) {
+    uint8_t buffer[len];
+    len = tud_vendor_n_read(itf, buffer, len);
+    log_buf_v(buffer, len);
+    if (_Vendor) {
+      _Vendor->_onRX(buffer, len);
+    }
+  } else {
+    if (_Vendor) {
+      _Vendor->_onRX(NULL, len);
+    }
+  }
+}
+
+extern "C" bool tinyusb_vendor_control_request_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) {
+  log_v(
+    "Port: %u, Stage: %u, Direction: %u, Type: %u, Recipient: %u, bRequest: 0x%x, wValue: %u, wIndex: %u, wLength: %u", rhport, stage,
+    request->bmRequestType_bit.direction, request->bmRequestType_bit.type, request->bmRequestType_bit.recipient, request->bRequest, request->wValue,
+    request->wIndex, request->wLength
+  );
+
+  if (_Vendor) {
+    return _Vendor->_onRequest(rhport, stage, (arduino_usb_control_request_t const *)request);
+  }
+  return false;
+}
+
+USBVendor::USBVendor(uint16_t endpoint_size) : itf(0), cb(NULL) {
+  if (!_Vendor) {
+    _Vendor = this;
+    if (endpoint_size == 0) {
+      endpoint_size = CFG_TUD_ENDOINT_SIZE;
+    }
+    if (endpoint_size <= CFG_TUD_ENDOINT_SIZE) {
+      USB_VENDOR_ENDPOINT_SIZE = endpoint_size;
+    }
+    tinyusb_enable_interface(USB_INTERFACE_VENDOR, TUD_VENDOR_DESC_LEN, tusb_vendor_load_descriptor);
+  } else {
+    itf = _Vendor->itf;
+    cb = _Vendor->cb;
+  }
+}
+
+size_t USBVendor::setRxBufferSize(size_t rx_queue_len) {
+  if (rx_queue) {
+    if (!rx_queue_len) {
+      vQueueDelete(rx_queue);
+      rx_queue = NULL;
+    }
+    return 0;
+  }
+  rx_queue = xQueueCreate(rx_queue_len, sizeof(uint8_t));
+  if (!rx_queue) {
+    return 0;
+  }
+  return rx_queue_len;
+}
+
+void USBVendor::begin() {
+  setRxBufferSize(512);  //default if not preset
+}
+
+void USBVendor::end() {
+  setRxBufferSize(0);
+}
+
+void USBVendor::onEvent(esp_event_handler_t callback) {
+  onEvent(ARDUINO_USB_VENDOR_ANY_EVENT, callback);
+}
+
+void USBVendor::onEvent(arduino_usb_vendor_event_t event, esp_event_handler_t callback) {
+  arduino_usb_event_handler_register_with(ARDUINO_USB_VENDOR_EVENTS, event, callback, this);
+}
+
+bool USBVendor::mounted() {
+  return tud_vendor_n_mounted(itf);
+}
+
+bool USBVendor::sendResponse(uint8_t rhport, arduino_usb_control_request_t const *request, void *data, size_t len) {
+  if (!request) {
+    return false;
+  }
+  if (!data || !len) {
+    return tud_control_status(rhport, (tusb_control_request_t const *)request);
+  } else {
+    return tud_control_xfer(rhport, (tusb_control_request_t const *)request, data, len);
+  }
+}
+
+void USBVendor::onRequest(arduino_usb_vendor_control_request_handler_t handler) {
+  cb = handler;
+}
+
+bool USBVendor::_onRequest(uint8_t rhport, uint8_t stage, arduino_usb_control_request_t const *request) {
+  if (cb) {
+    return cb(rhport, stage, request);
+  }
+  return false;
+}
+
+void USBVendor::_onRX(const uint8_t *buffer, size_t len) {
+  for (uint32_t i = 0; i < len; i++) {
+    if (rx_queue == NULL || !xQueueSend(rx_queue, buffer + i, 0)) {
+      len = i + 1;
+      log_e("RX Queue Overflow");
+      break;
+    }
+  }
+  arduino_usb_vendor_event_data_t p;
+  p.data.len = len;
+  arduino_usb_event_post(ARDUINO_USB_VENDOR_EVENTS, ARDUINO_USB_VENDOR_DATA_EVENT, &p, sizeof(arduino_usb_vendor_event_data_t), portMAX_DELAY);
+}
+
+size_t USBVendor::write(const uint8_t *buffer, size_t len) {
+  if (!mounted()) {
+    log_e("not mounted");
+    return 0;
+  }
+  size_t max_len = tud_vendor_n_write_available(itf);
+  if (len > max_len) {
+    len = max_len;
+  }
+  if (len) {
+    return tud_vendor_n_write(itf, buffer, len);
+  }
+  return len;
+}
+
+size_t USBVendor::write(uint8_t c) {
+  return write(&c, 1);
+}
+
+int USBVendor::available(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  return uxQueueMessagesWaiting(rx_queue);
+}
+
+int USBVendor::peek(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c;
+  if (xQueuePeek(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+int USBVendor::read(void) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  if (xQueueReceive(rx_queue, &c, 0)) {
+    return c;
+  }
+  return -1;
+}
+
+size_t USBVendor::read(uint8_t *buffer, size_t size) {
+  if (rx_queue == NULL) {
+    return -1;
+  }
+  uint8_t c = 0;
+  size_t count = 0;
+  while (count < size && xQueueReceive(rx_queue, &c, 0)) {
+    buffer[count++] = c;
+  }
+  return count;
+}
+
+void USBVendor::flush(void) {
+  tud_vendor_n_write_flush(itf);
+}
+
+#endif /* CONFIG_TINYUSB_VENDOR_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/USBVendor.h b/libraries/USB/src/USBVendor.h
new file mode 100644
index 00000000000..4990e466321
--- /dev/null
+++ b/libraries/USB/src/USBVendor.h
@@ -0,0 +1,100 @@
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_USB_OTG_SUPPORTED
+
+#include "Stream.h"
+#include "sdkconfig.h"
+
+#if CONFIG_TINYUSB_VENDOR_ENABLED
+#include "esp_event.h"
+
+ESP_EVENT_DECLARE_BASE(ARDUINO_USB_VENDOR_EVENTS);
+
+#define REQUEST_STAGE_SETUP 0
+#define REQUEST_STAGE_DATA  1
+#define REQUEST_STAGE_ACK   2
+
+#define REQUEST_TYPE_STANDARD 0
+#define REQUEST_TYPE_CLASS    1
+#define REQUEST_TYPE_VENDOR   2
+#define REQUEST_TYPE_INVALID  3
+
+#define REQUEST_RECIPIENT_DEVICE    0
+#define REQUEST_RECIPIENT_INTERFACE 1
+#define REQUEST_RECIPIENT_ENDPOINT  2
+#define REQUEST_RECIPIENT_OTHER     3
+
+#define REQUEST_DIRECTION_OUT 0
+#define REQUEST_DIRECTION_IN  1
+
+typedef struct __attribute__((packed)) {
+  struct __attribute__((packed)) {
+    uint8_t bmRequestRecipient : 5;
+    uint8_t bmRequestType      : 2;
+    uint8_t bmRequestDirection : 1;
+  };
+  uint8_t bRequest;
+  uint16_t wValue;
+  uint16_t wIndex;
+  uint16_t wLength;
+} arduino_usb_control_request_t;
+
+typedef enum {
+  ARDUINO_USB_VENDOR_ANY_EVENT = ESP_EVENT_ANY_ID,
+  ARDUINO_USB_VENDOR_DATA_EVENT,
+  ARDUINO_USB_VENDOR_MAX_EVENT,
+} arduino_usb_vendor_event_t;
+
+typedef union {
+  struct {
+    uint16_t len;
+  } data;
+} arduino_usb_vendor_event_data_t;
+
+typedef bool (*arduino_usb_vendor_control_request_handler_t)(uint8_t rhport, uint8_t stage, arduino_usb_control_request_t const *request);
+
+class USBVendor : public Stream {
+private:
+  uint8_t itf;
+  arduino_usb_vendor_control_request_handler_t cb;
+
+public:
+  USBVendor(uint16_t endpoint_size = 0);
+  void begin(void);
+  void end(void);
+  size_t setRxBufferSize(size_t);
+  bool mounted(void);
+  size_t write(const uint8_t *buffer, size_t len);
+  size_t write(uint8_t);
+  int available(void);
+  int peek(void);
+  int read(void);
+  size_t read(uint8_t *buffer, size_t size);
+  void flush(void);
+
+  void onEvent(esp_event_handler_t callback);
+  void onEvent(arduino_usb_vendor_event_t event, esp_event_handler_t callback);
+  void onRequest(arduino_usb_vendor_control_request_handler_t handler);
+  bool sendResponse(uint8_t rhport, arduino_usb_control_request_t const *request, void *data = NULL, size_t len = 0);
+
+  bool _onRequest(uint8_t rhport, uint8_t stage, arduino_usb_control_request_t const *request);
+  void _onRX(const uint8_t *buffer, size_t len);
+};
+
+#endif /* CONFIG_TINYUSB_VENDOR_ENABLED */
+#endif /* SOC_USB_OTG_SUPPORTED */
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout.h b/libraries/USB/src/keyboardLayout/KeyboardLayout.h
new file mode 100644
index 00000000000..ee6b6b4e11e
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout.h
@@ -0,0 +1,68 @@
+/*
+  KeyboardLayout.h
+
+  This file is not part of the public API. It is meant to be included
+  only in Keyboard.cpp and the keyboard layout files. Layout files map
+  ASCII character codes to keyboard scan codes (technically, to USB HID
+  Usage codes), possibly altered by the SHIFT or ALT_GR modifiers.
+  Non-ASCII characters (anything outside the 7-bit range NUL..DEL) are
+  not supported.
+
+  == Creating your own layout ==
+
+  In order to create your own layout file, copy an existing layout that
+  is similar to yours, then modify it to use the correct keys. The
+  layout is an array in ASCII order. Each entry contains a scan code,
+  possibly modified by "|SHIFT" or "|ALT_GR", as in this excerpt from
+  the Italian layout:
+
+      0x35,          // bslash
+      0x30|ALT_GR,   // ]
+      0x2e|SHIFT,    // ^
+
+  Do not change the control characters (those before scan code 0x2c,
+  corresponding to space). Do not attempt to grow the table past DEL. Do
+  not use both SHIFT and ALT_GR on the same character: this is not
+  supported. Unsupported characters should have 0x00 as scan code.
+
+  For a keyboard with an ISO physical layout, use the scan codes below:
+
+      +---+---+---+---+---+---+---+---+---+---+---+---+---+-------+
+      |35 |1e |1f |20 |21 |22 |23 |24 |25 |26 |27 |2d |2e |BackSp |
+      +---+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-----+
+      | Tab |14 |1a |08 |15 |17 |1c |18 |0c |12 |13 |2f |30 | Ret |
+      +-----++--++--++--++--++--++--++--++--++--++--++--++--++    |
+      |CapsL |04 |16 |07 |09 |0a |0b |0d |0e |0f |33 |34 |31 |    |
+      +----+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+---+----+
+      |Shi.|32 |1d |1b |06 |19 |05 |11 |10 |36 |37 |38 |  Shift   |
+      +----+---++--+-+-+---+---+---+---+---+--++---+---++----+----+
+      |Ctrl|Win |Alt |                        |AlGr|Win |Menu|Ctrl|
+      +----+----+----+------------------------+----+----+----+----+
+
+  The ANSI layout is identical except that key 0x31 is above (rather
+  than next to) Return, and there is not key 0x32.
+
+  Give a unique name to the layout array, then declare it in Keyboard.h
+  with a line of the form:
+
+    extern const uint8_t KeyboardLayout_xx_YY[];
+
+  == Encoding details ==
+
+  All scan codes are less than 0x80, which makes bit 7 available to
+  signal that a modifier (Shift or AltGr) is needed to generate the
+  character. With only one exception, keys that are used with modifiers
+  have scan codes that are less than 0x40. This makes bit 6 available
+  to signal whether the modifier is Shift or AltGr. The exception is
+  0x64, the key next next to Left Shift on the ISO layout (and absent
+  from the ANSI layout). We handle it by replacing its value by 0x32 in
+  the layout arrays.
+*/
+
+#include <Arduino.h>
+
+// Modifier keys for _asciimap[] table (not to be used directly)
+#define SHIFT           0x80
+#define ALT_GR          0x40
+#define ISO_KEY         0x64
+#define ISO_REPLACEMENT 0x32
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_da_DK.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_da_DK.cpp
new file mode 100644
index 00000000000..7de2e1f6a43
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_da_DK.cpp
@@ -0,0 +1,137 @@
+/*
+ * Danish keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_da_DK[128] = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,           // ' '
+  0x1e | SHIFT,   // !
+  0x1f | SHIFT,   // "
+  0x20 | SHIFT,   // #
+  0x21 | ALT_GR,  // $
+  0x22 | SHIFT,   // %
+  0x23 | SHIFT,   // &
+  0x31,           // '
+  0x25 | SHIFT,   // (
+  0x26 | SHIFT,   // )
+  0x31 | SHIFT,   // *
+  0x2d,           // +
+  0x36,           // ,
+  0x38,           // -
+  0x37,           // .
+  0x24 | SHIFT,   // /
+  0x27,           // 0
+  0x1e,           // 1
+  0x1f,           // 2
+  0x20,           // 3
+  0x21,           // 4
+  0x22,           // 5
+  0x23,           // 6
+  0x24,           // 7
+  0x25,           // 8
+  0x26,           // 9
+  0x37 | SHIFT,   // :
+  0x36 | SHIFT,   // ;
+  0x32,           // <
+  0x27 | SHIFT,   // =
+  0x32 | SHIFT,   // >
+  0x2d | SHIFT,   // ?
+  0x1f | ALT_GR,  // @
+  0x04 | SHIFT,   // A
+  0x05 | SHIFT,   // B
+  0x06 | SHIFT,   // C
+  0x07 | SHIFT,   // D
+  0x08 | SHIFT,   // E
+  0x09 | SHIFT,   // F
+  0x0a | SHIFT,   // G
+  0x0b | SHIFT,   // H
+  0x0c | SHIFT,   // I
+  0x0d | SHIFT,   // J
+  0x0e | SHIFT,   // K
+  0x0f | SHIFT,   // L
+  0x10 | SHIFT,   // M
+  0x11 | SHIFT,   // N
+  0x12 | SHIFT,   // O
+  0x13 | SHIFT,   // P
+  0x14 | SHIFT,   // Q
+  0x15 | SHIFT,   // R
+  0x16 | SHIFT,   // S
+  0x17 | SHIFT,   // T
+  0x18 | SHIFT,   // U
+  0x19 | SHIFT,   // V
+  0x1a | SHIFT,   // W
+  0x1b | SHIFT,   // X
+  0x1c | SHIFT,   // Y
+  0x1d | SHIFT,   // Z
+  0x25 | ALT_GR,  // [
+  0x32 | ALT_GR,  // bslash
+  0x26 | ALT_GR,  // ]
+  0x00,           // ^  not supported (requires dead key + space)
+  0x38 | SHIFT,   // _
+  0x00,           // `  not supported (requires dead key + space)
+  0x04,           // a
+  0x05,           // b
+  0x06,           // c
+  0x07,           // d
+  0x08,           // e
+  0x09,           // f
+  0x0a,           // g
+  0x0b,           // h
+  0x0c,           // i
+  0x0d,           // j
+  0x0e,           // k
+  0x0f,           // l
+  0x10,           // m
+  0x11,           // n
+  0x12,           // o
+  0x13,           // p
+  0x14,           // q
+  0x15,           // r
+  0x16,           // s
+  0x17,           // t
+  0x18,           // u
+  0x19,           // v
+  0x1a,           // w
+  0x1b,           // x
+  0x1c,           // y
+  0x1d,           // z
+  0x24 | ALT_GR,  // {
+  0x2e | ALT_GR,  // |
+  0x27 | ALT_GR,  // }
+  0x00,           // ~  not supported (requires dead key + space)
+  0x00            // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_de_DE.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_de_DE.cpp
new file mode 100644
index 00000000000..0e430164e05
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_de_DE.cpp
@@ -0,0 +1,137 @@
+/*
+ * German keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_de_DE[128] PROGMEM = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,           // ' '
+  0x1e | SHIFT,   // !
+  0x1f | SHIFT,   // "
+  0x31,           // #
+  0x21 | SHIFT,   // $
+  0x22 | SHIFT,   // %
+  0x23 | SHIFT,   // &
+  0x31 | SHIFT,   // '
+  0x25 | SHIFT,   // (
+  0x26 | SHIFT,   // )
+  0x30 | SHIFT,   // *
+  0x30,           // +
+  0x36,           // ,
+  0x38,           // -
+  0x37,           // .
+  0x24 | SHIFT,   // /
+  0x27,           // 0
+  0x1e,           // 1
+  0x1f,           // 2
+  0x20,           // 3
+  0x21,           // 4
+  0x22,           // 5
+  0x23,           // 6
+  0x24,           // 7
+  0x25,           // 8
+  0x26,           // 9
+  0x37 | SHIFT,   // :
+  0x36 | SHIFT,   // ;
+  0x32,           // <
+  0x27 | SHIFT,   // =
+  0x32 | SHIFT,   // >
+  0x2d | SHIFT,   // ?
+  0x14 | ALT_GR,  // @
+  0x04 | SHIFT,   // A
+  0x05 | SHIFT,   // B
+  0x06 | SHIFT,   // C
+  0x07 | SHIFT,   // D
+  0x08 | SHIFT,   // E
+  0x09 | SHIFT,   // F
+  0x0a | SHIFT,   // G
+  0x0b | SHIFT,   // H
+  0x0c | SHIFT,   // I
+  0x0d | SHIFT,   // J
+  0x0e | SHIFT,   // K
+  0x0f | SHIFT,   // L
+  0x10 | SHIFT,   // M
+  0x11 | SHIFT,   // N
+  0x12 | SHIFT,   // O
+  0x13 | SHIFT,   // P
+  0x14 | SHIFT,   // Q
+  0x15 | SHIFT,   // R
+  0x16 | SHIFT,   // S
+  0x17 | SHIFT,   // T
+  0x18 | SHIFT,   // U
+  0x19 | SHIFT,   // V
+  0x1a | SHIFT,   // W
+  0x1b | SHIFT,   // X
+  0x1d | SHIFT,   // Y
+  0x1c | SHIFT,   // Z
+  0x25 | ALT_GR,  // [
+  0x2d | ALT_GR,  // bslash
+  0x26 | ALT_GR,  // ]
+  0x00,           // ^  not supported (requires dead key + space)
+  0x38 | SHIFT,   // _
+  0x00,           // `  not supported (requires dead key + space)
+  0x04,           // a
+  0x05,           // b
+  0x06,           // c
+  0x07,           // d
+  0x08,           // e
+  0x09,           // f
+  0x0a,           // g
+  0x0b,           // h
+  0x0c,           // i
+  0x0d,           // j
+  0x0e,           // k
+  0x0f,           // l
+  0x10,           // m
+  0x11,           // n
+  0x12,           // o
+  0x13,           // p
+  0x14,           // q
+  0x15,           // r
+  0x16,           // s
+  0x17,           // t
+  0x18,           // u
+  0x19,           // v
+  0x1a,           // w
+  0x1b,           // x
+  0x1d,           // y
+  0x1c,           // z
+  0x24 | ALT_GR,  // {
+  0x32 | ALT_GR,  // |
+  0x27 | ALT_GR,  // }
+  0x30 | ALT_GR,  // ~
+  0x00            // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_en_US.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_en_US.cpp
new file mode 100644
index 00000000000..36a961e779f
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_en_US.cpp
@@ -0,0 +1,137 @@
+/*
+ * Standard US keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_en_US[128] PROGMEM = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,          // ' '
+  0x1e | SHIFT,  // !
+  0x34 | SHIFT,  // "
+  0x20 | SHIFT,  // #
+  0x21 | SHIFT,  // $
+  0x22 | SHIFT,  // %
+  0x24 | SHIFT,  // &
+  0x34,          // '
+  0x26 | SHIFT,  // (
+  0x27 | SHIFT,  // )
+  0x25 | SHIFT,  // *
+  0x2e | SHIFT,  // +
+  0x36,          // ,
+  0x2d,          // -
+  0x37,          // .
+  0x38,          // /
+  0x27,          // 0
+  0x1e,          // 1
+  0x1f,          // 2
+  0x20,          // 3
+  0x21,          // 4
+  0x22,          // 5
+  0x23,          // 6
+  0x24,          // 7
+  0x25,          // 8
+  0x26,          // 9
+  0x33 | SHIFT,  // :
+  0x33,          // ;
+  0x36 | SHIFT,  // <
+  0x2e,          // =
+  0x37 | SHIFT,  // >
+  0x38 | SHIFT,  // ?
+  0x1f | SHIFT,  // @
+  0x04 | SHIFT,  // A
+  0x05 | SHIFT,  // B
+  0x06 | SHIFT,  // C
+  0x07 | SHIFT,  // D
+  0x08 | SHIFT,  // E
+  0x09 | SHIFT,  // F
+  0x0a | SHIFT,  // G
+  0x0b | SHIFT,  // H
+  0x0c | SHIFT,  // I
+  0x0d | SHIFT,  // J
+  0x0e | SHIFT,  // K
+  0x0f | SHIFT,  // L
+  0x10 | SHIFT,  // M
+  0x11 | SHIFT,  // N
+  0x12 | SHIFT,  // O
+  0x13 | SHIFT,  // P
+  0x14 | SHIFT,  // Q
+  0x15 | SHIFT,  // R
+  0x16 | SHIFT,  // S
+  0x17 | SHIFT,  // T
+  0x18 | SHIFT,  // U
+  0x19 | SHIFT,  // V
+  0x1a | SHIFT,  // W
+  0x1b | SHIFT,  // X
+  0x1c | SHIFT,  // Y
+  0x1d | SHIFT,  // Z
+  0x2f,          // [
+  0x31,          // bslash
+  0x30,          // ]
+  0x23 | SHIFT,  // ^
+  0x2d | SHIFT,  // _
+  0x35,          // `
+  0x04,          // a
+  0x05,          // b
+  0x06,          // c
+  0x07,          // d
+  0x08,          // e
+  0x09,          // f
+  0x0a,          // g
+  0x0b,          // h
+  0x0c,          // i
+  0x0d,          // j
+  0x0e,          // k
+  0x0f,          // l
+  0x10,          // m
+  0x11,          // n
+  0x12,          // o
+  0x13,          // p
+  0x14,          // q
+  0x15,          // r
+  0x16,          // s
+  0x17,          // t
+  0x18,          // u
+  0x19,          // v
+  0x1a,          // w
+  0x1b,          // x
+  0x1c,          // y
+  0x1d,          // z
+  0x2f | SHIFT,  // {
+  0x31 | SHIFT,  // |
+  0x30 | SHIFT,  // }
+  0x35 | SHIFT,  // ~
+  0x00           // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_es_ES.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_es_ES.cpp
new file mode 100644
index 00000000000..dac69cb92c3
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_es_ES.cpp
@@ -0,0 +1,137 @@
+/*
+ * Spanish keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_es_ES[128] PROGMEM = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,           // ' '
+  0x1e | SHIFT,   // !
+  0x1f | SHIFT,   // "
+  0x20 | ALT_GR,  // #
+  0x21 | SHIFT,   // $
+  0x22 | SHIFT,   // %
+  0x23 | SHIFT,   // &
+  0x2d,           // '
+  0x25 | SHIFT,   // (
+  0x26 | SHIFT,   // )
+  0x30 | SHIFT,   // *
+  0x30,           // +
+  0x36,           // ,
+  0x38,           // -
+  0x37,           // .
+  0x24 | SHIFT,   // /
+  0x27,           // 0
+  0x1e,           // 1
+  0x1f,           // 2
+  0x20,           // 3
+  0x21,           // 4
+  0x22,           // 5
+  0x23,           // 6
+  0x24,           // 7
+  0x25,           // 8
+  0x26,           // 9
+  0x37 | SHIFT,   // :
+  0x36 | SHIFT,   // ;
+  0x32,           // <
+  0x27 | SHIFT,   // =
+  0x32 | SHIFT,   // >
+  0x2d | SHIFT,   // ?
+  0x1f | ALT_GR,  // @
+  0x04 | SHIFT,   // A
+  0x05 | SHIFT,   // B
+  0x06 | SHIFT,   // C
+  0x07 | SHIFT,   // D
+  0x08 | SHIFT,   // E
+  0x09 | SHIFT,   // F
+  0x0a | SHIFT,   // G
+  0x0b | SHIFT,   // H
+  0x0c | SHIFT,   // I
+  0x0d | SHIFT,   // J
+  0x0e | SHIFT,   // K
+  0x0f | SHIFT,   // L
+  0x10 | SHIFT,   // M
+  0x11 | SHIFT,   // N
+  0x12 | SHIFT,   // O
+  0x13 | SHIFT,   // P
+  0x14 | SHIFT,   // Q
+  0x15 | SHIFT,   // R
+  0x16 | SHIFT,   // S
+  0x17 | SHIFT,   // T
+  0x18 | SHIFT,   // U
+  0x19 | SHIFT,   // V
+  0x1a | SHIFT,   // W
+  0x1b | SHIFT,   // X
+  0x1c | SHIFT,   // Y
+  0x1d | SHIFT,   // Z
+  0x2f | ALT_GR,  // [
+  0x35 | ALT_GR,  // bslash
+  0x30 | ALT_GR,  // ]
+  0x00,           // ^  not supported (requires dead key + space)
+  0x38 | SHIFT,   // _
+  0x00,           // `  not supported (requires dead key + space)
+  0x04,           // a
+  0x05,           // b
+  0x06,           // c
+  0x07,           // d
+  0x08,           // e
+  0x09,           // f
+  0x0a,           // g
+  0x0b,           // h
+  0x0c,           // i
+  0x0d,           // j
+  0x0e,           // k
+  0x0f,           // l
+  0x10,           // m
+  0x11,           // n
+  0x12,           // o
+  0x13,           // p
+  0x14,           // q
+  0x15,           // r
+  0x16,           // s
+  0x17,           // t
+  0x18,           // u
+  0x19,           // v
+  0x1a,           // w
+  0x1b,           // x
+  0x1c,           // y
+  0x1d,           // z
+  0x34 | ALT_GR,  // {
+  0x1e | ALT_GR,  // |
+  0x31 | ALT_GR,  // }
+  0x00,           // ~  not supported (requires dead key + space)
+  0x00            // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_fr_FR.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_fr_FR.cpp
new file mode 100644
index 00000000000..8728417d8d8
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_fr_FR.cpp
@@ -0,0 +1,137 @@
+/*
+ * Traditional (not AFNOR) French keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_fr_FR[128] PROGMEM = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,           // ' '
+  0x38,           // !
+  0x20,           // "
+  0x20 | ALT_GR,  // #
+  0x30,           // $
+  0x34 | SHIFT,   // %
+  0x1E,           // &
+  0x21,           // '
+  0x22,           // (
+  0x2d,           // )
+  0x31,           // *
+  0x2e | SHIFT,   // +
+  0x10,           // ,
+  0x23,           // -
+  0x36 | SHIFT,   // .
+  0x37 | SHIFT,   // /
+  0x27 | SHIFT,   // 0
+  0x1e | SHIFT,   // 1
+  0x1f | SHIFT,   // 2
+  0x20 | SHIFT,   // 3
+  0x21 | SHIFT,   // 4
+  0x22 | SHIFT,   // 5
+  0x23 | SHIFT,   // 6
+  0x24 | SHIFT,   // 7
+  0x25 | SHIFT,   // 8
+  0x26 | SHIFT,   // 9
+  0x37,           // :
+  0x36,           // ;
+  0x32,           // <
+  0x2e,           // =
+  0x32 | SHIFT,   // >
+  0x10 | SHIFT,   // ?
+  0x27 | ALT_GR,  // @
+  0x14 | SHIFT,   // A
+  0x05 | SHIFT,   // B
+  0x06 | SHIFT,   // C
+  0x07 | SHIFT,   // D
+  0x08 | SHIFT,   // E
+  0x09 | SHIFT,   // F
+  0x0a | SHIFT,   // G
+  0x0b | SHIFT,   // H
+  0x0c | SHIFT,   // I
+  0x0d | SHIFT,   // J
+  0x0e | SHIFT,   // K
+  0x0f | SHIFT,   // L
+  0x33 | SHIFT,   // M
+  0x11 | SHIFT,   // N
+  0x12 | SHIFT,   // O
+  0x13 | SHIFT,   // P
+  0x04 | SHIFT,   // Q
+  0x15 | SHIFT,   // R
+  0x16 | SHIFT,   // S
+  0x17 | SHIFT,   // T
+  0x18 | SHIFT,   // U
+  0x19 | SHIFT,   // V
+  0x1d | SHIFT,   // W
+  0x1b | SHIFT,   // X
+  0x1c | SHIFT,   // Y
+  0x1a | SHIFT,   // Z
+  0x22 | ALT_GR,  // [
+  0x25 | ALT_GR,  // bslash
+  0x2d | ALT_GR,  // ]
+  0x26 | ALT_GR,  // ^
+  0x25,           // _
+  0x24 | ALT_GR,  // `
+  0x14,           // a
+  0x05,           // b
+  0x06,           // c
+  0x07,           // d
+  0x08,           // e
+  0x09,           // f
+  0x0a,           // g
+  0x0b,           // h
+  0x0c,           // i
+  0x0d,           // j
+  0x0e,           // k
+  0x0f,           // l
+  0x33,           // m
+  0x11,           // n
+  0x12,           // o
+  0x13,           // p
+  0x04,           // q
+  0x15,           // r
+  0x16,           // s
+  0x17,           // t
+  0x18,           // u
+  0x19,           // v
+  0x1d,           // w
+  0x1b,           // x
+  0x1c,           // y
+  0x1a,           // z
+  0x21 | ALT_GR,  // {
+  0x23 | ALT_GR,  // |
+  0x2e | ALT_GR,  // }
+  0x1f | ALT_GR,  // ~
+  0x00            // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_hu_HU.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_hu_HU.cpp
new file mode 100644
index 00000000000..ff4344a7a0d
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_hu_HU.cpp
@@ -0,0 +1,143 @@
+/*
+ * Standard HU keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_hu_HU[128] PROGMEM = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,           // ' '
+  0x21 | SHIFT,   // !
+  0x1f | SHIFT,   // "
+  0x1b | ALT_GR,  // #
+  0x33 | ALT_GR,  // $
+  0x22 | SHIFT,   // %
+  0x06 | ALT_GR,  // &
+  0x1e | SHIFT,   // '
+  0x25 | SHIFT,   // (
+  0x26 | SHIFT,   // )
+  0x38 | ALT_GR,  // *
+  0x20 | SHIFT,   // +
+  0x36,           // ,
+  0x38,           // -
+  0x37,           // .
+  0x23 | SHIFT,   // /
+
+  0x35,  // 0
+  0x1e,  // 1
+  0x1f,  // 2
+  0x20,  // 3
+  0x21,  // 4
+  0x22,  // 5
+  0x23,  // 6
+  0x24,  // 7
+  0x25,  // 8
+  0x26,  // 9
+
+  0x37 | SHIFT,   // :
+  0x36 | ALT_GR,  // ;
+  0x32 | ALT_GR,  // <
+  0x24 | SHIFT,   // =
+  0x1d | ALT_GR,  // >
+  0x36 | SHIFT,   // ?
+  0x19 | ALT_GR,  // @
+
+  0x04 | SHIFT,  // A
+  0x05 | SHIFT,  // B
+  0x06 | SHIFT,  // C
+  0x07 | SHIFT,  // D
+  0x08 | SHIFT,  // E
+  0x09 | SHIFT,  // F
+  0x0a | SHIFT,  // G
+  0x0b | SHIFT,  // H
+  0x0c | SHIFT,  // I
+  0x0d | SHIFT,  // J
+  0x0e | SHIFT,  // K
+  0x0f | SHIFT,  // L
+  0x10 | SHIFT,  // M
+  0x11 | SHIFT,  // N
+  0x12 | SHIFT,  // O
+  0x13 | SHIFT,  // P
+  0x14 | SHIFT,  // Q
+  0x15 | SHIFT,  // R
+  0x16 | SHIFT,  // S
+  0x17 | SHIFT,  // T
+  0x18 | SHIFT,  // U
+  0x19 | SHIFT,  // V
+  0x1a | SHIFT,  // W
+  0x1b | SHIFT,  // X
+  0x1d | SHIFT,  // Y
+  0x1c | SHIFT,  // Z
+
+  0x09 | ALT_GR,  // [
+  0x14 | ALT_GR,  // bslash
+  0x0a | ALT_GR,  // ]
+  0x20 | ALT_GR,  // ^
+  0x38 | SHIFT,   // _
+  0x24 | ALT_GR,  // `
+
+  0x04,  // a
+  0x05,  // b
+  0x06,  // c
+  0x07,  // d
+  0x08,  // e
+  0x09,  // f
+  0x0a,  // g
+  0x0b,  // h
+  0x0c,  // i
+  0x0d,  // j
+  0x0e,  // k
+  0x0f,  // l
+  0x10,  // m
+  0x11,  // n
+  0x12,  // o
+  0x13,  // p
+  0x14,  // q
+  0x15,  // r
+  0x16,  // s
+  0x17,  // t
+  0x18,  // u
+  0x19,  // v
+  0x1a,  // w
+  0x1b,  // x
+  0x1d,  // y
+  0x1c,  // z
+
+  0x05 | ALT_GR,  // {
+  0x1a | ALT_GR,  // |
+  0x11 | ALT_GR,  // }
+  0x1e | ALT_GR,  // ~
+  0x00            // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_it_IT.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_it_IT.cpp
new file mode 100644
index 00000000000..60a46bcd59f
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_it_IT.cpp
@@ -0,0 +1,137 @@
+/*
+ * Italian keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_it_IT[128] PROGMEM = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,           // ' '
+  0x1e | SHIFT,   // !
+  0x1f | SHIFT,   // "
+  0x34 | ALT_GR,  // #
+  0x21 | SHIFT,   // $
+  0x22 | SHIFT,   // %
+  0x23 | SHIFT,   // &
+  0x2d,           // '
+  0x25 | SHIFT,   // (
+  0x26 | SHIFT,   // )
+  0x30 | SHIFT,   // *
+  0x30,           // +
+  0x36,           // ,
+  0x38,           // -
+  0x37,           // .
+  0x24 | SHIFT,   // /
+  0x27,           // 0
+  0x1e,           // 1
+  0x1f,           // 2
+  0x20,           // 3
+  0x21,           // 4
+  0x22,           // 5
+  0x23,           // 6
+  0x24,           // 7
+  0x25,           // 8
+  0x26,           // 9
+  0x37 | SHIFT,   // :
+  0x36 | SHIFT,   // ;
+  0x32,           // <
+  0x27 | SHIFT,   // =
+  0x32 | SHIFT,   // >
+  0x2d | SHIFT,   // ?
+  0x33 | ALT_GR,  // @
+  0x04 | SHIFT,   // A
+  0x05 | SHIFT,   // B
+  0x06 | SHIFT,   // C
+  0x07 | SHIFT,   // D
+  0x08 | SHIFT,   // E
+  0x09 | SHIFT,   // F
+  0x0a | SHIFT,   // G
+  0x0b | SHIFT,   // H
+  0x0c | SHIFT,   // I
+  0x0d | SHIFT,   // J
+  0x0e | SHIFT,   // K
+  0x0f | SHIFT,   // L
+  0x10 | SHIFT,   // M
+  0x11 | SHIFT,   // N
+  0x12 | SHIFT,   // O
+  0x13 | SHIFT,   // P
+  0x14 | SHIFT,   // Q
+  0x15 | SHIFT,   // R
+  0x16 | SHIFT,   // S
+  0x17 | SHIFT,   // T
+  0x18 | SHIFT,   // U
+  0x19 | SHIFT,   // V
+  0x1a | SHIFT,   // W
+  0x1b | SHIFT,   // X
+  0x1c | SHIFT,   // Y
+  0x1d | SHIFT,   // Z
+  0x2f | ALT_GR,  // [
+  0x35,           // bslash
+  0x30 | ALT_GR,  // ]
+  0x2e | SHIFT,   // ^
+  0x38 | SHIFT,   // _
+  0x00,           // `  not in this layout
+  0x04,           // a
+  0x05,           // b
+  0x06,           // c
+  0x07,           // d
+  0x08,           // e
+  0x09,           // f
+  0x0a,           // g
+  0x0b,           // h
+  0x0c,           // i
+  0x0d,           // j
+  0x0e,           // k
+  0x0f,           // l
+  0x10,           // m
+  0x11,           // n
+  0x12,           // o
+  0x13,           // p
+  0x14,           // q
+  0x15,           // r
+  0x16,           // s
+  0x17,           // t
+  0x18,           // u
+  0x19,           // v
+  0x1a,           // w
+  0x1b,           // x
+  0x1c,           // y
+  0x1d,           // z
+  0x00,           // {  not supported (requires AltGr+Shift)
+  0x35 | SHIFT,   // |
+  0x00,           // }  not supported (requires AltGr+Shift)
+  0x00,           // ~  not in this layout
+  0x00            // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_BR.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_BR.cpp
new file mode 100644
index 00000000000..09014a7e04c
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_BR.cpp
@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Keyboard_pt_BR.h
+ * Portuguese Brazilian keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_pt_BR[128] PROGMEM = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,           // ' '
+  0x1e | SHIFT,   // !
+  0x35 | SHIFT,   // "
+  0x20 | SHIFT,   // #
+  0x21 | SHIFT,   // $
+  0x22 | SHIFT,   // %
+  0x24 | SHIFT,   // &
+  0x35,           // '
+  0x26 | SHIFT,   // (
+  0x27 | SHIFT,   // )
+  0x25 | SHIFT,   // *
+  0x2e | SHIFT,   // +
+  0x36,           // ,
+  0x2d,           // -
+  0x37,           // .
+  0x14 | ALT_GR,  // /  R_ALT + q
+  0x27,           // 0
+  0x1e,           // 1
+  0x1f,           // 2
+  0x20,           // 3
+  0x21,           // 4
+  0x22,           // 5
+  0x23,           // 6
+  0x24,           // 7
+  0x25,           // 8
+  0x26,           // 9
+  0x38 | SHIFT,   // :
+  0x38,           // ;
+  0x36 | SHIFT,   // <
+  0x2e,           // =
+  0x37 | SHIFT,   // >
+  0x1a | ALT_GR,  // ?  R_ALT + w
+  0x1f | SHIFT,   // @
+  0x04 | SHIFT,   // A
+  0x05 | SHIFT,   // B
+  0x06 | SHIFT,   // C
+  0x07 | SHIFT,   // D
+  0x08 | SHIFT,   // E
+  0x09 | SHIFT,   // F
+  0x0a | SHIFT,   // G
+  0x0b | SHIFT,   // H
+  0x0c | SHIFT,   // I
+  0x0d | SHIFT,   // J
+  0x0e | SHIFT,   // K
+  0x0f | SHIFT,   // L
+  0x10 | SHIFT,   // M
+  0x11 | SHIFT,   // N
+  0x12 | SHIFT,   // O
+  0x13 | SHIFT,   // P
+  0x14 | SHIFT,   // Q
+  0x15 | SHIFT,   // R
+  0x16 | SHIFT,   // S
+  0x17 | SHIFT,   // T
+  0x18 | SHIFT,   // U
+  0x19 | SHIFT,   // V
+  0x1a | SHIFT,   // W
+  0x1b | SHIFT,   // X
+  0x1c | SHIFT,   // Y
+  0x1d | SHIFT,   // Z
+  0x30,           // [
+  0x32,           // bslash    -->ISO Key
+  0x31,           // ]
+  0x34 | SHIFT,   // ^
+  0x2d | SHIFT,   // _
+  0x2f | SHIFT,   // `
+  0x04,           // a
+  0x05,           // b
+  0x06,           // c
+  0x07,           // d
+  0x08,           // e
+  0x09,           // f
+  0x0a,           // g
+  0x0b,           // h
+  0x0c,           // i
+  0x0d,           // j
+  0x0e,           // k
+  0x0f,           // l
+  0x10,           // m
+  0x11,           // n
+  0x12,           // o
+  0x13,           // p
+  0x14,           // q
+  0x15,           // r
+  0x16,           // s
+  0x17,           // t
+  0x18,           // u
+  0x19,           // v
+  0x1a,           // w
+  0x1b,           // x
+  0x1c,           // y
+  0x1d,           // z
+  0x30 | SHIFT,   // {
+  0x32 | SHIFT,   // |  -->ISO Key
+  0x31 | SHIFT,   // }
+  0x34,           // ~
+  0x4c            // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_PT.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_PT.cpp
new file mode 100644
index 00000000000..4f0c53d536d
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_pt_PT.cpp
@@ -0,0 +1,137 @@
+/*
+ * Portuguese keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_pt_PT[128] PROGMEM = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,           // ' '
+  0x1e | SHIFT,   // !
+  0x1f | SHIFT,   // "
+  0x20 | SHIFT,   // #
+  0x21 | SHIFT,   // $
+  0x22 | SHIFT,   // %
+  0x23 | SHIFT,   // &
+  0x2d,           // '
+  0x25 | SHIFT,   // (
+  0x26 | SHIFT,   // )
+  0x2f | SHIFT,   // *
+  0x2f,           // +
+  0x36,           // ,
+  0x38,           // -
+  0x37,           // .
+  0x24 | SHIFT,   // /
+  0x27,           // 0
+  0x1e,           // 1
+  0x1f,           // 2
+  0x20,           // 3
+  0x21,           // 4
+  0x22,           // 5
+  0x23,           // 6
+  0x24,           // 7
+  0x25,           // 8
+  0x26,           // 9
+  0x37 | SHIFT,   // :
+  0x36 | SHIFT,   // ;
+  0x32,           // <
+  0x27 | SHIFT,   // =
+  0x32 | SHIFT,   // >
+  0x2d | SHIFT,   // ?
+  0x1f | ALT_GR,  // @
+  0x04 | SHIFT,   // A
+  0x05 | SHIFT,   // B
+  0x06 | SHIFT,   // C
+  0x07 | SHIFT,   // D
+  0x08 | SHIFT,   // E
+  0x09 | SHIFT,   // F
+  0x0a | SHIFT,   // G
+  0x0b | SHIFT,   // H
+  0x0c | SHIFT,   // I
+  0x0d | SHIFT,   // J
+  0x0e | SHIFT,   // K
+  0x0f | SHIFT,   // L
+  0x10 | SHIFT,   // M
+  0x11 | SHIFT,   // N
+  0x12 | SHIFT,   // O
+  0x13 | SHIFT,   // P
+  0x14 | SHIFT,   // Q
+  0x15 | SHIFT,   // R
+  0x16 | SHIFT,   // S
+  0x17 | SHIFT,   // T
+  0x18 | SHIFT,   // U
+  0x19 | SHIFT,   // V
+  0x1a | SHIFT,   // W
+  0x1b | SHIFT,   // X
+  0x1c | SHIFT,   // Y
+  0x1d | SHIFT,   // Z
+  0x25 | ALT_GR,  // [
+  0x35,           // bslash
+  0x26 | ALT_GR,  // ]
+  0x00,           // ^  not supported (requires dead key + space)
+  0x38 | SHIFT,   // _
+  0x00,           // `  not supported (requires dead key + space)
+  0x04,           // a
+  0x05,           // b
+  0x06,           // c
+  0x07,           // d
+  0x08,           // e
+  0x09,           // f
+  0x0a,           // g
+  0x0b,           // h
+  0x0c,           // i
+  0x0d,           // j
+  0x0e,           // k
+  0x0f,           // l
+  0x10,           // m
+  0x11,           // n
+  0x12,           // o
+  0x13,           // p
+  0x14,           // q
+  0x15,           // r
+  0x16,           // s
+  0x17,           // t
+  0x18,           // u
+  0x19,           // v
+  0x1a,           // w
+  0x1b,           // x
+  0x1c,           // y
+  0x1d,           // z
+  0x24 | ALT_GR,  // {
+  0x35 | SHIFT,   // |
+  0x27 | ALT_GR,  // }
+  0x00,           // ~  not supported (requires dead key + space)
+  0x00            // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/KeyboardLayout_sv_SE.cpp b/libraries/USB/src/keyboardLayout/KeyboardLayout_sv_SE.cpp
new file mode 100644
index 00000000000..8ef92c1a0e6
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/KeyboardLayout_sv_SE.cpp
@@ -0,0 +1,137 @@
+/*
+ * Swedish keyboard layout.
+ */
+
+#include "KeyboardLayout.h"
+
+extern const uint8_t KeyboardLayout_sv_SE[128] PROGMEM = {
+  0x00,  // NUL
+  0x00,  // SOH
+  0x00,  // STX
+  0x00,  // ETX
+  0x00,  // EOT
+  0x00,  // ENQ
+  0x00,  // ACK
+  0x00,  // BEL
+  0x2a,  // BS  Backspace
+  0x2b,  // TAB Tab
+  0x28,  // LF  Enter
+  0x00,  // VT
+  0x00,  // FF
+  0x00,  // CR
+  0x00,  // SO
+  0x00,  // SI
+  0x00,  // DEL
+  0x00,  // DC1
+  0x00,  // DC2
+  0x00,  // DC3
+  0x00,  // DC4
+  0x00,  // NAK
+  0x00,  // SYN
+  0x00,  // ETB
+  0x00,  // CAN
+  0x00,  // EM
+  0x00,  // SUB
+  0x00,  // ESC
+  0x00,  // FS
+  0x00,  // GS
+  0x00,  // RS
+  0x00,  // US
+
+  0x2c,           // ' '
+  0x1e | SHIFT,   // !
+  0x1f | SHIFT,   // "
+  0x20 | SHIFT,   // #
+  0x21 | ALT_GR,  // $
+  0x22 | SHIFT,   // %
+  0x23 | SHIFT,   // &
+  0x31,           // '
+  0x25 | SHIFT,   // (
+  0x26 | SHIFT,   // )
+  0x31 | SHIFT,   // *
+  0x2d,           // +
+  0x36,           // ,
+  0x38,           // -
+  0x37,           // .
+  0x24 | SHIFT,   // /
+  0x27,           // 0
+  0x1e,           // 1
+  0x1f,           // 2
+  0x20,           // 3
+  0x21,           // 4
+  0x22,           // 5
+  0x23,           // 6
+  0x24,           // 7
+  0x25,           // 8
+  0x26,           // 9
+  0x37 | SHIFT,   // :
+  0x36 | SHIFT,   // ;
+  0x32,           // <
+  0x27 | SHIFT,   // =
+  0x32 | SHIFT,   // >
+  0x2d | SHIFT,   // ?
+  0x1f | ALT_GR,  // @
+  0x04 | SHIFT,   // A
+  0x05 | SHIFT,   // B
+  0x06 | SHIFT,   // C
+  0x07 | SHIFT,   // D
+  0x08 | SHIFT,   // E
+  0x09 | SHIFT,   // F
+  0x0a | SHIFT,   // G
+  0x0b | SHIFT,   // H
+  0x0c | SHIFT,   // I
+  0x0d | SHIFT,   // J
+  0x0e | SHIFT,   // K
+  0x0f | SHIFT,   // L
+  0x10 | SHIFT,   // M
+  0x11 | SHIFT,   // N
+  0x12 | SHIFT,   // O
+  0x13 | SHIFT,   // P
+  0x14 | SHIFT,   // Q
+  0x15 | SHIFT,   // R
+  0x16 | SHIFT,   // S
+  0x17 | SHIFT,   // T
+  0x18 | SHIFT,   // U
+  0x19 | SHIFT,   // V
+  0x1a | SHIFT,   // W
+  0x1b | SHIFT,   // X
+  0x1c | SHIFT,   // Y
+  0x1d | SHIFT,   // Z
+  0x25 | ALT_GR,  // [
+  0x2d | ALT_GR,  // bslash
+  0x26 | ALT_GR,  // ]
+  0x00,           // ^  not supported (requires dead key + space)
+  0x38 | SHIFT,   // _
+  0x00,           // `  not supported (requires dead key + space)
+  0x04,           // a
+  0x05,           // b
+  0x06,           // c
+  0x07,           // d
+  0x08,           // e
+  0x09,           // f
+  0x0a,           // g
+  0x0b,           // h
+  0x0c,           // i
+  0x0d,           // j
+  0x0e,           // k
+  0x0f,           // l
+  0x10,           // m
+  0x11,           // n
+  0x12,           // o
+  0x13,           // p
+  0x14,           // q
+  0x15,           // r
+  0x16,           // s
+  0x17,           // t
+  0x18,           // u
+  0x19,           // v
+  0x1a,           // w
+  0x1b,           // x
+  0x1c,           // y
+  0x1d,           // z
+  0x24 | ALT_GR,  // {
+  0x32 | ALT_GR,  // |
+  0x27 | ALT_GR,  // }
+  0x00,           // ~  not supported (requires dead key + space)
+  0x00            // DEL
+};
diff --git a/libraries/USB/src/keyboardLayout/Keyboard_da_DK.h b/libraries/USB/src/keyboardLayout/Keyboard_da_DK.h
new file mode 100644
index 00000000000..8ad1540ac57
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/Keyboard_da_DK.h
@@ -0,0 +1,35 @@
+/*
+  Keyboard_da_DK.h
+
+  Copyright (c) 2021, Peter John
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef KEYBOARD_DA_DK_h
+#define KEYBOARD_DA_DK_h
+
+//================================================================================
+//================================================================================
+//  Keyboard
+
+// DA_DK keys
+#define KEY_A_RING    (0x88 + 0x2f)
+#define KEY_SLASHED_O (0x88 + 0x34)
+#define KEY_ASH       (0x88 + 0x33)
+#define KEY_UMLAUT    (0x88 + 0x30)
+#define KEY_ACUTE_ACC (0x88 + 0x2e)
+
+#endif
diff --git a/libraries/USB/src/keyboardLayout/Keyboard_de_DE.h b/libraries/USB/src/keyboardLayout/Keyboard_de_DE.h
new file mode 100644
index 00000000000..8fec4e1b244
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/Keyboard_de_DE.h
@@ -0,0 +1,36 @@
+/*
+  Keyboard_de_DE.h
+
+  Copyright (c) 2022, Edgar Bonet
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef KEYBOARD_DE_DE_h
+#define KEYBOARD_DE_DE_h
+
+//================================================================================
+//================================================================================
+//  Keyboard
+
+// de_DE keys
+#define KEY_CIRCUMFLEX (0x88 + 0x35)
+#define KEY_ESZETT     (0x88 + 0x2d)
+#define KEY_ACUTE      (0x88 + 0x2e)
+#define KEY_U_UMLAUT   (0x88 + 0x2f)
+#define KEY_O_UMLAUT   (0x88 + 0x33)
+#define KEY_A_UMLAUT   (0x88 + 0x34)
+
+#endif
diff --git a/libraries/USB/src/keyboardLayout/Keyboard_es_ES.h b/libraries/USB/src/keyboardLayout/Keyboard_es_ES.h
new file mode 100644
index 00000000000..25f7c01395b
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/Keyboard_es_ES.h
@@ -0,0 +1,37 @@
+/*
+  Keyboard_es_ES.h
+
+  Copyright (c) 2022, Edgar Bonet
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef KEYBOARD_ES_ES_h
+#define KEYBOARD_ES_ES_h
+
+#include "class/hid/hid.h"
+//================================================================================
+//================================================================================
+//  Keyboard
+
+// es_ES keys
+#define KEY_MASCULINE_ORDINAL    (0x88 + 0x35)
+#define KEY_INVERTED_EXCLAMATION (0x88 + 0x2e)
+#define KEY_GRAVE                (0x88 + 0x2f)
+#define KEY_N_TILDE              (0x88 + 0x33)
+#define KEY_ACUTE                (0x88 + 0x34)
+#define KEY_C_CEDILLA            (0x88 + 0x31)
+
+#endif
diff --git a/libraries/USB/src/keyboardLayout/Keyboard_fr_FR.h b/libraries/USB/src/keyboardLayout/Keyboard_fr_FR.h
new file mode 100644
index 00000000000..d5d9fa80402
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/Keyboard_fr_FR.h
@@ -0,0 +1,37 @@
+/*
+  Keyboard_fr_FR.h
+
+  Copyright (c) 2022, Edgar Bonet
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef KEYBOARD_FR_FR_h
+#define KEYBOARD_FR_FR_h
+
+//================================================================================
+//================================================================================
+//  Keyboard
+
+// fr_FR keys
+#define KEY_SUPERSCRIPT_TWO (0x88 + 0x35)
+#define KEY_E_ACUTE         (0x88 + 0x1f)
+#define KEY_E_GRAVE         (0x88 + 0x24)
+#define KEY_C_CEDILLA       (0x88 + 0x26)
+#define KEY_A_GRAVE         (0x88 + 0x27)
+#define KEY_CIRCUMFLEX      (0x88 + 0x2f)
+#define KEY_U_GRAVE         (0x88 + 0x34)
+
+#endif
diff --git a/libraries/USB/src/keyboardLayout/Keyboard_hu_HU.h b/libraries/USB/src/keyboardLayout/Keyboard_hu_HU.h
new file mode 100644
index 00000000000..b0214319690
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/Keyboard_hu_HU.h
@@ -0,0 +1,43 @@
+/*
+  Keyboard_hu_HU.h
+
+  Copyright (c) 2023, Barab(0x34)si Rich(0x34)rd
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef KEYBOARD_HU_HU_h
+#define KEYBOARD_HU_HU_h
+
+//================================================================================
+//================================================================================
+//  Keyboard
+
+// hu_HU keys
+#define KEY_O_ACUTE        (0x88 + 0x2e)
+#define KEY_O_UMLAUT       (0x88 + 0x27)
+#define KEY_O_DOUBLE_ACUTE (0x88 + 0x2f)
+
+#define KEY_U_ACUTE        (0x88 + 0x30)
+#define KEY_U_UMLAUT       (0x88 + 0x2d)
+#define KEY_U_DOUBLE_ACUTE (0x88 + 0x31)
+
+#define KEY_A_ACUTE (0x88 + 0x34)
+
+#define KEY_E_ACUTE (0x88 + 0x33)
+
+#define KEY_I_ACUTE (0x88 + 0x32)
+
+#endif
diff --git a/libraries/USB/src/keyboardLayout/Keyboard_it_IT.h b/libraries/USB/src/keyboardLayout/Keyboard_it_IT.h
new file mode 100644
index 00000000000..41b52c8bb53
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/Keyboard_it_IT.h
@@ -0,0 +1,35 @@
+/*
+  Keyboard_it_IT.h
+
+  Copyright (c) 2022, Edgar Bonet
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef KEYBOARD_IT_IT_h
+#define KEYBOARD_IT_IT_h
+
+//================================================================================
+//================================================================================
+//  Keyboard
+
+// it_IT keys
+#define KEY_I_GRAVE (0x88 + 0x2e)
+#define KEY_E_GRAVE (0x88 + 0x2f)
+#define KEY_O_GRAVE (0x88 + 0x33)
+#define KEY_A_GRAVE (0x88 + 0x34)
+#define KEY_U_GRAVE (0x88 + 0x31)
+
+#endif
diff --git a/libraries/USB/src/keyboardLayout/Keyboard_pt_BR.h b/libraries/USB/src/keyboardLayout/Keyboard_pt_BR.h
new file mode 100644
index 00000000000..6b597e56386
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/Keyboard_pt_BR.h
@@ -0,0 +1,25 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Keyboard_pt_BR.h
+ * Portuguese Brazilian keyboard layout.
+*/
+
+#ifndef KEYBOARD_PT_BR_h
+#define KEYBOARD_PT_BR_h
+
+//================================================================================
+//================================================================================
+//  Keyboard
+
+// pt_BR keys
+#define KEY_C_CEDILLA (0x88 + 0x33)
+#define KEY_ACUTE     (0x88 + 0x2f)
+// use the pressRaw() to press the modification key and then press the key you want to modify
+#define KEY_MASCULINE_ORDINAL (0x88 + 0x32)  // first pressRaw(HID_KEY_ALT_RIGHT), then press(KEY_MASCULINE_ORDINAL)
+#define KEY_FEMININE_ORDINAL  (0x88 + 0x30)  // first pressRaw(HID_KEY_ALT_RIGHT), then press(KEY_FEMININE_ORDINAL)
+#define KEY_PARAGRAPH         (0x88 + 0x2e)  // first pressRaw(HID_KEY_ALT_RIGHT), then press(KEY_PARAGRAPH)
+#define KEY_UMLAUT            (0x88 + 0x23)  // first pressRaw(HID_KEY_SHIFT_RIGHT), then press(KEY_UMLAUT)
+
+#endif
diff --git a/libraries/USB/src/keyboardLayout/Keyboard_pt_PT.h b/libraries/USB/src/keyboardLayout/Keyboard_pt_PT.h
new file mode 100644
index 00000000000..c1a2dbfebf6
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/Keyboard_pt_PT.h
@@ -0,0 +1,35 @@
+/*
+  Keyboard_pt_PT.h
+
+  Copyright (c) 2022, Edgar Bonet
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef KEYBOARD_PT_PT_h
+#define KEYBOARD_PT_PT_h
+
+//================================================================================
+//================================================================================
+//  Keyboard
+
+// pt_PT keys
+#define KEY_LEFT_GUILLEMET    (0x88 + 0x2e)
+#define KEY_ACUTE             (0x88 + 0x30)
+#define KEY_C_CEDILLA         (0x88 + 0x33)
+#define KEY_MASCULINE_ORDINAL (0x88 + 0x34)
+#define KEY_TILDE             (0x88 + 0x31)
+
+#endif
diff --git a/libraries/USB/src/keyboardLayout/Keyboard_sv_SE.h b/libraries/USB/src/keyboardLayout/Keyboard_sv_SE.h
new file mode 100644
index 00000000000..1a3e3bc6087
--- /dev/null
+++ b/libraries/USB/src/keyboardLayout/Keyboard_sv_SE.h
@@ -0,0 +1,35 @@
+/*
+  Keyboard_sv_SE.h
+
+  Copyright (c) 2021, Peter John
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#ifndef KEYBOARD_SV_SE_h
+#define KEYBOARD_SV_SE_h
+
+//================================================================================
+//================================================================================
+//  Keyboard
+
+// SV_SE keys
+#define KEY_A_RING    (0x88 + 0x2f)
+#define KEY_A_UMLAUT  (0x88 + 0x34)
+#define KEY_O_UMLAUT  (0x88 + 0x33)
+#define KEY_UMLAUT    (0x88 + 0x30)
+#define KEY_ACUTE_ACC (0x88 + 0x2e)
+
+#endif
diff --git a/libraries/Update/examples/AWS_S3_OTA_Update/AWS_S3_OTA_Update.ino b/libraries/Update/examples/AWS_S3_OTA_Update/AWS_S3_OTA_Update.ino
index 8582874f129..08c0a5a9ff0 100644
--- a/libraries/Update/examples/AWS_S3_OTA_Update/AWS_S3_OTA_Update.ino
+++ b/libraries/Update/examples/AWS_S3_OTA_Update/AWS_S3_OTA_Update.ino
@@ -22,7 +22,7 @@
 #include <WiFi.h>
 #include <Update.h>
 
-WiFiClient client;
+NetworkClient client;
 
 // Variables to validate
 // response from S3
@@ -31,33 +31,30 @@ bool isValidContentType = false;
 
 // Your SSID and PSWD that the chip needs
 // to connect to
-const char* SSID = "YOUR-SSID";
-const char* PSWD = "YOUR-SSID-PSWD";
+const char *SSID = "YOUR-SSID";
+const char *PSWD = "YOUR-SSID-PSWD";
 
 // S3 Bucket Config
-String host = "bucket-name.s3.ap-south-1.amazonaws.com"; // Host => bucket-name.s3.region.amazonaws.com
-int port = 80; // Non https. For HTTPS 443. As of today, HTTPS doesn't work.
-String bin = "/sketch-name.ino.bin"; // bin file name with a slash in front.
+String host = "bucket-name.s3.ap-south-1.amazonaws.com";  // Host => bucket-name.s3.region.amazonaws.com
+int port = 80;                                            // Non https. For HTTPS 443. As of today, HTTPS doesn't work.
+String bin = "/sketch-name.ino.bin";                      // bin file name with a slash in front.
 
 // Utility to extract header value from headers
 String getHeaderValue(String header, String headerName) {
   return header.substring(strlen(headerName.c_str()));
 }
 
-// OTA Logic 
+// OTA Logic
 void execOTA() {
   Serial.println("Connecting to: " + String(host));
   // Connect to S3
   if (client.connect(host.c_str(), port)) {
     // Connection Succeed.
-    // Fecthing the bin
+    // Fetching the bin
     Serial.println("Fetching Bin: " + String(bin));
 
     // Get the contents of the bin file
-    client.print(String("GET ") + bin + " HTTP/1.1\r\n" +
-                 "Host: " + host + "\r\n" +
-                 "Cache-Control: no-cache\r\n" +
-                 "Connection: close\r\n\r\n");
+    client.print(String("GET ") + bin + " HTTP/1.1\r\n" + "Host: " + host + "\r\n" + "Cache-Control: no-cache\r\n" + "Connection: close\r\n\r\n");
 
     // Check what is being sent
     //    Serial.print(String("GET ") + bin + " HTTP/1.1\r\n" +
@@ -88,7 +85,7 @@ void execOTA() {
         Content-Type: application/octet-stream
         Content-Length: 357280
         Server: AmazonS3
-                                   
+
         {{BIN FILE CONTENTS}}
 
     */
@@ -105,7 +102,7 @@ void execOTA() {
       // Update.writeStream();
       if (!line.length()) {
         //headers ended
-        break; // and get the OTA started
+        break;  // and get the OTA started
       }
 
       // Check if the HTTP Response is 200
@@ -160,7 +157,7 @@ void execOTA() {
       if (written == contentLength) {
         Serial.println("Written : " + String(written) + " successfully");
       } else {
-        Serial.println("Written only : " + String(written) + "/" + String(contentLength) + ". Retry?" );
+        Serial.println("Written only : " + String(written) + "/" + String(contentLength) + ". Retry?");
         // retry??
         // execOTA();
       }
@@ -181,11 +178,11 @@ void execOTA() {
       // Understand the partitions and
       // space availability
       Serial.println("Not enough space to begin OTA");
-      client.flush();
+      client.clear();
     }
   } else {
     Serial.println("There was no content in the response");
-    client.flush();
+    client.clear();
   }
 }
 
@@ -201,7 +198,7 @@ void setup() {
 
   // Wait for connection to establish
   while (WiFi.status() != WL_CONNECTED) {
-    Serial.print("."); // Keep the serial monitor lit!
+    Serial.print(".");  // Keep the serial monitor lit!
     delay(500);
   }
 
@@ -219,12 +216,12 @@ void loop() {
 
 /*
  * Serial Monitor log for this sketch
- * 
+ *
  * If the OTA succeeded, it would load the preference sketch, with a small modification. i.e.
  * Print `OTA Update succeeded!! This is an example sketch : Preferences > StartCounter`
  * And then keeps on restarting every 10 seconds, updating the preferences
- * 
- * 
+ *
+ *
       rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
       configsip: 0, SPIWP:0x00
       clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
@@ -247,7 +244,7 @@ void loop() {
       OTA done!
       Update successfully completed. Rebooting.
       ets Jun  8 2016 00:22:57
-      
+
       rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
       configsip: 0, SPIWP:0x00
       clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
@@ -257,13 +254,13 @@ void loop() {
       load:0x40078000,len:10632
       load:0x40080000,len:252
       entry 0x40080034
-      
+
       OTA Update succeeded!! This is an example sketch : Preferences > StartCounter
       Current counter value: 1
       Restarting in 10 seconds...
       E (102534) wifi: esp_wifi_stop 802 wifi is not init
       ets Jun  8 2016 00:22:57
-      
+
       rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
       configsip: 0, SPIWP:0x00
       clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
@@ -273,11 +270,11 @@ void loop() {
       load:0x40078000,len:10632
       load:0x40080000,len:252
       entry 0x40080034
-      
+
       OTA Update succeeded!! This is an example sketch : Preferences > StartCounter
       Current counter value: 2
       Restarting in 10 seconds...
 
       ....
- * 
+ *
  */
diff --git a/libraries/Update/examples/AWS_S3_OTA_Update/StartCounter.ino.bin b/libraries/Update/examples/AWS_S3_OTA_Update/StartCounter.ino.bin
index 14732a0adb1..4892698815c 100644
Binary files a/libraries/Update/examples/AWS_S3_OTA_Update/StartCounter.ino.bin and b/libraries/Update/examples/AWS_S3_OTA_Update/StartCounter.ino.bin differ
diff --git a/libraries/Update/examples/AWS_S3_OTA_Update/ci.json b/libraries/Update/examples/AWS_S3_OTA_Update/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/Update/examples/AWS_S3_OTA_Update/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/Update/examples/HTTPS_OTA_Update/HTTPS_OTA_Update.ino b/libraries/Update/examples/HTTPS_OTA_Update/HTTPS_OTA_Update.ino
index 6e32ee5bd58..af30bf73e87 100644
--- a/libraries/Update/examples/HTTPS_OTA_Update/HTTPS_OTA_Update.ino
+++ b/libraries/Update/examples/HTTPS_OTA_Update/HTTPS_OTA_Update.ino
@@ -4,95 +4,82 @@
 // This sketch shows how to implement HTTPS firmware update Over The Air.
 // Please provide your WiFi credentials, https URL to the firmware image and the server certificate.
 
-static const char *ssid     = "your-ssid";  // your network SSID (name of wifi network)
-static const char *password = "your-password"; // your network password
+static const char *ssid = "your-ssid";          // your network SSID (name of wifi network)
+static const char *password = "your-password";  // your network password
 
-static const char *url = "https://example.com/firmware.bin"; //state url of your firmware image
+static const char *url = "https://example.com/firmware.bin";  //state url of your firmware image
 
-static const char *server_certificate = "-----BEGIN CERTIFICATE-----\n" \
-     "MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n" \
-     "MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n" \
-     "DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n" \
-     "SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n" \
-     "GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n" \
-     "AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n" \
-     "q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n" \
-     "SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n" \
-     "Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n" \
-     "a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n" \
-     "/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n" \
-     "AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n" \
-     "CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n" \
-     "bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n" \
-     "c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n" \
-     "VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n" \
-     "ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n" \
-     "MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n" \
-     "Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n" \
-     "AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n" \
-     "uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n" \
-     "wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n" \
-     "X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n" \
-     "PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n" \
-     "KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n" \
-     "-----END CERTIFICATE-----";
+static const char *server_certificate = "-----BEGIN CERTIFICATE-----\n"
+                                        "MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n"
+                                        "MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n"
+                                        "DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n"
+                                        "SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n"
+                                        "GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n"
+                                        "AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n"
+                                        "q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n"
+                                        "SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n"
+                                        "Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n"
+                                        "a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n"
+                                        "/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n"
+                                        "AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n"
+                                        "CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n"
+                                        "bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n"
+                                        "c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n"
+                                        "VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n"
+                                        "ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n"
+                                        "MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n"
+                                        "Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n"
+                                        "AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n"
+                                        "uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n"
+                                        "wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n"
+                                        "X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n"
+                                        "PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n"
+                                        "KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n"
+                                        "-----END CERTIFICATE-----";
 
 static HttpsOTAStatus_t otastatus;
 
-void HttpEvent(HttpEvent_t *event)
-{
-    switch(event->event_id) {
-        case HTTP_EVENT_ERROR:
-            Serial.println("Http Event Error");
-            break;
-        case HTTP_EVENT_ON_CONNECTED:
-            Serial.println("Http Event On Connected");
-            break;
-        case HTTP_EVENT_HEADER_SENT:
-            Serial.println("Http Event Header Sent");
-            break;
-        case HTTP_EVENT_ON_HEADER:
-            Serial.printf("Http Event On Header, key=%s, value=%s\n", event->header_key, event->header_value);
-            break;
-        case HTTP_EVENT_ON_DATA:
-            break;
-        case HTTP_EVENT_ON_FINISH:
-            Serial.println("Http Event On Finish");
-            break;
-        case HTTP_EVENT_DISCONNECTED:
-            Serial.println("Http Event Disconnected");
-            break;
-    }
+void HttpEvent(HttpEvent_t *event) {
+  switch (event->event_id) {
+    case HTTP_EVENT_ERROR:        Serial.println("Http Event Error"); break;
+    case HTTP_EVENT_ON_CONNECTED: Serial.println("Http Event On Connected"); break;
+    case HTTP_EVENT_HEADER_SENT:  Serial.println("Http Event Header Sent"); break;
+    case HTTP_EVENT_ON_HEADER:    Serial.printf("Http Event On Header, key=%s, value=%s\n", event->header_key, event->header_value); break;
+    case HTTP_EVENT_ON_DATA:      break;
+    case HTTP_EVENT_ON_FINISH:    Serial.println("Http Event On Finish"); break;
+    case HTTP_EVENT_DISCONNECTED: Serial.println("Http Event Disconnected"); break;
+    case HTTP_EVENT_REDIRECT:     Serial.println("Http Event Redirect"); break;
+  }
 }
 
-void setup(){
+void setup() {
 
-    Serial.begin(115200);
-    Serial.print("Attempting to connect to SSID: ");
-    WiFi.begin(ssid, password);
+  Serial.begin(115200);
+  Serial.print("Attempting to connect to SSID: ");
+  WiFi.begin(ssid, password);
 
-    // attempt to connect to Wifi network:
-    while (WiFi.status() != WL_CONNECTED) {
-        Serial.print(".");
-        delay(1000);
-    }
+  // attempt to connect to Wifi network:
+  while (WiFi.status() != WL_CONNECTED) {
+    Serial.print(".");
+    delay(1000);
+  }
+
+  Serial.print("Connected to ");
+  Serial.println(ssid);
 
-    Serial.print("Connected to ");
-    Serial.println(ssid);
-    
-    HttpsOTA.onHttpEvent(HttpEvent);
-    Serial.println("Starting OTA");
-    HttpsOTA.begin(url, server_certificate); 
+  HttpsOTA.onHttpEvent(HttpEvent);
+  Serial.println("Starting OTA");
+  HttpsOTA.begin(url, server_certificate);
 
-    Serial.println("Please Wait it takes some time ...");
+  Serial.println("Please Wait it takes some time ...");
 }
 
-void loop(){
-    otastatus = HttpsOTA.status();
-    if(otastatus == HTTPS_OTA_SUCCESS) { 
-        Serial.println("Firmware written successfully. To reboot device, call API ESP.restart() or PUSH restart button on device");
-    } else if(otastatus == HTTPS_OTA_FAIL) { 
-        Serial.println("Firmware Upgrade Fail");
-    }
-    delay(1000);
+void loop() {
+  otastatus = HttpsOTA.status();
+  if (otastatus == HTTPS_OTA_SUCCESS) {
+    Serial.println("Firmware written successfully. To reboot device, call API ESP.restart() or PUSH restart button on device");
+  } else if (otastatus == HTTPS_OTA_FAIL) {
+    Serial.println("Firmware Upgrade Fail");
+  }
+  delay(1000);
 }
diff --git a/libraries/Update/examples/HTTPS_OTA_Update/Readme.md b/libraries/Update/examples/HTTPS_OTA_Update/Readme.md
index 27fdb59612b..8a0a158a877 100644
--- a/libraries/Update/examples/HTTPS_OTA_Update/Readme.md
+++ b/libraries/Update/examples/HTTPS_OTA_Update/Readme.md
@@ -1,16 +1,16 @@
 # OTA Firmware Upgrade for Arduino
 This sketch allows Arduino user to perform Over The Air (OTA) firmware upgrade. It uses HTTPS.
- 
+
 # API introduced for OTA
 
-## HttpsOTA.begin(const char * url, const char * server_certificate, bool skip_cert_common_name_check) 
+## HttpsOTA.begin(const char * url, const char * server_certificate, bool skip_cert_common_name_check)
 
 Main API which starts firmware upgrade
 
 ### Parameters
 * url : URL for the uploaded firmware image
 * server_certificate : Provide the ota server certificate for authentication via HTTPS
-* skip_cert_common_name_check : Skip any validation of server certificate CN field 
+* skip_cert_common_name_check : Skip any validation of server certificate CN field
 
 The default value provided to skip_cert_common_name_check is true
 
@@ -19,14 +19,14 @@ The default value provided to skip_cert_common_name_check is true
 This API exposes HTTP Events to the user
 
 ### Parameter
-Function passed has following signature 
+Function passed has following signature
 void HttpEvent (HttpEvent_t * event);
 
 # HttpsOTA.otaStatus()
 
 It tracks the progress of OTA firmware upgrade.
 * HTTPS_OTA_IDLE : OTA upgrade have not started yet.
-* HTTPS_OTA_UPDATNG : OTA upgarde is in progress.
+* HTTPS_OTA_UPDATNG : OTA upgrade is in progress.
 * HTTPS_OTA_SUCCESS : OTA upgrade is successful.
 * HTTPS_OTA_FAIL : OTA upgrade failed.
-* HTTPS_OTA_ERR : Error occured while creating xEventGroup().
+* HTTPS_OTA_ERR : Error occurred while creating xEventGroup().
diff --git a/libraries/Update/examples/HTTPS_OTA_Update/ci.json b/libraries/Update/examples/HTTPS_OTA_Update/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/Update/examples/HTTPS_OTA_Update/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/Update/examples/HTTP_Client_AES_OTA_Update/HTTP_Client_AES_OTA_Update.ino b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/HTTP_Client_AES_OTA_Update.ino
new file mode 100644
index 00000000000..5c4c7ca00d0
--- /dev/null
+++ b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/HTTP_Client_AES_OTA_Update.ino
@@ -0,0 +1,330 @@
+/*
+An example of how to use HTTPClient to download an encrypted and plain image files OTA from a web server.
+This example uses Wifi & HTTPClient to connect to webserver and two functions for obtaining firmware image from webserver.
+One uses the example 'updater.php' code on server to check and/or send relevant download firmware image file,
+the other directly downloads the firmware file from web server.
+
+To use:-
+Make a folder/directory on your webserver where your firmware images will be uploaded to. ie. /firmware
+The 'updater.php' file can also be uploaded to the same folder. Edit and change definitions in 'update.php' to suit your needs.
+In sketch:
+   set HTTPUPDATE_HOST         to domain name or IP address if on LAN of your web server
+   set HTTPUPDATE_UPDATER_URI  to path and file to call 'updater.php'
+or set HTTPUPDATE_DIRECT_URI   to path and firmware file to download
+   edit other HTTPUPDATE_ as needed
+
+Encrypted image will help protect your app image file from being copied and used on blank devices, encrypt your image file by using espressif IDF.
+First install an app on device that has Update setup with the OTA decrypt mode on, same key, address and flash_crypt_conf as used in IDF to encrypt image file or vice versa.
+
+For easier development use the default U_AES_DECRYPT_AUTO decrypt mode. This mode allows both plain and encrypted app images to be uploaded.
+
+Note:- App image can also encrypted on device, by using espressif IDF to configure & enabled FLASH encryption, suggest the use of a different 'OTA_KEY' key for update from the eFuses 'flash_encryption' key used by device.
+
+  ie. "Update.setupCrypt(OTA_KEY, OTA_ADDRESS, OTA_CFG);"
+
+defaults:- {if not set ie. "Update.setupCrypt();" }
+  OTA_KEY     = 0  ( 0 = no key, disables decryption )
+  OTA_ADDRESS = 0  ( suggest dont set address to app0=0x10000 usually or app1=varies )
+  OTA_CFG     = 0xf
+  OTA_MODE    = U_AES_DECRYPT_AUTO
+
+OTA_MODE options:-
+  U_AES_DECRYPT_NONE       decryption disabled, loads OTA image files as sent(plain)
+  U_AES_DECRYPT_AUTO       auto loads both plain & encrypted OTA FLASH image files, and plain OTA SPIFFS image files
+  U_AES_DECRYPT_ON         decrypts OTA image files
+
+https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/
+
+Example:
+    espsecure.py encrypt_flash_data -k ota_key.bin --flash_crypt_conf 0xf -a 0x4320 -o output_filename.bin source_filename.bin
+
+espsecure.py encrypt_flash_data  = runs the idf encryption function to make a encrypted output file from a source file
+  -k text                        = path/filename to the AES 256bit(32byte) encryption key file
+  --flash_crypt_conf 0xn         = 0x0 to 0xf, the more bits set the higher the security of encryption(address salting, 0x0 would use ota_key with no address salting)
+  -a 0xnnnnnn00                  = 0x00 to 0x00fffff0 address offset(must be a multiple of 16, but better to use multiple of 32), used to offset the salting (has no effect when = --flash_crypt_conf 0x0)
+  -o text                        = path/filename to save encrypted output file to
+  text                           = path/filename to open source file from
+*/
+
+#include <Arduino.h>
+#include <WiFi.h>
+#include <NetworkClient.h>
+#include <HTTPClient.h>
+#include <Update.h>
+
+//==========================================================================
+//==========================================================================
+const char *WIFI_SSID = "wifi-ssid";
+const char *WIFI_PASSWORD = "wifi-password";
+
+const uint8_t OTA_KEY[32] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20,
+                             0x61, 0x20, 0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x74, 0x65, 0x73, 0x74, 0x20, 0x6b, 0x65, 0x79};
+
+/*
+const uint8_t  OTA_KEY[32] = {'0',  '1',  '2',  '3',  '4',  '5',  '6',  '7',
+                              '8',  '9',  ' ',  't',  'h',  'i',  's',  ' ',
+                              'a',  ' ',  's',  'i',  'm',  'p',  'l',  'e',
+                              't',  'e',  's',  't',  ' ',  'k',  'e',  'y' };
+*/
+
+//const uint8_t  OTA_KEY[33] = "0123456789 this a simpletest key";
+
+const uint32_t OTA_ADDRESS = 0x4320;
+const uint32_t OTA_CFG = 0x0f;
+const uint32_t OTA_MODE = U_AES_DECRYPT_AUTO;
+
+const char *HTTPUPDATE_USERAGRENT = "ESP32-Updater";
+//const char*    HTTPUPDATE_HOST         = "www.yourdomain.com";
+const char *HTTPUPDATE_HOST = "192.168.1.2";
+const uint16_t HTTPUPDATE_PORT = 80;
+const char *HTTPUPDATE_UPDATER_URI = "/firmware/updater.php";                          //uri to 'updater.php'
+const char *HTTPUPDATE_DIRECT_URI = "/firmware/HTTP_Client_AES_OTA_Update-v1.1.xbin";  //uri to image file
+
+const char *HTTPUPDATE_USER = NULL;  //use NULL if no authentication needed
+//const char*    HTTPUPDATE_USER       = "user";
+const char *HTTPUPDATE_PASSWORD = "password";
+
+const char *HTTPUPDATE_BRAND = "21";                         /* Brand ID */
+const char *HTTPUPDATE_MODEL = "HTTP_Client_AES_OTA_Update"; /* Project name */
+const char *HTTPUPDATE_FIRMWARE = "0.9";                     /* Firmware version */
+
+//==========================================================================
+//==========================================================================
+String urlEncode(const String &url, const char *safeChars = "-_.~") {
+  String encoded = "";
+  char temp[4];
+
+  for (int i = 0; i < url.length(); i++) {
+    temp[0] = url.charAt(i);
+    if (temp[0] == 32) {  //space
+      encoded.concat('+');
+    } else if ((temp[0] >= 48 && temp[0] <= 57)        /*0-9*/
+               || (temp[0] >= 65 && temp[0] <= 90)     /*A-Z*/
+               || (temp[0] >= 97 && temp[0] <= 122)    /*a-z*/
+               || (strchr(safeChars, temp[0]) != NULL) /* "=&-_.~" */
+    ) {
+      encoded.concat(temp[0]);
+    } else {  //character needs encoding
+      snprintf(temp, 4, "%%%02X", temp[0]);
+      encoded.concat(temp);
+    }
+  }
+  return encoded;
+}
+
+//==========================================================================
+bool addQuery(String *query, const String name, const String value) {
+  if (name.length() && value.length()) {
+    if (query->length() < 3) {
+      *query = "?";
+    } else {
+      query->concat('&');
+    }
+    query->concat(urlEncode(name));
+    query->concat('=');
+    query->concat(urlEncode(value));
+    return true;
+  }
+  return false;
+}
+
+//==========================================================================
+//==========================================================================
+void printProgress(size_t progress, const size_t &size) {
+  static int last_progress = -1;
+  if (size > 0) {
+    progress = (progress * 100) / size;
+    progress = (progress > 100 ? 100 : progress);  //0-100
+    if (progress != last_progress) {
+      Serial.printf("Progress: %d%%\n", progress);
+      last_progress = progress;
+    }
+  }
+}
+
+//==========================================================================
+bool http_downloadUpdate(HTTPClient &http, uint32_t size = 0) {
+  size = (size == 0 ? http.getSize() : size);
+  if (size == 0) {
+    return false;
+  }
+  NetworkClient *client = http.getStreamPtr();
+
+  if (!Update.begin(size, U_FLASH)) {
+    Serial.printf("Update.begin failed! (%s)\n", Update.errorString());
+    return false;
+  }
+
+  if (!Update.setupCrypt(OTA_KEY, OTA_ADDRESS, OTA_CFG, OTA_MODE)) {
+    Serial.println("Update.setupCrypt failed!");
+  }
+
+  if (Update.writeStream(*client) != size) {
+    Serial.printf("Update.writeStream failed! (%s)\n", Update.errorString());
+    return false;
+  }
+
+  if (!Update.end()) {
+    Serial.printf("Update.end failed! (%s)\n", Update.errorString());
+    return false;
+  }
+  return true;
+}
+
+//==========================================================================
+int http_sendRequest(HTTPClient &http) {
+
+  //set request Headers to be sent to server
+  http.useHTTP10(true);  // use HTTP/1.0 for update since the update handler not support any transfer Encoding
+  http.setTimeout(8000);
+  http.addHeader("Cache-Control", "no-cache");
+
+  //set own name for HTTPclient user-agent
+  http.setUserAgent(HTTPUPDATE_USERAGRENT);
+
+  int code = http.GET();  //send the GET request to HTTP server
+  int len = http.getSize();
+
+  if (code == HTTP_CODE_OK) {
+    return (len > 0 ? len : 0);  //return 0 or length of image to download
+  } else if (code < 0) {
+    Serial.printf("Error: %s\n", http.errorToString(code).c_str());
+    return code;  //error code should be minus between -1 to -11
+  } else {
+    Serial.printf("Error: HTTP Server response code %i\n", code);
+    return -code;  //return code should be minus between -100 to -511
+  }
+}
+
+//==========================================================================
+/* http_updater sends a GET request to 'update.php' on web server */
+bool http_updater(const String &host, const uint16_t &port, String uri, const bool &download, const char *user = NULL, const char *password = NULL) {
+  //add GET query params to be sent to server (are used by server 'updater.php' code to determine what action to take)
+  String query = "";
+  addQuery(&query, "cmd", (download ? "download" : "check"));  //action command
+
+  //setup HTTPclient to be ready to connect & send a request to HTTP server
+  HTTPClient http;
+  NetworkClient client;
+  uri.concat(query);  //GET query added to end of uri path
+  if (!http.begin(client, host, port, uri)) {
+    return false;  //httpclient setup error
+  }
+  Serial.printf("Sending HTTP request 'http://%s:%i%s'\n", host.c_str(), port, uri.c_str());
+
+  //set basic authorization, if needed for webpage access
+  if (user != NULL && password != NULL) {
+    http.setAuthorization(user, password);  //set basic Authorization to server, if needed be gain access
+  }
+
+  //add unique Headers to be sent to server used by server 'update.php' code to determine there a suitable firmware update image available
+  http.addHeader("Brand-Code", HTTPUPDATE_BRAND);
+  http.addHeader("Model", HTTPUPDATE_MODEL);
+  http.addHeader("Firmware", HTTPUPDATE_FIRMWARE);
+
+  //set headers to look for to get returned values in servers http response to our http request
+  const char *headerkeys[] = {"update", "version"};  //server returns update 0=no update found, 1=update found, version=version of update found
+  size_t headerkeyssize = sizeof(headerkeys) / sizeof(char *);
+  http.collectHeaders(headerkeys, headerkeyssize);
+
+  //connect & send HTTP request to server
+  int size = http_sendRequest(http);
+
+  //is there an image to download
+  if (size > 0 || (!download && size == 0)) {
+    if (!http.header("update") || http.header("update").toInt() == 0) {
+      Serial.println("No Firmware available");
+    } else if (!http.header("version") || http.header("version").toFloat() <= String(HTTPUPDATE_FIRMWARE).toFloat()) {
+      Serial.println("Firmware is upto Date");
+    } else {
+      //image avaliabe to download & update
+      if (!download) {
+        Serial.printf("Found V%s Firmware\n", http.header("version").c_str());
+      } else {
+        Serial.printf("Downloading & Installing V%s Firmware\n", http.header("version").c_str());
+      }
+      if (!download || http_downloadUpdate(http)) {
+        http.end();  //end connection
+        return true;
+      }
+    }
+  }
+
+  http.end();  //end connection
+  return false;
+}
+
+//==========================================================================
+/* this downloads Firmware image file directly from web server */
+bool http_direct(const String &host, const uint16_t &port, const String &uri, const char *user = NULL, const char *password = NULL) {
+  //setup HTTPclient to be ready to connect & send a request to HTTP server
+  HTTPClient http;
+  NetworkClient client;
+  if (!http.begin(client, host, port, uri)) {
+    return false;  //httpclient setup error
+  }
+  Serial.printf("Sending HTTP request 'http://%s:%i%s'\n", host.c_str(), port, uri.c_str());
+
+  //set basic authorization, if needed for webpage access
+  if (user != NULL && password != NULL) {
+    http.setAuthorization(user, password);  //set basic Authorization to server, if needed be gain access
+  }
+
+  //connect & send HTTP request to server
+  int size = http_sendRequest(http);
+
+  //is there an image to download
+  if (size > 0) {
+    if (http_downloadUpdate(http)) {
+      http.end();
+      return true;  //end connection
+    }
+  } else {
+    Serial.println("Image File not found");
+  }
+
+  http.end();  //end connection
+  return false;
+}
+
+//==========================================================================
+//==========================================================================
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println();
+  Serial.printf("Booting %s V%s\n", HTTPUPDATE_MODEL, HTTPUPDATE_FIRMWARE);
+
+  WiFi.mode(WIFI_AP_STA);
+  WiFi.begin(WIFI_SSID, WIFI_PASSWORD);
+  if (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("WiFi failed, retrying.");
+  }
+  int i = 0;
+  while (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.print(".");
+    if ((++i % 100) == 0) {
+      Serial.println();
+    }
+    delay(100);
+  }
+  Serial.printf("Connected to Wifi\nLocal IP: %s\n", WiFi.localIP().toString().c_str());
+
+  Update.onProgress(printProgress);
+
+  Serial.println("Checking with Server, if New Firmware available");
+  if (http_updater(HTTPUPDATE_HOST, HTTPUPDATE_PORT, HTTPUPDATE_UPDATER_URI, 0, HTTPUPDATE_USER, HTTPUPDATE_PASSWORD)) {    //check for new firmware
+    if (http_updater(HTTPUPDATE_HOST, HTTPUPDATE_PORT, HTTPUPDATE_UPDATER_URI, 1, HTTPUPDATE_USER, HTTPUPDATE_PASSWORD)) {  //update to new firmware
+      Serial.println("Firmware Update Successful, rebooting");
+      ESP.restart();
+    }
+  }
+
+  Serial.println("Checking Server for Firmware Image File to Download & Install");
+  if (http_direct(HTTPUPDATE_HOST, HTTPUPDATE_PORT, HTTPUPDATE_DIRECT_URI, HTTPUPDATE_USER, HTTPUPDATE_PASSWORD)) {
+    Serial.println("Firmware Update Successful, rebooting");
+    ESP.restart();
+  }
+}
+
+void loop() {}
diff --git a/libraries/Update/examples/HTTP_Client_AES_OTA_Update/ci.json b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/Update/examples/HTTP_Client_AES_OTA_Update/updater.php b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/updater.php
new file mode 100644
index 00000000000..056a741baa4
--- /dev/null
+++ b/libraries/Update/examples/HTTP_Client_AES_OTA_Update/updater.php
@@ -0,0 +1,64 @@
+<?php
+  /* Updater Server-side Example */
+  $brand_codes = array("20", "21");
+  $commands = array("check", "download");
+
+  function verify($valid){
+    if(!$valid){
+      http_response_code(404);
+      echo "Sorry, page not found";
+      die();
+    }
+  }
+
+  $headers = array();
+  foreach (getallheaders() as $name => $value) {
+    $headers += [$name => $value];
+  }
+  verify( in_array($headers['Brand-Code'], $brand_codes) );
+
+  $GetArgs = filter_input_array(INPUT_GET);
+  verify( in_array($GetArgs['cmd'], $commands) );
+
+  if($GetArgs['cmd'] == "check" || $GetArgs['cmd'] == "download"){
+/*********************************************************************************/
+/* $firmware version & filename definitions for different Brands, Models & Firmware versions */
+    if($headers['Brand-Code'] == "21"){
+      if($headers['Model'] == "HTTP_Client_AES_OTA_Update"){
+
+        if($headers['Firmware'] < "0.9"){//ie. update to latest of this major version
+          $firmware = array('version'=>"0.9", 'filename'=>"HTTP_Client_AES_OTA_Update-v0.9.xbin");
+        }
+        elseif($headers['Firmware'] == "0.9"){//ie. update between major versions
+          $firmware = array('version'=>"1.0", 'filename'=>"HTTP_Client_AES_OTA_Update-v1.0.xbin");
+        }
+        elseif($headers['Firmware'] <= "1.4"){//ie. update to latest version
+          $firmware = array('version'=>"1.4", 'filename'=>"HTTP_Client_AES_OTA_Update-v1.4.xbin");
+        }
+
+      }
+    }
+/*  end of $firmware definitions for firmware update images on server                */
+/*********************************************************************************/
+
+    if( !$firmware['filename'] || !file_exists($firmware['filename']) ){
+      header('update: 0' );//no update available
+      exit;
+    }else{
+      header('update: 1' );//update available
+      header('version: ' . $firmware['version'] );
+      if($GetArgs['cmd'] == "download"){
+//Get file type and set it as Content Type
+        $finfo = finfo_open(FILEINFO_MIME_TYPE);
+        header('Content-Type: ' . finfo_file($finfo, $firmware['filename']));//application/octet-stream for binary file
+        finfo_close($finfo);
+//Define file size
+        header('Content-Length: ' . filesize($firmware['filename']));
+        readfile($firmware['filename']); //send file
+      }
+      exit;
+    }
+  }
+
+  verify(false);
+?>
diff --git a/libraries/Update/examples/HTTP_Server_AES_OTA_Update/HTTP_Server_AES_OTA_Update.ino b/libraries/Update/examples/HTTP_Server_AES_OTA_Update/HTTP_Server_AES_OTA_Update.ino
new file mode 100644
index 00000000000..5af4f1bf9f4
--- /dev/null
+++ b/libraries/Update/examples/HTTP_Server_AES_OTA_Update/HTTP_Server_AES_OTA_Update.ino
@@ -0,0 +1,237 @@
+/*
+An example of how to use Update to upload encrypted and plain image files OTA. This example uses a simple webserver & Wifi connection via AP or STA with mDNS and DNS for simple host URI.
+
+Encrypted image will help protect your app image file from being copied and used on blank devices, encrypt your image file by using espressif IDF.
+First install an app on device that has Update setup with the OTA decrypt mode on, same key, address and flash_crypt_conf as used in IDF to encrypt image file or vice versa.
+
+For easier development use the default U_AES_DECRYPT_AUTO decrypt mode. This mode allows both plain and encrypted app images to be uploaded.
+
+Note:- App image can also encrypted on device, by using espressif IDF to configure & enabled FLASH encryption, suggest the use of a different 'OTA_KEY' key for update from the eFuses 'flash_encryption' key used by device.
+
+  ie. "Update.setupCrypt(OTA_KEY, OTA_ADDRESS, OTA_CFG);"
+
+defaults:- {if not set ie. "Update.setupCrypt();" }
+  OTA_KEY     = 0  ( 0 = no key, disables decryption )
+  OTA_ADDRESS = 0  ( suggest dont set address to app0=0x10000 usually or app1=varies )
+  OTA_CFG     = 0xf
+  OTA_MODE    = U_AES_DECRYPT_AUTO
+
+OTA_MODE options:-
+  U_AES_DECRYPT_NONE       decryption disabled, loads OTA image files as sent(plain)
+  U_AES_DECRYPT_AUTO       auto loads both plain & encrypted OTA FLASH image files, and plain OTA SPIFFS image files
+  U_AES_DECRYPT_ON         decrypts OTA image files
+
+https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/
+
+Example:
+    espsecure.py encrypt_flash_data -k ota_key.bin --flash_crypt_conf 0xf -a 0x4320 -o output_filename.bin source_filename.bin
+
+espsecure.py encrypt_flash_data  = runs the idf encryption function to make a encrypted output file from a source file
+  -k text                        = path/filename to the AES 256bit(32byte) encryption key file
+  --flash_crypt_conf 0xn         = 0x0 to 0xf, the more bits set the higher the security of encryption(address salting, 0x0 would use ota_key with no address salting)
+  -a 0xnnnnnn00                  = 0x00 to 0x00fffff0 address offset(must be a multiple of 16, but better to use multiple of 32), used to offset the salting (has no effect when = --flash_crypt_conf 0x0)
+  -o text                        = path/filename to save encrypted output file to
+  text                           = path/filename to open source file from
+*/
+
+#include <WiFi.h>
+#include <NetworkClient.h>
+#include <SPIFFS.h>
+#include <Update.h>
+#include <WebServer.h>
+#include <ESPmDNS.h>
+
+WebServer httpServer(80);
+
+//with WIFI_MODE_AP defined the ESP32 is a wifi AP, with it undefined ESP32 tries to connect to wifi STA
+#define WIFI_MODE_AP
+
+#ifdef WIFI_MODE_AP
+#include <DNSServer.h>
+DNSServer dnsServer;
+#endif
+
+const char *host = "esp32-web";
+const char *ssid = "wifi-ssid";
+const char *password = "wifi-password";
+
+const uint8_t OTA_KEY[32] = {0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x20, 0x74, 0x68, 0x69, 0x73, 0x20,
+                             0x61, 0x20, 0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x74, 0x65, 0x73, 0x74, 0x20, 0x6b, 0x65, 0x79};
+
+/*
+const uint8_t OTA_KEY[32] = {'0',  '1',  '2',  '3',  '4',  '5',  '6',  '7',
+                             '8',  '9',  ' ',  't',  'h',  'i',  's',  ' ',
+                             'a',  ' ',  's',  'i',  'm',  'p',  'l',  'e',
+                             't',  'e',  's',  't',  ' ',  'k',  'e',  'y' };
+*/
+
+//const uint8_t   OTA_KEY[33] = "0123456789 this a simpletest key";
+
+const uint32_t OTA_ADDRESS = 0x4320;  //OTA_ADDRESS value has no effect when OTA_CFG = 0x00
+const uint32_t OTA_CFG = 0x0f;
+const uint32_t OTA_MODE = U_AES_DECRYPT_AUTO;
+
+/*=================================================================*/
+const char *update_path = "update";
+
+static const char UpdatePage_HTML[] PROGMEM =
+  R"(<!DOCTYPE html>
+     <html lang='en'>
+     <head>
+         <title>Image Upload</title>
+         <meta charset='utf-8'>
+         <meta name='viewport' content='width=device-width,initial-scale=1'/>
+     </head>
+     <body style='background-color:black;color:#ffff66;text-align: center;font-size:20px;'>
+     <form method='POST' action='' enctype='multipart/form-data'>
+         Firmware:<br><br>
+         <input type='file' accept='.bin,.bin.gz' name='firmware' style='font-size:20px;'><br><br>
+         <input type='submit' value='Update' style='font-size:25px; height:50px; width:100px'>
+     </form>
+     <br><br><br>
+     <form method='POST' action='' enctype='multipart/form-data'>
+         FileSystem:<br><br>
+         <input type='file' accept='.bin,.bin.gz,.image' name='filesystem' style='font-size:20px;'><br><br>
+         <input type='submit' value='Update' style='font-size:25px; height:50px; width:100px'>
+     </form>
+     </body>
+     </html>)";
+
+/*=================================================================*/
+
+void printProgress(size_t progress, size_t size) {
+  static int last_progress = -1;
+  if (size > 0) {
+    progress = (progress * 100) / size;
+    progress = (progress > 100 ? 100 : progress);  //0-100
+    if (progress != last_progress) {
+      Serial.printf("\nProgress: %d%%", progress);
+      last_progress = progress;
+    }
+  }
+}
+
+void setupHttpUpdateServer() {
+  //redirecting not found web pages back to update page
+  httpServer.onNotFound([&]() {  //webpage not found
+    httpServer.sendHeader("Location", String("../") + String(update_path));
+    httpServer.send(302, F("text/html"), "");
+  });
+
+  // handler for the update web page
+  httpServer.on(String("/") + String(update_path), HTTP_GET, [&]() {
+    httpServer.send_P(200, PSTR("text/html"), UpdatePage_HTML);
+  });
+
+  // handler for the update page form POST
+  httpServer.on(
+    String("/") + String(update_path), HTTP_POST,
+    [&]() {
+      // handler when file upload finishes
+      if (Update.hasError()) {
+        httpServer.send(200, F("text/html"), String(F("<META http-equiv=\"refresh\" content=\"5;URL=/\">Update error: ")) + String(Update.errorString()));
+      } else {
+        httpServer.client().setNoDelay(true);
+        httpServer.send(200, PSTR("text/html"), String(F("<META http-equiv=\"refresh\" content=\"15;URL=/\">Update Success! Rebooting...")));
+        delay(100);
+        httpServer.client().stop();
+        ESP.restart();
+      }
+    },
+    [&]() {
+      // handler for the file upload, gets the sketch bytes, and writes
+      // them through the Update object
+      HTTPUpload &upload = httpServer.upload();
+      if (upload.status == UPLOAD_FILE_START) {
+        Serial.printf("Update: %s\n", upload.filename.c_str());
+        if (upload.name == "filesystem") {
+          if (!Update.begin(SPIFFS.totalBytes(), U_SPIFFS)) {  //start with max available size
+            Update.printError(Serial);
+          }
+        } else {
+          uint32_t maxSketchSpace = (ESP.getFreeSketchSpace() - 0x1000) & 0xFFFFF000;
+          if (!Update.begin(maxSketchSpace, U_FLASH)) {  //start with max available size
+            Update.printError(Serial);
+          }
+        }
+      } else if (upload.status == UPLOAD_FILE_ABORTED || Update.hasError()) {
+        if (upload.status == UPLOAD_FILE_ABORTED) {
+          if (!Update.end(false)) {
+            Update.printError(Serial);
+          }
+          Serial.println("Update was aborted");
+        }
+      } else if (upload.status == UPLOAD_FILE_WRITE) {
+        Serial.printf(".");
+        if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) {
+          Update.printError(Serial);
+        }
+      } else if (upload.status == UPLOAD_FILE_END) {
+        if (Update.end(true)) {  //true to set the size to the current progress
+          Serial.printf("Update Success: %u\nRebooting...\n", upload.totalSize);
+        } else {
+          Update.printError(Serial);
+        }
+      }
+      delay(0);
+    }
+  );
+
+  Update.onProgress(printProgress);
+}
+
+/*=================================================================*/
+
+void setup(void) {
+  Serial.begin(115200);
+  Serial.println();
+  Serial.println("Booting Sketch...");
+  WiFi.mode(WIFI_AP_STA);
+#ifdef WIFI_MODE_AP
+  WiFi.softAP(ssid, password);
+  dnsServer.setErrorReplyCode(DNSReplyCode::NoError);
+  dnsServer.start(53, "*", WiFi.softAPIP());  //if DNS started with "*" for domain name, it will reply with provided IP to all DNS request
+  Serial.printf("Wifi AP started, IP address: %s\n", WiFi.softAPIP().toString().c_str());
+  Serial.printf("You can connect to ESP32 AP use:-\n    ssid: %s\npassword: %s\n\n", ssid, password);
+#else
+  WiFi.begin(ssid, password);
+  if (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("WiFi failed, retrying.");
+  }
+  int i = 0;
+  while (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.print(".");
+    if ((++i % 100) == 0) {
+      Serial.println();
+    }
+    delay(100);
+  }
+  Serial.printf("Connected to Wifi\nLocal IP: %s\n", WiFi.localIP().toString().c_str());
+#endif
+
+  if (MDNS.begin(host)) {
+    Serial.println("mDNS responder started");
+  }
+
+  setupHttpUpdateServer();
+
+  if (Update.setupCrypt(OTA_KEY, OTA_ADDRESS, OTA_CFG, OTA_MODE)) {
+    Serial.println("Upload Decryption Ready");
+  }
+
+  httpServer.begin();
+
+  MDNS.addService("http", "tcp", 80);
+#ifdef WIFI_MODE_AP
+  Serial.printf("HTTPUpdateServer ready with Captive DNS!\nOpen http://anyname.xyz/%s in your browser\n", update_path);
+#else
+  Serial.printf("HTTPUpdateServer ready!\nOpen http://%s.local/%s in your browser\n", host, update_path);
+#endif
+}
+
+void loop(void) {
+  httpServer.handleClient();
+#ifdef WIFI_MODE_AP
+  dnsServer.processNextRequest();  //DNS captive portal for easy access to this device webserver
+#endif
+}
diff --git a/libraries/Update/examples/HTTP_Server_AES_OTA_Update/ci.json b/libraries/Update/examples/HTTP_Server_AES_OTA_Update/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/Update/examples/HTTP_Server_AES_OTA_Update/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/Update/examples/OTAWebUpdater/OTAWebUpdater.ino b/libraries/Update/examples/OTAWebUpdater/OTAWebUpdater.ino
new file mode 100644
index 00000000000..7059bef4496
--- /dev/null
+++ b/libraries/Update/examples/OTAWebUpdater/OTAWebUpdater.ino
@@ -0,0 +1,117 @@
+#include <WiFi.h>
+#include <WebServer.h>
+#include <ESPmDNS.h>
+#include <Update.h>
+#include <Ticker.h>
+#include "html.h"
+
+#define SSID_FORMAT "ESP32-%06lX"  // 12 chars total
+//#define PASSWORD "test123456"    // generate if remarked
+
+WebServer server(80);
+Ticker tkSecond;
+uint8_t otaDone = 0;
+
+const char *alphanum = "0123456789!@#$%^&*abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ";
+String generatePass(uint8_t str_len) {
+  String buff;
+  for (int i = 0; i < str_len; i++) {
+    buff += alphanum[random(strlen(alphanum) - 1)];
+  }
+  return buff;
+}
+
+void apMode() {
+  char ssid[13];
+  char passwd[11];
+  long unsigned int espmac = ESP.getEfuseMac() >> 24;
+  snprintf(ssid, 13, SSID_FORMAT, espmac);
+#ifdef PASSWORD
+  snprintf(passwd, 11, PASSWORD);
+#else
+  snprintf(passwd, 11, generatePass(10).c_str());
+#endif
+  WiFi.mode(WIFI_AP);
+  WiFi.softAP(ssid, passwd);  // Set up the SoftAP
+  MDNS.begin("esp32");
+  Serial.printf("AP: %s, PASS: %s\n", ssid, passwd);
+}
+
+void handleUpdateEnd() {
+  server.sendHeader("Connection", "close");
+  if (Update.hasError()) {
+    server.send(502, "text/plain", Update.errorString());
+  } else {
+    server.sendHeader("Refresh", "10");
+    server.sendHeader("Location", "/");
+    server.send(307);
+    ESP.restart();
+  }
+}
+
+void handleUpdate() {
+  size_t fsize = UPDATE_SIZE_UNKNOWN;
+  if (server.hasArg("size")) {
+    fsize = server.arg("size").toInt();
+  }
+  HTTPUpload &upload = server.upload();
+  if (upload.status == UPLOAD_FILE_START) {
+    Serial.printf("Receiving Update: %s, Size: %d\n", upload.filename.c_str(), fsize);
+    if (!Update.begin(fsize)) {
+      otaDone = 0;
+      Update.printError(Serial);
+    }
+  } else if (upload.status == UPLOAD_FILE_WRITE) {
+    if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) {
+      Update.printError(Serial);
+    } else {
+      otaDone = 100 * Update.progress() / Update.size();
+    }
+  } else if (upload.status == UPLOAD_FILE_END) {
+    if (Update.end(true)) {
+      Serial.printf("Update Success: %u bytes\nRebooting...\n", upload.totalSize);
+    } else {
+      Serial.printf("%s\n", Update.errorString());
+      otaDone = 0;
+    }
+  }
+}
+
+void webServerInit() {
+  server.on(
+    "/update", HTTP_POST,
+    []() {
+      handleUpdateEnd();
+    },
+    []() {
+      handleUpdate();
+    }
+  );
+  server.on("/favicon.ico", HTTP_GET, []() {
+    server.sendHeader("Content-Encoding", "gzip");
+    server.send_P(200, "image/x-icon", favicon_ico_gz, favicon_ico_gz_len);
+  });
+  server.onNotFound([]() {
+    server.send(200, "text/html", indexHtml);
+  });
+  server.begin();
+  Serial.printf("Web Server ready at http://esp32.local or http://%s\n", WiFi.softAPIP().toString().c_str());
+}
+
+void everySecond() {
+  if (otaDone > 1) {
+    Serial.printf("ota: %d%%\n", otaDone);
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  apMode();
+  webServerInit();
+  tkSecond.attach(1, everySecond);
+}
+
+void loop() {
+  delay(150);
+  server.handleClient();
+}
diff --git a/libraries/Update/examples/OTAWebUpdater/ci.json b/libraries/Update/examples/OTAWebUpdater/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/Update/examples/OTAWebUpdater/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/Update/examples/OTAWebUpdater/html.h b/libraries/Update/examples/OTAWebUpdater/html.h
new file mode 100644
index 00000000000..b4c488b003d
--- /dev/null
+++ b/libraries/Update/examples/OTAWebUpdater/html.h
@@ -0,0 +1,73 @@
+// Literal string
+const char *indexHtml = R"literal(
+  <!DOCTYPE html>
+  <link rel='icon' href='/favicon.ico' sizes='any'>
+  <body style='width:480px'>
+    <h2>ESP Firmware Update</h2>
+    <form method='POST' enctype='multipart/form-data' id='upload-form'>
+      <input type='file' id='file' name='update'>
+      <input type='submit' value='Update'>
+    </form>
+    <br>
+    <div id='prg' style='width:0;color:white;text-align:center'>0%</div>
+  </body>
+  <script>
+    var prg = document.getElementById('prg');
+    var form = document.getElementById('upload-form');
+    form.addEventListener('submit', el=>{
+      prg.style.backgroundColor = 'blue';
+      el.preventDefault();
+      var data = new FormData(form);
+      var req = new XMLHttpRequest();
+      var fsize = document.getElementById('file').files[0].size;
+      req.open('POST', '/update?size=' + fsize);
+      req.upload.addEventListener('progress', p=>{
+        let w = Math.round(p.loaded/p.total*100) + '%';
+          if(p.lengthComputable){
+             prg.innerHTML = w;
+             prg.style.width = w;
+          }
+          if(w == '100%') prg.style.backgroundColor = 'black';
+      });
+      req.send(data);
+     });
+  </script>
+)literal";
+
+// Compressed gzip in C include file style
+// listing was created using `xxd -i favicon.ico.gz`
+const char favicon_ico_gz[] = {
+  0x1f, 0x8b, 0x08, 0x08, 0x13, 0xb6, 0xa5, 0x62, 0x00, 0x03, 0x66, 0x61, 0x76, 0x69, 0x63, 0x6f, 0x6e, 0x2e, 0x69, 0x63, 0x6f, 0x00, 0xa5, 0x53, 0x69, 0x48,
+  0x54, 0x51, 0x14, 0x7e, 0x41, 0x99, 0x4b, 0xa0, 0x15, 0x24, 0xb4, 0x99, 0x8e, 0x1b, 0x25, 0xa8, 0x54, 0xb4, 0x19, 0x56, 0x62, 0x41, 0xab, 0x14, 0x45, 0x61,
+  0x51, 0x62, 0x86, 0x69, 0x1a, 0xd4, 0x60, 0xda, 0xa2, 0x99, 0x4b, 0x69, 0x1b, 0x42, 0x26, 0x5a, 0x09, 0x59, 0xd8, 0xfe, 0xab, 0x88, 0xa0, 0x82, 0xe8, 0x4f,
+  0x90, 0xa5, 0x14, 0x68, 0x0b, 0xe6, 0x2c, 0x6f, 0x9c, 0xed, 0xcd, 0x9b, 0xcd, 0x19, 0x9d, 0x99, 0x3b, 0xe3, 0xd7, 0x79, 0x6f, 0x34, 0xac, 0xe8, 0x57, 0xf7,
+  0x72, 0x1e, 0x87, 0xb3, 0xbe, 0xf3, 0x9d, 0xef, 0x72, 0xdc, 0x24, 0xba, 0x51, 0x51, 0x1c, 0x7d, 0x17, 0x70, 0x85, 0x93, 0x39, 0x6e, 0x16, 0xc7, 0x71, 0xc9,
+  0x24, 0x64, 0x22, 0x4b, 0xd0, 0x2e, 0x1f, 0xf2, 0xcd, 0x8c, 0x08, 0xca, 0xf8, 0x89, 0x48, 0x54, 0x7b, 0x49, 0xd8, 0xb8, 0x84, 0xc6, 0xab, 0xd9, 0xd4, 0x58,
+  0x15, 0x8b, 0x4e, 0xd1, 0xb0, 0xa4, 0x0c, 0x9e, 0x2d, 0x5a, 0xa3, 0x63, 0x31, 0x4b, 0xb4, 0x6c, 0x9a, 0x22, 0x68, 0x0f, 0x9f, 0x10, 0x3b, 0x21, 0x17, 0x92,
+  0x84, 0xc5, 0xa9, 0x90, 0xbc, 0x8a, 0x47, 0xe1, 0x31, 0x01, 0x95, 0xf5, 0x22, 0x6a, 0x1a, 0xac, 0x28, 0x3f, 0x2b, 0xa2, 0x8a, 0x74, 0xe5, 0x19, 0x0b, 0xb2,
+  0xb7, 0xeb, 0x11, 0x49, 0x71, 0xe1, 0x09, 0xc1, 0xf8, 0x09, 0x75, 0x10, 0xae, 0x50, 0x61, 0xf3, 0x6e, 0x03, 0x2a, 0xeb, 0x44, 0xe4, 0xec, 0x31, 0xa0, 0xf9,
+  0x86, 0x1d, 0xb7, 0x3b, 0x9d, 0x58, 0x9e, 0xa5, 0xc3, 0xb5, 0x1b, 0x0e, 0xd4, 0x5f, 0xb4, 0xe2, 0xa8, 0x52, 0xc0, 0xf1, 0x53, 0x16, 0xcc, 0x49, 0xd3, 0x8c,
+  0xd7, 0x90, 0xf3, 0xa5, 0xbe, 0xdb, 0x72, 0x0d, 0x78, 0xff, 0x71, 0x04, 0x77, 0x1f, 0x3a, 0x91, 0x9e, 0xc9, 0xe3, 0xed, 0xbb, 0x61, 0xb8, 0x87, 0x03, 0x28,
+  0x56, 0x9a, 0xc1, 0x0f, 0x32, 0xf4, 0x7d, 0xf5, 0x42, 0x91, 0xaa, 0xc1, 0xba, 0x6d, 0x7a, 0xc4, 0xaf, 0xe0, 0x11, 0x16, 0x1f, 0xcc, 0x0f, 0xa5, 0xb9, 0x16,
+  0xae, 0xe6, 0x51, 0x7b, 0xc9, 0x8a, 0x17, 0xaf, 0xdd, 0x18, 0xf1, 0x04, 0xb0, 0x65, 0x97, 0x01, 0x1d, 0xf7, 0x9c, 0xf0, 0xfb, 0x03, 0x28, 0x2a, 0x13, 0xd0,
+  0xfb, 0xcd, 0x8b, 0xfe, 0x1f, 0x5e, 0x1c, 0x38, 0x6c, 0xc2, 0xe3, 0xa7, 0x2e, 0x2c, 0xcd, 0x1e, 0x44, 0x98, 0x62, 0x2c, 0x9f, 0x30, 0x39, 0x52, 0x6e, 0x41,
+  0xe6, 0x56, 0x3d, 0x16, 0x65, 0xf0, 0xd8, 0xb9, 0xd7, 0x88, 0x0d, 0x39, 0x7a, 0x0c, 0xa8, 0x7d, 0x30, 0x99, 0x19, 0x0e, 0x95, 0x9a, 0x60, 0xb6, 0x30, 0x74,
+  0xf5, 0x8c, 0xa0, 0xbc, 0x52, 0xc0, 0x28, 0xdd, 0xcb, 0xd7, 0xed, 0x20, 0x2c, 0xe5, 0xfc, 0xd9, 0xa9, 0x1a, 0x56, 0xdd, 0x68, 0x45, 0x5c, 0xba, 0x16, 0xf9,
+  0xa5, 0x66, 0xb4, 0xdd, 0x72, 0xa0, 0x7f, 0xc0, 0x0b, 0x50, 0x5c, 0x6b, 0xbb, 0x1d, 0xf5, 0x97, 0xad, 0xb2, 0x7e, 0xb3, 0xc3, 0x81, 0x96, 0x5b, 0x76, 0x59,
+  0x3f, 0x5e, 0x69, 0xc1, 0xe4, 0x98, 0x60, 0x7e, 0x0a, 0xed, 0xe7, 0xd4, 0x39, 0x11, 0xe7, 0x29, 0x8e, 0xb1, 0x00, 0x46, 0x47, 0x47, 0x21, 0x50, 0xbf, 0x36,
+  0xca, 0x2d, 0x2c, 0x31, 0x41, 0x6f, 0x64, 0xb0, 0x88, 0x0c, 0x05, 0xa4, 0x7f, 0xa1, 0x39, 0x2c, 0x56, 0x3f, 0x76, 0xec, 0x37, 0x22, 0x76, 0x99, 0x56, 0xc2,
+  0x80, 0xa5, 0xad, 0xd5, 0xb1, 0x33, 0x84, 0x79, 0x17, 0x61, 0xe7, 0x72, 0xfb, 0x71, 0xe1, 0x8a, 0x0d, 0x07, 0x8b, 0x4d, 0xa8, 0x6d, 0x14, 0xa1, 0x1b, 0xf4,
+  0xc1, 0x47, 0x35, 0xa5, 0xda, 0x4d, 0x2d, 0x36, 0xb9, 0xf7, 0xfd, 0x27, 0x4e, 0xd4, 0xd2, 0x2e, 0xf6, 0x15, 0x99, 0x11, 0x12, 0xa3, 0x62, 0x8a, 0xe5, 0x3c,
+  0xab, 0x23, 0xff, 0xb3, 0x17, 0x2e, 0xb9, 0xf7, 0xf7, 0x7e, 0x2f, 0x0c, 0x26, 0x26, 0xeb, 0x16, 0x91, 0xea, 0x91, 0xaf, 0x82, 0x76, 0xef, 0x1c, 0xf2, 0x43,
+  0xab, 0xf3, 0xc9, 0xb5, 0xbb, 0xba, 0x3d, 0x58, 0x4f, 0x18, 0x87, 0xc4, 0xaa, 0x59, 0x64, 0x82, 0x9a, 0x9d, 0xac, 0x15, 0x91, 0x9b, 0x6f, 0xc4, 0xab, 0x37,
+  0xc3, 0x50, 0x6b, 0x7c, 0xe8, 0xfe, 0x34, 0x82, 0xf6, 0x3b, 0x0e, 0x14, 0x50, 0xec, 0xd5, 0x6b, 0x36, 0x38, 0x9c, 0x7e, 0xd8, 0x1c, 0x7e, 0x28, 0x4f, 0x0a,
+  0xe8, 0x7c, 0xe4, 0xc4, 0xc7, 0x4f, 0x1e, 0xcc, 0x25, 0x0e, 0x84, 0x25, 0x04, 0x39, 0xb9, 0x25, 0xd7, 0x88, 0xfc, 0x12, 0x33, 0xa2, 0x93, 0xd5, 0xc8, 0x2b,
+  0x32, 0xe1, 0xc4, 0x69, 0x01, 0xcd, 0xad, 0x76, 0xf4, 0xf6, 0x79, 0xe4, 0xff, 0xe0, 0xa9, 0xaf, 0xb2, 0x42, 0x40, 0x53, 0xb3, 0x0d, 0x43, 0x2e, 0xe2, 0x04,
+  0xed, 0x34, 0x74, 0x0c, 0x7f, 0xe2, 0x11, 0x9b, 0x4e, 0x79, 0xe5, 0xd5, 0x22, 0xb2, 0x88, 0x1b, 0xcf, 0x5f, 0xba, 0xe5, 0x39, 0x25, 0x11, 0x09, 0xab, 0x07,
+  0x34, 0xef, 0x41, 0xda, 0xfb, 0x3d, 0xea, 0xeb, 0x72, 0x07, 0x70, 0xf5, 0xba, 0x0d, 0x33, 0x92, 0xd5, 0xbf, 0xf3, 0x8f, 0xb8, 0x34, 0x7f, 0xb1, 0x16, 0x89,
+  0x2b, 0x79, 0x64, 0x6c, 0x1a, 0x44, 0x53, 0x9b, 0x1d, 0x65, 0x55, 0x22, 0x76, 0x12, 0xce, 0x35, 0x0d, 0x22, 0x3e, 0xf4, 0x78, 0xd0, 0xfd, 0xd9, 0x43, 0x5c,
+  0x14, 0x30, 0x23, 0xe9, 0x1f, 0xfc, 0x27, 0x9b, 0x54, 0x87, 0xf8, 0x28, 0xff, 0xdb, 0x94, 0xf9, 0x2a, 0x24, 0x10, 0x4f, 0xf3, 0x68, 0xae, 0x8d, 0xf4, 0x1e,
+  0xe6, 0x11, 0x3f, 0x24, 0x7b, 0x78, 0xe2, 0xaf, 0x5c, 0xfc, 0xf1, 0x06, 0xff, 0x12, 0x69, 0xbf, 0x53, 0x68, 0x47, 0x21, 0x84, 0x91, 0xa4, 0x4f, 0xf4, 0x8d,
+  0xbd, 0x63, 0x2f, 0xf7, 0x9f, 0xe7, 0x27, 0x40, 0xbb, 0x5a, 0x53, 0x7e, 0x04, 0x00, 0x00
+};
+const int favicon_ico_gz_len = 821;
diff --git a/libraries/Update/examples/SD_Update/SD_Update.ino b/libraries/Update/examples/SD_Update/SD_Update.ino
index 9f3f494aba8..8b2451ae88c 100644
--- a/libraries/Update/examples/SD_Update/SD_Update.ino
+++ b/libraries/Update/examples/SD_Update/SD_Update.ino
@@ -1,4 +1,4 @@
-/* 
+/*
  Name:      SD_Update.ino
  Created:   12.09.2017 15:07:17
  Author:    Frederik Merz <frederik.merz@novalight.de>
@@ -9,104 +9,95 @@
    2. Copy update.bin to a SD-Card, you can basically
       compile this or any other example
       then copy and rename the app binary to the sd card root
-   3. Connect SD-Card as shown in SD_MMC example, 
+   3. Connect SD-Card as shown in SD example,
       this can also be adapted for SPI
-   3. After successfull update and reboot, ESP32 shall start the new app
+   3. After successful update and reboot, ESP32 shall start the new app
 */
 
 #include <Update.h>
 #include <FS.h>
-#include <SD_MMC.h>
+#include <SD.h>
 
 // perform the actual update from a given stream
 void performUpdate(Stream &updateSource, size_t updateSize) {
-   if (Update.begin(updateSize)) {      
-      size_t written = Update.writeStream(updateSource);
-      if (written == updateSize) {
-         Serial.println("Written : " + String(written) + " successfully");
-      }
-      else {
-         Serial.println("Written only : " + String(written) + "/" + String(updateSize) + ". Retry?");
-      }
-      if (Update.end()) {
-         Serial.println("OTA done!");
-         if (Update.isFinished()) {
-            Serial.println("Update successfully completed. Rebooting.");
-         }
-         else {
-            Serial.println("Update not finished? Something went wrong!");
-         }
-      }
-      else {
-         Serial.println("Error Occurred. Error #: " + String(Update.getError()));
+  if (Update.begin(updateSize)) {
+    size_t written = Update.writeStream(updateSource);
+    if (written == updateSize) {
+      Serial.println("Written : " + String(written) + " successfully");
+    } else {
+      Serial.println("Written only : " + String(written) + "/" + String(updateSize) + ". Retry?");
+    }
+    if (Update.end()) {
+      Serial.println("OTA done!");
+      if (Update.isFinished()) {
+        Serial.println("Update successfully completed. Rebooting.");
+      } else {
+        Serial.println("Update not finished? Something went wrong!");
       }
+    } else {
+      Serial.println("Error Occurred. Error #: " + String(Update.getError()));
+    }
 
-   }
-   else
-   {
-      Serial.println("Not enough space to begin OTA");
-   }
+  } else {
+    Serial.println("Not enough space to begin OTA");
+  }
 }
 
 // check given FS for valid update.bin and perform update if available
 void updateFromFS(fs::FS &fs) {
-   File updateBin = fs.open("/update.bin");
-   if (updateBin) {
-      if(updateBin.isDirectory()){
-         Serial.println("Error, update.bin is not a file");
-         updateBin.close();
-         return;
-      }
+  File updateBin = fs.open("/update.bin");
+  if (updateBin) {
+    if (updateBin.isDirectory()) {
+      Serial.println("Error, update.bin is not a file");
+      updateBin.close();
+      return;
+    }
 
-      size_t updateSize = updateBin.size();
+    size_t updateSize = updateBin.size();
 
-      if (updateSize > 0) {
-         Serial.println("Try to start update");
-         performUpdate(updateBin, updateSize);
-      }
-      else {
-         Serial.println("Error, file is empty");
-      }
+    if (updateSize > 0) {
+      Serial.println("Try to start update");
+      performUpdate(updateBin, updateSize);
+    } else {
+      Serial.println("Error, file is empty");
+    }
 
-      updateBin.close();
-    
-      // whe finished remove the binary from sd card to indicate end of the process
-      fs.remove("/update.bin");      
-   }
-   else {
-      Serial.println("Could not load update.bin from sd root");
-   }
+    updateBin.close();
+
+    // when finished remove the binary from sd card to indicate end of the process
+    fs.remove("/update.bin");
+  } else {
+    Serial.println("Could not load update.bin from sd root");
+  }
 }
 
 void setup() {
-   uint8_t cardType;
-   Serial.begin(115200);
-   Serial.println("Welcome to the SD-Update example!");
+  uint8_t cardType;
+  Serial.begin(115200);
+  Serial.println("Welcome to the SD-Update example!");
 
-   // You can uncomment this and build again
-   // Serial.println("Update successfull");
+  // You can uncomment this and build again
+  // Serial.println("Update successful");
 
-   //first init and check SD card
-   if (!SD_MMC.begin()) {
-      rebootEspWithReason("Card Mount Failed");
-   }
+  //first init and check SD card
+  if (!SD.begin()) {
+    rebootEspWithReason("Card Mount Failed");
+  }
 
-   cardType = SD_MMC.cardType();
+  cardType = SD.cardType();
 
-   if (cardType == CARD_NONE) {
-      rebootEspWithReason("No SD_MMC card attached");
-   }else{
-      updateFromFS(SD_MMC);
+  if (cardType == CARD_NONE) {
+    rebootEspWithReason("No SD_MMC card attached");
+  } else {
+    updateFromFS(SD);
   }
 }
 
-void rebootEspWithReason(String reason){
-    Serial.println(reason);
-    delay(1000);
-    ESP.restart();
+void rebootEspWithReason(String reason) {
+  Serial.println(reason);
+  delay(1000);
+  ESP.restart();
 }
 
 //will not be reached
-void loop() {
-  
-}
\ No newline at end of file
+void loop() {}
diff --git a/libraries/Update/keywords.txt b/libraries/Update/keywords.txt
index 95dd92591c8..53544dbaf6c 100644
--- a/libraries/Update/keywords.txt
+++ b/libraries/Update/keywords.txt
@@ -21,4 +21,3 @@ printError	KEYWORD2
 #######################################
 # Constants (LITERAL1)
 #######################################
-
diff --git a/libraries/Update/library.properties b/libraries/Update/library.properties
index 666b1e425b6..c3ee8f7e506 100644
--- a/libraries/Update/library.properties
+++ b/libraries/Update/library.properties
@@ -1,5 +1,5 @@
 name=Update
-version=1.0
+version=3.2.0
 author=Hristo Gochkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=ESP32 Sketch Update Library
diff --git a/libraries/Update/src/HttpsOTAUpdate.cpp b/libraries/Update/src/HttpsOTAUpdate.cpp
index 574b054c721..9cc700a8cc8 100644
--- a/libraries/Update/src/HttpsOTAUpdate.cpp
+++ b/libraries/Update/src/HttpsOTAUpdate.cpp
@@ -11,20 +11,20 @@
 
 #include <freertos/FreeRTOS.h>
 #include <freertos/task.h>
+#include <freertos/event_groups.h>
 
 #include "esp32-hal-log.h"
 #include "esp_http_client.h"
 #include "esp_https_ota.h"
 
 #include "HttpsOTAUpdate.h"
-#include "Esp.h"
 #define OTA_TASK_STACK_SIZE 9216
 
-typedef void (*HttpEventCb)(HttpEvent_t*);
+typedef void (*HttpEventCb)(HttpEvent_t *);
 
-static esp_http_client_config_t config; 
+static esp_http_client_config_t config;
 static HttpEventCb cb;
-static EventGroupHandle_t ota_status = NULL;//check for ota status
+static EventGroupHandle_t ota_status = NULL;  //check for ota status
 static EventBits_t set_bit;
 
 const int OTA_IDLE_BIT = BIT0;
@@ -32,76 +32,78 @@ const int OTA_UPDATING_BIT = BIT1;
 const int OTA_SUCCESS_BIT = BIT2;
 const int OTA_FAIL_BIT = BIT3;
 
-esp_err_t http_event_handler(esp_http_client_event_t *event)
-{
-    cb(event); 
-    return ESP_OK;
+esp_err_t http_event_handler(esp_http_client_event_t *event) {
+  cb(event);
+  return ESP_OK;
 }
 
-void https_ota_task(void *param)
-{
-    if(ota_status) {
-        xEventGroupSetBits(ota_status, OTA_UPDATING_BIT);
-        xEventGroupClearBits(ota_status, OTA_IDLE_BIT);
+void https_ota_task(void *param) {
+  if (ota_status) {
+    xEventGroupSetBits(ota_status, OTA_UPDATING_BIT);
+    xEventGroupClearBits(ota_status, OTA_IDLE_BIT);
+  }
+  esp_https_ota_config_t cfg;
+  cfg.http_config = (const esp_http_client_config_t *)param;
+  cfg.http_client_init_cb = NULL;
+  cfg.bulk_flash_erase = false;       //Erase entire flash partition during initialization
+  cfg.partial_http_download = false;  //Enable Firmware image to be downloaded over multiple HTTP requests
+  cfg.max_http_request_size = 0;      //Maximum request size for partial HTTP download
+
+  esp_err_t ret = esp_https_ota((const esp_https_ota_config_t *)&cfg);
+  if (ret == ESP_OK) {
+    if (ota_status) {
+      xEventGroupClearBits(ota_status, OTA_UPDATING_BIT);
+      xEventGroupSetBits(ota_status, OTA_SUCCESS_BIT);
     }
-    esp_err_t ret = esp_https_ota((const esp_http_client_config_t *)param);
-    if(ret == ESP_OK) {
-        if(ota_status) {
-            xEventGroupClearBits(ota_status, OTA_UPDATING_BIT);
-            xEventGroupSetBits(ota_status, OTA_SUCCESS_BIT);
-        }
-    } else {
-        if(ota_status) {  
-            xEventGroupClearBits(ota_status, OTA_UPDATING_BIT);
-            xEventGroupSetBits(ota_status, OTA_FAIL_BIT);
-        }
+  } else {
+    if (ota_status) {
+      xEventGroupClearBits(ota_status, OTA_UPDATING_BIT);
+      xEventGroupSetBits(ota_status, OTA_FAIL_BIT);
     }
-    vTaskDelete(NULL);
+  }
+  vTaskDelete(NULL);
 }
 
-HttpsOTAStatus_t HttpsOTAUpdateClass::status()
-{
-    if(ota_status) {     
-        set_bit =  xEventGroupGetBits(ota_status);
-        if(set_bit == OTA_IDLE_BIT) {
-            return HTTPS_OTA_IDLE;
-        }
-        if(set_bit == OTA_UPDATING_BIT) {
-            return HTTPS_OTA_UPDATING;
-        }
-        if(set_bit == OTA_SUCCESS_BIT) {
-            return HTTPS_OTA_SUCCESS;
-        }
-        if(set_bit == OTA_FAIL_BIT) {
-            return HTTPS_OTA_FAIL;
-        }
+HttpsOTAStatus_t HttpsOTAUpdateClass::status() {
+  if (ota_status) {
+    set_bit = xEventGroupGetBits(ota_status);
+    if (set_bit == OTA_IDLE_BIT) {
+      return HTTPS_OTA_IDLE;
+    }
+    if (set_bit == OTA_UPDATING_BIT) {
+      return HTTPS_OTA_UPDATING;
+    }
+    if (set_bit == OTA_SUCCESS_BIT) {
+      return HTTPS_OTA_SUCCESS;
+    }
+    if (set_bit == OTA_FAIL_BIT) {
+      return HTTPS_OTA_FAIL;
     }
-    return HTTPS_OTA_ERR;
+  }
+  return HTTPS_OTA_ERR;
 }
 
-void HttpsOTAUpdateClass::onHttpEvent(HttpEventCb cbEvent)
-{
-    cb = cbEvent;
+void HttpsOTAUpdateClass::onHttpEvent(HttpEventCb cbEvent) {
+  cb = cbEvent;
 }
 
-void HttpsOTAUpdateClass::begin(const char *url, const char *cert_pem, bool skip_cert_common_name_check)
-{
-    config.url = url;
-    config.cert_pem = cert_pem; 
-    config.skip_cert_common_name_check = skip_cert_common_name_check;
-    config.event_handler = http_event_handler;
-
-    if(!ota_status) {
-        ota_status = xEventGroupCreate();
-        if(!ota_status) {
-            log_e("OTA Event Group Create Failed");
-        }
-        xEventGroupSetBits(ota_status, OTA_IDLE_BIT);
-    }
- 
-    if (xTaskCreate(&https_ota_task, "https_ota_task", OTA_TASK_STACK_SIZE, &config, 5, NULL) != pdPASS) {
-        log_e("Couldn't create ota task\n"); 
+void HttpsOTAUpdateClass::begin(const char *url, const char *cert_pem, bool skip_cert_common_name_check) {
+  config.url = url;
+  config.cert_pem = cert_pem;
+  config.skip_cert_common_name_check = skip_cert_common_name_check;
+  config.event_handler = http_event_handler;
+
+  if (!ota_status) {
+    ota_status = xEventGroupCreate();
+    if (!ota_status) {
+      log_e("OTA Event Group Create Failed");
     }
+    xEventGroupSetBits(ota_status, OTA_IDLE_BIT);
+  }
+
+  if (xTaskCreate(&https_ota_task, "https_ota_task", OTA_TASK_STACK_SIZE, &config, 5, NULL) != pdPASS) {
+    log_e("Couldn't create ota task\n");
+  }
 }
 
 HttpsOTAUpdateClass HttpsOTA;
diff --git a/libraries/Update/src/HttpsOTAUpdate.h b/libraries/Update/src/HttpsOTAUpdate.h
index bc52a3055ce..d470ad50722 100644
--- a/libraries/Update/src/HttpsOTAUpdate.h
+++ b/libraries/Update/src/HttpsOTAUpdate.h
@@ -1,21 +1,31 @@
+/* OTA task
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+#ifndef HTTPSOTAUPDATE_H
+#define HTTPSOTAUPDATE_H
 #include "esp_http_client.h"
 #define HttpEvent_t esp_http_client_event_t
 
-typedef enum
-{
-    HTTPS_OTA_IDLE,
-    HTTPS_OTA_UPDATING,
-    HTTPS_OTA_SUCCESS,
-    HTTPS_OTA_FAIL,
-    HTTPS_OTA_ERR
-}HttpsOTAStatus_t;
+typedef enum {
+  HTTPS_OTA_IDLE,
+  HTTPS_OTA_UPDATING,
+  HTTPS_OTA_SUCCESS,
+  HTTPS_OTA_FAIL,
+  HTTPS_OTA_ERR
+} HttpsOTAStatus_t;
 
 class HttpsOTAUpdateClass {
 
-    public:
-    void begin(const char *url, const char *cert_pem, bool skip_cert_common_name_check = true);
-    void onHttpEvent(void (*http_event_cb_t)(HttpEvent_t *));
-    HttpsOTAStatus_t status();
+public:
+  void begin(const char *url, const char *cert_pem, bool skip_cert_common_name_check = true);
+  void onHttpEvent(void (*http_event_cb_t)(HttpEvent_t *));
+  HttpsOTAStatus_t status();
 };
 
 extern HttpsOTAUpdateClass HttpsOTA;
+#endif
diff --git a/libraries/Update/src/Update.h b/libraries/Update/src/Update.h
index 15c7624c46d..9a4d3e02489 100644
--- a/libraries/Update/src/Update.h
+++ b/libraries/Update/src/Update.h
@@ -1,66 +1,95 @@
-#ifndef ESP8266UPDATER_H
-#define ESP8266UPDATER_H
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ESP32UPDATER_H
+#define ESP32UPDATER_H
 
 #include <Arduino.h>
 #include <MD5Builder.h>
 #include <functional>
 #include "esp_partition.h"
 
-#define UPDATE_ERROR_OK                 (0)
-#define UPDATE_ERROR_WRITE              (1)
-#define UPDATE_ERROR_ERASE              (2)
-#define UPDATE_ERROR_READ               (3)
-#define UPDATE_ERROR_SPACE              (4)
-#define UPDATE_ERROR_SIZE               (5)
-#define UPDATE_ERROR_STREAM             (6)
-#define UPDATE_ERROR_MD5                (7)
-#define UPDATE_ERROR_MAGIC_BYTE         (8)
-#define UPDATE_ERROR_ACTIVATE           (9)
-#define UPDATE_ERROR_NO_PARTITION       (10)
-#define UPDATE_ERROR_BAD_ARGUMENT       (11)
-#define UPDATE_ERROR_ABORT              (12)
+#define UPDATE_ERROR_OK           (0)
+#define UPDATE_ERROR_WRITE        (1)
+#define UPDATE_ERROR_ERASE        (2)
+#define UPDATE_ERROR_READ         (3)
+#define UPDATE_ERROR_SPACE        (4)
+#define UPDATE_ERROR_SIZE         (5)
+#define UPDATE_ERROR_STREAM       (6)
+#define UPDATE_ERROR_MD5          (7)
+#define UPDATE_ERROR_MAGIC_BYTE   (8)
+#define UPDATE_ERROR_ACTIVATE     (9)
+#define UPDATE_ERROR_NO_PARTITION (10)
+#define UPDATE_ERROR_BAD_ARGUMENT (11)
+#define UPDATE_ERROR_ABORT        (12)
+#define UPDATE_ERROR_DECRYPT      (13)
 
 #define UPDATE_SIZE_UNKNOWN 0xFFFFFFFF
 
-#define U_FLASH   0
-#define U_SPIFFS  100
-#define U_AUTH    200
+#define U_FLASH  0
+#define U_SPIFFS 100
+#define U_AUTH   200
+
+#define ENCRYPTED_BLOCK_SIZE       16
+#define ENCRYPTED_TWEAK_BLOCK_SIZE 32
+#define ENCRYPTED_KEY_SIZE         32
+
+#define U_AES_DECRYPT_NONE         0
+#define U_AES_DECRYPT_AUTO         1
+#define U_AES_DECRYPT_ON           2
+#define U_AES_DECRYPT_MODE_MASK    3
+#define U_AES_IMAGE_DECRYPTING_BIT 4
 
-#define ENCRYPTED_BLOCK_SIZE 16
+#define SPI_SECTORS_PER_BLOCK 16  // usually large erase block is 32k/64k
+#define SPI_FLASH_BLOCK_SIZE  (SPI_SECTORS_PER_BLOCK * SPI_FLASH_SEC_SIZE)
 
 class UpdateClass {
-  public:
-    typedef std::function<void(size_t, size_t)> THandlerFunction_Progress;
+public:
+  typedef std::function<void(size_t, size_t)> THandlerFunction_Progress;
 
-    UpdateClass();
+  UpdateClass();
 
-    /*
+  /*
       This callback will be called when Update is receiving data
     */
-    UpdateClass& onProgress(THandlerFunction_Progress fn);
+  UpdateClass &onProgress(THandlerFunction_Progress fn);
 
-    /*
+  /*
       Call this to check the space needed for the update
       Will return false if there is not enough space
     */
-    bool begin(size_t size=UPDATE_SIZE_UNKNOWN, int command = U_FLASH, int ledPin = -1, uint8_t ledOn = LOW, const char *label = NULL);
+  bool begin(size_t size = UPDATE_SIZE_UNKNOWN, int command = U_FLASH, int ledPin = -1, uint8_t ledOn = LOW, const char *label = NULL);
+
+#ifndef UPDATE_NOCRYPT
+  /*
+     Setup decryption configuration
+     Crypt Key is 32bytes(256bits) block of data, use the same key as used to encrypt image file
+     Crypt Address, use the same value as used to encrypt image file
+     Crypt Config,  use the same value as used to encrypt image file
+     Crypt Mode,    used to select if image files should be decrypted or not
+    */
+  bool setupCrypt(const uint8_t *cryptKey = 0, size_t cryptAddress = 0, uint8_t cryptConfig = 0xf, int cryptMode = U_AES_DECRYPT_AUTO);
+#endif /* UPDATE_NOCRYPT */
 
-    /*
+  /*
       Writes a buffer to the flash and increments the address
       Returns the amount written
     */
-    size_t write(uint8_t *data, size_t len);
+  size_t write(uint8_t *data, size_t len);
 
-    /*
+  /*
       Writes the remaining bytes from the Stream to the flash
       Uses readBytes() and sets UPDATE_ERROR_STREAM on timeout
       Returns the bytes written
       Should be equal to the remaining bytes when called
       Usable for slow streams like Serial
     */
-    size_t writeStream(Stream &data);
+  size_t writeStream(Stream &data);
 
-    /*
+  /*
       If all bytes are written
       this call will write the config to eboot
       and return true
@@ -68,123 +97,198 @@ class UpdateClass {
       or there is an error
       this will clear everything and return false
       the last error is available through getError()
-      evenIfRemaining is helpfull when you update without knowing the final size first
+      evenIfRemaining is helpful when you update without knowing the final size first
     */
-    bool end(bool evenIfRemaining = false);
+  bool end(bool evenIfRemaining = false);
 
-    /*
+#ifndef UPDATE_NOCRYPT
+  /*
+      sets AES256 key(32 bytes) used for decrypting image file
+    */
+  bool setCryptKey(const uint8_t *cryptKey);
+
+  /*
+      sets crypt mode used on image files
+    */
+  bool setCryptMode(const int cryptMode);
+
+  /*
+      sets address used for decrypting image file
+    */
+  void setCryptAddress(const size_t cryptAddress) {
+    _cryptAddress = cryptAddress & 0x00fffff0;
+  }
+
+  /*
+      sets crypt config used for decrypting image file
+    */
+  void setCryptConfig(const uint8_t cryptConfig) {
+    _cryptCfg = cryptConfig & 0x0f;
+  }
+#endif /* UPDATE_NOCRYPT */
+
+  /*
       Aborts the running update
     */
-    void abort();
+  void abort();
 
-    /*
+  /*
       Prints the last error to an output stream
     */
-    void printError(Print &out);
+  void printError(Print &out);
 
-    const char * errorString();
+  const char *errorString();
 
-    /*
+  /*
       sets the expected MD5 for the firmware (hexString)
+      If calc_post_decryption is true, the update library will calculate the MD5 after the decryption, if false the calculation occurs before the decryption
     */
-    bool setMD5(const char * expected_md5);
+  bool setMD5(
+    const char *expected_md5
+#ifndef UPDATE_NOCRYPT
+    ,
+    bool calc_post_decryption = true
+#endif /* #ifdef UPDATE_NOCRYPT */
+  );
 
-    /*
+  /*
       returns the MD5 String of the successfully ended firmware
     */
-    String md5String(void){ return _md5.toString(); }
+  String md5String(void) {
+    return _md5.toString();
+  }
 
-    /*
+  /*
       populated the result with the md5 bytes of the successfully ended firmware
     */
-    void md5(uint8_t * result){ return _md5.getBytes(result); }
+  void md5(uint8_t *result) {
+    return _md5.getBytes(result);
+  }
 
-    //Helpers
-    uint8_t getError(){ return _error; }
-    void clearError(){ _error = UPDATE_ERROR_OK; }
-    bool hasError(){ return _error != UPDATE_ERROR_OK; }
-    bool isRunning(){ return _size > 0; }
-    bool isFinished(){ return _progress == _size; }
-    size_t size(){ return _size; }
-    size_t progress(){ return _progress; }
-    size_t remaining(){ return _size - _progress; }
+  //Helpers
+  uint8_t getError() {
+    return _error;
+  }
+  void clearError() {
+    _error = UPDATE_ERROR_OK;
+  }
+  bool hasError() {
+    return _error != UPDATE_ERROR_OK;
+  }
+  bool isRunning() {
+    return _size > 0;
+  }
+  bool isFinished() {
+    return _progress == _size;
+  }
+  size_t size() {
+    return _size;
+  }
+  size_t progress() {
+    return _progress;
+  }
+  size_t remaining() {
+    return _size - _progress;
+  }
 
-    /*
+  /*
       Template to write from objects that expose
       available() and read(uint8_t*, size_t) methods
       faster than the writeStream method
       writes only what is available
     */
-    template<typename T>
-    size_t write(T &data){
-      size_t written = 0;
-      if (hasError() || !isRunning())
-        return 0;
+  template<typename T> size_t write(T &data) {
+    size_t written = 0;
+    if (hasError() || !isRunning()) {
+      return 0;
+    }
 
-      size_t available = data.available();
-      while(available) {
-        if(_bufferLen + available > remaining()){
-          available = remaining() - _bufferLen;
+    size_t available = data.available();
+    while (available) {
+      if (_bufferLen + available > remaining()) {
+        available = remaining() - _bufferLen;
+      }
+      if (_bufferLen + available > 4096) {
+        size_t toBuff = 4096 - _bufferLen;
+        data.read(_buffer + _bufferLen, toBuff);
+        _bufferLen += toBuff;
+        if (!_writeBuffer()) {
+          return written;
         }
-        if(_bufferLen + available > 4096) {
-          size_t toBuff = 4096 - _bufferLen;
-          data.read(_buffer + _bufferLen, toBuff);
-          _bufferLen += toBuff;
-          if(!_writeBuffer())
+        written += toBuff;
+      } else {
+        data.read(_buffer + _bufferLen, available);
+        _bufferLen += available;
+        written += available;
+        if (_bufferLen == remaining()) {
+          if (!_writeBuffer()) {
             return written;
-          written += toBuff;
-        } else {
-          data.read(_buffer + _bufferLen, available);
-          _bufferLen += available;
-          written += available;
-          if(_bufferLen == remaining()) {
-            if(!_writeBuffer()) {
-              return written;
-            }
           }
         }
-        if(remaining() == 0)
-          return written;
-        available = data.available();
       }
-      return written;
+      if (remaining() == 0) {
+        return written;
+      }
+      available = data.available();
     }
+    return written;
+  }
 
-    /*
+  /*
       check if there is a firmware on the other OTA partition that you can bootinto
     */
-    bool canRollBack();
-    /*
+  bool canRollBack();
+  /*
       set the other OTA partition as bootable (reboot to enable)
     */
-    bool rollBack();
+  bool rollBack();
 
-  private:
-    void _reset();
-    void _abort(uint8_t err);
-    bool _writeBuffer();
-    bool _verifyHeader(uint8_t data);
-    bool _verifyEnd();
-    bool _enablePartition(const esp_partition_t* partition);
+private:
+  void _reset();
+  void _abort(uint8_t err);
+#ifndef UPDATE_NOCRYPT
+  void _cryptKeyTweak(size_t cryptAddress, uint8_t *tweaked_key);
+  bool _decryptBuffer();
+#endif /* UPDATE_NOCRYPT */
+  bool _writeBuffer();
+  bool _verifyHeader(uint8_t data);
+  bool _verifyEnd();
+  bool _enablePartition(const esp_partition_t *partition);
+  bool _chkDataInBlock(const uint8_t *data, size_t len) const;  // check if block contains any data or is empty
 
+  uint8_t _error;
+#ifndef UPDATE_NOCRYPT
+  uint8_t *_cryptKey;
+  uint8_t *_cryptBuffer;
+#endif /* UPDATE_NOCRYPT */
+  uint8_t *_buffer;
+  uint8_t *_skipBuffer;
+  size_t _bufferLen;
+  size_t _size;
+  THandlerFunction_Progress _progress_callback;
+  uint32_t _progress;
+  uint32_t _paroffset;
+  uint32_t _command;
+  const esp_partition_t *_partition;
 
-    uint8_t _error;
-    uint8_t *_buffer;
-    uint8_t *_skipBuffer;
-    size_t _bufferLen;
-    size_t _size;
-    THandlerFunction_Progress _progress_callback;
-    uint32_t _progress;
-    uint32_t _command;
-    const esp_partition_t* _partition;
+  String _target_md5;
+#ifndef UPDATE_NOCRYPT
+  bool _target_md5_decrypted = true;
+#endif /* UPDATE_NOCRYPT */
+  MD5Builder _md5;
 
-    String _target_md5;
-    MD5Builder _md5;
+  int _ledPin;
+  uint8_t _ledOn;
 
-    int _ledPin;
-    uint8_t _ledOn;
+#ifndef UPDATE_NOCRYPT
+  uint8_t _cryptMode;
+  size_t _cryptAddress;
+  uint8_t _cryptCfg;
+#endif /* UPDATE_NOCRYPT */
 };
 
+#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_UPDATE)
 extern UpdateClass Update;
+#endif
 
 #endif
diff --git a/libraries/Update/src/Updater.cpp b/libraries/Update/src/Updater.cpp
index 7369de93733..3b0c517431d 100644
--- a/libraries/Update/src/Updater.cpp
+++ b/libraries/Update/src/Updater.cpp
@@ -1,386 +1,654 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #include "Update.h"
 #include "Arduino.h"
-#include "esp_spi_flash.h"
+#include "spi_flash_mmap.h"
 #include "esp_ota_ops.h"
 #include "esp_image_format.h"
-
-static const char * _err2str(uint8_t _error){
-    if(_error == UPDATE_ERROR_OK){
-        return ("No Error");
-    } else if(_error == UPDATE_ERROR_WRITE){
-        return ("Flash Write Failed");
-    } else if(_error == UPDATE_ERROR_ERASE){
-        return ("Flash Erase Failed");
-    } else if(_error == UPDATE_ERROR_READ){
-        return ("Flash Read Failed");
-    } else if(_error == UPDATE_ERROR_SPACE){
-        return ("Not Enough Space");
-    } else if(_error == UPDATE_ERROR_SIZE){
-        return ("Bad Size Given");
-    } else if(_error == UPDATE_ERROR_STREAM){
-        return ("Stream Read Timeout");
-    } else if(_error == UPDATE_ERROR_MD5){
-        return ("MD5 Check Failed");
-    } else if(_error == UPDATE_ERROR_MAGIC_BYTE){
-        return ("Wrong Magic Byte");
-    } else if(_error == UPDATE_ERROR_ACTIVATE){
-        return ("Could Not Activate The Firmware");
-    } else if(_error == UPDATE_ERROR_NO_PARTITION){
-        return ("Partition Could Not be Found");
-    } else if(_error == UPDATE_ERROR_BAD_ARGUMENT){
-        return ("Bad Argument");
-    } else if(_error == UPDATE_ERROR_ABORT){
-        return ("Aborted");
-    }
-    return ("UNKNOWN");
+#ifndef UPDATE_NOCRYPT
+#include "mbedtls/aes.h"
+#endif /* UPDATE_NOCRYPT */
+
+static const char *_err2str(uint8_t _error) {
+  if (_error == UPDATE_ERROR_OK) {
+    return ("No Error");
+  } else if (_error == UPDATE_ERROR_WRITE) {
+    return ("Flash Write Failed");
+  } else if (_error == UPDATE_ERROR_ERASE) {
+    return ("Flash Erase Failed");
+  } else if (_error == UPDATE_ERROR_READ) {
+    return ("Flash Read Failed");
+  } else if (_error == UPDATE_ERROR_SPACE) {
+    return ("Not Enough Space");
+  } else if (_error == UPDATE_ERROR_SIZE) {
+    return ("Bad Size Given");
+  } else if (_error == UPDATE_ERROR_STREAM) {
+    return ("Stream Read Timeout");
+  } else if (_error == UPDATE_ERROR_MD5) {
+    return ("MD5 Check Failed");
+  } else if (_error == UPDATE_ERROR_MAGIC_BYTE) {
+    return ("Wrong Magic Byte");
+  } else if (_error == UPDATE_ERROR_ACTIVATE) {
+    return ("Could Not Activate The Firmware");
+  } else if (_error == UPDATE_ERROR_NO_PARTITION) {
+    return ("Partition Could Not be Found");
+  } else if (_error == UPDATE_ERROR_BAD_ARGUMENT) {
+    return ("Bad Argument");
+  } else if (_error == UPDATE_ERROR_ABORT) {
+    return ("Aborted");
+#ifndef UPDATE_NOCRYPT
+  } else if (_error == UPDATE_ERROR_DECRYPT) {
+    return ("Decryption error");
+#endif /* UPDATE_NOCRYPT */
+  }
+  return ("UNKNOWN");
 }
 
-static bool _partitionIsBootable(const esp_partition_t* partition){
-    uint8_t buf[ENCRYPTED_BLOCK_SIZE];
-    if(!partition){
-        return false;
-    }
-    if(!ESP.partitionRead(partition, 0, (uint32_t*)buf, ENCRYPTED_BLOCK_SIZE)) {
-        return false;
-    }
+static bool _partitionIsBootable(const esp_partition_t *partition) {
+  uint8_t buf[ENCRYPTED_BLOCK_SIZE];
+  if (!partition) {
+    return false;
+  }
+  if (!ESP.partitionRead(partition, 0, (uint32_t *)buf, ENCRYPTED_BLOCK_SIZE)) {
+    return false;
+  }
 
-    if(buf[0] != ESP_IMAGE_HEADER_MAGIC) {
-        return false;
-    }
-    return true;
+  if (buf[0] != ESP_IMAGE_HEADER_MAGIC) {
+    return false;
+  }
+  return true;
 }
 
-bool UpdateClass::_enablePartition(const esp_partition_t* partition){
-    if(!partition){
-        return false;
-    }
-    return ESP.partitionWrite(partition, 0, (uint32_t*) _skipBuffer, ENCRYPTED_BLOCK_SIZE);
+bool UpdateClass::_enablePartition(const esp_partition_t *partition) {
+  if (!partition) {
+    return false;
+  }
+  return ESP.partitionWrite(partition, 0, (uint32_t *)_skipBuffer, ENCRYPTED_BLOCK_SIZE);
 }
 
 UpdateClass::UpdateClass()
-: _error(0)
-, _buffer(0)
-, _bufferLen(0)
-, _size(0)
-, _progress_callback(NULL)
-, _progress(0)
-, _command(U_FLASH)
-, _partition(NULL)
+  : _error(0),
+#ifndef UPDATE_NOCRYPT
+    _cryptKey(0), _cryptBuffer(0),
+#endif /* UPDATE_NOCRYPT */
+    _buffer(0), _skipBuffer(0), _bufferLen(0), _size(0), _progress_callback(NULL), _progress(0), _paroffset(0), _command(U_FLASH), _partition(NULL)
+#ifndef UPDATE_NOCRYPT
+    ,
+    _cryptMode(U_AES_DECRYPT_AUTO), _cryptAddress(0), _cryptCfg(0xf)
+#endif /* UPDATE_NOCRYPT */
 {
 }
 
-UpdateClass& UpdateClass::onProgress(THandlerFunction_Progress fn) {
-    _progress_callback = fn;
-    return *this;
+UpdateClass &UpdateClass::onProgress(THandlerFunction_Progress fn) {
+  _progress_callback = fn;
+  return *this;
 }
 
 void UpdateClass::_reset() {
-    if (_buffer)
-        delete[] _buffer;
-    _buffer = 0;
-    _bufferLen = 0;
-    _progress = 0;
-    _size = 0;
-    _command = U_FLASH;
-
-    if(_ledPin != -1) {
-      digitalWrite(_ledPin, !_ledOn); // off
-    }
+  if (_buffer) {
+    delete[] _buffer;
+  }
+  if (_skipBuffer) {
+    delete[] _skipBuffer;
+  }
+
+#ifndef UPDATE_NOCRYPT
+  _cryptBuffer = nullptr;
+#endif /* UPDATE_NOCRYPT */
+  _buffer = nullptr;
+  _skipBuffer = nullptr;
+  _bufferLen = 0;
+  _progress = 0;
+  _size = 0;
+  _command = U_FLASH;
+
+  if (_ledPin != -1) {
+    digitalWrite(_ledPin, !_ledOn);  // off
+  }
 }
 
-bool UpdateClass::canRollBack(){
-    if(_buffer){ //Update is running
-        return false;
-    }
-    const esp_partition_t* partition = esp_ota_get_next_update_partition(NULL);
-    return _partitionIsBootable(partition);
+bool UpdateClass::canRollBack() {
+  if (_buffer) {  //Update is running
+    return false;
+  }
+  const esp_partition_t *partition = esp_ota_get_next_update_partition(NULL);
+  return _partitionIsBootable(partition);
 }
 
-bool UpdateClass::rollBack(){
-    if(_buffer){ //Update is running
-        return false;
-    }
-    const esp_partition_t* partition = esp_ota_get_next_update_partition(NULL);
-    return _partitionIsBootable(partition) && !esp_ota_set_boot_partition(partition);
+bool UpdateClass::rollBack() {
+  if (_buffer) {  //Update is running
+    return false;
+  }
+  const esp_partition_t *partition = esp_ota_get_next_update_partition(NULL);
+  return _partitionIsBootable(partition) && !esp_ota_set_boot_partition(partition);
 }
 
 bool UpdateClass::begin(size_t size, int command, int ledPin, uint8_t ledOn, const char *label) {
-    if(_size > 0){
-        log_w("already running");
-        return false;
-    }
+  if (_size > 0) {
+    log_w("already running");
+    return false;
+  }
 
-    _ledPin = ledPin;
-    _ledOn = !!ledOn; // 0(LOW) or 1(HIGH)
+  _ledPin = ledPin;
+  _ledOn = !!ledOn;  // 0(LOW) or 1(HIGH)
 
-    _reset();
-    _error = 0;
-    _target_md5 = emptyString;
-    _md5 = MD5Builder();
+  _reset();
+  _error = 0;
+  _target_md5 = emptyString;
+  _md5 = MD5Builder();
 
-    if(size == 0) {
-        _error = UPDATE_ERROR_SIZE;
+  if (size == 0) {
+    _error = UPDATE_ERROR_SIZE;
+    return false;
+  }
+
+  if (command == U_FLASH) {
+    _partition = esp_ota_get_next_update_partition(NULL);
+    if (!_partition) {
+      _error = UPDATE_ERROR_NO_PARTITION;
+      return false;
+    }
+    log_d("OTA Partition: %s", _partition->label);
+  } else if (command == U_SPIFFS) {
+    _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, label);
+    _paroffset = 0;
+    if (!_partition) {
+      _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, NULL);
+      _paroffset = 0x1000;  //Offset for ffat, assuming size is already corrected
+      if (!_partition) {
+        _error = UPDATE_ERROR_NO_PARTITION;
         return false;
+      }
     }
+  } else {
+    _error = UPDATE_ERROR_BAD_ARGUMENT;
+    log_e("bad command %u", command);
+    return false;
+  }
 
-    if (command == U_FLASH) {
-        _partition = esp_ota_get_next_update_partition(NULL);
-        if(!_partition){
-            _error = UPDATE_ERROR_NO_PARTITION;
-            return false;
-        }
-        log_d("OTA Partition: %s", _partition->label);
-    }
-    else if (command == U_SPIFFS) {
-        _partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, label);
-        if(!_partition){
-            _error = UPDATE_ERROR_NO_PARTITION;
-            return false;
-        }
-    }
-    else {
-        _error = UPDATE_ERROR_BAD_ARGUMENT;
-        log_e("bad command %u", command);
-        return false;
-    }
+  if (size == UPDATE_SIZE_UNKNOWN) {
+    size = _partition->size;
+  } else if (size > _partition->size) {
+    _error = UPDATE_ERROR_SIZE;
+    log_e("too large %u > %u", size, _partition->size);
+    return false;
+  }
 
-    if(size == UPDATE_SIZE_UNKNOWN){
-        size = _partition->size;
-    } else if(size > _partition->size){
-        _error = UPDATE_ERROR_SIZE;
-        log_e("too large %u > %u", size, _partition->size);
-        return false;
-    }
+  //initialize
+  _buffer = new (std::nothrow) uint8_t[SPI_FLASH_SEC_SIZE];
+  if (!_buffer) {
+    log_e("_buffer allocation failed");
+    return false;
+  }
+  _size = size;
+  _command = command;
+  _md5.begin();
+  return true;
+}
 
-    //initialize
-    _buffer = (uint8_t*)malloc(SPI_FLASH_SEC_SIZE);
-    if(!_buffer){
-        log_e("malloc failed");
-        return false;
+#ifndef UPDATE_NOCRYPT
+bool UpdateClass::setupCrypt(const uint8_t *cryptKey, size_t cryptAddress, uint8_t cryptConfig, int cryptMode) {
+  if (setCryptKey(cryptKey)) {
+    if (setCryptMode(cryptMode)) {
+      setCryptAddress(cryptAddress);
+      setCryptConfig(cryptConfig);
+      return true;
     }
-    _size = size;
-    _command = command;
-    _md5.begin();
-    return true;
+  }
+  return false;
 }
 
-void UpdateClass::_abort(uint8_t err){
-    _reset();
-    _error = err;
+bool UpdateClass::setCryptKey(const uint8_t *cryptKey) {
+  if (!cryptKey) {
+    if (_cryptKey) {
+      delete[] _cryptKey;
+      _cryptKey = 0;
+      log_d("AES key unset");
+    }
+    return false;  //key cleared, no key to decrypt with
+  }
+  //initialize
+  if (!_cryptKey) {
+    _cryptKey = new (std::nothrow) uint8_t[ENCRYPTED_KEY_SIZE];
+  }
+  if (!_cryptKey) {
+    log_e("new failed");
+    return false;
+  }
+  memcpy(_cryptKey, cryptKey, ENCRYPTED_KEY_SIZE);
+  return true;
 }
 
-void UpdateClass::abort(){
-    _abort(UPDATE_ERROR_ABORT);
+bool UpdateClass::setCryptMode(const int cryptMode) {
+  if (cryptMode >= U_AES_DECRYPT_NONE && cryptMode <= U_AES_DECRYPT_ON) {
+    _cryptMode = cryptMode;
+  } else {
+    log_e("bad crypt mode argument %i", cryptMode);
+    return false;
+  }
+  return true;
 }
+#endif /* UPDATE_NOCRYPT */
 
-bool UpdateClass::_writeBuffer(){
-    //first bytes of new firmware
-    uint8_t skip = 0;
-    if(!_progress && _command == U_FLASH){
-        //check magic
-        if(_buffer[0] != ESP_IMAGE_HEADER_MAGIC){
-            _abort(UPDATE_ERROR_MAGIC_BYTE);
-            return false;
-        }
+void UpdateClass::_abort(uint8_t err) {
+  _reset();
+  _error = err;
+}
 
-        //Stash the first 16 bytes of data and set the offset so they are
-        //not written at this point so that partially written firmware
-        //will not be bootable
-        skip = ENCRYPTED_BLOCK_SIZE;
-        _skipBuffer = (uint8_t*)malloc(skip);
-        if(!_skipBuffer){
-            log_e("malloc failed");
-        return false;
+void UpdateClass::abort() {
+  _abort(UPDATE_ERROR_ABORT);
+}
+
+#ifndef UPDATE_NOCRYPT
+void UpdateClass::_cryptKeyTweak(size_t cryptAddress, uint8_t *tweaked_key) {
+  memcpy(tweaked_key, _cryptKey, ENCRYPTED_KEY_SIZE);
+  if (_cryptCfg == 0) {
+    return;  //no tweaking needed, use crypt key as-is
+  }
+
+  const uint8_t pattern[] = {23, 23, 23, 14, 23, 23, 23, 12, 23, 23, 23, 10, 23, 23, 23, 8};
+  int pattern_idx = 0;
+  int key_idx = 0;
+  int bit_len = 0;
+  uint32_t tweak = 0;
+  cryptAddress &= 0x00ffffe0;  //bit 23-5
+  cryptAddress <<= 8;          //bit23 shifted to bit31(MSB)
+  while (pattern_idx < sizeof(pattern)) {
+    tweak = cryptAddress << (23 - pattern[pattern_idx]);  //bit shift for small patterns
+    // alternative to: tweak = rotl32(tweak,8 - bit_len);
+    tweak = (tweak << (8 - bit_len)) | (tweak >> (24 + bit_len));  //rotate to line up with end of previous tweak bits
+    bit_len += pattern[pattern_idx++] - 4;                         //add number of bits in next pattern(23-4 = 19bits = 23bit to 5bit)
+    while (bit_len > 7) {
+      tweaked_key[key_idx++] ^= tweak;  //XOR byte
+      // alternative to: tweak = rotl32(tweak, 8);
+      tweak = (tweak << 8) | (tweak >> 24);  //compiler should optimize to use rotate(fast)
+      bit_len -= 8;
+    }
+    tweaked_key[key_idx] ^= tweak;  //XOR remaining bits, will XOR zeros if no remaining bits
+  }
+  if (_cryptCfg == 0xf) {
+    return;  //return with fully tweaked key
+  }
+
+  //some of tweaked key bits need to be restore back to crypt key bits
+  const uint8_t cfg_bits[] = {67, 65, 63, 61};
+  key_idx = 0;
+  pattern_idx = 0;
+  while (key_idx < ENCRYPTED_KEY_SIZE) {
+    bit_len += cfg_bits[pattern_idx];
+    if ((_cryptCfg & (1 << pattern_idx)) == 0) {  //restore crypt key bits
+      while (bit_len > 0) {
+        if (bit_len > 7 || ((_cryptCfg & (2 << pattern_idx)) == 0)) {  //restore a crypt key byte
+          tweaked_key[key_idx] = _cryptKey[key_idx];
+        } else {  //MSBits restore crypt key bits, LSBits keep as tweaked bits
+          tweaked_key[key_idx] &= (0xff >> bit_len);
+          tweaked_key[key_idx] |= (_cryptKey[key_idx] & (~(0xff >> bit_len)));
         }
-        memcpy(_skipBuffer, _buffer, skip);
-    }
-    if (!_progress && _progress_callback) {
-        _progress_callback(0, _size);
+        key_idx++;
+        bit_len -= 8;
+      }
+    } else {  //keep tweaked key bits
+      while (bit_len > 0) {
+        if (bit_len < 8 && ((_cryptCfg & (2 << pattern_idx)) == 0)) {  //MSBits keep as tweaked bits, LSBits restore crypt key bits
+          tweaked_key[key_idx] &= (~(0xff >> bit_len));
+          tweaked_key[key_idx] |= (_cryptKey[key_idx] & (0xff >> bit_len));
+        }
+        key_idx++;
+        bit_len -= 8;
+      }
     }
-    if(!ESP.partitionEraseRange(_partition, _progress, SPI_FLASH_SEC_SIZE)){
-        _abort(UPDATE_ERROR_ERASE);
+    pattern_idx++;
+  }
+}
+
+bool UpdateClass::_decryptBuffer() {
+  if (!_cryptKey) {
+    log_w("AES key not set");
+    return false;
+  }
+  if (_bufferLen % ENCRYPTED_BLOCK_SIZE != 0) {
+    log_e("buffer size error");
+    return false;
+  }
+  if (!_cryptBuffer) {
+    _cryptBuffer = new (std::nothrow) uint8_t[ENCRYPTED_BLOCK_SIZE];
+  }
+  if (!_cryptBuffer) {
+    log_e("new failed");
+    return false;
+  }
+  uint8_t tweaked_key[ENCRYPTED_KEY_SIZE];  //tweaked crypt key
+  int done = 0;
+
+  /*
+        Mbedtls functions will be replaced with esp_aes functions when hardware acceleration is available
+
+        To Do:
+        Replace mbedtls for the cases where there's no hardware acceleration
+     */
+
+  mbedtls_aes_context ctx;  //initialize AES
+  mbedtls_aes_init(&ctx);
+  while ((_bufferLen - done) >= ENCRYPTED_BLOCK_SIZE) {
+    for (int i = 0; i < ENCRYPTED_BLOCK_SIZE; i++) {
+      _cryptBuffer[(ENCRYPTED_BLOCK_SIZE - 1) - i] = _buffer[i + done];  //reverse order 16 bytes to decrypt
+    }
+    if (((_cryptAddress + _progress + done) % ENCRYPTED_TWEAK_BLOCK_SIZE) == 0 || done == 0) {
+      _cryptKeyTweak(_cryptAddress + _progress + done, tweaked_key);  //update tweaked crypt key
+      if (mbedtls_aes_setkey_enc(&ctx, tweaked_key, 256)) {
         return false;
-    }
-    if (!ESP.partitionWrite(_partition, _progress + skip, (uint32_t*)_buffer + skip/sizeof(uint32_t), _bufferLen - skip)) {
-        _abort(UPDATE_ERROR_WRITE);
+      }
+      if (mbedtls_aes_setkey_dec(&ctx, tweaked_key, 256)) {
         return false;
+      }
     }
-    //restore magic or md5 will fail
-    if(!_progress && _command == U_FLASH){
-        _buffer[0] = ESP_IMAGE_HEADER_MAGIC;
+    if (mbedtls_aes_crypt_ecb(&ctx, MBEDTLS_AES_ENCRYPT, _cryptBuffer, _cryptBuffer)) {  //use MBEDTLS_AES_ENCRYPT to decrypt flash code
+      return false;
     }
-    _md5.add(_buffer, _bufferLen);
-    _progress += _bufferLen;
-    _bufferLen = 0;
-    if (_progress_callback) {
-        _progress_callback(_progress, _size);
+    for (int i = 0; i < ENCRYPTED_BLOCK_SIZE; i++) {
+      _buffer[i + done] = _cryptBuffer[(ENCRYPTED_BLOCK_SIZE - 1) - i];  //reverse order 16 bytes from decrypt
     }
-    return true;
+    done += ENCRYPTED_BLOCK_SIZE;
+  }
+  return true;
 }
+#endif /* UPDATE_NOCRYPT */
 
-bool UpdateClass::_verifyHeader(uint8_t data) {
-    if(_command == U_FLASH) {
-        if(data != ESP_IMAGE_HEADER_MAGIC) {
-            _abort(UPDATE_ERROR_MAGIC_BYTE);
-            return false;
-        }
-        return true;
-    } else if(_command == U_SPIFFS) {
-        return true;
+bool UpdateClass::_writeBuffer() {
+#ifndef UPDATE_NOCRYPT
+  //first bytes of loading image, check to see if loading image needs decrypting
+  if (!_progress) {
+    _cryptMode &= U_AES_DECRYPT_MODE_MASK;
+    if ((_cryptMode == U_AES_DECRYPT_ON) || ((_command == U_FLASH) && (_cryptMode & U_AES_DECRYPT_AUTO) && (_buffer[0] != ESP_IMAGE_HEADER_MAGIC))) {
+      _cryptMode |= U_AES_IMAGE_DECRYPTING_BIT;  //set to decrypt the loading image
+      log_d("Decrypting OTA Image");
     }
-    return false;
-}
+  }
 
-bool UpdateClass::_verifyEnd() {
-    if(_command == U_FLASH) {
-        if(!_enablePartition(_partition) || !_partitionIsBootable(_partition)) {
-            _abort(UPDATE_ERROR_READ);
-            return false;
-        }
-
-        if(esp_ota_set_boot_partition(_partition)){
-            _abort(UPDATE_ERROR_ACTIVATE);
-            return false;
-        }
-        _reset();
-        return true;
-    } else if(_command == U_SPIFFS) {
-        _reset();
-        return true;
-    }
+  if (!_target_md5_decrypted) {
+    _md5.add(_buffer, _bufferLen);
+  }
+
+  //check if data in buffer needs decrypting
+  if (_cryptMode & U_AES_IMAGE_DECRYPTING_BIT) {
+    if (!_decryptBuffer()) {
+      _abort(UPDATE_ERROR_DECRYPT);
+      return false;
+    }
+  }
+#endif /* UPDATE_NOCRYPT */
+  //first bytes of new firmware
+  uint8_t skip = 0;
+  if (!_progress && _command == U_FLASH) {
+    //check magic
+    if (_buffer[0] != ESP_IMAGE_HEADER_MAGIC) {
+      _abort(UPDATE_ERROR_MAGIC_BYTE);
+      return false;
+    }
+
+    //Stash the first 16 bytes of data and set the offset so they are
+    //not written at this point so that partially written firmware
+    //will not be bootable
+    skip = ENCRYPTED_BLOCK_SIZE;
+    _skipBuffer = new (std::nothrow) uint8_t[skip];
+    if (!_skipBuffer) {
+      log_e("_skipBuffer allocation failed");
+      return false;
+    }
+    memcpy(_skipBuffer, _buffer, skip);
+  }
+  if (!_progress && _progress_callback) {
+    _progress_callback(0, _size);
+  }
+  size_t offset = _partition->address + _progress;
+  bool block_erase =
+    (_size - _progress >= SPI_FLASH_BLOCK_SIZE) && (offset % SPI_FLASH_BLOCK_SIZE == 0);  // if it's the block boundary, than erase the whole block from here
+  bool part_head_sectors =
+    _partition->address % SPI_FLASH_BLOCK_SIZE
+    && offset < (_partition->address / SPI_FLASH_BLOCK_SIZE + 1) * SPI_FLASH_BLOCK_SIZE;  // sector belong to unaligned partition heading block
+  bool part_tail_sectors =
+    offset >= (_partition->address + _size) / SPI_FLASH_BLOCK_SIZE * SPI_FLASH_BLOCK_SIZE;  // sector belong to unaligned partition tailing block
+  if (block_erase || part_head_sectors || part_tail_sectors) {
+    if (!ESP.partitionEraseRange(_partition, _progress, block_erase ? SPI_FLASH_BLOCK_SIZE : SPI_FLASH_SEC_SIZE)) {
+      _abort(UPDATE_ERROR_ERASE);
+      return false;
+    }
+  }
+
+  // try to skip empty blocks on unencrypted partitions
+  if ((_partition->encrypted || _chkDataInBlock(_buffer + skip / sizeof(uint32_t), _bufferLen - skip))
+      && !ESP.partitionWrite(_partition, _progress + skip, (uint32_t *)_buffer + skip / sizeof(uint32_t), _bufferLen - skip)) {
+    _abort(UPDATE_ERROR_WRITE);
     return false;
+  }
+
+  //restore magic or md5 will fail
+  if (!_progress && _command == U_FLASH) {
+    _buffer[0] = ESP_IMAGE_HEADER_MAGIC;
+  }
+#ifndef UPDATE_NOCRYPT
+  if (_target_md5_decrypted) {
+#endif /* UPDATE_NOCRYPT */
+    _md5.add(_buffer, _bufferLen);
+#ifndef UPDATE_NOCRYPT
+  }
+#endif /* UPDATE_NOCRYPT */
+  _progress += _bufferLen;
+  _bufferLen = 0;
+  if (_progress_callback) {
+    _progress_callback(_progress, _size);
+  }
+  return true;
 }
 
-bool UpdateClass::setMD5(const char * expected_md5){
-    if(strlen(expected_md5) != 32)
-    {
-        return false;
+bool UpdateClass::_verifyHeader(uint8_t data) {
+  if (_command == U_FLASH) {
+    if (data != ESP_IMAGE_HEADER_MAGIC) {
+      _abort(UPDATE_ERROR_MAGIC_BYTE);
+      return false;
     }
-    _target_md5 = expected_md5;
     return true;
+  } else if (_command == U_SPIFFS) {
+    return true;
+  }
+  return false;
 }
 
-bool UpdateClass::end(bool evenIfRemaining){
-    if(hasError() || _size == 0){
-        return false;
+bool UpdateClass::_verifyEnd() {
+  if (_command == U_FLASH) {
+    if (!_enablePartition(_partition) || !_partitionIsBootable(_partition)) {
+      _abort(UPDATE_ERROR_READ);
+      return false;
     }
 
-    if(!isFinished() && !evenIfRemaining){
-        log_e("premature end: res:%u, pos:%u/%u\n", getError(), progress(), _size);
-        _abort(UPDATE_ERROR_ABORT);
-        return false;
+    if (esp_ota_set_boot_partition(_partition)) {
+      _abort(UPDATE_ERROR_ACTIVATE);
+      return false;
     }
+    _reset();
+    return true;
+  } else if (_command == U_SPIFFS) {
+    _reset();
+    return true;
+  }
+  return false;
+}
 
-    if(evenIfRemaining) {
-        if(_bufferLen > 0) {
-            _writeBuffer();
-        }
-        _size = progress();
-    }
+bool UpdateClass::setMD5(
+  const char *expected_md5
+#ifndef UPDATE_NOCRYPT
+  ,
+  bool calc_post_decryption
+#endif /* UPDATE_NOCRYPT */
+) {
+  if (strlen(expected_md5) != 32) {
+    return false;
+  }
+  _target_md5 = expected_md5;
+  _target_md5.toLowerCase();
+#ifndef UPDATE_NOCRYPT
+  _target_md5_decrypted = calc_post_decryption;
+#endif /* UPDATE_NOCRYPT */
+  return true;
+}
 
-    _md5.calculate();
-    if(_target_md5.length()) {
-        if(_target_md5 != _md5.toString()){
-            _abort(UPDATE_ERROR_MD5);
-            return false;
-        }
-    }
+bool UpdateClass::end(bool evenIfRemaining) {
+  if (hasError() || _size == 0) {
+    return false;
+  }
 
-    return _verifyEnd();
-}
+  if (!isFinished() && !evenIfRemaining) {
+    log_e("premature end: res:%u, pos:%u/%u\n", getError(), progress(), _size);
+    _abort(UPDATE_ERROR_ABORT);
+    return false;
+  }
 
-size_t UpdateClass::write(uint8_t *data, size_t len) {
-    if(hasError() || !isRunning()){
-        return 0;
+  if (evenIfRemaining) {
+    if (_bufferLen > 0) {
+      _writeBuffer();
     }
+    _size = progress();
+  }
 
-    if(len > remaining()){
-        _abort(UPDATE_ERROR_SPACE);
-        return 0;
+  _md5.calculate();
+  if (_target_md5.length()) {
+    if (_target_md5 != _md5.toString()) {
+      _abort(UPDATE_ERROR_MD5);
+      return false;
     }
+  }
 
-    size_t left = len;
+  return _verifyEnd();
+}
 
-    while((_bufferLen + left) > SPI_FLASH_SEC_SIZE) {
-        size_t toBuff = SPI_FLASH_SEC_SIZE - _bufferLen;
-        memcpy(_buffer + _bufferLen, data + (len - left), toBuff);
-        _bufferLen += toBuff;
-        if(!_writeBuffer()){
-            return len - left;
-        }
-        left -= toBuff;
-    }
-    memcpy(_buffer + _bufferLen, data + (len - left), left);
-    _bufferLen += left;
-    if(_bufferLen == remaining()){
-        if(!_writeBuffer()){
-            return len - left;
-        }
-    }
-    return len;
+size_t UpdateClass::write(uint8_t *data, size_t len) {
+  if (hasError() || !isRunning()) {
+    return 0;
+  }
+
+  if (len > remaining()) {
+    _abort(UPDATE_ERROR_SPACE);
+    return 0;
+  }
+
+  size_t left = len;
+
+  while ((_bufferLen + left) > SPI_FLASH_SEC_SIZE) {
+    size_t toBuff = SPI_FLASH_SEC_SIZE - _bufferLen;
+    memcpy(_buffer + _bufferLen, data + (len - left), toBuff);
+    _bufferLen += toBuff;
+    if (!_writeBuffer()) {
+      return len - left;
+    }
+    left -= toBuff;
+  }
+  memcpy(_buffer + _bufferLen, data + (len - left), left);
+  _bufferLen += left;
+  if (_bufferLen == remaining()) {
+    if (!_writeBuffer()) {
+      return len - left;
+    }
+  }
+  return len;
 }
 
 size_t UpdateClass::writeStream(Stream &data) {
-    size_t written = 0;
-    size_t toRead = 0;
-    int timeout_failures = 0;
+  size_t written = 0;
+  size_t toRead = 0;
+  int timeout_failures = 0;
 
-    if(hasError() || !isRunning())
-        return 0;
+  if (hasError() || !isRunning()) {
+    return 0;
+  }
 
-    if(!_verifyHeader(data.peek())) {
-        _reset();
-        return 0;
+#ifndef UPDATE_NOCRYPT
+  if (_command == U_FLASH && !_cryptMode) {
+#endif /* UPDATE_NOCRYPT */
+    if (!_verifyHeader(data.peek())) {
+      _reset();
+      return 0;
     }
+#ifndef UPDATE_NOCRYPT
+  }
+#endif /* UPDATE_NOCRYPT */
 
-    if(_ledPin != -1) {
-        pinMode(_ledPin, OUTPUT);
-    }
+  if (_ledPin != -1) {
+    pinMode(_ledPin, OUTPUT);
+  }
 
-    while(remaining()) {
-        if(_ledPin != -1) {
-            digitalWrite(_ledPin, _ledOn); // Switch LED on
-        }
-        size_t bytesToRead = SPI_FLASH_SEC_SIZE - _bufferLen;
-        if(bytesToRead > remaining()) {
-            bytesToRead = remaining();
-        }
+  while (remaining()) {
+    if (_ledPin != -1) {
+      digitalWrite(_ledPin, _ledOn);  // Switch LED on
+    }
+    size_t bytesToRead = SPI_FLASH_SEC_SIZE - _bufferLen;
+    if (bytesToRead > remaining()) {
+      bytesToRead = remaining();
+    }
 
-        /* 
+    /*
         Init read&timeout counters and try to read, if read failed, increase counter,
         wait 100ms and try to read again. If counter > 300 (30 sec), give up/abort
         */
-        toRead = 0;
-        timeout_failures = 0;
-        while(!toRead) {
-            toRead = data.readBytes(_buffer + _bufferLen,  bytesToRead);
-            if(toRead == 0) {
-                timeout_failures++;
-                if (timeout_failures >= 300) {
-                    _abort(UPDATE_ERROR_STREAM);
-                    return written;
-                }
-                delay(100);
-            }
+    toRead = 0;
+    timeout_failures = 0;
+    while (!toRead) {
+      toRead = data.readBytes(_buffer + _bufferLen, bytesToRead);
+      if (toRead == 0) {
+        timeout_failures++;
+        if (timeout_failures >= 300) {
+          _abort(UPDATE_ERROR_STREAM);
+          return written;
         }
+        delay(100);
+      }
+    }
 
-        if(_ledPin != -1) {
-            digitalWrite(_ledPin, !_ledOn); // Switch LED off
-        }
-        _bufferLen += toRead;
-        if((_bufferLen == remaining() || _bufferLen == SPI_FLASH_SEC_SIZE) && !_writeBuffer())
-            return written;
-        written += toRead;
+    if (_ledPin != -1) {
+      digitalWrite(_ledPin, !_ledOn);  // Switch LED off
+    }
+    _bufferLen += toRead;
+    if ((_bufferLen == remaining() || _bufferLen == SPI_FLASH_SEC_SIZE) && !_writeBuffer()) {
+      return written;
     }
-    return written;
+    written += toRead;
+
+#if CONFIG_FREERTOS_UNICORE
+    delay(1);  // Fix solo WDT
+#endif
+  }
+  return written;
 }
 
-void UpdateClass::printError(Print &out){
-    out.println(_err2str(_error));
+void UpdateClass::printError(Print &out) {
+  out.println(_err2str(_error));
 }
 
-const char * UpdateClass::errorString(){
-    return _err2str(_error);
+const char *UpdateClass::errorString() {
+  return _err2str(_error);
+}
+
+bool UpdateClass::_chkDataInBlock(const uint8_t *data, size_t len) const {
+  // check 32-bit aligned blocks only
+  if (!len || len % sizeof(uint32_t)) {
+    return true;
+  }
+
+  size_t dwl = len / sizeof(uint32_t);
+
+  do {
+    if (*(uint32_t *)data ^ 0xffffffff) {  // for SPI NOR flash empty blocks are all one's, i.e. filled with 0xff byte
+      return true;
+    }
+
+    data += sizeof(uint32_t);
+  } while (--dwl);
+  return false;
 }
 
+#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_UPDATE)
 UpdateClass Update;
+#endif
diff --git a/libraries/WebServer/examples/AdvancedWebServer/AdvancedWebServer.ino b/libraries/WebServer/examples/AdvancedWebServer/AdvancedWebServer.ino
index 88ad6c8a08d..eb805d27334 100644
--- a/libraries/WebServer/examples/AdvancedWebServer/AdvancedWebServer.ino
+++ b/libraries/WebServer/examples/AdvancedWebServer/AdvancedWebServer.ino
@@ -29,7 +29,7 @@
 */
 
 #include <WiFi.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 #include <WebServer.h>
 #include <ESPmDNS.h>
 
@@ -44,12 +44,14 @@ void handleRoot() {
   digitalWrite(led, 1);
   char temp[400];
   int sec = millis() / 1000;
-  int min = sec / 60;
-  int hr = min / 60;
+  int hr = sec / 3600;
+  int min = (sec / 60) % 60;
+  sec = sec % 60;
 
-  snprintf(temp, 400,
+  snprintf(
+    temp, 400,
 
-           "<html>\
+    "<html>\
   <head>\
     <meta http-equiv='refresh' content='5'/>\
     <title>ESP32 Demo</title>\
@@ -64,8 +66,8 @@ void handleRoot() {
   </body>\
 </html>",
 
-           hr, min % 60, sec % 60
-          );
+    hr, min, sec
+  );
   server.send(200, "text/html", temp);
   digitalWrite(led, 0);
 }
@@ -125,6 +127,7 @@ void setup(void) {
 
 void loop(void) {
   server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
 }
 
 void drawGraph() {
diff --git a/libraries/WebServer/examples/AdvancedWebServer/ci.json b/libraries/WebServer/examples/AdvancedWebServer/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/AdvancedWebServer/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/FSBrowser/FSBrowser.ino b/libraries/WebServer/examples/FSBrowser/FSBrowser.ino
index f49ae81c158..4c6f89562b8 100644
--- a/libraries/WebServer/examples/FSBrowser/FSBrowser.ino
+++ b/libraries/WebServer/examples/FSBrowser/FSBrowser.ino
@@ -23,14 +23,14 @@
   edit the page by going to http://esp32fs.local/edit
 */
 #include <WiFi.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 #include <WebServer.h>
 #include <ESPmDNS.h>
 
 #define FILESYSTEM SPIFFS
 // You only need to format the filesystem once
 #define FORMAT_FILESYSTEM false
-#define DBG_OUTPUT_PORT Serial
+#define DBG_OUTPUT_PORT   Serial
 
 #if FILESYSTEM == FFat
 #include <FFat.h>
@@ -39,9 +39,9 @@
 #include <SPIFFS.h>
 #endif
 
-const char* ssid = "wifi-ssid";
-const char* password = "wifi-password";
-const char* host = "esp32fs";
+const char *ssid = "wifi-ssid";
+const char *password = "wifi-password";
+const char *host = "esp32fs";
 WebServer server(80);
 //holds the current upload
 File fsUploadFile;
@@ -90,10 +90,10 @@ String getContentType(String filename) {
   return "text/plain";
 }
 
-bool exists(String path){
+bool exists(String path) {
   bool yes = false;
   File file = FILESYSTEM.open(path, "r");
-  if(!file.isDirectory()){
+  if (!file.isDirectory()) {
     yes = true;
   }
   file.close();
@@ -123,13 +123,14 @@ void handleFileUpload() {
   if (server.uri() != "/edit") {
     return;
   }
-  HTTPUpload& upload = server.upload();
+  HTTPUpload &upload = server.upload();
   if (upload.status == UPLOAD_FILE_START) {
     String filename = upload.filename;
     if (!filename.startsWith("/")) {
       filename = "/" + filename;
     }
-    DBG_OUTPUT_PORT.print("handleFileUpload Name: "); DBG_OUTPUT_PORT.println(filename);
+    DBG_OUTPUT_PORT.print("handleFileUpload Name: ");
+    DBG_OUTPUT_PORT.println(filename);
     fsUploadFile = FILESYSTEM.open(filename, "w");
     filename = String();
   } else if (upload.status == UPLOAD_FILE_WRITE) {
@@ -141,7 +142,8 @@ void handleFileUpload() {
     if (fsUploadFile) {
       fsUploadFile.close();
     }
-    DBG_OUTPUT_PORT.print("handleFileUpload Size: "); DBG_OUTPUT_PORT.println(upload.totalSize);
+    DBG_OUTPUT_PORT.print("handleFileUpload Size: ");
+    DBG_OUTPUT_PORT.println(upload.totalSize);
   }
 }
 
@@ -193,24 +195,23 @@ void handleFileList() {
   String path = server.arg("dir");
   DBG_OUTPUT_PORT.println("handleFileList: " + path);
 
-
   File root = FILESYSTEM.open(path);
   path = String();
 
   String output = "[";
-  if(root.isDirectory()){
-      File file = root.openNextFile();
-      while(file){
-          if (output != "[") {
-            output += ',';
-          }
-          output += "{\"type\":\"";
-          output += (file.isDirectory()) ? "dir" : "file";
-          output += "\",\"name\":\"";
-          output += String(file.name()).substring(1);
-          output += "\"}";
-          file = root.openNextFile();
+  if (root.isDirectory()) {
+    File file = root.openNextFile();
+    while (file) {
+      if (output != "[") {
+        output += ',';
       }
+      output += "{\"type\":\"";
+      output += (file.isDirectory()) ? "dir" : "file";
+      output += "\",\"name\":\"";
+      output += String(file.path()).substring(1);
+      output += "\"}";
+      file = root.openNextFile();
+    }
   }
   output += "]";
   server.send(200, "text/json", output);
@@ -220,21 +221,22 @@ void setup(void) {
   DBG_OUTPUT_PORT.begin(115200);
   DBG_OUTPUT_PORT.print("\n");
   DBG_OUTPUT_PORT.setDebugOutput(true);
-  if (FORMAT_FILESYSTEM) FILESYSTEM.format();
+  if (FORMAT_FILESYSTEM) {
+    FILESYSTEM.format();
+  }
   FILESYSTEM.begin();
   {
-      File root = FILESYSTEM.open("/");
-      File file = root.openNextFile();
-      while(file){
-          String fileName = file.name();
-          size_t fileSize = file.size();
-          DBG_OUTPUT_PORT.printf("FS File: %s, size: %s\n", fileName.c_str(), formatBytes(fileSize).c_str());
-          file = root.openNextFile();
-      }
-      DBG_OUTPUT_PORT.printf("\n");
+    File root = FILESYSTEM.open("/");
+    File file = root.openNextFile();
+    while (file) {
+      String fileName = file.name();
+      size_t fileSize = file.size();
+      DBG_OUTPUT_PORT.printf("FS File: %s, size: %s\n", fileName.c_str(), formatBytes(fileSize).c_str());
+      file = root.openNextFile();
+    }
+    DBG_OUTPUT_PORT.printf("\n");
   }
 
-
   //WIFI INIT
   DBG_OUTPUT_PORT.printf("Connecting to %s\n", ssid);
   if (String(WiFi.SSID()) != String(ssid)) {
@@ -255,7 +257,6 @@ void setup(void) {
   DBG_OUTPUT_PORT.print(host);
   DBG_OUTPUT_PORT.println(".local/edit to see the file browser");
 
-
   //SERVER INIT
   //list directory
   server.on("/list", HTTP_GET, handleFileList);
@@ -271,9 +272,13 @@ void setup(void) {
   server.on("/edit", HTTP_DELETE, handleFileDelete);
   //first callback is called after the request has ended with all parsed arguments
   //second callback handles file uploads at that location
-  server.on("/edit", HTTP_POST, []() {
-    server.send(200, "text/plain", "");
-  }, handleFileUpload);
+  server.on(
+    "/edit", HTTP_POST,
+    []() {
+      server.send(200, "text/plain", "");
+    },
+    handleFileUpload
+  );
 
   //called when the url is not defined here
   //use it to load content from FILESYSTEM
@@ -295,9 +300,9 @@ void setup(void) {
   });
   server.begin();
   DBG_OUTPUT_PORT.println("HTTP server started");
-
 }
 
 void loop(void) {
   server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
 }
diff --git a/libraries/WebServer/examples/FSBrowser/ci.json b/libraries/WebServer/examples/FSBrowser/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/FSBrowser/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/FSBrowser/data/index.htm b/libraries/WebServer/examples/FSBrowser/data/index.htm
index 9cb560cb0b0..36858db6043 100644
--- a/libraries/WebServer/examples/FSBrowser/data/index.htm
+++ b/libraries/WebServer/examples/FSBrowser/data/index.htm
@@ -1,8 +1,8 @@
-<!-- 
+<!--
   FSWebServer - Example Index Page
   Copyright (c) 2015 Hristo Gochkov. All rights reserved.
   This file is part of the WebServer library for Arduino environment.
- 
+
   This library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
@@ -25,7 +25,7 @@
     var heap,temp,digi;
     var reloadPeriod = 1000;
     var running = false;
-    
+
     function loadValues(){
       if(!running) return;
       var xh = new XMLHttpRequest();
@@ -43,14 +43,14 @@
       xh.open("GET", "/all", true);
       xh.send(null);
     };
-    
+
     function run(){
       if(!running){
         running = true;
         loadValues();
       }
     }
-    
+
     function onBodyLoad(){
       var refreshInput = document.getElementById("refresh-rate");
       refreshInput.value = reloadPeriod;
@@ -67,7 +67,7 @@
       startButton.onclick = function(e){
         run();
       }
-      
+
       // Example with 10K thermistor
       //function calcThermistor(v) {
       //  var t = Math.log(((10230000 / v) - 10000));
@@ -75,7 +75,7 @@
       //  return (t>120)?0:Math.round(t*10)/10;
       //}
       //temp = createGraph(document.getElementById("analog"), "Temperature", 100, 128, 10, 40, false, "cyan", calcThermistor);
-      
+
       temp = createGraph(document.getElementById("analog"), "Analog Input", 100, 128, 0, 1023, false, "cyan");
       heap = createGraph(document.getElementById("heap"), "Current Heap", 100, 125, 0, 30000, true, "orange");
       digi = createDigiGraph(document.getElementById("digital"), "GPIO", 100, 146, [0, 4, 5, 16], "gold");
@@ -94,4 +94,4 @@
   <div id="analog"></div>
   <div id="digital"></div>
 </body>
-</html>
\ No newline at end of file
+</html>
diff --git a/libraries/WebServer/examples/Filters/Filters.ino b/libraries/WebServer/examples/Filters/Filters.ino
new file mode 100644
index 00000000000..8974e55d322
--- /dev/null
+++ b/libraries/WebServer/examples/Filters/Filters.ino
@@ -0,0 +1,110 @@
+#include <WiFi.h>
+#include <NetworkClient.h>
+#include <WebServer.h>
+#include <ESPmDNS.h>
+
+// Your STA WiFi Credentials
+// ( This is the AP your ESP will connect to )
+const char *ssid = "........";
+const char *password = "........";
+
+// Your AP WiFi Credentials
+// ( This is the AP your ESP will broadcast )
+const char *ap_ssid = "ESP32_Demo";
+const char *ap_password = "";
+
+WebServer server(80);
+
+const int led = 13;
+
+// ON_STA_FILTER - Only accept requests coming from STA interface
+bool ON_STA_FILTER(WebServer &server) {
+  return WiFi.STA.hasIP() && WiFi.STA.localIP() == server.client().localIP();
+}
+
+// ON_AP_FILTER - Only accept requests coming from AP interface
+bool ON_AP_FILTER(WebServer &server) {
+  return WiFi.AP.hasIP() && WiFi.AP.localIP() == server.client().localIP();
+}
+
+void handleNotFound() {
+  digitalWrite(led, 1);
+  String message = "File Not Found\n\n";
+  message += "URI: ";
+  message += server.uri();
+  message += "\nMethod: ";
+  message += (server.method() == HTTP_GET) ? "GET" : "POST";
+  message += "\nArguments: ";
+  message += server.args();
+  message += "\n";
+  for (uint8_t i = 0; i < server.args(); i++) {
+    message += " " + server.argName(i) + ": " + server.arg(i) + "\n";
+  }
+  server.send(404, "text/plain", message);
+  digitalWrite(led, 0);
+}
+
+void setup(void) {
+  pinMode(led, OUTPUT);
+  digitalWrite(led, 0);
+  Serial.begin(115200);
+  WiFi.mode(WIFI_AP_STA);
+  // Connect to STA
+  WiFi.begin(ssid, password);
+  // Start AP
+  WiFi.softAP(ap_ssid, ap_password);
+  Serial.println("");
+
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("");
+  Serial.print("Connected to ");
+  Serial.println(ssid);
+  Serial.print("IP address: ");
+  Serial.println(WiFi.localIP());
+
+  if (MDNS.begin("esp32")) {
+    Serial.println("MDNS responder started");
+  }
+
+  // This route will be accessible by STA clients only
+  server
+    .on(
+      "/",
+      [&]() {
+        digitalWrite(led, 1);
+        server.send(200, "text/plain", "Hi!, This route is accessible for STA clients only");
+        digitalWrite(led, 0);
+      }
+    )
+    .setFilter(ON_STA_FILTER);
+
+  // This route will be accessible by AP clients only
+  server
+    .on(
+      "/",
+      [&]() {
+        digitalWrite(led, 1);
+        server.send(200, "text/plain", "Hi!, This route is accessible for AP clients only");
+        digitalWrite(led, 0);
+      }
+    )
+    .setFilter(ON_AP_FILTER);
+
+  server.on("/inline", []() {
+    server.send(200, "text/plain", "this works as well");
+  });
+
+  server.onNotFound(handleNotFound);
+
+  server.begin();
+  Serial.println("HTTP server started");
+}
+
+void loop(void) {
+  server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
+}
diff --git a/libraries/WebServer/examples/Filters/ci.json b/libraries/WebServer/examples/Filters/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/Filters/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/HelloServer/HelloServer.ino b/libraries/WebServer/examples/HelloServer/HelloServer.ino
index 1a1180c2593..3cf8a73df7d 100644
--- a/libraries/WebServer/examples/HelloServer/HelloServer.ino
+++ b/libraries/WebServer/examples/HelloServer/HelloServer.ino
@@ -1,10 +1,10 @@
 #include <WiFi.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 #include <WebServer.h>
 #include <ESPmDNS.h>
 
-const char* ssid = "........";
-const char* password = "........";
+const char *ssid = "........";
+const char *password = "........";
 
 WebServer server(80);
 
@@ -70,4 +70,5 @@ void setup(void) {
 
 void loop(void) {
   server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
 }
diff --git a/libraries/WebServer/examples/HelloServer/ci.json b/libraries/WebServer/examples/HelloServer/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/HelloServer/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/HttpAdvancedAuth/HttpAdvancedAuth.ino b/libraries/WebServer/examples/HttpAdvancedAuth/HttpAdvancedAuth.ino
index 567fd487863..7d984d98708 100644
--- a/libraries/WebServer/examples/HttpAdvancedAuth/HttpAdvancedAuth.ino
+++ b/libraries/WebServer/examples/HttpAdvancedAuth/HttpAdvancedAuth.ino
@@ -9,15 +9,15 @@
 #include <ArduinoOTA.h>
 #include <WebServer.h>
 
-const char* ssid = "........";
-const char* password = "........";
+const char *ssid = "........";
+const char *password = "........";
 
 WebServer server(80);
 
-const char* www_username = "admin";
-const char* www_password = "esp32";
+const char *www_username = "admin";
+const char *www_password = "esp32";
 // allows you to set the realm of authentication Default:"Login Required"
-const char* www_realm = "Custom Auth Realm";
+const char *www_realm = "Custom Auth Realm";
 // the Content of the HTML response in case of Unautherized Access Default:empty
 String authFailResponse = "Authentication Failed";
 
@@ -34,13 +34,13 @@ void setup() {
 
   server.on("/", []() {
     if (!server.authenticate(www_username, www_password))
-      //Basic Auth Method with Custom realm and Failure Response
-      //return server.requestAuthentication(BASIC_AUTH, www_realm, authFailResponse);
-      //Digest Auth Method with realm="Login Required" and empty Failure Response
-      //return server.requestAuthentication(DIGEST_AUTH);
-      //Digest Auth Method with Custom realm and empty Failure Response
-      //return server.requestAuthentication(DIGEST_AUTH, www_realm);
-      //Digest Auth Method with Custom realm and Failure Response
+    //Basic Auth Method with Custom realm and Failure Response
+    //return server.requestAuthentication(BASIC_AUTH, www_realm, authFailResponse);
+    //Digest Auth Method with realm="Login Required" and empty Failure Response
+    //return server.requestAuthentication(DIGEST_AUTH);
+    //Digest Auth Method with Custom realm and empty Failure Response
+    //return server.requestAuthentication(DIGEST_AUTH, www_realm);
+    //Digest Auth Method with Custom realm and Failure Response
     {
       return server.requestAuthentication(DIGEST_AUTH, www_realm, authFailResponse);
     }
@@ -56,4 +56,5 @@ void setup() {
 void loop() {
   ArduinoOTA.handle();
   server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
 }
diff --git a/libraries/WebServer/examples/HttpAdvancedAuth/ci.json b/libraries/WebServer/examples/HttpAdvancedAuth/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/HttpAdvancedAuth/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/HttpAuthCallback/HttpAuthCallback.ino b/libraries/WebServer/examples/HttpAuthCallback/HttpAuthCallback.ino
new file mode 100644
index 00000000000..0d3bca1a720
--- /dev/null
+++ b/libraries/WebServer/examples/HttpAuthCallback/HttpAuthCallback.ino
@@ -0,0 +1,60 @@
+#include <WiFi.h>
+#include <ESPmDNS.h>
+#include <ArduinoOTA.h>
+#include <WebServer.h>
+
+const char *ssid = "........";
+const char *password = "........";
+
+WebServer server(80);
+
+typedef struct credentials_t {
+  String username;
+  String password;
+} credentials_t;
+
+credentials_t passwdfile[] = {
+  {"admin", "esp32"}, {"fred", "41234123"}, {"charlie", "sdfsd"}, {"alice", "vambdnkuhj"}, {"bob", "svcdbjhws12"},
+};
+const size_t N_CREDENTIALS = sizeof(passwdfile) / sizeof(credentials_t);
+
+String *credentialsHandler(HTTPAuthMethod mode, String username, String params[]) {
+  for (int i = 0; i < N_CREDENTIALS; i++) {
+    if (username == passwdfile[i].username) {
+      return new String(passwdfile[i].password);
+    }
+  }
+  return NULL;
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(ssid, password);
+  if (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("WiFi Connect Failed! Rebooting...");
+    delay(1000);
+    ESP.restart();
+  }
+  ArduinoOTA.begin();
+
+  server.on("/", []() {
+    if (!server.authenticate(&credentialsHandler)) {
+      server.requestAuthentication();
+      return;
+    }
+    server.send(200, "text/plain", "Login OK");
+  });
+  server.begin();
+
+  Serial.print("Open http://");
+  Serial.print(WiFi.localIP());
+  Serial.println("/ in your browser to see it working");
+}
+
+void loop() {
+  ArduinoOTA.handle();
+  server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
+}
diff --git a/libraries/WebServer/examples/HttpAuthCallback/ci.json b/libraries/WebServer/examples/HttpAuthCallback/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/HttpAuthCallback/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/HttpAuthCallbackInline/HttpAuthCallbackInline.ino b/libraries/WebServer/examples/HttpAuthCallbackInline/HttpAuthCallbackInline.ino
new file mode 100644
index 00000000000..bcf78a9ce65
--- /dev/null
+++ b/libraries/WebServer/examples/HttpAuthCallbackInline/HttpAuthCallbackInline.ino
@@ -0,0 +1,59 @@
+#include <WiFi.h>
+#include <ESPmDNS.h>
+#include <ArduinoOTA.h>
+#include <WebServer.h>
+
+const char *ssid = "........";
+const char *password = "........";
+
+WebServer server(80);
+
+typedef struct credentials_t {
+  const char *username;
+  const char *password;
+} credentials_t;
+
+credentials_t passwdfile[] = {{"admin", "esp32"}, {"fred", "41234123"}, {"charlie", "sdfsd"}, {"alice", "vambdnkuhj"}, {"bob", "svcdbjhws12"}, {NULL, NULL}};
+
+void setup() {
+  Serial.begin(115200);
+
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(ssid, password);
+  if (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("WiFi Connect Failed! Rebooting...");
+    delay(1000);
+    ESP.restart();
+  }
+  ArduinoOTA.begin();
+
+  server.on("/", []() {
+    if (!server.authenticate([](HTTPAuthMethod mode, String username, String params[]) -> String * {
+          // Scan the password list for the username and return the password if
+          // we find the username.
+          //
+          for (credentials_t *entry = passwdfile; entry->username; entry++) {
+            if (username == entry->username) {
+              return new String(entry->password);
+            };
+          };
+          // we've not found the user in the list.
+          return NULL;
+        })) {
+      server.requestAuthentication();
+      return;
+    }
+    server.send(200, "text/plain", "Login OK");
+  });
+  server.begin();
+
+  Serial.print("Open http://");
+  Serial.print(WiFi.localIP());
+  Serial.println("/ in your browser to see it working");
+}
+
+void loop() {
+  ArduinoOTA.handle();
+  server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
+}
diff --git a/libraries/WebServer/examples/HttpAuthCallbackInline/ci.json b/libraries/WebServer/examples/HttpAuthCallbackInline/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/HttpAuthCallbackInline/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/HttpBasicAuth/HttpBasicAuth.ino b/libraries/WebServer/examples/HttpBasicAuth/HttpBasicAuth.ino
index 7a7dcc9a5e3..f4d71f14a24 100644
--- a/libraries/WebServer/examples/HttpBasicAuth/HttpBasicAuth.ino
+++ b/libraries/WebServer/examples/HttpBasicAuth/HttpBasicAuth.ino
@@ -3,13 +3,13 @@
 #include <ArduinoOTA.h>
 #include <WebServer.h>
 
-const char* ssid = "........";
-const char* password = "........";
+const char *ssid = "........";
+const char *password = "........";
 
 WebServer server(80);
 
-const char* www_username = "admin";
-const char* www_password = "esp32";
+const char *www_username = "admin";
+const char *www_password = "esp32";
 
 void setup() {
   Serial.begin(115200);
@@ -38,4 +38,5 @@ void setup() {
 void loop() {
   ArduinoOTA.handle();
   server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
 }
diff --git a/libraries/WebServer/examples/HttpBasicAuth/ci.json b/libraries/WebServer/examples/HttpBasicAuth/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/HttpBasicAuth/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/HttpBasicAuthSHA1/HttpBasicAuthSHA1.ino b/libraries/WebServer/examples/HttpBasicAuthSHA1/HttpBasicAuthSHA1.ino
new file mode 100644
index 00000000000..643a05380e9
--- /dev/null
+++ b/libraries/WebServer/examples/HttpBasicAuthSHA1/HttpBasicAuthSHA1.ino
@@ -0,0 +1,72 @@
+#include <WiFi.h>
+#include <ESPmDNS.h>
+#include <ArduinoOTA.h>
+#include <WebServer.h>
+
+// Rather than specify the password as plaintext; we
+// provide it as an (unsalted!) SHA1 hash. This is not
+// much more secure (SHA1 is past its retirement age,
+// and long obsolete/insecure) - but it helps a little.
+
+const char *ssid = "........";
+const char *password = "........";
+
+WebServer server(80);
+
+// Passwords as plaintext - human readable and easily visible in
+// the sourcecode and in the firmware/binary.
+const char *www_username = "admin";
+const char *www_password = "esp32";
+
+// The sha1 of 'esp32' (without the trailing \0) expressed as 20
+// bytes of hex. Created by for example 'echo -n esp32 | openssl sha1'
+// or http://www.sha1-online.com.
+const char *www_username_hex = "hexadmin";
+const char *www_password_hex = "8cb124f8c277c16ec0b2ee00569fd151a08e342b";
+
+// The same; but now expressed as a base64 string (e.g. as commonly used
+// by webservers). Created by ` echo -n esp32 | openssl sha1 -binary | openssl base64`
+const char *www_username_base64 = "base64admin";
+const char *www_password_base64 = "jLEk+MJ3wW7Asu4AVp/RUaCONCs=";
+
+void setup() {
+  Serial.begin(115200);
+
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(ssid, password);
+  if (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("WiFi Connect Failed! Rebooting...");
+    delay(1000);
+    ESP.restart();
+  }
+  ArduinoOTA.begin();
+
+  server.on("/", []() {
+    if (server.authenticate(www_username, www_password)) {
+      server.send(200, "text/plain", "Login against cleartext password OK");
+      return;
+    }
+    if (server.authenticateBasicSHA1(www_username_hex, www_password_hex)) {
+      server.send(200, "text/plain", "Login against HEX of the SHA1 of the password OK");
+      return;
+    }
+    if (server.authenticateBasicSHA1(www_username_base64, www_password_base64)) {
+      server.send(200, "text/plain", "Login against Base64 of the SHA1 of the password OK");
+      return;
+    }
+    Serial.println("No/failed authentication");
+    return server.requestAuthentication();
+  });
+
+  server.begin();
+
+  Serial.print("Open http://");
+  Serial.print(WiFi.localIP());
+  Serial.println("/ in your browser to see it working");
+}
+
+void loop() {
+  ArduinoOTA.handle();
+  server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
+}
diff --git a/libraries/WebServer/examples/HttpBasicAuthSHA1/ci.json b/libraries/WebServer/examples/HttpBasicAuthSHA1/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/HttpBasicAuthSHA1/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/HttpBasicAuthSHA1orBearerToken.ino b/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/HttpBasicAuthSHA1orBearerToken.ino
new file mode 100644
index 00000000000..89933a4ddb2
--- /dev/null
+++ b/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/HttpBasicAuthSHA1orBearerToken.ino
@@ -0,0 +1,118 @@
+#include <WiFi.h>
+#include <ESPmDNS.h>
+#include <ArduinoOTA.h>
+#include <WebServer.h>
+#include <SHA1Builder.h>
+
+// We have two options - we either come in with a bearer
+// token - i.e. a special header or API token; or we
+// get a normal HTTP style basic auth prompt.
+//
+// To do a bearer fetch - use something like Swagger or with curl:
+//
+//    curl https://myesp.com/  -H "Authorization: Bearer SecritToken"
+//
+// We avoid hardcoding this "SecritToken" into the code by
+// using a SHA1 instead (which is not particularly secure).
+
+// Create the secret token SHA1 with:
+//        echo -n SecritToken | openssl sha1
+
+String secret_token_hex = "d2cce6b472959484a21c3194080c609b8a2c910b";
+
+// Wifi credentials
+
+const char *ssid = "........";
+const char *password = "........";
+
+WebServer server(80);
+
+// Rather than specify the admin password as plaintext; we
+// provide it as an (unsalted!) SHA1 hash. This is not
+// much more secure (SHA1 is past its retirement age,
+// and long obsolete/insecure) - but it helps a little.
+
+// The sha1 of 'esp32' (without the trailing \0) expressed as 20
+// bytes of hex. Created by for example 'echo -n esp32 | openssl sha1'
+// or http://www.sha1-online.com.
+const char *www_username_hex = "admin";
+const char *www_password_hex = "8cb124f8c277c16ec0b2ee00569fd151a08e342b";
+
+static unsigned char _bearer[20];
+
+String *check_bearer_or_auth(HTTPAuthMethod mode, String authReq, String params[]) {
+  // we expect authReq to be "bearer some-secret"
+  String lcAuthReq = authReq;
+  lcAuthReq.toLowerCase();
+  if (mode == OTHER_AUTH && (lcAuthReq.startsWith("bearer "))) {
+    String secret = authReq.substring(7);
+    secret.trim();
+
+    uint8_t sha1[20];
+    SHA1Builder sha_builder;
+
+    sha_builder.begin();
+    sha_builder.add((uint8_t *)secret.c_str(), secret.length());
+    sha_builder.calculate();
+    sha_builder.getBytes(sha1);
+
+    if (memcmp(_bearer, sha1, sizeof(_bearer)) == 0) {
+      Serial.println("Bearer token matches");
+      return new String("anything non null");
+    } else {
+      Serial.println("Bearer token does not match");
+    }
+  } else if (mode == BASIC_AUTH) {
+    bool ret = server.authenticateBasicSHA1(www_username_hex, www_password_hex);
+    if (ret) {
+      Serial.println("Basic auth succeeded");
+      return new String(params[0]);
+    } else {
+      Serial.println("Basic auth failed");
+    }
+  }
+
+  // No auth found
+  return NULL;
+};
+
+void setup() {
+  Serial.begin(115200);
+
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(ssid, password);
+  if (WiFi.waitForConnectResult() != WL_CONNECTED) {
+    Serial.println("WiFi Connect Failed! Rebooting...");
+    delay(1000);
+    ESP.restart();
+  }
+  ArduinoOTA.begin();
+
+  // Convert token to a convenient binary representation.
+  size_t len = HEXBuilder::hex2bytes(_bearer, sizeof(_bearer), secret_token_hex);
+  if (len != 20) {
+    Serial.println("Bearer token does not look like a valid SHA1 hex string ?!");
+  }
+
+  server.on("/", []() {
+    if (!server.authenticate(&check_bearer_or_auth)) {
+      Serial.println("No/failed authentication");
+      return server.requestAuthentication();
+    }
+    Serial.println("Authentication succeeded");
+    server.send(200, "text/plain", "Login OK");
+    return;
+  });
+
+  server.begin();
+
+  Serial.print("Open http://");
+  Serial.print(WiFi.localIP());
+  Serial.println("/ in your browser to see it working");
+}
+
+void loop() {
+  ArduinoOTA.handle();
+  server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
+}
diff --git a/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/ci.json b/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/HttpBasicAuthSHA1orBearerToken/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/Middleware/Middleware.ino b/libraries/WebServer/examples/Middleware/Middleware.ino
new file mode 100644
index 00000000000..9d957341c2d
--- /dev/null
+++ b/libraries/WebServer/examples/Middleware/Middleware.ino
@@ -0,0 +1,186 @@
+/**
+ * Basic example of using Middlewares with WebServer
+ *
+ * Middleware are common request/response processing functions that can be applied globally to all incoming requests or to specific handlers.
+ * They allow for a common processing thus saving memory and space to avoid duplicating code or states on multiple handlers.
+ *
+ * Once the example is flashed (with the correct WiFi credentials), you can test the following scenarios with the listed curl commands:
+ * - CORS Middleware: answers to OPTIONS requests with the specified CORS headers and also add CORS headers to the response when the request has the Origin header
+ * - Logging Middleware: logs the request and response to an output in a curl-like format
+ * - Authentication Middleware: test the authentication with Digest Auth
+ *
+ * You can also add your own Middleware by extending the Middleware class and implementing the run method.
+ * When implementing a Middleware, you can decide when to call the next Middleware in the chain by calling next().
+ *
+ * Middleware are execute in order of addition, the ones attached to the server will be executed first.
+ */
+#include <WiFi.h>
+#include <WebServer.h>
+#include <Middlewares.h>
+
+// Your AP WiFi Credentials
+// ( This is the AP your ESP will broadcast )
+const char *ap_ssid = "ESP32_Demo";
+const char *ap_password = "";
+
+WebServer server(80);
+
+LoggingMiddleware logger;
+CorsMiddleware cors;
+AuthenticationMiddleware auth;
+
+void setup(void) {
+  Serial.begin(115200);
+  WiFi.softAP(ap_ssid, ap_password);
+
+  Serial.print("IP address: ");
+  Serial.println(WiFi.AP.localIP());
+
+  // curl-like output example:
+  //
+  // > curl -v -X OPTIONS -H "origin: http://192.168.4.1" http://192.168.4.1/
+  //
+  //  Connection from 192.168.4.2:51683
+  // > OPTIONS / HTTP/1.1
+  // > Host: 192.168.4.1
+  // > User-Agent: curl/8.10.0
+  // > Accept: */*
+  // > origin: http://192.168.4.1
+  // >
+  // * Processed in 5 ms
+  // < HTTP/1.HTTP/1.1 200 OK
+  // < Content-Type: text/html
+  // < Access-Control-Allow-Origin: http://192.168.4.1
+  // < Access-Control-Allow-Methods: POST,GET,OPTIONS,DELETE
+  // < Access-Control-Allow-Headers: X-Custom-Header
+  // < Access-Control-Allow-Credentials: false
+  // < Access-Control-Max-Age: 600
+  // < Content-Length: 0
+  // < Connection: close
+  // <
+  logger.setOutput(Serial);
+
+  cors.setOrigin("http://192.168.4.1");
+  cors.setMethods("POST,GET,OPTIONS,DELETE");
+  cors.setHeaders("X-Custom-Header");
+  cors.setAllowCredentials(false);
+  cors.setMaxAge(600);
+
+  auth.setUsername("admin");
+  auth.setPassword("admin");
+  auth.setRealm("My Super App");
+  auth.setAuthMethod(DIGEST_AUTH);
+  auth.setAuthFailureMessage("Authentication Failed");
+
+  server.addMiddleware(&logger);
+  server.addMiddleware(&cors);
+
+  // Not authenticated
+  //
+  // Test CORS preflight request with:
+  // > curl -v -X OPTIONS -H "origin: http://192.168.4.1" http://192.168.4.1/
+  //
+  // Test cross-domain request with:
+  // > curl -v -X GET -H "origin: http://192.168.4.1" http://192.168.4.1/
+  //
+  server.on("/", []() {
+    server.send(200, "text/plain", "Home");
+  });
+
+  // Authenticated
+  //
+  // > curl -v -X GET -H "origin: http://192.168.4.1"  http://192.168.4.1/protected
+  //
+  // Outputs:
+  //
+  // * Connection from 192.168.4.2:51750
+  // > GET /protected HTTP/1.1
+  // > Host: 192.168.4.1
+  // > User-Agent: curl/8.10.0
+  // > Accept: */*
+  // > origin: http://192.168.4.1
+  // >
+  // * Processed in 7 ms
+  // < HTTP/1.HTTP/1.1 401 Unauthorized
+  // < Content-Type: text/html
+  // < Access-Control-Allow-Origin: http://192.168.4.1
+  // < Access-Control-Allow-Methods: POST,GET,OPTIONS,DELETE
+  // < Access-Control-Allow-Headers: X-Custom-Header
+  // < Access-Control-Allow-Credentials: false
+  // < Access-Control-Max-Age: 600
+  // < WWW-Authenticate: Digest realm="My Super App", qop="auth", nonce="ac388a64184e3e102aae6fff1c9e8d76", opaque="e7d158f2b54d25328142d118ff0f932d"
+  // < Content-Length: 21
+  // < Connection: close
+  // <
+  //
+  // > curl -v -X GET -H "origin: http://192.168.4.1" --digest -u admin:admin  http://192.168.4.1/protected
+  //
+  // Outputs:
+  //
+  // * Connection from 192.168.4.2:53662
+  // > GET /protected HTTP/1.1
+  // > Authorization: Digest username="admin", realm="My Super App", nonce="db9e6824eb2a13bc7b2bf8f3c43db896", uri="/protected", cnonce="NTliZDZiNTcwODM2MzAyY2JjMDBmZGJmNzFiY2ZmNzk=", nc=00000001, qop=auth, response="6ebd145ba0d3496a4a73f5ae79ff5264", opaque="23d739c22810282ff820538cba98bda4"
+  // > Host: 192.168.4.1
+  // > User-Agent: curl/8.10.0
+  // > Accept: */*
+  // > origin: http://192.168.4.1
+  // >
+  // Request handling...
+  // * Processed in 7 ms
+  // < HTTP/1.HTTP/1.1 200 OK
+  // < Content-Type: text/plain
+  // < Access-Control-Allow-Origin: http://192.168.4.1
+  // < Access-Control-Allow-Methods: POST,GET,OPTIONS,DELETE
+  // < Access-Control-Allow-Headers: X-Custom-Header
+  // < Access-Control-Allow-Credentials: false
+  // < Access-Control-Max-Age: 600
+  // < Content-Length: 9
+  // < Connection: close
+  // <
+  server
+    .on(
+      "/protected",
+      []() {
+        Serial.println("Request handling...");
+        server.send(200, "text/plain", "Protected");
+      }
+    )
+    .addMiddleware(&auth);
+
+  // Not found is also handled by global middleware
+  //
+  // curl -v -X GET -H "origin: http://192.168.4.1" http://192.168.4.1/inexsting
+  //
+  // Outputs:
+  //
+  // * Connection from 192.168.4.2:53683
+  // > GET /inexsting HTTP/1.1
+  // > Host: 192.168.4.1
+  // > User-Agent: curl/8.10.0
+  // > Accept: */*
+  // > origin: http://192.168.4.1
+  // >
+  // * Processed in 16 ms
+  // < HTTP/1.HTTP/1.1 404 Not Found
+  // < Content-Type: text/plain
+  // < Access-Control-Allow-Origin: http://192.168.4.1
+  // < Access-Control-Allow-Methods: POST,GET,OPTIONS,DELETE
+  // < Access-Control-Allow-Headers: X-Custom-Header
+  // < Access-Control-Allow-Credentials: false
+  // < Access-Control-Max-Age: 600
+  // < Content-Length: 14
+  // < Connection: close
+  // <
+  server.onNotFound([]() {
+    server.send(404, "text/plain", "Page not found");
+  });
+
+  server.collectAllHeaders();
+  server.begin();
+  Serial.println("HTTP server started");
+}
+
+void loop(void) {
+  server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
+}
diff --git a/libraries/WebServer/examples/Middleware/ci.json b/libraries/WebServer/examples/Middleware/ci.json
new file mode 100644
index 00000000000..36babb82730
--- /dev/null
+++ b/libraries/WebServer/examples/Middleware/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/MultiHomedServers/MultiHomedServers.ino b/libraries/WebServer/examples/MultiHomedServers/MultiHomedServers.ino
new file mode 100644
index 00000000000..300a651e3b1
--- /dev/null
+++ b/libraries/WebServer/examples/MultiHomedServers/MultiHomedServers.ino
@@ -0,0 +1,141 @@
+#include <WiFi.h>
+#include <NetworkClient.h>
+#include <WebServer.h>
+#include <ESPmDNS.h>
+
+const char *ssid = "WiFi_SSID";
+const char *password = "WiFi_Password";
+const char *apssid = "ESP32";
+
+WebServer *server0, *server1, *server2;
+
+#ifdef LED_BUILTIN
+const int led = LED_BUILTIN;
+#else
+const int led = 13;
+#endif
+
+void handleRoot(WebServer *server, const char *content) {
+  digitalWrite(led, 1);
+  server->send(200, "text/plain", content);
+  digitalWrite(led, 0);
+}
+
+void handleRoot0() {
+  handleRoot(server0, "Hello from server0 who listens on both WLAN and own Soft AP");
+}
+
+void handleRoot1() {
+  handleRoot(server1, "Hello from server1 who listens only on WLAN");
+}
+
+void handleRoot2() {
+  handleRoot(server2, "Hello from server2 who listens only on own Soft AP");
+}
+
+void handleNotFound(WebServer *server) {
+  digitalWrite(led, 1);
+  String message = "File Not Found\n\n";
+  message += "URI: ";
+  message += server->uri();
+  message += "\nMethod: ";
+  message += (server->method() == HTTP_GET) ? "GET" : "POST";
+  message += "\nArguments: ";
+  message += server->args();
+  message += "\n";
+  for (uint8_t i = 0; i < server->args(); i++) {
+    message += " " + server->argName(i) + ": " + server->arg(i) + "\n";
+  }
+  server->send(404, "text/plain", message);
+  digitalWrite(led, 0);
+}
+
+void handleNotFound0() {
+  handleNotFound(server0);
+}
+
+void handleNotFound1() {
+  handleNotFound(server1);
+}
+
+void handleNotFound2() {
+  handleNotFound(server2);
+}
+
+void setup(void) {
+  pinMode(led, OUTPUT);
+  digitalWrite(led, 0);
+  Serial.begin(115200);
+
+  Serial.println("Multi-homed Servers example starting");
+  delay(1000);
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(ssid, password);
+  Serial.print("Connecting ");
+
+  // Wait for connection
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("");
+  Serial.print("Connected to \"");
+  Serial.print(ssid);
+  Serial.print("\", IP address: \"");
+  Serial.println(WiFi.localIP());
+  if (!WiFi.softAP(apssid)) {
+    Serial.println("failed to start softAP");
+    for (;;) {
+      digitalWrite(led, 1);
+      delay(100);
+      digitalWrite(led, 0);
+      delay(100);
+    }
+  }
+  Serial.print("Soft AP SSID: \"");
+  Serial.print(apssid);
+  Serial.print("\", IP address: ");
+  Serial.println(WiFi.softAPIP());
+
+  if (MDNS.begin("esp32")) {
+    Serial.println("MDNS responder started");
+  }
+
+  server0 = new WebServer(8080);
+  server1 = new WebServer(WiFi.localIP(), 8081);
+  server2 = new WebServer(WiFi.softAPIP(), 8081);
+
+  server0->on("/", handleRoot0);
+  server1->on("/", handleRoot1);
+  server2->on("/", handleRoot2);
+
+  server0->onNotFound(handleNotFound0);
+  server1->onNotFound(handleNotFound1);
+  server2->onNotFound(handleNotFound2);
+
+  server0->begin();
+  Serial.println("HTTP server0 started");
+  server1->begin();
+  Serial.println("HTTP server1 started");
+  server2->begin();
+  Serial.println("HTTP server2 started");
+
+  Serial.printf("SSID: %s\n\thttp://", ssid);
+  Serial.print(WiFi.localIP());
+  Serial.print(":8080\n\thttp://");
+  Serial.print(WiFi.localIP());
+  Serial.println(":8081");
+  Serial.printf("SSID: %s\n\thttp://", apssid);
+  Serial.print(WiFi.softAPIP());
+  Serial.print(":8080\n\thttp://");
+  Serial.print(WiFi.softAPIP());
+  Serial.println(":8081");
+  Serial.printf("Any of the above SSIDs\n\thttp://esp32.local:8080\n\thttp://esp32.local:8081\n");
+}
+
+void loop(void) {
+  server0->handleClient();
+  server1->handleClient();
+  server2->handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
+}
diff --git a/libraries/WebServer/examples/MultiHomedServers/README.md b/libraries/WebServer/examples/MultiHomedServers/README.md
new file mode 100644
index 00000000000..04b96dfbd53
--- /dev/null
+++ b/libraries/WebServer/examples/MultiHomedServers/README.md
@@ -0,0 +1,115 @@
+# Multi Homed Servers
+
+This example tests support for multi-homed servers, i.e. a distinct web servers on distinct IP interface.
+
+It only tests the case n=2 because on a basic ESP32 device, we only have two IP interfaces, namely the Wi-Fi station interfaces and the Wi-Fi soft AP interface.
+For this to work, the WebServer and the NetworkServer classes must correctly handle the case where an IP address is passed to their relevant constructor.
+It also requires WebServer to work with multiple, simultaneous instances.
+
+Testing the WebServer and the NetworkServer constructors was the primary purpose of this script.
+The part of WebServer used by this sketch does seem to work with multiple, simultaneous instances.
+However there is much functionality in WebServer that is not tested here. It may all be well, but that is not proven here.
+
+This sketch starts the mDNS server, as did HelloServer, and it resolves esp32.local on both interfaces, but was not otherwise tested.
+This script also tests that a server not bound to a specific IP address still works.
+
+We create three, simultaneous web servers, one specific to each interface and one that listens on both:
+
+| name    | IP Address      | Port |
+| ----    | ----------      | ---- |
+| server0 | INADDR_ANY      | 8080 |
+| server1 | station address | 8081 |
+| server2 | soft AP address | 8081 |
+
+The expected responses to a browser's requests are as follows:
+
+#### 1. The Client connected to the same WLAN as the station:
+
+| Request URL                | Response |
+| -----------                | -------- |
+| [http://stationaddress:8080](http://stationaddress:8080) | Hello from server0 who listens on both WLAN and own Soft AP |
+| [http://stationaddress:8081](http://stationaddress:8081) | Hello from server1 who listens only on WLAN |
+
+#### 2. The Client is connected to the soft AP:
+
+| Request URL               | Response |
+| -----------               | -------- |
+| [http://softAPaddress:8080](http://softAPaddress:8080) | Hello from server0 who listens on both WLAN and own Soft AP |
+| [http://softAPaddress:8081](http://softAPaddress:8081) | Hello from server2 who listens only on own Soft AP |
+
+#### 3. The Client is connect to either WLAN or SoftAP:
+
+| Request URL               | Response |
+| -----------               | -------- |
+| [http://esp32.local:8080](http://esp32.local:8080) | Hello from server0 who listens on both WLAN and own Soft AP |
+| [http://esp32.local:8081](http://esp32.local:8081) | Hello from server1 who listens only on WLAN |
+
+MultiHomedServers was originally based on HelloServer.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- |
+
+## How to Use Example
+
+Change the SSID and password in the example to your Wi-Fi and flash the example.
+Open a serial terminal and the example will write the exact addresses with used IP addresses you can use to test the servers.
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example Log Output
+
+```
+Multi-homed Servers example starting
+Connecting ...
+Connected to "WiFi_SSID", IP address: "192.168.42.24
+Soft AP SSID: "ESP32", IP address: 192.168.4.1
+MDNS responder started
+SSID: WiFi_SSID
+	http://192.168.42.24:8080
+	http://192.168.42.24:8081
+SSID: ESP32
+	http://192.168.4.1:8080
+	http://192.168.4.1:8081
+Any of the above SSIDs
+	http://esp32.local:8080
+	http://esp32.local:8081
+HTTP server0 started
+HTTP server1 started
+HTTP server2 started
+```
+
+## Known issues
+
+`http://esp32.local` Does not work on some Android phones
+
+## Troubleshooting
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/WebServer/examples/MultiHomedServers/ci.json b/libraries/WebServer/examples/MultiHomedServers/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/MultiHomedServers/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/PathArgServer/PathArgServer.ino b/libraries/WebServer/examples/PathArgServer/PathArgServer.ino
index 0b4dc425869..1debb1897df 100644
--- a/libraries/WebServer/examples/PathArgServer/PathArgServer.ino
+++ b/libraries/WebServer/examples/PathArgServer/PathArgServer.ino
@@ -1,5 +1,5 @@
 #include <WiFi.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 #include <WebServer.h>
 #include <ESPmDNS.h>
 
@@ -40,7 +40,7 @@ void setup(void) {
     String user = server.pathArg(0);
     server.send(200, "text/plain", "User: '" + user + "'");
   });
-  
+
   server.on(UriRegex("^\\/users\\/([0-9]+)\\/devices\\/([0-9]+)$"), []() {
     String user = server.pathArg(0);
     String device = server.pathArg(1);
@@ -53,4 +53,5 @@ void setup(void) {
 
 void loop(void) {
   server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
 }
diff --git a/libraries/WebServer/examples/PathArgServer/ci.json b/libraries/WebServer/examples/PathArgServer/ci.json
new file mode 100644
index 00000000000..cbdd28f773d
--- /dev/null
+++ b/libraries/WebServer/examples/PathArgServer/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/SDWebServer/SDWebServer.ino b/libraries/WebServer/examples/SDWebServer/SDWebServer.ino
index a3271a03740..23fcc3fb0a9 100644
--- a/libraries/WebServer/examples/SDWebServer/SDWebServer.ino
+++ b/libraries/WebServer/examples/SDWebServer/SDWebServer.ino
@@ -20,15 +20,17 @@
 
   Have a FAT Formatted SD Card connected to the SPI port of the ESP8266
   The web root is the SD Card root folder
-  File extensions with more than 3 charecters are not supported by the SD Library
-  File Names longer than 8 charecters will be truncated by the SD library, so keep filenames shorter
+  File extensions with more than 3 characters are not supported by the SD Library
+  File Names longer than 8 characters will be truncated by the SD library, so keep filenames shorter
   index.htm is the default index (works on subfolders as well)
 
   upload the contents of SdRoot to the root of the SDcard and access the editor by going to http://esp8266sd.local/edit
+  To retrieve the contents of SDcard, visit http://esp32sd.local/list?dir=/
+      dir is the argument that needs to be passed to the function PrintDirectory via HTTP Get request.
 
 */
 #include <WiFi.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 #include <WebServer.h>
 #include <ESPmDNS.h>
 #include <SPI.h>
@@ -36,16 +38,15 @@
 
 #define DBG_OUTPUT_PORT Serial
 
-const char* ssid = "**********";
-const char* password = "**********";
-const char* host = "esp32sd";
+const char *ssid = "**********";
+const char *password = "**********";
+const char *host = "esp32sd";
 
 WebServer server(80);
 
 static bool hasSD = false;
 File uploadFile;
 
-
 void returnOK() {
   server.send(200, "text/plain", "");
 }
@@ -111,23 +112,26 @@ void handleFileUpload() {
   if (server.uri() != "/edit") {
     return;
   }
-  HTTPUpload& upload = server.upload();
+  HTTPUpload &upload = server.upload();
   if (upload.status == UPLOAD_FILE_START) {
     if (SD.exists((char *)upload.filename.c_str())) {
       SD.remove((char *)upload.filename.c_str());
     }
     uploadFile = SD.open(upload.filename.c_str(), FILE_WRITE);
-    DBG_OUTPUT_PORT.print("Upload: START, filename: "); DBG_OUTPUT_PORT.println(upload.filename);
+    DBG_OUTPUT_PORT.print("Upload: START, filename: ");
+    DBG_OUTPUT_PORT.println(upload.filename);
   } else if (upload.status == UPLOAD_FILE_WRITE) {
     if (uploadFile) {
       uploadFile.write(upload.buf, upload.currentSize);
     }
-    DBG_OUTPUT_PORT.print("Upload: WRITE, Bytes: "); DBG_OUTPUT_PORT.println(upload.currentSize);
+    DBG_OUTPUT_PORT.print("Upload: WRITE, Bytes: ");
+    DBG_OUTPUT_PORT.println(upload.currentSize);
   } else if (upload.status == UPLOAD_FILE_END) {
     if (uploadFile) {
       uploadFile.close();
     }
-    DBG_OUTPUT_PORT.print("Upload: END, Size: "); DBG_OUTPUT_PORT.println(upload.totalSize);
+    DBG_OUTPUT_PORT.print("Upload: END, Size: ");
+    DBG_OUTPUT_PORT.println(upload.totalSize);
   }
 }
 
@@ -212,7 +216,6 @@ void printDirectory() {
   dir.rewindDirectory();
   server.setContentLength(CONTENT_LENGTH_UNKNOWN);
   server.send(200, "text/json", "");
-  WiFiClient client = server.client();
 
   server.sendContent("[");
   for (int cnt = 0; true; ++cnt) {
@@ -229,7 +232,7 @@ void printDirectory() {
     output += "{\"type\":\"";
     output += (entry.isDirectory()) ? "dir" : "file";
     output += "\",\"name\":\"";
-    output += entry.name();
+    output += entry.path();
     output += "\"";
     output += "}";
     server.sendContent(output);
@@ -269,7 +272,7 @@ void setup(void) {
 
   // Wait for connection
   uint8_t i = 0;
-  while (WiFi.status() != WL_CONNECTED && i++ < 20) {//wait 10 seconds
+  while (WiFi.status() != WL_CONNECTED && i++ < 20) {  //wait 10 seconds
     delay(500);
   }
   if (i == 21) {
@@ -290,13 +293,16 @@ void setup(void) {
     DBG_OUTPUT_PORT.println(".local");
   }
 
-
   server.on("/list", HTTP_GET, printDirectory);
   server.on("/edit", HTTP_DELETE, handleDelete);
   server.on("/edit", HTTP_PUT, handleCreate);
-  server.on("/edit", HTTP_POST, []() {
-    returnOK();
-  }, handleFileUpload);
+  server.on(
+    "/edit", HTTP_POST,
+    []() {
+      returnOK();
+    },
+    handleFileUpload
+  );
   server.onNotFound(handleNotFound);
 
   server.begin();
@@ -310,4 +316,5 @@ void setup(void) {
 
 void loop(void) {
   server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
 }
diff --git a/libraries/WebServer/examples/SDWebServer/SdRoot/edit/index.htm b/libraries/WebServer/examples/SDWebServer/SdRoot/edit/index.htm
index f535601e7d7..054846ff7b0 100644
--- a/libraries/WebServer/examples/SDWebServer/SdRoot/edit/index.htm
+++ b/libraries/WebServer/examples/SDWebServer/SdRoot/edit/index.htm
@@ -34,7 +34,7 @@
       }
       .contextMenu li:hover { background: #444; }
       .contextMenu li:hover span { color: #EEE; }
-    
+
       .css-treeview ul, .css-treeview li {
         padding: 0;
         margin: 0;
@@ -117,18 +117,18 @@
           -webkit-animation: webkit-adjacent-element-selector-bugfix infinite 1s;
         }
 
-        @-webkit-keyframes webkit-adjacent-element-selector-bugfix 
+        @-webkit-keyframes webkit-adjacent-element-selector-bugfix
         {
-          from  { 
+          from  {
             padding: 0;
-          } 
-          to  { 
+          }
+          to  {
             padding: 0;
           }
         }
       }
 
-      #uploader { 
+      #uploader {
         position: absolute;
         top: 0;
         right: 0;
@@ -139,7 +139,7 @@
         background-color: #444;
         color:#EEE;
       }
-      #tree { 
+      #tree {
         position: absolute;
         top: 28px;
         bottom: 0;
@@ -147,7 +147,7 @@
         width:200px;
         padding: 8px;
       }
-      #editor, #preview { 
+      #editor, #preview {
         position: absolute;
         top: 28px;
         right: 0;
@@ -182,7 +182,7 @@
         var mkfile = document.createElement("button");
         mkfile.innerHTML = 'MkFile';
         document.getElementById(element).appendChild(mkfile);
-  
+
         function httpPostProcessRequest(){
           if (xmlHttp.readyState == 4){
             if(xmlHttp.status != 200) alert("ERROR["+xmlHttp.status+"]: "+xmlHttp.responseText);
@@ -199,7 +199,7 @@
           xmlHttp.open("PUT", "/edit");
           xmlHttp.send(formData);
         }
-        
+
         mkfile.onclick = function(e){
           if(path.value.indexOf(".") === -1) return;
           createPath(path.value);
@@ -252,17 +252,17 @@
         var treeRoot = document.createElement("div");
         treeRoot.className = "css-treeview";
         document.getElementById(element).appendChild(treeRoot);
-  
+
         function loadDownload(path){
           document.getElementById('download-frame').src = path+"?download=true";
         }
-  
+
         function loadPreview(path){
           document.getElementById("editor").style.display = "none";
           preview.style.display = "block";
           preview.innerHTML = '<img src="'+path+'" style="max-width:100%; max-height:100%; margin:auto; display:block;" />';
         }
-  
+
         function fillFolderMenu(el, path){
           var list = document.createElement("ul");
           el.appendChild(list);
@@ -316,7 +316,7 @@
             if(document.body.getElementsByClassName('contextMenu').length > 0) document.body.removeChild(el);
           };
         }
-  
+
         function fillFileMenu(el, path){
           var list = document.createElement("ul");
           el.appendChild(list);
@@ -350,7 +350,7 @@
             if(document.body.getElementsByClassName('contextMenu').length > 0) document.body.removeChild(el);
           };
         }
-  
+
         function showContextMenu(e, path, isfile){
           var divContext = document.createElement("div");
           var scrollTop = document.body.scrollTop ? document.body.scrollTop : document.documentElement.scrollTop;
@@ -372,10 +372,10 @@
             }
           };
         }
-  
+
         function createTreeLeaf(path, name, size){
           var leaf = document.createElement("li");
-          leaf.id = (((path == "/")?"":path)+"/"+name).toLowerCase();
+          leaf.id = name.toLowerCase();
           var label = document.createElement("span");
           label.textContent = name.toLowerCase();
           leaf.appendChild(label);
@@ -393,12 +393,12 @@
           };
           return leaf;
         }
-  
+
         function createTreeBranch(path, name, disabled){
           var leaf = document.createElement("li");
           var check = document.createElement("input");
           check.type = "checkbox";
-          check.id = (((path == "/")?"":path)+"/"+name).toLowerCase();
+          check.id = name.toLowerCase();
           if(typeof disabled !== "undefined" && disabled) check.disabled = "disabled";
           leaf.appendChild(check);
           var label = document.createElement("label");
@@ -427,7 +427,7 @@
           }
           return leaf;
         }
-  
+
         function addList(parent, path, items){
           var list = document.createElement("ul");
           parent.appendChild(list);
@@ -442,9 +442,9 @@
             }
             list.appendChild(itemEl);
           }
-    
+
         }
-  
+
         function isTextFile(path){
           var ext = /(?:\.([^.]+))?$/.exec(path)[1];
           if(typeof ext !== undefined){
@@ -464,7 +464,7 @@
           }
           return false;
         }
-  
+
         function isImageFile(path){
           var ext = /(?:\.([^.]+))?$/.exec(path)[1];
           if(typeof ext !== undefined){
@@ -478,7 +478,7 @@
           }
           return false;
         }
-  
+
         this.refreshPath = function(path){
           if(path.lastIndexOf('/') < 1){
             path = '/';
@@ -491,7 +491,7 @@
             httpGet(leaf, path);
           }
         };
-  
+
         function delCb(path){
           return function(){
             if (xmlHttp.readyState == 4){
@@ -512,7 +512,7 @@
             }
           }
         }
-  
+
         function httpDelete(filename){
           xmlHttp = new XMLHttpRequest();
           xmlHttp.onreadystatechange = delCb(filename);
@@ -521,7 +521,7 @@
           xmlHttp.open("DELETE", "/edit");
           xmlHttp.send(formData);
         }
-  
+
         function getCb(parent, path){
           return function(){
             if (xmlHttp.readyState == 4){
@@ -530,7 +530,7 @@
             }
           }
         }
-  
+
         function httpGet(parent, path){
           xmlHttp = new XMLHttpRequest(parent, path);
           xmlHttp.onreadystatechange = getCb(parent, path);
@@ -538,7 +538,7 @@
           xmlHttp.send(null);
           //start loading
         }
-  
+
         httpGet(treeRoot, "/");
         return this;
       }
@@ -565,23 +565,23 @@
           }
           return lang;
         }
-  
+
         if(typeof file === "undefined") file = "/index.htm";
-  
+
         if(typeof lang === "undefined"){
           lang = getLangFromFilename(file);
         }
-  
+
         if(typeof theme === "undefined") theme = "textmate";
-  
+
         if(typeof type === "undefined"){
           type = "text/"+lang;
           if(lang === "c_cpp") type = "text/plain";
         }
-  
+
         var xmlHttp = null;
         var editor = ace.edit(element);
-  
+
         //post
         function httpPostProcessRequest(){
           if (xmlHttp.readyState == 4){
@@ -612,7 +612,7 @@
             xmlHttp.open("GET", theUrl, true);
             xmlHttp.send(null);
         }
-  
+
         if(lang !== "plain") editor.getSession().setMode("ace/mode/"+lang);
         editor.setTheme("ace/theme/"+theme);
         editor.$blockScrolling = Infinity;
diff --git a/libraries/WebServer/examples/SDWebServer/ci.json b/libraries/WebServer/examples/SDWebServer/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/SDWebServer/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/SimpleAuthentification/SimpleAuthentification.ino b/libraries/WebServer/examples/SimpleAuthentification/SimpleAuthentification.ino
index 1adf20613ad..210429225a1 100644
--- a/libraries/WebServer/examples/SimpleAuthentification/SimpleAuthentification.ino
+++ b/libraries/WebServer/examples/SimpleAuthentification/SimpleAuthentification.ino
@@ -1,9 +1,9 @@
 #include <WiFi.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 #include <WebServer.h>
 
-const char* ssid = "........";
-const char* password = "........";
+const char *ssid = "........";
+const char *password = "........";
 
 WebServer server(80);
 
@@ -15,11 +15,11 @@ bool is_authentified() {
     String cookie = server.header("Cookie");
     Serial.println(cookie);
     if (cookie.indexOf("ESPSESSIONID=1") != -1) {
-      Serial.println("Authentification Successful");
+      Serial.println("Authentication Successful");
       return true;
     }
   }
-  Serial.println("Authentification Failed");
+  Serial.println("Authentication Failed");
   return false;
 }
 
@@ -40,7 +40,7 @@ void handleLogin() {
     return;
   }
   if (server.hasArg("USERNAME") && server.hasArg("PASSWORD")) {
-    if (server.arg("USERNAME") == "admin" &&  server.arg("PASSWORD") == "admin") {
+    if (server.arg("USERNAME") == "admin" && server.arg("PASSWORD") == "admin") {
       server.sendHeader("Location", "/");
       server.sendHeader("Cache-Control", "no-cache");
       server.sendHeader("Set-Cookie", "ESPSESSIONID=1");
@@ -59,7 +59,7 @@ void handleLogin() {
   server.send(200, "text/html", content);
 }
 
-//root page can be accessed only if authentification is ok
+//root page can be accessed only if authentication is ok
 void handleRoot() {
   Serial.println("Enter handleRoot");
   String header;
@@ -77,7 +77,7 @@ void handleRoot() {
   server.send(200, "text/html", content);
 }
 
-//no need authentification
+//no need authentication
 void handleNotFound() {
   String message = "File Not Found\n\n";
   message += "URI: ";
@@ -110,17 +110,16 @@ void setup(void) {
   Serial.print("IP address: ");
   Serial.println(WiFi.localIP());
 
-
   server.on("/", handleRoot);
   server.on("/login", handleLogin);
   server.on("/inline", []() {
-    server.send(200, "text/plain", "this works without need of authentification");
+    server.send(200, "text/plain", "this works without need of authentication");
   });
 
   server.onNotFound(handleNotFound);
   //here the list of headers to be recorded
-  const char * headerkeys[] = {"User-Agent", "Cookie"} ;
-  size_t headerkeyssize = sizeof(headerkeys) / sizeof(char*);
+  const char *headerkeys[] = {"User-Agent", "Cookie"};
+  size_t headerkeyssize = sizeof(headerkeys) / sizeof(char *);
   //ask server to track these headers
   server.collectHeaders(headerkeys, headerkeyssize);
   server.begin();
@@ -129,4 +128,5 @@ void setup(void) {
 
 void loop(void) {
   server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
 }
diff --git a/libraries/WebServer/examples/SimpleAuthentification/ci.json b/libraries/WebServer/examples/SimpleAuthentification/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/SimpleAuthentification/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/UploadHugeFile/README.md b/libraries/WebServer/examples/UploadHugeFile/README.md
new file mode 100644
index 00000000000..607dc9d71d8
--- /dev/null
+++ b/libraries/WebServer/examples/UploadHugeFile/README.md
@@ -0,0 +1,13 @@
+# Upload Huge File To SD Over Http
+
+This project is an example of an HTTP server designed to facilitate the transfer of large files using the PUT method, in accordance with RFC specifications.
+
+### Example cURL Command
+
+```bash
+curl -X PUT -T ./my-file.mp3 http://esp-ip/upload/my-file.mp3
+```
+
+## Resources
+
+- RFC HTTP/1.0 - Additional Request Methods - PUT : [Link](https://datatracker.ietf.org/doc/html/rfc1945#appendix-D.1.1)
diff --git a/libraries/WebServer/examples/UploadHugeFile/UploadHugeFile.ino b/libraries/WebServer/examples/UploadHugeFile/UploadHugeFile.ino
new file mode 100644
index 00000000000..54c94ed61d8
--- /dev/null
+++ b/libraries/WebServer/examples/UploadHugeFile/UploadHugeFile.ino
@@ -0,0 +1,88 @@
+#include <WiFi.h>
+#include <WebServer.h>
+#include <uri/UriRegex.h>
+#include <SD.h>
+
+const char *ssid = "**********";
+const char *password = "**********";
+
+WebServer server(80);
+
+File rawFile;
+void handleCreate() {
+  server.send(200, "text/plain", "");
+}
+void handleCreateProcess() {
+  String path = "/" + server.pathArg(0);
+  HTTPRaw &raw = server.raw();
+  if (raw.status == RAW_START) {
+    if (SD.exists((char *)path.c_str())) {
+      SD.remove((char *)path.c_str());
+    }
+    rawFile = SD.open(path.c_str(), FILE_WRITE);
+    Serial.print("Upload: START, filename: ");
+    Serial.println(path);
+  } else if (raw.status == RAW_WRITE) {
+    if (rawFile) {
+      rawFile.write(raw.buf, raw.currentSize);
+    }
+    Serial.print("Upload: WRITE, Bytes: ");
+    Serial.println(raw.currentSize);
+  } else if (raw.status == RAW_END) {
+    if (rawFile) {
+      rawFile.close();
+    }
+    Serial.print("Upload: END, Size: ");
+    Serial.println(raw.totalSize);
+  }
+}
+
+void returnFail(String msg) {
+  server.send(500, "text/plain", msg + "\r\n");
+}
+
+void handleNotFound() {
+  String message = "File Not Found\n\n";
+  message += "URI: ";
+  message += server.uri();
+  message += "\nMethod: ";
+  message += (server.method() == HTTP_GET) ? "GET" : "POST";
+  message += "\nArguments: ";
+  message += server.args();
+  message += "\n";
+  for (uint8_t i = 0; i < server.args(); i++) {
+    message += " " + server.argName(i) + ": " + server.arg(i) + "\n";
+  }
+  server.send(404, "text/plain", message);
+}
+
+void setup(void) {
+  Serial.begin(115200);
+
+  while (!SD.begin()) {
+    delay(1);
+  }
+  Serial.println("SD Card initialized.");
+
+  WiFi.mode(WIFI_STA);
+  WiFi.begin(ssid, password);
+
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.print("Connected to ");
+  Serial.println(ssid);
+  Serial.print("IP address: ");
+  Serial.println(WiFi.localIP());
+
+  server.on(UriRegex("/upload/(.*)"), HTTP_PUT, handleCreate, handleCreateProcess);
+  server.onNotFound(handleNotFound);
+  server.begin();
+  Serial.println("HTTP server started");
+}
+
+void loop(void) {
+  server.handleClient();
+  delay(2);  //allow the cpu to switch to other tasks
+}
diff --git a/libraries/WebServer/examples/UploadHugeFile/ci.json b/libraries/WebServer/examples/UploadHugeFile/ci.json
new file mode 100644
index 00000000000..cbdd28f773d
--- /dev/null
+++ b/libraries/WebServer/examples/UploadHugeFile/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/WebServer/README.md b/libraries/WebServer/examples/WebServer/README.md
new file mode 100644
index 00000000000..b316682845f
--- /dev/null
+++ b/libraries/WebServer/examples/WebServer/README.md
@@ -0,0 +1,297 @@
+# Arduino-ESP32 WebServer Example for WebServer Library
+
+This example shows different techniques on how to use and extend the WebServer for specific purposes
+
+It is a small project in it's own and has some files to use on the web server to show how to use simple REST based services.
+
+This example requires some space for a filesystem and runs fine on supported SoCs with 4 MByte or more flash by selecting the proper partition table:
+
+* For using SPIFFS(LittleFS): `Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)`
+* For using FATFS: `Default 4MB with ffat (1.2MB APP/1.5MB FATFS)`
+
+
+It features
+
+* Setup a web server
+* redirect when accessing the url with servername only
+* get real time by using builtin NTP functionality
+* send HTML responses from Sketch (see builtinfiles.h)
+* use a LittleFS file system on the data partition for static files
+* use http ETag Header for client side caching of static files
+* use custom ETag calculation for static files
+* extended FileServerHandler for uploading and deleting static files
+* uploading files using drag & drop
+* serve APIs using REST services (/api/list, /api/sysinfo)
+* define HTML response when no file/api/handler was found
+
+## Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 | ESP32-C3 | ESP32-C6 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- |
+|                   | yes   | yes      | yes      | yes      | yes      |
+
+## Use the Example
+
+How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+* In the file `secrets.h` you can add the home Wi-Fi network name ans password.
+* Compile and upload to the device.
+* Have a look into the monitoring output.
+* Open <http://webserver> or <http://(ip-address)> using a browser.
+* You will be redirected to <http://webserver/$upload.htm> as there are no files yet in the file system.
+* Drag the files from the data folder onto the drop area shown in the browser.
+* See below for more details
+
+## Implementing a web server
+
+The WebServer library offers a simple path to implement a web server on a ESP32 based board.
+
+The advantage on using the WebServer instead of the plain simple NetworkServer is that the WebServer
+takes much care about the http protocol conventions and features and allows easily access to parameters.
+It offers plug-in capabilities by registering specific functionalities that will be outlined below.
+
+### Initialization
+
+In the setup() function in the webserver.ino sketch file the following steps are implemented to make the webserver available on the local network.
+
+* Create a webserver listening to port 80 for HTTP requests.
+* Initialize the access to the filesystem in the free flash memory.
+* Connect to the local Wi-Fi network. Here is only a straight-forward implementation hard-coding network name and passphrase. You may consider to use something like the WiFiManager library in real applications.
+* Register the device in DNS using a known hostname.
+* Registering several plug-ins (see below).
+* Starting the web server.
+
+### Running
+
+In the loop() function the web server will be given time to receive and send network packages by calling
+`server.handleClient();`.
+
+## Registering simple functions to implement RESTful services
+
+Registering function is the simplest integration mechanism available to add functionality. The server offers the `on(path, function)` methods that take the URL and the function as parameters.
+
+There are 2 functions implemented that get registered to handle incoming GET requests for given URLs.
+
+The JSON data format is used often for such services as it is the "natural" data format of the browser using javascript.
+
+When the **handleSysInfo()** function is registered and a browser requests for <http://webserver/api/sysinfo> the function will be called and can collect the requested information.
+
+> ```CPP
+> server.on("/api/sysinfo", handleSysInfo);
+> ```
+
+The result in this case is a JSON object that is assembled in the result String variable and the returned as a response to the client also giving the information about the data format.
+
+You can try this request in a browser by opening <http://webserver/api/sysinfo> in the address bar.
+
+> ```CPP
+> server.on("/api/sysinfo", handleList);
+> ```
+
+The function **handleList()** is registered the same way to return the list of files in the file system also returning a JSON object including name, size and the last modification timestamp.
+
+You can try this request in a browser by opening <http://webserver/api/list> in the address bar.
+
+## Registering a function to send out some static content from a String
+
+This is an example of registering a inline function in the web server.
+The 2. parameter of the on() method is a so called CPP lambda function (without a name)
+that actually has only one line of functionality by sending a string as result to the client.
+
+> ``` cpp
+> server.on("/$upload.htm", []() {
+>   server.send(200, "text/html", FPSTR(uploadContent));
+> });
+> ```
+
+Here the text from a static String with html code is returned instead of a file from the filesystem.
+The content of this string can be found in the file `builtinfiles.h`. It contains a small html+javascript implementation
+that allows uploading new files into the empty filesystem.
+
+Just open <http://webserver/$upload.htm> and drag some files from the data folder on the drop area.
+
+## Registering a function to handle requests to the server without a path
+
+Often servers are addressed by using the base URL like <http://webserver/> where no further path details is given.
+Of course we like the user to be redirected to something usable. Therefore the `handleRoot()` function is registered:
+
+> ``` cpp
+> server.on("/$upload.htm", handleRoot);
+> ```
+
+The `handleRoot()` function checks the filesystem for the file named **/index.htm** and creates a redirect to this file when the file exists.
+Otherwise the redirection goes to the built-in **/$upload.htm** web page.
+
+## Using the serveStatic plug-in
+
+The **serveStatic** plug in is part of the library and handles delivering files from the filesystem to the client. It can be customized in some ways.
+
+> ``` cpp
+> server.enableCORS(true);
+> server.enableETag(true);
+> server.serveStatic("/", LittleFS, "/");
+> ```
+
+### Cross-Origin Resource Sharing (CORS)
+
+The `enableCORS(true)` function adds a `Access-Control-Allow-Origin: *` http-header to all responses to the client
+to inform that it is allowed to call URLs and services on this server from other web sites.
+
+The feature is disabled by default (in the current version) and when you like to disable this then you should call `enableCORS(false)` during setup.
+
+* Web sites providing high sensitive information like online banking this is disabled most of the times.
+* Web sites providing advertising information or reusable scripts / images this is enabled.
+
+### enabling ETag support
+
+To enable this in the embedded web server the `enableETag()` can be used.
+(next to enableCORS)
+
+In the simplest version just call `enableETag(true)` to enable the internal ETag generation that calcs the hint using a md5 checksum in base64 encoded form. This is an simple approach that adds some time for calculation on every request but avoids network traffic.
+
+The headers will look like:
+
+``` txt
+If-None-Match: "GhZka3HevoaEBbtQOgOqlA=="
+ETag: "GhZka3HevoaEBbtQOgOqlA=="
+```
+
+
+### ETag support customization
+
+The enableETag() function has an optional second optional parameter to provide a function for ETag calculation of files.
+
+The function enables eTags for all files by using calculating a value from the last write timestamp:
+
+``` cpp
+server.enableETag(true, [](FS &fs, const String &path) -> String {
+  File f = fs.open(path, "r");
+  String eTag = String(f.getLastWrite(), 16);  // use file modification timestamp to create ETag
+  f.close();
+  return (eTag);
+});
+```
+
+The headers will look like:
+
+``` txt
+ETag: "63bbaeb5"
+If-None-Match: "63bbaeb5"
+```
+
+
+## Registering a full-featured handler as plug-in
+
+The example also implements the class `FileServerHandler` derived from the class `RequestHandler` to plug in functionality
+that can handle more complex requests without giving a fixed URL.
+It implements uploading and deleting files in the file system that is not implemented by the standard server.serveStatic functionality.
+
+This class has to implements several functions and works in a more detailed way:
+
+* The `canHandle()` method can inspect the given http method and url to decide weather the RequestFileHandler can handle the incoming request or not.
+
+  In this case the RequestFileHandler will return true when the request method is an POST for upload or a DELETE for deleting files.
+
+  The regular GET requests will be ignored and therefore handled by the also registered server.serveStatic handler.
+
+* The function `handle()` then implements the real deletion of the file.
+
+* The `canUpload()`and `upload()` methods work similar while the `upload()` method is called multiple times to create, append data and close the new file.
+
+
+## File upload
+
+By opening <http://webserver/$upload.htm> you can easily upload files by dragging them over the drop area.
+
+Just take the files from the data folder to create some files that can explore the server functionality.
+
+Files will be uploaded to the root folder of the file system. and you will see it next time using  <http://webserver/files.htm>.
+
+The filesize that is uploaded is not known when the upload mechanism in function
+FileServerHandler::upload gets started.
+
+Uploading a file that fits into the available filesystem space
+can be found in the Serial output:
+
+``` txt
+starting upload file /file.txt...
+finished.
+1652 bytes uploaded.
+```
+
+Uploading a file that doesn't fit can be detected while uploading when writing to the filesystem fails.
+However upload cannot be aborted by the current handler implementation.
+
+The solution implemented here is to delete the partially uploaded file and wait for the upload ending.
+The following can be found in the Serial output:
+
+``` txt
+starting upload file /huge.jpg...
+./components/esp_littlefs/src/littlefs/lfs.c:584:error: No more free space 531
+  write error!
+finished.
+```
+
+You can see on the Serial output that one filesystem write error is reported.
+
+Please be patient and wait for the upload ending even when writing to the filesystem is disabled
+it maybe take more than a minute.
+
+
+## Registering a special handler for "file not found"
+
+Any other incoming request that was not handled by the registered plug-ins above can be detected by registering
+
+> ``` cpp
+> // handle cases when file is not found
+> server.onNotFound([]() {
+>   // standard not found in browser.
+>   server.send(404, "text/html", FPSTR(notFoundContent));
+> });
+> ```
+
+This allows sending back an "friendly" result for the browser. Here a simple html page is created from a static string.
+You can easily change the html code in the file `builtinfiles.h`.
+
+
+## customizations
+
+You may like to change the hostname and the timezone in the lines:
+
+> ``` cpp
+> #define HOSTNAME "webserver"
+> #define TIMEZONE "CET-1CEST,M3.5.0,M10.5.0/3"
+> ```
+
+
+## Troubleshooting
+
+Have a look in the Serial output for some additional runtime information.
+
+
+## Changes
+
+* 2024-08-02 -- Fixing for board implementation 3.0.4 ff.
+* 2024-08-02 -- Support for FAT
+
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/WebServer/examples/WebServer/WebServer.ino b/libraries/WebServer/examples/WebServer/WebServer.ino
new file mode 100644
index 00000000000..809a95ce1f3
--- /dev/null
+++ b/libraries/WebServer/examples/WebServer/WebServer.ino
@@ -0,0 +1,376 @@
+// @file WebServer.ino
+// @brief Example WebServer implementation using the ESP32 WebServer
+// and most common use cases related to web servers.
+//
+// * Setup a web server
+// * redirect when accessing the url with servername only
+// * get real time by using builtin NTP functionality
+// * send HTML responses from Sketch (see builtinfiles.h)
+// * use a LittleFS file system on the data partition for static files
+// * use http ETag Header for client side caching of static files
+// * use custom ETag calculation for static files
+// * extended FileServerHandler for uploading and deleting static files
+// * extended FileServerHandler for uploading and deleting static files
+// * serve APIs using REST services (/api/list, /api/sysinfo)
+// * define HTML response when no file/api/handler was found
+//
+// See also README.md for instructions and hints.
+//
+// Please use the following Arduino IDE configuration
+//
+// * Board: "ESP32 Dev Module" or other board with ESP32
+// * Partition Scheme: "Default 4MB with spiffs" or any other scheme with spiffs or FAT
+//     but LittleFS will be used in the partition (not SPIFFS)
+// * other setting as applicable
+//
+// Changelog:
+// 21.07.2021 creation, first version
+// 08.01.2023 ESP32 version with ETag
+// 02.08.2024 support LitteFS and FAT file systems (on large Flash chips)
+
+#include <Arduino.h>
+#include <WebServer.h>
+#include <WiFi.h>
+
+#include "secrets.h"  // add WLAN Credentials in here.
+
+#include "esp_partition.h"  // to check existing data partitions in Flash memory
+
+#include <FS.h>        // File System for Web Server Files
+#include <LittleFS.h>  // Use LittleFSThis file system is used.
+#include <FFat.h>      // or.. FAT
+
+// mark parameters not used in example
+#define UNUSED __attribute__((unused))
+
+// TRACE output simplified, can be deactivated here
+#define TRACE(...) Serial.printf(__VA_ARGS__)
+
+// name of the server. You reach it using http://webserver
+#define HOSTNAME "webserver"
+
+// local time zone definition (Berlin)
+#define TIMEZONE "CET-1CEST,M3.5.0,M10.5.0/3"
+
+// need a WebServer for http access on port 80.
+WebServer server(80);
+
+// The file system in use...
+fs::FS *fsys = nullptr;
+
+// The text of builtin files are in this header file
+#include "builtinfiles.h"
+
+// enable the CUSTOM_ETAG_CALC to enable calculation of ETags by a custom function
+#define CUSTOM_ETAG_CALC
+
+// ===== Simple functions used to answer simple GET requests =====
+
+// This function is called when the WebServer was requested without giving a filename.
+// This will redirect to the file index.htm when it is existing otherwise to the built-in $upload.htm page
+void handleRedirect() {
+  TRACE("Redirect...\n");
+  String url = "/index.htm";
+
+  if (!fsys->exists(url)) {
+    url = "/$upload.htm";
+  }
+
+  server.sendHeader("Location", url, true);
+  server.send(302);
+}  // handleRedirect()
+
+// This function is called when the WebServer was requested to list all existing files in the filesystem.
+// a JSON array with file information is returned.
+void handleListFiles() {
+  File dir = fsys->open("/", "r");
+  String result;
+
+  result += "[\n";
+  while (File entry = dir.openNextFile()) {
+    if (result.length() > 4) {
+      result += ",\n";
+    }
+    result += "  {";
+    result += "\"type\": \"file\", ";
+    result += "\"name\": \"" + String(entry.name()) + "\", ";
+    result += "\"size\": " + String(entry.size()) + ", ";
+    result += "\"time\": " + String(entry.getLastWrite());
+    result += "}";
+  }  // while
+
+  result += "\n]";
+  server.sendHeader("Cache-Control", "no-cache");
+  server.send(200, "text/javascript; charset=utf-8", result);
+}  // handleListFiles()
+
+// This function is called when the sysInfo service was requested.
+void handleSysInfo() {
+  String result;
+
+  result += "{\n";
+  result += "  \"Chip Model\": " + String(ESP.getChipModel()) + ",\n";
+  result += "  \"Chip Cores\": " + String(ESP.getChipCores()) + ",\n";
+  result += "  \"Chip Revision\": " + String(ESP.getChipRevision()) + ",\n";
+  result += "  \"flashSize\": " + String(ESP.getFlashChipSize()) + ",\n";
+  result += "  \"freeHeap\": " + String(ESP.getFreeHeap()) + ",\n";
+
+  if (fsys == (fs::FS *)&FFat) {
+    result += "  \"fsTotalBytes\": " + String(FFat.totalBytes()) + ",\n";
+    result += "  \"fsUsedBytes\": " + String(FFat.usedBytes()) + ",\n";
+  } else {
+    result += "  \"fsTotalBytes\": " + String(LittleFS.totalBytes()) + ",\n";
+    result += "  \"fsUsedBytes\": " + String(LittleFS.usedBytes()) + ",\n";
+  }
+
+  result += "}";
+
+  server.sendHeader("Cache-Control", "no-cache");
+  server.send(200, "text/javascript; charset=utf-8", result);
+}  // handleSysInfo()
+
+// ===== Request Handler class used to answer more complex requests =====
+
+// The FileServerHandler is registered to the web server to support DELETE and UPLOAD of files into the filesystem.
+class FileServerHandler : public RequestHandler {
+public:
+  // @brief Construct a new File Server Handler object
+  // @param fs The file system to be used.
+  // @param path Path to the root folder in the file system that is used for serving static data down and upload.
+  // @param cache_header Cache Header to be used in replies.
+  FileServerHandler() {
+    TRACE("FileServerHandler is registered\n");
+  }
+
+  // @brief check incoming request. Can handle POST for uploads and DELETE.
+  // @param requestMethod method of the http request line.
+  // @param requestUri request resource from the http request line.
+  // @return true when method can be handled.
+  bool canHandle(WebServer &server, HTTPMethod requestMethod, const String &uri) override {
+    return ((requestMethod == HTTP_POST) || (requestMethod == HTTP_DELETE));
+  }  // canHandle()
+
+  bool canUpload(WebServer &server, const String &uri) override {
+    // only allow upload on root fs level.
+    return (uri == "/");
+  }  // canUpload()
+
+  bool handle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override {
+    // ensure that filename starts with '/'
+    String fName = requestUri;
+    if (!fName.startsWith("/")) {
+      fName = "/" + fName;
+    }
+
+    if (requestMethod == HTTP_POST) {
+      // all done in upload. no other forms.
+
+    } else if (requestMethod == HTTP_DELETE) {
+      if (fsys->exists(fName)) {
+        TRACE("DELETE %s\n", fName.c_str());
+        fsys->remove(fName);
+      }
+    }  // if
+
+    server.send(200);  // all done.
+    return (true);
+  }  // handle()
+
+  // uploading process
+  void upload(WebServer UNUSED &server, const String &requestUri, HTTPUpload &upload) override {
+    // ensure that filename starts with '/'
+    static size_t uploadSize;
+
+    if (upload.status == UPLOAD_FILE_START) {
+      String fName = upload.filename;
+
+      // Open the file for writing
+      if (!fName.startsWith("/")) {
+        fName = "/" + fName;
+      }
+      TRACE("start uploading file %s...\n", fName.c_str());
+
+      if (fsys->exists(fName)) {
+        fsys->remove(fName);
+      }  // if
+      _fsUploadFile = fsys->open(fName, "w");
+      uploadSize = 0;
+
+    } else if (upload.status == UPLOAD_FILE_WRITE) {
+      // Write received bytes
+      if (_fsUploadFile) {
+        size_t written = _fsUploadFile.write(upload.buf, upload.currentSize);
+        if (written < upload.currentSize) {
+          // upload failed
+          TRACE("  write error!\n");
+          _fsUploadFile.close();
+
+          // delete file to free up space in filesystem
+          String fName = upload.filename;
+          if (!fName.startsWith("/")) {
+            fName = "/" + fName;
+          }
+          fsys->remove(fName);
+        }
+        uploadSize += upload.currentSize;
+        // TRACE("free:: %d of %d\n", LittleFS.usedBytes(), LittleFS.totalBytes());
+        // TRACE("written:: %d of %d\n", written, upload.currentSize);
+        // TRACE("totalSize: %d\n", upload.currentSize + upload.totalSize);
+      }  // if
+
+    } else if (upload.status == UPLOAD_FILE_END) {
+      TRACE("upload done.\n");
+      // Close the file
+      if (_fsUploadFile) {
+        _fsUploadFile.close();
+        TRACE(" %d bytes uploaded.\n", upload.totalSize);
+      }
+    }  // if
+
+  }  // upload()
+
+protected:
+  File _fsUploadFile;
+};
+
+// Setup everything to make the webserver work.
+void setup(void) {
+  delay(3000);  // wait for serial monitor to start completely.
+
+  // Use Serial port for some trace information from the example
+  Serial.begin(115200);
+  Serial.setDebugOutput(false);
+
+  TRACE("Starting WebServer example...\n");
+
+  // ----- check partitions for finding the filesystem type -----
+  esp_partition_iterator_t i;
+
+  i = esp_partition_find(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, nullptr);
+  if (i) {
+    TRACE("FAT partition found.");
+    fsys = &FFat;
+
+  } else {
+    i = esp_partition_find(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, nullptr);
+    if (i) {
+      TRACE("SPIFFS partition found.");
+      fsys = &LittleFS;
+
+    } else {
+      TRACE("no partition found.");
+    }
+  }
+  esp_partition_iterator_release(i);
+
+  // mount and format as needed
+  TRACE("Mounting the filesystem...\n");
+  if (!fsys) {
+    TRACE("need to change the board configuration to include a partition for files.\n");
+    delay(30000);
+
+  } else if ((fsys == (fs::FS *)&FFat) && (!FFat.begin())) {
+    TRACE("could not mount the filesystem...\n");
+    delay(2000);
+    TRACE("formatting FAT...\n");
+    FFat.format();
+    delay(2000);
+    TRACE("restarting...\n");
+    delay(2000);
+    ESP.restart();
+
+  } else if ((fsys == (fs::FS *)&LittleFS) && (!LittleFS.begin())) {
+    TRACE("could not mount the filesystem...\n");
+    delay(2000);
+    TRACE("formatting LittleFS...\n");
+    LittleFS.format();
+    delay(2000);
+    TRACE("restarting...\n");
+    delay(2000);
+    ESP.restart();
+  }
+
+  // allow to address the device by the given name e.g. http://webserver
+  WiFi.setHostname(HOSTNAME);
+
+  // start WiFI
+  WiFi.mode(WIFI_STA);
+  if (strlen(ssid) == 0) {
+    WiFi.begin();
+  } else {
+    WiFi.begin(ssid, passPhrase);
+  }
+
+  TRACE("Connect to WiFi...\n");
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    TRACE(".");
+  }
+  TRACE("connected.\n");
+
+  // Ask for the current time using NTP request builtin into ESP firmware.
+  TRACE("Setup ntp...\n");
+  configTzTime(TIMEZONE, "pool.ntp.org");
+
+  TRACE("Register redirect...\n");
+
+  // register a redirect handler when only domain name is given.
+  server.on("/", HTTP_GET, handleRedirect);
+
+  TRACE("Register service handlers...\n");
+
+  // serve a built-in htm page
+  server.on("/$upload.htm", []() {
+    server.send(200, "text/html", FPSTR(uploadContent));
+  });
+
+  // register some REST services
+  server.on("/api/list", HTTP_GET, handleListFiles);
+  server.on("/api/sysinfo", HTTP_GET, handleSysInfo);
+
+  TRACE("Register file system handlers...\n");
+
+  // UPLOAD and DELETE of files in the file system using a request handler.
+  server.addHandler(new FileServerHandler());
+
+  // enable CORS header in webserver results
+  server.enableCORS(true);
+
+  // enable ETAG header in webserver results (used by serveStatic handler)
+#if defined(CUSTOM_ETAG_CALC)
+  // This is a fast custom eTag generator. It returns a value based on the time the file was updated like
+  // ETag: 63bbceb5
+  server.enableETag(true, [](FS &fs, const String &path) -> String {
+    File f = fs.open(path, "r");
+    String eTag = String(f.getLastWrite(), 16);  // use file modification timestamp to create ETag
+    f.close();
+    return (eTag);
+  });
+
+#else
+  // enable standard ETAG calculation using md5 checksum of file content.
+  server.enableETag(true);
+#endif
+
+  // serve all static files
+  server.serveStatic("/", *fsys, "/");
+
+  TRACE("Register default (not found) answer...\n");
+
+  // handle cases when file is not found
+  server.onNotFound([]() {
+    // standard not found in browser.
+    server.send(404, "text/html", FPSTR(notFoundContent));
+  });
+
+  server.begin();
+
+  TRACE("open <http://%s> or <http://%s>\n", WiFi.getHostname(), WiFi.localIP().toString().c_str());
+}  // setup
+
+// run the server...
+void loop(void) {
+  server.handleClient();
+}  // loop()
+
+// end.
diff --git a/libraries/WebServer/examples/WebServer/builtinfiles.h b/libraries/WebServer/examples/WebServer/builtinfiles.h
new file mode 100644
index 00000000000..c7fa57f53d9
--- /dev/null
+++ b/libraries/WebServer/examples/WebServer/builtinfiles.h
@@ -0,0 +1,63 @@
+/**
+ * @file builtinfiles.h
+ * @brief This file is part of the WebServer example for the ESP8266WebServer.
+ *
+ * This file contains long, multiline text variables for  all builtin resources.
+ */
+
+// used for $upload.htm
+static const char uploadContent[] PROGMEM =
+  R"==(
+<!doctype html>
+<html lang='en'>
+
+<head>
+  <meta charset="utf-8">
+  <meta name="viewport" content="width=device-width, initial-scale=1">
+  <title>Upload</title>
+</head>
+
+<body style="width:300px">
+  <h1>Upload</h1>
+  <div><a href="/">Home</a></div>
+  <hr>
+  <div id='zone' style='width:16em;height:12em;padding:10px;background-color:#ddd'>Drop files here...</div>
+
+  <script>
+    // allow drag&drop of file objects
+    function dragHelper(e) {
+      e.stopPropagation();
+      e.preventDefault();
+    }
+
+    // allow drag&drop of file objects
+    function dropped(e) {
+      dragHelper(e);
+      var fls = e.dataTransfer.files;
+      var formData = new FormData();
+      for (var i = 0; i < fls.length; i++) {
+        formData.append('file', fls[i], '/' + fls[i].name);
+      }
+      fetch('/', { method: 'POST', body: formData }).then(function () {
+        window.alert('done.');
+      });
+    }
+    var z = document.getElementById('zone');
+    z.addEventListener('dragenter', dragHelper, false);
+    z.addEventListener('dragover', dragHelper, false);
+    z.addEventListener('drop', dropped, false);
+  </script>
+</body>
+)==";
+
+// used for $upload.htm
+static const char notFoundContent[] PROGMEM = R"==(
+<html>
+<head>
+  <title>Resource not found</title>
+</head>
+<body>
+  <p>The resource was not found.</p>
+  <p><a href="/">Start again</a></p>
+</body>
+)==";
diff --git a/libraries/WebServer/examples/WebServer/ci.json b/libraries/WebServer/examples/WebServer/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/WebServer/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/examples/WebServer/data/files.htm b/libraries/WebServer/examples/WebServer/data/files.htm
new file mode 100644
index 00000000000..90fb8faeda2
--- /dev/null
+++ b/libraries/WebServer/examples/WebServer/data/files.htm
@@ -0,0 +1,65 @@
+<html>
+
+<head>
+  <title>Files</title>
+  <link Content-Type="text/css" href="/style.css" rel="stylesheet" />
+</head>
+
+<body>
+  <h1>Files on Server</h1>
+
+  <p>These files are available on the server to be opened or delete:</p>
+  <div id="list">
+  </div>
+
+  <script>
+    // load and display all files after page loading has finished
+    window.addEventListener("load", function () {
+      fetch('/api/list')
+        .then(function (result) { return result.json(); })
+        .then(function (e) {
+          var listObj = document.querySelector('#list');
+          e.forEach(function (f) {
+            var entry = document.createElement("div");
+            var nameObj = document.createElement("a");
+            nameObj.href = '/' + f.name;
+            nameObj.innerText = '/' + f.name;
+            entry.appendChild(nameObj)
+
+            entry.appendChild(document.createTextNode(' (' + f.size + ') '));
+
+            var timeObj = document.createElement("span");
+            timeObj.innerText = (new Date(f.time*1000)).toLocaleString();
+            entry.appendChild(timeObj)
+            entry.appendChild(document.createTextNode(" "));
+
+            var delObj = document.createElement("span");
+            delObj.className = 'deleteFile';
+            delObj.innerText = ' [delete]';
+            entry.appendChild(delObj)
+
+            listObj.appendChild(entry)
+          });
+
+        })
+        .catch(function (err) {
+          window.alert(err);
+        });
+    });
+
+    window.addEventListener("click", function (evt) {
+      var t = evt.target;
+      if (t.className === 'deleteFile') {
+        var fname = t.parentElement.innerText;
+        fname = fname.split(' ')[0];
+        if (window.confirm("Delete " + fname + " ?")) {
+          fetch(fname, { method: 'DELETE' });
+          document.location.reload(false);
+        }
+      };
+    });
+
+  </script>
+</body>
+
+</html>
diff --git a/libraries/WebServer/examples/WebServer/data/index.htm b/libraries/WebServer/examples/WebServer/data/index.htm
new file mode 100644
index 00000000000..312dd7bb8e5
--- /dev/null
+++ b/libraries/WebServer/examples/WebServer/data/index.htm
@@ -0,0 +1,25 @@
+<html>
+
+<head>
+  <title>HomePage</title>
+  <link Content-Type="text/css" href="/style.css" rel="stylesheet" />
+</head>
+
+<body>
+  <h1>Homepage of the WebServer Example</h1>
+
+  <p>The following pages are available:</p>
+  <ul>
+    <li><a href="/index.htm">/index.htm</a> - This page</li>
+    <li><a href="/files.htm">/files.htm</a> - Manage files on the server</li>
+    <li><a href="/$upload.htm">/$upload.htm</a> - Built-in upload utility</a></li>
+    <li><a href="/none.htm">/none.htm</a> - See the default response when files are not found.</a></li>
+  </ul>
+
+  <p>The following REST services are available:</p>
+  <ul>
+    <li><a href="/api/sysinfo">/api/sysinfo</a> - Some system level information</a></li>
+    <li><a href="/api/list">/api/list</a> - Array of all files</a></li>
+  </ul>
+</body>
+</html>
diff --git a/libraries/WebServer/examples/WebServer/data/style.css b/libraries/WebServer/examples/WebServer/data/style.css
new file mode 100644
index 00000000000..e2af558e6b3
--- /dev/null
+++ b/libraries/WebServer/examples/WebServer/data/style.css
@@ -0,0 +1,9 @@
+html, body {
+  color: #111111; font-family: Arial, ui-sans-serif, sans-serif; font-size: 1em; background-color: #f0f0f0;
+}
+
+#list > div {
+  margin: 0 0 0.5rem 0;
+}
+
+a { color: inherit; cursor: pointer; }
diff --git a/libraries/WebServer/examples/WebServer/secrets.h b/libraries/WebServer/examples/WebServer/secrets.h
new file mode 100644
index 00000000000..0c5d3687eb1
--- /dev/null
+++ b/libraries/WebServer/examples/WebServer/secrets.h
@@ -0,0 +1,13 @@
+// Secrets for your local home network
+
+// This is a "hard way" to configure your local WiFi network name and passphrase
+// into the source code and the uploaded sketch.
+//
+// Using the WiFi Manager is preferred and avoids reprogramming when your network changes.
+// See https://homeding.github.io/#page=/wifimanager.md
+
+// ssid and passPhrase can be used when compiling for a specific environment as a 2. option.
+
+// add you wifi network name and PassPhrase or use WiFi Manager
+const char *ssid = "";
+const char *passPhrase = "";
diff --git a/libraries/WebServer/examples/WebUpdate/WebUpdate.ino b/libraries/WebServer/examples/WebUpdate/WebUpdate.ino
index 843867d5f3b..10ddb5e7b64 100644
--- a/libraries/WebServer/examples/WebUpdate/WebUpdate.ino
+++ b/libraries/WebServer/examples/WebUpdate/WebUpdate.ino
@@ -3,17 +3,18 @@
 */
 
 #include <WiFi.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 #include <WebServer.h>
 #include <ESPmDNS.h>
 #include <Update.h>
 
-const char* host = "esp32-webupdate";
-const char* ssid = "........";
-const char* password = "........";
+const char *host = "esp32-webupdate";
+const char *ssid = "........";
+const char *password = "........";
 
 WebServer server(80);
-const char* serverIndex = "<form method='POST' action='/update' enctype='multipart/form-data'><input type='file' name='update'><input type='submit' value='Update'></form>";
+const char *serverIndex =
+  "<form method='POST' action='/update' enctype='multipart/form-data'><input type='file' name='update'><input type='submit' value='Update'></form>";
 
 void setup(void) {
   Serial.begin(115200);
@@ -27,33 +28,37 @@ void setup(void) {
       server.sendHeader("Connection", "close");
       server.send(200, "text/html", serverIndex);
     });
-    server.on("/update", HTTP_POST, []() {
-      server.sendHeader("Connection", "close");
-      server.send(200, "text/plain", (Update.hasError()) ? "FAIL" : "OK");
-      ESP.restart();
-    }, []() {
-      HTTPUpload& upload = server.upload();
-      if (upload.status == UPLOAD_FILE_START) {
-        Serial.setDebugOutput(true);
-        Serial.printf("Update: %s\n", upload.filename.c_str());
-        if (!Update.begin()) { //start with max available size
-          Update.printError(Serial);
-        }
-      } else if (upload.status == UPLOAD_FILE_WRITE) {
-        if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) {
-          Update.printError(Serial);
-        }
-      } else if (upload.status == UPLOAD_FILE_END) {
-        if (Update.end(true)) { //true to set the size to the current progress
-          Serial.printf("Update Success: %u\nRebooting...\n", upload.totalSize);
+    server.on(
+      "/update", HTTP_POST,
+      []() {
+        server.sendHeader("Connection", "close");
+        server.send(200, "text/plain", (Update.hasError()) ? "FAIL" : "OK");
+        ESP.restart();
+      },
+      []() {
+        HTTPUpload &upload = server.upload();
+        if (upload.status == UPLOAD_FILE_START) {
+          Serial.setDebugOutput(true);
+          Serial.printf("Update: %s\n", upload.filename.c_str());
+          if (!Update.begin()) {  //start with max available size
+            Update.printError(Serial);
+          }
+        } else if (upload.status == UPLOAD_FILE_WRITE) {
+          if (Update.write(upload.buf, upload.currentSize) != upload.currentSize) {
+            Update.printError(Serial);
+          }
+        } else if (upload.status == UPLOAD_FILE_END) {
+          if (Update.end(true)) {  //true to set the size to the current progress
+            Serial.printf("Update Success: %u\nRebooting...\n", upload.totalSize);
+          } else {
+            Update.printError(Serial);
+          }
+          Serial.setDebugOutput(false);
         } else {
-          Update.printError(Serial);
+          Serial.printf("Update Failed Unexpectedly (likely broken connection): status=%d\n", upload.status);
         }
-        Serial.setDebugOutput(false);
-      } else {
-        Serial.printf("Update Failed Unexpectedly (likely broken connection): status=%d\n", upload.status);
       }
-    });
+    );
     server.begin();
     MDNS.addService("http", "tcp", 80);
 
@@ -65,5 +70,5 @@ void setup(void) {
 
 void loop(void) {
   server.handleClient();
-  delay(1);
+  delay(2);  //allow the cpu to switch to other tasks
 }
diff --git a/libraries/WebServer/examples/WebUpdate/ci.json b/libraries/WebServer/examples/WebUpdate/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WebServer/examples/WebUpdate/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WebServer/library.properties b/libraries/WebServer/library.properties
index a2ac5f5317c..2a9ff530d57 100644
--- a/libraries/WebServer/library.properties
+++ b/libraries/WebServer/library.properties
@@ -1,5 +1,5 @@
 name=WebServer
-version=1.0
+version=3.2.0
 author=Ivan Grokhotkov
 maintainer=Ivan Grokhtkov <ivan@esp8266.com>
 sentence=Simple web server library
diff --git a/libraries/WebServer/src/HTTP_Method.h b/libraries/WebServer/src/HTTP_Method.h
index 4532332bc88..66d53bf87a0 100644
--- a/libraries/WebServer/src/HTTP_Method.h
+++ b/libraries/WebServer/src/HTTP_Method.h
@@ -1,15 +1,9 @@
 #ifndef _HTTP_Method_H_
 #define _HTTP_Method_H_
 
-typedef enum {
-  HTTP_GET     = 0b00000001,
-  HTTP_POST    = 0b00000010,
-  HTTP_DELETE  = 0b00000100,
-  HTTP_PUT     = 0b00001000,
-  HTTP_PATCH   = 0b00010000,
-  HTTP_HEAD    = 0b00100000,
-  HTTP_OPTIONS = 0b01000000,
-  HTTP_ANY     = 0b01111111,
-} HTTPMethod;
+#include "http_parser.h"
+
+typedef enum http_method HTTPMethod;
+#define HTTP_ANY (HTTPMethod)(255)
 
 #endif /* _HTTP_Method_H_ */
diff --git a/libraries/WebServer/src/Middlewares.h b/libraries/WebServer/src/Middlewares.h
new file mode 100644
index 00000000000..04fab52790b
--- /dev/null
+++ b/libraries/WebServer/src/Middlewares.h
@@ -0,0 +1,66 @@
+#ifndef MIDDLEWARES_H
+#define MIDDLEWARES_H
+
+#include <WebServer.h>
+#include <Stream.h>
+
+#include <assert.h>
+
+// curl-like logging middleware
+class LoggingMiddleware : public Middleware {
+public:
+  void setOutput(Print &output);
+
+  bool run(WebServer &server, Middleware::Callback next) override;
+
+private:
+  Print *_out = nullptr;
+};
+
+class CorsMiddleware : public Middleware {
+public:
+  CorsMiddleware &setOrigin(const char *origin);
+  CorsMiddleware &setMethods(const char *methods);
+  CorsMiddleware &setHeaders(const char *headers);
+  CorsMiddleware &setAllowCredentials(bool credentials);
+  CorsMiddleware &setMaxAge(uint32_t seconds);
+
+  void addCORSHeaders(WebServer &server);
+
+  bool run(WebServer &server, Middleware::Callback next) override;
+
+private:
+  String _origin = F("*");
+  String _methods = F("*");
+  String _headers = F("*");
+  bool _credentials = true;
+  uint32_t _maxAge = 86400;
+};
+
+class AuthenticationMiddleware : public Middleware {
+public:
+  AuthenticationMiddleware &setUsername(const char *username);
+  AuthenticationMiddleware &setPassword(const char *password);
+  AuthenticationMiddleware &setPasswordHash(const char *sha1AsBase64orHex);
+  AuthenticationMiddleware &setCallback(WebServer::THandlerFunctionAuthCheck fn);
+
+  AuthenticationMiddleware &setRealm(const char *realm);
+  AuthenticationMiddleware &setAuthMethod(HTTPAuthMethod method);
+  AuthenticationMiddleware &setAuthFailureMessage(const char *message);
+
+  bool isAllowed(WebServer &server) const;
+
+  bool run(WebServer &server, Middleware::Callback next) override;
+
+private:
+  String _username;
+  String _password;
+  bool _hash = false;
+  WebServer::THandlerFunctionAuthCheck _callback;
+
+  const char *_realm = nullptr;
+  HTTPAuthMethod _method = BASIC_AUTH;
+  String _authFailMsg;
+};
+
+#endif
diff --git a/libraries/WebServer/src/Parsing.cpp b/libraries/WebServer/src/Parsing.cpp
index 1db2aef5541..3030317eeea 100644
--- a/libraries/WebServer/src/Parsing.cpp
+++ b/libraries/WebServer/src/Parsing.cpp
@@ -21,8 +21,8 @@
 
 #include <Arduino.h>
 #include <esp32-hal-log.h>
-#include "WiFiServer.h"
-#include "WiFiClient.h"
+#include "NetworkServer.h"
+#include "NetworkClient.h"
 #include "WebServer.h"
 #include "detail/mimetable.h"
 
@@ -30,28 +30,36 @@
 #define WEBSERVER_MAX_POST_ARGS 32
 #endif
 
+#define __STR(a) #a
+#define _STR(a)  __STR(a)
+static const char *_http_method_str[] = {
+#define XX(num, name, string) _STR(name),
+  HTTP_METHOD_MAP(XX)
+#undef XX
+};
+
 static const char Content_Type[] PROGMEM = "Content-Type";
 static const char filename[] PROGMEM = "filename";
 
-static char* readBytesWithTimeout(WiFiClient& client, size_t maxLength, size_t& dataLength, int timeout_ms)
-{
+static char *readBytesWithTimeout(NetworkClient &client, size_t maxLength, size_t &dataLength, int timeout_ms) {
   char *buf = nullptr;
   dataLength = 0;
   while (dataLength < maxLength) {
     int tries = timeout_ms;
     size_t newLength;
-    while (!(newLength = client.available()) && tries--) delay(1);
+    while (!(newLength = client.available()) && tries--) {
+      delay(1);
+    }
     if (!newLength) {
       break;
     }
     if (!buf) {
-      buf = (char *) malloc(newLength + 1);
+      buf = (char *)malloc(newLength + 1);
       if (!buf) {
         return nullptr;
       }
-    }
-    else {
-      char* newBuf = (char *) realloc(buf, dataLength + newLength + 1);
+    } else {
+      char *newBuf = (char *)realloc(buf, dataLength + newLength + 1);
       if (!newBuf) {
         free(buf);
         return nullptr;
@@ -65,14 +73,20 @@ static char* readBytesWithTimeout(WiFiClient& client, size_t maxLength, size_t&
   return buf;
 }
 
-bool WebServer::_parseRequest(WiFiClient& client) {
+bool WebServer::_parseRequest(NetworkClient &client) {
   // Read the first line of HTTP request
   String req = client.readStringUntil('\r');
   client.readStringUntil('\n');
   //reset header value
-  for (int i = 0; i < _headerKeysCount; ++i) {
-    _currentHeaders[i].value =String();
-   }
+  if (_collectAllHeaders) {
+    // clear previous headers
+    collectAllHeaders();
+  } else {
+    // clear previous headers
+    for (RequestArgument *header = _currentHeaders; header; header = header->next) {
+      header->value = String();
+    }
+  }
 
   // First line of HTTP request looks like "GET /path HTTP/1.1"
   // Retrieve the "/path" part by finding the spaces
@@ -89,99 +103,125 @@ bool WebServer::_parseRequest(WiFiClient& client) {
   _currentVersion = atoi(versionEnd.c_str());
   String searchStr = "";
   int hasSearch = url.indexOf('?');
-  if (hasSearch != -1){
+  if (hasSearch != -1) {
     searchStr = url.substring(hasSearch + 1);
     url = url.substring(0, hasSearch);
   }
   _currentUri = url;
   _chunked = false;
+  _clientContentLength = 0;  // not known yet, or invalid
 
-  HTTPMethod method = HTTP_GET;
-  if (methodStr == F("POST")) {
-    method = HTTP_POST;
-  } else if (methodStr == F("DELETE")) {
-    method = HTTP_DELETE;
-  } else if (methodStr == F("OPTIONS")) {
-    method = HTTP_OPTIONS;
-  } else if (methodStr == F("PUT")) {
-    method = HTTP_PUT;
-  } else if (methodStr == F("PATCH")) {
-    method = HTTP_PATCH;
+  HTTPMethod method = HTTP_ANY;
+  size_t num_methods = sizeof(_http_method_str) / sizeof(const char *);
+  for (size_t i = 0; i < num_methods; i++) {
+    if (methodStr == _http_method_str[i]) {
+      method = (HTTPMethod)i;
+      break;
+    }
+  }
+  if (method == HTTP_ANY) {
+    log_e("Unknown HTTP Method: %s", methodStr.c_str());
+    return false;
   }
   _currentMethod = method;
 
   log_v("method: %s url: %s search: %s", methodStr.c_str(), url.c_str(), searchStr.c_str());
 
   //attach handler
-  RequestHandler* handler;
+  RequestHandler *handler;
   for (handler = _firstHandler; handler; handler = handler->next()) {
-    if (handler->canHandle(_currentMethod, _currentUri))
+    if (handler->canHandle(*this, _currentMethod, _currentUri)) {
       break;
+    }
   }
   _currentHandler = handler;
 
   String formData;
   // below is needed only when POST type request
-  if (method == HTTP_POST || method == HTTP_PUT || method == HTTP_PATCH || method == HTTP_DELETE){
+  if (method == HTTP_POST || method == HTTP_PUT || method == HTTP_PATCH || method == HTTP_DELETE) {
     String boundaryStr;
     String headerName;
     String headerValue;
     bool isForm = false;
     bool isEncoded = false;
-    uint32_t contentLength = 0;
     //parse headers
-    while(1){
+    while (1) {
       req = client.readStringUntil('\r');
       client.readStringUntil('\n');
-      if (req == "") break;//no moar headers
+      if (req == "") {
+        break;  //no moar headers
+      }
       int headerDiv = req.indexOf(':');
-      if (headerDiv == -1){
+      if (headerDiv == -1) {
         break;
       }
       headerName = req.substring(0, headerDiv);
       headerValue = req.substring(headerDiv + 1);
       headerValue.trim();
-       _collectHeader(headerName.c_str(),headerValue.c_str());
+      _collectHeader(headerName.c_str(), headerValue.c_str());
 
-      log_v("headerName: %s", headerName.c_str());
-      log_v("headerValue: %s", headerValue.c_str());
-
-      if (headerName.equalsIgnoreCase(FPSTR(Content_Type))){
+      if (headerName.equalsIgnoreCase(FPSTR(Content_Type))) {
         using namespace mime;
-        if (headerValue.startsWith(FPSTR(mimeTable[txt].mimeType))){
+        if (headerValue.startsWith(FPSTR(mimeTable[txt].mimeType))) {
           isForm = false;
-        } else if (headerValue.startsWith(F("application/x-www-form-urlencoded"))){
+        } else if (headerValue.startsWith(F("application/x-www-form-urlencoded"))) {
           isForm = false;
           isEncoded = true;
-        } else if (headerValue.startsWith(F("multipart/"))){
+        } else if (headerValue.startsWith(F("multipart/"))) {
           boundaryStr = headerValue.substring(headerValue.indexOf('=') + 1);
-          boundaryStr.replace("\"","");
+          boundaryStr.replace("\"", "");
           isForm = true;
         }
-      } else if (headerName.equalsIgnoreCase(F("Content-Length"))){
-        contentLength = headerValue.toInt();
-      } else if (headerName.equalsIgnoreCase(F("Host"))){
+      } else if (headerName.equalsIgnoreCase(F("Content-Length"))) {
+        _clientContentLength = headerValue.toInt();
+      } else if (headerName.equalsIgnoreCase(F("Host"))) {
         _hostHeader = headerValue;
       }
     }
 
-    if (!isForm){
+    if (!isForm && _currentHandler && _currentHandler->canRaw(*this, _currentUri)) {
+      log_v("Parse raw");
+      _currentRaw.reset(new HTTPRaw());
+      _currentRaw->status = RAW_START;
+      _currentRaw->totalSize = 0;
+      _currentRaw->currentSize = 0;
+      log_v("Start Raw");
+      _currentHandler->raw(*this, _currentUri, *_currentRaw);
+      _currentRaw->status = RAW_WRITE;
+
+      while (_currentRaw->totalSize < _clientContentLength) {
+        size_t read_len = std::min(_clientContentLength - _currentRaw->totalSize, (size_t)HTTP_RAW_BUFLEN);
+        _currentRaw->currentSize = client.readBytes(_currentRaw->buf, read_len);
+        _currentRaw->totalSize += _currentRaw->currentSize;
+        if (_currentRaw->currentSize == 0) {
+          _currentRaw->status = RAW_ABORTED;
+          _currentHandler->raw(*this, _currentUri, *_currentRaw);
+          return false;
+        }
+        _currentHandler->raw(*this, _currentUri, *_currentRaw);
+      }
+      _currentRaw->status = RAW_END;
+      _currentHandler->raw(*this, _currentUri, *_currentRaw);
+      log_v("Finish Raw");
+    } else if (!isForm) {
       size_t plainLength;
-      char* plainBuf = readBytesWithTimeout(client, contentLength, plainLength, HTTP_MAX_POST_WAIT);
-      if (plainLength < contentLength) {
-      	free(plainBuf);
-      	return false;
+      char *plainBuf = readBytesWithTimeout(client, _clientContentLength, plainLength, HTTP_MAX_POST_WAIT);
+      if (plainLength < _clientContentLength) {
+        free(plainBuf);
+        return false;
       }
-      if (contentLength > 0) {
-        if(isEncoded){
+      if (_clientContentLength > 0) {
+        if (isEncoded) {
           //url encoded form
-          if (searchStr != "") searchStr += '&';
+          if (searchStr != "") {
+            searchStr += '&';
+          }
           searchStr += plainBuf;
         }
         _parseArguments(searchStr);
-        if(!isEncoded){
+        if (!isEncoded) {
           //plain post json or other data
-          RequestArgument& arg = _currentArgs[_currentArgCount++];
+          RequestArgument &arg = _currentArgs[_currentArgCount++];
           arg.key = F("plain");
           arg.value = String(plainBuf);
         }
@@ -192,11 +232,10 @@ bool WebServer::_parseRequest(WiFiClient& client) {
         // No content - but we can still have arguments in the URL.
         _parseArguments(searchStr);
       }
-    }
-
-    if (isForm){
+    } else {
+      // it IS a form
       _parseArguments(searchStr);
-      if (!_parseForm(client, boundaryStr, contentLength)) {
+      if (!_parseForm(client, boundaryStr, _clientContentLength)) {
         return false;
       }
     }
@@ -204,28 +243,27 @@ bool WebServer::_parseRequest(WiFiClient& client) {
     String headerName;
     String headerValue;
     //parse headers
-    while(1){
+    while (1) {
       req = client.readStringUntil('\r');
       client.readStringUntil('\n');
-      if (req == "") break;//no moar headers
+      if (req == "") {
+        break;  //no moar headers
+      }
       int headerDiv = req.indexOf(':');
-      if (headerDiv == -1){
+      if (headerDiv == -1) {
         break;
       }
       headerName = req.substring(0, headerDiv);
       headerValue = req.substring(headerDiv + 2);
-      _collectHeader(headerName.c_str(),headerValue.c_str());
+      _collectHeader(headerName.c_str(), headerValue.c_str());
 
-	  log_v("headerName: %s", headerName.c_str());
-	  log_v("headerValue: %s", headerValue.c_str());
-
-	  if (headerName.equalsIgnoreCase("Host")){
+      if (headerName.equalsIgnoreCase("Host")) {
         _hostHeader = headerValue;
       }
     }
     _parseArguments(searchStr);
   }
-  client.flush();
+  client.clear();
 
   log_v("Request: %s", url.c_str());
   log_v(" Arguments: %s", searchStr.c_str());
@@ -233,20 +271,38 @@ bool WebServer::_parseRequest(WiFiClient& client) {
   return true;
 }
 
-bool WebServer::_collectHeader(const char* headerName, const char* headerValue) {
-  for (int i = 0; i < _headerKeysCount; i++) {
-    if (_currentHeaders[i].key.equalsIgnoreCase(headerName)) {
-            _currentHeaders[i].value=headerValue;
-            return true;
-        }
+bool WebServer::_collectHeader(const char *headerName, const char *headerValue) {
+  RequestArgument *last = nullptr;
+  for (RequestArgument *header = _currentHeaders; header; header = header->next) {
+    if (header->next == nullptr) {
+      last = header;
+    }
+    if (header->key.equalsIgnoreCase(headerName)) {
+      header->value = headerValue;
+      log_v("header collected: %s: %s", headerName, headerValue);
+      return true;
+    }
+  }
+  assert(last);
+  if (_collectAllHeaders) {
+    last->next = new RequestArgument();
+    last->next->key = headerName;
+    last->next->value = headerValue;
+    _headerKeysCount++;
+    log_v("header collected: %s: %s", headerName, headerValue);
+    return true;
   }
+
+  log_v("header skipped: %s: %s", headerName, headerValue);
+
   return false;
 }
 
-void WebServer::_parseArguments(String data) {
+void WebServer::_parseArguments(const String &data) {
   log_v("args: %s", data.c_str());
-  if (_currentArgs)
+  if (_currentArgs) {
     delete[] _currentArgs;
+  }
   _currentArgs = 0;
   if (data.length() == 0) {
     _currentArgCount = 0;
@@ -255,16 +311,17 @@ void WebServer::_parseArguments(String data) {
   }
   _currentArgCount = 1;
 
-  for (int i = 0; i < (int)data.length(); ) {
+  for (int i = 0; i < (int)data.length();) {
     i = data.indexOf('&', i);
-    if (i == -1)
+    if (i == -1) {
       break;
+    }
     ++i;
     ++_currentArgCount;
   }
   log_v("args count: %d", _currentArgCount);
 
-  _currentArgs = new RequestArgument[_currentArgCount+1];
+  _currentArgs = new RequestArgument[_currentArgCount + 1];
   int pos = 0;
   int iarg;
   for (iarg = 0; iarg < _currentArgCount;) {
@@ -273,53 +330,58 @@ void WebServer::_parseArguments(String data) {
     log_v("pos %d =@%d &@%d", pos, equal_sign_index, next_arg_index);
     if ((equal_sign_index == -1) || ((equal_sign_index > next_arg_index) && (next_arg_index != -1))) {
       log_e("arg missing value: %d", iarg);
-      if (next_arg_index == -1)
+      if (next_arg_index == -1) {
         break;
+      }
       pos = next_arg_index + 1;
       continue;
     }
-    RequestArgument& arg = _currentArgs[iarg];
+    RequestArgument &arg = _currentArgs[iarg];
     arg.key = urlDecode(data.substring(pos, equal_sign_index));
     arg.value = urlDecode(data.substring(equal_sign_index + 1, next_arg_index));
     log_v("arg %d key: %s value: %s", iarg, arg.key.c_str(), arg.value.c_str());
     ++iarg;
-    if (next_arg_index == -1)
+    if (next_arg_index == -1) {
       break;
+    }
     pos = next_arg_index + 1;
   }
   _currentArgCount = iarg;
   log_v("args count: %d", _currentArgCount);
-
 }
 
-void WebServer::_uploadWriteByte(uint8_t b){
-  if (_currentUpload->currentSize == HTTP_UPLOAD_BUFLEN){
-    if(_currentHandler && _currentHandler->canUpload(_currentUri))
+void WebServer::_uploadWriteByte(uint8_t b) {
+  if (_currentUpload->currentSize == HTTP_UPLOAD_BUFLEN) {
+    if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) {
       _currentHandler->upload(*this, _currentUri, *_currentUpload);
+    }
     _currentUpload->totalSize += _currentUpload->currentSize;
     _currentUpload->currentSize = 0;
   }
   _currentUpload->buf[_currentUpload->currentSize++] = b;
 }
 
-int WebServer::_uploadReadByte(WiFiClient& client){
-  if (!client.connected()) return -1;
+int WebServer::_uploadReadByte(NetworkClient &client) {
   int res = client.read();
-  if(res < 0) {
+
+  if (res < 0) {
     // keep trying until you either read a valid byte or timeout
-    unsigned long startMillis = millis();
-    long timeoutIntervalMillis = client.getTimeout();
-    boolean timedOut = false;
-    for(;;) {
+    const unsigned long startMillis = millis();
+    const long timeoutIntervalMillis = client.getTimeout();
+    bool timedOut = false;
+    for (;;) {
+      if (!client.connected()) {
+        return -1;
+      }
       // loosely modeled after blinkWithoutDelay pattern
-      while(!timedOut && !client.available() && client.connected()){
+      while (!timedOut && !client.available() && client.connected()) {
         delay(2);
-        timedOut = millis() - startMillis >= timeoutIntervalMillis;
+        timedOut = (millis() - startMillis) >= timeoutIntervalMillis;
       }
 
       res = client.read();
-      if(res >= 0) {
-        return res; // exit on a valid read
+      if (res >= 0) {
+        return res;  // exit on a valid read
       }
       // NOTE: it is possible to get here and have all of the following
       //       assertions hold true
@@ -333,9 +395,9 @@ int WebServer::_uploadReadByte(WiFiClient& client){
       //       is elusive, and possibly indicative of a more subtle underlying
       //       issue
 
-      timedOut = millis() - startMillis >= timeoutIntervalMillis;
-      if(timedOut) {
-        return res; // exit on a timeout
+      timedOut = (millis() - startMillis) >= timeoutIntervalMillis;
+      if (timedOut) {
+        return res;  // exit on a timeout
       }
     }
   }
@@ -343,8 +405,8 @@ int WebServer::_uploadReadByte(WiFiClient& client){
   return res;
 }
 
-bool WebServer::_parseForm(WiFiClient& client, String boundary, uint32_t len){
-  (void) len;
+bool WebServer::_parseForm(NetworkClient &client, const String &boundary, uint32_t len) {
+  (void)len;
   log_v("Parse Form: Boundary: %s Length: %d", boundary.c_str(), len);
   String line;
   int retry = 0;
@@ -355,11 +417,13 @@ bool WebServer::_parseForm(WiFiClient& client, String boundary, uint32_t len){
 
   client.readStringUntil('\n');
   //start reading the form
-  if (line == ("--"+boundary)){
-   if(_postArgs) delete[] _postArgs;
+  if (line == ("--" + boundary)) {
+    if (_postArgs) {
+      delete[] _postArgs;
+    }
     _postArgs = new RequestArgument[WEBSERVER_MAX_POST_ARGS];
     _postArgsLen = 0;
-    while(1){
+    while (1) {
       String argName;
       String argValue;
       String argType;
@@ -368,49 +432,56 @@ bool WebServer::_parseForm(WiFiClient& client, String boundary, uint32_t len){
 
       line = client.readStringUntil('\r');
       client.readStringUntil('\n');
-      if (line.length() > 19 && line.substring(0, 19).equalsIgnoreCase(F("Content-Disposition"))){
+      if (line.length() > 19 && line.substring(0, 19).equalsIgnoreCase(F("Content-Disposition"))) {
         int nameStart = line.indexOf('=');
-        if (nameStart != -1){
-          argName = line.substring(nameStart+2);
+        if (nameStart != -1) {
+          argName = line.substring(nameStart + 2);
           nameStart = argName.indexOf('=');
-          if (nameStart == -1){
+          if (nameStart == -1) {
             argName = argName.substring(0, argName.length() - 1);
           } else {
-            argFilename = argName.substring(nameStart+2, argName.length() - 1);
+            argFilename = argName.substring(nameStart + 2, argName.length() - 1);
             argName = argName.substring(0, argName.indexOf('"'));
             argIsFile = true;
-            log_v("PostArg FileName: %s",argFilename.c_str());
+            log_v("PostArg FileName: %s", argFilename.c_str());
             //use GET to set the filename if uploading using blob
-            if (argFilename == F("blob") && hasArg(FPSTR(filename)))
+            if (argFilename == F("blob") && hasArg(FPSTR(filename))) {
               argFilename = arg(FPSTR(filename));
+            }
           }
           log_v("PostArg Name: %s", argName.c_str());
           using namespace mime;
           argType = FPSTR(mimeTable[txt].mimeType);
           line = client.readStringUntil('\r');
           client.readStringUntil('\n');
-          if (line.length() > 12 && line.substring(0, 12).equalsIgnoreCase(FPSTR(Content_Type))){
-            argType = line.substring(line.indexOf(':')+2);
-            //skip next line
-            client.readStringUntil('\r');
+          while (line.length() > 0) {
+            if (line.length() > 12 && line.substring(0, 12).equalsIgnoreCase(FPSTR(Content_Type))) {
+              argType = line.substring(line.indexOf(':') + 2);
+            }
+            //skip over any other headers
+            line = client.readStringUntil('\r');
             client.readStringUntil('\n');
           }
           log_v("PostArg Type: %s", argType.c_str());
-          if (!argIsFile){
-            while(1){
+          if (!argIsFile) {
+            while (1) {
               line = client.readStringUntil('\r');
               client.readStringUntil('\n');
-              if (line.startsWith("--"+boundary)) break;
-              if (argValue.length() > 0) argValue += "\n";
+              if (line.startsWith("--" + boundary)) {
+                break;
+              }
+              if (argValue.length() > 0) {
+                argValue += "\n";
+              }
               argValue += line;
             }
             log_v("PostArg Value: %s", argValue.c_str());
 
-            RequestArgument& arg = _postArgs[_postArgsLen++];
+            RequestArgument &arg = _postArgs[_postArgsLen++];
             arg.key = argName;
             arg.value = argValue;
 
-            if (line == ("--"+boundary+"--")){
+            if (line == ("--" + boundary + "--")) {
               log_v("Done Parsing POST");
               break;
             } else if (_postArgsLen >= WEBSERVER_MAX_POST_ARGS) {
@@ -426,114 +497,89 @@ bool WebServer::_parseForm(WiFiClient& client, String boundary, uint32_t len){
             _currentUpload->totalSize = 0;
             _currentUpload->currentSize = 0;
             log_v("Start File: %s Type: %s", _currentUpload->filename.c_str(), _currentUpload->type.c_str());
-            if(_currentHandler && _currentHandler->canUpload(_currentUri))
+            if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) {
               _currentHandler->upload(*this, _currentUri, *_currentUpload);
-            _currentUpload->status = UPLOAD_FILE_WRITE;
-            int argByte = _uploadReadByte(client);
-readfile:
-
-            while(argByte != 0x0D){
-                if(argByte < 0) return _parseFormUploadAborted();
-                _uploadWriteByte(argByte);
-                argByte = _uploadReadByte(client);
             }
+            _currentUpload->status = UPLOAD_FILE_WRITE;
 
-            argByte = _uploadReadByte(client);
-            if(argByte < 0) return _parseFormUploadAborted();
-            if (argByte == 0x0A){
-              argByte = _uploadReadByte(client);
-              if(argByte < 0) return _parseFormUploadAborted();
-              if ((char)argByte != '-'){
-                //continue reading the file
-                _uploadWriteByte(0x0D);
-                _uploadWriteByte(0x0A);
-                goto readfile;
-              } else {
-                argByte = _uploadReadByte(client);
-                if(argByte < 0) return _parseFormUploadAborted();
-                if ((char)argByte != '-'){
-                  //continue reading the file
-                  _uploadWriteByte(0x0D);
-                  _uploadWriteByte(0x0A);
-                  _uploadWriteByte((uint8_t)('-'));
-                  goto readfile;
-                }
-              }
-
-              uint8_t endBuf[boundary.length()];
-              uint32_t i = 0;
-              while(i < boundary.length()){
-                argByte = _uploadReadByte(client);
-                if(argByte < 0) return _parseFormUploadAborted();
-                if ((char)argByte == 0x0D){
-                  _uploadWriteByte(0x0D);
-                  _uploadWriteByte(0x0A);
-                  _uploadWriteByte((uint8_t)('-'));
-                  _uploadWriteByte((uint8_t)('-'));
-                  uint32_t j = 0;
-                  while(j < i){
-                    _uploadWriteByte(endBuf[j++]);
-                  }
-                  goto readfile;
-                }
-                endBuf[i++] = (uint8_t)argByte;
+            int fastBoundaryLen = 4 /* \r\n-- */ + boundary.length() + 1 /* \0 */;
+            char fastBoundary[fastBoundaryLen];
+            snprintf(fastBoundary, fastBoundaryLen, "\r\n--%s", boundary.c_str());
+            int boundaryPtr = 0;
+            while (true) {
+              int ret = _uploadReadByte(client);
+              if (ret < 0) {
+                // Unexpected, we should have had data available per above
+                return _parseFormUploadAborted();
               }
-
-              if (strstr((const char*)endBuf, boundary.c_str()) != NULL){
-                if(_currentHandler && _currentHandler->canUpload(_currentUri))
-                  _currentHandler->upload(*this, _currentUri, *_currentUpload);
-                _currentUpload->totalSize += _currentUpload->currentSize;
-                _currentUpload->status = UPLOAD_FILE_END;
-                if(_currentHandler && _currentHandler->canUpload(_currentUri))
-                  _currentHandler->upload(*this, _currentUri, *_currentUpload);
-                log_v("End File: %s Type: %s Size: %d", _currentUpload->filename.c_str(), _currentUpload->type.c_str(), _currentUpload->totalSize);
-                line = client.readStringUntil(0x0D);
-                client.readStringUntil(0x0A);
-                if (line == "--"){
-                  log_v("Done Parsing POST");
+              char in = (char)ret;
+              if (in == fastBoundary[boundaryPtr]) {
+                // The input matched the current expected character, advance and possibly exit this file
+                boundaryPtr++;
+                if (boundaryPtr == fastBoundaryLen - 1) {
+                  // We read the whole boundary line, we're done here!
                   break;
                 }
-                continue;
               } else {
-                _uploadWriteByte(0x0D);
-                _uploadWriteByte(0x0A);
-                _uploadWriteByte((uint8_t)('-'));
-                _uploadWriteByte((uint8_t)('-'));
-                uint32_t i = 0;
-                while(i < boundary.length()){
-                  _uploadWriteByte(endBuf[i++]);
+                // The char doesn't match what we want, so dump whatever matches we had, the read in char, and reset ptr to start
+                for (int i = 0; i < boundaryPtr; i++) {
+                  _uploadWriteByte(fastBoundary[i]);
+                }
+                if (in == fastBoundary[0]) {
+                  // This could be the start of the real end, mark it so and don't emit/skip it
+                  boundaryPtr = 1;
+                } else {
+                  // Not the 1st char of our pattern, so emit and ignore
+                  _uploadWriteByte(in);
+                  boundaryPtr = 0;
                 }
-                argByte = _uploadReadByte(client);
-                goto readfile;
               }
-            } else {
-              _uploadWriteByte(0x0D);
-              goto readfile;
             }
-            break;
+            // Found the boundary string, finish processing this file upload
+            if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) {
+              _currentHandler->upload(*this, _currentUri, *_currentUpload);
+            }
+            _currentUpload->totalSize += _currentUpload->currentSize;
+            _currentUpload->status = UPLOAD_FILE_END;
+            if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) {
+              _currentHandler->upload(*this, _currentUri, *_currentUpload);
+            }
+            log_v("End File: %s Type: %s Size: %d", _currentUpload->filename.c_str(), _currentUpload->type.c_str(), (int)_currentUpload->totalSize);
+            if (!client.connected()) {
+              return _parseFormUploadAborted();
+            }
+            line = client.readStringUntil('\r');
+            client.readStringUntil('\n');
+            if (line == "--") {  // extra two dashes mean we reached the end of all form fields
+              log_v("Done Parsing POST");
+              break;
+            }
+            continue;
           }
         }
       }
     }
 
     int iarg;
-    int totalArgs = ((WEBSERVER_MAX_POST_ARGS - _postArgsLen) < _currentArgCount)?(WEBSERVER_MAX_POST_ARGS - _postArgsLen):_currentArgCount;
-    for (iarg = 0; iarg < totalArgs; iarg++){
-      RequestArgument& arg = _postArgs[_postArgsLen++];
+    int totalArgs = ((WEBSERVER_MAX_POST_ARGS - _postArgsLen) < _currentArgCount) ? (WEBSERVER_MAX_POST_ARGS - _postArgsLen) : _currentArgCount;
+    for (iarg = 0; iarg < totalArgs; iarg++) {
+      RequestArgument &arg = _postArgs[_postArgsLen++];
       arg.key = _currentArgs[iarg].key;
       arg.value = _currentArgs[iarg].value;
     }
-    if (_currentArgs) delete[] _currentArgs;
+    if (_currentArgs) {
+      delete[] _currentArgs;
+    }
     _currentArgs = new RequestArgument[_postArgsLen];
-    for (iarg = 0; iarg < _postArgsLen; iarg++){
-      RequestArgument& arg = _currentArgs[iarg];
+    for (iarg = 0; iarg < _postArgsLen; iarg++) {
+      RequestArgument &arg = _currentArgs[iarg];
       arg.key = _postArgs[iarg].key;
       arg.value = _postArgs[iarg].value;
     }
     _currentArgCount = iarg;
     if (_postArgs) {
       delete[] _postArgs;
-      _postArgs=nullptr;
+      _postArgs = nullptr;
       _postArgsLen = 0;
     }
     return true;
@@ -542,40 +588,35 @@ bool WebServer::_parseForm(WiFiClient& client, String boundary, uint32_t len){
   return false;
 }
 
-String WebServer::urlDecode(const String& text)
-{
-	String decoded = "";
-	char temp[] = "0x00";
-	unsigned int len = text.length();
-	unsigned int i = 0;
-	while (i < len)
-	{
-		char decodedChar;
-		char encodedChar = text.charAt(i++);
-		if ((encodedChar == '%') && (i + 1 < len))
-		{
-			temp[2] = text.charAt(i++);
-			temp[3] = text.charAt(i++);
-
-			decodedChar = strtol(temp, NULL, 16);
-		}
-		else {
-			if (encodedChar == '+')
-			{
-				decodedChar = ' ';
-			}
-			else {
-				decodedChar = encodedChar;  // normal ascii char
-			}
-		}
-		decoded += decodedChar;
-	}
-	return decoded;
+String WebServer::urlDecode(const String &text) {
+  String decoded = "";
+  char temp[] = "0x00";
+  unsigned int len = text.length();
+  unsigned int i = 0;
+  while (i < len) {
+    char decodedChar;
+    char encodedChar = text.charAt(i++);
+    if ((encodedChar == '%') && (i + 1 < len)) {
+      temp[2] = text.charAt(i++);
+      temp[3] = text.charAt(i++);
+
+      decodedChar = strtol(temp, NULL, 16);
+    } else {
+      if (encodedChar == '+') {
+        decodedChar = ' ';
+      } else {
+        decodedChar = encodedChar;  // normal ascii char
+      }
+    }
+    decoded += decodedChar;
+  }
+  return decoded;
 }
 
-bool WebServer::_parseFormUploadAborted(){
+bool WebServer::_parseFormUploadAborted() {
   _currentUpload->status = UPLOAD_FILE_ABORTED;
-  if(_currentHandler && _currentHandler->canUpload(_currentUri))
+  if (_currentHandler && _currentHandler->canUpload(*this, _currentUri)) {
     _currentHandler->upload(*this, _currentUri, *_currentUpload);
+  }
   return false;
 }
diff --git a/libraries/WebServer/src/Uri.h b/libraries/WebServer/src/Uri.h
index d924a0bd0b1..34ec756d5e6 100644
--- a/libraries/WebServer/src/Uri.h
+++ b/libraries/WebServer/src/Uri.h
@@ -6,24 +6,24 @@
 
 class Uri {
 
-    protected:
-        const String _uri;
+protected:
+  const String _uri;
 
-    public:
-        Uri(const char *uri) : _uri(uri) {}
-        Uri(const String &uri) : _uri(uri) {}
-        Uri(const __FlashStringHelper *uri) : _uri(String(uri)) {} 
-        virtual ~Uri() {}
+public:
+  Uri(const char *uri) : _uri(uri) {}
+  Uri(const String &uri) : _uri(uri) {}
+  Uri(const __FlashStringHelper *uri) : _uri((const char *)uri) {}
+  virtual ~Uri() {}
 
-        virtual Uri* clone() const {
-            return new Uri(_uri);
-        };
+  virtual Uri *clone() const {
+    return new Uri(_uri);
+  };
 
-        virtual void initPathArgs(__attribute__((unused)) std::vector<String> &pathArgs) {}
+  virtual void initPathArgs(__attribute__((unused)) std::vector<String> &pathArgs) {}
 
-        virtual bool canHandle(const String &requestUri, __attribute__((unused)) std::vector<String> &pathArgs) {
-            return _uri == requestUri;
-        }
+  virtual bool canHandle(const String &requestUri, __attribute__((unused)) std::vector<String> &pathArgs) {
+    return _uri == requestUri;
+  }
 };
 
 #endif
diff --git a/libraries/WebServer/src/WebServer.cpp b/libraries/WebServer/src/WebServer.cpp
index 35d316308df..652a86f587f 100644
--- a/libraries/WebServer/src/WebServer.cpp
+++ b/libraries/WebServer/src/WebServer.cpp
@@ -20,78 +20,49 @@
   Modified 8 May 2015 by Hristo Gochkov (proper post and file upload handling)
 */
 
-
 #include <Arduino.h>
 #include <esp32-hal-log.h>
+#include <libb64/cdecode.h>
 #include <libb64/cencode.h>
-#include "WiFiServer.h"
-#include "WiFiClient.h"
+#include "esp_random.h"
+#include "NetworkServer.h"
+#include "NetworkClient.h"
 #include "WebServer.h"
 #include "FS.h"
 #include "detail/RequestHandlersImpl.h"
-#include "mbedtls/md5.h"
-
+#include "MD5Builder.h"
+#include "SHA1Builder.h"
+#include "base64.h"
 
 static const char AUTHORIZATION_HEADER[] = "Authorization";
-static const char qop_auth[] = "qop=\"auth\"";
+static const char qop_auth[] PROGMEM = "qop=auth";
+static const char qop_auth_quoted[] PROGMEM = "qop=\"auth\"";
 static const char WWW_Authenticate[] = "WWW-Authenticate";
 static const char Content_Length[] = "Content-Length";
+static const char ETAG_HEADER[] = "If-None-Match";
 
+WebServer::WebServer(IPAddress addr, int port) : _server(addr, port) {
+  log_v("WebServer::Webserver(addr=%s, port=%d)", addr.toString().c_str(), port);
+}
 
-WebServer::WebServer(IPAddress addr, int port)
-: _corsEnabled(false)
-, _server(addr, port)
-, _currentMethod(HTTP_ANY)
-, _currentVersion(0)
-, _currentStatus(HC_NONE)
-, _statusChange(0)
-, _nullDelay(true)
-, _currentHandler(nullptr)
-, _firstHandler(nullptr)
-, _lastHandler(nullptr)
-, _currentArgCount(0)
-, _currentArgs(nullptr)
-, _postArgsLen(0)
-, _postArgs(nullptr)
-, _headerKeysCount(0)
-, _currentHeaders(nullptr)
-, _contentLength(0)
-, _chunked(false)
-{
-}
-
-WebServer::WebServer(int port)
-: _corsEnabled(false)
-, _server(port)
-, _currentMethod(HTTP_ANY)
-, _currentVersion(0)
-, _currentStatus(HC_NONE)
-, _statusChange(0)
-, _nullDelay(true)
-, _currentHandler(nullptr)
-, _firstHandler(nullptr)
-, _lastHandler(nullptr)
-, _currentArgCount(0)
-, _currentArgs(nullptr)
-, _postArgsLen(0)
-, _postArgs(nullptr)
-, _headerKeysCount(0)
-, _currentHeaders(nullptr)
-, _contentLength(0)
-, _chunked(false)
-{
+WebServer::WebServer(int port) : _server(port) {
+  log_v("WebServer::Webserver(port=%d)", port);
 }
 
 WebServer::~WebServer() {
   _server.close();
-  if (_currentHeaders)
-    delete[]_currentHeaders;
-  RequestHandler* handler = _firstHandler;
+
+  _clearRequestHeaders();
+  _clearResponseHeaders();
+  delete _chain;
+
+  RequestHandler *handler = _firstHandler;
   while (handler) {
-    RequestHandler* next = handler->next();
+    RequestHandler *next = handler->next();
     delete handler;
     handler = next;
   }
+  _firstHandler = nullptr;
 }
 
 void WebServer::begin() {
@@ -106,191 +77,344 @@ void WebServer::begin(uint16_t port) {
   _server.setNoDelay(true);
 }
 
-String WebServer::_extractParam(String& authReq,const String& param,const char delimit){
+String WebServer::_extractParam(String &authReq, const String &param, const char delimit) {
   int _begin = authReq.indexOf(param);
-  if (_begin == -1)
+  if (_begin == -1) {
     return "";
-  return authReq.substring(_begin+param.length(),authReq.indexOf(delimit,_begin+param.length()));
-}
-
-static String md5str(String &in){
-  char out[33] = {0};
-  mbedtls_md5_context _ctx;
-  uint8_t i;
-  uint8_t * _buf = (uint8_t*)malloc(16);
-  if(_buf == NULL)
-    return String(out);
-  memset(_buf, 0x00, 16);
-  mbedtls_md5_init(&_ctx);
-  mbedtls_md5_starts(&_ctx);
-  mbedtls_md5_update(&_ctx, (const uint8_t *)in.c_str(), in.length());
-  mbedtls_md5_finish(&_ctx, _buf);
-  for(i = 0; i < 16; i++) {
-    sprintf(out + (i * 2), "%02x", _buf[i]);
-  }
-  out[32] = 0;
-  free(_buf);
-  return String(out);
-}
-
-bool WebServer::authenticate(const char * username, const char * password){
-  if(hasHeader(FPSTR(AUTHORIZATION_HEADER))) {
-    String authReq = header(FPSTR(AUTHORIZATION_HEADER));
-    if(authReq.startsWith(F("Basic"))){
-      authReq = authReq.substring(6);
-      authReq.trim();
-      char toencodeLen = strlen(username)+strlen(password)+1;
-      char *toencode = new char[toencodeLen + 1];
-      if(toencode == NULL){
-        authReq = "";
-        return false;
-      }
-      char *encoded = new char[base64_encode_expected_len(toencodeLen)+1];
-      if(encoded == NULL){
-        authReq = "";
-        delete[] toencode;
-        return false;
-      }
-      sprintf(toencode, "%s:%s", username, password);
-      if(base64_encode_chars(toencode, toencodeLen, encoded) > 0 && authReq.equalsConstantTime(encoded)) {
-        authReq = "";
-        delete[] toencode;
-        delete[] encoded;
-        return true;
-      }
-      delete[] toencode;
-      delete[] encoded;
-    } else if(authReq.startsWith(F("Digest"))) {
-      authReq = authReq.substring(7);
-      log_v("%s", authReq.c_str());
-      String _username = _extractParam(authReq,F("username=\""),'\"');
-      if(!_username.length() || _username != String(username)) {
-        authReq = "";
-        return false;
-      }
-      // extracting required parameters for RFC 2069 simpler Digest
-      String _realm    = _extractParam(authReq, F("realm=\""),'\"');
-      String _nonce    = _extractParam(authReq, F("nonce=\""),'\"');
-      String _uri      = _extractParam(authReq, F("uri=\""),'\"');
-      String _response = _extractParam(authReq, F("response=\""),'\"');
-      String _opaque   = _extractParam(authReq, F("opaque=\""),'\"');
-
-      if((!_realm.length()) || (!_nonce.length()) || (!_uri.length()) || (!_response.length()) || (!_opaque.length())) {
-        authReq = "";
-        return false;
-      }
-      if((_opaque != _sopaque) || (_nonce != _snonce) || (_realm != _srealm)) {
-        authReq = "";
-        return false;
-      }
-      // parameters for the RFC 2617 newer Digest
-      String _nc,_cnonce;
-      if(authReq.indexOf(FPSTR(qop_auth)) != -1) {
-        _nc = _extractParam(authReq, F("nc="), ',');
-        _cnonce = _extractParam(authReq, F("cnonce=\""),'\"');
-      }
-      String _H1 = md5str(String(username) + ':' + _realm + ':' + String(password));
-      log_v("Hash of user:realm:pass=%s", _H1.c_str());
-      String _H2 = "";
-      if(_currentMethod == HTTP_GET){
-          _H2 = md5str(String(F("GET:")) + _uri);
-      }else if(_currentMethod == HTTP_POST){
-          _H2 = md5str(String(F("POST:")) + _uri);
-      }else if(_currentMethod == HTTP_PUT){
-          _H2 = md5str(String(F("PUT:")) + _uri);
-      }else if(_currentMethod == HTTP_DELETE){
-          _H2 = md5str(String(F("DELETE:")) + _uri);
-      }else{
-          _H2 = md5str(String(F("GET:")) + _uri);
-      }
-      log_v("Hash of GET:uri=%s", _H2.c_str());
-      String _responsecheck = "";
-      if(authReq.indexOf(FPSTR(qop_auth)) != -1) {
-          _responsecheck = md5str(_H1 + ':' + _nonce + ':' + _nc + ':' + _cnonce + F(":auth:") + _H2);
-      } else {
-          _responsecheck = md5str(_H1 + ':' + _nonce + ':' + _H2);
-      }
-      log_v("The Proper response=%s", _responsecheck.c_str());
-      if(_response == _responsecheck){
+  }
+  return authReq.substring(_begin + param.length(), authReq.indexOf(delimit, _begin + param.length()));
+}
+
+static String md5str(String &in) {
+  MD5Builder md5 = MD5Builder();
+  md5.begin();
+  md5.add(in);
+  md5.calculate();
+  return md5.toString();
+}
+
+bool WebServer::authenticateBasicSHA1(const char *_username, const char *_sha1Base64orHex) {
+  return WebServer::authenticate([_username, _sha1Base64orHex](HTTPAuthMethod mode, String username, String params[]) -> String * {
+    // rather than work on a password to compare with; we take the sha1 of the
+    // password received over the wire and compare that to the base64 encoded
+    // sha1 passed as _sha1base64. That way there is no need to have a
+    // plaintext password in the code/binary (though note that SHA1 is well
+    // past its retirement age). When that matches - we `cheat' by returning
+    // the password we got in the first place; so the normal BasicAuth
+    // can be completed. Note that this cannot work for a digest auth -
+    // as there the password in the clear is part of the calculation.
+
+    if (params == nullptr) {
+      log_e("Something went wrong. params is NULL");
+      return NULL;
+    }
+
+    uint8_t sha1[20];
+    char sha1calc[48];  // large enough for base64 and Hex representation
+    String ret;
+    SHA1Builder sha_builder;
+    base64 b64;
+
+    log_v("Trying to authenticate user %s using SHA1.", username.c_str());
+    sha_builder.begin();
+    sha_builder.add((uint8_t *)params[0].c_str(), params[0].length());
+    sha_builder.calculate();
+    sha_builder.getBytes(sha1);
+
+    // we can either decode _sha1base64orHex and then compare the 20 bytes;
+    // or encode the sha we calculated. We pick the latter as encoding of a
+    // fixed array of 20 bytes is safer than operating on something external.
+    if (strlen(_sha1Base64orHex) == 20 * 2) {  // 2 chars per byte
+      sha_builder.bytes2hex(sha1calc, sizeof(sha1calc), sha1, sizeof(sha1));
+      log_v("Calculated SHA1 in hex: %s", sha1calc);
+    } else {
+      ret = b64.encode(sha1, sizeof(sha1));
+      ret.toCharArray(sha1calc, sizeof(sha1calc));
+      log_v("Calculated SHA1 in base64: %s", sha1calc);
+    }
+
+    return ((username.equalsConstantTime(_username)) && (String((char *)sha1calc).equalsConstantTime(_sha1Base64orHex))
+            && (mode == BASIC_AUTH) /* to keep things somewhat time constant. */
+           )
+             ? new String(params[0])
+             : NULL;
+  });
+}
+
+bool WebServer::authenticate(const char *_username, const char *_password) {
+  return WebServer::authenticate([_username, _password](HTTPAuthMethod mode, String username, String params[]) -> String * {
+    return username.equalsConstantTime(_username) ? new String(_password) : NULL;
+  });
+}
+
+bool WebServer::authenticate(THandlerFunctionAuthCheck fn) {
+  if (!hasHeader(FPSTR(AUTHORIZATION_HEADER))) {
+    return false;
+  }
+
+  String authReq = header(FPSTR(AUTHORIZATION_HEADER));
+  if (authReq.startsWith(AuthTypeBasic)) {
+    log_v("Trying to authenticate using Basic Auth");
+    bool ret = false;
+
+    authReq = authReq.substring(6);  // length of AuthTypeBasic including the space at the end.
+    authReq.trim();
+
+    /* base64 encoded string is always shorter (or equal) in length */
+    char *decoded = (authReq.length() < HTTP_MAX_BASIC_AUTH_LEN) ? new char[authReq.length()] : NULL;
+    if (decoded) {
+      char *p;
+      if (base64_decode_chars(authReq.c_str(), authReq.length(), decoded) && (p = index(decoded, ':')) && p) {
         authReq = "";
-        return true;
+        /* Note: rfc7617 guarantees that there will not be an escaped colon in the username itself.
+         * Note:  base64_decode_chars() guarantees a terminating \0
+         */
+        *p = '\0';
+        char *_username = decoded, *_password = p + 1;
+        String params[] = {_password, _srealm};
+        String *password = fn(BASIC_AUTH, _username, params);
+
+        if (password) {
+          ret = password->equalsConstantTime(_password);
+          // we're more concerned about the password; as the attacker already
+          // knows the _pasword. Arduino's string handling is simple; it reallocs
+          // even when smaller; so a memset is enough (no capacity/size).
+          memset((void *)password->c_str(), 0, password->length());
+          delete password;
+        }
       }
+      delete[] decoded;
     }
     authReq = "";
+    log_v("Authentication %s", ret ? "Success" : "Failed");
+    return ret;
+  } else if (authReq.startsWith(AuthTypeDigest)) {
+    log_v("Trying to authenticate using Digest Auth");
+    authReq = authReq.substring(7);
+    log_v("%s", authReq.c_str());
+
+    // extracting required parameters for RFC 2069 simpler Digest
+    String _username = _extractParam(authReq, F("username=\""), '\"');
+    String _realm = _extractParam(authReq, F("realm=\""), '\"');
+    String _uri = _extractParam(authReq, F("uri=\""), '\"');
+    if (!_username.length()) {
+      goto exf;
+    }
+
+    String params[] = {_realm, _uri};
+    String *password = fn(DIGEST_AUTH, _username, params);
+    if (!password) {
+      goto exf;
+    }
+
+    String _H1 = md5str(String(_username) + ':' + _realm + ':' + *password);
+    // we're extra concerned; as digest request us to know the password
+    // in the clear.
+    memset((void *)password->c_str(), 0, password->length());
+    delete password;
+    _username = "";
+
+    String _nonce = _extractParam(authReq, F("nonce=\""), '\"');
+    String _response = _extractParam(authReq, F("response=\""), '\"');
+    String _opaque = _extractParam(authReq, F("opaque=\""), '\"');
+
+    if ((!_realm.length()) || (!_nonce.length()) || (!_uri.length()) || (!_response.length()) || (!_opaque.length())) {
+      goto exf;
+    }
+
+    if ((_opaque != _sopaque) || (_nonce != _snonce) || (_realm != _srealm)) {
+      goto exf;
+    }
+
+    // parameters for the RFC 2617 newer Digest
+    String _nc, _cnonce;
+    if (authReq.indexOf(FPSTR(qop_auth)) != -1 || authReq.indexOf(FPSTR(qop_auth_quoted)) != -1) {
+      _nc = _extractParam(authReq, F("nc="), ',');
+      _cnonce = _extractParam(authReq, F("cnonce=\""), '\"');
+    }
+
+    log_v("Hash of user:realm:pass=%s", _H1.c_str());
+    String _H2 = "";
+    if (_currentMethod == HTTP_GET) {
+      _H2 = md5str(String(F("GET:")) + _uri);
+    } else if (_currentMethod == HTTP_POST) {
+      _H2 = md5str(String(F("POST:")) + _uri);
+    } else if (_currentMethod == HTTP_PUT) {
+      _H2 = md5str(String(F("PUT:")) + _uri);
+    } else if (_currentMethod == HTTP_DELETE) {
+      _H2 = md5str(String(F("DELETE:")) + _uri);
+    } else {
+      _H2 = md5str(String(F("GET:")) + _uri);
+    }
+    log_v("Hash of GET:uri=%s", _H2.c_str());
+    String _responsecheck = "";
+    if (authReq.indexOf(FPSTR(qop_auth)) != -1 || authReq.indexOf(FPSTR(qop_auth_quoted)) != -1) {
+      _responsecheck = md5str(_H1 + ':' + _nonce + ':' + _nc + ':' + _cnonce + F(":auth:") + _H2);
+    } else {
+      _responsecheck = md5str(_H1 + ':' + _nonce + ':' + _H2);
+    }
+    authReq = "";
+
+    log_v("The Proper response=%s", _responsecheck.c_str());
+    bool ret = _response == _responsecheck;
+    log_v("Authentication %s", ret ? "Success" : "Failed");
+    return ret;
+  } else if (authReq.length()) {
+    // OTHER_AUTH
+    log_v("Trying to authenticate using Other Auth, authReq=%s", authReq.c_str());
+    String *ret = fn(OTHER_AUTH, authReq, {});
+    if (ret) {
+      log_v("Authentication Success");
+      delete ret;
+      return true;
+    }
   }
+exf:
+  authReq = "";
+  log_v("Authentication Failed");
   return false;
 }
 
 String WebServer::_getRandomHexString() {
   char buffer[33];  // buffer to hold 32 Hex Digit + /0
   int i;
-  for(i = 0; i < 4; i++) {
-    sprintf (buffer + (i*8), "%08x", esp_random());
+  for (i = 0; i < 4; i++) {
+    sprintf(buffer + (i * 8), "%08lx", esp_random());
   }
   return String(buffer);
 }
 
-void WebServer::requestAuthentication(HTTPAuthMethod mode, const char* realm, const String& authFailMsg) {
-  if(realm == NULL) {
+void WebServer::requestAuthentication(HTTPAuthMethod mode, const char *realm, const String &authFailMsg) {
+  if (realm == NULL) {
     _srealm = String(F("Login Required"));
   } else {
     _srealm = String(realm);
   }
-  if(mode == BASIC_AUTH) {
-    sendHeader(String(FPSTR(WWW_Authenticate)), String(F("Basic realm=\"")) + _srealm + String(F("\"")));
+  if (mode == BASIC_AUTH) {
+    sendHeader(String(FPSTR(WWW_Authenticate)), AuthTypeBasic + String(F(" realm=\"")) + _srealm + String(F("\"")));
   } else {
-    _snonce=_getRandomHexString();
-    _sopaque=_getRandomHexString();
-    sendHeader(String(FPSTR(WWW_Authenticate)), String(F("Digest realm=\"")) +_srealm + String(F("\", qop=\"auth\", nonce=\"")) + _snonce + String(F("\", opaque=\"")) + _sopaque + String(F("\"")));
+    _snonce = _getRandomHexString();
+    _sopaque = _getRandomHexString();
+    sendHeader(
+      String(FPSTR(WWW_Authenticate)), AuthTypeDigest + String(F(" realm=\"")) + _srealm + String(F("\", qop=\"auth\", nonce=\"")) + _snonce
+                                         + String(F("\", opaque=\"")) + _sopaque + String(F("\""))
+    );
   }
   using namespace mime;
   send(401, String(FPSTR(mimeTable[html].mimeType)), authFailMsg);
 }
 
-void WebServer::on(const Uri &uri, WebServer::THandlerFunction handler) {
-  on(uri, HTTP_ANY, handler);
+RequestHandler &WebServer::on(const Uri &uri, WebServer::THandlerFunction handler) {
+  return on(uri, HTTP_ANY, handler);
+}
+
+RequestHandler &WebServer::on(const Uri &uri, HTTPMethod method, WebServer::THandlerFunction fn) {
+  return on(uri, method, fn, _fileUploadHandler);
 }
 
-void WebServer::on(const Uri &uri, HTTPMethod method, WebServer::THandlerFunction fn) {
-  on(uri, method, fn, _fileUploadHandler);
+RequestHandler &WebServer::on(const Uri &uri, HTTPMethod method, WebServer::THandlerFunction fn, WebServer::THandlerFunction ufn) {
+  FunctionRequestHandler *handler = new FunctionRequestHandler(fn, ufn, uri, method);
+  _addRequestHandler(handler);
+  return *handler;
 }
 
-void WebServer::on(const Uri &uri, HTTPMethod method, WebServer::THandlerFunction fn, WebServer::THandlerFunction ufn) {
-  _addRequestHandler(new FunctionRequestHandler(fn, ufn, uri, method));
+bool WebServer::removeRoute(const char *uri) {
+  return removeRoute(String(uri), HTTP_ANY);
 }
 
-void WebServer::addHandler(RequestHandler* handler) {
-    _addRequestHandler(handler);
+bool WebServer::removeRoute(const char *uri, HTTPMethod method) {
+  return removeRoute(String(uri), method);
 }
 
-void WebServer::_addRequestHandler(RequestHandler* handler) {
-    if (!_lastHandler) {
-      _firstHandler = handler;
-      _lastHandler = handler;
+bool WebServer::removeRoute(const String &uri) {
+  return removeRoute(uri, HTTP_ANY);
+}
+
+bool WebServer::removeRoute(const String &uri, HTTPMethod method) {
+  bool anyHandlerRemoved = false;
+  RequestHandler *handler = _firstHandler;
+  RequestHandler *previousHandler = nullptr;
+
+  while (handler) {
+    if (handler->canHandle(method, uri)) {
+      if (_removeRequestHandler(handler)) {
+        anyHandlerRemoved = true;
+        // Move to the next handler
+        if (previousHandler) {
+          handler = previousHandler->next();
+        } else {
+          handler = _firstHandler;
+        }
+        continue;
+      }
     }
-    else {
-      _lastHandler->next(handler);
-      _lastHandler = handler;
+    previousHandler = handler;
+    handler = handler->next();
+  }
+
+  return anyHandlerRemoved;
+}
+
+void WebServer::addHandler(RequestHandler *handler) {
+  _addRequestHandler(handler);
+}
+
+bool WebServer::removeHandler(RequestHandler *handler) {
+  return _removeRequestHandler(handler);
+}
+
+void WebServer::_addRequestHandler(RequestHandler *handler) {
+  if (!_lastHandler) {
+    _firstHandler = handler;
+    _lastHandler = handler;
+  } else {
+    _lastHandler->next(handler);
+    _lastHandler = handler;
+  }
+}
+
+bool WebServer::_removeRequestHandler(RequestHandler *handler) {
+  RequestHandler *current = _firstHandler;
+  RequestHandler *previous = nullptr;
+
+  while (current != nullptr) {
+    if (current == handler) {
+      if (previous == nullptr) {
+        _firstHandler = current->next();
+      } else {
+        previous->next(current->next());
+      }
+
+      if (current == _lastHandler) {
+        _lastHandler = previous;
+      }
+
+      // Delete 'matching' handler
+      delete current;
+      return true;
     }
+    previous = current;
+    current = current->next();
+  }
+  return false;
 }
 
-void WebServer::serveStatic(const char* uri, FS& fs, const char* path, const char* cache_header) {
-    _addRequestHandler(new StaticRequestHandler(fs, path, uri, cache_header));
+void WebServer::serveStatic(const char *uri, FS &fs, const char *path, const char *cache_header) {
+  _addRequestHandler(new StaticRequestHandler(fs, path, uri, cache_header));
 }
 
 void WebServer::handleClient() {
   if (_currentStatus == HC_NONE) {
-    WiFiClient client = _server.available();
-    if (!client) {
+    _currentClient = _server.accept();
+    if (!_currentClient) {
       if (_nullDelay) {
         delay(1);
       }
       return;
     }
 
-    log_v("New client");
+    log_v("New client: client.localIP()=%s", _currentClient.localIP().toString().c_str());
 
-    _currentClient = client;
     _currentStatus = HC_WAIT_READ;
     _statusChange = millis();
   }
@@ -300,46 +424,64 @@ void WebServer::handleClient() {
 
   if (_currentClient.connected()) {
     switch (_currentStatus) {
-    case HC_NONE:
-      // No-op to avoid C++ compiler warning
-      break;
-    case HC_WAIT_READ:
-      // Wait for data from client to become available
-      if (_currentClient.available()) {
-        if (_parseRequest(_currentClient)) {
-          // because HTTP_MAX_SEND_WAIT is expressed in milliseconds,
-          // it must be divided by 1000
-          _currentClient.setTimeout(HTTP_MAX_SEND_WAIT / 1000);
-          _contentLength = CONTENT_LENGTH_NOT_SET;
-          _handleRequest();
-
-// Fix for issue with Chrome based browsers: https://github.com/espressif/arduino-esp32/issues/3652
-//           if (_currentClient.connected()) {
-//             _currentStatus = HC_WAIT_CLOSE;
-//             _statusChange = millis();
-//             keepCurrentClient = true;
-//           }
+      case HC_NONE:
+        // No-op to avoid C++ compiler warning
+        break;
+      case HC_WAIT_READ:
+        // Wait for data from client to become available
+        if (_currentClient.available()) {
+          _currentClient.setTimeout(HTTP_MAX_SEND_WAIT); /* / 1000 removed, WifiClient setTimeout changed to ms */
+          if (_parseRequest(_currentClient)) {
+            _contentLength = CONTENT_LENGTH_NOT_SET;
+            _responseCode = 0;
+            _clearResponseHeaders();
+
+            // Run server-level middlewares
+            if (_chain) {
+              _chain->runChain(*this, [this]() {
+                return _handleRequest();
+              });
+            } else {
+              _handleRequest();
+            }
+
+            if (_currentClient.isSSE()) {
+              _currentStatus = HC_WAIT_CLOSE;
+              _statusChange = millis();
+              keepCurrentClient = true;
+            }
+            // Fix for issue with Chrome based browsers: https://github.com/espressif/arduino-esp32/issues/3652
+            //           if (_currentClient.connected()) {
+            //             _currentStatus = HC_WAIT_CLOSE;
+            //             _statusChange = millis();
+            //             keepCurrentClient = true;
+            //           }
+          }
+        } else {  // !_currentClient.available()
+          if (millis() - _statusChange <= HTTP_MAX_DATA_WAIT) {
+            keepCurrentClient = true;
+          }
+          callYield = true;
+        }
+        break;
+      case HC_WAIT_CLOSE:
+        if (_currentClient.isSSE()) {
+          // Never close connection
+          _statusChange = millis();
         }
-      } else { // !_currentClient.available()
-        if (millis() - _statusChange <= HTTP_MAX_DATA_WAIT) {
+        // Wait for client to close the connection
+        if (millis() - _statusChange <= HTTP_MAX_CLOSE_WAIT) {
           keepCurrentClient = true;
+          callYield = true;
         }
-        callYield = true;
-      }
-      break;
-    case HC_WAIT_CLOSE:
-      // Wait for client to close the connection
-      if (millis() - _statusChange <= HTTP_MAX_CLOSE_WAIT) {
-        keepCurrentClient = true;
-        callYield = true;
-      }
     }
   }
 
   if (!keepCurrentClient) {
-    _currentClient = WiFiClient();
+    _currentClient = NetworkClient();
     _currentStatus = HC_NONE;
     _currentUpload.reset();
+    _currentRaw.reset();
   }
 
   if (callYield) {
@@ -350,30 +492,36 @@ void WebServer::handleClient() {
 void WebServer::close() {
   _server.close();
   _currentStatus = HC_NONE;
-  if(!_headerKeysCount)
+  if (!_headerKeysCount) {
     collectHeaders(0, 0);
+  }
 }
 
 void WebServer::stop() {
   close();
 }
 
-void WebServer::sendHeader(const String& name, const String& value, bool first) {
-  String headerLine = name;
-  headerLine += F(": ");
-  headerLine += value;
-  headerLine += "\r\n";
+void WebServer::sendHeader(const String &name, const String &value, bool first) {
+  RequestArgument *header = new RequestArgument();
+  header->key = name;
+  header->value = value;
 
-  if (first) {
-    _responseHeaders = headerLine + _responseHeaders;
-  }
-  else {
-    _responseHeaders += headerLine;
+  if (!_responseHeaders || first) {
+    header->next = _responseHeaders;
+    _responseHeaders = header;
+  } else {
+    RequestArgument *last = _responseHeaders;
+    while (last->next) {
+      last = last->next;
+    }
+    last->next = header;
   }
+
+  _responseHeaderCount++;
 }
 
 void WebServer::setContentLength(const size_t contentLength) {
-    _contentLength = contentLength;
+  _contentLength = contentLength;
 }
 
 void WebServer::enableDelay(boolean value) {
@@ -388,97 +536,122 @@ void WebServer::enableCrossOrigin(boolean value) {
   enableCORS(value);
 }
 
-void WebServer::_prepareHeader(String& response, int code, const char* content_type, size_t contentLength) {
-    response = String(F("HTTP/1.")) + String(_currentVersion) + ' ';
-    response += String(code);
-    response += ' ';
-    response += _responseCodeToString(code);
-    response += "\r\n";
+void WebServer::enableETag(bool enable, ETagFunction fn) {
+  _eTagEnabled = enable;
+  _eTagFunction = fn;
+}
+
+void WebServer::_prepareHeader(String &response, int code, const char *content_type, size_t contentLength) {
+  _responseCode = code;
 
-    using namespace mime;
-    if (!content_type)
-        content_type = mimeTable[html].mimeType;
-
-    sendHeader(String(F("Content-Type")), String(FPSTR(content_type)), true);
-    if (_contentLength == CONTENT_LENGTH_NOT_SET) {
-        sendHeader(String(FPSTR(Content_Length)), String(contentLength));
-    } else if (_contentLength != CONTENT_LENGTH_UNKNOWN) {
-        sendHeader(String(FPSTR(Content_Length)), String(_contentLength));
-    } else if(_contentLength == CONTENT_LENGTH_UNKNOWN && _currentVersion){ //HTTP/1.1 or above client
-      //let's do chunked
-      _chunked = true;
-      sendHeader(String(F("Accept-Ranges")),String(F("none")));
-      sendHeader(String(F("Transfer-Encoding")),String(F("chunked")));
-    }
-    if (_corsEnabled) {
-        sendHeader(String(FPSTR("Access-Control-Allow-Origin")), String("*"));
-    }
-    sendHeader(String(F("Connection")), String(F("close")));
+  response.concat(version());
+  response.concat(' ');
+  response.concat(String(code));
+  response.concat(' ');
+  response.concat(responseCodeToString(code));
+  response.concat(F("\r\n"));
 
-    response += _responseHeaders;
-    response += "\r\n";
-    _responseHeaders = "";
-}
+  using namespace mime;
+  if (!content_type) {
+    content_type = mimeTable[html].mimeType;
+  }
+
+  sendHeader(String(F("Content-Type")), String(FPSTR(content_type)), true);
+  if (_contentLength == CONTENT_LENGTH_NOT_SET) {
+    sendHeader(String(FPSTR(Content_Length)), String(contentLength));
+  } else if (_contentLength != CONTENT_LENGTH_UNKNOWN) {
+    sendHeader(String(FPSTR(Content_Length)), String(_contentLength));
+  } else if (_contentLength == CONTENT_LENGTH_UNKNOWN && _currentVersion) {  //HTTP/1.1 or above client
+    //let's do chunked
+    _chunked = true;
+    sendHeader(String(F("Accept-Ranges")), String(F("none")));
+    sendHeader(String(F("Transfer-Encoding")), String(F("chunked")));
+  }
+  if (_corsEnabled) {
+    sendHeader(String(FPSTR("Access-Control-Allow-Origin")), String("*"));
+    sendHeader(String(FPSTR("Access-Control-Allow-Methods")), String("*"));
+    sendHeader(String(FPSTR("Access-Control-Allow-Headers")), String("*"));
+  }
+  sendHeader(String(F("Connection")), String(F("close")));
+
+  for (RequestArgument *header = _responseHeaders; header; header = header->next) {
+    response.concat(header->key);
+    response.concat(F(": "));
+    response.concat(header->value);
+    response.concat(F("\r\n"));
+  }
 
-void WebServer::send(int code, const char* content_type, const String& content) {
-    String header;
-    // Can we asume the following?
-    //if(code == 200 && content.length() == 0 && _contentLength == CONTENT_LENGTH_NOT_SET)
-    //  _contentLength = CONTENT_LENGTH_UNKNOWN;
-    _prepareHeader(header, code, content_type, content.length());
-    _currentClientWrite(header.c_str(), header.length());
-    if(content.length())
-      sendContent(content);
+  response.concat(F("\r\n"));
 }
 
-void WebServer::send_P(int code, PGM_P content_type, PGM_P content) {
-    size_t contentLength = 0;
+void WebServer::send(int code, const char *content_type, const String &content) {
+  String header;
+  // Can we assume the following?
+  //if(code == 200 && content.length() == 0 && _contentLength == CONTENT_LENGTH_NOT_SET)
+  //  _contentLength = CONTENT_LENGTH_UNKNOWN;
+  _prepareHeader(header, code, content_type, content.length());
+  _currentClientWrite(header.c_str(), header.length());
+  if (content.length()) {
+    sendContent(content);
+  }
+}
 
-    if (content != NULL) {
-        contentLength = strlen_P(content);
-    }
+void WebServer::send(int code, char *content_type, const String &content) {
+  send(code, (const char *)content_type, content);
+}
 
-    String header;
-    char type[64];
-    memccpy_P((void*)type, (PGM_VOID_P)content_type, 0, sizeof(type));
-    _prepareHeader(header, code, (const char* )type, contentLength);
-    _currentClientWrite(header.c_str(), header.length());
-    sendContent_P(content);
+void WebServer::send(int code, const String &content_type, const String &content) {
+  send(code, (const char *)content_type.c_str(), content);
 }
 
-void WebServer::send_P(int code, PGM_P content_type, PGM_P content, size_t contentLength) {
-    String header;
-    char type[64];
-    memccpy_P((void*)type, (PGM_VOID_P)content_type, 0, sizeof(type));
-    _prepareHeader(header, code, (const char* )type, contentLength);
-    sendContent(header);
-    sendContent_P(content, contentLength);
+void WebServer::send(int code, const char *content_type, const char *content) {
+  const String passStr = (String)content;
+  if (strlen(content) != passStr.length()) {
+    log_e("String cast failed.  Use send_P for long arrays");
+  }
+  send(code, content_type, passStr);
 }
 
-void WebServer::send(int code, char* content_type, const String& content) {
-  send(code, (const char*)content_type, content);
+void WebServer::send_P(int code, PGM_P content_type, PGM_P content) {
+  size_t contentLength = 0;
+
+  if (content != NULL) {
+    contentLength = strlen_P(content);
+  }
+
+  String header;
+  char type[64];
+  memccpy_P((void *)type, (PGM_VOID_P)content_type, 0, sizeof(type));
+  _prepareHeader(header, code, (const char *)type, contentLength);
+  _currentClientWrite(header.c_str(), header.length());
+  sendContent_P(content);
 }
 
-void WebServer::send(int code, const String& content_type, const String& content) {
-  send(code, (const char*)content_type.c_str(), content);
+void WebServer::send_P(int code, PGM_P content_type, PGM_P content, size_t contentLength) {
+  String header;
+  char type[64];
+  memccpy_P((void *)type, (PGM_VOID_P)content_type, 0, sizeof(type));
+  _prepareHeader(header, code, (const char *)type, contentLength);
+  sendContent(header);
+  sendContent_P(content, contentLength);
 }
 
-void WebServer::sendContent(const String& content) {
+void WebServer::sendContent(const String &content) {
   sendContent(content.c_str(), content.length());
 }
 
-void WebServer::sendContent(const char* content, size_t contentLength) {
-  const char * footer = "\r\n";
-  if(_chunked) {
-    char * chunkSize = (char *)malloc(11);
-    if(chunkSize){
+void WebServer::sendContent(const char *content, size_t contentLength) {
+  const char *footer = "\r\n";
+  if (_chunked) {
+    char *chunkSize = (char *)malloc(11);
+    if (chunkSize) {
       sprintf(chunkSize, "%x%s", contentLength, footer);
       _currentClientWrite(chunkSize, strlen(chunkSize));
       free(chunkSize);
     }
   }
   _currentClientWrite(content, contentLength);
-  if(_chunked){
+  if (_chunked) {
     _currentClient.write(footer, 2);
     if (contentLength == 0) {
       _chunked = false;
@@ -491,17 +664,17 @@ void WebServer::sendContent_P(PGM_P content) {
 }
 
 void WebServer::sendContent_P(PGM_P content, size_t size) {
-  const char * footer = "\r\n";
-  if(_chunked) {
-    char * chunkSize = (char *)malloc(11);
-    if(chunkSize){
+  const char *footer = "\r\n";
+  if (_chunked) {
+    char *chunkSize = (char *)malloc(11);
+    if (chunkSize) {
       sprintf(chunkSize, "%x%s", size, footer);
       _currentClientWrite(chunkSize, strlen(chunkSize));
       free(chunkSize);
     }
   }
   _currentClientWrite_P(content, size);
-  if(_chunked){
+  if (_chunked) {
     _currentClient.write(footer, 2);
     if (size == 0) {
       _chunked = false;
@@ -509,110 +682,118 @@ void WebServer::sendContent_P(PGM_P content, size_t size) {
   }
 }
 
-
-void WebServer::_streamFileCore(const size_t fileSize, const String & fileName, const String & contentType)
-{
+void WebServer::_streamFileCore(const size_t fileSize, const String &fileName, const String &contentType, const int code) {
   using namespace mime;
   setContentLength(fileSize);
-  if (fileName.endsWith(String(FPSTR(mimeTable[gz].endsWith))) &&
-      contentType != String(FPSTR(mimeTable[gz].mimeType)) &&
-      contentType != String(FPSTR(mimeTable[none].mimeType))) {
+  if (fileName.endsWith(String(FPSTR(mimeTable[gz].endsWith))) && contentType != String(FPSTR(mimeTable[gz].mimeType))
+      && contentType != String(FPSTR(mimeTable[none].mimeType))) {
     sendHeader(F("Content-Encoding"), F("gzip"));
   }
-  send(200, contentType, "");
+  send(code, contentType, "");
 }
 
-String WebServer::pathArg(unsigned int i) {
-  if (_currentHandler != nullptr)
+String WebServer::pathArg(unsigned int i) const {
+  if (_currentHandler != nullptr) {
     return _currentHandler->pathArg(i);
+  }
   return "";
 }
 
-String WebServer::arg(String name) {
+String WebServer::arg(const String &name) const {
   for (int j = 0; j < _postArgsLen; ++j) {
-	    if ( _postArgs[j].key == name )
-	      return _postArgs[j].value;
-	  }
+    if (_postArgs[j].key == name) {
+      return _postArgs[j].value;
+    }
+  }
   for (int i = 0; i < _currentArgCount; ++i) {
-    if ( _currentArgs[i].key == name )
+    if (_currentArgs[i].key == name) {
       return _currentArgs[i].value;
+    }
   }
   return "";
 }
 
-String WebServer::arg(int i) {
-  if (i < _currentArgCount)
+String WebServer::arg(int i) const {
+  if (i < _currentArgCount) {
     return _currentArgs[i].value;
+  }
   return "";
 }
 
-String WebServer::argName(int i) {
-  if (i < _currentArgCount)
+String WebServer::argName(int i) const {
+  if (i < _currentArgCount) {
     return _currentArgs[i].key;
+  }
   return "";
 }
 
-int WebServer::args() {
+int WebServer::args() const {
   return _currentArgCount;
 }
 
-bool WebServer::hasArg(String  name) {
+bool WebServer::hasArg(const String &name) const {
   for (int j = 0; j < _postArgsLen; ++j) {
-	    if (_postArgs[j].key == name)
-	      return true;
-	  }
+    if (_postArgs[j].key == name) {
+      return true;
+    }
+  }
   for (int i = 0; i < _currentArgCount; ++i) {
-    if (_currentArgs[i].key == name)
+    if (_currentArgs[i].key == name) {
       return true;
+    }
   }
   return false;
 }
 
-
-String WebServer::header(String name) {
-  for (int i = 0; i < _headerKeysCount; ++i) {
-    if (_currentHeaders[i].key.equalsIgnoreCase(name))
-      return _currentHeaders[i].value;
+String WebServer::header(const String &name) const {
+  for (RequestArgument *current = _currentHeaders; current; current = current->next) {
+    if (current->key.equalsIgnoreCase(name)) {
+      return current->value;
+    }
   }
   return "";
 }
 
-void WebServer::collectHeaders(const char* headerKeys[], const size_t headerKeysCount) {
-  _headerKeysCount = headerKeysCount + 1;
-  if (_currentHeaders)
-     delete[]_currentHeaders;
-  _currentHeaders = new RequestArgument[_headerKeysCount];
-  _currentHeaders[0].key = FPSTR(AUTHORIZATION_HEADER);
-  for (int i = 1; i < _headerKeysCount; i++){
-    _currentHeaders[i].key = headerKeys[i-1];
+void WebServer::collectHeaders(const char *headerKeys[], const size_t headerKeysCount) {
+  collectAllHeaders();
+  _collectAllHeaders = false;
+
+  _headerKeysCount += headerKeysCount;
+
+  RequestArgument *last = _currentHeaders->next;
+
+  for (int i = 2; i < _headerKeysCount; i++) {
+    last->next = new RequestArgument();
+    last->next->key = headerKeys[i - 2];
+    last = last->next;
   }
 }
 
-String WebServer::header(int i) {
-  if (i < _headerKeysCount)
-    return _currentHeaders[i].value;
-  return "";
+String WebServer::header(int i) const {
+  RequestArgument *current = _currentHeaders;
+  while (current && i--) {
+    current = current->next;
+  }
+  return current ? current->value : emptyString;
 }
 
-String WebServer::headerName(int i) {
-  if (i < _headerKeysCount)
-    return _currentHeaders[i].key;
-  return "";
+String WebServer::headerName(int i) const {
+  RequestArgument *current = _currentHeaders;
+  while (current && i--) {
+    current = current->next;
+  }
+  return current ? current->key : emptyString;
 }
 
-int WebServer::headers() {
+int WebServer::headers() const {
   return _headerKeysCount;
 }
 
-bool WebServer::hasHeader(String name) {
-  for (int i = 0; i < _headerKeysCount; ++i) {
-    if ((_currentHeaders[i].key.equalsIgnoreCase(name)) &&  (_currentHeaders[i].value.length() > 0))
-      return true;
-  }
-  return false;
+bool WebServer::hasHeader(const String &name) const {
+  return header(name).length() > 0;
 }
 
-String WebServer::hostHeader() {
+String WebServer::hostHeader() const {
   return _hostHeader;
 }
 
@@ -624,17 +805,17 @@ void WebServer::onNotFound(THandlerFunction fn) {
   _notFoundHandler = fn;
 }
 
-void WebServer::_handleRequest() {
+bool WebServer::_handleRequest() {
   bool handled = false;
-  if (!_currentHandler){
-    log_e("request handler not found");
-  }
-  else {
-    handled = _currentHandler->handle(*this, _currentMethod, _currentUri);
+  if (_currentHandler) {
+    handled = _currentHandler->process(*this, _currentMethod, _currentUri);
     if (!handled) {
       log_e("request handler failed to handle request");
     }
   }
+  // DO NOT LOG if _currentHandler == null !!
+  // This is is valid use case to handle any other requests
+  // Also, this is just causing log flooding
   if (!handled && _notFoundHandler) {
     _notFoundHandler();
     handled = true;
@@ -648,16 +829,16 @@ void WebServer::_handleRequest() {
     _finalizeResponse();
   }
   _currentUri = "";
+  return handled;
 }
 
-
 void WebServer::_finalizeResponse() {
   if (_chunked) {
     sendContent("");
   }
 }
 
-String WebServer::_responseCodeToString(int code) {
+String WebServer::responseCodeToString(int code) {
   switch (code) {
     case 100: return F("Continue");
     case 101: return F("Switching Protocols");
@@ -702,3 +883,108 @@ String WebServer::_responseCodeToString(int code) {
     default:  return F("");
   }
 }
+
+void WebServer::_clearResponseHeaders() {
+  _responseHeaderCount = 0;
+  RequestArgument *current = _responseHeaders;
+  while (current) {
+    RequestArgument *next = current->next;
+    delete current;
+    current = next;
+  }
+  _responseHeaders = nullptr;
+}
+
+void WebServer::_clearRequestHeaders() {
+  _headerKeysCount = 0;
+  RequestArgument *current = _currentHeaders;
+  while (current) {
+    RequestArgument *next = current->next;
+    delete current;
+    current = next;
+  }
+  _currentHeaders = nullptr;
+}
+
+void WebServer::collectAllHeaders() {
+  _clearRequestHeaders();
+
+  _currentHeaders = new RequestArgument();
+  _currentHeaders->key = FPSTR(AUTHORIZATION_HEADER);
+
+  _currentHeaders->next = new RequestArgument();
+  _currentHeaders->next->key = FPSTR(ETAG_HEADER);
+
+  _headerKeysCount = 2;
+  _collectAllHeaders = true;
+}
+
+const String &WebServer::responseHeader(String name) const {
+  for (RequestArgument *current = _responseHeaders; current; current = current->next) {
+    if (current->key.equalsIgnoreCase(name)) {
+      return current->value;
+    }
+  }
+  return emptyString;
+}
+
+const String &WebServer::responseHeader(int i) const {
+  RequestArgument *current = _responseHeaders;
+  while (current && i--) {
+    current = current->next;
+  }
+  return current ? current->value : emptyString;
+}
+
+const String &WebServer::responseHeaderName(int i) const {
+  RequestArgument *current = _responseHeaders;
+  while (current && i--) {
+    current = current->next;
+  }
+  return current ? current->key : emptyString;
+}
+
+bool WebServer::hasResponseHeader(const String &name) const {
+  return header(name).length() > 0;
+}
+
+int WebServer::clientContentLength() const {
+  return _clientContentLength;
+}
+
+const String WebServer::version() const {
+  String v;
+  v.reserve(8);
+  v.concat(F("HTTP/1."));
+  v.concat(_currentVersion);
+  return v;
+}
+int WebServer::responseCode() const {
+  return _responseCode;
+}
+int WebServer::responseHeaders() const {
+  return _responseHeaderCount;
+}
+
+WebServer &WebServer::addMiddleware(Middleware *middleware) {
+  if (!_chain) {
+    _chain = new MiddlewareChain();
+  }
+  _chain->addMiddleware(middleware);
+  return *this;
+}
+
+WebServer &WebServer::addMiddleware(Middleware::Function fn) {
+  if (!_chain) {
+    _chain = new MiddlewareChain();
+  }
+  _chain->addMiddleware(fn);
+  return *this;
+}
+
+WebServer &WebServer::removeMiddleware(Middleware *middleware) {
+  if (_chain) {
+    _chain->removeMiddleware(middleware);
+  }
+  return *this;
+}
diff --git a/libraries/WebServer/src/WebServer.h b/libraries/WebServer/src/WebServer.h
index c169da82229..8daf12c5c30 100644
--- a/libraries/WebServer/src/WebServer.h
+++ b/libraries/WebServer/src/WebServer.h
@@ -20,20 +20,38 @@
   Modified 8 May 2015 by Hristo Gochkov (proper post and file upload handling)
 */
 
-
 #ifndef WEBSERVER_H
 #define WEBSERVER_H
 
 #include <functional>
 #include <memory>
-#include <WiFi.h>
+#include "FS.h"
+#include "Network.h"
 #include "HTTP_Method.h"
 #include "Uri.h"
 
-enum HTTPUploadStatus { UPLOAD_FILE_START, UPLOAD_FILE_WRITE, UPLOAD_FILE_END,
-                        UPLOAD_FILE_ABORTED };
-enum HTTPClientStatus { HC_NONE, HC_WAIT_READ, HC_WAIT_CLOSE };
-enum HTTPAuthMethod { BASIC_AUTH, DIGEST_AUTH };
+enum HTTPUploadStatus {
+  UPLOAD_FILE_START,
+  UPLOAD_FILE_WRITE,
+  UPLOAD_FILE_END,
+  UPLOAD_FILE_ABORTED
+};
+enum HTTPRawStatus {
+  RAW_START,
+  RAW_WRITE,
+  RAW_END,
+  RAW_ABORTED
+};
+enum HTTPClientStatus {
+  HC_NONE,
+  HC_WAIT_READ,
+  HC_WAIT_CLOSE
+};
+enum HTTPAuthMethod {
+  BASIC_AUTH,
+  DIGEST_AUTH,
+  OTHER_AUTH
+};
 
 #define HTTP_DOWNLOAD_UNIT_SIZE 1436
 
@@ -41,34 +59,47 @@ enum HTTPAuthMethod { BASIC_AUTH, DIGEST_AUTH };
 #define HTTP_UPLOAD_BUFLEN 1436
 #endif
 
-#define HTTP_MAX_DATA_WAIT 5000 //ms to wait for the client to send the request
-#define HTTP_MAX_POST_WAIT 5000 //ms to wait for POST data to arrive
-#define HTTP_MAX_SEND_WAIT 5000 //ms to wait for data chunk to be ACKed
-#define HTTP_MAX_CLOSE_WAIT 2000 //ms to wait for the client to close the connection
+#ifndef HTTP_RAW_BUFLEN
+#define HTTP_RAW_BUFLEN 1436
+#endif
 
-#define CONTENT_LENGTH_UNKNOWN ((size_t) -1)
-#define CONTENT_LENGTH_NOT_SET ((size_t) -2)
+#define HTTP_MAX_DATA_WAIT      5000  //ms to wait for the client to send the request
+#define HTTP_MAX_POST_WAIT      5000  //ms to wait for POST data to arrive
+#define HTTP_MAX_SEND_WAIT      5000  //ms to wait for data chunk to be ACKed
+#define HTTP_MAX_CLOSE_WAIT     5000  //ms to wait for the client to close the connection
+#define HTTP_MAX_BASIC_AUTH_LEN 256   // maximum length of a basic Auth base64 encoded username:password string
+
+#define CONTENT_LENGTH_UNKNOWN ((size_t) - 1)
+#define CONTENT_LENGTH_NOT_SET ((size_t) - 2)
 
 class WebServer;
 
 typedef struct {
   HTTPUploadStatus status;
-  String  filename;
-  String  name;
-  String  type;
-  size_t  totalSize;    // file size
-  size_t  currentSize;  // size of data currently in buf
+  String filename;
+  String name;
+  String type;
+  size_t totalSize;    // file size
+  size_t currentSize;  // size of data currently in buf
   uint8_t buf[HTTP_UPLOAD_BUFLEN];
 } HTTPUpload;
 
+typedef struct {
+  HTTPRawStatus status;
+  size_t totalSize;    // content size
+  size_t currentSize;  // size of data currently in buf
+  uint8_t buf[HTTP_RAW_BUFLEN];
+  void *data;  // additional data
+} HTTPRaw;
+
+#include "middleware/Middleware.h"
 #include "detail/RequestHandler.h"
 
 namespace fs {
 class FS;
 }
 
-class WebServer
-{
+class WebServer {
 public:
   WebServer(IPAddress addr, int port = 80);
   WebServer(int port = 80);
@@ -81,131 +112,212 @@ class WebServer
   virtual void close();
   void stop();
 
-  bool authenticate(const char * username, const char * password);
-  void requestAuthentication(HTTPAuthMethod mode = BASIC_AUTH, const char* realm = NULL, const String& authFailMsg = String("") );
+  const String AuthTypeDigest = F("Digest");
+  const String AuthTypeBasic = F("Basic");
+
+  /* Callbackhandler for authentication. The extra parameters depend on the
+   * HTTPAuthMethod mode:
+   *
+   * BASIC_AUTH         enteredUsernameOrReq	contains the username entered by the user
+   *                    param[0]		          password entered (in the clear)
+   *                    param[1]		          authentication realm.
+   *
+   * To return - the password the user entered password is compared to. Or Null on fail.
+   *
+   * DIGEST_AUTH        enteredUsernameOrReq    contains the username entered by the user
+   *                    param[0]                autenticaiton realm
+   *                    param[1]                authentication URI
+   *
+   * To return - the password of which the digest will be based on for comparison. Or NULL
+   * to fail.
+   *
+   * OTHER_AUTH         enteredUsernameOrReq    rest of the auth line.
+   *                    params                  empty array
+   *
+   * To return - NULL to fail; or any string.
+   */
+  typedef std::function<String *(HTTPAuthMethod mode, String enteredUsernameOrReq, String extraParams[])> THandlerFunctionAuthCheck;
+
+  bool authenticate(THandlerFunctionAuthCheck fn);
+  bool authenticate(const char *username, const char *password);
+  bool authenticateBasicSHA1(const char *_username, const char *_sha1AsBase64orHex);
+
+  void requestAuthentication(HTTPAuthMethod mode = BASIC_AUTH, const char *realm = NULL, const String &authFailMsg = String(""));
 
   typedef std::function<void(void)> THandlerFunction;
-  void on(const Uri &uri, THandlerFunction handler);
-  void on(const Uri &uri, HTTPMethod method, THandlerFunction fn);
-  void on(const Uri &uri, HTTPMethod method, THandlerFunction fn, THandlerFunction ufn);
-  void addHandler(RequestHandler* handler);
-  void serveStatic(const char* uri, fs::FS& fs, const char* path, const char* cache_header = NULL );
-  void onNotFound(THandlerFunction fn);  //called when handler is not assigned
-  void onFileUpload(THandlerFunction fn); //handle file uploads
-
-  String uri() { return _currentUri; }
-  HTTPMethod method() { return _currentMethod; }
-  virtual WiFiClient client() { return _currentClient; }
-  HTTPUpload& upload() { return *_currentUpload; }
-
-  String pathArg(unsigned int i); // get request path argument by number
-  String arg(String name);        // get request argument value by name
-  String arg(int i);              // get request argument value by number
-  String argName(int i);          // get request argument name by number
-  int args();                     // get arguments count
-  bool hasArg(String name);       // check if argument exists
-  void collectHeaders(const char* headerKeys[], const size_t headerKeysCount); // set the request headers to collect
-  String header(String name);      // get request header value by name
-  String header(int i);              // get request header value by number
-  String headerName(int i);          // get request header name by number
-  int headers();                     // get header count
-  bool hasHeader(String name);       // check if header exists
-
-  String hostHeader();            // get request host header if available or empty String if not
+  typedef std::function<bool(WebServer &server)> FilterFunction;
+  RequestHandler &on(const Uri &uri, THandlerFunction fn);
+  RequestHandler &on(const Uri &uri, HTTPMethod method, THandlerFunction fn);
+  RequestHandler &on(const Uri &uri, HTTPMethod method, THandlerFunction fn, THandlerFunction ufn);  //ufn handles file uploads
+  bool removeRoute(const char *uri);
+  bool removeRoute(const char *uri, HTTPMethod method);
+  bool removeRoute(const String &uri);
+  bool removeRoute(const String &uri, HTTPMethod method);
+  void addHandler(RequestHandler *handler);
+  bool removeHandler(RequestHandler *handler);
+  void serveStatic(const char *uri, fs::FS &fs, const char *path, const char *cache_header = NULL);
+  void onNotFound(THandlerFunction fn);     //called when handler is not assigned
+  void onFileUpload(THandlerFunction ufn);  //handle file uploads
+
+  WebServer &addMiddleware(Middleware *middleware);
+  WebServer &addMiddleware(Middleware::Function fn);
+  WebServer &removeMiddleware(Middleware *middleware);
+
+  String uri() const {
+    return _currentUri;
+  }
+  HTTPMethod method() const {
+    return _currentMethod;
+  }
+  virtual NetworkClient &client() {
+    return _currentClient;
+  }
+  HTTPUpload &upload() {
+    return *_currentUpload;
+  }
+  HTTPRaw &raw() {
+    return *_currentRaw;
+  }
+
+  String pathArg(unsigned int i) const;                                         // get request path argument by number
+  String arg(const String &name) const;                                         // get request argument value by name
+  String arg(int i) const;                                                      // get request argument value by number
+  String argName(int i) const;                                                  // get request argument name by number
+  int args() const;                                                             // get arguments count
+  bool hasArg(const String &name) const;                                        // check if argument exists
+  void collectHeaders(const char *headerKeys[], const size_t headerKeysCount);  // set the request headers to collect
+  void collectAllHeaders();                                                     // collect all request headers
+  String header(const String &name) const;                                      // get request header value by name
+  String header(int i) const;                                                   // get request header value by number
+  String headerName(int i) const;                                               // get request header name by number
+  int headers() const;                                                          // get header count
+  bool hasHeader(const String &name) const;                                     // check if header exists
+
+  int clientContentLength() const;  // return "content-length" of incoming HTTP header from "_currentClient"
+  const String version() const;     // get the HTTP version string
+  String hostHeader() const;        // get request host header if available or empty String if not
+
+  int responseCode() const;                          // get the HTTP response code set
+  int responseHeaders() const;                       // get the HTTP response headers count
+  const String &responseHeader(String name) const;   // get the HTTP response header value by name
+  const String &responseHeader(int i) const;         // get the HTTP response header value by number
+  const String &responseHeaderName(int i) const;     // get the HTTP response header name by number
+  bool hasResponseHeader(const String &name) const;  // check if response header exists
 
   // send response to the client
   // code - HTTP response code, can be 200 or 404
   // content_type - HTTP content type, like "text/plain" or "image/png"
   // content - actual content body
-  void send(int code, const char* content_type = NULL, const String& content = String(""));
-  void send(int code, char* content_type, const String& content);
-  void send(int code, const String& content_type, const String& content);
+  void send(int code, const char *content_type = NULL, const String &content = String(""));
+  void send(int code, char *content_type, const String &content);
+  void send(int code, const String &content_type, const String &content);
+  void send(int code, const char *content_type, const char *content);
+
   void send_P(int code, PGM_P content_type, PGM_P content);
   void send_P(int code, PGM_P content_type, PGM_P content, size_t contentLength);
 
   void enableDelay(boolean value);
   void enableCORS(boolean value = true);
   void enableCrossOrigin(boolean value = true);
+  typedef std::function<String(FS &fs, const String &fName)> ETagFunction;
+  void enableETag(bool enable, ETagFunction fn = nullptr);
 
   void setContentLength(const size_t contentLength);
-  void sendHeader(const String& name, const String& value, bool first = false);
-  void sendContent(const String& content);
-  void sendContent(const char* content, size_t contentLength);
+  void sendHeader(const String &name, const String &value, bool first = false);
+  void sendContent(const String &content);
+  void sendContent(const char *content, size_t contentLength);
   void sendContent_P(PGM_P content);
   void sendContent_P(PGM_P content, size_t size);
 
-  static String urlDecode(const String& text);
+  static String urlDecode(const String &text);
 
-  template<typename T>
-  size_t streamFile(T &file, const String& contentType) {
-    _streamFileCore(file.size(), file.name(), contentType);
+  template<typename T> size_t streamFile(T &file, const String &contentType, const int code = 200) {
+    _streamFileCore(file.size(), file.name(), contentType, code);
     return _currentClient.write(file);
   }
 
+  bool _eTagEnabled = false;
+  ETagFunction _eTagFunction = nullptr;
+
+  static String responseCodeToString(int code);
+
 protected:
-  virtual size_t _currentClientWrite(const char* b, size_t l) { return _currentClient.write( b, l ); }
-  virtual size_t _currentClientWrite_P(PGM_P b, size_t l) { return _currentClient.write_P( b, l ); }
-  void _addRequestHandler(RequestHandler* handler);
-  void _handleRequest();
+  virtual size_t _currentClientWrite(const char *b, size_t l) {
+    return _currentClient.write(b, l);
+  }
+  virtual size_t _currentClientWrite_P(PGM_P b, size_t l) {
+    return _currentClient.write_P(b, l);
+  }
+  void _addRequestHandler(RequestHandler *handler);
+  bool _removeRequestHandler(RequestHandler *handler);
+  bool _handleRequest();
   void _finalizeResponse();
-  bool _parseRequest(WiFiClient& client);
-  void _parseArguments(String data);
-  static String _responseCodeToString(int code);
-  bool _parseForm(WiFiClient& client, String boundary, uint32_t len);
+  bool _parseRequest(NetworkClient &client);
+  void _parseArguments(const String &data);
+  bool _parseForm(NetworkClient &client, const String &boundary, uint32_t len);
   bool _parseFormUploadAborted();
   void _uploadWriteByte(uint8_t b);
-  int _uploadReadByte(WiFiClient& client);
-  void _prepareHeader(String& response, int code, const char* content_type, size_t contentLength);
-  bool _collectHeader(const char* headerName, const char* headerValue);
+  int _uploadReadByte(NetworkClient &client);
+  void _prepareHeader(String &response, int code, const char *content_type, size_t contentLength);
+  bool _collectHeader(const char *headerName, const char *headerValue);
 
-  void _streamFileCore(const size_t fileSize, const String & fileName, const String & contentType);
+  void _streamFileCore(const size_t fileSize, const String &fileName, const String &contentType, const int code = 200);
 
   String _getRandomHexString();
   // for extracting Auth parameters
-  String _extractParam(String& authReq,const String& param,const char delimit = '"');
+  String _extractParam(String &authReq, const String &param, const char delimit = '"');
+
+  void _clearResponseHeaders();
+  void _clearRequestHeaders();
 
   struct RequestArgument {
     String key;
     String value;
+    RequestArgument *next;
   };
 
-  boolean     _corsEnabled;
-  WiFiServer  _server;
+  boolean _corsEnabled = false;
+  NetworkServer _server;
 
-  WiFiClient  _currentClient;
-  HTTPMethod  _currentMethod;
-  String      _currentUri;
-  uint8_t     _currentVersion;
-  HTTPClientStatus _currentStatus;
-  unsigned long _statusChange;
-  boolean     _nullDelay;
+  NetworkClient _currentClient;
+  HTTPMethod _currentMethod = HTTP_ANY;
+  String _currentUri;
+  uint8_t _currentVersion = 0;
+  HTTPClientStatus _currentStatus = HC_NONE;
+  unsigned long _statusChange = 0;
+  boolean _nullDelay = true;
 
-  RequestHandler*  _currentHandler;
-  RequestHandler*  _firstHandler;
-  RequestHandler*  _lastHandler;
-  THandlerFunction _notFoundHandler;
-  THandlerFunction _fileUploadHandler;
+  RequestHandler *_currentHandler = nullptr;
+  RequestHandler *_firstHandler = nullptr;
+  RequestHandler *_lastHandler = nullptr;
+  THandlerFunction _notFoundHandler = nullptr;
+  THandlerFunction _fileUploadHandler = nullptr;
 
-  int              _currentArgCount;
-  RequestArgument* _currentArgs;
-  int              _postArgsLen;
-  RequestArgument* _postArgs;
+  int _currentArgCount = 0;
+  RequestArgument *_currentArgs = nullptr;
+  int _postArgsLen = 0;
+  RequestArgument *_postArgs = nullptr;
 
   std::unique_ptr<HTTPUpload> _currentUpload;
+  std::unique_ptr<HTTPRaw> _currentRaw;
 
-  int              _headerKeysCount;
-  RequestArgument* _currentHeaders;
-  size_t           _contentLength;
-  String           _responseHeaders;
+  int _headerKeysCount = 0;
+  RequestArgument *_currentHeaders = nullptr;
+  size_t _contentLength = 0;
+  int _clientContentLength = 0;  // "Content-Length" from header of incoming POST or GET request
+  RequestArgument *_responseHeaders = nullptr;
 
-  String           _hostHeader;
-  bool             _chunked;
+  String _hostHeader;
+  bool _chunked = false;
 
-  String           _snonce;  // Store noance and opaque for future comparison
-  String           _sopaque;
-  String           _srealm;  // Store the Auth realm between Calls
+  String _snonce;  // Store noance and opaque for future comparison
+  String _sopaque;
+  String _srealm;  // Store the Auth realm between Calls
 
+  int _responseHeaderCount = 0;
+  int _responseCode = 0;
+  bool _collectAllHeaders = false;
+  MiddlewareChain *_chain = nullptr;
 };
 
-
-#endif //ESP8266WEBSERVER_H
+#endif  //ESP8266WEBSERVER_H
diff --git a/libraries/WebServer/src/detail/RequestHandler.h b/libraries/WebServer/src/detail/RequestHandler.h
index 871ae5c8b3d..75e11c94ba8 100644
--- a/libraries/WebServer/src/detail/RequestHandler.h
+++ b/libraries/WebServer/src/detail/RequestHandler.h
@@ -6,26 +6,94 @@
 
 class RequestHandler {
 public:
-    virtual ~RequestHandler() { }
-    virtual bool canHandle(HTTPMethod method, String uri) { (void) method; (void) uri; return false; }
-    virtual bool canUpload(String uri) { (void) uri; return false; }
-    virtual bool handle(WebServer& server, HTTPMethod requestMethod, String requestUri) { (void) server; (void) requestMethod; (void) requestUri; return false; }
-    virtual void upload(WebServer& server, String requestUri, HTTPUpload& upload) { (void) server; (void) requestUri; (void) upload; }
+  virtual ~RequestHandler() {
+    delete _chain;
+  }
 
-    RequestHandler* next() { return _next; }
-    void next(RequestHandler* r) { _next = r; }
+  /*
+    note: old handler API for backward compatibility
+  */
+
+  virtual bool canHandle(HTTPMethod method, const String &uri) {
+    (void)method;
+    (void)uri;
+    return false;
+  }
+  virtual bool canUpload(const String &uri) {
+    (void)uri;
+    return false;
+  }
+  virtual bool canRaw(const String &uri) {
+    (void)uri;
+    return false;
+  }
+
+  /*
+    note: new handler API with support for filters etc.
+  */
+
+  virtual bool canHandle(WebServer &server, HTTPMethod method, const String &uri) {
+    (void)server;
+    (void)method;
+    (void)uri;
+    return false;
+  }
+  virtual bool canUpload(WebServer &server, const String &uri) {
+    (void)server;
+    (void)uri;
+    return false;
+  }
+  virtual bool canRaw(WebServer &server, const String &uri) {
+    (void)server;
+    (void)uri;
+    return false;
+  }
+  virtual bool handle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) {
+    (void)server;
+    (void)requestMethod;
+    (void)requestUri;
+    return false;
+  }
+  virtual void upload(WebServer &server, const String &requestUri, HTTPUpload &upload) {
+    (void)server;
+    (void)requestUri;
+    (void)upload;
+  }
+  virtual void raw(WebServer &server, const String &requestUri, HTTPRaw &raw) {
+    (void)server;
+    (void)requestUri;
+    (void)raw;
+  }
+
+  virtual RequestHandler &setFilter(std::function<bool(WebServer &)> filter) {
+    (void)filter;
+    return *this;
+  }
+
+  RequestHandler *next() {
+    return _next;
+  }
+  void next(RequestHandler *r) {
+    _next = r;
+  }
+
+  RequestHandler &addMiddleware(Middleware *middleware);
+  RequestHandler &addMiddleware(Middleware::Function fn);
+  RequestHandler &removeMiddleware(Middleware *middleware);
+  bool process(WebServer &server, HTTPMethod requestMethod, String requestUri);
 
 private:
-    RequestHandler* _next = nullptr;
+  RequestHandler *_next = nullptr;
+  MiddlewareChain *_chain = nullptr;
 
 protected:
-    std::vector<String> pathArgs;
+  std::vector<String> pathArgs;
 
 public:
-    const String& pathArg(unsigned int i) { 
-        assert(i < pathArgs.size());
-        return pathArgs[i];
-    }
+  const String &pathArg(unsigned int i) {
+    assert(i < pathArgs.size());
+    return pathArgs[i];
+  }
 };
 
-#endif //REQUESTHANDLER_H
+#endif  //REQUESTHANDLER_H
diff --git a/libraries/WebServer/src/detail/RequestHandlersImpl.h b/libraries/WebServer/src/detail/RequestHandlersImpl.h
index 27a2a8d328a..3750b594ab2 100644
--- a/libraries/WebServer/src/detail/RequestHandlersImpl.h
+++ b/libraries/WebServer/src/detail/RequestHandlersImpl.h
@@ -5,147 +5,293 @@
 #include "mimetable.h"
 #include "WString.h"
 #include "Uri.h"
+#include <MD5Builder.h>
+#include <base64.h>
 
 using namespace mime;
 
+RequestHandler &RequestHandler::addMiddleware(Middleware *middleware) {
+  if (!_chain) {
+    _chain = new MiddlewareChain();
+  }
+  _chain->addMiddleware(middleware);
+  return *this;
+}
+
+RequestHandler &RequestHandler::addMiddleware(Middleware::Function fn) {
+  if (!_chain) {
+    _chain = new MiddlewareChain();
+  }
+  _chain->addMiddleware(fn);
+  return *this;
+}
+
+RequestHandler &RequestHandler::removeMiddleware(Middleware *middleware) {
+  if (_chain) {
+    _chain->removeMiddleware(middleware);
+  }
+  return *this;
+}
+
+bool RequestHandler::process(WebServer &server, HTTPMethod requestMethod, String requestUri) {
+  if (_chain) {
+    return _chain->runChain(server, [this, &server, &requestMethod, &requestUri]() {
+      return handle(server, requestMethod, requestUri);
+    });
+  } else {
+    return handle(server, requestMethod, requestUri);
+  }
+}
+
 class FunctionRequestHandler : public RequestHandler {
 public:
-    FunctionRequestHandler(WebServer::THandlerFunction fn, WebServer::THandlerFunction ufn, const Uri &uri, HTTPMethod method)
-    : _fn(fn)
-    , _ufn(ufn)
-    , _uri(uri.clone())
-    , _method(method)
-    {
-        _uri->initPathArgs(pathArgs);
+  FunctionRequestHandler(WebServer::THandlerFunction fn, WebServer::THandlerFunction ufn, const Uri &uri, HTTPMethod method)
+    : _fn(fn), _ufn(ufn), _uri(uri.clone()), _method(method) {
+    _uri->initPathArgs(pathArgs);
+  }
+
+  ~FunctionRequestHandler() {
+    delete _uri;
+  }
+
+  bool canHandle(HTTPMethod requestMethod, const String &requestUri) override {
+    if (_method != HTTP_ANY && _method != requestMethod) {
+      return false;
     }
 
-    ~FunctionRequestHandler() {
-        delete _uri;
+    return _uri->canHandle(requestUri, pathArgs);
+  }
+
+  bool canUpload(const String &requestUri) override {
+    if (!_ufn || !canHandle(HTTP_POST, requestUri)) {
+      return false;
     }
 
-    bool canHandle(HTTPMethod requestMethod, String requestUri) override  {
-        if (_method != HTTP_ANY && _method != requestMethod)
-            return false;
+    return true;
+  }
 
-        return _uri->canHandle(requestUri, pathArgs);
+  bool canRaw(const String &requestUri) override {
+    if (!_ufn || _method == HTTP_GET) {
+      return false;
     }
 
-    bool canUpload(String requestUri) override  {
-        if (!_ufn || !canHandle(HTTP_POST, requestUri))
-            return false;
+    return true;
+  }
 
-        return true;
+  bool canHandle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override {
+    if (_method != HTTP_ANY && _method != requestMethod) {
+      return false;
     }
 
-    bool handle(WebServer& server, HTTPMethod requestMethod, String requestUri) override {
-        (void) server;
-        if (!canHandle(requestMethod, requestUri))
-            return false;
+    return _uri->canHandle(requestUri, pathArgs) && (_filter != NULL ? _filter(server) : true);
+  }
 
-        _fn();
-        return true;
+  bool canUpload(WebServer &server, const String &requestUri) override {
+    if (!_ufn || !canHandle(server, HTTP_POST, requestUri)) {
+      return false;
     }
 
-    void upload(WebServer& server, String requestUri, HTTPUpload& upload) override {
-        (void) server;
-        (void) upload;
-        if (canUpload(requestUri))
-            _ufn();
+    return true;
+  }
+
+  bool canRaw(WebServer &server, const String &requestUri) override {
+    if (!_ufn || _method == HTTP_GET || (_filter != NULL ? _filter(server) == false : false)) {
+      return false;
     }
 
+    return true;
+  }
+
+  bool handle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override {
+    if (!canHandle(server, requestMethod, requestUri)) {
+      return false;
+    }
+
+    _fn();
+    return true;
+  }
+
+  void upload(WebServer &server, const String &requestUri, HTTPUpload &upload) override {
+    (void)upload;
+    if (canUpload(server, requestUri)) {
+      _ufn();
+    }
+  }
+
+  void raw(WebServer &server, const String &requestUri, HTTPRaw &raw) override {
+    (void)raw;
+    if (canRaw(server, requestUri)) {
+      _ufn();
+    }
+  }
+
+  FunctionRequestHandler &setFilter(WebServer::FilterFunction filter) {
+    _filter = filter;
+    return *this;
+  }
+
 protected:
-    WebServer::THandlerFunction _fn;
-    WebServer::THandlerFunction _ufn;
-    Uri *_uri;
-    HTTPMethod _method;
+  WebServer::THandlerFunction _fn;
+  WebServer::THandlerFunction _ufn;
+  // _filter should return 'true' when the request should be handled
+  // and 'false' when the request should be ignored
+  WebServer::FilterFunction _filter;
+  Uri *_uri;
+  HTTPMethod _method;
 };
 
 class StaticRequestHandler : public RequestHandler {
 public:
-    StaticRequestHandler(FS& fs, const char* path, const char* uri, const char* cache_header)
-    : _fs(fs)
-    , _uri(uri)
-    , _path(path)
-    , _cache_header(cache_header)
-    {
-        _isFile = fs.exists(path);
-        log_v("StaticRequestHandler: path=%s uri=%s isFile=%d, cache_header=%s\r\n", path, uri, _isFile, cache_header);
-        _baseUriLength = _uri.length();
+  StaticRequestHandler(FS &fs, const char *path, const char *uri, const char *cache_header) : _fs(fs), _uri(uri), _path(path), _cache_header(cache_header) {
+    File f = fs.open(path);
+    _isFile = (f && (!f.isDirectory()));
+    log_v(
+      "StaticRequestHandler: path=%s uri=%s isFile=%d, cache_header=%s\r\n", path, uri, _isFile, cache_header ? cache_header : ""
+    );  // issue 5506 - cache_header can be nullptr
+    _baseUriLength = _uri.length();
+  }
+
+  bool canHandle(HTTPMethod requestMethod, const String &requestUri) override {
+    if (requestMethod != HTTP_GET) {
+      return false;
     }
 
-    bool canHandle(HTTPMethod requestMethod, String requestUri) override  {
-        if (requestMethod != HTTP_GET)
-            return false;
+    if ((_isFile && requestUri != _uri) || !requestUri.startsWith(_uri)) {
+      return false;
+    }
 
-        if ((_isFile && requestUri != _uri) || !requestUri.startsWith(_uri))
-            return false;
+    return true;
+  }
 
-        return true;
+  bool canHandle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override {
+    if (requestMethod != HTTP_GET) {
+      return false;
+    }
+
+    if ((_isFile && requestUri != _uri) || !requestUri.startsWith(_uri)) {
+      return false;
+    }
+
+    if (_filter != NULL ? _filter(server) == false : false) {
+      return false;
     }
 
-    bool handle(WebServer& server, HTTPMethod requestMethod, String requestUri) override {
-        if (!canHandle(requestMethod, requestUri))
-            return false;
+    return true;
+  }
 
-        log_v("StaticRequestHandler::handle: request=%s _uri=%s\r\n", requestUri.c_str(), _uri.c_str());
+  bool handle(WebServer &server, HTTPMethod requestMethod, const String &requestUri) override {
+    if (!canHandle(server, requestMethod, requestUri)) {
+      return false;
+    }
+
+    log_v("StaticRequestHandler::handle: request=%s _uri=%s\r\n", requestUri.c_str(), _uri.c_str());
 
-        String path(_path);
+    String path(_path);
 
-        if (!_isFile) {
-            // Base URI doesn't point to a file.
-            // If a directory is requested, look for index file.
-            if (requestUri.endsWith("/")) 
-              requestUri += "index.htm";
+    if (!_isFile) {
+      // Base URI doesn't point to a file.
+      // If a directory is requested, look for index file.
+      if (requestUri.endsWith("/")) {
+        return handle(server, requestMethod, String(requestUri + "index.htm"));
+      }
 
-            // Append whatever follows this URI in request to get the file path.
-            path += requestUri.substring(_baseUriLength);
-        }
-        log_v("StaticRequestHandler::handle: path=%s, isFile=%d\r\n", path.c_str(), _isFile);
+      // Append whatever follows this URI in request to get the file path.
+      path += requestUri.substring(_baseUriLength);
+    }
+    log_v("StaticRequestHandler::handle: path=%s, isFile=%d\r\n", path.c_str(), _isFile);
 
-        String contentType = getContentType(path);
+    String contentType = getContentType(path);
+
+    // look for gz file, only if the original specified path is not a gz.  So part only works to send gzip via content encoding when a non compressed is asked for
+    // if you point the the path to gzip you will serve the gzip as content type "application/x-gzip", not text or javascript etc...
+    if (!path.endsWith(FPSTR(mimeTable[gz].endsWith)) && !_fs.exists(path)) {
+      String pathWithGz = path + FPSTR(mimeTable[gz].endsWith);
+      if (_fs.exists(pathWithGz)) {
+        path += FPSTR(mimeTable[gz].endsWith);
+      }
+    }
 
-        // look for gz file, only if the original specified path is not a gz.  So part only works to send gzip via content encoding when a non compressed is asked for
-        // if you point the the path to gzip you will serve the gzip as content type "application/x-gzip", not text or javascript etc...
-        if (!path.endsWith(FPSTR(mimeTable[gz].endsWith)) && !_fs.exists(path))  {
-            String pathWithGz = path + FPSTR(mimeTable[gz].endsWith);
-            if(_fs.exists(pathWithGz))
-                path += FPSTR(mimeTable[gz].endsWith);
-        }
+    File f = _fs.open(path, "r");
+    if (!f || !f.available()) {
+      return false;
+    }
 
-        File f = _fs.open(path, "r");
-        if (!f || !f.available())
-            return false;
+    String eTagCode;
 
-        if (_cache_header.length() != 0)
-            server.sendHeader("Cache-Control", _cache_header);
+    if (server._eTagEnabled) {
+      if (server._eTagFunction) {
+        eTagCode = (server._eTagFunction)(_fs, path);
+      } else {
+        eTagCode = calcETag(_fs, path);
+      }
 
-        server.streamFile(f, contentType);
+      if (server.header("If-None-Match") == eTagCode) {
+        server.send(304);
         return true;
+      }
+    }
+
+    if (_cache_header.length() != 0) {
+      server.sendHeader("Cache-Control", _cache_header);
+    }
+
+    if ((server._eTagEnabled) && (eTagCode.length() > 0)) {
+      server.sendHeader("ETag", eTagCode);
     }
 
-    static String getContentType(const String& path) {
-        char buff[sizeof(mimeTable[0].mimeType)];
-        // Check all entries but last one for match, return if found
-        for (size_t i=0; i < sizeof(mimeTable)/sizeof(mimeTable[0])-1; i++) {
-            strcpy_P(buff, mimeTable[i].endsWith);
-            if (path.endsWith(buff)) {
-                strcpy_P(buff, mimeTable[i].mimeType);
-                return String(buff);
-            }
-        }
-        // Fall-through and just return default type
-        strcpy_P(buff, mimeTable[sizeof(mimeTable)/sizeof(mimeTable[0])-1].mimeType);
+    server.streamFile(f, contentType);
+    return true;
+  }
+
+  static String getContentType(const String &path) {
+    char buff[sizeof(mimeTable[0].mimeType)];
+    // Check all entries but last one for match, return if found
+    for (size_t i = 0; i < sizeof(mimeTable) / sizeof(mimeTable[0]) - 1; i++) {
+      strcpy_P(buff, mimeTable[i].endsWith);
+      if (path.endsWith(buff)) {
+        strcpy_P(buff, mimeTable[i].mimeType);
         return String(buff);
+      }
     }
+    // Fall-through and just return default type
+    strcpy_P(buff, mimeTable[sizeof(mimeTable) / sizeof(mimeTable[0]) - 1].mimeType);
+    return String(buff);
+  }
+
+  // calculate an ETag for a file in filesystem based on md5 checksum
+  // that can be used in the http headers - include quotes.
+  static String calcETag(FS &fs, const String &path) {
+    String result;
+
+    // calculate eTag using md5 checksum
+    uint8_t md5_buf[16];
+    File f = fs.open(path, "r");
+    MD5Builder calcMD5;
+    calcMD5.begin();
+    calcMD5.addStream(f, f.size());
+    calcMD5.calculate();
+    calcMD5.getBytes(md5_buf);
+    f.close();
+    // create a minimal-length eTag using base64 byte[]->text encoding.
+    result = "\"" + base64::encode(md5_buf, 16) + "\"";
+    return (result);
+  }  // calcETag
+
+  StaticRequestHandler &setFilter(WebServer::FilterFunction filter) {
+    _filter = filter;
+    return *this;
+  }
 
 protected:
-    FS _fs;
-    String _uri;
-    String _path;
-    String _cache_header;
-    bool _isFile;
-    size_t _baseUriLength;
+  // _filter should return 'true' when the request should be handled
+  // and 'false' when the request should be ignored
+  WebServer::FilterFunction _filter;
+  FS _fs;
+  String _uri;
+  String _path;
+  String _cache_header;
+  bool _isFile;
+  size_t _baseUriLength;
 };
 
-
-#endif //REQUESTHANDLERSIMPL_H
+#endif  //REQUESTHANDLERSIMPL_H
diff --git a/libraries/WebServer/src/detail/mimetable.cpp b/libraries/WebServer/src/detail/mimetable.cpp
index 563556a6358..758f3ad34ef 100644
--- a/libraries/WebServer/src/detail/mimetable.cpp
+++ b/libraries/WebServer/src/detail/mimetable.cpp
@@ -1,35 +1,33 @@
 #include "mimetable.h"
 #include "pgmspace.h"
 
-namespace mime
-{
+namespace mime {
 
 // Table of extension->MIME strings stored in PROGMEM, needs to be global due to GCC section typing rules
-const Entry mimeTable[maxType] = 
-{
-    { ".html", "text/html" },
-    { ".htm", "text/html" },
-    { ".css", "text/css" },
-    { ".txt", "text/plain" },
-    { ".js", "application/javascript" },
-    { ".json", "application/json" },
-    { ".png", "image/png" },
-    { ".gif", "image/gif" },
-    { ".jpg", "image/jpeg" },
-    { ".ico", "image/x-icon" },
-    { ".svg", "image/svg+xml" },
-    { ".ttf", "application/x-font-ttf" },
-    { ".otf", "application/x-font-opentype" },
-    { ".woff", "application/font-woff" },
-    { ".woff2", "application/font-woff2" },
-    { ".eot", "application/vnd.ms-fontobject" },
-    { ".sfnt", "application/font-sfnt" },
-    { ".xml", "text/xml" },
-    { ".pdf", "application/pdf" },
-    { ".zip", "application/zip" },
-    { ".gz", "application/x-gzip" },
-    { ".appcache", "text/cache-manifest" },
-    { "", "application/octet-stream" } 
+const Entry mimeTable[maxType] = {
+  {".html", "text/html"},
+  {".htm", "text/html"},
+  {".css", "text/css"},
+  {".txt", "text/plain"},
+  {".js", "application/javascript"},
+  {".json", "application/json"},
+  {".png", "image/png"},
+  {".gif", "image/gif"},
+  {".jpg", "image/jpeg"},
+  {".ico", "image/x-icon"},
+  {".svg", "image/svg+xml"},
+  {".ttf", "application/x-font-ttf"},
+  {".otf", "application/x-font-opentype"},
+  {".woff", "application/font-woff"},
+  {".woff2", "application/font-woff2"},
+  {".eot", "application/vnd.ms-fontobject"},
+  {".sfnt", "application/font-sfnt"},
+  {".xml", "text/xml"},
+  {".pdf", "application/pdf"},
+  {".zip", "application/zip"},
+  {".gz", "application/x-gzip"},
+  {".appcache", "text/cache-manifest"},
+  {"", "application/octet-stream"}
 };
 
-}
+}  // namespace mime
diff --git a/libraries/WebServer/src/detail/mimetable.h b/libraries/WebServer/src/detail/mimetable.h
index 191356c489a..4732e59c466 100644
--- a/libraries/WebServer/src/detail/mimetable.h
+++ b/libraries/WebServer/src/detail/mimetable.h
@@ -1,12 +1,9 @@
 #ifndef __MIMETABLE_H__
 #define __MIMETABLE_H__
 
+namespace mime {
 
-namespace mime
-{
-
-enum type
-{
+enum type {
   html,
   htm,
   css,
@@ -33,15 +30,12 @@ enum type
   maxType
 };
 
-struct Entry
-{
-  const char endsWith[16]; 
+struct Entry {
+  const char endsWith[16];
   const char mimeType[32];
 };
 
-
 extern const Entry mimeTable[maxType];
-}
-
+}  // namespace mime
 
 #endif
diff --git a/libraries/WebServer/src/middleware/AuthenticationMiddleware.cpp b/libraries/WebServer/src/middleware/AuthenticationMiddleware.cpp
new file mode 100644
index 00000000000..cab25ba4e50
--- /dev/null
+++ b/libraries/WebServer/src/middleware/AuthenticationMiddleware.cpp
@@ -0,0 +1,82 @@
+#include "Middlewares.h"
+
+AuthenticationMiddleware &AuthenticationMiddleware::setUsername(const char *username) {
+  _username = username;
+  _callback = nullptr;
+  return *this;
+}
+
+AuthenticationMiddleware &AuthenticationMiddleware::setPassword(const char *password) {
+  _password = password;
+  _hash = false;
+  _callback = nullptr;
+  return *this;
+}
+
+AuthenticationMiddleware &AuthenticationMiddleware::setPasswordHash(const char *sha1AsBase64orHex) {
+  _password = sha1AsBase64orHex;
+  _hash = true;
+  _callback = nullptr;
+  return *this;
+}
+
+AuthenticationMiddleware &AuthenticationMiddleware::setCallback(WebServer::THandlerFunctionAuthCheck fn) {
+  assert(fn);
+  _callback = fn;
+  _hash = false;
+  _username = emptyString;
+  _password = emptyString;
+  return *this;
+}
+
+AuthenticationMiddleware &AuthenticationMiddleware::setRealm(const char *realm) {
+  _realm = realm;
+  return *this;
+}
+
+AuthenticationMiddleware &AuthenticationMiddleware::setAuthMethod(HTTPAuthMethod method) {
+  _method = method;
+  return *this;
+}
+
+AuthenticationMiddleware &AuthenticationMiddleware::setAuthFailureMessage(const char *message) {
+  _authFailMsg = message;
+  return *this;
+}
+
+bool AuthenticationMiddleware::isAllowed(WebServer &server) const {
+  if (_callback) {
+    return server.authenticate(_callback);
+  }
+
+  if (!_username.isEmpty() && !_password.isEmpty()) {
+    if (_hash) {
+      return server.authenticateBasicSHA1(_username.c_str(), _password.c_str());
+    } else {
+      return server.authenticate(_username.c_str(), _password.c_str());
+    }
+  }
+
+  return true;
+}
+
+bool AuthenticationMiddleware::run(WebServer &server, Middleware::Callback next) {
+  bool authenticationRequired = false;
+
+  if (_callback) {
+    authenticationRequired = !server.authenticate(_callback);
+  } else if (!_username.isEmpty() && !_password.isEmpty()) {
+    if (_hash) {
+      authenticationRequired = !server.authenticateBasicSHA1(_username.c_str(), _password.c_str());
+    } else {
+      authenticationRequired = !server.authenticate(_username.c_str(), _password.c_str());
+    }
+  }
+
+  if (authenticationRequired) {
+    server.requestAuthentication(_method, _realm, _authFailMsg);
+    return true;
+  } else {
+    return next();
+  }
+}
diff --git a/libraries/WebServer/src/middleware/CorsMiddleware.cpp b/libraries/WebServer/src/middleware/CorsMiddleware.cpp
new file mode 100644
index 00000000000..a52ccd59f23
--- /dev/null
+++ b/libraries/WebServer/src/middleware/CorsMiddleware.cpp
@@ -0,0 +1,47 @@
+#include "Middlewares.h"
+
+CorsMiddleware &CorsMiddleware::setOrigin(const char *origin) {
+  _origin = origin;
+  return *this;
+}
+
+CorsMiddleware &CorsMiddleware::setMethods(const char *methods) {
+  _methods = methods;
+  return *this;
+}
+
+CorsMiddleware &CorsMiddleware::setHeaders(const char *headers) {
+  _headers = headers;
+  return *this;
+}
+
+CorsMiddleware &CorsMiddleware::setAllowCredentials(bool credentials) {
+  _credentials = credentials;
+  return *this;
+}
+
+CorsMiddleware &CorsMiddleware::setMaxAge(uint32_t seconds) {
+  _maxAge = seconds;
+  return *this;
+}
+
+void CorsMiddleware::addCORSHeaders(WebServer &server) {
+  server.sendHeader(F("Access-Control-Allow-Origin"), _origin.c_str());
+  server.sendHeader(F("Access-Control-Allow-Methods"), _methods.c_str());
+  server.sendHeader(F("Access-Control-Allow-Headers"), _headers.c_str());
+  server.sendHeader(F("Access-Control-Allow-Credentials"), _credentials ? F("true") : F("false"));
+  server.sendHeader(F("Access-Control-Max-Age"), String(_maxAge).c_str());
+}
+
+bool CorsMiddleware::run(WebServer &server, Middleware::Callback next) {
+  // Origin header ? => CORS handling
+  if (server.hasHeader(F("Origin"))) {
+    addCORSHeaders(server);
+    // check if this is a preflight request => handle it and return
+    if (server.method() == HTTP_OPTIONS) {
+      server.send(200);
+      return true;
+    }
+  }
+  return next();
+}
diff --git a/libraries/WebServer/src/middleware/LoggingMiddleware.cpp b/libraries/WebServer/src/middleware/LoggingMiddleware.cpp
new file mode 100644
index 00000000000..e1f6d708c2e
--- /dev/null
+++ b/libraries/WebServer/src/middleware/LoggingMiddleware.cpp
@@ -0,0 +1,74 @@
+#include "Middlewares.h"
+
+void LoggingMiddleware::setOutput(Print &output) {
+  _out = &output;
+}
+
+bool LoggingMiddleware::run(WebServer &server, Middleware::Callback next) {
+  if (_out == nullptr) {
+    return next();
+  }
+
+  _out->print(F("* Connection from "));
+  _out->print(server.client().remoteIP().toString());
+  _out->print(F(":"));
+  _out->println(server.client().remotePort());
+
+  _out->print(F("> "));
+  const HTTPMethod method = server.method();
+  if (method == HTTP_ANY) {
+    _out->print(F("HTTP_ANY"));
+  } else {
+    _out->print(http_method_str(method));
+  }
+  _out->print(F(" "));
+  _out->print(server.uri());
+  _out->print(F(" "));
+  _out->println(server.version());
+
+  int n = server.headers();
+  for (int i = 0; i < n; i++) {
+    String v = server.header(i);
+    if (!v.isEmpty()) {
+      // because these 2 are always there, eventually empty: "Authorization", "If-None-Match"
+      _out->print(F("> "));
+      _out->print(server.headerName(i));
+      _out->print(F(": "));
+      _out->println(server.header(i));
+    }
+  }
+
+  _out->println(F(">"));
+
+  uint32_t elapsed = millis();
+  const bool ret = next();
+  elapsed = millis() - elapsed;
+
+  if (ret) {
+    _out->print(F("* Processed in "));
+    _out->print(elapsed);
+    _out->println(F(" ms"));
+    _out->print(F("< "));
+    _out->print(F("HTTP/1."));
+    _out->print(server.version());
+    _out->print(F(" "));
+    _out->print(server.responseCode());
+    _out->print(F(" "));
+    _out->println(WebServer::responseCodeToString(server.responseCode()));
+
+    n = server.responseHeaders();
+    for (int i = 0; i < n; i++) {
+      _out->print(F("< "));
+      _out->print(server.responseHeaderName(i));
+      _out->print(F(": "));
+      _out->println(server.responseHeader(i));
+    }
+
+    _out->println(F("<"));
+
+  } else {
+    _out->println(F("* Not processed!"));
+  }
+
+  return ret;
+}
diff --git a/libraries/WebServer/src/middleware/Middleware.h b/libraries/WebServer/src/middleware/Middleware.h
new file mode 100644
index 00000000000..080f5be0aba
--- /dev/null
+++ b/libraries/WebServer/src/middleware/Middleware.h
@@ -0,0 +1,54 @@
+#ifndef MIDDLEWARE_H
+#define MIDDLEWARE_H
+
+#include <assert.h>
+#include <functional>
+
+class MiddlewareChain;
+class WebServer;
+
+class Middleware {
+public:
+  typedef std::function<bool(void)> Callback;
+  typedef std::function<bool(WebServer &server, Callback next)> Function;
+
+  virtual ~Middleware() {}
+
+  virtual bool run(WebServer &server, Callback next) {
+    return next();
+  };
+
+private:
+  friend MiddlewareChain;
+  Middleware *_next = nullptr;
+  bool _freeOnRemoval = false;
+};
+
+class MiddlewareFunction : public Middleware {
+public:
+  MiddlewareFunction(Middleware::Function fn) : _fn(fn) {}
+
+  bool run(WebServer &server, Middleware::Callback next) override {
+    return _fn(server, next);
+  }
+
+private:
+  Middleware::Function _fn;
+};
+
+class MiddlewareChain {
+public:
+  ~MiddlewareChain();
+
+  void addMiddleware(Middleware::Function fn);
+  void addMiddleware(Middleware *middleware);
+  bool removeMiddleware(Middleware *middleware);
+
+  bool runChain(WebServer &server, Middleware::Callback finalizer);
+
+private:
+  Middleware *_root = nullptr;
+  Middleware *_current = nullptr;
+};
+
+#endif
diff --git a/libraries/WebServer/src/middleware/MiddlewareChain.cpp b/libraries/WebServer/src/middleware/MiddlewareChain.cpp
new file mode 100644
index 00000000000..56b3066caea
--- /dev/null
+++ b/libraries/WebServer/src/middleware/MiddlewareChain.cpp
@@ -0,0 +1,73 @@
+#include "Middleware.h"
+
+MiddlewareChain::~MiddlewareChain() {
+  Middleware *current = _root;
+  while (current) {
+    Middleware *next = current->_next;
+    if (current->_freeOnRemoval) {
+      delete current;
+    }
+    current = next;
+  }
+  _root = nullptr;
+}
+
+void MiddlewareChain::addMiddleware(Middleware::Function fn) {
+  MiddlewareFunction *middleware = new MiddlewareFunction(fn);
+  middleware->_freeOnRemoval = true;
+  addMiddleware(middleware);
+}
+
+void MiddlewareChain::addMiddleware(Middleware *middleware) {
+  if (!_root) {
+    _root = middleware;
+    return;
+  }
+  Middleware *current = _root;
+  while (current->_next) {
+    current = current->_next;
+  }
+  current->_next = middleware;
+}
+
+bool MiddlewareChain::removeMiddleware(Middleware *middleware) {
+  if (!_root) {
+    return false;
+  }
+  if (_root == middleware) {
+    _root = _root->_next;
+    if (middleware->_freeOnRemoval) {
+      delete middleware;
+    }
+    return true;
+  }
+  Middleware *current = _root;
+  while (current->_next) {
+    if (current->_next == middleware) {
+      current->_next = current->_next->_next;
+      if (middleware->_freeOnRemoval) {
+        delete middleware;
+      }
+      return true;
+    }
+    current = current->_next;
+  }
+  return false;
+}
+
+bool MiddlewareChain::runChain(WebServer &server, Middleware::Callback finalizer) {
+  if (!_root) {
+    return finalizer();
+  }
+  _current = _root;
+  Middleware::Callback next;
+  next = [this, &server, &next, finalizer]() {
+    if (!_current) {
+      return finalizer();
+    }
+    Middleware *that = _current;
+    _current = _current->_next;
+    return that->run(server, next);
+  };
+  return next();
+}
diff --git a/libraries/WebServer/src/uri/UriBraces.h b/libraries/WebServer/src/uri/UriBraces.h
index 4a6049b3c46..aa8fe60861d 100644
--- a/libraries/WebServer/src/uri/UriBraces.h
+++ b/libraries/WebServer/src/uri/UriBraces.h
@@ -5,62 +5,64 @@
 
 class UriBraces : public Uri {
 
-    public:
-        explicit UriBraces(const char *uri) : Uri(uri) {};
-        explicit UriBraces(const String &uri) : Uri(uri) {};
+public:
+  explicit UriBraces(const char *uri) : Uri(uri){};
+  explicit UriBraces(const String &uri) : Uri(uri){};
 
-        Uri* clone() const override final {
-            return new UriBraces(_uri);
-        };
+  Uri *clone() const override final {
+    return new UriBraces(_uri);
+  };
 
-        void initPathArgs(std::vector<String> &pathArgs) override final {
-            int numParams = 0, start = 0;
-            do {
-                start = _uri.indexOf("{}", start);
-                if (start > 0) {
-                    numParams++;
-                    start += 2;
-                }
-            } while (start > 0);
-            pathArgs.resize(numParams);
-        }
-
-        bool canHandle(const String &requestUri, std::vector<String> &pathArgs) override final {
-            if (Uri::canHandle(requestUri, pathArgs))
-                return true;
+  void initPathArgs(std::vector<String> &pathArgs) override final {
+    int numParams = 0, start = 0;
+    do {
+      start = _uri.indexOf("{}", start);
+      if (start > 0) {
+        numParams++;
+        start += 2;
+      }
+    } while (start > 0);
+    pathArgs.resize(numParams);
+  }
 
-            size_t uriLength = _uri.length();
-            unsigned int pathArgIndex = 0;
-            unsigned int requestUriIndex = 0;
-            for (unsigned int i = 0; i < uriLength; i++, requestUriIndex++) {
-                char uriChar = _uri[i];
-                char requestUriChar = requestUri[requestUriIndex];
+  bool canHandle(const String &requestUri, std::vector<String> &pathArgs) override final {
+    if (Uri::canHandle(requestUri, pathArgs)) {
+      return true;
+    }
 
-                if (uriChar == requestUriChar)
-                    continue;
-                if (uriChar != '{')
-                    return false;
+    size_t uriLength = _uri.length();
+    unsigned int pathArgIndex = 0;
+    unsigned int requestUriIndex = 0;
+    for (unsigned int i = 0; i < uriLength; i++, requestUriIndex++) {
+      char uriChar = _uri[i];
+      char requestUriChar = requestUri[requestUriIndex];
 
-                i += 2; // index of char after '}'
-                if (i >= uriLength) {
-                    // there is no char after '}'
-                    pathArgs[pathArgIndex] = requestUri.substring(requestUriIndex);
-                    return pathArgs[pathArgIndex].indexOf("/") == -1; // path argument may not contain a '/'
-                }
-                else
-                {
-                    char charEnd = _uri[i];
-                    int uriIndex = requestUri.indexOf(charEnd, requestUriIndex);
-                    if (uriIndex < 0)
-                        return false;
-                    pathArgs[pathArgIndex] = requestUri.substring(requestUriIndex, uriIndex);
-                    requestUriIndex = (unsigned int) uriIndex;
-                }
-                pathArgIndex++;
-            }
+      if (uriChar == requestUriChar) {
+        continue;
+      }
+      if (uriChar != '{') {
+        return false;
+      }
 
-            return requestUriIndex >= requestUri.length();
+      i += 2;  // index of char after '}'
+      if (i >= uriLength) {
+        // there is no char after '}'
+        pathArgs[pathArgIndex] = requestUri.substring(requestUriIndex);
+        return pathArgs[pathArgIndex].indexOf("/") == -1;  // path argument may not contain a '/'
+      } else {
+        char charEnd = _uri[i];
+        int uriIndex = requestUri.indexOf(charEnd, requestUriIndex);
+        if (uriIndex < 0) {
+          return false;
         }
+        pathArgs[pathArgIndex] = requestUri.substring(requestUriIndex, uriIndex);
+        requestUriIndex = (unsigned int)uriIndex;
+      }
+      pathArgIndex++;
+    }
+
+    return requestUriIndex >= requestUri.length();
+  }
 };
 
 #endif
diff --git a/libraries/WebServer/src/uri/UriGlob.h b/libraries/WebServer/src/uri/UriGlob.h
index 1e222cbabd1..5e6995421e4 100644
--- a/libraries/WebServer/src/uri/UriGlob.h
+++ b/libraries/WebServer/src/uri/UriGlob.h
@@ -6,17 +6,17 @@
 
 class UriGlob : public Uri {
 
-    public:
-        explicit UriGlob(const char *uri) : Uri(uri) {};
-        explicit UriGlob(const String &uri) : Uri(uri) {};
+public:
+  explicit UriGlob(const char *uri) : Uri(uri){};
+  explicit UriGlob(const String &uri) : Uri(uri){};
 
-        Uri* clone() const override final {
-            return new UriGlob(_uri);
-        };
+  Uri *clone() const override final {
+    return new UriGlob(_uri);
+  };
 
-        bool canHandle(const String &requestUri, __attribute__((unused)) std::vector<String> &pathArgs) override final {
-            return fnmatch(_uri.c_str(), requestUri.c_str(), 0) == 0;
-        }
+  bool canHandle(const String &requestUri, __attribute__((unused)) std::vector<String> &pathArgs) override final {
+    return fnmatch(_uri.c_str(), requestUri.c_str(), 0) == 0;
+  }
 };
 
 #endif
diff --git a/libraries/WebServer/src/uri/UriRegex.h b/libraries/WebServer/src/uri/UriRegex.h
index 05702017f4f..6412e7e46d6 100644
--- a/libraries/WebServer/src/uri/UriRegex.h
+++ b/libraries/WebServer/src/uri/UriRegex.h
@@ -6,39 +6,40 @@
 
 class UriRegex : public Uri {
 
-    public:
-        explicit UriRegex(const char *uri) : Uri(uri) {};
-        explicit UriRegex(const String &uri) : Uri(uri) {};
-
-        Uri* clone() const override final {
-            return new UriRegex(_uri);
-        };
-
-        void initPathArgs(std::vector<String> &pathArgs) override final {
-            std::regex rgx((_uri + "|").c_str());
-            std::smatch matches;
-            std::string s{""};
-            std::regex_search(s, matches, rgx);
-            pathArgs.resize(matches.size() - 1);
-        }
-
-        bool canHandle(const String &requestUri, std::vector<String> &pathArgs) override final {
-            if (Uri::canHandle(requestUri, pathArgs))
-                return true;
-
-            unsigned int pathArgIndex = 0;
-            std::regex rgx(_uri.c_str());
-            std::smatch matches;
-            std::string s(requestUri.c_str());
-            if (std::regex_search(s, matches, rgx)) {
-                for (size_t i = 1; i < matches.size(); ++i) {  // skip first
-                    pathArgs[pathArgIndex] = String(matches[i].str().c_str());
-                    pathArgIndex++;
-                }
-                return true;
-            }
-            return false;
-        }
+public:
+  explicit UriRegex(const char *uri) : Uri(uri){};
+  explicit UriRegex(const String &uri) : Uri(uri){};
+
+  Uri *clone() const override final {
+    return new UriRegex(_uri);
+  };
+
+  void initPathArgs(std::vector<String> &pathArgs) override final {
+    std::regex rgx((_uri + "|").c_str());
+    std::smatch matches;
+    std::string s{""};
+    std::regex_search(s, matches, rgx);
+    pathArgs.resize(matches.size() - 1);
+  }
+
+  bool canHandle(const String &requestUri, std::vector<String> &pathArgs) override final {
+    if (Uri::canHandle(requestUri, pathArgs)) {
+      return true;
+    }
+
+    unsigned int pathArgIndex = 0;
+    std::regex rgx(_uri.c_str());
+    std::smatch matches;
+    std::string s(requestUri.c_str());
+    if (std::regex_search(s, matches, rgx)) {
+      for (size_t i = 1; i < matches.size(); ++i) {  // skip first
+        pathArgs[pathArgIndex] = String(matches[i].str().c_str());
+        pathArgIndex++;
+      }
+      return true;
+    }
+    return false;
+  }
 };
 
 #endif
diff --git a/libraries/WiFi/examples/ETH_LAN8720/ETH_LAN8720.ino b/libraries/WiFi/examples/ETH_LAN8720/ETH_LAN8720.ino
deleted file mode 100644
index 44bd1f965a0..00000000000
--- a/libraries/WiFi/examples/ETH_LAN8720/ETH_LAN8720.ino
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
-    This sketch shows the Ethernet event usage
-
-*/
-
-#include <ETH.h>
-
-static bool eth_connected = false;
-
-void WiFiEvent(WiFiEvent_t event)
-{
-  switch (event) {
-    case SYSTEM_EVENT_ETH_START:
-      Serial.println("ETH Started");
-      //set eth hostname here
-      ETH.setHostname("esp32-ethernet");
-      break;
-    case SYSTEM_EVENT_ETH_CONNECTED:
-      Serial.println("ETH Connected");
-      break;
-    case SYSTEM_EVENT_ETH_GOT_IP:
-      Serial.print("ETH MAC: ");
-      Serial.print(ETH.macAddress());
-      Serial.print(", IPv4: ");
-      Serial.print(ETH.localIP());
-      if (ETH.fullDuplex()) {
-        Serial.print(", FULL_DUPLEX");
-      }
-      Serial.print(", ");
-      Serial.print(ETH.linkSpeed());
-      Serial.println("Mbps");
-      eth_connected = true;
-      break;
-    case SYSTEM_EVENT_ETH_DISCONNECTED:
-      Serial.println("ETH Disconnected");
-      eth_connected = false;
-      break;
-    case SYSTEM_EVENT_ETH_STOP:
-      Serial.println("ETH Stopped");
-      eth_connected = false;
-      break;
-    default:
-      break;
-  }
-}
-
-void testClient(const char * host, uint16_t port)
-{
-  Serial.print("\nconnecting to ");
-  Serial.println(host);
-
-  WiFiClient client;
-  if (!client.connect(host, port)) {
-    Serial.println("connection failed");
-    return;
-  }
-  client.printf("GET / HTTP/1.1\r\nHost: %s\r\n\r\n", host);
-  while (client.connected() && !client.available());
-  while (client.available()) {
-    Serial.write(client.read());
-  }
-
-  Serial.println("closing connection\n");
-  client.stop();
-}
-
-void setup()
-{
-  Serial.begin(115200);
-  WiFi.onEvent(WiFiEvent);
-  ETH.begin();
-}
-
-
-void loop()
-{
-  if (eth_connected) {
-    testClient("google.com", 80);
-  }
-  delay(10000);
-}
diff --git a/libraries/WiFi/examples/ETH_LAN8720_internal_clock/ETH_LAN8720_internal_clock.ino b/libraries/WiFi/examples/ETH_LAN8720_internal_clock/ETH_LAN8720_internal_clock.ino
deleted file mode 100644
index 6e726b7080e..00000000000
--- a/libraries/WiFi/examples/ETH_LAN8720_internal_clock/ETH_LAN8720_internal_clock.ino
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
-    This sketch shows how to configure different external or internal clock sources for the Ethernet PHY
-*/
-
-#include <ETH.h>
-
-/* 
-   * ETH_CLOCK_GPIO0_IN   - default: external clock from crystal oscillator
-   * ETH_CLOCK_GPIO0_OUT  - 50MHz clock from internal APLL output on GPIO0 - possibly an inverter is needed for LAN8720
-   * ETH_CLOCK_GPIO16_OUT - 50MHz clock from internal APLL output on GPIO16 - possibly an inverter is needed for LAN8720
-   * ETH_CLOCK_GPIO17_OUT - 50MHz clock from internal APLL inverted output on GPIO17 - tested with LAN8720
-*/
-#ifdef ETH_CLK_MODE
-#undef ETH_CLK_MODE
-#endif
-#define ETH_CLK_MODE    ETH_CLOCK_GPIO17_OUT
-
-// Pin# of the enable signal for the external crystal oscillator (-1 to disable for internal APLL source)
-#define ETH_POWER_PIN   -1
-
-// Type of the Ethernet PHY (LAN8720 or TLK110)
-#define ETH_TYPE        ETH_PHY_LAN8720
-
-// I²C-address of Ethernet PHY (0 or 1 for LAN8720, 31 for TLK110)
-#define ETH_ADDR        0
-
-// Pin# of the I²C clock signal for the Ethernet PHY
-#define ETH_MDC_PIN     15
-
-// Pin# of the I²C IO signal for the Ethernet PHY
-#define ETH_MDIO_PIN    2
-
-
-static bool eth_connected = false;
-
-void WiFiEvent(WiFiEvent_t event) {
-  switch (event) {
-    case SYSTEM_EVENT_ETH_START:
-      Serial.println("ETH Started");
-      //set eth hostname here
-      ETH.setHostname("esp32-ethernet");
-      break;
-    case SYSTEM_EVENT_ETH_CONNECTED:
-      Serial.println("ETH Connected");
-      break;
-    case SYSTEM_EVENT_ETH_GOT_IP:
-      Serial.print("ETH MAC: ");
-      Serial.print(ETH.macAddress());
-      Serial.print(", IPv4: ");
-      Serial.print(ETH.localIP());
-      if (ETH.fullDuplex()) {
-        Serial.print(", FULL_DUPLEX");
-      }
-      Serial.print(", ");
-      Serial.print(ETH.linkSpeed());
-      Serial.println("Mbps");
-      eth_connected = true;
-      break;
-    case SYSTEM_EVENT_ETH_DISCONNECTED:
-      Serial.println("ETH Disconnected");
-      eth_connected = false;
-      break;
-    case SYSTEM_EVENT_ETH_STOP:
-      Serial.println("ETH Stopped");
-      eth_connected = false;
-      break;
-    default:
-      break;
-  }
-}
-
-void testClient(const char * host, uint16_t port) {
-  Serial.print("\nconnecting to ");
-  Serial.println(host);
-
-  WiFiClient client;
-  if (!client.connect(host, port)) {
-    Serial.println("connection failed");
-    return;
-  }
-  client.printf("GET / HTTP/1.1\r\nHost: %s\r\n\r\n", host);
-  while (client.connected() && !client.available());
-  while (client.available()) {
-    Serial.write(client.read());
-  }
-
-  Serial.println("closing connection\n");
-  client.stop();
-}
-
-void setup() {
-  Serial.begin(115200);
-  WiFi.onEvent(WiFiEvent);
-  ETH.begin(ETH_ADDR, ETH_POWER_PIN, ETH_MDC_PIN, ETH_MDIO_PIN, ETH_TYPE, ETH_CLK_MODE);
-}
-
-
-void loop() {
-  if (eth_connected) {
-    testClient("google.com", 80);
-  }
-  delay(10000);
-}
diff --git a/libraries/WiFi/examples/ETH_TLK110/ETH_TLK110.ino b/libraries/WiFi/examples/ETH_TLK110/ETH_TLK110.ino
deleted file mode 100644
index f2c127945ad..00000000000
--- a/libraries/WiFi/examples/ETH_TLK110/ETH_TLK110.ino
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
-    This sketch shows the Ethernet event usage
-
-*/
-
-#include <ETH.h>
-
-#define ETH_ADDR        31
-#define ETH_POWER_PIN   17
-#define ETH_MDC_PIN     23
-#define ETH_MDIO_PIN    18
-#define ETH_TYPE        ETH_PHY_TLK110
-
-static bool eth_connected = false;
-
-void WiFiEvent(WiFiEvent_t event)
-{
-  switch (event) {
-    case SYSTEM_EVENT_ETH_START:
-      Serial.println("ETH Started");
-      //set eth hostname here
-      ETH.setHostname("esp32-ethernet");
-      break;
-    case SYSTEM_EVENT_ETH_CONNECTED:
-      Serial.println("ETH Connected");
-      break;
-    case SYSTEM_EVENT_ETH_GOT_IP:
-      Serial.print("ETH MAC: ");
-      Serial.print(ETH.macAddress());
-      Serial.print(", IPv4: ");
-      Serial.print(ETH.localIP());
-      if (ETH.fullDuplex()) {
-        Serial.print(", FULL_DUPLEX");
-      }
-      Serial.print(", ");
-      Serial.print(ETH.linkSpeed());
-      Serial.println("Mbps");
-      eth_connected = true;
-      break;
-    case SYSTEM_EVENT_ETH_DISCONNECTED:
-      Serial.println("ETH Disconnected");
-      eth_connected = false;
-      break;
-    case SYSTEM_EVENT_ETH_STOP:
-      Serial.println("ETH Stopped");
-      eth_connected = false;
-      break;
-    default:
-      break;
-  }
-}
-
-void testClient(const char * host, uint16_t port)
-{
-  Serial.print("\nconnecting to ");
-  Serial.println(host);
-
-  WiFiClient client;
-  if (!client.connect(host, port)) {
-    Serial.println("connection failed");
-    return;
-  }
-  client.printf("GET / HTTP/1.1\r\nHost: %s\r\n\r\n", host);
-  while (client.connected() && !client.available());
-  while (client.available()) {
-    Serial.write(client.read());
-  }
-
-  Serial.println("closing connection\n");
-  client.stop();
-}
-
-void setup()
-{
-  Serial.begin(115200);
-  WiFi.onEvent(WiFiEvent);
-  ETH.begin(ETH_ADDR, ETH_POWER_PIN, ETH_MDC_PIN, ETH_MDIO_PIN, ETH_TYPE);
-}
-
-
-void loop()
-{
-  if (eth_connected) {
-    testClient("google.com", 80);
-  }
-  delay(10000);
-}
diff --git a/libraries/WiFi/examples/FTM/FTM_Initiator/FTM_Initiator.ino b/libraries/WiFi/examples/FTM/FTM_Initiator/FTM_Initiator.ino
new file mode 100644
index 00000000000..39322c07cdd
--- /dev/null
+++ b/libraries/WiFi/examples/FTM/FTM_Initiator/FTM_Initiator.ino
@@ -0,0 +1,91 @@
+/* Wi-Fi FTM Initiator Arduino Example
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+#include "WiFi.h"
+
+/*
+   THIS FEATURE IS SUPPORTED ONLY BY ESP32-S2 AND ESP32-C3
+*/
+
+// Change the SSID and PASSWORD here if needed
+const char *WIFI_FTM_SSID = "WiFi_FTM_Responder";  // SSID of AP that has FTM Enabled
+const char *WIFI_FTM_PASS = "ftm_responder";       // STA Password
+
+// FTM settings
+// Number of FTM frames requested in terms of 4 or 8 bursts (allowed values - 0 (No pref), 16, 24, 32, 64)
+const uint8_t FTM_FRAME_COUNT = 16;
+// Requested time period between consecutive FTM bursts in 100’s of milliseconds (allowed values - 0 (No pref) or 2-255)
+const uint16_t FTM_BURST_PERIOD = 2;
+
+// Semaphore to signal when FTM Report has been received
+SemaphoreHandle_t ftmSemaphore;
+// Status of the received FTM Report
+bool ftmSuccess = true;
+
+// FTM report handler with the calculated data from the round trip
+// WARNING: This function is called from a separate FreeRTOS task (thread)!
+void onFtmReport(arduino_event_t *event) {
+  const char *status_str[5] = {"SUCCESS", "UNSUPPORTED", "CONF_REJECTED", "NO_RESPONSE", "FAIL"};
+  wifi_event_ftm_report_t *report = &event->event_info.wifi_ftm_report;
+  // Set the global report status
+  ftmSuccess = report->status == FTM_STATUS_SUCCESS;
+  if (ftmSuccess) {
+    // The estimated distance in meters may vary depending on some factors (see README file)
+    Serial.printf("FTM Estimate: Distance: %.2f m, Return Time: %lu ns\n", (float)report->dist_est / 100.0, report->rtt_est);
+    // Pointer to FTM Report with multiple entries, should be freed after use
+    free(report->ftm_report_data);
+  } else {
+    Serial.print("FTM Error: ");
+    Serial.println(status_str[report->status]);
+  }
+  // Signal that report is received
+  xSemaphoreGive(ftmSemaphore);
+}
+
+// Initiate FTM Session and wait for FTM Report
+bool getFtmReport() {
+  if (!WiFi.initiateFTM(FTM_FRAME_COUNT, FTM_BURST_PERIOD)) {
+    Serial.println("FTM Error: Initiate Session Failed");
+    return false;
+  }
+  // Wait for signal that report is received and return true if status was success
+  return xSemaphoreTake(ftmSemaphore, portMAX_DELAY) == pdPASS && ftmSuccess;
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  // Create binary semaphore (initialized taken and can be taken/given from any thread/ISR)
+  ftmSemaphore = xSemaphoreCreateBinary();
+
+  // Will call onFtmReport() from another thread with FTM Report events.
+  WiFi.onEvent(onFtmReport, ARDUINO_EVENT_WIFI_FTM_REPORT);
+
+  // Connect to AP that has FTM Enabled
+  Serial.println("Connecting to FTM Responder");
+  WiFi.begin(WIFI_FTM_SSID, WIFI_FTM_PASS);
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("");
+  Serial.println("WiFi Connected");
+
+  Serial.print("Initiating FTM session with Frame Count ");
+  Serial.print(FTM_FRAME_COUNT);
+  Serial.print(" and Burst Period ");
+  Serial.print(FTM_BURST_PERIOD * 100);
+  Serial.println(" ms");
+
+  // Request FTM reports until one fails
+  while (getFtmReport());
+}
+
+void loop() {
+  delay(1000);
+}
diff --git a/libraries/WiFi/examples/FTM/FTM_Initiator/README.md b/libraries/WiFi/examples/FTM/FTM_Initiator/README.md
new file mode 100644
index 00000000000..b9c7f8d438d
--- /dev/null
+++ b/libraries/WiFi/examples/FTM/FTM_Initiator/README.md
@@ -0,0 +1,106 @@
+# Wi-Fi FTM Initiator Arduino Example
+
+This example demonstrates how to use the Fine Timing Measurement (FTM) to calculate the distance from the Access Point and the device. This is calculated by the Wi-Fi Round Trip Time (Wi-Fi RTT) introduced on the [IEEE Std 802.11-2016](https://en.wikipedia.org/wiki/IEEE_802.11mc) standard.
+
+This example was based on the [ESP-IDF FTM](https://github.com/espressif/esp-idf/tree/master/examples/wifi/ftm). See the README file for more details about on how to use this feature.
+
+Some usages for this feature includes:
+
+* Indoor positioning systems.
+* Navigation.
+* Device Location.
+* Smart Devices.
+* Alarms.
+
+# Supported Targets
+
+Currently, this example supports the following targets:
+
+| Supported Targets | ESP32-S2 | ESP32-C3 |
+| ----------------- | -------- | -------- |
+
+## How to Use Example
+
+In order to use the FTM, you will need a Responder or Wi-Fi router with FTM capabilities. If you don't own one, you can use a second ESP32-S2 or ESP32-C3 to simulate one.
+See the **Responder** example to prepare the environment.
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+### Configure the Project
+
+To configure this project, you can change the following configuration related to FTM feature:
+
+```c
+// Change the SSID and PASSWORD here if needed
+const char * WIFI_FTM_SSID = "WiFi_FTM_Responder"; // SSID of AP that has FTM Enabled
+const char * WIFI_FTM_PASS = "ftm_responder"; // STA Password
+
+// FTM settings
+// Number of FTM frames requested in terms of 4 or 8 bursts (allowed values - 0 (No pref), 16, 24, 32, 64)
+const uint8_t FTM_FRAME_COUNT = 16;
+// Requested time period between consecutive FTM bursts in 100’s of milliseconds (allowed values - 0 (No pref) or 2-255)
+const uint16_t FTM_BURST_PERIOD = 2;
+```
+
+* Change the Wi-Fi `SSID` and `PASSWORD` as the same as the Responder/Router.
+* Change `FTM_FRAME_COUNT` with the number of frames requested to the Responder.
+* Change `FTM_BURST_PERIOD` with the time between each FTM burst.
+
+To see more details about FTM, please see the [ESP-IDF docs](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-reference/network/esp_wifi.html).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Log Output
+
+Expected log output:
+
+```
+ESP-ROM:esp32s2-rc4-20191025
+Build:Oct 25 2019
+rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT)
+SPIWP:0xee
+mode:DIO, clock div:1
+load:0x3ffe6100,len:0x4b0
+load:0x4004c000,len:0xa6c
+load:0x40050000,len:0x25c4
+entry 0x4004c198
+Connecting to FTM Responder
+.....
+WiFi Connected
+Initiating FTM session with Frame Count 16 and Burst Period 200 ms
+FTM Estimate: Distance: 0.13 m, Return Time: 0 ns
+FTM Estimate: Distance: 0.13 m, Return Time: 0 ns
+FTM Estimate: Distance: 0.13 m, Return Time: 0 ns
+FTM Estimate: Distance: 0.00 m, Return Time: 0 ns
+...
+```
+
+## Troubleshooting
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source.***
+
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persist, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/WiFi/examples/FTM/FTM_Initiator/ci.json b/libraries/WiFi/examples/FTM/FTM_Initiator/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/FTM/FTM_Initiator/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/FTM/FTM_Responder/FTM_Responder.ino b/libraries/WiFi/examples/FTM/FTM_Responder/FTM_Responder.ino
new file mode 100644
index 00000000000..fd6bf2f3529
--- /dev/null
+++ b/libraries/WiFi/examples/FTM/FTM_Responder/FTM_Responder.ino
@@ -0,0 +1,23 @@
+/* Wi-Fi FTM Responder Arduino Example
+
+  This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+  Unless required by applicable law or agreed to in writing, this
+  software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+  CONDITIONS OF ANY KIND, either express or implied.
+*/
+#include "WiFi.h"
+// Change the SSID and PASSWORD here if needed
+const char *WIFI_FTM_SSID = "WiFi_FTM_Responder";
+const char *WIFI_FTM_PASS = "ftm_responder";
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Starting SoftAP with FTM Responder support");
+  // Enable AP with FTM support (last argument is 'true')
+  WiFi.softAP(WIFI_FTM_SSID, WIFI_FTM_PASS, 1, 0, 4, true);
+}
+
+void loop() {
+  delay(1000);
+}
diff --git a/libraries/WiFi/examples/FTM/FTM_Responder/README.md b/libraries/WiFi/examples/FTM/FTM_Responder/README.md
new file mode 100644
index 00000000000..fdcf1ab921b
--- /dev/null
+++ b/libraries/WiFi/examples/FTM/FTM_Responder/README.md
@@ -0,0 +1,90 @@
+# Wi-Fi FTM Responder Arduino Example
+
+This example demonstrates how to use the Fine Timing Measurement (FTM) to calculate the distance from the Access Point and the device. This is calculated by the Wi-Fi Round Trip Time (Wi-Fi RTT) introduced on the [IEEE Std 802.11-2016](https://en.wikipedia.org/wiki/IEEE_802.11mc) standard.
+
+This example will simulate the Router with FTM capability.
+
+This example was based on the [ESP-IDF FTM](https://github.com/espressif/esp-idf/tree/master/examples/wifi/ftm). See the README file for more details about on how to use this feature.
+
+Some usages for this feature includes:
+
+* Indoor positioning systems.
+* Navigation.
+* Device Location.
+* Smart Devices.
+* Alarms.
+
+# Supported Targets
+
+Currently, this example supports the following targets:
+
+| Supported Targets | ESP32-S2 | ESP32-C3 |
+| ----------------- | -------- | -------- |
+
+## How to Use Example
+
+See the **Initiator** example to prepare the environment.
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+### Configure the Project
+
+To configure this project, you can change the following configuration related to STA:
+
+```c
+// Change the SSID and PASSWORD here if needed
+const char * WIFI_FTM_SSID = "WiFi_FTM_Responder";
+const char * WIFI_FTM_PASS = "ftm_responder";
+```
+
+* Change the Wi-Fi `SSID` and `PASSWORD` as the same as the Initiator.
+
+To see more details about FTM, please see the [ESP-IDF docs](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-reference/network/esp_wifi.html).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Log Output
+
+Expected log output:
+
+```
+Build:Oct 25 2019
+rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT)
+SPIWP:0xee
+mode:DIO, clock div:1
+load:0x3ffe6100,len:0x4b0
+load:0x4004c000,len:0xa6c
+load:0x40050000,len:0x25c4
+entry 0x4004c198
+Starting SoftAP with FTM Responder support
+```
+
+## Troubleshooting
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source.***
+
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persist, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/WiFi/examples/FTM/FTM_Responder/ci.json b/libraries/WiFi/examples/FTM/FTM_Responder/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/FTM/FTM_Responder/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/SimpleWiFiServer/SimpleWiFiServer.ino b/libraries/WiFi/examples/SimpleWiFiServer/SimpleWiFiServer.ino
index 91ac9078613..ad5bdee6ec5 100644
--- a/libraries/WiFi/examples/SimpleWiFiServer/SimpleWiFiServer.ino
+++ b/libraries/WiFi/examples/SimpleWiFiServer/SimpleWiFiServer.ino
@@ -10,8 +10,8 @@
  http://yourAddress/H turns the LED on
  http://yourAddress/L turns it off
 
- This example is written for a network using WPA encryption. For
- WEP or WPA, change the Wifi.begin() call accordingly.
+ This example is written for a network using WPA2 encryption. For insecure
+ WEP or WPA, change the Wifi.begin() call and use Wifi.setMinSecurity() accordingly.
 
  Circuit:
  * WiFi shield attached
@@ -20,61 +20,57 @@
  created for arduino 25 Nov 2012
  by Tom Igoe
 
-ported for sparkfun esp32 
+ported for sparkfun esp32
 31.01.2017 by Jan Hendrik Berlin
- 
+
  */
 
 #include <WiFi.h>
 
-const char* ssid     = "yourssid";
-const char* password = "yourpasswd";
+const char *ssid = "yourssid";
+const char *password = "yourpasswd";
 
-WiFiServer server(80);
+NetworkServer server(80);
 
-void setup()
-{
-    Serial.begin(115200);
-    pinMode(5, OUTPUT);      // set the LED pin mode
+void setup() {
+  Serial.begin(115200);
+  pinMode(5, OUTPUT);  // set the LED pin mode
 
-    delay(10);
+  delay(10);
 
-    // We start by connecting to a WiFi network
+  // We start by connecting to a WiFi network
 
-    Serial.println();
-    Serial.println();
-    Serial.print("Connecting to ");
-    Serial.println(ssid);
+  Serial.println();
+  Serial.println();
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
 
-    WiFi.begin(ssid, password);
+  WiFi.begin(ssid, password);
 
-    while (WiFi.status() != WL_CONNECTED) {
-        delay(500);
-        Serial.print(".");
-    }
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
 
-    Serial.println("");
-    Serial.println("WiFi connected.");
-    Serial.println("IP address: ");
-    Serial.println(WiFi.localIP());
-    
-    server.begin();
+  Serial.println("");
+  Serial.println("WiFi connected.");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
 
+  server.begin();
 }
 
-int value = 0;
-
-void loop(){
- WiFiClient client = server.available();   // listen for incoming clients
+void loop() {
+  NetworkClient client = server.accept();  // listen for incoming clients
 
-  if (client) {                             // if you get a client,
-    Serial.println("New Client.");           // print a message out the serial port
-    String currentLine = "";                // make a String to hold incoming data from the client
-    while (client.connected()) {            // loop while the client's connected
-      if (client.available()) {             // if there's bytes to read from the client,
-        char c = client.read();             // read a byte, then
-        Serial.write(c);                    // print it out the serial monitor
-        if (c == '\n') {                    // if the byte is a newline character
+  if (client) {                     // if you get a client,
+    Serial.println("New Client.");  // print a message out the serial port
+    String currentLine = "";        // make a String to hold incoming data from the client
+    while (client.connected()) {    // loop while the client's connected
+      if (client.available()) {     // if there's bytes to read from the client,
+        char c = client.read();     // read a byte, then
+        Serial.write(c);            // print it out the serial monitor
+        if (c == '\n') {            // if the byte is a newline character
 
           // if the current line is blank, you got two newline characters in a row.
           // that's the end of the client HTTP request, so send a response:
@@ -93,7 +89,7 @@ void loop(){
             client.println();
             // break out of the while loop:
             break;
-          } else {    // if you got a newline, then clear currentLine:
+          } else {  // if you got a newline, then clear currentLine:
             currentLine = "";
           }
         } else if (c != '\r') {  // if you got anything else but a carriage return character,
@@ -102,10 +98,10 @@ void loop(){
 
         // Check to see if the client request was "GET /H" or "GET /L":
         if (currentLine.endsWith("GET /H")) {
-          digitalWrite(5, HIGH);               // GET /H turns the LED on
+          digitalWrite(5, HIGH);  // GET /H turns the LED on
         }
         if (currentLine.endsWith("GET /L")) {
-          digitalWrite(5, LOW);                // GET /L turns the LED off
+          digitalWrite(5, LOW);  // GET /L turns the LED off
         }
       }
     }
diff --git a/libraries/WiFi/examples/SimpleWiFiServer/ci.json b/libraries/WiFi/examples/SimpleWiFiServer/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/SimpleWiFiServer/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WPS/README.md b/libraries/WiFi/examples/WPS/README.md
index 69431423d5a..6c53535bef1 100644
--- a/libraries/WiFi/examples/WPS/README.md
+++ b/libraries/WiFi/examples/WPS/README.md
@@ -26,7 +26,7 @@ WPS Timedout, retrying
 WPS Timedout, retrying
 ```
 
-#### WPS Push Button Successfull
+#### WPS Push Button Successful
 
 ```
 ets Jun  8 2016 00:22:57
@@ -46,7 +46,7 @@ entry 0x40078a14
 
 Starting WPS
 Station Mode Started
-WPS Successfull, stopping WPS and connecting to: < Your Router SSID >
+WPS Successful, stopping WPS and connecting to: < Your Router SSID >
 Disconnected from station, attempting reconnection
 Connected to : < Your Router SSID >
 Got IP: 192.168.1.100
@@ -79,7 +79,7 @@ WPS Timedout, retrying
 WPS_PIN = 71321622
 ```
 
-#### WPS PIN Successfull
+#### WPS PIN Successful
 
 ```
 ets Jun  8 2016 00:22:57
@@ -97,7 +97,7 @@ entry 0x40078a14
 Starting WPS
 Station Mode Started
 WPS_PIN = 36807581
-WPS Successfull, stopping WPS and connecting to: <Your Router SSID>
+WPS Successful, stopping WPS and connecting to: <Your Router SSID>
 Disconnected from station, attempting reconnection
 Connected to :<Your Router SSID>
 Got IP: 192.168.1.100
diff --git a/libraries/WiFi/examples/WPS/WPS.ino b/libraries/WiFi/examples/WPS/WPS.ino
index 6b134375840..aacdd14ddab 100644
--- a/libraries/WiFi/examples/WPS/WPS.ino
+++ b/libraries/WiFi/examples/WPS/WPS.ino
@@ -14,96 +14,103 @@ Author:
 Pranav Cherukupalli <cherukupallip@gmail.com>
 */
 
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#error "WPS is only supported in SoCs with native Wi-Fi support"
+#endif
+
 #include "WiFi.h"
 #include "esp_wps.h"
 /*
 Change the definition of the WPS mode
 from WPS_TYPE_PBC to WPS_TYPE_PIN in
 the case that you are using pin type
-WPS
+WPS (pin is 00000000)
 */
-#define ESP_WPS_MODE      WPS_TYPE_PBC
-#define ESP_MANUFACTURER  "ESPRESSIF"
-#define ESP_MODEL_NUMBER  "ESP32"
-#define ESP_MODEL_NAME    "ESPRESSIF IOT"
-#define ESP_DEVICE_NAME   "ESP STATION"
-
-static esp_wps_config_t config;
+#define ESP_WPS_MODE WPS_TYPE_PBC
 
-void wpsInitConfig(){
-  config.crypto_funcs = &g_wifi_default_wps_crypto_funcs;
+void wpsStart() {
+  esp_wps_config_t config;
+  memset(&config, 0, sizeof(esp_wps_config_t));
+  //Same as config = WPS_CONFIG_INIT_DEFAULT(ESP_WPS_MODE);
   config.wps_type = ESP_WPS_MODE;
-  strcpy(config.factory_info.manufacturer, ESP_MANUFACTURER);
-  strcpy(config.factory_info.model_number, ESP_MODEL_NUMBER);
-  strcpy(config.factory_info.model_name, ESP_MODEL_NAME);
-  strcpy(config.factory_info.device_name, ESP_DEVICE_NAME);
+  strcpy(config.factory_info.manufacturer, "ESPRESSIF");
+  strcpy(config.factory_info.model_number, CONFIG_IDF_TARGET);
+  strcpy(config.factory_info.model_name, "ESPRESSIF IOT");
+  strcpy(config.factory_info.device_name, "ESP DEVICE");
+  strcpy(config.pin, "00000000");
+  esp_err_t err = esp_wifi_wps_enable(&config);
+  if (err != ESP_OK) {
+    Serial.printf("WPS Enable Failed: 0x%x: %s\n", err, esp_err_to_name(err));
+    return;
+  }
+
+  err = esp_wifi_wps_start(0);
+  if (err != ESP_OK) {
+    Serial.printf("WPS Start Failed: 0x%x: %s\n", err, esp_err_to_name(err));
+  }
+}
+
+void wpsStop() {
+  esp_err_t err = esp_wifi_wps_disable();
+  if (err != ESP_OK) {
+    Serial.printf("WPS Disable Failed: 0x%x: %s\n", err, esp_err_to_name(err));
+  }
 }
 
-String wpspin2string(uint8_t a[]){
+String wpspin2string(uint8_t a[]) {
   char wps_pin[9];
-  for(int i=0;i<8;i++){
+  for (int i = 0; i < 8; i++) {
     wps_pin[i] = a[i];
   }
   wps_pin[8] = '\0';
   return (String)wps_pin;
 }
 
-void WiFiEvent(WiFiEvent_t event, system_event_info_t info){
-  switch(event){
-    case SYSTEM_EVENT_STA_START:
-      Serial.println("Station Mode Started");
-      break;
-    case SYSTEM_EVENT_STA_GOT_IP:
+// WARNING: WiFiEvent is called from a separate FreeRTOS task (thread)!
+void WiFiEvent(WiFiEvent_t event, arduino_event_info_t info) {
+  switch (event) {
+    case ARDUINO_EVENT_WIFI_STA_START: Serial.println("Station Mode Started"); break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP:
       Serial.println("Connected to :" + String(WiFi.SSID()));
       Serial.print("Got IP: ");
       Serial.println(WiFi.localIP());
       break;
-    case SYSTEM_EVENT_STA_DISCONNECTED:
+    case ARDUINO_EVENT_WIFI_STA_DISCONNECTED:
       Serial.println("Disconnected from station, attempting reconnection");
       WiFi.reconnect();
       break;
-    case SYSTEM_EVENT_STA_WPS_ER_SUCCESS:
+    case ARDUINO_EVENT_WPS_ER_SUCCESS:
       Serial.println("WPS Successful, stopping WPS and connecting to: " + String(WiFi.SSID()));
-      esp_wifi_wps_disable();
+      wpsStop();
       delay(10);
       WiFi.begin();
       break;
-    case SYSTEM_EVENT_STA_WPS_ER_FAILED:
+    case ARDUINO_EVENT_WPS_ER_FAILED:
       Serial.println("WPS Failed, retrying");
-      esp_wifi_wps_disable();
-      esp_wifi_wps_enable(&config);
-      esp_wifi_wps_start(0);
-      break;
-    case SYSTEM_EVENT_STA_WPS_ER_TIMEOUT:
-      Serial.println("WPS Timeout, retrying");
-      esp_wifi_wps_disable();
-      esp_wifi_wps_enable(&config);
-      esp_wifi_wps_start(0);
+      wpsStop();
+      wpsStart();
       break;
-    case SYSTEM_EVENT_STA_WPS_ER_PIN:
-      Serial.println("WPS_PIN = " + wpspin2string(info.sta_er_pin.pin_code));
-      break;
-    default:
+    case ARDUINO_EVENT_WPS_ER_TIMEOUT:
+      Serial.println("WPS Timedout, retrying");
+      wpsStop();
+      wpsStart();
       break;
+    case ARDUINO_EVENT_WPS_ER_PIN: Serial.println("WPS_PIN = " + wpspin2string(info.wps_er_pin.pin_code)); break;
+    default:                       break;
   }
 }
 
-void setup(){
+void setup() {
   Serial.begin(115200);
   delay(10);
-
   Serial.println();
-
-  WiFi.onEvent(WiFiEvent);
+  WiFi.onEvent(WiFiEvent);  // Will call WiFiEvent() from another thread.
   WiFi.mode(WIFI_MODE_STA);
-
   Serial.println("Starting WPS");
-
-  wpsInitConfig();
-  esp_wifi_wps_enable(&config);
-  esp_wifi_wps_start(0);
+  wpsStart();
 }
 
-void loop(){
+void loop() {
   //nothing to do here
 }
diff --git a/libraries/WiFi/examples/WPS/ci.json b/libraries/WiFi/examples/WPS/ci.json
new file mode 100644
index 00000000000..36babb82730
--- /dev/null
+++ b/libraries/WiFi/examples/WPS/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino b/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino
index 4e654d12c79..19fd105b3f8 100644
--- a/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino
+++ b/libraries/WiFi/examples/WiFiAccessPoint/WiFiAccessPoint.ino
@@ -12,17 +12,18 @@
 */
 
 #include <WiFi.h>
-#include <WiFiClient.h>
+#include <NetworkClient.h>
 #include <WiFiAP.h>
 
-#define LED_BUILTIN 2   // Set the GPIO pin where you connected your test LED or comment this line out if your dev board has a built-in LED
+#ifndef LED_BUILTIN
+#define LED_BUILTIN 2  // Set the GPIO pin where you connected your test LED or comment this line out if your dev board has a built-in LED
+#endif
 
 // Set these to your desired credentials.
 const char *ssid = "yourAP";
 const char *password = "yourPassword";
 
-WiFiServer server(80);
-
+NetworkServer server(80);
 
 void setup() {
   pinMode(LED_BUILTIN, OUTPUT);
@@ -32,7 +33,11 @@ void setup() {
   Serial.println("Configuring access point...");
 
   // You can remove the password parameter if you want the AP to be open.
-  WiFi.softAP(ssid, password);
+  // a valid password must have more than 7 characters
+  if (!WiFi.softAP(ssid, password)) {
+    log_e("Soft AP creation failed.");
+    while (1);
+  }
   IPAddress myIP = WiFi.softAPIP();
   Serial.print("AP IP address: ");
   Serial.println(myIP);
@@ -42,16 +47,16 @@ void setup() {
 }
 
 void loop() {
-  WiFiClient client = server.available();   // listen for incoming clients
+  NetworkClient client = server.accept();  // listen for incoming clients
 
-  if (client) {                             // if you get a client,
-    Serial.println("New Client.");           // print a message out the serial port
-    String currentLine = "";                // make a String to hold incoming data from the client
-    while (client.connected()) {            // loop while the client's connected
-      if (client.available()) {             // if there's bytes to read from the client,
-        char c = client.read();             // read a byte, then
-        Serial.write(c);                    // print it out the serial monitor
-        if (c == '\n') {                    // if the byte is a newline character
+  if (client) {                     // if you get a client,
+    Serial.println("New Client.");  // print a message out the serial port
+    String currentLine = "";        // make a String to hold incoming data from the client
+    while (client.connected()) {    // loop while the client's connected
+      if (client.available()) {     // if there's bytes to read from the client,
+        char c = client.read();     // read a byte, then
+        Serial.write(c);            // print it out the serial monitor
+        if (c == '\n') {            // if the byte is a newline character
 
           // if the current line is blank, you got two newline characters in a row.
           // that's the end of the client HTTP request, so send a response:
@@ -70,7 +75,7 @@ void loop() {
             client.println();
             // break out of the while loop:
             break;
-          } else {    // if you got a newline, then clear currentLine:
+          } else {  // if you got a newline, then clear currentLine:
             currentLine = "";
           }
         } else if (c != '\r') {  // if you got anything else but a carriage return character,
@@ -79,10 +84,10 @@ void loop() {
 
         // Check to see if the client request was "GET /H" or "GET /L":
         if (currentLine.endsWith("GET /H")) {
-          digitalWrite(LED_BUILTIN, HIGH);               // GET /H turns the LED on
+          digitalWrite(LED_BUILTIN, HIGH);  // GET /H turns the LED on
         }
         if (currentLine.endsWith("GET /L")) {
-          digitalWrite(LED_BUILTIN, LOW);                // GET /L turns the LED off
+          digitalWrite(LED_BUILTIN, LOW);  // GET /L turns the LED off
         }
       }
     }
diff --git a/libraries/WiFi/examples/WiFiAccessPoint/ci.json b/libraries/WiFi/examples/WiFiAccessPoint/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiAccessPoint/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiBlueToothSwitch/WiFiBlueToothSwitch.ino b/libraries/WiFi/examples/WiFiBlueToothSwitch/WiFiBlueToothSwitch.ino
index e795bad83d6..805458ce694 100644
--- a/libraries/WiFi/examples/WiFiBlueToothSwitch/WiFiBlueToothSwitch.ino
+++ b/libraries/WiFi/examples/WiFiBlueToothSwitch/WiFiBlueToothSwitch.ino
@@ -20,51 +20,59 @@
 #define STA_PASS "your-pass"
 #define AP_SSID  "esp32"
 
-enum { STEP_BTON, STEP_BTOFF, STEP_STA, STEP_AP, STEP_AP_STA, STEP_OFF, STEP_BT_STA, STEP_END };
+enum {
+  STEP_BTON,
+  STEP_BTOFF,
+  STEP_STA,
+  STEP_AP,
+  STEP_AP_STA,
+  STEP_OFF,
+  STEP_BT_STA,
+  STEP_END
+};
 
-void onButton(){
+void onButton() {
   static uint32_t step = STEP_BTON;
-  switch(step){
-    case STEP_BTON://BT Only
+  switch (step) {
+    case STEP_BTON:  //BT Only
       Serial.println("** Starting BT");
       btStart();
-    break;
-    case STEP_BTOFF://All Off
+      break;
+    case STEP_BTOFF:  //All Off
       Serial.println("** Stopping BT");
       btStop();
-    break;
-    case STEP_STA://STA Only
+      break;
+    case STEP_STA:  //STA Only
       Serial.println("** Starting STA");
       WiFi.begin(STA_SSID, STA_PASS);
-    break;
-    case STEP_AP://AP Only
+      break;
+    case STEP_AP:  //AP Only
       Serial.println("** Stopping STA");
       WiFi.mode(WIFI_AP);
       Serial.println("** Starting AP");
       WiFi.softAP(AP_SSID);
-    break;
-    case STEP_AP_STA://AP+STA
+      break;
+    case STEP_AP_STA:  //AP+STA
       Serial.println("** Starting STA");
       WiFi.begin(STA_SSID, STA_PASS);
-    break;
-    case STEP_OFF://All Off
+      break;
+    case STEP_OFF:  //All Off
       Serial.println("** Stopping WiFi");
       WiFi.mode(WIFI_OFF);
-    break;
-    case STEP_BT_STA://BT+STA
+      break;
+    case STEP_BT_STA:  //BT+STA
       Serial.println("** Starting STA+BT");
       WiFi.begin(STA_SSID, STA_PASS);
       btStart();
-    break;
-    case STEP_END://All Off
+      break;
+    case STEP_END:  //All Off
       Serial.println("** Stopping WiFi+BT");
       WiFi.mode(WIFI_OFF);
       btStop();
-    break;
-    default:
-    break;
+      break;
+    default: break;
   }
-  if(step == STEP_END){
+  if (step == STEP_END) {
     step = STEP_BTON;
   } else {
     step++;
@@ -73,56 +81,48 @@ void onButton(){
   delay(100);
 }
 
-void WiFiEvent(WiFiEvent_t event){
-    switch(event) {
-        case SYSTEM_EVENT_AP_START:
-            Serial.println("AP Started");
-            WiFi.softAPsetHostname(AP_SSID);
-            break;
-        case SYSTEM_EVENT_AP_STOP:
-            Serial.println("AP Stopped");
-            break;
-        case SYSTEM_EVENT_STA_START:
-            Serial.println("STA Started");
-            WiFi.setHostname(AP_SSID);
-            break;
-        case SYSTEM_EVENT_STA_CONNECTED:
-            Serial.println("STA Connected");
-            WiFi.enableIpV6();
-            break;
-        case SYSTEM_EVENT_AP_STA_GOT_IP6:
-            Serial.print("STA IPv6: ");
-            Serial.println(WiFi.localIPv6());
-            break;
-        case SYSTEM_EVENT_STA_GOT_IP:
-            Serial.print("STA IPv4: ");
-            Serial.println(WiFi.localIP());
-            break;
-        case SYSTEM_EVENT_STA_DISCONNECTED:
-            Serial.println("STA Disconnected");
-            break;
-        case SYSTEM_EVENT_STA_STOP:
-            Serial.println("STA Stopped");
-            break;
-        default:
-            break;
-    }
+// WARNING: WiFiEvent is called from a separate FreeRTOS task (thread)!
+void WiFiEvent(WiFiEvent_t event) {
+  switch (event) {
+    case ARDUINO_EVENT_WIFI_AP_START:
+      Serial.println("AP Started");
+      WiFi.softAPsetHostname(AP_SSID);
+      break;
+    case ARDUINO_EVENT_WIFI_AP_STOP: Serial.println("AP Stopped"); break;
+    case ARDUINO_EVENT_WIFI_STA_START:
+      Serial.println("STA Started");
+      WiFi.setHostname(AP_SSID);
+      break;
+    case ARDUINO_EVENT_WIFI_STA_CONNECTED: Serial.println("STA Connected"); break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP6:
+      Serial.print("STA IPv6: ");
+      Serial.println(WiFi.linkLocalIPv6());
+      break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP:
+      Serial.print("STA IPv4: ");
+      Serial.println(WiFi.localIP());
+      break;
+    case ARDUINO_EVENT_WIFI_STA_DISCONNECTED: Serial.println("STA Disconnected"); break;
+    case ARDUINO_EVENT_WIFI_STA_STOP:         Serial.println("STA Stopped"); break;
+    default:                                  break;
+  }
 }
 
 void setup() {
-    Serial.begin(115200);
-    pinMode(0, INPUT_PULLUP);
-    WiFi.onEvent(WiFiEvent);
-    Serial.print("ESP32 SDK: ");
-    Serial.println(ESP.getSdkVersion());
-    Serial.println("Press the button to select the next mode");
+  Serial.begin(115200);
+  pinMode(0, INPUT_PULLUP);
+  WiFi.onEvent(WiFiEvent);  // Will call WiFiEvent() from another thread.
+  WiFi.enableIPv6();
+  Serial.print("ESP32 SDK: ");
+  Serial.println(ESP.getSdkVersion());
+  Serial.println("Press the button to select the next mode");
 }
 
 void loop() {
-    static uint8_t lastPinState = 1;
-    uint8_t pinState = digitalRead(0);
-    if(!pinState && lastPinState){
-        onButton();
-    }
-    lastPinState = pinState;
+  static uint8_t lastPinState = 1;
+  uint8_t pinState = digitalRead(0);
+  if (!pinState && lastPinState) {
+    onButton();
+  }
+  lastPinState = pinState;
 }
diff --git a/libraries/WiFi/examples/WiFiBlueToothSwitch/ci.json b/libraries/WiFi/examples/WiFiBlueToothSwitch/ci.json
new file mode 100644
index 00000000000..f27dd13c83e
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiBlueToothSwitch/ci.json
@@ -0,0 +1,9 @@
+{
+  "requires": [
+    "CONFIG_BT_ENABLED=y"
+  ],
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiClient/README.md b/libraries/WiFi/examples/WiFiClient/README.md
new file mode 100644
index 00000000000..9d3698a543a
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiClient/README.md
@@ -0,0 +1,161 @@
+# NetworkClient
+
+This example demonstrates reading and writing data from and to a web service which can be used for logging data, creating insights and taking actions based on those data.
+
+# Supported Targets
+
+Currently, this example supports all SoC with Wi-Fi.
+
+
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 |
+
+
+## How to Use Example
+
+Flash this example and observe the serial output. You can also take a look at the values at [https://thingspeak.com/channels/2005329](https://thingspeak.com/channels/2005329)
+
+Please note that this public channel can be accessed by anyone and it is possible that more people will write their values.
+
+### Configure the Project
+
+Change `SSID` and `password` to connect to your Wi-Fi.
+Default values will allow you to use this example without any changes. If you want to use your own channel and you don't have one already follow these steps:
+
+* Create an account on [thingspeak.com](https://www.thingspeak.com).
+* After logging in, click on the "New Channel" button to create a new channel for your data. This is where your data will be stored and displayed.
+* Fill in the Name, Description, and other fields for your channel as desired, then click the "Save Channel" button.
+* Take note of the "Write API Key" located in the "API keys" tab, this is the key you will use to send data to your channel.
+* Replace the channelID from tab "Channel Settings" and privateKey with "Read API Keys" from "API Keys" tab.
+* Replace the host variable with the thingspeak server hostname "api.thingspeak.com"
+* Upload the sketch to your ESP32 board and make sure that the board is connected to the internet. The ESP32 should now send data to your Thingspeak channel at the intervals specified by the loop function.
+* Go to the channel view page on thingspeak and check the "Field1" for the new incoming data.
+* You can use the data visualization and analysis tools provided by Thingspeak to display and process your data in various ways.
+* Please note, that Thingspeak accepts only integer values.
+
+#### Config example:
+
+You can find the data to be changed at the top of the file:
+
+```cpp
+const char* ssid     = "your-ssid"; // Change this to your WiFi SSID
+const char* password = "your-password"; // Change this to your WiFi password
+
+const char* host = "api.thingspeak.com"; // This should not be changed
+const int httpPort = 80; // This should not be changed
+const String channelID   = "2005329"; // Change this to your channel ID
+const String writeApiKey = "V6YOTILH9I7D51F9"; // Change this to your Write API key
+const String readApiKey = "34W6LGLIFXD56MPM"; // Change this to your Read API key
+
+// The default example accepts one data filed named "field1"
+// For your own server you can ofcourse create more of them.
+int field1 = 0;
+
+int numberOfResults = 3; // Number of results to be read
+int fieldNumber = 1; // Field number which will be read out
+```
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example Log Output
+
+The initial output which is common for all examples can be ignored:
+```
+SP-ROM:esp32c3-api1-20210207
+Build:Feb  7 2021
+rst:0x1 (POWERON),boot:0xc (SPI_FAST_FLASH_BOOT)
+SPIWP:0xee
+mode:DIO, clock div:1
+load:0x3fcd5810,len:0x438
+load:0x403cc710,len:0x918
+load:0x403ce710,len:0x24e4
+entry 0x403cc710
+```
+Follows the setup output where connection to your Wi-Fi happens:
+```
+******************************************************
+Connecting to your-ssid
+.
+WiFi connected
+IP address:
+192.168.1.2
+```
+Then you can see the write log:
+```
+HTTP/1.1 200 OK
+Date: Fri, 13 Jan 2023 13:12:31 GMT
+Content-Type: text/plain; charset=utf-8
+Content-Length: 1
+Connection: close
+Status: 200 OK
+Cache-Control: max-age=0, private, must-revalidate
+Access-Control-Allow-Origin: *
+Access-Control-Max-Age: 1800
+X-Request-Id: 188e3464-f155-44b0-96f6-0f3614170bb0
+Access-Control-Allow-Headers: origin, content-type, X-Requested-With
+Access-Control-Allow-Methods: GET, POST, PUT, OPTIONS, DELETE, PATCH
+ETag: W/"5feceb66ffc86f38d952786c6d696c79"
+X-Frame-Options: SAMEORIGIN
+
+0
+Closing connection
+```
+Last portion is the read log:
+```
+HTTP/1.1 200 OK
+Date: Fri, 13 Jan 2023 13:12:32 GMT
+Content-Type: application/json; charset=utf-8
+Transfer-Encoding: chunked
+Connection: close
+Status: 200 OK
+Cache-Control: max-age=7, private
+Access-Control-Allow-Origin: *
+Access-Control-Max-Age: 1800
+X-Request-Id: 91b97016-7625-44f6-9797-1b2973aa57b7
+Access-Control-Allow-Headers: origin, content-type, X-Requested-With
+Access-Control-Allow-Methods: GET, POST, PUT, OPTIONS, DELETE, PATCH
+ETag: W/"8e9c308fe2c50309f991586be1aff28d"
+X-Frame-Options: SAMEORIGIN
+
+1e3
+{"channel":{"id":2005329,"name":"WiFiCLient example","description":"Default setup for Arduino ESP32 NetworkClient example","latitude":"0.0","longitude":"0.0","field1":"data0","created_at":"2023-01-11T15:56:08Z","updated_at":"2023-01-13T08:13:58Z","last_entry_id":2871},"feeds":[{"created_at":"2023-01-13T13:11:30Z","entry_id":2869,"field1":"359"},{"created_at":"2023-01-13T13:11:57Z","entry_id":2870,"field1":"361"},{"created_at":"2023-01-13T13:12:23Z","entry_id":2871,"field1":"363"}]}
+0
+
+
+Closing connection
+```
+After this the write+read log repeat every 10 seconds.
+
+
+## Troubleshooting
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **Wi-Fi not connected:** Check the SSID and password and also that the signal has sufficient strength.
+* **400 Bad Request:** Check the writeApiKey.
+* **404 Not Found:** Check the channel ID.
+* **No data on chart / reading NULL:** Data must be sent as an integer, without commas.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* ESP32-S3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/WiFi/examples/WiFiClient/WiFiClient.ino b/libraries/WiFi/examples/WiFiClient/WiFiClient.ino
index 7dd9c8d0d35..b4c88244c26 100644
--- a/libraries/WiFi/examples/WiFiClient/WiFiClient.ino
+++ b/libraries/WiFi/examples/WiFiClient/WiFiClient.ino
@@ -1,94 +1,105 @@
 /*
- *  This sketch sends data via HTTP GET requests to data.sparkfun.com service.
- *
- *  You need to get streamId and privateKey at data.sparkfun.com and paste them
- *  below. Or just customize this script to talk to other HTTP servers.
- *
+    Go to thingspeak.com and create an account if you don't have one already.
+    After logging in, click on the "New Channel" button to create a new channel for your data. This is where your data will be stored and displayed.
+    Fill in the Name, Description, and other fields for your channel as desired, then click the "Save Channel" button.
+    Take note of the "Write API Key" located in the "API keys" tab, this is the key you will use to send data to your channel.
+    Replace the channelID from tab "Channel Settings" and privateKey with "Read API Keys" from "API Keys" tab.
+    Replace the host variable with the thingspeak server hostname "api.thingspeak.com"
+    Upload the sketch to your ESP32 board and make sure that the board is connected to the internet. The ESP32 should now send data to your Thingspeak channel at the intervals specified by the loop function.
+    Go to the channel view page on thingspeak and check the "Field1" for the new incoming data.
+    You can use the data visualization and analysis tools provided by Thingspeak to display and process your data in various ways.
+    Please note, that Thingspeak accepts only integer values.
+
+    You can later check the values at https://thingspeak.com/channels/2005329
+    Please note that this public channel can be accessed by anyone and it is possible that more people will write their values.
  */
 
 #include <WiFi.h>
 
-const char* ssid     = "your-ssid";
-const char* password = "your-password";
+const char *ssid = "your-ssid";          // Change this to your WiFi SSID
+const char *password = "your-password";  // Change this to your WiFi password
 
-const char* host = "data.sparkfun.com";
-const char* streamId   = "....................";
-const char* privateKey = "....................";
+const char *host = "api.thingspeak.com";        // This should not be changed
+const int httpPort = 80;                        // This should not be changed
+const String channelID = "2005329";             // Change this to your channel ID
+const String writeApiKey = "V6YOTILH9I7D51F9";  // Change this to your Write API key
+const String readApiKey = "34W6LGLIFXD56MPM";   // Change this to your Read API key
 
-void setup()
-{
-    Serial.begin(115200);
-    delay(10);
+// The default example accepts one data filed named "field1"
+// For your own server you can ofcourse create more of them.
+int field1 = 0;
 
-    // We start by connecting to a WiFi network
+int numberOfResults = 3;  // Number of results to be read
+int fieldNumber = 1;      // Field number which will be read out
 
-    Serial.println();
-    Serial.println();
-    Serial.print("Connecting to ");
-    Serial.println(ssid);
+void setup() {
+  Serial.begin(115200);
 
-    WiFi.begin(ssid, password);
+  // We start by connecting to a WiFi network
 
-    while (WiFi.status() != WL_CONNECTED) {
-        delay(500);
-        Serial.print(".");
+  Serial.println();
+  Serial.println("******************************************************");
+  Serial.print("Connecting to ");
+  Serial.println(ssid);
+
+  WiFi.begin(ssid, password);
+
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+
+  Serial.println("");
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
+}
+
+void readResponse(NetworkClient *client) {
+  unsigned long timeout = millis();
+  while (client->available() == 0) {
+    if (millis() - timeout > 5000) {
+      Serial.println(">>> Client Timeout !");
+      client->stop();
+      return;
     }
+  }
+
+  // Read all the lines of the reply from server and print them to Serial
+  while (client->available()) {
+    String line = client->readStringUntil('\r');
+    Serial.print(line);
+  }
 
-    Serial.println("");
-    Serial.println("WiFi connected");
-    Serial.println("IP address: ");
-    Serial.println(WiFi.localIP());
+  Serial.printf("\nClosing connection\n\n");
 }
 
-int value = 0;
+void loop() {
+  NetworkClient client;
+  String footer = String(" HTTP/1.1\r\n") + "Host: " + String(host) + "\r\n" + "Connection: close\r\n\r\n";
 
-void loop()
-{
-    delay(5000);
-    ++value;
+  // WRITE --------------------------------------------------------------------------------------------
+  if (!client.connect(host, httpPort)) {
+    return;
+  }
 
-    Serial.print("connecting to ");
-    Serial.println(host);
+  client.print("GET /update?api_key=" + writeApiKey + "&field1=" + field1 + footer);
+  readResponse(&client);
 
-    // Use WiFiClient class to create TCP connections
-    WiFiClient client;
-    const int httpPort = 80;
-    if (!client.connect(host, httpPort)) {
-        Serial.println("connection failed");
-        return;
-    }
+  // READ --------------------------------------------------------------------------------------------
 
-    // We now create a URI for the request
-    String url = "/input/";
-    url += streamId;
-    url += "?private_key=";
-    url += privateKey;
-    url += "&value=";
-    url += value;
-
-    Serial.print("Requesting URL: ");
-    Serial.println(url);
-
-    // This will send the request to the server
-    client.print(String("GET ") + url + " HTTP/1.1\r\n" +
-                 "Host: " + host + "\r\n" +
-                 "Connection: close\r\n\r\n");
-    unsigned long timeout = millis();
-    while (client.available() == 0) {
-        if (millis() - timeout > 5000) {
-            Serial.println(">>> Client Timeout !");
-            client.stop();
-            return;
-        }
-    }
+  String readRequest = "GET /channels/" + channelID + "/fields/" + fieldNumber + ".json?results=" + numberOfResults + " HTTP/1.1\r\n" + "Host: " + host + "\r\n"
+                       + "Connection: close\r\n\r\n";
 
-    // Read all the lines of the reply from server and print them to Serial
-    while(client.available()) {
-        String line = client.readStringUntil('\r');
-        Serial.print(line);
-    }
+  if (!client.connect(host, httpPort)) {
+    return;
+  }
 
-    Serial.println();
-    Serial.println("closing connection");
-}
+  client.print(readRequest);
+  readResponse(&client);
+
+  // -------------------------------------------------------------------------------------------------
 
+  ++field1;
+  delay(10000);
+}
diff --git a/libraries/WiFi/examples/WiFiClient/ci.json b/libraries/WiFi/examples/WiFiClient/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiClient/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino b/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino
index ecfed5e1957..3cbfb4a652a 100644
--- a/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino
+++ b/libraries/WiFi/examples/WiFiClientBasic/WiFiClientBasic.ino
@@ -8,80 +8,73 @@
 
 WiFiMulti WiFiMulti;
 
-void setup()
-{
-    Serial.begin(115200);
-    delay(10);
+void setup() {
+  Serial.begin(115200);
+  delay(10);
 
-    // We start by connecting to a WiFi network
-    WiFiMulti.addAP("SSID", "passpasspass");
+  // We start by connecting to a WiFi network
+  WiFiMulti.addAP("SSID", "passpasspass");
 
-    Serial.println();
-    Serial.println();
-    Serial.print("Waiting for WiFi... ");
+  Serial.println();
+  Serial.println();
+  Serial.print("Waiting for WiFi... ");
 
-    while(WiFiMulti.run() != WL_CONNECTED) {
-        Serial.print(".");
-        delay(500);
-    }
+  while (WiFiMulti.run() != WL_CONNECTED) {
+    Serial.print(".");
+    delay(500);
+  }
 
-    Serial.println("");
-    Serial.println("WiFi connected");
-    Serial.println("IP address: ");
-    Serial.println(WiFi.localIP());
+  Serial.println("");
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(WiFi.localIP());
 
-    delay(500);
+  delay(500);
 }
 
+void loop() {
+  //    const uint16_t port = 80;
+  //    const char * host = "192.168.1.1"; // ip or dns
+  const uint16_t port = 1337;
+  const char *host = "192.168.1.10";  // ip or dns
 
-void loop()
-{
-//    const uint16_t port = 80;
-//    const char * host = "192.168.1.1"; // ip or dns
-    const uint16_t port = 1337;
-    const char * host = "192.168.1.10"; // ip or dns
-
-    Serial.print("Connecting to ");
-    Serial.println(host);
+  Serial.print("Connecting to ");
+  Serial.println(host);
 
-    // Use WiFiClient class to create TCP connections
-    WiFiClient client;
+  // Use NetworkClient class to create TCP connections
+  NetworkClient client;
 
-    if (!client.connect(host, port)) {
-        Serial.println("Connection failed.");
-        Serial.println("Waiting 5 seconds before retrying...");
-        delay(5000);
-        return;
-    }
+  if (!client.connect(host, port)) {
+    Serial.println("Connection failed.");
+    Serial.println("Waiting 5 seconds before retrying...");
+    delay(5000);
+    return;
+  }
 
-    // This will send a request to the server
-    //uncomment this line to send an arbitrary string to the server
-    //client.print("Send this data to the server");
-    //uncomment this line to send a basic document request to the server
-    client.print("GET /index.html HTTP/1.1\n\n");
+  // This will send a request to the server
+  //uncomment this line to send an arbitrary string to the server
+  //client.print("Send this data to the server");
+  //uncomment this line to send a basic document request to the server
+  client.print("GET /index.html HTTP/1.1\n\n");
 
   int maxloops = 0;
 
   //wait for the server's reply to become available
-  while (!client.available() && maxloops < 1000)
-  {
+  while (!client.available() && maxloops < 1000) {
     maxloops++;
-    delay(1); //delay 1 msec
+    delay(1);  //delay 1 msec
   }
-  if (client.available() > 0)
-  {
+  if (client.available() > 0) {
     //read back one line from the server
     String line = client.readStringUntil('\r');
     Serial.println(line);
-  }
-  else
-  {
+  } else {
     Serial.println("client.available() timed out ");
   }
 
-    Serial.println("Closing connection.");
-    client.stop();
+  Serial.println("Closing connection.");
+  client.stop();
 
-    Serial.println("Waiting 5 seconds before restarting...");
-    delay(5000);
+  Serial.println("Waiting 5 seconds before restarting...");
+  delay(5000);
 }
diff --git a/libraries/WiFi/examples/WiFiClientBasic/ci.json b/libraries/WiFi/examples/WiFiClientBasic/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiClientBasic/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiClientConnect/README.md b/libraries/WiFi/examples/WiFiClientConnect/README.md
new file mode 100644
index 00000000000..939d44c5b76
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiClientConnect/README.md
@@ -0,0 +1,71 @@
+# NetworkClientConnect Example
+
+This example demonstrates how to connect to the Wi-Fi and manage the status and disconnection from STA.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 |
+| ----------------- | ----- | -------- | -------- |
+
+## How to Use Example
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+#### Using Arduino IDE
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example/Log Output
+
+```
+[WiFi] Connecting to MyWiFiNetwork
+[    66][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 0 - WIFI_READY
+[   150][V][WiFiGeneric.cpp:338] _arduino_event_cb(): STA Started
+[   151][V][WiFiGeneric.cpp:97] set_esp_interface_ip(): Configuring Station static IP: 0.0.0.0, MASK: 0.0.0.0, GW: 0.0.0.0
+[   151][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 2 - STA_START
+[WiFi] WiFi is disconnected
+[   234][V][WiFiGeneric.cpp:353] _arduino_event_cb(): STA Connected: SSID: MyWiFiNetwork, BSSID: xx:xx:xx:xx:xx:xx, Channel: 8, Auth: WPA2_PSK
+[   235][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 4 - STA_CONNECTED
+[   560][V][WiFiGeneric.cpp:367] _arduino_event_cb(): STA Got New IP:192.168.68.114
+[   561][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 7 - STA_GOT_IP
+[   564][D][WiFiGeneric.cpp:1004] _eventCallback(): STA IP: 192.168.68.114, MASK: 255.255.255.0, GW: 192.168.68.1
+[WiFi] WiFi is connected!
+[WiFi] IP address: 192.168.68.114
+[WiFi] Disconnecting from WiFi!
+[  2633][V][WiFiGeneric.cpp:360] _arduino_event_cb(): STA Disconnected: SSID: MyWiFiNetwork, BSSID: xx:xx:xx:xx:xx:xx, Reason: 8
+[  2634][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 5 - STA_DISCONNECTED
+[  2635][V][WiFiGeneric.cpp:341] _arduino_event_cb(): STA Stopped
+[  2641][W][WiFiGeneric.cpp:953] _eventCallback(): Reason: 8 - ASSOC_LEAVE
+[  2654][D][WiFiGeneric.cpp:975] _eventCallback(): WiFi the station is disconnected
+[  2661][D][WiFiGeneric.cpp:929] _eventCallback(): Arduino Event: 3 - STA_STOP
+[WiFi] Disconnected from WiFi!
+...
+```
+
+## Troubleshooting
+
+***Important: Be sure you're using a good quality USB cable that has enough power for your project.***
+
+* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed.
+* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/WiFi/examples/WiFiClientConnect/WiFiClientConnect.ino b/libraries/WiFi/examples/WiFiClientConnect/WiFiClientConnect.ino
new file mode 100644
index 00000000000..b2fdec604a1
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiClientConnect/WiFiClientConnect.ino
@@ -0,0 +1,90 @@
+/* Wi-Fi STA Connect and Disconnect Example
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+
+*/
+#include <WiFi.h>
+
+const char *ssid = "your-ssid";
+const char *password = "your-password";
+
+int btnGPIO = 0;
+int btnState = false;
+
+void setup() {
+  Serial.begin(115200);
+  delay(10);
+
+  // Set GPIO0 Boot button as input
+  pinMode(btnGPIO, INPUT);
+
+  // We start by connecting to a WiFi network
+  // To debug, please enable Core Debug Level to Verbose
+
+  Serial.println();
+  Serial.print("[WiFi] Connecting to ");
+  Serial.println(ssid);
+
+  WiFi.begin(ssid, password);
+  // Auto reconnect is set true as default
+  // To set auto connect off, use the following function
+  //    WiFi.setAutoReconnect(false);
+
+  // Will try for about 10 seconds (20x 500ms)
+  int tryDelay = 500;
+  int numberOfTries = 20;
+
+  // Wait for the WiFi event
+  while (true) {
+
+    switch (WiFi.status()) {
+      case WL_NO_SSID_AVAIL: Serial.println("[WiFi] SSID not found"); break;
+      case WL_CONNECT_FAILED:
+        Serial.print("[WiFi] Failed - WiFi not connected! Reason: ");
+        return;
+        break;
+      case WL_CONNECTION_LOST: Serial.println("[WiFi] Connection was lost"); break;
+      case WL_SCAN_COMPLETED:  Serial.println("[WiFi] Scan is completed"); break;
+      case WL_DISCONNECTED:    Serial.println("[WiFi] WiFi is disconnected"); break;
+      case WL_CONNECTED:
+        Serial.println("[WiFi] WiFi is connected!");
+        Serial.print("[WiFi] IP address: ");
+        Serial.println(WiFi.localIP());
+        return;
+        break;
+      default:
+        Serial.print("[WiFi] WiFi Status: ");
+        Serial.println(WiFi.status());
+        break;
+    }
+    delay(tryDelay);
+
+    if (numberOfTries <= 0) {
+      Serial.print("[WiFi] Failed to connect to WiFi!");
+      // Use disconnect function to force stop trying to connect
+      WiFi.disconnect();
+      return;
+    } else {
+      numberOfTries--;
+    }
+  }
+}
+
+void loop() {
+  // Read the button state
+  btnState = digitalRead(btnGPIO);
+
+  if (btnState == LOW) {
+    // Disconnect from WiFi
+    Serial.println("[WiFi] Disconnecting from WiFi!");
+    // This function will disconnect and turn off the WiFi (NVS WiFi data is kept)
+    if (WiFi.disconnect(true, false)) {
+      Serial.println("[WiFi] Disconnected from WiFi!");
+    }
+    delay(1000);
+  }
+}
diff --git a/libraries/WiFi/examples/WiFiClientConnect/ci.json b/libraries/WiFi/examples/WiFiClientConnect/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiClientConnect/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiClientEnterprise/README.md b/libraries/WiFi/examples/WiFiClientEnterprise/README.md
index 8160ddabccc..20d38b88d34 100644
--- a/libraries/WiFi/examples/WiFiClientEnterprise/README.md
+++ b/libraries/WiFi/examples/WiFiClientEnterprise/README.md
@@ -1,5 +1,5 @@
 # ESP32-Eduroam
-* Eduroam wifi connection with university login identity
+* Eduroam Wi-Fi connection with university login identity
 * Working under Eduroam networks worldwide
 * Methods: PEAP + MsCHAPv2
 
@@ -11,10 +11,11 @@
 * Change IDENTITY
 * Change password
 * Upload sketch and enjoy!
-* After sucessful assign of IP address, board will connect to HTTP page on internet to verify your authentification
+* After successful assign of IP address, board will connect to HTTP page on internet to verify your authentication
 * Board will auto reconnect to Eduroam if it lost connection
 
 # Tested locations
+<!-- vale off -->
 |University|Board|Method|Result|
 |-------------|-------------| -----|------|
 |Technical University in Košice (Slovakia)|ESP32 Devkit v1|PEAP + MsCHAPv2|Working|
@@ -29,15 +30,16 @@
 |Universidade Federal de Santa Catarina (Brazil)|xxx|EAP-TTLS + MsCHAPv2|Working|
 |University of Central Florida (Orlando, Florida)|ESP32 Built-in OLED – Heltec WiFi Kit 32|PEAP + MsCHAPv2|Working|
 |Université de Montpellier (France)|NodeMCU-32S|PEAP + MsCHAPv2|Working|
+<!-- vale on -->
 
 # Common errors - Switch to Debug mode for Serial monitor prints
 |Error|Appearance|Solution|
 |-------------|-------------|-------------|
-|wifi: Set status to INIT|Frequent|Hold EN button for few seconds|
-|HANDSHAKE_TIMEOUT|Rare|Bug was found under Zeroshell RADIUS authentization - Unsucessful connection|
-|AUTH_EXPIRE|Common|In the case of weak wifi network signal, this error is quite common, bring your device closer to AP|
+|Wi-Fi: Set status to INIT|Frequent|Hold EN button for few seconds|
+|HANDSHAKE_TIMEOUT|Rare|Bug was found under Zeroshell RADIUS authentization - Unsuccessful connection|
+|AUTH_EXPIRE|Common|In the case of weak Wi-Fi network signal, this error is quite common, bring your device closer to AP|
 |ASSOC_EXPIRE|Rare|-|
-# Sucessful connection example
+# Successful connection example
  ![alt text](https://i.nahraj.to/f/24Kc.png)
-# Unsucessful connection example
+# Unsuccessful connection example
  ![alt text](https://camo.githubusercontent.com/87e47d1b27f4e8ace87423e40e8edbce7983bafa/68747470733a2f2f692e6e616872616a2e746f2f662f323435572e504e47)
diff --git a/libraries/WiFi/examples/WiFiClientEnterprise/WiFiClientEnterprise.ino b/libraries/WiFi/examples/WiFiClientEnterprise/WiFiClientEnterprise.ino
index 0c861cddcf0..198f97e2805 100644
--- a/libraries/WiFi/examples/WiFiClientEnterprise/WiFiClientEnterprise.ino
+++ b/libraries/WiFi/examples/WiFiClientEnterprise/WiFiClientEnterprise.ino
@@ -1,10 +1,26 @@
-#include <WiFi.h> //Wifi library
-#include "esp_wpa2.h" //wpa2 library for connections to Enterprise networks
-#define EAP_IDENTITY "login" //if connecting from another corporation, use identity@organisation.domain in Eduroam 
-#define EAP_PASSWORD "password" //your Eduroam password
-const char* ssid = "eduroam"; // Eduroam SSID
-const char* host = "arduino.php5.sk"; //external server domain for HTTP connection after authentification
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#error "WPA-Enterprise is only supported in SoCs with native Wi-Fi support"
+#endif
+
+#include <WiFi.h>                      //Wifi library
+#define EAP_IDENTITY "login"           //if connecting from another corporation, use identity@organization.domain in Eduroam
+#define EAP_USERNAME "login"           //oftentimes just a repeat of the identity
+#define EAP_PASSWORD "password"        //your Eduroam password
+const char *ssid = "eduroam";          // Eduroam SSID
+const char *host = "arduino.php5.sk";  //external server domain for HTTP connection after authentication
 int counter = 0;
+
+// NOTE: For some systems, various certification keys are required to connect to the wifi system.
+//       Usually you are provided these by the IT department of your organization when certs are required
+//       and you can't connect with just an identity and password.
+//       Most eduroam setups we have seen do not require this level of authentication, but you should contact
+//       your IT department to verify.
+//       You should uncomment these and populate with the contents of the files if this is required for your scenario (See Example 2 and Example 3 below).
+//const char *ca_pem = "insert your CA cert from your .pem file here";
+//const char *client_cert = "insert your client cert from your .crt file here";
+//const char *client_key = "insert your client key from your .key file here";
+
 void setup() {
   Serial.begin(115200);
   delay(10);
@@ -12,45 +28,49 @@ void setup() {
   Serial.print("Connecting to network: ");
   Serial.println(ssid);
   WiFi.disconnect(true);  //disconnect form wifi to set new wifi connection
-  WiFi.mode(WIFI_STA); //init wifi mode
-  esp_wifi_sta_wpa2_ent_set_identity((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY)); //provide identity
-  esp_wifi_sta_wpa2_ent_set_username((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY)); //provide username --> identity and username is same
-  esp_wifi_sta_wpa2_ent_set_password((uint8_t *)EAP_PASSWORD, strlen(EAP_PASSWORD)); //provide password
-  esp_wpa2_config_t config = WPA2_CONFIG_INIT_DEFAULT(); //set config settings to default
-  esp_wifi_sta_wpa2_ent_enable(&config); //set config settings to enable function
-  WiFi.begin(ssid); //connect to wifi
+  WiFi.mode(WIFI_STA);    //init wifi mode
+
+  // Example1 (most common): a cert-file-free eduroam with PEAP (or TTLS)
+  WiFi.begin(ssid, WPA2_AUTH_PEAP, EAP_IDENTITY, EAP_USERNAME, EAP_PASSWORD);
+
+  // Example 2: a cert-file WPA2 Enterprise with PEAP
+  //WiFi.begin(ssid, WPA2_AUTH_PEAP, EAP_IDENTITY, EAP_USERNAME, EAP_PASSWORD, ca_pem, client_cert, client_key);
+
+  // Example 3: TLS with cert-files and no password
+  //WiFi.begin(ssid, WPA2_AUTH_TLS, EAP_IDENTITY, NULL, NULL, ca_pem, client_cert, client_key);
+
   while (WiFi.status() != WL_CONNECTED) {
     delay(500);
     Serial.print(".");
     counter++;
-    if(counter>=60){ //after 30 seconds timeout - reset board
+    if (counter >= 60) {  //after 30 seconds timeout - reset board
       ESP.restart();
     }
   }
   Serial.println("");
   Serial.println("WiFi connected");
-  Serial.println("IP address set: "); 
-  Serial.println(WiFi.localIP()); //print LAN IP
+  Serial.println("IP address set: ");
+  Serial.println(WiFi.localIP());  //print LAN IP
 }
 void loop() {
-  if (WiFi.status() == WL_CONNECTED) { //if we are connected to Eduroam network
-    counter = 0; //reset counter
-    Serial.println("Wifi is still connected with IP: "); 
-    Serial.println(WiFi.localIP());   //inform user about his IP address
-  }else if (WiFi.status() != WL_CONNECTED) { //if we lost connection, retry
-    WiFi.begin(ssid);      
+  if (WiFi.status() == WL_CONNECTED) {  //if we are connected to Eduroam network
+    counter = 0;                        //reset counter
+    Serial.println("Wifi is still connected with IP: ");
+    Serial.println(WiFi.localIP());            //inform user about his IP address
+  } else if (WiFi.status() != WL_CONNECTED) {  //if we lost connection, retry
+    WiFi.begin(ssid);
   }
-  while (WiFi.status() != WL_CONNECTED) { //during lost connection, print dots
+  while (WiFi.status() != WL_CONNECTED) {  //during lost connection, print dots
     delay(500);
     Serial.print(".");
     counter++;
-    if(counter>=60){ //30 seconds timeout - reset board
-    ESP.restart();
+    if (counter >= 60) {  //30 seconds timeout - reset board
+      ESP.restart();
     }
   }
   Serial.print("Connecting to website: ");
   Serial.println(host);
-  WiFiClient client;
+  NetworkClient client;
   if (client.connect(host, 80)) {
     String url = "/rele/rele1.txt";
     client.print(String("GET ") + url + " HTTP/1.1\r\n" + "Host: " + host + "\r\n" + "User-Agent: ESP32\r\n" + "Connection: close\r\n\r\n");
@@ -62,8 +82,8 @@ void loop() {
       }
     }
     String line = client.readStringUntil('\n');
-   Serial.println(line);
-  }else{
-      Serial.println("Connection unsucessful");
-    }  
+    Serial.println(line);
+  } else {
+    Serial.println("Connection unsuccessful");
+  }
 }
diff --git a/libraries/WiFi/examples/WiFiClientEnterprise/ci.json b/libraries/WiFi/examples/WiFiClientEnterprise/ci.json
new file mode 100644
index 00000000000..36babb82730
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiClientEnterprise/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino b/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino
index a7b029481e5..41b2fd0177b 100644
--- a/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino
+++ b/libraries/WiFi/examples/WiFiClientEvents/WiFiClientEvents.ino
@@ -6,161 +6,119 @@
 /*
 * WiFi Events
 
-0  SYSTEM_EVENT_WIFI_READY               < ESP32 WiFi ready
-1  SYSTEM_EVENT_SCAN_DONE                < ESP32 finish scanning AP
-2  SYSTEM_EVENT_STA_START                < ESP32 station start
-3  SYSTEM_EVENT_STA_STOP                 < ESP32 station stop
-4  SYSTEM_EVENT_STA_CONNECTED            < ESP32 station connected to AP
-5  SYSTEM_EVENT_STA_DISCONNECTED         < ESP32 station disconnected from AP
-6  SYSTEM_EVENT_STA_AUTHMODE_CHANGE      < the auth mode of AP connected by ESP32 station changed
-7  SYSTEM_EVENT_STA_GOT_IP               < ESP32 station got IP from connected AP
-8  SYSTEM_EVENT_STA_LOST_IP              < ESP32 station lost IP and the IP is reset to 0
-9  SYSTEM_EVENT_STA_WPS_ER_SUCCESS       < ESP32 station wps succeeds in enrollee mode
-10 SYSTEM_EVENT_STA_WPS_ER_FAILED        < ESP32 station wps fails in enrollee mode
-11 SYSTEM_EVENT_STA_WPS_ER_TIMEOUT       < ESP32 station wps timeout in enrollee mode
-12 SYSTEM_EVENT_STA_WPS_ER_PIN           < ESP32 station wps pin code in enrollee mode
-13 SYSTEM_EVENT_AP_START                 < ESP32 soft-AP start
-14 SYSTEM_EVENT_AP_STOP                  < ESP32 soft-AP stop
-15 SYSTEM_EVENT_AP_STACONNECTED          < a station connected to ESP32 soft-AP
-16 SYSTEM_EVENT_AP_STADISCONNECTED       < a station disconnected from ESP32 soft-AP
-17 SYSTEM_EVENT_AP_STAIPASSIGNED         < ESP32 soft-AP assign an IP to a connected station
-18 SYSTEM_EVENT_AP_PROBEREQRECVED        < Receive probe request packet in soft-AP interface
-19 SYSTEM_EVENT_GOT_IP6                  < ESP32 station or ap or ethernet interface v6IP addr is preferred
-20 SYSTEM_EVENT_ETH_START                < ESP32 ethernet start
-21 SYSTEM_EVENT_ETH_STOP                 < ESP32 ethernet stop
-22 SYSTEM_EVENT_ETH_CONNECTED            < ESP32 ethernet phy link up
-23 SYSTEM_EVENT_ETH_DISCONNECTED         < ESP32 ethernet phy link down
-24 SYSTEM_EVENT_ETH_GOT_IP               < ESP32 ethernet got IP from connected AP
-25 SYSTEM_EVENT_MAX
+0  ARDUINO_EVENT_WIFI_READY               < ESP32 WiFi ready
+1  ARDUINO_EVENT_WIFI_SCAN_DONE                < ESP32 finish scanning AP
+2  ARDUINO_EVENT_WIFI_STA_START                < ESP32 station start
+3  ARDUINO_EVENT_WIFI_STA_STOP                 < ESP32 station stop
+4  ARDUINO_EVENT_WIFI_STA_CONNECTED            < ESP32 station connected to AP
+5  ARDUINO_EVENT_WIFI_STA_DISCONNECTED         < ESP32 station disconnected from AP
+6  ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE      < the auth mode of AP connected by ESP32 station changed
+7  ARDUINO_EVENT_WIFI_STA_GOT_IP               < ESP32 station got IP from connected AP
+8  ARDUINO_EVENT_WIFI_STA_LOST_IP              < ESP32 station lost IP and the IP is reset to 0
+9  ARDUINO_EVENT_WPS_ER_SUCCESS       < ESP32 station wps succeeds in enrollee mode
+10 ARDUINO_EVENT_WPS_ER_FAILED        < ESP32 station wps fails in enrollee mode
+11 ARDUINO_EVENT_WPS_ER_TIMEOUT       < ESP32 station wps timeout in enrollee mode
+12 ARDUINO_EVENT_WPS_ER_PIN           < ESP32 station wps pin code in enrollee mode
+13 ARDUINO_EVENT_WIFI_AP_START                 < ESP32 soft-AP start
+14 ARDUINO_EVENT_WIFI_AP_STOP                  < ESP32 soft-AP stop
+15 ARDUINO_EVENT_WIFI_AP_STACONNECTED          < a station connected to ESP32 soft-AP
+16 ARDUINO_EVENT_WIFI_AP_STADISCONNECTED       < a station disconnected from ESP32 soft-AP
+17 ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED         < ESP32 soft-AP assign an IP to a connected station
+18 ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED        < Receive probe request packet in soft-AP interface
+19 ARDUINO_EVENT_WIFI_AP_GOT_IP6               < ESP32 ap interface v6IP addr is preferred
+19 ARDUINO_EVENT_WIFI_STA_GOT_IP6              < ESP32 station interface v6IP addr is preferred
+20 ARDUINO_EVENT_ETH_START                < ESP32 ethernet start
+21 ARDUINO_EVENT_ETH_STOP                 < ESP32 ethernet stop
+22 ARDUINO_EVENT_ETH_CONNECTED            < ESP32 ethernet phy link up
+23 ARDUINO_EVENT_ETH_DISCONNECTED         < ESP32 ethernet phy link down
+24 ARDUINO_EVENT_ETH_GOT_IP               < ESP32 ethernet got IP from connected AP
+19 ARDUINO_EVENT_ETH_GOT_IP6              < ESP32 ethernet interface v6IP addr is preferred
+25 ARDUINO_EVENT_MAX
 */
 
 #include <WiFi.h>
 
-const char* ssid     = "your-ssid";
-const char* password = "your-password";
-
-
-void WiFiEvent(WiFiEvent_t event)
-{
-    Serial.printf("[WiFi-event] event: %d\n", event);
-
-    switch (event) {
-        case SYSTEM_EVENT_WIFI_READY: 
-            Serial.println("WiFi interface ready");
-            break;
-        case SYSTEM_EVENT_SCAN_DONE:
-            Serial.println("Completed scan for access points");
-            break;
-        case SYSTEM_EVENT_STA_START:
-            Serial.println("WiFi client started");
-            break;
-        case SYSTEM_EVENT_STA_STOP:
-            Serial.println("WiFi clients stopped");
-            break;
-        case SYSTEM_EVENT_STA_CONNECTED:
-            Serial.println("Connected to access point");
-            break;
-        case SYSTEM_EVENT_STA_DISCONNECTED:
-            Serial.println("Disconnected from WiFi access point");
-            break;
-        case SYSTEM_EVENT_STA_AUTHMODE_CHANGE:
-            Serial.println("Authentication mode of access point has changed");
-            break;
-        case SYSTEM_EVENT_STA_GOT_IP:
-            Serial.print("Obtained IP address: ");
-            Serial.println(WiFi.localIP());
-            break;
-        case SYSTEM_EVENT_STA_LOST_IP:
-            Serial.println("Lost IP address and IP address is reset to 0");
-            break;
-        case SYSTEM_EVENT_STA_WPS_ER_SUCCESS:
-            Serial.println("WiFi Protected Setup (WPS): succeeded in enrollee mode");
-            break;
-        case SYSTEM_EVENT_STA_WPS_ER_FAILED:
-            Serial.println("WiFi Protected Setup (WPS): failed in enrollee mode");
-            break;
-        case SYSTEM_EVENT_STA_WPS_ER_TIMEOUT:
-            Serial.println("WiFi Protected Setup (WPS): timeout in enrollee mode");
-            break;
-        case SYSTEM_EVENT_STA_WPS_ER_PIN:
-            Serial.println("WiFi Protected Setup (WPS): pin code in enrollee mode");
-            break;
-        case SYSTEM_EVENT_AP_START:
-            Serial.println("WiFi access point started");
-            break;
-        case SYSTEM_EVENT_AP_STOP:
-            Serial.println("WiFi access point  stopped");
-            break;
-        case SYSTEM_EVENT_AP_STACONNECTED:
-            Serial.println("Client connected");
-            break;
-        case SYSTEM_EVENT_AP_STADISCONNECTED:
-            Serial.println("Client disconnected");
-            break;
-        case SYSTEM_EVENT_AP_STAIPASSIGNED:
-            Serial.println("Assigned IP address to client");
-            break;
-        case SYSTEM_EVENT_AP_PROBEREQRECVED:
-            Serial.println("Received probe request");
-            break;
-        case SYSTEM_EVENT_GOT_IP6:
-            Serial.println("IPv6 is preferred");
-            break;
-        case SYSTEM_EVENT_ETH_START:
-            Serial.println("Ethernet started");
-            break;
-        case SYSTEM_EVENT_ETH_STOP:
-            Serial.println("Ethernet stopped");
-            break;
-        case SYSTEM_EVENT_ETH_CONNECTED:
-            Serial.println("Ethernet connected");
-            break;
-        case SYSTEM_EVENT_ETH_DISCONNECTED:
-            Serial.println("Ethernet disconnected");
-            break;
-        case SYSTEM_EVENT_ETH_GOT_IP:
-            Serial.println("Obtained IP address");
-            break;
-        default: break;
-    }}
+const char *ssid = "your-ssid";
+const char *password = "your-password";
+
+// WARNING: This function is called from a separate FreeRTOS task (thread)!
+void WiFiEvent(WiFiEvent_t event) {
+  Serial.printf("[WiFi-event] event: %d\n", event);
+
+  switch (event) {
+    case ARDUINO_EVENT_WIFI_READY:               Serial.println("WiFi interface ready"); break;
+    case ARDUINO_EVENT_WIFI_SCAN_DONE:           Serial.println("Completed scan for access points"); break;
+    case ARDUINO_EVENT_WIFI_STA_START:           Serial.println("WiFi client started"); break;
+    case ARDUINO_EVENT_WIFI_STA_STOP:            Serial.println("WiFi clients stopped"); break;
+    case ARDUINO_EVENT_WIFI_STA_CONNECTED:       Serial.println("Connected to access point"); break;
+    case ARDUINO_EVENT_WIFI_STA_DISCONNECTED:    Serial.println("Disconnected from WiFi access point"); break;
+    case ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE: Serial.println("Authentication mode of access point has changed"); break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP:
+      Serial.print("Obtained IP address: ");
+      Serial.println(WiFi.localIP());
+      break;
+    case ARDUINO_EVENT_WIFI_STA_LOST_IP:        Serial.println("Lost IP address and IP address is reset to 0"); break;
+    case ARDUINO_EVENT_WPS_ER_SUCCESS:          Serial.println("WiFi Protected Setup (WPS): succeeded in enrollee mode"); break;
+    case ARDUINO_EVENT_WPS_ER_FAILED:           Serial.println("WiFi Protected Setup (WPS): failed in enrollee mode"); break;
+    case ARDUINO_EVENT_WPS_ER_TIMEOUT:          Serial.println("WiFi Protected Setup (WPS): timeout in enrollee mode"); break;
+    case ARDUINO_EVENT_WPS_ER_PIN:              Serial.println("WiFi Protected Setup (WPS): pin code in enrollee mode"); break;
+    case ARDUINO_EVENT_WIFI_AP_START:           Serial.println("WiFi access point started"); break;
+    case ARDUINO_EVENT_WIFI_AP_STOP:            Serial.println("WiFi access point  stopped"); break;
+    case ARDUINO_EVENT_WIFI_AP_STACONNECTED:    Serial.println("Client connected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STADISCONNECTED: Serial.println("Client disconnected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED:   Serial.println("Assigned IP address to client"); break;
+    case ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED:  Serial.println("Received probe request"); break;
+    case ARDUINO_EVENT_WIFI_AP_GOT_IP6:         Serial.println("AP IPv6 is preferred"); break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP6:        Serial.println("STA IPv6 is preferred"); break;
+    case ARDUINO_EVENT_ETH_GOT_IP6:             Serial.println("Ethernet IPv6 is preferred"); break;
+    case ARDUINO_EVENT_ETH_START:               Serial.println("Ethernet started"); break;
+    case ARDUINO_EVENT_ETH_STOP:                Serial.println("Ethernet stopped"); break;
+    case ARDUINO_EVENT_ETH_CONNECTED:           Serial.println("Ethernet connected"); break;
+    case ARDUINO_EVENT_ETH_DISCONNECTED:        Serial.println("Ethernet disconnected"); break;
+    case ARDUINO_EVENT_ETH_GOT_IP:              Serial.println("Obtained IP address"); break;
+    default:                                    break;
+  }
+}
 
-void WiFiGotIP(WiFiEvent_t event, WiFiEventInfo_t info)
-{
-    Serial.println("WiFi connected");
-    Serial.println("IP address: ");
-    Serial.println(IPAddress(info.got_ip.ip_info.ip.addr));
+// WARNING: This function is called from a separate FreeRTOS task (thread)!
+void WiFiGotIP(WiFiEvent_t event, WiFiEventInfo_t info) {
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(IPAddress(info.got_ip.ip_info.ip.addr));
 }
 
-void setup()
-{
-    Serial.begin(115200);
+void setup() {
+  Serial.begin(115200);
 
-    // delete old config
-    WiFi.disconnect(true);
+  // delete old config
+  WiFi.disconnect(true);
 
-    delay(1000);
+  delay(1000);
 
-    // Examples of different ways to register wifi events
-    WiFi.onEvent(WiFiEvent);
-    WiFi.onEvent(WiFiGotIP, WiFiEvent_t::SYSTEM_EVENT_STA_GOT_IP);
-    WiFiEventId_t eventID = WiFi.onEvent([](WiFiEvent_t event, WiFiEventInfo_t info){
-        Serial.print("WiFi lost connection. Reason: ");
-        Serial.println(info.disconnected.reason);
-    }, WiFiEvent_t::SYSTEM_EVENT_STA_DISCONNECTED);
+  // Examples of different ways to register wifi events;
+  // these handlers will be called from another thread.
+  WiFi.onEvent(WiFiEvent);
+  WiFi.onEvent(WiFiGotIP, WiFiEvent_t::ARDUINO_EVENT_WIFI_STA_GOT_IP);
+  WiFiEventId_t eventID = WiFi.onEvent(
+    [](WiFiEvent_t event, WiFiEventInfo_t info) {
+      Serial.print("WiFi lost connection. Reason: ");
+      Serial.println(info.wifi_sta_disconnected.reason);
+    },
+    WiFiEvent_t::ARDUINO_EVENT_WIFI_STA_DISCONNECTED
+  );
 
-    // Remove WiFi event
-    Serial.print("WiFi Event ID: ");
-    Serial.println(eventID);
-    // WiFi.removeEvent(eventID);
+  // Remove WiFi event
+  Serial.print("WiFi Event ID: ");
+  Serial.println(eventID);
+  // WiFi.removeEvent(eventID);
 
-    WiFi.begin(ssid, password);
+  WiFi.begin(ssid, password);
 
-    Serial.println();
-    Serial.println();
-    Serial.println("Wait for WiFi... ");
+  Serial.println();
+  Serial.println();
+  Serial.println("Wait for WiFi... ");
 }
 
-void loop()
-{
-    delay(1000);
+void loop() {
+  delay(1000);
 }
diff --git a/libraries/WiFi/examples/WiFiClientEvents/ci.json b/libraries/WiFi/examples/WiFiClientEvents/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiClientEvents/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiClientStaticIP/WiFiClientStaticIP.ino b/libraries/WiFi/examples/WiFiClientStaticIP/WiFiClientStaticIP.ino
index 1f4032f0640..4d93d00df1b 100644
--- a/libraries/WiFi/examples/WiFiClientStaticIP/WiFiClientStaticIP.ino
+++ b/libraries/WiFi/examples/WiFiClientStaticIP/WiFiClientStaticIP.ino
@@ -6,19 +6,18 @@
 
 #include <WiFi.h>
 
-const char* ssid     = "your_network_name";
-const char* password = "your_network_password";
-const char* host     = "example.com";
-const char* url      = "/index.html";
+const char *ssid = "your_network_name";
+const char *password = "your_network_password";
+const char *host = "example.com";
+const char *url = "/index.html";
 
 IPAddress local_IP(192, 168, 31, 115);
 IPAddress gateway(192, 168, 31, 1);
 IPAddress subnet(255, 255, 0, 0);
-IPAddress primaryDNS(8, 8, 8, 8); //optional
-IPAddress secondaryDNS(8, 8, 4, 4); //optional
+IPAddress primaryDNS(8, 8, 8, 8);    //optional
+IPAddress secondaryDNS(8, 8, 4, 4);  //optional
 
-void setup()
-{
+void setup() {
   Serial.begin(115200);
 
   if (!WiFi.config(local_IP, gateway, subnet, primaryDNS, secondaryDNS)) {
@@ -49,15 +48,14 @@ void setup()
   Serial.println(WiFi.dnsIP());
 }
 
-void loop()
-{
+void loop() {
   delay(5000);
 
   Serial.print("connecting to ");
   Serial.println(host);
 
-  // Use WiFiClient class to create TCP connections
-  WiFiClient client;
+  // Use NetworkClient class to create TCP connections
+  NetworkClient client;
   const int httpPort = 80;
   if (!client.connect(host, httpPort)) {
     Serial.println("connection failed");
@@ -68,9 +66,7 @@ void loop()
   Serial.println(url);
 
   // This will send the request to the server
-  client.print(String("GET ") + url + " HTTP/1.1\r\n" +
-               "Host: " + host + "\r\n" +
-               "Connection: close\r\n\r\n");
+  client.print(String("GET ") + url + " HTTP/1.1\r\n" + "Host: " + host + "\r\n" + "Connection: close\r\n\r\n");
   unsigned long timeout = millis();
   while (client.available() == 0) {
     if (millis() - timeout > 5000) {
@@ -89,4 +85,3 @@ void loop()
   Serial.println();
   Serial.println("closing connection");
 }
-
diff --git a/libraries/WiFi/examples/WiFiClientStaticIP/ci.json b/libraries/WiFi/examples/WiFiClientStaticIP/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiClientStaticIP/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiExtender/WiFiExtender.ino b/libraries/WiFi/examples/WiFiExtender/WiFiExtender.ino
new file mode 100644
index 00000000000..c7f95c1b416
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiExtender/WiFiExtender.ino
@@ -0,0 +1,68 @@
+#include <WiFi.h>
+
+#define STA_SSID "YOUR-SSID"
+#define STA_PASS "YOUR-PASS"
+
+#define AP_SSID "ESP32-WIFI-EXTENDER"
+#define AP_PASS "password"
+
+IPAddress ap_ip(192, 168, 4, 1);
+IPAddress ap_mask(255, 255, 255, 0);
+IPAddress ap_leaseStart(192, 168, 4, 2);
+IPAddress ap_dns(8, 8, 4, 4);
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+  Network.onEvent(onEvent);
+
+  WiFi.AP.begin();
+  WiFi.AP.config(ap_ip, ap_ip, ap_mask, ap_leaseStart, ap_dns);
+  WiFi.AP.create(AP_SSID, AP_PASS);
+  if (!WiFi.AP.waitStatusBits(ESP_NETIF_STARTED_BIT, 1000)) {
+    Serial.println("Failed to start AP!");
+    return;
+  }
+
+  WiFi.begin(STA_SSID, STA_PASS);
+}
+
+void loop() {
+  delay(20000);
+}
+
+void onEvent(arduino_event_id_t event, arduino_event_info_t info) {
+  switch (event) {
+    case ARDUINO_EVENT_WIFI_STA_START:     Serial.println("STA Started"); break;
+    case ARDUINO_EVENT_WIFI_STA_CONNECTED: Serial.println("STA Connected"); break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP:
+      Serial.println("STA Got IP");
+      Serial.println(WiFi.STA);
+      WiFi.AP.enableNAPT(true);
+      break;
+    case ARDUINO_EVENT_WIFI_STA_LOST_IP:
+      Serial.println("STA Lost IP");
+      WiFi.AP.enableNAPT(false);
+      break;
+    case ARDUINO_EVENT_WIFI_STA_DISCONNECTED:
+      Serial.println("STA Disconnected");
+      WiFi.AP.enableNAPT(false);
+      break;
+    case ARDUINO_EVENT_WIFI_STA_STOP: Serial.println("STA Stopped"); break;
+
+    case ARDUINO_EVENT_WIFI_AP_START:
+      Serial.println("AP Started");
+      Serial.println(WiFi.AP);
+      break;
+    case ARDUINO_EVENT_WIFI_AP_STACONNECTED:    Serial.println("AP STA Connected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STADISCONNECTED: Serial.println("AP STA Disconnected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED:
+      Serial.print("AP STA IP Assigned: ");
+      Serial.println(IPAddress(info.wifi_ap_staipassigned.ip.addr));
+      break;
+    case ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED: Serial.println("AP Probe Request Received"); break;
+    case ARDUINO_EVENT_WIFI_AP_STOP:           Serial.println("AP Stopped"); break;
+
+    default: break;
+  }
+}
diff --git a/libraries/WiFi/examples/WiFiExtender/ci.json b/libraries/WiFi/examples/WiFiExtender/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiExtender/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiIPv6/WiFiIPv6.ino b/libraries/WiFi/examples/WiFiIPv6/WiFiIPv6.ino
index 2d3b69789a4..d7241a2f1a4 100644
--- a/libraries/WiFi/examples/WiFiIPv6/WiFiIPv6.ino
+++ b/libraries/WiFi/examples/WiFiIPv6/WiFiIPv6.ino
@@ -6,23 +6,23 @@
 
 static volatile bool wifi_connected = false;
 
-WiFiUDP ntpClient;
+NetworkUDP ntpClient;
 
-void wifiOnConnect(){
-    Serial.println("STA Connected");
-    Serial.print("STA IPv4: ");
-    Serial.println(WiFi.localIP());
-    
-    ntpClient.begin(2390);
+void wifiOnConnect() {
+  Serial.println("STA Connected");
+  Serial.print("STA IPv4: ");
+  Serial.println(WiFi.localIP());
+
+  ntpClient.begin(2390);
 }
 
-void wifiOnDisconnect(){
-    Serial.println("STA Disconnected");
-    delay(1000);
-    WiFi.begin(STA_SSID, STA_PASS);
+void wifiOnDisconnect() {
+  Serial.println("STA Disconnected");
+  delay(1000);
+  WiFi.begin(STA_SSID, STA_PASS);
 }
 
-void wifiConnectedLoop(){
+void wifiConnectedLoop() {
   //lets check the time
   const int NTP_PACKET_SIZE = 48;
   byte ntpPacketBuffer[NTP_PACKET_SIZE];
@@ -30,33 +30,34 @@ void wifiConnectedLoop(){
   IPAddress address;
   WiFi.hostByName("time.nist.gov", address);
   memset(ntpPacketBuffer, 0, NTP_PACKET_SIZE);
-  ntpPacketBuffer[0] = 0b11100011;   // LI, Version, Mode
-  ntpPacketBuffer[1] = 0;     // Stratum, or type of clock
-  ntpPacketBuffer[2] = 6;     // Polling Interval
-  ntpPacketBuffer[3] = 0xEC;  // Peer Clock Precision
+  ntpPacketBuffer[0] = 0b11100011;  // LI, Version, Mode
+  ntpPacketBuffer[1] = 0;           // Stratum, or type of clock
+  ntpPacketBuffer[2] = 6;           // Polling Interval
+  ntpPacketBuffer[3] = 0xEC;        // Peer Clock Precision
   // 8 bytes of zero for Root Delay & Root Dispersion
-  ntpPacketBuffer[12]  = 49;
-  ntpPacketBuffer[13]  = 0x4E;
-  ntpPacketBuffer[14]  = 49;
-  ntpPacketBuffer[15]  = 52;
-  ntpClient.beginPacket(address, 123); //NTP requests are to port 123
+  ntpPacketBuffer[12] = 49;
+  ntpPacketBuffer[13] = 0x4E;
+  ntpPacketBuffer[14] = 49;
+  ntpPacketBuffer[15] = 52;
+  ntpClient.beginPacket(address, 123);  //NTP requests are to port 123
   ntpClient.write(ntpPacketBuffer, NTP_PACKET_SIZE);
   ntpClient.endPacket();
 
   delay(1000);
-  
+
   int packetLength = ntpClient.parsePacket();
-  if (packetLength){
-    if(packetLength >= NTP_PACKET_SIZE){
+  if (packetLength) {
+    if (packetLength >= NTP_PACKET_SIZE) {
       ntpClient.read(ntpPacketBuffer, NTP_PACKET_SIZE);
     }
-    ntpClient.flush();
-    uint32_t secsSince1900 = (uint32_t)ntpPacketBuffer[40] << 24 | (uint32_t)ntpPacketBuffer[41] << 16 | (uint32_t)ntpPacketBuffer[42] << 8 | ntpPacketBuffer[43];
+    ntpClient.clear();
+    uint32_t secsSince1900 =
+      (uint32_t)ntpPacketBuffer[40] << 24 | (uint32_t)ntpPacketBuffer[41] << 16 | (uint32_t)ntpPacketBuffer[42] << 8 | ntpPacketBuffer[43];
     //Serial.printf("Seconds since Jan 1 1900: %u\n", secsSince1900);
     uint32_t epoch = secsSince1900 - 2208988800UL;
     //Serial.printf("EPOCH: %u\n", epoch);
-    uint8_t h = (epoch  % 86400L) / 3600;
-    uint8_t m = (epoch  % 3600) / 60;
+    uint8_t h = (epoch % 86400L) / 3600;
+    uint8_t m = (epoch % 3600) / 60;
     uint8_t s = (epoch % 60);
     Serial.printf("UTC: %02u:%02u:%02u (GMT)\n", h, m, s);
   }
@@ -64,56 +65,56 @@ void wifiConnectedLoop(){
   delay(9000);
 }
 
-void WiFiEvent(WiFiEvent_t event){
-    switch(event) {
-
-        case SYSTEM_EVENT_AP_START:
-            //can set ap hostname here
-            WiFi.softAPsetHostname(AP_SSID);
-            //enable ap ipv6 here
-            WiFi.softAPenableIpV6();
-            break;
-
-        case SYSTEM_EVENT_STA_START:
-            //set sta hostname here
-            WiFi.setHostname(AP_SSID);
-            break;
-        case SYSTEM_EVENT_STA_CONNECTED:
-            //enable sta ipv6 here
-            WiFi.enableIpV6();
-            break;
-        case SYSTEM_EVENT_AP_STA_GOT_IP6:
-            //both interfaces get the same event
-            Serial.print("STA IPv6: ");
-            Serial.println(WiFi.localIPv6());
-            Serial.print("AP IPv6: ");
-            Serial.println(WiFi.softAPIPv6());
-            break;
-        case SYSTEM_EVENT_STA_GOT_IP:
-            wifiOnConnect();
-            wifi_connected = true;
-            break;
-        case SYSTEM_EVENT_STA_DISCONNECTED:
-            wifi_connected = false;
-            wifiOnDisconnect();
-            break;
-        default:
-            break;
-    }
+// WARNING: WiFiEvent is called from a separate FreeRTOS task (thread)!
+void WiFiEvent(WiFiEvent_t event) {
+  switch (event) {
+    case ARDUINO_EVENT_WIFI_AP_START:
+      //can set ap hostname here
+      WiFi.softAPsetHostname(AP_SSID);
+      break;
+    case ARDUINO_EVENT_WIFI_STA_START:
+      //set sta hostname here
+      WiFi.setHostname(AP_SSID);
+      break;
+    case ARDUINO_EVENT_WIFI_STA_CONNECTED: break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP6:
+      Serial.print("STA IPv6: ");
+      Serial.println(WiFi.linkLocalIPv6());
+      break;
+    case ARDUINO_EVENT_WIFI_AP_GOT_IP6:
+      Serial.print("AP IPv6: ");
+      Serial.println(WiFi.softAPlinkLocalIPv6());
+      break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP:
+      wifiOnConnect();
+      wifi_connected = true;
+      break;
+    case ARDUINO_EVENT_WIFI_STA_DISCONNECTED:
+      wifi_connected = false;
+      wifiOnDisconnect();
+      break;
+    default: break;
+  }
 }
 
-void setup(){
-    Serial.begin(115200);
-    WiFi.disconnect(true);
-    WiFi.onEvent(WiFiEvent);
-    WiFi.mode(WIFI_MODE_APSTA);
-    WiFi.softAP(AP_SSID);
-    WiFi.begin(STA_SSID, STA_PASS);
+void setup() {
+  Serial.begin(115200);
+  WiFi.disconnect(true);
+  WiFi.onEvent(WiFiEvent);  // Will call WiFiEvent() from another thread.
+  WiFi.mode(WIFI_MODE_APSTA);
+  //enable ap ipv6 here
+  WiFi.softAPenableIPv6();
+  WiFi.softAP(AP_SSID);
+  //enable sta ipv6 here
+  WiFi.enableIPv6();
+  WiFi.begin(STA_SSID, STA_PASS);
 }
 
-void loop(){
-    if(wifi_connected){
-        wifiConnectedLoop();
-    }
-    while(Serial.available()) Serial.write(Serial.read());
+void loop() {
+  if (wifi_connected) {
+    wifiConnectedLoop();
+  }
+  while (Serial.available()) {
+    Serial.write(Serial.read());
+  }
 }
diff --git a/libraries/WiFi/examples/WiFiIPv6/ci.json b/libraries/WiFi/examples/WiFiIPv6/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiIPv6/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino b/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino
index 2e490d065a8..00a24568e13 100644
--- a/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino
+++ b/libraries/WiFi/examples/WiFiMulti/WiFiMulti.ino
@@ -1,5 +1,5 @@
 /*
- *  This sketch trys to Connect to the best AP based on a given list
+ *  This sketch tries to Connect to the best AP based on a given list
  *
  */
 
@@ -8,28 +8,26 @@
 
 WiFiMulti wifiMulti;
 
-void setup()
-{
-    Serial.begin(115200);
-    delay(10);
+void setup() {
+  Serial.begin(115200);
+  delay(10);
 
-    wifiMulti.addAP("ssid_from_AP_1", "your_password_for_AP_1");
-    wifiMulti.addAP("ssid_from_AP_2", "your_password_for_AP_2");
-    wifiMulti.addAP("ssid_from_AP_3", "your_password_for_AP_3");
+  wifiMulti.addAP("ssid_from_AP_1", "your_password_for_AP_1");
+  wifiMulti.addAP("ssid_from_AP_2", "your_password_for_AP_2");
+  wifiMulti.addAP("ssid_from_AP_3", "your_password_for_AP_3");
 
-    Serial.println("Connecting Wifi...");
-    if(wifiMulti.run() == WL_CONNECTED) {
-        Serial.println("");
-        Serial.println("WiFi connected");
-        Serial.println("IP address: ");
-        Serial.println(WiFi.localIP());
-    }
+  Serial.println("Connecting Wifi...");
+  if (wifiMulti.run() == WL_CONNECTED) {
+    Serial.println("");
+    Serial.println("WiFi connected");
+    Serial.println("IP address: ");
+    Serial.println(WiFi.localIP());
+  }
 }
 
-void loop()
-{
-    if(wifiMulti.run() != WL_CONNECTED) {
-        Serial.println("WiFi not connected!");
-        delay(1000);
-    }
-}
\ No newline at end of file
+void loop() {
+  if (wifiMulti.run() != WL_CONNECTED) {
+    Serial.println("WiFi not connected!");
+    delay(1000);
+  }
+}
diff --git a/libraries/WiFi/examples/WiFiMulti/ci.json b/libraries/WiFi/examples/WiFiMulti/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiMulti/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiMultiAdvanced/WiFiMultiAdvanced.ino b/libraries/WiFi/examples/WiFiMultiAdvanced/WiFiMultiAdvanced.ino
new file mode 100644
index 00000000000..80861611d78
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiMultiAdvanced/WiFiMultiAdvanced.ino
@@ -0,0 +1,64 @@
+/*
+ *  This sketch tries to connect to the best AP available
+ *  and tests for captive portals on open networks
+ *
+ */
+
+#include <WiFi.h>
+#include <WiFiMulti.h>
+#include <HTTPClient.h>
+
+WiFiMulti wifiMulti;
+
+// callback used to check Internet connectivity
+bool testConnection() {
+  HTTPClient http;
+  http.begin("http://www.espressif.com");
+  int httpCode = http.GET();
+  // we expect to get a 301 because it will ask to use HTTPS instead of HTTP
+  if (httpCode == HTTP_CODE_MOVED_PERMANENTLY) {
+    return true;
+  }
+  return false;
+}
+
+void setup() {
+  Serial.begin(115200);
+  delay(10);
+
+  wifiMulti.addAP("ssid_from_AP_1", "your_password_for_AP_1");
+  wifiMulti.addAP("ssid_from_AP_2", "your_password_for_AP_2");
+  wifiMulti.addAP("ssid_from_AP_3", "your_password_for_AP_3");
+
+  // These options can help when you need ANY kind of wifi connection to get a config file, report errors, etc.
+  wifiMulti.setStrictMode(false);  // Default is true.  Library will disconnect and forget currently connected AP if it's not in the AP list.
+  wifiMulti.setAllowOpenAP(true);  // Default is false.  True adds open APs to the AP list.
+  wifiMulti.setConnectionTestCallbackFunc(testConnection);  // Attempts to connect to a remote webserver in case of captive portals.
+
+  Serial.println("Connecting Wifi...");
+  if (wifiMulti.run() == WL_CONNECTED) {
+    Serial.println("");
+    Serial.println("WiFi connected");
+    Serial.println("IP address: ");
+    Serial.println(WiFi.localIP());
+  }
+}
+
+void loop() {
+  static bool isConnected = false;
+  uint8_t WiFiStatus = wifiMulti.run();
+
+  if (WiFiStatus == WL_CONNECTED) {
+    if (!isConnected) {
+      Serial.println("");
+      Serial.println("WiFi connected");
+      Serial.println("IP address: ");
+      Serial.println(WiFi.localIP());
+    }
+    isConnected = true;
+  } else {
+    Serial.println("WiFi not connected!");
+    isConnected = false;
+    delay(5000);
+  }
+}
diff --git a/libraries/WiFi/examples/WiFiMultiAdvanced/ci.json b/libraries/WiFi/examples/WiFiMultiAdvanced/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiMultiAdvanced/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiScan/README.md b/libraries/WiFi/examples/WiFiScan/README.md
new file mode 100644
index 00000000000..f1268f21b5c
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScan/README.md
@@ -0,0 +1,61 @@
+# WiFiScan Example
+
+This example demonstrates how to use the Wi-Fi library to scan available Wi-Fi networks and print the results.
+
+## Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C6 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- |
+
+## How to Use Example
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+#### Using Arduino IDE
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example/Log Output
+
+```
+Setup done
+Scan start
+Scan done
+17 networks found
+Nr | SSID            | RSSI | CH | Encryption
+ 1 | IoTNetwork      |  -62 |  1 | WPA2
+ 2 | WiFiSSID        |  -62 |  1 | WPA2-EAP
+ 3 | B3A7992         |  -63 |  6 | WPA+WPA2
+ 4 | WiFi            |  -63 |  6 | WPA3
+ 5 | IoTNetwork2     |  -64 | 11 | WPA2+WPA3
+...
+```
+
+## Troubleshooting
+
+***Important: Be sure you're using a good quality USB cable and you have enough power source for your project.***
+
+* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed.
+* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else.
+
+## Resources
+
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/WiFi/examples/WiFiScan/WiFiScan.ino b/libraries/WiFi/examples/WiFiScan/WiFiScan.ino
index 5d11fbb6926..15ce367c897 100644
--- a/libraries/WiFi/examples/WiFiScan/WiFiScan.ino
+++ b/libraries/WiFi/examples/WiFiScan/WiFiScan.ino
@@ -1,48 +1,64 @@
 /*
  *  This sketch demonstrates how to scan WiFi networks.
- *  The API is almost the same as with the WiFi Shield library,
- *  the most obvious difference being the different file you need to include:
+ *  The API is based on the Arduino WiFi Shield library, but has significant changes as newer WiFi functions are supported.
+ *  E.g. the return value of `encryptionType()` different because more modern encryption is supported.
  */
 #include "WiFi.h"
 
-void setup()
-{
-    Serial.begin(115200);
+void setup() {
+  Serial.begin(115200);
 
-    // Set WiFi to station mode and disconnect from an AP if it was previously connected
-    WiFi.mode(WIFI_STA);
-    WiFi.disconnect();
-    delay(100);
+  // Set WiFi to station mode and disconnect from an AP if it was previously connected.
+  WiFi.mode(WIFI_STA);
+  WiFi.disconnect();
+  delay(100);
 
-    Serial.println("Setup done");
+  Serial.println("Setup done");
 }
 
-void loop()
-{
-    Serial.println("scan start");
+void loop() {
+  Serial.println("Scan start");
 
-    // WiFi.scanNetworks will return the number of networks found
-    int n = WiFi.scanNetworks();
-    Serial.println("scan done");
-    if (n == 0) {
-        Serial.println("no networks found");
-    } else {
-        Serial.print(n);
-        Serial.println(" networks found");
-        for (int i = 0; i < n; ++i) {
-            // Print SSID and RSSI for each network found
-            Serial.print(i + 1);
-            Serial.print(": ");
-            Serial.print(WiFi.SSID(i));
-            Serial.print(" (");
-            Serial.print(WiFi.RSSI(i));
-            Serial.print(")");
-            Serial.println((WiFi.encryptionType(i) == WIFI_AUTH_OPEN)?" ":"*");
-            delay(10);
-        }
+  // WiFi.scanNetworks will return the number of networks found.
+  int n = WiFi.scanNetworks();
+  Serial.println("Scan done");
+  if (n == 0) {
+    Serial.println("no networks found");
+  } else {
+    Serial.print(n);
+    Serial.println(" networks found");
+    Serial.println("Nr | SSID                             | RSSI | CH | Encryption");
+    for (int i = 0; i < n; ++i) {
+      // Print SSID and RSSI for each network found
+      Serial.printf("%2d", i + 1);
+      Serial.print(" | ");
+      Serial.printf("%-32.32s", WiFi.SSID(i).c_str());
+      Serial.print(" | ");
+      Serial.printf("%4ld", WiFi.RSSI(i));
+      Serial.print(" | ");
+      Serial.printf("%2ld", WiFi.channel(i));
+      Serial.print(" | ");
+      switch (WiFi.encryptionType(i)) {
+        case WIFI_AUTH_OPEN:            Serial.print("open"); break;
+        case WIFI_AUTH_WEP:             Serial.print("WEP"); break;
+        case WIFI_AUTH_WPA_PSK:         Serial.print("WPA"); break;
+        case WIFI_AUTH_WPA2_PSK:        Serial.print("WPA2"); break;
+        case WIFI_AUTH_WPA_WPA2_PSK:    Serial.print("WPA+WPA2"); break;
+        case WIFI_AUTH_WPA2_ENTERPRISE: Serial.print("WPA2-EAP"); break;
+        case WIFI_AUTH_WPA3_PSK:        Serial.print("WPA3"); break;
+        case WIFI_AUTH_WPA2_WPA3_PSK:   Serial.print("WPA2+WPA3"); break;
+        case WIFI_AUTH_WAPI_PSK:        Serial.print("WAPI"); break;
+        default:                        Serial.print("unknown");
+      }
+      Serial.println();
+      delay(10);
     }
-    Serial.println("");
+  }
+  Serial.println("");
 
-    // Wait a bit before scanning again
-    delay(5000);
+  // Delete the scan result to free memory for code below.
+  WiFi.scanDelete();
+
+  // Wait a bit before scanning again.
+  delay(5000);
 }
diff --git a/libraries/WiFi/examples/WiFiScan/ci.json b/libraries/WiFi/examples/WiFiScan/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScan/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiScanAsync/README.md b/libraries/WiFi/examples/WiFiScanAsync/README.md
new file mode 100644
index 00000000000..26120aaa31c
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScanAsync/README.md
@@ -0,0 +1,71 @@
+# WiFiScanAsync Example
+
+This example demonstrates how to use the Wi-Fi library to scan available Wi-Fi networks in asynchronous mode and print the results.
+
+## Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C6 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- |
+
+## How to Use Example
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+#### Using Arduino IDE
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example/Log Output
+
+```
+Setup done
+Scan start
+Loop running...
+Loop running...
+Loop running...
+Loop running...
+Loop running...
+Loop running...
+Loop running...
+Loop running...
+Loop running...
+
+Scan done
+17 networks found
+Nr | SSID            | RSSI | CH | Encryption
+ 1 | IoTNetwork      |  -62 |  1 | WPA2
+ 2 | WiFiSSID        |  -62 |  1 | WPA2-EAP
+ 3 | B3A7992         |  -63 |  6 | WPA+WPA2
+ 4 | WiFi            |  -63 |  6 | WPA3
+ 5 | IoTNetwork2     |  -64 | 11 | WPA2+WPA3
+...
+```
+
+## Troubleshooting
+
+***Important: Be sure you're using a good quality USB cable and you have enough power source for your project.***
+
+* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed.
+* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else.
+
+## Resources
+
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/WiFi/examples/WiFiScanAsync/WiFiScanAsync.ino b/libraries/WiFi/examples/WiFiScanAsync/WiFiScanAsync.ino
new file mode 100644
index 00000000000..b5f4a0abe08
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScanAsync/WiFiScanAsync.ino
@@ -0,0 +1,82 @@
+/*
+    This sketch demonstrates how to scan WiFi networks in Async Mode.
+    The API is based on the Arduino WiFi Shield library, but has significant changes as newer WiFi functions are supported.
+    E.g. the return value of `encryptionType()` different because more modern encryption is supported.
+*/
+#include "WiFi.h"
+
+void startWiFiScan() {
+  Serial.println("Scan start");
+  // WiFi.scanNetworks will return immediately in Async Mode.
+  WiFi.scanNetworks(true);  // 'true' turns Async Mode ON
+}
+
+void printScannedNetworks(uint16_t networksFound) {
+  if (networksFound == 0) {
+    Serial.println("no networks found");
+  } else {
+    Serial.println("\nScan done");
+    Serial.print(networksFound);
+    Serial.println(" networks found");
+    Serial.println("Nr | SSID                             | RSSI | CH | Encryption");
+    for (int i = 0; i < networksFound; ++i) {
+      // Print SSID and RSSI for each network found
+      Serial.printf("%2d", i + 1);
+      Serial.print(" | ");
+      Serial.printf("%-32.32s", WiFi.SSID(i).c_str());
+      Serial.print(" | ");
+      Serial.printf("%4ld", WiFi.RSSI(i));
+      Serial.print(" | ");
+      Serial.printf("%2ld", WiFi.channel(i));
+      Serial.print(" | ");
+      switch (WiFi.encryptionType(i)) {
+        case WIFI_AUTH_OPEN:            Serial.print("open"); break;
+        case WIFI_AUTH_WEP:             Serial.print("WEP"); break;
+        case WIFI_AUTH_WPA_PSK:         Serial.print("WPA"); break;
+        case WIFI_AUTH_WPA2_PSK:        Serial.print("WPA2"); break;
+        case WIFI_AUTH_WPA_WPA2_PSK:    Serial.print("WPA+WPA2"); break;
+        case WIFI_AUTH_WPA2_ENTERPRISE: Serial.print("WPA2-EAP"); break;
+        case WIFI_AUTH_WPA3_PSK:        Serial.print("WPA3"); break;
+        case WIFI_AUTH_WPA2_WPA3_PSK:   Serial.print("WPA2+WPA3"); break;
+        case WIFI_AUTH_WAPI_PSK:        Serial.print("WAPI"); break;
+        default:                        Serial.print("unknown");
+      }
+      Serial.println();
+      delay(10);
+    }
+    Serial.println("");
+    // Delete the scan result to free memory for code below.
+    WiFi.scanDelete();
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  // Set WiFi to station mode and disconnect from an AP if it was previously connected.
+  WiFi.mode(WIFI_STA);
+  WiFi.disconnect();
+  delay(100);
+
+  Serial.println("Setup done");
+  startWiFiScan();
+}
+
+void loop() {
+  // check WiFi Scan Async process
+  int16_t WiFiScanStatus = WiFi.scanComplete();
+  if (WiFiScanStatus < 0) {  // it is busy scanning or got an error
+    if (WiFiScanStatus == WIFI_SCAN_FAILED) {
+      Serial.println("WiFi Scan has failed. Starting again.");
+      startWiFiScan();
+    }
+    // other option is status WIFI_SCAN_RUNNING - just wait.
+  } else {  // Found Zero or more Wireless Networks
+    printScannedNetworks(WiFiScanStatus);
+    startWiFiScan();  // start over...
+  }
+
+  // Loop can do something else...
+  delay(250);
+  Serial.println("Loop running...");
+}
diff --git a/libraries/WiFi/examples/WiFiScanAsync/ci.json b/libraries/WiFi/examples/WiFiScanAsync/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScanAsync/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiScanDualAntenna/README.md b/libraries/WiFi/examples/WiFiScanDualAntenna/README.md
new file mode 100644
index 00000000000..9a6611149d0
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScanDualAntenna/README.md
@@ -0,0 +1,66 @@
+# WiFiScan Example
+
+This example demonstrates how to use the Wi-Fi library to scan available Wi-Fi networks and print the results.
+
+This example shows the basic functionality of the dual antenna capability.
+
+# Supported Targets
+
+This example is compatible with the ESP32-WROOM-DA.
+
+## How to Use Example
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+#### Using Arduino IDE
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example/Log Output
+
+```
+ets Jul 29 2019 12:21:46
+
+rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
+configsip: 0, SPIWP:0xee
+clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
+mode:DIO, clock div:1
+load:0x3fff0030,len:1412
+load:0x40078000,len:13400
+load:0x40080400,len:3672
+entry 0x400805f8
+Setup done
+scan start
+scan done
+17 networks found
+1: IoTNetwork (-62)*
+2: WiFiSSID (-62)*
+3: B3A7992 (-63)*
+4: WiFi (-63)
+5: IoTNetwork2 (-64)*
+...
+```
+
+## Troubleshooting
+
+***Important: Be sure you're using a good quality USB cable and you have enough power source for your project.***
+
+* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed.
+* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else.
+
+## Resources
+
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-WROOM-DA Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-wroom-da_datasheet_en.pdf)
diff --git a/libraries/WiFi/examples/WiFiScanDualAntenna/WiFiScanDualAntenna.ino b/libraries/WiFi/examples/WiFiScanDualAntenna/WiFiScanDualAntenna.ino
new file mode 100644
index 00000000000..4db68d87d98
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScanDualAntenna/WiFiScanDualAntenna.ino
@@ -0,0 +1,77 @@
+/*
+ *  This sketch demonstrates how to scan WiFi networks.
+ *  The API is almost the same as with the WiFi Shield library,
+ *  the most obvious difference being the different file you need to include:
+ */
+#include "WiFi.h"
+
+/* These are the GPIOs connected to the antenna switch on the ESP32-WROOM-DA.
+ * Both GPIOs are not exposed to the module pins and cannot be used except to
+ * control the antnnas switch.
+ *
+ * For more details, see the datashhet at:
+ * https://www.espressif.com/sites/default/files/documentation/esp32-wroom-da_datasheet_en.pdf
+ */
+
+#define GPIO_ANT1 2   // GPIO for antenna 1
+#define GPIO_ANT2 25  // GPIO for antenna 2 (default)
+
+void setup() {
+  bool err = false;
+  Serial.begin(115200);
+
+  // Set WiFi to station mode and disconnect from an AP if it was previously connected
+  WiFi.mode(WIFI_STA);
+
+  /* Attention: This is the manual procedure for the dual antenna configuration.
+     * If you choose the ESP32-WROOM-DA module from the Tools -> Board, this configuration
+     * is not necessary!
+     *
+     * Set WiFi dual antenna configuration by passing the GPIO and antenna mode for RX ant TX
+     */
+  err = WiFi.setDualAntennaConfig(GPIO_ANT1, GPIO_ANT2, WIFI_RX_ANT_AUTO, WIFI_TX_ANT_AUTO);
+
+  /* For more details on how to use this feature, see our docs:
+     * https://docs.espressif.com/projects/arduino-esp32/en/latest/api/wifi.html
+     */
+
+  if (err == false) {
+    Serial.println("Dual Antenna configuration failed!");
+  } else {
+    Serial.println("Dual Antenna configuration successfully done!");
+  }
+
+  WiFi.disconnect();
+  delay(100);
+
+  Serial.println("Setup done");
+}
+
+void loop() {
+  Serial.println("scan start");
+
+  // WiFi.scanNetworks will return the number of networks found
+  int n = WiFi.scanNetworks();
+  Serial.println("scan done");
+  if (n == 0) {
+    Serial.println("no networks found");
+  } else {
+    Serial.print(n);
+    Serial.println(" networks found");
+    for (int i = 0; i < n; ++i) {
+      // Print SSID and RSSI for each network found
+      Serial.print(i + 1);
+      Serial.print(": ");
+      Serial.print(WiFi.SSID(i));
+      Serial.print(" (");
+      Serial.print(WiFi.RSSI(i));
+      Serial.print(")");
+      Serial.println((WiFi.encryptionType(i) == WIFI_AUTH_OPEN) ? " " : "*");
+      delay(10);
+    }
+  }
+  Serial.println("");
+
+  // Wait a bit before scanning again
+  delay(5000);
+}
diff --git a/libraries/WiFi/examples/WiFiScanDualAntenna/ci.json b/libraries/WiFi/examples/WiFiScanDualAntenna/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScanDualAntenna/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiScanTime/README.md b/libraries/WiFi/examples/WiFiScanTime/README.md
new file mode 100644
index 00000000000..7be0e05d4fe
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScanTime/README.md
@@ -0,0 +1,61 @@
+# WiFiScanTime Example
+
+This example demonstrates how to use the Wi-Fi library to scan available Wi-Fi networks with custom scan timing and print the results.
+
+## Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 | ESP32-C6 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- |
+
+## How to Use Example
+
+* How to install the Arduino IDE: [Install Arduino IDE](https://github.com/espressif/arduino-esp32/tree/master/docs/arduino-ide).
+
+#### Using Arduino IDE
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+
+## Example/Log Output
+
+```
+Setup done
+Scan start
+Scan done, elapsed time: 4960 ms
+17 networks found
+Nr | SSID            | RSSI | CH | Encryption
+ 1 | IoTNetwork      |  -62 |  1 | WPA2
+ 2 | WiFiSSID        |  -62 |  1 | WPA2-EAP
+ 3 | B3A7992         |  -63 |  6 | WPA+WPA2
+ 4 | WiFi            |  -63 |  6 | WPA3
+ 5 | IoTNetwork2     |  -64 | 11 | WPA2+WPA3
+...
+```
+
+## Troubleshooting
+
+***Important: Be sure you're using a good quality USB cable and you have enough power source for your project.***
+
+* **Programming Fail:** If the programming/flash procedure fails, try to reduce the serial connection speed.
+* **COM port not detected:** Check the USB cable connection and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try the Troubleshooting and to check if the same issue was already created by someone else.
+
+## Resources
+
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf)
+* ESP32-S2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf)
+* ESP32-C3 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/WiFi/examples/WiFiScanTime/WiFiScanTime.ino b/libraries/WiFi/examples/WiFiScanTime/WiFiScanTime.ino
new file mode 100644
index 00000000000..93dba7905ae
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScanTime/WiFiScanTime.ino
@@ -0,0 +1,92 @@
+/*
+ *  This sketch demonstrates how to scan WiFi networks with custom scanning time.
+ *  The API is based on the Arduino WiFi Shield library, but has significant changes as newer WiFi functions are supported.
+ *  E.g. the return value of `encryptionType()` different because more modern encryption is supported.
+ */
+
+/*
+ * WiFi scan timing parameters explained:
+ *
+ * min=0, max=0: scan dwells on each channel for 120 ms.
+ * min>0, max=0: scan dwells on each channel for 120 ms.
+ * min=0, max>0: scan dwells on each channel for max ms.
+ * min>0, max>0: the minimum time the scan dwells on each channel is min ms. If no AP is found during this time frame, the scan switches to the next channel. Otherwise, the scan dwells on the channel for max ms.
+ */
+
+#include "WiFi.h"
+
+void wifiScan(uint16_t min_time, uint16_t max_time) {
+  Serial.println("Scan start");
+
+  // Set the minimum time per channel for active scanning.
+  WiFi.setScanActiveMinTime(min_time);
+
+  // Capture the start time of the scan.
+  uint32_t start = millis();
+
+  // WiFi.scanNetworks will return the number of networks found.
+  // Scan networks with those options: Synchrone mode, show hidden networks, active scan, max scan time per channel.
+  int n = WiFi.scanNetworks(false, true, false, max_time);
+  Serial.printf("Scan done, elapsed time: %lu ms\n", millis() - start);
+  if (n == 0) {
+    Serial.println("no networks found");
+  } else {
+    Serial.print(n);
+    Serial.println(" networks found");
+    Serial.println("Nr | SSID                             | RSSI | CH | Encryption");
+    for (int i = 0; i < n; ++i) {
+      // Print SSID and RSSI for each network found
+      Serial.printf("%2d", i + 1);
+      Serial.print(" | ");
+      Serial.printf("%-32.32s", WiFi.SSID(i).c_str());
+      Serial.print(" | ");
+      Serial.printf("%4ld", WiFi.RSSI(i));
+      Serial.print(" | ");
+      Serial.printf("%2ld", WiFi.channel(i));
+      Serial.print(" | ");
+      switch (WiFi.encryptionType(i)) {
+        case WIFI_AUTH_OPEN:            Serial.print("open"); break;
+        case WIFI_AUTH_WEP:             Serial.print("WEP"); break;
+        case WIFI_AUTH_WPA_PSK:         Serial.print("WPA"); break;
+        case WIFI_AUTH_WPA2_PSK:        Serial.print("WPA2"); break;
+        case WIFI_AUTH_WPA_WPA2_PSK:    Serial.print("WPA+WPA2"); break;
+        case WIFI_AUTH_WPA2_ENTERPRISE: Serial.print("WPA2-EAP"); break;
+        case WIFI_AUTH_WPA3_PSK:        Serial.print("WPA3"); break;
+        case WIFI_AUTH_WPA2_WPA3_PSK:   Serial.print("WPA2+WPA3"); break;
+        case WIFI_AUTH_WAPI_PSK:        Serial.print("WAPI"); break;
+        default:                        Serial.print("unknown");
+      }
+      Serial.println();
+      delay(10);
+    }
+  }
+  Serial.println("");
+
+  // Delete the scan result to free memory for code below.
+  WiFi.scanDelete();
+
+  // Wait a bit before scanning again
+  delay(2000);
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  // Set WiFi to station mode and disconnect from an AP if it was previously connected.
+  WiFi.mode(WIFI_STA);
+  WiFi.disconnect();
+  delay(100);
+
+  // Scan WiFi networks with a minimum time of 100 ms per channel and a maximum time of 300 ms per channel (default values).
+  wifiScan(100, 300);
+
+  // Scan WiFi networks with a minimum time of 100 ms per channel and a maximum time of 1500 ms per channel.
+  wifiScan(100, 1500);
+
+  // Scan WiFi networks with a minimum time of 0 ms per channel and a maximum time of 1500 ms per channel.
+  wifiScan(0, 1500);
+}
+
+void loop() {
+  // Nothing to do here
+}
diff --git a/libraries/WiFi/examples/WiFiScanTime/ci.json b/libraries/WiFi/examples/WiFiScanTime/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiScanTime/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiSmartConfig/WiFiSmartConfig.ino b/libraries/WiFi/examples/WiFiSmartConfig/WiFiSmartConfig.ino
index 4c1f1a8ce6d..724355c6a37 100644
--- a/libraries/WiFi/examples/WiFiSmartConfig/WiFiSmartConfig.ino
+++ b/libraries/WiFi/examples/WiFiSmartConfig/WiFiSmartConfig.ino
@@ -1,3 +1,8 @@
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#error "SmartConfig is only supported in SoCs with native Wi-Fi support"
+#endif
+
 #include "WiFi.h"
 
 void setup() {
@@ -32,5 +37,4 @@ void setup() {
 
 void loop() {
   // put your main code here, to run repeatedly:
-
 }
diff --git a/libraries/WiFi/examples/WiFiSmartConfig/ci.json b/libraries/WiFi/examples/WiFiSmartConfig/ci.json
new file mode 100644
index 00000000000..36babb82730
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiSmartConfig/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino b/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino
index 63bdf6c13b6..c227da08910 100644
--- a/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino
+++ b/libraries/WiFi/examples/WiFiTelnetToSerial/WiFiTelnetToSerial.ino
@@ -25,11 +25,11 @@ WiFiMulti wifiMulti;
 
 //how many clients should be able to telnet to this ESP32
 #define MAX_SRV_CLIENTS 1
-const char* ssid = "**********";
-const char* password = "**********";
+const char *ssid = "**********";
+const char *password = "**********";
 
-WiFiServer server(23);
-WiFiClient serverClients[MAX_SRV_CLIENTS];
+NetworkServer server(23);
+NetworkClient serverClients[MAX_SRV_CLIENTS];
 
 void setup() {
   Serial.begin(115200);
@@ -47,8 +47,7 @@ void setup() {
       Serial.print("IP address: ");
       Serial.println(WiFi.localIP());
       break;
-    }
-    else {
+    } else {
       Serial.println(loops);
       delay(1000);
     }
@@ -60,7 +59,7 @@ void setup() {
   }
 
   //start UART and the server
-  Serial2.begin(9600);
+  Serial1.begin(9600);
   server.begin();
   server.setNoDelay(true);
 
@@ -73,56 +72,63 @@ void loop() {
   uint8_t i;
   if (wifiMulti.run() == WL_CONNECTED) {
     //check if there are any new clients
-    if (server.hasClient()){
-      for(i = 0; i < MAX_SRV_CLIENTS; i++){
+    if (server.hasClient()) {
+      for (i = 0; i < MAX_SRV_CLIENTS; i++) {
         //find free/disconnected spot
-        if (!serverClients[i] || !serverClients[i].connected()){
-          if(serverClients[i]) serverClients[i].stop();
-          serverClients[i] = server.available();
-          if (!serverClients[i]) Serial.println("available broken");
+        if (!serverClients[i] || !serverClients[i].connected()) {
+          if (serverClients[i]) {
+            serverClients[i].stop();
+          }
+          serverClients[i] = server.accept();
+          if (!serverClients[i]) {
+            Serial.println("available broken");
+          }
           Serial.print("New client: ");
-          Serial.print(i); Serial.print(' ');
+          Serial.print(i);
+          Serial.print(' ');
           Serial.println(serverClients[i].remoteIP());
           break;
         }
       }
       if (i >= MAX_SRV_CLIENTS) {
         //no free/disconnected spot so reject
-        server.available().stop();
+        server.accept().stop();
       }
     }
     //check clients for data
-    for(i = 0; i < MAX_SRV_CLIENTS; i++){
-      if (serverClients[i] && serverClients[i].connected()){
-        if(serverClients[i].available()){
+    for (i = 0; i < MAX_SRV_CLIENTS; i++) {
+      if (serverClients[i] && serverClients[i].connected()) {
+        if (serverClients[i].available()) {
           //get data from the telnet client and push it to the UART
-          while(serverClients[i].available()) Serial2.write(serverClients[i].read());
+          while (serverClients[i].available()) {
+            Serial1.write(serverClients[i].read());
+          }
         }
-      }
-      else {
+      } else {
         if (serverClients[i]) {
           serverClients[i].stop();
         }
       }
     }
     //check UART for data
-    if(Serial2.available()){
-      size_t len = Serial2.available();
+    if (Serial1.available()) {
+      size_t len = Serial1.available();
       uint8_t sbuf[len];
-      Serial2.readBytes(sbuf, len);
+      Serial1.readBytes(sbuf, len);
       //push UART data to all connected telnet clients
-      for(i = 0; i < MAX_SRV_CLIENTS; i++){
-        if (serverClients[i] && serverClients[i].connected()){
+      for (i = 0; i < MAX_SRV_CLIENTS; i++) {
+        if (serverClients[i] && serverClients[i].connected()) {
           serverClients[i].write(sbuf, len);
           delay(1);
         }
       }
     }
-  }
-  else {
+  } else {
     Serial.println("WiFi not connected!");
-    for(i = 0; i < MAX_SRV_CLIENTS; i++) {
-      if (serverClients[i]) serverClients[i].stop();
+    for (i = 0; i < MAX_SRV_CLIENTS; i++) {
+      if (serverClients[i]) {
+        serverClients[i].stop();
+      }
     }
     delay(1000);
   }
diff --git a/libraries/WiFi/examples/WiFiTelnetToSerial/ci.json b/libraries/WiFi/examples/WiFiTelnetToSerial/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiTelnetToSerial/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiUDPClient/WiFiUDPClient.ino b/libraries/WiFi/examples/WiFiUDPClient/WiFiUDPClient.ino
index 310989f0c1f..f828ca264e7 100644
--- a/libraries/WiFi/examples/WiFiUDPClient/WiFiUDPClient.ino
+++ b/libraries/WiFi/examples/WiFiUDPClient/WiFiUDPClient.ino
@@ -3,74 +3,74 @@
  *
  */
 #include <WiFi.h>
-#include <WiFiUdp.h>
+#include <NetworkUdp.h>
 
 // WiFi network name and password:
-const char * networkName = "your-ssid";
-const char * networkPswd = "your-password";
+const char *networkName = "your-ssid";
+const char *networkPswd = "your-password";
 
 //IP address to send UDP data to:
-// either use the ip address of the server or 
+// either use the ip address of the server or
 // a network broadcast address
-const char * udpAddress = "192.168.0.255";
+const char *udpAddress = "192.168.0.255";
 const int udpPort = 3333;
 
 //Are we currently connected?
 boolean connected = false;
 
 //The udp library class
-WiFiUDP udp;
+NetworkUDP udp;
 
-void setup(){
-  // Initilize hardware serial:
+void setup() {
+  // Initialize hardware serial:
   Serial.begin(115200);
-  
+
   //Connect to the WiFi network
   connectToWiFi(networkName, networkPswd);
 }
 
-void loop(){
+void loop() {
   //only send data when connected
-  if(connected){
+  if (connected) {
     //Send a packet
-    udp.beginPacket(udpAddress,udpPort);
-    udp.printf("Seconds since boot: %lu", millis()/1000);
+    udp.beginPacket(udpAddress, udpPort);
+    udp.printf("Seconds since boot: %lu", millis() / 1000);
     udp.endPacket();
   }
   //Wait for 1 second
   delay(1000);
 }
 
-void connectToWiFi(const char * ssid, const char * pwd){
+void connectToWiFi(const char *ssid, const char *pwd) {
   Serial.println("Connecting to WiFi network: " + String(ssid));
 
   // delete old config
   WiFi.disconnect(true);
   //register event handler
-  WiFi.onEvent(WiFiEvent);
-  
+  WiFi.onEvent(WiFiEvent);  // Will call WiFiEvent() from another thread.
+
   //Initiate connection
   WiFi.begin(ssid, pwd);
 
   Serial.println("Waiting for WIFI connection...");
 }
 
-//wifi event handler
-void WiFiEvent(WiFiEvent_t event){
-    switch(event) {
-      case SYSTEM_EVENT_STA_GOT_IP:
-          //When connected set 
-          Serial.print("WiFi connected! IP address: ");
-          Serial.println(WiFi.localIP());  
-          //initializes the UDP state
-          //This initializes the transfer buffer
-          udp.begin(WiFi.localIP(),udpPort);
-          connected = true;
-          break;
-      case SYSTEM_EVENT_STA_DISCONNECTED:
-          Serial.println("WiFi lost connection");
-          connected = false;
-          break;
-      default: break;
-    }
+// WARNING: WiFiEvent is called from a separate FreeRTOS task (thread)!
+void WiFiEvent(WiFiEvent_t event) {
+  switch (event) {
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP:
+      //When connected set
+      Serial.print("WiFi connected! IP address: ");
+      Serial.println(WiFi.localIP());
+      //initializes the UDP state
+      //This initializes the transfer buffer
+      udp.begin(WiFi.localIP(), udpPort);
+      connected = true;
+      break;
+    case ARDUINO_EVENT_WIFI_STA_DISCONNECTED:
+      Serial.println("WiFi lost connection");
+      connected = false;
+      break;
+    default: break;
+  }
 }
diff --git a/libraries/WiFi/examples/WiFiUDPClient/ci.json b/libraries/WiFi/examples/WiFiUDPClient/ci.json
new file mode 100644
index 00000000000..618e46bd244
--- /dev/null
+++ b/libraries/WiFi/examples/WiFiUDPClient/ci.json
@@ -0,0 +1,6 @@
+{
+  "requires_any": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y",
+    "CONFIG_ESP_WIFI_REMOTE_ENABLED=y"
+  ]
+}
diff --git a/libraries/WiFi/examples/WiFiUDPClient/udp_server.py b/libraries/WiFi/examples/WiFiUDPClient/udp_server.py
index 90272353ac1..c70a6fe2c37 100644
--- a/libraries/WiFi/examples/WiFiUDPClient/udp_server.py
+++ b/libraries/WiFi/examples/WiFiUDPClient/udp_server.py
@@ -1,30 +1,32 @@
-# This python script listens on UDP port 3333 
+# This python script listens on UDP port 3333
 # for messages from the ESP32 board and prints them
 import socket
 import sys
 
-try :
+try:
     s = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
     s.setsockopt(socket.SOL_SOCKET, socket.SO_REUSEADDR, 1)
-except socket.error, msg :
-    print 'Failed to create socket. Error Code : ' + str(msg[0]) + ' Message ' + msg[1]
+except socket.error as msg:
+    print("Failed to create socket. Error Code : " + str(msg[0]) + " Message " + msg[1])
     sys.exit()
 
 try:
-    s.bind(('', 3333))
-except socket.error , msg:
-    print 'Bind failed. Error: ' + str(msg[0]) + ': ' + msg[1]
+    s.bind(("", 3333))
+except socket.error as msg:
+    print("Bind failed. Error: " + str(msg[0]) + ": " + msg[1])
     sys.exit()
-     
-print 'Server listening'
+
+print("Server listening")
+
+print("Server listening")
 
 while 1:
     d = s.recvfrom(1024)
     data = d[0]
-     
-    if not data: 
+
+    if not data:
         break
-    
-    print data.strip()
-    
-s.close()
\ No newline at end of file
+
+    print(data.strip())
+
+s.close()
diff --git a/libraries/WiFi/examples/WiFiUDPClient/udp_server.rb b/libraries/WiFi/examples/WiFiUDPClient/udp_server.rb
index 50e241d4bcf..abcfccab87a 100644
--- a/libraries/WiFi/examples/WiFiUDPClient/udp_server.rb
+++ b/libraries/WiFi/examples/WiFiUDPClient/udp_server.rb
@@ -1,4 +1,4 @@
-# This ruby script listens on UDP port 3333 
+# This ruby script listens on UDP port 3333
 # for messages from the ESP32 board and prints them
 
 require 'socket'
@@ -6,11 +6,11 @@
 
 udp_socket = UDPSocket.new(AF_INET)
 
-#bind 
+#bind
 udp_socket.bind("", 3333)
 puts 'Server listening'
 
 while true do
   message, sender = udp_socket.recvfrom(1024)
   puts message
-end
\ No newline at end of file
+end
diff --git a/libraries/WiFi/keywords.txt b/libraries/WiFi/keywords.txt
index 5720aaac81c..08b970b928f 100644
--- a/libraries/WiFi/keywords.txt
+++ b/libraries/WiFi/keywords.txt
@@ -13,10 +13,10 @@ WiFi	KEYWORD3
 #######################################
 
 WiFi	KEYWORD1
-WiFiClient	KEYWORD1
-WiFiServer	KEYWORD1
-WiFiUDP	KEYWORD1
-WiFiClientSecure	KEYWORD1
+NetworkClient	KEYWORD1
+NetworkServer	KEYWORD1
+NetworkUDP	KEYWORD1
+NetworkClientSecure	KEYWORD1
 
 #######################################
 # Methods and Functions (KEYWORD2)
diff --git a/libraries/WiFi/library.properties b/libraries/WiFi/library.properties
index c98691df3a7..03112c2fcc6 100644
--- a/libraries/WiFi/library.properties
+++ b/libraries/WiFi/library.properties
@@ -1,9 +1,9 @@
 name=WiFi
-version=1.0
+version=3.2.0
 author=Hristo Gochkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=Enables network connection (local and Internet) using the ESP32 built-in WiFi.
-paragraph=With this library you can instantiate Servers, Clients and send/receive UDP packets through WiFi. The shield can connect either to open or encrypted networks (WEP, WPA). The IP address can be assigned statically or through a DHCP. The library can also manage DNS.
+paragraph=With this library you can instantiate Servers, Clients and send/receive UDP packets through WiFi. The shield can connect either to open or encrypted networks. The IP address can be assigned statically or through a DHCP. The library can also manage DNS.
 category=Communication
 url=
 architectures=esp32
diff --git a/libraries/WiFi/src/AP.cpp b/libraries/WiFi/src/AP.cpp
new file mode 100644
index 00000000000..0e7839764ea
--- /dev/null
+++ b/libraries/WiFi/src/AP.cpp
@@ -0,0 +1,376 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "WiFi.h"
+#include "WiFiGeneric.h"
+#include "WiFiAP.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+#include <string.h>
+#include <esp_err.h>
+#include <esp_mac.h>
+#include <esp_wifi.h>
+#include <esp_event.h>
+#include <lwip/ip_addr.h>
+#include "dhcpserver/dhcpserver_options.h"
+#include "esp_netif.h"
+
+esp_netif_t *get_esp_interface_netif(esp_interface_t interface);
+
+static size_t _wifi_strncpy(char *dst, const char *src, size_t dst_len) {
+  if (!dst || !src || !dst_len) {
+    return 0;
+  }
+  size_t src_len = strlen(src);
+  if (src_len >= dst_len) {
+    src_len = dst_len;
+  } else {
+    src_len += 1;
+  }
+  memcpy(dst, src, src_len);
+  return src_len;
+}
+
+/**
+ * compare two AP configurations
+ * @param lhs softap_config
+ * @param rhs softap_config
+ * @return equal
+ */
+static bool softap_config_equal(const wifi_config_t &lhs, const wifi_config_t &rhs) {
+  if (strncmp(reinterpret_cast<const char *>(lhs.ap.ssid), reinterpret_cast<const char *>(rhs.ap.ssid), 32) != 0) {
+    return false;
+  }
+  if (strncmp(reinterpret_cast<const char *>(lhs.ap.password), reinterpret_cast<const char *>(rhs.ap.password), 64) != 0) {
+    return false;
+  }
+  if (lhs.ap.channel != rhs.ap.channel) {
+    return false;
+  }
+  if (lhs.ap.authmode != rhs.ap.authmode) {
+    return false;
+  }
+  if (lhs.ap.ssid_hidden != rhs.ap.ssid_hidden) {
+    return false;
+  }
+  if (lhs.ap.max_connection != rhs.ap.max_connection) {
+    return false;
+  }
+  if (lhs.ap.pairwise_cipher != rhs.ap.pairwise_cipher) {
+    return false;
+  }
+  if (lhs.ap.ftm_responder != rhs.ap.ftm_responder) {
+    return false;
+  }
+  return true;
+}
+
+static APClass *_ap_network_if = NULL;
+
+static esp_event_handler_instance_t _ap_ev_instance = NULL;
+static void _ap_event_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == WIFI_EVENT) {
+    ((APClass *)arg)->_onApEvent(event_id, event_data);
+  }
+}
+
+static void _onApArduinoEvent(arduino_event_t *ev) {
+  if (_ap_network_if == NULL || ev->event_id < ARDUINO_EVENT_WIFI_AP_START || ev->event_id > ARDUINO_EVENT_WIFI_AP_GOT_IP6) {
+    return;
+  }
+  log_v("Arduino AP Event: %d - %s", ev->event_id, Network.eventName(ev->event_id));
+  if (ev->event_id == ARDUINO_EVENT_WIFI_AP_START) {
+#if CONFIG_LWIP_IPV6
+    if (_ap_network_if->getStatusBits() & ESP_NETIF_WANT_IP6_BIT) {
+      esp_err_t err = esp_netif_create_ip6_linklocal(_ap_network_if->netif());
+      if (err != ESP_OK) {
+        log_e("Failed to enable IPv6 Link Local on AP:  0x%x: %s", err, esp_err_to_name(err));
+      } else {
+        log_v("Enabled IPv6 Link Local on %s", _ap_network_if->desc());
+      }
+    }
+#endif
+  }
+}
+
+void APClass::_onApEvent(int32_t event_id, void *event_data) {
+  arduino_event_t arduino_event;
+  arduino_event.event_id = ARDUINO_EVENT_MAX;
+
+  if (event_id == WIFI_EVENT_AP_START) {
+    log_v("AP Started");
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_START;
+    setStatusBits(ESP_NETIF_STARTED_BIT);
+  } else if (event_id == WIFI_EVENT_AP_STOP) {
+    log_v("AP Stopped");
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_STOP;
+    clearStatusBits(ESP_NETIF_STARTED_BIT | ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT);
+  } else if (event_id == WIFI_EVENT_AP_PROBEREQRECVED) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    wifi_event_ap_probe_req_rx_t *event = (wifi_event_ap_probe_req_rx_t *)event_data;
+    log_v("AP Probe Request: RSSI: %d, MAC: " MACSTR, event->rssi, MAC2STR(event->mac));
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED;
+    memcpy(&arduino_event.event_info.wifi_ap_probereqrecved, event_data, sizeof(wifi_event_ap_probe_req_rx_t));
+  } else if (event_id == WIFI_EVENT_AP_STACONNECTED) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    wifi_event_ap_staconnected_t *event = (wifi_event_ap_staconnected_t *)event_data;
+    log_v("AP Station Connected: MAC: " MACSTR ", AID: %d", MAC2STR(event->mac), event->aid);
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_STACONNECTED;
+    memcpy(&arduino_event.event_info.wifi_ap_staconnected, event_data, sizeof(wifi_event_ap_staconnected_t));
+    setStatusBits(ESP_NETIF_CONNECTED_BIT);
+  } else if (event_id == WIFI_EVENT_AP_STADISCONNECTED) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    wifi_event_ap_stadisconnected_t *event = (wifi_event_ap_stadisconnected_t *)event_data;
+    log_v("AP Station Disconnected: MAC: " MACSTR ", AID: %d", MAC2STR(event->mac), event->aid);
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_AP_STADISCONNECTED;
+    memcpy(&arduino_event.event_info.wifi_ap_stadisconnected, event_data, sizeof(wifi_event_ap_stadisconnected_t));
+    // If no more clients are left
+    wifi_sta_list_t clients;
+    if (esp_wifi_ap_get_sta_list(&clients) != ESP_OK || clients.num == 0) {
+      clearStatusBits(ESP_NETIF_CONNECTED_BIT);
+    }
+  } else {
+    return;
+  }
+
+  if (arduino_event.event_id < ARDUINO_EVENT_MAX) {
+    Network.postEvent(&arduino_event);
+  }
+}
+
+APClass::APClass() : _wifi_ap_event_handle(0) {
+  _ap_network_if = this;
+}
+
+APClass::~APClass() {
+  end();
+  _ap_network_if = NULL;
+}
+
+bool APClass::onEnable() {
+  if (_ap_ev_instance == NULL && esp_event_handler_instance_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &_ap_event_cb, this, &_ap_ev_instance)) {
+    log_e("event_handler_instance_register for WIFI_EVENT Failed!");
+    return false;
+  }
+  if (_esp_netif == NULL) {
+    _wifi_ap_event_handle = Network.onSysEvent(_onApArduinoEvent);
+    _esp_netif = get_esp_interface_netif(ESP_IF_WIFI_AP);
+    /* attach to receive events */
+    initNetif(ESP_NETIF_ID_AP);
+  }
+  return true;
+}
+
+bool APClass::onDisable() {
+  Network.removeEvent(_wifi_ap_event_handle);
+  _wifi_ap_event_handle = 0;
+  // we just set _esp_netif to NULL here, so destroyNetif() does not try to destroy it.
+  // That would be done by WiFi.enableAP(false) if STA is not enabled, or when it gets disabled
+  _esp_netif = NULL;
+  destroyNetif();
+  if (_ap_ev_instance != NULL) {
+    esp_event_handler_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, &_ap_event_cb);
+    _ap_ev_instance = NULL;
+  }
+  return true;
+}
+
+bool APClass::begin() {
+  if (!WiFi.enableAP(true)) {
+    log_e("AP enable failed!");
+    return false;
+  }
+  if (!waitStatusBits(ESP_NETIF_STARTED_BIT, 1000)) {
+    log_e("Failed to start AP!");
+    return false;
+  }
+  return true;
+}
+
+bool APClass::end() {
+  if (!WiFi.enableAP(false)) {
+    log_e("AP disable failed!");
+    return false;
+  }
+  return true;
+}
+
+bool APClass::create(
+  const char *ssid, const char *passphrase, int channel, int ssid_hidden, int max_connection, bool ftm_responder, wifi_auth_mode_t auth_mode,
+  wifi_cipher_type_t cipher
+) {
+  if (!ssid || *ssid == 0) {
+    log_e("SSID missing!");
+    return false;
+  }
+
+  if (passphrase && (strlen(passphrase) > 0 && strlen(passphrase) < 8)) {
+    log_e("passphrase too short!");
+    return false;
+  }
+
+  if (!begin()) {
+    return false;
+  }
+
+  wifi_config_t conf;
+  memset(&conf, 0, sizeof(wifi_config_t));
+  conf.ap.channel = channel;
+  conf.ap.max_connection = max_connection;
+  conf.ap.beacon_interval = 100;
+  conf.ap.ssid_hidden = ssid_hidden;
+  conf.ap.ftm_responder = ftm_responder;
+  if (ssid != NULL && ssid[0] != 0) {
+    _wifi_strncpy((char *)conf.ap.ssid, ssid, 32);
+    conf.ap.ssid_len = strlen(ssid);
+    if (passphrase != NULL && passphrase[0] != 0) {
+      conf.ap.authmode = auth_mode;
+      conf.ap.pairwise_cipher = cipher;
+      _wifi_strncpy((char *)conf.ap.password, passphrase, 64);
+    }
+  }
+
+  wifi_config_t conf_current;
+  esp_err_t err = esp_wifi_get_config(WIFI_IF_AP, &conf_current);
+  if (err) {
+    log_e("Get AP config failed! 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+  if (!softap_config_equal(conf, conf_current)) {
+    err = esp_wifi_set_config(WIFI_IF_AP, &conf);
+    if (err) {
+      log_e("Set AP config failed! 0x%x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+  }
+
+  return true;
+}
+
+bool APClass::clear() {
+  if (!begin()) {
+    return false;
+  }
+  wifi_config_t conf;
+  memset(&conf, 0, sizeof(wifi_config_t));
+  conf.ap.channel = 1;
+  conf.ap.max_connection = 4;
+  conf.ap.beacon_interval = 100;
+  esp_err_t err = esp_wifi_set_config(WIFI_IF_AP, &conf);
+  if (err) {
+    log_e("Set AP config failed! 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return true;
+}
+
+bool APClass::bandwidth(wifi_bandwidth_t bandwidth) {
+  if (!begin()) {
+    return false;
+  }
+  esp_err_t err = esp_wifi_set_bandwidth(WIFI_IF_AP, bandwidth);
+  if (err) {
+    log_e("Could not set AP bandwidth! 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  return true;
+}
+
+bool APClass::enableNAPT(bool enable) {
+  if (!started()) {
+    log_e("AP must be first started to enable/disable NAPT");
+    return false;
+  }
+  esp_err_t err = ESP_OK;
+  if (enable) {
+    err = esp_netif_napt_enable(_esp_netif);
+  } else {
+    err = esp_netif_napt_disable(_esp_netif);
+  }
+  if (err) {
+    log_e("Could not set enable/disable NAPT! 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return true;
+}
+
+String APClass::SSID(void) const {
+  if (!started()) {
+    return String();
+  }
+  wifi_config_t info;
+  if (!esp_wifi_get_config(WIFI_IF_AP, &info)) {
+    return String(reinterpret_cast<char *>(info.ap.ssid));
+  }
+  return String();
+}
+
+uint8_t APClass::stationCount() {
+  wifi_sta_list_t clients;
+  if (!started()) {
+    return 0;
+  }
+  if (esp_wifi_ap_get_sta_list(&clients) == ESP_OK) {
+    return clients.num;
+  }
+  return 0;
+}
+
+size_t APClass::printDriverInfo(Print &out) const {
+  size_t bytes = 0;
+  wifi_config_t info;
+  wifi_sta_list_t clients;
+  if (!started()) {
+    return bytes;
+  }
+  if (esp_wifi_get_config(WIFI_IF_AP, &info) != ESP_OK) {
+    return bytes;
+  }
+  bytes += out.print(",");
+  bytes += out.print((const char *)info.ap.ssid);
+  bytes += out.print(",CH:");
+  bytes += out.print(info.ap.channel);
+
+  if (info.ap.authmode == WIFI_AUTH_OPEN) {
+    bytes += out.print(",OPEN");
+  } else if (info.ap.authmode == WIFI_AUTH_WEP) {
+    bytes += out.print(",WEP");
+  } else if (info.ap.authmode == WIFI_AUTH_WPA_PSK) {
+    bytes += out.print(",WPA_PSK");
+  } else if (info.ap.authmode == WIFI_AUTH_WPA2_PSK) {
+    bytes += out.print(",WPA2_PSK");
+  } else if (info.ap.authmode == WIFI_AUTH_WPA_WPA2_PSK) {
+    bytes += out.print(",WPA_WPA2_PSK");
+  } else if (info.ap.authmode == WIFI_AUTH_ENTERPRISE) {
+    bytes += out.print(",WEAP");
+  } else if (info.ap.authmode == WIFI_AUTH_WPA3_PSK) {
+    bytes += out.print(",WPA3_PSK");
+  } else if (info.ap.authmode == WIFI_AUTH_WPA2_WPA3_PSK) {
+    bytes += out.print(",WPA2_WPA3_PSK");
+  } else if (info.ap.authmode == WIFI_AUTH_WAPI_PSK) {
+    bytes += out.print(",WAPI_PSK");
+  } else if (info.ap.authmode == WIFI_AUTH_OWE) {
+    bytes += out.print(",OWE");
+  } else if (info.ap.authmode == WIFI_AUTH_WPA3_ENT_192) {
+    bytes += out.print(",WPA3_ENT_SUITE_B_192_BIT");
+  }
+
+  if (esp_wifi_ap_get_sta_list(&clients) == ESP_OK) {
+    bytes += out.print(",STA:");
+    bytes += out.print(clients.num);
+  }
+  return bytes;
+}
+
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/ETH.cpp b/libraries/WiFi/src/ETH.cpp
deleted file mode 100644
index d3ee9a670e4..00000000000
--- a/libraries/WiFi/src/ETH.cpp
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- ETH.h - espre ETH PHY support.
- Based on WiFi.h from Arduino WiFi shield library.
- Copyright (c) 2011-2014 Arduino.  All right reserved.
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include "ETH.h"
-#include "eth_phy/phy.h"
-#include "eth_phy/phy_tlk110.h"
-#include "eth_phy/phy_lan8720.h"
-#include "lwip/err.h"
-#include "lwip/dns.h"
-
-extern void tcpipInit();
-
-static int _eth_phy_mdc_pin = -1;
-static int _eth_phy_mdio_pin = -1;
-static int _eth_phy_power_pin = -1;
-static eth_phy_power_enable_func _eth_phy_power_enable_orig = NULL;
-
-static void _eth_phy_config_gpio(void)
-{
-    if(_eth_phy_mdc_pin < 0 || _eth_phy_mdio_pin < 0){
-        log_e("MDC and MDIO pins are not configured!");
-        return;
-    }
-    phy_rmii_configure_data_interface_pins();
-    phy_rmii_smi_configure_pins(_eth_phy_mdc_pin, _eth_phy_mdio_pin);
-}
-
-static void _eth_phy_power_enable(bool enable)
-{
-    pinMode(_eth_phy_power_pin, OUTPUT);
-    digitalWrite(_eth_phy_power_pin, enable);
-    delay(1);
-}
-
-ETHClass::ETHClass():initialized(false),started(false),staticIP(false)
-{
-}
-
-ETHClass::~ETHClass()
-{}
-
-bool ETHClass::begin(uint8_t phy_addr, int power, int mdc, int mdio, eth_phy_type_t type, eth_clock_mode_t clock_mode)
-{
-    esp_err_t err;
-    if(initialized){
-        err = esp_eth_enable();
-        if(err){
-            log_e("esp_eth_enable error: %d", err);
-            return false;
-        }
-        started = true;
-        return true;
-    }
-    _eth_phy_mdc_pin = mdc;
-    _eth_phy_mdio_pin = mdio;
-    _eth_phy_power_pin = power;
-
-    if(type == ETH_PHY_LAN8720){
-        eth_config_t config = phy_lan8720_default_ethernet_config;
-        memcpy(&eth_config, &config, sizeof(eth_config_t));
-    } else if(type == ETH_PHY_TLK110){
-        eth_config_t config = phy_tlk110_default_ethernet_config;
-        memcpy(&eth_config, &config, sizeof(eth_config_t));
-    } else {
-        log_e("Bad ETH_PHY type: %u", (uint8_t)type);
-        return false;
-    }
-
-    eth_config.phy_addr = (eth_phy_base_t)phy_addr;
-    eth_config.clock_mode = clock_mode;
-    eth_config.gpio_config = _eth_phy_config_gpio;
-    eth_config.tcpip_input = tcpip_adapter_eth_input;
-    if(_eth_phy_power_pin >= 0){
-        _eth_phy_power_enable_orig = eth_config.phy_power_enable;
-        eth_config.phy_power_enable = _eth_phy_power_enable;
-    }
-
-    tcpipInit();
-    err = esp_eth_init(&eth_config);
-    if(!err){
-        initialized = true;
-        err = esp_eth_enable();
-        if(err){
-            log_e("esp_eth_enable error: %d", err);
-        } else {
-            started = true;
-            return true;
-        }
-    } else {
-        log_e("esp_eth_init error: %d", err);
-    }
-    return false;
-}
-
-bool ETHClass::config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1, IPAddress dns2)
-{
-    esp_err_t err = ESP_OK;
-    tcpip_adapter_ip_info_t info;
-	
-    if(local_ip != (uint32_t)0x00000000){
-        info.ip.addr = static_cast<uint32_t>(local_ip);
-        info.gw.addr = static_cast<uint32_t>(gateway);
-        info.netmask.addr = static_cast<uint32_t>(subnet);
-    } else {
-        info.ip.addr = 0;
-        info.gw.addr = 0;
-        info.netmask.addr = 0;
-	}
-
-    err = tcpip_adapter_dhcpc_stop(TCPIP_ADAPTER_IF_ETH);
-    if(err != ESP_OK && err != ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPPED){
-        log_e("DHCP could not be stopped! Error: %d", err);
-        return false;
-    }
-
-    err = tcpip_adapter_set_ip_info(TCPIP_ADAPTER_IF_ETH, &info);
-    if(err != ERR_OK){
-        log_e("STA IP could not be configured! Error: %d", err);
-        return false;
-}
-    if(info.ip.addr){
-        staticIP = true;
-    } else {
-        err = tcpip_adapter_dhcpc_start(TCPIP_ADAPTER_IF_ETH);
-        if(err != ESP_OK && err != ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED){
-            log_w("DHCP could not be started! Error: %d", err);
-            return false;
-        }
-        staticIP = false;
-    }
-
-    ip_addr_t d;
-    d.type = IPADDR_TYPE_V4;
-
-    if(dns1 != (uint32_t)0x00000000) {
-        // Set DNS1-Server
-        d.u_addr.ip4.addr = static_cast<uint32_t>(dns1);
-        dns_setserver(0, &d);
-    }
-
-    if(dns2 != (uint32_t)0x00000000) {
-        // Set DNS2-Server
-        d.u_addr.ip4.addr = static_cast<uint32_t>(dns2);
-        dns_setserver(1, &d);
-    }
-
-    return true;
-}
-
-IPAddress ETHClass::localIP()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_ETH, &ip)){
-        return IPAddress();
-    }
-    return IPAddress(ip.ip.addr);
-}
-
-IPAddress ETHClass::subnetMask()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_ETH, &ip)){
-        return IPAddress();
-    }
-    return IPAddress(ip.netmask.addr);
-}
-
-IPAddress ETHClass::gatewayIP()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_ETH, &ip)){
-        return IPAddress();
-    }
-    return IPAddress(ip.gw.addr);
-}
-
-IPAddress ETHClass::dnsIP(uint8_t dns_no)
-{
-    const ip_addr_t* dns_ip = dns_getserver(dns_no);
-    return IPAddress(dns_ip->u_addr.ip4.addr);
-}
-
-IPAddress ETHClass::broadcastIP()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_ETH, &ip)){
-        return IPAddress();
-    }
-    return WiFiGenericClass::calculateBroadcast(IPAddress(ip.gw.addr), IPAddress(ip.netmask.addr));
-}
-
-IPAddress ETHClass::networkID()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_ETH, &ip)){
-        return IPAddress();
-    }
-    return WiFiGenericClass::calculateNetworkID(IPAddress(ip.gw.addr), IPAddress(ip.netmask.addr));
-}
-
-uint8_t ETHClass::subnetCIDR()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_ETH, &ip)){
-        return (uint8_t)0;
-    }
-    return WiFiGenericClass::calculateSubnetCIDR(IPAddress(ip.netmask.addr));
-}
-
-const char * ETHClass::getHostname()
-{
-    const char * hostname;
-    if(tcpip_adapter_get_hostname(TCPIP_ADAPTER_IF_ETH, &hostname)){
-        return NULL;
-    }
-    return hostname;
-}
-
-bool ETHClass::setHostname(const char * hostname)
-{
-    return tcpip_adapter_set_hostname(TCPIP_ADAPTER_IF_ETH, hostname) == 0;
-}
-
-bool ETHClass::fullDuplex()
-{
-    return eth_config.phy_get_duplex_mode();
-}
-
-bool ETHClass::linkUp()
-{
-    return eth_config.phy_check_link();
-}
-
-uint8_t ETHClass::linkSpeed()
-{
-    return eth_config.phy_get_speed_mode()?100:10;
-}
-
-bool ETHClass::enableIpV6()
-{
-    return tcpip_adapter_create_ip6_linklocal(TCPIP_ADAPTER_IF_ETH) == 0;
-}
-
-IPv6Address ETHClass::localIPv6()
-{
-    static ip6_addr_t addr;
-    if(tcpip_adapter_get_ip6_linklocal(TCPIP_ADAPTER_IF_ETH, &addr)){
-        return IPv6Address();
-    }
-    return IPv6Address(addr.addr);
-}
-
-uint8_t * macAddress(uint8_t* mac)
-{
-    if(!mac){
-        return NULL;
-    }
-    esp_eth_get_mac(mac);
-    return mac;
-}
-
-String ETHClass::macAddress(void)
-{
-    uint8_t mac[6];
-    char macStr[18] = { 0 };
-    esp_eth_get_mac(mac);
-    sprintf(macStr, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-    return String(macStr);
-}
-
-ETHClass ETH;
diff --git a/libraries/WiFi/src/ETH.h b/libraries/WiFi/src/ETH.h
deleted file mode 100644
index f5441a9d0ed..00000000000
--- a/libraries/WiFi/src/ETH.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- ETH.h - espre ETH PHY support.
- Based on WiFi.h from Ardiono WiFi shield library.
- Copyright (c) 2011-2014 Arduino.  All right reserved.
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef _ETH_H_
-#define _ETH_H_
-
-#include "WiFi.h"
-#include "esp_eth.h"
-
-#ifndef ETH_PHY_ADDR
-#define ETH_PHY_ADDR 0
-#endif
-
-#ifndef ETH_PHY_TYPE
-#define ETH_PHY_TYPE ETH_PHY_LAN8720
-#endif
-
-#ifndef ETH_PHY_POWER
-#define ETH_PHY_POWER -1
-#endif
-
-#ifndef ETH_PHY_MDC
-#define ETH_PHY_MDC 23
-#endif
-
-#ifndef ETH_PHY_MDIO
-#define ETH_PHY_MDIO 18
-#endif
-
-#ifndef ETH_CLK_MODE
-#define ETH_CLK_MODE ETH_CLOCK_GPIO0_IN
-#endif
-
-typedef enum { ETH_PHY_LAN8720, ETH_PHY_TLK110, ETH_PHY_MAX } eth_phy_type_t;
-
-class ETHClass {
-    private:
-        bool initialized;
-        bool started;
-        bool staticIP;
-        eth_config_t eth_config;
-    public:
-        ETHClass();
-        ~ETHClass();
-
-        bool begin(uint8_t phy_addr=ETH_PHY_ADDR, int power=ETH_PHY_POWER, int mdc=ETH_PHY_MDC, int mdio=ETH_PHY_MDIO, eth_phy_type_t type=ETH_PHY_TYPE, eth_clock_mode_t clk_mode=ETH_CLK_MODE);
-
-        bool config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1 = (uint32_t)0x00000000, IPAddress dns2 = (uint32_t)0x00000000);
-
-        const char * getHostname();
-        bool setHostname(const char * hostname);
-
-        bool fullDuplex();
-        bool linkUp();
-        uint8_t linkSpeed();
-
-        bool enableIpV6();
-        IPv6Address localIPv6();
-
-        IPAddress localIP();
-        IPAddress subnetMask();
-        IPAddress gatewayIP();
-        IPAddress dnsIP(uint8_t dns_no = 0);
-
-        IPAddress broadcastIP();
-        IPAddress networkID();
-        uint8_t subnetCIDR();
-
-        uint8_t * macAddress(uint8_t* mac);
-        String macAddress();
-
-        friend class WiFiClient;
-        friend class WiFiServer;
-};
-
-extern ETHClass ETH;
-
-#endif /* _ETH_H_ */
diff --git a/libraries/WiFi/src/STA.cpp b/libraries/WiFi/src/STA.cpp
new file mode 100644
index 00000000000..84258589b28
--- /dev/null
+++ b/libraries/WiFi/src/STA.cpp
@@ -0,0 +1,805 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "WiFi.h"
+#include "WiFiGeneric.h"
+#include "WiFiSTA.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+#include <string.h>
+#include <esp_err.h>
+#include <esp_wifi.h>
+#include <esp_event.h>
+#include <esp32-hal.h>
+#include <lwip/ip_addr.h>
+#include "lwip/err.h"
+#include "lwip/dns.h"
+#include <esp_smartconfig.h>
+#include <esp_netif.h>
+#include "esp_mac.h"
+
+#if __has_include("esp_eap_client.h")
+#include "esp_eap_client.h"
+#else
+#include "esp_wpa2.h"
+#endif
+
+esp_netif_t *get_esp_interface_netif(esp_interface_t interface);
+
+static size_t _wifi_strncpy(char *dst, const char *src, size_t dst_len) {
+  if (!dst || !src || !dst_len) {
+    return 0;
+  }
+  size_t src_len = strlen(src);
+  if (src_len >= dst_len) {
+    src_len = dst_len;
+  } else {
+    src_len += 1;
+  }
+  memcpy(dst, src, src_len);
+  return src_len;
+}
+
+static STAClass *_sta_network_if = NULL;
+
+static esp_event_handler_instance_t _sta_ev_instance = NULL;
+static void _sta_event_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  if (event_base == WIFI_EVENT) {
+    ((STAClass *)arg)->_onStaEvent(event_id, event_data);
+  }
+}
+
+static bool _is_staReconnectableReason(uint8_t reason) {
+  switch (reason) {
+    case WIFI_REASON_UNSPECIFIED:
+    //Timeouts (retry)
+    case WIFI_REASON_AUTH_EXPIRE:
+    case WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT:
+    case WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT:
+    case WIFI_REASON_802_1X_AUTH_FAILED:
+    case WIFI_REASON_HANDSHAKE_TIMEOUT:
+    //Transient error (reconnect)
+    case WIFI_REASON_AUTH_LEAVE:
+    case WIFI_REASON_ASSOC_EXPIRE:
+    case WIFI_REASON_ASSOC_TOOMANY:
+    case WIFI_REASON_NOT_AUTHED:
+    case WIFI_REASON_NOT_ASSOCED:
+    case WIFI_REASON_ASSOC_NOT_AUTHED:
+    case WIFI_REASON_MIC_FAILURE:
+    case WIFI_REASON_IE_IN_4WAY_DIFFERS:
+    case WIFI_REASON_INVALID_PMKID:
+    case WIFI_REASON_BEACON_TIMEOUT:
+    case WIFI_REASON_NO_AP_FOUND:
+    case WIFI_REASON_ASSOC_FAIL:
+    case WIFI_REASON_CONNECTION_FAIL:
+    case WIFI_REASON_AP_TSF_RESET:
+    case WIFI_REASON_ROAMING:            return true;
+    default:                             return false;
+  }
+}
+
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+static const char *auth_mode_str(int authmode) {
+  switch (authmode) {
+    case WIFI_AUTH_OPEN:            return ("OPEN"); break;
+    case WIFI_AUTH_WEP:             return ("WEP"); break;
+    case WIFI_AUTH_WPA_PSK:         return ("WPA_PSK"); break;
+    case WIFI_AUTH_WPA2_PSK:        return ("WPA2_PSK"); break;
+    case WIFI_AUTH_WPA_WPA2_PSK:    return ("WPA_WPA2_PSK"); break;
+    case WIFI_AUTH_WPA2_ENTERPRISE: return ("WPA2_ENTERPRISE"); break;
+    case WIFI_AUTH_WPA3_PSK:        return ("WPA3_PSK"); break;
+    case WIFI_AUTH_WPA2_WPA3_PSK:   return ("WPA2_WPA3_PSK"); break;
+    case WIFI_AUTH_WAPI_PSK:        return ("WPAPI_PSK"); break;
+    default:                        break;
+  }
+  return ("UNKNOWN");
+}
+#endif
+
+static void _onStaArduinoEvent(arduino_event_t *ev) {
+  if (_sta_network_if == NULL || ev->event_id < ARDUINO_EVENT_WIFI_STA_START || ev->event_id > ARDUINO_EVENT_WIFI_STA_LOST_IP) {
+    return;
+  }
+  static bool first_connect = true;
+  log_v("Arduino STA Event: %d - %s", ev->event_id, Network.eventName(ev->event_id));
+
+  if (ev->event_id == ARDUINO_EVENT_WIFI_STA_START) {
+    _sta_network_if->_setStatus(WL_DISCONNECTED);
+    if (esp_wifi_set_ps(WiFi.getSleep()) != ESP_OK) {
+      log_e("esp_wifi_set_ps failed");
+    }
+  } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_STOP) {
+    _sta_network_if->_setStatus(WL_STOPPED);
+  } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_CONNECTED) {
+    _sta_network_if->_setStatus(WL_IDLE_STATUS);
+#if CONFIG_LWIP_IPV6
+    if (_sta_network_if->getStatusBits() & ESP_NETIF_WANT_IP6_BIT) {
+      esp_err_t err = esp_netif_create_ip6_linklocal(_sta_network_if->netif());
+      if (err != ESP_OK) {
+        log_e("Failed to enable IPv6 Link Local on STA:  0x%x: %s", err, esp_err_to_name(err));
+      } else {
+        log_v("Enabled IPv6 Link Local on %s", _sta_network_if->desc());
+      }
+    }
+#endif
+  } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_DISCONNECTED) {
+    uint8_t reason = ev->event_info.wifi_sta_disconnected.reason;
+    // Reason 0 causes crash, use reason 1 (UNSPECIFIED) instead
+    if (!reason) {
+      reason = WIFI_REASON_UNSPECIFIED;
+    }
+    log_w("Reason: %u - %s", reason, WiFi.STA.disconnectReasonName((wifi_err_reason_t)reason));
+    if (reason == WIFI_REASON_NO_AP_FOUND) {
+      _sta_network_if->_setStatus(WL_NO_SSID_AVAIL);
+    } else if ((reason == WIFI_REASON_AUTH_FAIL) && !first_connect) {
+      _sta_network_if->_setStatus(WL_CONNECT_FAILED);
+    } else if (reason == WIFI_REASON_BEACON_TIMEOUT || reason == WIFI_REASON_HANDSHAKE_TIMEOUT) {
+      _sta_network_if->_setStatus(WL_CONNECTION_LOST);
+    } else if (reason == WIFI_REASON_AUTH_EXPIRE) {
+
+    } else {
+      _sta_network_if->_setStatus(WL_DISCONNECTED);
+    }
+
+    bool DoReconnect = false;
+    if (reason == WIFI_REASON_ASSOC_LEAVE) {  //Voluntarily disconnected. Don't reconnect!
+    } else if (first_connect) {               //Retry once for all failure reasons
+      first_connect = false;
+      DoReconnect = true;
+      log_d("WiFi Reconnect Running");
+    } else if (_sta_network_if->getAutoReconnect() && _is_staReconnectableReason(reason)) {
+      DoReconnect = true;
+      log_d("WiFi AutoReconnect Running");
+    } else if (reason == WIFI_REASON_ASSOC_FAIL) {
+      _sta_network_if->_setStatus(WL_CONNECT_FAILED);
+    }
+    if (DoReconnect) {
+      _sta_network_if->disconnect();
+      _sta_network_if->connect();
+    }
+  } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_GOT_IP) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    uint8_t *ip = (uint8_t *)&(ev->event_info.got_ip.ip_info.ip.addr);
+    uint8_t *mask = (uint8_t *)&(ev->event_info.got_ip.ip_info.netmask.addr);
+    uint8_t *gw = (uint8_t *)&(ev->event_info.got_ip.ip_info.gw.addr);
+    log_v(
+      "STA IP: %u.%u.%u.%u, MASK: %u.%u.%u.%u, GW: %u.%u.%u.%u", ip[0], ip[1], ip[2], ip[3], mask[0], mask[1], mask[2], mask[3], gw[0], gw[1], gw[2], gw[3]
+    );
+#endif
+    _sta_network_if->_setStatus(WL_CONNECTED);
+  } else if (ev->event_id == ARDUINO_EVENT_WIFI_STA_LOST_IP) {
+    _sta_network_if->_setStatus(WL_IDLE_STATUS);
+  }
+}
+
+void STAClass::_onStaEvent(int32_t event_id, void *event_data) {
+  arduino_event_t arduino_event;
+  arduino_event.event_id = ARDUINO_EVENT_MAX;
+
+  if (event_id == WIFI_EVENT_STA_START) {
+    log_v("STA Started");
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_START;
+    setStatusBits(ESP_NETIF_STARTED_BIT);
+  } else if (event_id == WIFI_EVENT_STA_STOP) {
+    log_v("STA Stopped");
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_STOP;
+    clearStatusBits(
+      ESP_NETIF_STARTED_BIT | ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT
+      | ESP_NETIF_HAS_STATIC_IP_BIT
+    );
+  } else if (event_id == WIFI_EVENT_STA_AUTHMODE_CHANGE) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    wifi_event_sta_authmode_change_t *event = (wifi_event_sta_authmode_change_t *)event_data;
+    log_v("STA Auth Mode Changed: From: %s, To: %s", auth_mode_str(event->old_mode), auth_mode_str(event->new_mode));
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE;
+    memcpy(&arduino_event.event_info.wifi_sta_authmode_change, event_data, sizeof(wifi_event_sta_authmode_change_t));
+  } else if (event_id == WIFI_EVENT_STA_CONNECTED) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    wifi_event_sta_connected_t *event = (wifi_event_sta_connected_t *)event_data;
+    log_v(
+      "STA Connected: SSID: %s, BSSID: " MACSTR ", Channel: %u, Auth: %s", event->ssid, MAC2STR(event->bssid), event->channel, auth_mode_str(event->authmode)
+    );
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_CONNECTED;
+    memcpy(&arduino_event.event_info.wifi_sta_connected, event_data, sizeof(wifi_event_sta_connected_t));
+    setStatusBits(ESP_NETIF_CONNECTED_BIT);
+  } else if (event_id == WIFI_EVENT_STA_DISCONNECTED) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    wifi_event_sta_disconnected_t *event = (wifi_event_sta_disconnected_t *)event_data;
+    log_v("STA Disconnected: SSID: %s, BSSID: " MACSTR ", Reason: %u", event->ssid, MAC2STR(event->bssid), event->reason);
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_STA_DISCONNECTED;
+    memcpy(&arduino_event.event_info.wifi_sta_disconnected, event_data, sizeof(wifi_event_sta_disconnected_t));
+    clearStatusBits(ESP_NETIF_CONNECTED_BIT | ESP_NETIF_HAS_IP_BIT | ESP_NETIF_HAS_LOCAL_IP6_BIT | ESP_NETIF_HAS_GLOBAL_IP6_BIT);
+  } else {
+    return;
+  }
+
+  if (arduino_event.event_id < ARDUINO_EVENT_MAX) {
+    Network.postEvent(&arduino_event);
+  }
+}
+
+STAClass::STAClass()
+  : _minSecurity(WIFI_AUTH_WPA2_PSK), _scanMethod(WIFI_FAST_SCAN), _sortMethod(WIFI_CONNECT_AP_BY_SIGNAL), _autoReconnect(true), _status(WL_STOPPED),
+    _wifi_sta_event_handle(0) {
+  _sta_network_if = this;
+}
+
+STAClass::~STAClass() {
+  end();
+  _sta_network_if = NULL;
+}
+
+wl_status_t STAClass::status() {
+  return _status;
+}
+
+void STAClass::_setStatus(wl_status_t status) {
+  _status = status;
+}
+
+/**
+ * Sets the working bandwidth of the STA mode
+ * @param m wifi_bandwidth_t
+ */
+bool STAClass::bandwidth(wifi_bandwidth_t bandwidth) {
+  if (!begin()) {
+    return false;
+  }
+
+  esp_err_t err;
+  err = esp_wifi_set_bandwidth(WIFI_IF_STA, bandwidth);
+  if (err) {
+    log_e("Could not set STA bandwidth! 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  return true;
+}
+
+bool STAClass::onEnable() {
+  if (_sta_ev_instance == NULL && esp_event_handler_instance_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &_sta_event_cb, this, &_sta_ev_instance)) {
+    log_e("event_handler_instance_register for WIFI_EVENT Failed!");
+    return false;
+  }
+  if (_esp_netif == NULL) {
+    _esp_netif = get_esp_interface_netif(ESP_IF_WIFI_STA);
+    if (_esp_netif == NULL) {
+      log_e("STA was enabled, but netif is NULL???");
+      return false;
+    }
+    /* attach to receive events */
+    _wifi_sta_event_handle = Network.onSysEvent(_onStaArduinoEvent);
+    initNetif(ESP_NETIF_ID_STA);
+  }
+  return true;
+}
+
+bool STAClass::onDisable() {
+  Network.removeEvent(_wifi_sta_event_handle);
+  _wifi_sta_event_handle = 0;
+  // we just set _esp_netif to NULL here, so destroyNetif() does not try to destroy it.
+  // That would be done by WiFi.enableSTA(false) if AP is not enabled, or when it gets disabled
+  _esp_netif = NULL;
+  destroyNetif();
+  if (_sta_ev_instance != NULL) {
+    esp_event_handler_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, &_sta_event_cb);
+    _sta_ev_instance = NULL;
+  }
+  return true;
+}
+
+bool STAClass::begin(bool tryConnect) {
+  if (!WiFi.enableSTA(true)) {
+    log_e("STA enable failed!");
+    return false;
+  }
+  if (!waitStatusBits(ESP_NETIF_STARTED_BIT, 1000)) {
+    log_e("Failed to start STA!");
+    return false;
+  }
+  if (tryConnect) {
+    return connect();
+  }
+  return true;
+}
+
+bool STAClass::end() {
+  if (!WiFi.enableSTA(false)) {
+    log_e("STA disable failed!");
+    return false;
+  }
+  return true;
+}
+
+bool STAClass::connect() {
+  if (_esp_netif == NULL) {
+    log_e("STA not started! You must call begin() first.");
+    return false;
+  }
+
+  if (connected()) {
+    log_w("STA already connected.");
+    return true;
+  }
+
+  wifi_config_t current_conf;
+  if (esp_wifi_get_config(WIFI_IF_STA, &current_conf) != ESP_OK || esp_wifi_set_config(WIFI_IF_STA, &current_conf) != ESP_OK) {
+    log_e("STA config failed");
+    return false;
+  }
+
+  if ((getStatusBits() & ESP_NETIF_HAS_STATIC_IP_BIT) == 0 && !config()) {
+    log_e("STA failed to configure dynamic IP!");
+    return false;
+  }
+
+  esp_err_t err = esp_wifi_connect();
+  if (err) {
+    log_e("STA connect failed! 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return true;
+}
+
+/**
+ * Start Wifi connection
+ * if passphrase is set the most secure supported mode will be automatically selected
+ * @param ssid const char*          Pointer to the SSID string.
+ * @param passphrase const char *   Optional. Passphrase. Valid characters in a passphrase must be between ASCII 32-126 (decimal).
+ * @param bssid uint8_t[6]          Optional. BSSID / MAC of AP
+ * @param channel                   Optional. Channel of AP
+ * @param connect                   Optional. call connect
+ * @return
+ */
+bool STAClass::connect(const char *ssid, const char *passphrase, int32_t channel, const uint8_t *bssid, bool tryConnect) {
+  if (_esp_netif == NULL) {
+    log_e("STA not started! You must call begin() first.");
+    return false;
+  }
+
+  if (connected()) {
+    log_w("STA currently connected. Disconnecting...");
+    if (!disconnect(true, 1000)) {
+      return false;
+    }
+  }
+
+  if (!ssid || *ssid == 0x00 || strlen(ssid) > 32) {
+    log_e("SSID too long or missing!");
+    return false;
+  }
+
+  if (passphrase && strlen(passphrase) > 64) {
+    log_e("passphrase too long!");
+    return false;
+  }
+
+  wifi_config_t conf;
+  memset(&conf, 0, sizeof(wifi_config_t));
+  conf.sta.channel = channel;
+  conf.sta.scan_method = _scanMethod;
+  conf.sta.sort_method = _sortMethod;
+  conf.sta.threshold.rssi = -127;
+  conf.sta.pmf_cfg.capable = true;
+  if (ssid != NULL && ssid[0] != 0) {
+    _wifi_strncpy((char *)conf.sta.ssid, ssid, 32);
+    if (passphrase != NULL && passphrase[0] != 0) {
+      conf.sta.threshold.authmode = _minSecurity;
+      _wifi_strncpy((char *)conf.sta.password, passphrase, 64);
+    }
+    if (bssid != NULL) {
+      conf.sta.bssid_set = 1;
+      memcpy(conf.sta.bssid, bssid, 6);
+    }
+  }
+
+  esp_err_t err = esp_wifi_set_config(WIFI_IF_STA, &conf);
+  if (err != ESP_OK) {
+    log_e("STA clear config failed! 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  if ((getStatusBits() & ESP_NETIF_HAS_STATIC_IP_BIT) == 0 && !config()) {
+    log_e("STA failed to configure dynamic IP!");
+    return false;
+  }
+
+  if (tryConnect) {
+    esp_err_t err = esp_wifi_connect();
+    if (err) {
+      log_e("STA connect failed! 0x%x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+  }
+  return true;
+}
+
+#if CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT
+/**
+ * Start Wifi connection with a WPA2 Enterprise AP
+ * if passphrase is set the most secure supported mode will be automatically selected
+ * @param ssid const char*          Pointer to the SSID string.
+ * @param method wpa2_method_t      The authentication method of WPA2 (WPA2_AUTH_TLS, WPA2_AUTH_PEAP, WPA2_AUTH_TTLS)
+ * @param wpa2_identity  const char*          Pointer to the entity
+ * @param wpa2_username  const char*          Pointer to the username
+ * @param password const char *     Pointer to the password.
+ * @param ca_pem const char*        Pointer to a string with the contents of a  .pem  file with CA cert
+ * @param client_crt const char*        Pointer to a string with the contents of a .crt file with client cert
+ * @param client_key const char*        Pointer to a string with the contents of a .key file with client key
+ * @param bssid uint8_t[6]          Optional. BSSID / MAC of AP
+ * @param channel                   Optional. Channel of AP
+ * @param connect                   Optional. call connect
+ * @return
+ */
+bool STAClass::connect(
+  const char *wpa2_ssid, wpa2_auth_method_t method, const char *wpa2_identity, const char *wpa2_username, const char *wpa2_password, const char *ca_pem,
+  const char *client_crt, const char *client_key, int ttls_phase2_type, int32_t channel, const uint8_t *bssid, bool tryConnect
+) {
+  if (_esp_netif == NULL) {
+    log_e("STA not started! You must call begin() first.");
+    return false;
+  }
+
+  if (connected()) {
+    log_w("STA currently connected. Disconnecting...");
+    if (!disconnect(true, 1000)) {
+      return false;
+    }
+  }
+
+  if (!wpa2_ssid || *wpa2_ssid == 0x00 || strlen(wpa2_ssid) > 32) {
+    log_e("SSID too long or missing!");
+    return false;
+  }
+
+  if (wpa2_identity && strlen(wpa2_identity) > 64) {
+    log_e("identity too long!");
+    return false;
+  }
+
+  if (wpa2_username && strlen(wpa2_username) > 64) {
+    log_e("username too long!");
+    return false;
+  }
+
+  if (wpa2_password && strlen(wpa2_password) > 64) {
+    log_e("password too long!");
+    return false;
+  }
+
+  if (ttls_phase2_type >= 0) {
+#if __has_include("esp_eap_client.h")
+    esp_eap_client_set_ttls_phase2_method((esp_eap_ttls_phase2_types)ttls_phase2_type);
+#else
+    esp_wifi_sta_wpa2_ent_set_ttls_phase2_method((esp_eap_ttls_phase2_types)ttls_phase2_type);
+#endif
+  }
+
+  if (ca_pem) {
+#if __has_include("esp_eap_client.h")
+    esp_eap_client_set_ca_cert((uint8_t *)ca_pem, strlen(ca_pem));
+#else
+    esp_wifi_sta_wpa2_ent_set_ca_cert((uint8_t *)ca_pem, strlen(ca_pem));
+#endif
+  }
+
+  if (client_crt) {
+#if __has_include("esp_eap_client.h")
+    esp_eap_client_set_certificate_and_key((uint8_t *)client_crt, strlen(client_crt), (uint8_t *)client_key, strlen(client_key), NULL, 0);
+#else
+    esp_wifi_sta_wpa2_ent_set_cert_key((uint8_t *)client_crt, strlen(client_crt), (uint8_t *)client_key, strlen(client_key), NULL, 0);
+#endif
+  }
+
+#if __has_include("esp_eap_client.h")
+  esp_eap_client_set_identity((uint8_t *)wpa2_identity, strlen(wpa2_identity));
+#else
+  esp_wifi_sta_wpa2_ent_set_identity((uint8_t *)wpa2_identity, strlen(wpa2_identity));
+#endif
+  if (method == WPA2_AUTH_PEAP || method == WPA2_AUTH_TTLS) {
+#if __has_include("esp_eap_client.h")
+    esp_eap_client_set_username((uint8_t *)wpa2_username, strlen(wpa2_username));
+    esp_eap_client_set_password((uint8_t *)wpa2_password, strlen(wpa2_password));
+#else
+    esp_wifi_sta_wpa2_ent_set_username((uint8_t *)wpa2_username, strlen(wpa2_username));
+    esp_wifi_sta_wpa2_ent_set_password((uint8_t *)wpa2_password, strlen(wpa2_password));
+#endif
+  }
+#if __has_include("esp_eap_client.h")
+  esp_wifi_sta_enterprise_enable();  //set config settings to enable function
+#else
+  esp_wifi_sta_wpa2_ent_enable();  //set config settings to enable function
+#endif
+
+  return connect(wpa2_ssid, NULL, channel, bssid, tryConnect);  //connect to wifi
+}
+#endif /* CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT */
+
+bool STAClass::disconnect(bool eraseap, unsigned long timeout) {
+  if (eraseap) {
+    if (!started()) {
+      log_e("STA not started! You must call begin first.");
+      return false;
+    }
+    wifi_config_t conf;
+    memset(&conf, 0, sizeof(wifi_config_t));
+    esp_err_t err = esp_wifi_set_config(WIFI_IF_STA, &conf);
+    if (err != ESP_OK) {
+      log_e("STA clear config failed! 0x%x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+  }
+
+  if (!connected()) {
+    log_w("STA already disconnected.");
+    return true;
+  }
+
+  esp_err_t err = esp_wifi_disconnect();
+  if (err != ESP_OK) {
+    log_e("STA disconnect failed! 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  if (timeout) {
+    const unsigned long start = millis();
+    while (connected() && ((millis() - start) < timeout)) {
+      delay(5);
+    }
+    if (connected()) {
+      return false;
+    }
+  }
+
+  return true;
+}
+
+bool STAClass::reconnect() {
+  if (connected()) {
+    if (esp_wifi_disconnect() != ESP_OK) {
+      return false;
+    }
+  }
+  return esp_wifi_connect() == ESP_OK;
+}
+
+bool STAClass::erase() {
+  if (!started()) {
+    log_e("STA not started! You must call begin first.");
+    return false;
+  }
+  return esp_wifi_restore() == ESP_OK;
+}
+
+uint8_t STAClass::waitForConnectResult(unsigned long timeoutLength) {
+  //1 and 3 have STA enabled
+  if ((WiFiGenericClass::getMode() & WIFI_MODE_STA) == 0) {
+    return WL_DISCONNECTED;
+  }
+  unsigned long start = millis();
+  while ((!status() || status() >= WL_DISCONNECTED) && (millis() - start) < timeoutLength) {
+    delay(100);
+  }
+  return status();
+}
+
+bool STAClass::setAutoReconnect(bool autoReconnect) {
+  _autoReconnect = autoReconnect;
+  return true;
+}
+
+bool STAClass::getAutoReconnect() {
+  return _autoReconnect;
+}
+
+void STAClass::setMinSecurity(wifi_auth_mode_t minSecurity) {
+  _minSecurity = minSecurity;
+}
+
+void STAClass::setScanMethod(wifi_scan_method_t scanMethod) {
+  _scanMethod = scanMethod;
+}
+
+void STAClass::setSortMethod(wifi_sort_method_t sortMethod) {
+  _sortMethod = sortMethod;
+}
+
+String STAClass::SSID() const {
+  if (!started()) {
+    return String();
+  }
+  wifi_ap_record_t info;
+  if (!esp_wifi_sta_get_ap_info(&info)) {
+    return String(reinterpret_cast<char *>(info.ssid));
+  }
+  return String();
+}
+
+String STAClass::psk() const {
+  if (!started()) {
+    return String();
+  }
+  wifi_config_t conf;
+  esp_wifi_get_config((wifi_interface_t)ESP_IF_WIFI_STA, &conf);
+  return String(reinterpret_cast<char *>(conf.sta.password));
+}
+
+uint8_t *STAClass::BSSID(uint8_t *buff) {
+  static uint8_t bssid[6];
+  wifi_ap_record_t info;
+  if (!started()) {
+    return NULL;
+  }
+  esp_err_t err = esp_wifi_sta_get_ap_info(&info);
+  if (buff != NULL) {
+    if (err) {
+      memset(buff, 0, 6);
+    } else {
+      memcpy(buff, info.bssid, 6);
+    }
+    return buff;
+  }
+  if (!err) {
+    memcpy(bssid, info.bssid, 6);
+    return reinterpret_cast<uint8_t *>(bssid);
+  }
+  return NULL;
+}
+
+String STAClass::BSSIDstr() {
+  uint8_t *bssid = BSSID();
+  if (!bssid) {
+    return String();
+  }
+  char mac[18] = {0};
+  sprintf(mac, "%02X:%02X:%02X:%02X:%02X:%02X", bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
+  return String(mac);
+}
+
+int8_t STAClass::RSSI() {
+  if (!started()) {
+    return 0;
+  }
+  wifi_ap_record_t info;
+  if (!esp_wifi_sta_get_ap_info(&info)) {
+    return info.rssi;
+  }
+  return 0;
+}
+
+size_t STAClass::printDriverInfo(Print &out) const {
+  size_t bytes = 0;
+  wifi_ap_record_t info;
+  if (!started()) {
+    return bytes;
+  }
+  if (esp_wifi_sta_get_ap_info(&info) != ESP_OK) {
+    return bytes;
+  }
+  bytes += out.print(",");
+  bytes += out.print((const char *)info.ssid);
+  bytes += out.print(",CH:");
+  bytes += out.print(info.primary);
+  bytes += out.print(",RSSI:");
+  bytes += out.print(info.rssi);
+  bytes += out.print(",");
+  if (info.phy_11ax) {
+    bytes += out.print("AX");
+  } else if (info.phy_11n) {
+    bytes += out.print("N");
+  } else if (info.phy_11g) {
+    bytes += out.print("G");
+  } else if (info.phy_11b) {
+    bytes += out.print("B");
+  }
+  if (info.phy_lr) {
+    bytes += out.print(",");
+    bytes += out.print("LR");
+  }
+
+  if (info.authmode == WIFI_AUTH_OPEN) {
+    bytes += out.print(",OPEN");
+  } else if (info.authmode == WIFI_AUTH_WEP) {
+    bytes += out.print(",WEP");
+  } else if (info.authmode == WIFI_AUTH_WPA_PSK) {
+    bytes += out.print(",WPA_PSK");
+  } else if (info.authmode == WIFI_AUTH_WPA2_PSK) {
+    bytes += out.print(",WPA2_PSK");
+  } else if (info.authmode == WIFI_AUTH_WPA_WPA2_PSK) {
+    bytes += out.print(",WPA_WPA2_PSK");
+  } else if (info.authmode == WIFI_AUTH_ENTERPRISE) {
+    bytes += out.print(",EAP");
+  } else if (info.authmode == WIFI_AUTH_WPA3_PSK) {
+    bytes += out.print(",WPA3_PSK");
+  } else if (info.authmode == WIFI_AUTH_WPA2_WPA3_PSK) {
+    bytes += out.print(",WPA2_WPA3_PSK");
+  } else if (info.authmode == WIFI_AUTH_WAPI_PSK) {
+    bytes += out.print(",WAPI_PSK");
+  } else if (info.authmode == WIFI_AUTH_OWE) {
+    bytes += out.print(",OWE");
+  } else if (info.authmode == WIFI_AUTH_WPA3_ENT_192) {
+    bytes += out.print(",WPA3_ENT_SUITE_B_192_BIT");
+  }
+
+  return bytes;
+}
+
+/**
+ * @brief Convert wifi_err_reason_t to a string.
+ * @param [in] reason The reason to be converted.
+ * @return A string representation of the error code.
+ * @note: wifi_err_reason_t values as of Mar 2023 (arduino-esp32 r2.0.7) are: (1-39, 46-51, 67-68, 200-208) and are defined in /tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h.
+ */
+const char *STAClass::disconnectReasonName(wifi_err_reason_t reason) {
+  switch (reason) {
+    //ESP_ARDUINO_VERSION >= ESP_ARDUINO_VERSION_VAL(2,0,7)
+    case WIFI_REASON_UNSPECIFIED:                        return "UNSPECIFIED";
+    case WIFI_REASON_AUTH_EXPIRE:                        return "AUTH_EXPIRE";
+    case WIFI_REASON_AUTH_LEAVE:                         return "AUTH_LEAVE";
+    case WIFI_REASON_ASSOC_EXPIRE:                       return "ASSOC_EXPIRE";
+    case WIFI_REASON_ASSOC_TOOMANY:                      return "ASSOC_TOOMANY";
+    case WIFI_REASON_NOT_AUTHED:                         return "NOT_AUTHED";
+    case WIFI_REASON_NOT_ASSOCED:                        return "NOT_ASSOCED";
+    case WIFI_REASON_ASSOC_LEAVE:                        return "ASSOC_LEAVE";
+    case WIFI_REASON_ASSOC_NOT_AUTHED:                   return "ASSOC_NOT_AUTHED";
+    case WIFI_REASON_DISASSOC_PWRCAP_BAD:                return "DISASSOC_PWRCAP_BAD";
+    case WIFI_REASON_DISASSOC_SUPCHAN_BAD:               return "DISASSOC_SUPCHAN_BAD";
+    case WIFI_REASON_BSS_TRANSITION_DISASSOC:            return "BSS_TRANSITION_DISASSOC";
+    case WIFI_REASON_IE_INVALID:                         return "IE_INVALID";
+    case WIFI_REASON_MIC_FAILURE:                        return "MIC_FAILURE";
+    case WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT:             return "4WAY_HANDSHAKE_TIMEOUT";
+    case WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT:           return "GROUP_KEY_UPDATE_TIMEOUT";
+    case WIFI_REASON_IE_IN_4WAY_DIFFERS:                 return "IE_IN_4WAY_DIFFERS";
+    case WIFI_REASON_GROUP_CIPHER_INVALID:               return "GROUP_CIPHER_INVALID";
+    case WIFI_REASON_PAIRWISE_CIPHER_INVALID:            return "PAIRWISE_CIPHER_INVALID";
+    case WIFI_REASON_AKMP_INVALID:                       return "AKMP_INVALID";
+    case WIFI_REASON_UNSUPP_RSN_IE_VERSION:              return "UNSUPP_RSN_IE_VERSION";
+    case WIFI_REASON_INVALID_RSN_IE_CAP:                 return "INVALID_RSN_IE_CAP";
+    case WIFI_REASON_802_1X_AUTH_FAILED:                 return "802_1X_AUTH_FAILED";
+    case WIFI_REASON_CIPHER_SUITE_REJECTED:              return "CIPHER_SUITE_REJECTED";
+    case WIFI_REASON_TDLS_PEER_UNREACHABLE:              return "TDLS_PEER_UNREACHABLE";
+    case WIFI_REASON_TDLS_UNSPECIFIED:                   return "TDLS_UNSPECIFIED";
+    case WIFI_REASON_SSP_REQUESTED_DISASSOC:             return "SSP_REQUESTED_DISASSOC";
+    case WIFI_REASON_NO_SSP_ROAMING_AGREEMENT:           return "NO_SSP_ROAMING_AGREEMENT";
+    case WIFI_REASON_BAD_CIPHER_OR_AKM:                  return "BAD_CIPHER_OR_AKM";
+    case WIFI_REASON_NOT_AUTHORIZED_THIS_LOCATION:       return "NOT_AUTHORIZED_THIS_LOCATION";
+    case WIFI_REASON_SERVICE_CHANGE_PERCLUDES_TS:        return "SERVICE_CHANGE_PERCLUDES_TS";
+    case WIFI_REASON_UNSPECIFIED_QOS:                    return "UNSPECIFIED_QOS";
+    case WIFI_REASON_NOT_ENOUGH_BANDWIDTH:               return "NOT_ENOUGH_BANDWIDTH";
+    case WIFI_REASON_MISSING_ACKS:                       return "MISSING_ACKS";
+    case WIFI_REASON_EXCEEDED_TXOP:                      return "EXCEEDED_TXOP";
+    case WIFI_REASON_STA_LEAVING:                        return "STA_LEAVING";
+    case WIFI_REASON_END_BA:                             return "END_BA";
+    case WIFI_REASON_UNKNOWN_BA:                         return "UNKNOWN_BA";
+    case WIFI_REASON_TIMEOUT:                            return "TIMEOUT";
+    case WIFI_REASON_PEER_INITIATED:                     return "PEER_INITIATED";
+    case WIFI_REASON_AP_INITIATED:                       return "AP_INITIATED";
+    case WIFI_REASON_INVALID_FT_ACTION_FRAME_COUNT:      return "INVALID_FT_ACTION_FRAME_COUNT";
+    case WIFI_REASON_INVALID_PMKID:                      return "INVALID_PMKID";
+    case WIFI_REASON_INVALID_MDE:                        return "INVALID_MDE";
+    case WIFI_REASON_INVALID_FTE:                        return "INVALID_FTE";
+    case WIFI_REASON_TRANSMISSION_LINK_ESTABLISH_FAILED: return "TRANSMISSION_LINK_ESTABLISH_FAILED";
+    case WIFI_REASON_ALTERATIVE_CHANNEL_OCCUPIED:        return "ALTERATIVE_CHANNEL_OCCUPIED";
+    case WIFI_REASON_BEACON_TIMEOUT:                     return "BEACON_TIMEOUT";
+    case WIFI_REASON_NO_AP_FOUND:                        return "NO_AP_FOUND";
+    case WIFI_REASON_AUTH_FAIL:                          return "AUTH_FAIL";
+    case WIFI_REASON_ASSOC_FAIL:                         return "ASSOC_FAIL";
+    case WIFI_REASON_HANDSHAKE_TIMEOUT:                  return "HANDSHAKE_TIMEOUT";
+    case WIFI_REASON_CONNECTION_FAIL:                    return "CONNECTION_FAIL";
+    case WIFI_REASON_AP_TSF_RESET:                       return "AP_TSF_RESET";
+    case WIFI_REASON_ROAMING:                            return "ROAMING";
+    case WIFI_REASON_ASSOC_COMEBACK_TIME_TOO_LONG:       return "ASSOC_COMEBACK_TIME_TOO_LONG";
+    default:                                             return "";
+  }
+}
+
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFi.cpp b/libraries/WiFi/src/WiFi.cpp
index 44d46ee0b76..7fb0ed16459 100644
--- a/libraries/WiFi/src/WiFi.cpp
+++ b/libraries/WiFi/src/WiFi.cpp
@@ -22,6 +22,7 @@
 
  */
 #include "WiFi.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
 extern "C" {
 #include <stdint.h>
@@ -32,36 +33,33 @@ extern "C" {
 #include <string.h>
 #include <esp_err.h>
 #include <esp_wifi.h>
-#include <esp_event_loop.h>
+#include <esp_event.h>
 }
 
-
 // -----------------------------------------------------------------------------------------------------------------------
 // ---------------------------------------------------------- Debug ------------------------------------------------------
 // -----------------------------------------------------------------------------------------------------------------------
 
-
 /**
  * Output WiFi settings to an object derived from Print interface (like Serial).
  * @param p Print interface
  */
-void WiFiClass::printDiag(Print& p)
-{
-    const char* modes[] = { "NULL", "STA", "AP", "STA+AP" };
+void WiFiClass::printDiag(Print &p) {
+  const char *modes[] = {"NULL", "STA", "AP", "STA+AP"};
 
-    wifi_mode_t mode;
-    esp_wifi_get_mode(&mode);
+  wifi_mode_t mode;
+  esp_wifi_get_mode(&mode);
 
-    uint8_t primaryChan;
-    wifi_second_chan_t secondChan;
-    esp_wifi_get_channel(&primaryChan, &secondChan);
+  uint8_t primaryChan;
+  wifi_second_chan_t secondChan;
+  esp_wifi_get_channel(&primaryChan, &secondChan);
 
-    p.print("Mode: ");
-    p.println(modes[mode]);
+  p.print("Mode: ");
+  p.println(modes[mode]);
 
-    p.print("Channel: ");
-    p.println(primaryChan);
-    /*
+  p.print("Channel: ");
+  p.println(primaryChan);
+  /*
         p.print("AP id: ");
         p.println(wifi_station_get_current_ap_id());
 
@@ -69,33 +67,33 @@ void WiFiClass::printDiag(Print& p)
         p.println(wifi_station_get_connect_status());
     */
 
-    wifi_config_t conf;
-    esp_wifi_get_config(WIFI_IF_STA, &conf);
+  wifi_config_t conf;
+  esp_wifi_get_config((wifi_interface_t)WIFI_IF_STA, &conf);
 
-    const char* ssid = reinterpret_cast<const char*>(conf.sta.ssid);
-    p.print("SSID (");
-    p.print(strlen(ssid));
-    p.print("): ");
-    p.println(ssid);
+  const char *ssid = reinterpret_cast<const char *>(conf.sta.ssid);
+  p.print("SSID (");
+  p.print(strlen(ssid));
+  p.print("): ");
+  p.println(ssid);
 
-    const char* passphrase = reinterpret_cast<const char*>(conf.sta.password);
-    p.print("Passphrase (");
-    p.print(strlen(passphrase));
-    p.print("): ");
-    p.println(passphrase);
+  const char *passphrase = reinterpret_cast<const char *>(conf.sta.password);
+  p.print("Passphrase (");
+  p.print(strlen(passphrase));
+  p.print("): ");
+  p.println(passphrase);
 
-    p.print("BSSID set: ");
-    p.println(conf.sta.bssid_set);
+  p.print("BSSID set: ");
+  p.println(conf.sta.bssid_set);
 }
 
-void WiFiClass::enableProv(bool status)
-{
-    prov_enable = status;
+void WiFiClass::enableProv(bool status) {
+  prov_enable = status;
 }
 
-bool WiFiClass::isProvEnabled()
-{
-    return prov_enable;
+bool WiFiClass::isProvEnabled() {
+  return prov_enable;
 }
 
 WiFiClass WiFi;
+
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFi.h b/libraries/WiFi/src/WiFi.h
index 457f913ae8e..ea2efd97697 100644
--- a/libraries/WiFi/src/WiFi.h
+++ b/libraries/WiFi/src/WiFi.h
@@ -19,14 +19,16 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#ifndef WiFi_h
-#define WiFi_h
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
 #include <stdint.h>
 
 #include "Print.h"
 #include "IPAddress.h"
-#include "IPv6Address.h"
 
 #include "WiFiType.h"
 #include "WiFiSTA.h"
@@ -38,38 +40,38 @@
 #include "WiFiServer.h"
 #include "WiFiUdp.h"
 
-class WiFiClass : public WiFiGenericClass, public WiFiSTAClass, public WiFiScanClass, public WiFiAPClass
-{
+class WiFiClass : public WiFiGenericClass, public WiFiSTAClass, public WiFiScanClass, public WiFiAPClass {
 private:
-    bool prov_enable;
+  bool prov_enable;
+
+public:
+  WiFiClass() {
+    prov_enable = false;
+  }
+
+  using WiFiGenericClass::channel;
+
+  using WiFiSTAClass::BSSID;
+  using WiFiSTAClass::BSSIDstr;
+  using WiFiSTAClass::RSSI;
+  using WiFiSTAClass::SSID;
+
+  using WiFiScanClass::BSSID;
+  using WiFiScanClass::BSSIDstr;
+  using WiFiScanClass::channel;
+  using WiFiScanClass::encryptionType;
+  using WiFiScanClass::RSSI;
+  using WiFiScanClass::SSID;
+
 public:
-    WiFiClass()
-    {
-        prov_enable = false;
-    }
-
-    using WiFiGenericClass::channel;
-
-    using WiFiSTAClass::SSID;
-    using WiFiSTAClass::RSSI;
-    using WiFiSTAClass::BSSID;
-    using WiFiSTAClass::BSSIDstr;
-
-    using WiFiScanClass::SSID;
-    using WiFiScanClass::encryptionType;
-    using WiFiScanClass::RSSI;
-    using WiFiScanClass::BSSID;
-    using WiFiScanClass::BSSIDstr;
-    using WiFiScanClass::channel;
-public:  
-    void printDiag(Print& dest);
-    friend class WiFiClient;
-    friend class WiFiServer;
-    friend class WiFiUDP;
-    void enableProv(bool status);
-    bool isProvEnabled();
+  void printDiag(Print &dest);
+  friend class NetworkClient;
+  friend class NetworkServer;
+  friend class NetworkUDP;
+  void enableProv(bool status);
+  bool isProvEnabled();
 };
 
 extern WiFiClass WiFi;
 
-#endif
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiAP.cpp b/libraries/WiFi/src/WiFiAP.cpp
index 1f8af5852ee..bb15ff44625 100644
--- a/libraries/WiFi/src/WiFiAP.cpp
+++ b/libraries/WiFi/src/WiFiAP.cpp
@@ -25,8 +25,8 @@
 #include "WiFi.h"
 #include "WiFiGeneric.h"
 #include "WiFiAP.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
-extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include <stdio.h>
@@ -35,51 +35,9 @@ extern "C" {
 #include <string.h>
 #include <esp_err.h>
 #include <esp_wifi.h>
-#include <esp_event_loop.h>
+#include <esp_event.h>
 #include <lwip/ip_addr.h>
 #include "dhcpserver/dhcpserver_options.h"
-}
-
-
-
-// -----------------------------------------------------------------------------------------------------------------------
-// ---------------------------------------------------- Private functions ------------------------------------------------
-// -----------------------------------------------------------------------------------------------------------------------
-
-static bool softap_config_equal(const wifi_config_t& lhs, const wifi_config_t& rhs);
-
-
-
-/**
- * compare two AP configurations
- * @param lhs softap_config
- * @param rhs softap_config
- * @return equal
- */
-static bool softap_config_equal(const wifi_config_t& lhs, const wifi_config_t& rhs)
-{
-    if(strcmp(reinterpret_cast<const char*>(lhs.ap.ssid), reinterpret_cast<const char*>(rhs.ap.ssid)) != 0) {
-        return false;
-    }
-    if(strcmp(reinterpret_cast<const char*>(lhs.ap.password), reinterpret_cast<const char*>(rhs.ap.password)) != 0) {
-        return false;
-    }
-    if(lhs.ap.channel != rhs.ap.channel) {
-        return false;
-    }
-    if(lhs.ap.ssid_hidden != rhs.ap.ssid_hidden) {
-        return false;
-    }
-    if(lhs.ap.max_connection != rhs.ap.max_connection) {
-        return false;
-    }
-    return true;
-}
-
-// -----------------------------------------------------------------------------------------------------------------------
-// ----------------------------------------------------- AP function -----------------------------------------------------
-// -----------------------------------------------------------------------------------------------------------------------
-
 
 /**
  * Set up an access point
@@ -89,54 +47,20 @@ static bool softap_config_equal(const wifi_config_t& lhs, const wifi_config_t& r
  * @param ssid_hidden       Network cloaking (0 = broadcast SSID, 1 = hide SSID)
  * @param max_connection    Max simultaneous connected clients, 1 - 4.
 */
-bool WiFiAPClass::softAP(const char* ssid, const char* passphrase, int channel, int ssid_hidden, int max_connection)
-{
-
-    if(!WiFi.enableAP(true)) {
-        // enable AP failed
-        log_e("enable AP first!");
-        return false;
-    }
-
-    if(!ssid || *ssid == 0) {
-        // fail SSID missing
-        log_e("SSID missing!");
-        return false;
-    }
-
-    if(passphrase && (strlen(passphrase) > 0 && strlen(passphrase) < 8)) {
-        // fail passphrase too short
-        log_e("passphrase too short!");
-        return false;
-    }
-
-    esp_wifi_start();
-
-    wifi_config_t conf;
-    strlcpy(reinterpret_cast<char*>(conf.ap.ssid), ssid, sizeof(conf.ap.ssid));
-    conf.ap.channel = channel;
-    conf.ap.ssid_len = strlen(reinterpret_cast<char *>(conf.ap.ssid));
-    conf.ap.ssid_hidden = ssid_hidden;
-    conf.ap.max_connection = max_connection;
-    conf.ap.beacon_interval = 100;
-
-    if(!passphrase || strlen(passphrase) == 0) {
-        conf.ap.authmode = WIFI_AUTH_OPEN;
-        *conf.ap.password = 0;
-    } else {
-        conf.ap.authmode = WIFI_AUTH_WPA2_PSK;
-        strlcpy(reinterpret_cast<char*>(conf.ap.password), passphrase, sizeof(conf.ap.password));
-    }
-
-    wifi_config_t conf_current;
-    esp_wifi_get_config(WIFI_IF_AP, &conf_current);
-    if(!softap_config_equal(conf, conf_current) && esp_wifi_set_config(WIFI_IF_AP, &conf) != ESP_OK) {
-        return false;
-    }
-
-    return true;
+bool WiFiAPClass::softAP(
+  const char *ssid, const char *passphrase, int channel, int ssid_hidden, int max_connection, bool ftm_responder, wifi_auth_mode_t auth_mode,
+  wifi_cipher_type_t cipher
+) {
+  return AP.begin() && AP.create(ssid, passphrase, channel, ssid_hidden, max_connection, ftm_responder, auth_mode, cipher);
 }
 
+/**
+ * Return the current SSID associated with the network
+ * @return SSID
+ */
+String WiFiAPClass::softAPSSID() const {
+  return AP.SSID();
+}
 
 /**
  * Configure access point
@@ -144,137 +68,79 @@ bool WiFiAPClass::softAP(const char* ssid, const char* passphrase, int channel,
  * @param gateway       gateway IP
  * @param subnet        subnet mask
  */
-bool WiFiAPClass::softAPConfig(IPAddress local_ip, IPAddress gateway, IPAddress subnet)
-{
-
-    if(!WiFi.enableAP(true)) {
-        // enable AP failed
-        return false;
-    }
-
-    esp_wifi_start();
-
-    tcpip_adapter_ip_info_t info;
-    info.ip.addr = static_cast<uint32_t>(local_ip);
-    info.gw.addr = static_cast<uint32_t>(gateway);
-    info.netmask.addr = static_cast<uint32_t>(subnet);
-    tcpip_adapter_dhcps_stop(TCPIP_ADAPTER_IF_AP);
-    if(tcpip_adapter_set_ip_info(TCPIP_ADAPTER_IF_AP, &info) == ESP_OK) {
-        dhcps_lease_t lease;
-        lease.enable = true;
-        lease.start_ip.addr = static_cast<uint32_t>(local_ip) + (1 << 24);
-        lease.end_ip.addr = static_cast<uint32_t>(local_ip) + (11 << 24);
-
-        tcpip_adapter_dhcps_option(
-            (tcpip_adapter_option_mode_t)TCPIP_ADAPTER_OP_SET,
-            (tcpip_adapter_option_id_t)REQUESTED_IP_ADDRESS,
-            (void*)&lease, sizeof(dhcps_lease_t)
-        );
-
-        return tcpip_adapter_dhcps_start(TCPIP_ADAPTER_IF_AP) == ESP_OK;
-    }
-    return false;
+bool WiFiAPClass::softAPConfig(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dhcp_lease_start, IPAddress dns) {
+  return AP.begin() && AP.config(local_ip, gateway, subnet, dhcp_lease_start, dns);
 }
 
-
-
 /**
  * Disconnect from the network (close AP)
  * @param wifioff disable mode?
  * @return one value of wl_status_t enum
  */
-bool WiFiAPClass::softAPdisconnect(bool wifioff)
-{
-    bool ret;
-    wifi_config_t conf;
-
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return ESP_ERR_INVALID_STATE;
-    }
-
-    *conf.ap.ssid     = 0;
-    *conf.ap.password = 0;
-    conf.ap.authmode  = WIFI_AUTH_OPEN; // auth must be open if pass=0   
-    ret = esp_wifi_set_config(WIFI_IF_AP, &conf) == ESP_OK;
-
-    if(wifioff) {
-        ret = WiFi.enableAP(false) == ESP_OK;
-    }
-
-    return ret;
+bool WiFiAPClass::softAPdisconnect(bool wifioff) {
+  if (!AP.clear()) {
+    return false;
+  }
+  if (wifioff) {
+    return AP.end();
+  }
+  return true;
 }
 
+/**
+ * Sets the working bandwidth of the AP mode
+ * @param m wifi_bandwidth_t
+ */
+bool WiFiAPClass::softAPbandwidth(wifi_bandwidth_t bandwidth) {
+  return AP.bandwidth(bandwidth);
+}
 
 /**
  * Get the count of the Station / client that are connected to the softAP interface
  * @return Stations count
  */
-uint8_t WiFiAPClass::softAPgetStationNum()
-{
-    wifi_sta_list_t clients;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return 0;
-    }
-    if(esp_wifi_ap_get_sta_list(&clients) == ESP_OK) {
-        return clients.num;
-    }
-    return 0;
+uint8_t WiFiAPClass::softAPgetStationNum() {
+  return AP.stationCount();
 }
 
 /**
  * Get the softAP interface IP address.
  * @return IPAddress softAP IP
  */
-IPAddress WiFiAPClass::softAPIP()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPAddress();
-    }
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_AP, &ip);
-    return IPAddress(ip.ip.addr);
+IPAddress WiFiAPClass::softAPIP() {
+  return AP.localIP();
 }
 
 /**
  * Get the softAP broadcast IP address.
  * @return IPAddress softAP broadcastIP
  */
-IPAddress WiFiAPClass::softAPBroadcastIP()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPAddress();
-    }
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_AP, &ip);
-    return WiFiGenericClass::calculateBroadcast(IPAddress(ip.gw.addr), IPAddress(ip.netmask.addr));
+IPAddress WiFiAPClass::softAPBroadcastIP() {
+  return AP.broadcastIP();
 }
 
 /**
  * Get the softAP network ID.
  * @return IPAddress softAP networkID
  */
-IPAddress WiFiAPClass::softAPNetworkID()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPAddress();
-    }
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_AP, &ip);
-    return WiFiGenericClass::calculateNetworkID(IPAddress(ip.gw.addr), IPAddress(ip.netmask.addr));
+IPAddress WiFiAPClass::softAPNetworkID() {
+  return AP.networkID();
+}
+
+/**
+ * Get the softAP subnet mask.
+ * @return IPAddress subnetMask
+ */
+IPAddress WiFiAPClass::softAPSubnetMask() {
+  return AP.subnetMask();
 }
 
 /**
  * Get the softAP subnet CIDR.
  * @return uint8_t softAP subnetCIDR
  */
-uint8_t WiFiAPClass::softAPSubnetCIDR()
-{
-    tcpip_adapter_ip_info_t ip;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return (uint8_t)0;
-    }
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_AP, &ip);
-    return WiFiGenericClass::calculateSubnetCIDR(IPAddress(ip.netmask.addr));
+uint8_t WiFiAPClass::softAPSubnetCIDR() {
+  return AP.subnetCIDR();
 }
 
 /**
@@ -282,45 +148,24 @@ uint8_t WiFiAPClass::softAPSubnetCIDR()
  * @param mac   pointer to uint8_t array with length WL_MAC_ADDR_LENGTH
  * @return      pointer to uint8_t*
  */
-uint8_t* WiFiAPClass::softAPmacAddress(uint8_t* mac)
-{
-    if(WiFiGenericClass::getMode() != WIFI_MODE_NULL){
-        esp_wifi_get_mac(WIFI_IF_AP, mac);
-    }
-    return mac;
+uint8_t *WiFiAPClass::softAPmacAddress(uint8_t *mac) {
+  return AP.macAddress(mac);
 }
 
 /**
  * Get the softAP interface MAC address.
  * @return String mac
  */
-String WiFiAPClass::softAPmacAddress(void)
-{
-    uint8_t mac[6];
-    char macStr[18] = { 0 };
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return String();
-    }
-    esp_wifi_get_mac(WIFI_IF_AP, mac);
-
-    sprintf(macStr, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-    return String(macStr);
+String WiFiAPClass::softAPmacAddress(void) {
+  return AP.macAddress();
 }
 
 /**
  * Get the softAP interface Host name.
  * @return char array hostname
  */
-const char * WiFiAPClass::softAPgetHostname()
-{
-    const char * hostname = NULL;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return hostname;
-    }
-    if(tcpip_adapter_get_hostname(TCPIP_ADAPTER_IF_AP, &hostname)) {
-        return hostname;
-    }
-    return hostname;
+const char *WiFiAPClass::softAPgetHostname() {
+  return AP.getHostname();
 }
 
 /**
@@ -328,38 +173,26 @@ const char * WiFiAPClass::softAPgetHostname()
  * @param  hostname  pointer to const string
  * @return true on   success
  */
-bool WiFiAPClass::softAPsetHostname(const char * hostname)
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return false;
-    }
-    return tcpip_adapter_set_hostname(TCPIP_ADAPTER_IF_AP, hostname) == ESP_OK;
+bool WiFiAPClass::softAPsetHostname(const char *hostname) {
+  return AP.setHostname(hostname);
 }
 
+#if CONFIG_LWIP_IPV6
 /**
  * Enable IPv6 on the softAP interface.
  * @return true on success
  */
-bool WiFiAPClass::softAPenableIpV6()
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return false;
-    }
-    return tcpip_adapter_create_ip6_linklocal(TCPIP_ADAPTER_IF_AP) == ESP_OK;
+bool WiFiAPClass::softAPenableIPv6(bool enable) {
+  return AP.enableIPv6(enable);
 }
 
 /**
  * Get the softAP interface IPv6 address.
- * @return IPv6Address softAP IPv6
+ * @return IPAddress softAP IPv6
  */
-IPv6Address WiFiAPClass::softAPIPv6()
-{
-    static ip6_addr_t addr;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPv6Address();
-    }
-    if(tcpip_adapter_get_ip6_linklocal(TCPIP_ADAPTER_IF_AP, &addr)) {
-        return IPv6Address();
-    }
-    return IPv6Address(addr.addr);
+
+IPAddress WiFiAPClass::softAPlinkLocalIPv6() {
+  return AP.linkLocalIPv6();
 }
+#endif
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiAP.h b/libraries/WiFi/src/WiFiAP.h
index f1533cc3611..540ec87f44f 100644
--- a/libraries/WiFi/src/WiFiAP.h
+++ b/libraries/WiFi/src/WiFiAP.h
@@ -20,46 +20,101 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#ifndef ESP32WIFIAP_H_
-#define ESP32WIFIAP_H_
+#pragma once
 
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
+#include "esp_wifi_types.h"
 #include "WiFiType.h"
 #include "WiFiGeneric.h"
 
+#define WIFI_AP_DEFAULT_AUTH_MODE WIFI_AUTH_WPA2_PSK
+#define WIFI_AP_DEFAULT_CIPHER    WIFI_CIPHER_TYPE_CCMP  // Disable by default enabled insecure TKIP and use just CCMP.
 
-class WiFiAPClass
-{
+// ----------------------------------------------------------------------------------------------
+// ------------------------------------ NEW AP Implementation  ----------------------------------
+// ----------------------------------------------------------------------------------------------
 
-    // ----------------------------------------------------------------------------------------------
-    // ----------------------------------------- AP function ----------------------------------------
-    // ----------------------------------------------------------------------------------------------
+class APClass : public NetworkInterface {
+public:
+  APClass();
+  ~APClass();
+
+  bool begin();
+  bool end();
+
+  bool create(
+    const char *ssid, const char *passphrase = NULL, int channel = 1, int ssid_hidden = 0, int max_connection = 4, bool ftm_responder = false,
+    wifi_auth_mode_t auth_mode = WIFI_AP_DEFAULT_AUTH_MODE, wifi_cipher_type_t cipher = WIFI_AP_DEFAULT_CIPHER
+  );
+  bool clear();
+
+  bool bandwidth(wifi_bandwidth_t bandwidth);
+  bool enableNAPT(bool enable = true);
+
+  String SSID(void) const;
+  uint8_t stationCount();
+
+  void _onApEvent(int32_t event_id, void *event_data);
+
+protected:
+  network_event_handle_t _wifi_ap_event_handle;
+
+  size_t printDriverInfo(Print &out) const;
+
+  friend class WiFiGenericClass;
+  bool onEnable();
+  bool onDisable();
+};
+
+// ----------------------------------------------------------------------------------------------
+// ------------------------------- OLD AP API (compatibility)  ----------------------------------
+// ----------------------------------------------------------------------------------------------
+
+class WiFiAPClass {
 
 public:
+  APClass AP;
 
-    bool softAP(const char* ssid, const char* passphrase = NULL, int channel = 1, int ssid_hidden = 0, int max_connection = 4);
-    bool softAPConfig(IPAddress local_ip, IPAddress gateway, IPAddress subnet);
-    bool softAPdisconnect(bool wifioff = false);
+  bool softAP(
+    const char *ssid, const char *passphrase = NULL, int channel = 1, int ssid_hidden = 0, int max_connection = 4, bool ftm_responder = false,
+    wifi_auth_mode_t auth_mode = WIFI_AP_DEFAULT_AUTH_MODE, wifi_cipher_type_t cipher = WIFI_AP_DEFAULT_CIPHER
+  );
+  bool softAP(
+    const String &ssid, const String &passphrase = emptyString, int channel = 1, int ssid_hidden = 0, int max_connection = 4, bool ftm_responder = false,
+    wifi_auth_mode_t auth_mode = WIFI_AP_DEFAULT_AUTH_MODE, wifi_cipher_type_t cipher = WIFI_AP_DEFAULT_CIPHER
+  ) {
+    return softAP(ssid.c_str(), passphrase.c_str(), channel, ssid_hidden, max_connection, ftm_responder, auth_mode, cipher);
+  }
 
-    uint8_t softAPgetStationNum();
+  bool softAPConfig(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dhcp_lease_start = (uint32_t)0, IPAddress dns = (uint32_t)0);
+  bool softAPdisconnect(bool wifioff = false);
 
-    IPAddress softAPIP();
+  bool softAPbandwidth(wifi_bandwidth_t bandwidth);
 
-    IPAddress softAPBroadcastIP();
-    IPAddress softAPNetworkID();
-    uint8_t softAPSubnetCIDR();
+  uint8_t softAPgetStationNum();
+  String softAPSSID(void) const;
 
-    bool softAPenableIpV6();
-    IPv6Address softAPIPv6();
+  IPAddress softAPIP();
+  IPAddress softAPBroadcastIP();
+  IPAddress softAPNetworkID();
+  IPAddress softAPSubnetMask();
+  uint8_t softAPSubnetCIDR();
 
-    const char * softAPgetHostname();
-    bool softAPsetHostname(const char * hostname);
+#if CONFIG_LWIP_IPV6
+  bool softAPenableIPv6(bool enable = true);
+  IPAddress softAPlinkLocalIPv6();
+#endif
 
-    uint8_t* softAPmacAddress(uint8_t* mac);
-    String softAPmacAddress(void);
+  const char *softAPgetHostname();
+  bool softAPsetHostname(const char *hostname);
 
-protected:
+  uint8_t *softAPmacAddress(uint8_t *mac);
+  String softAPmacAddress(void);
 
+protected:
 };
 
-#endif /* ESP32WIFIAP_H_*/
+#endif /* SOC_WIFI_SUPPORTED*/
diff --git a/libraries/WiFi/src/WiFiClient.cpp b/libraries/WiFi/src/WiFiClient.cpp
deleted file mode 100644
index 52df273149a..00000000000
--- a/libraries/WiFi/src/WiFiClient.cpp
+++ /dev/null
@@ -1,597 +0,0 @@
-/*
-  Client.h - Client class for Raspberry Pi
-  Copyright (c) 2016 Hristo Gochkov  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-
-#include "WiFiClient.h"
-#include "WiFi.h"
-#include <lwip/sockets.h>
-#include <lwip/netdb.h>
-#include <errno.h>
-
-#define WIFI_CLIENT_MAX_WRITE_RETRY   (10)
-#define WIFI_CLIENT_SELECT_TIMEOUT_US (1000000)
-#define WIFI_CLIENT_FLUSH_BUFFER_SIZE (1024)
-
-#undef connect
-#undef write
-#undef read
-
-class WiFiClientRxBuffer {
-private:
-        size_t _size;
-        uint8_t *_buffer;
-        size_t _pos;
-        size_t _fill;
-        int _fd;
-        bool _failed;
-
-        size_t r_available()
-        {
-            if(_fd < 0){
-                return 0;
-            }
-            int count;
-            int res = lwip_ioctl_r(_fd, FIONREAD, &count);
-            if(res < 0) {
-                _failed = true;
-                return 0;
-            }
-            return count;
-        }
-
-        size_t fillBuffer()
-        {
-            if(!_buffer){
-                _buffer = (uint8_t *)malloc(_size);
-                if(!_buffer) {
-                    log_e("Not enough memory to allocate buffer");
-                    _failed = true;
-                    return 0;
-                }
-            }
-            if(_fill && _pos == _fill){
-                _fill = 0;
-                _pos = 0;
-            }
-            if(!_buffer || _size <= _fill || !r_available()) {
-                return 0;
-            }
-            int res = recv(_fd, _buffer + _fill, _size - _fill, MSG_DONTWAIT);
-            if(res < 0) {
-                if(errno != EWOULDBLOCK) {
-                    _failed = true;
-                }
-                return 0;
-            }
-            _fill += res;
-            return res;
-        }
-
-public:
-    WiFiClientRxBuffer(int fd, size_t size=1436)
-        :_size(size)
-        ,_buffer(NULL)
-        ,_pos(0)
-        ,_fill(0)
-        ,_fd(fd)
-        ,_failed(false)
-    {
-        //_buffer = (uint8_t *)malloc(_size);
-    }
-
-    ~WiFiClientRxBuffer()
-    {
-        free(_buffer);
-    }
-
-    bool failed(){
-        return _failed;
-    }
-
-    int read(uint8_t * dst, size_t len){
-        if(!dst || !len || (_pos == _fill && !fillBuffer())){
-            return _failed ? -1 : 0;
-        }
-        size_t a = _fill - _pos;
-        if(len <= a || ((len - a) <= (_size - _fill) && fillBuffer() >= (len - a))){
-            if(len == 1){
-                *dst = _buffer[_pos];
-            } else {
-                memcpy(dst, _buffer + _pos, len);
-            }
-            _pos += len;
-            return len;
-        }
-        size_t left = len;
-        size_t toRead = a;
-        uint8_t * buf = dst;
-        memcpy(buf, _buffer + _pos, toRead);
-        _pos += toRead;
-        left -= toRead;
-        buf += toRead;
-        while(left){
-            if(!fillBuffer()){
-                return len - left;
-            }
-            a = _fill - _pos;
-            toRead = (a > left)?left:a;
-            memcpy(buf, _buffer + _pos, toRead);
-            _pos += toRead;
-            left -= toRead;
-            buf += toRead;
-        }
-        return len;
-    }
-
-    int peek(){
-        if(_pos == _fill && !fillBuffer()){
-            return -1;
-        }
-        return _buffer[_pos];
-    }
-
-    size_t available(){
-        return _fill - _pos + r_available();
-    }
-};
-
-class WiFiClientSocketHandle {
-private:
-    int sockfd;
-
-public:
-    WiFiClientSocketHandle(int fd):sockfd(fd)
-    {
-    }
-
-    ~WiFiClientSocketHandle()
-    {
-        close(sockfd);
-    }
-
-    int fd()
-    {
-        return sockfd;
-    }
-};
-
-WiFiClient::WiFiClient():_connected(false),next(NULL)
-{
-}
-
-WiFiClient::WiFiClient(int fd):_connected(true),next(NULL)
-{
-    clientSocketHandle.reset(new WiFiClientSocketHandle(fd));
-    _rxBuffer.reset(new WiFiClientRxBuffer(fd));
-}
-
-WiFiClient::~WiFiClient()
-{
-    stop();
-}
-
-WiFiClient & WiFiClient::operator=(const WiFiClient &other)
-{
-    stop();
-    clientSocketHandle = other.clientSocketHandle;
-    _rxBuffer = other._rxBuffer;
-    _connected = other._connected;
-    return *this;
-}
-
-void WiFiClient::stop()
-{
-    clientSocketHandle = NULL;
-    _rxBuffer = NULL;
-    _connected = false;
-}
-
-int WiFiClient::connect(IPAddress ip, uint16_t port)
-{
-    return connect(ip,port,-1);
-}
-int WiFiClient::connect(IPAddress ip, uint16_t port, int32_t timeout)
-{
-    int sockfd = socket(AF_INET, SOCK_STREAM, 0);
-    if (sockfd < 0) {
-        log_e("socket: %d", errno);
-        return 0;
-    }
-    fcntl( sockfd, F_SETFL, fcntl( sockfd, F_GETFL, 0 ) | O_NONBLOCK );
-
-    uint32_t ip_addr = ip;
-    struct sockaddr_in serveraddr;
-    bzero((char *) &serveraddr, sizeof(serveraddr));
-    serveraddr.sin_family = AF_INET;
-    bcopy((const void *)(&ip_addr), (void *)&serveraddr.sin_addr.s_addr, 4);
-    serveraddr.sin_port = htons(port);
-    fd_set fdset;
-    struct timeval tv;
-    FD_ZERO(&fdset);
-    FD_SET(sockfd, &fdset);
-    tv.tv_sec = 0;
-    tv.tv_usec = timeout * 1000;
-
-    int res = lwip_connect_r(sockfd, (struct sockaddr*)&serveraddr, sizeof(serveraddr));
-    if (res < 0 && errno != EINPROGRESS) {
-        log_e("connect on fd %d, errno: %d, \"%s\"", sockfd, errno, strerror(errno));
-        close(sockfd);
-        return 0;
-    }
-
-    res = select(sockfd + 1, nullptr, &fdset, nullptr, timeout<0 ? nullptr : &tv);
-    if (res < 0) {
-        log_e("select on fd %d, errno: %d, \"%s\"", sockfd, errno, strerror(errno));
-        close(sockfd);
-        return 0;
-    } else if (res == 0) {
-        log_i("select returned due to timeout %d ms for fd %d", timeout, sockfd);
-        close(sockfd);
-        return 0;
-    } else {
-        int sockerr;
-        socklen_t len = (socklen_t)sizeof(int);
-        res = getsockopt(sockfd, SOL_SOCKET, SO_ERROR, &sockerr, &len);
-
-        if (res < 0) {
-            log_e("getsockopt on fd %d, errno: %d, \"%s\"", sockfd, errno, strerror(errno));
-            close(sockfd);
-            return 0;
-        }
-
-        if (sockerr != 0) {
-            log_e("socket error on fd %d, errno: %d, \"%s\"", sockfd, sockerr, strerror(sockerr));
-            close(sockfd);
-            return 0;
-        }
-    }
-
-    fcntl( sockfd, F_SETFL, fcntl( sockfd, F_GETFL, 0 ) & (~O_NONBLOCK) );
-    clientSocketHandle.reset(new WiFiClientSocketHandle(sockfd));
-    _rxBuffer.reset(new WiFiClientRxBuffer(sockfd));
-    _connected = true;
-    return 1;
-}
-
-int WiFiClient::connect(const char *host, uint16_t port)
-{
-    return connect(host,port,-1);
-}
-int WiFiClient::connect(const char *host, uint16_t port, int32_t timeout)
-{
-    IPAddress srv((uint32_t)0);
-    if(!WiFiGenericClass::hostByName(host, srv)){
-        return 0;
-    }
-    return connect(srv, port, timeout);
-}
-
-int WiFiClient::setSocketOption(int option, char* value, size_t len)
-{
-    int res = setsockopt(fd(), SOL_SOCKET, option, value, len);
-    if(res < 0) {
-        log_e("%X : %d", option, errno);
-    }
-    return res;
-}
-
-int WiFiClient::setTimeout(uint32_t seconds)
-{
-    Client::setTimeout(seconds * 1000);
-    struct timeval tv;
-    tv.tv_sec = seconds;
-    tv.tv_usec = 0;
-    if(setSocketOption(SO_RCVTIMEO, (char *)&tv, sizeof(struct timeval)) < 0) {
-        return -1;
-    }
-    return setSocketOption(SO_SNDTIMEO, (char *)&tv, sizeof(struct timeval));
-}
-
-int WiFiClient::setOption(int option, int *value)
-{
-    int res = setsockopt(fd(), IPPROTO_TCP, option, (char *) value, sizeof(int));
-    if(res < 0) {
-        log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
-    }
-    return res;
-}
-
-int WiFiClient::getOption(int option, int *value)
-{
-    size_t size = sizeof(int);
-    int res = getsockopt(fd(), IPPROTO_TCP, option, (char *)value, &size);
-    if(res < 0) {
-        log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
-    }
-    return res;
-}
-
-int WiFiClient::setNoDelay(bool nodelay)
-{
-    int flag = nodelay;
-    return setOption(TCP_NODELAY, &flag);
-}
-
-bool WiFiClient::getNoDelay()
-{
-    int flag = 0;
-    getOption(TCP_NODELAY, &flag);
-    return flag;
-}
-
-size_t WiFiClient::write(uint8_t data)
-{
-    return write(&data, 1);
-}
-
-int WiFiClient::read()
-{
-    uint8_t data = 0;
-    int res = read(&data, 1);
-    if(res < 0) {
-        return res;
-    }
-    if (res == 0) {  //  No data available.
-        return -1;
-    }
-    return data;
-}
-
-size_t WiFiClient::write(const uint8_t *buf, size_t size)
-{
-    int res =0;
-    int retry = WIFI_CLIENT_MAX_WRITE_RETRY;
-    int socketFileDescriptor = fd();
-    size_t totalBytesSent = 0;
-    size_t bytesRemaining = size;
-
-    if(!_connected || (socketFileDescriptor < 0)) {
-        return 0;
-    }
-
-    while(retry) {
-        //use select to make sure the socket is ready for writing
-        fd_set set;
-        struct timeval tv;
-        FD_ZERO(&set);        // empties the set
-        FD_SET(socketFileDescriptor, &set); // adds FD to the set
-        tv.tv_sec = 0;
-        tv.tv_usec = WIFI_CLIENT_SELECT_TIMEOUT_US;
-        retry--;
-
-        if(select(socketFileDescriptor + 1, NULL, &set, NULL, &tv) < 0) {
-            return 0;
-        }
-
-        if(FD_ISSET(socketFileDescriptor, &set)) {
-            res = send(socketFileDescriptor, (void*) buf, bytesRemaining, MSG_DONTWAIT);
-            if(res > 0) {
-                totalBytesSent += res;
-                if (totalBytesSent >= size) {
-                    //completed successfully
-                    retry = 0;
-                } else {
-                    buf += res;
-                    bytesRemaining -= res;
-                    retry = WIFI_CLIENT_MAX_WRITE_RETRY;
-                }
-            }
-            else if(res < 0) {
-                log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
-                if(errno != EAGAIN) {
-                    //if resource was busy, can try again, otherwise give up
-                    stop();
-                    res = 0;
-                    retry = 0;
-                }
-            }
-            else {
-                // Try again
-            }
-        }
-    }
-    return totalBytesSent;
-}
-
-size_t WiFiClient::write_P(PGM_P buf, size_t size)
-{
-    return write(buf, size);
-}
-
-size_t WiFiClient::write(Stream &stream)
-{
-    uint8_t * buf = (uint8_t *)malloc(1360);
-    if(!buf){
-        return 0;
-    }
-    size_t toRead = 0, toWrite = 0, written = 0;
-    size_t available = stream.available();
-    while(available){
-        toRead = (available > 1360)?1360:available;
-        toWrite = stream.readBytes(buf, toRead);
-        written += write(buf, toWrite);
-        available = stream.available();
-    }
-    free(buf);
-    return written;
-}
-
-int WiFiClient::read(uint8_t *buf, size_t size)
-{
-    int res = -1;
-    res = _rxBuffer->read(buf, size);
-    if(_rxBuffer->failed()) {
-        log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
-        stop();
-    }
-    return res;
-}
-
-int WiFiClient::peek()
-{
-    int res = _rxBuffer->peek();
-    if(_rxBuffer->failed()) {
-        log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
-        stop();
-    }
-    return res;
-}
-
-int WiFiClient::available()
-{
-    if(!_rxBuffer)
-    {
-        return 0;
-    }
-    int res = _rxBuffer->available();
-    if(_rxBuffer->failed()) {
-        log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
-        stop();
-    }
-    return res;
-}
-
-// Though flushing means to send all pending data,
-// seems that in Arduino it also means to clear RX
-void WiFiClient::flush() {
-    int res;
-    size_t a = available(), toRead = 0;
-    if(!a){
-        return;//nothing to flush
-    }
-    uint8_t * buf = (uint8_t *)malloc(WIFI_CLIENT_FLUSH_BUFFER_SIZE);
-    if(!buf){
-        return;//memory error
-    }
-    while(a){
-        toRead = (a>WIFI_CLIENT_FLUSH_BUFFER_SIZE)?WIFI_CLIENT_FLUSH_BUFFER_SIZE:a;
-        res = recv(fd(), buf, toRead, MSG_DONTWAIT);
-        if(res < 0) {
-            log_e("fail on fd %d, errno: %d, \"%s\"", fd(), errno, strerror(errno));
-            stop();
-            break;
-        }
-        a -= res;
-    }
-    free(buf);
-}
-
-uint8_t WiFiClient::connected()
-{
-    if (_connected) {
-        uint8_t dummy;
-        int res = recv(fd(), &dummy, 0, MSG_DONTWAIT);
-        // avoid unused var warning by gcc
-        (void)res;
-        // recv only sets errno if res is <= 0
-        if (res <= 0){
-          switch (errno) {
-              case EWOULDBLOCK:
-              case ENOENT: //caused by vfs
-                  _connected = true;
-                  break;
-              case ENOTCONN:
-              case EPIPE:
-              case ECONNRESET:
-              case ECONNREFUSED:
-              case ECONNABORTED:
-                  _connected = false;
-                  log_d("Disconnected: RES: %d, ERR: %d", res, errno);
-                  break;
-              default:
-                  log_i("Unexpected: RES: %d, ERR: %d", res, errno);
-                  _connected = true;
-                  break;
-          }
-        } else {
-          _connected = true;
-        }
-    }
-    return _connected;
-}
-
-IPAddress WiFiClient::remoteIP(int fd) const
-{
-    struct sockaddr_storage addr;
-    socklen_t len = sizeof addr;
-    getpeername(fd, (struct sockaddr*)&addr, &len);
-    struct sockaddr_in *s = (struct sockaddr_in *)&addr;
-    return IPAddress((uint32_t)(s->sin_addr.s_addr));
-}
-
-uint16_t WiFiClient::remotePort(int fd) const
-{
-    struct sockaddr_storage addr;
-    socklen_t len = sizeof addr;
-    getpeername(fd, (struct sockaddr*)&addr, &len);
-    struct sockaddr_in *s = (struct sockaddr_in *)&addr;
-    return ntohs(s->sin_port);
-}
-
-IPAddress WiFiClient::remoteIP() const
-{
-    return remoteIP(fd());
-}
-
-uint16_t WiFiClient::remotePort() const
-{
-    return remotePort(fd());
-}
-
-IPAddress WiFiClient::localIP(int fd) const
-{
-    struct sockaddr_storage addr;
-    socklen_t len = sizeof addr;
-    getsockname(fd, (struct sockaddr*)&addr, &len);
-    struct sockaddr_in *s = (struct sockaddr_in *)&addr;
-    return IPAddress((uint32_t)(s->sin_addr.s_addr));
-}
-
-uint16_t WiFiClient::localPort(int fd) const
-{
-    struct sockaddr_storage addr;
-    socklen_t len = sizeof addr;
-    getsockname(fd, (struct sockaddr*)&addr, &len);
-    struct sockaddr_in *s = (struct sockaddr_in *)&addr;
-    return ntohs(s->sin_port);
-}
-
-IPAddress WiFiClient::localIP() const
-{
-    return localIP(fd());
-}
-
-uint16_t WiFiClient::localPort() const
-{
-    return localPort(fd());
-}
-
-bool WiFiClient::operator==(const WiFiClient& rhs)
-{
-    return clientSocketHandle == rhs.clientSocketHandle && remotePort() == rhs.remotePort() && remoteIP() == rhs.remoteIP();
-}
-
-int WiFiClient::fd() const
-{
-    if (clientSocketHandle == NULL) {
-        return -1;
-    } else {
-        return clientSocketHandle->fd();
-    }
-}
-
diff --git a/libraries/WiFi/src/WiFiClient.h b/libraries/WiFi/src/WiFiClient.h
index 4915cfd5203..4add805ca09 100644
--- a/libraries/WiFi/src/WiFiClient.h
+++ b/libraries/WiFi/src/WiFiClient.h
@@ -1,108 +1,3 @@
-/*
-  Client.h - Base class that provides Client
-  Copyright (c) 2011 Adrian McEwen.  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-
-#ifndef _WIFICLIENT_H_
-#define _WIFICLIENT_H_
-
-
-#include "Arduino.h"
-#include "Client.h"
-#include <memory>
-
-class WiFiClientSocketHandle;
-class WiFiClientRxBuffer;
-
-class ESPLwIPClient : public Client
-{
-public:
-        virtual int connect(IPAddress ip, uint16_t port, int32_t timeout) = 0;
-        virtual int connect(const char *host, uint16_t port, int32_t timeout) = 0;
-        virtual int setTimeout(uint32_t seconds) = 0;
-};
-
-class WiFiClient : public ESPLwIPClient
-{
-protected:
-    std::shared_ptr<WiFiClientSocketHandle> clientSocketHandle;
-    std::shared_ptr<WiFiClientRxBuffer> _rxBuffer;
-    bool _connected;
-
-public:
-    WiFiClient *next;
-    WiFiClient();
-    WiFiClient(int fd);
-    ~WiFiClient();
-    int connect(IPAddress ip, uint16_t port);
-    int connect(IPAddress ip, uint16_t port, int32_t timeout);
-    int connect(const char *host, uint16_t port);
-    int connect(const char *host, uint16_t port, int32_t timeout);
-    size_t write(uint8_t data);
-    size_t write(const uint8_t *buf, size_t size);
-    size_t write_P(PGM_P buf, size_t size);
-    size_t write(Stream &stream);
-    int available();
-    int read();
-    int read(uint8_t *buf, size_t size);
-    int peek();
-    void flush();
-    void stop();
-    uint8_t connected();
-
-    operator bool()
-    {
-        return connected();
-    }
-    WiFiClient & operator=(const WiFiClient &other);
-    bool operator==(const bool value)
-    {
-        return bool() == value;
-    }
-    bool operator!=(const bool value)
-    {
-        return bool() != value;
-    }
-    bool operator==(const WiFiClient&);
-    bool operator!=(const WiFiClient& rhs)
-    {
-        return !this->operator==(rhs);
-    };
-
-    int fd() const;
-
-    int setSocketOption(int option, char* value, size_t len);
-    int setOption(int option, int *value);
-    int getOption(int option, int *value);
-    int setTimeout(uint32_t seconds);
-    int setNoDelay(bool nodelay);
-    bool getNoDelay();
-
-    IPAddress remoteIP() const;
-    IPAddress remoteIP(int fd) const;
-    uint16_t remotePort() const;
-    uint16_t remotePort(int fd) const;
-    IPAddress localIP() const;
-    IPAddress localIP(int fd) const;
-    uint16_t localPort() const;
-    uint16_t localPort(int fd) const;
-
-    //friend class WiFiServer;
-    using Print::write;
-};
-
-#endif /* _WIFICLIENT_H_ */
+#pragma once
+#include "NetworkClient.h"
+typedef NetworkClient WiFiClient;
diff --git a/libraries/WiFi/src/WiFiGeneric.cpp b/libraries/WiFi/src/WiFiGeneric.cpp
index 1362a65bee9..3faf34fef34 100644
--- a/libraries/WiFi/src/WiFiGeneric.cpp
+++ b/libraries/WiFi/src/WiFiGeneric.cpp
@@ -24,6 +24,7 @@
 
 #include "WiFi.h"
 #include "WiFiGeneric.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
 extern "C" {
 #include <stdint.h>
@@ -35,554 +36,622 @@ extern "C" {
 
 #include <esp_err.h>
 #include <esp_wifi.h>
-#include <esp_event_loop.h>
+#include <esp_event.h>
+#include <esp_mac.h>
+#include <esp_netif.h>
+#if SOC_WIFI_SUPPORTED
+#include <esp_phy.h>
+#endif
 #include "lwip/ip_addr.h"
 #include "lwip/opt.h"
 #include "lwip/err.h"
 #include "lwip/dns.h"
-#include "esp_ipc.h"
+#include "lwip/netif.h"
+#include "dhcpserver/dhcpserver.h"
+#include "dhcpserver/dhcpserver_options.h"
 
-} //extern "C"
+}  //extern "C"
 
-#include "esp32-hal-log.h"
+#include "esp32-hal.h"
 #include <vector>
 #include "sdkconfig.h"
 
-static xQueueHandle _network_event_queue;
-static TaskHandle_t _network_event_task_handle = NULL;
-static EventGroupHandle_t _network_event_group = NULL;
+ESP_EVENT_DEFINE_BASE(ARDUINO_EVENTS);
 
-esp_err_t postToSysQueue(system_prov_event_t *data)
-{
-    if (xQueueSend(_network_event_queue, &data, portMAX_DELAY) != pdPASS) {
-        log_w("Network Event Queue Send Failed!");
-            return ESP_FAIL;
-    }
-    return ESP_OK;
-}
-
-static void _network_event_task(void * arg){
-    system_prov_event_t *data;
-    for (;;) {
-        if(xQueueReceive(_network_event_queue, &data, portMAX_DELAY) == pdTRUE){
-            if(data->prov_event != NULL){
-                WiFiGenericClass::_eventCallback(arg, data->sys_event, data->prov_event);
-                free(data->sys_event);
-                free(data->prov_event);
-            } else {
-                WiFiGenericClass::_eventCallback(arg, data->sys_event, NULL);
-            }
-            free(data);
-        }        
-    }
-    vTaskDelete(NULL);
-    _network_event_task_handle = NULL;
-}
+static esp_netif_t *esp_netifs[ESP_IF_MAX] = {NULL, NULL, NULL};
 
-static esp_err_t _network_event_cb(void *arg, system_event_t *event){ 
-    system_prov_event_t *sys_prov_data = (system_prov_event_t *)malloc(sizeof(system_prov_event_t));
-    if(sys_prov_data == NULL) {
-        return ESP_FAIL;
-    }
-    sys_prov_data->sys_event = event;
-    sys_prov_data->prov_event = NULL;
-    if (postToSysQueue(sys_prov_data) != ESP_OK){
-        free(sys_prov_data);
-        return ESP_FAIL;
-    }
-    return ESP_OK;
+esp_netif_t *get_esp_interface_netif(esp_interface_t interface) {
+  if (interface < ESP_IF_MAX) {
+    return esp_netifs[interface];
+  }
+  return NULL;
 }
 
-static bool _start_network_event_task(){
-    if(!_network_event_group){
-        _network_event_group = xEventGroupCreate();
-        if(!_network_event_group){
-            log_e("Network Event Group Create Failed!");
-            return false;
-        }
-        xEventGroupSetBits(_network_event_group, WIFI_DNS_IDLE_BIT);
-    }
-    if(!_network_event_queue){
-        _network_event_queue = xQueueCreate(32, sizeof(system_prov_event_t));
-        if(!_network_event_queue){
-            log_e("Network Event Queue Create Failed!");
-            return false;
-        }
-    }
-    if(!_network_event_task_handle){
-        xTaskCreateUniversal(_network_event_task, "network_event", 4096, NULL, ESP_TASKD_EVENT_PRIO - 1, &_network_event_task_handle, CONFIG_ARDUINO_EVENT_RUNNING_CORE);
-        if(!_network_event_task_handle){
-            log_e("Network Event Task Start Failed!");
-            return false;
-        }
-    }
-    return esp_event_loop_init(&_network_event_cb, NULL) == ESP_OK;
-}
+static void _arduino_event_cb(void *arg, esp_event_base_t event_base, int32_t event_id, void *event_data) {
+  arduino_event_t arduino_event;
+  arduino_event.event_id = ARDUINO_EVENT_MAX;
 
-void tcpipInit(){
-    static bool initialized = false;
-    if(!initialized && _start_network_event_task()){
-        initialized = true;
-        tcpip_adapter_init();
-    }
-}
+  /*
+	 * SCAN
+	 * */
+  if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_SCAN_DONE) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    wifi_event_sta_scan_done_t *event = (wifi_event_sta_scan_done_t *)event_data;
+    log_v("SCAN Done: ID: %u, Status: %u, Results: %u", event->scan_id, event->status, event->number);
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_SCAN_DONE;
+    memcpy(&arduino_event.event_info.wifi_scan_done, event_data, sizeof(wifi_event_sta_scan_done_t));
+
+    /*
+	 * WPS
+	 * */
+  } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_SUCCESS) {
+    arduino_event.event_id = ARDUINO_EVENT_WPS_ER_SUCCESS;
+  } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_FAILED) {
+    arduino_event.event_id = ARDUINO_EVENT_WPS_ER_FAILED;
+    memcpy(&arduino_event.event_info.wps_fail_reason, event_data, sizeof(wifi_event_sta_wps_fail_reason_t));
+  } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_TIMEOUT) {
+    arduino_event.event_id = ARDUINO_EVENT_WPS_ER_TIMEOUT;
+  } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_PIN) {
+    arduino_event.event_id = ARDUINO_EVENT_WPS_ER_PIN;
+    memcpy(&arduino_event.event_info.wps_er_pin, event_data, sizeof(wifi_event_sta_wps_er_pin_t));
+  } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_WPS_ER_PBC_OVERLAP) {
+    arduino_event.event_id = ARDUINO_EVENT_WPS_ER_PBC_OVERLAP;
+
+    /*
+	 * FTM
+	 * */
+  } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_FTM_REPORT) {
+    arduino_event.event_id = ARDUINO_EVENT_WIFI_FTM_REPORT;
+    memcpy(&arduino_event.event_info.wifi_ftm_report, event_data, sizeof(wifi_event_ftm_report_t));
+
+#if !CONFIG_ESP_WIFI_REMOTE_ENABLED
+    /*
+	 * SMART CONFIG
+	 * */
+  } else if (event_base == SC_EVENT && event_id == SC_EVENT_SCAN_DONE) {
+    log_v("SC Scan Done");
+    arduino_event.event_id = ARDUINO_EVENT_SC_SCAN_DONE;
+  } else if (event_base == SC_EVENT && event_id == SC_EVENT_FOUND_CHANNEL) {
+    log_v("SC Found Channel");
+    arduino_event.event_id = ARDUINO_EVENT_SC_FOUND_CHANNEL;
+  } else if (event_base == SC_EVENT && event_id == SC_EVENT_GOT_SSID_PSWD) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    smartconfig_event_got_ssid_pswd_t *event = (smartconfig_event_got_ssid_pswd_t *)event_data;
+    log_v("SC: SSID: %s, Password: %s", (const char *)event->ssid, (const char *)event->password);
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_SC_GOT_SSID_PSWD;
+    memcpy(&arduino_event.event_info.sc_got_ssid_pswd, event_data, sizeof(smartconfig_event_got_ssid_pswd_t));
+
+  } else if (event_base == SC_EVENT && event_id == SC_EVENT_SEND_ACK_DONE) {
+    log_v("SC Send Ack Done");
+    arduino_event.event_id = ARDUINO_EVENT_SC_SEND_ACK_DONE;
+
+#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI
+    /*
+	 * Provisioning
+	 * */
+  } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_INIT) {
+    log_v("Provisioning Initialized!");
+    arduino_event.event_id = ARDUINO_EVENT_PROV_INIT;
+  } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_DEINIT) {
+    log_v("Provisioning Uninitialized!");
+    arduino_event.event_id = ARDUINO_EVENT_PROV_DEINIT;
+  } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_START) {
+    log_v("Provisioning Start!");
+    arduino_event.event_id = ARDUINO_EVENT_PROV_START;
+  } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_END) {
+    log_v("Provisioning End!");
+    network_prov_mgr_deinit();
+    arduino_event.event_id = ARDUINO_EVENT_PROV_END;
+  } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_WIFI_CRED_RECV) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_VERBOSE
+    wifi_sta_config_t *event = (wifi_sta_config_t *)event_data;
+    log_v("Provisioned Credentials: SSID: %s, Password: %s", (const char *)event->ssid, (const char *)event->password);
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_PROV_CRED_RECV;
+    memcpy(&arduino_event.event_info.prov_cred_recv, event_data, sizeof(wifi_sta_config_t));
+  } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_WIFI_CRED_FAIL) {
+#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
+    network_prov_wifi_sta_fail_reason_t *reason = (network_prov_wifi_sta_fail_reason_t *)event_data;
+    log_e("Provisioning Failed: Reason : %s", (*reason == NETWORK_PROV_WIFI_STA_AUTH_ERROR) ? "Authentication Failed" : "AP Not Found");
+#endif
+    arduino_event.event_id = ARDUINO_EVENT_PROV_CRED_FAIL;
+    memcpy(&arduino_event.event_info.prov_fail_reason, event_data, sizeof(network_prov_wifi_sta_fail_reason_t));
+  } else if (event_base == NETWORK_PROV_EVENT && event_id == NETWORK_PROV_WIFI_CRED_SUCCESS) {
+    log_v("Provisioning Success!");
+    arduino_event.event_id = ARDUINO_EVENT_PROV_CRED_SUCCESS;
+#endif
+#endif
+  }
 
-static bool lowLevelInitDone = false;
-static bool wifiLowLevelInit(bool persistent){
-    if(!lowLevelInitDone){
-        tcpipInit();
-        wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
-        esp_err_t err = esp_wifi_init(&cfg);
-        if(err){
-            log_e("esp_wifi_init %d", err);
-            return false;
-        }
-        if(!persistent){
-          esp_wifi_set_storage(WIFI_STORAGE_RAM);
-        }
-        lowLevelInitDone = true;
-    }
-    return true;
+  if (arduino_event.event_id < ARDUINO_EVENT_MAX) {
+    Network.postEvent(&arduino_event);
+  }
 }
 
-static bool wifiLowLevelDeinit(){
-    //deinit not working yet!
-    //esp_wifi_deinit();
-    return true;
-}
+static bool initWiFiEvents() {
+  if (esp_event_handler_instance_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb, NULL, NULL)) {
+    log_e("event_handler_instance_register for WIFI_EVENT Failed!");
+    return false;
+  }
 
-static bool _esp_wifi_started = false;
+#if !CONFIG_ESP_WIFI_REMOTE_ENABLED
+  if (esp_event_handler_instance_register(SC_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb, NULL, NULL)) {
+    log_e("event_handler_instance_register for SC_EVENT Failed!");
+    return false;
+  }
 
-static bool espWiFiStart(){
-    if(_esp_wifi_started){
-        return true;
-    }
-    esp_err_t err = esp_wifi_start();
-    if (err != ESP_OK) {
-        log_e("esp_wifi_start %d", err);
-        return false;
-    }
-    _esp_wifi_started = true;
-    system_event_t event;
-    event.event_id = SYSTEM_EVENT_WIFI_READY;
-    WiFiGenericClass::_eventCallback(nullptr, &event, NULL);
-    return true;
-}
+#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI
+  if (esp_event_handler_instance_register(NETWORK_PROV_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb, NULL, NULL)) {
+    log_e("event_handler_instance_register for NETWORK_PROV_EVENT Failed!");
+    return false;
+  }
+#endif
+#endif
 
-static bool espWiFiStop(){
-    esp_err_t err;
-    if(!_esp_wifi_started){
-        return true;
-    }
-    _esp_wifi_started = false;
-    err = esp_wifi_stop();
-    if(err){
-        log_e("Could not stop WiFi! %d", err);
-        _esp_wifi_started = true;
-        return false;
-    }
-    return wifiLowLevelDeinit();
+  return true;
 }
 
-// -----------------------------------------------------------------------------------------------------------------------
-// ------------------------------------------------- Generic WiFi function -----------------------------------------------
-// -----------------------------------------------------------------------------------------------------------------------
-
-typedef struct WiFiEventCbList {
-    static wifi_event_id_t current_id;
-    wifi_event_id_t id;
-    WiFiEventCb cb;
-    WiFiEventFuncCb fcb;
-    WiFiEventSysCb scb;
-    WiFiProvEventCb provcb;
-    system_event_id_t event;
+static bool deinitWiFiEvents() {
+  if (esp_event_handler_unregister(WIFI_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb)) {
+    log_e("esp_event_handler_unregister for WIFI_EVENT Failed!");
+    return false;
+  }
 
-    WiFiEventCbList() : id(current_id++), cb(NULL), fcb(NULL), scb(NULL), provcb(NULL), event(SYSTEM_EVENT_WIFI_READY) {}
-} WiFiEventCbList_t;
-wifi_event_id_t WiFiEventCbList::current_id = 1;
+#if !CONFIG_ESP_WIFI_REMOTE_ENABLED
+  if (esp_event_handler_unregister(SC_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb)) {
+    log_e("esp_event_handler_unregister for SC_EVENT Failed!");
+    return false;
+  }
 
+#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI
+  if (esp_event_handler_unregister(NETWORK_PROV_EVENT, ESP_EVENT_ANY_ID, &_arduino_event_cb)) {
+    log_e("esp_event_handler_unregister for NETWORK_PROV_EVENT Failed!");
+    return false;
+  }
+#endif
+#endif
 
-// arduino dont like std::vectors move static here
-static std::vector<WiFiEventCbList_t> cbEventList;
+  return true;
+}
 
-bool WiFiGenericClass::_persistent = true;
-bool WiFiGenericClass::_long_range = false;
-wifi_mode_t WiFiGenericClass::_forceSleepLastMode = WIFI_MODE_NULL;
+/*
+ * WiFi INIT
+ * */
 
-WiFiGenericClass::WiFiGenericClass()
-{
+static bool lowLevelInitDone = false;
+bool WiFiGenericClass::_wifiUseStaticBuffers = false;
 
+bool WiFiGenericClass::useStaticBuffers() {
+  return _wifiUseStaticBuffers;
 }
 
-int WiFiGenericClass::setStatusBits(int bits){
-    if(!_network_event_group){
-        return 0;
-    }
-    return xEventGroupSetBits(_network_event_group, bits);
+void WiFiGenericClass::useStaticBuffers(bool bufferMode) {
+  if (lowLevelInitDone) {
+    log_w("WiFi already started. Call WiFi.mode(WIFI_MODE_NULL) before setting Static Buffer Mode.");
+  }
+  _wifiUseStaticBuffers = bufferMode;
 }
 
-int WiFiGenericClass::clearStatusBits(int bits){
-    if(!_network_event_group){
-        return 0;
-    }
-    return xEventGroupClearBits(_network_event_group, bits);
-}
+// Temporary fix to ensure that CDC+JTAG stay on on ESP32-C3
+#if CONFIG_IDF_TARGET_ESP32C3
+extern "C" void phy_bbpll_en_usb(bool en);
+#endif
 
-int WiFiGenericClass::getStatusBits(){
-    if(!_network_event_group){
-        return 0;
-    }
-    return xEventGroupGetBits(_network_event_group);
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+extern "C" {
+//#include "esp_hosted.h"
+#include "esp_hosted_transport_config.h"
+extern esp_err_t esp_hosted_init();
+extern esp_err_t esp_hosted_deinit();
+};
+static bool hosted_initialized = false;
+
+static bool wifiHostedInit() {
+  if (!hosted_initialized) {
+    hosted_initialized = true;
+    struct esp_hosted_sdio_config conf = INIT_DEFAULT_HOST_SDIO_CONFIG();
+    conf.pin_clk.pin = CONFIG_ESP_SDIO_PIN_CLK;
+    conf.pin_cmd.pin = CONFIG_ESP_SDIO_PIN_CMD;
+    conf.pin_d0.pin = CONFIG_ESP_SDIO_PIN_D0;
+    conf.pin_d1.pin = CONFIG_ESP_SDIO_PIN_D1;
+    conf.pin_d2.pin = CONFIG_ESP_SDIO_PIN_D2;
+    conf.pin_d3.pin = CONFIG_ESP_SDIO_PIN_D3;
+    //conf.pin_rst.pin = CONFIG_ESP_SDIO_GPIO_RESET_SLAVE;
+    // esp_hosted_sdio_set_config() will fail on second attempt but here temporarily to not cause exception on reinit
+    if (esp_hosted_sdio_set_config(&conf) != ESP_OK || esp_hosted_init() != ESP_OK) {
+      log_e("esp_hosted_init failed!");
+      hosted_initialized = false;
+      return false;
+    }
+    log_v("ESP-HOSTED initialized!");
+  }
+  // Attach pins to PeriMan here
+  // Slave chip model is CONFIG_IDF_SLAVE_TARGET
+  // CONFIG_ESP_SDIO_PIN_CMD
+  // CONFIG_ESP_SDIO_PIN_CLK
+  // CONFIG_ESP_SDIO_PIN_D0
+  // CONFIG_ESP_SDIO_PIN_D1
+  // CONFIG_ESP_SDIO_PIN_D2
+  // CONFIG_ESP_SDIO_PIN_D3
+  // CONFIG_ESP_SDIO_GPIO_RESET_SLAVE
+
+  return true;
 }
+#endif
 
-int WiFiGenericClass::waitStatusBits(int bits, uint32_t timeout_ms){
-    if(!_network_event_group){
-        return 0;
+bool wifiLowLevelInit(bool persistent) {
+  if (!lowLevelInitDone) {
+    lowLevelInitDone = true;
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+    if (!wifiHostedInit()) {
+      lowLevelInitDone = false;
+      return lowLevelInitDone;
     }
-    return xEventGroupWaitBits(
-        _network_event_group,    // The event group being tested.
-        bits,  // The bits within the event group to wait for.
-        pdFALSE,         // BIT_0 and BIT_4 should be cleared before returning.
-        pdTRUE,        // Don't wait for both bits, either bit will do.
-        timeout_ms / portTICK_PERIOD_MS ) & bits; // Wait a maximum of 100ms for either bit to be set.
-}
-
-/**
- * set callback function
- * @param cbEvent WiFiEventCb
- * @param event optional filter (WIFI_EVENT_MAX is all events)
- */
-wifi_event_id_t WiFiGenericClass::onEvent(WiFiProvEventCb cbEvent, system_event_id_t event)
-{
-    if(!cbEvent){
-        return 0;
+#endif
+    if (!Network.begin()) {
+      lowLevelInitDone = false;
+      return lowLevelInitDone;
     }
-    WiFiEventCbList_t newEventHandler;
-    newEventHandler.cb = NULL;
-    newEventHandler.fcb = NULL;
-    newEventHandler.scb = NULL;
-    newEventHandler.provcb = cbEvent;
-    newEventHandler.event = event;
-    cbEventList.push_back(newEventHandler);
-    return newEventHandler.id;
-}
-wifi_event_id_t WiFiGenericClass::onEvent(WiFiEventCb cbEvent, system_event_id_t event)
-{
-    if(!cbEvent) {
-        return 0;
+
+    wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
+
+    if (!WiFiGenericClass::useStaticBuffers()) {
+      cfg.static_tx_buf_num = 0;
+      cfg.dynamic_tx_buf_num = 32;
+      cfg.tx_buf_type = 1;
+      cfg.cache_tx_buf_num = 4;  // can't be zero!
+      cfg.static_rx_buf_num = 4;
+      cfg.dynamic_rx_buf_num = 32;
     }
-    WiFiEventCbList_t newEventHandler;
-    newEventHandler.cb = cbEvent;
-    newEventHandler.fcb = NULL;
-    newEventHandler.scb = NULL;
-    newEventHandler.provcb = NULL;
-    newEventHandler.event = event;
-    cbEventList.push_back(newEventHandler);
-    return newEventHandler.id;
-}
-
-wifi_event_id_t WiFiGenericClass::onEvent(WiFiEventFuncCb cbEvent, system_event_id_t event)
-{
-    if(!cbEvent) {
-        return 0;
+
+    esp_err_t err = esp_wifi_init(&cfg);
+    if (err) {
+      log_e("esp_wifi_init 0x%x: %s", err, esp_err_to_name(err));
+      lowLevelInitDone = false;
+      return lowLevelInitDone;
     }
-    WiFiEventCbList_t newEventHandler;
-    newEventHandler.cb = NULL;
-    newEventHandler.fcb = cbEvent;
-    newEventHandler.scb = NULL;
-    newEventHandler.provcb = NULL;
-    newEventHandler.event = event;
-    cbEventList.push_back(newEventHandler);
-    return newEventHandler.id;
-}
-
-wifi_event_id_t WiFiGenericClass::onEvent(WiFiEventSysCb cbEvent, system_event_id_t event)
-{
-    if(!cbEvent) {
-        return 0;
+// Temporary fix to ensure that CDC+JTAG stay on on ESP32-C3
+#if CONFIG_IDF_TARGET_ESP32C3
+    phy_bbpll_en_usb(true);
+#endif
+    if (!persistent) {
+      lowLevelInitDone = esp_wifi_set_storage(WIFI_STORAGE_RAM) == ESP_OK;
+    }
+    if (lowLevelInitDone) {
+      initWiFiEvents();
+      if (esp_netifs[ESP_IF_WIFI_AP] == NULL) {
+        esp_netifs[ESP_IF_WIFI_AP] = esp_netif_create_default_wifi_ap();
+      }
+      if (esp_netifs[ESP_IF_WIFI_STA] == NULL) {
+        esp_netifs[ESP_IF_WIFI_STA] = esp_netif_create_default_wifi_sta();
+      }
+
+      arduino_event_t arduino_event;
+      arduino_event.event_id = ARDUINO_EVENT_WIFI_READY;
+      Network.postEvent(&arduino_event);
+    }
+  }
+  return lowLevelInitDone;
+}
+
+static bool wifiLowLevelDeinit() {
+  if (lowLevelInitDone) {
+    lowLevelInitDone = false;
+    deinitWiFiEvents();
+    if (esp_netifs[ESP_IF_WIFI_AP] != NULL) {
+      esp_netif_destroy_default_wifi(esp_netifs[ESP_IF_WIFI_AP]);
+      esp_netifs[ESP_IF_WIFI_AP] = NULL;
+    }
+    if (esp_netifs[ESP_IF_WIFI_STA] != NULL) {
+      esp_netif_destroy_default_wifi(esp_netifs[ESP_IF_WIFI_STA]);
+      esp_netifs[ESP_IF_WIFI_STA] = NULL;
+    }
+    lowLevelInitDone = !(esp_wifi_deinit() == ESP_OK);
+    if (!lowLevelInitDone) {
+      arduino_event_t arduino_event;
+      arduino_event.event_id = ARDUINO_EVENT_WIFI_OFF;
+      Network.postEvent(&arduino_event);
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+      if (hosted_initialized && esp_hosted_deinit() == ESP_OK) {
+        hosted_initialized = false;
+        log_v("ESP-HOSTED uninitialized!");
+        // detach SDIO pins from PeriMan
+      }
+#endif
     }
-    WiFiEventCbList_t newEventHandler;
-    newEventHandler.cb = NULL;
-    newEventHandler.fcb = NULL;
-    newEventHandler.scb = cbEvent;
-    newEventHandler.provcb = NULL;
-    newEventHandler.event = event;
-    cbEventList.push_back(newEventHandler);
-    return newEventHandler.id;
+  }
+  return !lowLevelInitDone;
 }
 
-/**
- * removes a callback form event handler
- * @param cbEvent WiFiEventCb
- * @param event optional filter (WIFI_EVENT_MAX is all events)
- */
-void WiFiGenericClass::removeEvent(WiFiEventCb cbEvent, system_event_id_t event)
-{
-    if(!cbEvent) {
-        return;
-    }
+static bool _esp_wifi_started = false;
 
-    for(uint32_t i = 0; i < cbEventList.size(); i++) {
-        WiFiEventCbList_t entry = cbEventList[i];
-        if(entry.cb == cbEvent && entry.event == event) {
-            cbEventList.erase(cbEventList.begin() + i);
-        }
-    }
+static bool espWiFiStart() {
+  if (_esp_wifi_started) {
+    return true;
+  }
+  _esp_wifi_started = true;
+  esp_err_t err = esp_wifi_start();
+  if (err != ESP_OK) {
+    _esp_wifi_started = false;
+    log_e("esp_wifi_start 0x%x: %s", err, esp_err_to_name(err));
+    return _esp_wifi_started;
+  }
+  return _esp_wifi_started;
 }
 
-void WiFiGenericClass::removeEvent(WiFiEventSysCb cbEvent, system_event_id_t event)
-{
-    if(!cbEvent) {
-        return;
-    }
+static bool espWiFiStop() {
+  esp_err_t err;
+  if (!_esp_wifi_started) {
+    return true;
+  }
+  _esp_wifi_started = false;
+  err = esp_wifi_stop();
+  if (err) {
+    log_e("Could not stop WiFi! 0x%x: %s", err, esp_err_to_name(err));
+    _esp_wifi_started = true;
+    return false;
+  }
+  return wifiLowLevelDeinit();
+}
 
-    for(uint32_t i = 0; i < cbEventList.size(); i++) {
-        WiFiEventCbList_t entry = cbEventList[i];
-        if(entry.scb == cbEvent && entry.event == event) {
-            cbEventList.erase(cbEventList.begin() + i);
-        }
-    }
+// -----------------------------------------------------------------------------------------------------------------------
+// ------------------------------------------------- Generic WiFi function -----------------------------------------------
+// -----------------------------------------------------------------------------------------------------------------------
+
+bool WiFiGenericClass::_persistent = true;
+bool WiFiGenericClass::_long_range = false;
+wifi_mode_t WiFiGenericClass::_forceSleepLastMode = WIFI_MODE_NULL;
+#if CONFIG_IDF_TARGET_ESP32S2
+wifi_ps_type_t WiFiGenericClass::_sleepEnabled = WIFI_PS_NONE;
+#else
+wifi_ps_type_t WiFiGenericClass::_sleepEnabled = WIFI_PS_MIN_MODEM;
+#endif
+
+WiFiGenericClass::WiFiGenericClass() {}
+
+const char *WiFiGenericClass::disconnectReasonName(wifi_err_reason_t reason) {
+  return WiFi.STA.disconnectReasonName(reason);
 }
 
-void WiFiGenericClass::removeEvent(wifi_event_id_t id)
-{
-    for(uint32_t i = 0; i < cbEventList.size(); i++) {
-        WiFiEventCbList_t entry = cbEventList[i];
-        if(entry.id == id) {
-            cbEventList.erase(cbEventList.begin() + i);
-        }
-    }
+const char *WiFiGenericClass::eventName(arduino_event_id_t id) {
+  return Network.eventName(id);
+}
+
+const char *WiFiGenericClass::getHostname() {
+  return NetworkManager::getHostname();
+}
+
+bool WiFiGenericClass::setHostname(const char *hostname) {
+  return NetworkManager::setHostname(hostname);
 }
 
 /**
  * callback for WiFi events
  * @param arg
  */
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-const char * system_event_names[] = { "WIFI_READY", "SCAN_DONE", "STA_START", "STA_STOP", "STA_CONNECTED", "STA_DISCONNECTED", "STA_AUTHMODE_CHANGE", "STA_GOT_IP", "STA_LOST_IP", "STA_WPS_ER_SUCCESS", "STA_WPS_ER_FAILED", "STA_WPS_ER_TIMEOUT", "STA_WPS_ER_PIN", "STA_WPS_ER_PBC_OVERLAP", "AP_START", "AP_STOP", "AP_STACONNECTED", "AP_STADISCONNECTED", "AP_STAIPASSIGNED", "AP_PROBEREQRECVED", "GOT_IP6", "ETH_START", "ETH_STOP", "ETH_CONNECTED", "ETH_DISCONNECTED", "ETH_GOT_IP", "MAX"};
-#endif
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_WARN
-const char * system_event_reasons[] = { "UNSPECIFIED", "AUTH_EXPIRE", "AUTH_LEAVE", "ASSOC_EXPIRE", "ASSOC_TOOMANY", "NOT_AUTHED", "NOT_ASSOCED", "ASSOC_LEAVE", "ASSOC_NOT_AUTHED", "DISASSOC_PWRCAP_BAD", "DISASSOC_SUPCHAN_BAD", "UNSPECIFIED", "IE_INVALID", "MIC_FAILURE", "4WAY_HANDSHAKE_TIMEOUT", "GROUP_KEY_UPDATE_TIMEOUT", "IE_IN_4WAY_DIFFERS", "GROUP_CIPHER_INVALID", "PAIRWISE_CIPHER_INVALID", "AKMP_INVALID", "UNSUPP_RSN_IE_VERSION", "INVALID_RSN_IE_CAP", "802_1X_AUTH_FAILED", "CIPHER_SUITE_REJECTED", "BEACON_TIMEOUT", "NO_AP_FOUND", "AUTH_FAIL", "ASSOC_FAIL", "HANDSHAKE_TIMEOUT", "CONNECTION_FAIL" };
-#define reason2str(r) ((r>176)?system_event_reasons[r-176]:system_event_reasons[r-1])
+void WiFiGenericClass::_eventCallback(arduino_event_t *event) {
+  if (!event) {
+    return;  //Null would crash this function
+  }
+
+  // log_d("Arduino Event: %d - %s", event->event_id, WiFi.eventName(event->event_id));
+  if (event->event_id == ARDUINO_EVENT_WIFI_SCAN_DONE) {
+    WiFiScanClass::_scanDone();
+#if !CONFIG_ESP_WIFI_REMOTE_ENABLED
+  } else if (event->event_id == ARDUINO_EVENT_SC_GOT_SSID_PSWD) {
+    WiFi.begin(
+      (const char *)event->event_info.sc_got_ssid_pswd.ssid, (const char *)event->event_info.sc_got_ssid_pswd.password, 0,
+      ((event->event_info.sc_got_ssid_pswd.bssid_set == true) ? event->event_info.sc_got_ssid_pswd.bssid : NULL)
+    );
+  } else if (event->event_id == ARDUINO_EVENT_SC_SEND_ACK_DONE) {
+    esp_smartconfig_stop();
+    WiFiSTAClass::_smartConfigDone = true;
 #endif
-esp_err_t WiFiGenericClass::_eventCallback(void *arg, system_event_t *event, wifi_prov_event_t *prov_event)
-{
-    if(WiFi.isProvEnabled()) {
-        wifi_prov_mgr_event_handler(arg,event);        
-    }
-    if(event->event_id < 26) {
-        log_d("Event: %d - %s", event->event_id, system_event_names[event->event_id]);
-    }
-    if(event->event_id == SYSTEM_EVENT_SCAN_DONE) {
-        WiFiScanClass::_scanDone();
-
-    } else if(event->event_id == SYSTEM_EVENT_STA_START) {
-        WiFiSTAClass::_setStatus(WL_DISCONNECTED);
-        setStatusBits(STA_STARTED_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_STA_STOP) {
-        WiFiSTAClass::_setStatus(WL_NO_SHIELD);
-        clearStatusBits(STA_STARTED_BIT | STA_CONNECTED_BIT | STA_HAS_IP_BIT | STA_HAS_IP6_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_STA_CONNECTED) {
-        WiFiSTAClass::_setStatus(WL_IDLE_STATUS);
-        setStatusBits(STA_CONNECTED_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_STA_DISCONNECTED) {
-        uint8_t reason = event->event_info.disconnected.reason;
-        log_w("Reason: %u - %s", reason, reason2str(reason));
-        if(reason == WIFI_REASON_NO_AP_FOUND) {
-            WiFiSTAClass::_setStatus(WL_NO_SSID_AVAIL);
-        } else if(reason == WIFI_REASON_AUTH_FAIL || reason == WIFI_REASON_ASSOC_FAIL) {
-            WiFiSTAClass::_setStatus(WL_CONNECT_FAILED);
-        } else if(reason == WIFI_REASON_BEACON_TIMEOUT || reason == WIFI_REASON_HANDSHAKE_TIMEOUT) {
-            WiFiSTAClass::_setStatus(WL_CONNECTION_LOST);
-        } else if(reason == WIFI_REASON_AUTH_EXPIRE) {
-
-        } else {
-            WiFiSTAClass::_setStatus(WL_DISCONNECTED);
-        }
-        clearStatusBits(STA_CONNECTED_BIT | STA_HAS_IP_BIT | STA_HAS_IP6_BIT);
-        if(((reason == WIFI_REASON_AUTH_EXPIRE) ||
-            (reason >= WIFI_REASON_BEACON_TIMEOUT && reason != WIFI_REASON_AUTH_FAIL)) &&
-            WiFi.getAutoReconnect())
-        {
-            WiFi.disconnect();
-            WiFi.begin();
-        }
-    } else if(event->event_id == SYSTEM_EVENT_STA_GOT_IP) {
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-        uint8_t * ip = (uint8_t *)&(event->event_info.got_ip.ip_info.ip.addr);
-        uint8_t * mask = (uint8_t *)&(event->event_info.got_ip.ip_info.netmask.addr);
-        uint8_t * gw = (uint8_t *)&(event->event_info.got_ip.ip_info.gw.addr);
-        log_d("STA IP: %u.%u.%u.%u, MASK: %u.%u.%u.%u, GW: %u.%u.%u.%u",
-            ip[0], ip[1], ip[2], ip[3],
-            mask[0], mask[1], mask[2], mask[3],
-            gw[0], gw[1], gw[2], gw[3]);
-#endif
-        WiFiSTAClass::_setStatus(WL_CONNECTED);
-        setStatusBits(STA_HAS_IP_BIT | STA_CONNECTED_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_STA_LOST_IP) {
-        WiFiSTAClass::_setStatus(WL_IDLE_STATUS);
-        clearStatusBits(STA_HAS_IP_BIT);
-
-    } else if(event->event_id == SYSTEM_EVENT_AP_START) {
-        setStatusBits(AP_STARTED_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_AP_STOP) {
-        clearStatusBits(AP_STARTED_BIT | AP_HAS_CLIENT_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_AP_STACONNECTED) {
-        setStatusBits(AP_HAS_CLIENT_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_AP_STADISCONNECTED) {
-        wifi_sta_list_t clients;
-        if(esp_wifi_ap_get_sta_list(&clients) != ESP_OK || !clients.num){
-            clearStatusBits(AP_HAS_CLIENT_BIT);
-        }
-
-    } else if(event->event_id == SYSTEM_EVENT_ETH_START) {
-        setStatusBits(ETH_STARTED_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_ETH_STOP) {
-        clearStatusBits(ETH_STARTED_BIT | ETH_CONNECTED_BIT | ETH_HAS_IP_BIT | ETH_HAS_IP6_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_ETH_CONNECTED) {
-        setStatusBits(ETH_CONNECTED_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_ETH_DISCONNECTED) {
-        clearStatusBits(ETH_CONNECTED_BIT | ETH_HAS_IP_BIT | ETH_HAS_IP6_BIT);
-    } else if(event->event_id == SYSTEM_EVENT_ETH_GOT_IP) {
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-        uint8_t * ip = (uint8_t *)&(event->event_info.got_ip.ip_info.ip.addr);
-        uint8_t * mask = (uint8_t *)&(event->event_info.got_ip.ip_info.netmask.addr);
-        uint8_t * gw = (uint8_t *)&(event->event_info.got_ip.ip_info.gw.addr);
-        log_d("ETH IP: %u.%u.%u.%u, MASK: %u.%u.%u.%u, GW: %u.%u.%u.%u",
-            ip[0], ip[1], ip[2], ip[3],
-            mask[0], mask[1], mask[2], mask[3],
-            gw[0], gw[1], gw[2], gw[3]);
-#endif
-        setStatusBits(ETH_CONNECTED_BIT | ETH_HAS_IP_BIT);
-
-    } else if(event->event_id == SYSTEM_EVENT_GOT_IP6) {
-        if(event->event_info.got_ip6.if_index == TCPIP_ADAPTER_IF_AP){
-            setStatusBits(AP_HAS_IP6_BIT);
-        } else if(event->event_info.got_ip6.if_index == TCPIP_ADAPTER_IF_STA){
-            setStatusBits(STA_CONNECTED_BIT | STA_HAS_IP6_BIT);
-        } else if(event->event_info.got_ip6.if_index == TCPIP_ADAPTER_IF_ETH){
-            setStatusBits(ETH_CONNECTED_BIT | ETH_HAS_IP6_BIT);
-        }
-    }
- 
-    for(uint32_t i = 0; i < cbEventList.size(); i++) {
-        WiFiEventCbList_t entry = cbEventList[i];
-        if(entry.cb || entry.fcb || entry.scb) {
-            if(entry.event == (system_event_id_t) event->event_id || entry.event == SYSTEM_EVENT_MAX) {
-                if(entry.cb) {
-                    entry.cb((system_event_id_t) event->event_id);
-                } else if(entry.fcb) {
-                    entry.fcb((system_event_id_t) event->event_id, (system_event_info_t) event->event_info);
-                } else {
-                    entry.scb(event);
-                }
-            }
-        }
-
-        if(entry.provcb) {
-            entry.provcb(event,prov_event);
-        }
-    }
-    return ESP_OK;
+  }
 }
 
 /**
  * Return the current channel associated with the network
  * @return channel (1-13)
  */
-int32_t WiFiGenericClass::channel(void)
-{
-    uint8_t primaryChan = 0;
-    wifi_second_chan_t secondChan = WIFI_SECOND_CHAN_NONE;
-    if(!lowLevelInitDone){
-        return primaryChan;
-    }
-    esp_wifi_get_channel(&primaryChan, &secondChan);
+int32_t WiFiGenericClass::channel(void) {
+  uint8_t primaryChan = 0;
+  wifi_second_chan_t secondChan = WIFI_SECOND_CHAN_NONE;
+  if (!lowLevelInitDone) {
     return primaryChan;
+  }
+  esp_wifi_get_channel(&primaryChan, &secondChan);
+  return primaryChan;
 }
 
+/**
+ * Set the WiFi channel configuration
+ * @param primary primary channel. Depending on the region, not all channels may be available.
+ * @param secondary secondary channel (WIFI_SECOND_CHAN_NONE, WIFI_SECOND_CHAN_ABOVE, WIFI_SECOND_CHAN_BELOW)
+ * @return 0 on success, otherwise error
+ */
+int WiFiGenericClass::setChannel(uint8_t primary, wifi_second_chan_t secondary) {
+  wifi_country_t country;
+  esp_err_t ret;
+
+  ret = esp_wifi_get_country(&country);
+  if (ret != ESP_OK) {
+    log_e("Failed to get country info 0x%x: %s", ret, esp_err_to_name(ret));
+    return ret;
+  }
+
+  uint8_t min_chan = country.schan;
+  uint8_t max_chan = min_chan + country.nchan - 1;
+
+  if (primary < min_chan || primary > max_chan) {
+    log_e("Invalid primary channel: %d. Valid range is %d-%d for country %s", primary, min_chan, max_chan, country.cc);
+    return ESP_ERR_INVALID_ARG;
+  }
+
+  ret = esp_wifi_set_channel(primary, secondary);
+  if (ret != ESP_OK) {
+    log_e("Failed to set channel 0x%x: %s", ret, esp_err_to_name(ret));
+    return ret;
+  }
+
+  return ESP_OK;
+}
 
 /**
  * store WiFi config in SDK flash area
  * @param persistent
  */
-void WiFiGenericClass::persistent(bool persistent)
-{
-    _persistent = persistent;
+void WiFiGenericClass::persistent(bool persistent) {
+  _persistent = persistent;
 }
 
-
 /**
  * enable WiFi long range mode
  * @param enable
  */
-void WiFiGenericClass::enableLongRange(bool enable)
-{
-    _long_range = enable;
+void WiFiGenericClass::enableLongRange(bool enable) {
+  _long_range = enable;
 }
 
-
 /**
  * set new mode
  * @param m WiFiMode_t
  */
-bool WiFiGenericClass::mode(wifi_mode_t m)
-{
-    wifi_mode_t cm = getMode();
-    if(cm == m) {
-        return true;
-    }
-    if(!cm && m){
-        if(!wifiLowLevelInit(_persistent)){
-            return false;
-        }
-    } else if(cm && !m){
-        return espWiFiStop();
+bool WiFiGenericClass::mode(wifi_mode_t m) {
+  wifi_mode_t cm = getMode();
+  if (cm == m) {
+    return true;
+  }
+  if (!cm && m) {
+    // Turn ON WiFi
+    if (!wifiLowLevelInit(_persistent)) {
+      return false;
+    }
+    Network.onSysEvent(_eventCallback);
+  }
+
+  if (((m & WIFI_MODE_STA) != 0) && ((cm & WIFI_MODE_STA) == 0)) {
+    // we are enabling STA interface
+    WiFi.STA.onEnable();
+  }
+  if (((m & WIFI_MODE_AP) != 0) && ((cm & WIFI_MODE_AP) == 0)) {
+    // we are enabling AP interface
+    WiFi.AP.onEnable();
+  }
+
+  if (cm && !m) {
+    // Turn OFF WiFi
+    if (!espWiFiStop()) {
+      return false;
+    }
+    if ((cm & WIFI_MODE_STA) != 0) {
+      // we are disabling STA interface
+      WiFi.STA.onDisable();
+    }
+    if ((cm & WIFI_MODE_AP) != 0) {
+      // we are disabling AP interface
+      WiFi.AP.onDisable();
+    }
+    Network.removeEvent(_eventCallback);
+    return true;
+  }
+
+  esp_err_t err;
+  if (((m & WIFI_MODE_STA) != 0) && ((cm & WIFI_MODE_STA) == 0)) {
+    err = esp_netif_set_hostname(esp_netifs[ESP_IF_WIFI_STA], NetworkManager::getHostname());
+    if (err) {
+      log_e("Could not set hostname! 0x%x: %s", err, esp_err_to_name(err));
+      return false;
+    }
+  }
+  err = esp_wifi_set_mode(m);
+  if (err) {
+    log_e("Could not set mode! 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  if (((m & WIFI_MODE_STA) == 0) && ((cm & WIFI_MODE_STA) != 0)) {
+    // we are disabling STA interface (but AP is ON)
+    WiFi.STA.onDisable();
+  }
+  if (((m & WIFI_MODE_AP) == 0) && ((cm & WIFI_MODE_AP) != 0)) {
+    // we are disabling AP interface (but STA is ON)
+    WiFi.AP.onDisable();
+  }
+
+  if (_long_range) {
+    if (m & WIFI_MODE_STA) {
+      err = esp_wifi_set_protocol(WIFI_IF_STA, WIFI_PROTOCOL_LR);
+      if (err != ESP_OK) {
+        log_e("Could not enable long range on STA! 0x%x: %s", err, esp_err_to_name(err));
+        return false;
+      }
     }
-
-    esp_err_t err;
-    err = esp_wifi_set_mode(m);
-    if(err){
-        log_e("Could not set mode! %d", err);
+    if (m & WIFI_MODE_AP) {
+      err = esp_wifi_set_protocol(WIFI_IF_AP, WIFI_PROTOCOL_LR);
+      if (err != ESP_OK) {
+        log_e("Could not enable long range on AP! 0x%x: %s", err, esp_err_to_name(err));
         return false;
+      }
     }
-    if(_long_range){
-        if(m & WIFI_MODE_STA){
-            err = esp_wifi_set_protocol(WIFI_IF_STA, WIFI_PROTOCOL_LR);
-            if(err != ESP_OK){
-                log_e("Could not enable long range on STA! %d", err);
-                return false;
-            }
+  } else {
+#if CONFIG_SOC_WIFI_HE_SUPPORT
+#define WIFI_PROTOCOL_DEFAULT (WIFI_PROTOCOL_11B | WIFI_PROTOCOL_11G | WIFI_PROTOCOL_11N | WIFI_PROTOCOL_11AX)
+#else
+#define WIFI_PROTOCOL_DEFAULT (WIFI_PROTOCOL_11B | WIFI_PROTOCOL_11G | WIFI_PROTOCOL_11N)
+#endif
+    uint32_t current_protocol = 0;
+    if (m & WIFI_MODE_STA) {
+      err = esp_wifi_get_protocol(WIFI_IF_STA, (uint8_t *)&current_protocol);
+      if (err == ESP_OK && current_protocol == WIFI_PROTOCOL_LR) {
+        log_v("Disabling long range on STA");
+        err = esp_wifi_set_protocol(WIFI_IF_STA, WIFI_PROTOCOL_DEFAULT);
+        if (err != ESP_OK) {
+          log_e("Could not disable long range on STA! 0x%x: %s", err, esp_err_to_name(err));
         }
-        if(m & WIFI_MODE_AP){
-            err = esp_wifi_set_protocol(WIFI_IF_AP, WIFI_PROTOCOL_LR);
-            if(err != ESP_OK){
-                log_e("Could not enable long range on AP! %d", err);
-                return false;
-            }
+      }
+    }
+    if (m & WIFI_MODE_AP) {
+      err = esp_wifi_get_protocol(WIFI_IF_AP, (uint8_t *)&current_protocol);
+      if (err == ESP_OK && current_protocol == WIFI_PROTOCOL_LR) {
+        log_v("Disabling long range on AP");
+        err = esp_wifi_set_protocol(WIFI_IF_AP, WIFI_PROTOCOL_DEFAULT);
+        if (err != ESP_OK) {
+          log_e("Could not disable long range on AP! 0x%x: %s", err, esp_err_to_name(err));
         }
+      }
     }
-    if(!espWiFiStart()){
-        return false;
-    }
-    return true;
+  }
+  if (!espWiFiStart()) {
+    return false;
+  }
+
+#ifdef BOARD_HAS_DUAL_ANTENNA
+  if (!setDualAntennaConfig(ANT1, ANT2, WIFI_RX_ANT_AUTO, WIFI_TX_ANT_AUTO)) {
+    log_e("Dual Antenna Config failed!");
+    return false;
+  }
+#endif
+
+  return true;
 }
 
 /**
  * get WiFi mode
  * @return WiFiMode
  */
-wifi_mode_t WiFiGenericClass::getMode()
-{
-    if(!lowLevelInitDone || !_esp_wifi_started){
-        return WIFI_MODE_NULL;
-    }
-    wifi_mode_t mode;
-    if(esp_wifi_get_mode(&mode) == ESP_ERR_WIFI_NOT_INIT){
-        log_w("WiFi not started");
-        return WIFI_MODE_NULL;
-    }
-    return mode;
+wifi_mode_t WiFiGenericClass::getMode() {
+  if (!lowLevelInitDone || !_esp_wifi_started) {
+    return WIFI_MODE_NULL;
+  }
+  wifi_mode_t mode;
+  if (esp_wifi_get_mode(&mode) != ESP_OK) {
+    log_w("WiFi not started");
+    return WIFI_MODE_NULL;
+  }
+  return mode;
 }
 
 /**
@@ -590,19 +659,18 @@ wifi_mode_t WiFiGenericClass::getMode()
  * @param enable bool
  * @return ok
  */
-bool WiFiGenericClass::enableSTA(bool enable)
-{
+bool WiFiGenericClass::enableSTA(bool enable) {
 
-    wifi_mode_t currentMode = getMode();
-    bool isEnabled = ((currentMode & WIFI_MODE_STA) != 0);
+  wifi_mode_t currentMode = getMode();
+  bool isEnabled = ((currentMode & WIFI_MODE_STA) != 0);
 
-    if(isEnabled != enable) {
-        if(enable) {
-            return mode((wifi_mode_t)(currentMode | WIFI_MODE_STA));
-        }
-        return mode((wifi_mode_t)(currentMode & (~WIFI_MODE_STA)));
+  if (isEnabled != enable) {
+    if (enable) {
+      return mode((wifi_mode_t)(currentMode | WIFI_MODE_STA));
     }
-    return true;
+    return mode((wifi_mode_t)(currentMode & (~WIFI_MODE_STA)));
+  }
+  return true;
 }
 
 /**
@@ -610,19 +678,18 @@ bool WiFiGenericClass::enableSTA(bool enable)
  * @param enable bool
  * @return ok
  */
-bool WiFiGenericClass::enableAP(bool enable)
-{
+bool WiFiGenericClass::enableAP(bool enable) {
 
-    wifi_mode_t currentMode = getMode();
-    bool isEnabled = ((currentMode & WIFI_MODE_AP) != 0);
+  wifi_mode_t currentMode = getMode();
+  bool isEnabled = ((currentMode & WIFI_MODE_AP) != 0);
 
-    if(isEnabled != enable) {
-        if(enable) {
-            return mode((wifi_mode_t)(currentMode | WIFI_MODE_AP));
-        }
-        return mode((wifi_mode_t)(currentMode & (~WIFI_MODE_AP)));
+  if (isEnabled != enable) {
+    if (enable) {
+      return mode((wifi_mode_t)(currentMode | WIFI_MODE_AP));
     }
-    return true;
+    return mode((wifi_mode_t)(currentMode & (~WIFI_MODE_AP)));
+  }
+  return true;
 }
 
 /**
@@ -630,13 +697,8 @@ bool WiFiGenericClass::enableAP(bool enable)
  * @param enable bool
  * @return ok
  */
-bool WiFiGenericClass::setSleep(bool enable)
-{
-    if((getMode() & WIFI_MODE_STA) == 0){
-        log_w("STA has not been started");
-        return false;
-    }
-    return esp_wifi_set_ps(enable?WIFI_PS_MIN_MODEM:WIFI_PS_NONE) == ESP_OK;
+bool WiFiGenericClass::setSleep(bool enabled) {
+  return setSleep(enabled ? WIFI_PS_MIN_MODEM : WIFI_PS_NONE);
 }
 
 /**
@@ -644,30 +706,27 @@ bool WiFiGenericClass::setSleep(bool enable)
  * @param mode wifi_ps_type_t
  * @return ok
  */
-bool WiFiGenericClass::setSleep(wifi_ps_type_t mode)
-{
-    if((getMode() & WIFI_MODE_STA) == 0){
-        log_w("STA has not been started");
+bool WiFiGenericClass::setSleep(wifi_ps_type_t sleepType) {
+  if (sleepType != _sleepEnabled) {
+    _sleepEnabled = sleepType;
+    if (WiFi.STA.started()) {
+      esp_err_t err = esp_wifi_set_ps(_sleepEnabled);
+      if (err != ESP_OK) {
+        log_e("esp_wifi_set_ps failed!: 0x%x: %s", err, esp_err_to_name(err));
         return false;
+      }
     }
-    return esp_wifi_set_ps(mode) == ESP_OK;
+    return true;
+  }
+  return false;
 }
 
 /**
  * get modem sleep enabled
  * @return true if modem sleep is enabled
  */
-bool WiFiGenericClass::getSleep()
-{
-    wifi_ps_type_t ps;
-    if((getMode() & WIFI_MODE_STA) == 0){
-        log_w("STA has not been started");
-        return false;
-    }
-    if(esp_wifi_get_ps(&ps) == ESP_OK){
-        return ps == WIFI_PS_MIN_MODEM;
-    }
-    return false;
+wifi_ps_type_t WiFiGenericClass::getSleep() {
+  return _sleepEnabled;
 }
 
 /**
@@ -675,110 +734,234 @@ bool WiFiGenericClass::getSleep()
  * @param power enum maximum wifi tx power
  * @return ok
  */
-bool WiFiGenericClass::setTxPower(wifi_power_t power){
-    if((getStatusBits() & (STA_STARTED_BIT | AP_STARTED_BIT)) == 0){
-        log_w("Neither AP or STA has been started");
-        return false;
-    }
-    return esp_wifi_set_max_tx_power(power) == ESP_OK;
-}
-
-wifi_power_t WiFiGenericClass::getTxPower(){
-    int8_t power;
-    if((getStatusBits() & (STA_STARTED_BIT | AP_STARTED_BIT)) == 0){
-        log_w("Neither AP or STA has been started");
-        return WIFI_POWER_19_5dBm;
-    }
-    if(esp_wifi_get_max_tx_power(&power)){
-        return WIFI_POWER_19_5dBm;
-    }
-    return (wifi_power_t)power;
+bool WiFiGenericClass::setTxPower(wifi_power_t power) {
+  if (!WiFi.STA.started() && !WiFi.AP.started()) {
+    log_w("Neither AP or STA has been started");
+    return false;
+  }
+  esp_err_t err = esp_wifi_set_max_tx_power(power);
+  if (err != ESP_OK) {
+    log_e("Failed to set TX Power: 0x%x: %s", err, esp_err_to_name(err));
+  }
+  return err == ESP_OK;
+}
+
+wifi_power_t WiFiGenericClass::getTxPower() {
+  int8_t power;
+  if (!WiFi.STA.started() && !WiFi.AP.started()) {
+    log_w("Neither AP or STA has been started");
+    return WIFI_POWER_19_5dBm;
+  }
+  esp_err_t err = esp_wifi_get_max_tx_power(&power);
+  if (err != ESP_OK) {
+    log_e("Failed to get TX Power: 0x%x: %s", err, esp_err_to_name(err));
+    return WIFI_POWER_19_5dBm;
+  }
+  return (wifi_power_t)power;
 }
 
-// -----------------------------------------------------------------------------------------------------------------------
-// ------------------------------------------------ Generic Network function ---------------------------------------------
-// -----------------------------------------------------------------------------------------------------------------------
-
 /**
- * DNS callback
- * @param name
- * @param ipaddr
- * @param callback_arg
+ * Initiate FTM Session.
+ * @param frm_count Number of FTM frames requested in terms of 4 or 8 bursts (allowed values - 0(No pref), 16, 24, 32, 64)
+ * @param burst_period Requested time period between consecutive FTM bursts in 100's of milliseconds (allowed values - 0(No pref), 2 - 255)
+ * @param channel Primary channel of the FTM Responder
+ * @param mac MAC address of the FTM Responder
+ * @return true on success
  */
-static void wifi_dns_found_callback(const char *name, const ip_addr_t *ipaddr, void *callback_arg)
-{
-    if(ipaddr) {
-        (*reinterpret_cast<IPAddress*>(callback_arg)) = ipaddr->u_addr.ip4.addr;
-    }
-    xEventGroupSetBits(_network_event_group, WIFI_DNS_DONE_BIT);
+bool WiFiGenericClass::initiateFTM(uint8_t frm_count, uint16_t burst_period, uint8_t channel, const uint8_t *mac) {
+  wifi_ftm_initiator_cfg_t ftmi_cfg = {
+    .resp_mac = {0, 0, 0, 0, 0, 0}, .channel = channel, .frm_count = frm_count, .burst_period = burst_period, .use_get_report_api = true
+  };
+  if (mac != NULL) {
+    memcpy(ftmi_cfg.resp_mac, mac, 6);
+  }
+  // Request FTM session with the Responder
+  esp_err_t err = esp_wifi_ftm_initiate_session(&ftmi_cfg);
+  if (ESP_OK != err) {
+    log_e("Failed to initiate FTM session: 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+  return true;
 }
 
 /**
- * Resolve the given hostname to an IP address.
- * @param aHostname     Name to be resolved
- * @param aResult       IPAddress structure to store the returned IP address
- * @return 1 if aIPAddrString was successfully converted to an IP address,
- *          else error code
+ * Configure Dual antenna.
+ * @param gpio_ant1 Configure the GPIO number for the antenna 1 connected to the RF switch (default GPIO2 on ESP32-WROOM-DA)
+ * @param gpio_ant2 Configure the GPIO number for the antenna 2 connected to the RF switch (default GPIO25 on ESP32-WROOM-DA)
+ * @param rx_mode Set the RX antenna mode. See wifi_rx_ant_t for the options.
+ * @param tx_mode Set the TX antenna mode. See wifi_tx_ant_t for the options.
+ * @return true on success
  */
-int WiFiGenericClass::hostByName(const char* aHostname, IPAddress& aResult)
-{
-    ip_addr_t addr;
-    aResult = static_cast<uint32_t>(0);
-    waitStatusBits(WIFI_DNS_IDLE_BIT, 16000);
-    clearStatusBits(WIFI_DNS_IDLE_BIT | WIFI_DNS_DONE_BIT);
-    err_t err = dns_gethostbyname(aHostname, &addr, &wifi_dns_found_callback, &aResult);
-    if(err == ERR_OK && addr.u_addr.ip4.addr) {
-        aResult = addr.u_addr.ip4.addr;
-    } else if(err == ERR_INPROGRESS) {
-        waitStatusBits(WIFI_DNS_DONE_BIT, 15000);  //real internal timeout in lwip library is 14[s]
-        clearStatusBits(WIFI_DNS_DONE_BIT);
-    }
-    setStatusBits(WIFI_DNS_IDLE_BIT);
-    if((uint32_t)aResult == 0){
-        log_e("DNS Failed for %s", aHostname);
-    }
-    return (uint32_t)aResult != 0;
+bool WiFiGenericClass::setDualAntennaConfig(uint8_t gpio_ant1, uint8_t gpio_ant2, wifi_rx_ant_t rx_mode, wifi_tx_ant_t tx_mode) {
+#if !CONFIG_ESP_WIFI_REMOTE_ENABLED
+
+  esp_phy_ant_gpio_config_t wifi_ant_io;
+
+  esp_err_t err = esp_phy_get_ant_gpio(&wifi_ant_io);
+  if (ESP_OK != err) {
+    log_e("Failed to get antenna configuration: 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  wifi_ant_io.gpio_cfg[0].gpio_num = gpio_ant1;
+  wifi_ant_io.gpio_cfg[0].gpio_select = 1;
+  wifi_ant_io.gpio_cfg[1].gpio_num = gpio_ant2;
+  wifi_ant_io.gpio_cfg[1].gpio_select = 1;
+
+  err = esp_phy_set_ant_gpio(&wifi_ant_io);
+  if (ESP_OK != err) {
+    log_e("Failed to set antenna GPIO configuration: 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+
+  // Set antenna default configuration
+  esp_phy_ant_config_t ant_config = {
+    .rx_ant_mode = ESP_PHY_ANT_MODE_AUTO,
+    .rx_ant_default = ESP_PHY_ANT_MAX,  // Ignored in AUTO mode
+    .tx_ant_mode = ESP_PHY_ANT_MODE_AUTO,
+    .enabled_ant0 = 1,
+    .enabled_ant1 = 2,
+  };
+
+  switch (rx_mode) {
+    case WIFI_RX_ANT0: ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_ANT0; break;
+    case WIFI_RX_ANT1: ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_ANT1; break;
+    case WIFI_RX_ANT_AUTO:
+      log_i("TX Antenna will be automatically selected");
+      ant_config.rx_ant_default = ESP_PHY_ANT_ANT0;
+      ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_AUTO;
+      // Force TX for AUTO if RX is AUTO
+      ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_AUTO;
+      goto set_ant;
+      break;
+    default:
+      log_e("Invalid default antenna! Falling back to AUTO");
+      ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_AUTO;
+      break;
+  }
+
+  switch (tx_mode) {
+    case WIFI_TX_ANT0: ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_ANT0; break;
+    case WIFI_TX_ANT1: ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_ANT1; break;
+    case WIFI_TX_ANT_AUTO:
+      log_i("RX Antenna will be automatically selected");
+      ant_config.rx_ant_default = ESP_PHY_ANT_ANT0;
+      ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_AUTO;
+      // Force RX for AUTO if RX is AUTO
+      ant_config.rx_ant_mode = ESP_PHY_ANT_MODE_AUTO;
+      break;
+    default:
+      log_e("Invalid default antenna! Falling back to AUTO");
+      ant_config.rx_ant_default = ESP_PHY_ANT_ANT0;
+      ant_config.tx_ant_mode = ESP_PHY_ANT_MODE_AUTO;
+      break;
+  }
+
+set_ant:
+  err = esp_phy_set_ant(&ant_config);
+  if (ESP_OK != err) {
+    log_e("Failed to set antenna configuration: 0x%x: %s", err, esp_err_to_name(err));
+    return false;
+  }
+#endif
+  return true;
+}
+
+// -----------------------------------------------------------------------------------------------------------------------
+// ------------------------------------------------ Generic Network function ---------------------------------------------
+// -----------------------------------------------------------------------------------------------------------------------
+
+/*
+ * Deprecated Methods
+*/
+int WiFiGenericClass::hostByName(const char *aHostname, IPAddress &aResult) {
+  return Network.hostByName(aHostname, aResult);
 }
 
 IPAddress WiFiGenericClass::calculateNetworkID(IPAddress ip, IPAddress subnet) {
-	IPAddress networkID;
+  IPAddress networkID;
 
-	for (size_t i = 0; i < 4; i++)
-		networkID[i] = subnet[i] & ip[i];
+  for (size_t i = 0; i < 4; i++) {
+    networkID[i] = subnet[i] & ip[i];
+  }
 
-	return networkID;
+  return networkID;
 }
 
 IPAddress WiFiGenericClass::calculateBroadcast(IPAddress ip, IPAddress subnet) {
-    IPAddress broadcastIp;
-    
-    for (int i = 0; i < 4; i++)
-        broadcastIp[i] = ~subnet[i] | ip[i];
+  IPAddress broadcastIp;
 
-    return broadcastIp;
+  for (int i = 0; i < 4; i++) {
+    broadcastIp[i] = ~subnet[i] | ip[i];
+  }
+
+  return broadcastIp;
 }
 
 uint8_t WiFiGenericClass::calculateSubnetCIDR(IPAddress subnetMask) {
-	uint8_t CIDR = 0;
-
-	for (uint8_t i = 0; i < 4; i++) {
-		if (subnetMask[i] == 0x80)  // 128
-			CIDR += 1;
-		else if (subnetMask[i] == 0xC0)  // 192
-			CIDR += 2;
-		else if (subnetMask[i] == 0xE0)  // 224
-			CIDR += 3;
-		else if (subnetMask[i] == 0xF0)  // 242
-			CIDR += 4;
-		else if (subnetMask[i] == 0xF8)  // 248
-			CIDR += 5;
-		else if (subnetMask[i] == 0xFC)  // 252
-			CIDR += 6;
-		else if (subnetMask[i] == 0xFE)  // 254
-			CIDR += 7;
-		else if (subnetMask[i] == 0xFF)  // 255
-			CIDR += 8;
-	}
-
-	return CIDR;
+  uint8_t CIDR = 0;
+
+  for (uint8_t i = 0; i < 4; i++) {
+    if (subnetMask[i] == 0x80) {  // 128
+      CIDR += 1;
+    } else if (subnetMask[i] == 0xC0) {  // 192
+      CIDR += 2;
+    } else if (subnetMask[i] == 0xE0) {  // 224
+      CIDR += 3;
+    } else if (subnetMask[i] == 0xF0) {  // 242
+      CIDR += 4;
+    } else if (subnetMask[i] == 0xF8) {  // 248
+      CIDR += 5;
+    } else if (subnetMask[i] == 0xFC) {  // 252
+      CIDR += 6;
+    } else if (subnetMask[i] == 0xFE) {  // 254
+      CIDR += 7;
+    } else if (subnetMask[i] == 0xFF) {  // 255
+      CIDR += 8;
+    }
+  }
+
+  return CIDR;
+}
+
+wifi_event_id_t WiFiGenericClass::onEvent(WiFiEventCb cbEvent, arduino_event_id_t event) {
+  return Network.onEvent(cbEvent, event);
+}
+
+wifi_event_id_t WiFiGenericClass::onEvent(WiFiEventFuncCb cbEvent, arduino_event_id_t event) {
+  return Network.onEvent(cbEvent, event);
+}
+
+wifi_event_id_t WiFiGenericClass::onEvent(WiFiEventSysCb cbEvent, arduino_event_id_t event) {
+  return Network.onEvent(cbEvent, event);
+}
+
+void WiFiGenericClass::removeEvent(WiFiEventCb cbEvent, arduino_event_id_t event) {
+  Network.removeEvent(cbEvent, event);
 }
+
+void WiFiGenericClass::removeEvent(WiFiEventSysCb cbEvent, arduino_event_id_t event) {
+  Network.removeEvent(cbEvent, event);
+}
+
+void WiFiGenericClass::removeEvent(wifi_event_id_t id) {
+  Network.removeEvent(id);
+}
+
+int WiFiGenericClass::setStatusBits(int bits) {
+  return Network.setStatusBits(bits);
+}
+
+int WiFiGenericClass::clearStatusBits(int bits) {
+  return Network.clearStatusBits(bits);
+}
+
+int WiFiGenericClass::getStatusBits() {
+  return Network.getStatusBits();
+}
+
+int WiFiGenericClass::waitStatusBits(int bits, uint32_t timeout_ms) {
+  return Network.waitStatusBits(bits, timeout_ms);
+}
+
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiGeneric.h b/libraries/WiFi/src/WiFiGeneric.h
index 2cd2db4a890..ed216229ed4 100644
--- a/libraries/WiFi/src/WiFiGeneric.h
+++ b/libraries/WiFi/src/WiFiGeneric.h
@@ -20,121 +20,135 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#ifndef ESP32WIFIGENERIC_H_
-#define ESP32WIFIGENERIC_H_
+#pragma once
 
-#include <esp_err.h>
-#include <esp_event_loop.h>
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
+
+#include "esp_err.h"
+#include "esp_event.h"
 #include <functional>
 #include "WiFiType.h"
 #include "IPAddress.h"
-#include <wifi_provisioning/manager.h>
+#include "esp_smartconfig.h"
+#include "esp_netif_types.h"
+#if CONFIG_ETH_ENABLED
+#include "esp_eth_driver.h"
+#endif
+#if CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI
+#include "network_provisioning/manager.h"
+#endif
+#include "lwip/ip_addr.h"
+
+#include "Network.h"
+
+#define WiFiEventCb     NetworkEventCb
+#define WiFiEventFuncCb NetworkEventFuncCb
+#define WiFiEventSysCb  NetworkEventSysCb
+#define wifi_event_id_t network_event_handle_t
 
-typedef struct
-{
-     wifi_prov_cb_event_t event;
-     void *event_data;
-}wifi_prov_event_t;
+typedef enum {
+  WIFI_POWER_21dBm = 84,      // 21dBm
+  WIFI_POWER_20_5dBm = 82,    // 20.5dBm
+  WIFI_POWER_20dBm = 80,      // 20dBm
+  WIFI_POWER_19_5dBm = 78,    // 19.5dBm
+  WIFI_POWER_19dBm = 76,      // 19dBm
+  WIFI_POWER_18_5dBm = 74,    // 18.5dBm
+  WIFI_POWER_17dBm = 68,      // 17dBm
+  WIFI_POWER_15dBm = 60,      // 15dBm
+  WIFI_POWER_13dBm = 52,      // 13dBm
+  WIFI_POWER_11dBm = 44,      // 11dBm
+  WIFI_POWER_8_5dBm = 34,     // 8.5dBm
+  WIFI_POWER_7dBm = 28,       // 7dBm
+  WIFI_POWER_5dBm = 20,       // 5dBm
+  WIFI_POWER_2dBm = 8,        // 2dBm
+  WIFI_POWER_MINUS_1dBm = -4  // -1dBm
+} wifi_power_t;
 
-typedef struct
-{
-    wifi_prov_event_t *prov_event;
-    system_event_t *sys_event;
-}system_prov_event_t;
+typedef enum {
+  WIFI_RX_ANT0 = 0,
+  WIFI_RX_ANT1,
+  WIFI_RX_ANT_AUTO
+} wifi_rx_ant_t;
 
-typedef void (*WiFiEventCb)(system_event_id_t event);
-typedef std::function<void(system_event_id_t event, system_event_info_t info)> WiFiEventFuncCb;
-typedef void (*WiFiEventSysCb)(system_event_t *event);
-typedef void (*WiFiProvEventCb)(system_event_t *sys_event, wifi_prov_event_t *prov_event);
+typedef enum {
+  WIFI_TX_ANT0 = 0,
+  WIFI_TX_ANT1,
+  WIFI_TX_ANT_AUTO
+} wifi_tx_ant_t;
 
-typedef size_t wifi_event_id_t;
+class WiFiGenericClass {
+public:
+  WiFiGenericClass();
 
-typedef enum {
-    WIFI_POWER_19_5dBm = 78,// 19.5dBm
-    WIFI_POWER_19dBm = 76,// 19dBm
-    WIFI_POWER_18_5dBm = 74,// 18.5dBm
-    WIFI_POWER_17dBm = 68,// 17dBm
-    WIFI_POWER_15dBm = 60,// 15dBm
-    WIFI_POWER_13dBm = 52,// 13dBm
-    WIFI_POWER_11dBm = 44,// 11dBm
-    WIFI_POWER_8_5dBm = 34,// 8.5dBm
-    WIFI_POWER_7dBm = 28,// 7dBm
-    WIFI_POWER_5dBm = 20,// 5dBm
-    WIFI_POWER_2dBm = 8,// 2dBm
-    WIFI_POWER_MINUS_1dBm = -4// -1dBm
-} wifi_power_t;
+  wifi_event_id_t onEvent(WiFiEventCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+  wifi_event_id_t onEvent(WiFiEventFuncCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+  wifi_event_id_t onEvent(WiFiEventSysCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+  void removeEvent(WiFiEventCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+  void removeEvent(WiFiEventSysCb cbEvent, arduino_event_id_t event = ARDUINO_EVENT_MAX);
+  void removeEvent(wifi_event_id_t id);
+
+  static int getStatusBits();
+  static int waitStatusBits(int bits, uint32_t timeout_ms);
+
+  int32_t channel(void);
+  int setChannel(uint8_t primary, wifi_second_chan_t secondary = WIFI_SECOND_CHAN_NONE);
+
+  void persistent(bool persistent);
+  void enableLongRange(bool enable);
+
+  static bool mode(wifi_mode_t);
+  static wifi_mode_t getMode();
+
+  bool enableSTA(bool enable);
+  bool enableAP(bool enable);
+
+  bool setSleep(bool enabled);
+  bool setSleep(wifi_ps_type_t sleepType);
+  wifi_ps_type_t getSleep();
+
+  bool setTxPower(wifi_power_t power);
+  wifi_power_t getTxPower();
+
+  bool initiateFTM(uint8_t frm_count = 16, uint16_t burst_period = 2, uint8_t channel = 1, const uint8_t *mac = NULL);
+
+  static bool setDualAntennaConfig(uint8_t gpio_ant1, uint8_t gpio_ant2, wifi_rx_ant_t rx_mode, wifi_tx_ant_t tx_mode);
+
+  static const char *getHostname();
+  static bool setHostname(const char *hostname);
+  static bool hostname(const String &aHostname) {
+    return setHostname(aHostname.c_str());
+  }
+
+  static void useStaticBuffers(bool bufferMode);
+  static bool useStaticBuffers();
+
+  static int hostByName(const char *aHostname, IPAddress &aResult);
+
+  static IPAddress calculateNetworkID(IPAddress ip, IPAddress subnet);
+  static IPAddress calculateBroadcast(IPAddress ip, IPAddress subnet);
+  static uint8_t calculateSubnetCIDR(IPAddress subnetMask);
+
+  const char *disconnectReasonName(wifi_err_reason_t reason);
+  const char *eventName(arduino_event_id_t id);
+
+  static void _eventCallback(arduino_event_t *event);
+
+protected:
+  static bool _persistent;
+  static bool _long_range;
+  static wifi_mode_t _forceSleepLastMode;
+  static wifi_ps_type_t _sleepEnabled;
+  static bool _wifiUseStaticBuffers;
+
+  static int setStatusBits(int bits);
+  static int clearStatusBits(int bits);
 
-static const int AP_STARTED_BIT    = BIT0;
-static const int AP_HAS_IP6_BIT    = BIT1;
-static const int AP_HAS_CLIENT_BIT = BIT2;
-static const int STA_STARTED_BIT   = BIT3;
-static const int STA_CONNECTED_BIT = BIT4;
-static const int STA_HAS_IP_BIT    = BIT5;
-static const int STA_HAS_IP6_BIT   = BIT6;
-static const int ETH_STARTED_BIT   = BIT7;
-static const int ETH_CONNECTED_BIT = BIT8;
-static const int ETH_HAS_IP_BIT    = BIT9;
-static const int ETH_HAS_IP6_BIT   = BIT10;
-static const int WIFI_SCANNING_BIT = BIT11;
-static const int WIFI_SCAN_DONE_BIT= BIT12;
-static const int WIFI_DNS_IDLE_BIT = BIT13;
-static const int WIFI_DNS_DONE_BIT = BIT14;
-
-class WiFiGenericClass
-{
-  public:
-    WiFiGenericClass();
-
-    wifi_event_id_t onEvent(WiFiEventCb cbEvent, system_event_id_t event = SYSTEM_EVENT_MAX);
-    wifi_event_id_t onEvent(WiFiEventFuncCb cbEvent, system_event_id_t event = SYSTEM_EVENT_MAX);
-    wifi_event_id_t onEvent(WiFiEventSysCb cbEvent, system_event_id_t event = SYSTEM_EVENT_MAX);
-    wifi_event_id_t onEvent(WiFiProvEventCb cbEvent, system_event_id_t event = SYSTEM_EVENT_MAX);
-    void removeEvent(WiFiEventCb cbEvent, system_event_id_t event = SYSTEM_EVENT_MAX);
-    void removeEvent(WiFiEventSysCb cbEvent, system_event_id_t event = SYSTEM_EVENT_MAX);
-    void removeEvent(wifi_event_id_t id);
-
-    static int getStatusBits();
-    static int waitStatusBits(int bits, uint32_t timeout_ms);
-
-    int32_t channel(void);
-
-    void persistent(bool persistent);
-    void enableLongRange(bool enable);
-
-    static bool mode(wifi_mode_t);
-    static wifi_mode_t getMode();
-
-    bool enableSTA(bool enable);
-    bool enableAP(bool enable);
-
-    bool setSleep(bool enable);
-    bool setSleep(wifi_ps_type_t mode);
-    bool getSleep();
-
-    bool setTxPower(wifi_power_t power);
-    wifi_power_t getTxPower();
-
-    static esp_err_t _eventCallback(void *arg, system_event_t *event, wifi_prov_event_t *prov_event);
-
-  protected:
-    static bool _persistent;
-    static bool _long_range;
-    static wifi_mode_t _forceSleepLastMode;
-
-    static int setStatusBits(int bits);
-    static int clearStatusBits(int bits);
-
-  public:
-    static int hostByName(const char *aHostname, IPAddress &aResult);
-
-    static IPAddress calculateNetworkID(IPAddress ip, IPAddress subnet);
-    static IPAddress calculateBroadcast(IPAddress ip, IPAddress subnet);
-    static uint8_t calculateSubnetCIDR(IPAddress subnetMask);
-
-  protected:
-    friend class WiFiSTAClass;
-    friend class WiFiScanClass;
-    friend class WiFiAPClass;
+  friend class WiFiSTAClass;
+  friend class WiFiScanClass;
+  friend class WiFiAPClass;
+  friend class ETHClass;
 };
 
-#endif /* ESP32WIFIGENERIC_H_ */
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiMulti.cpp b/libraries/WiFi/src/WiFiMulti.cpp
index 876b3887684..c99bef5ac90 100644
--- a/libraries/WiFi/src/WiFiMulti.cpp
+++ b/libraries/WiFi/src/WiFiMulti.cpp
@@ -24,181 +24,330 @@
  */
 
 #include "WiFiMulti.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 #include <limits.h>
 #include <string.h>
 #include <esp32-hal.h>
 
-WiFiMulti::WiFiMulti()
-{
+WiFiMulti::WiFiMulti() {
+  ipv6_support = false;
 }
 
-WiFiMulti::~WiFiMulti()
-{
-    for(uint32_t i = 0; i < APlist.size(); i++) {
-        WifiAPlist_t entry = APlist[i];
-        if(entry.ssid) {
-            free(entry.ssid);
-        }
-        if(entry.passphrase) {
-            free(entry.passphrase);
-        }
+void WiFiMulti::APlistClean(void) {
+  for (auto entry : APlist) {
+    if (entry.ssid) {
+      free(entry.ssid);
     }
-    APlist.clear();
+    if (entry.passphrase) {
+      free(entry.passphrase);
+    }
+  }
+  APlist.clear();
+}
+
+WiFiMulti::~WiFiMulti() {
+  APlistClean();
 }
 
-bool WiFiMulti::addAP(const char* ssid, const char *passphrase)
-{
-    WifiAPlist_t newAP;
+bool WiFiMulti::addAP(const char *ssid, const char *passphrase) {
+  WifiAPlist_t newAP;
 
-    if(!ssid || *ssid == 0x00 || strlen(ssid) > 31) {
-        // fail SSID too long or missing!
-        log_e("[WIFI][APlistAdd] no ssid or ssid too long");
-        return false;
-    }
+  if (!ssid || *ssid == '\0' || strlen(ssid) > 31) {
+    // fail SSID too long or missing!
+    log_e("[WIFI][APlistAdd] no ssid or ssid too long");
+    return false;
+  }
 
-    if(passphrase && strlen(passphrase) > 63) {
-        // fail passphrase too long!
-        log_e("[WIFI][APlistAdd] passphrase too long");
-        return false;
-    }
+  if (passphrase && strlen(passphrase) > 63) {
+    // fail passphrase too long!
+    log_e("[WIFI][APlistAdd] passphrase too long");
+    return false;
+  }
+
+  newAP.ssid = strdup(ssid);
 
-    newAP.ssid = strdup(ssid);
+  if (!newAP.ssid) {
+    log_e("[WIFI][APlistAdd] fail newAP.ssid == 0");
+    return false;
+  }
 
-    if(!newAP.ssid) {
-        log_e("[WIFI][APlistAdd] fail newAP.ssid == 0");
-        return false;
+  if (passphrase && *passphrase != '\0') {
+    newAP.passphrase = strdup(passphrase);
+    if (!newAP.passphrase) {
+      log_e("[WIFI][APlistAdd] fail newAP.passphrase == 0");
+      free(newAP.ssid);
+      return false;
     }
+  } else {
+    newAP.passphrase = NULL;
+  }
+  newAP.hasFailed = false;
+  APlist.push_back(newAP);
+  log_i("[WIFI][APlistAdd] add SSID: %s", newAP.ssid);
+  return true;
+}
 
-    if(passphrase && *passphrase != 0x00) {
-        newAP.passphrase = strdup(passphrase);
-        if(!newAP.passphrase) {
-            log_e("[WIFI][APlistAdd] fail newAP.passphrase == 0");
-            free(newAP.ssid);
-            return false;
-        }
+uint8_t WiFiMulti::run(uint32_t connectTimeout, bool scanHidden) {
+  int8_t scanResult;
+  unsigned long startTime;
+  uint8_t status = WiFi.status();
+  if (status == WL_CONNECTED) {
+    if (!_bWFMInit && _connectionTestCBFunc != NULL) {
+      if (_connectionTestCBFunc() == true) {
+        _bWFMInit = true;
+        return status;
+      }
     } else {
-        newAP.passphrase = NULL;
+      if (!_bStrict) {
+        return status;
+      } else {
+        for (auto ap : APlist) {
+          if (WiFi.SSID() == ap.ssid) {
+            return status;
+          }
+        }
+      }
     }
+    WiFi.disconnect(false, false);
+    delay(10);
+    status = WiFi.status();
+  }
 
-    APlist.push_back(newAP);
-    log_i("[WIFI][APlistAdd] add SSID: %s", newAP.ssid);
-    return true;
-}
+  scanResult = WiFi.scanNetworks(false, scanHidden);
+  if (scanResult == WIFI_SCAN_RUNNING) {
+    // scan is running
+    return WL_NO_SSID_AVAIL;
+  } else if (scanResult >= 0) {
+    // scan done analyze
+    int32_t bestIndex = -1;
+    WifiAPlist_t bestNetwork{NULL, NULL, false};
+    int bestNetworkDb = INT_MIN;
+    int bestNetworkSec = WIFI_AUTH_MAX;
+    uint8_t bestBSSID[6];
+    int32_t bestChannel = 0;
+
+    log_i("[WIFI] scan done");
+
+    if (scanResult == 0) {
+      log_e("[WIFI] no networks found");
+    } else {
+      log_i("[WIFI] %d networks found", scanResult);
 
-uint8_t WiFiMulti::run(uint32_t connectTimeout)
-{
-    int8_t scanResult;
-    uint8_t status = WiFi.status();
-    if(status == WL_CONNECTED) {
-        for(uint32_t x = 0; x < APlist.size(); x++) {
-            if(WiFi.SSID()==APlist[x].ssid) {
-                return status;
+      int8_t failCount = 0;
+      int8_t foundCount = 0;
+      for (int8_t i = 0; i < scanResult; ++i) {
+
+        String ssid_scan;
+        int32_t rssi_scan;
+        uint8_t sec_scan;
+        uint8_t *BSSID_scan;
+        int32_t chan_scan;
+        bool hidden_scan;
+
+        WiFi.getNetworkInfo(i, ssid_scan, sec_scan, rssi_scan, BSSID_scan, chan_scan);
+        hidden_scan = (ssid_scan.length() == 0) && scanHidden;
+        // add any Open WiFi AP to the list, if allowed with setAllowOpenAP(true)
+        if (_bAllowOpenAP && sec_scan == WIFI_AUTH_OPEN) {
+          bool found = false;
+          for (auto check : APlist) {
+            if (ssid_scan == check.ssid) {
+              found = true;
+              break;
             }
+          }
+          // If we didn't find it, add this Open WiFi AP to the list
+          if (!found) {
+            log_i("[WIFI][APlistAdd] adding Open WiFi SSID: %s", ssid_scan.c_str());
+            addAP(ssid_scan.c_str());
+          }
         }
-        WiFi.disconnect(false,false);
-        delay(10);
-        status = WiFi.status();
-    }
 
-    scanResult = WiFi.scanNetworks();
-    if(scanResult == WIFI_SCAN_RUNNING) {
-        // scan is running
-        return WL_NO_SSID_AVAIL;
-    } else if(scanResult >= 0) {
-        // scan done analyze
-        WifiAPlist_t bestNetwork { NULL, NULL };
-        int bestNetworkDb = INT_MIN;
-        uint8_t bestBSSID[6];
-        int32_t bestChannel = 0;
-
-        log_i("[WIFI] scan done");
-
-        if(scanResult == 0) {
-            log_e("[WIFI] no networks found");
-        } else {
-            log_i("[WIFI] %d networks found", scanResult);
-            for(int8_t i = 0; i < scanResult; ++i) {
-
-                String ssid_scan;
-                int32_t rssi_scan;
-                uint8_t sec_scan;
-                uint8_t* BSSID_scan;
-                int32_t chan_scan;
-
-                WiFi.getNetworkInfo(i, ssid_scan, sec_scan, rssi_scan, BSSID_scan, chan_scan);
-
-                bool known = false;
-                for(uint32_t x = 0; x < APlist.size(); x++) {
-                    WifiAPlist_t entry = APlist[x];
-
-                    if(ssid_scan == entry.ssid) { // SSID match
-                        known = true;
-                        if(rssi_scan > bestNetworkDb) { // best network
-                            if(sec_scan == WIFI_AUTH_OPEN || entry.passphrase) { // check for passphrase if not open wlan
-                                bestNetworkDb = rssi_scan;
-                                bestChannel = chan_scan;
-                                memcpy((void*) &bestNetwork, (void*) &entry, sizeof(bestNetwork));
-                                memcpy((void*) &bestBSSID, (void*) BSSID_scan, sizeof(bestBSSID));
-                            }
-                        }
-                        break;
-                    }
+        if (hidden_scan) {
+          log_v("hidden ssid on channel %d found, trying to connect with known credentials...", chan_scan);
+        }
+
+        bool known = false;
+        for (uint32_t x = 0; x < APlist.size(); x++) {
+          WifiAPlist_t entry = APlist[x];
+
+          if (ssid_scan == entry.ssid || hidden_scan) {  // SSID match or hidden network found
+            if (!hidden_scan) {
+              log_v("known ssid: %s, has failed: %s", entry.ssid, entry.hasFailed ? "yes" : "no");
+              foundCount++;
+            }
+            if (!entry.hasFailed) {
+              if (hidden_scan) {
+                WiFi.begin(entry.ssid, entry.passphrase, chan_scan, BSSID_scan);
+
+                // If the ssid returned from the scan is empty, it is a hidden SSID
+                // it appears that the WiFi.begin() function is asynchronous and takes
+                // additional time to connect to a hidden SSID. Therefore a delay of 1000ms
+                // is added for hidden SSIDs before calling WiFi.status()
+                delay(1000);
+
+                status = WiFi.status();
+                startTime = millis();
+
+                while (status != WL_CONNECTED && (millis() - startTime) <= connectTimeout) {
+                  delay(10);
+                  status = WiFi.status();
                 }
 
-                if(known) {
-                    log_d(" --->   %d: [%d][%02X:%02X:%02X:%02X:%02X:%02X] %s (%d) %c", i, chan_scan, BSSID_scan[0], BSSID_scan[1], BSSID_scan[2], BSSID_scan[3], BSSID_scan[4], BSSID_scan[5], ssid_scan.c_str(), rssi_scan, (sec_scan == WIFI_AUTH_OPEN) ? ' ' : '*');
+                WiFi.disconnect();
+                delay(10);
+
+                if (status == WL_CONNECTED) {
+                  log_v("hidden ssid %s found", entry.ssid);
+                  ssid_scan = entry.ssid;
+                  foundCount++;
                 } else {
-                    log_d("       %d: [%d][%02X:%02X:%02X:%02X:%02X:%02X] %s (%d) %c", i, chan_scan, BSSID_scan[0], BSSID_scan[1], BSSID_scan[2], BSSID_scan[3], BSSID_scan[4], BSSID_scan[5], ssid_scan.c_str(), rssi_scan, (sec_scan == WIFI_AUTH_OPEN) ? ' ' : '*');
+                  continue;
                 }
+              }
+              known = true;
+              log_v("rssi_scan: %d, bestNetworkDb: %d", rssi_scan, bestNetworkDb);
+              if (rssi_scan > bestNetworkDb) {                                            // best network
+                if (_bAllowOpenAP || (sec_scan == WIFI_AUTH_OPEN || entry.passphrase)) {  // check for passphrase if not open wlan
+                  log_v("best network is now: %s", ssid_scan);
+                  bestIndex = x;
+                  bestNetworkSec = sec_scan;
+                  bestNetworkDb = rssi_scan;
+                  bestChannel = chan_scan;
+                  memcpy((void *)&bestNetwork, (void *)&entry, sizeof(bestNetwork));
+                  memcpy((void *)&bestBSSID, (void *)BSSID_scan, sizeof(bestBSSID));
+                }
+              }
+              break;
+            } else {
+              failCount++;
             }
+          }
         }
 
-        // clean up ram
-        WiFi.scanDelete();
+        if (known) {
+          log_d(
+            " --->   %d: [%d][%02X:%02X:%02X:%02X:%02X:%02X] %s (%d) (%c) (%s)", i, chan_scan, BSSID_scan[0], BSSID_scan[1], BSSID_scan[2], BSSID_scan[3],
+            BSSID_scan[4], BSSID_scan[5], ssid_scan.c_str(), rssi_scan, (sec_scan == WIFI_AUTH_OPEN) ? ' ' : '*', (hidden_scan) ? "hidden" : "visible"
+          );
+        } else {
+          log_d(
+            "        %d: [%d][%02X:%02X:%02X:%02X:%02X:%02X] %s (%d) (%c) (%s)", i, chan_scan, BSSID_scan[0], BSSID_scan[1], BSSID_scan[2], BSSID_scan[3],
+            BSSID_scan[4], BSSID_scan[5], ssid_scan.c_str(), rssi_scan, (sec_scan == WIFI_AUTH_OPEN) ? ' ' : '*', (hidden_scan) ? "hidden" : "visible"
+          );
+        }
+      }
+      log_v("foundCount = %d, failCount = %d", foundCount, failCount);
+      // if all the APs in the list have failed, reset the failure flags
+      if (foundCount == failCount) {
+        resetFails();  // keeps trying the APs in the list
+      }
+    }
+    // clean up ram
+    WiFi.scanDelete();
 
-        if(bestNetwork.ssid) {
-            log_i("[WIFI] Connecting BSSID: %02X:%02X:%02X:%02X:%02X:%02X SSID: %s Channel: %d (%d)", bestBSSID[0], bestBSSID[1], bestBSSID[2], bestBSSID[3], bestBSSID[4], bestBSSID[5], bestNetwork.ssid, bestChannel, bestNetworkDb);
+    if (bestIndex >= 0) {
+      log_i(
+        "[WIFI] Connecting BSSID: %02X:%02X:%02X:%02X:%02X:%02X SSID: %s Channel: %d (%d)", bestBSSID[0], bestBSSID[1], bestBSSID[2], bestBSSID[3],
+        bestBSSID[4], bestBSSID[5], bestNetwork.ssid, bestChannel, bestNetworkDb
+      );
 
-            WiFi.begin(bestNetwork.ssid, bestNetwork.passphrase, bestChannel, bestBSSID);
-            status = WiFi.status();
+#if CONFIG_LWIP_IPV6
+      if (ipv6_support == true) {
+        WiFi.enableIPv6();
+      }
+#endif
+      WiFi.disconnect();
+      delay(10);
+      WiFi.begin(bestNetwork.ssid, (_bAllowOpenAP && bestNetworkSec == WIFI_AUTH_OPEN) ? NULL : bestNetwork.passphrase, bestChannel, bestBSSID);
+      status = WiFi.status();
+      _bWFMInit = true;
 
-            auto startTime = millis();
-            // wait for connection, fail, or timeout
-            while(status != WL_CONNECTED && status != WL_NO_SSID_AVAIL && status != WL_CONNECT_FAILED && (millis() - startTime) <= connectTimeout) {
-                delay(10);
-                status = WiFi.status();
-            }
+      startTime = millis();
+      // wait for connection, fail, or timeout
+      while (status != WL_CONNECTED && (millis() - startTime) <= connectTimeout) {  // && status != WL_NO_SSID_AVAIL && status != WL_CONNECT_FAILED
+        delay(10);
+        status = WiFi.status();
+      }
+
+      switch (status) {
+        case WL_CONNECTED:
+          log_i("[WIFI] Connecting done.");
+          log_d("[WIFI] SSID: %s", WiFi.SSID().c_str());
+          log_d("[WIFI] IP: %s", WiFi.localIP().toString().c_str());
+          log_d("[WIFI] MAC: %s", WiFi.BSSIDstr().c_str());
+          log_d("[WIFI] Channel: %d", WiFi.channel());
 
-            switch(status) {
-            case WL_CONNECTED:
-                log_i("[WIFI] Connecting done.");
-                log_d("[WIFI] SSID: %s", WiFi.SSID().c_str());
-                log_d("[WIFI] IP: %s", WiFi.localIP().toString().c_str());
-                log_d("[WIFI] MAC: %s", WiFi.BSSIDstr().c_str());
-                log_d("[WIFI] Channel: %d", WiFi.channel());
-                break;
-            case WL_NO_SSID_AVAIL:
-                log_e("[WIFI] Connecting Failed AP not found.");
-                break;
-            case WL_CONNECT_FAILED:
-                log_e("[WIFI] Connecting Failed.");
-                break;
-            default:
-                log_e("[WIFI] Connecting Failed (%d).", status);
-                break;
+          if (_connectionTestCBFunc != NULL) {
+            // We connected to an AP but if it's a captive portal we're not going anywhere.  Test it.
+            if (_connectionTestCBFunc()) {
+              resetFails();
+            } else {
+              markAsFailed(bestIndex);
+              WiFi.disconnect();
+              delay(10);
+              status = WiFi.status();
             }
-        } else {
-            log_e("[WIFI] no matching wifi found!");
-        }
+          } else {
+            resetFails();
+          }
+          break;
+        case WL_NO_SSID_AVAIL:
+          log_e("[WIFI] Connecting Failed AP not found.");
+          markAsFailed(bestIndex);
+          break;
+        case WL_CONNECT_FAILED:
+          log_e("[WIFI] Connecting Failed.");
+          markAsFailed(bestIndex);
+          break;
+        default:
+          log_e("[WIFI] Connecting Failed (%d).", status);
+          markAsFailed(bestIndex);
+          break;
+      }
     } else {
-        // start scan
-        log_d("[WIFI] delete old wifi config...");
-        WiFi.disconnect();
-
-        log_d("[WIFI] start scan");
-        // scan wifi async mode
-        WiFi.scanNetworks(true);
+      log_e("[WIFI] no matching wifi found!");
     }
+  } else {
+    // start scan
+    log_d("[WIFI] delete old wifi config...");
+    WiFi.disconnect();
 
-    return status;
+    log_d("[WIFI] start scan");
+    // scan wifi async mode
+    WiFi.scanNetworks(true);
+  }
+
+  return status;
+}
+
+#if CONFIG_LWIP_IPV6
+void WiFiMulti::enableIPv6(bool state) {
+  ipv6_support = state;
+}
+#endif
+
+void WiFiMulti::markAsFailed(int32_t i) {
+  APlist[i].hasFailed = true;
+  log_d("[WIFI] Marked SSID %s as failed", APlist[i].ssid);
+}
+
+void WiFiMulti::resetFails() {
+  for (uint32_t i = 0; i < APlist.size(); i++) {
+    APlist[i].hasFailed = false;
+  }
+  log_d("[WIFI] Resetting failure flags");
 }
+
+void WiFiMulti::setStrictMode(bool bStrict) {
+  _bStrict = bStrict;
+}
+
+void WiFiMulti::setAllowOpenAP(bool bAllowOpenAP) {
+  _bAllowOpenAP = bAllowOpenAP;
+}
+
+void WiFiMulti::setConnectionTestCallbackFunc(ConnectionTestCB_t cbFunc) {
+  _connectionTestCBFunc = cbFunc;
+}
+
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiMulti.h b/libraries/WiFi/src/WiFiMulti.h
index 38ddb5d9f95..d818f77899f 100644
--- a/libraries/WiFi/src/WiFiMulti.h
+++ b/libraries/WiFi/src/WiFiMulti.h
@@ -23,29 +23,61 @@
  *
  */
 
-#ifndef WIFICLIENTMULTI_H_
-#define WIFICLIENTMULTI_H_
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
 #include "WiFi.h"
 #include <vector>
 
 typedef struct {
-    char * ssid;
-    char * passphrase;
+  char *ssid;
+  char *passphrase;
+  bool hasFailed;
 } WifiAPlist_t;
 
-class WiFiMulti
-{
+typedef std::function<bool(void)> ConnectionTestCB_t;
+
+class WiFiMulti {
 public:
-    WiFiMulti();
-    ~WiFiMulti();
+  WiFiMulti();
+  ~WiFiMulti();
+
+  bool addAP(const char *ssid, const char *passphrase = NULL);
+  uint8_t run(uint32_t connectTimeout = 5000, bool scanHidden = false);
+#if CONFIG_LWIP_IPV6
+  void enableIPv6(bool state);
+#endif
+
+  // Force (default: true) to only keep connected or to connect to an AP from the provided WiFiMulti list.
+  // When bStrict is false, it will keep the last/current connected AP even if not in the WiFiMulti List.
+  void setStrictMode(bool bStrict = true);
 
-    bool addAP(const char* ssid, const char *passphrase = NULL);
+  // allows (true) to connect to ANY open AP, even if not in the user list
+  // default false (do not connect to an open AP that has not been explicitaly added by the user to list)
+  void setAllowOpenAP(bool bAllowOpenAP = false);
 
-    uint8_t run(uint32_t connectTimeout=5000);
+  // clears the current list of Multi APs and frees the memory
+  void APlistClean(void);
+
+  // allow the user to define a callback function that will validate the connection to the Internet.
+  // if the callback returns true, the connection is considered valid and the AP will added to the validated AP list.
+  // set the callback to NULL to disable the feature and validate any SSID that is in the list.
+  void setConnectionTestCallbackFunc(ConnectionTestCB_t cbFunc);
 
 private:
-    std::vector<WifiAPlist_t> APlist;
+  std::vector<WifiAPlist_t> APlist;
+  bool ipv6_support;
+
+  bool _bStrict = true;
+  bool _bAllowOpenAP = false;
+  ConnectionTestCB_t _connectionTestCBFunc = NULL;
+  bool _bWFMInit = false;
+
+  void markAsFailed(int32_t i);
+  void resetFails();
 };
 
-#endif /* WIFICLIENTMULTI_H_ */
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiSTA.cpp b/libraries/WiFi/src/WiFiSTA.cpp
index a1da8a874a9..b956e35ba26 100644
--- a/libraries/WiFi/src/WiFiSTA.cpp
+++ b/libraries/WiFi/src/WiFiSTA.cpp
@@ -25,8 +25,8 @@
 #include "WiFi.h"
 #include "WiFiGeneric.h"
 #include "WiFiSTA.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
-extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include <stdio.h>
@@ -35,235 +35,126 @@ extern "C" {
 #include <string.h>
 #include <esp_err.h>
 #include <esp_wifi.h>
-#include <esp_event_loop.h>
+#include <esp_event.h>
 #include <esp32-hal.h>
 #include <lwip/ip_addr.h>
 #include "lwip/err.h"
 #include "lwip/dns.h"
 #include <esp_smartconfig.h>
-#include <tcpip_adapter.h>
-}
+#include <esp_netif.h>
+#include "esp_mac.h"
+
+#if __has_include("esp_eap_client.h")
+#include "esp_eap_client.h"
+#else
+#include "esp_wpa2.h"
+#endif
 
 // -----------------------------------------------------------------------------------------------------------------------
-// ---------------------------------------------------- Private functions ------------------------------------------------
+// ---------------------------------------------------- STA function -----------------------------------------------------
 // -----------------------------------------------------------------------------------------------------------------------
 
-static bool sta_config_equal(const wifi_config_t& lhs, const wifi_config_t& rhs);
-
-
 /**
- * compare two STA configurations
- * @param lhs station_config
- * @param rhs station_config
- * @return equal
+ * Return Connection status.
+ * @return one of the value defined in wl_status_t
+ *
  */
-static bool sta_config_equal(const wifi_config_t& lhs, const wifi_config_t& rhs)
-{
-    if(memcmp(&lhs, &rhs, sizeof(wifi_config_t)) != 0) {
-        return false;
-    }
-    return true;
+wl_status_t WiFiSTAClass::status() {
+  return STA.status();
 }
 
-// -----------------------------------------------------------------------------------------------------------------------
-// ---------------------------------------------------- STA function -----------------------------------------------------
-// -----------------------------------------------------------------------------------------------------------------------
-
-bool WiFiSTAClass::_autoReconnect = true;
-bool WiFiSTAClass::_useStaticIp = false;
+#if CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT
+wl_status_t WiFiSTAClass::begin(
+  const char *wpa2_ssid, wpa2_auth_method_t method, const char *wpa2_identity, const char *wpa2_username, const char *wpa2_password, const char *ca_pem,
+  const char *client_crt, const char *client_key, int ttls_phase2_type, int32_t channel, const uint8_t *bssid, bool connect
+) {
+  if (!STA.begin()) {
+    return WL_CONNECT_FAILED;
+  }
 
-static wl_status_t _sta_status = WL_NO_SHIELD;
-static EventGroupHandle_t _sta_status_group = NULL;
+  if (!STA.connect(wpa2_ssid, method, wpa2_identity, wpa2_username, wpa2_password, ca_pem, client_crt, client_key, ttls_phase2_type, channel, bssid, connect)) {
+    return WL_CONNECT_FAILED;
+  }
 
-void WiFiSTAClass::_setStatus(wl_status_t status)
-{
-    if(!_sta_status_group){
-        _sta_status_group = xEventGroupCreate();
-        if(!_sta_status_group){
-            log_e("STA Status Group Create Failed!");
-            _sta_status = status;
-            return;
-        }
-    }
-    xEventGroupClearBits(_sta_status_group, 0x00FFFFFF);
-    xEventGroupSetBits(_sta_status_group, status);
+  return STA.status();
 }
+#endif /* CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT */
 
-/**
- * Return Connection status.
- * @return one of the value defined in wl_status_t
- *
- */
-wl_status_t WiFiSTAClass::status()
-{
-    if(!_sta_status_group){
-        return _sta_status;
-    }
-    return (wl_status_t)xEventGroupClearBits(_sta_status_group, 0);
-}
-
-/**
- * Start Wifi connection
- * if passphrase is set the most secure supported mode will be automatically selected
- * @param ssid const char*          Pointer to the SSID string.
- * @param passphrase const char *   Optional. Passphrase. Valid characters in a passphrase must be between ASCII 32-126 (decimal).
- * @param bssid uint8_t[6]          Optional. BSSID / MAC of AP
- * @param channel                   Optional. Channel of AP
- * @param connect                   Optional. call connect
- * @return
- */
-wl_status_t WiFiSTAClass::begin(const char* ssid, const char *passphrase, int32_t channel, const uint8_t* bssid, bool connect)
-{
-
-    if(!WiFi.enableSTA(true)) {
-        log_e("STA enable failed!");
-        return WL_CONNECT_FAILED;
-    }
-
-    if(!ssid || *ssid == 0x00 || strlen(ssid) > 31) {
-        log_e("SSID too long or missing!");
-        return WL_CONNECT_FAILED;
-    }
-
-    if(passphrase && strlen(passphrase) > 64) {
-        log_e("passphrase too long!");
-        return WL_CONNECT_FAILED;
-    }
-
-    wifi_config_t conf;
-    memset(&conf, 0, sizeof(wifi_config_t));
-    strcpy(reinterpret_cast<char*>(conf.sta.ssid), ssid);
-
-    if(passphrase) {
-        if (strlen(passphrase) == 64){ // it's not a passphrase, is the PSK
-            memcpy(reinterpret_cast<char*>(conf.sta.password), passphrase, 64);
-        } else {
-            strcpy(reinterpret_cast<char*>(conf.sta.password), passphrase);
-        }
-    }
-
-    if(bssid) {
-        conf.sta.bssid_set = 1;
-        memcpy((void *) &conf.sta.bssid[0], (void *) bssid, 6);
-    }
-
-    if(channel > 0 && channel <= 13) {
-        conf.sta.channel = channel;
-    }
-
-    wifi_config_t current_conf;
-    esp_wifi_get_config(WIFI_IF_STA, &current_conf);
-    if(!sta_config_equal(current_conf, conf)) {
-        if(esp_wifi_disconnect()){
-            log_e("disconnect failed!");
-            return WL_CONNECT_FAILED;
-        }
-
-        esp_wifi_set_config(WIFI_IF_STA, &conf);
-    } else if(status() == WL_CONNECTED){
-        return WL_CONNECTED;
-    } else {
-        esp_wifi_set_config(WIFI_IF_STA, &conf);
-    }
-
-    if(!_useStaticIp) {
-        if(tcpip_adapter_dhcpc_start(TCPIP_ADAPTER_IF_STA) == ESP_ERR_TCPIP_ADAPTER_DHCPC_START_FAILED){
-            log_e("dhcp client start failed!");
-            return WL_CONNECT_FAILED;
-        }
-    } else {
-        tcpip_adapter_dhcpc_stop(TCPIP_ADAPTER_IF_STA);
-    }
-
-    if(connect && esp_wifi_connect()) {
-        log_e("connect failed!");
-        return WL_CONNECT_FAILED;
-    }
-
-    return status();
-}
-
-wl_status_t WiFiSTAClass::begin(char* ssid, char *passphrase, int32_t channel, const uint8_t* bssid, bool connect)
-{
-    return begin((const char*) ssid, (const char*) passphrase, channel, bssid, connect);
+wl_status_t WiFiSTAClass::begin(const char *ssid, const char *passphrase, int32_t channel, const uint8_t *bssid, bool connect) {
+  if (!STA.begin()) {
+    return WL_CONNECT_FAILED;
+  }
+
+  if (!STA.connect(ssid, passphrase, channel, bssid, connect)) {
+    return WL_CONNECT_FAILED;
+  }
+
+  return STA.status();
 }
 
 /**
  * Use to connect to SDK config.
  * @return wl_status_t
  */
-wl_status_t WiFiSTAClass::begin()
-{
-
-    if(!WiFi.enableSTA(true)) {
-        log_e("STA enable failed!");
-        return WL_CONNECT_FAILED;
-    }
+wl_status_t WiFiSTAClass::begin() {
+  if (!STA.begin(true)) {
+    return WL_CONNECT_FAILED;
+  }
 
-    wifi_config_t current_conf;
-    if(esp_wifi_get_config(WIFI_IF_STA, &current_conf) != ESP_OK || esp_wifi_set_config(WIFI_IF_STA, &current_conf) != ESP_OK) {
-        log_e("config failed");
-        return WL_CONNECT_FAILED;
-    }
-
-    if(!_useStaticIp) {
-        if(tcpip_adapter_dhcpc_start(TCPIP_ADAPTER_IF_STA) == ESP_ERR_TCPIP_ADAPTER_DHCPC_START_FAILED){
-            log_e("dhcp client start failed!");
-            return WL_CONNECT_FAILED;
-        }
-    } else {
-        tcpip_adapter_dhcpc_stop(TCPIP_ADAPTER_IF_STA);
-    }
-
-    if(status() != WL_CONNECTED && esp_wifi_connect()){
-        log_e("connect failed!");
-        return WL_CONNECT_FAILED;
-    }
-
-    return status();
+  return STA.status();
 }
 
 /**
  * will force a disconnect and then start reconnecting to AP
  * @return true when successful
  */
-bool WiFiSTAClass::reconnect()
-{
-    if(WiFi.getMode() & WIFI_MODE_STA) {
-        if(esp_wifi_disconnect() == ESP_OK) {
-            return esp_wifi_connect() == ESP_OK;
-        }
-    }
-    return false;
+bool WiFiSTAClass::reconnect() {
+  return STA.reconnect();
 }
 
 /**
- * Disconnect from the network
- * @param wifioff
- * @return  one value of wl_status_t enum
- */
-bool WiFiSTAClass::disconnect(bool wifioff, bool eraseap)
-{
-    wifi_config_t conf;
-
-    if(WiFi.getMode() & WIFI_MODE_STA){
-        if(eraseap){
-            memset(&conf, 0, sizeof(wifi_config_t));
-            if(esp_wifi_set_config(WIFI_IF_STA, &conf)){
-                log_e("clear config failed!");
-            }
-        }
-        if(esp_wifi_disconnect()){
-            log_e("disconnect failed!");
-            return false;
-        }
-        if(wifioff) {
-             return WiFi.enableSTA(false);
-        }
-        return true;
-    }
+ * Disconnect from the network.
+ * @param wifioff `true` to turn the Wi-Fi radio off.
+ * @param eraseap `true` to erase the AP configuration from the NVS memory.
+ * @return `true` when successful.
+ */
+bool WiFiSTAClass::disconnectAsync(bool wifioff, bool eraseap) {
+  return disconnect(wifioff, eraseap, 0);
+}
 
+/**
+ * Disconnect from the network.
+ * @param wifioff `true` to turn the Wi-Fi radio off.
+ * @param eraseap `true` to erase the AP configuration from the NVS memory.
+ * @param timeoutLength timeout to wait for status change
+ * @return `true` when successful.
+ */
+bool WiFiSTAClass::disconnect(bool wifioff, bool eraseap, unsigned long timeoutLength) {
+  if (!STA.disconnect(eraseap, timeoutLength)) {
     return false;
+  }
+  if (wifioff) {
+    return STA.end();
+  }
+  return true;
+}
+
+/**
+ * @brief  Reset WiFi settings in NVS to default values.
+ *
+ * This function will reset settings made using the following APIs:
+ * - esp_wifi_set_bandwidth,
+ * - esp_wifi_set_protocol,
+ * - esp_wifi_set_config related
+ * - esp_wifi_set_mode
+ *
+ * @return true if erase succeeded
+ * @note: Resets SSID, password, protocol, mode, etc.
+ * These settings are maintained by WiFi driver in IDF.
+ * WiFi driver must be initialized.
+ */
+bool WiFiSTAClass::eraseAP(void) {
+  return STA.erase();
 }
 
 /**
@@ -274,113 +165,104 @@ bool WiFiSTAClass::disconnect(bool wifioff, bool eraseap)
  * @param dns1       Static DNS server 1
  * @param dns2       Static DNS server 2
  */
-bool WiFiSTAClass::config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1, IPAddress dns2)
-{
-    esp_err_t err = ESP_OK;
-
-    if(!WiFi.enableSTA(true)) {
-        return false;
-    }
-
-    tcpip_adapter_ip_info_t info;
-
-    if(local_ip != (uint32_t)0x00000000){
-        info.ip.addr = static_cast<uint32_t>(local_ip);
-        info.gw.addr = static_cast<uint32_t>(gateway);
-        info.netmask.addr = static_cast<uint32_t>(subnet);
-    } else {
-        info.ip.addr = 0;
-        info.gw.addr = 0;
-        info.netmask.addr = 0;
-    }
-
-    err = tcpip_adapter_dhcpc_stop(TCPIP_ADAPTER_IF_STA);
-    if(err != ESP_OK && err != ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPPED){
-        log_e("DHCP could not be stopped! Error: %d", err);
-        return false;
-    }
-
-    err = tcpip_adapter_set_ip_info(TCPIP_ADAPTER_IF_STA, &info);
-    if(err != ERR_OK){
-        log_e("STA IP could not be configured! Error: %d", err);
-        return false;
-    }
-
-    if(info.ip.addr){
-        _useStaticIp = true;
-    } else {
-        err = tcpip_adapter_dhcpc_start(TCPIP_ADAPTER_IF_STA);
-        if(err == ESP_ERR_TCPIP_ADAPTER_DHCPC_START_FAILED){
-            log_e("dhcp client start failed!");
-            return false;
-        }
-        _useStaticIp = false;
-    }
-
-    ip_addr_t d;
-    d.type = IPADDR_TYPE_V4;
-
-    if(dns1 != (uint32_t)0x00000000) {
-        // Set DNS1-Server
-        d.u_addr.ip4.addr = static_cast<uint32_t>(dns1);
-        dns_setserver(0, &d);
-    }
-
-    if(dns2 != (uint32_t)0x00000000) {
-        // Set DNS2-Server
-        d.u_addr.ip4.addr = static_cast<uint32_t>(dns2);
-        dns_setserver(1, &d);
-    }
+bool WiFiSTAClass::config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1, IPAddress dns2) {
+  // handle Arduino ordering of parameters: ip, dns, gw, subnet
+  if (local_ip.type() == IPv4 && local_ip != INADDR_NONE && subnet[0] != 255) {
+    IPAddress tmp = dns1;
+    dns1 = gateway;
+    gateway = subnet;
+    subnet = (tmp != INADDR_NONE) ? tmp : IPAddress(255, 255, 255, 0);
+  }
 
-    return true;
+  return STA.begin() && STA.config(local_ip, gateway, subnet, dns1, dns2);
+}
+
+bool WiFiSTAClass::config(IPAddress local_ip, IPAddress dns) {
+
+  if (local_ip == INADDR_NONE) {
+    return config(INADDR_NONE, INADDR_NONE, INADDR_NONE);
+  }
+
+  if (local_ip.type() != IPv4) {
+    return false;
+  }
+
+  IPAddress gw(local_ip);
+  gw[3] = 1;
+  if (dns == INADDR_NONE) {
+    dns = gw;
+  }
+  return config(local_ip, gw, IPAddress(255, 255, 255, 0), dns);
+}
+
+/**
+ * Change DNS server for static IP configuration
+ * @param dns1       Static DNS server 1
+ * @param dns2       Static DNS server 2 (optional)
+ */
+bool WiFiSTAClass::setDNS(IPAddress dns1, IPAddress dns2) {
+  return STA.begin() && STA.dnsIP(0, dns1) && STA.dnsIP(1, dns2);
+}
+
+/**
+ * Sets the working bandwidth of the STA mode
+ * @param m wifi_bandwidth_t
+ */
+bool WiFiSTAClass::bandwidth(wifi_bandwidth_t bandwidth) {
+  return STA.bandwidth(bandwidth);
 }
 
 /**
  * is STA interface connected?
  * @return true if STA is connected to an AP
  */
-bool WiFiSTAClass::isConnected()
-{
-    return (status() == WL_CONNECTED);
+bool WiFiSTAClass::isConnected() {
+  return STA.connected() && STA.hasIP();
 }
 
-
 /**
- * Setting the ESP32 station to connect to the AP (which is recorded)
- * automatically or not when powered on. Enable auto-connect by default.
- * @param autoConnect bool
- * @return if saved
+ * Set the minimum security for AP to be considered connectable.
+ * Must be called before WiFi.begin().
+ * @param minSecurity wifi_auth_mode_t
  */
-bool WiFiSTAClass::setAutoConnect(bool autoConnect)
-{
-    /*bool ret;
-    ret = esp_wifi_set_auto_connect(autoConnect);
-    return ret;*/
-    return false;//now deprecated
+void WiFiSTAClass::setMinSecurity(wifi_auth_mode_t minSecurity) {
+  return STA.setMinSecurity(minSecurity);
 }
 
 /**
- * Checks if ESP32 station mode will connect to AP
- * automatically or not when it is powered on.
- * @return auto connect
+ * Set the way that AP is chosen.
+ * First SSID match[WIFI_FAST_SCAN] or Sorted[WIFI_ALL_CHANNEL_SCAN] (RSSI or Security)
+ * Must be called before WiFi.begin()
+ * @param scanMethod wifi_scan_method_t
  */
-bool WiFiSTAClass::getAutoConnect()
-{
-    /*bool autoConnect;
-    esp_wifi_get_auto_connect(&autoConnect);
-    return autoConnect;*/
-    return false;//now deprecated
+void WiFiSTAClass::setScanMethod(wifi_scan_method_t scanMethod) {
+  return STA.setScanMethod(scanMethod);
 }
 
-bool WiFiSTAClass::setAutoReconnect(bool autoReconnect)
-{
-    _autoReconnect = autoReconnect;
-    return true;
+/**
+ * Set the way that AP is sorted. (requires scanMethod WIFI_ALL_CHANNEL_SCAN)
+ * By SSID[WIFI_CONNECT_AP_BY_SIGNAL] or Security[WIFI_CONNECT_AP_BY_SECURITY]
+ * Must be called before WiFi.begin()
+ * @param sortMethod wifi_sort_method_t
+ */
+void WiFiSTAClass::setSortMethod(wifi_sort_method_t sortMethod) {
+  return STA.setSortMethod(sortMethod);
 }
 
-bool WiFiSTAClass::getAutoReconnect()
-{
-    return _autoReconnect;
+/**
+ * Function used to set the automatic reconnection if the connection is lost.
+ * @param autoReconnect `true` to enable this option.
+ * @return true
+ */
+bool WiFiSTAClass::setAutoReconnect(bool autoReconnect) {
+  return STA.setAutoReconnect(autoReconnect);
+}
+/**
+ * Function used to get the automatic reconnection if the connection is lost.
+ * @return The function will return `true` if this setting is enabled.
+ */
+bool WiFiSTAClass::getAutoReconnect() {
+  return STA.getAutoReconnect();
 }
 
 /**
@@ -388,94 +270,49 @@ bool WiFiSTAClass::getAutoReconnect()
  * returns the status reached or disconnect if STA is off
  * @return wl_status_t
  */
-uint8_t WiFiSTAClass::waitForConnectResult()
-{
-    //1 and 3 have STA enabled
-    if((WiFiGenericClass::getMode() & WIFI_MODE_STA) == 0) {
-        return WL_DISCONNECTED;
-    }
-    int i = 0;
-    while((!status() || status() >= WL_DISCONNECTED) && i++ < 100) {
-        delay(100);
-    }
-    return status();
+uint8_t WiFiSTAClass::waitForConnectResult(unsigned long timeoutLength) {
+  return STA.waitForConnectResult(timeoutLength);
 }
 
 /**
  * Get the station interface IP address.
  * @return IPAddress station IP
  */
-IPAddress WiFiSTAClass::localIP()
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPAddress();
-    }
-    tcpip_adapter_ip_info_t ip;
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ip);
-    return IPAddress(ip.ip.addr);
+IPAddress WiFiSTAClass::localIP() {
+  return STA.localIP();
 }
 
-
 /**
  * Get the station interface MAC address.
  * @param mac   pointer to uint8_t array with length WL_MAC_ADDR_LENGTH
  * @return      pointer to uint8_t *
  */
-uint8_t* WiFiSTAClass::macAddress(uint8_t* mac)
-{
-    if(WiFiGenericClass::getMode() != WIFI_MODE_NULL){
-        esp_wifi_get_mac(WIFI_IF_STA, mac);	
-    }
-    else{
-        esp_read_mac(mac, ESP_MAC_WIFI_STA);
-    }
-    return mac;
+uint8_t *WiFiSTAClass::macAddress(uint8_t *mac) {
+  return STA.macAddress(mac);
 }
 
 /**
  * Get the station interface MAC address.
  * @return String mac
  */
-String WiFiSTAClass::macAddress(void)
-{
-    uint8_t mac[6];
-    char macStr[18] = { 0 };
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        esp_read_mac(mac, ESP_MAC_WIFI_STA);
-    }
-    else{
-        esp_wifi_get_mac(WIFI_IF_STA, mac);
-    }
-    sprintf(macStr, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-    return String(macStr);
+String WiFiSTAClass::macAddress(void) {
+  return STA.macAddress();
 }
 
 /**
  * Get the interface subnet mask address.
  * @return IPAddress subnetMask
  */
-IPAddress WiFiSTAClass::subnetMask()
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPAddress();
-    }
-    tcpip_adapter_ip_info_t ip;
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ip);
-    return IPAddress(ip.netmask.addr);
+IPAddress WiFiSTAClass::subnetMask() {
+  return STA.subnetMask();
 }
 
 /**
  * Get the gateway ip address.
  * @return IPAddress gatewayIP
  */
-IPAddress WiFiSTAClass::gatewayIP()
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPAddress();
-    }
-    tcpip_adapter_ip_info_t ip;
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ip);
-    return IPAddress(ip.gw.addr);
+IPAddress WiFiSTAClass::gatewayIP() {
+  return STA.gatewayIP();
 }
 
 /**
@@ -483,278 +320,165 @@ IPAddress WiFiSTAClass::gatewayIP()
  * @param dns_no
  * @return IPAddress DNS Server IP
  */
-IPAddress WiFiSTAClass::dnsIP(uint8_t dns_no)
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPAddress();
-    }
-    const ip_addr_t* dns_ip = dns_getserver(dns_no);
-    return IPAddress(dns_ip->u_addr.ip4.addr);
+IPAddress WiFiSTAClass::dnsIP(uint8_t dns_no) {
+  return STA.dnsIP(dns_no);
 }
 
 /**
  * Get the broadcast ip address.
  * @return IPAddress broadcastIP
  */
-IPAddress WiFiSTAClass::broadcastIP()
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPAddress();
-    }
-    tcpip_adapter_ip_info_t ip;
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ip);
-    return WiFiGenericClass::calculateBroadcast(IPAddress(ip.gw.addr), IPAddress(ip.netmask.addr));
+IPAddress WiFiSTAClass::broadcastIP() {
+  return STA.broadcastIP();
 }
 
 /**
  * Get the network id.
  * @return IPAddress networkID
  */
-IPAddress WiFiSTAClass::networkID()
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPAddress();
-    }
-    tcpip_adapter_ip_info_t ip;
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ip);
-    return WiFiGenericClass::calculateNetworkID(IPAddress(ip.gw.addr), IPAddress(ip.netmask.addr));
+IPAddress WiFiSTAClass::networkID() {
+  return STA.networkID();
 }
 
 /**
  * Get the subnet CIDR.
  * @return uint8_t subnetCIDR
  */
-uint8_t WiFiSTAClass::subnetCIDR()
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return (uint8_t)0;
-    }
-    tcpip_adapter_ip_info_t ip;
-    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ip);
-    return WiFiGenericClass::calculateSubnetCIDR(IPAddress(ip.netmask.addr));
+uint8_t WiFiSTAClass::subnetCIDR() {
+  return STA.subnetCIDR();
 }
 
 /**
  * Return the current SSID associated with the network
  * @return SSID
  */
-String WiFiSTAClass::SSID() const
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return String();
-    }
-    wifi_ap_record_t info;
-    if(!esp_wifi_sta_get_ap_info(&info)) {
-        return String(reinterpret_cast<char*>(info.ssid));
-    }
-    return String();
+String WiFiSTAClass::SSID() const {
+  return STA.SSID();
 }
 
 /**
  * Return the current pre shared key associated with the network
  * @return  psk string
  */
-String WiFiSTAClass::psk() const
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return String();
-    }
-    wifi_config_t conf;
-    esp_wifi_get_config(WIFI_IF_STA, &conf);
-    return String(reinterpret_cast<char*>(conf.sta.password));
+String WiFiSTAClass::psk() const {
+  return STA.psk();
 }
 
 /**
  * Return the current bssid / mac associated with the network if configured
  * @return bssid uint8_t *
  */
-uint8_t* WiFiSTAClass::BSSID(void)
-{
-    static uint8_t bssid[6];
-    wifi_ap_record_t info;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return NULL;
-    }
-    if(!esp_wifi_sta_get_ap_info(&info)) {
-        memcpy(bssid, info.bssid, 6);
-        return reinterpret_cast<uint8_t*>(bssid);
-    }
-    return NULL;
+uint8_t *WiFiSTAClass::BSSID(uint8_t *buff) {
+  return STA.BSSID(buff);
 }
 
 /**
  * Return the current bssid / mac associated with the network if configured
  * @return String bssid mac
  */
-String WiFiSTAClass::BSSIDstr(void)
-{
-    uint8_t* bssid = BSSID();
-    if(!bssid){
-        return String();
-    }
-    char mac[18] = { 0 };
-    sprintf(mac, "%02X:%02X:%02X:%02X:%02X:%02X", bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
-    return String(mac);
+String WiFiSTAClass::BSSIDstr(void) {
+  return STA.BSSIDstr();
 }
 
 /**
  * Return the current network RSSI.
  * @return  RSSI value
  */
-int8_t WiFiSTAClass::RSSI(void)
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return 0;
-    }
-    wifi_ap_record_t info;
-    if(!esp_wifi_sta_get_ap_info(&info)) {
-        return info.rssi;
-    }
-    return 0;
-}
-
-/**
- * Get the station interface Host name.
- * @return char array hostname
- */
-const char * WiFiSTAClass::getHostname()
-{
-    const char * hostname = NULL;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return hostname;
-    }
-    if(tcpip_adapter_get_hostname(TCPIP_ADAPTER_IF_STA, &hostname)){
-        return NULL;
-    }
-    return hostname;
+int8_t WiFiSTAClass::RSSI(void) {
+  return STA.RSSI();
 }
 
+#if CONFIG_LWIP_IPV6
 /**
- * Set the station interface Host name.
- * @param  hostname  pointer to const string
- * @return true on   success
+ * Enable IPv6 on the station interface.
+ * Should be called before WiFi.begin()
+ *
+ * @return true on success
  */
-bool WiFiSTAClass::setHostname(const char * hostname)
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return false;
-    }
-    return tcpip_adapter_set_hostname(TCPIP_ADAPTER_IF_STA, hostname) == 0;
+bool WiFiSTAClass::enableIPv6(bool en) {
+  return STA.enableIPv6(en);
 }
 
 /**
- * Enable IPv6 on the station interface.
- * @return true on success
+ * Get the station interface link-local IPv6 address.
+ * @return IPAddress
  */
-bool WiFiSTAClass::enableIpV6()
-{
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return false;
-    }
-    return tcpip_adapter_create_ip6_linklocal(TCPIP_ADAPTER_IF_STA) == 0;
+IPAddress WiFiSTAClass::linkLocalIPv6() {
+  return STA.linkLocalIPv6();
 }
 
 /**
- * Get the station interface IPv6 address.
- * @return IPv6Address
+ * Get the station interface global IPv6 address.
+ * @return IPAddress
  */
-IPv6Address WiFiSTAClass::localIPv6()
-{
-    static ip6_addr_t addr;
-    if(WiFiGenericClass::getMode() == WIFI_MODE_NULL){
-        return IPv6Address();
-    }
-    if(tcpip_adapter_get_ip6_linklocal(TCPIP_ADAPTER_IF_STA, &addr)){
-        return IPv6Address();
-    }
-    return IPv6Address(addr.addr);
+IPAddress WiFiSTAClass::globalIPv6() {
+  return STA.globalIPv6();
 }
-
+#endif
 
 bool WiFiSTAClass::_smartConfigStarted = false;
 bool WiFiSTAClass::_smartConfigDone = false;
 
+/**
+ * @brief
+ *
+ * @param type Select type of SmartConfig. Default type is SC_TYPE_ESPTOUCH
+ * @param crypt_key When using type SC_TYPE_ESPTOUTCH_V2 crypt key needed, else ignored. Length should be 16 chars.
+ * @return true if configuration is successful.
+ * @return false if configuration fails.
+ */
+bool WiFiSTAClass::beginSmartConfig(smartconfig_type_t type, char *crypt_key) {
+  esp_err_t err;
+  if (_smartConfigStarted) {
+    return false;
+  }
 
-bool WiFiSTAClass::beginSmartConfig() {
-    if (_smartConfigStarted) {
-        return false;
-    }
+  if (!WiFi.mode(WIFI_STA)) {
+    return false;
+  }
+  esp_wifi_disconnect();
 
-    if (!WiFi.mode(WIFI_STA)) {
-        return false;
-    }
+  smartconfig_start_config_t conf = SMARTCONFIG_START_CONFIG_DEFAULT();
 
-    esp_wifi_disconnect();
+  if (type == SC_TYPE_ESPTOUCH_V2) {
+    conf.esp_touch_v2_enable_crypt = true;
+    conf.esp_touch_v2_key = crypt_key;
+  }
 
-    esp_err_t err;
-    err = esp_smartconfig_start(reinterpret_cast<sc_callback_t>(&WiFiSTAClass::_smartConfigCallback), 1);
-    if (err == ESP_OK) {
-        _smartConfigStarted = true;
-        _smartConfigDone = false;
-        return true;
-    }
+  err = esp_smartconfig_set_type(type);
+  if (err != ESP_OK) {
+    log_e("SmartConfig Set Type Failed!");
+    return false;
+  }
+  err = esp_smartconfig_start(&conf);
+  if (err != ESP_OK) {
+    log_e("SmartConfig Start Failed!");
     return false;
+  }
+  _smartConfigStarted = true;
+  _smartConfigDone = false;
+  return true;
 }
 
 bool WiFiSTAClass::stopSmartConfig() {
-    if (!_smartConfigStarted) {
-        return true;
-    }
+  if (!_smartConfigStarted) {
+    return true;
+  }
 
-    if (esp_smartconfig_stop() == ESP_OK) {
-        _smartConfigStarted = false;
-        return true;
-    }
+  if (esp_smartconfig_stop() == ESP_OK) {
+    _smartConfigStarted = false;
+    return true;
+  }
 
-    return false;
+  return false;
 }
 
 bool WiFiSTAClass::smartConfigDone() {
-    if (!_smartConfigStarted) {
-        return false;
-    }
-
-    return _smartConfigDone;
-}
-
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-const char * sc_status_strings[] = {
-    "WAIT",
-    "FIND_CHANNEL",
-    "GETTING_SSID_PSWD",
-    "LINK",
-    "LINK_OVER"
-};
-
-const char * sc_type_strings[] = {
-    "ESPTOUCH",
-    "AIRKISS",
-    "ESPTOUCH_AIRKISS"
-};
-#endif
+  if (!_smartConfigStarted) {
+    return false;
+  }
 
-void WiFiSTAClass::_smartConfigCallback(uint32_t st, void* result) {
-    smartconfig_status_t status = (smartconfig_status_t) st;
-    log_d("Status: %s", sc_status_strings[st % 5]);
-    if (status == SC_STATUS_GETTING_SSID_PSWD) {
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-        smartconfig_type_t * type = (smartconfig_type_t *)result;
-        log_d("Type: %s", sc_type_strings[*type % 3]);
-#endif
-    } else if (status == SC_STATUS_LINK) {
-        wifi_sta_config_t *sta_conf = reinterpret_cast<wifi_sta_config_t *>(result);
-        log_d("SSID: %s", (char *)(sta_conf->ssid));
-        sta_conf->bssid_set = 0;
-        esp_wifi_set_config(WIFI_IF_STA, (wifi_config_t *)sta_conf);
-        esp_wifi_connect();
-        _smartConfigDone = true;
-    } else if (status == SC_STATUS_LINK_OVER) {
-        if(result){
-#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_DEBUG
-            ip4_addr_t * ip = (ip4_addr_t *)result;
-            log_d("Sender IP: " IPSTR, IP2STR(ip));
-#endif
-        }
-        WiFi.stopSmartConfig();
-    }
+  return _smartConfigDone;
 }
+
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiSTA.h b/libraries/WiFi/src/WiFiSTA.h
index d9140101593..6063eae7968 100644
--- a/libraries/WiFi/src/WiFiSTA.h
+++ b/libraries/WiFi/src/WiFiSTA.h
@@ -20,87 +20,190 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#ifndef ESP32WIFISTA_H_
-#define ESP32WIFISTA_H_
+#pragma once
 
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
 #include "WiFiType.h"
 #include "WiFiGeneric.h"
+#ifdef ESP_IDF_VERSION_MAJOR
+#include "esp_event.h"
+#endif
 
+typedef enum {
+  WPA2_AUTH_TLS = 0,
+  WPA2_AUTH_PEAP = 1,
+  WPA2_AUTH_TTLS = 2
+} wpa2_auth_method_t;
 
-class WiFiSTAClass
-{
-    // ----------------------------------------------------------------------------------------------
-    // ---------------------------------------- STA function ----------------------------------------
-    // ----------------------------------------------------------------------------------------------
+// ----------------------------------------------------------------------------------------------
+// ------------------------------------ NEW STA Implementation ----------------------------------
+// ----------------------------------------------------------------------------------------------
 
+class STAClass : public NetworkInterface {
 public:
+  STAClass();
+  ~STAClass();
 
-    wl_status_t begin(const char* ssid, const char *passphrase = NULL, int32_t channel = 0, const uint8_t* bssid = NULL, bool connect = true);
-    wl_status_t begin(char* ssid, char *passphrase = NULL, int32_t channel = 0, const uint8_t* bssid = NULL, bool connect = true);
-    wl_status_t begin();
+  bool begin(bool tryConnect = false);
+  bool end();
 
-    bool config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1 = (uint32_t)0x00000000, IPAddress dns2 = (uint32_t)0x00000000);
+  bool bandwidth(wifi_bandwidth_t bandwidth);
 
-    bool reconnect();
-    bool disconnect(bool wifioff = false, bool eraseap = false);
+  bool connect();
+  bool connect(const char *ssid, const char *passphrase = NULL, int32_t channel = 0, const uint8_t *bssid = NULL, bool connect = true);
+#if CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT
+  bool connect(
+    const char *wpa2_ssid, wpa2_auth_method_t method, const char *wpa2_identity = NULL, const char *wpa2_username = NULL, const char *wpa2_password = NULL,
+    const char *ca_pem = NULL, const char *client_crt = NULL, const char *client_key = NULL, int ttls_phase2_type = -1, int32_t channel = 0,
+    const uint8_t *bssid = 0, bool connect = true
+  );
+#endif /* CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT */
+  bool disconnect(bool eraseap = false, unsigned long timeout = 0);
+  bool reconnect();
+  bool erase();
 
-    bool isConnected();
+  uint8_t waitForConnectResult(unsigned long timeoutLength = 60000);
 
-    bool setAutoConnect(bool autoConnect);
-    bool getAutoConnect();
+  bool setAutoReconnect(bool autoReconnect);
+  bool getAutoReconnect();
 
-    bool setAutoReconnect(bool autoReconnect);
-    bool getAutoReconnect();
+  // Next group functions must be called before WiFi.begin()
+  void setMinSecurity(wifi_auth_mode_t minSecurity);  // Default is WIFI_AUTH_WPA2_PSK
+  void setScanMethod(wifi_scan_method_t scanMethod);  // Default is WIFI_FAST_SCAN
+  void setSortMethod(wifi_sort_method_t sortMethod);  // Default is WIFI_CONNECT_AP_BY_SIGNAL
 
-    uint8_t waitForConnectResult();
+  wl_status_t status();
 
-    // STA network info
-    IPAddress localIP();
+  String SSID() const;
+  String psk() const;
+  uint8_t *BSSID(uint8_t *bssid = NULL);
+  String BSSIDstr();
+  int8_t RSSI();
 
-    uint8_t * macAddress(uint8_t* mac);
-    String macAddress();
+  const char *disconnectReasonName(wifi_err_reason_t reason);
 
-    IPAddress subnetMask();
-    IPAddress gatewayIP();
-    IPAddress dnsIP(uint8_t dns_no = 0);
+  // Private Use
+  void _setStatus(wl_status_t status);
+  void _onStaEvent(int32_t event_id, void *event_data);
 
-    IPAddress broadcastIP();
-    IPAddress networkID();
-    uint8_t subnetCIDR();
-    
-    bool enableIpV6();
-    IPv6Address localIPv6();
-
-    const char * getHostname();
-    bool setHostname(const char * hostname);
-
-    // STA WiFi info
-    static wl_status_t status();
-    String SSID() const;
-    String psk() const;
-
-    uint8_t * BSSID();
-    String BSSIDstr();
-
-    int8_t RSSI();
-
-    static void _setStatus(wl_status_t status);
 protected:
-    static bool _useStaticIp;
-    static bool _autoReconnect;
+  wifi_auth_mode_t _minSecurity;
+  wifi_scan_method_t _scanMethod;
+  wifi_sort_method_t _sortMethod;
+  bool _autoReconnect;
+  wl_status_t _status;
+  network_event_handle_t _wifi_sta_event_handle;
+
+  size_t printDriverInfo(Print &out) const;
+
+  friend class WiFiGenericClass;
+  bool onEnable();
+  bool onDisable();
+};
 
-public: 
-    bool beginSmartConfig();
-    bool stopSmartConfig();
-    bool smartConfigDone();
+// ----------------------------------------------------------------------------------------------
+// ------------------------------- OLD STA API (compatibility) ----------------------------------
+// ----------------------------------------------------------------------------------------------
 
+class WiFiSTAClass {
+public:
+  STAClass STA;
+
+#if CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT
+  wl_status_t begin(
+    const char *wpa2_ssid, wpa2_auth_method_t method, const char *wpa2_identity = NULL, const char *wpa2_username = NULL, const char *wpa2_password = NULL,
+    const char *ca_pem = NULL, const char *client_crt = NULL, const char *client_key = NULL, int ttls_phase2_type = -1, int32_t channel = 0,
+    const uint8_t *bssid = 0, bool connect = true
+  );
+  wl_status_t begin(
+    const String &wpa2_ssid, wpa2_auth_method_t method, const String &wpa2_identity = (const char *)NULL, const String &wpa2_username = (const char *)NULL,
+    const String &wpa2_password = (const char *)NULL, const String &ca_pem = (const char *)NULL, const String &client_crt = (const char *)NULL,
+    const String &client_key = (const char *)NULL, int ttls_phase2_type = -1, int32_t channel = 0, const uint8_t *bssid = 0, bool connect = true
+  ) {
+    return begin(
+      wpa2_ssid.c_str(), method, wpa2_identity.c_str(), wpa2_username.c_str(), wpa2_password.c_str(), ca_pem.c_str(), client_crt.c_str(), client_key.c_str(),
+      ttls_phase2_type, channel, bssid, connect
+    );
+  }
+#endif /* CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT */
+
+  wl_status_t begin(const char *ssid, const char *passphrase = NULL, int32_t channel = 0, const uint8_t *bssid = NULL, bool connect = true);
+  wl_status_t begin(const String &ssid, const String &passphrase = (const char *)NULL, int32_t channel = 0, const uint8_t *bssid = NULL, bool connect = true) {
+    return begin(ssid.c_str(), passphrase.c_str(), channel, bssid, connect);
+  }
+  wl_status_t begin();
+
+  // also accepts Arduino ordering of parameters: ip, dns, gw, mask
+  bool config(IPAddress local_ip, IPAddress gateway, IPAddress subnet, IPAddress dns1 = (uint32_t)0x00000000, IPAddress dns2 = (uint32_t)0x00000000);
+
+  // two and one parameter version. 2nd parameter is DNS like in Arduino
+  bool config(IPAddress local_ip, IPAddress dns = (uint32_t)0x00000000);
+
+  bool setDNS(IPAddress dns1, IPAddress dns2 = (uint32_t)0x00000000);  // sets DNS IP for all network interfaces
+
+  bool bandwidth(wifi_bandwidth_t bandwidth);
+
+  bool reconnect();
+  bool disconnectAsync(bool wifioff = false, bool eraseap = false);
+  bool disconnect(bool wifioff = false, bool eraseap = false, unsigned long timeoutLength = 100);
+  bool eraseAP(void);
+
+  bool isConnected();
+
+  bool setAutoReconnect(bool autoReconnect);
+  bool getAutoReconnect();
+
+  uint8_t waitForConnectResult(unsigned long timeoutLength = 60000);
+
+  // Next group functions must be called before WiFi.begin()
+  void setMinSecurity(wifi_auth_mode_t minSecurity);  // Default is WIFI_AUTH_WPA2_PSK
+  void setScanMethod(wifi_scan_method_t scanMethod);  // Default is WIFI_FAST_SCAN
+  void setSortMethod(wifi_sort_method_t sortMethod);  // Default is WIFI_CONNECT_AP_BY_SIGNAL
+
+  // STA WiFi info
+  wl_status_t status();
+  String SSID() const;
+  String psk() const;
+
+  uint8_t *BSSID(uint8_t *bssid = NULL);
+  String BSSIDstr();
+
+  int8_t RSSI();
+
+  IPAddress localIP();
+
+  uint8_t *macAddress(uint8_t *mac);
+  String macAddress();
+
+  IPAddress subnetMask();
+  IPAddress gatewayIP();
+  IPAddress dnsIP(uint8_t dns_no = 0);
+
+  IPAddress broadcastIP();
+  IPAddress networkID();
+  uint8_t subnetCIDR();
+
+#if CONFIG_LWIP_IPV6
+  bool enableIPv6(bool en = true);
+  IPAddress linkLocalIPv6();
+  IPAddress globalIPv6();
+#endif
+
+  // ----------------------------------------------------------------------------------------------
+  // ---------------------------------------- Smart Config ----------------------------------------
+  // ----------------------------------------------------------------------------------------------
 protected:
-    static bool _smartConfigStarted;
-    static bool _smartConfigDone;
-    static void _smartConfigCallback(uint32_t status, void* result);
+  static bool _smartConfigStarted;
 
-};
+public:
+  bool beginSmartConfig(smartconfig_type_t type = SC_TYPE_ESPTOUCH, char *crypt_key = NULL);
+  bool stopSmartConfig();
+  bool smartConfigDone();
 
+  static bool _smartConfigDone;
+};
 
-#endif /* ESP32WIFISTA_H_ */
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiScan.cpp b/libraries/WiFi/src/WiFiScan.cpp
index 7c6254fcc0d..086b875fcb2 100644
--- a/libraries/WiFi/src/WiFiScan.cpp
+++ b/libraries/WiFi/src/WiFiScan.cpp
@@ -22,10 +22,10 @@
 
  */
 
-
 #include "WiFi.h"
 #include "WiFiGeneric.h"
 #include "WiFiScan.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
 extern "C" {
 #include <stdint.h>
@@ -36,7 +36,7 @@ extern "C" {
 #include <string.h>
 #include <esp_err.h>
 #include <esp_wifi.h>
-#include <esp_event_loop.h>
+#include <esp_event.h>
 #include <esp32-hal.h>
 #include <lwip/ip_addr.h>
 #include "lwip/err.h"
@@ -44,9 +44,19 @@ extern "C" {
 
 bool WiFiScanClass::_scanAsync = false;
 uint32_t WiFiScanClass::_scanStarted = 0;
-uint32_t WiFiScanClass::_scanTimeout = 10000;
+uint32_t WiFiScanClass::_scanTimeout = 60000;
 uint16_t WiFiScanClass::_scanCount = 0;
-void* WiFiScanClass::_scanResult = 0;
+uint32_t WiFiScanClass::_scanActiveMinTime = 100;
+
+void *WiFiScanClass::_scanResult = nullptr;
+
+void WiFiScanClass::setScanTimeout(uint32_t ms) {
+  WiFiScanClass::_scanTimeout = ms;
+}
+
+void WiFiScanClass::setScanActiveMinTime(uint32_t ms) {
+  WiFiScanClass::_scanActiveMinTime = ms;
+}
 
 /**
  * Start scan WiFi networks available
@@ -54,70 +64,73 @@ void* WiFiScanClass::_scanResult = 0;
  * @param show_hidden   show hidden networks
  * @return Number of discovered networks
  */
-int16_t WiFiScanClass::scanNetworks(bool async, bool show_hidden, bool passive, uint32_t max_ms_per_chan, uint8_t channel)
-{
-    if(WiFiGenericClass::getStatusBits() & WIFI_SCANNING_BIT) {
-        return WIFI_SCAN_RUNNING;
-    }
-
-    WiFiScanClass::_scanTimeout = max_ms_per_chan * 20;
-    WiFiScanClass::_scanAsync = async;
+int16_t
+  WiFiScanClass::scanNetworks(bool async, bool show_hidden, bool passive, uint32_t max_ms_per_chan, uint8_t channel, const char *ssid, const uint8_t *bssid) {
+  if (WiFiGenericClass::getStatusBits() & WIFI_SCANNING_BIT) {
+    return WIFI_SCAN_RUNNING;
+  }
+
+  WiFiScanClass::_scanAsync = async;
+
+  WiFi.enableSTA(true);
+
+  scanDelete();
+
+  wifi_scan_config_t config;
+  memset(&config, 0, sizeof(wifi_scan_config_t));
+  config.ssid = (uint8_t *)ssid;
+  config.bssid = (uint8_t *)bssid;
+  config.channel = channel;
+  config.show_hidden = show_hidden;
+  if (passive) {
+    config.scan_type = WIFI_SCAN_TYPE_PASSIVE;
+    config.scan_time.passive = max_ms_per_chan;
+  } else {
+    config.scan_type = WIFI_SCAN_TYPE_ACTIVE;
+    config.scan_time.active.min = _scanActiveMinTime;
+    config.scan_time.active.max = max_ms_per_chan;
+  }
+  if (esp_wifi_scan_start(&config, false) == ESP_OK) {
+    _scanStarted = millis();
 
-    WiFi.enableSTA(true);
-
-    scanDelete();
+    WiFiGenericClass::clearStatusBits(WIFI_SCAN_DONE_BIT);
+    WiFiGenericClass::setStatusBits(WIFI_SCANNING_BIT);
 
-    wifi_scan_config_t config;
-    config.ssid = 0;
-    config.bssid = 0;
-    config.channel = channel;
-    config.show_hidden = show_hidden;
-    if(passive){
-        config.scan_type = WIFI_SCAN_TYPE_PASSIVE;
-        config.scan_time.passive = max_ms_per_chan;
-    } else {
-        config.scan_type = WIFI_SCAN_TYPE_ACTIVE;
-        config.scan_time.active.min = 100;
-        config.scan_time.active.max = max_ms_per_chan;
+    if (WiFiScanClass::_scanAsync) {
+      return WIFI_SCAN_RUNNING;
     }
-    if(esp_wifi_scan_start(&config, false) == ESP_OK) {
-        _scanStarted = millis();
-        if (!_scanStarted) { //Prevent 0 from millis overflow
-	    ++_scanStarted;
-	}
-
-        WiFiGenericClass::clearStatusBits(WIFI_SCAN_DONE_BIT);
-        WiFiGenericClass::setStatusBits(WIFI_SCANNING_BIT);
-
-        if(WiFiScanClass::_scanAsync) {
-            return WIFI_SCAN_RUNNING;
-        }
-        if(WiFiGenericClass::waitStatusBits(WIFI_SCAN_DONE_BIT, 10000)){
-            return (int16_t) WiFiScanClass::_scanCount;
-        }
+    if (WiFiGenericClass::waitStatusBits(WIFI_SCAN_DONE_BIT, _scanTimeout)) {
+      return (int16_t)WiFiScanClass::_scanCount;
     }
-    return WIFI_SCAN_FAILED;
+  }
+  return WIFI_SCAN_FAILED;
 }
 
-
 /**
  * private
  * scan callback
  * @param result  void *arg
  * @param status STATUS
  */
-void WiFiScanClass::_scanDone()
-{
-    esp_wifi_scan_get_ap_num(&(WiFiScanClass::_scanCount));
-    if(WiFiScanClass::_scanCount) {
-        WiFiScanClass::_scanResult = new wifi_ap_record_t[WiFiScanClass::_scanCount];
-        if(!WiFiScanClass::_scanResult || esp_wifi_scan_get_ap_records(&(WiFiScanClass::_scanCount), (wifi_ap_record_t*)_scanResult) != ESP_OK) {
-            WiFiScanClass::_scanCount = 0;
-        }
+void WiFiScanClass::_scanDone() {
+  esp_wifi_scan_get_ap_num(&(WiFiScanClass::_scanCount));
+  if (WiFiScanClass::_scanResult) {
+    free(WiFiScanClass::_scanResult);
+    WiFiScanClass::_scanResult = NULL;
+  }
+
+  if (WiFiScanClass::_scanCount) {
+    WiFiScanClass::_scanResult = calloc(WiFiScanClass::_scanCount, sizeof(wifi_ap_record_t));
+    if (!WiFiScanClass::_scanResult) {
+      WiFiScanClass::_scanCount = 0;
+    } else if (esp_wifi_scan_get_ap_records(&(WiFiScanClass::_scanCount), (wifi_ap_record_t *)_scanResult) != ESP_OK) {
+      free(WiFiScanClass::_scanResult);
+      WiFiScanClass::_scanResult = NULL;
+      WiFiScanClass::_scanCount = 0;
     }
-    WiFiScanClass::_scanStarted=0; //Reset after a scan is completed for normal behavior
-    WiFiGenericClass::setStatusBits(WIFI_SCAN_DONE_BIT);
-    WiFiGenericClass::clearStatusBits(WIFI_SCANNING_BIT);
+  }
+  WiFiGenericClass::setStatusBits(WIFI_SCAN_DONE_BIT);
+  WiFiGenericClass::clearStatusBits(WIFI_SCANNING_BIT);
 }
 
 /**
@@ -125,12 +138,11 @@ void WiFiScanClass::_scanDone()
  * @param i specify from which network item want to get the information
  * @return bss_info *
  */
-void * WiFiScanClass::_getScanInfoByIndex(int i)
-{
-    if(!WiFiScanClass::_scanResult || (size_t) i >= WiFiScanClass::_scanCount) {
-        return 0;
-    }
-    return reinterpret_cast<wifi_ap_record_t*>(WiFiScanClass::_scanResult) + i;
+void *WiFiScanClass::_getScanInfoByIndex(int i) {
+  if (!WiFiScanClass::_scanResult || (size_t)i >= WiFiScanClass::_scanCount) {
+    return 0;
+  }
+  return reinterpret_cast<wifi_ap_record_t *>(WiFiScanClass::_scanResult) + i;
 }
 
 /**
@@ -139,38 +151,36 @@ void * WiFiScanClass::_getScanInfoByIndex(int i)
  *          -1 if scan not fin
  *          -2 if scan not triggered
  */
-int16_t WiFiScanClass::scanComplete()
-{
-    if (WiFiScanClass::_scanStarted && (millis()-WiFiScanClass::_scanStarted) > WiFiScanClass::_scanTimeout) { //Check is scan was started and if the delay expired, return WIFI_SCAN_FAILED in this case 
-    	WiFiGenericClass::clearStatusBits(WIFI_SCANNING_BIT);
-	return WIFI_SCAN_FAILED;
-    }
-
-    if(WiFiGenericClass::getStatusBits() & WIFI_SCAN_DONE_BIT) {
-        return WiFiScanClass::_scanCount;
+int16_t WiFiScanClass::scanComplete() {
+  if (WiFiGenericClass::getStatusBits() & WIFI_SCAN_DONE_BIT) {
+    return WiFiScanClass::_scanCount;
+  }
+
+  if (WiFiGenericClass::getStatusBits() & WIFI_SCANNING_BIT) {
+    // Check if the delay expired, return WIFI_SCAN_FAILED in this case
+    if ((millis() - WiFiScanClass::_scanStarted) > WiFiScanClass::_scanTimeout) {
+      WiFiGenericClass::clearStatusBits(WIFI_SCANNING_BIT);
+      return WIFI_SCAN_FAILED;
     }
+    return WIFI_SCAN_RUNNING;
+  }
 
-    if(WiFiGenericClass::getStatusBits() & WIFI_SCANNING_BIT) {
-        return WIFI_SCAN_RUNNING;
-    }
-
-    return WIFI_SCAN_FAILED;
+  return WIFI_SCAN_FAILED;
 }
 
 /**
  * delete last scan result from RAM
  */
-void WiFiScanClass::scanDelete()
-{
-    WiFiGenericClass::clearStatusBits(WIFI_SCAN_DONE_BIT);
-    if(WiFiScanClass::_scanResult) {
-        delete[] reinterpret_cast<wifi_ap_record_t*>(WiFiScanClass::_scanResult);
-        WiFiScanClass::_scanResult = 0;
-        WiFiScanClass::_scanCount = 0;
-    }
+void WiFiScanClass::scanDelete() {
+  WiFiGenericClass::clearStatusBits(WIFI_SCAN_DONE_BIT);
+  WiFiGenericClass::clearStatusBits(WIFI_SCANNING_BIT);
+  if (WiFiScanClass::_scanResult) {
+    free(WiFiScanClass::_scanResult);
+    WiFiScanClass::_scanResult = NULL;
+  }
+  WiFiScanClass::_scanCount = 0;
 }
 
-
 /**
  * loads all infos from a scanned wifi in to the ptr parameters
  * @param networkItem uint8_t
@@ -181,48 +191,43 @@ void WiFiScanClass::scanDelete()
  * @param channel int32_t *
  * @return (true if ok)
  */
-bool WiFiScanClass::getNetworkInfo(uint8_t i, String &ssid, uint8_t &encType, int32_t &rssi, uint8_t* &bssid, int32_t &channel)
-{
-    wifi_ap_record_t* it = reinterpret_cast<wifi_ap_record_t*>(_getScanInfoByIndex(i));
-    if(!it) {
-        return false;
-    }
-    ssid = (const char*) it->ssid;
-    encType = it->authmode;
-    rssi = it->rssi;
-    bssid = it->bssid;
-    channel = it->primary;
-    return true;
+bool WiFiScanClass::getNetworkInfo(uint8_t i, String &ssid, uint8_t &encType, int32_t &rssi, uint8_t *&bssid, int32_t &channel) {
+  wifi_ap_record_t *it = reinterpret_cast<wifi_ap_record_t *>(_getScanInfoByIndex(i));
+  if (!it) {
+    return false;
+  }
+  ssid = (const char *)it->ssid;
+  encType = it->authmode;
+  rssi = it->rssi;
+  bssid = it->bssid;
+  channel = it->primary;
+  return true;
 }
 
-
 /**
  * Return the SSID discovered during the network scan.
  * @param i     specify from which network item want to get the information
  * @return       ssid string of the specified item on the networks scanned list
  */
-String WiFiScanClass::SSID(uint8_t i)
-{
-    wifi_ap_record_t* it = reinterpret_cast<wifi_ap_record_t*>(_getScanInfoByIndex(i));
-    if(!it) {
-        return String();
-    }
-    return String(reinterpret_cast<const char*>(it->ssid));
+String WiFiScanClass::SSID(uint8_t i) {
+  wifi_ap_record_t *it = reinterpret_cast<wifi_ap_record_t *>(_getScanInfoByIndex(i));
+  if (!it) {
+    return String();
+  }
+  return String(reinterpret_cast<const char *>(it->ssid));
 }
 
-
 /**
  * Return the encryption type of the networks discovered during the scanNetworks
  * @param i specify from which network item want to get the information
  * @return  encryption type (enum wl_enc_type) of the specified item on the networks scanned list
  */
-wifi_auth_mode_t WiFiScanClass::encryptionType(uint8_t i)
-{
-    wifi_ap_record_t* it = reinterpret_cast<wifi_ap_record_t*>(_getScanInfoByIndex(i));
-    if(!it) {
-        return WIFI_AUTH_OPEN;
-    }
-    return it->authmode;
+wifi_auth_mode_t WiFiScanClass::encryptionType(uint8_t i) {
+  wifi_ap_record_t *it = reinterpret_cast<wifi_ap_record_t *>(_getScanInfoByIndex(i));
+  if (!it) {
+    return WIFI_AUTH_OPEN;
+  }
+  return it->authmode;
 }
 
 /**
@@ -230,28 +235,34 @@ wifi_auth_mode_t WiFiScanClass::encryptionType(uint8_t i)
  * @param i specify from which network item want to get the information
  * @return  signed value of RSSI of the specified item on the networks scanned list
  */
-int32_t WiFiScanClass::RSSI(uint8_t i)
-{
-    wifi_ap_record_t* it = reinterpret_cast<wifi_ap_record_t*>(_getScanInfoByIndex(i));
-    if(!it) {
-        return 0;
-    }
-    return it->rssi;
+int32_t WiFiScanClass::RSSI(uint8_t i) {
+  wifi_ap_record_t *it = reinterpret_cast<wifi_ap_record_t *>(_getScanInfoByIndex(i));
+  if (!it) {
+    return 0;
+  }
+  return it->rssi;
 }
 
-
 /**
  * return MAC / BSSID of scanned wifi
  * @param i specify from which network item want to get the information
+ * @param buff optional buffer for the result uint8_t array with length 6
  * @return uint8_t * MAC / BSSID of scanned wifi
  */
-uint8_t * WiFiScanClass::BSSID(uint8_t i)
-{
-    wifi_ap_record_t* it = reinterpret_cast<wifi_ap_record_t*>(_getScanInfoByIndex(i));
-    if(!it) {
-        return 0;
+uint8_t *WiFiScanClass::BSSID(uint8_t i, uint8_t *buff) {
+  wifi_ap_record_t *it = reinterpret_cast<wifi_ap_record_t *>(_getScanInfoByIndex(i));
+  if (buff != NULL) {
+    if (!it) {
+      memset(buff, 0, 6);
+    } else {
+      memcpy(buff, it->bssid, 6);
     }
-    return it->bssid;
+    return buff;
+  }
+  if (!it) {
+    return 0;
+  }
+  return it->bssid;
 }
 
 /**
@@ -259,23 +270,22 @@ uint8_t * WiFiScanClass::BSSID(uint8_t i)
  * @param i specify from which network item want to get the information
  * @return String MAC / BSSID of scanned wifi
  */
-String WiFiScanClass::BSSIDstr(uint8_t i)
-{
-    char mac[18] = { 0 };
-    wifi_ap_record_t* it = reinterpret_cast<wifi_ap_record_t*>(_getScanInfoByIndex(i));
-    if(!it) {
-        return String();
-    }
-    sprintf(mac, "%02X:%02X:%02X:%02X:%02X:%02X", it->bssid[0], it->bssid[1], it->bssid[2], it->bssid[3], it->bssid[4], it->bssid[5]);
-    return String(mac);
+String WiFiScanClass::BSSIDstr(uint8_t i) {
+  char mac[18] = {0};
+  wifi_ap_record_t *it = reinterpret_cast<wifi_ap_record_t *>(_getScanInfoByIndex(i));
+  if (!it) {
+    return String();
+  }
+  sprintf(mac, "%02X:%02X:%02X:%02X:%02X:%02X", it->bssid[0], it->bssid[1], it->bssid[2], it->bssid[3], it->bssid[4], it->bssid[5]);
+  return String(mac);
 }
 
-int32_t WiFiScanClass::channel(uint8_t i)
-{
-    wifi_ap_record_t* it = reinterpret_cast<wifi_ap_record_t*>(_getScanInfoByIndex(i));
-    if(!it) {
-        return 0;
-    }
-    return it->primary;
+int32_t WiFiScanClass::channel(uint8_t i) {
+  wifi_ap_record_t *it = reinterpret_cast<wifi_ap_record_t *>(_getScanInfoByIndex(i));
+  if (!it) {
+    return 0;
+  }
+  return it->primary;
 }
 
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiScan.h b/libraries/WiFi/src/WiFiScan.h
index 1929e46627b..7afd26bb76a 100644
--- a/libraries/WiFi/src/WiFiScan.h
+++ b/libraries/WiFi/src/WiFiScan.h
@@ -20,47 +20,55 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
-#ifndef ESP32WIFISCAN_H_
-#define ESP32WIFISCAN_H_
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
 #include "WiFiType.h"
 #include "WiFiGeneric.h"
 
-class WiFiScanClass
-{
+class WiFiScanClass {
 
 public:
+  void setScanTimeout(uint32_t ms);
+  void setScanActiveMinTime(uint32_t ms);
+
+  int16_t scanNetworks(
+    bool async = false, bool show_hidden = false, bool passive = false, uint32_t max_ms_per_chan = 300, uint8_t channel = 0, const char *ssid = nullptr,
+    const uint8_t *bssid = nullptr
+  );
 
-    int16_t scanNetworks(bool async = false, bool show_hidden = false, bool passive = false, uint32_t max_ms_per_chan = 300, uint8_t channel = 0);
+  int16_t scanComplete();
+  void scanDelete();
 
-    int16_t scanComplete();
-    void scanDelete();
+  // scan result
+  bool getNetworkInfo(uint8_t networkItem, String &ssid, uint8_t &encryptionType, int32_t &RSSI, uint8_t *&BSSID, int32_t &channel);
 
-    // scan result
-    bool getNetworkInfo(uint8_t networkItem, String &ssid, uint8_t &encryptionType, int32_t &RSSI, uint8_t* &BSSID, int32_t &channel);
+  String SSID(uint8_t networkItem);
+  wifi_auth_mode_t encryptionType(uint8_t networkItem);
+  int32_t RSSI(uint8_t networkItem);
+  uint8_t *BSSID(uint8_t networkItem, uint8_t *bssid = NULL);
+  String BSSIDstr(uint8_t networkItem);
+  int32_t channel(uint8_t networkItem);
+  static void *getScanInfoByIndex(int i) {
+    return _getScanInfoByIndex(i);
+  };
 
-    String SSID(uint8_t networkItem);
-    wifi_auth_mode_t encryptionType(uint8_t networkItem);
-    int32_t RSSI(uint8_t networkItem);
-    uint8_t * BSSID(uint8_t networkItem);
-    String BSSIDstr(uint8_t networkItem);
-    int32_t channel(uint8_t networkItem);
-    static void * getScanInfoByIndex(int i) { return _getScanInfoByIndex(i); }; 
+  static void _scanDone();
 
-    static void _scanDone();
 protected:
+  static bool _scanAsync;
 
-    static bool _scanAsync;
-    
-    static uint32_t _scanStarted;
-    static uint32_t _scanTimeout;
-    static uint16_t _scanCount;
-    
-    static void* _scanResult;
+  static uint32_t _scanStarted;
+  static uint32_t _scanTimeout;
+  static uint16_t _scanCount;
+  static uint32_t _scanActiveMinTime;
 
-    static void * _getScanInfoByIndex(int i);
+  static void *_scanResult;
 
+  static void *_getScanInfoByIndex(int i);
 };
 
-
-#endif /* ESP32WIFISCAN_H_ */
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiServer.cpp b/libraries/WiFi/src/WiFiServer.cpp
deleted file mode 100644
index d6a5ae822ca..00000000000
--- a/libraries/WiFi/src/WiFiServer.cpp
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
-  Server.cpp - Server class for Raspberry Pi
-  Copyright (c) 2016 Hristo Gochkov  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-#include "WiFiServer.h"
-#include <lwip/sockets.h>
-#include <lwip/netdb.h>
-
-#undef write
-#undef close
-
-int WiFiServer::setTimeout(uint32_t seconds){
-  struct timeval tv;
-  tv.tv_sec = seconds;
-  tv.tv_usec = 0;
-  if(setsockopt(sockfd, SOL_SOCKET, SO_RCVTIMEO, (char *)&tv, sizeof(struct timeval)) < 0)
-    return -1;
-  return setsockopt(sockfd, SOL_SOCKET, SO_SNDTIMEO, (char *)&tv, sizeof(struct timeval));
-}
-
-size_t WiFiServer::write(const uint8_t *data, size_t len){
-  return 0;
-}
-
-void WiFiServer::stopAll(){}
-
-WiFiClient WiFiServer::available(){
-  if(!_listening)
-    return WiFiClient();
-  int client_sock;
-  if (_accepted_sockfd >= 0) {
-    client_sock = _accepted_sockfd;
-    _accepted_sockfd = -1;
-  }
-  else {
-  struct sockaddr_in _client;
-  int cs = sizeof(struct sockaddr_in);
-    client_sock = lwip_accept_r(sockfd, (struct sockaddr *)&_client, (socklen_t*)&cs);
-  }
-  if(client_sock >= 0){
-    int val = 1;
-    if(setsockopt(client_sock, SOL_SOCKET, SO_KEEPALIVE, (char*)&val, sizeof(int)) == ESP_OK) {
-      val = _noDelay;
-      if(setsockopt(client_sock, IPPROTO_TCP, TCP_NODELAY, (char*)&val, sizeof(int)) == ESP_OK)
-        return WiFiClient(client_sock);
-    }
-  }
-  return WiFiClient();
-}
-
-void WiFiServer::begin(uint16_t port){
-    begin(port, 1);
-}
-
-void WiFiServer::begin(uint16_t port, int enable){
-  if(_listening)
-    return;
-  if(port){
-      _port = port;
-  }
-  struct sockaddr_in server;
-  sockfd = socket(AF_INET , SOCK_STREAM, 0);
-  if (sockfd < 0)
-    return;
-  setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &enable, sizeof(int));
-  server.sin_family = AF_INET;
-  server.sin_addr.s_addr = INADDR_ANY;
-  server.sin_port = htons(_port);
-  if(bind(sockfd, (struct sockaddr *)&server, sizeof(server)) < 0)
-    return;
-  if(listen(sockfd , _max_clients) < 0)
-    return;
-  fcntl(sockfd, F_SETFL, O_NONBLOCK);
-  _listening = true;
-  _noDelay = false;
-  _accepted_sockfd = -1;
-}
-
-void WiFiServer::setNoDelay(bool nodelay) {
-    _noDelay = nodelay;
-}
-
-bool WiFiServer::getNoDelay() {
-    return _noDelay;
-}
-
-bool WiFiServer::hasClient() {
-    if (_accepted_sockfd >= 0) {
-      return true;
-    }
-    struct sockaddr_in _client;
-    int cs = sizeof(struct sockaddr_in);
-    _accepted_sockfd = lwip_accept_r(sockfd, (struct sockaddr *)&_client, (socklen_t*)&cs);
-    if (_accepted_sockfd >= 0) {
-      return true;
-    }
-    return false;
-}
-
-void WiFiServer::end(){
-  lwip_close_r(sockfd);
-  sockfd = -1;
-  _listening = false;
-}
-
-void WiFiServer::close(){
-  end();
-}
-
-void WiFiServer::stop(){
-  end();
-}
-
diff --git a/libraries/WiFi/src/WiFiServer.h b/libraries/WiFi/src/WiFiServer.h
index aeb831db1ba..850bd98d9c8 100644
--- a/libraries/WiFi/src/WiFiServer.h
+++ b/libraries/WiFi/src/WiFiServer.h
@@ -1,61 +1,3 @@
-/*
-  Server.h - Server class for Raspberry Pi
-  Copyright (c) 2016 Hristo Gochkov  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-#ifndef _WIFISERVER_H_
-#define _WIFISERVER_H_
-
-#include "Arduino.h"
-#include "Server.h"
-#include "WiFiClient.h"
-
-class WiFiServer : public Server {
-  private:
-    int sockfd;
-    int _accepted_sockfd = -1;
-    uint16_t _port;
-    uint8_t _max_clients;
-    bool _listening;
-    bool _noDelay = false;
-
-  public:
-    void listenOnLocalhost(){}
-
-    WiFiServer(uint16_t port=80, uint8_t max_clients=4):sockfd(-1),_accepted_sockfd(-1),_port(port),_max_clients(max_clients),_listening(false),_noDelay(false){}
-    ~WiFiServer(){ end();}
-    WiFiClient available();
-    WiFiClient accept(){return available();}
-    void begin(uint16_t port=0);
-    void begin(uint16_t port, int reuse_enable);
-    void setNoDelay(bool nodelay);
-    bool getNoDelay();
-    bool hasClient();
-    size_t write(const uint8_t *data, size_t len);
-    size_t write(uint8_t data){
-      return write(&data, 1);
-    }
-    using Print::write;
-
-    void end();
-    void close();
-    void stop();
-    operator bool(){return _listening;}
-    int setTimeout(uint32_t seconds);
-    void stopAll();
-};
-
-#endif /* _WIFISERVER_H_ */
+#pragma once
+#include "NetworkServer.h"
+typedef NetworkServer WiFiServer;
diff --git a/libraries/WiFi/src/WiFiType.h b/libraries/WiFi/src/WiFiType.h
index cce29eea4a2..29af9ce2252 100644
--- a/libraries/WiFi/src/WiFiType.h
+++ b/libraries/WiFi/src/WiFiType.h
@@ -19,33 +19,37 @@
  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#pragma once
 
-#ifndef ESP32WIFITYPE_H_
-#define ESP32WIFITYPE_H_
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_WIFI_SUPPORTED || CONFIG_ESP_WIFI_REMOTE_ENABLED
 
-#define WIFI_SCAN_RUNNING   (-1)
-#define WIFI_SCAN_FAILED    (-2)
+#include "esp_wifi_types.h"
 
-#define WiFiMode_t   wifi_mode_t
-#define WIFI_OFF     WIFI_MODE_NULL
-#define WIFI_STA     WIFI_MODE_STA
-#define WIFI_AP      WIFI_MODE_AP
-#define WIFI_AP_STA  WIFI_MODE_APSTA
+#define WIFI_SCAN_RUNNING (-1)
+#define WIFI_SCAN_FAILED  (-2)
 
-#define WiFiEvent_t  system_event_id_t
-#define WiFiEventInfo_t system_event_info_t
-#define WiFiEventId_t wifi_event_id_t
+#define WiFiMode_t  wifi_mode_t
+#define WIFI_OFF    WIFI_MODE_NULL
+#define WIFI_STA    WIFI_MODE_STA
+#define WIFI_AP     WIFI_MODE_AP
+#define WIFI_AP_STA WIFI_MODE_APSTA
 
+#define WiFiEvent_t     arduino_event_id_t
+#define WiFiEventInfo_t arduino_event_info_t
+#define WiFiEventId_t   wifi_event_id_t
 
 typedef enum {
-    WL_NO_SHIELD        = 255,   // for compatibility with WiFi Shield library
-    WL_IDLE_STATUS      = 0,
-    WL_NO_SSID_AVAIL    = 1,
-    WL_SCAN_COMPLETED   = 2,
-    WL_CONNECTED        = 3,
-    WL_CONNECT_FAILED   = 4,
-    WL_CONNECTION_LOST  = 5,
-    WL_DISCONNECTED     = 6
+  WL_NO_SHIELD = 255,  // for compatibility with WiFi Shield library
+  WL_STOPPED = 254,
+  WL_IDLE_STATUS = 0,
+  WL_NO_SSID_AVAIL = 1,
+  WL_SCAN_COMPLETED = 2,
+  WL_CONNECTED = 3,
+  WL_CONNECT_FAILED = 4,
+  WL_CONNECTION_LOST = 5,
+  WL_DISCONNECTED = 6
 } wl_status_t;
 
-#endif /* ESP32WIFITYPE_H_ */
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFi/src/WiFiUdp.cpp b/libraries/WiFi/src/WiFiUdp.cpp
deleted file mode 100644
index 476b5a4a8b5..00000000000
--- a/libraries/WiFi/src/WiFiUdp.cpp
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
-  Udp.cpp - UDP class for Raspberry Pi
-  Copyright (c) 2016 Hristo Gochkov  All right reserved.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-#include "WiFiUdp.h"
-#include <lwip/sockets.h>
-#include <lwip/netdb.h>
-#include <errno.h>
-
-#undef write
-#undef read
-
-WiFiUDP::WiFiUDP()
-: udp_server(-1)
-, server_port(0)
-, remote_port(0)
-, tx_buffer(0)
-, tx_buffer_len(0)
-, rx_buffer(0)
-{}
-
-WiFiUDP::~WiFiUDP(){
-   stop();
-}
-
-uint8_t WiFiUDP::begin(IPAddress address, uint16_t port){
-  stop();
-
-  server_port = port;
-
-  tx_buffer = new char[1460];
-  if(!tx_buffer){
-    log_e("could not create tx buffer: %d", errno);
-    return 0;
-  }
-
-  if ((udp_server=socket(AF_INET, SOCK_DGRAM, 0)) == -1){
-    log_e("could not create socket: %d", errno);
-    return 0;
-  }
-
-  int yes = 1;
-  if (setsockopt(udp_server,SOL_SOCKET,SO_REUSEADDR,&yes,sizeof(yes)) < 0) {
-      log_e("could not set socket option: %d", errno);
-      stop();
-      return 0;
-  }
-
-  struct sockaddr_in addr;
-  memset((char *) &addr, 0, sizeof(addr));
-  addr.sin_family = AF_INET;
-  addr.sin_port = htons(server_port);
-  addr.sin_addr.s_addr = (in_addr_t)address;
-  if(bind(udp_server , (struct sockaddr*)&addr, sizeof(addr)) == -1){
-    log_e("could not bind socket: %d", errno);
-    stop();
-    return 0;
-  }
-  fcntl(udp_server, F_SETFL, O_NONBLOCK);
-  return 1;
-}
-
-uint8_t WiFiUDP::begin(uint16_t p){
-  return begin(IPAddress(INADDR_ANY), p);
-}
-
-uint8_t WiFiUDP::beginMulticast(IPAddress a, uint16_t p){
-  if(begin(IPAddress(INADDR_ANY), p)){
-    if(a != 0){
-      struct ip_mreq mreq;
-      mreq.imr_multiaddr.s_addr = (in_addr_t)a;
-      mreq.imr_interface.s_addr = INADDR_ANY;
-      if (setsockopt(udp_server, IPPROTO_IP, IP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)) < 0) {
-          log_e("could not join igmp: %d", errno);
-          stop();
-          return 0;
-      }
-      multicast_ip = a;
-    }
-    return 1;
-  }
-  return 0;
-}
-
-void WiFiUDP::stop(){
-  if(tx_buffer){
-    delete[] tx_buffer;
-    tx_buffer = NULL;
-  }
-  tx_buffer_len = 0;
-  if(rx_buffer){
-    cbuf *b = rx_buffer;
-    rx_buffer = NULL;
-    delete b;
-  }
-  if(udp_server == -1)
-    return;
-  if(multicast_ip != 0){
-    struct ip_mreq mreq;
-    mreq.imr_multiaddr.s_addr = (in_addr_t)multicast_ip;
-    mreq.imr_interface.s_addr = (in_addr_t)0;
-    setsockopt(udp_server, IPPROTO_IP, IP_DROP_MEMBERSHIP, &mreq, sizeof(mreq));
-    multicast_ip = IPAddress(INADDR_ANY);
-  }
-  close(udp_server);
-  udp_server = -1;
-}
-
-int WiFiUDP::beginMulticastPacket(){
-  if(!server_port || multicast_ip == IPAddress(INADDR_ANY))
-    return 0;
-  remote_ip = multicast_ip;
-  remote_port = server_port;
-  return beginPacket();
-}
-
-int WiFiUDP::beginPacket(){
-  if(!remote_port)
-    return 0;
-
-  // allocate tx_buffer if is necessary
-  if(!tx_buffer){
-    tx_buffer = new char[1460];
-    if(!tx_buffer){
-      log_e("could not create tx buffer: %d", errno);
-      return 0;
-    }
-  }
-
-  tx_buffer_len = 0;
-
-  // check whereas socket is already open
-  if (udp_server != -1)
-    return 1;
-
-  if ((udp_server=socket(AF_INET, SOCK_DGRAM, 0)) == -1){
-    log_e("could not create socket: %d", errno);
-    return 0;
-  }
-
-  fcntl(udp_server, F_SETFL, O_NONBLOCK);
-
-  return 1;
-}
-
-int WiFiUDP::beginPacket(IPAddress ip, uint16_t port){
-  remote_ip = ip;
-  remote_port = port;
-  return beginPacket();
-}
-
-int WiFiUDP::beginPacket(const char *host, uint16_t port){
-  struct hostent *server;
-  server = gethostbyname(host);
-  if (server == NULL){
-    log_e("could not get host from dns: %d", errno);
-    return 0;
-  }
-  return beginPacket(IPAddress((const uint8_t *)(server->h_addr_list[0])), port);
-}
-
-int WiFiUDP::endPacket(){
-  struct sockaddr_in recipient;
-  recipient.sin_addr.s_addr = (uint32_t)remote_ip;
-  recipient.sin_family = AF_INET;
-  recipient.sin_port = htons(remote_port);
-  int sent = sendto(udp_server, tx_buffer, tx_buffer_len, 0, (struct sockaddr*) &recipient, sizeof(recipient));
-  if(sent < 0){
-    log_e("could not send data: %d", errno);
-    return 0;
-  }
-  return 1;
-}
-
-size_t WiFiUDP::write(uint8_t data){
-  if(tx_buffer_len == 1460){
-    endPacket();
-    tx_buffer_len = 0;
-  }
-  tx_buffer[tx_buffer_len++] = data;
-  return 1;
-}
-
-size_t WiFiUDP::write(const uint8_t *buffer, size_t size){
-  size_t i;
-  for(i=0;i<size;i++)
-    write(buffer[i]);
-  return i;
-}
-
-int WiFiUDP::parsePacket(){
-  if(rx_buffer)
-    return 0;
-  struct sockaddr_in si_other;
-  int slen = sizeof(si_other) , len;
-  char * buf = new char[1460];
-  if(!buf){
-    return 0;
-  }
-  if ((len = recvfrom(udp_server, buf, 1460, MSG_DONTWAIT, (struct sockaddr *) &si_other, (socklen_t *)&slen)) == -1){
-    delete[] buf;
-    if(errno == EWOULDBLOCK){
-      return 0;
-    }
-    log_e("could not receive data: %d", errno);
-    return 0;
-  }
-  remote_ip = IPAddress(si_other.sin_addr.s_addr);
-  remote_port = ntohs(si_other.sin_port);
-  if (len > 0) {
-    rx_buffer = new cbuf(len);
-    rx_buffer->write(buf, len);
-  }
-  delete[] buf;
-  return len;
-}
-
-int WiFiUDP::available(){
-  if(!rx_buffer) return 0;
-  return rx_buffer->available();
-}
-
-int WiFiUDP::read(){
-  if(!rx_buffer) return -1;
-  int out = rx_buffer->read();
-  if(!rx_buffer->available()){
-    cbuf *b = rx_buffer;
-    rx_buffer = 0;
-    delete b;
-  }
-  return out;
-}
-
-int WiFiUDP::read(unsigned char* buffer, size_t len){
-  return read((char *)buffer, len);
-}
-
-int WiFiUDP::read(char* buffer, size_t len){
-  if(!rx_buffer) return 0;
-  int out = rx_buffer->read(buffer, len);
-  if(!rx_buffer->available()){
-    cbuf *b = rx_buffer;
-    rx_buffer = 0;
-    delete b;
-  }
-  return out;
-}
-
-int WiFiUDP::peek(){
-  if(!rx_buffer) return -1;
-  return rx_buffer->peek();
-}
-
-void WiFiUDP::flush(){
-  if(!rx_buffer) return;
-  cbuf *b = rx_buffer;
-  rx_buffer = 0;
-  delete b;
-}
-
-IPAddress WiFiUDP::remoteIP(){
-  return remote_ip;
-}
-
-uint16_t WiFiUDP::remotePort(){
-  return remote_port;
-}
diff --git a/libraries/WiFi/src/WiFiUdp.h b/libraries/WiFi/src/WiFiUdp.h
index b543d5f9646..420d29b634b 100644
--- a/libraries/WiFi/src/WiFiUdp.h
+++ b/libraries/WiFi/src/WiFiUdp.h
@@ -1,77 +1,3 @@
-/*
- *  Udp.cpp: Library to send/receive UDP packets.
- *
- * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray for mentioning these)
- * 1) UDP does not guarantee the order in which assembled UDP packets are received. This
- * might not happen often in practice, but in larger network topologies, a UDP
- * packet can be received out of sequence.
- * 2) UDP does not guard against lost packets - so packets *can* disappear without the sender being
- * aware of it. Again, this may not be a concern in practice on small local networks.
- * For more information, see http://www.cafeaulait.org/course/week12/35.html
- *
- * MIT License:
- * Copyright (c) 2008 Bjoern Hartmann
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * bjoern@cs.stanford.edu 12/30/2008
- */
-
-#ifndef _WIFIUDP_H_
-#define _WIFIUDP_H_
-
-#include <Arduino.h>
-#include <Udp.h>
-#include <cbuf.h>
-
-class WiFiUDP : public UDP {
-private:
-  int udp_server;
-  IPAddress multicast_ip;
-  IPAddress remote_ip;
-  uint16_t server_port;
-  uint16_t remote_port;
-  char * tx_buffer;
-  size_t tx_buffer_len;
-  cbuf * rx_buffer;
-public:
-  WiFiUDP();
-  ~WiFiUDP();
-  uint8_t begin(IPAddress a, uint16_t p);
-  uint8_t begin(uint16_t p);
-  uint8_t beginMulticast(IPAddress a, uint16_t p);
-  void stop();
-  int beginMulticastPacket();
-  int beginPacket();
-  int beginPacket(IPAddress ip, uint16_t port);
-  int beginPacket(const char *host, uint16_t port);
-  int endPacket();
-  size_t write(uint8_t);
-  size_t write(const uint8_t *buffer, size_t size);
-  int parsePacket();
-  int available();
-  int read();
-  int read(unsigned char* buffer, size_t len);
-  int read(char* buffer, size_t len);
-  int peek();
-  void flush();
-  IPAddress remoteIP();
-  uint16_t remotePort();
-};
-
-#endif /* _WIFIUDP_H_ */
+#pragma once
+#include "NetworkUdp.h"
+typedef NetworkUDP WiFiUDP;
diff --git a/libraries/WiFiClientSecure/README.md b/libraries/WiFiClientSecure/README.md
deleted file mode 100644
index c7582c15d99..00000000000
--- a/libraries/WiFiClientSecure/README.md
+++ /dev/null
@@ -1,68 +0,0 @@
-WiFiClientSecure
-================
-
-The WiFiClientSecure class implements support for secure connections using TLS (SSL).
-It inherits from WiFiClient and thus implements a superset of that class' interface.
-There are three ways to establish a secure connection using the WiFiClientSecure class:
-using a root certificate authority (CA) cert, using a root CA cert plus a client cert and key,
-and using a pre-shared key (PSK).
-
-Using a root certificate authority cert
----------------------------------------
-This method authenticates the server and negotiates an encrypted connection.
-It is the same functionality as implemented in your web browser when you connect to HTTPS sites.
-
-If you are accessing your own server:
-- Generate a root certificate for your own certificate authority
-- Generate a cert & private key using your root certificate ("self-signed cert") for your server
-
-If you are accessing a public server:
-- Obtain the cert of the public CA that signed that server's cert
-Then:
-- In WiFiClientSecure use setCACert (or the appropriate connect method) to set the root cert of your
-  CA or of the public CA
-- When WiFiClientSecure connects to the target server it uses the CA cert to verify the certificate
-  presented by the server, and then negotiates encryption for the connection
-
-Please see the WiFiClientSecure example.
-
-Using a root CA cert and client cert/keys
------------------------------------------
-This method authenticates the server and additionally also authenticates
-the client to the server, then negotiates an encrypted connection.
-
-- Follow steps above
-- Using your root CA generate cert/key for your client
-- Register the keys with the server you will be accessing so the server can authenticate your client
-- In WiFiClientSecure use setCACert (or the appropriate connect method) to set the root cert of your
-  CA or of the public CA, this is used to authenticate the server
-- In WiFiClientSecure use setCertificate, and setPrivateKey (or the appropriate connect method) to
-  set your client's cert & key, this will be used to authenticate your client to the server
-- When WiFiClientSecure connects to the target server it uses the CA cert to verify the certificate
-  presented by the server, it will use the cert/key to authenticate your client to the server, and
-  it will then negotiate encryption for the connection
-
-Using Pre-Shared Keys (PSK)
----------------------------
-
-TLS supports authentication and encryption using a pre-shared key (i.e. a key that both client and
-server know) as an alternative to the public key cryptography commonly used on the web for HTTPS.
-PSK is starting to be used for MQTT, e.g. in mosquitto, to simplify the set-up and avoid having to
-go through the whole CA, cert, and private key process.
-
-A pre-shared key is a binary string of up to 32 bytes and is commonly represented in hex form. In
-addition to the key, clients can also present an id and typically the server allows a different key
-to be associated with each client id. In effect this is very similar to username and password pairs,
-except that unlike a password the key is not directly transmitted to the server, thus a connection to a
-malicious server does not divulge the password. Plus the server is also authenticated to the client.
-
-To use PSK:
-- Generate a random hex string (generating an MD5 or SHA for some file is one way to do this)
-- Come up with a string id for your client and configure your server to accept the id/key pair
-- In WiFiClientSecure use setPreSharedKey (or the appropriate connect method) to
-  set the id/key combo
-- When WiFiClientSecure connects to the target server it uses the id/key combo to authenticate the
-  server (it must prove that it has the key too), authenticate the client and then negotiate
-  encryption for the connection
-
-Please see the WiFiClientPSK example.
diff --git a/libraries/WiFiClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino b/libraries/WiFiClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino
deleted file mode 100644
index a49ec21e19f..00000000000
--- a/libraries/WiFiClientSecure/examples/WiFiClientSecure/WiFiClientSecure.ino
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
-  Wifi secure connection example for ESP32
-  Running on TLS 1.2 using mbedTLS
-  Suporting the following chipersuites:
-  "TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384","TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384","TLS_DHE_RSA_WITH_AES_256_GCM_SHA384","TLS_ECDHE_ECDSA_WITH_AES_256_CCM","TLS_DHE_RSA_WITH_AES_256_CCM","TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384","TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384","TLS_DHE_RSA_WITH_AES_256_CBC_SHA256","TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA","TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA","TLS_DHE_RSA_WITH_AES_256_CBC_SHA","TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8","TLS_DHE_RSA_WITH_AES_256_CCM_8","TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384","TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384","TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256","TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA","TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256","TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256","TLS_DHE_RSA_WITH_AES_128_GCM_SHA256","TLS_ECDHE_ECDSA_WITH_AES_128_CCM","TLS_DHE_RSA_WITH_AES_128_CCM","TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256","TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256","TLS_DHE_RSA_WITH_AES_128_CBC_SHA256","TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA","TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA","TLS_DHE_RSA_WITH_AES_128_CBC_SHA","TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8","TLS_DHE_RSA_WITH_AES_128_CCM_8","TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA","TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA","TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA","TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA","TLS_DHE_PSK_WITH_AES_256_GCM_SHA384","TLS_DHE_PSK_WITH_AES_256_CCM","TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384","TLS_DHE_PSK_WITH_AES_256_CBC_SHA384","TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA","TLS_DHE_PSK_WITH_AES_256_CBC_SHA","TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384","TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384","TLS_PSK_DHE_WITH_AES_256_CCM_8","TLS_DHE_PSK_WITH_AES_128_GCM_SHA256","TLS_DHE_PSK_WITH_AES_128_CCM","TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256","TLS_DHE_PSK_WITH_AES_128_CBC_SHA256","TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA","TLS_DHE_PSK_WITH_AES_128_CBC_SHA","TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256","TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256","TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256","TLS_PSK_DHE_WITH_AES_128_CCM_8","TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA","TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA","TLS_RSA_WITH_AES_256_GCM_SHA384","TLS_RSA_WITH_AES_256_CCM","TLS_RSA_WITH_AES_256_CBC_SHA256","TLS_RSA_WITH_AES_256_CBC_SHA","TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384","TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384","TLS_ECDH_RSA_WITH_AES_256_CBC_SHA","TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384","TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384","TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA","TLS_RSA_WITH_AES_256_CCM_8","TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256","TLS_RSA_WITH_CAMELLIA_256_CBC_SHA","TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384","TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384","TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384","TLS_RSA_WITH_AES_128_GCM_SHA256","TLS_RSA_WITH_AES_128_CCM","TLS_RSA_WITH_AES_128_CBC_SHA256","TLS_RSA_WITH_AES_128_CBC_SHA","TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256","TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256","TLS_ECDH_RSA_WITH_AES_128_CBC_SHA","TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256","TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256","TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA","TLS_RSA_WITH_AES_128_CCM_8","TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_RSA_WITH_CAMELLIA_128_CBC_SHA","TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256","TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256","TLS_RSA_WITH_3DES_EDE_CBC_SHA","TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA","TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA","TLS_RSA_PSK_WITH_AES_256_GCM_SHA384","TLS_RSA_PSK_WITH_AES_256_CBC_SHA384","TLS_RSA_PSK_WITH_AES_256_CBC_SHA","TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384","TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384","TLS_RSA_PSK_WITH_AES_128_GCM_SHA256","TLS_RSA_PSK_WITH_AES_128_CBC_SHA256","TLS_RSA_PSK_WITH_AES_128_CBC_SHA","TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256","TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256","TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA","TLS_PSK_WITH_AES_256_GCM_SHA384","TLS_PSK_WITH_AES_256_CCM","TLS_PSK_WITH_AES_256_CBC_SHA384","TLS_PSK_WITH_AES_256_CBC_SHA","TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384","TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384","TLS_PSK_WITH_AES_256_CCM_8","TLS_PSK_WITH_AES_128_GCM_SHA256","TLS_PSK_WITH_AES_128_CCM","TLS_PSK_WITH_AES_128_CBC_SHA256","TLS_PSK_WITH_AES_128_CBC_SHA","TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256","TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256","TLS_PSK_WITH_AES_128_CCM_8","TLS_PSK_WITH_3DES_EDE_CBC_SHA","TLS_EMPTY_RENEGOTIATION_INFO_SCSV"]
-  2017 - Evandro Copercini - Apache 2.0 License.
-*/
-
-#include <WiFiClientSecure.h>
-
-const char* ssid     = "your-ssid";     // your network SSID (name of wifi network)
-const char* password = "your-password"; // your network password
-
-const char*  server = "www.howsmyssl.com";  // Server URL
-
-// www.howsmyssl.com root certificate authority, to verify the server
-// change it to your server root CA
-// SHA1 fingerprint is broken now!
-
-const char* test_root_ca= \
-     "-----BEGIN CERTIFICATE-----\n" \
-     "MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n" \
-     "MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n" \
-     "DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n" \
-     "SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n" \
-     "GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n" \
-     "AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n" \
-     "q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n" \
-     "SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n" \
-     "Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n" \
-     "a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n" \
-     "/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n" \
-     "AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n" \
-     "CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n" \
-     "bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n" \
-     "c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n" \
-     "VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n" \
-     "ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n" \
-     "MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n" \
-     "Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n" \
-     "AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n" \
-     "uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n" \
-     "wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n" \
-     "X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n" \
-     "PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n" \
-     "KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n" \
-     "-----END CERTIFICATE-----\n";
-
-// You can use x.509 client certificates if you want
-//const char* test_client_key = "";   //to verify the client
-//const char* test_client_cert = "";  //to verify the client
-
-
-WiFiClientSecure client;
-
-void setup() {
-  //Initialize serial and wait for port to open:
-  Serial.begin(115200);
-  delay(100);
-
-  Serial.print("Attempting to connect to SSID: ");
-  Serial.println(ssid);
-  WiFi.begin(ssid, password);
-
-  // attempt to connect to Wifi network:
-  while (WiFi.status() != WL_CONNECTED) {
-    Serial.print(".");
-    // wait 1 second for re-trying
-    delay(1000);
-  }
-
-  Serial.print("Connected to ");
-  Serial.println(ssid);
-
-  client.setCACert(test_root_ca);
-  //client.setCertificate(test_client_key); // for client verification
-  //client.setPrivateKey(test_client_cert);	// for client verification
-
-  Serial.println("\nStarting connection to server...");
-  if (!client.connect(server, 443))
-    Serial.println("Connection failed!");
-  else {
-    Serial.println("Connected to server!");
-    // Make a HTTP request:
-    client.println("GET https://www.howsmyssl.com/a/check HTTP/1.0");
-    client.println("Host: www.howsmyssl.com");
-    client.println("Connection: close");
-    client.println();
-
-    while (client.connected()) {
-      String line = client.readStringUntil('\n');
-      if (line == "\r") {
-        Serial.println("headers received");
-        break;
-      }
-    }
-    // if there are incoming bytes available
-    // from the server, read them and print them:
-    while (client.available()) {
-      char c = client.read();
-      Serial.write(c);
-    }
-
-    client.stop();
-  }
-}
-
-void loop() {
-  // do nothing
-}
diff --git a/libraries/WiFiClientSecure/examples/WiFiClientSecureEnterprise/WiFiClientSecureEnterprise.ino b/libraries/WiFiClientSecure/examples/WiFiClientSecureEnterprise/WiFiClientSecureEnterprise.ino
deleted file mode 100644
index d4e389c2440..00000000000
--- a/libraries/WiFiClientSecure/examples/WiFiClientSecureEnterprise/WiFiClientSecureEnterprise.ino
+++ /dev/null
@@ -1,117 +0,0 @@
-/*|-----------------------------------------------------------|*/
-/*|WORKING EXAMPLE FOR HTTPS CONNECTION                       |*/
-/*|Author: Bc. Martin Chlebovec                               |*/
-/*|Technical University of Košice                             |*/
-/*|TESTED BOARDS: Devkit v1 DOIT, Devkitc v4                  |*/
-/*|CORE: 0.9x, 1.0.0, 1.0.1 tested, working (newer not tested)|*/
-/*|Supported methods: PEAP + MsCHAPv2, EAP-TTLS + MsCHAPv2    |*/
-/*|-----------------------------------------------------------|*/
-
-#include <WiFi.h>
-#include <WiFiClientSecure.h>
-#include "esp_wpa2.h"
-#include <Wire.h>
-#define EAP_ANONYMOUS_IDENTITY "anonymous@example.com" //anonymous identity
-#define EAP_IDENTITY "id@example.com"                  //user identity
-#define EAP_PASSWORD "password" //eduroam user password
-const char* ssid = "eduroam"; // eduroam SSID
-const char* host = "arduino.php5.sk"; //external server domain for HTTPS connection
-int counter = 0;
-const char* test_root_ca = \
-                           "-----BEGIN CERTIFICATE-----\n" \
-                           "MIIEsTCCA5mgAwIBAgIQCKWiRs1LXIyD1wK0u6tTSTANBgkqhkiG9w0BAQsFADBh\n" \
-                           "MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3\n" \
-                           "d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBD\n" \
-                           "QTAeFw0xNzExMDYxMjIzMzNaFw0yNzExMDYxMjIzMzNaMF4xCzAJBgNVBAYTAlVT\n" \
-                           "MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j\n" \
-                           "b20xHTAbBgNVBAMTFFJhcGlkU1NMIFJTQSBDQSAyMDE4MIIBIjANBgkqhkiG9w0B\n" \
-                           "AQEFAAOCAQ8AMIIBCgKCAQEA5S2oihEo9nnpezoziDtx4WWLLCll/e0t1EYemE5n\n" \
-                           "+MgP5viaHLy+VpHP+ndX5D18INIuuAV8wFq26KF5U0WNIZiQp6mLtIWjUeWDPA28\n" \
-                           "OeyhTlj9TLk2beytbtFU6ypbpWUltmvY5V8ngspC7nFRNCjpfnDED2kRyJzO8yoK\n" \
-                           "MFz4J4JE8N7NA1uJwUEFMUvHLs0scLoPZkKcewIRm1RV2AxmFQxJkdf7YN9Pckki\n" \
-                           "f2Xgm3b48BZn0zf0qXsSeGu84ua9gwzjzI7tbTBjayTpT+/XpWuBVv6fvarI6bik\n" \
-                           "KB859OSGQuw73XXgeuFwEPHTIRoUtkzu3/EQ+LtwznkkdQIDAQABo4IBZjCCAWIw\n" \
-                           "HQYDVR0OBBYEFFPKF1n8a8ADIS8aruSqqByCVtp1MB8GA1UdIwQYMBaAFAPeUDVW\n" \
-                           "0Uy7ZvCj4hsbw5eyPdFVMA4GA1UdDwEB/wQEAwIBhjAdBgNVHSUEFjAUBggrBgEF\n" \
-                           "BQcDAQYIKwYBBQUHAwIwEgYDVR0TAQH/BAgwBgEB/wIBADA0BggrBgEFBQcBAQQo\n" \
-                           "MCYwJAYIKwYBBQUHMAGGGGh0dHA6Ly9vY3NwLmRpZ2ljZXJ0LmNvbTBCBgNVHR8E\n" \
-                           "OzA5MDegNaAzhjFodHRwOi8vY3JsMy5kaWdpY2VydC5jb20vRGlnaUNlcnRHbG9i\n" \
-                           "YWxSb290Q0EuY3JsMGMGA1UdIARcMFowNwYJYIZIAYb9bAECMCowKAYIKwYBBQUH\n" \
-                           "AgEWHGh0dHBzOi8vd3d3LmRpZ2ljZXJ0LmNvbS9DUFMwCwYJYIZIAYb9bAEBMAgG\n" \
-                           "BmeBDAECATAIBgZngQwBAgIwDQYJKoZIhvcNAQELBQADggEBAH4jx/LKNW5ZklFc\n" \
-                           "YWs8Ejbm0nyzKeZC2KOVYR7P8gevKyslWm4Xo4BSzKr235FsJ4aFt6yAiv1eY0tZ\n" \
-                           "/ZN18bOGSGStoEc/JE4ocIzr8P5Mg11kRYHbmgYnr1Rxeki5mSeb39DGxTpJD4kG\n" \
-                           "hs5lXNoo4conUiiJwKaqH7vh2baryd8pMISag83JUqyVGc2tWPpO0329/CWq2kry\n" \
-                           "qv66OSMjwulUz0dXf4OHQasR7CNfIr+4KScc6ABlQ5RDF86PGeE6kdwSQkFiB/cQ\n" \
-                           "ysNyq0jEDQTkfa2pjmuWtMCNbBnhFXBYejfubIhaUbEv2FOQB3dCav+FPg5eEveX\n" \
-                           "TVyMnGo=\n" \
-                           "-----END CERTIFICATE-----\n";
-// You can use x.509 client certificates if you want
-//const char* test_client_key = "";   //to verify the client
-//const char* test_client_cert = "";  //to verify the client
-WiFiClientSecure client;
-void setup() {
-  Serial.begin(115200);
-  delay(10);
-  Serial.println();
-  Serial.print("Connecting to network: ");
-  Serial.println(ssid);
-  WiFi.disconnect(true);  //disconnect form wifi to set new wifi connection
-  WiFi.mode(WIFI_STA); //init wifi mode
-  esp_wifi_sta_wpa2_ent_set_identity((uint8_t *)EAP_ANONYMOUS_IDENTITY, strlen(EAP_ANONYMOUS_IDENTITY)); //provide identity
-  esp_wifi_sta_wpa2_ent_set_username((uint8_t *)EAP_IDENTITY, strlen(EAP_IDENTITY)); //provide username
-  esp_wifi_sta_wpa2_ent_set_password((uint8_t *)EAP_PASSWORD, strlen(EAP_PASSWORD)); //provide password
-  esp_wpa2_config_t config = WPA2_CONFIG_INIT_DEFAULT();
-  esp_wifi_sta_wpa2_ent_enable(&config);
-  WiFi.begin(ssid); //connect to wifi
-  while (WiFi.status() != WL_CONNECTED) {
-    delay(500);
-    Serial.print(".");
-    counter++;
-    if (counter >= 60) { //after 30 seconds timeout - reset board (on unsucessful connection)
-      ESP.restart();
-    }
-  }
-  client.setCACert(test_root_ca);
-  //client.setCertificate(test_client_key); // for client verification - certificate
-  //client.setPrivateKey(test_client_cert);  // for client verification - private key
-  Serial.println("");
-  Serial.println("WiFi connected");
-  Serial.println("IP address set: ");
-  Serial.println(WiFi.localIP()); //print LAN IP
-}
-void loop() {
-  if (WiFi.status() == WL_CONNECTED) { //if we are connected to eduroam network
-    counter = 0; //reset counter
-    Serial.println("Wifi is still connected with IP: ");
-    Serial.println(WiFi.localIP());   //inform user about his IP address
-  } else if (WiFi.status() != WL_CONNECTED) { //if we lost connection, retry
-    WiFi.begin(ssid);
-  }
-  while (WiFi.status() != WL_CONNECTED) { //during lost connection, print dots
-    delay(500);
-    Serial.print(".");
-    counter++;
-    if (counter >= 60) { //30 seconds timeout - reset board
-      ESP.restart();
-    }
-  }
-  Serial.print("Connecting to website: ");
-  Serial.println(host);
-  if (client.connect(host, 443)) {
-    String url = "/rele/rele1.txt";
-    client.print(String("GET ") + url + " HTTP/1.1\r\n" + "Host: " + host + "\r\n" + "User-Agent: ESP32\r\n" + "Connection: close\r\n\r\n");
-    while (client.connected()) {
-      String header = client.readStringUntil('\n');
-      Serial.println(header);
-      if (header == "\r") {
-        break;
-      }
-    }
-    String line = client.readStringUntil('\n');
-    Serial.println(line);
-  } else {
-    Serial.println("Connection unsucessful");
-  }
-  delay(5000);
-}
diff --git a/libraries/WiFiClientSecure/keywords.txt b/libraries/WiFiClientSecure/keywords.txt
deleted file mode 100644
index b1bf2c7388a..00000000000
--- a/libraries/WiFiClientSecure/keywords.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-#######################################
-# Syntax Coloring Map For WiFi
-#######################################
-
-#######################################
-# Library (KEYWORD3)
-#######################################
-
-WiFiClientSecure	KEYWORD3
-
-#######################################
-# Datatypes (KEYWORD1)
-#######################################
-
-WiFiClientSecure	KEYWORD1
-
-#######################################
-# Methods and Functions (KEYWORD2)
-#######################################
-
-connect	KEYWORD2
-write	KEYWORD2
-available	KEYWORD2
-config	KEYWORD2
-read	KEYWORD2
-flush	KEYWORD2
-stop	KEYWORD2
-connected	KEYWORD2
-setCACert	KEYWORD2
-setCertificate	KEYWORD2
-setPrivateKey	KEYWORD2
-
-#######################################
-# Constants (LITERAL1)
-#######################################
diff --git a/libraries/WiFiClientSecure/library.properties b/libraries/WiFiClientSecure/library.properties
deleted file mode 100644
index 7e932754b69..00000000000
--- a/libraries/WiFiClientSecure/library.properties
+++ /dev/null
@@ -1,9 +0,0 @@
-name=WiFiClientSecure
-version=1.0
-author=Evandro Luis Copercini
-maintainer=Github Community
-sentence=Enables secure network connection (local and Internet) using the ESP32 built-in WiFi.
-paragraph=With this library you can make a TLS or SSL connection to a remote server.
-category=Communication
-url=
-architectures=esp32
diff --git a/libraries/WiFiClientSecure/src/WiFiClientSecure.cpp b/libraries/WiFiClientSecure/src/WiFiClientSecure.cpp
deleted file mode 100644
index 5402fd503e5..00000000000
--- a/libraries/WiFiClientSecure/src/WiFiClientSecure.cpp
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
-  WiFiClientSecure.cpp - Client Secure class for ESP32
-  Copyright (c) 2016 Hristo Gochkov  All right reserved.
-  Additions Copyright (C) 2017 Evandro Luis Copercini.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-
-#include "WiFiClientSecure.h"
-#include <lwip/sockets.h>
-#include <lwip/netdb.h>
-#include <errno.h>
-
-#undef connect
-#undef write
-#undef read
-
-
-WiFiClientSecure::WiFiClientSecure()
-{
-    _connected = false;
-
-    sslclient = new sslclient_context;
-    ssl_init(sslclient);
-    sslclient->socket = -1;
-    sslclient->handshake_timeout = 120000;
-    _CA_cert = NULL;
-    _cert = NULL;
-    _private_key = NULL;
-    _pskIdent = NULL;
-    _psKey = NULL;
-    next = NULL;
-}
-
-
-WiFiClientSecure::WiFiClientSecure(int sock)
-{
-    _connected = false;
-    _timeout = 0;
-
-    sslclient = new sslclient_context;
-    ssl_init(sslclient);
-    sslclient->socket = sock;
-    sslclient->handshake_timeout = 120000;
-
-    if (sock >= 0) {
-        _connected = true;
-    }
-
-    _CA_cert = NULL;
-    _cert = NULL;
-    _private_key = NULL;
-    _pskIdent = NULL;
-    _psKey = NULL;
-    next = NULL;
-}
-
-WiFiClientSecure::~WiFiClientSecure()
-{
-    stop();
-    delete sslclient;
-}
-
-WiFiClientSecure &WiFiClientSecure::operator=(const WiFiClientSecure &other)
-{
-    stop();
-    sslclient->socket = other.sslclient->socket;
-    _connected = other._connected;
-    return *this;
-}
-
-void WiFiClientSecure::stop()
-{
-    if (sslclient->socket >= 0) {
-        close(sslclient->socket);
-        sslclient->socket = -1;
-        _connected = false;
-        _peek = -1;
-    }
-    stop_ssl_socket(sslclient, _CA_cert, _cert, _private_key);
-}
-
-int WiFiClientSecure::connect(IPAddress ip, uint16_t port)
-{
-    if (_pskIdent && _psKey)
-        return connect(ip, port, _pskIdent, _psKey);
-    return connect(ip, port, _CA_cert, _cert, _private_key);
-}
-
-int WiFiClientSecure::connect(IPAddress ip, uint16_t port, int32_t timeout){
-    _timeout = timeout;
-    return connect(ip, port);
-}
-
-int WiFiClientSecure::connect(const char *host, uint16_t port)
-{
-    if (_pskIdent && _psKey)
-        return connect(host, port, _pskIdent, _psKey);
-    return connect(host, port, _CA_cert, _cert, _private_key);
-}
-
-int WiFiClientSecure::connect(const char *host, uint16_t port, int32_t timeout){
-    _timeout = timeout;
-    return connect(host, port);
-}
-
-int WiFiClientSecure::connect(IPAddress ip, uint16_t port, const char *_CA_cert, const char *_cert, const char *_private_key)
-{
-    return connect(ip.toString().c_str(), port, _CA_cert, _cert, _private_key);
-}
-
-int WiFiClientSecure::connect(const char *host, uint16_t port, const char *_CA_cert, const char *_cert, const char *_private_key)
-{
-    if(_timeout > 0){
-        sslclient->handshake_timeout = _timeout;
-    }
-    int ret = start_ssl_client(sslclient, host, port, _timeout, _CA_cert, _cert, _private_key, NULL, NULL);
-    _lastError = ret;
-    if (ret < 0) {
-        log_e("start_ssl_client: %d", ret);
-        stop();
-        return 0;
-    }
-    _connected = true;
-    return 1;
-}
-
-int WiFiClientSecure::connect(IPAddress ip, uint16_t port, const char *pskIdent, const char *psKey) {
-    return connect(ip.toString().c_str(), port,_pskIdent, _psKey);
-}
-
-int WiFiClientSecure::connect(const char *host, uint16_t port, const char *pskIdent, const char *psKey) {
-    log_v("start_ssl_client with PSK");
-    if(_timeout > 0){
-        sslclient->handshake_timeout = _timeout;
-    }
-    int ret = start_ssl_client(sslclient, host, port, _timeout, NULL, NULL, NULL, _pskIdent, _psKey);
-    _lastError = ret;
-    if (ret < 0) {
-        log_e("start_ssl_client: %d", ret);
-        stop();
-        return 0;
-    }
-    _connected = true;
-    return 1;
-}
-
-int WiFiClientSecure::peek(){
-    if(_peek >= 0){
-        return _peek;
-    }
-    _peek = timedRead();
-    return _peek;
-}
-
-size_t WiFiClientSecure::write(uint8_t data)
-{
-    return write(&data, 1);
-}
-
-int WiFiClientSecure::read()
-{
-    uint8_t data = -1;
-    int res = read(&data, 1);
-    if (res < 0) {
-        return res;
-    }
-    return data;
-}
-
-size_t WiFiClientSecure::write(const uint8_t *buf, size_t size)
-{
-    if (!_connected) {
-        return 0;
-    }
-    int res = send_ssl_data(sslclient, buf, size);
-    if (res < 0) {
-        stop();
-        res = 0;
-    }
-    return res;
-}
-
-int WiFiClientSecure::read(uint8_t *buf, size_t size)
-{
-    int peeked = 0;
-    int avail = available();
-    if ((!buf && size) || avail <= 0) {
-        return -1;
-    }
-    if(!size){
-        return 0;
-    }
-    if(_peek >= 0){
-        buf[0] = _peek;
-        _peek = -1;
-        size--;
-        avail--;
-        if(!size || !avail){
-            return 1;
-        }
-        buf++;
-        peeked = 1;
-    }
-    
-    int res = get_ssl_receive(sslclient, buf, size);
-    if (res < 0) {
-        stop();
-        return peeked?peeked:res;
-    }
-    return res + peeked;
-}
-
-int WiFiClientSecure::available()
-{
-    int peeked = (_peek >= 0);
-    if (!_connected) {
-        return peeked;
-    }
-    int res = data_to_read(sslclient);
-    if (res < 0) {
-        stop();
-        return peeked?peeked:res;
-    }
-    return res+peeked;
-}
-
-uint8_t WiFiClientSecure::connected()
-{
-    uint8_t dummy = 0;
-    read(&dummy, 0);
-
-    return _connected;
-}
-
-void WiFiClientSecure::setCACert (const char *rootCA)
-{
-    _CA_cert = rootCA;
-}
-
-void WiFiClientSecure::setCertificate (const char *client_ca)
-{
-    _cert = client_ca;
-}
-
-void WiFiClientSecure::setPrivateKey (const char *private_key)
-{
-    _private_key = private_key;
-}
-
-void WiFiClientSecure::setPreSharedKey(const char *pskIdent, const char *psKey) {
-    _pskIdent = pskIdent;
-    _psKey = psKey;
-}
-
-bool WiFiClientSecure::verify(const char* fp, const char* domain_name)
-{
-    if (!sslclient)
-        return false;
-
-    return verify_ssl_fingerprint(sslclient, fp, domain_name);
-}
-
-char *WiFiClientSecure::_streamLoad(Stream& stream, size_t size) {
-  char *dest = (char*)malloc(size+1);
-  if (!dest) {
-    return nullptr;
-  }
-  if (size != stream.readBytes(dest, size)) {
-    free(dest);
-    dest = nullptr;
-    return nullptr;
-  }
-  dest[size] = '\0';
-  return dest;
-}
-
-bool WiFiClientSecure::loadCACert(Stream& stream, size_t size) {
-  char *dest = _streamLoad(stream, size);
-  bool ret = false;
-  if (dest) {
-    setCACert(dest);
-    ret = true;
-  }
-  return ret;
-}
-
-bool WiFiClientSecure::loadCertificate(Stream& stream, size_t size) {
-  char *dest = _streamLoad(stream, size);
-  bool ret = false;
-  if (dest) {
-    setCertificate(dest);
-    ret = true;
-  }
-  return ret;
-}
-
-bool WiFiClientSecure::loadPrivateKey(Stream& stream, size_t size) {
-  char *dest = _streamLoad(stream, size);
-  bool ret = false;
-  if (dest) {
-    setPrivateKey(dest);
-    ret = true;
-  }
-  return ret;
-}
-
-int WiFiClientSecure::lastError(char *buf, const size_t size)
-{
-    if (!_lastError) {
-        return 0;
-    }
-    char error_buf[100];
-    mbedtls_strerror(_lastError, error_buf, 100);
-    snprintf(buf, size, "%s", error_buf);
-    return _lastError;
-}
-
-void WiFiClientSecure::setHandshakeTimeout(unsigned long handshake_timeout)
-{
-    sslclient->handshake_timeout = handshake_timeout * 1000;
-}
diff --git a/libraries/WiFiClientSecure/src/WiFiClientSecure.h b/libraries/WiFiClientSecure/src/WiFiClientSecure.h
deleted file mode 100644
index cd4f20e0f1c..00000000000
--- a/libraries/WiFiClientSecure/src/WiFiClientSecure.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
-  WiFiClientSecure.h - Base class that provides Client SSL to ESP32
-  Copyright (c) 2011 Adrian McEwen.  All right reserved.
-  Additions Copyright (C) 2017 Evandro Luis Copercini.
-
-  This library is free software; you can redistribute it and/or
-  modify it under the terms of the GNU Lesser General Public
-  License as published by the Free Software Foundation; either
-  version 2.1 of the License, or (at your option) any later version.
-
-  This library is distributed in the hope that it will be useful,
-  but WITHOUT ANY WARRANTY; without even the implied warranty of
-  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-  Lesser General Public License for more details.
-
-  You should have received a copy of the GNU Lesser General Public
-  License along with this library; if not, write to the Free Software
-  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-*/
-
-#ifndef WiFiClientSecure_h
-#define WiFiClientSecure_h
-#include "Arduino.h"
-#include "IPAddress.h"
-#include <WiFi.h>
-#include "ssl_client.h"
-
-class WiFiClientSecure : public WiFiClient
-{
-protected:
-    sslclient_context *sslclient;
- 
-    int _lastError = 0;
-	int _peek = -1;
-    int _timeout = 0;
-    const char *_CA_cert;
-    const char *_cert;
-    const char *_private_key;
-    const char *_pskIdent; // identity for PSK cipher suites
-    const char *_psKey; // key in hex for PSK cipher suites
-
-public:
-    WiFiClientSecure *next;
-    WiFiClientSecure();
-    WiFiClientSecure(int socket);
-    ~WiFiClientSecure();
-    int connect(IPAddress ip, uint16_t port);
-    int connect(IPAddress ip, uint16_t port, int32_t timeout);
-    int connect(const char *host, uint16_t port);
-    int connect(const char *host, uint16_t port, int32_t timeout);
-    int connect(IPAddress ip, uint16_t port, const char *rootCABuff, const char *cli_cert, const char *cli_key);
-    int connect(const char *host, uint16_t port, const char *rootCABuff, const char *cli_cert, const char *cli_key);
-    int connect(IPAddress ip, uint16_t port, const char *pskIdent, const char *psKey);
-    int connect(const char *host, uint16_t port, const char *pskIdent, const char *psKey);
-	int peek();
-    size_t write(uint8_t data);
-    size_t write(const uint8_t *buf, size_t size);
-    int available();
-    int read();
-    int read(uint8_t *buf, size_t size);
-    void flush() {}
-    void stop();
-    uint8_t connected();
-    int lastError(char *buf, const size_t size);
-    void setPreSharedKey(const char *pskIdent, const char *psKey); // psKey in Hex
-    void setCACert(const char *rootCA);
-    void setCertificate(const char *client_ca);
-    void setPrivateKey (const char *private_key);
-    bool loadCACert(Stream& stream, size_t size);
-    bool loadCertificate(Stream& stream, size_t size);
-    bool loadPrivateKey(Stream& stream, size_t size);
-    bool verify(const char* fingerprint, const char* domain_name);
-    void setHandshakeTimeout(unsigned long handshake_timeout);
-
-    int setTimeout(uint32_t seconds){ return 0; }
-
-    operator bool()
-    {
-        return connected();
-    }
-    WiFiClientSecure &operator=(const WiFiClientSecure &other);
-    bool operator==(const bool value)
-    {
-        return bool() == value;
-    }
-    bool operator!=(const bool value)
-    {
-        return bool() != value;
-    }
-    bool operator==(const WiFiClientSecure &);
-    bool operator!=(const WiFiClientSecure &rhs)
-    {
-        return !this->operator==(rhs);
-    };
-
-    int socket()
-    {
-        return sslclient->socket = -1;
-    }
-
-private:
-    char *_streamLoad(Stream& stream, size_t size);
-
-    //friend class WiFiServer;
-    using Print::write;
-};
-
-#endif /* _WIFICLIENT_H_ */
diff --git a/libraries/WiFiClientSecure/src/ssl_client.cpp b/libraries/WiFiClientSecure/src/ssl_client.cpp
deleted file mode 100644
index 9f168a0aabd..00000000000
--- a/libraries/WiFiClientSecure/src/ssl_client.cpp
+++ /dev/null
@@ -1,453 +0,0 @@
-/* Provide SSL/TLS functions to ESP32 with Arduino IDE
-*
-* Adapted from the ssl_client1 example of mbedtls.
-*
-* Original Copyright (C) 2006-2015, ARM Limited, All Rights Reserved, Apache 2.0 License.
-* Additions Copyright (C) 2017 Evandro Luis Copercini, Apache 2.0 License.
-*/
-
-#include "Arduino.h"
-#include <esp32-hal-log.h>
-#include <lwip/err.h>
-#include <lwip/sockets.h>
-#include <lwip/sys.h>
-#include <lwip/netdb.h>
-#include <mbedtls/sha256.h>
-#include <mbedtls/oid.h>
-#include <algorithm>
-#include <string>
-#include "ssl_client.h"
-#include "WiFi.h"
-
-#ifndef MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED
-#  error "Please configure IDF framework to include mbedTLS -> Enable pre-shared-key ciphersuites and activate at least one cipher"
-#endif
-
-const char *pers = "esp32-tls";
-
-static int _handle_error(int err, const char * file, int line)
-{
-    if(err == -30848){
-        return err;
-    }
-#ifdef MBEDTLS_ERROR_C
-    char error_buf[100];
-    mbedtls_strerror(err, error_buf, 100);
-    log_e("[%s():%d]: (%d) %s", file, line, err, error_buf);
-#else
-    log_e("[%s():%d]: code %d", file, line, err);
-#endif
-    return err;
-}
-
-#define handle_error(e) _handle_error(e, __FUNCTION__, __LINE__)
-
-
-void ssl_init(sslclient_context *ssl_client)
-{
-    mbedtls_ssl_init(&ssl_client->ssl_ctx);
-    mbedtls_ssl_config_init(&ssl_client->ssl_conf);
-    mbedtls_ctr_drbg_init(&ssl_client->drbg_ctx);
-}
-
-
-int start_ssl_client(sslclient_context *ssl_client, const char *host, uint32_t port, int timeout, const char *rootCABuff, const char *cli_cert, const char *cli_key, const char *pskIdent, const char *psKey)
-{
-    char buf[512];
-    int ret, flags;
-    int enable = 1;
-    log_v("Free internal heap before TLS %u", ESP.getFreeHeap());
-
-    log_v("Starting socket");
-    ssl_client->socket = -1;
-
-    ssl_client->socket = lwip_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
-    if (ssl_client->socket < 0) {
-        log_e("ERROR opening socket");
-        return ssl_client->socket;
-    }
-
-    IPAddress srv((uint32_t)0);
-    if(!WiFiGenericClass::hostByName(host, srv)){
-        return -1;
-    }
-
-    struct sockaddr_in serv_addr;
-    memset(&serv_addr, 0, sizeof(serv_addr));
-    serv_addr.sin_family = AF_INET;
-    serv_addr.sin_addr.s_addr = srv;
-    serv_addr.sin_port = htons(port);
-
-    if (lwip_connect(ssl_client->socket, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) == 0) {
-        if(timeout <= 0){
-            timeout = 30000; // Milli seconds.
-        }
-        timeval so_timeout = { .tv_sec = timeout / 1000, .tv_usec = (timeout % 1000) * 1000 };
-
-#define ROE(x,msg) { if (((x)<0)) { log_e("LWIP Socket config of " msg " failed."); return -1; }}
-        ROE(lwip_setsockopt(ssl_client->socket, SOL_SOCKET, SO_RCVTIMEO, &so_timeout, sizeof(so_timeout)),"SO_RCVTIMEO");
-        ROE(lwip_setsockopt(ssl_client->socket, SOL_SOCKET, SO_SNDTIMEO, &so_timeout, sizeof(so_timeout)),"SO_SNDTIMEO");
-
-        ROE(lwip_setsockopt(ssl_client->socket, IPPROTO_TCP, TCP_NODELAY, &enable, sizeof(enable)),"TCP_NODELAY");
-        ROE(lwip_setsockopt(ssl_client->socket, SOL_SOCKET, SO_KEEPALIVE, &enable, sizeof(enable)),"SO_KEEPALIVE");
-    } else {
-        log_e("Connect to Server failed!");
-        return -1;
-    }
-
-    fcntl( ssl_client->socket, F_SETFL, fcntl( ssl_client->socket, F_GETFL, 0 ) | O_NONBLOCK );
-
-    log_v("Seeding the random number generator");
-    mbedtls_entropy_init(&ssl_client->entropy_ctx);
-
-    ret = mbedtls_ctr_drbg_seed(&ssl_client->drbg_ctx, mbedtls_entropy_func,
-                                &ssl_client->entropy_ctx, (const unsigned char *) pers, strlen(pers));
-    if (ret < 0) {
-        return handle_error(ret);
-    }
-
-    log_v("Setting up the SSL/TLS structure...");
-
-    if ((ret = mbedtls_ssl_config_defaults(&ssl_client->ssl_conf,
-                                           MBEDTLS_SSL_IS_CLIENT,
-                                           MBEDTLS_SSL_TRANSPORT_STREAM,
-                                           MBEDTLS_SSL_PRESET_DEFAULT)) != 0) {
-        return handle_error(ret);
-    }
-
-    // MBEDTLS_SSL_VERIFY_REQUIRED if a CA certificate is defined on Arduino IDE and
-    // MBEDTLS_SSL_VERIFY_NONE if not.
-
-    if (rootCABuff != NULL) {
-        log_v("Loading CA cert");
-        mbedtls_x509_crt_init(&ssl_client->ca_cert);
-        mbedtls_ssl_conf_authmode(&ssl_client->ssl_conf, MBEDTLS_SSL_VERIFY_REQUIRED);
-        ret = mbedtls_x509_crt_parse(&ssl_client->ca_cert, (const unsigned char *)rootCABuff, strlen(rootCABuff) + 1);
-        mbedtls_ssl_conf_ca_chain(&ssl_client->ssl_conf, &ssl_client->ca_cert, NULL);
-        //mbedtls_ssl_conf_verify(&ssl_client->ssl_ctx, my_verify, NULL );
-        if (ret < 0) {
-		// free the ca_cert in the case parse failed, otherwise, the old ca_cert still in the heap memory, that lead to "out of memory" crash.
-		mbedtls_x509_crt_free(&ssl_client->ca_cert);
-            return handle_error(ret);
-        }
-    } else if (pskIdent != NULL && psKey != NULL) {
-        log_v("Setting up PSK");
-        // convert PSK from hex to binary
-        if ((strlen(psKey) & 1) != 0 || strlen(psKey) > 2*MBEDTLS_PSK_MAX_LEN) {
-            log_e("pre-shared key not valid hex or too long");
-            return -1;
-        }
-        unsigned char psk[MBEDTLS_PSK_MAX_LEN];
-        size_t psk_len = strlen(psKey)/2;
-        for (int j=0; j<strlen(psKey); j+= 2) {
-            char c = psKey[j];
-            if (c >= '0' && c <= '9') c -= '0';
-            else if (c >= 'A' && c <= 'F') c -= 'A' - 10;
-            else if (c >= 'a' && c <= 'f') c -= 'a' - 10;
-            else return -1;
-            psk[j/2] = c<<4;
-            c = psKey[j+1];
-            if (c >= '0' && c <= '9') c -= '0';
-            else if (c >= 'A' && c <= 'F') c -= 'A' - 10;
-            else if (c >= 'a' && c <= 'f') c -= 'a' - 10;
-            else return -1;
-            psk[j/2] |= c;
-        }
-        // set mbedtls config
-        ret = mbedtls_ssl_conf_psk(&ssl_client->ssl_conf, psk, psk_len,
-                 (const unsigned char *)pskIdent, strlen(pskIdent));
-        if (ret != 0) {
-            log_e("mbedtls_ssl_conf_psk returned %d", ret);
-            return handle_error(ret);
-        }
-    } else {
-        mbedtls_ssl_conf_authmode(&ssl_client->ssl_conf, MBEDTLS_SSL_VERIFY_NONE);
-        log_i("WARNING: Use certificates for a more secure communication!");
-    }
-
-    if (cli_cert != NULL && cli_key != NULL) {
-        mbedtls_x509_crt_init(&ssl_client->client_cert);
-        mbedtls_pk_init(&ssl_client->client_key);
-
-        log_v("Loading CRT cert");
-
-        ret = mbedtls_x509_crt_parse(&ssl_client->client_cert, (const unsigned char *)cli_cert, strlen(cli_cert) + 1);
-        if (ret < 0) {
-		// free the client_cert in the case parse failed, otherwise, the old client_cert still in the heap memory, that lead to "out of memory" crash.
-		mbedtls_x509_crt_free(&ssl_client->client_cert);
-            return handle_error(ret);
-        }
-
-        log_v("Loading private key");
-        ret = mbedtls_pk_parse_key(&ssl_client->client_key, (const unsigned char *)cli_key, strlen(cli_key) + 1, NULL, 0);
-
-        if (ret != 0) {
-            return handle_error(ret);
-        }
-
-        mbedtls_ssl_conf_own_cert(&ssl_client->ssl_conf, &ssl_client->client_cert, &ssl_client->client_key);
-    }
-
-    log_v("Setting hostname for TLS session...");
-
-    // Hostname set here should match CN in server certificate
-    if((ret = mbedtls_ssl_set_hostname(&ssl_client->ssl_ctx, host)) != 0){
-        return handle_error(ret);
-	}
-
-    mbedtls_ssl_conf_rng(&ssl_client->ssl_conf, mbedtls_ctr_drbg_random, &ssl_client->drbg_ctx);
-
-    if ((ret = mbedtls_ssl_setup(&ssl_client->ssl_ctx, &ssl_client->ssl_conf)) != 0) {
-        return handle_error(ret);
-    }
-
-    mbedtls_ssl_set_bio(&ssl_client->ssl_ctx, &ssl_client->socket, mbedtls_net_send, mbedtls_net_recv, NULL );
-
-    log_v("Performing the SSL/TLS handshake...");
-    unsigned long handshake_start_time=millis();
-    while ((ret = mbedtls_ssl_handshake(&ssl_client->ssl_ctx)) != 0) {
-        if (ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE) {
-            return handle_error(ret);
-        }
-        if((millis()-handshake_start_time)>ssl_client->handshake_timeout)
-			return -1;
-	    vTaskDelay(10 / portTICK_PERIOD_MS);
-    }
-
-
-    if (cli_cert != NULL && cli_key != NULL) {
-        log_d("Protocol is %s Ciphersuite is %s", mbedtls_ssl_get_version(&ssl_client->ssl_ctx), mbedtls_ssl_get_ciphersuite(&ssl_client->ssl_ctx));
-        if ((ret = mbedtls_ssl_get_record_expansion(&ssl_client->ssl_ctx)) >= 0) {
-            log_d("Record expansion is %d", ret);
-        } else {
-            log_w("Record expansion is unknown (compression)");
-        }
-    }
-
-    log_v("Verifying peer X.509 certificate...");
-
-    if ((flags = mbedtls_ssl_get_verify_result(&ssl_client->ssl_ctx)) != 0) {
-        bzero(buf, sizeof(buf));
-        mbedtls_x509_crt_verify_info(buf, sizeof(buf), "  ! ", flags);
-        log_e("Failed to verify peer certificate! verification info: %s", buf);
-        stop_ssl_socket(ssl_client, rootCABuff, cli_cert, cli_key);  //It's not safe continue.
-        return handle_error(ret);
-    } else {
-        log_v("Certificate verified.");
-    }
-    
-    if (rootCABuff != NULL) {
-        mbedtls_x509_crt_free(&ssl_client->ca_cert);
-    }
-
-    if (cli_cert != NULL) {
-        mbedtls_x509_crt_free(&ssl_client->client_cert);
-    }
-
-    if (cli_key != NULL) {
-        mbedtls_pk_free(&ssl_client->client_key);
-    }    
-
-    log_v("Free internal heap after TLS %u", ESP.getFreeHeap());
-
-    return ssl_client->socket;
-}
-
-
-void stop_ssl_socket(sslclient_context *ssl_client, const char *rootCABuff, const char *cli_cert, const char *cli_key)
-{
-    log_v("Cleaning SSL connection.");
-
-    if (ssl_client->socket >= 0) {
-        close(ssl_client->socket);
-        ssl_client->socket = -1;
-    }
-
-    mbedtls_ssl_free(&ssl_client->ssl_ctx);
-    mbedtls_ssl_config_free(&ssl_client->ssl_conf);
-    mbedtls_ctr_drbg_free(&ssl_client->drbg_ctx);
-    mbedtls_entropy_free(&ssl_client->entropy_ctx);
-}
-
-
-int data_to_read(sslclient_context *ssl_client)
-{
-    int ret, res;
-    ret = mbedtls_ssl_read(&ssl_client->ssl_ctx, NULL, 0);
-    //log_e("RET: %i",ret);   //for low level debug
-    res = mbedtls_ssl_get_bytes_avail(&ssl_client->ssl_ctx);
-    //log_e("RES: %i",res);    //for low level debug
-    if (ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE && ret < 0) {
-        return handle_error(ret);
-    }
-
-    return res;
-}
-
-int send_ssl_data(sslclient_context *ssl_client, const uint8_t *data, uint16_t len)
-{
-    log_v("Writing HTTP request with %d bytes...", len); //for low level debug
-    int ret = -1;
-
-    if ((ret = mbedtls_ssl_write(&ssl_client->ssl_ctx, data, len)) <= 0){
-        log_v("Handling error %d", ret); //for low level debug
-        return handle_error(ret);
-    } else{
-        log_v("Returning with %d bytes written", ret); //for low level debug
-    }
-
-    return ret;
-}
-
-int get_ssl_receive(sslclient_context *ssl_client, uint8_t *data, int length)
-{
-    //log_d( "Reading HTTP response...");   //for low level debug
-    int ret = -1;
-
-    ret = mbedtls_ssl_read(&ssl_client->ssl_ctx, data, length);
-
-    //log_v( "%d bytes read", ret);   //for low level debug
-    return ret;
-}
-
-static bool parseHexNibble(char pb, uint8_t* res)
-{
-    if (pb >= '0' && pb <= '9') {
-        *res = (uint8_t) (pb - '0'); return true;
-    } else if (pb >= 'a' && pb <= 'f') {
-        *res = (uint8_t) (pb - 'a' + 10); return true;
-    } else if (pb >= 'A' && pb <= 'F') {
-        *res = (uint8_t) (pb - 'A' + 10); return true;
-    }
-    return false;
-}
-
-// Compare a name from certificate and domain name, return true if they match
-static bool matchName(const std::string& name, const std::string& domainName)
-{
-    size_t wildcardPos = name.find('*');
-    if (wildcardPos == std::string::npos) {
-        // Not a wildcard, expect an exact match
-        return name == domainName;
-    }
-
-    size_t firstDotPos = name.find('.');
-    if (wildcardPos > firstDotPos) {
-        // Wildcard is not part of leftmost component of domain name
-        // Do not attempt to match (rfc6125 6.4.3.1)
-        return false;
-    }
-    if (wildcardPos != 0 || firstDotPos != 1) {
-        // Matching of wildcards such as baz*.example.com and b*z.example.com
-        // is optional. Maybe implement this in the future?
-        return false;
-    }
-    size_t domainNameFirstDotPos = domainName.find('.');
-    if (domainNameFirstDotPos == std::string::npos) {
-        return false;
-    }
-    return domainName.substr(domainNameFirstDotPos) == name.substr(firstDotPos);
-}
-
-// Verifies certificate provided by the peer to match specified SHA256 fingerprint
-bool verify_ssl_fingerprint(sslclient_context *ssl_client, const char* fp, const char* domain_name)
-{
-    // Convert hex string to byte array
-    uint8_t fingerprint_local[32];
-    int len = strlen(fp);
-    int pos = 0;
-    for (size_t i = 0; i < sizeof(fingerprint_local); ++i) {
-        while (pos < len && ((fp[pos] == ' ') || (fp[pos] == ':'))) {
-            ++pos;
-        }
-        if (pos > len - 2) {
-            log_d("pos:%d len:%d fingerprint too short", pos, len);
-            return false;
-        }
-        uint8_t high, low;
-        if (!parseHexNibble(fp[pos], &high) || !parseHexNibble(fp[pos+1], &low)) {
-            log_d("pos:%d len:%d invalid hex sequence: %c%c", pos, len, fp[pos], fp[pos+1]);
-            return false;
-        }
-        pos += 2;
-        fingerprint_local[i] = low | (high << 4);
-    }
-
-    // Get certificate provided by the peer
-    const mbedtls_x509_crt* crt = mbedtls_ssl_get_peer_cert(&ssl_client->ssl_ctx);
-
-    if (!crt)
-    {
-        log_d("could not fetch peer certificate");
-        return false;
-    }
-
-    // Calculate certificate's SHA256 fingerprint
-    uint8_t fingerprint_remote[32];
-    mbedtls_sha256_context sha256_ctx;
-    mbedtls_sha256_init(&sha256_ctx);
-    mbedtls_sha256_starts(&sha256_ctx, false);
-    mbedtls_sha256_update(&sha256_ctx, crt->raw.p, crt->raw.len);
-    mbedtls_sha256_finish(&sha256_ctx, fingerprint_remote);
-
-    // Check if fingerprints match
-    if (memcmp(fingerprint_local, fingerprint_remote, 32))
-    {
-        log_d("fingerprint doesn't match");
-        return false;
-    }
-
-    // Additionally check if certificate has domain name if provided
-    if (domain_name)
-        return verify_ssl_dn(ssl_client, domain_name);
-    else
-        return true;
-}
-
-// Checks if peer certificate has specified domain in CN or SANs
-bool verify_ssl_dn(sslclient_context *ssl_client, const char* domain_name)
-{
-    log_d("domain name: '%s'", (domain_name)?domain_name:"(null)");
-    std::string domain_name_str(domain_name);
-    std::transform(domain_name_str.begin(), domain_name_str.end(), domain_name_str.begin(), ::tolower);
-
-    // Get certificate provided by the peer
-    const mbedtls_x509_crt* crt = mbedtls_ssl_get_peer_cert(&ssl_client->ssl_ctx);
-
-    // Check for domain name in SANs
-    const mbedtls_x509_sequence* san = &crt->subject_alt_names;
-    while (san != nullptr)
-    {
-        std::string san_str((const char*)san->buf.p, san->buf.len);
-        std::transform(san_str.begin(), san_str.end(), san_str.begin(), ::tolower);
-
-        if (matchName(san_str, domain_name_str))
-            return true;
-
-        log_d("SAN '%s': no match", san_str.c_str());
-
-        // Fetch next SAN
-        san = san->next;
-    }
-
-    // Check for domain name in CN
-    const mbedtls_asn1_named_data* common_name = &crt->subject;
-    while (common_name != nullptr)
-    {
-        // While iterating through DN objects, check for CN object
-        if (!MBEDTLS_OID_CMP(MBEDTLS_OID_AT_CN, &common_name->oid))
-        {
-            std::string common_name_str((const char*)common_name->val.p, common_name->val.len);
-
-            if (matchName(common_name_str, domain_name_str))
-                return true;
-
-            log_d("CN '%s': not match", common_name_str.c_str());
-        }
-
-        // Fetch next DN object
-        common_name = common_name->next;
-    }
-
-    return false;
-}
diff --git a/libraries/WiFiClientSecure/src/ssl_client.h b/libraries/WiFiClientSecure/src/ssl_client.h
deleted file mode 100644
index dd57a0ff45f..00000000000
--- a/libraries/WiFiClientSecure/src/ssl_client.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Provide SSL/TLS functions to ESP32 with Arduino IDE
- * by Evandro Copercini - 2017 - Apache 2.0 License
- */
-
-#ifndef ARD_SSL_H
-#define ARD_SSL_H
-#include "mbedtls/platform.h"
-#include "mbedtls/net.h"
-#include "mbedtls/debug.h"
-#include "mbedtls/ssl.h"
-#include "mbedtls/entropy.h"
-#include "mbedtls/ctr_drbg.h"
-#include "mbedtls/error.h"
-
-typedef struct sslclient_context {
-    int socket;
-    mbedtls_ssl_context ssl_ctx;
-    mbedtls_ssl_config ssl_conf;
-
-    mbedtls_ctr_drbg_context drbg_ctx;
-    mbedtls_entropy_context entropy_ctx;
-
-    mbedtls_x509_crt ca_cert;
-    mbedtls_x509_crt client_cert;
-    mbedtls_pk_context client_key;
-
-    unsigned long handshake_timeout;
-} sslclient_context;
-
-
-void ssl_init(sslclient_context *ssl_client);
-int start_ssl_client(sslclient_context *ssl_client, const char *host, uint32_t port, int timeout, const char *rootCABuff, const char *cli_cert, const char *cli_key, const char *pskIdent, const char *psKey);
-void stop_ssl_socket(sslclient_context *ssl_client, const char *rootCABuff, const char *cli_cert, const char *cli_key);
-int data_to_read(sslclient_context *ssl_client);
-int send_ssl_data(sslclient_context *ssl_client, const uint8_t *data, uint16_t len);
-int get_ssl_receive(sslclient_context *ssl_client, uint8_t *data, int length);
-bool verify_ssl_fingerprint(sslclient_context *ssl_client, const char* fp, const char* domain_name);
-bool verify_ssl_dn(sslclient_context *ssl_client, const char* domain_name);
-
-#endif
diff --git a/libraries/WiFiProv/examples/WiFiProv/README.md b/libraries/WiFiProv/examples/WiFiProv/README.md
index 0350de7af96..690c27606d0 100644
--- a/libraries/WiFiProv/examples/WiFiProv/README.md
+++ b/libraries/WiFiProv/examples/WiFiProv/README.md
@@ -1,126 +1,125 @@
 # Provisioning for Arduino
 
-This sketch implements provisioning using various IDF components
+This sketch implements provisioning using various IDF components.
 
-# Description
+## Description
 
-This example allows Arduino user to choose either BLE or SOFTAP as a mode of transport, over which the provisioning related communication is to take place, between the device (to be provisioned) and the client (owner of the device).
+This example allows Arduino users to choose either BLE or SOFTAP as the mode of transport for provisioning-related communication between the device (to be provisioned) and the client (owner of the device).
 
-# APIs introduced for provisioning
+## APIs introduced for provisioning
 
-## WiFi.onEvent()
+<!-- vale off -->
+### WiFi.onEvent()
+<!-- vale on -->
 
-Using this API user can register to receive WiFi Events and Provisioning Events
+This API can be used to register a function to be called from another
+thread for Wi-Fi Events and Provisioning Events.
 
-#### Parameters passed
-
-A function with following signature
-* void SysProvEvent(system_event_t * , wifi_prov_event_t * );
- 
-#### structure [ wifi_prov_event_t ]
-
-* wifi_prov_cb_event_t event;
-* void * event_data;
-
-## WiFi.beginProvision()
+<!-- vale off -->
+### WiFi.beginProvision()
+<!-- vale on -->
 
-WiFi.beginProvision(void ( * scheme_cb)(), wifi_prov_scheme_event_handler_t scheme_event_handler, wifi_prov_security_t security, char * pop, char * service_name, char * service_key, uint8_t * uuid);
+```
+WiFi.beginProvision(void (*scheme_cb)(), wifi_prov_scheme_event_handler_t scheme_event_handler, wifi_prov_security_t security, char *pop, char *service_name, char *service_key, uint8_t *uuid);
+```
 
 #### Parameters passed
 
-*  function pointer : choose the mode of transfer
-    * provSchemeBLE - Using BLE
-    * provSchemeSoftAP - Using SoftAP
-        
-* security : choose security type
-    * WIFI_PROV_SECURITY_1 - It allows secure communication which consists of secure handshake using key exchange and proof of possession (pop) and encryption/decryption of messages.
+- Function pointer: Choose the mode of transfer
+    - `provSchemeBLE` - Using BLE
+    - `provSchemeSoftAP` - Using SoftAP
 
-    * WIFI_PROV_SECURITY_0 - It do not provide application level security, it involve simply plain text communication.
+- `security`: Choose the security type
+    - `WIFI_PROV_SECURITY_1` - Enables secure communication with a secure handshake using key exchange and proof of possession (pop), and encryption/decryption of messages.
+    - `WIFI_PROV_SECURITY_0` - Does not provide application-level security, allowing plain text communication.
 
-* scheme_event_handler : specify the handlers according to the mode chosen
-    * BLE :
-        - WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BTDM - This scheme event handler is used when application doesn't need BT and BLE after provisioning is finised
-        - WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BLE - This scheme event handler is used when application doesn't need BLE to be active after provisioning is finised
-        - WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BT - This scheme event handler is used when application doesn't need BT to be active after provisioning is finised
+- `scheme_event_handler`: Specify the handlers according to the chosen mode
+    - BLE:
+        - `WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BTDM` - Used when the application doesn't need BT and BLE after provisioning is finished.
+        - `WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BLE` - Used when the application doesn't need BLE to be active after provisioning is finished.
+        - `WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BT` - Used when the application doesn't need BT to be active after provisioning is finished.
 
-    * SoftAp :
-        - WIFI_PROV_EVENT_HANDLER_NONE
+    - SoftAP:
+        - `WIFI_PROV_EVENT_HANDLER_NONE`
 
-* pop : It is the string that is used to provide the authentication.
+- `pop`: String used for authentication.
 
-* service_name : Specify service name for the device, if it is not specified then default chosen name is PROV_XXX where XXX are the last 3 bytes of the MAC address.  
+- `service_name`: Specify the service name for the device. If not specified, the default chosen name is `PROV_XXX`, where XXX represents the last 3 bytes of the MAC address.
 
-* service_key : Specify service key, if chosen mode of provisioning is BLE then service_key is always NULL
+- `service_key`: Specify the service key. If the chosen mode of provisioning is BLE, the `service_key` is always NULL.
 
-* uuid : user can specify there own 128 bit UUID while provisioning using BLE, if not specified then default value taken is
-        - {  0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf,
-             0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02, }
+- `uuid`: Users can specify their own 128-bit UUID while provisioning using BLE. If not specified, the default value is:
 
-# NOTE
+```
+{ 0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf, 0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02 }
+```
+
+- `reset_provisioned`: Resets previously provisioned data before initializing. Using this prevents problem when the device automatically connects to previously connected Wi-Fi and therefore cannot be found.
 
-* If none of the parameters are specified in beginProvision then default provisioning takes place using SoftAP with
-    * scheme = WIFI_PROV_SCHEME_SOFTAP
-    * scheme_event_handler = WIFI_PROV_EVENT_HANDLER_NONE
-    * security = WIFI_PROV_SECURITY_1
-    * pop = "abcd1234"
-    * service_name = "PROV_XXX"
-    * service_key = NULL
-    * uuid = NULL
+**NOTE:** If none of the parameters are specified in `beginProvision`, default provisioning takes place using SoftAP with the following settings:
+- `scheme = WIFI_PROV_SCHEME_SOFTAP`
+- `scheme_event_handler = WIFI_PROV_EVENT_HANDLER_NONE`
+- `security = WIFI_PROV_SECURITY_1`
+- `pop = "abcd1234"`
+- `service_name = "PROV_XXX"`
+- `service_key = NULL`
+- `uuid = NULL`
+- `reset_provisioned = false`
 
-# Log Output
-* Enable debuger : [ Tools -> Core Debug Level -> Info ] 
+## Flashing
+This sketch takes up a lot of space for the app and may not be able to flash with default setting on some chips.
+If you see Error like this: "Sketch too big"
+In Arduino IDE go to: Tools > Partition scheme > chose anything that has more than 1.4 MB APP for example `No OTA (2MB APP/2MB SPIFFS)`
 
-# Provisioning Tools
-https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/provisioning/wifi_provisioning.html#provisioning-tools
+## Log Output
+- To enable debugging: Go to Tools -> Core Debug Level -> Info.
 
-# Example output
+## Provisioning Tools
+[Provisioning Tools](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/provisioning/wifi_provisioning.html#provisioning-tools)
 
-## Provisioning using SoftAP
+## Example Output
 
+### Provisioning using SoftAP
 ```
 [I][WiFiProv.cpp:117] beginProvision(): Starting AP using SOFTAP
- service_name : PROV_XXX
- password : 123456789
- pop : abcd1234
+ service_name: PROV_XXX
+ password: 123456789
+ pop: abcd1234
 
 Provisioning started
-Give Credentials of your access point using " Android app "
+Give Credentials of your access point using "Android app"
 
 Received Wi-Fi credentials
-	SSID : GIONEE M2
-	Password : 123456789
+    SSID: GIONEE M2
+    Password: 123456789
 
-Connected IP address : 192.168.43.120
+Connected IP address: 192.168.43.120
 Provisioning Successful
 Provisioning Ends
-
 ```
 
-## Provisioning using BLE
-
+### Provisioning using BLE
 ```
 [I][WiFiProv.cpp:115] beginProvision(): Starting AP using BLE
- service_name : PROV_XXX
- pop : abcd1234
+ service_name: PROV_XXX
+ pop: abcd1234
 
 Provisioning started
-Give Credentials of your access point using " Android app "
+Give Credentials of your access point using "Android app"
 
 Received Wi-Fi credentials
-	SSID : GIONEE M2
-	Password : 123456789
+    SSID: GIONEE M2
+    Password: 123456789
 
-Connected IP address : 192.168.43.120
+Connected IP address: 192.168.43.120
 Provisioning Successful
 Provisioning Ends
-
 ```
 
-## Credentials are available on device
-
+### Credentials are available on the device
 ```
-[I][WiFiProv.cpp:146] beginProvision(): Aleardy Provisioned, starting Wi-Fi STA
-[I][WiFiProv.cpp:150] beginProvision(): SSID : Wce*****
-[I][WiFiProv.cpp:152] beginProvision(): CONNECTING TO THE ACCESS POINT : 
-Connected IP address : 192.168.43.120
+[I][WiFiProv.cpp:146] beginProvision(): Already Provisioned, starting Wi-Fi STA
+[I][WiFiProv.cpp:150] beginProvision(): SSID: Wce*****
+[I][WiFiProv.cpp:152] beginProvision(): CONNECTING TO THE ACCESS POINT:
+Connected IP address: 192.168.43.120
 ```
diff --git a/libraries/WiFiProv/examples/WiFiProv/WiFiProv.ino b/libraries/WiFiProv/examples/WiFiProv/WiFiProv.ino
index 48ffe1e7712..76025d75770 100644
--- a/libraries/WiFiProv/examples/WiFiProv/WiFiProv.ino
+++ b/libraries/WiFiProv/examples/WiFiProv/WiFiProv.ino
@@ -1,64 +1,82 @@
+/*
+Please read README.md file in this folder, or on the web:
+https://github.com/espressif/arduino-esp32/tree/master/libraries/WiFiProv/examples/WiFiProv
+
+Note: This sketch takes up a lot of space for the app and may not be able to flash with default setting on some chips.
+  If you see Error like this: "Sketch too big"
+  In Arduino IDE go to: Tools > Partition scheme > chose anything that has more than 1.4MB APP
+   - for example "No OTA (2MB APP/2MB SPIFFS)"
+*/
+
+#include "sdkconfig.h"
+#if CONFIG_ESP_WIFI_REMOTE_ENABLED
+#error "WiFiProv is only supported in SoCs with native Wi-Fi support"
+#endif
+
 #include "WiFiProv.h"
-void SysProvEvent(system_event_t *sys_event,wifi_prov_event_t *prov_event)
-{
-    if(sys_event) {
-      switch (sys_event->event_id) {
-      case SYSTEM_EVENT_STA_GOT_IP:
-          Serial.print("\nConnected IP address : ");
-          Serial.println(ip4addr_ntoa(&sys_event->event_info.got_ip.ip_info.ip));
-          break;
-      case SYSTEM_EVENT_STA_DISCONNECTED:
-          Serial.println("\nDisconnected. Connecting to the AP again... ");
-          break;
-      default:
-          break;
-      }      
-    }
+#include "WiFi.h"
 
-    if(prov_event) {
-        switch (prov_event->event) {
-        case WIFI_PROV_START:
-            Serial.println("\nProvisioning started\nGive Credentials of your access point using \" Android app \"");
-            break;
-        case WIFI_PROV_CRED_RECV: { 
-            Serial.println("\nReceived Wi-Fi credentials");
-            wifi_sta_config_t *wifi_sta_cfg = (wifi_sta_config_t *)prov_event->event_data;
-            Serial.print("\tSSID : ");
-            Serial.println((const char *) wifi_sta_cfg->ssid);
-            Serial.print("\tPassword : ");
-            Serial.println((char const *) wifi_sta_cfg->password);
-            break;
-        }
-        case WIFI_PROV_CRED_FAIL: { 
-            wifi_prov_sta_fail_reason_t *reason = (wifi_prov_sta_fail_reason_t *)prov_event->event_data;
-            Serial.println("\nProvisioning failed!\nPlease reset to factory and retry provisioning\n");
-            if(*reason == WIFI_PROV_STA_AUTH_ERROR) 
-                Serial.println("\nWi-Fi AP password incorrect");
-            else
-                Serial.println("\nWi-Fi AP not found....Add API \" nvs_flash_erase() \" before beginProvision()");        
-            break;
-        }
-        case WIFI_PROV_CRED_SUCCESS:
-            Serial.println("\nProvisioning Successful");
-            break;
-        case WIFI_PROV_END:
-            Serial.println("\nProvisioning Ends");
-            break;
-        default:
-            break;
-        }      
+// #define USE_SOFT_AP // Uncomment if you want to enforce using the Soft AP method instead of BLE
+const char *pop = "abcd1234";           // Proof of possession - otherwise called a PIN - string provided by the device, entered by the user in the phone app
+const char *service_name = "PROV_123";  // Name of your device (the Espressif apps expects by default device name starting with "Prov_")
+const char *service_key = NULL;         // Password used for SofAP method (NULL = no password needed)
+bool reset_provisioned = true;          // When true the library will automatically delete previously provisioned data.
+
+// WARNING: SysProvEvent is called from a separate FreeRTOS task (thread)!
+void SysProvEvent(arduino_event_t *sys_event) {
+  switch (sys_event->event_id) {
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP:
+      Serial.print("\nConnected IP address : ");
+      Serial.println(IPAddress(sys_event->event_info.got_ip.ip_info.ip.addr));
+      break;
+    case ARDUINO_EVENT_WIFI_STA_DISCONNECTED: Serial.println("\nDisconnected. Connecting to the AP again... "); break;
+    case ARDUINO_EVENT_PROV_START:            Serial.println("\nProvisioning started\nGive Credentials of your access point using smartphone app"); break;
+    case ARDUINO_EVENT_PROV_CRED_RECV:
+    {
+      Serial.println("\nReceived Wi-Fi credentials");
+      Serial.print("\tSSID : ");
+      Serial.println((const char *)sys_event->event_info.prov_cred_recv.ssid);
+      Serial.print("\tPassword : ");
+      Serial.println((char const *)sys_event->event_info.prov_cred_recv.password);
+      break;
+    }
+    case ARDUINO_EVENT_PROV_CRED_FAIL:
+    {
+      Serial.println("\nProvisioning failed!\nPlease reset to factory and retry provisioning\n");
+      if (sys_event->event_info.prov_fail_reason == NETWORK_PROV_WIFI_STA_AUTH_ERROR) {
+        Serial.println("\nWi-Fi AP password incorrect");
+      } else {
+        Serial.println("\nWi-Fi AP not found....Add API \" nvs_flash_erase() \" before beginProvision()");
+      }
+      break;
     }
+    case ARDUINO_EVENT_PROV_CRED_SUCCESS: Serial.println("\nProvisioning Successful"); break;
+    case ARDUINO_EVENT_PROV_END:          Serial.println("\nProvisioning Ends"); break;
+    default:                              break;
+  }
 }
 
 void setup() {
   Serial.begin(115200);
-  //Sample uuid that user can pass during provisioning using BLE
-  /* uint8_t uuid[16] = {0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf,
-                   0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02 };*/
+  WiFi.begin();  // no SSID/PWD - get it from the Provisioning APP or from NVS (last successful connection)
   WiFi.onEvent(SysProvEvent);
-  //WiFiProv.beginProvision(provSchemeBLE, WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BTDM, WIFI_PROV_SECURITY_1, "abcd1234", "PROV_XXX", NULL, NULL);
-  WiFiProv.beginProvision(provSchemeSoftAP, WIFI_PROV_EVENT_HANDLER_NONE, WIFI_PROV_SECURITY_1, "abcd1234", NULL, NULL, NULL);
-}
 
-void loop() {
+// BLE Provisioning using the ESP SoftAP Prov works fine for any BLE SoC, including ESP32, ESP32S3 and ESP32C3.
+#if CONFIG_BLUEDROID_ENABLED && !defined(USE_SOFT_AP)
+  Serial.println("Begin Provisioning using BLE");
+  // Sample uuid that user can pass during provisioning using BLE
+  uint8_t uuid[16] = {0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf, 0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02};
+  WiFiProv.beginProvision(
+    NETWORK_PROV_SCHEME_BLE, NETWORK_PROV_SCHEME_HANDLER_FREE_BLE, NETWORK_PROV_SECURITY_1, pop, service_name, service_key, uuid, reset_provisioned
+  );
+  log_d("ble qr");
+  WiFiProv.printQR(service_name, pop, "ble");
+#else
+  Serial.println("Begin Provisioning using Soft AP");
+  WiFiProv.beginProvision(NETWORK_PROV_SCHEME_SOFTAP, NETWORK_PROV_SCHEME_HANDLER_NONE, NETWORK_PROV_SECURITY_1, pop, service_name, service_key);
+  log_d("wifi qr");
+  WiFiProv.printQR(service_name, pop, "softap");
+#endif
 }
+
+void loop() {}
diff --git a/libraries/WiFiProv/examples/WiFiProv/ci.json b/libraries/WiFiProv/examples/WiFiProv/ci.json
new file mode 100644
index 00000000000..04eb62b977a
--- /dev/null
+++ b/libraries/WiFiProv/examples/WiFiProv/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=huge_app",
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/WiFiProv/library.properties b/libraries/WiFiProv/library.properties
index 8383d2ff0f9..13a63c50bb1 100644
--- a/libraries/WiFiProv/library.properties
+++ b/libraries/WiFiProv/library.properties
@@ -1,9 +1,8 @@
 name=WiFiProv
-version=1.0
+version=3.2.0
 author=Switi Mhaiske <sweetymhaiske@gmail.com>
 maintainer=Hristo Gochkov <hristo@espressif.com>
 sentence=Enables provisioning.
 paragraph=With this library you can perform provisioning on esp32 via SoftAP or BLE.
-category=
 url=
 architectures=esp32
diff --git a/libraries/WiFiProv/src/WiFiProv.cpp b/libraries/WiFiProv/src/WiFiProv.cpp
index db6f86f8802..31337196b5f 100644
--- a/libraries/WiFiProv/src/WiFiProv.cpp
+++ b/libraries/WiFiProv/src/WiFiProv.cpp
@@ -1,22 +1,25 @@
 /*
     WiFiProv.cpp - WiFiProv class for provisioning
     All rights reserved.
- 
+
     This library is free software; you can redistribute it and/or
     modify it under the terms of the GNU Lesser General Public
     License as published by the Free Software Foundation; either
     version 2.1 of the License, or (at your option) any later version.
-  
+
     This library is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     Lesser General Public License for more details.
-  
+
     You should have received a copy of the GNU Lesser General Public
     License along with this library; if not, write to the Free Software
     Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
-    
+
 */
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_WIFI_SUPPORTED && CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI
 
 #include <stdio.h>
 #include <stdint.h>
@@ -24,136 +27,259 @@
 #include <string.h>
 #include <esp_err.h>
 #include <esp_wifi.h>
-#include <esp_event_loop.h>
+#include <esp_event.h>
 #include <esp32-hal.h>
+#if __has_include("qrcode.h")
+#include "qrcode.h"
+#endif
 
-#include <wifi_provisioning/scheme_ble.h>
-#include <wifi_provisioning/scheme_softap.h>
-#include <wifi_provisioning/manager.h>
+#include <nvs_flash.h>
+#if CONFIG_BLUEDROID_ENABLED
+#include "network_provisioning/scheme_ble.h"
+#endif
+#include <network_provisioning/scheme_softap.h>
+#include <network_provisioning/manager.h>
 #undef IPADDR_NONE
 #include "WiFiProv.h"
+#if CONFIG_IDF_TARGET_ESP32
 #include "SimpleBLE.h"
+#endif
 
-extern esp_err_t postToSysQueue(system_prov_event_t *);
+bool wifiLowLevelInit(bool persistent);
 
-static wifi_prov_mgr_config_t config;
-static scheme_t prov_scheme;
-static const uint8_t custom_service_uuid[16] = {  0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf,
-                                                  0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02, };
+#if CONFIG_BLUEDROID_ENABLED
+static const uint8_t custom_service_uuid[16] = {
+  0xb4, 0xdf, 0x5a, 0x1c, 0x3f, 0x6b, 0xf4, 0xbf, 0xea, 0x4a, 0x82, 0x03, 0x04, 0x90, 0x1a, 0x02,
+};
+#endif
 
 #define SERV_NAME_PREFIX_PROV "PROV_"
 
-void provSchemeBLE()
-{
-    prov_scheme = WIFI_PROV_SCHEME_BLE;
-    config.scheme = wifi_prov_scheme_ble;    
+static void get_device_service_name(prov_scheme_t prov_scheme, char *service_name, size_t max) {
+  uint8_t eth_mac[6] = {0, 0, 0, 0, 0, 0};
+  if (esp_wifi_get_mac((wifi_interface_t)WIFI_IF_STA, eth_mac) != ESP_OK) {
+    log_e("esp_wifi_get_mac failed!");
+    return;
+  }
+#if CONFIG_IDF_TARGET_ESP32 && defined(CONFIG_BLUEDROID_ENABLED)
+  if (prov_scheme == NETWORK_PROV_SCHEME_BLE) {
+    snprintf(service_name, max, "%s%02X%02X%02X", SERV_NAME_PREFIX_PROV, eth_mac[3], eth_mac[4], eth_mac[5]);
+  } else {
+#endif
+    snprintf(service_name, max, "%s%02X%02X%02X", SERV_NAME_PREFIX_PROV, eth_mac[3], eth_mac[4], eth_mac[5]);
+#if CONFIG_IDF_TARGET_ESP32 && defined(CONFIG_BLUEDROID_ENABLED)
+  }
+#endif
 }
 
-void provSchemeSoftAP()
-{
-    prov_scheme = WIFI_PROV_SCHEME_SOFTAP;
-    config.scheme = wifi_prov_scheme_softap;
-}
+void WiFiProvClass ::initProvision(prov_scheme_t prov_scheme, scheme_handler_t scheme_handler, bool reset_provisioned) {
+  if (this->provInitDone) {
+    log_i("provInit was already done!");
+    return;
+  }
+  network_prov_mgr_config_t config;
+#if CONFIG_BLUEDROID_ENABLED
+  if (prov_scheme == NETWORK_PROV_SCHEME_BLE) {
+    config.scheme = network_prov_scheme_ble;
+  } else {
+#endif
+    config.scheme = network_prov_scheme_softap;
+#if CONFIG_BLUEDROID_ENABLED
+  }
 
-static void prov_event_handler(void *user_data, wifi_prov_cb_event_t event, void *event_data)
-{
-    if (!event) {
-         return;
-     }
-
-     system_prov_event_t *sys_prov = (system_prov_event_t *)malloc(sizeof(system_prov_event_t));
-     if(sys_prov == NULL) {
-         log_e("Malloc Failed");
-         return;
-     }
-
-     sys_prov->prov_event = (wifi_prov_event_t *)malloc(sizeof(wifi_prov_event_t));
-     if(sys_prov->prov_event == NULL) {
-         log_e("Malloc Failed");
-         free(sys_prov);
-         return;
-     }
-
-     sys_prov->sys_event = (system_event_t *)malloc(sizeof(system_event_t));
-     if(sys_prov->sys_event == NULL) {
-         log_e("Malloc Failed");
-         free(sys_prov->prov_event);
-         free(sys_prov);
-         return;
-     }
-
-     sys_prov->prov_event->event = event;
-     sys_prov->prov_event->event_data = event_data;
-     sys_prov->sys_event->event_id = SYSTEM_EVENT_MAX;
-     esp_err_t check = postToSysQueue(sys_prov);
-     if(check == ESP_FAIL) {
-         log_e("Provisioning event not send to queue");
-         free(sys_prov->sys_event);
-         free(sys_prov->prov_event);
-         free(sys_prov);
-     }
+  if (scheme_handler == NETWORK_PROV_SCHEME_HANDLER_NONE) {
+#endif
+    network_prov_event_handler_t scheme_event_handler = NETWORK_PROV_EVENT_HANDLER_NONE;
+    memcpy(&config.scheme_event_handler, &scheme_event_handler, sizeof(network_prov_event_handler_t));
+#if CONFIG_BLUEDROID_ENABLED
+  } else if (scheme_handler == NETWORK_PROV_SCHEME_HANDLER_FREE_BTDM) {
+    network_prov_event_handler_t scheme_event_handler = NETWORK_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BTDM;
+    memcpy(&config.scheme_event_handler, &scheme_event_handler, sizeof(network_prov_event_handler_t));
+  } else if (scheme_handler == NETWORK_PROV_SCHEME_HANDLER_FREE_BT) {
+    network_prov_event_handler_t scheme_event_handler = NETWORK_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BT;
+    memcpy(&config.scheme_event_handler, &scheme_event_handler, sizeof(network_prov_event_handler_t));
+  } else if (scheme_handler == NETWORK_PROV_SCHEME_HANDLER_FREE_BLE) {
+    network_prov_event_handler_t scheme_event_handler = NETWORK_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BLE;
+    memcpy(&config.scheme_event_handler, &scheme_event_handler, sizeof(network_prov_event_handler_t));
+  } else {
+    log_e("Unknown scheme handler!");
+    return;
+  }
+#endif
+  config.app_event_handler.event_cb = NULL;
+  config.app_event_handler.user_data = NULL;
+  WiFi.STA.begin(false);
+  if (network_prov_mgr_init(config) != ESP_OK) {
+    log_e("network_prov_mgr_init failed!");
+    return;
+  }
+  if (reset_provisioned) {
+    log_i("Resetting provisioned data.");
+    network_prov_mgr_reset_wifi_provisioning();
+  } else if (network_prov_mgr_is_wifi_provisioned(&(this->provisioned)) != ESP_OK) {
+    log_e("network_prov_mgr_is_wifi_provisioned failed!");
+    network_prov_mgr_deinit();
+    return;
+  }
+  this->provInitDone = true;
 }
 
-static void get_device_service_name(char *service_name, size_t max)
-{
-    uint8_t eth_mac[6];
-    WiFi.macAddress(eth_mac);
-    snprintf(service_name, max, "%s%02X%02X%02X",SERV_NAME_PREFIX_PROV, eth_mac[3], eth_mac[4], eth_mac[5]);
-}
+void WiFiProvClass ::beginProvision(
+  prov_scheme_t prov_scheme, scheme_handler_t scheme_handler, network_prov_security_t security, const char *pop, const char *service_name,
+  const char *service_key, uint8_t *uuid, bool reset_provisioned
+) {
+  if (!this->provInitDone) {
+    WiFiProvClass ::initProvision(prov_scheme, scheme_handler, reset_provisioned);
+  }
+  static char service_name_temp[32];
+  if (provisioned == false) {
+#if CONFIG_BLUEDROID_ENABLED
+    if (prov_scheme == NETWORK_PROV_SCHEME_BLE) {
+      service_key = NULL;
+      if (uuid == NULL) {
+        uuid = (uint8_t *)custom_service_uuid;
+      }
+      network_prov_scheme_ble_set_service_uuid(uuid);
+    }
+#endif
 
-void WiFiProvClass :: beginProvision(void (*scheme_cb)(), wifi_prov_event_handler_t scheme_event_handler, wifi_prov_security_t security, const char * pop, const char *service_name, const char *service_key, uint8_t * uuid)
-{
-    WiFi.enableProv(true);
-    bool provisioned = false;
-    scheme_cb();
-    config.scheme_event_handler = scheme_event_handler;
-    config.app_event_handler = {
-            .event_cb = prov_event_handler,
-            .user_data = NULL
-            };
- 
-    wifi_prov_mgr_init(config);
-    WiFi.mode(WIFI_MODE_AP);
-    wifi_prov_mgr_is_provisioned(&provisioned);
-    if(provisioned == false) {
-        if(prov_scheme == WIFI_PROV_SCHEME_BLE) {
-            service_key = NULL;
-            if(uuid == NULL) {
-                uuid=(uint8_t *)custom_service_uuid;
-            }
-            wifi_prov_scheme_ble_set_service_uuid(uuid);
-        }
-
-        if(service_name == NULL) {
-            char service_name_temp[12];
-            get_device_service_name(service_name_temp,sizeof(service_name_temp));
-            service_name = (const char *)service_name_temp;
-        }
-
-        if(prov_scheme == WIFI_PROV_SCHEME_BLE) {
-            log_i("Starting AP using BLE\n service_name : %s\n pop : %s",service_name,pop);
-
-        } else {
-            if(service_key == NULL) {
-               log_i("Starting AP using SOFTAP\n service_name : %s\n pop : %s",service_name,pop); 
-            } else { 
-               log_i("Starting AP using SOFTAP\n service_name : %s\n password : %s\n pop : %s",service_name,service_key,pop); 
-            }
-        }
-           
-        wifi_prov_mgr_start_provisioning(security,pop,service_name,service_key);
+    if (service_name == NULL) {
+      get_device_service_name(prov_scheme, service_name_temp, 32);
+      service_name = (const char *)service_name_temp;
+    }
 
+#if CONFIG_BLUEDROID_ENABLED
+    if (prov_scheme == NETWORK_PROV_SCHEME_BLE) {
+      log_i("Starting AP using BLE. service_name : %s, pop : %s", service_name, pop);
     } else {
-        wifi_prov_mgr_deinit();
-        WiFi.mode(WIFI_MODE_STA);
-        log_i("Already Provisioned, starting Wi-Fi STA");
+#endif
+      if (service_key == NULL) {
+        log_i("Starting provisioning AP using SOFTAP. service_name : %s, pop : %s", service_name, pop);
+      } else {
+        log_i("Starting provisioning AP using SOFTAP. service_name : %s, password : %s, pop : %s", service_name, service_key, pop);
+      }
+#if CONFIG_BLUEDROID_ENABLED
+    }
+#endif
+    if (network_prov_mgr_start_provisioning(security, pop, service_name, service_key) != ESP_OK) {
+      log_e("network_prov_mgr_start_provisioning failed!");
+      return;
+    }
+  } else {
+    log_i("Already Provisioned");
 #if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
-        wifi_config_t conf;
-        esp_wifi_get_config(WIFI_IF_STA,&conf);
-        log_i("SSID : %s\n",conf.sta.ssid);
+    static wifi_config_t conf;
+    esp_wifi_get_config((wifi_interface_t)WIFI_IF_STA, &conf);
+    log_i("Attempting connect to AP: %s\n", conf.sta.ssid);
 #endif
-        log_i("CONNECTING TO THE ACCESS POINT : ");
-        WiFi.begin(); 
+    esp_wifi_start();
+    network_prov_mgr_deinit();
+    WiFi.begin();
+  }
+}
+
+void WiFiProvClass::endProvision() {
+  network_prov_mgr_stop_provisioning();
+}
+
+bool WiFiProvClass::disableAutoStop(uint32_t cleanup_delay) {
+  esp_err_t err = network_prov_mgr_disable_auto_stop(cleanup_delay);
+  if (err != ESP_OK) {
+    log_e("disable_auto_stop failed!");
+  }
+  return err == ESP_OK;
+}
+
+// Copied from IDF example
+
+#if __has_include("qrcode.h")
+static const char *lt[] = {
+  /* 0 */ "  ",
+  /* 1 */ "\u2580 ",
+  /* 2 */ " \u2580",
+  /* 3 */ "\u2580\u2580",
+  /* 4 */ "\u2584 ",
+  /* 5 */ "\u2588 ",
+  /* 6 */ "\u2584\u2580",
+  /* 7 */ "\u2588\u2580",
+  /* 8 */ " \u2584",
+  /* 9 */ "\u2580\u2584",
+  /* 10 */ " \u2588",
+  /* 11 */ "\u2580\u2588",
+  /* 12 */ "\u2584\u2584",
+  /* 13 */ "\u2588\u2584",
+  /* 14 */ "\u2584\u2588",
+  /* 15 */ "\u2588\u2588",
+};
+
+static Print *qr_out = NULL;
+
+static void _qrcode_print_console(esp_qrcode_handle_t qrcode) {
+  int size = esp_qrcode_get_size(qrcode);
+  int border = 2;
+  unsigned char num = 0;
+
+  if (qr_out == NULL) {
+    return;
+  }
+
+  for (int y = -border; y < size + border; y += 2) {
+    for (int x = -border; x < size + border; x += 2) {
+      num = 0;
+      if (esp_qrcode_get_module(qrcode, x, y)) {
+        num |= 1 << 0;
+      }
+      if ((x < size + border) && esp_qrcode_get_module(qrcode, x + 1, y)) {
+        num |= 1 << 1;
+      }
+      if ((y < size + border) && esp_qrcode_get_module(qrcode, x, y + 1)) {
+        num |= 1 << 2;
+      }
+      if ((x < size + border) && (y < size + border) && esp_qrcode_get_module(qrcode, x + 1, y + 1)) {
+        num |= 1 << 3;
+      }
+      qr_out->print(lt[num]);
     }
+    qr_out->print("\n");
+  }
+  qr_out->print("\n");
 }
+#endif
+
+void WiFiProvClass::printQR(const char *name, const char *pop, const char *transport, Print &out) {
+  if (!name || !transport) {
+    log_w("Cannot generate QR code payload. Data missing.");
+    return;
+  }
+  char payload[150] = {0};
+  if (pop) {
+    snprintf(
+      payload, sizeof(payload),
+      "{\"ver\":\"%s\",\"name\":\"%s\""
+      ",\"pop\":\"%s\",\"transport\":\"%s\"}",
+      "v1", name, pop, transport
+    );
+  } else {
+    snprintf(
+      payload, sizeof(payload),
+      "{\"ver\":\"%s\",\"name\":\"%s\""
+      ",\"transport\":\"%s\"}",
+      "v1", name, transport
+    );
+  }
+#if __has_include("qrcode.h")
+  esp_qrcode_config_t cfg = ESP_QRCODE_CONFIG_DEFAULT();
+  cfg.display_func = _qrcode_print_console;
+  out.printf("Scan this QR code from the provisioning application for Provisioning.\n");
+  qr_out = &out;
+  esp_qrcode_generate(&cfg, payload);
+  qr_out = NULL;
+  out.printf("If QR code is not visible, copy paste the below URL in a browser.\nhttps://rainmaker.espressif.com/qrcode.html?data=%s\n", payload);
+#else
+  out.println("If you are using Arduino as IDF component, install ESP Rainmaker:\nhttps://github.com/espressif/esp-rainmaker");
+#endif
+}
+
 WiFiProvClass WiFiProv;
+
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/WiFiProv/src/WiFiProv.h b/libraries/WiFiProv/src/WiFiProv.h
index 89b6315ed67..b660f8cf064 100644
--- a/libraries/WiFiProv/src/WiFiProv.h
+++ b/libraries/WiFiProv/src/WiFiProv.h
@@ -1,48 +1,70 @@
 /*
     WiFiProv.h - Base class for provisioning support
     All right reserved.
- 
+
     This library is free software; you can redistribute it and/or
     modify it under the terms of the GNU Lesser General Public
     License as published by the Free Software Foundation; either
     version 2.1 of the License, or (at your option) any later version.
-  
+
     This library is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     Lesser General Public License for more details.
-  
+
     You should have received a copy of the GNU Lesser General Public
     License along with this library; if not, write to the Free Software
     Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if SOC_WIFI_SUPPORTED && CONFIG_NETWORK_PROV_NETWORK_TYPE_WIFI
+
 #include "WiFi.h"
-#include "wifi_provisioning/manager.h"
-#include "wifi_provisioning/scheme_ble.h"
+#include "HardwareSerial.h"
+#include "network_provisioning/manager.h"
 //Select the scheme using which you want to provision
-typedef enum 
-{
-    WIFI_PROV_SCHEME_BLE,
-    WIFI_PROV_SCHEME_SOFTAP
-}scheme_t;
+typedef enum {
+  NETWORK_PROV_SCHEME_SOFTAP,
+#if CONFIG_BLUEDROID_ENABLED
+  NETWORK_PROV_SCHEME_BLE,
+#endif
+  NETWORK_PROV_SCHEME_MAX
+} prov_scheme_t;
 
-extern void provSchemeSoftAP();
-extern void provSchemeBLE();
+typedef enum {
+  NETWORK_PROV_SCHEME_HANDLER_NONE,
+#if CONFIG_BLUEDROID_ENABLED
+  NETWORK_PROV_SCHEME_HANDLER_FREE_BTDM,
+  NETWORK_PROV_SCHEME_HANDLER_FREE_BLE,
+  NETWORK_PROV_SCHEME_HANDLER_FREE_BT,
+#endif
+  NETWORK_PROV_SCHEME_HANDLER_MAX
+} scheme_handler_t;
 
-//Provisioning class 
-class WiFiProvClass
-{
-    public:
+//Provisioning class
+class WiFiProvClass {
+private:
+  bool provInitDone = false;
+  bool provisioned = false;
 
-    void beginProvision(void (*scheme_cb)() = provSchemeSoftAP, wifi_prov_event_handler_t scheme_event_handler = WIFI_PROV_EVENT_HANDLER_NONE, wifi_prov_security_t security = WIFI_PROV_SECURITY_1, const char * pop = "abcd1234", const char * service_name = NULL, const char * service_key = NULL, uint8_t *uuid = NULL);
+public:
+  void initProvision(
+    prov_scheme_t prov_scheme = NETWORK_PROV_SCHEME_SOFTAP, scheme_handler_t scheme_handler = NETWORK_PROV_SCHEME_HANDLER_NONE, bool reset_provisioned = false
+  );
+  void beginProvision(
+    prov_scheme_t prov_scheme = NETWORK_PROV_SCHEME_SOFTAP, scheme_handler_t scheme_handler = NETWORK_PROV_SCHEME_HANDLER_NONE,
+    network_prov_security_t security = NETWORK_PROV_SECURITY_1, const char *pop = "abcd1234", const char *service_name = NULL, const char *service_key = NULL,
+    uint8_t *uuid = NULL, bool reset_provisioned = false
+  );
+  void endProvision();
+  bool disableAutoStop(uint32_t cleanup_delay);
+  void printQR(const char *name, const char *pop, const char *transport, Print &out = Serial);
 };
+
 extern WiFiProvClass WiFiProv;
-/*
- Event Handler for BLE
-      - WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BTDM
-      - WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BLE
-      - WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BT
-Event Handler for SOFTAP
-      - WIFI_PROV_EVENT_HANDLER_NONE
-*/
+
+#endif /* SOC_WIFI_SUPPORTED */
diff --git a/libraries/Wire/doc/i2c_debugging.md b/libraries/Wire/doc/i2c_debugging.md
deleted file mode 100644
index 35c6e2e7f17..00000000000
--- a/libraries/Wire/doc/i2c_debugging.md
+++ /dev/null
@@ -1,276 +0,0 @@
-# Debugging I2C
-
-With the release of Arduino-ESP32 V1.0.1 the I2C subsystem contains code to exhaustively report communication errors.  
-* Basic debugging can be enable by setting the *CORE DEBUG LEVEL* at or above *ERROR*. All errors will be directed the the *DEBUG OUTPUT* normally connected to `Serial()`.  
-* Enhanced debugging can be used to generate specified information at specific positions during the i2c communication sequence. Increase *CORE DEBUG LEVEL* to ***DEBUG***
-
-## Enable Debug Buffer
-The Enhanced debug features are enabled by uncommenting the `\\#define ENABLE_I2C_DEBUG_BUFFER` at line 45 of `esp32-hal-i2c.c`.  
-* When Arduino-Esp32 is installed in Windows with Arduino Boards Manager, `esp32-hal-i2c.c` can be found in:
-`C:\Users\{user}\AppData\Local\Arduino15\packages\esp32\hardware\esp32\1.0.1\cores\esp32\`
-* When Arduino-Esp32 Development version is installed from GitHub, `esp32-hal-i2c.c` can be found in:
-`{arduino Sketch}\hardware\espressif\esp32\cores\esp32\`
-
-
-```c++ 
-//#define ENABLE_I2C_DEBUG_BUFFER
-```
-Change it to:
-```c++ 
-#define ENABLE_I2C_DEBUG_BUFFER
-```
-and recompile/upload the resulting code to your ESP32.
-
-Enabling this `#define` will consume an additional 2570 bytes of RAM and include a commensurate amount of code FLASH. If you see the message `"Debug Buffer not Enabled"` in your console log I would suggest you un-comment the line and regenerate the error.  Additional information will be supplied on the log console.
-
-## Manually controlled Debugging
-Manual logging of the i2c control data buffers can be accomplished by using the debug control function of `Wire()`:
-```c++
-    uint32_t setDebugFlags( uint32_t setBits, uint32_t resetBits);
-```
-`setBits`, and `resetBits` manually cause output of the control structures to the log console.   They are bit fields that enable/disable the reporting of individual control structures during specific phases of the i2c communications sequence.  The 32bit values are divided into four 8bit fields.  Currently only five bits are defined. ***If an error is detected during normal operations, the relevant control structure will bit added to the log irrespective of the current debug flags.***
-
-* **bit 0** causes DumpI2c to execute 
-header information about current communications event,
-and the dataQueue elements showing the logical i2c transaction commands
-* **bit 1** causes DumpInts to execute
-Actual sequence of interrupts handled during last communications event, cleared on entry into `ProcQueue()`.
-* **bit 2** causes DumpCmdqueue to execute
-The last block of commands to the i2c peripheral.
-* **bit 3** causes DumpStatus to execute
-A descriptive display of the 32bit i2c peripheral status word.
-* **bit 4** causes DumpFifo to execute
-A buffer listing the sequence of data added to the txFifo of the i2c peripheral.
-
-Of the four division, only three are currently implemented:
-* 0xXX - - - - - - : at entry of ProcQueue (`bitFlags << 24`)
-* 0x - - XX - - - - : at exit of ProcQueue (`bitFlags << 16`)
-* 0x - - - - - - XX : at entry of Flush    (`bitFlags`)
- 
-For example, to display the sequence of Interrupts processed during the i2c communication transaction, **bit 1** would be set, and, since this information on Interrupt usage would only be valid after the communications have completed, the locus would be *at exit of ProcQueue*.  The following code would be necessary.
-### code
-```c++
-uint8_t flag = 1 << 1; // turn on bit 1
-uint32_t debugFlag = flag << 16; // correctly position the 8bits of flag as the second byte of setBits.
-Wire.setDebugFlags(debugFlag,0);// resetBits=0 says leave all current setBits as is.
-
-Wire.requestFrom(id,byteCount); // read byteCount bytes from slave at id 
-
-Wire.setDebugFlags(0,debugFlag); // don't add any new debug, remove debugFlag
-``` 
-### output of log console
-```
-[I][esp32-hal-i2c.c:437] i2cTriggerDumps(): after ProcQueue
-[I][esp32-hal-i2c.c:346] i2cDumpInts(): 0 row	count	INTR	TX	RX	Tick 
-[I][esp32-hal-i2c.c:350] i2cDumpInts(): [01]	0x0001	0x0002	0x0003	0x0000	0x005baac5
-[I][esp32-hal-i2c.c:350] i2cDumpInts(): [02]	0x0001	0x0200	0x0000	0x0000	0x005baac5
-[I][esp32-hal-i2c.c:350] i2cDumpInts(): [03]	0x0001	0x0080	0x0000	0x0008	0x005baac6
-```    
-# Debug Log example
-### Code
-To read eight bytes of data from a DS1307 RTCC
-```
-    uint32_t debugFlag = 0x001F0000;
-    uint8_t ID = 0x68;
-    uint8_t block=8;
-    
-    if(debugFlag >0){
-        Wire.setDebugFlags(debugFlag,0);
-    }
-
-    Wire.beginTransmission(ID);
-    Wire.write(lowByte(addr));
-    if((err=Wire.endTransmission(false))!=0)    {
-        Serial.printf(" EndTransmission=%d(%s)",Wire.lastError(),Wire.getErrorText(Wire.lastError()));
-
-        if(err!=2) {
-            Serial.printf(", resetting\n");
-            if( !Wire.begin()) Serial.printf(" Reset Failed\n");
-            if(debugFlag >0) Wire.setDebugFlags(0,debugFlag);
-            return;
-        } else {
-            Serial.printf(", No Device present, aborting\n");
-            currentCommand= NO_COMMAND;
-            return;
-        }
-    }
-    err = Wire.requestFrom(ID,block,true);
-    if(debugFlag >0){
-        Wire.setDebugFlags(0,debugFlag);
-    }
-```
-### output of log console
-```
-[I][esp32-hal-i2c.c:437] i2cTriggerDumps(): after ProcQueue
-[E][esp32-hal-i2c.c:318] i2cDumpI2c(): i2c=0x3ffbdc78
-[I][esp32-hal-i2c.c:319] i2cDumpI2c(): dev=0x60013000 date=0x16042000
-[I][esp32-hal-i2c.c:321] i2cDumpI2c(): lock=0x3ffb843c
-[I][esp32-hal-i2c.c:323] i2cDumpI2c(): num=0
-[I][esp32-hal-i2c.c:324] i2cDumpI2c(): mode=1
-[I][esp32-hal-i2c.c:325] i2cDumpI2c(): stage=3
-[I][esp32-hal-i2c.c:326] i2cDumpI2c(): error=1
-[I][esp32-hal-i2c.c:327] i2cDumpI2c(): event=0x3ffb85c4 bits=10
-[I][esp32-hal-i2c.c:328] i2cDumpI2c(): intr_handle=0x3ffb85f4
-[I][esp32-hal-i2c.c:329] i2cDumpI2c(): dq=0x3ffb858c
-[I][esp32-hal-i2c.c:330] i2cDumpI2c(): queueCount=2
-[I][esp32-hal-i2c.c:331] i2cDumpI2c(): queuePos=1
-[I][esp32-hal-i2c.c:332] i2cDumpI2c(): errorByteCnt=0
-[I][esp32-hal-i2c.c:333] i2cDumpI2c(): errorQueue=0
-[I][esp32-hal-i2c.c:334] i2cDumpI2c(): debugFlags=0x001F0000
-[I][esp32-hal-i2c.c:288] i2cDumpDqData(): [0] 7bit 68 W  buf@=0x3ffc04b2, len=1, pos=1, ctrl=11101
-[I][esp32-hal-i2c.c:306] i2cDumpDqData(): 0x0000: .                                00 
-[I][esp32-hal-i2c.c:288] i2cDumpDqData(): [1] 7bit 68 R STOP buf@=0x3ffc042c, len=8, pos=8, ctrl=11111
-[I][esp32-hal-i2c.c:306] i2cDumpDqData(): 0x0000: 5P......                         35 50 07 06 13 09 18 00 
-[I][esp32-hal-i2c.c:346] i2cDumpInts(): 0 row	count	INTR	TX	RX	Tick 
-[I][esp32-hal-i2c.c:350] i2cDumpInts(): [01]	0x0001	0x0002	0x0003	0x0000	0x000073d5
-[I][esp32-hal-i2c.c:350] i2cDumpInts(): [02]	0x0001	0x0200	0x0000	0x0000	0x000073d5
-[I][esp32-hal-i2c.c:350] i2cDumpInts(): [03]	0x0001	0x0080	0x0000	0x0008	0x000073d6
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 0]	Y	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 1]	Y	WRITE	val[0]	exp[0]	en[1]	bytes[1]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 2]	Y	WRITE	val[0]	exp[0]	en[1]	bytes[1]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 3]	Y	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 4]	Y	WRITE	val[0]	exp[0]	en[1]	bytes[1]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 5]	Y	READ	val[0]	exp[0]	en[0]	bytes[7]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 6]	Y	READ	val[1]	exp[0]	en[0]	bytes[1]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 7]	Y	STOP	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 8]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 9]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [10]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [11]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [12]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [13]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [14]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [15]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[I][esp32-hal-i2c.c:385] i2cDumpStatus(): ack(0) sl_rw(0) to(0) arb(0) busy(0) sl(1) trans(0) rx(0) tx(0) sclMain(5) scl(6)
-[I][esp32-hal-i2c.c:424] i2cDumpFifo(): WRITE 0x68   0 
-[I][esp32-hal-i2c.c:424] i2cDumpFifo(): READ  0x68
-```
-## Explaination of log output
-### DumpI2c
-```
-[I][esp32-hal-i2c.c:437] i2cTriggerDumps(): after ProcQueue
-[E][esp32-hal-i2c.c:318] i2cDumpI2c(): i2c=0x3ffbdc78
-[I][esp32-hal-i2c.c:319] i2cDumpI2c(): dev=0x60013000 date=0x16042000
-[I][esp32-hal-i2c.c:321] i2cDumpI2c(): lock=0x3ffb843c
-[I][esp32-hal-i2c.c:323] i2cDumpI2c(): num=0
-[I][esp32-hal-i2c.c:324] i2cDumpI2c(): mode=1
-[I][esp32-hal-i2c.c:325] i2cDumpI2c(): stage=3
-[I][esp32-hal-i2c.c:326] i2cDumpI2c(): error=1
-[I][esp32-hal-i2c.c:327] i2cDumpI2c(): event=0x3ffb85c4 bits=10
-[I][esp32-hal-i2c.c:328] i2cDumpI2c(): intr_handle=0x3ffb85f4
-[I][esp32-hal-i2c.c:329] i2cDumpI2c(): dq=0x3ffb858c
-[I][esp32-hal-i2c.c:330] i2cDumpI2c(): queueCount=2
-[I][esp32-hal-i2c.c:331] i2cDumpI2c(): queuePos=1
-[I][esp32-hal-i2c.c:332] i2cDumpI2c(): errorByteCnt=0
-[I][esp32-hal-i2c.c:333] i2cDumpI2c(): errorQueue=0
-[I][esp32-hal-i2c.c:334] i2cDumpI2c(): debugFlags=0x001F0000
-```
-variable | description
----- | ----
-**i2c** | *memory address for control block*
-**dev** | *memory address for access to i2c peripheral registers*
-**date** | *revision date of peripheral silicon 2016, 42 week*
-**lock** | *hal lock handle*
-**num** | *0,1 which peripheral is being controlled*
-**mode** | *configuration of driver 0=none, 1=MASTER, 2=SLAVE, 3=MASTER and SLAVE*
-**stage** | *internal STATE of driver 0=not configured, 1=startup, 2=running, 3=done*
-**error** | *internal ERROR status 0=not configured, 1=ok, 2=error, 3=address NAK, 4=data NAK, 5=arbitration loss, 6=timeout*
-**event** | *handle for interprocess FreeRTOS eventSemaphore for communication between ISR and APP*
-**intr_handle** | *FreeRTOS handle for allocated interrupt*
-**dq** | *memory address for data queue control block*
-**queueCount** | *number of data operations in queue control block*
-**queuePos** | *last executed data block*
-**errorByteCnt** | *position in current data block when error occured -1=address byte*
-**errorQueue** | *queue that was executing when error occurred*
-**debugFlags** | *current specified error bits*
-
-### DQ data
-```
-[I][esp32-hal-i2c.c:288] i2cDumpDqData(): [0] 7bit 68 W  buf@=0x3ffc04b2, len=1, pos=1, ctrl=11101
-[I][esp32-hal-i2c.c:306] i2cDumpDqData(): 0x0000: .                                00 
-[I][esp32-hal-i2c.c:288] i2cDumpDqData(): [1] 7bit 68 R STOP buf@=0x3ffc042c, len=8, pos=8, ctrl=11111
-[I][esp32-hal-i2c.c:306] i2cDumpDqData(): 0x0000: 5P......                         35 50 07 06 13 09 18 00 
-```
-variable | description
---- | ---
-**[n]** | *index of data queue element*
-**i2c address** | *7bit= 7bit i2c slave address, 10bit= 10bit i2c slave address*
-**direction** | *W=Write, R=READ*
-**STOP** | *command issued a I2C STOP, else if blank, a RESTART was issued by next dq element.*
-**buf@** | *pointer to data buffer*
-**len** | *length of data buffer*
-**pos** | *last position used in buffer*
-**ctrl** | *bit field for data queue control, this bits describe if all necessary commands have been added to peripheral command buffer. in order(START,ADDRESS_Write,DATA,STOP,ADDRESS_value*
-**0xnnnn** | *data buffer content, displayable followed by HEX, 32 bytes on a line.*
- 
-### DumpInts
-```
-[I][esp32-hal-i2c.c:346] i2cDumpInts(): 0 row	count	INTR	TX	RX	Tick 
-[I][esp32-hal-i2c.c:350] i2cDumpInts(): [01]	0x0001	0x0002	0x0003	0x0000	0x000073d5
-[I][esp32-hal-i2c.c:350] i2cDumpInts(): [02]	0x0001	0x0200	0x0000	0x0000	0x000073d5
-[I][esp32-hal-i2c.c:350] i2cDumpInts(): [03]	0x0001	0x0080	0x0000	0x0008	0x000073d6
-```
-variable | description
----- | ----
-**row** | *array index*
-**count** | *number of consecutive, duplicate interrupts*
-**INTR** | *bit value of active interrupt (from ..\esp32\tools\sdk\include\soc\soc\i2c_struct.h)*
-**TX** | *number of bytes added to txFifo*
-**RX** | *number of bytes read from rxFifo*
-**Tick** | *current tick counter from xTaskGetTickCountFromISR()*
-
-### DumpCmdQueue
-```
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 0]	Y	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 1]	Y	WRITE	val[0]	exp[0]	en[1]	bytes[1]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 2]	Y	WRITE	val[0]	exp[0]	en[1]	bytes[1]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 3]	Y	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 4]	Y	WRITE	val[0]	exp[0]	en[1]	bytes[1]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 5]	Y	READ	val[0]	exp[0]	en[0]	bytes[7]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 6]	Y	READ	val[1]	exp[0]	en[0]	bytes[1]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 7]	Y	STOP	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 8]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [ 9]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [10]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [11]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [12]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [13]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [14]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-[E][esp32-hal-i2c.c:243] i2cDumpCmdQueue(): [15]	N	RSTART	val[0]	exp[0]	en[0]	bytes[0]
-```
-Column | description
----- | ----
-**command** | *RSTART= generate i2c START sequence, WRITE= output byte(s), READ= input byte(s), STOP= generate i2c STOP sequence, END= continuation flag for peripheral to pause execution waiting for a refilled command list*
-**val** | *value for ACK bit, 0 = LOW, 1= HIGH*
-**exp** | *test of ACK bit 0=no, 1=yes*
-**en** | *output of val, 0=no, 1=yes*
-**bytes** | *number of byte to send(WRITE) or receive(READ) 1..255*
- 
-### DumpStatus
-```
-[I][esp32-hal-i2c.c:385] i2cDumpStatus(): ack(0) sl_rw(0) to(0) arb(0) busy(0) sl(1) trans(0) rx(0) tx(0) sclMain(5) scl(6)
-```
-variable | description
----- | ----
-**ack** | *last value for ACK bit*
-**sl_rw** | *mode for SLAVE operation 0=write, 1=read*
-**to** | *timeout*
-**arb** | *arbitration loss*
-**busy** | *bus is inuse by other Master, or SLAVE is holding SCL,SDA*
-**sl** | *last address on bus was equal to slave_addr*
-**trans** | *a byte has moved though peripheral*
-**rx** | *count of bytes in rxFifo*
-**tx** | *count of bytes in txFifo*
-**sclMain** | *state machine for i2c module.  0: SCL_MAIN_IDLE,  1: SCL_ADDRESS_SHIFT, 2: SCL_ACK_ADDRESS, 3: SCL_RX_DATA, 4: SCL_TX_DATA, 5: SCL_SEND_ACK, 6 :SCL_WAIT_ACK*
-**scl** | *SCL clock state. 0: SCL_IDLE, 1: SCL_START, 2: SCL_LOW_EDGE, 3: SCL_LOW, 4: SCL_HIGH_EDGE, 5: SCL_HIGH, 6:SCL_STOP*
-
-### DumpFifo
-```
-[I][esp32-hal-i2c.c:424] i2cDumpFifo(): WRITE 0x68   0 
-[I][esp32-hal-i2c.c:424] i2cDumpFifo(): READ  0x68
-```
-Mode | datavalues
---- | ---
-**WRITE** | the following bytes added to the txFifo are in response to a WRITE command
-**READ** | the following bytes added to the txFifo are in response to a READ command
-
diff --git a/libraries/Wire/examples/WireMaster/WireMaster.ino b/libraries/Wire/examples/WireMaster/WireMaster.ino
new file mode 100644
index 00000000000..ea603e3c649
--- /dev/null
+++ b/libraries/Wire/examples/WireMaster/WireMaster.ino
@@ -0,0 +1,30 @@
+#include "Wire.h"
+
+#define I2C_DEV_ADDR 0x55
+
+uint32_t i = 0;
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+  Wire.begin();
+}
+
+void loop() {
+  delay(5000);
+
+  //Write message to the slave
+  Wire.beginTransmission(I2C_DEV_ADDR);
+  Wire.printf("Hello World! %lu", i++);
+  uint8_t error = Wire.endTransmission(true);
+  Serial.printf("endTransmission: %u\n", error);
+
+  //Read 16 bytes from the slave
+  uint8_t bytesReceived = Wire.requestFrom(I2C_DEV_ADDR, 16);
+  Serial.printf("requestFrom: %u\n", bytesReceived);
+  if ((bool)bytesReceived) {  //If received more than zero bytes
+    uint8_t temp[bytesReceived];
+    Wire.readBytes(temp, bytesReceived);
+    log_print_buf(temp, bytesReceived);
+  }
+}
diff --git a/libraries/Wire/examples/WireMaster/ci.json b/libraries/Wire/examples/WireMaster/ci.json
new file mode 100644
index 00000000000..1844adfc786
--- /dev/null
+++ b/libraries/Wire/examples/WireMaster/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_I2C_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/Wire/examples/WireScan/WireScan.ino b/libraries/Wire/examples/WireScan/WireScan.ino
new file mode 100644
index 00000000000..59f17af60fc
--- /dev/null
+++ b/libraries/Wire/examples/WireScan/WireScan.ino
@@ -0,0 +1,28 @@
+#include "Wire.h"
+
+void setup() {
+  Serial.begin(115200);
+  Wire.begin();
+}
+
+void loop() {
+  byte error, address;
+  int nDevices = 0;
+
+  delay(5000);
+
+  Serial.println("Scanning for I2C devices ...");
+  for (address = 0x01; address < 0x7f; address++) {
+    Wire.beginTransmission(address);
+    error = Wire.endTransmission();
+    if (error == 0) {
+      Serial.printf("I2C device found at address 0x%02X\n", address);
+      nDevices++;
+    } else if (error != 2) {
+      Serial.printf("Error %d at address 0x%02X\n", error, address);
+    }
+  }
+  if (nDevices == 0) {
+    Serial.println("No I2C devices found");
+  }
+}
diff --git a/libraries/Wire/examples/WireScan/ci.json b/libraries/Wire/examples/WireScan/ci.json
new file mode 100644
index 00000000000..1844adfc786
--- /dev/null
+++ b/libraries/Wire/examples/WireScan/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_I2C_SUPPORTED=y"
+  ]
+}
diff --git a/libraries/Wire/examples/WireSlave/WireSlave.ino b/libraries/Wire/examples/WireSlave/WireSlave.ino
new file mode 100644
index 00000000000..9e8654966c6
--- /dev/null
+++ b/libraries/Wire/examples/WireSlave/WireSlave.ino
@@ -0,0 +1,35 @@
+#include "Wire.h"
+
+#define I2C_DEV_ADDR 0x55
+
+uint32_t i = 0;
+
+void onRequest() {
+  Wire.print(i++);
+  Wire.print(" Packets.");
+  Serial.println("onRequest");
+}
+
+void onReceive(int len) {
+  Serial.printf("onReceive[%d]: ", len);
+  while (Wire.available()) {
+    Serial.write(Wire.read());
+  }
+  Serial.println();
+}
+
+void setup() {
+  Serial.begin(115200);
+  Serial.setDebugOutput(true);
+  Wire.onReceive(onReceive);
+  Wire.onRequest(onRequest);
+  Wire.begin((uint8_t)I2C_DEV_ADDR);
+
+#if CONFIG_IDF_TARGET_ESP32
+  char message[64];
+  snprintf(message, 64, "%lu Packets.", i++);
+  Wire.slaveWrite((uint8_t *)message, strlen(message));
+#endif
+}
+
+void loop() {}
diff --git a/libraries/Wire/examples/WireSlave/ci.json b/libraries/Wire/examples/WireSlave/ci.json
new file mode 100644
index 00000000000..3c877975d62
--- /dev/null
+++ b/libraries/Wire/examples/WireSlave/ci.json
@@ -0,0 +1,5 @@
+{
+  "requires": [
+    "CONFIG_SOC_I2C_SUPPORT_SLAVE=y"
+  ]
+}
diff --git a/libraries/Wire/keywords.txt b/libraries/Wire/keywords.txt
index 3344011d406..80d5f0d61a2 100644
--- a/libraries/Wire/keywords.txt
+++ b/libraries/Wire/keywords.txt
@@ -11,13 +11,14 @@
 #######################################
 
 begin	KEYWORD2
+end	KEYWORD2
 setClock	KEYWORD2
-setClockStretchLimit	KEYWORD2
+getClock	KEYWORD2
+setTimeOut	KEYWORD2
+getTimeOut	KEYWORD2
 beginTransmission	KEYWORD2
 endTransmission	KEYWORD2
 requestFrom	KEYWORD2
-send	KEYWORD2
-receive	KEYWORD2
 onReceive	KEYWORD2
 onRequest	KEYWORD2
 
@@ -26,8 +27,8 @@ onRequest	KEYWORD2
 #######################################
 
 Wire	KEYWORD2
+TwoWire	KEYWORD2
 
 #######################################
 # Constants (LITERAL1)
 #######################################
-
diff --git a/libraries/Wire/library.properties b/libraries/Wire/library.properties
index 099cf6f0bac..655f4bd3194 100644
--- a/libraries/Wire/library.properties
+++ b/libraries/Wire/library.properties
@@ -1,8 +1,8 @@
 name=Wire
-version=1.0.1
+version=3.2.0
 author=Hristo Gochkov
 maintainer=Hristo Gochkov <hristo@espressif.com>
-sentence=Allows the communication between devices or sensors connected via Two Wire Interface Bus. For esp8266 boards. 
+sentence=Allows the communication between devices or sensors connected via Two Wire Interface Bus. For esp8266 boards.
 paragraph=
 category=Signal Input/Output
 url=http://arduino.cc/en/Reference/Wire
diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp
index 3fbd0eb0876..f8d9496389f 100644
--- a/libraries/Wire/src/Wire.cpp
+++ b/libraries/Wire/src/Wire.cpp
@@ -20,7 +20,10 @@
   Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support
   Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support
   Modified Nov 2017 by Chuck Todd (ctodd@cableone.net) - ESP32 ISR Support
+  Modified Nov 2021 by Hristo Gochkov <Me-No-Dev> to support ESP-IDF API
  */
+#include "soc/soc_caps.h"
+#if SOC_I2C_SUPPORTED
 
 extern "C" {
 #include <stdlib.h>
@@ -29,354 +32,631 @@ extern "C" {
 }
 
 #include "esp32-hal-i2c.h"
+#if SOC_I2C_SUPPORT_SLAVE
+#include "esp32-hal-i2c-slave.h"
+#endif /* SOC_I2C_SUPPORT_SLAVE */
 #include "Wire.h"
 #include "Arduino.h"
 
 TwoWire::TwoWire(uint8_t bus_num)
-    :num(bus_num & 1)
-    ,sda(-1)
-    ,scl(-1)
-    ,i2c(NULL)
-    ,rxIndex(0)
-    ,rxLength(0)
-    ,rxQueued(0)
-    ,txIndex(0)
-    ,txLength(0)
-    ,txAddress(0)
-    ,txQueued(0)
-    ,transmitting(0)
-    ,last_error(I2C_ERROR_OK)
-    ,_timeOutMillis(50)
-{}
-
-TwoWire::~TwoWire()
+  : num(bus_num & 1), sda(-1), scl(-1), bufferSize(I2C_BUFFER_LENGTH)  // default Wire Buffer Size
+    ,
+    rxBuffer(NULL), rxIndex(0), rxLength(0), txBuffer(NULL), txLength(0), txAddress(0), _timeOutMillis(50), nonStop(false)
+#if !CONFIG_DISABLE_HAL_LOCKS
+    ,
+    currentTaskHandle(NULL), lock(NULL)
+#endif
+#if SOC_I2C_SUPPORT_SLAVE
+    ,
+    is_slave(false), user_onRequest(NULL), user_onReceive(NULL)
+#endif /* SOC_I2C_SUPPORT_SLAVE */
 {
-    flush();
-    if(i2c) {
-        i2cRelease(i2c);
-        i2c=NULL;
-    }
 }
 
-bool TwoWire::setPins(int sdaPin, int sclPin)
-{
-    if(i2c) {
-        log_e("can not set pins if begin was already called");
-        return false;
-    }
-    sda = sdaPin;
-    scl = sclPin;
-    return true;
+TwoWire::~TwoWire() {
+  end();
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (lock != NULL) {
+    vSemaphoreDelete(lock);
+  }
+#endif
 }
 
-bool TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency)
-{
-    if(sdaPin < 0) { // default param passed
-        if(num == 0) {
-            if(sda==-1) {
-                sdaPin = SDA;    //use Default Pin
-            } else {
-                sdaPin = sda;    // reuse prior pin
-            }
-        } else {
-            if(sda==-1) {
-                log_e("no Default SDA Pin for Second Peripheral");
-                return false; //no Default pin for Second Peripheral
-            } else {
-                sdaPin = sda;    // reuse prior pin
-            }
-        }
-    }
-
-    if(sclPin < 0) { // default param passed
-        if(num == 0) {
-            if(scl == -1) {
-                sclPin = SCL;    // use Default pin
-            } else {
-                sclPin = scl;    // reuse prior pin
-            }
-        } else {
-            if(scl == -1) {
-                log_e("no Default SCL Pin for Second Peripheral");
-                return false; //no Default pin for Second Peripheral
-            } else {
-                sclPin = scl;    // reuse prior pin
-            }
-        }
-    }
-
-    sda = sdaPin;
-    scl = sclPin;
-    i2c = i2cInit(num, sdaPin, sclPin, frequency);
-    if(!i2c) {
-        return false;
+bool TwoWire::initPins(int sdaPin, int sclPin) {
+  if (sdaPin < 0) {  // default param passed
+    if (num == 0) {
+      if (sda == -1) {
+        sdaPin = SDA;  //use Default Pin
+      } else {
+        sdaPin = sda;  // reuse prior pin
+      }
+    } else {
+      if (sda == -1) {
+#ifdef WIRE1_PIN_DEFINED
+        sdaPin = SDA1;
+#else
+        log_e("no Default SDA Pin for Second Peripheral");
+        return false;  //no Default pin for Second Peripheral
+#endif
+      } else {
+        sdaPin = sda;  // reuse prior pin
+      }
     }
-
-    flush();
-    return true;
-
-}
-
-void TwoWire::setTimeOut(uint16_t timeOutMillis)
-{
-    _timeOutMillis = timeOutMillis;
-}
-
-uint16_t TwoWire::getTimeOut()
-{
-    return _timeOutMillis;
-}
-
-void TwoWire::setClock(uint32_t frequency)
-{
-    i2cSetFrequency(i2c, frequency);
-}
-
-size_t TwoWire::getClock()
-{
-    return i2cGetFrequency(i2c);
-}
-
-/* stickBreaker Nov 2017 ISR, and bigblock 64k-1
- */
-i2c_err_t TwoWire::writeTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop)
-{
-    last_error = i2cWrite(i2c, address, buff, size, sendStop, _timeOutMillis);
-    return last_error;
-}
-
-i2c_err_t TwoWire::readTransmission(uint16_t address, uint8_t *buff, uint16_t size, bool sendStop, uint32_t *readCount)
-{
-    last_error = i2cRead(i2c, address, buff, size, sendStop, _timeOutMillis, readCount);
-    return last_error;
-}
-
-void TwoWire::beginTransmission(uint16_t address)
-{
-    transmitting = 1;
-    txAddress = address;
-    txIndex = txQueued; // allow multiple beginTransmission(),write(),endTransmission(false) until endTransmission(true)
-    txLength = txQueued;
-    last_error = I2C_ERROR_OK;
-}
-
-/*stickbreaker isr
- */
-uint8_t TwoWire::endTransmission(bool sendStop)  // Assumes Wire.beginTransaction(), Wire.write()
-{
-    if(transmitting == 1) {
-            // txlength is howmany bytes in txbuffer have been use
-        last_error = writeTransmission(txAddress, &txBuffer[txQueued], txLength - txQueued, sendStop);
-        if(last_error == I2C_ERROR_CONTINUE){
-            txQueued = txLength;
-        } else if( last_error == I2C_ERROR_OK){
-          rxIndex = 0;
-          rxLength = rxQueued;
-          rxQueued = 0;
-          txQueued = 0; // the SendStop=true will restart all Queueing
-        }
+  }
+
+  if (sclPin < 0) {  // default param passed
+    if (num == 0) {
+      if (scl == -1) {
+        sclPin = SCL;  // use Default pin
+      } else {
+        sclPin = scl;  // reuse prior pin
+      }
     } else {
-        last_error = I2C_ERROR_NO_BEGIN;
-        flush();
+      if (scl == -1) {
+#ifdef WIRE1_PIN_DEFINED
+        sclPin = SCL1;
+#else
+        log_e("no Default SCL Pin for Second Peripheral");
+        return false;  //no Default pin for Second Peripheral
+#endif
+      } else {
+        sclPin = scl;  // reuse prior pin
+      }
     }
-    txIndex = 0;
-    txLength = 0;
-    transmitting = 0;
-    return (last_error == I2C_ERROR_CONTINUE)?I2C_ERROR_OK:last_error; // Don't return Continue for compatibility.
+  }
+
+  sda = sdaPin;
+  scl = sclPin;
+  return true;
 }
 
-/* @stickBreaker 11/2017 fix for ReSTART timeout, ISR
- */
-uint8_t TwoWire::requestFrom(uint16_t address, uint8_t size, bool sendStop)
-{
-    //use internal Wire rxBuffer, multiple requestFrom()'s may be pending, try to share rxBuffer
-    uint32_t cnt = rxQueued; // currently queued reads, next available position in rxBuffer
-    if(cnt < (I2C_BUFFER_LENGTH-1) && (size + cnt) <= I2C_BUFFER_LENGTH) { // any room left in rxBuffer
-        rxQueued += size;
-    } else { // no room to receive more!
-        log_e("rxBuff overflow %d", cnt + size);
-        cnt = 0;
-        last_error = I2C_ERROR_MEMORY;
-        flush();
-        return cnt;
+bool TwoWire::setPins(int sdaPin, int sclPin) {
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (lock == NULL) {
+    lock = xSemaphoreCreateMutex();
+    if (lock == NULL) {
+      log_e("xSemaphoreCreateMutex failed");
+      return false;
     }
-
-    last_error = readTransmission(address, &rxBuffer[cnt], size, sendStop, &cnt);
-    rxIndex = 0;
-  
-    rxLength = cnt;
-  
-    if( last_error != I2C_ERROR_CONTINUE){ // not a  buffered ReSTART operation
-      // so this operation actually moved data, queuing is done.
-        rxQueued = 0;
-        txQueued = 0; // the SendStop=true will restart all Queueing or error condition
+  }
+  //acquire lock
+  if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return false;
+  }
+#endif
+  if (!i2cIsInit(num)) {
+    initPins(sdaPin, sclPin);
+  } else {
+    log_e("bus already initialized. change pins only when not.");
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(lock);
+#endif
+  return !i2cIsInit(num);
+}
+
+bool TwoWire::allocateWireBuffer() {
+  // or both buffer can be allocated or none will be
+  if (rxBuffer == NULL) {
+    rxBuffer = (uint8_t *)malloc(bufferSize);
+    if (rxBuffer == NULL) {
+      log_e("Can't allocate memory for I2C_%d rxBuffer", num);
+      return false;
     }
-  
-    if(last_error != I2C_ERROR_OK){ // ReSTART on read does not return any data
-        cnt = 0;
+  }
+  if (txBuffer == NULL) {
+    txBuffer = (uint8_t *)malloc(bufferSize);
+    if (txBuffer == NULL) {
+      log_e("Can't allocate memory for I2C_%d txBuffer", num);
+      freeWireBuffer();  // free rxBuffer for safety!
+      return false;
     }
-  
-    return cnt;
-}
-
-size_t TwoWire::write(uint8_t data)
-{
-    if(transmitting) {
-        if(txLength >= I2C_BUFFER_LENGTH) {
-            last_error = I2C_ERROR_MEMORY;
-            return 0;
-        }
-        txBuffer[txIndex] = data;
-        ++txIndex;
-        txLength = txIndex;
-        return 1;
+  }
+  // in case both were allocated before, they must have the same size. All good.
+  return true;
+}
+
+void TwoWire::freeWireBuffer() {
+  if (rxBuffer != NULL) {
+    free(rxBuffer);
+    rxBuffer = NULL;
+  }
+  if (txBuffer != NULL) {
+    free(txBuffer);
+    txBuffer = NULL;
+  }
+}
+
+size_t TwoWire::setBufferSize(size_t bSize) {
+  // Maximum size .... HEAP limited ;-)
+  if (bSize < 32) {  // 32 bytes is the I2C FIFO Len for ESP32/S2/S3/C3
+    log_e("Minimum Wire Buffer size is 32 bytes");
+    return 0;
+  }
+
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (lock == NULL) {
+    lock = xSemaphoreCreateMutex();
+    if (lock == NULL) {
+      log_e("xSemaphoreCreateMutex failed");
+      return 0;
     }
-    last_error = I2C_ERROR_NO_BEGIN; // no begin, not transmitting
+  }
+  //acquire lock
+  if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
     return 0;
-}
-
-size_t TwoWire::write(const uint8_t *data, size_t quantity)
-{
-    for(size_t i = 0; i < quantity; ++i) {
-        if(!write(data[i])) {
-            return i;
-        }
+  }
+#endif
+  // allocateWireBuffer allocates memory for both pointers or just free them
+  if (rxBuffer != NULL || txBuffer != NULL) {
+    // if begin() has been already executed, memory size changes... data may be lost. We don't care! :^)
+    if (bSize != bufferSize) {
+      // we want a new buffer size ... just reset buffer pointers and allocate new ones
+      freeWireBuffer();
+      bufferSize = bSize;
+      if (!allocateWireBuffer()) {
+        // failed! Error message already issued
+        bSize = 0;  // returns error
+        log_e("Buffer allocation failed");
+      }
+    }  // else nothing changes, all set!
+  } else {
+    // no memory allocated yet, just change the size value - allocation in begin()
+    bufferSize = bSize;
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(lock);
+
+#endif
+  return bSize;
+}
+
+#if SOC_I2C_SUPPORT_SLAVE
+// Slave Begin
+bool TwoWire::begin(uint8_t addr, int sdaPin, int sclPin, uint32_t frequency) {
+  bool started = false;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (lock == NULL) {
+    lock = xSemaphoreCreateMutex();
+    if (lock == NULL) {
+      log_e("xSemaphoreCreateMutex failed");
+      return false;
     }
-    return quantity;
-
-}
-
-int TwoWire::available(void)
-{
-    int result = rxLength - rxIndex;
-    return result;
-}
-
-int TwoWire::read(void)
-{
-    int value = -1;
-    if(rxIndex < rxLength) {
-        value = rxBuffer[rxIndex];
-        ++rxIndex;
+  }
+  //acquire lock
+  if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return false;
+  }
+#endif
+  if (is_slave) {
+    log_w("Bus already started in Slave Mode.");
+    started = true;
+    goto end;
+  }
+  if (i2cIsInit(num)) {
+    log_e("Bus already started in Master Mode.");
+    goto end;
+  }
+  if (!allocateWireBuffer()) {
+    // failed! Error Message already issued
+    goto end;
+  }
+  if (!initPins(sdaPin, sclPin)) {
+    goto end;
+  }
+  i2cSlaveAttachCallbacks(num, onRequestService, onReceiveService, this);
+  if (i2cSlaveInit(num, sda, scl, addr, frequency, bufferSize, bufferSize) != ESP_OK) {
+    log_e("Slave Init ERROR");
+    goto end;
+  }
+  is_slave = true;
+  started = true;
+end:
+  if (!started) {
+    freeWireBuffer();
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(lock);
+#endif
+  return started;
+}
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+
+// Master Begin
+bool TwoWire::begin(int sdaPin, int sclPin, uint32_t frequency) {
+  bool started = false;
+  esp_err_t err = ESP_OK;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (lock == NULL) {
+    lock = xSemaphoreCreateMutex();
+    if (lock == NULL) {
+      log_e("xSemaphoreCreateMutex failed");
+      return false;
     }
-    return value;
-}
-
-int TwoWire::peek(void)
-{
-    int value = -1;
-    if(rxIndex < rxLength) {
-        value = rxBuffer[rxIndex];
+  }
+  //acquire lock
+  if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return false;
+  }
+#endif
+#if SOC_I2C_SUPPORT_SLAVE
+  if (is_slave) {
+    log_e("Bus already started in Slave Mode.");
+    goto end;
+  }
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+  if (i2cIsInit(num)) {
+    log_w("Bus already started in Master Mode.");
+    started = true;
+    goto end;
+  }
+  if (!allocateWireBuffer()) {
+    // failed! Error Message already issued
+    goto end;
+  }
+  if (!initPins(sdaPin, sclPin)) {
+    goto end;
+  }
+  err = i2cInit(num, sda, scl, frequency);
+  started = (err == ESP_OK);
+
+end:
+  if (!started) {
+    freeWireBuffer();
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(lock);
+#endif
+  return started;
+}
+
+bool TwoWire::end() {
+  esp_err_t err = ESP_OK;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  if (lock != NULL) {
+    //acquire lock
+    if (xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) {
+      log_e("could not acquire lock");
+      return false;
     }
-    return value;
+#endif
+#if SOC_I2C_SUPPORT_SLAVE
+    if (is_slave) {
+      err = i2cSlaveDeinit(num);
+      if (err == ESP_OK) {
+        is_slave = false;
+      }
+    } else
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+      if (i2cIsInit(num)) {
+        err = i2cDeinit(num);
+      }
+    freeWireBuffer();
+#if !CONFIG_DISABLE_HAL_LOCKS
+    //release lock
+    xSemaphoreGive(lock);
+  }
+#endif
+  return (err == ESP_OK);
+}
+
+uint32_t TwoWire::getClock() {
+  uint32_t frequency = 0;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (lock == NULL || xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+  } else {
+#endif
+#if SOC_I2C_SUPPORT_SLAVE
+    if (is_slave) {
+      log_e("Bus is in Slave Mode");
+    } else
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+    {
+      i2cGetClock(num, &frequency);
+    }
+#if !CONFIG_DISABLE_HAL_LOCKS
+    //release lock
+    xSemaphoreGive(lock);
+  }
+#endif
+  return frequency;
+}
+
+bool TwoWire::setClock(uint32_t frequency) {
+  esp_err_t err = ESP_OK;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //acquire lock
+  if (lock == NULL || xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) {
+    log_e("could not acquire lock");
+    return false;
+  }
+#endif
+#if SOC_I2C_SUPPORT_SLAVE
+  if (is_slave) {
+    log_e("Bus is in Slave Mode");
+    err = ESP_FAIL;
+  } else
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+  {
+    err = i2cSetClock(num, frequency);
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  //release lock
+  xSemaphoreGive(lock);
+#endif
+  return (err == ESP_OK);
+}
+
+void TwoWire::setTimeOut(uint16_t timeOutMillis) {
+  _timeOutMillis = timeOutMillis;
+}
+
+uint16_t TwoWire::getTimeOut() {
+  return _timeOutMillis;
+}
+
+void TwoWire::beginTransmission(uint8_t address) {
+#if SOC_I2C_SUPPORT_SLAVE
+  if (is_slave) {
+    log_e("Bus is in Slave Mode");
+    return;
+  }
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+#if !CONFIG_DISABLE_HAL_LOCKS
+  TaskHandle_t task = xTaskGetCurrentTaskHandle();
+  if (currentTaskHandle != task) {
+    //acquire lock
+    if (lock == NULL || xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) {
+      log_e("could not acquire lock");
+      return;
+    }
+    currentTaskHandle = task;
+  }
+#endif
+  nonStop = false;
+  txAddress = address;
+  txLength = 0;
 }
 
-void TwoWire::flush(void)
-{
+/*
+https://www.arduino.cc/reference/en/language/functions/communication/wire/endtransmission/
+endTransmission() returns:
+0: success.
+1: data too long to fit in transmit buffer.
+2: received NACK on transmit of address.
+3: received NACK on transmit of data.
+4: other error.
+5: timeout
+*/
+uint8_t TwoWire::endTransmission(bool sendStop) {
+#if SOC_I2C_SUPPORT_SLAVE
+  if (is_slave) {
+    log_e("Bus is in Slave Mode");
+    return 4;
+  }
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+  if (txBuffer == NULL) {
+    log_e("NULL TX buffer pointer");
+    return 4;
+  }
+  esp_err_t err = ESP_OK;
+  if (sendStop) {
+    err = i2cWrite(num, txAddress, txBuffer, txLength, _timeOutMillis);
+#if !CONFIG_DISABLE_HAL_LOCKS
+    currentTaskHandle = NULL;
+    //release lock
+    xSemaphoreGive(lock);
+#endif
+  } else {
+    //mark as non-stop
+    nonStop = true;
+  }
+  switch (err) {
+    case ESP_OK:            return 0;
+    case ESP_FAIL:          return 2;
+    case ESP_ERR_NOT_FOUND: return 2;
+    case ESP_ERR_TIMEOUT:   return 5;
+    default:                break;
+  }
+  return 4;
+}
+
+uint8_t TwoWire::endTransmission() {
+  return endTransmission(true);
+}
+
+size_t TwoWire::requestFrom(uint8_t address, size_t size, bool sendStop) {
+#if SOC_I2C_SUPPORT_SLAVE
+  if (is_slave) {
+    log_e("Bus is in Slave Mode");
+    return 0;
+  }
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+  if (rxBuffer == NULL || txBuffer == NULL) {
+    log_e("NULL buffer pointer");
+    return 0;
+  }
+  esp_err_t err = ESP_OK;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  TaskHandle_t task = xTaskGetCurrentTaskHandle();
+  if (currentTaskHandle != task) {
+    //acquire lock
+    if (lock == NULL || xSemaphoreTake(lock, portMAX_DELAY) != pdTRUE) {
+      log_e("could not acquire lock");
+      return 0;
+    }
+    currentTaskHandle = task;
+  }
+#endif
+  if (nonStop) {
+    if (address != txAddress) {
+      log_e("Unfinished Repeated Start transaction! Expected address do not match! %u != %u", address, txAddress);
+#if !CONFIG_DISABLE_HAL_LOCKS
+      currentTaskHandle = NULL;
+      //release lock
+      xSemaphoreGive(lock);
+#endif
+      return 0;
+    }
+    nonStop = false;
     rxIndex = 0;
     rxLength = 0;
-    txIndex = 0;
-    txLength = 0;
-    rxQueued = 0;
-    txQueued = 0;
-    i2cFlush(i2c); // cleanup
-}
-
-uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity, uint8_t sendStop)
-{
-    return requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), static_cast<bool>(sendStop));
-}
-
-uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity, uint8_t sendStop)
-{
-    return requestFrom(address, static_cast<size_t>(quantity), static_cast<bool>(sendStop));
-}
-
-uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity)
-{
-    return requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), true);
-}
-
-uint8_t TwoWire::requestFrom(uint16_t address, uint8_t quantity)
-{
-    return requestFrom(address, static_cast<size_t>(quantity), true);
-}
-
-uint8_t TwoWire::requestFrom(int address, int quantity)
-{
-    return requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), true);
-}
-
-uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop)
-{
-    return static_cast<uint8_t>(requestFrom(static_cast<uint16_t>(address), static_cast<size_t>(quantity), static_cast<bool>(sendStop)));
-}
-
-void TwoWire::beginTransmission(int address)
-{
-    beginTransmission(static_cast<uint16_t>(address));
-}
-
-void TwoWire::beginTransmission(uint8_t address)
-{
-    beginTransmission(static_cast<uint16_t>(address));
+    err = i2cWriteReadNonStop(num, address, txBuffer, txLength, rxBuffer, size, _timeOutMillis, &rxLength);
+    if (err) {
+      log_e("i2cWriteReadNonStop returned Error %d", err);
+    }
+  } else {
+    rxIndex = 0;
+    rxLength = 0;
+    err = i2cRead(num, address, rxBuffer, size, _timeOutMillis, &rxLength);
+    if (err) {
+      log_e("i2cRead returned Error %d", err);
+    }
+  }
+#if !CONFIG_DISABLE_HAL_LOCKS
+  currentTaskHandle = NULL;
+  //release lock
+  xSemaphoreGive(lock);
+#endif
+  return rxLength;
 }
 
-uint8_t TwoWire::endTransmission(void)
-{
-    return endTransmission(true);
+size_t TwoWire::requestFrom(uint8_t address, size_t size) {
+  return requestFrom(address, size, true);
 }
 
-/* stickbreaker Nov2017 better error reporting
- */
-uint8_t TwoWire::lastError()
-{
-    return (uint8_t)last_error;
+size_t TwoWire::write(uint8_t data) {
+  if (txBuffer == NULL) {
+    log_e("NULL TX buffer pointer");
+    return 0;
+  }
+  if (txLength >= bufferSize) {
+    return 0;
+  }
+  txBuffer[txLength++] = data;
+  return 1;
 }
 
-const char ERRORTEXT[] =
-    "OK\0"
-    "DEVICE\0"
-    "ACK\0"
-    "TIMEOUT\0"
-    "BUS\0"
-    "BUSY\0"
-    "MEMORY\0"
-    "CONTINUE\0"
-    "NO_BEGIN\0"
-    "\0";
-
-
-char * TwoWire::getErrorText(uint8_t err)
-{
-    uint8_t t = 0;
-    bool found = false;
-    char * message = (char*)&ERRORTEXT;
-
-    while(!found && message[0]) {
-        found = t == err;
-        if(!found) {
-            message = message + strlen(message) + 1;
-            t++;
-        }
-    }
-    if(!found) {
-        return NULL;
-    } else {
-        return message;
+size_t TwoWire::write(const uint8_t *data, size_t quantity) {
+  for (size_t i = 0; i < quantity; ++i) {
+    if (!write(data[i])) {
+      return i;
     }
+  }
+  return quantity;
 }
 
-/*stickbreaker Dump i2c Interrupt buffer, i2c isr Debugging
- */
- 
-uint32_t TwoWire::setDebugFlags( uint32_t setBits, uint32_t resetBits){
-  return i2cDebug(i2c,setBits,resetBits);
+int TwoWire::available() {
+  int result = rxLength - rxIndex;
+  return result;
 }
 
-bool TwoWire::busy(void){
-  return ((i2cGetStatus(i2c) & 16 )==16);
+int TwoWire::read() {
+  int value = -1;
+  if (rxBuffer == NULL) {
+    log_e("NULL RX buffer pointer");
+    return value;
+  }
+  if (rxIndex < rxLength) {
+    value = rxBuffer[rxIndex++];
+  }
+  return value;
 }
 
+int TwoWire::peek() {
+  int value = -1;
+  if (rxBuffer == NULL) {
+    log_e("NULL RX buffer pointer");
+    return value;
+  }
+  if (rxIndex < rxLength) {
+    value = rxBuffer[rxIndex];
+  }
+  return value;
+}
+
+void TwoWire::flush() {
+  rxIndex = 0;
+  rxLength = 0;
+  txLength = 0;
+  //i2cFlush(num); // cleanup
+}
+
+void TwoWire::onReceive(void (*function)(int)) {
+#if SOC_I2C_SUPPORT_SLAVE
+  user_onReceive = function;
+#endif
+}
+
+// sets function called on slave read
+void TwoWire::onRequest(void (*function)(void)) {
+#if SOC_I2C_SUPPORT_SLAVE
+  user_onRequest = function;
+#endif
+}
+
+#if SOC_I2C_SUPPORT_SLAVE
+
+size_t TwoWire::slaveWrite(const uint8_t *buffer, size_t len) {
+  return i2cSlaveWrite(num, buffer, len, _timeOutMillis);
+}
+
+void TwoWire::onReceiveService(uint8_t num, uint8_t *inBytes, size_t numBytes, bool stop, void *arg) {
+  TwoWire *wire = (TwoWire *)arg;
+  if (!wire->user_onReceive) {
+    return;
+  }
+  if (wire->rxBuffer == NULL) {
+    log_e("NULL RX buffer pointer");
+    return;
+  }
+  for (uint8_t i = 0; i < numBytes; ++i) {
+    wire->rxBuffer[i] = inBytes[i];
+  }
+  wire->rxIndex = 0;
+  wire->rxLength = numBytes;
+  wire->user_onReceive(numBytes);
+}
+
+void TwoWire::onRequestService(uint8_t num, void *arg) {
+  TwoWire *wire = (TwoWire *)arg;
+  if (!wire->user_onRequest) {
+    return;
+  }
+  if (wire->txBuffer == NULL) {
+    log_e("NULL TX buffer pointer");
+    return;
+  }
+  wire->txLength = 0;
+  wire->user_onRequest();
+  if (wire->txLength) {
+    wire->slaveWrite((uint8_t *)wire->txBuffer, wire->txLength);
+  }
+}
+
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+
 TwoWire Wire = TwoWire(0);
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
+#if SOC_I2C_NUM > 1
+TwoWire Wire1 = TwoWire(1);
+#elif SOC_I2C_NUM > 2
+TwoWire Wire2 = TwoWire(2);
+#endif /* SOC_I2C_NUM */
+#else
+#if SOC_HP_I2C_NUM > 1
 TwoWire Wire1 = TwoWire(1);
+#endif /* SOC_HP_I2C_NUM */
+#endif
+
+#endif /* SOC_I2C_SUPPORTED */
diff --git a/libraries/Wire/src/Wire.h b/libraries/Wire/src/Wire.h
index 00f268b7df4..0deab7d4a57 100644
--- a/libraries/Wire/src/Wire.h
+++ b/libraries/Wire/src/Wire.h
@@ -20,134 +20,142 @@
   Modified December 2014 by Ivan Grokhotkov (ivan@esp8266.com) - esp8266 support
   Modified April 2015 by Hrsto Gochkov (ficeto@ficeto.com) - alternative esp8266 support
   Modified November 2017 by Chuck Todd <stickbreaker on GitHub> to use ISR and increase stability.
+  Modified Nov 2021 by Hristo Gochkov <Me-No-Dev> to support ESP-IDF API
 */
 
 #ifndef TwoWire_h
 #define TwoWire_h
 
+#include "soc/soc_caps.h"
+#if SOC_I2C_SUPPORTED
+#include "esp_idf_version.h"
+
 #include <esp32-hal.h>
+#include <esp32-hal-log.h>
+#if !CONFIG_DISABLE_HAL_LOCKS
 #include "freertos/FreeRTOS.h"
-#include "freertos/queue.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#endif
+#include "HardwareI2C.h"
 #include "Stream.h"
 
-#define STICKBREAKER 'V1.1.0'
-#define I2C_BUFFER_LENGTH 128
-typedef void(*user_onRequest)(void);
-typedef void(*user_onReceive)(uint8_t*, int);
+// WIRE_HAS_BUFFER_SIZE means Wire has setBufferSize()
+#define WIRE_HAS_BUFFER_SIZE 1
+// WIRE_HAS_END means Wire has end()
+#define WIRE_HAS_END 1
+
+#ifndef I2C_BUFFER_LENGTH
+#define I2C_BUFFER_LENGTH 128  // Default size, if none is set using Wire::setBuffersize(size_t)
+#endif
+#if SOC_I2C_SUPPORT_SLAVE
+typedef void (*user_onRequest)(void);
+typedef void (*user_onReceive)(uint8_t *, int);
+#endif /* SOC_I2C_SUPPORT_SLAVE */
 
-class TwoWire: public Stream
-{
+class TwoWire : public HardwareI2C {
 protected:
-    uint8_t num;
-    int8_t sda;
-    int8_t scl;
-    i2c_t * i2c;
-
-    uint8_t rxBuffer[I2C_BUFFER_LENGTH];
-    uint16_t rxIndex;
-    uint16_t rxLength;
-    uint16_t rxQueued; //@stickBreaker
-
-    uint8_t txBuffer[I2C_BUFFER_LENGTH];
-    uint16_t txIndex;
-    uint16_t txLength;
-    uint16_t txAddress;
-    uint16_t txQueued; //@stickbreaker
-
-    uint8_t transmitting;
-    /* slave Mode, not yet Stickbreaker
-            static user_onRequest uReq[2];
-            static user_onReceive uRcv[2];
-        void onRequestService(void);
-        void onReceiveService(uint8_t*, int);
-    */
-    i2c_err_t last_error; // @stickBreaker from esp32-hal-i2c.h
-    uint16_t _timeOutMillis;
+  uint8_t num;
+  int8_t sda;
+  int8_t scl;
+
+  size_t bufferSize;
+  uint8_t *rxBuffer;
+  size_t rxIndex;
+  size_t rxLength;
+
+  uint8_t *txBuffer;
+  size_t txLength;
+  uint16_t txAddress;
+
+  uint32_t _timeOutMillis;
+  bool nonStop;
+#if !CONFIG_DISABLE_HAL_LOCKS
+  TaskHandle_t currentTaskHandle;
+  SemaphoreHandle_t lock;
+#endif
+private:
+#if SOC_I2C_SUPPORT_SLAVE
+  bool is_slave;
+  void (*user_onRequest)(void);
+  void (*user_onReceive)(int);
+  static void onRequestService(uint8_t, void *);
+  static void onReceiveService(uint8_t, uint8_t *, size_t, bool, void *);
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+  bool initPins(int sdaPin, int sclPin);
+  bool allocateWireBuffer();
+  void freeWireBuffer();
 
 public:
-    TwoWire(uint8_t bus_num);
-    ~TwoWire();
-    
-    //call setPins() first, so that begin() can be called without arguments from libraries
-    bool setPins(int sda, int scl);
-    
-    bool begin(int sda=-1, int scl=-1, uint32_t frequency=0); // returns true, if successful init of i2c bus
-      // calling will attemp to recover hung bus
-
-    void setClock(uint32_t frequency); // change bus clock without initing hardware
-    size_t getClock(); // current bus clock rate in hz
-
-    void setTimeOut(uint16_t timeOutMillis); // default timeout of i2c transactions is 50ms
-    uint16_t getTimeOut();
-
-    uint8_t lastError();
-    char * getErrorText(uint8_t err);
-
-    //@stickBreaker for big blocks and ISR model
-    i2c_err_t writeTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true);
-    i2c_err_t readTransmission(uint16_t address, uint8_t* buff, uint16_t size, bool sendStop=true, uint32_t *readCount=NULL);
-
-    void beginTransmission(uint16_t address);
-    void beginTransmission(uint8_t address);
-    void beginTransmission(int address);
-
-    uint8_t endTransmission(bool sendStop);
-    uint8_t endTransmission(void);
-
-    uint8_t requestFrom(uint16_t address, uint8_t size, bool sendStop);
-    uint8_t requestFrom(uint16_t address, uint8_t size, uint8_t sendStop);
-    uint8_t requestFrom(uint16_t address, uint8_t size);
-    uint8_t requestFrom(uint8_t address, uint8_t size, uint8_t sendStop);
-    uint8_t requestFrom(uint8_t address, uint8_t size);
-    uint8_t requestFrom(int address, int size, int sendStop);
-    uint8_t requestFrom(int address, int size);
-
-    size_t write(uint8_t);
-    size_t write(const uint8_t *, size_t);
-    int available(void);
-    int read(void);
-    int peek(void);
-    void flush(void);
-
-    inline size_t write(const char * s)
-    {
-        return write((uint8_t*) s, strlen(s));
-    }
-    inline size_t write(unsigned long n)
-    {
-        return write((uint8_t)n);
-    }
-    inline size_t write(long n)
-    {
-        return write((uint8_t)n);
-    }
-    inline size_t write(unsigned int n)
-    {
-        return write((uint8_t)n);
-    }
-    inline size_t write(int n)
-    {
-        return write((uint8_t)n);
-    }
-
-    void onReceive( void (*)(int) );
-    void onRequest( void (*)(void) );
-
-    uint32_t setDebugFlags( uint32_t setBits, uint32_t resetBits);
-    bool busy();
+  TwoWire(uint8_t bus_num);
+  ~TwoWire();
+
+  bool begin() override final {
+    return begin(-1, -1);
+  }
+
+  bool begin(uint8_t address) override final {
+#if SOC_I2C_SUPPORT_SLAVE
+    return begin(address, -1, -1, 0);
+#else
+    log_e("I2C slave is not supported on " CONFIG_IDF_TARGET);
+    return false;
+#endif
+  }
+
+  bool end() override;
+
+  bool setClock(uint32_t freq) override;
+
+  void beginTransmission(uint8_t address) override;
+  uint8_t endTransmission(bool stopBit) override;
+  uint8_t endTransmission() override;
+
+  size_t requestFrom(uint8_t address, size_t len, bool stopBit) override;
+  size_t requestFrom(uint8_t address, size_t len) override;
+
+  void onReceive(void (*)(int)) override;
+  void onRequest(void (*)(void)) override;
+
+  //call setPins() first, so that begin() can be called without arguments from libraries
+  bool setPins(int sda, int scl);
+
+  bool begin(int sda, int scl, uint32_t frequency = 0);  // returns true, if successful init of i2c bus
+#if SOC_I2C_SUPPORT_SLAVE
+  bool begin(uint8_t slaveAddr, int sda, int scl, uint32_t frequency);
+#endif /* SOC_I2C_SUPPORT_SLAVE */
+
+  size_t setBufferSize(size_t bSize);
+
+  void setTimeOut(uint16_t timeOutMillis);  // default timeout of i2c transactions is 50ms
+  uint16_t getTimeOut();
+
+  uint32_t getClock();
+
+  size_t write(uint8_t) override;
+  size_t write(const uint8_t *, size_t) override;
+  int available() override;
+  int read() override;
+  int peek() override;
+  void flush() override;
+
+#if SOC_I2C_SUPPORT_SLAVE
+  size_t slaveWrite(const uint8_t *, size_t);
+#endif /* SOC_I2C_SUPPORT_SLAVE */
 };
 
 extern TwoWire Wire;
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 4, 0)
+#if SOC_I2C_NUM > 1
 extern TwoWire Wire1;
-
-
-/*
-V1.1.0 08JAN2019 Support CPU Clock frequency changes
-V1.0.2 30NOV2018 stop returning I2C_ERROR_CONTINUE on ReSTART operations, regain compatibility with Arduino libs
-V1.0.1 02AUG2018 First Fix after release, Correct ReSTART handling, change Debug control, change begin()
-  to a function, this allow reporting if bus cannot be initialized, Wire.begin() can be used to recover
-  a hung bus busy condition.
-V0.2.2 13APR2018 preserve custom SCL,SDA,Frequency when no parameters passed to begin()
-V0.2.1 15MAR2018 Hardware reset, Glitch prevention, adding destructor for second i2c testing
-*/
+#elif SOC_I2C_NUM > 2
+extern TwoWire Wire2;
+#endif /* SOC_I2C_NUM */
+#else
+#if SOC_HP_I2C_NUM > 1
+extern TwoWire Wire1;
+#endif /* SOC_HP_I2C_NUM */
 #endif
+
+#endif /* SOC_I2C_SUPPORTED */
+#endif /* TwoWire_h */
diff --git a/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/README.md b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/README.md
new file mode 100644
index 00000000000..d62941755c7
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/README.md
@@ -0,0 +1,72 @@
+# Arduino-ESP32 Zigbee Analog Input Output Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) analog input/output device.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Analog Sensor Functions
+
+ * After this board first starts up, it would be configured locally to report an analog input on change or every 30 seconds.
+ * By clicking the button (BOOT) on this board, this board will immediately send a report of the current measured  value to the network.
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+
+### Configure the Project
+
+Set the ADC GPIO by changing the `analogPin` variable. By default, it's the pin `A0`.
+Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/Zigbee_Analog_Input_Output.ino b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/Zigbee_Analog_Input_Output.ino
new file mode 100644
index 00000000000..e31407cc8be
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/Zigbee_Analog_Input_Output.ino
@@ -0,0 +1,119 @@
+// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee analog input / output device.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device analog device.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ * Modified by Pat Clay
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee analog device configuration */
+#define ANALOG_DEVICE_ENDPOINT_NUMBER 1
+
+uint8_t analogPin = A0;
+uint8_t button = BOOT_PIN;
+
+ZigbeeAnalog zbAnalogDevice = ZigbeeAnalog(ANALOG_DEVICE_ENDPOINT_NUMBER);
+
+void onAnalogOutputChange(float analog_output) {
+  Serial.printf("Received analog output change: %.1f\r\n", analog_output);
+}
+
+void setup() {
+  Serial.begin(115200);
+  Serial.println("Starting...");
+
+  // Init button switch
+  pinMode(button, INPUT_PULLUP);
+
+  // Set analog resolution to 10 bits
+  analogReadResolution(10);
+
+  // Optional: set Zigbee device name and model
+  zbAnalogDevice.setManufacturerAndModel("Espressif", "ZigbeeAnalogDevice");
+
+  // Add analog clusters to Zigbee Analog according your needs
+  zbAnalogDevice.addAnalogInput();
+  zbAnalogDevice.addAnalogOutput();
+
+  // If analog output cluster is added, set callback function for analog output change
+  zbAnalogDevice.onAnalogOutputChange(onAnalogOutputChange);
+
+  // Add endpoints to Zigbee Core
+  Zigbee.addEndpoint(&zbAnalogDevice);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println("Connected");
+
+  // Optional: Add reporting for analog input
+  zbAnalogDevice.setAnalogInputReporting(0, 30, 10);  // report every 30 seconds if value changes by 10
+}
+
+void loop() {
+  static uint32_t timeCounter = 0;
+
+  // Read ADC value and update the analog value every 2s
+  if (!(timeCounter++ % 20)) {  // delaying for 100ms x 20 = 2s
+    float analog = (float)analogRead(analogPin);
+    Serial.printf("Updating analog input to %.1f\r\n", analog);
+    zbAnalogDevice.setAnalogInput(analog);
+
+    // Analog input supports reporting
+    zbAnalogDevice.reportAnalogInput();
+  }
+
+  // Checking button for factory reset and reporting
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/ci.json b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Analog_Input_Output/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/README.md
new file mode 100644
index 00000000000..88c8bf04a65
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/README.md
@@ -0,0 +1,72 @@
+# Arduino-ESP32 Carbon dioxide (CO2) Sensor Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) simple sensor device type with carbon dioxide measuring.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Pressure + Flow Sensor Functions
+
+ * After this board first starts up, it would be configured locally to report the carbon dioxide on every 30 seconds.
+ * By clicking the button (BOOT) on this board, this board will immediately send a report of the current measured carbon dioxide to the network.
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+
+### Configure the Project
+
+In this example, the internal temperature sensor is used to demonstrate reading of the carbon dioxide sensors.
+Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/Zigbee_CarbonDioxide_Sensor.ino b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/Zigbee_CarbonDioxide_Sensor.ino
new file mode 100644
index 00000000000..47b9a05493f
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/Zigbee_CarbonDioxide_Sensor.ino
@@ -0,0 +1,106 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee carbon dioxide sensor.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device carbon dioxide sensor.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee carbon dioxide sensor configuration */
+#define CARBON_DIOXIDE_SENSOR_ENDPOINT_NUMBER 10
+uint8_t button = BOOT_PIN;
+
+ZigbeeCarbonDioxideSensor zbCarbonDioxideSensor = ZigbeeCarbonDioxideSensor(CARBON_DIOXIDE_SENSOR_ENDPOINT_NUMBER);
+
+void setup() {
+  Serial.begin(115200);
+
+  // Init button switch
+  pinMode(button, INPUT_PULLUP);
+
+  // Optional: set Zigbee device name and model
+  zbCarbonDioxideSensor.setManufacturerAndModel("Espressif", "ZigbeeCarbonDioxideSensor");
+
+  // Set minimum and maximum carbon dioxide measurement value in ppm
+  zbCarbonDioxideSensor.setMinMaxValue(0, 1500);
+
+  // Add endpoints to Zigbee Core
+  Zigbee.addEndpoint(&zbCarbonDioxideSensor);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+
+  // Set reporting interval for carbon dioxide measurement to be done every 30 seconds, must be called after Zigbee.begin()
+  // min_interval and max_interval in seconds, delta (carbon dioxide change in ppm)
+  // if min = 1 and max = 0, reporting is sent only when carbon dioxide changes by delta
+  // if min = 0 and max = 10, reporting is sent every 10 seconds or when carbon dioxide changes by delta
+  // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of delta change
+  zbCarbonDioxideSensor.setReporting(0, 30, 0);
+}
+
+void loop() {
+  static uint32_t timeCounter = 0;
+  // Read carbon dioxide sensor every 2s
+  if (!(timeCounter++ % 20)) {  // delaying for 100ms x 20 = 2s
+    // Read sensor value - here is chip temperature used + 300 as a dummy value for demonstration
+    uint16_t carbon_dioxide_value = 300 + (uint16_t)temperatureRead();
+    Serial.printf("Updating carbon dioxide sensor value to %d ppm\r\n", carbon_dioxide_value);
+    zbCarbonDioxideSensor.setCarbonDioxide(carbon_dioxide_value);
+  }
+
+  // Checking button for factory reset and reporting
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    zbCarbonDioxideSensor.report();
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/ci.json b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_CarbonDioxide_Sensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/README.md b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/README.md
new file mode 100644
index 00000000000..4da23c8c7d2
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/README.md
@@ -0,0 +1,68 @@
+# Arduino-ESP32 Zigbee Color Dimmable Light Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) color dimmable light.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee coordinator (loaded with Zigbee_Color_Dimmer_Switch example)
+* A USB cable for power supply and programming
+* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the Zigbee_Color_Dimmable_Light example
+
+### Configure the Project
+
+Set the LED GPIO by changing the `LED_PIN` definition. By default, the LED_PIN is `RGB_BUILTIN`.
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/Zigbee_Color_Dimmable_Light.ino b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/Zigbee_Color_Dimmable_Light.ino
new file mode 100644
index 00000000000..e84720d4863
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/Zigbee_Color_Dimmable_Light.ino
@@ -0,0 +1,122 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee Color Dimmable light bulb.
+ *
+ * The example demonstrates how to use Zigbee library to create an end device with
+ * color dimmable light end point.
+ * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee color dimmable light configuration */
+#define ZIGBEE_RGB_LIGHT_ENDPOINT 10
+uint8_t led = RGB_BUILTIN;
+uint8_t button = BOOT_PIN;
+
+ZigbeeColorDimmableLight zbColorLight = ZigbeeColorDimmableLight(ZIGBEE_RGB_LIGHT_ENDPOINT);
+
+/********************* RGB LED functions **************************/
+void setRGBLight(bool state, uint8_t red, uint8_t green, uint8_t blue, uint8_t level) {
+  if (!state) {
+    rgbLedWrite(led, 0, 0, 0);
+    return;
+  }
+  float brightness = (float)level / 255;
+  rgbLedWrite(led, red * brightness, green * brightness, blue * brightness);
+}
+
+// Create a task on identify call to handle the identify function
+void identify(uint16_t time) {
+  static uint8_t blink = 1;
+  log_d("Identify called for %d seconds", time);
+  if (time == 0) {
+    // If identify time is 0, stop blinking and restore light as it was used for identify
+    zbColorLight.restoreLight();
+    return;
+  }
+  rgbLedWrite(led, 255 * blink, 255 * blink, 255 * blink);
+  blink = !blink;
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Init RMT and leave light OFF
+  rgbLedWrite(led, 0, 0, 0);
+
+  // Init button for factory reset
+  pinMode(button, INPUT_PULLUP);
+
+  // Set callback function for light change
+  zbColorLight.onLightChange(setRGBLight);
+
+  // Optional: Set callback function for device identify
+  zbColorLight.onIdentify(identify);
+
+  // Optional: Set Zigbee device name and model
+  zbColorLight.setManufacturerAndModel("Espressif", "ZBColorLightBulb");
+
+  // Add endpoint to Zigbee Core
+  Serial.println("Adding ZigbeeLight endpoint to Zigbee Core");
+  Zigbee.addEndpoint(&zbColorLight);
+
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+}
+
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    // Increase blightness by 50 every time the button is pressed
+    zbColorLight.setLightLevel(zbColorLight.getLightLevel() + 50);
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/ci.json b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmable_Light/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/README.md b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/README.md
new file mode 100644
index 00000000000..8dd63a78c5e
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/README.md
@@ -0,0 +1,68 @@
+# Arduino-ESP32 Zigbee Color Dimmer Switch Example
+
+This example shows how to configure Zigbee Coordinator and use it as a Home Automation (HA) color dimmer light switch.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee end device (loaded with Zigbee_Color_Dimmable_Light example).
+* A USB cable for power supply and programming.
+* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee coordinator and upload the Zigbee_Color_Dimmable_Light example.
+
+### Configure the Project
+
+Set the Button Switch GPIO by changing the `GPIO_SWITCH` definition. By default, it's the pin `9` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the Coordinator Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`.
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`.
+* Select the COM port: `Tools -> Port: xxx where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with the example `Zigbee_Color_Dimmable_Light` is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/Zigbee_Color_Dimmer_Switch.ino b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/Zigbee_Color_Dimmer_Switch.ino
new file mode 100644
index 00000000000..a313f3c0594
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/Zigbee_Color_Dimmer_Switch.ino
@@ -0,0 +1,147 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee color dimmer switch.
+ *
+ * The example demonstrates how to use Zigbee library to control a RGB light bulb.
+ * The RGB light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator (Switch).
+ * To turn on/off the light, push the button on the switch.
+ * To change the color or level of the light, send serial commands to the switch.
+ *
+ * By setting the switch to allow multiple binding, so it can bind to multiple lights.
+ * Also every 30 seconds, all bound lights are printed to the serial console.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ZCZR
+#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee color dimmer switch configuration */
+#define SWITCH_ENDPOINT_NUMBER 5
+uint8_t button = BOOT_PIN;
+
+/* Zigbee switch */
+ZigbeeColorDimmerSwitch zbSwitch = ZigbeeColorDimmerSwitch(SWITCH_ENDPOINT_NUMBER);
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  //Init button switch
+  pinMode(button, INPUT_PULLUP);
+
+  //Optional: set Zigbee device name and model
+  zbSwitch.setManufacturerAndModel("Espressif", "ZigbeeSwitch");
+
+  //Optional to allow multiple light to bind to the switch
+  zbSwitch.allowMultipleBinding(true);
+
+  //Add endpoint to Zigbee Core
+  Zigbee.addEndpoint(&zbSwitch);
+
+  //Open network for 180 seconds after boot
+  Zigbee.setRebootOpenNetwork(180);
+
+  //When all EPs are registered, start Zigbee with ZIGBEE_COORDINATOR mode
+  if (!Zigbee.begin(ZIGBEE_COORDINATOR)) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+
+  Serial.println("Waiting for Light to bound to the switch");
+  //Wait for switch to bound to a light:
+  while (!zbSwitch.bound()) {
+    Serial.printf(".");
+    delay(500);
+  }
+  Serial.println();
+}
+
+void loop() {
+  // Handle button switch in loop()
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    while (digitalRead(button) == LOW) {
+      delay(50);
+    }
+    // Toggle light
+    zbSwitch.lightToggle();
+  }
+  // Handle serial input to control color and level of the light
+  if (Serial.available()) {
+    String command = Serial.readString();
+
+    if (command == "on") {
+      zbSwitch.lightOn();
+    } else if (command == "off") {
+      zbSwitch.lightOff();
+    } else if (command == "toggle") {
+      zbSwitch.lightToggle();
+    } else if (command == "red") {
+      zbSwitch.setLightColor(255, 0, 0);
+    } else if (command == "green") {
+      zbSwitch.setLightColor(0, 255, 0);
+    } else if (command == "blue") {
+      zbSwitch.setLightColor(0, 0, 255);
+    } else if (command == "white") {
+      zbSwitch.setLightColor(255, 255, 255);
+    } else if (command == "color") {
+      //wait for color value
+      Serial.println("Enter red value (0-255):");
+      while (!Serial.available()) {
+        delay(100);
+      }
+      int red = Serial.parseInt();
+      Serial.println("Enter green value (0-255):");
+      while (!Serial.available()) {
+        delay(100);
+      }
+      int green = Serial.parseInt();
+      Serial.println("Enter blue value (0-255):");
+      while (!Serial.available()) {
+        delay(100);
+      }
+      int blue = Serial.parseInt();
+      zbSwitch.setLightColor(red, green, blue);
+    } else if (command == "level") {
+      //wait for level value
+      Serial.println("Enter level value (0-255):");
+      while (!Serial.available()) {
+        delay(100);
+      }
+      int level = Serial.parseInt();
+      zbSwitch.setLightLevel(level);
+    } else {
+      Serial.println("Unknown command");
+    }
+  }
+
+  // print the bound devices (lights) every 30 seconds
+  static uint32_t last_print = 0;
+  if (millis() - last_print > 30000) {
+    last_print = millis();
+    zbSwitch.printBoundDevices(Serial);
+  }
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/ci.json b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/ci.json
new file mode 100644
index 00000000000..15d6190e4ae
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Color_Dimmer_Switch/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee_zczr,ZigbeeMode=zczr",
+  "requires": [
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Contact_Switch/README.md b/libraries/Zigbee/examples/Zigbee_Contact_Switch/README.md
new file mode 100644
index 00000000000..a5a32358a7c
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Contact_Switch/README.md
@@ -0,0 +1,58 @@
+# Arduino-ESP32 Zigbee Contact Switch Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) contact switch (IAS Zone),
+that can be used for example as window/door sensor having 2 states - closed/open.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+
+### Configure the Project
+
+Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+Set the Sensor GPIO by changing the `sensor_pin` variable.
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Contact_Switch/Zigbee_Contact_Switch.ino b/libraries/Zigbee/examples/Zigbee_Contact_Switch/Zigbee_Contact_Switch.ino
new file mode 100644
index 00000000000..ce9eedb683d
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Contact_Switch/Zigbee_Contact_Switch.ino
@@ -0,0 +1,100 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee contact switch (IAS Zone).
+ *
+ * The example demonstrates how to use Zigbee library to create a end device contact switch.
+ * The contact switch is a Zigbee end device, which is reporting data to the Zigbee network.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee contact sensor configuration */
+#define CONTACT_SWITCH_ENDPOINT_NUMBER 10
+uint8_t button = BOOT_PIN;
+uint8_t sensor_pin = 4;
+
+ZigbeeContactSwitch zbContactSwitch = ZigbeeContactSwitch(CONTACT_SWITCH_ENDPOINT_NUMBER);
+
+void setup() {
+  Serial.begin(115200);
+
+  // Init button + switch
+  pinMode(button, INPUT_PULLUP);
+  pinMode(sensor_pin, INPUT_PULLUP);
+
+  // Optional: set Zigbee device name and model
+  zbContactSwitch.setManufacturerAndModel("Espressif", "ZigbeeContactSwitch");
+
+  // Add endpoint to Zigbee Core
+  Zigbee.addEndpoint(&zbContactSwitch);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+}
+
+void loop() {
+  // Checking pin for contact change
+  static bool contact = false;
+  if (digitalRead(sensor_pin) == HIGH && !contact) {
+    // Update contact sensor value
+    zbContactSwitch.setOpen();
+    contact = true;
+  } else if (digitalRead(sensor_pin) == LOW && contact) {
+    zbContactSwitch.setClosed();
+    contact = false;
+  }
+
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Contact_Switch/ci.json b/libraries/Zigbee/examples/Zigbee_Contact_Switch/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Contact_Switch/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Dimmable_Light/README.md b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/README.md
new file mode 100644
index 00000000000..e5bf51b660c
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/README.md
@@ -0,0 +1,68 @@
+# Arduino-ESP32 Zigbee Dimmable Light Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) dimmable light.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+* Board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the Zigbee_Dimmable_Light example
+* Zigbee network / coordinator (Other board with switch examples or Zigbee2mqtt or ZigbeeHomeAssistant like application)
+
+### Configure the Project
+
+Set the LED GPIO by changing the `LED_PIN` definition. By default, the LED_PIN is `RGB_BUILTIN`.
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Dimmable_Light/Zigbee_Dimmable_Light.ino b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/Zigbee_Dimmable_Light.ino
new file mode 100644
index 00000000000..c77a7e742d1
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/Zigbee_Dimmable_Light.ino
@@ -0,0 +1,121 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee Dimmable light bulb.
+ *
+ * The example demonstrates how to use Zigbee library to create an end device with
+ * dimmable light end point.
+ * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by [FaBjE](https://github.com/FaBjE) based on examples by [Jan Procházka](https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee dimmable light configuration */
+#define ZIGBEE_LIGHT_ENDPOINT 10
+uint8_t led = RGB_BUILTIN;
+uint8_t button = BOOT_PIN;
+
+ZigbeeDimmableLight zbDimmableLight = ZigbeeDimmableLight(ZIGBEE_LIGHT_ENDPOINT);
+
+/********************* RGB LED functions **************************/
+void setLight(bool state, uint8_t level) {
+  if (!state) {
+    rgbLedWrite(led, 0, 0, 0);
+    return;
+  }
+  rgbLedWrite(led, level, level, level);
+}
+
+// Create a task on identify call to handle the identify function
+void identify(uint16_t time) {
+  static uint8_t blink = 1;
+  log_d("Identify called for %d seconds", time);
+  if (time == 0) {
+    // If identify time is 0, stop blinking and restore light as it was used for identify
+    zbDimmableLight.restoreLight();
+    return;
+  }
+  rgbLedWrite(led, 255 * blink, 255 * blink, 255 * blink);
+  blink = !blink;
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Init RMT and leave light OFF
+  rgbLedWrite(led, 0, 0, 0);
+
+  // Init button for factory reset
+  pinMode(button, INPUT_PULLUP);
+
+  // Set callback function for light change
+  zbDimmableLight.onLightChange(setLight);
+
+  // Optional: Set callback function for device identify
+  zbDimmableLight.onIdentify(identify);
+
+  // Optional: Set Zigbee device name and model
+  zbDimmableLight.setManufacturerAndModel("Espressif", "ZBLightBulb");
+
+  // Add endpoint to Zigbee Core
+  Serial.println("Adding ZigbeeLight endpoint to Zigbee Core");
+  Zigbee.addEndpoint(&zbDimmableLight);
+
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+}
+
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    // Increase blightness by 50 every time the button is pressed
+    zbDimmableLight.setLightLevel(zbDimmableLight.getLightLevel() + 50);
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Dimmable_Light/ci.json b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Dimmable_Light/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Gateway/README.md b/libraries/Zigbee/examples/Zigbee_Gateway/README.md
new file mode 100644
index 00000000000..4156538ccd9
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Gateway/README.md
@@ -0,0 +1,64 @@
+# Arduino-ESP32 Zigbee Gateway Example
+
+This example shows how to configure Zigbee Gateway device, running on SoCs without native IEEE 802.15.4.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 | ESP32-C3 |
+| ----------------- | ----- | -------- | -------- | -------- |
+
+## Hardware Required
+
+* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee Radio Co-processor loaded with [ot_rcp example](https://github.com/espressif/esp-idf/tree/master/examples/openthread/ot_rcp).
+* A USB cable for power supply and programming.
+* Choose another board from supported targets as Zigbee coordinator/router and upload the Zigbee_Gateway example.
+
+### Configure the Project
+
+Set the RCP connection (UART) by changing the `GATEWAY_RCP_UART_PORT`, `GATEWAY_RCP_RX_PIN` and `GATEWAY_RCP_TX_PIN` definition.
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the Coordinator Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`.
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`.
+* Select the COM port: `Tools -> Port: xxx where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Gateway/Zigbee_Gateway.ino b/libraries/Zigbee/examples/Zigbee_Gateway/Zigbee_Gateway.ino
new file mode 100644
index 00000000000..402227b9a3d
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Gateway/Zigbee_Gateway.ino
@@ -0,0 +1,130 @@
+// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates simple Zigbee Gateway functionality.
+ *
+ * The example demonstrates how to use Zigbee library on ESP32s to create a Zigbee Gateway, updating the time from NTP server.
+ * The Gateway is able to communicate with Zigbee end devices and send/receive data to/from them.
+ * The Gateway is also able to communicate with the cloud or other devices over Wi-Fi / BLE.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode->Zigbee ZCZR (coordinator/router)
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme->Zigbee ZCZR
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ZCZR
+#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+#include <WiFi.h>
+#include "time.h"
+#include "esp_sntp.h"
+
+/* Zigbee gateway configuration */
+#define GATEWAY_ENDPOINT_NUMBER 1
+#define GATEWAY_RCP_UART_PORT   UART_NUM_1  // UART 0 is used for Serial communication
+#define GATEWAY_RCP_RX_PIN      4
+#define GATEWAY_RCP_TX_PIN      5
+
+ZigbeeGateway zbGateway = ZigbeeGateway(GATEWAY_ENDPOINT_NUMBER);
+
+/* Wi-Fi credentials */
+const char *ssid = "your-ssid";
+const char *password = "your-password";
+
+/* NTP server configuration */
+const char *ntpServer1 = "pool.ntp.org";
+const char *ntpServer2 = "time.nist.gov";
+const long gmtOffset_sec = 3600;
+const int daylightOffset_sec = 3600;
+const char *time_zone = "CET-1CEST,M3.5.0,M10.5.0/3";  // TimeZone rule for Europe/Rome including daylight adjustment rules (optional)
+
+/* Time structure */
+struct tm timeinfo;
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Initialize Wi-Fi and connect to AP
+  WiFi.begin(ssid, password);
+  esp_sntp_servermode_dhcp(1);  // (optional)
+
+  Serial.print("Connecting to WiFi");
+
+  while (WiFi.status() != WL_CONNECTED) {
+    delay(500);
+    Serial.print(".");
+  }
+  Serial.println("WiFi connected");
+
+  // Initialize Zigbee and Begin Zigbee stack
+  // Optional: set Zigbee device name and model
+  zbGateway.setManufacturerAndModel("Espressif", "ZigbeeGateway");
+  zbGateway.addTimeCluster(timeinfo, gmtOffset_sec);
+
+  // Add endpoint to Zigbee Core
+  Serial.println("Adding Zigbee Gateway endpoint");
+  Zigbee.addEndpoint(&zbGateway);
+
+  // Optional: Open network for 180 seconds after boot
+  Zigbee.setRebootOpenNetwork(180);
+
+  // Set custom radio configuration for RCP communication
+  esp_zb_radio_config_t radio_config = ZIGBEE_DEFAULT_UART_RCP_RADIO_CONFIG();
+  radio_config.radio_uart_config.port = GATEWAY_RCP_UART_PORT;
+  radio_config.radio_uart_config.rx_pin = (gpio_num_t)GATEWAY_RCP_RX_PIN;
+  radio_config.radio_uart_config.tx_pin = (gpio_num_t)GATEWAY_RCP_TX_PIN;
+
+  Zigbee.setRadioConfig(radio_config);
+
+  // When all EPs are registered, start Zigbee with ZIGBEE_COORDINATOR or ZIGBEE_ROUTER mode
+  if (!Zigbee.begin(ZIGBEE_COORDINATOR)) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+
+  // set notification call-back function
+  sntp_set_time_sync_notification_cb(timeavailable);
+  sntp_set_sync_interval(30000);  // sync every 30 seconds
+
+  // config time zone and NTP servers
+  configTime(gmtOffset_sec, daylightOffset_sec, ntpServer1, ntpServer2);
+}
+
+void loop() {
+  // Nothing to do here in this example
+}
+
+void printLocalTime() {
+  if (!getLocalTime(&timeinfo)) {
+    Serial.println("No time available (yet)");
+    return;
+  }
+  Serial.println(&timeinfo, "%A, %B %d %Y %H:%M:%S");
+  zbGateway.setTime(timeinfo);
+  Serial.println("Time updated in Zigbee Gateway");
+}
+
+// Callback function (gets called when time adjusts via NTP)
+void timeavailable(struct timeval *t) {
+  Serial.println("Got time adjustment from NTP!");
+  printLocalTime();
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Gateway/ci.json b/libraries/Zigbee/examples/Zigbee_Gateway/ci.json
new file mode 100644
index 00000000000..23e1c59d1da
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Gateway/ci.json
@@ -0,0 +1,10 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee_zczr_8MB,ZigbeeMode=zczr",
+  "requires": [
+    "CONFIG_ZB_ENABLED=y"
+  ],
+  "targets": {
+    "esp32c6": false,
+    "esp32h2": false
+  }
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/README.md
new file mode 100644
index 00000000000..fe723696d5a
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/README.md
@@ -0,0 +1,78 @@
+# Arduino-ESP32 Zigbee Illuminance Sensor Example
+
+This example demonstrates how to use the Zigbee library to create an end device illuminance sensor and use it as a Home Automation (HA) extended illuminance sensor.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Illuminance Sensor Functions
+
+1. Initialize a Zigbee illuminance sensor.
+2. Measure illuminance value.
+3. Report the measured value to the Zigbee network.
+
+## Hardware Required
+
+* ESP32-H2 or ESP32-C6 development board
+* A USB cable for power supply and programming
+* Some kind of light sensor, such as a photoresistor
+
+### Configure the Project
+
+In this example the raw analog value of a light sensor is used to calculate illuminance.
+Alter the calculation according to your use case and calibrate it to receive correct lux values.
+Set the illuminance sensor GPIO by changing the `illuminance_sensor_pin` variable to the pin to the pin to which your sensor is connected.
+Set the button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Enable USB CDC to be able to use the serial monitor: `Tools -> USB CDC On Boot: Enabled`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure that you are using a good quality USB cable with data lines and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/Zigbee_Illuminance_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/Zigbee_Illuminance_Sensor.ino
new file mode 100644
index 00000000000..bbb2cba569f
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/Zigbee_Illuminance_Sensor.ino
@@ -0,0 +1,141 @@
+// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee illuminance sensor.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device illuminance sensor.
+ * The illuminance sensor is a Zigbee end device, which is controlled by a Zigbee coordinator.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by MikaFromTheRoof (https://github.com/MikaFromTheRoof)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+#define ZIGBEE_ILLUMINANCE_SENSOR_ENDPOINT 9
+uint8_t button = BOOT_PIN;
+uint8_t illuminance_sensor_pin = 6;  // Insert the analog pin to which the sensor (e.g. photoresistor) is connected
+
+ZigbeeIlluminanceSensor zbIlluminanceSensor = ZigbeeIlluminanceSensor(ZIGBEE_ILLUMINANCE_SENSOR_ENDPOINT);
+
+/********************* Illuminance sensor **************************/
+static void illuminance_sensor_value_update(void *arg) {
+  for (;;) {
+    // read the raw analog value from the sensor
+    int lsens_analog_raw = analogRead(illuminance_sensor_pin);
+    Serial.printf("[Illuminance Sensor] raw analog value: %d\r\n", lsens_analog_raw);
+
+    // conversion into zigbee raw illuminance value (typically between 0 in darkness and 50000 in direct sunlight)
+    // depends on the value range of the raw analog sensor values and will need calibration for correct lux values
+    // for demonstration purpose map the 12-bit ADC value (0-4095) to Zigbee illuminance range (0-50000)
+    int lsens_illuminance_raw = map(lsens_analog_raw, 0, 4095, 0, 50000);
+    Serial.printf("[Illuminance Sensor] raw illuminance value: %d\r\n", lsens_illuminance_raw);
+
+    // according to zigbee documentation the formular 10^(lsens_illuminance_raw/10000)-1 can be used to calculate lux value from raw illuminance value
+    // Note: Zigbee2MQTT seems to be using the formular 10^(lsens_illuminance_raw/10000) instead (without -1)
+    int lsens_illuminance_lux = round(pow(10, (lsens_illuminance_raw / 10000.0)) - 1);
+    Serial.printf("[Illuminance Sensor] lux value: %d lux\r\n", lsens_illuminance_lux);
+
+    // Update illuminance in illuminance sensor EP
+    zbIlluminanceSensor.setIlluminance(lsens_illuminance_raw);  // use raw illuminance here!
+
+    delay(1000);  // reduce delay (in ms), if you want your device to react more quickly to changes in illuminance
+  }
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Optional: configure analog input
+  analogSetAttenuation(ADC_11db);  // set analog to digital converter (ADC) attenuation to 11 dB (up to ~3.3V input)
+  analogReadResolution(12);        // set analog read resolution to 12 bits (value range from 0 to 4095), 12 is default
+
+  // Init button for factory reset
+  pinMode(button, INPUT_PULLUP);
+
+  // Optional: Set Zigbee device name and model
+  zbIlluminanceSensor.setManufacturerAndModel("Espressif", "ZigbeeIlluminanceSensor");
+
+  // Optional: Set power source (choose between ZB_POWER_SOURCE_MAINS and ZB_POWER_SOURCE_BATTERY), defaults to unknown
+  zbIlluminanceSensor.setPowerSource(ZB_POWER_SOURCE_MAINS);
+
+  // Set minimum and maximum for raw illuminance value (0 min and 50000 max equals to 0 lux - 100,000 lux)
+  zbIlluminanceSensor.setMinMaxValue(0, 50000);
+
+  // Optional: Set tolerance for raw illuminance value
+  zbIlluminanceSensor.setTolerance(1);
+
+  // Add endpoint to Zigbee Core
+  Serial.println("Adding Zigbee illuminance sensor endpoint to Zigbee Core");
+  Zigbee.addEndpoint(&zbIlluminanceSensor);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+
+  // Start illuminance sensor reading task
+  xTaskCreate(illuminance_sensor_value_update, "illuminance_sensor_update", 2048, NULL, 10, NULL);
+
+  // Set reporting schedule for illuminance value measurement in seconds, must be called after Zigbee.begin()
+  // min_interval and max_interval in seconds, delta
+  // if min = 1 and max = 0, delta = 1000, reporting is sent when raw illuminance value changes by 1000, but at most once per second
+  // if min = 0 and max = 10, delta = 1000, reporting is sent every 10 seconds or if raw illuminance value changes by 1000
+  // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of illuminance change
+  // Note: On pairing with Zigbee Home Automation or Zigbee2MQTT the reporting schedule will most likely be overwritten with their default settings
+  zbIlluminanceSensor.setReporting(1, 0, 1000);
+}
+
+/********************* Main loop **************************/
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3 secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    // force report of illuminance when button is pressed
+    zbIlluminanceSensor.report();
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/ci.json b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Illuminance_Sensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_OTA_Client/README.md b/libraries/Zigbee/examples/Zigbee_OTA_Client/README.md
new file mode 100644
index 00000000000..143ff946f28
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_OTA_Client/README.md
@@ -0,0 +1,68 @@
+# Arduino-ESP32 Zigbee OTA Client + on/off light Example
+
+This example shows how to configure the Zigbee end device with OTA Client and use it as a Home Automation (HA) on/off light.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+
+### Configure the Project
+
+Set the LED GPIO by changing the `LED_PIN` definition. By default, the LED_PIN is `RGB_BUILTIN`.
+By default, the `rgbLedWrite` function is used to control the LED. You can change it to digitalWrite to control a simple LED.
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_OTA_Client/Zigbee_OTA_Client.ino b/libraries/Zigbee/examples/Zigbee_OTA_Client/Zigbee_OTA_Client.ino
new file mode 100644
index 00000000000..29d114014b4
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_OTA_Client/Zigbee_OTA_Client.ino
@@ -0,0 +1,112 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates OTA support on light bulb.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device light bulb with OTA support.
+ * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee light bulb configuration */
+#define ZIGBEE_LIGHT_ENDPOINT 1
+uint8_t led = RGB_BUILTIN;
+uint8_t button = BOOT_PIN;
+
+/* Zigbee OTA configuration */
+#define OTA_UPGRADE_RUNNING_FILE_VERSION    0x01010100  // Increment this value when the running image is updated
+#define OTA_UPGRADE_DOWNLOADED_FILE_VERSION 0x01010101  // Increment this value when the downloaded image is updated
+#define OTA_UPGRADE_HW_VERSION              0x0101      // The hardware version, this can be used to differentiate between different hardware versions
+
+ZigbeeLight zbLight = ZigbeeLight(ZIGBEE_LIGHT_ENDPOINT);
+
+/********************* RGB LED functions **************************/
+void setLED(bool value) {
+  digitalWrite(led, value);
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Init LED and turn it OFF (if LED_PIN == RGB_BUILTIN, the rgbLedWrite() will be used under the hood)
+  pinMode(led, OUTPUT);
+  digitalWrite(led, LOW);
+
+  // Init button for factory reset
+  pinMode(button, INPUT_PULLUP);
+
+  // Optional: set Zigbee device name and model
+  zbLight.setManufacturerAndModel("Espressif", "ZBLightBulb");
+
+  // Set callback function for light change
+  zbLight.onLightChange(setLED);
+
+  // Add OTA client to the light bulb
+  zbLight.addOTAClient(OTA_UPGRADE_RUNNING_FILE_VERSION, OTA_UPGRADE_DOWNLOADED_FILE_VERSION, OTA_UPGRADE_HW_VERSION);
+
+  // Add endpoint to Zigbee Core
+  Serial.println("Adding ZigbeeLight endpoint to Zigbee Core");
+  Zigbee.addEndpoint(&zbLight);
+
+  // When all EPs are registered, start Zigbee. By default acts as ZIGBEE_END_DEVICE
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+
+  // Start Zigbee OTA client query, first request is within a minute and the next requests are sent every hour automatically
+  zbLight.requestOTAUpdate();
+}
+
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    // Toggle light by pressing the button
+    zbLight.setLight(!zbLight.getLightState());
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_OTA_Client/ci.json b/libraries/Zigbee/examples/Zigbee_OTA_Client/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_OTA_Client/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/README.md
new file mode 100644
index 00000000000..0c5dcd013f2
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/README.md
@@ -0,0 +1,57 @@
+# Arduino-ESP32 Zigbee Occupancy Sensor Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) occupancy sensor (PIR).
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+
+### Configure the Project
+
+Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+Set the Sensor GPIO by changing the `sensor_pin` variable.
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/Zigbee_Occupancy_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/Zigbee_Occupancy_Sensor.ino
new file mode 100644
index 00000000000..46afdf3d273
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/Zigbee_Occupancy_Sensor.ino
@@ -0,0 +1,103 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee occupancy sensor.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device occupancy sensor.
+ * The occupancy sensor is a Zigbee end device, which is reporting data to the Zigbee network.
+ * Tested with PIR sensor HC-SR501 connected to GPIO4.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee occupancy sensor configuration */
+#define OCCUPANCY_SENSOR_ENDPOINT_NUMBER 10
+uint8_t button = BOOT_PIN;
+uint8_t sensor_pin = 4;
+
+ZigbeeOccupancySensor zbOccupancySensor = ZigbeeOccupancySensor(OCCUPANCY_SENSOR_ENDPOINT_NUMBER);
+
+void setup() {
+  Serial.begin(115200);
+
+  // Init button + PIR sensor
+  pinMode(button, INPUT_PULLUP);
+  pinMode(sensor_pin, INPUT);
+
+  // Optional: set Zigbee device name and model
+  zbOccupancySensor.setManufacturerAndModel("Espressif", "ZigbeeOccupancyPIRSensor");
+
+  // Add endpoint to Zigbee Core
+  Zigbee.addEndpoint(&zbOccupancySensor);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+}
+
+void loop() {
+  // Checking PIR sensor for occupancy change
+  static bool occupancy = false;
+  if (digitalRead(sensor_pin) == HIGH && !occupancy) {
+    // Update occupancy sensor value
+    zbOccupancySensor.setOccupancy(true);
+    zbOccupancySensor.report();
+    occupancy = true;
+  } else if (digitalRead(sensor_pin) == LOW && occupancy) {
+    zbOccupancySensor.setOccupancy(false);
+    zbOccupancySensor.report();
+    occupancy = false;
+  }
+
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/ci.json b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Occupancy_Sensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Light/README.md b/libraries/Zigbee/examples/Zigbee_On_Off_Light/README.md
new file mode 100644
index 00000000000..e74c7505ddb
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_On_Off_Light/README.md
@@ -0,0 +1,70 @@
+# Arduino-ESP32 Zigbee On/Off Light Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) on/off light.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* One development board (ESP32-H2 or ESP32-C6) acting  as Zigbee coordinator (loaded with Zigbee_On_Off_switch example)
+* A USB cable for power supply and programming
+* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the Zigbee_On_Off_Light example
+
+### Configure the Project
+
+Set the LED GPIO by changing the `LED_PIN` definition. By default, the LED_PIN is `RGB_BUILTIN`.
+By default, the `rgbLedWrite` function is used to control the LED. You can change it to digitalWrite to control a simple LED.
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Light/Zigbee_On_Off_Light.ino b/libraries/Zigbee/examples/Zigbee_On_Off_Light/Zigbee_On_Off_Light.ino
new file mode 100644
index 00000000000..6db8bd7b022
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_On_Off_Light/Zigbee_On_Off_Light.ino
@@ -0,0 +1,101 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates simple Zigbee light bulb.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device light bulb.
+ * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee light bulb configuration */
+#define ZIGBEE_LIGHT_ENDPOINT 10
+uint8_t led = RGB_BUILTIN;
+uint8_t button = BOOT_PIN;
+
+ZigbeeLight zbLight = ZigbeeLight(ZIGBEE_LIGHT_ENDPOINT);
+
+/********************* RGB LED functions **************************/
+void setLED(bool value) {
+  digitalWrite(led, value);
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Init LED and turn it OFF (if LED_PIN == RGB_BUILTIN, the rgbLedWrite() will be used under the hood)
+  pinMode(led, OUTPUT);
+  digitalWrite(led, LOW);
+
+  // Init button for factory reset
+  pinMode(button, INPUT_PULLUP);
+
+  //Optional: set Zigbee device name and model
+  zbLight.setManufacturerAndModel("Espressif", "ZBLightBulb");
+
+  // Set callback function for light change
+  zbLight.onLightChange(setLED);
+
+  //Add endpoint to Zigbee Core
+  Serial.println("Adding ZigbeeLight endpoint to Zigbee Core");
+  Zigbee.addEndpoint(&zbLight);
+
+  // When all EPs are registered, start Zigbee. By default acts as ZIGBEE_END_DEVICE
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+}
+
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    // Toggle light by pressing the button
+    zbLight.setLight(!zbLight.getLightState());
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Light/ci.json b/libraries/Zigbee/examples/Zigbee_On_Off_Light/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_On_Off_Light/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Switch/README.md b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/README.md
new file mode 100644
index 00000000000..b70f57d6e89
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/README.md
@@ -0,0 +1,68 @@
+# Arduino-ESP32 Zigbee On/Off Light Switch Example
+
+This example shows how to configure Zigbee Coordinator and use it as a Home Automation (HA) on/off light switch.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee end device (loaded with Zigbee_On_Off_Light example).
+* A USB cable for power supply and programming.
+* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee coordinator and upload the Zigbee_On_Off_Switch example.
+
+### Configure the Project
+
+Set the Button Switch GPIO by changing the `GPIO_INPUT_IO_TOGGLE_SWITCH` definition. By default, it's the pin `9` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the Coordinator Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`.
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`.
+* Select the COM port: `Tools -> Port: xxx where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with the example `Zigbee_On_Off_Light` is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* In the `Zigbee_On_Off_Light` example sketch call `Zigbee.factoryReset();`.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Switch/Zigbee_On_Off_Switch.ino b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/Zigbee_On_Off_Switch.ino
new file mode 100644
index 00000000000..0721371ce0e
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/Zigbee_On_Off_Switch.ino
@@ -0,0 +1,198 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates simple Zigbee light switch.
+ *
+ * The example demonstrates how to use Zigbee library to control a light bulb.
+ * The light bulb is a Zigbee end device, which is controlled by a Zigbee coordinator (Switch).
+ * Button switch and Zigbee runs in separate tasks.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ZCZR
+#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee switch configuration */
+#define SWITCH_ENDPOINT_NUMBER 5
+
+#define GPIO_INPUT_IO_TOGGLE_SWITCH BOOT_PIN
+#define PAIR_SIZE(TYPE_STR_PAIR)    (sizeof(TYPE_STR_PAIR) / sizeof(TYPE_STR_PAIR[0]))
+
+typedef enum {
+  SWITCH_ON_CONTROL,
+  SWITCH_OFF_CONTROL,
+  SWITCH_ONOFF_TOGGLE_CONTROL,
+  SWITCH_LEVEL_UP_CONTROL,
+  SWITCH_LEVEL_DOWN_CONTROL,
+  SWITCH_LEVEL_CYCLE_CONTROL,
+  SWITCH_COLOR_CONTROL,
+} SwitchFunction;
+
+typedef struct {
+  uint8_t pin;
+  SwitchFunction func;
+} SwitchData;
+
+typedef enum {
+  SWITCH_IDLE,
+  SWITCH_PRESS_ARMED,
+  SWITCH_PRESS_DETECTED,
+  SWITCH_PRESSED,
+  SWITCH_RELEASE_DETECTED,
+} SwitchState;
+
+static SwitchData buttonFunctionPair[] = {{GPIO_INPUT_IO_TOGGLE_SWITCH, SWITCH_ONOFF_TOGGLE_CONTROL}};
+
+ZigbeeSwitch zbSwitch = ZigbeeSwitch(SWITCH_ENDPOINT_NUMBER);
+
+/********************* Zigbee functions **************************/
+static void onZbButton(SwitchData *button_func_pair) {
+  if (button_func_pair->func == SWITCH_ONOFF_TOGGLE_CONTROL) {
+    // Send toggle command to the light
+    Serial.println("Toggling light");
+    zbSwitch.lightToggle();
+  }
+}
+
+/********************* GPIO functions **************************/
+static QueueHandle_t gpio_evt_queue = NULL;
+
+static void IRAM_ATTR onGpioInterrupt(void *arg) {
+  xQueueSendFromISR(gpio_evt_queue, (SwitchData *)arg, NULL);
+}
+
+static void enableGpioInterrupt(bool enabled) {
+  for (int i = 0; i < PAIR_SIZE(buttonFunctionPair); ++i) {
+    if (enabled) {
+      enableInterrupt((buttonFunctionPair[i]).pin);
+    } else {
+      disableInterrupt((buttonFunctionPair[i]).pin);
+    }
+  }
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  //Optional: set Zigbee device name and model
+  zbSwitch.setManufacturerAndModel("Espressif", "ZigbeeSwitch");
+
+  //Optional to allow multiple light to bind to the switch
+  zbSwitch.allowMultipleBinding(true);
+
+  //Add endpoint to Zigbee Core
+  Serial.println("Adding ZigbeeSwitch endpoint to Zigbee Core");
+  Zigbee.addEndpoint(&zbSwitch);
+
+  //Open network for 180 seconds after boot
+  Zigbee.setRebootOpenNetwork(180);
+
+  // Init button switch
+  for (int i = 0; i < PAIR_SIZE(buttonFunctionPair); i++) {
+    pinMode(buttonFunctionPair[i].pin, INPUT_PULLUP);
+    /* create a queue to handle gpio event from isr */
+    gpio_evt_queue = xQueueCreate(10, sizeof(SwitchData));
+    if (gpio_evt_queue == 0) {
+      Serial.println("Queue creating failed, rebooting...");
+      ESP.restart();
+    }
+    attachInterruptArg(buttonFunctionPair[i].pin, onGpioInterrupt, (void *)(buttonFunctionPair + i), FALLING);
+  }
+
+  // When all EPs are registered, start Zigbee with ZIGBEE_COORDINATOR mode
+  if (!Zigbee.begin(ZIGBEE_COORDINATOR)) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+
+  Serial.println("Waiting for Light to bound to the switch");
+  //Wait for switch to bound to a light:
+  while (!zbSwitch.bound()) {
+    Serial.printf(".");
+    delay(500);
+  }
+
+  // Optional: List all bound devices and read manufacturer and model name
+  std::list<zb_device_params_t *> boundLights = zbSwitch.getBoundDevices();
+  for (const auto &device : boundLights) {
+    Serial.printf("Device on endpoint %d, short address: 0x%x\r\n", device->endpoint, device->short_addr);
+    Serial.printf(
+      "IEEE Address: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\r\n", device->ieee_addr[7], device->ieee_addr[6], device->ieee_addr[5], device->ieee_addr[4],
+      device->ieee_addr[3], device->ieee_addr[2], device->ieee_addr[1], device->ieee_addr[0]
+    );
+    char *manufacturer = zbSwitch.readManufacturer(device->endpoint, device->short_addr, device->ieee_addr);
+    char *model = zbSwitch.readModel(device->endpoint, device->short_addr, device->ieee_addr);
+    if (manufacturer != nullptr) {
+      Serial.printf("Light manufacturer: %s\r\n", manufacturer);
+    }
+    if (model != nullptr) {
+      Serial.printf("Light model: %s\r\n", model);
+    }
+  }
+
+  Serial.println();
+}
+
+void loop() {
+  // Handle button switch in loop()
+  uint8_t pin = 0;
+  SwitchData buttonSwitch;
+  static SwitchState buttonState = SWITCH_IDLE;
+  bool eventFlag = false;
+
+  /* check if there is any queue received, if yes read out the buttonSwitch */
+  if (xQueueReceive(gpio_evt_queue, &buttonSwitch, portMAX_DELAY)) {
+    pin = buttonSwitch.pin;
+    enableGpioInterrupt(false);
+    eventFlag = true;
+  }
+  while (eventFlag) {
+    bool value = digitalRead(pin);
+    switch (buttonState) {
+      case SWITCH_IDLE:           buttonState = (value == LOW) ? SWITCH_PRESS_DETECTED : SWITCH_IDLE; break;
+      case SWITCH_PRESS_DETECTED: buttonState = (value == LOW) ? SWITCH_PRESS_DETECTED : SWITCH_RELEASE_DETECTED; break;
+      case SWITCH_RELEASE_DETECTED:
+        buttonState = SWITCH_IDLE;
+        /* callback to button_handler */
+        (*onZbButton)(&buttonSwitch);
+        break;
+      default: break;
+    }
+    if (buttonState == SWITCH_IDLE) {
+      enableGpioInterrupt(true);
+      eventFlag = false;
+      break;
+    }
+    vTaskDelay(10 / portTICK_PERIOD_MS);
+  }
+
+  // print the bound lights every 10 seconds
+  static uint32_t lastPrint = 0;
+  if (millis() - lastPrint > 10000) {
+    lastPrint = millis();
+    zbSwitch.printBoundDevices(Serial);
+  }
+}
diff --git a/libraries/Zigbee/examples/Zigbee_On_Off_Switch/ci.json b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/ci.json
new file mode 100644
index 00000000000..15d6190e4ae
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_On_Off_Switch/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee_zczr,ZigbeeMode=zczr",
+  "requires": [
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_PM25_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/README.md
new file mode 100644
index 00000000000..51bf11459b7
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/README.md
@@ -0,0 +1,72 @@
+# Arduino-ESP32 PM2.5 Sensor
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) simple sensor device type with particulate matter (PM2.5) measuring
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Pressure + Flow Sensor Functions
+
+ * After this board first starts up, it would be configured locally to report the PM2.5 on every 30 seconds.
+ * By clicking the button (BOOT) on this board, this board will immediately send a report of the current PM2.5 to the network.
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+
+### Configure the Project
+
+In this example, the internal temperature sensor is used to demonstrate reading of the PM2.5 sensors.
+Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_PM25_Sensor/Zigbee_PM25_Sensor.ino b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/Zigbee_PM25_Sensor.ino
new file mode 100644
index 00000000000..a98d697f700
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/Zigbee_PM25_Sensor.ino
@@ -0,0 +1,109 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee PM2.5 sensor.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device PM2.5 sensor.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee PM2.5 sensor configuration */
+#define PM2_5_SENSOR_ENDPOINT_NUMBER 1
+uint8_t button = BOOT_PIN;
+
+ZigbeePM25Sensor zbPM25Sensor = ZigbeePM25Sensor(PM2_5_SENSOR_ENDPOINT_NUMBER);
+
+void setup() {
+  Serial.begin(115200);
+
+  // Init button switch
+  pinMode(button, INPUT_PULLUP);
+
+  // Optional: set Zigbee device name and model
+  zbPM25Sensor.setManufacturerAndModel("Espressif", "ZigbeePM25Sensor");
+
+  // Set minimum and maximum PM2.5 measurement value in µg/m³
+  zbPM25Sensor.setMinMaxValue(0, 350);
+
+  // Set tolerance for PM2.5 measurement in µg/m³
+  zbPM25Sensor.setTolerance(0.1);
+
+  // Add endpoints to Zigbee Core
+  Zigbee.addEndpoint(&zbPM25Sensor);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+
+  // Set reporting interval for PM2.5 measurement to be done every 30 seconds, must be called after Zigbee.begin()
+  // min_interval and max_interval in seconds, delta (PM2.5 change in µg/m³)
+  // if min = 1 and max = 0, reporting is sent only when PM2.5 changes by delta
+  // if min = 0 and max = 10, reporting is sent every 10 seconds or when PM2.5 changes by delta
+  // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of delta change
+  zbPM25Sensor.setReporting(0, 30, 0);
+}
+
+void loop() {
+  static uint32_t timeCounter = 0;
+  // Read PM2.5 sensor every 2s
+  if (!(timeCounter++ % 20)) {  // delaying for 100ms x 20 = 2s
+    // Read sensor value - here is chip temperature used + 50 as a dummy value for demonstration
+    float pm25_value = 50.5 + temperatureRead();
+    Serial.printf("Updating PM2.5 sensor value to %0.1f µg/m³\r\n", pm25_value);
+    zbPM25Sensor.setPM25(pm25_value);
+  }
+
+  // Checking button for factory reset and reporting
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    zbPM25Sensor.report();
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_PM25_Sensor/ci.json b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_PM25_Sensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/README.md
new file mode 100644
index 00000000000..964c7503027
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/README.md
@@ -0,0 +1,72 @@
+# Arduino-ESP32 Zigbee Pressure + Flow Sensor Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) simple sensor device type with pressure and flow measuring.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Pressure + Flow Sensor Functions
+
+ * After this board first starts up, it would be configured locally to report the pressure and flow on change or every 30 seconds.
+ * By clicking the button (BOOT) on this board, this board will immediately send a report of the current measured flow and pressure to the network.
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+
+### Configure the Project
+
+In this example, the internal temperature sensor is used to demonstrate reading of the flow and pressure sensors.
+Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/Zigbee_Pressure_Flow_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/Zigbee_Pressure_Flow_Sensor.ino
new file mode 100644
index 00000000000..a652a22c493
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/Zigbee_Pressure_Flow_Sensor.ino
@@ -0,0 +1,128 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee temperature sensor.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device temperature sensor.
+ * The temperature sensor is a Zigbee end device, which is controlled by a Zigbee coordinator.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee flow + pressure sensor configuration */
+#define FLOW_SENSOR_ENDPOINT_NUMBER     10
+#define PRESSURE_SENSOR_ENDPOINT_NUMBER 11
+
+uint8_t button = BOOT_PIN;
+
+ZigbeeFlowSensor zbFlowSensor = ZigbeeFlowSensor(FLOW_SENSOR_ENDPOINT_NUMBER);
+ZigbeePressureSensor zbPressureSensor = ZigbeePressureSensor(PRESSURE_SENSOR_ENDPOINT_NUMBER);
+
+void setup() {
+  Serial.begin(115200);
+
+  // Init button switch
+  pinMode(button, INPUT_PULLUP);
+
+  // Optional: set Zigbee device name and model
+  zbFlowSensor.setManufacturerAndModel("Espressif", "ZigbeeFlowSensor");
+
+  // Set minimum and maximum flow measurement value in 0,1 m3/h
+  zbFlowSensor.setMinMaxValue(0.0, 100.0);
+
+  // Optional: Set tolerance for flow measurement in 0,1 m3/h
+  zbFlowSensor.setTolerance(1.0);
+
+  // Optional: set Zigbee device name and model
+  zbPressureSensor.setManufacturerAndModel("Espressif", "ZigbeePressureSensor");
+
+  // Set minimum and maximum pressure measurement value in hPa
+  zbPressureSensor.setMinMaxValue(0, 10000);
+
+  // Optional: Set tolerance for pressure measurement in hPa
+  zbPressureSensor.setTolerance(1);
+
+  // Add endpoints to Zigbee Core
+  Zigbee.addEndpoint(&zbFlowSensor);
+  Zigbee.addEndpoint(&zbPressureSensor);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+
+  // Set reporting interval for flow and pressure measurement in seconds, must be called after Zigbee.begin()
+  // min_interval and max_interval in seconds, delta (pressure change in hPa, flow change in 0,1 m3/h)
+  // if min = 1 and max = 0, reporting is sent only when temperature changes by delta
+  // if min = 0 and max = 10, reporting is sent every 10 seconds or temperature changes by delta
+  // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of delta change
+  zbFlowSensor.setReporting(0, 30, 1.0);
+  zbPressureSensor.setReporting(0, 30, 1);
+}
+
+void loop() {
+  static uint32_t timeCounter = 0;
+
+  // Read flow and pressure sensors every 2s
+  if (!(timeCounter++ % 20)) {  // delaying for 100ms x 20 = 2s
+    float flow_value = temperatureRead();
+    uint16_t pressure_value = (uint16_t)temperatureRead() * 100;  //*100 for demonstration so the value is in 1000-3000hPa
+    Serial.printf("Updating flow sensor value to %.2f m3/h\r\n", flow_value);
+    zbFlowSensor.setFlow(flow_value);
+    Serial.printf("Updating pressure sensor value to %d hPa\r\n", pressure_value);
+    zbPressureSensor.setPressure(pressure_value);
+  }
+
+  // Checking button for factory reset and reporting
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    zbFlowSensor.report();
+    zbPressureSensor.report();
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/ci.json b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Pressure_Flow_Sensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Range_Extender/README.md b/libraries/Zigbee/examples/Zigbee_Range_Extender/README.md
new file mode 100644
index 00000000000..198dd85b6ee
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Range_Extender/README.md
@@ -0,0 +1,68 @@
+# Arduino-ESP32 Zigbee Range Extender (Router) Example
+
+This example shows how to configure the Zigbee Router device and use it as a Home Automation (HA) network range extender.
+
+To see if the communication with your Zigbee network works, use the Serial monitor and watch for output there.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+* Board (ESP32-H2 or ESP32-C6) as Zigbee router device and upload the Zigbee_Range_Extender example
+* Zigbee network / coordinator (Other board with switch examples or Zigbee2mqtt or ZigbeeHomeAssistant like application)
+
+### Configure the Project
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the Coordinator/Router device Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs` (select correct size)
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the Router device flashed with this example is not connecting to the coordinator, erase the flash of the Router device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Range_Extender/Zigbee_Range_Extender.ino b/libraries/Zigbee/examples/Zigbee_Range_Extender/Zigbee_Range_Extender.ino
new file mode 100644
index 00000000000..a1ba90fbaf6
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Range_Extender/Zigbee_Range_Extender.ino
@@ -0,0 +1,120 @@
+// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates simple Zigbee Range Extender (router).
+ *
+ * The example demonstrates how to use Zigbee library to create a Zigbee network ragbe extender (router).
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ZCZR
+#error "Zigbee coordinator/router mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee light bulb configuration */
+#define USE_CUSTOM_ZIGBEE_CONFIG 1
+#define ZIGBEE_EXTENDER_ENDPOINT 1
+
+#ifndef LED_BUILTIN
+#define LED_BUILTIN 4
+#endif
+
+uint8_t led = LED_BUILTIN;
+uint8_t button = BOOT_PIN;
+
+ZigbeeRangeExtender zbExtender = ZigbeeRangeExtender(ZIGBEE_EXTENDER_ENDPOINT);
+
+/************************** Identify ******************************/
+// Create a task on identify call to handle the identify function
+void identify(uint16_t time) {
+  static uint8_t blink = 1;
+  log_d("Identify called for %d seconds", time);
+  if (time == 0) {
+    digitalWrite(led, LOW);
+    return;
+  }
+  digitalWrite(led, blink);
+  blink = !blink;
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Init LED and turn it OFF (if LED_PIN == RGB_BUILTIN, the rgbLedWrite() will be used under the hood)
+  pinMode(led, OUTPUT);
+  digitalWrite(led, LOW);
+
+  // Init button for factory reset
+  pinMode(button, INPUT_PULLUP);
+
+  // Optional: Set callback function for device identify
+  zbExtender.onIdentify(identify);
+
+  // Optional: Set Zigbee device name and model
+  zbExtender.setManufacturerAndModel("Espressif", "ZigbeeRangeExtender");
+
+  // Add endpoint to Zigbee Core
+  Serial.println("Adding Zigbee Extender endpoint to Zigbee Core");
+  Zigbee.addEndpoint(&zbExtender);
+
+#if USE_CUSTOM_ZIGBEE_CONFIG
+  // Optional: Create a custom Zigbee configuration for Zigbee Extender
+  esp_zb_cfg_t zigbeeConfig = ZIGBEE_DEFAULT_ROUTER_CONFIG();
+  zigbeeConfig.nwk_cfg.zczr_cfg.max_children = 20;  // 10 is default
+
+  // When all EPs are registered, start Zigbee with custom config
+  if (!Zigbee.begin(&zigbeeConfig)) {
+#else
+  // When all EPs are registered, start Zigbee as ROUTER device
+  if (!Zigbee.begin(ZIGBEE_ROUTER)) {
+#endif
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+}
+
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+  }
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Range_Extender/ci.json b/libraries/Zigbee/examples/Zigbee_Range_Extender/ci.json
new file mode 100644
index 00000000000..15d6190e4ae
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Range_Extender/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee_zczr,ZigbeeMode=zczr",
+  "requires": [
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Scan_Networks/README.md b/libraries/Zigbee/examples/Zigbee_Scan_Networks/README.md
new file mode 100644
index 00000000000..0b2b2f94695
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Scan_Networks/README.md
@@ -0,0 +1,71 @@
+# Arduino-ESP32 Zigbee Networks Scan Example
+
+This example shows how to scan Zigbee Networks.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Example Output
+
+    Setup done
+    Loop running...
+    Loop running...
+    Loop running...
+    Loop running...
+
+    Scan done
+    2 networks found:
+    Nr | PAN ID | CH | Permit Joining | Router Capacity | End Device Capacity | Extended PAN ID
+     1 | 0xe6f0 | 14 | Yes            | Yes             | Yes                 | f0:f5:bd:ff:fe:02:3f:24
+     2 | 0xa9bb | 24 | No             | Yes             | Yes                 | 60:55:f9:00:00:f7:52:d0
+
+## Hardware Required
+
+* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee coordinator (loaded with `Zigbee_Thermostat` example)
+* A USB cable for power supply and programming
+* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee end device (loaded with `Zigbee_Temperature_Sensor` example)
+
+### Configure the Project
+
+In this example, the internal temperature sensor task is reading the chip temperature.
+Set the Button Switch GPIO by changing the `GPIO_INPUT_IO_TOGGLE_SWITCH` definition. By default, it's the `GPIO_NUM_9` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Scan_Networks/Zigbee_Scan_Networks.ino b/libraries/Zigbee/examples/Zigbee_Scan_Networks/Zigbee_Scan_Networks.ino
new file mode 100644
index 00000000000..eab6ecfd76e
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Scan_Networks/Zigbee_Scan_Networks.ino
@@ -0,0 +1,109 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee Network Scanning.
+ *
+ * The example demonstrates how to use ESP Zigbee stack to scan for Zigbee networks.
+ *
+ * Any Zigbee mode can be selected in Tools->Zigbee mode
+ * with proper Zigbee partition scheme in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#if !defined(ZIGBEE_MODE_ED) && !defined(ZIGBEE_MODE_ZCZR)
+#error "Zigbee device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+#ifdef ZIGBEE_MODE_ZCZR
+zigbee_role_t role = ZIGBEE_ROUTER;  // or can be ZIGBEE_COORDINATOR, but it won't scan itself
+#else
+zigbee_role_t role = ZIGBEE_END_DEVICE;
+#endif
+
+void printScannedNetworks(uint16_t networksFound) {
+  if (networksFound == 0) {
+    Serial.println("No networks found");
+  } else {
+    zigbee_scan_result_t *scan_result = Zigbee.getScanResult();
+    Serial.println("\nScan done");
+    Serial.print(networksFound);
+    Serial.println(" networks found:");
+    Serial.println("Nr | PAN ID | CH | Permit Joining | Router Capacity | End Device Capacity | Extended PAN ID");
+    for (int i = 0; i < networksFound; ++i) {
+      // Print all available info for each network found
+      Serial.printf("%2d", i + 1);
+      Serial.print(" | ");
+      Serial.printf("0x%04hx", scan_result[i].short_pan_id);
+      Serial.print(" | ");
+      Serial.printf("%2d", scan_result[i].logic_channel);
+      Serial.print(" | ");
+      Serial.printf("%-14.14s", scan_result[i].permit_joining ? "Yes" : "No");
+      Serial.print(" | ");
+      Serial.printf("%-15.15s", scan_result[i].router_capacity ? "Yes" : "No");
+      Serial.print(" | ");
+      Serial.printf("%-19.19s", scan_result[i].end_device_capacity ? "Yes" : "No");
+      Serial.print(" | ");
+      Serial.printf(
+        "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", scan_result[i].extended_pan_id[7], scan_result[i].extended_pan_id[6], scan_result[i].extended_pan_id[5],
+        scan_result[i].extended_pan_id[4], scan_result[i].extended_pan_id[3], scan_result[i].extended_pan_id[2], scan_result[i].extended_pan_id[1],
+        scan_result[i].extended_pan_id[0]
+      );
+      Serial.println();
+      delay(10);
+    }
+    Serial.println("");
+    // Delete the scan result to free memory for code below.
+    Zigbee.scanDelete();
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  // Initialize Zigbee stack without any EPs just for scanning
+  if (!Zigbee.begin(role)) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+
+  Serial.println("Setup done, starting Zigbee network scan...");
+  // Start Zigbee Network Scan with default parameters (all channels, scan time 5)
+  Zigbee.scanNetworks();
+}
+
+void loop() {
+  // check Zigbee Network Scan process
+  int16_t ZigbeeScanStatus = Zigbee.scanComplete();
+  if (ZigbeeScanStatus < 0) {  // it is busy scanning or got an error
+    if (ZigbeeScanStatus == ZB_SCAN_FAILED) {
+      Serial.println("Zigbee scan has failed. Starting again.");
+      Zigbee.scanNetworks();
+    }
+    // other option is status ZB_SCAN_RUNNING - just wait.
+  } else {  // Found Zero or more Wireless Networks
+    printScannedNetworks(ZigbeeScanStatus);
+    Zigbee.scanNetworks();  // start over...
+  }
+
+  // Loop can do something else...
+  delay(500);
+  Serial.println("Loop running...");
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Scan_Networks/ci.json b/libraries/Zigbee/examples/Zigbee_Scan_Networks/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Scan_Networks/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/README.md b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/README.md
new file mode 100644
index 00000000000..afaa12c0bfa
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/README.md
@@ -0,0 +1,75 @@
+# Arduino-ESP32 Zigbee Temperature and Humidity Sensor Sleepy Device Example
+
+This example demonstrates how to use the Zigbee library to create an end device temperature/humidity sensor and use it as a Home Automation (HA) extended temperature sensor.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Temperature Sensor Functions
+
+1. Initialize a Zigbee temperature and humidity sensor.
+2. Measure temperature and humidity values.
+3. Report the measured values to the Zigbee network.
+4. Put the device to sleep to save power.
+
+## Hardware Required
+
+* ESP32-H2 or ESP32-C6 development board
+* A USB cable for power supply and programming
+
+### Configure the Project
+
+In this example, to demonstrate the functionality the chip temperature is used and reported as temperature and humidity.
+Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/Zigbee_Temp_Hum_Sensor_Sleepy.ino b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/Zigbee_Temp_Hum_Sensor_Sleepy.ino
new file mode 100644
index 00000000000..e9d08d32175
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/Zigbee_Temp_Hum_Sensor_Sleepy.ino
@@ -0,0 +1,147 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee temperature and humidity sensor Sleepy device.
+ *
+ * The example demonstrates how to use Zigbee library to create an end device temperature and humidity sensor.
+ * The sensor is a Zigbee end device, which is reporting data to the Zigbee network.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee temperature + humidity sensor configuration */
+#define TEMP_SENSOR_ENDPOINT_NUMBER 10
+
+#define uS_TO_S_FACTOR 1000000ULL /* Conversion factor for micro seconds to seconds */
+#define TIME_TO_SLEEP  55         /* Sleep for 55s will + 5s delay for establishing connection => data reported every 1 minute */
+
+uint8_t button = BOOT_PIN;
+
+ZigbeeTempSensor zbTempSensor = ZigbeeTempSensor(TEMP_SENSOR_ENDPOINT_NUMBER);
+
+/************************ Temp sensor *****************************/
+void meausureAndSleep() {
+  // Measure temperature sensor value
+  float temperature = temperatureRead();
+
+  // Use temperature value as humidity value to demonstrate both temperature and humidity
+  float humidity = temperature;
+
+  // Update temperature and humidity values in Temperature sensor EP
+  zbTempSensor.setTemperature(temperature);
+  zbTempSensor.setHumidity(humidity);
+
+  // Report temperature and humidity values
+  zbTempSensor.report();
+  Serial.printf("Reported temperature: %.2f°C, Humidity: %.2f%%\r\n", temperature, humidity);
+
+  // Add small delay to allow the data to be sent before going to sleep
+  delay(100);
+
+  // Put device to deep sleep
+  Serial.println("Going to sleep now");
+  esp_deep_sleep_start();
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Init button switch
+  pinMode(button, INPUT_PULLUP);
+
+  // Configure the wake up source and set to wake up every 5 seconds
+  esp_sleep_enable_timer_wakeup(TIME_TO_SLEEP * uS_TO_S_FACTOR);
+
+  // Optional: set Zigbee device name and model
+  zbTempSensor.setManufacturerAndModel("Espressif", "SleepyZigbeeTempSensor");
+
+  // Set minimum and maximum temperature measurement value (10-50°C is default range for chip temperature measurement)
+  zbTempSensor.setMinMaxValue(10, 50);
+
+  // Set tolerance for temperature measurement in °C (lowest possible value is 0.01°C)
+  zbTempSensor.setTolerance(1);
+
+  // Set power source to battery, battery percentage and battery voltage (now 100% and 3.5V for demonstration)
+  // The value can be also updated by calling zbTempSensor.setBatteryPercentage(percentage) or zbTempSensor.setBatteryVoltage(voltage) anytime after Zigbee.begin()
+  zbTempSensor.setPowerSource(ZB_POWER_SOURCE_BATTERY, 100, 35);
+
+  // Add humidity cluster to the temperature sensor device with min, max and tolerance values
+  zbTempSensor.addHumiditySensor(0, 100, 1);
+
+  // Add endpoint to Zigbee Core
+  Zigbee.addEndpoint(&zbTempSensor);
+
+  // Create a custom Zigbee configuration for End Device with keep alive 10s to avoid interference with reporting data
+  esp_zb_cfg_t zigbeeConfig = ZIGBEE_DEFAULT_ED_CONFIG();
+  zigbeeConfig.nwk_cfg.zed_cfg.keep_alive = 10000;
+
+  // For battery powered devices, it can be better to set timeout for Zigbee Begin to lower value to save battery
+  // If the timeout has been reached, the network channel mask will be reset and the device will try to connect again after reset (scanning all channels)
+  Zigbee.setTimeout(10000);  // Set timeout for Zigbee Begin to 10s (default is 30s)
+
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin(&zigbeeConfig, false)) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();  // If Zigbee failed to start, reboot the device and try again
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+  Serial.println("Successfully connected to Zigbee network");
+
+  // Delay approx 1s (may be adjusted) to allow establishing proper connection with coordinator, needed for sleepy devices
+  delay(1000);
+}
+
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 10000) {
+        // If key pressed for more than 10secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        // Optional set reset in factoryReset to false, to not restart device after erasing nvram, but set it to endless sleep manually instead
+        Zigbee.factoryReset(false);
+        Serial.println("Going to endless sleep, press RESET button or power off/on the device to wake up");
+        esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TIMER);
+        esp_deep_sleep_start();
+      }
+    }
+  }
+
+  // Call the function to measure temperature and put the device to sleep
+  meausureAndSleep();
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/ci.json b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Temp_Hum_Sensor_Sleepy/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/README.md
new file mode 100644
index 00000000000..577bd7c8058
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/README.md
@@ -0,0 +1,79 @@
+# Arduino-ESP32 Zigbee Temperature Sensor Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) temperature sensor.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Temperature Sensor Functions
+
+Note:
+ * This board means the board (e.g. ESP32-H2 / C6) loaded with `Zigbee_Temperature_Sensor` example.
+ * The remote board means the board (e.g. ESP32-H2 / C6) loaded with `Zigbee_Thermostat` example.
+
+Functions:
+ * After this board first starts up, it would be configured locally to report the temperature on 1 degree change and no periodic reporting to the remote board.
+ * By clicking the button (BOOT) on this board, this board will immediately send a report of the current measured temperature to the remote board.
+
+## Hardware Required
+
+* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee coordinator (loaded with `Zigbee_Thermostat` example)
+* A USB cable for power supply and programming
+* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the `Zigbee_Temperature_Sensor` example
+
+### Configure the Project
+
+In this example, the internal temperature sensor task is reading the chip temperature.
+Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/Zigbee_Temperature_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/Zigbee_Temperature_Sensor.ino
new file mode 100644
index 00000000000..ad007abbbaa
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/Zigbee_Temperature_Sensor.ino
@@ -0,0 +1,138 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee temperature sensor.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device temperature sensor.
+ * The temperature sensor is a Zigbee end device, which is controlled by a Zigbee coordinator.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee temperature sensor configuration */
+#define TEMP_SENSOR_ENDPOINT_NUMBER 10
+uint8_t button = BOOT_PIN;
+
+// Optional Time cluster variables
+struct tm timeinfo;
+struct tm *localTime;
+int32_t timezone;
+
+ZigbeeTempSensor zbTempSensor = ZigbeeTempSensor(TEMP_SENSOR_ENDPOINT_NUMBER);
+
+/************************ Temp sensor *****************************/
+static void temp_sensor_value_update(void *arg) {
+  for (;;) {
+    // Read temperature sensor value
+    float tsens_value = temperatureRead();
+    Serial.printf("Updated temperature sensor value to %.2f°C\r\n", tsens_value);
+    // Update temperature value in Temperature sensor EP
+    zbTempSensor.setTemperature(tsens_value);
+    delay(1000);
+  }
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Init button switch
+  pinMode(button, INPUT_PULLUP);
+
+  // Optional: set Zigbee device name and model
+  zbTempSensor.setManufacturerAndModel("Espressif", "ZigbeeTempSensor");
+
+  // Set minimum and maximum temperature measurement value (10-50°C is default range for chip temperature measurement)
+  zbTempSensor.setMinMaxValue(10, 50);
+
+  // Optional: Set tolerance for temperature measurement in °C (lowest possible value is 0.01°C)
+  zbTempSensor.setTolerance(1);
+
+  // Optional: Time cluster configuration (default params, as this device will revieve time from coordinator)
+  zbTempSensor.addTimeCluster();
+
+  // Add endpoint to Zigbee Core
+  Zigbee.addEndpoint(&zbTempSensor);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+
+  // Optional: If time cluster is added, time can be read from the coordinator
+  timeinfo = zbTempSensor.getTime();
+  timezone = zbTempSensor.getTimezone();
+
+  Serial.println("UTC time:");
+  Serial.println(&timeinfo, "%A, %B %d %Y %H:%M:%S");
+
+  time_t local = mktime(&timeinfo) + timezone;
+  localTime = localtime(&local);
+
+  Serial.println("Local time with timezone:");
+  Serial.println(localTime, "%A, %B %d %Y %H:%M:%S");
+
+  // Start Temperature sensor reading task
+  xTaskCreate(temp_sensor_value_update, "temp_sensor_update", 2048, NULL, 10, NULL);
+
+  // Set reporting interval for temperature measurement in seconds, must be called after Zigbee.begin()
+  // min_interval and max_interval in seconds, delta (temp change in 0,1 °C)
+  // if min = 1 and max = 0, reporting is sent only when temperature changes by delta
+  // if min = 0 and max = 10, reporting is sent every 10 seconds or temperature changes by delta
+  // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of temperature change
+  zbTempSensor.setReporting(1, 0, 1);
+}
+
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    zbTempSensor.reportTemperature();
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/ci.json b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Temperature_Sensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Thermostat/README.md b/libraries/Zigbee/examples/Zigbee_Thermostat/README.md
new file mode 100644
index 00000000000..e61173f6f4d
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Thermostat/README.md
@@ -0,0 +1,79 @@
+# Arduino-ESP32 Zigbee Thermostat Example
+
+This example shows how to configure Zigbee Coordinator and use it as a Home Automation (HA) thermostat.
+
+**This example is based on ESP-Zigbee-SDK example esp_zigbee_HA_sample/HA_thermostat.**
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Thermostat Functions
+
+Note:
+ * This board means the board (e.g. ESP32-H2) loaded with `Zigbee_Thermostat` example.
+ * The remote board means the board (e.g. ESP32-H2) loaded with `Zigbee_Temperature_Sensor` example.
+
+Functions:
+ * By clicking the button (BOOT) on this board, this board will read temperature value, temperature measurement range and temperature tolerance from the remote board. Also, this board will configure the remote board to report the measured temperature value every 10 seconds or every 2 degree changes.
+
+## Hardware Required
+
+* One development board (ESP32-H2 or ESP32-C6) acting as Zigbee end device (loaded with Zigbee_Temperature_Sensor example).
+* A USB cable for power supply and programming.
+* Choose another board (ESP32-H2 or ESP32-C6) as Zigbee coordinator (loaded with Zigbee_Thermostat example).
+
+### Configure the Project
+
+Set the Button GPIO by changing the `BUTTON_PIN` definition. By default, it's the pin `9` (BOOT button on ESP32-C6 and ESP32-H2).
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the Coordinator Zigbee mode: `Tools -> Zigbee mode: Zigbee ZCZR (coordinator/router)`.
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`.
+* Select the COM port: `Tools -> Port: xxx where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with the example `Zigbee_Temperature_Sensor` is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* In the `Zigbee_Temperature_Sensor` example sketch call `Zigbee.factoryReset();`.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Thermostat/Zigbee_Thermostat.ino b/libraries/Zigbee/examples/Zigbee_Thermostat/Zigbee_Thermostat.ino
new file mode 100644
index 00000000000..7cdf45ef711
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Thermostat/Zigbee_Thermostat.ino
@@ -0,0 +1,134 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates simple Zigbee thermostat.
+ *
+ * The example demonstrates how to use Zigbee library to get data from temperature
+ * sensor end device and act as an thermostat.
+ * The temperature sensor is a Zigbee end device, which is controlled by a Zigbee coordinator (thermostat).
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ZCZR
+#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee thermostat configuration */
+#define THERMOSTAT_ENDPOINT_NUMBER 5
+uint8_t button = BOOT_PIN;
+
+ZigbeeThermostat zbThermostat = ZigbeeThermostat(THERMOSTAT_ENDPOINT_NUMBER);
+
+// Save temperature sensor data
+float sensor_temp;
+float sensor_max_temp;
+float sensor_min_temp;
+float sensor_tolerance;
+
+struct tm timeinfo = {};  // Time structure for Time cluster
+
+/****************** Temperature sensor handling *******************/
+void recieveSensorTemp(float temperature) {
+  Serial.printf("Temperature sensor value: %.2f°C\n", temperature);
+  sensor_temp = temperature;
+}
+
+void recieveSensorConfig(float min_temp, float max_temp, float tolerance) {
+  Serial.printf("Temperature sensor settings: min %.2f°C, max %.2f°C, tolerance %.2f°C\n", min_temp, max_temp, tolerance);
+  sensor_min_temp = min_temp;
+  sensor_max_temp = max_temp;
+  sensor_tolerance = tolerance;
+}
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+
+  // Init button switch
+  pinMode(button, INPUT_PULLUP);
+
+  // Set callback functions for temperature and configuration receive
+  zbThermostat.onTempRecieve(recieveSensorTemp);
+  zbThermostat.onConfigRecieve(recieveSensorConfig);
+
+  //Optional: set Zigbee device name and model
+  zbThermostat.setManufacturerAndModel("Espressif", "ZigbeeThermostat");
+
+  //Optional Time cluster configuration
+  //example time January 13, 2025 13:30:30 CET
+  timeinfo.tm_year = 2025 - 1900;  // = 2025
+  timeinfo.tm_mon = 0;             // January
+  timeinfo.tm_mday = 13;           // 13th
+  timeinfo.tm_hour = 12;           // 12 hours - 1 hour (CET)
+  timeinfo.tm_min = 30;            // 30 minutes
+  timeinfo.tm_sec = 30;            // 30 seconds
+  timeinfo.tm_isdst = -1;
+
+  // Set time and gmt offset (timezone in seconds -> CET = +3600 seconds)
+  zbThermostat.addTimeCluster(timeinfo, 3600);
+
+  //Add endpoint to Zigbee Core
+  Zigbee.addEndpoint(&zbThermostat);
+
+  //Open network for 180 seconds after boot
+  Zigbee.setRebootOpenNetwork(180);
+
+  // When all EPs are registered, start Zigbee with ZIGBEE_COORDINATOR mode
+  if (!Zigbee.begin(ZIGBEE_COORDINATOR)) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+
+  Serial.println("Waiting for Temperature sensor to bound to the thermostat");
+  while (!zbThermostat.bound()) {
+    Serial.printf(".");
+    delay(500);
+  }
+
+  Serial.println();
+
+  // Get temperature sensor configuration
+  zbThermostat.getSensorSettings();
+}
+
+void loop() {
+  // Handle button switch in loop()
+  if (digitalRead(button) == LOW) {  // Push button pressed
+
+    // Key debounce handling
+    while (digitalRead(button) == LOW) {
+      delay(50);
+    }
+
+    // Set reporting interval for temperature sensor
+    zbThermostat.setTemperatureReporting(0, 10, 2);
+  }
+
+  // Print temperature sensor data each 10 seconds
+  static uint32_t last_print = 0;
+  if (millis() - last_print > 10000) {
+    last_print = millis();
+    int temp_percent = (int)((sensor_temp - sensor_min_temp) / (sensor_max_temp - sensor_min_temp) * 100);
+    Serial.printf("Loop temperature info: %.2f°C (%d %%)\n", sensor_temp, temp_percent);
+  }
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Thermostat/ci.json b/libraries/Zigbee/examples/Zigbee_Thermostat/ci.json
new file mode 100644
index 00000000000..15d6190e4ae
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Thermostat/ci.json
@@ -0,0 +1,6 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee_zczr,ZigbeeMode=zczr",
+  "requires": [
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/README.md
new file mode 100644
index 00000000000..b0e5b5f09e8
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/README.md
@@ -0,0 +1,58 @@
+# Arduino-ESP32 Zigbee Vibration Sensor Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) vibration sensor (IAS Zone),
+that can be used for example as a security device which is sensing a vibrations.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+
+### Configure the Project
+
+Set the Button GPIO by changing the `button` variable. By default, it's the pin `BOOT_PIN` (BOOT button on ESP32-C6 and ESP32-H2).
+Set the Sensor GPIO by changing the `sensor_pin` variable.
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/Zigbee_Vibration_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/Zigbee_Vibration_Sensor.ino
new file mode 100644
index 00000000000..d9ac7b6e241
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/Zigbee_Vibration_Sensor.ino
@@ -0,0 +1,104 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee vibration sensor (IAS Zone).
+ *
+ * The example demonstrates how to use Zigbee library to create a end device vibration sensor.
+ * The vibration sensor is a Zigbee end device, which is reporting data to the Zigbee network.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+/* Zigbee vibration sensor configuration */
+#define VIBRATION_SENSOR_ENDPOINT_NUMBER 10
+uint8_t button = BOOT_PIN;
+uint8_t sensor_pin = 4;
+
+ZigbeeVibrationSensor zbVibrationSensor = ZigbeeVibrationSensor(VIBRATION_SENSOR_ENDPOINT_NUMBER);
+
+void setup() {
+  Serial.begin(115200);
+
+  // Init button + sensor
+  pinMode(button, INPUT_PULLUP);
+  pinMode(sensor_pin, INPUT);
+
+  // Optional: set Zigbee device name and model
+  zbVibrationSensor.setManufacturerAndModel("Espressif", "ZigbeeVibrationSensor");
+
+  // Add endpoint to Zigbee Core
+  Zigbee.addEndpoint(&zbVibrationSensor);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+}
+
+void loop() {
+  // Checking pin for contact change
+  static bool sensed = false;
+  if (digitalRead(sensor_pin) == HIGH && !sensed) {
+    // Update contact sensor value
+    zbVibrationSensor.setVibration(true);
+    sensed = true;
+    //if sensed, wait 2 seconds before next sensing
+    delay(2000);
+  } else if (digitalRead(sensor_pin) == LOW && sensed) {
+    zbVibrationSensor.setVibration(false);
+    sensed = false;
+    //if not sensed, wait 0,5 seconds before next sensing
+    delay(500);
+  }
+
+  // Checking button for factory reset
+  if (digitalRead(button) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(button) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/ci.json b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Vibration_Sensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/README.md b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/README.md
new file mode 100644
index 00000000000..826c7666e6b
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/README.md
@@ -0,0 +1,60 @@
+# Zigbee Wind Speed Sensor Integration with HomeAssistant ZHA
+
+This guide provides a workaround for integrating a Zigbee Wind Speed Sensor with HomeAssistant using the ZHA integration. Since the wind speed cluster is not natively supported, we will use the ZHA Toolkit from HACS to read the wind speed attribute and store it in a helper variable.
+## Alternative Option: Creating a Custom Quirk
+
+For advanced users, a more robust solution is to create a custom quirk for your Zigbee Wind Speed Sensor. This approach involves writing a custom device handler that directly supports the wind speed cluster, providing a more seamless integration with HomeAssistant.
+
+Creating a custom quirk can be complex and requires familiarity with Python and the Zigbee protocol. However, it offers greater flexibility and control over your device's behavior.
+
+For more information and guidance on creating custom quirks, visit the [ZHA Device Handlers repository](https://github.com/zigpy/zha-device-handlers/).
+
+## Prerequisites
+
+- HomeAssistant installed and running
+- Zigbee Wind Speed Sensor paired with HomeAssistant ZHA
+- HACS (Home Assistant Community Store) installed. For more information, visit [HACS](https://hacs.xyz)
+
+## Steps
+
+### 1. Install ZHA Toolkit
+
+1. Open HomeAssistant.
+2. Navigate to HACS > Integrations.
+3. Search for "ZHA Toolkit - Service for advanced Zigbee Usage" and install it. For more information, visit the [ZHA Toolkit repository](https://github.com/mdeweerd/zha-toolkit).
+4. Restart HomeAssistant to apply changes.
+
+### 2. Create a Helper Variable
+
+1. Go to Configuration -> Devices & Services -> Helpers.
+2. Click on "Add Helper" and select "Number".
+3. Name the helper (e.g., `wind_speed`), set the minimum and maximum values, and save it.
+
+### 3. Create an Automation
+
+1. Go to Configuration > Automations & Scenes.
+2. Click on "Add Automation" and choose "Start with an empty automation".
+3. Set a name for the automation (e.g., `Read Wind Speed`).
+4. Add a trigger:
+    - Trigger Type: Time Pattern
+    - Every: 30 seconds
+5. Add an action (Then do):
+    - Action Type: ZHA Toolkit: Read Attribute
+    - Setup the action:
+      ```yaml
+        action: zha_toolkit.attr_read
+        metadata: {}
+        data:
+            ieee: f0:f5:bd:ff:fe:0e:61:30 #set device IEEE address
+            endpoint: 10 #set windspeed device endpoint
+            cluster: 1035 #use this windspeed cluster
+            attribute: 0 #read measurement value
+            state_id: input_number.wind_speed #save to created helper variable
+            state_value_template: value/100 #use correct value format (convert u16 to float)
+      ```
+6. Save the automation.
+
+## Conclusion
+
+By following these steps, you can successfully integrate your Zigbee Wind Speed Sensor with HomeAssistant using the ZHA integration and ZHA Toolkit. The wind speed readings will be updated every 30 seconds and stored in the helper variable for use in your HomeAssistant setup.
+The helper variable `wind_speed` is now an entity in HomeAssistant. You can use this entity to display the wind speed on your dashboard or in other automations.
diff --git a/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/Zigbee_Wind_Speed_Sensor.ino b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/Zigbee_Wind_Speed_Sensor.ino
new file mode 100644
index 00000000000..1c24df9a091
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/Zigbee_Wind_Speed_Sensor.ino
@@ -0,0 +1,119 @@
+// Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee windspeed sensor.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device wind speed sensor.
+ * The wind speed sensor is a Zigbee end device, which is controlled by a Zigbee coordinator.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee coordinator mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "Zigbee.h"
+
+#define BUTTON_PIN                        9  //Boot button for C6/H2
+#define WIND_SPEED_SENSOR_ENDPOINT_NUMBER 10
+
+ZigbeeWindSpeedSensor zbWindSpeedSensor = ZigbeeWindSpeedSensor(WIND_SPEED_SENSOR_ENDPOINT_NUMBER);
+
+/************************ WindSpeed sensor *****************************/
+static void windspeed_sensor_value_update(void *arg) {
+  for (;;) {
+    // Read wind speed sensor value (simulated now by temperature sensor)
+    float windspeed = temperatureRead();
+    log_v("Wind speed sensor value: %.2fm/s", windspeed);
+    // Update windspeed value in Windspeed sensor EP
+    zbWindSpeedSensor.setWindSpeed(windspeed);
+    delay(1000);
+  }
+}
+
+/********************* Arduino functions **************************/
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  // Init button switch
+  pinMode(BUTTON_PIN, INPUT);
+
+  // Optional: set Zigbee device name and model
+  zbWindSpeedSensor.setManufacturerAndModel("Espressif", "ZigbeeWindSpeedSensor");
+
+  // Set minimum and maximum windspeed measurement value in m/s
+  zbWindSpeedSensor.setMinMaxValue(0, 50);
+
+  // Set tolerance for windspeed measurement in m/s (lowest possible value is 0.01 m/s)
+  zbWindSpeedSensor.setTolerance(1);
+
+  // Add endpoint to Zigbee Core
+  Zigbee.addEndpoint(&zbWindSpeedSensor);
+
+  Serial.println("Starting Zigbee...");
+  // When all EPs are registered, start Zigbee in End Device mode
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  } else {
+    Serial.println("Zigbee started successfully!");
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+
+  // Start Wind speed sensor reading task
+  xTaskCreate(windspeed_sensor_value_update, "wind_speed_sensor_update", 2048, NULL, 10, NULL);
+
+  // Set reporting interval for windspeed measurement in seconds, must be called after Zigbee.begin()
+  // min_interval and max_interval in seconds, delta (WindSpeed change in m/s)
+  // if min = 1 and max = 0, reporting is sent only when windspeed changes by delta
+  // if min = 0 and max = 10, reporting is sent every 10 seconds or windspeed changes by delta
+  // if min = 0, max = 10 and delta = 0, reporting is sent every 10 seconds regardless of windspeed change
+  zbWindSpeedSensor.setReporting(1, 0, 1);
+}
+
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(BUTTON_PIN) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(BUTTON_PIN) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.println("Resetting Zigbee to factory and rebooting in 1s.");
+        delay(1000);
+        Zigbee.factoryReset();
+      }
+    }
+    zbWindSpeedSensor.reportWindSpeed();
+  }
+  delay(100);
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/ci.json b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Wind_Speed_Sensor/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Window_Covering/README.md b/libraries/Zigbee/examples/Zigbee_Window_Covering/README.md
new file mode 100644
index 00000000000..469560a0e0c
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Window_Covering/README.md
@@ -0,0 +1,69 @@
+# Arduino-ESP32 Window Covering Example
+
+This example shows how to configure the Zigbee end device and use it as a Home Automation (HA) window covering device.
+
+To see if the communication with your Zigbee network works, use the Serial monitor and watch for output there.
+
+# Supported Targets
+
+Currently, this example supports the following targets.
+
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+## Hardware Required
+
+* A USB cable for power supply and programming
+* Board (ESP32-H2 or ESP32-C6) as Zigbee end device and upload the Zigbee_Window_Covering example
+* Zigbee network / coordinator (Other board with switch examples or Zigbee2mqtt or ZigbeeHomeAssistant like application)
+
+### Configure the Project
+
+#### Using Arduino IDE
+
+To get more information about the Espressif boards see [Espressif Development Kits](https://www.espressif.com/en/products/devkits).
+
+* Before Compile/Verify, select the correct board: `Tools -> Board`.
+* Select the End device Zigbee mode: `Tools -> Zigbee mode: Zigbee ED (end device)`
+* Select Tools / USB CDC On Boot: "Enabled"
+* Select Partition Scheme for Zigbee: `Tools -> Partition Scheme: Zigbee 4MB with spiffs`
+* Select the COM port: `Tools -> Port: xxx` where the `xxx` is the detected COM port.
+* Optional: Set debug level to verbose to see all logs from Zigbee stack: `Tools -> Core Debug Level: Verbose`.
+
+## Troubleshooting
+
+If the End device flashed with this example is not connecting to the coordinator, erase the flash of the End device before flashing the example to the board. It is recommended to do this if you re-flash the coordinator.
+You can do the following:
+
+* In the Arduino IDE go to the Tools menu and set `Erase All Flash Before Sketch Upload` to `Enabled`.
+* Add to the sketch `Zigbee.factoryReset();` to reset the device and Zigbee stack.
+
+By default, the coordinator network is closed after rebooting or flashing new firmware.
+To open the network you have 2 options:
+
+* Open network after reboot by setting `Zigbee.setRebootOpenNetwork(time);` before calling `Zigbee.begin();`.
+* In application you can anytime call `Zigbee.openNetwork(time);` to open the network for devices to join.
+
+***Important: Make sure you are using a good quality USB cable and that you have a reliable power source***
+
+* **LED not blinking:** Check the wiring connection and the IO selection.
+* **Programming Fail:** If the programming/flash procedure fails, try reducing the serial connection speed.
+* **COM port not detected:** Check the USB cable and the USB to Serial driver installation.
+
+If the error persists, you can ask for help at the official [ESP32 forum](https://esp32.com) or see [Contribute](#contribute).
+
+## Contribute
+
+To know how to contribute to this project, see [How to contribute.](https://github.com/espressif/arduino-esp32/blob/master/CONTRIBUTING.rst)
+
+If you have any **feedback** or **issue** to report on this example/library, please open an issue or fix it by creating a new PR. Contributions are more than welcome!
+
+Before creating a new issue, be sure to try Troubleshooting and check if the same issue was already created by someone else.
+
+## Resources
+
+* Official ESP32 Forum: [Link](https://esp32.com)
+* Arduino-ESP32 Official Repository: [espressif/arduino-esp32](https://github.com/espressif/arduino-esp32)
+* ESP32-C6 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf)
+* ESP32-H2 Datasheet: [Link to datasheet](https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)
+* Official ESP-IDF documentation: [ESP-IDF](https://idf.espressif.com)
diff --git a/libraries/Zigbee/examples/Zigbee_Window_Covering/Zigbee_Window_Covering.ino b/libraries/Zigbee/examples/Zigbee_Window_Covering/Zigbee_Window_Covering.ino
new file mode 100644
index 00000000000..c7f9cf84f74
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Window_Covering/Zigbee_Window_Covering.ino
@@ -0,0 +1,198 @@
+// Copyright 2025 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/**
+ * @brief This example demonstrates Zigbee Window Covering.
+ *
+ * The example demonstrates how to use Zigbee library to create a end device window covering device.
+ * The window covering is a Zigbee end device, which is moving the blinds (lift+tilt) and reporting
+ * its current position to the Zigbee network.
+ *
+ * Use setCoveringType() to set the type of covering (blind, shade, etc.).
+ *
+ * The example also demonstrates how to use the button to manually control the lift position.
+ *
+ * Proper Zigbee mode must be selected in Tools->Zigbee mode
+ * and also the correct partition scheme must be selected in Tools->Partition Scheme.
+ *
+ * Please check the README.md for instructions and more detailed description.
+ *
+ * Created by hennikul and Jan Procházka (https://github.com/P-R-O-C-H-Y/)
+ */
+
+#ifndef ZIGBEE_MODE_ED
+#error "Zigbee end device mode is not selected in Tools->Zigbee mode"
+#endif
+
+#include "ZigbeeCore.h"
+#include "ep/ZigbeeWindowCovering.h"
+
+#define ZIGBEE_COVERING_ENDPOINT 10
+#define BUTTON_PIN               9  // ESP32-C6/H2 Boot button
+
+#define MAX_LIFT 200  // centimeters from open position (0-900)
+#define MIN_LIFT 0
+
+#define MAX_TILT 40  // centimeters from open position (0-900)
+#define MIN_TILT 0
+
+uint16_t currentLift = MAX_LIFT;
+uint8_t currentLiftPercentage = 100;
+
+uint16_t currentTilt = MAX_TILT;
+uint8_t currentTiltPercentage = 100;
+
+ZigbeeWindowCovering zbCovering = ZigbeeWindowCovering(ZIGBEE_COVERING_ENDPOINT);
+
+void setup() {
+  Serial.begin(115200);
+
+  // Init button for factory reset
+  pinMode(BUTTON_PIN, INPUT_PULLUP);
+
+  // Optional: set Zigbee device name and model
+  zbCovering.setManufacturerAndModel("Espressif", "WindowBlinds");
+
+  // Set proper covering type, it defines which attributes are available
+  zbCovering.setCoveringType(BLIND_LIFT_AND_TILT);
+
+  // Set configuration: operational, online, not commands_reversed, lift / tilt closed_loop, lift / tilt encoder_controlled
+  zbCovering.setConfigStatus(true, true, false, true, true, true, true);
+
+  // Set mode: not motor_reversed, calibration_mode, not maintenance_mode, not leds_on
+  zbCovering.setMode(false, true, false, false);
+
+  // Set limits of motion
+  zbCovering.setLimits(MIN_LIFT, MAX_LIFT, MIN_TILT, MAX_TILT);
+
+  // Set callback function for open, close, filt and tilt change, stop
+  zbCovering.onOpen(fullOpen);
+  zbCovering.onClose(fullClose);
+  zbCovering.onGoToLiftPercentage(goToLiftPercentage);
+  zbCovering.onGoToTiltPercentage(goToTiltPercentage);
+  zbCovering.onStop(stopMotor);
+
+  // Add endpoint to Zigbee Core
+  Serial.println("Adding ZigbeeWindowCovering endpoint to Zigbee Core");
+  Zigbee.addEndpoint(&zbCovering);
+
+  // When all EPs are registered, start Zigbee. By default acts as ZIGBEE_END_DEVICE
+  Serial.println("Calling Zigbee.begin()");
+  if (!Zigbee.begin()) {
+    Serial.println("Zigbee failed to start!");
+    Serial.println("Rebooting...");
+    ESP.restart();
+  }
+  Serial.println("Connecting to network");
+  while (!Zigbee.connected()) {
+    Serial.print(".");
+    delay(100);
+  }
+  Serial.println();
+
+  // Set initial position
+  zbCovering.setLiftPercentage(currentLiftPercentage);
+  zbCovering.setTiltPercentage(currentTiltPercentage);
+}
+
+void loop() {
+  // Checking button for factory reset
+  if (digitalRead(BUTTON_PIN) == LOW) {  // Push button pressed
+    // Key debounce handling
+    delay(100);
+    int startTime = millis();
+    while (digitalRead(BUTTON_PIN) == LOW) {
+      delay(50);
+      if ((millis() - startTime) > 3000) {
+        // If key pressed for more than 3secs, factory reset Zigbee and reboot
+        Serial.printf("Resetting Zigbee to factory settings, reboot.\n");
+        Zigbee.factoryReset();
+        delay(30000);
+      }
+    }
+    // Manual lift control simulation by pressing button
+    manualControl();
+  }
+  delay(500);
+}
+
+void fullOpen() {
+  /* This is where you would trigger your motor to go to full open state, currentLift should
+     be updated until full open has been reached in order to provide feedback to controller of actual position
+     The stop can be always called, so the movement can be stopped at any time */
+
+  // Our cover updates instantly!
+  currentLift = MAX_LIFT;
+  currentLiftPercentage = 100;
+  Serial.println("Opening cover");
+  // Update the current position
+  zbCovering.setLiftPercentage(currentLiftPercentage);
+}
+
+void fullClose() {
+  /* This is where you would trigger your motor to go to full close state, currentLift should
+     be updated until full close has been reached in order to provide feedback to controller of actual position
+     The stop can be always called, so the movement can be stopped at any time */
+
+  // Our cover updates instantly!
+  currentLift = MIN_LIFT;
+  currentLiftPercentage = 0;
+  Serial.println("Closing cover");
+  // Update the current position
+  zbCovering.setLiftPercentage(currentLiftPercentage);
+}
+
+void goToLiftPercentage(uint8_t liftPercentage) {
+  /* This is where you would trigger your motor to go towards liftPercentage, currentLift should
+     be updated until liftPercentage has been reached in order to provide feedback to controller */
+
+  // Our simulated cover updates instantly!
+  currentLift = (liftPercentage * MAX_LIFT) / 100;
+  currentLiftPercentage = liftPercentage;
+  Serial.printf("New requested lift from Zigbee: %d (%d)\n", currentLift, liftPercentage);
+
+  // Update the current position
+  zbCovering.setLiftPercentage(currentLiftPercentage);  //or setLiftPosition()
+}
+
+void goToTiltPercentage(uint8_t tiltPercentage) {
+  /* This is where you would trigger your motor to go towards tiltPercentage, currentTilt should
+     be updated until tiltPercentage has been reached in order to provide feedback to controller */
+
+  // Our simulated cover updates instantly!
+  currentTilt = (tiltPercentage * MAX_TILT) / 100;
+  currentTiltPercentage = tiltPercentage;
+  Serial.printf("New requested tilt from Zigbee: %d (%d)\n", currentTilt, tiltPercentage);
+
+  // Update the current position
+  zbCovering.setTiltPercentage(currentTiltPercentage);  //or setTiltPosition()
+}
+
+void stopMotor() {
+  // Motor can be stopped while moving cover toward current target, when stopped the actual position should be updated
+  Serial.println("Stopping motor");
+  // Update the current position of both lift and tilt
+  zbCovering.setLiftPercentage(currentLiftPercentage);
+  zbCovering.setTiltPercentage(currentTiltPercentage);
+}
+
+void manualControl() {
+  // Simulate lift percentage move by increasing it by 20% each time
+  currentLiftPercentage += 20;
+  if (currentLiftPercentage > 100) {
+    currentLiftPercentage = 0;
+  }
+  zbCovering.setLiftPercentage(currentLiftPercentage);
+  // Also setLiftPosition() can be used to set the exact position instead of percentage
+}
diff --git a/libraries/Zigbee/examples/Zigbee_Window_Covering/ci.json b/libraries/Zigbee/examples/Zigbee_Window_Covering/ci.json
new file mode 100644
index 00000000000..ceacc367801
--- /dev/null
+++ b/libraries/Zigbee/examples/Zigbee_Window_Covering/ci.json
@@ -0,0 +1,7 @@
+{
+  "fqbn_append": "PartitionScheme=zigbee,ZigbeeMode=ed",
+  "requires": [
+    "CONFIG_SOC_IEEE802154_SUPPORTED=y",
+    "CONFIG_ZB_ENABLED=y"
+  ]
+}
diff --git a/libraries/Zigbee/keywords.txt b/libraries/Zigbee/keywords.txt
new file mode 100644
index 00000000000..586d2bdc677
--- /dev/null
+++ b/libraries/Zigbee/keywords.txt
@@ -0,0 +1,193 @@
+#######################################
+# Syntax Coloring Map For Zigbee
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+# Base Classes
+ZigbeeCore	KEYWORD1
+Zigbee	KEYWORD1
+ZigbeeEP	KEYWORD1
+
+# Endpoint Classes
+ZigbeeLight	KEYWORD1
+ZigbeeSwitch	KEYWORD1
+ZigbeeColorDimmableLight	KEYWORD1
+ZigbeeColorDimmerSwitch	KEYWORD1
+ZigbeeTempSensor	KEYWORD1
+ZigbeeThermostat	KEYWORD1
+ZigbeeFlowSensor	KEYWORD1
+ZigbeePressureSensor	KEYWORD1
+ZigbeeOccupancySensor	KEYWORD1
+ZigbeeAnalog	KEYWORD1
+ZigbeeCarbonDioxideSensor	KEYWORD1
+ZigbeeContactSwitch	KEYWORD1
+ZigbeeDoorWindowHandle	KEYWORD1
+ZigbeeGateway	KEYWORD1
+ZigbeeRangeExtender	KEYWORD1
+ZigbeeVibrationSensor	KEYWORD1
+ZigbeeWindowCovering	KEYWORD1
+ZigbeeIlluminanceSensor	KEYWORD1
+
+# Other
+zigbee_role_t	KEYWORD1
+zbstring_t	KEYWORD1
+zb_device_params_t	KEYWORD1
+zigbee_scan_result_t	KEYWORD1
+zb_power_source_t	KEYWORD1
+ZigbeeWindowCoveringType	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+# ZigbeeCore
+begin	KEYWORD2
+started	KEYWORD2
+connected	KEYWORD2
+getRole	KEYWORD2
+addEndpoint	KEYWORD2
+setRadioConfig	KEYWORD2
+getRadioConfig	KEYWORD2
+setHostConfig	KEYWORD2
+getHostConfig	KEYWORD2
+setPrimaryChannelMask	KEYWORD2
+setScanDuration	KEYWORD2
+getScanDuration	KEYWORD2
+setRebootOpenNetwork	KEYWORD2
+openNetwork	KEYWORD2
+scanNetworks	KEYWORD2
+scanComplete	KEYWORD2
+getScanResult	KEYWORD2
+scanDelete	KEYWORD2
+factoryReset	KEYWORD2
+
+# Common ZigbeeEP
+setEpConfig	KEYWORD2
+setVersion	KEYWORD2
+getEndpoint	KEYWORD2
+printBoundDevices	KEYWORD2
+getBoundDevices	KEYWORD2
+bound	KEYWORD2
+allowMultipleBinding	KEYWORD2
+setManufacturerAndModel	KEYWORD2
+setPowerSource	KEYWORD2
+setBatteryPercentage	KEYWORD2
+reportBatteryPercentage	KEYWORD2
+readManufacturer	KEYWORD2
+readModel	KEYWORD2
+onIdentify	KEYWORD2
+
+# ZigbeeLight + ZigbeeColorDimmableLight
+onLightChange	KEYWORD2
+restoreLight	KEYWORD2
+setLight	KEYWORD2
+setLightState	KEYWORD2
+setLightLevel	KEYWORD2
+setLightColor	KEYWORD2
+getLightState	KEYWORD2
+getLightLevel	KEYWORD2
+getLightRed	KEYWORD2
+getLightGreen	KEYWORD2
+getLightBlue	KEYWORD2
+
+# ZigbeeSwitch + ZigbeeColorDimmerSwitch
+lightToggle	KEYWORD2
+lightOn	KEYWORD2
+lightOff	KEYWORD2
+lightOffWithEffect	KEYWORD2
+lightOnWithTimedOff	KEYWORD2
+lightOnWithSceneRecall	KEYWORD2
+setLightLevel	KEYWORD2
+setLightColor	KEYWORD2
+
+# ZigbeeThermostat
+onTempRecieve	KEYWORD2
+onConfigRecieve	KEYWORD2
+getTemperature	KEYWORD2
+getSensorSettings	KEYWORD2
+setTemperatureReporting	KEYWORD2
+
+# Common Zigbee Sensor
+setMinMaxValue	KEYWORD2
+setTolerance	KEYWORD2
+setReporting	KEYWORD2
+report	KEYWORD2
+
+# ZigbeeTempSensor + humidity
+setTemperature	KEYWORD2
+reportTemperature	KEYWORD2
+addHumiditySensor	KEYWORD2
+setHumidity	KEYWORD2
+setHumidityReporting	KEYWORD2
+reportHumidity	KEYWORD2
+
+# ZigbeeIlluminanceSensor
+setIlluminance	KEYWORD2
+
+# ZigbeeFlowSensor
+setFlow	KEYWORD2
+
+# ZigbeePressureSensor
+setPressure	KEYWORD2
+
+# ZigbeeOccupancySensor
+setOccupancy	KEYWORD2
+setSensorType	KEYWORD2
+
+# ZigbeeCarbonDioxideSensor
+setCarbonDioxide	KEYWORD2
+
+# ZigbeeAnalog
+addAnalogValue	KEYWORD2
+addAnalogInput	KEYWORD2
+addAnalogOutput	KEYWORD2
+onAnalogOutputChange	KEYWORD2
+setAnalogValue	KEYWORD2
+setAnalogInput	KEYWORD2
+reportAnalogInput	KEYWORD2
+setAnalogInputReporting	KEYWORD2
+
+# ZigbeeCarbonDioxideSensor
+setCarbonDioxide	KEYWORD2
+
+# ZigbeeContactSwitch + ZigbeeDoorWindowHandle
+setIASClientEndpoint	KEYWORD2
+setClosed	KEYWORD2
+setOpen	KEYWORD2
+setTilted	KEYWORD2
+
+# ZigbeeVibrationSensor
+setVibration	KEYWORD2
+
+ZigbeeWindowCovering
+onOpen	KEYWORD2
+onClose	KEYWORD2
+onGoToLiftPercentage	KEYWORD2
+onGoToTiltPercentage	KEYWORD2
+onStop	KEYWORD2
+setLiftPosition	KEYWORD2
+setLiftPercentage	KEYWORD2
+setTiltPosition	KEYWORD2
+setTiltPercentage	KEYWORD2
+setCoveringType	KEYWORD2
+setConfigStatus	KEYWORD2
+setMode	KEYWORD2
+setLimits	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+
+ZIGBEE_COORDINATOR	LITERAL1
+ZIGBEE_ROUTER	LITERAL1
+ZIGBEE_END_DEVICE	LITERAL1
+ZIGBEE_DEFAULT_ED_CONFIG	LITERAL1
+ZIGBEE_DEFAULT_ROUTER_CONFIG	LITERAL1
+ZIGBEE_DEFAULT_COORDINATOR_CONFIG	LITERAL1
+ZIGBEE_DEFAULT_RADIO_CONFIG	LITERAL1
+ZIGBEE_DEFAULT_UART_RCP_RADIO_CONFIG	LITERAL1
+ZIGBEE_DEFAULT_HOST_CONFIG	LITERAL1
+ZB_ARRAY_LENTH	LITERAL1
diff --git a/libraries/Zigbee/library.properties b/libraries/Zigbee/library.properties
new file mode 100644
index 00000000000..9a558d70216
--- /dev/null
+++ b/libraries/Zigbee/library.properties
@@ -0,0 +1,9 @@
+name=Zigbee
+version=3.2.0
+author=P-R-O-C-H-Y
+maintainer=Jan Procházka <jan.prochazka@espressif.com>
+sentence=Enables zigbee connection with the ESP32
+paragraph=With this library you can create zigbee end devices, routers, coordinators and connect them to the zigbee network.
+category=Communication
+url=
+architectures=esp32
diff --git a/libraries/Zigbee/src/Zigbee.h b/libraries/Zigbee/src/Zigbee.h
new file mode 100644
index 00000000000..7f44d7813af
--- /dev/null
+++ b/libraries/Zigbee/src/Zigbee.h
@@ -0,0 +1,35 @@
+// Zigbee library header file for includes of all Zigbee library headers.
+
+#pragma once
+
+// Core
+#include "ZigbeeCore.h"
+#include "ZigbeeEP.h"
+
+// Endpoints
+//// Switches
+#include "ep/ZigbeeColorDimmerSwitch.h"
+#include "ep/ZigbeeSwitch.h"
+//// Lights
+#include "ep/ZigbeeColorDimmableLight.h"
+#include "ep/ZigbeeDimmableLight.h"
+#include "ep/ZigbeeLight.h"
+//// Controllers
+#include "ep/ZigbeeThermostat.h"
+//// Sensors
+#include "ep/ZigbeeAnalog.h"
+#include "ep/ZigbeeCarbonDioxideSensor.h"
+#include "ep/ZigbeeContactSwitch.h"
+#include "ep/ZigbeeDoorWindowHandle.h"
+#include "ep/ZigbeeFlowSensor.h"
+#include "ep/ZigbeeIlluminanceSensor.h"
+#include "ep/ZigbeeOccupancySensor.h"
+#include "ep/ZigbeePM25Sensor.h"
+#include "ep/ZigbeePressureSensor.h"
+#include "ep/ZigbeeTempSensor.h"
+#include "ep/ZigbeeVibrationSensor.h"
+#include "ep/ZigbeeWindSpeedSensor.h"
+#include "ep/ZigbeeWindowCovering.h"
+//// Other
+#include "ep/ZigbeeGateway.h"
+#include "ep/ZigbeeRangeExtender.h"
diff --git a/libraries/Zigbee/src/ZigbeeCore.cpp b/libraries/Zigbee/src/ZigbeeCore.cpp
new file mode 100644
index 00000000000..b93542159a6
--- /dev/null
+++ b/libraries/Zigbee/src/ZigbeeCore.cpp
@@ -0,0 +1,577 @@
+/* Zigbee Core Functions */
+
+#include "ZigbeeCore.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeHandlers.cpp"
+#include "Arduino.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "zboss_api.h"
+extern zb_ret_t zb_nvram_write_dataset(zb_nvram_dataset_types_t t);                            // rejoin scanning workaround
+extern void zb_set_ed_node_descriptor(bool power_src, bool rx_on_when_idle, bool alloc_addr);  // sleepy device power mode workaround
+#ifdef __cplusplus
+}
+#endif
+
+static bool edBatteryPowered = false;
+
+ZigbeeCore::ZigbeeCore() {
+  _radio_config.radio_mode = ZB_RADIO_MODE_NATIVE;                   // Use the native 15.4 radio
+  _host_config.host_connection_mode = ZB_HOST_CONNECTION_MODE_NONE;  // Disable host connection
+  _zb_ep_list = esp_zb_ep_list_create();
+  _primary_channel_mask = ESP_ZB_TRANSCEIVER_ALL_CHANNELS_MASK;
+  _open_network = 0;
+  _scan_status = ZB_SCAN_FAILED;
+  _begin_timeout = ZB_BEGIN_TIMEOUT_DEFAULT;
+  _started = false;
+  _connected = false;
+  _scan_duration = 3;  // default scan duration
+  _rx_on_when_idle = true;
+  if (!lock) {
+    lock = xSemaphoreCreateBinary();
+    if (lock == NULL) {
+      log_e("Semaphore creation failed");
+    }
+  }
+}
+
+//forward declaration
+static esp_err_t zb_action_handler(esp_zb_core_action_callback_id_t callback_id, const void *message);
+
+bool ZigbeeCore::begin(esp_zb_cfg_t *role_cfg, bool erase_nvs) {
+  if (!zigbeeInit(role_cfg, erase_nvs)) {
+    log_e("ZigbeeCore begin failed");
+    return false;
+  }
+  _role = (zigbee_role_t)role_cfg->esp_zb_role;
+  if (xSemaphoreTake(lock, _begin_timeout) != pdTRUE) {
+    log_e("ZigbeeCore begin failed or timeout");
+    if (_role != ZIGBEE_COORDINATOR) {  // Only End Device and Router can rejoin
+      resetNVRAMChannelMask();
+    }
+  }
+  return started();
+}
+
+bool ZigbeeCore::begin(zigbee_role_t role, bool erase_nvs) {
+  bool status = true;
+  switch (role) {
+    case ZIGBEE_COORDINATOR:
+    {
+      _role = ZIGBEE_COORDINATOR;
+      esp_zb_cfg_t zb_nwk_cfg = ZIGBEE_DEFAULT_COORDINATOR_CONFIG();
+      status = zigbeeInit(&zb_nwk_cfg, erase_nvs);
+      break;
+    }
+    case ZIGBEE_ROUTER:
+    {
+      _role = ZIGBEE_ROUTER;
+      esp_zb_cfg_t zb_nwk_cfg = ZIGBEE_DEFAULT_ROUTER_CONFIG();
+      status = zigbeeInit(&zb_nwk_cfg, erase_nvs);
+      break;
+    }
+    case ZIGBEE_END_DEVICE:
+    {
+      _role = ZIGBEE_END_DEVICE;
+      esp_zb_cfg_t zb_nwk_cfg = ZIGBEE_DEFAULT_ED_CONFIG();
+      status = zigbeeInit(&zb_nwk_cfg, erase_nvs);
+      break;
+    }
+    default: log_e("Invalid Zigbee Role"); return false;
+  }
+  if (!status || xSemaphoreTake(lock, _begin_timeout) != pdTRUE) {
+    log_e("ZigbeeCore begin failed or timeout");
+    if (_role != ZIGBEE_COORDINATOR) {  // Only End Device and Router can rejoin
+      resetNVRAMChannelMask();
+    }
+  }
+  return started();
+}
+
+bool ZigbeeCore::addEndpoint(ZigbeeEP *ep) {
+  ep_objects.push_back(ep);
+
+  log_d("Endpoint: %d, Device ID: 0x%04x", ep->_endpoint, ep->_device_id);
+  //Register clusters and ep_list to the ZigbeeCore class's ep_list
+  if (ep->_ep_config.endpoint == 0 || ep->_cluster_list == nullptr) {
+    log_e("Endpoint config or Cluster list is not initialized, EP not added to ZigbeeCore's EP list");
+    return false;
+  }
+  esp_err_t ret = ESP_OK;
+  if (ep->_device_id == ESP_ZB_HA_HOME_GATEWAY_DEVICE_ID) {
+    ret = esp_zb_ep_list_add_gateway_ep(_zb_ep_list, ep->_cluster_list, ep->_ep_config);
+  } else {
+    ret = esp_zb_ep_list_add_ep(_zb_ep_list, ep->_cluster_list, ep->_ep_config);
+  }
+  if (ret != ESP_OK) {
+    log_e("Failed to add endpoint: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+static void esp_zb_task(void *pvParameters) {
+  esp_zb_bdb_set_scan_duration(Zigbee.getScanDuration());
+
+  /* initialize Zigbee stack */
+  ESP_ERROR_CHECK(esp_zb_start(false));
+
+  //NOTE: This is a workaround to make battery powered devices to be discovered as battery powered
+  if (((zigbee_role_t)Zigbee.getRole() == ZIGBEE_END_DEVICE) && edBatteryPowered) {
+    zb_set_ed_node_descriptor(0, Zigbee.getRxOnWhenIdle(), 1);
+  }
+
+  esp_zb_stack_main_loop();
+}
+
+// Zigbee core init function
+bool ZigbeeCore::zigbeeInit(esp_zb_cfg_t *zb_cfg, bool erase_nvs) {
+  // Zigbee platform configuration
+  esp_zb_platform_config_t platform_config = {
+    .radio_config = _radio_config,
+    .host_config = _host_config,
+  };
+
+  esp_err_t err = esp_zb_platform_config(&platform_config);
+  if (err != ESP_OK) {
+    log_e("Failed to configure Zigbee platform");
+    return false;
+  }
+
+  // Initialize Zigbee stack
+  log_d("Initialize Zigbee stack");
+  esp_zb_init(zb_cfg);
+
+  // Register all Zigbee EPs in list
+  if (ep_objects.empty()) {
+    log_w("No Zigbee EPs to register");
+  } else {
+    log_d("Register all Zigbee EPs in list");
+    err = esp_zb_device_register(_zb_ep_list);
+    if (err != ESP_OK) {
+      log_e("Failed to register Zigbee EPs");
+      return false;
+    }
+
+    //print the list of Zigbee EPs from ep_objects
+    log_i("List of registered Zigbee EPs:");
+    for (std::list<ZigbeeEP *>::iterator it = ep_objects.begin(); it != ep_objects.end(); ++it) {
+      log_i("Device type: %s, Endpoint: %d, Device ID: 0x%04x", getDeviceTypeString((*it)->_device_id), (*it)->_endpoint, (*it)->_device_id);
+      if ((*it)->_power_source == ZB_POWER_SOURCE_BATTERY) {
+        edBatteryPowered = true;
+      }
+    }
+  }
+  // Register Zigbee action handler
+  esp_zb_core_action_handler_register(zb_action_handler);
+  err = esp_zb_set_primary_network_channel_set(_primary_channel_mask);
+  if (err != ESP_OK) {
+    log_e("Failed to set primary network channel mask");
+    return false;
+  }
+
+  //Erase NVRAM before creating connection to new Coordinator
+  if (erase_nvs) {
+    esp_zb_nvram_erase_at_start(true);
+  }
+
+  // Create Zigbee task and start Zigbee stack
+  xTaskCreate(esp_zb_task, "Zigbee_main", 8192, NULL, 5, NULL);
+
+  return true;
+}
+
+void ZigbeeCore::setRadioConfig(esp_zb_radio_config_t config) {
+  _radio_config = config;
+}
+
+esp_zb_radio_config_t ZigbeeCore::getRadioConfig() {
+  return _radio_config;
+}
+
+void ZigbeeCore::setHostConfig(esp_zb_host_config_t config) {
+  _host_config = config;
+}
+
+esp_zb_host_config_t ZigbeeCore::getHostConfig() {
+  return _host_config;
+}
+
+void ZigbeeCore::setPrimaryChannelMask(uint32_t mask) {
+  _primary_channel_mask = mask;
+}
+
+void ZigbeeCore::setScanDuration(uint8_t duration) {
+  if (duration < 1 || duration > 4) {
+    log_e("Invalid scan duration, must be between 1 and 4");
+    return;
+  }
+  _scan_duration = duration;
+}
+
+void ZigbeeCore::setRebootOpenNetwork(uint8_t time) {
+  _open_network = time;
+}
+
+void ZigbeeCore::openNetwork(uint8_t time) {
+  if (started()) {
+    log_v("Opening network for joining for %d seconds", time);
+    esp_zb_bdb_open_network(time);
+  }
+}
+
+static void bdb_start_top_level_commissioning_cb(uint8_t mode_mask) {
+  ESP_ERROR_CHECK(esp_zb_bdb_start_top_level_commissioning(mode_mask));
+}
+
+void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct) {
+  //common variables
+  uint32_t *p_sg_p = signal_struct->p_app_signal;
+  esp_err_t err_status = signal_struct->esp_err_status;
+  esp_zb_app_signal_type_t sig_type = (esp_zb_app_signal_type_t)*p_sg_p;
+  //coordinator variables
+  esp_zb_zdo_signal_device_annce_params_t *dev_annce_params = NULL;
+
+  //main switch
+  switch (sig_type) {
+    case ESP_ZB_ZDO_SIGNAL_SKIP_STARTUP:  // Common
+      log_i("Zigbee stack initialized");
+      log_d("Zigbee channel mask: 0x%08x", esp_zb_get_channel_mask());
+      esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_INITIALIZATION);
+      break;
+    case ESP_ZB_BDB_SIGNAL_DEVICE_FIRST_START:  // Common
+    case ESP_ZB_BDB_SIGNAL_DEVICE_REBOOT:       // Common
+      if (err_status == ESP_OK) {
+        log_i("Device started up in %s factory-reset mode", esp_zb_bdb_is_factory_new() ? "" : "non");
+        if (esp_zb_bdb_is_factory_new()) {
+          // Role specific code
+          if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) {
+            log_i("Start network formation");
+            esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_NETWORK_FORMATION);
+          } else {
+            log_i("Start network steering");
+            esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_NETWORK_STEERING);
+            Zigbee._started = true;
+            xSemaphoreGive(Zigbee.lock);
+          }
+        } else {
+          log_i("Device rebooted");
+          Zigbee._started = true;
+          xSemaphoreGive(Zigbee.lock);
+          if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR && Zigbee._open_network > 0) {
+            log_i("Opening network for joining for %d seconds", Zigbee._open_network);
+            esp_zb_bdb_open_network(Zigbee._open_network);
+          } else {
+            // Save the channel mask to NVRAM in case of reboot which may be on a different channel after a change in the network
+            Zigbee.setNVRAMChannelMask(1 << esp_zb_get_current_channel());
+            Zigbee._connected = true;
+          }
+          Zigbee.searchBindings();
+        }
+      } else {
+        /* commissioning failed */
+        log_w("Commissioning failed, trying again...", esp_err_to_name(err_status));
+        esp_zb_scheduler_alarm((esp_zb_callback_t)bdb_start_top_level_commissioning_cb, ESP_ZB_BDB_MODE_INITIALIZATION, 500);
+      }
+      break;
+    case ESP_ZB_BDB_SIGNAL_FORMATION:  // Coordinator
+      if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) {
+        if (err_status == ESP_OK) {
+          esp_zb_ieee_addr_t extended_pan_id;
+          esp_zb_get_extended_pan_id(extended_pan_id);
+          log_i(
+            "Formed network successfully (Extended PAN ID: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x, PAN ID: 0x%04hx, Channel:%d, Short Address: 0x%04hx)",
+            extended_pan_id[7], extended_pan_id[6], extended_pan_id[5], extended_pan_id[4], extended_pan_id[3], extended_pan_id[2], extended_pan_id[1],
+            extended_pan_id[0], esp_zb_get_pan_id(), esp_zb_get_current_channel(), esp_zb_get_short_address()
+          );
+          esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_NETWORK_STEERING);
+        } else {
+          log_i("Restart network formation (status: %s)", esp_err_to_name(err_status));
+          esp_zb_scheduler_alarm((esp_zb_callback_t)bdb_start_top_level_commissioning_cb, ESP_ZB_BDB_MODE_NETWORK_FORMATION, 1000);
+        }
+      }
+      break;
+    case ESP_ZB_BDB_SIGNAL_STEERING:  // Router and End Device
+      if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) {
+        if (err_status == ESP_OK) {
+          log_i("Network steering started");
+        }
+        Zigbee._started = true;
+        xSemaphoreGive(Zigbee.lock);
+      } else {
+        if (err_status == ESP_OK) {
+          esp_zb_ieee_addr_t extended_pan_id;
+          esp_zb_get_extended_pan_id(extended_pan_id);
+          log_i(
+            "Joined network successfully (Extended PAN ID: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x, PAN ID: 0x%04hx, Channel:%d, Short Address: 0x%04hx)",
+            extended_pan_id[7], extended_pan_id[6], extended_pan_id[5], extended_pan_id[4], extended_pan_id[3], extended_pan_id[2], extended_pan_id[1],
+            extended_pan_id[0], esp_zb_get_pan_id(), esp_zb_get_current_channel(), esp_zb_get_short_address()
+          );
+          Zigbee._connected = true;
+          // Set channel mask and write to NVRAM, so that the device will re-join the network faster after reboot (scan only on the current channel)
+          Zigbee.setNVRAMChannelMask(1 << esp_zb_get_current_channel());
+        } else {
+          log_i("Network steering was not successful (status: %s)", esp_err_to_name(err_status));
+          esp_zb_scheduler_alarm((esp_zb_callback_t)bdb_start_top_level_commissioning_cb, ESP_ZB_BDB_MODE_NETWORK_STEERING, 1000);
+        }
+      }
+      break;
+    case ESP_ZB_ZDO_SIGNAL_DEVICE_ANNCE:  // Coordinator
+      if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) {
+        dev_annce_params = (esp_zb_zdo_signal_device_annce_params_t *)esp_zb_app_signal_get_params(p_sg_p);
+        log_i("New device commissioned or rejoined (short: 0x%04hx)", dev_annce_params->device_short_addr);
+        esp_zb_zdo_match_desc_req_param_t cmd_req;
+        cmd_req.dst_nwk_addr = dev_annce_params->device_short_addr;
+        cmd_req.addr_of_interest = dev_annce_params->device_short_addr;
+        log_v("Device capabilities: 0x%02x", dev_annce_params->capability);
+        /*
+            capability:
+            Bit 0 – Alternate PAN Coordinator
+            Bit 1 – Device type: 1- ZigBee Router; 0 – End Device
+            Bit 2 – Power Source: 1 Main powered
+            Bit 3 – Receiver on when Idle
+            Bit 4 – Reserved
+            Bit 5 – Reserved
+            Bit 6 – Security capability
+            Bit 7 – Reserved
+        */
+        // for each endpoint in the list call the findEndpoint function if not bounded or allowed to bind multiple devices
+        for (std::list<ZigbeeEP *>::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) {
+          if (!(*it)->bound() || (*it)->epAllowMultipleBinding()) {
+            // Check if the device is already bound
+            bool found = false;
+            // Get the list of devices bound to the EP
+            std::list<zb_device_params_t *> bound_devices = (*it)->getBoundDevices();
+            for (std::list<zb_device_params_t *>::iterator device = bound_devices.begin(); device != bound_devices.end(); ++device) {
+              if (((*device)->short_addr == dev_annce_params->device_short_addr) || (memcmp((*device)->ieee_addr, dev_annce_params->ieee_addr, 8) == 0)) {
+                found = true;
+                log_d("Device already bound to endpoint %d", (*it)->getEndpoint());
+                break;
+              }
+            }
+            if (!found) {
+              (*it)->findEndpoint(&cmd_req);
+            }
+          }
+        }
+      }
+      break;
+    case ESP_ZB_NWK_SIGNAL_PERMIT_JOIN_STATUS:  // Coordinator
+      if ((zigbee_role_t)Zigbee.getRole() == ZIGBEE_COORDINATOR) {
+        if (err_status == ESP_OK) {
+          if (*(uint8_t *)esp_zb_app_signal_get_params(p_sg_p)) {
+            log_i("Network(0x%04hx) is open for %d seconds", esp_zb_get_pan_id(), *(uint8_t *)esp_zb_app_signal_get_params(p_sg_p));
+          } else {
+            log_i("Network(0x%04hx) closed, devices joining not allowed.", esp_zb_get_pan_id());
+          }
+        }
+      }
+      break;
+    case ESP_ZB_ZDO_SIGNAL_LEAVE:  // End Device + Router
+      // Device was removed from the network, factory reset the device
+      if ((zigbee_role_t)Zigbee.getRole() != ZIGBEE_COORDINATOR) {
+        Zigbee.factoryReset(true);
+      }
+      break;
+    default: log_v("ZDO signal: %s (0x%x), status: %s", esp_zb_zdo_signal_to_string(sig_type), sig_type, esp_err_to_name(err_status)); break;
+  }
+}
+
+void ZigbeeCore::factoryReset(bool restart) {
+  if (restart) {
+    log_v("Factory resetting Zigbee stack, device will reboot");
+    esp_zb_factory_reset();
+  } else {
+    log_v("Factory resetting Zigbee NVRAM to factory default");
+    log_w("The device will not reboot, to take effect please reboot the device manually");
+    esp_zb_zcl_reset_nvram_to_factory_default();
+  }
+}
+
+void ZigbeeCore::scanCompleteCallback(esp_zb_zdp_status_t zdo_status, uint8_t count, esp_zb_network_descriptor_t *nwk_descriptor) {
+  log_v("Zigbee network scan complete");
+  if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) {
+    log_v("Found %d networks", count);
+    //print Zigbee networks
+    for (int i = 0; i < count; i++) {
+      log_v(
+        "Network %d: PAN ID: 0x%04hx, Permit Joining: %s, Extended PAN ID: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x, Channel: %d, Router Capacity: %s, End "
+        "Device Capacity: %s",
+        i, nwk_descriptor[i].short_pan_id, nwk_descriptor[i].permit_joining ? "Yes" : "No", nwk_descriptor[i].extended_pan_id[7],
+        nwk_descriptor[i].extended_pan_id[6], nwk_descriptor[i].extended_pan_id[5], nwk_descriptor[i].extended_pan_id[4], nwk_descriptor[i].extended_pan_id[3],
+        nwk_descriptor[i].extended_pan_id[2], nwk_descriptor[i].extended_pan_id[1], nwk_descriptor[i].extended_pan_id[0], nwk_descriptor[i].logic_channel,
+        nwk_descriptor[i].router_capacity ? "Yes" : "No", nwk_descriptor[i].end_device_capacity ? "Yes" : "No"
+      );
+    }
+    //save scan result and update scan status
+    //copy network descriptor to _scan_result to keep the data after the callback
+    Zigbee._scan_result = (esp_zb_network_descriptor_t *)malloc(count * sizeof(esp_zb_network_descriptor_t));
+    memcpy(Zigbee._scan_result, nwk_descriptor, count * sizeof(esp_zb_network_descriptor_t));
+    Zigbee._scan_status = count;
+  } else {
+    log_e("Failed to scan Zigbee network (status: 0x%x)", zdo_status);
+    Zigbee._scan_status = ZB_SCAN_FAILED;
+    Zigbee._scan_result = nullptr;
+  }
+}
+
+void ZigbeeCore::scanNetworks(u_int32_t channel_mask, u_int8_t scan_duration) {
+  if (!started()) {
+    log_e("Zigbee stack is not started, cannot scan networks");
+    return;
+  }
+  log_v("Scanning Zigbee networks");
+  esp_zb_zdo_active_scan_request(channel_mask, scan_duration, scanCompleteCallback);
+  _scan_status = ZB_SCAN_RUNNING;
+}
+
+int16_t ZigbeeCore::scanComplete() {
+  return _scan_status;
+}
+
+zigbee_scan_result_t *ZigbeeCore::getScanResult() {
+  return _scan_result;
+}
+
+void ZigbeeCore::scanDelete() {
+  if (_scan_result != nullptr) {
+    free(_scan_result);
+    _scan_result = nullptr;
+  }
+  _scan_status = ZB_SCAN_FAILED;
+}
+
+// Recall bounded devices from the binding table after reboot
+void ZigbeeCore::bindingTableCb(const esp_zb_zdo_binding_table_info_t *table_info, void *user_ctx) {
+  bool done = true;
+  esp_zb_zdo_mgmt_bind_param_t *req = (esp_zb_zdo_mgmt_bind_param_t *)user_ctx;
+  esp_zb_zdp_status_t zdo_status = (esp_zb_zdp_status_t)table_info->status;
+  log_d("Binding table callback for address 0x%04x with status %d", req->dst_addr, zdo_status);
+  if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) {
+    // Print binding table log simple
+    log_d("Binding table info: total %d, index %d, count %d", table_info->total, table_info->index, table_info->count);
+
+    if (table_info->total == 0) {
+      log_d("No binding table entries found");
+      free(req);
+      return;
+    }
+
+    esp_zb_zdo_binding_table_record_t *record = table_info->record;
+    for (int i = 0; i < table_info->count; i++) {
+      log_d(
+        "Binding table record: src_endp %d, dst_endp %d, cluster_id 0x%04x, dst_addr_mode %d", record->src_endp, record->dst_endp, record->cluster_id,
+        record->dst_addr_mode
+      );
+
+      zb_device_params_t *device = (zb_device_params_t *)calloc(1, sizeof(zb_device_params_t));
+      device->endpoint = record->dst_endp;
+      if (record->dst_addr_mode == ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT || record->dst_addr_mode == ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT) {
+        device->short_addr = record->dst_address.addr_short;
+      } else {  //ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT
+        memcpy(device->ieee_addr, record->dst_address.addr_long, sizeof(esp_zb_ieee_addr_t));
+      }
+
+      // Add to list of bound devices of proper endpoint
+      for (std::list<ZigbeeEP *>::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) {
+        if ((*it)->getEndpoint() == record->src_endp) {
+          (*it)->addBoundDevice(device);
+          log_d(
+            "Device bound to EP %d -> device endpoint: %d, short addr: 0x%04x, ieee addr: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X", record->src_endp,
+            device->endpoint, device->short_addr, device->ieee_addr[7], device->ieee_addr[6], device->ieee_addr[5], device->ieee_addr[4], device->ieee_addr[3],
+            device->ieee_addr[2], device->ieee_addr[1], device->ieee_addr[0]
+          );
+        }
+      }
+      record = record->next;
+    }
+
+    // Continue reading the binding table
+    if (table_info->index + table_info->count < table_info->total) {
+      /* There are unreported binding table entries, request for them. */
+      req->start_index = table_info->index + table_info->count;
+      esp_zb_zdo_binding_table_req(req, bindingTableCb, req);
+      done = false;
+    }
+  }
+
+  if (done) {
+    // Print bound devices
+    log_d("Filling bounded devices finished");
+    free(req);
+  }
+}
+
+void ZigbeeCore::searchBindings() {
+  esp_zb_zdo_mgmt_bind_param_t *mb_req = (esp_zb_zdo_mgmt_bind_param_t *)malloc(sizeof(esp_zb_zdo_mgmt_bind_param_t));
+  mb_req->dst_addr = esp_zb_get_short_address();
+  mb_req->start_index = 0;
+  log_d("Requesting binding table for address 0x%04x", mb_req->dst_addr);
+  esp_zb_zdo_binding_table_req(mb_req, bindingTableCb, (void *)mb_req);
+}
+
+void ZigbeeCore::resetNVRAMChannelMask() {
+  _primary_channel_mask = ESP_ZB_TRANSCEIVER_ALL_CHANNELS_MASK;
+  esp_zb_set_channel_mask(_primary_channel_mask);
+  zb_nvram_write_dataset(ZB_NVRAM_COMMON_DATA);
+  log_v("Channel mask reset to all channels");
+}
+
+void ZigbeeCore::setNVRAMChannelMask(uint32_t mask) {
+  _primary_channel_mask = mask;
+  esp_zb_set_channel_mask(_primary_channel_mask);
+  zb_nvram_write_dataset(ZB_NVRAM_COMMON_DATA);
+  log_v("Channel mask set to 0x%08x", mask);
+}
+
+// Function to convert enum value to string
+const char *ZigbeeCore::getDeviceTypeString(esp_zb_ha_standard_devices_t deviceId) {
+  switch (deviceId) {
+    case ESP_ZB_HA_ON_OFF_SWITCH_DEVICE_ID:              return "General On/Off switch";
+    case ESP_ZB_HA_LEVEL_CONTROL_SWITCH_DEVICE_ID:       return "Level Control Switch";
+    case ESP_ZB_HA_ON_OFF_OUTPUT_DEVICE_ID:              return "General On/Off output";
+    case ESP_ZB_HA_LEVEL_CONTROLLABLE_OUTPUT_DEVICE_ID:  return "Level Controllable Output";
+    case ESP_ZB_HA_SCENE_SELECTOR_DEVICE_ID:             return "Scene Selector";
+    case ESP_ZB_HA_CONFIGURATION_TOOL_DEVICE_ID:         return "Configuration Tool";
+    case ESP_ZB_HA_REMOTE_CONTROL_DEVICE_ID:             return "Remote Control";
+    case ESP_ZB_HA_COMBINED_INTERFACE_DEVICE_ID:         return "Combined Interface";
+    case ESP_ZB_HA_RANGE_EXTENDER_DEVICE_ID:             return "Range Extender";
+    case ESP_ZB_HA_MAINS_POWER_OUTLET_DEVICE_ID:         return "Mains Power Outlet";
+    case ESP_ZB_HA_DOOR_LOCK_DEVICE_ID:                  return "Door lock client";
+    case ESP_ZB_HA_DOOR_LOCK_CONTROLLER_DEVICE_ID:       return "Door lock controller";
+    case ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID:              return "Simple Sensor device";
+    case ESP_ZB_HA_CONSUMPTION_AWARENESS_DEVICE_ID:      return "Consumption Awareness Device";
+    case ESP_ZB_HA_HOME_GATEWAY_DEVICE_ID:               return "Home Gateway";
+    case ESP_ZB_HA_SMART_PLUG_DEVICE_ID:                 return "Smart plug";
+    case ESP_ZB_HA_WHITE_GOODS_DEVICE_ID:                return "White Goods";
+    case ESP_ZB_HA_METER_INTERFACE_DEVICE_ID:            return "Meter Interface";
+    case ESP_ZB_HA_ON_OFF_LIGHT_DEVICE_ID:               return "On/Off Light Device";
+    case ESP_ZB_HA_DIMMABLE_LIGHT_DEVICE_ID:             return "Dimmable Light Device";
+    case ESP_ZB_HA_COLOR_DIMMABLE_LIGHT_DEVICE_ID:       return "Color Dimmable Light Device";
+    case ESP_ZB_HA_DIMMER_SWITCH_DEVICE_ID:              return "Dimmer Switch Device";
+    case ESP_ZB_HA_COLOR_DIMMER_SWITCH_DEVICE_ID:        return "Color Dimmer Switch Device";
+    case ESP_ZB_HA_LIGHT_SENSOR_DEVICE_ID:               return "Light Sensor";
+    case ESP_ZB_HA_SHADE_DEVICE_ID:                      return "Shade";
+    case ESP_ZB_HA_SHADE_CONTROLLER_DEVICE_ID:           return "Shade controller";
+    case ESP_ZB_HA_WINDOW_COVERING_DEVICE_ID:            return "Window Covering client";
+    case ESP_ZB_HA_WINDOW_COVERING_CONTROLLER_DEVICE_ID: return "Window Covering controller";
+    case ESP_ZB_HA_HEATING_COOLING_UNIT_DEVICE_ID:       return "Heating/Cooling Unit device";
+    case ESP_ZB_HA_THERMOSTAT_DEVICE_ID:                 return "Thermostat Device";
+    case ESP_ZB_HA_TEMPERATURE_SENSOR_DEVICE_ID:         return "Temperature Sensor";
+    case ESP_ZB_HA_IAS_CONTROL_INDICATING_EQUIPMENT_ID:  return "IAS Control and Indicating Equipment";
+    case ESP_ZB_HA_IAS_ANCILLARY_CONTROL_EQUIPMENT_ID:   return "IAS Ancillary Control Equipment";
+    case ESP_ZB_HA_IAS_ZONE_ID:                          return "IAS Zone";
+    case ESP_ZB_HA_IAS_WARNING_DEVICE_ID:                return "IAS Warning Device";
+    case ESP_ZB_HA_TEST_DEVICE_ID:                       return "Custom HA device for test";
+    case ESP_ZB_HA_CUSTOM_TUNNEL_DEVICE_ID:              return "Custom Tunnel device";
+    case ESP_ZB_HA_CUSTOM_ATTR_DEVICE_ID:                return "Custom Attributes Device";
+    default:                                             return "Unknown device type";
+  }
+}
+
+ZigbeeCore Zigbee = ZigbeeCore();
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ZigbeeCore.h b/libraries/Zigbee/src/ZigbeeCore.h
new file mode 100644
index 00000000000..06c3ec4551a
--- /dev/null
+++ b/libraries/Zigbee/src/ZigbeeCore.h
@@ -0,0 +1,175 @@
+/* Zigbee core class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "esp_zigbee_core.h"
+#include "zdo/esp_zigbee_zdo_common.h"
+#include <esp32-hal-log.h>
+#include <list>
+#include "ZigbeeEP.h"
+class ZigbeeEP;
+
+typedef void (*voidFuncPtr)(void);
+typedef void (*voidFuncPtrArg)(void *);
+
+typedef esp_zb_network_descriptor_t zigbee_scan_result_t;
+
+// enum of Zigbee Roles
+typedef enum {
+  ZIGBEE_COORDINATOR = 0,
+  ZIGBEE_ROUTER = 1,
+  ZIGBEE_END_DEVICE = 2
+} zigbee_role_t;
+
+#define ZB_SCAN_RUNNING (-1)
+#define ZB_SCAN_FAILED  (-2)
+
+#define ZB_BEGIN_TIMEOUT_DEFAULT 30000  // 30 seconds
+
+#define ZIGBEE_DEFAULT_ED_CONFIG()                                      \
+  {                                                                     \
+    .esp_zb_role = ESP_ZB_DEVICE_TYPE_ED, .install_code_policy = false, \
+    .nwk_cfg = {                                                        \
+      .zed_cfg =                                                        \
+        {                                                               \
+          .ed_timeout = ESP_ZB_ED_AGING_TIMEOUT_64MIN,                  \
+          .keep_alive = 3000,                                           \
+        },                                                              \
+    },                                                                  \
+  }
+
+#define ZIGBEE_DEFAULT_ROUTER_CONFIG()                                                   \
+  {                                                                                      \
+    .esp_zb_role = ESP_ZB_DEVICE_TYPE_ROUTER, .install_code_policy = false, .nwk_cfg = { \
+      .zczr_cfg =                                                                        \
+        {                                                                                \
+          .max_children = 10,                                                            \
+        },                                                                               \
+    }                                                                                    \
+  }
+
+#define ZIGBEE_DEFAULT_COORDINATOR_CONFIG()                                                   \
+  {                                                                                           \
+    .esp_zb_role = ESP_ZB_DEVICE_TYPE_COORDINATOR, .install_code_policy = false, .nwk_cfg = { \
+      .zczr_cfg =                                                                             \
+        {                                                                                     \
+          .max_children = 10,                                                                 \
+        },                                                                                    \
+    }                                                                                         \
+  }
+
+#define ZIGBEE_DEFAULT_UART_RCP_RADIO_CONFIG()   \
+  {                                              \
+    .radio_mode = ZB_RADIO_MODE_UART_RCP,        \
+    .radio_uart_config = {                       \
+      .port = UART_NUM_1,                        \
+      .rx_pin = GPIO_NUM_NC,                     \
+      .tx_pin = GPIO_NUM_NC,                     \
+      .uart_config =                             \
+        {                                        \
+          .baud_rate = 460800,                   \
+          .data_bits = UART_DATA_8_BITS,         \
+          .parity = UART_PARITY_DISABLE,         \
+          .stop_bits = UART_STOP_BITS_1,         \
+          .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, \
+          .rx_flow_ctrl_thresh = 0,              \
+          .source_clk = UART_SCLK_DEFAULT,       \
+        },                                       \
+    },                                           \
+  }
+
+class ZigbeeCore {
+private:
+  esp_zb_radio_config_t _radio_config;
+  esp_zb_host_config_t _host_config;
+  uint32_t _primary_channel_mask;
+  uint32_t _begin_timeout;
+  int16_t _scan_status;
+  uint8_t _scan_duration;
+  bool _rx_on_when_idle;
+
+  esp_zb_ep_list_t *_zb_ep_list;
+  zigbee_role_t _role;
+  bool _started;
+  bool _connected;
+
+  uint8_t _open_network;
+  zigbee_scan_result_t *_scan_result;
+  SemaphoreHandle_t lock;
+
+  bool zigbeeInit(esp_zb_cfg_t *zb_cfg, bool erase_nvs);
+  static void scanCompleteCallback(esp_zb_zdp_status_t zdo_status, uint8_t count, esp_zb_network_descriptor_t *nwk_descriptor);
+  const char *getDeviceTypeString(esp_zb_ha_standard_devices_t deviceId);
+  void searchBindings();
+  static void bindingTableCb(const esp_zb_zdo_binding_table_info_t *table_info, void *user_ctx);
+  void resetNVRAMChannelMask();             // Reset to default mask also in NVRAM
+  void setNVRAMChannelMask(uint32_t mask);  // Set channel mask in NVRAM
+
+public:
+  ZigbeeCore();
+  ~ZigbeeCore() {}
+
+  std::list<ZigbeeEP *> ep_objects;
+
+  bool begin(zigbee_role_t role = ZIGBEE_END_DEVICE, bool erase_nvs = false);
+  bool begin(esp_zb_cfg_t *role_cfg, bool erase_nvs = false);
+  // bool end();
+
+  bool started() {
+    return _started;
+  }
+  bool connected() {
+    return _connected;
+  }
+  zigbee_role_t getRole() {
+    return _role;
+  }
+
+  bool addEndpoint(ZigbeeEP *ep);
+  //void removeEndpoint(ZigbeeEP *ep);
+
+  void setRadioConfig(esp_zb_radio_config_t config);
+  esp_zb_radio_config_t getRadioConfig();
+
+  void setHostConfig(esp_zb_host_config_t config);
+  esp_zb_host_config_t getHostConfig();
+
+  void setPrimaryChannelMask(uint32_t mask);  // By default all channels are scanned (11-26) -> mask 0x07FFF800
+
+  void setScanDuration(uint8_t duration);  // Can be set from 1 - 4. 1 is fastest, 4 is slowest
+  uint8_t getScanDuration() {
+    return _scan_duration;
+  }
+
+  void setRxOnWhenIdle(bool rx_on_when_idle) {
+    _rx_on_when_idle = rx_on_when_idle;
+  }
+  bool getRxOnWhenIdle() {
+    return _rx_on_when_idle;
+  }
+  void setTimeout(uint32_t timeout) {
+    _begin_timeout = timeout;
+  }
+  void setRebootOpenNetwork(uint8_t time);
+  void openNetwork(uint8_t time);
+
+  //scan_duration Time spent scanning each channel, in units of ((1 << scan_duration) + 1) * a beacon time. (15.36 microseconds)
+  void scanNetworks(uint32_t channel_mask = ESP_ZB_TRANSCEIVER_ALL_CHANNELS_MASK, uint8_t scan_duration = 5);
+  // Zigbee scan complete status check, -2: failed or not started, -1: running, 0: no networks found, >0: number of networks found
+  int16_t scanComplete();
+  zigbee_scan_result_t *getScanResult();
+  void scanDelete();
+
+  void factoryReset(bool restart = true);
+
+  // Friend function declaration to allow access to private members
+  friend void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct);
+};
+
+extern ZigbeeCore Zigbee;
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ZigbeeEP.cpp b/libraries/Zigbee/src/ZigbeeEP.cpp
new file mode 100644
index 00000000000..cf52a902983
--- /dev/null
+++ b/libraries/Zigbee/src/ZigbeeEP.cpp
@@ -0,0 +1,603 @@
+/* Common Class for Zigbee End Point */
+
+#include "ZigbeeEP.h"
+
+#if CONFIG_ZB_ENABLED
+
+#include "esp_zigbee_cluster.h"
+#include "zcl/esp_zigbee_zcl_power_config.h"
+
+bool ZigbeeEP::_is_bound = false;
+bool ZigbeeEP::_allow_multiple_binding = false;
+
+//TODO: is_bound and allow_multiple_binding to make not static
+
+/* Zigbee End Device Class */
+ZigbeeEP::ZigbeeEP(uint8_t endpoint) {
+  _endpoint = endpoint;
+  log_v("Endpoint: %d", _endpoint);
+  _ep_config.endpoint = 0;
+  _cluster_list = nullptr;
+  _on_identify = nullptr;
+  _read_model = NULL;
+  _read_manufacturer = NULL;
+  _time_status = 0;
+  if (!lock) {
+    lock = xSemaphoreCreateBinary();
+    if (lock == NULL) {
+      log_e("Semaphore creation failed");
+    }
+  }
+}
+
+void ZigbeeEP::setVersion(uint8_t version) {
+  _ep_config.app_device_version = version;
+}
+
+bool ZigbeeEP::setManufacturerAndModel(const char *name, const char *model) {
+  // Allocate a new array of size length + 2 (1 for the length, 1 for null terminator)
+  char zb_name[ZB_MAX_NAME_LENGTH + 2];
+  char zb_model[ZB_MAX_NAME_LENGTH + 2];
+
+  // Convert manufacturer to ZCL string
+  size_t name_length = strlen(name);
+  size_t model_length = strlen(model);
+  if (name_length > ZB_MAX_NAME_LENGTH || model_length > ZB_MAX_NAME_LENGTH) {
+    log_e("Manufacturer or model name is too long");
+    return false;
+  }
+  // Get and check the basic cluster
+  esp_zb_attribute_list_t *basic_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BASIC, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  if (basic_cluster == nullptr) {
+    log_e("Failed to get basic cluster");
+    return false;
+  }
+  // Store the length as the first element
+  zb_name[0] = static_cast<char>(name_length);  // Cast size_t to char
+  zb_model[0] = static_cast<char>(model_length);
+  // Use memcpy to copy the characters to the result array
+  memcpy(zb_name + 1, name, name_length);
+  memcpy(zb_model + 1, model, model_length);
+  // Null-terminate the array
+  zb_name[name_length + 1] = '\0';
+  zb_model[model_length + 1] = '\0';
+  // Update the manufacturer and model attributes
+  esp_err_t ret_name = esp_zb_basic_cluster_add_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_MANUFACTURER_NAME_ID, (void *)zb_name);
+  if (ret_name != ESP_OK) {
+    log_e("Failed to set manufacturer: 0x%x: %s", ret_name, esp_err_to_name(ret_name));
+  }
+  esp_err_t ret_model = esp_zb_basic_cluster_add_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_MODEL_IDENTIFIER_ID, (void *)zb_model);
+  if (ret_model != ESP_OK) {
+    log_e("Failed to set model: 0x%x: %s", ret_model, esp_err_to_name(ret_model));
+  }
+  return ret_name == ESP_OK && ret_model == ESP_OK;
+}
+
+bool ZigbeeEP::setPowerSource(zb_power_source_t power_source, uint8_t battery_percentage, uint8_t battery_voltage) {
+  esp_zb_attribute_list_t *basic_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BASIC, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_POWER_SOURCE_ID, (void *)&power_source);
+  if (ret != ESP_OK) {
+    log_e("Failed to set power source: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+
+  if (power_source == ZB_POWER_SOURCE_BATTERY) {
+    // Add power config cluster and battery percentage attribute
+    if (battery_percentage > 100) {
+      battery_percentage = 100;
+    }
+    battery_percentage = battery_percentage * 2;
+    esp_zb_attribute_list_t *power_config_cluster = esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_POWER_CONFIG);
+    ret = esp_zb_power_config_cluster_add_attr(power_config_cluster, ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_PERCENTAGE_REMAINING_ID, (void *)&battery_percentage);
+    if (ret != ESP_OK) {
+      log_e("Failed to add battery percentage attribute: 0x%x: %s", ret, esp_err_to_name(ret));
+      return false;
+    }
+    ret = esp_zb_power_config_cluster_add_attr(power_config_cluster, ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_VOLTAGE_ID, (void *)&battery_voltage);
+    if (ret != ESP_OK) {
+      log_e("Failed to add battery voltage attribute: 0x%x: %s", ret, esp_err_to_name(ret));
+      return false;
+    }
+    ret = esp_zb_cluster_list_add_power_config_cluster(_cluster_list, power_config_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+    if (ret != ESP_OK) {
+      log_e("Failed to add power config cluster: 0x%x: %s", ret, esp_err_to_name(ret));
+      return false;
+    }
+  }
+  _power_source = power_source;
+  return true;
+}
+
+bool ZigbeeEP::setBatteryPercentage(uint8_t percentage) {
+  // 100% = 200 in decimal, 0% = 0
+  // Convert percentage to 0-200 range
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  if (percentage > 100) {
+    percentage = 100;
+  }
+  percentage = percentage * 2;
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_POWER_CONFIG, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_PERCENTAGE_REMAINING_ID, &percentage,
+    false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set battery percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  log_v("Battery percentage updated");
+  return true;
+}
+
+bool ZigbeeEP::setBatteryVoltage(uint8_t voltage) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_POWER_CONFIG, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_VOLTAGE_ID, &voltage, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set battery voltage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  log_v("Battery voltage updated");
+  return true;
+}
+
+bool ZigbeeEP::reportBatteryPercentage() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_POWER_CONFIG_BATTERY_PERCENTAGE_REMAINING_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_POWER_CONFIG;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to report battery percentage: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Battery percentage reported");
+  return true;
+}
+
+char *ZigbeeEP::readManufacturer(uint8_t endpoint, uint16_t short_addr, esp_zb_ieee_addr_t ieee_addr) {
+  /* Read peer Manufacture Name & Model Identifier */
+  esp_zb_zcl_read_attr_cmd_t read_req;
+
+  if (short_addr != 0) {
+    read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+  } else {
+    read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+  }
+
+  read_req.zcl_basic_cmd.src_endpoint = _endpoint;
+  read_req.zcl_basic_cmd.dst_endpoint = endpoint;
+  read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_BASIC;
+
+  uint16_t attributes[] = {
+    ESP_ZB_ZCL_ATTR_BASIC_MANUFACTURER_NAME_ID,
+  };
+  read_req.attr_number = ZB_ARRAY_LENTH(attributes);
+  read_req.attr_field = attributes;
+
+  if (_read_manufacturer != NULL) {
+    free(_read_manufacturer);
+  }
+  _read_manufacturer = NULL;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_zb_zcl_read_attr_cmd_req(&read_req);
+  esp_zb_lock_release();
+
+  //Wait for response or timeout
+  if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) {
+    log_e("Error while reading manufacturer");
+  }
+  return _read_manufacturer;
+}
+
+char *ZigbeeEP::readModel(uint8_t endpoint, uint16_t short_addr, esp_zb_ieee_addr_t ieee_addr) {
+  /* Read peer Manufacture Name & Model Identifier */
+  esp_zb_zcl_read_attr_cmd_t read_req;
+
+  if (short_addr != 0) {
+    read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    read_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+  } else {
+    read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+  }
+
+  read_req.zcl_basic_cmd.src_endpoint = _endpoint;
+  read_req.zcl_basic_cmd.dst_endpoint = endpoint;
+  read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_BASIC;
+
+  uint16_t attributes[] = {
+    ESP_ZB_ZCL_ATTR_BASIC_MODEL_IDENTIFIER_ID,
+  };
+  read_req.attr_number = ZB_ARRAY_LENTH(attributes);
+  read_req.attr_field = attributes;
+
+  if (_read_model != NULL) {
+    free(_read_model);
+  }
+  _read_model = NULL;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_zb_zcl_read_attr_cmd_req(&read_req);
+  esp_zb_lock_release();
+
+  //Wait for response or timeout
+  if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) {
+    log_e("Error while reading model");
+  }
+  return _read_model;
+}
+
+void ZigbeeEP::printBoundDevices() {
+  log_i("Bound devices:");
+  for ([[maybe_unused]]
+       const auto &device : _bound_devices) {
+    log_i(
+      "Device on endpoint %d, short address: 0x%x, ieee address: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", device->endpoint, device->short_addr,
+      device->ieee_addr[7], device->ieee_addr[6], device->ieee_addr[5], device->ieee_addr[4], device->ieee_addr[3], device->ieee_addr[2], device->ieee_addr[1],
+      device->ieee_addr[0]
+    );
+  }
+}
+
+void ZigbeeEP::printBoundDevices(Print &print) {
+  print.println("Bound devices:");
+  for ([[maybe_unused]]
+       const auto &device : _bound_devices) {
+    print.printf(
+      "Device on endpoint %d, short address: 0x%x, ieee address: %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\r\n", device->endpoint, device->short_addr,
+      device->ieee_addr[7], device->ieee_addr[6], device->ieee_addr[5], device->ieee_addr[4], device->ieee_addr[3], device->ieee_addr[2], device->ieee_addr[1],
+      device->ieee_addr[0]
+    );
+  }
+}
+
+void ZigbeeEP::zbReadBasicCluster(const esp_zb_zcl_attribute_t *attribute) {
+  /* Basic cluster attributes */
+  if (attribute->id == ESP_ZB_ZCL_ATTR_BASIC_MANUFACTURER_NAME_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_CHAR_STRING && attribute->data.value) {
+    zbstring_t *zbstr = (zbstring_t *)attribute->data.value;
+    _read_manufacturer = (char *)malloc(zbstr->len + 1);
+    if (_read_manufacturer == NULL) {
+      log_e("Failed to allocate memory for manufacturer data");
+      xSemaphoreGive(lock);
+      return;
+    }
+    memcpy(_read_manufacturer, zbstr->data, zbstr->len);
+    _read_manufacturer[zbstr->len] = '\0';
+    log_i("Peer Manufacturer is \"%s\"", _read_manufacturer);
+    xSemaphoreGive(lock);
+  }
+  if (attribute->id == ESP_ZB_ZCL_ATTR_BASIC_MODEL_IDENTIFIER_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_CHAR_STRING && attribute->data.value) {
+    zbstring_t *zbstr = (zbstring_t *)attribute->data.value;
+    _read_model = (char *)malloc(zbstr->len + 1);
+    if (_read_model == NULL) {
+      log_e("Failed to allocate memory for model data");
+      xSemaphoreGive(lock);
+      return;
+    }
+    memcpy(_read_model, zbstr->data, zbstr->len);
+    _read_model[zbstr->len] = '\0';
+    log_i("Peer Model is \"%s\"", _read_model);
+    xSemaphoreGive(lock);
+  }
+}
+
+void ZigbeeEP::zbIdentify(const esp_zb_zcl_set_attr_value_message_t *message) {
+  if (message->attribute.id == ESP_ZB_ZCL_CMD_IDENTIFY_IDENTIFY_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) {
+    if (_on_identify != NULL) {
+      _on_identify(*(uint16_t *)message->attribute.data.value);
+    }
+  } else {
+    log_w("Other identify commands are not implemented yet.");
+  }
+}
+
+bool ZigbeeEP::addTimeCluster(tm time, int32_t gmt_offset) {
+  time_t utc_time = 0;
+  // Check if time is set
+  if (time.tm_year > 0) {
+    // Convert time to UTC
+    utc_time = mktime(&time);
+  }
+
+  // Create time cluster server attributes
+  esp_zb_attribute_list_t *time_cluster_server = esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_TIME);
+  esp_err_t ret = esp_zb_time_cluster_add_attr(time_cluster_server, ESP_ZB_ZCL_ATTR_TIME_TIME_ZONE_ID, (void *)&gmt_offset);
+  if (ret != ESP_OK) {
+    log_e("Failed to add time zone attribute: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_time_cluster_add_attr(time_cluster_server, ESP_ZB_ZCL_ATTR_TIME_TIME_ID, (void *)&utc_time);
+  if (ret != ESP_OK) {
+    log_e("Failed to add time attribute: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_time_cluster_add_attr(time_cluster_server, ESP_ZB_ZCL_ATTR_TIME_TIME_STATUS_ID, (void *)&_time_status);
+  if (ret != ESP_OK) {
+    log_e("Failed to add time status attribute: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  // Create time cluster client attributes
+  esp_zb_attribute_list_t *time_cluster_client = esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_TIME);
+  // Add time clusters to cluster list
+  ret = esp_zb_cluster_list_add_time_cluster(_cluster_list, time_cluster_server, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  if (ret != ESP_OK) {
+    log_e("Failed to add time cluster (server role): 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_list_add_time_cluster(_cluster_list, time_cluster_client, ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE);
+  if (ret != ESP_OK) {
+    log_e("Failed to add time cluster (client role): 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeEP::setTime(tm time) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  time_t utc_time = mktime(&time);
+  log_d("Setting time to %lld", utc_time);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_TIME, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_TIME_TIME_ID, &utc_time, false);
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set time: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeEP::setTimezone(int32_t gmt_offset) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  log_d("Setting timezone to %d", gmt_offset);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret =
+    esp_zb_zcl_set_attribute_val(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_TIME, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_TIME_TIME_ZONE_ID, &gmt_offset, false);
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set timezone: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+tm ZigbeeEP::getTime(uint8_t endpoint, int32_t short_addr, esp_zb_ieee_addr_t ieee_addr) {
+  /* Read peer time */
+  esp_zb_zcl_read_attr_cmd_t read_req;
+
+  if (short_addr >= 0) {
+    read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    read_req.zcl_basic_cmd.dst_addr_u.addr_short = (uint16_t)short_addr;
+  } else {
+    read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+  }
+
+  uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_TIME_TIME_ID};
+  read_req.attr_number = ZB_ARRAY_LENTH(attributes);
+  read_req.attr_field = attributes;
+
+  read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TIME;
+
+  read_req.zcl_basic_cmd.dst_endpoint = endpoint;
+  read_req.zcl_basic_cmd.src_endpoint = _endpoint;
+
+  // clear read time
+  _read_time = 0;
+
+  log_v("Reading time from endpoint %d", endpoint);
+  esp_zb_zcl_read_attr_cmd_req(&read_req);
+
+  //Wait for response or timeout
+  if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) {
+    log_e("Error while reading time");
+    return tm();
+  }
+
+  struct tm *timeinfo = localtime(&_read_time);
+  if (timeinfo) {
+    // Update time
+    setTime(*timeinfo);
+    // Update time status to synced
+    _time_status |= 0x02;
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_set_attribute_val(
+      _endpoint, ESP_ZB_ZCL_CLUSTER_ID_TIME, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_TIME_TIME_STATUS_ID, &_time_status, false
+    );
+    esp_zb_lock_release();
+
+    return *timeinfo;
+  } else {
+    log_e("Error while converting time");
+    return tm();
+  }
+}
+
+int32_t ZigbeeEP::getTimezone(uint8_t endpoint, int32_t short_addr, esp_zb_ieee_addr_t ieee_addr) {
+  /* Read peer timezone */
+  esp_zb_zcl_read_attr_cmd_t read_req;
+
+  if (short_addr >= 0) {
+    read_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    read_req.zcl_basic_cmd.dst_addr_u.addr_short = (uint16_t)short_addr;
+  } else {
+    read_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    memcpy(read_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+  }
+
+  uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_TIME_TIME_ZONE_ID};
+  read_req.attr_number = ZB_ARRAY_LENTH(attributes);
+  read_req.attr_field = attributes;
+
+  read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TIME;
+
+  read_req.zcl_basic_cmd.dst_endpoint = endpoint;
+  read_req.zcl_basic_cmd.src_endpoint = _endpoint;
+
+  // clear read timezone
+  _read_timezone = 0;
+
+  log_v("Reading timezone from endpoint %d", endpoint);
+  esp_zb_zcl_read_attr_cmd_req(&read_req);
+
+  //Wait for response or timeout
+  if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) {
+    log_e("Error while reading timezone");
+    return 0;
+  }
+  setTimezone(_read_timezone);
+  return _read_timezone;
+}
+
+void ZigbeeEP::zbReadTimeCluster(const esp_zb_zcl_attribute_t *attribute) {
+  /* Time cluster attributes */
+  if (attribute->id == ESP_ZB_ZCL_ATTR_TIME_TIME_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_UTC_TIME) {
+    log_v("Time attribute received");
+    log_v("Time: %lld", *(uint32_t *)attribute->data.value);
+    _read_time = *(uint32_t *)attribute->data.value;
+    xSemaphoreGive(lock);
+  } else if (attribute->id == ESP_ZB_ZCL_ATTR_TIME_TIME_ZONE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_S32) {
+    log_v("Timezone attribute received");
+    log_v("Timezone: %d", *(int32_t *)attribute->data.value);
+    _read_timezone = *(int32_t *)attribute->data.value;
+    xSemaphoreGive(lock);
+  }
+}
+
+// typedef struct esp_zb_ota_cluster_cfg_s {
+//     uint32_t ota_upgrade_file_version;            /*!<  The attribute indicates the file version of the running firmware image on the device */
+//     uint16_t ota_upgrade_manufacturer;            /*!<  The attribute indicates the value for the manufacturer of the device */
+//     uint16_t ota_upgrade_image_type;              /*!<  The attribute indicates the the image type of the file that the client is currently downloading */
+//     uint32_t ota_upgrade_downloaded_file_ver;     /*!<  The attribute indicates the file version of the downloaded image on the device*/
+// esp_zb_ota_cluster_cfg_t;
+
+// typedef struct esp_zb_zcl_ota_upgrade_client_variable_s {
+//     uint16_t timer_query;  /*!< The field indicates the time of querying OTA image for OTA upgrade client */
+//     uint16_t hw_version;   /*!< The hardware version */
+//     uint8_t max_data_size; /*!< The maximum size of OTA data */
+// } esp_zb_zcl_ota_upgrade_client_variable_t;
+
+bool ZigbeeEP::addOTAClient(
+  uint32_t file_version, uint32_t downloaded_file_ver, uint16_t hw_version, uint16_t manufacturer, uint16_t image_type, uint8_t max_data_size
+) {
+
+  esp_zb_ota_cluster_cfg_t ota_cluster_cfg = {};
+  ota_cluster_cfg.ota_upgrade_file_version = file_version;                //OTA_UPGRADE_RUNNING_FILE_VERSION;
+  ota_cluster_cfg.ota_upgrade_downloaded_file_ver = downloaded_file_ver;  //OTA_UPGRADE_DOWNLOADED_FILE_VERSION;
+  ota_cluster_cfg.ota_upgrade_manufacturer = manufacturer;                //OTA_UPGRADE_MANUFACTURER;
+  ota_cluster_cfg.ota_upgrade_image_type = image_type;                    //OTA_UPGRADE_IMAGE_TYPE;
+
+  esp_zb_attribute_list_t *ota_cluster = esp_zb_ota_cluster_create(&ota_cluster_cfg);
+
+  esp_zb_zcl_ota_upgrade_client_variable_t variable_config = {};
+  variable_config.timer_query = ESP_ZB_ZCL_OTA_UPGRADE_QUERY_TIMER_COUNT_DEF;
+  variable_config.hw_version = hw_version;        //OTA_UPGRADE_HW_VERSION;
+  variable_config.max_data_size = max_data_size;  //OTA_UPGRADE_MAX_DATA_SIZE;
+
+  uint16_t ota_upgrade_server_addr = 0xffff;
+  uint8_t ota_upgrade_server_ep = 0xff;
+
+  esp_err_t ret = esp_zb_ota_cluster_add_attr(ota_cluster, ESP_ZB_ZCL_ATTR_OTA_UPGRADE_CLIENT_DATA_ID, (void *)&variable_config);
+  if (ret != ESP_OK) {
+    log_e("Failed to add OTA client data: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_ota_cluster_add_attr(ota_cluster, ESP_ZB_ZCL_ATTR_OTA_UPGRADE_SERVER_ADDR_ID, (void *)&ota_upgrade_server_addr);
+  if (ret != ESP_OK) {
+    log_e("Failed to add OTA server address: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_ota_cluster_add_attr(ota_cluster, ESP_ZB_ZCL_ATTR_OTA_UPGRADE_SERVER_ENDPOINT_ID, (void *)&ota_upgrade_server_ep);
+  if (ret != ESP_OK) {
+    log_e("Failed to add OTA server endpoint: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_list_add_ota_cluster(_cluster_list, ota_cluster, ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE);
+  if (ret != ESP_OK) {
+    log_e("Failed to add OTA cluster: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+static void findOTAServer(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) {
+  if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) {
+    esp_zb_ota_upgrade_client_query_interval_set(*((uint8_t *)user_ctx), OTA_UPGRADE_QUERY_INTERVAL);
+    esp_zb_ota_upgrade_client_query_image_req(addr, endpoint);
+    log_i("Query OTA upgrade from server endpoint: %d after %d seconds", endpoint, OTA_UPGRADE_QUERY_INTERVAL);
+  } else {
+    log_w("No OTA Server found");
+  }
+}
+
+void ZigbeeEP::requestOTAUpdate() {
+  esp_zb_zdo_match_desc_req_param_t req;
+  uint16_t cluster_list[] = {ESP_ZB_ZCL_CLUSTER_ID_OTA_UPGRADE};
+
+  /* Match the OTA server of coordinator */
+  req.addr_of_interest = 0x0000;
+  req.dst_nwk_addr = 0x0000;
+  req.num_in_clusters = 1;
+  req.num_out_clusters = 0;
+  req.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  req.cluster_list = cluster_list;
+  esp_zb_lock_acquire(portMAX_DELAY);
+  if (esp_zb_bdb_dev_joined()) {
+    esp_zb_zdo_match_cluster(&req, findOTAServer, &_endpoint);
+  }
+  esp_zb_lock_release();
+}
+
+const char *ZigbeeEP::esp_zb_zcl_status_to_name(esp_zb_zcl_status_t status) {
+  switch (status) {
+    case ESP_ZB_ZCL_STATUS_SUCCESS:               return "Success";
+    case ESP_ZB_ZCL_STATUS_FAIL:                  return "Fail";
+    case ESP_ZB_ZCL_STATUS_NOT_AUTHORIZED:        return "Not authorized";
+    case ESP_ZB_ZCL_STATUS_MALFORMED_CMD:         return "Malformed command";
+    case ESP_ZB_ZCL_STATUS_UNSUP_CLUST_CMD:       return "Unsupported cluster command";
+    case ESP_ZB_ZCL_STATUS_UNSUP_GEN_CMD:         return "Unsupported general command";
+    case ESP_ZB_ZCL_STATUS_UNSUP_MANUF_CLUST_CMD: return "Unsupported manufacturer cluster command";
+    case ESP_ZB_ZCL_STATUS_UNSUP_MANUF_GEN_CMD:   return "Unsupported manufacturer general command";
+    case ESP_ZB_ZCL_STATUS_INVALID_FIELD:         return "Invalid field";
+    case ESP_ZB_ZCL_STATUS_UNSUP_ATTRIB:          return "Unsupported attribute";
+    case ESP_ZB_ZCL_STATUS_INVALID_VALUE:         return "Invalid value";
+    case ESP_ZB_ZCL_STATUS_READ_ONLY:             return "Read only";
+    case ESP_ZB_ZCL_STATUS_INSUFF_SPACE:          return "Insufficient space";
+    case ESP_ZB_ZCL_STATUS_DUPE_EXISTS:           return "Duplicate exists";
+    case ESP_ZB_ZCL_STATUS_NOT_FOUND:             return "Not found";
+    case ESP_ZB_ZCL_STATUS_UNREPORTABLE_ATTRIB:   return "Unreportable attribute";
+    case ESP_ZB_ZCL_STATUS_INVALID_TYPE:          return "Invalid type";
+    case ESP_ZB_ZCL_STATUS_WRITE_ONLY:            return "Write only";
+    case ESP_ZB_ZCL_STATUS_INCONSISTENT:          return "Inconsistent";
+    case ESP_ZB_ZCL_STATUS_ACTION_DENIED:         return "Action denied";
+    case ESP_ZB_ZCL_STATUS_TIMEOUT:               return "Timeout";
+    case ESP_ZB_ZCL_STATUS_ABORT:                 return "Abort";
+    case ESP_ZB_ZCL_STATUS_INVALID_IMAGE:         return "Invalid OTA upgrade image";
+    case ESP_ZB_ZCL_STATUS_WAIT_FOR_DATA:         return "Server does not have data block available yet";
+    case ESP_ZB_ZCL_STATUS_NO_IMAGE_AVAILABLE:    return "No image available";
+    case ESP_ZB_ZCL_STATUS_REQUIRE_MORE_IMAGE:    return "Require more image";
+    case ESP_ZB_ZCL_STATUS_NOTIFICATION_PENDING:  return "Notification pending";
+    case ESP_ZB_ZCL_STATUS_HW_FAIL:               return "Hardware failure";
+    case ESP_ZB_ZCL_STATUS_SW_FAIL:               return "Software failure";
+    case ESP_ZB_ZCL_STATUS_CALIB_ERR:             return "Calibration error";
+    case ESP_ZB_ZCL_STATUS_UNSUP_CLUST:           return "Cluster is not found on the target endpoint";
+    case ESP_ZB_ZCL_STATUS_LIMIT_REACHED:         return "Limit reached";
+    default:                                      return "Unknown status";
+  }
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ZigbeeEP.h b/libraries/Zigbee/src/ZigbeeEP.h
new file mode 100644
index 00000000000..e13b3b59de9
--- /dev/null
+++ b/libraries/Zigbee/src/ZigbeeEP.h
@@ -0,0 +1,170 @@
+/* Common Class for Zigbee End point */
+
+#pragma once
+
+#include "ZigbeeCore.h"
+#if CONFIG_ZB_ENABLED
+
+#include <Arduino.h>
+#include <ColorFormat.h>
+
+/* Useful defines */
+#define ZB_CMD_TIMEOUT             10000     // 10 seconds
+#define OTA_UPGRADE_QUERY_INTERVAL (1 * 60)  // 1 hour = 60 minutes
+
+#define ZB_ARRAY_LENTH(arr) (sizeof(arr) / sizeof(arr[0]))
+
+#define RGB_TO_XYZ(r, g, b, X, Y, Z)                               \
+  {                                                                \
+    X = (float)(0.412453 * (r) + 0.357580 * (g) + 0.180423 * (b)); \
+    Y = (float)(0.212671 * (r) + 0.715160 * (g) + 0.072169 * (b)); \
+    Z = (float)(0.019334 * (r) + 0.119193 * (g) + 0.950227 * (b)); \
+  }
+
+typedef struct zbstring_s {
+  uint8_t len;
+  char data[];
+} ESP_ZB_PACKED_STRUCT zbstring_t;
+
+typedef struct zb_device_params_s {
+  esp_zb_ieee_addr_t ieee_addr;
+  uint8_t endpoint;
+  uint16_t short_addr;
+} zb_device_params_t;
+
+typedef enum {
+  ZB_POWER_SOURCE_UNKNOWN = 0x00,
+  ZB_POWER_SOURCE_MAINS = 0x01,
+  ZB_POWER_SOURCE_BATTERY = 0x03,
+} zb_power_source_t;
+
+/* Zigbee End Device Class */
+class ZigbeeEP {
+public:
+  // constants and limits
+  static constexpr size_t ZB_MAX_NAME_LENGTH = 32;
+
+  // constructors and destructor
+  ZigbeeEP(uint8_t endpoint = 10);
+  ~ZigbeeEP() {}
+
+  // Set ep config and cluster list
+  void setEpConfig(esp_zb_endpoint_config_t ep_config, esp_zb_cluster_list_t *cluster_list) {
+    _ep_config = ep_config;
+    _cluster_list = cluster_list;
+  }
+
+  void setVersion(uint8_t version);
+  uint8_t getEndpoint() {
+    return _endpoint;
+  }
+
+  void printBoundDevices();
+  void printBoundDevices(Print &print);
+
+  std::list<zb_device_params_t *> getBoundDevices() const {
+    return _bound_devices;
+  }
+
+  static bool bound() {
+    return _is_bound;
+  }
+  static void allowMultipleBinding(bool bind) {
+    _allow_multiple_binding = bind;
+  }
+
+  // Set Manufacturer name and model
+  bool setManufacturerAndModel(const char *name, const char *model);
+
+  // Methods to read manufacturer and model name from selected endpoint and short address
+  char *readManufacturer(uint8_t endpoint, uint16_t short_addr, esp_zb_ieee_addr_t ieee_addr);
+  char *readModel(uint8_t endpoint, uint16_t short_addr, esp_zb_ieee_addr_t ieee_addr);
+
+  // Set Power source and battery percentage for battery powered devices
+  bool setPowerSource(zb_power_source_t power_source, uint8_t percentage = 0xff, uint8_t voltage = 0xff);  // voltage in 100mV
+  bool setBatteryPercentage(uint8_t percentage);                                                           // 0-100 %
+  bool setBatteryVoltage(uint8_t voltage);                                                                 // voltage in 100mV (example value 35 for 3.5V)
+  bool reportBatteryPercentage();                                                                          // battery voltage is not reportable attribute
+
+  // Set time
+  bool addTimeCluster(tm time = {}, int32_t gmt_offset = 0);  // gmt offset in seconds
+  bool setTime(tm time);
+  bool setTimezone(int32_t gmt_offset);
+
+  // Get time from Coordinator or specific endpoint (blocking until response)
+  struct tm getTime(uint8_t endpoint = 1, int32_t short_addr = 0x0000, esp_zb_ieee_addr_t ieee_addr = {0});
+  int32_t getTimezone(uint8_t endpoint = 1, int32_t short_addr = 0x0000, esp_zb_ieee_addr_t ieee_addr = {0});  // gmt offset in seconds
+
+  bool epAllowMultipleBinding() {
+    return _allow_multiple_binding;
+  }
+
+  // OTA methods
+  /**
+   * @brief Add OTA client to the Zigbee endpoint.
+   *
+   * @param file_version The current file version of the OTA client.
+   * @param downloaded_file_ver The version of the downloaded file.
+   * @param hw_version The hardware version of the device.
+   * @param manufacturer The manufacturer code (default: 0x1001).
+   * @param image_type The image type code (default: 0x1011).
+   * @param max_data_size The maximum data size for OTA transfer (default and recommended: 223).
+   * @return true if the OTA client was added successfully, false otherwise.
+   */
+  bool addOTAClient(
+    uint32_t file_version, uint32_t downloaded_file_ver, uint16_t hw_version, uint16_t manufacturer = 0x1001, uint16_t image_type = 0x1011,
+    uint8_t max_data_size = 223
+  );
+  /**
+   * @brief Request OTA update from the server, first request is within a minute and the next requests are sent every hour automatically.
+  */
+  void requestOTAUpdate();
+
+  // findEndpoint may be implemented by EPs to find and bind devices
+  virtual void findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req) {};
+
+  // list of all handlers function calls, to be override by EPs implementation
+  virtual void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) {};
+  virtual void zbAttributeRead(uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute) {};
+  virtual void zbReadBasicCluster(const esp_zb_zcl_attribute_t *attribute);  //already implemented
+  virtual void zbIdentify(const esp_zb_zcl_set_attr_value_message_t *message);
+  virtual void zbWindowCoveringMovementCmd(const esp_zb_zcl_window_covering_movement_message_t *message) {};
+  virtual void zbReadTimeCluster(const esp_zb_zcl_attribute_t *attribute);  //already implemented
+  virtual void zbIASZoneStatusChangeNotification(const esp_zb_zcl_ias_zone_status_change_notification_message_t *message) {};
+  virtual void zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) {};
+
+  virtual void addBoundDevice(zb_device_params_t *device) {
+    _bound_devices.push_back(device);
+    _is_bound = true;
+  }
+
+  void onIdentify(void (*callback)(uint16_t)) {
+    _on_identify = callback;
+  }
+
+private:
+  char *_read_manufacturer;
+  char *_read_model;
+  void (*_on_identify)(uint16_t time);
+  time_t _read_time;
+  int32_t _read_timezone;
+
+protected:
+  // Convert ZCL status to name
+  const char *esp_zb_zcl_status_to_name(esp_zb_zcl_status_t status);
+
+  uint8_t _endpoint;
+  esp_zb_ha_standard_devices_t _device_id;
+  esp_zb_endpoint_config_t _ep_config;
+  esp_zb_cluster_list_t *_cluster_list;
+  static bool _is_bound;
+  static bool _allow_multiple_binding;
+  std::list<zb_device_params_t *> _bound_devices;
+  SemaphoreHandle_t lock;
+  zb_power_source_t _power_source;
+  uint8_t _time_status;
+
+  friend class ZigbeeCore;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ZigbeeHandlers.cpp b/libraries/Zigbee/src/ZigbeeHandlers.cpp
new file mode 100644
index 00000000000..eeeb1e8013a
--- /dev/null
+++ b/libraries/Zigbee/src/ZigbeeHandlers.cpp
@@ -0,0 +1,400 @@
+/* Zigbee Common Functions */
+#include "ZigbeeCore.h"
+#include "Arduino.h"
+
+#if CONFIG_ZB_ENABLED
+
+#include "esp_ota_ops.h"
+#if CONFIG_ZB_DELTA_OTA  // Delta OTA, code is prepared for this feature but not enabled by default
+#include "esp_delta_ota_ops.h"
+#endif
+
+//OTA Upgrade defines and variables
+#define OTA_ELEMENT_HEADER_LEN 6 /* OTA element format header size include tag identifier and length field */
+
+/**
+ * @name Enumeration for the tag identifier denotes the type and format of the data within the element
+ * @anchor esp_ota_element_tag_id_t
+ */
+typedef enum esp_ota_element_tag_id_e {
+  UPGRADE_IMAGE = 0x0000, /*!< Upgrade image */
+} esp_ota_element_tag_id_t;
+
+static const esp_partition_t *s_ota_partition = NULL;
+static esp_ota_handle_t s_ota_handle = 0;
+static bool s_tagid_received = false;
+
+// forward declaration of all implemented handlers
+static esp_err_t zb_attribute_set_handler(const esp_zb_zcl_set_attr_value_message_t *message);
+static esp_err_t zb_attribute_reporting_handler(const esp_zb_zcl_report_attr_message_t *message);
+static esp_err_t zb_cmd_read_attr_resp_handler(const esp_zb_zcl_cmd_read_attr_resp_message_t *message);
+static esp_err_t zb_configure_report_resp_handler(const esp_zb_zcl_cmd_config_report_resp_message_t *message);
+static esp_err_t zb_cmd_ias_zone_status_change_handler(const esp_zb_zcl_ias_zone_status_change_notification_message_t *message);
+static esp_err_t zb_cmd_ias_zone_enroll_response_handler(const esp_zb_zcl_ias_zone_enroll_response_message_t *message);
+static esp_err_t zb_cmd_default_resp_handler(const esp_zb_zcl_cmd_default_resp_message_t *message);
+static esp_err_t zb_window_covering_movement_resp_handler(const esp_zb_zcl_window_covering_movement_message_t *message);
+static esp_err_t zb_ota_upgrade_status_handler(const esp_zb_zcl_ota_upgrade_value_message_t *message);
+static esp_err_t zb_ota_upgrade_query_image_resp_handler(const esp_zb_zcl_ota_upgrade_query_image_resp_message_t *message);
+
+// Zigbee action handlers
+[[maybe_unused]]
+static esp_err_t zb_action_handler(esp_zb_core_action_callback_id_t callback_id, const void *message) {
+  esp_err_t ret = ESP_OK;
+  switch (callback_id) {
+    case ESP_ZB_CORE_SET_ATTR_VALUE_CB_ID:         ret = zb_attribute_set_handler((esp_zb_zcl_set_attr_value_message_t *)message); break;
+    case ESP_ZB_CORE_REPORT_ATTR_CB_ID:            ret = zb_attribute_reporting_handler((esp_zb_zcl_report_attr_message_t *)message); break;
+    case ESP_ZB_CORE_CMD_READ_ATTR_RESP_CB_ID:     ret = zb_cmd_read_attr_resp_handler((esp_zb_zcl_cmd_read_attr_resp_message_t *)message); break;
+    case ESP_ZB_CORE_CMD_REPORT_CONFIG_RESP_CB_ID: ret = zb_configure_report_resp_handler((esp_zb_zcl_cmd_config_report_resp_message_t *)message); break;
+    case ESP_ZB_CORE_CMD_IAS_ZONE_ZONE_STATUS_CHANGE_NOT_ID:
+      ret = zb_cmd_ias_zone_status_change_handler((esp_zb_zcl_ias_zone_status_change_notification_message_t *)message);
+      break;
+    case ESP_ZB_CORE_IAS_ZONE_ENROLL_RESPONSE_VALUE_CB_ID:
+      ret = zb_cmd_ias_zone_enroll_response_handler((esp_zb_zcl_ias_zone_enroll_response_message_t *)message);
+      break;
+    case ESP_ZB_CORE_WINDOW_COVERING_MOVEMENT_CB_ID:
+      ret = zb_window_covering_movement_resp_handler((esp_zb_zcl_window_covering_movement_message_t *)message);
+      break;
+    case ESP_ZB_CORE_OTA_UPGRADE_VALUE_CB_ID: ret = zb_ota_upgrade_status_handler((esp_zb_zcl_ota_upgrade_value_message_t *)message); break;
+    case ESP_ZB_CORE_OTA_UPGRADE_QUERY_IMAGE_RESP_CB_ID:
+      ret = zb_ota_upgrade_query_image_resp_handler((esp_zb_zcl_ota_upgrade_query_image_resp_message_t *)message);
+      break;
+    case ESP_ZB_CORE_CMD_DEFAULT_RESP_CB_ID: ret = zb_cmd_default_resp_handler((esp_zb_zcl_cmd_default_resp_message_t *)message); break;
+    default:                                 log_w("Receive unhandled Zigbee action(0x%x) callback", callback_id); break;
+  }
+  return ret;
+}
+
+static esp_err_t zb_attribute_set_handler(const esp_zb_zcl_set_attr_value_message_t *message) {
+  if (!message) {
+    log_e("Empty message");
+    return ESP_FAIL;
+  }
+  if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Received message: error status(%d)", message->info.status);
+    return ESP_ERR_INVALID_ARG;
+  }
+
+  log_v(
+    "Received message: endpoint(%d), cluster(0x%x), attribute(0x%x), data size(%d)", message->info.dst_endpoint, message->info.cluster, message->attribute.id,
+    message->attribute.data.size
+  );
+
+  // List through all Zigbee EPs and call the callback function, with the message
+  for (std::list<ZigbeeEP *>::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) {
+    if (message->info.dst_endpoint == (*it)->getEndpoint()) {
+      if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_IDENTIFY) {
+        (*it)->zbIdentify(message);  //method zbIdentify implemented in the common EP class
+      } else {
+        (*it)->zbAttributeSet(message);  //method zbAttributeSet must be implemented in specific EP class
+      }
+    }
+  }
+  return ESP_OK;
+}
+
+static esp_err_t zb_attribute_reporting_handler(const esp_zb_zcl_report_attr_message_t *message) {
+  if (!message) {
+    log_e("Empty message");
+    return ESP_FAIL;
+  }
+  if (message->status != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Received message: error status(%d)", message->status);
+    return ESP_ERR_INVALID_ARG;
+  }
+  log_v(
+    "Received report from address(0x%x) src endpoint(%d) to dst endpoint(%d) cluster(0x%x)", message->src_address.u.short_addr, message->src_endpoint,
+    message->dst_endpoint, message->cluster
+  );
+  // List through all Zigbee EPs and call the callback function, with the message
+  for (std::list<ZigbeeEP *>::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) {
+    if (message->dst_endpoint == (*it)->getEndpoint()) {
+      (*it)->zbAttributeRead(message->cluster, &message->attribute);  //method zbAttributeRead must be implemented in specific EP class
+    }
+  }
+  return ESP_OK;
+}
+
+static esp_err_t zb_cmd_read_attr_resp_handler(const esp_zb_zcl_cmd_read_attr_resp_message_t *message) {
+  if (!message) {
+    log_e("Empty message");
+    return ESP_FAIL;
+  }
+  if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Received message: error status(%d)", message->info.status);
+    return ESP_ERR_INVALID_ARG;
+  }
+  log_v(
+    "Read attribute response: from address(0x%x) src endpoint(%d) to dst endpoint(%d) cluster(0x%x)", message->info.src_address.u.short_addr,
+    message->info.src_endpoint, message->info.dst_endpoint, message->info.cluster
+  );
+
+  for (std::list<ZigbeeEP *>::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) {
+    if (message->info.dst_endpoint == (*it)->getEndpoint()) {
+      esp_zb_zcl_read_attr_resp_variable_t *variable = message->variables;
+      while (variable) {
+        log_v(
+          "Read attribute response: status(%d), cluster(0x%x), attribute(0x%x), type(0x%x), value(%d)", variable->status, message->info.cluster,
+          variable->attribute.id, variable->attribute.data.type, variable->attribute.data.value ? *(uint8_t *)variable->attribute.data.value : 0
+        );
+        if (variable->status == ESP_ZB_ZCL_STATUS_SUCCESS) {
+          if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_BASIC) {
+            (*it)->zbReadBasicCluster(&variable->attribute);  //method zbReadBasicCluster implemented in the common EP class
+          } else if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_TIME) {
+            (*it)->zbReadTimeCluster(&variable->attribute);  //method zbReadTimeCluster implemented in the common EP class
+          } else {
+            (*it)->zbAttributeRead(message->info.cluster, &variable->attribute);  //method zbAttributeRead must be implemented in specific EP class
+          }
+        }
+        variable = variable->next;
+      }
+    }
+  }
+  return ESP_OK;
+}
+
+static esp_err_t zb_configure_report_resp_handler(const esp_zb_zcl_cmd_config_report_resp_message_t *message) {
+  if (!message) {
+    log_e("Empty message");
+    return ESP_FAIL;
+  }
+  if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Received message: error status(%d)", message->info.status);
+    return ESP_ERR_INVALID_ARG;
+  }
+  esp_zb_zcl_config_report_resp_variable_t *variable = message->variables;
+  while (variable) {
+    log_v(
+      "Configure report response: status(%d), cluster(0x%x), direction(0x%x), attribute(0x%x)", variable->status, message->info.cluster, variable->direction,
+      variable->attribute_id
+    );
+    variable = variable->next;
+  }
+  return ESP_OK;
+}
+
+static esp_err_t zb_cmd_ias_zone_status_change_handler(const esp_zb_zcl_ias_zone_status_change_notification_message_t *message) {
+  if (!message) {
+    log_e("Empty message");
+    return ESP_FAIL;
+  }
+  if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Received message: error status(%d)", message->info.status);
+    return ESP_ERR_INVALID_ARG;
+  }
+  log_v(
+    "IAS Zone Status Notification: from address(0x%x) src endpoint(%d) to dst endpoint(%d) cluster(0x%x)", message->info.src_address.u.short_addr,
+    message->info.src_endpoint, message->info.dst_endpoint, message->info.cluster
+  );
+
+  for (std::list<ZigbeeEP *>::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) {
+    if (message->info.dst_endpoint == (*it)->getEndpoint()) {
+      (*it)->zbIASZoneStatusChangeNotification(message);
+    }
+  }
+  return ESP_OK;
+}
+
+static esp_err_t zb_cmd_ias_zone_enroll_response_handler(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) {
+  if (!message) {
+    log_e("Empty message");
+    return ESP_FAIL;
+  }
+  if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Received message: error status(%d)", message->info.status);
+    return ESP_ERR_INVALID_ARG;
+  }
+  log_v("IAS Zone Enroll Response received");
+  for (std::list<ZigbeeEP *>::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) {
+    if (message->info.dst_endpoint == (*it)->getEndpoint()) {
+      (*it)->zbIASZoneEnrollResponse(message);
+    }
+  }
+  return ESP_OK;
+}
+
+static esp_err_t zb_window_covering_movement_resp_handler(const esp_zb_zcl_window_covering_movement_message_t *message) {
+  if (!message) {
+    log_e("Empty message");
+  }
+  if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Received message: error status(%d)", message->info.status);
+  }
+
+  log_v(
+    "Received message: endpoint(%d), cluster(0x%x), command(0x%x), payload(%d)", message->info.dst_endpoint, message->info.cluster, message->command,
+    message->payload
+  );
+
+  // List through all Zigbee EPs and call the callback function, with the message
+  for (std::list<ZigbeeEP *>::iterator it = Zigbee.ep_objects.begin(); it != Zigbee.ep_objects.end(); ++it) {
+    if (message->info.dst_endpoint == (*it)->getEndpoint()) {
+      (*it)->zbWindowCoveringMovementCmd(message);  //method zbWindowCoveringMovementCmd must be implemented in specific EP class
+    }
+  }
+  return ESP_OK;
+}
+
+static esp_err_t esp_element_ota_data(uint32_t total_size, const void *payload, uint16_t payload_size, void **outbuf, uint16_t *outlen) {
+  static uint16_t tagid = 0;
+  void *data_buf = NULL;
+  uint16_t data_len;
+
+  if (!s_tagid_received) {
+    uint32_t length = 0;
+    if (!payload || payload_size <= OTA_ELEMENT_HEADER_LEN) {
+      log_e("Invalid element format");
+      return ESP_ERR_INVALID_ARG;
+    }
+
+    const uint8_t *payload_ptr = (const uint8_t *)payload;
+    tagid = *(const uint16_t *)payload_ptr;
+    length = *(const uint32_t *)(payload_ptr + sizeof(tagid));
+    if ((length + OTA_ELEMENT_HEADER_LEN) != total_size) {
+      log_e("Invalid element length [%ld/%ld]", length, total_size);
+      return ESP_ERR_INVALID_ARG;
+    }
+
+    s_tagid_received = true;
+
+    data_buf = (void *)(payload_ptr + OTA_ELEMENT_HEADER_LEN);
+    data_len = payload_size - OTA_ELEMENT_HEADER_LEN;
+  } else {
+    data_buf = (void *)payload;
+    data_len = payload_size;
+  }
+
+  switch (tagid) {
+    case UPGRADE_IMAGE:
+      *outbuf = data_buf;
+      *outlen = data_len;
+      break;
+    default:
+      log_e("Unsupported element tag identifier %d", tagid);
+      return ESP_ERR_INVALID_ARG;
+      break;
+  }
+
+  return ESP_OK;
+}
+
+static esp_err_t zb_ota_upgrade_status_handler(const esp_zb_zcl_ota_upgrade_value_message_t *message) {
+  static uint32_t total_size = 0;
+  static uint32_t offset = 0;
+  [[maybe_unused]]
+  static int64_t start_time = 0;
+  esp_err_t ret = ESP_OK;
+
+  if (message->info.status == ESP_ZB_ZCL_STATUS_SUCCESS) {
+    switch (message->upgrade_status) {
+      case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_START:
+        log_i("Zigbee - OTA upgrade start");
+        start_time = esp_timer_get_time();
+        s_ota_partition = esp_ota_get_next_update_partition(NULL);
+        assert(s_ota_partition);
+#if CONFIG_ZB_DELTA_OTA
+        ret = esp_delta_ota_begin(s_ota_partition, 0, &s_ota_handle);
+#else
+        ret = esp_ota_begin(s_ota_partition, 0, &s_ota_handle);
+#endif
+        if (ret != ESP_OK) {
+          log_e("Zigbee - Failed to begin OTA partition, status: %s", esp_err_to_name(ret));
+          return ret;
+        }
+        break;
+      case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_RECEIVE:
+        total_size = message->ota_header.image_size;
+        offset += message->payload_size;
+        log_i("Zigbee - OTA Client receives data: progress [%ld/%ld]", offset, total_size);
+        if (message->payload_size && message->payload) {
+          uint16_t payload_size = 0;
+          void *payload = NULL;
+          ret = esp_element_ota_data(total_size, message->payload, message->payload_size, &payload, &payload_size);
+          if (ret != ESP_OK) {
+            log_e("Zigbee - Failed to element OTA data, status: %s", esp_err_to_name(ret));
+            return ret;
+          }
+#if CONFIG_ZB_DELTA_OTA
+          ret = esp_delta_ota_write(s_ota_handle, payload, payload_size);
+#else
+          ret = esp_ota_write(s_ota_handle, (const void *)payload, payload_size);
+#endif
+          if (ret != ESP_OK) {
+            log_e("Zigbee - Failed to write OTA data to partition, status: %s", esp_err_to_name(ret));
+            return ret;
+          }
+        }
+        break;
+      case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_APPLY: log_i("Zigbee - OTA upgrade apply"); break;
+      case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_CHECK:
+        ret = offset == total_size ? ESP_OK : ESP_FAIL;
+        offset = 0;
+        total_size = 0;
+        s_tagid_received = false;
+        log_i("Zigbee - OTA upgrade check status: %s", esp_err_to_name(ret));
+        break;
+      case ESP_ZB_ZCL_OTA_UPGRADE_STATUS_FINISH:
+        log_i("Zigbee - OTA Finish");
+        log_i(
+          "Zigbee - OTA Information: version: 0x%lx, manufacturer code: 0x%x, image type: 0x%x, total size: %ld bytes, cost time: %lld ms,",
+          message->ota_header.file_version, message->ota_header.manufacturer_code, message->ota_header.image_type, message->ota_header.image_size,
+          (esp_timer_get_time() - start_time) / 1000
+        );
+#if CONFIG_ZB_DELTA_OTA
+        ret = esp_delta_ota_end(s_ota_handle);
+#else
+        ret = esp_ota_end(s_ota_handle);
+#endif
+        if (ret != ESP_OK) {
+          log_e("Zigbee - Failed to end OTA partition, status: %s", esp_err_to_name(ret));
+          return ret;
+        }
+        ret = esp_ota_set_boot_partition(s_ota_partition);
+        if (ret != ESP_OK) {
+          log_e("Zigbee - Failed to set OTA boot partition, status: %s", esp_err_to_name(ret));
+          return ret;
+        }
+        log_w("Zigbee - Prepare to restart system");
+        esp_restart();
+        break;
+      default: log_i("Zigbee - OTA status: %d", message->upgrade_status); break;
+    }
+  }
+  return ret;
+}
+
+static esp_err_t zb_ota_upgrade_query_image_resp_handler(const esp_zb_zcl_ota_upgrade_query_image_resp_message_t *message) {
+  if (message->info.status == ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_i("Zigbee - Queried OTA image from address: 0x%04hx, endpoint: %d", message->server_addr.u.short_addr, message->server_endpoint);
+    log_i("Zigbee - Image version: 0x%lx, manufacturer code: 0x%x, image size: %ld", message->file_version, message->manufacturer_code, message->image_size);
+    if (message->image_size == 0) {
+      log_i("Zigbee - Rejecting OTA image upgrade, image size is 0");
+      return ESP_FAIL;
+    }
+    if (message->file_version == 0) {
+      log_i("Zigbee - Rejecting OTA image upgrade, file version is 0");
+      return ESP_FAIL;
+    }
+    log_i("Zigbee - Approving OTA image upgrade");
+  } else {
+    log_i("Zigbee - OTA image upgrade response status: 0x%x", message->info.status);
+  }
+  return ESP_OK;
+}
+
+static esp_err_t zb_cmd_default_resp_handler(const esp_zb_zcl_cmd_default_resp_message_t *message) {
+  if (!message) {
+    log_e("Empty message");
+    return ESP_FAIL;
+  }
+  if (message->info.status != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Received message: error status(%d)", message->info.status);
+    return ESP_ERR_INVALID_ARG;
+  }
+  log_v(
+    "Received default response: from address(0x%x), src_endpoint(%d) to dst_endpoint(%d), cluster(0x%x) with status 0x%x",
+    message->info.src_address.u.short_addr, message->info.src_endpoint, message->info.dst_endpoint, message->info.cluster, message->status_code
+  );
+  return ESP_OK;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeAnalog.cpp b/libraries/Zigbee/src/ep/ZigbeeAnalog.cpp
new file mode 100644
index 00000000000..a95668b7afe
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeAnalog.cpp
@@ -0,0 +1,123 @@
+#include "ZigbeeAnalog.h"
+#if CONFIG_ZB_ENABLED
+
+ZigbeeAnalog::ZigbeeAnalog(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID;
+
+  //Create basic analog sensor clusters without configuration
+  _cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(_cluster_list, esp_zb_basic_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0};
+}
+
+bool ZigbeeAnalog::addAnalogInput() {
+  esp_err_t ret = esp_zb_cluster_list_add_analog_input_cluster(_cluster_list, esp_zb_analog_input_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  if (ret != ESP_OK) {
+    log_e("Failed to add Analog Input cluster: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  _analog_clusters |= ANALOG_INPUT;
+  return true;
+}
+
+bool ZigbeeAnalog::addAnalogOutput() {
+  esp_err_t ret = esp_zb_cluster_list_add_analog_output_cluster(_cluster_list, esp_zb_analog_output_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  if (ret != ESP_OK) {
+    log_e("Failed to add Analog Output cluster: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  _analog_clusters |= ANALOG_OUTPUT;
+  return true;
+}
+
+//set attribute method -> method overridden in child class
+void ZigbeeAnalog::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) {
+  if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_ANALOG_OUTPUT) {
+    if (message->attribute.id == ESP_ZB_ZCL_ATTR_ANALOG_OUTPUT_PRESENT_VALUE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_SINGLE) {
+      float analog_output = *(float *)message->attribute.data.value;
+      analogOutputChanged(analog_output);
+    } else {
+      log_w("Received message ignored. Attribute ID: %d not supported for Analog Output", message->attribute.id);
+    }
+  } else {
+    log_w("Received message ignored. Cluster ID: %d not supported for Analog endpoint", message->info.cluster);
+  }
+}
+
+void ZigbeeAnalog::analogOutputChanged(float analog_output) {
+  if (_on_analog_output_change) {
+    _on_analog_output_change(analog_output);
+  } else {
+    log_w("No callback function set for analog output change");
+  }
+}
+
+bool ZigbeeAnalog::setAnalogInput(float analog) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  if (!(_analog_clusters & ANALOG_INPUT)) {
+    log_e("Analog Input cluster not added");
+    return false;
+  }
+  log_d("Setting analog input to %.1f", analog);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ANALOG_INPUT_PRESENT_VALUE_ID, &analog, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set analog input: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeAnalog::reportAnalogInput() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_ANALOG_INPUT_PRESENT_VALUE_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send Analog Input report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Analog Input report sent");
+  return true;
+}
+
+bool ZigbeeAnalog::setAnalogInputReporting(uint16_t min_interval, uint16_t max_interval, float delta) {
+  esp_zb_zcl_reporting_info_t reporting_info;
+  memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t));
+  reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV;
+  reporting_info.ep = _endpoint;
+  reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ANALOG_INPUT;
+  reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE;
+  reporting_info.attr_id = ESP_ZB_ZCL_ATTR_ANALOG_INPUT_PRESENT_VALUE_ID;
+  reporting_info.u.send_info.min_interval = min_interval;
+  reporting_info.u.send_info.max_interval = max_interval;
+  reporting_info.u.send_info.def_min_interval = min_interval;
+  reporting_info.u.send_info.def_max_interval = max_interval;
+  reporting_info.u.send_info.delta.s32 = delta;
+  reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to set Analog Input reporting: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeAnalog.h b/libraries/Zigbee/src/ep/ZigbeeAnalog.h
new file mode 100644
index 00000000000..03fbc678b6e
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeAnalog.h
@@ -0,0 +1,57 @@
+/* Class of Zigbee Analog sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+//enum for bits set to check what analog cluster were added
+enum zigbee_analog_clusters {
+  ANALOG_INPUT = 1,
+  ANALOG_OUTPUT = 2
+};
+
+typedef struct zigbee_analog_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_analog_output_cluster_cfg_t analog_output_cfg;
+  esp_zb_analog_input_cluster_cfg_t analog_input_cfg;
+} zigbee_analog_cfg_t;
+
+class ZigbeeAnalog : public ZigbeeEP {
+public:
+  ZigbeeAnalog(uint8_t endpoint);
+  ~ZigbeeAnalog() {}
+
+  // Add analog clusters
+  bool addAnalogInput();
+  bool addAnalogOutput();
+
+  // Use to set a cb function to be called on analog output change
+  void onAnalogOutputChange(void (*callback)(float analog)) {
+    _on_analog_output_change = callback;
+  }
+
+  // Set the analog input value
+  bool setAnalogInput(float analog);
+
+  // Report Analog Input value
+  bool reportAnalogInput();
+
+  // Set reporting for Analog Input
+  bool setAnalogInputReporting(uint16_t min_interval, uint16_t max_interval, float delta);
+
+private:
+  void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override;
+
+  void (*_on_analog_output_change)(float);
+  void analogOutputChanged(float analog_output);
+
+  uint8_t _analog_clusters;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.cpp
new file mode 100644
index 00000000000..2b8271f09a9
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.cpp
@@ -0,0 +1,126 @@
+#include "ZigbeeCarbonDioxideSensor.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *zigbee_carbon_dioxide_sensor_clusters_create(zigbee_carbon_dioxide_sensor_cfg_t *carbon_dioxide_sensor) {
+  esp_zb_basic_cluster_cfg_t *basic_cfg = carbon_dioxide_sensor ? &(carbon_dioxide_sensor->basic_cfg) : NULL;
+  esp_zb_identify_cluster_cfg_t *identify_cfg = carbon_dioxide_sensor ? &(carbon_dioxide_sensor->identify_cfg) : NULL;
+  esp_zb_carbon_dioxide_measurement_cluster_cfg_t *carbon_dioxide_meas_cfg = carbon_dioxide_sensor ? &(carbon_dioxide_sensor->carbon_dioxide_meas_cfg) : NULL;
+  esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_carbon_dioxide_measurement_cluster(
+    cluster_list, esp_zb_carbon_dioxide_measurement_cluster_create(carbon_dioxide_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE
+  );
+  return cluster_list;
+}
+
+ZigbeeCarbonDioxideSensor::ZigbeeCarbonDioxideSensor(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID;
+
+  //Create custom pressure sensor configuration
+  zigbee_carbon_dioxide_sensor_cfg_t carbon_dioxide_sensor_cfg = ZIGBEE_DEFAULT_CARBON_DIOXIDE_SENSOR_CONFIG();
+  _cluster_list = zigbee_carbon_dioxide_sensor_clusters_create(&carbon_dioxide_sensor_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0};
+}
+
+bool ZigbeeCarbonDioxideSensor::setMinMaxValue(float min, float max) {
+  float zb_min = min / 1000000.0f;
+  float zb_max = max / 1000000.0f;
+  esp_zb_attribute_list_t *carbon_dioxide_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(carbon_dioxide_measure_cluster, ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MIN_MEASURED_VALUE_ID, (void *)&zb_min);
+  if (ret != ESP_OK) {
+    log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(carbon_dioxide_measure_cluster, ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MAX_MEASURED_VALUE_ID, (void *)&zb_max);
+  if (ret != ESP_OK) {
+    log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeCarbonDioxideSensor::setTolerance(float tolerance) {
+  float zb_tolerance = tolerance / 1000000.0f;
+  esp_zb_attribute_list_t *carbon_dioxide_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_carbon_dioxide_measurement_cluster_add_attr(
+    carbon_dioxide_measure_cluster, ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_TOLERANCE_ID, (void *)&zb_tolerance
+  );
+  if (ret != ESP_OK) {
+    log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeCarbonDioxideSensor::setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta) {
+  esp_zb_zcl_reporting_info_t reporting_info;
+  memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t));
+  reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV;
+  reporting_info.ep = _endpoint;
+  reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT;
+  reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE;
+  reporting_info.attr_id = ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MEASURED_VALUE_ID;
+  reporting_info.u.send_info.min_interval = min_interval;
+  reporting_info.u.send_info.max_interval = max_interval;
+  reporting_info.u.send_info.def_min_interval = min_interval;
+  reporting_info.u.send_info.def_max_interval = max_interval;
+  reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+  float delta_f = delta / 1000000.0f;
+  memcpy(&reporting_info.u.send_info.delta.s32, &delta_f, sizeof(float));
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeCarbonDioxideSensor::setCarbonDioxide(float carbon_dioxide) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  float zb_carbon_dioxide = carbon_dioxide / 1000000.0f;
+  log_v("Updating carbon dioxide sensor value...");
+  /* Update carbon dioxide sensor measured value */
+  log_d("Setting carbon dioxide to %0.1f", carbon_dioxide);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MEASURED_VALUE_ID,
+    &zb_carbon_dioxide, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set carbon dioxide: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeCarbonDioxideSensor::report() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_CARBON_DIOXIDE_MEASUREMENT_MEASURED_VALUE_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_CARBON_DIOXIDE_MEASUREMENT;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send carbon dioxide report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Carbon dioxide report sent");
+  return true;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.h b/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.h
new file mode 100644
index 00000000000..e0a6de48648
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeCarbonDioxideSensor.h
@@ -0,0 +1,61 @@
+/* Class of Zigbee Pressure sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+// clang-format off
+#define ZIGBEE_DEFAULT_CARBON_DIOXIDE_SENSOR_CONFIG()                     \
+  {                                                                       \
+    .basic_cfg =                                                          \
+      {                                                                   \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,        \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,      \
+      },                                                                  \
+    .identify_cfg =                                                       \
+      {                                                                   \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \
+      },                                                                  \
+    .carbon_dioxide_meas_cfg =                                            \
+      {                                                                   \
+        .measured_value = 0.0,                                            \
+        .min_measured_value = 0.0,                                        \
+        .max_measured_value = 1.0,                                        \
+      },                                                                  \
+  }
+// clang-format on
+
+typedef struct zigbee_carbon_dioxide_sensor_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_carbon_dioxide_measurement_cluster_cfg_t carbon_dioxide_meas_cfg;
+} zigbee_carbon_dioxide_sensor_cfg_t;
+
+class ZigbeeCarbonDioxideSensor : public ZigbeeEP {
+public:
+  ZigbeeCarbonDioxideSensor(uint8_t endpoint);
+  ~ZigbeeCarbonDioxideSensor() {}
+
+  // Set the carbon dioxide value in ppm
+  bool setCarbonDioxide(float carbon_dioxide);
+
+  // Set the min and max value for the carbon dioxide sensor in ppm
+  bool setMinMaxValue(float min, float max);
+
+  // Set the tolerance value for the carbon dioxide sensor in ppm
+  bool setTolerance(float tolerance);
+
+  // Set the reporting interval for carbon dioxide measurement in seconds and delta (carbon dioxide change in ppm)
+  // NOTE: Delta reporting is currently not supported by the carbon dioxide sensor
+  bool setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta);
+
+  // Report the carbon dioxide value
+  bool report();
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.cpp b/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.cpp
new file mode 100644
index 00000000000..caac73b5c68
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.cpp
@@ -0,0 +1,209 @@
+#include "ZigbeeColorDimmableLight.h"
+#if CONFIG_ZB_ENABLED
+
+ZigbeeColorDimmableLight::ZigbeeColorDimmableLight(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_COLOR_DIMMABLE_LIGHT_DEVICE_ID;
+
+  esp_zb_color_dimmable_light_cfg_t light_cfg = ZIGBEE_DEFAULT_COLOR_DIMMABLE_LIGHT_CONFIG();
+  _cluster_list = esp_zb_color_dimmable_light_clusters_create(&light_cfg);
+
+  //Add support for hue and saturation
+  uint8_t hue = 0;
+  uint8_t saturation = 0;
+
+  esp_zb_attribute_list_t *color_cluster = esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_color_control_cluster_add_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID, &hue);
+  esp_zb_color_control_cluster_add_attr(color_cluster, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID, &saturation);
+
+  _ep_config = {
+    .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_COLOR_DIMMABLE_LIGHT_DEVICE_ID, .app_device_version = 0
+  };
+
+  //set default values
+  _current_state = false;
+  _current_level = 255;
+  _current_color = {255, 255, 255};
+}
+
+uint16_t ZigbeeColorDimmableLight::getCurrentColorX() {
+  return (*(uint16_t *)esp_zb_zcl_get_attribute(
+             _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID
+  )
+             ->data_p);
+}
+
+uint16_t ZigbeeColorDimmableLight::getCurrentColorY() {
+  return (*(uint16_t *)esp_zb_zcl_get_attribute(
+             _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID
+  )
+             ->data_p);
+}
+
+uint8_t ZigbeeColorDimmableLight::getCurrentColorHue() {
+  return (*(uint8_t *)esp_zb_zcl_get_attribute(
+             _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID
+  )
+             ->data_p);
+}
+
+uint8_t ZigbeeColorDimmableLight::getCurrentColorSaturation() {
+  return (*(uint16_t *)esp_zb_zcl_get_attribute(
+             _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID
+  )
+             ->data_p);
+}
+
+//set attribute method -> method overridden in child class
+void ZigbeeColorDimmableLight::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) {
+  //check the data and call right method
+  if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_ON_OFF) {
+    if (message->attribute.id == ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) {
+      if (_current_state != *(bool *)message->attribute.data.value) {
+        _current_state = *(bool *)message->attribute.data.value;
+        lightChanged();
+      }
+      return;
+    } else {
+      log_w("Received message ignored. Attribute ID: %d not supported for On/Off Light", message->attribute.id);
+    }
+  } else if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL) {
+    if (message->attribute.id == ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) {
+      if (_current_level != *(uint8_t *)message->attribute.data.value) {
+        _current_level = *(uint8_t *)message->attribute.data.value;
+        lightChanged();
+      }
+      return;
+    } else {
+      log_w("Received message ignored. Attribute ID: %d not supported for Level Control", message->attribute.id);
+      //TODO: implement more attributes -> includes/zcl/esp_zigbee_zcl_level.h
+    }
+  } else if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL) {
+    if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) {
+      uint16_t light_color_x = (*(uint16_t *)message->attribute.data.value);
+      uint16_t light_color_y = getCurrentColorY();
+      //calculate RGB from XY and call setColor()
+      _current_color = espXYToRgbColor(255, light_color_x, light_color_y);  //TODO: Check if level is correct
+      lightChanged();
+      return;
+
+    } else if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) {
+      uint16_t light_color_x = getCurrentColorX();
+      uint16_t light_color_y = (*(uint16_t *)message->attribute.data.value);
+      //calculate RGB from XY and call setColor()
+      _current_color = espXYToRgbColor(255, light_color_x, light_color_y);  //TODO: Check if level is correct
+      lightChanged();
+      return;
+    } else if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) {
+      uint8_t light_color_hue = (*(uint8_t *)message->attribute.data.value);
+      _current_color = espHsvToRgbColor(light_color_hue, getCurrentColorSaturation(), 255);
+      lightChanged();
+      return;
+    } else if (message->attribute.id == ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) {
+      uint8_t light_color_saturation = (*(uint8_t *)message->attribute.data.value);
+      _current_color = espHsvToRgbColor(getCurrentColorHue(), light_color_saturation, 255);
+      lightChanged();
+      return;
+    } else {
+      log_w("Received message ignored. Attribute ID: %d not supported for Color Control", message->attribute.id);
+    }
+  } else {
+    log_w("Received message ignored. Cluster ID: %d not supported for Color dimmable Light", message->info.cluster);
+  }
+}
+
+void ZigbeeColorDimmableLight::lightChanged() {
+  if (_on_light_change) {
+    _on_light_change(_current_state, _current_color.r, _current_color.g, _current_color.b, _current_level);
+  }
+}
+
+bool ZigbeeColorDimmableLight::setLight(bool state, uint8_t level, uint8_t red, uint8_t green, uint8_t blue) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  //Update all attributes
+  _current_state = state;
+  _current_level = level;
+  _current_color = {red, green, blue};
+  lightChanged();
+
+  espXyColor_t xy_color = espRgbColorToXYColor(_current_color);
+  espHsvColor_t hsv_color = espRgbColorToHsvColor(_current_color);
+  uint8_t hue = (uint8_t)hsv_color.h;
+
+  log_v("Updating light state: %d, level: %d, color: %d, %d, %d", state, level, red, green, blue);
+  /* Update light clusters */
+  esp_zb_lock_acquire(portMAX_DELAY);
+  //set on/off state
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID, &_current_state, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set light state: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  //set level
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID, &_current_level, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set light level: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  //set x color
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_X_ID, &xy_color.x, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set light xy color: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  //set y color
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_Y_ID, &xy_color.y, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set light y color: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  //set hue
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_HUE_ID, &hue, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set light hue: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  //set saturation
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_COLOR_CONTROL_CURRENT_SATURATION_ID, &hsv_color.s, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set light saturation: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+unlock_and_return:
+  esp_zb_lock_release();
+  return ret == ESP_ZB_ZCL_STATUS_SUCCESS;
+}
+
+bool ZigbeeColorDimmableLight::setLightState(bool state) {
+  return setLight(state, _current_level, _current_color.r, _current_color.g, _current_color.b);
+}
+
+bool ZigbeeColorDimmableLight::setLightLevel(uint8_t level) {
+  return setLight(_current_state, level, _current_color.r, _current_color.g, _current_color.b);
+}
+
+bool ZigbeeColorDimmableLight::setLightColor(uint8_t red, uint8_t green, uint8_t blue) {
+  return setLight(_current_state, _current_level, red, green, blue);
+}
+
+bool ZigbeeColorDimmableLight::setLightColor(espRgbColor_t rgb_color) {
+  return setLight(_current_state, _current_level, rgb_color.r, rgb_color.g, rgb_color.b);
+}
+
+bool ZigbeeColorDimmableLight::setLightColor(espHsvColor_t hsv_color) {
+  espRgbColor_t rgb_color = espHsvColorToRgbColor(hsv_color);
+  return setLight(_current_state, _current_level, rgb_color.r, rgb_color.g, rgb_color.b);
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.h b/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.h
new file mode 100644
index 00000000000..6681f213ad0
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeColorDimmableLight.h
@@ -0,0 +1,108 @@
+/* Class of Zigbee On/Off Light endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+#define ZIGBEE_DEFAULT_COLOR_DIMMABLE_LIGHT_CONFIG()                                     \
+  {                                                                                      \
+    .basic_cfg =                                                                         \
+      {                                                                                  \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                       \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                     \
+      },                                                                                 \
+    .identify_cfg =                                                                      \
+      {                                                                                  \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,                \
+      },                                                                                 \
+    .groups_cfg =                                                                        \
+      {                                                                                  \
+        .groups_name_support_id = ESP_ZB_ZCL_GROUPS_NAME_SUPPORT_DEFAULT_VALUE,          \
+      },                                                                                 \
+    .scenes_cfg =                                                                        \
+      {                                                                                  \
+        .scenes_count = ESP_ZB_ZCL_SCENES_SCENE_COUNT_DEFAULT_VALUE,                     \
+        .current_scene = ESP_ZB_ZCL_SCENES_CURRENT_SCENE_DEFAULT_VALUE,                  \
+        .current_group = ESP_ZB_ZCL_SCENES_CURRENT_GROUP_DEFAULT_VALUE,                  \
+        .scene_valid = ESP_ZB_ZCL_SCENES_SCENE_VALID_DEFAULT_VALUE,                      \
+        .name_support = ESP_ZB_ZCL_SCENES_NAME_SUPPORT_DEFAULT_VALUE,                    \
+      },                                                                                 \
+    .on_off_cfg =                                                                        \
+      {                                                                                  \
+        .on_off = ESP_ZB_ZCL_ON_OFF_ON_OFF_DEFAULT_VALUE,                                \
+      },                                                                                 \
+    .level_cfg =                                                                         \
+      {                                                                                  \
+        .current_level = ESP_ZB_ZCL_LEVEL_CONTROL_CURRENT_LEVEL_DEFAULT_VALUE,           \
+      },                                                                                 \
+    .color_cfg = {                                                                       \
+      .current_x = ESP_ZB_ZCL_COLOR_CONTROL_CURRENT_X_DEF_VALUE,                         \
+      .current_y = ESP_ZB_ZCL_COLOR_CONTROL_CURRENT_Y_DEF_VALUE,                         \
+      .color_mode = ESP_ZB_ZCL_COLOR_CONTROL_COLOR_MODE_DEFAULT_VALUE,                   \
+      .options = ESP_ZB_ZCL_COLOR_CONTROL_OPTIONS_DEFAULT_VALUE,                         \
+      .enhanced_color_mode = ESP_ZB_ZCL_COLOR_CONTROL_ENHANCED_COLOR_MODE_DEFAULT_VALUE, \
+      .color_capabilities = 0x0009,                                                      \
+    },                                                                                   \
+  }
+
+class ZigbeeColorDimmableLight : public ZigbeeEP {
+public:
+  ZigbeeColorDimmableLight(uint8_t endpoint);
+  ~ZigbeeColorDimmableLight() {}
+
+  void onLightChange(void (*callback)(bool, uint8_t, uint8_t, uint8_t, uint8_t)) {
+    _on_light_change = callback;
+  }
+  void restoreLight() {
+    lightChanged();
+  }
+
+  bool setLightState(bool state);
+  bool setLightLevel(uint8_t level);
+  bool setLightColor(uint8_t red, uint8_t green, uint8_t blue);
+  bool setLightColor(espRgbColor_t rgb_color);
+  bool setLightColor(espHsvColor_t hsv_color);
+  bool setLight(bool state, uint8_t level, uint8_t red, uint8_t green, uint8_t blue);
+
+  bool getLightState() {
+    return _current_state;
+  }
+  uint8_t getLightLevel() {
+    return _current_level;
+  }
+  espRgbColor_t getLightColor() {
+    return _current_color;
+  }
+  uint8_t getLightRed() {
+    return _current_color.r;
+  }
+  uint8_t getLightGreen() {
+    return _current_color.g;
+  }
+  uint8_t getLightBlue() {
+    return _current_color.b;
+  }
+
+private:
+  void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override;
+
+  uint16_t getCurrentColorX();
+  uint16_t getCurrentColorY();
+  uint8_t getCurrentColorHue();
+  uint8_t getCurrentColorSaturation();
+
+  void lightChanged();
+  //callback function to be called on light change (State, R, G, B, Level)
+  void (*_on_light_change)(bool, uint8_t, uint8_t, uint8_t, uint8_t);
+
+  bool _current_state;
+  uint8_t _current_level;
+  espRgbColor_t _current_color;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.cpp b/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.cpp
new file mode 100644
index 00000000000..68f287153cb
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.cpp
@@ -0,0 +1,484 @@
+#include "ZigbeeColorDimmerSwitch.h"
+#if CONFIG_ZB_ENABLED
+
+// Initialize the static instance pointer
+ZigbeeColorDimmerSwitch *ZigbeeColorDimmerSwitch::_instance = nullptr;
+
+ZigbeeColorDimmerSwitch::ZigbeeColorDimmerSwitch(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_COLOR_DIMMER_SWITCH_DEVICE_ID;
+  _instance = this;  // Set the static pointer to this instance
+
+  esp_zb_color_dimmable_switch_cfg_t switch_cfg = ESP_ZB_DEFAULT_COLOR_DIMMABLE_SWITCH_CONFIG();
+  _cluster_list = esp_zb_color_dimmable_switch_clusters_create(&switch_cfg);
+
+  _ep_config = {
+    .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_COLOR_DIMMER_SWITCH_DEVICE_ID, .app_device_version = 0
+  };
+}
+
+void ZigbeeColorDimmerSwitch::bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx) {
+  if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) {
+    log_i("Bound successfully!");
+    if (user_ctx) {
+      zb_device_params_t *light = (zb_device_params_t *)user_ctx;
+      log_i("The light originating from address(0x%x) on endpoint(%d)", light->short_addr, light->endpoint);
+      _instance->_bound_devices.push_back(light);
+    }
+    _is_bound = true;
+  } else {
+    log_e("Binding failed!");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) {
+  if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) {
+    log_d("Found light endpoint");
+    esp_zb_zdo_bind_req_param_t bind_req;
+    zb_device_params_t *light = (zb_device_params_t *)malloc(sizeof(zb_device_params_t));
+    light->endpoint = endpoint;
+    light->short_addr = addr;
+    esp_zb_ieee_address_by_short(light->short_addr, light->ieee_addr);
+    esp_zb_get_long_address(bind_req.src_address);
+    bind_req.src_endp = *((uint8_t *)user_ctx);  //_endpoint;
+    bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF;
+    bind_req.dst_addr_mode = ESP_ZB_ZDO_BIND_DST_ADDR_MODE_64_BIT_EXTENDED;
+    memcpy(bind_req.dst_address_u.addr_long, light->ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    bind_req.dst_endp = endpoint;
+    bind_req.req_dst_addr = esp_zb_get_short_address();
+    log_v("Try to bind on/off control of dimmable light");
+    esp_zb_zdo_device_bind_req(&bind_req, bindCb, NULL);
+    bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL;
+    log_v("Try to bind level control of dimmable light");
+    esp_zb_zdo_device_bind_req(&bind_req, bindCb, NULL);
+    bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL;
+    log_v("Try to bind color control of dimmable light");
+    esp_zb_zdo_device_bind_req(&bind_req, bindCb, (void *)light);
+  } else {
+    log_v("No color dimmable light endpoint found");
+  }
+}
+
+// find on_off light endpoint
+void ZigbeeColorDimmerSwitch::findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req) {
+  uint16_t cluster_list[] = {ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL,
+                             ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_ID_COLOR_CONTROL};
+  esp_zb_zdo_match_desc_req_param_t color_dimmable_light_req = {
+    .dst_nwk_addr = cmd_req->dst_nwk_addr,
+    .addr_of_interest = cmd_req->addr_of_interest,
+    .profile_id = ESP_ZB_AF_HA_PROFILE_ID,
+    .num_in_clusters = 3,
+    .num_out_clusters = 3,
+    .cluster_list = cluster_list,
+  };
+  esp_zb_zdo_match_cluster(&color_dimmable_light_req, findCb, &_endpoint);
+}
+
+// Methods to control the light
+void ZigbeeColorDimmerSwitch::lightToggle() {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID;
+    log_v("Sending 'light toggle' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightToggle(uint16_t group_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID;
+    log_v("Sending 'light toggle' command to group address 0x%x", group_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightToggle(uint8_t endpoint, uint16_t short_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID;
+    log_v("Sending 'light toggle' command to endpoint %d, address 0x%x", endpoint, short_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightToggle(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID;
+    memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    log_v(
+      "Sending 'light toggle' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5],
+      ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]
+    );
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOn() {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID;
+    log_v("Sending 'light on' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOn(uint16_t group_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID;
+    log_v("Sending 'light on' command to group address 0x%x", group_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOn(uint8_t endpoint, uint16_t short_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID;
+    log_v("Sending 'light on' command to endpoint %d, address 0x%x", endpoint, short_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOn(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID;
+    memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    log_v(
+      "Sending 'light on' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5],
+      ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]
+    );
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOff() {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID;
+    log_v("Sending 'light off' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOff(uint16_t group_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID;
+    log_v("Sending 'light off' command to group address 0x%x", group_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOff(uint8_t endpoint, uint16_t short_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID;
+    log_v("Sending 'light off' command to endpoint %d, address 0x%x", endpoint, short_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOff(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID;
+    memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    log_v(
+      "Sending 'light off' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5],
+      ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]
+    );
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOffWithEffect(uint8_t effect_id, uint8_t effect_variant) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_off_with_effect_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.effect_id = effect_id;
+    cmd_req.effect_variant = effect_variant;
+    log_v("Sending 'light off with effect' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_off_with_effect_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOnWithSceneRecall() {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_on_with_recall_global_scene_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    log_v("Sending 'light on with scene recall' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_on_with_recall_global_scene_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::lightOnWithTimedOff(uint8_t on_off_control, uint16_t time_on, uint16_t time_off) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_on_with_timed_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.on_off_control = on_off_control;  //TODO: Test how it works, then maybe change API
+    cmd_req.on_time = time_on;
+    cmd_req.off_wait_time = time_off;
+    log_v("Sending 'light on with time off' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_on_with_timed_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::setLightLevel(uint8_t level) {
+  if (_is_bound) {
+    esp_zb_zcl_move_to_level_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.level = level;
+    cmd_req.transition_time = 0xffff;
+    log_v("Sending 'set light level' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_level_move_to_level_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::setLightLevel(uint8_t level, uint16_t group_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_move_to_level_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT;
+    cmd_req.level = level;
+    cmd_req.transition_time = 0xffff;
+    log_v("Sending 'set light level' command to group address 0x%x", group_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_level_move_to_level_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::setLightLevel(uint8_t level, uint8_t endpoint, uint16_t short_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_move_to_level_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    cmd_req.level = level;
+    cmd_req.transition_time = 0xffff;
+    log_v("Sending 'set light level' command to endpoint %d, address 0x%x", endpoint, short_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_level_move_to_level_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::setLightLevel(uint8_t level, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_move_to_level_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    cmd_req.level = level;
+    cmd_req.transition_time = 0xffff;
+    log_v(
+      "Sending 'set light level' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6],
+      ieee_addr[5], ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]
+    );
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_level_move_to_level_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::setLightColor(uint8_t red, uint8_t green, uint8_t blue) {
+  if (_is_bound) {
+    espXyColor_t xy_color = espRgbToXYColor(red, green, blue);
+
+    esp_zb_zcl_color_move_to_color_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.color_x = xy_color.x;
+    cmd_req.color_y = xy_color.y;
+    cmd_req.transition_time = 0;
+    log_v("Sending 'set light color' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_color_move_to_color_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint16_t group_addr) {
+  if (_is_bound) {
+    espXyColor_t xy_color = espRgbToXYColor(red, green, blue);
+
+    esp_zb_zcl_color_move_to_color_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT;
+    cmd_req.color_x = xy_color.x;
+    cmd_req.color_y = xy_color.y;
+    cmd_req.transition_time = 0;
+    log_v("Sending 'set light color' command to group address 0x%x", group_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_color_move_to_color_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint8_t endpoint, uint16_t short_addr) {
+  if (_is_bound) {
+    espXyColor_t xy_color = espRgbToXYColor(red, green, blue);
+
+    esp_zb_zcl_color_move_to_color_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    cmd_req.color_x = xy_color.x;
+    cmd_req.color_y = xy_color.y;
+    cmd_req.transition_time = 0;
+    log_v("Sending 'set light color' command to endpoint %d, address 0x%x", endpoint, short_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_color_move_to_color_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeColorDimmerSwitch::setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) {
+  if (_is_bound) {
+    espXyColor_t xy_color = espRgbToXYColor(red, green, blue);
+
+    esp_zb_zcl_color_move_to_color_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    cmd_req.color_x = xy_color.x;
+    cmd_req.color_y = xy_color.y;
+    cmd_req.transition_time = 0;
+    log_v(
+      "Sending 'set light color' command to endpoint %d,  ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6],
+      ieee_addr[5], ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]
+    );
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_color_move_to_color_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.h b/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.h
new file mode 100644
index 00000000000..dbe50a20230
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeColorDimmerSwitch.h
@@ -0,0 +1,58 @@
+/* Class of Zigbee On/Off Switch endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+class ZigbeeColorDimmerSwitch : public ZigbeeEP {
+public:
+  ZigbeeColorDimmerSwitch(uint8_t endpoint);
+  ~ZigbeeColorDimmerSwitch() {}
+
+  // methods to control the color dimmable light
+  void lightToggle();
+  void lightToggle(uint16_t group_addr);
+  void lightToggle(uint8_t endpoint, uint16_t short_addr);
+  void lightToggle(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr);
+
+  void lightOn();
+  void lightOn(uint16_t group_addr);
+  void lightOn(uint8_t endpoint, uint16_t short_addr);
+  void lightOn(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr);
+
+  void lightOff();
+  void lightOff(uint16_t group_addr);
+  void lightOff(uint8_t endpoint, uint16_t short_addr);
+  void lightOff(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr);
+
+  void lightOffWithEffect(uint8_t effect_id, uint8_t effect_variant);
+  void lightOnWithTimedOff(uint8_t on_off_control, uint16_t time_on, uint16_t time_off);
+  void lightOnWithSceneRecall();
+
+  void setLightLevel(uint8_t level);
+  void setLightLevel(uint8_t level, uint16_t group_addr);
+  void setLightLevel(uint8_t level, uint8_t endpoint, uint16_t short_addr);
+  void setLightLevel(uint8_t level, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr);
+
+  void setLightColor(uint8_t red, uint8_t green, uint8_t blue);
+  void setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint16_t group_addr);
+  void setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint8_t endpoint, uint16_t short_addr);
+  void setLightColor(uint8_t red, uint8_t green, uint8_t blue, uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr);
+
+private:
+  // save instance of the class in order to use it in static functions
+  static ZigbeeColorDimmerSwitch *_instance;
+
+  void findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req);
+  static void bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx);
+  static void findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx);
+
+  void calculateXY(uint8_t red, uint8_t green, uint8_t blue, uint16_t &x, uint16_t &y);
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeContactSwitch.cpp b/libraries/Zigbee/src/ep/ZigbeeContactSwitch.cpp
new file mode 100644
index 00000000000..ced8e43d6ea
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeContactSwitch.cpp
@@ -0,0 +1,111 @@
+#include "ZigbeeContactSwitch.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *zigbee_contact_switch_clusters_create(zigbee_contact_switch_cfg_t *contact_switch) {
+  esp_zb_basic_cluster_cfg_t *basic_cfg = contact_switch ? &(contact_switch->basic_cfg) : NULL;
+  esp_zb_identify_cluster_cfg_t *identify_cfg = contact_switch ? &(contact_switch->identify_cfg) : NULL;
+  esp_zb_ias_zone_cluster_cfg_t *ias_zone_cfg = contact_switch ? &(contact_switch->ias_zone_cfg) : NULL;
+  esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_ias_zone_cluster(cluster_list, esp_zb_ias_zone_cluster_create(ias_zone_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  return cluster_list;
+}
+
+ZigbeeContactSwitch::ZigbeeContactSwitch(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_IAS_ZONE_ID;
+  _zone_status = 0;
+  _zone_id = 0xff;
+  _ias_cie_endpoint = 1;
+
+  //Create custom contact switch configuration
+  zigbee_contact_switch_cfg_t contact_switch_cfg = ZIGBEE_DEFAULT_CONTACT_SWITCH_CONFIG();
+  _cluster_list = zigbee_contact_switch_clusters_create(&contact_switch_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_IAS_ZONE_ID, .app_device_version = 0};
+}
+
+void ZigbeeContactSwitch::setIASClientEndpoint(uint8_t ep_number) {
+  _ias_cie_endpoint = ep_number;
+}
+
+bool ZigbeeContactSwitch::setClosed() {
+  log_v("Setting Contact switch to closed");
+  uint8_t closed = 0;  // ALARM1 = 0, ALARM2 = 0
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &closed, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to set contact switch to closed: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  _zone_status = closed;
+  return report();
+}
+
+bool ZigbeeContactSwitch::setOpen() {
+  log_v("Setting Contact switch to open");
+  uint8_t open = ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM1 | ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM2;  // ALARM1 = 1, ALARM2 = 1
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &open, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to set contact switch to open: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  _zone_status = open;
+  return report();
+}
+
+bool ZigbeeContactSwitch::report() {
+  /* Send IAS Zone status changed notification command */
+
+  esp_zb_zcl_ias_zone_status_change_notif_cmd_t status_change_notif_cmd;
+  status_change_notif_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+  status_change_notif_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  status_change_notif_cmd.zcl_basic_cmd.dst_endpoint = _ias_cie_endpoint;  //default is 1
+  memcpy(status_change_notif_cmd.zcl_basic_cmd.dst_addr_u.addr_long, _ias_cie_addr, sizeof(esp_zb_ieee_addr_t));
+
+  status_change_notif_cmd.zone_status = _zone_status;
+  status_change_notif_cmd.extend_status = 0;
+  status_change_notif_cmd.zone_id = _zone_id;
+  status_change_notif_cmd.delay = 0;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_ias_zone_status_change_notif_cmd_req(&status_change_notif_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send IAS Zone status changed notification: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("IAS Zone status changed notification sent");
+  return true;
+}
+
+void ZigbeeContactSwitch::zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) {
+  if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE) {
+    log_v("IAS Zone Enroll Response: zone id(%d), status(%d)", message->zone_id, message->response_code);
+    if (message->response_code == ESP_ZB_ZCL_IAS_ZONE_ENROLL_RESPONSE_CODE_SUCCESS) {
+      log_v("IAS Zone Enroll Response: success");
+      esp_zb_lock_acquire(portMAX_DELAY);
+      memcpy(
+        _ias_cie_addr,
+        (*(esp_zb_ieee_addr_t *)
+            esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_IAS_CIE_ADDRESS_ID)
+              ->data_p),
+        sizeof(esp_zb_ieee_addr_t)
+      );
+      esp_zb_lock_release();
+      _zone_id = message->zone_id;
+    }
+
+  } else {
+    log_w("Received message ignored. Cluster ID: %d not supported for On/Off Light", message->info.cluster);
+  }
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeContactSwitch.h b/libraries/Zigbee/src/ep/ZigbeeContactSwitch.h
new file mode 100644
index 00000000000..b33effd8dfc
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeContactSwitch.h
@@ -0,0 +1,67 @@
+/* Class of Zigbee contact switch (IAS Zone) endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+// clang-format off
+#define ZIGBEE_DEFAULT_CONTACT_SWITCH_CONFIG()                                                      \
+    {                                                                                               \
+        .basic_cfg =                                                                                \
+            {                                                                                       \
+                .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                          \
+                .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                        \
+            },                                                                                      \
+        .identify_cfg =                                                                             \
+            {                                                                                       \
+                .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,                   \
+            },                                                                                      \
+        .ias_zone_cfg =                                                                             \
+            {                                                                                       \
+                .zone_state = ESP_ZB_ZCL_IAS_ZONE_ZONESTATE_NOT_ENROLLED,                           \
+                .zone_type = ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_CONTACT_SWITCH,                           \
+                .zone_status = 0,                                                                   \
+                .ias_cie_addr = ESP_ZB_ZCL_ZONE_IAS_CIE_ADDR_DEFAULT,                               \
+                .zone_id = 0xff,                                                                    \
+                .zone_ctx = {0, 0, 0, 0},                                                           \
+            },                                                                                      \
+    }
+// clang-format on
+
+typedef struct zigbee_contact_switch_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_ias_zone_cluster_cfg_t ias_zone_cfg;
+} zigbee_contact_switch_cfg_t;
+
+class ZigbeeContactSwitch : public ZigbeeEP {
+public:
+  ZigbeeContactSwitch(uint8_t endpoint);
+  ~ZigbeeContactSwitch() {}
+
+  // Set the IAS Client endpoint number (default is 1)
+  void setIASClientEndpoint(uint8_t ep_number);
+
+  // Set the contact switch value to closed
+  bool setClosed();
+
+  // Set the contact switch value to open
+  bool setOpen();
+
+  // Report the contact switch value, done automatically after setting the position
+  bool report();
+
+private:
+  void zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) override;
+  uint8_t _zone_status;
+  uint8_t _zone_id;
+  esp_zb_ieee_addr_t _ias_cie_addr;
+  uint8_t _ias_cie_endpoint;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeDimmableLight.cpp b/libraries/Zigbee/src/ep/ZigbeeDimmableLight.cpp
new file mode 100644
index 00000000000..05a7e5ad6c1
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeDimmableLight.cpp
@@ -0,0 +1,113 @@
+#include "ZigbeeDimmableLight.h"
+#if CONFIG_ZB_ENABLED
+
+#include "esp_zigbee_cluster.h"
+
+ZigbeeDimmableLight::ZigbeeDimmableLight(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_DIMMABLE_LIGHT_DEVICE_ID;
+
+  zigbee_dimmable_light_cfg_t light_cfg = ZIGBEE_DEFAULT_DIMMABLE_LIGHT_CONFIG();
+  _cluster_list = zigbee_dimmable_light_clusters_create(&light_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_DIMMABLE_LIGHT_DEVICE_ID, .app_device_version = 0};
+
+  // set default values
+  _current_state = false;
+  _current_level = 255;
+}
+
+// set attribute method -> method overridden in child class
+void ZigbeeDimmableLight::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) {
+  // check the data and call right method
+  if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_ON_OFF) {
+    if (message->attribute.id == ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) {
+      if (_current_state != *(bool *)message->attribute.data.value) {
+        _current_state = *(bool *)message->attribute.data.value;
+        lightChanged();
+      }
+      return;
+    } else {
+      log_w("Received message ignored. Attribute ID: %d not supported for On/Off Light", message->attribute.id);
+    }
+  } else if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL) {
+    if (message->attribute.id == ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_U8) {
+      if (_current_level != *(uint8_t *)message->attribute.data.value) {
+        _current_level = *(uint8_t *)message->attribute.data.value;
+        lightChanged();
+      }
+      return;
+    } else {
+      log_w("Received message ignored. Attribute ID: %d not supported for Level Control", message->attribute.id);
+      // TODO: implement more attributes -> includes/zcl/esp_zigbee_zcl_level.h
+    }
+  } else {
+    log_w("Received message ignored. Cluster ID: %d not supported for dimmable Light", message->info.cluster);
+  }
+}
+
+void ZigbeeDimmableLight::lightChanged() {
+  if (_on_light_change) {
+    _on_light_change(_current_state, _current_level);
+  }
+}
+
+bool ZigbeeDimmableLight::setLight(bool state, uint8_t level) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  // Update all attributes
+  _current_state = state;
+  _current_level = level;
+  lightChanged();
+
+  log_v("Updating on/off light state to %d", state);
+  /* Update light clusters */
+  esp_zb_lock_acquire(portMAX_DELAY);
+  // set on/off state
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID, &_current_state, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set light state: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  // set level
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_LEVEL_CONTROL, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_LEVEL_CONTROL_CURRENT_LEVEL_ID, &_current_level, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set light level: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+unlock_and_return:
+  esp_zb_lock_release();
+  return ret == ESP_ZB_ZCL_STATUS_SUCCESS;
+}
+
+bool ZigbeeDimmableLight::setLightState(bool state) {
+  return setLight(state, _current_level);
+}
+
+bool ZigbeeDimmableLight::setLightLevel(uint8_t level) {
+  return setLight(_current_state, level);
+}
+
+esp_zb_cluster_list_t *ZigbeeDimmableLight::zigbee_dimmable_light_clusters_create(zigbee_dimmable_light_cfg_t *light_cfg) {
+  esp_zb_attribute_list_t *esp_zb_basic_cluster = esp_zb_basic_cluster_create(&light_cfg->basic_cfg);
+  esp_zb_attribute_list_t *esp_zb_identify_cluster = esp_zb_identify_cluster_create(&light_cfg->identify_cfg);
+  esp_zb_attribute_list_t *esp_zb_groups_cluster = esp_zb_groups_cluster_create(&light_cfg->groups_cfg);
+  esp_zb_attribute_list_t *esp_zb_scenes_cluster = esp_zb_scenes_cluster_create(&light_cfg->scenes_cfg);
+  esp_zb_attribute_list_t *esp_zb_on_off_cluster = esp_zb_on_off_cluster_create(&light_cfg->on_off_cfg);
+  esp_zb_attribute_list_t *esp_zb_level_cluster = esp_zb_level_cluster_create(&light_cfg->level_cfg);
+
+  // ------------------------------ Create cluster list ------------------------------
+  esp_zb_cluster_list_t *esp_zb_cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(esp_zb_cluster_list, esp_zb_basic_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(esp_zb_cluster_list, esp_zb_identify_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_groups_cluster(esp_zb_cluster_list, esp_zb_groups_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_scenes_cluster(esp_zb_cluster_list, esp_zb_scenes_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_on_off_cluster(esp_zb_cluster_list, esp_zb_on_off_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_level_cluster(esp_zb_cluster_list, esp_zb_level_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+
+  return esp_zb_cluster_list;
+}
+
+#endif  // SOC_IEEE802154_SUPPORTED
diff --git a/libraries/Zigbee/src/ep/ZigbeeDimmableLight.h b/libraries/Zigbee/src/ep/ZigbeeDimmableLight.h
new file mode 100644
index 00000000000..747fdbafaef
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeDimmableLight.h
@@ -0,0 +1,112 @@
+/* Class of Zigbee On/Off Light endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+/**
+ * @brief Zigbee HA standard dimmable light device clusters.
+ *        Added here as not supported by ESP Zigbee library.
+ *
+ *
+ */
+typedef struct zigbee_dimmable_light_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;       /*!<  Basic cluster configuration, @ref esp_zb_basic_cluster_cfg_s */
+  esp_zb_identify_cluster_cfg_t identify_cfg; /*!<  Identify cluster configuration, @ref esp_zb_identify_cluster_cfg_s */
+  esp_zb_groups_cluster_cfg_t groups_cfg;     /*!<  Groups cluster configuration, @ref esp_zb_groups_cluster_cfg_s */
+  esp_zb_scenes_cluster_cfg_t scenes_cfg;     /*!<  Scenes cluster configuration, @ref esp_zb_scenes_cluster_cfg_s */
+  esp_zb_on_off_cluster_cfg_t on_off_cfg;     /*!<  On off cluster configuration, @ref esp_zb_on_off_cluster_cfg_s */
+  esp_zb_level_cluster_cfg_t level_cfg;       /*!<  Level cluster configuration, @ref esp_zb_level_cluster_cfg_s */
+} zigbee_dimmable_light_cfg_t;
+
+/**
+ * @brief Zigbee HA standard dimmable light device default config value.
+ *        Added here as not supported by ESP Zigbee library.
+ *
+ */
+// clang-format off
+#define ZIGBEE_DEFAULT_DIMMABLE_LIGHT_CONFIG()                                  \
+  {                                                                             \
+    .basic_cfg =                                                                \
+      {                                                                         \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,              \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,            \
+      },                                                                        \
+    .identify_cfg =                                                             \
+      {                                                                         \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,       \
+      },                                                                        \
+    .groups_cfg =                                                               \
+      {                                                                         \
+        .groups_name_support_id = ESP_ZB_ZCL_GROUPS_NAME_SUPPORT_DEFAULT_VALUE, \
+      },                                                                        \
+    .scenes_cfg =                                                               \
+      {                                                                         \
+        .scenes_count = ESP_ZB_ZCL_SCENES_SCENE_COUNT_DEFAULT_VALUE,            \
+        .current_scene = ESP_ZB_ZCL_SCENES_CURRENT_SCENE_DEFAULT_VALUE,         \
+        .current_group = ESP_ZB_ZCL_SCENES_CURRENT_GROUP_DEFAULT_VALUE,         \
+        .scene_valid = ESP_ZB_ZCL_SCENES_SCENE_VALID_DEFAULT_VALUE,             \
+        .name_support = ESP_ZB_ZCL_SCENES_NAME_SUPPORT_DEFAULT_VALUE,           \
+      },                                                                        \
+    .on_off_cfg =                                                               \
+      {                                                                         \
+        .on_off = ESP_ZB_ZCL_ON_OFF_ON_OFF_DEFAULT_VALUE,                       \
+      },                                                                        \
+    .level_cfg =                                                                \
+      {                                                                         \
+        .current_level = ESP_ZB_ZCL_LEVEL_CONTROL_CURRENT_LEVEL_DEFAULT_VALUE,  \
+      },                                                                        \
+  }
+// clang-format on
+
+class ZigbeeDimmableLight : public ZigbeeEP {
+public:
+  ZigbeeDimmableLight(uint8_t endpoint);
+  ~ZigbeeDimmableLight() {}
+
+  void onLightChange(void (*callback)(bool, uint8_t)) {
+    _on_light_change = callback;
+  }
+  void restoreLight() {
+    lightChanged();
+  }
+
+  bool setLightState(bool state);
+  bool setLightLevel(uint8_t level);
+  bool setLight(bool state, uint8_t level);
+
+  bool getLightState() {
+    return _current_state;
+  }
+  uint8_t getLightLevel() {
+    return _current_level;
+  }
+
+private:
+  void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override;
+  void lightChanged();
+  // callback function to be called on light change (State, Level)
+  void (*_on_light_change)(bool, uint8_t);
+
+  /**
+   * @brief  Create a standard HA dimmable light cluster list.
+   *        Added here as not supported by ESP Zigbee library.
+   *
+   * @note This contains basic, identify, groups, scenes, on-off, level, as server side.
+   * @param[in] light_cfg  Configuration parameters for this cluster lists defined by @ref zigbee_dimmable_light_cfg_t
+   *
+   * @return Pointer to cluster list  @ref esp_zb_cluster_list_s
+   *
+   */
+  esp_zb_cluster_list_t *zigbee_dimmable_light_clusters_create(zigbee_dimmable_light_cfg_t *light_cfg);
+
+  bool _current_state;
+  uint8_t _current_level;
+};
+
+#endif  // SOC_IEEE802154_SUPPORTED
diff --git a/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.cpp b/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.cpp
new file mode 100644
index 00000000000..c5b62ee2b75
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.cpp
@@ -0,0 +1,127 @@
+#include "ZigbeeDoorWindowHandle.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *zigbee_door_window_handle_clusters_create(zigbee_door_window_handle_cfg_t *door_window_handle) {
+  esp_zb_basic_cluster_cfg_t *basic_cfg = door_window_handle ? &(door_window_handle->basic_cfg) : NULL;
+  esp_zb_identify_cluster_cfg_t *identify_cfg = door_window_handle ? &(door_window_handle->identify_cfg) : NULL;
+  esp_zb_ias_zone_cluster_cfg_t *ias_zone_cfg = door_window_handle ? &(door_window_handle->ias_zone_cfg) : NULL;
+  esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_ias_zone_cluster(cluster_list, esp_zb_ias_zone_cluster_create(ias_zone_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  return cluster_list;
+}
+
+ZigbeeDoorWindowHandle::ZigbeeDoorWindowHandle(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_IAS_ZONE_ID;
+  _zone_status = 0;
+  _zone_id = 0xff;
+  _ias_cie_endpoint = 1;
+
+  //Create custom door window handle configuration
+  zigbee_door_window_handle_cfg_t door_window_handle_cfg = ZIGBEE_DEFAULT_DOOR_WINDOW_HANDLE_CONFIG();
+  _cluster_list = zigbee_door_window_handle_clusters_create(&door_window_handle_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_IAS_ZONE_ID, .app_device_version = 0};
+}
+
+void ZigbeeDoorWindowHandle::setIASClientEndpoint(uint8_t ep_number) {
+  _ias_cie_endpoint = ep_number;
+}
+
+bool ZigbeeDoorWindowHandle::setClosed() {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  log_v("Setting Door/Window handle to closed");
+  uint8_t closed = 0;  // ALARM1 = 0, ALARM2 = 0
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &closed, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set door/window handle to closed: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  _zone_status = closed;
+  return report();
+}
+
+bool ZigbeeDoorWindowHandle::setOpen() {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  log_v("Setting Door/Window handle to open");
+  uint8_t open = ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM1 | ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM2;  // ALARM1 = 1, ALARM2 = 1
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &open, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set door/window handle to open: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  _zone_status = open;
+  return report();
+}
+
+bool ZigbeeDoorWindowHandle::setTilted() {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  log_v("Setting Door/Window handle to tilted");
+  uint8_t tilted = ESP_ZB_ZCL_IAS_ZONE_ZONE_STATUS_ALARM1;  // ALARM1 = 1, ALARM2 = 0
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &tilted, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set door/window handle to tilted: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  _zone_status = tilted;
+  return report();
+}
+
+bool ZigbeeDoorWindowHandle::report() {
+  /* Send IAS Zone status changed notification command */
+
+  esp_zb_zcl_ias_zone_status_change_notif_cmd_t status_change_notif_cmd;
+  status_change_notif_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+  status_change_notif_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  status_change_notif_cmd.zcl_basic_cmd.dst_endpoint = _ias_cie_endpoint;  //default is 1
+  memcpy(status_change_notif_cmd.zcl_basic_cmd.dst_addr_u.addr_long, _ias_cie_addr, sizeof(esp_zb_ieee_addr_t));
+
+  status_change_notif_cmd.zone_status = _zone_status;
+  status_change_notif_cmd.extend_status = 0;
+  status_change_notif_cmd.zone_id = _zone_id;
+  status_change_notif_cmd.delay = 0;
+
+  //NOTE: Check result of esp_zb_zcl_ias_zone_status_change_notif_cmd_req() and return true if success, false if failure
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_zb_zcl_ias_zone_status_change_notif_cmd_req(&status_change_notif_cmd);
+  esp_zb_lock_release();
+  log_v("IAS Zone status changed notification sent");
+  return true;
+}
+
+void ZigbeeDoorWindowHandle::zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) {
+  if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE) {
+    log_v("IAS Zone Enroll Response: zone id(%d), status(%d)", message->zone_id, message->response_code);
+    if (message->response_code == ESP_ZB_ZCL_IAS_ZONE_ENROLL_RESPONSE_CODE_SUCCESS) {
+      log_v("IAS Zone Enroll Response: success");
+      esp_zb_lock_acquire(portMAX_DELAY);
+      memcpy(
+        _ias_cie_addr,
+        (*(esp_zb_ieee_addr_t *)
+            esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_IAS_CIE_ADDRESS_ID)
+              ->data_p),
+        sizeof(esp_zb_ieee_addr_t)
+      );
+      esp_zb_lock_release();
+      _zone_id = message->zone_id;
+    }
+
+  } else {
+    log_w("Received message ignored. Cluster ID: %d not supported for On/Off Light", message->info.cluster);
+  }
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.h b/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.h
new file mode 100644
index 00000000000..efffd34b12f
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeDoorWindowHandle.h
@@ -0,0 +1,71 @@
+/* Class of Zigbee door window handle (IAS Zone) endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+#define ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_DOOR_WINDOW_HANDLE 0x0016
+// clang-format off
+#define ZIGBEE_DEFAULT_DOOR_WINDOW_HANDLE_CONFIG()                                                  \
+    {                                                                                               \
+        .basic_cfg =                                                                                \
+            {                                                                                       \
+                .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                          \
+                .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                        \
+            },                                                                                      \
+        .identify_cfg =                                                                             \
+            {                                                                                       \
+                .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,                   \
+            },                                                                                      \
+        .ias_zone_cfg =                                                                             \
+            {                                                                                       \
+                .zone_state = ESP_ZB_ZCL_IAS_ZONE_ZONESTATE_NOT_ENROLLED,                           \
+                .zone_type = ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_DOOR_WINDOW_HANDLE,                       \
+                .zone_status = 0,                                                                   \
+                .ias_cie_addr = ESP_ZB_ZCL_ZONE_IAS_CIE_ADDR_DEFAULT,                               \
+                .zone_id = 0xff,                                                                    \
+                .zone_ctx = {0, 0, 0, 0},                                                           \
+            },                                                                                      \
+    }
+// clang-format on
+
+typedef struct zigbee_door_window_handle_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_ias_zone_cluster_cfg_t ias_zone_cfg;
+} zigbee_door_window_handle_cfg_t;
+
+class ZigbeeDoorWindowHandle : public ZigbeeEP {
+public:
+  ZigbeeDoorWindowHandle(uint8_t endpoint);
+  ~ZigbeeDoorWindowHandle() {}
+
+  // Set the IAS Client endpoint number (default is 1)
+  void setIASClientEndpoint(uint8_t ep_number);
+
+  // Set the door/window handle value to closed
+  bool setClosed();
+
+  // Set the door/window handle value to open
+  bool setOpen();
+
+  // Set the door/window handle value to tilted
+  bool setTilted();
+
+  // Report the door/window handle value, done automatically after setting the position
+  bool report();
+
+private:
+  void zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) override;
+  uint8_t _zone_status;
+  uint8_t _zone_id;
+  esp_zb_ieee_addr_t _ias_cie_addr;
+  uint8_t _ias_cie_endpoint;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeFlowSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeFlowSensor.cpp
new file mode 100644
index 00000000000..8a60af5a8e1
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeFlowSensor.cpp
@@ -0,0 +1,124 @@
+#include "ZigbeeFlowSensor.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *zigbee_flow_sensor_clusters_create(zigbee_flow_sensor_cfg_t *flow_sensor) {
+  esp_zb_basic_cluster_cfg_t *basic_cfg = flow_sensor ? &(flow_sensor->basic_cfg) : NULL;
+  esp_zb_identify_cluster_cfg_t *identify_cfg = flow_sensor ? &(flow_sensor->identify_cfg) : NULL;
+  esp_zb_flow_meas_cluster_cfg_t *flow_meas_cfg = flow_sensor ? &(flow_sensor->flow_meas_cfg) : NULL;
+  esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_flow_meas_cluster(cluster_list, esp_zb_flow_meas_cluster_create(flow_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  return cluster_list;
+}
+
+ZigbeeFlowSensor::ZigbeeFlowSensor(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID;
+
+  //Create custom pressure sensor configuration
+  zigbee_flow_sensor_cfg_t flow_sensor_cfg = ZIGBEE_DEFAULT_FLOW_SENSOR_CONFIG();
+  _cluster_list = zigbee_flow_sensor_clusters_create(&flow_sensor_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0};
+}
+
+bool ZigbeeFlowSensor::setMinMaxValue(float min, float max) {
+  uint16_t zb_min = (uint16_t)(min * 10);
+  uint16_t zb_max = (uint16_t)(max * 10);
+  esp_zb_attribute_list_t *flow_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(flow_measure_cluster, ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_MIN_VALUE_ID, (void *)&zb_min);
+  if (ret != ESP_OK) {
+    log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(flow_measure_cluster, ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_MAX_VALUE_ID, (void *)&zb_max);
+  if (ret != ESP_OK) {
+    log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeFlowSensor::setTolerance(float tolerance) {
+  uint16_t zb_tolerance = (uint16_t)(tolerance * 10);
+  esp_zb_attribute_list_t *flow_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_flow_meas_cluster_add_attr(flow_measure_cluster, ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_TOLERANCE_ID, (void *)&zb_tolerance);
+  if (ret != ESP_OK) {
+    log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeFlowSensor::setReporting(uint16_t min_interval, uint16_t max_interval, float delta) {
+  esp_zb_zcl_reporting_info_t reporting_info;
+  memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t));
+  reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV;
+  reporting_info.ep = _endpoint;
+  reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT;
+  reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE;
+  reporting_info.attr_id = ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_VALUE_ID;
+  reporting_info.u.send_info.min_interval = min_interval;
+  reporting_info.u.send_info.max_interval = max_interval;
+  reporting_info.u.send_info.def_min_interval = min_interval;
+  reporting_info.u.send_info.def_max_interval = max_interval;
+  reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 10);  // Convert delta to ZCL uint16_t
+  reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info);
+  esp_zb_lock_release();
+
+  if (ret != ESP_OK) {
+    log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeFlowSensor::setFlow(float flow) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  uint16_t zb_flow = (uint16_t)(flow * 10);
+  log_v("Updating flow sensor value...");
+  /* Update temperature sensor measured value */
+  log_d("Setting flow to %d", zb_flow);
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_VALUE_ID, &zb_flow, false
+  );
+  esp_zb_lock_release();
+
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set flow value: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeFlowSensor::report() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_FLOW_MEASUREMENT_VALUE_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_FLOW_MEASUREMENT;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+
+  if (ret != ESP_OK) {
+    log_e("Failed to send flow report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Flow report sent");
+  return true;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeFlowSensor.h b/libraries/Zigbee/src/ep/ZigbeeFlowSensor.h
new file mode 100644
index 00000000000..fa16b4a5636
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeFlowSensor.h
@@ -0,0 +1,60 @@
+/* Class of Zigbee Flow sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+// clang-format off
+#define ZIGBEE_DEFAULT_FLOW_SENSOR_CONFIG()                               \
+  {                                                                       \
+    .basic_cfg =                                                          \
+      {                                                                   \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,        \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,      \
+      },                                                                  \
+    .identify_cfg =                                                       \
+      {                                                                   \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE, \
+      },                                                                  \
+    .flow_meas_cfg =                                                      \
+      {                                                                   \
+        .measured_value = 0,                                              \
+        .min_value = 0,                                                   \
+        .max_value = 0x7FFF,                                              \
+      },                                                                  \
+  }
+// clang-format on
+
+typedef struct zigbee_flow_sensor_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_flow_meas_cluster_cfg_t flow_meas_cfg;
+} zigbee_flow_sensor_cfg_t;
+
+class ZigbeeFlowSensor : public ZigbeeEP {
+public:
+  ZigbeeFlowSensor(uint8_t endpoint);
+  ~ZigbeeFlowSensor() {}
+
+  // Set the flow value in 0,1 m3/h
+  bool setFlow(float value);
+
+  // Set the min and max value for the flow sensor in 0,1 m3/h
+  bool setMinMaxValue(float min, float max);
+
+  // Set the tolerance value for the flow sensor in 0,01 m3/h
+  bool setTolerance(float tolerance);
+
+  // Set the reporting interval for flow measurement in seconds and delta (temp change in 0,1 m3/h)
+  bool setReporting(uint16_t min_interval, uint16_t max_interval, float delta);
+
+  // Report the flow value
+  bool report();
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeGateway.cpp b/libraries/Zigbee/src/ep/ZigbeeGateway.cpp
new file mode 100644
index 00000000000..b0be81395ca
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeGateway.cpp
@@ -0,0 +1,15 @@
+#include "ZigbeeGateway.h"
+#if CONFIG_ZB_ENABLED
+
+ZigbeeGateway::ZigbeeGateway(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_HOME_GATEWAY_DEVICE_ID;
+
+  _cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(_cluster_list, esp_zb_basic_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_IDENTIFY), ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_HOME_GATEWAY_DEVICE_ID, .app_device_version = 0};
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeGateway.h b/libraries/Zigbee/src/ep/ZigbeeGateway.h
new file mode 100644
index 00000000000..3925630c0b8
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeGateway.h
@@ -0,0 +1,18 @@
+/* Class of Zigbee Gateway endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+class ZigbeeGateway : public ZigbeeEP {
+public:
+  ZigbeeGateway(uint8_t endpoint);
+  ~ZigbeeGateway() {}
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.cpp
new file mode 100644
index 00000000000..f1661c3a026
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.cpp
@@ -0,0 +1,106 @@
+#include "ZigbeeIlluminanceSensor.h"
+#if CONFIG_ZB_ENABLED
+
+ZigbeeIlluminanceSensor::ZigbeeIlluminanceSensor(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_LIGHT_SENSOR_DEVICE_ID;
+
+  esp_zb_light_sensor_cfg_t light_sensor_cfg = ZIGBEE_DEFAULT_ILLUMINANCE_SENSOR_CONFIG();
+  _cluster_list = esp_zb_light_sensor_clusters_create(&light_sensor_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_LIGHT_SENSOR_DEVICE_ID, .app_device_version = 0};
+}
+
+bool ZigbeeIlluminanceSensor::setMinMaxValue(uint16_t min, uint16_t max) {
+  esp_zb_attribute_list_t *light_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(light_measure_cluster, ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MIN_MEASURED_VALUE_ID, (void *)&min);
+  if (ret != ESP_OK) {
+    log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(light_measure_cluster, ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MAX_MEASURED_VALUE_ID, (void *)&max);
+  if (ret != ESP_OK) {
+    log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeIlluminanceSensor::setTolerance(uint16_t tolerance) {
+  esp_zb_attribute_list_t *light_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_illuminance_meas_cluster_add_attr(light_measure_cluster, ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_TOLERANCE_ID, (void *)&tolerance);
+  if (ret != ESP_OK) {
+    log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeIlluminanceSensor::setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta) {
+  esp_zb_zcl_reporting_info_t reporting_info;
+  memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t));
+  reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV;
+  reporting_info.ep = _endpoint;
+  reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT;
+  reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE;
+  reporting_info.attr_id = ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MEASURED_VALUE_ID;
+  reporting_info.u.send_info.min_interval = min_interval;
+  reporting_info.u.send_info.max_interval = max_interval;
+  reporting_info.u.send_info.def_min_interval = min_interval;
+  reporting_info.u.send_info.def_max_interval = max_interval;
+  reporting_info.u.send_info.delta.u16 = delta;
+  reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info);
+  esp_zb_lock_release();
+
+  if (ret != ESP_OK) {
+    log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeIlluminanceSensor::setIlluminance(uint16_t illuminanceValue) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  log_v("Updating Illuminance...");
+  /* Update illuminance sensor measured illuminance */
+  log_d("Setting Illuminance to %d", illuminanceValue);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MEASURED_VALUE_ID,
+    &illuminanceValue, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set illuminance: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeIlluminanceSensor::report() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MEASURED_VALUE_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_ILLUMINANCE_MEASUREMENT;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send illuminance report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Illuminance report sent");
+  return true;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.h b/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.h
new file mode 100644
index 00000000000..133dfc315db
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeIlluminanceSensor.h
@@ -0,0 +1,51 @@
+/* Class of Zigbee Illuminance sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+#define ZIGBEE_DEFAULT_ILLUMINANCE_SENSOR_CONFIG()                                          \
+  {                                                                                         \
+    .basic_cfg =                                                                            \
+      {                                                                                     \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                          \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                        \
+      },                                                                                    \
+    .identify_cfg =                                                                         \
+      {                                                                                     \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,                   \
+      },                                                                                    \
+    .illuminance_cfg = {                                                                    \
+      .measured_value = ESP_ZB_ZCL_ILLUMINANCE_MEASUREMENT_LIGHT_SENSOR_TYPE_DEFAULT_VALUE, \
+      .min_value = ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MIN_MEASURED_VALUE_MIN_VALUE,    \
+      .max_value = ESP_ZB_ZCL_ATTR_ILLUMINANCE_MEASUREMENT_MAX_MEASURED_VALUE_MAX_VALUE,    \
+    },                                                                                      \
+  }
+
+class ZigbeeIlluminanceSensor : public ZigbeeEP {
+public:
+  ZigbeeIlluminanceSensor(uint8_t endpoint);
+  ~ZigbeeIlluminanceSensor() {}
+
+  // Set the illuminance value
+  bool setIlluminance(uint16_t value);
+
+  // Set the min and max value for the illuminance sensor
+  bool setMinMaxValue(uint16_t min, uint16_t max);
+
+  // Set the tolerance value for the illuminance sensor
+  bool setTolerance(uint16_t tolerance);
+
+  // Set the reporting interval for illuminance measurement in seconds and delta
+  bool setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta);
+
+  // Report the illuminance value
+  bool report();
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeLight.cpp b/libraries/Zigbee/src/ep/ZigbeeLight.cpp
new file mode 100644
index 00000000000..edfac04fcdf
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeLight.cpp
@@ -0,0 +1,56 @@
+#include "ZigbeeLight.h"
+#if CONFIG_ZB_ENABLED
+
+ZigbeeLight::ZigbeeLight(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_ON_OFF_LIGHT_DEVICE_ID;
+
+  esp_zb_on_off_light_cfg_t light_cfg = ESP_ZB_DEFAULT_ON_OFF_LIGHT_CONFIG();
+  _cluster_list = esp_zb_on_off_light_clusters_create(&light_cfg);  // use esp_zb_zcl_cluster_list_create() instead of esp_zb_on_off_light_clusters_create()
+  _ep_config = {.endpoint = endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_ON_OFF_LIGHT_DEVICE_ID, .app_device_version = 0};
+  log_v("Light endpoint created %d", _endpoint);
+}
+
+//set attribute method -> method overridden in child class
+void ZigbeeLight::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) {
+  //check the data and call right method
+  if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_ON_OFF) {
+    if (message->attribute.id == ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_BOOL) {
+      _current_state = *(bool *)message->attribute.data.value;
+      lightChanged();
+    } else {
+      log_w("Received message ignored. Attribute ID: %d not supported for On/Off Light", message->attribute.id);
+    }
+  } else {
+    log_w("Received message ignored. Cluster ID: %d not supported for On/Off Light", message->info.cluster);
+  }
+}
+
+void ZigbeeLight::lightChanged() {
+  if (_on_light_change) {
+    _on_light_change(_current_state);
+  } else {
+    log_w("No callback function set for light change");
+  }
+}
+
+bool ZigbeeLight::setLight(bool state) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  _current_state = state;
+  lightChanged();
+
+  log_v("Updating on/off light state to %d", state);
+  /* Update on/off light state */
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_ON_OFF_ON_OFF_ID, &_current_state, false
+  );
+  esp_zb_lock_release();
+
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set light state: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeLight.h b/libraries/Zigbee/src/ep/ZigbeeLight.h
new file mode 100644
index 00000000000..773fbb14ec5
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeLight.h
@@ -0,0 +1,41 @@
+/* Class of Zigbee On/Off Light endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+class ZigbeeLight : public ZigbeeEP {
+public:
+  ZigbeeLight(uint8_t endpoint);
+  ~ZigbeeLight() {}
+
+  // Use to set a cb function to be called on light change
+  void onLightChange(void (*callback)(bool)) {
+    _on_light_change = callback;
+  }
+  // Use to restore light state
+  void restoreLight() {
+    lightChanged();
+  }
+  // Use to control light state
+  bool setLight(bool state);
+  // Use to get light state
+  bool getLightState() {
+    return _current_state;
+  }
+
+private:
+  void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override;
+  //callback function to be called on light change
+  void (*_on_light_change)(bool);
+  void lightChanged();
+
+  bool _current_state;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.cpp b/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.cpp
new file mode 100644
index 00000000000..b8f88fed4a4
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.cpp
@@ -0,0 +1,80 @@
+#include "ZigbeeOccupancySensor.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *zigbee_occupancy_sensor_clusters_create(zigbee_occupancy_sensor_cfg_t *occupancy_sensor) {
+  esp_zb_basic_cluster_cfg_t *basic_cfg = occupancy_sensor ? &(occupancy_sensor->basic_cfg) : NULL;
+  esp_zb_identify_cluster_cfg_t *identify_cfg = occupancy_sensor ? &(occupancy_sensor->identify_cfg) : NULL;
+  esp_zb_occupancy_sensing_cluster_cfg_t *occupancy_meas_cfg = occupancy_sensor ? &(occupancy_sensor->occupancy_meas_cfg) : NULL;
+  esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_occupancy_sensing_cluster(cluster_list, esp_zb_occupancy_sensing_cluster_create(occupancy_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  return cluster_list;
+}
+
+ZigbeeOccupancySensor::ZigbeeOccupancySensor(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID;
+
+  //Create custom occupancy sensor configuration
+  zigbee_occupancy_sensor_cfg_t occupancy_sensor_cfg = ZIGBEE_DEFAULT_OCCUPANCY_SENSOR_CONFIG();
+  _cluster_list = zigbee_occupancy_sensor_clusters_create(&occupancy_sensor_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0};
+}
+
+bool ZigbeeOccupancySensor::setSensorType(uint8_t sensor_type) {
+  uint8_t sensor_type_bitmap = 1 << sensor_type;
+  esp_zb_attribute_list_t *occupancy_sens_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_OCCUPANCY_SENSING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(occupancy_sens_cluster, ESP_ZB_ZCL_ATTR_OCCUPANCY_SENSING_OCCUPANCY_SENSOR_TYPE_ID, (void *)&sensor_type);
+  if (ret != ESP_OK) {
+    log_e("Failed to set sensor type: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(occupancy_sens_cluster, ESP_ZB_ZCL_ATTR_OCCUPANCY_SENSING_OCCUPANCY_SENSOR_TYPE_BITMAP_ID, (void *)&sensor_type_bitmap);
+  if (ret != ESP_OK) {
+    log_e("Failed to set sensor type bitmap: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeOccupancySensor::setOccupancy(bool occupied) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  log_v("Updating occupancy sensor value...");
+  /* Update occupancy sensor value */
+  log_d("Setting occupancy to %d", occupied);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_OCCUPANCY_SENSING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_OCCUPANCY_SENSING_OCCUPANCY_ID, &occupied, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set occupancy: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeOccupancySensor::report() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_OCCUPANCY_SENSING_OCCUPANCY_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_OCCUPANCY_SENSING;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send occupancy report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Occupancy report sent");
+  return true;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.h b/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.h
new file mode 100644
index 00000000000..7408e10a76b
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeOccupancySensor.h
@@ -0,0 +1,54 @@
+/* Class of Zigbee Pressure sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+// clang-format off
+#define ZIGBEE_DEFAULT_OCCUPANCY_SENSOR_CONFIG()                                             \
+  {                                                                                          \
+    .basic_cfg =                                                                             \
+      {                                                                                      \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                           \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                         \
+      },                                                                                     \
+    .identify_cfg =                                                                          \
+      {                                                                                      \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,                    \
+      },                                                                                     \
+    .occupancy_meas_cfg =                                                                    \
+      {                                                                                      \
+        .occupancy = ESP_ZB_ZCL_OCCUPANCY_SENSING_OCCUPANCY_UNOCCUPIED,                      \
+        .sensor_type = ESP_ZB_ZCL_OCCUPANCY_SENSING_OCCUPANCY_SENSOR_TYPE_PIR,               \
+        .sensor_type_bitmap = (1 << ESP_ZB_ZCL_OCCUPANCY_SENSING_OCCUPANCY_SENSOR_TYPE_PIR), \
+      },                                                                                     \
+  }
+// clang-format on
+
+typedef struct zigbee_occupancy_sensor_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_occupancy_sensing_cluster_cfg_t occupancy_meas_cfg;
+} zigbee_occupancy_sensor_cfg_t;
+
+class ZigbeeOccupancySensor : public ZigbeeEP {
+public:
+  ZigbeeOccupancySensor(uint8_t endpoint);
+  ~ZigbeeOccupancySensor() {}
+
+  // Set the occupancy value. True for occupied, false for unoccupied
+  bool setOccupancy(bool occupied);
+
+  // Set the sensor type, see esp_zb_zcl_occupancy_sensing_occupancy_sensor_type_t
+  bool setSensorType(uint8_t sensor_type);
+
+  // Report the occupancy value
+  bool report();
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeePM25Sensor.cpp b/libraries/Zigbee/src/ep/ZigbeePM25Sensor.cpp
new file mode 100644
index 00000000000..d25d15e5de3
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeePM25Sensor.cpp
@@ -0,0 +1,118 @@
+#include "ZigbeePM25Sensor.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *zigbee_pm2_5_sensor_clusters_create(zigbee_pm2_5_sensor_cfg_t *pm2_5_sensor) {
+  esp_zb_basic_cluster_cfg_t *basic_cfg = pm2_5_sensor ? &(pm2_5_sensor->basic_cfg) : NULL;
+  esp_zb_identify_cluster_cfg_t *identify_cfg = pm2_5_sensor ? &(pm2_5_sensor->identify_cfg) : NULL;
+  esp_zb_pm2_5_measurement_cluster_cfg_t *pm2_5_meas_cfg = pm2_5_sensor ? &(pm2_5_sensor->pm2_5_meas_cfg) : NULL;
+  esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_pm2_5_measurement_cluster(cluster_list, esp_zb_pm2_5_measurement_cluster_create(pm2_5_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  return cluster_list;
+}
+
+ZigbeePM25Sensor::ZigbeePM25Sensor(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID;
+
+  //Create custom PM2.5 sensor configuration
+  zigbee_pm2_5_sensor_cfg_t pm2_5_sensor_cfg = ZIGBEE_DEFAULT_PM2_5_SENSOR_CONFIG();
+  _cluster_list = zigbee_pm2_5_sensor_clusters_create(&pm2_5_sensor_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0};
+}
+
+bool ZigbeePM25Sensor::setMinMaxValue(float min, float max) {
+  esp_zb_attribute_list_t *pm2_5_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(pm2_5_measure_cluster, ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MIN_MEASURED_VALUE_ID, (void *)&min);
+  if (ret != ESP_OK) {
+    log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(pm2_5_measure_cluster, ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MAX_MEASURED_VALUE_ID, (void *)&max);
+  if (ret != ESP_OK) {
+    log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeePM25Sensor::setTolerance(float tolerance) {
+  esp_zb_attribute_list_t *pm2_5_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_pm2_5_measurement_cluster_add_attr(pm2_5_measure_cluster, ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_TOLERANCE_ID, (void *)&tolerance);
+  if (ret != ESP_OK) {
+    log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeePM25Sensor::setReporting(uint16_t min_interval, uint16_t max_interval, float delta) {
+  esp_zb_zcl_reporting_info_t reporting_info;
+  memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t));
+  reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV;
+  reporting_info.ep = _endpoint;
+  reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT;
+  reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE;
+  reporting_info.attr_id = ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MEASURED_VALUE_ID;
+  reporting_info.u.send_info.min_interval = min_interval;
+  reporting_info.u.send_info.max_interval = max_interval;
+  reporting_info.u.send_info.def_min_interval = min_interval;
+  reporting_info.u.send_info.def_max_interval = max_interval;
+  // reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 100);  // Convert delta to ZCL uint16_t
+  reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+  float delta_f = delta;
+  memcpy(&reporting_info.u.send_info.delta.s32, &delta_f, sizeof(float));
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeePM25Sensor::setPM25(float pm25) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  log_v("Updating PM2.5 sensor value...");
+  /* Update PM2.5 sensor measured value */
+  log_d("Setting PM2.5 to %0.1f", pm25);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MEASURED_VALUE_ID, &pm25, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set PM2.5: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeePM25Sensor::report() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_PM2_5_MEASUREMENT_MEASURED_VALUE_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_PM2_5_MEASUREMENT;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send PM2.5 report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("PM2.5 report sent");
+  return true;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeePM25Sensor.h b/libraries/Zigbee/src/ep/ZigbeePM25Sensor.h
new file mode 100644
index 00000000000..344f3e1f479
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeePM25Sensor.h
@@ -0,0 +1,60 @@
+/* Class of Zigbee PM2.5 sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+// clang-format off
+#define ZIGBEE_DEFAULT_PM2_5_SENSOR_CONFIG()                                           \
+  {                                                                                    \
+    .basic_cfg =                                                                       \
+      {                                                                                \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                     \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                   \
+      },                                                                               \
+    .identify_cfg =                                                                    \
+      {                                                                                \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,              \
+      },                                                                               \
+    .pm2_5_meas_cfg =                                                                  \
+      {                                                                                \
+        .measured_value = 0.0,                                                         \
+        .min_measured_value = 0.0,                                                     \
+        .max_measured_value = 500.0,                                                   \
+      },                                                                               \
+  }
+// clang-format on
+
+typedef struct zigbee_pm2_5_sensor_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_pm2_5_measurement_cluster_cfg_t pm2_5_meas_cfg;
+} zigbee_pm2_5_sensor_cfg_t;
+
+class ZigbeePM25Sensor : public ZigbeeEP {
+public:
+  ZigbeePM25Sensor(uint8_t endpoint);
+  ~ZigbeePM25Sensor() {}
+
+  // Set the PM2.5 value in 0.1 µg/m³
+  bool setPM25(float pm25);
+
+  // Set the min and max value for the PM2.5 sensor in 0.1 µg/m³
+  bool setMinMaxValue(float min, float max);
+
+  // Set the tolerance value for the PM2.5 sensor in 0.1 µg/m³
+  bool setTolerance(float tolerance);
+
+  // Set the reporting interval for PM2.5 measurement in seconds and delta (PM2.5 change in 0.1 µg/m³)
+  bool setReporting(uint16_t min_interval, uint16_t max_interval, float delta);
+
+  // Report the PM2.5 value
+  bool report();
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeePressureSensor.cpp b/libraries/Zigbee/src/ep/ZigbeePressureSensor.cpp
new file mode 100644
index 00000000000..bca06a35d0c
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeePressureSensor.cpp
@@ -0,0 +1,114 @@
+#include "ZigbeePressureSensor.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *zigbee_pressure_sensor_clusters_create(zigbee_pressure_sensor_cfg_t *pressure_sensor) {
+  esp_zb_basic_cluster_cfg_t *basic_cfg = pressure_sensor ? &(pressure_sensor->basic_cfg) : NULL;
+  esp_zb_identify_cluster_cfg_t *identify_cfg = pressure_sensor ? &(pressure_sensor->identify_cfg) : NULL;
+  esp_zb_pressure_meas_cluster_cfg_t *pressure_meas_cfg = pressure_sensor ? &(pressure_sensor->pressure_meas_cfg) : NULL;
+  esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_pressure_meas_cluster(cluster_list, esp_zb_pressure_meas_cluster_create(pressure_meas_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  return cluster_list;
+}
+
+ZigbeePressureSensor::ZigbeePressureSensor(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID;
+
+  //Create custom pressure sensor configuration
+  zigbee_pressure_sensor_cfg_t presssure_sensor_cfg = ZIGBEE_DEFAULT_PRESSURE_SENSOR_CONFIG();
+  _cluster_list = zigbee_pressure_sensor_clusters_create(&presssure_sensor_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0};
+}
+
+bool ZigbeePressureSensor::setMinMaxValue(int16_t min, int16_t max) {
+  esp_zb_attribute_list_t *pressure_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(pressure_measure_cluster, ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_MIN_VALUE_ID, (void *)&min);
+  if (ret != ESP_OK) {
+    log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(pressure_measure_cluster, ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_MAX_VALUE_ID, (void *)&max);
+  if (ret != ESP_OK) {
+    log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeePressureSensor::setTolerance(uint16_t tolerance) {
+  esp_zb_attribute_list_t *pressure_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_pressure_meas_cluster_add_attr(pressure_measure_cluster, ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_TOLERANCE_ID, (void *)&tolerance);
+  if (ret != ESP_OK) {
+    log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret));
+  }
+  return ret == ESP_OK;
+}
+
+bool ZigbeePressureSensor::setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta) {
+  esp_zb_zcl_reporting_info_t reporting_info;
+  memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t));
+  reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV;
+  reporting_info.ep = _endpoint;
+  reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT;
+  reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE;
+  reporting_info.attr_id = ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_VALUE_ID;
+  reporting_info.u.send_info.min_interval = min_interval;
+  reporting_info.u.send_info.max_interval = max_interval;
+  reporting_info.u.send_info.def_min_interval = min_interval;
+  reporting_info.u.send_info.def_max_interval = max_interval;
+  reporting_info.u.send_info.delta.u16 = delta;  // x hPa
+  reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeePressureSensor::setPressure(int16_t pressure) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  log_v("Updating pressure sensor value...");
+  /* Update pressure sensor measured value */
+  log_d("Setting pressure to %d hPa", pressure);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_VALUE_ID, &pressure, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set pressure: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeePressureSensor::report() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_VALUE_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_PRESSURE_MEASUREMENT;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send pressure report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Pressure report sent");
+  return true;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeePressureSensor.h b/libraries/Zigbee/src/ep/ZigbeePressureSensor.h
new file mode 100644
index 00000000000..f93df7a7411
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeePressureSensor.h
@@ -0,0 +1,60 @@
+/* Class of Zigbee Pressure sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+// clang-format off
+#define ZIGBEE_DEFAULT_PRESSURE_SENSOR_CONFIG()                                                     \
+    {                                                                                               \
+        .basic_cfg =                                                                                \
+            {                                                                                       \
+                .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                          \
+                .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                        \
+            },                                                                                      \
+        .identify_cfg =                                                                             \
+            {                                                                                       \
+                .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,                   \
+            },                                                                                      \
+        .pressure_meas_cfg =                                                                        \
+            {                                                                                       \
+                .measured_value = ESP_ZB_ZCL_ATTR_PRESSURE_MEASUREMENT_VALUE_DEFAULT_VALUE,         \
+                .min_value = ESP_ZB_ZCL_PATTR_RESSURE_MEASUREMENT_MIN_VALUE_DEFAULT_VALUE,          \
+                .max_value = ESP_ZB_ZCL_PATTR_RESSURE_MEASUREMENT_MAX_VALUE_DEFAULT_VALUE,          \
+            },                                                                                      \
+    }
+// clang-format on
+
+typedef struct zigbee_pressure_sensor_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_pressure_meas_cluster_cfg_t pressure_meas_cfg;
+} zigbee_pressure_sensor_cfg_t;
+
+class ZigbeePressureSensor : public ZigbeeEP {
+public:
+  ZigbeePressureSensor(uint8_t endpoint);
+  ~ZigbeePressureSensor() {}
+
+  // Set the pressure value in 1 hPa
+  bool setPressure(int16_t value);
+
+  // Set the min and max value for the pressure sensor in 1 hPa
+  bool setMinMaxValue(int16_t min, int16_t max);
+
+  // Set the tolerance value for the pressure sensor in 1 hPa
+  bool setTolerance(uint16_t tolerance);
+
+  // Set the reporting interval for pressure measurement in seconds and delta (pressure change in 1 hPa)
+  bool setReporting(uint16_t min_interval, uint16_t max_interval, uint16_t delta);
+
+  // Report the pressure value
+  bool report();
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeRangeExtender.cpp b/libraries/Zigbee/src/ep/ZigbeeRangeExtender.cpp
new file mode 100644
index 00000000000..20db20d758a
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeRangeExtender.cpp
@@ -0,0 +1,15 @@
+#include "ZigbeeRangeExtender.h"
+#if CONFIG_ZB_ENABLED
+
+ZigbeeRangeExtender::ZigbeeRangeExtender(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_RANGE_EXTENDER_DEVICE_ID;
+
+  _cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(_cluster_list, esp_zb_basic_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_IDENTIFY), ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_RANGE_EXTENDER_DEVICE_ID, .app_device_version = 0};
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeRangeExtender.h b/libraries/Zigbee/src/ep/ZigbeeRangeExtender.h
new file mode 100644
index 00000000000..f9e4a963164
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeRangeExtender.h
@@ -0,0 +1,18 @@
+/* Class of Zigbee Range Extender endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+class ZigbeeRangeExtender : public ZigbeeEP {
+public:
+  ZigbeeRangeExtender(uint8_t endpoint);
+  ~ZigbeeRangeExtender() {}
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeSwitch.cpp b/libraries/Zigbee/src/ep/ZigbeeSwitch.cpp
new file mode 100644
index 00000000000..86c68ae1870
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeSwitch.cpp
@@ -0,0 +1,316 @@
+#include "ZigbeeSwitch.h"
+#if CONFIG_ZB_ENABLED
+
+// Initialize the static instance pointer
+ZigbeeSwitch *ZigbeeSwitch::_instance = nullptr;
+
+ZigbeeSwitch::ZigbeeSwitch(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_ON_OFF_SWITCH_DEVICE_ID;
+  _instance = this;  // Set the static pointer to this instance
+
+  esp_zb_on_off_switch_cfg_t switch_cfg = ESP_ZB_DEFAULT_ON_OFF_SWITCH_CONFIG();
+  _cluster_list = esp_zb_on_off_switch_clusters_create(&switch_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_ON_OFF_SWITCH_DEVICE_ID, .app_device_version = 0};
+}
+
+void ZigbeeSwitch::bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx) {
+  if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) {
+    log_i("Bound successfully!");
+    if (user_ctx) {
+      zb_device_params_t *light = (zb_device_params_t *)user_ctx;
+      log_i("The light originating from address(0x%x) on endpoint(%d)", light->short_addr, light->endpoint);
+      _instance->_bound_devices.push_back(light);
+    }
+    _is_bound = true;
+  }
+}
+
+void ZigbeeSwitch::findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) {
+  if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) {
+    log_d("Found light endpoint");
+    esp_zb_zdo_bind_req_param_t bind_req;
+    zb_device_params_t *light = (zb_device_params_t *)malloc(sizeof(zb_device_params_t));
+    light->endpoint = endpoint;
+    light->short_addr = addr;
+    esp_zb_ieee_address_by_short(light->short_addr, light->ieee_addr);
+    esp_zb_get_long_address(bind_req.src_address);
+    bind_req.src_endp = *((uint8_t *)user_ctx);  //_endpoint;
+    bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_ON_OFF;
+    bind_req.dst_addr_mode = ESP_ZB_ZDO_BIND_DST_ADDR_MODE_64_BIT_EXTENDED;
+    memcpy(bind_req.dst_address_u.addr_long, light->ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    bind_req.dst_endp = endpoint;
+    bind_req.req_dst_addr = esp_zb_get_short_address();
+    log_i("Try to bind On/Off");
+    esp_zb_zdo_device_bind_req(&bind_req, bindCb, (void *)light);
+  } else {
+    log_d("No light endpoint found");
+  }
+}
+
+// find on_off light endpoint
+void ZigbeeSwitch::findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req) {
+  uint16_t cluster_list[] = {ESP_ZB_ZCL_CLUSTER_ID_ON_OFF, ESP_ZB_ZCL_CLUSTER_ID_ON_OFF};
+  esp_zb_zdo_match_desc_req_param_t on_off_req = {
+    .dst_nwk_addr = cmd_req->dst_nwk_addr,
+    .addr_of_interest = cmd_req->addr_of_interest,
+    .profile_id = ESP_ZB_AF_HA_PROFILE_ID,
+    .num_in_clusters = 1,
+    .num_out_clusters = 1,
+    .cluster_list = cluster_list,
+  };
+  esp_zb_zdo_match_cluster(&on_off_req, findCb, &_endpoint);
+}
+
+// Methods to control the light
+void ZigbeeSwitch::lightToggle() {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID;
+    log_v("Sending 'light toggle' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightToggle(uint16_t group_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID;
+    log_v("Sending 'light toggle' command to group address 0x%x", group_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightToggle(uint8_t endpoint, uint16_t short_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID;
+    log_v("Sending 'light toggle' command to endpoint %d, address 0x%x", endpoint, short_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightToggle(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID;
+    memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    log_v(
+      "Sending 'light toggle' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5],
+      ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]
+    );
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOn() {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID;
+    log_v("Sending 'light on' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOn(uint16_t group_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID;
+    log_v("Sending 'light on' command to group address 0x%x", group_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOn(uint8_t endpoint, uint16_t short_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID;
+    log_v("Sending 'light on' command to endpoint %d, address 0x%x", endpoint, short_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOn(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_ON_ID;
+    memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    log_v(
+      "Sending 'light on' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5],
+      ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]
+    );
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOff() {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID;
+    log_v("Sending 'light off' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOff(uint16_t group_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = group_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_GROUP_ENDP_NOT_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID;
+    log_v("Sending 'light off' command to group address 0x%x", group_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOff(uint8_t endpoint, uint16_t short_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.zcl_basic_cmd.dst_addr_u.addr_short = short_addr;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_16_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID;
+    log_v("Sending 'light off' command to endpoint %d, address 0x%x", endpoint, short_addr);
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOff(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.zcl_basic_cmd.dst_endpoint = endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+    cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_OFF_ID;
+    memcpy(cmd_req.zcl_basic_cmd.dst_addr_u.addr_long, ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    log_v(
+      "Sending 'light off' command to endpoint %d, ieee address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", endpoint, ieee_addr[7], ieee_addr[6], ieee_addr[5],
+      ieee_addr[4], ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]
+    );
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOffWithEffect(uint8_t effect_id, uint8_t effect_variant) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_off_with_effect_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.effect_id = effect_id;
+    cmd_req.effect_variant = effect_variant;
+    log_v("Sending 'light off with effect' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_off_with_effect_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+void ZigbeeSwitch::lightOnWithSceneRecall() {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_on_with_recall_global_scene_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    log_v("Sending 'light on with scene recall' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_on_with_recall_global_scene_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+void ZigbeeSwitch::lightOnWithTimedOff(uint8_t on_off_control, uint16_t time_on, uint16_t time_off) {
+  if (_is_bound) {
+    esp_zb_zcl_on_off_on_with_timed_off_cmd_t cmd_req;
+    cmd_req.zcl_basic_cmd.src_endpoint = _endpoint;
+    cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+    cmd_req.on_off_control = on_off_control;  //TODO: Test how it works, then maybe change API
+    cmd_req.on_time = time_on;
+    cmd_req.off_wait_time = time_off;
+    log_v("Sending 'light on with time off' command");
+    esp_zb_lock_acquire(portMAX_DELAY);
+    esp_zb_zcl_on_off_on_with_timed_off_cmd_req(&cmd_req);
+    esp_zb_lock_release();
+  } else {
+    log_e("Light not bound");
+  }
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeSwitch.h b/libraries/Zigbee/src/ep/ZigbeeSwitch.h
new file mode 100644
index 00000000000..5c527bec6e3
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeSwitch.h
@@ -0,0 +1,46 @@
+/* Class of Zigbee On/Off Switch endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+class ZigbeeSwitch : public ZigbeeEP {
+public:
+  ZigbeeSwitch(uint8_t endpoint);
+  ~ZigbeeSwitch() {}
+
+  // methods to control the on/off light
+  void lightToggle();
+  void lightToggle(uint16_t group_addr);
+  void lightToggle(uint8_t endpoint, uint16_t short_addr);
+  void lightToggle(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr);
+
+  void lightOn();
+  void lightOn(uint16_t group_addr);
+  void lightOn(uint8_t endpoint, uint16_t short_addr);
+  void lightOn(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr);
+
+  void lightOff();
+  void lightOff(uint16_t group_addr);
+  void lightOff(uint8_t endpoint, uint16_t short_addr);
+  void lightOff(uint8_t endpoint, esp_zb_ieee_addr_t ieee_addr);
+
+  void lightOffWithEffect(uint8_t effect_id, uint8_t effect_variant);
+  void lightOnWithTimedOff(uint8_t on_off_control, uint16_t time_on, uint16_t time_off);
+  void lightOnWithSceneRecall();
+
+private:
+  // save instance of the class in order to use it in static functions
+  static ZigbeeSwitch *_instance;
+
+  void findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req);
+  static void bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx);
+  static void findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx);
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeTempSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeTempSensor.cpp
new file mode 100644
index 00000000000..7126dae15cf
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeTempSensor.cpp
@@ -0,0 +1,203 @@
+#include "ZigbeeTempSensor.h"
+#if CONFIG_ZB_ENABLED
+
+ZigbeeTempSensor::ZigbeeTempSensor(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_TEMPERATURE_SENSOR_DEVICE_ID;
+  _humidity_sensor = false;
+
+  esp_zb_temperature_sensor_cfg_t temp_sensor_cfg = ESP_ZB_DEFAULT_TEMPERATURE_SENSOR_CONFIG();
+  _cluster_list = esp_zb_temperature_sensor_clusters_create(&temp_sensor_cfg);
+
+  _ep_config = {
+    .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_TEMPERATURE_SENSOR_DEVICE_ID, .app_device_version = 0
+  };
+}
+
+static int16_t zb_float_to_s16(float temp) {
+  return (int16_t)(temp * 100);
+}
+
+bool ZigbeeTempSensor::setMinMaxValue(float min, float max) {
+  int16_t zb_min = zb_float_to_s16(min);
+  int16_t zb_max = zb_float_to_s16(max);
+  esp_zb_attribute_list_t *temp_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(temp_measure_cluster, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MIN_VALUE_ID, (void *)&zb_min);
+  if (ret != ESP_OK) {
+    log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(temp_measure_cluster, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MAX_VALUE_ID, (void *)&zb_max);
+  if (ret != ESP_OK) {
+    log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeTempSensor::setTolerance(float tolerance) {
+  // Convert tolerance to ZCL uint16_t
+  uint16_t zb_tolerance = (uint16_t)(tolerance * 100);
+  esp_zb_attribute_list_t *temp_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_temperature_meas_cluster_add_attr(temp_measure_cluster, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_TOLERANCE_ID, (void *)&zb_tolerance);
+  if (ret != ESP_OK) {
+    log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeTempSensor::setReporting(uint16_t min_interval, uint16_t max_interval, float delta) {
+  esp_zb_zcl_reporting_info_t reporting_info;
+  memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t));
+  reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV;
+  reporting_info.ep = _endpoint;
+  reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT;
+  reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE;
+  reporting_info.attr_id = ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID;
+  reporting_info.u.send_info.min_interval = min_interval;
+  reporting_info.u.send_info.max_interval = max_interval;
+  reporting_info.u.send_info.def_min_interval = min_interval;
+  reporting_info.u.send_info.def_max_interval = max_interval;
+  reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 100);  // Convert delta to ZCL uint16_t
+  reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeTempSensor::setTemperature(float temperature) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  int16_t zb_temperature = zb_float_to_s16(temperature);
+  log_v("Updating temperature sensor value...");
+  /* Update temperature sensor measured value */
+  log_d("Setting temperature to %d", zb_temperature);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID, &zb_temperature, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set temperature: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeTempSensor::reportTemperature() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send temperature report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Temperature report sent");
+  return true;
+}
+
+void ZigbeeTempSensor::addHumiditySensor(float min, float max, float tolerance) {
+  int16_t zb_min = zb_float_to_s16(min);
+  int16_t zb_max = zb_float_to_s16(max);
+  uint16_t zb_tolerance = (uint16_t)(tolerance * 100);
+  int16_t default_hum = ESP_ZB_ZCL_REL_HUMIDITY_MEASUREMENT_MEASURED_VALUE_DEFAULT;
+  esp_zb_attribute_list_t *humidity_cluster = esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT);
+  esp_zb_humidity_meas_cluster_add_attr(humidity_cluster, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID, &default_hum);
+  esp_zb_humidity_meas_cluster_add_attr(humidity_cluster, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MIN_VALUE_ID, &zb_min);
+  esp_zb_humidity_meas_cluster_add_attr(humidity_cluster, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_MAX_VALUE_ID, &zb_max);
+  esp_zb_humidity_meas_cluster_add_attr(humidity_cluster, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_TOLERANCE_ID, &zb_tolerance);
+  esp_zb_cluster_list_add_humidity_meas_cluster(_cluster_list, humidity_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  _humidity_sensor = true;
+}
+
+bool ZigbeeTempSensor::setHumidity(float humidity) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  int16_t zb_humidity = zb_float_to_s16(humidity);
+  log_v("Updating humidity sensor value...");
+  /* Update humidity sensor measured value */
+  log_d("Setting humidity to %d", zb_humidity);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID, &zb_humidity,
+    false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set humidity: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeTempSensor::reportHumidity() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send humidity report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Humidity report sent");
+  return true;
+}
+
+bool ZigbeeTempSensor::setHumidityReporting(uint16_t min_interval, uint16_t max_interval, float delta) {
+  esp_zb_zcl_reporting_info_t reporting_info;
+  memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t));
+  reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV;
+  reporting_info.ep = _endpoint;
+  reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_REL_HUMIDITY_MEASUREMENT;
+  reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE;
+  reporting_info.attr_id = ESP_ZB_ZCL_ATTR_REL_HUMIDITY_MEASUREMENT_VALUE_ID;
+  reporting_info.u.send_info.min_interval = min_interval;
+  reporting_info.u.send_info.max_interval = max_interval;
+  reporting_info.u.send_info.def_min_interval = min_interval;
+  reporting_info.u.send_info.def_max_interval = max_interval;
+  reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 100);  // Convert delta to ZCL uint16_t
+  reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to set humidity reporting: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeTempSensor::report() {
+  bool temp_ret = reportTemperature();
+  bool hum_ret = true;
+  if (_humidity_sensor) {
+    hum_ret = reportHumidity();
+  }
+  return temp_ret && hum_ret;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeTempSensor.h b/libraries/Zigbee/src/ep/ZigbeeTempSensor.h
new file mode 100644
index 00000000000..bc769b32de6
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeTempSensor.h
@@ -0,0 +1,51 @@
+/* Class of Zigbee Temperature + Humidity sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+class ZigbeeTempSensor : public ZigbeeEP {
+public:
+  ZigbeeTempSensor(uint8_t endpoint);
+  ~ZigbeeTempSensor() {}
+
+  // Set the temperature value in 0,01°C
+  bool setTemperature(float value);
+
+  // Set the min and max value for the temperature sensor in 0,01°C
+  bool setMinMaxValue(float min, float max);
+
+  // Set the tolerance value for the temperature sensor in 0,01°C
+  bool setTolerance(float tolerance);
+
+  // Set the reporting interval for temperature measurement in seconds and delta (temp change in 0,01 °C)
+  bool setReporting(uint16_t min_interval, uint16_t max_interval, float delta);
+
+  // Report the temperature value
+  bool reportTemperature();
+
+  // Add humidity cluster to the temperature sensor device
+  void addHumiditySensor(float min, float max, float tolerance);
+
+  // Set the humidity value in 0,01%
+  bool setHumidity(float value);
+
+  // Set the reporting interval for humidity measurement in seconds and delta (humidity change in 0,01%)
+  bool setHumidityReporting(uint16_t min_interval, uint16_t max_interval, float delta);
+
+  // Report the humidity value
+  bool reportHumidity();
+
+  // Report the temperature and humidity values if humidity sensor is added
+  bool report();
+
+private:
+  bool _humidity_sensor;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeThermostat.cpp b/libraries/Zigbee/src/ep/ZigbeeThermostat.cpp
new file mode 100644
index 00000000000..357bcaed1bc
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeThermostat.cpp
@@ -0,0 +1,205 @@
+#include "ZigbeeThermostat.h"
+#if CONFIG_ZB_ENABLED
+
+static float zb_s16_to_temperature(int16_t value) {
+  return 1.0 * value / 100;
+}
+
+// Initialize the static instance of the class
+ZigbeeThermostat *ZigbeeThermostat::_instance = nullptr;
+
+ZigbeeThermostat::ZigbeeThermostat(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_THERMOSTAT_DEVICE_ID;
+  _instance = this;  // Set the static pointer to this instance
+
+  //use custom config to avoid narrowing error -> must be fixed in zigbee-sdk
+  esp_zb_thermostat_cfg_t thermostat_cfg = ZB_DEFAULT_THERMOSTAT_CONFIG();
+
+  //use custom cluster creating to accept reportings from temperature sensor
+  _cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_attribute_list_t *basic_cluster = esp_zb_basic_cluster_create(&(thermostat_cfg.basic_cfg));
+  esp_zb_cluster_list_add_basic_cluster(_cluster_list, basic_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_identify_cluster_create(&(thermostat_cfg.identify_cfg)), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(_cluster_list, esp_zb_zcl_attr_list_create(ESP_ZB_ZCL_CLUSTER_ID_IDENTIFY), ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE);
+  esp_zb_cluster_list_add_thermostat_cluster(_cluster_list, esp_zb_thermostat_cluster_create(&(thermostat_cfg.thermostat_cfg)), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  /* Add temperature measurement cluster for attribute reporting */
+  esp_zb_cluster_list_add_temperature_meas_cluster(_cluster_list, esp_zb_temperature_meas_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_CLIENT_ROLE);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_THERMOSTAT_DEVICE_ID, .app_device_version = 0};
+}
+
+void ZigbeeThermostat::bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx) {
+  if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) {
+    if (user_ctx) {
+      zb_device_params_t *sensor = (zb_device_params_t *)user_ctx;
+      log_i("The temperature sensor originating from address(0x%x) on endpoint(%d)", sensor->short_addr, sensor->endpoint);
+      _instance->_bound_devices.push_back(sensor);
+    } else {
+      log_v("Local binding success");
+    }
+    _is_bound = true;
+  } else {
+    log_e("Binding failed!");
+  }
+}
+
+void ZigbeeThermostat::findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx) {
+  if (zdo_status == ESP_ZB_ZDP_STATUS_SUCCESS) {
+    log_i("Found temperature sensor");
+    esp_zb_zdo_bind_req_param_t bind_req;
+    /* Store the information of the remote device */
+    zb_device_params_t *sensor = (zb_device_params_t *)malloc(sizeof(zb_device_params_t));
+    sensor->endpoint = endpoint;
+    sensor->short_addr = addr;
+    esp_zb_ieee_address_by_short(sensor->short_addr, sensor->ieee_addr);
+    log_d("Temperature sensor found: short address(0x%x), endpoint(%d)", sensor->short_addr, sensor->endpoint);
+
+    /* 1. Send binding request to the sensor */
+    bind_req.req_dst_addr = addr;
+    log_d("Request temperature sensor to bind us");
+
+    /* populate the src information of the binding */
+    memcpy(bind_req.src_address, sensor->ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    bind_req.src_endp = endpoint;
+    bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT;
+    log_d("Bind temperature sensor");
+
+    /* populate the dst information of the binding */
+    bind_req.dst_addr_mode = ESP_ZB_ZDO_BIND_DST_ADDR_MODE_64_BIT_EXTENDED;
+    esp_zb_get_long_address(bind_req.dst_address_u.addr_long);
+    bind_req.dst_endp = *((uint8_t *)user_ctx);  //_endpoint;
+
+    log_i("Request temperature sensor to bind us");
+    esp_zb_zdo_device_bind_req(&bind_req, bindCb, NULL);
+
+    /* 2. Send binding request to self */
+    bind_req.req_dst_addr = esp_zb_get_short_address();
+
+    /* populate the src information of the binding */
+    esp_zb_get_long_address(bind_req.src_address);
+    bind_req.src_endp = *((uint8_t *)user_ctx);  //_endpoint;
+    bind_req.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT;
+
+    /* populate the dst information of the binding */
+    bind_req.dst_addr_mode = ESP_ZB_ZDO_BIND_DST_ADDR_MODE_64_BIT_EXTENDED;
+    memcpy(bind_req.dst_address_u.addr_long, sensor->ieee_addr, sizeof(esp_zb_ieee_addr_t));
+    bind_req.dst_endp = endpoint;
+
+    log_i("Bind temperature sensor");
+    esp_zb_zdo_device_bind_req(&bind_req, bindCb, (void *)sensor);
+  }
+}
+
+void ZigbeeThermostat::findEndpoint(esp_zb_zdo_match_desc_req_param_t *param) {
+  uint16_t cluster_list[] = {ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT};
+  param->profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  param->num_in_clusters = 1;
+  param->num_out_clusters = 0;
+  param->cluster_list = cluster_list;
+  esp_zb_zdo_match_cluster(param, findCb, &_endpoint);
+}
+
+void ZigbeeThermostat::zbAttributeRead(uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute) {
+  static uint8_t read_config = 0;
+  if (cluster_id == ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT) {
+    if (attribute->id == ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_S16) {
+      int16_t value = attribute->data.value ? *(int16_t *)attribute->data.value : 0;
+      if (_on_temp_recieve) {
+        _on_temp_recieve(zb_s16_to_temperature(value));
+      }
+    }
+    if (attribute->id == ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MIN_VALUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_S16) {
+      int16_t min_value = attribute->data.value ? *(int16_t *)attribute->data.value : 0;
+      _min_temp = zb_s16_to_temperature(min_value);
+      read_config++;
+    }
+    if (attribute->id == ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MAX_VALUE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_S16) {
+      int16_t max_value = attribute->data.value ? *(int16_t *)attribute->data.value : 0;
+      _max_temp = zb_s16_to_temperature(max_value);
+      read_config++;
+    }
+    if (attribute->id == ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_TOLERANCE_ID && attribute->data.type == ESP_ZB_ZCL_ATTR_TYPE_U16) {
+      uint16_t tolerance = attribute->data.value ? *(uint16_t *)attribute->data.value : 0;
+      _tolerance = 1.0 * tolerance / 100;
+      read_config++;
+    }
+    if (read_config == 3) {
+      read_config = 0;
+      xSemaphoreGive(lock);
+    }
+  }
+}
+
+void ZigbeeThermostat::getTemperature() {
+  /* Send "read attributes" command to the bound sensor */
+  esp_zb_zcl_read_attr_cmd_t read_req;
+  read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  read_req.zcl_basic_cmd.src_endpoint = _endpoint;
+  read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT;
+
+  uint16_t attributes[] = {ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID};
+  read_req.attr_number = ZB_ARRAY_LENTH(attributes);
+  read_req.attr_field = attributes;
+
+  log_i("Sending 'read temperature' command");
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_zb_zcl_read_attr_cmd_req(&read_req);
+  esp_zb_lock_release();
+}
+
+void ZigbeeThermostat::getSensorSettings() {
+  /* Send "read attributes" command to the bound sensor */
+  esp_zb_zcl_read_attr_cmd_t read_req;
+  read_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  read_req.zcl_basic_cmd.src_endpoint = _endpoint;
+  read_req.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT;
+
+  uint16_t attributes[] = {
+    ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MIN_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_MAX_VALUE_ID, ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_TOLERANCE_ID
+  };
+  read_req.attr_number = ZB_ARRAY_LENTH(attributes);
+  read_req.attr_field = attributes;
+
+  log_i("Sending 'read temperature' command");
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_zb_zcl_read_attr_cmd_req(&read_req);
+  esp_zb_lock_release();
+
+  //Take semaphore to wait for response of all attributes
+  if (xSemaphoreTake(lock, ZB_CMD_TIMEOUT) != pdTRUE) {
+    log_e("Error while reading attributes");
+    return;
+  } else {
+    //Call the callback function when all attributes are read
+    _on_config_recieve(_min_temp, _max_temp, _tolerance);
+  }
+}
+
+void ZigbeeThermostat::setTemperatureReporting(uint16_t min_interval, uint16_t max_interval, float delta) {
+  /* Send "configure report attribute" command to the bound sensor */
+  esp_zb_zcl_config_report_cmd_t report_cmd;
+  report_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_TEMP_MEASUREMENT;
+
+  int16_t report_change = (int16_t)delta * 100;
+  esp_zb_zcl_config_report_record_t records[] = {
+    {
+      .direction = ESP_ZB_ZCL_REPORT_DIRECTION_SEND,
+      .attributeID = ESP_ZB_ZCL_ATTR_TEMP_MEASUREMENT_VALUE_ID,
+      .attrType = ESP_ZB_ZCL_ATTR_TYPE_S16,
+      .min_interval = min_interval,
+      .max_interval = max_interval,
+      .reportable_change = &report_change,
+    },
+  };
+  report_cmd.record_number = ZB_ARRAY_LENTH(records);
+  report_cmd.record_field = records;
+
+  log_i("Sending 'configure reporting' command");
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_zb_zcl_config_report_cmd_req(&report_cmd);
+  esp_zb_lock_release();
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeThermostat.h b/libraries/Zigbee/src/ep/ZigbeeThermostat.h
new file mode 100644
index 00000000000..7895115e1d1
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeThermostat.h
@@ -0,0 +1,65 @@
+/* Class of Zigbee Temperature sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+//define the thermostat configuration to avoid narrowing conversion issue in zigbee-sdk
+#define ZB_DEFAULT_THERMOSTAT_CONFIG()                                                               \
+  {                                                                                                  \
+    .basic_cfg =                                                                                     \
+      {                                                                                              \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                                   \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                                 \
+      },                                                                                             \
+    .identify_cfg =                                                                                  \
+      {                                                                                              \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,                            \
+      },                                                                                             \
+    .thermostat_cfg = {                                                                              \
+      .local_temperature = (int16_t)ESP_ZB_ZCL_THERMOSTAT_LOCAL_TEMPERATURE_DEFAULT_VALUE,           \
+      .occupied_cooling_setpoint = ESP_ZB_ZCL_THERMOSTAT_OCCUPIED_COOLING_SETPOINT_DEFAULT_VALUE,    \
+      .occupied_heating_setpoint = ESP_ZB_ZCL_THERMOSTAT_OCCUPIED_HEATING_SETPOINT_DEFAULT_VALUE,    \
+      .control_sequence_of_operation = ESP_ZB_ZCL_THERMOSTAT_CONTROL_SEQ_OF_OPERATION_DEFAULT_VALUE, \
+      .system_mode = ESP_ZB_ZCL_THERMOSTAT_CONTROL_SYSTEM_MODE_DEFAULT_VALUE,                        \
+    },                                                                                               \
+  }
+class ZigbeeThermostat : public ZigbeeEP {
+public:
+  ZigbeeThermostat(uint8_t endpoint);
+  ~ZigbeeThermostat() {}
+
+  void onTempRecieve(void (*callback)(float)) {
+    _on_temp_recieve = callback;
+  }
+  void onConfigRecieve(void (*callback)(float, float, float)) {
+    _on_config_recieve = callback;
+  }
+
+  void getTemperature();
+  void getSensorSettings();
+  void setTemperatureReporting(uint16_t min_interval, uint16_t max_interval, float delta);
+
+private:
+  // save instance of the class in order to use it in static functions
+  static ZigbeeThermostat *_instance;
+
+  void (*_on_temp_recieve)(float);
+  void (*_on_config_recieve)(float, float, float);
+  float _min_temp;
+  float _max_temp;
+  float _tolerance;
+
+  void findEndpoint(esp_zb_zdo_match_desc_req_param_t *cmd_req);
+  static void bindCb(esp_zb_zdp_status_t zdo_status, void *user_ctx);
+  static void findCb(esp_zb_zdp_status_t zdo_status, uint16_t addr, uint8_t endpoint, void *user_ctx);
+
+  void zbAttributeRead(uint16_t cluster_id, const esp_zb_zcl_attribute_t *attribute) override;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.cpp
new file mode 100644
index 00000000000..6be457c389a
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.cpp
@@ -0,0 +1,91 @@
+#include "ZigbeeVibrationSensor.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *zigbee_vibration_sensor_clusters_create(zigbee_vibration_sensor_cfg_t *vibration_sensor) {
+  esp_zb_basic_cluster_cfg_t *basic_cfg = vibration_sensor ? &(vibration_sensor->basic_cfg) : NULL;
+  esp_zb_identify_cluster_cfg_t *identify_cfg = vibration_sensor ? &(vibration_sensor->identify_cfg) : NULL;
+  esp_zb_ias_zone_cluster_cfg_t *ias_zone_cfg = vibration_sensor ? &(vibration_sensor->ias_zone_cfg) : NULL;
+  esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_ias_zone_cluster(cluster_list, esp_zb_ias_zone_cluster_create(ias_zone_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  return cluster_list;
+}
+
+ZigbeeVibrationSensor::ZigbeeVibrationSensor(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_IAS_ZONE_ID;
+  _zone_status = 0;
+  _zone_id = 0xff;
+  _ias_cie_endpoint = 1;
+
+  //Create custom vibration sensor configuration
+  zigbee_vibration_sensor_cfg_t vibration_sensor_cfg = ZIGBEE_DEFAULT_VIBRATION_SENSOR_CONFIG();
+  _cluster_list = zigbee_vibration_sensor_clusters_create(&vibration_sensor_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_IAS_ZONE_ID, .app_device_version = 0};
+}
+
+void ZigbeeVibrationSensor::setIASClientEndpoint(uint8_t ep_number) {
+  _ias_cie_endpoint = ep_number;
+}
+
+bool ZigbeeVibrationSensor::setVibration(bool sensed) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  log_v("Setting Vibration sensor to %s", sensed ? "sensed" : "not sensed");
+  uint8_t vibration = (uint8_t)sensed;
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_ZONESTATUS_ID, &vibration, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set vibration status: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  _zone_status = vibration;
+  report();
+  return true;
+}
+
+void ZigbeeVibrationSensor::report() {
+  /* Send IAS Zone status changed notification command */
+
+  esp_zb_zcl_ias_zone_status_change_notif_cmd_t status_change_notif_cmd;
+  status_change_notif_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_64_ENDP_PRESENT;
+  status_change_notif_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  status_change_notif_cmd.zcl_basic_cmd.dst_endpoint = _ias_cie_endpoint;  //default is 1
+  memcpy(status_change_notif_cmd.zcl_basic_cmd.dst_addr_u.addr_long, _ias_cie_addr, sizeof(esp_zb_ieee_addr_t));
+  status_change_notif_cmd.zone_status = _zone_status;
+  status_change_notif_cmd.extend_status = 0;
+  status_change_notif_cmd.zone_id = _zone_id;
+  status_change_notif_cmd.delay = 0;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_zb_zcl_ias_zone_status_change_notif_cmd_req(&status_change_notif_cmd);
+  esp_zb_lock_release();
+  log_v("IAS Zone status changed notification sent");
+}
+
+void ZigbeeVibrationSensor::zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) {
+  if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE) {
+    log_v("IAS Zone Enroll Response: zone id(%d), status(%d)", message->zone_id, message->response_code);
+    if (message->response_code == ESP_ZB_ZCL_IAS_ZONE_ENROLL_RESPONSE_CODE_SUCCESS) {
+      log_v("IAS Zone Enroll Response: success");
+      esp_zb_lock_acquire(portMAX_DELAY);
+      memcpy(
+        _ias_cie_addr,
+        (*(esp_zb_ieee_addr_t *)
+            esp_zb_zcl_get_attribute(_endpoint, ESP_ZB_ZCL_CLUSTER_ID_IAS_ZONE, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_IAS_ZONE_IAS_CIE_ADDRESS_ID)
+              ->data_p),
+        sizeof(esp_zb_ieee_addr_t)
+      );
+      esp_zb_lock_release();
+      _zone_id = message->zone_id;
+    }
+
+  } else {
+    log_w("Received message ignored. Cluster ID: %d not supported for On/Off Light", message->info.cluster);
+  }
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.h b/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.h
new file mode 100644
index 00000000000..2f67c7bb6b4
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeVibrationSensor.h
@@ -0,0 +1,64 @@
+/* Class of Zigbee contact switch (IAS Zone) endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+// clang-format off
+#define ZIGBEE_DEFAULT_VIBRATION_SENSOR_CONFIG()                                                    \
+    {                                                                                               \
+        .basic_cfg =                                                                                \
+            {                                                                                       \
+                .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                          \
+                .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                        \
+            },                                                                                      \
+        .identify_cfg =                                                                             \
+            {                                                                                       \
+                .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,                   \
+            },                                                                                      \
+        .ias_zone_cfg =                                                                             \
+            {                                                                                       \
+                .zone_state = ESP_ZB_ZCL_IAS_ZONE_ZONESTATE_NOT_ENROLLED,                           \
+                .zone_type = ESP_ZB_ZCL_IAS_ZONE_ZONETYPE_VIBRATION_MOVEMENT,                       \
+                .zone_status = 0,                                                                   \
+                .ias_cie_addr = ESP_ZB_ZCL_ZONE_IAS_CIE_ADDR_DEFAULT,                               \
+                .zone_id = 0xff,                                                                    \
+                .zone_ctx = {0, 0, 0, 0},                                                           \
+            },                                                                                      \
+    }
+// clang-format on
+
+typedef struct zigbee_vibration_sensor_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_ias_zone_cluster_cfg_t ias_zone_cfg;
+} zigbee_vibration_sensor_cfg_t;
+
+class ZigbeeVibrationSensor : public ZigbeeEP {
+public:
+  ZigbeeVibrationSensor(uint8_t endpoint);
+  ~ZigbeeVibrationSensor() {}
+
+  // Set the IAS Client endpoint number (default is 1)
+  void setIASClientEndpoint(uint8_t ep_number);
+
+  // Set the vibration sensor value (true = sensed, false = not sensed)
+  bool setVibration(bool sensed);
+
+  // Report the vibration sensor value, done automatically after setting the sensed value
+  void report();
+
+private:
+  void zbIASZoneEnrollResponse(const esp_zb_zcl_ias_zone_enroll_response_message_t *message) override;
+  uint8_t _zone_status;
+  uint8_t _zone_id;
+  esp_zb_ieee_addr_t _ias_cie_addr;
+  uint8_t _ias_cie_endpoint;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.cpp b/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.cpp
new file mode 100644
index 00000000000..72184927d4d
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.cpp
@@ -0,0 +1,128 @@
+#include "ZigbeeWindSpeedSensor.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *zigbee_wind_speed_sensor_clusters_create(zigbee_wind_speed_sensor_cfg_t *wind_speed_sensor) {
+  esp_zb_basic_cluster_cfg_t *basic_cfg = wind_speed_sensor ? &(wind_speed_sensor->basic_cfg) : NULL;
+  esp_zb_identify_cluster_cfg_t *identify_cfg = wind_speed_sensor ? &(wind_speed_sensor->identify_cfg) : NULL;
+  esp_zb_wind_speed_measurement_cluster_cfg_t *wind_speed_cfg = wind_speed_sensor ? &(wind_speed_sensor->wind_speed_meas_cfg) : NULL;
+  esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(cluster_list, esp_zb_basic_cluster_create(basic_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(identify_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_wind_speed_measurement_cluster(
+    cluster_list, esp_zb_wind_speed_measurement_cluster_create(wind_speed_cfg), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE
+  );
+  return cluster_list;
+}
+
+// There is no device_id for wind speed sensor, we use a generic one
+ZigbeeWindSpeedSensor::ZigbeeWindSpeedSensor(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID;
+
+  zigbee_wind_speed_sensor_cfg_t windspeed_sensor_cfg = ZIGBEE_DEFAULT_WIND_SPEED_SENSOR_CONFIG();
+  _cluster_list = zigbee_wind_speed_sensor_clusters_create(&windspeed_sensor_cfg);
+
+  _ep_config = {.endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_SIMPLE_SENSOR_DEVICE_ID, .app_device_version = 0};
+}
+
+static uint16_t zb_windspeed_to_u16(float windspeed) {
+  return (uint16_t)(windspeed * 100);
+}
+
+bool ZigbeeWindSpeedSensor::setMinMaxValue(float min, float max) {
+  uint16_t zb_min = zb_windspeed_to_u16(min);
+  uint16_t zb_max = zb_windspeed_to_u16(max);
+  esp_zb_attribute_list_t *windspeed_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(windspeed_measure_cluster, ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MIN_MEASURED_VALUE_ID, (void *)&zb_min);
+  if (ret != ESP_OK) {
+    log_e("Failed to set min value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(windspeed_measure_cluster, ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MAX_MEASURED_VALUE_ID, (void *)&zb_max);
+  if (ret != ESP_OK) {
+    log_e("Failed to set max value: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeWindSpeedSensor::setTolerance(float tolerance) {
+  // Convert tolerance to ZCL uint16_t
+  uint16_t zb_tolerance = zb_windspeed_to_u16(tolerance);
+  esp_zb_attribute_list_t *windspeed_measure_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret =
+    esp_zb_wind_speed_measurement_cluster_add_attr(windspeed_measure_cluster, ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_TOLERANCE_ID, (void *)&zb_tolerance);
+  if (ret != ESP_OK) {
+    log_e("Failed to set tolerance: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeWindSpeedSensor::setReporting(uint16_t min_interval, uint16_t max_interval, float delta) {
+  esp_zb_zcl_reporting_info_t reporting_info;
+  memset(&reporting_info, 0, sizeof(esp_zb_zcl_reporting_info_t));
+  reporting_info.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_SRV;
+  reporting_info.ep = _endpoint;
+  reporting_info.cluster_id = ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT;
+  reporting_info.cluster_role = ESP_ZB_ZCL_CLUSTER_SERVER_ROLE;
+  reporting_info.attr_id = ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MEASURED_VALUE_ID;
+  reporting_info.u.send_info.min_interval = min_interval;
+  reporting_info.u.send_info.max_interval = max_interval;
+  reporting_info.u.send_info.def_min_interval = min_interval;
+  reporting_info.u.send_info.def_max_interval = max_interval;
+  reporting_info.u.send_info.delta.u16 = (uint16_t)(delta * 100);  // Convert delta to ZCL uint16_t
+  reporting_info.dst.profile_id = ESP_ZB_AF_HA_PROFILE_ID;
+  reporting_info.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_update_reporting_info(&reporting_info);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to set reporting: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeWindSpeedSensor::setWindSpeed(float windspeed) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  uint16_t zb_windspeed = zb_windspeed_to_u16(windspeed);
+  log_v("Updating windspeed sensor value...");
+  /* Update windspeed sensor measured value */
+  log_d("Setting windspeed to %d", zb_windspeed);
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MEASURED_VALUE_ID,
+    &zb_windspeed, false
+  );
+  esp_zb_lock_release();
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set wind speed: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeWindSpeedSensor::reportWindSpeed() {
+  /* Send report attributes command */
+  esp_zb_zcl_report_attr_cmd_t report_attr_cmd;
+  report_attr_cmd.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
+  report_attr_cmd.attributeID = ESP_ZB_ZCL_ATTR_WIND_SPEED_MEASUREMENT_MEASURED_VALUE_ID;
+  report_attr_cmd.direction = ESP_ZB_ZCL_CMD_DIRECTION_TO_CLI;
+  report_attr_cmd.clusterID = ESP_ZB_ZCL_CLUSTER_ID_WIND_SPEED_MEASUREMENT;
+  report_attr_cmd.zcl_basic_cmd.src_endpoint = _endpoint;
+  report_attr_cmd.manuf_code = ESP_ZB_ZCL_ATTR_NON_MANUFACTURER_SPECIFIC;
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  esp_err_t ret = esp_zb_zcl_report_attr_cmd_req(&report_attr_cmd);
+  esp_zb_lock_release();
+  if (ret != ESP_OK) {
+    log_e("Failed to send wind speed report: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  log_v("Wind speed measurement report sent");
+  return true;
+}
+
+#endif  //CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.h b/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.h
new file mode 100644
index 00000000000..641c1d84780
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeWindSpeedSensor.h
@@ -0,0 +1,56 @@
+/* Class of Zigbee WindSpeed sensor endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+#define ZIGBEE_DEFAULT_WIND_SPEED_SENSOR_CONFIG()                                         \
+  {                                                                                       \
+    .basic_cfg =                                                                          \
+      {                                                                                   \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                        \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                      \
+      },                                                                                  \
+    .identify_cfg =                                                                       \
+      {                                                                                   \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,                 \
+      },                                                                                  \
+    .wind_speed_meas_cfg = {                                                              \
+      .measured_value = ESP_ZB_ZCL_WIND_SPEED_MEASUREMENT_MEASURED_VALUE_DEFAULT,         \
+      .min_measured_value = ESP_ZB_ZCL_WIND_SPEED_MEASUREMENT_MIN_MEASURED_VALUE_DEFAULT, \
+      .max_measured_value = ESP_ZB_ZCL_WIND_SPEED_MEASUREMENT_MAX_MEASURED_VALUE_DEFAULT, \
+    },                                                                                    \
+  }
+
+typedef struct zigbee_wind_speed_sensor_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;       /*!<  Basic cluster configuration, @ref esp_zb_basic_cluster_cfg_s */
+  esp_zb_identify_cluster_cfg_t identify_cfg; /*!<  Identify cluster configuration, @ref esp_zb_identify_cluster_cfg_s */
+  esp_zb_wind_speed_measurement_cluster_cfg_t
+    wind_speed_meas_cfg; /*!<  Wind speed measurement cluster configuration, @ref esp_zb_wind_speed_measurement_cluster_cfg_s */
+} zigbee_wind_speed_sensor_cfg_t;
+
+class ZigbeeWindSpeedSensor : public ZigbeeEP {
+public:
+  ZigbeeWindSpeedSensor(uint8_t endpoint);
+  ~ZigbeeWindSpeedSensor() {}
+
+  // Set the WindSpeed value in 0,01 m/s
+  bool setWindSpeed(float value);
+
+  // Set the min and max value for the WindSpeed sensor
+  bool setMinMaxValue(float min, float max);
+
+  // Set the tolerance value for the WindSpeed sensor
+  bool setTolerance(float tolerance);
+
+  // Set the reporting interval for WindSpeed measurement in seconds and delta
+  bool setReporting(uint16_t min_interval, uint16_t max_interval, float delta);
+  bool reportWindSpeed();
+};
+
+#endif  //CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeWindowCovering.cpp b/libraries/Zigbee/src/ep/ZigbeeWindowCovering.cpp
new file mode 100644
index 00000000000..7c7889dbbf7
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeWindowCovering.cpp
@@ -0,0 +1,394 @@
+#include "ZigbeeWindowCovering.h"
+#if CONFIG_ZB_ENABLED
+
+esp_zb_cluster_list_t *ZigbeeWindowCovering::zigbee_window_covering_clusters_create(zigbee_window_covering_cfg_t *window_covering_cfg) {
+  esp_zb_attribute_list_t *esp_zb_basic_cluster = esp_zb_basic_cluster_create(&window_covering_cfg->basic_cfg);
+  esp_zb_attribute_list_t *esp_zb_identify_cluster = esp_zb_identify_cluster_create(&window_covering_cfg->identify_cfg);
+  esp_zb_attribute_list_t *esp_zb_groups_cluster = esp_zb_groups_cluster_create(&window_covering_cfg->groups_cfg);
+  esp_zb_attribute_list_t *esp_zb_scenes_cluster = esp_zb_scenes_cluster_create(&window_covering_cfg->scenes_cfg);
+  esp_zb_attribute_list_t *esp_zb_window_covering_cluster = esp_zb_window_covering_cluster_create(&window_covering_cfg->window_covering_cfg);
+
+  esp_zb_window_covering_cluster_add_attr(
+    esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_PERCENTAGE_ID, &_current_lift_percentage
+  );
+  esp_zb_window_covering_cluster_add_attr(
+    esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_PERCENTAGE_ID, &_current_tilt_percentage
+  );
+  esp_zb_window_covering_cluster_add_attr(esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_ID, &_current_lift_position);
+  esp_zb_window_covering_cluster_add_attr(esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_ID, &_current_lift_position);
+  esp_zb_window_covering_cluster_add_attr(
+    esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_LIFT_ID, &_installed_open_limit_lift
+  );
+  esp_zb_window_covering_cluster_add_attr(
+    esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_TILT_ID, &_installed_open_limit_tilt
+  );
+  esp_zb_window_covering_cluster_add_attr(
+    esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_LIFT_ID, &_installed_closed_limit_lift
+  );
+  esp_zb_window_covering_cluster_add_attr(
+    esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_TILT_ID, &_installed_closed_limit_tilt
+  );
+  esp_zb_window_covering_cluster_add_attr(
+    esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_PHYSICAL_CLOSED_LIMIT_LIFT_ID, &_physical_closed_limit_lift
+  );
+  esp_zb_window_covering_cluster_add_attr(
+    esp_zb_window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_PHY_CLOSED_LIMIT_TILT_ID, &_physical_closed_limit_lift
+  );
+
+  // ------------------------------ Create cluster list ------------------------------
+  esp_zb_cluster_list_t *esp_zb_cluster_list = esp_zb_zcl_cluster_list_create();
+  esp_zb_cluster_list_add_basic_cluster(esp_zb_cluster_list, esp_zb_basic_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_identify_cluster(esp_zb_cluster_list, esp_zb_identify_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_groups_cluster(esp_zb_cluster_list, esp_zb_groups_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_scenes_cluster(esp_zb_cluster_list, esp_zb_scenes_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_zb_cluster_list_add_window_covering_cluster(esp_zb_cluster_list, esp_zb_window_covering_cluster, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+
+  return esp_zb_cluster_list;
+}
+
+ZigbeeWindowCovering::ZigbeeWindowCovering(uint8_t endpoint) : ZigbeeEP(endpoint) {
+  _device_id = ESP_ZB_HA_WINDOW_COVERING_DEVICE_ID;
+
+  // set default values for window covering attributes
+  _current_lift_percentage = ESP_ZB_ZCL_WINDOW_COVERING_CURRENT_POSITION_LIFT_PERCENTAGE_DEFAULT_VALUE;
+  _current_tilt_percentage = ESP_ZB_ZCL_WINDOW_COVERING_CURRENT_POSITION_TILT_PERCENTAGE_DEFAULT_VALUE;
+  _installed_open_limit_lift = ESP_ZB_ZCL_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_LIFT_DEFAULT_VALUE;
+  _installed_closed_limit_lift = ESP_ZB_ZCL_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_LIFT_DEFAULT_VALUE;
+  _installed_open_limit_tilt = ESP_ZB_ZCL_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_TILT_DEFAULT_VALUE;
+  _installed_closed_limit_tilt = ESP_ZB_ZCL_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_TILT_DEFAULT_VALUE;
+  _current_lift_position = ESP_ZB_ZCL_WINDOW_COVERING_CURRENT_POSITION_LIFT_DEFAULT_VALUE;
+  _current_tilt_position = ESP_ZB_ZCL_WINDOW_COVERING_CURRENT_POSITION_TILT_DEFAULT_VALUE;
+  _physical_closed_limit_lift = ESP_ZB_ZCL_WINDOW_COVERING_PHYSICAL_CLOSED_LIMIT_LIFT_DEFAULT_VALUE;
+  _physical_closed_limit_tilt = ESP_ZB_ZCL_WINDOW_COVERING_PHY_CLOSED_LIMIT_TILT_DEFAULT_VALUE;
+
+  // Create custom window covering configuration
+  zigbee_window_covering_cfg_t window_covering_cfg = ZIGBEE_DEFAULT_WINDOW_COVERING_CONFIG();
+  _cluster_list = zigbee_window_covering_clusters_create(&window_covering_cfg);
+
+  _ep_config = {
+    .endpoint = _endpoint, .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID, .app_device_id = ESP_ZB_HA_WINDOW_COVERING_DEVICE_ID, .app_device_version = 0
+  };
+}
+
+// Configuration methods for window covering
+bool ZigbeeWindowCovering::setCoveringType(ZigbeeWindowCoveringType covering_type) {
+  esp_zb_attribute_list_t *window_covering_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_WINDOW_COVERING_TYPE_ID, (void *)&covering_type);
+  if (ret != ESP_OK) {
+    log_e("Failed to set covering type: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeWindowCovering::setConfigStatus(
+  bool operational, bool online, bool commands_reversed, bool lift_closed_loop, bool tilt_closed_loop, bool lift_encoder_controlled,
+  bool tilt_encoder_controlled
+) {
+  uint8_t config_status = (operational ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_OPERATIONAL : 0) | (online ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_ONLINE : 0)
+                          | (commands_reversed ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_REVERSE_COMMANDS : 0)
+                          | (lift_closed_loop ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_LIFT_CONTROL_IS_CLOSED_LOOP : 0)
+                          | (tilt_closed_loop ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_TILT_CONTROL_IS_CLOSED_LOOP : 0)
+                          | (lift_encoder_controlled ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_LIFT_ENCODER_CONTROLLED : 0)
+                          | (tilt_encoder_controlled ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_TILT_ENCODER_CONTROLLED : 0);
+
+  log_v("Updating window covering config status to %d", config_status);
+
+  esp_zb_attribute_list_t *window_covering_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_STATUS_ID, (void *)&config_status);
+  if (ret != ESP_OK) {
+    log_e("Failed to set config status: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeWindowCovering::setMode(bool motor_reversed, bool calibration_mode, bool maintenance_mode, bool leds_on) {
+  uint8_t mode = (motor_reversed ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_REVERSED_MOTOR_DIRECTION : 0)
+                 | (calibration_mode ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_RUN_IN_CALIBRATION_MODE : 0)
+                 | (maintenance_mode ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_MOTOR_IS_RUNNING_IN_MAINTENANCE_MODE : 0)
+                 | (leds_on ? ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_LEDS_WILL_DISPLAY_FEEDBACK : 0);
+
+  log_v("Updating window covering mode to %d", mode);
+
+  esp_zb_attribute_list_t *window_covering_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_MODE_ID, (void *)&mode);
+  if (ret != ESP_OK) {
+    log_e("Failed to set mode: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+bool ZigbeeWindowCovering::setLimits(
+  uint16_t installed_open_limit_lift, uint16_t installed_closed_limit_lift, uint16_t installed_open_limit_tilt, uint16_t installed_closed_limit_tilt
+) {
+  _installed_open_limit_lift = installed_open_limit_lift;
+  _installed_closed_limit_lift = installed_closed_limit_lift;
+  _physical_closed_limit_lift = installed_closed_limit_lift;
+  _installed_open_limit_tilt = installed_open_limit_tilt;
+  _installed_closed_limit_tilt = installed_closed_limit_tilt;
+  _physical_closed_limit_tilt = installed_closed_limit_tilt;
+
+  esp_zb_attribute_list_t *window_covering_cluster =
+    esp_zb_cluster_list_get_cluster(_cluster_list, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+  esp_err_t ret =
+    esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_LIFT_ID, (void *)&_installed_open_limit_lift);
+  if (ret != ESP_OK) {
+    log_e("Failed to set installed open limit lift: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret =
+    esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_LIFT_ID, (void *)&_installed_closed_limit_lift);
+  if (ret != ESP_OK) {
+    log_e("Failed to set installed closed limit lift: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_OPEN_LIMIT_TILT_ID, (void *)&_installed_open_limit_tilt);
+  if (ret != ESP_OK) {
+    log_e("Failed to set installed open limit tilt: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret =
+    esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_INSTALLED_CLOSED_LIMIT_TILT_ID, (void *)&_installed_closed_limit_tilt);
+  if (ret != ESP_OK) {
+    log_e("Failed to set installed closed limit tilt: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret =
+    esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_PHYSICAL_CLOSED_LIMIT_LIFT_ID, (void *)&_physical_closed_limit_lift);
+  if (ret != ESP_OK) {
+    log_e("Failed to set physical closed limit lift: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  ret = esp_zb_cluster_update_attr(window_covering_cluster, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_PHY_CLOSED_LIMIT_TILT_ID, (void *)&_physical_closed_limit_tilt);
+  if (ret != ESP_OK) {
+    log_e("Failed to set physical closed limit tilt: 0x%x: %s", ret, esp_err_to_name(ret));
+    return false;
+  }
+  return true;
+}
+
+// Callback for handling incoming messages and commands
+void ZigbeeWindowCovering::zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) {
+  //check the data and call right method
+  if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING) {
+    log_v("Received attribute id: 0x%x / data.type: 0x%x", message->attribute.id, message->attribute.data.type);
+    if (message->attribute.id == ESP_ZB_ZCL_ATTR_WINDOW_COVERING_MODE_ID && message->attribute.data.type == ESP_ZB_ZCL_ATTR_TYPE_8BITMAP) {
+      uint8_t mode = *(uint8_t *)message->attribute.data.value;
+      bool motor_reversed = mode & ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_REVERSED_MOTOR_DIRECTION;
+      bool calibration_mode = mode & ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_RUN_IN_CALIBRATION_MODE;
+      bool maintenance_mode = mode & ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_MOTOR_IS_RUNNING_IN_MAINTENANCE_MODE;
+      bool leds_on = mode & ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_LEDS_WILL_DISPLAY_FEEDBACK;
+      log_v(
+        "Updating window covering mode to motor reversed: %d, calibration mode: %d, maintenance mode: %d, leds on: %d", motor_reversed, calibration_mode,
+        maintenance_mode, leds_on
+      );
+      setMode(motor_reversed, calibration_mode, maintenance_mode, leds_on);
+      //Update Configuration status with motor reversed status
+      uint8_t config_status;
+      config_status = (*(uint8_t *)esp_zb_zcl_get_attribute(
+                          _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_STATUS_ID
+      )
+                          ->data_p);
+      config_status = motor_reversed ? config_status | ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_REVERSE_COMMANDS
+                                     : config_status & ~ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_REVERSE_COMMANDS;
+      log_v("Updating window covering config status to %d", config_status);
+      esp_zb_lock_acquire(portMAX_DELAY);
+      esp_zb_zcl_set_attribute_val(
+        _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CONFIG_STATUS_ID, &config_status,
+        false
+      );
+      esp_zb_lock_release();
+      return;
+    }
+  } else {
+    log_w("Received message ignored. Cluster ID: %d not supported for Window Covering", message->info.cluster);
+  }
+}
+
+void ZigbeeWindowCovering::zbWindowCoveringMovementCmd(const esp_zb_zcl_window_covering_movement_message_t *message) {
+  // check the data and call right method
+  if (message->info.cluster == ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING) {
+    if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_UP_OPEN) {
+      open();
+      return;
+    } else if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_DOWN_CLOSE) {
+      close();
+      return;
+    } else if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_STOP) {
+      stop();
+      return;
+    } else if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_GO_TO_LIFT_PERCENTAGE) {
+      if (_current_lift_percentage != message->payload.percentage_lift_value) {
+        _current_lift_percentage = message->payload.percentage_lift_value;
+        goToLiftPercentage(_current_lift_percentage);
+        return;
+      }
+    } else if (message->command == ESP_ZB_ZCL_CMD_WINDOW_COVERING_GO_TO_TILT_PERCENTAGE) {
+      if (_current_tilt_percentage != message->payload.percentage_tilt_value) {
+        _current_tilt_percentage = message->payload.percentage_tilt_value;
+        goToTiltPercentage(_current_tilt_percentage);
+        return;
+      }
+    } else {
+      log_w("Received message ignored. Command: %d not supported for Window Covering", message->command);
+    }
+  } else {
+    log_w("Received message ignored. Cluster ID: %d not supported for Window Covering", message->info.cluster);
+  }
+}
+
+void ZigbeeWindowCovering::open() {
+  if (_on_open) {
+    _on_open();
+  }
+}
+
+void ZigbeeWindowCovering::close() {
+  if (_on_close) {
+    _on_close();
+  }
+}
+
+void ZigbeeWindowCovering::goToLiftPercentage(uint8_t lift_percentage) {
+  if (_on_go_to_lift_percentage) {
+    _on_go_to_lift_percentage(lift_percentage);
+  }
+}
+
+void ZigbeeWindowCovering::goToTiltPercentage(uint8_t tilt_percentage) {
+  if (_on_go_to_tilt_percentage) {
+    _on_go_to_tilt_percentage(tilt_percentage);
+  }
+}
+
+void ZigbeeWindowCovering::stop() {
+  if (_on_stop) {
+    _on_stop();
+  }
+}
+
+// Methods to control window covering from user application
+bool ZigbeeWindowCovering::setLiftPosition(uint16_t lift_position) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  // Update both lift attributes
+  _current_lift_position = lift_position;
+  _current_lift_percentage = ((lift_position - _installed_open_limit_lift) * 100) / (_installed_closed_limit_lift - _installed_open_limit_lift);
+  log_v("Updating window covering lift position to %d (%d%)", _current_lift_position, _current_lift_percentage);
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_ID,
+    &_current_lift_position, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set lift position: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_PERCENTAGE_ID,
+    &_current_lift_percentage, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set lift percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+unlock_and_return:
+  esp_zb_lock_release();
+  return ret == ESP_ZB_ZCL_STATUS_SUCCESS;
+}
+
+bool ZigbeeWindowCovering::setLiftPercentage(uint8_t lift_percentage) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  // Update both lift attributes
+  _current_lift_percentage = lift_percentage;
+  _current_lift_position = _installed_open_limit_lift + ((_installed_closed_limit_lift - _installed_open_limit_lift) * lift_percentage) / 100;
+  log_v("Updating window covering lift percentage to %d%% (%d)", _current_lift_percentage, _current_lift_position);
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_ID,
+    &_current_lift_position, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set lift position: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_LIFT_PERCENTAGE_ID,
+    &_current_lift_percentage, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set lift percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+unlock_and_return:
+  esp_zb_lock_release();
+  return ret == ESP_ZB_ZCL_STATUS_SUCCESS;
+}
+
+bool ZigbeeWindowCovering::setTiltPosition(uint16_t tilt_position) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  // Update both tilt attributes
+  _current_tilt_position = tilt_position;
+  _current_tilt_percentage = ((tilt_position - _installed_open_limit_tilt) * 100) / (_installed_closed_limit_tilt - _installed_open_limit_tilt);
+
+  log_v("Updating window covering tilt position to %d (%d%)", _current_tilt_position, _current_tilt_percentage);
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_ID,
+    &_current_tilt_position, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set tilt position: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_PERCENTAGE_ID,
+    &_current_tilt_percentage, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set tilt percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+unlock_and_return:
+  esp_zb_lock_release();
+  return ret == ESP_ZB_ZCL_STATUS_SUCCESS;
+}
+
+bool ZigbeeWindowCovering::setTiltPercentage(uint8_t tilt_percentage) {
+  esp_zb_zcl_status_t ret = ESP_ZB_ZCL_STATUS_SUCCESS;
+  // Update both tilt attributes
+  _current_tilt_percentage = tilt_percentage;
+  _current_tilt_position = _installed_open_limit_tilt + ((_installed_closed_limit_tilt - _installed_open_limit_tilt) * tilt_percentage) / 100;
+
+  log_v("Updating window covering tilt percentage to %d%% (%d)", _current_tilt_percentage, _current_tilt_position);
+
+  esp_zb_lock_acquire(portMAX_DELAY);
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_ID,
+    &_current_tilt_position, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set tilt position: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+  ret = esp_zb_zcl_set_attribute_val(
+    _endpoint, ESP_ZB_ZCL_CLUSTER_ID_WINDOW_COVERING, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE, ESP_ZB_ZCL_ATTR_WINDOW_COVERING_CURRENT_POSITION_TILT_PERCENTAGE_ID,
+    &_current_tilt_percentage, false
+  );
+  if (ret != ESP_ZB_ZCL_STATUS_SUCCESS) {
+    log_e("Failed to set tilt percentage: 0x%x: %s", ret, esp_zb_zcl_status_to_name(ret));
+    goto unlock_and_return;
+  }
+unlock_and_return:
+  esp_zb_lock_release();
+  return ret == ESP_ZB_ZCL_STATUS_SUCCESS;
+}
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/libraries/Zigbee/src/ep/ZigbeeWindowCovering.h b/libraries/Zigbee/src/ep/ZigbeeWindowCovering.h
new file mode 100644
index 00000000000..288d92c5765
--- /dev/null
+++ b/libraries/Zigbee/src/ep/ZigbeeWindowCovering.h
@@ -0,0 +1,147 @@
+/* Class of Zigbee Window Covering endpoint inherited from common EP class */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_ZB_ENABLED
+
+#include "ZigbeeEP.h"
+#include "ha/esp_zigbee_ha_standard.h"
+
+// Window covering types supported by Zigbee Window Covering cluster
+enum ZigbeeWindowCoveringType {
+  ROLLERSHADE = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_ROLLERSHADE,                                    // LIFT support
+  ROLLERSHADE_2_MOTOR = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_ROLLERSHADE_2_MOTOR,                    // LIFT support
+  ROLLERSHADE_EXTERIOR = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_ROLLERSHADE_EXTERIOR,                  // LIFT support
+  ROLLERSHADE_EXTERIOR_2_MOTOR = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_ROLLERSHADE_EXTERIOR_2_MOTOR,  // LIFT support
+  DRAPERY = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_DRAPERY,                                            // LIFT support
+  AWNING = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_AWNING,                                              // LIFT support
+  SHUTTER = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_SHUTTER,                                            // TILT support
+  BLIND_TILT_ONLY = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_TILT_BLIND_TILT_ONLY,                       // TILT support
+  BLIND_LIFT_AND_TILT = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_TILT_BLIND_LIFT_AND_TILT,               // LIFT and TILT support
+  PROJECTOR_SCREEN = ESP_ZB_ZCL_ATTR_WINDOW_COVERING_TYPE_PROJECTOR_SCREEN,                          // LIFT support
+};
+
+// clang-format off
+#define ZIGBEE_DEFAULT_WINDOW_COVERING_CONFIG()                                         \
+  {                                                                                     \
+    .basic_cfg =                                                                        \
+      {                                                                                 \
+        .zcl_version = ESP_ZB_ZCL_BASIC_ZCL_VERSION_DEFAULT_VALUE,                      \
+        .power_source = ESP_ZB_ZCL_BASIC_POWER_SOURCE_DEFAULT_VALUE,                    \
+      },                                                                                \
+    .identify_cfg =                                                                     \
+      {                                                                                 \
+        .identify_time = ESP_ZB_ZCL_IDENTIFY_IDENTIFY_TIME_DEFAULT_VALUE,               \
+      },                                                                                \
+    .groups_cfg =                                                                       \
+      {                                                                                 \
+        .groups_name_support_id = ESP_ZB_ZCL_GROUPS_NAME_SUPPORT_DEFAULT_VALUE,         \
+      },                                                                                \
+    .scenes_cfg =                                                                       \
+      {                                                                                 \
+        .scenes_count = ESP_ZB_ZCL_SCENES_SCENE_COUNT_DEFAULT_VALUE,                    \
+        .current_scene = ESP_ZB_ZCL_SCENES_CURRENT_SCENE_DEFAULT_VALUE,                 \
+        .current_group = ESP_ZB_ZCL_SCENES_CURRENT_GROUP_DEFAULT_VALUE,                 \
+        .scene_valid = ESP_ZB_ZCL_SCENES_SCENE_VALID_DEFAULT_VALUE,                     \
+        .name_support = ESP_ZB_ZCL_SCENES_NAME_SUPPORT_DEFAULT_VALUE,                   \
+      },                                                                                \
+    .window_covering_cfg =                                                              \
+      {                                                                                 \
+        .covering_type = ESP_ZB_ZCL_WINDOW_COVERING_WINDOW_COVERING_TYPE_DEFAULT_VALUE, \
+        .covering_status = ESP_ZB_ZCL_WINDOW_COVERING_CONFIG_STATUS_DEFAULT_VALUE,      \
+        .covering_mode = ESP_ZB_ZCL_WINDOW_COVERING_MODE_DEFAULT_VALUE,                 \
+      },                                                                                \
+  }
+// clang-format on
+
+typedef struct zigbee_window_covering_cfg_s {
+  esp_zb_basic_cluster_cfg_t basic_cfg;
+  esp_zb_identify_cluster_cfg_t identify_cfg;
+  esp_zb_groups_cluster_cfg_t groups_cfg;
+  esp_zb_scenes_cluster_cfg_t scenes_cfg;
+  esp_zb_window_covering_cluster_cfg_t window_covering_cfg;
+} zigbee_window_covering_cfg_t;
+
+class ZigbeeWindowCovering : public ZigbeeEP {
+public:
+  ZigbeeWindowCovering(uint8_t endpoint);
+  ~ZigbeeWindowCovering() {}
+
+  // Set the callback functions for the window covering commands
+  void onOpen(void (*callback)()) {
+    _on_open = callback;
+  }
+  void onClose(void (*callback)()) {
+    _on_close = callback;
+  }
+  void onGoToLiftPercentage(void (*callback)(uint8_t)) {
+    _on_go_to_lift_percentage = callback;
+  }
+  void onGoToTiltPercentage(void (*callback)(uint8_t)) {
+    _on_go_to_tilt_percentage = callback;
+  }
+  void onStop(void (*callback)()) {
+    _on_stop = callback;
+  }
+
+  // Set the window covering position in centimeters or percentage (0-100)
+  bool setLiftPosition(uint16_t lift_position);
+  bool setLiftPercentage(uint8_t lift_percentage);
+  bool setTiltPosition(uint16_t tilt_position);
+  bool setTiltPercentage(uint8_t tilt_percentage);
+
+  // Set the window covering type (see ZigbeeWindowCoveringType)
+  bool setCoveringType(ZigbeeWindowCoveringType covering_type);
+
+  // Set window covering config/status, for more info see esp_zb_zcl_window_covering_config_status_t
+  bool setConfigStatus(
+    bool operational, bool online, bool commands_reversed, bool lift_closed_loop, bool tilt_closed_loop, bool lift_encoder_controlled,
+    bool tilt_encoder_controlled
+  );
+
+  // Set configuration mode of window covering, for more info see esp_zb_zcl_window_covering_mode_t
+  bool setMode(bool motor_reversed, bool calibration_mode, bool maintenance_mode, bool leds_on);
+
+  // Set limits of motion, for more info see esp_zb_zcl_window_covering_info_attr_t
+  bool setLimits(
+    uint16_t installed_open_limit_lift, uint16_t installed_closed_limit_lift, uint16_t installed_open_limit_tilt, uint16_t installed_closed_limit_tilt
+  );
+
+private:
+  void zbAttributeSet(const esp_zb_zcl_set_attr_value_message_t *message) override;
+  void zbWindowCoveringMovementCmd(const esp_zb_zcl_window_covering_movement_message_t *message) override;
+
+  // Create window covering cluster list
+  esp_zb_cluster_list_t *zigbee_window_covering_clusters_create(zigbee_window_covering_cfg_t *window_covering_cfg);
+
+  void open();
+  void close();
+  void goToLiftPercentage(uint8_t);
+  void goToTiltPercentage(uint8_t);
+  void stop();
+
+  // callback function to be called on lift percentage change (lift percentage)
+  void (*_on_open)();
+  void (*_on_close)();
+  void (*_on_go_to_lift_percentage)(uint8_t);
+  void (*_on_go_to_tilt_percentage)(uint8_t);
+  void (*_on_stop)();
+
+  // Widows covering lift attributes
+  uint8_t _current_lift_percentage;
+  uint16_t _current_lift_position;
+  uint16_t _installed_open_limit_lift;
+  uint16_t _installed_closed_limit_lift;
+  uint16_t _physical_closed_limit_lift;
+
+  // Windows covering tilt attributes
+  uint8_t _current_tilt_percentage;
+  uint16_t _current_tilt_position;
+  uint16_t _installed_open_limit_tilt;
+  uint16_t _installed_closed_limit_tilt;
+  uint16_t _physical_closed_limit_tilt;
+};
+
+#endif  // CONFIG_ZB_ENABLED
diff --git a/package.json b/package.json
old mode 100755
new mode 100644
index 1a7f443f58a..9c918733209
--- a/package.json
+++ b/package.json
@@ -1,6 +1,16 @@
 {
-    "name": "framework-arduinoespressif32",
-    "description": "Arduino Wiring-based Framework (ESP32 Core)",
-    "version": "0.0.0",
+  "name": "framework-arduinoespressif32",
+  "version": "3.2.0",
+  "description": "Arduino Wiring-based Framework for the Espressif ESP32, ESP32-P4, ESP32-S and ESP32-C series of SoCs",
+  "keywords": [
+    "framework",
+    "arduino",
+    "espressif",
+    "esp32"
+  ],
+  "license": "LGPL-2.1-or-later",
+  "repository": {
+    "type": "git",
     "url": "https://github.com/espressif/arduino-esp32"
-}
\ No newline at end of file
+  }
+}
diff --git a/package/package_esp32_index.template.json b/package/package_esp32_index.template.json
index fc5f095deef..19254d11682 100644
--- a/package/package_esp32_index.template.json
+++ b/package/package_esp32_index.template.json
@@ -23,128 +23,557 @@
           },
           "boards": [
             {
-              "name": "ESP32 Dev Module"
+              "name": "ESP32 Dev Board"
             },
             {
-              "name": "WEMOS LoLin32"
+              "name": "ESP32-C3 Dev Board"
             },
             {
-              "name": "WEMOS D1 MINI ESP32"
+              "name": "ESP32-C6 Dev Board"
+            },
+            {
+              "name": "ESP32-H2 Dev Board"
+            },
+            {
+              "name": "ESP32-P4 Dev Board"
+            },
+            {
+              "name": "ESP32-S2 Dev Board"
+            },
+            {
+              "name": "ESP32-S3 Dev Board"
+            },
+            {
+              "name": "Arduino Nano ESP32"
             }
           ],
           "toolsDependencies": [
             {
               "packager": "esp32",
-              "name": "xtensa-esp32-elf-gcc",
-              "version": "1.22.0-96-g2852398-5.2.0"
+              "name": "esp32-arduino-libs",
+              "version": "idf-release_v5.4-2f7dcd86-v1"
+            },
+            {
+              "packager": "esp32",
+              "name": "xtensa-esp-elf-gcc",
+              "version": "esp-14.2.0_20241119"
+            },
+            {
+              "packager": "esp32",
+              "name": "xtensa-esp-elf-gdb",
+              "version": "14.2_20240403"
+            },
+            {
+              "packager": "esp32",
+              "name": "riscv32-esp-elf-gcc",
+              "version": "esp-14.2.0_20241119"
+            },
+            {
+              "packager": "esp32",
+              "name": "riscv32-esp-elf-gdb",
+              "version": "14.2_20240403"
+            },
+            {
+              "packager": "esp32",
+              "name": "openocd-esp32",
+              "version": "v0.12.0-esp32-20241016"
             },
             {
               "packager": "esp32",
               "name": "esptool_py",
-              "version": "3.0.0"
+              "version": "4.9.dev3"
             },
             {
               "packager": "esp32",
               "name": "mkspiffs",
               "version": "0.2.3"
+            },
+            {
+              "packager": "esp32",
+              "name": "mklittlefs",
+              "version": "3.0.0-gnu12-dc7f933"
+            },
+            {
+              "packager": "arduino",
+              "name": "dfu-util",
+              "version": "0.11.0-arduino5"
             }
           ]
         }
       ],
       "tools": [
         {
-          "name": "xtensa-esp32-elf-gcc",
-          "version": "1.22.0-96-g2852398-5.2.0",
+          "name": "esp32-arduino-libs",
+          "version": "idf-release_v5.4-2f7dcd86-v1",
           "systems": [
             {
               "host": "i686-mingw32",
-              "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-win32-1.22.0-96-g2852398-5.2.0.zip",
-              "archiveFileName": "xtensa-esp32-elf-win32-1.22.0-96-g2852398-5.2.0.zip",
-              "checksum": "SHA-256:8e2a2e25d4714ae6e4b992be1b1c261caed5b523b0cc0887b6749229c9febbb0",
-              "size": "125810912"
+              "url": "https://github.com/espressif/esp32-arduino-lib-builder/releases/download/idf-release_v5.4/esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "archiveFileName": "esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "checksum": "SHA-256:11f1271fe5e2857155d90384690069e4d33f0f97a4c04e7474b29a7cbc7ededd",
+              "size": "352347498"
+            },
+            {
+              "host": "x86_64-mingw32",
+              "url": "https://github.com/espressif/esp32-arduino-lib-builder/releases/download/idf-release_v5.4/esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "archiveFileName": "esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "checksum": "SHA-256:11f1271fe5e2857155d90384690069e4d33f0f97a4c04e7474b29a7cbc7ededd",
+              "size": "352347498"
+            },
+            {
+              "host": "arm64-apple-darwin",
+              "url": "https://github.com/espressif/esp32-arduino-lib-builder/releases/download/idf-release_v5.4/esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "archiveFileName": "esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "checksum": "SHA-256:11f1271fe5e2857155d90384690069e4d33f0f97a4c04e7474b29a7cbc7ededd",
+              "size": "352347498"
             },
             {
               "host": "x86_64-apple-darwin",
-              "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-macos-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "archiveFileName": "xtensa-esp32-elf-macos-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "checksum": "SHA-256:6aeae9547f0cd7e442d1df21821cea8b15d0a6ce349bbd86466e2997b738a99c",
-              "size": "50520203"
+              "url": "https://github.com/espressif/esp32-arduino-lib-builder/releases/download/idf-release_v5.4/esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "archiveFileName": "esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "checksum": "SHA-256:11f1271fe5e2857155d90384690069e4d33f0f97a4c04e7474b29a7cbc7ededd",
+              "size": "352347498"
             },
             {
               "host": "x86_64-pc-linux-gnu",
-              "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-linux64-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "archiveFileName": "xtensa-esp32-elf-linux64-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "checksum": "SHA-256:798a8638f11ad37f41b9640582f869c61ffb4da6d932279fde94a2b636ad2dac",
-              "size": "44211883"
+              "url": "https://github.com/espressif/esp32-arduino-lib-builder/releases/download/idf-release_v5.4/esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "archiveFileName": "esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "checksum": "SHA-256:11f1271fe5e2857155d90384690069e4d33f0f97a4c04e7474b29a7cbc7ededd",
+              "size": "352347498"
             },
             {
               "host": "i686-pc-linux-gnu",
-              "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-linux32-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "archiveFileName": "xtensa-esp32-elf-linux32-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "checksum": "SHA-256:4eea601188aa8f3c3d45d7936ab4c0fabb75b4970dccf7a061de47dba49e377f",
-              "size": "45563578"
+              "url": "https://github.com/espressif/esp32-arduino-lib-builder/releases/download/idf-release_v5.4/esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "archiveFileName": "esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "checksum": "SHA-256:11f1271fe5e2857155d90384690069e4d33f0f97a4c04e7474b29a7cbc7ededd",
+              "size": "352347498"
+            },
+            {
+              "host": "aarch64-linux-gnu",
+              "url": "https://github.com/espressif/esp32-arduino-lib-builder/releases/download/idf-release_v5.4/esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "archiveFileName": "esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "checksum": "SHA-256:11f1271fe5e2857155d90384690069e4d33f0f97a4c04e7474b29a7cbc7ededd",
+              "size": "352347498"
             },
             {
               "host": "arm-linux-gnueabihf",
-              "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-linux-armel-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "archiveFileName": "xtensa-esp32-elf-linux-armel-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "checksum": "SHA-256:abfe06522f7c3479f6c7434c4bf926c50fa2039362b96abe95fa1f05ec519a9b",
-              "size": "50670980"
+              "url": "https://github.com/espressif/esp32-arduino-lib-builder/releases/download/idf-release_v5.4/esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "archiveFileName": "esp32-arduino-libs-idf-release_v5.4-2f7dcd86-v1.zip",
+              "checksum": "SHA-256:11f1271fe5e2857155d90384690069e4d33f0f97a4c04e7474b29a7cbc7ededd",
+              "size": "352347498"
+            }
+          ]
+        },
+        {
+          "name": "xtensa-esp-elf-gcc",
+          "version": "esp-14.2.0_20241119",
+          "systems": [
+            {
+              "host": "x86_64-pc-linux-gnu",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/xtensa-esp-elf-14.2.0_20241119-x86_64-linux-gnu.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-14.2.0_20241119-x86_64-linux-gnu.tar.gz",
+              "checksum": "SHA-256:b1859df334a85541ae746e1b86439f59180d87f8cf1cc04c2e770fadf9f006e9",
+              "size": "323678089"
             },
             {
               "host": "aarch64-linux-gnu",
-              "url": "https://dl.espressif.com/dl/xtensa-esp32-elf-linux-armel-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "archiveFileName": "xtensa-esp32-elf-linux-armel-1.22.0-96-g2852398-5.2.0.tar.gz",
-              "checksum": "SHA-256:abfe06522f7c3479f6c7434c4bf926c50fa2039362b96abe95fa1f05ec519a9b",
-              "size": "50670980"
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/xtensa-esp-elf-14.2.0_20241119-aarch64-linux-gnu.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-14.2.0_20241119-aarch64-linux-gnu.tar.gz",
+              "checksum": "SHA-256:7ff023033a5c00e55b9fc0a0b26d18fb0e476c24e24c5b0459bcb2e05a3729f1",
+              "size": "320064691"
+            },
+            {
+              "host": "arm-linux-gnueabihf",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/xtensa-esp-elf-14.2.0_20241119-arm-linux-gnueabi.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-14.2.0_20241119-arm-linux-gnueabi.tar.gz",
+              "checksum": "SHA-256:bb11dbf3ed25d4e0cc9e938749519e8236cfa2609e85742d311f1d869111805a",
+              "size": "319454139"
+            },
+            {
+              "host": "i686-pc-linux-gnu",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/xtensa-esp-elf-14.2.0_20241119-i586-linux-gnu.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-14.2.0_20241119-i586-linux-gnu.tar.gz",
+              "checksum": "SHA-256:5ac611dca62ec791d413d1f417d566c444b006d2a4f97bd749b15f782d87249b",
+              "size": "328335914"
+            },
+            {
+              "host": "x86_64-apple-darwin",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/xtensa-esp-elf-14.2.0_20241119-x86_64-apple-darwin_signed.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-14.2.0_20241119-x86_64-apple-darwin_signed.tar.gz",
+              "checksum": "SHA-256:15b3e60362028eaeff9156dc82dac3f1436b4aeef3920b28d7650974d8c34751",
+              "size": "336215844"
+            },
+            {
+              "host": "arm64-apple-darwin",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/xtensa-esp-elf-14.2.0_20241119-aarch64-apple-darwin_signed.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-14.2.0_20241119-aarch64-apple-darwin_signed.tar.gz",
+              "checksum": "SHA-256:45c475518735133789bacccad31f872318b7ecc0b31cc9b7924aad880034f0bf",
+              "size": "318797396"
+            },
+            {
+              "host": "i686-mingw32",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/xtensa-esp-elf-14.2.0_20241119-i686-w64-mingw32.zip",
+              "archiveFileName": "xtensa-esp-elf-14.2.0_20241119-i686-w64-mingw32.zip",
+              "checksum": "SHA-256:b30e450e0af279783c54a9ae77c3b367dd556b78eda930a92ec7b784a74c28c8",
+              "size": "382457717"
+            },
+            {
+              "host": "x86_64-mingw32",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/xtensa-esp-elf-14.2.0_20241119-x86_64-w64-mingw32.zip",
+              "archiveFileName": "xtensa-esp-elf-14.2.0_20241119-x86_64-w64-mingw32.zip",
+              "checksum": "SHA-256:62ae704777d73c30689efff6e81178632a1ca44d1a2d60f4621eb997e040e028",
+              "size": "386316009"
             }
           ]
         },
         {
-          "name": "esptool_py",
-          "version": "3.0.0",
+          "name": "xtensa-esp-elf-gdb",
+          "version": "14.2_20240403",
           "systems": [
+            {
+              "host": "x86_64-pc-linux-gnu",
+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/xtensa-esp-elf-gdb-14.2_20240403-x86_64-linux-gnu.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-gdb-14.2_20240403-x86_64-linux-gnu.tar.gz",
+              "checksum": "SHA-256:9d68472d4cba5cf8c2b79d94f86f92c828e76a632bd1e6be5e7706e5b304d36e",
+              "size": "31010320"
+            },
+            {
+              "host": "aarch64-linux-gnu",
+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/xtensa-esp-elf-gdb-14.2_20240403-aarch64-linux-gnu.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-gdb-14.2_20240403-aarch64-linux-gnu.tar.gz",
+              "checksum": "SHA-256:bdabc3217994815fc311c4e16e588b78f6596b5ad4ffa46c80b40e982cfb1e66",
+              "size": "30954580"
+            },
+            {
+              "host": "arm-linux-gnueabihf",
+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/xtensa-esp-elf-gdb-14.2_20240403-arm-linux-gnueabi.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-gdb-14.2_20240403-arm-linux-gnueabi.tar.gz",
+              "checksum": "SHA-256:d54b8d703ba897b28c627da3d27106a3906dd01ba298778a67064710bc33c76d",
+              "size": "28697281"
+            },
+            {
+              "host": "i686-pc-linux-gnu",
+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/xtensa-esp-elf-gdb-14.2_20240403-i586-linux-gnu.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-gdb-14.2_20240403-i586-linux-gnu.tar.gz",
+              "checksum": "SHA-256:64d3bc992ed8fdec383d49e8b803ac494605a38117c8293db8da055037de96b0",
+              "size": "29890994"
+            },
+            {
+              "host": "x86_64-apple-darwin",
+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/xtensa-esp-elf-gdb-14.2_20240403-x86_64-apple-darwin14.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-gdb-14.2_20240403-x86_64-apple-darwin14.tar.gz",
+              "checksum": "SHA-256:023e74b3fda793da4bc0509b02de776ee0dad6efaaac17bef5916fb7dc9c26b9",
+              "size": "44446611"
+            },
+            {
+              "host": "arm64-apple-darwin",
+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/xtensa-esp-elf-gdb-14.2_20240403-aarch64-apple-darwin21.1.tar.gz",
+              "archiveFileName": "xtensa-esp-elf-gdb-14.2_20240403-aarch64-apple-darwin21.1.tar.gz",
+              "checksum": "SHA-256:ea757c6bf8c25238f6d2fdcc6bbab25a1b00608a0f9e19b7ddd2f37ddbdc3fb1",
+              "size": "37021423"
+            },
             {
               "host": "i686-mingw32",
-              "url": "https://dl.espressif.com/dl/esptool-3.0.0.2-windows.zip",
-              "archiveFileName": "esptool-3.0.0.2-windows.zip",
-              "checksum": "SHA-256:b192bfc1545a3c92658ce586b4edcc2aca3f0ad4b3fa8417d658bc8a48f1387e",
-              "size": "3434736"
+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/xtensa-esp-elf-gdb-14.2_20240403-i686-w64-mingw32.zip",
+              "archiveFileName": "xtensa-esp-elf-gdb-14.2_20240403-i686-w64-mingw32.zip",
+              "checksum": "SHA-256:322e8d9b700dc32d8158e3dc55fb85ec55de48d0bb7789375ee39a28d5d655e2",
+              "size": "26302466"
+            },
+            {
+              "host": "x86_64-mingw32",
+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/xtensa-esp-elf-gdb-14.2_20240403-x86_64-w64-mingw32.zip",
+              "archiveFileName": "xtensa-esp-elf-gdb-14.2_20240403-x86_64-w64-mingw32.zip",
+              "checksum": "SHA-256:a27a2fe20f192f8e0a51b8936428b4e1cf8935cfe008ee445cc49f6fc7f6db2e",
+              "size": "28366035"
+            }
+          ]
+        },
+        {
+          "name": "riscv32-esp-elf-gcc",
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+            {
+              "host": "x86_64-pc-linux-gnu",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/riscv32-esp-elf-14.2.0_20241119-x86_64-linux-gnu.tar.gz",
+              "archiveFileName": "riscv32-esp-elf-14.2.0_20241119-x86_64-linux-gnu.tar.gz",
+              "checksum": "SHA-256:a16942465d33c7f0334c16e83bc6feb62e06eeb79cf19099293480bb8d48c0cd",
+              "size": "593721156"
+            },
+            {
+              "host": "aarch64-linux-gnu",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/riscv32-esp-elf-14.2.0_20241119-aarch64-linux-gnu.tar.gz",
+              "archiveFileName": "riscv32-esp-elf-14.2.0_20241119-aarch64-linux-gnu.tar.gz",
+              "checksum": "SHA-256:22486233d0e0fd58a54ae453b701f195f1432fc6f2e17085b9d6c8d5d9acefb7",
+              "size": "587879927"
+            },
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+              "host": "arm-linux-gnueabihf",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/riscv32-esp-elf-14.2.0_20241119-arm-linux-gnueabi.tar.gz",
+              "archiveFileName": "riscv32-esp-elf-14.2.0_20241119-arm-linux-gnueabi.tar.gz",
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+              "size": "586531522"
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+            {
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+              "archiveFileName": "riscv32-esp-elf-14.2.0_20241119-i586-linux-gnu.tar.gz",
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             {
               "host": "x86_64-apple-darwin",
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-              "archiveFileName": "esptool-3.0.0.2-macos.tar.gz",
-              "checksum": "SHA-256:9213f46d5aa865558da4a2ef4218e87eef4782779128083c15ce2b3e4d07a1ea",
-              "size": "3849615"
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+              "archiveFileName": "riscv32-esp-elf-14.2.0_20241119-x86_64-apple-darwin_signed.tar.gz",
+              "checksum": "SHA-256:5f8b571e1aedbe9f856f3bdeca6600cd5510ccff1ca102c4f001421eda560585",
+              "size": "602343061"
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+            {
+              "host": "arm64-apple-darwin",
+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/riscv32-esp-elf-14.2.0_20241119-aarch64-apple-darwin_signed.tar.gz",
+              "archiveFileName": "riscv32-esp-elf-14.2.0_20241119-aarch64-apple-darwin_signed.tar.gz",
+              "checksum": "SHA-256:a7276042a7eb2d33c2dff7167539e445c32c07d43a2c6827e86d035642503e0b",
+              "size": "578521565"
             },
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+              "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-14.2.0_20241119/riscv32-esp-elf-14.2.0_20241119-i686-w64-mingw32.zip",
+              "archiveFileName": "riscv32-esp-elf-14.2.0_20241119-i686-w64-mingw32.zip",
+              "checksum": "SHA-256:54193a97bd75205678ead8d11f00b351cfa3c2a6e5ab5d966341358b9f9422d7",
+              "size": "672055172"
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+            {
+              "host": "x86_64-mingw32",
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+              "archiveFileName": "riscv32-esp-elf-14.2.0_20241119-x86_64-w64-mingw32.zip",
+              "checksum": "SHA-256:24c8407fa467448d394e0639436a5ede31caf1838e35e8435e19df58ebed438c",
+              "size": "677812937"
+            }
+          ]
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+        {
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             {
               "host": "x86_64-pc-linux-gnu",
-              "url": "https://dl.espressif.com/dl/esptool-3.0.0.2-linux.tar.gz",
-              "archiveFileName": "esptool-3.0.0.2-linux.tar.gz",
-              "checksum": "SHA-256:d5cb51da1c74ff69f81b820470d2ecccb5c7c3a2dec7776483d4c89588b00020",
-              "size": "57526"
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+              "archiveFileName": "riscv32-esp-elf-gdb-14.2_20240403-x86_64-linux-gnu.tar.gz",
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+              "archiveFileName": "riscv32-esp-elf-gdb-14.2_20240403-aarch64-linux-gnu.tar.gz",
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+              "archiveFileName": "riscv32-esp-elf-gdb-14.2_20240403-arm-linux-gnueabi.tar.gz",
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-              "archiveFileName": "esptool-3.0.0.2-linux.tar.gz",
-              "checksum": "SHA-256:d5cb51da1c74ff69f81b820470d2ecccb5c7c3a2dec7776483d4c89588b00020",
-              "size": "57526"
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+              "archiveFileName": "riscv32-esp-elf-gdb-14.2_20240403-i586-linux-gnu.tar.gz",
+              "checksum": "SHA-256:0e628ee37438ab6ba05eb889a76d09e50cb98e0020a16b8e2b935c5cf19b4ed2",
+              "size": "29947521"
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+            {
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+              "archiveFileName": "riscv32-esp-elf-gdb-14.2_20240403-x86_64-apple-darwin14.tar.gz",
+              "checksum": "SHA-256:8f6bda832d70dad5860a639d55aba4237bd10cbac9f4822db1eece97357b34a9",
+              "size": "44196117"
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+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/riscv32-esp-elf-gdb-14.2_20240403-aarch64-apple-darwin21.1.tar.gz",
+              "archiveFileName": "riscv32-esp-elf-gdb-14.2_20240403-aarch64-apple-darwin21.1.tar.gz",
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+              "size": "36794404"
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+              "host": "i686-mingw32",
+              "url": "https://github.com/espressif/binutils-gdb/releases/download/esp-gdb-v14.2_20240403/riscv32-esp-elf-gdb-14.2_20240403-i686-w64-mingw32.zip",
+              "archiveFileName": "riscv32-esp-elf-gdb-14.2_20240403-i686-w64-mingw32.zip",
+              "checksum": "SHA-256:d6e7ce05805b0d8d4dd138ad239b98a1adf8da98941867d60760eb1ae5361730",
+              "size": "26486295"
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+            {
+              "host": "x86_64-mingw32",
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+              "archiveFileName": "riscv32-esp-elf-gdb-14.2_20240403-x86_64-w64-mingw32.zip",
+              "checksum": "SHA-256:5c9f211dc46daf6b96fad09d709284a0f0186fef8947d9f6edd6bca5b5ad4317",
+              "size": "27942579"
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+        },
+        {
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+          "systems": [
+            {
+              "host": "x86_64-pc-linux-gnu",
+              "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-linux-amd64-0.12.0-esp32-20241016.tar.gz",
+              "archiveFileName": "openocd-esp32-linux-amd64-0.12.0-esp32-20241016.tar.gz",
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+              "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-linux-arm64-0.12.0-esp32-20241016.tar.gz",
+              "archiveFileName": "openocd-esp32-linux-arm64-0.12.0-esp32-20241016.tar.gz",
+              "checksum": "SHA-256:8f8daf5bd22ec5d2fa9257b0862ec33da18ee677e023fb9a9eb17f74ce208c76",
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-              "url": "https://dl.espressif.com/dl/esptool-3.0.0.2-linux.tar.gz",
-              "archiveFileName": "esptool-3.0.0.2-linux.tar.gz",
-              "checksum": "SHA-256:d5cb51da1c74ff69f81b820470d2ecccb5c7c3a2dec7776483d4c89588b00020",
-              "size": "57526"
+              "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-linux-armel-0.12.0-esp32-20241016.tar.gz",
+              "archiveFileName": "openocd-esp32-linux-armel-0.12.0-esp32-20241016.tar.gz",
+              "checksum": "SHA-256:bc9c020ecf20e2000f76cffa44305fd5bc44d2e688ea78cce423399d33f19767",
+              "size": "2414206"
+            },
+            {
+              "host": "x86_64-apple-darwin",
+              "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-macos-0.12.0-esp32-20241016.tar.gz",
+              "archiveFileName": "openocd-esp32-macos-0.12.0-esp32-20241016.tar.gz",
+              "checksum": "SHA-256:02a2dffe801a2d005fa9e614d80ff8173395b2cb0b5d3118d0229d094a9946a7",
+              "size": "2508089"
+            },
+            {
+              "host": "arm64-apple-darwin",
+              "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-macos-arm64-0.12.0-esp32-20241016.tar.gz",
+              "archiveFileName": "openocd-esp32-macos-arm64-0.12.0-esp32-20241016.tar.gz",
+              "checksum": "SHA-256:c382f9e884d6565cb6089bff5f200f4810994667d885f062c3d3c5625a0fa9d6",
+              "size": "2552569"
+            },
+            {
+              "host": "i686-mingw32",
+              "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-win32-0.12.0-esp32-20241016.zip",
+              "archiveFileName": "openocd-esp32-win32-0.12.0-esp32-20241016.zip",
+              "checksum": "SHA-256:3b5d615e0a72cc771a45dd469031312d5881c01d7b6bc9edb29b8b6bda8c2e90",
+              "size": "2946244"
             },
+            {
+              "host": "x86_64-mingw32",
+              "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-win64-0.12.0-esp32-20241016.zip",
+              "archiveFileName": "openocd-esp32-win64-0.12.0-esp32-20241016.zip",
+              "checksum": "SHA-256:5e7b2fd1947d3a8625f6a11db7a2340cf2f41ff4c61284c022c7d7c32b18780a",
+              "size": "2946244"
+            }
+          ]
+        },
+        {
+          "name": "esptool_py",
+          "version": "4.9.dev3",
+          "systems": [
+            {
+              "host": "x86_64-pc-linux-gnu",
+              "url": "https://github.com/espressif/arduino-esp32/releases/download/3.1.0-RC3/esptool-v4.9.dev3-linux-amd64.tar.gz",
+              "archiveFileName": "esptool-v4.9.dev3-linux-amd64.tar.gz",
+              "checksum": "SHA-256:4ecaf51836cbf4ea3c19840018bfef3b0b8cd8fc3c95f6e1e043ca5bbeab9bf0",
+              "size": "64958202"
+            },
+            {
+              "host": "arm-linux-gnueabihf",
+              "url": "https://github.com/espressif/arduino-esp32/releases/download/3.1.0-RC3/esptool-v4.9.dev3-linux-armv7.tar.gz",
+              "archiveFileName": "esptool-v4.9.dev3-linux-armv7.tar.gz",
+              "checksum": "SHA-256:fff818573bce483ee793ac83c8211f6abf764aa3350f198228859f696a0a0b36",
+              "size": "31530030"
+            },
+            {
+              "host": "aarch64-linux-gnu",
+              "url": "https://github.com/espressif/arduino-esp32/releases/download/3.1.0-RC3/esptool-v4.9.dev3-linux-aarch64.tar.gz",
+              "archiveFileName": "esptool-v4.9.dev3-linux-aarch64.tar.gz",
+              "checksum": "SHA-256:5b274bdff2f62e6a07c3c1dfa51b1128924621f661747eca3dbe0f77972f2f06",
+              "size": "33663882"
+            },
+            {
+              "host": "x86_64-apple-darwin",
+              "url": "https://github.com/espressif/arduino-esp32/releases/download/3.1.0-RC3/esptool-v4.9.dev3-macos-amd64.tar.gz",
+              "archiveFileName": "esptool-v4.9.dev3-macos-amd64.tar.gz",
+              "checksum": "SHA-256:c733c83b58fcf5f642fbb2fddb8ff24640c2c785126cba0821fb70c4a5ceea7a",
+              "size": "32767836"
+            },
+            {
+              "host": "arm64-apple-darwin",
+              "url": "https://github.com/espressif/arduino-esp32/releases/download/3.1.0-RC3/esptool-v4.9.dev3-macos-arm64.tar.gz",
+              "archiveFileName": "esptool-v4.9.dev3-macos-arm64.tar.gz",
+              "checksum": "SHA-256:83c195a15981e6a5e7a130db2ccfb21e2d8093912e5b003681f9a5abadd71af7",
+              "size": "30121441"
+            },
+            {
+              "host": "i686-mingw32",
+              "url": "https://github.com/espressif/arduino-esp32/releases/download/3.1.0-RC3/esptool-v4.9.dev3-win64.zip",
+              "archiveFileName": "esptool-v4.9.dev3-win64.zip",
+              "checksum": "SHA-256:890051a4fdc684ff6f4af18d0bb27d274ca940ee0eef716a9455f8c64b25b215",
+              "size": "36072564"
+            },
+            {
+              "host": "x86_64-mingw32",
+              "url": "https://github.com/espressif/arduino-esp32/releases/download/3.1.0-RC3/esptool-v4.9.dev3-win64.zip",
+              "archiveFileName": "esptool-v4.9.dev3-win64.zip",
+              "checksum": "SHA-256:890051a4fdc684ff6f4af18d0bb27d274ca940ee0eef716a9455f8c64b25b215",
+              "size": "36072564"
+            }
+          ]
+        },
+        {
+          "version": "3.0.0-gnu12-dc7f933",
+          "name": "mklittlefs",
+          "systems": [
             {
               "host": "aarch64-linux-gnu",
-              "url": "https://dl.espressif.com/dl/esptool-3.0.0.2-linux.tar.gz",
-              "archiveFileName": "esptool-3.0.0.2-linux.tar.gz",
-              "checksum": "SHA-256:d5cb51da1c74ff69f81b820470d2ecccb5c7c3a2dec7776483d4c89588b00020",
-              "size": "57526"
+              "url": "https://github.com/earlephilhower/esp-quick-toolchain/releases/download/3.0.0-gnu12/aarch64-linux-gnu.mklittlefs-c41e51a.200706.tar.gz",
+              "archiveFileName": "aarch64-linux-gnu.mklittlefs-c41e51a.200706.tar.gz",
+              "checksum": "SHA-256:fc56e389383749e4cf4fab0fcf75cc0ebc41e59383caf6c2eff1c3d9794af200",
+              "size": "44651"
+            },
+            {
+              "host": "arm-linux-gnueabihf",
+              "url": "https://github.com/earlephilhower/esp-quick-toolchain/releases/download/3.0.0-gnu12/arm-linux-gnueabihf.mklittlefs-c41e51a.200706.tar.gz",
+              "archiveFileName": "arm-linux-gnueabihf.mklittlefs-c41e51a.200706.tar.gz",
+              "checksum": "SHA-256:52b642dd0545eb3bd8dfb75dde6601df21700e4867763fd2696274be279294c5",
+              "size": "37211"
+            },
+            {
+              "host": "i686-pc-linux-gnu",
+              "url": "https://github.com/earlephilhower/esp-quick-toolchain/releases/download/3.0.0-gnu12/i686-linux-gnu.mklittlefs-c41e51a.200706.tar.gz",
+              "archiveFileName": "i686-linux-gnu.mklittlefs-c41e51a.200706.tar.gz",
+              "checksum": "SHA-256:7886051d8ccc54aed0af2e7cdf6ff992bb51638df86f3b545955697720b6d062",
+              "size": "48033"
+            },
+            {
+              "host": "i686-mingw32",
+              "url": "https://github.com/earlephilhower/esp-quick-toolchain/releases/download/3.0.0-gnu12/i686-w64-mingw32.mklittlefs-c41e51a.200706.zip",
+              "archiveFileName": "i686-w64-mingw32.mklittlefs-c41e51a.200706.zip",
+              "checksum": "SHA-256:43740db30ce451454f2337331f10ab4ed41bd83dbf0fa0cb4387107388b59f42",
+              "size": "332655"
+            },
+            {
+              "host": "x86_64-apple-darwin",
+              "url": "https://github.com/earlephilhower/esp-quick-toolchain/releases/download/3.0.0-gnu12/x86_64-apple-darwin14.mklittlefs-c41e51a.200706.tar.gz",
+              "archiveFileName": "x86_64-apple-darwin14.mklittlefs-c41e51a.200706.tar.gz",
+              "checksum": "SHA-256:e3edd5e05b70db3c7df6b9d626558348ad04804022fe955c799aeb51808c7dc3",
+              "size": "362608"
+            },
+            {
+              "host": "x86_64-pc-linux-gnu",
+              "url": "https://github.com/earlephilhower/esp-quick-toolchain/releases/download/3.0.0-gnu12/x86_64-linux-gnu.mklittlefs-c41e51a.200706.tar.gz",
+              "archiveFileName": "x86_64-linux-gnu.mklittlefs-c41e51a.200706.tar.gz",
+              "checksum": "SHA-256:66e84dda0aad747517da3785125e05738a540948aab2b7eaa02855167a1eea53",
+              "size": "46778"
+            },
+            {
+              "host": "x86_64-mingw32",
+              "url": "https://github.com/earlephilhower/esp-quick-toolchain/releases/download/3.0.0-gnu12/x86_64-w64-mingw32.mklittlefs-c41e51a.200706.zip",
+              "archiveFileName": "x86_64-w64-mingw32.mklittlefs-c41e51a.200706.zip",
+              "checksum": "SHA-256:2e319077491f8e832e96eb4f2f7a70dd919333cee4b388c394e0e848d031d542",
+              "size": "345132"
             }
           ]
         },
@@ -193,6 +622,13 @@
               "archiveFileName": "mkspiffs-0.2.3-arduino-esp32-linux-armhf.tar.gz",
               "checksum": "SHA-256:ade3dc00117912ac08a1bdbfbfe76b12d21a34bc5fa1de0cfc45fe7a8d0a0185",
               "size": "40665"
+            },
+            {
+              "host": "aarch64-linux-gnu",
+              "url": "https://github.com/igrr/mkspiffs/releases/download/0.2.3/mkspiffs-0.2.3-arduino-esp32-linux-armhf.tar.gz",
+              "archiveFileName": "mkspiffs-0.2.3-arduino-esp32-linux-armhf.tar.gz",
+              "checksum": "SHA-256:ade3dc00117912ac08a1bdbfbfe76b12d21a34bc5fa1de0cfc45fe7a8d0a0185",
+              "size": "40665"
             }
           ]
         }
diff --git a/platform.txt b/platform.txt
index 3677e1ee4bd..65be05b3bf4 100644
--- a/platform.txt
+++ b/platform.txt
@@ -1,97 +1,183 @@
 name=ESP32 Arduino
-version=0.0.1
+version=3.2.0
 
-runtime.tools.xtensa-esp32-elf-gcc.path={runtime.platform.path}/tools/xtensa-esp32-elf
+tools.esp32-arduino-libs.path={runtime.platform.path}/tools/esp32-arduino-libs
+tools.esp32-arduino-libs.path.windows={runtime.platform.path}\tools\esp32-arduino-libs
+tools.xtensa-esp-elf-gcc.path={runtime.platform.path}/tools/xtensa-esp-elf
+tools.xtensa-esp-elf-gdb.path={runtime.platform.path}/tools/xtensa-esp-elf-gdb
+tools.riscv32-esp-elf-gcc.path={runtime.platform.path}/tools/riscv32-esp-elf
+tools.riscv32-esp-elf-gdb.path={runtime.platform.path}/tools/riscv32-esp-elf-gdb
 
 tools.esptool_py.path={runtime.platform.path}/tools/esptool
 tools.esptool_py.cmd=esptool
-tools.esptool_py.cmd.linux=esptool.py
 tools.esptool_py.cmd.windows=esptool.exe
 
-tools.esptool_py.network_cmd=python "{runtime.platform.path}/tools/espota.py"
-tools.esptool_py.network_cmd.windows="{runtime.platform.path}/tools/espota.exe"
+tools.esptool_py.network_cmd=python3 "{runtime.platform.path}/tools/espota.py" -r
+tools.esptool_py.network_cmd.windows="{runtime.platform.path}\tools\espota.exe" -r
 
-tools.gen_esp32part.cmd=python "{runtime.platform.path}/tools/gen_esp32part.py"
-tools.gen_esp32part.cmd.windows="{runtime.platform.path}/tools/gen_esp32part.exe"
+tools.esp_ota.cmd=python3 "{runtime.platform.path}/tools/espota.py" -r
+tools.esp_ota.cmd.windows="{runtime.platform.path}\tools\espota.exe" -r
 
-compiler.warning_flags=-w
-compiler.warning_flags.none=-w
-compiler.warning_flags.default=
-compiler.warning_flags.more=-Wall -Werror=all
-compiler.warning_flags.all=-Wall -Werror=all -Wextra
+tools.gen_esp32part.cmd=python3 "{runtime.platform.path}/tools/gen_esp32part.py"
+tools.gen_esp32part.cmd.windows="{runtime.platform.path}\tools\gen_esp32part.exe"
 
-compiler.path={runtime.tools.xtensa-esp32-elf-gcc.path}/bin/
-compiler.sdk.path={runtime.platform.path}/tools/sdk
-compiler.cpreprocessor.flags=-DESP_PLATFORM -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DHAVE_CONFIG_H -DGCC_NOT_5_2_0=0 -DWITH_POSIX "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/app_trace" "-I{compiler.sdk.path}/include/app_update" "-I{compiler.sdk.path}/include/asio" "-I{compiler.sdk.path}/include/bootloader_support" "-I{compiler.sdk.path}/include/bt" "-I{compiler.sdk.path}/include/coap" "-I{compiler.sdk.path}/include/console" "-I{compiler.sdk.path}/include/driver" "-I{compiler.sdk.path}/include/efuse" "-I{compiler.sdk.path}/include/esp-tls" "-I{compiler.sdk.path}/include/esp32" "-I{compiler.sdk.path}/include/esp_adc_cal" "-I{compiler.sdk.path}/include/esp_event" "-I{compiler.sdk.path}/include/esp_http_client" "-I{compiler.sdk.path}/include/esp_http_server" "-I{compiler.sdk.path}/include/esp_https_ota" "-I{compiler.sdk.path}/include/esp_https_server" "-I{compiler.sdk.path}/include/esp_ringbuf" "-I{compiler.sdk.path}/include/esp_websocket_client" "-I{compiler.sdk.path}/include/espcoredump" "-I{compiler.sdk.path}/include/ethernet" "-I{compiler.sdk.path}/include/expat" "-I{compiler.sdk.path}/include/fatfs" "-I{compiler.sdk.path}/include/freemodbus" "-I{compiler.sdk.path}/include/freertos" "-I{compiler.sdk.path}/include/heap" "-I{compiler.sdk.path}/include/idf_test" "-I{compiler.sdk.path}/include/jsmn" "-I{compiler.sdk.path}/include/json" "-I{compiler.sdk.path}/include/libsodium" "-I{compiler.sdk.path}/include/log" "-I{compiler.sdk.path}/include/lwip" "-I{compiler.sdk.path}/include/mbedtls" "-I{compiler.sdk.path}/include/mdns" "-I{compiler.sdk.path}/include/micro-ecc" "-I{compiler.sdk.path}/include/mqtt" "-I{compiler.sdk.path}/include/newlib" "-I{compiler.sdk.path}/include/nghttp" "-I{compiler.sdk.path}/include/nimble" "-I{compiler.sdk.path}/include/nvs_flash" "-I{compiler.sdk.path}/include/openssl" "-I{compiler.sdk.path}/include/protobuf-c" "-I{compiler.sdk.path}/include/protocomm" "-I{compiler.sdk.path}/include/pthread" "-I{compiler.sdk.path}/include/sdmmc" "-I{compiler.sdk.path}/include/smartconfig_ack" "-I{compiler.sdk.path}/include/soc" "-I{compiler.sdk.path}/include/spi_flash" "-I{compiler.sdk.path}/include/spiffs" "-I{compiler.sdk.path}/include/tcp_transport" "-I{compiler.sdk.path}/include/tcpip_adapter" "-I{compiler.sdk.path}/include/ulp" "-I{compiler.sdk.path}/include/unity" "-I{compiler.sdk.path}/include/vfs" "-I{compiler.sdk.path}/include/wear_levelling" "-I{compiler.sdk.path}/include/wifi_provisioning" "-I{compiler.sdk.path}/include/wpa_supplicant" "-I{compiler.sdk.path}/include/xtensa-debug-module" "-I{compiler.sdk.path}/include/esp-face" "-I{compiler.sdk.path}/include/esp32-camera" "-I{compiler.sdk.path}/include/esp-face" "-I{compiler.sdk.path}/include/fb_gfx"
+tools.gen_insights_pkg.cmd=python3 "{runtime.platform.path}"/tools/gen_insights_package.py
+tools.gen_insights_pkg.cmd.windows="{runtime.platform.path}\tools\gen_insights_package.exe"
 
-compiler.c.cmd=xtensa-esp32-elf-gcc
-compiler.c.flags=-std=gnu99 -Os -g3 -fstack-protector -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib -Wpointer-arith {compiler.warning_flags} -Wno-maybe-uninitialized -Wno-unused-function -Wno-unused-but-set-variable -Wno-unused-variable -Wno-deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -Wno-old-style-declaration -MMD -c
+compiler.path={tools.{build.tarch}-esp-elf-gcc.path}/bin/
+compiler.prefix={build.tarch}-{build.target}-elf-
 
-compiler.cpp.cmd=xtensa-esp32-elf-g++
-compiler.cpp.flags=-std=gnu++11 -Os -g3 -Wpointer-arith -fexceptions -fstack-protector -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib {compiler.warning_flags} -Wno-error=maybe-uninitialized -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-unused-but-set-parameter -Wno-missing-field-initializers -Wno-sign-compare -fno-rtti -MMD -c
+compiler.sdk.path={tools.esp32-arduino-libs.path}/{build.mcu}
+compiler.sdk.path.windows={tools.esp32-arduino-libs.path}\{build.mcu}
 
-compiler.S.cmd=xtensa-esp32-elf-gcc
-compiler.S.flags=-c -g3 -x assembler-with-cpp -MMD -mlongcalls
+# EXPERIMENTAL feature: optimization flags
+#  - this is alpha and may be subject to change without notice
+compiler.optimization_flags=-Os
+compiler.optimization_flags.release=-Os
+compiler.optimization_flags.debug=-Og -g3
 
-compiler.c.elf.cmd=xtensa-esp32-elf-gcc
-compiler.c.elf.flags=-nostdlib "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" -T esp32_out.ld -T esp32.project.ld -T esp32.rom.ld -T esp32.peripherals.ld -T esp32.rom.libgcc.ld -T esp32.rom.spiram_incompatible_fns.ld -u ld_include_panic_highint_hdl -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static -Wl,--undefined=uxTopUsedPriority  -u __cxa_guard_dummy -u __cxx_fatal_exception
-compiler.c.elf.libs=-lgcc -lopenssl -lbtdm_app -lfatfs -lwps -lcoexist -lwear_levelling -lesp_http_client -lprotobuf-c -lhal -lnewlib -ldriver -lbootloader_support -lpp -lfreemodbus -lmesh -lsmartconfig -ljsmn -lwpa -lethernet -lphy -lapp_trace -lconsole -lulp -lwpa_supplicant -lfreertos -lbt -lmicro-ecc -lesp32-camera -lcxx -lxtensa-debug-module -ltcp_transport -lod -lmdns -ldetection -lvfs -lpe -lesp_websocket_client -lespcoredump -lesp_ringbuf -lsoc -lcore -lfb_gfx -lsdmmc -llibsodium -lcoap -ltcpip_adapter -lprotocomm -lesp_event -limage_util -lc_nano -lesp-tls -lasio -lrtc -lspi_flash -lwpa2 -lwifi_provisioning -lesp32 -lface_recognition -lapp_update -lnghttp -ldl -lspiffs -lface_detection -lefuse -lunity -lesp_https_server -lespnow -lnvs_flash -lesp_adc_cal -llog -ldetection_cat_face -lsmartconfig_ack -lexpat -lm -lfr -lmqtt -lc -lheap -lmbedtls -llwip -lnet80211 -lesp_http_server -lpthread -ljson -lesp_https_ota -lfd  -lstdc++
+# Arduino Compile Warning Levels
+compiler.warning_flags=-w
+compiler.warning_flags.none=-w
+compiler.warning_flags.default=
+compiler.warning_flags.more=-Wall
+compiler.warning_flags.all=-Wall -Wextra
 
-compiler.as.cmd=xtensa-esp32-elf-as
+# Additional flags specific to Arduino (not based on IDF flags).
+# Update tools/pioarduino-build.py when changing these flags.
+compiler.common_werror_flags=-Werror=return-type
 
-compiler.ar.cmd=xtensa-esp32-elf-ar
-compiler.ar.flags=cru
+# Compile Flags
+compiler.cpreprocessor.flags="@{compiler.sdk.path}/flags/defines" "-I{build.source.path}" -iprefix "{compiler.sdk.path}/include/" "@{compiler.sdk.path}/flags/includes" "-I{compiler.sdk.path}/{build.memory_type}/include"
+compiler.c.flags=-MMD -c "@{compiler.sdk.path}/flags/c_flags" {compiler.warning_flags} {compiler.optimization_flags} {compiler.common_werror_flags}
+compiler.cpp.flags=-MMD -c "@{compiler.sdk.path}/flags/cpp_flags" {compiler.warning_flags} {compiler.optimization_flags} {compiler.common_werror_flags}
+compiler.S.flags=-MMD -c -x assembler-with-cpp "@{compiler.sdk.path}/flags/S_flags" {compiler.warning_flags} {compiler.optimization_flags}
+compiler.c.elf.flags="-Wl,--Map={build.path}/{build.project_name}.map" "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" "-L{compiler.sdk.path}/{build.memory_type}" "-Wl,--wrap=esp_panic_handler" "@{compiler.sdk.path}/flags/ld_flags" "@{compiler.sdk.path}/flags/ld_scripts"
+compiler.c.elf.libs="@{compiler.sdk.path}/flags/ld_libs"
+compiler.ar.flags=cr
 
-compiler.size.cmd=xtensa-esp32-elf-size
+# Compilers
+compiler.c.cmd={compiler.prefix}gcc
+compiler.cpp.cmd={compiler.prefix}g++
+compiler.S.cmd={compiler.prefix}gcc
+compiler.c.elf.cmd={compiler.prefix}g++
+compiler.as.cmd={compiler.prefix}as
+compiler.ar.cmd={compiler.prefix}gcc-ar
+compiler.size.cmd={compiler.prefix}size
 
+# These can be overridden in platform.local.txt
+compiler.c.extra_flags=
+compiler.cpp.extra_flags=
+compiler.S.extra_flags=
+compiler.c.elf.extra_flags=
+compiler.ar.extra_flags=
+compiler.objcopy.eep.extra_flags=
+compiler.elf2hex.extra_flags=
 compiler.libraries.ldflags=
 
+# Target dependent definitions
+build.extra_flags.esp32=-DARDUINO_USB_CDC_ON_BOOT=0
+build.extra_flags.esp32s3=-DARDUINO_USB_MODE={build.usb_mode} -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} -DARDUINO_USB_MSC_ON_BOOT={build.msc_on_boot} -DARDUINO_USB_DFU_ON_BOOT={build.dfu_on_boot}
+build.extra_flags.esp32s2=-DARDUINO_USB_MODE=0 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} -DARDUINO_USB_MSC_ON_BOOT={build.msc_on_boot} -DARDUINO_USB_DFU_ON_BOOT={build.dfu_on_boot}
+build.extra_flags.esp32c2=-DARDUINO_USB_CDC_ON_BOOT=0
+build.extra_flags.esp32c3=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot}
+build.extra_flags.esp32c6=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot}
+build.extra_flags.esp32h2=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot}
+build.extra_flags.esp32p4=-DARDUINO_USB_MODE={build.usb_mode} -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} -DARDUINO_USB_MSC_ON_BOOT={build.msc_on_boot} -DARDUINO_USB_DFU_ON_BOOT={build.dfu_on_boot}
+
 # This can be overriden in boards.txt
+build.zigbee_mode=
+build.zigbee_libs=
 build.flash_size=4MB
 build.flash_mode=dio
-build.boot=bootloader
+build.flash_freq=80m
+build.img_freq={build.flash_freq}
+build.boot=qio
+build.boot_freq={build.flash_freq}
+build.bootloader_addr=0x1000
+build.custom_bootloader=bootloader
+build.custom_partitions=partitions
 build.code_debug=0
 build.defines=
-build.extra_flags=-DESP32 -DCORE_DEBUG_LEVEL={build.code_debug} {build.defines}
+build.loop_core=
+build.event_core=
+build.extra_flags=-DARDUINO_HOST_OS="{runtime.os}" -DARDUINO_FQBN="{build.fqbn}" -DESP32=ESP32 -DCORE_DEBUG_LEVEL={build.code_debug} {build.loop_core} {build.event_core} {build.defines} {build.extra_flags.{build.mcu}} {build.zigbee_mode}
+build.extra_libs=
+build.memory_type={build.boot}_qspi
 
-# These can be overridden in platform.local.txt
-compiler.c.extra_flags=
-compiler.c.elf.extra_flags=
-compiler.S.extra_flags=
-compiler.cpp.extra_flags=
-compiler.ar.extra_flags=
-compiler.objcopy.eep.extra_flags=
-compiler.elf2hex.extra_flags=
-compiler.libraries.ldflags=
+# Custom build options
+build.opt.name=build_opt.h
+build.opt.path={build.path}/{build.opt.name}
+
+# Check if custom partitions exist: source > variant > build.partitions
+recipe.hooks.prebuild.1.pattern=/usr/bin/env bash -c "[ ! -f "{build.source.path}"/partitions.csv ] || cp -f "{build.source.path}"/partitions.csv "{build.path}"/partitions.csv"
+recipe.hooks.prebuild.2.pattern=/usr/bin/env bash -c "[ -f "{build.path}"/partitions.csv ] || [ ! -f "{build.variant.path}"/{build.custom_partitions}.csv ] || cp "{build.variant.path}"/{build.custom_partitions}.csv "{build.path}"/partitions.csv"
+recipe.hooks.prebuild.3.pattern=/usr/bin/env bash -c "[ -f "{build.path}"/partitions.csv ] || cp "{runtime.platform.path}"/tools/partitions/{build.partitions}.csv "{build.path}"/partitions.csv"
+
+recipe.hooks.prebuild.1.pattern.windows=cmd /c if exist "{build.source.path}\partitions.csv" COPY /y "{build.source.path}\partitions.csv" "{build.path}\partitions.csv"
+recipe.hooks.prebuild.2.pattern.windows=cmd /c if not exist "{build.path}\partitions.csv" if exist "{build.variant.path}\{build.custom_partitions}.csv" COPY "{build.variant.path}\{build.custom_partitions}.csv" "{build.path}\partitions.csv"
+recipe.hooks.prebuild.3.pattern.windows=cmd /c if not exist "{build.path}\partitions.csv" COPY "{runtime.platform.path}\tools\partitions\{build.partitions}.csv" "{build.path}\partitions.csv"
 
-# Build Dir: {build.path}
-# Sketch Dir: {build.source.path}
-recipe.hooks.prebuild.1.pattern=bash -c "[ ! -f {build.source.path}/partitions.csv ] || cp -f {build.source.path}/partitions.csv {build.path}/partitions.csv"
-recipe.hooks.prebuild.2.pattern=bash -c "[ -f {build.path}/partitions.csv ] || cp {runtime.platform.path}/tools/partitions/{build.partitions}.csv {build.path}/partitions.csv"
-recipe.hooks.prebuild.1.pattern.windows=cmd /c if exist "{build.source.path}\partitions.csv" copy /y "{build.source.path}\partitions.csv" "{build.path}\partitions.csv"
-recipe.hooks.prebuild.2.pattern.windows=cmd /c if not exist "{build.path}\partitions.csv" copy "{runtime.platform.path}\tools\partitions\{build.partitions}.csv" "{build.path}\partitions.csv"
+# Check if custom bootloader exist: source > variant > build.boot
+recipe.hooks.prebuild.4.pattern_args=--chip {build.mcu} elf2image --flash_mode {build.flash_mode} --flash_freq {build.img_freq} --flash_size {build.flash_size} -o
+recipe.hooks.prebuild.4.pattern=/usr/bin/env bash -c "[ -f "{build.source.path}"/bootloader.bin ] && cp -f "{build.source.path}"/bootloader.bin "{build.path}"/{build.project_name}.bootloader.bin || ( [ -f "{build.variant.path}"/{build.custom_bootloader}.bin ] && cp "{build.variant.path}"/{build.custom_bootloader}.bin "{build.path}"/{build.project_name}.bootloader.bin || "{tools.esptool_py.path}"/{tools.esptool_py.cmd} {recipe.hooks.prebuild.4.pattern_args} "{build.path}"/{build.project_name}.bootloader.bin "{compiler.sdk.path}"/bin/bootloader_{build.boot}_{build.boot_freq}.elf )"
+recipe.hooks.prebuild.4.pattern.windows=cmd /c IF EXIST "{build.source.path}\bootloader.bin" ( COPY /y "{build.source.path}\bootloader.bin" "{build.path}\{build.project_name}.bootloader.bin" ) ELSE ( IF EXIST "{build.variant.path}\{build.custom_bootloader}.bin" ( COPY "{build.variant.path}\{build.custom_bootloader}.bin" "{build.path}\{build.project_name}.bootloader.bin" ) ELSE ( "{tools.esptool_py.path}\{tools.esptool_py.cmd}" {recipe.hooks.prebuild.4.pattern_args} "{build.path}\{build.project_name}.bootloader.bin" "{compiler.sdk.path}\bin\bootloader_{build.boot}_{build.boot_freq}.elf" ) )
+
+# Check if custom build options exist in the sketch folder
+recipe.hooks.prebuild.5.pattern=/usr/bin/env bash -c "[ ! -f "{build.source.path}"/build_opt.h ] || cp -f "{build.source.path}"/build_opt.h "{build.path}"/build_opt.h"
+recipe.hooks.prebuild.6.pattern=/usr/bin/env bash -c "[ -f "{build.path}"/build_opt.h ] || : > "{build.path}"/build_opt.h"
+
+recipe.hooks.prebuild.5.pattern.windows=cmd /c if exist "{build.source.path}\build_opt.h" COPY /y "{build.source.path}\build_opt.h" "{build.path}\build_opt.h"
+recipe.hooks.prebuild.6.pattern.windows=cmd /c if not exist "{build.path}\build_opt.h" type nul > "{build.path}\build_opt.h"
+
+# Set -DARDUINO_CORE_BUILD only on core file compilation
+file_opts.path={build.path}/file_opts
+recipe.hooks.prebuild.7.pattern=/usr/bin/env bash -c ": > '{file_opts.path}'"
+recipe.hooks.core.prebuild.1.pattern=/usr/bin/env bash -c "echo -DARDUINO_CORE_BUILD > '{file_opts.path}'"
+recipe.hooks.core.postbuild.1.pattern=/usr/bin/env bash -c ": > '{file_opts.path}'"
+
+recipe.hooks.prebuild.7.pattern.windows=cmd /c type nul > "{file_opts.path}"
+recipe.hooks.core.prebuild.1.pattern.windows=cmd /c echo "-DARDUINO_CORE_BUILD" > "{file_opts.path}"
+recipe.hooks.core.postbuild.1.pattern.windows=cmd /c type nul > "{file_opts.path}"
+
+# Copy sdkconfig to build folder
+recipe.hooks.prebuild.8.pattern=/usr/bin/env bash -c "cp -f "{compiler.sdk.path}"/sdkconfig "{build.path}"/sdkconfig"
+recipe.hooks.prebuild.8.pattern.windows=cmd /c COPY /y "{compiler.sdk.path}\sdkconfig" "{build.path}\sdkconfig"
 
 ## Compile c files
-recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.c.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" -DARDUINO_VARIANT="{build.variant}" {compiler.c.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}"
+recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.extra_flags} {compiler.c.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" -DARDUINO_VARIANT="{build.variant}" -DARDUINO_PARTITION_{build.partitions} {build.extra_flags} {compiler.cpreprocessor.flags} {includes} "@{build.opt.path}" "@{file_opts.path}" "{source_file}" -o "{object_file}"
 
 ## Compile c++ files
-recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpreprocessor.flags} {compiler.cpp.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" -DARDUINO_VARIANT="{build.variant}" {compiler.cpp.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}"
+recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.extra_flags} {compiler.cpp.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" -DARDUINO_VARIANT="{build.variant}" -DARDUINO_PARTITION_{build.partitions} {build.extra_flags} {compiler.cpreprocessor.flags} {includes} "@{build.opt.path}" "@{file_opts.path}" "{source_file}" -o "{object_file}"
 
 ## Compile S files
-recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.cpreprocessor.flags} {compiler.S.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" -DARDUINO_VARIANT="{build.variant}" {compiler.S.extra_flags} {build.extra_flags} {includes} "{source_file}" -o "{object_file}"
+recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.extra_flags} {compiler.S.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} -DARDUINO_BOARD="{build.board}" -DARDUINO_VARIANT="{build.variant}" -DARDUINO_PARTITION_{build.partitions} {build.extra_flags} {compiler.cpreprocessor.flags} {includes} "@{build.opt.path}" "@{file_opts.path}" "{source_file}" -o "{object_file}"
 
 ## Create archives
 recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}"
 
 ## Combine gc-sections, archives, and objects
-recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} {compiler.c.elf.extra_flags} {compiler.libraries.ldflags} -Wl,--start-group {object_files} "{archive_file_path}" {compiler.c.elf.libs} -Wl,--end-group -Wl,-EL -o "{build.path}/{build.project_name}.elf"
+recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} {compiler.c.elf.extra_flags} -Wl,--start-group {object_files} "{archive_file_path}" {build.extra_libs} {build.zigbee_libs} {compiler.c.elf.libs} {compiler.libraries.ldflags} -Wl,--end-group -Wl,-EL -o "{build.path}/{build.project_name}.elf"
 
 ## Create partitions.bin
 recipe.objcopy.partitions.bin.pattern={tools.gen_esp32part.cmd} -q "{build.path}/partitions.csv" "{build.path}/{build.project_name}.partitions.bin"
 
 ## Create bin
-recipe.objcopy.bin.pattern="{tools.esptool_py.path}/{tools.esptool_py.cmd}" --chip esp32 elf2image --flash_mode "{build.flash_mode}" --flash_freq "{build.flash_freq}" --flash_size "{build.flash_size}" -o "{build.path}/{build.project_name}.bin" "{build.path}/{build.project_name}.elf"
-recipe.objcopy.bin.pattern.linux=python "{tools.esptool_py.path}/{tools.esptool_py.cmd}" --chip esp32 elf2image --flash_mode "{build.flash_mode}" --flash_freq "{build.flash_freq}" --flash_size "{build.flash_size}" -o "{build.path}/{build.project_name}.bin" "{build.path}/{build.project_name}.elf"
+recipe.objcopy.bin.pattern_args=--chip {build.mcu} elf2image --flash_mode "{build.flash_mode}" --flash_freq "{build.img_freq}" --flash_size "{build.flash_size}" --elf-sha256-offset 0xb0 -o "{build.path}/{build.project_name}.bin" "{build.path}/{build.project_name}.elf"
+recipe.objcopy.bin.pattern="{tools.esptool_py.path}/{tools.esptool_py.cmd}" {recipe.objcopy.bin.pattern_args}
+
+## Create Insights Firmware Package
+recipe.hooks.objcopy.postobjcopy.1.pattern_args={build.path} {build.project_name} "{build.source.path}"
+recipe.hooks.objcopy.postobjcopy.1.pattern=/usr/bin/env bash -c "[ ! -d "{build.path}"/libraries/Insights ] || {tools.gen_insights_pkg.cmd} {recipe.hooks.objcopy.postobjcopy.1.pattern_args}"
+recipe.hooks.objcopy.postobjcopy.1.pattern.windows=cmd /c if exist "{build.path}\libraries\Insights" {tools.gen_insights_pkg.cmd} {recipe.hooks.objcopy.postobjcopy.1.pattern_args}
+
+## Copy ESP_SR Model
+recipe.hooks.objcopy.postobjcopy.2.pattern=/usr/bin/env bash -c "[ ! -d "{build.path}"/libraries/ESP_SR ] || [ ! -f "{compiler.sdk.path}"/esp_sr/srmodels.bin ] || cp -f "{compiler.sdk.path}"/esp_sr/srmodels.bin "{build.path}"/srmodels.bin"
+recipe.hooks.objcopy.postobjcopy.2.pattern.windows=cmd /c if exist "{build.path}\libraries\ESP_SR" if exist "{compiler.sdk.path}\esp_sr\srmodels.bin" COPY /y "{compiler.sdk.path}\esp_sr\srmodels.bin" "{build.path}\srmodels.bin"
+
+# Create merged binary
+recipe.hooks.objcopy.postobjcopy.3.pattern_args=--chip {build.mcu} merge_bin -o "{build.path}/{build.project_name}.merged.bin" --fill-flash-size {build.flash_size} --flash_mode keep --flash_freq keep --flash_size keep {build.bootloader_addr} "{build.path}/{build.project_name}.bootloader.bin" 0x8000 "{build.path}/{build.project_name}.partitions.bin" 0xe000 "{runtime.platform.path}/tools/partitions/boot_app0.bin" 0x10000 "{build.path}/{build.project_name}.bin"
+recipe.hooks.objcopy.postobjcopy.3.pattern="{tools.esptool_py.path}/{tools.esptool_py.cmd}" {recipe.hooks.objcopy.postobjcopy.3.pattern_args}
 
 ## Save bin
 recipe.output.tmp_file={build.project_name}.bin
@@ -99,14 +185,148 @@ recipe.output.save_file={build.project_name}.{build.variant}.bin
 
 ## Compute size
 recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf"
-recipe.size.regex=^(?:\.iram0\.text|\.iram0\.vectors|\.dram0\.data|\.flash\.text|\.flash\.rodata|)\s+([0-9]+).*
-recipe.size.regex.data=^(?:\.dram0\.data|\.dram0\.bss|\.noinit)\s+([0-9]+).*
+recipe.size.regex=^(?:\.iram0\.text|\.iram0\.vectors|\.dram0\.data|\.dram1\.data|\.flash\.text|\.flash\.rodata|\.flash\.appdesc|\.flash\.init_array|\.eh_frame|)\s+([0-9]+).*
+recipe.size.regex.data=^(?:\.dram0\.data|\.dram0\.bss|\.dram1\.data|\.dram1\.bss|\.noinit)\s+([0-9]+).*
+
+## Required discoveries and monitors
+## ---------------------------------
+pluggable_discovery.required.0=builtin:serial-discovery
+pluggable_discovery.required.1=builtin:mdns-discovery
+pluggable_monitor.required.serial=builtin:serial-monitor
+
+## ------------------
+## Upload/Debug tools
+## ------------------
+
+# Debugger configuration
+# ----------------------
+
+# ESP32 debug configuration
+debug_script.esp32=esp32-wrover-kit-3.3v.cfg
+debug_config.esp32.cortex-debug.custom.name=Arduino on ESP32
+debug_config.esp32.cortex-debug.custom.postAttachCommands.0=set remote hardware-watchpoint-limit 2
+debug_config.esp32.cortex-debug.custom.postAttachCommands.1=monitor reset halt
+debug_config.esp32.cortex-debug.custom.postAttachCommands.2=monitor gdb_sync
+debug_config.esp32.cortex-debug.custom.postAttachCommands.3=thb setup
+debug_config.esp32.cortex-debug.custom.postAttachCommands.4=c
+debug_config.esp32.cortex-debug.custom.overrideRestartCommands.0=monitor reset halt
+debug_config.esp32.cortex-debug.custom.overrideRestartCommands.1=monitor gdb_sync
+debug_config.esp32.cortex-debug.custom.overrideRestartCommands.2=thb setup
+debug_config.esp32.cortex-debug.custom.overrideRestartCommands.3=c
+
+# ESP32-S2 debug configuration
+debug_script.esp32s2=esp32s2-kaluga-1.cfg
+debug_config.esp32s2.cortex-debug.custom.name=Arduino on ESP32-S2
+debug_config.esp32s2.cortex-debug.custom.postAttachCommands.0=set remote hardware-watchpoint-limit 2
+debug_config.esp32s2.cortex-debug.custom.postAttachCommands.1=monitor reset halt
+debug_config.esp32s2.cortex-debug.custom.postAttachCommands.2=monitor gdb_sync
+debug_config.esp32s2.cortex-debug.custom.postAttachCommands.3=thb setup
+debug_config.esp32s2.cortex-debug.custom.postAttachCommands.4=c
+debug_config.esp32s2.cortex-debug.custom.overrideRestartCommands.0=monitor reset halt
+debug_config.esp32s2.cortex-debug.custom.overrideRestartCommands.1=monitor gdb_sync
+debug_config.esp32s2.cortex-debug.custom.overrideRestartCommands.2=thb setup
+debug_config.esp32s2.cortex-debug.custom.overrideRestartCommands.3=c
 
-# ------------------------------
+# ESP32-S3 debug configuration
+debug_script.esp32s3=esp32s3-builtin.cfg
+debug_config.esp32s3.cortex-debug.custom.name=Arduino on ESP32-S3
+debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.0=set remote hardware-watchpoint-limit 2
+debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.1=monitor reset halt
+debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.2=monitor gdb_sync
+debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.3=thb setup
+debug_config.esp32s3.cortex-debug.custom.overrideAttachCommands.4=c
+debug_config.esp32s3.cortex-debug.custom.overrideRestartCommands.0=monitor reset halt
+debug_config.esp32s3.cortex-debug.custom.overrideRestartCommands.1=monitor gdb_sync
 
-tools.esptool_py.upload.protocol=esp32
+# ESP32-C3 debug configuration
+debug_script.esp32c3=esp32c3-builtin.cfg
+debug_config.esp32c3.cortex-debug.custom.name=Arduino on ESP32-C3
+debug_config.esp32c3.cortex-debug.custom.serverArgs.0=-d3
+debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.0=set remote hardware-watchpoint-limit 8
+debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.1=monitor reset
+debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.2=monitor halt
+debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.3=monitor gdb_sync
+debug_config.esp32c3.cortex-debug.custom.overrideAttachCommands.4=thb setup
+debug_config.esp32c3.cortex-debug.custom.overrideRestartCommands.0=monitor reset
+debug_config.esp32c3.cortex-debug.custom.overrideRestartCommands.1=monitor halt
+debug_config.esp32c3.cortex-debug.custom.overrideRestartCommands.2=monitor gdb_sync
+debug_config.esp32c3.cortex-debug.custom.overrideRestartCommands.3=thb setup
+
+# ESP32-C6 debug configuration (TBD)
+debug_script.esp32c6=esp32c6-builtin.cfg
+debug_config.esp32c6=
+
+# ESP32-H2 debug configuration (TBD)
+debug_script.esp32h2=esp32h2-builtin.cfg
+debug_config.esp32h2=
+
+# Debug API variable definitions
+debug.executable={build.path}/{build.project_name}.elf
+debug.toolchain=gcc
+debug.toolchain.path={tools.{build.tarch}-esp-elf-gdb.path}/bin/
+debug.toolchain.prefix={build.tarch}-{build.target}-elf
+debug.server=openocd
+debug.server.openocd.path={runtime.platform.path}/tools/openocd-esp32/bin/openocd
+debug.server.openocd.scripts_dir={runtime.platform.path}/tools/openocd-esp32/share/openocd/scripts/
+debug.server.openocd.scripts_dir.windows={runtime.platform.path}\tools\openocd-esp32\share\openocd\scripts\
+debug.server.openocd.scripts.0=board/{debug_script.{build.mcu}}
+debug.svd_file={runtime.platform.path}/tools/ide-debug/svd/{build.mcu}.svd
+
+debug.cortex-debug.custom.objdumpPath={compiler.path}{compiler.prefix}objdump
+debug.cortex-debug.custom.request=attach
+debug.additional_config=debug_config.{build.mcu}
+
+##
+## ESPTool
+##
+
+## Upload Sketch
+## -------------
+tools.esptool_py.upload.protocol=serial
 tools.esptool_py.upload.params.verbose=
 tools.esptool_py.upload.params.quiet=
-tools.esptool_py.upload.pattern="{path}/{cmd}" --chip esp32 --port "{serial.port}" --baud {upload.speed}  --before default_reset --after hard_reset write_flash -z --flash_mode {build.flash_mode} --flash_freq {build.flash_freq} --flash_size detect 0xe000 "{runtime.platform.path}/tools/partitions/boot_app0.bin" 0x1000 "{runtime.platform.path}/tools/sdk/bin/bootloader_{build.boot}_{build.flash_freq}.bin" 0x10000 "{build.path}/{build.project_name}.bin" 0x8000 "{build.path}/{build.project_name}.partitions.bin"
-tools.esptool_py.upload.pattern.linux=python "{path}/{cmd}" --chip esp32 --port "{serial.port}" --baud {upload.speed}  --before default_reset --after hard_reset write_flash -z --flash_mode {build.flash_mode} --flash_freq {build.flash_freq} --flash_size detect 0xe000 "{runtime.platform.path}/tools/partitions/boot_app0.bin" 0x1000 "{runtime.platform.path}/tools/sdk/bin/bootloader_{build.boot}_{build.flash_freq}.bin" 0x10000 "{build.path}/{build.project_name}.bin" 0x8000 "{build.path}/{build.project_name}.partitions.bin"
+tools.esptool_py.upload.pattern_args=--chip {build.mcu} --port "{serial.port}" --baud {upload.speed} {upload.flags} --before default_reset --after hard_reset write_flash {upload.erase_cmd} -z --flash_mode keep --flash_freq keep --flash_size keep {build.bootloader_addr} "{build.path}/{build.project_name}.bootloader.bin" 0x8000 "{build.path}/{build.project_name}.partitions.bin" 0xe000 "{runtime.platform.path}/tools/partitions/boot_app0.bin" 0x10000 "{build.path}/{build.project_name}.bin" {upload.extra_flags}
+tools.esptool_py.upload.pattern="{path}/{cmd}" {upload.pattern_args}
+
+## Program Application
+## -------------------
+tools.esptool_py.program.params.verbose=
+tools.esptool_py.program.params.quiet=
+tools.esptool_py.program.pattern_args=--chip {build.mcu} --port "{serial.port}" --baud {upload.speed} {upload.flags} --before default_reset --after hard_reset write_flash -z --flash_mode keep --flash_freq keep --flash_size keep 0x10000 "{build.path}/{build.project_name}.bin"
+tools.esptool_py.program.pattern="{path}/{cmd}" {program.pattern_args}
+
+## Erase Chip (before burning the bootloader)
+## ------------------------------------------
+tools.esptool_py.erase.protocol=serial
+tools.esptool_py.erase.params.verbose=
+tools.esptool_py.erase.params.quiet=
+tools.esptool_py.erase.pattern_args=--chip {build.mcu} --port "{serial.port}" --baud {upload.speed} {upload.flags} --before default_reset --after hard_reset erase_flash
+tools.esptool_py.erase.pattern="{path}/{cmd}" {erase.pattern_args}
+
+## Burn Bootloader
+## ---------------
+tools.esptool_py.bootloader.protocol=serial
+tools.esptool_py.bootloader.params.verbose=
+tools.esptool_py.bootloader.params.quiet=
+tools.esptool_py.bootloader.pattern=
+
+## Upload Sketch Through OTA (Arduino IDE 1.x)
+## -------------------------------------------
+## The following rule is deprecated by pluggable discovery.
+## We keep it to avoid breaking compatibility with the Arduino Java IDE.
 tools.esptool_py.upload.network_pattern={network_cmd} -i "{serial.port}" -p "{network.port}" "--auth={network.password}" -f "{build.path}/{build.project_name}.bin"
+
+## Upload Sketch Through OTA (Arduino IDE 2.x)
+## -------------------------------------------
+tools.esp_ota.upload.protocol=network
+tools.esp_ota.upload.field.password=Password
+tools.esp_ota.upload.field.password.secret=true
+tools.esp_ota.upload.pattern={cmd} -i {upload.port.address} -p {upload.port.properties.port} "--auth={upload.field.password}" -f "{build.path}/{build.project_name}.bin"
+
+## Upload Sketch Through DFU OTA
+## -------------------------------------------
+tools.dfu-util.path={runtime.tools.dfu-util-0.11.0-arduino5.path}
+tools.dfu-util.cmd=dfu-util
+tools.dfu-util.upload.params.verbose=-d
+tools.dfu-util.upload.params.quiet=
+tools.dfu-util.upload.pattern="{path}/{cmd}" --device {vid.0}:{pid.0} -D "{build.path}/{build.project_name}.bin" -Q
diff --git a/programmers.txt b/programmers.txt
index e69de29bb2d..8148c185a52 100644
--- a/programmers.txt
+++ b/programmers.txt
@@ -0,0 +1,8 @@
+esptool.name=Esptool
+esptool.communication=serial
+esptool.protocol=serial
+esptool.program.protocol=serial
+esptool.program.tool=esptool_py
+esptool.program.tool.default=esptool_py
+esptool.program.extra_params=
+esptool.extra_params=
diff --git a/tests/.gitignore b/tests/.gitignore
new file mode 100644
index 00000000000..fc427d51090
--- /dev/null
+++ b/tests/.gitignore
@@ -0,0 +1,6 @@
+build*/
+__pycache__/
+*.xml
+result_*.json
+diagram.json
+wokwi.toml
diff --git a/tests/performance/coremark/ci.json b/tests/performance/coremark/ci.json
new file mode 100644
index 00000000000..accee2b2135
--- /dev/null
+++ b/tests/performance/coremark/ci.json
@@ -0,0 +1,6 @@
+{
+  "platforms": {
+    "qemu": false,
+    "wokwi": false
+  }
+}
diff --git a/tests/performance/coremark/core_list_join.c b/tests/performance/coremark/core_list_join.c
new file mode 100644
index 00000000000..a5154284a37
--- /dev/null
+++ b/tests/performance/coremark/core_list_join.c
@@ -0,0 +1,495 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/*
+Topic: Description
+	Benchmark using a linked list.
+
+	Linked list is a common data structure used in many applications.
+	
+	For our purposes, this will excercise the memory units of the processor.
+	In particular, usage of the list pointers to find and alter data.
+	
+	We are not using Malloc since some platforms do not support this library.
+	
+	Instead, the memory block being passed in is used to create a list,
+	and the benchmark takes care not to add more items then can be
+	accomodated by the memory block. The porting layer will make sure
+	that we have a valid memory block.
+	
+	All operations are done in place, without using any extra memory.
+	
+	The list itself contains list pointers and pointers to data items.
+	Data items contain the following:
+	
+	idx - An index that captures the initial order of the list.
+	data - Variable data initialized based on the input parameters. The 16b are divided as follows:
+	o Upper 8b are backup of original data.
+	o Bit 7 indicates if the lower 7 bits are to be used as is or calculated.
+	o Bits 0-2 indicate type of operation to perform to get a 7b value.
+	o Bits 3-6 provide input for the operation.
+	
+*/
+
+/* local functions */
+
+list_head *core_list_find(list_head *list,list_data *info);
+list_head *core_list_reverse(list_head *list);
+list_head *core_list_remove(list_head *item);
+list_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified);
+list_head *core_list_insert_new(list_head *insert_point
+	, list_data *info, list_head **memblock, list_data **datablock
+	, list_head *memblock_end, list_data *datablock_end);
+typedef ee_s32(*list_cmp)(list_data *a, list_data *b, core_results *res);
+list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res);
+
+ee_s16 calc_func(ee_s16 *pdata, core_results *res) {
+	ee_s16 data=*pdata;
+	ee_s16 retval;
+	ee_u8 optype=(data>>7) & 1; /* bit 7 indicates if the function result has been cached */
+	if (optype) /* if cached, use cache */
+		return (data & 0x007f);
+	else { /* otherwise calculate and cache the result */
+		ee_s16 flag=data & 0x7; /* bits 0-2 is type of function to perform */
+		ee_s16 dtype=((data>>3) & 0xf); /* bits 3-6 is specific data for the operation */
+		dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */
+		switch (flag) {
+			case 0:
+				if (dtype<0x22) /* set min period for bit corruption */
+					dtype=0x22;
+				retval=core_bench_state(res->size,res->memblock[3],res->seed1,res->seed2,dtype,res->crc);
+				if (res->crcstate==0)
+					res->crcstate=retval;
+				break;
+			case 1:
+				retval=core_bench_matrix(&(res->mat),dtype,res->crc);
+				if (res->crcmatrix==0)
+					res->crcmatrix=retval;
+				break;
+			default:
+				retval=data;
+				break;
+		}
+		res->crc=crcu16(retval,res->crc);
+		retval &= 0x007f; 
+		*pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */
+		return retval;
+	}
+}
+/* Function: cmp_complex
+	Compare the data item in a list cell.
+
+	Can be used by mergesort.
+*/
+ee_s32 cmp_complex(list_data *a, list_data *b, core_results *res) {
+	ee_s16 val1=calc_func(&(a->data16),res);
+	ee_s16 val2=calc_func(&(b->data16),res);
+	return val1 - val2;
+}
+
+/* Function: cmp_idx
+	Compare the idx item in a list cell, and regen the data.
+
+	Can be used by mergesort.
+*/
+ee_s32 cmp_idx(list_data *a, list_data *b, core_results *res) {
+	if (res==NULL) {
+		a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16>>8));
+		b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16>>8));
+	}
+	return a->idx - b->idx;
+}
+
+void copy_info(list_data *to,list_data *from) {
+	to->data16=from->data16;
+	to->idx=from->idx;
+}
+
+/* Benchmark for linked list:
+	- Try to find multiple data items.
+	- List sort
+	- Operate on data from list (crc)
+	- Single remove/reinsert
+	* At the end of this function, the list is back to original state
+*/
+ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx) {
+	ee_u16 retval=0;
+	ee_u16 found=0,missed=0;
+	list_head *list=res->list;
+	ee_s16 find_num=res->seed3;
+	list_head *this_find;
+	list_head *finder, *remover;
+	list_data info;
+	ee_s16 i;
+
+	info.idx=finder_idx;
+	/* find <find_num> values in the list, and change the list each time (reverse and cache if value found) */
+	for (i=0; i<find_num; i++) {
+		info.data16= (i & 0xff) ;
+		this_find=core_list_find(list,&info);
+		list=core_list_reverse(list);
+		if (this_find==NULL) {
+			missed++;
+			retval+=(list->next->info->data16 >> 8) & 1;
+		}
+		else {
+			found++;
+			if (this_find->info->data16 & 0x1) /* use found value */
+				retval+=(this_find->info->data16 >> 9) & 1;
+			/* and cache next item at the head of the list (if any) */
+			if (this_find->next != NULL) {
+				finder = this_find->next;
+				this_find->next = finder->next;
+				finder->next=list->next;
+				list->next=finder;
+			}
+		}
+		if (info.idx>=0)
+			info.idx++;
+#if CORE_DEBUG
+	ee_printf("List find %d: [%d,%d,%d]\n",i,retval,missed,found);
+#endif
+	}
+	retval+=found*4-missed;
+	/* sort the list by data content and remove one item*/
+	if (finder_idx>0)
+		list=core_list_mergesort(list,cmp_complex,res);
+	remover=core_list_remove(list->next);
+	/* CRC data content of list from location of index N forward, and then undo remove */
+	finder=core_list_find(list,&info);
+	if (!finder)
+		finder=list->next;
+	while (finder) {
+		retval=crc16(list->info->data16,retval);
+		finder=finder->next;
+	}
+#if CORE_DEBUG
+	ee_printf("List sort 1: %04x\n",retval);
+#endif
+	remover=core_list_undo_remove(remover,list->next);
+	/* sort the list by index, in effect returning the list to original state */
+	list=core_list_mergesort(list,cmp_idx,NULL);
+	/* CRC data content of list */
+	finder=list->next;
+	while (finder) {
+		retval=crc16(list->info->data16,retval);
+		finder=finder->next;
+	}
+#if CORE_DEBUG
+	ee_printf("List sort 2: %04x\n",retval);
+#endif
+	return retval;
+}
+/* Function: core_list_init
+	Initialize list with data.
+
+	Parameters:
+	blksize - Size of memory to be initialized.
+	memblock - Pointer to memory block.
+	seed - 	Actual values chosen depend on the seed parameter.
+		The seed parameter MUST be supplied from a source that cannot be determined at compile time
+
+	Returns:
+	Pointer to the head of the list.
+
+*/
+list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed) {
+	/* calculated pointers for the list */
+	ee_u32 per_item=16+sizeof(struct list_data_s);
+	ee_u32 size=(blksize/per_item)-2; /* to accomodate systems with 64b pointers, and make sure same code is executed, set max list elements */
+	list_head *memblock_end=memblock+size;
+	list_data *datablock=(list_data *)(memblock_end);
+	list_data *datablock_end=datablock+size;
+	/* some useful variables */
+	ee_u32 i;
+	list_head *finder,*list=memblock;
+	list_data info;
+
+	/* create a fake items for the list head and tail */
+	list->next=NULL;
+	list->info=datablock;
+	list->info->idx=0x0000;
+	list->info->data16=(ee_s16)0x8080;
+	memblock++;
+	datablock++;
+	info.idx=0x7fff;
+	info.data16=(ee_s16)0xffff;
+	core_list_insert_new(list,&info,&memblock,&datablock,memblock_end,datablock_end);
+	
+	/* then insert size items */
+	for (i=0; i<size; i++) {
+		ee_u16 datpat=((ee_u16)(seed^i) & 0xf);
+		ee_u16 dat=(datpat<<3) | (i&0x7); /* alternate between algorithms */
+		info.data16=(dat<<8) | dat;		/* fill the data with actual data and upper bits with rebuild value */
+		core_list_insert_new(list,&info,&memblock,&datablock,memblock_end,datablock_end);
+	}
+	/* and now index the list so we know initial seed order of the list */
+	finder=list->next;
+	i=1;
+	while (finder->next!=NULL) {
+		if (i<size/5) /* first 20% of the list in order */
+			finder->info->idx=i++;
+		else { 
+			ee_u16 pat=(ee_u16)(i++ ^ seed); /* get a pseudo random number */
+			finder->info->idx=0x3fff & (((i & 0x07) << 8) | pat); /* make sure the mixed items end up after the ones in sequence */
+		}
+		finder=finder->next;
+	}
+	list = core_list_mergesort(list,cmp_idx,NULL);
+#if CORE_DEBUG
+	ee_printf("Initialized list:\n");
+	finder=list;
+	while (finder) {
+		ee_printf("[%04x,%04x]",finder->info->idx,(ee_u16)finder->info->data16);
+		finder=finder->next;
+	}
+	ee_printf("\n");
+#endif
+	return list;
+}
+
+/* Function: core_list_insert
+	Insert an item to the list
+
+	Parameters:
+	insert_point - where to insert the item.
+	info - data for the cell.
+	memblock - pointer for the list header
+	datablock - pointer for the list data
+	memblock_end - end of region for list headers
+	datablock_end - end of region for list data
+
+	Returns:
+	Pointer to new item.
+*/
+list_head *core_list_insert_new(list_head *insert_point, list_data *info, list_head **memblock, list_data **datablock
+	, list_head *memblock_end, list_data *datablock_end) {
+	list_head *newitem;
+	
+	if ((*memblock+1) >= memblock_end)
+		return NULL;
+	if ((*datablock+1) >= datablock_end)
+		return NULL;
+		
+	newitem=*memblock;
+	(*memblock)++;
+	newitem->next=insert_point->next;
+	insert_point->next=newitem;
+	
+	newitem->info=*datablock;
+	(*datablock)++;
+	copy_info(newitem->info,info);
+	
+	return newitem;
+}
+
+/* Function: core_list_remove
+	Remove an item from the list.
+
+	Operation:
+	For a singly linked list, remove by copying the data from the next item 
+	over to the current cell, and unlinking the next item.
+
+	Note: 
+	since there is always a fake item at the end of the list, no need to check for NULL.
+
+	Returns:
+	Removed item.
+*/
+list_head *core_list_remove(list_head *item) {
+	list_data *tmp;
+	list_head *ret=item->next;
+	/* swap data pointers */
+	tmp=item->info;
+	item->info=ret->info;
+	ret->info=tmp;
+	/* and eliminate item */
+	item->next=item->next->next;
+	ret->next=NULL;
+	return ret;
+}
+
+/* Function: core_list_undo_remove
+	Undo a remove operation.
+
+	Operation:
+	Since we want each iteration of the benchmark to be exactly the same,
+	we need to be able to undo a remove. 
+	Link the removed item back into the list, and switch the info items.
+
+	Parameters:
+	item_removed - Return value from the <core_list_remove>
+	item_modified - List item that was modified during <core_list_remove>
+
+	Returns:
+	The item that was linked back to the list.
+	
+*/
+list_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified) {
+	list_data *tmp;
+	/* swap data pointers */
+	tmp=item_removed->info;
+	item_removed->info=item_modified->info;
+	item_modified->info=tmp;
+	/* and insert item */
+	item_removed->next=item_modified->next;
+	item_modified->next=item_removed;
+	return item_removed;
+}
+
+/* Function: core_list_find
+	Find an item in the list
+
+	Operation:
+	Find an item by idx (if not 0) or specific data value
+
+	Parameters:
+	list - list head
+	info - idx or data to find
+
+	Returns:
+	Found item, or NULL if not found.
+*/
+list_head *core_list_find(list_head *list,list_data *info) {
+	if (info->idx>=0) {
+		while (list && (list->info->idx != info->idx))
+			list=list->next;
+		return list;
+	} else {
+		while (list && ((list->info->data16 & 0xff) != info->data16))
+			list=list->next;
+		return list;
+	}
+}
+/* Function: core_list_reverse
+	Reverse a list
+
+	Operation:
+	Rearrange the pointers so the list is reversed.
+
+	Parameters:
+	list - list head
+	info - idx or data to find
+
+	Returns:
+	Found item, or NULL if not found.
+*/
+
+list_head *core_list_reverse(list_head *list) {
+	list_head *next=NULL, *tmp;
+	while (list) {
+		tmp=list->next;
+		list->next=next;
+		next=list;
+		list=tmp;
+	}
+	return next;
+}
+/* Function: core_list_mergesort
+	Sort the list in place without recursion.
+
+	Description:
+	Use mergesort, as for linked list this is a realistic solution. 
+	Also, since this is aimed at embedded, care was taken to use iterative rather then recursive algorithm.
+	The sort can either return the list to original order (by idx) ,
+	or use the data item to invoke other other algorithms and change the order of the list.
+
+	Parameters:
+	list - list to be sorted.
+	cmp - cmp function to use
+
+	Returns:
+	New head of the list.
+
+	Note: 
+	We have a special header for the list that will always be first,
+	but the algorithm could theoretically modify where the list starts.
+
+ */
+list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res) {
+    list_head *p, *q, *e, *tail;
+    ee_s32 insize, nmerges, psize, qsize, i;
+
+    insize = 1;
+
+    while (1) {
+        p = list;
+        list = NULL;
+        tail = NULL;
+
+        nmerges = 0;  /* count number of merges we do in this pass */
+
+        while (p) {
+            nmerges++;  /* there exists a merge to be done */
+            /* step `insize' places along from p */
+            q = p;
+            psize = 0;
+            for (i = 0; i < insize; i++) {
+                psize++;
+			    q = q->next;
+                if (!q) break;
+            }
+
+            /* if q hasn't fallen off end, we have two lists to merge */
+            qsize = insize;
+
+            /* now we have two lists; merge them */
+            while (psize > 0 || (qsize > 0 && q)) {
+
+				/* decide whether next element of merge comes from p or q */
+				if (psize == 0) {
+				    /* p is empty; e must come from q. */
+				    e = q; q = q->next; qsize--;
+				} else if (qsize == 0 || !q) {
+				    /* q is empty; e must come from p. */
+				    e = p; p = p->next; psize--;
+				} else if (cmp(p->info,q->info,res) <= 0) {
+				    /* First element of p is lower (or same); e must come from p. */
+				    e = p; p = p->next; psize--;
+				} else {
+				    /* First element of q is lower; e must come from q. */
+				    e = q; q = q->next; qsize--;
+				}
+
+		        /* add the next element to the merged list */
+				if (tail) {
+				    tail->next = e;
+				} else {
+				    list = e;
+				}
+				tail = e;
+	        }
+
+			/* now p has stepped `insize' places along, and q has too */
+			p = q;
+        }
+		
+	    tail->next = NULL;
+
+        /* If we have done only one merge, we're finished. */
+        if (nmerges <= 1)   /* allow for nmerges==0, the empty list case */
+            return list;
+
+        /* Otherwise repeat, merging lists twice the size */
+        insize *= 2;
+    }
+#if COMPILER_REQUIRES_SORT_RETURN
+	return list;
+#endif
+}
diff --git a/tests/performance/coremark/core_main.c b/tests/performance/coremark/core_main.c
new file mode 100644
index 00000000000..61619744ea4
--- /dev/null
+++ b/tests/performance/coremark/core_main.c
@@ -0,0 +1,356 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* File: core_main.c
+	This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.
+*/
+#include "coremark.h"
+
+/* Function: iterate
+	Run the benchmark for a specified number of iterations.
+
+	Operation:
+	For each type of benchmarked algorithm:
+		a - Initialize the data block for the algorithm.
+		b - Execute the algorithm N times.
+
+	Returns:
+	NULL.
+*/
+static ee_u16 list_known_crc[]   =      {(ee_u16)0xd4b0,(ee_u16)0x3340,(ee_u16)0x6a79,(ee_u16)0xe714,(ee_u16)0xe3c1};
+static ee_u16 matrix_known_crc[] =      {(ee_u16)0xbe52,(ee_u16)0x1199,(ee_u16)0x5608,(ee_u16)0x1fd7,(ee_u16)0x0747};
+static ee_u16 state_known_crc[]  =      {(ee_u16)0x5e47,(ee_u16)0x39bf,(ee_u16)0xe5a4,(ee_u16)0x8e3a,(ee_u16)0x8d84};
+void *iterate(void *pres) {
+	ee_u32 i;
+	ee_u16 crc;
+	core_results *res=(core_results *)pres;
+	ee_u32 iterations=res->iterations;
+	res->crc=0;
+	res->crclist=0;
+	res->crcmatrix=0;
+	res->crcstate=0;
+
+	for (i=0; i<iterations; i++) {
+		crc=core_bench_list(res,1);
+		res->crc=crcu16(crc,res->crc);
+		crc=core_bench_list(res,-1);
+		res->crc=crcu16(crc,res->crc);
+		if (i==0) res->crclist=res->crc;
+	}
+	return NULL;
+}
+
+#if (SEED_METHOD==SEED_ARG)
+ee_s32 get_seed_args(int i, int argc, char *argv[]);
+#define get_seed(x) (ee_s16)get_seed_args(x,argc,argv)
+#define get_seed_32(x) get_seed_args(x,argc,argv)
+#else /* via function or volatile */
+ee_s32 get_seed_32(int i);
+#define get_seed(x) (ee_s16)get_seed_32(x)
+#endif
+
+#if (MEM_METHOD==MEM_STATIC)
+ee_u8 static_memblk[TOTAL_DATA_SIZE];
+#endif
+char *mem_name[3] = {"Static","Heap","Stack"};
+/* Function: main
+	Main entry routine for the benchmark.
+	This function is responsible for the following steps:
+
+	1 - Initialize input seeds from a source that cannot be determined at compile time.
+	2 - Initialize memory block for use.
+	3 - Run and time the benchmark.
+	4 - Report results, testing the validity of the output if the seeds are known.
+
+	Arguments:
+	1 - first seed  : Any value
+	2 - second seed : Must be identical to first for iterations to be identical
+	3 - third seed  : Any value, should be at least an order of magnitude less then the input size, but bigger then 32.
+	4 - Iterations  : Special, if set to 0, iterations will be automatically determined such that the benchmark will run between 10 to 100 secs
+
+*/
+
+#if MAIN_HAS_NOARGC
+MAIN_RETURN_TYPE main(void) {
+	int argc=0;
+	char *argv[1];
+#else
+MAIN_RETURN_TYPE main(int argc, char *argv[]) {
+#endif
+	ee_u16 i,j=0,num_algorithms=0;
+	ee_s16 known_id=-1,total_errors=0;
+	ee_u16 seedcrc=0;
+	CORE_TICKS total_time;
+	core_results results[MULTITHREAD];
+#if (MEM_METHOD==MEM_STACK)
+	ee_u8 stack_memblock[TOTAL_DATA_SIZE*MULTITHREAD];
+#endif
+	/* first call any initializations needed */
+	portable_init(&(results[0].port), &argc, argv);
+	/* First some checks to make sure benchmark will run ok */
+	if (sizeof(struct list_head_s)>128) {
+		ee_printf("list_head structure too big for comparable data!\n");
+		return MAIN_RETURN_VAL;
+	}
+	results[0].seed1=get_seed(1);
+	results[0].seed2=get_seed(2);
+	results[0].seed3=get_seed(3);
+	results[0].iterations=get_seed_32(4);
+#if CORE_DEBUG
+	results[0].iterations=1;
+#endif
+	results[0].execs=get_seed_32(5);
+	if (results[0].execs==0) { /* if not supplied, execute all algorithms */
+		results[0].execs=ALL_ALGORITHMS_MASK;
+	}
+		/* put in some default values based on one seed only for easy testing */
+	if ((results[0].seed1==0) && (results[0].seed2==0) && (results[0].seed3==0)) { /* validation run */
+		results[0].seed1=0;
+		results[0].seed2=0;
+		results[0].seed3=0x66;
+	}
+	if ((results[0].seed1==1) && (results[0].seed2==0) && (results[0].seed3==0)) { /* perfromance run */
+		results[0].seed1=0x3415;
+		results[0].seed2=0x3415;
+		results[0].seed3=0x66;
+	}
+#if (MEM_METHOD==MEM_STATIC)
+	results[0].memblock[0]=(void *)static_memblk;
+	results[0].size=TOTAL_DATA_SIZE;
+	results[0].err=0;
+	#if (MULTITHREAD>1)
+	#error "Cannot use a static data area with multiple contexts!"
+	#endif
+#elif (MEM_METHOD==MEM_MALLOC)
+	for (i=0 ; i<MULTITHREAD; i++) {
+		ee_s32 malloc_override=get_seed(7);
+		if (malloc_override != 0) 
+			results[i].size=malloc_override;
+		else
+			results[i].size=TOTAL_DATA_SIZE;
+		results[i].memblock[0]=portable_malloc(results[i].size);
+		results[i].seed1=results[0].seed1;
+		results[i].seed2=results[0].seed2;
+		results[i].seed3=results[0].seed3;
+		results[i].err=0;
+		results[i].execs=results[0].execs;
+	}
+#elif (MEM_METHOD==MEM_STACK)
+	for (i=0 ; i<MULTITHREAD; i++) {
+		results[i].memblock[0]=stack_memblock+i*TOTAL_DATA_SIZE;
+		results[i].size=TOTAL_DATA_SIZE;
+		results[i].seed1=results[0].seed1;
+		results[i].seed2=results[0].seed2;
+		results[i].seed3=results[0].seed3;
+		results[i].err=0;
+		results[i].execs=results[0].execs;
+	}
+#else
+#error "Please define a way to initialize a memory block."
+#endif
+	/* Data init */ 
+	/* Find out how space much we have based on number of algorithms */
+	for (i=0; i<NUM_ALGORITHMS; i++) {
+		if ((1<<(ee_u32)i) & results[0].execs)
+			num_algorithms++;
+	}
+	for (i=0 ; i<MULTITHREAD; i++) 
+		results[i].size=results[i].size/num_algorithms;
+	/* Assign pointers */
+	for (i=0; i<NUM_ALGORITHMS; i++) {
+		ee_u32 ctx;
+		if ((1<<(ee_u32)i) & results[0].execs) {
+			for (ctx=0 ; ctx<MULTITHREAD; ctx++)
+				results[ctx].memblock[i+1]=(char *)(results[ctx].memblock[0])+results[0].size*j;
+			j++;
+		}
+	}
+	/* call inits */
+	for (i=0 ; i<MULTITHREAD; i++) {
+		if (results[i].execs & ID_LIST) {
+			results[i].list=core_list_init(results[0].size,results[i].memblock[1],results[i].seed1);
+		}
+		if (results[i].execs & ID_MATRIX) {
+			core_init_matrix(results[0].size, results[i].memblock[2], (ee_s32)results[i].seed1 | (((ee_s32)results[i].seed2) << 16), &(results[i].mat) );
+		}
+		if (results[i].execs & ID_STATE) {
+			core_init_state(results[0].size,results[i].seed1,results[i].memblock[3]);
+		}
+	}
+	
+	/* automatically determine number of iterations if not set */
+	if (results[0].iterations==0) { 
+		secs_ret secs_passed=0;
+		ee_u32 divisor;
+		results[0].iterations=1;
+		while (secs_passed < (secs_ret)1) {
+			results[0].iterations*=10;
+			start_time();
+			iterate(&results[0]);
+			stop_time();
+			secs_passed=time_in_secs(get_time());
+		}
+		/* now we know it executes for at least 1 sec, set actual run time at about 10 secs */
+		divisor=(ee_u32)secs_passed;
+		if (divisor==0) /* some machines cast float to int as 0 since this conversion is not defined by ANSI, but we know at least one second passed */
+			divisor=1;
+		results[0].iterations*=1+10/divisor;
+	}
+	/* perform actual benchmark */
+	start_time();
+#if (MULTITHREAD>1)
+	if (default_num_contexts>MULTITHREAD) {
+		default_num_contexts=MULTITHREAD;
+	}
+	for (i=0 ; i<default_num_contexts; i++) {
+		results[i].iterations=results[0].iterations;
+		results[i].execs=results[0].execs;
+		core_start_parallel(&results[i]);
+	}
+	for (i=0 ; i<default_num_contexts; i++) {
+		core_stop_parallel(&results[i]);
+	}
+#else
+	iterate(&results[0]);
+#endif
+	stop_time();
+	total_time=get_time();
+	/* get a function of the input to report */
+	seedcrc=crc16(results[0].seed1,seedcrc);
+	seedcrc=crc16(results[0].seed2,seedcrc);
+	seedcrc=crc16(results[0].seed3,seedcrc);
+	seedcrc=crc16(results[0].size,seedcrc);
+	
+	switch (seedcrc) { /* test known output for common seeds */
+		case 0x8a02: /* seed1=0, seed2=0, seed3=0x66, size 2000 per algorithm */
+			known_id=0;
+			ee_printf("6k performance run parameters for coremark.\n");
+			break;
+		case 0x7b05: /*  seed1=0x3415, seed2=0x3415, seed3=0x66, size 2000 per algorithm */
+			known_id=1;
+			ee_printf("6k validation run parameters for coremark.\n");
+			break;
+		case 0x4eaf: /* seed1=0x8, seed2=0x8, seed3=0x8, size 400 per algorithm */
+			known_id=2;
+			ee_printf("Profile generation run parameters for coremark.\n");
+			break;
+		case 0xe9f5: /* seed1=0, seed2=0, seed3=0x66, size 666 per algorithm */
+			known_id=3;
+			ee_printf("2K performance run parameters for coremark.\n");
+			break;
+		case 0x18f2: /*  seed1=0x3415, seed2=0x3415, seed3=0x66, size 666 per algorithm */
+			known_id=4;
+			ee_printf("2K validation run parameters for coremark.\n");
+			break;
+		default:
+			total_errors=-1;
+			break;
+	}
+	if (known_id>=0) {
+		for (i=0 ; i<default_num_contexts; i++) {
+			results[i].err=0;
+			if ((results[i].execs & ID_LIST) && 
+				(results[i].crclist!=list_known_crc[known_id])) {
+				ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n",i,results[i].crclist,list_known_crc[known_id]);
+				results[i].err++;
+			}
+			if ((results[i].execs & ID_MATRIX) &&
+				(results[i].crcmatrix!=matrix_known_crc[known_id])) {
+				ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n",i,results[i].crcmatrix,matrix_known_crc[known_id]);
+				results[i].err++;
+			}
+			if ((results[i].execs & ID_STATE) &&
+				(results[i].crcstate!=state_known_crc[known_id])) {
+				ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n",i,results[i].crcstate,state_known_crc[known_id]);
+				results[i].err++;
+			}
+			total_errors+=results[i].err;
+		}
+	}
+	total_errors+=check_data_types();
+	/* and report results */
+	ee_printf("CoreMark Size    : %lu\n", (long unsigned) results[0].size);
+	ee_printf("Total ticks      : %lu\n", (long unsigned) total_time);
+#if HAS_FLOAT
+	ee_printf("Total time (secs): %f\n",time_in_secs(total_time));
+	if (time_in_secs(total_time) > 0)
+		ee_printf("Iterations/Sec   : %f\n",default_num_contexts*results[0].iterations/time_in_secs(total_time));
+#else 
+	ee_printf("Total time (secs): %d\n",time_in_secs(total_time));
+	if (time_in_secs(total_time) > 0)
+		ee_printf("Iterations/Sec   : %d\n",default_num_contexts*results[0].iterations/time_in_secs(total_time));
+#endif
+	if (time_in_secs(total_time) < 10) {
+		ee_printf("ERROR! Must execute for at least 10 secs for a valid result!\n");
+		total_errors++;
+	}
+
+	ee_printf("Iterations       : %lu\n", (long unsigned) default_num_contexts*results[0].iterations);
+	ee_printf("Compiler version : %s\n",COMPILER_VERSION);
+	ee_printf("Compiler flags   : %s\n",COMPILER_FLAGS);
+#if (MULTITHREAD>1)
+	ee_printf("Parallel %s : %d\n",PARALLEL_METHOD,default_num_contexts);
+#endif
+	ee_printf("Memory location  : %s\n",MEM_LOCATION);
+	/* output for verification */
+	ee_printf("seedcrc          : 0x%04x\n",seedcrc);
+	if (results[0].execs & ID_LIST)
+		for (i=0 ; i<default_num_contexts; i++) 
+			ee_printf("[%d]crclist       : 0x%04x\n",i,results[i].crclist);
+	if (results[0].execs & ID_MATRIX) 
+		for (i=0 ; i<default_num_contexts; i++) 
+			ee_printf("[%d]crcmatrix     : 0x%04x\n",i,results[i].crcmatrix);
+	if (results[0].execs & ID_STATE)
+		for (i=0 ; i<default_num_contexts; i++) 
+			ee_printf("[%d]crcstate      : 0x%04x\n",i,results[i].crcstate);
+	for (i=0 ; i<default_num_contexts; i++) 
+		ee_printf("[%d]crcfinal      : 0x%04x\n",i,results[i].crc);
+	if (total_errors==0) {
+		ee_printf("Correct operation validated. See README.md for run and reporting rules.\n");
+#if HAS_FLOAT
+		if (known_id==3) {
+			ee_printf("CoreMark 1.0 : %f / %s %s",default_num_contexts*results[0].iterations/time_in_secs(total_time),COMPILER_VERSION,COMPILER_FLAGS);
+#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC)
+			ee_printf(" / %s",MEM_LOCATION);
+#else
+			ee_printf(" / %s",mem_name[MEM_METHOD]);
+#endif
+
+#if (MULTITHREAD>1)
+			ee_printf(" / %d:%s",default_num_contexts,PARALLEL_METHOD);
+#endif
+			ee_printf("\n");
+		}
+#endif
+	}
+	if (total_errors>0)
+		ee_printf("Errors detected\n");
+	if (total_errors<0)
+		ee_printf("Cannot validate operation for these seed values, please compare with results on a known platform.\n");
+
+#if (MEM_METHOD==MEM_MALLOC)
+	for (i=0 ; i<MULTITHREAD; i++) 
+		portable_free(results[i].memblock[0]);
+#endif
+	/* And last call any target specific code for finalizing */
+	portable_fini(&(results[0].port));
+
+	return MAIN_RETURN_VAL;	
+}
+
+
diff --git a/tests/performance/coremark/core_matrix.c b/tests/performance/coremark/core_matrix.c
new file mode 100644
index 00000000000..ebfa1d7e5b3
--- /dev/null
+++ b/tests/performance/coremark/core_matrix.c
@@ -0,0 +1,308 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/*
+Topic: Description
+	Matrix manipulation benchmark
+	
+	This very simple algorithm forms the basis of many more complex algorithms. 
+	
+	The tight inner loop is the focus of many optimizations (compiler as well as hardware based) 
+	and is thus relevant for embedded processing. 
+	
+	The total available data space will be divided to 3 parts:
+	NxN Matrix A - initialized with small values (upper 3/4 of the bits all zero).
+	NxN Matrix B - initialized with medium values (upper half of the bits all zero).
+	NxN Matrix C - used for the result.
+
+	The actual values for A and B must be derived based on input that is not available at compile time.
+*/
+ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val);
+ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval);
+void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val);
+void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B);
+void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val);
+
+#define matrix_test_next(x) (x+1)
+#define matrix_clip(x,y) ((y) ? (x) & 0x0ff : (x) & 0x0ffff)
+#define matrix_big(x) (0xf000 | (x))
+#define bit_extract(x,from,to) (((x)>>(from)) & (~(0xffffffff << (to))))
+
+#if CORE_DEBUG
+void printmat(MATDAT *A, ee_u32 N, char *name) {
+	ee_u32 i,j;
+	ee_printf("Matrix %s [%dx%d]:\n",name,N,N);
+	for (i=0; i<N; i++) {
+		for (j=0; j<N; j++) {
+			if (j!=0)
+				ee_printf(",");
+			ee_printf("%d",A[i*N+j]);
+		}
+		ee_printf("\n");
+	}
+}
+void printmatC(MATRES *C, ee_u32 N, char *name) {
+	ee_u32 i,j;
+	ee_printf("Matrix %s [%dx%d]:\n",name,N,N);
+	for (i=0; i<N; i++) {
+		for (j=0; j<N; j++) {
+			if (j!=0)
+				ee_printf(",");
+			ee_printf("%d",C[i*N+j]);
+		}
+		ee_printf("\n");
+	}
+}
+#endif
+/* Function: core_bench_matrix
+	Benchmark function
+
+	Iterate <matrix_test> N times, 
+	changing the matrix values slightly by a constant amount each time.
+*/
+ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc) {
+	ee_u32 N=p->N;
+	MATRES *C=p->C;
+	MATDAT *A=p->A;
+	MATDAT *B=p->B;
+	MATDAT val=(MATDAT)seed;
+
+	crc=crc16(matrix_test(N,C,A,B,val),crc);
+
+	return crc;
+}
+
+/* Function: matrix_test
+	Perform matrix manipulation.
+
+	Parameters:
+	N - Dimensions of the matrix.
+	C - memory for result matrix.
+	A - input matrix
+	B - operator matrix (not changed during operations)
+
+	Returns:
+	A CRC value that captures all results calculated in the function.
+	In particular, crc of the value calculated on the result matrix 
+	after each step by <matrix_sum>.
+
+	Operation:
+	
+	1 - Add a constant value to all elements of a matrix.
+	2 - Multiply a matrix by a constant.
+	3 - Multiply a matrix by a vector.
+	4 - Multiply a matrix by a matrix.
+	5 - Add a constant value to all elements of a matrix.
+
+	After the last step, matrix A is back to original contents.
+*/
+ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val) {
+	ee_u16 crc=0;
+	MATDAT clipval=matrix_big(val);
+
+	matrix_add_const(N,A,val); /* make sure data changes  */
+#if CORE_DEBUG
+	printmat(A,N,"matrix_add_const");
+#endif
+	matrix_mul_const(N,C,A,val);
+	crc=crc16(matrix_sum(N,C,clipval),crc);
+#if CORE_DEBUG
+	printmatC(C,N,"matrix_mul_const");
+#endif
+	matrix_mul_vect(N,C,A,B);
+	crc=crc16(matrix_sum(N,C,clipval),crc);
+#if CORE_DEBUG
+	printmatC(C,N,"matrix_mul_vect");
+#endif
+	matrix_mul_matrix(N,C,A,B);
+	crc=crc16(matrix_sum(N,C,clipval),crc);
+#if CORE_DEBUG
+	printmatC(C,N,"matrix_mul_matrix");
+#endif
+	matrix_mul_matrix_bitextract(N,C,A,B);
+	crc=crc16(matrix_sum(N,C,clipval),crc);
+#if CORE_DEBUG
+	printmatC(C,N,"matrix_mul_matrix_bitextract");
+#endif
+	
+	matrix_add_const(N,A,-val); /* return matrix to initial value */
+	return crc;
+}
+
+/* Function : matrix_init
+	Initialize the memory block for matrix benchmarking.
+
+	Parameters:
+	blksize - Size of memory to be initialized.
+	memblk - Pointer to memory block.
+	seed - Actual values chosen depend on the seed parameter.
+	p - pointers to <mat_params> containing initialized matrixes.
+
+	Returns:
+	Matrix dimensions.
+	
+	Note:
+	The seed parameter MUST be supplied from a source that cannot be determined at compile time
+*/
+ee_u32 core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p) {
+	ee_u32 N=0;
+	MATDAT *A;
+	MATDAT *B;
+	ee_s32 order=1;
+	MATDAT val;
+	ee_u32 i=0,j=0;
+	if (seed==0)
+		seed=1;
+	while (j<blksize) {
+		i++;
+		j=i*i*2*4;		
+	}
+	N=i-1;
+	A=(MATDAT *)align_mem(memblk);
+	B=A+N*N;
+
+	for (i=0; i<N; i++) {
+		for (j=0; j<N; j++) {
+			seed = ( ( order * seed ) % 65536 );
+			val = (seed + order);
+			val=matrix_clip(val,0);
+			B[i*N+j] = val;
+			val =  (val + order);
+			val=matrix_clip(val,1);
+			A[i*N+j] = val;
+			order++;
+		}
+	}
+
+	p->A=A;
+	p->B=B;
+	p->C=(MATRES *)align_mem(B+N*N);
+	p->N=N;
+#if CORE_DEBUG
+	printmat(A,N,"A");
+	printmat(B,N,"B");
+#endif
+	return N;
+}
+
+/* Function: matrix_sum
+	Calculate a function that depends on the values of elements in the matrix.
+
+	For each element, accumulate into a temporary variable.
+	
+	As long as this value is under the parameter clipval, 
+	add 1 to the result if the element is bigger then the previous.
+	
+	Otherwise, reset the accumulator and add 10 to the result.
+*/
+ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) {
+	MATRES tmp=0,prev=0,cur=0;
+	ee_s16 ret=0;
+	ee_u32 i,j;
+	for (i=0; i<N; i++) {
+		for (j=0; j<N; j++) {
+			cur=C[i*N+j];
+			tmp+=cur;
+			if (tmp>clipval) {
+				ret+=10;
+				tmp=0;
+			} else {
+				ret += (cur>prev) ? 1 : 0;
+			}
+			prev=cur;
+		}
+	}
+	return ret;
+}
+
+/* Function: matrix_mul_const
+	Multiply a matrix by a constant.
+	This could be used as a scaler for instance.
+*/
+void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) {
+	ee_u32 i,j;
+	for (i=0; i<N; i++) {
+		for (j=0; j<N; j++) {
+			C[i*N+j]=(MATRES)A[i*N+j] * (MATRES)val;
+		}
+	}
+}
+
+/* Function: matrix_add_const
+	Add a constant value to all elements of a matrix.
+*/
+void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val) {
+	ee_u32 i,j;
+	for (i=0; i<N; i++) {
+		for (j=0; j<N; j++) {
+			A[i*N+j] += val;
+		}
+	}
+}
+
+/* Function: matrix_mul_vect
+	Multiply a matrix by a vector.
+	This is common in many simple filters (e.g. fir where a vector of coefficients is applied to the matrix.)
+*/
+void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) {
+	ee_u32 i,j;
+	for (i=0; i<N; i++) {
+		C[i]=0;
+		for (j=0; j<N; j++) {
+			C[i]+=(MATRES)A[i*N+j] * (MATRES)B[j];
+		}
+	}
+}
+
+/* Function: matrix_mul_matrix
+	Multiply a matrix by a matrix.
+	Basic code is used in many algorithms, mostly with minor changes such as scaling.
+*/
+void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) {
+	ee_u32 i,j,k;
+	for (i=0; i<N; i++) {
+		for (j=0; j<N; j++) {
+			C[i*N+j]=0;
+			for(k=0;k<N;k++)
+			{
+				C[i*N+j]+=(MATRES)A[i*N+k] * (MATRES)B[k*N+j];
+			}
+		}
+	}
+}
+
+/* Function: matrix_mul_matrix_bitextract
+	Multiply a matrix by a matrix, and extract some bits from the result.
+	Basic code is used in many algorithms, mostly with minor changes such as scaling.
+*/
+void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) {
+	ee_u32 i,j,k;
+	for (i=0; i<N; i++) {
+		for (j=0; j<N; j++) {
+			C[i*N+j]=0;
+			for(k=0;k<N;k++)
+			{
+				MATRES tmp=(MATRES)A[i*N+k] * (MATRES)B[k*N+j];
+				C[i*N+j]+=bit_extract(tmp,2,4)*bit_extract(tmp,5,7);
+			}
+		}
+	}
+}
diff --git a/tests/performance/coremark/core_portme.c b/tests/performance/coremark/core_portme.c
new file mode 100644
index 00000000000..198d75dfec4
--- /dev/null
+++ b/tests/performance/coremark/core_portme.c
@@ -0,0 +1,168 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+#include "coremark.h"
+#include "core_portme.h"
+
+extern uint32_t Arduino_millis();
+
+#if (MULTITHREAD > 1)
+static uint8_t next_core = 0;
+#endif
+
+#if VALIDATION_RUN
+	volatile ee_s32 seed1_volatile=0x3415;
+	volatile ee_s32 seed2_volatile=0x3415;
+	volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PERFORMANCE_RUN
+	volatile ee_s32 seed1_volatile=0x0;
+	volatile ee_s32 seed2_volatile=0x0;
+	volatile ee_s32 seed3_volatile=0x66;
+#endif
+#if PROFILE_RUN
+	volatile ee_s32 seed1_volatile=0x8;
+	volatile ee_s32 seed2_volatile=0x8;
+	volatile ee_s32 seed3_volatile=0x8;
+#endif
+	volatile ee_s32 seed4_volatile=ITERATIONS;
+	volatile ee_s32 seed5_volatile=0;
+/* Porting : Timing functions
+	How to capture time and convert to seconds must be ported to whatever is supported by the platform.
+	e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc.
+	Sample implementation for standard time.h and windows.h definitions included.
+*/
+CORETIMETYPE barebones_clock() {
+	return Arduino_millis();
+}
+/* Define : TIMER_RES_DIVIDER
+	Divider to trade off timer resolution and total time that can be measured.
+
+	Use lower values to increase resolution, but make sure that overflow does not occur.
+	If there are issues with the return value overflowing, increase this value.
+	*/
+#define CLOCKS_PER_SEC 1000.0
+#define TIMER_RES_DIVIDER 1
+
+#define GETMYTIME(_t) (*_t=barebones_clock())
+#define MYTIMEDIFF(fin,ini) ((fin)-(ini))
+#define TIMER_RES_DIVIDER 1
+#define SAMPLE_TIME_IMPLEMENTATION 1
+#define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER)
+
+/** Define Host specific (POSIX), or target specific global time variables. */
+static CORETIMETYPE start_time_val, stop_time_val;
+
+/* Function : start_time
+	This function will be called right before starting the timed portion of the benchmark.
+
+	Implementation may be capturing a system timer (as implemented in the example code)
+	or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.
+*/
+void start_time(void) {
+	GETMYTIME(&start_time_val );
+}
+/* Function : stop_time
+	This function will be called right after ending the timed portion of the benchmark.
+
+	Implementation may be capturing a system timer (as implemented in the example code)
+	or other system parameters - e.g. reading the current value of cpu cycles counter.
+*/
+void stop_time(void) {
+	GETMYTIME(&stop_time_val );
+}
+/* Function : get_time
+	Return an abstract "ticks" number that signifies time on the system.
+
+	Actual value returned may be cpu cycles, milliseconds or any other value,
+	as long as it can be converted to seconds by <time_in_secs>.
+	This methodology is taken to accomodate any hardware or simulated platform.
+	The sample implementation returns millisecs by default,
+	and the resolution is controlled by <TIMER_RES_DIVIDER>
+*/
+CORE_TICKS get_time(void) {
+	CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val));
+	return elapsed;
+}
+/* Function : time_in_secs
+	Convert the value returned by get_time to seconds.
+
+	The <secs_ret> type is used to accomodate systems with no support for floating point.
+	Default implementation implemented by the EE_TICKS_PER_SEC macro above.
+*/
+secs_ret time_in_secs(CORE_TICKS ticks) {
+	secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC;
+	return retval;
+}
+
+ee_u32 default_num_contexts = MULTITHREAD;
+
+/* Function : portable_init
+	Target specific initialization code
+	Test for some common mistakes.
+*/
+void portable_init(core_portable *p, int *argc, char *argv[])
+{
+	// Serial.begin(9600);
+	// #error "Call board initialization routines in portable init (if needed), in particular initialize UART!\n"
+	if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) {
+		ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n");
+	}
+	if (sizeof(ee_u32) != 4) {
+		ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n");
+	}
+	p->portable_id=1;
+}
+/* Function : portable_fini
+	Target specific final code
+*/
+void portable_fini(core_portable *p)
+{
+	p->portable_id=0;
+}
+
+void iterate_task(void *arg)
+{
+  iterate(arg);
+  vTaskDelete(NULL);
+}
+
+#if (MULTITHREAD > 1)
+ee_u8 core_start_parallel(core_results *res)
+{
+    int ret;
+    res->port.task = NULL;
+    ret = xTaskCreatePinnedToCore(iterate_task,      /* Function to implement the task */
+                                  "CoreMarkTask",    /* Name of the task */
+                                  10000,             /* Stack size in words */
+                                  (void *)res,       /* Task input parameter */
+                                  20,                /* Priority of the task */
+                                  &(res->port.task), /* Task handle */
+                                  next_core);        /* Core where the task should run */
+
+    next_core = (next_core + 1) % MULTITHREAD;
+    return (ee_u8) ret;
+}
+
+ee_u8 core_stop_parallel(core_results *res)
+{
+    while (eTaskGetState(res->port.task) != eDeleted);
+    res->port.task = NULL;
+    return 0;
+}
+#endif
+
diff --git a/tests/performance/coremark/core_portme.h b/tests/performance/coremark/core_portme.h
new file mode 100644
index 00000000000..9511aafba68
--- /dev/null
+++ b/tests/performance/coremark/core_portme.h
@@ -0,0 +1,217 @@
+#include "Arduino.h"
+#include <stdint.h>
+#include <stdio.h>
+
+// a minor hack to rename the main function, so we can call it from C++
+#define main(ignore) coremark_main(void)
+
+#define FLAGS_STR "(flags unknown)"
+
+#define PERFORMANCE_RUN 1
+
+// 0 means auto-detect number of iterations for 10 second test
+#define ITERATIONS 0
+
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+/* Topic : Description
+	This file contains configuration constants required to execute on different platforms
+*/
+#ifndef CORE_PORTME_H
+#define CORE_PORTME_H
+/************************/
+/* Data types and settings */
+/************************/
+/* Configuration : HAS_FLOAT
+	Define to 1 if the platform supports floating point.
+*/
+#ifndef HAS_FLOAT
+#define HAS_FLOAT 1
+#endif
+/* Configuration : HAS_TIME_H
+	Define to 1 if platform has the time.h header file,
+	and implementation of functions thereof.
+*/
+#ifndef HAS_TIME_H
+#define HAS_TIME_H 0
+#endif
+/* Configuration : USE_CLOCK
+	Define to 1 if platform has the time.h header file,
+	and implementation of functions thereof.
+*/
+#ifndef USE_CLOCK
+#define USE_CLOCK 0
+#endif
+/* Configuration : HAS_STDIO
+	Define to 1 if the platform has stdio.h.
+*/
+#ifndef HAS_STDIO
+#define HAS_STDIO 1
+#endif
+/* Configuration : HAS_PRINTF
+	Define to 1 if the platform has stdio.h and implements the printf function.
+*/
+#ifndef HAS_PRINTF
+#define HAS_PRINTF 0
+#endif
+
+
+/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION
+	Initialize these strings per platform
+*/
+#ifndef COMPILER_VERSION
+ #ifdef __GNUC__
+ #define COMPILER_VERSION "GCC"__VERSION__
+ #else
+ #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)"
+ #endif
+#endif
+#ifndef COMPILER_FLAGS
+ #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */
+#endif
+#ifndef MEM_LOCATION
+ #define MEM_LOCATION "STACK"
+#endif
+
+/* Data Types :
+	To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>.
+
+	*Imprtant* :
+	ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!!
+*/
+typedef int16_t  ee_s16;
+typedef uint16_t ee_u16;
+typedef int32_t  ee_s32;
+typedef double   ee_f32;
+typedef uint8_t  ee_u8;
+typedef uint32_t ee_u32;
+typedef uintptr_t ee_ptr_int;
+typedef size_t ee_size_t;
+#define NULL ((void *)0)
+/* align_mem :
+	This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks.
+*/
+#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3))
+
+/* Configuration : CORE_TICKS
+	Define type of return from the timing functions.
+ */
+#define CORETIMETYPE ee_u32
+typedef ee_u32 CORE_TICKS;
+
+/* Configuration : SEED_METHOD
+	Defines method to get seed values that cannot be computed at compile time.
+
+	Valid values :
+	SEED_ARG - from command line.
+	SEED_FUNC - from a system function.
+	SEED_VOLATILE - from volatile variables.
+*/
+#ifndef SEED_METHOD
+#define SEED_METHOD SEED_VOLATILE
+#endif
+
+/* Configuration : MEM_METHOD
+	Defines method to get a block of memry.
+
+	Valid values :
+	MEM_MALLOC - for platforms that implement malloc and have malloc.h.
+	MEM_STATIC - to use a static memory array.
+	MEM_STACK - to allocate the data block on the stack (NYI).
+*/
+#ifndef MEM_METHOD
+#define MEM_METHOD MEM_STACK
+#endif
+
+/* Configuration : MULTITHREAD
+	Define for parallel execution
+
+	Valid values :
+	1 - only one context (default).
+	N>1 - will execute N copies in parallel.
+
+	Note :
+	If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.
+
+	Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them.
+
+	It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>,
+	to fit a particular architecture.
+*/
+#ifndef MULTITHREAD
+#define MULTITHREAD CONFIG_SOC_CPU_CORES_NUM
+#define PARALLEL_METHOD "FreeRTOS"
+#define USE_PTHREAD 0
+#define USE_FORK 0
+#define USE_SOCKET 0
+#endif
+
+/* Configuration : MAIN_HAS_NOARGC
+	Needed if platform does not support getting arguments to main.
+
+	Valid values :
+	0 - argc/argv to main is supported
+	1 - argc/argv to main is not supported
+
+	Note :
+	This flag only matters if MULTITHREAD has been defined to a value greater then 1.
+*/
+#ifndef MAIN_HAS_NOARGC
+#define MAIN_HAS_NOARGC 1
+#endif
+
+/* Configuration : MAIN_HAS_NORETURN
+	Needed if platform does not support returning a value from main.
+
+	Valid values :
+	0 - main returns an int, and return value will be 0.
+	1 - platform does not support returning a value from main
+*/
+#ifndef MAIN_HAS_NORETURN
+#define MAIN_HAS_NORETURN 0
+#endif
+
+/* Variable : default_num_contexts
+	Not used for this simple port, must cintain the value 1.
+*/
+extern ee_u32 default_num_contexts;
+
+typedef struct CORE_PORTABLE_S {
+#if (MULTITHREAD > 1)
+  TaskHandle_t task;
+#endif
+	ee_u8	portable_id;
+} core_portable;
+
+/* target specific init/fini */
+void portable_init(core_portable *p, int *argc, char *argv[]);
+void portable_fini(core_portable *p);
+
+#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN)
+#if (TOTAL_DATA_SIZE==1200)
+#define PROFILE_RUN 1
+#elif (TOTAL_DATA_SIZE==2000)
+#define PERFORMANCE_RUN 1
+#else
+#define VALIDATION_RUN 1
+#endif
+#endif
+
+int ee_printf(const char *fmt, ...);
+
+#endif /* CORE_PORTME_H */
diff --git a/tests/performance/coremark/core_state.c b/tests/performance/coremark/core_state.c
new file mode 100644
index 00000000000..bb3193308bd
--- /dev/null
+++ b/tests/performance/coremark/core_state.c
@@ -0,0 +1,277 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/* local functions */
+enum CORE_STATE core_state_transition( ee_u8 **instr , ee_u32 *transition_count);
+
+/*
+Topic: Description
+	Simple state machines like this one are used in many embedded products.
+	
+	For more complex state machines, sometimes a state transition table implementation is used instead, 
+	trading speed of direct coding for ease of maintenance.
+	
+	Since the main goal of using a state machine in CoreMark is to excercise the switch/if behaviour,
+	we are using a small moore machine. 
+	
+	In particular, this machine tests type of string input,
+	trying to determine whether the input is a number or something else.
+	(see core_state.png).
+*/
+
+/* Function: core_bench_state
+	Benchmark function
+
+	Go over the input twice, once direct, and once after introducing some corruption. 
+*/
+ee_u16 core_bench_state(ee_u32 blksize, ee_u8 *memblock, 
+		ee_s16 seed1, ee_s16 seed2, ee_s16 step, ee_u16 crc) 
+{
+	ee_u32 final_counts[NUM_CORE_STATES];
+	ee_u32 track_counts[NUM_CORE_STATES];
+	ee_u8 *p=memblock;
+	ee_u32 i;
+
+
+#if CORE_DEBUG
+	ee_printf("State Bench: %d,%d,%d,%04x\n",seed1,seed2,step,crc);
+#endif
+	for (i=0; i<NUM_CORE_STATES; i++) {
+		final_counts[i]=track_counts[i]=0;
+	}
+	/* run the state machine over the input */
+	while (*p!=0) {
+		enum CORE_STATE fstate=core_state_transition(&p,track_counts);
+		final_counts[fstate]++;
+#if CORE_DEBUG
+	ee_printf("%d,",fstate);
+	}
+	ee_printf("\n");
+#else
+	}
+#endif
+	p=memblock;
+	while (p < (memblock+blksize)) { /* insert some corruption */
+		if (*p!=',')
+			*p^=(ee_u8)seed1;
+		p+=step;
+	}
+	p=memblock;
+	/* run the state machine over the input again */
+	while (*p!=0) {
+		enum CORE_STATE fstate=core_state_transition(&p,track_counts);
+		final_counts[fstate]++;
+#if CORE_DEBUG
+	ee_printf("%d,",fstate);
+	}
+	ee_printf("\n");
+#else
+	}
+#endif
+	p=memblock;
+	while (p < (memblock+blksize)) { /* undo corruption is seed1 and seed2 are equal */
+		if (*p!=',')
+			*p^=(ee_u8)seed2;
+		p+=step;
+	}
+	/* end timing */
+	for (i=0; i<NUM_CORE_STATES; i++) {
+		crc=crcu32(final_counts[i],crc);
+		crc=crcu32(track_counts[i],crc);
+	}
+	return crc;
+}
+
+/* Default initialization patterns */
+static ee_u8 *intpat[4]  ={(ee_u8 *)"5012",(ee_u8 *)"1234",(ee_u8 *)"-874",(ee_u8 *)"+122"};
+static ee_u8 *floatpat[4]={(ee_u8 *)"35.54400",(ee_u8 *)".1234500",(ee_u8 *)"-110.700",(ee_u8 *)"+0.64400"};
+static ee_u8 *scipat[4]  ={(ee_u8 *)"5.500e+3",(ee_u8 *)"-.123e-2",(ee_u8 *)"-87e+832",(ee_u8 *)"+0.6e-12"};
+static ee_u8 *errpat[4]  ={(ee_u8 *)"T0.3e-1F",(ee_u8 *)"-T.T++Tq",(ee_u8 *)"1T3.4e4z",(ee_u8 *)"34.0e-T^"};
+
+/* Function: core_init_state
+	Initialize the input data for the state machine.
+
+	Populate the input with several predetermined strings, interspersed.
+	Actual patterns chosen depend on the seed parameter.
+	
+	Note:
+	The seed parameter MUST be supplied from a source that cannot be determined at compile time
+*/
+void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p) {
+	ee_u32 total=0,next=0,i;
+	ee_u8 *buf=0;
+#if CORE_DEBUG
+	ee_u8 *start=p;
+	ee_printf("State: %d,%d\n",size,seed);
+#endif
+	size--;
+	next=0;
+	while ((total+next+1)<size) {
+		if (next>0) {
+			for(i=0;i<next;i++)
+				*(p+total+i)=buf[i];
+			*(p+total+i)=',';
+			total+=next+1;
+		}
+		seed++;
+		switch (seed & 0x7) {
+			case 0: /* int */
+			case 1: /* int */
+			case 2: /* int */
+				buf=intpat[(seed>>3) & 0x3];
+				next=4;
+			break;
+			case 3: /* float */
+			case 4: /* float */
+				buf=floatpat[(seed>>3) & 0x3];
+				next=8;
+			break;
+			case 5: /* scientific */
+			case 6: /* scientific */
+				buf=scipat[(seed>>3) & 0x3];
+				next=8;
+			break;
+			case 7: /* invalid */
+				buf=errpat[(seed>>3) & 0x3];
+				next=8;
+			break;
+			default: /* Never happen, just to make some compilers happy */
+			break;
+		}
+	}
+	size++;
+	while (total<size) { /* fill the rest with 0 */
+		*(p+total)=0;
+		total++;
+	}
+#if CORE_DEBUG
+	ee_printf("State Input: %s\n",start);
+#endif
+}
+
+static ee_u8 ee_isdigit(ee_u8 c) {
+	ee_u8 retval;
+	retval = ((c>='0') & (c<='9')) ? 1 : 0;
+	return retval;
+}
+
+/* Function: core_state_transition
+	Actual state machine.
+
+	The state machine will continue scanning until either:
+	1 - an invalid input is detcted.
+	2 - a valid number has been detected.
+	
+	The input pointer is updated to point to the end of the token, and the end state is returned (either specific format determined or invalid).
+*/
+
+enum CORE_STATE core_state_transition( ee_u8 **instr , ee_u32 *transition_count) {
+	ee_u8 *str=*instr;
+	ee_u8 NEXT_SYMBOL;
+	enum CORE_STATE state=CORE_START;
+	for( ; *str && state != CORE_INVALID; str++ ) {
+		NEXT_SYMBOL = *str;
+		if (NEXT_SYMBOL==',') /* end of this input */ {
+			str++;
+			break;
+		}
+		switch(state) {
+		case CORE_START:
+			if(ee_isdigit(NEXT_SYMBOL)) {
+				state = CORE_INT;
+			}
+			else if( NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-' ) {
+				state = CORE_S1;
+			}
+			else if( NEXT_SYMBOL == '.' ) {
+				state = CORE_FLOAT;
+			}
+			else {
+				state = CORE_INVALID;
+				transition_count[CORE_INVALID]++;
+			}
+			transition_count[CORE_START]++;
+			break;
+		case CORE_S1:
+			if(ee_isdigit(NEXT_SYMBOL)) {
+				state = CORE_INT;
+				transition_count[CORE_S1]++;
+			}
+			else if( NEXT_SYMBOL == '.' ) {
+				state = CORE_FLOAT;
+				transition_count[CORE_S1]++;
+			}
+			else {
+				state = CORE_INVALID;
+				transition_count[CORE_S1]++;
+			}
+			break;
+		case CORE_INT:
+			if( NEXT_SYMBOL == '.' ) {
+				state = CORE_FLOAT;
+				transition_count[CORE_INT]++;
+			}
+			else if(!ee_isdigit(NEXT_SYMBOL)) {
+				state = CORE_INVALID;
+				transition_count[CORE_INT]++;
+			}
+			break;
+		case CORE_FLOAT:
+			if( NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e' ) {
+				state = CORE_S2;
+				transition_count[CORE_FLOAT]++;
+			}
+			else if(!ee_isdigit(NEXT_SYMBOL)) {
+				state = CORE_INVALID;
+				transition_count[CORE_FLOAT]++;
+			}
+			break;
+		case CORE_S2:
+			if( NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-' ) {
+				state = CORE_EXPONENT;
+				transition_count[CORE_S2]++;
+			}
+			else {
+				state = CORE_INVALID;
+				transition_count[CORE_S2]++;
+			}
+			break;
+		case CORE_EXPONENT:
+			if(ee_isdigit(NEXT_SYMBOL)) {
+				state = CORE_SCIENTIFIC;
+				transition_count[CORE_EXPONENT]++;
+			}
+			else {
+				state = CORE_INVALID;
+				transition_count[CORE_EXPONENT]++;
+			}
+			break;
+		case CORE_SCIENTIFIC:
+			if(!ee_isdigit(NEXT_SYMBOL)) {
+				state = CORE_INVALID;
+				transition_count[CORE_INVALID]++;
+			}
+			break;
+		default:
+			break;
+		}
+	}
+	*instr=str;
+	return state;
+}
diff --git a/tests/performance/coremark/core_util.c b/tests/performance/coremark/core_util.c
new file mode 100644
index 00000000000..581adcc2426
--- /dev/null
+++ b/tests/performance/coremark/core_util.c
@@ -0,0 +1,210 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+#include "coremark.h"
+/* Function: get_seed
+	Get a values that cannot be determined at compile time.
+
+	Since different embedded systems and compilers are used, 3 different methods are provided:
+	1 - Using a volatile variable. This method is only valid if the compiler is forced to generate code that
+	reads the value of a volatile variable from memory at run time. 
+	Please note, if using this method, you would need to modify core_portme.c to generate training profile.
+	2 - Command line arguments. This is the preferred method if command line arguments are supported.
+	3 - System function. If none of the first 2 methods is available on the platform,
+	a system function which is not a stub can be used.
+	
+	e.g. read the value on GPIO pins connected to switches, or invoke special simulator functions.
+*/
+#if (SEED_METHOD==SEED_VOLATILE)
+	extern volatile ee_s32 seed1_volatile;
+	extern volatile ee_s32 seed2_volatile;
+	extern volatile ee_s32 seed3_volatile;
+	extern volatile ee_s32 seed4_volatile;
+	extern volatile ee_s32 seed5_volatile;
+	ee_s32 get_seed_32(int i) {
+		ee_s32 retval;
+		switch (i) {
+			case 1:
+				retval=seed1_volatile;
+				break;
+			case 2:
+				retval=seed2_volatile;
+				break;
+			case 3:
+				retval=seed3_volatile;
+				break;
+			case 4:
+				retval=seed4_volatile;
+				break;
+			case 5:
+				retval=seed5_volatile;
+				break;
+			default:
+				retval=0;
+				break;
+		}
+		return retval;
+	}
+#elif (SEED_METHOD==SEED_ARG)
+ee_s32 parseval(char *valstring) {
+	ee_s32 retval=0;
+	ee_s32 neg=1;
+	int hexmode=0;
+	if (*valstring == '-') {
+		neg=-1;
+		valstring++;
+	}
+	if ((valstring[0] == '0') && (valstring[1] == 'x')) {
+		hexmode=1;
+		valstring+=2;
+	}
+		/* first look for digits */
+	if (hexmode) {
+		while (((*valstring >= '0') && (*valstring <= '9')) || ((*valstring >= 'a') && (*valstring <= 'f'))) {
+			ee_s32 digit=*valstring-'0';
+			if (digit>9)
+				digit=10+*valstring-'a';
+			retval*=16;
+			retval+=digit;
+			valstring++;
+		}
+	} else {
+		while ((*valstring >= '0') && (*valstring <= '9')) {
+			ee_s32 digit=*valstring-'0';
+			retval*=10;
+			retval+=digit;
+			valstring++;
+		}
+	}
+	/* now add qualifiers */
+	if (*valstring=='K')
+		retval*=1024;
+	if (*valstring=='M')
+		retval*=1024*1024;
+
+	retval*=neg;
+	return retval;
+}
+
+ee_s32 get_seed_args(int i, int argc, char *argv[]) {
+	if (argc>i)
+		return parseval(argv[i]);
+	return 0;
+}
+
+#elif (SEED_METHOD==SEED_FUNC)
+/* If using OS based function, you must define and implement the functions below in core_portme.h and core_portme.c ! */
+ee_s32 get_seed_32(int i) {
+	ee_s32 retval;
+	switch (i) {
+		case 1:
+			retval=portme_sys1();
+			break;
+		case 2:
+			retval=portme_sys2();
+			break;
+		case 3:
+			retval=portme_sys3();
+			break;
+		case 4:
+			retval=portme_sys4();
+			break;
+		case 5:
+			retval=portme_sys5();
+			break;
+		default:
+			retval=0;
+			break;
+	}
+	return retval;
+}
+#endif
+
+/* Function: crc*
+	Service functions to calculate 16b CRC code.
+
+*/
+ee_u16 crcu8(ee_u8 data, ee_u16 crc )
+{
+	ee_u8 i=0,x16=0,carry=0;
+
+	for (i = 0; i < 8; i++)
+    {
+		x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1));
+		data >>= 1;
+
+		if (x16 == 1)
+		{
+		   crc ^= 0x4002;
+		   carry = 1;
+		}
+		else 
+			carry = 0;
+		crc >>= 1;
+		if (carry)
+		   crc |= 0x8000;
+		else
+		   crc &= 0x7fff;
+    }
+	return crc;
+} 
+ee_u16 crcu16(ee_u16 newval, ee_u16 crc) {
+	crc=crcu8( (ee_u8) (newval)				,crc);
+	crc=crcu8( (ee_u8) ((newval)>>8)	,crc);
+	return crc;
+}
+ee_u16 crcu32(ee_u32 newval, ee_u16 crc) {
+	crc=crc16((ee_s16) newval		,crc);
+	crc=crc16((ee_s16) (newval>>16)	,crc);
+	return crc;
+}
+ee_u16 crc16(ee_s16 newval, ee_u16 crc) {
+	return crcu16((ee_u16)newval, crc);
+}
+
+ee_u8 check_data_types() {
+	ee_u8 retval=0;
+	if (sizeof(ee_u8) != 1) {
+		ee_printf("ERROR: ee_u8 is not an 8b datatype!\n");
+		retval++;
+	}
+	if (sizeof(ee_u16) != 2) {
+		ee_printf("ERROR: ee_u16 is not a 16b datatype!\n");
+		retval++;
+	}
+	if (sizeof(ee_s16) != 2) {
+		ee_printf("ERROR: ee_s16 is not a 16b datatype!\n");
+		retval++;
+	}
+	if (sizeof(ee_s32) != 4) {
+		ee_printf("ERROR: ee_s32 is not a 32b datatype!\n");
+		retval++;
+	}
+	if (sizeof(ee_u32) != 4) {
+		ee_printf("ERROR: ee_u32 is not a 32b datatype!\n");
+		retval++;
+	}
+	if (sizeof(ee_ptr_int) != sizeof(int *)) {
+		ee_printf("ERROR: ee_ptr_int is not a datatype that holds an int pointer!\n");
+		retval++;
+	}
+	if (retval>0) {
+		ee_printf("ERROR: Please modify the datatypes in core_portme.h!\n");
+	}
+	return retval;
+}
diff --git a/tests/performance/coremark/coremark.h b/tests/performance/coremark/coremark.h
new file mode 100644
index 00000000000..dc9f8c7ae24
--- /dev/null
+++ b/tests/performance/coremark/coremark.h
@@ -0,0 +1,174 @@
+/*
+Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC)
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Original Author: Shay Gal-on
+*/
+
+/* Topic: Description
+	This file contains  declarations of the various benchmark functions.
+*/
+
+/* Configuration: TOTAL_DATA_SIZE
+	Define total size for data algorithms will operate on
+*/
+#ifndef TOTAL_DATA_SIZE 
+#define TOTAL_DATA_SIZE 2*1000
+#endif
+
+#define SEED_ARG 0
+#define SEED_FUNC 1
+#define SEED_VOLATILE 2
+
+#define MEM_STATIC 0
+#define MEM_MALLOC 1
+#define MEM_STACK 2
+
+#include "core_portme.h"
+
+#if HAS_STDIO
+#include <stdio.h>
+#endif
+#if HAS_PRINTF
+#define ee_printf printf
+#endif
+
+/* Actual benchmark execution in iterate */
+void *iterate(void *pres);
+
+/* Typedef: secs_ret
+	For machines that have floating point support, get number of seconds as a double. 
+	Otherwise an unsigned int.
+*/
+#if HAS_FLOAT
+typedef double secs_ret;
+#else
+typedef ee_u32 secs_ret;
+#endif
+
+#if MAIN_HAS_NORETURN
+#define MAIN_RETURN_VAL 
+#define MAIN_RETURN_TYPE void
+#else
+#define MAIN_RETURN_VAL 0
+#define MAIN_RETURN_TYPE int
+#endif 
+
+void start_time(void);
+void stop_time(void);
+CORE_TICKS get_time(void);
+secs_ret time_in_secs(CORE_TICKS ticks);
+
+/* Misc useful functions */
+ee_u16 crcu8(ee_u8 data, ee_u16 crc);
+ee_u16 crc16(ee_s16 newval, ee_u16 crc);
+ee_u16 crcu16(ee_u16 newval, ee_u16 crc);
+ee_u16 crcu32(ee_u32 newval, ee_u16 crc);
+ee_u8 check_data_types();
+void *portable_malloc(ee_size_t size);
+void portable_free(void *p);
+ee_s32 parseval(char *valstring);
+
+/* Algorithm IDS */
+#define ID_LIST 	(1<<0)
+#define ID_MATRIX 	(1<<1)
+#define ID_STATE 	(1<<2)
+#define ALL_ALGORITHMS_MASK (ID_LIST|ID_MATRIX|ID_STATE)
+#define NUM_ALGORITHMS 3
+
+/* list data structures */
+typedef struct list_data_s {
+	ee_s16 data16;
+	ee_s16 idx;
+} list_data;
+
+typedef struct list_head_s {
+	struct list_head_s *next;
+	struct list_data_s *info;
+} list_head;
+
+
+/*matrix benchmark related stuff */
+#define MATDAT_INT 1
+#if MATDAT_INT
+typedef ee_s16 MATDAT;
+typedef ee_s32 MATRES;
+#else
+typedef ee_f16 MATDAT;
+typedef ee_f32 MATRES;
+#endif
+
+typedef struct MAT_PARAMS_S {
+	int N;
+	MATDAT *A;
+	MATDAT *B;
+	MATRES *C;
+} mat_params;
+
+/* state machine related stuff */
+/* List of all the possible states for the FSM */
+typedef enum CORE_STATE {
+	CORE_START=0,
+	CORE_INVALID,
+	CORE_S1,
+	CORE_S2,
+	CORE_INT,
+	CORE_FLOAT,
+	CORE_EXPONENT,
+	CORE_SCIENTIFIC,
+	NUM_CORE_STATES
+} core_state_e ;
+
+		
+/* Helper structure to hold results */
+typedef struct RESULTS_S {
+	/* inputs */
+	ee_s16	seed1;		/* Initializing seed */
+	ee_s16	seed2;		/* Initializing seed */
+	ee_s16	seed3;		/* Initializing seed */
+	void	*memblock[4];	/* Pointer to safe memory location */
+	ee_u32	size;		/* Size of the data */
+	ee_u32 iterations;		/* Number of iterations to execute */
+	ee_u32	execs;		/* Bitmask of operations to execute */
+	struct list_head_s *list;
+	mat_params mat;
+	/* outputs */
+	ee_u16	crc;
+	ee_u16	crclist;
+	ee_u16	crcmatrix;
+	ee_u16	crcstate;
+	ee_s16	err;
+	/* ultithread specific */
+	core_portable port;
+} core_results;
+
+/* Multicore execution handling */
+#if (MULTITHREAD>1)
+ee_u8 core_start_parallel(core_results *res);
+ee_u8 core_stop_parallel(core_results *res);
+#endif
+
+/* list benchmark functions */
+list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed);
+ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx);
+
+/* state benchmark functions */
+void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p);
+ee_u16 core_bench_state(ee_u32 blksize, ee_u8 *memblock, 
+		ee_s16 seed1, ee_s16 seed2, ee_s16 step, ee_u16 crc);
+
+/* matrix benchmark functions */
+ee_u32 core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p);
+ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc);
+
diff --git a/tests/performance/coremark/coremark.ino b/tests/performance/coremark/coremark.ino
new file mode 100644
index 00000000000..872b53050f0
--- /dev/null
+++ b/tests/performance/coremark/coremark.ino
@@ -0,0 +1,118 @@
+/*
+    CoreMark benchmark for ESP32 using Arduino's C++ environment with multithreading support.
+
+    Based on https://github.com/PaulStoffregen/CoreMark/tree/master
+    Modified to run on ESP32 by Lucas Saavedra Vaz, 2024.
+*/
+
+#include <Arduino.h>
+#include <stdarg.h>
+
+#include <esp_task_wdt.h>
+
+// Timeout for the task watchdog timer
+#define TWDT_TIMEOUT_S 20
+
+// Number of runs to average
+#define N_RUNS 3
+
+// A way to call the C-only coremark function from Arduino's C++ environment
+extern "C" int coremark_main(void);
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  // To avoid the watchdog timer from resetting the ESP32 while running CoreMark we
+  // need to reconfigure it to have a longer timeout.
+  esp_task_wdt_config_t config = {
+    .timeout_ms = TWDT_TIMEOUT_S * 1000,
+    .idle_core_mask = 0,
+    .trigger_panic = false,
+  };
+
+  esp_task_wdt_reconfigure(&config);
+
+  log_d("Starting CoreMark test");
+  Serial.printf("Runs: %d\n", N_RUNS);
+  Serial.printf("Cores: %d\n", CONFIG_SOC_CPU_CORES_NUM);
+  Serial.flush();
+  for (int i = 0; i < N_RUNS; i++) {
+    Serial.printf("Run %d\n", i);
+    coremark_main();
+    Serial.flush();
+  }
+  log_d("CoreMark test finished");
+}
+
+void loop() {
+  vTaskDelete(NULL);
+}
+
+// CoreMark calls this function to print results.
+extern "C" int ee_printf(const char *format, ...) {
+  va_list args;
+  va_start(args, format);
+  for (; *format; format++) {
+    if (*format == '%') {
+      bool islong = false;
+      format++;
+      if (*format == '%') {
+        Serial.print(*format);
+        continue;
+      }
+      if (*format == '-') {
+        format++;  // ignore size
+      }
+      while (*format >= '0' && *format <= '9') {
+        format++;  // ignore size
+      }
+      if (*format == 'l') {
+        islong = true;
+        format++;
+      }
+      if (*format == '\0') {
+        break;
+      }
+      if (*format == 's') {
+        Serial.print((char *)va_arg(args, int));
+      } else if (*format == 'f') {
+        Serial.print(va_arg(args, double));
+      } else if (*format == 'd') {
+        if (islong) {
+          Serial.print(va_arg(args, long));
+        } else {
+          Serial.print(va_arg(args, int));
+        }
+      } else if (*format == 'u') {
+        if (islong) {
+          Serial.print(va_arg(args, unsigned long));
+        } else {
+          Serial.print(va_arg(args, unsigned int));
+        }
+      } else if (*format == 'x') {
+        if (islong) {
+          Serial.print(va_arg(args, unsigned long), HEX);
+        } else {
+          Serial.print(va_arg(args, unsigned int), HEX);
+        }
+      } else if (*format == 'c') {
+        Serial.print(va_arg(args, int));
+      }
+    } else {
+      if (*format == '\n') {
+        Serial.print('\r');
+      }
+      Serial.print(*format);
+    }
+  }
+  va_end(args);
+  return 1;
+}
+
+// CoreMark calls this function to measure elapsed time
+extern "C" uint32_t Arduino_millis(void) {
+  return millis();
+}
diff --git a/tests/performance/coremark/test_coremark.py b/tests/performance/coremark/test_coremark.py
new file mode 100644
index 00000000000..befd7c3a1c9
--- /dev/null
+++ b/tests/performance/coremark/test_coremark.py
@@ -0,0 +1,58 @@
+import json
+import logging
+import os
+
+
+def test_coremark(dut, request):
+    LOGGER = logging.getLogger(__name__)
+
+    # Match "Runs: %d"
+    res = dut.expect(r"Runs: (\d+)", timeout=60)
+    runs = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of runs: {}".format(runs))
+    assert runs > 0, "Invalid number of runs"
+
+    # Match "Cores: %d"
+    res = dut.expect(r"Cores: (\d+)", timeout=60)
+    cores = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of cores: {}".format(cores))
+    assert cores > 0, "Invalid number of cores"
+
+    total_score = 0
+
+    for i in range(runs):
+        # Match "Run %d"
+        res = dut.expect(r"Run (\d+)", timeout=120)
+        run = int(res.group(0).decode("utf-8").split(" ")[1])
+        LOGGER.info("Run {}".format(run))
+        assert run == i, "Invalid run number"
+
+        score = 0
+        # Match "CoreMark 1.0 : %d"
+        res = dut.expect(r"CoreMark 1.0 : (\d+)\.(\d+)", timeout=120)
+        score = float(res.group(0).decode("utf-8").split(" ")[3])
+        LOGGER.info("CoreMark score: {}".format(score))
+        assert score > 0 and score < 10000, "Impossible CoreMark score"
+        total_score += score
+
+    avg_score = round(total_score / runs, 2)
+    LOGGER.info("Average CoreMark score: {}".format(avg_score))
+    assert avg_score > 0 and avg_score < 10000, "Impossible CoreMark score"
+
+    # Create JSON with results and write it to file
+    # Always create a JSON with this format (so it can be merged later on):
+    # { TEST_NAME_STR: TEST_RESULTS_DICT }
+    results = {"coremark": {"runs": runs, "cores": cores, "avg_score": avg_score}}
+
+    current_folder = os.path.dirname(request.path)
+    file_index = 0
+    report_file = os.path.join(current_folder, "result_coremark" + str(file_index) + ".json")
+    while os.path.exists(report_file):
+        report_file = report_file.replace(str(file_index) + ".json", str(file_index + 1) + ".json")
+        file_index += 1
+
+    with open(report_file, "w") as f:
+        try:
+            f.write(json.dumps(results))
+        except Exception as e:
+            LOGGER.warning("Failed to write results to file: {}".format(e))
diff --git a/tests/performance/fibonacci/ci.json b/tests/performance/fibonacci/ci.json
new file mode 100644
index 00000000000..accee2b2135
--- /dev/null
+++ b/tests/performance/fibonacci/ci.json
@@ -0,0 +1,6 @@
+{
+  "platforms": {
+    "qemu": false,
+    "wokwi": false
+  }
+}
diff --git a/tests/performance/fibonacci/fibonacci.ino b/tests/performance/fibonacci/fibonacci.ino
new file mode 100644
index 00000000000..c82fd6b70d8
--- /dev/null
+++ b/tests/performance/fibonacci/fibonacci.ino
@@ -0,0 +1,48 @@
+/*
+  Fibonacci calculation test for Arduino and ESP32.
+  Created by Lucas Saavedra Vaz, 2024
+*/
+
+#include <Arduino.h>
+
+// Number of runs to average
+#define N_RUNS 3
+
+// Fibonacci number to calculate. Keep between 35 and 45.
+#define FIB_N 40
+
+uint64_t fib(uint32_t n) {
+  if (n < 2) {
+    return n;
+  }
+  return fib(n - 1) + fib(n - 2);
+}
+
+void setup() {
+  uint64_t fibonacci;
+
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  log_d("Starting fibonacci calculation");
+  Serial.printf("Runs: %d\n", N_RUNS);
+  Serial.printf("N: %d\n", FIB_N);
+  Serial.flush();
+  for (int i = 0; i < N_RUNS; i++) {
+    Serial.printf("Run %d\n", i);
+    unsigned long start = millis();
+    fibonacci = fib(FIB_N);
+    unsigned long elapsed = millis() - start;
+    Serial.printf("Fibonacci(N): %llu\n", fibonacci);
+    Serial.printf("Time: %lu.%03lu s\n", elapsed / 1000, elapsed % 1000);
+    Serial.flush();
+  }
+
+  log_d("Fibonacci calculation test done");
+}
+
+void loop() {
+  vTaskDelete(NULL);
+}
diff --git a/tests/performance/fibonacci/test_fibonacci.py b/tests/performance/fibonacci/test_fibonacci.py
new file mode 100644
index 00000000000..cf560d9691c
--- /dev/null
+++ b/tests/performance/fibonacci/test_fibonacci.py
@@ -0,0 +1,80 @@
+import json
+import logging
+import os
+
+fib_results = {}
+
+
+def fib(n):
+    if n < 2:
+        return n
+    elif str(n) in fib_results:
+        return fib_results[str(n)]
+    else:
+        fib_results[str(n)] = fib(n - 1) + fib(n - 2)
+        return fib_results[str(n)]
+
+
+def test_fibonacci(dut, request):
+    LOGGER = logging.getLogger(__name__)
+
+    # Match "Runs: %d"
+    res = dut.expect(r"Runs: (\d+)", timeout=60)
+    runs = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of runs: {}".format(runs))
+    assert runs > 0, "Invalid number of runs"
+
+    # Match "N: %d"
+    res = dut.expect(r"N: (\d+)", timeout=300)
+    fib_n = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Calculating Fibonacci({})".format(fib_n))
+    assert fib_n > 0, "Invalid Fibonacci number"
+
+    # Calculate Fibonacci results
+    expected_result = fib(fib_n)
+    LOGGER.info("Expected Fibonacci result: {}".format(expected_result))
+
+    list_time = []
+
+    for i in range(runs):
+        # Match "Run %d"
+        res = dut.expect(r"Run (\d+)", timeout=120)
+        run = int(res.group(0).decode("utf-8").split(" ")[1])
+        LOGGER.info("Run {}".format(run))
+        assert run == i, "Invalid run number"
+
+        # Match "Fibonacci(N): %llu"
+        res = dut.expect(r"Fibonacci\(N\): (\d+)", timeout=300)
+        fib_result = int(res.group(0).decode("utf-8").split(" ")[1])
+        LOGGER.info("Fibonacci({}) = {}".format(fib_n, fib_result))
+        assert fib_result > 0, "Invalid Fibonacci result"
+
+        # Check if the result is correct
+        assert fib_result == expected_result
+
+        # Match "Time: %lu.%03lu s"
+        res = dut.expect(r"Time: (\d+)\.(\d+) s", timeout=300)
+        time = float(res.group(0).decode("utf-8").split(" ")[1])
+        LOGGER.info("Time on run {}: {} s".format(i, time))
+        assert time > 0 and time < 1000, "Invalid time"
+        list_time.append(time)
+
+    avg_time = round(sum(list_time) / len(list_time), 3)
+
+    # Create JSON with results and write it to file
+    # Always create a JSON with this format (so it can be merged later on):
+    # { TEST_NAME_STR: TEST_RESULTS_DICT }
+    results = {"fibonacci": {"runs": runs, "fib_n": fib_n, "avg_time": avg_time}}
+
+    current_folder = os.path.dirname(request.path)
+    file_index = 0
+    report_file = os.path.join(current_folder, "result_fibonacci" + str(file_index) + ".json")
+    while os.path.exists(report_file):
+        report_file = report_file.replace(str(file_index) + ".json", str(file_index + 1) + ".json")
+        file_index += 1
+
+    with open(report_file, "w") as f:
+        try:
+            f.write(json.dumps(results))
+        except Exception as e:
+            LOGGER.warning("Failed to write results to file: {}".format(e))
diff --git a/tests/performance/linpack_double/ci.json b/tests/performance/linpack_double/ci.json
new file mode 100644
index 00000000000..accee2b2135
--- /dev/null
+++ b/tests/performance/linpack_double/ci.json
@@ -0,0 +1,6 @@
+{
+  "platforms": {
+    "qemu": false,
+    "wokwi": false
+  }
+}
diff --git a/tests/performance/linpack_double/linpack_double.ino b/tests/performance/linpack_double/linpack_double.ino
new file mode 100644
index 00000000000..5148b6ef591
--- /dev/null
+++ b/tests/performance/linpack_double/linpack_double.ino
@@ -0,0 +1,1094 @@
+/*
+  Linpack test for Arduino and ESP32.
+  Based on https://github.com/VioletGiraffe/EmbeddedLinpack
+  Created by Violet Giraffe, 2018
+  Adapted by Lucas Saavedra Vaz, 2024
+*/
+
+#include <Arduino.h>
+#include <math.h>
+
+// Number of runs to average
+#define N_RUNS 1000
+
+using floating_point_t = double;
+bool type_float;
+
+floating_point_t benchmark(void);
+floating_point_t cpu_time(void);
+void daxpy(int n, floating_point_t da, floating_point_t dx[], int incx, floating_point_t dy[], int incy);
+floating_point_t ddot(int n, floating_point_t dx[], int incx, floating_point_t dy[], int incy);
+int dgefa(floating_point_t a[], int lda, int n, int ipvt[]);
+void dgesl(floating_point_t a[], int lda, int n, int ipvt[], floating_point_t b[], int job);
+void dscal(int n, floating_point_t sa, floating_point_t x[], int incx);
+int idamax(int n, floating_point_t dx[], int incx);
+floating_point_t r8_abs(floating_point_t x);
+floating_point_t r8_epsilon(void);
+floating_point_t r8_max(floating_point_t x, floating_point_t y);
+floating_point_t r8_random(int iseed[4]);
+void r8mat_gen(int lda, int n, floating_point_t *a);
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  String data_type;
+
+  if (sizeof(floating_point_t) == sizeof(float)) {
+    data_type = "float";
+    type_float = true;
+  } else if (sizeof(floating_point_t) == sizeof(double)) {
+    data_type = "double";
+    type_float = false;
+  } else {
+    data_type = "unknown";
+    log_e("Unknown data type size. Aborting.");
+    while (1);
+  }
+
+  log_d("Starting Linpack %s test", data_type.c_str());
+  Serial.printf("Runs: %d\n", N_RUNS);
+  Serial.printf("Type: %s\n", data_type.c_str());
+  Serial.flush();
+  int i = 0;
+
+  floating_point_t minMflops = 1000000000.0, maxMflops = 0.0, avgMflops = 0.0;
+  for (i = 0; i < N_RUNS; ++i) {
+    Serial.printf("Run %d\n", i);
+    const auto mflops = benchmark();
+    avgMflops += mflops;
+    minMflops = fmin(mflops, minMflops);
+    maxMflops = fmax(mflops, maxMflops);
+    Serial.flush();
+  }
+
+  avgMflops /= N_RUNS;
+  Serial.println(String("Runs completed: ") + i);
+  Serial.println(String("Average MFLOPS: ") + avgMflops);
+  Serial.println(String("Min MFLOPS: ") + minMflops);
+  Serial.println(String("Max MFLOPS: ") + maxMflops);
+  Serial.flush();
+}
+
+void loop() {
+  vTaskDelete(NULL);
+}
+
+/******************************************************************************/
+
+floating_point_t benchmark(void)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    MAIN is the main program for LINPACK_BENCH.
+
+  Discussion:
+
+    LINPACK_BENCH drives the floating_point_t precision LINPACK benchmark program.
+
+  Modified:
+
+    25 July 2008
+
+  Parameters:
+
+    N is the problem size.
+*/
+{
+#define N   8
+#define LDA (N + 1)
+
+  static floating_point_t a[N * LDA];
+  static floating_point_t a_max;
+  static floating_point_t b[N];
+  static floating_point_t b_max;
+  const floating_point_t cray = 0.056;
+  static floating_point_t eps;
+  int i;
+  int info;
+  static int ipvt[N];
+  int j;
+  int job;
+  floating_point_t ops;
+  static floating_point_t resid[N];
+  floating_point_t resid_max;
+  [[maybe_unused]]
+  floating_point_t residn;
+  static floating_point_t rhs[N];
+  floating_point_t t1;
+  floating_point_t t2;
+  static floating_point_t time[6];
+  floating_point_t total;
+  floating_point_t x[N];
+
+  log_d("LINPACK_BENCH");
+  log_d("  C version");
+  log_d("  The LINPACK benchmark.");
+  log_d("  Language: C");
+  if (!type_float) {
+    log_d("  Datatype: Double precision real");
+  } else if (type_float) {
+    log_d("  Datatype: Single precision real");
+  } else {
+    log_d("  Datatype: unknown");
+  }
+  log_d("  Matrix order N               = %d", N);
+  log_d("  Leading matrix dimension LDA = %d", LDA);
+
+  ops = (floating_point_t)(2L * N * N * N) / 3.0 + 2.0 * (floating_point_t)((long)N * N);
+
+  /*
+  Allocate space for arrays.
+*/
+  r8mat_gen(LDA, N, a);
+
+  a_max = 0.0;
+  for (j = 0; j < N; j++) {
+    for (i = 0; i < N; i++) {
+      a_max = r8_max(a_max, a[i + j * LDA]);
+    }
+  }
+
+  for (i = 0; i < N; i++) {
+    x[i] = 1.0;
+  }
+
+  for (i = 0; i < N; i++) {
+    b[i] = 0.0;
+    for (j = 0; j < N; j++) {
+      b[i] = b[i] + a[i + j * LDA] * x[j];
+    }
+  }
+  t1 = cpu_time();
+
+  info = dgefa(a, LDA, N, ipvt);
+
+  if (info != 0) {
+    log_d("LINPACK_BENCH - Fatal error!");
+    log_d("  The matrix A is apparently singular.");
+    log_d("  Abnormal end of execution.");
+    return 1;
+  }
+
+  t2 = cpu_time();
+  time[0] = t2 - t1;
+
+  t1 = cpu_time();
+
+  job = 0;
+  dgesl(a, LDA, N, ipvt, b, job);
+
+  t2 = cpu_time();
+  time[1] = t2 - t1;
+
+  total = time[0] + time[1];
+
+  /*
+  Compute a residual to verify results.
+*/
+  r8mat_gen(LDA, N, a);
+
+  for (i = 0; i < N; i++) {
+    x[i] = 1.0;
+  }
+
+  for (i = 0; i < N; i++) {
+    rhs[i] = 0.0;
+    for (j = 0; j < N; j++) {
+      rhs[i] = rhs[i] + a[i + j * LDA] * x[j];
+    }
+  }
+
+  for (i = 0; i < N; i++) {
+    resid[i] = -rhs[i];
+    for (j = 0; j < N; j++) {
+      resid[i] = resid[i] + a[i + j * LDA] * b[j];
+    }
+  }
+
+  resid_max = 0.0;
+  for (i = 0; i < N; i++) {
+    resid_max = r8_max(resid_max, r8_abs(resid[i]));
+  }
+
+  b_max = 0.0;
+  for (i = 0; i < N; i++) {
+    b_max = r8_max(b_max, r8_abs(b[i]));
+  }
+
+  eps = r8_epsilon();
+
+  residn = resid_max / (floating_point_t)N / a_max / b_max / eps;
+
+  time[2] = total;
+  if (0.0 < total) {
+    time[3] = ops / (1.0E+06 * total);
+  } else {
+    time[3] = -1.0;
+  }
+  time[4] = 2.0 / time[3];
+  time[5] = total / cray;
+
+  log_d("");
+  log_d("     Norm. Resid      Resid           MACHEP         X[1]          X[N]");
+  log_d("  %14f  %14f  %14e  %14f  %14f", residn, resid_max, eps, b[0], b[N - 1]);
+  log_d("");
+  log_d("      Factor     Solve      Total     MFLOPS       Unit      Cray-Ratio");
+  log_d("  %9f  %9f  %9f  %9f  %9f  %9f", time[0], time[1], time[2], time[3], time[4], time[5]);
+
+  /*
+  Terminate.
+*/
+  log_d("");
+  log_d("LINPACK_BENCH");
+  log_d("  Normal end of execution.");
+  log_d("");
+
+  return time[3];
+#undef LDA
+#undef N
+}
+/******************************************************************************/
+
+floating_point_t cpu_time(void)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    CPU_TIME returns the current reading on the CPU clock.
+
+  Discussion:
+
+    The CPU time measurements available through this routine are often
+    not very accurate.  In some cases, the accuracy is no better than
+    a hundredth of a second.
+
+  Licensing:
+
+    This code is distributed under the GNU LGPL license.
+
+  Modified:
+
+    06 June 2005
+
+  Author:
+
+    John Burkardt
+
+  Parameters:
+
+    Output, floating_point_t CPU_TIME, the current reading of the CPU clock, in seconds.
+*/
+{
+  floating_point_t value;
+
+  value = (floating_point_t)micros() / (floating_point_t)1000000;
+
+  return value;
+}
+/******************************************************************************/
+
+void daxpy(int n, floating_point_t da, floating_point_t dx[], int incx, floating_point_t dy[], int incy)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DAXPY computes constant times a vector plus a vector.
+
+  Discussion:
+
+    This routine uses unrolled loops for increments equal to one.
+
+  Modified:
+
+    30 March 2007
+
+  Author:
+
+    FORTRAN77 original by Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart.
+    C version by John Burkardt
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, 1979.
+
+    Charles Lawson, Richard Hanson, David Kincaid, Fred Krogh,
+    Basic Linear Algebra Subprograms for Fortran Usage,
+    Algorithm 539,
+    ACM Transactions on Mathematical Software,
+    Volume 5, Number 3, September 1979, pages 308-323.
+
+  Parameters:
+
+    Input, int N, the number of elements in DX and DY.
+
+    Input, floating_point_t DA, the multiplier of DX.
+
+    Input, floating_point_t DX[*], the first vector.
+
+    Input, int INCX, the increment between successive entries of DX.
+
+    Input/output, floating_point_t DY[*], the second vector.
+    On output, DY[*] has been replaced by DY[*] + DA * DX[*].
+
+    Input, int INCY, the increment between successive entries of DY.
+*/
+{
+  int i;
+  int ix;
+  int iy;
+  int m;
+
+  if (n <= 0) {
+    return;
+  }
+
+  if (da == 0.0) {
+    return;
+  }
+  /*
+  Code for unequal increments or equal increments
+  not equal to 1.
+*/
+  if (incx != 1 || incy != 1) {
+    if (0 <= incx) {
+      ix = 0;
+    } else {
+      ix = (-n + 1) * incx;
+    }
+
+    if (0 <= incy) {
+      iy = 0;
+    } else {
+      iy = (-n + 1) * incy;
+    }
+
+    for (i = 0; i < n; i++) {
+      dy[iy] = dy[iy] + da * dx[ix];
+      ix = ix + incx;
+      iy = iy + incy;
+    }
+  }
+  /*
+  Code for both increments equal to 1.
+*/
+  else {
+    m = n % 4;
+
+    for (i = 0; i < m; i++) {
+      dy[i] = dy[i] + da * dx[i];
+    }
+
+    for (i = m; i < n; i = i + 4) {
+      dy[i] = dy[i] + da * dx[i];
+      dy[i + 1] = dy[i + 1] + da * dx[i + 1];
+      dy[i + 2] = dy[i + 2] + da * dx[i + 2];
+      dy[i + 3] = dy[i + 3] + da * dx[i + 3];
+    }
+  }
+  return;
+}
+/******************************************************************************/
+
+floating_point_t ddot(int n, floating_point_t dx[], int incx, floating_point_t dy[], int incy)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DDOT forms the dot product of two vectors.
+
+  Discussion:
+
+    This routine uses unrolled loops for increments equal to one.
+
+  Modified:
+
+    30 March 2007
+
+  Author:
+
+    FORTRAN77 original by Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart.
+    C version by John Burkardt
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, 1979.
+
+    Charles Lawson, Richard Hanson, David Kincaid, Fred Krogh,
+    Basic Linear Algebra Subprograms for Fortran Usage,
+    Algorithm 539,
+    ACM Transactions on Mathematical Software,
+    Volume 5, Number 3, September 1979, pages 308-323.
+
+  Parameters:
+
+    Input, int N, the number of entries in the vectors.
+
+    Input, floating_point_t DX[*], the first vector.
+
+    Input, int INCX, the increment between successive entries in DX.
+
+    Input, floating_point_t DY[*], the second vector.
+
+    Input, int INCY, the increment between successive entries in DY.
+
+    Output, floating_point_t DDOT, the sum of the product of the corresponding
+    entries of DX and DY.
+*/
+{
+  floating_point_t dtemp;
+  int i;
+  int ix;
+  int iy;
+  int m;
+
+  dtemp = 0.0;
+
+  if (n <= 0) {
+    return dtemp;
+  }
+  /*
+  Code for unequal increments or equal increments
+  not equal to 1.
+*/
+  if (incx != 1 || incy != 1) {
+    if (0 <= incx) {
+      ix = 0;
+    } else {
+      ix = (-n + 1) * incx;
+    }
+
+    if (0 <= incy) {
+      iy = 0;
+    } else {
+      iy = (-n + 1) * incy;
+    }
+
+    for (i = 0; i < n; i++) {
+      dtemp = dtemp + dx[ix] * dy[iy];
+      ix = ix + incx;
+      iy = iy + incy;
+    }
+  }
+  /*
+  Code for both increments equal to 1.
+*/
+  else {
+    m = n % 5;
+
+    for (i = 0; i < m; i++) {
+      dtemp = dtemp + dx[i] * dy[i];
+    }
+
+    for (i = m; i < n; i = i + 5) {
+      dtemp = dtemp + dx[i] * dy[i] + dx[i + 1] * dy[i + 1] + dx[i + 2] * dy[i + 2] + dx[i + 3] * dy[i + 3] + dx[i + 4] * dy[i + 4];
+    }
+  }
+  return dtemp;
+}
+/******************************************************************************/
+
+int dgefa(floating_point_t a[], int lda, int n, int ipvt[])
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DGEFA factors a real general matrix.
+
+  Modified:
+
+    16 May 2005
+
+  Author:
+
+    C version by John Burkardt.
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch and Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, (Society for Industrial and Applied Mathematics),
+    3600 University City Science Center,
+    Philadelphia, PA, 19104-2688.
+    ISBN 0-89871-172-X
+
+  Parameters:
+
+    Input/output, floating_point_t A[LDA*N].
+    On input, the matrix to be factored.
+    On output, an upper triangular matrix and the multipliers used to obtain
+    it.  The factorization can be written A=L*U, where L is a product of
+    permutation and unit lower triangular matrices, and U is upper triangular.
+
+    Input, int LDA, the leading dimension of A.
+
+    Input, int N, the order of the matrix A.
+
+    Output, int IPVT[N], the pivot indices.
+
+    Output, int DGEFA, singularity indicator.
+    0, normal value.
+    K, if U(K,K) == 0.  This is not an error condition for this subroutine,
+    but it does indicate that DGESL or DGEDI will divide by zero if called.
+    Use RCOND in DGECO for a reliable indication of singularity.
+*/
+{
+  int info;
+  int j;
+  int k;
+  int l;
+  floating_point_t t;
+  /*
+  Gaussian elimination with partial pivoting.
+*/
+  info = 0;
+
+  for (k = 1; k <= n - 1; k++) {
+    /*
+  Find L = pivot index.
+*/
+    l = idamax(n - k + 1, a + (k - 1) + (k - 1) * lda, 1) + k - 1;
+    ipvt[k - 1] = l;
+    /*
+  Zero pivot implies this column already triangularized.
+*/
+    if (a[l - 1 + (k - 1) * lda] == 0.0) {
+      info = k;
+      continue;
+    }
+    /*
+  Interchange if necessary.
+*/
+    if (l != k) {
+      t = a[l - 1 + (k - 1) * lda];
+      a[l - 1 + (k - 1) * lda] = a[k - 1 + (k - 1) * lda];
+      a[k - 1 + (k - 1) * lda] = t;
+    }
+    /*
+  Compute multipliers.
+*/
+    t = -1.0 / a[k - 1 + (k - 1) * lda];
+
+    dscal(n - k, t, a + k + (k - 1) * lda, 1);
+    /*
+  Row elimination with column indexing.
+*/
+    for (j = k + 1; j <= n; j++) {
+      t = a[l - 1 + (j - 1) * lda];
+      if (l != k) {
+        a[l - 1 + (j - 1) * lda] = a[k - 1 + (j - 1) * lda];
+        a[k - 1 + (j - 1) * lda] = t;
+      }
+      daxpy(n - k, t, a + k + (k - 1) * lda, 1, a + k + (j - 1) * lda, 1);
+    }
+  }
+
+  ipvt[n - 1] = n;
+
+  if (a[n - 1 + (n - 1) * lda] == 0.0) {
+    info = n;
+  }
+
+  return info;
+}
+/******************************************************************************/
+
+void dgesl(floating_point_t a[], int lda, int n, int ipvt[], floating_point_t b[], int job)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DGESL solves a real general linear system A * X = B.
+
+  Discussion:
+
+    DGESL can solve either of the systems A * X = B or A' * X = B.
+
+    The system matrix must have been factored by DGECO or DGEFA.
+
+    A division by zero will occur if the input factor contains a
+    zero on the diagonal.  Technically this indicates singularity
+    but it is often caused by improper arguments or improper
+    setting of LDA.  It will not occur if the subroutines are
+    called correctly and if DGECO has set 0.0 < RCOND
+    or DGEFA has set INFO == 0.
+
+  Modified:
+
+    16 May 2005
+
+  Author:
+
+    C version by John Burkardt.
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch and Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, (Society for Industrial and Applied Mathematics),
+    3600 University City Science Center,
+    Philadelphia, PA, 19104-2688.
+    ISBN 0-89871-172-X
+
+  Parameters:
+
+    Input, floating_point_t A[LDA*N], the output from DGECO or DGEFA.
+
+    Input, int LDA, the leading dimension of A.
+
+    Input, int N, the order of the matrix A.
+
+    Input, int IPVT[N], the pivot vector from DGECO or DGEFA.
+
+    Input/output, floating_point_t B[N].
+    On input, the right hand side vector.
+    On output, the solution vector.
+
+    Input, int JOB.
+    0, solve A * X = B;
+    nonzero, solve A' * X = B.
+*/
+{
+  int k;
+  int l;
+  floating_point_t t;
+  /*
+  Solve A * X = B.
+*/
+  if (job == 0) {
+    for (k = 1; k <= n - 1; k++) {
+      l = ipvt[k - 1];
+      t = b[l - 1];
+
+      if (l != k) {
+        b[l - 1] = b[k - 1];
+        b[k - 1] = t;
+      }
+
+      daxpy(n - k, t, a + k + (k - 1) * lda, 1, b + k, 1);
+    }
+
+    for (k = n; 1 <= k; k--) {
+      b[k - 1] = b[k - 1] / a[k - 1 + (k - 1) * lda];
+      t = -b[k - 1];
+      daxpy(k - 1, t, a + 0 + (k - 1) * lda, 1, b, 1);
+    }
+  }
+  /*
+  Solve A' * X = B.
+*/
+  else {
+    for (k = 1; k <= n; k++) {
+      t = ddot(k - 1, a + 0 + (k - 1) * lda, 1, b, 1);
+      b[k - 1] = (b[k - 1] - t) / a[k - 1 + (k - 1) * lda];
+    }
+
+    for (k = n - 1; 1 <= k; k--) {
+      b[k - 1] = b[k - 1] + ddot(n - k, a + k + (k - 1) * lda, 1, b + k, 1);
+      l = ipvt[k - 1];
+
+      if (l != k) {
+        t = b[l - 1];
+        b[l - 1] = b[k - 1];
+        b[k - 1] = t;
+      }
+    }
+  }
+  return;
+}
+/******************************************************************************/
+
+void dscal(int n, floating_point_t sa, floating_point_t x[], int incx)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DSCAL scales a vector by a constant.
+
+  Modified:
+
+    30 March 2007
+
+  Author:
+
+    FORTRAN77 original by Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart.
+    C version by John Burkardt
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, 1979.
+
+    Charles Lawson, Richard Hanson, David Kincaid, Fred Krogh,
+    Basic Linear Algebra Subprograms for Fortran Usage,
+    Algorithm 539,
+    ACM Transactions on Mathematical Software,
+    Volume 5, Number 3, September 1979, pages 308-323.
+
+  Parameters:
+
+    Input, int N, the number of entries in the vector.
+
+    Input, floating_point_t SA, the multiplier.
+
+    Input/output, floating_point_t X[*], the vector to be scaled.
+
+    Input, int INCX, the increment between successive entries of X.
+*/
+{
+  int i;
+  int ix;
+  int m;
+
+  if (n <= 0) {
+  } else if (incx == 1) {
+    m = n % 5;
+
+    for (i = 0; i < m; i++) {
+      x[i] = sa * x[i];
+    }
+
+    for (i = m; i < n; i = i + 5) {
+      x[i] = sa * x[i];
+      x[i + 1] = sa * x[i + 1];
+      x[i + 2] = sa * x[i + 2];
+      x[i + 3] = sa * x[i + 3];
+      x[i + 4] = sa * x[i + 4];
+    }
+  } else {
+    if (0 <= incx) {
+      ix = 0;
+    } else {
+      ix = (-n + 1) * incx;
+    }
+
+    for (i = 0; i < n; i++) {
+      x[ix] = sa * x[ix];
+      ix = ix + incx;
+    }
+  }
+  return;
+}
+/******************************************************************************/
+
+int idamax(int n, floating_point_t dx[], int incx)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    IDAMAX finds the index of the vector element of maximum absolute value.
+
+  Discussion:
+
+    WARNING: This index is a 1-based index, not a 0-based index!
+
+  Modified:
+
+    30 March 2007
+
+  Author:
+
+    FORTRAN77 original by Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart.
+    C version by John Burkardt
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, 1979.
+
+    Charles Lawson, Richard Hanson, David Kincaid, Fred Krogh,
+    Basic Linear Algebra Subprograms for Fortran Usage,
+    Algorithm 539,
+    ACM Transactions on Mathematical Software,
+    Volume 5, Number 3, September 1979, pages 308-323.
+
+  Parameters:
+
+    Input, int N, the number of entries in the vector.
+
+    Input, floating_point_t X[*], the vector to be examined.
+
+    Input, int INCX, the increment between successive entries of SX.
+
+    Output, int IDAMAX, the index of the element of maximum
+    absolute value.
+*/
+{
+  floating_point_t dmax;
+  int i;
+  int ix;
+  int value;
+
+  value = 0;
+
+  if (n < 1 || incx <= 0) {
+    return value;
+  }
+
+  value = 1;
+
+  if (n == 1) {
+    return value;
+  }
+
+  if (incx == 1) {
+    dmax = r8_abs(dx[0]);
+
+    for (i = 1; i < n; i++) {
+      if (dmax < r8_abs(dx[i])) {
+        value = i + 1;
+        dmax = r8_abs(dx[i]);
+      }
+    }
+  } else {
+    ix = 0;
+    dmax = r8_abs(dx[0]);
+    ix = ix + incx;
+
+    for (i = 1; i < n; i++) {
+      if (dmax < r8_abs(dx[ix])) {
+        value = i + 1;
+        dmax = r8_abs(dx[ix]);
+      }
+      ix = ix + incx;
+    }
+  }
+
+  return value;
+}
+/******************************************************************************/
+
+floating_point_t r8_abs(floating_point_t x)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8_ABS returns the absolute value of a R8.
+
+  Modified:
+
+    02 April 2005
+
+  Author:
+
+    John Burkardt
+
+  Parameters:
+
+    Input, floating_point_t X, the quantity whose absolute value is desired.
+
+    Output, floating_point_t R8_ABS, the absolute value of X.
+*/
+{
+  floating_point_t value;
+
+  if (0.0 <= x) {
+    value = x;
+  } else {
+    value = -x;
+  }
+  return value;
+}
+/******************************************************************************/
+
+floating_point_t r8_epsilon(void)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8_EPSILON returns the R8 round off unit.
+
+  Discussion:
+
+    R8_EPSILON is a number R which is a power of 2 with the property that,
+    to the precision of the computer's arithmetic,
+      1 < 1 + R
+    but
+      1 = ( 1 + R / 2 )
+
+  Licensing:
+
+    This code is distributed under the GNU LGPL license.
+
+  Modified:
+
+    08 May 2006
+
+  Author:
+
+    John Burkardt
+
+  Parameters:
+
+    Output, floating_point_t R8_EPSILON, the floating_point_t precision round-off unit.
+*/
+{
+  floating_point_t r;
+
+  r = 1.0;
+
+  while (1.0 < (floating_point_t)(1.0 + r)) {
+    r = r / 2.0;
+  }
+  r = 2.0 * r;
+
+  return r;
+}
+/******************************************************************************/
+
+floating_point_t r8_max(floating_point_t x, floating_point_t y)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8_MAX returns the maximum of two R8's.
+
+  Modified:
+
+    18 August 2004
+
+  Author:
+
+    John Burkardt
+
+  Parameters:
+
+    Input, floating_point_t X, Y, the quantities to compare.
+
+    Output, floating_point_t R8_MAX, the maximum of X and Y.
+*/
+{
+  floating_point_t value;
+
+  if (y < x) {
+    value = x;
+  } else {
+    value = y;
+  }
+  return value;
+}
+/******************************************************************************/
+
+floating_point_t r8_random(int iseed[4])
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8_RANDOM returns a uniformly distributed random number between 0 and 1.
+
+  Discussion:
+
+    This routine uses a multiplicative congruential method with modulus
+    2**48 and multiplier 33952834046453 (see G.S.Fishman,
+    'Multiplicative congruential random number generators with modulus
+    2**b: an exhaustive analysis for b = 32 and a partial analysis for
+    b = 48', Math. Comp. 189, pp 331-344, 1990).
+
+    48-bit integers are stored in 4 integer array elements with 12 bits
+    per element. Hence the routine is portable across machines with
+    integers of 32 bits or more.
+
+  Parameters:
+
+    Input/output, integer ISEED(4).
+    On entry, the seed of the random number generator; the array
+    elements must be between 0 and 4095, and ISEED(4) must be odd.
+    On exit, the seed is updated.
+
+    Output, floating_point_t R8_RANDOM, the next pseudorandom number.
+*/
+{
+  int ipw2 = 4096;
+  int it1;
+  int it2;
+  int it3;
+  int it4;
+  int m1 = 494;
+  int m2 = 322;
+  int m3 = 2508;
+  int m4 = 2549;
+  floating_point_t r = 1.0 / 4096.0;
+  floating_point_t value;
+  /*
+  Multiply the seed by the multiplier modulo 2**48.
+*/
+  it4 = iseed[3] * m4;
+  it3 = it4 / ipw2;
+  it4 = it4 - ipw2 * it3;
+  it3 = it3 + iseed[2] * m4 + iseed[3] * m3;
+  it2 = it3 / ipw2;
+  it3 = it3 - ipw2 * it2;
+  it2 = it2 + iseed[1] * m4 + iseed[2] * m3 + iseed[3] * m2;
+  it1 = it2 / ipw2;
+  it2 = it2 - ipw2 * it1;
+  it1 = it1 + iseed[0] * m4 + iseed[1] * m3 + iseed[2] * m2 + iseed[3] * m1;
+  it1 = (it1 % ipw2);
+  /*
+  Return updated seed
+*/
+  iseed[0] = it1;
+  iseed[1] = it2;
+  iseed[2] = it3;
+  iseed[3] = it4;
+  /*
+  Convert 48-bit integer to a real number in the interval (0,1)
+*/
+  value = r * ((floating_point_t)(it1) + r * ((floating_point_t)(it2) + r * ((floating_point_t)(it3) + r * ((floating_point_t)(it4)))));
+
+  return value;
+}
+/******************************************************************************/
+
+void r8mat_gen(int lda, int n, floating_point_t *a)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8MAT_GEN generates a random R8MAT.
+
+  Modified:
+
+    06 June 2005
+
+  Parameters:
+
+    Input, integer LDA, the leading dimension of the matrix.
+
+    Input, integer N, the order of the matrix.
+
+    Output, floating_point_t R8MAT_GEN[LDA*N], the N by N matrix.
+*/
+{
+  int i;
+  int init[4] = {1, 2, 3, 1325};
+  int j;
+
+  for (j = 1; j <= n; j++) {
+    for (i = 1; i <= n; i++) {
+      a[i - 1 + (j - 1) * lda] = r8_random(init) - 0.5;
+    }
+  }
+}
+/******************************************************************************/
diff --git a/tests/performance/linpack_double/test_linpack_double.py b/tests/performance/linpack_double/test_linpack_double.py
new file mode 100644
index 00000000000..0a6e2f90ef3
--- /dev/null
+++ b/tests/performance/linpack_double/test_linpack_double.py
@@ -0,0 +1,61 @@
+import json
+import logging
+import os
+
+
+def test_linpack_double(dut, request):
+    LOGGER = logging.getLogger(__name__)
+
+    # Match "Runs: %d"
+    res = dut.expect(r"Runs: (\d+)", timeout=60)
+    runs = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of runs: {}".format(runs))
+    assert runs > 0, "Invalid number of runs"
+
+    # Match "Type: %s"
+    res = dut.expect(r"Type: (\w+)", timeout=60)
+    data_type = res.group(0).decode("utf-8").split(" ")[1]
+    LOGGER.info("Data type: {}".format(data_type))
+    assert data_type == "double", "Invalid data type"
+
+    # Match "Runs completed: %d"
+    res = dut.expect(r"Runs completed: (\d+)", timeout=120)
+    runs_completed = int(res.group(0).decode("utf-8").split(" ")[2])
+    LOGGER.info("Runs completed: {}".format(runs_completed))
+    assert runs_completed == runs, "Invalid number of runs completed"
+
+    # Match "Average MFLOPS: %f"
+    res = dut.expect(r"Average MFLOPS: (\d+\.\d+)", timeout=120)
+    avg_score = float(res.group(0).decode("utf-8").split(" ")[2])
+    LOGGER.info("Average MFLOPS: {}".format(avg_score))
+    assert avg_score > 0, "Invalid average MFLOPS"
+
+    # Match "Min MFLOPS: %f"
+    res = dut.expect(r"Min MFLOPS: (\d+\.\d+)", timeout=120)
+    min_score = float(res.group(0).decode("utf-8").split(" ")[2])
+    LOGGER.info("Min MFLOPS: {}".format(min_score))
+    assert min_score > 0 and min_score < 1000000000.0, "Invalid min MFLOPS"
+
+    # Match "Max MFLOPS: %f"
+    res = dut.expect(r"Max MFLOPS: (\d+\.\d+)", timeout=120)
+    max_score = float(res.group(0).decode("utf-8").split(" ")[2])
+    LOGGER.info("Max MFLOPS: {}".format(max_score))
+    assert max_score > 0, "Invalid max MFLOPS"
+
+    # Create JSON with results and write it to file
+    # Always create a JSON with this format (so it can be merged later on):
+    # { TEST_NAME_STR: TEST_RESULTS_DICT }
+    results = {"linpack_double": {"runs": runs, "avg_score": avg_score, "min_score": min_score, "max_score": max_score}}
+
+    current_folder = os.path.dirname(request.path)
+    file_index = 0
+    report_file = os.path.join(current_folder, "result_linpack_double" + str(file_index) + ".json")
+    while os.path.exists(report_file):
+        report_file = report_file.replace(str(file_index) + ".json", str(file_index + 1) + ".json")
+        file_index += 1
+
+    with open(report_file, "w") as f:
+        try:
+            f.write(json.dumps(results))
+        except Exception as e:
+            LOGGER.warning("Failed to write results to file: {}".format(e))
diff --git a/tests/performance/linpack_float/ci.json b/tests/performance/linpack_float/ci.json
new file mode 100644
index 00000000000..accee2b2135
--- /dev/null
+++ b/tests/performance/linpack_float/ci.json
@@ -0,0 +1,6 @@
+{
+  "platforms": {
+    "qemu": false,
+    "wokwi": false
+  }
+}
diff --git a/tests/performance/linpack_float/linpack_float.ino b/tests/performance/linpack_float/linpack_float.ino
new file mode 100644
index 00000000000..24dd9e7c461
--- /dev/null
+++ b/tests/performance/linpack_float/linpack_float.ino
@@ -0,0 +1,1094 @@
+/*
+  Linpack test for Arduino and ESP32.
+  Based on https://github.com/VioletGiraffe/EmbeddedLinpack
+  Created by Violet Giraffe, 2018
+  Adapted by Lucas Saavedra Vaz, 2024
+*/
+
+#include <Arduino.h>
+#include <math.h>
+
+// Number of runs to average
+#define N_RUNS 1000
+
+using floating_point_t = float;
+bool type_float;
+
+floating_point_t benchmark(void);
+floating_point_t cpu_time(void);
+void daxpy(int n, floating_point_t da, floating_point_t dx[], int incx, floating_point_t dy[], int incy);
+floating_point_t ddot(int n, floating_point_t dx[], int incx, floating_point_t dy[], int incy);
+int dgefa(floating_point_t a[], int lda, int n, int ipvt[]);
+void dgesl(floating_point_t a[], int lda, int n, int ipvt[], floating_point_t b[], int job);
+void dscal(int n, floating_point_t sa, floating_point_t x[], int incx);
+int idamax(int n, floating_point_t dx[], int incx);
+floating_point_t r8_abs(floating_point_t x);
+floating_point_t r8_epsilon(void);
+floating_point_t r8_max(floating_point_t x, floating_point_t y);
+floating_point_t r8_random(int iseed[4]);
+void r8mat_gen(int lda, int n, floating_point_t *a);
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  String data_type;
+
+  if (sizeof(floating_point_t) == sizeof(float)) {
+    data_type = "float";
+    type_float = true;
+  } else if (sizeof(floating_point_t) == sizeof(double)) {
+    data_type = "double";
+    type_float = false;
+  } else {
+    data_type = "unknown";
+    log_e("Unknown data type size. Aborting.");
+    while (1);
+  }
+
+  log_d("Starting Linpack %s test", data_type.c_str());
+  Serial.printf("Runs: %d\n", N_RUNS);
+  Serial.printf("Type: %s\n", data_type.c_str());
+  Serial.flush();
+  int i = 0;
+
+  floating_point_t minMflops = 1000000000.0, maxMflops = 0.0, avgMflops = 0.0;
+  for (i = 0; i < N_RUNS; ++i) {
+    Serial.printf("Run %d\n", i);
+    const auto mflops = benchmark();
+    avgMflops += mflops;
+    minMflops = fmin(mflops, minMflops);
+    maxMflops = fmax(mflops, maxMflops);
+    Serial.flush();
+  }
+
+  avgMflops /= N_RUNS;
+  Serial.println(String("Runs completed: ") + i);
+  Serial.println(String("Average MFLOPS: ") + avgMflops);
+  Serial.println(String("Min MFLOPS: ") + minMflops);
+  Serial.println(String("Max MFLOPS: ") + maxMflops);
+  Serial.flush();
+}
+
+void loop() {
+  vTaskDelete(NULL);
+}
+
+/******************************************************************************/
+
+floating_point_t benchmark(void)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    MAIN is the main program for LINPACK_BENCH.
+
+  Discussion:
+
+    LINPACK_BENCH drives the floating_point_t precision LINPACK benchmark program.
+
+  Modified:
+
+    25 July 2008
+
+  Parameters:
+
+    N is the problem size.
+*/
+{
+#define N   8
+#define LDA (N + 1)
+
+  static floating_point_t a[N * LDA];
+  static floating_point_t a_max;
+  static floating_point_t b[N];
+  static floating_point_t b_max;
+  const floating_point_t cray = 0.056;
+  static floating_point_t eps;
+  int i;
+  int info;
+  static int ipvt[N];
+  int j;
+  int job;
+  floating_point_t ops;
+  static floating_point_t resid[N];
+  floating_point_t resid_max;
+  [[maybe_unused]]
+  floating_point_t residn;
+  static floating_point_t rhs[N];
+  floating_point_t t1;
+  floating_point_t t2;
+  static floating_point_t time[6];
+  floating_point_t total;
+  floating_point_t x[N];
+
+  log_d("LINPACK_BENCH");
+  log_d("  C version");
+  log_d("  The LINPACK benchmark.");
+  log_d("  Language: C");
+  if (!type_float) {
+    log_d("  Datatype: Double precision real");
+  } else if (type_float) {
+    log_d("  Datatype: Single precision real");
+  } else {
+    log_d("  Datatype: unknown");
+  }
+  log_d("  Matrix order N               = %d", N);
+  log_d("  Leading matrix dimension LDA = %d", LDA);
+
+  ops = (floating_point_t)(2L * N * N * N) / 3.0 + 2.0 * (floating_point_t)((long)N * N);
+
+  /*
+  Allocate space for arrays.
+*/
+  r8mat_gen(LDA, N, a);
+
+  a_max = 0.0;
+  for (j = 0; j < N; j++) {
+    for (i = 0; i < N; i++) {
+      a_max = r8_max(a_max, a[i + j * LDA]);
+    }
+  }
+
+  for (i = 0; i < N; i++) {
+    x[i] = 1.0;
+  }
+
+  for (i = 0; i < N; i++) {
+    b[i] = 0.0;
+    for (j = 0; j < N; j++) {
+      b[i] = b[i] + a[i + j * LDA] * x[j];
+    }
+  }
+  t1 = cpu_time();
+
+  info = dgefa(a, LDA, N, ipvt);
+
+  if (info != 0) {
+    log_d("LINPACK_BENCH - Fatal error!");
+    log_d("  The matrix A is apparently singular.");
+    log_d("  Abnormal end of execution.");
+    return 1;
+  }
+
+  t2 = cpu_time();
+  time[0] = t2 - t1;
+
+  t1 = cpu_time();
+
+  job = 0;
+  dgesl(a, LDA, N, ipvt, b, job);
+
+  t2 = cpu_time();
+  time[1] = t2 - t1;
+
+  total = time[0] + time[1];
+
+  /*
+  Compute a residual to verify results.
+*/
+  r8mat_gen(LDA, N, a);
+
+  for (i = 0; i < N; i++) {
+    x[i] = 1.0;
+  }
+
+  for (i = 0; i < N; i++) {
+    rhs[i] = 0.0;
+    for (j = 0; j < N; j++) {
+      rhs[i] = rhs[i] + a[i + j * LDA] * x[j];
+    }
+  }
+
+  for (i = 0; i < N; i++) {
+    resid[i] = -rhs[i];
+    for (j = 0; j < N; j++) {
+      resid[i] = resid[i] + a[i + j * LDA] * b[j];
+    }
+  }
+
+  resid_max = 0.0;
+  for (i = 0; i < N; i++) {
+    resid_max = r8_max(resid_max, r8_abs(resid[i]));
+  }
+
+  b_max = 0.0;
+  for (i = 0; i < N; i++) {
+    b_max = r8_max(b_max, r8_abs(b[i]));
+  }
+
+  eps = r8_epsilon();
+
+  residn = resid_max / (floating_point_t)N / a_max / b_max / eps;
+
+  time[2] = total;
+  if (0.0 < total) {
+    time[3] = ops / (1.0E+06 * total);
+  } else {
+    time[3] = -1.0;
+  }
+  time[4] = 2.0 / time[3];
+  time[5] = total / cray;
+
+  log_d("");
+  log_d("     Norm. Resid      Resid           MACHEP         X[1]          X[N]");
+  log_d("  %14f  %14f  %14e  %14f  %14f", residn, resid_max, eps, b[0], b[N - 1]);
+  log_d("");
+  log_d("      Factor     Solve      Total     MFLOPS       Unit      Cray-Ratio");
+  log_d("  %9f  %9f  %9f  %9f  %9f  %9f", time[0], time[1], time[2], time[3], time[4], time[5]);
+
+  /*
+  Terminate.
+*/
+  log_d("");
+  log_d("LINPACK_BENCH");
+  log_d("  Normal end of execution.");
+  log_d("");
+
+  return time[3];
+#undef LDA
+#undef N
+}
+/******************************************************************************/
+
+floating_point_t cpu_time(void)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    CPU_TIME returns the current reading on the CPU clock.
+
+  Discussion:
+
+    The CPU time measurements available through this routine are often
+    not very accurate.  In some cases, the accuracy is no better than
+    a hundredth of a second.
+
+  Licensing:
+
+    This code is distributed under the GNU LGPL license.
+
+  Modified:
+
+    06 June 2005
+
+  Author:
+
+    John Burkardt
+
+  Parameters:
+
+    Output, floating_point_t CPU_TIME, the current reading of the CPU clock, in seconds.
+*/
+{
+  floating_point_t value;
+
+  value = (floating_point_t)micros() / (floating_point_t)1000000;
+
+  return value;
+}
+/******************************************************************************/
+
+void daxpy(int n, floating_point_t da, floating_point_t dx[], int incx, floating_point_t dy[], int incy)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DAXPY computes constant times a vector plus a vector.
+
+  Discussion:
+
+    This routine uses unrolled loops for increments equal to one.
+
+  Modified:
+
+    30 March 2007
+
+  Author:
+
+    FORTRAN77 original by Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart.
+    C version by John Burkardt
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, 1979.
+
+    Charles Lawson, Richard Hanson, David Kincaid, Fred Krogh,
+    Basic Linear Algebra Subprograms for Fortran Usage,
+    Algorithm 539,
+    ACM Transactions on Mathematical Software,
+    Volume 5, Number 3, September 1979, pages 308-323.
+
+  Parameters:
+
+    Input, int N, the number of elements in DX and DY.
+
+    Input, floating_point_t DA, the multiplier of DX.
+
+    Input, floating_point_t DX[*], the first vector.
+
+    Input, int INCX, the increment between successive entries of DX.
+
+    Input/output, floating_point_t DY[*], the second vector.
+    On output, DY[*] has been replaced by DY[*] + DA * DX[*].
+
+    Input, int INCY, the increment between successive entries of DY.
+*/
+{
+  int i;
+  int ix;
+  int iy;
+  int m;
+
+  if (n <= 0) {
+    return;
+  }
+
+  if (da == 0.0) {
+    return;
+  }
+  /*
+  Code for unequal increments or equal increments
+  not equal to 1.
+*/
+  if (incx != 1 || incy != 1) {
+    if (0 <= incx) {
+      ix = 0;
+    } else {
+      ix = (-n + 1) * incx;
+    }
+
+    if (0 <= incy) {
+      iy = 0;
+    } else {
+      iy = (-n + 1) * incy;
+    }
+
+    for (i = 0; i < n; i++) {
+      dy[iy] = dy[iy] + da * dx[ix];
+      ix = ix + incx;
+      iy = iy + incy;
+    }
+  }
+  /*
+  Code for both increments equal to 1.
+*/
+  else {
+    m = n % 4;
+
+    for (i = 0; i < m; i++) {
+      dy[i] = dy[i] + da * dx[i];
+    }
+
+    for (i = m; i < n; i = i + 4) {
+      dy[i] = dy[i] + da * dx[i];
+      dy[i + 1] = dy[i + 1] + da * dx[i + 1];
+      dy[i + 2] = dy[i + 2] + da * dx[i + 2];
+      dy[i + 3] = dy[i + 3] + da * dx[i + 3];
+    }
+  }
+  return;
+}
+/******************************************************************************/
+
+floating_point_t ddot(int n, floating_point_t dx[], int incx, floating_point_t dy[], int incy)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DDOT forms the dot product of two vectors.
+
+  Discussion:
+
+    This routine uses unrolled loops for increments equal to one.
+
+  Modified:
+
+    30 March 2007
+
+  Author:
+
+    FORTRAN77 original by Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart.
+    C version by John Burkardt
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, 1979.
+
+    Charles Lawson, Richard Hanson, David Kincaid, Fred Krogh,
+    Basic Linear Algebra Subprograms for Fortran Usage,
+    Algorithm 539,
+    ACM Transactions on Mathematical Software,
+    Volume 5, Number 3, September 1979, pages 308-323.
+
+  Parameters:
+
+    Input, int N, the number of entries in the vectors.
+
+    Input, floating_point_t DX[*], the first vector.
+
+    Input, int INCX, the increment between successive entries in DX.
+
+    Input, floating_point_t DY[*], the second vector.
+
+    Input, int INCY, the increment between successive entries in DY.
+
+    Output, floating_point_t DDOT, the sum of the product of the corresponding
+    entries of DX and DY.
+*/
+{
+  floating_point_t dtemp;
+  int i;
+  int ix;
+  int iy;
+  int m;
+
+  dtemp = 0.0;
+
+  if (n <= 0) {
+    return dtemp;
+  }
+  /*
+  Code for unequal increments or equal increments
+  not equal to 1.
+*/
+  if (incx != 1 || incy != 1) {
+    if (0 <= incx) {
+      ix = 0;
+    } else {
+      ix = (-n + 1) * incx;
+    }
+
+    if (0 <= incy) {
+      iy = 0;
+    } else {
+      iy = (-n + 1) * incy;
+    }
+
+    for (i = 0; i < n; i++) {
+      dtemp = dtemp + dx[ix] * dy[iy];
+      ix = ix + incx;
+      iy = iy + incy;
+    }
+  }
+  /*
+  Code for both increments equal to 1.
+*/
+  else {
+    m = n % 5;
+
+    for (i = 0; i < m; i++) {
+      dtemp = dtemp + dx[i] * dy[i];
+    }
+
+    for (i = m; i < n; i = i + 5) {
+      dtemp = dtemp + dx[i] * dy[i] + dx[i + 1] * dy[i + 1] + dx[i + 2] * dy[i + 2] + dx[i + 3] * dy[i + 3] + dx[i + 4] * dy[i + 4];
+    }
+  }
+  return dtemp;
+}
+/******************************************************************************/
+
+int dgefa(floating_point_t a[], int lda, int n, int ipvt[])
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DGEFA factors a real general matrix.
+
+  Modified:
+
+    16 May 2005
+
+  Author:
+
+    C version by John Burkardt.
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch and Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, (Society for Industrial and Applied Mathematics),
+    3600 University City Science Center,
+    Philadelphia, PA, 19104-2688.
+    ISBN 0-89871-172-X
+
+  Parameters:
+
+    Input/output, floating_point_t A[LDA*N].
+    On input, the matrix to be factored.
+    On output, an upper triangular matrix and the multipliers used to obtain
+    it.  The factorization can be written A=L*U, where L is a product of
+    permutation and unit lower triangular matrices, and U is upper triangular.
+
+    Input, int LDA, the leading dimension of A.
+
+    Input, int N, the order of the matrix A.
+
+    Output, int IPVT[N], the pivot indices.
+
+    Output, int DGEFA, singularity indicator.
+    0, normal value.
+    K, if U(K,K) == 0.  This is not an error condition for this subroutine,
+    but it does indicate that DGESL or DGEDI will divide by zero if called.
+    Use RCOND in DGECO for a reliable indication of singularity.
+*/
+{
+  int info;
+  int j;
+  int k;
+  int l;
+  floating_point_t t;
+  /*
+  Gaussian elimination with partial pivoting.
+*/
+  info = 0;
+
+  for (k = 1; k <= n - 1; k++) {
+    /*
+  Find L = pivot index.
+*/
+    l = idamax(n - k + 1, a + (k - 1) + (k - 1) * lda, 1) + k - 1;
+    ipvt[k - 1] = l;
+    /*
+  Zero pivot implies this column already triangularized.
+*/
+    if (a[l - 1 + (k - 1) * lda] == 0.0) {
+      info = k;
+      continue;
+    }
+    /*
+  Interchange if necessary.
+*/
+    if (l != k) {
+      t = a[l - 1 + (k - 1) * lda];
+      a[l - 1 + (k - 1) * lda] = a[k - 1 + (k - 1) * lda];
+      a[k - 1 + (k - 1) * lda] = t;
+    }
+    /*
+  Compute multipliers.
+*/
+    t = -1.0 / a[k - 1 + (k - 1) * lda];
+
+    dscal(n - k, t, a + k + (k - 1) * lda, 1);
+    /*
+  Row elimination with column indexing.
+*/
+    for (j = k + 1; j <= n; j++) {
+      t = a[l - 1 + (j - 1) * lda];
+      if (l != k) {
+        a[l - 1 + (j - 1) * lda] = a[k - 1 + (j - 1) * lda];
+        a[k - 1 + (j - 1) * lda] = t;
+      }
+      daxpy(n - k, t, a + k + (k - 1) * lda, 1, a + k + (j - 1) * lda, 1);
+    }
+  }
+
+  ipvt[n - 1] = n;
+
+  if (a[n - 1 + (n - 1) * lda] == 0.0) {
+    info = n;
+  }
+
+  return info;
+}
+/******************************************************************************/
+
+void dgesl(floating_point_t a[], int lda, int n, int ipvt[], floating_point_t b[], int job)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DGESL solves a real general linear system A * X = B.
+
+  Discussion:
+
+    DGESL can solve either of the systems A * X = B or A' * X = B.
+
+    The system matrix must have been factored by DGECO or DGEFA.
+
+    A division by zero will occur if the input factor contains a
+    zero on the diagonal.  Technically this indicates singularity
+    but it is often caused by improper arguments or improper
+    setting of LDA.  It will not occur if the subroutines are
+    called correctly and if DGECO has set 0.0 < RCOND
+    or DGEFA has set INFO == 0.
+
+  Modified:
+
+    16 May 2005
+
+  Author:
+
+    C version by John Burkardt.
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch and Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, (Society for Industrial and Applied Mathematics),
+    3600 University City Science Center,
+    Philadelphia, PA, 19104-2688.
+    ISBN 0-89871-172-X
+
+  Parameters:
+
+    Input, floating_point_t A[LDA*N], the output from DGECO or DGEFA.
+
+    Input, int LDA, the leading dimension of A.
+
+    Input, int N, the order of the matrix A.
+
+    Input, int IPVT[N], the pivot vector from DGECO or DGEFA.
+
+    Input/output, floating_point_t B[N].
+    On input, the right hand side vector.
+    On output, the solution vector.
+
+    Input, int JOB.
+    0, solve A * X = B;
+    nonzero, solve A' * X = B.
+*/
+{
+  int k;
+  int l;
+  floating_point_t t;
+  /*
+  Solve A * X = B.
+*/
+  if (job == 0) {
+    for (k = 1; k <= n - 1; k++) {
+      l = ipvt[k - 1];
+      t = b[l - 1];
+
+      if (l != k) {
+        b[l - 1] = b[k - 1];
+        b[k - 1] = t;
+      }
+
+      daxpy(n - k, t, a + k + (k - 1) * lda, 1, b + k, 1);
+    }
+
+    for (k = n; 1 <= k; k--) {
+      b[k - 1] = b[k - 1] / a[k - 1 + (k - 1) * lda];
+      t = -b[k - 1];
+      daxpy(k - 1, t, a + 0 + (k - 1) * lda, 1, b, 1);
+    }
+  }
+  /*
+  Solve A' * X = B.
+*/
+  else {
+    for (k = 1; k <= n; k++) {
+      t = ddot(k - 1, a + 0 + (k - 1) * lda, 1, b, 1);
+      b[k - 1] = (b[k - 1] - t) / a[k - 1 + (k - 1) * lda];
+    }
+
+    for (k = n - 1; 1 <= k; k--) {
+      b[k - 1] = b[k - 1] + ddot(n - k, a + k + (k - 1) * lda, 1, b + k, 1);
+      l = ipvt[k - 1];
+
+      if (l != k) {
+        t = b[l - 1];
+        b[l - 1] = b[k - 1];
+        b[k - 1] = t;
+      }
+    }
+  }
+  return;
+}
+/******************************************************************************/
+
+void dscal(int n, floating_point_t sa, floating_point_t x[], int incx)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    DSCAL scales a vector by a constant.
+
+  Modified:
+
+    30 March 2007
+
+  Author:
+
+    FORTRAN77 original by Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart.
+    C version by John Burkardt
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, 1979.
+
+    Charles Lawson, Richard Hanson, David Kincaid, Fred Krogh,
+    Basic Linear Algebra Subprograms for Fortran Usage,
+    Algorithm 539,
+    ACM Transactions on Mathematical Software,
+    Volume 5, Number 3, September 1979, pages 308-323.
+
+  Parameters:
+
+    Input, int N, the number of entries in the vector.
+
+    Input, floating_point_t SA, the multiplier.
+
+    Input/output, floating_point_t X[*], the vector to be scaled.
+
+    Input, int INCX, the increment between successive entries of X.
+*/
+{
+  int i;
+  int ix;
+  int m;
+
+  if (n <= 0) {
+  } else if (incx == 1) {
+    m = n % 5;
+
+    for (i = 0; i < m; i++) {
+      x[i] = sa * x[i];
+    }
+
+    for (i = m; i < n; i = i + 5) {
+      x[i] = sa * x[i];
+      x[i + 1] = sa * x[i + 1];
+      x[i + 2] = sa * x[i + 2];
+      x[i + 3] = sa * x[i + 3];
+      x[i + 4] = sa * x[i + 4];
+    }
+  } else {
+    if (0 <= incx) {
+      ix = 0;
+    } else {
+      ix = (-n + 1) * incx;
+    }
+
+    for (i = 0; i < n; i++) {
+      x[ix] = sa * x[ix];
+      ix = ix + incx;
+    }
+  }
+  return;
+}
+/******************************************************************************/
+
+int idamax(int n, floating_point_t dx[], int incx)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    IDAMAX finds the index of the vector element of maximum absolute value.
+
+  Discussion:
+
+    WARNING: This index is a 1-based index, not a 0-based index!
+
+  Modified:
+
+    30 March 2007
+
+  Author:
+
+    FORTRAN77 original by Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart.
+    C version by John Burkardt
+
+  Reference:
+
+    Jack Dongarra, Cleve Moler, Jim Bunch, Pete Stewart,
+    LINPACK User's Guide,
+    SIAM, 1979.
+
+    Charles Lawson, Richard Hanson, David Kincaid, Fred Krogh,
+    Basic Linear Algebra Subprograms for Fortran Usage,
+    Algorithm 539,
+    ACM Transactions on Mathematical Software,
+    Volume 5, Number 3, September 1979, pages 308-323.
+
+  Parameters:
+
+    Input, int N, the number of entries in the vector.
+
+    Input, floating_point_t X[*], the vector to be examined.
+
+    Input, int INCX, the increment between successive entries of SX.
+
+    Output, int IDAMAX, the index of the element of maximum
+    absolute value.
+*/
+{
+  floating_point_t dmax;
+  int i;
+  int ix;
+  int value;
+
+  value = 0;
+
+  if (n < 1 || incx <= 0) {
+    return value;
+  }
+
+  value = 1;
+
+  if (n == 1) {
+    return value;
+  }
+
+  if (incx == 1) {
+    dmax = r8_abs(dx[0]);
+
+    for (i = 1; i < n; i++) {
+      if (dmax < r8_abs(dx[i])) {
+        value = i + 1;
+        dmax = r8_abs(dx[i]);
+      }
+    }
+  } else {
+    ix = 0;
+    dmax = r8_abs(dx[0]);
+    ix = ix + incx;
+
+    for (i = 1; i < n; i++) {
+      if (dmax < r8_abs(dx[ix])) {
+        value = i + 1;
+        dmax = r8_abs(dx[ix]);
+      }
+      ix = ix + incx;
+    }
+  }
+
+  return value;
+}
+/******************************************************************************/
+
+floating_point_t r8_abs(floating_point_t x)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8_ABS returns the absolute value of a R8.
+
+  Modified:
+
+    02 April 2005
+
+  Author:
+
+    John Burkardt
+
+  Parameters:
+
+    Input, floating_point_t X, the quantity whose absolute value is desired.
+
+    Output, floating_point_t R8_ABS, the absolute value of X.
+*/
+{
+  floating_point_t value;
+
+  if (0.0 <= x) {
+    value = x;
+  } else {
+    value = -x;
+  }
+  return value;
+}
+/******************************************************************************/
+
+floating_point_t r8_epsilon(void)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8_EPSILON returns the R8 round off unit.
+
+  Discussion:
+
+    R8_EPSILON is a number R which is a power of 2 with the property that,
+    to the precision of the computer's arithmetic,
+      1 < 1 + R
+    but
+      1 = ( 1 + R / 2 )
+
+  Licensing:
+
+    This code is distributed under the GNU LGPL license.
+
+  Modified:
+
+    08 May 2006
+
+  Author:
+
+    John Burkardt
+
+  Parameters:
+
+    Output, floating_point_t R8_EPSILON, the floating_point_t precision round-off unit.
+*/
+{
+  floating_point_t r;
+
+  r = 1.0;
+
+  while (1.0 < (floating_point_t)(1.0 + r)) {
+    r = r / 2.0;
+  }
+  r = 2.0 * r;
+
+  return r;
+}
+/******************************************************************************/
+
+floating_point_t r8_max(floating_point_t x, floating_point_t y)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8_MAX returns the maximum of two R8's.
+
+  Modified:
+
+    18 August 2004
+
+  Author:
+
+    John Burkardt
+
+  Parameters:
+
+    Input, floating_point_t X, Y, the quantities to compare.
+
+    Output, floating_point_t R8_MAX, the maximum of X and Y.
+*/
+{
+  floating_point_t value;
+
+  if (y < x) {
+    value = x;
+  } else {
+    value = y;
+  }
+  return value;
+}
+/******************************************************************************/
+
+floating_point_t r8_random(int iseed[4])
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8_RANDOM returns a uniformly distributed random number between 0 and 1.
+
+  Discussion:
+
+    This routine uses a multiplicative congruential method with modulus
+    2**48 and multiplier 33952834046453 (see G.S.Fishman,
+    'Multiplicative congruential random number generators with modulus
+    2**b: an exhaustive analysis for b = 32 and a partial analysis for
+    b = 48', Math. Comp. 189, pp 331-344, 1990).
+
+    48-bit integers are stored in 4 integer array elements with 12 bits
+    per element. Hence the routine is portable across machines with
+    integers of 32 bits or more.
+
+  Parameters:
+
+    Input/output, integer ISEED(4).
+    On entry, the seed of the random number generator; the array
+    elements must be between 0 and 4095, and ISEED(4) must be odd.
+    On exit, the seed is updated.
+
+    Output, floating_point_t R8_RANDOM, the next pseudorandom number.
+*/
+{
+  int ipw2 = 4096;
+  int it1;
+  int it2;
+  int it3;
+  int it4;
+  int m1 = 494;
+  int m2 = 322;
+  int m3 = 2508;
+  int m4 = 2549;
+  floating_point_t r = 1.0 / 4096.0;
+  floating_point_t value;
+  /*
+  Multiply the seed by the multiplier modulo 2**48.
+*/
+  it4 = iseed[3] * m4;
+  it3 = it4 / ipw2;
+  it4 = it4 - ipw2 * it3;
+  it3 = it3 + iseed[2] * m4 + iseed[3] * m3;
+  it2 = it3 / ipw2;
+  it3 = it3 - ipw2 * it2;
+  it2 = it2 + iseed[1] * m4 + iseed[2] * m3 + iseed[3] * m2;
+  it1 = it2 / ipw2;
+  it2 = it2 - ipw2 * it1;
+  it1 = it1 + iseed[0] * m4 + iseed[1] * m3 + iseed[2] * m2 + iseed[3] * m1;
+  it1 = (it1 % ipw2);
+  /*
+  Return updated seed
+*/
+  iseed[0] = it1;
+  iseed[1] = it2;
+  iseed[2] = it3;
+  iseed[3] = it4;
+  /*
+  Convert 48-bit integer to a real number in the interval (0,1)
+*/
+  value = r * ((floating_point_t)(it1) + r * ((floating_point_t)(it2) + r * ((floating_point_t)(it3) + r * ((floating_point_t)(it4)))));
+
+  return value;
+}
+/******************************************************************************/
+
+void r8mat_gen(int lda, int n, floating_point_t *a)
+
+/******************************************************************************/
+/*
+  Purpose:
+
+    R8MAT_GEN generates a random R8MAT.
+
+  Modified:
+
+    06 June 2005
+
+  Parameters:
+
+    Input, integer LDA, the leading dimension of the matrix.
+
+    Input, integer N, the order of the matrix.
+
+    Output, floating_point_t R8MAT_GEN[LDA*N], the N by N matrix.
+*/
+{
+  int i;
+  int init[4] = {1, 2, 3, 1325};
+  int j;
+
+  for (j = 1; j <= n; j++) {
+    for (i = 1; i <= n; i++) {
+      a[i - 1 + (j - 1) * lda] = r8_random(init) - 0.5;
+    }
+  }
+}
+/******************************************************************************/
diff --git a/tests/performance/linpack_float/test_linpack_float.py b/tests/performance/linpack_float/test_linpack_float.py
new file mode 100644
index 00000000000..d11f6c74136
--- /dev/null
+++ b/tests/performance/linpack_float/test_linpack_float.py
@@ -0,0 +1,61 @@
+import json
+import logging
+import os
+
+
+def test_linpack_float(dut, request):
+    LOGGER = logging.getLogger(__name__)
+
+    # Match "Runs: %d"
+    res = dut.expect(r"Runs: (\d+)", timeout=60)
+    runs = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of runs: {}".format(runs))
+    assert runs > 0, "Invalid number of runs"
+
+    # Match "Type: %s"
+    res = dut.expect(r"Type: (\w+)", timeout=60)
+    data_type = res.group(0).decode("utf-8").split(" ")[1]
+    LOGGER.info("Data type: {}".format(data_type))
+    assert data_type == "float", "Invalid data type"
+
+    # Match "Runs completed: %d"
+    res = dut.expect(r"Runs completed: (\d+)", timeout=120)
+    runs_completed = int(res.group(0).decode("utf-8").split(" ")[2])
+    LOGGER.info("Runs completed: {}".format(runs_completed))
+    assert runs_completed == runs, "Invalid number of runs completed"
+
+    # Match "Average MFLOPS: %f"
+    res = dut.expect(r"Average MFLOPS: (\d+\.\d+)", timeout=120)
+    avg_score = float(res.group(0).decode("utf-8").split(" ")[2])
+    LOGGER.info("Average MFLOPS: {}".format(avg_score))
+    assert avg_score > 0, "Invalid average MFLOPS"
+
+    # Match "Min MFLOPS: %f"
+    res = dut.expect(r"Min MFLOPS: (\d+\.\d+)", timeout=120)
+    min_score = float(res.group(0).decode("utf-8").split(" ")[2])
+    LOGGER.info("Min MFLOPS: {}".format(min_score))
+    assert min_score > 0 and min_score < 1000000000.0, "Invalid min MFLOPS"
+
+    # Match "Max MFLOPS: %f"
+    res = dut.expect(r"Max MFLOPS: (\d+\.\d+)", timeout=120)
+    max_score = float(res.group(0).decode("utf-8").split(" ")[2])
+    LOGGER.info("Max MFLOPS: {}".format(max_score))
+    assert max_score > 0, "Invalid max MFLOPS"
+
+    # Create JSON with results and write it to file
+    # Always create a JSON with this format (so it can be merged later on):
+    # { TEST_NAME_STR: TEST_RESULTS_DICT }
+    results = {"linpack_float": {"runs": runs, "avg_score": avg_score, "min_score": min_score, "max_score": max_score}}
+
+    current_folder = os.path.dirname(request.path)
+    file_index = 0
+    report_file = os.path.join(current_folder, "result_linpack_float" + str(file_index) + ".json")
+    while os.path.exists(report_file):
+        report_file = report_file.replace(str(file_index) + ".json", str(file_index + 1) + ".json")
+        file_index += 1
+
+    with open(report_file, "w") as f:
+        try:
+            f.write(json.dumps(results))
+        except Exception as e:
+            LOGGER.warning("Failed to write results to file: {}".format(e))
diff --git a/tests/performance/psramspeed/ci.json b/tests/performance/psramspeed/ci.json
new file mode 100644
index 00000000000..341df103671
--- /dev/null
+++ b/tests/performance/psramspeed/ci.json
@@ -0,0 +1,9 @@
+{
+  "platforms": {
+    "qemu": false,
+    "wokwi": false
+  },
+  "requires": [
+    "CONFIG_SPIRAM=y"
+  ]
+}
diff --git a/tests/performance/psramspeed/psramspeed.ino b/tests/performance/psramspeed/psramspeed.ino
new file mode 100644
index 00000000000..be91733abfc
--- /dev/null
+++ b/tests/performance/psramspeed/psramspeed.ino
@@ -0,0 +1,266 @@
+/*
+  Based on the ramspeed test from NuttX.
+  https://github.com/apache/nuttx-apps/blob/master/benchmarks/ramspeed/ramspeed_main.c
+  Modified for Arduino and ESP32 by Lucas Saavedra Vaz, 2024
+*/
+
+#include <Arduino.h>
+
+// Test settings
+
+// Number of runs to average
+#define N_RUNS 3
+
+// Value to fill the memory with
+#define FILL_VALUE 0x00
+
+// Number of copies to be performed in each test
+#define N_COPIES 400
+
+// Start size for the tests. Value must be a power of 2.
+// Values lower or equal than 32 KB may cause the operations to use the cache instead of the PSRAM.
+#define START_SIZE 65536
+
+// Max size to be copied. Must be bigger than 32 and it will be floored to the nearest power of 2
+#define MAX_TEST_SIZE 512 * 1024  // 512KB
+
+// Implementation macros
+
+#if defined(UINTPTR_MAX) && UINTPTR_MAX > 0xFFFFFFFF
+#define MEM_UNIT   uint64_t
+#define ALIGN_MASK 0x7
+#else
+#define MEM_UNIT   uint32_t
+#define ALIGN_MASK 0x3
+#endif
+
+#define COPY32 \
+  *d32 = *s32; \
+  d32++;       \
+  s32++;
+#define COPY8 \
+  *d8 = *s8;  \
+  d8++;       \
+  s8++;
+#define SET32(x) \
+  *d32 = x;      \
+  d32++;
+#define SET8(x) \
+  *d8 = x;      \
+  d8++;
+#define REPEAT8(expr) expr expr expr expr expr expr expr expr
+
+/* Functions */
+
+static void *mock_memcpy(void *dst, const void *src, size_t len) {
+  uint8_t *d8 = (uint8_t *)dst;
+  const uint8_t *s8 = (uint8_t *)src;
+
+  uintptr_t d_align = (uintptr_t)d8 & ALIGN_MASK;
+  uintptr_t s_align = (uintptr_t)s8 & ALIGN_MASK;
+  uint32_t *d32;
+  const uint32_t *s32;
+
+  /* Byte copy for unaligned memories */
+
+  if (s_align != d_align) {
+    while (len > 32) {
+      REPEAT8(COPY8);
+      REPEAT8(COPY8);
+      REPEAT8(COPY8);
+      REPEAT8(COPY8);
+      len -= 32;
+    }
+
+    while (len) {
+      COPY8;
+      len--;
+    }
+
+    return dst;
+  }
+
+  /* Make the memories aligned */
+
+  if (d_align) {
+    d_align = ALIGN_MASK + 1 - d_align;
+    while (d_align && len) {
+      COPY8;
+      d_align--;
+      len--;
+    }
+  }
+
+  d32 = (uint32_t *)d8;
+  s32 = (uint32_t *)s8;
+  while (len > 32) {
+    REPEAT8(COPY32);
+    len -= 32;
+  }
+
+  while (len > 4) {
+    COPY32;
+    len -= 4;
+  }
+
+  d8 = (uint8_t *)d32;
+  s8 = (const uint8_t *)s32;
+  while (len) {
+    COPY8;
+    len--;
+  }
+
+  return dst;
+}
+
+static void mock_memset(void *dst, uint8_t v, size_t len) {
+  uint8_t *d8 = (uint8_t *)dst;
+  uintptr_t d_align = (uintptr_t)d8 & ALIGN_MASK;
+  uint32_t v32;
+  uint32_t *d32;
+
+  /* Make the address aligned */
+
+  if (d_align) {
+    d_align = ALIGN_MASK + 1 - d_align;
+    while (d_align && len) {
+      SET8(v);
+      len--;
+      d_align--;
+    }
+  }
+
+  v32 = (uint32_t)v + ((uint32_t)v << 8) + ((uint32_t)v << 16) + ((uint32_t)v << 24);
+
+  d32 = (uint32_t *)d8;
+
+  while (len > 32) {
+    REPEAT8(SET32(v32));
+    len -= 32;
+  }
+
+  while (len > 4) {
+    SET32(v32);
+    len -= 4;
+  }
+
+  d8 = (uint8_t *)d32;
+  while (len) {
+    SET8(v);
+    len--;
+  }
+}
+
+static void print_rate(const char *name, uint64_t bytes, uint32_t cost_time) {
+  uint32_t rate;
+  if (cost_time == 0) {
+    Serial.println("Error: Too little time taken, please increase N_COPIES");
+    return;
+  }
+
+  rate = bytes * 1000 / cost_time / 1024;
+  Serial.printf("%s Rate = %" PRIu32 " KB/s Time: %" PRIu32 " ms\n", name, rate, cost_time);
+}
+
+static void memcpy_speed_test(void *dest, const void *src, size_t size, uint32_t repeat_cnt) {
+  uint32_t start_time;
+  uint32_t cost_time_system;
+  uint32_t cost_time_mock;
+  uint32_t cnt;
+  uint32_t step;
+  uint64_t total_size;
+
+  for (step = START_SIZE; step <= size; step <<= 1) {
+    total_size = (uint64_t)step * (uint64_t)repeat_cnt;
+
+    Serial.printf("Memcpy %" PRIu32 " Bytes test\n", step);
+
+    start_time = millis();
+
+    for (cnt = 0; cnt < repeat_cnt; cnt++) {
+      memcpy(dest, src, step);
+    }
+
+    cost_time_system = millis() - start_time;
+
+    start_time = millis();
+
+    for (cnt = 0; cnt < repeat_cnt; cnt++) {
+      mock_memcpy(dest, src, step);
+    }
+
+    cost_time_mock = millis() - start_time;
+
+    print_rate("System memcpy():", total_size, cost_time_system);
+    print_rate("Mock memcpy():", total_size, cost_time_mock);
+  }
+}
+
+static void memset_speed_test(void *dest, uint8_t value, size_t size, uint32_t repeat_num) {
+  uint32_t start_time;
+  uint32_t cost_time_system;
+  uint32_t cost_time_mock;
+  uint32_t cnt;
+  uint32_t step;
+  uint64_t total_size;
+
+  for (step = START_SIZE; step <= size; step <<= 1) {
+    total_size = (uint64_t)step * (uint64_t)repeat_num;
+
+    Serial.printf("Memset %" PRIu32 " Bytes test\n", step);
+
+    start_time = millis();
+
+    for (cnt = 0; cnt < repeat_num; cnt++) {
+      memset(dest, value, step);
+    }
+
+    cost_time_system = millis() - start_time;
+
+    start_time = millis();
+
+    for (cnt = 0; cnt < repeat_num; cnt++) {
+      mock_memset(dest, value, step);
+    }
+
+    cost_time_mock = millis() - start_time;
+
+    print_rate("System memset():", total_size, cost_time_system);
+    print_rate("Mock memset():", total_size, cost_time_mock);
+  }
+}
+
+/* Main */
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  void *dest = ps_malloc(MAX_TEST_SIZE);
+  const void *src = ps_malloc(MAX_TEST_SIZE);
+
+  if (!dest || !src) {
+    Serial.println("Memory allocation failed");
+    return;
+  }
+
+  log_d("Starting PSRAM speed test");
+  Serial.printf("Runs: %d\n", N_RUNS);
+  Serial.printf("Copies: %d\n", N_COPIES);
+  Serial.printf("Max test size: %d\n", MAX_TEST_SIZE);
+  Serial.flush();
+  for (int i = 0; i < N_RUNS; i++) {
+    Serial.printf("Run %d\n", i);
+    memcpy_speed_test(dest, src, MAX_TEST_SIZE, N_COPIES);
+    Serial.flush();
+    memset_speed_test(dest, FILL_VALUE, MAX_TEST_SIZE, N_COPIES);
+    Serial.flush();
+  }
+  log_d("PSRAM speed test done");
+}
+
+void loop() {
+  vTaskDelete(NULL);
+}
diff --git a/tests/performance/psramspeed/test_psramspeed.py b/tests/performance/psramspeed/test_psramspeed.py
new file mode 100644
index 00000000000..9e96e158504
--- /dev/null
+++ b/tests/performance/psramspeed/test_psramspeed.py
@@ -0,0 +1,105 @@
+import json
+import logging
+import os
+
+from collections import defaultdict
+
+
+def test_psramspeed(dut, request):
+    LOGGER = logging.getLogger(__name__)
+
+    runs_results = []
+
+    # Match "Runs: %d"
+    res = dut.expect(r"Runs: (\d+)", timeout=60)
+    runs = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of runs: {}".format(runs))
+    assert runs > 0, "Invalid number of runs"
+
+    # Match "Copies: %d"
+    res = dut.expect(r"Copies: (\d+)", timeout=60)
+    copies = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of copies in each test: {}".format(copies))
+    assert copies > 0, "Invalid number of copies"
+
+    # Match "Max test size: %lu"
+    res = dut.expect(r"Max test size: (\d+)", timeout=60)
+    max_test_size = int(res.group(0).decode("utf-8").split(" ")[3])
+    LOGGER.info("Max test size: {}".format(max_test_size))
+    assert max_test_size > 0, "Invalid max test size"
+
+    for i in range(runs):
+        # Match "Run %d"
+        res = dut.expect(r"Run (\d+)", timeout=120)
+        run = int(res.group(0).decode("utf-8").split(" ")[1])
+        LOGGER.info("Run {}".format(run))
+        assert run == i, "Invalid run number"
+
+        for j in range(2):
+            while True:
+                # Match "Memcpy/Memtest %d Bytes test"
+                res = dut.expect(r"(Memcpy|Memset) (\d+) Bytes test", timeout=60)
+                current_test = res.group(0).decode("utf-8").split(" ")[0].lower()
+                current_test_size = int(res.group(0).decode("utf-8").split(" ")[1])
+                LOGGER.info("Current {} test size: {}".format(current_test, current_test_size))
+                assert current_test_size > 0, "Invalid test size"
+
+                for k in range(2):
+                    # Match "System/Mock memcpy/memtest(): Rate = %d KB/s Time: %d ms" or "Error: %s"
+                    res = dut.expect(
+                        r"((System|Mock) (memcpy|memset)\(\): Rate = (\d+) KB/s Time: (\d+) ms|^Error)", timeout=90
+                    )
+                    implementation = res.group(0).decode("utf-8").split(" ")[0].lower()
+                    assert implementation != "error:", "Error detected in test output"
+                    test_type = res.group(0).decode("utf-8").split(" ")[1].lower()[:-3]
+                    rate = int(res.group(0).decode("utf-8").split(" ")[4])
+                    time = int(res.group(0).decode("utf-8").split(" ")[7])
+                    assert rate > 0, "Invalid rate"
+                    assert time > 0, "Invalid time"
+                    assert test_type == current_test, "Missing test output"
+                    LOGGER.info("{} {}: Rate = {} KB/s. Time = {} ms".format(implementation, test_type, rate, time))
+
+                    runs_results.append(((current_test, str(current_test_size), implementation), (rate, time)))
+
+                if current_test_size == max_test_size:
+                    break
+
+            LOGGER.info("=============================================================")
+
+    # Calculate average rate and time for each test size
+    sums = defaultdict(lambda: {"rate_sum": 0, "time_sum": 0})
+
+    for (test, size, impl), (rate, time) in runs_results:
+        sums[(test, size, impl)]["rate_sum"] += rate
+        sums[(test, size, impl)]["time_sum"] += time
+
+    avg_results = {}
+    for test, size, impl in sums:
+        rate_avg = round(sums[(test, size, impl)]["rate_sum"] / runs, 2)
+        time_avg = round(sums[(test, size, impl)]["time_sum"] / runs, 2)
+        LOGGER.info(
+            "Test: {}-{}-{}: Average rate = {} KB/s. Average time = {} ms".format(test, size, impl, rate_avg, time_avg)
+        )
+        if test not in avg_results:
+            avg_results[test] = {}
+        if size not in avg_results[test]:
+            avg_results[test][size] = {}
+        avg_results[test][size][impl] = {"avg_rate": rate_avg, "avg_time": time_avg}
+
+    # Create JSON with results and write it to file
+    # Always create a JSON with this format (so it can be merged later on):
+    # { TEST_NAME_STR: TEST_RESULTS_DICT }
+    results = {"psramspeed": {"runs": runs, "copies": copies, "max_test_size": max_test_size, "results": avg_results}}
+
+    current_folder = os.path.dirname(request.path)
+    file_index = 0
+    report_file = os.path.join(current_folder, "result_psramspeed" + str(file_index) + ".json")
+    while os.path.exists(report_file):
+        report_file = report_file.replace(str(file_index) + ".json", str(file_index + 1) + ".json")
+        file_index += 1
+
+    with open(report_file, "w") as f:
+        try:
+            f.write(json.dumps(results))
+        except Exception as e:
+            LOGGER.warning("Failed to write results to file: {}".format(e))
diff --git a/tests/performance/ramspeed/ci.json b/tests/performance/ramspeed/ci.json
new file mode 100644
index 00000000000..d880ca64dfb
--- /dev/null
+++ b/tests/performance/ramspeed/ci.json
@@ -0,0 +1,17 @@
+{
+  "fqbn": {
+    "esp32": [
+      "espressif:esp32:esp32:PSRAM=disabled,PartitionScheme=huge_app"
+    ],
+    "esp32s2": [
+      "espressif:esp32:esp32s2:PSRAM=disabled,PartitionScheme=huge_app"
+    ],
+    "esp32s3": [
+      "espressif:esp32:esp32s3:PSRAM=disabled,USBMode=default,PartitionScheme=huge_app"
+    ]
+  },
+  "platform": {
+    "qemu": false,
+    "wokwi": false
+  }
+}
diff --git a/tests/performance/ramspeed/ramspeed.ino b/tests/performance/ramspeed/ramspeed.ino
new file mode 100644
index 00000000000..776f6540679
--- /dev/null
+++ b/tests/performance/ramspeed/ramspeed.ino
@@ -0,0 +1,262 @@
+/*
+  Based on the ramspeed test from NuttX.
+  https://github.com/apache/nuttx-apps/blob/master/benchmarks/ramspeed/ramspeed_main.c
+  Modified for Arduino and ESP32 by Lucas Saavedra Vaz, 2024
+*/
+
+#include <Arduino.h>
+
+// Test settings
+
+// Number of runs to average
+#define N_RUNS 3
+
+// Value to fill the memory with
+#define FILL_VALUE 0x00
+
+// Number of copies to be performed in each test
+#define N_COPIES 50000
+
+// Max size to be copied. Must be bigger than 32 and it will be floored to the nearest power of 2
+#define MAX_TEST_SIZE 64 * 1024  // 64KB
+
+// Implementation macros
+
+#if defined(UINTPTR_MAX) && UINTPTR_MAX > 0xFFFFFFFF
+#define MEM_UNIT   uint64_t
+#define ALIGN_MASK 0x7
+#else
+#define MEM_UNIT   uint32_t
+#define ALIGN_MASK 0x3
+#endif
+
+#define COPY32 \
+  *d32 = *s32; \
+  d32++;       \
+  s32++;
+#define COPY8 \
+  *d8 = *s8;  \
+  d8++;       \
+  s8++;
+#define SET32(x) \
+  *d32 = x;      \
+  d32++;
+#define SET8(x) \
+  *d8 = x;      \
+  d8++;
+#define REPEAT8(expr) expr expr expr expr expr expr expr expr
+
+/* Functions */
+
+static void *mock_memcpy(void *dst, const void *src, size_t len) {
+  uint8_t *d8 = (uint8_t *)dst;
+  const uint8_t *s8 = (uint8_t *)src;
+
+  uintptr_t d_align = (uintptr_t)d8 & ALIGN_MASK;
+  uintptr_t s_align = (uintptr_t)s8 & ALIGN_MASK;
+  uint32_t *d32;
+  const uint32_t *s32;
+
+  /* Byte copy for unaligned memories */
+
+  if (s_align != d_align) {
+    while (len > 32) {
+      REPEAT8(COPY8);
+      REPEAT8(COPY8);
+      REPEAT8(COPY8);
+      REPEAT8(COPY8);
+      len -= 32;
+    }
+
+    while (len) {
+      COPY8;
+      len--;
+    }
+
+    return dst;
+  }
+
+  /* Make the memories aligned */
+
+  if (d_align) {
+    d_align = ALIGN_MASK + 1 - d_align;
+    while (d_align && len) {
+      COPY8;
+      d_align--;
+      len--;
+    }
+  }
+
+  d32 = (uint32_t *)d8;
+  s32 = (uint32_t *)s8;
+  while (len > 32) {
+    REPEAT8(COPY32);
+    len -= 32;
+  }
+
+  while (len > 4) {
+    COPY32;
+    len -= 4;
+  }
+
+  d8 = (uint8_t *)d32;
+  s8 = (const uint8_t *)s32;
+  while (len) {
+    COPY8;
+    len--;
+  }
+
+  return dst;
+}
+
+static void mock_memset(void *dst, uint8_t v, size_t len) {
+  uint8_t *d8 = (uint8_t *)dst;
+  uintptr_t d_align = (uintptr_t)d8 & ALIGN_MASK;
+  uint32_t v32;
+  uint32_t *d32;
+
+  /* Make the address aligned */
+
+  if (d_align) {
+    d_align = ALIGN_MASK + 1 - d_align;
+    while (d_align && len) {
+      SET8(v);
+      len--;
+      d_align--;
+    }
+  }
+
+  v32 = (uint32_t)v + ((uint32_t)v << 8) + ((uint32_t)v << 16) + ((uint32_t)v << 24);
+
+  d32 = (uint32_t *)d8;
+
+  while (len > 32) {
+    REPEAT8(SET32(v32));
+    len -= 32;
+  }
+
+  while (len > 4) {
+    SET32(v32);
+    len -= 4;
+  }
+
+  d8 = (uint8_t *)d32;
+  while (len) {
+    SET8(v);
+    len--;
+  }
+}
+
+static void print_rate(const char *name, uint64_t bytes, uint32_t cost_time) {
+  uint32_t rate;
+  if (cost_time == 0) {
+    Serial.println("Error: Too little time taken, please increase N_COPIES");
+    return;
+  }
+
+  rate = bytes * 1000 / cost_time / 1024;
+  Serial.printf("%s Rate = %" PRIu32 " KB/s Time: %" PRIu32 " ms\n", name, rate, cost_time);
+}
+
+static void memcpy_speed_test(void *dest, const void *src, size_t size, uint32_t repeat_cnt) {
+  uint32_t start_time;
+  uint32_t cost_time_system;
+  uint32_t cost_time_mock;
+  uint32_t cnt;
+  uint32_t step;
+  uint64_t total_size;
+
+  for (step = 32; step <= size; step <<= 1) {
+    total_size = (uint64_t)step * (uint64_t)repeat_cnt;
+
+    Serial.printf("Memcpy %" PRIu32 " Bytes test\n", step);
+
+    start_time = millis();
+
+    for (cnt = 0; cnt < repeat_cnt; cnt++) {
+      memcpy(dest, src, step);
+    }
+
+    cost_time_system = millis() - start_time;
+
+    start_time = millis();
+
+    for (cnt = 0; cnt < repeat_cnt; cnt++) {
+      mock_memcpy(dest, src, step);
+    }
+
+    cost_time_mock = millis() - start_time;
+
+    print_rate("System memcpy():", total_size, cost_time_system);
+    print_rate("Mock memcpy():", total_size, cost_time_mock);
+  }
+}
+
+static void memset_speed_test(void *dest, uint8_t value, size_t size, uint32_t repeat_num) {
+  uint32_t start_time;
+  uint32_t cost_time_system;
+  uint32_t cost_time_mock;
+  uint32_t cnt;
+  uint32_t step;
+  uint64_t total_size;
+
+  for (step = 32; step <= size; step <<= 1) {
+    total_size = (uint64_t)step * (uint64_t)repeat_num;
+
+    Serial.printf("Memset %" PRIu32 " Bytes test\n", step);
+
+    start_time = millis();
+
+    for (cnt = 0; cnt < repeat_num; cnt++) {
+      memset(dest, value, step);
+    }
+
+    cost_time_system = millis() - start_time;
+
+    start_time = millis();
+
+    for (cnt = 0; cnt < repeat_num; cnt++) {
+      mock_memset(dest, value, step);
+    }
+
+    cost_time_mock = millis() - start_time;
+
+    print_rate("System memset():", total_size, cost_time_system);
+    print_rate("Mock memset():", total_size, cost_time_mock);
+  }
+}
+
+/* Main */
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  void *dest = malloc(MAX_TEST_SIZE);
+  const void *src = malloc(MAX_TEST_SIZE);
+
+  if (!dest || !src) {
+    Serial.println("Memory allocation failed");
+    return;
+  }
+
+  log_d("Starting RAM speed test");
+  Serial.printf("Runs: %d\n", N_RUNS);
+  Serial.printf("Copies: %d\n", N_COPIES);
+  Serial.printf("Max test size: %d\n", MAX_TEST_SIZE);
+  Serial.flush();
+  for (int i = 0; i < N_RUNS; i++) {
+    Serial.printf("Run %d\n", i);
+    memcpy_speed_test(dest, src, MAX_TEST_SIZE, N_COPIES);
+    Serial.flush();
+    memset_speed_test(dest, FILL_VALUE, MAX_TEST_SIZE, N_COPIES);
+    Serial.flush();
+  }
+  log_d("RAM speed test done");
+}
+
+void loop() {
+  vTaskDelete(NULL);
+}
diff --git a/tests/performance/ramspeed/test_ramspeed.py b/tests/performance/ramspeed/test_ramspeed.py
new file mode 100644
index 00000000000..dbe1670d329
--- /dev/null
+++ b/tests/performance/ramspeed/test_ramspeed.py
@@ -0,0 +1,105 @@
+import json
+import logging
+import os
+
+from collections import defaultdict
+
+
+def test_ramspeed(dut, request):
+    LOGGER = logging.getLogger(__name__)
+
+    runs_results = []
+
+    # Match "Runs: %d"
+    res = dut.expect(r"Runs: (\d+)", timeout=60)
+    runs = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of runs: {}".format(runs))
+    assert runs > 0, "Invalid number of runs"
+
+    # Match "Copies: %d"
+    res = dut.expect(r"Copies: (\d+)", timeout=60)
+    copies = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of copies in each test: {}".format(copies))
+    assert copies > 0, "Invalid number of copies"
+
+    # Match "Max test size: %lu"
+    res = dut.expect(r"Max test size: (\d+)", timeout=60)
+    max_test_size = int(res.group(0).decode("utf-8").split(" ")[3])
+    LOGGER.info("Max test size: {}".format(max_test_size))
+    assert max_test_size > 0, "Invalid max test size"
+
+    for i in range(runs):
+        # Match "Run %d"
+        res = dut.expect(r"Run (\d+)", timeout=120)
+        run = int(res.group(0).decode("utf-8").split(" ")[1])
+        LOGGER.info("Run {}".format(run))
+        assert run == i, "Invalid run number"
+
+        for j in range(2):
+            while True:
+                # Match "Memcpy/Memtest %d Bytes test"
+                res = dut.expect(r"(Memcpy|Memset) (\d+) Bytes test", timeout=60)
+                current_test = res.group(0).decode("utf-8").split(" ")[0].lower()
+                current_test_size = int(res.group(0).decode("utf-8").split(" ")[1])
+                LOGGER.info("Current {} test size: {}".format(current_test, current_test_size))
+                assert current_test_size > 0, "Invalid test size"
+
+                for k in range(2):
+                    # Match "System/Mock memcpy/memtest(): Rate = %d KB/s Time: %d ms" or "Error: %s"
+                    res = dut.expect(
+                        r"((System|Mock) (memcpy|memset)\(\): Rate = (\d+) KB/s Time: (\d+) ms|^Error)", timeout=90
+                    )
+                    implementation = res.group(0).decode("utf-8").split(" ")[0].lower()
+                    assert implementation != "error:", "Error detected in test output"
+                    test_type = res.group(0).decode("utf-8").split(" ")[1].lower()[:-3]
+                    rate = int(res.group(0).decode("utf-8").split(" ")[4])
+                    time = int(res.group(0).decode("utf-8").split(" ")[7])
+                    assert rate > 0, "Invalid rate"
+                    assert time > 0, "Invalid time"
+                    assert test_type == current_test, "Missing test output"
+                    LOGGER.info("{} {}: Rate = {} KB/s. Time = {} ms".format(implementation, test_type, rate, time))
+
+                    runs_results.append(((current_test, str(current_test_size), implementation), (rate, time)))
+
+                if current_test_size == max_test_size:
+                    break
+
+            LOGGER.info("=============================================================")
+
+    # Calculate average rate and time for each test size
+    sums = defaultdict(lambda: {"rate_sum": 0, "time_sum": 0})
+
+    for (test, size, impl), (rate, time) in runs_results:
+        sums[(test, size, impl)]["rate_sum"] += rate
+        sums[(test, size, impl)]["time_sum"] += time
+
+    avg_results = {}
+    for test, size, impl in sums:
+        rate_avg = round(sums[(test, size, impl)]["rate_sum"] / runs, 2)
+        time_avg = round(sums[(test, size, impl)]["time_sum"] / runs, 2)
+        LOGGER.info(
+            "Test: {}-{}-{}: Average rate = {} KB/s. Average time = {} ms".format(test, size, impl, rate_avg, time_avg)
+        )
+        if test not in avg_results:
+            avg_results[test] = {}
+        if size not in avg_results[test]:
+            avg_results[test][size] = {}
+        avg_results[test][size][impl] = {"avg_rate": rate_avg, "avg_time": time_avg}
+
+    # Create JSON with results and write it to file
+    # Always create a JSON with this format (so it can be merged later on):
+    # { TEST_NAME_STR: TEST_RESULTS_DICT }
+    results = {"ramspeed": {"runs": runs, "copies": copies, "max_test_size": max_test_size, "results": avg_results}}
+
+    current_folder = os.path.dirname(request.path)
+    file_index = 0
+    report_file = os.path.join(current_folder, "result_ramspeed" + str(file_index) + ".json")
+    while os.path.exists(report_file):
+        report_file = report_file.replace(str(file_index) + ".json", str(file_index + 1) + ".json")
+        file_index += 1
+
+    with open(report_file, "w") as f:
+        try:
+            f.write(json.dumps(results))
+        except Exception as e:
+            LOGGER.warning("Failed to write results to file: {}".format(e))
diff --git a/tests/performance/superpi/ci.json b/tests/performance/superpi/ci.json
new file mode 100644
index 00000000000..accee2b2135
--- /dev/null
+++ b/tests/performance/superpi/ci.json
@@ -0,0 +1,6 @@
+{
+  "platforms": {
+    "qemu": false,
+    "wokwi": false
+  }
+}
diff --git a/tests/performance/superpi/fftsg_h.cpp b/tests/performance/superpi/fftsg_h.cpp
new file mode 100644
index 00000000000..8361b5a5751
--- /dev/null
+++ b/tests/performance/superpi/fftsg_h.cpp
@@ -0,0 +1,2329 @@
+/*
+  Based on "Calculation of PI(= 3.14159...) using FFT and AGM" by T.Ooura, Nov. 1999.
+  https://github.com/Fibonacci43/SuperPI
+  Modified for Arduino by Lucas Saavedra Vaz, 2024.
+*/
+
+#include <fftsg_h.h>
+
+void cdft(int n, int isgn, double *a) {
+  if (isgn >= 0) {
+    cftfsub(n, a);
+  } else {
+    cftbsub(n, a);
+  }
+}
+
+void rdft(int n, int isgn, double *a) {
+  double xi;
+
+  if (isgn >= 0) {
+    if (n > 4) {
+      cftfsub(n, a);
+      rftfsub(n, a);
+    } else if (n == 4) {
+      cftfsub(n, a);
+    }
+    xi = a[0] - a[1];
+    a[0] += a[1];
+    a[1] = xi;
+  } else {
+    a[1] = 0.5 * (a[0] - a[1]);
+    a[0] -= a[1];
+    if (n > 4) {
+      rftbsub(n, a);
+      cftbsub(n, a);
+    } else if (n == 4) {
+      cftbsub(n, a);
+    }
+  }
+}
+
+void ddct(int n, int isgn, double *a) {
+  int j;
+  double xr;
+
+  if (isgn < 0) {
+    xr = a[n - 1];
+    for (j = n - 2; j >= 2; j -= 2) {
+      a[j + 1] = a[j] - a[j - 1];
+      a[j] += a[j - 1];
+    }
+    a[1] = a[0] - xr;
+    a[0] += xr;
+    if (n > 4) {
+      rftbsub(n, a);
+      cftbsub(n, a);
+    } else if (n == 4) {
+      cftbsub(n, a);
+    }
+  }
+  if (n > 4) {
+    dctsub(n, a);
+  } else {
+    dctsub4(n, a);
+  }
+  if (isgn >= 0) {
+    if (n > 4) {
+      cftfsub(n, a);
+      rftfsub(n, a);
+    } else if (n == 4) {
+      cftfsub(n, a);
+    }
+    xr = a[0] - a[1];
+    a[0] += a[1];
+    for (j = 2; j < n; j += 2) {
+      a[j - 1] = a[j] - a[j + 1];
+      a[j] += a[j + 1];
+    }
+    a[n - 1] = xr;
+  }
+}
+
+void ddst(int n, int isgn, double *a) {
+  int j;
+  double xr;
+
+  if (isgn < 0) {
+    xr = a[n - 1];
+    for (j = n - 2; j >= 2; j -= 2) {
+      a[j + 1] = -a[j] - a[j - 1];
+      a[j] -= a[j - 1];
+    }
+    a[1] = a[0] + xr;
+    a[0] -= xr;
+    if (n > 4) {
+      rftbsub(n, a);
+      cftbsub(n, a);
+    } else if (n == 4) {
+      cftbsub(n, a);
+    }
+  }
+  if (n > 4) {
+    dstsub(n, a);
+  } else {
+    dstsub4(n, a);
+  }
+  if (isgn >= 0) {
+    if (n > 4) {
+      cftfsub(n, a);
+      rftfsub(n, a);
+    } else if (n == 4) {
+      cftfsub(n, a);
+    }
+    xr = a[0] - a[1];
+    a[0] += a[1];
+    for (j = 2; j < n; j += 2) {
+      a[j - 1] = -a[j] - a[j + 1];
+      a[j] -= a[j + 1];
+    }
+    a[n - 1] = -xr;
+  }
+}
+
+void dfct(int n, double *a) {
+  int j, k, m, mh;
+  double xr, xi, yr, yi, an;
+
+  m = n >> 1;
+  for (j = 0; j < m; j++) {
+    k = n - j;
+    xr = a[j] + a[k];
+    a[j] -= a[k];
+    a[k] = xr;
+  }
+  an = a[n];
+  while (m >= 2) {
+    ddct(m, 1, a);
+    bitrv1(m, a);
+    mh = m >> 1;
+    xi = a[m];
+    a[m] = a[0];
+    a[0] = an - xi;
+    an += xi;
+    for (j = 1; j < mh; j++) {
+      k = m - j;
+      xr = a[m + k];
+      xi = a[m + j];
+      yr = a[j];
+      yi = a[k];
+      a[m + j] = yr;
+      a[m + k] = yi;
+      a[j] = xr - xi;
+      a[k] = xr + xi;
+    }
+    xr = a[mh];
+    a[mh] = a[m + mh];
+    a[m + mh] = xr;
+    m = mh;
+  }
+  xi = a[1];
+  a[1] = a[0];
+  a[0] = an + xi;
+  a[n] = an - xi;
+  bitrv1(n, a);
+}
+
+void dfst(int n, double *a) {
+  int j, k, m, mh;
+  double xr, xi, yr, yi;
+
+  m = n >> 1;
+  for (j = 1; j < m; j++) {
+    k = n - j;
+    xr = a[j] - a[k];
+    a[j] += a[k];
+    a[k] = xr;
+  }
+  a[0] = a[m];
+  while (m >= 2) {
+    ddst(m, 1, a);
+    bitrv1(m, a);
+    mh = m >> 1;
+    for (j = 1; j < mh; j++) {
+      k = m - j;
+      xr = a[m + k];
+      xi = a[m + j];
+      yr = a[j];
+      yi = a[k];
+      a[m + j] = yr;
+      a[m + k] = yi;
+      a[j] = xr + xi;
+      a[k] = xr - xi;
+    }
+    a[m] = a[0];
+    a[0] = a[m + mh];
+    a[m + mh] = a[mh];
+    m = mh;
+  }
+  a[1] = a[0];
+  a[0] = 0;
+  bitrv1(n, a);
+}
+
+/* -------- child routines -------- */
+
+void cftfsub(int n, double *a) {
+  int m;
+
+  if (n > 32) {
+    m = n >> 2;
+    cftmdl1(n, a);
+    if (n > CDFT_RECURSIVE_N) {
+      cftrec1(m, a);
+      cftrec2(m, &a[m]);
+      cftrec1(m, &a[2 * m]);
+      cftrec1(m, &a[3 * m]);
+    } else if (m > 32) {
+      cftexp1(n, a);
+    } else {
+      cftfx41(n, a);
+    }
+    bitrv2(n, a);
+  } else if (n > 8) {
+    if (n == 32) {
+      cftf161(a);
+      bitrv216(a);
+    } else {
+      cftf081(a);
+      bitrv208(a);
+    }
+  } else if (n == 8) {
+    cftf040(a);
+  } else if (n == 4) {
+    cftx020(a);
+  }
+}
+
+void cftbsub(int n, double *a) {
+  int m;
+
+  if (n > 32) {
+    m = n >> 2;
+    cftb1st(n, a);
+    if (n > CDFT_RECURSIVE_N) {
+      cftrec1(m, a);
+      cftrec2(m, &a[m]);
+      cftrec1(m, &a[2 * m]);
+      cftrec1(m, &a[3 * m]);
+    } else if (m > 32) {
+      cftexp1(n, a);
+    } else {
+      cftfx41(n, a);
+    }
+    bitrv2conj(n, a);
+  } else if (n > 8) {
+    if (n == 32) {
+      cftf161(a);
+      bitrv216neg(a);
+    } else {
+      cftf081(a);
+      bitrv208neg(a);
+    }
+  } else if (n == 8) {
+    cftb040(a);
+  } else if (n == 4) {
+    cftx020(a);
+  }
+}
+
+void bitrv2(int n, double *a) {
+  int j0, k0, j1, k1, l, m, i, j, k;
+  double xr, xi, yr, yi;
+
+  l = n >> 2;
+  m = 2;
+  while (m < l) {
+    l >>= 1;
+    m <<= 1;
+  }
+  if (m == l) {
+    j0 = 0;
+    for (k0 = 0; k0 < m; k0 += 2) {
+      k = k0;
+      for (j = j0; j < j0 + k0; j += 2) {
+        xr = a[j];
+        xi = a[j + 1];
+        yr = a[k];
+        yi = a[k + 1];
+        a[j] = yr;
+        a[j + 1] = yi;
+        a[k] = xr;
+        a[k + 1] = xi;
+        j1 = j + m;
+        k1 = k + 2 * m;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += m;
+        k1 -= m;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += m;
+        k1 += 2 * m;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        for (i = n >> 1; i > (k ^= i); i >>= 1);
+      }
+      j1 = j0 + k0 + m;
+      k1 = j1 + m;
+      xr = a[j1];
+      xi = a[j1 + 1];
+      yr = a[k1];
+      yi = a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      for (i = n >> 1; i > (j0 ^= i); i >>= 1);
+    }
+  } else {
+    j0 = 0;
+    for (k0 = 2; k0 < m; k0 += 2) {
+      for (i = n >> 1; i > (j0 ^= i); i >>= 1);
+      k = k0;
+      for (j = j0; j < j0 + k0; j += 2) {
+        xr = a[j];
+        xi = a[j + 1];
+        yr = a[k];
+        yi = a[k + 1];
+        a[j] = yr;
+        a[j + 1] = yi;
+        a[k] = xr;
+        a[k + 1] = xi;
+        j1 = j + m;
+        k1 = k + m;
+        xr = a[j1];
+        xi = a[j1 + 1];
+        yr = a[k1];
+        yi = a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        for (i = n >> 1; i > (k ^= i); i >>= 1);
+      }
+    }
+  }
+}
+
+void bitrv2conj(int n, double *a) {
+  int j0, k0, j1, k1, l, m, i, j, k;
+  double xr, xi, yr, yi;
+
+  l = n >> 2;
+  m = 2;
+  while (m < l) {
+    l >>= 1;
+    m <<= 1;
+  }
+  if (m == l) {
+    j0 = 0;
+    for (k0 = 0; k0 < m; k0 += 2) {
+      k = k0;
+      for (j = j0; j < j0 + k0; j += 2) {
+        xr = a[j];
+        xi = -a[j + 1];
+        yr = a[k];
+        yi = -a[k + 1];
+        a[j] = yr;
+        a[j + 1] = yi;
+        a[k] = xr;
+        a[k + 1] = xi;
+        j1 = j + m;
+        k1 = k + 2 * m;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += m;
+        k1 -= m;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        j1 += m;
+        k1 += 2 * m;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        for (i = n >> 1; i > (k ^= i); i >>= 1);
+      }
+      k1 = j0 + k0;
+      a[k1 + 1] = -a[k1 + 1];
+      j1 = k1 + m;
+      k1 = j1 + m;
+      xr = a[j1];
+      xi = -a[j1 + 1];
+      yr = a[k1];
+      yi = -a[k1 + 1];
+      a[j1] = yr;
+      a[j1 + 1] = yi;
+      a[k1] = xr;
+      a[k1 + 1] = xi;
+      k1 += m;
+      a[k1 + 1] = -a[k1 + 1];
+      for (i = n >> 1; i > (j0 ^= i); i >>= 1);
+    }
+  } else {
+    a[1] = -a[1];
+    a[m + 1] = -a[m + 1];
+    j0 = 0;
+    for (k0 = 2; k0 < m; k0 += 2) {
+      for (i = n >> 1; i > (j0 ^= i); i >>= 1);
+      k = k0;
+      for (j = j0; j < j0 + k0; j += 2) {
+        xr = a[j];
+        xi = -a[j + 1];
+        yr = a[k];
+        yi = -a[k + 1];
+        a[j] = yr;
+        a[j + 1] = yi;
+        a[k] = xr;
+        a[k + 1] = xi;
+        j1 = j + m;
+        k1 = k + m;
+        xr = a[j1];
+        xi = -a[j1 + 1];
+        yr = a[k1];
+        yi = -a[k1 + 1];
+        a[j1] = yr;
+        a[j1 + 1] = yi;
+        a[k1] = xr;
+        a[k1 + 1] = xi;
+        for (i = n >> 1; i > (k ^= i); i >>= 1);
+      }
+      k1 = j0 + k0;
+      a[k1 + 1] = -a[k1 + 1];
+      a[k1 + m + 1] = -a[k1 + m + 1];
+    }
+  }
+}
+
+void bitrv216(double *a) {
+  double x1r, x1i, x2r, x2i, x3r, x3i, x4r, x4i, x5r, x5i, x7r, x7i, x8r, x8i, x10r, x10i, x11r, x11i, x12r, x12i, x13r, x13i, x14r, x14i;
+
+  x1r = a[2];
+  x1i = a[3];
+  x2r = a[4];
+  x2i = a[5];
+  x3r = a[6];
+  x3i = a[7];
+  x4r = a[8];
+  x4i = a[9];
+  x5r = a[10];
+  x5i = a[11];
+  x7r = a[14];
+  x7i = a[15];
+  x8r = a[16];
+  x8i = a[17];
+  x10r = a[20];
+  x10i = a[21];
+  x11r = a[22];
+  x11i = a[23];
+  x12r = a[24];
+  x12i = a[25];
+  x13r = a[26];
+  x13i = a[27];
+  x14r = a[28];
+  x14i = a[29];
+  a[2] = x8r;
+  a[3] = x8i;
+  a[4] = x4r;
+  a[5] = x4i;
+  a[6] = x12r;
+  a[7] = x12i;
+  a[8] = x2r;
+  a[9] = x2i;
+  a[10] = x10r;
+  a[11] = x10i;
+  a[14] = x14r;
+  a[15] = x14i;
+  a[16] = x1r;
+  a[17] = x1i;
+  a[20] = x5r;
+  a[21] = x5i;
+  a[22] = x13r;
+  a[23] = x13i;
+  a[24] = x3r;
+  a[25] = x3i;
+  a[26] = x11r;
+  a[27] = x11i;
+  a[28] = x7r;
+  a[29] = x7i;
+}
+
+void bitrv216neg(double *a) {
+  double x1r, x1i, x2r, x2i, x3r, x3i, x4r, x4i, x5r, x5i, x6r, x6i, x7r, x7i, x8r, x8i, x9r, x9i, x10r, x10i, x11r, x11i, x12r, x12i, x13r, x13i, x14r, x14i,
+    x15r, x15i;
+
+  x1r = a[2];
+  x1i = a[3];
+  x2r = a[4];
+  x2i = a[5];
+  x3r = a[6];
+  x3i = a[7];
+  x4r = a[8];
+  x4i = a[9];
+  x5r = a[10];
+  x5i = a[11];
+  x6r = a[12];
+  x6i = a[13];
+  x7r = a[14];
+  x7i = a[15];
+  x8r = a[16];
+  x8i = a[17];
+  x9r = a[18];
+  x9i = a[19];
+  x10r = a[20];
+  x10i = a[21];
+  x11r = a[22];
+  x11i = a[23];
+  x12r = a[24];
+  x12i = a[25];
+  x13r = a[26];
+  x13i = a[27];
+  x14r = a[28];
+  x14i = a[29];
+  x15r = a[30];
+  x15i = a[31];
+  a[2] = x15r;
+  a[3] = x15i;
+  a[4] = x7r;
+  a[5] = x7i;
+  a[6] = x11r;
+  a[7] = x11i;
+  a[8] = x3r;
+  a[9] = x3i;
+  a[10] = x13r;
+  a[11] = x13i;
+  a[12] = x5r;
+  a[13] = x5i;
+  a[14] = x9r;
+  a[15] = x9i;
+  a[16] = x1r;
+  a[17] = x1i;
+  a[18] = x14r;
+  a[19] = x14i;
+  a[20] = x6r;
+  a[21] = x6i;
+  a[22] = x10r;
+  a[23] = x10i;
+  a[24] = x2r;
+  a[25] = x2i;
+  a[26] = x12r;
+  a[27] = x12i;
+  a[28] = x4r;
+  a[29] = x4i;
+  a[30] = x8r;
+  a[31] = x8i;
+}
+
+void bitrv208(double *a) {
+  double x1r, x1i, x3r, x3i, x4r, x4i, x6r, x6i;
+
+  x1r = a[2];
+  x1i = a[3];
+  x3r = a[6];
+  x3i = a[7];
+  x4r = a[8];
+  x4i = a[9];
+  x6r = a[12];
+  x6i = a[13];
+  a[2] = x4r;
+  a[3] = x4i;
+  a[6] = x6r;
+  a[7] = x6i;
+  a[8] = x1r;
+  a[9] = x1i;
+  a[12] = x3r;
+  a[13] = x3i;
+}
+
+void bitrv208neg(double *a) {
+  double x1r, x1i, x2r, x2i, x3r, x3i, x4r, x4i, x5r, x5i, x6r, x6i, x7r, x7i;
+
+  x1r = a[2];
+  x1i = a[3];
+  x2r = a[4];
+  x2i = a[5];
+  x3r = a[6];
+  x3i = a[7];
+  x4r = a[8];
+  x4i = a[9];
+  x5r = a[10];
+  x5i = a[11];
+  x6r = a[12];
+  x6i = a[13];
+  x7r = a[14];
+  x7i = a[15];
+  a[2] = x7r;
+  a[3] = x7i;
+  a[4] = x3r;
+  a[5] = x3i;
+  a[6] = x5r;
+  a[7] = x5i;
+  a[8] = x1r;
+  a[9] = x1i;
+  a[10] = x6r;
+  a[11] = x6i;
+  a[12] = x2r;
+  a[13] = x2i;
+  a[14] = x4r;
+  a[15] = x4i;
+}
+
+void bitrv1(int n, double *a) {
+  int j0, k0, j1, k1, l, m, i, j, k;
+  double x;
+
+  l = n >> 2;
+  m = 1;
+  while (m < l) {
+    l >>= 1;
+    m <<= 1;
+  }
+  if (m == l) {
+    j0 = 0;
+    for (k0 = 0; k0 < m; k0++) {
+      k = k0;
+      for (j = j0; j < j0 + k0; j++) {
+        x = a[j];
+        a[j] = a[k];
+        a[k] = x;
+        j1 = j + m;
+        k1 = k + 2 * m;
+        x = a[j1];
+        a[j1] = a[k1];
+        a[k1] = x;
+        j1 += m;
+        k1 -= m;
+        x = a[j1];
+        a[j1] = a[k1];
+        a[k1] = x;
+        j1 += m;
+        k1 += 2 * m;
+        x = a[j1];
+        a[j1] = a[k1];
+        a[k1] = x;
+        for (i = n >> 1; i > (k ^= i); i >>= 1);
+      }
+      j1 = j0 + k0 + m;
+      k1 = j1 + m;
+      x = a[j1];
+      a[j1] = a[k1];
+      a[k1] = x;
+      for (i = n >> 1; i > (j0 ^= i); i >>= 1);
+    }
+  } else {
+    j0 = 0;
+    for (k0 = 1; k0 < m; k0++) {
+      for (i = n >> 1; i > (j0 ^= i); i >>= 1);
+      k = k0;
+      for (j = j0; j < j0 + k0; j++) {
+        x = a[j];
+        a[j] = a[k];
+        a[k] = x;
+        j1 = j + m;
+        k1 = k + m;
+        x = a[j1];
+        a[j1] = a[k1];
+        a[k1] = x;
+        for (i = n >> 1; i > (k ^= i); i >>= 1);
+      }
+    }
+  }
+}
+
+void cftb1st(int n, double *a) {
+  int i, i0, j, j0, j1, j2, j3, m, mh;
+  double ew, w1r, w1i, wk1r, wk1i, wk3r, wk3i, wd1r, wd1i, wd3r, wd3i, ss1, ss3;
+  double x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i;
+
+  mh = n >> 3;
+  m = 2 * mh;
+  j1 = m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[0] + a[j2];
+  x0i = -a[1] - a[j2 + 1];
+  x1r = a[0] - a[j2];
+  x1i = -a[1] + a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[0] = x0r + x2r;
+  a[1] = x0i - x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i + x2i;
+  a[j2] = x1r + x3i;
+  a[j2 + 1] = x1i + x3r;
+  a[j3] = x1r - x3i;
+  a[j3 + 1] = x1i - x3r;
+  wd1r = 1;
+  wd1i = 0;
+  wd3r = 1;
+  wd3i = 0;
+  ew = M_PI_2 / m;
+  w1r = cos(2 * ew);
+  w1i = sin(2 * ew);
+  wk1r = w1r;
+  wk1i = w1i;
+  ss1 = 2 * w1i;
+  wk3i = 2 * ss1 * wk1r;
+  wk3r = wk1r - wk3i * wk1i;
+  wk3i = wk1i - wk3i * wk1r;
+  ss3 = 2 * wk3i;
+  i = 0;
+  for (;;) {
+    i0 = i + 4 * CDFT_LOOP_DIV;
+    if (i0 > mh - 4) {
+      i0 = mh - 4;
+    }
+    for (j = i + 2; j < i0; j += 4) {
+      wd1r -= ss1 * wk1i;
+      wd1i += ss1 * wk1r;
+      wd3r -= ss3 * wk3i;
+      wd3i += ss3 * wk3r;
+      j1 = j + m;
+      j2 = j1 + m;
+      j3 = j2 + m;
+      x0r = a[j] + a[j2];
+      x0i = -a[j + 1] - a[j2 + 1];
+      x1r = a[j] - a[j2];
+      x1i = -a[j + 1] + a[j2 + 1];
+      x2r = a[j1] + a[j3];
+      x2i = a[j1 + 1] + a[j3 + 1];
+      x3r = a[j1] - a[j3];
+      x3i = a[j1 + 1] - a[j3 + 1];
+      a[j] = x0r + x2r;
+      a[j + 1] = x0i - x2i;
+      a[j1] = x0r - x2r;
+      a[j1 + 1] = x0i + x2i;
+      x0r = x1r + x3i;
+      x0i = x1i + x3r;
+      a[j2] = wk1r * x0r - wk1i * x0i;
+      a[j2 + 1] = wk1r * x0i + wk1i * x0r;
+      x0r = x1r - x3i;
+      x0i = x1i - x3r;
+      a[j3] = wk3r * x0r + wk3i * x0i;
+      a[j3 + 1] = wk3r * x0i - wk3i * x0r;
+      x0r = a[j + 2] + a[j2 + 2];
+      x0i = -a[j + 3] - a[j2 + 3];
+      x1r = a[j + 2] - a[j2 + 2];
+      x1i = -a[j + 3] + a[j2 + 3];
+      x2r = a[j1 + 2] + a[j3 + 2];
+      x2i = a[j1 + 3] + a[j3 + 3];
+      x3r = a[j1 + 2] - a[j3 + 2];
+      x3i = a[j1 + 3] - a[j3 + 3];
+      a[j + 2] = x0r + x2r;
+      a[j + 3] = x0i - x2i;
+      a[j1 + 2] = x0r - x2r;
+      a[j1 + 3] = x0i + x2i;
+      x0r = x1r + x3i;
+      x0i = x1i + x3r;
+      a[j2 + 2] = wd1r * x0r - wd1i * x0i;
+      a[j2 + 3] = wd1r * x0i + wd1i * x0r;
+      x0r = x1r - x3i;
+      x0i = x1i - x3r;
+      a[j3 + 2] = wd3r * x0r + wd3i * x0i;
+      a[j3 + 3] = wd3r * x0i - wd3i * x0r;
+      j0 = m - j;
+      j1 = j0 + m;
+      j2 = j1 + m;
+      j3 = j2 + m;
+      x0r = a[j0] + a[j2];
+      x0i = -a[j0 + 1] - a[j2 + 1];
+      x1r = a[j0] - a[j2];
+      x1i = -a[j0 + 1] + a[j2 + 1];
+      x2r = a[j1] + a[j3];
+      x2i = a[j1 + 1] + a[j3 + 1];
+      x3r = a[j1] - a[j3];
+      x3i = a[j1 + 1] - a[j3 + 1];
+      a[j0] = x0r + x2r;
+      a[j0 + 1] = x0i - x2i;
+      a[j1] = x0r - x2r;
+      a[j1 + 1] = x0i + x2i;
+      x0r = x1r + x3i;
+      x0i = x1i + x3r;
+      a[j2] = wk1i * x0r - wk1r * x0i;
+      a[j2 + 1] = wk1i * x0i + wk1r * x0r;
+      x0r = x1r - x3i;
+      x0i = x1i - x3r;
+      a[j3] = wk3i * x0r + wk3r * x0i;
+      a[j3 + 1] = wk3i * x0i - wk3r * x0r;
+      x0r = a[j0 - 2] + a[j2 - 2];
+      x0i = -a[j0 - 1] - a[j2 - 1];
+      x1r = a[j0 - 2] - a[j2 - 2];
+      x1i = -a[j0 - 1] + a[j2 - 1];
+      x2r = a[j1 - 2] + a[j3 - 2];
+      x2i = a[j1 - 1] + a[j3 - 1];
+      x3r = a[j1 - 2] - a[j3 - 2];
+      x3i = a[j1 - 1] - a[j3 - 1];
+      a[j0 - 2] = x0r + x2r;
+      a[j0 - 1] = x0i - x2i;
+      a[j1 - 2] = x0r - x2r;
+      a[j1 - 1] = x0i + x2i;
+      x0r = x1r + x3i;
+      x0i = x1i + x3r;
+      a[j2 - 2] = wd1i * x0r - wd1r * x0i;
+      a[j2 - 1] = wd1i * x0i + wd1r * x0r;
+      x0r = x1r - x3i;
+      x0i = x1i - x3r;
+      a[j3 - 2] = wd3i * x0r + wd3r * x0i;
+      a[j3 - 1] = wd3i * x0i - wd3r * x0r;
+      wk1r -= ss1 * wd1i;
+      wk1i += ss1 * wd1r;
+      wk3r -= ss3 * wd3i;
+      wk3i += ss3 * wd3r;
+    }
+    if (i0 == mh - 4) {
+      break;
+    }
+    wd1r = cos(ew * i0);
+    wd1i = sin(ew * i0);
+    wd3i = 4 * wd1i * wd1r;
+    wd3r = wd1r - wd3i * wd1i;
+    wd3i = wd1i - wd3i * wd1r;
+    wk1r = w1r * wd1r - w1i * wd1i;
+    wk1i = w1r * wd1i + w1i * wd1r;
+    wk3i = 4 * wk1i * wk1r;
+    wk3r = wk1r - wk3i * wk1i;
+    wk3i = wk1i - wk3i * wk1r;
+    i = i0;
+  }
+  wd1r -= ss1 * wk1i;
+  j0 = mh;
+  j1 = j0 + m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[j0 - 2] + a[j2 - 2];
+  x0i = -a[j0 - 1] - a[j2 - 1];
+  x1r = a[j0 - 2] - a[j2 - 2];
+  x1i = -a[j0 - 1] + a[j2 - 1];
+  x2r = a[j1 - 2] + a[j3 - 2];
+  x2i = a[j1 - 1] + a[j3 - 1];
+  x3r = a[j1 - 2] - a[j3 - 2];
+  x3i = a[j1 - 1] - a[j3 - 1];
+  a[j0 - 2] = x0r + x2r;
+  a[j0 - 1] = x0i - x2i;
+  a[j1 - 2] = x0r - x2r;
+  a[j1 - 1] = x0i + x2i;
+  x0r = x1r + x3i;
+  x0i = x1i + x3r;
+  a[j2 - 2] = wk1r * x0r - wk1i * x0i;
+  a[j2 - 1] = wk1r * x0i + wk1i * x0r;
+  x0r = x1r - x3i;
+  x0i = x1i - x3r;
+  a[j3 - 2] = wk3r * x0r + wk3i * x0i;
+  a[j3 - 1] = wk3r * x0i - wk3i * x0r;
+  x0r = a[j0] + a[j2];
+  x0i = -a[j0 + 1] - a[j2 + 1];
+  x1r = a[j0] - a[j2];
+  x1i = -a[j0 + 1] + a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[j0] = x0r + x2r;
+  a[j0 + 1] = x0i - x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i + x2i;
+  x0r = x1r + x3i;
+  x0i = x1i + x3r;
+  a[j2] = wd1r * (x0r - x0i);
+  a[j2 + 1] = wd1r * (x0i + x0r);
+  x0r = x1r - x3i;
+  x0i = x1i - x3r;
+  a[j3] = -wd1r * (x0r + x0i);
+  a[j3 + 1] = -wd1r * (x0i - x0r);
+  x0r = a[j0 + 2] + a[j2 + 2];
+  x0i = -a[j0 + 3] - a[j2 + 3];
+  x1r = a[j0 + 2] - a[j2 + 2];
+  x1i = -a[j0 + 3] + a[j2 + 3];
+  x2r = a[j1 + 2] + a[j3 + 2];
+  x2i = a[j1 + 3] + a[j3 + 3];
+  x3r = a[j1 + 2] - a[j3 + 2];
+  x3i = a[j1 + 3] - a[j3 + 3];
+  a[j0 + 2] = x0r + x2r;
+  a[j0 + 3] = x0i - x2i;
+  a[j1 + 2] = x0r - x2r;
+  a[j1 + 3] = x0i + x2i;
+  x0r = x1r + x3i;
+  x0i = x1i + x3r;
+  a[j2 + 2] = wk1i * x0r - wk1r * x0i;
+  a[j2 + 3] = wk1i * x0i + wk1r * x0r;
+  x0r = x1r - x3i;
+  x0i = x1i - x3r;
+  a[j3 + 2] = wk3i * x0r + wk3r * x0i;
+  a[j3 + 3] = wk3i * x0i - wk3r * x0r;
+}
+
+void cftrec1(int n, double *a) {
+  int m;
+
+  m = n >> 2;
+  cftmdl1(n, a);
+  if (n > CDFT_RECURSIVE_N) {
+    cftrec1(m, a);
+    cftrec2(m, &a[m]);
+    cftrec1(m, &a[2 * m]);
+    cftrec1(m, &a[3 * m]);
+  } else {
+    cftexp1(n, a);
+  }
+}
+
+void cftrec2(int n, double *a) {
+  int m;
+
+  m = n >> 2;
+  cftmdl2(n, a);
+  if (n > CDFT_RECURSIVE_N) {
+    cftrec1(m, a);
+    cftrec2(m, &a[m]);
+    cftrec1(m, &a[2 * m]);
+    cftrec2(m, &a[3 * m]);
+  } else {
+    cftexp2(n, a);
+  }
+}
+
+void cftexp1(int n, double *a) {
+  int j, k, l;
+
+  l = n >> 2;
+  while (l > 128) {
+    for (k = l; k < n; k <<= 2) {
+      for (j = k - l; j < n; j += 4 * k) {
+        cftmdl1(l, &a[j]);
+        cftmdl2(l, &a[k + j]);
+        cftmdl1(l, &a[2 * k + j]);
+      }
+    }
+    cftmdl1(l, &a[n - l]);
+    l >>= 2;
+  }
+  for (k = l; k < n; k <<= 2) {
+    for (j = k - l; j < n; j += 4 * k) {
+      cftmdl1(l, &a[j]);
+      cftfx41(l, &a[j]);
+      cftmdl2(l, &a[k + j]);
+      cftfx42(l, &a[k + j]);
+      cftmdl1(l, &a[2 * k + j]);
+      cftfx41(l, &a[2 * k + j]);
+    }
+  }
+  cftmdl1(l, &a[n - l]);
+  cftfx41(l, &a[n - l]);
+}
+
+void cftexp2(int n, double *a) {
+  int j, k, l, m;
+
+  m = n >> 1;
+  l = n >> 2;
+  while (l > 128) {
+    for (k = l; k < m; k <<= 2) {
+      for (j = k - l; j < m; j += 2 * k) {
+        cftmdl1(l, &a[j]);
+        cftmdl1(l, &a[m + j]);
+      }
+      for (j = 2 * k - l; j < m; j += 4 * k) {
+        cftmdl2(l, &a[j]);
+        cftmdl2(l, &a[m + j]);
+      }
+    }
+    l >>= 2;
+  }
+  for (k = l; k < m; k <<= 2) {
+    for (j = k - l; j < m; j += 2 * k) {
+      cftmdl1(l, &a[j]);
+      cftfx41(l, &a[j]);
+      cftmdl1(l, &a[m + j]);
+      cftfx41(l, &a[m + j]);
+    }
+    for (j = 2 * k - l; j < m; j += 4 * k) {
+      cftmdl2(l, &a[j]);
+      cftfx42(l, &a[j]);
+      cftmdl2(l, &a[m + j]);
+      cftfx42(l, &a[m + j]);
+    }
+  }
+}
+
+void cftmdl1(int n, double *a) {
+  int i, i0, j, j0, j1, j2, j3, m, mh;
+  double ew, w1r, w1i, wk1r, wk1i, wk3r, wk3i, wd1r, wd1i, wd3r, wd3i, ss1, ss3;
+  double x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i;
+
+  mh = n >> 3;
+  m = 2 * mh;
+  j1 = m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[0] + a[j2];
+  x0i = a[1] + a[j2 + 1];
+  x1r = a[0] - a[j2];
+  x1i = a[1] - a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[0] = x0r + x2r;
+  a[1] = x0i + x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i - x2i;
+  a[j2] = x1r - x3i;
+  a[j2 + 1] = x1i + x3r;
+  a[j3] = x1r + x3i;
+  a[j3 + 1] = x1i - x3r;
+  wd1r = 1;
+  wd1i = 0;
+  wd3r = 1;
+  wd3i = 0;
+  ew = M_PI_2 / m;
+  w1r = cos(2 * ew);
+  w1i = sin(2 * ew);
+  wk1r = w1r;
+  wk1i = w1i;
+  ss1 = 2 * w1i;
+  wk3i = 2 * ss1 * wk1r;
+  wk3r = wk1r - wk3i * wk1i;
+  wk3i = wk1i - wk3i * wk1r;
+  ss3 = 2 * wk3i;
+  i = 0;
+  for (;;) {
+    i0 = i + 4 * CDFT_LOOP_DIV;
+    if (i0 > mh - 4) {
+      i0 = mh - 4;
+    }
+    for (j = i + 2; j < i0; j += 4) {
+      wd1r -= ss1 * wk1i;
+      wd1i += ss1 * wk1r;
+      wd3r -= ss3 * wk3i;
+      wd3i += ss3 * wk3r;
+      j1 = j + m;
+      j2 = j1 + m;
+      j3 = j2 + m;
+      x0r = a[j] + a[j2];
+      x0i = a[j + 1] + a[j2 + 1];
+      x1r = a[j] - a[j2];
+      x1i = a[j + 1] - a[j2 + 1];
+      x2r = a[j1] + a[j3];
+      x2i = a[j1 + 1] + a[j3 + 1];
+      x3r = a[j1] - a[j3];
+      x3i = a[j1 + 1] - a[j3 + 1];
+      a[j] = x0r + x2r;
+      a[j + 1] = x0i + x2i;
+      a[j1] = x0r - x2r;
+      a[j1 + 1] = x0i - x2i;
+      x0r = x1r - x3i;
+      x0i = x1i + x3r;
+      a[j2] = wk1r * x0r - wk1i * x0i;
+      a[j2 + 1] = wk1r * x0i + wk1i * x0r;
+      x0r = x1r + x3i;
+      x0i = x1i - x3r;
+      a[j3] = wk3r * x0r + wk3i * x0i;
+      a[j3 + 1] = wk3r * x0i - wk3i * x0r;
+      x0r = a[j + 2] + a[j2 + 2];
+      x0i = a[j + 3] + a[j2 + 3];
+      x1r = a[j + 2] - a[j2 + 2];
+      x1i = a[j + 3] - a[j2 + 3];
+      x2r = a[j1 + 2] + a[j3 + 2];
+      x2i = a[j1 + 3] + a[j3 + 3];
+      x3r = a[j1 + 2] - a[j3 + 2];
+      x3i = a[j1 + 3] - a[j3 + 3];
+      a[j + 2] = x0r + x2r;
+      a[j + 3] = x0i + x2i;
+      a[j1 + 2] = x0r - x2r;
+      a[j1 + 3] = x0i - x2i;
+      x0r = x1r - x3i;
+      x0i = x1i + x3r;
+      a[j2 + 2] = wd1r * x0r - wd1i * x0i;
+      a[j2 + 3] = wd1r * x0i + wd1i * x0r;
+      x0r = x1r + x3i;
+      x0i = x1i - x3r;
+      a[j3 + 2] = wd3r * x0r + wd3i * x0i;
+      a[j3 + 3] = wd3r * x0i - wd3i * x0r;
+      j0 = m - j;
+      j1 = j0 + m;
+      j2 = j1 + m;
+      j3 = j2 + m;
+      x0r = a[j0] + a[j2];
+      x0i = a[j0 + 1] + a[j2 + 1];
+      x1r = a[j0] - a[j2];
+      x1i = a[j0 + 1] - a[j2 + 1];
+      x2r = a[j1] + a[j3];
+      x2i = a[j1 + 1] + a[j3 + 1];
+      x3r = a[j1] - a[j3];
+      x3i = a[j1 + 1] - a[j3 + 1];
+      a[j0] = x0r + x2r;
+      a[j0 + 1] = x0i + x2i;
+      a[j1] = x0r - x2r;
+      a[j1 + 1] = x0i - x2i;
+      x0r = x1r - x3i;
+      x0i = x1i + x3r;
+      a[j2] = wk1i * x0r - wk1r * x0i;
+      a[j2 + 1] = wk1i * x0i + wk1r * x0r;
+      x0r = x1r + x3i;
+      x0i = x1i - x3r;
+      a[j3] = wk3i * x0r + wk3r * x0i;
+      a[j3 + 1] = wk3i * x0i - wk3r * x0r;
+      x0r = a[j0 - 2] + a[j2 - 2];
+      x0i = a[j0 - 1] + a[j2 - 1];
+      x1r = a[j0 - 2] - a[j2 - 2];
+      x1i = a[j0 - 1] - a[j2 - 1];
+      x2r = a[j1 - 2] + a[j3 - 2];
+      x2i = a[j1 - 1] + a[j3 - 1];
+      x3r = a[j1 - 2] - a[j3 - 2];
+      x3i = a[j1 - 1] - a[j3 - 1];
+      a[j0 - 2] = x0r + x2r;
+      a[j0 - 1] = x0i + x2i;
+      a[j1 - 2] = x0r - x2r;
+      a[j1 - 1] = x0i - x2i;
+      x0r = x1r - x3i;
+      x0i = x1i + x3r;
+      a[j2 - 2] = wd1i * x0r - wd1r * x0i;
+      a[j2 - 1] = wd1i * x0i + wd1r * x0r;
+      x0r = x1r + x3i;
+      x0i = x1i - x3r;
+      a[j3 - 2] = wd3i * x0r + wd3r * x0i;
+      a[j3 - 1] = wd3i * x0i - wd3r * x0r;
+      wk1r -= ss1 * wd1i;
+      wk1i += ss1 * wd1r;
+      wk3r -= ss3 * wd3i;
+      wk3i += ss3 * wd3r;
+    }
+    if (i0 == mh - 4) {
+      break;
+    }
+    wd1r = cos(ew * i0);
+    wd1i = sin(ew * i0);
+    wd3i = 4 * wd1i * wd1r;
+    wd3r = wd1r - wd3i * wd1i;
+    wd3i = wd1i - wd3i * wd1r;
+    wk1r = w1r * wd1r - w1i * wd1i;
+    wk1i = w1r * wd1i + w1i * wd1r;
+    wk3i = 4 * wk1i * wk1r;
+    wk3r = wk1r - wk3i * wk1i;
+    wk3i = wk1i - wk3i * wk1r;
+    i = i0;
+  }
+  wd1r -= ss1 * wk1i;
+  j0 = mh;
+  j1 = j0 + m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[j0 - 2] + a[j2 - 2];
+  x0i = a[j0 - 1] + a[j2 - 1];
+  x1r = a[j0 - 2] - a[j2 - 2];
+  x1i = a[j0 - 1] - a[j2 - 1];
+  x2r = a[j1 - 2] + a[j3 - 2];
+  x2i = a[j1 - 1] + a[j3 - 1];
+  x3r = a[j1 - 2] - a[j3 - 2];
+  x3i = a[j1 - 1] - a[j3 - 1];
+  a[j0 - 2] = x0r + x2r;
+  a[j0 - 1] = x0i + x2i;
+  a[j1 - 2] = x0r - x2r;
+  a[j1 - 1] = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  a[j2 - 2] = wk1r * x0r - wk1i * x0i;
+  a[j2 - 1] = wk1r * x0i + wk1i * x0r;
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  a[j3 - 2] = wk3r * x0r + wk3i * x0i;
+  a[j3 - 1] = wk3r * x0i - wk3i * x0r;
+  x0r = a[j0] + a[j2];
+  x0i = a[j0 + 1] + a[j2 + 1];
+  x1r = a[j0] - a[j2];
+  x1i = a[j0 + 1] - a[j2 + 1];
+  x2r = a[j1] + a[j3];
+  x2i = a[j1 + 1] + a[j3 + 1];
+  x3r = a[j1] - a[j3];
+  x3i = a[j1 + 1] - a[j3 + 1];
+  a[j0] = x0r + x2r;
+  a[j0 + 1] = x0i + x2i;
+  a[j1] = x0r - x2r;
+  a[j1 + 1] = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  a[j2] = wd1r * (x0r - x0i);
+  a[j2 + 1] = wd1r * (x0i + x0r);
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  a[j3] = -wd1r * (x0r + x0i);
+  a[j3 + 1] = -wd1r * (x0i - x0r);
+  x0r = a[j0 + 2] + a[j2 + 2];
+  x0i = a[j0 + 3] + a[j2 + 3];
+  x1r = a[j0 + 2] - a[j2 + 2];
+  x1i = a[j0 + 3] - a[j2 + 3];
+  x2r = a[j1 + 2] + a[j3 + 2];
+  x2i = a[j1 + 3] + a[j3 + 3];
+  x3r = a[j1 + 2] - a[j3 + 2];
+  x3i = a[j1 + 3] - a[j3 + 3];
+  a[j0 + 2] = x0r + x2r;
+  a[j0 + 3] = x0i + x2i;
+  a[j1 + 2] = x0r - x2r;
+  a[j1 + 3] = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  a[j2 + 2] = wk1i * x0r - wk1r * x0i;
+  a[j2 + 3] = wk1i * x0i + wk1r * x0r;
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  a[j3 + 2] = wk3i * x0r + wk3r * x0i;
+  a[j3 + 3] = wk3i * x0i - wk3r * x0r;
+}
+
+void cftmdl2(int n, double *a) {
+  int i, i0, j, j0, j1, j2, j3, m, mh;
+  double ew, w1r, w1i, wn4r, wk1r, wk1i, wk3r, wk3i, wl1r, wl1i, wl3r, wl3i, wd1r, wd1i, wd3r, wd3i, we1r, we1i, we3r, we3i, ss1, ss3;
+  double x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i, y0r, y0i, y2r, y2i;
+
+  mh = n >> 3;
+  m = 2 * mh;
+  wn4r = WR5000;
+  j1 = m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[0] - a[j2 + 1];
+  x0i = a[1] + a[j2];
+  x1r = a[0] + a[j2 + 1];
+  x1i = a[1] - a[j2];
+  x2r = a[j1] - a[j3 + 1];
+  x2i = a[j1 + 1] + a[j3];
+  x3r = a[j1] + a[j3 + 1];
+  x3i = a[j1 + 1] - a[j3];
+  y0r = wn4r * (x2r - x2i);
+  y0i = wn4r * (x2i + x2r);
+  a[0] = x0r + y0r;
+  a[1] = x0i + y0i;
+  a[j1] = x0r - y0r;
+  a[j1 + 1] = x0i - y0i;
+  y0r = wn4r * (x3r - x3i);
+  y0i = wn4r * (x3i + x3r);
+  a[j2] = x1r - y0i;
+  a[j2 + 1] = x1i + y0r;
+  a[j3] = x1r + y0i;
+  a[j3 + 1] = x1i - y0r;
+  wl1r = 1;
+  wl1i = 0;
+  wl3r = 1;
+  wl3i = 0;
+  we1r = wn4r;
+  we1i = wn4r;
+  we3r = -wn4r;
+  we3i = -wn4r;
+  ew = M_PI_2 / (2 * m);
+  w1r = cos(2 * ew);
+  w1i = sin(2 * ew);
+  wk1r = w1r;
+  wk1i = w1i;
+  wd1r = wn4r * (w1r - w1i);
+  wd1i = wn4r * (w1i + w1r);
+  ss1 = 2 * w1i;
+  wk3i = 2 * ss1 * wk1r;
+  wk3r = wk1r - wk3i * wk1i;
+  wk3i = wk1i - wk3i * wk1r;
+  ss3 = 2 * wk3i;
+  wd3r = -wn4r * (wk3r - wk3i);
+  wd3i = -wn4r * (wk3i + wk3r);
+  i = 0;
+  for (;;) {
+    i0 = i + 4 * CDFT_LOOP_DIV;
+    if (i0 > mh - 4) {
+      i0 = mh - 4;
+    }
+    for (j = i + 2; j < i0; j += 4) {
+      wl1r -= ss1 * wk1i;
+      wl1i += ss1 * wk1r;
+      wl3r -= ss3 * wk3i;
+      wl3i += ss3 * wk3r;
+      we1r -= ss1 * wd1i;
+      we1i += ss1 * wd1r;
+      we3r -= ss3 * wd3i;
+      we3i += ss3 * wd3r;
+      j1 = j + m;
+      j2 = j1 + m;
+      j3 = j2 + m;
+      x0r = a[j] - a[j2 + 1];
+      x0i = a[j + 1] + a[j2];
+      x1r = a[j] + a[j2 + 1];
+      x1i = a[j + 1] - a[j2];
+      x2r = a[j1] - a[j3 + 1];
+      x2i = a[j1 + 1] + a[j3];
+      x3r = a[j1] + a[j3 + 1];
+      x3i = a[j1 + 1] - a[j3];
+      y0r = wk1r * x0r - wk1i * x0i;
+      y0i = wk1r * x0i + wk1i * x0r;
+      y2r = wd1r * x2r - wd1i * x2i;
+      y2i = wd1r * x2i + wd1i * x2r;
+      a[j] = y0r + y2r;
+      a[j + 1] = y0i + y2i;
+      a[j1] = y0r - y2r;
+      a[j1 + 1] = y0i - y2i;
+      y0r = wk3r * x1r + wk3i * x1i;
+      y0i = wk3r * x1i - wk3i * x1r;
+      y2r = wd3r * x3r + wd3i * x3i;
+      y2i = wd3r * x3i - wd3i * x3r;
+      a[j2] = y0r + y2r;
+      a[j2 + 1] = y0i + y2i;
+      a[j3] = y0r - y2r;
+      a[j3 + 1] = y0i - y2i;
+      x0r = a[j + 2] - a[j2 + 3];
+      x0i = a[j + 3] + a[j2 + 2];
+      x1r = a[j + 2] + a[j2 + 3];
+      x1i = a[j + 3] - a[j2 + 2];
+      x2r = a[j1 + 2] - a[j3 + 3];
+      x2i = a[j1 + 3] + a[j3 + 2];
+      x3r = a[j1 + 2] + a[j3 + 3];
+      x3i = a[j1 + 3] - a[j3 + 2];
+      y0r = wl1r * x0r - wl1i * x0i;
+      y0i = wl1r * x0i + wl1i * x0r;
+      y2r = we1r * x2r - we1i * x2i;
+      y2i = we1r * x2i + we1i * x2r;
+      a[j + 2] = y0r + y2r;
+      a[j + 3] = y0i + y2i;
+      a[j1 + 2] = y0r - y2r;
+      a[j1 + 3] = y0i - y2i;
+      y0r = wl3r * x1r + wl3i * x1i;
+      y0i = wl3r * x1i - wl3i * x1r;
+      y2r = we3r * x3r + we3i * x3i;
+      y2i = we3r * x3i - we3i * x3r;
+      a[j2 + 2] = y0r + y2r;
+      a[j2 + 3] = y0i + y2i;
+      a[j3 + 2] = y0r - y2r;
+      a[j3 + 3] = y0i - y2i;
+      j0 = m - j;
+      j1 = j0 + m;
+      j2 = j1 + m;
+      j3 = j2 + m;
+      x0r = a[j0] - a[j2 + 1];
+      x0i = a[j0 + 1] + a[j2];
+      x1r = a[j0] + a[j2 + 1];
+      x1i = a[j0 + 1] - a[j2];
+      x2r = a[j1] - a[j3 + 1];
+      x2i = a[j1 + 1] + a[j3];
+      x3r = a[j1] + a[j3 + 1];
+      x3i = a[j1 + 1] - a[j3];
+      y0r = wd1i * x0r - wd1r * x0i;
+      y0i = wd1i * x0i + wd1r * x0r;
+      y2r = wk1i * x2r - wk1r * x2i;
+      y2i = wk1i * x2i + wk1r * x2r;
+      a[j0] = y0r + y2r;
+      a[j0 + 1] = y0i + y2i;
+      a[j1] = y0r - y2r;
+      a[j1 + 1] = y0i - y2i;
+      y0r = wd3i * x1r + wd3r * x1i;
+      y0i = wd3i * x1i - wd3r * x1r;
+      y2r = wk3i * x3r + wk3r * x3i;
+      y2i = wk3i * x3i - wk3r * x3r;
+      a[j2] = y0r + y2r;
+      a[j2 + 1] = y0i + y2i;
+      a[j3] = y0r - y2r;
+      a[j3 + 1] = y0i - y2i;
+      x0r = a[j0 - 2] - a[j2 - 1];
+      x0i = a[j0 - 1] + a[j2 - 2];
+      x1r = a[j0 - 2] + a[j2 - 1];
+      x1i = a[j0 - 1] - a[j2 - 2];
+      x2r = a[j1 - 2] - a[j3 - 1];
+      x2i = a[j1 - 1] + a[j3 - 2];
+      x3r = a[j1 - 2] + a[j3 - 1];
+      x3i = a[j1 - 1] - a[j3 - 2];
+      y0r = we1i * x0r - we1r * x0i;
+      y0i = we1i * x0i + we1r * x0r;
+      y2r = wl1i * x2r - wl1r * x2i;
+      y2i = wl1i * x2i + wl1r * x2r;
+      a[j0 - 2] = y0r + y2r;
+      a[j0 - 1] = y0i + y2i;
+      a[j1 - 2] = y0r - y2r;
+      a[j1 - 1] = y0i - y2i;
+      y0r = we3i * x1r + we3r * x1i;
+      y0i = we3i * x1i - we3r * x1r;
+      y2r = wl3i * x3r + wl3r * x3i;
+      y2i = wl3i * x3i - wl3r * x3r;
+      a[j2 - 2] = y0r + y2r;
+      a[j2 - 1] = y0i + y2i;
+      a[j3 - 2] = y0r - y2r;
+      a[j3 - 1] = y0i - y2i;
+      wk1r -= ss1 * wl1i;
+      wk1i += ss1 * wl1r;
+      wk3r -= ss3 * wl3i;
+      wk3i += ss3 * wl3r;
+      wd1r -= ss1 * we1i;
+      wd1i += ss1 * we1r;
+      wd3r -= ss3 * we3i;
+      wd3i += ss3 * we3r;
+    }
+    if (i0 == mh - 4) {
+      break;
+    }
+    wl1r = cos(ew * i0);
+    wl1i = sin(ew * i0);
+    wl3i = 4 * wl1i * wl1r;
+    wl3r = wl1r - wl3i * wl1i;
+    wl3i = wl1i - wl3i * wl1r;
+    we1r = wn4r * (wl1r - wl1i);
+    we1i = wn4r * (wl1i + wl1r);
+    we3r = -wn4r * (wl3r - wl3i);
+    we3i = -wn4r * (wl3i + wl3r);
+    wk1r = w1r * wl1r - w1i * wl1i;
+    wk1i = w1r * wl1i + w1i * wl1r;
+    wk3i = 4 * wk1i * wk1r;
+    wk3r = wk1r - wk3i * wk1i;
+    wk3i = wk1i - wk3i * wk1r;
+    wd1r = wn4r * (wk1r - wk1i);
+    wd1i = wn4r * (wk1i + wk1r);
+    wd3r = -wn4r * (wk3r - wk3i);
+    wd3i = -wn4r * (wk3i + wk3r);
+    i = i0;
+  }
+  wl1r -= ss1 * wk1i;
+  wl1i += ss1 * wk1r;
+  j0 = mh;
+  j1 = j0 + m;
+  j2 = j1 + m;
+  j3 = j2 + m;
+  x0r = a[j0 - 2] - a[j2 - 1];
+  x0i = a[j0 - 1] + a[j2 - 2];
+  x1r = a[j0 - 2] + a[j2 - 1];
+  x1i = a[j0 - 1] - a[j2 - 2];
+  x2r = a[j1 - 2] - a[j3 - 1];
+  x2i = a[j1 - 1] + a[j3 - 2];
+  x3r = a[j1 - 2] + a[j3 - 1];
+  x3i = a[j1 - 1] - a[j3 - 2];
+  y0r = wk1r * x0r - wk1i * x0i;
+  y0i = wk1r * x0i + wk1i * x0r;
+  y2r = wd1r * x2r - wd1i * x2i;
+  y2i = wd1r * x2i + wd1i * x2r;
+  a[j0 - 2] = y0r + y2r;
+  a[j0 - 1] = y0i + y2i;
+  a[j1 - 2] = y0r - y2r;
+  a[j1 - 1] = y0i - y2i;
+  y0r = wk3r * x1r + wk3i * x1i;
+  y0i = wk3r * x1i - wk3i * x1r;
+  y2r = wd3r * x3r + wd3i * x3i;
+  y2i = wd3r * x3i - wd3i * x3r;
+  a[j2 - 2] = y0r + y2r;
+  a[j2 - 1] = y0i + y2i;
+  a[j3 - 2] = y0r - y2r;
+  a[j3 - 1] = y0i - y2i;
+  x0r = a[j0] - a[j2 + 1];
+  x0i = a[j0 + 1] + a[j2];
+  x1r = a[j0] + a[j2 + 1];
+  x1i = a[j0 + 1] - a[j2];
+  x2r = a[j1] - a[j3 + 1];
+  x2i = a[j1 + 1] + a[j3];
+  x3r = a[j1] + a[j3 + 1];
+  x3i = a[j1 + 1] - a[j3];
+  y0r = wl1r * x0r - wl1i * x0i;
+  y0i = wl1r * x0i + wl1i * x0r;
+  y2r = wl1i * x2r - wl1r * x2i;
+  y2i = wl1i * x2i + wl1r * x2r;
+  a[j0] = y0r + y2r;
+  a[j0 + 1] = y0i + y2i;
+  a[j1] = y0r - y2r;
+  a[j1 + 1] = y0i - y2i;
+  y0r = wl1i * x1r - wl1r * x1i;
+  y0i = wl1i * x1i + wl1r * x1r;
+  y2r = wl1r * x3r - wl1i * x3i;
+  y2i = wl1r * x3i + wl1i * x3r;
+  a[j2] = y0r - y2r;
+  a[j2 + 1] = y0i - y2i;
+  a[j3] = y0r + y2r;
+  a[j3 + 1] = y0i + y2i;
+  x0r = a[j0 + 2] - a[j2 + 3];
+  x0i = a[j0 + 3] + a[j2 + 2];
+  x1r = a[j0 + 2] + a[j2 + 3];
+  x1i = a[j0 + 3] - a[j2 + 2];
+  x2r = a[j1 + 2] - a[j3 + 3];
+  x2i = a[j1 + 3] + a[j3 + 2];
+  x3r = a[j1 + 2] + a[j3 + 3];
+  x3i = a[j1 + 3] - a[j3 + 2];
+  y0r = wd1i * x0r - wd1r * x0i;
+  y0i = wd1i * x0i + wd1r * x0r;
+  y2r = wk1i * x2r - wk1r * x2i;
+  y2i = wk1i * x2i + wk1r * x2r;
+  a[j0 + 2] = y0r + y2r;
+  a[j0 + 3] = y0i + y2i;
+  a[j1 + 2] = y0r - y2r;
+  a[j1 + 3] = y0i - y2i;
+  y0r = wd3i * x1r + wd3r * x1i;
+  y0i = wd3i * x1i - wd3r * x1r;
+  y2r = wk3i * x3r + wk3r * x3i;
+  y2i = wk3i * x3i - wk3r * x3r;
+  a[j2 + 2] = y0r + y2r;
+  a[j2 + 3] = y0i + y2i;
+  a[j3 + 2] = y0r - y2r;
+  a[j3 + 3] = y0i - y2i;
+}
+
+void cftfx41(int n, double *a) {
+  if (n == 128) {
+    cftf161(a);
+    cftf162(&a[32]);
+    cftf161(&a[64]);
+    cftf161(&a[96]);
+  } else {
+    cftf081(a);
+    cftf082(&a[16]);
+    cftf081(&a[32]);
+    cftf081(&a[48]);
+  }
+}
+
+void cftfx42(int n, double *a) {
+  if (n == 128) {
+    cftf161(a);
+    cftf162(&a[32]);
+    cftf161(&a[64]);
+    cftf162(&a[96]);
+  } else {
+    cftf081(a);
+    cftf082(&a[16]);
+    cftf081(&a[32]);
+    cftf082(&a[48]);
+  }
+}
+
+void cftf161(double *a) {
+  double wn4r, wk1r, wk1i, x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i, y0r, y0i, y1r, y1i, y2r, y2i, y3r, y3i, y4r, y4i, y5r, y5i, y6r, y6i, y7r, y7i, y8r, y8i,
+    y9r, y9i, y10r, y10i, y11r, y11i, y12r, y12i, y13r, y13i, y14r, y14i, y15r, y15i;
+
+  wn4r = WR5000;
+  wk1r = WR2500;
+  wk1i = WI2500;
+  x0r = a[0] + a[16];
+  x0i = a[1] + a[17];
+  x1r = a[0] - a[16];
+  x1i = a[1] - a[17];
+  x2r = a[8] + a[24];
+  x2i = a[9] + a[25];
+  x3r = a[8] - a[24];
+  x3i = a[9] - a[25];
+  y0r = x0r + x2r;
+  y0i = x0i + x2i;
+  y4r = x0r - x2r;
+  y4i = x0i - x2i;
+  y8r = x1r - x3i;
+  y8i = x1i + x3r;
+  y12r = x1r + x3i;
+  y12i = x1i - x3r;
+  x0r = a[2] + a[18];
+  x0i = a[3] + a[19];
+  x1r = a[2] - a[18];
+  x1i = a[3] - a[19];
+  x2r = a[10] + a[26];
+  x2i = a[11] + a[27];
+  x3r = a[10] - a[26];
+  x3i = a[11] - a[27];
+  y1r = x0r + x2r;
+  y1i = x0i + x2i;
+  y5r = x0r - x2r;
+  y5i = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  y9r = wk1r * x0r - wk1i * x0i;
+  y9i = wk1r * x0i + wk1i * x0r;
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  y13r = wk1i * x0r - wk1r * x0i;
+  y13i = wk1i * x0i + wk1r * x0r;
+  x0r = a[4] + a[20];
+  x0i = a[5] + a[21];
+  x1r = a[4] - a[20];
+  x1i = a[5] - a[21];
+  x2r = a[12] + a[28];
+  x2i = a[13] + a[29];
+  x3r = a[12] - a[28];
+  x3i = a[13] - a[29];
+  y2r = x0r + x2r;
+  y2i = x0i + x2i;
+  y6r = x0r - x2r;
+  y6i = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  y10r = wn4r * (x0r - x0i);
+  y10i = wn4r * (x0i + x0r);
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  y14r = wn4r * (x0r + x0i);
+  y14i = wn4r * (x0i - x0r);
+  x0r = a[6] + a[22];
+  x0i = a[7] + a[23];
+  x1r = a[6] - a[22];
+  x1i = a[7] - a[23];
+  x2r = a[14] + a[30];
+  x2i = a[15] + a[31];
+  x3r = a[14] - a[30];
+  x3i = a[15] - a[31];
+  y3r = x0r + x2r;
+  y3i = x0i + x2i;
+  y7r = x0r - x2r;
+  y7i = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  y11r = wk1i * x0r - wk1r * x0i;
+  y11i = wk1i * x0i + wk1r * x0r;
+  x0r = x1r + x3i;
+  x0i = x1i - x3r;
+  y15r = wk1r * x0r - wk1i * x0i;
+  y15i = wk1r * x0i + wk1i * x0r;
+  x0r = y12r - y14r;
+  x0i = y12i - y14i;
+  x1r = y12r + y14r;
+  x1i = y12i + y14i;
+  x2r = y13r - y15r;
+  x2i = y13i - y15i;
+  x3r = y13r + y15r;
+  x3i = y13i + y15i;
+  a[24] = x0r + x2r;
+  a[25] = x0i + x2i;
+  a[26] = x0r - x2r;
+  a[27] = x0i - x2i;
+  a[28] = x1r - x3i;
+  a[29] = x1i + x3r;
+  a[30] = x1r + x3i;
+  a[31] = x1i - x3r;
+  x0r = y8r + y10r;
+  x0i = y8i + y10i;
+  x1r = y8r - y10r;
+  x1i = y8i - y10i;
+  x2r = y9r + y11r;
+  x2i = y9i + y11i;
+  x3r = y9r - y11r;
+  x3i = y9i - y11i;
+  a[16] = x0r + x2r;
+  a[17] = x0i + x2i;
+  a[18] = x0r - x2r;
+  a[19] = x0i - x2i;
+  a[20] = x1r - x3i;
+  a[21] = x1i + x3r;
+  a[22] = x1r + x3i;
+  a[23] = x1i - x3r;
+  x0r = y5r - y7i;
+  x0i = y5i + y7r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  x0r = y5r + y7i;
+  x0i = y5i - y7r;
+  x3r = wn4r * (x0r - x0i);
+  x3i = wn4r * (x0i + x0r);
+  x0r = y4r - y6i;
+  x0i = y4i + y6r;
+  x1r = y4r + y6i;
+  x1i = y4i - y6r;
+  a[8] = x0r + x2r;
+  a[9] = x0i + x2i;
+  a[10] = x0r - x2r;
+  a[11] = x0i - x2i;
+  a[12] = x1r - x3i;
+  a[13] = x1i + x3r;
+  a[14] = x1r + x3i;
+  a[15] = x1i - x3r;
+  x0r = y0r + y2r;
+  x0i = y0i + y2i;
+  x1r = y0r - y2r;
+  x1i = y0i - y2i;
+  x2r = y1r + y3r;
+  x2i = y1i + y3i;
+  x3r = y1r - y3r;
+  x3i = y1i - y3i;
+  a[0] = x0r + x2r;
+  a[1] = x0i + x2i;
+  a[2] = x0r - x2r;
+  a[3] = x0i - x2i;
+  a[4] = x1r - x3i;
+  a[5] = x1i + x3r;
+  a[6] = x1r + x3i;
+  a[7] = x1i - x3r;
+}
+
+void cftf162(double *a) {
+  double wn4r, wk1r, wk1i, wk2r, wk2i, wk3r, wk3i, x0r, x0i, x1r, x1i, x2r, x2i, y0r, y0i, y1r, y1i, y2r, y2i, y3r, y3i, y4r, y4i, y5r, y5i, y6r, y6i, y7r, y7i,
+    y8r, y8i, y9r, y9i, y10r, y10i, y11r, y11i, y12r, y12i, y13r, y13i, y14r, y14i, y15r, y15i;
+
+  wn4r = WR5000;
+  wk1r = WR1250;
+  wk1i = WI1250;
+  wk2r = WR2500;
+  wk2i = WI2500;
+  wk3r = WR3750;
+  wk3i = WI3750;
+  x1r = a[0] - a[17];
+  x1i = a[1] + a[16];
+  x0r = a[8] - a[25];
+  x0i = a[9] + a[24];
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  y0r = x1r + x2r;
+  y0i = x1i + x2i;
+  y4r = x1r - x2r;
+  y4i = x1i - x2i;
+  x1r = a[0] + a[17];
+  x1i = a[1] - a[16];
+  x0r = a[8] + a[25];
+  x0i = a[9] - a[24];
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  y8r = x1r - x2i;
+  y8i = x1i + x2r;
+  y12r = x1r + x2i;
+  y12i = x1i - x2r;
+  x0r = a[2] - a[19];
+  x0i = a[3] + a[18];
+  x1r = wk1r * x0r - wk1i * x0i;
+  x1i = wk1r * x0i + wk1i * x0r;
+  x0r = a[10] - a[27];
+  x0i = a[11] + a[26];
+  x2r = wk3i * x0r - wk3r * x0i;
+  x2i = wk3i * x0i + wk3r * x0r;
+  y1r = x1r + x2r;
+  y1i = x1i + x2i;
+  y5r = x1r - x2r;
+  y5i = x1i - x2i;
+  x0r = a[2] + a[19];
+  x0i = a[3] - a[18];
+  x1r = wk3r * x0r - wk3i * x0i;
+  x1i = wk3r * x0i + wk3i * x0r;
+  x0r = a[10] + a[27];
+  x0i = a[11] - a[26];
+  x2r = wk1r * x0r + wk1i * x0i;
+  x2i = wk1r * x0i - wk1i * x0r;
+  y9r = x1r - x2r;
+  y9i = x1i - x2i;
+  y13r = x1r + x2r;
+  y13i = x1i + x2i;
+  x0r = a[4] - a[21];
+  x0i = a[5] + a[20];
+  x1r = wk2r * x0r - wk2i * x0i;
+  x1i = wk2r * x0i + wk2i * x0r;
+  x0r = a[12] - a[29];
+  x0i = a[13] + a[28];
+  x2r = wk2i * x0r - wk2r * x0i;
+  x2i = wk2i * x0i + wk2r * x0r;
+  y2r = x1r + x2r;
+  y2i = x1i + x2i;
+  y6r = x1r - x2r;
+  y6i = x1i - x2i;
+  x0r = a[4] + a[21];
+  x0i = a[5] - a[20];
+  x1r = wk2i * x0r - wk2r * x0i;
+  x1i = wk2i * x0i + wk2r * x0r;
+  x0r = a[12] + a[29];
+  x0i = a[13] - a[28];
+  x2r = wk2r * x0r - wk2i * x0i;
+  x2i = wk2r * x0i + wk2i * x0r;
+  y10r = x1r - x2r;
+  y10i = x1i - x2i;
+  y14r = x1r + x2r;
+  y14i = x1i + x2i;
+  x0r = a[6] - a[23];
+  x0i = a[7] + a[22];
+  x1r = wk3r * x0r - wk3i * x0i;
+  x1i = wk3r * x0i + wk3i * x0r;
+  x0r = a[14] - a[31];
+  x0i = a[15] + a[30];
+  x2r = wk1i * x0r - wk1r * x0i;
+  x2i = wk1i * x0i + wk1r * x0r;
+  y3r = x1r + x2r;
+  y3i = x1i + x2i;
+  y7r = x1r - x2r;
+  y7i = x1i - x2i;
+  x0r = a[6] + a[23];
+  x0i = a[7] - a[22];
+  x1r = wk1i * x0r + wk1r * x0i;
+  x1i = wk1i * x0i - wk1r * x0r;
+  x0r = a[14] + a[31];
+  x0i = a[15] - a[30];
+  x2r = wk3i * x0r - wk3r * x0i;
+  x2i = wk3i * x0i + wk3r * x0r;
+  y11r = x1r + x2r;
+  y11i = x1i + x2i;
+  y15r = x1r - x2r;
+  y15i = x1i - x2i;
+  x1r = y0r + y2r;
+  x1i = y0i + y2i;
+  x2r = y1r + y3r;
+  x2i = y1i + y3i;
+  a[0] = x1r + x2r;
+  a[1] = x1i + x2i;
+  a[2] = x1r - x2r;
+  a[3] = x1i - x2i;
+  x1r = y0r - y2r;
+  x1i = y0i - y2i;
+  x2r = y1r - y3r;
+  x2i = y1i - y3i;
+  a[4] = x1r - x2i;
+  a[5] = x1i + x2r;
+  a[6] = x1r + x2i;
+  a[7] = x1i - x2r;
+  x1r = y4r - y6i;
+  x1i = y4i + y6r;
+  x0r = y5r - y7i;
+  x0i = y5i + y7r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  a[8] = x1r + x2r;
+  a[9] = x1i + x2i;
+  a[10] = x1r - x2r;
+  a[11] = x1i - x2i;
+  x1r = y4r + y6i;
+  x1i = y4i - y6r;
+  x0r = y5r + y7i;
+  x0i = y5i - y7r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  a[12] = x1r - x2i;
+  a[13] = x1i + x2r;
+  a[14] = x1r + x2i;
+  a[15] = x1i - x2r;
+  x1r = y8r + y10r;
+  x1i = y8i + y10i;
+  x2r = y9r - y11r;
+  x2i = y9i - y11i;
+  a[16] = x1r + x2r;
+  a[17] = x1i + x2i;
+  a[18] = x1r - x2r;
+  a[19] = x1i - x2i;
+  x1r = y8r - y10r;
+  x1i = y8i - y10i;
+  x2r = y9r + y11r;
+  x2i = y9i + y11i;
+  a[20] = x1r - x2i;
+  a[21] = x1i + x2r;
+  a[22] = x1r + x2i;
+  a[23] = x1i - x2r;
+  x1r = y12r - y14i;
+  x1i = y12i + y14r;
+  x0r = y13r + y15i;
+  x0i = y13i - y15r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  a[24] = x1r + x2r;
+  a[25] = x1i + x2i;
+  a[26] = x1r - x2r;
+  a[27] = x1i - x2i;
+  x1r = y12r + y14i;
+  x1i = y12i - y14r;
+  x0r = y13r - y15i;
+  x0i = y13i + y15r;
+  x2r = wn4r * (x0r - x0i);
+  x2i = wn4r * (x0i + x0r);
+  a[28] = x1r - x2i;
+  a[29] = x1i + x2r;
+  a[30] = x1r + x2i;
+  a[31] = x1i - x2r;
+}
+
+void cftf081(double *a) {
+  double wn4r, x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i, y0r, y0i, y1r, y1i, y2r, y2i, y3r, y3i, y4r, y4i, y5r, y5i, y6r, y6i, y7r, y7i;
+
+  wn4r = WR5000;
+  x0r = a[0] + a[8];
+  x0i = a[1] + a[9];
+  x1r = a[0] - a[8];
+  x1i = a[1] - a[9];
+  x2r = a[4] + a[12];
+  x2i = a[5] + a[13];
+  x3r = a[4] - a[12];
+  x3i = a[5] - a[13];
+  y0r = x0r + x2r;
+  y0i = x0i + x2i;
+  y2r = x0r - x2r;
+  y2i = x0i - x2i;
+  y1r = x1r - x3i;
+  y1i = x1i + x3r;
+  y3r = x1r + x3i;
+  y3i = x1i - x3r;
+  x0r = a[2] + a[10];
+  x0i = a[3] + a[11];
+  x1r = a[2] - a[10];
+  x1i = a[3] - a[11];
+  x2r = a[6] + a[14];
+  x2i = a[7] + a[15];
+  x3r = a[6] - a[14];
+  x3i = a[7] - a[15];
+  y4r = x0r + x2r;
+  y4i = x0i + x2i;
+  y6r = x0r - x2r;
+  y6i = x0i - x2i;
+  x0r = x1r - x3i;
+  x0i = x1i + x3r;
+  x2r = x1r + x3i;
+  x2i = x1i - x3r;
+  y5r = wn4r * (x0r - x0i);
+  y5i = wn4r * (x0r + x0i);
+  y7r = wn4r * (x2r - x2i);
+  y7i = wn4r * (x2r + x2i);
+  a[8] = y1r + y5r;
+  a[9] = y1i + y5i;
+  a[10] = y1r - y5r;
+  a[11] = y1i - y5i;
+  a[12] = y3r - y7i;
+  a[13] = y3i + y7r;
+  a[14] = y3r + y7i;
+  a[15] = y3i - y7r;
+  a[0] = y0r + y4r;
+  a[1] = y0i + y4i;
+  a[2] = y0r - y4r;
+  a[3] = y0i - y4i;
+  a[4] = y2r - y6i;
+  a[5] = y2i + y6r;
+  a[6] = y2r + y6i;
+  a[7] = y2i - y6r;
+}
+
+void cftf082(double *a) {
+  double wn4r, wk1r, wk1i, x0r, x0i, x1r, x1i, y0r, y0i, y1r, y1i, y2r, y2i, y3r, y3i, y4r, y4i, y5r, y5i, y6r, y6i, y7r, y7i;
+
+  wn4r = WR5000;
+  wk1r = WR2500;
+  wk1i = WI2500;
+  y0r = a[0] - a[9];
+  y0i = a[1] + a[8];
+  y1r = a[0] + a[9];
+  y1i = a[1] - a[8];
+  x0r = a[4] - a[13];
+  x0i = a[5] + a[12];
+  y2r = wn4r * (x0r - x0i);
+  y2i = wn4r * (x0i + x0r);
+  x0r = a[4] + a[13];
+  x0i = a[5] - a[12];
+  y3r = wn4r * (x0r - x0i);
+  y3i = wn4r * (x0i + x0r);
+  x0r = a[2] - a[11];
+  x0i = a[3] + a[10];
+  y4r = wk1r * x0r - wk1i * x0i;
+  y4i = wk1r * x0i + wk1i * x0r;
+  x0r = a[2] + a[11];
+  x0i = a[3] - a[10];
+  y5r = wk1i * x0r - wk1r * x0i;
+  y5i = wk1i * x0i + wk1r * x0r;
+  x0r = a[6] - a[15];
+  x0i = a[7] + a[14];
+  y6r = wk1i * x0r - wk1r * x0i;
+  y6i = wk1i * x0i + wk1r * x0r;
+  x0r = a[6] + a[15];
+  x0i = a[7] - a[14];
+  y7r = wk1r * x0r - wk1i * x0i;
+  y7i = wk1r * x0i + wk1i * x0r;
+  x0r = y0r + y2r;
+  x0i = y0i + y2i;
+  x1r = y4r + y6r;
+  x1i = y4i + y6i;
+  a[0] = x0r + x1r;
+  a[1] = x0i + x1i;
+  a[2] = x0r - x1r;
+  a[3] = x0i - x1i;
+  x0r = y0r - y2r;
+  x0i = y0i - y2i;
+  x1r = y4r - y6r;
+  x1i = y4i - y6i;
+  a[4] = x0r - x1i;
+  a[5] = x0i + x1r;
+  a[6] = x0r + x1i;
+  a[7] = x0i - x1r;
+  x0r = y1r - y3i;
+  x0i = y1i + y3r;
+  x1r = y5r - y7r;
+  x1i = y5i - y7i;
+  a[8] = x0r + x1r;
+  a[9] = x0i + x1i;
+  a[10] = x0r - x1r;
+  a[11] = x0i - x1i;
+  x0r = y1r + y3i;
+  x0i = y1i - y3r;
+  x1r = y5r + y7r;
+  x1i = y5i + y7i;
+  a[12] = x0r - x1i;
+  a[13] = x0i + x1r;
+  a[14] = x0r + x1i;
+  a[15] = x0i - x1r;
+}
+
+void cftf040(double *a) {
+  double x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i;
+
+  x0r = a[0] + a[4];
+  x0i = a[1] + a[5];
+  x1r = a[0] - a[4];
+  x1i = a[1] - a[5];
+  x2r = a[2] + a[6];
+  x2i = a[3] + a[7];
+  x3r = a[2] - a[6];
+  x3i = a[3] - a[7];
+  a[0] = x0r + x2r;
+  a[1] = x0i + x2i;
+  a[4] = x0r - x2r;
+  a[5] = x0i - x2i;
+  a[2] = x1r - x3i;
+  a[3] = x1i + x3r;
+  a[6] = x1r + x3i;
+  a[7] = x1i - x3r;
+}
+
+void cftb040(double *a) {
+  double x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i;
+
+  x0r = a[0] + a[4];
+  x0i = a[1] + a[5];
+  x1r = a[0] - a[4];
+  x1i = a[1] - a[5];
+  x2r = a[2] + a[6];
+  x2i = a[3] + a[7];
+  x3r = a[2] - a[6];
+  x3i = a[3] - a[7];
+  a[0] = x0r + x2r;
+  a[1] = x0i + x2i;
+  a[4] = x0r - x2r;
+  a[5] = x0i - x2i;
+  a[2] = x1r + x3i;
+  a[3] = x1i - x3r;
+  a[6] = x1r - x3i;
+  a[7] = x1i + x3r;
+}
+
+void cftx020(double *a) {
+  double x0r, x0i;
+
+  x0r = a[0] - a[2];
+  x0i = a[1] - a[3];
+  a[0] += a[2];
+  a[1] += a[3];
+  a[2] = x0r;
+  a[3] = x0i;
+}
+
+void rftfsub(int n, double *a) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss, xr, xi, yr, yi;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 4) {
+      i0 = 4;
+    }
+    for (j = i - 4; j >= i0; j -= 4) {
+      k = n - j;
+      xr = a[j + 2] - a[k - 2];
+      xi = a[j + 3] + a[k - 1];
+      yr = wdr * xr - wdi * xi;
+      yi = wdr * xi + wdi * xr;
+      a[j + 2] -= yr;
+      a[j + 3] -= yi;
+      a[k - 2] += yr;
+      a[k - 1] -= yi;
+      wkr += ss * wdi;
+      wki += ss * (0.5 - wdr);
+      xr = a[j] - a[k];
+      xi = a[j + 1] + a[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      a[j] -= yr;
+      a[j + 1] -= yi;
+      a[k] += yr;
+      a[k + 1] -= yi;
+      wdr += ss * wki;
+      wdi += ss * (0.5 - wkr);
+    }
+    if (i0 == 4) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+  xr = a[2] - a[n - 2];
+  xi = a[3] + a[n - 1];
+  yr = wdr * xr - wdi * xi;
+  yi = wdr * xi + wdi * xr;
+  a[2] -= yr;
+  a[3] -= yi;
+  a[n - 2] += yr;
+  a[n - 1] -= yi;
+}
+
+void rftbsub(int n, double *a) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss, xr, xi, yr, yi;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 4) {
+      i0 = 4;
+    }
+    for (j = i - 4; j >= i0; j -= 4) {
+      k = n - j;
+      xr = a[j + 2] - a[k - 2];
+      xi = a[j + 3] + a[k - 1];
+      yr = wdr * xr + wdi * xi;
+      yi = wdr * xi - wdi * xr;
+      a[j + 2] -= yr;
+      a[j + 3] -= yi;
+      a[k - 2] += yr;
+      a[k - 1] -= yi;
+      wkr += ss * wdi;
+      wki += ss * (0.5 - wdr);
+      xr = a[j] - a[k];
+      xi = a[j + 1] + a[k + 1];
+      yr = wkr * xr + wki * xi;
+      yi = wkr * xi - wki * xr;
+      a[j] -= yr;
+      a[j + 1] -= yi;
+      a[k] += yr;
+      a[k + 1] -= yi;
+      wdr += ss * wki;
+      wdi += ss * (0.5 - wkr);
+    }
+    if (i0 == 4) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+  xr = a[2] - a[n - 2];
+  xi = a[3] + a[n - 1];
+  yr = wdr * xr + wdi * xi;
+  yi = wdr * xi - wdi * xr;
+  a[2] -= yr;
+  a[3] -= yi;
+  a[n - 2] += yr;
+  a[n - 1] -= yi;
+}
+
+void dctsub(int n, double *a) {
+  int i, i0, j, k, m;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss, xr, xi, yr, yi;
+
+  ec = M_PI_2 / n;
+  wkr = 0.5;
+  wki = 0.5;
+  w1r = cos(ec);
+  w1i = sin(ec);
+  wdr = 0.5 * (w1r - w1i);
+  wdi = 0.5 * (w1r + w1i);
+  ss = 2 * w1i;
+  m = n >> 1;
+  i = 0;
+  for (;;) {
+    i0 = i + 2 * DCST_LOOP_DIV;
+    if (i0 > m - 2) {
+      i0 = m - 2;
+    }
+    for (j = i + 2; j <= i0; j += 2) {
+      k = n - j;
+      xr = wdi * a[j - 1] - wdr * a[k + 1];
+      xi = wdr * a[j - 1] + wdi * a[k + 1];
+      wkr -= ss * wdi;
+      wki += ss * wdr;
+      yr = wki * a[j] - wkr * a[k];
+      yi = wkr * a[j] + wki * a[k];
+      wdr -= ss * wki;
+      wdi += ss * wkr;
+      a[k + 1] = xr;
+      a[k] = yr;
+      a[j - 1] = xi;
+      a[j] = yi;
+    }
+    if (i0 == m - 2) {
+      break;
+    }
+    wdr = cos(ec * i0);
+    wdi = sin(ec * i0);
+    wkr = 0.5 * (wdr - wdi);
+    wki = 0.5 * (wdr + wdi);
+    wdr = wkr * w1r - wki * w1i;
+    wdi = wkr * w1i + wki * w1r;
+    i = i0;
+  }
+  xr = wdi * a[m - 1] - wdr * a[m + 1];
+  a[m - 1] = wdr * a[m - 1] + wdi * a[m + 1];
+  a[m + 1] = xr;
+  a[m] *= wki + ss * wdr;
+}
+
+void dstsub(int n, double *a) {
+  int i, i0, j, k, m;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss, xr, xi, yr, yi;
+
+  ec = M_PI_2 / n;
+  wkr = 0.5;
+  wki = 0.5;
+  w1r = cos(ec);
+  w1i = sin(ec);
+  wdr = 0.5 * (w1r - w1i);
+  wdi = 0.5 * (w1r + w1i);
+  ss = 2 * w1i;
+  m = n >> 1;
+  i = 0;
+  for (;;) {
+    i0 = i + 2 * DCST_LOOP_DIV;
+    if (i0 > m - 2) {
+      i0 = m - 2;
+    }
+    for (j = i + 2; j <= i0; j += 2) {
+      k = n - j;
+      xr = wdi * a[k + 1] - wdr * a[j - 1];
+      xi = wdr * a[k + 1] + wdi * a[j - 1];
+      wkr -= ss * wdi;
+      wki += ss * wdr;
+      yr = wki * a[k] - wkr * a[j];
+      yi = wkr * a[k] + wki * a[j];
+      wdr -= ss * wki;
+      wdi += ss * wkr;
+      a[j - 1] = xr;
+      a[j] = yr;
+      a[k + 1] = xi;
+      a[k] = yi;
+    }
+    if (i0 == m - 2) {
+      break;
+    }
+    wdr = cos(ec * i0);
+    wdi = sin(ec * i0);
+    wkr = 0.5 * (wdr - wdi);
+    wki = 0.5 * (wdr + wdi);
+    wdr = wkr * w1r - wki * w1i;
+    wdi = wkr * w1i + wki * w1r;
+    i = i0;
+  }
+  xr = wdi * a[m + 1] - wdr * a[m - 1];
+  a[m + 1] = wdr * a[m + 1] + wdi * a[m - 1];
+  a[m - 1] = xr;
+  a[m] *= wki + ss * wdr;
+}
+
+void dctsub4(int n, double *a) {
+  int m;
+  double wki, wdr, wdi, xr;
+
+  wki = WR5000;
+  m = n >> 1;
+  if (m == 2) {
+    wdr = wki * WI2500;
+    wdi = wki * WR2500;
+    xr = wdi * a[1] - wdr * a[3];
+    a[1] = wdr * a[1] + wdi * a[3];
+    a[3] = xr;
+  }
+  a[m] *= wki;
+}
+
+void dstsub4(int n, double *a) {
+  int m;
+  double wki, wdr, wdi, xr;
+
+  wki = WR5000;
+  m = n >> 1;
+  if (m == 2) {
+    wdr = wki * WI2500;
+    wdi = wki * WR2500;
+    xr = wdi * a[3] - wdr * a[1];
+    a[3] = wdr * a[3] + wdi * a[1];
+    a[1] = xr;
+  }
+  a[m] *= wki;
+}
diff --git a/tests/performance/superpi/fftsg_h.h b/tests/performance/superpi/fftsg_h.h
new file mode 100644
index 00000000000..3158ce80ab0
--- /dev/null
+++ b/tests/performance/superpi/fftsg_h.h
@@ -0,0 +1,88 @@
+/*
+  Based on "Calculation of PI(= 3.14159...) using FFT and AGM" by T.Ooura, Nov. 1999.
+  https://github.com/Fibonacci43/SuperPI
+  Modified for Arduino by Lucas Saavedra Vaz, 2024.
+*/
+
+#pragma once
+
+#include <math.h>
+
+#ifndef M_PI_2
+#define M_PI_2 1.570796326794896619231321691639751442098584699687
+#endif
+#ifndef WR5000 /* cos(M_PI_2*0.5000) */
+#define WR5000 0.707106781186547524400844362104849039284835937688
+#endif
+#ifndef WR2500 /* cos(M_PI_2*0.2500) */
+#define WR2500 0.923879532511286756128183189396788286822416625863
+#endif
+#ifndef WI2500 /* sin(M_PI_2*0.2500) */
+#define WI2500 0.382683432365089771728459984030398866761344562485
+#endif
+#ifndef WR1250 /* cos(M_PI_2*0.1250) */
+#define WR1250 0.980785280403230449126182236134239036973933730893
+#endif
+#ifndef WI1250 /* sin(M_PI_2*0.1250) */
+#define WI1250 0.195090322016128267848284868477022240927691617751
+#endif
+#ifndef WR3750 /* cos(M_PI_2*0.3750) */
+#define WR3750 0.831469612302545237078788377617905756738560811987
+#endif
+#ifndef WI3750 /* sin(M_PI_2*0.3750) */
+#define WI3750 0.555570233019602224742830813948532874374937190754
+#endif
+
+#ifndef CDFT_RECURSIVE_N     /* length of the recursive FFT mode */
+#define CDFT_RECURSIVE_N 512 /* <= (L1 cache size) / 16 */
+#endif
+
+#ifndef CDFT_LOOP_DIV /* control of the CDFT's speed & tolerance */
+#define CDFT_LOOP_DIV 32
+#endif
+
+#ifndef RDFT_LOOP_DIV /* control of the RDFT's speed & tolerance */
+#define RDFT_LOOP_DIV 64
+#endif
+
+#ifndef DCST_LOOP_DIV /* control of the DCT,DST's speed & tolerance */
+#define DCST_LOOP_DIV 64
+#endif
+
+void bitrv1(int n, double *a);
+void bitrv2(int n, double *a);
+void bitrv208(double *a);
+void bitrv208neg(double *a);
+void bitrv216(double *a);
+void bitrv216neg(double *a);
+void bitrv2conj(int n, double *a);
+void cdft(int n, int isgn, double *a);
+void cftb040(double *a);
+void cftb1st(int n, double *a);
+void cftbsub(int n, double *a);
+void cftexp1(int n, double *a);
+void cftexp2(int n, double *a);
+void cftf040(double *a);
+void cftf081(double *a);
+void cftf082(double *a);
+void cftf161(double *a);
+void cftf162(double *a);
+void cftfsub(int n, double *a);
+void cftfx41(int n, double *a);
+void cftfx42(int n, double *a);
+void cftmdl1(int n, double *a);
+void cftmdl2(int n, double *a);
+void cftrec1(int n, double *a);
+void cftrec2(int n, double *a);
+void cftx020(double *a);
+void dctsub(int n, double *a);
+void dctsub4(int n, double *a);
+void ddct(int n, int isgn, double *a);
+void ddst(int n, int isgn, double *a);
+void dfct(int n, double *a);
+void dfst(int n, double *a);
+void dstsub(int n, double *a);
+void dstsub4(int n, double *a);
+void rdft(int n, int isgn, double *a);
+void rftbsub(int n, double *a);
+void rftfsub(int n, double *a);
diff --git a/tests/performance/superpi/pi_fftcs.cpp b/tests/performance/superpi/pi_fftcs.cpp
new file mode 100644
index 00000000000..bf83dd29133
--- /dev/null
+++ b/tests/performance/superpi/pi_fftcs.cpp
@@ -0,0 +1,2214 @@
+/*
+  Based on "Calculation of PI(= 3.14159...) using FFT and AGM" by T.Ooura, Nov. 1999.
+  https://github.com/Fibonacci43/SuperPI
+  Modified for Arduino by Lucas Saavedra Vaz, 2024.
+*/
+
+#include <Arduino.h>
+#include <assert.h>
+#include <math.h>
+#include <limits.h>
+#include <float.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "fftsg_h.h"
+#include "pi_fftcs.h"
+
+void pi_calc(int nfft) {
+  int log2_nfft, radix, log10_radix, n, npow, nprc;
+#if PRINT_DIGITS
+  int j = 0, k = 0, l = 0;
+#endif
+  double err;
+  int *a, *b, *c, *e, *i1, *i2;
+  double *d1, *d2, *d3;
+  char *dgt;
+  uint32_t start_time;
+  double elap_time, loop_time;
+  log_d("Calculation of PI using FFT and AGM, %s", PI_FFTC_VER);
+
+  // DGTINT is defined as short int, so it should be 2 bytes
+  assert(sizeof(DGTINT) == 2);
+
+  log_d("initializing...");
+  nfft /= 4;
+  start_time = millis();
+  for (log2_nfft = 1; (1 << log2_nfft) < nfft; log2_nfft++);
+  nfft = 1 << log2_nfft;
+  n = nfft + 2;
+  a = (int *)malloc(2 * sizeof(int) + n * sizeof(DGTINT));
+  b = (int *)malloc(2 * sizeof(int) + n * sizeof(DGTINT));
+  c = (int *)malloc(2 * sizeof(int) + n * sizeof(DGTINT));
+  e = (int *)malloc(2 * sizeof(int) + n * sizeof(DGTINT));
+  i1 = (int *)malloc(2 * sizeof(int) + n * sizeof(DGTINT));
+  i2 = (int *)malloc(2 * sizeof(int) + n * sizeof(DGTINT));
+  d1 = (double *)malloc((nfft + 2) * sizeof(double));
+  d2 = (double *)malloc((nfft + 2) * sizeof(double));
+  d3 = (double *)malloc((nfft + 2) * sizeof(double));
+  if (d3 == NULL) {
+    printf("Allocation Failure!\n");
+    exit(1);
+  }
+  /* ---- radix test ---- */
+  log10_radix = 1;
+  radix = 10;
+  err = mp_mul_radix_test(n, radix, nfft, d1);
+  err += DBL_EPSILON * (n * radix * radix / 4);
+  while (100 * err < DBL_ERROR_MARGIN && radix <= DGTINT_MAX / 20) {
+    err *= 100;
+    log10_radix++;
+    radix *= 10;
+  }
+  log_d("nfft= %d, radix= %d, error_margin= %g", nfft, radix, err);
+  log_d("calculating %d digits of PI...", log10_radix * (n - 2));
+  /*
+   * ---- a formula based on the AGM (Arithmetic-Geometric Mean) ----
+   *   c = sqrt(0.125);
+   *   a = 1 + 3 * c;
+   *   b = sqrt(a);
+   *   e = b - 0.625;
+   *   b = 2 * b;
+   *   c = e - c;
+   *   a = a + e;
+   *   npow = 4;
+   *   do {
+   *       npow = 2 * npow;
+   *       e = (a + b) / 2;
+   *       b = sqrt(a * b);
+   *       e = e - b;
+   *       b = 2 * b;
+   *       c = c - e;
+   *       a = e + b;
+   *   } while (e > SQRT_SQRT_EPSILON);
+   *   e = e * e / 4;
+   *   a = a + b;
+   *   pi = (a * a - e - e / 2) / (a * c - e) / npow;
+   * ---- modification ----
+   *   This is a modified version of Gauss-Legendre formula
+   *   (by T.Ooura). It is faster than original version.
+   * ---- reference ----
+   *   1. E.Salamin,
+   *      Computation of PI Using Arithmetic-Geometric Mean,
+   *      Mathematics of Computation, Vol.30 1976.
+   *   2. R.P.Brent,
+   *      Fast Multiple-Precision Evaluation of Elementary Functions,
+   *      J. ACM 23 1976.
+   *   3. D.Takahasi, Y.Kanada,
+   *      Calculation of PI to 51.5 Billion Decimal Digits on
+   *      Distributed Memoriy Parallel Processors,
+   *      Transactions of Information Processing Society of Japan,
+   *      Vol.39 No.7 1998.
+   *   4. T.Ooura,
+   *      Improvement of the PI Calculation Algorithm and
+   *      Implementation of Fast Multiple-Precision Computation,
+   *      Information Processing Society of Japan SIG Notes,
+   *      98-HPC-74, 1998.
+   */
+  /* ---- c = 1 / sqrt(8) ---- */
+  mp_invisqrt(n, radix, 8, c, i1, i2, nfft, d1, d2);
+  /* ---- a = 1 + 3 * c ---- */
+  mp_imul(n, radix, c, 3, e);
+  mp_sscanf(n, log10_radix, (char *)"1", a);
+  mp_add(n, radix, a, e, a);
+  /* ---- b = sqrt(a) ---- */
+  mp_sqrt(n, radix, a, b, i1, i2, nfft, d1, d2);
+  /* ---- e = b - 0.625 ---- */
+  mp_sscanf(n, log10_radix, (char *)"0.625", e);
+  mp_sub(n, radix, b, e, e);
+  /* ---- b = 2 * b ---- */
+  mp_add(n, radix, b, b, b);
+  /* ---- c = e - c ---- */
+  mp_sub(n, radix, e, c, c);
+  /* ---- a = a + e ---- */
+  mp_add(n, radix, a, e, a);
+  log_d("AGM iteration");
+  npow = 4;
+  elap_time = ((double)(millis() - start_time)) / 1000;
+
+  do {
+    uint32_t start_loop_time = millis();
+    npow *= 2;
+    /* ---- e = (a + b) / 2 ---- */
+    mp_add(n, radix, a, b, e);
+    mp_idiv_2(n, radix, e, e);
+    /* ---- b = sqrt(a * b) ---- */
+    mp_mul(n, radix, a, b, a, i1, nfft, d1, d2, d3);
+    mp_sqrt(n, radix, a, b, i1, i2, nfft, d1, d2);
+    /* ---- e = e - b ---- */
+    mp_sub(n, radix, e, b, e);
+    /* ---- b = 2 * b ---- */
+    mp_add(n, radix, b, b, b);
+    /* ---- c = c - e ---- */
+    mp_sub(n, radix, c, e, c);
+    /* ---- a = e + b ---- */
+    mp_add(n, radix, e, b, a);
+    /* ---- convergence check ---- */
+    nprc = -e[1];
+    if (e[0] == 0) {
+      nprc = n;
+    }
+    loop_time = ((double)(millis() - start_loop_time)) / 1000;
+    elap_time += loop_time;
+    log_d("precision= %d: %0.2f sec", 4 * nprc * log10_radix, loop_time);
+  } while (4 * nprc <= n);
+  start_time = millis();
+  /* ---- e = e * e / 4 (half precision) ---- */
+  mp_idiv_2(n, radix, e, e);
+  mp_squh(n, radix, e, e, nfft, d1);
+  /* ---- a = a + b ---- */
+  mp_add(n, radix, a, b, a);
+  /* ---- a = (a * a - e - e / 2) / (a * c - e) / npow ---- */
+  mp_mulhf(n, radix, a, c, c, i1, nfft, d1, d2);
+  mp_sub(n, radix, c, e, c);
+  mp_inv(n, radix, c, b, i1, i2, nfft, d2, d3);
+  mp_squhf_use_infft(n, radix, d1, a, a, i1, nfft, d2);
+  mp_sub(n, radix, a, e, a);
+  mp_idiv_2(n, radix, e, e);
+  mp_sub(n, radix, a, e, a);
+  mp_mul(n, radix, a, b, a, i1, nfft, d1, d2, d3);
+  mp_idiv(n, radix, a, npow, a);
+  /* ---- output ---- */
+  dgt = (char *)d1;
+  mp_sprintf(n - 1, log10_radix, a, dgt);
+  elap_time = ((double)(millis() - start_time)) / 1000;
+
+#if PRINT_DIGITS
+  do {
+    if (!isdigit(*dgt)) {
+      if (isalpha(*dgt) != 0) {
+        fputc('\n', stdout);
+        fputc('\n', stdout);
+      }
+      fputc(*dgt, stdout);
+      fputc('\n', stdout);
+      fputc('\n', stdout);
+      j = 0;
+      k = 0;
+      l = 0;
+      continue;
+    }
+    fputc(*dgt, stdout);
+    if (++j >= DGT_PACK) {
+      j = 0;
+      if (++k >= DGT_PACK_LINE) {
+        k = 0;
+        fputc('\n', stdout);
+        if (++l >= DGT_LINE_BLOCK) {
+          l = 0;
+          fputc('\n', stdout);
+        }
+      } else {
+        fputc(' ', stdout);
+      }
+    }
+  } while (*dgt++ && *dgt != 'e');
+  fputc('\n', stdout);
+  fprintf(stdout, "%s\n", dgt);
+#endif
+
+  free(d3);
+  free(d2);
+  free(d1);
+  free(i2);
+  free(i1);
+  free(e);
+  free(c);
+  free(b);
+  free(a);
+  /* ---- difftime ---- */
+  log_d("%0.2f sec. (real time)", elap_time);
+}
+
+/* -------- multiple precision routines -------- */
+
+/* -------- mp_load routines -------- */
+
+void mp_load_0(int n, int radix, int out[]) {
+  int j;
+  DGTINT *outr;
+
+  outr = ((DGTINT *)&out[2]) - 2;
+  out[0] = 0;
+  out[1] = 0;
+  for (j = 2; j <= n + 1; j++) {
+    outr[j] = 0;
+  }
+}
+
+void mp_load_1(int n, int radix, int out[]) {
+  int j;
+  DGTINT *outr;
+
+  outr = ((DGTINT *)&out[2]) - 2;
+  out[0] = 1;
+  out[1] = 0;
+  outr[2] = 1;
+  for (j = 3; j <= n + 1; j++) {
+    outr[j] = 0;
+  }
+}
+
+void mp_round(int n, int radix, int m, int inout[]) {
+  int j, x;
+  DGTINT *inoutr;
+
+  inoutr = ((DGTINT *)&inout[2]) - 2;
+  if (m < n) {
+    for (j = n + 1; j > m + 2; j--) {
+      inoutr[j] = 0;
+    }
+    x = 2 * inoutr[m + 2];
+    inoutr[m + 2] = 0;
+    if (x >= radix) {
+      for (j = m + 1; j >= 2; j--) {
+        x = inoutr[j] + 1;
+        if (x < radix) {
+          inoutr[j] = (DGTINT)x;
+          break;
+        }
+        inoutr[j] = 0;
+      }
+      if (x >= radix) {
+        inoutr[2] = 1;
+        inout[1]++;
+      }
+    }
+  }
+}
+
+/* -------- mp_add routines -------- */
+
+int mp_cmp(int n, int radix, int in1[], int in2[]) {
+  int mp_unsgn_cmp(int n, int in1[], int in2[]);
+
+  if (in1[0] > in2[0]) {
+    return 1;
+  } else if (in1[0] < in2[0]) {
+    return -1;
+  }
+  return in1[0] * mp_unsgn_cmp(n, &in1[1], &in2[1]);
+}
+
+void mp_add(int n, int radix, int in1[], int in2[], int out[]) {
+  int mp_unsgn_cmp(int n, int in1[], int in2[]);
+  int mp_unexp_add(int n, int radix, int expdif, DGTINT in1[], DGTINT in2[], DGTINT out[]);
+  int mp_unexp_sub(int n, int radix, int expdif, DGTINT in1[], DGTINT in2[], DGTINT out[]);
+  int outsgn, outexp, expdif;
+
+  expdif = in1[1] - in2[1];
+  outexp = in1[1];
+  if (expdif < 0) {
+    outexp = in2[1];
+  }
+  outsgn = in1[0] * in2[0];
+  if (outsgn >= 0) {
+    if (outsgn > 0) {
+      outsgn = in1[0];
+    } else {
+      outsgn = in1[0] + in2[0];
+      outexp = in1[1] + in2[1];
+      expdif = 0;
+    }
+    if (expdif >= 0) {
+      outexp += mp_unexp_add(n, radix, expdif, (DGTINT *)&in1[2], (DGTINT *)&in2[2], (DGTINT *)&out[2]);
+    } else {
+      outexp += mp_unexp_add(n, radix, -expdif, (DGTINT *)&in2[2], (DGTINT *)&in1[2], (DGTINT *)&out[2]);
+    }
+  } else {
+    outsgn = mp_unsgn_cmp(n, &in1[1], &in2[1]);
+    if (outsgn >= 0) {
+      expdif = mp_unexp_sub(n, radix, expdif, (DGTINT *)&in1[2], (DGTINT *)&in2[2], (DGTINT *)&out[2]);
+    } else {
+      expdif = mp_unexp_sub(n, radix, -expdif, (DGTINT *)&in2[2], (DGTINT *)&in1[2], (DGTINT *)&out[2]);
+    }
+    outexp -= expdif;
+    outsgn *= in1[0];
+    if (expdif == n) {
+      outsgn = 0;
+    }
+  }
+  if (outsgn == 0) {
+    outexp = 0;
+  }
+  out[0] = outsgn;
+  out[1] = outexp;
+}
+
+void mp_sub(int n, int radix, int in1[], int in2[], int out[]) {
+  int mp_unsgn_cmp(int n, int in1[], int in2[]);
+  int mp_unexp_add(int n, int radix, int expdif, DGTINT in1[], DGTINT in2[], DGTINT out[]);
+  int mp_unexp_sub(int n, int radix, int expdif, DGTINT in1[], DGTINT in2[], DGTINT out[]);
+  int outsgn, outexp, expdif;
+
+  expdif = in1[1] - in2[1];
+  outexp = in1[1];
+  if (expdif < 0) {
+    outexp = in2[1];
+  }
+  outsgn = in1[0] * in2[0];
+  if (outsgn <= 0) {
+    if (outsgn < 0) {
+      outsgn = in1[0];
+    } else {
+      outsgn = in1[0] - in2[0];
+      outexp = in1[1] + in2[1];
+      expdif = 0;
+    }
+    if (expdif >= 0) {
+      outexp += mp_unexp_add(n, radix, expdif, (DGTINT *)&in1[2], (DGTINT *)&in2[2], (DGTINT *)&out[2]);
+    } else {
+      outexp += mp_unexp_add(n, radix, -expdif, (DGTINT *)&in2[2], (DGTINT *)&in1[2], (DGTINT *)&out[2]);
+    }
+  } else {
+    outsgn = mp_unsgn_cmp(n, &in1[1], &in2[1]);
+    if (outsgn >= 0) {
+      expdif = mp_unexp_sub(n, radix, expdif, (DGTINT *)&in1[2], (DGTINT *)&in2[2], (DGTINT *)&out[2]);
+    } else {
+      expdif = mp_unexp_sub(n, radix, -expdif, (DGTINT *)&in2[2], (DGTINT *)&in1[2], (DGTINT *)&out[2]);
+    }
+    outexp -= expdif;
+    outsgn *= in1[0];
+    if (expdif == n) {
+      outsgn = 0;
+    }
+  }
+  if (outsgn == 0) {
+    outexp = 0;
+  }
+  out[0] = outsgn;
+  out[1] = outexp;
+}
+
+/* -------- mp_add child routines -------- */
+
+int mp_unsgn_cmp(int n, int in1[], int in2[]) {
+  int j, cmp;
+  DGTINT *in1r, *in2r;
+
+  in1r = ((DGTINT *)&in1[1]) - 1;
+  in2r = ((DGTINT *)&in2[1]) - 1;
+  cmp = in1[0] - in2[0];
+  for (j = 1; j <= n && cmp == 0; j++) {
+    cmp = in1r[j] - in2r[j];
+  }
+  if (cmp > 0) {
+    cmp = 1;
+  } else if (cmp < 0) {
+    cmp = -1;
+  }
+  return cmp;
+}
+
+int mp_unexp_add(int n, int radix, int expdif, DGTINT in1[], DGTINT in2[], DGTINT out[]) {
+  int j, x, carry;
+
+  carry = 0;
+  if (expdif == 0 && in1[0] + in2[0] >= radix) {
+    x = in1[n - 1] + in2[n - 1];
+    carry = x >= radix ? -1 : 0;
+    for (j = n - 1; j > 0; j--) {
+      x = in1[j - 1] + in2[j - 1] - carry;
+      carry = x >= radix ? -1 : 0;
+      out[j] = (DGTINT)(x - (radix & carry));
+    }
+    out[0] = (DGTINT)-carry;
+  } else {
+    if (expdif > n) {
+      expdif = n;
+    }
+    for (j = n - 1; j >= expdif; j--) {
+      x = in1[j] + in2[j - expdif] - carry;
+      carry = x >= radix ? -1 : 0;
+      out[j] = (DGTINT)(x - (radix & carry));
+    }
+    for (j = expdif - 1; j >= 0; j--) {
+      x = in1[j] - carry;
+      carry = x >= radix ? -1 : 0;
+      out[j] = (DGTINT)(x - (radix & carry));
+    }
+    if (carry != 0) {
+      for (j = n - 1; j > 0; j--) {
+        out[j] = out[j - 1];
+      }
+      out[0] = (DGTINT)-carry;
+    }
+  }
+  return -carry;
+}
+
+int mp_unexp_sub(int n, int radix, int expdif, DGTINT in1[], DGTINT in2[], DGTINT out[]) {
+  int j, x, borrow, ncancel;
+
+  if (expdif > n) {
+    expdif = n;
+  }
+  borrow = 0;
+  for (j = n - 1; j >= expdif; j--) {
+    x = in1[j] - in2[j - expdif] + borrow;
+    borrow = x < 0 ? -1 : 0;
+    out[j] = (DGTINT)(x + (radix & borrow));
+  }
+  for (j = expdif - 1; j >= 0; j--) {
+    x = in1[j] + borrow;
+    borrow = x < 0 ? -1 : 0;
+    out[j] = (DGTINT)(x + (radix & borrow));
+  }
+  ncancel = 0;
+  for (j = 0; j < n && out[j] == 0; j++) {
+    ncancel = j + 1;
+  }
+  if (ncancel > 0 && ncancel < n) {
+    for (j = 0; j < n - ncancel; j++) {
+      out[j] = out[j + ncancel];
+    }
+    for (j = n - ncancel; j < n; j++) {
+      out[j] = 0;
+    }
+  }
+  return ncancel;
+}
+
+/* -------- mp_imul routines -------- */
+
+void mp_imul(int n, int radix, int in1[], int in2, int out[]) {
+  void mp_unsgn_imul(int n, double dradix, int in1[], double din2, int out[]);
+
+  if (in2 > 0) {
+    out[0] = in1[0];
+  } else if (in2 < 0) {
+    out[0] = -in1[0];
+    in2 = -in2;
+  } else {
+    out[0] = 0;
+  }
+  mp_unsgn_imul(n, radix, &in1[1], in2, &out[1]);
+  if (out[0] == 0) {
+    out[1] = 0;
+  }
+}
+
+int mp_idiv(int n, int radix, int in1[], int in2, int out[]) {
+  void mp_load_0(int n, int radix, int out[]);
+  void mp_unsgn_idiv(int n, double dradix, int in1[], double din2, int out[]);
+
+  if (in2 == 0) {
+    return -1;
+  }
+  if (in2 > 0) {
+    out[0] = in1[0];
+  } else {
+    out[0] = -in1[0];
+    in2 = -in2;
+  }
+  if (in1[0] == 0) {
+    mp_load_0(n, radix, out);
+    return 0;
+  }
+  mp_unsgn_idiv(n, radix, &in1[1], in2, &out[1]);
+  return 0;
+}
+
+void mp_idiv_2(int n, int radix, int in[], int out[]) {
+  int j, ix, carry, shift;
+  DGTINT *inr, *outr;
+
+  inr = ((DGTINT *)&in[2]) - 2;
+  outr = ((DGTINT *)&out[2]) - 2;
+  out[0] = in[0];
+  shift = 0;
+  if (inr[2] == 1) {
+    shift = 1;
+  }
+  out[1] = in[1] - shift;
+  carry = -shift;
+  for (j = 2; j <= n + 1 - shift; j++) {
+    ix = inr[j + shift] + (radix & carry);
+    carry = -(ix & 1);
+    outr[j] = (DGTINT)(ix >> 1);
+  }
+  if (shift > 0) {
+    outr[n + 1] = (DGTINT)((radix & carry) >> 1);
+  }
+}
+
+/* -------- mp_imul child routines -------- */
+
+void mp_unsgn_imul(int n, double dradix, int in1[], double din2, int out[]) {
+  int j, carry, shift;
+  double x, d1_radix;
+  DGTINT *in1r, *outr;
+
+  in1r = ((DGTINT *)&in1[1]) - 1;
+  outr = ((DGTINT *)&out[1]) - 1;
+  d1_radix = 1.0 / dradix;
+  carry = 0;
+  for (j = n; j >= 1; j--) {
+    x = din2 * in1r[j] + carry + 0.5;
+    carry = (int)(d1_radix * x);
+    outr[j] = (DGTINT)(x - dradix * carry);
+  }
+  shift = 0;
+  x = carry + 0.5;
+  while (x > 1) {
+    x *= d1_radix;
+    shift++;
+  }
+  out[0] = in1[0] + shift;
+  if (shift > 0) {
+    while (shift > n) {
+      carry = (int)(d1_radix * carry + 0.5);
+      shift--;
+    }
+    for (j = n; j >= shift + 1; j--) {
+      outr[j] = outr[j - shift];
+    }
+    for (j = shift; j >= 1; j--) {
+      x = carry + 0.5;
+      carry = (int)(d1_radix * x);
+      outr[j] = (DGTINT)(x - dradix * carry);
+    }
+  }
+}
+
+void mp_unsgn_idiv(int n, double dradix, int in1[], double din2, int out[]) {
+  int j, ix, carry, shift;
+  double x, d1_in2;
+  DGTINT *in1r, *outr;
+
+  in1r = ((DGTINT *)&in1[1]) - 1;
+  outr = ((DGTINT *)&out[1]) - 1;
+  d1_in2 = 1.0 / din2;
+  shift = 0;
+  x = 0;
+  do {
+    shift++;
+    x *= dradix;
+    if (shift <= n) {
+      x += in1r[shift];
+    }
+  } while (x < din2 - 0.5);
+  x += 0.5;
+  ix = (int)(d1_in2 * x);
+  carry = (int)(x - din2 * ix);
+  outr[1] = (DGTINT)ix;
+  shift--;
+  out[0] = in1[0] - shift;
+  if (shift >= n) {
+    shift = n - 1;
+  }
+  for (j = 2; j <= n - shift; j++) {
+    x = in1r[j + shift] + dradix * carry + 0.5;
+    ix = (int)(d1_in2 * x);
+    carry = (int)(x - din2 * ix);
+    outr[j] = (DGTINT)ix;
+  }
+  for (j = n - shift + 1; j <= n; j++) {
+    x = dradix * carry + 0.5;
+    ix = (int)(d1_in2 * x);
+    carry = (int)(x - din2 * ix);
+    outr[j] = (DGTINT)ix;
+  }
+}
+
+/* -------- mp_mul routines -------- */
+
+double mp_mul_radix_test(int n, int radix, int nfft, double tmpfft[]) {
+  void mp_mul_csqu(int nfft, double d1[]);
+  double mp_mul_d2i_test(int radix, int nfft, double din[]);
+  int j, ndata, radix_2;
+
+  ndata = (nfft >> 1) + 1;
+  if (ndata > n) {
+    ndata = n;
+  }
+  tmpfft[nfft + 1] = radix - 1;
+  for (j = nfft; j > ndata; j--) {
+    tmpfft[j] = 0;
+  }
+  radix_2 = (radix + 1) / 2;
+  for (j = ndata; j > 2; j--) {
+    tmpfft[j] = radix_2;
+  }
+  tmpfft[2] = radix;
+  tmpfft[1] = radix - 1;
+  tmpfft[0] = 0;
+  mp_mul_csqu(nfft, tmpfft);
+  return 2 * mp_mul_d2i_test(radix, nfft, tmpfft);
+}
+
+void mp_mul(int n, int radix, int in1[], int in2[], int out[], int tmp[], int nfft, double tmp1fft[], double tmp2fft[], double tmp3fft[]) {
+  void mp_add(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]);
+  void mp_mul_cmul_nt_out(int nfft, double d1[], double d2[]);
+  void mp_mul_cmul_nt_d2(int nfft, double d1[], double d2[]);
+  void mp_mul_cmul_nt_d1_add(int nfft, double d1[], double d2[], double d3[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+  int n_h, shift;
+  DGTINT *in1r, *in2r;
+
+  in1r = ((DGTINT *)&in1[2]) - 2;
+  in2r = ((DGTINT *)&in2[2]) - 2;
+  shift = (nfft >> 1) + 1;
+  while (n > shift) {
+    if (in1r[shift + 2] + in2r[shift + 2] != 0) {
+      break;
+    }
+    shift++;
+  }
+  n_h = n / 2 + 1;
+  if (n_h < n - shift) {
+    n_h = n - shift;
+  }
+  /* ---- tmp3fft = (upper) in1 * (lower) in2 ---- */
+  mp_mul_i2d(n, radix, nfft, 0, in1, tmp1fft);
+  mp_mul_i2d(n, radix, nfft, shift, in2, tmp3fft);
+  mp_mul_cmul_nt_out(nfft, tmp1fft, tmp3fft);
+  /* ---- tmp = (upper) in1 * (upper) in2 ---- */
+  mp_mul_i2d(n, radix, nfft, 0, in2, tmp2fft);
+  mp_mul_cmul_nt_d2(nfft, tmp2fft, tmp1fft);
+  mp_mul_d2i(n, radix, nfft, tmp1fft, tmp);
+  /* ---- tmp3fft += (upper) in2 * (lower) in1 ---- */
+  mp_mul_i2d(n, radix, nfft, shift, in1, tmp1fft);
+  mp_mul_cmul_nt_d1_add(nfft, tmp2fft, tmp1fft, tmp3fft);
+  /* ---- out = tmp + tmp3fft ---- */
+  mp_mul_d2i(n_h, radix, nfft, tmp3fft, out);
+  mp_add(n, radix, out, tmp, out);
+}
+
+void mp_squ(int n, int radix, int in[], int out[], int tmp[], int nfft, double tmp1fft[], double tmp2fft[]) {
+  void mp_add(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]);
+  void mp_mul_cmul(int nfft, double d1[], double d2[]);
+  void mp_mul_csqu_nt_d1(int nfft, double d1[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+  int n_h, shift;
+  DGTINT *inr;
+
+  inr = ((DGTINT *)&in[2]) - 2;
+  shift = (nfft >> 1) + 1;
+  while (n > shift) {
+    if (inr[shift + 2] != 0) {
+      break;
+    }
+    shift++;
+  }
+  n_h = n / 2 + 1;
+  if (n_h < n - shift) {
+    n_h = n - shift;
+  }
+  /* ---- tmp = 2 * (upper) in * (lower) in ---- */
+  mp_mul_i2d(n, radix, nfft, 0, in, tmp1fft);
+  mp_mul_i2d(n, radix, nfft, shift, in, tmp2fft);
+  mp_mul_cmul(nfft, tmp1fft, tmp2fft);
+  mp_mul_d2i(n_h, radix, nfft, tmp2fft, tmp);
+  mp_add(n_h, radix, tmp, tmp, tmp);
+  /* ---- out = tmp + ((upper) in)^2 ---- */
+  mp_mul_csqu_nt_d1(nfft, tmp1fft);
+  mp_mul_d2i(n, radix, nfft, tmp1fft, out);
+  mp_add(n, radix, out, tmp, out);
+}
+
+void mp_mulhf(int n, int radix, int in1[], int in2[], int out[], int tmp[], int nfft, double in1fft[], double tmpfft[]) {
+  void mp_add(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]);
+  void mp_mul_cmul(int nfft, double d1[], double d2[]);
+  void mp_mul_cmul_nt_d1(int nfft, double d1[], double d2[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+  int n_h, shift;
+  DGTINT *in2r;
+
+  in2r = ((DGTINT *)&in2[2]) - 2;
+  shift = (nfft >> 1) + 1;
+  while (n > shift) {
+    if (in2r[shift + 2] != 0) {
+      break;
+    }
+    shift++;
+  }
+  n_h = n / 2 + 1;
+  if (n_h < n - shift) {
+    n_h = n - shift;
+  }
+  /* ---- tmp = (upper) in1 * (upper) in2 ---- */
+  mp_mul_i2d(n, radix, nfft, 0, in1, in1fft);
+  mp_mul_i2d(n, radix, nfft, 0, in2, tmpfft);
+  mp_mul_cmul(nfft, in1fft, tmpfft);
+  mp_mul_d2i(n, radix, nfft, tmpfft, tmp);
+  /* ---- out = tmp + (upper) in1 * (lower) in2 ---- */
+  mp_mul_i2d(n, radix, nfft, shift, in2, tmpfft);
+  mp_mul_cmul_nt_d1(nfft, in1fft, tmpfft);
+  mp_mul_d2i(n_h, radix, nfft, tmpfft, out);
+  mp_add(n, radix, out, tmp, out);
+}
+
+void mp_mulhf_use_in1fft(int n, int radix, double in1fft[], int in2[], int out[], int tmp[], int nfft, double tmpfft[]) {
+  void mp_add(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]);
+  void mp_mul_cmul_nt_d1(int nfft, double d1[], double d2[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+  int n_h, shift;
+  DGTINT *in2r;
+
+  in2r = ((DGTINT *)&in2[2]) - 2;
+  shift = (nfft >> 1) + 1;
+  while (n > shift) {
+    if (in2r[shift + 2] != 0) {
+      break;
+    }
+    shift++;
+  }
+  n_h = n / 2 + 1;
+  if (n_h < n - shift) {
+    n_h = n - shift;
+  }
+  /* ---- tmp = (upper) in1fft * (upper) in2 ---- */
+  mp_mul_i2d(n, radix, nfft, 0, in2, tmpfft);
+  mp_mul_cmul_nt_d1(nfft, in1fft, tmpfft);
+  mp_mul_d2i(n, radix, nfft, tmpfft, tmp);
+  /* ---- out = tmp + (upper) in1 * (lower) in2 ---- */
+  mp_mul_i2d(n, radix, nfft, shift, in2, tmpfft);
+  mp_mul_cmul_nt_d1(nfft, in1fft, tmpfft);
+  mp_mul_d2i(n_h, radix, nfft, tmpfft, out);
+  mp_add(n, radix, out, tmp, out);
+}
+
+void mp_squhf_use_infft(int n, int radix, double infft[], int in[], int out[], int tmp[], int nfft, double tmpfft[]) {
+  void mp_add(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]);
+  void mp_mul_cmul_nt_d1(int nfft, double d1[], double d2[]);
+  void mp_mul_csqu_nt_d1(int nfft, double d1[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+  int n_h, shift;
+  DGTINT *inr;
+
+  inr = ((DGTINT *)&in[2]) - 2;
+  shift = (nfft >> 1) + 1;
+  while (n > shift) {
+    if (inr[shift + 2] != 0) {
+      break;
+    }
+    shift++;
+  }
+  n_h = n / 2 + 1;
+  if (n_h < n - shift) {
+    n_h = n - shift;
+  }
+  /* ---- tmp = (upper) infft * (lower) in ---- */
+  mp_mul_i2d(n, radix, nfft, shift, in, tmpfft);
+  mp_mul_cmul_nt_d1(nfft, infft, tmpfft);
+  mp_mul_d2i(n_h, radix, nfft, tmpfft, tmp);
+  /* ---- out = tmp + ((upper) infft)^2 ---- */
+  mp_mul_csqu_nt_d1(nfft, infft);
+  mp_mul_d2i(n, radix, nfft, infft, out);
+  mp_add(n, radix, out, tmp, out);
+}
+
+void mp_mulh(int n, int radix, int in1[], int in2[], int out[], int nfft, double in1fft[], double outfft[]) {
+  void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]);
+  void mp_mul_cmul(int nfft, double d1[], double d2[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+
+  mp_mul_i2d(n, radix, nfft, 0, in1, in1fft);
+  mp_mul_i2d(n, radix, nfft, 0, in2, outfft);
+  mp_mul_cmul(nfft, in1fft, outfft);
+  mp_mul_d2i(n, radix, nfft, outfft, out);
+}
+
+void mp_mulh_use_in1fft(int n, int radix, double in1fft[], int shift, int in2[], int out[], int nfft, double outfft[]) {
+  void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]);
+  void mp_mul_cmul_nt_d1(int nfft, double d1[], double d2[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+  DGTINT *in2r;
+
+  in2r = ((DGTINT *)&in2[2]) - 2;
+  while (n > shift) {
+    if (in2r[shift + 2] != 0) {
+      break;
+    }
+    shift++;
+  }
+  mp_mul_i2d(n, radix, nfft, shift, in2, outfft);
+  mp_mul_cmul_nt_d1(nfft, in1fft, outfft);
+  mp_mul_d2i(n, radix, nfft, outfft, out);
+}
+
+void mp_squh(int n, int radix, int in[], int out[], int nfft, double outfft[]) {
+  void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]);
+  void mp_mul_csqu(int nfft, double d1[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+
+  mp_mul_i2d(n, radix, nfft, 0, in, outfft);
+  mp_mul_csqu(nfft, outfft);
+  mp_mul_d2i(n, radix, nfft, outfft, out);
+}
+
+void mp_squh_save_infft(int n, int radix, int in[], int out[], int nfft, double infft[], double outfft[]) {
+  void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]);
+  void mp_mul_csqu_save_d1(int nfft, double d1[], double d2[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+
+  mp_mul_i2d(n, radix, nfft, 0, in, infft);
+  mp_mul_csqu_save_d1(nfft, infft, outfft);
+  mp_mul_d2i(n, radix, nfft, outfft, out);
+}
+
+void mp_squh_use_in1fft(int n, int radix, double inoutfft[], int out[], int nfft) {
+  void mp_mul_csqu_nt_d1(int nfft, double d1[]);
+  void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]);
+
+  mp_mul_csqu_nt_d1(nfft, inoutfft);
+  mp_mul_d2i(n, radix, nfft, inoutfft, out);
+}
+
+/* -------- mp_mul child routines -------- */
+
+void mp_mul_i2d(int n, int radix, int nfft, int shift, int in[], double dout[]) {
+  int j, x, carry, ndata, radix_2, topdgt;
+  DGTINT *inr;
+
+  inr = ((DGTINT *)&in[2]) - 2;
+  ndata = 0;
+  topdgt = 0;
+  if (n > shift) {
+    topdgt = inr[shift + 2];
+    ndata = (nfft >> 1) + 1;
+    if (ndata > n - shift) {
+      ndata = n - shift;
+    }
+  }
+  dout[nfft + 1] = in[0] * topdgt;
+  for (j = nfft; j > ndata; j--) {
+    dout[j] = 0;
+  }
+  /* ---- abs(dout[j]) <= radix/2 (to keep FFT precision) ---- */
+  if (ndata > 1) {
+    radix_2 = radix / 2;
+    carry = 0;
+    for (j = ndata + 1; j > 3; j--) {
+      x = inr[j + shift] - carry;
+      carry = x >= radix_2 ? -1 : 0;
+      dout[j - 1] = x - (radix & carry);
+    }
+    dout[2] = inr[shift + 3] - carry;
+  }
+  dout[1] = topdgt;
+  dout[0] = in[1] - shift;
+}
+
+void mp_mul_cmul(int nfft, double d1[], double d2[]) {
+  void cdft(int n, int isgn, double *a);
+  void mp_mul_rcmul(int n, double *a, double *b);
+  double xr, xi;
+
+  cdft(nfft, 1, &d1[1]);
+  cdft(nfft, 1, &d2[1]);
+  d2[0] += d1[0];
+  xr = d1[1] * d2[1] + d1[2] * d2[2];
+  xi = d1[1] * d2[2] + d1[2] * d2[1];
+  d2[1] = xr;
+  d2[2] = xi;
+  if (nfft > 2) {
+    mp_mul_rcmul(nfft, &d1[1], &d2[1]);
+  }
+  d2[nfft + 1] *= d1[nfft + 1];
+  cdft(nfft, -1, &d2[1]);
+}
+
+void mp_mul_cmul_nt_d1(int nfft, double d1[], double d2[]) {
+  void cdft(int n, int isgn, double *a);
+  void mp_mul_rcmul_nt_in1(int n, double *a, double *b);
+  double xr, xi;
+
+  cdft(nfft, 1, &d2[1]);
+  d2[0] += d1[0];
+  xr = d1[1] * d2[1] + d1[2] * d2[2];
+  xi = d1[1] * d2[2] + d1[2] * d2[1];
+  d2[1] = xr;
+  d2[2] = xi;
+  if (nfft > 2) {
+    mp_mul_rcmul_nt_in1(nfft, &d1[1], &d2[1]);
+  }
+  d2[nfft + 1] *= d1[nfft + 1];
+  cdft(nfft, -1, &d2[1]);
+}
+
+void mp_mul_cmul_nt_d2(int nfft, double d1[], double d2[]) {
+  void cdft(int n, int isgn, double *a);
+  void mp_mul_rcmul_nt_in2(int n, double *a, double *b);
+  double xr, xi;
+
+  cdft(nfft, 1, &d1[1]);
+  d2[0] += d1[0];
+  xr = d1[1] * d2[1] + d1[2] * d2[2];
+  xi = d1[1] * d2[2] + d1[2] * d2[1];
+  d2[1] = xr;
+  d2[2] = xi;
+  if (nfft > 2) {
+    mp_mul_rcmul_nt_in2(nfft, &d1[1], &d2[1]);
+  }
+  d2[nfft + 1] *= d1[nfft + 1];
+  cdft(nfft, -1, &d2[1]);
+}
+
+void mp_mul_cmul_nt_out(int nfft, double d1[], double d2[]) {
+  void cdft(int n, int isgn, double *a);
+  void mp_mul_rcmul_nt_out(int n, double *a, double *b);
+  double xr, xi;
+
+  cdft(nfft, 1, &d1[1]);
+  cdft(nfft, 1, &d2[1]);
+  d2[0] += d1[0];
+  xr = d1[1] * d2[1] + d1[2] * d2[2];
+  xi = d1[1] * d2[2] + d1[2] * d2[1];
+  d2[1] = xr;
+  d2[2] = xi;
+  if (nfft > 2) {
+    mp_mul_rcmul_nt_out(nfft, &d1[1], &d2[1]);
+  }
+  d2[nfft + 1] *= d1[nfft + 1];
+}
+
+void mp_mul_cmul_nt_d1_add(int nfft, double d1[], double d2[], double d3[]) {
+  void cdft(int n, int isgn, double *a);
+  void mp_mul_rcmul_nt_in1_add(int n, double *a, double *b, double *badd);
+  double xr, xi;
+
+  cdft(nfft, 1, &d2[1]);
+  xr = d1[1] * d2[1] + d1[2] * d2[2];
+  xi = d1[1] * d2[2] + d1[2] * d2[1];
+  d3[1] += xr;
+  d3[2] += xi;
+  if (nfft > 2) {
+    mp_mul_rcmul_nt_in1_add(nfft, &d1[1], &d2[1], &d3[1]);
+  }
+  d3[nfft + 1] += d1[nfft + 1] * d2[nfft + 1];
+  cdft(nfft, -1, &d3[1]);
+}
+
+void mp_mul_csqu(int nfft, double d1[]) {
+  void cdft(int n, int isgn, double *a);
+  void mp_mul_rcsqu(int n, double *a);
+  double xr, xi;
+
+  cdft(nfft, 1, &d1[1]);
+  d1[0] *= 2;
+  xr = d1[1] * d1[1] + d1[2] * d1[2];
+  xi = 2 * d1[1] * d1[2];
+  d1[1] = xr;
+  d1[2] = xi;
+  if (nfft > 2) {
+    mp_mul_rcsqu(nfft, &d1[1]);
+  }
+  d1[nfft + 1] *= d1[nfft + 1];
+  cdft(nfft, -1, &d1[1]);
+}
+
+void mp_mul_csqu_save_d1(int nfft, double d1[], double d2[]) {
+  void cdft(int n, int isgn, double *a);
+  void mp_mul_rcsqu_save(int n, double *a, double *b);
+  double xr, xi;
+
+  cdft(nfft, 1, &d1[1]);
+  d2[0] = 2 * d1[0];
+  xr = d1[1] * d1[1] + d1[2] * d1[2];
+  xi = 2 * d1[1] * d1[2];
+  d2[1] = xr;
+  d2[2] = xi;
+  if (nfft > 2) {
+    mp_mul_rcsqu_save(nfft, &d1[1], &d2[1]);
+  }
+  d2[nfft + 1] = d1[nfft + 1] * d1[nfft + 1];
+  cdft(nfft, -1, &d2[1]);
+}
+
+void mp_mul_csqu_nt_d1(int nfft, double d1[]) {
+  void cdft(int n, int isgn, double *a);
+  void mp_mul_rcsqu_nt_in(int n, double *a);
+  double xr, xi;
+
+  d1[0] *= 2;
+  xr = d1[1] * d1[1] + d1[2] * d1[2];
+  xi = 2 * d1[1] * d1[2];
+  d1[1] = xr;
+  d1[2] = xi;
+  if (nfft > 2) {
+    mp_mul_rcsqu_nt_in(nfft, &d1[1]);
+  }
+  d1[nfft + 1] *= d1[nfft + 1];
+  cdft(nfft, -1, &d1[1]);
+}
+
+void mp_mul_d2i(int n, int radix, int nfft, double din[], int out[]) {
+  int j, carry, carry1, carry2, shift, ndata;
+  double x, scale, d1_radix, d1_radix2, pow_radix, topdgt;
+  DGTINT *outr;
+
+  outr = ((DGTINT *)&out[2]) - 2;
+  scale = 2.0 / nfft;
+  d1_radix = 1.0 / radix;
+  d1_radix2 = d1_radix * d1_radix;
+  topdgt = din[nfft + 1];
+  x = topdgt < 0 ? -topdgt : topdgt;
+  shift = x + 0.5 >= radix ? 1 : 0;
+  /* ---- correction of cyclic convolution of din[1] ---- */
+  x *= nfft * 0.5;
+  din[nfft + 1] = din[1] - x;
+  din[1] = x;
+  /* ---- output of digits ---- */
+  ndata = n;
+  if (n > nfft + 1 + shift) {
+    ndata = nfft + 1 + shift;
+    for (j = n + 1; j > ndata + 1; j--) {
+      outr[j] = 0;
+    }
+  }
+  x = 0;
+  pow_radix = 1;
+  for (j = ndata + 1 - shift; j <= nfft + 1; j++) {
+    x += pow_radix * din[j];
+    pow_radix *= d1_radix;
+    if (pow_radix < DBL_EPSILON) {
+      break;
+    }
+  }
+  x = d1_radix2 * (scale * x + 0.5);
+  carry2 = ((int)x) - 1;
+  carry = (int)(radix * (x - carry2) + 0.5);
+  for (j = ndata; j > 1; j--) {
+    x = d1_radix2 * (scale * din[j - shift] + carry + 0.5);
+    carry = carry2;
+    carry2 = ((int)x) - 1;
+    x = radix * (x - carry2);
+    carry1 = (int)x;
+    outr[j + 1] = (DGTINT)(radix * (x - carry1));
+    carry += carry1;
+  }
+  x = carry + ((double)radix) * carry2 + 0.5;
+  if (shift == 0) {
+    x += scale * din[1];
+  }
+  carry = (int)(d1_radix * x);
+  outr[2] = (DGTINT)(x - ((double)radix) * carry);
+  if (carry > 0) {
+    for (j = n + 1; j > 2; j--) {
+      outr[j] = outr[j - 1];
+    }
+    outr[2] = (DGTINT)carry;
+    shift++;
+  }
+  /* ---- output of exp, sgn ---- */
+  x = din[0] + shift + 0.5;
+  shift = ((int)x) - 1;
+  out[1] = shift + ((int)(x - shift));
+  out[0] = topdgt > 0.5 ? 1 : -1;
+  if (outr[2] == 0) {
+    out[0] = 0;
+    out[1] = 0;
+  }
+}
+
+double mp_mul_d2i_test(int radix, int nfft, double din[]) {
+  int j, carry, carry1, carry2;
+  double x, scale, d1_radix, d1_radix2, err;
+
+  scale = 2.0 / nfft;
+  d1_radix = 1.0 / radix;
+  d1_radix2 = d1_radix * d1_radix;
+  /* ---- correction of cyclic convolution of din[1] ---- */
+  x = din[nfft + 1] * nfft * 0.5;
+  if (x < 0) {
+    x = -x;
+  }
+  din[nfft + 1] = din[1] - x;
+  /* ---- check of digits ---- */
+  err = 0;
+  carry = 0;
+  carry2 = 0;
+  for (j = nfft + 1; j > 1; j--) {
+    x = d1_radix2 * (scale * din[j] + carry + 0.5);
+    carry = carry2;
+    carry2 = ((int)x) - 1;
+    x = radix * (x - carry2);
+    carry1 = (int)x;
+    x = radix * (x - carry1);
+    carry += carry1;
+    x = x - 0.5 - ((int)x);
+    if (x > err) {
+      err = x;
+    } else if (-x > err) {
+      err = -x;
+    }
+  }
+  return err;
+}
+
+/* -------- mp_mul child^2 routines (mix RFFT routines) -------- */
+
+#ifndef M_PI_2
+#define M_PI_2 1.570796326794896619231321691639751442098584699687
+#endif
+
+#ifndef RDFT_LOOP_DIV /* control of the RDFT's speed & tolerance */
+#define RDFT_LOOP_DIV 64
+#endif
+
+void mp_mul_rcmul(int n, double *a, double *b) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss;
+  double xr, xi, yr, yi, ajr, aji, akr, aki, bjr, bji, bkr, bki;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  xr = a[i];
+  xi = a[i + 1];
+  yr = b[i];
+  yi = b[i + 1];
+  b[i] = xr * yr - xi * yi;
+  b[i + 1] = xr * yi + xi * yr;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 2) {
+      i0 = 2;
+    }
+    for (j = i - 2; j >= i0; j -= 2) {
+      k = n - j;
+      xr = wkr + ss * wdi;
+      xi = wki + ss * (0.5 - wdr);
+      wkr = wdr;
+      wki = wdi;
+      wdr = xr;
+      wdi = xi;
+      /* ---- transform CFFT data a[] into RFFT data ---- */
+      xr = a[j] - a[k];
+      xi = a[j + 1] + a[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      ajr = a[j] - yr;
+      aji = a[j + 1] - yi;
+      akr = a[k] + yr;
+      aki = a[k + 1] - yi;
+      a[j] = ajr;
+      a[j + 1] = aji;
+      a[k] = akr;
+      a[k + 1] = aki;
+      /* ---- transform CFFT data b[] into RFFT data ---- */
+      xr = b[j] - b[k];
+      xi = b[j + 1] + b[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      xr = b[j] - yr;
+      xi = b[j + 1] - yi;
+      yr = b[k] + yr;
+      yi = b[k + 1] - yi;
+      /* ---- cmul ---- */
+      bjr = ajr * xr - aji * xi;
+      bji = ajr * xi + aji * xr;
+      bkr = akr * yr - aki * yi;
+      bki = akr * yi + aki * yr;
+      /* ---- transform RFFT data bxx into CFFT data ---- */
+      xr = bjr - bkr;
+      xi = bji + bki;
+      yr = wkr * xr + wki * xi;
+      yi = wkr * xi - wki * xr;
+      b[j] = bjr - yr;
+      b[j + 1] = bji - yi;
+      b[k] = bkr + yr;
+      b[k + 1] = bki - yi;
+    }
+    if (i0 == 2) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+}
+
+void mp_mul_rcmul_nt_in1(int n, double *a, double *b) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss;
+  double xr, xi, yr, yi, bjr, bji, bkr, bki;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  xr = a[i];
+  xi = a[i + 1];
+  yr = b[i];
+  yi = b[i + 1];
+  b[i] = xr * yr - xi * yi;
+  b[i + 1] = xr * yi + xi * yr;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 2) {
+      i0 = 2;
+    }
+    for (j = i - 2; j >= i0; j -= 2) {
+      k = n - j;
+      xr = wkr + ss * wdi;
+      xi = wki + ss * (0.5 - wdr);
+      wkr = wdr;
+      wki = wdi;
+      wdr = xr;
+      wdi = xi;
+      /* ---- transform CFFT data b[] into RFFT data ---- */
+      xr = b[j] - b[k];
+      xi = b[j + 1] + b[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      xr = b[j] - yr;
+      xi = b[j + 1] - yi;
+      yr = b[k] + yr;
+      yi = b[k + 1] - yi;
+      /* ---- cmul ---- */
+      bjr = a[j] * xr - a[j + 1] * xi;
+      bji = a[j] * xi + a[j + 1] * xr;
+      bkr = a[k] * yr - a[k + 1] * yi;
+      bki = a[k] * yi + a[k + 1] * yr;
+      /* ---- transform RFFT data bxx into CFFT data ---- */
+      xr = bjr - bkr;
+      xi = bji + bki;
+      yr = wkr * xr + wki * xi;
+      yi = wkr * xi - wki * xr;
+      b[j] = bjr - yr;
+      b[j + 1] = bji - yi;
+      b[k] = bkr + yr;
+      b[k + 1] = bki - yi;
+    }
+    if (i0 == 2) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+}
+
+void mp_mul_rcmul_nt_in2(int n, double *a, double *b) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss;
+  double xr, xi, yr, yi, bjr, bji, bkr, bki;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  xr = a[i];
+  xi = a[i + 1];
+  yr = b[i];
+  yi = b[i + 1];
+  b[i] = xr * yr - xi * yi;
+  b[i + 1] = xr * yi + xi * yr;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 2) {
+      i0 = 2;
+    }
+    for (j = i - 2; j >= i0; j -= 2) {
+      k = n - j;
+      xr = wkr + ss * wdi;
+      xi = wki + ss * (0.5 - wdr);
+      wkr = wdr;
+      wki = wdi;
+      wdr = xr;
+      wdi = xi;
+      /* ---- transform CFFT data a[] into RFFT data ---- */
+      xr = a[j] - a[k];
+      xi = a[j + 1] + a[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      xr = a[j] - yr;
+      xi = a[j + 1] - yi;
+      yr = a[k] + yr;
+      yi = a[k + 1] - yi;
+      a[j] = xr;
+      a[j + 1] = xi;
+      a[k] = yr;
+      a[k + 1] = yi;
+      /* ---- cmul ---- */
+      bjr = b[j] * xr - b[j + 1] * xi;
+      bji = b[j] * xi + b[j + 1] * xr;
+      bkr = b[k] * yr - b[k + 1] * yi;
+      bki = b[k] * yi + b[k + 1] * yr;
+      /* ---- transform RFFT data bxx into CFFT data ---- */
+      xr = bjr - bkr;
+      xi = bji + bki;
+      yr = wkr * xr + wki * xi;
+      yi = wkr * xi - wki * xr;
+      b[j] = bjr - yr;
+      b[j + 1] = bji - yi;
+      b[k] = bkr + yr;
+      b[k + 1] = bki - yi;
+    }
+    if (i0 == 2) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+}
+
+void mp_mul_rcmul_nt_out(int n, double *a, double *b) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss;
+  double xr, xi, yr, yi, ajr, aji, akr, aki;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  xr = a[i];
+  xi = a[i + 1];
+  yr = b[i];
+  yi = b[i + 1];
+  b[i] = xr * yr - xi * yi;
+  b[i + 1] = xr * yi + xi * yr;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 2) {
+      i0 = 2;
+    }
+    for (j = i - 2; j >= i0; j -= 2) {
+      k = n - j;
+      xr = wkr + ss * wdi;
+      xi = wki + ss * (0.5 - wdr);
+      wkr = wdr;
+      wki = wdi;
+      wdr = xr;
+      wdi = xi;
+      /* ---- transform CFFT data a[] into RFFT data ---- */
+      xr = a[j] - a[k];
+      xi = a[j + 1] + a[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      ajr = a[j] - yr;
+      aji = a[j + 1] - yi;
+      akr = a[k] + yr;
+      aki = a[k + 1] - yi;
+      a[j] = ajr;
+      a[j + 1] = aji;
+      a[k] = akr;
+      a[k + 1] = aki;
+      /* ---- transform CFFT data b[] into RFFT data ---- */
+      xr = b[j] - b[k];
+      xi = b[j + 1] + b[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      xr = b[j] - yr;
+      xi = b[j + 1] - yi;
+      yr = b[k] + yr;
+      yi = b[k + 1] - yi;
+      /* ---- cmul ---- */
+      b[j] = ajr * xr - aji * xi;
+      b[j + 1] = ajr * xi + aji * xr;
+      b[k] = akr * yr - aki * yi;
+      b[k + 1] = akr * yi + aki * yr;
+    }
+    if (i0 == 2) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+}
+
+void mp_mul_rcmul_nt_in1_add(int n, double *a, double *b, double *badd) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss;
+  double xr, xi, yr, yi, bjr, bji, bkr, bki;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  xr = a[i];
+  xi = a[i + 1];
+  yr = b[i];
+  yi = b[i + 1];
+  badd[i] += xr * yr - xi * yi;
+  badd[i + 1] += xr * yi + xi * yr;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 2) {
+      i0 = 2;
+    }
+    for (j = i - 2; j >= i0; j -= 2) {
+      k = n - j;
+      xr = wkr + ss * wdi;
+      xi = wki + ss * (0.5 - wdr);
+      wkr = wdr;
+      wki = wdi;
+      wdr = xr;
+      wdi = xi;
+      /* ---- transform CFFT data b[] into RFFT data ---- */
+      xr = b[j] - b[k];
+      xi = b[j + 1] + b[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      xr = b[j] - yr;
+      xi = b[j + 1] - yi;
+      yr = b[k] + yr;
+      yi = b[k + 1] - yi;
+      /* ---- cmul + add ---- */
+      bjr = badd[j] + (a[j] * xr - a[j + 1] * xi);
+      bji = badd[j + 1] + (a[j] * xi + a[j + 1] * xr);
+      bkr = badd[k] + (a[k] * yr - a[k + 1] * yi);
+      bki = badd[k + 1] + (a[k] * yi + a[k + 1] * yr);
+      /* ---- transform RFFT data bxx into CFFT data ---- */
+      xr = bjr - bkr;
+      xi = bji + bki;
+      yr = wkr * xr + wki * xi;
+      yi = wkr * xi - wki * xr;
+      badd[j] = bjr - yr;
+      badd[j + 1] = bji - yi;
+      badd[k] = bkr + yr;
+      badd[k + 1] = bki - yi;
+    }
+    if (i0 == 2) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+}
+
+void mp_mul_rcsqu(int n, double *a) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss;
+  double xr, xi, yr, yi, ajr, aji, akr, aki;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  xr = a[i];
+  xi = a[i + 1];
+  a[i] = xr * xr - xi * xi;
+  a[i + 1] = 2 * xr * xi;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 2) {
+      i0 = 2;
+    }
+    for (j = i - 2; j >= i0; j -= 2) {
+      k = n - j;
+      xr = wkr + ss * wdi;
+      xi = wki + ss * (0.5 - wdr);
+      wkr = wdr;
+      wki = wdi;
+      wdr = xr;
+      wdi = xi;
+      /* ---- transform CFFT data a[] into RFFT data ---- */
+      xr = a[j] - a[k];
+      xi = a[j + 1] + a[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      xr = a[j] - yr;
+      xi = a[j + 1] - yi;
+      yr = a[k] + yr;
+      yi = a[k + 1] - yi;
+      /* ---- csqu ---- */
+      ajr = xr * xr - xi * xi;
+      aji = 2 * xr * xi;
+      akr = yr * yr - yi * yi;
+      aki = 2 * yr * yi;
+      /* ---- transform RFFT data axx into CFFT data ---- */
+      xr = ajr - akr;
+      xi = aji + aki;
+      yr = wkr * xr + wki * xi;
+      yi = wkr * xi - wki * xr;
+      a[j] = ajr - yr;
+      a[j + 1] = aji - yi;
+      a[k] = akr + yr;
+      a[k + 1] = aki - yi;
+    }
+    if (i0 == 2) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+}
+
+void mp_mul_rcsqu_save(int n, double *a, double *b) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss;
+  double xr, xi, yr, yi, ajr, aji, akr, aki;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  xr = a[i];
+  xi = a[i + 1];
+  b[i] = xr * xr - xi * xi;
+  b[i + 1] = 2 * xr * xi;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 2) {
+      i0 = 2;
+    }
+    for (j = i - 2; j >= i0; j -= 2) {
+      k = n - j;
+      xr = wkr + ss * wdi;
+      xi = wki + ss * (0.5 - wdr);
+      wkr = wdr;
+      wki = wdi;
+      wdr = xr;
+      wdi = xi;
+      /* ---- transform CFFT data a[] into RFFT data ---- */
+      xr = a[j] - a[k];
+      xi = a[j + 1] + a[k + 1];
+      yr = wkr * xr - wki * xi;
+      yi = wkr * xi + wki * xr;
+      xr = a[j] - yr;
+      xi = a[j + 1] - yi;
+      yr = a[k] + yr;
+      yi = a[k + 1] - yi;
+      a[j] = xr;
+      a[j + 1] = xi;
+      a[k] = yr;
+      a[k + 1] = yi;
+      /* ---- csqu ---- */
+      ajr = xr * xr - xi * xi;
+      aji = 2 * xr * xi;
+      akr = yr * yr - yi * yi;
+      aki = 2 * yr * yi;
+      /* ---- transform RFFT data axx into CFFT data ---- */
+      xr = ajr - akr;
+      xi = aji + aki;
+      yr = wkr * xr + wki * xi;
+      yi = wkr * xi - wki * xr;
+      b[j] = ajr - yr;
+      b[j + 1] = aji - yi;
+      b[k] = akr + yr;
+      b[k + 1] = aki - yi;
+    }
+    if (i0 == 2) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+}
+
+void mp_mul_rcsqu_nt_in(int n, double *a) {
+  int i, i0, j, k;
+  double ec, w1r, w1i, wkr, wki, wdr, wdi, ss;
+  double xr, xi, yr, yi, ajr, aji, akr, aki;
+
+  ec = 2 * M_PI_2 / n;
+  wkr = 0;
+  wki = 0;
+  wdi = cos(ec);
+  wdr = sin(ec);
+  wdi *= wdr;
+  wdr *= wdr;
+  w1r = 1 - 2 * wdr;
+  w1i = 2 * wdi;
+  ss = 2 * w1i;
+  i = n >> 1;
+  xr = a[i];
+  xi = a[i + 1];
+  a[i] = xr * xr - xi * xi;
+  a[i + 1] = 2 * xr * xi;
+  for (;;) {
+    i0 = i - 4 * RDFT_LOOP_DIV;
+    if (i0 < 2) {
+      i0 = 2;
+    }
+    for (j = i - 2; j >= i0; j -= 2) {
+      k = n - j;
+      xr = wkr + ss * wdi;
+      xi = wki + ss * (0.5 - wdr);
+      wkr = wdr;
+      wki = wdi;
+      wdr = xr;
+      wdi = xi;
+      /* ---- csqu ---- */
+      xr = a[j];
+      xi = a[j + 1];
+      yr = a[k];
+      yi = a[k + 1];
+      ajr = xr * xr - xi * xi;
+      aji = 2 * xr * xi;
+      akr = yr * yr - yi * yi;
+      aki = 2 * yr * yi;
+      /* ---- transform RFFT data axx into CFFT data ---- */
+      xr = ajr - akr;
+      xi = aji + aki;
+      yr = wkr * xr + wki * xi;
+      yi = wkr * xi - wki * xr;
+      a[j] = ajr - yr;
+      a[j + 1] = aji - yi;
+      a[k] = akr + yr;
+      a[k + 1] = aki - yi;
+    }
+    if (i0 == 2) {
+      break;
+    }
+    wkr = 0.5 * sin(ec * i0);
+    wki = 0.5 * cos(ec * i0);
+    wdr = 0.5 - (wkr * w1r - wki * w1i);
+    wdi = wkr * w1i + wki * w1r;
+    wkr = 0.5 - wkr;
+    i = i0;
+  }
+}
+
+/* -------- mp_inv routines -------- */
+
+int mp_inv(int n, int radix, int in[], int out[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]) {
+  int mp_get_nfft_init(int radix, int nfft_max);
+  void mp_inv_init(int n, int radix, int in[], int out[]);
+  int mp_inv_newton(int n, int radix, int in[], int inout[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]);
+  int n_nwt, nfft_nwt, thr, prc;
+
+  if (in[0] == 0) {
+    return -1;
+  }
+  nfft_nwt = mp_get_nfft_init(radix, nfft);
+  n_nwt = nfft_nwt + 2;
+  if (n_nwt > n) {
+    n_nwt = n;
+  }
+  mp_inv_init(n_nwt, radix, in, out);
+  thr = 8;
+  do {
+    n_nwt = nfft_nwt + 2;
+    if (n_nwt > n) {
+      n_nwt = n;
+    }
+    prc = mp_inv_newton(n_nwt, radix, in, out, tmp1, tmp2, nfft_nwt, tmp1fft, tmp2fft);
+#ifdef DEBUG
+    printf("n=%d, nfft=%d, prc=%d\n", n_nwt, nfft_nwt, prc);
+#endif
+    if (thr * nfft_nwt >= nfft) {
+      thr = 0;
+      if (2 * prc <= n_nwt - 2) {
+        nfft_nwt >>= 1;
+      }
+    } else {
+      if (3 * prc < n_nwt - 2) {
+        nfft_nwt >>= 1;
+      }
+    }
+    nfft_nwt <<= 1;
+  } while (nfft_nwt <= nfft);
+  return 0;
+}
+
+int mp_sqrt(int n, int radix, int in[], int out[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]) {
+  void mp_load_0(int n, int radix, int out[]);
+  int mp_get_nfft_init(int radix, int nfft_max);
+  void mp_sqrt_init(int n, int radix, int in[], int out[], int out_rev[]);
+  int mp_sqrt_newton(int n, int radix, int in[], int inout[], int inout_rev[], int tmp[], int nfft, double tmp1fft[], double tmp2fft[], int *n_tmp1fft);
+  int n_nwt, nfft_nwt, thr, prc, n_tmp1fft;
+
+  if (in[0] < 0) {
+    return -1;
+  } else if (in[0] == 0) {
+    mp_load_0(n, radix, out);
+    return 0;
+  }
+  nfft_nwt = mp_get_nfft_init(radix, nfft);
+  n_nwt = nfft_nwt + 2;
+  if (n_nwt > n) {
+    n_nwt = n;
+  }
+  mp_sqrt_init(n_nwt, radix, in, out, tmp1);
+  n_tmp1fft = 0;
+  thr = 8;
+  do {
+    n_nwt = nfft_nwt + 2;
+    if (n_nwt > n) {
+      n_nwt = n;
+    }
+    prc = mp_sqrt_newton(n_nwt, radix, in, out, tmp1, tmp2, nfft_nwt, tmp1fft, tmp2fft, &n_tmp1fft);
+#ifdef DEBUG
+    printf("n=%d, nfft=%d, prc=%d\n", n_nwt, nfft_nwt, prc);
+#endif
+    if (thr * nfft_nwt >= nfft) {
+      thr = 0;
+      if (2 * prc <= n_nwt - 2) {
+        nfft_nwt >>= 1;
+      }
+    } else {
+      if (3 * prc < n_nwt - 2) {
+        nfft_nwt >>= 1;
+      }
+    }
+    nfft_nwt <<= 1;
+  } while (nfft_nwt <= nfft);
+  return 0;
+}
+
+int mp_invisqrt(int n, int radix, int in, int out[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]) {
+  int mp_get_nfft_init(int radix, int nfft_max);
+  void mp_invisqrt_init(int n, int radix, int in, int out[]);
+  int mp_invisqrt_newton(int n, int radix, int in, int inout[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]);
+  int n_nwt, nfft_nwt, thr, prc;
+
+  if (in <= 0) {
+    return -1;
+  }
+  nfft_nwt = mp_get_nfft_init(radix, nfft);
+  n_nwt = nfft_nwt + 2;
+  if (n_nwt > n) {
+    n_nwt = n;
+  }
+  mp_invisqrt_init(n_nwt, radix, in, out);
+  thr = 8;
+  do {
+    n_nwt = nfft_nwt + 2;
+    if (n_nwt > n) {
+      n_nwt = n;
+    }
+    prc = mp_invisqrt_newton(n_nwt, radix, in, out, tmp1, tmp2, nfft_nwt, tmp1fft, tmp2fft);
+#ifdef DEBUG
+    printf("n=%d, nfft=%d, prc=%d\n", n_nwt, nfft_nwt, prc);
+#endif
+    if (thr * nfft_nwt >= nfft) {
+      thr = 0;
+      if (2 * prc <= n_nwt - 2) {
+        nfft_nwt >>= 1;
+      }
+    } else {
+      if (3 * prc < n_nwt - 2) {
+        nfft_nwt >>= 1;
+      }
+    }
+    nfft_nwt <<= 1;
+  } while (nfft_nwt <= nfft);
+  return 0;
+}
+
+/* -------- mp_inv child routines -------- */
+
+int mp_get_nfft_init(int radix, int nfft_max) {
+  int nfft_init;
+  double r;
+
+  r = radix;
+  nfft_init = 1;
+  do {
+    r *= r;
+    nfft_init <<= 1;
+  } while (DBL_EPSILON * r < 1 && nfft_init < nfft_max);
+  return nfft_init;
+}
+
+void mp_inv_init(int n, int radix, int in[], int out[]) {
+  void mp_unexp_d2mp(int n, int radix, double din, DGTINT out[]);
+  double mp_unexp_mp2d(int n, int radix, DGTINT in[]);
+  int outexp;
+  double din;
+
+  out[0] = in[0];
+  outexp = -in[1];
+  din = 1.0 / mp_unexp_mp2d(n, radix, (DGTINT *)&in[2]);
+  while (din < 1) {
+    din *= radix;
+    outexp--;
+  }
+  out[1] = outexp;
+  mp_unexp_d2mp(n, radix, din, (DGTINT *)&out[2]);
+}
+
+void mp_sqrt_init(int n, int radix, int in[], int out[], int out_rev[]) {
+  void mp_unexp_d2mp(int n, int radix, double din, DGTINT out[]);
+  double mp_unexp_mp2d(int n, int radix, DGTINT in[]);
+  int outexp;
+  double din;
+
+  out[0] = 1;
+  out_rev[0] = 1;
+  outexp = in[1];
+  din = mp_unexp_mp2d(n, radix, (DGTINT *)&in[2]);
+  if (outexp % 2 != 0) {
+    din *= radix;
+    outexp--;
+  }
+  outexp /= 2;
+  din = sqrt(din);
+  if (din < 1) {
+    din *= radix;
+    outexp--;
+  }
+  out[1] = outexp;
+  mp_unexp_d2mp(n, radix, din, (DGTINT *)&out[2]);
+  outexp = -outexp;
+  din = 1.0 / din;
+  while (din < 1) {
+    din *= radix;
+    outexp--;
+  }
+  out_rev[1] = outexp;
+  mp_unexp_d2mp(n, radix, din, (DGTINT *)&out_rev[2]);
+}
+
+void mp_invisqrt_init(int n, int radix, int in, int out[]) {
+  void mp_unexp_d2mp(int n, int radix, double din, DGTINT out[]);
+  int outexp;
+  double dout;
+
+  out[0] = 1;
+  outexp = 0;
+  dout = sqrt(1.0 / in);
+  while (dout < 1) {
+    dout *= radix;
+    outexp--;
+  }
+  out[1] = outexp;
+  mp_unexp_d2mp(n, radix, dout, (DGTINT *)&out[2]);
+}
+
+void mp_unexp_d2mp(int n, int radix, double din, DGTINT out[]) {
+  int j, x;
+
+  for (j = 0; j < n; j++) {
+    x = (int)din;
+    if (x >= radix) {
+      x = radix - 1;
+      din = radix;
+    }
+    din = radix * (din - x);
+    out[j] = (DGTINT)x;
+  }
+}
+
+double mp_unexp_mp2d(int n, int radix, DGTINT in[]) {
+  int j;
+  double d1_radix, dout;
+
+  d1_radix = 1.0 / radix;
+  dout = 0;
+  for (j = n - 1; j >= 0; j--) {
+    dout = d1_radix * dout + in[j];
+  }
+  return dout;
+}
+
+int mp_inv_newton(int n, int radix, int in[], int inout[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]) {
+  void mp_load_1(int n, int radix, int out[]);
+  void mp_round(int n, int radix, int m, int inout[]);
+  void mp_add(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_sub(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_mulh(int n, int radix, int in1[], int in2[], int out[], int nfft, double in1fft[], double outfft[]);
+  void mp_mulh_use_in1fft(int n, int radix, double in1fft[], int shift, int in2[], int out[], int nfft, double outfft[]);
+  int n_h, shift, prc;
+
+  shift = (nfft >> 1) + 1;
+  n_h = n / 2 + 1;
+  if (n_h < n - shift) {
+    n_h = n - shift;
+  }
+  /* ---- tmp1 = inout * (upper) in (half to normal precision) ---- */
+  mp_round(n, radix, shift, inout);
+  mp_mulh(n, radix, inout, in, tmp1, nfft, tmp1fft, tmp2fft);
+  /* ---- tmp2 = 1 - tmp1 ---- */
+  mp_load_1(n, radix, tmp2);
+  mp_sub(n, radix, tmp2, tmp1, tmp2);
+  /* ---- tmp2 -= inout * (lower) in (half precision) ---- */
+  mp_mulh_use_in1fft(n, radix, tmp1fft, shift, in, tmp1, nfft, tmp2fft);
+  mp_sub(n_h, radix, tmp2, tmp1, tmp2);
+  /* ---- get precision ---- */
+  prc = -tmp2[1];
+  if (tmp2[0] == 0) {
+    prc = nfft + 1;
+  }
+  /* ---- tmp2 *= inout (half precision) ---- */
+  mp_mulh_use_in1fft(n_h, radix, tmp1fft, 0, tmp2, tmp2, nfft, tmp2fft);
+  /* ---- inout += tmp2 ---- */
+  mp_add(n, radix, inout, tmp2, inout);
+  return prc;
+}
+
+int mp_sqrt_newton(int n, int radix, int in[], int inout[], int inout_rev[], int tmp[], int nfft, double tmp1fft[], double tmp2fft[], int *n_tmp1fft) {
+  void mp_round(int n, int radix, int m, int inout[]);
+  void mp_add(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_sub(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_idiv_2(int n, int radix, int in[], int out[]);
+  void mp_mulh(int n, int radix, int in1[], int in2[], int out[], int nfft, double in1fft[], double outfft[]);
+  void mp_squh(int n, int radix, int in[], int out[], int nfft, double outfft[]);
+  void mp_squh_use_in1fft(int n, int radix, double inoutfft[], int out[], int nfft);
+  int n_h, nfft_h, shift, prc;
+
+  nfft_h = nfft >> 1;
+  shift = nfft_h + 1;
+  if (nfft_h < 2) {
+    nfft_h = 2;
+  }
+  n_h = n / 2 + 1;
+  if (n_h < n - shift) {
+    n_h = n - shift;
+  }
+  /* ---- tmp = inout_rev^2 (1/4 to half precision) ---- */
+  mp_round(n_h, radix, (nfft_h >> 1) + 1, inout_rev);
+  if (*n_tmp1fft != nfft_h) {
+    mp_squh(n_h, radix, inout_rev, tmp, nfft_h, tmp1fft);
+  } else {
+    mp_squh_use_in1fft(n_h, radix, tmp1fft, tmp, nfft_h);
+  }
+  /* ---- tmp = inout_rev - inout * tmp (half precision) ---- */
+  mp_round(n, radix, shift, inout);
+  mp_mulh(n_h, radix, inout, tmp, tmp, nfft, tmp1fft, tmp2fft);
+  mp_sub(n_h, radix, inout_rev, tmp, tmp);
+  /* ---- inout_rev += tmp ---- */
+  mp_add(n_h, radix, inout_rev, tmp, inout_rev);
+  /* ---- tmp = in - inout^2 (half to normal precision) ---- */
+  mp_squh_use_in1fft(n, radix, tmp1fft, tmp, nfft);
+  mp_sub(n, radix, in, tmp, tmp);
+  /* ---- get precision ---- */
+  prc = in[1] - tmp[1];
+  if (((DGTINT *)&in[2])[0] > ((DGTINT *)&tmp[2])[0]) {
+    prc++;
+  }
+  if (tmp[0] == 0) {
+    prc = nfft + 1;
+  }
+  /* ---- tmp = tmp * inout_rev / 2 (half precision) ---- */
+  mp_round(n_h, radix, shift, inout_rev);
+  mp_mulh(n_h, radix, inout_rev, tmp, tmp, nfft, tmp1fft, tmp2fft);
+  *n_tmp1fft = nfft;
+  mp_idiv_2(n_h, radix, tmp, tmp);
+  /* ---- inout += tmp ---- */
+  mp_add(n, radix, inout, tmp, inout);
+  return prc;
+}
+
+int mp_invisqrt_newton(int n, int radix, int in, int inout[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]) {
+  void mp_load_1(int n, int radix, int out[]);
+  void mp_round(int n, int radix, int m, int inout[]);
+  void mp_add(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_sub(int n, int radix, int in1[], int in2[], int out[]);
+  void mp_imul(int n, int radix, int in1[], int in2, int out[]);
+  void mp_idiv_2(int n, int radix, int in[], int out[]);
+  void mp_squh_save_infft(int n, int radix, int in[], int out[], int nfft, double infft[], double outfft[]);
+  void mp_mulh_use_in1fft(int n, int radix, double in1fft[], int shift, int in2[], int out[], int nfft, double outfft[]);
+  int n_h, shift, prc;
+
+  shift = (nfft >> 1) + 1;
+  n_h = n / 2 + 1;
+  if (n_h < n - shift) {
+    n_h = n - shift;
+  }
+  /* ---- tmp1 = in * inout^2 (half to normal precision) ---- */
+  mp_round(n, radix, shift, inout);
+  mp_squh_save_infft(n, radix, inout, tmp1, nfft, tmp1fft, tmp2fft);
+  mp_imul(n, radix, tmp1, in, tmp1);
+  /* ---- tmp2 = 1 - tmp1 ---- */
+  mp_load_1(n, radix, tmp2);
+  mp_sub(n, radix, tmp2, tmp1, tmp2);
+  /* ---- get precision ---- */
+  prc = -tmp2[1];
+  if (tmp2[0] == 0) {
+    prc = nfft + 1;
+  }
+  /* ---- tmp2 *= inout / 2 (half precision) ---- */
+  mp_mulh_use_in1fft(n_h, radix, tmp1fft, 0, tmp2, tmp2, nfft, tmp2fft);
+  mp_idiv_2(n_h, radix, tmp2, tmp2);
+  /* ---- inout += tmp2 ---- */
+  mp_add(n, radix, inout, tmp2, inout);
+  return prc;
+}
+
+/* -------- mp_io routines -------- */
+
+void mp_sprintf(int n, int log10_radix, int in[], char out[]) {
+  int j, k, x, y, outexp, shift;
+  DGTINT *inr;
+
+  inr = ((DGTINT *)&in[2]) - 2;
+  if (in[0] < 0) {
+    *out++ = '-';
+  }
+  x = inr[2];
+  shift = log10_radix;
+  for (k = log10_radix; k > 0; k--) {
+    y = x % 10;
+    x /= 10;
+    out[k] = '0' + y;
+    if (y != 0) {
+      shift = k;
+    }
+  }
+  out[0] = out[shift];
+  out[1] = '.';
+  for (k = 1; k <= log10_radix - shift; k++) {
+    out[k + 1] = out[k + shift];
+  }
+  outexp = log10_radix - shift;
+  out += outexp + 2;
+  for (j = 3; j <= n + 1; j++) {
+    x = inr[j];
+    for (k = log10_radix - 1; k >= 0; k--) {
+      y = x % 10;
+      x /= 10;
+      out[k] = '0' + y;
+    }
+    out += log10_radix;
+  }
+  *out++ = 'e';
+  outexp += log10_radix * in[1];
+  sprintf(out, "%d", outexp);
+}
+
+void mp_sscanf(int n, int log10_radix, char in[], int out[]) {
+  char *s;
+  int j, x, outexp, outexp_mod;
+  DGTINT *outr;
+
+  outr = ((DGTINT *)&out[2]) - 2;
+  while (*in == ' ') {
+    in++;
+  }
+  out[0] = 1;
+  if (*in == '-') {
+    out[0] = -1;
+    in++;
+  } else if (*in == '+') {
+    in++;
+  }
+  while (*in == ' ' || *in == '0') {
+    in++;
+  }
+  outexp = 0;
+  for (s = in; *s != '\0'; s++) {
+    if (*s == 'e' || *s == 'E' || *s == 'd' || *s == 'D') {
+      if (sscanf(++s, "%d", &outexp) != 1) {
+        outexp = 0;
+      }
+      break;
+    }
+  }
+  if (*in == '.') {
+    do {
+      outexp--;
+      while (*++in == ' ');
+    } while (*in == '0' && *in != '\0');
+  } else if (*in != '\0') {
+    s = in;
+    while (*++s == ' ');
+    while (*s >= '0' && *s <= '9' && *s != '\0') {
+      outexp++;
+      while (*++s == ' ');
+    }
+  }
+  x = outexp / log10_radix;
+  outexp_mod = outexp - log10_radix * x;
+  if (outexp_mod < 0) {
+    x--;
+    outexp_mod += log10_radix;
+  }
+  out[1] = x;
+  x = 0;
+  j = 2;
+  for (s = in; *s != '\0'; s++) {
+    if (*s == '.' || *s == ' ') {
+      continue;
+    }
+    if (*s < '0' || *s > '9') {
+      break;
+    }
+    x = 10 * x + (*s - '0');
+    if (--outexp_mod < 0) {
+      if (j > n + 1) {
+        break;
+      }
+      outr[j++] = (DGTINT)x;
+      x = 0;
+      outexp_mod = log10_radix - 1;
+    }
+  }
+  while (outexp_mod-- >= 0) {
+    x *= 10;
+  }
+  while (j <= n + 1) {
+    outr[j++] = (DGTINT)x;
+    x = 0;
+  }
+  if (outr[2] == 0) {
+    out[0] = 0;
+    out[1] = 0;
+  }
+}
diff --git a/tests/performance/superpi/pi_fftcs.h b/tests/performance/superpi/pi_fftcs.h
new file mode 100644
index 00000000000..419b15613b0
--- /dev/null
+++ b/tests/performance/superpi/pi_fftcs.h
@@ -0,0 +1,47 @@
+/*
+  Based on "Calculation of PI(= 3.14159...) using FFT and AGM" by T.Ooura, Nov. 1999.
+  https://github.com/Fibonacci43/SuperPI
+  Modified for Arduino by Lucas Saavedra Vaz, 2024.
+*/
+
+#pragma once
+
+#include <ctype.h>
+
+#define PI_FFTC_VER "ver. LG1.1.2-MP1.5.2a.memsave"
+
+/* Please check the following macros before compiling */
+#ifndef DBL_ERROR_MARGIN
+#define DBL_ERROR_MARGIN 0.4 /* must be < 0.5 */
+#endif
+
+#define DGTINT     short int /* sizeof(DGTINT) == 2 */
+#define DGTINT_MAX SHRT_MAX
+
+#define DGT_PACK       10
+#define DGT_PACK_LINE  5
+#define DGT_LINE_BLOCK 20
+
+void pi_calc(int nfft);
+void mp_load_0(int n, int radix, int out[]);
+void mp_load_1(int n, int radix, int out[]);
+void mp_round(int n, int radix, int m, int inout[]);
+int mp_cmp(int n, int radix, int in1[], int in2[]);
+void mp_add(int n, int radix, int in1[], int in2[], int out[]);
+void mp_sub(int n, int radix, int in1[], int in2[], int out[]);
+void mp_imul(int n, int radix, int in1[], int in2, int out[]);
+int mp_idiv(int n, int radix, int in1[], int in2, int out[]);
+void mp_idiv_2(int n, int radix, int in[], int out[]);
+double mp_mul_radix_test(int n, int radix, int nfft, double tmpfft[]);
+void mp_mul(int n, int radix, int in1[], int in2[], int out[], int tmp[], int nfft, double tmp1fft[], double tmp2fft[], double tmp3fft[]);
+void mp_squ(int n, int radix, int in[], int out[], int tmp[], int nfft, double tmp1fft[], double tmp2fft[]);
+void mp_mulhf(int n, int radix, int in1[], int in2[], int out[], int tmp[], int nfft, double in1fft[], double tmpfft[]);
+void mp_mulhf_use_in1fft(int n, int radix, double in1fft[], int in2[], int out[], int tmp[], int nfft, double tmpfft[]);
+void mp_squhf_use_infft(int n, int radix, double infft[], int in[], int out[], int tmp[], int nfft, double tmpfft[]);
+void mp_mulh(int n, int radix, int in1[], int in2[], int out[], int nfft, double in1fft[], double outfft[]);
+void mp_squh(int n, int radix, int in[], int out[], int nfft, double outfft[]);
+int mp_inv(int n, int radix, int in[], int out[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]);
+int mp_sqrt(int n, int radix, int in[], int out[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]);
+int mp_invisqrt(int n, int radix, int in, int out[], int tmp1[], int tmp2[], int nfft, double tmp1fft[], double tmp2fft[]);
+void mp_sprintf(int n, int log10_radix, int in[], char out[]);
+void mp_sscanf(int n, int log10_radix, char in[], int out[]);
diff --git a/tests/performance/superpi/superpi.ino b/tests/performance/superpi/superpi.ino
new file mode 100644
index 00000000000..7ac4b2f13d7
--- /dev/null
+++ b/tests/performance/superpi/superpi.ino
@@ -0,0 +1,41 @@
+/*
+  Based on "Calculation of PI(= 3.14159...) using FFT and AGM" by T.Ooura, Nov. 1999.
+  https://github.com/Fibonacci43/SuperPI
+  Modified for Arduino by Lucas Saavedra Vaz, 2024.
+*/
+
+#include <Arduino.h>
+
+#include "pi_fftcs.h"
+
+// Number of runs to average
+#define N_RUNS 3
+
+// Number of decimal digits to calculate
+#define DIGITS (1 << 14)
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  log_d("Starting PI calculation");
+  Serial.printf("Runs: %d\n", N_RUNS);
+  Serial.printf("Digits: %d\n", DIGITS);
+  Serial.flush();
+  for (int i = 0; i < N_RUNS; i++) {
+    Serial.printf("Run %d\n", i);
+    unsigned long start = millis();
+    pi_calc(DIGITS);
+    unsigned long elapsed = millis() - start;
+    Serial.printf("Time: %lu.%03lu s\n", elapsed / 1000, elapsed % 1000);
+    Serial.flush();
+  }
+
+  log_d("PI calculation test done");
+}
+
+void loop() {
+  vTaskDelete(NULL);
+}
diff --git a/tests/performance/superpi/test_superpi.py b/tests/performance/superpi/test_superpi.py
new file mode 100644
index 00000000000..0bd7a3477b6
--- /dev/null
+++ b/tests/performance/superpi/test_superpi.py
@@ -0,0 +1,53 @@
+import json
+import logging
+import os
+
+
+def test_superpi(dut, request):
+    LOGGER = logging.getLogger(__name__)
+
+    # Match "Runs: %d"
+    res = dut.expect(r"Runs: (\d+)", timeout=60)
+    runs = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of runs: {}".format(runs))
+
+    # Match "Digits: %d"
+    res = dut.expect(r"Digits: (\d+)", timeout=60)
+    digits = int(res.group(0).decode("utf-8").split(" ")[1])
+    LOGGER.info("Number of decimal digits: {}".format(digits))
+
+    list_time = []
+
+    for i in range(runs):
+        # Match "Run %d"
+        res = dut.expect(r"Run (\d+)", timeout=120)
+        run = int(res.group(0).decode("utf-8").split(" ")[1])
+        LOGGER.info("Run {}".format(run))
+        assert run == i, "Invalid run number"
+
+        # Match "Time: %lu.%03lu s"
+        res = dut.expect(r"Time: (\d+)\.(\d+) s", timeout=300)
+        time = float(res.group(0).decode("utf-8").split(" ")[1])
+        LOGGER.info("Time on run {}: {} s".format(i, time))
+        assert time > 0 and time < 1000, "Invalid time"
+        list_time.append(time)
+
+    avg_time = round(sum(list_time) / len(list_time), 3)
+
+    # Create JSON with results and write it to file
+    # Always create a JSON with this format (so it can be merged later on):
+    # { TEST_NAME_STR: TEST_RESULTS_DICT }
+    results = {"superpi": {"runs": runs, "digits": digits, "avg_time": avg_time}}
+
+    current_folder = os.path.dirname(request.path)
+    file_index = 0
+    report_file = os.path.join(current_folder, "result_superpi" + str(file_index) + ".json")
+    while os.path.exists(report_file):
+        report_file = report_file.replace(str(file_index) + ".json", str(file_index + 1) + ".json")
+        file_index += 1
+
+    with open(report_file, "w") as f:
+        try:
+            f.write(json.dumps(results))
+        except Exception as e:
+            LOGGER.warning("Failed to write results to file: {}".format(e))
diff --git a/tests/pytest.ini b/tests/pytest.ini
new file mode 100644
index 00000000000..b507b437727
--- /dev/null
+++ b/tests/pytest.ini
@@ -0,0 +1,13 @@
+[pytest]
+addopts = --embedded-services esp,arduino,wokwi,qemu
+
+# log related
+log_cli = True
+log_cli_level = INFO
+log_cli_format = %(asctime)s %(levelname)s %(message)s
+log_cli_date_format = %Y-%m-%d %H:%M:%S
+
+log_file = test.log
+log_file_level = INFO
+log_file_format = %(asctime)s %(levelname)s %(message)s
+log_file_date_format = %Y-%m-%d %H:%M:%S
diff --git a/tests/requirements.txt b/tests/requirements.txt
new file mode 100644
index 00000000000..b2bae3b86d0
--- /dev/null
+++ b/tests/requirements.txt
@@ -0,0 +1,8 @@
+cryptography==44.0.1
+--only-binary cryptography
+pytest-cov==5.0.0
+pytest-embedded-serial-esp==1.12.0
+pytest-embedded-arduino==1.12.0
+pytest-embedded-wokwi==1.12.0
+pytest-embedded-qemu==1.12.0
+esptool==4.8.1
diff --git a/tests/validation/democfg/ci.json b/tests/validation/democfg/ci.json
new file mode 100644
index 00000000000..cf5c796644e
--- /dev/null
+++ b/tests/validation/democfg/ci.json
@@ -0,0 +1,31 @@
+{
+  "fqbn": {
+    "esp32": [
+      "espressif:esp32:esp32:PSRAM=enabled,PartitionScheme=huge_app,FlashMode=dio",
+      "espressif:esp32:esp32:PSRAM=enabled,PartitionScheme=huge_app,FlashMode=qio"
+    ],
+    "esp32s2": [
+      "espressif:esp32:esp32s2:PSRAM=enabled,PartitionScheme=huge_app"
+    ],
+    "esp32s3": [
+      "espressif:esp32:esp32s3:PSRAM=opi,USBMode=default,PartitionScheme=huge_app"
+    ]
+  },
+  "platforms": {
+    "hardware": true,
+    "qemu": false,
+    "wokwi": false
+  },
+  "requires": [
+    "CONFIG_SOC_UART_SUPPORTED=y"
+  ],
+  "targets": {
+    "esp32": true,
+    "esp32c3": false,
+    "esp32c6": true,
+    "esp32h2": false,
+    "esp32s2": true,
+    "esp32s3": true,
+    "esp32p4": false
+  }
+}
diff --git a/tests/validation/democfg/democfg.ino b/tests/validation/democfg/democfg.ino
new file mode 100644
index 00000000000..ca20afedf49
--- /dev/null
+++ b/tests/validation/democfg/democfg.ino
@@ -0,0 +1,10 @@
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    ;
+  }
+
+  Serial.println("Hello cfg!");
+}
+
+void loop() {}
diff --git a/tests/validation/democfg/test_democfg.py b/tests/validation/democfg/test_democfg.py
new file mode 100644
index 00000000000..c19e51b5906
--- /dev/null
+++ b/tests/validation/democfg/test_democfg.py
@@ -0,0 +1,2 @@
+def test_cfg(dut):
+    dut.expect_exact("Hello cfg!")
diff --git a/tests/validation/gpio/ci.json b/tests/validation/gpio/ci.json
new file mode 100644
index 00000000000..7bc6a6ed163
--- /dev/null
+++ b/tests/validation/gpio/ci.json
@@ -0,0 +1,6 @@
+{
+  "platforms": {
+    "hardware": false,
+    "qemu": false
+  }
+}
diff --git a/tests/validation/gpio/diagram.esp32.json b/tests/validation/gpio/diagram.esp32.json
new file mode 100644
index 00000000000..05b28156e37
--- /dev/null
+++ b/tests/validation/gpio/diagram.esp32.json
@@ -0,0 +1,28 @@
+{
+  "version": 1,
+  "author": "P-R-O-C-H-Y",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-devkit-c-v4",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    {
+      "type": "wokwi-pushbutton",
+      "id": "btn1",
+      "top": -13,
+      "left": -19.2,
+      "attrs": { "color": "green" }
+    }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "btn1:1.l", "esp32:0", "blue", [ "h-19.2", "v48", "h-38.4" ] ],
+    [ "btn1:2.r", "esp32:GND.1", "black", [ "h19.4", "v173", "h-269.2", "v-98.23" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/gpio/diagram.esp32c3.json b/tests/validation/gpio/diagram.esp32c3.json
new file mode 100644
index 00000000000..c237e089ea2
--- /dev/null
+++ b/tests/validation/gpio/diagram.esp32c3.json
@@ -0,0 +1,28 @@
+{
+  "version": 1,
+  "author": "P-R-O-C-H-Y",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-c3-devkitm-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    {
+      "type": "wokwi-pushbutton",
+      "id": "btn1",
+      "top": -22.6,
+      "left": -19.2,
+      "attrs": { "color": "green" }
+    }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "btn1:1.l", "esp32:0", "blue", [ "h-28.8", "v144", "h-144", "v-95.7" ] ],
+    [ "btn1:2.r", "esp32:GND.1", "black", [ "h19.4", "v173", "h-269.2", "v-98.23" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/gpio/diagram.esp32c6.json b/tests/validation/gpio/diagram.esp32c6.json
new file mode 100644
index 00000000000..5020171f4e6
--- /dev/null
+++ b/tests/validation/gpio/diagram.esp32c6.json
@@ -0,0 +1,28 @@
+{
+  "version": 1,
+  "author": "P-R-O-C-H-Y",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-c6-devkitc-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    {
+      "type": "wokwi-pushbutton",
+      "id": "btn1",
+      "top": -22.6,
+      "left": -19.2,
+      "attrs": { "color": "green" }
+    }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "btn1:1.l", "esp32:0", "blue", [ "h-19.2", "v-96", "h-163.2", "v93.77" ] ],
+    [ "btn1:2.r", "esp32:GND.1", "black", [ "h19.4", "v173", "h-269.2", "v-98.23" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/gpio/diagram.esp32h2.json b/tests/validation/gpio/diagram.esp32h2.json
new file mode 100644
index 00000000000..48189dcea9f
--- /dev/null
+++ b/tests/validation/gpio/diagram.esp32h2.json
@@ -0,0 +1,28 @@
+{
+  "version": 1,
+  "author": "P-R-O-C-H-Y",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-h2-devkitm-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    {
+      "type": "wokwi-pushbutton",
+      "id": "btn1",
+      "top": -22.6,
+      "left": -19.2,
+      "attrs": { "color": "green" }
+    }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "btn1:1.l", "esp32:0", "blue", [ "h-19.2", "v-96", "h-163.2", "v93.77" ] ],
+    [ "btn1:2.r", "esp32:GND.1", "black", [ "h19.4", "v173", "h-269.2", "v-98.23" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/gpio/diagram.esp32p4.json b/tests/validation/gpio/diagram.esp32p4.json
new file mode 100644
index 00000000000..ffb0cde2775
--- /dev/null
+++ b/tests/validation/gpio/diagram.esp32p4.json
@@ -0,0 +1,28 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-p4-function-ev",
+      "id": "esp32",
+      "top": -66.32,
+      "left": -277.63,
+      "attrs": {}
+    },
+    {
+      "type": "wokwi-pushbutton",
+      "id": "btn1",
+      "top": -128.2,
+      "left": -19.2,
+      "attrs": { "color": "green", "bounce": "1" }
+    }
+  ],
+  "connections": [
+    [ "esp32:38", "$serialMonitor:TX", "", [] ],
+    [ "esp32:37", "$serialMonitor:RX", "", [] ],
+    [ "btn1:2.r", "esp32:GND.3", "black", [ "h19.4", "v29" ] ],
+    [ "esp32:0", "btn1:1.l", "blue", [ "h-48", "v-67.2" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/gpio/diagram.esp32s2.json b/tests/validation/gpio/diagram.esp32s2.json
new file mode 100644
index 00000000000..e3f850e193e
--- /dev/null
+++ b/tests/validation/gpio/diagram.esp32s2.json
@@ -0,0 +1,28 @@
+{
+  "version": 1,
+  "author": "P-R-O-C-H-Y",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-s2-devkitm-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    {
+      "type": "wokwi-pushbutton",
+      "id": "btn1",
+      "top": -22.6,
+      "left": -19.2,
+      "attrs": { "color": "green" }
+    }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "btn1:1.l", "esp32:0", "blue", [ "h-28.8", "v-57.6", "h-144", "v42.71" ] ],
+    [ "btn1:2.r", "esp32:GND.1", "black", [ "h19.4", "v173", "h-269.2", "v-98.23" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/gpio/diagram.esp32s3.json b/tests/validation/gpio/diagram.esp32s3.json
new file mode 100644
index 00000000000..ad9f9e0308a
--- /dev/null
+++ b/tests/validation/gpio/diagram.esp32s3.json
@@ -0,0 +1,28 @@
+{
+  "version": 1,
+  "author": "P-R-O-C-H-Y",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-s3-devkitc-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    {
+      "type": "wokwi-pushbutton",
+      "id": "btn1",
+      "top": -22.6,
+      "left": -19.2,
+      "attrs": { "color": "green" }
+    }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "btn1:1.l", "esp32:0", "blue", [ "h-38.4", "v105.78" ] ],
+    [ "btn1:2.r", "esp32:GND.1", "black", [ "h19.4", "v221", "h-269.2", "v-57.42" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/gpio/gpio.ino b/tests/validation/gpio/gpio.ino
new file mode 100644
index 00000000000..a5bec1cb5a3
--- /dev/null
+++ b/tests/validation/gpio/gpio.ino
@@ -0,0 +1,31 @@
+#include <Arduino.h>
+#include <unity.h>
+
+#define BTN 0
+
+void test_button() {
+  Serial.println("Button test");
+  static int count = 0;
+  static int lastState = HIGH;
+  while (count < 3) {
+    int state = digitalRead(BTN);
+    if (state != lastState) {
+      if (state == LOW) {
+        count++;
+        Serial.print("Button pressed ");
+        Serial.print(count);
+        Serial.println(" times");
+      }
+      lastState = state;
+    }
+    delay(10);
+  }
+}
+
+void setup() {
+  Serial.begin(115200);
+  pinMode(BTN, INPUT_PULLUP);
+  test_button();
+}
+
+void loop() {}
diff --git a/tests/validation/gpio/scenario.yaml b/tests/validation/gpio/scenario.yaml
new file mode 100644
index 00000000000..957f58b2176
--- /dev/null
+++ b/tests/validation/gpio/scenario.yaml
@@ -0,0 +1,40 @@
+name: Pushbutton counter test
+version: 1
+author: Jan Prochazka (jan.prochazka@espressif.com)
+
+steps:
+  - wait-serial: "Button test"
+
+  # Need for 1s delay for scenario to run properly
+  - delay: 5000ms
+
+  # Press once
+  - set-control:
+      part-id: btn1
+      control: pressed
+      value: 1
+  - delay: 2000ms
+  - set-control:
+      part-id: btn1
+      control: pressed
+      value: 0
+  - delay: 3000ms
+
+  # Press 2nd time
+  - set-control:
+      part-id: btn1
+      control: pressed
+      value: 1
+  - delay: 2000ms
+  - set-control:
+      part-id: btn1
+      control: pressed
+      value: 0
+  - delay: 3000ms
+
+  # Press for the 3rd time
+  - set-control:
+      part-id: btn1
+      control: pressed
+      value: 1
+  - wait-serial: "Button pressed 3 times"
diff --git a/tests/validation/gpio/test_gpio.py b/tests/validation/gpio/test_gpio.py
new file mode 100644
index 00000000000..8aa3a42dcc6
--- /dev/null
+++ b/tests/validation/gpio/test_gpio.py
@@ -0,0 +1,16 @@
+import logging
+
+
+def test_gpio(dut):
+    LOGGER = logging.getLogger(__name__)
+
+    dut.expect_exact("Button test")
+
+    LOGGER.info("Expecting button press 1")
+    dut.expect_exact("Button pressed 1 times")
+
+    LOGGER.info("Expecting button press 2")
+    dut.expect_exact("Button pressed 2 times")
+
+    LOGGER.info("Expecting button press 3")
+    dut.expect_exact("Button pressed 3 times")
diff --git a/tests/validation/hello_world/hello_world.ino b/tests/validation/hello_world/hello_world.ino
new file mode 100644
index 00000000000..5aaf971ecb9
--- /dev/null
+++ b/tests/validation/hello_world/hello_world.ino
@@ -0,0 +1,11 @@
+void setup() {
+  // Open serial communications and wait for port to open:
+  Serial.begin(115200);
+  while (!Serial) {
+    ;
+  }
+
+  Serial.println("Hello Arduino!");
+}
+
+void loop() {}
diff --git a/tests/validation/hello_world/test_hello_world.py b/tests/validation/hello_world/test_hello_world.py
new file mode 100644
index 00000000000..725e9a713c5
--- /dev/null
+++ b/tests/validation/hello_world/test_hello_world.py
@@ -0,0 +1,2 @@
+def test_hello_world(dut):
+    dut.expect_exact("Hello Arduino!")
diff --git a/tests/validation/i2c_master/ci.json b/tests/validation/i2c_master/ci.json
new file mode 100644
index 00000000000..2b8792cd131
--- /dev/null
+++ b/tests/validation/i2c_master/ci.json
@@ -0,0 +1,9 @@
+{
+  "platforms": {
+    "hardware": false,
+    "qemu": false
+  },
+  "requires": [
+    "CONFIG_SOC_I2C_SUPPORTED=y"
+  ]
+}
diff --git a/tests/validation/i2c_master/diagram.esp32.json b/tests/validation/i2c_master/diagram.esp32.json
new file mode 100644
index 00000000000..28e5d2e9c23
--- /dev/null
+++ b/tests/validation/i2c_master/diagram.esp32.json
@@ -0,0 +1,24 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-devkit-c-v4",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    { "type": "wokwi-ds1307", "id": "rtc1", "top": -43.8, "left": -19.1, "attrs": {} }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "esp32:22", "rtc1:SCL", "green", [ "h38.4", "v-9.6" ] ],
+    [ "esp32:21", "rtc1:SDA", "blue", [ "h48", "v-28.8", "h19.2" ] ],
+    [ "esp32:GND.2", "rtc1:GND", "black", [ "v0" ] ],
+    [ "rtc1:5V", "esp32:5V", "red", [ "h-28.8", "v-67.6", "h-172.8", "v230.4" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/i2c_master/diagram.esp32c3.json b/tests/validation/i2c_master/diagram.esp32c3.json
new file mode 100644
index 00000000000..a7471ec3ca1
--- /dev/null
+++ b/tests/validation/i2c_master/diagram.esp32c3.json
@@ -0,0 +1,25 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-c3-devkitm-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    { "type": "wokwi-ds1307", "id": "rtc1", "top": -43.8, "left": -19.1, "attrs": {} }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "rtc1:5V", "esp32:5V", "red", [ "h-28.8", "v-67.6", "h-172.8", "v230.4" ] ],
+    [ "esp32:5V.1", "rtc1:5V", "red", [ "h-18.22", "v-144.3", "h153.6", "v48" ] ],
+    [ "esp32:GND.10", "rtc1:GND", "black", [ "h56.16", "v9.3" ] ],
+    [ "esp32:8", "rtc1:SDA", "green", [ "h17.76", "v-19.5" ] ],
+    [ "esp32:9", "rtc1:SCL", "blue", [ "h0" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/i2c_master/diagram.esp32c6.json b/tests/validation/i2c_master/diagram.esp32c6.json
new file mode 100644
index 00000000000..9c759682ae5
--- /dev/null
+++ b/tests/validation/i2c_master/diagram.esp32c6.json
@@ -0,0 +1,26 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-c6-devkitc-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    { "type": "wokwi-ds1307", "id": "rtc1", "top": -43.8, "left": -19.1, "attrs": {} }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "rtc1:5V", "esp32:5V", "red", [ "h-28.8", "v-67.6", "h-172.8", "v230.4" ] ],
+    [ "esp32:5V.1", "rtc1:5V", "red", [ "h-18.22", "v-144.3", "h153.6", "v48" ] ],
+    [ "esp32:GND.10", "rtc1:GND", "black", [ "h56.16", "v9.3" ] ],
+    [ "esp32:23", "rtc1:SDA", "green", [ "h17.38", "v-23.51" ] ],
+    [ "esp32:GND.4", "rtc1:GND", "black", [ "h55.78", "v-4.31" ] ],
+    [ "esp32:22", "rtc1:SCL", "blue", [ "h26.98", "v-23.51" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/i2c_master/diagram.esp32h2.json b/tests/validation/i2c_master/diagram.esp32h2.json
new file mode 100644
index 00000000000..d2a2acfecd7
--- /dev/null
+++ b/tests/validation/i2c_master/diagram.esp32h2.json
@@ -0,0 +1,24 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-h2-devkitm-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    { "type": "wokwi-ds1307", "id": "rtc1", "top": -43.8, "left": -19.1, "attrs": {} }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "esp32:GND.6", "rtc1:GND", "black", [ "h0" ] ],
+    [ "esp32:5V", "rtc1:5V", "red", [ "h-29.14", "v-160.97", "h172.8", "v48" ] ],
+    [ "esp32:12", "rtc1:SDA", "green", [ "h36.58", "v-36.17" ] ],
+    [ "esp32:22", "rtc1:SCL", "blue", [ "v-7.37", "h46.18", "v-38.4" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/i2c_master/diagram.esp32p4.json b/tests/validation/i2c_master/diagram.esp32p4.json
new file mode 100644
index 00000000000..ab250c2aafd
--- /dev/null
+++ b/tests/validation/i2c_master/diagram.esp32p4.json
@@ -0,0 +1,24 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-p4-function-ev",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    { "type": "wokwi-ds1307", "id": "rtc1", "top": -197.4, "left": 57.7, "attrs": {} }
+  ],
+  "connections": [
+    [ "esp32:38", "$serialMonitor:TX", "", [] ],
+    [ "esp32:37", "$serialMonitor:RX", "", [] ],
+    [ "esp32:5V.1", "rtc1:5V", "red", [ "v0" ] ],
+    [ "esp32:GND.1", "rtc1:GND", "black", [ "v-133.52", "h5.53" ] ],
+    [ "esp32:7", "rtc1:SDA", "green", [ "v0" ] ],
+    [ "esp32:8", "rtc1:SCL", "blue", [ "h15.13", "v-114.12" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/i2c_master/diagram.esp32s2.json b/tests/validation/i2c_master/diagram.esp32s2.json
new file mode 100644
index 00000000000..c34a176bd7e
--- /dev/null
+++ b/tests/validation/i2c_master/diagram.esp32s2.json
@@ -0,0 +1,24 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-s2-devkitm-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    { "type": "wokwi-ds1307", "id": "rtc1", "top": -43.8, "left": -19.1, "attrs": {} }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "esp32:GND.2", "rtc1:GND", "black", [ "v0" ] ],
+    [ "rtc1:5V", "esp32:5V", "red", [ "h-28.8", "v-67.6", "h-172.8", "v230.4" ] ],
+    [ "esp32:8", "rtc1:SDA", "green", [ "h-19.47", "v-119.51", "h144", "v57.6" ] ],
+    [ "esp32:9", "rtc1:SCL", "blue", [ "h-29.07", "v-138.71", "h144", "v76.8" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/i2c_master/diagram.esp32s3.json b/tests/validation/i2c_master/diagram.esp32s3.json
new file mode 100644
index 00000000000..6d168fb42e6
--- /dev/null
+++ b/tests/validation/i2c_master/diagram.esp32s3.json
@@ -0,0 +1,24 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-s3-devkitc-1",
+      "id": "esp32",
+      "top": -57.6,
+      "left": -177.56,
+      "attrs": {}
+    },
+    { "type": "wokwi-ds1307", "id": "rtc1", "top": -43.8, "left": -19.1, "attrs": {} }
+  ],
+  "connections": [
+    [ "esp32:RX", "$serialMonitor:TX", "", [] ],
+    [ "esp32:TX", "$serialMonitor:RX", "", [] ],
+    [ "esp32:GND.2", "rtc1:GND", "black", [ "v0" ] ],
+    [ "rtc1:5V", "esp32:5V", "red", [ "h-28.8", "v-67.6", "h-172.8", "v230.4" ] ],
+    [ "esp32:8", "rtc1:SDA", "green", [ "h-19.47", "v-119.51", "h144", "v32.93", "h38.35" ] ],
+    [ "esp32:9", "rtc1:SCL", "blue", [ "h-29.07", "v-138.71", "h144", "v32.93", "h47.95" ] ]
+  ],
+  "dependencies": {}
+}
diff --git a/tests/validation/i2c_master/i2c_master.ino b/tests/validation/i2c_master/i2c_master.ino
new file mode 100644
index 00000000000..41e7d2ae5f9
--- /dev/null
+++ b/tests/validation/i2c_master/i2c_master.ino
@@ -0,0 +1,319 @@
+/*
+  I2C Master Test for
+*/
+
+#include <Arduino.h>
+#include <unity.h>
+#include <Wire.h>
+#include <vector>
+#include <algorithm>
+#include <WiFi.h>
+
+#include "sdkconfig.h"
+
+/* DS1307 functions */
+
+const uint8_t DS1307_ADDR = 0x68;
+const uint8_t start_sec = 1;
+const uint8_t start_min = 2;
+const uint8_t start_hour = 3;
+const uint8_t start_day = 4;
+const uint8_t start_month = 5;
+const uint16_t start_year = 2020;
+
+static uint8_t read_sec = 0;
+static uint8_t read_min = 0;
+static uint8_t read_hour = 0;
+static uint8_t read_day = 0;
+static uint8_t read_month = 0;
+static uint16_t read_year = 0;
+static int peek_data = -1;
+
+const char *ssid = "Wokwi-GUEST";
+const char *password = "";
+
+const auto BCD2DEC = [](uint8_t num) -> uint8_t {
+  return ((num / 16 * 10) + (num % 16));
+};
+
+const auto DEC2BCD = [](uint8_t num) -> uint8_t {
+  return ((num / 10 * 16) + (num % 10));
+};
+
+void reset_read_values() {
+  read_sec = 0;
+  read_min = 0;
+  read_hour = 0;
+  read_day = 0;
+  read_month = 0;
+  read_year = 0;
+}
+
+void ds1307_start(void) {
+  uint8_t sec;
+
+  //Get seconds
+  Wire.beginTransmission(DS1307_ADDR);
+  Wire.write(0x00);
+  Wire.endTransmission();
+  Wire.requestFrom(DS1307_ADDR, 1);
+  sec = Wire.read() & 0x7F;  //Seconds without halt bit
+
+  //Set seconds and start clock
+  Wire.beginTransmission(DS1307_ADDR);
+  Wire.write(0x00);
+  Wire.write(sec);
+  Wire.endTransmission();
+}
+
+void ds1307_stop(void) {
+  uint8_t sec;
+
+  //Get seconds
+  Wire.beginTransmission(DS1307_ADDR);
+  Wire.write(0x00);
+  Wire.endTransmission();
+  Wire.requestFrom(DS1307_ADDR, 1);
+  sec = Wire.read() | 0x80;  //Seconds with halt bit
+
+  //Set seconds and halt clock
+  Wire.beginTransmission(DS1307_ADDR);
+  Wire.write(0x00);
+  Wire.write(sec);
+  Wire.endTransmission();
+}
+
+void ds1307_get_time(uint8_t *sec, uint8_t *min, uint8_t *hour, uint8_t *day, uint8_t *month, uint16_t *year) {
+  //Get time
+  Wire.beginTransmission(DS1307_ADDR);
+  Wire.write(0x00);
+  Wire.endTransmission();
+  Wire.requestFrom(DS1307_ADDR, 7);
+
+  TEST_ASSERT_EQUAL(7, Wire.available());
+
+  if (peek_data == -1 && Wire.peek() != -1) {
+    peek_data = Wire.peek();
+  }
+
+  *sec = BCD2DEC(Wire.read() & 0x7F);  //Seconds without halt bit
+  *min = BCD2DEC(Wire.read());
+  *hour = BCD2DEC(Wire.read() & 0x3F);
+  Wire.read();  //Ignore day of week
+  *day = BCD2DEC(Wire.read());
+  *month = BCD2DEC(Wire.read());
+  *year = BCD2DEC(Wire.read()) + 2000;
+}
+
+void ds1307_set_time(uint8_t sec, uint8_t min, uint8_t hour, uint8_t day, uint8_t month, uint16_t year) {
+  Wire.beginTransmission(DS1307_ADDR);
+  Wire.write(0x00);
+  Wire.write(DEC2BCD(sec));
+  Wire.write(DEC2BCD(min));
+  Wire.write(DEC2BCD(hour));
+  Wire.write(DEC2BCD(0));  //Ignore day of week
+  Wire.write(DEC2BCD(day));
+  Wire.write(DEC2BCD(month));
+  Wire.write(DEC2BCD(year - 2000));
+  Wire.endTransmission();
+}
+
+/* Unity functions */
+
+// This function is automatically called by unity before each test is run
+void setUp(void) {
+  reset_read_values();
+  Wire.begin();
+}
+
+// This function is automatically called by unity after each test is run
+void tearDown(void) {
+  //Reset time
+  ds1307_set_time(start_sec, start_min, start_hour, start_day, start_month, start_year);
+
+  Wire.end();
+}
+
+void rtc_set_time() {
+  //Set time
+  ds1307_set_time(start_sec, start_min, start_hour, start_day, start_month, start_year);
+
+  //Get time
+  ds1307_get_time(&read_sec, &read_min, &read_hour, &read_day, &read_month, &read_year);
+
+  //Check time
+  TEST_ASSERT_EQUAL(start_sec, read_sec);
+  TEST_ASSERT_EQUAL(start_min, read_min);
+  TEST_ASSERT_EQUAL(start_hour, read_hour);
+  TEST_ASSERT_EQUAL(start_day, read_day);
+  TEST_ASSERT_EQUAL(start_month, read_month);
+  TEST_ASSERT_EQUAL(start_year, read_year);
+}
+
+void rtc_run_clock() {
+  uint8_t old_sec = 0;
+
+  //Run clock for 5 seconds
+  ds1307_start();
+  delay(5000);
+  ds1307_stop();
+
+  //Get time
+  ds1307_get_time(&read_sec, &read_min, &read_hour, &read_day, &read_month, &read_year);
+
+  //Check time
+  TEST_ASSERT_NOT_EQUAL(start_sec, read_sec);  //Seconds should have changed
+  TEST_ASSERT_EQUAL(start_min, read_min);
+  TEST_ASSERT_EQUAL(start_hour, read_hour);
+  TEST_ASSERT_EQUAL(start_day, read_day);
+  TEST_ASSERT_EQUAL(start_month, read_month);
+  TEST_ASSERT_EQUAL(start_year, read_year);
+
+  old_sec = read_sec;
+  reset_read_values();
+
+  //Get time again to check that clock is stopped
+  delay(2000);
+  ds1307_get_time(&read_sec, &read_min, &read_hour, &read_day, &read_month, &read_year);
+
+  //Check time
+  TEST_ASSERT_EQUAL(old_sec, read_sec);
+  TEST_ASSERT_EQUAL(start_min, read_min);
+  TEST_ASSERT_EQUAL(start_hour, read_hour);
+  TEST_ASSERT_EQUAL(start_day, read_day);
+  TEST_ASSERT_EQUAL(start_month, read_month);
+  TEST_ASSERT_EQUAL(start_year, read_year);
+}
+
+void change_clock() {
+  //Get time
+  ds1307_get_time(&read_sec, &read_min, &read_hour, &read_day, &read_month, &read_year);
+
+  //Check time
+  TEST_ASSERT_EQUAL(start_sec, read_sec);
+  TEST_ASSERT_EQUAL(start_min, read_min);
+  TEST_ASSERT_EQUAL(start_hour, read_hour);
+  TEST_ASSERT_EQUAL(start_day, read_day);
+  TEST_ASSERT_EQUAL(start_month, read_month);
+  TEST_ASSERT_EQUAL(start_year, read_year);
+
+  Wire.setClock(400000);
+  reset_read_values();
+
+  TEST_ASSERT_EQUAL(400000, Wire.getClock());
+
+  //Get time
+  ds1307_get_time(&read_sec, &read_min, &read_hour, &read_day, &read_month, &read_year);
+
+  //Check time
+  TEST_ASSERT_EQUAL(start_sec, read_sec);
+  TEST_ASSERT_EQUAL(start_min, read_min);
+  TEST_ASSERT_EQUAL(start_hour, read_hour);
+  TEST_ASSERT_EQUAL(start_day, read_day);
+  TEST_ASSERT_EQUAL(start_month, read_month);
+  TEST_ASSERT_EQUAL(start_year, read_year);
+}
+
+void swap_pins() {
+  Wire.setPins(SCL, SDA);
+  Wire.begin();
+  //Set time
+  ds1307_set_time(start_sec, start_min, start_hour, start_day, start_month, start_year);
+
+  //Get time
+  ds1307_get_time(&read_sec, &read_min, &read_hour, &read_day, &read_month, &read_year);
+
+  //Check time
+  TEST_ASSERT_EQUAL(start_sec, read_sec);
+  TEST_ASSERT_EQUAL(start_min, read_min);
+  TEST_ASSERT_EQUAL(start_hour, read_hour);
+  TEST_ASSERT_EQUAL(start_day, read_day);
+  TEST_ASSERT_EQUAL(start_month, read_month);
+  TEST_ASSERT_EQUAL(start_year, read_year);
+
+  Wire.setPins(SDA, SCL);
+}
+
+void test_api() {
+  int integer_ret;
+
+  // Set Buffer Size
+  integer_ret = Wire.setBufferSize(32);
+  TEST_ASSERT_EQUAL(32, integer_ret);
+  integer_ret = Wire.setBufferSize(I2C_BUFFER_LENGTH);
+  TEST_ASSERT_EQUAL(I2C_BUFFER_LENGTH, integer_ret);
+
+  // Set TimeOut
+  Wire.setTimeOut(100);
+  TEST_ASSERT_EQUAL(100, Wire.getTimeOut());
+
+  // Check if buffer can be peeked
+  TEST_ASSERT_GREATER_THAN(-1, peek_data);
+
+  Wire.flush();
+}
+
+bool device_found() {
+  uint8_t err;
+
+  for (uint8_t address = 1; address < 127; ++address) {
+    Wire.beginTransmission(address);
+    err = Wire.endTransmission();
+    log_d("Address: 0x%02X, Error: %d", address, err);
+    if (err == 0) {
+      log_i("Found device at address: 0x%02X", address);
+    } else if (address == DS1307_ADDR) {
+      log_e("Failed to find DS1307");
+      return false;
+    }
+  }
+
+  return true;
+}
+
+void scan_bus() {
+  TEST_ASSERT_TRUE(device_found());
+}
+
+#if SOC_WIFI_SUPPORTED
+void scan_bus_with_wifi() {
+  // delete old config
+  WiFi.disconnect(true, true, 1000);
+  delay(1000);
+  WiFi.begin(ssid, password);
+  delay(5000);
+  bool found = device_found();
+  WiFi.disconnect(true, true, 1000);
+
+  TEST_ASSERT_TRUE(found);
+}
+#endif
+
+/* Main */
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  log_d("Starting I2C Master");
+  Wire.begin();
+
+  log_d("Starting tests");
+  UNITY_BEGIN();
+  RUN_TEST(scan_bus);
+#if SOC_WIFI_SUPPORTED
+  RUN_TEST(scan_bus_with_wifi);
+#endif
+  RUN_TEST(rtc_set_time);
+  RUN_TEST(rtc_run_clock);
+  RUN_TEST(change_clock);
+  RUN_TEST(swap_pins);
+  RUN_TEST(test_api);
+  UNITY_END();
+}
+
+void loop() {
+  vTaskDelete(NULL);
+}
diff --git a/tests/validation/i2c_master/test_i2c_master.py b/tests/validation/i2c_master/test_i2c_master.py
new file mode 100644
index 00000000000..da5f790c0f8
--- /dev/null
+++ b/tests/validation/i2c_master/test_i2c_master.py
@@ -0,0 +1,2 @@
+def test_i2c_master(dut):
+    dut.expect_unity_test_output(timeout=240)
diff --git a/tests/validation/nvs/ci.json b/tests/validation/nvs/ci.json
new file mode 100644
index 00000000000..7f8ce83ec54
--- /dev/null
+++ b/tests/validation/nvs/ci.json
@@ -0,0 +1,42 @@
+{
+  "fqbn": {
+    "esp32": [
+      "espressif:esp32:esp32:PSRAM=enabled,PartitionScheme=huge_app,FlashMode=dio",
+      "espressif:esp32:esp32:PSRAM=enabled,PartitionScheme=huge_app,FlashMode=qio"
+    ],
+    "esp32c3": [
+      "espressif:esp32:esp32c3:PartitionScheme=huge_app,FlashMode=dio",
+      "espressif:esp32:esp32c3:PartitionScheme=huge_app,FlashMode=qio"
+    ],
+    "esp32c6": [
+      "espressif:esp32:esp32c6:PartitionScheme=huge_app,FlashMode=dio",
+      "espressif:esp32:esp32c6:PartitionScheme=huge_app,FlashMode=dio,FlashFreq=40",
+      "espressif:esp32:esp32c6:PartitionScheme=huge_app,FlashMode=qio",
+      "espressif:esp32:esp32c6:PartitionScheme=huge_app,FlashMode=qio,FlashFreq=40"
+    ],
+    "esp32h2": [
+      "espressif:esp32:esp32h2:PartitionScheme=huge_app,FlashMode=dio",
+      "espressif:esp32:esp32h2:PartitionScheme=huge_app,FlashMode=dio,FlashFreq=16",
+      "espressif:esp32:esp32h2:PartitionScheme=huge_app,FlashMode=qio",
+      "espressif:esp32:esp32h2:PartitionScheme=huge_app,FlashMode=qio,FlashFreq=16"
+    ],
+    "esp32s2": [
+      "espressif:esp32:esp32s2:PSRAM=enabled,PartitionScheme=huge_app,FlashMode=dio",
+      "espressif:esp32:esp32s2:PSRAM=enabled,PartitionScheme=huge_app,FlashMode=qio"
+    ],
+    "esp32s3": [
+      "espressif:esp32:esp32s3:PSRAM=opi,USBMode=default,PartitionScheme=huge_app,FlashMode=qio",
+      "espressif:esp32:esp32s3:PSRAM=opi,USBMode=default,PartitionScheme=huge_app,FlashMode=qio120",
+      "espressif:esp32:esp32s3:PSRAM=opi,USBMode=default,PartitionScheme=huge_app,FlashMode=dio"
+    ],
+    "esp32p4": [
+      "espressif:esp32:esp32p4:PSRAM=enabled,USBMode=default,PartitionScheme=huge_app,FlashMode=dio",
+      "espressif:esp32:esp32p4:PSRAM=enabled,USBMode=default,PartitionScheme=huge_app,FlashMode=dio,FlashFreq=40",
+      "espressif:esp32:esp32p4:PSRAM=enabled,USBMode=default,PartitionScheme=huge_app,FlashMode=qio",
+      "espressif:esp32:esp32p4:PSRAM=enabled,USBMode=default,PartitionScheme=huge_app,FlashMode=qio,FlashFreq=40"
+    ]
+  },
+  "platforms": {
+    "qemu": false
+  }
+}
diff --git a/tests/validation/nvs/nvs.ino b/tests/validation/nvs/nvs.ino
new file mode 100644
index 00000000000..20b5b460098
--- /dev/null
+++ b/tests/validation/nvs/nvs.ino
@@ -0,0 +1,36 @@
+#include <Preferences.h>
+
+Preferences preferences;
+
+void setup() {
+  Serial.begin(115200);
+
+  while (!Serial) {
+    ;
+  }
+
+  preferences.begin("my-app", false);
+
+  // Get the counter value, if the key does not exist, return a default value of 0
+  unsigned int counter = preferences.getUInt("counter", 0);
+
+  // Print the counter to Serial Monitor
+  Serial.printf("Current counter value: %u\n", counter);
+
+  // Increase counter by 1
+  counter++;
+
+  // Store the counter to the Preferences
+  preferences.putUInt("counter", counter);
+
+  // Close the Preferences
+  preferences.end();
+
+  // Wait 1 second
+  delay(1000);
+
+  // Restart ESP
+  ESP.restart();
+}
+
+void loop() {}
diff --git a/tests/validation/nvs/test_nvs.py b/tests/validation/nvs/test_nvs.py
new file mode 100644
index 00000000000..424095a49ba
--- /dev/null
+++ b/tests/validation/nvs/test_nvs.py
@@ -0,0 +1,14 @@
+import logging
+
+
+def test_nvs(dut):
+    LOGGER = logging.getLogger(__name__)
+
+    LOGGER.info("Expecting counter value 0")
+    dut.expect_exact("Current counter value: 0")
+
+    LOGGER.info("Expecting counter value 1")
+    dut.expect_exact("Current counter value: 1")
+
+    LOGGER.info("Expecting counter value 2")
+    dut.expect_exact("Current counter value: 2")
diff --git a/tests/validation/periman/ci.json b/tests/validation/periman/ci.json
new file mode 100644
index 00000000000..22ff71c54ff
--- /dev/null
+++ b/tests/validation/periman/ci.json
@@ -0,0 +1,9 @@
+{
+  "platforms": {
+    "qemu": false,
+    "wokwi": false
+  },
+  "targets": {
+    "esp32p4": false
+  }
+}
diff --git a/tests/validation/periman/periman.ino b/tests/validation/periman/periman.ino
new file mode 100644
index 00000000000..8da59dd23b9
--- /dev/null
+++ b/tests/validation/periman/periman.ino
@@ -0,0 +1,301 @@
+/* Peripheral Manager test
+ *
+ * This test is using Serial to check if the peripheral manager is able to
+ * attach and detach peripherals correctly on shared pins.
+ * Make sure that the peripheral names contain only letters, numbers and underscores.
+ *
+ * This test skips the following peripherals:
+ * - USB: USB is not able to be detached
+ * - SDMMC: SDMMC requires a card to be mounted before the pins are attached
+ * - ETH: ETH requires a ethernet port to be connected before the pins are attached
+ */
+
+#if SOC_I2S_SUPPORTED
+#include "ESP_I2S.h"
+#endif
+
+#if SOC_I2C_SUPPORTED
+#include "Wire.h"
+#endif
+
+#if SOC_GPSPI_SUPPORTED
+#include "SPI.h"
+#endif
+
+/* Definitions */
+
+#define UART1_RX_DEFAULT 4
+#define UART1_TX_DEFAULT 5
+
+#define ADC1_DEFAULT A4
+
+#if CONFIG_IDF_TARGET_ESP32
+#define ADC2_DEFAULT A5
+#else
+#define ADC2_DEFAULT A3
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32
+#define TOUCH1_DEFAULT T0
+#define TOUCH2_DEFAULT T2
+#else
+#define TOUCH1_DEFAULT T4
+#define TOUCH2_DEFAULT T5
+#endif
+
+/* Global variables */
+
+bool test_executed = false;
+String current_test;
+int8_t uart1_rx_pin;
+int8_t uart1_tx_pin;
+
+/* Callback functions */
+
+void onReceive_cb(void) {
+  // This is a callback function that will be activated on UART RX events
+  size_t available = Serial1.available();
+  while (available--) {
+    Serial.print((char)Serial1.read());
+  }
+}
+
+// This function is called by before each test is run
+void setup_test(String test_name, int8_t rx_pin = UART1_RX_DEFAULT, int8_t tx_pin = UART1_TX_DEFAULT) {
+  log_v("Setting up %s test", test_name.c_str());
+
+  current_test = test_name;
+  uart1_rx_pin = rx_pin;
+  uart1_tx_pin = tx_pin;
+  test_executed = false;
+
+  pinMode(uart1_rx_pin, INPUT_PULLUP);
+  pinMode(uart1_tx_pin, OUTPUT);
+  Serial1.setPins(uart1_rx_pin, uart1_tx_pin);
+  uart_internal_loopback(1, uart1_rx_pin);
+  delay(100);
+  log_v("Running %s test", test_name.c_str());
+}
+
+// This function is called after each test is run
+void teardown_test(void) {
+  log_v("Tearing down %s test", current_test.c_str());
+  if (test_executed) {
+    pinMode(uart1_rx_pin, INPUT_PULLUP);
+    pinMode(uart1_tx_pin, OUTPUT);
+    Serial1.print(current_test);
+    Serial1.println(" test: This should not be printed");
+    Serial1.flush();
+
+    Serial1.setPins(uart1_rx_pin, uart1_tx_pin);
+    uart_internal_loopback(1, uart1_rx_pin);
+    delay(100);
+  }
+
+  Serial1.print(current_test);
+  Serial1.println(" test: This should be printed");
+  Serial1.flush();
+
+  log_v("Finished %s test", current_test.c_str());
+}
+
+/* Test functions */
+/* These functions must call "setup_test" and "teardown_test" and set "test_executed" to true
+ * if the test is executed
+ */
+
+void gpio_test(void) {
+  setup_test("GPIO");
+  test_executed = true;
+  pinMode(uart1_rx_pin, INPUT);
+  pinMode(uart1_tx_pin, OUTPUT);
+  digitalRead(uart1_rx_pin);
+  digitalWrite(uart1_tx_pin, HIGH);
+  teardown_test();
+}
+
+void sigmadelta_test(void) {
+  setup_test("SigmaDelta");
+#if SOC_SDM_SUPPORTED
+  test_executed = true;
+  if (!sigmaDeltaAttach(uart1_rx_pin, 312500)) {
+    Serial.println("SigmaDelta init failed");
+  }
+  if (!sigmaDeltaAttach(uart1_tx_pin, 312500)) {
+    Serial.println("SigmaDelta init failed");
+  }
+#endif
+  teardown_test();
+}
+
+void adc_oneshot_test(void) {
+#if !SOC_ADC_SUPPORTED
+  setup_test("ADC_Oneshot");
+#else
+  setup_test("ADC_Oneshot", ADC1_DEFAULT, ADC2_DEFAULT);
+  test_executed = true;
+  analogReadResolution(12);
+  pinMode(ADC1_DEFAULT, INPUT);
+  pinMode(ADC2_DEFAULT, INPUT);
+  analogRead(ADC1_DEFAULT);
+  analogRead(ADC2_DEFAULT);
+#endif
+  teardown_test();
+}
+
+#if SOC_ADC_SUPPORTED
+volatile bool adc_coversion_done = false;
+void ARDUINO_ISR_ATTR adcComplete() {
+  adc_coversion_done = true;
+}
+#endif
+
+void adc_continuous_test(void) {
+#if !SOC_ADC_SUPPORTED
+  setup_test("ADC_Continuous");
+#else
+  setup_test("ADC_Continuous", ADC1_DEFAULT, ADC2_DEFAULT);
+  test_executed = true;
+  uint8_t adc_pins[] = {ADC1_DEFAULT, ADC2_DEFAULT};
+  uint8_t adc_pins_count = 2;
+  adc_continuous_data_t *result = NULL;
+
+  analogContinuousSetWidth(12);
+  analogContinuousSetAtten(ADC_11db);
+
+  analogContinuous(adc_pins, adc_pins_count, 6, 20000, &adcComplete);
+  analogContinuousStart();
+
+  while (adc_coversion_done == false) {
+    delay(1);
+  }
+
+  if (!analogContinuousRead(&result, 0)) {
+    Serial.println("ADC continuous read failed");
+  }
+
+  analogContinuousStop();
+#endif
+  teardown_test();
+}
+
+void dac_test(void) {
+#if !SOC_DAC_SUPPORTED
+  setup_test("DAC");
+#else
+  setup_test("DAC", DAC1, DAC2);
+  test_executed = true;
+  dacWrite(DAC1, 255);
+  dacWrite(DAC2, 255);
+#endif
+  teardown_test();
+}
+
+void ledc_test(void) {
+  setup_test("LEDC");
+#if SOC_LEDC_SUPPORTED
+  test_executed = true;
+  if (!ledcAttach(uart1_rx_pin, 5000, 12)) {
+    Serial.println("LEDC init failed");
+  }
+  if (!ledcAttach(uart1_tx_pin, 5000, 12)) {
+    Serial.println("LEDC init failed");
+  }
+#endif
+  teardown_test();
+}
+
+void rmt_test(void) {
+  setup_test("RMT");
+#if SOC_RMT_SUPPORTED
+  test_executed = true;
+  if (!rmtInit(uart1_rx_pin, RMT_TX_MODE, RMT_MEM_NUM_BLOCKS_1, 10000000)) {
+    Serial.println("RMT init failed");
+  }
+  if (!rmtInit(uart1_tx_pin, RMT_RX_MODE, RMT_MEM_NUM_BLOCKS_1, 10000000)) {
+    Serial.println("RMT init failed");
+  }
+#endif
+  teardown_test();
+}
+
+void i2s_test(void) {
+  setup_test("I2S");
+#if SOC_I2S_SUPPORTED
+  test_executed = true;
+  I2SClass i2s;
+
+  i2s.setPins(uart1_rx_pin, uart1_tx_pin, -1);
+  i2s.setTimeout(1000);
+  if (!i2s.begin(I2S_MODE_STD, 16000, I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO)) {
+    Serial.println("I2S init failed");
+  }
+#endif
+  teardown_test();
+}
+
+void i2c_test(void) {
+  setup_test("I2C");
+#if SOC_I2C_SUPPORTED
+  test_executed = true;
+  if (!Wire.begin(uart1_rx_pin, uart1_tx_pin)) {
+    Serial.println("I2C init failed");
+  }
+#endif
+  teardown_test();
+}
+
+void spi_test(void) {
+  setup_test("SPI");
+#if SOC_GPSPI_SUPPORTED
+  test_executed = true;
+  SPI.begin(uart1_rx_pin, uart1_tx_pin, -1, -1);
+#endif
+  teardown_test();
+}
+
+void touch_test(void) {
+#if !SOC_TOUCH_SENSOR_SUPPORTED
+  setup_test("Touch");
+#else
+  setup_test("Touch", TOUCH1_DEFAULT, TOUCH2_DEFAULT);
+  test_executed = true;
+  touchRead(TOUCH1_DEFAULT);
+  touchRead(TOUCH2_DEFAULT);
+#endif
+  teardown_test();
+}
+
+/* Main functions */
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  Serial1.setPins(UART1_RX_DEFAULT, UART1_TX_DEFAULT);
+  Serial1.begin(115200);
+  while (!Serial1) {
+    delay(10);
+  }
+  Serial1.onReceive(onReceive_cb);
+  uart_internal_loopback(1, uart1_rx_pin);
+
+  gpio_test();
+  sigmadelta_test();
+  ledc_test();
+  rmt_test();
+  i2s_test();
+  i2c_test();
+  spi_test();
+  adc_oneshot_test();
+  adc_continuous_test();
+  dac_test();
+  touch_test();
+
+  // Print to Serial1 to avoid buffering issues
+  Serial1.println("Peripheral Manager test done");
+}
+
+void loop() {}
diff --git a/tests/validation/periman/test_periman.py b/tests/validation/periman/test_periman.py
new file mode 100644
index 00000000000..2728abcef80
--- /dev/null
+++ b/tests/validation/periman/test_periman.py
@@ -0,0 +1,42 @@
+import logging
+
+
+def test_periman(dut):
+    LOGGER = logging.getLogger(__name__)
+    peripherals = [
+        "GPIO",
+        "SigmaDelta",
+        "LEDC",
+        "RMT",
+        "I2S",
+        "I2C",
+        "SPI",
+        "ADC_Oneshot",
+        "ADC_Continuous",
+        "DAC",
+        "Touch",
+    ]
+
+    pattern = rb"(?:\b\w+\b test: This should(?: not)? be printed|Peripheral Manager test done)"
+
+    while True:
+        try:
+            res = dut.expect(pattern, timeout=10)
+        except Exception as e:  # noqa: F841
+            assert False, "Could not detect end of test"
+
+        console_output = res.group(0).decode("utf-8")
+        peripheral = console_output.split()[0]
+
+        if "Peripheral Manager test done" in console_output:
+            break
+
+        if peripheral in peripherals:
+            if "not" in console_output:
+                assert False, f"Output printed when it should not after peripheral {peripheral}"
+            LOGGER.info(f"Correct output after peripheral: {peripheral}")
+            peripherals.remove(peripheral)
+        else:
+            assert False, f"Unknown peripheral: {peripheral}"
+
+    assert peripherals == [], f"Missing output after peripherals: {peripherals}"
diff --git a/tests/validation/psram/ci.json b/tests/validation/psram/ci.json
new file mode 100644
index 00000000000..999d3be953e
--- /dev/null
+++ b/tests/validation/psram/ci.json
@@ -0,0 +1,8 @@
+{
+  "platforms": {
+    "qemu": false
+  },
+  "requires": [
+    "CONFIG_SPIRAM=y"
+  ]
+}
diff --git a/tests/validation/psram/diagram.esp32s3.json b/tests/validation/psram/diagram.esp32s3.json
new file mode 100644
index 00000000000..837ff1eed33
--- /dev/null
+++ b/tests/validation/psram/diagram.esp32s3.json
@@ -0,0 +1,24 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-s3-devkitc-1",
+      "id": "esp",
+      "attrs": { "psramType": "octal" }
+    }
+  ],
+  "connections": [
+    [
+      "esp:TX",
+      "$serialMonitor:RX",
+      ""
+    ],
+    [
+      "esp:RX",
+      "$serialMonitor:TX",
+      ""
+    ]
+  ]
+}
diff --git a/tests/validation/psram/psram.ino b/tests/validation/psram/psram.ino
new file mode 100644
index 00000000000..7bf7bc11c5d
--- /dev/null
+++ b/tests/validation/psram/psram.ino
@@ -0,0 +1,128 @@
+#include <Arduino.h>
+#include <unity.h>
+
+#define MAX_TEST_SIZE 512 * 1024  // 512KB
+
+void *buf = NULL;
+uint32_t psram_size = 0;
+
+void psram_found(void) {
+  psram_size = ESP.getPsramSize();
+  TEST_ASSERT_TRUE(psram_size > 0);
+}
+
+void test_malloc_success(void) {
+  buf = ps_malloc(MAX_TEST_SIZE);
+  TEST_ASSERT_NOT_NULL(buf);
+  free(buf);
+  buf = NULL;
+}
+
+void test_calloc_success(void) {
+  buf = ps_calloc(MAX_TEST_SIZE, 1);
+  TEST_ASSERT_NOT_NULL(buf);
+  free(buf);
+  buf = NULL;
+}
+
+void test_realloc_success(void) {
+  buf = ps_malloc(MAX_TEST_SIZE);
+  TEST_ASSERT_NOT_NULL(buf);
+  buf = ps_realloc(buf, MAX_TEST_SIZE + 1024);
+  TEST_ASSERT_NOT_NULL(buf);
+  free(buf);
+  buf = NULL;
+}
+
+void test_malloc_fail(void) {
+  buf = ps_malloc(0xFFFFFFFF);
+  TEST_ASSERT_NULL(buf);
+}
+
+void test_memset_all_zeroes(void) {
+  memset(buf, 0, MAX_TEST_SIZE);
+  for (size_t i = 0; i < MAX_TEST_SIZE; i++) {
+    TEST_ASSERT_EQUAL(0, ((uint8_t *)buf)[i]);
+  }
+}
+
+void test_memset_all_ones(void) {
+  memset(buf, 0xFF, MAX_TEST_SIZE);
+  for (size_t i = 0; i < MAX_TEST_SIZE; i++) {
+    TEST_ASSERT_EQUAL(0xFF, ((uint8_t *)buf)[i]);
+  }
+}
+
+void test_memset_alternating(void) {
+  for (size_t i = 0; i < MAX_TEST_SIZE; i++) {
+    ((uint8_t *)buf)[i] = i % 2 == 0 ? 0x00 : 0xFF;
+  }
+  memset(buf, 0xAA, MAX_TEST_SIZE);
+  for (size_t i = 0; i < MAX_TEST_SIZE; i++) {
+    TEST_ASSERT_EQUAL(0xAA, ((uint8_t *)buf)[i]);
+  }
+}
+
+void test_memset_random(void) {
+  for (size_t i = 0; i < MAX_TEST_SIZE; i++) {
+    ((uint8_t *)buf)[i] = random(0, 256);
+  }
+  memset(buf, 0x55, MAX_TEST_SIZE);
+  for (size_t i = 0; i < MAX_TEST_SIZE; i++) {
+    TEST_ASSERT_EQUAL(0x55, ((uint8_t *)buf)[i]);
+  }
+}
+
+void test_memcpy(void) {
+  void *buf2 = malloc(1024);  // 1KB
+  TEST_ASSERT_NOT_NULL(buf2);
+  memset(buf, 0x55, MAX_TEST_SIZE);
+  memset(buf2, 0xAA, 1024);
+
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpointer-arith"
+
+  for (size_t i = 0; i < MAX_TEST_SIZE; i += 1024) {
+    memcpy(buf + i, buf2, 1024);
+  }
+
+  for (size_t i = 0; i < MAX_TEST_SIZE; i += 1024) {
+    TEST_ASSERT_NULL(memcmp(buf + i, buf2, 1024));
+  }
+
+#pragma GCC diagnostic pop
+
+  free(buf2);
+}
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  UNITY_BEGIN();
+  RUN_TEST(psram_found);
+
+  if (psram_size == 0) {
+    UNITY_END();
+    return;
+  }
+
+  RUN_TEST(test_malloc_success);
+  RUN_TEST(test_malloc_fail);
+  RUN_TEST(test_calloc_success);
+  RUN_TEST(test_realloc_success);
+  buf = ps_malloc(MAX_TEST_SIZE);
+  RUN_TEST(test_memset_all_zeroes);
+  RUN_TEST(test_memset_all_ones);
+  RUN_TEST(test_memset_alternating);
+#ifndef CONFIG_IDF_TARGET_ESP32P4
+  // These tests are taking too long on ESP32-P4 in Wokwi
+  RUN_TEST(test_memset_random);
+  RUN_TEST(test_memcpy);
+#endif
+  UNITY_END();
+}
+
+void loop() {}
diff --git a/tests/validation/psram/test_psram.py b/tests/validation/psram/test_psram.py
new file mode 100644
index 00000000000..7bd1d9d735d
--- /dev/null
+++ b/tests/validation/psram/test_psram.py
@@ -0,0 +1,2 @@
+def test_psram(dut):
+    dut.expect_unity_test_output(timeout=120)
diff --git a/tests/validation/timer/test_timer.py b/tests/validation/timer/test_timer.py
new file mode 100644
index 00000000000..9859c9bfbef
--- /dev/null
+++ b/tests/validation/timer/test_timer.py
@@ -0,0 +1,2 @@
+def test_timer(dut):
+    dut.expect_unity_test_output(timeout=240)
diff --git a/tests/validation/timer/timer.ino b/tests/validation/timer/timer.ino
new file mode 100644
index 00000000000..49ce2d2fb92
--- /dev/null
+++ b/tests/validation/timer/timer.ino
@@ -0,0 +1,132 @@
+/* HW Timer test */
+#include <unity.h>
+
+#define TIMER_FREQUENCY          4000000
+#define TIMER_FREQUENCY_XTAL_CLK 1000
+
+/*
+ * ESP32 - APB clk only (1kHz not possible)
+ * C3 - APB + XTAL clk
+ * S2 - APB + XTAL clk
+ * S3 - APB + XTAL clk
+ */
+
+static hw_timer_t *timer = NULL;
+static volatile bool alarm_flag;
+
+/* setUp / tearDown functions are intended to be called before / after each test. */
+void setUp(void) {
+  timer = timerBegin(TIMER_FREQUENCY);
+  if (timer == NULL) {
+    TEST_FAIL_MESSAGE("Timer init failed in setUp()");
+  }
+  timerStop(timer);
+  timerRestart(timer);
+}
+
+void tearDown(void) {
+  timerEnd(timer);
+}
+
+void ARDUINO_ISR_ATTR onTimer() {
+  alarm_flag = true;
+}
+
+void timer_interrupt_test(void) {
+
+  alarm_flag = false;
+  timerAttachInterrupt(timer, &onTimer);
+  timerAlarm(timer, (1.2 * TIMER_FREQUENCY), true, 0);
+  timerStart(timer);
+
+  delay(2000);
+
+  TEST_ASSERT_EQUAL(true, alarm_flag);
+
+  timerStop(timer);
+  timerRestart(timer);
+  alarm_flag = false;
+  timerDetachInterrupt(timer);
+  timerStart(timer);
+
+  delay(2000);
+  TEST_ASSERT_EQUAL(false, alarm_flag);
+}
+
+void timer_divider_test(void) {
+
+  uint64_t time_val;
+  uint64_t comp_time_val;
+
+  timerStart(timer);
+
+  delay(1000);
+  time_val = timerRead(timer);
+
+  // compare divider  16 and 8, value should be double
+  timerEnd(timer);
+
+  timer = timerBegin(2 * TIMER_FREQUENCY);
+  if (timer == NULL) {
+    TEST_FAIL_MESSAGE("Timer init failed!");
+  }
+  timerRestart(timer);
+  delay(1000);
+  comp_time_val = timerRead(timer);
+
+  TEST_ASSERT_INT_WITHIN(4000, 4000000, time_val);
+  TEST_ASSERT_INT_WITHIN(8000, 8000000, comp_time_val);
+
+  // divider is 256, value should be 2^4
+  timerEnd(timer);
+
+  timer = timerBegin(TIMER_FREQUENCY / 16);
+  if (timer == NULL) {
+    TEST_FAIL_MESSAGE("Timer init failed!");
+  }
+  timerRestart(timer);
+  delay(1000);
+  comp_time_val = timerRead(timer);
+
+  TEST_ASSERT_INT_WITHIN(4000, 4000000, time_val);
+  TEST_ASSERT_INT_WITHIN(2500, 250000, comp_time_val);
+}
+
+void timer_read_test(void) {
+
+  uint64_t set_timer_val = 0xFF;
+  uint64_t get_timer_val = 0;
+
+  timerWrite(timer, set_timer_val);
+  get_timer_val = timerRead(timer);
+
+  TEST_ASSERT_EQUAL(set_timer_val, get_timer_val);
+}
+
+void timer_clock_select_test(void) {
+  // Set timer frequency that can be achieved using XTAL clock source (autoselected)
+  timer = timerBegin(TIMER_FREQUENCY_XTAL_CLK);
+
+  uint32_t resolution = timerGetFrequency(timer);
+  TEST_ASSERT_EQUAL(TIMER_FREQUENCY_XTAL_CLK, resolution);
+}
+
+void setup() {
+
+  // Open serial communications and wait for port to open:
+  Serial.begin(115200);
+  while (!Serial) {
+    ;
+  }
+
+  UNITY_BEGIN();
+  RUN_TEST(timer_read_test);
+  RUN_TEST(timer_interrupt_test);
+  RUN_TEST(timer_divider_test);
+#if !CONFIG_IDF_TARGET_ESP32
+  RUN_TEST(timer_clock_select_test);
+#endif
+  UNITY_END();
+}
+
+void loop() {}
diff --git a/tests/validation/touch/ci.json b/tests/validation/touch/ci.json
new file mode 100644
index 00000000000..855e9bd964d
--- /dev/null
+++ b/tests/validation/touch/ci.json
@@ -0,0 +1,9 @@
+{
+  "platforms": {
+    "qemu": false,
+    "wokwi": false
+  },
+  "requires": [
+    "CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y"
+  ]
+}
diff --git a/tests/validation/touch/test_touch.py b/tests/validation/touch/test_touch.py
new file mode 100644
index 00000000000..dc80b6dfaa4
--- /dev/null
+++ b/tests/validation/touch/test_touch.py
@@ -0,0 +1,2 @@
+def test_touch(dut):
+    dut.expect_unity_test_output(timeout=240)
diff --git a/tests/validation/touch/touch.ino b/tests/validation/touch/touch.ino
new file mode 100644
index 00000000000..97aac8a65e6
--- /dev/null
+++ b/tests/validation/touch/touch.ino
@@ -0,0 +1,202 @@
+#include <unity.h>
+#include "soc/soc_caps.h"
+#include "driver/touch_pad.h"
+
+#if SOC_TOUCH_SENSOR_VERSION == 3
+#include "hal/touch_sensor_ll.h"
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32
+
+#define TEST_TOUCH_CHANNEL (9)
+static touch_pad_t touch_list[TEST_TOUCH_CHANNEL] = {
+  TOUCH_PAD_NUM0,
+  //TOUCH_PAD_NUM1 is GPIO0, for download.
+  TOUCH_PAD_NUM2, TOUCH_PAD_NUM3, TOUCH_PAD_NUM4, TOUCH_PAD_NUM5, TOUCH_PAD_NUM6, TOUCH_PAD_NUM7, TOUCH_PAD_NUM8, TOUCH_PAD_NUM9
+};
+
+uint8_t TOUCH_GPIOS[] = {4, 2, 15, 13, 12, 14, 27, 33, 32};
+
+#define NO_TOUCH_GPIO 25
+
+#elif (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3)
+
+#define TEST_TOUCH_CHANNEL (12)  //14
+static touch_pad_t touch_list[TEST_TOUCH_CHANNEL] = {
+  TOUCH_PAD_NUM1, TOUCH_PAD_NUM2, TOUCH_PAD_NUM3,  TOUCH_PAD_NUM4,  TOUCH_PAD_NUM5, TOUCH_PAD_NUM6, TOUCH_PAD_NUM7,
+  TOUCH_PAD_NUM8, TOUCH_PAD_NUM9, TOUCH_PAD_NUM10, TOUCH_PAD_NUM11, TOUCH_PAD_NUM12
+  //TOUCH_PAD_NUM13, //Wrong reading
+  //TOUCH_PAD_NUM14
+};
+
+uint8_t TOUCH_GPIOS[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 /*,13,14*/};
+
+#define NO_TOUCH_GPIO 17
+
+#else  //ESP32P4
+
+#define TEST_TOUCH_CHANNEL (5)  //14
+static touch_pad_t touch_list[TEST_TOUCH_CHANNEL] = {
+  TOUCH_PAD_NUM0, TOUCH_PAD_NUM1, TOUCH_PAD_NUM2,
+  TOUCH_PAD_NUM3, TOUCH_PAD_NUM4, /* TOUCH_PAD_NUM5, TOUCH_PAD_NUM6,
+  TOUCH_PAD_NUM7, TOUCH_PAD_NUM8, TOUCH_PAD_NUM9, TOUCH_PAD_NUM10, TOUCH_PAD_NUM11, TOUCH_PAD_NUM12, TOUCH_PAD_NUM13*/
+};
+
+uint8_t TOUCH_GPIOS[] = {2, 3, 4, 5, 6 /*, 7, 8, 9, 10, 11, 12 ,13, 14, 15*/};
+
+#define NO_TOUCH_GPIO 17
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32
+#define RELEASED_VALUE      75  //75+ read value to pass test
+#define PRESSED_VALUE       20  //20- read value to pass test
+#define INTERRUPT_THRESHOLD 40
+#elif CONFIG_IDF_TARGET_ESP32S2
+#define RELEASED_VALUE      10000  //10000- read value to pass test
+#define PRESSED_VALUE       42000  //40000+ read value to pass test
+#define INTERRUPT_THRESHOLD 30000
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define RELEASED_VALUE      25000  //25000- read value to pass test
+#define PRESSED_VALUE       90000  //90000+ read value to pass test
+#define INTERRUPT_THRESHOLD 80000
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define PRESSED_VALUE_DIFFERENCE 200  //200+ read value difference against the unpressed value
+#define INTERRUPT_THRESHOLD      0    // Use benchmarked threshold
+#else
+#error Test not currently supported on this chip. Please adjust and try again!
+#endif
+
+bool touch1detected = false;
+bool touch2detected = false;
+
+void gotTouch1() {
+  touch1detected = true;
+}
+
+void gotTouch2() {
+  touch2detected = true;
+}
+
+/*
+ * Change the slope to get larger value from touch sensor. (Capacitor for ESP32P4)
+ */
+static void test_press_fake(touch_pad_t pad_num) {
+#if SOC_TOUCH_SENSOR_VERSION <= 2
+  touch_pad_set_cnt_mode(pad_num, TOUCH_PAD_SLOPE_1, TOUCH_PAD_TIE_OPT_DEFAULT);
+#else
+  touch_ll_set_internal_capacitor(0x7f);
+#endif
+}
+
+/*
+ * Change the slope to get smaller value from touch sensor. (Capacitor for ESP32P4)
+ */
+static void test_release_fake(touch_pad_t pad_num) {
+#if SOC_TOUCH_SENSOR_VERSION <= 2
+  touch_pad_set_cnt_mode(pad_num, TOUCH_PAD_SLOPE_7, TOUCH_PAD_TIE_OPT_DEFAULT);
+#else
+  touch_ll_set_internal_capacitor(0);
+#endif
+}
+
+/* These functions are intended to be called before and after each test. */
+void setUp(void) {}
+
+void tearDown(void) {
+  for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {
+    test_release_fake(touch_list[i]);
+  }
+  delay(100);
+}
+
+/*
+ * Test Touch read on all available channels - compare values if reading is right
+ */
+void test_touch_read(void) {
+
+#if SOC_TOUCH_SENSOR_VERSION <= 2
+  //TEST RELEASE STATE
+  for (int i = 0; i < sizeof(TOUCH_GPIOS); i++) {
+#ifdef CONFIG_IDF_TARGET_ESP32
+    TEST_ASSERT_GREATER_THAN(RELEASED_VALUE, touchRead(TOUCH_GPIOS[i]));
+#else
+    TEST_ASSERT_LESS_THAN(RELEASED_VALUE, touchRead(TOUCH_GPIOS[i]));
+#endif
+  }
+
+  // TEST PRESS STATE
+  for (int j = 0; j < TEST_TOUCH_CHANNEL; j++) {
+    test_press_fake(touch_list[j]);
+  }
+  delay(100);
+
+  for (int k = 0; k < sizeof(TOUCH_GPIOS); k++) {
+#ifdef CONFIG_IDF_TARGET_ESP32
+    TEST_ASSERT_LESS_THAN(PRESSED_VALUE, touchRead(TOUCH_GPIOS[k]));
+#else
+    TEST_ASSERT_GREATER_THAN(PRESSED_VALUE, touchRead(TOUCH_GPIOS[k]));
+#endif
+  }
+#else  //TOUCH V3
+  //TEST RELEASE STATE
+  touch_value_t touch_unpressed[sizeof(TOUCH_GPIOS)];
+  for (int i = 0; i < sizeof(TOUCH_GPIOS); i++) {
+    touch_unpressed[i] = touchRead(TOUCH_GPIOS[i]);
+  }
+
+  // TEST PRESS STATE
+  for (int j = 0; j < TEST_TOUCH_CHANNEL; j++) {
+    test_press_fake(touch_list[j]);
+  }
+  delay(100);
+
+  touch_value_t touch_pressed[sizeof(TOUCH_GPIOS)];
+  for (int k = 0; k < sizeof(TOUCH_GPIOS); k++) {
+    touch_pressed[k] = touchRead(TOUCH_GPIOS[k]);
+  }
+
+  // COMPARE PRESSED > UNPRESSED
+  for (int l = 0; l < sizeof(TOUCH_GPIOS); l++) {
+    TEST_ASSERT_GREATER_THAN((touch_unpressed[l] + PRESSED_VALUE_DIFFERENCE), touch_pressed[l]);
+  }
+#endif
+}
+
+void test_touch_interrtupt(void) {
+
+  touchAttachInterrupt(TOUCH_GPIOS[0], gotTouch1, INTERRUPT_THRESHOLD);
+  touchAttachInterrupt(TOUCH_GPIOS[1], gotTouch2, INTERRUPT_THRESHOLD);
+
+  test_press_fake(touch_list[0]);
+  test_press_fake(touch_list[1]);
+
+  delay(300);
+
+  touchDetachInterrupt(TOUCH_GPIOS[0]);
+  touchDetachInterrupt(TOUCH_GPIOS[1]);
+
+  TEST_ASSERT_TRUE(touch1detected);
+  TEST_ASSERT_TRUE(touch2detected);
+}
+
+void test_touch_errors(void) {
+
+  TEST_ASSERT_FALSE(touchRead(NO_TOUCH_GPIO));
+}
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    ;
+  }
+
+  UNITY_BEGIN();
+  RUN_TEST(test_touch_read);
+  RUN_TEST(test_touch_interrtupt);
+  RUN_TEST(test_touch_errors);
+  UNITY_END();
+}
+
+void loop() {
+  delay(10);
+}
diff --git a/tests/validation/uart/ci.json b/tests/validation/uart/ci.json
new file mode 100644
index 00000000000..54da33b6176
--- /dev/null
+++ b/tests/validation/uart/ci.json
@@ -0,0 +1,5 @@
+{
+  "platforms": {
+    "qemu": false
+  }
+}
diff --git a/tests/validation/uart/diagram.esp32.json b/tests/validation/uart/diagram.esp32.json
new file mode 100644
index 00000000000..c2fbd952fd0
--- /dev/null
+++ b/tests/validation/uart/diagram.esp32.json
@@ -0,0 +1,24 @@
+{
+  "version": 1,
+  "author": "lucasssvaz",
+  "editor": "wokwi",
+  "parts": [
+    {
+      "type": "board-esp32-devkit-c-v4",
+      "id": "esp",
+      "attrs": { "cpuFrequency": "120" }
+    }
+  ],
+  "connections": [
+    [
+      "esp:TX",
+      "$serialMonitor:RX",
+      ""
+    ],
+    [
+      "esp:RX",
+      "$serialMonitor:TX",
+      ""
+    ]
+  ]
+}
diff --git a/tests/validation/uart/test_uart.py b/tests/validation/uart/test_uart.py
new file mode 100644
index 00000000000..f4a6b759845
--- /dev/null
+++ b/tests/validation/uart/test_uart.py
@@ -0,0 +1,2 @@
+def test_uart(dut):
+    dut.expect_unity_test_output(timeout=120)
diff --git a/tests/validation/uart/uart.ino b/tests/validation/uart/uart.ino
new file mode 100644
index 00000000000..794fc9affc2
--- /dev/null
+++ b/tests/validation/uart/uart.ino
@@ -0,0 +1,556 @@
+/* UART test
+ *
+ * This test is using UART0 (Serial) only for reporting test status and helping with the auto
+ * baudrate detection test.
+ * The other serials are used for testing.
+ */
+
+// Default pins:
+//          |  Name   | ESP32 | S2 | S3 | C3 | C6 | H2 | P4 |
+// UART0 RX | SOC_RX0 |   3   | 44 | 44 | 20 | 17 | 23 | 38 |
+// UART0 TX | SOC_TX0 |   1   | 43 | 43 | 21 | 16 | 24 | 37 |
+// UART1 RX |   RX1   |  26   |  4 | 15 | 18 |  4 |  0 | 11 |
+// UART1 TX |   TX1   |  27   |  5 | 16 | 19 |  5 |  1 | 10 |
+// UART2 RX |   RX2   |   4   | -- | 19 | -- | -- | -- | -- |
+// UART2 TX |   TX2   |  25   | -- | 20 | -- | -- | -- | -- |
+
+/*
+ * For each UART:
+ *
+ *           terminal
+ *          |       ^
+ *          v UART0 |
+ *          RX  ^  TX
+ *              |
+ *        report status
+ *              |
+ *         TX <---> RX
+ *            UARTx
+ */
+
+#include <vector>
+#include <unity.h>
+#include "HardwareSerial.h"
+#include "esp_rom_gpio.h"
+#include "Wire.h"
+
+/* Utility defines */
+
+#define TEST_UART_NUM (uart_test_configs.size())
+
+/* Utility classes */
+
+class UARTTestConfig {
+public:
+  int uart_num;
+  HardwareSerial &serial;
+  int peeked_char;
+  int8_t default_rx_pin;
+  int8_t default_tx_pin;
+  String recv_msg;
+
+  UARTTestConfig(int num, HardwareSerial &serial_ref, int8_t rx_pin, int8_t tx_pin)
+    : uart_num(num), serial(serial_ref), peeked_char(-1), default_rx_pin(rx_pin), default_tx_pin(tx_pin), recv_msg("") {}
+
+  void begin(unsigned long baudrate) {
+    // pinMode will force enabling the internal pullup resistor (IDF 5.3.2 Change)
+    pinMode(default_rx_pin, INPUT_PULLUP);
+    serial.begin(baudrate, SERIAL_8N1, default_rx_pin, default_tx_pin);
+    while (!serial) {
+      delay(10);
+    }
+  }
+
+  void end() {
+    serial.end();
+  }
+
+  void reset_buffers() {
+    recv_msg = "";
+    peeked_char = -1;
+  }
+
+  void transmit_and_check_msg(const String &msg_append, bool perform_assert = true) {
+    reset_buffers();
+    delay(100);
+    serial.print("Hello from Serial" + String(uart_num) + " " + msg_append);
+    serial.flush();
+    delay(100);
+    if (perform_assert) {
+      TEST_ASSERT_EQUAL_STRING(("Hello from Serial" + String(uart_num) + " " + msg_append).c_str(), recv_msg.c_str());
+      log_d("UART%d received message: %s\n", uart_num, recv_msg.c_str());
+    }
+  }
+
+  void onReceive() {
+    char c;
+    size_t available = serial.available();
+    if (peeked_char == -1) {
+      peeked_char = serial.peek();
+    }
+    while (available--) {
+      c = (char)serial.read();
+      recv_msg += c;
+    }
+  }
+};
+
+/* Utility global variables */
+
+[[maybe_unused]]
+static const int NEW_RX1 = 9;
+[[maybe_unused]]
+static const int NEW_TX1 = 10;
+std::vector<UARTTestConfig *> uart_test_configs;
+
+/* Utility functions */
+
+extern "C" int8_t uart_get_RxPin(uint8_t uart_num);
+extern "C" int8_t uart_get_TxPin(uint8_t uart_num);
+
+/* Tasks */
+
+// This task is used to send a message after a delay to test the auto baudrate detection
+void task_delayed_msg(void *pvParameters) {
+  HardwareSerial &selected_serial = uart_test_configs.size() == 1 ? Serial : Serial1;
+  delay(2000);
+  selected_serial.println("Hello to detect baudrate");
+  selected_serial.flush();
+  vTaskDelete(NULL);
+}
+
+/* Unity functions */
+
+// This function is automatically called by unity before each test is run
+void setUp(void) {
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    //log_d("Setup internal loop-back from and back to UART%d TX >> UART%d RX", config.uart_num, config.uart_num);
+    config.begin(115200);
+    config.serial.onReceive([&config]() {
+      config.onReceive();
+    });
+    uart_internal_loopback(config.uart_num, uart_get_RxPin(config.uart_num));
+  }
+}
+
+// This function is automatically called by unity after each test is run
+void tearDown(void) {
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    config.end();
+  }
+}
+
+/* Test functions */
+
+// This test checks if a message can be transmitted and received correctly using the default settings
+void basic_transmission_test(void) {
+  log_d("Performing basic transmission test");
+
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    config.transmit_and_check_msg("");
+  }
+
+  Serial.println("Basic transmission test successful");
+}
+
+// This test checks if the baudrate can be changed and if the message can be transmitted and received correctly after the change
+void change_baudrate_test(void) {
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    log_d("Changing baudrate of UART%d to 9600", config.uart_num);
+
+    //Baudrate error should be within 2% of the target baudrate
+    config.serial.updateBaudRate(9600);
+    TEST_ASSERT_UINT_WITHIN(192, 9600, config.serial.baudRate());
+
+    log_d("Sending string on UART%d using 9600 baudrate", config.uart_num);
+    config.transmit_and_check_msg("using 9600 baudrate");
+
+    config.serial.begin(115200);
+    TEST_ASSERT_UINT_WITHIN(2304, 115200, config.serial.baudRate());
+
+    log_d("Sending string on UART%d using 115200 baudrate", config.uart_num);
+    config.transmit_and_check_msg("using 115200 baudrate");
+  }
+
+  Serial.println("Change baudrate test successful");
+}
+
+// This test checks if the buffers can be resized properly
+void resize_buffers_test(void) {
+  size_t ret;
+
+  log_d("Trying to resize RX buffer while running.");
+  ret = Serial1.setRxBufferSize(256);
+  TEST_ASSERT_EQUAL(0, ret);
+
+  log_d("Trying to resize TX buffer while running.");
+  ret = Serial1.setTxBufferSize(256);
+  TEST_ASSERT_EQUAL(0, ret);
+
+  Serial1.end();
+
+  log_d("Trying to resize RX buffer while stopped.");
+  ret = Serial1.setRxBufferSize(256);
+  TEST_ASSERT_EQUAL(256, ret);
+
+  log_d("Trying to resize TX buffer while stopped.");
+  ret = Serial1.setTxBufferSize(256);
+  TEST_ASSERT_EQUAL(256, ret);
+
+  Serial.println("Buffer resize test successful");
+}
+
+// This test checks if the begin function can be called when the UART is already running
+void begin_when_running_test(void) {
+  log_d("Trying to set up serial twice");
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    // Calling twice should not crash
+    config.begin(115200);
+    config.begin(115200);
+  }
+  Serial.println("Begin when running test successful");
+}
+
+// This test checks if the end function can be called when the UART is already stopped
+void end_when_stopped_test(void) {
+  log_d("Trying to end serial twice");
+
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    // Calling twice should not crash
+    config.end();
+    config.end();
+  }
+
+  Serial.println("End when stopped test successful");
+}
+
+// This test checks if all the UART methods work when the UART is running
+void enabled_uart_calls_test(void) {
+  bool boolean_ret;
+  long int integer_ret;
+  uint8_t test_buf[1];
+
+  log_d("Checking if Serial 1 can set the RX timeout while running");
+  boolean_ret = Serial1.setRxTimeout(1);
+  TEST_ASSERT_EQUAL(true, boolean_ret);
+
+  log_d("Checking if Serial 1 can set the RX FIFO full interrupt threshold while running");
+  boolean_ret = Serial1.setRxFIFOFull(120);
+  TEST_ASSERT_EQUAL(true, boolean_ret);
+
+  log_d("Checking if Serial 1 is writable while running");
+  boolean_ret = Serial1.availableForWrite();
+  TEST_ASSERT_EQUAL(true, boolean_ret);
+
+  log_d("Checking if Serial 1 is peekable while running");
+  TEST_ASSERT_GREATER_OR_EQUAL(0, uart_test_configs[0]->peeked_char);
+
+  log_d("Checking if Serial 1 can read bytes while running");
+  integer_ret = Serial1.readBytes(test_buf, 1);
+  TEST_ASSERT_GREATER_OR_EQUAL(0, integer_ret);
+
+  log_d("Checking if Serial 1 can set the flow control while running");
+  boolean_ret = Serial1.setHwFlowCtrlMode(UART_HW_FLOWCTRL_DISABLE, 64);
+  TEST_ASSERT_EQUAL(true, boolean_ret);
+
+  log_d("Checking if Serial 1 can set the mode while running");
+  boolean_ret = Serial1.setMode(UART_MODE_UART);
+  TEST_ASSERT_EQUAL(true, boolean_ret);
+
+  // Tests without return values. Just check for crashes.
+
+  log_d("Checking if Serial 1 event queue can be reset while running");
+  Serial1.eventQueueReset();
+
+  log_d("Checking if Serial 1 debug output can be enabled while running");
+  Serial1.setDebugOutput(true);
+  Serial1.setDebugOutput(false);
+
+  log_d("Checking if Serial 1 RX can be inverted while running");
+  Serial1.setRxInvert(true);
+  Serial1.setRxInvert(false);
+
+  Serial.println("Enabled UART calls test successful");
+}
+
+// This test checks if all the UART methods work when the UART is stopped
+void disabled_uart_calls_test(void) {
+  bool boolean_ret;
+  int integer_ret;
+  uint8_t test_buf[1];
+
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    config.end();
+  }
+
+  log_d("Checking if Serial 1 can set the RX timeout when stopped");
+  boolean_ret = Serial1.setRxTimeout(1);
+  TEST_ASSERT_EQUAL(false, boolean_ret);
+
+  log_d("Checking if Serial 1 can set the RX FIFO full interrupt threshold when stopped");
+  boolean_ret = Serial1.setRxFIFOFull(128);
+  TEST_ASSERT_EQUAL(false, boolean_ret);
+
+  log_d("Checking if Serial 1 is available when stopped");
+  boolean_ret = Serial1.available();
+  TEST_ASSERT_EQUAL(false, boolean_ret);
+
+  log_d("Checking if Serial 1 is writable when stopped");
+  boolean_ret = Serial1.availableForWrite();
+  TEST_ASSERT_EQUAL(false, boolean_ret);
+
+  log_d("Checking if Serial 1 is peekable when stopped");
+  integer_ret = Serial1.peek();
+  TEST_ASSERT_EQUAL(-1, integer_ret);
+
+  log_d("Checking if Serial 1 is readable when stopped");
+  integer_ret = Serial1.read();
+  TEST_ASSERT_EQUAL(-1, integer_ret);
+
+  log_d("Checking if Serial 1 can read bytes when stopped");
+  integer_ret = Serial1.readBytes(test_buf, 1);
+  TEST_ASSERT_EQUAL(0, integer_ret);
+
+  log_d("Checking if Serial 1 can retrieve the baudrate when stopped");
+  integer_ret = Serial1.baudRate();
+  TEST_ASSERT_EQUAL(0, integer_ret);
+
+  log_d("Checking if Serial 1 can set the flow control when stopped");
+  boolean_ret = Serial1.setHwFlowCtrlMode(UART_HW_FLOWCTRL_DISABLE, 64);
+  TEST_ASSERT_EQUAL(false, boolean_ret);
+
+  log_d("Checking if Serial 1 can set the mode when stopped");
+  boolean_ret = Serial1.setMode(UART_MODE_UART);
+  TEST_ASSERT_EQUAL(false, boolean_ret);
+
+  log_d("Checking if Serial 1 set the baudrate when stopped");
+  Serial1.updateBaudRate(9600);
+  integer_ret = Serial1.baudRate();
+  TEST_ASSERT_EQUAL(0, integer_ret);
+
+  // Tests without return values. Just check for crashes.
+
+  log_d("Checking if Serial 1 event queue can be reset when stopped");
+  Serial1.eventQueueReset();
+
+  log_d("Checking if Serial 1 can be flushed when stopped");
+  Serial1.flush();
+
+  log_d("Checking if Serial 1 debug output can be enabled when stopped");
+  Serial1.setDebugOutput(true);
+  Serial1.setDebugOutput(false);
+
+  log_d("Checking if Serial 1 RX can be inverted when stopped");
+  Serial1.setRxInvert(true);
+  Serial1.setRxInvert(false);
+
+  Serial.println("Disabled UART calls test successful");
+}
+
+// This test checks if the pins can be changed and if the message can be transmitted and received correctly after the change
+void change_pins_test(void) {
+  log_d("Disabling UART loopback");
+
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    esp_rom_gpio_connect_out_signal(config.default_rx_pin, SIG_GPIO_OUT_IDX, false, false);
+  }
+
+  log_d("Swapping UART pins and testing transmission");
+
+  if (TEST_UART_NUM == 1) {
+    UARTTestConfig &config = *uart_test_configs[0];
+    // pinMode will force enabling the internal pullup resistor (IDF 5.3.2 Change)
+    pinMode(NEW_RX1, INPUT_PULLUP);
+    config.serial.setPins(NEW_RX1, NEW_TX1);
+    TEST_ASSERT_EQUAL(NEW_RX1, uart_get_RxPin(config.uart_num));
+    TEST_ASSERT_EQUAL(NEW_TX1, uart_get_TxPin(config.uart_num));
+
+    uart_internal_loopback(config.uart_num, NEW_RX1);
+    config.transmit_and_check_msg("using new pins");
+  } else {
+    for (int i = 0; i < TEST_UART_NUM; i++) {
+      UARTTestConfig &config = *uart_test_configs[i];
+      UARTTestConfig &next_uart = *uart_test_configs[(i + 1) % TEST_UART_NUM];
+      config.serial.setPins(next_uart.default_rx_pin, next_uart.default_tx_pin);
+      TEST_ASSERT_EQUAL(uart_get_RxPin(config.uart_num), next_uart.default_rx_pin);
+      TEST_ASSERT_EQUAL(uart_get_TxPin(config.uart_num), next_uart.default_tx_pin);
+
+      uart_internal_loopback(config.uart_num, next_uart.default_rx_pin);
+      config.transmit_and_check_msg("using new pins");
+    }
+  }
+
+  Serial.println("Change pins test successful");
+}
+
+// This test checks if the auto baudrate detection works on ESP32 and ESP32-S2
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+void auto_baudrate_test(void) {
+  log_d("Starting auto baudrate test");
+
+  HardwareSerial *selected_serial;
+  unsigned long baudrate;
+
+  log_d("Stopping test serial. Using Serial2 for ESP32 and Serial1 for ESP32-S2.");
+
+  if (TEST_UART_NUM == 1) {
+    selected_serial = &Serial1;
+    // UART1 pins were swapped because of ESP32-P4
+    uart_internal_loopback(0, /*RX1*/ TX1);
+  } else {
+#ifdef RX2
+    selected_serial = &Serial2;
+    uart_internal_loopback(1, RX2);
+#endif
+  }
+
+  //selected_serial->end(false);
+
+  log_d("Starting delayed task to send message");
+
+  xTaskCreate(task_delayed_msg, "task_delayed_msg", 2048, NULL, 2, NULL);
+
+  log_d("Starting serial with auto baudrate detection");
+
+  selected_serial->begin(0);
+  baudrate = selected_serial->baudRate();
+
+  if (TEST_UART_NUM == 1) {
+    Serial.end();
+    Serial.begin(115200);
+  }
+
+  TEST_ASSERT_UINT_WITHIN(2304, 115200, baudrate);
+
+  Serial.println("Auto baudrate test successful");
+}
+#endif
+
+// This test checks if the peripheral manager can properly manage UART pins
+void periman_test(void) {
+  log_d("Checking if peripheral manager can properly manage UART pins");
+
+  log_d("Setting up I2C on the same pins as UART");
+
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    Wire.begin(config.default_rx_pin, config.default_tx_pin);
+    config.recv_msg = "";
+
+    log_d("Trying to send message using UART%d with I2C enabled", config.uart_num);
+    config.transmit_and_check_msg("while used by I2C", false);
+    TEST_ASSERT_EQUAL_STRING("", config.recv_msg.c_str());
+
+    log_d("Disabling I2C and re-enabling UART%d", config.uart_num);
+
+    config.serial.setPins(config.default_rx_pin, config.default_tx_pin);
+    uart_internal_loopback(config.uart_num, config.default_rx_pin);
+
+    log_d("Trying to send message using UART%d with I2C disabled", config.uart_num);
+    config.transmit_and_check_msg("while I2C is disabled");
+  }
+
+  Serial.println("Peripheral manager test successful");
+}
+
+// This test checks if messages can be transmitted and received correctly after changing the CPU frequency
+void change_cpu_frequency_test(void) {
+  uint32_t old_freq = getCpuFrequencyMhz();
+  uint32_t new_freq = getXtalFrequencyMhz();
+
+  log_d("Changing CPU frequency from %dMHz to %dMHz", old_freq, new_freq);
+  Serial.flush();
+  setCpuFrequencyMhz(new_freq);
+
+  Serial.updateBaudRate(115200);
+
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    log_d("Trying to send message with the new CPU frequency on UART%d", config.uart_num);
+    config.transmit_and_check_msg("with new CPU frequency");
+  }
+
+  log_d("Changing CPU frequency back to %dMHz", old_freq);
+  Serial.flush();
+  setCpuFrequencyMhz(old_freq);
+
+  Serial.updateBaudRate(115200);
+
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    log_d("Trying to send message with the original CPU frequency on UART%d", config.uart_num);
+    config.transmit_and_check_msg("with the original CPU frequency");
+  }
+
+  Serial.println("Change CPU frequency test successful");
+}
+
+/* Main functions */
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    delay(10);
+  }
+
+  uart_test_configs = {
+#if SOC_UART_HP_NUM >= 2 && defined(RX1) && defined(TX1)
+    // inverting RX1<->TX1 because ESP32-P4 has a problem with loopback on RX1 :: GPIO11 <-- UART_TX SGINAL
+    new UARTTestConfig(1, Serial1, TX1, RX1),
+#endif
+#if SOC_UART_HP_NUM >= 3 && defined(RX2) && defined(TX2)
+    new UARTTestConfig(2, Serial2, RX2, TX2),
+#endif
+#if SOC_UART_HP_NUM >= 4 && defined(RX3) && defined(TX3)
+    new UARTTestConfig(3, Serial3, RX3, TX3),
+#endif
+#if SOC_UART_HP_NUM >= 5 && defined(RX4) && defined(TX4)
+    new UARTTestConfig(4, Serial4, RX4, TX4)
+#endif
+  };
+
+  if (TEST_UART_NUM == 0) {
+    log_e("This test requires at least one UART besides UART0 configured");
+    abort();
+  }
+
+  log_d("TEST_UART_NUM = %d", TEST_UART_NUM);
+
+  for (auto *ref : uart_test_configs) {
+    UARTTestConfig &config = *ref;
+    config.begin(115200);
+    log_d("Setup internal loop-back from and back to UART%d TX >> UART%d RX", config.uart_num, config.uart_num);
+    config.serial.onReceive([&config]() {
+      config.onReceive();
+    });
+    uart_internal_loopback(config.uart_num, uart_get_RxPin(config.uart_num));
+  }
+
+  log_d("Setup done. Starting tests");
+
+  UNITY_BEGIN();
+  RUN_TEST(begin_when_running_test);
+  RUN_TEST(basic_transmission_test);
+  RUN_TEST(resize_buffers_test);
+  RUN_TEST(change_baudrate_test);
+  RUN_TEST(change_cpu_frequency_test);
+  RUN_TEST(disabled_uart_calls_test);
+  RUN_TEST(enabled_uart_calls_test);
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+  RUN_TEST(auto_baudrate_test);
+#endif
+  RUN_TEST(periman_test);
+  RUN_TEST(change_pins_test);
+  RUN_TEST(end_when_stopped_test);
+  UNITY_END();
+}
+
+void loop() {}
diff --git a/tests/validation/unity/test_unity.py b/tests/validation/unity/test_unity.py
new file mode 100644
index 00000000000..a5a391cc5af
--- /dev/null
+++ b/tests/validation/unity/test_unity.py
@@ -0,0 +1,2 @@
+def test_unity(dut):
+    dut.expect_unity_test_output(timeout=240)
diff --git a/tests/validation/unity/unity.ino b/tests/validation/unity/unity.ino
new file mode 100644
index 00000000000..a0fc7f683d9
--- /dev/null
+++ b/tests/validation/unity/unity.ino
@@ -0,0 +1,28 @@
+#include <unity.h>
+
+/* These functions are intended to be called before and after each test. */
+void setUp(void) {}
+
+void tearDown(void) {}
+
+void test_pass(void) {
+  TEST_ASSERT_EQUAL(1, 1);
+}
+
+void test_fail(void) {
+  TEST_ASSERT_EQUAL(1, 1);
+}
+
+void setup() {
+  Serial.begin(115200);
+  while (!Serial) {
+    ;
+  }
+
+  UNITY_BEGIN();
+  RUN_TEST(test_pass);
+  RUN_TEST(test_fail);
+  UNITY_END();
+}
+
+void loop() {}
diff --git a/tests/validation/wifi/ci.json b/tests/validation/wifi/ci.json
new file mode 100644
index 00000000000..36e91b221cb
--- /dev/null
+++ b/tests/validation/wifi/ci.json
@@ -0,0 +1,27 @@
+{
+  "extra_tags": [
+    "wifi"
+  ],
+  "fqbn": {
+    "esp32": [
+      "espressif:esp32:esp32:PSRAM=enabled,PartitionScheme=huge_app,FlashMode=dio",
+      "espressif:esp32:esp32:PSRAM=disabled,PartitionScheme=huge_app,FlashMode=dio"
+    ],
+    "esp32s2": [
+      "espressif:esp32:esp32s2:PSRAM=enabled,PartitionScheme=huge_app,FlashMode=dio",
+      "espressif:esp32:esp32s2:PSRAM=disabled,PartitionScheme=huge_app,FlashMode=dio"
+    ],
+    "esp32s3": [
+      "espressif:esp32:esp32s3:PSRAM=opi,USBMode=default,PartitionScheme=huge_app,FlashMode=qio",
+      "espressif:esp32:esp32s3:PSRAM=disabled,USBMode=default,PartitionScheme=huge_app,FlashMode=qio",
+      "espressif:esp32:esp32s3:PSRAM=enabled,USBMode=default,PartitionScheme=huge_app,FlashMode=qio"
+    ]
+  },
+  "platforms": {
+    "hardware": false,
+    "qemu": false
+  },
+  "requires": [
+    "CONFIG_SOC_WIFI_SUPPORTED=y"
+  ]
+}
diff --git a/tests/validation/wifi/test_wifi.py b/tests/validation/wifi/test_wifi.py
new file mode 100644
index 00000000000..5049aae7b85
--- /dev/null
+++ b/tests/validation/wifi/test_wifi.py
@@ -0,0 +1,16 @@
+import logging
+
+
+def test_wifi(dut):
+    LOGGER = logging.getLogger(__name__)
+
+    LOGGER.info("Starting WiFi Scan")
+    dut.expect_exact("Scan start")
+    dut.expect_exact("Scan done")
+    dut.expect_exact("Wokwi-GUEST")
+    LOGGER.info("WiFi Scan done")
+
+    LOGGER.info("Connecting to WiFi")
+    dut.expect_exact("WiFi connected")
+    dut.expect_exact("IP address:")
+    LOGGER.info("WiFi connected")
diff --git a/tests/validation/wifi/wifi.ino b/tests/validation/wifi/wifi.ino
new file mode 100644
index 00000000000..696234505cc
--- /dev/null
+++ b/tests/validation/wifi/wifi.ino
@@ -0,0 +1,146 @@
+/*
+ *  This sketch shows the WiFi event usage
+ *
+*/
+
+/*
+* WiFi Events
+
+0  ARDUINO_EVENT_WIFI_READY               < ESP32 WiFi ready
+1  ARDUINO_EVENT_WIFI_SCAN_DONE                < ESP32 finish scanning AP
+2  ARDUINO_EVENT_WIFI_STA_START                < ESP32 station start
+3  ARDUINO_EVENT_WIFI_STA_STOP                 < ESP32 station stop
+4  ARDUINO_EVENT_WIFI_STA_CONNECTED            < ESP32 station connected to AP
+5  ARDUINO_EVENT_WIFI_STA_DISCONNECTED         < ESP32 station disconnected from AP
+6  ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE      < the auth mode of AP connected by ESP32 station changed
+7  ARDUINO_EVENT_WIFI_STA_GOT_IP               < ESP32 station got IP from connected AP
+8  ARDUINO_EVENT_WIFI_STA_LOST_IP              < ESP32 station lost IP and the IP is reset to 0
+9  ARDUINO_EVENT_WPS_ER_SUCCESS       < ESP32 station wps succeeds in enrollee mode
+10 ARDUINO_EVENT_WPS_ER_FAILED        < ESP32 station wps fails in enrollee mode
+11 ARDUINO_EVENT_WPS_ER_TIMEOUT       < ESP32 station wps timeout in enrollee mode
+12 ARDUINO_EVENT_WPS_ER_PIN           < ESP32 station wps pin code in enrollee mode
+13 ARDUINO_EVENT_WIFI_AP_START                 < ESP32 soft-AP start
+14 ARDUINO_EVENT_WIFI_AP_STOP                  < ESP32 soft-AP stop
+15 ARDUINO_EVENT_WIFI_AP_STACONNECTED          < a station connected to ESP32 soft-AP
+16 ARDUINO_EVENT_WIFI_AP_STADISCONNECTED       < a station disconnected from ESP32 soft-AP
+17 ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED         < ESP32 soft-AP assign an IP to a connected station
+18 ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED        < Receive probe request packet in soft-AP interface
+19 ARDUINO_EVENT_WIFI_AP_GOT_IP6               < ESP32 ap interface v6IP addr is preferred
+19 ARDUINO_EVENT_WIFI_STA_GOT_IP6              < ESP32 station interface v6IP addr is preferred
+20 ARDUINO_EVENT_ETH_START                < ESP32 ethernet start
+21 ARDUINO_EVENT_ETH_STOP                 < ESP32 ethernet stop
+22 ARDUINO_EVENT_ETH_CONNECTED            < ESP32 ethernet phy link up
+23 ARDUINO_EVENT_ETH_DISCONNECTED         < ESP32 ethernet phy link down
+24 ARDUINO_EVENT_ETH_GOT_IP               < ESP32 ethernet got IP from connected AP
+19 ARDUINO_EVENT_ETH_GOT_IP6              < ESP32 ethernet interface v6IP addr is preferred
+25 ARDUINO_EVENT_MAX
+*/
+
+#include <WiFi.h>
+
+const char *ssid = "Wokwi-GUEST";
+const char *password = "";
+
+// WARNING: This function is called from a separate FreeRTOS task (thread)!
+void WiFiEvent(WiFiEvent_t event) {
+  Serial.printf("[WiFi-event] event: %d\n", event);
+
+  switch (event) {
+    case ARDUINO_EVENT_WIFI_READY:               Serial.println("WiFi interface ready"); break;
+    case ARDUINO_EVENT_WIFI_SCAN_DONE:           Serial.println("Completed scan for access points"); break;
+    case ARDUINO_EVENT_WIFI_STA_START:           Serial.println("WiFi client started"); break;
+    case ARDUINO_EVENT_WIFI_STA_STOP:            Serial.println("WiFi clients stopped"); break;
+    case ARDUINO_EVENT_WIFI_STA_CONNECTED:       Serial.println("Connected to access point"); break;
+    case ARDUINO_EVENT_WIFI_STA_DISCONNECTED:    Serial.println("Disconnected from WiFi access point"); break;
+    case ARDUINO_EVENT_WIFI_STA_AUTHMODE_CHANGE: Serial.println("Authentication mode of access point has changed"); break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP:
+      Serial.print("Obtained IP address: ");
+      Serial.println(WiFi.localIP());
+      break;
+    case ARDUINO_EVENT_WIFI_STA_LOST_IP:        Serial.println("Lost IP address and IP address is reset to 0"); break;
+    case ARDUINO_EVENT_WPS_ER_SUCCESS:          Serial.println("WiFi Protected Setup (WPS): succeeded in enrollee mode"); break;
+    case ARDUINO_EVENT_WPS_ER_FAILED:           Serial.println("WiFi Protected Setup (WPS): failed in enrollee mode"); break;
+    case ARDUINO_EVENT_WPS_ER_TIMEOUT:          Serial.println("WiFi Protected Setup (WPS): timeout in enrollee mode"); break;
+    case ARDUINO_EVENT_WPS_ER_PIN:              Serial.println("WiFi Protected Setup (WPS): pin code in enrollee mode"); break;
+    case ARDUINO_EVENT_WIFI_AP_START:           Serial.println("WiFi access point started"); break;
+    case ARDUINO_EVENT_WIFI_AP_STOP:            Serial.println("WiFi access point  stopped"); break;
+    case ARDUINO_EVENT_WIFI_AP_STACONNECTED:    Serial.println("Client connected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STADISCONNECTED: Serial.println("Client disconnected"); break;
+    case ARDUINO_EVENT_WIFI_AP_STAIPASSIGNED:   Serial.println("Assigned IP address to client"); break;
+    case ARDUINO_EVENT_WIFI_AP_PROBEREQRECVED:  Serial.println("Received probe request"); break;
+    case ARDUINO_EVENT_WIFI_AP_GOT_IP6:         Serial.println("AP IPv6 is preferred"); break;
+    case ARDUINO_EVENT_WIFI_STA_GOT_IP6:        Serial.println("STA IPv6 is preferred"); break;
+    case ARDUINO_EVENT_ETH_GOT_IP6:             Serial.println("Ethernet IPv6 is preferred"); break;
+    case ARDUINO_EVENT_ETH_START:               Serial.println("Ethernet started"); break;
+    case ARDUINO_EVENT_ETH_STOP:                Serial.println("Ethernet stopped"); break;
+    case ARDUINO_EVENT_ETH_CONNECTED:           Serial.println("Ethernet connected"); break;
+    case ARDUINO_EVENT_ETH_DISCONNECTED:        Serial.println("Ethernet disconnected"); break;
+    case ARDUINO_EVENT_ETH_GOT_IP:              Serial.println("Obtained IP address"); break;
+    default:                                    break;
+  }
+}
+
+// WARNING: This function is called from a separate FreeRTOS task (thread)!
+void WiFiGotIP(WiFiEvent_t event, WiFiEventInfo_t info) {
+  Serial.println("WiFi connected");
+  Serial.println("IP address: ");
+  Serial.println(IPAddress(info.got_ip.ip_info.ip.addr));
+}
+
+void setup() {
+  Serial.begin(115200);
+
+  // delete old config
+  WiFi.disconnect(true);
+
+  delay(1000);
+
+  // Examples of different ways to register wifi events;
+  // these handlers will be called from another thread.
+  WiFi.onEvent(WiFiEvent);
+  WiFi.onEvent(WiFiGotIP, WiFiEvent_t::ARDUINO_EVENT_WIFI_STA_GOT_IP);
+  WiFiEventId_t eventID = WiFi.onEvent(
+    [](WiFiEvent_t event, WiFiEventInfo_t info) {
+      Serial.print("WiFi lost connection. Reason: ");
+      Serial.println(info.wifi_sta_disconnected.reason);
+    },
+    WiFiEvent_t::ARDUINO_EVENT_WIFI_STA_DISCONNECTED
+  );
+
+  // Remove WiFi event
+  Serial.print("WiFi Event ID: ");
+  Serial.println(eventID);
+  // WiFi.removeEvent(eventID);
+
+  Serial.println("Scan start");
+
+  // WiFi.scanNetworks will return the number of networks found.
+  int n = WiFi.scanNetworks();
+  Serial.println("Scan done");
+  if (n == 0) {
+    Serial.println("no networks found");
+  } else {
+    Serial.print(n);
+    Serial.println(" networks found");
+    for (int i = 0; i < n; ++i) {
+      // Print SSID for each network found
+      Serial.printf("%s\n", WiFi.SSID(i).c_str());
+      Serial.println();
+      delay(10);
+    }
+  }
+  Serial.println("");
+
+  // Delete the scan result to free memory for code below.
+  WiFi.scanDelete();
+
+  WiFi.begin(ssid, password);
+
+  Serial.println();
+  Serial.println();
+  Serial.println("Wait for WiFi... ");
+}
+
+void loop() {
+  delay(1000);
+}
diff --git a/tools/add_lib.sh b/tools/add_lib.sh
new file mode 100755
index 00000000000..9760f8114c6
--- /dev/null
+++ b/tools/add_lib.sh
@@ -0,0 +1,152 @@
+#!/bin/bash
+
+HELP="This script help to add library when using arduino-esp32 as an ESP-IDF component
+The script accepts up to three arguments:
+-n  NEW: URL address to new library on GIThub (cannot be combined with -e)
+-l  LOCAL: Path to the project where the library should be placed locally (must be paired with -e or -n)
+-e  EXISTING: path to existing libary- this will simply skip the download (cannot be combined with -n)
+
+Examples:
+./add_lib.sh -n https://github.com/me-no-dev/ESPAsyncWebServer
+./add_lib.sh -l ~/esp/esp-idf/examples/your_project
+./add_lib.sh -e ~/Arduino/libraries/existing_library
+
+./add_lib.sh -n https://github.com/me-no-dev/ESPAsyncWebServer -l ~/esp/esp-idf/examples/your_project
+./add_lib.sh -e ~/Arduino/libraries/existing_library -l ~/esp/esp-idf/examples/your_project"
+
+# Get the directory name where this script is located
+SCRIPT_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
+
+# Construct the absolute path to libraries folder
+ARDUINO_LIBS_PATH="$SCRIPT_DIR/../libraries"
+
+# Define the default values for the parameters
+e_param=""
+l_param=""
+n_param=""
+
+# Parse the command-line arguments using getopts
+while getopts "he:l:n:" opt; do
+    case $opt in
+        h)
+            echo "$HELP"
+            exit 0
+            ;;
+        e)
+            #e_param="$OPTARG"
+            e_param="${OPTARG/#~/$HOME}"
+            ;;
+        l)
+            #l_param="$OPTARG"
+            l_param="${OPTARG/#~/$HOME}"
+            ;;
+        n)
+            n_param=$OPTARG
+            ;;
+        \?)
+            echo "Invalid option: -$OPTARG" >&2
+            echo "$HELP"
+            exit 1
+            ;;
+        :)
+            echo "Option -$OPTARG requires an argument." >&2
+            echo "$HELP"
+            exit 1
+            ;;
+        *)
+            echo "Invalid option: -$OPTARG" >&2
+            echo "$HELP"
+            exit 1
+            ;;
+    esac
+done
+
+# No parameter check
+if [[ -z "$e_param" ]] && [[ -z "$l_param" ]] && [[ -z "$n_param" ]]; then
+    echo "Error: No parameters" >&2
+    echo "$HELP"
+    exit 1
+fi
+
+# Only local path check (not permitted)
+if [[ -z "$e_param" ]] && [[ -n "$l_param" ]] && [[ -z "$n_param" ]]; then
+    echo "Error: -l parameter must be paired with -e or -n" >&2
+    echo "$HELP"
+    exit 1
+fi
+
+# Invalid combination check
+if [[ -n $e_param ]] && [[ -n $n_param ]]; then
+    echo "ERROR: Cannot combine -n with -e" >&2
+    echo "$HELP"
+    exit 1
+fi
+
+# Check existing lib
+if [[ -n "$e_param" ]]; then
+    if  [[ ! -d "${e_param/#~/$HOME}" ]]; then # this works!
+        echo "Error: existing library parameter - path does not exist" >&2
+        exit 1
+    fi
+fi
+
+LIBRARY=""
+
+# Only existing library was supplied
+if [[ -n $e_param ]] && [[ -z $l_param ]] && [[ -z $n_param ]]; then
+    LIBRARY=$e_param
+fi
+
+# Install new lib
+if [ -n "$n_param" ]; then
+    INSTALL_TARGET=""
+    if [ -z "$l_param" ]; then
+        # If local path for project is not supplied - use as INSTALL_TARGET Arduino libraries path
+        INSTALL_TARGET=$ARDUINO_LIBS_PATH/$(basename "$n_param")
+    else
+        INSTALL_TARGET=$l_param/components/$(basename "$n_param")
+        if [ ! -d "$l_param/components" ]; then
+            echo "Folder components does not exist yet: mkdir -p \"$l_param/components\""
+            mkdir -p "$l_param/components"
+        fi
+    fi
+    # clone the new lib
+    echo "Cloning: git clone --recursive $n_param $INSTALL_TARGET"
+    git clone --recursive "$n_param" "$INSTALL_TARGET"
+    LIBRARY=$INSTALL_TARGET
+fi
+
+# Copy existing lib to local project
+if [[ -n $e_param ]] && [[ -n $l_param ]]; then
+    if [ ! -d "$l_param/components" ]; then
+        echo "Folder components does not exist yet: mkdir -p \"$l_param/components\""
+        mkdir -p "$l_param/components"
+    fi
+    echo "Copy from $e_param to $l_param"
+    echo "cp -r $e_param $l_param/components/\"$(basename "$e_param")\""
+    cp -r "$e_param" "$l_param"/components/"$(basename "$e_param")"
+    LIBRARY=$l_param/components/"$(basename "$e_param")"
+fi
+
+
+if [ -z "$LIBRARY" ]; then
+    echo "ERROR: No library path" >&2
+    exit 1
+fi
+
+# 1. get the source list:
+FILES=$(find "$LIBRARY" -print0 -name '*.c' -o -name '*.cpp' | xargs -0 -I{} basename {})
+
+# Fresh start
+if [ -f "$LIBRARY"/CMakeLists.txt ]; then
+    rm "$LIBRARY"/CMakeLists.txt
+    touch "$LIBRARY"/CMakeLists.txt
+fi
+
+# Generate CMakeLists.txt
+{
+    echo "idf_component_register(SRCS $(echo "$FILES" | sed -e 's/ /" "/g' | sed -e 's/^/"/' -e 's/$/"/')"
+    echo "                       INCLUDE_DIRS \".\""
+    echo "                       REQUIRES \"arduino-esp32\""
+    echo "                       )"
+} >> "$LIBRARY"/CMakeLists.txt
diff --git a/tools/espota.exe b/tools/espota.exe
index 3de37913ce0..8bee0c9036f 100644
Binary files a/tools/espota.exe and b/tools/espota.exe differ
diff --git a/tools/espota.py b/tools/espota.py
index 77fcfd75c64..fd95955a2f3 100755
--- a/tools/espota.py
+++ b/tools/espota.py
@@ -8,9 +8,10 @@
 # Modified since 2016-01-03 from Matthew O'Gorman (https://githumb.com/mogorman)
 #
 # This script will push an OTA update to the ESP
-# use it like: python espota.py -i <ESP_IP_address> -I <Host_IP_address> -p <ESP_port> -P <Host_port> [-a password] -f <sketch.bin>
+# use it like:
+# python espota.py -i <ESP_IP_addr> -I <Host_IP_addr> -p <ESP_port> -P <Host_port> [-a password] -f <sketch.bin>
 # Or to upload SPIFFS image:
-# python espota.py -i <ESP_IP_address> -I <Host_IP_address> -p <ESP_port> -P <HOST_port> [-a password] -s -f <spiffs.bin>
+# python espota.py -i <ESP_IP_addr> -I <Host_IP_addr> -p <ESP_port> -P <HOST_port> [-a password] -s -f <spiffs.bin>
 #
 # Changes
 # 2015-09-18:
@@ -27,12 +28,20 @@
 # 2016-01-03:
 # - Added more options to parser.
 #
+# Changes
+# 2023-05-22:
+# - Replaced the deprecated optparse module with argparse.
+# - Adjusted the code style to conform to PEP 8 guidelines.
+# - Used with statement for file handling to ensure proper resource cleanup.
+# - Incorporated exception handling to catch and handle potential errors.
+# - Made variable names more descriptive for better readability.
+# - Introduced constants for better code maintainability.
 
 from __future__ import print_function
 import socket
 import sys
 import os
-import optparse
+import argparse
 import logging
 import hashlib
 import random
@@ -41,313 +50,276 @@
 FLASH = 0
 SPIFFS = 100
 AUTH = 200
-PROGRESS = False
-# update_progress() : Displays or updates a console progress bar
-## Accepts a float between 0 and 1. Any int will be converted to a float.
-## A value under 0 represents a 'halt'.
-## A value at 1 or bigger represents 100%
+
+# Constants
+PROGRESS_BAR_LENGTH = 60
+
+
+# update_progress(): Displays or updates a console progress bar
 def update_progress(progress):
-  if (PROGRESS):
-    barLength = 60 # Modify this to change the length of the progress bar
-    status = ""
-    if isinstance(progress, int):
-      progress = float(progress)
-    if not isinstance(progress, float):
-      progress = 0
-      status = "error: progress var must be float\r\n"
-    if progress < 0:
-      progress = 0
-      status = "Halt...\r\n"
-    if progress >= 1:
-      progress = 1
-      status = "Done...\r\n"
-    block = int(round(barLength*progress))
-    text = "\rUploading: [{0}] {1}% {2}".format( "="*block + " "*(barLength-block), int(progress*100), status)
-    sys.stderr.write(text)
-    sys.stderr.flush()
-  else:
-    sys.stderr.write('.')
-    sys.stderr.flush()
+    if PROGRESS:
+        status = ""
+        if isinstance(progress, int):
+            progress = float(progress)
+        if not isinstance(progress, float):
+            progress = 0
+            status = "Error: progress var must be float\r\n"
+        if progress < 0:
+            progress = 0
+            status = "Halt...\r\n"
+        if progress >= 1:
+            progress = 1
+            status = "Done...\r\n"
+        block = int(round(PROGRESS_BAR_LENGTH * progress))
+        text = "\rUploading: [{0}] {1}% {2}".format(
+            "=" * block + " " * (PROGRESS_BAR_LENGTH - block), int(progress * 100), status
+        )
+        sys.stderr.write(text)
+        sys.stderr.flush()
+    else:
+        sys.stderr.write(".")
+        sys.stderr.flush()
 
-def serve(remoteAddr, localAddr, remotePort, localPort, password, filename, command = FLASH):
-  # Create a TCP/IP socket
-  sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
-  server_address = (localAddr, localPort)
-  logging.info('Starting on %s:%s', str(server_address[0]), str(server_address[1]))
-  try:
-    sock.bind(server_address)
-    sock.listen(1)
-  except:
-    logging.error("Listen Failed")
-    return 1
 
-  content_size = os.path.getsize(filename)
-  f = open(filename,'rb')
-  file_md5 = hashlib.md5(f.read()).hexdigest()
-  f.close()
-  logging.info('Upload size: %d', content_size)
-  message = '%d %d %d %s\n' % (command, localPort, content_size, file_md5)
-
-  # Wait for a connection
-  inv_trys = 0
-  data = ''
-  msg = 'Sending invitation to %s ' % (remoteAddr)
-  sys.stderr.write(msg)
-  sys.stderr.flush()
-  while (inv_trys < 10):
-    inv_trys += 1
-    sock2 = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
-    remote_address = (remoteAddr, int(remotePort))
-    try:
-      sent = sock2.sendto(message.encode(), remote_address)
-    except:
-      sys.stderr.write('failed\n')
-      sys.stderr.flush()
-      sock2.close()
-      logging.error('Host %s Not Found', remoteAddr)
-      return 1
-    sock2.settimeout(TIMEOUT)
+def serve(remote_addr, local_addr, remote_port, local_port, password, filename, command=FLASH):  # noqa: C901
+    # Create a TCP/IP socket
+    sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+    server_address = (local_addr, local_port)
+    logging.info("Starting on %s:%s", str(server_address[0]), str(server_address[1]))
     try:
-      data = sock2.recv(37).decode()
-      break;
-    except:
-      sys.stderr.write('.')
-      sys.stderr.flush()
-      sock2.close()
-  sys.stderr.write('\n')
-  sys.stderr.flush()
-  if (inv_trys == 10):
-    logging.error('No response from the ESP')
-    return 1
-  if (data != "OK"):
-    if(data.startswith('AUTH')):
-      nonce = data.split()[1]
-      cnonce_text = '%s%u%s%s' % (filename, content_size, file_md5, remoteAddr)
-      cnonce = hashlib.md5(cnonce_text.encode()).hexdigest()
-      passmd5 = hashlib.md5(password.encode()).hexdigest()
-      result_text = '%s:%s:%s' % (passmd5 ,nonce, cnonce)
-      result = hashlib.md5(result_text.encode()).hexdigest()
-      sys.stderr.write('Authenticating...')
-      sys.stderr.flush()
-      message = '%d %s %s\n' % (AUTH, cnonce, result)
-      sock2.sendto(message.encode(), remote_address)
-      sock2.settimeout(10)
-      try:
-        data = sock2.recv(32).decode()
-      except:
-        sys.stderr.write('FAIL\n')
-        logging.error('No Answer to our Authentication')
-        sock2.close()
+        sock.bind(server_address)
+        sock.listen(1)
+    except Exception as e:
+        logging.error("Listen Failed: %s", str(e))
         return 1
-      if (data != "OK"):
-        sys.stderr.write('FAIL\n')
-        logging.error('%s', data)
-        sock2.close()
-        sys.exit(1);
+
+    content_size = os.path.getsize(filename)
+    file_md5 = hashlib.md5(open(filename, "rb").read()).hexdigest()
+    logging.info("Upload size: %d", content_size)
+    message = "%d %d %d %s\n" % (command, local_port, content_size, file_md5)
+
+    # Wait for a connection
+    inv_tries = 0
+    data = ""
+    msg = "Sending invitation to %s " % remote_addr
+    sys.stderr.write(msg)
+    sys.stderr.flush()
+    while inv_tries < 10:
+        inv_tries += 1
+        sock2 = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
+        remote_address = (remote_addr, int(remote_port))
+        try:
+            sent = sock2.sendto(message.encode(), remote_address)  # noqa: F841
+        except:  # noqa: E722
+            sys.stderr.write("failed\n")
+            sys.stderr.flush()
+            sock2.close()
+            logging.error("Host %s Not Found", remote_addr)
+            return 1
+        sock2.settimeout(TIMEOUT)
+        try:
+            data = sock2.recv(37).decode()
+            break
+        except:  # noqa: E722
+            sys.stderr.write(".")
+            sys.stderr.flush()
+            sock2.close()
+    sys.stderr.write("\n")
+    sys.stderr.flush()
+    if inv_tries == 10:
+        logging.error("No response from the ESP")
         return 1
-      sys.stderr.write('OK\n')
-    else:
-      logging.error('Bad Answer: %s', data)
-      sock2.close()
-      return 1
-  sock2.close()
-
-  logging.info('Waiting for device...')
-  try:
-    sock.settimeout(10)
-    connection, client_address = sock.accept()
-    sock.settimeout(None)
-    connection.settimeout(None)
-  except:
-    logging.error('No response from device')
-    sock.close()
-    return 1
-  try:
-    f = open(filename, "rb")
-    if (PROGRESS):
-      update_progress(0)
-    else:
-      sys.stderr.write('Uploading')
-      sys.stderr.flush()
-    offset = 0
-    while True:
-      chunk = f.read(1024)
-      if not chunk: break
-      offset += len(chunk)
-      update_progress(offset/float(content_size))
-      connection.settimeout(10)
-      try:
-        connection.sendall(chunk)
-        res = connection.recv(10)
-        lastResponseContainedOK = 'OK' in res.decode()
-      except:
-        sys.stderr.write('\n')
-        logging.error('Error Uploading')
-        connection.close()
-        f.close()
+    if data != "OK":
+        if data.startswith("AUTH"):
+            nonce = data.split()[1]
+            cnonce_text = "%s%u%s%s" % (filename, content_size, file_md5, remote_addr)
+            cnonce = hashlib.md5(cnonce_text.encode()).hexdigest()
+            passmd5 = hashlib.md5(password.encode()).hexdigest()
+            result_text = "%s:%s:%s" % (passmd5, nonce, cnonce)
+            result = hashlib.md5(result_text.encode()).hexdigest()
+            sys.stderr.write("Authenticating...")
+            sys.stderr.flush()
+            message = "%d %s %s\n" % (AUTH, cnonce, result)
+            sock2.sendto(message.encode(), remote_address)
+            sock2.settimeout(10)
+            try:
+                data = sock2.recv(32).decode()
+            except:  # noqa: E722
+                sys.stderr.write("FAIL\n")
+                logging.error("No Answer to our Authentication")
+                sock2.close()
+                return 1
+            if data != "OK":
+                sys.stderr.write("FAIL\n")
+                logging.error("%s", data)
+                sock2.close()
+                sys.exit(1)
+                return 1
+            sys.stderr.write("OK\n")
+        else:
+            logging.error("Bad Answer: %s", data)
+            sock2.close()
+            return 1
+    sock2.close()
+
+    logging.info("Waiting for device...")
+    try:
+        sock.settimeout(10)
+        connection, client_address = sock.accept()
+        sock.settimeout(None)
+        connection.settimeout(None)
+    except:  # noqa: E722
+        logging.error("No response from device")
         sock.close()
         return 1
+    try:
+        with open(filename, "rb") as f:
+            if PROGRESS:
+                update_progress(0)
+            else:
+                sys.stderr.write("Uploading")
+                sys.stderr.flush()
+            offset = 0
+            while True:
+                chunk = f.read(1024)
+                if not chunk:
+                    break
+                offset += len(chunk)
+                update_progress(offset / float(content_size))
+                connection.settimeout(10)
+                try:
+                    connection.sendall(chunk)
+                    res = connection.recv(10)
+                    last_response_contained_ok = "OK" in res.decode()
+                except Exception as e:
+                    sys.stderr.write("\n")
+                    logging.error("Error Uploading: %s", str(e))
+                    connection.close()
+                    return 1
 
-    if lastResponseContainedOK:
-      logging.info('Success')
-      connection.close()
-      f.close()
-      sock.close()
-      return 0
+            if last_response_contained_ok:
+                logging.info("Success")
+                connection.close()
+                return 0
 
-    sys.stderr.write('\n')
-    logging.info('Waiting for result...')
-    try:
-      count = 0
-      while True:
-        count=count+1
-        connection.settimeout(60)
-        data = connection.recv(32).decode()
-        logging.info('Result: %s' ,data)
-
-        if "OK" in data:
-          logging.info('Success')
-          connection.close()
-          f.close()
-          sock.close()
-          return 0;
-        if count == 5:
-          logging.error('Error response from device')
-          connection.close()
-          f.close()
-          sock.close()
-          return 1
-    except e:
-      logging.error('No Result!')
-      connection.close()
-      f.close()
-      sock.close()
-      return 1
-
-  finally:
-    connection.close()
-    f.close()
-
-  sock.close()
-  return 1
-# end serve
-
-
-def parser(unparsed_args):
-  parser = optparse.OptionParser(
-    usage = "%prog [options]",
-    description = "Transmit image over the air to the esp32 module with OTA support."
-  )
-
-  # destination ip and port
-  group = optparse.OptionGroup(parser, "Destination")
-  group.add_option("-i", "--ip",
-    dest = "esp_ip",
-    action = "store",
-    help = "ESP32 IP Address.",
-    default = False
-  )
-  group.add_option("-I", "--host_ip",
-    dest = "host_ip",
-    action = "store",
-    help = "Host IP Address.",
-    default = "0.0.0.0"
-  )
-  group.add_option("-p", "--port",
-    dest = "esp_port",
-    type = "int",
-    help = "ESP32 ota Port. Default 3232",
-    default = 3232
-  )
-  group.add_option("-P", "--host_port",
-    dest = "host_port",
-    type = "int",
-    help = "Host server ota Port. Default random 10000-60000",
-    default = random.randint(10000,60000)
-  )
-  parser.add_option_group(group)
-
-  # auth
-  group = optparse.OptionGroup(parser, "Authentication")
-  group.add_option("-a", "--auth",
-    dest = "auth",
-    help = "Set authentication password.",
-    action = "store",
-    default = ""
-  )
-  parser.add_option_group(group)
-
-  # image
-  group = optparse.OptionGroup(parser, "Image")
-  group.add_option("-f", "--file",
-    dest = "image",
-    help = "Image file.",
-    metavar="FILE",
-    default = None
-  )
-  group.add_option("-s", "--spiffs",
-    dest = "spiffs",
-    action = "store_true",
-    help = "Use this option to transmit a SPIFFS image and do not flash the module.",
-    default = False
-  )
-  parser.add_option_group(group)
-
-  # output group
-  group = optparse.OptionGroup(parser, "Output")
-  group.add_option("-d", "--debug",
-    dest = "debug",
-    help = "Show debug output. And override loglevel with debug.",
-    action = "store_true",
-    default = False
-  )
-  group.add_option("-r", "--progress",
-    dest = "progress",
-    help = "Show progress output. Does not work for ArduinoIDE",
-    action = "store_true",
-    default = False
-  )
-  group.add_option("-t", "--timeout",
-    dest = "timeout",
-    type = "int",
-    help = "Timeout to wait for the ESP32 to accept invitation",
-    default = 10
-  )
-  parser.add_option_group(group)
-
-  (options, args) = parser.parse_args(unparsed_args)
-
-  return options
-# end parser
+            sys.stderr.write("\n")
+            logging.info("Waiting for result...")
+            count = 0
+            while count < 5:
+                count += 1
+                connection.settimeout(60)
+                try:
+                    data = connection.recv(32).decode()
+                    logging.info("Result: %s", data)
 
+                    if "OK" in data:
+                        logging.info("Success")
+                        connection.close()
+                        return 0
 
-def main(args):
-  options = parser(args)
-  loglevel = logging.WARNING
-  if (options.debug):
-    loglevel = logging.DEBUG
-
-  logging.basicConfig(level = loglevel, format = '%(asctime)-8s [%(levelname)s]: %(message)s', datefmt = '%H:%M:%S')
-  logging.debug("Options: %s", str(options))
-
-  # check options
-  global PROGRESS
-  PROGRESS = options.progress
-
-  global TIMEOUT
-  TIMEOUT = options.timeout
-  
-  if (not options.esp_ip or not options.image):
-    logging.critical("Not enough arguments.")
+                except Exception as e:
+                    logging.error("Error receiving result: %s", str(e))
+                    connection.close()
+                    return 1
+
+            logging.error("Error response from device")
+            connection.close()
+            return 1
+
+    finally:
+        connection.close()
+
+    sock.close()
     return 1
 
-  command = FLASH
-  if (options.spiffs):
-    command = SPIFFS
 
-  return serve(options.esp_ip, options.host_ip, options.esp_port, options.host_port, options.auth, options.image, command)
-# end main
+def parse_args(unparsed_args):
+    parser = argparse.ArgumentParser(description="Transmit image over the air to the ESP32 module with OTA support.")
+
+    # destination ip and port
+    parser.add_argument("-i", "--ip", dest="esp_ip", action="store", help="ESP32 IP Address.", default=False)
+    parser.add_argument("-I", "--host_ip", dest="host_ip", action="store", help="Host IP Address.", default="0.0.0.0")
+    parser.add_argument("-p", "--port", dest="esp_port", type=int, help="ESP32 OTA Port. Default: 3232", default=3232)
+    parser.add_argument(
+        "-P",
+        "--host_port",
+        dest="host_port",
+        type=int,
+        help="Host server OTA Port. Default: random 10000-60000",
+        default=random.randint(10000, 60000),
+    )
+
+    # authentication
+    parser.add_argument("-a", "--auth", dest="auth", help="Set authentication password.", action="store", default="")
+
+    # image
+    parser.add_argument("-f", "--file", dest="image", help="Image file.", metavar="FILE", default=None)
+    parser.add_argument(
+        "-s",
+        "--spiffs",
+        dest="spiffs",
+        action="store_true",
+        help="Transmit a SPIFFS image and do not flash the module.",
+        default=False,
+    )
+
+    # output
+    parser.add_argument(
+        "-d",
+        "--debug",
+        dest="debug",
+        action="store_true",
+        help="Show debug output. Overrides loglevel with debug.",
+        default=False,
+    )
+    parser.add_argument(
+        "-r",
+        "--progress",
+        dest="progress",
+        action="store_true",
+        help="Show progress output. Does not work for Arduino IDE.",
+        default=False,
+    )
+    parser.add_argument(
+        "-t",
+        "--timeout",
+        dest="timeout",
+        type=int,
+        help="Timeout to wait for the ESP32 to accept invitation.",
+        default=10,
+    )
+
+    return parser.parse_args(unparsed_args)
+
+
+def main(args):
+    options = parse_args(args)
+    log_level = logging.WARNING
+    if options.debug:
+        log_level = logging.DEBUG
+
+    logging.basicConfig(level=log_level, format="%(asctime)-8s [%(levelname)s]: %(message)s", datefmt="%H:%M:%S")
+    logging.debug("Options: %s", str(options))
+
+    # check options
+    global PROGRESS
+    PROGRESS = options.progress
+
+    global TIMEOUT
+    TIMEOUT = options.timeout
+
+    if not options.esp_ip or not options.image:
+        logging.critical("Not enough arguments.")
+        return 1
+
+    command = FLASH
+    if options.spiffs:
+        command = SPIFFS
+
+    return serve(
+        options.esp_ip, options.host_ip, options.esp_port, options.host_port, options.auth, options.image, command
+    )
 
 
-if __name__ == '__main__':
-  sys.exit(main(sys.argv))
+if __name__ == "__main__":
+    sys.exit(main(sys.argv[1:]))
diff --git a/tools/esptool.py b/tools/esptool.py
deleted file mode 100755
index c68e6fc1f52..00000000000
--- a/tools/esptool.py
+++ /dev/null
@@ -1,3201 +0,0 @@
-#!/usr/bin/env python
-#
-# ESP8266 & ESP32 ROM Bootloader Utility
-# Copyright (C) 2014-2016 Fredrik Ahlberg, Angus Gratton, Espressif Systems (Shanghai) PTE LTD, other contributors as noted.
-# https://github.com/espressif/esptool
-#
-# This program is free software; you can redistribute it and/or modify it under
-# the terms of the GNU General Public License as published by the Free Software
-# Foundation; either version 2 of the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License along with
-# this program; if not, write to the Free Software Foundation, Inc., 51 Franklin
-# Street, Fifth Floor, Boston, MA 02110-1301 USA.
-
-from __future__ import division, print_function
-
-import argparse
-import base64
-import binascii
-import copy
-import hashlib
-import inspect
-import io
-import os
-import shlex
-import struct
-import sys
-import time
-import zlib
-import string
-
-try:
-    import serial
-except ImportError:
-    print("Pyserial is not installed for %s. Check the README for installation instructions." % (sys.executable))
-    raise
-
-# check 'serial' is 'pyserial' and not 'serial' https://github.com/espressif/esptool/issues/269
-try:
-    if "serialization" in serial.__doc__ and "deserialization" in serial.__doc__:
-        raise ImportError("""
-esptool.py depends on pyserial, but there is a conflict with a currently installed package named 'serial'.
-
-You may be able to work around this by 'pip uninstall serial; pip install pyserial' \
-but this may break other installed Python software that depends on 'serial'.
-
-There is no good fix for this right now, apart from configuring virtualenvs. \
-See https://github.com/espressif/esptool/issues/269#issuecomment-385298196 for discussion of the underlying issue(s).""")
-except TypeError:
-    pass  # __doc__ returns None for pyserial
-
-try:
-    import serial.tools.list_ports as list_ports
-except ImportError:
-    print("The installed version (%s) of pyserial appears to be too old for esptool.py (Python interpreter %s). "
-          "Check the README for installation instructions." % (sys.VERSION, sys.executable))
-    raise
-
-__version__ = "2.8"
-
-MAX_UINT32 = 0xffffffff
-MAX_UINT24 = 0xffffff
-
-DEFAULT_TIMEOUT = 3                   # timeout for most flash operations
-START_FLASH_TIMEOUT = 20              # timeout for starting flash (may perform erase)
-CHIP_ERASE_TIMEOUT = 120              # timeout for full chip erase
-MAX_TIMEOUT = CHIP_ERASE_TIMEOUT * 2  # longest any command can run
-SYNC_TIMEOUT = 0.1                    # timeout for syncing with bootloader
-MD5_TIMEOUT_PER_MB = 8                # timeout (per megabyte) for calculating md5sum
-ERASE_REGION_TIMEOUT_PER_MB = 30      # timeout (per megabyte) for erasing a region
-MEM_END_ROM_TIMEOUT = 0.05            # special short timeout for ESP_MEM_END, as it may never respond
-DEFAULT_SERIAL_WRITE_TIMEOUT = 10     # timeout for serial port write
-
-
-def timeout_per_mb(seconds_per_mb, size_bytes):
-    """ Scales timeouts which are size-specific """
-    result = seconds_per_mb * (size_bytes / 1e6)
-    if result < DEFAULT_TIMEOUT:
-        return DEFAULT_TIMEOUT
-    return result
-
-
-DETECTED_FLASH_SIZES = {0x12: '256KB', 0x13: '512KB', 0x14: '1MB',
-                        0x15: '2MB', 0x16: '4MB', 0x17: '8MB', 0x18: '16MB'}
-
-
-def check_supported_function(func, check_func):
-    """
-    Decorator implementation that wraps a check around an ESPLoader
-    bootloader function to check if it's supported.
-
-    This is used to capture the multidimensional differences in
-    functionality between the ESP8266 & ESP32 ROM loaders, and the
-    software stub that runs on both. Not possible to do this cleanly
-    via inheritance alone.
-    """
-    def inner(*args, **kwargs):
-        obj = args[0]
-        if check_func(obj):
-            return func(*args, **kwargs)
-        else:
-            raise NotImplementedInROMError(obj, func)
-    return inner
-
-
-def stub_function_only(func):
-    """ Attribute for a function only supported in the software stub loader """
-    return check_supported_function(func, lambda o: o.IS_STUB)
-
-
-def stub_and_esp32_function_only(func):
-    """ Attribute for a function only supported by software stubs or ESP32 ROM """
-    return check_supported_function(func, lambda o: o.IS_STUB or o.CHIP_NAME == "ESP32")
-
-
-PYTHON2 = sys.version_info[0] < 3  # True if on pre-Python 3
-
-# Function to return nth byte of a bitstring
-# Different behaviour on Python 2 vs 3
-if PYTHON2:
-    def byte(bitstr, index):
-        return ord(bitstr[index])
-else:
-    def byte(bitstr, index):
-        return bitstr[index]
-
-# Provide a 'basestring' class on Python 3
-try:
-    basestring
-except NameError:
-    basestring = str
-
-
-def _mask_to_shift(mask):
-    """ Return the index of the least significant bit in the mask """
-    shift = 0
-    while mask & 0x1 == 0:
-        shift += 1
-        mask >>= 1
-    return shift
-
-
-def esp8266_function_only(func):
-    """ Attribute for a function only supported on ESP8266 """
-    return check_supported_function(func, lambda o: o.CHIP_NAME == "ESP8266")
-
-
-class ESPLoader(object):
-    """ Base class providing access to ESP ROM & software stub bootloaders.
-    Subclasses provide ESP8266 & ESP32 specific functionality.
-
-    Don't instantiate this base class directly, either instantiate a subclass or
-    call ESPLoader.detect_chip() which will interrogate the chip and return the
-    appropriate subclass instance.
-
-    """
-    CHIP_NAME = "Espressif device"
-    IS_STUB = False
-
-    DEFAULT_PORT = "/dev/ttyUSB0"
-
-    # Commands supported by ESP8266 ROM bootloader
-    ESP_FLASH_BEGIN = 0x02
-    ESP_FLASH_DATA  = 0x03
-    ESP_FLASH_END   = 0x04
-    ESP_MEM_BEGIN   = 0x05
-    ESP_MEM_END     = 0x06
-    ESP_MEM_DATA    = 0x07
-    ESP_SYNC        = 0x08
-    ESP_WRITE_REG   = 0x09
-    ESP_READ_REG    = 0x0a
-
-    # Some comands supported by ESP32 ROM bootloader (or -8266 w/ stub)
-    ESP_SPI_SET_PARAMS = 0x0B
-    ESP_SPI_ATTACH     = 0x0D
-    ESP_CHANGE_BAUDRATE = 0x0F
-    ESP_FLASH_DEFL_BEGIN = 0x10
-    ESP_FLASH_DEFL_DATA  = 0x11
-    ESP_FLASH_DEFL_END   = 0x12
-    ESP_SPI_FLASH_MD5    = 0x13
-
-    # Some commands supported by stub only
-    ESP_ERASE_FLASH = 0xD0
-    ESP_ERASE_REGION = 0xD1
-    ESP_READ_FLASH = 0xD2
-    ESP_RUN_USER_CODE = 0xD3
-
-    # Flash encryption debug more command
-    ESP_FLASH_ENCRYPT_DATA = 0xD4
-
-    # Maximum block sized for RAM and Flash writes, respectively.
-    ESP_RAM_BLOCK   = 0x1800
-
-    FLASH_WRITE_SIZE = 0x400
-
-    # Default baudrate. The ROM auto-bauds, so we can use more or less whatever we want.
-    ESP_ROM_BAUD    = 115200
-
-    # First byte of the application image
-    ESP_IMAGE_MAGIC = 0xe9
-
-    # Initial state for the checksum routine
-    ESP_CHECKSUM_MAGIC = 0xef
-
-    # Flash sector size, minimum unit of erase.
-    FLASH_SECTOR_SIZE = 0x1000
-
-    # This register happens to exist on both ESP8266 & ESP32
-    UART_DATA_REG_ADDR = 0x60000078
-
-    UART_CLKDIV_MASK = 0xFFFFF
-
-    # Memory addresses
-    IROM_MAP_START = 0x40200000
-    IROM_MAP_END = 0x40300000
-
-    # The number of bytes in the UART response that signify command status
-    STATUS_BYTES_LENGTH = 2
-
-    def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, trace_enabled=False):
-        """Base constructor for ESPLoader bootloader interaction
-
-        Don't call this constructor, either instantiate ESP8266ROM
-        or ESP32ROM, or use ESPLoader.detect_chip().
-
-        This base class has all of the instance methods for bootloader
-        functionality supported across various chips & stub
-        loaders. Subclasses replace the functions they don't support
-        with ones which throw NotImplementedInROMError().
-
-        """
-        if isinstance(port, basestring):
-            self._port = serial.serial_for_url(port)
-        else:
-            self._port = port
-        self._slip_reader = slip_reader(self._port, self.trace)
-        # setting baud rate in a separate step is a workaround for
-        # CH341 driver on some Linux versions (this opens at 9600 then
-        # sets), shouldn't matter for other platforms/drivers. See
-        # https://github.com/espressif/esptool/issues/44#issuecomment-107094446
-        self._set_port_baudrate(baud)
-        self._trace_enabled = trace_enabled
-        # set write timeout, to prevent esptool blocked at write forever.
-        try:
-            self._port.write_timeout = DEFAULT_SERIAL_WRITE_TIMEOUT
-        except NotImplementedError:
-            # no write timeout for RFC2217 ports
-            # need to set the property back to None or it will continue to fail
-            self._port.write_timeout = None
-
-    def _set_port_baudrate(self, baud):
-        try:
-            self._port.baudrate = baud
-        except IOError:
-            raise FatalError("Failed to set baud rate %d. The driver may not support this rate." % baud)
-
-    @staticmethod
-    def detect_chip(port=DEFAULT_PORT, baud=ESP_ROM_BAUD, connect_mode='default_reset', trace_enabled=False):
-        """ Use serial access to detect the chip type.
-
-        We use the UART's datecode register for this, it's mapped at
-        the same address on ESP8266 & ESP32 so we can use one
-        memory read and compare to the datecode register for each chip
-        type.
-
-        This routine automatically performs ESPLoader.connect() (passing
-        connect_mode parameter) as part of querying the chip.
-        """
-        detect_port = ESPLoader(port, baud, trace_enabled=trace_enabled)
-        detect_port.connect(connect_mode)
-        try:
-            print('Detecting chip type...', end='')
-            sys.stdout.flush()
-            date_reg = detect_port.read_reg(ESPLoader.UART_DATA_REG_ADDR)
-
-            for cls in [ESP8266ROM, ESP32ROM]:
-                if date_reg == cls.DATE_REG_VALUE:
-                    # don't connect a second time
-                    inst = cls(detect_port._port, baud, trace_enabled=trace_enabled)
-                    print(' %s' % inst.CHIP_NAME, end='')
-                    return inst
-        finally:
-            print('')  # end line
-        raise FatalError("Unexpected UART datecode value 0x%08x. Failed to autodetect chip type." % date_reg)
-
-    """ Read a SLIP packet from the serial port """
-    def read(self):
-        return next(self._slip_reader)
-
-    """ Write bytes to the serial port while performing SLIP escaping """
-    def write(self, packet):
-        buf = b'\xc0' \
-              + (packet.replace(b'\xdb',b'\xdb\xdd').replace(b'\xc0',b'\xdb\xdc')) \
-              + b'\xc0'
-        self.trace("Write %d bytes: %s", len(buf), HexFormatter(buf))
-        self._port.write(buf)
-
-    def trace(self, message, *format_args):
-        if self._trace_enabled:
-            now = time.time()
-            try:
-
-                delta = now - self._last_trace
-            except AttributeError:
-                delta = 0.0
-            self._last_trace = now
-            prefix = "TRACE +%.3f " % delta
-            print(prefix + (message % format_args))
-
-    """ Calculate checksum of a blob, as it is defined by the ROM """
-    @staticmethod
-    def checksum(data, state=ESP_CHECKSUM_MAGIC):
-        for b in data:
-            if type(b) is int:  # python 2/3 compat
-                state ^= b
-            else:
-                state ^= ord(b)
-
-        return state
-
-    """ Send a request and read the response """
-    def command(self, op=None, data=b"", chk=0, wait_response=True, timeout=DEFAULT_TIMEOUT):
-        saved_timeout = self._port.timeout
-        new_timeout = min(timeout, MAX_TIMEOUT)
-        if new_timeout != saved_timeout:
-            self._port.timeout = new_timeout
-
-        try:
-            if op is not None:
-                self.trace("command op=0x%02x data len=%s wait_response=%d timeout=%.3f data=%s",
-                           op, len(data), 1 if wait_response else 0, timeout, HexFormatter(data))
-                pkt = struct.pack(b'<BBHI', 0x00, op, len(data), chk) + data
-                self.write(pkt)
-
-            if not wait_response:
-                return
-
-            # tries to get a response until that response has the
-            # same operation as the request or a retries limit has
-            # exceeded. This is needed for some esp8266s that
-            # reply with more sync responses than expected.
-            for retry in range(100):
-                p = self.read()
-                if len(p) < 8:
-                    continue
-                (resp, op_ret, len_ret, val) = struct.unpack('<BBHI', p[:8])
-                if resp != 1:
-                    continue
-                data = p[8:]
-                if op is None or op_ret == op:
-                    return val, data
-        finally:
-            if new_timeout != saved_timeout:
-                self._port.timeout = saved_timeout
-
-        raise FatalError("Response doesn't match request")
-
-    def check_command(self, op_description, op=None, data=b'', chk=0, timeout=DEFAULT_TIMEOUT):
-        """
-        Execute a command with 'command', check the result code and throw an appropriate
-        FatalError if it fails.
-
-        Returns the "result" of a successful command.
-        """
-        val, data = self.command(op, data, chk, timeout=timeout)
-
-        # things are a bit weird here, bear with us
-
-        # the status bytes are the last 2/4 bytes in the data (depending on chip)
-        if len(data) < self.STATUS_BYTES_LENGTH:
-            raise FatalError("Failed to %s. Only got %d byte status response." % (op_description, len(data)))
-        status_bytes = data[-self.STATUS_BYTES_LENGTH:]
-        # we only care if the first one is non-zero. If it is, the second byte is a reason.
-        if byte(status_bytes, 0) != 0:
-            raise FatalError.WithResult('Failed to %s' % op_description, status_bytes)
-
-        # if we had more data than just the status bytes, return it as the result
-        # (this is used by the md5sum command, maybe other commands?)
-        if len(data) > self.STATUS_BYTES_LENGTH:
-            return data[:-self.STATUS_BYTES_LENGTH]
-        else:  # otherwise, just return the 'val' field which comes from the reply header (this is used by read_reg)
-            return val
-
-    def flush_input(self):
-        self._port.flushInput()
-        self._slip_reader = slip_reader(self._port, self.trace)
-
-    def sync(self):
-        self.command(self.ESP_SYNC, b'\x07\x07\x12\x20' + 32 * b'\x55',
-                     timeout=SYNC_TIMEOUT)
-        for i in range(7):
-            self.command()
-
-    def _setDTR(self, state):
-        self._port.setDTR(state)
-
-    def _setRTS(self, state):
-        self._port.setRTS(state)
-        # Work-around for adapters on Windows using the usbser.sys driver:
-        # generate a dummy change to DTR so that the set-control-line-state
-        # request is sent with the updated RTS state and the same DTR state
-        self._port.setDTR(self._port.dtr)
-
-    def _connect_attempt(self, mode='default_reset', esp32r0_delay=False):
-        """ A single connection attempt, with esp32r0 workaround options """
-        # esp32r0_delay is a workaround for bugs with the most common auto reset
-        # circuit and Windows, if the EN pin on the dev board does not have
-        # enough capacitance.
-        #
-        # Newer dev boards shouldn't have this problem (higher value capacitor
-        # on the EN pin), and ESP32 revision 1 can't use this workaround as it
-        # relies on a silicon bug.
-        #
-        # Details: https://github.com/espressif/esptool/issues/136
-        last_error = None
-
-        # If we're doing no_sync, we're likely communicating as a pass through
-        # with an intermediate device to the ESP32
-        if mode == "no_reset_no_sync":
-            return last_error
-
-        # issue reset-to-bootloader:
-        # RTS = either CH_PD/EN or nRESET (both active low = chip in reset
-        # DTR = GPIO0 (active low = boot to flasher)
-        #
-        # DTR & RTS are active low signals,
-        # ie True = pin @ 0V, False = pin @ VCC.
-        if mode != 'no_reset':
-            self._setDTR(False)  # IO0=HIGH
-            self._setRTS(True)   # EN=LOW, chip in reset
-            time.sleep(0.1)
-            if esp32r0_delay:
-                # Some chips are more likely to trigger the esp32r0
-                # watchdog reset silicon bug if they're held with EN=LOW
-                # for a longer period
-                time.sleep(1.2)
-            self._setDTR(True)   # IO0=LOW
-            self._setRTS(False)  # EN=HIGH, chip out of reset
-            if esp32r0_delay:
-                # Sleep longer after reset.
-                # This workaround only works on revision 0 ESP32 chips,
-                # it exploits a silicon bug spurious watchdog reset.
-                time.sleep(0.4)  # allow watchdog reset to occur
-            time.sleep(0.05)
-            self._setDTR(False)  # IO0=HIGH, done
-
-        for _ in range(5):
-            try:
-                self.flush_input()
-                self._port.flushOutput()
-                self.sync()
-                return None
-            except FatalError as e:
-                if esp32r0_delay:
-                    print('_', end='')
-                else:
-                    print('.', end='')
-                sys.stdout.flush()
-                time.sleep(0.05)
-                last_error = e
-        return last_error
-
-    def connect(self, mode='default_reset'):
-        """ Try connecting repeatedly until successful, or giving up """
-        print('Connecting...', end='')
-        sys.stdout.flush()
-        last_error = None
-
-        try:
-            for _ in range(7):
-                last_error = self._connect_attempt(mode=mode, esp32r0_delay=False)
-                if last_error is None:
-                    return
-                last_error = self._connect_attempt(mode=mode, esp32r0_delay=True)
-                if last_error is None:
-                    return
-        finally:
-            print('')  # end 'Connecting...' line
-        raise FatalError('Failed to connect to %s: %s' % (self.CHIP_NAME, last_error))
-
-    def read_reg(self, addr):
-        """ Read memory address in target """
-        # we don't call check_command here because read_reg() function is called
-        # when detecting chip type, and the way we check for success (STATUS_BYTES_LENGTH) is different
-        # for different chip types (!)
-        val, data = self.command(self.ESP_READ_REG, struct.pack('<I', addr))
-        if byte(data, 0) != 0:
-            raise FatalError.WithResult("Failed to read register address %08x" % addr, data)
-        return val
-
-    def write_reg(self, addr, value, mask=0xFFFFFFFF, delay_us=0):
-        """ Write to memory address in target
-
-        Note: mask option is not supported by stub loaders, use update_reg() function.
-        """
-        return self.check_command("write target memory", self.ESP_WRITE_REG,
-                                  struct.pack('<IIII', addr, value, mask, delay_us))
-
-    def update_reg(self, addr, mask, new_val):
-        """ Update register at 'addr', replace the bits masked out by 'mask'
-        with new_val. new_val is shifted left to match the LSB of 'mask'
-
-        Returns just-written value of register.
-        """
-        shift = _mask_to_shift(mask)
-        val = self.read_reg(addr)
-        val &= ~mask
-        val |= (new_val << shift) & mask
-        self.write_reg(addr, val)
-
-        return val
-
-    """ Start downloading an application image to RAM """
-    def mem_begin(self, size, blocks, blocksize, offset):
-        if self.IS_STUB:  # check we're not going to overwrite a running stub with this data
-            stub = self.STUB_CODE
-            load_start = offset
-            load_end = offset + size
-            for (start, end) in [(stub["data_start"], stub["data_start"] + len(stub["data"])),
-                                 (stub["text_start"], stub["text_start"] + len(stub["text"]))]:
-                if load_start < end and load_end > start:
-                    raise FatalError(("Software loader is resident at 0x%08x-0x%08x. " +
-                                      "Can't load binary at overlapping address range 0x%08x-0x%08x. " +
-                                      "Either change binary loading address, or use the --no-stub " +
-                                      "option to disable the software loader.") % (start, end, load_start, load_end))
-
-        return self.check_command("enter RAM download mode", self.ESP_MEM_BEGIN,
-                                  struct.pack('<IIII', size, blocks, blocksize, offset))
-
-    """ Send a block of an image to RAM """
-    def mem_block(self, data, seq):
-        return self.check_command("write to target RAM", self.ESP_MEM_DATA,
-                                  struct.pack('<IIII', len(data), seq, 0, 0) + data,
-                                  self.checksum(data))
-
-    """ Leave download mode and run the application """
-    def mem_finish(self, entrypoint=0):
-        # Sending ESP_MEM_END usually sends a correct response back, however sometimes
-        # (with ROM loader) the executed code may reset the UART or change the baud rate
-        # before the transmit FIFO is empty. So in these cases we set a short timeout and
-        # ignore errors.
-        timeout = DEFAULT_TIMEOUT if self.IS_STUB else MEM_END_ROM_TIMEOUT
-        data = struct.pack('<II', int(entrypoint == 0), entrypoint)
-        try:
-            return self.check_command("leave RAM download mode", self.ESP_MEM_END,
-                                      data=data, timeout=timeout)
-        except FatalError:
-            if self.IS_STUB:
-                raise
-            pass
-
-    """ Start downloading to Flash (performs an erase)
-
-    Returns number of blocks (of size self.FLASH_WRITE_SIZE) to write.
-    """
-    def flash_begin(self, size, offset):
-        num_blocks = (size + self.FLASH_WRITE_SIZE - 1) // self.FLASH_WRITE_SIZE
-        erase_size = self.get_erase_size(offset, size)
-
-        t = time.time()
-        if self.IS_STUB:
-            timeout = DEFAULT_TIMEOUT
-        else:
-            timeout = timeout_per_mb(ERASE_REGION_TIMEOUT_PER_MB, size)  # ROM performs the erase up front
-        self.check_command("enter Flash download mode", self.ESP_FLASH_BEGIN,
-                           struct.pack('<IIII', erase_size, num_blocks, self.FLASH_WRITE_SIZE, offset),
-                           timeout=timeout)
-        if size != 0 and not self.IS_STUB:
-            print("Took %.2fs to erase flash block" % (time.time() - t))
-        return num_blocks
-
-    """ Write block to flash """
-    def flash_block(self, data, seq, timeout=DEFAULT_TIMEOUT):
-        self.check_command("write to target Flash after seq %d" % seq,
-                           self.ESP_FLASH_DATA,
-                           struct.pack('<IIII', len(data), seq, 0, 0) + data,
-                           self.checksum(data),
-                           timeout=timeout)
-
-    """ Encrypt before writing to flash """
-    def flash_encrypt_block(self, data, seq, timeout=DEFAULT_TIMEOUT):
-        self.check_command("Write encrypted to target Flash after seq %d" % seq,
-                           self.ESP_FLASH_ENCRYPT_DATA,
-                           struct.pack('<IIII', len(data), seq, 0, 0) + data,
-                           self.checksum(data),
-                           timeout=timeout)
-
-    """ Leave flash mode and run/reboot """
-    def flash_finish(self, reboot=False):
-        pkt = struct.pack('<I', int(not reboot))
-        # stub sends a reply to this command
-        self.check_command("leave Flash mode", self.ESP_FLASH_END, pkt)
-
-    """ Run application code in flash """
-    def run(self, reboot=False):
-        # Fake flash begin immediately followed by flash end
-        self.flash_begin(0, 0)
-        self.flash_finish(reboot)
-
-    """ Read SPI flash manufacturer and device id """
-    def flash_id(self):
-        SPIFLASH_RDID = 0x9F
-        return self.run_spiflash_command(SPIFLASH_RDID, b"", 24)
-
-    def parse_flash_size_arg(self, arg):
-        try:
-            return self.FLASH_SIZES[arg]
-        except KeyError:
-            raise FatalError("Flash size '%s' is not supported by this chip type. Supported sizes: %s"
-                             % (arg, ", ".join(self.FLASH_SIZES.keys())))
-
-    def run_stub(self, stub=None):
-        if stub is None:
-            if self.IS_STUB:
-                raise FatalError("Not possible for a stub to load another stub (memory likely to overlap.)")
-            stub = self.STUB_CODE
-
-        # Upload
-        print("Uploading stub...")
-        for field in ['text', 'data']:
-            if field in stub:
-                offs = stub[field + "_start"]
-                length = len(stub[field])
-                blocks = (length + self.ESP_RAM_BLOCK - 1) // self.ESP_RAM_BLOCK
-                self.mem_begin(length, blocks, self.ESP_RAM_BLOCK, offs)
-                for seq in range(blocks):
-                    from_offs = seq * self.ESP_RAM_BLOCK
-                    to_offs = from_offs + self.ESP_RAM_BLOCK
-                    self.mem_block(stub[field][from_offs:to_offs], seq)
-        print("Running stub...")
-        self.mem_finish(stub['entry'])
-
-        p = self.read()
-        if p != b'OHAI':
-            raise FatalError("Failed to start stub. Unexpected response: %s" % p)
-        print("Stub running...")
-        return self.STUB_CLASS(self)
-
-    @stub_and_esp32_function_only
-    def flash_defl_begin(self, size, compsize, offset):
-        """ Start downloading compressed data to Flash (performs an erase)
-
-        Returns number of blocks (size self.FLASH_WRITE_SIZE) to write.
-        """
-        num_blocks = (compsize + self.FLASH_WRITE_SIZE - 1) // self.FLASH_WRITE_SIZE
-        erase_blocks = (size + self.FLASH_WRITE_SIZE - 1) // self.FLASH_WRITE_SIZE
-
-        t = time.time()
-        if self.IS_STUB:
-            write_size = size  # stub expects number of bytes here, manages erasing internally
-            timeout = DEFAULT_TIMEOUT
-        else:
-            write_size = erase_blocks * self.FLASH_WRITE_SIZE  # ROM expects rounded up to erase block size
-            timeout = timeout_per_mb(ERASE_REGION_TIMEOUT_PER_MB, write_size)  # ROM performs the erase up front
-        print("Compressed %d bytes to %d..." % (size, compsize))
-        self.check_command("enter compressed flash mode", self.ESP_FLASH_DEFL_BEGIN,
-                           struct.pack('<IIII', write_size, num_blocks, self.FLASH_WRITE_SIZE, offset),
-                           timeout=timeout)
-        if size != 0 and not self.IS_STUB:
-            # (stub erases as it writes, but ROM loaders erase on begin)
-            print("Took %.2fs to erase flash block" % (time.time() - t))
-        return num_blocks
-
-    """ Write block to flash, send compressed """
-    @stub_and_esp32_function_only
-    def flash_defl_block(self, data, seq, timeout=DEFAULT_TIMEOUT):
-        self.check_command("write compressed data to flash after seq %d" % seq,
-                           self.ESP_FLASH_DEFL_DATA, struct.pack('<IIII', len(data), seq, 0, 0) + data, self.checksum(data), timeout=timeout)
-
-    """ Leave compressed flash mode and run/reboot """
-    @stub_and_esp32_function_only
-    def flash_defl_finish(self, reboot=False):
-        if not reboot and not self.IS_STUB:
-            # skip sending flash_finish to ROM loader, as this
-            # exits the bootloader. Stub doesn't do this.
-            return
-        pkt = struct.pack('<I', int(not reboot))
-        self.check_command("leave compressed flash mode", self.ESP_FLASH_DEFL_END, pkt)
-        self.in_bootloader = False
-
-    @stub_and_esp32_function_only
-    def flash_md5sum(self, addr, size):
-        # the MD5 command returns additional bytes in the standard
-        # command reply slot
-        timeout = timeout_per_mb(MD5_TIMEOUT_PER_MB, size)
-        res = self.check_command('calculate md5sum', self.ESP_SPI_FLASH_MD5, struct.pack('<IIII', addr, size, 0, 0),
-                                 timeout=timeout)
-
-        if len(res) == 32:
-            return res.decode("utf-8")  # already hex formatted
-        elif len(res) == 16:
-            return hexify(res).lower()
-        else:
-            raise FatalError("MD5Sum command returned unexpected result: %r" % res)
-
-    @stub_and_esp32_function_only
-    def change_baud(self, baud):
-        print("Changing baud rate to %d" % baud)
-        # stub takes the new baud rate and the old one
-        second_arg = self._port.baudrate if self.IS_STUB else 0
-        self.command(self.ESP_CHANGE_BAUDRATE, struct.pack('<II', baud, second_arg))
-        print("Changed.")
-        self._set_port_baudrate(baud)
-        time.sleep(0.05)  # get rid of crap sent during baud rate change
-        self.flush_input()
-
-    @stub_function_only
-    def erase_flash(self):
-        # depending on flash chip model the erase may take this long (maybe longer!)
-        self.check_command("erase flash", self.ESP_ERASE_FLASH,
-                           timeout=CHIP_ERASE_TIMEOUT)
-
-    @stub_function_only
-    def erase_region(self, offset, size):
-        if offset % self.FLASH_SECTOR_SIZE != 0:
-            raise FatalError("Offset to erase from must be a multiple of 4096")
-        if size % self.FLASH_SECTOR_SIZE != 0:
-            raise FatalError("Size of data to erase must be a multiple of 4096")
-        timeout = timeout_per_mb(ERASE_REGION_TIMEOUT_PER_MB, size)
-        self.check_command("erase region", self.ESP_ERASE_REGION, struct.pack('<II', offset, size), timeout=timeout)
-
-    @stub_function_only
-    def read_flash(self, offset, length, progress_fn=None):
-        # issue a standard bootloader command to trigger the read
-        self.check_command("read flash", self.ESP_READ_FLASH,
-                           struct.pack('<IIII',
-                                       offset,
-                                       length,
-                                       self.FLASH_SECTOR_SIZE,
-                                       64))
-        # now we expect (length // block_size) SLIP frames with the data
-        data = b''
-        while len(data) < length:
-            p = self.read()
-            data += p
-            if len(data) < length and len(p) < self.FLASH_SECTOR_SIZE:
-                raise FatalError('Corrupt data, expected 0x%x bytes but received 0x%x bytes' % (self.FLASH_SECTOR_SIZE, len(p)))
-            self.write(struct.pack('<I', len(data)))
-            if progress_fn and (len(data) % 1024 == 0 or len(data) == length):
-                progress_fn(len(data), length)
-        if progress_fn:
-            progress_fn(len(data), length)
-        if len(data) > length:
-            raise FatalError('Read more than expected')
-
-        digest_frame = self.read()
-        if len(digest_frame) != 16:
-            raise FatalError('Expected digest, got: %s' % hexify(digest_frame))
-        expected_digest = hexify(digest_frame).upper()
-        digest = hashlib.md5(data).hexdigest().upper()
-        if digest != expected_digest:
-            raise FatalError('Digest mismatch: expected %s, got %s' % (expected_digest, digest))
-        return data
-
-    def flash_spi_attach(self, hspi_arg):
-        """Send SPI attach command to enable the SPI flash pins
-
-        ESP8266 ROM does this when you send flash_begin, ESP32 ROM
-        has it as a SPI command.
-        """
-        # last 3 bytes in ESP_SPI_ATTACH argument are reserved values
-        arg = struct.pack('<I', hspi_arg)
-        if not self.IS_STUB:
-            # ESP32 ROM loader takes additional 'is legacy' arg, which is not
-            # currently supported in the stub loader or esptool.py (as it's not usually needed.)
-            is_legacy = 0
-            arg += struct.pack('BBBB', is_legacy, 0, 0, 0)
-        self.check_command("configure SPI flash pins", ESP32ROM.ESP_SPI_ATTACH, arg)
-
-    def flash_set_parameters(self, size):
-        """Tell the ESP bootloader the parameters of the chip
-
-        Corresponds to the "flashchip" data structure that the ROM
-        has in RAM.
-
-        'size' is in bytes.
-
-        All other flash parameters are currently hardcoded (on ESP8266
-        these are mostly ignored by ROM code, on ESP32 I'm not sure.)
-        """
-        fl_id = 0
-        total_size = size
-        block_size = 64 * 1024
-        sector_size = 4 * 1024
-        page_size = 256
-        status_mask = 0xffff
-        self.check_command("set SPI params", ESP32ROM.ESP_SPI_SET_PARAMS,
-                           struct.pack('<IIIIII', fl_id, total_size, block_size, sector_size, page_size, status_mask))
-
-    def run_spiflash_command(self, spiflash_command, data=b"", read_bits=0):
-        """Run an arbitrary SPI flash command.
-
-        This function uses the "USR_COMMAND" functionality in the ESP
-        SPI hardware, rather than the precanned commands supported by
-        hardware. So the value of spiflash_command is an actual command
-        byte, sent over the wire.
-
-        After writing command byte, writes 'data' to MOSI and then
-        reads back 'read_bits' of reply on MISO. Result is a number.
-        """
-
-        # SPI_USR register flags
-        SPI_USR_COMMAND = (1 << 31)
-        SPI_USR_MISO    = (1 << 28)
-        SPI_USR_MOSI    = (1 << 27)
-
-        # SPI registers, base address differs ESP32 vs 8266
-        base = self.SPI_REG_BASE
-        SPI_CMD_REG       = base + 0x00
-        SPI_USR_REG       = base + 0x1C
-        SPI_USR1_REG      = base + 0x20
-        SPI_USR2_REG      = base + 0x24
-        SPI_W0_REG        = base + self.SPI_W0_OFFS
-
-        # following two registers are ESP32 only
-        if self.SPI_HAS_MOSI_DLEN_REG:
-            # ESP32 has a more sophisticated wayto set up "user" commands
-            def set_data_lengths(mosi_bits, miso_bits):
-                SPI_MOSI_DLEN_REG = base + 0x28
-                SPI_MISO_DLEN_REG = base + 0x2C
-                if mosi_bits > 0:
-                    self.write_reg(SPI_MOSI_DLEN_REG, mosi_bits - 1)
-                if miso_bits > 0:
-                    self.write_reg(SPI_MISO_DLEN_REG, miso_bits - 1)
-        else:
-
-            def set_data_lengths(mosi_bits, miso_bits):
-                SPI_DATA_LEN_REG = SPI_USR1_REG
-                SPI_MOSI_BITLEN_S = 17
-                SPI_MISO_BITLEN_S = 8
-                mosi_mask = 0 if (mosi_bits == 0) else (mosi_bits - 1)
-                miso_mask = 0 if (miso_bits == 0) else (miso_bits - 1)
-                self.write_reg(SPI_DATA_LEN_REG,
-                               (miso_mask << SPI_MISO_BITLEN_S) | (
-                                   mosi_mask << SPI_MOSI_BITLEN_S))
-
-        # SPI peripheral "command" bitmasks for SPI_CMD_REG
-        SPI_CMD_USR  = (1 << 18)
-
-        # shift values
-        SPI_USR2_DLEN_SHIFT = 28
-
-        if read_bits > 32:
-            raise FatalError("Reading more than 32 bits back from a SPI flash operation is unsupported")
-        if len(data) > 64:
-            raise FatalError("Writing more than 64 bytes of data with one SPI command is unsupported")
-
-        data_bits = len(data) * 8
-        old_spi_usr = self.read_reg(SPI_USR_REG)
-        old_spi_usr2 = self.read_reg(SPI_USR2_REG)
-        flags = SPI_USR_COMMAND
-        if read_bits > 0:
-            flags |= SPI_USR_MISO
-        if data_bits > 0:
-            flags |= SPI_USR_MOSI
-        set_data_lengths(data_bits, read_bits)
-        self.write_reg(SPI_USR_REG, flags)
-        self.write_reg(SPI_USR2_REG,
-                       (7 << SPI_USR2_DLEN_SHIFT) | spiflash_command)
-        if data_bits == 0:
-            self.write_reg(SPI_W0_REG, 0)  # clear data register before we read it
-        else:
-            data = pad_to(data, 4, b'\00')  # pad to 32-bit multiple
-            words = struct.unpack("I" * (len(data) // 4), data)
-            next_reg = SPI_W0_REG
-            for word in words:
-                self.write_reg(next_reg, word)
-                next_reg += 4
-        self.write_reg(SPI_CMD_REG, SPI_CMD_USR)
-
-        def wait_done():
-            for _ in range(10):
-                if (self.read_reg(SPI_CMD_REG) & SPI_CMD_USR) == 0:
-                    return
-            raise FatalError("SPI command did not complete in time")
-        wait_done()
-
-        status = self.read_reg(SPI_W0_REG)
-        # restore some SPI controller registers
-        self.write_reg(SPI_USR_REG, old_spi_usr)
-        self.write_reg(SPI_USR2_REG, old_spi_usr2)
-        return status
-
-    def read_status(self, num_bytes=2):
-        """Read up to 24 bits (num_bytes) of SPI flash status register contents
-        via RDSR, RDSR2, RDSR3 commands
-
-        Not all SPI flash supports all three commands. The upper 1 or 2
-        bytes may be 0xFF.
-        """
-        SPIFLASH_RDSR  = 0x05
-        SPIFLASH_RDSR2 = 0x35
-        SPIFLASH_RDSR3 = 0x15
-
-        status = 0
-        shift = 0
-        for cmd in [SPIFLASH_RDSR, SPIFLASH_RDSR2, SPIFLASH_RDSR3][0:num_bytes]:
-            status += self.run_spiflash_command(cmd, read_bits=8) << shift
-            shift += 8
-        return status
-
-    def write_status(self, new_status, num_bytes=2, set_non_volatile=False):
-        """Write up to 24 bits (num_bytes) of new status register
-
-        num_bytes can be 1, 2 or 3.
-
-        Not all flash supports the additional commands to write the
-        second and third byte of the status register. When writing 2
-        bytes, esptool also sends a 16-byte WRSR command (as some
-        flash types use this instead of WRSR2.)
-
-        If the set_non_volatile flag is set, non-volatile bits will
-        be set as well as volatile ones (WREN used instead of WEVSR).
-
-        """
-        SPIFLASH_WRSR = 0x01
-        SPIFLASH_WRSR2 = 0x31
-        SPIFLASH_WRSR3 = 0x11
-        SPIFLASH_WEVSR = 0x50
-        SPIFLASH_WREN = 0x06
-        SPIFLASH_WRDI = 0x04
-
-        enable_cmd = SPIFLASH_WREN if set_non_volatile else SPIFLASH_WEVSR
-
-        # try using a 16-bit WRSR (not supported by all chips)
-        # this may be redundant, but shouldn't hurt
-        if num_bytes == 2:
-            self.run_spiflash_command(enable_cmd)
-            self.run_spiflash_command(SPIFLASH_WRSR, struct.pack("<H", new_status))
-
-        # also try using individual commands (also not supported by all chips for num_bytes 2 & 3)
-        for cmd in [SPIFLASH_WRSR, SPIFLASH_WRSR2, SPIFLASH_WRSR3][0:num_bytes]:
-            self.run_spiflash_command(enable_cmd)
-            self.run_spiflash_command(cmd, struct.pack("B", new_status & 0xFF))
-            new_status >>= 8
-
-        self.run_spiflash_command(SPIFLASH_WRDI)
-
-    def get_crystal_freq(self):
-        # Figure out the crystal frequency from the UART clock divider
-        # Returns a normalized value in integer MHz (40 or 26 are the only supported values)
-        #
-        # The logic here is:
-        # - We know that our baud rate and the ESP UART baud rate are roughly the same, or we couldn't communicate
-        # - We can read the UART clock divider register to know how the ESP derives this from the APB bus frequency
-        # - Multiplying these two together gives us the bus frequency which is either the crystal frequency (ESP32)
-        #   or double the crystal frequency (ESP8266). See the self.XTAL_CLK_DIVIDER parameter for this factor.
-        uart_div = self.read_reg(self.UART_CLKDIV_REG) & self.UART_CLKDIV_MASK
-        est_xtal = (self._port.baudrate * uart_div) / 1e6 / self.XTAL_CLK_DIVIDER
-        norm_xtal = 40 if est_xtal > 33 else 26
-        if abs(norm_xtal - est_xtal) > 1:
-            print("WARNING: Detected crystal freq %.2fMHz is quite different to normalized freq %dMHz. Unsupported crystal in use?" % (est_xtal, norm_xtal))
-        return norm_xtal
-
-    def hard_reset(self):
-        self._setRTS(True)  # EN->LOW
-        time.sleep(0.1)
-        self._setRTS(False)
-
-    def soft_reset(self, stay_in_bootloader):
-        if not self.IS_STUB:
-            if stay_in_bootloader:
-                return  # ROM bootloader is already in bootloader!
-            else:
-                # 'run user code' is as close to a soft reset as we can do
-                self.flash_begin(0, 0)
-                self.flash_finish(False)
-        else:
-            if stay_in_bootloader:
-                # soft resetting from the stub loader
-                # will re-load the ROM bootloader
-                self.flash_begin(0, 0)
-                self.flash_finish(True)
-            elif self.CHIP_NAME != "ESP8266":
-                raise FatalError("Soft resetting is currently only supported on ESP8266")
-            else:
-                # running user code from stub loader requires some hacks
-                # in the stub loader
-                self.command(self.ESP_RUN_USER_CODE, wait_response=False)
-
-
-class ESP8266ROM(ESPLoader):
-    """ Access class for ESP8266 ROM bootloader
-    """
-    CHIP_NAME = "ESP8266"
-    IS_STUB = False
-
-    DATE_REG_VALUE = 0x00062000
-
-    # OTP ROM addresses
-    ESP_OTP_MAC0    = 0x3ff00050
-    ESP_OTP_MAC1    = 0x3ff00054
-    ESP_OTP_MAC3    = 0x3ff0005c
-
-    SPI_REG_BASE    = 0x60000200
-    SPI_W0_OFFS     = 0x40
-    SPI_HAS_MOSI_DLEN_REG = False
-
-    UART_CLKDIV_REG = 0x60000014
-
-    XTAL_CLK_DIVIDER = 2
-
-    FLASH_SIZES = {
-        '512KB':0x00,
-        '256KB':0x10,
-        '1MB':0x20,
-        '2MB':0x30,
-        '4MB':0x40,
-        '2MB-c1': 0x50,
-        '4MB-c1':0x60,
-        '8MB':0x80,
-        '16MB':0x90,
-    }
-
-    BOOTLOADER_FLASH_OFFSET = 0
-
-    MEMORY_MAP = [[0x3FF00000, 0x3FF00010, "DPORT"],
-                  [0x3FFE8000, 0x40000000, "DRAM"],
-                  [0x40100000, 0x40108000, "IRAM"],
-                  [0x40201010, 0x402E1010, "IROM"]]
-
-    def get_efuses(self):
-        # Return the 128 bits of ESP8266 efuse as a single Python integer
-        return (self.read_reg(0x3ff0005c) << 96 |
-                self.read_reg(0x3ff00058) << 64 |
-                self.read_reg(0x3ff00054) << 32 |
-                self.read_reg(0x3ff00050))
-
-    def get_chip_description(self):
-        efuses = self.get_efuses()
-        is_8285 = (efuses & ((1 << 4) | 1 << 80)) != 0  # One or the other efuse bit is set for ESP8285
-        return "ESP8285" if is_8285 else "ESP8266EX"
-
-    def get_chip_features(self):
-        features = ["WiFi"]
-        if self.get_chip_description() == "ESP8285":
-            features += ["Embedded Flash"]
-        return features
-
-    def flash_spi_attach(self, hspi_arg):
-        if self.IS_STUB:
-            super(ESP8266ROM, self).flash_spi_attach(hspi_arg)
-        else:
-            # ESP8266 ROM has no flash_spi_attach command in serial protocol,
-            # but flash_begin will do it
-            self.flash_begin(0, 0)
-
-    def flash_set_parameters(self, size):
-        # not implemented in ROM, but OK to silently skip for ROM
-        if self.IS_STUB:
-            super(ESP8266ROM, self).flash_set_parameters(size)
-
-    def chip_id(self):
-        """ Read Chip ID from efuse - the equivalent of the SDK system_get_chip_id() function """
-        id0 = self.read_reg(self.ESP_OTP_MAC0)
-        id1 = self.read_reg(self.ESP_OTP_MAC1)
-        return (id0 >> 24) | ((id1 & MAX_UINT24) << 8)
-
-    def read_mac(self):
-        """ Read MAC from OTP ROM """
-        mac0 = self.read_reg(self.ESP_OTP_MAC0)
-        mac1 = self.read_reg(self.ESP_OTP_MAC1)
-        mac3 = self.read_reg(self.ESP_OTP_MAC3)
-        if (mac3 != 0):
-            oui = ((mac3 >> 16) & 0xff, (mac3 >> 8) & 0xff, mac3 & 0xff)
-        elif ((mac1 >> 16) & 0xff) == 0:
-            oui = (0x18, 0xfe, 0x34)
-        elif ((mac1 >> 16) & 0xff) == 1:
-            oui = (0xac, 0xd0, 0x74)
-        else:
-            raise FatalError("Unknown OUI")
-        return oui + ((mac1 >> 8) & 0xff, mac1 & 0xff, (mac0 >> 24) & 0xff)
-
-    def get_erase_size(self, offset, size):
-        """ Calculate an erase size given a specific size in bytes.
-
-        Provides a workaround for the bootloader erase bug."""
-
-        sectors_per_block = 16
-        sector_size = self.FLASH_SECTOR_SIZE
-        num_sectors = (size + sector_size - 1) // sector_size
-        start_sector = offset // sector_size
-
-        head_sectors = sectors_per_block - (start_sector % sectors_per_block)
-        if num_sectors < head_sectors:
-            head_sectors = num_sectors
-
-        if num_sectors < 2 * head_sectors:
-            return (num_sectors + 1) // 2 * sector_size
-        else:
-            return (num_sectors - head_sectors) * sector_size
-
-    def override_vddsdio(self, new_voltage):
-        raise NotImplementedInROMError("Overriding VDDSDIO setting only applies to ESP32")
-
-
-class ESP8266StubLoader(ESP8266ROM):
-    """ Access class for ESP8266 stub loader, runs on top of ROM.
-    """
-    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
-    IS_STUB = True
-
-    def __init__(self, rom_loader):
-        self._port = rom_loader._port
-        self._trace_enabled = rom_loader._trace_enabled
-        self.flush_input()  # resets _slip_reader
-
-    def get_erase_size(self, offset, size):
-        return size  # stub doesn't have same size bug as ROM loader
-
-
-ESP8266ROM.STUB_CLASS = ESP8266StubLoader
-
-
-class ESP32ROM(ESPLoader):
-    """Access class for ESP32 ROM bootloader
-
-    """
-    CHIP_NAME = "ESP32"
-    IMAGE_CHIP_ID = 0
-    IS_STUB = False
-
-    DATE_REG_VALUE = 0x15122500
-
-    IROM_MAP_START = 0x400d0000
-    IROM_MAP_END   = 0x40400000
-    DROM_MAP_START = 0x3F400000
-    DROM_MAP_END   = 0x3F800000
-
-    # ESP32 uses a 4 byte status reply
-    STATUS_BYTES_LENGTH = 4
-
-    SPI_REG_BASE   = 0x60002000
-    EFUSE_REG_BASE = 0x6001a000
-
-    DR_REG_SYSCON_BASE = 0x3ff66000
-
-    SPI_W0_OFFS = 0x80
-    SPI_HAS_MOSI_DLEN_REG = True
-
-    UART_CLKDIV_REG = 0x3ff40014
-
-    XTAL_CLK_DIVIDER = 1
-
-    FLASH_SIZES = {
-        '1MB':0x00,
-        '2MB':0x10,
-        '4MB':0x20,
-        '8MB':0x30,
-        '16MB':0x40
-    }
-
-    BOOTLOADER_FLASH_OFFSET = 0x1000
-
-    OVERRIDE_VDDSDIO_CHOICES = ["1.8V", "1.9V", "OFF"]
-
-    MEMORY_MAP = [[0x3F400000, 0x3F800000, "DROM"],
-                  [0x3F800000, 0x3FC00000, "EXTRAM_DATA"],
-                  [0x3FF80000, 0x3FF82000, "RTC_DRAM"],
-                  [0x3FF90000, 0x40000000, "BYTE_ACCESSIBLE"],
-                  [0x3FFAE000, 0x40000000, "DRAM"],
-                  [0x3FFAE000, 0x40000000, "DMA"],
-                  [0x3FFE0000, 0x3FFFFFFC, "DIRAM_DRAM"],
-                  [0x40000000, 0x40070000, "IROM"],
-                  [0x40070000, 0x40078000, "CACHE_PRO"],
-                  [0x40078000, 0x40080000, "CACHE_APP"],
-                  [0x40080000, 0x400A0000, "IRAM"],
-                  [0x400A0000, 0x400BFFFC, "DIRAM_IRAM"],
-                  [0x400C0000, 0x400C2000, "RTC_IRAM"],
-                  [0x400D0000, 0x40400000, "IROM"],
-                  [0x50000000, 0x50002000, "RTC_DATA"]]
-
-    """ Try to read the BLOCK1 (encryption key) and check if it is valid """
-
-    def is_flash_encryption_key_valid(self):
-
-        """ Bit 0 of efuse_rd_disable[3:0] is mapped to BLOCK1
-        this bit is at position 16 in EFUSE_BLK0_RDATA0_REG """
-        word0 = self.read_efuse(0)
-        rd_disable = (word0 >> 16) & 0x1
-
-        # reading of BLOCK1 is NOT ALLOWED so we assume valid key is programmed
-        if rd_disable:
-            return True
-        else:
-            """ reading of BLOCK1 is ALLOWED so we will read and verify for non-zero.
-            When ESP32 has not generated AES/encryption key in BLOCK1, the contents will be readable and 0.
-            If the flash encryption is enabled it is expected to have a valid non-zero key. We break out on
-            first occurance of non-zero value """
-            key_word = [0] * 7
-            for i in range(len(key_word)):
-                key_word[i] = self.read_efuse(14 + i)
-                # key is non-zero so break & return
-                if key_word[i] != 0:
-                    return True
-            return False
-
-    """ For flash encryption related commands we need to make sure
-    user has programmed all the relevant efuse correctly so at
-    the end of write_flash_encrypt esptool will verify the values
-    of flash_crypt_config to be non zero if they are not read
-    protected. If the values are zero a warning will be printed
-    """
-
-    def get_flash_crypt_config(self):
-        """ bit 3 in efuse_rd_disable[3:0] is mapped to flash_crypt_config
-        this bit is at position 19 in EFUSE_BLK0_RDATA0_REG """
-        word0 = self.read_efuse(0)
-        rd_disable = (word0 >> 19) & 0x1
-
-        if rd_disable == 0:
-            """ we can read the flash_crypt_config efuse value
-            so go & read it (EFUSE_BLK0_RDATA5_REG[31:28]) """
-            word5 = self.read_efuse(5)
-            word5 = (word5 >> 28) & 0xF
-            return word5
-        else:
-            # if read of the efuse is disabled we assume it is set correctly
-            return 0xF
-
-    def get_chip_description(self):
-        word3 = self.read_efuse(3)
-        word5 = self.read_efuse(5)
-        apb_ctl_date = self.read_reg(self.DR_REG_SYSCON_BASE + 0x7C)
-        rev_bit0 = (word3 >> 15) & 0x1
-        rev_bit1 = (word5 >> 20) & 0x1
-        rev_bit2 = (apb_ctl_date >> 31) & 0x1
-        pkg_version = (word3 >> 9) & 0x07
-
-        chip_name = {
-            0: "ESP32D0WDQ6",
-            1: "ESP32D0WDQ5",
-            2: "ESP32D2WDQ5",
-            5: "ESP32-PICO-D4",
-        }.get(pkg_version, "unknown ESP32")
-
-        chip_revision = 0
-        if rev_bit0:
-            if rev_bit1:
-                if rev_bit2:
-                    chip_revision = 3
-                else:
-                    chip_revision = 2
-            else:
-                chip_revision = 1
-        return "%s (revision %d)" % (chip_name, chip_revision)
-
-    def get_chip_features(self):
-        features = ["WiFi"]
-        word3 = self.read_efuse(3)
-
-        # names of variables in this section are lowercase
-        #  versions of EFUSE names as documented in TRM and
-        # ESP-IDF efuse_reg.h
-
-        chip_ver_dis_bt = word3 & (1 << 1)
-        if chip_ver_dis_bt == 0:
-            features += ["BT"]
-
-        chip_ver_dis_app_cpu = word3 & (1 << 0)
-        if chip_ver_dis_app_cpu:
-            features += ["Single Core"]
-        else:
-            features += ["Dual Core"]
-
-        chip_cpu_freq_rated = word3 & (1 << 13)
-        if chip_cpu_freq_rated:
-            chip_cpu_freq_low = word3 & (1 << 12)
-            if chip_cpu_freq_low:
-                features += ["160MHz"]
-            else:
-                features += ["240MHz"]
-
-        pkg_version = (word3 >> 9) & 0x07
-        if pkg_version in [2, 4, 5]:
-            features += ["Embedded Flash"]
-
-        word4 = self.read_efuse(4)
-        adc_vref = (word4 >> 8) & 0x1F
-        if adc_vref:
-            features += ["VRef calibration in efuse"]
-
-        blk3_part_res = word3 >> 14 & 0x1
-        if blk3_part_res:
-            features += ["BLK3 partially reserved"]
-
-        word6 = self.read_efuse(6)
-        coding_scheme = word6 & 0x3
-        features += ["Coding Scheme %s" % {
-            0: "None",
-            1: "3/4",
-            2: "Repeat (UNSUPPORTED)",
-            3: "Invalid"}[coding_scheme]]
-
-        return features
-
-    def read_efuse(self, n):
-        """ Read the nth word of the ESP3x EFUSE region. """
-        return self.read_reg(self.EFUSE_REG_BASE + (4 * n))
-
-    def chip_id(self):
-        raise NotSupportedError(self, "chip_id")
-
-    def read_mac(self):
-        """ Read MAC from EFUSE region """
-        words = [self.read_efuse(2), self.read_efuse(1)]
-        bitstring = struct.pack(">II", *words)
-        bitstring = bitstring[2:8]  # trim the 2 byte CRC
-        try:
-            return tuple(ord(b) for b in bitstring)
-        except TypeError:  # Python 3, bitstring elements are already bytes
-            return tuple(bitstring)
-
-    def get_erase_size(self, offset, size):
-        return size
-
-    def override_vddsdio(self, new_voltage):
-        new_voltage = new_voltage.upper()
-        if new_voltage not in self.OVERRIDE_VDDSDIO_CHOICES:
-            raise FatalError("The only accepted VDDSDIO overrides are '1.8V', '1.9V' and 'OFF'")
-        RTC_CNTL_SDIO_CONF_REG = 0x3ff48074
-        RTC_CNTL_XPD_SDIO_REG = (1 << 31)
-        RTC_CNTL_DREFH_SDIO_M = (3 << 29)
-        RTC_CNTL_DREFM_SDIO_M = (3 << 27)
-        RTC_CNTL_DREFL_SDIO_M = (3 << 25)
-        # RTC_CNTL_SDIO_TIEH = (1 << 23)  # not used here, setting TIEH=1 would set 3.3V output, not safe for esptool.py to do
-        RTC_CNTL_SDIO_FORCE = (1 << 22)
-        RTC_CNTL_SDIO_PD_EN = (1 << 21)
-
-        reg_val = RTC_CNTL_SDIO_FORCE  # override efuse setting
-        reg_val |= RTC_CNTL_SDIO_PD_EN
-        if new_voltage != "OFF":
-            reg_val |= RTC_CNTL_XPD_SDIO_REG  # enable internal LDO
-        if new_voltage == "1.9V":
-            reg_val |= (RTC_CNTL_DREFH_SDIO_M | RTC_CNTL_DREFM_SDIO_M | RTC_CNTL_DREFL_SDIO_M)  # boost voltage
-        self.write_reg(RTC_CNTL_SDIO_CONF_REG, reg_val)
-        print("VDDSDIO regulator set to %s" % new_voltage)
-
-
-class ESP32StubLoader(ESP32ROM):
-    """ Access class for ESP32 stub loader, runs on top of ROM.
-    """
-    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
-    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
-    IS_STUB = True
-
-    def __init__(self, rom_loader):
-        self._port = rom_loader._port
-        self._trace_enabled = rom_loader._trace_enabled
-        self.flush_input()  # resets _slip_reader
-
-
-ESP32ROM.STUB_CLASS = ESP32StubLoader
-
-
-class ESPBOOTLOADER(object):
-    """ These are constants related to software ESP bootloader, working with 'v2' image files """
-
-    # First byte of the "v2" application image
-    IMAGE_V2_MAGIC = 0xea
-
-    # First 'segment' value in a "v2" application image, appears to be a constant version value?
-    IMAGE_V2_SEGMENT = 4
-
-
-def LoadFirmwareImage(chip, filename):
-    """ Load a firmware image. Can be for ESP8266 or ESP32. ESP8266 images will be examined to determine if they are
-        original ROM firmware images (ESP8266ROMFirmwareImage) or "v2" OTA bootloader images.
-
-        Returns a BaseFirmwareImage subclass, either ESP8266ROMFirmwareImage (v1) or ESP8266V2FirmwareImage (v2).
-    """
-    with open(filename, 'rb') as f:
-        if chip.lower() == 'esp32':
-            return ESP32FirmwareImage(f)
-        else:  # Otherwise, ESP8266 so look at magic to determine the image type
-            magic = ord(f.read(1))
-            f.seek(0)
-            if magic == ESPLoader.ESP_IMAGE_MAGIC:
-                return ESP8266ROMFirmwareImage(f)
-            elif magic == ESPBOOTLOADER.IMAGE_V2_MAGIC:
-                return ESP8266V2FirmwareImage(f)
-            else:
-                raise FatalError("Invalid image magic number: %d" % magic)
-
-
-class ImageSegment(object):
-    """ Wrapper class for a segment in an ESP image
-    (very similar to a section in an ELFImage also) """
-    def __init__(self, addr, data, file_offs=None):
-        self.addr = addr
-        self.data = data
-        self.file_offs = file_offs
-        self.include_in_checksum = True
-        if self.addr != 0:
-            self.pad_to_alignment(4)  # pad all "real" ImageSegments 4 byte aligned length
-
-    def copy_with_new_addr(self, new_addr):
-        """ Return a new ImageSegment with same data, but mapped at
-        a new address. """
-        return ImageSegment(new_addr, self.data, 0)
-
-    def split_image(self, split_len):
-        """ Return a new ImageSegment which splits "split_len" bytes
-        from the beginning of the data. Remaining bytes are kept in
-        this segment object (and the start address is adjusted to match.) """
-        result = copy.copy(self)
-        result.data = self.data[:split_len]
-        self.data = self.data[split_len:]
-        self.addr += split_len
-        self.file_offs = None
-        result.file_offs = None
-        return result
-
-    def __repr__(self):
-        r = "len 0x%05x load 0x%08x" % (len(self.data), self.addr)
-        if self.file_offs is not None:
-            r += " file_offs 0x%08x" % (self.file_offs)
-        return r
-
-    def pad_to_alignment(self, alignment):
-        self.data = pad_to(self.data, alignment, b'\x00')
-
-
-class ELFSection(ImageSegment):
-    """ Wrapper class for a section in an ELF image, has a section
-    name as well as the common properties of an ImageSegment. """
-    def __init__(self, name, addr, data):
-        super(ELFSection, self).__init__(addr, data)
-        self.name = name.decode("utf-8")
-
-    def __repr__(self):
-        return "%s %s" % (self.name, super(ELFSection, self).__repr__())
-
-
-class BaseFirmwareImage(object):
-    SEG_HEADER_LEN = 8
-    SHA256_DIGEST_LEN = 32
-
-    """ Base class with common firmware image functions """
-    def __init__(self):
-        self.segments = []
-        self.entrypoint = 0
-        self.elf_sha256 = None
-        self.elf_sha256_offset = 0
-
-    def load_common_header(self, load_file, expected_magic):
-        (magic, segments, self.flash_mode, self.flash_size_freq, self.entrypoint) = struct.unpack('<BBBBI', load_file.read(8))
-
-        if magic != expected_magic:
-            raise FatalError('Invalid firmware image magic=0x%x' % (magic))
-        return segments
-
-    def verify(self):
-        if len(self.segments) > 16:
-            raise FatalError('Invalid segment count %d (max 16). Usually this indicates a linker script problem.' % len(self.segments))
-
-    def load_segment(self, f, is_irom_segment=False):
-        """ Load the next segment from the image file """
-        file_offs = f.tell()
-        (offset, size) = struct.unpack('<II', f.read(8))
-        self.warn_if_unusual_segment(offset, size, is_irom_segment)
-        segment_data = f.read(size)
-        if len(segment_data) < size:
-            raise FatalError('End of file reading segment 0x%x, length %d (actual length %d)' % (offset, size, len(segment_data)))
-        segment = ImageSegment(offset, segment_data, file_offs)
-        self.segments.append(segment)
-        return segment
-
-    def warn_if_unusual_segment(self, offset, size, is_irom_segment):
-        if not is_irom_segment:
-            if offset > 0x40200000 or offset < 0x3ffe0000 or size > 65536:
-                print('WARNING: Suspicious segment 0x%x, length %d' % (offset, size))
-
-    def maybe_patch_segment_data(self, f, segment_data):
-        """If SHA256 digest of the ELF file needs to be inserted into this segment, do so. Returns segment data."""
-        segment_len = len(segment_data)
-        file_pos = f.tell()  # file_pos is position in the .bin file
-        if self.elf_sha256_offset >= file_pos and self.elf_sha256_offset < file_pos + segment_len:
-            # SHA256 digest needs to be patched into this binary segment,
-            # calculate offset of the digest inside the binary segment.
-            patch_offset = self.elf_sha256_offset - file_pos
-            # Sanity checks
-            if patch_offset < self.SEG_HEADER_LEN or patch_offset + self.SHA256_DIGEST_LEN > segment_len:
-                raise FatalError('Cannot place SHA256 digest on segment boundary' +
-                                 '(elf_sha256_offset=%d, file_pos=%d, segment_size=%d)' %
-                                 (self.elf_sha256_offset, file_pos, segment_len))
-            if segment_data[patch_offset:patch_offset + self.SHA256_DIGEST_LEN] != b'\x00' * self.SHA256_DIGEST_LEN:
-                raise FatalError('Contents of segment at SHA256 digest offset 0x%x are not all zero. Refusing to overwrite.' %
-                                 self.elf_sha256_offset)
-            assert(len(self.elf_sha256) == self.SHA256_DIGEST_LEN)
-            # offset relative to the data part
-            patch_offset -= self.SEG_HEADER_LEN
-            segment_data = segment_data[0:patch_offset] + self.elf_sha256 + \
-                segment_data[patch_offset + self.SHA256_DIGEST_LEN:]
-        return segment_data
-
-    def save_segment(self, f, segment, checksum=None):
-        """ Save the next segment to the image file, return next checksum value if provided """
-        segment_data = self.maybe_patch_segment_data(f, segment.data)
-        f.write(struct.pack('<II', segment.addr, len(segment_data)))
-        f.write(segment_data)
-        if checksum is not None:
-            return ESPLoader.checksum(segment_data, checksum)
-
-    def read_checksum(self, f):
-        """ Return ESPLoader checksum from end of just-read image """
-        # Skip the padding. The checksum is stored in the last byte so that the
-        # file is a multiple of 16 bytes.
-        align_file_position(f, 16)
-        return ord(f.read(1))
-
-    def calculate_checksum(self):
-        """ Calculate checksum of loaded image, based on segments in
-        segment array.
-        """
-        checksum = ESPLoader.ESP_CHECKSUM_MAGIC
-        for seg in self.segments:
-            if seg.include_in_checksum:
-                checksum = ESPLoader.checksum(seg.data, checksum)
-        return checksum
-
-    def append_checksum(self, f, checksum):
-        """ Append ESPLoader checksum to the just-written image """
-        align_file_position(f, 16)
-        f.write(struct.pack(b'B', checksum))
-
-    def write_common_header(self, f, segments):
-        f.write(struct.pack('<BBBBI', ESPLoader.ESP_IMAGE_MAGIC, len(segments),
-                            self.flash_mode, self.flash_size_freq, self.entrypoint))
-
-    def is_irom_addr(self, addr):
-        """ Returns True if an address starts in the irom region.
-        Valid for ESP8266 only.
-        """
-        return ESP8266ROM.IROM_MAP_START <= addr < ESP8266ROM.IROM_MAP_END
-
-    def get_irom_segment(self):
-        irom_segments = [s for s in self.segments if self.is_irom_addr(s.addr)]
-        if len(irom_segments) > 0:
-            if len(irom_segments) != 1:
-                raise FatalError('Found %d segments that could be irom0. Bad ELF file?' % len(irom_segments))
-            return irom_segments[0]
-        return None
-
-    def get_non_irom_segments(self):
-        irom_segment = self.get_irom_segment()
-        return [s for s in self.segments if s != irom_segment]
-
-
-class ESP8266ROMFirmwareImage(BaseFirmwareImage):
-    """ 'Version 1' firmware image, segments loaded directly by the ROM bootloader. """
-
-    ROM_LOADER = ESP8266ROM
-
-    def __init__(self, load_file=None):
-        super(ESP8266ROMFirmwareImage, self).__init__()
-        self.flash_mode = 0
-        self.flash_size_freq = 0
-        self.version = 1
-
-        if load_file is not None:
-            segments = self.load_common_header(load_file, ESPLoader.ESP_IMAGE_MAGIC)
-
-            for _ in range(segments):
-                self.load_segment(load_file)
-            self.checksum = self.read_checksum(load_file)
-
-            self.verify()
-
-    def default_output_name(self, input_file):
-        """ Derive a default output name from the ELF name. """
-        return input_file + '-'
-
-    def save(self, basename):
-        """ Save a set of V1 images for flashing. Parameter is a base filename. """
-        # IROM data goes in its own plain binary file
-        irom_segment = self.get_irom_segment()
-        if irom_segment is not None:
-            with open("%s0x%05x.bin" % (basename, irom_segment.addr - ESP8266ROM.IROM_MAP_START), "wb") as f:
-                f.write(irom_segment.data)
-
-        # everything but IROM goes at 0x00000 in an image file
-        normal_segments = self.get_non_irom_segments()
-        with open("%s0x00000.bin" % basename, 'wb') as f:
-            self.write_common_header(f, normal_segments)
-            checksum = ESPLoader.ESP_CHECKSUM_MAGIC
-            for segment in normal_segments:
-                checksum = self.save_segment(f, segment, checksum)
-            self.append_checksum(f, checksum)
-
-
-ESP8266ROM.BOOTLOADER_IMAGE = ESP8266ROMFirmwareImage
-
-
-class ESP8266V2FirmwareImage(BaseFirmwareImage):
-    """ 'Version 2' firmware image, segments loaded by software bootloader stub
-        (ie Espressif bootloader or rboot)
-    """
-
-    ROM_LOADER = ESP8266ROM
-
-    def __init__(self, load_file=None):
-        super(ESP8266V2FirmwareImage, self).__init__()
-        self.version = 2
-        if load_file is not None:
-            segments = self.load_common_header(load_file, ESPBOOTLOADER.IMAGE_V2_MAGIC)
-            if segments != ESPBOOTLOADER.IMAGE_V2_SEGMENT:
-                # segment count is not really segment count here, but we expect to see '4'
-                print('Warning: V2 header has unexpected "segment" count %d (usually 4)' % segments)
-
-            # irom segment comes before the second header
-            #
-            # the file is saved in the image with a zero load address
-            # in the header, so we need to calculate a load address
-            irom_segment = self.load_segment(load_file, True)
-            irom_segment.addr = 0  # for actual mapped addr, add ESP8266ROM.IROM_MAP_START + flashing_addr + 8
-            irom_segment.include_in_checksum = False
-
-            first_flash_mode = self.flash_mode
-            first_flash_size_freq = self.flash_size_freq
-            first_entrypoint = self.entrypoint
-            # load the second header
-
-            segments = self.load_common_header(load_file, ESPLoader.ESP_IMAGE_MAGIC)
-
-            if first_flash_mode != self.flash_mode:
-                print('WARNING: Flash mode value in first header (0x%02x) disagrees with second (0x%02x). Using second value.'
-                      % (first_flash_mode, self.flash_mode))
-            if first_flash_size_freq != self.flash_size_freq:
-                print('WARNING: Flash size/freq value in first header (0x%02x) disagrees with second (0x%02x). Using second value.'
-                      % (first_flash_size_freq, self.flash_size_freq))
-            if first_entrypoint != self.entrypoint:
-                print('WARNING: Entrypoint address in first header (0x%08x) disagrees with second header (0x%08x). Using second value.'
-                      % (first_entrypoint, self.entrypoint))
-
-            # load all the usual segments
-            for _ in range(segments):
-                self.load_segment(load_file)
-            self.checksum = self.read_checksum(load_file)
-
-            self.verify()
-
-    def default_output_name(self, input_file):
-        """ Derive a default output name from the ELF name. """
-        irom_segment = self.get_irom_segment()
-        if irom_segment is not None:
-            irom_offs = irom_segment.addr - ESP8266ROM.IROM_MAP_START
-        else:
-            irom_offs = 0
-        return "%s-0x%05x.bin" % (os.path.splitext(input_file)[0],
-                                  irom_offs & ~(ESPLoader.FLASH_SECTOR_SIZE - 1))
-
-    def save(self, filename):
-        with open(filename, 'wb') as f:
-            # Save first header for irom0 segment
-            f.write(struct.pack(b'<BBBBI', ESPBOOTLOADER.IMAGE_V2_MAGIC, ESPBOOTLOADER.IMAGE_V2_SEGMENT,
-                                self.flash_mode, self.flash_size_freq, self.entrypoint))
-
-            irom_segment = self.get_irom_segment()
-            if irom_segment is not None:
-                # save irom0 segment, make sure it has load addr 0 in the file
-                irom_segment = irom_segment.copy_with_new_addr(0)
-                irom_segment.pad_to_alignment(16)  # irom_segment must end on a 16 byte boundary
-                self.save_segment(f, irom_segment)
-
-            # second header, matches V1 header and contains loadable segments
-            normal_segments = self.get_non_irom_segments()
-            self.write_common_header(f, normal_segments)
-            checksum = ESPLoader.ESP_CHECKSUM_MAGIC
-            for segment in normal_segments:
-                checksum = self.save_segment(f, segment, checksum)
-            self.append_checksum(f, checksum)
-
-        # calculate a crc32 of entire file and append
-        # (algorithm used by recent 8266 SDK bootloaders)
-        with open(filename, 'rb') as f:
-            crc = esp8266_crc32(f.read())
-        with open(filename, 'ab') as f:
-            f.write(struct.pack(b'<I', crc))
-
-
-# Backwards compatibility for previous API, remove in esptool.py V3
-ESPFirmwareImage = ESP8266ROMFirmwareImage
-OTAFirmwareImage = ESP8266V2FirmwareImage
-
-
-def esp8266_crc32(data):
-    """
-    CRC32 algorithm used by 8266 SDK bootloader (and gen_appbin.py).
-    """
-    crc = binascii.crc32(data, 0) & 0xFFFFFFFF
-    if crc & 0x80000000:
-        return crc ^ 0xFFFFFFFF
-    else:
-        return crc + 1
-
-
-class ESP32FirmwareImage(BaseFirmwareImage):
-    """ ESP32 firmware image is very similar to V1 ESP8266 image,
-    except with an additional 16 byte reserved header at top of image,
-    and because of new flash mapping capabilities the flash-mapped regions
-    can be placed in the normal image (just @ 64kB padded offsets).
-    """
-
-    ROM_LOADER = ESP32ROM
-
-    # ROM bootloader will read the wp_pin field if SPI flash
-    # pins are remapped via flash. IDF actually enables QIO only
-    # from software bootloader, so this can be ignored. But needs
-    # to be set to this value so ROM bootloader will skip it.
-    WP_PIN_DISABLED = 0xEE
-
-    EXTENDED_HEADER_STRUCT_FMT = "<BBBBHB" + ("B" * 8) + "B"
-
-    IROM_ALIGN = 65536
-
-    def __init__(self, load_file=None):
-        super(ESP32FirmwareImage, self).__init__()
-        self.secure_pad = False
-        self.flash_mode = 0
-        self.flash_size_freq = 0
-        self.version = 1
-        self.wp_pin = self.WP_PIN_DISABLED
-        # SPI pin drive levels
-        self.clk_drv = 0
-        self.q_drv = 0
-        self.d_drv = 0
-        self.cs_drv = 0
-        self.hd_drv = 0
-        self.wp_drv = 0
-        self.min_rev = 0
-
-        self.append_digest = True
-
-        if load_file is not None:
-            start = load_file.tell()
-
-            segments = self.load_common_header(load_file, ESPLoader.ESP_IMAGE_MAGIC)
-            self.load_extended_header(load_file)
-
-            for _ in range(segments):
-                self.load_segment(load_file)
-            self.checksum = self.read_checksum(load_file)
-
-            if self.append_digest:
-                end = load_file.tell()
-                self.stored_digest = load_file.read(32)
-                load_file.seek(start)
-                calc_digest = hashlib.sha256()
-                calc_digest.update(load_file.read(end - start))
-                self.calc_digest = calc_digest.digest()  # TODO: decide what to do here?
-
-            self.verify()
-
-    def is_flash_addr(self, addr):
-        return (ESP32ROM.IROM_MAP_START <= addr < ESP32ROM.IROM_MAP_END) \
-            or (ESP32ROM.DROM_MAP_START <= addr < ESP32ROM.DROM_MAP_END)
-
-    def default_output_name(self, input_file):
-        """ Derive a default output name from the ELF name. """
-        return "%s.bin" % (os.path.splitext(input_file)[0])
-
-    def warn_if_unusual_segment(self, offset, size, is_irom_segment):
-        pass  # TODO: add warnings for ESP32 segment offset/size combinations that are wrong
-
-    def save(self, filename):
-        total_segments = 0
-        with io.BytesIO() as f:  # write file to memory first
-            self.write_common_header(f, self.segments)
-
-            # first 4 bytes of header are read by ROM bootloader for SPI
-            # config, but currently unused
-            self.save_extended_header(f)
-
-            checksum = ESPLoader.ESP_CHECKSUM_MAGIC
-
-            # split segments into flash-mapped vs ram-loaded, and take copies so we can mutate them
-            flash_segments = [copy.deepcopy(s) for s in sorted(self.segments, key=lambda s:s.addr) if self.is_flash_addr(s.addr)]
-            ram_segments = [copy.deepcopy(s) for s in sorted(self.segments, key=lambda s:s.addr) if not self.is_flash_addr(s.addr)]
-
-            # check for multiple ELF sections that are mapped in the same flash mapping region.
-            # this is usually a sign of a broken linker script, but if you have a legitimate
-            # use case then let us know (we can merge segments here, but as a rule you probably
-            # want to merge them in your linker script.)
-            if len(flash_segments) > 0:
-                last_addr = flash_segments[0].addr
-                for segment in flash_segments[1:]:
-                    if segment.addr // self.IROM_ALIGN == last_addr // self.IROM_ALIGN:
-                        raise FatalError(("Segment loaded at 0x%08x lands in same 64KB flash mapping as segment loaded at 0x%08x. " +
-                                          "Can't generate binary. Suggest changing linker script or ELF to merge sections.") %
-                                         (segment.addr, last_addr))
-                    last_addr = segment.addr
-
-            def get_alignment_data_needed(segment):
-                # Actual alignment (in data bytes) required for a segment header: positioned so that
-                # after we write the next 8 byte header, file_offs % IROM_ALIGN == segment.addr % IROM_ALIGN
-                #
-                # (this is because the segment's vaddr may not be IROM_ALIGNed, more likely is aligned
-                # IROM_ALIGN+0x18 to account for the binary file header
-                align_past = (segment.addr % self.IROM_ALIGN) - self.SEG_HEADER_LEN
-                pad_len = (self.IROM_ALIGN - (f.tell() % self.IROM_ALIGN)) + align_past
-                if pad_len == 0 or pad_len == self.IROM_ALIGN:
-                    return 0  # already aligned
-
-                # subtract SEG_HEADER_LEN a second time, as the padding block has a header as well
-                pad_len -= self.SEG_HEADER_LEN
-                if pad_len < 0:
-                    pad_len += self.IROM_ALIGN
-                return pad_len
-
-            # try to fit each flash segment on a 64kB aligned boundary
-            # by padding with parts of the non-flash segments...
-            while len(flash_segments) > 0:
-                segment = flash_segments[0]
-                pad_len = get_alignment_data_needed(segment)
-                if pad_len > 0:  # need to pad
-                    if len(ram_segments) > 0 and pad_len > self.SEG_HEADER_LEN:
-                        pad_segment = ram_segments[0].split_image(pad_len)
-                        if len(ram_segments[0].data) == 0:
-                            ram_segments.pop(0)
-                    else:
-                        pad_segment = ImageSegment(0, b'\x00' * pad_len, f.tell())
-                    checksum = self.save_segment(f, pad_segment, checksum)
-                    total_segments += 1
-                else:
-                    # write the flash segment
-                    assert (f.tell() + 8) % self.IROM_ALIGN == segment.addr % self.IROM_ALIGN
-                    checksum = self.save_flash_segment(f, segment, checksum)
-                    flash_segments.pop(0)
-                    total_segments += 1
-
-            # flash segments all written, so write any remaining RAM segments
-            for segment in ram_segments:
-                checksum = self.save_segment(f, segment, checksum)
-                total_segments += 1
-
-            if self.secure_pad:
-                # pad the image so that after signing it will end on a a 64KB boundary.
-                # This ensures all mapped flash content will be verified.
-                if not self.append_digest:
-                    raise FatalError("secure_pad only applies if a SHA-256 digest is also appended to the image")
-                align_past = (f.tell() + self.SEG_HEADER_LEN) % self.IROM_ALIGN
-                # 16 byte aligned checksum (force the alignment to simplify calculations)
-                checksum_space = 16
-                # after checksum: SHA-256 digest + (to be added by signing process) version, signature + 12 trailing bytes due to alignment
-                space_after_checksum = 32 + 4 + 64 + 12
-                pad_len = (self.IROM_ALIGN - align_past - checksum_space - space_after_checksum) % self.IROM_ALIGN
-                pad_segment = ImageSegment(0, b'\x00' * pad_len, f.tell())
-
-                checksum = self.save_segment(f, pad_segment, checksum)
-                total_segments += 1
-
-            # done writing segments
-            self.append_checksum(f, checksum)
-            image_length = f.tell()
-
-            if self.secure_pad:
-                assert ((image_length + space_after_checksum) % self.IROM_ALIGN) == 0
-
-            # kinda hacky: go back to the initial header and write the new segment count
-            # that includes padding segments. This header is not checksummed
-            f.seek(1)
-            try:
-                f.write(chr(total_segments))
-            except TypeError:  # Python 3
-                f.write(bytes([total_segments]))
-
-            if self.append_digest:
-                # calculate the SHA256 of the whole file and append it
-                f.seek(0)
-                digest = hashlib.sha256()
-                digest.update(f.read(image_length))
-                f.write(digest.digest())
-
-            with open(filename, 'wb') as real_file:
-                real_file.write(f.getvalue())
-
-    def save_flash_segment(self, f, segment, checksum=None):
-        """ Save the next segment to the image file, return next checksum value if provided """
-        segment_end_pos = f.tell() + len(segment.data) + self.SEG_HEADER_LEN
-        segment_len_remainder = segment_end_pos % self.IROM_ALIGN
-        if segment_len_remainder < 0x24:
-            # Work around a bug in ESP-IDF 2nd stage bootloader, that it didn't map the
-            # last MMU page, if an IROM/DROM segment was < 0x24 bytes over the page boundary.
-            segment.data += b'\x00' * (0x24 - segment_len_remainder)
-        return self.save_segment(f, segment, checksum)
-
-    def load_extended_header(self, load_file):
-        def split_byte(n):
-            return (n & 0x0F, (n >> 4) & 0x0F)
-
-        fields = list(struct.unpack(self.EXTENDED_HEADER_STRUCT_FMT, load_file.read(16)))
-
-        self.wp_pin = fields[0]
-
-        # SPI pin drive stengths are two per byte
-        self.clk_drv, self.q_drv = split_byte(fields[1])
-        self.d_drv, self.cs_drv = split_byte(fields[2])
-        self.hd_drv, self.wp_drv = split_byte(fields[3])
-
-        chip_id = fields[4]
-        if chip_id != self.ROM_LOADER.IMAGE_CHIP_ID:
-            print(("Unexpected chip id in image. Expected %d but value was %d. " +
-                  "Is this image for a different chip model?") % (self.ROM_LOADER.IMAGE_CHIP_ID, chip_id))
-
-        # reserved fields in the middle should all be zero
-        if any(f for f in fields[6:-1] if f != 0):
-            print("Warning: some reserved header fields have non-zero values. This image may be from a newer esptool.py?")
-
-        append_digest = fields[-1]  # last byte is append_digest
-        if append_digest in [0, 1]:
-            self.append_digest = (append_digest == 1)
-        else:
-            raise RuntimeError("Invalid value for append_digest field (0x%02x). Should be 0 or 1.", append_digest)
-
-    def save_extended_header(self, save_file):
-        def join_byte(ln,hn):
-            return (ln & 0x0F) + ((hn & 0x0F) << 4)
-
-        append_digest = 1 if self.append_digest else 0
-
-        fields = [self.wp_pin,
-                  join_byte(self.clk_drv, self.q_drv),
-                  join_byte(self.d_drv, self.cs_drv),
-                  join_byte(self.hd_drv, self.wp_drv),
-                  self.ROM_LOADER.IMAGE_CHIP_ID,
-                  self.min_rev]
-        fields += [0] * 8  # padding
-        fields += [append_digest]
-
-        packed = struct.pack(self.EXTENDED_HEADER_STRUCT_FMT, *fields)
-        save_file.write(packed)
-
-
-ESP32ROM.BOOTLOADER_IMAGE = ESP32FirmwareImage
-
-
-class ELFFile(object):
-    SEC_TYPE_PROGBITS = 0x01
-    SEC_TYPE_STRTAB = 0x03
-
-    LEN_SEC_HEADER = 0x28
-
-    def __init__(self, name):
-        # Load sections from the ELF file
-        self.name = name
-        with open(self.name, 'rb') as f:
-            self._read_elf_file(f)
-
-    def get_section(self, section_name):
-        for s in self.sections:
-            if s.name == section_name:
-                return s
-        raise ValueError("No section %s in ELF file" % section_name)
-
-    def _read_elf_file(self, f):
-        # read the ELF file header
-        LEN_FILE_HEADER = 0x34
-        try:
-            (ident,_type,machine,_version,
-             self.entrypoint,_phoff,shoff,_flags,
-             _ehsize, _phentsize,_phnum, shentsize,
-             shnum,shstrndx) = struct.unpack("<16sHHLLLLLHHHHHH", f.read(LEN_FILE_HEADER))
-        except struct.error as e:
-            raise FatalError("Failed to read a valid ELF header from %s: %s" % (self.name, e))
-
-        if byte(ident, 0) != 0x7f or ident[1:4] != b'ELF':
-            raise FatalError("%s has invalid ELF magic header" % self.name)
-        if machine != 0x5e:
-            raise FatalError("%s does not appear to be an Xtensa ELF file. e_machine=%04x" % (self.name, machine))
-        if shentsize != self.LEN_SEC_HEADER:
-            raise FatalError("%s has unexpected section header entry size 0x%x (not 0x28)" % (self.name, shentsize, self.LEN_SEC_HEADER))
-        if shnum == 0:
-            raise FatalError("%s has 0 section headers" % (self.name))
-        self._read_sections(f, shoff, shnum, shstrndx)
-
-    def _read_sections(self, f, section_header_offs, section_header_count, shstrndx):
-        f.seek(section_header_offs)
-        len_bytes = section_header_count * self.LEN_SEC_HEADER
-        section_header = f.read(len_bytes)
-        if len(section_header) == 0:
-            raise FatalError("No section header found at offset %04x in ELF file." % section_header_offs)
-        if len(section_header) != (len_bytes):
-            raise FatalError("Only read 0x%x bytes from section header (expected 0x%x.) Truncated ELF file?" % (len(section_header), len_bytes))
-
-        # walk through the section header and extract all sections
-        section_header_offsets = range(0, len(section_header), self.LEN_SEC_HEADER)
-
-        def read_section_header(offs):
-            name_offs,sec_type,_flags,lma,sec_offs,size = struct.unpack_from("<LLLLLL", section_header[offs:])
-            return (name_offs, sec_type, lma, size, sec_offs)
-        all_sections = [read_section_header(offs) for offs in section_header_offsets]
-        prog_sections = [s for s in all_sections if s[1] == ELFFile.SEC_TYPE_PROGBITS]
-
-        # search for the string table section
-        if not (shstrndx * self.LEN_SEC_HEADER) in section_header_offsets:
-            raise FatalError("ELF file has no STRTAB section at shstrndx %d" % shstrndx)
-        _,sec_type,_,sec_size,sec_offs = read_section_header(shstrndx * self.LEN_SEC_HEADER)
-        if sec_type != ELFFile.SEC_TYPE_STRTAB:
-            print('WARNING: ELF file has incorrect STRTAB section type 0x%02x' % sec_type)
-        f.seek(sec_offs)
-        string_table = f.read(sec_size)
-
-        # build the real list of ELFSections by reading the actual section names from the
-        # string table section, and actual data for each section from the ELF file itself
-        def lookup_string(offs):
-            raw = string_table[offs:]
-            return raw[:raw.index(b'\x00')]
-
-        def read_data(offs,size):
-            f.seek(offs)
-            return f.read(size)
-
-        prog_sections = [ELFSection(lookup_string(n_offs), lma, read_data(offs, size)) for (n_offs, _type, lma, size, offs) in prog_sections
-                         if lma != 0 and size > 0]
-        self.sections = prog_sections
-
-    def sha256(self):
-        # return SHA256 hash of the input ELF file
-        sha256 = hashlib.sha256()
-        with open(self.name, 'rb') as f:
-            sha256.update(f.read())
-        return sha256.digest()
-
-
-def slip_reader(port, trace_function):
-    """Generator to read SLIP packets from a serial port.
-    Yields one full SLIP packet at a time, raises exception on timeout or invalid data.
-
-    Designed to avoid too many calls to serial.read(1), which can bog
-    down on slow systems.
-    """
-    partial_packet = None
-    in_escape = False
-    while True:
-        waiting = port.inWaiting()
-        read_bytes = port.read(1 if waiting == 0 else waiting)
-        if read_bytes == b'':
-            waiting_for = "header" if partial_packet is None else "content"
-            trace_function("Timed out waiting for packet %s", waiting_for)
-            raise FatalError("Timed out waiting for packet %s" % waiting_for)
-        trace_function("Read %d bytes: %s", len(read_bytes), HexFormatter(read_bytes))
-        for b in read_bytes:
-            if type(b) is int:
-                b = bytes([b])  # python 2/3 compat
-
-            if partial_packet is None:  # waiting for packet header
-                if b == b'\xc0':
-                    partial_packet = b""
-                else:
-                    trace_function("Read invalid data: %s", HexFormatter(read_bytes))
-                    trace_function("Remaining data in serial buffer: %s", HexFormatter(port.read(port.inWaiting())))
-                    raise FatalError('Invalid head of packet (0x%s)' % hexify(b))
-            elif in_escape:  # part-way through escape sequence
-                in_escape = False
-                if b == b'\xdc':
-                    partial_packet += b'\xc0'
-                elif b == b'\xdd':
-                    partial_packet += b'\xdb'
-                else:
-                    trace_function("Read invalid data: %s", HexFormatter(read_bytes))
-                    trace_function("Remaining data in serial buffer: %s", HexFormatter(port.read(port.inWaiting())))
-                    raise FatalError('Invalid SLIP escape (0xdb, 0x%s)' % (hexify(b)))
-            elif b == b'\xdb':  # start of escape sequence
-                in_escape = True
-            elif b == b'\xc0':  # end of packet
-                trace_function("Received full packet: %s", HexFormatter(partial_packet))
-                yield partial_packet
-                partial_packet = None
-            else:  # normal byte in packet
-                partial_packet += b
-
-
-def arg_auto_int(x):
-    return int(x, 0)
-
-
-def div_roundup(a, b):
-    """ Return a/b rounded up to nearest integer,
-    equivalent result to int(math.ceil(float(int(a)) / float(int(b))), only
-    without possible floating point accuracy errors.
-    """
-    return (int(a) + int(b) - 1) // int(b)
-
-
-def align_file_position(f, size):
-    """ Align the position in the file to the next block of specified size """
-    align = (size - 1) - (f.tell() % size)
-    f.seek(align, 1)
-
-
-def flash_size_bytes(size):
-    """ Given a flash size of the type passed in args.flash_size
-    (ie 512KB or 1MB) then return the size in bytes.
-    """
-    if "MB" in size:
-        return int(size[:size.index("MB")]) * 1024 * 1024
-    elif "KB" in size:
-        return int(size[:size.index("KB")]) * 1024
-    else:
-        raise FatalError("Unknown size %s" % size)
-
-
-def hexify(s, uppercase=True):
-    format_str = '%02X' if uppercase else '%02x'
-    if not PYTHON2:
-        return ''.join(format_str % c for c in s)
-    else:
-        return ''.join(format_str % ord(c) for c in s)
-
-
-class HexFormatter(object):
-    """
-    Wrapper class which takes binary data in its constructor
-    and returns a hex string as it's __str__ method.
-
-    This is intended for "lazy formatting" of trace() output
-    in hex format. Avoids overhead (significant on slow computers)
-    of generating long hex strings even if tracing is disabled.
-
-    Note that this doesn't save any overhead if passed as an
-    argument to "%", only when passed to trace()
-
-    If auto_split is set (default), any long line (> 16 bytes) will be
-    printed as separately indented lines, with ASCII decoding at the end
-    of each line.
-    """
-    def __init__(self, binary_string, auto_split=True):
-        self._s = binary_string
-        self._auto_split = auto_split
-
-    def __str__(self):
-        if self._auto_split and len(self._s) > 16:
-            result = ""
-            s = self._s
-            while len(s) > 0:
-                line = s[:16]
-                ascii_line = "".join(c if (c == ' ' or (c in string.printable and c not in string.whitespace))
-                                     else '.' for c in line.decode('ascii', 'replace'))
-                s = s[16:]
-                result += "\n    %-16s %-16s | %s" % (hexify(line[:8], False), hexify(line[8:], False), ascii_line)
-            return result
-        else:
-            return hexify(self._s, False)
-
-
-def pad_to(data, alignment, pad_character=b'\xFF'):
-    """ Pad to the next alignment boundary """
-    pad_mod = len(data) % alignment
-    if pad_mod != 0:
-        data += pad_character * (alignment - pad_mod)
-    return data
-
-
-class FatalError(RuntimeError):
-    """
-    Wrapper class for runtime errors that aren't caused by internal bugs, but by
-    ESP8266 responses or input content.
-    """
-    def __init__(self, message):
-        RuntimeError.__init__(self, message)
-
-    @staticmethod
-    def WithResult(message, result):
-        """
-        Return a fatal error object that appends the hex values of
-        'result' as a string formatted argument.
-        """
-        message += " (result was %s)" % hexify(result)
-        return FatalError(message)
-
-
-class NotImplementedInROMError(FatalError):
-    """
-    Wrapper class for the error thrown when a particular ESP bootloader function
-    is not implemented in the ROM bootloader.
-    """
-    def __init__(self, bootloader, func):
-        FatalError.__init__(self, "%s ROM does not support function %s." % (bootloader.CHIP_NAME, func.__name__))
-
-
-class NotSupportedError(FatalError):
-    def __init__(self, esp, function_name):
-        FatalError.__init__(self, "Function %s is not supported for %s." % (function_name, esp.CHIP_NAME))
-
-# "Operation" commands, executable at command line. One function each
-#
-# Each function takes either two args (<ESPLoader instance>, <args>) or a single <args>
-# argument.
-
-
-def load_ram(esp, args):
-    image = LoadFirmwareImage(esp.CHIP_NAME, args.filename)
-
-    print('RAM boot...')
-    for seg in image.segments:
-        size = len(seg.data)
-        print('Downloading %d bytes at %08x...' % (size, seg.addr), end=' ')
-        sys.stdout.flush()
-        esp.mem_begin(size, div_roundup(size, esp.ESP_RAM_BLOCK), esp.ESP_RAM_BLOCK, seg.addr)
-
-        seq = 0
-        while len(seg.data) > 0:
-            esp.mem_block(seg.data[0:esp.ESP_RAM_BLOCK], seq)
-            seg.data = seg.data[esp.ESP_RAM_BLOCK:]
-            seq += 1
-        print('done!')
-
-    print('All segments done, executing at %08x' % image.entrypoint)
-    esp.mem_finish(image.entrypoint)
-
-
-def read_mem(esp, args):
-    print('0x%08x = 0x%08x' % (args.address, esp.read_reg(args.address)))
-
-
-def write_mem(esp, args):
-    esp.write_reg(args.address, args.value, args.mask, 0)
-    print('Wrote %08x, mask %08x to %08x' % (args.value, args.mask, args.address))
-
-
-def dump_mem(esp, args):
-    with open(args.filename, 'wb') as f:
-        for i in range(args.size // 4):
-            d = esp.read_reg(args.address + (i * 4))
-            f.write(struct.pack(b'<I', d))
-            if f.tell() % 1024 == 0:
-                print('\r%d bytes read... (%d %%)' % (f.tell(),
-                                                      f.tell() * 100 // args.size),
-                      end=' ')
-            sys.stdout.flush()
-    print('Done!')
-
-
-def detect_flash_size(esp, args):
-    if args.flash_size == 'detect':
-        flash_id = esp.flash_id()
-        size_id = flash_id >> 16
-        args.flash_size = DETECTED_FLASH_SIZES.get(size_id)
-        if args.flash_size is None:
-            print('Warning: Could not auto-detect Flash size (FlashID=0x%x, SizeID=0x%x), defaulting to 4MB' % (flash_id, size_id))
-            args.flash_size = '4MB'
-        else:
-            print('Auto-detected Flash size:', args.flash_size)
-
-
-def _update_image_flash_params(esp, address, args, image):
-    """ Modify the flash mode & size bytes if this looks like an executable bootloader image  """
-    if len(image) < 8:
-        return image  # not long enough to be a bootloader image
-
-    # unpack the (potential) image header
-    magic, _, flash_mode, flash_size_freq = struct.unpack("BBBB", image[:4])
-    if address != esp.BOOTLOADER_FLASH_OFFSET:
-        return image  # not flashing bootloader offset, so don't modify this
-
-    if (args.flash_mode, args.flash_freq, args.flash_size) == ('keep',) * 3:
-        return image  # all settings are 'keep', not modifying anything
-
-    # easy check if this is an image: does it start with a magic byte?
-    if magic != esp.ESP_IMAGE_MAGIC:
-        print("Warning: Image file at 0x%x doesn't look like an image file, so not changing any flash settings." % address)
-        return image
-
-    # make sure this really is an image, and not just data that
-    # starts with esp.ESP_IMAGE_MAGIC (mostly a problem for encrypted
-    # images that happen to start with a magic byte
-    try:
-        test_image = esp.BOOTLOADER_IMAGE(io.BytesIO(image))
-        test_image.verify()
-    except Exception:
-        print("Warning: Image file at 0x%x is not a valid %s image, so not changing any flash settings." % (address,esp.CHIP_NAME))
-        return image
-
-    if args.flash_mode != 'keep':
-        flash_mode = {'qio':0, 'qout':1, 'dio':2, 'dout': 3}[args.flash_mode]
-
-    flash_freq = flash_size_freq & 0x0F
-    if args.flash_freq != 'keep':
-        flash_freq = {'40m':0, '26m':1, '20m':2, '80m': 0xf}[args.flash_freq]
-
-    flash_size = flash_size_freq & 0xF0
-    if args.flash_size != 'keep':
-        flash_size = esp.parse_flash_size_arg(args.flash_size)
-
-    flash_params = struct.pack(b'BB', flash_mode, flash_size + flash_freq)
-    if flash_params != image[2:4]:
-        print('Flash params set to 0x%04x' % struct.unpack(">H", flash_params))
-        image = image[0:2] + flash_params + image[4:]
-    return image
-
-
-def write_flash(esp, args):
-    # set args.compress based on default behaviour:
-    # -> if either --compress or --no-compress is set, honour that
-    # -> otherwise, set --compress unless --no-stub is set
-    if args.compress is None and not args.no_compress:
-        args.compress = not args.no_stub
-
-    # For encrypt option we do few sanity checks before actual flash write
-    if args.encrypt:
-        do_write = True
-        crypt_cfg_efuse = esp.get_flash_crypt_config()
-
-        if crypt_cfg_efuse != 0xF:
-            print('\nWARNING: Unexpected FLASH_CRYPT_CONFIG value', hex(crypt_cfg_efuse))
-            print('\nMake sure flash encryption is enabled correctly, refer to Flash Encryption documentation')
-            do_write = False
-
-        enc_key_valid = esp.is_flash_encryption_key_valid()
-
-        if not enc_key_valid:
-            print('\nFlash encryption key is not programmed')
-            print('\nMake sure flash encryption is enabled correctly, refer to Flash Encryption documentation')
-            do_write = False
-
-        if (esp.FLASH_WRITE_SIZE % 32) != 0:
-            print('\nWARNING - Flash write address is not aligned to the recommeded 32 bytes')
-            do_write = False
-
-        if not do_write and not args.ignore_flash_encryption_efuse_setting:
-            raise FatalError("Incorrect efuse setting: aborting flash write")
-
-    # verify file sizes fit in flash
-    if args.flash_size != 'keep':  # TODO: check this even with 'keep'
-        flash_end = flash_size_bytes(args.flash_size)
-        for address, argfile in args.addr_filename:
-            argfile.seek(0,2)  # seek to end
-            if address + argfile.tell() > flash_end:
-                raise FatalError(("File %s (length %d) at offset %d will not fit in %d bytes of flash. " +
-                                  "Use --flash-size argument, or change flashing address.")
-                                 % (argfile.name, argfile.tell(), address, flash_end))
-            argfile.seek(0)
-
-    if args.erase_all:
-        erase_flash(esp, args)
-
-    if args.encrypt and args.compress:
-        print('\nWARNING: - compress and encrypt options are mutually exclusive ')
-        print('Will flash uncompressed')
-        args.compress = False
-
-    for address, argfile in args.addr_filename:
-        if args.no_stub:
-            print('Erasing flash...')
-        image = pad_to(argfile.read(), 32 if args.encrypt else 4)
-        if len(image) == 0:
-            print('WARNING: File %s is empty' % argfile.name)
-            continue
-        image = _update_image_flash_params(esp, address, args, image)
-        calcmd5 = hashlib.md5(image).hexdigest()
-        uncsize = len(image)
-        if args.compress:
-            uncimage = image
-            image = zlib.compress(uncimage, 9)
-            ratio = uncsize / len(image)
-            blocks = esp.flash_defl_begin(uncsize, len(image), address)
-        else:
-            ratio = 1.0
-            blocks = esp.flash_begin(uncsize, address)
-        argfile.seek(0)  # in case we need it again
-        seq = 0
-        written = 0
-        t = time.time()
-        while len(image) > 0:
-            print('\rWriting at 0x%08x... (%d %%)' % (address + seq * esp.FLASH_WRITE_SIZE, 100 * (seq + 1) // blocks), end='')
-            sys.stdout.flush()
-            block = image[0:esp.FLASH_WRITE_SIZE]
-            if args.compress:
-                esp.flash_defl_block(block, seq, timeout=DEFAULT_TIMEOUT * ratio * 2)
-            else:
-                # Pad the last block
-                block = block + b'\xff' * (esp.FLASH_WRITE_SIZE - len(block))
-                if args.encrypt:
-                    esp.flash_encrypt_block(block, seq)
-                else:
-                    esp.flash_block(block, seq)
-            image = image[esp.FLASH_WRITE_SIZE:]
-            seq += 1
-            written += len(block)
-        t = time.time() - t
-        speed_msg = ""
-        if args.compress:
-            if t > 0.0:
-                speed_msg = " (effective %.1f kbit/s)" % (uncsize / t * 8 / 1000)
-            print('\rWrote %d bytes (%d compressed) at 0x%08x in %.1f seconds%s...' % (uncsize, written, address, t, speed_msg))
-        else:
-            if t > 0.0:
-                speed_msg = " (%.1f kbit/s)" % (written / t * 8 / 1000)
-            print('\rWrote %d bytes at 0x%08x in %.1f seconds%s...' % (written, address, t, speed_msg))
-
-        if not args.encrypt:
-            try:
-                res = esp.flash_md5sum(address, uncsize)
-                if res != calcmd5:
-                    print('File  md5: %s' % calcmd5)
-                    print('Flash md5: %s' % res)
-                    print('MD5 of 0xFF is %s' % (hashlib.md5(b'\xFF' * uncsize).hexdigest()))
-                    raise FatalError("MD5 of file does not match data in flash!")
-                else:
-                    print('Hash of data verified.')
-            except NotImplementedInROMError:
-                pass
-
-    print('\nLeaving...')
-
-    if esp.IS_STUB:
-        # skip sending flash_finish to ROM loader here,
-        # as it causes the loader to exit and run user code
-        esp.flash_begin(0, 0)
-        if args.compress:
-            esp.flash_defl_finish(False)
-        else:
-            esp.flash_finish(False)
-
-    if args.verify:
-        print('Verifying just-written flash...')
-        print('(This option is deprecated, flash contents are now always read back after flashing.)')
-        verify_flash(esp, args)
-
-
-def image_info(args):
-    image = LoadFirmwareImage(args.chip, args.filename)
-    print('Image version: %d' % image.version)
-    print('Entry point: %08x' % image.entrypoint if image.entrypoint != 0 else 'Entry point not set')
-    print('%d segments' % len(image.segments))
-    print()
-    idx = 0
-    for seg in image.segments:
-        idx += 1
-        seg_name = ", ".join([seg_range[2] for seg_range in image.ROM_LOADER.MEMORY_MAP if seg_range[0] <= seg.addr < seg_range[1]])
-        print('Segment %d: %r [%s]' % (idx, seg, seg_name))
-    calc_checksum = image.calculate_checksum()
-    print('Checksum: %02x (%s)' % (image.checksum,
-                                   'valid' if image.checksum == calc_checksum else 'invalid - calculated %02x' % calc_checksum))
-    try:
-        digest_msg = 'Not appended'
-        if image.append_digest:
-            is_valid = image.stored_digest == image.calc_digest
-            digest_msg = "%s (%s)" % (hexify(image.calc_digest).lower(),
-                                      "valid" if is_valid else "invalid")
-            print('Validation Hash: %s' % digest_msg)
-    except AttributeError:
-        pass  # ESP8266 image has no append_digest field
-
-
-def make_image(args):
-    image = ESP8266ROMFirmwareImage()
-    if len(args.segfile) == 0:
-        raise FatalError('No segments specified')
-    if len(args.segfile) != len(args.segaddr):
-        raise FatalError('Number of specified files does not match number of specified addresses')
-    for (seg, addr) in zip(args.segfile, args.segaddr):
-        with open(seg, 'rb') as f:
-            data = f.read()
-            image.segments.append(ImageSegment(addr, data))
-    image.entrypoint = args.entrypoint
-    image.save(args.output)
-
-
-def elf2image(args):
-    e = ELFFile(args.input)
-    if args.chip == 'auto':  # Default to ESP8266 for backwards compatibility
-        print("Creating image for ESP8266...")
-        args.chip = 'esp8266'
-
-    if args.chip == 'esp32':
-        image = ESP32FirmwareImage()
-        image.secure_pad = args.secure_pad
-        image.min_rev = int(args.min_rev)
-    elif args.version == '1':  # ESP8266
-        image = ESP8266ROMFirmwareImage()
-    else:
-        image = ESP8266V2FirmwareImage()
-    image.entrypoint = e.entrypoint
-    image.segments = e.sections  # ELFSection is a subclass of ImageSegment
-    image.flash_mode = {'qio':0, 'qout':1, 'dio':2, 'dout': 3}[args.flash_mode]
-    image.flash_size_freq = image.ROM_LOADER.FLASH_SIZES[args.flash_size]
-    image.flash_size_freq += {'40m':0, '26m':1, '20m':2, '80m': 0xf}[args.flash_freq]
-
-    if args.elf_sha256_offset:
-        image.elf_sha256 = e.sha256()
-        image.elf_sha256_offset = args.elf_sha256_offset
-
-    image.verify()
-
-    if args.output is None:
-        args.output = image.default_output_name(args.input)
-    image.save(args.output)
-
-
-def read_mac(esp, args):
-    mac = esp.read_mac()
-
-    def print_mac(label, mac):
-        print('%s: %s' % (label, ':'.join(map(lambda x: '%02x' % x, mac))))
-    print_mac("MAC", mac)
-
-
-def chip_id(esp, args):
-    try:
-        chipid = esp.chip_id()
-        print('Chip ID: 0x%08x' % chipid)
-    except NotSupportedError:
-        print('Warning: %s has no Chip ID. Reading MAC instead.' % esp.CHIP_NAME)
-        read_mac(esp, args)
-
-
-def erase_flash(esp, args):
-    print('Erasing flash (this may take a while)...')
-    t = time.time()
-    esp.erase_flash()
-    print('Chip erase completed successfully in %.1fs' % (time.time() - t))
-
-
-def erase_region(esp, args):
-    print('Erasing region (may be slow depending on size)...')
-    t = time.time()
-    esp.erase_region(args.address, args.size)
-    print('Erase completed successfully in %.1f seconds.' % (time.time() - t))
-
-
-def run(esp, args):
-    esp.run()
-
-
-def flash_id(esp, args):
-    flash_id = esp.flash_id()
-    print('Manufacturer: %02x' % (flash_id & 0xff))
-    flid_lowbyte = (flash_id >> 16) & 0xFF
-    print('Device: %02x%02x' % ((flash_id >> 8) & 0xff, flid_lowbyte))
-    print('Detected flash size: %s' % (DETECTED_FLASH_SIZES.get(flid_lowbyte, "Unknown")))
-
-
-def read_flash(esp, args):
-    if args.no_progress:
-        flash_progress = None
-    else:
-        def flash_progress(progress, length):
-            msg = '%d (%d %%)' % (progress, progress * 100.0 / length)
-            padding = '\b' * len(msg)
-            if progress == length:
-                padding = '\n'
-            sys.stdout.write(msg + padding)
-            sys.stdout.flush()
-    t = time.time()
-    data = esp.read_flash(args.address, args.size, flash_progress)
-    t = time.time() - t
-    print('\rRead %d bytes at 0x%x in %.1f seconds (%.1f kbit/s)...'
-          % (len(data), args.address, t, len(data) / t * 8 / 1000))
-    with open(args.filename, 'wb') as f:
-        f.write(data)
-
-
-def verify_flash(esp, args):
-    differences = False
-
-    for address, argfile in args.addr_filename:
-        image = pad_to(argfile.read(), 4)
-        argfile.seek(0)  # rewind in case we need it again
-
-        image = _update_image_flash_params(esp, address, args, image)
-
-        image_size = len(image)
-        print('Verifying 0x%x (%d) bytes @ 0x%08x in flash against %s...' % (image_size, image_size, address, argfile.name))
-        # Try digest first, only read if there are differences.
-        digest = esp.flash_md5sum(address, image_size)
-        expected_digest = hashlib.md5(image).hexdigest()
-        if digest == expected_digest:
-            print('-- verify OK (digest matched)')
-            continue
-        else:
-            differences = True
-            if getattr(args, 'diff', 'no') != 'yes':
-                print('-- verify FAILED (digest mismatch)')
-                continue
-
-        flash = esp.read_flash(address, image_size)
-        assert flash != image
-        diff = [i for i in range(image_size) if flash[i] != image[i]]
-        print('-- verify FAILED: %d differences, first @ 0x%08x' % (len(diff), address + diff[0]))
-        for d in diff:
-            flash_byte = flash[d]
-            image_byte = image[d]
-            if PYTHON2:
-                flash_byte = ord(flash_byte)
-                image_byte = ord(image_byte)
-            print('   %08x %02x %02x' % (address + d, flash_byte, image_byte))
-    if differences:
-        raise FatalError("Verify failed.")
-
-
-def read_flash_status(esp, args):
-    print('Status value: 0x%04x' % esp.read_status(args.bytes))
-
-
-def write_flash_status(esp, args):
-    fmt = "0x%%0%dx" % (args.bytes * 2)
-    args.value = args.value & ((1 << (args.bytes * 8)) - 1)
-    print(('Initial flash status: ' + fmt) % esp.read_status(args.bytes))
-    print(('Setting flash status: ' + fmt) % args.value)
-    esp.write_status(args.value, args.bytes, args.non_volatile)
-    print(('After flash status:   ' + fmt) % esp.read_status(args.bytes))
-
-
-def version(args):
-    print(__version__)
-
-#
-# End of operations functions
-#
-
-
-def main(custom_commandline=None):
-    """
-    Main function for esptool
-
-    custom_commandline - Optional override for default arguments parsing (that uses sys.argv), can be a list of custom arguments
-    as strings. Arguments and their values need to be added as individual items to the list e.g. "-b 115200" thus
-    becomes ['-b', '115200'].
-    """
-    parser = argparse.ArgumentParser(description='esptool.py v%s - ESP8266 ROM Bootloader Utility' % __version__, prog='esptool')
-
-    parser.add_argument('--chip', '-c',
-                        help='Target chip type',
-                        choices=['auto', 'esp8266', 'esp32'],
-                        default=os.environ.get('ESPTOOL_CHIP', 'auto'))
-
-    parser.add_argument(
-        '--port', '-p',
-        help='Serial port device',
-        default=os.environ.get('ESPTOOL_PORT', None))
-
-    parser.add_argument(
-        '--baud', '-b',
-        help='Serial port baud rate used when flashing/reading',
-        type=arg_auto_int,
-        default=os.environ.get('ESPTOOL_BAUD', ESPLoader.ESP_ROM_BAUD))
-
-    parser.add_argument(
-        '--before',
-        help='What to do before connecting to the chip',
-        choices=['default_reset', 'no_reset', 'no_reset_no_sync'],
-        default=os.environ.get('ESPTOOL_BEFORE', 'default_reset'))
-
-    parser.add_argument(
-        '--after', '-a',
-        help='What to do after esptool.py is finished',
-        choices=['hard_reset', 'soft_reset', 'no_reset'],
-        default=os.environ.get('ESPTOOL_AFTER', 'hard_reset'))
-
-    parser.add_argument(
-        '--no-stub',
-        help="Disable launching the flasher stub, only talk to ROM bootloader. Some features will not be available.",
-        action='store_true')
-
-    parser.add_argument(
-        '--trace', '-t',
-        help="Enable trace-level output of esptool.py interactions.",
-        action='store_true')
-
-    parser.add_argument(
-        '--override-vddsdio',
-        help="Override ESP32 VDDSDIO internal voltage regulator (use with care)",
-        choices=ESP32ROM.OVERRIDE_VDDSDIO_CHOICES,
-        nargs='?')
-
-    subparsers = parser.add_subparsers(
-        dest='operation',
-        help='Run esptool {command} -h for additional help')
-
-    def add_spi_connection_arg(parent):
-        parent.add_argument('--spi-connection', '-sc', help='ESP32-only argument. Override default SPI Flash connection. ' +
-                            'Value can be SPI, HSPI or a comma-separated list of 5 I/O numbers to use for SPI flash (CLK,Q,D,HD,CS).',
-                            action=SpiConnectionAction)
-
-    parser_load_ram = subparsers.add_parser(
-        'load_ram',
-        help='Download an image to RAM and execute')
-    parser_load_ram.add_argument('filename', help='Firmware image')
-
-    parser_dump_mem = subparsers.add_parser(
-        'dump_mem',
-        help='Dump arbitrary memory to disk')
-    parser_dump_mem.add_argument('address', help='Base address', type=arg_auto_int)
-    parser_dump_mem.add_argument('size', help='Size of region to dump', type=arg_auto_int)
-    parser_dump_mem.add_argument('filename', help='Name of binary dump')
-
-    parser_read_mem = subparsers.add_parser(
-        'read_mem',
-        help='Read arbitrary memory location')
-    parser_read_mem.add_argument('address', help='Address to read', type=arg_auto_int)
-
-    parser_write_mem = subparsers.add_parser(
-        'write_mem',
-        help='Read-modify-write to arbitrary memory location')
-    parser_write_mem.add_argument('address', help='Address to write', type=arg_auto_int)
-    parser_write_mem.add_argument('value', help='Value', type=arg_auto_int)
-    parser_write_mem.add_argument('mask', help='Mask of bits to write', type=arg_auto_int)
-
-    def add_spi_flash_subparsers(parent, is_elf2image):
-        """ Add common parser arguments for SPI flash properties """
-        extra_keep_args = [] if is_elf2image else ['keep']
-        auto_detect = not is_elf2image
-
-        if auto_detect:
-            extra_fs_message = ", detect, or keep"
-        else:
-            extra_fs_message = ""
-
-        parent.add_argument('--flash_freq', '-ff', help='SPI Flash frequency',
-                            choices=extra_keep_args + ['40m', '26m', '20m', '80m'],
-                            default=os.environ.get('ESPTOOL_FF', '40m' if is_elf2image else 'keep'))
-        parent.add_argument('--flash_mode', '-fm', help='SPI Flash mode',
-                            choices=extra_keep_args + ['qio', 'qout', 'dio', 'dout'],
-                            default=os.environ.get('ESPTOOL_FM', 'qio' if is_elf2image else 'keep'))
-        parent.add_argument('--flash_size', '-fs', help='SPI Flash size in MegaBytes (1MB, 2MB, 4MB, 8MB, 16M)'
-                            ' plus ESP8266-only (256KB, 512KB, 2MB-c1, 4MB-c1)' + extra_fs_message,
-                            action=FlashSizeAction, auto_detect=auto_detect,
-                            default=os.environ.get('ESPTOOL_FS', 'detect' if auto_detect else '1MB'))
-        add_spi_connection_arg(parent)
-
-    parser_write_flash = subparsers.add_parser(
-        'write_flash',
-        help='Write a binary blob to flash')
-
-    parser_write_flash.add_argument('addr_filename', metavar='<address> <filename>', help='Address followed by binary filename, separated by space',
-                                    action=AddrFilenamePairAction)
-    parser_write_flash.add_argument('--erase-all', '-e',
-                                    help='Erase all regions of flash (not just write areas) before programming',
-                                    action="store_true")
-
-    add_spi_flash_subparsers(parser_write_flash, is_elf2image=False)
-    parser_write_flash.add_argument('--no-progress', '-p', help='Suppress progress output', action="store_true")
-    parser_write_flash.add_argument('--verify', help='Verify just-written data on flash ' +
-                                    '(mostly superfluous, data is read back during flashing)', action='store_true')
-    parser_write_flash.add_argument('--encrypt', help='Encrypt before write ',
-                                    action='store_true')
-    parser_write_flash.add_argument('--ignore-flash-encryption-efuse-setting', help='Ignore flash encryption efuse settings ',
-                                    action='store_true')
-
-    compress_args = parser_write_flash.add_mutually_exclusive_group(required=False)
-    compress_args.add_argument('--compress', '-z', help='Compress data in transfer (default unless --no-stub is specified)',action="store_true", default=None)
-    compress_args.add_argument('--no-compress', '-u', help='Disable data compression during transfer (default if --no-stub is specified)',action="store_true")
-
-    subparsers.add_parser(
-        'run',
-        help='Run application code in flash')
-
-    parser_image_info = subparsers.add_parser(
-        'image_info',
-        help='Dump headers from an application image')
-    parser_image_info.add_argument('filename', help='Image file to parse')
-
-    parser_make_image = subparsers.add_parser(
-        'make_image',
-        help='Create an application image from binary files')
-    parser_make_image.add_argument('output', help='Output image file')
-    parser_make_image.add_argument('--segfile', '-f', action='append', help='Segment input file')
-    parser_make_image.add_argument('--segaddr', '-a', action='append', help='Segment base address', type=arg_auto_int)
-    parser_make_image.add_argument('--entrypoint', '-e', help='Address of entry point', type=arg_auto_int, default=0)
-
-    parser_elf2image = subparsers.add_parser(
-        'elf2image',
-        help='Create an application image from ELF file')
-    parser_elf2image.add_argument('input', help='Input ELF file')
-    parser_elf2image.add_argument('--output', '-o', help='Output filename prefix (for version 1 image), or filename (for version 2 single image)', type=str)
-    parser_elf2image.add_argument('--version', '-e', help='Output image version', choices=['1','2'], default='1')
-    parser_elf2image.add_argument('--min-rev', '-r', help='Minimum chip revision', choices=['0','1','2','3'], default='0')
-    parser_elf2image.add_argument('--secure-pad', action='store_true', help='Pad image so once signed it will end on a 64KB boundary. For ESP32 images only.')
-    parser_elf2image.add_argument('--elf-sha256-offset', help='If set, insert SHA256 hash (32 bytes) of the input ELF file at specified offset in the binary.',
-                                  type=arg_auto_int, default=None)
-
-    add_spi_flash_subparsers(parser_elf2image, is_elf2image=True)
-
-    subparsers.add_parser(
-        'read_mac',
-        help='Read MAC address from OTP ROM')
-
-    subparsers.add_parser(
-        'chip_id',
-        help='Read Chip ID from OTP ROM')
-
-    parser_flash_id = subparsers.add_parser(
-        'flash_id',
-        help='Read SPI flash manufacturer and device ID')
-    add_spi_connection_arg(parser_flash_id)
-
-    parser_read_status = subparsers.add_parser(
-        'read_flash_status',
-        help='Read SPI flash status register')
-
-    add_spi_connection_arg(parser_read_status)
-    parser_read_status.add_argument('--bytes', help='Number of bytes to read (1-3)', type=int, choices=[1,2,3], default=2)
-
-    parser_write_status = subparsers.add_parser(
-        'write_flash_status',
-        help='Write SPI flash status register')
-
-    add_spi_connection_arg(parser_write_status)
-    parser_write_status.add_argument('--non-volatile', help='Write non-volatile bits (use with caution)', action='store_true')
-    parser_write_status.add_argument('--bytes', help='Number of status bytes to write (1-3)', type=int, choices=[1,2,3], default=2)
-    parser_write_status.add_argument('value', help='New value', type=arg_auto_int)
-
-    parser_read_flash = subparsers.add_parser(
-        'read_flash',
-        help='Read SPI flash content')
-    add_spi_connection_arg(parser_read_flash)
-    parser_read_flash.add_argument('address', help='Start address', type=arg_auto_int)
-    parser_read_flash.add_argument('size', help='Size of region to dump', type=arg_auto_int)
-    parser_read_flash.add_argument('filename', help='Name of binary dump')
-    parser_read_flash.add_argument('--no-progress', '-p', help='Suppress progress output', action="store_true")
-
-    parser_verify_flash = subparsers.add_parser(
-        'verify_flash',
-        help='Verify a binary blob against flash')
-    parser_verify_flash.add_argument('addr_filename', help='Address and binary file to verify there, separated by space',
-                                     action=AddrFilenamePairAction)
-    parser_verify_flash.add_argument('--diff', '-d', help='Show differences',
-                                     choices=['no', 'yes'], default='no')
-    add_spi_flash_subparsers(parser_verify_flash, is_elf2image=False)
-
-    parser_erase_flash = subparsers.add_parser(
-        'erase_flash',
-        help='Perform Chip Erase on SPI flash')
-    add_spi_connection_arg(parser_erase_flash)
-
-    parser_erase_region = subparsers.add_parser(
-        'erase_region',
-        help='Erase a region of the flash')
-    add_spi_connection_arg(parser_erase_region)
-    parser_erase_region.add_argument('address', help='Start address (must be multiple of 4096)', type=arg_auto_int)
-    parser_erase_region.add_argument('size', help='Size of region to erase (must be multiple of 4096)', type=arg_auto_int)
-
-    subparsers.add_parser(
-        'version', help='Print esptool version')
-
-    # internal sanity check - every operation matches a module function of the same name
-    for operation in subparsers.choices.keys():
-        assert operation in globals(), "%s should be a module function" % operation
-
-    expand_file_arguments()
-
-    args = parser.parse_args(custom_commandline)
-
-    print('esptool.py v%s' % __version__)
-
-    # operation function can take 1 arg (args), 2 args (esp, arg)
-    # or be a member function of the ESPLoader class.
-
-    if args.operation is None:
-        parser.print_help()
-        sys.exit(1)
-
-    operation_func = globals()[args.operation]
-
-    if PYTHON2:
-        # This function is depreciated in Python3
-        operation_args = inspect.getargspec(operation_func).args
-    else:
-        operation_args = inspect.getfullargspec(operation_func).args
-
-    if operation_args[0] == 'esp':  # operation function takes an ESPLoader connection object
-        if args.before != "no_reset_no_sync":
-            initial_baud = min(ESPLoader.ESP_ROM_BAUD, args.baud)  # don't sync faster than the default baud rate
-        else:
-            initial_baud = args.baud
-
-        if args.port is None:
-            ser_list = sorted(ports.device for ports in list_ports.comports())
-            print("Found %d serial ports" % len(ser_list))
-        else:
-            ser_list = [args.port]
-        esp = None
-        for each_port in reversed(ser_list):
-            print("Serial port %s" % each_port)
-            try:
-                if args.chip == 'auto':
-                    esp = ESPLoader.detect_chip(each_port, initial_baud, args.before, args.trace)
-                else:
-                    chip_class = {
-                        'esp8266': ESP8266ROM,
-                        'esp32': ESP32ROM,
-                    }[args.chip]
-                    esp = chip_class(each_port, initial_baud, args.trace)
-                    esp.connect(args.before)
-                break
-            except (FatalError, OSError) as err:
-                if args.port is not None:
-                    raise
-                print("%s failed to connect: %s" % (each_port, err))
-                esp = None
-        if esp is None:
-            raise FatalError("Could not connect to an Espressif device on any of the %d available serial ports." % len(ser_list))
-
-        print("Chip is %s" % (esp.get_chip_description()))
-
-        print("Features: %s" % ", ".join(esp.get_chip_features()))
-
-        print("Crystal is %dMHz" % esp.get_crystal_freq())
-
-        read_mac(esp, args)
-
-        if not args.no_stub:
-            esp = esp.run_stub()
-
-        if args.override_vddsdio:
-            esp.override_vddsdio(args.override_vddsdio)
-
-        if args.baud > initial_baud:
-            try:
-                esp.change_baud(args.baud)
-            except NotImplementedInROMError:
-                print("WARNING: ROM doesn't support changing baud rate. Keeping initial baud rate %d" % initial_baud)
-
-        # override common SPI flash parameter stuff if configured to do so
-        if hasattr(args, "spi_connection") and args.spi_connection is not None:
-            if esp.CHIP_NAME != "ESP32":
-                raise FatalError("Chip %s does not support --spi-connection option." % esp.CHIP_NAME)
-            print("Configuring SPI flash mode...")
-            esp.flash_spi_attach(args.spi_connection)
-        elif args.no_stub:
-            print("Enabling default SPI flash mode...")
-            # ROM loader doesn't enable flash unless we explicitly do it
-            esp.flash_spi_attach(0)
-
-        if hasattr(args, "flash_size"):
-            print("Configuring flash size...")
-            detect_flash_size(esp, args)
-            if args.flash_size != 'keep':  # TODO: should set this even with 'keep'
-                esp.flash_set_parameters(flash_size_bytes(args.flash_size))
-
-        try:
-            operation_func(esp, args)
-        finally:
-            try:  # Clean up AddrFilenamePairAction files
-                for address, argfile in args.addr_filename:
-                    argfile.close()
-            except AttributeError:
-                pass
-
-        # Handle post-operation behaviour (reset or other)
-        if operation_func == load_ram:
-            # the ESP is now running the loaded image, so let it run
-            print('Exiting immediately.')
-        elif args.after == 'hard_reset':
-            print('Hard resetting via RTS pin...')
-            esp.hard_reset()
-        elif args.after == 'soft_reset':
-            print('Soft resetting...')
-            # flash_finish will trigger a soft reset
-            esp.soft_reset(False)
-        else:
-            print('Staying in bootloader.')
-            if esp.IS_STUB:
-                esp.soft_reset(True)  # exit stub back to ROM loader
-
-        esp._port.close()
-
-    else:
-        operation_func(args)
-
-
-def expand_file_arguments():
-    """ Any argument starting with "@" gets replaced with all values read from a text file.
-    Text file arguments can be split by newline or by space.
-    Values are added "as-is", as if they were specified in this order on the command line.
-    """
-    new_args = []
-    expanded = False
-    for arg in sys.argv:
-        if arg.startswith("@"):
-            expanded = True
-            with open(arg[1:],"r") as f:
-                for line in f.readlines():
-                    new_args += shlex.split(line)
-        else:
-            new_args.append(arg)
-    if expanded:
-        print("esptool.py %s" % (" ".join(new_args[1:])))
-        sys.argv = new_args
-
-
-class FlashSizeAction(argparse.Action):
-    """ Custom flash size parser class to support backwards compatibility with megabit size arguments.
-
-    (At next major relase, remove deprecated sizes and this can become a 'normal' choices= argument again.)
-    """
-    def __init__(self, option_strings, dest, nargs=1, auto_detect=False, **kwargs):
-        super(FlashSizeAction, self).__init__(option_strings, dest, nargs, **kwargs)
-        self._auto_detect = auto_detect
-
-    def __call__(self, parser, namespace, values, option_string=None):
-        try:
-            value = {
-                '2m': '256KB',
-                '4m': '512KB',
-                '8m': '1MB',
-                '16m': '2MB',
-                '32m': '4MB',
-                '16m-c1': '2MB-c1',
-                '32m-c1': '4MB-c1',
-            }[values[0]]
-            print("WARNING: Flash size arguments in megabits like '%s' are deprecated." % (values[0]))
-            print("Please use the equivalent size '%s'." % (value))
-            print("Megabit arguments may be removed in a future release.")
-        except KeyError:
-            value = values[0]
-
-        known_sizes = dict(ESP8266ROM.FLASH_SIZES)
-        known_sizes.update(ESP32ROM.FLASH_SIZES)
-        if self._auto_detect:
-            known_sizes['detect'] = 'detect'
-            known_sizes['keep'] = 'keep'
-        if value not in known_sizes:
-            raise argparse.ArgumentError(self, '%s is not a known flash size. Known sizes: %s' % (value, ", ".join(known_sizes.keys())))
-        setattr(namespace, self.dest, value)
-
-
-class SpiConnectionAction(argparse.Action):
-    """ Custom action to parse 'spi connection' override. Values are SPI, HSPI, or a sequence of 5 pin numbers separated by commas.
-    """
-    def __call__(self, parser, namespace, value, option_string=None):
-        if value.upper() == "SPI":
-            value = 0
-        elif value.upper() == "HSPI":
-            value = 1
-        elif "," in value:
-            values = value.split(",")
-            if len(values) != 5:
-                raise argparse.ArgumentError(self, '%s is not a valid list of comma-separate pin numbers. Must be 5 numbers - CLK,Q,D,HD,CS.' % value)
-            try:
-                values = tuple(int(v,0) for v in values)
-            except ValueError:
-                raise argparse.ArgumentError(self, '%s is not a valid argument. All pins must be numeric values' % values)
-            if any([v for v in values if v > 33 or v < 0]):
-                raise argparse.ArgumentError(self, 'Pin numbers must be in the range 0-33.')
-            # encode the pin numbers as a 32-bit integer with packed 6-bit values, the same way ESP32 ROM takes them
-            # TODO: make this less ESP32 ROM specific somehow...
-            clk,q,d,hd,cs = values
-            value = (hd << 24) | (cs << 18) | (d << 12) | (q << 6) | clk
-        else:
-            raise argparse.ArgumentError(self, '%s is not a valid spi-connection value. ' +
-                                         'Values are SPI, HSPI, or a sequence of 5 pin numbers CLK,Q,D,HD,CS).' % value)
-        setattr(namespace, self.dest, value)
-
-
-class AddrFilenamePairAction(argparse.Action):
-    """ Custom parser class for the address/filename pairs passed as arguments """
-    def __init__(self, option_strings, dest, nargs='+', **kwargs):
-        super(AddrFilenamePairAction, self).__init__(option_strings, dest, nargs, **kwargs)
-
-    def __call__(self, parser, namespace, values, option_string=None):
-        # validate pair arguments
-        pairs = []
-        for i in range(0,len(values),2):
-            try:
-                address = int(values[i],0)
-            except ValueError:
-                raise argparse.ArgumentError(self,'Address "%s" must be a number' % values[i])
-            try:
-                argfile = open(values[i + 1], 'rb')
-            except IOError as e:
-                raise argparse.ArgumentError(self, e)
-            except IndexError:
-                raise argparse.ArgumentError(self,'Must be pairs of an address and the binary filename to write there')
-            pairs.append((address, argfile))
-
-        # Sort the addresses and check for overlapping
-        end = 0
-        for address, argfile in sorted(pairs):
-            argfile.seek(0,2)  # seek to end
-            size = argfile.tell()
-            argfile.seek(0)
-            sector_start = address & ~(ESPLoader.FLASH_SECTOR_SIZE - 1)
-            sector_end = ((address + size + ESPLoader.FLASH_SECTOR_SIZE - 1) & ~(ESPLoader.FLASH_SECTOR_SIZE - 1)) - 1
-            if sector_start < end:
-                message = 'Detected overlap at address: 0x%x for file: %s' % (address, argfile.name)
-                raise argparse.ArgumentError(self, message)
-            end = sector_end
-        setattr(namespace, self.dest, pairs)
-
-
-# Binary stub code (see flasher_stub dir for source & details)
-ESP8266ROM.STUB_CODE = eval(zlib.decompress(base64.b64decode(b"""
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-""")))
-ESP32ROM.STUB_CODE = eval(zlib.decompress(base64.b64decode(b"""
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-""")))
-
-
-def _main():
-    try:
-        main()
-    except FatalError as e:
-        print('\nA fatal error occurred: %s' % e)
-        sys.exit(2)
-
-
-if __name__ == '__main__':
-    _main()
diff --git a/tools/gen_crt_bundle.py b/tools/gen_crt_bundle.py
new file mode 100644
index 00000000000..4f2c78c1df4
--- /dev/null
+++ b/tools/gen_crt_bundle.py
@@ -0,0 +1,240 @@
+#!/usr/bin/env python
+#
+# ESP32 x509 certificate bundle generation utility
+#
+# Converts PEM and DER certificates to a custom bundle format which stores just the
+# subject name and public key to reduce space
+#
+# The bundle will have the format: number of certificates; crt 1 subject name length; crt 1 public key length;
+# crt 1 subject name; crt 1 public key; crt 2...
+#
+# Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http:#www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from __future__ import with_statement
+
+import argparse
+import csv
+import os
+import re
+import struct
+import sys
+from io import open
+
+try:
+    from cryptography import x509
+    from cryptography.hazmat.backends import default_backend
+    from cryptography.hazmat.primitives import serialization
+except ImportError:
+    print(
+        "The cryptography package is not installed."
+        "Please refer to the Get Started section of the ESP-IDF Programming Guide for "
+        "setting up the required packages."
+    )
+    raise
+
+ca_bundle_bin_file = "x509_crt_bundle"
+
+quiet = False
+
+
+def status(msg):
+    """Print status message to stderr"""
+    if not quiet:
+        critical(msg)
+
+
+def critical(msg):
+    """Print critical message to stderr"""
+    sys.stderr.write("gen_crt_bundle.py: ")
+    sys.stderr.write(msg)
+    sys.stderr.write("\n")
+
+
+class CertificateBundle:
+    def __init__(self):
+        self.certificates = []
+        self.compressed_crts = []
+
+        if os.path.isfile(ca_bundle_bin_file):
+            os.remove(ca_bundle_bin_file)
+
+    def add_from_path(self, crts_path):
+
+        found = False
+        for file_path in os.listdir(crts_path):
+            found |= self.add_from_file(os.path.join(crts_path, file_path))
+
+        if found is False:
+            raise InputError("No valid x509 certificates found in %s" % crts_path)
+
+    def add_from_file(self, file_path):
+        try:
+            if file_path.endswith(".pem"):
+                status("Parsing certificates from %s" % file_path)
+                with open(file_path, "r", encoding="utf-8") as f:
+                    crt_str = f.read()
+                    self.add_from_pem(crt_str)
+                    return True
+
+            elif file_path.endswith(".der"):
+                status("Parsing certificates from %s" % file_path)
+                with open(file_path, "rb") as f:
+                    crt_str = f.read()
+                    self.add_from_der(crt_str)
+                    return True
+
+        except ValueError:
+            critical("Invalid certificate in %s" % file_path)
+            raise InputError("Invalid certificate")
+
+        return False
+
+    def add_from_pem(self, crt_str):
+        """A single PEM file may have multiple certificates"""
+
+        crt = ""
+        count = 0
+        start = False
+
+        for strg in crt_str.splitlines(True):
+            if strg == "-----BEGIN CERTIFICATE-----\n" and start is False:
+                crt = ""
+                start = True
+            elif strg == "-----END CERTIFICATE-----\n" and start is True:
+                crt += strg + "\n"
+                start = False
+                self.certificates.append(x509.load_pem_x509_certificate(crt.encode(), default_backend()))
+                count += 1
+            if start is True:
+                crt += strg
+
+        if count == 0:
+            raise InputError("No certificate found")
+
+        status("Successfully added %d certificates" % count)
+
+    def add_from_der(self, crt_str):
+        self.certificates.append(x509.load_der_x509_certificate(crt_str, default_backend()))
+        status("Successfully added 1 certificate")
+
+    def create_bundle(self):
+        # Sort certificates in order to do binary search when looking up certificates
+        self.certificates = sorted(self.certificates, key=lambda cert: cert.subject.public_bytes(default_backend()))
+
+        bundle = struct.pack(">H", len(self.certificates))
+
+        for crt in self.certificates:
+            """Read the public key as DER format"""
+            pub_key = crt.public_key()
+            pub_key_der = pub_key.public_bytes(
+                serialization.Encoding.DER, serialization.PublicFormat.SubjectPublicKeyInfo
+            )
+
+            """ Read the subject name as DER format """
+            sub_name_der = crt.subject.public_bytes(default_backend())
+
+            name_len = len(sub_name_der)
+            key_len = len(pub_key_der)
+            len_data = struct.pack(">HH", name_len, key_len)
+
+            bundle += len_data
+            bundle += sub_name_der
+            bundle += pub_key_der
+
+        return bundle
+
+    def add_with_filter(self, crts_path, filter_path):
+
+        filter_set = set()
+        with open(filter_path, "r", encoding="utf-8") as f:
+            csv_reader = csv.reader(f, delimiter=",")
+
+            # Skip header
+            next(csv_reader)
+            for row in csv_reader:
+                filter_set.add(row[1])
+
+        status("Parsing certificates from %s" % crts_path)
+        crt_str = []
+        with open(crts_path, "r", encoding="utf-8") as f:
+            crt_str = f.read()
+
+            # Split all certs into a list of (name, certificate string) tuples
+            pem_crts = re.findall(r"(^.+?)\n(=+\n[\s\S]+?END CERTIFICATE-----\n)", crt_str, re.MULTILINE)
+
+            filtered_crts = ""
+            for name, crt in pem_crts:
+                if name in filter_set:
+                    filtered_crts += crt
+
+        self.add_from_pem(filtered_crts)
+
+
+class InputError(RuntimeError):
+    def __init__(self, e):
+        super(InputError, self).__init__(e)
+
+
+def main():
+    global quiet
+
+    parser = argparse.ArgumentParser(description="ESP-IDF x509 certificate bundle utility")
+
+    parser.add_argument("--quiet", "-q", help="Don't print non-critical status messages to stderr", action="store_true")
+    parser.add_argument(
+        "--input",
+        "-i",
+        nargs="+",
+        required=True,
+        help="Paths to the custom certificate folders or files to parse, parses all .pem or .der files",
+    )
+    parser.add_argument(
+        "--filter",
+        "-f",
+        help="Path to CSV-file where the second columns contains the name of the certificates \
+                        that should be included from cacrt_all.pem",
+    )
+
+    args = parser.parse_args()
+
+    quiet = args.quiet
+
+    bundle = CertificateBundle()
+
+    for path in args.input:
+        if os.path.isfile(path):
+            if os.path.basename(path) == "cacrt_all.pem" and args.filter:
+                bundle.add_with_filter(path, args.filter)
+            else:
+                bundle.add_from_file(path)
+        elif os.path.isdir(path):
+            bundle.add_from_path(path)
+        else:
+            raise InputError("Invalid --input=%s, is neither file nor folder" % args.input)
+
+    status("Successfully added %d certificates in total" % len(bundle.certificates))
+
+    crt_bundle = bundle.create_bundle()
+
+    with open(ca_bundle_bin_file, "wb") as f:
+        f.write(crt_bundle)
+
+
+if __name__ == "__main__":
+    try:
+        main()
+    except InputError as e:
+        print(e)
+        sys.exit(2)
diff --git a/tools/gen_esp32part.exe b/tools/gen_esp32part.exe
index f81ac71c56a..5bd12c6360d 100644
Binary files a/tools/gen_esp32part.exe and b/tools/gen_esp32part.exe differ
diff --git a/tools/gen_esp32part.py b/tools/gen_esp32part.py
index ac8f3af6a0f..ffa740a36e0 100755
--- a/tools/gen_esp32part.py
+++ b/tools/gen_esp32part.py
@@ -7,38 +7,32 @@
 # See https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/partition-tables.html
 # for explanation of partition table structure and uses.
 #
-# Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http:#www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-from __future__ import print_function, division
-from __future__ import unicode_literals
+# SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Apache-2.0
+
+from __future__ import division, print_function, unicode_literals
+
 import argparse
+import binascii
+import errno
+import hashlib
 import os
 import re
 import struct
 import sys
-import hashlib
-import binascii
-import errno
 
-MAX_PARTITION_LENGTH = 0xC00   # 3K for partition data (96 entries) leaves 1K in a 4K sector for signature
+MAX_PARTITION_LENGTH = 0xC00  # 3K for partition data (96 entries) leaves 1K in a 4K sector for signature
 MD5_PARTITION_BEGIN = b"\xEB\xEB" + b"\xFF" * 14  # The first 2 bytes are like magic numbers for MD5 sum
-PARTITION_TABLE_SIZE  = 0x1000  # Size of partition table
+PARTITION_TABLE_SIZE = 0x1000  # Size of partition table
 
 MIN_PARTITION_SUBTYPE_APP_OTA = 0x10
 NUM_PARTITION_SUBTYPE_APP_OTA = 16
 
-__version__ = '1.2'
+SECURE_NONE = None
+SECURE_V1 = "v1"
+SECURE_V2 = "v2"
+
+__version__ = "1.2"
 
 APP_TYPE = 0x00
 DATA_TYPE = 0x01
@@ -48,6 +42,18 @@
     "data": DATA_TYPE,
 }
 
+
+def get_ptype_as_int(ptype):
+    """Convert a string which might be numeric or the name of a partition type to an integer"""
+    try:
+        return TYPES[ptype]
+    except KeyError:
+        try:
+            return int(ptype, 0)
+        except TypeError:
+            return ptype
+
+
 # Keep this map in sync with esp_partition_subtype_t enum in esp_partition.h
 SUBTYPES = {
     APP_TYPE: {
@@ -61,28 +67,85 @@
         "coredump": 0x03,
         "nvs_keys": 0x04,
         "efuse": 0x05,
+        "undefined": 0x06,
         "esphttpd": 0x80,
         "fat": 0x81,
         "spiffs": 0x82,
+        "littlefs": 0x83,
     },
 }
 
+
+def get_subtype_as_int(ptype, subtype):
+    """Convert a string which might be numeric or the name of a partition subtype to an integer"""
+    try:
+        return SUBTYPES[get_ptype_as_int(ptype)][subtype]
+    except KeyError:
+        try:
+            return int(subtype, 0)
+        except TypeError:
+            return subtype
+
+
+ALIGNMENT = {
+    APP_TYPE: 0x10000,
+    DATA_TYPE: 0x1000,
+}
+
+
+def get_alignment_offset_for_type(ptype):
+    return ALIGNMENT.get(ptype, ALIGNMENT[DATA_TYPE])
+
+
+def get_alignment_size_for_type(ptype):
+    if ptype == APP_TYPE and secure == SECURE_V1:
+        # For secure boot v1 case, app partition must be 64K aligned
+        # signature block (68 bytes) lies at the very end of 64K block
+        return 0x10000
+    if ptype == APP_TYPE and secure == SECURE_V2:
+        # For secure boot v2 case, app partition must be 4K aligned
+        # signature block (4K) is kept after padding the unsigned image to 64K boundary
+        return 0x1000
+    # No specific size alignment requirement as such
+    return 0x1
+
+
+def get_partition_type(ptype):
+    if ptype == "app":
+        return APP_TYPE
+    if ptype == "data":
+        return DATA_TYPE
+    raise InputError("Invalid partition type")
+
+
+def add_extra_subtypes(csv):
+    for line_no in csv:
+        try:
+            fields = [line.strip() for line in line_no.split(",")]
+            for subtype, subtype_values in SUBTYPES.items():
+                if int(fields[2], 16) in subtype_values.values() and subtype == get_partition_type(fields[0]):
+                    raise ValueError("Found duplicate value in partition subtype")
+            SUBTYPES[TYPES[fields[0]]][fields[1]] = int(fields[2], 16)
+        except InputError as err:
+            raise InputError("Error parsing custom subtypes: %s" % err)
+
+
 quiet = False
 md5sum = True
-secure = False
+secure = SECURE_NONE
 offset_part_table = 0
 
 
 def status(msg):
-    """ Print status message to stderr """
+    """Print status message to stderr"""
     if not quiet:
         critical(msg)
 
 
 def critical(msg):
-    """ Print critical message to stderr """
+    """Print critical message to stderr"""
     sys.stderr.write(msg)
-    sys.stderr.write('\n')
+    sys.stderr.write("\n")
 
 
 class PartitionTable(list):
@@ -90,13 +153,25 @@ def __init__(self):
         super(PartitionTable, self).__init__(self)
 
     @classmethod
-    def from_csv(cls, csv_contents):
+    def from_file(cls, f):
+        data = f.read()
+        data_is_binary = data[0:2] == PartitionDefinition.MAGIC_BYTES
+        if data_is_binary:
+            status("Parsing binary partition input...")
+            return cls.from_binary(data), True
+
+        data = data.decode()
+        status("Parsing CSV input...")
+        return cls.from_csv(data), False
+
+    @classmethod
+    def from_csv(cls, csv_contents):  # noqa: C901
         res = PartitionTable()
         lines = csv_contents.splitlines()
 
         def expand_vars(f):
             f = os.path.expandvars(f)
-            m = re.match(r'(?<!\\)\$([A-Za-z_][A-Za-z0-9_]*)', f)
+            m = re.match(r"(?<!\\)\$([A-Za-z_][A-Za-z0-9_]*)", f)
             if m:
                 raise InputError("unknown variable '%s'" % m.group(1))
             return f
@@ -107,8 +182,11 @@ def expand_vars(f):
                 continue
             try:
                 res.append(PartitionDefinition.from_csv(line, line_no + 1))
-            except InputError as e:
-                raise InputError("Error at line %d: %s" % (line_no + 1, e))
+            except InputError as err:
+                raise InputError(
+                    "Error at line %d: %s\nPlease check extra_partition_subtypes.inc file in build/config directory"
+                    % (line_no + 1, err)
+                )
             except Exception:
                 critical("Unexpected error parsing CSV line %d: %s" % (line_no + 1, line))
                 raise
@@ -118,13 +196,18 @@ def expand_vars(f):
         for e in res:
             if e.offset is not None and e.offset < last_end:
                 if e == res[0]:
-                    raise InputError("CSV Error: First partition offset 0x%x overlaps end of partition table 0x%x"
-                                     % (e.offset, last_end))
+                    raise InputError(
+                        "CSV Error at line %d: Partitions overlap. Partition sets offset 0x%x. "
+                        "But partition table occupies the whole sector 0x%x. "
+                        "Use a free offset 0x%x or higher." % (e.line_no, e.offset, offset_part_table, last_end)
+                    )
                 else:
-                    raise InputError("CSV Error: Partitions overlap. Partition at line %d sets offset 0x%x. Previous partition ends 0x%x"
-                                     % (e.line_no, e.offset, last_end))
+                    raise InputError(
+                        "CSV Error at line %d: Partitions overlap. Partition sets offset 0x%x. Previous partition ends 0x%x"  # noqa: E501
+                        % (e.line_no, e.offset, last_end)
+                    )
             if e.offset is None:
-                pad_to = 0x10000 if e.type == APP_TYPE else 4
+                pad_to = get_alignment_offset_for_type(e.type)
                 if last_end % pad_to != 0:
                     last_end += pad_to - (last_end % pad_to)
                 e.offset = last_end
@@ -135,8 +218,8 @@ def expand_vars(f):
         return res
 
     def __getitem__(self, item):
-        """ Allow partition table access via name as well as by
-        numeric index. """
+        """Allow partition table access via name as well as by
+        numeric index."""
         if isinstance(item, str):
             for x in self:
                 if x.name == item:
@@ -146,28 +229,16 @@ def __getitem__(self, item):
             return super(PartitionTable, self).__getitem__(item)
 
     def find_by_type(self, ptype, subtype):
-        """ Return a partition by type & subtype, returns
-        None if not found """
+        """Return a partition by type & subtype, returns
+        None if not found"""
         # convert ptype & subtypes names (if supplied this way) to integer values
-        try:
-            ptype = TYPES[ptype]
-        except KeyError:
-            try:
-                ptype = int(ptype, 0)
-            except TypeError:
-                pass
-        try:
-            subtype = SUBTYPES[int(ptype)][subtype]
-        except KeyError:
-            try:
-                subtype = int(subtype, 0)
-            except TypeError:
-                pass
+        ptype = get_ptype_as_int(ptype)
+        subtype = get_subtype_as_int(ptype, subtype)
 
         for p in self:
             if p.type == ptype and p.subtype == subtype:
-                return p
-        return None
+                yield p
+        return
 
     def find_by_name(self, name):
         for p in self:
@@ -175,35 +246,53 @@ def find_by_name(self, name):
                 return p
         return None
 
-    def verify(self):
+    def verify(self):  # noqa: C901
         # verify each partition individually
         for p in self:
             p.verify()
 
         # check on duplicate name
         names = [p.name for p in self]
-        duplicates = set(n for n in names if names.count(n) > 1)
+        duplicates = set(n for n in names if names.count(n) > 1)  # noqa: C401
 
         # print sorted duplicate partitions by name
         if len(duplicates) != 0:
-            print("A list of partitions that have the same name:")
-            for p in sorted(self, key=lambda x:x.name):
+            critical("A list of partitions that have the same name:")
+            for p in sorted(self, key=lambda x: x.name):
                 if len(duplicates.intersection([p.name])) != 0:
-                    print("%s" % (p.to_csv()))
+                    critical("%s" % (p.to_csv()))
             raise InputError("Partition names must be unique")
 
         # check for overlaps
         last = None
-        for p in sorted(self, key=lambda x:x.offset):
+        for p in sorted(self, key=lambda x: x.offset):
             if p.offset < offset_part_table + PARTITION_TABLE_SIZE:
-                raise InputError("Partition offset 0x%x is below 0x%x" % (p.offset, offset_part_table + PARTITION_TABLE_SIZE))
+                raise InputError(
+                    "Partition offset 0x%x is below 0x%x" % (p.offset, offset_part_table + PARTITION_TABLE_SIZE)
+                )
             if last is not None and p.offset < last.offset + last.size:
-                raise InputError("Partition at 0x%x overlaps 0x%x-0x%x" % (p.offset, last.offset, last.offset + last.size - 1))
+                raise InputError(
+                    "Partition at 0x%x overlaps 0x%x-0x%x" % (p.offset, last.offset, last.offset + last.size - 1)
+                )
             last = p
 
+        # check that otadata should be unique
+        otadata_duplicates = [p for p in self if p.type == TYPES["data"] and p.subtype == SUBTYPES[DATA_TYPE]["ota"]]
+        if len(otadata_duplicates) > 1:
+            for p in otadata_duplicates:
+                critical("%s" % (p.to_csv()))
+            raise InputError(
+                'Found multiple otadata partitions. Only one partition can be defined with type="data"(1) and subtype="ota"(0).'  # noqa: E501
+            )
+
+        if len(otadata_duplicates) == 1 and otadata_duplicates[0].size != 0x2000:
+            p = otadata_duplicates[0]
+            critical("%s" % (p.to_csv()))
+            raise InputError("otadata partition must have size = 0x2000")
+
     def flash_size(self):
-        """ Return the size that partitions will occupy in flash
-            (ie the offset the last partition ends at)
+        """Return the size that partitions will occupy in flash
+        (ie the offset the last partition ends at)
         """
         try:
             last = sorted(self, reverse=True)[0]
@@ -211,21 +300,37 @@ def flash_size(self):
             return 0  # empty table!
         return last.offset + last.size
 
+    def verify_size_fits(self, flash_size_bytes: int) -> None:
+        """Check that partition table fits into the given flash size.
+        Raises InputError otherwise.
+        """
+        table_size = self.flash_size()
+        if flash_size_bytes < table_size:
+            mb = 1024 * 1024
+            raise InputError(
+                "Partitions tables occupies %.1fMB of flash (%d bytes) which does not fit in configured "
+                "flash size %dMB. Change the flash size in menuconfig under the 'Serial Flasher Config' menu."
+                % (table_size / mb, table_size, flash_size_bytes / mb)
+            )
+
     @classmethod
     def from_binary(cls, b):
         md5 = hashlib.md5()
         result = cls()
-        for o in range(0,len(b),32):
-            data = b[o:o + 32]
+        for o in range(0, len(b), 32):
+            data = b[o : o + 32]
             if len(data) != 32:
                 raise InputError("Partition table length must be a multiple of 32 bytes")
-            if data == b'\xFF' * 32:
+            if data == b"\xFF" * 32:
                 return result  # got end marker
             if md5sum and data[:2] == MD5_PARTITION_BEGIN[:2]:  # check only the magic number part
                 if data[16:] == md5.digest():
                     continue  # the next iteration will check for the end marker
                 else:
-                    raise InputError("MD5 checksums don't match! (computed: 0x%s, parsed: 0x%s)" % (md5.hexdigest(), binascii.hexlify(data[16:])))
+                    raise InputError(
+                        "MD5 checksums don't match! (computed: 0x%s, parsed: 0x%s)"
+                        % (md5.hexdigest(), binascii.hexlify(data[16:]))
+                    )
             else:
                 md5.update(data)
             result.append(PartitionDefinition.from_binary(data))
@@ -241,8 +346,7 @@ def to_binary(self):
         return result
 
     def to_csv(self, simple_formatting=False):
-        rows = ["# Espressif ESP32 Partition Table",
-                "# Name, Type, SubType, Offset, Size, Flags"]
+        rows = ["# ESP-IDF Partition Table", "# Name, Type, SubType, Offset, Size, Flags"]
         rows += [x.to_csv(simple_formatting) for x in self]
         return "\n".join(rows) + "\n"
 
@@ -250,16 +354,9 @@ def to_csv(self, simple_formatting=False):
 class PartitionDefinition(object):
     MAGIC_BYTES = b"\xAA\x50"
 
-    ALIGNMENT = {
-        APP_TYPE: 0x10000,
-        DATA_TYPE: 0x04,
-    }
-
     # dictionary maps flag name (as used in CSV flags list, property name)
     # to bit set in flags words in binary format
-    FLAGS = {
-        "encrypted": 0
-    }
+    FLAGS = {"encrypted": 0}
 
     # add subtypes for the 16 OTA slot values ("ota_XX, etc.")
     for ota_slot in range(NUM_PARTITION_SUBTYPE_APP_OTA):
@@ -275,7 +372,7 @@ def __init__(self):
 
     @classmethod
     def from_csv(cls, line, line_no):
-        """ Parse a line from the CSV """
+        """Parse a line from the CSV"""
         line_w_defaults = line + ",,,,"  # lazy way to support default fields
         fields = [f.strip() for f in line_w_defaults.split(",")]
 
@@ -299,18 +396,34 @@ def from_csv(cls, line, line_no):
         return res
 
     def __eq__(self, other):
-        return self.name == other.name and self.type == other.type \
-            and self.subtype == other.subtype and self.offset == other.offset \
+        return (
+            self.name == other.name
+            and self.type == other.type
+            and self.subtype == other.subtype
+            and self.offset == other.offset
             and self.size == other.size
+        )
 
     def __repr__(self):
         def maybe_hex(x):
             return "0x%x" % x if x is not None else "None"
-        return "PartitionDefinition('%s', 0x%x, 0x%x, %s, %s)" % (self.name, self.type, self.subtype or 0,
-                                                                  maybe_hex(self.offset), maybe_hex(self.size))
+
+        return "PartitionDefinition('%s', 0x%x, 0x%x, %s, %s)" % (
+            self.name,
+            self.type,
+            self.subtype or 0,
+            maybe_hex(self.offset),
+            maybe_hex(self.size),
+        )
 
     def __str__(self):
-        return "Part '%s' %d/%d @ 0x%x size 0x%x" % (self.name, self.type, self.subtype, self.offset or -1, self.size or -1)
+        return "Part '%s' %d/%d @ 0x%x size 0x%x" % (
+            self.name,
+            self.type,
+            self.subtype,
+            self.offset or -1,
+            self.size or -1,
+        )
 
     def __cmp__(self, other):
         return self.offset - other.offset
@@ -334,7 +447,9 @@ def parse_type(self, strval):
 
     def parse_subtype(self, strval):
         if strval == "":
-            return 0  # default
+            if self.type == TYPES["app"]:
+                raise InputError("App partition cannot have an empty subtype")
+            return SUBTYPES[DATA_TYPE]["undefined"]
         return parse_int(strval, SUBTYPES.get(self.type, {}))
 
     def parse_address(self, strval):
@@ -342,30 +457,37 @@ def parse_address(self, strval):
             return None  # PartitionTable will fill in default
         return parse_int(strval)
 
-    def verify(self):
+    def verify(self):  # noqa: C901
         if self.type is None:
             raise ValidationError(self, "Type field is not set")
         if self.subtype is None:
             raise ValidationError(self, "Subtype field is not set")
         if self.offset is None:
             raise ValidationError(self, "Offset field is not set")
-        align = self.ALIGNMENT.get(self.type, 4)
-        if self.offset % align:
-            raise ValidationError(self, "Offset 0x%x is not aligned to 0x%x" % (self.offset, align))
-        if self.size % align and secure:
-            raise ValidationError(self, "Size 0x%x is not aligned to 0x%x" % (self.size, align))
         if self.size is None:
             raise ValidationError(self, "Size field is not set")
+        offset_align = get_alignment_offset_for_type(self.type)
+        if self.offset % offset_align:
+            raise ValidationError(self, "Offset 0x%x is not aligned to 0x%x" % (self.offset, offset_align))
+        if self.type == APP_TYPE and secure is not SECURE_NONE:
+            size_align = get_alignment_size_for_type(self.type)
+            if self.size % size_align:
+                raise ValidationError(self, "Size 0x%x is not aligned to 0x%x" % (self.size, size_align))
 
         if self.name in TYPES and TYPES.get(self.name, "") != self.type:
-            critical("WARNING: Partition has name '%s' which is a partition type, but does not match this partition's "
-                     "type (0x%x). Mistake in partition table?" % (self.name, self.type))
+            critical(
+                "WARNING: Partition has name '%s' which is a partition type, but does not match this partition's "
+                "type (0x%x). Mistake in partition table?" % (self.name, self.type)
+            )
         all_subtype_names = []
         for names in (t.keys() for t in SUBTYPES.values()):
             all_subtype_names += names
         if self.name in all_subtype_names and SUBTYPES.get(self.type, {}).get(self.name, "") != self.subtype:
-            critical("WARNING: Partition has name '%s' which is a partition subtype, but this partition has "
-                     "non-matching type 0x%x and subtype 0x%x. Mistake in partition table?" % (self.name, self.type, self.subtype))
+            critical(
+                "WARNING: Partition has name '%s' which is a partition subtype, but this partition has "
+                "non-matching type 0x%x and subtype 0x%x. Mistake in partition table?"
+                % (self.name, self.type, self.subtype)
+            )
 
     STRUCT_FORMAT = b"<2sBBLL16sL"
 
@@ -374,14 +496,13 @@ def from_binary(cls, b):
         if len(b) != 32:
             raise InputError("Partition definition length must be exactly 32 bytes. Got %d bytes." % len(b))
         res = cls()
-        (magic, res.type, res.subtype, res.offset,
-         res.size, res.name, flags) = struct.unpack(cls.STRUCT_FORMAT, b)
+        (magic, res.type, res.subtype, res.offset, res.size, res.name, flags) = struct.unpack(cls.STRUCT_FORMAT, b)
         if b"\x00" in res.name:  # strip null byte padding from name string
-            res.name = res.name[:res.name.index(b"\x00")]
+            res.name = res.name[: res.name.index(b"\x00")]
         res.name = res.name.decode()
         if magic != cls.MAGIC_BYTES:
             raise InputError("Invalid magic bytes (%r) for partition definition" % magic)
-        for flag,bit in cls.FLAGS.items():
+        for flag, bit in cls.FLAGS.items():
             if flags & (1 << bit):
                 setattr(res, flag, True)
                 flags &= ~(1 << bit)
@@ -394,37 +515,45 @@ def get_flags_list(self):
 
     def to_binary(self):
         flags = sum((1 << self.FLAGS[flag]) for flag in self.get_flags_list())
-        return struct.pack(self.STRUCT_FORMAT,
-                           self.MAGIC_BYTES,
-                           self.type, self.subtype,
-                           self.offset, self.size,
-                           self.name.encode(),
-                           flags)
+        return struct.pack(
+            self.STRUCT_FORMAT,
+            self.MAGIC_BYTES,
+            self.type,
+            self.subtype,
+            self.offset,
+            self.size,
+            self.name.encode(),
+            flags,
+        )
 
     def to_csv(self, simple_formatting=False):
         def addr_format(a, include_sizes):
             if not simple_formatting and include_sizes:
-                for (val, suffix) in [(0x100000, "M"), (0x400, "K")]:
+                for val, suffix in [(0x100000, "M"), (0x400, "K")]:
                     if a % val == 0:
                         return "%d%s" % (a // val, suffix)
             return "0x%x" % a
 
         def lookup_keyword(t, keywords):
-            for k,v in keywords.items():
+            for k, v in keywords.items():
                 if simple_formatting is False and t == v:
                     return k
             return "%d" % t
 
         def generate_text_flags():
-            """ colon-delimited list of flags """
+            """colon-delimited list of flags"""
             return ":".join(self.get_flags_list())
 
-        return ",".join([self.name,
-                         lookup_keyword(self.type, TYPES),
-                         lookup_keyword(self.subtype, SUBTYPES.get(self.type, {})),
-                         addr_format(self.offset, False),
-                         addr_format(self.size, True),
-                         generate_text_flags()])
+        return ",".join(
+            [
+                self.name,
+                lookup_keyword(self.type, TYPES),
+                lookup_keyword(self.subtype, SUBTYPES.get(self.type, {})),
+                addr_format(self.offset, False),
+                addr_format(self.size, True),
+                generate_text_flags(),
+            ]
+        )
 
 
 def parse_int(v, keywords={}):
@@ -445,25 +574,47 @@ def parse_int(v, keywords={}):
             raise InputError("Value '%s' is not valid. Known keywords: %s" % (v, ", ".join(keywords)))
 
 
-def main():
+def main():  # noqa: C901
     global quiet
     global md5sum
     global offset_part_table
     global secure
-    parser = argparse.ArgumentParser(description='ESP32 partition table utility')
-
-    parser.add_argument('--flash-size', help='Optional flash size limit, checks partition table fits in flash',
-                        nargs='?', choices=['1MB', '2MB', '4MB', '8MB', '16MB'])
-    parser.add_argument('--disable-md5sum', help='Disable md5 checksum for the partition table', default=False, action='store_true')
-    parser.add_argument('--no-verify', help="Don't verify partition table fields", action='store_true')
-    parser.add_argument('--verify', '-v', help="Verify partition table fields (deprecated, this behaviour is "
-                                               "enabled by default and this flag does nothing.", action='store_true')
-    parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
-    parser.add_argument('--offset', '-o', help='Set offset partition table', default='0x8000')
-    parser.add_argument('--secure', help="Require app partitions to be suitable for secure boot", action='store_true')
-    parser.add_argument('input', help='Path to CSV or binary file to parse.', type=argparse.FileType('rb'))
-    parser.add_argument('output', help='Path to output converted binary or CSV file. Will use stdout if omitted.',
-                        nargs='?', default='-')
+    parser = argparse.ArgumentParser(description="ESP32 partition table utility")
+
+    parser.add_argument(
+        "--flash-size",
+        help="Optional flash size limit, checks partition table fits in flash",
+        nargs="?",
+        choices=["1MB", "2MB", "4MB", "8MB", "16MB", "32MB", "64MB", "128MB"],
+    )
+    parser.add_argument(
+        "--disable-md5sum", help="Disable md5 checksum for the partition table", default=False, action="store_true"
+    )
+    parser.add_argument("--no-verify", help="Don't verify partition table fields", action="store_true")
+    parser.add_argument(
+        "--verify",
+        "-v",
+        help="Verify partition table fields (deprecated, this behavior is "
+        "enabled by default and this flag does nothing.",
+        action="store_true",
+    )
+    parser.add_argument("--quiet", "-q", help="Don't print non-critical status messages to stderr", action="store_true")
+    parser.add_argument("--offset", "-o", help="Set offset partition table", default="0x8000")
+    parser.add_argument(
+        "--secure",
+        help="Require app partitions to be suitable for secure boot",
+        nargs="?",
+        const=SECURE_V1,
+        choices=[SECURE_V1, SECURE_V2],
+    )
+    parser.add_argument("--extra-partition-subtypes", help="Extra partition subtype entries", nargs="*")
+    parser.add_argument("input", help="Path to CSV or binary file to parse.", type=argparse.FileType("rb"))
+    parser.add_argument(
+        "output",
+        help="Path to output converted binary or CSV file. Will use stdout if omitted.",
+        nargs="?",
+        default="-",
+    )
 
     args = parser.parse_args()
 
@@ -471,15 +622,10 @@ def main():
     md5sum = not args.disable_md5sum
     secure = args.secure
     offset_part_table = int(args.offset, 0)
-    input = args.input.read()
-    input_is_binary = input[0:2] == PartitionDefinition.MAGIC_BYTES
-    if input_is_binary:
-        status("Parsing binary partition input...")
-        table = PartitionTable.from_binary(input)
-    else:
-        input = input.decode()
-        status("Parsing CSV input...")
-        table = PartitionTable.from_csv(input)
+    if args.extra_partition_subtypes:
+        add_extra_subtypes(args.extra_partition_subtypes)
+
+    table, input_is_binary = PartitionTable.from_file(args.input)
 
     if not args.no_verify:
         status("Verifying table...")
@@ -487,12 +633,7 @@ def main():
 
     if args.flash_size:
         size_mb = int(args.flash_size.replace("MB", ""))
-        size = size_mb * 1024 * 1024  # flash memory uses honest megabytes!
-        table_size = table.flash_size()
-        if size < table_size:
-            raise InputError("Partitions defined in '%s' occupy %.1fMB of flash (%d bytes) which does not fit in configured "
-                             "flash size %dMB. Change the flash size in menuconfig under the 'Serial Flasher Config' menu." %
-                             (args.input.name, table_size / 1024.0 / 1024.0, table_size, size_mb))
+        table.verify_size_fits(size_mb * 1024 * 1024)
 
     # Make sure that the output directory is created
     output_dir = os.path.abspath(os.path.dirname(args.output))
@@ -506,7 +647,7 @@ def main():
 
     if input_is_binary:
         output = table.to_csv()
-        with sys.stdout if args.output == '-' else open(args.output, 'w') as f:
+        with sys.stdout if args.output == "-" else open(args.output, "w") as f:
             f.write(output)
     else:
         output = table.to_binary()
@@ -514,7 +655,7 @@ def main():
             stdout_binary = sys.stdout.buffer  # Python 3
         except AttributeError:
             stdout_binary = sys.stdout
-        with stdout_binary if args.output == '-' else open(args.output, 'wb') as f:
+        with stdout_binary if args.output == "-" else open(args.output, "wb") as f:
             f.write(output)
 
 
@@ -525,11 +666,10 @@ def __init__(self, e):
 
 class ValidationError(InputError):
     def __init__(self, partition, message):
-        super(ValidationError, self).__init__(
-            "Partition %s invalid: %s" % (partition.name, message))
+        super(ValidationError, self).__init__("Partition %s invalid: %s" % (partition.name, message))
 
 
-if __name__ == '__main__':
+if __name__ == "__main__":
     try:
         main()
     except InputError as e:
diff --git a/tools/gen_insights_package.exe b/tools/gen_insights_package.exe
new file mode 100755
index 00000000000..444f34584d8
Binary files /dev/null and b/tools/gen_insights_package.exe differ
diff --git a/tools/gen_insights_package.py b/tools/gen_insights_package.py
new file mode 100644
index 00000000000..c9e2765ce94
--- /dev/null
+++ b/tools/gen_insights_package.py
@@ -0,0 +1,53 @@
+import os
+import sys
+import shutil
+import json
+
+APP_HEADER_SIZE = 32
+VERSION_NAME_OFFSET = APP_HEADER_SIZE + 16
+VERSION_NAME_SIZE = 32
+PROJECT_NAME_OFFSET = VERSION_NAME_OFFSET + VERSION_NAME_SIZE
+PROJECT_NAME_SIZE = 32
+
+# Input path of temporary build directory created by Arduino
+BUILD_DIR = sys.argv[1]
+# Input project name
+PROJ_NAME = sys.argv[2]
+# Input path to create output package
+TARGET_PATH = sys.argv[3]
+
+
+def main():
+    print("Creating ESP Insights Firmware Package.")
+    archive_path = os.path.join(BUILD_DIR, PROJ_NAME)
+    out_path = os.path.join(TARGET_PATH, PROJ_NAME)
+
+    # Create target archive directories
+    os.makedirs(archive_path, exist_ok=True)
+    os.makedirs(os.path.join(archive_path, "partition_table"), exist_ok=True)
+    os.makedirs(os.path.join(archive_path, "bootloader"), exist_ok=True)
+
+    # Copy files from build directory to archive directory
+    shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".bin"), archive_path)
+    shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".elf"), archive_path)
+    shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".map"), archive_path)
+    shutil.copy2(os.path.join(BUILD_DIR, "partitions.csv"), archive_path)
+    shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".bootloader.bin"), os.path.join(archive_path, "bootloader"))
+    shutil.copy2(os.path.join(BUILD_DIR, PROJ_NAME + ".partitions.bin"), os.path.join(archive_path, "partition_table"))
+
+    with open(os.path.join(BUILD_DIR, PROJ_NAME + ".bin"), "rb") as bin_file:
+        bin_file.seek(VERSION_NAME_OFFSET)
+        version_name = (bin_file.read(VERSION_NAME_SIZE).decode("utf-8")).split("\x00", 1)[0]
+        bin_file.seek(PROJECT_NAME_OFFSET)
+        project_name = (bin_file.read(PROJECT_NAME_SIZE).decode("utf-8")).split("\x00", 1)[0]
+        project_build_config_obj = {"project": {"name": project_name, "version": version_name}}
+        with open(os.path.join(archive_path, "project_build_config.json"), "w") as json_file:
+            json_file.write(json.dumps(project_build_config_obj))
+
+    shutil.make_archive(out_path, "zip", BUILD_DIR, PROJ_NAME)
+    print("Archive created at {}".format(out_path + ".zip"))
+    return
+
+
+if __name__ == "__main__":
+    main()
diff --git a/tools/get.exe b/tools/get.exe
index a498e5214f3..b56f2b98384 100644
Binary files a/tools/get.exe and b/tools/get.exe differ
diff --git a/tools/get.py b/tools/get.py
index cb1cfb95cb9..c791020b7e9 100755
--- a/tools/get.py
+++ b/tools/get.py
@@ -3,7 +3,7 @@
 """Script to download and extract tools
 
 This script will download and extract required tools into the current directory.
-Tools list is obtained from package/package_esp8266com_index.template.json file.
+Tools list is obtained from package/package_esp32_index.template.json file.
 """
 
 from __future__ import print_function
@@ -22,21 +22,33 @@
 import tarfile
 import zipfile
 import re
+import time
+import argparse
+
+# Initialize start_time globally
+start_time = -1
 
 if sys.version_info[0] == 3:
     from urllib.request import urlretrieve
     from urllib.request import urlopen
-    unicode = lambda s: str(s)
+
+    unicode = lambda s: str(s)  # noqa: E731
 else:
     # Not Python 3 - today, it is most likely to be Python 2
     from urllib import urlretrieve
     from urllib import urlopen
 
-if 'Windows' in platform.system():
+if "Windows" in platform.system():
     import requests
 
-current_dir = os.path.dirname(os.path.realpath(unicode(__file__)))
-dist_dir = current_dir + '/dist/'
+# determine if application is a script file or frozen exe
+if getattr(sys, "frozen", False):
+    current_dir = os.path.dirname(os.path.realpath(unicode(sys.executable)))
+elif __file__:
+    current_dir = os.path.dirname(os.path.realpath(unicode(__file__)))
+
+dist_dir = current_dir + "/dist/"
+
 
 def sha256sum(filename, blocksize=65536):
     hash = hashlib.sha256()
@@ -45,6 +57,7 @@ def sha256sum(filename, blocksize=65536):
             hash.update(block)
     return hash.hexdigest()
 
+
 def mkdir_p(path):
     try:
         os.makedirs(path)
@@ -52,46 +65,256 @@ def mkdir_p(path):
         if exc.errno != errno.EEXIST or not os.path.isdir(path):
             raise
 
-def report_progress(count, blockSize, totalSize):
-    percent = int(count*blockSize*100/totalSize)
-    percent = min(100, percent)
-    sys.stdout.write("\r%d%%" % percent)
-    sys.stdout.flush()
-
-def unpack(filename, destination):
-    dirname = ''
-    print('Extracting {0} ...'.format(os.path.basename(filename)))
-    sys.stdout.flush()
-    if filename.endswith('tar.gz'):
-        tfile = tarfile.open(filename, 'r:gz')
-        tfile.extractall(destination)
-        dirname = tfile.getnames()[0]
-    elif filename.endswith('zip'):
-        zfile = zipfile.ZipFile(filename)
-        zfile.extractall(destination)
-        dirname = zfile.namelist()[0]
+
+def format_time(seconds):
+    minutes, seconds = divmod(seconds, 60)
+    return "{:02}:{:05.2f}".format(int(minutes), seconds)
+
+
+def report_progress(block_count, block_size, total_size, start_time):
+    downloaded_size = block_count * block_size
+    time_elapsed = time.time() - start_time
+    current_speed = downloaded_size / (time_elapsed)
+
+    if sys.stdout.isatty():
+        if total_size > 0:
+            percent_complete = min((downloaded_size / total_size) * 100, 100)
+            sys.stdout.write(
+                f"\rDownloading... {percent_complete:.2f}% - {downloaded_size / 1024 / 1024:.2f} MB downloaded - Elapsed Time: {format_time(time_elapsed)} - Speed: {current_speed / 1024 / 1024:.2f} MB/s"  # noqa: E501
+            )
+        else:
+            sys.stdout.write(
+                f"\rDownloading... {downloaded_size / 1024 / 1024:.2f} MB downloaded - Elapsed Time: {format_time(time_elapsed)} - Speed: {current_speed / 1024 / 1024:.2f} MB/s"  # noqa: E501
+            )
+        sys.stdout.flush()
+
+
+def print_verification_progress(total_files, i, t1):
+    if sys.stdout.isatty():
+        sys.stdout.write(f"\rElapsed time {format_time(time.time() - t1)}")
+        sys.stdout.flush()
+
+
+def verify_files(filename, destination, rename_to):
+    # Set the path of the extracted directory
+    extracted_dir_path = destination
+    t1 = time.time()
+    if filename.endswith(".zip"):
+        try:
+            archive = zipfile.ZipFile(filename, "r")
+            file_list = archive.namelist()
+        except zipfile.BadZipFile:
+            if verbose:
+                print(f"Verification failed; aborted in {format_time(time.time() - t1)}")
+            return False
+    elif filename.endswith(".tar.gz"):
+        try:
+            archive = tarfile.open(filename, "r:gz")
+            file_list = archive.getnames()
+        except tarfile.ReadError:
+            if verbose:
+                print(f"Verification failed; aborted in {format_time(time.time() - t1)}")
+            return False
+    elif filename.endswith(".tar.xz"):
+        try:
+            archive = tarfile.open(filename, "r:xz")
+            file_list = archive.getnames()
+        except tarfile.ReadError:
+            if verbose:
+                print(f"Verification failed; aborted in {format_time(time.time() - t1)}")
+            return False
+    else:
+        raise NotImplementedError("Unsupported archive type")
+
+    try:
+        first_dir = file_list[0].split("/")[0]
+        total_files = len(file_list)
+        for i, zipped_file in enumerate(file_list, 1):
+            local_path = os.path.join(extracted_dir_path, zipped_file.replace(first_dir, rename_to, 1))
+            if not os.path.exists(local_path):
+                if verbose:
+                    print(f"\nMissing {zipped_file} on location: {extracted_dir_path}")
+                    print(f"Verification failed; aborted in {format_time(time.time() - t1)}")
+                return False
+            print_verification_progress(total_files, i, t1)
+    except Exception as e:
+        print(f"\nError: {e}")
+        return False
+
+    if verbose:
+        print(f"\nVerification passed; completed in {format_time(time.time() - t1)}")
+
+    return True
+
+
+def is_latest_version(destination, dirname, rename_to, cfile, checksum):
+    current_version = None
+    expected_version = None
+
+    try:
+        expected_version = checksum
+        with open(os.path.join(destination, rename_to, ".package_checksum"), "r") as f:
+            current_version = f.read()
+
+        if verbose:
+            print(f"\nTool: {rename_to}")
+            print(f"Current version: {current_version}")
+            print(f"Expected version: {expected_version}")
+
+        if current_version and current_version == expected_version:
+            if verbose:
+                print("Latest version already installed. Skipping extraction")
+            return True
+
+        if verbose:
+            print("New version detected")
+
+    except Exception as e:
+        if verbose:
+            print(f"Failed to verify version for {rename_to}: {e}")
+
+    return False
+
+
+def unpack(filename, destination, force_extract, checksum):  # noqa: C901
+    sys_name = platform.system()
+    dirname = ""
+    cfile = None  # Compressed file
+    file_is_corrupted = False
+    if not force_extract:
+        print(" > Verify archive... ", end="", flush=True)
+
+    try:
+        if filename.endswith("tar.gz"):
+            if tarfile.is_tarfile(filename):
+                cfile = tarfile.open(filename, "r:gz")
+                dirname = cfile.getnames()[0].split("/")[0]
+            else:
+                print("File corrupted!")
+                file_is_corrupted = True
+        elif filename.endswith("tar.xz"):
+            if tarfile.is_tarfile(filename):
+                cfile = tarfile.open(filename, "r:xz")
+                dirname = cfile.getnames()[0].split("/")[0]
+            else:
+                print("File corrupted!")
+                file_is_corrupted = True
+        elif filename.endswith("zip"):
+            if zipfile.is_zipfile(filename):
+                cfile = zipfile.ZipFile(filename)
+                dirname = cfile.namelist()[0].split("/")[0]
+            else:
+                print("File corrupted!")
+                file_is_corrupted = True
+        else:
+            raise NotImplementedError("Unsupported archive type")
+    except EOFError:
+        print("File corrupted or incomplete!")
+        cfile = None
+        file_is_corrupted = True
+
+    if file_is_corrupted:
+        corrupted_filename = filename + ".corrupted"
+        os.rename(filename, corrupted_filename)
+        if verbose:
+            print(f"Renaming corrupted archive to {corrupted_filename}")
+        return False
+
+    # A little trick to rename tool directories so they don't contain version number
+    rename_to = re.match(r"^([a-z][^\-]*\-*)+", dirname).group(0).strip("-")
+    if rename_to == dirname and dirname.startswith("esp32-arduino-libs-"):
+        rename_to = "esp32-arduino-libs"
+    elif rename_to == dirname and dirname.startswith("esptool-"):
+        rename_to = "esptool"
+
+    if not force_extract:
+        if is_latest_version(destination, dirname, rename_to, cfile, checksum):
+            if verify_files(filename, destination, rename_to):
+                print(" Files ok. Skipping Extraction")
+                return True
+        print(" Extracting archive...")
     else:
-        raise NotImplementedError('Unsupported archive type')
+        print(" Forcing extraction")
+
+    if os.path.isdir(os.path.join(destination, rename_to)):
+        print("Removing existing {0} ...".format(rename_to))
+        shutil.rmtree(os.path.join(destination, rename_to), ignore_errors=True)
+
+    if filename.endswith("tar.gz"):
+        if not cfile:
+            cfile = tarfile.open(filename, "r:gz")
+        cfile.extractall(destination, filter="tar")
+    elif filename.endswith("tar.xz"):
+        if not cfile:
+            cfile = tarfile.open(filename, "r:xz")
+        cfile.extractall(destination, filter="tar")
+    elif filename.endswith("zip"):
+        if not cfile:
+            cfile = zipfile.ZipFile(filename)
+        cfile.extractall(destination)
+    else:
+        raise NotImplementedError("Unsupported archive type")
 
-    # a little trick to rename tool directories so they don't contain version number
-    rename_to = re.match(r'^([a-z][^\-]*\-*)+', dirname).group(0).strip('-')
     if rename_to != dirname:
-        print('Renaming {0} to {1} ...'.format(dirname, rename_to))
-        if os.path.isdir(rename_to):
-            shutil.rmtree(rename_to)
+        print("Renaming {0} to {1} ...".format(dirname, rename_to))
         shutil.move(dirname, rename_to)
 
-def download_file(url,filename):
+    # Add execute permission to esptool on non-Windows platforms
+    if rename_to.startswith("esptool") and "CYGWIN_NT" not in sys_name and "Windows" not in sys_name:
+        st = os.stat(os.path.join(destination, rename_to, "esptool"))
+        os.chmod(os.path.join(destination, rename_to, "esptool"), st.st_mode | 0o111)
+
+    with open(os.path.join(destination, rename_to, ".package_checksum"), "w") as f:
+        f.write(checksum)
+
+    if verify_files(filename, destination, rename_to):
+        print(" Files extracted successfully.")
+        return True
+    else:
+        print(" Failed to extract files.")
+        return False
+
+
+def download_file_with_progress(url, filename, start_time):
+    import ssl
+    import contextlib
+
+    ctx = ssl.create_default_context()
+    ctx.check_hostname = False
+    ctx.verify_mode = ssl.CERT_NONE
+    with contextlib.closing(urlopen(url, context=ctx)) as fp:
+        total_size = int(fp.getheader("Content-Length", fp.getheader("Content-length", "0")))
+        block_count = 0
+        block_size = 1024 * 8
+        block = fp.read(block_size)
+        if block:
+            with open(filename, "wb") as out_file:
+                out_file.write(block)
+                block_count += 1
+                report_progress(block_count, block_size, total_size, start_time)
+                while True:
+                    block = fp.read(block_size)
+                    if not block:
+                        break
+                    out_file.write(block)
+                    block_count += 1
+                    report_progress(block_count, block_size, total_size, start_time)
+        else:
+            raise Exception("Non-existing file or connection error")
+
+
+def download_file(url, filename):
     import ssl
     import contextlib
+
     ctx = ssl.create_default_context()
     ctx.check_hostname = False
     ctx.verify_mode = ssl.CERT_NONE
-    with contextlib.closing(urlopen(url,context=ctx)) as fp:
+    with contextlib.closing(urlopen(url, context=ctx)) as fp:
         block_size = 1024 * 8
         block = fp.read(block_size)
         if block:
-            with open(filename,'wb') as out_file:
+            with open(filename, "wb") as out_file:
                 out_file.write(block)
                 while True:
                     block = fp.read(block_size)
@@ -99,72 +322,167 @@ def download_file(url,filename):
                         break
                     out_file.write(block)
         else:
-            raise Exception ('nonexisting file or connection error')
+            raise Exception("Non-existing file or connection error")
 
-def get_tool(tool):
+
+def get_tool(tool, force_download, force_extract):
     sys_name = platform.system()
-    archive_name = tool['archiveFileName']
+    archive_name = tool["archiveFileName"]
+    checksum = tool["checksum"][8:]
     local_path = dist_dir + archive_name
-    url = tool['url']
-    if not os.path.isfile(local_path):
-        print('Downloading ' + archive_name + ' ...')
+    url = tool["url"]
+    start_time = time.time()
+    print("")
+    if not os.path.isfile(local_path) or force_download:
+        if verbose:
+            print("Downloading '" + archive_name + "' to '" + local_path + "'")
+        else:
+            print("Downloading '" + archive_name + "' ...")
         sys.stdout.flush()
-        if 'CYGWIN_NT' in sys_name:
+        if "CYGWIN_NT" in sys_name:
             import ssl
+
             ctx = ssl.create_default_context()
             ctx.check_hostname = False
             ctx.verify_mode = ssl.CERT_NONE
             urlretrieve(url, local_path, report_progress, context=ctx)
-        elif 'Windows' in sys_name:
+        elif "Windows" in sys_name:
             r = requests.get(url)
-            f = open(local_path, 'wb')
+            f = open(local_path, "wb")
             f.write(r.content)
             f.close()
         else:
-            is_ci = os.environ.get('GITHUB_WORKSPACE');
+            is_ci = os.environ.get("GITHUB_WORKSPACE")
             if is_ci:
                 download_file(url, local_path)
             else:
-                urlretrieve(url, local_path, report_progress)
-                sys.stdout.write("\rDone\n")
+                try:
+                    urlretrieve(url, local_path, report_progress)
+                except:  # noqa: E722
+                    download_file_with_progress(url, local_path, start_time)
+                sys.stdout.write(" - Done\n")
                 sys.stdout.flush()
     else:
-        print('Tool {0} already downloaded'.format(archive_name))
+        print("Tool {0} already downloaded".format(archive_name))
         sys.stdout.flush()
-    unpack(local_path, '.')
+
+    if sha256sum(local_path) != checksum:
+        print("Checksum mismatch for {0}".format(archive_name))
+        return False
+
+    return unpack(local_path, ".", force_extract, checksum)
+
 
 def load_tools_list(filename, platform):
-    tools_info = json.load(open(filename))['packages'][0]['tools']
+    tools_info = json.load(open(filename))["packages"][0]["tools"]
     tools_to_download = []
     for t in tools_info:
-        tool_platform = [p for p in t['systems'] if p['host'] == platform]
+        if platform == "x86_64-mingw32":
+            if "i686-mingw32" not in [p["host"] for p in t["systems"]]:
+                raise Exception("Windows x64 requires both i686-mingw32 and x86_64-mingw32 tools")
+
+        tool_platform = [p for p in t["systems"] if p["host"] == platform]
         if len(tool_platform) == 0:
-            continue
+            # Fallback to x86 on Apple ARM
+            if platform == "arm64-apple-darwin":
+                tool_platform = [p for p in t["systems"] if p["host"] == "x86_64-apple-darwin"]
+                if len(tool_platform) == 0:
+                    continue
+            # Fallback to 32bit on 64bit x86 Windows
+            elif platform == "x86_64-mingw32":
+                tool_platform = [p for p in t["systems"] if p["host"] == "i686-mingw32"]
+                if len(tool_platform) == 0:
+                    continue
+            else:
+                if verbose:
+                    print(f"Tool {t['name']} is not available for platform {platform}")
+                continue
         tools_to_download.append(tool_platform[0])
     return tools_to_download
 
+
 def identify_platform():
-    arduino_platform_names = {'Darwin'  : {32 : 'i386-apple-darwin',   64 : 'x86_64-apple-darwin'},
-                              'Linux'   : {32 : 'i686-pc-linux-gnu',   64 : 'x86_64-pc-linux-gnu'},
-                              'LinuxARM': {32 : 'arm-linux-gnueabihf', 64 : 'aarch64-linux-gnu'},
-                              'Windows' : {32 : 'i686-mingw32',        64 : 'i686-mingw32'}}
+    arduino_platform_names = {
+        "Darwin": {32: "i386-apple-darwin", 64: "x86_64-apple-darwin"},
+        "DarwinARM": {32: "arm64-apple-darwin", 64: "arm64-apple-darwin"},
+        "Linux": {32: "i686-pc-linux-gnu", 64: "x86_64-pc-linux-gnu"},
+        "LinuxARM": {32: "arm-linux-gnueabihf", 64: "aarch64-linux-gnu"},
+        "Windows": {32: "i686-mingw32", 64: "x86_64-mingw32"},
+    }
     bits = 32
     if sys.maxsize > 2**32:
         bits = 64
     sys_name = platform.system()
     sys_platform = platform.platform()
-    if 'Linux' in sys_name and (sys_platform.find('arm') > 0 or sys_platform.find('aarch64') > 0):
-        sys_name = 'LinuxARM'
-    if 'CYGWIN_NT' in sys_name:
-        sys_name = 'Windows'
-    print('System: %s, Bits: %d, Info: %s' % (sys_name, bits, sys_platform))
+    if "Darwin" in sys_name and (sys_platform.find("arm") > 0 or sys_platform.find("arm64") > 0):
+        sys_name = "DarwinARM"
+    if "Linux" in sys_name and (sys_platform.find("arm") > 0 or sys_platform.find("aarch64") > 0):
+        sys_name = "LinuxARM"
+    if "CYGWIN_NT" in sys_name:
+        sys_name = "Windows"
+    print("System: %s, Bits: %d, Info: %s" % (sys_name, bits, sys_platform))
     return arduino_platform_names[sys_name][bits]
 
-if __name__ == '__main__':
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(description="Download and extract tools")
+
+    parser.add_argument("-v", "--verbose", action="store_true", required=False, help="Print verbose output")
+
+    parser.add_argument("-d", "--force_download", action="store_true", required=False, help="Force download of tools")
+
+    parser.add_argument("-e", "--force_extract", action="store_true", required=False, help="Force extraction of tools")
+
+    parser.add_argument(
+        "-f", "--force_all", action="store_true", required=False, help="Force download and extraction of tools"
+    )
+
+    parser.add_argument("-t", "--test", action="store_true", required=False, help=argparse.SUPPRESS)
+
+    args = parser.parse_args()
+
+    verbose = args.verbose
+    force_download = args.force_download
+    force_extract = args.force_extract
+    force_all = args.force_all
+    is_test = args.test
+
+    # Set current directory to the script location
+    if getattr(sys, "frozen", False):
+        os.chdir(os.path.dirname(sys.executable))
+    else:
+        os.chdir(os.path.dirname(os.path.abspath(__file__)))
+
+    if is_test and (force_download or force_extract or force_all):
+        print("Cannot combine test (-t) and forced execution (-d | -e | -f)")
+        parser.print_help(sys.stderr)
+        sys.exit(1)
+
+    if is_test:
+        print("Test run!")
+
+    if force_all:
+        force_download = True
+        force_extract = True
+
     identified_platform = identify_platform()
-    print('Platform: {0}'.format(identified_platform))
-    tools_to_download = load_tools_list(current_dir + '/../package/package_esp32_index.template.json', identified_platform)
+    print("Platform: {0}".format(identified_platform))
+    tools_to_download = load_tools_list(
+        current_dir + "/../package/package_esp32_index.template.json", identified_platform
+    )
     mkdir_p(dist_dir)
+
+    print("\nDownloading and extracting tools...")
+
     for tool in tools_to_download:
-        get_tool(tool)
-    print('Platform Tools Installed')
+        if is_test:
+            print("Would install: {0}".format(tool["archiveFileName"]))
+        else:
+            if not get_tool(tool, force_download, force_extract):
+                if verbose:
+                    print(f"Tool {tool['archiveFileName']} was corrupted. Re-downloading...\n")
+                if not get_tool(tool, True, force_extract):
+                    print(f"Tool {tool['archiveFileName']} was corrupted, but re-downloading did not help!\n")
+                    sys.exit(1)
+
+    print("\nPlatform Tools Installed")
diff --git a/tools/ide-debug/svd/esp32.svd b/tools/ide-debug/svd/esp32.svd
new file mode 100644
index 00000000000..7e895e4e354
--- /dev/null
+++ b/tools/ide-debug/svd/esp32.svd
@@ -0,0 +1,46087 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+  <vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
+  <vendorID>ESPRESSIF</vendorID>
+  <name>ESP32</name>
+  <series>ESP32</series>
+  <version>8</version>
+  <description>32-bit MCU &amp; 2.4 GHz Wi-Fi &amp; Bluetooth/Bluetooth LE</description>
+  <licenseText>
+    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+</licenseText>
+  <cpu>
+    <name>Xtensa LX6</name>
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>true</fpuPresent>
+    <nvicPrioBits>3</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>32</addressUnitBits>
+  <width>32</width>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AES</name>
+      <description>AES (Advanced Encryption Standard) Accelerator</description>
+      <groupName>AES</groupName>
+      <baseAddress>0x3FF01000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x40</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>START</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>Write 1 to start the AES operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>AES Idle register. Reads ’zero’ while the AES Accelerator is busy processing; reads ’one’ otherwise.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Selects the AES accelerator mode of operation. See Table 22-1 for details.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>KEY_%s</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY</name>
+              <description>AES key material register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TEXT_%s</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT</name>
+              <description>Plaintext and ciphertext register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENDIAN</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENDIAN</name>
+              <description>Endianness selection register. See Table 22-2 for details.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>APB_CTRL</name>
+      <description>Advanced Peripheral Bus Controller</description>
+      <groupName>APB_CTRL</groupName>
+      <baseAddress>0x3FF66000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x44</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SYSCLK_CONF</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002000</resetValue>
+          <fields>
+            <field>
+              <name>PRE_DIV_CNT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_320M_EN</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_TICK_CNT</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>QUICK_CLK_CHNG</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL_TICK_CONF</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000027</resetValue>
+          <fields>
+            <field>
+              <name>XTAL_TICK_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PLL_TICK_CONF</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000004F</resetValue>
+          <fields>
+            <field>
+              <name>PLL_TICK_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CK8M_TICK_CONF</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>CK8M_TICK_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_CTRL</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x007F8240</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_START_FORCE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_START</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_MUX</name>
+              <description>1: SAR ADC2 is controlled by DIG ADC2 CTRL  0: SAR ADC2 is controlled by PWDET CTRL</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_WORK_MODE</name>
+              <description>0: single mode  1: double mode  2: alternate mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_SEL</name>
+              <description>0: SAR1  1: SAR2  only work for single SAR mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_GATED</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_DIV</name>
+              <description>SAR clock divider</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_PATT_P_CLEAR</name>
+              <description>clear the pointer of pattern table for DIG ADC1 CTRL</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_PATT_P_CLEAR</name>
+              <description>clear the pointer of pattern table for DIG ADC2 CTRL</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_DATA_SAR_SEL</name>
+              <description>1: sar_sel will be coded by the MSB of the 16-bit output data  in this case the resolution should not be larger than 11 bits.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_DATA_TO_I2S</name>
+              <description>1: I2S input data is from SAR ADC (for DMA)  0: I2S input data is from GPIO matrix</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_CTRL2</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001FE</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_MEAS_NUM_LIMIT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_MAX_MEAS_NUM</name>
+              <description>max conversion number</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_INV</name>
+              <description>1: data to DIG ADC1 CTRL is inverted  otherwise not</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_INV</name>
+              <description>1: data to DIG ADC2 CTRL is inverted  otherwise not</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_FSM</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0208FF08</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_RSTB_WAIT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_STANDBY_WAIT</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_START_WAIT</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAMPLE_CYCLE</name>
+              <description>sample cycles</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_SAR1_PATT_TAB1</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_SAR1_PATT_TAB2</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_SAR1_PATT_TAB3</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_PATT_TAB3</name>
+              <description>Item 8 ~ 11 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_SAR1_PATT_TAB4</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_PATT_TAB4</name>
+              <description>Item 12 ~ 15 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_SAR2_PATT_TAB1</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 2 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_SAR2_PATT_TAB2</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 2 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_SAR2_PATT_TAB3</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_PATT_TAB3</name>
+              <description>Item 8 ~ 11 for pattern table 2 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC_SAR2_PATT_TAB4</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_PATT_TAB4</name>
+              <description>Item 12 ~ 15 for pattern table 2 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APLL_TICK_CONF</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000063</resetValue>
+          <fields>
+            <field>
+              <name>APLL_TICK_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x16042000</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>BB</name>
+      <description>Peripheral BB</description>
+      <groupName>BB</groupName>
+      <baseAddress>0x3FF5D000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>BBPD_CTRL</name>
+          <description>Baseband control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DC_EST_FORCE_PD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DC_EST_FORCE_PU</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FFT_FORCE_PD</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FFT_FORCE_PU</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DPORT</name>
+      <description>Peripheral DPORT</description>
+      <groupName>DPORT</groupName>
+      <baseAddress>0x3FF00000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x5C0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WIFI_MAC</name>
+        <value>0</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_NMI</name>
+        <value>1</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_BB</name>
+        <value>2</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_MAC</name>
+        <value>3</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_BB</name>
+        <value>4</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_BB_NMI</name>
+        <value>5</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBT</name>
+        <value>6</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBLE</name>
+        <value>7</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBT_NMI</name>
+        <value>8</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBLE_NMI</name>
+        <value>9</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PRO_BOOT_REMAP_CTRL</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_BOOT_REMAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_BOOT_REMAP_CTRL</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_BOOT_REMAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACCESS_CHECK</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_APB_MASK0</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRODPORT_APB_MASK0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_APB_MASK1</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRODPORT_APB_MASK1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DPORT_APB_MASK0</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APPDPORT_APB_MASK0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DPORT_APB_MASK1</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APPDPORT_APB_MASK1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_CLK_EN</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_CLK_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_RST_EN</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_RST_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_CFG</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_CFG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_CFG_2</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_CFG_2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APPCPU_CTRL_A</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>APPCPU_RESETTING</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APPCPU_CTRL_B</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APPCPU_CLKGATE_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APPCPU_CTRL_C</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APPCPU_RUNSTALL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APPCPU_CTRL_D</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APPCPU_BOOT_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PER_CONF</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOWSPEED_CLK_SEL</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_CLK_RTC_SEL</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_CTRL</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CACHE_MODE</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_ENABLE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_FLUSH_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_FLUSH_DONE</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_LOCK_0_EN</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_LOCK_1_EN</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_LOCK_2_EN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_LOCK_3_EN</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_SINGLE_IRAM_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM_SPLIT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_SPI_REQ</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_SLAVE_REQ</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AHB_SPI_REQ</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_REQ</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DRAM_HL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_CTRL1</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000008FF</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CACHE_MASK_IRAM0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MASK_IRAM1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MASK_IROM0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MASK_DRAM1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MASK_DROM0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MASK_OPSDRAM</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CMMU_SRAM_PAGE_MODE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CMMU_FLASH_PAGE_MODE</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CMMU_FORCE_ON</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CMMU_PD</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MMU_IA_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_LOCK_0_ADDR</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_LOCK_1_ADDR</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_LOCK_2_ADDR</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_LOCK_3_ADDR</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CACHE_CTRL</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_CACHE_MODE</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_ENABLE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_FLUSH_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_FLUSH_DONE</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CACHE_LOCK_0_EN</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_LOCK_1_EN</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_LOCK_2_EN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_LOCK_3_EN</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_SINGLE_IRAM_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_DRAM_SPLIT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_AHB_SPI_REQ</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_SLAVE_REQ</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_DRAM_HL</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CACHE_CTRL1</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000008FF</resetValue>
+          <fields>
+            <field>
+              <name>APP_CACHE_MASK_IRAM0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_MASK_IRAM1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_MASK_IROM0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_MASK_DRAM1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_MASK_DROM0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_MASK_OPSDRAM</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CMMU_SRAM_PAGE_MODE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CMMU_FLASH_PAGE_MODE</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CMMU_FORCE_ON</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CMMU_PD</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_MMU_IA_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CACHE_LOCK_0_ADDR</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CACHE_LOCK_1_ADDR</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CACHE_LOCK_2_ADDR</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CACHE_LOCK_3_ADDR</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRACEMEM_MUX_MODE</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRACEMEM_MUX_MODE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TRACEMEM_ENA</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_TRACEMEM_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TRACEMEM_ENA</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_TRACEMEM_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MUX_MODE</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MUX_MODE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_PAGE_MODE</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_IMMU_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IMMU_PAGE_MODE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_PAGE_MODE</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_DMMU_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMMU_PAGE_MODE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_MPU_ENA</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHARE_ROM_MPU_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ROM_MPU_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_ROM_MPU_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_PD_MASK</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>LSLP_MEM_PD_MASK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_PD_CTRL</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ROM_PD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_ROM_PD</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SHARE_ROM_PD</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_FO_CTRL</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ROM_FO</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_ROM_FO</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SHARE_ROM_FO</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_PD_CTRL_0</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SRAM_PD_0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_PD_CTRL_1</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SRAM_PD_1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_FO_CTRL_0</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_FO_0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_FO_CTRL_1</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_FO_1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IRAM_DRAM_AHB_SEL</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MASK_PRO_IRAM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASK_APP_IRAM</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASK_PRO_DRAM</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASK_APP_DRAM</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASK_AHB</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAC_DUMP_MODE</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TAG_FO_CTRL</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000101</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CACHE_TAG_FORCE_ON</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_TAG_PD</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_TAG_FORCE_ON</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_TAG_PD</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_LITE_MASK</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRODPORT</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APPDPORT</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_LITE_SDHOST_PID</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_MPU_TABLE_0</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>AHB_ACCESS_GRANT_0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_MPU_TABLE_1</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001FF</resetValue>
+          <fields>
+            <field>
+              <name>AHB_ACCESS_GRANT_1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_INF_SEL</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_IO_SWAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LINK_DEVICE_SEL</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_CLK_EN</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xF9C1E06F</resetValue>
+          <fields>
+            <field>
+              <name>TIMERS_CLK_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI01_CLK_EN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_CLK_EN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDG_CLK_EN</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S0_CLK_EN</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CLK_EN</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_CLK_EN</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C0_EXT0_CLK_EN</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI0_CLK_EN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_CLK_EN</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCNT_CLK_EN</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_CLK_EN</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI1_CLK_EN</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_CLK_EN</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_CLK_EN</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP1_CLK_EN</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_CLK_EN</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM0_CLK_EN</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT1_CLK_EN</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TWAI_CLK_EN</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM1_CLK_EN</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S1_CLK_EN</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_CLK_EN</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART2_CLK_EN</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_CLK_EN</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM2_CLK_EN</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM3_CLK_EN</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_RST_EN</name>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMERS_RST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI01_RST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDG_RST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S0_RST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_RST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_RST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C0_EXT0_RST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI0_RST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_RST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCNT_RST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_RST</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI1_RST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_RST</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_RST</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP1_RST</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_RST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM0_RST</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT1_RST</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TWAI_RST</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM1_RST</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S1_RST</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_RST</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART2_RST</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_RST</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM2_RST</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM3_RST</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_SPI_CONFIG</name>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_SPI_MASK_PRO</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SPI_MASK_APP</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_ENCRYPT_ENABLE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DECRYPT_ENABLE</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_CLK_EN</name>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFCE030</resetValue>
+          <fields>
+            <field>
+              <name>WIFI_CLK_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_CLK_WIFI_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_CLK_WIFI_BT_COMMON</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_CLK_BT_EN</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_RST_EN</name>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_RST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BB_RST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FE_RST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAC_RST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_RST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BTMAC_RST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_RST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_HOST_RST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EMAC_RST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MACPWR_RST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RW_BTMAC_RST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RW_BTLP_RST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_LPCK_DIV_INT</name>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>BT_LPCK_DIV_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BTEXTWAKEUP_REQ</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_LPCK_DIV_FRAC</name>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02001001</resetValue>
+          <fields>
+            <field>
+              <name>BT_LPCK_DIV_B</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_LPCK_DIV_A</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_RTC_SLOW</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_8M</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL32K</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0</name>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1</name>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2</name>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3</name>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_0</name>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_INTR_STATUS_0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_1</name>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_INTR_STATUS_1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_2</name>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_INTR_STATUS_2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INTR_STATUS_0</name>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_INTR_STATUS_0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INTR_STATUS_1</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_INTR_STATUS_1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INTR_STATUS_2</name>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_INTR_STATUS_2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_MAC_INTR_MAP</name>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MAC_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_MAC_NMI_MAP</name>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MAC_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BB_INT_MAP</name>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_BB_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BT_MAC_INT_MAP</name>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_BT_MAC_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BT_BB_INT_MAP</name>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_BT_BB_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BT_BB_NMI_MAP</name>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_BT_BB_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RWBT_IRQ_MAP</name>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RWBT_IRQ_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RWBLE_IRQ_MAP</name>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RWBLE_IRQ_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RWBT_NMI_MAP</name>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RWBT_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RWBLE_NMI_MAP</name>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RWBLE_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SLC0_INTR_MAP</name>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SLC0_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SLC1_INTR_MAP</name>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SLC1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UHCI0_INTR_MAP</name>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UHCI0_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UHCI1_INTR_MAP</name>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UHCI1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_T0_LEVEL_INT_MAP</name>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_T0_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_T1_LEVEL_INT_MAP</name>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_T1_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_WDT_LEVEL_INT_MAP</name>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_WDT_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_LACT_LEVEL_INT_MAP</name>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_LACT_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_T0_LEVEL_INT_MAP</name>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_T0_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_T1_LEVEL_INT_MAP</name>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_T1_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_WDT_LEVEL_INT_MAP</name>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_WDT_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_LACT_LEVEL_INT_MAP</name>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_LACT_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_GPIO_INTERRUPT_MAP</name>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_GPIO_INTERRUPT_PRO_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_GPIO_INTERRUPT_NMI_MAP</name>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_GPIO_INTERRUPT_PRO_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_INTR_FROM_CPU_0_MAP</name>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_INTR_FROM_CPU_0_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_INTR_FROM_CPU_1_MAP</name>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_INTR_FROM_CPU_1_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_INTR_FROM_CPU_2_MAP</name>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_INTR_FROM_CPU_2_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_INTR_FROM_CPU_3_MAP</name>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_INTR_FROM_CPU_3_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI_INTR_0_MAP</name>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI_INTR_0_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI_INTR_1_MAP</name>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI_INTR_1_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI_INTR_2_MAP</name>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI_INTR_2_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI_INTR_3_MAP</name>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI_INTR_3_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_I2S0_INT_MAP</name>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I2S0_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_I2S1_INT_MAP</name>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I2S1_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UART_INTR_MAP</name>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UART_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UART1_INTR_MAP</name>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UART1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UART2_INTR_MAP</name>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UART2_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SDIO_HOST_INTERRUPT_MAP</name>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SDIO_HOST_INTERRUPT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_EMAC_INT_MAP</name>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_EMAC_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PWM0_INTR_MAP</name>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PWM0_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PWM1_INTR_MAP</name>
+          <addressOffset>0x1A4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PWM1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PWM2_INTR_MAP</name>
+          <addressOffset>0x1A8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PWM2_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PWM3_INTR_MAP</name>
+          <addressOffset>0x1AC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PWM3_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_LEDC_INT_MAP</name>
+          <addressOffset>0x1B0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_LEDC_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_EFUSE_INT_MAP</name>
+          <addressOffset>0x1B4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_EFUSE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CAN_INT_MAP</name>
+          <addressOffset>0x1B8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CAN_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RTC_CORE_INTR_MAP</name>
+          <addressOffset>0x1BC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RTC_CORE_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RMT_INTR_MAP</name>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RMT_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PCNT_INTR_MAP</name>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PCNT_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_I2C_EXT0_INTR_MAP</name>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I2C_EXT0_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_I2C_EXT1_INTR_MAP</name>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I2C_EXT1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RSA_INTR_MAP</name>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RSA_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI1_DMA_INT_MAP</name>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI1_DMA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI2_DMA_INT_MAP</name>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI2_DMA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI3_DMA_INT_MAP</name>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI3_DMA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_WDG_INT_MAP</name>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_WDG_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TIMER_INT1_MAP</name>
+          <addressOffset>0x1E4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TIMER_INT1_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TIMER_INT2_MAP</name>
+          <addressOffset>0x1E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TIMER_INT2_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_T0_EDGE_INT_MAP</name>
+          <addressOffset>0x1EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_T0_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_T1_EDGE_INT_MAP</name>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_T1_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_WDT_EDGE_INT_MAP</name>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_WDT_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_LACT_EDGE_INT_MAP</name>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_LACT_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_T0_EDGE_INT_MAP</name>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_T0_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_T1_EDGE_INT_MAP</name>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_T1_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_WDT_EDGE_INT_MAP</name>
+          <addressOffset>0x204</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_WDT_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_LACT_EDGE_INT_MAP</name>
+          <addressOffset>0x208</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_LACT_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_MMU_IA_INT_MAP</name>
+          <addressOffset>0x20C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MMU_IA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_MPU_IA_INT_MAP</name>
+          <addressOffset>0x210</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MPU_IA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_IA_INT_MAP</name>
+          <addressOffset>0x214</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CACHE_IA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_MAC_INTR_MAP</name>
+          <addressOffset>0x218</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_MAC_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_MAC_NMI_MAP</name>
+          <addressOffset>0x21C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_MAC_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_BB_INT_MAP</name>
+          <addressOffset>0x220</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_BB_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_BT_MAC_INT_MAP</name>
+          <addressOffset>0x224</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_BT_MAC_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_BT_BB_INT_MAP</name>
+          <addressOffset>0x228</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_BT_BB_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_BT_BB_NMI_MAP</name>
+          <addressOffset>0x22C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_BT_BB_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_RWBT_IRQ_MAP</name>
+          <addressOffset>0x230</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_RWBT_IRQ_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_RWBLE_IRQ_MAP</name>
+          <addressOffset>0x234</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_RWBLE_IRQ_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_RWBT_NMI_MAP</name>
+          <addressOffset>0x238</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_RWBT_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_RWBLE_NMI_MAP</name>
+          <addressOffset>0x23C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_RWBLE_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SLC0_INTR_MAP</name>
+          <addressOffset>0x240</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SLC0_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SLC1_INTR_MAP</name>
+          <addressOffset>0x244</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SLC1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_UHCI0_INTR_MAP</name>
+          <addressOffset>0x248</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_UHCI0_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_UHCI1_INTR_MAP</name>
+          <addressOffset>0x24C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_UHCI1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG_T0_LEVEL_INT_MAP</name>
+          <addressOffset>0x250</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG_T0_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG_T1_LEVEL_INT_MAP</name>
+          <addressOffset>0x254</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG_T1_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG_WDT_LEVEL_INT_MAP</name>
+          <addressOffset>0x258</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG_WDT_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG_LACT_LEVEL_INT_MAP</name>
+          <addressOffset>0x25C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG_LACT_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG1_T0_LEVEL_INT_MAP</name>
+          <addressOffset>0x260</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG1_T0_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG1_T1_LEVEL_INT_MAP</name>
+          <addressOffset>0x264</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG1_T1_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG1_WDT_LEVEL_INT_MAP</name>
+          <addressOffset>0x268</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG1_WDT_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG1_LACT_LEVEL_INT_MAP</name>
+          <addressOffset>0x26C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG1_LACT_LEVEL_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_GPIO_INTERRUPT_MAP</name>
+          <addressOffset>0x270</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_GPIO_INTERRUPT_APP_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_GPIO_INTERRUPT_NMI_MAP</name>
+          <addressOffset>0x274</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_GPIO_INTERRUPT_APP_NMI_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_INTR_FROM_CPU_0_MAP</name>
+          <addressOffset>0x278</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_CPU_INTR_FROM_CPU_0_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_INTR_FROM_CPU_1_MAP</name>
+          <addressOffset>0x27C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_CPU_INTR_FROM_CPU_1_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_INTR_FROM_CPU_2_MAP</name>
+          <addressOffset>0x280</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_CPU_INTR_FROM_CPU_2_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_INTR_FROM_CPU_3_MAP</name>
+          <addressOffset>0x284</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_CPU_INTR_FROM_CPU_3_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SPI_INTR_0_MAP</name>
+          <addressOffset>0x288</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SPI_INTR_0_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SPI_INTR_1_MAP</name>
+          <addressOffset>0x28C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SPI_INTR_1_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SPI_INTR_2_MAP</name>
+          <addressOffset>0x290</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SPI_INTR_2_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SPI_INTR_3_MAP</name>
+          <addressOffset>0x294</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SPI_INTR_3_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_I2S0_INT_MAP</name>
+          <addressOffset>0x298</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_I2S0_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_I2S1_INT_MAP</name>
+          <addressOffset>0x29C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_I2S1_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_UART_INTR_MAP</name>
+          <addressOffset>0x2A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_UART_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_UART1_INTR_MAP</name>
+          <addressOffset>0x2A4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_UART1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_UART2_INTR_MAP</name>
+          <addressOffset>0x2A8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_UART2_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SDIO_HOST_INTERRUPT_MAP</name>
+          <addressOffset>0x2AC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SDIO_HOST_INTERRUPT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_EMAC_INT_MAP</name>
+          <addressOffset>0x2B0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_EMAC_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_PWM0_INTR_MAP</name>
+          <addressOffset>0x2B4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_PWM0_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_PWM1_INTR_MAP</name>
+          <addressOffset>0x2B8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_PWM1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_PWM2_INTR_MAP</name>
+          <addressOffset>0x2BC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_PWM2_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_PWM3_INTR_MAP</name>
+          <addressOffset>0x2C0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_PWM3_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_LEDC_INT_MAP</name>
+          <addressOffset>0x2C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_LEDC_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_EFUSE_INT_MAP</name>
+          <addressOffset>0x2C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_EFUSE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CAN_INT_MAP</name>
+          <addressOffset>0x2CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_CAN_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_RTC_CORE_INTR_MAP</name>
+          <addressOffset>0x2D0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_RTC_CORE_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_RMT_INTR_MAP</name>
+          <addressOffset>0x2D4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_RMT_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_PCNT_INTR_MAP</name>
+          <addressOffset>0x2D8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_PCNT_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_I2C_EXT0_INTR_MAP</name>
+          <addressOffset>0x2DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_I2C_EXT0_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_I2C_EXT1_INTR_MAP</name>
+          <addressOffset>0x2E0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_I2C_EXT1_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_RSA_INTR_MAP</name>
+          <addressOffset>0x2E4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_RSA_INTR_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SPI1_DMA_INT_MAP</name>
+          <addressOffset>0x2E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SPI1_DMA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SPI2_DMA_INT_MAP</name>
+          <addressOffset>0x2EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SPI2_DMA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_SPI3_DMA_INT_MAP</name>
+          <addressOffset>0x2F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_SPI3_DMA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_WDG_INT_MAP</name>
+          <addressOffset>0x2F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_WDG_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TIMER_INT1_MAP</name>
+          <addressOffset>0x2F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TIMER_INT1_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TIMER_INT2_MAP</name>
+          <addressOffset>0x2FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TIMER_INT2_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG_T0_EDGE_INT_MAP</name>
+          <addressOffset>0x300</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG_T0_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG_T1_EDGE_INT_MAP</name>
+          <addressOffset>0x304</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG_T1_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG_WDT_EDGE_INT_MAP</name>
+          <addressOffset>0x308</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG_WDT_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG_LACT_EDGE_INT_MAP</name>
+          <addressOffset>0x30C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG_LACT_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG1_T0_EDGE_INT_MAP</name>
+          <addressOffset>0x310</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG1_T0_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG1_T1_EDGE_INT_MAP</name>
+          <addressOffset>0x314</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG1_T1_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG1_WDT_EDGE_INT_MAP</name>
+          <addressOffset>0x318</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG1_WDT_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_TG1_LACT_EDGE_INT_MAP</name>
+          <addressOffset>0x31C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_TG1_LACT_EDGE_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_MMU_IA_INT_MAP</name>
+          <addressOffset>0x320</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_MMU_IA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_MPU_IA_INT_MAP</name>
+          <addressOffset>0x324</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_MPU_IA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CACHE_IA_INT_MAP</name>
+          <addressOffset>0x328</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APP_CACHE_IA_INT_MAP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_UART</name>
+          <addressOffset>0x32C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UART_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_SPI1</name>
+          <addressOffset>0x330</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI1_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_SPI0</name>
+          <addressOffset>0x334</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI0_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_GPIO</name>
+          <addressOffset>0x338</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_FE2</name>
+          <addressOffset>0x33C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FE2_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_FE</name>
+          <addressOffset>0x340</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FE_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_TIMER</name>
+          <addressOffset>0x344</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_RTC</name>
+          <addressOffset>0x348</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_IO_MUX</name>
+          <addressOffset>0x34C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IOMUX_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_WDG</name>
+          <addressOffset>0x350</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDG_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_HINF</name>
+          <addressOffset>0x354</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HINF_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_UHCI1</name>
+          <addressOffset>0x358</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UHCI1_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_MISC</name>
+          <addressOffset>0x35C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MISC_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_I2C</name>
+          <addressOffset>0x360</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_I2S0</name>
+          <addressOffset>0x364</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S0_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_UART1</name>
+          <addressOffset>0x368</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UART1_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_BT</name>
+          <addressOffset>0x36C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_BT_BUFFER</name>
+          <addressOffset>0x370</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BTBUFFER_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_I2C_EXT0</name>
+          <addressOffset>0x374</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2CEXT0_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_UHCI0</name>
+          <addressOffset>0x378</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UHCI0_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_SLCHOST</name>
+          <addressOffset>0x37C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_RMT</name>
+          <addressOffset>0x380</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RMT_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_PCNT</name>
+          <addressOffset>0x384</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PCNT_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_SLC</name>
+          <addressOffset>0x388</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_LEDC</name>
+          <addressOffset>0x38C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LEDC_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_EFUSE</name>
+          <addressOffset>0x390</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EFUSE_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_SPI_ENCRYPT</name>
+          <addressOffset>0x394</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_ENCRYPY_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_BB</name>
+          <addressOffset>0x398</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BB_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_PWM0</name>
+          <addressOffset>0x39C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PWM0_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_TIMERGROUP</name>
+          <addressOffset>0x3A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMERGROUP_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_TIMERGROUP1</name>
+          <addressOffset>0x3A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMERGROUP1_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_SPI2</name>
+          <addressOffset>0x3A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI2_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_SPI3</name>
+          <addressOffset>0x3AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI3_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_APB_CTRL</name>
+          <addressOffset>0x3B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APBCTRL_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_I2C_EXT1</name>
+          <addressOffset>0x3B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2CEXT1_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_SDIO_HOST</name>
+          <addressOffset>0x3B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIOHOST_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_EMAC</name>
+          <addressOffset>0x3BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EMAC_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_CAN</name>
+          <addressOffset>0x3C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAN_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_PWM1</name>
+          <addressOffset>0x3C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PWM1_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_I2S1</name>
+          <addressOffset>0x3C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S1_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_UART2</name>
+          <addressOffset>0x3CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UART2_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_PWM2</name>
+          <addressOffset>0x3D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PWM2_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_PWM3</name>
+          <addressOffset>0x3D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PWM3_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_RWBT</name>
+          <addressOffset>0x3D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RWBT_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_BTMAC</name>
+          <addressOffset>0x3DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BTMAC_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_WIFIMAC</name>
+          <addressOffset>0x3E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFIMAC_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHBLITE_MPU_TABLE_PWR</name>
+          <addressOffset>0x3E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PWR_ACCESS_GRANT_CONFIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_ACCESS_DBUG0</name>
+          <addressOffset>0x3E8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ROM_MPU_AD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_ROM_IA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_ROM_MPU_AD</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_ROM_IA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SHARE_ROM_MPU_AD</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SHARE_ROM_IA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_MMU_AD</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_IA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_MMU_MULTI_HIT</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_ACCESS_DBUG1</name>
+          <addressOffset>0x3EC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_MMU_MISS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_IA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIDGEN_IA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AHB_ACCESS_DENY</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AHBLITE_ACCESS_DENY</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AHBLITE_IA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG0</name>
+          <addressOffset>0x3F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_SLAVE_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MMU_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_IA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_STATE</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_WR_BAK_TO_READ</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_TX_END</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_SLAVE_WR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_SLAVE_WDATA_V</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_RX_END</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG1</name>
+          <addressOffset>0x3F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CTAG_RAM_RDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG2</name>
+          <addressOffset>0x3F8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_VADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG3</name>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_MMU_RDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_CPU_DISABLED_CACHE_IA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_CPU_DISABLED_CACHE_IA_OPPOSITE</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CPU_DISABLED_CACHE_IA_DRAM1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CPU_DISABLED_CACHE_IA_IROM0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CPU_DISABLED_CACHE_IA_IRAM1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CPU_DISABLED_CACHE_IA_IRAM0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CPU_DISABLED_CACHE_IA_DROM0</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_IRAM0_PID_ERROR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG4</name>
+          <addressOffset>0x400</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DRAM1ADDR0_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG5</name>
+          <addressOffset>0x404</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DROM0ADDR0_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG6</name>
+          <addressOffset>0x408</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_IRAM0ADDR_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG7</name>
+          <addressOffset>0x40C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_IRAM1ADDR_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG8</name>
+          <addressOffset>0x410</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_IROM0ADDR_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_DBUG9</name>
+          <addressOffset>0x414</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_OPSDRAMADDR_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG0</name>
+          <addressOffset>0x418</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_SLAVE_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_MMU_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CACHE_IA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CACHE_STATE</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_WR_BAK_TO_READ</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_TX_END</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_SLAVE_WR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_SLAVE_WDATA_V</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_RX_END</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG1</name>
+          <addressOffset>0x41C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_CTAG_RAM_RDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG2</name>
+          <addressOffset>0x420</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_CACHE_VADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG3</name>
+          <addressOffset>0x424</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_MMU_RDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CPU_DISABLED_CACHE_IA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CPU_DISABLED_CACHE_IA_OPPOSITE</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CPU_DISABLED_CACHE_IA_DRAM1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CPU_DISABLED_CACHE_IA_IROM0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CPU_DISABLED_CACHE_IA_IRAM1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CPU_DISABLED_CACHE_IA_IRAM0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CPU_DISABLED_CACHE_IA_DROM0</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CACHE_IRAM0_PID_ERROR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG4</name>
+          <addressOffset>0x428</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_DRAM1ADDR0_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG5</name>
+          <addressOffset>0x42C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_DROM0ADDR0_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG6</name>
+          <addressOffset>0x430</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_IRAM0ADDR_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG7</name>
+          <addressOffset>0x434</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_IRAM1ADDR_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG8</name>
+          <addressOffset>0x438</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_IROM0ADDR_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_DCACHE_DBUG9</name>
+          <addressOffset>0x43C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_OPSDRAMADDR_IA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_CTRL</name>
+          <addressOffset>0x440</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_RECORD_ENABLE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CPU_RECORD_DISABLE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CPU_PDEBUG_ENABLE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_STATUS</name>
+          <addressOffset>0x444</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CPU_RECORDING</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_PID</name>
+          <addressOffset>0x448</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_PRO_PID</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_PDEBUGINST</name>
+          <addressOffset>0x44C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_PRO_PDEBUGINST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGINST_SZ</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGINST_ISRC</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGINST_LOOP_REP</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGINST_LOOP</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGINST_CINTL</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_PDEBUGSTATUS</name>
+          <addressOffset>0x450</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_PRO_PDEBUGSTATUS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGSTATUS_BBCAUSE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGSTATUS_INSNTYPE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_PDEBUGDATA</name>
+          <addressOffset>0x454</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_PRO_PDEBUGDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_DEP_OTHER</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_EXCVEC</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_INSNTYPE_SR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_INSNTYPE_RER</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_BUFF</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_INSNTYPE_WER</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_BUFFCONFL</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_INSNTYPE_ER</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_DCM</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_LSU</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_ICM</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_IRAMBUSY</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_DEP_LSU</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_IPIF</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_INSNTYPE_RSR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_TIE</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_INSNTYPE_WSR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_RUN</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_INSNTYPE_XSR</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_DEP_STR</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_DEP</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_BPIFETCH</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_L32R</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_LSPROC</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_BPLOAD</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_DEP_MEMW</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_EXCCAUSE</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_BANKCONFL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_DEP_HALT</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_ITERMUL</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGDATA_STALL_ITERDIV</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_PDEBUGPC</name>
+          <addressOffset>0x458</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_PRO_PDEBUGPC</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_PDEBUGLS0STAT</name>
+          <addressOffset>0x45C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_PRO_PDEBUGLS0STAT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_TYPE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_SZ</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_DTLBM</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_DCM</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_DCH</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_UC</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_WB</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_COH</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_STCOH</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_PDEBUGLS0STAT_TGT</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_PDEBUGLS0ADDR</name>
+          <addressOffset>0x460</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_PRO_PDEBUGLS0ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_RECORD_PDEBUGLS0DATA</name>
+          <addressOffset>0x464</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_PRO_PDEBUGLS0DATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_CTRL</name>
+          <addressOffset>0x468</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>APP_CPU_RECORD_ENABLE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CPU_RECORD_DISABLE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CPU_PDEBUG_ENABLE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_STATUS</name>
+          <addressOffset>0x46C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_CPU_RECORDING</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_PID</name>
+          <addressOffset>0x470</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_APP_PID</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_PDEBUGINST</name>
+          <addressOffset>0x474</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_APP_PDEBUGINST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_PDEBUGSTATUS</name>
+          <addressOffset>0x478</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_APP_PDEBUGSTATUS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_PDEBUGDATA</name>
+          <addressOffset>0x47C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_APP_PDEBUGDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_PDEBUGPC</name>
+          <addressOffset>0x480</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_APP_PDEBUGPC</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_PDEBUGLS0STAT</name>
+          <addressOffset>0x484</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_APP_PDEBUGLS0STAT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_PDEBUGLS0ADDR</name>
+          <addressOffset>0x488</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_APP_PDEBUGLS0ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_CPU_RECORD_PDEBUGLS0DATA</name>
+          <addressOffset>0x48C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_APP_PDEBUGLS0DATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_PD_CTRL</name>
+          <addressOffset>0x490</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RSA_PD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_MPU_TABLE0</name>
+          <addressOffset>0x494</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ROM_MPU_TABLE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_MPU_TABLE1</name>
+          <addressOffset>0x498</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ROM_MPU_TABLE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_MPU_TABLE2</name>
+          <addressOffset>0x49C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ROM_MPU_TABLE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_MPU_TABLE3</name>
+          <addressOffset>0x4A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ROM_MPU_TABLE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE0</name>
+          <addressOffset>0x4A4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE1</name>
+          <addressOffset>0x4A8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE2</name>
+          <addressOffset>0x4AC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE3</name>
+          <addressOffset>0x4B0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE4</name>
+          <addressOffset>0x4B4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE5</name>
+          <addressOffset>0x4B8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE6</name>
+          <addressOffset>0x4BC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE7</name>
+          <addressOffset>0x4C0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE8</name>
+          <addressOffset>0x4C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE8</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE9</name>
+          <addressOffset>0x4C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE9</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE10</name>
+          <addressOffset>0x4CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE10</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE11</name>
+          <addressOffset>0x4D0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE11</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE12</name>
+          <addressOffset>0x4D4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE12</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE13</name>
+          <addressOffset>0x4D8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE13</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE14</name>
+          <addressOffset>0x4DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE14</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE15</name>
+          <addressOffset>0x4E0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE15</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE16</name>
+          <addressOffset>0x4E4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE16</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE17</name>
+          <addressOffset>0x4E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE17</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE18</name>
+          <addressOffset>0x4EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE18</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE19</name>
+          <addressOffset>0x4F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE19</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE20</name>
+          <addressOffset>0x4F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE20</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE21</name>
+          <addressOffset>0x4F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE21</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE22</name>
+          <addressOffset>0x4FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE22</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHROM_MPU_TABLE23</name>
+          <addressOffset>0x500</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHROM_MPU_TABLE23</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE0</name>
+          <addressOffset>0x504</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IMMU_TABLE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE1</name>
+          <addressOffset>0x508</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE2</name>
+          <addressOffset>0x50C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE3</name>
+          <addressOffset>0x510</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE4</name>
+          <addressOffset>0x514</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE5</name>
+          <addressOffset>0x518</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE6</name>
+          <addressOffset>0x51C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000006</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE7</name>
+          <addressOffset>0x520</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE8</name>
+          <addressOffset>0x524</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE8</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE9</name>
+          <addressOffset>0x528</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE9</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE10</name>
+          <addressOffset>0x52C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE10</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE11</name>
+          <addressOffset>0x530</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE11</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE12</name>
+          <addressOffset>0x534</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000C</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE12</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE13</name>
+          <addressOffset>0x538</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE13</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE14</name>
+          <addressOffset>0x53C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000E</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE14</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMMU_TABLE15</name>
+          <addressOffset>0x540</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>IMMU_TABLE15</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE0</name>
+          <addressOffset>0x544</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMMU_TABLE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE1</name>
+          <addressOffset>0x548</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE2</name>
+          <addressOffset>0x54C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE3</name>
+          <addressOffset>0x550</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE4</name>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE5</name>
+          <addressOffset>0x558</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE6</name>
+          <addressOffset>0x55C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000006</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE7</name>
+          <addressOffset>0x560</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE8</name>
+          <addressOffset>0x564</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE8</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE9</name>
+          <addressOffset>0x568</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000009</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE9</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE10</name>
+          <addressOffset>0x56C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE10</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE11</name>
+          <addressOffset>0x570</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE11</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE12</name>
+          <addressOffset>0x574</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000C</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE12</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE13</name>
+          <addressOffset>0x578</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE13</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE14</name>
+          <addressOffset>0x57C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000E</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE14</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMMU_TABLE15</name>
+          <addressOffset>0x580</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>DMMU_TABLE15</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTRUSION_CTRL</name>
+          <addressOffset>0x584</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PRO_INTRUSION_RECORD_RESET_N</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTRUSION_STATUS</name>
+          <addressOffset>0x588</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_INTRUSION_RECORD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INTRUSION_CTRL</name>
+          <addressOffset>0x58C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>APP_INTRUSION_RECORD_RESET_N</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INTRUSION_STATUS</name>
+          <addressOffset>0x590</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_INTRUSION_RECORD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRONT_END_MEM_PD</name>
+          <addressOffset>0x594</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>AGC_MEM_FORCE_PU</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AGC_MEM_FORCE_PD</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBUS_MEM_FORCE_PU</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBUS_MEM_FORCE_PD</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MMU_IA_INT_EN</name>
+          <addressOffset>0x598</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MMU_IA_INT_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MPU_IA_INT_EN</name>
+          <addressOffset>0x59C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MPU_IA_INT_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_IA_INT_EN</name>
+          <addressOffset>0x5A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_IA_INT_EN</name>
+              <description>Interrupt enable bits for various invalid cache access reasons</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_APP_DROM0</name>
+              <description>APP CPU invalid access to DROM0 when cache is disabled </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_APP_IRAM0</name>
+              <description>APP CPU invalid access to IRAM0 when cache is disabled </description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_APP_IRAM1</name>
+              <description>APP CPU invalid access to IRAM1 when cache is disabled </description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_APP_IROM0</name>
+              <description>APP CPU invalid access to IROM0 when cache is disabled </description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_APP_DRAM1</name>
+              <description>APP CPU invalid access to DRAM1 when cache is disabled </description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_APP_OPPOSITE</name>
+              <description>APP CPU invalid access to APP CPU cache when cache disabled </description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_PRO_DROM0</name>
+              <description>PRO CPU invalid access to DROM0 when cache is disabled </description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_PRO_IRAM0</name>
+              <description>PRO CPU invalid access to IRAM0 when cache is disabled </description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_PRO_IRAM1</name>
+              <description>PRO CPU invalid access to IRAM1 when cache is disabled </description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_PRO_IROM0</name>
+              <description>PRO CPU invalid access to IROM0 when cache is disabled </description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_PRO_DRAM1</name>
+              <description>PRO CPU invalid access to DRAM1 when cache is disabled </description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IA_INT_PRO_OPPOSITE</name>
+              <description>PRO CPU invalid access to APP CPU cache when cache disabled </description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SECURE_BOOT_CTRL</name>
+          <addressOffset>0x5A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_BOOTLOADER_SEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_CHAN_SEL</name>
+          <addressOffset>0x5A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI1_DMA_CHAN_SEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_DMA_CHAN_SEL</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_DMA_CHAN_SEL</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_VECBASE_CTRL</name>
+          <addressOffset>0x5AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_OUT_VECBASE_SEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_VECBASE_SET</name>
+          <addressOffset>0x5B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_OUT_VECBASE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_VECBASE_CTRL</name>
+          <addressOffset>0x5B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_OUT_VECBASE_SEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_VECBASE_SET</name>
+          <addressOffset>0x5B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_OUT_VECBASE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01605190</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EFUSE</name>
+      <description>eFuse Controller</description>
+      <groupName>EFUSE</groupName>
+      <baseAddress>0x3FF5A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x124</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EFUSE</name>
+        <value>44</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BLK0_RDATA0</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_EFUSE_WR_DIS</name>
+              <description>read for efuse_wr_disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_EFUSE_RD_DIS</name>
+              <description>read for efuse_rd_disable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_FLASH_CRYPT_CNT</name>
+              <description>read for flash_crypt_cnt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_RDATA1</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_WIFI_MAC_CRC_LOW</name>
+              <description>read for low 32bit WIFI_MAC_Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_RDATA2</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_WIFI_MAC_CRC_HIGH</name>
+              <description>read for high 24bit WIFI_MAC_Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_RDATA3</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_CHIP_VER_DIS_APP_CPU</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_CHIP_VER_DIS_BT</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_CHIP_VER_PKG_4BIT</name>
+              <description>most significant bit of chip package </description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_CHIP_VER_DIS_CACHE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_SPI_PAD_CONFIG_HD</name>
+              <description>read for SPI_pad_config_hd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_CHIP_VER_PKG</name>
+              <description>least significant bits of chip package </description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_CHIP_CPU_FREQ_LOW</name>
+              <description>If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_CHIP_CPU_FREQ_RATED</name>
+              <description>If set, the ESP32's maximum CPU frequency has been rated</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_BLK3_PART_RESERVE</name>
+              <description>If set, this bit indicates that BLOCK3[143:96] is reserved for internal use</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_CHIP_VER_REV1</name>
+              <description>bit is set to 1 for rev1 silicon</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_RDATA4</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_CK8M_FREQ</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_ADC_VREF</name>
+              <description>True ADC reference voltage </description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_SDIO_DREFH</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_SDIO_DREFM</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_SDIO_DREFL</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_XPD_SDIO</name>
+              <description>read for XPD_SDIO_REG</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_SDIO_TIEH</name>
+              <description>read for SDIO_TIEH</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_SDIO_FORCE</name>
+              <description>read for sdio_force</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_RDATA5</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_SPI_PAD_CONFIG_CLK</name>
+              <description>read for SPI_pad_config_clk</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_SPI_PAD_CONFIG_Q</name>
+              <description>read for SPI_pad_config_q</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_SPI_PAD_CONFIG_D</name>
+              <description>read for SPI_pad_config_d</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_SPI_PAD_CONFIG_CS0</name>
+              <description>read for SPI_pad_config_cs0</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_CHIP_VER_REV2</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_VOL_LEVEL_HP_INV</name>
+              <description>This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_WAFER_VERSION_MINOR</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_FLASH_CRYPT_CONFIG</name>
+              <description>read for flash_crypt_config</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_RDATA6</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_CODING_SCHEME</name>
+              <description>read for coding_scheme</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_CONSOLE_DEBUG_DISABLE</name>
+              <description>read for console_debug_disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_DISABLE_SDIO_HOST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_ABS_DONE_0</name>
+              <description>read for abstract_done_0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_ABS_DONE_1</name>
+              <description>read for abstract_done_1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_DISABLE_JTAG</name>
+              <description>read for JTAG_disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_DISABLE_DL_ENCRYPT</name>
+              <description>read for download_dis_encrypt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_DISABLE_DL_DECRYPT</name>
+              <description>read for download_dis_decrypt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_DISABLE_DL_CACHE</name>
+              <description>read for download_dis_cache</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_KEY_STATUS</name>
+              <description>read for key_status</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_WDATA0</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_DIS</name>
+              <description>program for efuse_wr_disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_DIS</name>
+              <description>program for efuse_rd_disable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_CRYPT_CNT</name>
+              <description>program for flash_crypt_cnt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_WDATA1</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_MAC_CRC_LOW</name>
+              <description>program for low 32bit WIFI_MAC_Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_WDATA2</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_MAC_CRC_HIGH</name>
+              <description>program for high 24bit WIFI_MAC_Address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_WDATA3</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHIP_VER_DIS_APP_CPU</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIP_VER_DIS_BT</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIP_VER_PKG_4BIT</name>
+              <description>most significant bit of chip package </description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CHIP_VER_DIS_CACHE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_PAD_CONFIG_HD</name>
+              <description>program for SPI_pad_config_hd</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIP_VER_PKG</name>
+              <description>least significant bits of chip package </description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIP_CPU_FREQ_LOW</name>
+              <description>If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIP_CPU_FREQ_RATED</name>
+              <description>If set, the ESP32's maximum CPU frequency has been rated</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BLK3_PART_RESERVE</name>
+              <description>If set, this bit indicates that BLOCK3[143:96] is reserved for internal use</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIP_VER_REV1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_WDATA4</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CK8M_FREQ</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_VREF</name>
+              <description>True ADC reference voltage </description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DREFH</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DREFM</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DREFL</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SDIO</name>
+              <description>program for XPD_SDIO_REG</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_TIEH</name>
+              <description>program for SDIO_TIEH</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_FORCE</name>
+              <description>program for sdio_force</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_WDATA5</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_PAD_CONFIG_CLK</name>
+              <description>program for SPI_pad_config_clk</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_PAD_CONFIG_Q</name>
+              <description>program for SPI_pad_config_q</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_PAD_CONFIG_D</name>
+              <description>program for SPI_pad_config_d</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_PAD_CONFIG_CS0</name>
+              <description>program for SPI_pad_config_cs0</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INST_CONFIG</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VOL_LEVEL_HP_INV</name>
+              <description>This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_VOL_L6</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_CRYPT_CONFIG</name>
+              <description>program for flash_crypt_config</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_WDATA6</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CODING_SCHEME</name>
+              <description>program for coding_scheme</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONSOLE_DEBUG_DISABLE</name>
+              <description>program for console_debug_disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISABLE_SDIO_HOST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ABS_DONE_0</name>
+              <description>program for abstract_done_0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ABS_DONE_1</name>
+              <description>program for abstract_done_1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISABLE_JTAG</name>
+              <description>program for JTAG_disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISABLE_DL_ENCRYPT</name>
+              <description>program for download_dis_encrypt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISABLE_DL_DECRYPT</name>
+              <description>program for download_dis_decrypt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISABLE_DL_CACHE</name>
+              <description>program for download_dis_cache</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>KEY_STATUS</name>
+              <description>program for key_status</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_RDATA0</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DOUT0</name>
+              <description>read for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_RDATA1</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DOUT1</name>
+              <description>read for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_RDATA2</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DOUT2</name>
+              <description>read for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_RDATA3</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DOUT3</name>
+              <description>read for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_RDATA4</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DOUT4</name>
+              <description>read for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_RDATA5</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DOUT5</name>
+              <description>read for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_RDATA6</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DOUT6</name>
+              <description>read for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_RDATA7</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DOUT7</name>
+              <description>read for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_RDATA0</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DOUT0</name>
+              <description>read for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_RDATA1</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DOUT1</name>
+              <description>read for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_RDATA2</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DOUT2</name>
+              <description>read for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_RDATA3</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DOUT3</name>
+              <description>read for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_RDATA4</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DOUT4</name>
+              <description>read for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_RDATA5</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DOUT5</name>
+              <description>read for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_RDATA6</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DOUT6</name>
+              <description>read for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_RDATA7</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DOUT7</name>
+              <description>read for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_RDATA0</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DOUT0</name>
+              <description>read for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_RDATA1</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DOUT1</name>
+              <description>read for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_RDATA2</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DOUT2</name>
+              <description>read for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_RDATA3</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DOUT3</name>
+              <description>read for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_ADC1_TP_LOW</name>
+              <description>ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_ADC1_TP_HIGH</name>
+              <description>ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE </description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_ADC2_TP_LOW</name>
+              <description>ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE </description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_ADC2_TP_HIGH</name>
+              <description>ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE </description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_RDATA4</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DOUT4</name>
+              <description>read for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RD_CAL_RESERVED</name>
+              <description>Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_RDATA5</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DOUT5</name>
+              <description>read for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_RDATA6</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DOUT6</name>
+              <description>read for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_RDATA7</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DOUT7</name>
+              <description>read for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_WDATA0</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DIN0</name>
+              <description>program for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_WDATA1</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DIN1</name>
+              <description>program for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_WDATA2</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DIN2</name>
+              <description>program for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_WDATA3</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DIN3</name>
+              <description>program for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_WDATA4</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DIN4</name>
+              <description>program for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_WDATA5</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DIN5</name>
+              <description>program for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_WDATA6</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DIN6</name>
+              <description>program for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_WDATA7</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_DIN7</name>
+              <description>program for BLOCK1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_WDATA0</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DIN0</name>
+              <description>program for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_WDATA1</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DIN1</name>
+              <description>program for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_WDATA2</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DIN2</name>
+              <description>program for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_WDATA3</name>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DIN3</name>
+              <description>program for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_WDATA4</name>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DIN4</name>
+              <description>program for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_WDATA5</name>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DIN5</name>
+              <description>program for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_WDATA6</name>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DIN6</name>
+              <description>program for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_WDATA7</name>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DIN7</name>
+              <description>program for BLOCK2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_WDATA0</name>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DIN0</name>
+              <description>program for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_WDATA1</name>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DIN1</name>
+              <description>program for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_WDATA2</name>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DIN2</name>
+              <description>program for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_WDATA3</name>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DIN3</name>
+              <description>program for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_TP_LOW</name>
+              <description>ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_TP_HIGH</name>
+              <description>ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE </description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_TP_LOW</name>
+              <description>ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE </description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_TP_HIGH</name>
+              <description>ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE </description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_WDATA4</name>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DIN4</name>
+              <description>program for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAL_RESERVED</name>
+              <description>Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_WDATA5</name>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DIN5</name>
+              <description>program for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_WDATA6</name>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DIN6</name>
+              <description>program for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_WDATA7</name>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DIN7</name>
+              <description>program for BLOCK3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004052</resetValue>
+          <fields>
+            <field>
+              <name>SEL0</name>
+              <description>efuse timing configure</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL1</name>
+              <description>efuse timing configure</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>OP_CODE</name>
+              <description>efuse operation code</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_NO_WR_RD_DIS</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DEBUG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_CMD</name>
+              <description>command for read</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_CMD</name>
+              <description>command for program</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_RAW</name>
+              <description>read done interrupt raw status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_RAW</name>
+              <description>program done interrupt raw status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ST</name>
+              <description>read done interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ST</name>
+              <description>program done interrupt status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ENA</name>
+              <description>read done interrupt enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ENA</name>
+              <description>program done interrupt enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_CLR</name>
+              <description>read done interrupt clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_CLR</name>
+              <description>program done interrupt clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAC_CONF</name>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000028</resetValue>
+          <fields>
+            <field>
+              <name>DAC_CLK_DIV</name>
+              <description>efuse timing configure</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_PAD_SEL</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEC_STATUS</name>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DEC_WARNINGS</name>
+              <description>the decode result of 3/4 coding scheme has warning</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x16042600</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>FLASH_ENCRYPTION</name>
+      <description>Flash Encryption Peripheral</description>
+      <groupName>FLASH_ENCRYPTION</groupName>
+      <baseAddress>0x3FF46000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x2C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>BUFFER_%s</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUFFER</name>
+              <description>Data buffers for encryption.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>START</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FLASH_START</name>
+              <description>Set this bit to start encryption operation on data buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDRESS</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADDRESS</name>
+              <description>The physical address on the off-chip flash must be 8-word boundary aligned.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DONE</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FLASH_DONE</name>
+              <description>Set this bit when encryption operation is complete.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>FRC_TIMER</name>
+      <description>Peripheral FRC_TIMER</description>
+      <groupName>FRC</groupName>
+      <baseAddress>0x3FF47000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x14</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>TIMER_LOAD</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>VALUE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_COUNT</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COUNT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_CTRL</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_PRESCALER</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_INT</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_ALARM</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_ALARM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <baseAddress>0x3FF44000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x5CC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>GPIO</name>
+        <value>22</value>
+      </interrupt>
+      <interrupt>
+        <name>GPIO_NMI</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BT_SELECT</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_SEL</name>
+              <description>NA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO0~31 output value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TS</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DATA_W1TS</name>
+              <description>GPIO0~31 output value write 1 to set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TC</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DATA_W1TC</name>
+              <description>GPIO0~31 output value write 1 to clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO32~39 output value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1_W1TS</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT1_DATA_W1TS</name>
+              <description>GPIO32~39 output value write 1 to set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1_W1TC</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT1_DATA_W1TC</name>
+              <description>GPIO32~39 output value write 1 to clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SELECT</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_SEL</name>
+              <description>SDIO PADS on/off control from outside</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO0~31 output enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TS</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_DATA_W1TS</name>
+              <description>GPIO0~31 output enable write 1 to set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_DATA_W1TC</name>
+              <description>GPIO0~31 output enable write 1 to clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO32~39 output enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1_W1TS</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE1_DATA_W1TS</name>
+              <description>GPIO32~39 output enable write 1 to set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1_W1TC</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE1_DATA_W1TC</name>
+              <description>GPIO32~39 output enable write 1 to clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STRAP</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRAPPING</name>
+              <description>{10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO0~31 input value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN1</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO32~39 input value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT</name>
+              <description>GPIO0~31 interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TS</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INT_W1TS</name>
+              <description>GPIO0~31 interrupt status write 1 to set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TC</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INT_W1TC</name>
+              <description>GPIO0~31 interrupt status write 1 to clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT</name>
+              <description>GPIO32~39 interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1_W1TS</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS1_INT_W1TS</name>
+              <description>GPIO32~39 interrupt status write 1 to set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1_W1TC</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS1_INT_W1TC</name>
+              <description>GPIO32~39 interrupt status write 1 to clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACPU_INT</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APPCPU_INT</name>
+              <description>GPIO0~31 APP CPU interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACPU_NMI_INT</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APPCPU_NMI_INT</name>
+              <description>GPIO0~31 APP CPU non-maskable interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT</name>
+              <description>GPIO0~31 PRO CPU interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT</name>
+              <description>GPIO0~31 PRO CPU non-maskable interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT</name>
+              <description>SDIO's extent GPIO0~31 interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACPU_INT1</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APPCPU_INT_H</name>
+              <description>GPIO32~39 APP CPU interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACPU_NMI_INT1</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APPCPU_NMI_INT_H</name>
+              <description>GPIO32~39 APP CPU non-maskable interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT1</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT_H</name>
+              <description>GPIO32~39 PRO CPU interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT1</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT_H</name>
+              <description>GPIO32~39 PRO CPU non-maskable interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT1</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT_H</name>
+              <description>SDIO's extent GPIO32~39 interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIN_PAD_DRIVER</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PIN_INT_TYPE</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PIN_WAKEUP_ENABLE</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PIN_CONFIG</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PIN_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>40</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-39</dimIndex>
+          <name>PIN%s</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>if set to 0: normal output  if set to 1: open drain</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TYPE</name>
+              <description>if set to 0: GPIO interrupt disable  if set to 1: rising edge trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENABLE</name>
+              <description>GPIO wake up enable  only available in light sleep</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONFIG</name>
+              <description>NA</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_ENA</name>
+              <description>bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>cali_conf</name>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALI_RTC_MAX</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CALI_START</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>cali_data</name>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALI_VALUE_SYNC2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CALI_RDY_REAL</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CALI_RDY_SYNC2</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>256</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-255</dimIndex>
+          <name>FUNC%s_IN_SEL_CFG</name>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>select one of the 256 inputs</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>revert the value of the input if you want to revert  please set the value to 1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>if the slow signal bypass the io matrix or not if you want  setting the value to 1</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>40</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-39</dimIndex>
+          <name>FUNC%s_OUT_SEL_CFG</name>
+          <addressOffset>0x530</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_SEL</name>
+              <description>select one of the 256 output to 40 GPIO</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INV_SEL</name>
+              <description>invert the output value  if you want to revert the output value  setting the value to 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_SEL</name>
+              <description>weather using the logical oen signal or not using the value setting by the register</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_INV_SEL</name>
+              <description>invert the output enable value  if you want to revert the output enable value  setting the value to 1</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO_SD</name>
+      <description>Sigma-Delta Modulation</description>
+      <groupName>GPIO_SIGMADELTA</groupName>
+      <baseAddress>0x3FF44F00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x2C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SIGMADELTA0</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD0_IN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD0_PRESCALE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA1</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD1_IN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD1_PRESCALE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA2</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD2_IN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD2_PRESCALE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA3</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD3_IN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD3_PRESCALE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA4</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD4_IN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD4_PRESCALE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA5</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD5_IN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD5_PRESCALE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA6</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD6_IN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD6_PRESCALE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA7</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD7_IN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD7_PRESCALE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CG</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SD_CLK_EN</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SWAP</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VERSION</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01506190</resetValue>
+          <fields>
+            <field>
+              <name>SD_DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HINF</name>
+      <description>Peripheral HINF</description>
+      <groupName>HINF</groupName>
+      <baseAddress>0x3FF4B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x34</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CFG_DATA0</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x22226666</resetValue>
+          <fields>
+            <field>
+              <name>USER_ID_FN1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEVICE_ID_FN1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG_DATA1</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01110011</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_ENABLE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IOREADY1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HIGHSPEED_ENABLE</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HIGHSPEED_MODE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_CD_ENABLE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IOREADY2</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_INT_MASK</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IOENABLE2</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CD_DISABLE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FUNC1_EPS</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EMP</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IOENABLE1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO20_CONF0</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_VER</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC2_EPS</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO20_CONF1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG_DATA7</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00020000</resetValue>
+          <fields>
+            <field>
+              <name>PIN_STATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIP_STATE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_RST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IOREADY0</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF0</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF1</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF2</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF3</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF4</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF5</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF6</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF7</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG_DATA16</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x33336666</resetValue>
+          <fields>
+            <field>
+              <name>USER_ID_FN2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEVICE_ID_FN2</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x15030200</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2C0</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x3FF53000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x9C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C_EXT0</name>
+        <value>49</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SCL_LOW_PERIOD</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_LOW_PERIOD</name>
+              <description>This register is used to configure the  low level width of SCL clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTR</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>1: normally ouput sda data   0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>1: normally ouput scl clock  0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal  scl_oe is the enable bit for the internal output scl signal)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAMPLE_SCL_LEVEL</name>
+              <description>Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>Set this bit to configure the module as i2c master  clear this bit to configure the module as i2c slave.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>Set this bit to start sending data in txfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>This bit is used to control the sending mode for  data need to be send. 1: receive data from most significant bit    0: receive data from least significant bit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>This bit is used to control the storage mode for received datas. 1: receive data from most significant bit    0: receive data from least significant bit</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>This is the clock gating control bit for reading or writing registers.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ACK_REC</name>
+              <description>This register stores the value of ACK bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW</name>
+              <description>when in slave mode  1: master read slave  0: master write slave.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT</name>
+              <description>when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>when I2C lost control of SDA line  this register changes to high level.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>1:I2C bus is busy transferring data. 0:I2C bus is in idle state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDRESSED</name>
+              <description>when configured as i2c slave  and the address send by master is equal to slave's address  then this bit will be high level.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS</name>
+              <description>This register changes to high level when one byte is transferred.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>This register represent the amount of data need to send.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>This register stores the amount of received data  in ram.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_STATE_LAST</name>
+              <description>This register stores the value of state machine for i2c module.  3'h0: SCL_MAIN_IDLE  3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS  3'h3: SCL_RX_DATA  3'h4 SCL_TX_DATA  3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_STATE_LAST</name>
+              <description>This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE  3'h1:SCL_START   3'h2:SCL_LOW_EDGE  3'h3: SCL_LOW   3'h4:SCL_HIGH_EDGE   3'h5:SCL_HIGH  3'h6:SCL_STOP</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TO</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_OUT</name>
+              <description>This register is used to configure the max clock number of receiving  a data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_ADDR</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_ADDR</name>
+              <description>when configured as i2c slave  this register is used to configure slave's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_EN</name>
+              <description>This register is used to enable slave 10bit address mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXFIFO_ST</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_START_ADDR</name>
+              <description>This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_END_ADDR</name>
+              <description>This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_START_ADDR</name>
+              <description>This is the offset address of the first  sending data as described in nonfifo_tx_thres register.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_END_ADDR</name>
+              <description>This is the offset address of the last  sending data as described in nonfifo_tx_thres register.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_CONF</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0155408B</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_THRHD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_THRHD</name>
+              <description>Config txfifo empty threhd value when using apb fifo access</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_EN</name>
+              <description>Set this bit to enble apb nonfifo access.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_ADDR_CFG_EN</name>
+              <description>When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RST</name>
+              <description>Set this bit to reset rx fifo when using apb fifo access.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RST</name>
+              <description>Set this bit to reset tx fifo when using apb fifo access.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_RX_THRES</name>
+              <description>when I2C receives more than nonfifo_rx_thres data  it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_TX_THRES</name>
+              <description>when I2C sends more than nonfifo_tx_thres data  it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_RDATA</name>
+              <description>The register represent the byte  data read from rxfifo when use apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_RAW</name>
+              <description>The raw interrupt status bit for rxfifo full when use apb fifo access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_RAW</name>
+              <description>The raw interrupt status bit for txfifo empty when use apb fifo access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt status bit for receiving data overflow when use apb fifo access.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_RAW</name>
+              <description>The raw interrupt status bit for end_detect_int interrupt. when I2C deals with  the END command  it will produce end_detect_int interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_RAW</name>
+              <description>The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detectsthe STOP bit  it will produce slave_tran_comp_int interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_RAW</name>
+              <description>The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command  it will produce trans_complete_int interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data  it will produce  time_out_int interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_RAW</name>
+              <description>The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_RAW</name>
+              <description>The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit  it will produce ack_err_int interrupt..</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_REC_FULL_INT_RAW</name>
+              <description>The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data  than nonfifo_rx_thres  it will produce rx_rec_full_int interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_SEND_EMPTY_INT_RAW</name>
+              <description>The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres  it will produce tx_send_empty_int interrupt..</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_full_int interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear the txfifo_empty_int interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_ovf_int interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_CLR</name>
+              <description>Set this bit to clear the end_detect_int interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_CLR</name>
+              <description>Set this bit to clear the slave_tran_comp_int interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <description>Set this bit to clear the arbitration_lost_int interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_CLR</name>
+              <description>Set this bit to clear the master_tran_comp interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <description>Set this bit to clear the trans_complete_int interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <description>Set this bit to clear the time_out_int interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_CLR</name>
+              <description>Set this bit to clear the trans_start_int interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_CLR</name>
+              <description>Set this bit to clear the ack_err_int interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_REC_FULL_INT_CLR</name>
+              <description>Set this bit to clear the rx_rec_full_int interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_SEND_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear the tx_send_empty_int interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ENA</name>
+              <description>The enable bit for rxfifo_full_int interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ENA</name>
+              <description>The enable bit for txfifo_empty_int interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>The enable bit for rxfifo_ovf_int interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ENA</name>
+              <description>The enable bit for end_detect_int interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_ENA</name>
+              <description>The enable bit for slave_tran_comp_int interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>The enable bit for arbitration_lost_int interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_ENA</name>
+              <description>The enable bit for master_tran_comp_int interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ENA</name>
+              <description>The enable bit for trans_complete_int interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ENA</name>
+              <description>The enable bit for time_out_int interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ENA</name>
+              <description>The enable bit for trans_start_int interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_ENA</name>
+              <description>The enable bit for ack_err_int interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_REC_FULL_INT_ENA</name>
+              <description>The enable bit for rx_rec_full_int interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SEND_EMPTY_INT_ENA</name>
+              <description>The enable bit for tx_send_empty_int interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ST</name>
+              <description>The masked interrupt status for rxfifo_full_int interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ST</name>
+              <description>The masked interrupt status for txfifo_empty_int interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status for rxfifo_ovf_int interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ST</name>
+              <description>The masked interrupt status for end_detect_int interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_ST</name>
+              <description>The masked interrupt status for slave_tran_comp_int interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>The masked interrupt status for arbitration_lost_int interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_ST</name>
+              <description>The masked interrupt status for master_tran_comp_int interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ST</name>
+              <description>The masked interrupt status for trans_complete_int interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ST</name>
+              <description>The masked interrupt status for time_out_int interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ST</name>
+              <description>The masked interrupt status for trans_start_int interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_ST</name>
+              <description>The masked interrupt status for ack_err_int interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_REC_FULL_INT_ST</name>
+              <description>The masked interrupt status for rx_rec_full_int interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_SEND_EMPTY_INT_ST</name>
+              <description>The masked interrupt status for tx_send_empty_int interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_HOLD</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_SAMPLE</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH_PERIOD</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_HIGH_PERIOD</name>
+              <description>This register is used to configure the clock num during SCL is low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_HOLD</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_RSTART_SETUP</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_HOLD</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the clock num after the STOP bit's posedge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_SETUP</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_FILTER_CFG</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>SCL_FILTER_THRES</name>
+              <description>When input SCL's pulse width is smaller than this register value  I2C ignores this pulse.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FILTER_EN</name>
+              <description>This is the filter enable bit for SCL.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_FILTER_CFG</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>SDA_FILTER_THRES</name>
+              <description>When input SCL's pulse width is smaller than this register value  I2C ignores this pulse.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_EN</name>
+              <description>This is the filter enable bit for SDA.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-15</dimIndex>
+          <name>COMD%s</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND</name>
+              <description>This is the content of command0. It consists of three part. op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND_DONE</name>
+              <description>When command0 is done in I2C Master mode  this bit changes to high level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x16042000</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_START_ADDR</name>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="I2C0">
+      <name>I2C1</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <baseAddress>0x3FF67000</baseAddress>
+      <interrupt>
+        <name>I2C_EXT1</name>
+        <value>50</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>I2S0</name>
+      <description>I2S (Inter-IC Sound) Controller</description>
+      <groupName>I2S</groupName>
+      <baseAddress>0x3FF4F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S0</name>
+        <value>32</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030300</resetValue>
+          <fields>
+            <field>
+              <name>TX_RESET</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RESET</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RESET</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RESET</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_START</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_START</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SLAVE_MOD</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SLAVE_MOD</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_RIGHT_FIRST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RIGHT_FIRST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MSB_SHIFT</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MSB_SHIFT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SHORT_SYNC</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SHORT_SYNC</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MSB_RIGHT</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MSB_RIGHT</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_LOOPBACK</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_TAKE_DATA_INT_RAW</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_PUT_DATA_INT_RAW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_WFULL_INT_RAW</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_REMPTY_INT_RAW</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_WFULL_INT_RAW</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_REMPTY_INT_RAW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_RAW</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_RAW</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_RAW</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_RAW</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_RAW</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_RAW</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_RAW</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_RAW</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_TAKE_DATA_INT_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_PUT_DATA_INT_ST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_WFULL_INT_ST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_REMPTY_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_WFULL_INT_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_REMPTY_INT_ST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ST</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_ST</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_ST</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_ST</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_TAKE_DATA_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PUT_DATA_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WFULL_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_REMPTY_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WFULL_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_REMPTY_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TAKE_DATA_INT_CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PUT_DATA_INT_CLR</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_WFULL_INT_CLR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_REMPTY_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_WFULL_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_REMPTY_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_CLR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_CLR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_CLR</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_CLR</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_CLR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_CLR</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_CLR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_CLR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMING</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BCK_IN_DELAY</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IN_DELAY</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_IN_DELAY</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IN_DELAY</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SD_IN_DELAY</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_OUT_DELAY</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_OUT_DELAY</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SD_OUT_DELAY</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_OUT_DELAY</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_OUT_DELAY</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DSYNC_SW</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DSYNC_SW</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_ENABLE_DELAY</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_IN_INV</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_CONF</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001820</resetValue>
+          <fields>
+            <field>
+              <name>RX_DATA_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DATA_NUM</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSCR_EN</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_MOD</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_MOD</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_MOD_FORCE_EN</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_MOD_FORCE_EN</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXEOF_NUM</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000040</resetValue>
+          <fields>
+            <field>
+              <name>RX_EOF_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_SIGLE_DATA</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SIGLE_DATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_CHAN</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_CHAN_MOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CHAN_MOD</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_LINK</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_LINK</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_DES_ADDR</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EOF_DES_ADDR</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_BFR_DES_ADDR</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_TEST</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHB_TESTMODE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_TESTADDR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR_BF0</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR_BF1</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR_BF0</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR_BF1</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_CONF</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_RST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_FIFO_RST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_RST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_NO_RESTART_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_OWNER</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTFIFO_PUSH</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INFIFO_POP</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_STATE0</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LC_STATE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_STATE1</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LC_STATE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_HUNG_CONF</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000810</resetValue>
+          <fields>
+            <field>
+              <name>LC_FIFO_TIMEOUT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_SHIFT</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CVSD_CONF0</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80007FFF</resetValue>
+          <fields>
+            <field>
+              <name>CVSD_Y_MAX</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CVSD_Y_MIN</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CVSD_CONF1</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A0500</resetValue>
+          <fields>
+            <field>
+              <name>CVSD_SIGMA_MAX</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CVSD_SIGMA_MIN</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CVSD_CONF2</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000502A4</resetValue>
+          <fields>
+            <field>
+              <name>CVSD_K</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CVSD_J</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CVSD_BETA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CVSD_H</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PLC_CONF0</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08A80339</resetValue>
+          <fields>
+            <field>
+              <name>GOOD_PACK_MAX</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>N_ERR_SEG</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SHIFT_RATE</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX_SLIDE_SAMPLE</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PACK_LEN_8K</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>N_MIN_ERR</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PLC_CONF1</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xA0178A05</resetValue>
+          <fields>
+            <field>
+              <name>BAD_CEF_ATTEN_PARA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BAD_CEF_ATTEN_PARA_SHIFT</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BAD_OLA_WIN2_PARA_SHIFT</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BAD_OLA_WIN2_PARA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLIDE_WIN_LEN</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PLC_CONF2</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000028</resetValue>
+          <fields>
+            <field>
+              <name>CVSD_SEG_MOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN_PERIOD</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESCO_CONF0</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ESCO_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESCO_CHAN_MOD</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESCO_CVSD_DEC_PACK_ERR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESCO_CVSD_PACK_LEN_8K</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESCO_CVSD_INF_EN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CVSD_DEC_START</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CVSD_DEC_RESET</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLC_EN</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLC2DMA_EN</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCO_CONF0</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCO_WITH_I2S_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCO_NO_I2S_EN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CVSD_ENC_START</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CVSD_ENC_RESET</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000089</resetValue>
+          <fields>
+            <field>
+              <name>TX_PCM_CONF</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_BYPASS</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_CONF</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_BYPASS</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP_EN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_ZEROS_RM_EN</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_CONF</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>FIFO_FORCE_PD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_FORCE_PU</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLC_MEM_FORCE_PD</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLC_MEM_FORCE_PU</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF2</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAMERA_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_TX_WRX2_EN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_TX_SDX2_EN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_ENABLE_TEST_EN</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_ENABLE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_EN</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_ADC_START_EN</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_VALID_EN</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKM_CONF</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>CLKM_DIV_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_B</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_A</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKA_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPLE_RATE_CONF</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00410186</resetValue>
+          <fields>
+            <field>
+              <name>TX_BCK_DIV_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_DIV_NUM</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BITS_MOD</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BITS_MOD</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDM_CONF</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01550020</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PDM_EN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCM2PDM_CONV_EN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDM2PCM_CONV_EN</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_OSR2</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_PRESCALE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_HP_IN_SHIFT</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_LP_IN_SHIFT</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_IN_SHIFT</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_IN_SHIFT</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PDM_SINC_DSR_16_EN</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_HP_BYPASS</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PDM_FREQ_CONF</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000F01E0</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_FS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_FP</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>TX_IDLE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RESET_BACK</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RESET_BACK</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01604201</resetValue>
+          <fields>
+            <field>
+              <name>I2SDATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="I2S0">
+      <name>I2S1</name>
+      <description>I2S (Inter-IC Sound) Controller</description>
+      <baseAddress>0x3FF6D000</baseAddress>
+      <interrupt>
+        <name>I2S1</name>
+        <value>33</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>IO_MUX</name>
+      <description>Input/Output Multiplexer</description>
+      <groupName>IO_MUX</groupName>
+      <baseAddress>0x3FF49000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x94</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PIN_CTRL</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK1</name>
+              <description>If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK2</name>
+              <description>If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK3</name>
+              <description>If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO36</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO37</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO38</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO39</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO34</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO35</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO32</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO33</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO25</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO26</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO27</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO14</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO12</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO13</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO15</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO2</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO0</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO4</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO16</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO17</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO9</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO10</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO11</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO6</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO7</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO8</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO5</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO18</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO19</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO20</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO21</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO22</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO3</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO1</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO23</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO24</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: enable output; 0: disable output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LEDC</name>
+      <description>LED Control PWM (Pulse Width Modulation)</description>
+      <groupName>LEDC</groupName>
+      <baseAddress>0x3FF59000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x198</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LEDC</name>
+        <value>43</value>
+      </interrupt>
+      <interrupt>
+        <name>TIMER1</name>
+        <value>56</value>
+      </interrupt>
+      <interrupt>
+        <name>TIMER2</name>
+        <value>57</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>HSCH%s_CONF0</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SEL</name>
+              <description>There are four high speed timers  the two bits are used to select one of them for high speed channel0.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_OUT_EN</name>
+              <description>This is the output enable control bit for high speed channel0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_LV</name>
+              <description>This bit is used to control the output value when high speed channel0 is off.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>HSCH%s_HPOINT</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HPOINT</name>
+              <description>The output value changes to high when htimerx(x=[0 3]) selected by high speed channel0 has reached reg_hpoint_hsch0[19:0]</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>HSCH%s_DUTY</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY</name>
+              <description>This register represents the current duty of the output signal for high speed channel0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>HSCH%s_CONF1</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_SCALE</name>
+              <description>This register controls the increase or decrease step scale for high speed channel0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CYCLE</name>
+              <description>This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_NUM</name>
+              <description>This register is used to control the num of increased or decreased times for high speed channel0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_INC</name>
+              <description>This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel0.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_START</name>
+              <description>When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>HSCH%s_DUTY_R</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_R</name>
+              <description>This register represents the current duty cycle of the output signal for high-speed channel %s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>LSCH%s_CONF0</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SEL</name>
+              <description>There are four low speed timers  the two bits are used to select one of them for low speed channel0.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_OUT_EN</name>
+              <description>This is the output enable control bit for low speed channel0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_LV</name>
+              <description>This bit is used to control the output value when low speed channel0 is off.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>LSCH%s_HPOINT</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HPOINT</name>
+              <description>The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel0 has reached reg_hpoint_lsch0[19:0]</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>LSCH%s_DUTY</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <access>read-write</access>
+          <fields>
+            <field>
+              <name>DUTY</name>
+              <description>This register represents the current duty of the output signal for low speed channel0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>LSCH%s_CONF1</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_SCALE</name>
+              <description>This register controls the increase or decrease step scale for low speed channel0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CYCLE</name>
+              <description>This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_NUM</name>
+              <description>This register is used to control the num of increased or decreased times for low speed channel6.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_INC</name>
+              <description>This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_START</name>
+              <description>When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>LSCH%s_DUTY_R</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_R</name>
+              <description>This register represents the current duty cycle of the output signal for low-speed channel %s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0-3</dimIndex>
+          <name>HSTIMER%s_CONF</name>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_RES</name>
+              <description>This register controls the range of the counter in high speed timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIV_NUM</name>
+              <description>This register is used to configure parameter for divider in high speed timer0 the least significant eight bits represent the decimal part.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAUSE</name>
+              <description>This bit is used to pause the counter in high speed timer0</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>This bit is used to reset high speed timer0 the counter will be 0 after reset.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_SEL</name>
+              <description>This bit is used to choose apb_clk or ref_tick for high speed timer0. 1'b1:apb_clk  0:ref_tick</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LIM</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0-3</dimIndex>
+          <name>HSTIMER%s_VALUE</name>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>software can read this register to get the current counter value in high speed timer0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0-3</dimIndex>
+          <name>LSTIMER%s_CONF</name>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_RES</name>
+              <description>This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIV_NUM</name>
+              <description>This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAUSE</name>
+              <description>This bit is used to pause the counter in low speed timer0.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>This bit is used to reset low speed timer0 the counter will be 0 after reset.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_SEL</name>
+              <description>This bit is used to choose slow_clk or ref_tick for low speed timer0. 1'b1:slow_clk  0:ref_tick</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>Set this bit  to update  reg_div_num_lstime0 and  reg_lstimer0_lim.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LIM</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0-3</dimIndex>
+          <name>LSTIMER%s_VALUE</name>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>software can read this register to get the current counter value in low speed timer0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HSTIMER0_OVF_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel0  counter overflow.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSTIMER1_OVF_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel1  counter overflow.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSTIMER2_OVF_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel2  counter overflow.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSTIMER3_OVF_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel3  counter overflow.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER0_OVF_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel0  counter overflow.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER1_OVF_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel1  counter overflow.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER2_OVF_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel2  counter overflow.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER3_OVF_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel3  counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH0_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel 0 duty change done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH1_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel 1 duty change done.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH2_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel 2 duty change done.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH3_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel 3 duty change done.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH4_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel 4 duty change done.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH5_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel 5 duty change done.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH6_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel 6 duty change done.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH7_INT_RAW</name>
+              <description>The interrupt raw bit for high speed channel 7 duty change done.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH0_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel 0 duty change done.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH1_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel 1 duty change done.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH2_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel 2 duty change done.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH3_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel 3 duty change done.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH4_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel 4 duty change done.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH5_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel 5 duty change done.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH6_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel 6 duty change done.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH7_INT_RAW</name>
+              <description>The interrupt raw bit for low speed channel 7 duty change done.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HSTIMER0_OVF_INT_ST</name>
+              <description>The interrupt status bit for high speed channel0  counter overflow event.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSTIMER1_OVF_INT_ST</name>
+              <description>The interrupt status bit for high speed channel1  counter overflow event.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSTIMER2_OVF_INT_ST</name>
+              <description>The interrupt status bit for high speed channel2  counter overflow event.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSTIMER3_OVF_INT_ST</name>
+              <description>The interrupt status bit for high speed channel3  counter overflow event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER0_OVF_INT_ST</name>
+              <description>The interrupt status bit for low speed channel0  counter overflow event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER1_OVF_INT_ST</name>
+              <description>The interrupt status bit for low speed channel1  counter overflow event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER2_OVF_INT_ST</name>
+              <description>The interrupt status bit for low speed channel2  counter overflow event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER3_OVF_INT_ST</name>
+              <description>The interrupt status bit for low speed channel3  counter overflow event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH0_INT_ST</name>
+              <description>The interrupt status bit for high speed channel 0 duty change done event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH1_INT_ST</name>
+              <description>The interrupt status bit for high speed channel 1 duty change done event.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH2_INT_ST</name>
+              <description>The interrupt status bit for high speed channel 2 duty change done event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH3_INT_ST</name>
+              <description>The interrupt status bit for high speed channel 3 duty change done event.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH4_INT_ST</name>
+              <description>The interrupt status bit for high speed channel 4 duty change done event.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH5_INT_ST</name>
+              <description>The interrupt status bit for high speed channel 5 duty change done event.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH6_INT_ST</name>
+              <description>The interrupt status bit for high speed channel 6 duty change done event.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH7_INT_ST</name>
+              <description>The interrupt status bit for high speed channel 7 duty change done event.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH0_INT_ST</name>
+              <description>The interrupt status bit for low speed channel 0 duty change done event.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH1_INT_ST</name>
+              <description>The interrupt status bit for low speed channel 1 duty change done event.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH2_INT_ST</name>
+              <description>The interrupt status bit for low speed channel 2 duty change done event.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH3_INT_ST</name>
+              <description>The interrupt status bit for low speed channel 3 duty change done event.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH4_INT_ST</name>
+              <description>The interrupt status bit for low speed channel 4 duty change done event.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH5_INT_ST</name>
+              <description>The interrupt status bit for low speed channel 5 duty change done event.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH6_INT_ST</name>
+              <description>The interrupt status bit for low speed channel 6 duty change done event.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH7_INT_ST</name>
+              <description>The interrupt status bit for low speed channel 7 duty change done event</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HSTIMER0_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel0  counter overflow interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTIMER1_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel1  counter overflow interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTIMER2_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel2  counter overflow interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTIMER3_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel3  counter overflow interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSTIMER0_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel0  counter overflow interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSTIMER1_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel1  counter overflow interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSTIMER2_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel2  counter overflow interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSTIMER3_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel3  counter overflow interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH0_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel 0 duty change done interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH1_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel 1 duty change done interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH2_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel 2 duty change done interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH3_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel 3 duty change done interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH4_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel 4 duty change done interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH5_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel 5 duty change done interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH6_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel 6 duty change done interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH7_INT_ENA</name>
+              <description>The interrupt enable bit for high speed channel 7 duty change done interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH0_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel 0 duty change done interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH1_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel 1 duty change done interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH2_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel 2 duty change done interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH3_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel 3 duty change done interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH4_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel 4 duty change done interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH5_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel 5 duty change done interrupt.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH6_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel 6 duty change done interrupt.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH7_INT_ENA</name>
+              <description>The interrupt enable bit for low speed channel 7 duty change done interrupt.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HSTIMER0_OVF_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel0  counter overflow interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HSTIMER1_OVF_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel1  counter overflow interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HSTIMER2_OVF_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel2  counter overflow interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HSTIMER3_OVF_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel3  counter overflow interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LSTIMER0_OVF_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel0  counter overflow interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LSTIMER1_OVF_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel1  counter overflow interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LSTIMER2_OVF_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel2  counter overflow interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LSTIMER3_OVF_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel3  counter overflow interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH0_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel 0 duty change done interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH1_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel 1 duty change done interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH2_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel 2 duty change done interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH3_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel 3 duty change done interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH4_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel 4 duty change done interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH5_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel 5 duty change done interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH6_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel 6 duty change done interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_HSCH7_INT_CLR</name>
+              <description>Set this  bit to clear  high speed channel 7 duty change done interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH0_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel 0 duty change done interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH1_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel 1 duty change done interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH2_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel 2 duty change done interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH3_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel 3 duty change done interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH4_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel 4 duty change done interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH5_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel 5 duty change done interrupt.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH6_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel 6 duty change done interrupt.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH7_INT_CLR</name>
+              <description>Set this  bit to clear  low speed channel 7 duty change done interrupt.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_CLK_SEL</name>
+              <description>This bit is used to set the frequency of slow_clk. 1'b1:80mhz  1'b0:8mhz</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x16031700</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This register represents the version .</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PWM0</name>
+      <description>Motor Control Pulse-Width Modulation</description>
+      <groupName>MCPWM</groupName>
+      <baseAddress>0x3FF5E000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x128</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PWM0</name>
+        <value>39</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CLK_CFG</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_PRESCALE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_CFG0</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>TIMER0_PRESCALE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PERIOD</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PERIOD_UPMETHOD</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_CFG1</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_START</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_MOD</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_SYNC</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_SYNCI_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_SYNCO_SEL</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PHASE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PHASE_DIRECTION</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_STATUS</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_VALUE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_DIRECTION</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_CFG0</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>TIMER1_PRESCALE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PERIOD</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PERIOD_UPMETHOD</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_CFG1</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER1_START</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_MOD</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_SYNC</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER1_SYNCI_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_SYNCO_SEL</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PHASE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PHASE_DIRECTION</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_STATUS</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER1_VALUE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_DIRECTION</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_CFG0</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>TIMER2_PRESCALE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PERIOD</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PERIOD_UPMETHOD</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_CFG1</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER2_START</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_MOD</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_SYNC</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER2_SYNCI_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_SYNCO_SEL</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PHASE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PHASE_DIRECTION</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_STATUS</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER2_VALUE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_DIRECTION</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_SYNCI_CFG</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_SYNCISEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_SYNCISEL</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_SYNCISEL</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTERNAL_SYNCI0_INVERT</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTERNAL_SYNCI1_INVERT</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTERNAL_SYNCI2_INVERT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OPERATOR_TIMERSEL</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OPERATOR0_TIMERSEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OPERATOR1_TIMERSEL</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OPERATOR2_TIMERSEL</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_STMP_CFG</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN0_A_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_UPMETHOD</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_SHDW_FULL</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_SHDW_FULL</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_TSTMP_A</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN0_A</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_TSTMP_B</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN0_B</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_CFG0</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN0_CFG_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_T0_SEL</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_T1_SEL</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_FORCE</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>GEN0_CNTUFORCE_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_CNTUFORCE_MODE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_CNTUFORCE_MODE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_NCIFORCE</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_NCIFORCE_MODE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_NCIFORCE</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_NCIFORCE_MODE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_A</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_B</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT0_CFG</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>DT0_FED_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_RED_UPMETHOD</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_DEB_MODE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_A_OUTSWAP</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_B_OUTSWAP</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_RED_INSEL</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_FED_INSEL</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_RED_OUTINVERT</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_FED_OUTINVERT</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_A_OUTBYPASS</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_B_OUTBYPASS</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0_CLK_SEL</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT0_FED_CFG</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DT0_FED</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT0_RED_CFG</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DT0_RED</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CARRIER0_CFG</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARRIER0_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER0_PRESCALE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER0_DUTY</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER0_OSHTWTH</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER0_OUT_INVERT</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER0_IN_INVERT</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH0_CFG0</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FH0_SW_CBC</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_F2_CBC</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_F1_CBC</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_F0_CBC</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_SW_OST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_F2_OST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_F1_OST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_F0_OST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_A_CBC_D</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_A_CBC_U</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_A_OST_D</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_A_OST_U</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_B_CBC_D</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_B_CBC_U</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_B_OST_D</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_B_OST_U</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH0_CFG1</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FH0_CLR_OST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_CBCPULSE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_FORCE_CBC</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_FORCE_OST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH0_STATUS</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FH0_CBC_ON</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH0_OST_ON</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_STMP_CFG</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN1_A_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_UPMETHOD</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_SHDW_FULL</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_SHDW_FULL</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_TSTMP_A</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN1_A</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_TSTMP_B</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN1_B</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_CFG0</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN1_CFG_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_T0_SEL</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_T1_SEL</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_FORCE</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>GEN1_CNTUFORCE_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_CNTUFORCE_MODE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_CNTUFORCE_MODE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_NCIFORCE</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_NCIFORCE_MODE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_NCIFORCE</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_NCIFORCE_MODE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_A</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_B</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT1_CFG</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>DT1_FED_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_RED_UPMETHOD</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_DEB_MODE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_A_OUTSWAP</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_B_OUTSWAP</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_RED_INSEL</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_FED_INSEL</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_RED_OUTINVERT</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_FED_OUTINVERT</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_A_OUTBYPASS</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_B_OUTBYPASS</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1_CLK_SEL</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT1_FED_CFG</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DT1_FED</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT1_RED_CFG</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DT1_RED</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CARRIER1_CFG</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARRIER1_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER1_PRESCALE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER1_DUTY</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER1_OSHTWTH</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER1_OUT_INVERT</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER1_IN_INVERT</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH1_CFG0</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FH1_SW_CBC</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_F2_CBC</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_F1_CBC</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_F0_CBC</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_SW_OST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_F2_OST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_F1_OST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_F0_OST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_A_CBC_D</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_A_CBC_U</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_A_OST_D</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_A_OST_U</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_B_CBC_D</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_B_CBC_U</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_B_OST_D</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_B_OST_U</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH1_CFG1</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FH1_CLR_OST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_CBCPULSE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_FORCE_CBC</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_FORCE_OST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH1_STATUS</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FH1_CBC_ON</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH1_OST_ON</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_STMP_CFG</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN2_A_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_UPMETHOD</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_SHDW_FULL</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_SHDW_FULL</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_TSTMP_A</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN2_A</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_TSTMP_B</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN2_B</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_CFG0</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN2_CFG_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_T0_SEL</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_T1_SEL</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_FORCE</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>GEN2_CNTUFORCE_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_CNTUFORCE_MODE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_CNTUFORCE_MODE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_NCIFORCE</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_NCIFORCE_MODE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_NCIFORCE</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_NCIFORCE_MODE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_A</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_B</name>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT2_CFG</name>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>DT2_FED_UPMETHOD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_RED_UPMETHOD</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_DEB_MODE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_A_OUTSWAP</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_B_OUTSWAP</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_RED_INSEL</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_FED_INSEL</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_RED_OUTINVERT</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_FED_OUTINVERT</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_A_OUTBYPASS</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_B_OUTBYPASS</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT2_CLK_SEL</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT2_FED_CFG</name>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DT2_FED</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT2_RED_CFG</name>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DT2_RED</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CARRIER2_CFG</name>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARRIER2_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER2_PRESCALE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER2_DUTY</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER2_OSHTWTH</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER2_OUT_INVERT</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER2_IN_INVERT</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH2_CFG0</name>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FH2_SW_CBC</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_F2_CBC</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_F1_CBC</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_F0_CBC</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_SW_OST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_F2_OST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_F1_OST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_F0_OST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_A_CBC_D</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_A_CBC_U</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_A_OST_D</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_A_OST_U</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_B_CBC_D</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_B_CBC_U</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_B_OST_D</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_B_OST_U</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH2_CFG1</name>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FH2_CLR_OST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_CBCPULSE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_FORCE_CBC</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_FORCE_OST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH2_STATUS</name>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FH2_CBC_ON</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH2_OST_ON</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FAULT_DETECT</name>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>F0_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F1_EN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F2_EN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F0_POLE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F1_POLE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F2_POLE</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVENT_F0</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EVENT_F1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EVENT_F2</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_TIMER_CFG</name>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP_TIMER_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP_SYNCI_EN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP_SYNCI_SEL</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP_SYNC_SW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_TIMER_PHASE</name>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP_TIMER_PHASE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH0_CFG</name>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP0_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_MODE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_PRESCALE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_IN_INVERT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_SW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH1_CFG</name>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP1_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_MODE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_PRESCALE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_IN_INVERT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_SW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH2_CFG</name>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP2_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_MODE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_PRESCALE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_IN_INVERT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_SW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH0</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP0_VALUE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH1</name>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP1_VALUE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH2</name>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP2_VALUE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_STATUS</name>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP0_EDGE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP1_EDGE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP2_EDGE</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UPDATE_CFG</name>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000055</resetValue>
+          <fields>
+            <field>
+              <name>GLOBAL_UP_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLOBAL_FORCE_UP</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP0_UP_EN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP0_FORCE_UP</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP1_UP_EN</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP1_FORCE_UP</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP2_UP_EN</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP2_FORCE_UP</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP0_TEA_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP1_TEA_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP2_TEA_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP0_TEB_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP1_TEB_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP2_TEB_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_CBC_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_CBC_INT_ENA</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_CBC_INT_ENA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH0_OST_INT_ENA</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH1_OST_INT_ENA</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FH2_OST_INT_ENA</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_INT_ENA</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_INT_ENA</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_INT_ENA</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_RAW</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_RAW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_RAW</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_RAW</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_RAW</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_RAW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_RAW</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_RAW</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_RAW</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_RAW</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_RAW</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_RAW</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_RAW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_RAW</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_RAW</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP0_TEA_INT_RAW</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP1_TEA_INT_RAW</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP2_TEA_INT_RAW</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP0_TEB_INT_RAW</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP1_TEB_INT_RAW</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP2_TEB_INT_RAW</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH0_CBC_INT_RAW</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH1_CBC_INT_RAW</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH2_CBC_INT_RAW</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH0_OST_INT_RAW</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH1_OST_INT_RAW</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH2_OST_INT_RAW</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP0_INT_RAW</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP1_INT_RAW</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP2_INT_RAW</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_ST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_ST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_ST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_ST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_ST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_ST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_ST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_ST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_ST</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_ST</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_ST</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP0_TEA_INT_ST</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP1_TEA_INT_ST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP2_TEA_INT_ST</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP0_TEB_INT_ST</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP1_TEB_INT_ST</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP2_TEB_INT_ST</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH0_CBC_INT_ST</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH1_CBC_INT_ST</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH2_CBC_INT_ST</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH0_OST_INT_ST</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH1_OST_INT_ST</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FH2_OST_INT_ST</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP0_INT_ST</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP1_INT_ST</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP2_INT_ST</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_CLR</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_CLR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_CLR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_CLR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_CLR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_CLR</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_CLR</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_CLR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_CLR</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OP0_TEA_INT_CLR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OP1_TEA_INT_CLR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OP2_TEA_INT_CLR</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OP0_TEB_INT_CLR</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OP1_TEB_INT_CLR</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OP2_TEB_INT_CLR</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FH0_CBC_INT_CLR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FH1_CBC_INT_CLR</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FH2_CBC_INT_CLR</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FH0_OST_INT_CLR</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FH1_OST_INT_CLR</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FH2_OST_INT_CLR</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAP0_INT_CLR</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAP1_INT_CLR</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAP2_INT_CLR</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VERSION</name>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02107230</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PWM0">
+      <name>PWM1</name>
+      <description>Motor Control Pulse-Width Modulation</description>
+      <baseAddress>0x3FF6C000</baseAddress>
+      <interrupt>
+        <name>PWM1</name>
+        <value>40</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>NRX</name>
+      <description>Peripheral NRX</description>
+      <groupName>NRX</groupName>
+      <baseAddress>0x3FF5CC00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>NRXPD_CTRL</name>
+          <description>WiFi RX control register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DEMAP_FORCE_PD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEMAP_FORCE_PU</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VIT_FORCE_PD</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VIT_FORCE_PU</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_ROT_FORCE_PD</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_ROT_FORCE_PU</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAN_EST_FORCE_PD</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAN_EST_FORCE_PU</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PCNT</name>
+      <description>Pulse Count Controller</description>
+      <groupName>PCNT</groupName>
+      <baseAddress>0x3FF57000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PCNT</name>
+        <value>48</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>U0_CONF0</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U0</name>
+              <description>This register is used to filter pluse whose width is smaller than this value for unit0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U0</name>
+              <description>This is the enable bit for filtering input signals for unit0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U0</name>
+              <description>This is the enable bit for comparing unit0's count with 0 value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U0</name>
+              <description>This is the enable bit for  comparing unit0's count with thr_h_lim value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U0</name>
+              <description>This is the enable bit for comparing unit0's count with thr_l_lim  value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U0</name>
+              <description>This is the enable bit for comparing unit0's count with  thres0 value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U0</name>
+              <description>This is the enable bit for  comparing  unit0's count with thres1 value .</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U0</name>
+              <description>This register is used to control the mode of channel0's input negedge signal for unit0. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U0</name>
+              <description>This register is used to control the mode of channel0's input posedge signal for unit0. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U0</name>
+              <description>This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U0</name>
+              <description>This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U0</name>
+              <description>This register is used to control the mode of channel1's input negedge signal for unit0. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U0</name>
+              <description>This register is used to control the mode of channel1's input posedge signal for unit0. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U0</name>
+              <description>This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U0</name>
+              <description>This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U0_CONF1</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U0</name>
+              <description>This register is used to configure thres0 value for unit0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U0</name>
+              <description>This register is used to configure  thres1 value for unit0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U0_CONF2</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U0</name>
+              <description>This register is used to configure thr_h_lim value for unit0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U0</name>
+              <description>This register is used to confiugre thr_l_lim value for unit0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U1_CONF0</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U1</name>
+              <description>This register is used to filter pluse whose width is smaller than this value for unit1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U1</name>
+              <description>This is the enable bit for filtering input signals for unit1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U1</name>
+              <description>This is the enable bit for comparing unit1's count with 0 value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U1</name>
+              <description>This is the enable bit for  comparing unit1's count with thr_h_lim value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U1</name>
+              <description>This is the enable bit for comparing unit1's count with thr_l_lim  value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U1</name>
+              <description>This is the enable bit for comparing unit1's count with  thres0 value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U1</name>
+              <description>This is the enable bit for  comparing  unit1's count with thres1 value .</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U1</name>
+              <description>This register is used to control the mode of channel0's input negedge signal for unit1. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U1</name>
+              <description>This register is used to control the mode of channel0's input posedge signal for unit1. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U1</name>
+              <description>This register is used to control the mode of channel0's high control signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U1</name>
+              <description>This register is used to control the mode of channel0's low control signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U1</name>
+              <description>This register is used to control the mode of channel1's input negedge signal for unit1. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U1</name>
+              <description>This register is used to control the mode of channel1's input posedge signal for unit1. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U1</name>
+              <description>This register is used to control the mode of channel1's high control signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U1</name>
+              <description>This register is used to control the mode of channel1's low control signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U1_CONF1</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U1</name>
+              <description>This register is used to configure thres0 value for unit1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U1</name>
+              <description>This register is used to configure  thres1 value for unit1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U1_CONF2</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U1</name>
+              <description>This register is used to configure thr_h_lim value for unit1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U1</name>
+              <description>This register is used to confiugre thr_l_lim value for unit1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U2_CONF0</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U2</name>
+              <description>This register is used to filter pluse whose width is smaller than this value for unit2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U2</name>
+              <description>This is the enable bit for filtering input signals for unit2.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U2</name>
+              <description>This is the enable bit for comparing unit2's count with 0 value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U2</name>
+              <description>This is the enable bit for  comparing unit2's count with thr_h_lim value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U2</name>
+              <description>This is the enable bit for comparing unit2's count with thr_l_lim  value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U2</name>
+              <description>This is the enable bit for comparing unit2's count with  thres0 value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U2</name>
+              <description>This is the enable bit for  comparing  unit2's count with thres1 value .</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U2</name>
+              <description>This register is used to control the mode of channel0's input negedge signal for unit2. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U2</name>
+              <description>This register is used to control the mode of channel0's input posedge signal for unit2. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U2</name>
+              <description>This register is used to control the mode of channel0's high control signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U2</name>
+              <description>This register is used to control the mode of channel0's low control signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U2</name>
+              <description>This register is used to control the mode of channel1's input negedge signal for unit2. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U2</name>
+              <description>This register is used to control the mode of channel1's input posedge signal for unit2. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U2</name>
+              <description>This register is used to control the mode of channel1's high control signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U2</name>
+              <description>This register is used to control the mode of channel1's low control signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U2_CONF1</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U2</name>
+              <description>This register is used to configure thres0 value for unit2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U2</name>
+              <description>This register is used to configure  thres1 value for unit2.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U2_CONF2</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U2</name>
+              <description>This register is used to configure thr_h_lim value for unit2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U2</name>
+              <description>This register is used to confiugre thr_l_lim value for unit2.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U3_CONF0</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U3</name>
+              <description>This register is used to filter pluse whose width is smaller than this value for unit3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U3</name>
+              <description>This is the enable bit for filtering input signals for unit3.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U3</name>
+              <description>This is the enable bit for comparing unit3's count with 0 value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U3</name>
+              <description>This is the enable bit for  comparing unit3's count with thr_h_lim value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U3</name>
+              <description>This is the enable bit for comparing unit3's count with thr_l_lim  value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U3</name>
+              <description>This is the enable bit for comparing unit3's count with  thres0 value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U3</name>
+              <description>This is the enable bit for  comparing  unit3's count with thres1 value .</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U3</name>
+              <description>This register is used to control the mode of channel0's input negedge signal for unit3. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U3</name>
+              <description>This register is used to control the mode of channel0's input posedge signal for unit3. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U3</name>
+              <description>This register is used to control the mode of channel0's high control signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U3</name>
+              <description>This register is used to control the mode of channel0's low control signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U3</name>
+              <description>This register is used to control the mode of channel1's input negedge signal for unit3. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U3</name>
+              <description>This register is used to control the mode of channel1's input posedge signal for unit3. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U3</name>
+              <description>This register is used to control the mode of channel1's high control signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U3</name>
+              <description>This register is used to control the mode of channel1's low control signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U3_CONF1</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U3</name>
+              <description>This register is used to configure thres0 value for unit3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U3</name>
+              <description>This register is used to configure  thres1 value for unit3.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U3_CONF2</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U3</name>
+              <description>This register is used to configure thr_h_lim value for unit3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U3</name>
+              <description>This register is used to confiugre thr_l_lim value for unit3.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U4_CONF0</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U4</name>
+              <description>This register is used to filter pluse whose width is smaller than this value for unit4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U4</name>
+              <description>This is the enable bit for filtering input signals for unit4.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U4</name>
+              <description>This is the enable bit for comparing unit4's count with 0 value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U4</name>
+              <description>This is the enable bit for  comparing unit4's count with thr_h_lim value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U4</name>
+              <description>This is the enable bit for comparing unit4's count with thr_l_lim  value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U4</name>
+              <description>This is the enable bit for comparing unit4's count with  thres0 value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U4</name>
+              <description>This is the enable bit for  comparing  unit4's count with thres1 value .</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U4</name>
+              <description>This register is used to control the mode of channel0's input negedge signal for unit4. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U4</name>
+              <description>This register is used to control the mode of channel0's input posedge signal for unit4. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U4</name>
+              <description>This register is used to control the mode of channel0's high control signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U4</name>
+              <description>This register is used to control the mode of channel0's low control signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U4</name>
+              <description>This register is used to control the mode of channel1's input negedge signal for unit4. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U4</name>
+              <description>This register is used to control the mode of channel1's input posedge signal for unit4. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U4</name>
+              <description>This register is used to control the mode of channel1's high control signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U4</name>
+              <description>This register is used to control the mode of channel1's low control signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U4_CONF1</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U4</name>
+              <description>This register is used to configure thres0 value for unit4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U4</name>
+              <description>This register is used to configure  thres1 value for unit4.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U4_CONF2</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U4</name>
+              <description>This register is used to configure thr_h_lim value for unit4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U4</name>
+              <description>This register is used to confiugre thr_l_lim value for unit4.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U5_CONF0</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U5</name>
+              <description>This register is used to filter pluse whose width is smaller than this value for unit5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U5</name>
+              <description>This is the enable bit for filtering input signals for unit5.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U5</name>
+              <description>This is the enable bit for comparing unit5's count with 0 value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U5</name>
+              <description>This is the enable bit for  comparing unit5's count with thr_h_lim value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U5</name>
+              <description>This is the enable bit for comparing unit5's count with thr_l_lim  value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U5</name>
+              <description>This is the enable bit for comparing unit5's count with  thres0 value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U5</name>
+              <description>This is the enable bit for  comparing  unit5's count with thres1 value .</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U5</name>
+              <description>This register is used to control the mode of channel0's input negedge signal for unit5. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U5</name>
+              <description>This register is used to control the mode of channel0's input posedge signal for unit5. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U5</name>
+              <description>This register is used to control the mode of channel0's high control signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U5</name>
+              <description>This register is used to control the mode of channel0's low control signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U5</name>
+              <description>This register is used to control the mode of channel1's input negedge signal for unit5. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U5</name>
+              <description>This register is used to control the mode of channel1's input posedge signal for unit5. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U5</name>
+              <description>This register is used to control the mode of channel1's high control signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U5</name>
+              <description>This register is used to control the mode of channel1's low control signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U5_CONF1</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U5</name>
+              <description>This register is used to configure thres0 value for unit5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U5</name>
+              <description>This register is used to configure  thres1 value for unit5.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U5_CONF2</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U5</name>
+              <description>This register is used to configure thr_h_lim value for unit5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U5</name>
+              <description>This register is used to confiugre thr_l_lim value for unit5.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U6_CONF0</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U6</name>
+              <description>This register is used to filter pluse whose width is smaller than this value for unit6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U6</name>
+              <description>This is the enable bit for filtering input signals for unit6.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U6</name>
+              <description>This is the enable bit for comparing unit6's count with 0 value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U6</name>
+              <description>This is the enable bit for  comparing unit6's count with thr_h_lim value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U6</name>
+              <description>This is the enable bit for comparing unit6's count with thr_l_lim  value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U6</name>
+              <description>This is the enable bit for comparing unit6's count with  thres0 value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U6</name>
+              <description>This is the enable bit for  comparing  unit6's count with thres1 value .</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U6</name>
+              <description>This register is used to control the mode of channel0's input negedge signal for unit6. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U6</name>
+              <description>This register is used to control the mode of channel0's input posedge signal for unit6. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U6</name>
+              <description>This register is used to control the mode of channel0's high control signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U6</name>
+              <description>This register is used to control the mode of channel0's low control signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U6</name>
+              <description>This register is used to control the mode of channel1's input negedge signal for unit6. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U6</name>
+              <description>This register is used to control the mode of channel1's input posedge signal for unit6. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U6</name>
+              <description>This register is used to control the mode of channel1's high control signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U6</name>
+              <description>This register is used to control the mode of channel1's low control signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U6_CONF1</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U6</name>
+              <description>This register is used to configure thres0 value for unit6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U6</name>
+              <description>This register is used to configure  thres1 value for unit6.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U6_CONF2</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U6</name>
+              <description>This register is used to configure thr_h_lim value for unit6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U6</name>
+              <description>This register is used to confiugre thr_l_lim value for unit6.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U7_CONF0</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U7</name>
+              <description>This register is used to filter pluse whose width is smaller than this value for unit7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U7</name>
+              <description>This is the enable bit for filtering input signals for unit7.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U7</name>
+              <description>This is the enable bit for comparing unit7's count with 0 value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U7</name>
+              <description>This is the enable bit for  comparing unit7's count with thr_h_lim value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U7</name>
+              <description>This is the enable bit for comparing unit7's count with thr_l_lim  value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U7</name>
+              <description>This is the enable bit for comparing unit7's count with  thres0 value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U7</name>
+              <description>This is the enable bit for  comparing  unit7's count with thres1 value .</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U7</name>
+              <description>This register is used to control the mode of channel0's input negedge signal for unit7. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U7</name>
+              <description>This register is used to control the mode of channel0's input posedge signal for unit7. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U7</name>
+              <description>This register is used to control the mode of channel0's high control signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U7</name>
+              <description>This register is used to control the mode of channel0's low control signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U7</name>
+              <description>This register is used to control the mode of channel1's input negedge signal for unit7. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U7</name>
+              <description>This register is used to control the mode of channel1's input posedge signal for unit7. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U7</name>
+              <description>This register is used to control the mode of channel1's high control signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U7</name>
+              <description>This register is used to control the mode of channel1's low control signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U7_CONF1</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U7</name>
+              <description>This register is used to configure thres0 value for unit7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U7</name>
+              <description>This register is used to configure  thres1 value for unit7.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U7_CONF2</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U7</name>
+              <description>This register is used to configure thr_h_lim value for unit7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U7</name>
+              <description>This register is used to confiugre thr_l_lim value for unit7.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U0_CNT</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLUS_CNT_U0</name>
+              <description>This register stores the current pulse count value for unit0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U1_CNT</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLUS_CNT_U1</name>
+              <description>This register stores the current pulse count value for unit1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U2_CNT</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLUS_CNT_U2</name>
+              <description>This register stores the current pulse count value for unit2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U3_CNT</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLUS_CNT_U3</name>
+              <description>This register stores the current pulse count value for unit3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U4_CNT</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLUS_CNT_U4</name>
+              <description>This register stores the current pulse count value for unit4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U5_CNT</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLUS_CNT_U5</name>
+              <description>This register stores the current pulse count value for unit5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U6_CNT</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLUS_CNT_U6</name>
+              <description>This register stores the current pulse count value for unit6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U7_CNT</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLUS_CNT_U7</name>
+              <description>This register stores the current pulse count value for unit7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_RAW</name>
+              <description>This is the interrupt raw bit for channel0 event.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_RAW</name>
+              <description>This is the interrupt raw bit for channel1 event.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_RAW</name>
+              <description>This is the interrupt raw bit for channel2 event.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_RAW</name>
+              <description>This is the interrupt raw bit for channel3 event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U4_INT_RAW</name>
+              <description>This is the interrupt raw bit for channel4 event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U5_INT_RAW</name>
+              <description>This is the interrupt raw bit for channel5 event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U6_INT_RAW</name>
+              <description>This is the interrupt raw bit for channel6 event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U7_INT_RAW</name>
+              <description>This is the interrupt raw bit for channel7 event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ST</name>
+              <description>This is the  interrupt status bit for channel0 event.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ST</name>
+              <description>This is the  interrupt status bit for channel1 event.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ST</name>
+              <description>This is the  interrupt status bit for channel2 event.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ST</name>
+              <description>This is the  interrupt status bit for channel3 event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U4_INT_ST</name>
+              <description>This is the  interrupt status bit for channel4 event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U5_INT_ST</name>
+              <description>This is the  interrupt status bit for channel5 event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U6_INT_ST</name>
+              <description>This is the  interrupt status bit for channel6 event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U7_INT_ST</name>
+              <description>This is the  interrupt status bit for channel7 event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ENA</name>
+              <description>This is the  interrupt enable bit for channel0 event.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ENA</name>
+              <description>This is the  interrupt enable bit for channel1 event.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ENA</name>
+              <description>This is the  interrupt enable bit for channel2 event.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ENA</name>
+              <description>This is the  interrupt enable bit for channel3 event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U4_INT_ENA</name>
+              <description>This is the  interrupt enable bit for channel4 event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U5_INT_ENA</name>
+              <description>This is the  interrupt enable bit for channel5 event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U6_INT_ENA</name>
+              <description>This is the  interrupt enable bit for channel6 event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U7_INT_ENA</name>
+              <description>This is the  interrupt enable bit for channel7 event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_CLR</name>
+              <description>Set this bit to clear channel0 event interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_CLR</name>
+              <description>Set this bit to clear channel1 event interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_CLR</name>
+              <description>Set this bit to clear channel2 event interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_CLR</name>
+              <description>Set this bit to clear channel3 event interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U4_INT_CLR</name>
+              <description>Set this bit to clear channel4 event interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U5_INT_CLR</name>
+              <description>Set this bit to clear channel5 event interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U6_INT_CLR</name>
+              <description>Set this bit to clear channel6 event interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U7_INT_CLR</name>
+              <description>Set this bit to clear channel7 event interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U0_STATUS</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_STATUS_U0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATUS_CNT_MODE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STATUS_THRES1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STATUS_THRES0</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STATUS_L_LIM</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STATUS_H_LIM</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STATUS_ZERO</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U1_STATUS</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_STATUS_U1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U2_STATUS</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_STATUS_U2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U3_STATUS</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_STATUS_U3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U4_STATUS</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_STATUS_U4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U5_STATUS</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_STATUS_U5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U6_STATUS</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_STATUS_U6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>U7_STATUS</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_STATUS_U7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00005555</resetValue>
+          <fields>
+            <field>
+              <name>PLUS_CNT_RST_U0</name>
+              <description>Set this bit to clear unit0's counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U0</name>
+              <description>Set this bit to pause unit0's counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLUS_CNT_RST_U1</name>
+              <description>Set this bit to clear unit1's counter.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U1</name>
+              <description>Set this bit to pause unit1's counter.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLUS_CNT_RST_U2</name>
+              <description>Set this bit to clear unit2's counter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U2</name>
+              <description>Set this bit to pause unit2's counter.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLUS_CNT_RST_U3</name>
+              <description>Set this bit to clear unit3's counter.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U3</name>
+              <description>Set this bit to pause unit3's counter.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLUS_CNT_RST_U4</name>
+              <description>Set this bit to clear unit4's counter.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U4</name>
+              <description>Set this bit to pause unit4's counter.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLUS_CNT_RST_U5</name>
+              <description>Set this bit to clear unit5's counter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U5</name>
+              <description>Set this bit to pause unit5's counter.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLUS_CNT_RST_U6</name>
+              <description>Set this bit to clear unit6's counter.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U6</name>
+              <description>Set this bit to pause unit6's counter.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLUS_CNT_RST_U7</name>
+              <description>Set this bit to clear unit7's counter.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U7</name>
+              <description>Set this bit to pause unit7's counter.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x14122600</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RMT</name>
+      <description>Remote Control Peripheral</description>
+      <groupName>RMT</groupName>
+      <baseAddress>0x3FF56000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xF8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RMT</name>
+        <value>47</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CH0DATA</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>CH1DATA</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>CH2DATA</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>CH3DATA</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>CH4DATA</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>CH5DATA</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>CH6DATA</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>CH7DATA</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>CH%sCONF0</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x31100002</resetValue>
+          <fields>
+            <field>
+              <name>DIV_CNT</name>
+              <description>This register is used to configure the  frequency divider's factor in channel0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_THRES</name>
+              <description>In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE</name>
+              <description>This register is used to configure the the amount of memory blocks allocated to channel0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN</name>
+              <description>This is the carrier modulation enable control bit for channel0.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV</name>
+              <description>This bit is used to configure the way carrier wave is modulated for  channel0.1'b1:transmit on low output level  1'b0:transmit  on high output level.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_PD</name>
+              <description>This bit is used to reduce power consumed by mem. 1:mem is in low power state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>This bit  is used  to control clock.when software config RMT internal registers  it controls the register clock.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>CH%sCONF1</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000F20</resetValue>
+          <fields>
+            <field>
+              <name>TX_START</name>
+              <description>Set this bit to start sending data for channel0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_EN</name>
+              <description>Set this bit to enbale receving data for channel0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_WR_RST</name>
+              <description>Set this bit to reset write ram address for channel0 by receiver access.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_RD_RST</name>
+              <description>Set this bit to reset read ram address for channel0 by transmitter access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST</name>
+              <description>Set this bit to reset W/R ram address for channel0 by apb fifo access</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_OWNER</name>
+              <description>This is the mark of channel0's ram usage right.1'b1：receiver uses the ram  0：transmitter uses the ram</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CONTI_MODE</name>
+              <description>Set this bit to continue sending  from the first data to the last data in channel0 again and again.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_EN</name>
+              <description>This is the receive filter enable bit for channel0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_THRES</name>
+              <description>in receive mode  channel0 ignore input pulse when the pulse width is smaller then this value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REF_CNT_RST</name>
+              <description>This bit is used to reset divider in channel0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REF_ALWAYS_ON</name>
+              <description>This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_LV</name>
+              <description>This bit configures the output signal's level for channel0 in IDLE state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_EN</name>
+              <description>This is the output enable control bit for channel0 in IDLE state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH0STATUS</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The status for channel0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>The current memory read address of channel0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>The current memory write address of channel0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>The channel0 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>When channel0 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>The memory full status bit for channel0 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>The memory empty status bit for channel0. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>The apb write memory status bit for channel0 turns to high level when the apb write address exceeds the configuration range.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>The apb read memory status bit for channel0 turns to high level when the apb read address exceeds the configuration range.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH1STATUS</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The status for channel1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>The current memory read address of channel1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>The current memory write address of channel1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>The channel1 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>When channel1 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>The memory full status bit for channel1 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>The memory empty status bit for channel1. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>The apb write memory status bit for channel1 turns to high level when the apb write address exceeds the configuration range.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>The apb read memory status bit for channel1 turns to high level when the apb read address exceeds the configuration range.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH2STATUS</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The status for channel2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>The current memory read address of channel2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>The current memory write address of channel2.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>The channel2 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>When channel2 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>The memory full status bit for channel2 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>The memory empty status bit for channel2. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>The apb write memory status bit for channel2 turns to high level when the apb write address exceeds the configuration range.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>The apb read memory status bit for channel2 turns to high level when the apb read address exceeds the configuration range.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH3STATUS</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The status for channel3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>The current memory read address of channel3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>The current memory write address of channel3.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>The channel3 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>When channel3 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>The memory full status bit for channel3 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>The memory empty status bit for channel3. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>The apb write memory status bit for channel3 turns to high level when the apb write address exceeds the configuration range.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>The apb read memory status bit for channel3 turns to high level when the apb read address exceeds the configuration range.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH4STATUS</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The status for channel4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>The current memory read address of channel4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>The current memory write address of channel4.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>The channel4 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>When channel4 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>The memory full status bit for channel4 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>The memory empty status bit for channel4. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>The apb write memory status bit for channel4 turns to high level when the apb write address exceeds the configuration range.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>The apb read memory status bit for channel4 turns to high level when the apb read address exceeds the configuration range.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH5STATUS</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The status for channel5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>The current memory read address of channel5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>The current memory write address of channel5.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>The channel5 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>When channel5 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>The memory full status bit for channel5 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>The memory empty status bit for channel5. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>The apb write memory status bit for channel5 turns to high level when the apb write address exceeds the configuration range.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>The apb read memory status bit for channel5 turns to high level when the apb read address exceeds the configuration range.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH6STATUS</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The status for channel6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>The current memory read address of channel6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>The current memory write address of channel6.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>The channel6 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>When channel6 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>The memory full status bit for channel6 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>The memory empty status bit for channel6. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>The apb write memory status bit for channel6 turns to high level when the apb write address exceeds the configuration range.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>The apb read memory status bit for channel6 turns to high level when the apb read address exceeds the configuration range.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH7STATUS</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The status for channel7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>The current memory read address of channel7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>The current memory write address of channel7.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>The channel7 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>When channel7 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>The memory full status bit for channel7 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>The memory empty status bit for channel7. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>The apb write memory status bit for channel7 turns to high level when the apb write address exceeds the configuration range.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>The apb read memory status bit for channel7 turns to high level when the apb read address exceeds the configuration range.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH0ADDR</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_MEM_ADDR</name>
+              <description>The ram relative address in channel0 by apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH1ADDR</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_MEM_ADDR</name>
+              <description>The ram relative address in channel1 by apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH2ADDR</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_MEM_ADDR</name>
+              <description>The ram relative address in channel2 by apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH3ADDR</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_MEM_ADDR</name>
+              <description>The ram relative address in channel3 by apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH4ADDR</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_MEM_ADDR</name>
+              <description>The ram relative address in channel4 by apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH5ADDR</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_MEM_ADDR</name>
+              <description>The ram relative address in channel5 by apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH6ADDR</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_MEM_ADDR</name>
+              <description>The ram relative address in channel6 by apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH7ADDR</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_MEM_ADDR</name>
+              <description>The ram relative address in channel7 by apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_TX_END_INT_RAW</name>
+              <description>The interrupt raw bit for channel %s turns to high level when the transmit process is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_RX_END_INT_RAW</name>
+              <description>The interrupt raw bit for channel %s turns to high level when the receive process is done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for channel %s turns to high level when channle %s detects some errors.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for channel %s turns to high level when transmitter in channle%s  have send datas more than  reg_rmt_tx_lim_ch%s  after detecting this interrupt  software can updata the old datas with new datas.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_TX_END_INT_ST</name>
+              <description>The interrupt  state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_RX_END_INT_ST</name>
+              <description>The interrupt  state bit for channel %s's rmt_ch%s_rx_end_int_raw when  rmt_ch%s_rx_end_int_ena is set to %s.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_ERR_INT_ST</name>
+              <description>The interrupt  state bit for channel %s's rmt_ch%s_err_int_raw when  rmt_ch%s_err_int_ena is set to %s.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_ST</name>
+              <description>The interrupt state bit  for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_TX_END_INT_ENA</name>
+              <description>Set this bit to enable rmt_ch%s_tx_end_int_st.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_RX_END_INT_ENA</name>
+              <description>Set this bit to enable rmt_ch%s_rx_end_int_st.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_ERR_INT_ENA</name>
+              <description>Set this bit to enable rmt_ch%s_err_int_st.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_ENA</name>
+              <description>Set this bit to enable rmt_ch%s_tx_thr_event_int_st.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_TX_END_INT_CLR</name>
+              <description>Set this bit to clear the rmt_ch%s_rx_end_int_raw..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_RX_END_INT_CLR</name>
+              <description>Set this bit to clear the rmt_ch%s_tx_end_int_raw.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_ERR_INT_CLR</name>
+              <description>Set this bit to clear the  rmt_ch%s_err_int_raw.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-7</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear the  rmt_ch%s_tx_thr_event_int_raw interrupt.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH0CARRIER_DUTY</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave's low level value for channel0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave's high level value for channel0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH1CARRIER_DUTY</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave's low level value for channel1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave's high level value for channel1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH2CARRIER_DUTY</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave's low level value for channel2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave's high level value for channel2.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH3CARRIER_DUTY</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave's low level value for channel3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave's high level value for channel3.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH4CARRIER_DUTY</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave's low level value for channel4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave's high level value for channel4.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH5CARRIER_DUTY</name>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave's low level value for channel5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave's high level value for channel5.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH6CARRIER_DUTY</name>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave's low level value for channel6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave's high level value for channel6.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH7CARRIER_DUTY</name>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave's low level value for channel7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave's high level value for channel7.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>CH%s_TX_LIM</name>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>TX_LIM</name>
+              <description>When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 produce the relative interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_CONF</name>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_FIFO_MASK</name>
+              <description>Set this bit to disable apb fifo access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TX_WRAP_EN</name>
+              <description>when datas need to be send is more than channel's mem can store  then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x16022600</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RNG</name>
+      <description>Hardware random number generator</description>
+      <groupName>RNG</groupName>
+      <baseAddress>0x60035000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>DATA</name>
+          <description>Random number data</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RSA</name>
+      <description>RSA (Rivest Shamir Adleman) Accelerator</description>
+      <groupName>RSA</groupName>
+      <baseAddress>0x3FF02000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RSA</name>
+        <value>51</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>M_PRIME</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M_PRIME</name>
+              <description>This register contains M’.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEXP_MODE</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEXP_MODE</name>
+              <description>This register contains the mode of modular exponentiation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEXP_START</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEXP_START</name>
+              <description>Write 1 to start modular exponentiation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_MODE</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MULT_MODE</name>
+              <description>This register contains the mode of modular multiplication and multiplication.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_START</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MULT_START</name>
+              <description>Write 1 to start modular multiplication or multiplication.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>RSA interrupt status register. Will read 1 once an operation has completed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAN</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAN</name>
+              <description>This bit will read 1 once the memory initialization is completed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC_CNTL</name>
+      <description>Real-Time Clock Control</description>
+      <groupName>RTC_CNTL</groupName>
+      <baseAddress>0x3FF48000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xDC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_CORE</name>
+        <value>46</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>OPTIONS0</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1C492000</resetValue>
+          <fields>
+            <field>
+              <name>SW_STALL_APPCPU_C0</name>
+              <description>{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STALL_PROCPU_C0</name>
+              <description>{reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_APPCPU_RST</name>
+              <description>APP CPU SW reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_PROCPU_RST</name>
+              <description>PRO CPU SW reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PD</name>
+              <description>BB_I2C force power down</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PU</name>
+              <description>BB_I2C force power up</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PD</name>
+              <description>BB_PLL _I2C force power down</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PU</name>
+              <description>BB_PLL_I2C force power up</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PD</name>
+              <description>BB_PLL force power down</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PU</name>
+              <description>BB_PLL force power up</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PD</name>
+              <description>crystall force power down</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PU</name>
+              <description>crystall force power up</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_SLEEP_FOLW_8M</name>
+              <description>BIAS_SLEEP follow CK8M</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_FORCE_SLEEP</name>
+              <description>BIAS_SLEEP force sleep</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_FORCE_NOSLEEP</name>
+              <description>BIAS_SLEEP force no sleep</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_I2C_FOLW_8M</name>
+              <description>BIAS_I2C follow CK8M</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_I2C_FORCE_PD</name>
+              <description>BIAS_I2C force power down</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_I2C_FORCE_PU</name>
+              <description>BIAS_I2C force power up</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_CORE_FOLW_8M</name>
+              <description>BIAS_CORE follow CK8M</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_CORE_FORCE_PD</name>
+              <description>BIAS_CORE force power down</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_CORE_FORCE_PU</name>
+              <description>BIAS_CORE force power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_ISO</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FORCE_ISO</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_ISO</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_NOISO</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FORCE_NOISO</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_NOISO</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_RST</name>
+              <description>digital wrap force reset in deep sleep</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NORST</name>
+              <description>digital core force no reset in deep sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_SYS_RST</name>
+              <description>SW system reset</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER0</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_LO</name>
+              <description>RTC sleep timer low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER1</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_HI</name>
+              <description>RTC sleep timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_ALARM_EN</name>
+              <description>timer alarm enable bit</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_UPDATE</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_VALID</name>
+              <description>To indicate the register is updated</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_UPDATE</name>
+              <description>Set 1: to update register with RTC timer</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME0</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_LO</name>
+              <description>RTC timer low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME1</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_HI</name>
+              <description>RTC timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00300000</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_WAKEUP_FORCE_EN</name>
+              <description>touch controller force wake up</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_WAKEUP_FORCE_EN</name>
+              <description>ULP-coprocessor force wake up</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB2RTC_BRIDGE_SEL</name>
+              <description>1: APB to RTC using bridge   0: APB to RTC using sync</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_TIMER_EN</name>
+              <description>touch timer enable bit</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_SLP_TIMER_EN</name>
+              <description>ULP-coprocessor timer enable bit</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_ACTIVE_IND</name>
+              <description>SDIO active indication</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_WAKEUP</name>
+              <description>sleep wakeup bit</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT</name>
+              <description>sleep reject bit</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_EN</name>
+              <description>sleep enable bit</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x28140403</resetValue>
+          <fields>
+            <field>
+              <name>CPU_STALL_EN</name>
+              <description>CPU stall enable bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_STALL_WAIT</name>
+              <description>CPU stall wait cycles in fast_clk_rtc</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_WAIT</name>
+              <description>CK8M wait cycles in slow_clk_rtc</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_BUF_WAIT</name>
+              <description>XTAL wait cycles in slow_clk_rtc</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_BUF_WAIT</name>
+              <description>PLL wait cycles in slow_clk_rtc</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01080000</resetValue>
+          <fields>
+            <field>
+              <name>ULPCP_TOUCH_START_WAIT</name>
+              <description>wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN_TIME_CK8M_OFF</name>
+              <description>minimal cycles in slow_clk_rtc for CK8M in power down state</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER3</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x14160A08</resetValue>
+          <fields>
+            <field>
+              <name>WIFI_WAIT_TIMER</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_POWERUP_TIMER</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM_RAM_WAIT_TIMER</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM_RAM_POWERUP_TIMER</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER4</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10200A08</resetValue>
+          <fields>
+            <field>
+              <name>WAIT_TIMER</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWERUP_TIMER</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_WAIT_TIMER</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_POWERUP_TIMER</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER5</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x12148001</resetValue>
+          <fields>
+            <field>
+              <name>ULP_CP_SUBTIMER_PREDIV</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN_SLP_VAL</name>
+              <description>minimal sleep cycles in slow_clk_rtc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTCMEM_WAIT_TIMER</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTCMEM_POWERUP_TIMER</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ANA_CONF</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>PLLA_FORCE_PD</name>
+              <description>PLLA force power down</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLA_FORCE_PU</name>
+              <description>PLLA force power up</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_SLP_START</name>
+              <description>start BBPLL calibration during sleep</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVTMON_PU</name>
+              <description>1: PVTMON power up   otherwise power down</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXRF_I2C_PU</name>
+              <description>1: TXRF_I2C power up   otherwise power down</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RFRX_PBUS_PU</name>
+              <description>1: RFRX_PBUS power up   otherwise power down</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CKGEN_I2C_PU</name>
+              <description>1: CKGEN_I2C power up   otherwise power down</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_I2C_PU</name>
+              <description>1: PLL_I2C power up   otherwise power down</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESET_STATE</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003000</resetValue>
+          <fields>
+            <field>
+              <name>RESET_CAUSE_PROCPU</name>
+              <description>reset cause of PRO CPU</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESET_CAUSE_APPCPU</name>
+              <description>reset cause of APP CPU</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APPCPU_STAT_VECTOR_SEL</name>
+              <description>APP CPU state vector sel</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PROCPU_STAT_VECTOR_SEL</name>
+              <description>PRO CPU state vector sel</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP_STATE</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00006000</resetValue>
+          <fields>
+            <field>
+              <name>WAKEUP_CAUSE</name>
+              <description>wakeup cause</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENA</name>
+              <description>wakeup enable bitmap</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_WAKEUP_FILTER</name>
+              <description>enable filter for gpio wakeup event</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA</name>
+              <description>enable sleep wakeup interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA</name>
+              <description>enable sleep reject interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ENA</name>
+              <description>enable SDIO idle interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>enable RTC WDT interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_VALID_INT_ENA</name>
+              <description>enable RTC time valid interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_ENA</name>
+              <description>enable ULP-coprocessor interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_INT_ENA</name>
+              <description>enable touch interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA</name>
+              <description>enable brown out interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA</name>
+              <description>enable RTC main timer interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_RAW</name>
+              <description>sleep wakeup interrupt raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_RAW</name>
+              <description>sleep reject interrupt raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_RAW</name>
+              <description>SDIO idle interrupt raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>RTC WDT interrupt raw</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_VALID_INT_RAW</name>
+              <description>RTC time valid interrupt raw</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_RAW</name>
+              <description>ULP-coprocessor interrupt raw</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INT_RAW</name>
+              <description>touch interrupt raw</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_RAW</name>
+              <description>brown out interrupt raw</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_RAW</name>
+              <description>RTC main timer interrupt raw</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ST</name>
+              <description>sleep wakeup interrupt state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ST</name>
+              <description>sleep reject interrupt state</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ST</name>
+              <description>SDIO idle interrupt state</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>RTC WDT interrupt state</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_VALID_INT_ST</name>
+              <description>RTC time valid interrupt state</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_INT_ST</name>
+              <description>ULP-coprocessor interrupt state</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INT_ST</name>
+              <description>touch interrupt state</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ST</name>
+              <description>brown out interrupt state</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ST</name>
+              <description>RTC main timer interrupt state</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_CLR</name>
+              <description>Clear sleep wakeup interrupt state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_CLR</name>
+              <description>Clear sleep reject interrupt state</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_CLR</name>
+              <description>Clear SDIO idle interrupt state</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Clear RTC WDT interrupt state</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_VALID_INT_CLR</name>
+              <description>Clear RTC time valid interrupt state</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_INT_CLR</name>
+              <description>Clear ULP-coprocessor interrupt state</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INT_CLR</name>
+              <description>Clear touch interrupt state</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_CLR</name>
+              <description>Clear brown out interrupt state</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_CLR</name>
+              <description>Clear RTC main timer interrupt state</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE0</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH0</name>
+              <description>32-bit general purpose retention register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE1</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH1</name>
+              <description>32-bit general purpose retention register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE2</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH2</name>
+              <description>32-bit general purpose retention register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE3</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH3</name>
+              <description>32-bit general purpose retention register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_XTL_CONF</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XTL_EXT_CTR_LV</name>
+              <description>0: power down XTAL at high level  1: power down XTAL at low level</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_EN</name>
+              <description>enable control XTAL by external pads</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP_CONF</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_WAKEUP0_LV</name>
+              <description>0: external wakeup at low level  1: external wakeup at high level</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP1_LV</name>
+              <description>0: external wakeup at low level  1: external wakeup at high level</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_REJECT_CONF</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_REJECT_EN</name>
+              <description>enable GPIO reject</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_REJECT_EN</name>
+              <description>enable SDIO reject</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LIGHT_SLP_REJECT_EN</name>
+              <description>enable reject for light sleep</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEEP_SLP_REJECT_EN</name>
+              <description>enable reject for deep sleep</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REJECT_CAUSE</name>
+              <description>sleep reject cause</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERIOD_CONF</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPUSEL_CONF</name>
+              <description>CPU sel option</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <description>CPU period sel</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_ACT_CONF</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_ACT_DNUM</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002210</resetValue>
+          <fields>
+            <field>
+              <name>CK8M_DIV</name>
+              <description>CK8M_D256_OUT divider. 00: div128  01: div256  10: div512  11: div1024.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <name>CK8M_DIV</name>
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>DIV128</name>
+                  <description>DIV128</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV256</name>
+                  <description>DIV256</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV512</name>
+                  <description>DIV512</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>DIV1024</name>
+                  <description>DIV1024</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ENB_CK8M</name>
+              <description>disable CK8M and CK8M_D256_OUT</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_CK8M_DIV</name>
+              <description>1: CK8M_D256_OUT is actually CK8M  0: CK8M_D256_OUT is CK8M divided by 256</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <name>ENB_CK8M_DIV</name>
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>CK8M_DIV_256</name>
+                  <description>CK8M_DIV_256</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CK8M</name>
+                  <description>CK8M</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>DIG_XTAL32K_EN</name>
+              <description>enable CK_XTAL_32K for digital core (no relationship with RTC core)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_D256_EN</name>
+              <description>enable CK8M_D256_OUT for digital core (no relationship with RTC core)</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_EN</name>
+              <description>enable CK8M for digital core (no relationship with RTC core)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DFREQ_FORCE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV_SEL</name>
+              <description>divider = reg_ck8m_div_sel + 1</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_FORCE_NOGATING</name>
+              <description>XTAL force no gating during sleep</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_NOGATING</name>
+              <description>CK8M force no gating during sleep</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DFREQ</name>
+              <description>CK8M_DFREQ</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PD</name>
+              <description>CK8M force power down</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PU</name>
+              <description>CK8M force power up</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOC_CLK_SEL</name>
+              <description>SOC clock sel. 0: XTAL  1: PLL  2: CK8M  3: APLL</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <name>SOC_CLK_SEL</name>
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>XTAL</name>
+                  <description>XTAL</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>PLL</name>
+                  <description>PLL</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CK8M</name>
+                  <description>CK8M</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>APLL</name>
+                  <description>APLL</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>FAST_CLK_RTC_SEL</name>
+              <description>fast_clk_rtc sel. 0: XTAL div 4  1: CK8M</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <name>FAST_CLK_RTC_SEL</name>
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>XTAL_DIV_4</name>
+                  <description>XTAL_DIV_4</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CK8M</name>
+                  <description>CK8M</description>
+                  <value>1</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>ANA_CLK_RTC_SEL</name>
+              <description>slow_clk_rtc sel. 0: SLOW_CK  1: CK_XTAL_32K  2: CK8M_D256_OUT</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <name>ANA_CLK_RTC_SEL</name>
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>SLOW_CK</name>
+                  <description>SLOW_CK</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CK_XTAL_32K</name>
+                  <description>CK_XTAL_32K</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>CK8M_D256_OUT</name>
+                  <description>CK8M_D256_OUT</description>
+                  <value>2</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CONF</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02A00000</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_PD_EN</name>
+              <description>power down SDIO_REG in sleep. Only active when reg_sdio_force = 0</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_FORCE</name>
+              <description>1: use SW option to control SDIO_REG  0: use state machine</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_TIEH</name>
+              <description>SW option for SDIO_TIEH. Only active when reg_sdio_force = 1</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG1P8_READY</name>
+              <description>read only register for REG1P8_READY</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DREFL_SDIO</name>
+              <description>SW option for DREFL_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DREFM_SDIO</name>
+              <description>SW option for DREFM_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DREFH_SDIO</name>
+              <description>SW option for DREFH_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SDIO</name>
+              <description>SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BIAS_CONF</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBG_ATTEN</name>
+              <description>DBG_ATTEN</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_SCK_XTAL</name>
+              <description>ENB_SCK_XTAL</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INC_HEARTBEAT_REFRESH</name>
+              <description>INC_HEARTBEAT_REFRESH</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEC_HEARTBEAT_PERIOD</name>
+              <description>DEC_HEARTBEAT_PERIOD</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INC_HEARTBEAT_PERIOD</name>
+              <description>INC_HEARTBEAT_PERIOD</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEC_HEARTBEAT_WIDTH</name>
+              <description>DEC_HEARTBEAT_WIDTH</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_BIAS_I2C</name>
+              <description>RST_BIAS_I2C</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x29002400</resetValue>
+          <fields>
+            <field>
+              <name>SCK_DCAP_FORCE</name>
+              <description>N/A</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_DBIAS_SLP</name>
+              <description>DIG_REG_DBIAS during sleep</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_DBIAS_WAK</name>
+              <description>DIG_REG_DBIAS during wakeup</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCK_DCAP</name>
+              <description>SCK_DCAP</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBIAS_SLP</name>
+              <description>RTC_DBIAS during sleep</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBIAS_WAK</name>
+              <description>RTC_DBIAS during wakeup</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBOOST_FORCE_PD</name>
+              <description>RTC_DBOOST force power down</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBOOST_FORCE_PU</name>
+              <description>RTC_DBOOST force power up</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_PD</name>
+              <description>RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_PU</name>
+              <description>RTC_REG force power up</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWC</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00012925</resetValue>
+          <fields>
+            <field>
+              <name>FASTMEM_FORCE_NOISO</name>
+              <description>Fast RTC memory force no ISO</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_ISO</name>
+              <description>Fast RTC memory force ISO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_NOISO</name>
+              <description>RTC memory force no ISO</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_ISO</name>
+              <description>RTC memory force ISO</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_ISO</name>
+              <description>rtc_peri force ISO</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_NOISO</name>
+              <description>rtc_peri force no ISO</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FOLW_CPU</name>
+              <description>1: Fast RTC memory PD following CPU  0: fast RTC memory PD following RTC state machine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_LPD</name>
+              <description>Fast RTC memory force PD</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_LPU</name>
+              <description>Fast RTC memory force no PD</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FOLW_CPU</name>
+              <description>1: RTC memory  PD following CPU  0: RTC memory PD following RTC state machine</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_LPD</name>
+              <description>RTC memory force PD</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_LPU</name>
+              <description>RTC memory force no PD</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_PD</name>
+              <description>Fast RTC memory force power down</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_PU</name>
+              <description>Fast RTC memory force power up</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_PD_EN</name>
+              <description>enable power down fast RTC memory in sleep</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_PD</name>
+              <description>RTC memory force power down</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_PU</name>
+              <description>RTC memory force power up</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_PD_EN</name>
+              <description>enable power down RTC memory in sleep</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_PD</name>
+              <description>rtc_peri force power down</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_PU</name>
+              <description>rtc_peri force power up</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_EN</name>
+              <description>enable power down rtc_peri in sleep</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PWC</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00155550</resetValue>
+          <fields>
+            <field>
+              <name>LSLP_MEM_FORCE_PD</name>
+              <description>memories in digital core force PD in sleep</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSLP_MEM_FORCE_PU</name>
+              <description>memories in digital core force no PD in sleep</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_FORCE_PD</name>
+              <description>ROM force power down</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_FORCE_PU</name>
+              <description>ROM force power up</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_FORCE_PD</name>
+              <description>internal SRAM 0 force power down</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_FORCE_PU</name>
+              <description>internal SRAM 0 force power up</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_FORCE_PD</name>
+              <description>internal SRAM 1 force power down</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_FORCE_PU</name>
+              <description>internal SRAM 1 force power up</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_FORCE_PD</name>
+              <description>internal SRAM 2 force power down</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_FORCE_PU</name>
+              <description>internal SRAM 2 force power up</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_FORCE_PD</name>
+              <description>internal SRAM 3 force power down</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_FORCE_PU</name>
+              <description>internal SRAM 3 force power up</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_FORCE_PD</name>
+              <description>internal SRAM 4 force power down</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_FORCE_PU</name>
+              <description>internal SRAM 4 force power up</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_PD</name>
+              <description>wifi force power down</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_PU</name>
+              <description>wifi force power up</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PD</name>
+              <description>digital core force power down</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PU</name>
+              <description>digital core force power up</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_PD_EN</name>
+              <description>enable power down ROM in sleep</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_PD_EN</name>
+              <description>enable power down internal SRAM 0 in sleep</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_PD_EN</name>
+              <description>enable power down internal SRAM 1 in sleep</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_PD_EN</name>
+              <description>enable power down internal SRAM 2 in sleep</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_PD_EN</name>
+              <description>enable power down internal SRAM 3 in sleep</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_PD_EN</name>
+              <description>enable power down internal SRAM 4 in sleep</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_PD_EN</name>
+              <description>enable power down wifi in sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_PD_EN</name>
+              <description>enable power down digital core in sleep</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_ISO</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xAAAA5000</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_OFF</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_ON</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD</name>
+              <description>read only register to indicate digital pad auto-hold status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLR_DG_PAD_AUTOHOLD</name>
+              <description>wtite only register to clear digital pad auto-hold</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD_EN</name>
+              <description>digital pad enable auto-hold</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_NOISO</name>
+              <description>digital pad force no ISO</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_ISO</name>
+              <description>digital pad force ISO</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_UNHOLD</name>
+              <description>digital pad force un-hold</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_HOLD</name>
+              <description>digital pad force hold</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_FORCE_ISO</name>
+              <description>ROM force ISO</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_FORCE_NOISO</name>
+              <description>ROM force no ISO</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_FORCE_ISO</name>
+              <description>internal SRAM 0 force ISO</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_FORCE_NOISO</name>
+              <description>internal SRAM 0 force no ISO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_FORCE_ISO</name>
+              <description>internal SRAM 1 force ISO</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_FORCE_NOISO</name>
+              <description>internal SRAM 1 force no ISO</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_FORCE_ISO</name>
+              <description>internal SRAM 2 force ISO</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_FORCE_NOISO</name>
+              <description>internal SRAM 2 force no ISO</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_FORCE_ISO</name>
+              <description>internal SRAM 3 force ISO</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_FORCE_NOISO</name>
+              <description>internal SRAM 3 force no ISO</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_FORCE_ISO</name>
+              <description>internal SRAM 4 force ISO</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_FORCE_NOISO</name>
+              <description>internal SRAM 4 force no ISO</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_ISO</name>
+              <description>wifi force ISO</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_NOISO</name>
+              <description>wifi force no ISO</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_ISO</name>
+              <description>digital core force ISO</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NOISO</name>
+              <description>digital core force no ISO</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004C80</resetValue>
+          <fields>
+            <field>
+              <name>WDT_PAUSE_IN_SLP</name>
+              <description>pause WDT in sleep</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>enable WDT reset APP CPU</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>enable WDT reset PRO CPU</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>enable WDT in flash boot</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>system reset counter length</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>CPU reset counter length</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_LEVEL_INT_EN</name>
+              <description>N/A</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EDGE_INT_EN</name>
+              <description>N/A</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>enable RTC WDT</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001F400</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013880</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEST_MUX</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENT_RTC</name>
+              <description>ENT_RTC</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEST_RTC</name>
+              <description>DTEST_RTC</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SW_CPU_STALL</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_STALL_APPCPU_C1</name>
+              <description>{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STALL_PROCPU_C1</name>
+              <description>{reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE4</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH4</name>
+              <description>32-bit general purpose retention register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE5</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH5</name>
+              <description>32-bit general purpose retention register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE6</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH6</name>
+              <description>32-bit general purpose retention register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE7</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH7</name>
+              <description>32-bit general purpose retention register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOW_POWER_ST</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOW_POWER_DIAG0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RDY_FOR_WAKEUP</name>
+              <description>1 if RTC controller is ready to execute WAKE instruction, 0 otherwise </description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIAG1</name>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOW_POWER_DIAG1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOLD_FORCE</name>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC1_HOLD_FORCE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_HOLD_FORCE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_HOLD_FORCE</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_HOLD_FORCE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE1_HOLD_FORCE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE2_HOLD_FORCE</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE3_HOLD_FORCE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE4_HOLD_FORCE</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_HOLD_FORCE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD1_HOLD_FORCE</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD2_HOLD_FORCE</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD3_HOLD_FORCE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD4_HOLD_FORCE</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD5_HOLD_FORCE</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD6_HOLD_FORCE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD7_HOLD_FORCE</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_HOLD_FORCE</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_HOLD_FORCE</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP1</name>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Bitmap to select RTC pads for ext wakeup1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STATUS_CLR</name>
+              <description>clear ext wakeup1 status</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP1_STATUS</name>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_WAKEUP1_STATUS</name>
+              <description>ext wakeup1 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BROWN_OUT</name>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x13FF0000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_MEM_PID_CONF</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_START</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_ADDR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLOSE_FLASH_ENA</name>
+              <description>enable close flash when brown out happens</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_RF_ENA</name>
+              <description>enable power down RF when brown out happens</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_WAIT</name>
+              <description>brown out reset wait cycles</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_LEN</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_ENA</name>
+              <description>enable brown out reset</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBROWN_OUT_THRES</name>
+              <description>brown out threshold</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENA</name>
+              <description>enable brown out</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET</name>
+              <description>brown out detect</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_FINISH</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01604280</resetValue>
+          <fields>
+            <field>
+              <name>CNTL_DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTCIO</name>
+      <description>Peripheral RTCIO</description>
+      <groupName>RTC_GPIO</groupName>
+      <baseAddress>0x3FF48400</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xCC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>OUT</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO0~17 output value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TS</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DATA_W1TS</name>
+              <description>GPIO0~17 output value write 1 to set</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TC</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DATA_W1TC</name>
+              <description>GPIO0~17 output value write 1 to clear</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>GPIO0~17 output enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TS</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TS</name>
+              <description>GPIO0~17 output enable write 1 to set</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TC</name>
+              <description>GPIO0~17 output enable write 1 to clear</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT</name>
+              <description>GPIO0~17 interrupt status</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TS</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INT_W1TS</name>
+              <description>GPIO0~17 interrupt status write 1 to set</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TC</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INT_W1TC</name>
+              <description>GPIO0~17 interrupt status write 1 to clear</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>NEXT</name>
+              <description>GPIO0~17 input value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>18</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-17</dimIndex>
+          <name>PIN%s</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>if set to 0: normal output  if set to 1: open drain</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TYPE</name>
+              <description>if set to 0: GPIO interrupt disable  if set to 1: rising edge trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENABLE</name>
+              <description>GPIO wake up enable  only available in light sleep</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_DEBUG_SEL</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DEBUG_SEL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL2</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL4</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_12M_NO_GATING</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PAD_HOLD</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIG_PAD_HOLD</name>
+              <description>select the digital pad hold value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HALL_SENS</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HALL_PHASE</name>
+              <description>Reverse phase of hall sensor</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_HALL</name>
+              <description>Power on hall sensor and connect to VP and VN</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SENSOR_PADS</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SENSE4_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE4_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE4_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE4_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE3_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE3_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE3_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE3_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE2_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE2_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE2_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE2_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE1_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE1_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE1_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE1_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE4_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE3_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE2_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE1_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE4_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE3_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE2_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SENSE1_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADC_PAD</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC2_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_DAC1</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>PDAC1_DAC_XPD_FORCE</name>
+              <description>Power on DAC1. Usually  we need to tristate PDAC1 if we power on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_XPD_DAC</name>
+              <description>Power on DAC1. Usually  we need to tristate PDAC1 if we power on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_DAC</name>
+              <description>PAD DAC1 control code.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_DAC2</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>PDAC2_DAC_XPD_FORCE</name>
+              <description>Power on DAC2. Usually  we need to tristate PDAC2 if we power on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_XPD_DAC</name>
+              <description>Power on DAC2. Usually  we need to tristate PDAC1 if we power on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_DAC</name>
+              <description>PAD DAC2 control code.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL_32K_PAD</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x84100010</resetValue>
+          <fields>
+            <field>
+              <name>DBIAS_XTAL_32K</name>
+              <description>32K XTAL self-bias reference control.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRES_XTAL_32K</name>
+              <description>32K XTAL resistor bias control.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_XTAL_32K</name>
+              <description>Power up 32kHz crystal oscillator</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_XTAL_32K</name>
+              <description>32K XTAL bias current DAC.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_CFG</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x66000000</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_DCUR</name>
+              <description>touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP  this setting is available</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DRANGE</name>
+              <description>touch sensor saw wave voltage range.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DREFL</name>
+              <description>touch sensor saw wave bottom voltage.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DREFH</name>
+              <description>touch sensor saw wave top voltage.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_XPD_BIAS</name>
+              <description>touch sensor bias power on.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD0</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x52000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD1</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x4A000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD2</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x52000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD3</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x4A000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD4</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x52000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD5</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x52000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD6</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x4A000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD7</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x42000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>the input enable of the pad</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>the output enable of the pad in sleep status</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>the input enable of the pad in sleep status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>the sleep status selection signal of the pad</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>the functional selection signal of the pad</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>Ò1Ó select the digital function  Ó0Óslection the rtc function</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>the pull up enable of the pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>the pull down enable of the pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>the driver strength of the pad</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD</name>
+              <description>hold the current value of the output when setting the hold to Ò1Ó</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD8</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD9</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02000000</resetValue>
+          <fields>
+            <field>
+              <name>TO_GPIO</name>
+              <description>connect the rtc pad input to digital pad input Ó0Ó is availbale</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>default touch sensor tie option. 0: tie low  1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC</name>
+              <description>touch sensor slope control. 3-bit for each touch panel  default 100.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP0</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTL_EXT_CTR</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_I2C_IO</name>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_DEBUG_BIT_SEL</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SCL_SEL</name>
+              <description>Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SDA_SEL</name>
+              <description>Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01603160</resetValue>
+          <fields>
+            <field>
+              <name>IO_DATE</name>
+              <description>date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC_I2C</name>
+      <description>Peripheral RTC_I2C</description>
+      <groupName>RTC_I2C</groupName>
+      <baseAddress>0x3FF48C00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x3C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCL_LOW_PERIOD</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_LOW_PERIOD</name>
+              <description>number of cycles that scl == 0 </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>SDA is push-pull (1) or open-drain (0) </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>SCL is push-pull (1) or open-drain (0) </description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>Master (1) or slave (0) </description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>Force to generate start condition </description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>Send LSB first </description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>Receive LSB first </description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEBUG_STATUS</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ACK_VAL</name>
+              <description>The value of an acknowledge signal on the bus </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_RW</name>
+              <description>When working as a slave, the value of R/W bit received </description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMED_OUT</name>
+              <description>Transfer has timed out </description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>When working as a master, lost control of I2C bus </description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>operation is in progress </description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDR_MATCH</name>
+              <description>When working as a slave, whether address was matched </description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS</name>
+              <description>8 bit transmit done </description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE</name>
+              <description>state of the main state machine </description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_STATE</name>
+              <description>state of SCL state machine </description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMEOUT</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMEOUT</name>
+              <description>Maximum number of FAST_CLK cycles that the transmission can take </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_ADDR</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_ADDR</name>
+              <description>local slave address </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>_10BIT</name>
+              <description>Set if local slave address is 10-bit </description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRANS_COMPLETE_INT_RAW</name>
+              <description>Slave accepted 1 byte and address matched </description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>Master lost arbitration </description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_TRANS_COMPLETE_INT_RAW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>Stop condition has been detected interrupt raw status </description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>time out interrupt raw status </description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRANS_COMPLETE_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_TRANS_COMPLETE_INT_CLR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_EN</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>SDA_DUTY</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDA_DUTY</name>
+              <description>Number of FAST_CLK cycles SDA will switch after falling edge of SCL </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH_PERIOD</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_HIGH_PERIOD</name>
+              <description>Number of FAST_CLK cycles for SCL to be high </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_PERIOD</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_START_PERIOD</name>
+              <description>Number of FAST_CLK cycles to wait before generating start condition </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_PERIOD</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_STOP_PERIOD</name>
+              <description>Number of FAST_CLK cycles to wait before generating stop condition </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>VAL</name>
+              <description>Command content </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DONE</name>
+              <description>Bit is set by HW when command is done </description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SDMMC</name>
+      <description>SD/MMC Host Controller</description>
+      <groupName>SDHOST</groupName>
+      <baseAddress>0x3FF68000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>Control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTROLLER_RESET</name>
+              <description>To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_RESET</name>
+              <description>To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation.
+Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RESET</name>
+              <description>To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_ENABLE</name>
+              <description>Global interrupt enable/disable bit. 0: Disable; 1: Enable.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>READ_WAIT</name>
+              <description>For sending read-wait to SDIO cards.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_IRQ_RESPONSE</name>
+              <description>Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ABORT_READ_DATA</name>
+              <description>After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_CCSD</name>
+              <description>When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit  in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked.
+NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_AUTO_STOP_CCSD</name>
+              <description>Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the  SDHOST_SEND_AUTO_STOP_CCSD bit.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CEATA_DEVICE_INTERRUPT_STATUS</name>
+              <description>Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV</name>
+          <description>Clock divider configuration register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_DIVIDER0</name>
+              <description>Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DIVIDER1</name>
+              <description>Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DIVIDER2</name>
+              <description>Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DIVIDER3</name>
+              <description>Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKSRC</name>
+          <description>Clock source selection register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLKSRC</name>
+              <description>Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value.
+00 : Clock divider 0;
+01 : Clock divider 1;
+10 : Clock divider 2;
+11 : Clock divider 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKENA</name>
+          <description>Clock enable register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CCLK_ENABLE</name>
+              <description>Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card.
+0: Clock disabled;
+1: Clock enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_ENABLE</name>
+              <description>Disable clock when the card is in IDLE state. One bit per card.
+0: clock disabled;
+1: clock enabled.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TMOUT</name>
+          <description>Data and response timeout configuration register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFF40</resetValue>
+          <fields>
+            <field>
+              <name>RESPONSE_TIMEOUT</name>
+              <description>Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_TIMEOUT</name>
+              <description>Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card.
+NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTYPE</name>
+          <description>Card bus width configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARD_WIDTH4</name>
+              <description>One bit per card indicates if card is 1-bit or 4-bit mode.
+0: 1-bit mode;
+1: 4-bit mode.
+Bit[1:0] correspond to card[1:0] respectively.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARD_WIDTH8</name>
+              <description>One bit per card indicates if card is in 8-bit mode.
+0: Non 8-bit mode;
+1: 8-bit mode.
+Bit[17:16] correspond to card[1:0] respectively.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLKSIZ</name>
+          <description>Card data block size configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>BLOCK_SIZE</name>
+              <description>Block size.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BYTCNT</name>
+          <description>Data transfer length configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>BYTE_COUNT</name>
+              <description>Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTMASK</name>
+          <description>SDIO interrupt mask register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_MASK</name>
+              <description>These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt.
+Bit 15 (EBE): End-bit error/no CRC error;
+Bit 14 (ACD): Auto command done;
+Bit 13 (SBE/BCI): Rx Start Bit Error;
+Bit 12 (HLE): Hardware locked write error;
+Bit 11 (FRUN): FIFO underrun/overrun error;
+Bit 10 (HTO): Data starvation-by-host timeout;
+Bit 9 (DRTO): Data read timeout;
+Bit 8 (RTO): Response timeout;
+Bit 7 (DCRC): Data CRC error;
+Bit 6 (RCRC): Response CRC error;
+Bit 5 (RXDR): Receive FIFO data request;
+Bit 4 (TXDR): Transmit FIFO data request;
+Bit 3 (DTO): Data transfer over;
+Bit 2 (CD): Command done;
+Bit 1 (RE): Response error;
+Bit 0 (CD): Card detect.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_INT_MASK</name>
+              <description>SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMDARG</name>
+          <description>Command argument data register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMDARG</name>
+              <description>Value indicates command argument to be passed to the card.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>Command and boot configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20000000</resetValue>
+          <fields>
+            <field>
+              <name>INDEX</name>
+              <description>Command index.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESPONSE_EXPECT</name>
+              <description>0: No response expected from card; 1: Response expected from card.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESPONSE_LENGTH</name>
+              <description>0: Short response expected from card; 1: Long response expected from card.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_RESPONSE_CRC</name>
+              <description>0: Do not check; 1: Check response CRC.
+Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_EXPECTED</name>
+              <description>0: No data transfer expected; 1: Data transfer expected.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>READ_WRITE</name>
+              <description>0: Read from card; 1: Write to card.
+Don't care if no data is expected from card.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANSFER_MODE</name>
+              <description>Block data transfer command; 1: Stream data transfer command.
+Don't care if no data expected.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_AUTO_STOP</name>
+              <description>0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_PRVDATA_COMPLETE</name>
+              <description>0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command.
+The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOP_ABORT_CMD</name>
+              <description>0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress.
+When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_INITIALIZATION</name>
+              <description>0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command.
+After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARD_NUMBER</name>
+              <description>Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UPDATE_CLOCK_REGISTERS_ONLY</name>
+              <description>0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain.
+Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA.
+Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>READ_CEATA_DEVICE</name>
+              <description>Read access flag.
+0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;
+1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.
+Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CCS_EXPECTED</name>
+              <description>Expected Command Completion Signal (CCS) configuration.
+0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device;
+1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device.
+If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USE_HOLE</name>
+              <description>Use Hold Register.
+0: CMD and DATA sent to card bypassing HOLD Register;
+1: CMD and DATA sent to card through the HOLD Register.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START_CMD</name>
+              <description>Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESP0</name>
+          <description>Response data register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RESPONSE0</name>
+              <description>Bit[31:0] of response.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESP1</name>
+          <description>Long response data register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RESPONSE1</name>
+              <description>Bit[63:32] of long response.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESP2</name>
+          <description>Long response data register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RESPONSE2</name>
+              <description>Bit[95:64] of long response.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESP3</name>
+          <description>Long response data register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RESPONSE3</name>
+              <description>Bit[127:96] of long response.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MINTSTS</name>
+          <description>Masked interrupt status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_STATUS_MSK</name>
+              <description>Interrupt enabled only if corresponding bit in interrupt mask register is set.
+Bit 15 (EBE): End-bit error/no CRC error;
+Bit 14 (ACD): Auto command done;
+Bit 13 (SBE/BCI): RX Start Bit Error;
+Bit 12 (HLE): Hardware locked write error;
+Bit 11 (FRUN): FIFO underrun/overrun error;
+Bit 10 (HTO): Data starvation by host timeout (HTO);
+Bit 9 (DTRO): Data read timeout;
+Bit 8 (RTO): Response timeout;
+Bit 7 (DCRC): Data CRC error;
+Bit 6 (RCRC): Response CRC error;
+Bit 5 (RXDR): Receive FIFO data request;
+Bit 4 (TXDR): Transmit FIFO data request;
+Bit 3 (DTO): Data transfer over;
+Bit 2 (CD): Command done;
+Bit 1 (RE): Response error;
+Bit 0 (CD): Card detect.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_INTERRUPT_MSK</name>
+              <description>Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt).</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RINTSTS</name>
+          <description>Raw interrupt status register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_STATUS_RAW</name>
+              <description>Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status.
+Bit 15 (EBE): End-bit error/no CRC error;
+Bit 14 (ACD): Auto command done;
+Bit 13 (SBE/BCI): RX Start Bit Error;
+Bit 12 (HLE): Hardware locked write error;
+Bit 11 (FRUN): FIFO underrun/overrun error;
+Bit 10 (HTO): Data starvation by host timeout (HTO);
+Bit 9 (DTRO): Data read timeout;
+Bit 8 (RTO): Response timeout;
+Bit 7 (DCRC): Data CRC error;
+Bit 6 (RCRC): Response CRC error;
+Bit 5 (RXDR): Receive FIFO data request;
+Bit 4 (TXDR): Transmit FIFO data request;
+Bit 3 (DTO): Data transfer over;
+Bit 2 (CD): Command done;
+Bit 1 (RE): Response error;
+Bit 0 (CD): Card detect.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_INTERRUPT_RAW</name>
+              <description>Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect.
+0: No SDIO interrupt from card;
+1: SDIO interrupt from card.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>SD/MMC status register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000716</resetValue>
+          <fields>
+            <field>
+              <name>FIFO_RX_WATERMARK</name>
+              <description>FIFO reached Receive watermark level, not qualified with data transfer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FIFO_TX_WATERMARK</name>
+              <description>FIFO reached Transmit watermark level, not qualified with data transfer.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FIFO_EMPTY</name>
+              <description>FIFO is empty status.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FIFO_FULL</name>
+              <description>FIFO is full status.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COMMAND_FSM_STATES</name>
+              <description>Command FSM states.
+0: Idle;
+1: Send init sequence;
+2: Send cmd start bit;
+3: Send cmd tx bit;
+4: Send cmd index + arg;
+5: Send cmd crc7;
+6: Send cmd end bit;
+7: Receive resp start bit;
+8: Receive resp IRQ response;
+9: Receive resp tx bit;
+10: Receive resp cmd idx;
+11: Receive resp data;
+12: Receive resp crc7;
+13: Receive resp end bit;
+14: Cmd path wait NCC;
+15: Wait, cmd-to-response turnaround.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DATA_3_STATUS</name>
+              <description>Raw selected sdhost_card_data[3], checks whether card is present.
+0: card not present;
+1: card present.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DATA_BUSY</name>
+              <description>Inverted version of raw selected sdhost_card_data[0].
+0: Card data not busy;
+1: Card data busy.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DATA_STATE_MC_BUSY</name>
+              <description>Data transmit or receive state-machine is busy.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESPONSE_INDEX</name>
+              <description>Index of previous response, including any auto-stop sent by core.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FIFO_COUNT</name>
+              <description>FIFO count, number of filled locations in FIFO.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFOTH</name>
+          <description>FIFO configuration register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_WMARK</name>
+              <description>FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt  occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty).  In DMA mode, at end of packet, if last transfer is less than burst  size, DMA controller does single cycles until required bytes are  transferred.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WMARK</name>
+              <description>FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_MULTIPLE_TRANSACTION_SIZE</name>
+              <description>Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE.
+000: 1-byte transfer;
+001: 4-byte transfer;
+010: 8-byte transfer;
+011: 16-byte transfer;
+100: 32-byte transfer;
+101: 64-byte transfer;
+110: 128-byte transfer;
+111: 256-byte transfer.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CDETECT</name>
+          <description>Card detect register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARD_DETECT_N</name>
+              <description>Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WRTPRT</name>
+          <description>Card write protection (WP) status register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WRITE_PROTECT</name>
+              <description>Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TCBCNT</name>
+          <description>Transferred byte count register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TCBCNT</name>
+              <description>Number of bytes transferred by CIU unit to card.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TBBCNT</name>
+          <description>Transferred byte count register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TBBCNT</name>
+              <description>Number of bytes transferred between Host/DMA memory and BIU FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEBNCE</name>
+          <description>Debounce filter time configuration register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DEBOUNCE_COUNT</name>
+              <description>Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted or removed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USRID</name>
+          <description>User ID (scratchpad) register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USRID</name>
+              <description>User identification register, value set by user. Can also be used as a scratchpad register by user.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VERID</name>
+          <description>Version ID (scratchpad) register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5432270A</resetValue>
+          <fields>
+            <field>
+              <name>VERSIONID</name>
+              <description>Hardware version register. Can also be read by fireware.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCON</name>
+          <description>Hardware feature register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03444CC3</resetValue>
+          <fields>
+            <field>
+              <name>CARD_TYPE</name>
+              <description>Hardware support SDIO and MMC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CARD_NUM</name>
+              <description>Support card number is 2.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_TYPE</name>
+              <description>Register config is APB bus.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DATA_WIDTH</name>
+              <description>Regisger data widht is 32.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDR_WIDTH</name>
+              <description>Register address width is 32.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_WIDTH</name>
+              <description>DMA data witdth is 32.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RAM_INDISE</name>
+              <description>Inside RAM in SDMMC module.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOLD</name>
+              <description>Have a hold regiser in data path .</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NUM_CLK_DIV</name>
+              <description>Have 4 clk divider in design .</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UHS</name>
+          <description>UHS-1 register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DDR</name>
+              <description>DDR mode selecton,1 bit for each card.
+0-Non-DDR mdoe.
+1-DDR mdoe.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RST_N</name>
+          <description>Card reset register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CARD_RESET</name>
+              <description>Hardware reset.
+1: Active mode;
+0: Reset.
+These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BMOD</name>
+          <description>Burst mode transfer configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SWR</name>
+              <description>Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FB</name>
+              <description>Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DE</name>
+              <description>IDMAC Enable. When set, the IDMAC is enabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBL</name>
+              <description>Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows:
+000: 1-byte transfer;
+001: 4-byte transfer;
+010: 8-byte transfer;
+011: 16-byte transfer;
+100: 32-byte transfer;
+101: 64-byte transfer;
+110: 128-byte transfer;
+111: 256-byte transfer.
+PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PLDMND</name>
+          <description>Poll demand configuration register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PD</name>
+              <description>Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only .</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBADDR</name>
+          <description>Descriptor base address register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBADDR</name>
+              <description>Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDSTS</name>
+          <description>IDMAC status register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TI</name>
+              <description>Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RI</name>
+              <description>Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FBE</name>
+              <description>Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DU</name>
+              <description>Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CES</name>
+              <description>Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits:
+EBE : End Bit Error;
+RTO : Response Timeout/Boot Ack Timeout;
+RCRC : Response CRC;
+SBE : Start Bit Error;
+DRTO : Data Read Timeout/BDS timeout;
+DCRC : Data CRC for Receive;
+RE : Response Error.
+Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NIS</name>
+              <description>Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AIS</name>
+              <description>Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FBE_CODE</name>
+              <description>Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt.
+001: Host Abort received during transmission;
+010: Host Abort received during reception;
+Others: Reserved.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FSM</name>
+              <description>DMAC FSM present state.
+0: DMA_IDLE (idle state);
+1: DMA_SUSPEND (suspend state);
+2: DESC_RD (descriptor reading state);
+3: DESC_CHK (descriptor checking state);
+4: DMA_RD_REQ_WAIT (read-data request waiting state);
+5: DMA_WR_REQ_WAIT (write-data request waiting state);
+6: DMA_RD (data-read state);
+7: DMA_WR (data-write state);
+8: DESC_CLOSE (descriptor close state).</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDINTEN</name>
+          <description>IDMAC interrupt enable register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TI</name>
+              <description>Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RI</name>
+              <description>Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FBE</name>
+              <description>Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DU</name>
+              <description>Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CES</name>
+              <description>Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NI</name>
+              <description>Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits:
+IDINTEN[0]: Transmit Interrupt;
+IDINTEN[1]: Receive Interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AI</name>
+              <description>Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits:
+IDINTEN[2]: Fatal Bus Error Interrupt;
+IDINTEN[4]: DU Interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DSCADDR</name>
+          <description>Host descriptor address pointer</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DSCADDR</name>
+              <description>Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUFADDR</name>
+          <description>Host buffer address pointer register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUFADDR</name>
+              <description>Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CARDTHRCTL</name>
+          <description>Card Threshold Control register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARDRDTHREN</name>
+              <description>Card read threshold enable.
+1'b0-Card read threshold disabled.
+1'b1-Card read threshold enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARDCLRINTEN</name>
+              <description>Busy clear interrupt generation:
+1'b0-Busy clear interrypt disabled.
+1'b1-Busy clear interrypt enabled.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARDWRTHREN</name>
+              <description>Applicable when HS400 mode is enabled.
+1'b0-Card write Threshold disabled.
+1'b1-Card write Threshold enabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARDTHRESHOLD</name>
+              <description>The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EMMCDDR</name>
+          <description>eMMC DDR register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HALFSTARTBIT</name>
+              <description>Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be:
+1'b0-Full cycle.
+1'b1-less than one full cycle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HS400_MODE</name>
+              <description>Set 1 to enable HS400 mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENSHIFT</name>
+          <description>Enable Phase Shift register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_SHIFT</name>
+              <description>Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card.
+2'b00-Default phase shift.
+2'b01-Enables shifted to next immediate positive edge.
+2'b10-Enables shifted to next immediate negative edge.
+2'b11-Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUFFIFO</name>
+          <description>CPU write and read transmit data by FIFO</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUFFIFO</name>
+              <description>CPU write and read transmit data by FIFO. This register points to the current Data FIFO .</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_EDGE_SEL</name>
+          <description>SDIO control register.</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00820200</resetValue>
+          <fields>
+            <field>
+              <name>CCLKIN_EDGE_DRV_SEL</name>
+              <description>It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CCLKIN_EDGE_SAM_SEL</name>
+              <description>It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CCLKIN_EDGE_SLF_SEL</name>
+              <description>It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CCLLKIN_EDGE_H</name>
+              <description>The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CCLLKIN_EDGE_L</name>
+              <description>The low level of the divider clock. The value should be  larger than CCLKIN_EDGE_H.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CCLLKIN_EDGE_N</name>
+              <description>The value should be equal to CCLKIN_EDGE_L.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESDIO_MODE</name>
+              <description>Enable esdio mode.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESD_MODE</name>
+              <description>Enable esd mode.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CCLK_EN</name>
+              <description>Sdio clock enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SENS</name>
+      <description>Peripheral SENS</description>
+      <groupName>SENS</groupName>
+      <baseAddress>0x3FF48800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SAR_READ_CTRL</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00070902</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_CLK_DIV</name>
+              <description>clock divider</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_SAMPLE_CYCLE</name>
+              <description>sample cycles for SAR ADC1</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_SAMPLE_BIT</name>
+              <description>00: for 9-bit width  01: for 10-bit width  10: for 11-bit width  11: for 12-bit width</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_CLK_GATED</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_SAMPLE_NUM</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_DIG_FORCE</name>
+              <description>1: SAR ADC1 controlled by DIG ADC1 CTRL  0: SAR ADC1 controlled by RTC ADC1 CTRL</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_DATA_INV</name>
+              <description>Invert SAR ADC1 data</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_READ_STATUS1</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR1_READER_STATUS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS_WAIT1</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A000A</resetValue>
+          <fields>
+            <field>
+              <name>SAR_AMP_WAIT1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_WAIT2</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS_WAIT2</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0020000A</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_XPD_SAR_SW</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_WAIT3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XPD_AMP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XPD_SAR</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_RSTB_WAIT</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS_CTRL</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0707338F</resetValue>
+          <fields>
+            <field>
+              <name>XPD_SAR_AMP_FSM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_RST_FB_FSM</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_FSM</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_GND_FSM</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SAR_FSM</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_RSTB_FSM</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_XPD_WAIT</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_READ_STATUS2</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR2_READER_STATUS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_SLEEP_CYC0</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000C8</resetValue>
+          <fields>
+            <field>
+              <name>SLEEP_CYCLES_S0</name>
+              <description>sleep cycles for ULP-coprocessor timer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_SLEEP_CYC1</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000064</resetValue>
+          <fields>
+            <field>
+              <name>SLEEP_CYCLES_S1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_SLEEP_CYC2</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000032</resetValue>
+          <fields>
+            <field>
+              <name>SLEEP_CYCLES_S2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_SLEEP_CYC3</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000028</resetValue>
+          <fields>
+            <field>
+              <name>SLEEP_CYCLES_S3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_SLEEP_CYC4</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000014</resetValue>
+          <fields>
+            <field>
+              <name>SLEEP_CYCLES_S4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_START_FORCE</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_BIT_WIDTH</name>
+              <description>00: 9 bit  01: 10 bits  10: 11bits  11: 12bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_BIT_WIDTH</name>
+              <description>00: 9 bit  01: 10 bits  10: 11bits  11: 12bits</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_EN_TEST</name>
+              <description>SAR2_EN_TEST  only active when reg_sar2_dig_force = 0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_PWDET_CCT</name>
+              <description>SAR2_PWDET_CCT  PA power detector capacitance tuning.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_FORCE_START_TOP</name>
+              <description>1: ULP-coprocessor is started by SW  0: ULP-coprocessor is started by timer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_START_TOP</name>
+              <description>Write 1 to start ULP-coprocessor  only active when reg_ulp_cp_force_start_top = 1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARCLK_EN</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PC_INIT</name>
+              <description>initialized PC for ULP-coprocessor</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_STOP</name>
+              <description>stop SAR ADC2 conversion</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_STOP</name>
+              <description>stop SAR ADC1 conversion</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_PWDET_EN</name>
+              <description>N/A</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEM_WR_CTRL</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00100200</resetValue>
+          <fields>
+            <field>
+              <name>MEM_WR_ADDR_INIT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_WR_ADDR_SIZE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_WR_OFFST_CLR</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_ATTEN1</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_ATTEN</name>
+              <description>2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_ATTEN2</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SAR2_ATTEN</name>
+              <description>2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR1</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SLAVE_ADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SLAVE_ADDR0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEAS_STATUS</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR2</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SLAVE_ADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SLAVE_ADDR2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR3</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SLAVE_ADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SLAVE_ADDR4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_OUT</name>
+              <description>temperature sensor data out</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_RDY_OUT</name>
+              <description>indicate temperature sensor out ready</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR4</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SLAVE_ADDR7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SLAVE_ADDR6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RDATA</name>
+              <description>I2C read data</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_DONE</name>
+              <description>indicate I2C done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TSENS_CTRL</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00066002</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_XPD_WAIT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_XPD_FORCE</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_INV</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_GATED</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_IN_INV</name>
+              <description>invert temperature sensor data</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_DIV</name>
+              <description>temperature sensor clock divider</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_POWER_UP</name>
+              <description>temperature sensor power up</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_POWER_UP_FORCE</name>
+              <description>1: dump out &amp; power up controlled by SW  0: by FSM</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_DUMP_OUT</name>
+              <description>temperature sensor dump out  only active when reg_tsens_power_up_force = 1</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_I2C_CTRL</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_I2C_CTRL</name>
+              <description>I2C control data  only active when reg_sar_i2c_start_force = 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_START</name>
+              <description>start I2C  only active when reg_sar_i2c_start_force = 1</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_START_FORCE</name>
+              <description>1: I2C started by SW  0: I2C started by FSM</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS_START1</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEAS1_DATA_SAR</name>
+              <description>SAR ADC1 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEAS1_DONE_SAR</name>
+              <description>SAR ADC1 conversion done indication</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEAS1_START_SAR</name>
+              <description>SAR ADC1 controller (in RTC) starts conversion  only active when reg_meas1_start_force = 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEAS1_START_FORCE</name>
+              <description>1: SAR ADC1 controller (in RTC) is started by SW  0: SAR ADC1 controller is started by ULP-coprocessor</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_EN_PAD</name>
+              <description>SAR ADC1 pad enable bitmap  only active when reg_sar1_en_pad_force = 1</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_EN_PAD_FORCE</name>
+              <description>1: SAR ADC1 pad enable bitmap is controlled by SW  0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_CTRL1</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02041000</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_MEAS_DELAY</name>
+              <description>the meas length (in 8MHz)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_XPD_WAIT</name>
+              <description>the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_OUT_SEL</name>
+              <description>1: when the counter is greater then the threshold  the touch pad is considered as "touched"  0: when the counter is less than the threshold  the touch pad is considered as "touched"</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_OUT_1EN</name>
+              <description>1: wakeup interrupt is generated if SET1 is "touched"  0: wakeup interrupt is generated only if SET1 &amp; SET2 is both "touched"</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_HALL_FORCE</name>
+              <description>1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HALL_PHASE_FORCE</name>
+              <description>1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled by FSM in ULP-coprocessor</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES1</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH1</name>
+              <description>the threshold for touch pad 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_OUT_TH0</name>
+              <description>the threshold for touch pad 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES2</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH3</name>
+              <description>the threshold for touch pad 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_OUT_TH2</name>
+              <description>the threshold for touch pad 2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES3</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH5</name>
+              <description>the threshold for touch pad 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_OUT_TH4</name>
+              <description>the threshold for touch pad 4</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES4</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH7</name>
+              <description>the threshold for touch pad 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_OUT_TH6</name>
+              <description>the threshold for touch pad 6</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES5</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH9</name>
+              <description>the threshold for touch pad 9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_OUT_TH8</name>
+              <description>the threshold for touch pad 8</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_OUT1</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_MEAS_OUT1</name>
+              <description>the counter for touch pad 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_OUT0</name>
+              <description>the counter for touch pad 0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_OUT2</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_MEAS_OUT3</name>
+              <description>the counter for touch pad 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_OUT2</name>
+              <description>the counter for touch pad 2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_OUT3</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_MEAS_OUT5</name>
+              <description>the counter for touch pad 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_OUT4</name>
+              <description>the counter for touch pad 4</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_OUT4</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_MEAS_OUT7</name>
+              <description>the counter for touch pad 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_OUT6</name>
+              <description>the counter for touch pad 6</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_OUT5</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_MEAS_OUT9</name>
+              <description>the counter for touch pad 9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_OUT8</name>
+              <description>the counter for touch pad 8</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_CTRL2</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400800</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_MEAS_EN</name>
+              <description>10-bit register to indicate which pads are "touched"</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_DONE</name>
+              <description>fsm set 1 to indicate touch touch meas is done</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_START_FSM_EN</name>
+              <description>1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm  0: TOUCH_START &amp; TOUCH_XPD is controlled by registers</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_START_EN</name>
+              <description>1: start touch fsm  valid when reg_touch_start_force is set</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_START_FORCE</name>
+              <description>1: to start touch fsm by SW  0: to start touch fsm by timer</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLEEP_CYCLES</name>
+              <description>sleep cycles for timer</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_EN_CLR</name>
+              <description>to clear reg_touch_meas_en</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_ENABLE</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3FFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_PAD_WORKEN</name>
+              <description>Bitmap defining the working set during the measurement.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD_OUTEN2</name>
+              <description>Bitmap defining SET2 for generating wakeup interrupt. SET2 is "touched" only if at least one of touch pad in SET2 is "touched".</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD_OUTEN1</name>
+              <description>Bitmap defining SET1 for generating wakeup interrupt. SET1 is "touched" only if at least one of touch pad in SET1 is "touched".</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_READ_CTRL2</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00070902</resetValue>
+          <fields>
+            <field>
+              <name>SAR2_CLK_DIV</name>
+              <description>clock divider</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_SAMPLE_CYCLE</name>
+              <description>sample cycles for SAR ADC2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_SAMPLE_BIT</name>
+              <description>00: for 9-bit width  01: for 10-bit width  10: for 11-bit width  11: for 12-bit width</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_CLK_GATED</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_SAMPLE_NUM</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_PWDET_FORCE</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_DIG_FORCE</name>
+              <description>1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL  0: SAR ADC2 controlled by RTC ADC2 CTRL</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_DATA_INV</name>
+              <description>Invert SAR ADC2 data</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS_START2</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEAS2_DATA_SAR</name>
+              <description>SAR ADC2 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEAS2_DONE_SAR</name>
+              <description>SAR ADC2 conversion done indication</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEAS2_START_SAR</name>
+              <description>SAR ADC2 controller (in RTC) starts conversion  only active when reg_meas2_start_force = 1</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEAS2_START_FORCE</name>
+              <description>1: SAR ADC2 controller (in RTC) is started by SW  0: SAR ADC2 controller is started by ULP-coprocessor</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_EN_PAD</name>
+              <description>SAR ADC2 pad enable bitmap  only active when reg_sar2_en_pad_force = 1</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_EN_PAD_FORCE</name>
+              <description>1: SAR ADC2 pad enable bitmap is controlled by SW  0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_DAC_CTRL1</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_FSTEP</name>
+              <description>frequency step for CW generator  can be used to adjust the frequency</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_TONE_EN</name>
+              <description>1: enable CW generator  0: disable CW generator</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_BIT_SEL</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_DIG_FORCE</name>
+              <description>1: DAC1 &amp; DAC2 use DMA  0: DAC1 &amp; DAC2 do not use DMA</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_FORCE_LOW</name>
+              <description>1: force PDAC_CLK to low</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_FORCE_HIGH</name>
+              <description>1: force PDAC_CLK to high</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_INV</name>
+              <description>1: invert PDAC_CLK</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_DAC_CTRL2</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03000000</resetValue>
+          <fields>
+            <field>
+              <name>DAC_DC1</name>
+              <description>DC offset for DAC1 CW generator</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_DC2</name>
+              <description>DC offset for DAC2 CW generator</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_SCALE1</name>
+              <description>00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_SCALE2</name>
+              <description>00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_INV1</name>
+              <description>00: do not invert any bits  01: invert all bits  10: invert MSB  11: invert all bits except MSB</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_INV2</name>
+              <description>00: do not invert any bits  01: invert all bits  10: invert MSB  11: invert all bits except MSB</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CW_EN1</name>
+              <description>1: to select CW generator as source to PDAC1_DAC[7:0]  0: to select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CW_EN2</name>
+              <description>1: to select CW generator as source to PDAC2_DAC[7:0]  0: to select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS_CTRL2</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_DAC_XPD_FSM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_DAC_XPD_FSM_IDLE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SAR_AMP_FSM_IDLE</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_RST_FB_FSM_IDLE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_FSM_IDLE</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_GND_FSM_IDLE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SAR_FSM_IDLE</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_RSTB_FSM_IDLE</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_RSTB_FORCE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_RST_FB_FORCE</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_FORCE</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_GND_FORCE</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_NOUSE</name>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_NOUSE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SARDATE</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01605180</resetValue>
+          <fields>
+            <field>
+              <name>SAR_DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SHA</name>
+      <description>SHA (Secure Hash Algorithm) Accelerator</description>
+      <groupName>SHA</groupName>
+      <baseAddress>0x3FF03000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xC0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TEXT_%s</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT</name>
+              <description>SHA Message block and hash result register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA1_START</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA1_START</name>
+              <description>Write 1 to start an SHA-1 operation on the first message block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA1_CONTINUE</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA1_CONTINUE</name>
+              <description>Write 1 to continue the SHA-1 operation with subsequent blocks.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA1_LOAD</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA1_LOAD</name>
+              <description>Write 1 to finish the SHA-1 operation to calculate the final message hash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA1_BUSY</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA1_BUSY</name>
+              <description>SHA-1 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA256_START</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA256_START</name>
+              <description>Write 1 to start an SHA-256 operation on the first message block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA256_LOAD</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA256_LOAD</name>
+              <description>Write 1 to finish the SHA-256 operation to calculate the final message hash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA256_CONTINUE</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA256_CONTINUE</name>
+              <description>Write 1 to continue the SHA-256 operation with subsequent blocks.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA256_BUSY</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA256_BUSY</name>
+              <description>SHA-256 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA384_START</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA384_START</name>
+              <description>Write 1 to start an SHA-384 operation on the first message block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA384_CONTINUE</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA384_CONTINUE</name>
+              <description>Write 1 to continue the SHA-384 operation with subsequent blocks.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA384_LOAD</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA384_LOAD</name>
+              <description>Write 1 to finish the SHA-384 operation to calculate the final message hash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA384_BUSY</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA384_BUSY</name>
+              <description>SHA-384 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA512_START</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA512_START</name>
+              <description>Write 1 to start an SHA-512 operation on the first message block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA512_CONTINUE</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA512_CONTINUE</name>
+              <description>Write 1 to continue the SHA-512 operation with subsequent blocks.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA512_LOAD</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA512_LOAD</name>
+              <description>Write 1 to finish the SHA-512 operation to calculate the final message hash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA512_BUSY</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA512_BUSY</name>
+              <description>SHA-512 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SLC</name>
+      <description>Peripheral SLC</description>
+      <groupName>SLC</groupName>
+      <baseAddress>0x3FF58000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x14C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CONF0</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFF3CFF30</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_TX_RST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_RST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_FIFO_RST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_RST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_LOOP_TEST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_LOOP_TEST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_AUTO_WRBACK</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_NO_RESTART_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RXDSCR_BURST_EN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RXDATA_BURST_EN</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RXLINK_AUTO_RET</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TXLINK_AUTO_RET</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TXDSCR_BURST_EN</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TXDATA_BURST_EN</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN_AUTO_CLR</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN_SEL</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_RST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_RST</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_WR_RETRY_MASK_EN</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_WR_RETRY_MASK_EN</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_LOOP_TEST</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_LOOP_TEST</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_AUTO_WRBACK</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_NO_RESTART_CLR</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RXDSCR_BURST_EN</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RXDATA_BURST_EN</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RXLINK_AUTO_RET</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TXLINK_AUTO_RET</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TXDSCR_BURST_EN</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TXDATA_BURST_EN</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN_AUTO_CLR</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN_SEL</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0INT_RAW</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT0_INT_RAW</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT1_INT_RAW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT2_INT_RAW</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT3_INT_RAW</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT4_INT_RAW</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT5_INT_RAW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT6_INT_RAW</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT7_INT_RAW</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_START_INT_RAW</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_START_INT_RAW</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_RAW</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_RAW</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_RAW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_RAW</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DONE_INT_RAW</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_SUC_EOF_INT_RAW</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DONE_INT_RAW</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_EOF_INT_RAW</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_INT_RAW</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_ERR_INT_RAW</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DSCR_ERR_INT_RAW</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_EMPTY_INT_RAW</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_ACK_INT_RAW</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_WR_RETRY_DONE_INT_RAW</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_ERR_EOF_INT_RAW</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMD_DTC_INT_RAW</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_QUICK_EOF_INT_RAW</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0INT_ST</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT0_INT_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT1_INT_ST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT2_INT_ST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT3_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT4_INT_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT5_INT_ST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT6_INT_ST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT7_INT_ST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_START_INT_ST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_START_INT_ST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_ST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_ST</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_ST</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DONE_INT_ST</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_SUC_EOF_INT_ST</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DONE_INT_ST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_EOF_INT_ST</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_INT_ST</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_ERR_INT_ST</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DSCR_ERR_INT_ST</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_EMPTY_INT_ST</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_ACK_INT_ST</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_WR_RETRY_DONE_INT_ST</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_ERR_EOF_INT_ST</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMD_DTC_INT_ST</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_QUICK_EOF_INT_ST</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0INT_ENA</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT0_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT1_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT2_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT3_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT4_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT5_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT6_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT7_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_START_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_START_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DONE_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_SUC_EOF_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DONE_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_EOF_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_ERR_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DSCR_ERR_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_EMPTY_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_ACK_INT_ENA</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_WR_RETRY_DONE_INT_ENA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_ERR_EOF_INT_ENA</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMD_DTC_INT_ENA</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_QUICK_EOF_INT_ENA</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0INT_CLR</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT0_INT_CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT1_INT_CLR</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT2_INT_CLR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT3_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT4_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT5_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT6_INT_CLR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT7_INT_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_START_INT_CLR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_START_INT_CLR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_CLR</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_CLR</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_CLR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DONE_INT_CLR</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_SUC_EOF_INT_CLR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DONE_INT_CLR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_EOF_INT_CLR</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_INT_CLR</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_ERR_INT_CLR</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DSCR_ERR_INT_CLR</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_EMPTY_INT_CLR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_ACK_INT_CLR</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_WR_RETRY_DONE_INT_CLR</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_ERR_EOF_INT_CLR</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMD_DTC_INT_CLR</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_QUICK_EOF_INT_CLR</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1INT_RAW</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT8_INT_RAW</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT9_INT_RAW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT10_INT_RAW</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT11_INT_RAW</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT12_INT_RAW</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT13_INT_RAW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT14_INT_RAW</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT15_INT_RAW</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_START_INT_RAW</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_START_INT_RAW</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_RAW</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_RAW</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_RAW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_RAW</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DONE_INT_RAW</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_SUC_EOF_INT_RAW</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DONE_INT_RAW</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_EOF_INT_RAW</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_INT_RAW</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_ERR_INT_RAW</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DSCR_ERR_INT_RAW</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_EMPTY_INT_RAW</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_ACK_INT_RAW</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_WR_RETRY_DONE_INT_RAW</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_ERR_EOF_INT_RAW</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1INT_ST</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT8_INT_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT9_INT_ST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT10_INT_ST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT11_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT12_INT_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT13_INT_ST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT14_INT_ST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT15_INT_ST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_START_INT_ST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_START_INT_ST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_ST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_ST</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_ST</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DONE_INT_ST</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_SUC_EOF_INT_ST</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DONE_INT_ST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_EOF_INT_ST</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_INT_ST</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_ERR_INT_ST</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DSCR_ERR_INT_ST</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_EMPTY_INT_ST</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_ACK_INT_ST</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_WR_RETRY_DONE_INT_ST</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_ERR_EOF_INT_ST</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1INT_ENA</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT8_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT9_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT10_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT11_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT12_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT13_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT14_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT15_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_START_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_START_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DONE_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_SUC_EOF_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DONE_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_EOF_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_ERR_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DSCR_ERR_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_EMPTY_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_ACK_INT_ENA</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_WR_RETRY_DONE_INT_ENA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_ERR_EOF_INT_ENA</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1INT_CLR</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT8_INT_CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT9_INT_CLR</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT10_INT_CLR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT11_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT12_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT13_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT14_INT_CLR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT15_INT_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_START_INT_CLR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_START_INT_CLR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_CLR</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_CLR</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_CLR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DONE_INT_CLR</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_SUC_EOF_INT_CLR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DONE_INT_CLR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_EOF_INT_CLR</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_INT_CLR</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_ERR_INT_CLR</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DSCR_ERR_INT_CLR</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_EMPTY_INT_CLR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_ACK_INT_CLR</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_WR_RETRY_DONE_INT_CLR</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_ERR_EOF_INT_CLR</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_STATUS</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00020002</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_RX_FULL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_EMPTY</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_FULL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_EMPTY</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0RXFIFO_PUSH</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RXFIFO_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RXFIFO_PUSH</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1RXFIFO_PUSH</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_RXFIFO_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RXFIFO_PUSH</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_STATUS</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00020002</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_TX_FULL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_EMPTY</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_FULL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_EMPTY</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0TXFIFO_POP</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TXFIFO_RDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TXFIFO_POP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1TXFIFO_POP</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TXFIFO_RDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TXFIFO_POP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0RX_LINK</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RXLINK_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RXLINK_STOP</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RXLINK_START</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RXLINK_RESTART</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RXLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0TX_LINK</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TXLINK_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TXLINK_STOP</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TXLINK_START</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TXLINK_RESTART</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TXLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1RX_LINK</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00100000</resetValue>
+          <fields>
+            <field>
+              <name>SLC1_RXLINK_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_BT_PACKET</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RXLINK_STOP</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RXLINK_START</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RXLINK_RESTART</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RXLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1TX_LINK</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TXLINK_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TXLINK_STOP</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TXLINK_START</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TXLINK_RESTART</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TXLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTVEC_TOHOST</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOHOST_INTVEC</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_INTVEC</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0TOKEN0</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOKEN0_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_WR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_INC</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_INC_MORE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0TOKEN1</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOKEN1_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_WR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_INC</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_INC_MORE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1TOKEN0</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TOKEN0_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_WR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_INC</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_INC_MORE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1TOKEN1</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TOKEN1_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_WR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_INC</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_INC_MORE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00300078</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_CHECK_OWNER</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_CHECK_SUM_EN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_CHECK_SUM_EN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMD_HOLD_EN</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_LEN_AUTO_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_STITCH_EN</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_STITCH_EN</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_CHECK_OWNER</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_CHECK_SUM_EN</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_CHECK_SUM_EN</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_INT_LEVEL_SEL</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_STITCH_EN</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_STITCH_EN</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_STATE0</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_STATE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_STATE1</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_STATE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_STATE0</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_STATE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_STATE1</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_STATE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BRIDGE_CONF</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A7720</resetValue>
+          <fields>
+            <field>
+              <name>TXEOF_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_MAP_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DUMMY_MODE</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HDA_MAP_128K</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DUMMY_MODE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PUSH_IDLE_NUM</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TO_EOF_DES_ADDR</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TO_EOF_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TX_EOF_DES_ADDR</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TX_SUC_EOF_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TO_EOF_BFR_DES_ADDR</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TO_EOF_BFR_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_TO_EOF_DES_ADDR</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TO_EOF_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_TX_EOF_DES_ADDR</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TX_SUC_EOF_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_TO_EOF_BFR_DES_ADDR</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TO_EOF_BFR_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_TEST</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHB_TESTMODE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_TESTADDR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_ST</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMD_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FUNC_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_WAKEUP</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FUNC1_ACC_STATE</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FUNC2_ACC_STATE</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_DSCR_CONF</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x101B101A</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_TOKEN_NO_REPLACE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_INFOR_NO_REPLACE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_FILL_MODE</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_EOF_MODE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_FILL_EN</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RD_RETRY_THRESHOLD</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN_NO_REPLACE</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_INFOR_NO_REPLACE</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_FILL_MODE</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_EOF_MODE</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_FILL_EN</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RD_RETRY_THRESHOLD</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TXLINK_DSCR</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TXLINK_DSCR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TXLINK_DSCR_BF0</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TXLINK_DSCR_BF0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TXLINK_DSCR_BF1</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TXLINK_DSCR_BF1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_RXLINK_DSCR</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RXLINK_DSCR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_RXLINK_DSCR_BF0</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RXLINK_DSCR_BF0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_RXLINK_DSCR_BF1</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RXLINK_DSCR_BF1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_TXLINK_DSCR</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TXLINK_DSCR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_TXLINK_DSCR_BF0</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TXLINK_DSCR_BF0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_TXLINK_DSCR_BF1</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TXLINK_DSCR_BF1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_RXLINK_DSCR</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_RXLINK_DSCR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_RXLINK_DSCR_BF0</name>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_RXLINK_DSCR_BF0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_RXLINK_DSCR_BF1</name>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_RXLINK_DSCR_BF1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TX_ERREOF_DES_ADDR</name>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TX_ERR_EOF_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1_TX_ERREOF_DES_ADDR</name>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TX_ERR_EOF_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOKEN_LAT</name>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOKEN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_DSCR_CONF</name>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>WR_RETRY_THRESHOLD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD_INFOR0</name>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMD_CONTENT0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD_INFOR1</name>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMD_CONTENT1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_LEN_CONF</name>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_LEN_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_LEN_WR</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_LEN_INC</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_LEN_INC_MORE</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_PACKET_LOAD_EN</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_PACKET_LOAD_EN</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_GET_USED_DSCR</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_GET_USED_DSCR</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_NEW_PKT_IND</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_NEW_PKT_IND</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_LENGTH</name>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_LEN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TXPKT_H_DSCR</name>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TX_PKT_H_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TXPKT_E_DSCR</name>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TX_PKT_E_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_RXPKT_H_DSCR</name>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RX_PKT_H_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_RXPKT_E_DSCR</name>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RX_PKT_E_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TXPKTU_H_DSCR</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TX_PKT_START_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_TXPKTU_E_DSCR</name>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TX_PKT_END_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_RXPKTU_H_DSCR</name>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RX_PKT_START_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_RXPKTU_E_DSCR</name>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RX_PKT_END_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEQ_POSITION</name>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000509</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_SEQ_POSITION</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_SEQ_POSITION</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_DSCR_REC_CONF</name>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000003FF</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_RX_DSCR_REC_LIM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CRC_ST0</name>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DAT0_CRC_ERR_CNT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DAT1_CRC_ERR_CNT</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DAT2_CRC_ERR_CNT</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DAT3_CRC_ERR_CNT</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CRC_ST1</name>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMD_CRC_ERR_CNT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_CNT_CLR</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_EOF_START_DES</name>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_EOF_START_DES_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_PUSH_DSCR_ADDR</name>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RX_PUSH_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_DONE_DSCR_ADDR</name>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RX_DONE_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_SUB_START_DES</name>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_SUB_PAC_START_DSCR_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_DSCR_CNT</name>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_RX_DSCR_CNT_LAT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_GET_EOF_OCC</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0_LEN_LIM_CONF</name>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00005400</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_LEN_LIM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0INT_ST1</name>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT0_INT_ST1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT1_INT_ST1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT2_INT_ST1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT3_INT_ST1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT4_INT_ST1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT5_INT_ST1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT6_INT_ST1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT7_INT_ST1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_START_INT_ST1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_START_INT_ST1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_ST1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_ST1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_ST1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_ST1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DONE_INT_ST1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_SUC_EOF_INT_ST1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DONE_INT_ST1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_EOF_INT_ST1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_INT_ST1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_ERR_INT_ST1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DSCR_ERR_INT_ST1</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_EMPTY_INT_ST1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_ACK_INT_ST1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_WR_RETRY_DONE_INT_ST1</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_ERR_EOF_INT_ST1</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMD_DTC_INT_ST1</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_QUICK_EOF_INT_ST1</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_0INT_ENA1</name>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT0_INT_ENA1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT1_INT_ENA1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT2_INT_ENA1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT3_INT_ENA1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT4_INT_ENA1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT5_INT_ENA1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT6_INT_ENA1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT7_INT_ENA1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_START_INT_ENA1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_START_INT_ENA1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_ENA1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_ENA1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_ENA1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_ENA1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DONE_INT_ENA1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_SUC_EOF_INT_ENA1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DONE_INT_ENA1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_EOF_INT_ENA1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_INT_ENA1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_ERR_INT_ENA1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_DSCR_ERR_INT_ENA1</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_DSCR_EMPTY_INT_ENA1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_ACK_INT_ENA1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_WR_RETRY_DONE_INT_ENA1</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_ERR_EOF_INT_ENA1</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMD_DTC_INT_ENA1</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_QUICK_EOF_INT_ENA1</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1INT_ST1</name>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT8_INT_ST1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT9_INT_ST1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT10_INT_ST1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT11_INT_ST1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT12_INT_ST1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT13_INT_ST1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT14_INT_ST1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT15_INT_ST1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_START_INT_ST1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_START_INT_ST1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_ST1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_ST1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_ST1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_ST1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DONE_INT_ST1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_SUC_EOF_INT_ST1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DONE_INT_ST1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_EOF_INT_ST1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_INT_ST1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_ERR_INT_ST1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DSCR_ERR_INT_ST1</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_EMPTY_INT_ST1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_ACK_INT_ST1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_WR_RETRY_DONE_INT_ST1</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_ERR_EOF_INT_ST1</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>_1INT_ENA1</name>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRHOST_BIT8_INT_ENA1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT9_INT_ENA1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT10_INT_ENA1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT11_INT_ENA1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT12_INT_ENA1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT13_INT_ENA1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT14_INT_ENA1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRHOST_BIT15_INT_ENA1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_START_INT_ENA1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_START_INT_ENA1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_ENA1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_ENA1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_ENA1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_ENA1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DONE_INT_ENA1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_SUC_EOF_INT_ENA1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DONE_INT_ENA1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_EOF_INT_ENA1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_INT_ENA1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_ERR_INT_ENA1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_DSCR_ERR_INT_ENA1</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_DSCR_EMPTY_INT_ENA1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_ACK_INT_ENA1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_WR_RETRY_DONE_INT_ENA1</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_ERR_EOF_INT_ENA1</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x16022500</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ID</name>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>ID</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SLCHOST</name>
+      <description>Peripheral SLCHOST</description>
+      <groupName>SLCHOST</groupName>
+      <baseAddress>0x3FF55000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x104</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>HOST_SLCHOST_FUNC2_0</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC_FUNC2_INT</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_FUNC2_1</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC_FUNC2_INT_EN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_FUNC2_2</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>HOST_SLC_FUNC1_MDSTAT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_GPIO_STATUS0</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_GPIO_SDIO_INT0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_GPIO_STATUS1</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_GPIO_SDIO_INT1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_GPIO_IN0</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_GPIO_SDIO_IN0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_GPIO_IN1</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_GPIO_SDIO_IN1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_TOKEN_RDATA</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0_TOKEN0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_PF_VALID</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_HOSTSLC0_TOKEN1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_PF_EOF</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0_HOST_PF</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0_PF_DATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1_HOST_PF</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC1_PF_DATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_INT_RAW</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT0_INT_RAW</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT1_INT_RAW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT2_INT_RAW</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT3_INT_RAW</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT4_INT_RAW</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT5_INT_RAW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT6_INT_RAW</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT7_INT_RAW</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_1TO0_INT_RAW</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_1TO0_INT_RAW</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_0TO1_INT_RAW</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_0TO1_INT_RAW</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_SOF_INT_RAW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_EOF_INT_RAW</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_START_INT_RAW</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_TX_START_INT_RAW</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_UDF_INT_RAW</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TX_OVF_INT_RAW</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_PF_VALID_INT_RAW</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT0_INT_RAW</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT1_INT_RAW</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT2_INT_RAW</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT3_INT_RAW</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_NEW_PACKET_INT_RAW</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_HOST_RD_RETRY_INT_RAW</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_GPIO_SDIO_INT_RAW</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_INT_RAW</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT0_INT_RAW</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT1_INT_RAW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT2_INT_RAW</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT3_INT_RAW</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT4_INT_RAW</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT5_INT_RAW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT6_INT_RAW</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT7_INT_RAW</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_1TO0_INT_RAW</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_1TO0_INT_RAW</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_0TO1_INT_RAW</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_0TO1_INT_RAW</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_SOF_INT_RAW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_EOF_INT_RAW</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_START_INT_RAW</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TX_START_INT_RAW</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_UDF_INT_RAW</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TX_OVF_INT_RAW</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_PF_VALID_INT_RAW</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT0_INT_RAW</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT1_INT_RAW</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT2_INT_RAW</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT3_INT_RAW</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_HOST_RD_RETRY_INT_RAW</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_INT_ST</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT0_INT_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT1_INT_ST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT2_INT_ST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT3_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT4_INT_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT5_INT_ST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT6_INT_ST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT7_INT_ST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_1TO0_INT_ST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_1TO0_INT_ST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_0TO1_INT_ST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_0TO1_INT_ST</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_SOF_INT_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_EOF_INT_ST</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_START_INT_ST</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_TX_START_INT_ST</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_UDF_INT_ST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TX_OVF_INT_ST</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_PF_VALID_INT_ST</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT0_INT_ST</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT1_INT_ST</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT2_INT_ST</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT3_INT_ST</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_NEW_PACKET_INT_ST</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_HOST_RD_RETRY_INT_ST</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_GPIO_SDIO_INT_ST</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_INT_ST</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT0_INT_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT1_INT_ST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT2_INT_ST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT3_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT4_INT_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT5_INT_ST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT6_INT_ST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT7_INT_ST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_1TO0_INT_ST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_1TO0_INT_ST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_0TO1_INT_ST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_0TO1_INT_ST</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_SOF_INT_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_EOF_INT_ST</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_START_INT_ST</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TX_START_INT_ST</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_UDF_INT_ST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TX_OVF_INT_ST</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_PF_VALID_INT_ST</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT0_INT_ST</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT1_INT_ST</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT2_INT_ST</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT3_INT_ST</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_HOST_RD_RETRY_INT_ST</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_BT_RX_NEW_PACKET_INT_ST</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_PKT_LEN</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_HOSTSLC0_LEN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_HOSTSLC0_LEN_CHECK</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_STATE_W0</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_STATE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_STATE1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_STATE2</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_STATE3</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_STATE_W1</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_STATE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_STATE5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_STATE6</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_STATE7</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W0</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF2</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF3</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W1</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF6</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF7</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W2</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF8</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF9</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF10</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF11</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W3</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000C0</resetValue>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF12</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF13</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF14</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF15</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W4</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001FF</resetValue>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF16</name>
+              <description>SLC timeout value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF17</name>
+              <description>SLC timeout enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF18</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF19</name>
+              <description>Interrupt to target CPU</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W5</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF20</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF21</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF22</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF23</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_WIN_CMD</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W6</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF24</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF25</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF26</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF27</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W7</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF28</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF29</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF30</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF31</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_PKT_LEN0</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_HOSTSLC0_LEN0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_PKT_LEN1</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_HOSTSLC0_LEN1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_PKT_LEN2</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_HOSTSLC0_LEN2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W8</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF32</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF33</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF34</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF35</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W9</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF36</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF37</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF38</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF39</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W10</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF40</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF41</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF42</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF43</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W11</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF44</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF45</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF46</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF47</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W12</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF48</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF49</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF50</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF51</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W13</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF52</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF53</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF54</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF55</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W14</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF56</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF57</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF58</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF59</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF_W15</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CONF60</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF61</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF62</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_CONF63</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CHECK_SUM0</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CHECK_SUM0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CHECK_SUM1</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_CHECK_SUM1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_TOKEN_RDATA</name>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC1_TOKEN0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_PF_VALID</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_HOSTSLC1_TOKEN1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_PF_EOF</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_TOKEN_WDATA</name>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0HOST_TOKEN0_WD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_TOKEN1_WD</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_TOKEN_WDATA</name>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC1HOST_TOKEN0_WD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TOKEN1_WD</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_TOKEN_CON</name>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0HOST_TOKEN0_DEC</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_TOKEN1_DEC</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_TOKEN0_WR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_TOKEN1_WR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TOKEN0_DEC</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TOKEN1_DEC</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TOKEN0_WR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TOKEN1_WR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_LEN_WR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_INT_CLR</name>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT0_INT_CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT1_INT_CLR</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT2_INT_CLR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT3_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT4_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT5_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT6_INT_CLR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT7_INT_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_1TO0_INT_CLR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_1TO0_INT_CLR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_0TO1_INT_CLR</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_0TO1_INT_CLR</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_SOF_INT_CLR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_EOF_INT_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_START_INT_CLR</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_TX_START_INT_CLR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_UDF_INT_CLR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TX_OVF_INT_CLR</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_PF_VALID_INT_CLR</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT0_INT_CLR</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT1_INT_CLR</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT2_INT_CLR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT3_INT_CLR</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_NEW_PACKET_INT_CLR</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_HOST_RD_RETRY_INT_CLR</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_GPIO_SDIO_INT_CLR</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_INT_CLR</name>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT0_INT_CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT1_INT_CLR</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT2_INT_CLR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT3_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT4_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT5_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT6_INT_CLR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT7_INT_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_1TO0_INT_CLR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_1TO0_INT_CLR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_0TO1_INT_CLR</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_0TO1_INT_CLR</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_SOF_INT_CLR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_EOF_INT_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_START_INT_CLR</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TX_START_INT_CLR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_UDF_INT_CLR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TX_OVF_INT_CLR</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_PF_VALID_INT_CLR</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT0_INT_CLR</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT1_INT_CLR</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT2_INT_CLR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT3_INT_CLR</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_HOST_RD_RETRY_INT_CLR</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_FUNC1_INT_ENA</name>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0HOST_RX_SOF_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0HOST_RX_EOF_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0HOST_RX_START_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0HOST_TX_START_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_RX_UDF_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_TX_OVF_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_RX_PF_VALID_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_EXT_BIT0_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_EXT_BIT1_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_EXT_BIT2_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_EXT_BIT3_INT_ENA</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_GPIO_SDIO_INT_ENA</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_FUNC1_INT_ENA</name>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1HOST_RX_SOF_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1HOST_RX_EOF_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1HOST_RX_START_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1HOST_TX_START_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_RX_UDF_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_TX_OVF_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_RX_PF_VALID_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_EXT_BIT0_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_EXT_BIT1_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_EXT_BIT2_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_EXT_BIT3_INT_ENA</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_FUNC2_INT_ENA</name>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0HOST_RX_SOF_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0HOST_RX_EOF_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0HOST_RX_START_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0HOST_TX_START_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_RX_UDF_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_TX_OVF_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_RX_PF_VALID_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_EXT_BIT0_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_EXT_BIT1_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_EXT_BIT2_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_EXT_BIT3_INT_ENA</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_GPIO_SDIO_INT_ENA</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_FUNC2_INT_ENA</name>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1HOST_RX_SOF_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1HOST_RX_EOF_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1HOST_RX_START_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1HOST_TX_START_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_RX_UDF_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_TX_OVF_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_RX_PF_VALID_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_EXT_BIT0_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_EXT_BIT1_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_EXT_BIT2_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_EXT_BIT3_INT_ENA</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_INT_ENA</name>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT0_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT1_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT2_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT3_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT4_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT5_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT6_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT7_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_1TO0_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_1TO0_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_0TO1_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_0TO1_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_SOF_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_EOF_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_START_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_TX_START_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_UDF_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TX_OVF_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_PF_VALID_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT0_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT1_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT2_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT3_INT_ENA</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_NEW_PACKET_INT_ENA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_HOST_RD_RETRY_INT_ENA</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_GPIO_SDIO_INT_ENA</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_INT_ENA</name>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT0_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT1_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT2_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT3_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT4_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT5_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT6_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT7_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_1TO0_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_1TO0_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_0TO1_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_0TO1_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_SOF_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_EOF_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_START_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TX_START_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_UDF_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TX_OVF_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_PF_VALID_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT0_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT1_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT2_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT3_INT_ENA</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_HOST_RD_RETRY_INT_ENA</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_RX_INFOR</name>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0HOST_RX_INFOR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_RX_INFOR</name>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC1HOST_RX_INFOR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_LEN_WD</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0HOST_LEN_WD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC_APBWIN_WDATA</name>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC_APBWIN_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC_APBWIN_CONF</name>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC_APBWIN_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC_APBWIN_WR</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC_APBWIN_START</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC_APBWIN_RDATA</name>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC_APBWIN_RDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_RDCLR0</name>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003C044</resetValue>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_SLC0_BIT7_CLRADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_SLC0_BIT6_CLRADDR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_RDCLR1</name>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003C1E0</resetValue>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_SLC1_BIT7_CLRADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLCHOST_SLC1_BIT6_CLRADDR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC0HOST_INT_ENA1</name>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT0_INT_ENA1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT1_INT_ENA1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT2_INT_ENA1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT3_INT_ENA1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT4_INT_ENA1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT5_INT_ENA1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT6_INT_ENA1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOHOST_BIT7_INT_ENA1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_1TO0_INT_ENA1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_1TO0_INT_ENA1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN0_0TO1_INT_ENA1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TOKEN1_0TO1_INT_ENA1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_SOF_INT_ENA1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_EOF_INT_ENA1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_RX_START_INT_ENA1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0HOST_TX_START_INT_ENA1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_UDF_INT_ENA1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_TX_OVF_INT_ENA1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_PF_VALID_INT_ENA1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT0_INT_ENA1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT1_INT_ENA1</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT2_INT_ENA1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_EXT_BIT3_INT_ENA1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_RX_NEW_PACKET_INT_ENA1</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC0_HOST_RD_RETRY_INT_ENA1</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_GPIO_SDIO_INT_ENA1</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLC1HOST_INT_ENA1</name>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT0_INT_ENA1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT1_INT_ENA1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT2_INT_ENA1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT3_INT_ENA1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT4_INT_ENA1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT5_INT_ENA1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT6_INT_ENA1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOHOST_BIT7_INT_ENA1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_1TO0_INT_ENA1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_1TO0_INT_ENA1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN0_0TO1_INT_ENA1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TOKEN1_0TO1_INT_ENA1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_SOF_INT_ENA1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_EOF_INT_ENA1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_RX_START_INT_ENA1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1HOST_TX_START_INT_ENA1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_UDF_INT_ENA1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_TX_OVF_INT_ENA1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_RX_PF_VALID_INT_ENA1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT0_INT_ENA1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT1_INT_ENA1</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT2_INT_ENA1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_EXT_BIT3_INT_ENA1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_HOST_RD_RETRY_INT_ENA1</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOSTDATE</name>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x16022500</resetValue>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOSTID</name>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000600</resetValue>
+          <fields>
+            <field>
+              <name>HOST_SLCHOST_ID</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_CONF</name>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_FRC_SDIO11</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FRC_SDIO20</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FRC_NEG_SAMP</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FRC_POS_SAMP</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_FRC_QUICK_IN</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SDIO20_INT_DELAY</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_SDIO_PAD_PULLUP</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOST_HSPEED_CON_EN</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_SLCHOST_INF_ST</name>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOST_SDIO20_MODE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SDIO_NEG_SAMP</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOST_SDIO_QUICK_IN</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI0</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI</groupName>
+      <baseAddress>0x3FF43000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x110</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI0</name>
+        <value>28</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CMD</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FLASH_PER</name>
+              <description>program erase resume bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES</name>
+              <description>program erase suspend bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_HPM</name>
+              <description>Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RES</name>
+              <description>This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_DP</name>
+              <description>Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_CE</name>
+              <description>Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_BE</name>
+              <description>Block erase enable. A 64KB block is erased via SPI command D8H.  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_SE</name>
+              <description>Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PP</name>
+              <description>Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WRSR</name>
+              <description>Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RDSR</name>
+              <description>Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RDID</name>
+              <description>Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WRDI</name>
+              <description>Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WREN</name>
+              <description>Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_READ</name>
+              <description>Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0020A400</resetValue>
+          <fields>
+            <field>
+              <name>FCS_CRC_EN</name>
+              <description>For SPI1  initialize crc32 module before writing encrypted data to flash. Active low.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CRC_EN</name>
+              <description>For SPI1  enable crc32 when writing encrypted data to flash. 1: enable  0:disable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_FLASH_IDLE_EN</name>
+              <description>wait flash idle when program flash or erase flash. 1: enable 0: disable.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTRD_MODE</name>
+              <description>This bit enable the bits: spi_fread_qio  spi_fread_dio  spi_fread_qout and spi_fread_dout. 1: enable 0: disable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESANDRES</name>
+              <description>The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high  0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WRSR_2B</name>
+              <description>two bytes data will be written to status register when it is set. 1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DIO</name>
+              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QIO</name>
+              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_BIT_ORDER</name>
+              <description>In read-data (MISO) phase 1: LSB first 0: MSB first</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WR_BIT_ORDER</name>
+              <description>In command address write-data (MOSI) phases 1: LSB firs 0: MSB first</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL1</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5FFF0000</resetValue>
+          <fields>
+            <field>
+              <name>CS_HOLD_DELAY_RES</name>
+              <description>Delay cycles of resume Flash when resume Flash is enable by spi clock.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_DELAY</name>
+              <description>SPI cs signal is delayed by spi clock cycles</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_STATUS</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>In the slave mode, it is the status for master to read out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WB_MODE</name>
+              <description>Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STATUS_EXT</name>
+              <description>In the slave mode,it is the status for master to read out.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000011</resetValue>
+          <fields>
+            <field>
+              <name>SETUP_TIME</name>
+              <description>(cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD_TIME</name>
+              <description>delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_LOW_MODE</name>
+              <description>modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_HIGH_MODE</name>
+              <description>modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MISO_DELAY_MODE</name>
+              <description>MISO signals are delayed by spi_clk. 0: zero  1: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by half cycle    else delayed by one cycle  2: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by one cycle  else delayed by half cycle  3: delayed one cycle</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MISO_DELAY_NUM</name>
+              <description>MISO signals are delayed by system clock cycles</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MOSI_DELAY_MODE</name>
+              <description>MOSI signals are delayed by spi_clk. 0: zero  1: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by half cycle    else delayed by one cycle  2: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by one cycle  else delayed by half cycle  3: delayed one cycle</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MOSI_DELAY_NUM</name>
+              <description>MOSI signals are delayed by system clock cycles</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_DELAY_MODE</name>
+              <description>spi_cs signal is delayed by spi_clk . 0: zero  1: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by half cycle    else delayed by one cycle  2: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by one cycle   else delayed by half cycle  3: delayed one cycle</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_DELAY_NUM</name>
+              <description>spi_cs signal is delayed by system clock cycles</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80003043</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKDIV_PRE</name>
+              <description>In the master mode it is pre-divider of spi_clk.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000040</resetValue>
+          <fields>
+            <field>
+              <name>DOUTDIN</name>
+              <description>Set the bit to enable full duplex communication. 1: enable 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD</name>
+              <description>spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP</name>
+              <description>spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_I_EDGE</name>
+              <description>In the slave mode  the bit is same as spi_ck_out_edge in master mode. It is combined with  spi_miso_delay_mode bits.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_BYTE_ORDER</name>
+              <description>In read-data (MISO) phase 1: big-endian 0: little_endian</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WR_BYTE_ORDER</name>
+              <description>In command address write-data (MOSI) phases 1: big-endian 0: litte_endian</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DIO</name>
+              <description>In the write operations address phase and read-data phase apply 2 signals.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QIO</name>
+              <description>In the write operations address phase and read-data phase apply 4 signals.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIO</name>
+              <description>Set the bit to enable 3-line half duplex communication  mosi and miso signals share the same pin. 1: enable 0: disable.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_HOLD_POL</name>
+              <description>It is combined with hold bits to set the polarity of spi hold line  1: spi will be held when spi hold line is high  0: spi will be held when spi hold line is low</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DOUT_HOLD</name>
+              <description>spi is hold at data out state  the bit combined with spi_usr_hold_pol bit.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DIN_HOLD</name>
+              <description>spi is hold at data in state  the bit combined with spi_usr_hold_pol bit.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_HOLD</name>
+              <description>spi is hold at dummy state  the bit combined with spi_usr_hold_pol bit.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_HOLD</name>
+              <description>spi is hold at address state  the bit combined with spi_usr_hold_pol bit.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_CMD_HOLD</name>
+              <description>spi is hold at command state  the bit combined with spi_usr_hold_pol bit.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_PREP_HOLD</name>
+              <description>spi is hold at prepare state  the bit combined with spi_usr_hold_pol bit.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR</name>
+              <description>This bit enable the address phase of an operation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of  command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MOSI_DLEN</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MOSI_DBITLEN</name>
+              <description>The length in bits of write-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISO_DLEN</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MISO_DBITLEN</name>
+              <description>The length in bits of  read-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLV_WR_STATUS</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_WR_ST</name>
+              <description>In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIN</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000006</resetValue>
+          <fields>
+            <field>
+              <name>CS0_DIS</name>
+              <description>SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS1_DIS</name>
+              <description>SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS2_DIS</name>
+              <description>SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_DIS</name>
+              <description>1: spi clk out disable  0: spi clk out enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_CS_POL</name>
+              <description>In the master mode  the bits are the polarity of spi cs line  the value is equivalent to spi_cs ^ spi_master_cs_pol.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_CK_SEL</name>
+              <description>In the master mode  spi cs line is enable as spi clk  it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>SLV_RD_BUF_DONE</name>
+              <description>The interrupt raw bit for the completion of read-buffer operation in the slave mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE</name>
+              <description>The interrupt raw bit for the completion of write-buffer operation in the slave mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_STA_DONE</name>
+              <description>The interrupt raw bit for the completion of read-status operation in the slave mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_STA_DONE</name>
+              <description>The interrupt raw bit for the completion of write-status operation in the slave mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_DONE</name>
+              <description>The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_EN</name>
+              <description>Interrupt enable bits for the below 5 sources</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_I_MODE</name>
+              <description>In the slave mode  this bits used to synchronize the input spi cs signal and eliminate spi cs  jitter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_COMMAND</name>
+              <description>In the slave mode it is the value of command.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_LAST_STATE</name>
+              <description>In the slave mode it is the state of spi state machine.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_CNT</name>
+              <description>The operations counter in both the master mode and the slave mode. 4: read-status</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_DEFINE</name>
+              <description>1: slave mode commands are defined in SPI_SLAVE3.  0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_RD_STA_EN</name>
+              <description>write and read status enable  in the slave mode</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_RD_BUF_EN</name>
+              <description>write and read buffer enable in the slave mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>1: slave mode 0: master mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC_RESET</name>
+              <description>Software reset enable, reset the spi clock line cs line and data lines.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE1</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02000000</resetValue>
+          <fields>
+            <field>
+              <name>SLV_RDBUF_DUMMY_EN</name>
+              <description>In the slave mode it is the enable bit of dummy phase for read-buffer operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRBUF_DUMMY_EN</name>
+              <description>In the slave mode it is the enable bit of dummy phase for write-buffer operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDSTA_DUMMY_EN</name>
+              <description>In the slave mode it is the enable bit of dummy phase for read-status operations.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRSTA_DUMMY_EN</name>
+              <description>In the slave mode it is the enable bit of dummy phase for write-status operations.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_ADDR_BITLEN</name>
+              <description>In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_ADDR_BITLEN</name>
+              <description>In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_STATUS_READBACK</name>
+              <description>In the slave mode  1:read register of SPI_SLV_WR_STATUS  0: read register of SPI_RD_STATUS.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_STATUS_FAST_EN</name>
+              <description>In the slave mode enable fast read status.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_STATUS_BITLEN</name>
+              <description>In the slave mode it is the length of status bit.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE2</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_RDSTA_DUMMY_CYCLELEN</name>
+              <description>In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRSTA_DUMMY_CYCLELEN</name>
+              <description>In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDBUF_DUMMY_CYCLELEN</name>
+              <description>In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRBUF_DUMMY_CYCLELEN</name>
+              <description>In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE3</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_RDBUF_CMD_VALUE</name>
+              <description>In the slave mode it is the value of read-buffer command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRBUF_CMD_VALUE</name>
+              <description>In the slave mode it is the value of write-buffer command.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDSTA_CMD_VALUE</name>
+              <description>In the slave mode it is the value of read-status command.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRSTA_CMD_VALUE</name>
+              <description>In the slave mode it is the value of write-status command.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLV_WRBUF_DLEN</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_WRBUF_DBITLEN</name>
+              <description>In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLV_RDBUF_DLEN</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_RDBUF_DBITLEN</name>
+              <description>In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_FCTRL</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_REQ_EN</name>
+              <description>For SPI0  Cache access enable  1: enable  0:disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_USR_CMD_4BYTE</name>
+              <description>For SPI0  cache  read flash with 4 bytes command  1: enable  0:disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_FLASH_USR_CMD</name>
+              <description>For SPI0  cache  read flash for user define command  1: enable  0:disable.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_FLASH_PES_EN</name>
+              <description>For SPI0  spi1 send suspend command before cache read flash 1: enable  0:disable.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SCTRL</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x15C04830</resetValue>
+          <fields>
+            <field>
+              <name>USR_SRAM_DIO</name>
+              <description>For SPI0  In the spi sram mode  spi dual I/O mode enable  1: enable  0:disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_SRAM_QIO</name>
+              <description>For SPI0  In the spi sram mode  spi quad I/O mode enable  1: enable  0:disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_WR_SRAM_DUMMY</name>
+              <description>For SPI0  In the spi sram mode  it is the enable bit of dummy phase for write operations.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_RD_SRAM_DUMMY</name>
+              <description>For SPI0  In the spi sram mode  it is the enable bit of dummy phase for read operations.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SRAM_USR_RCMD</name>
+              <description>For SPI0  In the spi sram mode cache read sram for user define command.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_BYTES_LEN</name>
+              <description>For SPI0  In the sram mode  it is the byte length of spi read sram data.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_DUMMY_CYCLELEN</name>
+              <description>For SPI0  In the sram mode  it is the length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_ADDR_BITLEN</name>
+              <description>For SPI0  In the sram mode  it is the length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SRAM_USR_WCMD</name>
+              <description>For SPI0  In the spi sram mode cache write sram for user define command</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_CMD</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SRAM_DIO</name>
+              <description>For SPI0 SRAM DIO mode enable .  SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_QIO</name>
+              <description>For SPI0 SRAM QIO mode enable .  SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_RSTIO</name>
+              <description>For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_DRD_CMD</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_SRAM_USR_RD_CMD_VALUE</name>
+              <description>For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SRAM_USR_RD_CMD_BITLEN</name>
+              <description>For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_DWR_CMD</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_SRAM_USR_WR_CMD_VALUE</name>
+              <description>For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SRAM_USR_WR_CMD_BITLEN</name>
+              <description>For SPI0 When cache mode is enable it is the in bits of command phase  for SRAM. The register value shall be (bit_num-1).</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLV_RD_BIT</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_RDATA_BIT</name>
+              <description>In the slave mode it is the bit length of read data. The value is the length - 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W0</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W1</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W2</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W3</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W4</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W5</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W6</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W7</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W8</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W9</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W10</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W11</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W12</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W13</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W14</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W15</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CRC</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>For SPI1  the value of crc32 for 256 bits data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT0</name>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x800A0050</resetValue>
+          <fields>
+            <field>
+              <name>T_PP_TIME</name>
+              <description>page program delay time  by system clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_PP_SHIFT</name>
+              <description>page program delay time shift .</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_PP_ENA</name>
+              <description>page program delay enable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT1</name>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x800F0000</resetValue>
+          <fields>
+            <field>
+              <name>T_ERASE_TIME</name>
+              <description>erase flash delay time by system clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_ERASE_SHIFT</name>
+              <description>erase flash delay time shift.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_ERASE_ENA</name>
+              <description>erase flash delay enable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT2</name>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST</name>
+              <description>The status of spi state machine .</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT3</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_HOLD_ENA</name>
+              <description>This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set  if the other SPI is busy  the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>The bit is used to reset in dma fsm and in data fifo pointer.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_RST</name>
+              <description>The bit is used to reset out dma fsm and out data fifo pointer.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_FIFO_RST</name>
+              <description>reset spi dma ahb master fifo pointer.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_RST</name>
+              <description>reset spi dma ahb master.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>Set bit to test in link.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>Set bit to test out link.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>when the link is empty   jump to next automatically.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>out eof flag generation mode . 1: when dma pop all data from fifo  0:when ahb push all data to fifo.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>read descriptor use burst mode when read data for memory.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>read descriptor use burst mode when write data to memory.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <description>spi dma read data from memory in burst mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_STOP</name>
+              <description>spi dma read data stop  when in continue tx/rx mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_STOP</name>
+              <description>spi dma write data stop when in continue tx/rx mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_CONTINUE</name>
+              <description>spi dma continue tx/rx data.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_LINK</name>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>The address of the first outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set the bit to stop to use outlink descriptor.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set the bit to start to use outlink descriptor.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set the bit to mount on new outlink descriptors.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_LINK</name>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>The address of the first inlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET</name>
+              <description>when the bit is set  inlink descriptor returns to the next descriptor while a packet is wrong</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set the bit to stop to use inlink descriptor.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set the bit to start to use inlink descriptor.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set the bit to mount on new inlink descriptors.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_STATUS</name>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_RX_EN</name>
+              <description>spi dma read data status bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_TX_EN</name>
+              <description>spi dma write data status bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ENA</name>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_EMPTY_INT_ENA</name>
+              <description>The enable bit for lack of enough inlink descriptors.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_DSCR_ERROR_INT_ENA</name>
+              <description>The enable bit for outlink descriptor error.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_DSCR_ERROR_INT_ENA</name>
+              <description>The enable bit for inlink descriptor error.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ENA</name>
+              <description>The enable bit for completing usage of a inlink descriptor.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ENA</name>
+              <description>The enable bit for receiving error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ENA</name>
+              <description>The enable bit for completing receiving all the packets from host.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ENA</name>
+              <description>The enable bit for completing usage of a outlink descriptor .</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ENA</name>
+              <description>The enable bit for sending a packet to host done.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ENA</name>
+              <description>The enable bit for sending all the packets to host done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_RAW</name>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_EMPTY_INT_RAW</name>
+              <description>The raw bit for lack of enough inlink descriptors.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_DSCR_ERROR_INT_RAW</name>
+              <description>The raw bit for outlink descriptor error.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INLINK_DSCR_ERROR_INT_RAW</name>
+              <description>The raw bit for inlink descriptor error.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_RAW</name>
+              <description>The raw bit for completing usage of a inlink descriptor.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_RAW</name>
+              <description>The raw bit for receiving error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_RAW</name>
+              <description>The raw bit for completing receiving all the packets from host.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_RAW</name>
+              <description>The raw bit for completing usage of a outlink descriptor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <description>The raw bit for sending a packet to host done.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_RAW</name>
+              <description>The raw bit for sending all the packets to host done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ST</name>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_EMPTY_INT_ST</name>
+              <description>The status bit for lack of enough inlink descriptors.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_DSCR_ERROR_INT_ST</name>
+              <description>The status bit for outlink descriptor error.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INLINK_DSCR_ERROR_INT_ST</name>
+              <description>The status bit for inlink descriptor error.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ST</name>
+              <description>The status bit for completing usage of a inlink descriptor.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ST</name>
+              <description>The status bit for receiving error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ST</name>
+              <description>The status bit for completing receiving all the packets from host.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ST</name>
+              <description>The status bit for completing usage of a outlink descriptor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ST</name>
+              <description>The status bit for sending a packet to host done.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ST</name>
+              <description>The status bit for sending all the packets to host done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_CLR</name>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_EMPTY_INT_CLR</name>
+              <description>The clear bit for lack of enough inlink descriptors.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_DSCR_ERROR_INT_CLR</name>
+              <description>The clear bit for outlink descriptor error.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_DSCR_ERROR_INT_CLR</name>
+              <description>The clear bit for inlink descriptor error.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_CLR</name>
+              <description>The clear bit for completing usage of a inlink descriptor.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_CLR</name>
+              <description>The clear bit for receiving error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_CLR</name>
+              <description>The clear bit for completing receiving all the packets from host.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_CLR</name>
+              <description>The clear bit for completing usage of a outlink descriptor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_CLR</name>
+              <description>The clear bit for sending a packet to host done.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_CLR</name>
+              <description>The clear bit for sending all the packets to host done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_ERR_EOF_DES_ADDR</name>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_IN_ERR_EOF_DES_ADDR</name>
+              <description>The inlink descriptor address when spi dma produce receiving error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_SUC_EOF_DES_ADDR</name>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_IN_SUC_EOF_DES_ADDR</name>
+              <description>The last inlink descriptor address when spi dma produce from_suc_eof.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR</name>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INLINK_DSCR</name>
+              <description>The content of current in descriptor pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR_BF0</name>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INLINK_DSCR_BF0</name>
+              <description>The content of next in descriptor pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR_BF1</name>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INLINK_DSCR_BF1</name>
+              <description>The content of current in descriptor data buffer pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_BFR_DES_ADDR</name>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUT_EOF_BFR_DES_ADDR</name>
+              <description>The address of buffer relative to the outlink descriptor that produce eof.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_DES_ADDR</name>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUT_EOF_DES_ADDR</name>
+              <description>The last outlink descriptor address when spi dma produce to_eof.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR</name>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUTLINK_DSCR</name>
+              <description>The content of current out descriptor pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR_BF0</name>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUTLINK_DSCR_BF0</name>
+              <description>The content of next out descriptor pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR_BF1</name>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUTLINK_DSCR_BF1</name>
+              <description>The content of current out descriptor data buffer pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_RSTATUS</name>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUT_STATUS</name>
+              <description>spi dma read data from memory status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_TSTATUS</name>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_IN_STATUS</name>
+              <description>spi dma write data to memory status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01604270</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+      <name>SPI1</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x3FF42000</baseAddress>
+      <interrupt>
+        <name>SPI1</name>
+        <value>29</value>
+      </interrupt>
+      <interrupt>
+        <name>SPI1_DMA</name>
+        <value>52</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+      <name>SPI2</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x3FF64000</baseAddress>
+      <interrupt>
+        <name>SPI2</name>
+        <value>30</value>
+      </interrupt>
+      <interrupt>
+        <name>SPI2_DMA</name>
+        <value>53</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+      <name>SPI3</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x3FF65000</baseAddress>
+      <interrupt>
+        <name>SPI3</name>
+        <value>31</value>
+      </interrupt>
+      <interrupt>
+        <name>SPI3_DMA</name>
+        <value>54</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TIMG0</name>
+      <description>Timer Group</description>
+      <groupName>TIMG</groupName>
+      <baseAddress>0x3FF5F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TG0_T0_LEVEL</name>
+        <value>14</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_T1_LEVEL</name>
+        <value>15</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_WDT_LEVEL</name>
+        <value>16</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_LACT_LEVEL</name>
+        <value>17</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_T0_EDGE</name>
+        <value>58</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_T1_EDGE</name>
+        <value>59</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_WDT_EDGE</name>
+        <value>60</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_LACT_EDGE</name>
+        <value>61</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>T0CONFIG</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002000</resetValue>
+          <fields>
+            <field>
+              <name>ALARM_EN</name>
+              <description>When set  alarm is enabled</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEVEL_INT_EN</name>
+              <description>When set  level type interrupt will be generated during alarm</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EDGE_INT_EN</name>
+              <description>When set  edge type interrupt will be generated during alarm</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIVIDER</name>
+              <description>Timer 0 clock (T0_clk) prescale value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTORELOAD</name>
+              <description>When set  timer 0 auto-reload at alarming is enabled</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCREASE</name>
+              <description>When set  timer 0 time-base counter increment. When cleared timer 0 time-base counter decrement.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>When set  timer 0 time-base counter is enabled</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LO</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LO</name>
+              <description>Register to store timer 0 time-base counter current value lower 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0HI</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HI</name>
+              <description>Register to store timer 0 time-base counter current value higher 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0UPDATE</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UPDATE</name>
+              <description>Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMLO</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_LO</name>
+              <description>Timer 0 time-base counter value lower 32 bits that will trigger the alarm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMHI</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_HI</name>
+              <description>Timer 0 time-base counter value higher 32 bits that will trigger the alarm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADLO</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_LO</name>
+              <description>Lower 32 bits of the value that will load into timer 0 time-base counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADHI</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_HI</name>
+              <description>higher 32 bits of the value that will load into timer 0 time-base counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOAD</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD</name>
+              <description>Write any value will trigger timer 0 time-base counter reload</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T1CONFIG</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002000</resetValue>
+          <fields>
+            <field>
+              <name>ALARM_EN</name>
+              <description>When set  alarm is enabled</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEVEL_INT_EN</name>
+              <description>When set  level type interrupt will be generated during alarm</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EDGE_INT_EN</name>
+              <description>When set  edge type interrupt will be generated during alarm</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIVIDER</name>
+              <description>Timer 1 clock (T1_clk) prescale value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTORELOAD</name>
+              <description>When set  timer 1 auto-reload at alarming is enabled</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCREASE</name>
+              <description>When set  timer 1 time-base counter increment. When cleared timer 1 time-base counter decrement.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>When set  timer 1 time-base counter is enabled</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T1LO</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LO</name>
+              <description>Register to store timer 1 time-base counter current value lower 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T1HI</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HI</name>
+              <description>Register to store timer 1 time-base counter current value higher 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T1UPDATE</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UPDATE</name>
+              <description>Write any value will trigger a timer 1 time-base counter value update (timer 1 current value will be stored in registers above)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T1ALARMLO</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_LO</name>
+              <description>Timer 1 time-base counter value lower 32 bits that will trigger the alarm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T1ALARMHI</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_HI</name>
+              <description>Timer 1 time-base counter value higher 32 bits that will trigger the alarm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T1LOADLO</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_LO</name>
+              <description>Lower 32 bits of the value that will load into timer 1 time-base counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T1LOADHI</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_HI</name>
+              <description>higher 32 bits of the value that will load into timer 1 time-base counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T1LOAD</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD</name>
+              <description>Write any value will trigger timer 1 time-base counter reload</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0004C000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>When set  flash boot protection is enabled</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>length of system reset selection. 0: 100ns  1: 200ns  2: 300ns  3: 400ns  4: 500ns  5: 800ns  6: 1.6us  7: 3.2us</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <name>WDT_SYS_RESET_LENGTH</name>
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>NS100</name>
+                  <description>100ns</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS200</name>
+                  <description>200ns</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS300</name>
+                  <description>300ns</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS400</name>
+                  <description>400ns</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS500</name>
+                  <description>500ns</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS800</name>
+                  <description>800ns</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS1600</name>
+                  <description>1.6us</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS3200</name>
+                  <description>3.2us</description>
+                  <value>7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>length of CPU reset selection. 0: 100ns  1: 200ns  2: 300ns 3: 400ns  4: 500ns  5: 800ns  6: 1.6us  7: 3.2us</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <name>WDT_CPU_RESET_LENGTH</name>
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>NS100</name>
+                  <description>100ns</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS200</name>
+                  <description>200ns</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS300</name>
+                  <description>300ns</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS400</name>
+                  <description>400ns</description>
+                  <value>3</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS500</name>
+                  <description>500ns</description>
+                  <value>4</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS800</name>
+                  <description>800ns</description>
+                  <value>5</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS1600</name>
+                  <description>1.6us</description>
+                  <value>6</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>NS3200</name>
+                  <description>3.2us</description>
+                  <value>7</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDT_LEVEL_INT_EN</name>
+              <description>When set  level type interrupt generation is enabled</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EDGE_INT_EN</name>
+              <description>When set  edge type interrupt generation is enabled</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>Stage 3 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues>
+                <name>WDT_STG3</name>
+                <usage>read-write</usage>
+                <enumeratedValue>
+                  <name>OFF</name>
+                  <description>Off</description>
+                  <value>0</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>INTERRUPT</name>
+                  <description>Interrupt</description>
+                  <value>1</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET</name>
+                  <description>Reset CPU</description>
+                  <value>2</value>
+                </enumeratedValue>
+                <enumeratedValue>
+                  <name>RESET_SYS</name>
+                  <description>Reset system</description>
+                  <value>3</value>
+                </enumeratedValue>
+              </enumeratedValues>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>Stage 2 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues derivedFrom="WDT_STG3"/>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>Stage 1 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues derivedFrom="WDT_STG3"/>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>Stage 0 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+              <enumeratedValues derivedFrom="WDT_STG3"/>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>When set  SWDT is enabled</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CLK_PRESCALE</name>
+              <description>SWDT clock prescale value. Period = 12.5ns * value stored in this register</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x018CBA80</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>Stage 0 timeout value in SWDT clock cycles</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>Stage 1 timeout value in SWDT clock cycles</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>Stage 2 timeout value in SWDT clock cycles</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG5</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>Stage 3 timeout value in SWDT clock cycles</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>Write any value will feed SWDT</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>If change its value from default  then write protection is on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_START_CYCLING</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_CLK_SEL</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_RDY</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_MAX</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_START</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG1</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_CALI_VALUE</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTCONFIG</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002300</resetValue>
+          <fields>
+            <field>
+              <name>LACT_RTC_ONLY</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_CPST_EN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_LAC_EN</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_ALARM_EN</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_LEVEL_INT_EN</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_EDGE_INT_EN</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_DIVIDER</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_AUTORELOAD</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_INCREASE</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_EN</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTRTC</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_RTC_STEP_LEN</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTLO</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_LO</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTHI</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_HI</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTUPDATE</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_UPDATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTALARMLO</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_ALARM_LO</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTALARMHI</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_ALARM_HI</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTLOADLO</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_LOAD_LO</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTLOADHI</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_LOAD_HI</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTLOAD</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_LOAD</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_TIMERS</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ENA</name>
+              <description>interrupt when timer0 alarm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1_INT_ENA</name>
+              <description>interrupt when timer1 alarm</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>Interrupt when an interrupt stage timeout</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_TIMERS</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_RAW</name>
+              <description>interrupt when timer0 alarm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>T1_INT_RAW</name>
+              <description>interrupt when timer1 alarm</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>Interrupt when an interrupt stage timeout</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LACT_INT_RAW</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_TIMERS</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ST</name>
+              <description>interrupt when timer0 alarm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>T1_INT_ST</name>
+              <description>interrupt when timer1 alarm</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>Interrupt when an interrupt stage timeout</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LACT_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_TIMERS</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_CLR</name>
+              <description>interrupt when timer0 alarm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>T1_INT_CLR</name>
+              <description>interrupt when timer1 alarm</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Interrupt when an interrupt stage timeout</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LACT_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NTIMERS_DATE</name>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01604290</resetValue>
+          <fields>
+            <field>
+              <name>NTIMERS_DATE</name>
+              <description>Version of this regfile</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMGCLK</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Force clock enable for this regfile</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMG0">
+      <name>TIMG1</name>
+      <description>Timer Group</description>
+      <baseAddress>0x3FF60000</baseAddress>
+      <interrupt>
+        <name>TG1_T0_LEVEL</name>
+        <value>18</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_T1_LEVEL</name>
+        <value>19</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_WDT_LEVEL</name>
+        <value>20</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_LACT_LEVEL</name>
+        <value>21</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_T0_EDGE</name>
+        <value>62</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_T1_EDGE</name>
+        <value>63</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_WDT_EDGE</name>
+        <value>64</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_LACT_EDGE</name>
+        <value>65</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TWAI</name>
+      <description>Two-Wire Automotive Interface</description>
+      <groupName>TWAI</groupName>
+      <baseAddress>0x3FF6B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x6C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TWAI</name>
+        <value>45</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Mode Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RESET_MODE</name>
+              <description>This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LISTEN_ONLY_MODE</name>
+              <description>1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SELF_TEST_MODE</name>
+              <description>1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_MODE</name>
+              <description>This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>Command Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_REQ</name>
+              <description>Set the bit to 1 to allow the driving nodes start transmission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ABORT_TX</name>
+              <description>Set the bit to 1 to cancel a pending transmission request.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RELEASE_BUF</name>
+              <description>Set the bit to 1 to release the RX buffer.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CLR_OVERRUN</name>
+              <description>Set the bit to 1 to clear the data overrun status bit.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SELF_RX_REQ</name>
+              <description>Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_BUF_ST</name>
+              <description>1: The data in the RX buffer is not empty, with at least one received data packet.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN_ST</name>
+              <description>1: The RX FIFO is full and data overrun has occurred.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BUF_ST</name>
+              <description>1: The TX buffer is empty, the CPU may write a message into it.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_COMPLETE</name>
+              <description>1: The TWAI controller has successfully received a packet from the bus.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_ST</name>
+              <description>1: The TWAI Controller is receiving a message from the bus.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_ST</name>
+              <description>1: The TWAI Controller is transmitting a message to the bus.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_ST</name>
+              <description>1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_OFF_ST</name>
+              <description>1: In bus-off status, the TWAI Controller is no longer involved in bus activities.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MISS_ST</name>
+              <description>This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_INT_ST</name>
+              <description>Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_INT_ST</name>
+              <description>Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_WARN_INT_ST</name>
+              <description>Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN_INT_ST</name>
+              <description>Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ST</name>
+              <description>Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST_INT_ST</name>
+              <description>Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ST</name>
+              <description>Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt Enable Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_INT_ENA</name>
+              <description>Set this bit to 1 to enable receive interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_INT_ENA</name>
+              <description>Set this bit to 1 to enable transmit interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WARN_INT_ENA</name>
+              <description>Set this bit to 1 to enable error warning interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVERRUN_INT_ENA</name>
+              <description>Set this bit to 1 to enable data overrun interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ENA</name>
+              <description>Set this bit to 1 to enable error passive interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_LOST_INT_ENA</name>
+              <description>Set this bit to 1 to enable arbitration lost interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ENA</name>
+              <description>Set this bit to 1 to enable error interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_0</name>
+          <description>Bus Timing Register 0</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BAUD_PRESC</name>
+              <description>Baud Rate Prescaler, determines the frequency dividing ratio.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+            </field>
+            <field>
+              <name>SYNC_JUMP_WIDTH</name>
+              <description>Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_1</name>
+          <description>Bus Timing Register 1</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_SEG1</name>
+              <description>The width of PBS1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+            </field>
+            <field>
+              <name>TIME_SEG2</name>
+              <description>The width of PBS2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+            </field>
+            <field>
+              <name>TIME_SAMP</name>
+              <description>The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_LOST_CAP</name>
+          <description>Arbitration Lost Capture Register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ARB_LOST_CAP</name>
+              <description>This register contains information about the bit position of lost arbitration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_CODE_CAP</name>
+          <description>Error Code Capture Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ECC_SEGMENT</name>
+              <description>This register contains information about the location of errors, see Table 181 for details.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_DIRECTION</name>
+              <description>This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_TYPE</name>
+              <description>This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_WARNING_LIMIT</name>
+          <description>Error Warning Limit Register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000060</resetValue>
+          <fields>
+            <field>
+              <name>ERR_WARNING_LIMIT</name>
+              <description>Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_ERR_CNT</name>
+          <description>Receive Error Counter Register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CNT</name>
+              <description>The RX error counter register, reflects value changes under reception status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_ERR_CNT</name>
+          <description>Transmit Error Counter Register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_ERR_CNT</name>
+              <description>The TX error counter register, reflects value changes under transmission status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_0</name>
+          <description>Data register 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_0</name>
+              <description>In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_1</name>
+          <description>Data register 1</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_1</name>
+              <description>In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_2</name>
+          <description>Data register 2</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_2</name>
+              <description>In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_3</name>
+          <description>Data register 3</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_3</name>
+              <description>In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_4</name>
+          <description>Data register 4</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_4</name>
+              <description>In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_5</name>
+          <description>Data register 5</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_5</name>
+              <description>In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_6</name>
+          <description>Data register 6</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_6</name>
+              <description>In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_7</name>
+          <description>Data register 7</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_7</name>
+              <description>In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_8</name>
+          <description>Data register 8</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_8</name>
+              <description>Stored the 8th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_9</name>
+          <description>Data register 9</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_9</name>
+              <description>Stored the 9th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_10</name>
+          <description>Data register 10</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_10</name>
+              <description>Stored the 10th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_11</name>
+          <description>Data register 11</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_11</name>
+              <description>Stored the 11th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_12</name>
+          <description>Data register 12</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_12</name>
+              <description>Stored the 12th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_MESSAGE_CNT</name>
+          <description>Receive Message Counter Register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_MESSAGE_COUNTER</name>
+              <description>This register reflects the number of messages available within the RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_DIVIDER</name>
+          <description>Clock Divider register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CD</name>
+              <description>These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLOCK_OFF</name>
+              <description>This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>UART0</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x3FF40000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x7C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART0</name>
+        <value>34</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>FIFO</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RD_BYTE</name>
+              <description>This register stores one byte data  read by rx fifo.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the parity error of data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects data's frame error .</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the start bit.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter completes  sendding  0 after all the datas in transmitter's fifo are send.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the  last data has been send.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has send all the data in fifo.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when rs485 detects the parity error.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when rs485 detects the data frame error.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ST</name>
+              <description>This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ST</name>
+              <description>This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ST</name>
+              <description>This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ST</name>
+              <description>This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ST</name>
+              <description>This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ST</name>
+              <description>This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ST</name>
+              <description>This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ST</name>
+              <description>This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ST</name>
+              <description>This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ST</name>
+              <description>This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ST</name>
+              <description>This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ST</name>
+              <description>This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ST</name>
+              <description>This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_full_int_st register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_full_int_st register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for parity_err_int_st register.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for frm_err_int_st register.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_ovf_int_st register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ENA</name>
+              <description>This is the enable bit for dsr_chg_int_st register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ENA</name>
+              <description>This is the enable bit for cts_chg_int_st register.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ENA</name>
+              <description>This is the enable bit for brk_det_int_st register.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_tout_int_st register.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ENA</name>
+              <description>This is the enable bit for sw_xon_int_st register.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ENA</name>
+              <description>This is the enable bit for sw_xoff_int_st register.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>This is the enable bit for glitch_det_int_st register.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_done_int_st register.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_idle_done_int_st register.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_done_int_st register.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ENA</name>
+              <description>This is the enable bit for rs485_clash_int_st register.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ENA</name>
+              <description>This is the enable bit for at_cmd_char_det_int_st register.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_full_int_raw interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear txfifo_empty_int_raw interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear parity_err_int_raw interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear frm_err_int_raw interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear rxfifo_ovf_int_raw interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_CLR</name>
+              <description>Set this bit to clear the dsr_chg_int_raw interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear the cts_chg_int_raw interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_CLR</name>
+              <description>Set this bit to clear the brk_det_int_raw interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_tout_int_raw interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_CLR</name>
+              <description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_CLR</name>
+              <description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Set this bit to clear the glitch_det_int_raw interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_done_int_raw interrupt..</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_idle_done_int_raw interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_done_int_raw interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_parity_err_int_raw interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_frm_err_int_raw interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_CLR</name>
+              <description>Set this bit to clear the rs485_clash_int_raw interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_CLR</name>
+              <description>Set this bit to clear the at_cmd_char_det_int_raw interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000002B6</resetValue>
+          <fields>
+            <field>
+              <name>CLKDIV</name>
+              <description>The register value is  the  integer part of the frequency divider's factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRAG</name>
+              <description>The register  value is the decimal part of the frequency divider's factor.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AUTOBAUD</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>This is the enable bit for detecting baudrate.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_FILT</name>
+              <description>when input pulse width is lower then this value igore this pulse.this register is used in autobaud detect process.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>(rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits  rxfifo_cnt stores the 8 least significant bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ST_URX_OUT</name>
+              <description>This register stores the value of receiver's finite state machine. 0:RX_IDLE  1:RX_STRT  2:RX_DAT0  3:RX_DAT1  4:RX_DAT2  5:RX_DAT3  6:RX_DAT4  7:RX_DAT5  8:RX_DAT6  9:RX_DAT7   10:RX_PRTY   11:RX_STP1  12:RX_STP2 13:RX_DL1</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSRN</name>
+              <description>This register stores the level value of the internal uart dsr signal.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTSN</name>
+              <description>This register stores the level value of the internal uart cts signal.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXD</name>
+              <description>This register stores the level value of the internal uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>(tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits  txfifo_cnt stores the 8 least significant bits.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ST_UTX_OUT</name>
+              <description>This register stores the value of transmitter's finite state machine. 0:TX_IDLE  1:TX_STRT  2:TX_DAT0  3:TX_DAT1  4:TX_DAT2   5:TX_DAT3 6:TX_DAT4  7:TX_DAT5  8:TX_DAT6 9:TX_DAT7  10:TX_PRTY   11:TX_STP1  12:TX_STP2  13:TX_DL0   14:TX_DL1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTRN</name>
+              <description>The register represent the level value of the internal uart dsr signal.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTSN</name>
+              <description>This register represent the level value of the internal uart cts signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXD</name>
+              <description>This register represent the  level value of the internal uart rxd signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0800001C</resetValue>
+          <fields>
+            <field>
+              <name>PARITY</name>
+              <description>This register is used to configure the parity check mode.  0:even 1:odd</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_EN</name>
+              <description>Set this bit to enable uart parity check.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIT_NUM</name>
+              <description>This registe is used to set the length of data:  0:5bits 1:6bits 2:7bits 3:8bits</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOP_BIT_NUM</name>
+              <description>This register is used to set the length of  stop bit. 1:1bit  2:1.5bits  3:2bits</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_RTS</name>
+              <description>This register is used to configure the software rts signal which is used in software flow control.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_DTR</name>
+              <description>This register is used to configure the software dtr signal which is used in software flow control..</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_BRK</name>
+              <description>Set this bit to enbale transmitter to  send 0 when the process of sending data is done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_DPLX</name>
+              <description>Set this bit to enable irda loopback mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_EN</name>
+              <description>This is the start enable bit for irda transmitter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_WCTL</name>
+              <description>1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_INV</name>
+              <description>Set this bit to inverse the level value of  irda transmitter's level.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_RX_INV</name>
+              <description>Set this bit to inverse the level value of irda receiver's level.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOPBACK</name>
+              <description>Set this bit to enable uart loopback test mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FLOW_EN</name>
+              <description>Set this bit to enable transmitter's flow control function.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_EN</name>
+              <description>Set this bit to enable irda protocol.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>Set this bit to reset uart receiver's fifo.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_RST</name>
+              <description>Set this bit to reset uart transmitter's fifo.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXD_INV</name>
+              <description>Set this bit to inverse the level value of uart rxd signal.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_INV</name>
+              <description>Set this bit to inverse the level value of uart cts signal.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_INV</name>
+              <description>Set this bit to inverse the level value of uart dsr signal.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_INV</name>
+              <description>Set this bit to inverse the level value of uart txd signal.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTS_INV</name>
+              <description>Set this bit to inverse the level value of uart rts signal.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTR_INV</name>
+              <description>Set this bit to inverse the level value of uart dtr signal.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1.force clock on for registers.support clock only when write registers</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WR_MASK</name>
+              <description>1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the  received data is wrong.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_REF_ALWAYS_ON</name>
+              <description>This register is used to select the clock.1.apb clock 0:ref_tick</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00006060</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_THRHD</name>
+              <description>When receiver receives more data than its threshold value.receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_THRHD</name>
+              <description>when the data amount in transmitter fifo is less than its threshold value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_THRHD</name>
+              <description>when receiver receives more data than its threshold value. receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_EN</name>
+              <description>This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_THRHD</name>
+              <description>This register is used to configure the timeout value for uart receiver receiving a byte.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_EN</name>
+              <description>This is the enble bit for uart receiver's timeout function.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOWPULSE</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores the value of the minimum duration time for the low level pulse. it is used in baudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HIGHPULSE</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores  the value of the maxinum duration time for the high level pulse. it is used in baudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXD_CNT</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXD_EDGE_CNT</name>
+              <description>This register stores the count of rxd edge change. it is used in baudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW_CONF</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_FLOW_CON_EN</name>
+              <description>Set this bit to enable software  flow control. it is used with register sw_xon or sw_xoff .</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XONOFF_DEL</name>
+              <description>Set this bit to remove flow control char from the received data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XON</name>
+              <description>Set this bit to clear ctsn to stop the  transmitter from sending data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XOFF</name>
+              <description>Set this bit to set ctsn to enable the transmitter to go on sending data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XON</name>
+              <description>Set this bit to send xon char. it is cleared by hardware automatically.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XOFF</name>
+              <description>Set this bit to send xoff char. it is cleared by hardware automatically.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000F0</resetValue>
+          <fields>
+            <field>
+              <name>ACTIVE_THRESHOLD</name>
+              <description>When the input rxd edge changes more than this register value. the uart is active from light sleeping mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1311E000</resetValue>
+          <fields>
+            <field>
+              <name>XON_THRESHOLD</name>
+              <description>when the data amount in receiver's fifo is more than this register value. it will send a xoff char with uart_sw_flow_con_en set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_THRESHOLD</name>
+              <description>When the data amount in receiver's fifo is less than this register value. it will send a xon char with uart_sw_flow_con_en set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XON_CHAR</name>
+              <description>This register stores the xon flow control char.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_CHAR</name>
+              <description>This register stores the xoff flow control char.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_CONF</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00A40100</resetValue>
+          <fields>
+            <field>
+              <name>RX_IDLE_THRHD</name>
+              <description>when receiver takes more time than this register value to receive a byte data. it will produce frame end signal for uhci to stop receiving data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between transfers.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_NUM</name>
+              <description>This register is used to configure the num of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RS485_CONF</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RS485_EN</name>
+              <description>Set this bit to choose rs485 mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL0_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL1_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485TX_RX_EN</name>
+              <description>Set this bit to enable loopback transmitter's output data signal to receiver's input data signal.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485RXBY_TX_EN</name>
+              <description>1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_RX_DLY_NUM</name>
+              <description>This register is used to delay the receiver's internal data signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_TX_DLY_NUM</name>
+              <description>This register is used to delay the transmitter's internal data signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_PRECNT</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00186A00</resetValue>
+          <fields>
+            <field>
+              <name>PRE_IDLE_NUM</name>
+              <description>This register is used to configure the idle duration time before the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_POSTCNT</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00186A00</resetValue>
+          <fields>
+            <field>
+              <name>POST_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between the last at_cmd and the next data. when the duration is less than this register value  it will not take the previous data as at_cmd char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_GAPTOUT</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001E00</resetValue>
+          <fields>
+            <field>
+              <name>RX_GAP_TOUT</name>
+              <description>This register is used to configure the duration time between the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_CHAR</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000032B</resetValue>
+          <fields>
+            <field>
+              <name>AT_CMD_CHAR</name>
+              <description>This register is used to configure the content of at_cmd char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAR_NUM</name>
+              <description>This register is used to configure the num of continous at_cmd chars received by receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000088</resetValue>
+          <fields>
+            <field>
+              <name>MEM_PD</name>
+              <description>Set this bit to power down mem.when reg_mem_pd registers in the 3 uarts are all set to 1  mem will enter low power mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SIZE</name>
+              <description>This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SIZE</name>
+              <description>This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_THRHD_H3</name>
+              <description>refer to the rx_flow_thrhd's describtion.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_THRHD_H3</name>
+              <description>refer to the rx_tout_thrhd's describtion.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XON_THRESHOLD_H2</name>
+              <description>refer to the uart_xon_threshold's describtion.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_THRESHOLD_H2</name>
+              <description>refer to the uart_xoff_threshold's describtion.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MEM_FULL_THRHD</name>
+              <description>refer to the rxfifo_full_thrhd's describtion.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MEM_EMPTY_THRHD</name>
+              <description>refer to txfifo_empty_thrhd 's describtion.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_TX_STATUS</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_TX_STATUS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_RX_STATUS</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_RX_STATUS</name>
+              <description>This register stores the current uart rx mem read address  and rx mem write address </description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RX_RD_ADDR</name>
+              <description>This register stores the rx mem read address </description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RX_WR_ADDR</name>
+              <description>This register stores the rx mem write address </description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CNT_STATUS</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_MEM_CNT</name>
+              <description>refer to the rxfifo_cnt's describtion.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_MEM_CNT</name>
+              <description>refer to the txfifo_cnt's describtion.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POSPULSE</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>POSEDGE_MIN_CNT</name>
+              <description>This register stores the count of rxd posedge edge. it is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NEGPULSE</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>NEGEDGE_MIN_CNT</name>
+              <description>This register stores the count of rxd negedge edge. it is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x15122500</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ID</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000500</resetValue>
+          <fields>
+            <field>
+              <name>ID</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <name>UART1</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <baseAddress>0x3FF50000</baseAddress>
+      <interrupt>
+        <name>UART1</name>
+        <value>35</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <name>UART2</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <baseAddress>0x3FF6E000</baseAddress>
+      <interrupt>
+        <name>UART2</name>
+        <value>36</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>UHCI0</name>
+      <description>Universal Host Controller Interface</description>
+      <groupName>UHCI</groupName>
+      <baseAddress>0x3FF54000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xC8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UHCI0</name>
+        <value>12</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF0</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00370100</resetValue>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>Set this bit to reset in link operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_RST</name>
+              <description>Set this bit to reset out link operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_FIFO_RST</name>
+              <description>Set this bit to reset dma ahb fifo.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_RST</name>
+              <description>Set this bit to reset dma  ahb interface.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>Set this bit to enable loop test for in links.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>Set this bit to enable loop test for out links.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>when in link's length is 0  go on to use the next in link automatically.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_NO_RESTART_CLR</name>
+              <description>don't use</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>Set this bit to produce eof after DMA pops all data  clear this bit to produce eof after DMA pushes all data</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_CE</name>
+              <description>Set this bit to use UART to transmit or receive data.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CE</name>
+              <description>Set this bit to use UART1 to transmit or receive data.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART2_CE</name>
+              <description>Set this bit to use UART2 to transmit or receive data.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>Set this bit to enable DMA in links to use burst mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>Set this bit to enable DMA out links to use burst mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <description>Set this bit to enable DMA burst MODE</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_EN</name>
+              <description>Set this bit to use special char to separate the data frame.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HEAD_EN</name>
+              <description>Set this bit to enable to use head packet  before the data frame.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_REC_EN</name>
+              <description>Set this bit to enable receiver''s ability of crc calculation  when crc_en bit in head packet is 1 then there will be crc bytes after data_frame</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_IDLE_EOF_EN</name>
+              <description>Set this bit to enable to use idle time  when the idle time after data frame is satisfied  this means the end of a data frame.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEN_EOF_EN</name>
+              <description>Set this bit to enable to use packet_len in packet head  when the received data is equal to packet_len  this means the end of a data frame.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCODE_CRC_EN</name>
+              <description>Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clock-gating for read or write registers.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RX_BRK_EOF_EN</name>
+              <description>Set this bit to enable to use brk char as the end of a data frame.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_RAW</name>
+              <description>when a separator char has been send  it will produce uhci_rx_start_int interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_RAW</name>
+              <description>when DMA detects a separator char it will produce uhci_tx_start_int interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>when DMA takes a lot of time to receive a data   it will produce uhci_rx_hung_int interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>when DMA takes a lot of time to read a data from RAM  it will produce uhci_tx_hung_int interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_RAW</name>
+              <description>when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_RAW</name>
+              <description>when a data packet has been received  it will produce uhci_in_suc_eof_int interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_RAW</name>
+              <description>when there are some errors about eof in in link descriptor  it will produce uhci_in_err_eof_int interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_RAW</name>
+              <description>when a out link descriptor is completed  it will produce uhci_out_done_int interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <description>when the current descriptor's eof bit is 1  it will produce uhci_out_eof_int interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_RAW</name>
+              <description>when there are some errors about the out link descriptor  it will produce uhci_in_dscr_err_int interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_RAW</name>
+              <description>when there are some errors about the in link descriptor  it will produce uhci_out_dscr_err_int interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_RAW</name>
+              <description>when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_RAW</name>
+              <description>when there are some errors about eof in outlink descriptor  it will produce uhci_outlink_eof_err_int interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_RAW</name>
+              <description>When all data have been send  it will produce uhci_out_total_eof_int interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_Q_INT_RAW</name>
+              <description>When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_Q_INT_RAW</name>
+              <description>When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_WM_INT_RAW</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_ST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_ST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_ST</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ST</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_Q_INT_ST</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_Q_INT_ST</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_WM_INT_ST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_S_Q_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_A_Q_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_WM_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_CLR</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_CLR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_CLR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_CLR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_CLR</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_CLR</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_CLR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_S_Q_INT_CLR</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_A_Q_INT_CLR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_WM_INT_CLR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_STATUS</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>OUT_FULL</name>
+              <description>1:DMA out link descriptor's fifo is full.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EMPTY</name>
+              <description>1:DMA in link descriptor's fifo is empty.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_PUSH</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA</name>
+              <description>This is the data need to be pushed into out link descriptor's fifo.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH</name>
+              <description>Set this bit to push data in out link descriptor's fifo.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_STATUS</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>IN_FULL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EMPTY</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_ERR_CAUSE</name>
+              <description>This register stores the errors caused in out link descriptor's data packet.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_POP</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA</name>
+              <description>This register stores the data pop from in link descriptor's fifo.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP</name>
+              <description>Set this bit to pop data in in link descriptor's fifo.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_LINK</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>This register stores the least 20 bits of the first out link descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set this bit to stop dealing with the out link descriptors.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set this bit to start dealing with the out link descriptors.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set this bit to mount on new out link descriptors</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK</name>
+              <description>1£º the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_LINK</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00100000</resetValue>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>This register stores the least 20 bits of the first in link descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET</name>
+              <description>1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set this bit to stop dealing with the in link descriptors.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set this bit to start dealing with the in link descriptors.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set this bit to mount on new in link descriptors</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_PARK</name>
+              <description>1:the in link descriptor's fsm is in idle state.   0:the in link descriptor's fsm is working</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>CHECK_SUM_EN</name>
+              <description>Set this bit to enable decoder to check  check_sum in packet header.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_SEQ_EN</name>
+              <description>Set this bit to enable decoder to check seq num in packet header.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_DISABLE</name>
+              <description>Set this bit to disable crc calculation.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAVE_HEAD</name>
+              <description>Set this bit to save packet header .</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHECK_SUM_RE</name>
+              <description>Set this bit to enable hardware replace check_sum in packet header automatically.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_ACK_NUM_RE</name>
+              <description>Set this bit to enable hardware replace ack num in packet header automatically.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_OWNER</name>
+              <description>Set this bit to check the owner bit in link descriptor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_SW_START</name>
+              <description>Set this bit to enable software way to add packet header.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_START</name>
+              <description>Set this bit to start inserting the packet header.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_THRS</name>
+              <description>when data amount in link descriptor's fifo is more than this register value  it will produce uhci_dma_infifo_full_wm_int interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE1</name>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_EOF_DES_ADDR</name>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR</name>
+              <description>This register stores the address of out link descriptoir when eof bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_SUC_EOF_DES_ADDR</name>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR</name>
+              <description>This register stores the address of in link descriptor when eof bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_ERR_EOF_DES_ADDR</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_ERR_EOF_DES_ADDR</name>
+              <description>This register stores the address of in link descriptor when there are some errors in this descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_EOF_BFR_DES_ADDR</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR</name>
+              <description>This register stores the address of out link descriptor when there are some errors in this descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_TEST</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHB_TESTMODE</name>
+              <description>bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_TESTADDR</name>
+              <description>The two bits represent ahb bus address bit[20:19]</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_DSCR</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR</name>
+              <description>The content of current in link descriptor's third dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_DSCR_BF0</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0</name>
+              <description>The content of current in link descriptor's first dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_DSCR_BF1</name>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1</name>
+              <description>The content of current in link descriptor's second dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_DSCR</name>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR</name>
+              <description>The content of current out link descriptor's third dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_DSCR_BF0</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0</name>
+              <description>The content of current out link descriptor's first dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_DSCR_BF1</name>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1</name>
+              <description>The content of current out link descriptor's second dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESCAPE_CONF</name>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>TX_C0_ESC_EN</name>
+              <description>Set this bit to enable  0xc0 char decode when DMA receives data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DB_ESC_EN</name>
+              <description>Set this bit to enable  0xdb char decode when DMA receives data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_11_ESC_EN</name>
+              <description>Set this bit to enable  flow control char 0x11 decode when DMA receives data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_13_ESC_EN</name>
+              <description>Set this bit to enable flow control char 0x13 decode when DMA receives data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_C0_ESC_EN</name>
+              <description>Set this bit to enable  0xc0 char replace when DMA sends data.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DB_ESC_EN</name>
+              <description>Set this bit to enable  0xdb char replace when DMA sends data.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_11_ESC_EN</name>
+              <description>Set this bit to enable  flow control char 0x11 replace when DMA sends data.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_13_ESC_EN</name>
+              <description>Set this bit to enable  flow control char 0x13 replace when DMA sends data.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HUNG_CONF</name>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00810810</resetValue>
+          <fields>
+            <field>
+              <name>TXFIFO_TIMEOUT</name>
+              <description>This register stores the timeout value.when DMA takes more time than this register value to receive a data  it will produce  uhci_tx_hung_int interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_SHIFT</name>
+              <description>The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_ENA</name>
+              <description>The enable bit for txfifo receive data  timeout</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT</name>
+              <description>This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM  it will produce  uhci_rx_hung_int interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_SHIFT</name>
+              <description>The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_ENA</name>
+              <description>This is the enable bit for DMA  send data timeout</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACK_NUM</name>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+        </register>
+        <register>
+          <name>RX_HEAD</name>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_HEAD</name>
+              <description>This register stores the packet header received by DMA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUICK_SENT</name>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_SEND_NUM</name>
+              <description>The bits are used to choose which short packet</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SINGLE_SEND_EN</name>
+              <description>Set this bit to enable  send a short packet</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_NUM</name>
+              <description>The bits are used to choose which short packet</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_EN</name>
+              <description>Set this bit to enable continuously send the same short packet</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q0_WORD0</name>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD0</name>
+              <description>This register stores the content of short packet's first dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q0_WORD1</name>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD1</name>
+              <description>This register stores the content of short packet's second dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q1_WORD0</name>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD0</name>
+              <description>This register stores the content of short packet's first dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q1_WORD1</name>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD1</name>
+              <description>This register stores the content of short packet's second dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q2_WORD0</name>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD0</name>
+              <description>This register stores the content of short packet's first dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q2_WORD1</name>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD1</name>
+              <description>This register stores the content of short packet's second dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q3_WORD0</name>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD0</name>
+              <description>This register stores the content of short packet's first dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q3_WORD1</name>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD1</name>
+              <description>This register stores the content of short packet's second dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q4_WORD0</name>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD0</name>
+              <description>This register stores the content of short packet's first dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q4_WORD1</name>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD1</name>
+              <description>This register stores the content of short packet's second dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q5_WORD0</name>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD0</name>
+              <description>This register stores the content of short packet's first dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q5_WORD1</name>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD1</name>
+              <description>This register stores the content of short packet's second dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q6_WORD0</name>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD0</name>
+              <description>This register stores the content of short packet's first dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q6_WORD1</name>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD1</name>
+              <description>This register stores the content of short packet's second dword</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF0</name>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DCDBC0</resetValue>
+          <fields>
+            <field>
+              <name>SEPER_CHAR</name>
+              <description>This register stores the seperator char  seperator char is used to seperate the data frame.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR0</name>
+              <description>This register stores thee first char used to replace seperator char in data.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR1</name>
+              <description>This register stores the second char used to replace seperator char in data . 0xdc 0xdb replace 0xc0 by default.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF1</name>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DDDBDB</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ0</name>
+              <description>This register stores the first substitute char used to replace the seperator char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR0</name>
+              <description>This register stores the first char used to replace reg_esc_seq0 in data.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR1</name>
+              <description>This register stores the second char used to replace the reg_esc_seq0 in data</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF2</name>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DEDB11</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ1</name>
+              <description>This register stores the flow control char to turn on the flow_control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR0</name>
+              <description>This register stores the first char used to replace the reg_esc_seq1 in data.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR1</name>
+              <description>This register stores the second char used to replace the reg_esc_seq1 in data.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF3</name>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DFDB13</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ2</name>
+              <description>This register stores the flow_control char to turn off the flow_control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR0</name>
+              <description>This register stores the first char used to replace the reg_esc_seq2 in data.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR1</name>
+              <description>This register stores  the second char used to replace the reg_esc_seq2 in data.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_THRES</name>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>PKT_THRS</name>
+              <description>when the amount of packet payload is greater than this value the process of receiving data is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x16041001</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UHCI0">
+      <name>UHCI1</name>
+      <description>Universal Host Controller Interface</description>
+      <baseAddress>0x3FF4C000</baseAddress>
+      <interrupt>
+        <name>UHCI1</name>
+        <value>13</value>
+      </interrupt>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/tools/ide-debug/svd/esp32c2.svd b/tools/ide-debug/svd/esp32c2.svd
new file mode 100644
index 00000000000..84aa455b880
--- /dev/null
+++ b/tools/ide-debug/svd/esp32c2.svd
@@ -0,0 +1,20749 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+  <vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
+  <vendorID>ESPRESSIF</vendorID>
+  <name>ESP32-C2</name>
+  <series>ESP32-C2</series>
+  <version>4</version>
+  <description>32-bit RISC-V MCU</description>
+  <licenseText>
+    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+</licenseText>
+  <cpu>
+    <name>RV32IMC</name>
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <nvicPrioBits>4</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>32</addressUnitBits>
+  <width>32</width>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>APB_CTRL</name>
+      <description>Advanced Peripheral Bus Controller</description>
+      <groupName>APB_CTRL</groupName>
+      <baseAddress>0x60026000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>APB_CTRL</name>
+        <value>12</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SYSCLK_CONF</name>
+          <description>APB_CTRL_SYSCLK_CONF_REG</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PRE_DIV_CNT</name>
+              <description>reg_pre_div_cnt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_320M_EN</name>
+              <description>reg_clk_320m_en</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_TICK_CNT</name>
+              <description>reg_rst_tick_cnt</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TICK_CONF</name>
+          <description>APB_CTRL_TICK_CONF_REG</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010727</resetValue>
+          <fields>
+            <field>
+              <name>XTAL_TICK_NUM</name>
+              <description>reg_xtal_tick_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_TICK_NUM</name>
+              <description>reg_ck8m_tick_num</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_ENABLE</name>
+              <description>reg_tick_enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_OUT_EN</name>
+          <description>APB_CTRL_CLK_OUT_EN_REG</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>CLK20_OEN</name>
+              <description>reg_clk20_oen</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK22_OEN</name>
+              <description>reg_clk22_oen</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK44_OEN</name>
+              <description>reg_clk44_oen</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_BB_OEN</name>
+              <description>reg_clk_bb_oen</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK80_OEN</name>
+              <description>reg_clk80_oen</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK160_OEN</name>
+              <description>reg_clk160_oen</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_320M_OEN</name>
+              <description>reg_clk_320m_oen</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_ADC_INF_OEN</name>
+              <description>reg_clk_adc_inf_oen</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DAC_CPU_OEN</name>
+              <description>reg_clk_dac_cpu_oen</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK40X_BB_OEN</name>
+              <description>reg_clk40x_bb_oen</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_XTAL_OEN</name>
+              <description>reg_clk_xtal_oen</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_CFG</name>
+          <description>APB_CTRL_WIFI_BB_CFG_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_CFG</name>
+              <description>reg_wifi_bb_cfg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_CFG_2</name>
+          <description>APB_CTRL_WIFI_BB_CFG_2_REG</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_CFG_2</name>
+              <description>reg_wifi_bb_cfg_2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_CLK_EN</name>
+          <description>APB_CTRL_WIFI_CLK_EN_REG</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFCE030</resetValue>
+          <fields>
+            <field>
+              <name>WIFI_CLK_EN</name>
+              <description>reg_wifi_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_RST_EN</name>
+          <description>APB_CTRL_WIFI_RST_EN_REG</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_RST</name>
+              <description>reg_wifi_rst</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_INF_SEL</name>
+          <description>APB_CTRL_HOST_INF_SEL_REG</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_IO_SWAP</name>
+              <description>reg_peri_io_swap</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_MEM_PMS_LOCK</name>
+          <description>APB_CTRL_EXT_MEM_PMS_LOCK_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_MEM_PMS_LOCK</name>
+              <description>reg_ext_mem_pms_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE0_ATTR</name>
+          <description>APB_CTRL_FLASH_ACE0_ATTR_REG</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE0_ATTR</name>
+              <description>reg_flash_ace0_attr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE1_ATTR</name>
+          <description>APB_CTRL_FLASH_ACE1_ATTR_REG</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE1_ATTR</name>
+              <description>reg_flash_ace1_attr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE2_ATTR</name>
+          <description>APB_CTRL_FLASH_ACE2_ATTR_REG</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE2_ATTR</name>
+              <description>reg_flash_ace2_attr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE3_ATTR</name>
+          <description>APB_CTRL_FLASH_ACE3_ATTR_REG</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE3_ATTR</name>
+              <description>reg_flash_ace3_attr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE0_ADDR</name>
+          <description>APB_CTRL_FLASH_ACE0_ADDR_REG</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>reg_flash_ace0_addr_s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE1_ADDR</name>
+          <description>APB_CTRL_FLASH_ACE1_ADDR_REG</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>reg_flash_ace1_addr_s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE2_ADDR</name>
+          <description>APB_CTRL_FLASH_ACE2_ADDR_REG</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>reg_flash_ace2_addr_s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE3_ADDR</name>
+          <description>APB_CTRL_FLASH_ACE3_ADDR_REG</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C00000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>reg_flash_ace3_addr_s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE0_SIZE</name>
+          <description>APB_CTRL_FLASH_ACE0_SIZE_REG</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000400</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE0_SIZE</name>
+              <description>reg_flash_ace0_size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE1_SIZE</name>
+          <description>APB_CTRL_FLASH_ACE1_SIZE_REG</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000400</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE1_SIZE</name>
+              <description>reg_flash_ace1_size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE2_SIZE</name>
+          <description>APB_CTRL_FLASH_ACE2_SIZE_REG</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000400</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE2_SIZE</name>
+              <description>reg_flash_ace2_size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE3_SIZE</name>
+          <description>APB_CTRL_FLASH_ACE3_SIZE_REG</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000400</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE3_SIZE</name>
+              <description>reg_flash_ace3_size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_PMS_CTRL</name>
+          <description>APB_CTRL_SPI_MEM_PMS_CTRL_REG</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_INT</name>
+              <description>reg_spi_mem_reject_int</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_REJECT_CLR</name>
+              <description>reg_spi_mem_reject_clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_REJECT_CDE</name>
+              <description>reg_spi_mem_reject_cde</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REJECT_ADDR</name>
+          <description>APB_CTRL_SPI_MEM_REJECT_ADDR_REG</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_ADDR</name>
+              <description>reg_spi_mem_reject_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CTRL</name>
+          <description>APB_CTRL_SDIO_CTRL_REG</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_WIN_ACCESS_EN</name>
+              <description>reg_sdio_win_access_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDCY_SIG0_REG</name>
+          <description>APB_CTRL_REDCY_SIG0_REG_REG</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_SIG0</name>
+              <description>reg_redcy_sig0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDCY_ANDOR</name>
+              <description>reg_redcy_andor</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDCY_SIG1_REG</name>
+          <description>APB_CTRL_REDCY_SIG1_REG_REG</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_SIG1</name>
+              <description>reg_redcy_sig1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDCY_NANDOR</name>
+              <description>reg_redcy_nandor</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRONT_END_MEM_PD</name>
+          <description>APB_CTRL_FRONT_END_MEM_PD_REG</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000055</resetValue>
+          <fields>
+            <field>
+              <name>AGC_MEM_FORCE_PU</name>
+              <description>reg_agc_mem_force_pu</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AGC_MEM_FORCE_PD</name>
+              <description>reg_agc_mem_force_pd</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBUS_MEM_FORCE_PU</name>
+              <description>reg_pbus_mem_force_pu</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBUS_MEM_FORCE_PD</name>
+              <description>reg_pbus_mem_force_pd</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DC_MEM_FORCE_PU</name>
+              <description>reg_dc_mem_force_pu</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DC_MEM_FORCE_PD</name>
+              <description>reg_dc_mem_force_pd</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREQ_MEM_FORCE_PU</name>
+              <description>reg_freq_mem_force_pu</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREQ_MEM_FORCE_PD</name>
+              <description>reg_freq_mem_force_pd</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL</name>
+          <description>APB_CTRL_RETENTION_CTRL_REG</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RETENTION_LINK_ADDR</name>
+              <description>reg_retention_link_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NOBYPASS_CPU_ISO_RST</name>
+              <description>reg_nobypass_cpu_iso_rst</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKGATE_FORCE_ON</name>
+          <description>Memory power configuration registers</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>ROM_CLKGATE_FORCE_ON</name>
+              <description>Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_CLKGATE_FORCE_ON</name>
+              <description>Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_POWER_DOWN</name>
+          <description>Memory power configuration registers</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>ROM_POWER_DOWN</name>
+              <description>Set 1 to let rom power down</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_POWER_DOWN</name>
+              <description>Set 1 to let sram power down</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_POWER_UP</name>
+          <description>Memory power configuration registers</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>ROM_POWER_UP</name>
+              <description>Set 1 to let rom power up</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_POWER_UP</name>
+              <description>Set 1 to let sram power up</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RND_DATA</name>
+          <description>APB_CTRL_RND_DATA_REG</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RND_DATA</name>
+              <description>reg_rnd_data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_CONFIG_REG</name>
+          <description>APB_CTRL_PERI_BACKUP_CONFIG_REG_REG</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00006480</resetValue>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_FLOW_ERR</name>
+              <description>reg_peri_backup_flow_err</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_BURST_LIMIT</name>
+              <description>reg_peri_backup_burst_limit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_TOUT_THRES</name>
+              <description>reg_peri_backup_tout_thres</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_SIZE</name>
+              <description>reg_peri_backup_size</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_START</name>
+              <description>reg_peri_backup_start</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_TO_MEM</name>
+              <description>reg_peri_backup_to_mem</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ENA</name>
+              <description>reg_peri_backup_ena</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_APB_ADDR_REG</name>
+          <description>APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_APB_START_ADDR</name>
+              <description>reg_backup_apb_start_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_MEM_ADDR_REG</name>
+          <description>APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_MEM_START_ADDR</name>
+              <description>reg_backup_mem_start_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_RAW</name>
+          <description>APB_CTRL_PERI_BACKUP_INT_RAW_REG</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_DONE_INT_RAW</name>
+              <description>reg_peri_backup_done_int_raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ERR_INT_RAW</name>
+              <description>reg_peri_backup_err_int_raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_ST</name>
+          <description>APB_CTRL_PERI_BACKUP_INT_ST_REG</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_DONE_INT_ST</name>
+              <description>reg_peri_backup_done_int_st</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ERR_INT_ST</name>
+              <description>reg_peri_backup_err_int_st</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_ENA</name>
+          <description>APB_CTRL_PERI_BACKUP_INT_ENA_REG</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_DONE_INT_ENA</name>
+              <description>reg_peri_backup_done_int_ena</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ERR_INT_ENA</name>
+              <description>reg_peri_backup_err_int_ena</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_CLR</name>
+          <description>APB_CTRL_PERI_BACKUP_INT_CLR_REG</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_DONE_INT_CLR</name>
+              <description>reg_peri_backup_done_int_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ERR_INT_CLR</name>
+              <description>reg_peri_backup_err_int_clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>APB_CTRL_DATE_REG</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02106080</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_dateVersion control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>APB_SARADC</name>
+      <description>Successive Approximation Register Analog to Digital Converter</description>
+      <groupName>APB_SARADC</groupName>
+      <baseAddress>0x60040000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>APB_ADC</name>
+        <value>32</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40038240</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_START_FORCE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_START</name>
+              <description>Need add description</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_GATED</name>
+              <description>Need add description</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_DIV</name>
+              <description>SAR clock divider</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_PATT_P_CLEAR</name>
+              <description>clear the pointer of pattern table for DIG ADC1 CTRL</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_XPD_SAR_FORCE</name>
+              <description>force option to xpd sar blocks</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_WAIT_ARB_CYCLE</name>
+              <description>wait arbit signal stable after sar_done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>register description</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000A1FE</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_MEAS_NUM_LIMIT</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_MAX_MEAS_NUM</name>
+              <description>max conversion number</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_INV</name>
+              <description>1: data to DIG ADC1 CTRL is inverted, otherwise not</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_INV</name>
+              <description>1: data to DIG ADC2 CTRL is inverted, otherwise not</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_TARGET</name>
+              <description>to set saradc timer target</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_EN</name>
+              <description>to enable saradc timer trigger</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL1</name>
+          <description>register description</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FILTER_FACTOR1</name>
+              <description>Need add description</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_FACTOR0</name>
+              <description>Need add description</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_WAIT</name>
+          <description>register description</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FF0808</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_XPD_WAIT</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_RSTB_WAIT</name>
+              <description>Need add description</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_STANDBY_WAIT</name>
+              <description>Need add description</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_STATUS</name>
+          <description>register description</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_STATUS</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_STATUS</name>
+          <description>register description</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_STATUS</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PATT_TAB1</name>
+          <description>register description</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PATT_TAB2</name>
+          <description>register description</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ONETIME_SAMPLE</name>
+          <description>register description</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1A000000</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_ONETIME_ATTEN</name>
+              <description>Need add description</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_ONETIME_CHANNEL</name>
+              <description>Need add description</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_ONETIME_START</name>
+              <description>Need add description</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC2_ONETIME_SAMPLE</name>
+              <description>Need add description</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC1_ONETIME_SAMPLE</name>
+              <description>Need add description</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADC_ARB_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000900</resetValue>
+          <fields>
+            <field>
+              <name>ADC_ARB_APB_FORCE</name>
+              <description>adc2 arbiter force to enableapb controller</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_FORCE</name>
+              <description>adc2 arbiter force to enable rtc controller</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_FORCE</name>
+              <description>adc2 arbiter force to enable wifi controller</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_GRANT_FORCE</name>
+              <description>adc2 arbiter force grant</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_APB_PRIORITY</name>
+              <description>Set adc2 arbiterapb priority</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_PRIORITY</name>
+              <description>Set adc2 arbiter rtc priority</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_PRIORITY</name>
+              <description>Set adc2 arbiter wifi priority</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_FIX_PRIORITY</name>
+              <description>adc2 arbiter uses fixed priority</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL0</name>
+          <description>register description</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03740000</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_CHANNEL1</name>
+              <description>Need add description</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_CHANNEL0</name>
+              <description>apb_adc1_filter_factor</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_RESET</name>
+              <description>enable apb_adc1_filter</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1DATA_STATUS</name>
+          <description>register description</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC1_DATA</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2DATA_STATUS</name>
+          <description>register description</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC2_DATA</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES0_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>THRES0_CHANNEL</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH</name>
+              <description>saradc1's thres0 monitor thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_LOW</name>
+              <description>saradc1's thres0 monitor thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES1_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>THRES1_CHANNEL</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH</name>
+              <description>saradc1's thres0 monitor thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES1_LOW</name>
+              <description>saradc1's thres0 monitor thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES_ALL_EN</name>
+              <description>Need add description</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES3_EN</name>
+              <description>Need add description</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES2_EN</name>
+              <description>Need add description</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES1_EN</name>
+              <description>Need add description</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_EN</name>
+              <description>Need add description</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>register description</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES1_LOW_INT_ENA</name>
+              <description>Need add description</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_LOW_INT_ENA</name>
+              <description>Need add description</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH_INT_ENA</name>
+              <description>Need add description</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH_INT_ENA</name>
+              <description>Need add description</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ENA</name>
+              <description>Need add description</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ENA</name>
+              <description>Need add description</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>register description</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES1_LOW_INT_RAW</name>
+              <description>Need add description</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES0_LOW_INT_RAW</name>
+              <description>Need add description</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH_INT_RAW</name>
+              <description>Need add description</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH_INT_RAW</name>
+              <description>Need add description</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_RAW</name>
+              <description>Need add description</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_RAW</name>
+              <description>Need add description</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>register description</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES1_LOW_INT_ST</name>
+              <description>Need add description</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES0_LOW_INT_ST</name>
+              <description>Need add description</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH_INT_ST</name>
+              <description>Need add description</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH_INT_ST</name>
+              <description>Need add description</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ST</name>
+              <description>Need add description</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ST</name>
+              <description>Need add description</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>register description</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES1_LOW_INT_CLR</name>
+              <description>Need add description</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>THRES0_LOW_INT_CLR</name>
+              <description>Need add description</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH_INT_CLR</name>
+              <description>Need add description</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH_INT_CLR</name>
+              <description>Need add description</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_CLR</name>
+              <description>Need add description</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_CLR</name>
+              <description>Need add description</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>APB_ADC_EOF_NUM</name>
+              <description>the dma_in_suc_eof gen when sample cnt = spi_eof_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_RESET_FSM</name>
+              <description>reset_apb_adc_state</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_TRANS</name>
+              <description>enable apb_adc use spi_dma</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADC_CLKM_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>REG_CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_CLKM_DIV_B</name>
+              <description>Fractional clock divider numerator value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_CLKM_DIV_A</name>
+              <description>Fractional clock divider denominator value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Need add description</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_CLK_SEL</name>
+              <description>Set this bit to enable clk_apll</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_TSENS_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>REG_TSENS_OUT</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REG_TSENS_IN_INV</name>
+              <description>Need add description</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_TSENS_CLK_DIV</name>
+              <description>Need add description</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_TSENS_PU</name>
+              <description>Need add description</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_TSENS_CTRL2</name>
+          <description>register description</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004002</resetValue>
+          <fields>
+            <field>
+              <name>REG_TSENS_XPD_WAIT</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_TSENS_XPD_FORCE</name>
+              <description>Need add description</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_TSENS_CLK_INV</name>
+              <description>Need add description</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_SEL</name>
+              <description>Need add description</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALI</name>
+          <description>register description</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>CFG</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_CTRL_DATE</name>
+          <description>register description</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02107210</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ASSIST_DEBUG</name>
+      <description>Debug Assist</description>
+      <groupName>ASSIST_DEBUG</groupName>
+      <baseAddress>0x600CE000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x38</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CORE_0_INTR_ENA</name>
+          <description>core0 monitor enable configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_ENA</name>
+              <description>enbale sp underlow monitor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_ENA</name>
+              <description>enbale sp overflow monitor</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_RAW</name>
+          <description>core0 monitor interrupt status register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_RAW</name>
+              <description>sp underlow monitor interrupt status register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_RAW</name>
+              <description>sp overflow monitor interupt status register</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_RLS</name>
+          <description>core0 monitor interrupt enable register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_RLS</name>
+              <description>enbale sp underlow monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_RLS</name>
+              <description>enbale sp overflow monitor interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_CLR</name>
+          <description>core0 monitor interrupt clr register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_CLR</name>
+              <description>clr sp underlow monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_CLR</name>
+              <description>clr sp overflow monitor interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MIN</name>
+          <description>stack min value</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MIN</name>
+              <description>core0 sp region configuration regsiter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MAX</name>
+          <description>stack max value</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MAX</name>
+              <description>core0 sp pc status register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_PC</name>
+          <description>stack monitor pc status register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_PC</name>
+              <description>This regsiter stores the PC when trigger stack monitor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_EN</name>
+          <description>record enable configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_RECORDEN</name>
+              <description>Set 1 to enable record PC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_RCD_PDEBUGEN</name>
+              <description>Set 1 to enable cpu pdebug function, must set this bit can get cpu PC</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGPC</name>
+          <description>record status regsiter</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGPC</name>
+              <description>recorded PC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGSP</name>
+          <description>record status regsiter</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGSP</name>
+              <description>recorded sp</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_LASTPC_BEFORE_EXCEPTION</name>
+          <description>cpu status register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_LASTPC_BEFORE_EXC</name>
+              <description>cpu's lastpc before exception</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DEBUG_MODE</name>
+          <description>cpu status register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DEBUG_MODE</name>
+              <description>cpu debug mode status, 1 means cpu enter debug mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DEBUG_MODULE_ACTIVE</name>
+              <description>cpu debug_module active status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock gate register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>clock gate register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02106020</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMA</name>
+      <description>DMA (Direct Memory Access) Controller</description>
+      <groupName>DMA</groupName>
+      <baseAddress>0x6003F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x84</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMA_CH0</name>
+        <value>33</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INT_RAW_CH0</name>
+          <description>DMA_INT_RAW_CH0_REG.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_CH0</name>
+          <description>DMA_INT_ST_CH0_REG.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt status bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_CH0</name>
+          <description>DMA_INT_ENA_CH0_REG.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The interrupt enable bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The interrupt enable bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The interrupt enable bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_CH0</name>
+          <description>DMA_INT_CLR_CH0_REG.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>Set this bit to clear the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>Set this bit to clear the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>Set this bit to clear the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_TEST</name>
+          <description>DMA_AHB_TEST_REG.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHB_TESTMODE</name>
+              <description>reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_TESTADDR</name>
+              <description>reserved</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC_CONF</name>
+          <description>DMA_MISC_CONF_REG.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHBM_RST_INTER</name>
+              <description>Set this bit, then clear this bit to reset the internal ahb FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_PRI_DIS</name>
+              <description>Set this bit to disable priority arbitration function.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>DMA_DATE_REG.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02105280</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_CONF0_CH0</name>
+          <description>DMA_IN_CONF0_CH0_REG.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <description>Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_CONF1_CH0</name>
+          <description>DMA_IN_CONF1_CH0_REG.</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INFIFO_STATUS_CH0</name>
+          <description>DMA_INFIFO_STATUS_CH0_REG.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800003</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_FULL</name>
+              <description>L1 Rx FIFO full signal for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_EMPTY</name>
+              <description>L1 Rx FIFO empty signal for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT</name>
+              <description>The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_1B</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_2B</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_3B</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_4B</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_BUF_HUNGRY</name>
+              <description>reserved</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_POP_CH0</name>
+          <description>DMA_IN_POP_CH0_REG.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA</name>
+              <description>This register stores the data popping from DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP</name>
+              <description>Set this bit to pop data from DMA FIFO.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_LINK_CH0</name>
+          <description>DMA_IN_LINK_CH0_REG.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01100000</resetValue>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET</name>
+              <description>Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set this bit to stop dealing with the inlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set this bit to start dealing with the inlink descriptors.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set this bit to mount a new inlink descriptor.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_PARK</name>
+              <description>1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_STATE_CH0</name>
+          <description>DMA_IN_STATE_CH0_REG.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_ADDR</name>
+              <description>This register stores the current inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_SUC_EOF_DES_ADDR_CH0</name>
+          <description>DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_ERR_EOF_DES_ADDR_CH0</name>
+          <description>DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_ERR_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_CH0</name>
+          <description>DMA_IN_DSCR_CH0_REG.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR</name>
+              <description>The address of the current inlink descriptor x.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_BF0_CH0</name>
+          <description>DMA_IN_DSCR_BF0_CH0_REG.</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0</name>
+              <description>The address of the last inlink descriptor x-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_BF1_CH0</name>
+          <description>DMA_IN_DSCR_BF1_CH0_REG.</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_PRI_CH0</name>
+          <description>DMA_IN_PRI_CH0_REG.</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_PRI</name>
+              <description>The priority of Rx channel 0. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_PERI_SEL_CH0</name>
+          <description>DMA_IN_PERI_SEL_CH0_REG.</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_IN_SEL</name>
+              <description>This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_CONF0_CH0</name>
+          <description>DMA_OUT_CONF0_CH0_REG.</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>OUT_RST</name>
+              <description>This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_CONF1_CH0</name>
+          <description>DMA_OUT_CONF1_CH0_REG.</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTFIFO_STATUS_CH0</name>
+          <description>DMA_OUTFIFO_STATUS_CH0_REG.</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800002</resetValue>
+          <fields>
+            <field>
+              <name>OUTFIFO_FULL</name>
+              <description>L1 Tx FIFO full signal for Tx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY</name>
+              <description>L1 Tx FIFO empty signal for Tx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT</name>
+              <description>The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_1B</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_2B</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_3B</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_4B</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PUSH_CH0</name>
+          <description>DMA_OUT_PUSH_CH0_REG.</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA</name>
+              <description>This register stores the data that need to be pushed into DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH</name>
+              <description>Set this bit to push data into DMA FIFO.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_LINK_CH0</name>
+          <description>DMA_OUT_LINK_CH0_REG.</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set this bit to stop dealing with the outlink descriptors.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set this bit to start dealing with the outlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set this bit to restart a new outlink from the last address.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK</name>
+              <description>1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_STATE_CH0</name>
+          <description>DMA_OUT_STATE_CH0_REG.</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_ADDR</name>
+              <description>This register stores the current outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_DES_ADDR_CH0</name>
+          <description>DMA_OUT_EOF_DES_ADDR_CH0_REG.</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_BFR_DES_ADDR_CH0</name>
+          <description>DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor before the last outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_CH0</name>
+          <description>DMA_OUT_DSCR_CH0_REG.</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR</name>
+              <description>The address of the current outlink descriptor y.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_BF0_CH0</name>
+          <description>DMA_OUT_DSCR_BF0_CH0_REG.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0</name>
+              <description>The address of the last outlink descriptor y-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_BF1_CH0</name>
+          <description>DMA_OUT_DSCR_BF1_CH0_REG.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PRI_CH0</name>
+          <description>DMA_OUT_PRI_CH0_REG.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_PRI</name>
+              <description>The priority of Tx channel 0. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PERI_SEL_CH0</name>
+          <description>DMA_OUT_PERI_SEL_CH0_REG.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_OUT_SEL</name>
+              <description>This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ECC</name>
+      <description>ECC (ECC Hardware Accelerator)</description>
+      <groupName>ECC</groupName>
+      <baseAddress>0x6003E000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x18</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>MULT_INT_RAW</name>
+          <description>I2S interrupt raw register, valid in level.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_INT_ST</name>
+          <description>I2S interrupt status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_INT_ENA</name>
+          <description>I2S interrupt enable register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_INT_CLR</name>
+          <description>I2S interrupt clear register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_CONF</name>
+          <description>I2S RX configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>Set this bit to reset receiver</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESET</name>
+              <description>Set this bit to reset Rx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>KEY_LENGTH</name>
+              <description>Set this bit to start receiving data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SECURITY_MODE</name>
+              <description>Set this bit to enable slave receiver mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>clk gate</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WORK_MODE</name>
+              <description>Reserved</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VERIFICATION_RESULT</name>
+              <description>Reserve</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02012230</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>ECC mult version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EFUSE</name>
+      <description>eFuse Controller</description>
+      <groupName>EFUSE</groupName>
+      <baseAddress>0x60008800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xC0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EFUSE</name>
+        <value>20</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PGM_DATA0</name>
+          <description>Register 0 that stores data to be programmed.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_0</name>
+              <description>The content of the 0th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA1</name>
+          <description>Register 1 that stores data to be programmed.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_1</name>
+              <description>The content of the 1st 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA2</name>
+          <description>Register 2 that stores data to be programmed.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_2</name>
+              <description>The content of the 2nd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA3</name>
+          <description>Register 3 that stores data to be programmed.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_3</name>
+              <description>The content of the 3rd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA4</name>
+          <description>Register 4 that stores data to be programmed.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_4</name>
+              <description>The content of the 4th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA5</name>
+          <description>Register 5 that stores data to be programmed.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_5</name>
+              <description>The content of the 5th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA6</name>
+          <description>Register 6 that stores data to be programmed.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_6</name>
+              <description>The content of the 6th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA7</name>
+          <description>Register 7 that stores data to be programmed.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_7</name>
+              <description>The content of the 7th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE0</name>
+          <description>Register 0 that stores the RS code to be programmed.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_0</name>
+              <description>The content of the 0th 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE1</name>
+          <description>Register 1 that stores the RS code to be programmed.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_1</name>
+              <description>The content of the 1st 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE2</name>
+          <description>Register 2 that stores the RS code to be programmed.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_2</name>
+              <description>The content of the 2nd 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_WR_DIS</name>
+          <description>BLOCK0 data register 0.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_DIS</name>
+              <description>Disable programming of individual eFuses.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA0</name>
+          <description>BLOCK0 data register 1.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS</name>
+              <description>The bit be set to disable software read high/low 128-bit of BLK3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL</name>
+              <description>Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG</name>
+              <description>Set this bit to disable pad jtag.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE</name>
+              <description>The bit be set to disable icache in download mode.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>The bit be set to disable manual encryption.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_ENCRYPT_DECRYPT_CNT</name>
+              <description>These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTS_KEY_LENGTH_256</name>
+              <description>The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, XTS_AES use 128-bit eFuse data in BLOCK3.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL</name>
+              <description>Set this bit to disable usb printing.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME</name>
+              <description>Set this bit to force ROM code to send a resume command during SPI boot.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MODE</name>
+              <description>Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DIRECT_BOOT</name>
+              <description>This bit set means disable direct_boot mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD</name>
+              <description>Set this bit to enable secure UART download mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW</name>
+              <description>Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value.  Otherwise, the waiting time is twice the configurable value.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN</name>
+              <description>The bit be set to enable secure boot.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK1_DATA0</name>
+          <description>BLOCK1 data register 0.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTEM_DATA0</name>
+              <description>Stores the bits [0:31] of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK1_DATA1</name>
+          <description>BLOCK1 data register 1.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTEM_DATA1</name>
+              <description>Stores the bits [32:63] of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK1_DATA2</name>
+          <description>BLOCK1 data register 2.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTEM_DATA2</name>
+              <description>Stores the bits [64:87] of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK2_DATA0</name>
+          <description>Register 0 of BLOCK2.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_DATA0</name>
+              <description>Store the bit [0:31] of MAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK2_DATA1</name>
+          <description>Register 1 of BLOCK2.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_ID_HIGH</name>
+              <description>Store the bit [31:47] of MAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAFER_VERSION</name>
+              <description>Store wafer version.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PKG_VERSION</name>
+              <description>Store package version.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK2_EFUSE_VERSION</name>
+              <description>Store efuse version.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RF_REF_I_BIAS_CONFIG</name>
+              <description>Store rf configuration parameters.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LDO_VOL_BIAS_CONFIG_LOW</name>
+              <description>Store the bit [0:2] of ido configuration parameters.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK2_DATA2</name>
+          <description>Register 2 of BLOCK2.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LDO_VOL_BIAS_CONFIG_HIGH</name>
+              <description>Store the bit [3:29] of ido configuration parameters.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PVT_LOW</name>
+              <description>Store the bit [0:4] of pvt.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK2_DATA3</name>
+          <description>Register 3 of BLOCK2.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PVT_HIGH</name>
+              <description>Store the bit [5:14] of pvt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADC_CALIBRATION_0</name>
+              <description>Store the bit [0:21] of ADC calibration data.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK2_DATA4</name>
+          <description>Register 4 of BLOCK2.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC_CALIBRATION_1</name>
+              <description>Store the bit [22:53] of ADC calibration data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK2_DATA5</name>
+          <description>Register 5 of BLOCK2.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC_CALIBRATION_2</name>
+              <description>Store the bit [54:85] of ADC calibration data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK2_DATA6</name>
+          <description>Register 6 of BLOCK2.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC_CALIBRATION_3</name>
+              <description>Store the bit [86:96] of ADC calibration data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK2_RESERVED_DATA_0</name>
+              <description>Store the bit [0:20] of block2 reserved data.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>21</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK2_DATA7</name>
+          <description>Register 7 of BLOCK2.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK2_RESERVED_DATA_1</name>
+              <description>Store the bit [21:52] of block2 reserved data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK3_DATA0</name>
+          <description>Register 0 of BLOCK3.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DATA0</name>
+              <description>Store the first 32-bit of Block3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK3_DATA1</name>
+          <description>Register 1 of BLOCK3.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DATA1</name>
+              <description>Store the second 32-bit of Block3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK3_DATA2</name>
+          <description>Register 2 of BLOCK3.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DATA2</name>
+              <description>Store the third 32-bit of Block3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK3_DATA3</name>
+          <description>Register 3 of BLOCK3.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DATA3</name>
+              <description>Store the fourth 32-bit of Block3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK3_DATA4</name>
+          <description>Register 4 of BLOCK3.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DATA4</name>
+              <description>Store the fifth 32-bit of Block3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK3_DATA5</name>
+          <description>Register 5 of BLOCK3.</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DATA5</name>
+              <description>Store the sixth 32-bit of Block3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK3_DATA6</name>
+          <description>Register 6 of BLOCK3.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DATA6</name>
+              <description>Store the seventh 32-bit of Block3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_BLK3_DATA7</name>
+          <description>Register 7 of BLOCK3.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK3_DATA7</name>
+              <description>Store the eighth 32-bit of Block3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR</name>
+          <description>Programming error record register 0 of BLOCK0.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS_ERR</name>
+              <description>If any bit in RD_DIS is 1, then it indicates a programming error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL_ERR</name>
+              <description>If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG_ERR</name>
+              <description>If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE_ERR</name>
+              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR</name>
+              <description>If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR</name>
+              <description>If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming error.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTS_KEY_LENGTH_256_ERR</name>
+              <description>If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL_ERR</name>
+              <description>If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME_ERR</name>
+              <description>If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MODE_ERR</name>
+              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DIRECT_BOOT_ERR</name>
+              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD_ERR</name>
+              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW_ERR</name>
+              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN_ERR</name>
+              <description>If any bit in this filed is 1, then it indicates a programming error.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED_ERR</name>
+              <description>Reserved.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR</name>
+          <description>Programming error record register 0 of BLOCK1-10.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLK1_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in block1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK1_FAIL</name>
+              <description>0: Means no failure and that the data of block1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in block2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK2_FAIL</name>
+              <description>0: Means no failure and that the data of block2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK3_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in block3.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK3_FAIL</name>
+              <description>0: Means no failure and that the block3 data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>eFuse clcok configuration register.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EFUSE_MEM_FORCE_PD</name>
+              <description>Set this bit to force eFuse SRAM into power-saving mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>Set this bit and force to activate clock signal of eFuse SRAM.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_MEM_FORCE_PU</name>
+              <description>Set this bit to force eFuse SRAM into working mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Set this bit and force to enable clock signal of eFuse memory.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>eFuse operation mode configuraiton register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OP_CODE</name>
+              <description>0x5A5A: Operate programming command 0x5AA5: Operate read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>eFuse status register.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Indicates the state of the eFuse state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_LOAD_SW</name>
+              <description>The value of OTP_LOAD_SW.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_C_SYNC2</name>
+              <description>The value of OTP_VDDQ_C_SYNC2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_STROBE_SW</name>
+              <description>The value of OTP_STROBE_SW.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_CSB_SW</name>
+              <description>The value of OTP_CSB_SW.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_PGENB_SW</name>
+              <description>The value of OTP_PGENB_SW.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_IS_SW</name>
+              <description>The value of OTP_VDDQ_IS_SW.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK0_VALID_BIT_CNT</name>
+              <description>Record the number of bit '1' in BLOCK0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>eFuse command register.</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_CMD</name>
+              <description>Set this bit to send read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_CMD</name>
+              <description>Set this bit to send programming command.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BLK_NUM</name>
+              <description>The serial number of the block to be programmed. Value 0-3 corresponds to block number 0-3, respectively.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>eFuse raw interrupt register.</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_RAW</name>
+              <description>The raw bit signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_RAW</name>
+              <description>The raw bit signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>eFuse interrupt status register.</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ST</name>
+              <description>The status signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ST</name>
+              <description>The status signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>eFuse interrupt enable register.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ENA</name>
+              <description>The enable signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ENA</name>
+              <description>The enable signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>eFuse interrupt clear register.</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_CLR</name>
+              <description>The clear signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_CLR</name>
+              <description>The clear signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAC_CONF</name>
+          <description>Controls the eFuse programming voltage.</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001FE1C</resetValue>
+          <fields>
+            <field>
+              <name>DAC_CLK_DIV</name>
+              <description>Controls the division factor of the rising clock of the programming voltage.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_PAD_SEL</name>
+              <description>Don't care.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_NUM</name>
+              <description>Controls the rising period of the programming voltage.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OE_CLR</name>
+              <description>Reduces the power supply of the programming voltage.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_TIM_CONF</name>
+          <description>Configures read timing parameters.</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x12010201</resetValue>
+          <fields>
+            <field>
+              <name>THR_A</name>
+              <description>Configures hold time for efuse read.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRD</name>
+              <description>Configures pulse time for efuse read.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSUR_A</name>
+              <description>Configures setup time for efuse read.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>READ_INIT_NUM</name>
+              <description>Configures the initial read time of eFuse.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF0</name>
+          <description>Configurarion register 0 of eFuse programming timing parameters.</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C80101</resetValue>
+          <fields>
+            <field>
+              <name>THP_A</name>
+              <description>Configures hold time for efuse program.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TPGM_INACTIVE</name>
+              <description>Configures pulse time for burning '0' bit.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TPGM</name>
+              <description>Configures pulse time for burning '1' bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF1</name>
+          <description>Configurarion register 1 of eFuse programming timing parameters.</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00300001</resetValue>
+          <fields>
+            <field>
+              <name>TSUP_A</name>
+              <description>Configures setup time for efuse program.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWR_ON_NUM</name>
+              <description>Configures the power up time for VDDQ.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF2</name>
+          <description>Configurarion register 2 of eFuse programming timing parameters.</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000190</resetValue>
+          <fields>
+            <field>
+              <name>PWR_OFF_NUM</name>
+              <description>Configures the power outage time for VDDQ.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>eFuse version register.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02108190</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Stores eFuse version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EXTMEM</name>
+      <description>External Memory</description>
+      <groupName>EXTMEM</groupName>
+      <baseAddress>0x600C4000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x94</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>ICACHE_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_ENABLE</name>
+              <description>The bit is used to activate the data cache. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_CTRL1</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_SHUT_IBUS</name>
+              <description>The bit is used to disable core0 ibus, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SHUT_DBUS</name>
+              <description>The bit is used to disable core1 ibus, 0: enable, 1: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_TAG_POWER_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_INVALIDATE_ENA</name>
+              <description>The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SYNC_DONE</name>
+              <description>The bit is used to indicate invalidate operation is finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_ADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_ADDR</name>
+              <description>The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_SIZE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_SIZE</name>
+              <description>The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_TO_FLASH_START_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x42000000</resetValue>
+          <fields>
+            <field>
+              <name>IBUS_TO_FLASH_START_VADDR</name>
+              <description>The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_TO_FLASH_END_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x423FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>IBUS_TO_FLASH_END_VADDR</name>
+              <description>The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_TO_FLASH_START_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3C000000</resetValue>
+          <fields>
+            <field>
+              <name>DBUS_TO_FLASH_START_VADDR</name>
+              <description>The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_TO_FLASH_END_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3C3FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DBUS_TO_FLASH_END_VADDR</name>
+              <description>The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ACS_CNT_CLR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS_ACS_CNT_CLR</name>
+              <description>The bit is used to clear ibus counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_CNT_CLR</name>
+              <description>The bit is used to clear dbus counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ILG_INT_ENA</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_OP_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by sync configurations fault.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_OP_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by preload configurations fault.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by mmu entry fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IBUS_CNT_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt by ibus counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUS_CNT_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt by dbus counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ILG_INT_CLR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_OP_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by sync configurations fault.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_OP_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by preload configurations fault.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by mmu entry fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IBUS_CNT_OVF_INT_CLR</name>
+              <description>The bit is used to clear interrupt by ibus counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DBUS_CNT_OVF_INT_CLR</name>
+              <description>The bit is used to clear interrupt by dbus counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ILG_INT_ST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_OP_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by sync configurations fault.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_OP_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by preload configurations fault.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by mmu entry fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS_ACS_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_FLASH_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus access flash miss counter overflow.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_ACS_CACHE_INT_ENA</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ACS_MSK_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WR_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ACS_MSK_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_WR_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by dbus trying to write icache</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_ACS_CACHE_INT_CLR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ACS_MSK_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WR_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ACS_MSK_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_WR_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by dbus trying to write icache</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_ACS_CACHE_INT_ST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ACS_MSK_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WR_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ACS_MSK_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_WR_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by dbus trying to write icache</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_DBUS_REJECT_ST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_DBUS_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_WORLD</name>
+              <description>The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_DBUS_REJECT_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE0_DBUS_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access dbus when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_IBUS_REJECT_ST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WORLD</name>
+              <description>The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_IBUS_REJECT_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_FAULT_CONTENT</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_FAULT_CONTENT</name>
+              <description>The bits are used to indicate the content of mmu entry which cause mmu fault..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_FAULT_CODE</name>
+              <description>The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_FAULT_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_FAULT_VADDR</name>
+              <description>The bits are used to indicate the virtual address which cause mmu fault..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_WRAP_AROUND_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_FLASH_WRAP_AROUND</name>
+              <description>The bit is used to enable wrap around mode when read data from flash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_POWER_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_MMU_MEM_FORCE_ON</name>
+              <description>The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_MEM_FORCE_PD</name>
+              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_MEM_FORCE_PU</name>
+              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_STATE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_STATE</name>
+              <description>The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_DISABLE_DB_ENCRYPT</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_DISABLE_G0CB_DECRYPT</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>CLK_FORCE_ON_MANUAL_CRYPT</name>
+              <description>The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_FORCE_ON_AUTO_CRYPT</name>
+              <description>The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_FORCE_ON_CRYPT</name>
+              <description>The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_PRELOAD_INT_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by  icache pre-load done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by  icache pre-load done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by  icache pre-load done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SYNC_INT_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by  icache sync done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_SYNC_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by  icache sync done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SYNC_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by  icache sync done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_OWNER</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_OWNER</name>
+              <description>The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CONF_MISC</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT</name>
+              <description>The bit is used to disable checking mmu entry fault by preload operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT</name>
+              <description>The bit is used to disable checking mmu entry fault by sync operation.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_TRACE_ENA</name>
+              <description>The bit is used to enable cache trace function.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_PAGE_SIZE</name>
+              <description>This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_FREEZE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENA</name>
+              <description>The bit is used to enable icache freeze mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DONE</name>
+              <description>The bit is used to indicate icache freeze success</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_ATOMIC_OPERATE_ENA</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_ATOMIC_OPERATE_ENA</name>
+              <description>The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_REQUEST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BYPASS</name>
+              <description>The bit is used to disable request recording which could cause performance issue</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>clock gate enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_DATE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02107050</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <baseAddress>0x60004000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x314</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>GPIO</name>
+        <value>13</value>
+      </interrupt>
+      <interrupt>
+        <name>GPIO_NMI</name>
+        <value>14</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BT_SELECT</name>
+          <description>GPIO bit select register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_SEL</name>
+              <description>GPIO bit select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT</name>
+          <description>GPIO output register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_ORIG</name>
+              <description>GPIO output register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TS</name>
+          <description>GPIO output set register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TS</name>
+              <description>GPIO output set register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TC</name>
+          <description>GPIO output clear register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TC</name>
+              <description>GPIO output clear register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SELECT</name>
+          <description>GPIO sdio select register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_SEL</name>
+              <description>GPIO sdio select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE</name>
+          <description>GPIO output enable register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO output enable register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TS</name>
+          <description>GPIO output enable set register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TS</name>
+              <description>GPIO output enable set register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <description>GPIO output enable clear register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TC</name>
+              <description>GPIO output enable clear register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STRAP</name>
+          <description>pad strapping register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRAPPING</name>
+              <description>pad strapping register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <description>GPIO input register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO input register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>GPIO interrupt status register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>GPIO interrupt status register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TS</name>
+          <description>GPIO interrupt status set register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TS</name>
+              <description>GPIO interrupt status set register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TC</name>
+          <description>GPIO interrupt status clear register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TC</name>
+              <description>GPIO interrupt status clear register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT</name>
+          <description>GPIO PRO_CPU interrupt status register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT</name>
+              <description>GPIO PRO_CPU interrupt status register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT</name>
+          <description>GPIO PRO_CPU(not shielded) interrupt status register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT</name>
+              <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT</name>
+          <description>GPIO CPUSDIO interrupt status register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT</name>
+              <description>GPIO CPUSDIO interrupt status register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>25</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-24</dimIndex>
+          <name>PIN%s</name>
+          <description>GPIO pin configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYNC2_BYPASS</name>
+              <description>set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>set this bit to select pad driver. 1:open-drain. 0:normal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC1_BYPASS</name>
+              <description>set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TYPE</name>
+              <description>set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENABLE</name>
+              <description>set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONFIG</name>
+              <description>reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_ENA</name>
+              <description>set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_NEXT</name>
+          <description>GPIO interrupt source register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INTERRUPT_NEXT</name>
+              <description>GPIO interrupt source register for GPIO0-24</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>128</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-127</dimIndex>
+          <name>FUNC%s_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>25</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-24</dimIndex>
+          <name>FUNC%s_OUT_SEL_CFG</name>
+          <description>GPIO output function select register</description>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>OUT_SEL</name>
+              <description>The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INV_SEL</name>
+              <description>set this bit to invert output signal.1:invert.0:not invert.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_SEL</name>
+              <description>set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_INV_SEL</name>
+              <description>set this bit to invert output enable signal.1:invert.0:not invert.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE_REG</name>
+          <description>GPIO clock gate register</description>
+          <addressOffset>0x62C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>set this bit to enable GPIO clock gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_DATE_REG</name>
+          <description>GPIO version register</description>
+          <addressOffset>0x6FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02106190</resetValue>
+          <fields>
+            <field>
+              <name>REG_DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2C0</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x60013000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C_MST</name>
+        <value>11</value>
+      </interrupt>
+      <interrupt>
+        <name>I2C_EXT0</name>
+        <value>22</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SCL_LOW_PERIOD</name>
+          <description>Configures the low level width of the SCL
+Clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_LOW_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTR</name>
+          <description>Transmission setting</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000020B</resetValue>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>0: direct output, 1: open drain output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>0: direct output, 1: open drain output.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAMPLE_SCL_LEVEL</name>
+              <description>This register is used to select the sample mode.
+1: sample SDA data on the SCL low level.
+0: sample SDA data on the SCL high level.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FULL_ACK_LEVEL</name>
+              <description>This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>Set this bit to configure the module as an I2C Master. Clear this bit to configure the
+module as an I2C Slave.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>Set this bit to start sending the data in txfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>This bit is used to control the sending mode for data needing to be sent.
+1: send data from the least significant bit,
+0: send data from the most significant bit.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>This bit is used to control the storage mode for received data.
+1: receive data from the least significant bit,
+0: receive data from the most significant bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_EN</name>
+              <description>This is the enable bit for arbitration_lost.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FSM_RST</name>
+              <description>This register is used to reset the scl FMS.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPGATE</name>
+              <description>synchronization bit</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_TX_AUTO_START_EN</name>
+              <description>This is the enable bit for slave to send data automatically</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <description>Describe I2C work status.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RESP_REC</name>
+              <description>The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>When the I2C controller loses control of SCL line, this register changes to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>This field represents the amount of data needed to be sent.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>This field stores the amount of received data in RAM.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_STATE_LAST</name>
+              <description>This field indicates the states of the I2C module state machine.
+0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_STATE_LAST</name>
+              <description>This field indicates the states of the state machine used to produce SCL.
+0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TO</name>
+          <description>Setting time out control for receiving data.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TIME_OUT_VALUE</name>
+              <description>This register is used to configure the timeout for receiving a data bit in APB
+clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_EN</name>
+              <description>This is the enable bit for time out control.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_ST</name>
+          <description>FIFO status register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RADDR</name>
+              <description>This is the offset address of the APB reading from rxfifo</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_WADDR</name>
+              <description>This is the offset address of i2c module receiving data and writing to rxfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_RADDR</name>
+              <description>This is the offset address of i2c module reading from txfifo.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WADDR</name>
+              <description>This is the offset address of APB bus writing to txfifo.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_CONF</name>
+          <description>FIFO configuration register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004046</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_EN</name>
+              <description>Set this bit to enable APB nonfifo access.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RST</name>
+              <description>Set this bit to reset rx-fifo.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RST</name>
+              <description>Set this bit to reset tx-fifo.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_PRT_EN</name>
+              <description>The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Rx FIFO read data.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_RDATA</name>
+              <description>The value of rx FIFO read data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <description>Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_CLR</name>
+              <description>Set this bit to clear I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NACK_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS</name>
+          <description>Status of captured I2C communication events</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_HOLD</name>
+          <description>Configures the hold time after a negative SCL edge.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time to hold the data after the negative
+edge of SCL, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_SAMPLE</name>
+          <description>Configures the sample time after a positive SCL edge.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure for how long SDA is sampled, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH_PERIOD</name>
+          <description>Configures the high level width of SCL</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_HIGH_PERIOD</name>
+              <description>This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_WAIT_HIGH_PERIOD</name>
+              <description>This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_HOLD</name>
+          <description>Configures the delay between the SDA and SCL negative edge for a start condition</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the negative edge
+of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_RSTART_SETUP</name>
+          <description>Configures the delay between the positive
+edge of SCL and the negative edge of SDA</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive
+edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_HOLD</name>
+          <description>Configures the delay after the SCL clock
+edge for a stop condition</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the delay after the STOP condition,
+in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_SETUP</name>
+          <description>Configures the delay between the SDA and
+SCL positive edge for a stop condition</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive edge
+of SCL and the positive edge of SDA, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CFG</name>
+          <description>SCL and SDA filter configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000300</resetValue>
+          <fields>
+            <field>
+              <name>SCL_FILTER_THRES</name>
+              <description>When a pulse on the SCL input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_THRES</name>
+              <description>When a pulse on the SDA input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FILTER_EN</name>
+              <description>This is the filter enable bit for SCL.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_EN</name>
+              <description>This is the filter enable bit for SDA.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>I2C CLK configuration register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00200000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>the integral part of the fractional divisor for i2c module</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>the numerator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>the denominator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>The clock selection for i2c module:0-XTAL,1-CLK_8MHz.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_ACTIVE</name>
+              <description>The clock switch for i2c module</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>COMD%s</name>
+          <description>I2C command register %s</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND</name>
+              <description>This is the content of command 0. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND_DONE</name>
+              <description>When command 0 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_ST_TIME_OUT</name>
+          <description>SCL status time out register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_ST_TO_I2C</name>
+              <description>The threshold value of SCL_FSM state unchanged period. It should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_MAIN_ST_TIME_OUT</name>
+          <description>SCL main status time out register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_MAIN_ST_TO_I2C</name>
+              <description>The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_SP_CONF</name>
+          <description>Power configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_RST_SLV_EN</name>
+              <description>When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_RST_SLV_NUM</name>
+              <description>Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_PD_EN</name>
+              <description>The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_PD_EN</name>
+              <description>The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02106243</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXFIFO_START_ADDR</name>
+          <description>I2C TXFIFO base address register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TXFIFO_START_ADDR</name>
+              <description>This is the I2C txfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXFIFO_START_ADDR</name>
+          <description>I2C RXFIFO base address register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_START_ADDR</name>
+              <description>This is the I2C rxfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>INTERRUPT_CORE0</name>
+      <description>Interrupt Core</description>
+      <groupName>INTERRUPT_CORE0</groupName>
+      <baseAddress>0x600C2000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x150</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>MAC_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_MAC_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_MAC_NMI_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_MAC_NMI_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_PWR_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_PWR_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_MAC_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_MAC_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_BB_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_NMI_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_BB_NMI_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_TIMER_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_TIMER_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COEX_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COEX_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLE_TIMER_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLE_TIMER_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLE_SEC_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLE_SEC_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_MST_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_MST_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_CTRL_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_CTRL_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_1_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_INTR_1_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_2_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_INTR_2_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UART_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UART1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LEDC_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LEDC_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EFUSE_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EFUSE_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_CORE_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_CORE_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_EXT0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_EXT0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_T0_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG_T0_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_WDT_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG_WDT_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_IA_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_IA_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET0_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET0_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET1_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET1_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET2_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET2_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REJECT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADC_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_ADC_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CH0_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CH0_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ECC_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ECC_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ASSIST_DEBUG_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ASSIST_DEBUG_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CORE0_ACS_INT_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_CORE0_ACS_INT_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_STATUS_REG_0</name>
+          <description>register description</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_0</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_STATUS_REG_1</name>
+          <description>register description</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_1</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>register description</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>REG_CLK_EN</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_ENABLE</name>
+          <description>register description</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_ENABLE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_TYPE</name>
+          <description>register description</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_TYPE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_CLEAR</name>
+          <description>register description</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_CLEAR</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_EIP_STATUS</name>
+          <description>register description</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_EIP_STATUS</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_0</name>
+          <description>register description</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_0_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_1</name>
+          <description>register description</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_1_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_2</name>
+          <description>register description</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_2_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_3</name>
+          <description>register description</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_3_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_4</name>
+          <description>register description</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_4_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_5</name>
+          <description>register description</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_5_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_6</name>
+          <description>register description</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_6_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_7</name>
+          <description>register description</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_7_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_8</name>
+          <description>register description</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_8_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_9</name>
+          <description>register description</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_9_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_10</name>
+          <description>register description</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_10_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_11</name>
+          <description>register description</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_11_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_12</name>
+          <description>register description</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_12_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_13</name>
+          <description>register description</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_13_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_14</name>
+          <description>register description</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_14_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_15</name>
+          <description>register description</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_15_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_16</name>
+          <description>register description</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_16_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_17</name>
+          <description>register description</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_17_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_18</name>
+          <description>register description</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_18_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_19</name>
+          <description>register description</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_19_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_20</name>
+          <description>register description</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_20_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_21</name>
+          <description>register description</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_21_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_22</name>
+          <description>register description</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_22_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_23</name>
+          <description>register description</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_23_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_24</name>
+          <description>register description</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_24_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_25</name>
+          <description>register description</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_25_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_26</name>
+          <description>register description</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_26_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_27</name>
+          <description>register description</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_27_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_28</name>
+          <description>register description</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_28_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_29</name>
+          <description>register description</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_29_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_30</name>
+          <description>register description</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_30_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_31</name>
+          <description>register description</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_31_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_THRESH</name>
+          <description>register description</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_THRESH</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT_REG_DATE</name>
+          <description>register description</description>
+          <addressOffset>0x7FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02108190</resetValue>
+          <fields>
+            <field>
+              <name>INTERRUPT_REG_DATE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>IO_MUX</name>
+      <description>Input/Output Multiplexer</description>
+      <groupName>IO_MUX</groupName>
+      <baseAddress>0x60009000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x5C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PIN_CTRL</name>
+          <description>Clock Output Configuration Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>CLK_OUT1</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT2</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT3</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>21</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>GPIO%s</name>
+          <description>IO MUX Configure Register for pad XTAL_32K_P</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>IO MUX Version Control Register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02106190</resetValue>
+          <fields>
+            <field>
+              <name>REG_DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LEDC</name>
+      <description>LED PWM (Pulse Width Modulation) Controller</description>
+      <groupName>LEDC</groupName>
+      <baseAddress>0x60019000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LEDC</name>
+        <value>19</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF0</name>
+          <description>Configuration register 0 for channel %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SEL</name>
+              <description>This field is used to select one of timers for channel %s.
+
+0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_OUT_EN</name>
+              <description>Set this bit to enable signal output on channel %s.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_LV</name>
+              <description>This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0).</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_NUM</name>
+              <description>This register is used to configure the maximum times of overflow minus 1.
+
+The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_EN</name>
+              <description>This bit is used to enable the ovf_cnt of channel %s.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_RESET</name>
+              <description>Set this bit to reset the ovf_cnt of channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_HPOINT</name>
+          <description>High point register for channel %s</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HPOINT</name>
+              <description>The output value changes to high when the selected timers has reached the value specified by this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY</name>
+          <description>Initial duty cycle for channel %s</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY</name>
+              <description>This register is used to change the output duty by controlling the Lpoint.
+
+The output value turns to low when the selected timers has reached the Lpoint.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF1</name>
+          <description>Configuration register 1 for channel %s</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_SCALE</name>
+              <description>This register is used to configure the changing step scale of duty on channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CYCLE</name>
+              <description>The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_NUM</name>
+              <description>This register is used to control the number of times the duty cycle will be changed.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_INC</name>
+              <description>This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_START</name>
+              <description>Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY_R</name>
+          <description>Current duty cycle for channel %s</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_CH0_R</name>
+              <description>This register stores the current duty of output signal on channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_CONF</name>
+          <description>Timer %s configuration</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_RES</name>
+              <description>This register is used to control the range of the counter in timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DIV</name>
+              <description>This register is used to configure the divisor for the divider in timer %s.
+
+The least significant eight bits represent the fractional part.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAUSE</name>
+              <description>This bit is used to suspend the counter in timer %s.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>This bit is used to reset timer %s. The counter will show 0 after reset.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_SEL</name>
+              <description>This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.
+
+1'h0: SLOW_CLK 1'h1: REF_TICK</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_VALUE</name>
+          <description>Timer %s current counter value</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>This register stores the current counter value of timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OVF_INT_RAW</name>
+              <description>Triggered when the timer0 has reached its maximum counter value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_RAW</name>
+              <description>Triggered when the timer1 has reached its maximum counter value.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_RAW</name>
+              <description>Triggered when the timer2 has reached its maximum counter value.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_RAW</name>
+              <description>Triggered when the timer3 has reached its maximum counter value.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>Global ledc configuration register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_CLK_SEL</name>
+              <description>This bit is used to select clock source for the 4 timers .
+
+2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19061700</resetValue>
+          <fields>
+            <field>
+              <name>LEDC_DATE</name>
+              <description>This is the version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RNG</name>
+      <description>Hardware random number generator</description>
+      <groupName>RNG</groupName>
+      <baseAddress>0x60026000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>DATA</name>
+          <description>Random number data</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC_CNTL</name>
+      <description>Real Time Controller</description>
+      <groupName>RTC_CNTL</groupName>
+      <baseAddress>0x60008000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x114</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_CORE</name>
+        <value>21</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>OPTIONS0</name>
+          <description>register description</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1000A000</resetValue>
+          <fields>
+            <field>
+              <name>SW_STALL_PROCPU_C0</name>
+              <description>{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_PROCPU_RST</name>
+              <description>PRO CPU SW reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PD</name>
+              <description>BB_I2C force power down</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PU</name>
+              <description>BB_I2C force power up</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PD</name>
+              <description>BB_PLL _I2C force power down</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PU</name>
+              <description>BB_PLL_I2C force power up</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PD</name>
+              <description>BB_PLL force power down</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PU</name>
+              <description>BB_PLL force power up</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PD</name>
+              <description>crystall force power down</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PU</name>
+              <description>crystall force power up</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EN_WAIT</name>
+              <description>wait bias_sleep and current source wakeup</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_ISO</name>
+              <description>Need add desc</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_NOISO</name>
+              <description>Need add desc</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_RST</name>
+              <description>digital wrap force reset in deep sleep</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NORST</name>
+              <description>digital core force no reset in deep sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_SYS_RST</name>
+              <description>SW system reset</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER0</name>
+          <description>register description</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_LO</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER1</name>
+          <description>register description</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_HI</name>
+              <description>RTC sleep timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_ALARM_EN</name>
+              <description>timer alarm enable bit</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_UPDATE</name>
+          <description>register description</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SYS_STALL</name>
+              <description>Enable to record system stall time</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_XTL_OFF</name>
+              <description>Enable to record 40M XTAL OFF time</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_SYS_RST</name>
+              <description>enable to record system reset time</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_UPDATE</name>
+              <description>Set 1: to update register with RTC timer</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_LOW0</name>
+          <description>register description</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE0_LOW</name>
+              <description>RTC timer low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_HIGH0</name>
+          <description>register description</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE0_HIGH</name>
+              <description>RTC timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <description>register description</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_CPU_INT</name>
+              <description>rtc software interrupt to main cpu</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_CAUSE_CLR</name>
+              <description>clear rtc sleep reject cause</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB2RTC_BRIDGE_SEL</name>
+              <description>1: APB to RTC using bridge</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_ACTIVE_IND</name>
+              <description>SDIO active indication</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_WAKEUP</name>
+              <description>leep wakeup bit</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT</name>
+              <description>leep reject bit</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_EN</name>
+              <description>sleep enable bit</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1</name>
+          <description>register description</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x28140403</resetValue>
+          <fields>
+            <field>
+              <name>CPU_STALL_EN</name>
+              <description>CPU stall enable bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_STALL_WAIT</name>
+              <description>CPU stall wait cycles in fast_clk_rtc</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_WAIT</name>
+              <description>CK8M wait cycles in slow_clk_rtc</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_BUF_WAIT</name>
+              <description>XTAL wait cycles in slow_clk_rtc</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_BUF_WAIT</name>
+              <description>PLL wait cycles in slow_clk_rtc</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2</name>
+          <description>register description</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000000</resetValue>
+          <fields>
+            <field>
+              <name>MIN_TIME_CK8M_OFF</name>
+              <description>minimal cycles in slow_clk_rtc for CK8M in power down state</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER4</name>
+          <description>register description</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10200000</resetValue>
+          <fields>
+            <field>
+              <name>DG_WRAP_WAIT_TIMER</name>
+              <description>Need add desc</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_POWERUP_TIMER</name>
+              <description>Need add desc</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER5</name>
+          <description>register description</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MIN_SLP_VAL</name>
+              <description>minimal sleep cycles in slow_clk_rtc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ANA_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00440000</resetValue>
+          <fields>
+            <field>
+              <name>I2C_RESET_POR_FORCE_PD</name>
+              <description>Need add desc</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RESET_POR_FORCE_PU</name>
+              <description>Need add desc</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_PU</name>
+              <description>PLLA force power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_SLP_START</name>
+              <description>start BBPLL calibration during sleep</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXRF_I2C_PU</name>
+              <description>1: TXRF_I2C power up</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RFRX_PBUS_PU</name>
+              <description>1: RFRX_PBUS power up</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CKGEN_I2C_PU</name>
+              <description>1: CKGEN_I2C power up</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_I2C_PU</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLA_FORCE_PD</name>
+              <description>PLLA force power down</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLA_FORCE_PU</name>
+              <description>PLLA force power up</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESET_STATE</name>
+          <description>register description</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002000</resetValue>
+          <fields>
+            <field>
+              <name>RESET_CAUSE_PROCPU</name>
+              <description>reset cause of PRO CPU</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STAT_VECTOR_SEL_PROCPU</name>
+              <description>PRO CPU state vector sel</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OCD_HALT_ON_RESET_PROCPU</name>
+              <description>PROCPU OcdHaltOnReset</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRESET_MASK_PROCPU</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP_STATE</name>
+          <description>register description</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00060000</resetValue>
+          <fields>
+            <field>
+              <name>WAKEUP_ENA</name>
+              <description>wakeup enable bitmap</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC</name>
+          <description>register description</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA</name>
+              <description>enable sleep wakeup interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA</name>
+              <description>enable sleep reject interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>enable RTC WDT interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA</name>
+              <description>enable brown out interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA</name>
+              <description>enable RTC main timer interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>SWD_INT_ENA</name>
+              <description>enable super watch dog interrupt</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_ENA</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_RTC</name>
+          <description>register description</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_RAW</name>
+              <description>sleep wakeup interrupt raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_RAW</name>
+              <description>sleep reject interrupt raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>RTC WDT interrupt raw</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_RAW</name>
+              <description>brown out interrupt raw</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_RAW</name>
+              <description>RTC main timer interrupt raw</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_INT_RAW</name>
+              <description>super watch dog interrupt raw</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_RAW</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_RTC</name>
+          <description>register description</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ST</name>
+              <description>sleep wakeup interrupt state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ST</name>
+              <description>sleep reject interrupt state</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>RTC WDT interrupt state</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ST</name>
+              <description>brown out interrupt state</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ST</name>
+              <description>RTC main timer interrupt state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_INT_ST</name>
+              <description>super watch dog interrupt state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_ST</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_RTC</name>
+          <description>register description</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_CLR</name>
+              <description>Clear sleep wakeup interrupt state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_CLR</name>
+              <description>Clear sleep reject interrupt state</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Clear RTC WDT interrupt state</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_CLR</name>
+              <description>Clear brown out interrupt state</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_CLR</name>
+              <description>Clear RTC main timer interrupt state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_INT_CLR</name>
+              <description>Clear super watch dog interrupt state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_CLR</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE0</name>
+          <description>register description</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH0</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE1</name>
+          <description>register description</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH1</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE2</name>
+          <description>register description</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH2</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE3</name>
+          <description>register description</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH3</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_XTL_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XTL_EXT_CTR_LV</name>
+              <description>0: power down XTAL at high level</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_EN</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_WAKEUP_FILTER</name>
+              <description>enable filter for gpio wakeup event</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_REJECT_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLEEP_REJECT_ENA</name>
+              <description>sleep reject enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LIGHT_SLP_REJECT_EN</name>
+              <description>enable reject for light sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEEP_SLP_REJECT_EN</name>
+              <description>enable reject for deep sleep</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERIOD_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPUSEL_CONF</name>
+              <description>CPU sel option</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x11583218</resetValue>
+          <fields>
+            <field>
+              <name>EFUSE_CLK_FORCE_GATING</name>
+              <description>Need add desc</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_CLK_FORCE_NOGATING</name>
+              <description>Need add desc</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV_SEL_VLD</name>
+              <description>used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV</name>
+              <description>CK8M_D256_OUT divider. 00: div128</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_CK8M</name>
+              <description>disable CK8M and CK8M_D256_OUT</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_CK8M_DIV</name>
+              <description>1: CK8M_D256_OUT is actually CK8M</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_XTAL32K_EN</name>
+              <description>enable CK_XTAL_32K for digital core (no relationship with RTC core)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_D256_EN</name>
+              <description>enable CK8M_D256_OUT for digital core (no relationship with RTC core)</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_EN</name>
+              <description>enable CK8M for digital core (no relationship with RTC core)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV_SEL</name>
+              <description>divider = reg_ck8m_div_sel + 1</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_FORCE_NOGATING</name>
+              <description>XTAL force no gating during sleep</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_NOGATING</name>
+              <description>CK8M force no gating during sleep</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DFREQ</name>
+              <description>CK8M_DFREQ</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PD</name>
+              <description>CK8M force power down</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PU</name>
+              <description>CK8M force power up</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_GLOBAL_FORCE_GATING</name>
+              <description>Need add desc</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_GLOBAL_FORCE_NOGATING</name>
+              <description>Need add desc</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_CLK_RTC_SEL</name>
+              <description>fast_clk_rtc sel. 0: XTAL div 4</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANA_CLK_RTC_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLOW_CLK_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>ANA_CLK_DIV_VLD</name>
+              <description>used to sync div bus. clear vld before set reg_rtc_ana_clk_div</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANA_CLK_DIV</name>
+              <description>Need add desc</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOW_CLK_NEXT_EDGE</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BIAS_CONF</name>
+          <description>register description</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010800</resetValue>
+          <fields>
+            <field>
+              <name>DG_VDD_DRV_B_SLP</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_VDD_DRV_B_SLP_EN</name>
+              <description>Need add desc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_IDLE</name>
+              <description>Need add desc</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_WAKE</name>
+              <description>Need add desc</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_DEEP_SLP</name>
+              <description>Need add desc</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_MONITOR</name>
+              <description>Need add desc</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_CUR_DEEP_SLP</name>
+              <description>xpd cur when rtc in sleep_state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_CUR_MONITOR</name>
+              <description>xpd cur when rtc in monitor state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_SLEEP_DEEP_SLP</name>
+              <description>bias_sleep when rtc in sleep_state</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_SLEEP_MONITOR</name>
+              <description>bias_sleep when rtc in monitor state</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_DEEP_SLP</name>
+              <description>DBG_ATTEN when rtc in sleep state</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_MONITOR</name>
+              <description>DBG_ATTEN when rtc in active state</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_ACTIVE</name>
+              <description>Need add desc</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_CNTL</name>
+          <description>register description</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>DIG_REG_CAL_EN</name>
+              <description>Need add desc</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCK_DCAP</name>
+              <description>SCK_DCAP</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGULATOR_FORCE_PD</name>
+              <description>RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGULATOR_FORCE_PU</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWC</name>
+          <description>register description</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PAD_FORCE_HOLD</name>
+              <description>rtc pad force hold</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PWC</name>
+          <description>register description</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00100020</resetValue>
+          <fields>
+            <field>
+              <name>VDD_SPI_PWR_DRV</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VDD_SPI_PWR_FORCE</name>
+              <description>Need add desc</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VDD_SPI_PD_EN</name>
+              <description>Need add desc</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSLP_MEM_FORCE_PD</name>
+              <description>memories in digital core force PD in sleep</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSLP_MEM_FORCE_PU</name>
+              <description>memories in digital core force no PD in sleep</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PD</name>
+              <description>digital core force power down</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PU</name>
+              <description>digital core force power up</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_PD_EN</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_ISO</name>
+          <description>register description</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80005080</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_OFF</name>
+              <description>Need add desc</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_ON</name>
+              <description>Need add desc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD</name>
+              <description>read only register to indicate digital pad auto-hold status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLR_DG_PAD_AUTOHOLD</name>
+              <description>wtite only register to clear digital pad auto-hold</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD_EN</name>
+              <description>digital pad enable auto-hold</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_NOISO</name>
+              <description>digital pad force no ISO</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_ISO</name>
+              <description>digital pad force ISO</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_UNHOLD</name>
+              <description>digital pad force un-hold</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_HOLD</name>
+              <description>digital pad force hold</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_ISO</name>
+              <description>digital core force ISO</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NOISO</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>register description</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013214</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CHIP_RESET_WIDTH</name>
+              <description>chip reset siginal pulse width</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CHIP_RESET_EN</name>
+              <description>wdt reset whole chip enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PAUSE_IN_SLP</name>
+              <description>pause WDT in sleep</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>enable WDT reset PRO CPU</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>enable WDT in flash boot</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>system reset counter length</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>CPU reset counter length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>1: interrupt stage en</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>1: interrupt stage en</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>1: interrupt stage en</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>1: interrupt stage en</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>register description</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030D40</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>register description</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013880</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>register description</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>register description</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>register description</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>register description</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_CONF</name>
+          <description>register description</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x04B00000</resetValue>
+          <fields>
+            <field>
+              <name>SWD_RESET_FLAG</name>
+              <description>swd reset flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_FEED_INT</name>
+              <description>swd interrupt for feeding</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_BYPASS_RST</name>
+              <description>Need add desc</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_SIGNAL_WIDTH</name>
+              <description>adjust signal width send to swd</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_RST_FLAG_CLR</name>
+              <description>reset swd reset flag</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_FEED</name>
+              <description>Sw feed swd</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_DISABLE</name>
+              <description>disabel SWD</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_AUTO_FEED_EN</name>
+              <description>automatically feed swd when int comes</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_WPROTECT</name>
+          <description>register description</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SWD_WKEY</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SW_CPU_STALL</name>
+          <description>register description</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_STALL_PROCPU_C1</name>
+              <description>Need add desc</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE4</name>
+          <description>register description</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH4</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE5</name>
+          <description>register description</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH5</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE6</name>
+          <description>register description</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH6</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE7</name>
+          <description>register description</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH7</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOW_POWER_ST</name>
+          <description>register description</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XPD_DIG</name>
+              <description>digital wrap power down</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_START</name>
+              <description>touch should start to work</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_SWITCH</name>
+              <description>touch is about to working. Switch rtc main state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_SLP</name>
+              <description>touch is in sleep state</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_DONE</name>
+              <description>touch is done</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_START</name>
+              <description>ulp/cocpu should start to work</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_SWITCH</name>
+              <description>ulp/cocpu is about to working. Switch rtc main state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_SLP</name>
+              <description>ulp/cocpu is in sleep state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_DONE</name>
+              <description>ulp/cocpu is done</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_XTAL_ISO</name>
+              <description>no use any more</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_PLL_ON</name>
+              <description>rtc main state machine is in states that pll should be running</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDY_FOR_WAKEUP</name>
+              <description>rtc is ready to receive wake up trigger from wake up source</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_WAIT_END</name>
+              <description>rtc main state machine has been waited for some cycles</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_WAKEUP_STATE</name>
+              <description>rtc main state machine is in the states of wakeup process</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOW_POWER_STATE</name>
+              <description>rtc main state machine is in the states of low power</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_8M</name>
+              <description>rtc main state machine is in wait 8m state</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_PLL</name>
+              <description>rtc main state machine is in wait pll state</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_XTL</name>
+              <description>rtc main state machine is in wait xtal state</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_SLP</name>
+              <description>rtc main state machine is in sleep state</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_IDLE</name>
+              <description>rtc main state machine is in idle state</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_STATE</name>
+              <description>rtc main state machine status</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIAG0</name>
+          <description>register description</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOW_POWER_DIAG1</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_HOLD</name>
+          <description>register description</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_PIN0_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PAD_HOLD</name>
+          <description>register description</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIG_PAD_HOLD</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BROWN_OUT</name>
+          <description>register description</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x43FF0010</resetValue>
+          <fields>
+            <field>
+              <name>BROWN_OUT_INT_WAIT</name>
+              <description>brown out interrupt wait cycles</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_CLOSE_FLASH_ENA</name>
+              <description>enable close flash when brown out happens</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_PD_RF_ENA</name>
+              <description>enable power down RF when brown out happens</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_RST_WAIT</name>
+              <description>brown out reset wait cycles</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_RST_ENA</name>
+              <description>enable brown out reset</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_RST_SEL</name>
+              <description>1:  4-pos reset</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_ANA_RST_EN</name>
+              <description>Need add desc</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_CNT_CLR</name>
+              <description>clear brown out counter</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_ENA</name>
+              <description>enable brown out</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_LOW1</name>
+          <description>register description</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE1_LOW</name>
+              <description>RTC timer low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_HIGH1</name>
+          <description>register description</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE1_HIGH</name>
+              <description>RTC timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_CONF</name>
+          <description>register description</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IO_MUX_RESET_DISABLE</name>
+              <description>Need add desc</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_REJECT_CAUSE</name>
+          <description>register description</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REJECT_CAUSE</name>
+              <description>sleep reject cause</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OPTION1</name>
+          <description>register description</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FORCE_DOWNLOAD_BOOT</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CAUSE</name>
+          <description>register description</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WAKEUP_CAUSE</name>
+              <description>sleep wakeup cause</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_TIMER_1</name>
+          <description>register description</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C800</resetValue>
+          <fields>
+            <field>
+              <name>ULP_CP_TIMER_SLP_CYCLE</name>
+              <description>sleep cycles for ULP-coprocessor timer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC_W1TS</name>
+          <description>register description</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA_W1TS</name>
+              <description>enable sleep wakeup interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA_W1TS</name>
+              <description>enable sleep reject interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA_W1TS</name>
+              <description>enable RTC WDT interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA_W1TS</name>
+              <description>enable brown out interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA_W1TS</name>
+              <description>enable RTC main timer interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_INT_ENA_W1TS</name>
+              <description>enable super watch dog interrupt</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_ENA_W1TS</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC_W1TC</name>
+          <description>register description</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA_W1TC</name>
+              <description>enable sleep wakeup interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA_W1TC</name>
+              <description>enable sleep reject interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA_W1TC</name>
+              <description>enable RTC WDT interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA_W1TC</name>
+              <description>enable brown out interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA_W1TC</name>
+              <description>enable RTC main timer interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_INT_ENA_W1TC</name>
+              <description>enable super watch dog interrupt</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_ENA_W1TC</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNTL_RETENTION_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xA0D00000</resetValue>
+          <fields>
+            <field>
+              <name>RETENTION_CLK_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_DONE_WAIT</name>
+              <description>Need add desc</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_CLKOFF_WAIT</name>
+              <description>Need add desc</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_EN</name>
+              <description>Need add desc</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_WAIT</name>
+              <description>wait cycles for rention operation</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIB_SEL</name>
+          <description>register description</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>FIB_SEL</name>
+              <description>select use analog fib signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNTL_GPIO_WAKEUP</name>
+          <description>register description</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_WAKEUP_STATUS</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_WAKEUP_STATUS_CLR</name>
+              <description>Need add desc</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN_CLK_GATE</name>
+              <description>Need add desc</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_INT_TYPE</name>
+              <description>Need add desc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_INT_TYPE</name>
+              <description>Need add desc</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_INT_TYPE</name>
+              <description>Need add desc</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_INT_TYPE</name>
+              <description>Need add desc</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_INT_TYPE</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_INT_TYPE</name>
+              <description>Need add desc</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_WAKEUP_ENABLE</name>
+              <description>Need add desc</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_WAKEUP_ENABLE</name>
+              <description>Need add desc</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_WAKEUP_ENABLE</name>
+              <description>Need add desc</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_WAKEUP_ENABLE</name>
+              <description>Need add desc</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_WAKEUP_ENABLE</name>
+              <description>Need add desc</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_WAKEUP_ENABLE</name>
+              <description>Need add desc</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNTL_DBG_SEL</name>
+          <description>register description</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DEBUG_12M_NO_GATING</name>
+              <description>Need add desc</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_BIT_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL0</name>
+              <description>Need add desc</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL1</name>
+              <description>Need add desc</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL2</name>
+              <description>Need add desc</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL3</name>
+              <description>Need add desc</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL4</name>
+              <description>Need add desc</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNTL_DBG_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_PIN5_MUX_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_MUX_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_MUX_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_MUX_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_MUX_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_MUX_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_FUN_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_FUN_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_FUN_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_FUN_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_FUN_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_FUN_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNTL_SENSOR_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR2_PWDET_CCT</name>
+              <description>Need add desc</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XPD_SAR</name>
+              <description>Need add desc</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNTL_DBG_SAR_SEL</name>
+          <description>register description</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_DEBUG_SEL</name>
+              <description>Need add desc</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CNTL_DATE</name>
+          <description>register description</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02107190</resetValue>
+          <fields>
+            <field>
+              <name>CNTL_DATE</name>
+              <description>Need add desc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SENSITIVE</name>
+      <description>Sensitive</description>
+      <groupName>SENSITIVE</groupName>
+      <baseAddress>0x600C1000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x48</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>ROM_TABLE_LOCK</name>
+          <description>register description</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ROM_TABLE_LOCK</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_TABLE</name>
+          <description>register description</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ROM_TABLE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_ACCESS_0</name>
+          <description>register description</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_PERIPHERAL_ACCESS_LOCK</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_ACCESS_1</name>
+          <description>register description</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>APB_PERIPHERAL_ACCESS_SPLIT_BURST</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_0</name>
+          <description>register description</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_LOCK</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_1</name>
+          <description>register description</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_CPU_CACHE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_CPU_SRAM</name>
+              <description>Need add description</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_3</name>
+          <description>register description</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_ALLOC_MAC_DUMP</name>
+              <description>Need add description</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_ACCESS_0</name>
+          <description>register description</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_TAG_ACCESS_LOCK</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_ACCESS_1</name>
+          <description>register description</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I_TAG_RD_ACS</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_I_TAG_WR_ACS</name>
+              <description>Need add description</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_D_TAG_RD_ACS</name>
+              <description>Need add description</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_D_TAG_WR_ACS</name>
+              <description>Need add description</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_ACCESS_0</name>
+          <description>register description</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_ACCESS_LOCK</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_ACCESS_1</name>
+          <description>register description</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MMU_RD_ACS</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_MMU_WR_ACS</name>
+              <description>Need add description</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIF_ACCESS_MONITOR_0</name>
+          <description>register description</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PIF_ACCESS_MONITOR_LOCK</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIF_ACCESS_MONITOR_1</name>
+          <description>register description</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN</name>
+              <description>Need add description</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIF_ACCESS_MONITOR_2</name>
+          <description>register description</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE</name>
+              <description>Need add description</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIF_ACCESS_MONITOR_3</name>
+          <description>register description</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTS_AES_KEY_UPDATE</name>
+          <description>register description</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XTS_AES_KEY_UPDATE</name>
+              <description>Set this bit to update xts_aes key</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>register description</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SENSITIVE_REG_DATE</name>
+          <description>register description</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02106301</resetValue>
+          <fields>
+            <field>
+              <name>SENSITIVE_REG_DATE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SHA</name>
+      <description>SHA (Secure Hash Algorithm) Accelerator</description>
+      <groupName>SHA</groupName>
+      <baseAddress>0x6003B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SHA</name>
+        <value>34</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Initial configuration register.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Sha mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_STRING</name>
+          <description>SHA 512/t configuration register 0.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_STRING</name>
+              <description>Sha t_string (used if and only if mode == SHA_512/t).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_LENGTH</name>
+          <description>SHA 512/t configuration register 1.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LENGTH</name>
+              <description>Sha t_length (used if and only if mode == SHA_512/t).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_BLOCK_NUM</name>
+          <description>DMA configuration register 0.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_BLOCK_NUM</name>
+              <description>Dma-sha block number.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>START</name>
+          <description>Typical SHA configuration register 0.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE</name>
+          <description>Typical SHA configuration register 1.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSY</name>
+          <description>Busy register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Sha busy state. 1'b0: idle. 1'b1: busy.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_START</name>
+          <description>DMA configuration register 1.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_START</name>
+              <description>Start dma-sha.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONTINUE</name>
+          <description>DMA configuration register 2.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CONTINUE</name>
+              <description>Continue dma-sha.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR_IRQ</name>
+          <description>Interrupt clear register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>Clear sha interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IRQ_ENA</name>
+          <description>Interrupt enable register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT_ENA</name>
+              <description>Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200616</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Sha date information/ sha version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>H_MEM[%s]</name>
+          <description>Sha H memory which contains intermediate hash or finial hash.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>Sha M memory which contains message.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI0</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI0</groupName>
+      <baseAddress>0x60003000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x48</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI_MEM_REJECT_CACHE</name>
+        <value>29</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>SPI0 control register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x002C2000</resetValue>
+          <fields>
+            <field>
+              <name>FDUMMY_OUT</name>
+              <description>In the dummy phase the signal level of spi is output by the spi controller.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Apply 2 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTRD_MODE</name>
+              <description>This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DIO</name>
+              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QIO</name>
+              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL1</name>
+          <description>SPI0 control1 register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>SPI0 RX FIFO reset signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>SPI0 control2 register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000021</resetValue>
+          <fields>
+            <field>
+              <name>CS_SETUP_TIME</name>
+              <description>(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_TIME</name>
+              <description>Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_DELAY</name>
+              <description>These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC_RESET</name>
+              <description>The FSM will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI clock division control register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>Set this bit in 1-division mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI0 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI0 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI0 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of  command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_STATUS</name>
+          <description>SPI0 read control register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI0 misc register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRANS_END</name>
+              <description>The bit is used to indicate the  spi0_mst_st controlled transmitting is done.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_END_INT_ENA</name>
+              <description>The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CSPI_ST_TRANS_END</name>
+              <description>The bit is used to indicate the  spi0_slv_st controlled transmitting is done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CSPI_ST_TRANS_END_INT_ENA</name>
+              <description>The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_FCTRL</name>
+          <description>SPI0 bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_REQ_EN</name>
+              <description>For SPI0, Cache access enable, 1: enable, 0:disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_USR_ADDR_4BYTE</name>
+              <description>For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_FLASH_USR_CMD</name>
+              <description>For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_DUAL</name>
+              <description>For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_DUAL</name>
+              <description>For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_QUAD</name>
+              <description>For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_QUAD</name>
+              <description>For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM</name>
+          <description>SPI0 FSM status register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>CSPI_ST</name>
+              <description>The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EM_ST</name>
+              <description>The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CSPI_LOCK_DELAY_TIME</name>
+              <description>The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMING_CALI</name>
+          <description>SPI0 timing calibration register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMING_CLK_ENA</name>
+              <description>The bit is used to enable timing adjust clock for all reading operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMING_CALI</name>
+              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EXTRA_DUMMY_CYCLELEN</name>
+              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_MODE</name>
+          <description>SPI0 input delay mode control register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN1_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN2_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN3_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_NUM</name>
+          <description>SPI0 input delay number control register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN1_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN2_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN3_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOUT_MODE</name>
+          <description>SPI0 output delay mode control register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DOUT0_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT1_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT2_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT3_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>SPI0 clk_gate register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_CLK_SEL</name>
+          <description>SPI0 module clock select register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI01_CLK_SEL</name>
+              <description>When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02106191</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI1</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI1</groupName>
+      <baseAddress>0x60002000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CMD</name>
+          <description>SPI1 memory command register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI1_MST_ST</name>
+              <description>The current status of SPI1 master FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MSPI_ST</name>
+              <description>The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_PE</name>
+              <description>In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_HPM</name>
+              <description>Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RES</name>
+              <description>This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_DP</name>
+              <description>Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_CE</name>
+              <description>Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_BE</name>
+              <description>Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_SE</name>
+              <description>Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PP</name>
+              <description>Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WRSR</name>
+              <description>Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RDSR</name>
+              <description>Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RDID</name>
+              <description>Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WRDI</name>
+              <description>Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WREN</name>
+              <description>Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_READ</name>
+              <description>Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI1 address register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_ADDR_VALUE</name>
+              <description>In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>SPI1 control register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x002CA000</resetValue>
+          <fields>
+            <field>
+              <name>FDUMMY_OUT</name>
+              <description>In the dummy phase the signal level of spi is output by the spi controller.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Apply 2 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCS_CRC_EN</name>
+              <description>For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CRC_EN</name>
+              <description>For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTRD_MODE</name>
+              <description>This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESANDRES</name>
+              <description>The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WRSR_2B</name>
+              <description>two bytes data will be written to status register when it is set. 1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DIO</name>
+              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QIO</name>
+              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL1</name>
+          <description>SPI1 control1 register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFC</resetValue>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_DLY_RES</name>
+              <description>After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>SPI1 control2 register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYNC_RESET</name>
+              <description>The FSM will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI1 clock division control register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>reserved</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI1 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DIO</name>
+              <description>In the write operations address phase and read-data phase apply 2 signals.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QIO</name>
+              <description>In the write operations address phase and read-data phase apply 4 signals.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>SPI clock is disable in dummy phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR</name>
+              <description>This bit enable the address phase of an operation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI1 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI1 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of  command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MOSI_DLEN</name>
+          <description>SPI1 send data bit length control register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MOSI_DBITLEN</name>
+              <description>The length in bits of write-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISO_DLEN</name>
+          <description>SPI1 receive data bit length control register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MISO_DBITLEN</name>
+              <description>The length in bits of  read-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_STATUS</name>
+          <description>SPI1 status register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI1 misc register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>CS0_DIS</name>
+              <description>SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS1_DIS</name>
+              <description>SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CRC</name>
+          <description>SPI1 TX CRC data register.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>For SPI1, the value of crc32.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_FCTRL</name>
+          <description>SPI1 bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_USR_ADDR_4BYTE</name>
+              <description>For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_DUAL</name>
+              <description>For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_DUAL</name>
+              <description>For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_QUAD</name>
+              <description>For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_QUAD</name>
+              <description>For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W0</name>
+          <description>SPI1 memory data buffer0</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W1</name>
+          <description>SPI1 memory data buffer1</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W2</name>
+          <description>SPI1 memory data buffer2</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W3</name>
+          <description>SPI1 memory data buffer3</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W4</name>
+          <description>SPI1 memory data buffer4</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W5</name>
+          <description>SPI1 memory data buffer5</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W6</name>
+          <description>SPI1 memory data buffer6</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W7</name>
+          <description>SPI1 memory data buffer7</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W8</name>
+          <description>SPI1 memory data buffer8</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W9</name>
+          <description>SPI1 memory data buffer9</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W10</name>
+          <description>SPI1 memory data buffer10</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W11</name>
+          <description>SPI1 memory data buffer11</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W12</name>
+          <description>SPI1 memory data buffer12</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W13</name>
+          <description>SPI1 memory data buffer13</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W14</name>
+          <description>SPI1 memory data buffer14</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W15</name>
+          <description>SPI1 memory data buffer15</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_WAITI_CTRL</name>
+          <description>SPI1 wait idle control register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000014</resetValue>
+          <fields>
+            <field>
+              <name>WAITI_DUMMY</name>
+              <description>The dummy phase enable when wait flash idle (RDSR)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAITI_CMD</name>
+              <description>The command to wait flash idle(RDSR).</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAITI_DUMMY_CYCLELEN</name>
+              <description>The dummy cycle length when wait flash idle(RDSR).</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_SUS_CTRL</name>
+          <description>SPI1 flash suspend control register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08002000</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_PER</name>
+              <description>program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES</name>
+              <description>program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PER_WAIT_EN</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_WAIT_EN</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PES_PER_EN</name>
+              <description>Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_EN</name>
+              <description>Set this bit to enable Auto-suspending function.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PESR_END_MSK</name>
+              <description>The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_RD_SUS_2B</name>
+              <description>1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PER_END_EN</name>
+              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PES_END_EN</name>
+              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUS_TIMEOUT_CNT</name>
+              <description>When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_SUS_CMD</name>
+          <description>SPI1 flash suspend command register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0005757A</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_PER_COMMAND</name>
+              <description>Program/Erase resume command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_COMMAND</name>
+              <description>Program/Erase suspend command.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_PESR_COMMAND</name>
+              <description>Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SUS_STATUS</name>
+          <description>SPI1 flash suspend status register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FLASH_SUS</name>
+              <description>The status of flash suspend, only used in SPI1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_PESR_CMD_2B</name>
+              <description>1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_HPM_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RES_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_DP_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PER_DLY_128</name>
+              <description>Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_DLY_128</name>
+              <description>Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI0_LOCK_EN</name>
+              <description>1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMING_CALI</name>
+          <description>SPI1 timing control register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMING_CALI</name>
+              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EXTRA_DUMMY_CYCLELEN</name>
+              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>SPI1 interrupt enable register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PES_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WPE_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>SPI1 interrupt clear register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PES_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WPE_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_CLR</name>
+              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>SPI1 interrupt raw register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PES_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WPE_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>SPI1 interrupt status register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PES_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WPE_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ST</name>
+              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>SPI1 clk_gate register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02107013</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI2</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI2</groupName>
+      <baseAddress>0x60024000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x98</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI_INTR_1</name>
+        <value>15</value>
+      </interrupt>
+      <interrupt>
+        <name>SPI_INTR_2</name>
+        <value>16</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CMD</name>
+          <description>Command control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONF_BITLEN</name>
+              <description>Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UPDATE</name>
+              <description>Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address value register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_ADDR_VALUE</name>
+              <description>Address to slave. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>SPI control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003C0000</resetValue>
+          <fields>
+            <field>
+              <name>DUMMY_OUT</name>
+              <description>0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_OCT</name>
+              <description>Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_OCT</name>
+              <description>Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_OCT</name>
+              <description>In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD_POL</name>
+              <description>SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP_POL</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_BIT_ORDER</name>
+              <description>In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WR_BIT_ORDER</name>
+              <description>In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI clock control register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80003043</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKDIV_PRE</name>
+              <description>In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI USER control register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x800000C0</resetValue>
+          <fields>
+            <field>
+              <name>DOUTDIN</name>
+              <description>Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>QPI_MODE</name>
+              <description>Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OPI_MODE</name>
+              <description>Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals. Can be configured in CONF state.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_OCT</name>
+              <description>In the write operations read-data phase apply 8 signals. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_CONF_NXT</name>
+              <description>1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIO</name>
+              <description>Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR</name>
+              <description>This bit enable the address phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI USER control register 1</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xB8410007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_WFULL_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP_TIME</name>
+              <description>(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_TIME</name>
+              <description>delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI USER control register 2</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x78000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of  command. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_REMPTY_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MS_DLEN</name>
+          <description>SPI data bit length control register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MS_DATA_BITLEN</name>
+              <description>The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI misc register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003E</resetValue>
+          <fields>
+            <field>
+              <name>CS0_DIS</name>
+              <description>SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS1_DIS</name>
+              <description>SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS2_DIS</name>
+              <description>SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS3_DIS</name>
+              <description>SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS4_DIS</name>
+              <description>SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS5_DIS</name>
+              <description>SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_DIS</name>
+              <description>1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_CS_POL</name>
+              <description>In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DATA_DTR_EN</name>
+              <description>1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DATA_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDR_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMD_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_CS_POL</name>
+              <description>spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DQS_IDLE_EDGE</name>
+              <description>The default value of spi_dqs. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>QUAD_DIN_PIN_SWAP</name>
+              <description>1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_MODE</name>
+          <description>SPI input delay mode configuration</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN1_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN2_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN3_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN4_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN5_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN6_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN7_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMING_HCLK_ACTIVE</name>
+              <description>1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_NUM</name>
+          <description>SPI input delay number configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN1_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN2_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN3_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN4_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN5_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN6_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIN7_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOUT_MODE</name>
+          <description>SPI output delay mode configuration</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DOUT0_MODE</name>
+              <description>The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT1_MODE</name>
+              <description>The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT2_MODE</name>
+              <description>The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT3_MODE</name>
+              <description>The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT4_MODE</name>
+              <description>The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT5_MODE</name>
+              <description>The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT6_MODE</name>
+              <description>The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DOUT7_MODE</name>
+              <description>The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_DQS_MODE</name>
+              <description>The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>SPI DMA control register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY</name>
+              <description>Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL</name>
+              <description>Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_SLV_SEG_TRANS_EN</name>
+              <description>Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_TX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_EOF_EN</name>
+              <description>1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled receive data mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled send data mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_AFIFO_RST</name>
+              <description>Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BUF_AFIFO_RST</name>
+              <description>Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_AFIFO_RST</name>
+              <description>Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ENA</name>
+          <description>SPI interrupt enable register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_ENA</name>
+              <description>The enable bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP2_INT_ENA</name>
+              <description>The enable bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP1_INT_ENA</name>
+              <description>The enable bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_CLR</name>
+          <description>SPI interrupt clear register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_CLR</name>
+              <description>The clear bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_CLR</name>
+              <description>The clear bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_CLR</name>
+              <description>The clear bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_RAW</name>
+          <description>SPI interrupt raw register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_RAW</name>
+              <description>The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_RAW</name>
+              <description>The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_RAW</name>
+              <description>The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ST</name>
+          <description>SPI interrupt status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_ST</name>
+              <description>The status bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_ST</name>
+              <description>The status bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_ST</name>
+              <description>The status bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_ST</name>
+              <description>The status bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_ST</name>
+              <description>The status bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_ST</name>
+              <description>The status bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_ST</name>
+              <description>The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_ST</name>
+              <description>The status bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_ST</name>
+              <description>The status bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_SET</name>
+          <description>SPI interrupt software set register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_SET</name>
+              <description>The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_SET</name>
+              <description>The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_SET</name>
+              <description>The software set bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_SET</name>
+              <description>The software set bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_SET</name>
+              <description>The software set bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_SET</name>
+              <description>The software set bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_SET</name>
+              <description>The software set bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_SET</name>
+              <description>The software set bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_SET</name>
+              <description>The software set bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_SET</name>
+              <description>The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_SET</name>
+              <description>The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_SET</name>
+              <description>The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_SET</name>
+              <description>The software set bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_SET</name>
+              <description>The software set bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W0</name>
+          <description>SPI CPU-controlled buffer0</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W1</name>
+          <description>SPI CPU-controlled buffer1</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W2</name>
+          <description>SPI CPU-controlled buffer2</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W3</name>
+          <description>SPI CPU-controlled buffer3</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W4</name>
+          <description>SPI CPU-controlled buffer4</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W5</name>
+          <description>SPI CPU-controlled buffer5</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W6</name>
+          <description>SPI CPU-controlled buffer6</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W7</name>
+          <description>SPI CPU-controlled buffer7</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W8</name>
+          <description>SPI CPU-controlled buffer8</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W9</name>
+          <description>SPI CPU-controlled buffer9</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W10</name>
+          <description>SPI CPU-controlled buffer10</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W11</name>
+          <description>SPI CPU-controlled buffer11</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W12</name>
+          <description>SPI CPU-controlled buffer12</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W13</name>
+          <description>SPI CPU-controlled buffer13</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W14</name>
+          <description>SPI CPU-controlled buffer14</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W15</name>
+          <description>SPI CPU-controlled buffer15</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE</name>
+          <description>SPI slave control register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02800000</resetValue>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_MODE_13</name>
+              <description>{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSCK_DATA_OUT</name>
+              <description>It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_MAGIC_VALUE</name>
+              <description>The magic value of BM table in master DMA seg-trans.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Set SPI work mode. 1: slave mode 0: master mode.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOFT_RESET</name>
+              <description>Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USR_CONF</name>
+              <description>1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE1</name>
+          <description>SPI slave control register 1</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_DATA_BITLEN</name>
+              <description>The transferred data bit length in SPI slave FD and HD mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_COMMAND</name>
+              <description>In the slave mode it is the value of command.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_ADDR</name>
+              <description>In the slave mode it is the value of address.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_GATE</name>
+          <description>SPI module clock and register clock control</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_CLK_ACTIVE</name>
+              <description>Set this bit to power on the SPI module clock.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_CLK_SEL</name>
+              <description>This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02106070</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SYSTEM</name>
+      <description>System</description>
+      <groupName>SYSTEM</groupName>
+      <baseAddress>0x600C0000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CPU_PERI_CLK_EN</name>
+          <description>cpu_peripheral clock gating register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN_ASSIST_DEBUG</name>
+              <description>Set 1 to open assist_debug module clock</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN_DEDICATED_GPIO</name>
+              <description>Set 1 to open dedicated_gpio module clk</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_RST_EN</name>
+          <description>cpu_peripheral reset register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000C0</resetValue>
+          <fields>
+            <field>
+              <name>RST_EN_ASSIST_DEBUG</name>
+              <description>Set 1 to let assist_debug module reset</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_EN_DEDICATED_GPIO</name>
+              <description>Set 1 to let dedicated_gpio module reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PER_CONF</name>
+          <description>cpu clock config register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000C</resetValue>
+          <fields>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <description>This field used to sel cpu clock frequent.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FREQ_SEL</name>
+              <description>This field used to sel pll frequent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_WAIT_MODE_FORCE_ON</name>
+              <description>Set 1 to force cpu_waiti_clk enable.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_WAITI_DELAY_NUM</name>
+              <description>This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_PD_MASK</name>
+          <description>memory power down mask register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>LSLP_MEM_PD_MASK</name>
+              <description>Set 1 to mask memory power down.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_CLK_EN0</name>
+          <description>peripheral clock gating register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x71002066</resetValue>
+          <fields>
+            <field>
+              <name>SPI01_CLK_EN</name>
+              <description>Set 1 to enable SPI01 clock</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_CLK_EN</name>
+              <description>Set 1 to enable UART clock</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CLK_EN</name>
+              <description>Set 1 to enable UART1 clock</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_CLK_EN</name>
+              <description>Set 1 to enable SPI2 clock</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT0_CLK_EN</name>
+              <description>Set 1 to enable I2C_EXT0 clock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_CLK_EN</name>
+              <description>Set 1 to enable LEDC clock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_CLK_EN</name>
+              <description>Set 1 to enable TIMERGROUP clock</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_CLK_EN</name>
+              <description>Set 1 to enable UART_MEM clock</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_CLK_EN</name>
+              <description>Set 1 to enable APB_SARADC clock</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_CLK_EN</name>
+              <description>Set 1 to enable SYSTEMTIMER clock</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_ARB_CLK_EN</name>
+              <description>Set 1 to enable ADC2_ARB clock</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_CLK_EN1</name>
+          <description>peripheral clock gating register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CRYPTO_ECC_CLK_EN</name>
+              <description>Set 1 to enable ECC clock</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_SHA_CLK_EN</name>
+              <description>Set 1 to enable SHA clock</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_CLK_EN</name>
+              <description>Set 1 to enable DMA clock</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_EN</name>
+              <description>Set 1 to enable TSENS clock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_RST_EN0</name>
+          <description>reserved</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI01_RST</name>
+              <description>Set 1 to let SPI01 reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RST</name>
+              <description>Set 1 to let UART reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_RST</name>
+              <description>Set 1 to let UART1 reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_RST</name>
+              <description>Set 1 to let SPI2 reset</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT0_RST</name>
+              <description>Set 1 to let I2C_EXT0 reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_RST</name>
+              <description>Set 1 to let LEDC reset</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_RST</name>
+              <description>Set 1 to let TIMERGROUP reset</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_RST</name>
+              <description>Set 1 to let UART_MEM reset</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_RST</name>
+              <description>Set 1 to let APB_SARADC reset</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_RST</name>
+              <description>Set 1 to let SYSTIMER reset</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_ARB_RST</name>
+              <description>Set 1 to let ADC2_ARB reset</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_RST_EN1</name>
+          <description>peripheral reset register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000046</resetValue>
+          <fields>
+            <field>
+              <name>CRYPTO_ECC_RST</name>
+              <description>Set 1 to let CRYPTO_ECC reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_SHA_RST</name>
+              <description>Set 1 to let CRYPTO_SHA reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RST</name>
+              <description>Set 1 to let DMA reset</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_RST</name>
+              <description>Set 1 to let TSENS reset</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_LPCK_DIV_INT</name>
+          <description>clock config register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>BT_LPCK_DIV_NUM</name>
+              <description>This field is lower power clock frequent division factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_LPCK_DIV_FRAC</name>
+          <description>low power clock configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02001001</resetValue>
+          <fields>
+            <field>
+              <name>BT_LPCK_DIV_B</name>
+              <description>This field is lower power clock frequent division factor b</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_LPCK_DIV_A</name>
+              <description>This field is lower power clock frequent division factor a</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_RTC_SLOW</name>
+              <description>Set 1 to select rtc-slow clock as rtc low power clock</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_8M</name>
+              <description>Set 1 to select 8m clock as rtc low power clock</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL</name>
+              <description>Set 1 to select xtal clock as rtc low power clock</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL32K</name>
+              <description>Set 1 to select xtal32k clock as low power clock</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_RTC_EN</name>
+              <description>Set 1 to enable RTC low power clock</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0</name>
+          <description>interrupt generate register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0</name>
+              <description>Set 1 to generate cpu interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1</name>
+          <description>interrupt generate register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1</name>
+              <description>Set 1 to generate cpu interrupt 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2</name>
+          <description>interrupt generate register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2</name>
+              <description>Set 1 to generate cpu interrupt 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3</name>
+          <description>interrupt generate register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3</name>
+              <description>Set 1 to generate cpu interrupt 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_PD_CTRL</name>
+          <description>rsa memory power control register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RSA_MEM_PD</name>
+              <description>Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA. This bit is invalid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PU</name>
+              <description>Set 1 to force power up RSA memory. This bit has the second highest priority.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PD</name>
+              <description>Set 1 to force power down RSA memory. This bit has the highest priority.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_CTRL</name>
+          <description>edma clcok and reset register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>EDMA_CLK_ON</name>
+              <description>Set 1 to enable EDMA clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EDMA_RESET</name>
+              <description>Set 1 to let EDMA reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CONTROL</name>
+          <description>cache control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_CLK_ON</name>
+              <description>Set 1 to enable icache clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_RESET</name>
+              <description>Set 1 to let icache reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_CLK_ON</name>
+              <description>Set 1 to enable dcache clock</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_RESET</name>
+              <description>Set 1 to let dcache reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL</name>
+          <description>SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_SPI_MANUAL_ENCRYPT</name>
+              <description>Set 1 to enable the SPI manual encrypt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_DB_ENCRYPT</name>
+              <description>Set 1 to enable download DB encrypt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_G0CB_DECRYPT</name>
+              <description>Set 1 to enable download G0CB decrypt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>Set 1 to enable download manual encrypt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_FASTMEM_CONFIG</name>
+          <description>fast memory config register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7FF00000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_MEM_CRC_START</name>
+              <description>Set 1 to start the CRC of RTC memory</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_ADDR</name>
+              <description>This field is used to set address of RTC memory for CRC.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_LEN</name>
+              <description>This field is used to set length of RTC memory for CRC based on start address.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_FINISH</name>
+              <description>This bit stores the status of RTC memory CRC.1 means finished.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_FASTMEM_CRC</name>
+          <description>reserved</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_MEM_CRC_RES</name>
+              <description>This field stores the CRC result of RTC memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDUNDANT_ECO_CTRL</name>
+          <description>eco register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDUNDANT_ECO_DRIVE</name>
+              <description>reg_redundant_eco_drive</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDUNDANT_ECO_RESULT</name>
+              <description>reg_redundant_eco_result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock gating register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSCLK_CONF</name>
+          <description>system clock config register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PRE_DIV_CNT</name>
+              <description>This field is used to set the count of prescaler of XTAL_CLK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOC_CLK_SEL</name>
+              <description>This field is used to select soc clock.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_XTAL_FREQ</name>
+              <description>This field is used to read xtal frequency in MHz.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLK_DIV_EN</name>
+              <description>reg_clk_div_en</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_PVT</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>MEM_PATH_LEN</name>
+              <description>reg_mem_path_len</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_ERR_CNT_CLR</name>
+              <description>reg_mem_err_cnt_clr</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MONITOR_EN</name>
+              <description>reg_mem_pvt_monitor_en</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TIMING_ERR_CNT</name>
+              <description>reg_mem_timing_err_cnt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_VT_SEL</name>
+              <description>reg_mem_vt_sel</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_LVT_CONF</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>COMB_PATH_LEN_LVT</name>
+              <description>reg_comb_path_len_lvt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMB_ERR_CNT_CLR_LVT</name>
+              <description>reg_comb_err_cnt_clr_lvt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COMB_PVT_MONITOR_EN_LVT</name>
+              <description>reg_comb_pvt_monitor_en_lvt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_NVT_CONF</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>COMB_PATH_LEN_NVT</name>
+              <description>reg_comb_path_len_nvt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMB_ERR_CNT_CLR_NVT</name>
+              <description>reg_comb_err_cnt_clr_nvt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COMB_PVT_MONITOR_EN_NVT</name>
+              <description>reg_comb_pvt_monitor_en_nvt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_HVT_CONF</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>COMB_PATH_LEN_HVT</name>
+              <description>reg_comb_path_len_hvt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMB_ERR_CNT_CLR_HVT</name>
+              <description>reg_comb_err_cnt_clr_hvt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COMB_PVT_MONITOR_EN_HVT</name>
+              <description>reg_comb_pvt_monitor_en_hvt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE0</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE0</name>
+              <description>reg_comb_timing_err_cnt_lvt_site0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE0</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE0</name>
+              <description>reg_comb_timing_err_cnt_nvt_site0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE0</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE0</name>
+              <description>reg_comb_timing_err_cnt_hvt_site0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE1</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE1</name>
+              <description>reg_comb_timing_err_cnt_lvt_site1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE1</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE1</name>
+              <description>reg_comb_timing_err_cnt_nvt_site1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE1</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE1</name>
+              <description>reg_comb_timing_err_cnt_hvt_site1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE2</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE2</name>
+              <description>reg_comb_timing_err_cnt_lvt_site2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE2</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE2</name>
+              <description>reg_comb_timing_err_cnt_nvt_site2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE2</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE2</name>
+              <description>reg_comb_timing_err_cnt_hvt_site2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE3</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE3</name>
+              <description>reg_comb_timing_err_cnt_lvt_site3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE3</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE3</name>
+              <description>reg_comb_timing_err_cnt_nvt_site3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE3</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE3</name>
+              <description>reg_comb_timing_err_cnt_hvt_site3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02108190</resetValue>
+          <fields>
+            <field>
+              <name>SYSTEM_REG_DATE</name>
+              <description>reg_system_reg_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SYSTIMER</name>
+      <description>System Timer</description>
+      <groupName>SYSTIMER</groupName>
+      <baseAddress>0x60023000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x78</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSTIMER_TARGET0</name>
+        <value>26</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET1</name>
+        <value>27</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET2</name>
+        <value>28</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF</name>
+          <description>Configure system timer clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x46000000</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_CLK_FO</name>
+              <description>systimer clock force on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_WORK_EN</name>
+              <description>target2 work enable</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_WORK_EN</name>
+              <description>target1 work enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_WORK_EN</name>
+              <description>target0 work enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE1_STALL_EN</name>
+              <description>If timer unit1 is stalled when core1 stalled</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE0_STALL_EN</name>
+              <description>If timer unit1 is stalled when core0 stalled</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE1_STALL_EN</name>
+              <description>If timer unit0 is stalled when core1 stalled</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE0_STALL_EN</name>
+              <description>If timer unit0 is stalled when core0 stalled</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_WORK_EN</name>
+              <description>timer unit1 work enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_WORK_EN</name>
+              <description>timer unit0 work enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>register file clk gating</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_OP</name>
+          <description>system timer unit0 value update register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_VALID</name>
+              <description>timer value is sync and valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_UPDATE</name>
+              <description>update timer_unit0</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_OP</name>
+          <description>system timer unit1 value update register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_VALID</name>
+              <description>timer value is sync and valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_UPDATE</name>
+              <description>update timer unit1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_HI</name>
+          <description>system timer unit0 value high load register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_HI</name>
+              <description>timer unit0 load high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_LO</name>
+          <description>system timer unit0 value low load register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_LO</name>
+              <description>timer unit0 load low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_HI</name>
+          <description>system timer unit1 value high load register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_HI</name>
+              <description>timer unit1 load high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_LO</name>
+          <description>system timer unit1 value low load register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_LO</name>
+              <description>timer unit1 load low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_HI</name>
+          <description>system timer comp0 value high register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_HI</name>
+              <description>timer taget0 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_LO</name>
+          <description>system timer comp0 value low register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_LO</name>
+              <description>timer taget0 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_HI</name>
+          <description>system timer comp1 value high register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_HI</name>
+              <description>timer taget1 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_LO</name>
+          <description>system timer comp1 value low register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_LO</name>
+              <description>timer taget1 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_HI</name>
+          <description>system timer comp2 value high register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_HI</name>
+              <description>timer taget2 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_LO</name>
+          <description>system timer comp2 value low register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_LO</name>
+              <description>timer taget2 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_CONF</name>
+          <description>system timer comp0 target mode register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_PERIOD</name>
+              <description>target0 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_PERIOD_MODE</name>
+              <description>Set target0 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_CONF</name>
+          <description>system timer comp1 target mode register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_PERIOD</name>
+              <description>target1 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_PERIOD_MODE</name>
+              <description>Set target1 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_CONF</name>
+          <description>system timer comp2 target mode register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_PERIOD</name>
+              <description>target2 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_PERIOD_MODE</name>
+              <description>Set target2 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_HI</name>
+          <description>system timer unit0 value high register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_HI</name>
+              <description>timer read value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_LO</name>
+          <description>system timer unit0 value low register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_LO</name>
+              <description>timer read value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_HI</name>
+          <description>system timer unit1 value high register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_HI</name>
+              <description>timer read value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_LO</name>
+          <description>system timer unit1 value low register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_LO</name>
+              <description>timer read value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP0_LOAD</name>
+          <description>system timer comp0 conf sync register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP0_LOAD</name>
+              <description>timer comp0 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP1_LOAD</name>
+          <description>system timer comp1 conf sync register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP1_LOAD</name>
+              <description>timer comp1 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP2_LOAD</name>
+          <description>system timer comp2 conf sync register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP2_LOAD</name>
+              <description>timer comp2 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD</name>
+          <description>system timer unit0 conf sync register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD</name>
+              <description>timer unit0 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD</name>
+          <description>system timer unit1 conf sync register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD</name>
+              <description>timer unit1 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>systimer interrupt enable register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ENA</name>
+              <description>interupt0 enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ENA</name>
+              <description>interupt1 enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ENA</name>
+              <description>interupt2 enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>systimer interrupt raw register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_RAW</name>
+              <description>interupt0 raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_RAW</name>
+              <description>interupt1 raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_RAW</name>
+              <description>interupt2 raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>systimer interrupt clear register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_CLR</name>
+              <description>interupt0 clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_CLR</name>
+              <description>interupt1 clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_CLR</name>
+              <description>interupt2 clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>systimer interrupt status register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ST</name>
+              <description>interupt0 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ST</name>
+              <description>interupt1 status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ST</name>
+              <description>interupt2 status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>system timer version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02012251</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>systimer register version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TIMG0</name>
+      <description>Timer Group</description>
+      <groupName>TIMG</groupName>
+      <baseAddress>0x6001F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TG0_T0_LEVEL</name>
+        <value>23</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_WDT_LEVEL</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>T0CONFIG</name>
+          <description>Timer %s configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002000</resetValue>
+          <fields>
+            <field>
+              <name>USE_XTAL</name>
+              <description>1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALARM_EN</name>
+              <description>When set, the alarm is enabled. This bit is automatically cleared once an
+alarm occurs.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIVCNT_RST</name>
+              <description>When set, Timer %s 's clock divider counter will be reset.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DIVIDER</name>
+              <description>Timer %s clock (T%s_clk) prescaler value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTORELOAD</name>
+              <description>When set, timer %s auto-reload at alarm is enabled.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCREASE</name>
+              <description>When set, the timer %s time-base counter will increment every clock tick. When
+cleared, the timer %s time-base counter will decrement.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>When set, the timer %s time-base counter is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LO</name>
+          <description>Timer %s current value, low 32 bits</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LO</name>
+              <description>After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter
+of timer %s can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0HI</name>
+          <description>Timer $x current value, high 22 bits</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_HI</name>
+              <description>After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
+of timer 0 can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0UPDATE</name>
+          <description>Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_UPDATE</name>
+              <description>After writing 0 or 1 to TIMG_T31UPDATE_REG, the counter value is latched.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMLO</name>
+          <description>Timer $x alarm value, low 32 bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_LO</name>
+              <description>Timer 0 alarm trigger time-base counter value, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMHI</name>
+          <description>Timer $x alarm value, high bits</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_HI</name>
+              <description>Timer 0 alarm trigger time-base counter value, high 22 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADLO</name>
+          <description>Timer $x reload value, low 32 bits</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_LO</name>
+              <description>Low 32 bits of the value that a reload will load onto timer 0 time-base
+Counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADHI</name>
+          <description>Timer $x reload value, high 22 bits</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_HI</name>
+              <description>High 22 bits of the value that a reload will load onto timer 0 time-base
+counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOAD</name>
+          <description>Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD</name>
+              <description>
+Write any value to trigger a timer 0 time-base counter reload.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>Watchdog timer configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0004C000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>WDT reset CPU enable.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>WDT reset CPU enable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>When set, Flash boot protection is enabled.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>System reset signal length selection. 0: 100 ns, 1: 200 ns,
+2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_USE_XTAL</name>
+              <description>choose WDT clock:0-apb_clk; 1-xtal_clk.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CONF_UPDATE_EN</name>
+              <description>update the WDT configuration registers</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>When set, MWDT is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>Watchdog timer prescaler register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_DIVCNT_RST</name>
+              <description>When set, WDT 's clock divider counter will be reset.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_CLK_PRESCALE</name>
+              <description>MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+TIMG_WDT_CLK_PRESCALE.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>Watchdog timer stage 0 timeout value</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x018CBA80</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>Stage 0 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>Watchdog timer stage 1 timeout value</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>Stage 1 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>Watchdog timer stage 2 timeout value</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>Stage 2 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG5</name>
+          <description>Watchdog timer stage 3 timeout value</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>Stage 3 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>Write to feed the watchdog timer</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>Write any value to feed the MWDT. (WO)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>Watchdog write protect register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>If the register contains a different value than its reset value, write
+protection is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG</name>
+          <description>RTC calibration configure register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_START_CYCLING</name>
+              <description>Reserved</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_CLK_SEL</name>
+              <description>0:rtc slow clock. 1:clk_8m, 2:xtal_32k.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_RDY</name>
+              <description>Reserved</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_MAX</name>
+              <description>Reserved</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_START</name>
+              <description>Reserved</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG1</name>
+          <description>RTC calibration configure1 register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_CALI_CYCLING_DATA_VLD</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_VALUE</name>
+              <description>Reserved</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_TIMERS</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_TIMERS</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_TIMERS</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_TIMERS</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG2</name>
+          <description>Timer group calibration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFF98</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_TIMEOUT</name>
+              <description>RTC calibration timeout indicator</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_RST_CNT</name>
+              <description>Cycles that release calibration timeout reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_THRES</name>
+              <description>Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NTIMERS_DATE</name>
+          <description>Timer version control register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02006191</resetValue>
+          <fields>
+            <field>
+              <name>NTIMGS_DATE</name>
+              <description>Timer version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGCLK</name>
+          <description>Timer group clock gate register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60000000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CLK_IS_ACTIVE</name>
+              <description>enable WDT's clock</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_CLK_IS_ACTIVE</name>
+              <description>enable Timer 30's clock</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>UART0</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x60000000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x84</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART0</name>
+        <value>17</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>FIFO</name>
+          <description>FIFO data register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RD_BYTE</name>
+              <description>UART 0 accesses FIFO via this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error in the data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error .</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ST</name>
+              <description>This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ST</name>
+              <description>This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ST</name>
+              <description>This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ST</name>
+              <description>This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ST</name>
+              <description>This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ST</name>
+              <description>This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ST</name>
+              <description>This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ST</name>
+              <description>This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ST</name>
+              <description>This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ST</name>
+              <description>This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ST</name>
+              <description>This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ST</name>
+              <description>This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ST</name>
+              <description>This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ST</name>
+              <description>This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_full_int_st register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ENA</name>
+              <description>This is the enable bit for txfifo_empty_int_st register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for parity_err_int_st register.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for frm_err_int_st register.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_ovf_int_st register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ENA</name>
+              <description>This is the enable bit for dsr_chg_int_st register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ENA</name>
+              <description>This is the enable bit for cts_chg_int_st register.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ENA</name>
+              <description>This is the enable bit for brk_det_int_st register.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_tout_int_st register.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ENA</name>
+              <description>This is the enable bit for sw_xon_int_st register.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ENA</name>
+              <description>This is the enable bit for sw_xoff_int_st register.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>This is the enable bit for glitch_det_int_st register.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_done_int_st register.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_idle_done_int_st register.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_done_int_st register.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ENA</name>
+              <description>This is the enable bit for rs485_clash_int_st register.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ENA</name>
+              <description>This is the enable bit for at_cmd_char_det_int_st register.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ENA</name>
+              <description>This is the enable bit for uart_wakeup_int_st register.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_full_int_raw interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear txfifo_empty_int_raw interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear parity_err_int_raw interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear frm_err_int_raw interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear rxfifo_ovf_int_raw interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_CLR</name>
+              <description>Set this bit to clear the dsr_chg_int_raw interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear the cts_chg_int_raw interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_CLR</name>
+              <description>Set this bit to clear the brk_det_int_raw interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_tout_int_raw interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_CLR</name>
+              <description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_CLR</name>
+              <description>Set this bit to clear the sw_xoff_int_raw interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Set this bit to clear the glitch_det_int_raw interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_done_int_raw interrupt..</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_idle_done_int_raw interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_done_int_raw interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_parity_err_int_raw interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_frm_err_int_raw interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_CLR</name>
+              <description>Set this bit to clear the rs485_clash_int_raw interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_CLR</name>
+              <description>Set this bit to clear the at_cmd_char_det_int_raw interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_CLR</name>
+              <description>Set this bit to clear the uart_wakeup_int_raw interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV</name>
+          <description>Clock divider configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000002B6</resetValue>
+          <fields>
+            <field>
+              <name>CLKDIV</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRAG</name>
+              <description>The decimal part of the frequency divider factor.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_FILT</name>
+          <description>Rx Filter configuration</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>GLITCH_FILT</name>
+              <description>when input pulse width is lower than this value, the pulse is ignored.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_FILT_EN</name>
+              <description>Set this bit to enable Rx signal filter.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>UART status register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xE000C000</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>Stores the byte number of valid data in Rx-FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSRN</name>
+              <description>The register represent the level value of the internal uart dsr signal.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTSN</name>
+              <description>This register represent the level value of the internal uart cts signal.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXD</name>
+              <description>This register represent the  level value of the internal uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>Stores the byte number of data in Tx-FIFO.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTRN</name>
+              <description>This bit represents the level of the internal uart dtr signal.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTSN</name>
+              <description>This bit represents the level of the internal uart rts signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXD</name>
+              <description>This bit represents the  level of the internal uart txd signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0</name>
+          <description>a</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1000001C</resetValue>
+          <fields>
+            <field>
+              <name>PARITY</name>
+              <description>This register is used to configure the parity check mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_EN</name>
+              <description>Set this bit to enable uart parity check.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIT_NUM</name>
+              <description>This register is used to set the length of data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOP_BIT_NUM</name>
+              <description>This register is used to set the length of  stop bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_RTS</name>
+              <description>This register is used to configure the software rts signal which is used in software flow control.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_DTR</name>
+              <description>This register is used to configure the software dtr signal which is used in software flow control.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_BRK</name>
+              <description>Set this bit to enbale transmitter to  send NULL when the process of sending data is done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_DPLX</name>
+              <description>Set this bit to enable IrDA loopback mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_EN</name>
+              <description>This is the start enable bit for IrDA transmitter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_WCTL</name>
+              <description>1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_INV</name>
+              <description>Set this bit to invert the level of  IrDA transmitter.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_RX_INV</name>
+              <description>Set this bit to invert the level of IrDA receiver.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOPBACK</name>
+              <description>Set this bit to enable uart loopback test mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FLOW_EN</name>
+              <description>Set this bit to enable flow control function for transmitter.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_EN</name>
+              <description>Set this bit to enable IrDA protocol.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>Set this bit to reset the uart receive-FIFO.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_RST</name>
+              <description>Set this bit to reset the uart transmit-FIFO.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXD_INV</name>
+              <description>Set this bit to inverse the level value of uart rxd signal.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_INV</name>
+              <description>Set this bit to inverse the level value of uart cts signal.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_INV</name>
+              <description>Set this bit to inverse the level value of uart dsr signal.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_INV</name>
+              <description>Set this bit to inverse the level value of uart txd signal.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTS_INV</name>
+              <description>Set this bit to inverse the level value of uart rts signal.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTR_INV</name>
+              <description>Set this bit to inverse the level value of uart dtr signal.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WR_MASK</name>
+              <description>1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTOBAUD_EN</name>
+              <description>This is the enable bit for detecting baudrate.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_EN</name>
+              <description>UART memory clock gate enable signal.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>Configuration register 1</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C060</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_THRHD</name>
+              <description>It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_THRHD</name>
+              <description>It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIS_RX_DAT_OVF</name>
+              <description>Disable UART Rx data overflow detect.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_FLOW_DIS</name>
+              <description>Set this bit to stop accumulating idle_cnt when hardware flow control works.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_EN</name>
+              <description>This is the flow enable bit for UART receiver.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_EN</name>
+              <description>This is the enble bit for uart receiver's timeout function.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOWPULSE</name>
+          <description>Autobaud minimum low pulse duration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HIGHPULSE</name>
+          <description>Autobaud minimum high pulse duration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXD_CNT</name>
+          <description>Autobaud edge change count register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXD_EDGE_CNT</name>
+              <description>This register stores the count of rxd edge change. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW_CONF</name>
+          <description>Software flow-control configuration</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_FLOW_CON_EN</name>
+              <description>Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XONOFF_DEL</name>
+              <description>Set this bit to remove flow control char from the received data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XON</name>
+              <description>Set this bit to enable the transmitter to go on sending data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XOFF</name>
+              <description>Set this bit to stop the  transmitter from sending data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XON</name>
+              <description>Set this bit to send Xon char. It is cleared by hardware automatically.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XOFF</name>
+              <description>Set this bit to send Xoff char. It is cleared by hardware automatically.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF</name>
+          <description>Sleep-mode configuration</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000F0</resetValue>
+          <fields>
+            <field>
+              <name>ACTIVE_THRESHOLD</name>
+              <description>The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF0</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000026E0</resetValue>
+          <fields>
+            <field>
+              <name>XOFF_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_CHAR</name>
+              <description>This register stores the Xoff flow control char.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF1</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002200</resetValue>
+          <fields>
+            <field>
+              <name>XON_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XON_CHAR</name>
+              <description>This register stores the Xon flow control char.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXBRK_CONF</name>
+          <description>Tx Break character configuration</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>TX_BRK_NUM</name>
+              <description>This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_CONF</name>
+          <description>Frame-end idle configuration</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040100</resetValue>
+          <fields>
+            <field>
+              <name>RX_IDLE_THRHD</name>
+              <description>It will produce frame end signal when receiver takes more time to receive one byte data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between transfers.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RS485_CONF</name>
+          <description>RS485 mode configuration</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RS485_EN</name>
+              <description>Set this bit to choose the rs485 mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL0_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL1_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485TX_RX_EN</name>
+              <description>Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485RXBY_TX_EN</name>
+              <description>1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_RX_DLY_NUM</name>
+              <description>This register is used to delay the receiver's internal data signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_TX_DLY_NUM</name>
+              <description>This register is used to delay the transmitter's internal data signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_PRECNT</name>
+          <description>Pre-sequence timing configuration</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>PRE_IDLE_NUM</name>
+              <description>This register is used to configure the idle duration time before the first at_cmd is received by receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_POSTCNT</name>
+          <description>Post-sequence timing configuration</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>POST_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between the last at_cmd and the next data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_GAPTOUT</name>
+          <description>Timeout configuration</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>RX_GAP_TOUT</name>
+              <description>This register is used to configure the duration time between the at_cmd chars.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_CHAR</name>
+          <description>AT escape sequence detection configuration</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000032B</resetValue>
+          <fields>
+            <field>
+              <name>AT_CMD_CHAR</name>
+              <description>This register is used to configure the content of at_cmd char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAR_NUM</name>
+              <description>This register is used to configure the num of continuous at_cmd chars received by receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>UART threshold and allocation configuration</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A0012</resetValue>
+          <fields>
+            <field>
+              <name>RX_SIZE</name>
+              <description>This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SIZE</name>
+              <description>This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_THRHD</name>
+              <description>This register is used to configure the maximum amount of data that can be received  when hardware flow control works.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_THRHD</name>
+              <description>This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to force power down UART memory.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>Set this bit to force power up UART memory.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_TX_STATUS</name>
+          <description>Tx-FIFO write and read offset address.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_TX_WADDR</name>
+              <description>This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_RADDR</name>
+              <description>This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_RX_STATUS</name>
+          <description>Rx-FIFO write and read offset address.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00080100</resetValue>
+          <fields>
+            <field>
+              <name>APB_RX_RADDR</name>
+              <description>This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_WADDR</name>
+              <description>This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_STATUS</name>
+          <description>UART transmit and receive status.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST_URX_OUT</name>
+              <description>This is the status register of receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ST_UTX_OUT</name>
+              <description>This is the status register of transmitter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POSPULSE</name>
+          <description>Autobaud high pulse register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>POSEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NEGPULSE</name>
+          <description>Autobaud low pulse register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>NEGEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>UART core clock configuration</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03701000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>The  denominator of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>The numerator of the frequency divider factor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_EN</name>
+              <description>Set this bit to enable UART Tx/Rx clock.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_CORE</name>
+              <description>Write 1 then write 0 to this bit, reset UART Tx/Rx.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SCLK_EN</name>
+              <description>Set this bit to enable UART Tx clock.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SCLK_EN</name>
+              <description>Set this bit to enable UART Rx clock.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit, reset UART Tx.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit, reset UART Rx.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UART Version register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02008270</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ID</name>
+          <description>UART ID register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000500</resetValue>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>This register is used to configure the uart_id.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HIGH_SPEED</name>
+              <description>This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_UPDATE</name>
+              <description>Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <name>UART1</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <baseAddress>0x60010000</baseAddress>
+      <interrupt>
+        <name>UART1</name>
+        <value>18</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>XTS_AES</name>
+      <description>XTS-AES-128 Flash Encryption</description>
+      <groupName>XTS_AES</groupName>
+      <baseAddress>0x600CC000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x30</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PLAIN_MEM[%s]</name>
+          <description>The memory that stores plaintext</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>LINESIZE</name>
+          <description>XTS-AES line-size register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINESIZE</name>
+              <description>This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESTINATION</name>
+          <description>XTS-AES destination register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DESTINATION</name>
+              <description>This bit stores the destination. 0: flash(default). 1: reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PHYSICAL_ADDRESS</name>
+          <description>XTS-AES physical address register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PHYSICAL_ADDRESS</name>
+              <description>Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>XTS-AES trigger register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRIGGER</name>
+              <description>Set this bit to start manual encryption calculation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RELEASE</name>
+          <description>XTS-AES release register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RELEASE</name>
+              <description>Set this bit to release the manual encrypted result, after that the result will be visible to spi</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESTROY</name>
+          <description>XTS-AES destroy register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DESTROY</name>
+              <description>Set this bit to destroy XTS-AES result.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>XTS-AES status register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>XTS-AES version control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200623</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Those bits stores the version information of XTS-AES.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/tools/ide-debug/svd/esp32c3.svd b/tools/ide-debug/svd/esp32c3.svd
new file mode 100644
index 00000000000..aea2a98acdd
--- /dev/null
+++ b/tools/ide-debug/svd/esp32c3.svd
@@ -0,0 +1,36098 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+  <vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
+  <vendorID>ESPRESSIF</vendorID>
+  <name>ESP32-C3</name>
+  <series>ESP32-C3</series>
+  <version>10</version>
+  <description>32-bit RISC-V MCU &amp; 2.4 GHz Wi-Fi &amp; Bluetooth 5 (LE)</description>
+  <licenseText>
+    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+</licenseText>
+  <cpu>
+    <name>RV32IMC</name>
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <nvicPrioBits>4</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>32</addressUnitBits>
+  <width>32</width>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AES</name>
+      <description>AES (Advanced Encryption Standard) Accelerator</description>
+      <groupName>AES</groupName>
+      <baseAddress>0x6003A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xBC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AES</name>
+        <value>48</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>KEY_0</name>
+          <description>Key material key_0 configure register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_0</name>
+              <description>This bits stores key_0 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_1</name>
+          <description>Key material key_1 configure register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_1</name>
+              <description>This bits stores key_1 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_2</name>
+          <description>Key material key_2 configure register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_2</name>
+              <description>This bits stores key_2 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_3</name>
+          <description>Key material key_3 configure register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_3</name>
+              <description>This bits stores key_3 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_4</name>
+          <description>Key material key_4 configure register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_4</name>
+              <description>This bits stores key_4 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_5</name>
+          <description>Key material key_5 configure register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_5</name>
+              <description>This bits stores key_5 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_6</name>
+          <description>Key material key_6 configure register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_6</name>
+              <description>This bits stores key_6 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_7</name>
+          <description>Key material key_7 configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_7</name>
+              <description>This bits stores key_7 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_0</name>
+          <description>source text material text_in_0 configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_0</name>
+              <description>This bits stores text_in_0 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_1</name>
+          <description>source text material text_in_1 configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_1</name>
+              <description>This bits stores text_in_1 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_2</name>
+          <description>source text material text_in_2 configure register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_2</name>
+              <description>This bits stores text_in_2 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_3</name>
+          <description>source text material text_in_3 configure register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_3</name>
+              <description>This bits stores text_in_3 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_0</name>
+          <description>result text material text_out_0 configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_0</name>
+              <description>This bits stores text_out_0 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_1</name>
+          <description>result text material text_out_1 configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_1</name>
+              <description>This bits stores text_out_1 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_2</name>
+          <description>result text material text_out_2 configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_2</name>
+              <description>This bits stores text_out_2 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_3</name>
+          <description>result text material text_out_3 configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_3</name>
+              <description>This bits stores text_out_3 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>AES Mode register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENDIAN</name>
+          <description>AES Endian configure register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENDIAN</name>
+              <description>endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out endian or out_stream endian</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>AES trigger register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRIGGER</name>
+              <description>Set this bit to start AES calculation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>AES state register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>IV_MEM[%s]</name>
+          <description>The memory that stores initialization vector</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>H_MEM[%s]</name>
+          <description>The memory that stores GCM hash subkey</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>J0_MEM[%s]</name>
+          <description>The memory that stores J0</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>T0_MEM[%s]</name>
+          <description>The memory that stores T0</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>DMA_ENABLE</name>
+          <description>DMA-AES working mode register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_ENABLE</name>
+              <description>1'b0: typical AES working mode, 1'b1: DMA-AES working mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_MODE</name>
+          <description>AES cipher block mode register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_MODE</name>
+              <description>Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_NUM</name>
+          <description>AES block number register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_NUM</name>
+              <description>Those bits stores the number of Plaintext/ciphertext block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INC_SEL</name>
+          <description>Standard incrementing function configure register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INC_SEL</name>
+              <description>This bit decides the standard incrementing function. 0: INC32. 1: INC128.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AAD_BLOCK_NUM</name>
+          <description>Additional Authential Data block number register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AAD_BLOCK_NUM</name>
+              <description>Those bits stores the number of AAD block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REMAINDER_BIT_NUM</name>
+          <description>AES remainder bit number register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REMAINDER_BIT_NUM</name>
+              <description>Those bits stores the number of remainder bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE</name>
+          <description>AES continue register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE</name>
+              <description>Set this bit to continue GCM operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLEAR</name>
+          <description>AES Interrupt clear register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_CLEAR</name>
+              <description>Set this bit to clear the AES interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>AES Interrupt enable register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_ENA</name>
+              <description>Set this bit to enable interrupt that occurs when DMA-AES calculation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>AES version control register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20191210</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This bits stores the version information of AES.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_EXIT</name>
+          <description>AES-DMA exit config</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_EXIT</name>
+              <description>Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>APB_CTRL</name>
+      <description>Advanced Peripheral Bus Controller</description>
+      <groupName>APB_CTRL</groupName>
+      <baseAddress>0x60026000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SYSCLK_CONF</name>
+          <description>APB_CTRL_SYSCLK_CONF_REG</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PRE_DIV_CNT</name>
+              <description>reg_pre_div_cnt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_320M_EN</name>
+              <description>reg_clk_320m_en</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_TICK_CNT</name>
+              <description>reg_rst_tick_cnt</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TICK_CONF</name>
+          <description>APB_CTRL_TICK_CONF_REG</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010727</resetValue>
+          <fields>
+            <field>
+              <name>XTAL_TICK_NUM</name>
+              <description>reg_xtal_tick_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_TICK_NUM</name>
+              <description>reg_ck8m_tick_num</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_ENABLE</name>
+              <description>reg_tick_enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_OUT_EN</name>
+          <description>APB_CTRL_CLK_OUT_EN_REG</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>CLK20_OEN</name>
+              <description>reg_clk20_oen</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK22_OEN</name>
+              <description>reg_clk22_oen</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK44_OEN</name>
+              <description>reg_clk44_oen</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_BB_OEN</name>
+              <description>reg_clk_bb_oen</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK80_OEN</name>
+              <description>reg_clk80_oen</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK160_OEN</name>
+              <description>reg_clk160_oen</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_320M_OEN</name>
+              <description>reg_clk_320m_oen</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_ADC_INF_OEN</name>
+              <description>reg_clk_adc_inf_oen</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DAC_CPU_OEN</name>
+              <description>reg_clk_dac_cpu_oen</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK40X_BB_OEN</name>
+              <description>reg_clk40x_bb_oen</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_XTAL_OEN</name>
+              <description>reg_clk_xtal_oen</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_CFG</name>
+          <description>APB_CTRL_WIFI_BB_CFG_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_CFG</name>
+              <description>reg_wifi_bb_cfg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_CFG_2</name>
+          <description>APB_CTRL_WIFI_BB_CFG_2_REG</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_CFG_2</name>
+              <description>reg_wifi_bb_cfg_2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_CLK_EN</name>
+          <description>APB_CTRL_WIFI_CLK_EN_REG</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFCE030</resetValue>
+          <fields>
+            <field>
+              <name>WIFI_CLK_EN</name>
+              <description>reg_wifi_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_RST_EN</name>
+          <description>APB_CTRL_WIFI_RST_EN_REG</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_RST</name>
+              <description>reg_wifi_rst</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_INF_SEL</name>
+          <description>APB_CTRL_HOST_INF_SEL_REG</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_IO_SWAP</name>
+              <description>reg_peri_io_swap</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_MEM_PMS_LOCK</name>
+          <description>APB_CTRL_EXT_MEM_PMS_LOCK_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_MEM_PMS_LOCK</name>
+              <description>reg_ext_mem_pms_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE0_ATTR</name>
+          <description>APB_CTRL_FLASH_ACE0_ATTR_REG</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE0_ATTR</name>
+              <description>reg_flash_ace0_attr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE1_ATTR</name>
+          <description>APB_CTRL_FLASH_ACE1_ATTR_REG</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE1_ATTR</name>
+              <description>reg_flash_ace1_attr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE2_ATTR</name>
+          <description>APB_CTRL_FLASH_ACE2_ATTR_REG</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE2_ATTR</name>
+              <description>reg_flash_ace2_attr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE3_ATTR</name>
+          <description>APB_CTRL_FLASH_ACE3_ATTR_REG</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE3_ATTR</name>
+              <description>reg_flash_ace3_attr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE0_ADDR</name>
+          <description>APB_CTRL_FLASH_ACE0_ADDR_REG</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>reg_flash_ace0_addr_s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE1_ADDR</name>
+          <description>APB_CTRL_FLASH_ACE1_ADDR_REG</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>reg_flash_ace1_addr_s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE2_ADDR</name>
+          <description>APB_CTRL_FLASH_ACE2_ADDR_REG</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>reg_flash_ace2_addr_s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE3_ADDR</name>
+          <description>APB_CTRL_FLASH_ACE3_ADDR_REG</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C00000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>reg_flash_ace3_addr_s</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE0_SIZE</name>
+          <description>APB_CTRL_FLASH_ACE0_SIZE_REG</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000400</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE0_SIZE</name>
+              <description>reg_flash_ace0_size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE1_SIZE</name>
+          <description>APB_CTRL_FLASH_ACE1_SIZE_REG</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000400</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE1_SIZE</name>
+              <description>reg_flash_ace1_size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE2_SIZE</name>
+          <description>APB_CTRL_FLASH_ACE2_SIZE_REG</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000400</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE2_SIZE</name>
+              <description>reg_flash_ace2_size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE3_SIZE</name>
+          <description>APB_CTRL_FLASH_ACE3_SIZE_REG</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000400</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE3_SIZE</name>
+              <description>reg_flash_ace3_size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_PMS_CTRL</name>
+          <description>APB_CTRL_SPI_MEM_PMS_CTRL_REG</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_INT</name>
+              <description>reg_spi_mem_reject_int</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_REJECT_CLR</name>
+              <description>reg_spi_mem_reject_clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_REJECT_CDE</name>
+              <description>reg_spi_mem_reject_cde</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REJECT_ADDR</name>
+          <description>APB_CTRL_SPI_MEM_REJECT_ADDR_REG</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_ADDR</name>
+              <description>reg_spi_mem_reject_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CTRL</name>
+          <description>APB_CTRL_SDIO_CTRL_REG</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_WIN_ACCESS_EN</name>
+              <description>reg_sdio_win_access_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDCY_SIG0</name>
+          <description>APB_CTRL_REDCY_SIG0_REG_REG</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_SIG0</name>
+              <description>reg_redcy_sig0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDCY_ANDOR</name>
+              <description>reg_redcy_andor</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDCY_SIG1</name>
+          <description>APB_CTRL_REDCY_SIG1_REG_REG</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_SIG1</name>
+              <description>reg_redcy_sig1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDCY_NANDOR</name>
+              <description>reg_redcy_nandor</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRONT_END_MEM_PD</name>
+          <description>APB_CTRL_FRONT_END_MEM_PD_REG</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000015</resetValue>
+          <fields>
+            <field>
+              <name>AGC_MEM_FORCE_PU</name>
+              <description>reg_agc_mem_force_pu</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AGC_MEM_FORCE_PD</name>
+              <description>reg_agc_mem_force_pd</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBUS_MEM_FORCE_PU</name>
+              <description>reg_pbus_mem_force_pu</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBUS_MEM_FORCE_PD</name>
+              <description>reg_pbus_mem_force_pd</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DC_MEM_FORCE_PU</name>
+              <description>reg_dc_mem_force_pu</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DC_MEM_FORCE_PD</name>
+              <description>reg_dc_mem_force_pd</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL</name>
+          <description>APB_CTRL_RETENTION_CTRL_REG</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RETENTION_LINK_ADDR</name>
+              <description>reg_retention_link_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NOBYPASS_CPU_ISO_RST</name>
+              <description>reg_nobypass_cpu_iso_rst</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKGATE_FORCE_ON</name>
+          <description>APB_CTRL_CLKGATE_FORCE_ON_REG</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>ROM_CLKGATE_FORCE_ON</name>
+              <description>reg_rom_clkgate_force_on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_CLKGATE_FORCE_ON</name>
+              <description>reg_sram_clkgate_force_on</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_POWER_DOWN</name>
+          <description>APB_CTRL_MEM_POWER_DOWN_REG</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ROM_POWER_DOWN</name>
+              <description>reg_rom_power_down</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_POWER_DOWN</name>
+              <description>reg_sram_power_down</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_POWER_UP</name>
+          <description>APB_CTRL_MEM_POWER_UP_REG</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>ROM_POWER_UP</name>
+              <description>reg_rom_power_up</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_POWER_UP</name>
+              <description>reg_sram_power_up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RND_DATA</name>
+          <description>APB_CTRL_RND_DATA_REG</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RND_DATA</name>
+              <description>reg_rnd_data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_CONFIG</name>
+          <description>APB_CTRL_PERI_BACKUP_CONFIG_REG_REG</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00006480</resetValue>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_FLOW_ERR</name>
+              <description>reg_peri_backup_flow_err</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_BURST_LIMIT</name>
+              <description>reg_peri_backup_burst_limit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_TOUT_THRES</name>
+              <description>reg_peri_backup_tout_thres</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_SIZE</name>
+              <description>reg_peri_backup_size</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_START</name>
+              <description>reg_peri_backup_start</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_TO_MEM</name>
+              <description>reg_peri_backup_to_mem</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ENA</name>
+              <description>reg_peri_backup_ena</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_APB_ADDR</name>
+          <description>APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_APB_START_ADDR</name>
+              <description>reg_backup_apb_start_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_MEM_ADDR</name>
+          <description>APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_MEM_START_ADDR</name>
+              <description>reg_backup_mem_start_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_RAW</name>
+          <description>APB_CTRL_PERI_BACKUP_INT_RAW_REG</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_DONE_INT_RAW</name>
+              <description>reg_peri_backup_done_int_raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ERR_INT_RAW</name>
+              <description>reg_peri_backup_err_int_raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_ST</name>
+          <description>APB_CTRL_PERI_BACKUP_INT_ST_REG</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_DONE_INT_ST</name>
+              <description>reg_peri_backup_done_int_st</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ERR_INT_ST</name>
+              <description>reg_peri_backup_err_int_st</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_ENA</name>
+          <description>APB_CTRL_PERI_BACKUP_INT_ENA_REG</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_DONE_INT_ENA</name>
+              <description>reg_peri_backup_done_int_ena</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ERR_INT_ENA</name>
+              <description>reg_peri_backup_err_int_ena</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_CLR</name>
+          <description>APB_CTRL_PERI_BACKUP_INT_CLR_REG</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_DONE_INT_CLR</name>
+              <description>reg_peri_backup_done_int_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PERI_BACKUP_ERR_INT_CLR</name>
+              <description>reg_peri_backup_err_int_clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>APB_CTRL_DATE_REG</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007210</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_dateVersion control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>APB_SARADC</name>
+      <description>Successive Approximation Register Analog to Digital Converter</description>
+      <groupName>APB_SARADC</groupName>
+      <baseAddress>0x60040000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>APB_ADC</name>
+        <value>43</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40038240</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_START_FORCE</name>
+              <description>select software enable saradc sample</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_START</name>
+              <description>software enable saradc sample</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_GATED</name>
+              <description>SAR clock gated</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_DIV</name>
+              <description>SAR clock divider</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_PATT_P_CLEAR</name>
+              <description>clear the pointer of pattern table for DIG ADC1 CTRL</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_XPD_SAR_FORCE</name>
+              <description>force option to xpd sar blocks</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_WAIT_ARB_CYCLE</name>
+              <description>wait arbit signal stable after sar_done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000A1FE</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_MEAS_NUM_LIMIT</name>
+              <description>enable max meas num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_MAX_MEAS_NUM</name>
+              <description>max conversion number</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_INV</name>
+              <description>1: data to DIG ADC1 CTRL is inverted, otherwise not</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_INV</name>
+              <description>1: data to DIG ADC2 CTRL is inverted, otherwise not</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_TARGET</name>
+              <description>to set saradc timer target</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_EN</name>
+              <description>to enable saradc timer trigger</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL1</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_FILTER_FACTOR1</name>
+              <description>Factor of saradc filter1</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_FILTER_FACTOR0</name>
+              <description>Factor of saradc filter0</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_WAIT</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FF0808</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_XPD_WAIT</name>
+              <description>saradc_xpd_wait</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_RSTB_WAIT</name>
+              <description>saradc_rstb_wait</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_STANDBY_WAIT</name>
+              <description>saradc_standby_wait</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_STATUS</name>
+              <description>saradc1 status about data and channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_STATUS</name>
+              <description>saradc2 status about data and channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PATT_TAB1</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PATT_TAB2</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ONETIME_SAMPLE</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1A000000</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_ONETIME_ATTEN</name>
+              <description>configure onetime atten</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_ONETIME_CHANNEL</name>
+              <description>configure onetime channel</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_ONETIME_START</name>
+              <description>trigger adc onetime sample</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC2_ONETIME_SAMPLE</name>
+              <description>enable adc2 onetime sample</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC1_ONETIME_SAMPLE</name>
+              <description>enable adc1 onetime sample</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000900</resetValue>
+          <fields>
+            <field>
+              <name>ADC_ARB_APB_FORCE</name>
+              <description>adc2 arbiter force to enableapb controller</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_FORCE</name>
+              <description>adc2 arbiter force to enable rtc controller</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_FORCE</name>
+              <description>adc2 arbiter force to enable wifi controller</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_GRANT_FORCE</name>
+              <description>adc2 arbiter force grant</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_APB_PRIORITY</name>
+              <description>Set adc2 arbiterapb priority</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_PRIORITY</name>
+              <description>Set adc2 arbiter rtc priority</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_PRIORITY</name>
+              <description>Set adc2 arbiter wifi priority</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_FIX_PRIORITY</name>
+              <description>adc2 arbiter uses fixed priority</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL0</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03740000</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_FILTER_CHANNEL1</name>
+              <description>configure filter1 to adc channel</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_FILTER_CHANNEL0</name>
+              <description>configure filter0 to adc channel</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_FILTER_RESET</name>
+              <description>enable apb_adc1_filter</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1DATA_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC1_DATA</name>
+              <description>saradc1 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2DATA_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC2_DATA</name>
+              <description>saradc2 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES0_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES0_CHANNEL</name>
+              <description>configure thres0 to adc channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH</name>
+              <description>saradc thres0 monitor thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW</name>
+              <description>saradc thres0 monitor thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES1_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES1_CHANNEL</name>
+              <description>configure thres1 to adc channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH</name>
+              <description>saradc thres1 monitor thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW</name>
+              <description>saradc thres1 monitor thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES_ALL_EN</name>
+              <description>enable thres to all channel</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_EN</name>
+              <description>enable thres1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_EN</name>
+              <description>enable thres0</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_ENA</name>
+              <description>saradc thres1 low  interrupt enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_ENA</name>
+              <description>saradc thres0 low interrupt enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_ENA</name>
+              <description>saradc thres1 high interrupt enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_ENA</name>
+              <description>saradc thres0 high interrupt enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ENA</name>
+              <description>saradc2 done interrupt enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ENA</name>
+              <description>saradc1 done interrupt enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_RAW</name>
+              <description>saradc thres1 low  interrupt raw</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_RAW</name>
+              <description>saradc thres0 low interrupt raw</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_RAW</name>
+              <description>saradc thres1 high interrupt raw</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_RAW</name>
+              <description>saradc thres0 high interrupt raw</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_RAW</name>
+              <description>saradc2 done interrupt raw</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_RAW</name>
+              <description>saradc1 done interrupt raw</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_ST</name>
+              <description>saradc thres1 low  interrupt state</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_ST</name>
+              <description>saradc thres0 low interrupt state</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_ST</name>
+              <description>saradc thres1 high interrupt state</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_ST</name>
+              <description>saradc thres0 high interrupt state</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ST</name>
+              <description>saradc2 done interrupt state</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ST</name>
+              <description>saradc1 done interrupt state</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_CLR</name>
+              <description>saradc thres1 low  interrupt clear</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_CLR</name>
+              <description>saradc thres0 low interrupt clear</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_CLR</name>
+              <description>saradc thres1 high interrupt clear</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_CLR</name>
+              <description>saradc thres0 high interrupt clear</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_CLR</name>
+              <description>saradc2 done interrupt clear</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_CLR</name>
+              <description>saradc1 done interrupt clear</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>APB_ADC_EOF_NUM</name>
+              <description>the dma_in_suc_eof gen when sample cnt = spi_eof_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_RESET_FSM</name>
+              <description>reset_apb_adc_state</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_TRANS</name>
+              <description>enable apb_adc use spi_dma</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKM_CONF</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_B</name>
+              <description>Fractional clock divider numerator value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_A</name>
+              <description>Fractional clock divider denominator value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg clk en</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_SEL</name>
+              <description>Set this bit to enable clk_apll</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_TSENS_CTRL</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_OUT</name>
+              <description>temperature sensor data out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_IN_INV</name>
+              <description>invert temperature sensor data</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_DIV</name>
+              <description>temperature sensor clock divider</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_PU</name>
+              <description>temperature sensor power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TSENS_CTRL2</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004002</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_XPD_WAIT</name>
+              <description>the time that power up tsens need wait</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_XPD_FORCE</name>
+              <description>force power up tsens</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_INV</name>
+              <description>inv tsens clk</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_SEL</name>
+              <description>tsens clk select</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALI</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_CALI_CFG</name>
+              <description>saradc cali factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL_DATE</name>
+          <description>version</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007171</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ASSIST_DEBUG</name>
+      <description>Debug Assist</description>
+      <groupName>ASSIST_DEBUG</groupName>
+      <baseAddress>0x600CE000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ASSIST_DEBUG</name>
+        <value>54</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>C0RE_0_MONTR_ENA</name>
+          <description>ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_ENA</name>
+              <description>reg_core_0_area_dram0_0_rd_ena</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_ENA</name>
+              <description>reg_core_0_area_dram0_0_wr_ena</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_ENA</name>
+              <description>reg_core_0_area_dram0_1_rd_ena</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_ENA</name>
+              <description>reg_core_0_area_dram0_1_wr_ena</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_ENA</name>
+              <description>reg_core_0_area_pif_0_rd_ena</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_ENA</name>
+              <description>reg_core_0_area_pif_0_wr_ena</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_ENA</name>
+              <description>reg_core_0_area_pif_1_rd_ena</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_ENA</name>
+              <description>reg_core_0_area_pif_1_wr_ena</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_ENA</name>
+              <description>reg_core_0_sp_spill_min_ena</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_ENA</name>
+              <description>reg_core_0_sp_spill_max_ena</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>reg_core_0_iram0_exception_monitor_ena</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>reg_core_0_dram0_exception_monitor_ena</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_RAW</name>
+          <description>ASSIST_DEBUG_CORE_0_INTR_RAW_REG</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_RAW</name>
+              <description>reg_core_0_area_dram0_0_rd_raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_RAW</name>
+              <description>reg_core_0_area_dram0_0_wr_raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_RAW</name>
+              <description>reg_core_0_area_dram0_1_rd_raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_RAW</name>
+              <description>reg_core_0_area_dram0_1_wr_raw</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_RAW</name>
+              <description>reg_core_0_area_pif_0_rd_raw</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_RAW</name>
+              <description>reg_core_0_area_pif_0_wr_raw</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_RAW</name>
+              <description>reg_core_0_area_pif_1_rd_raw</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_RAW</name>
+              <description>reg_core_0_area_pif_1_wr_raw</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_RAW</name>
+              <description>reg_core_0_sp_spill_min_raw</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_RAW</name>
+              <description>reg_core_0_sp_spill_max_raw</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>reg_core_0_iram0_exception_monitor_raw</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>reg_core_0_dram0_exception_monitor_raw</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_ENA</name>
+          <description>ASSIST_DEBUG_CORE_0_INTR_ENA_REG</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_INTR_ENA</name>
+              <description>reg_core_0_area_dram0_0_rd_intr_ena</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_INTR_ENA</name>
+              <description>reg_core_0_area_dram0_0_wr_intr_ena</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_INTR_ENA</name>
+              <description>reg_core_0_area_dram0_1_rd_intr_ena</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_INTR_ENA</name>
+              <description>reg_core_0_area_dram0_1_wr_intr_ena</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_INTR_ENA</name>
+              <description>reg_core_0_area_pif_0_rd_intr_ena</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_INTR_ENA</name>
+              <description>reg_core_0_area_pif_0_wr_intr_ena</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_INTR_ENA</name>
+              <description>reg_core_0_area_pif_1_rd_intr_ena</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_INTR_ENA</name>
+              <description>reg_core_0_area_pif_1_wr_intr_ena</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_INTR_ENA</name>
+              <description>reg_core_0_sp_spill_min_intr_ena</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_INTR_ENA</name>
+              <description>reg_core_0_sp_spill_max_intr_ena</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>reg_core_0_iram0_exception_monitor_ena</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>reg_core_0_dram0_exception_monitor_ena</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_CLR</name>
+          <description>ASSIST_DEBUG_CORE_0_INTR_CLR_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_CLR</name>
+              <description>reg_core_0_area_dram0_0_rd_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_CLR</name>
+              <description>reg_core_0_area_dram0_0_wr_clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_CLR</name>
+              <description>reg_core_0_area_dram0_1_rd_clr</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_CLR</name>
+              <description>reg_core_0_area_dram0_1_wr_clr</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_CLR</name>
+              <description>reg_core_0_area_pif_0_rd_clr</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_CLR</name>
+              <description>reg_core_0_area_pif_0_wr_clr</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_CLR</name>
+              <description>reg_core_0_area_pif_1_rd_clr</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_CLR</name>
+              <description>reg_core_0_area_pif_1_wr_clr</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_CLR</name>
+              <description>reg_core_0_sp_spill_min_clr</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_CLR</name>
+              <description>reg_core_0_sp_spill_max_clr</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>reg_core_0_iram0_exception_monitor_clr</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>reg_core_0_dram0_exception_monitor_clr</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_0_MIN</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_MIN</name>
+              <description>reg_core_0_area_dram0_0_min</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_0_MAX</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_MAX</name>
+              <description>reg_core_0_area_dram0_0_max</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_1_MIN</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_MIN</name>
+              <description>reg_core_0_area_dram0_1_min</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_1_MAX</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_MAX</name>
+              <description>reg_core_0_area_dram0_1_max</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_0_MIN</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_0_MIN</name>
+              <description>reg_core_0_area_pif_0_min</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_0_MAX</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_0_MAX</name>
+              <description>reg_core_0_area_pif_0_max</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_1_MIN</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_1_MIN</name>
+              <description>reg_core_0_area_pif_1_min</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_1_MAX</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_1_MAX</name>
+              <description>reg_core_0_area_pif_1_max</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PC</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_PC_REG</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PC</name>
+              <description>reg_core_0_area_pc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_SP</name>
+          <description>ASSIST_DEBUG_CORE_0_AREA_SP_REG</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_SP</name>
+              <description>reg_core_0_area_sp</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MIN</name>
+          <description>ASSIST_DEBUG_CORE_0_SP_MIN_REG</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MIN</name>
+              <description>reg_core_0_sp_min</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MAX</name>
+          <description>ASSIST_DEBUG_CORE_0_SP_MAX_REG</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MAX</name>
+              <description>reg_core_0_sp_max</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_PC</name>
+          <description>ASSIST_DEBUG_CORE_0_SP_PC_REG</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_PC</name>
+              <description>reg_core_0_sp_pc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_EN</name>
+          <description>ASSIST_DEBUG_CORE_0_RCD_EN_REG</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_RECORDEN</name>
+              <description>reg_core_0_rcd_recorden</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_RCD_PDEBUGEN</name>
+              <description>reg_core_0_rcd_pdebugen</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGPC</name>
+          <description>ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGPC</name>
+              <description>reg_core_0_rcd_pdebugpc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGSP</name>
+          <description>ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGSP</name>
+              <description>reg_core_0_rcd_pdebugsp</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_EXCEPTION_MONITOR_0</name>
+          <description>ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_ADDR_0</name>
+              <description>reg_core_0_iram0_recording_addr_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_WR_0</name>
+              <description>reg_core_0_iram0_recording_wr_0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_LOADSTORE_0</name>
+              <description>reg_core_0_iram0_recording_loadstore_0</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_EXCEPTION_MONITOR_1</name>
+          <description>ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_ADDR_1</name>
+              <description>reg_core_0_iram0_recording_addr_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_WR_1</name>
+              <description>reg_core_0_iram0_recording_wr_1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_LOADSTORE_1</name>
+              <description>reg_core_0_iram0_recording_loadstore_1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_0</name>
+          <description>ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_ADDR_0</name>
+              <description>reg_core_0_dram0_recording_addr_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_WR_0</name>
+              <description>reg_core_0_dram0_recording_wr_0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_BYTEEN_0</name>
+              <description>reg_core_0_dram0_recording_byteen_0</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_1</name>
+          <description>ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_PC_0</name>
+              <description>reg_core_0_dram0_recording_pc_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_2</name>
+          <description>ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_ADDR_1</name>
+              <description>reg_core_0_dram0_recording_addr_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_WR_1</name>
+              <description>reg_core_0_dram0_recording_wr_1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_BYTEEN_1</name>
+              <description>reg_core_0_dram0_recording_byteen_1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_3</name>
+          <description>ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_PC_1</name>
+              <description>reg_core_0_dram0_recording_pc_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0</name>
+          <description>ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0</name>
+              <description>reg_core_x_iram0_dram0_limit_cycle_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1</name>
+          <description>ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1</name>
+              <description>reg_core_x_iram0_dram0_limit_cycle_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_SETTING</name>
+          <description>ASSIST_DEBUG_LOG_SETTING</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>LOG_ENA</name>
+              <description>reg_log_ena</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOG_MODE</name>
+              <description>reg_log_mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOG_MEM_LOOP_ENABLE</name>
+              <description>reg_log_mem_loop_enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_DATA_0</name>
+          <description>ASSIST_DEBUG_LOG_DATA_0_REG</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_DATA_0</name>
+              <description>reg_log_data_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_DATA_MASK</name>
+          <description>ASSIST_DEBUG_LOG_DATA_MASK_REG</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_DATA_SIZE</name>
+              <description>reg_log_data_size</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MIN</name>
+          <description>ASSIST_DEBUG_LOG_MIN_REG</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MIN</name>
+              <description>reg_log_min</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MAX</name>
+          <description>ASSIST_DEBUG_LOG_MAX_REG</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MAX</name>
+              <description>reg_log_max</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_START</name>
+          <description>ASSIST_DEBUG_LOG_MEM_START_REG</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_START</name>
+              <description>reg_log_mem_start</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_END</name>
+          <description>ASSIST_DEBUG_LOG_MEM_END_REG</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_END</name>
+              <description>reg_log_mem_end</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_WRITING_ADDR</name>
+          <description>ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_WRITING_ADDR</name>
+              <description>reg_log_mem_writing_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_FULL_FLAG</name>
+          <description>ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_FULL_FLAG</name>
+              <description>reg_log_mem_full_flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLR_LOG_MEM_FULL_FLAG</name>
+              <description>reg_clr_log_mem_full_flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C0RE_0_LASTPC_BEFORE_EXCEPTION</name>
+          <description>ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_LASTPC_BEFORE_EXC</name>
+              <description>reg_core_0_lastpc_before_exc</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C0RE_0_DEBUG_MODE</name>
+          <description>ASSIST_DEBUG_C0RE_0_DEBUG_MODE</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DEBUG_MODE</name>
+              <description>reg_core_0_debug_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DEBUG_MODULE_ACTIVE</name>
+              <description>reg_core_0_debug_module_active</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>ASSIST_DEBUG_DATE_REG</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02008010</resetValue>
+          <fields>
+            <field>
+              <name>ASSIST_DEBUG_DATE</name>
+              <description>reg_assist_debug_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMA</name>
+      <description>DMA (Direct Memory Access) Controller</description>
+      <groupName>DMA</groupName>
+      <baseAddress>0x6003F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x174</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMA_CH0</name>
+        <value>44</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_CH1</name>
+        <value>45</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_CH2</name>
+        <value>46</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INT_RAW_CH0</name>
+          <description>DMA_INT_RAW_CH0_REG.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_CH0</name>
+          <description>DMA_INT_ST_CH0_REG.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt status bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_CH0</name>
+          <description>DMA_INT_ENA_CH0_REG.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The interrupt enable bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The interrupt enable bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The interrupt enable bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_CH0</name>
+          <description>DMA_INT_CLR_CH0_REG.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>Set this bit to clear the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>Set this bit to clear the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>Set this bit to clear the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_CH1</name>
+          <description>DMA_INT_RAW_CH1_REG.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_CH1</name>
+          <description>DMA_INT_ST_CH1_REG.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt status bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_CH1</name>
+          <description>DMA_INT_ENA_CH1_REG.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The interrupt enable bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The interrupt enable bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The interrupt enable bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_CH1</name>
+          <description>DMA_INT_CLR_CH1_REG.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>Set this bit to clear the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>Set this bit to clear the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>Set this bit to clear the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_CH2</name>
+          <description>DMA_INT_RAW_CH2_REG.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_CH2</name>
+          <description>DMA_INT_ST_CH2_REG.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt status bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_CH2</name>
+          <description>DMA_INT_ENA_CH2_REG.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The interrupt enable bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The interrupt enable bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The interrupt enable bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_CH2</name>
+          <description>DMA_INT_CLR_CH2_REG.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>Set this bit to clear the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE</name>
+              <description>Set this bit to clear the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>Set this bit to clear the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF</name>
+              <description>Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF</name>
+              <description>Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF</name>
+              <description>Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF</name>
+              <description>Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_TEST</name>
+          <description>DMA_AHB_TEST_REG.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHB_TESTMODE</name>
+              <description>reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_TESTADDR</name>
+              <description>reserved</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC_CONF</name>
+          <description>DMA_MISC_CONF_REG.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHBM_RST_INTER</name>
+              <description>Set this bit, then clear this bit to reset the internal ahb FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_PRI_DIS</name>
+              <description>Set this bit to disable priority arbitration function.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>DMA_DATE_REG.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02008250</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_CONF0_CH0</name>
+          <description>DMA_IN_CONF0_CH0_REG.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <description>Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_CONF1_CH0</name>
+          <description>DMA_IN_CONF1_CH0_REG.</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INFIFO_STATUS_CH0</name>
+          <description>DMA_INFIFO_STATUS_CH0_REG.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800003</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_FULL</name>
+              <description>L1 Rx FIFO full signal for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_EMPTY</name>
+              <description>L1 Rx FIFO empty signal for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT</name>
+              <description>The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_1B</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_2B</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_3B</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_4B</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_BUF_HUNGRY</name>
+              <description>reserved</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_POP_CH0</name>
+          <description>DMA_IN_POP_CH0_REG.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA</name>
+              <description>This register stores the data popping from DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP</name>
+              <description>Set this bit to pop data from DMA FIFO.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_LINK_CH0</name>
+          <description>DMA_IN_LINK_CH0_REG.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01100000</resetValue>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET</name>
+              <description>Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set this bit to stop dealing with the inlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set this bit to start dealing with the inlink descriptors.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set this bit to mount a new inlink descriptor.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_PARK</name>
+              <description>1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_STATE_CH0</name>
+          <description>DMA_IN_STATE_CH0_REG.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_ADDR</name>
+              <description>This register stores the current inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_SUC_EOF_DES_ADDR_CH0</name>
+          <description>DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_ERR_EOF_DES_ADDR_CH0</name>
+          <description>DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_ERR_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_CH0</name>
+          <description>DMA_IN_DSCR_CH0_REG.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR</name>
+              <description>The address of the current inlink descriptor x.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_BF0_CH0</name>
+          <description>DMA_IN_DSCR_BF0_CH0_REG.</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0</name>
+              <description>The address of the last inlink descriptor x-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_BF1_CH0</name>
+          <description>DMA_IN_DSCR_BF1_CH0_REG.</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_PRI_CH0</name>
+          <description>DMA_IN_PRI_CH0_REG.</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_PRI</name>
+              <description>The priority of Rx channel 0. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_PERI_SEL_CH0</name>
+          <description>DMA_IN_PERI_SEL_CH0_REG.</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_IN_SEL</name>
+              <description>This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_CONF0_CH0</name>
+          <description>DMA_OUT_CONF0_CH0_REG.</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>OUT_RST</name>
+              <description>This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_CONF1_CH0</name>
+          <description>DMA_OUT_CONF1_CH0_REG.</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTFIFO_STATUS_CH0</name>
+          <description>DMA_OUTFIFO_STATUS_CH0_REG.</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800002</resetValue>
+          <fields>
+            <field>
+              <name>OUTFIFO_FULL</name>
+              <description>L1 Tx FIFO full signal for Tx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY</name>
+              <description>L1 Tx FIFO empty signal for Tx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT</name>
+              <description>The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_1B</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_2B</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_3B</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_4B</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PUSH_CH0</name>
+          <description>DMA_OUT_PUSH_CH0_REG.</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA</name>
+              <description>This register stores the data that need to be pushed into DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH</name>
+              <description>Set this bit to push data into DMA FIFO.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_LINK_CH0</name>
+          <description>DMA_OUT_LINK_CH0_REG.</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set this bit to stop dealing with the outlink descriptors.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set this bit to start dealing with the outlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set this bit to restart a new outlink from the last address.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK</name>
+              <description>1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_STATE_CH0</name>
+          <description>DMA_OUT_STATE_CH0_REG.</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_ADDR</name>
+              <description>This register stores the current outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_DES_ADDR_CH0</name>
+          <description>DMA_OUT_EOF_DES_ADDR_CH0_REG.</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_BFR_DES_ADDR_CH0</name>
+          <description>DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor before the last outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_CH0</name>
+          <description>DMA_OUT_DSCR_CH0_REG.</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR</name>
+              <description>The address of the current outlink descriptor y.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_BF0_CH0</name>
+          <description>DMA_OUT_DSCR_BF0_CH0_REG.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0</name>
+              <description>The address of the last outlink descriptor y-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_BF1_CH0</name>
+          <description>DMA_OUT_DSCR_BF1_CH0_REG.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PRI_CH0</name>
+          <description>DMA_OUT_PRI_CH0_REG.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_PRI</name>
+              <description>The priority of Tx channel 0. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PERI_SEL_CH0</name>
+          <description>DMA_OUT_PERI_SEL_CH0_REG.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_OUT_SEL</name>
+              <description>This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_CONF0_CH1</name>
+          <description>DMA_IN_CONF0_CH1_REG.</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <description>Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_CONF1_CH1</name>
+          <description>DMA_IN_CONF1_CH1_REG.</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INFIFO_STATUS_CH1</name>
+          <description>DMA_INFIFO_STATUS_CH1_REG.</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800003</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_FULL</name>
+              <description>L1 Rx FIFO full signal for Rx channel 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_EMPTY</name>
+              <description>L1 Rx FIFO empty signal for Rx channel 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT</name>
+              <description>The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_1B</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_2B</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_3B</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_4B</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_BUF_HUNGRY</name>
+              <description>reserved</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_POP_CH1</name>
+          <description>DMA_IN_POP_CH1_REG.</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA</name>
+              <description>This register stores the data popping from DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP</name>
+              <description>Set this bit to pop data from DMA FIFO.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_LINK_CH1</name>
+          <description>DMA_IN_LINK_CH1_REG.</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01100000</resetValue>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET</name>
+              <description>Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set this bit to stop dealing with the inlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set this bit to start dealing with the inlink descriptors.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set this bit to mount a new inlink descriptor.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_PARK</name>
+              <description>1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_STATE_CH1</name>
+          <description>DMA_IN_STATE_CH1_REG.</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_ADDR</name>
+              <description>This register stores the current inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_SUC_EOF_DES_ADDR_CH1</name>
+          <description>DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_ERR_EOF_DES_ADDR_CH1</name>
+          <description>DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_ERR_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_CH1</name>
+          <description>DMA_IN_DSCR_CH1_REG.</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR</name>
+              <description>The address of the current inlink descriptor x.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_BF0_CH1</name>
+          <description>DMA_IN_DSCR_BF0_CH1_REG.</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0</name>
+              <description>The address of the last inlink descriptor x-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_BF1_CH1</name>
+          <description>DMA_IN_DSCR_BF1_CH1_REG.</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_PRI_CH1</name>
+          <description>DMA_IN_PRI_CH1_REG.</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_PRI</name>
+              <description>The priority of Rx channel 1. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_PERI_SEL_CH1</name>
+          <description>DMA_IN_PERI_SEL_CH1_REG.</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_IN_SEL</name>
+              <description>This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_CONF0_CH1</name>
+          <description>DMA_OUT_CONF0_CH1_REG.</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>OUT_RST</name>
+              <description>This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_CONF1_CH1</name>
+          <description>DMA_OUT_CONF1_CH1_REG.</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTFIFO_STATUS_CH1</name>
+          <description>DMA_OUTFIFO_STATUS_CH1_REG.</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800002</resetValue>
+          <fields>
+            <field>
+              <name>OUTFIFO_FULL</name>
+              <description>L1 Tx FIFO full signal for Tx channel 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY</name>
+              <description>L1 Tx FIFO empty signal for Tx channel 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT</name>
+              <description>The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_1B</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_2B</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_3B</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_4B</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PUSH_CH1</name>
+          <description>DMA_OUT_PUSH_CH1_REG.</description>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA</name>
+              <description>This register stores the data that need to be pushed into DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH</name>
+              <description>Set this bit to push data into DMA FIFO.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_LINK_CH1</name>
+          <description>DMA_OUT_LINK_CH1_REG.</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set this bit to stop dealing with the outlink descriptors.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set this bit to start dealing with the outlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set this bit to restart a new outlink from the last address.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK</name>
+              <description>1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_STATE_CH1</name>
+          <description>DMA_OUT_STATE_CH1_REG.</description>
+          <addressOffset>0x1A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_ADDR</name>
+              <description>This register stores the current outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_DES_ADDR_CH1</name>
+          <description>DMA_OUT_EOF_DES_ADDR_CH1_REG.</description>
+          <addressOffset>0x1A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_BFR_DES_ADDR_CH1</name>
+          <description>DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.</description>
+          <addressOffset>0x1AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor before the last outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_CH1</name>
+          <description>DMA_OUT_DSCR_CH1_REG.</description>
+          <addressOffset>0x1B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR</name>
+              <description>The address of the current outlink descriptor y.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_BF0_CH1</name>
+          <description>DMA_OUT_DSCR_BF0_CH1_REG.</description>
+          <addressOffset>0x1B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0</name>
+              <description>The address of the last outlink descriptor y-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_BF1_CH1</name>
+          <description>DMA_OUT_DSCR_BF1_CH1_REG.</description>
+          <addressOffset>0x1B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PRI_CH1</name>
+          <description>DMA_OUT_PRI_CH1_REG.</description>
+          <addressOffset>0x1BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_PRI</name>
+              <description>The priority of Tx channel 1. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PERI_SEL_CH1</name>
+          <description>DMA_OUT_PERI_SEL_CH1_REG.</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_OUT_SEL</name>
+              <description>This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_CONF0_CH2</name>
+          <description>DMA_IN_CONF0_CH2_REG.</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <description>Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_CONF1_CH2</name>
+          <description>DMA_IN_CONF1_CH2_REG.</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INFIFO_STATUS_CH2</name>
+          <description>DMA_INFIFO_STATUS_CH2_REG.</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800003</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_FULL</name>
+              <description>L1 Rx FIFO full signal for Rx channel 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_EMPTY</name>
+              <description>L1 Rx FIFO empty signal for Rx channel 2.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT</name>
+              <description>The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_1B</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_2B</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_3B</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_4B</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_BUF_HUNGRY</name>
+              <description>reserved</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_POP_CH2</name>
+          <description>DMA_IN_POP_CH2_REG.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA</name>
+              <description>This register stores the data popping from DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP</name>
+              <description>Set this bit to pop data from DMA FIFO.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_LINK_CH2</name>
+          <description>DMA_IN_LINK_CH2_REG.</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01100000</resetValue>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET</name>
+              <description>Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set this bit to stop dealing with the inlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set this bit to start dealing with the inlink descriptors.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set this bit to mount a new inlink descriptor.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_PARK</name>
+              <description>1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_STATE_CH2</name>
+          <description>DMA_IN_STATE_CH2_REG.</description>
+          <addressOffset>0x204</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_ADDR</name>
+              <description>This register stores the current inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_SUC_EOF_DES_ADDR_CH2</name>
+          <description>DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.</description>
+          <addressOffset>0x208</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_ERR_EOF_DES_ADDR_CH2</name>
+          <description>DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.</description>
+          <addressOffset>0x20C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_ERR_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_CH2</name>
+          <description>DMA_IN_DSCR_CH2_REG.</description>
+          <addressOffset>0x210</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR</name>
+              <description>The address of the current inlink descriptor x.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_BF0_CH2</name>
+          <description>DMA_IN_DSCR_BF0_CH2_REG.</description>
+          <addressOffset>0x214</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0</name>
+              <description>The address of the last inlink descriptor x-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DSCR_BF1_CH2</name>
+          <description>DMA_IN_DSCR_BF1_CH2_REG.</description>
+          <addressOffset>0x218</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_PRI_CH2</name>
+          <description>DMA_IN_PRI_CH2_REG.</description>
+          <addressOffset>0x21C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_PRI</name>
+              <description>The priority of Rx channel 2. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_PERI_SEL_CH2</name>
+          <description>DMA_IN_PERI_SEL_CH2_REG.</description>
+          <addressOffset>0x220</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_IN_SEL</name>
+              <description>This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_CONF0_CH2</name>
+          <description>DMA_OUT_CONF0_CH2_REG.</description>
+          <addressOffset>0x250</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>OUT_RST</name>
+              <description>This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_CONF1_CH2</name>
+          <description>DMA_OUT_CONF1_CH2_REG.</description>
+          <addressOffset>0x254</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTFIFO_STATUS_CH2</name>
+          <description>DMA_OUTFIFO_STATUS_CH2_REG.</description>
+          <addressOffset>0x258</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800002</resetValue>
+          <fields>
+            <field>
+              <name>OUTFIFO_FULL</name>
+              <description>L1 Tx FIFO full signal for Tx channel 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY</name>
+              <description>L1 Tx FIFO empty signal for Tx channel 2.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT</name>
+              <description>The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_1B</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_2B</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_3B</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_4B</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PUSH_CH2</name>
+          <description>DMA_OUT_PUSH_CH2_REG.</description>
+          <addressOffset>0x25C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA</name>
+              <description>This register stores the data that need to be pushed into DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH</name>
+              <description>Set this bit to push data into DMA FIFO.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_LINK_CH2</name>
+          <description>DMA_OUT_LINK_CH2_REG.</description>
+          <addressOffset>0x260</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set this bit to stop dealing with the outlink descriptors.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set this bit to start dealing with the outlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set this bit to restart a new outlink from the last address.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK</name>
+              <description>1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_STATE_CH2</name>
+          <description>DMA_OUT_STATE_CH2_REG.</description>
+          <addressOffset>0x264</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_ADDR</name>
+              <description>This register stores the current outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_DES_ADDR_CH2</name>
+          <description>DMA_OUT_EOF_DES_ADDR_CH2_REG.</description>
+          <addressOffset>0x268</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_BFR_DES_ADDR_CH2</name>
+          <description>DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.</description>
+          <addressOffset>0x26C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor before the last outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_CH2</name>
+          <description>DMA_OUT_DSCR_CH2_REG.</description>
+          <addressOffset>0x270</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR</name>
+              <description>The address of the current outlink descriptor y.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_BF0_CH2</name>
+          <description>DMA_OUT_DSCR_BF0_CH2_REG.</description>
+          <addressOffset>0x274</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0</name>
+              <description>The address of the last outlink descriptor y-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DSCR_BF1_CH2</name>
+          <description>DMA_OUT_DSCR_BF1_CH2_REG.</description>
+          <addressOffset>0x278</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PRI_CH2</name>
+          <description>DMA_OUT_PRI_CH2_REG.</description>
+          <addressOffset>0x27C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_PRI</name>
+              <description>The priority of Tx channel 2. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_PERI_SEL_CH2</name>
+          <description>DMA_OUT_PERI_SEL_CH2_REG.</description>
+          <addressOffset>0x280</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_OUT_SEL</name>
+              <description>This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DS</name>
+      <description>Digital Signature</description>
+      <groupName>DS</groupName>
+      <baseAddress>0x6003D000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x108C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Y_MEM[%s]</name>
+          <description>memory that stores Y</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>memory that stores M</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>RB_MEM[%s]</name>
+          <description>memory that stores Rb</description>
+          <addressOffset>0x400</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>48</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>BOX_MEM[%s]</name>
+          <description>memory that stores BOX</description>
+          <addressOffset>0x600</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>X_MEM[%s]</name>
+          <description>memory that stores X</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Z_MEM[%s]</name>
+          <description>memory that stores Z</description>
+          <addressOffset>0xA00</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>SET_START</name>
+          <description>DS start control register</description>
+          <addressOffset>0xE00</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>set this bit to start DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_CONTINUE</name>
+          <description>DS continue control register</description>
+          <addressOffset>0xE04</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_CONTINUE</name>
+              <description>set this bit to continue DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_FINISH</name>
+          <description>DS finish control register</description>
+          <addressOffset>0xE08</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_FINISH</name>
+              <description>Set this bit to finish DS process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>DS query busy register</description>
+          <addressOffset>0xE0C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_BUSY</name>
+              <description>digital signature state. 1'b0: idle, 1'b1: busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_KEY_WRONG</name>
+          <description>DS query key-wrong counter register</description>
+          <addressOffset>0xE10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_KEY_WRONG</name>
+              <description>digital signature key wrong counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_CHECK</name>
+          <description>DS query check result register</description>
+          <addressOffset>0xE14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MD_ERROR</name>
+              <description>MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PADDING_BAD</name>
+              <description>padding checkout result. 1'b0: a good padding, 1'b1: a bad padding</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>DS version control register</description>
+          <addressOffset>0xE20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200618</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>ds version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EFUSE</name>
+      <description>eFuse Controller</description>
+      <groupName>EFUSE</groupName>
+      <baseAddress>0x60008800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1CC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EFUSE</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PGM_DATA0</name>
+          <description>Register 0 that stores data to be programmed.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_0</name>
+              <description>The content of the 0th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA1</name>
+          <description>Register 1 that stores data to be programmed.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_1</name>
+              <description>The content of the 1st 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA2</name>
+          <description>Register 2 that stores data to be programmed.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_2</name>
+              <description>The content of the 2nd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA3</name>
+          <description>Register 3 that stores data to be programmed.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_3</name>
+              <description>The content of the 3rd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA4</name>
+          <description>Register 4 that stores data to be programmed.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_4</name>
+              <description>The content of the 4th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA5</name>
+          <description>Register 5 that stores data to be programmed.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_5</name>
+              <description>The content of the 5th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA6</name>
+          <description>Register 6 that stores data to be programmed.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_6</name>
+              <description>The content of the 6th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA7</name>
+          <description>Register 7 that stores data to be programmed.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_7</name>
+              <description>The content of the 7th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE0</name>
+          <description>Register 0 that stores the RS code to be programmed.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_0</name>
+              <description>The content of the 0th 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE1</name>
+          <description>Register 1 that stores the RS code to be programmed.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_1</name>
+              <description>The content of the 1st 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE2</name>
+          <description>Register 2 that stores the RS code to be programmed.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_2</name>
+              <description>The content of the 2nd 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_WR_DIS</name>
+          <description>BLOCK0 data register 0.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_DIS</name>
+              <description>Disable programming of individual eFuses.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA0</name>
+          <description>BLOCK0 data register 1.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS</name>
+              <description>Set this bit to disable reading from BlOCK4-10.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_RTC_RAM_BOOT</name>
+              <description>Set this bit to disable boot from RTC RAM.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE</name>
+              <description>Set this bit to disable Icache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_JTAG</name>
+              <description>Set this bit to disable function of usb switch to jtag in module of usb device.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE</name>
+              <description>Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DEVICE</name>
+              <description>Set this bit to disable usb device.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD</name>
+              <description>Set this bit to disable the function that forces chip into download mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED6</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_CAN</name>
+              <description>Set this bit to disable CAN function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>JTAG_SEL_ENABLE</name>
+              <description>Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG</name>
+              <description>Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG</name>
+              <description>Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>Set this bit to disable flash encryption when in download boot modes.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH</name>
+              <description>Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL</name>
+              <description>Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS</name>
+              <description>Set this bit to exchange USB D+ and D- pins.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_AS_GPIO</name>
+              <description>Set this bit to vdd spi pin function as gpio.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTLC_GPIO_ENABLE</name>
+              <description>Enable btlc gpio.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWERGLITCH_EN</name>
+              <description>Set this bit to enable power glitch function.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_DSENSE</name>
+              <description>Sample delay configuration of power glitch.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA1</name>
+          <description>BLOCK0 data register 2.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED2</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL</name>
+              <description>Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT</name>
+              <description>Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0</name>
+              <description>Set this bit to enable revoking first secure boot key.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1</name>
+              <description>Set this bit to enable revoking second secure boot key.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2</name>
+              <description>Set this bit to enable revoking third secure boot key.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0</name>
+              <description>Purpose of Key0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1</name>
+              <description>Purpose of Key1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA2</name>
+          <description>BLOCK0 data register 3.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2</name>
+              <description>Purpose of Key2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3</name>
+              <description>Purpose of Key3.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4</name>
+              <description>Purpose of Key4.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5</name>
+              <description>Purpose of Key5.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN</name>
+              <description>Set this bit to enable secure boot.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE</name>
+              <description>Set this bit to enable revoking aggressive secure boot.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW</name>
+              <description>Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA3</name>
+          <description>BLOCK0 data register 4.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE</name>
+              <description>Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_LEGACY_SPI_BOOT</name>
+              <description>Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CHANNEL</name>
+              <description>Selectes the default UART print channel. 0: UART0. 1: UART1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_ECC_MODE</name>
+              <description>Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DOWNLOAD_MODE</name>
+              <description>Set this bit to disable UART download mode through USB.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD</name>
+              <description>Set this bit to enable secure UART download mode.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL</name>
+              <description>Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIN_POWER_SELECTION</name>
+              <description>GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TYPE</name>
+              <description>Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_PAGE_SIZE</name>
+              <description>Set Flash page size.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_ECC_EN</name>
+              <description>Set 1 to enable ECC for flash boot.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME</name>
+              <description>Set this bit to force ROM code to send a resume command during SPI boot.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION</name>
+              <description>Secure version (used by ESP-IDF anti-rollback feature).</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED1</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA4</name>
+          <description>BLOCK0 data register 5.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED4</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_0</name>
+          <description>BLOCK1 data register 0.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_0</name>
+              <description>Stores the low 32 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_1</name>
+          <description>BLOCK1 data register 1.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_1</name>
+              <description>Stores the high 16 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_PAD_CONF_0</name>
+              <description>Stores the zeroth part of SPI_PAD_CONF.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_2</name>
+          <description>BLOCK1 data register 2.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_PAD_CONF_1</name>
+              <description>Stores the first part of SPI_PAD_CONF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_3</name>
+          <description>BLOCK1 data register 3.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_PAD_CONF_2</name>
+              <description>Stores the second part of SPI_PAD_CONF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_DATA_PART0_0</name>
+              <description>Stores the fist 14 bits of the zeroth part of system data.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_4</name>
+          <description>BLOCK1 data register 4.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_1</name>
+              <description>Stores the fist 32 bits of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_5</name>
+          <description>BLOCK1 data register 5.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_2</name>
+              <description>Stores the second 32 bits of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA0</name>
+          <description>Register 0 of BLOCK2 (system).</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_0</name>
+              <description>Stores the zeroth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA1</name>
+          <description>Register 1 of BLOCK2 (system).</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_1</name>
+              <description>Stores the first 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA2</name>
+          <description>Register 2 of BLOCK2 (system).</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_2</name>
+              <description>Stores the second 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA3</name>
+          <description>Register 3 of BLOCK2 (system).</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_3</name>
+              <description>Stores the third 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA4</name>
+          <description>Register 4 of BLOCK2 (system).</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_4</name>
+              <description>Stores the fourth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA5</name>
+          <description>Register 5 of BLOCK2 (system).</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_5</name>
+              <description>Stores the fifth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA6</name>
+          <description>Register 6 of BLOCK2 (system).</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_6</name>
+              <description>Stores the sixth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA7</name>
+          <description>Register 7 of BLOCK2 (system).</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_7</name>
+              <description>Stores the seventh 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA0</name>
+          <description>Register 0 of BLOCK3 (user).</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA0</name>
+              <description>Stores the zeroth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA1</name>
+          <description>Register 1 of BLOCK3 (user).</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA1</name>
+              <description>Stores the first 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA2</name>
+          <description>Register 2 of BLOCK3 (user).</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA2</name>
+              <description>Stores the second 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA3</name>
+          <description>Register 3 of BLOCK3 (user).</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA3</name>
+              <description>Stores the third 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA4</name>
+          <description>Register 4 of BLOCK3 (user).</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA4</name>
+              <description>Stores the fourth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA5</name>
+          <description>Register 5 of BLOCK3 (user).</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA5</name>
+              <description>Stores the fifth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA6</name>
+          <description>Register 6 of BLOCK3 (user).</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA6</name>
+              <description>Stores the sixth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA7</name>
+          <description>Register 7 of BLOCK3 (user).</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA7</name>
+              <description>Stores the seventh 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA0</name>
+          <description>Register 0 of BLOCK4 (KEY0).</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA1</name>
+          <description>Register 1 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA1</name>
+              <description>Stores the first 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA2</name>
+          <description>Register 2 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA2</name>
+              <description>Stores the second 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA3</name>
+          <description>Register 3 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA3</name>
+              <description>Stores the third 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA4</name>
+          <description>Register 4 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA5</name>
+          <description>Register 5 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA6</name>
+          <description>Register 6 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA7</name>
+          <description>Register 7 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA0</name>
+          <description>Register 0 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA1</name>
+          <description>Register 1 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA1</name>
+              <description>Stores the first 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA2</name>
+          <description>Register 2 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA2</name>
+              <description>Stores the second 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA3</name>
+          <description>Register 3 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA3</name>
+              <description>Stores the third 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA4</name>
+          <description>Register 4 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA5</name>
+          <description>Register 5 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA6</name>
+          <description>Register 6 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA7</name>
+          <description>Register 7 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA0</name>
+          <description>Register 0 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA1</name>
+          <description>Register 1 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA1</name>
+              <description>Stores the first 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA2</name>
+          <description>Register 2 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA2</name>
+              <description>Stores the second 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA3</name>
+          <description>Register 3 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA3</name>
+              <description>Stores the third 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA4</name>
+          <description>Register 4 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA5</name>
+          <description>Register 5 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA6</name>
+          <description>Register 6 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA7</name>
+          <description>Register 7 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA0</name>
+          <description>Register 0 of BLOCK7 (KEY3).</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA1</name>
+          <description>Register 1 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA1</name>
+              <description>Stores the first 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA2</name>
+          <description>Register 2 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA2</name>
+              <description>Stores the second 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA3</name>
+          <description>Register 3 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA3</name>
+              <description>Stores the third 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA4</name>
+          <description>Register 4 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA5</name>
+          <description>Register 5 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA6</name>
+          <description>Register 6 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA7</name>
+          <description>Register 7 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA0</name>
+          <description>Register 0 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA1</name>
+          <description>Register 1 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA1</name>
+              <description>Stores the first 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA2</name>
+          <description>Register 2 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA2</name>
+              <description>Stores the second 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA3</name>
+          <description>Register 3 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA3</name>
+              <description>Stores the third 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA4</name>
+          <description>Register 4 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA5</name>
+          <description>Register 5 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA6</name>
+          <description>Register 6 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA7</name>
+          <description>Register 7 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA0</name>
+          <description>Register 0 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA1</name>
+          <description>Register 1 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA1</name>
+              <description>Stores the first 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA2</name>
+          <description>Register 2 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA2</name>
+              <description>Stores the second 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA3</name>
+          <description>Register 3 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA3</name>
+              <description>Stores the third 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA4</name>
+          <description>Register 4 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA5</name>
+          <description>Register 5 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA6</name>
+          <description>Register 6 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA7</name>
+          <description>Register 7 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA0</name>
+          <description>Register 0 of BLOCK10 (system).</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_0</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA1</name>
+          <description>Register 1 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_1</name>
+              <description>Stores the 1st 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA2</name>
+          <description>Register 2 of BLOCK10 (system).</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_2</name>
+              <description>Stores the 2nd 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA3</name>
+          <description>Register 3 of BLOCK10 (system).</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_3</name>
+              <description>Stores the 3rd 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA4</name>
+          <description>Register 4 of BLOCK10 (system).</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_4</name>
+              <description>Stores the 4th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA5</name>
+          <description>Register 5 of BLOCK10 (system).</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_5</name>
+              <description>Stores the 5th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA6</name>
+          <description>Register 6 of BLOCK10 (system).</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_6</name>
+              <description>Stores the 6th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA7</name>
+          <description>Register 7 of BLOCK10 (system).</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_7</name>
+              <description>Stores the 7th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR0</name>
+          <description>Programming error record register 0 of BLOCK0.</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS_ERR</name>
+              <description>If any bit in RD_DIS is 1, then it indicates a programming error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_RTC_RAM_BOOT_ERR</name>
+              <description>If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE_ERR</name>
+              <description>If DIS_ICACHE is 1, then it indicates a programming error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_JTAG_ERR</name>
+              <description>If DIS_USB_JTAG is 1, then it indicates a programming error.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE_ERR</name>
+              <description>If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DEVICE_ERR</name>
+              <description>If DIS_USB_DEVICE is 1, then it indicates a programming error.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD_ERR</name>
+              <description>If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED6_ERR</name>
+              <description>Reserved.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_CAN_ERR</name>
+              <description>If DIS_CAN is 1, then it indicates a programming error.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>JTAG_SEL_ENABLE_ERR</name>
+              <description>If JTAG_SEL_ENABLE is 1, then it indicates a programming error.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG_ERR</name>
+              <description>If SOFT_DIS_JTAG is 1, then it indicates a programming error.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG_ERR</name>
+              <description>If DIS_PAD_JTAG is 1, then it indicates a programming error.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR</name>
+              <description>If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH_ERR</name>
+              <description>If any bit in USB_DREFH is 1, then it indicates a programming error.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL_ERR</name>
+              <description>If any bit in USB_DREFL is 1, then it indicates a programming error.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS_ERR</name>
+              <description>If USB_EXCHG_PINS is 1, then it indicates a programming error.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_AS_GPIO_ERR</name>
+              <description>If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTLC_GPIO_ENABLE_ERR</name>
+              <description>If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWERGLITCH_EN_ERR</name>
+              <description>If POWERGLITCH_EN is 1, then it indicates a programming error.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_DSENSE_ERR</name>
+              <description>If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR1</name>
+          <description>Programming error record register 1 of BLOCK0.</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED2_ERR</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL_ERR</name>
+              <description>If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT_ERR</name>
+              <description>If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0_ERR</name>
+              <description>If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1_ERR</name>
+              <description>If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2_ERR</name>
+              <description>If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0_ERR</name>
+              <description>If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1_ERR</name>
+              <description>If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR2</name>
+          <description>Programming error record register 2 of BLOCK0.</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2_ERR</name>
+              <description>If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3_ERR</name>
+              <description>If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4_ERR</name>
+              <description>If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5_ERR</name>
+              <description>If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_ERR</name>
+              <description>Reserved.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN_ERR</name>
+              <description>If SECURE_BOOT_EN is 1, then it indicates a programming error.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE_ERR</name>
+              <description>If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR</name>
+              <description>Reserved.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW_ERR</name>
+              <description>If any bit in FLASH_TPUM is 1, then it indicates a programming error.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR3</name>
+          <description>Programming error record register 3 of BLOCK0.</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE_ERR</name>
+              <description>If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_LEGACY_SPI_BOOT_ERR</name>
+              <description>If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CHANNEL_ERR</name>
+              <description>If UART_PRINT_CHANNEL is 1, then it indicates a programming error.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_ECC_MODE_ERR</name>
+              <description>If FLASH_ECC_MODE is 1, then it indicates a programming error.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DOWNLOAD_MODE_ERR</name>
+              <description>If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD_ERR</name>
+              <description>If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL_ERR</name>
+              <description>If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIN_POWER_SELECTION_ERR</name>
+              <description>If PIN_POWER_SELECTION is 1, then it indicates a programming error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TYPE_ERR</name>
+              <description>If FLASH_TYPE is 1, then it indicates a programming error.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_PAGE_SIZE_ERR</name>
+              <description>If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_ECC_EN_ERR</name>
+              <description>If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME_ERR</name>
+              <description>If FORCE_SEND_RESUME is 1, then it indicates a programming error.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION_ERR</name>
+              <description>If any bit in SECURE_VERSION is 1, then it indicates a programming error.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED1_ERR</name>
+              <description>Reserved.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR4</name>
+          <description>Programming error record register 4 of BLOCK0.</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED4_ERR</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR0</name>
+          <description>Programming error record register 0 of BLOCK1-10.</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_SPI_8M_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAC_SPI_8M_FAIL</name>
+              <description>0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_FAIL</name>
+              <description>0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_FAIL</name>
+              <description>0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_FAIL</name>
+              <description>0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_FAIL</name>
+              <description>0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_FAIL</name>
+              <description>0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_FAIL</name>
+              <description>0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_FAIL</name>
+              <description>0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR1</name>
+          <description>Programming error record register 1 of BLOCK1-10.</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY5_FAIL</name>
+              <description>0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_FAIL</name>
+              <description>0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>eFuse clcok configuration register.</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EFUSE_MEM_FORCE_PD</name>
+              <description>Set this bit to force eFuse SRAM into power-saving mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>Set this bit and force to activate clock signal of eFuse SRAM.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_MEM_FORCE_PU</name>
+              <description>Set this bit to force eFuse SRAM into working mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Set this bit and force to enable clock signal of eFuse memory.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>eFuse operation mode configuraiton register;</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OP_CODE</name>
+              <description>0x5A5A: Operate programming command 0x5AA5: Operate read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>eFuse status register.</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Indicates the state of the eFuse state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_LOAD_SW</name>
+              <description>The value of OTP_LOAD_SW.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_C_SYNC2</name>
+              <description>The value of OTP_VDDQ_C_SYNC2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_STROBE_SW</name>
+              <description>The value of OTP_STROBE_SW.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_CSB_SW</name>
+              <description>The value of OTP_CSB_SW.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_PGENB_SW</name>
+              <description>The value of OTP_PGENB_SW.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_IS_SW</name>
+              <description>The value of OTP_VDDQ_IS_SW.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REPEAT_ERR_CNT</name>
+              <description>Indicates the number of error bits during programming BLOCK0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>eFuse command register.</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_CMD</name>
+              <description>Set this bit to send read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_CMD</name>
+              <description>Set this bit to send programming command.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BLK_NUM</name>
+              <description>The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>eFuse raw interrupt register.</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_RAW</name>
+              <description>The raw bit signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_RAW</name>
+              <description>The raw bit signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>eFuse interrupt status register.</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ST</name>
+              <description>The status signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ST</name>
+              <description>The status signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>eFuse interrupt enable register.</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ENA</name>
+              <description>The enable signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ENA</name>
+              <description>The enable signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>eFuse interrupt clear register.</description>
+          <addressOffset>0x1E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_CLR</name>
+              <description>The clear signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_CLR</name>
+              <description>The clear signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAC_CONF</name>
+          <description>Controls the eFuse programming voltage.</description>
+          <addressOffset>0x1E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001FE1C</resetValue>
+          <fields>
+            <field>
+              <name>DAC_CLK_DIV</name>
+              <description>Controls the division factor of the rising clock of the programming voltage.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_PAD_SEL</name>
+              <description>Don't care.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_NUM</name>
+              <description>Controls the rising period of the programming voltage.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OE_CLR</name>
+              <description>Reduces the power supply of the programming voltage.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_TIM_CONF</name>
+          <description>Configures read timing parameters.</description>
+          <addressOffset>0x1EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x12000000</resetValue>
+          <fields>
+            <field>
+              <name>READ_INIT_NUM</name>
+              <description>Configures the initial read time of eFuse.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF1</name>
+          <description>Configurarion register 1 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00288000</resetValue>
+          <fields>
+            <field>
+              <name>PWR_ON_NUM</name>
+              <description>Configures the power up time for VDDQ.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF2</name>
+          <description>Configurarion register 2 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000190</resetValue>
+          <fields>
+            <field>
+              <name>PWR_OFF_NUM</name>
+              <description>Configures the power outage time for VDDQ.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>eFuse version register.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007200</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Stores eFuse version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EXTMEM</name>
+      <description>External Memory</description>
+      <groupName>EXTMEM</groupName>
+      <baseAddress>0x600C4000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x108</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>ICACHE_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_ENABLE</name>
+              <description>The bit is used to activate the data cache. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_CTRL1</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_SHUT_IBUS</name>
+              <description>The bit is used to disable core0 ibus, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SHUT_DBUS</name>
+              <description>The bit is used to disable core1 ibus, 0: enable, 1: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_TAG_POWER_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOCK_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOCK_SCT0_EN</name>
+              <description>The bit is used to enable the first section of prelock function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOCK_SCT1_EN</name>
+              <description>The bit is used to enable the second section of prelock function.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOCK_SCT0_ADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOCK_SCT0_ADDR</name>
+              <description>The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOCK_SCT1_ADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOCK_SCT1_ADDR</name>
+              <description>The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOCK_SCT_SIZE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOCK_SCT1_SIZE</name>
+              <description>The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOCK_SCT0_SIZE</name>
+              <description>The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_LOCK_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_LOCK_ENA</name>
+              <description>The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_UNLOCK_ENA</name>
+              <description>The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_LOCK_DONE</name>
+              <description>The bit is used to indicate unlock/lock operation is finished.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_LOCK_ADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_LOCK_ADDR</name>
+              <description>The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_LOCK_SIZE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_LOCK_SIZE</name>
+              <description>The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_INVALIDATE_ENA</name>
+              <description>The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SYNC_DONE</name>
+              <description>The bit is used to indicate invalidate operation is finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_ADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_ADDR</name>
+              <description>The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_SIZE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_SIZE</name>
+              <description>The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_DONE</name>
+              <description>The bit is used to indicate preload operation is finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_ORDER</name>
+              <description>The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_ADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_ADDR</name>
+              <description>The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_SIZE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_SIZE</name>
+              <description>The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT0_ENA</name>
+              <description>The bits are used to enable the first section for autoload operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT1_ENA</name>
+              <description>The bits are used to enable the second section for autoload operation.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate autoload operation is finished.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_ORDER</name>
+              <description>The bits are used to configure the direction of autoload. 1: descending, 0: ascending.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_RQST</name>
+              <description>The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_SCT0_ADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT0_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_SCT0_SIZE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT0_SIZE</name>
+              <description>The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_SCT1_ADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT1_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_SCT1_SIZE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT1_SIZE</name>
+              <description>The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_TO_FLASH_START_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x42000000</resetValue>
+          <fields>
+            <field>
+              <name>IBUS_TO_FLASH_START_VADDR</name>
+              <description>The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_TO_FLASH_END_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x427FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>IBUS_TO_FLASH_END_VADDR</name>
+              <description>The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_TO_FLASH_START_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3C000000</resetValue>
+          <fields>
+            <field>
+              <name>DBUS_TO_FLASH_START_VADDR</name>
+              <description>The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_TO_FLASH_END_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3C7FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DBUS_TO_FLASH_END_VADDR</name>
+              <description>The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ACS_CNT_CLR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS_ACS_CNT_CLR</name>
+              <description>The bit is used to clear ibus counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_CNT_CLR</name>
+              <description>The bit is used to clear dbus counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_ACS_MISS_CNT</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS_ACS_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by ibus access flash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_ACS_CNT</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS_ACS_CNT</name>
+              <description>The bits are used to count the number of ibus access flash through icache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_ACS_FLASH_MISS_CNT</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS_ACS_FLASH_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by dbus access flash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_ACS_CNT</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS_ACS_CNT</name>
+              <description>The bits are used to count the number of dbus access flash through icache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ILG_INT_ENA</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_OP_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by sync configurations fault.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_OP_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by preload configurations fault.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by mmu entry fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IBUS_CNT_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt by ibus counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUS_CNT_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt by dbus counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ILG_INT_CLR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_OP_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by sync configurations fault.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_OP_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by preload configurations fault.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by mmu entry fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IBUS_CNT_OVF_INT_CLR</name>
+              <description>The bit is used to clear interrupt by ibus counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DBUS_CNT_OVF_INT_CLR</name>
+              <description>The bit is used to clear interrupt by dbus counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ILG_INT_ST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_OP_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by sync configurations fault.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_OP_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by preload configurations fault.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by mmu entry fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS_ACS_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_FLASH_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus access flash miss counter overflow.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_ACS_CACHE_INT_ENA</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ACS_MSK_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WR_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ACS_MSK_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_WR_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by dbus trying to write icache</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_ACS_CACHE_INT_CLR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ACS_MSK_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WR_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ACS_MSK_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_WR_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by dbus trying to write icache</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_ACS_CACHE_INT_ST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ACS_MSK_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WR_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ACS_MSK_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_WR_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by dbus trying to write icache</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_DBUS_REJECT_ST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_DBUS_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_WORLD</name>
+              <description>The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_DBUS_REJECT_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE0_DBUS_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access dbus when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_IBUS_REJECT_ST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WORLD</name>
+              <description>The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_IBUS_REJECT_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_FAULT_CONTENT</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_FAULT_CONTENT</name>
+              <description>The bits are used to indicate the content of mmu entry which cause mmu fault..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_FAULT_CODE</name>
+              <description>The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_FAULT_VADDR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_FAULT_VADDR</name>
+              <description>The bits are used to indicate the virtual address which cause mmu fault..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_WRAP_AROUND_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_FLASH_WRAP_AROUND</name>
+              <description>The bit is used to enable wrap around mode when read data from flash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_POWER_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_MMU_MEM_FORCE_ON</name>
+              <description>The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_MEM_FORCE_PD</name>
+              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_MEM_FORCE_PU</name>
+              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_STATE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_STATE</name>
+              <description>The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_DISABLE_DB_ENCRYPT</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_DISABLE_G0CB_DECRYPT</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>CLK_FORCE_ON_MANUAL_CRYPT</name>
+              <description>The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_FORCE_ON_AUTO_CRYPT</name>
+              <description>The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_FORCE_ON_CRYPT</name>
+              <description>The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_PRELOAD_INT_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by  icache pre-load done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by  icache pre-load done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by  icache pre-load done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SYNC_INT_CTRL</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by  icache sync done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_SYNC_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by  icache sync done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SYNC_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by  icache sync done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_OWNER</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_OWNER</name>
+              <description>The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CONF_MISC</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT</name>
+              <description>The bit is used to disable checking mmu entry fault by preload operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT</name>
+              <description>The bit is used to disable checking mmu entry fault by sync operation.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_TRACE_ENA</name>
+              <description>The bit is used to enable cache trace function.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_FREEZE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENA</name>
+              <description>The bit is used to enable icache freeze mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DONE</name>
+              <description>The bit is used to indicate icache freeze success</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_ATOMIC_OPERATE_ENA</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_ATOMIC_OPERATE_ENA</name>
+              <description>The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_REQUEST</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BYPASS</name>
+              <description>The bit is used to disable request recording which could cause performance issue</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_PMS_TBL_LOCK</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS_PMS_LOCK</name>
+              <description>The bit is used to configure the ibus permission control section boundary0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_PMS_TBL_BOUNDARY0</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS_PMS_BOUNDARY0</name>
+              <description>The bit is used to configure the ibus permission control section boundary0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_PMS_TBL_BOUNDARY1</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>IBUS_PMS_BOUNDARY1</name>
+              <description>The bit is used to configure the ibus permission control section boundary1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_PMS_TBL_BOUNDARY2</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>IBUS_PMS_BOUNDARY2</name>
+              <description>The bit is used to configure the ibus permission control section boundary2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_PMS_TBL_ATTR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>IBUS_PMS_SCT1_ATTR</name>
+              <description>The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IBUS_PMS_SCT2_ATTR</name>
+              <description>The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_PMS_TBL_LOCK</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS_PMS_LOCK</name>
+              <description>The bit is used to configure the ibus permission control section boundary0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_PMS_TBL_BOUNDARY0</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS_PMS_BOUNDARY0</name>
+              <description>The bit is used to configure the dbus permission control section boundary0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_PMS_TBL_BOUNDARY1</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>DBUS_PMS_BOUNDARY1</name>
+              <description>The bit is used to configure the dbus permission control section boundary1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_PMS_TBL_BOUNDARY2</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>DBUS_PMS_BOUNDARY2</name>
+              <description>The bit is used to configure the dbus permission control section boundary2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_PMS_TBL_ATTR</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>DBUS_PMS_SCT1_ATTR</name>
+              <description>The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUS_PMS_SCT2_ATTR</name>
+              <description>The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>clock gate enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_DATE</name>
+          <description>This description will be updated in the near future.</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007160</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <baseAddress>0x60004000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x31C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>GPIO</name>
+        <value>16</value>
+      </interrupt>
+      <interrupt>
+        <name>GPIO_NMI</name>
+        <value>17</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BT_SELECT</name>
+          <description>GPIO bit select register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_SEL</name>
+              <description>GPIO bit select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT</name>
+          <description>GPIO output register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_ORIG</name>
+              <description>GPIO output register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TS</name>
+          <description>GPIO output set register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TS</name>
+              <description>GPIO output set register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TC</name>
+          <description>GPIO output clear register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TC</name>
+              <description>GPIO output clear register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SELECT</name>
+          <description>GPIO sdio select register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_SEL</name>
+              <description>GPIO sdio select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE</name>
+          <description>GPIO output enable register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO output enable register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TS</name>
+          <description>GPIO output enable set register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TS</name>
+              <description>GPIO output enable set register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <description>GPIO output enable clear register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TC</name>
+              <description>GPIO output enable clear register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STRAP</name>
+          <description>pad strapping register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRAPPING</name>
+              <description>pad strapping register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <description>GPIO input register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO input register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>GPIO interrupt status register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>GPIO interrupt status register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TS</name>
+          <description>GPIO interrupt status set register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TS</name>
+              <description>GPIO interrupt status set register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TC</name>
+          <description>GPIO interrupt status clear register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TC</name>
+              <description>GPIO interrupt status clear register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT</name>
+          <description>GPIO PRO_CPU interrupt status register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT</name>
+              <description>GPIO PRO_CPU interrupt status register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT</name>
+          <description>GPIO PRO_CPU(not shielded) interrupt status register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT</name>
+              <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT</name>
+          <description>GPIO CPUSDIO interrupt status register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT</name>
+              <description>GPIO CPUSDIO interrupt status register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>26</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-25</dimIndex>
+          <name>PIN%s</name>
+          <description>GPIO pin configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYNC2_BYPASS</name>
+              <description>set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>set this bit to select pad driver. 1:open-drain. 0:normal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC1_BYPASS</name>
+              <description>set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TYPE</name>
+              <description>set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENABLE</name>
+              <description>set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONFIG</name>
+              <description>reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_ENA</name>
+              <description>set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_NEXT</name>
+          <description>GPIO interrupt source register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INTERRUPT_NEXT</name>
+              <description>GPIO interrupt source register for GPIO0-25</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>128</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-127</dimIndex>
+          <name>FUNC%s_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>26</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-25</dimIndex>
+          <name>FUNC%s_OUT_SEL_CFG</name>
+          <description>GPIO output function select register</description>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>OUT_SEL</name>
+              <description>The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INV_SEL</name>
+              <description>set this bit to invert output signal.1:invert.0:not invert.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_SEL</name>
+              <description>set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_INV_SEL</name>
+              <description>set this bit to invert output enable signal.1:invert.0:not invert.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>GPIO clock gate register</description>
+          <addressOffset>0x62C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>set this bit to enable GPIO clock gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_DATE</name>
+          <description>GPIO version register</description>
+          <addressOffset>0x6FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02006130</resetValue>
+          <fields>
+            <field>
+              <name>REG_DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIOSD</name>
+      <description>Sigma-Delta Modulation</description>
+      <groupName>GPIOSD</groupName>
+      <baseAddress>0x60004F00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SIGMADELTA%s</name>
+          <description>Duty Cycle Configure Register of SDM%s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD0_IN</name>
+              <description>This field is used to configure the duty cycle of sigma delta modulation output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD0_PRESCALE</name>
+              <description>This field is used to set a divider value to divide APB clock.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_CG</name>
+          <description>Clock Gating Configure Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Clock enable bit of configuration registers for sigma delta modulation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_MISC</name>
+          <description>MISC Register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FUNCTION_CLK_EN</name>
+              <description>Clock enable bit of sigma delta modulation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SWAP</name>
+              <description>Reserved.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_VERSION</name>
+          <description>Version Control Register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02006230</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_SD_DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMAC</name>
+      <description>HMAC (Hash-based Message Authentication Code) Accelerator</description>
+      <groupName>HMAC</groupName>
+      <baseAddress>0x6003E000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SET_START</name>
+          <description>Process control register 0.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>Start hmac operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_PURPOSE</name>
+          <description>Configure purpose.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PURPOSE_SET</name>
+              <description>Set hmac parameter purpose.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_KEY</name>
+          <description>Configure key.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_SET</name>
+              <description>Set hmac parameter key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_FINISH</name>
+          <description>Finish initial configuration.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_PARA_END</name>
+              <description>Finish hmac configuration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ONE</name>
+          <description>Process control register 1.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ONE</name>
+              <description>Call SHA to calculate one message block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ING</name>
+          <description>Process control register 2.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ING</name>
+              <description>Continue typical hmac.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_END</name>
+          <description>Process control register 3.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_END</name>
+              <description>Start hardware padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_RESULT_FINISH</name>
+          <description>Process control register 4.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_RESULT_END</name>
+              <description>After read result from upstream, then let hmac back to idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_JTAG</name>
+          <description>Invalidate register 0.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_JTAG</name>
+              <description>Clear result from hmac downstream JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_DS</name>
+          <description>Invalidate register 1.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_DS</name>
+              <description>Clear result from hmac downstream DS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_ERROR</name>
+          <description>Error register.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUREY_CHECK</name>
+              <description>Hmac configuration state. 0: key are agree with purpose. 1: error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>Busy register.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUSY_STATE</name>
+              <description>Hmac state. 1'b0: idle. 1'b1: busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>WR_MESSAGE_MEM[%s]</name>
+          <description>Message block memory.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>RD_RESULT_MEM[%s]</name>
+          <description>Result from upstream.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>SET_MESSAGE_PAD</name>
+          <description>Process control register 5.</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_PAD</name>
+              <description>Start software padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ONE_BLOCK</name>
+          <description>Process control register 6.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_ONE_BLOCK</name>
+              <description>Don't have to do padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SOFT_JTAG_CTRL</name>
+          <description>Jtag register 0.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SOFT_JTAG_CTRL</name>
+              <description>Turn on JTAG verification.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_JTAG</name>
+          <description>Jtag register 1.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_JTAG</name>
+              <description>32-bit of key to be compared.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2C0</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x60013000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x90</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C_EXT0</name>
+        <value>29</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SCL_LOW_PERIOD</name>
+          <description>I2C_SCL_LOW_PERIOD_REG</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_LOW_PERIOD</name>
+              <description>reg_scl_low_period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTR</name>
+          <description>I2C_CTR_REG</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000020B</resetValue>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>reg_sda_force_out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>reg_scl_force_out</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAMPLE_SCL_LEVEL</name>
+              <description>reg_sample_scl_level</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FULL_ACK_LEVEL</name>
+              <description>reg_rx_full_ack_level</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>reg_ms_mode</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>reg_trans_start</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>reg_tx_lsb_first</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>reg_rx_lsb_first</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_EN</name>
+              <description>reg_arbitration_en</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FSM_RST</name>
+              <description>reg_fsm_rst</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPGATE</name>
+              <description>reg_conf_upgate</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_TX_AUTO_START_EN</name>
+              <description>reg_slv_tx_auto_start_en</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_RW_CHECK_EN</name>
+              <description>reg_addr_10bit_rw_check_en</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_BROADCASTING_EN</name>
+              <description>reg_addr_broadcasting_en</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <description>I2C_SR_REG</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C000</resetValue>
+          <fields>
+            <field>
+              <name>RESP_REC</name>
+              <description>reg_resp_rec</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW</name>
+              <description>reg_slave_rw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>reg_arb_lost</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>reg_bus_busy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDRESSED</name>
+              <description>reg_slave_addressed</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>reg_rxfifo_cnt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STRETCH_CAUSE</name>
+              <description>reg_stretch_cause</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>reg_txfifo_cnt</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_STATE_LAST</name>
+              <description>reg_scl_main_state_last</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_STATE_LAST</name>
+              <description>reg_scl_state_last</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TO</name>
+          <description>I2C_TO_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TIME_OUT_VALUE</name>
+              <description>reg_time_out_value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_EN</name>
+              <description>reg_time_out_en</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_ADDR</name>
+          <description>I2C_SLAVE_ADDR_REG</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_ADDR</name>
+              <description>reg_slave_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_EN</name>
+              <description>reg_addr_10bit_en</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_ST</name>
+          <description>I2C_FIFO_ST_REG</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RADDR</name>
+              <description>reg_rxfifo_raddr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_WADDR</name>
+              <description>reg_rxfifo_waddr</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_RADDR</name>
+              <description>reg_txfifo_raddr</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WADDR</name>
+              <description>reg_txfifo_waddr</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW_POINT</name>
+              <description>reg_slave_rw_point</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_CONF</name>
+          <description>I2C_FIFO_CONF_REG</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000408B</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_THRHD</name>
+              <description>reg_rxfifo_wm_thrhd</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_THRHD</name>
+              <description>reg_txfifo_wm_thrhd</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_EN</name>
+              <description>reg_nonfifo_en</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_ADDR_CFG_EN</name>
+              <description>reg_fifo_addr_cfg_en</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RST</name>
+              <description>reg_rx_fifo_rst</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RST</name>
+              <description>reg_tx_fifo_rst</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_PRT_EN</name>
+              <description>reg_fifo_prt_en</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>I2C_FIFO_DATA_REG</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_RDATA</name>
+              <description>reg_fifo_rdata</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>I2C_INT_RAW_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_RAW</name>
+              <description>reg_rxfifo_wm_int_raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_RAW</name>
+              <description>reg_txfifo_wm_int_raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>reg_rxfifo_ovf_int_raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_RAW</name>
+              <description>reg_end_detect_int_raw</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_RAW</name>
+              <description>reg_byte_trans_done_int_raw</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>reg_arbitration_lost_int_raw</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_RAW</name>
+              <description>reg_mst_txfifo_udf_int_raw</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>reg_trans_complete_int_raw</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>reg_time_out_int_raw</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_RAW</name>
+              <description>reg_trans_start_int_raw</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_RAW</name>
+              <description>reg_nack_int_raw</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_RAW</name>
+              <description>reg_txfifo_ovf_int_raw</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_RAW</name>
+              <description>reg_rxfifo_udf_int_raw</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_RAW</name>
+              <description>reg_scl_st_to_int_raw</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_RAW</name>
+              <description>reg_scl_main_st_to_int_raw</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_RAW</name>
+              <description>reg_det_start_int_raw</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_RAW</name>
+              <description>reg_slave_stretch_int_raw</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_RAW</name>
+              <description>reg_general_call_int_raw</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>I2C_INT_CLR_REG</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_CLR</name>
+              <description>reg_rxfifo_wm_int_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_CLR</name>
+              <description>reg_txfifo_wm_int_clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>reg_rxfifo_ovf_int_clr</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_CLR</name>
+              <description>reg_end_detect_int_clr</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_CLR</name>
+              <description>reg_byte_trans_done_int_clr</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <description>reg_arbitration_lost_int_clr</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_CLR</name>
+              <description>reg_mst_txfifo_udf_int_clr</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <description>reg_trans_complete_int_clr</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <description>reg_time_out_int_clr</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_CLR</name>
+              <description>reg_trans_start_int_clr</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_CLR</name>
+              <description>reg_nack_int_clr</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_CLR</name>
+              <description>reg_txfifo_ovf_int_clr</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_CLR</name>
+              <description>reg_rxfifo_udf_int_clr</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_CLR</name>
+              <description>reg_scl_st_to_int_clr</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_CLR</name>
+              <description>reg_scl_main_st_to_int_clr</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_CLR</name>
+              <description>reg_det_start_int_clr</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_CLR</name>
+              <description>reg_slave_stretch_int_clr</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_CLR</name>
+              <description>reg_general_call_int_clr</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>I2C_INT_ENA_REG</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ENA</name>
+              <description>reg_rxfifo_wm_int_ena</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ENA</name>
+              <description>reg_txfifo_wm_int_ena</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>reg_rxfifo_ovf_int_ena</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ENA</name>
+              <description>reg_end_detect_int_ena</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ENA</name>
+              <description>reg_byte_trans_done_int_ena</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>reg_arbitration_lost_int_ena</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ENA</name>
+              <description>reg_mst_txfifo_udf_int_ena</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ENA</name>
+              <description>reg_trans_complete_int_ena</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ENA</name>
+              <description>reg_time_out_int_ena</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ENA</name>
+              <description>reg_trans_start_int_ena</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NACK_INT_ENA</name>
+              <description>reg_nack_int_ena</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ENA</name>
+              <description>reg_txfifo_ovf_int_ena</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ENA</name>
+              <description>reg_rxfifo_udf_int_ena</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ENA</name>
+              <description>reg_scl_st_to_int_ena</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ENA</name>
+              <description>reg_scl_main_st_to_int_ena</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ENA</name>
+              <description>reg_det_start_int_ena</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ENA</name>
+              <description>reg_slave_stretch_int_ena</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_ENA</name>
+              <description>reg_general_call_int_ena</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS</name>
+          <description>I2C_INT_STATUS_REG</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ST</name>
+              <description>reg_rxfifo_wm_int_st</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ST</name>
+              <description>reg_txfifo_wm_int_st</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>reg_rxfifo_ovf_int_st</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ST</name>
+              <description>reg_end_detect_int_st</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ST</name>
+              <description>reg_byte_trans_done_int_st</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>reg_arbitration_lost_int_st</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ST</name>
+              <description>reg_mst_txfifo_udf_int_st</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ST</name>
+              <description>reg_trans_complete_int_st</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ST</name>
+              <description>reg_time_out_int_st</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ST</name>
+              <description>reg_trans_start_int_st</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_ST</name>
+              <description>reg_nack_int_st</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ST</name>
+              <description>reg_txfifo_ovf_int_st</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ST</name>
+              <description>reg_rxfifo_udf_int_st</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ST</name>
+              <description>reg_scl_st_to_int_st</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ST</name>
+              <description>reg_scl_main_st_to_int_st</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ST</name>
+              <description>reg_det_start_int_st</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ST</name>
+              <description>reg_slave_stretch_int_st</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_ST</name>
+              <description>reg_general_call_int_st</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_HOLD</name>
+          <description>I2C_SDA_HOLD_REG</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>reg_sda_hold_time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_SAMPLE</name>
+          <description>I2C_SDA_SAMPLE_REG</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>reg_sda_sample_time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH_PERIOD</name>
+          <description>I2C_SCL_HIGH_PERIOD_REG</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_HIGH_PERIOD</name>
+              <description>reg_scl_high_period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_WAIT_HIGH_PERIOD</name>
+              <description>reg_scl_wait_high_period</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_HOLD</name>
+          <description>I2C_SCL_START_HOLD_REG</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>reg_scl_start_hold_time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_RSTART_SETUP</name>
+          <description>I2C_SCL_RSTART_SETUP_REG</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>reg_scl_rstart_setup_time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_HOLD</name>
+          <description>I2C_SCL_STOP_HOLD_REG</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>reg_scl_stop_hold_time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_SETUP</name>
+          <description>I2C_SCL_STOP_SETUP_REG</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>reg_scl_stop_setup_time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CFG</name>
+          <description>I2C_FILTER_CFG_REG</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000300</resetValue>
+          <fields>
+            <field>
+              <name>SCL_FILTER_THRES</name>
+              <description>reg_scl_filter_thres</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_THRES</name>
+              <description>reg_sda_filter_thres</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FILTER_EN</name>
+              <description>reg_scl_filter_en</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_EN</name>
+              <description>reg_sda_filter_en</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>I2C_CLK_CONF_REG</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00200000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>reg_sclk_div_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>reg_sclk_div_a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>reg_sclk_div_b</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>reg_sclk_sel</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_ACTIVE</name>
+              <description>reg_sclk_active</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>COMD%s</name>
+          <description>I2C_COMD%s_REG</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND</name>
+              <description>reg_command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND_DONE</name>
+              <description>reg_command_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_ST_TIME_OUT</name>
+          <description>I2C_SCL_ST_TIME_OUT_REG</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_ST_TO_I2C</name>
+              <description>reg_scl_st_to_regno more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_MAIN_ST_TIME_OUT</name>
+          <description>I2C_SCL_MAIN_ST_TIME_OUT_REG</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_MAIN_ST_TO_I2C</name>
+              <description>reg_scl_main_st_to_regno more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_SP_CONF</name>
+          <description>I2C_SCL_SP_CONF_REG</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_RST_SLV_EN</name>
+              <description>reg_scl_rst_slv_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_RST_SLV_NUM</name>
+              <description>reg_scl_rst_slv_num</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_PD_EN</name>
+              <description>reg_scl_pd_en</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_PD_EN</name>
+              <description>reg_sda_pd_en</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STRETCH_CONF</name>
+          <description>I2C_SCL_STRETCH_CONF_REG</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRETCH_PROTECT_NUM</name>
+              <description>reg_stretch_protect_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_EN</name>
+              <description>reg_slave_scl_stretch_en</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_CLR</name>
+              <description>reg_slave_scl_stretch_clr</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_BYTE_ACK_CTL_EN</name>
+              <description>reg_slave_byte_ack_ctl_en</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_BYTE_ACK_LVL</name>
+              <description>reg_slave_byte_ack_lvl</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>I2C_DATE_REG</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20070201</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXFIFO_START_ADDR</name>
+          <description>I2C_TXFIFO_START_ADDR_REG</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TXFIFO_START_ADDR</name>
+              <description>reg_txfifo_start_addr.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXFIFO_START_ADDR</name>
+          <description>I2C_RXFIFO_START_ADDR_REG</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_START_ADDR</name>
+              <description>reg_rxfifo_start_addr.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <description>I2S (Inter-IC Sound) Controller</description>
+      <groupName>I2S</groupName>
+      <baseAddress>0x6002D000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x5C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S</name>
+        <value>20</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INT_RAW</name>
+          <description>I2S interrupt raw register, valid in level.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>I2S interrupt status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>I2S interrupt enable register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>I2S interrupt clear register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CONF</name>
+          <description>I2S RX configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00009600</resetValue>
+          <fields>
+            <field>
+              <name>RX_RESET</name>
+              <description>Set this bit to reset receiver</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RESET</name>
+              <description>Set this bit to reset Rx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_START</name>
+              <description>Set this bit to start receiving data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave receiver mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO</name>
+              <description>Set this bit to enable receiver  in mono mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIG_ENDIAN</name>
+              <description>I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_UPDATE</name>
+              <description>Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_CONF</name>
+              <description>I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_BYPASS</name>
+              <description>Set this bit to bypass Compress/Decompress module for received data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_STOP_MODE</name>
+              <description>0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LEFT_ALIGN</name>
+              <description>1: I2S RX left alignment mode. 0: I2S RX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_24_FILL_EN</name>
+              <description>1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIT_ORDER</name>
+              <description>I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_EN</name>
+              <description>1: Enable I2S TDM Rx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PDM_EN</name>
+              <description>1: Enable I2S PDM Rx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CONF</name>
+          <description>I2S TX configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000B200</resetValue>
+          <fields>
+            <field>
+              <name>TX_RESET</name>
+              <description>Set this bit to reset transmitter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RESET</name>
+              <description>Set this bit to reset Tx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START</name>
+              <description>Set this bit to start transmitting data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave transmitter mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO</name>
+              <description>Set this bit to enable transmitter in mono mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHAN_EQUAL</name>
+              <description>1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIG_ENDIAN</name>
+              <description>I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_UPDATE</name>
+              <description>Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_CONF</name>
+              <description>I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_BYPASS</name>
+              <description>Set this bit to bypass  Compress/Decompress module for transmitted data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP_EN</name>
+              <description>Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LEFT_ALIGN</name>
+              <description>1: I2S TX left alignment mode. 0: I2S TX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_24_FILL_EN</name>
+              <description>1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIT_ORDER</name>
+              <description>I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_EN</name>
+              <description>1: Enable I2S TDM Tx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_EN</name>
+              <description>1: Enable I2S PDM Tx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHAN_MOD</name>
+              <description>I2S transmitter channel mode configuration bits.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_LOOPBACK</name>
+              <description>Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CONF1</name>
+          <description>I2S RX configure register 1</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x2F3DE300</resetValue>
+          <fields>
+            <field>
+              <name>RX_TDM_WS_WIDTH</name>
+              <description>The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in receiver mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HALF_SAMPLE_BITS</name>
+              <description>I2S Rx half sample bits -1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN_BITS</name>
+              <description>The Rx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MSB_SHIFT</name>
+              <description>Set this bit to enable receiver in Phillips standard mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CONF1</name>
+          <description>I2S TX configure register 1</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x6F3DE300</resetValue>
+          <fields>
+            <field>
+              <name>TX_TDM_WS_WIDTH</name>
+              <description>The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in transmitter mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HALF_SAMPLE_BITS</name>
+              <description>I2S Tx half sample bits -1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN_BITS</name>
+              <description>The Tx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MSB_SHIFT</name>
+              <description>Set this bit to enable transmitter in Phillips standard mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_NO_DLY</name>
+              <description>1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CLKM_CONF</name>
+          <description>I2S RX clock configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RX_CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLK_ACTIVE</name>
+              <description>I2S Rx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLK_SEL</name>
+              <description>Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCLK_SEL</name>
+              <description>0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CLKM_CONF</name>
+          <description>I2S TX clock configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>TX_CLKM_DIV_NUM</name>
+              <description>Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b &lt;= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLK_ACTIVE</name>
+              <description>I2S Tx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLK_SEL</name>
+              <description>Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CLKM_DIV_CONF</name>
+          <description>I2S RX module clock divider configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>RX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CLKM_DIV_CONF</name>
+          <description>I2S TX module clock divider configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>TX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_PCM2PDM_CONF</name>
+          <description>I2S TX PCM2PDM configuration register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x004AA004</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_HP_BYPASS</name>
+              <description>I2S TX PDM bypass hp filter or not. The option has been removed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_OSR2</name>
+              <description>I2S TX PDM OSR2 value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_PRESCALE</name>
+              <description>I2S TX PDM prescale for sigmadelta</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_HP_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_LP_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_DITHER2</name>
+              <description>I2S TX PDM sigmadelta dither2 value</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_DITHER</name>
+              <description>I2S TX PDM sigmadelta dither value</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_DAC_2OUT_EN</name>
+              <description>I2S TX PDM dac mode enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_DAC_MODE_EN</name>
+              <description>I2S TX PDM dac 2channel enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCM2PDM_CONV_EN</name>
+              <description>I2S TX PDM Converter enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_PCM2PDM_CONF1</name>
+          <description>I2S TX PCM2PDM configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03F783C0</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_FP</name>
+              <description>I2S TX PDM Fp</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_FS</name>
+              <description>I2S TX PDM Fs</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IIR_HP_MULT12_5</name>
+              <description>The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IIR_HP_MULT12_0</name>
+              <description>The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>RX_TDM_PDM_CHAN0_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN1_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN2_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN3_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN4_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN5_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN6_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN7_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>TX_TDM_CHAN0_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN1_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN2_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN3_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN4_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN5_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN6_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN7_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_SKIP_MSK_EN</name>
+              <description>When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_TIMING</name>
+          <description>I2S RX timing control register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_SD_IN_DM</name>
+              <description>The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_OUT_DM</name>
+              <description>The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IN_DM</name>
+              <description>The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_IN_DM</name>
+              <description>The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_TIMING</name>
+          <description>I2S TX timing control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_SD_OUT_DM</name>
+              <description>The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SD1_OUT_DM</name>
+              <description>The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_OUT_DM</name>
+              <description>The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IN_DM</name>
+              <description>The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_IN_DM</name>
+              <description>The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_HUNG_CONF</name>
+          <description>I2S HUNG configure register.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000810</resetValue>
+          <fields>
+            <field>
+              <name>LC_FIFO_TIMEOUT</name>
+              <description>the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_SHIFT</name>
+              <description>The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_ENA</name>
+              <description>The enable bit for FIFO timeout</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXEOF_NUM</name>
+          <description>I2S RX data number control register.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000040</resetValue>
+          <fields>
+            <field>
+              <name>RX_EOF_NUM</name>
+              <description>The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_SIGLE_DATA</name>
+          <description>I2S signal data register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_DATA</name>
+              <description>The configured constant channel data to be sent out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>I2S TX status register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TX_IDLE</name>
+              <description>1: i2s_tx is idle state. 0: i2s_tx is working.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007220</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>I2S version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>INTERRUPT_CORE0</name>
+      <description>Interrupt Core</description>
+      <groupName>INTERRUPT_CORE0</groupName>
+      <baseAddress>0x600C2000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x19C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WIFI_MAC</name>
+        <value>0</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_MAC_NMI</name>
+        <value>1</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_PWR</name>
+        <value>2</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_BB</name>
+        <value>3</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_MAC</name>
+        <value>4</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_BB</name>
+        <value>5</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_BB_NMI</name>
+        <value>6</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBT</name>
+        <value>7</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBLE</name>
+        <value>8</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBT_NMI</name>
+        <value>9</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBLE_NMI</name>
+        <value>10</value>
+      </interrupt>
+      <interrupt>
+        <name>SW_INTR_0</name>
+        <value>50</value>
+      </interrupt>
+      <interrupt>
+        <name>SW_INTR_1</name>
+        <value>51</value>
+      </interrupt>
+      <interrupt>
+        <name>SW_INTR_2</name>
+        <value>52</value>
+      </interrupt>
+      <interrupt>
+        <name>SW_INTR_3</name>
+        <value>53</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MAC_INTR_MAP</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_INTR_MAP</name>
+              <description>core0_mac_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAC_NMI_MAP</name>
+          <description>mac nmi_intr map register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_NMI_MAP</name>
+              <description>reg_core0_mac_nmi_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWR_INTR_MAP</name>
+          <description>pwr intr map register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PWR_INTR_MAP</name>
+              <description>reg_core0_pwr_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BB_INT_MAP</name>
+          <description>bb intr map register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BB_INT_MAP</name>
+              <description>reg_core0_bb_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_MAC_INT_MAP</name>
+          <description>bt intr map register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_MAC_INT_MAP</name>
+              <description>reg_core0_bt_mac_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_INT_MAP</name>
+          <description>bb_bt intr map register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_BB_INT_MAP</name>
+              <description>reg_core0_bt_bb_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_NMI_MAP</name>
+          <description>bb_bt_nmi intr map register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_BB_NMI_MAP</name>
+              <description>reg_core0_bt_bb_nmi_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBT_IRQ_MAP</name>
+          <description>rwbt intr map register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RWBT_IRQ_MAP</name>
+              <description>reg_core0_rwbt_irq_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBLE_IRQ_MAP</name>
+          <description>rwble intr map register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RWBLE_IRQ_MAP</name>
+              <description>reg_core0_rwble_irq_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBT_NMI_MAP</name>
+          <description>rwbt_nmi intr map register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RWBT_NMI_MAP</name>
+              <description>reg_core0_rwbt_nmi_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBLE_NMI_MAP</name>
+          <description>rwble_nmi intr map register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RWBLE_NMI_MAP</name>
+              <description>reg_core0_rwble_nmi_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_MST_INT_MAP</name>
+          <description>i2c intr map register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_MST_INT_MAP</name>
+              <description>reg_core0_i2c_mst_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0_INTR_MAP</name>
+          <description>slc0 intr map register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_INTR_MAP</name>
+              <description>reg_core0_slc0_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1_INTR_MAP</name>
+          <description>slc1 intr map register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_INTR_MAP</name>
+              <description>reg_core0_slc1_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_CTRL_INTR_MAP</name>
+          <description>apb_ctrl intr map register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_CTRL_INTR_MAP</name>
+              <description>reg_core0_apb_ctrl_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UHCI0_INTR_MAP</name>
+          <description>uchi0 intr map register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UHCI0_INTR_MAP</name>
+              <description>reg_core0_uhci0_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_MAP</name>
+          <description>gpio intr map register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_MAP</name>
+              <description>reg_core0_gpio_interrupt_pro_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+          <description>gpio_pro intr map register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+              <description>reg_core0_gpio_interrupt_pro_nmi_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_1_MAP</name>
+          <description>gpio_pro_nmi intr map register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_INTR_1_MAP</name>
+              <description>reg_core0_spi_intr_1_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_2_MAP</name>
+          <description>spi1 intr map register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_INTR_2_MAP</name>
+              <description>reg_core0_spi_intr_2_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S1_INT_MAP</name>
+          <description>spi2 intr map register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S1_INT_MAP</name>
+              <description>reg_core0_i2s1_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INTR_MAP</name>
+          <description>i2s1 intr map register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UART_INTR_MAP</name>
+              <description>reg_core0_uart_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART1_INTR_MAP</name>
+          <description>uart1 intr map register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UART1_INTR_MAP</name>
+              <description>reg_core0_uart1_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LEDC_INT_MAP</name>
+          <description>ledc intr map register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LEDC_INT_MAP</name>
+              <description>reg_core0_ledc_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EFUSE_INT_MAP</name>
+          <description>efuse intr map register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EFUSE_INT_MAP</name>
+              <description>reg_core0_efuse_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAN_INT_MAP</name>
+          <description>can intr map register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAN_INT_MAP</name>
+              <description>reg_core0_can_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_INTR_MAP</name>
+          <description>usb intr map register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_INTR_MAP</name>
+              <description>reg_core0_usb_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_CORE_INTR_MAP</name>
+          <description>rtc intr map register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_CORE_INTR_MAP</name>
+              <description>reg_core0_rtc_core_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RMT_INTR_MAP</name>
+          <description>rmt intr map register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RMT_INTR_MAP</name>
+              <description>reg_core0_rmt_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_EXT0_INTR_MAP</name>
+          <description>i2c intr map register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_EXT0_INTR_MAP</name>
+              <description>reg_core0_i2c_ext0_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_INT1_MAP</name>
+          <description>timer1 intr map register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_INT1_MAP</name>
+              <description>reg_core0_timer_int1_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_INT2_MAP</name>
+          <description>timer2 intr map register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_INT2_MAP</name>
+              <description>reg_core0_timer_int2_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_T0_INT_MAP</name>
+          <description>tg to intr map register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG_T0_INT_MAP</name>
+              <description>reg_core0_tg_t0_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_WDT_INT_MAP</name>
+          <description>tg wdt intr map register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG_WDT_INT_MAP</name>
+              <description>reg_core0_tg_wdt_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_T0_INT_MAP</name>
+          <description>tg1 to intr map register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG1_T0_INT_MAP</name>
+              <description>reg_core0_tg1_t0_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_WDT_INT_MAP</name>
+          <description>tg1 wdt intr map register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG1_WDT_INT_MAP</name>
+              <description>reg_core0_tg1_wdt_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_IA_INT_MAP</name>
+          <description>cache ia intr map register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_IA_INT_MAP</name>
+              <description>reg_core0_cache_ia_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET0_INT_MAP</name>
+          <description>systimer intr map register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET0_INT_MAP</name>
+              <description>reg_core0_systimer_target0_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET1_INT_MAP</name>
+          <description>systimer target1 intr map register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET1_INT_MAP</name>
+              <description>reg_core0_systimer_target1_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET2_INT_MAP</name>
+          <description>systimer target2 intr map register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET2_INT_MAP</name>
+              <description>reg_core0_systimer_target2_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REJECT_INTR_MAP</name>
+          <description>spi mem reject intr map register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_INTR_MAP</name>
+              <description>reg_core0_spi_mem_reject_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_INT_MAP</name>
+          <description>icache perload intr map register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_INT_MAP</name>
+              <description>reg_core0_icache_preload_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_INT_MAP</name>
+          <description>icache sync intr map register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_INT_MAP</name>
+              <description>reg_core0_icache_sync_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADC_INT_MAP</name>
+          <description>adc intr map register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_ADC_INT_MAP</name>
+              <description>reg_core0_apb_adc_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CH0_INT_MAP</name>
+          <description>dma ch0 intr map register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CH0_INT_MAP</name>
+              <description>reg_core0_dma_ch0_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CH1_INT_MAP</name>
+          <description>dma ch1 intr map register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CH1_INT_MAP</name>
+              <description>reg_core0_dma_ch1_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CH2_INT_MAP</name>
+          <description>dma ch2 intr map register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CH2_INT_MAP</name>
+              <description>reg_core0_dma_ch2_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_INT_MAP</name>
+          <description>rsa intr map register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RSA_INT_MAP</name>
+              <description>reg_core0_rsa_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AES_INT_MAP</name>
+          <description>aes intr map register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AES_INT_MAP</name>
+              <description>reg_core0_aes_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA_INT_MAP</name>
+          <description>sha intr map register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA_INT_MAP</name>
+              <description>reg_core0_sha_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0_MAP</name>
+          <description>cpu from cpu 0 intr map register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0_MAP</name>
+              <description>reg_core0_cpu_intr_from_cpu_0_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1_MAP</name>
+          <description>cpu from cpu 0 intr map register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1_MAP</name>
+              <description>reg_core0_cpu_intr_from_cpu_1_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2_MAP</name>
+          <description>cpu from cpu 1 intr map register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2_MAP</name>
+              <description>reg_core0_cpu_intr_from_cpu_2_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3_MAP</name>
+          <description>cpu from cpu 3 intr map register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3_MAP</name>
+              <description>reg_core0_cpu_intr_from_cpu_3_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ASSIST_DEBUG_INTR_MAP</name>
+          <description>assist debug intr map register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ASSIST_DEBUG_INTR_MAP</name>
+              <description>reg_core0_assist_debug_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>dma pms violatile intr map register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>reg_core0_dma_apbperi_pms_monitor_violate_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>iram0 pms violatile intr map register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>reg_core0_core_0_iram0_pms_monitor_violate_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>mac intr map register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>reg_core0_core_0_dram0_pms_monitor_violate_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>mac intr map register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>reg_core0_core_0_pif_pms_monitor_violate_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+          <description>mac intr map register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+              <description>reg_core0_core_0_pif_pms_monitor_violate_size_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_PMS_VIOLATE_INTR_MAP</name>
+          <description>mac intr map register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_PMS_VIOLATE_INTR_MAP</name>
+              <description>reg_core0_backup_pms_violate_intr_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CORE0_ACS_INT_MAP</name>
+          <description>mac intr map register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_CORE0_ACS_INT_MAP</name>
+              <description>reg_core0_cache_core0_acs_int_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_STATUS_REG_0</name>
+          <description>mac intr map register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_0</name>
+              <description>reg_core0_intr_status_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_STATUS_REG_1</name>
+          <description>mac intr map register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_1</name>
+              <description>reg_core0_intr_status_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>REG_CLK_EN</name>
+              <description>reg_core0_reg_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_ENABLE</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_ENABLE</name>
+              <description>reg_core0_cpu_int_enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_TYPE</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_TYPE</name>
+              <description>reg_core0_cpu_int_type</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_CLEAR</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_CLEAR</name>
+              <description>reg_core0_cpu_int_clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_EIP_STATUS</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_EIP_STATUS</name>
+              <description>reg_core0_cpu_int_eip_status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_0</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_0_MAP</name>
+              <description>reg_core0_cpu_pri_0_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_1</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_1_MAP</name>
+              <description>reg_core0_cpu_pri_1_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_2</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_2_MAP</name>
+              <description>reg_core0_cpu_pri_2_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_3</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_3_MAP</name>
+              <description>reg_core0_cpu_pri_3_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_4</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_4_MAP</name>
+              <description>reg_core0_cpu_pri_4_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_5</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_5_MAP</name>
+              <description>reg_core0_cpu_pri_5_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_6</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_6_MAP</name>
+              <description>reg_core0_cpu_pri_6_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_7</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_7_MAP</name>
+              <description>reg_core0_cpu_pri_7_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_8</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_8_MAP</name>
+              <description>reg_core0_cpu_pri_8_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_9</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_9_MAP</name>
+              <description>reg_core0_cpu_pri_9_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_10</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_10_MAP</name>
+              <description>reg_core0_cpu_pri_10_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_11</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_11_MAP</name>
+              <description>reg_core0_cpu_pri_11_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_12</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_12_MAP</name>
+              <description>reg_core0_cpu_pri_12_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_13</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_13_MAP</name>
+              <description>reg_core0_cpu_pri_13_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_14</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_14_MAP</name>
+              <description>reg_core0_cpu_pri_14_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_15</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_15_MAP</name>
+              <description>reg_core0_cpu_pri_15_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_16</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_16_MAP</name>
+              <description>reg_core0_cpu_pri_16_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_17</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_17_MAP</name>
+              <description>reg_core0_cpu_pri_17_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_18</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_18_MAP</name>
+              <description>reg_core0_cpu_pri_18_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_19</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_19_MAP</name>
+              <description>reg_core0_cpu_pri_19_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_20</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_20_MAP</name>
+              <description>reg_core0_cpu_pri_20_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_21</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_21_MAP</name>
+              <description>reg_core0_cpu_pri_21_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_22</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_22_MAP</name>
+              <description>reg_core0_cpu_pri_22_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_23</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_23_MAP</name>
+              <description>reg_core0_cpu_pri_23_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_24</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_24_MAP</name>
+              <description>reg_core0_cpu_pri_24_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_25</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_25_MAP</name>
+              <description>reg_core0_cpu_pri_25_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_26</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_26_MAP</name>
+              <description>reg_core0_cpu_pri_26_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_27</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_27_MAP</name>
+              <description>reg_core0_cpu_pri_27_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_28</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_28_MAP</name>
+              <description>reg_core0_cpu_pri_28_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_29</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_29_MAP</name>
+              <description>reg_core0_cpu_pri_29_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_30</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_30_MAP</name>
+              <description>reg_core0_cpu_pri_30_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_PRI_31</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PRI_31_MAP</name>
+              <description>reg_core0_cpu_pri_31_map</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INT_THRESH</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INT_THRESH</name>
+              <description>reg_core0_cpu_int_thresh</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT_REG_DATE</name>
+          <description>mac intr map register</description>
+          <addressOffset>0x7FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007210</resetValue>
+          <fields>
+            <field>
+              <name>INTERRUPT_REG_DATE</name>
+              <description>reg_core0_interrupt_reg_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>IO_MUX</name>
+      <description>Input/Output Multiplexer</description>
+      <groupName>IO_MUX</groupName>
+      <baseAddress>0x60009000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x60</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PIN_CTRL</name>
+          <description>Clock Output Configuration Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>CLK_OUT1</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT2</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT3</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>22</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>GPIO%s</name>
+          <description>IO MUX Configure Register for pad XTAL_32K_P</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>IO MUX Version Control Register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02006050</resetValue>
+          <fields>
+            <field>
+              <name>REG_DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LEDC</name>
+      <description>LED Control PWM (Pulse Width Modulation)</description>
+      <groupName>LEDC</groupName>
+      <baseAddress>0x60019000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LEDC</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-5</dimIndex>
+          <name>CH%s_CONF0</name>
+          <description>LEDC_LSCH%s_CONF%s.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SEL</name>
+              <description>reg_timer_sel_lsch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_OUT_EN</name>
+              <description>reg_sig_out_en_lsch0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_LV</name>
+              <description>reg_idle_lv_lsch0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>reg_para_up_lsch0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_NUM</name>
+              <description>reg_ovf_num_lsch0.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_EN</name>
+              <description>reg_ovf_cnt_en_lsch0.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_RESET</name>
+              <description>reg_ovf_cnt_reset_lsch0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-5</dimIndex>
+          <name>CH%s_HPOINT</name>
+          <description>LEDC_LSCH%s_HPOINT.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HPOINT</name>
+              <description>reg_hpoint_lsch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-5</dimIndex>
+          <name>CH%s_DUTY</name>
+          <description>LEDC_LSCH%s_DUTY.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY</name>
+              <description>reg_duty_lsch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-5</dimIndex>
+          <name>CH%s_CONF1</name>
+          <description>LEDC_LSCH%s_CONF1.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_SCALE</name>
+              <description>reg_duty_scale_lsch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CYCLE</name>
+              <description>reg_duty_cycle_lsch0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_NUM</name>
+              <description>reg_duty_num_lsch0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_INC</name>
+              <description>reg_duty_inc_lsch0.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_START</name>
+              <description>reg_duty_start_lsch0.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <dimIndex>0-5</dimIndex>
+          <name>CH%s_DUTY_R</name>
+          <description>LEDC_LSCH%s_DUTY_R.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_R</name>
+              <description>reg_duty_lsch0_r.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0-3</dimIndex>
+          <name>TIMER%s_CONF</name>
+          <description>LEDC_LSTIMER%s_CONF.</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_RES</name>
+              <description>reg_lstimer0_duty_res.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DIV</name>
+              <description>reg_clk_div_lstimer0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAUSE</name>
+              <description>reg_lstimer0_pause.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>reg_lstimer0_rst.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_SEL</name>
+              <description>reg_tick_sel_lstimer0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>reg_lstimer0_para_up.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>0-3</dimIndex>
+          <name>TIMER%s_VALUE</name>
+          <description>LEDC_LSTIMER%s_VALUE.</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>reg_lstimer0_cnt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>LEDC_INT_RAW.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LSTIMER0_OVF_INT_RAW</name>
+              <description>reg_lstimer0_ovf_int_raw.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER1_OVF_INT_RAW</name>
+              <description>reg_lstimer1_ovf_int_raw.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER2_OVF_INT_RAW</name>
+              <description>reg_lstimer2_ovf_int_raw.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER3_OVF_INT_RAW</name>
+              <description>reg_lstimer3_ovf_int_raw.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH0_INT_RAW</name>
+              <description>reg_duty_chng_end_lsch0_int_raw.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH1_INT_RAW</name>
+              <description>reg_duty_chng_end_lsch1_int_raw.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH2_INT_RAW</name>
+              <description>reg_duty_chng_end_lsch2_int_raw.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH3_INT_RAW</name>
+              <description>reg_duty_chng_end_lsch3_int_raw.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH4_INT_RAW</name>
+              <description>reg_duty_chng_end_lsch4_int_raw.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH5_INT_RAW</name>
+              <description>reg_duty_chng_end_lsch5_int_raw.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH0_INT_RAW</name>
+              <description>reg_ovf_cnt_lsch0_int_raw.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH1_INT_RAW</name>
+              <description>reg_ovf_cnt_lsch1_int_raw.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH2_INT_RAW</name>
+              <description>reg_ovf_cnt_lsch2_int_raw.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH3_INT_RAW</name>
+              <description>reg_ovf_cnt_lsch3_int_raw.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH4_INT_RAW</name>
+              <description>reg_ovf_cnt_lsch4_int_raw.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH5_INT_RAW</name>
+              <description>reg_ovf_cnt_lsch5_int_raw.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>LEDC_INT_ST.</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LSTIMER0_OVF_INT_ST</name>
+              <description>reg_lstimer0_ovf_int_st.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER1_OVF_INT_ST</name>
+              <description>reg_lstimer1_ovf_int_st.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER2_OVF_INT_ST</name>
+              <description>reg_lstimer2_ovf_int_st.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LSTIMER3_OVF_INT_ST</name>
+              <description>reg_lstimer3_ovf_int_st.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH0_INT_ST</name>
+              <description>reg_duty_chng_end_lsch0_int_st.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH1_INT_ST</name>
+              <description>reg_duty_chng_end_lsch1_int_st.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH2_INT_ST</name>
+              <description>reg_duty_chng_end_lsch2_int_st.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH3_INT_ST</name>
+              <description>reg_duty_chng_end_lsch3_int_st.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH4_INT_ST</name>
+              <description>reg_duty_chng_end_lsch4_int_st.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH5_INT_ST</name>
+              <description>reg_duty_chng_end_lsch5_int_st.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH0_INT_ST</name>
+              <description>reg_ovf_cnt_lsch0_int_st.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH1_INT_ST</name>
+              <description>reg_ovf_cnt_lsch1_int_st.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH2_INT_ST</name>
+              <description>reg_ovf_cnt_lsch2_int_st.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH3_INT_ST</name>
+              <description>reg_ovf_cnt_lsch3_int_st.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH4_INT_ST</name>
+              <description>reg_ovf_cnt_lsch4_int_st.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH5_INT_ST</name>
+              <description>reg_ovf_cnt_lsch5_int_st.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>LEDC_INT_ENA.</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LSTIMER0_OVF_INT_ENA</name>
+              <description>reg_lstimer0_ovf_int_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSTIMER1_OVF_INT_ENA</name>
+              <description>reg_lstimer1_ovf_int_ena.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSTIMER2_OVF_INT_ENA</name>
+              <description>reg_lstimer2_ovf_int_ena.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSTIMER3_OVF_INT_ENA</name>
+              <description>reg_lstimer3_ovf_int_ena.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH0_INT_ENA</name>
+              <description>reg_duty_chng_end_lsch0_int_ena.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH1_INT_ENA</name>
+              <description>reg_duty_chng_end_lsch1_int_ena.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH2_INT_ENA</name>
+              <description>reg_duty_chng_end_lsch2_int_ena.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH3_INT_ENA</name>
+              <description>reg_duty_chng_end_lsch3_int_ena.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH4_INT_ENA</name>
+              <description>reg_duty_chng_end_lsch4_int_ena.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH5_INT_ENA</name>
+              <description>reg_duty_chng_end_lsch5_int_ena.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH0_INT_ENA</name>
+              <description>reg_ovf_cnt_lsch0_int_ena.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH1_INT_ENA</name>
+              <description>reg_ovf_cnt_lsch1_int_ena.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH2_INT_ENA</name>
+              <description>reg_ovf_cnt_lsch2_int_ena.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH3_INT_ENA</name>
+              <description>reg_ovf_cnt_lsch3_int_ena.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH4_INT_ENA</name>
+              <description>reg_ovf_cnt_lsch4_int_ena.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH5_INT_ENA</name>
+              <description>reg_ovf_cnt_lsch5_int_ena.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>LEDC_INT_CLR.</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LSTIMER0_OVF_INT_CLR</name>
+              <description>reg_lstimer0_ovf_int_clr.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LSTIMER1_OVF_INT_CLR</name>
+              <description>reg_lstimer1_ovf_int_clr.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LSTIMER2_OVF_INT_CLR</name>
+              <description>reg_lstimer2_ovf_int_clr.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LSTIMER3_OVF_INT_CLR</name>
+              <description>reg_lstimer3_ovf_int_clr.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH0_INT_CLR</name>
+              <description>reg_duty_chng_end_lsch0_int_clr.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH1_INT_CLR</name>
+              <description>reg_duty_chng_end_lsch1_int_clr.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH2_INT_CLR</name>
+              <description>reg_duty_chng_end_lsch2_int_clr.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH3_INT_CLR</name>
+              <description>reg_duty_chng_end_lsch3_int_clr.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH4_INT_CLR</name>
+              <description>reg_duty_chng_end_lsch4_int_clr.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_LSCH5_INT_CLR</name>
+              <description>reg_duty_chng_end_lsch5_int_clr.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH0_INT_CLR</name>
+              <description>reg_ovf_cnt_lsch0_int_clr.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH1_INT_CLR</name>
+              <description>reg_ovf_cnt_lsch1_int_clr.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH2_INT_CLR</name>
+              <description>reg_ovf_cnt_lsch2_int_clr.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH3_INT_CLR</name>
+              <description>reg_ovf_cnt_lsch3_int_clr.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH4_INT_CLR</name>
+              <description>reg_ovf_cnt_lsch4_int_clr.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_LSCH5_INT_CLR</name>
+              <description>reg_ovf_cnt_lsch5_int_clr.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>LEDC_CONF.</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_CLK_SEL</name>
+              <description>reg_apb_clk_sel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>LEDC_DATE.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19061700</resetValue>
+          <fields>
+            <field>
+              <name>LEDC_DATE</name>
+              <description>reg_ledc_date.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RMT</name>
+      <description>Remote Control Peripheral</description>
+      <groupName>RMT</groupName>
+      <baseAddress>0x60016000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x78</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RMT</name>
+        <value>28</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CH0DATA</name>
+          <description>RMT_CH0DATA_REG.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH1DATA</name>
+          <description>RMT_CH1DATA_REG.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH2DATA</name>
+          <description>RMT_CH2DATA_REG.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH3DATA</name>
+          <description>RMT_CH3DATA_REG.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-1</dimIndex>
+          <name>CH%s_TX_CONF0</name>
+          <description>RMT_CH%sCONF%s_REG.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00710200</resetValue>
+          <fields>
+            <field>
+              <name>TX_START</name>
+              <description>reg_tx_start_ch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_RD_RST</name>
+              <description>reg_mem_rd_rst_ch0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST</name>
+              <description>reg_apb_mem_rst_ch0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_CONTI_MODE</name>
+              <description>reg_tx_conti_mode_ch0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TX_WRAP_EN</name>
+              <description>reg_mem_tx_wrap_en_ch0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_LV</name>
+              <description>reg_idle_out_lv_ch0.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_EN</name>
+              <description>reg_idle_out_en_ch0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP</name>
+              <description>reg_tx_stop_ch0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIV_CNT</name>
+              <description>reg_div_cnt_ch0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE</name>
+              <description>reg_mem_size_ch0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EFF_EN</name>
+              <description>reg_carrier_eff_en_ch0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN</name>
+              <description>reg_carrier_en_ch0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV</name>
+              <description>reg_carrier_out_lv_ch0.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFIFO_RST</name>
+              <description>reg_afifo_rst_ch0.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPDATE</name>
+              <description>reg_reg_conf_update_ch0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <dimIndex>2-3</dimIndex>
+          <name>CH%s_RX_CONF0</name>
+          <description>RMT_CH2CONF0_REG.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x30FFFF02</resetValue>
+          <fields>
+            <field>
+              <name>DIV_CNT</name>
+              <description>reg_div_cnt_ch2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_THRES</name>
+              <description>reg_idle_thres_ch2.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE</name>
+              <description>reg_mem_size_ch2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN</name>
+              <description>reg_carrier_en_ch2.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV</name>
+              <description>reg_carrier_out_lv_ch2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH2CONF1</name>
+          <description>RMT_CH2CONF1_REG.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001E8</resetValue>
+          <fields>
+            <field>
+              <name>RX_EN</name>
+              <description>reg_rx_en_ch2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_WR_RST</name>
+              <description>reg_mem_wr_rst_ch2.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST</name>
+              <description>reg_apb_mem_rst_ch2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER</name>
+              <description>reg_mem_owner_ch2.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_EN</name>
+              <description>reg_rx_filter_en_ch2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_THRES</name>
+              <description>reg_rx_filter_thres_ch2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_RX_WRAP_EN</name>
+              <description>reg_mem_rx_wrap_en_ch2.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFIFO_RST</name>
+              <description>reg_afifo_rst_ch2.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPDATE</name>
+              <description>reg_conf_update_ch2.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH3CONF1</name>
+          <description>RMT_CH3CONF1_REG.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001E8</resetValue>
+          <fields>
+            <field>
+              <name>RX_EN</name>
+              <description>reg_rx_en_ch3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_WR_RST</name>
+              <description>reg_mem_wr_rst_ch3.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST</name>
+              <description>reg_apb_mem_rst_ch3.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER</name>
+              <description>reg_mem_owner_ch3.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_EN</name>
+              <description>reg_rx_filter_en_ch3.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_THRES</name>
+              <description>reg_rx_filter_thres_ch3.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_RX_WRAP_EN</name>
+              <description>reg_mem_rx_wrap_en_ch3.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFIFO_RST</name>
+              <description>reg_afifo_rst_ch3.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPDATE</name>
+              <description>reg_conf_update_ch3.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH0STATUS</name>
+          <description>RMT_CH0STATUS_REG.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>reg_mem_raddr_ex_ch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>reg_state_ch0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WADDR</name>
+              <description>reg_apb_mem_waddr_ch0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>reg_apb_mem_rd_err_ch0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>reg_mem_empty_ch0.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>reg_apb_mem_wr_err_ch0.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR</name>
+              <description>reg_apb_mem_raddr_ch0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH1STATUS</name>
+          <description>RMT_CH1STATUS_REG.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>reg_mem_raddr_ex_ch1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>reg_state_ch1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WADDR</name>
+              <description>reg_apb_mem_waddr_ch1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>reg_apb_mem_rd_err_ch1.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>reg_mem_empty_ch1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>reg_apb_mem_wr_err_ch1.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR</name>
+              <description>reg_apb_mem_raddr_ch1.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH2STATUS</name>
+          <description>RMT_CH2STATUS_REG.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>reg_mem_waddr_ex_ch2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR</name>
+              <description>reg_apb_mem_raddr_ch2.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>reg_state_ch2.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>reg_mem_owner_err_ch2.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>reg_mem_full_ch2.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>reg_apb_mem_rd_err_ch2.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH3STATUS</name>
+          <description>RMT_CH3STATUS_REG.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>reg_mem_waddr_ex_ch3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR</name>
+              <description>reg_apb_mem_raddr_ch3.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>reg_state_ch3.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>reg_mem_owner_err_ch3.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>reg_mem_full_ch3.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>reg_apb_mem_rd_err_ch3.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>RMT_INT_RAW_REG.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_END_INT_RAW</name>
+              <description>reg_ch%s_tx_end_int_raw.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>2-3</dimIndex>
+              <name>CH%s_RX_END_INT_RAW</name>
+              <description>reg_ch2_rx_end_int_raw.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_ERR_INT_RAW</name>
+              <description>reg_ch%s_err_int_raw.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>2-3</dimIndex>
+              <name>CH%s_RX_ERR_INT_RAW</name>
+              <description>reg_ch2_err_int_raw.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_RAW</name>
+              <description>reg_ch%s_tx_thr_event_int_raw.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_RAW</name>
+              <description>reg_ch2_rx_thr_event_int_raw.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_RAW</name>
+              <description>reg_ch3_rx_thr_event_int_raw.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_LOOP_INT_RAW</name>
+              <description>reg_ch%s_tx_loop_int_raw.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>RMT_INT_ST_REG.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_END_INT_ST</name>
+              <description>reg_ch%s_tx_end_int_st.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>2-3</dimIndex>
+              <name>CH%s_RX_END_INT_ST</name>
+              <description>reg_ch2_rx_end_int_st.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_ERR_INT_ST</name>
+              <description>reg_ch%s_err_int_st.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>2-3</dimIndex>
+              <name>CH%s_RX_ERR_INT_ST</name>
+              <description>reg_ch2_err_int_st.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_ST</name>
+              <description>reg_ch%s_tx_thr_event_int_st.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_ST</name>
+              <description>reg_ch2_rx_thr_event_int_st.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_ST</name>
+              <description>reg_ch3_rx_thr_event_int_st.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_LOOP_INT_ST</name>
+              <description>reg_ch%s_tx_loop_int_st.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>RMT_INT_ENA_REG.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_END_INT_ENA</name>
+              <description>reg_ch%s_tx_end_int_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>2-3</dimIndex>
+              <name>CH%s_RX_END_INT_ENA</name>
+              <description>reg_ch2_rx_end_int_ena.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_ERR_INT_ENA</name>
+              <description>reg_ch%s_err_int_ena.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>2-3</dimIndex>
+              <name>CH%s_RX_ERR_INT_ENA</name>
+              <description>reg_ch2_err_int_ena.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_ENA</name>
+              <description>reg_ch%s_tx_thr_event_int_ena.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_ENA</name>
+              <description>reg_ch2_rx_thr_event_int_ena.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_ENA</name>
+              <description>reg_ch3_rx_thr_event_int_ena.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_LOOP_INT_ENA</name>
+              <description>reg_ch%s_tx_loop_int_ena.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>RMT_INT_CLR_REG.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_END_INT_CLR</name>
+              <description>reg_ch%s_tx_end_int_clr.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>2-3</dimIndex>
+              <name>CH%s_RX_END_INT_CLR</name>
+              <description>reg_ch2_rx_end_int_clr.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_ERR_INT_CLR</name>
+              <description>reg_ch%s_err_int_clr.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>2-3</dimIndex>
+              <name>CH%s_RX_ERR_INT_CLR</name>
+              <description>reg_ch2_err_int_clr.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_CLR</name>
+              <description>reg_ch%s_tx_thr_event_int_clr.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_CLR</name>
+              <description>reg_ch2_rx_thr_event_int_clr.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_CLR</name>
+              <description>reg_ch3_rx_thr_event_int_clr.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>2</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-1</dimIndex>
+              <name>CH%s_TX_LOOP_INT_CLR</name>
+              <description>reg_ch%s_tx_loop_int_clr.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH0CARRIER_DUTY</name>
+          <description>RMT_CH0CARRIER_DUTY_REG.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>reg_carrier_low_ch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>reg_carrier_high_ch0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH1CARRIER_DUTY</name>
+          <description>RMT_CH1CARRIER_DUTY_REG.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>reg_carrier_low_ch1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>reg_carrier_high_ch1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH2_RX_CARRIER_RM</name>
+          <description>RMT_CH2_RX_CARRIER_RM_REG.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARRIER_LOW_THRES</name>
+              <description>reg_carrier_low_thres_ch2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH_THRES</name>
+              <description>reg_carrier_high_thres_ch2.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH3_RX_CARRIER_RM</name>
+          <description>RMT_CH3_RX_CARRIER_RM_REG.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARRIER_LOW_THRES</name>
+              <description>reg_carrier_low_thres_ch3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH_THRES</name>
+              <description>reg_carrier_high_thres_ch3.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-1</dimIndex>
+          <name>CH%s_TX_LIM</name>
+          <description>RMT_CH%s_TX_LIM_REG.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>TX_LIM</name>
+              <description>reg_rmt_tx_lim_ch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_NUM</name>
+              <description>reg_rmt_tx_loop_num_ch0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_CNT_EN</name>
+              <description>reg_rmt_tx_loop_cnt_en_ch0.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOP_COUNT_RESET</name>
+              <description>reg_loop_count_reset_ch0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>2-3</dimIndex>
+          <name>CH%s_RX_LIM</name>
+          <description>RMT_CH2_RX_LIM_REG.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>RX_LIM</name>
+              <description>reg_rmt_rx_lim_ch2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYS_CONF</name>
+          <description>RMT_SYS_CONF_REG.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x05000010</resetValue>
+          <fields>
+            <field>
+              <name>APB_FIFO_MASK</name>
+              <description>reg_apb_fifo_mask.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>reg_mem_clk_force_on.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>reg_rmt_mem_force_pd.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>reg_rmt_mem_force_pu.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>reg_rmt_sclk_div_num.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>reg_rmt_sclk_div_a.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>reg_rmt_sclk_div_b.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>reg_rmt_sclk_sel.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_ACTIVE</name>
+              <description>reg_rmt_sclk_active.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_SIM</name>
+          <description>RMT_TX_SIM_REG.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_SIM_CH0</name>
+              <description>reg_rmt_tx_sim_ch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SIM_CH1</name>
+              <description>reg_rmt_tx_sim_ch1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SIM_EN</name>
+              <description>reg_rmt_tx_sim_en.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REF_CNT_RST</name>
+          <description>RMT_REF_CNT_RST_REG.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0</name>
+              <description>reg_ref_cnt_rst_ch0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH1</name>
+              <description>reg_ref_cnt_rst_ch1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH2</name>
+              <description>reg_ref_cnt_rst_ch2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH3</name>
+              <description>reg_ref_cnt_rst_ch3.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>RMT_DATE_REG.</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02006231</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_rmt_date.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RNG</name>
+      <description>Hardware random number generator</description>
+      <groupName>RNG</groupName>
+      <baseAddress>0x60026000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>DATA</name>
+          <description>Random number data</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RSA</name>
+      <description>RSA (Rivest Shamir Adleman) Accelerator</description>
+      <groupName>RSA</groupName>
+      <baseAddress>0x6003C000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x74</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RSA</name>
+        <value>47</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>The memory that stores M</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Z_MEM[%s]</name>
+          <description>The memory that stores Z</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Y_MEM[%s]</name>
+          <description>The memory that stores Y</description>
+          <addressOffset>0x400</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>X_MEM[%s]</name>
+          <description>The memory that stores X</description>
+          <addressOffset>0x600</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>M_PRIME</name>
+          <description>RSA M_prime register</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M_PRIME</name>
+              <description>Those bits stores m'</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>RSA mode register</description>
+          <addressOffset>0x804</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>rsa mode (rsa length).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_CLEAN</name>
+          <description>RSA query clean register</description>
+          <addressOffset>0x808</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_CLEAN</name>
+              <description>query clean</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_START_MODEXP</name>
+          <description>RSA modular exponentiation trigger register.</description>
+          <addressOffset>0x80C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START_MODEXP</name>
+              <description>start modular exponentiation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_START_MODMULT</name>
+          <description>RSA modular multiplication trigger register.</description>
+          <addressOffset>0x810</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START_MODMULT</name>
+              <description>start modular multiplication</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_START_MULT</name>
+          <description>RSA normal multiplication trigger register.</description>
+          <addressOffset>0x814</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START_MULT</name>
+              <description>start multiplicaiton</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_IDLE</name>
+          <description>RSA query idle register</description>
+          <addressOffset>0x818</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_IDLE</name>
+              <description>query rsa idle. 1'b0: busy, 1'b1: idle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>RSA interrupt clear register</description>
+          <addressOffset>0x81C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>set this bit to clear RSA interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONSTANT_TIME</name>
+          <description>RSA constant time option register</description>
+          <addressOffset>0x820</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CONSTANT_TIME</name>
+              <description>Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_ENABLE</name>
+          <description>RSA search option</description>
+          <addressOffset>0x824</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_ENABLE</name>
+              <description>Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_POS</name>
+          <description>RSA search position configure register</description>
+          <addressOffset>0x828</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_POS</name>
+              <description>Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>RSA interrupt enable register</description>
+          <addressOffset>0x82C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_ENA</name>
+              <description>Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>RSA version control register</description>
+          <addressOffset>0x830</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200618</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>rsa version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC_CNTL</name>
+      <description>Real-Time Clock Control</description>
+      <groupName>RTC_CNTL</groupName>
+      <baseAddress>0x60008000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x12C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_CORE</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>OPTIONS0</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1C00A000</resetValue>
+          <fields>
+            <field>
+              <name>SW_STALL_APPCPU_C0</name>
+              <description>{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STALL_PROCPU_C0</name>
+              <description>{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_APPCPU_RST</name>
+              <description>APP CPU SW reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_PROCPU_RST</name>
+              <description>PRO CPU SW reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PD</name>
+              <description>BB_I2C force power down</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PU</name>
+              <description>BB_I2C force power up</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PD</name>
+              <description>BB_PLL _I2C force power down</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PU</name>
+              <description>BB_PLL_I2C force power up</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PD</name>
+              <description>BB_PLL force power down</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PU</name>
+              <description>BB_PLL force power up</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PD</name>
+              <description>crystall force power down</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PU</name>
+              <description>crystall force power up</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EN_WAIT</name>
+              <description>wait bias_sleep and current source wakeup</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_SEL</name>
+              <description>analog configure</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_ISO</name>
+              <description>analog configure</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FORCE_ISO</name>
+              <description>analog configure</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_ISO</name>
+              <description>analog configure</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_NOISO</name>
+              <description>analog configure</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FORCE_NOISO</name>
+              <description>analog configure</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_NOISO</name>
+              <description>analog configure</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_RST</name>
+              <description>digital wrap force reset in deep sleep</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NORST</name>
+              <description>digital core force no reset in deep sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_SYS_RST</name>
+              <description>SW system reset</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER0</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_LO</name>
+              <description>configure the  sleep time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER1</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_HI</name>
+              <description>RTC sleep timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_ALARM_EN</name>
+              <description>timer alarm enable bit</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_UPDATE</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SYS_STALL</name>
+              <description>Enable to record system stall time</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_XTL_OFF</name>
+              <description>Enable to record 40M XTAL OFF time</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_SYS_RST</name>
+              <description>enable to record system reset time</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_UPDATE</name>
+              <description>Set 1: to update register with RTC timer</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_LOW0</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE0_LOW</name>
+              <description>RTC timer low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_HIGH0</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE0_HIGH</name>
+              <description>RTC timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_CPU_INT</name>
+              <description>rtc software interrupt to main cpu</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_CAUSE_CLR</name>
+              <description>clear rtc sleep reject cause</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB2RTC_BRIDGE_SEL</name>
+              <description>1: APB to RTC using bridge</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_ACTIVE_IND</name>
+              <description>SDIO active indication</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_WAKEUP</name>
+              <description>leep wakeup bit</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT</name>
+              <description>leep reject bit</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_EN</name>
+              <description>sleep enable bit</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x28140403</resetValue>
+          <fields>
+            <field>
+              <name>CPU_STALL_EN</name>
+              <description>CPU stall enable bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_STALL_WAIT</name>
+              <description>CPU stall wait cycles in fast_clk_rtc</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_WAIT</name>
+              <description>CK8M wait cycles in slow_clk_rtc</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_BUF_WAIT</name>
+              <description>XTAL wait cycles in slow_clk_rtc</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_BUF_WAIT</name>
+              <description>PLL wait cycles in slow_clk_rtc</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000000</resetValue>
+          <fields>
+            <field>
+              <name>MIN_TIME_CK8M_OFF</name>
+              <description>minimal cycles in slow_clk_rtc for CK8M in power down state</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER3</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0A080A08</resetValue>
+          <fields>
+            <field>
+              <name>WIFI_WAIT_TIMER</name>
+              <description>wifi power domain wakeup time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_POWERUP_TIMER</name>
+              <description>wifi power domain power on time</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_WAIT_TIMER</name>
+              <description>bt power domain wakeup time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_POWERUP_TIMER</name>
+              <description>bt power domain power on time</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER4</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10200A08</resetValue>
+          <fields>
+            <field>
+              <name>CPU_TOP_WAIT_TIMER</name>
+              <description>cpu top power domain wakeup time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_POWERUP_TIMER</name>
+              <description>cpu top power domain power on time</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_WAIT_TIMER</name>
+              <description>digital wrap power domain wakeup time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_POWERUP_TIMER</name>
+              <description>digital wrap power domain power on time</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER5</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MIN_SLP_VAL</name>
+              <description>minimal sleep cycles in slow_clk_rtc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER6</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0A080000</resetValue>
+          <fields>
+            <field>
+              <name>DG_PERI_WAIT_TIMER</name>
+              <description>digital peri power domain wakeup time</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_POWERUP_TIMER</name>
+              <description>digital peri power domain power on time</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ANA_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C40000</resetValue>
+          <fields>
+            <field>
+              <name>RESET_POR_FORCE_PD</name>
+              <description>force no bypass i2c power on reset</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESET_POR_FORCE_PU</name>
+              <description>force bypass i2c power on reset</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_RST_EN</name>
+              <description>enable glitch reset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_PU</name>
+              <description>PLLA force power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLA_FORCE_PD</name>
+              <description>PLLA force power down</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLA_FORCE_PU</name>
+              <description>PLLA force power up</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_SLP_START</name>
+              <description>start BBPLL calibration during sleep</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVTMON_PU</name>
+              <description>1: PVTMON power up</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXRF_I2C_PU</name>
+              <description>1: TXRF_I2C power up</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RFRX_PBUS_PU</name>
+              <description>1: RFRX_PBUS power up</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CKGEN_I2C_PU</name>
+              <description>1: CKGEN_I2C power up</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_I2C_PU</name>
+              <description>power up pll i2c</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESET_STATE</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003000</resetValue>
+          <fields>
+            <field>
+              <name>RESET_CAUSE_PROCPU</name>
+              <description>reset cause of PRO CPU</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESET_CAUSE_APPCPU</name>
+              <description>reset cause of APP CPU</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STAT_VECTOR_SEL_APPCPU</name>
+              <description>APP CPU state vector sel</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STAT_VECTOR_SEL_PROCPU</name>
+              <description>PRO CPU state vector sel</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALL_RESET_FLAG_PROCPU</name>
+              <description>PRO CPU reset_flag</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ALL_RESET_FLAG_APPCPU</name>
+              <description>APP CPU reset flag</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ALL_RESET_FLAG_CLR_PROCPU</name>
+              <description>clear PRO CPU reset_flag</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ALL_RESET_FLAG_CLR_APPCPU</name>
+              <description>clear APP CPU reset flag</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OCD_HALT_ON_RESET_APPCPU</name>
+              <description>APPCPU OcdHaltOnReset</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OCD_HALT_ON_RESET_PROCPU</name>
+              <description>PROCPU OcdHaltOnReset</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>JTAG_RESET_FLAG_PROCPU</name>
+              <description>configure jtag reset configure</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>JTAG_RESET_FLAG_APPCPU</name>
+              <description>configure jtag reset configure</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>JTAG_RESET_FLAG_CLR_PROCPU</name>
+              <description>configure jtag reset configure</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>JTAG_RESET_FLAG_CLR_APPCPU</name>
+              <description>configure jtag reset configure</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DRESET_MASK_APPCPU</name>
+              <description>configure dreset configure</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRESET_MASK_PROCPU</name>
+              <description>configure dreset configure</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP_STATE</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00060000</resetValue>
+          <fields>
+            <field>
+              <name>WAKEUP_ENA</name>
+              <description>wakeup enable bitmap</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA</name>
+              <description>enable sleep wakeup interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA</name>
+              <description>enable sleep reject interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>enable RTC WDT interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA</name>
+              <description>enable brown out interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA</name>
+              <description>enable RTC main timer interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_INT_ENA</name>
+              <description>enable super watch dog interrupt</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ENA</name>
+              <description>enable xtal32k_dead  interrupt</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>enbale gitch det interrupt</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_ENA</name>
+              <description>enbale bbpll cal end interrupt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_RTC</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_RAW</name>
+              <description>sleep wakeup interrupt raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_RAW</name>
+              <description>sleep reject interrupt raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>RTC WDT interrupt raw</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_RAW</name>
+              <description>brown out interrupt raw</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_RAW</name>
+              <description>RTC main timer interrupt raw</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_RAW</name>
+              <description>super watch dog interrupt raw</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_RAW</name>
+              <description>xtal32k dead detection interrupt raw</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>glitch_det_interrupt_raw</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_RAW</name>
+              <description>bbpll cal end interrupt state</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_RTC</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ST</name>
+              <description>sleep wakeup interrupt state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ST</name>
+              <description>sleep reject interrupt state</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>RTC WDT interrupt state</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ST</name>
+              <description>brown out interrupt state</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ST</name>
+              <description>RTC main timer interrupt state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_ST</name>
+              <description>super watch dog interrupt state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ST</name>
+              <description>xtal32k dead detection interrupt state</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>glitch_det_interrupt state</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_ST</name>
+              <description>bbpll cal end interrupt state</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_RTC</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_CLR</name>
+              <description>Clear sleep wakeup interrupt state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_CLR</name>
+              <description>Clear sleep reject interrupt state</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Clear RTC WDT interrupt state</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_CLR</name>
+              <description>Clear brown out interrupt state</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_CLR</name>
+              <description>Clear RTC main timer interrupt state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_CLR</name>
+              <description>Clear super watch dog interrupt state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_CLR</name>
+              <description>Clear RTC WDT interrupt state</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Clear glitch det interrupt state</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_CLR</name>
+              <description>clear bbpll cal end interrupt state</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE0</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH0</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE1</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH1</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE2</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH2</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE3</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH3</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_XTL_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00066C80</resetValue>
+          <fields>
+            <field>
+              <name>XTAL32K_WDT_EN</name>
+              <description>xtal 32k watch dog enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_WDT_CLK_FO</name>
+              <description>xtal 32k watch dog clock force on</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_WDT_RESET</name>
+              <description>xtal 32k watch dog sw reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_EXT_CLK_FO</name>
+              <description>xtal 32k external xtal clock force on</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_AUTO_BACKUP</name>
+              <description>xtal 32k switch to back up clock when xtal is dead</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_AUTO_RESTART</name>
+              <description>xtal 32k restart xtal when xtal is dead</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_AUTO_RETURN</name>
+              <description>xtal 32k switch back xtal when xtal is restarted</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_XPD_FORCE</name>
+              <description>Xtal 32k xpd control by sw or fsm</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCKINIT_XTAL_32K</name>
+              <description>apply an internal clock to help xtal 32k to start</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUF_XTAL_32K</name>
+              <description>0: single-end buffer 1: differential buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DGM_XTAL_32K</name>
+              <description>xtal_32k gm control</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRES_XTAL_32K</name>
+              <description>DRES_XTAL_32K</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_XTAL_32K</name>
+              <description>XPD_XTAL_32K</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_XTAL_32K</name>
+              <description>DAC_XTAL_32K</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STATE</name>
+              <description>state of 32k_wdt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_GPIO_SEL</name>
+              <description>XTAL_32K sel. 0: external XTAL_32K</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_LV</name>
+              <description>0: power down XTAL at high level</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_EN</name>
+              <description>enable gpio configure xtal power on</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_WAKEUP_FILTER</name>
+              <description>enable filter for gpio wakeup event</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_REJECT_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLEEP_REJECT_ENA</name>
+              <description>sleep reject enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LIGHT_SLP_REJECT_EN</name>
+              <description>enable reject for light sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEEP_SLP_REJECT_EN</name>
+              <description>enable reject for deep sleep</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERIOD_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPUSEL_CONF</name>
+              <description>CPU sel option</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <description>CPU clk sel option</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x11583218</resetValue>
+          <fields>
+            <field>
+              <name>EFUSE_CLK_FORCE_GATING</name>
+              <description>efuse_clk_force_gating</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_CLK_FORCE_NOGATING</name>
+              <description>efuse_clk_force_nogating</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV_SEL_VLD</name>
+              <description>used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV</name>
+              <description>CK8M_D256_OUT divider. 00: div128</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_CK8M</name>
+              <description>disable CK8M and CK8M_D256_OUT</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_CK8M_DIV</name>
+              <description>1: CK8M_D256_OUT is actually CK8M</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_XTAL32K_EN</name>
+              <description>enable CK_XTAL_32K for digital core (no relationship with RTC core)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_D256_EN</name>
+              <description>enable CK8M_D256_OUT for digital core (no relationship with RTC core)</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_EN</name>
+              <description>enable CK8M for digital core (no relationship with RTC core)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV_SEL</name>
+              <description>divider = reg_ck8m_div_sel + 1</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_FORCE_NOGATING</name>
+              <description>XTAL force no gating during sleep</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_NOGATING</name>
+              <description>CK8M force no gating during sleep</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DFREQ</name>
+              <description>CK8M_DFREQ</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PD</name>
+              <description>CK8M force power down</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PU</name>
+              <description>CK8M force power up</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_GLOBAL_FORCE_GATING</name>
+              <description>force enable xtal clk gating</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_GLOBAL_FORCE_NOGATING</name>
+              <description>force bypass xtal clk gating</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_CLK_RTC_SEL</name>
+              <description>fast_clk_rtc sel. 0: XTAL div 4</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANA_CLK_RTC_SEL</name>
+              <description>slelect rtc slow clk</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLOW_CLK_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>ANA_CLK_DIV_VLD</name>
+              <description>used to sync div bus. clear vld before set reg_rtc_ana_clk_div</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANA_CLK_DIV</name>
+              <description>the clk divider num of RTC_CLK</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOW_CLK_NEXT_EDGE</name>
+              <description>flag rtc_slow_clk_next_edge</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0AB0BE0A</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_TIMER_TARGET</name>
+              <description>timer count to apply reg_sdio_dcap after sdio power on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DTHDRV</name>
+              <description>Tieh = 1 mode drive ability. Initially set to 0 to limit charge current</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DCAP</name>
+              <description>ability to prevent LDO from overshoot</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_INITI</name>
+              <description>add resistor from ldo output to ground. 0: no res</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_EN_INITI</name>
+              <description>0 to set init[1:0]=0</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DCURLIM</name>
+              <description>tune current limit threshold when tieh = 0. About 800mA/(8+d)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_MODECURLIM</name>
+              <description>select current limit mode</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_ENCURLIM</name>
+              <description>enable current limit</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_REG_PD_EN</name>
+              <description>power down SDIO_REG in sleep. Only active when reg_sdio_force = 0</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_FORCE</name>
+              <description>1: use SW option to control SDIO_REG</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_TIEH</name>
+              <description>SW option for SDIO_TIEH. Only active when reg_sdio_force = 1</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>_1P8_READY</name>
+              <description>read only register for REG1P8_READY</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DREFL_SDIO</name>
+              <description>SW option for DREFL_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DREFM_SDIO</name>
+              <description>SW option for DREFM_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DREFH_SDIO</name>
+              <description>SW option for DREFH_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SDIO</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BIAS_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010800</resetValue>
+          <fields>
+            <field>
+              <name>DG_VDD_DRV_B_SLP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_VDD_DRV_B_SLP_EN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_IDLE</name>
+              <description>bias buf when rtc in normal work state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_WAKE</name>
+              <description>bias buf when rtc in wakeup state</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_DEEP_SLP</name>
+              <description>bias buf when rtc in sleep state</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_MONITOR</name>
+              <description>bias buf when rtc in monitor state</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_CUR_DEEP_SLP</name>
+              <description>xpd cur when rtc in sleep_state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_CUR_MONITOR</name>
+              <description>xpd cur when rtc in monitor state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_SLEEP_DEEP_SLP</name>
+              <description>bias_sleep when rtc in sleep_state</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_SLEEP_MONITOR</name>
+              <description>bias_sleep when rtc in monitor state</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_DEEP_SLP</name>
+              <description>DBG_ATTEN when rtc in sleep state</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_MONITOR</name>
+              <description>DBG_ATTEN when rtc in monitor state</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_CNTL</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xA0000000</resetValue>
+          <fields>
+            <field>
+              <name>DIG_REG_CAL_EN</name>
+              <description>software enable digital regulator cali</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCK_DCAP</name>
+              <description>SCK_DCAP</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBOOST_FORCE_PD</name>
+              <description>RTC_DBOOST force power down</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBOOST_FORCE_PU</name>
+              <description>RTC_DBOOST force power up</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGULATOR_FORCE_PD</name>
+              <description>RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGULATOR_FORCE_PU</name>
+              <description>RTC_REG force power up</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWC</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PAD_FORCE_HOLD</name>
+              <description>rtc pad force hold</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PWC</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00555010</resetValue>
+          <fields>
+            <field>
+              <name>VDD_SPI_PWR_DRV</name>
+              <description>vdd_spi drv's software value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VDD_SPI_PWR_FORCE</name>
+              <description>vdd_spi drv use software value</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSLP_MEM_FORCE_PD</name>
+              <description>memories in digital core force PD in sleep</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSLP_MEM_FORCE_PU</name>
+              <description>memories in digital core force PU in sleep</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_FORCE_PD</name>
+              <description>bt force power down</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_FORCE_PU</name>
+              <description>bt force power up</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_FORCE_PD</name>
+              <description>digital peri force power down</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_FORCE_PU</name>
+              <description>digital peri force power up</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_LPD</name>
+              <description>fastmemory  retention mode in sleep</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_LPU</name>
+              <description>fastmemory donlt entry retention mode in sleep</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_PD</name>
+              <description>wifi force power down</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_PU</name>
+              <description>wifi force power up</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PD</name>
+              <description>digital core force power down</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PU</name>
+              <description>digital core force power up</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_FORCE_PD</name>
+              <description>cpu core force power down</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_FORCE_PU</name>
+              <description>cpu force power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_PD_EN</name>
+              <description>enable power down bt in sleep</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_PD_EN</name>
+              <description>enable power down digital peri in sleep</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_PD_EN</name>
+              <description>enable power down cpu in sleep</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_PD_EN</name>
+              <description>enable power down wifi in sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_PD_EN</name>
+              <description>enable power down digital wrap in sleep</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_ISO</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xAA805080</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_OFF</name>
+              <description>DIG_ISO force off</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_ON</name>
+              <description>DIG_ISO force on</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD</name>
+              <description>read only register to indicate digital pad auto-hold status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLR_DG_PAD_AUTOHOLD</name>
+              <description>wtite only register to clear digital pad auto-hold</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD_EN</name>
+              <description>digital pad enable auto-hold</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_NOISO</name>
+              <description>digital pad force no ISO</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_ISO</name>
+              <description>digital pad force ISO</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_UNHOLD</name>
+              <description>digital pad force un-hold</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_HOLD</name>
+              <description>digital pad force hold</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_FORCE_ISO</name>
+              <description>bt force ISO</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_FORCE_NOISO</name>
+              <description>bt force no ISO</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_FORCE_ISO</name>
+              <description>Digital peri force ISO</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_FORCE_NOISO</name>
+              <description>digital peri force no ISO</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_FORCE_ISO</name>
+              <description>cpu force ISO</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_FORCE_NOISO</name>
+              <description>cpu force no ISO</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_ISO</name>
+              <description>wifi force ISO</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_NOISO</name>
+              <description>wifi force no ISO</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_ISO</name>
+              <description>digital core force ISO</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NOISO</name>
+              <description>digital core force no ISO</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013214</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CHIP_RESET_WIDTH</name>
+              <description>chip reset siginal pulse width</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CHIP_RESET_EN</name>
+              <description>wdt reset whole chip enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PAUSE_IN_SLP</name>
+              <description>pause WDT in sleep</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>enable WDT reset APP CPU</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>enable WDT reset PRO CPU</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>enable WDT in flash boot</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>system reset counter length</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>CPU reset counter length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>1: interrupt stage en</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>1: interrupt stage en</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>1: interrupt stage en</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>1: interrupt stage en</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>enable rtc wdt</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030D40</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>the hold time of stage0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013880</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>the hold time of stage1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>the hold time of stage2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>the hold time of stage3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>sw feed rtc wdt</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>the key of rtc wdt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x04B00000</resetValue>
+          <fields>
+            <field>
+              <name>SWD_RESET_FLAG</name>
+              <description>swd reset flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_FEED_INT</name>
+              <description>swd interrupt for feeding</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_BYPASS_RST</name>
+              <description>Bypass swd rst</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_SIGNAL_WIDTH</name>
+              <description>adjust signal width send to swd</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_RST_FLAG_CLR</name>
+              <description>reset swd reset flag</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_FEED</name>
+              <description>Sw feed swd</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_DISABLE</name>
+              <description>disabel SWD</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_AUTO_FEED_EN</name>
+              <description>automatically feed swd when int comes</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_WPROTECT</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SWD_WKEY</name>
+              <description>the key of super wdt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SW_CPU_STALL</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_STALL_APPCPU_C1</name>
+              <description>{reg_sw_stall_appcpu_c1[5:0]</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STALL_PROCPU_C1</name>
+              <description>stall cpu by software</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE4</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH4</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE5</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH5</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE6</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH6</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE7</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH7</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOW_POWER_ST</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XPD_ROM0</name>
+              <description>rom0 power down</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_DIG_DCDC</name>
+              <description>External DCDC power down</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERI_ISO</name>
+              <description>rtc peripheral iso</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_RTC_PERI</name>
+              <description>rtc peripheral power down</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WIFI_ISO</name>
+              <description>wifi iso</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_WIFI</name>
+              <description>wifi wrap power down</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIG_ISO</name>
+              <description>digital wrap iso</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_DIG</name>
+              <description>digital wrap power down</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_START</name>
+              <description>touch should start to work</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_SWITCH</name>
+              <description>touch is about to working. Switch rtc main state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_SLP</name>
+              <description>touch is in sleep state</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_DONE</name>
+              <description>touch is done</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_START</name>
+              <description>ulp/cocpu should start to work</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_SWITCH</name>
+              <description>ulp/cocpu is about to working. Switch rtc main state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_SLP</name>
+              <description>ulp/cocpu is in sleep state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_DONE</name>
+              <description>ulp/cocpu is done</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_XTAL_ISO</name>
+              <description>no use any more</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_PLL_ON</name>
+              <description>rtc main state machine is in states that pll should be running</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RDY_FOR_WAKEUP</name>
+              <description>rtc is ready to receive wake up trigger from wake up source</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_WAIT_END</name>
+              <description>rtc main state machine has been waited for some cycles</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_WAKEUP_STATE</name>
+              <description>rtc main state machine is in the states of wakeup process</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_LOW_POWER_STATE</name>
+              <description>rtc main state machine is in the states of low power</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_8M</name>
+              <description>rtc main state machine is in wait 8m state</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_PLL</name>
+              <description>rtc main state machine is in wait pll state</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_XTL</name>
+              <description>rtc main state machine is in wait xtal state</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_SLP</name>
+              <description>rtc main state machine is in sleep state</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_IDLE</name>
+              <description>rtc main state machine is in idle state</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE</name>
+              <description>rtc main state machine status</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIAG0</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOW_POWER_DIAG1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_HOLD</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_PIN0_HOLD</name>
+              <description>the hold configure of rtc gpio0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_HOLD</name>
+              <description>the hold configure of rtc gpio1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_HOLD</name>
+              <description>the hold configure of rtc gpio2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_HOLD</name>
+              <description>the hold configure of rtc gpio3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_HOLD</name>
+              <description>the hold configure of rtc gpio4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_HOLD</name>
+              <description>the hold configure of rtc gpio5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PAD_HOLD</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIG_PAD_HOLD</name>
+              <description>the configure of digital pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BROWN_OUT</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x43FF0010</resetValue>
+          <fields>
+            <field>
+              <name>BROWN_OUT_INT_WAIT</name>
+              <description>brown out interrupt wait cycles</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_CLOSE_FLASH_ENA</name>
+              <description>enable close flash when brown out happens</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_PD_RF_ENA</name>
+              <description>enable power down RF when brown out happens</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_RST_WAIT</name>
+              <description>brown out reset wait cycles</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_RST_ENA</name>
+              <description>enable brown out reset</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_RST_SEL</name>
+              <description>1:  4-pos reset</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_ANA_RST_EN</name>
+              <description>brown_out origin reset enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_CNT_CLR</name>
+              <description>clear brown out counter</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_ENA</name>
+              <description>enable brown out</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET</name>
+              <description>the flag of brown det from analog</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_LOW1</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE1_LOW</name>
+              <description>RTC timer low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_HIGH1</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE1_HIGH</name>
+              <description>RTC timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL32K_CLK_FACTOR</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XTAL32K_CLK_FACTOR</name>
+              <description>xtal 32k watch dog backup clock factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL32K_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0FF00000</resetValue>
+          <fields>
+            <field>
+              <name>XTAL32K_RETURN_WAIT</name>
+              <description>cycles to wait to return noral xtal 32k</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_RESTART_WAIT</name>
+              <description>cycles to wait to repower on xtal 32k</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_WDT_TIMEOUT</name>
+              <description>If no clock detected for this amount of time</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_STABLE_THRES</name>
+              <description>if restarted xtal32k period is smaller than this</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_CONF</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IO_MUX_RESET_DISABLE</name>
+              <description>disable io_mux reset</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_REJECT_CAUSE</name>
+          <description>RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REJECT_CAUSE</name>
+              <description>sleep reject cause</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OPTION1</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FORCE_DOWNLOAD_BOOT</name>
+              <description>force chip entry download mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CAUSE</name>
+          <description>RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WAKEUP_CAUSE</name>
+              <description>sleep wakeup cause</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_TIMER_1</name>
+          <description>rtc configure register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C800</resetValue>
+          <fields>
+            <field>
+              <name>ULP_CP_TIMER_SLP_CYCLE</name>
+              <description>sleep cycles for ULP-coprocessor timer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC_W1TS</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA_W1TS</name>
+              <description>enable sleep wakeup interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA_W1TS</name>
+              <description>enable sleep reject interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA_W1TS</name>
+              <description>enable RTC WDT interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA_W1TS</name>
+              <description>enable brown out interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA_W1TS</name>
+              <description>enable RTC main timer interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_ENA_W1TS</name>
+              <description>enable super watch dog interrupt</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ENA_W1TS</name>
+              <description>enable xtal32k_dead  interrupt</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA_W1TS</name>
+              <description>enbale gitch det interrupt</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_ENA_W1TS</name>
+              <description>enbale bbpll cal interrupt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC_W1TC</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA_W1TC</name>
+              <description>clear sleep wakeup interrupt enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA_W1TC</name>
+              <description>clear sleep reject interrupt enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA_W1TC</name>
+              <description>clear RTC WDT interrupt enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA_W1TC</name>
+              <description>clear brown out interrupt enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA_W1TC</name>
+              <description>Clear RTC main timer interrupt enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_ENA_W1TC</name>
+              <description>clear super watch dog interrupt enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ENA_W1TC</name>
+              <description>clear xtal32k_dead  interrupt enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA_W1TC</name>
+              <description>clear gitch det interrupt enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_INT_ENA_W1TC</name>
+              <description>clear bbpll cal interrupt enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xA0D00000</resetValue>
+          <fields>
+            <field>
+              <name>RETENTION_CLK_SEL</name>
+              <description>Retention clk sel</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_DONE_WAIT</name>
+              <description>Retention done wait time</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_CLKOFF_WAIT</name>
+              <description>Retention clkoff wait time</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_EN</name>
+              <description>enable cpu retention when light sleep</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_WAIT</name>
+              <description>wait cycles for rention operation</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIB_SEL</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>FIB_SEL</name>
+              <description>select use analog fib signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_WAKEUP</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_WAKEUP_STATUS</name>
+              <description>rtc gpio wakeup flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO_WAKEUP_STATUS_CLR</name>
+              <description>clear rtc gpio wakeup flag</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN_CLK_GATE</name>
+              <description>enable rtc io clk gate</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_INT_TYPE</name>
+              <description>configure gpio wakeup type</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_INT_TYPE</name>
+              <description>configure gpio wakeup type</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_INT_TYPE</name>
+              <description>configure gpio wakeup type</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_INT_TYPE</name>
+              <description>configure gpio wakeup type</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_INT_TYPE</name>
+              <description>configure gpio wakeup type</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_INT_TYPE</name>
+              <description>configure gpio wakeup type</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_WAKEUP_ENABLE</name>
+              <description>enable wakeup from rtc gpio5</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_WAKEUP_ENABLE</name>
+              <description>enable wakeup from rtc gpio4</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_WAKEUP_ENABLE</name>
+              <description>enable wakeup from rtc gpio3</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_WAKEUP_ENABLE</name>
+              <description>enable wakeup from rtc gpio2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_WAKEUP_ENABLE</name>
+              <description>enable wakeup from rtc gpio1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_WAKEUP_ENABLE</name>
+              <description>enable wakeup from rtc gpio0</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBG_SEL</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DEBUG_12M_NO_GATING</name>
+              <description>use for debug</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_BIT_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL0</name>
+              <description>use for debug</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL1</name>
+              <description>use for debug</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL2</name>
+              <description>use for debug</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL3</name>
+              <description>use for debug</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_SEL4</name>
+              <description>use for debug</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBG_MAP</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_PIN5_MUX_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_MUX_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_MUX_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_MUX_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_MUX_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_MUX_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_FUN_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_FUN_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_FUN_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_FUN_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_FUN_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_FUN_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SENSOR_CTRL</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR2_PWDET_CCT</name>
+              <description>reg_sar2_pwdet_cct</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XPD_SAR</name>
+              <description>force power up SAR</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBG_SAR_SEL</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_DEBUG_SEL</name>
+              <description>use for debug</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PG_CTRL</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>POWER_GLITCH_DSENSE</name>
+              <description>power glitch desense</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_FORCE_PD</name>
+              <description>force disable power glitch</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_FORCE_PU</name>
+              <description>force enable power glitch</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_EFUSE_SEL</name>
+              <description>use efuse value control power glitch enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_EN</name>
+              <description>enable power glitch</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>rtc configure register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007270</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>verision</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SENSITIVE</name>
+      <description>Sensitive</description>
+      <groupName>SENSITIVE</groupName>
+      <baseAddress>0x600C1000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x178</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>ROM_TABLE_LOCK</name>
+          <description>SENSITIVE_ROM_TABLE_LOCK_REG</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ROM_TABLE_LOCK</name>
+              <description>rom_table_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_TABLE</name>
+          <description>SENSITIVE_ROM_TABLE_REG</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ROM_TABLE</name>
+              <description>rom_table</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRIVILEGE_MODE_SEL_LOCK</name>
+          <description>SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRIVILEGE_MODE_SEL_LOCK</name>
+              <description>privilege_mode_sel_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRIVILEGE_MODE_SEL</name>
+          <description>SENSITIVE_PRIVILEGE_MODE_SEL_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRIVILEGE_MODE_SEL</name>
+              <description>privilege_mode_sel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_ACCESS_0</name>
+          <description>SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_PERIPHERAL_ACCESS_LOCK</name>
+              <description>apb_peripheral_access_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_ACCESS_1</name>
+          <description>SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>APB_PERIPHERAL_ACCESS_SPLIT_BURST</name>
+              <description>apb_peripheral_access_split_burst</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_0</name>
+          <description>SENSITIVE_INTERNAL_SRAM_USAGE_0_REG</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_LOCK</name>
+              <description>internal_sram_usage_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_1</name>
+          <description>SENSITIVE_INTERNAL_SRAM_USAGE_1_REG</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_CPU_CACHE</name>
+              <description>internal_sram_usage_cpu_cache</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_CPU_SRAM</name>
+              <description>internal_sram_usage_cpu_sram</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_3</name>
+          <description>SENSITIVE_INTERNAL_SRAM_USAGE_3_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM</name>
+              <description>internal_sram_usage_mac_dump_sram</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_ALLOC_MAC_DUMP</name>
+              <description>internal_sram_alloc_mac_dump</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_4</name>
+          <description>SENSITIVE_INTERNAL_SRAM_USAGE_4_REG</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_LOG_SRAM</name>
+              <description>internal_sram_usage_log_sram</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_ACCESS_0</name>
+          <description>SENSITIVE_CACHE_TAG_ACCESS_0_REG</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_TAG_ACCESS_LOCK</name>
+              <description>cache_tag_access_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_ACCESS_1</name>
+          <description>SENSITIVE_CACHE_TAG_ACCESS_1_REG</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I_TAG_RD_ACS</name>
+              <description>pro_i_tag_rd_acs</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_I_TAG_WR_ACS</name>
+              <description>pro_i_tag_wr_acs</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_D_TAG_RD_ACS</name>
+              <description>pro_d_tag_rd_acs</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_D_TAG_WR_ACS</name>
+              <description>pro_d_tag_wr_acs</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_ACCESS_0</name>
+          <description>SENSITIVE_CACHE_MMU_ACCESS_0_REG</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_ACCESS_LOCK</name>
+              <description>cache_mmu_access_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_ACCESS_1</name>
+          <description>SENSITIVE_CACHE_MMU_ACCESS_1_REG</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MMU_RD_ACS</name>
+              <description>pro_mmu_rd_acs</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_MMU_WR_ACS</name>
+              <description>pro_mmu_wr_acs</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK</name>
+              <description>dma_apbperi_spi2_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK</name>
+              <description>dma_apbperi_uchi0_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK</name>
+              <description>dma_apbperi_i2s0_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK</name>
+              <description>dma_apbperi_mac_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>dma_apbperi_mac_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>dma_apbperi_mac_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>dma_apbperi_mac_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>dma_apbperi_mac_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>dma_apbperi_mac_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>dma_apbperi_mac_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>dma_apbperi_mac_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>dma_apbperi_mac_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK</name>
+              <description>dma_apbperi_backup_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>dma_apbperi_backup_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>dma_apbperi_backup_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>dma_apbperi_backup_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>dma_apbperi_backup_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>dma_apbperi_backup_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>dma_apbperi_backup_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>dma_apbperi_backup_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>dma_apbperi_backup_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_LC_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK</name>
+              <description>dma_apbperi_lc_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_LC_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>dma_apbperi_lc_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>dma_apbperi_lc_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>dma_apbperi_lc_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>dma_apbperi_lc_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>dma_apbperi_lc_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>dma_apbperi_lc_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>dma_apbperi_lc_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>dma_apbperi_lc_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_AES_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK</name>
+              <description>dma_apbperi_aes_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_AES_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>dma_apbperi_aes_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>dma_apbperi_aes_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>dma_apbperi_aes_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>dma_apbperi_aes_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>dma_apbperi_aes_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>dma_apbperi_aes_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>dma_apbperi_aes_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>dma_apbperi_aes_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK</name>
+              <description>dma_apbperi_sha_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>dma_apbperi_sha_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>dma_apbperi_sha_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>dma_apbperi_sha_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>dma_apbperi_sha_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>dma_apbperi_sha_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>dma_apbperi_sha_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>dma_apbperi_sha_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>dma_apbperi_sha_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK</name>
+              <description>dma_apbperi_adc_dac_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_0</name>
+          <description>SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_LOCK</name>
+              <description>dma_apbperi_pms_monitor_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_1</name>
+          <description>SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>dma_apbperi_pms_monitor_violate_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_EN</name>
+              <description>dma_apbperi_pms_monitor_violate_en</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_2</name>
+          <description>SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>dma_apbperi_pms_monitor_violate_intr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD</name>
+              <description>dma_apbperi_pms_monitor_violate_status_world</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR</name>
+              <description>dma_apbperi_pms_monitor_violate_status_addr</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_3</name>
+          <description>SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR</name>
+              <description>dma_apbperi_pms_monitor_violate_status_wr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN</name>
+              <description>dma_apbperi_pms_monitor_violate_status_byteen</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0</name>
+          <description>SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK</name>
+              <description>core_x_iram0_dram0_dma_split_line_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1</name>
+          <description>SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0</name>
+              <description>core_x_iram0_dram0_dma_sram_category_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1</name>
+              <description>core_x_iram0_dram0_dma_sram_category_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2</name>
+              <description>core_x_iram0_dram0_dma_sram_category_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR</name>
+              <description>core_x_iram0_dram0_dma_sram_splitaddr</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2</name>
+          <description>SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0</name>
+              <description>core_x_iram0_sram_line_0_category_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1</name>
+              <description>core_x_iram0_sram_line_0_category_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2</name>
+              <description>core_x_iram0_sram_line_0_category_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR</name>
+              <description>core_x_iram0_sram_line_0_splitaddr</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3</name>
+          <description>SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0</name>
+              <description>core_x_iram0_sram_line_1_category_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1</name>
+              <description>core_x_iram0_sram_line_1_category_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2</name>
+              <description>core_x_iram0_sram_line_1_category_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR</name>
+              <description>core_x_iram0_sram_line_1_splitaddr</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4</name>
+          <description>SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0</name>
+              <description>core_x_dram0_dma_sram_line_0_category_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1</name>
+              <description>core_x_dram0_dma_sram_line_0_category_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2</name>
+              <description>core_x_dram0_dma_sram_line_0_category_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR</name>
+              <description>core_x_dram0_dma_sram_line_0_splitaddr</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5</name>
+          <description>SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0</name>
+              <description>core_x_dram0_dma_sram_line_1_category_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1</name>
+              <description>core_x_dram0_dma_sram_line_1_category_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2</name>
+              <description>core_x_dram0_dma_sram_line_1_category_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR</name>
+              <description>core_x_dram0_dma_sram_line_1_splitaddr</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_LOCK</name>
+              <description>core_x_iram0_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001C7FFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>core_x_iram0_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>core_x_iram0_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>core_x_iram0_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>core_x_iram0_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0</name>
+              <description>core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS</name>
+              <description>core_x_iram0_pms_constrain_rom_world_1_pms</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_PMS_CONSTRAIN_2</name>
+          <description>SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001C7FFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>core_x_iram0_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>core_x_iram0_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>core_x_iram0_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>core_x_iram0_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0</name>
+              <description>core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS</name>
+              <description>core_x_iram0_pms_constrain_rom_world_0_pms</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_PMS_MONITOR_0</name>
+          <description>SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_LOCK</name>
+              <description>core_0_iram0_pms_monitor_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_PMS_MONITOR_1</name>
+          <description>SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>core_0_iram0_pms_monitor_violate_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN</name>
+              <description>core_0_iram0_pms_monitor_violate_en</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_PMS_MONITOR_2</name>
+          <description>SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>core_0_iram0_pms_monitor_violate_intr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR</name>
+              <description>core_0_iram0_pms_monitor_violate_status_wr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE</name>
+              <description>core_0_iram0_pms_monitor_violate_status_loadstore</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD</name>
+              <description>core_0_iram0_pms_monitor_violate_status_world</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR</name>
+              <description>core_0_iram0_pms_monitor_violate_status_addr</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_DRAM0_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_LOCK</name>
+              <description>core_x_dram0_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_DRAM0_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0FF0FF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>core_x_dram0_pms_constrain_sram_world_0_pms_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>core_x_dram0_pms_constrain_sram_world_0_pms_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>core_x_dram0_pms_constrain_sram_world_0_pms_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>core_x_dram0_pms_constrain_sram_world_0_pms_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>core_x_dram0_pms_constrain_sram_world_1_pms_0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>core_x_dram0_pms_constrain_sram_world_1_pms_1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>core_x_dram0_pms_constrain_sram_world_1_pms_2</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>core_x_dram0_pms_constrain_sram_world_1_pms_3</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS</name>
+              <description>core_x_dram0_pms_constrain_rom_world_0_pms</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS</name>
+              <description>core_x_dram0_pms_constrain_rom_world_1_pms</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_0</name>
+          <description>SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_LOCK</name>
+              <description>core_0_dram0_pms_monitor_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_1</name>
+          <description>SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>core_0_dram0_pms_monitor_violate_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN</name>
+              <description>core_0_dram0_pms_monitor_violate_en</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_2</name>
+          <description>SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>core_0_dram0_pms_monitor_violate_intr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK</name>
+              <description>core_0_dram0_pms_monitor_violate_status_lock</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD</name>
+              <description>core_0_dram0_pms_monitor_violate_status_world</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR</name>
+              <description>core_0_dram0_pms_monitor_violate_status_addr</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_3</name>
+          <description>SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR</name>
+              <description>core_0_dram0_pms_monitor_violate_status_wr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN</name>
+              <description>core_0_dram0_pms_monitor_violate_status_byteen</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_LOCK</name>
+              <description>core_0_pif_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xCF0FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART</name>
+              <description>core_0_pif_pms_constrain_world_0_uart</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1</name>
+              <description>core_0_pif_pms_constrain_world_0_g0spi_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0</name>
+              <description>core_0_pif_pms_constrain_world_0_g0spi_0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO</name>
+              <description>core_0_pif_pms_constrain_world_0_gpio</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2</name>
+              <description>core_0_pif_pms_constrain_world_0_fe2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE</name>
+              <description>core_0_pif_pms_constrain_world_0_fe</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER</name>
+              <description>core_0_pif_pms_constrain_world_0_timer</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC</name>
+              <description>core_0_pif_pms_constrain_world_0_rtc</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX</name>
+              <description>core_0_pif_pms_constrain_world_0_io_mux</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG</name>
+              <description>core_0_pif_pms_constrain_world_0_wdg</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC</name>
+              <description>core_0_pif_pms_constrain_world_0_misc</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C</name>
+              <description>core_0_pif_pms_constrain_world_0_i2c</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1</name>
+              <description>core_0_pif_pms_constrain_world_0_uart1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_2</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFCC30CF3</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT</name>
+              <description>core_0_pif_pms_constrain_world_0_bt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0</name>
+              <description>core_0_pif_pms_constrain_world_0_i2c_ext0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0</name>
+              <description>core_0_pif_pms_constrain_world_0_uhci0</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT</name>
+              <description>core_0_pif_pms_constrain_world_0_rmt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC</name>
+              <description>core_0_pif_pms_constrain_world_0_ledc</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB</name>
+              <description>core_0_pif_pms_constrain_world_0_bb</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP</name>
+              <description>core_0_pif_pms_constrain_world_0_timergroup</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1</name>
+              <description>core_0_pif_pms_constrain_world_0_timergroup1</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER</name>
+              <description>core_0_pif_pms_constrain_world_0_systimer</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_3</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3CC0CC33</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2</name>
+              <description>core_0_pif_pms_constrain_world_0_spi_2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL</name>
+              <description>core_0_pif_pms_constrain_world_0_apb_ctrl</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN</name>
+              <description>core_0_pif_pms_constrain_world_0_can</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1</name>
+              <description>core_0_pif_pms_constrain_world_0_i2s1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT</name>
+              <description>core_0_pif_pms_constrain_world_0_rwbt</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC</name>
+              <description>core_0_pif_pms_constrain_world_0_wifimac</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR</name>
+              <description>core_0_pif_pms_constrain_world_0_pwr</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_4</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFF3FC</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP</name>
+              <description>core_0_pif_pms_constrain_world_0_usb_wrap</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI</name>
+              <description>core_0_pif_pms_constrain_world_0_crypto_peri</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA</name>
+              <description>core_0_pif_pms_constrain_world_0_crypto_dma</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC</name>
+              <description>core_0_pif_pms_constrain_world_0_apb_adc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR</name>
+              <description>core_0_pif_pms_constrain_world_0_bt_pwr</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE</name>
+              <description>core_0_pif_pms_constrain_world_0_usb_device</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM</name>
+              <description>core_0_pif_pms_constrain_world_0_system</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE</name>
+              <description>core_0_pif_pms_constrain_world_0_sensitive</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT</name>
+              <description>core_0_pif_pms_constrain_world_0_interrupt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY</name>
+              <description>core_0_pif_pms_constrain_world_0_dma_copy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG</name>
+              <description>core_0_pif_pms_constrain_world_0_cache_config</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD</name>
+              <description>core_0_pif_pms_constrain_world_0_ad</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO</name>
+              <description>core_0_pif_pms_constrain_world_0_dio</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER</name>
+              <description>core_0_pif_pms_constrain_world_0_world_controller</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_5</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xCF0FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART</name>
+              <description>core_0_pif_pms_constrain_world_1_uart</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1</name>
+              <description>core_0_pif_pms_constrain_world_1_g0spi_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0</name>
+              <description>core_0_pif_pms_constrain_world_1_g0spi_0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO</name>
+              <description>core_0_pif_pms_constrain_world_1_gpio</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2</name>
+              <description>core_0_pif_pms_constrain_world_1_fe2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE</name>
+              <description>core_0_pif_pms_constrain_world_1_fe</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER</name>
+              <description>core_0_pif_pms_constrain_world_1_timer</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC</name>
+              <description>core_0_pif_pms_constrain_world_1_rtc</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX</name>
+              <description>core_0_pif_pms_constrain_world_1_io_mux</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG</name>
+              <description>core_0_pif_pms_constrain_world_1_wdg</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC</name>
+              <description>core_0_pif_pms_constrain_world_1_misc</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C</name>
+              <description>core_0_pif_pms_constrain_world_1_i2c</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1</name>
+              <description>core_0_pif_pms_constrain_world_1_uart1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_6</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFCC30CF3</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT</name>
+              <description>core_0_pif_pms_constrain_world_1_bt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0</name>
+              <description>core_0_pif_pms_constrain_world_1_i2c_ext0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0</name>
+              <description>core_0_pif_pms_constrain_world_1_uhci0</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT</name>
+              <description>core_0_pif_pms_constrain_world_1_rmt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC</name>
+              <description>core_0_pif_pms_constrain_world_1_ledc</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB</name>
+              <description>core_0_pif_pms_constrain_world_1_bb</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP</name>
+              <description>core_0_pif_pms_constrain_world_1_timergroup</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1</name>
+              <description>core_0_pif_pms_constrain_world_1_timergroup1</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER</name>
+              <description>core_0_pif_pms_constrain_world_1_systimer</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_7</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3CC0CC33</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2</name>
+              <description>core_0_pif_pms_constrain_world_1_spi_2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL</name>
+              <description>core_0_pif_pms_constrain_world_1_apb_ctrl</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN</name>
+              <description>core_0_pif_pms_constrain_world_1_can</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1</name>
+              <description>core_0_pif_pms_constrain_world_1_i2s1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT</name>
+              <description>core_0_pif_pms_constrain_world_1_rwbt</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC</name>
+              <description>core_0_pif_pms_constrain_world_1_wifimac</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR</name>
+              <description>core_0_pif_pms_constrain_world_1_pwr</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_8</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFF3FC</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP</name>
+              <description>core_0_pif_pms_constrain_world_1_usb_wrap</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI</name>
+              <description>core_0_pif_pms_constrain_world_1_crypto_peri</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA</name>
+              <description>core_0_pif_pms_constrain_world_1_crypto_dma</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC</name>
+              <description>core_0_pif_pms_constrain_world_1_apb_adc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR</name>
+              <description>core_0_pif_pms_constrain_world_1_bt_pwr</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE</name>
+              <description>core_0_pif_pms_constrain_world_1_usb_device</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM</name>
+              <description>core_0_pif_pms_constrain_world_1_system</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE</name>
+              <description>core_0_pif_pms_constrain_world_1_sensitive</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT</name>
+              <description>core_0_pif_pms_constrain_world_1_interrupt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY</name>
+              <description>core_0_pif_pms_constrain_world_1_dma_copy</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG</name>
+              <description>core_0_pif_pms_constrain_world_1_cache_config</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD</name>
+              <description>core_0_pif_pms_constrain_world_1_ad</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO</name>
+              <description>core_0_pif_pms_constrain_world_1_dio</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER</name>
+              <description>core_0_pif_pms_constrain_world_1_world_controller</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_9</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0</name>
+              <description>core_0_pif_pms_constrain_rtcfast_spltaddr_world_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1</name>
+              <description>core_0_pif_pms_constrain_rtcfast_spltaddr_world_1</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_10</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L</name>
+              <description>core_0_pif_pms_constrain_rtcfast_world_0_l</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H</name>
+              <description>core_0_pif_pms_constrain_rtcfast_world_0_h</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L</name>
+              <description>core_0_pif_pms_constrain_rtcfast_world_1_l</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H</name>
+              <description>core_0_pif_pms_constrain_rtcfast_world_1_h</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_LOCK</name>
+              <description>region_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003FFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_0_AREA_0</name>
+              <description>region_pms_constrain_world_0_area_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_0_AREA_1</name>
+              <description>region_pms_constrain_world_0_area_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_0_AREA_2</name>
+              <description>region_pms_constrain_world_0_area_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_0_AREA_3</name>
+              <description>region_pms_constrain_world_0_area_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_0_AREA_4</name>
+              <description>region_pms_constrain_world_0_area_4</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_0_AREA_5</name>
+              <description>region_pms_constrain_world_0_area_5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_0_AREA_6</name>
+              <description>region_pms_constrain_world_0_area_6</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_2</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_2_REG</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003FFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_1_AREA_0</name>
+              <description>region_pms_constrain_world_1_area_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_1_AREA_1</name>
+              <description>region_pms_constrain_world_1_area_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_1_AREA_2</name>
+              <description>region_pms_constrain_world_1_area_2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_1_AREA_3</name>
+              <description>region_pms_constrain_world_1_area_3</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_1_AREA_4</name>
+              <description>region_pms_constrain_world_1_area_4</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_1_AREA_5</name>
+              <description>region_pms_constrain_world_1_area_5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_WORLD_1_AREA_6</name>
+              <description>region_pms_constrain_world_1_area_6</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_3</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_3_REG</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_ADDR_0</name>
+              <description>region_pms_constrain_addr_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_4</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_4_REG</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_ADDR_1</name>
+              <description>region_pms_constrain_addr_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_5</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_5_REG</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_ADDR_2</name>
+              <description>region_pms_constrain_addr_2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_6</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_6_REG</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_ADDR_3</name>
+              <description>region_pms_constrain_addr_3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_7</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_7_REG</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_ADDR_4</name>
+              <description>region_pms_constrain_addr_4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_8</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_8_REG</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_ADDR_5</name>
+              <description>region_pms_constrain_addr_5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_9</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_9_REG</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_ADDR_6</name>
+              <description>region_pms_constrain_addr_6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION_PMS_CONSTRAIN_10</name>
+          <description>SENSITIVE_REGION_PMS_CONSTRAIN_10_REG</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION_PMS_CONSTRAIN_ADDR_7</name>
+              <description>region_pms_constrain_addr_7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_0</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_LOCK</name>
+              <description>core_0_pif_pms_monitor_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_1</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>core_0_pif_pms_monitor_violate_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_EN</name>
+              <description>core_0_pif_pms_monitor_violate_en</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_2</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>core_0_pif_pms_monitor_violate_intr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0</name>
+              <description>core_0_pif_pms_monitor_violate_status_hport_0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE</name>
+              <description>core_0_pif_pms_monitor_violate_status_hsize</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE</name>
+              <description>core_0_pif_pms_monitor_violate_status_hwrite</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD</name>
+              <description>core_0_pif_pms_monitor_violate_status_hworld</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_3</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR</name>
+              <description>core_0_pif_pms_monitor_violate_status_haddr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_4</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR</name>
+              <description>core_0_pif_pms_monitor_nonword_violate_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN</name>
+              <description>core_0_pif_pms_monitor_nonword_violate_en</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_5</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR</name>
+              <description>core_0_pif_pms_monitor_nonword_violate_intr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE</name>
+              <description>core_0_pif_pms_monitor_nonword_violate_status_hsize</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD</name>
+              <description>core_0_pif_pms_monitor_nonword_violate_status_hworld</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_6</name>
+          <description>SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR</name>
+              <description>core_0_pif_pms_monitor_nonword_violate_status_haddr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_0</name>
+          <description>SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_LOCK</name>
+              <description>backup_bus_pms_constrain_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_1</name>
+          <description>SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xCF0FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_UART</name>
+              <description>backup_bus_pms_constrain_uart</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1</name>
+              <description>backup_bus_pms_constrain_g0spi_1</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0</name>
+              <description>backup_bus_pms_constrain_g0spi_0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_GPIO</name>
+              <description>backup_bus_pms_constrain_gpio</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_FE2</name>
+              <description>backup_bus_pms_constrain_fe2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_FE</name>
+              <description>backup_bus_pms_constrain_fe</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_TIMER</name>
+              <description>backup_bus_pms_constrain_timer</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_RTC</name>
+              <description>backup_bus_pms_constrain_rtc</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_IO_MUX</name>
+              <description>backup_bus_pms_constrain_io_mux</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_WDG</name>
+              <description>backup_bus_pms_constrain_wdg</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_MISC</name>
+              <description>backup_bus_pms_constrain_misc</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_I2C</name>
+              <description>backup_bus_pms_constrain_i2c</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_UART1</name>
+              <description>backup_bus_pms_constrain_uart1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_2</name>
+          <description>SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFCC30CF3</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_BT</name>
+              <description>backup_bus_pms_constrain_bt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0</name>
+              <description>backup_bus_pms_constrain_i2c_ext0</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_UHCI0</name>
+              <description>backup_bus_pms_constrain_uhci0</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_RMT</name>
+              <description>backup_bus_pms_constrain_rmt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_LEDC</name>
+              <description>backup_bus_pms_constrain_ledc</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_BB</name>
+              <description>backup_bus_pms_constrain_bb</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP</name>
+              <description>backup_bus_pms_constrain_timergroup</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1</name>
+              <description>backup_bus_pms_constrain_timergroup1</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER</name>
+              <description>backup_bus_pms_constrain_systimer</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_3</name>
+          <description>SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3CC0CC33</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SPI_2</name>
+              <description>backup_bus_pms_constrain_spi_2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL</name>
+              <description>backup_bus_pms_constrain_apb_ctrl</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_CAN</name>
+              <description>backup_bus_pms_constrain_can</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_I2S1</name>
+              <description>backup_bus_pms_constrain_i2s1</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_RWBT</name>
+              <description>backup_bus_pms_constrain_rwbt</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC</name>
+              <description>backup_bus_pms_constrain_wifimac</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_PWR</name>
+              <description>backup_bus_pms_constrain_pwr</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_4</name>
+          <description>SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000F3FC</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP</name>
+              <description>backup_bus_pms_constrain_usb_wrap</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI</name>
+              <description>backup_bus_pms_constrain_crypto_peri</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA</name>
+              <description>backup_bus_pms_constrain_crypto_dma</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_APB_ADC</name>
+              <description>backup_bus_pms_constrain_apb_adc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_BT_PWR</name>
+              <description>backup_bus_pms_constrain_bt_pwr</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE</name>
+              <description>backup_bus_pms_constrain_usb_device</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_MONITOR_0</name>
+          <description>SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_LOCK</name>
+              <description>backup_bus_pms_monitor_lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_MONITOR_1</name>
+          <description>SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>backup_bus_pms_monitor_violate_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_EN</name>
+              <description>backup_bus_pms_monitor_violate_en</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_MONITOR_2</name>
+          <description>SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>backup_bus_pms_monitor_violate_intr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS</name>
+              <description>backup_bus_pms_monitor_violate_status_htrans</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE</name>
+              <description>backup_bus_pms_monitor_violate_status_hsize</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE</name>
+              <description>backup_bus_pms_monitor_violate_status_hwrite</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_MONITOR_3</name>
+          <description>SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR</name>
+              <description>backup_bus_pms_monitor_violate_haddr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>SENSITIVE_CLOCK_GATE_REG_REG</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>SENSITIVE_DATE_REG</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02010200</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SHA</name>
+      <description>SHA (Secure Hash Algorithm) Accelerator</description>
+      <groupName>SHA</groupName>
+      <baseAddress>0x6003B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SHA</name>
+        <value>49</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Initial configuration register.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Sha mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_STRING</name>
+          <description>SHA 512/t configuration register 0.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_STRING</name>
+              <description>Sha t_string (used if and only if mode == SHA_512/t).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_LENGTH</name>
+          <description>SHA 512/t configuration register 1.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LENGTH</name>
+              <description>Sha t_length (used if and only if mode == SHA_512/t).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_BLOCK_NUM</name>
+          <description>DMA configuration register 0.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_BLOCK_NUM</name>
+              <description>Dma-sha block number.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>START</name>
+          <description>Typical SHA configuration register 0.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE</name>
+          <description>Typical SHA configuration register 1.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSY</name>
+          <description>Busy register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Sha busy state. 1'b0: idle. 1'b1: busy.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_START</name>
+          <description>DMA configuration register 1.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_START</name>
+              <description>Start dma-sha.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONTINUE</name>
+          <description>DMA configuration register 2.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CONTINUE</name>
+              <description>Continue dma-sha.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR_IRQ</name>
+          <description>Interrupt clear register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>Clear sha interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IRQ_ENA</name>
+          <description>Interrupt enable register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT_ENA</name>
+              <description>Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200616</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Sha date information/ sha version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>H_MEM[%s]</name>
+          <description>Sha H memory which contains intermediate hash or finial hash.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>Sha M memory which contains message.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI0</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI0</groupName>
+      <baseAddress>0x60003000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x48</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>SPI0 control register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x002C2000</resetValue>
+          <fields>
+            <field>
+              <name>FDUMMY_OUT</name>
+              <description>In the dummy phase the signal level of spi is output by the spi controller.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Apply 2 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTRD_MODE</name>
+              <description>This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DIO</name>
+              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QIO</name>
+              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL1</name>
+          <description>SPI0 control1 register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>SPI0 RX FIFO reset signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>SPI0 control2 register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000021</resetValue>
+          <fields>
+            <field>
+              <name>CS_SETUP_TIME</name>
+              <description>(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_TIME</name>
+              <description>Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_DELAY</name>
+              <description>These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC_RESET</name>
+              <description>The FSM will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI clock division control register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>Set this bit in 1-division mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI0 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI0 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI0 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of  command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_STATUS</name>
+          <description>SPI0 read control register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI0 misc register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRANS_END</name>
+              <description>The bit is used to indicate the  spi0_mst_st controlled transmitting is done.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_END_INT_ENA</name>
+              <description>The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CSPI_ST_TRANS_END</name>
+              <description>The bit is used to indicate the  spi0_slv_st controlled transmitting is done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CSPI_ST_TRANS_END_INT_ENA</name>
+              <description>The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_FCTRL</name>
+          <description>SPI0 bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_REQ_EN</name>
+              <description>For SPI0, Cache access enable, 1: enable, 0:disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_USR_ADDR_4BYTE</name>
+              <description>For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_FLASH_USR_CMD</name>
+              <description>For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_DUAL</name>
+              <description>For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_DUAL</name>
+              <description>For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_QUAD</name>
+              <description>For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_QUAD</name>
+              <description>For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM</name>
+          <description>SPI0 FSM status register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>CSPI_ST</name>
+              <description>The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EM_ST</name>
+              <description>The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CSPI_LOCK_DELAY_TIME</name>
+              <description>The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMING_CALI</name>
+          <description>SPI0 timing calibration register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TIMING_CLK_ENA</name>
+              <description>The bit is used to enable timing adjust clock for all reading operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMING_CALI</name>
+              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTRA_DUMMY_CYCLELEN</name>
+              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_MODE</name>
+          <description>SPI0 input delay mode control register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_NUM</name>
+          <description>SPI0 input delay number control register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOUT_MODE</name>
+          <description>SPI0 output delay mode control register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DOUT0_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT1_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT2_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT3_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>SPI0 clk_gate register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_CLK_SEL</name>
+          <description>SPI0 module clock select register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI01_CLK_SEL</name>
+              <description>When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007130</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI1</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI1</groupName>
+      <baseAddress>0x60002000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CMD</name>
+          <description>SPI1 memory command register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI1_MST_ST</name>
+              <description>The current status of SPI1 master FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MSPI_ST</name>
+              <description>The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_PE</name>
+              <description>In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_HPM</name>
+              <description>Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RES</name>
+              <description>This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_DP</name>
+              <description>Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_CE</name>
+              <description>Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_BE</name>
+              <description>Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_SE</name>
+              <description>Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PP</name>
+              <description>Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WRSR</name>
+              <description>Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RDSR</name>
+              <description>Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RDID</name>
+              <description>Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WRDI</name>
+              <description>Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WREN</name>
+              <description>Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_READ</name>
+              <description>Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI1 address register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_ADDR_VALUE</name>
+              <description>In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>SPI1 control register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x002CA000</resetValue>
+          <fields>
+            <field>
+              <name>FDUMMY_OUT</name>
+              <description>In the dummy phase the signal level of spi is output by the spi controller.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Apply 2 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCS_CRC_EN</name>
+              <description>For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CRC_EN</name>
+              <description>For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTRD_MODE</name>
+              <description>This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESANDRES</name>
+              <description>The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WRSR_2B</name>
+              <description>two bytes data will be written to status register when it is set. 1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DIO</name>
+              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QIO</name>
+              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL1</name>
+          <description>SPI1 control1 register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFC</resetValue>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_DLY_RES</name>
+              <description>After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>SPI1 control2 register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYNC_RESET</name>
+              <description>The FSM will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI1 clock division control register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>reserved</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI1 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DIO</name>
+              <description>In the write operations address phase and read-data phase apply 2 signals.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QIO</name>
+              <description>In the write operations address phase and read-data phase apply 4 signals.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>SPI clock is disable in dummy phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR</name>
+              <description>This bit enable the address phase of an operation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI1 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI1 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of  command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MOSI_DLEN</name>
+          <description>SPI1 send data bit length control register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MOSI_DBITLEN</name>
+              <description>The length in bits of write-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISO_DLEN</name>
+          <description>SPI1 receive data bit length control register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MISO_DBITLEN</name>
+              <description>The length in bits of  read-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_STATUS</name>
+          <description>SPI1 status register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI1 misc register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>CS0_DIS</name>
+              <description>SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS1_DIS</name>
+              <description>SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CRC</name>
+          <description>SPI1 TX CRC data register.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>For SPI1, the value of crc32.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_FCTRL</name>
+          <description>SPI1 bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_USR_ADDR_4BYTE</name>
+              <description>For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_DUAL</name>
+              <description>For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_DUAL</name>
+              <description>For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_QUAD</name>
+              <description>For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_QUAD</name>
+              <description>For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W0</name>
+          <description>SPI1 memory data buffer0</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W1</name>
+          <description>SPI1 memory data buffer1</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W2</name>
+          <description>SPI1 memory data buffer2</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W3</name>
+          <description>SPI1 memory data buffer3</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W4</name>
+          <description>SPI1 memory data buffer4</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W5</name>
+          <description>SPI1 memory data buffer5</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W6</name>
+          <description>SPI1 memory data buffer6</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W7</name>
+          <description>SPI1 memory data buffer7</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W8</name>
+          <description>SPI1 memory data buffer8</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W9</name>
+          <description>SPI1 memory data buffer9</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W10</name>
+          <description>SPI1 memory data buffer10</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W11</name>
+          <description>SPI1 memory data buffer11</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W12</name>
+          <description>SPI1 memory data buffer12</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W13</name>
+          <description>SPI1 memory data buffer13</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W14</name>
+          <description>SPI1 memory data buffer14</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W15</name>
+          <description>SPI1 memory data buffer15</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_WAITI_CTRL</name>
+          <description>SPI1 wait idle control register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000014</resetValue>
+          <fields>
+            <field>
+              <name>WAITI_DUMMY</name>
+              <description>The dummy phase enable when wait flash idle (RDSR)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAITI_CMD</name>
+              <description>The command to wait flash idle(RDSR).</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAITI_DUMMY_CYCLELEN</name>
+              <description>The dummy cycle length when wait flash idle(RDSR).</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_SUS_CTRL</name>
+          <description>SPI1 flash suspend control register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08002000</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_PER</name>
+              <description>program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES</name>
+              <description>program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PER_WAIT_EN</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_WAIT_EN</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PES_PER_EN</name>
+              <description>Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_EN</name>
+              <description>Set this bit to enable Auto-suspending function.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PESR_END_MSK</name>
+              <description>The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_SUS_2B</name>
+              <description>1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PER_END_EN</name>
+              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PES_END_EN</name>
+              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUS_TIMEOUT_CNT</name>
+              <description>When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_SUS_CMD</name>
+          <description>SPI1 flash suspend command register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0005757A</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_PER_COMMAND</name>
+              <description>Program/Erase resume command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_COMMAND</name>
+              <description>Program/Erase suspend command.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_PESR_COMMAND</name>
+              <description>Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SUS_STATUS</name>
+          <description>SPI1 flash suspend status register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FLASH_SUS</name>
+              <description>The status of flash suspend, only used in SPI1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_PESR_CMD_2B</name>
+              <description>1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_HPM_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RES_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_DP_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PER_DLY_128</name>
+              <description>Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_DLY_128</name>
+              <description>Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI0_LOCK_EN</name>
+              <description>1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMING_CALI</name>
+          <description>SPI1 timing control register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMING_CALI</name>
+              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTRA_DUMMY_CYCLELEN</name>
+              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>SPI1 interrupt enable register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PES_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WPE_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>SPI1 interrupt clear register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PES_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WPE_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>SPI1 interrupt raw register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PES_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WPE_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>SPI1 interrupt status register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PES_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WPE_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>SPI1 clk_gate register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007170</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI2</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI2</groupName>
+      <baseAddress>0x60024000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x94</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI2</name>
+        <value>19</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CMD</name>
+          <description>Command control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONF_BITLEN</name>
+              <description>Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UPDATE</name>
+              <description>Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address value register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_ADDR_VALUE</name>
+              <description>Address to slave. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>SPI control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003C0000</resetValue>
+          <fields>
+            <field>
+              <name>DUMMY_OUT</name>
+              <description>In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD_POL</name>
+              <description>SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP_POL</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_BIT_ORDER</name>
+              <description>In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WR_BIT_ORDER</name>
+              <description>In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI clock control register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80003043</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKDIV_PRE</name>
+              <description>In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI USER control register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x800000C0</resetValue>
+          <fields>
+            <field>
+              <name>DOUTDIN</name>
+              <description>Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>QPI_MODE</name>
+              <description>Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals. Can be configured in CONF state.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_CONF_NXT</name>
+              <description>1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIO</name>
+              <description>Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR</name>
+              <description>This bit enable the address phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI USER control register 1</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xB8410007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_WFULL_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP_TIME</name>
+              <description>(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_TIME</name>
+              <description>delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI USER control register 2</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x78000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of  command. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_REMPTY_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MS_DLEN</name>
+          <description>SPI data bit length control register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MS_DATA_BITLEN</name>
+              <description>The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI misc register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003E</resetValue>
+          <fields>
+            <field>
+              <name>CS0_DIS</name>
+              <description>SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS1_DIS</name>
+              <description>SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS2_DIS</name>
+              <description>SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS3_DIS</name>
+              <description>SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS4_DIS</name>
+              <description>SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS5_DIS</name>
+              <description>SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_DIS</name>
+              <description>1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_CS_POL</name>
+              <description>In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_CS_POL</name>
+              <description>spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>QUAD_DIN_PIN_SWAP</name>
+              <description>1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_MODE</name>
+          <description>SPI input delay mode configuration</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMING_HCLK_ACTIVE</name>
+              <description>1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_NUM</name>
+          <description>SPI input delay number configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOUT_MODE</name>
+          <description>SPI output delay mode configuration</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DOUT0_MODE</name>
+              <description>The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT1_MODE</name>
+              <description>The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT2_MODE</name>
+              <description>The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT3_MODE</name>
+              <description>The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>SPI DMA control register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_SLV_SEG_TRANS_EN</name>
+              <description>Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_TX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_EOF_EN</name>
+              <description>1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled receive data mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled send data mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_AFIFO_RST</name>
+              <description>Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BUF_AFIFO_RST</name>
+              <description>Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_AFIFO_RST</name>
+              <description>Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ENA</name>
+          <description>SPI DMA interrupt enable register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_ENA</name>
+              <description>The enable bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP2_INT_ENA</name>
+              <description>The enable bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP1_INT_ENA</name>
+              <description>The enable bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_CLR</name>
+          <description>SPI DMA interrupt clear register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_CLR</name>
+              <description>The clear bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_CLR</name>
+              <description>The clear bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_CLR</name>
+              <description>The clear bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_RAW</name>
+          <description>SPI DMA interrupt raw register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_RAW</name>
+              <description>The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP2_INT_RAW</name>
+              <description>The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP1_INT_RAW</name>
+              <description>The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ST</name>
+          <description>SPI DMA interrupt status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_ST</name>
+              <description>The status bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_ST</name>
+              <description>The status bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_ST</name>
+              <description>The status bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_ST</name>
+              <description>The status bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_ST</name>
+              <description>The status bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_ST</name>
+              <description>The status bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_ST</name>
+              <description>The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_ST</name>
+              <description>The status bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_ST</name>
+              <description>The status bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W0</name>
+          <description>SPI CPU-controlled buffer0</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W1</name>
+          <description>SPI CPU-controlled buffer1</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W2</name>
+          <description>SPI CPU-controlled buffer2</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W3</name>
+          <description>SPI CPU-controlled buffer3</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W4</name>
+          <description>SPI CPU-controlled buffer4</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W5</name>
+          <description>SPI CPU-controlled buffer5</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W6</name>
+          <description>SPI CPU-controlled buffer6</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W7</name>
+          <description>SPI CPU-controlled buffer7</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W8</name>
+          <description>SPI CPU-controlled buffer8</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W9</name>
+          <description>SPI CPU-controlled buffer9</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W10</name>
+          <description>SPI CPU-controlled buffer10</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W11</name>
+          <description>SPI CPU-controlled buffer11</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W12</name>
+          <description>SPI CPU-controlled buffer12</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W13</name>
+          <description>SPI CPU-controlled buffer13</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W14</name>
+          <description>SPI CPU-controlled buffer14</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W15</name>
+          <description>SPI CPU-controlled buffer15</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE</name>
+          <description>SPI slave control register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02800000</resetValue>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_MODE_13</name>
+              <description>{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSCK_DATA_OUT</name>
+              <description>It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_MAGIC_VALUE</name>
+              <description>The magic value of BM table in master DMA seg-trans.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Set SPI work mode. 1: slave mode 0: master mode.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOFT_RESET</name>
+              <description>Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USR_CONF</name>
+              <description>1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE1</name>
+          <description>SPI slave control register 1</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_DATA_BITLEN</name>
+              <description>The transferred data bit length in SPI slave FD and HD mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_COMMAND</name>
+              <description>In the slave mode it is the value of command.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_ADDR</name>
+              <description>In the slave mode it is the value of address.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_GATE</name>
+          <description>SPI module clock and register clock control</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_CLK_ACTIVE</name>
+              <description>Set this bit to power on the SPI module clock.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_CLK_SEL</name>
+              <description>This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007220</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SYSTEM</name>
+      <description>System</description>
+      <groupName>SYSTEM</groupName>
+      <baseAddress>0x600C0000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CPU_PERI_CLK_EN</name>
+          <description>cpu_peripheral clock gating register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN_ASSIST_DEBUG</name>
+              <description>reg_clk_en_assist_debug</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN_DEDICATED_GPIO</name>
+              <description>reg_clk_en_dedicated_gpio</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_RST_EN</name>
+          <description>cpu_peripheral reset register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000C0</resetValue>
+          <fields>
+            <field>
+              <name>RST_EN_ASSIST_DEBUG</name>
+              <description>reg_rst_en_assist_debug</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_EN_DEDICATED_GPIO</name>
+              <description>reg_rst_en_dedicated_gpio</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PER_CONF</name>
+          <description>cpu clock config register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000C</resetValue>
+          <fields>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <description>reg_cpuperiod_sel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FREQ_SEL</name>
+              <description>reg_pll_freq_sel</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_WAIT_MODE_FORCE_ON</name>
+              <description>reg_cpu_wait_mode_force_on</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_WAITI_DELAY_NUM</name>
+              <description>reg_cpu_waiti_delay_num</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_PD_MASK</name>
+          <description>memory power down mask register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>LSLP_MEM_PD_MASK</name>
+              <description>reg_lslp_mem_pd_mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_CLK_EN0</name>
+          <description>peripheral clock gating register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xF9C1E06F</resetValue>
+          <fields>
+            <field>
+              <name>TIMERS_CLK_EN</name>
+              <description>reg_timers_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI01_CLK_EN</name>
+              <description>reg_spi01_clk_en</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_CLK_EN</name>
+              <description>reg_uart_clk_en</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDG_CLK_EN</name>
+              <description>reg_wdg_clk_en</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S0_CLK_EN</name>
+              <description>reg_i2s0_clk_en</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CLK_EN</name>
+              <description>reg_uart1_clk_en</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_CLK_EN</name>
+              <description>reg_spi2_clk_en</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT0_CLK_EN</name>
+              <description>reg_ext0_clk_en</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI0_CLK_EN</name>
+              <description>reg_uhci0_clk_en</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_CLK_EN</name>
+              <description>reg_rmt_clk_en</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCNT_CLK_EN</name>
+              <description>reg_pcnt_clk_en</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_CLK_EN</name>
+              <description>reg_ledc_clk_en</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI1_CLK_EN</name>
+              <description>reg_uhci1_clk_en</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_CLK_EN</name>
+              <description>reg_timergroup_clk_en</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_CLK_EN</name>
+              <description>reg_efuse_clk_en</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP1_CLK_EN</name>
+              <description>reg_timergroup1_clk_en</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_CLK_EN</name>
+              <description>reg_spi3_clk_en</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM0_CLK_EN</name>
+              <description>reg_pwm0_clk_en</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT1_CLK_EN</name>
+              <description>reg_ext1_clk_en</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAN_CLK_EN</name>
+              <description>reg_can_clk_en</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM1_CLK_EN</name>
+              <description>reg_pwm1_clk_en</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S1_CLK_EN</name>
+              <description>reg_i2s1_clk_en</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_DMA_CLK_EN</name>
+              <description>reg_spi2_dma_clk_en</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DEVICE_CLK_EN</name>
+              <description>reg_usb_device_clk_en</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_CLK_EN</name>
+              <description>reg_uart_mem_clk_en</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM2_CLK_EN</name>
+              <description>reg_pwm2_clk_en</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM3_CLK_EN</name>
+              <description>reg_pwm3_clk_en</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_DMA_CLK_EN</name>
+              <description>reg_spi3_dma_clk_en</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_CLK_EN</name>
+              <description>reg_apb_saradc_clk_en</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_CLK_EN</name>
+              <description>reg_systimer_clk_en</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_ARB_CLK_EN</name>
+              <description>reg_adc2_arb_clk_en</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI4_CLK_EN</name>
+              <description>reg_spi4_clk_en</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_CLK_EN1</name>
+          <description>peripheral clock gating register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>CRYPTO_AES_CLK_EN</name>
+              <description>reg_crypto_aes_clk_en</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_SHA_CLK_EN</name>
+              <description>reg_crypto_sha_clk_en</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_RSA_CLK_EN</name>
+              <description>reg_crypto_rsa_clk_en</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_DS_CLK_EN</name>
+              <description>reg_crypto_ds_clk_en</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_HMAC_CLK_EN</name>
+              <description>reg_crypto_hmac_clk_en</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_CLK_EN</name>
+              <description>reg_dma_clk_en</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_HOST_CLK_EN</name>
+              <description>reg_sdio_host_clk_en</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CAM_CLK_EN</name>
+              <description>reg_lcd_cam_clk_en</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART2_CLK_EN</name>
+              <description>reg_uart2_clk_en</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_EN</name>
+              <description>reg_tsens_clk_en</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_RST_EN0</name>
+          <description>reserved</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMERS_RST</name>
+              <description>reg_timers_rst</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI01_RST</name>
+              <description>reg_spi01_rst</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RST</name>
+              <description>reg_uart_rst</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDG_RST</name>
+              <description>reg_wdg_rst</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S0_RST</name>
+              <description>reg_i2s0_rst</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_RST</name>
+              <description>reg_uart1_rst</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_RST</name>
+              <description>reg_spi2_rst</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT0_RST</name>
+              <description>reg_ext0_rst</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI0_RST</name>
+              <description>reg_uhci0_rst</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_RST</name>
+              <description>reg_rmt_rst</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCNT_RST</name>
+              <description>reg_pcnt_rst</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_RST</name>
+              <description>reg_ledc_rst</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI1_RST</name>
+              <description>reg_uhci1_rst</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_RST</name>
+              <description>reg_timergroup_rst</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_RST</name>
+              <description>reg_efuse_rst</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP1_RST</name>
+              <description>reg_timergroup1_rst</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_RST</name>
+              <description>reg_spi3_rst</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM0_RST</name>
+              <description>reg_pwm0_rst</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT1_RST</name>
+              <description>reg_ext1_rst</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAN_RST</name>
+              <description>reg_can_rst</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM1_RST</name>
+              <description>reg_pwm1_rst</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S1_RST</name>
+              <description>reg_i2s1_rst</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_DMA_RST</name>
+              <description>reg_spi2_dma_rst</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DEVICE_RST</name>
+              <description>reg_usb_device_rst</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_RST</name>
+              <description>reg_uart_mem_rst</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM2_RST</name>
+              <description>reg_pwm2_rst</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM3_RST</name>
+              <description>reg_pwm3_rst</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_DMA_RST</name>
+              <description>reg_spi3_dma_rst</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_RST</name>
+              <description>reg_apb_saradc_rst</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_RST</name>
+              <description>reg_systimer_rst</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_ARB_RST</name>
+              <description>reg_adc2_arb_rst</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI4_RST</name>
+              <description>reg_spi4_rst</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_RST_EN1</name>
+          <description>peripheral reset register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001FE</resetValue>
+          <fields>
+            <field>
+              <name>CRYPTO_AES_RST</name>
+              <description>reg_crypto_aes_rst</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_SHA_RST</name>
+              <description>reg_crypto_sha_rst</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_RSA_RST</name>
+              <description>reg_crypto_rsa_rst</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_DS_RST</name>
+              <description>reg_crypto_ds_rst</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_HMAC_RST</name>
+              <description>reg_crypto_hmac_rst</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RST</name>
+              <description>reg_dma_rst</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_HOST_RST</name>
+              <description>reg_sdio_host_rst</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CAM_RST</name>
+              <description>reg_lcd_cam_rst</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART2_RST</name>
+              <description>reg_uart2_rst</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_RST</name>
+              <description>reg_tsens_rst</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_LPCK_DIV_INT</name>
+          <description>clock config register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>BT_LPCK_DIV_NUM</name>
+              <description>reg_bt_lpck_div_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_LPCK_DIV_FRAC</name>
+          <description>clock config register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02001001</resetValue>
+          <fields>
+            <field>
+              <name>BT_LPCK_DIV_B</name>
+              <description>reg_bt_lpck_div_b</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_LPCK_DIV_A</name>
+              <description>reg_bt_lpck_div_a</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_RTC_SLOW</name>
+              <description>reg_lpclk_sel_rtc_slow</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_8M</name>
+              <description>reg_lpclk_sel_8m</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL</name>
+              <description>reg_lpclk_sel_xtal</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL32K</name>
+              <description>reg_lpclk_sel_xtal32k</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_RTC_EN</name>
+              <description>reg_lpclk_rtc_en</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0</name>
+          <description>interrupt generate register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0</name>
+              <description>reg_cpu_intr_from_cpu_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1</name>
+          <description>interrupt generate register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1</name>
+              <description>reg_cpu_intr_from_cpu_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2</name>
+          <description>interrupt generate register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2</name>
+              <description>reg_cpu_intr_from_cpu_2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3</name>
+          <description>interrupt generate register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3</name>
+              <description>reg_cpu_intr_from_cpu_3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_PD_CTRL</name>
+          <description>rsa memory power control register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RSA_MEM_PD</name>
+              <description>reg_rsa_mem_pd</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PU</name>
+              <description>reg_rsa_mem_force_pu</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PD</name>
+              <description>reg_rsa_mem_force_pd</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_CTRL</name>
+          <description>edma clcok and reset register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>EDMA_CLK_ON</name>
+              <description>reg_edma_clk_on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EDMA_RESET</name>
+              <description>reg_edma_reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CONTROL</name>
+          <description>cache control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_CLK_ON</name>
+              <description>reg_icache_clk_on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_RESET</name>
+              <description>reg_icache_reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_CLK_ON</name>
+              <description>reg_dcache_clk_on</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_RESET</name>
+              <description>reg_dcache_reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL</name>
+          <description>SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_SPI_MANUAL_ENCRYPT</name>
+              <description>reg_enable_spi_manual_encrypt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_DB_ENCRYPT</name>
+              <description>reg_enable_download_db_encrypt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_G0CB_DECRYPT</name>
+              <description>reg_enable_download_g0cb_decrypt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>reg_enable_download_manual_encrypt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_FASTMEM_CONFIG</name>
+          <description>fast memory config register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7FF00000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_MEM_CRC_START</name>
+              <description>reg_rtc_mem_crc_start</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_ADDR</name>
+              <description>reg_rtc_mem_crc_addr</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_LEN</name>
+              <description>reg_rtc_mem_crc_len</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_FINISH</name>
+              <description>reg_rtc_mem_crc_finish</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_FASTMEM_CRC</name>
+          <description>reserved</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_MEM_CRC_RES</name>
+              <description>reg_rtc_mem_crc_res</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDUNDANT_ECO_CTRL</name>
+          <description>eco register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDUNDANT_ECO_DRIVE</name>
+              <description>reg_redundant_eco_drive</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDUNDANT_ECO_RESULT</name>
+              <description>reg_redundant_eco_result</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock gating register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSCLK_CONF</name>
+          <description>system clock config register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PRE_DIV_CNT</name>
+              <description>reg_pre_div_cnt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOC_CLK_SEL</name>
+              <description>reg_soc_clk_sel</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_XTAL_FREQ</name>
+              <description>reg_clk_xtal_freq</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLK_DIV_EN</name>
+              <description>reg_clk_div_en</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_PVT</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>MEM_PATH_LEN</name>
+              <description>reg_mem_path_len</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_ERR_CNT_CLR</name>
+              <description>reg_mem_err_cnt_clr</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MONITOR_EN</name>
+              <description>reg_mem_pvt_monitor_en</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TIMING_ERR_CNT</name>
+              <description>reg_mem_timing_err_cnt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_VT_SEL</name>
+              <description>reg_mem_vt_sel</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_LVT_CONF</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>COMB_PATH_LEN_LVT</name>
+              <description>reg_comb_path_len_lvt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMB_ERR_CNT_CLR_LVT</name>
+              <description>reg_comb_err_cnt_clr_lvt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COMB_PVT_MONITOR_EN_LVT</name>
+              <description>reg_comb_pvt_monitor_en_lvt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_NVT_CONF</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>COMB_PATH_LEN_NVT</name>
+              <description>reg_comb_path_len_nvt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMB_ERR_CNT_CLR_NVT</name>
+              <description>reg_comb_err_cnt_clr_nvt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COMB_PVT_MONITOR_EN_NVT</name>
+              <description>reg_comb_pvt_monitor_en_nvt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_HVT_CONF</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>COMB_PATH_LEN_HVT</name>
+              <description>reg_comb_path_len_hvt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMB_ERR_CNT_CLR_HVT</name>
+              <description>reg_comb_err_cnt_clr_hvt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COMB_PVT_MONITOR_EN_HVT</name>
+              <description>reg_comb_pvt_monitor_en_hvt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE0</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE0</name>
+              <description>reg_comb_timing_err_cnt_lvt_site0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE0</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE0</name>
+              <description>reg_comb_timing_err_cnt_nvt_site0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE0</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE0</name>
+              <description>reg_comb_timing_err_cnt_hvt_site0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE1</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE1</name>
+              <description>reg_comb_timing_err_cnt_lvt_site1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE1</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE1</name>
+              <description>reg_comb_timing_err_cnt_nvt_site1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE1</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE1</name>
+              <description>reg_comb_timing_err_cnt_hvt_site1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE2</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE2</name>
+              <description>reg_comb_timing_err_cnt_lvt_site2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE2</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE2</name>
+              <description>reg_comb_timing_err_cnt_nvt_site2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE2</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE2</name>
+              <description>reg_comb_timing_err_cnt_hvt_site2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE3</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE3</name>
+              <description>reg_comb_timing_err_cnt_lvt_site3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE3</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE3</name>
+              <description>reg_comb_timing_err_cnt_nvt_site3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE3</name>
+          <description>mem pvt register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE3</name>
+              <description>reg_comb_timing_err_cnt_hvt_site3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTEM_REG_DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007150</resetValue>
+          <fields>
+            <field>
+              <name>SYSTEM_REG_DATE</name>
+              <description>reg_system_reg_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SYSTIMER</name>
+      <description>System Timer</description>
+      <groupName>SYSTIMER</groupName>
+      <baseAddress>0x60023000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x78</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSTIMER_TARGET0</name>
+        <value>37</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET1</name>
+        <value>38</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET2</name>
+        <value>39</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF</name>
+          <description>SYSTIMER_CONF.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x46000000</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_CLK_FO</name>
+              <description>systimer clock force on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_WORK_EN</name>
+              <description>target2 work enable</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_WORK_EN</name>
+              <description>target1 work enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_WORK_EN</name>
+              <description>target0 work enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE1_STALL_EN</name>
+              <description>If timer unit1 is stalled when core1 stalled</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE0_STALL_EN</name>
+              <description>If timer unit1 is stalled when core0 stalled</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE1_STALL_EN</name>
+              <description>If timer unit0 is stalled when core1 stalled</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE0_STALL_EN</name>
+              <description>If timer unit0 is stalled when core0 stalled</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_WORK_EN</name>
+              <description>timer unit1 work enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_WORK_EN</name>
+              <description>timer unit0 work enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>register file clk gating</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_OP</name>
+          <description>SYSTIMER_UNIT0_OP.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_VALID</name>
+              <description>reg_timer_unit0_value_valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_UPDATE</name>
+              <description>update timer_unit0</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_OP</name>
+          <description>SYSTIMER_UNIT1_OP.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_VALID</name>
+              <description>timer value is sync and valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_UPDATE</name>
+              <description>update timer unit1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_HI</name>
+          <description>SYSTIMER_UNIT0_LOAD_HI.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_HI</name>
+              <description>timer unit0 load high 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_LO</name>
+          <description>SYSTIMER_UNIT0_LOAD_LO.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_LO</name>
+              <description>timer unit0 load low 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_HI</name>
+          <description>SYSTIMER_UNIT1_LOAD_HI.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_HI</name>
+              <description>timer unit1 load high 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_LO</name>
+          <description>SYSTIMER_UNIT1_LOAD_LO.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_LO</name>
+              <description>timer unit1 load low 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_HI</name>
+          <description>SYSTIMER_TARGET0_HI.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_HI</name>
+              <description>timer taget0 high 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_LO</name>
+          <description>SYSTIMER_TARGET0_LO.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_LO</name>
+              <description>timer taget0 low 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_HI</name>
+          <description>SYSTIMER_TARGET1_HI.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_HI</name>
+              <description>timer taget1 high 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_LO</name>
+          <description>SYSTIMER_TARGET1_LO.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_LO</name>
+              <description>timer taget1 low 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_HI</name>
+          <description>SYSTIMER_TARGET2_HI.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_HI</name>
+              <description>timer taget2 high 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_LO</name>
+          <description>SYSTIMER_TARGET2_LO.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_LO</name>
+              <description>timer taget2 low 32 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_CONF</name>
+          <description>SYSTIMER_TARGET0_CONF.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_PERIOD</name>
+              <description>target0 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_PERIOD_MODE</name>
+              <description>Set target0 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_CONF</name>
+          <description>SYSTIMER_TARGET1_CONF.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_PERIOD</name>
+              <description>target1 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_PERIOD_MODE</name>
+              <description>Set target1 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_CONF</name>
+          <description>SYSTIMER_TARGET2_CONF.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_PERIOD</name>
+              <description>target2 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_PERIOD_MODE</name>
+              <description>Set target2 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_HI</name>
+          <description>SYSTIMER_UNIT0_VALUE_HI.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_HI</name>
+              <description>timer read value high 32bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_LO</name>
+          <description>SYSTIMER_UNIT0_VALUE_LO.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_LO</name>
+              <description>timer read value low 32bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_HI</name>
+          <description>SYSTIMER_UNIT1_VALUE_HI.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_HI</name>
+              <description>timer read value high 32bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_LO</name>
+          <description>SYSTIMER_UNIT1_VALUE_LO.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_LO</name>
+              <description>timer read value low 32bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP0_LOAD</name>
+          <description>SYSTIMER_COMP0_LOAD.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP0_LOAD</name>
+              <description>timer comp0 load value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP1_LOAD</name>
+          <description>SYSTIMER_COMP1_LOAD.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP1_LOAD</name>
+              <description>timer comp1 load value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP2_LOAD</name>
+          <description>SYSTIMER_COMP2_LOAD.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP2_LOAD</name>
+              <description>timer comp2 load value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD</name>
+          <description>SYSTIMER_UNIT0_LOAD.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD</name>
+              <description>timer unit0 load value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD</name>
+          <description>SYSTIMER_UNIT1_LOAD.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD</name>
+              <description>timer unit1 load value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>SYSTIMER_INT_ENA.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ENA</name>
+              <description>interupt0 enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ENA</name>
+              <description>interupt1 enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ENA</name>
+              <description>interupt2 enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>SYSTIMER_INT_RAW.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_RAW</name>
+              <description>interupt0 raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_RAW</name>
+              <description>interupt1 raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_RAW</name>
+              <description>interupt2 raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>SYSTIMER_INT_CLR.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_CLR</name>
+              <description>interupt0 clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_CLR</name>
+              <description>interupt1 clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_CLR</name>
+              <description>interupt2 clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>SYSTIMER_INT_ST.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ST</name>
+              <description>reg_target0_int_st</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ST</name>
+              <description>reg_target1_int_st</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ST</name>
+              <description>reg_target2_int_st</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>SYSTIMER_DATE.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02006171</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TIMG0</name>
+      <description>Timer Group</description>
+      <groupName>TIMG</groupName>
+      <baseAddress>0x6001F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TG0_T0_LEVEL</name>
+        <value>32</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_WDT_LEVEL</name>
+        <value>33</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>T0CONFIG</name>
+          <description>TIMG_T0CONFIG_REG.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002000</resetValue>
+          <fields>
+            <field>
+              <name>USE_XTAL</name>
+              <description>reg_t0_use_xtal.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALARM_EN</name>
+              <description>reg_t0_alarm_en.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIVCNT_RST</name>
+              <description>reg_t0_divcnt_rst.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DIVIDER</name>
+              <description>reg_t0_divider.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTORELOAD</name>
+              <description>reg_t0_autoreload.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCREASE</name>
+              <description>reg_t0_increase.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>reg_t0_en.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LO</name>
+          <description>TIMG_T0LO_REG.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LO</name>
+              <description>t0_lo</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0HI</name>
+          <description>TIMG_T0HI_REG.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HI</name>
+              <description>t0_hi</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0UPDATE</name>
+          <description>TIMG_T0UPDATE_REG.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UPDATE</name>
+              <description>t0_update</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMLO</name>
+          <description>TIMG_T0ALARMLO_REG.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_LO</name>
+              <description>reg_t0_alarm_lo.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMHI</name>
+          <description>TIMG_T0ALARMHI_REG.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_HI</name>
+              <description>reg_t0_alarm_hi.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADLO</name>
+          <description>TIMG_T0LOADLO_REG.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_LO</name>
+              <description>reg_t0_load_lo.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADHI</name>
+          <description>TIMG_T0LOADHI_REG.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_HI</name>
+              <description>reg_t0_load_hi.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOAD</name>
+          <description>TIMG_T0LOAD_REG.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD</name>
+              <description>t0_load</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>TIMG_WDTCONFIG0_REG.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0004C000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>reg_wdt_appcpu_reset_en.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>reg_wdt_procpu_reset_en.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>reg_wdt_flashboot_mod_en.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>reg_wdt_sys_reset_length.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>reg_wdt_cpu_reset_length.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_USE_XTAL</name>
+              <description>reg_wdt_use_xtal.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CONF_UPDATE_EN</name>
+              <description>reg_wdt_conf_update_en.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>reg_wdt_stg3.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>reg_wdt_stg2.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>reg_wdt_stg1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>reg_wdt_stg0.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>reg_wdt_en.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>TIMG_WDTCONFIG1_REG.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_DIVCNT_RST</name>
+              <description>reg_wdt_divcnt_rst.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_CLK_PRESCALE</name>
+              <description>reg_wdt_clk_prescale.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>TIMG_WDTCONFIG2_REG.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x018CBA80</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>reg_wdt_stg0_hold.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>TIMG_WDTCONFIG3_REG.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>reg_wdt_stg1_hold.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>TIMG_WDTCONFIG4_REG.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>reg_wdt_stg2_hold.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG5</name>
+          <description>TIMG_WDTCONFIG5_REG.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>reg_wdt_stg3_hold.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>TIMG_WDTFEED_REG.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>wdt_feed</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>TIMG_WDTWPROTECT_REG.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>reg_wdt_wkey.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG</name>
+          <description>TIMG_RTCCALICFG_REG.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_START_CYCLING</name>
+              <description>reg_rtc_cali_start_cycling.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_CLK_SEL</name>
+              <description>reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_RDY</name>
+              <description>rtc_cali_rdy</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_MAX</name>
+              <description>reg_rtc_cali_max.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_START</name>
+              <description>reg_rtc_cali_start.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG1</name>
+          <description>TIMG_RTCCALICFG1_REG.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_CALI_CYCLING_DATA_VLD</name>
+              <description>rtc_cali_cycling_data_vld</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_VALUE</name>
+              <description>rtc_cali_value</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_TIMERS</name>
+          <description>INT_ENA_TIMG_REG</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ENA</name>
+              <description>t0_int_ena</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>wdt_int_ena</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_TIMERS</name>
+          <description>INT_RAW_TIMG_REG</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_RAW</name>
+              <description>t0_int_raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>wdt_int_raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_TIMERS</name>
+          <description>INT_ST_TIMG_REG</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ST</name>
+              <description>t0_int_st</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>wdt_int_st</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_TIMERS</name>
+          <description>INT_CLR_TIMG_REG</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_CLR</name>
+              <description>t0_int_clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>wdt_int_clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG2</name>
+          <description>TIMG_RTCCALICFG2_REG.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFF98</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_TIMEOUT</name>
+              <description>timeoutindicator</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_RST_CNT</name>
+              <description>reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_THRES</name>
+              <description>reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NTIMG_DATE</name>
+          <description>TIMG_NTIMG_DATE_REG.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02006191</resetValue>
+          <fields>
+            <field>
+              <name>NTIMGS_DATE</name>
+              <description>reg_ntimers_date.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGCLK</name>
+          <description>TIMG_REGCLK_REG.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60000000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CLK_IS_ACTIVE</name>
+              <description>reg_wdt_clk_is_active.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_CLK_IS_ACTIVE</name>
+              <description>reg_timer_clk_is_active.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMG0">
+      <name>TIMG1</name>
+      <description>Timer Group</description>
+      <baseAddress>0x60020000</baseAddress>
+      <interrupt>
+        <name>TG1_T0_LEVEL</name>
+        <value>34</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_WDT_LEVEL</name>
+        <value>35</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TWAI</name>
+      <description>Two-Wire Automotive Interface</description>
+      <groupName>TWAI</groupName>
+      <baseAddress>0x6002B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x6C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TWAI</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Mode Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RESET_MODE</name>
+              <description>This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LISTEN_ONLY_MODE</name>
+              <description>1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SELF_TEST_MODE</name>
+              <description>1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_MODE</name>
+              <description>This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>Command Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_REQ</name>
+              <description>Set the bit to 1 to allow the driving nodes start transmission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ABORT_TX</name>
+              <description>Set the bit to 1 to cancel a pending transmission request.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RELEASE_BUF</name>
+              <description>Set the bit to 1 to release the RX buffer.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CLR_OVERRUN</name>
+              <description>Set the bit to 1 to clear the data overrun status bit.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SELF_RX_REQ</name>
+              <description>Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_BUF_ST</name>
+              <description>1: The data in the RX buffer is not empty, with at least one received data packet.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN_ST</name>
+              <description>1: The RX FIFO is full and data overrun has occurred.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BUF_ST</name>
+              <description>1: The TX buffer is empty, the CPU may write a message into it.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_COMPLETE</name>
+              <description>1: The TWAI controller has successfully received a packet from the bus.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_ST</name>
+              <description>1: The TWAI Controller is receiving a message from the bus.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_ST</name>
+              <description>1: The TWAI Controller is transmitting a message to the bus.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_ST</name>
+              <description>1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_OFF_ST</name>
+              <description>1: In bus-off status, the TWAI Controller is no longer involved in bus activities.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MISS_ST</name>
+              <description>This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_INT_ST</name>
+              <description>Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_INT_ST</name>
+              <description>Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_WARN_INT_ST</name>
+              <description>Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN_INT_ST</name>
+              <description>Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ST</name>
+              <description>Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST_INT_ST</name>
+              <description>Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ST</name>
+              <description>Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt Enable Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_INT_ENA</name>
+              <description>Set this bit to 1 to enable receive interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_INT_ENA</name>
+              <description>Set this bit to 1 to enable transmit interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WARN_INT_ENA</name>
+              <description>Set this bit to 1 to enable error warning interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVERRUN_INT_ENA</name>
+              <description>Set this bit to 1 to enable data overrun interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ENA</name>
+              <description>Set this bit to 1 to enable error passive interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_LOST_INT_ENA</name>
+              <description>Set this bit to 1 to enable arbitration lost interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ENA</name>
+              <description>Set this bit to 1 to enable error interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_0</name>
+          <description>Bus Timing Register 0</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BAUD_PRESC</name>
+              <description>Baud Rate Prescaler, determines the frequency dividing ratio.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC_JUMP_WIDTH</name>
+              <description>Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_1</name>
+          <description>Bus Timing Register 1</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_SEG1</name>
+              <description>The width of PBS1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SEG2</name>
+              <description>The width of PBS2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SAMP</name>
+              <description>The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_LOST_CAP</name>
+          <description>Arbitration Lost Capture Register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ARB_LOST_CAP</name>
+              <description>This register contains information about the bit position of lost arbitration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_CODE_CAP</name>
+          <description>Error Code Capture Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ECC_SEGMENT</name>
+              <description>This register contains information about the location of errors, see Table 181 for details.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_DIRECTION</name>
+              <description>This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_TYPE</name>
+              <description>This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_WARNING_LIMIT</name>
+          <description>Error Warning Limit Register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000060</resetValue>
+          <fields>
+            <field>
+              <name>ERR_WARNING_LIMIT</name>
+              <description>Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_ERR_CNT</name>
+          <description>Receive Error Counter Register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CNT</name>
+              <description>The RX error counter register, reflects value changes under reception status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_ERR_CNT</name>
+          <description>Transmit Error Counter Register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_ERR_CNT</name>
+              <description>The TX error counter register, reflects value changes under transmission status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_0</name>
+          <description>Data register 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_0</name>
+              <description>In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_1</name>
+          <description>Data register 1</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_1</name>
+              <description>In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_2</name>
+          <description>Data register 2</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_2</name>
+              <description>In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_3</name>
+          <description>Data register 3</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_3</name>
+              <description>In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_4</name>
+          <description>Data register 4</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_4</name>
+              <description>In reset mode, it is acceptance code register 4 with R/W Permission. In operation mode, it stores the 4th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_5</name>
+          <description>Data register 5</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_5</name>
+              <description>In reset mode, it is acceptance code register 5 with R/W Permission. In operation mode, it stores the 5th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_6</name>
+          <description>Data register 6</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_6</name>
+              <description>In reset mode, it is acceptance code register 6 with R/W Permission. In operation mode, it stores the 6th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_7</name>
+          <description>Data register 7</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_7</name>
+              <description>In reset mode, it is acceptance code register 7 with R/W Permission. In operation mode, it stores the 7th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_8</name>
+          <description>Data register 8</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_8</name>
+              <description>In operation mode, it stores the 8th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_9</name>
+          <description>Data register 9</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_9</name>
+              <description>In operation mode, it stores the 9th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_10</name>
+          <description>Data register 10</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_10</name>
+              <description>In operation mode, it stores the 10th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_11</name>
+          <description>Data register 11</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_11</name>
+              <description>In operation mode, it stores the 11th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_12</name>
+          <description>Data register 12</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_12</name>
+              <description>In operation mode, it stores the 12th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_MESSAGE_CNT</name>
+          <description>Receive Message Counter Register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_MESSAGE_COUNTER</name>
+              <description>This register reflects the number of messages available within the RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_DIVIDER</name>
+          <description>Clock Divider register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CD</name>
+              <description>These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLOCK_OFF</name>
+              <description>This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>UART0</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x60000000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x84</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART0</name>
+        <value>21</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>FIFO</name>
+          <description>FIFO data register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RD_BYTE</name>
+              <description>UART 0 accesses FIFO via this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error in the data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error .</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ST</name>
+              <description>This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ST</name>
+              <description>This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ST</name>
+              <description>This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ST</name>
+              <description>This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ST</name>
+              <description>This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ST</name>
+              <description>This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ST</name>
+              <description>This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ST</name>
+              <description>This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ST</name>
+              <description>This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ST</name>
+              <description>This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ST</name>
+              <description>This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ST</name>
+              <description>This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ST</name>
+              <description>This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ST</name>
+              <description>This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_full_int_st register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ENA</name>
+              <description>This is the enable bit for txfifo_empty_int_st register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for parity_err_int_st register.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for frm_err_int_st register.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_ovf_int_st register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ENA</name>
+              <description>This is the enable bit for dsr_chg_int_st register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ENA</name>
+              <description>This is the enable bit for cts_chg_int_st register.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ENA</name>
+              <description>This is the enable bit for brk_det_int_st register.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_tout_int_st register.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ENA</name>
+              <description>This is the enable bit for sw_xon_int_st register.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ENA</name>
+              <description>This is the enable bit for sw_xoff_int_st register.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>This is the enable bit for glitch_det_int_st register.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_done_int_st register.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_idle_done_int_st register.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_done_int_st register.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ENA</name>
+              <description>This is the enable bit for rs485_clash_int_st register.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ENA</name>
+              <description>This is the enable bit for at_cmd_char_det_int_st register.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ENA</name>
+              <description>This is the enable bit for uart_wakeup_int_st register.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_full_int_raw interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear txfifo_empty_int_raw interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear parity_err_int_raw interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear frm_err_int_raw interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear rxfifo_ovf_int_raw interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_CLR</name>
+              <description>Set this bit to clear the dsr_chg_int_raw interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear the cts_chg_int_raw interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_CLR</name>
+              <description>Set this bit to clear the brk_det_int_raw interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_tout_int_raw interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_CLR</name>
+              <description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_CLR</name>
+              <description>Set this bit to clear the sw_xoff_int_raw interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Set this bit to clear the glitch_det_int_raw interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_done_int_raw interrupt..</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_idle_done_int_raw interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_done_int_raw interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_parity_err_int_raw interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_frm_err_int_raw interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_CLR</name>
+              <description>Set this bit to clear the rs485_clash_int_raw interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_CLR</name>
+              <description>Set this bit to clear the at_cmd_char_det_int_raw interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_CLR</name>
+              <description>Set this bit to clear the uart_wakeup_int_raw interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV</name>
+          <description>Clock divider configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000002B6</resetValue>
+          <fields>
+            <field>
+              <name>CLKDIV</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRAG</name>
+              <description>The decimal part of the frequency divider factor.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_FILT</name>
+          <description>Rx Filter configuration</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>GLITCH_FILT</name>
+              <description>when input pulse width is lower than this value, the pulse is ignored.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_FILT_EN</name>
+              <description>Set this bit to enable Rx signal filter.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>UART status register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xE000C000</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>Stores the byte number of valid data in Rx-FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSRN</name>
+              <description>The register represent the level value of the internal uart dsr signal.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTSN</name>
+              <description>This register represent the level value of the internal uart cts signal.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXD</name>
+              <description>This register represent the  level value of the internal uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>Stores the byte number of data in Tx-FIFO.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTRN</name>
+              <description>This bit represents the level of the internal uart dtr signal.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTSN</name>
+              <description>This bit represents the level of the internal uart rts signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXD</name>
+              <description>This bit represents the  level of the internal uart txd signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0</name>
+          <description>a</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1000001C</resetValue>
+          <fields>
+            <field>
+              <name>PARITY</name>
+              <description>This register is used to configure the parity check mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_EN</name>
+              <description>Set this bit to enable uart parity check.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIT_NUM</name>
+              <description>This register is used to set the length of data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOP_BIT_NUM</name>
+              <description>This register is used to set the length of  stop bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_RTS</name>
+              <description>This register is used to configure the software rts signal which is used in software flow control.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_DTR</name>
+              <description>This register is used to configure the software dtr signal which is used in software flow control.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_BRK</name>
+              <description>Set this bit to enbale transmitter to  send NULL when the process of sending data is done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_DPLX</name>
+              <description>Set this bit to enable IrDA loopback mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_EN</name>
+              <description>This is the start enable bit for IrDA transmitter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_WCTL</name>
+              <description>1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_INV</name>
+              <description>Set this bit to invert the level of  IrDA transmitter.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_RX_INV</name>
+              <description>Set this bit to invert the level of IrDA receiver.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOPBACK</name>
+              <description>Set this bit to enable uart loopback test mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FLOW_EN</name>
+              <description>Set this bit to enable flow control function for transmitter.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_EN</name>
+              <description>Set this bit to enable IrDA protocol.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>Set this bit to reset the uart receive-FIFO.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_RST</name>
+              <description>Set this bit to reset the uart transmit-FIFO.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXD_INV</name>
+              <description>Set this bit to inverse the level value of uart rxd signal.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_INV</name>
+              <description>Set this bit to inverse the level value of uart cts signal.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_INV</name>
+              <description>Set this bit to inverse the level value of uart dsr signal.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_INV</name>
+              <description>Set this bit to inverse the level value of uart txd signal.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTS_INV</name>
+              <description>Set this bit to inverse the level value of uart rts signal.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTR_INV</name>
+              <description>Set this bit to inverse the level value of uart dtr signal.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WR_MASK</name>
+              <description>1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTOBAUD_EN</name>
+              <description>This is the enable bit for detecting baudrate.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_EN</name>
+              <description>UART memory clock gate enable signal.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>Configuration register 1</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C060</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_THRHD</name>
+              <description>It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_THRHD</name>
+              <description>It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIS_RX_DAT_OVF</name>
+              <description>Disable UART Rx data overflow detect.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_FLOW_DIS</name>
+              <description>Set this bit to stop accumulating idle_cnt when hardware flow control works.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_EN</name>
+              <description>This is the flow enable bit for UART receiver.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_EN</name>
+              <description>This is the enble bit for uart receiver's timeout function.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOWPULSE</name>
+          <description>Autobaud minimum low pulse duration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HIGHPULSE</name>
+          <description>Autobaud minimum high pulse duration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXD_CNT</name>
+          <description>Autobaud edge change count register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXD_EDGE_CNT</name>
+              <description>This register stores the count of rxd edge change. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW_CONF</name>
+          <description>Software flow-control configuration</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_FLOW_CON_EN</name>
+              <description>Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XONOFF_DEL</name>
+              <description>Set this bit to remove flow control char from the received data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XON</name>
+              <description>Set this bit to enable the transmitter to go on sending data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XOFF</name>
+              <description>Set this bit to stop the  transmitter from sending data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XON</name>
+              <description>Set this bit to send Xon char. It is cleared by hardware automatically.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XOFF</name>
+              <description>Set this bit to send Xoff char. It is cleared by hardware automatically.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF</name>
+          <description>Sleep-mode configuration</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000F0</resetValue>
+          <fields>
+            <field>
+              <name>ACTIVE_THRESHOLD</name>
+              <description>The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF0</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000026E0</resetValue>
+          <fields>
+            <field>
+              <name>XOFF_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_CHAR</name>
+              <description>This register stores the Xoff flow control char.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF1</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002200</resetValue>
+          <fields>
+            <field>
+              <name>XON_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XON_CHAR</name>
+              <description>This register stores the Xon flow control char.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXBRK_CONF</name>
+          <description>Tx Break character configuration</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>TX_BRK_NUM</name>
+              <description>This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_CONF</name>
+          <description>Frame-end idle configuration</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040100</resetValue>
+          <fields>
+            <field>
+              <name>RX_IDLE_THRHD</name>
+              <description>It will produce frame end signal when receiver takes more time to receive one byte data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between transfers.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RS485_CONF</name>
+          <description>RS485 mode configuration</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RS485_EN</name>
+              <description>Set this bit to choose the rs485 mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL0_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL1_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485TX_RX_EN</name>
+              <description>Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485RXBY_TX_EN</name>
+              <description>1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_RX_DLY_NUM</name>
+              <description>This register is used to delay the receiver's internal data signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_TX_DLY_NUM</name>
+              <description>This register is used to delay the transmitter's internal data signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_PRECNT</name>
+          <description>Pre-sequence timing configuration</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>PRE_IDLE_NUM</name>
+              <description>This register is used to configure the idle duration time before the first at_cmd is received by receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_POSTCNT</name>
+          <description>Post-sequence timing configuration</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>POST_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between the last at_cmd and the next data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_GAPTOUT</name>
+          <description>Timeout configuration</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>RX_GAP_TOUT</name>
+              <description>This register is used to configure the duration time between the at_cmd chars.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_CHAR</name>
+          <description>AT escape sequence detection configuration</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000032B</resetValue>
+          <fields>
+            <field>
+              <name>AT_CMD_CHAR</name>
+              <description>This register is used to configure the content of at_cmd char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAR_NUM</name>
+              <description>This register is used to configure the num of continuous at_cmd chars received by receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>UART threshold and allocation configuration</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A0012</resetValue>
+          <fields>
+            <field>
+              <name>RX_SIZE</name>
+              <description>This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SIZE</name>
+              <description>This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_THRHD</name>
+              <description>This register is used to configure the maximum amount of data that can be received  when hardware flow control works.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_THRHD</name>
+              <description>This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to force power down UART memory.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>Set this bit to force power up UART memory.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_TX_STATUS</name>
+          <description>Tx-FIFO write and read offset address.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_TX_WADDR</name>
+              <description>This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_RADDR</name>
+              <description>This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_RX_STATUS</name>
+          <description>Rx-FIFO write and read offset address.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00080100</resetValue>
+          <fields>
+            <field>
+              <name>APB_RX_RADDR</name>
+              <description>This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_WADDR</name>
+              <description>This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_STATUS</name>
+          <description>UART transmit and receive status.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST_URX_OUT</name>
+              <description>This is the status register of receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ST_UTX_OUT</name>
+              <description>This is the status register of transmitter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POSPULSE</name>
+          <description>Autobaud high pulse register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>POSEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NEGPULSE</name>
+          <description>Autobaud low pulse register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>NEGEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>UART core clock configuration</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03701000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>The  denominator of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>The numerator of the frequency divider factor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_EN</name>
+              <description>Set this bit to enable UART Tx/Rx clock.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_CORE</name>
+              <description>Write 1 then write 0 to this bit, reset UART Tx/Rx.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SCLK_EN</name>
+              <description>Set this bit to enable UART Tx clock.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SCLK_EN</name>
+              <description>Set this bit to enable UART Rx clock.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit, reset UART Tx.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit, reset UART Rx.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UART Version register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02008270</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ID</name>
+          <description>UART ID register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000500</resetValue>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>This register is used to configure the uart_id.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HIGH_SPEED</name>
+              <description>This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_UPDATE</name>
+              <description>Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <name>UART1</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <baseAddress>0x60010000</baseAddress>
+      <interrupt>
+        <name>UART1</name>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>UHCI0</name>
+      <description>Universal Host Controller Interface</description>
+      <groupName>UHCI</groupName>
+      <baseAddress>0x60014000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x84</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UHCI0</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF0</name>
+          <description>a</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000006E0</resetValue>
+          <fields>
+            <field>
+              <name>TX_RST</name>
+              <description>Write 1, then write 0 to this bit to reset decode state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST</name>
+              <description>Write 1, then write 0 to this bit to reset encode state machine.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_CE</name>
+              <description>Set this bit to link up HCI and UART0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CE</name>
+              <description>Set this bit to link up HCI and UART1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_EN</name>
+              <description>Set this bit to separate the data frame using a special char.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HEAD_EN</name>
+              <description>Set this bit to encode the data packet with a formatting header.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_REC_EN</name>
+              <description>Set this bit to enable UHCI to receive the 16 bit CRC.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_IDLE_EOF_EN</name>
+              <description>If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEN_EOF_EN</name>
+              <description>If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCODE_CRC_EN</name>
+              <description>Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RX_BRK_EOF_EN</name>
+              <description>If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>a</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when there are some errors in EOF in the</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_RAW</name>
+              <description>Soft control int raw bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_RAW</name>
+              <description>Soft control int raw bit.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>a</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ST</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ST</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ST</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ST</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ST</name>
+              <description>a</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_ST</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_ST</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>a</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>a</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>a</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>CHECK_SUM_EN</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_SEQ_EN</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_DISABLE</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAVE_HEAD</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHECK_SUM_RE</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_ACK_NUM_RE</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_SW_START</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_START</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <description>a</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CAUSE</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DECODE_STATE</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE1</name>
+          <description>a</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENCODE_STATE</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESCAPE_CONF</name>
+          <description>a</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>TX_C0_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DB_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_11_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_13_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_C0_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DB_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_11_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_13_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HUNG_CONF</name>
+          <description>a</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00810810</resetValue>
+          <fields>
+            <field>
+              <name>TXFIFO_TIMEOUT</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_SHIFT</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_ENA</name>
+              <description>a</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT</name>
+              <description>a</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_SHIFT</name>
+              <description>a</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_ENA</name>
+              <description>a</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACK_NUM</name>
+          <description>a</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>ACK_NUM</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_HEAD</name>
+          <description>a</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_HEAD</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUICK_SENT</name>
+          <description>a</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_SEND_NUM</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SINGLE_SEND_EN</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_NUM</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_EN</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q0_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q0_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q1_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q1_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q2_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q2_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q3_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q3_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q4_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q4_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q5_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q5_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q6_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q6_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF0</name>
+          <description>a</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DCDBC0</resetValue>
+          <fields>
+            <field>
+              <name>SEPER_CHAR</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR0</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR1</name>
+              <description>a</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF1</name>
+          <description>a</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DDDBDB</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR0</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR1</name>
+              <description>a</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF2</name>
+          <description>a</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DEDB11</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR0</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR1</name>
+              <description>a</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF3</name>
+          <description>a</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DFDB13</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ2</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR0</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR1</name>
+              <description>a</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_THRES</name>
+          <description>a</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>PKT_THRS</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>a</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007170</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UHCI0">
+      <name>UHCI1</name>
+      <description>Universal Host Controller Interface</description>
+      <baseAddress>0x6000C000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>USB_DEVICE</name>
+      <description>Full-speed USB Serial/JTAG Controller</description>
+      <groupName>USB_DEVICE</groupName>
+      <baseAddress>0x60043000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x50</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_SERIAL_JTAG</name>
+        <value>26</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>EP1</name>
+          <description>USB_DEVICE_EP1_REG.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RDWR_BYTE</name>
+              <description>Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EP1_CONF</name>
+          <description>USB_DEVICE_EP1_CONF_REG.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>WR_DONE</name>
+              <description>Set this bit to indicate writing byte data to UART Tx FIFO is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EP_DATA_FREE</name>
+              <description>1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_EP_DATA_AVAIL</name>
+              <description>1'b1: Indicate there is data in UART Rx FIFO.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>USB_DEVICE_INT_RAW_REG.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>JTAG_IN_FLUSH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOF_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when SOF frame is received.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_RECV_PKT_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EMPTY_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PID_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when pid error is detected.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRC5_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when CRC5 error is detected.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRC16_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when CRC16 error is detected.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STUFF_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when stuff error is detected.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_TOKEN_REC_IN_EP1_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_BUS_RESET_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when usb bus reset is detected.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_ZERO_PAYLOAD_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_ZERO_PAYLOAD_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>USB_DEVICE_INT_ST_REG.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>JTAG_IN_FLUSH_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOF_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_RECV_PKT_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EMPTY_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PID_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRC5_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRC16_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STUFF_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_TOKEN_REC_IN_EP1_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_BUS_RESET_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_ZERO_PAYLOAD_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_ZERO_PAYLOAD_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>USB_DEVICE_INT_ENA_REG.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>JTAG_IN_FLUSH_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOF_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_RECV_PKT_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EMPTY_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PID_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC5_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC16_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUFF_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_TOKEN_REC_IN_EP1_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_BUS_RESET_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EP1_ZERO_PAYLOAD_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EP2_ZERO_PAYLOAD_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>USB_DEVICE_INT_CLR_REG.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>JTAG_IN_FLUSH_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SOF_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_RECV_PKT_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PID_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC5_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC16_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STUFF_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_TOKEN_REC_IN_EP1_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_BUS_RESET_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_ZERO_PAYLOAD_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_ZERO_PAYLOAD_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0</name>
+          <description>USB_DEVICE_CONF0_REG.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004200</resetValue>
+          <fields>
+            <field>
+              <name>PHY_SEL</name>
+              <description>Select internal/external PHY</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXCHG_PINS_OVERRIDE</name>
+              <description>Enable software control USB D+ D- exchange</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXCHG_PINS</name>
+              <description>USB D+ D- exchange</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREFH</name>
+              <description>Control single-end input high threshold,1.76V to 2V, step 80mV</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREFL</name>
+              <description>Control single-end input low threshold,0.8V to 1.04V, step 80mV</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREF_OVERRIDE</name>
+              <description>Enable software control input  threshold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_PULL_OVERRIDE</name>
+              <description>Enable software control USB D+ D- pullup pulldown</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DP_PULLUP</name>
+              <description>Control USB D+ pull up.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DP_PULLDOWN</name>
+              <description>Control USB D+ pull down.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DM_PULLUP</name>
+              <description>Control USB D- pull up.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DM_PULLDOWN</name>
+              <description>Control USB D- pull down.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULLUP_VALUE</name>
+              <description>Control pull up value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_ENABLE</name>
+              <description>Enable USB pad function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEST</name>
+          <description>USB_DEVICE_TEST_REG.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable test of the USB pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_OE</name>
+              <description>USB pad oen in test</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DP</name>
+              <description>USB D+ tx value in test</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DM</name>
+              <description>USB D- tx value in test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JFIFO_ST</name>
+          <description>USB_DEVICE_JFIFO_ST_REG.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000044</resetValue>
+          <fields>
+            <field>
+              <name>IN_FIFO_CNT</name>
+              <description>JTAT in fifo counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_FIFO_EMPTY</name>
+              <description>1: JTAG in fifo is empty.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_FIFO_FULL</name>
+              <description>1: JTAG in fifo is full.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_FIFO_CNT</name>
+              <description>JTAT out fifo counter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_FIFO_EMPTY</name>
+              <description>1: JTAG out fifo is empty.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_FIFO_FULL</name>
+              <description>1: JTAG out fifo is full.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_FIFO_RESET</name>
+              <description>Write 1 to reset JTAG in fifo.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_FIFO_RESET</name>
+              <description>Write 1 to reset JTAG out fifo.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRAM_NUM</name>
+          <description>USB_DEVICE_FRAM_NUM_REG.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SOF_FRAME_INDEX</name>
+              <description>Frame index of received SOF frame.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP0_ST</name>
+          <description>USB_DEVICE_IN_EP0_ST_REG.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IN_EP0_STATE</name>
+              <description>State of IN Endpoint 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP0_WR_ADDR</name>
+              <description>Write data address of IN endpoint 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP0_RD_ADDR</name>
+              <description>Read data address of IN endpoint 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP1_ST</name>
+          <description>USB_DEVICE_IN_EP1_ST_REG.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IN_EP1_STATE</name>
+              <description>State of IN Endpoint 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP1_WR_ADDR</name>
+              <description>Write data address of IN endpoint 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP1_RD_ADDR</name>
+              <description>Read data address of IN endpoint 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP2_ST</name>
+          <description>USB_DEVICE_IN_EP2_ST_REG.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IN_EP2_STATE</name>
+              <description>State of IN Endpoint 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP2_WR_ADDR</name>
+              <description>Write data address of IN endpoint 2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP2_RD_ADDR</name>
+              <description>Read data address of IN endpoint 2.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP3_ST</name>
+          <description>USB_DEVICE_IN_EP3_ST_REG.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IN_EP3_STATE</name>
+              <description>State of IN Endpoint 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP3_WR_ADDR</name>
+              <description>Write data address of IN endpoint 3.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP3_RD_ADDR</name>
+              <description>Read data address of IN endpoint 3.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP0_ST</name>
+          <description>USB_DEVICE_OUT_EP0_ST_REG.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EP0_STATE</name>
+              <description>State of OUT Endpoint 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP0_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP0_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP1_ST</name>
+          <description>USB_DEVICE_OUT_EP1_ST_REG.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EP1_STATE</name>
+              <description>State of OUT Endpoint 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_REC_DATA_CNT</name>
+              <description>Data count in OUT endpoint 1 when one packet is received.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP2_ST</name>
+          <description>USB_DEVICE_OUT_EP2_ST_REG.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EP2_STATE</name>
+              <description>State of OUT Endpoint 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 2.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC_CONF</name>
+          <description>USB_DEVICE_MISC_CONF_REG.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>USB_DEVICE_MEM_CONF_REG.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>USB_MEM_PD</name>
+              <description>1: power down usb memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_MEM_CLK_EN</name>
+              <description>1: Force clock on for usb memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>USB_DEVICE_DATE_REG.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007300</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>XTS_AES</name>
+      <description>XTS-AES-128 Flash Encryption</description>
+      <groupName>XTS_AES</groupName>
+      <baseAddress>0x600CC000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x30</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PLAIN_MEM[%s]</name>
+          <description>The memory that stores plaintext</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>LINESIZE</name>
+          <description>XTS-AES line-size register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINESIZE</name>
+              <description>This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESTINATION</name>
+          <description>XTS-AES destination register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DESTINATION</name>
+              <description>This bit stores the destination. 0: flash(default). 1: reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PHYSICAL_ADDRESS</name>
+          <description>XTS-AES physical address register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PHYSICAL_ADDRESS</name>
+              <description>Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>XTS-AES trigger register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRIGGER</name>
+              <description>Set this bit to start manual encryption calculation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RELEASE</name>
+          <description>XTS-AES release register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RELEASE</name>
+              <description>Set this bit to release the manual encrypted result, after that the result will be visible to spi</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESTROY</name>
+          <description>XTS-AES destroy register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DESTROY</name>
+              <description>Set this bit to destroy XTS-AES result.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>XTS-AES status register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>XTS-AES version control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200623</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Those bits stores the version information of XTS-AES.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/tools/ide-debug/svd/esp32c6.svd b/tools/ide-debug/svd/esp32c6.svd
new file mode 100644
index 00000000000..33d3464537a
--- /dev/null
+++ b/tools/ide-debug/svd/esp32c6.svd
@@ -0,0 +1,70852 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+  <vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
+  <vendorID>ESPRESSIF</vendorID>
+  <name>ESP32-C6</name>
+  <series>ESP32-C6</series>
+  <version>1</version>
+  <description>32-bit RISC-V MCU &amp; 2.4 GHz Wi-Fi 6 &amp; Bluetooth 5 (LE) &amp; IEEE 802.15.4</description>
+  <licenseText>
+    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+</licenseText>
+  <cpu>
+    <name>RV32IMC</name>
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <nvicPrioBits>4</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>32</addressUnitBits>
+  <width>32</width>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AES</name>
+      <description>AES (Advanced Encryption Standard) Accelerator</description>
+      <groupName>AES</groupName>
+      <baseAddress>0x60088000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xBC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AES</name>
+        <value>73</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>KEY_0</name>
+          <description>Key material key_0 configure register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_0</name>
+              <description>This bits stores key_0 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_1</name>
+          <description>Key material key_1 configure register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_1</name>
+              <description>This bits stores key_1 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_2</name>
+          <description>Key material key_2 configure register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_2</name>
+              <description>This bits stores key_2 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_3</name>
+          <description>Key material key_3 configure register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_3</name>
+              <description>This bits stores key_3 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_4</name>
+          <description>Key material key_4 configure register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_4</name>
+              <description>This bits stores key_4 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_5</name>
+          <description>Key material key_5 configure register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_5</name>
+              <description>This bits stores key_5 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_6</name>
+          <description>Key material key_6 configure register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_6</name>
+              <description>This bits stores key_6 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_7</name>
+          <description>Key material key_7 configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_7</name>
+              <description>This bits stores key_7 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_0</name>
+          <description>source text material text_in_0 configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_0</name>
+              <description>This bits stores text_in_0 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_1</name>
+          <description>source text material text_in_1 configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_1</name>
+              <description>This bits stores text_in_1 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_2</name>
+          <description>source text material text_in_2 configure register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_2</name>
+              <description>This bits stores text_in_2 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_3</name>
+          <description>source text material text_in_3 configure register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_3</name>
+              <description>This bits stores text_in_3 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_0</name>
+          <description>result text material text_out_0 configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_0</name>
+              <description>This bits stores text_out_0 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_1</name>
+          <description>result text material text_out_1 configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_1</name>
+              <description>This bits stores text_out_1 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_2</name>
+          <description>result text material text_out_2 configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_2</name>
+              <description>This bits stores text_out_2 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_3</name>
+          <description>result text material text_out_3 configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_3</name>
+              <description>This bits stores text_out_3 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>AES Mode register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENDIAN</name>
+          <description>AES Endian configure register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENDIAN</name>
+              <description>endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out endian or out_stream endian</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>AES trigger register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRIGGER</name>
+              <description>Set this bit to start AES calculation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>AES state register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>IV_MEM[%s]</name>
+          <description>The memory that stores initialization vector</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>H_MEM[%s]</name>
+          <description>The memory that stores GCM hash subkey</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>J0_MEM[%s]</name>
+          <description>The memory that stores J0</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>T0_MEM[%s]</name>
+          <description>The memory that stores T0</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>DMA_ENABLE</name>
+          <description>DMA-AES working mode register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_ENABLE</name>
+              <description>1'b0: typical AES working mode, 1'b1: DMA-AES working mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_MODE</name>
+          <description>AES cipher block mode register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_MODE</name>
+              <description>Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_NUM</name>
+          <description>AES block number register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_NUM</name>
+              <description>Those bits stores the number of Plaintext/ciphertext block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INC_SEL</name>
+          <description>Standard incrementing function configure register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INC_SEL</name>
+              <description>This bit decides the standard incrementing function. 0: INC32. 1: INC128.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AAD_BLOCK_NUM</name>
+          <description>Additional Authential Data block number register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AAD_BLOCK_NUM</name>
+              <description>Those bits stores the number of AAD block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REMAINDER_BIT_NUM</name>
+          <description>AES remainder bit number register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REMAINDER_BIT_NUM</name>
+              <description>Those bits stores the number of remainder bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE</name>
+          <description>AES continue register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE</name>
+              <description>Set this bit to continue GCM operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLEAR</name>
+          <description>AES Interrupt clear register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_CLEAR</name>
+              <description>Set this bit to clear the AES interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>AES Interrupt enable register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_ENA</name>
+              <description>Set this bit to enable interrupt that occurs when DMA-AES calculation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>AES version control register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20191210</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This bits stores the version information of AES.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_EXIT</name>
+          <description>AES-DMA exit config</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_EXIT</name>
+              <description>Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>APB_SARADC</name>
+      <description>Successive Approximation Register Analog to Digital Converter</description>
+      <groupName>APB_SARADC</groupName>
+      <baseAddress>0x6000E000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x70</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>APB_SARADC</name>
+        <value>60</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40038240</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_START_FORCE</name>
+              <description>select software enable saradc sample</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_START</name>
+              <description>software enable saradc sample</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_GATED</name>
+              <description>SAR clock gated</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_DIV</name>
+              <description>SAR clock divider</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_PATT_P_CLEAR</name>
+              <description>clear the pointer of pattern table for DIG ADC1 CTRL</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_XPD_SAR_FORCE</name>
+              <description>force option to xpd sar blocks</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC2_PWDET_DRV</name>
+              <description>enable saradc2 power detect driven func.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_WAIT_ARB_CYCLE</name>
+              <description>wait arbit signal stable after sar_done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000A1FE</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_MEAS_NUM_LIMIT</name>
+              <description>enable max meas num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_MAX_MEAS_NUM</name>
+              <description>max conversion number</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_INV</name>
+              <description>1: data to DIG ADC1 CTRL is inverted, otherwise not</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_INV</name>
+              <description>1: data to DIG ADC2 CTRL is inverted, otherwise not</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_TARGET</name>
+              <description>to set saradc timer target</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_EN</name>
+              <description>to enable saradc timer trigger</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL1</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_FILTER_FACTOR1</name>
+              <description>Factor of saradc filter1</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_FILTER_FACTOR0</name>
+              <description>Factor of saradc filter0</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_WAIT</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FF0808</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_XPD_WAIT</name>
+              <description>saradc_xpd_wait</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_RSTB_WAIT</name>
+              <description>saradc_rstb_wait</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_STANDBY_WAIT</name>
+              <description>saradc_standby_wait</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20000000</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_STATUS</name>
+              <description>saradc1 status about data and channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20000000</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_STATUS</name>
+              <description>saradc2 status about data and channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PATT_TAB1</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PATT_TAB2</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ONETIME_SAMPLE</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1A000000</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_ONETIME_ATTEN</name>
+              <description>configure onetime atten</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_ONETIME_CHANNEL</name>
+              <description>configure onetime channel</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_ONETIME_START</name>
+              <description>trigger adc onetime sample</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC2_ONETIME_SAMPLE</name>
+              <description>enable adc2 onetime sample</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC1_ONETIME_SAMPLE</name>
+              <description>enable adc1 onetime sample</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000900</resetValue>
+          <fields>
+            <field>
+              <name>ADC_ARB_APB_FORCE</name>
+              <description>adc2 arbiter force to enableapb controller</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_FORCE</name>
+              <description>adc2 arbiter force to enable rtc controller</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_FORCE</name>
+              <description>adc2 arbiter force to enable wifi controller</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_GRANT_FORCE</name>
+              <description>adc2 arbiter force grant</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_APB_PRIORITY</name>
+              <description>Set adc2 arbiterapb priority</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_PRIORITY</name>
+              <description>Set adc2 arbiter rtc priority</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_PRIORITY</name>
+              <description>Set adc2 arbiter wifi priority</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_FIX_PRIORITY</name>
+              <description>adc2 arbiter uses fixed priority</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL0</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03740000</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_FILTER_CHANNEL1</name>
+              <description>configure filter1 to adc channel</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_FILTER_CHANNEL0</name>
+              <description>configure filter0 to adc channel</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_FILTER_RESET</name>
+              <description>enable apb_adc1_filter</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1DATA_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC1_DATA</name>
+              <description>saradc1 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2DATA_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC2_DATA</name>
+              <description>saradc2 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES0_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES0_CHANNEL</name>
+              <description>configure thres0 to adc channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH</name>
+              <description>saradc thres0 monitor thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW</name>
+              <description>saradc thres0 monitor thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES1_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES1_CHANNEL</name>
+              <description>configure thres1 to adc channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH</name>
+              <description>saradc thres1 monitor thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW</name>
+              <description>saradc thres1 monitor thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES_ALL_EN</name>
+              <description>enable thres to all channel</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_EN</name>
+              <description>enable thres1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_EN</name>
+              <description>enable thres0</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_TSENS_INT_ENA</name>
+              <description>tsens low  interrupt enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_ENA</name>
+              <description>saradc thres1 low  interrupt enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_ENA</name>
+              <description>saradc thres0 low interrupt enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_ENA</name>
+              <description>saradc thres1 high interrupt enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_ENA</name>
+              <description>saradc thres0 high interrupt enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ENA</name>
+              <description>saradc2 done interrupt enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ENA</name>
+              <description>saradc1 done interrupt enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_TSENS_INT_RAW</name>
+              <description>saradc tsens  interrupt raw</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_RAW</name>
+              <description>saradc thres1 low  interrupt raw</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_RAW</name>
+              <description>saradc thres0 low interrupt raw</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_RAW</name>
+              <description>saradc thres1 high interrupt raw</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_RAW</name>
+              <description>saradc thres0 high interrupt raw</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_RAW</name>
+              <description>saradc2 done interrupt raw</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_RAW</name>
+              <description>saradc1 done interrupt raw</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_TSENS_INT_ST</name>
+              <description>saradc tsens  interrupt state</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_ST</name>
+              <description>saradc thres1 low  interrupt state</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_ST</name>
+              <description>saradc thres0 low interrupt state</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_ST</name>
+              <description>saradc thres1 high interrupt state</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_ST</name>
+              <description>saradc thres0 high interrupt state</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ST</name>
+              <description>saradc2 done interrupt state</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ST</name>
+              <description>saradc1 done interrupt state</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_TSENS_INT_CLR</name>
+              <description>saradc tsens  interrupt clear</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_CLR</name>
+              <description>saradc thres1 low  interrupt clear</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_CLR</name>
+              <description>saradc thres0 low interrupt clear</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_CLR</name>
+              <description>saradc thres1 high interrupt clear</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_CLR</name>
+              <description>saradc thres0 high interrupt clear</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_CLR</name>
+              <description>saradc2 done interrupt clear</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_CLR</name>
+              <description>saradc1 done interrupt clear</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>APB_ADC_EOF_NUM</name>
+              <description>the dma_in_suc_eof gen when sample cnt = spi_eof_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_RESET_FSM</name>
+              <description>reset_apb_adc_state</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_TRANS</name>
+              <description>enable apb_adc use spi_dma</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKM_CONF</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_B</name>
+              <description>Fractional clock divider numerator value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_A</name>
+              <description>Fractional clock divider denominator value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg clk en</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_SEL</name>
+              <description>Set this bit to enable clk_apll</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_TSENS_CTRL</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018080</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_OUT</name>
+              <description>temperature sensor data out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_IN_INV</name>
+              <description>invert temperature sensor data</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_DIV</name>
+              <description>temperature sensor clock divider</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_PU</name>
+              <description>temperature sensor power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TSENS_CTRL2</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004002</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_XPD_WAIT</name>
+              <description>the time that power up tsens need wait</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_XPD_FORCE</name>
+              <description>force power up tsens</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_INV</name>
+              <description>inv tsens clk</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_SEL</name>
+              <description>tsens clk select</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALI</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_CALI_CFG</name>
+              <description>saradc cali factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_TSENS_WAKE</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>WAKEUP_TH_LOW</name>
+              <description>reg_wakeup_th_low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_TH_HIGH</name>
+              <description>reg_wakeup_th_high</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_OVER_UPPER_TH</name>
+              <description>reg_wakeup_over_upper_th</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_MODE</name>
+              <description>reg_wakeup_mode</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_EN</name>
+              <description>reg_wakeup_en</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_TSENS_SAMPLE</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000014</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_SAMPLE_RATE</name>
+              <description>HW sample rate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_SAMPLE_EN</name>
+              <description>HW sample en</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL_DATE</name>
+          <description>version</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206240</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ASSIST_DEBUG</name>
+      <description>Debug Assist</description>
+      <groupName>ASSIST_DEBUG</groupName>
+      <baseAddress>0x600C2000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ASSIST_DEBUG</name>
+        <value>26</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>C0RE_0_INTR_ENA</name>
+          <description>core0 monitor enable configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_ENA</name>
+              <description>Core0 dram0 area0 read monitor enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_ENA</name>
+              <description>Core0 dram0 area0 write monitor enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_ENA</name>
+              <description>Core0 dram0 area1 read monitor enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_ENA</name>
+              <description>Core0 dram0 area1 write monitor enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_ENA</name>
+              <description>Core0 PIF area0 read monitor enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_ENA</name>
+              <description>Core0 PIF area0 write monitor enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_ENA</name>
+              <description>Core0 PIF area1 read monitor enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_ENA</name>
+              <description>Core0 PIF area1 write monitor enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_ENA</name>
+              <description>Core0 stackpoint underflow monitor enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_ENA</name>
+              <description>Core0 stackpoint overflow monitor enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>IBUS busy monitor enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>DBUS busy monitor enbale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_RAW</name>
+          <description>core0 monitor interrupt status register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_RAW</name>
+              <description>Core0 dram0 area0 read monitor interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_RAW</name>
+              <description>Core0 dram0 area0 write monitor interrupt status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_RAW</name>
+              <description>Core0 dram0 area1 read monitor interrupt status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_RAW</name>
+              <description>Core0 dram0 area1 write monitor interrupt status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_RAW</name>
+              <description>Core0 PIF area0 read monitor interrupt status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_RAW</name>
+              <description>Core0 PIF area0 write monitor interrupt status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_RAW</name>
+              <description>Core0 PIF area1 read monitor interrupt status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_RAW</name>
+              <description>Core0 PIF area1 write monitor interrupt status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_RAW</name>
+              <description>Core0 stackpoint underflow monitor interrupt status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_RAW</name>
+              <description>Core0 stackpoint overflow monitor interrupt status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>IBUS busy monitor interrupt status</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>DBUS busy monitor initerrupt status</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_RLS</name>
+          <description>core0 monitor interrupt enable register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_RLS</name>
+              <description>Core0 dram0 area0 read monitor interrupt enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_RLS</name>
+              <description>Core0 dram0 area0 write monitor interrupt enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_RLS</name>
+              <description>Core0 dram0 area1 read monitor interrupt enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_RLS</name>
+              <description>Core0 dram0 area1 write monitor interrupt enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_RLS</name>
+              <description>Core0 PIF area0 read monitor interrupt enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_RLS</name>
+              <description>Core0 PIF area0 write monitor interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_RLS</name>
+              <description>Core0 PIF area1 read monitor interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_RLS</name>
+              <description>Core0 PIF area1 write monitor interrupt enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_RLS</name>
+              <description>Core0 stackpoint underflow monitor interrupt enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_RLS</name>
+              <description>Core0 stackpoint overflow monitor interrupt enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>IBUS busy monitor interrupt enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>DBUS busy monitor interrupt enbale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_CLR</name>
+          <description>core0 monitor interrupt clr register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_CLR</name>
+              <description>Core0 dram0 area0 read monitor interrupt clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_CLR</name>
+              <description>Core0 dram0 area0 write monitor interrupt clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_CLR</name>
+              <description>Core0 dram0 area1 read monitor interrupt clr</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_CLR</name>
+              <description>Core0 dram0 area1 write monitor interrupt clr</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_CLR</name>
+              <description>Core0 PIF area0 read monitor interrupt clr</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_CLR</name>
+              <description>Core0 PIF area0 write monitor interrupt clr</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_CLR</name>
+              <description>Core0 PIF area1 read monitor interrupt clr</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_CLR</name>
+              <description>Core0 PIF area1 write monitor interrupt clr</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_CLR</name>
+              <description>Core0 stackpoint underflow monitor interrupt clr</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_CLR</name>
+              <description>Core0 stackpoint overflow monitor interrupt clr</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>IBUS busy monitor interrupt clr</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>DBUS busy monitor interrupt clr</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_0_MIN</name>
+          <description>core0 dram0 region0 addr configuration register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_MIN</name>
+              <description>Core0 dram0 region0 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_0_MAX</name>
+          <description>core0 dram0 region0 addr configuration register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_MAX</name>
+              <description>Core0 dram0 region0 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_1_MIN</name>
+          <description>core0 dram0 region1 addr configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_MIN</name>
+              <description>Core0 dram0 region1 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_1_MAX</name>
+          <description>core0 dram0 region1 addr configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_MAX</name>
+              <description>Core0 dram0 region1 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_0_MIN</name>
+          <description>core0 PIF region0 addr configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_0_MIN</name>
+              <description>Core0 PIF region0 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_0_MAX</name>
+          <description>core0 PIF region0 addr configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_0_MAX</name>
+              <description>Core0 PIF region0 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_1_MIN</name>
+          <description>core0 PIF region1 addr configuration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_1_MIN</name>
+              <description>Core0 PIF region1 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_1_MAX</name>
+          <description>core0 PIF region1 addr configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_1_MAX</name>
+              <description>Core0 PIF region1 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PC</name>
+          <description>core0 area pc status register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PC</name>
+              <description>the stackpointer when first touch region monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_SP</name>
+          <description>core0 area sp status register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_SP</name>
+              <description>the PC when first touch region monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MIN</name>
+          <description>stack min value</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MIN</name>
+              <description>core0 sp region configuration regsiter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MAX</name>
+          <description>stack max value</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MAX</name>
+              <description>core0 sp pc status register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_PC</name>
+          <description>stack monitor pc status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_PC</name>
+              <description>This regsiter stores the PC when trigger stack monitor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_EN</name>
+          <description>record enable configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_RECORDEN</name>
+              <description>Set 1 to enable record PC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_RCD_PDEBUGEN</name>
+              <description>Set 1 to enable cpu pdebug function, must set this bit can get cpu PC</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGPC</name>
+          <description>record status regsiter</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGPC</name>
+              <description>recorded PC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGSP</name>
+          <description>record status regsiter</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGSP</name>
+              <description>recorded sp</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_EXCEPTION_MONITOR_0</name>
+          <description>exception monitor status register0</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_ADDR_0</name>
+              <description>reg_core_0_iram0_recording_addr_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_WR_0</name>
+              <description>reg_core_0_iram0_recording_wr_0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_LOADSTORE_0</name>
+              <description>reg_core_0_iram0_recording_loadstore_0</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_EXCEPTION_MONITOR_1</name>
+          <description>exception monitor status register1</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_ADDR_1</name>
+              <description>reg_core_0_iram0_recording_addr_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_WR_1</name>
+              <description>reg_core_0_iram0_recording_wr_1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_LOADSTORE_1</name>
+              <description>reg_core_0_iram0_recording_loadstore_1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_0</name>
+          <description>exception monitor status register2</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_ADDR_0</name>
+              <description>reg_core_0_dram0_recording_addr_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_WR_0</name>
+              <description>reg_core_0_dram0_recording_wr_0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_BYTEEN_0</name>
+              <description>reg_core_0_dram0_recording_byteen_0</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_1</name>
+          <description>exception monitor status register3</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_PC_0</name>
+              <description>reg_core_0_dram0_recording_pc_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_2</name>
+          <description>exception monitor status register4</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_ADDR_1</name>
+              <description>reg_core_0_dram0_recording_addr_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_WR_1</name>
+              <description>reg_core_0_dram0_recording_wr_1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_BYTEEN_1</name>
+              <description>reg_core_0_dram0_recording_byteen_1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_3</name>
+          <description>exception monitor status register5</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_PC_1</name>
+              <description>reg_core_0_dram0_recording_pc_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0</name>
+          <description>exception monitor status register6</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0</name>
+              <description>reg_core_x_iram0_dram0_limit_cycle_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1</name>
+          <description>exception monitor status register7</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1</name>
+              <description>reg_core_x_iram0_dram0_limit_cycle_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C0RE_0_LASTPC_BEFORE_EXCEPTION</name>
+          <description>cpu status register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_LASTPC_BEFORE_EXC</name>
+              <description>cpu's lastpc before exception</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C0RE_0_DEBUG_MODE</name>
+          <description>cpu status register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DEBUG_MODE</name>
+              <description>cpu debug mode status, 1 means cpu enter debug mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DEBUG_MODULE_ACTIVE</name>
+              <description>cpu debug_module active status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set 1 force on the clock gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02109130</resetValue>
+          <fields>
+            <field>
+              <name>ASSIST_DEBUG_DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ATOMIC</name>
+      <description>Peripheral ATOMIC</description>
+      <groupName>ATOMIC</groupName>
+      <baseAddress>0x60011000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x14</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>ADDR_LOCK</name>
+          <description>hardware lock regsiter</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOCK</name>
+              <description>read to acquire hardware lock, write to release hardware lock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LR_ADDR</name>
+          <description>gloable lr address regsiter</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GLOABLE_LR_ADDR</name>
+              <description>backup gloable address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LR_VALUE</name>
+          <description>gloable lr value regsiter</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GLOABLE_LR_VALUE</name>
+              <description>backup gloable value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOCK_STATUS</name>
+          <description>lock status regsiter</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOCK_STATUS</name>
+              <description>read hareware lock status for debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COUNTER</name>
+          <description>wait counter register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WAIT_COUNTER</name>
+              <description>delay counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMA</name>
+      <description>DMA (Direct Memory Access) Controller</description>
+      <groupName>DMA</groupName>
+      <baseAddress>0x60080000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1A4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMA_IN_CH0</name>
+        <value>66</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_IN_CH1</name>
+        <value>67</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_IN_CH2</name>
+        <value>68</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_OUT_CH0</name>
+        <value>69</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_OUT_CH1</name>
+        <value>70</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_OUT_CH2</name>
+        <value>71</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>IN_INT_RAW_CH%s</name>
+          <description>Raw status interrupt of channel 0</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_CH_INT_RAW</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_CH_INT_RAW</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>IN_INT_ST_CH%s</name>
+          <description>Masked interrupt of channel 0</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>IN_INT_ENA_CH%s</name>
+          <description>Interrupt enable bits of channel 0</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>IN_INT_CLR_CH%s</name>
+          <description>Interrupt clear bits of channel 0</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_CH_INT_CLR</name>
+              <description>Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_CH_INT_CLR</name>
+              <description>Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>OUT_INT_RAW_CH%s</name>
+          <description>Raw status interrupt of channel 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_CH_INT_RAW</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_CH_INT_RAW</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>OUT_INT_ST_CH%s</name>
+          <description>Masked interrupt of channel 0</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>OUT_INT_ENA_CH%s</name>
+          <description>Interrupt enable bits of channel 0</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>OUT_INT_CLR_CH%s</name>
+          <description>Interrupt clear bits of channel 0</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_TEST</name>
+          <description>reserved</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHB_TESTMODE</name>
+              <description>reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_TESTADDR</name>
+              <description>reserved</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC_CONF</name>
+          <description>MISC register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHBM_RST_INTER</name>
+              <description>Set this bit then clear this bit to reset the internal ahb FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_PRI_DIS</name>
+              <description>Set this bit to disable priority arbitration function.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02202250</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_CONF0_CH%s</name>
+          <description>Configure 0 register of Rx channel 0</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_RST_CH</name>
+              <description>This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST_CH</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN_CH</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DATA_BURST_EN_CH</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN_CH</name>
+              <description>Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ETM_EN_CH</name>
+              <description>Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_CONF1_CH%s</name>
+          <description>Configure 1 register of Rx channel 0</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_CHECK_OWNER_CH</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>INFIFO_STATUS_CH%s</name>
+          <description>Receive FIFO status of Rx channel 0</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800003</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_FULL_CH</name>
+              <description>L1 Rx FIFO full signal for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_EMPTY_CH</name>
+              <description>L1 Rx FIFO empty signal for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT_CH</name>
+              <description>The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_1B_CH</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_2B_CH</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_3B_CH</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_4B_CH</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_BUF_HUNGRY_CH</name>
+              <description>reserved</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_POP_CH%s</name>
+          <description>Pop control register of Rx channel 0</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA_CH</name>
+              <description>This register stores the data popping from DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP_CH</name>
+              <description>Set this bit to pop data from DMA FIFO.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_LINK_CH%s</name>
+          <description>Link descriptor configure and control register of Rx channel 0</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01100000</resetValue>
+          <fields>
+            <field>
+              <name>INLINK_ADDR_CH</name>
+              <description>This register stores the 20 least significant bits of the first inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET_CH</name>
+              <description>Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP_CH</name>
+              <description>Set this bit to stop dealing with the inlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INLINK_START_CH</name>
+              <description>Set this bit to start dealing with the inlink descriptors.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART_CH</name>
+              <description>Set this bit to mount a new inlink descriptor.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INLINK_PARK_CH</name>
+              <description>1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_STATE_CH%s</name>
+          <description>Receive status of Rx channel 0</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_ADDR_CH</name>
+              <description>This register stores the current inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_STATE_CH</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_STATE_CH</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_SUC_EOF_DES_ADDR_CH%s</name>
+          <description>Inlink descriptor address when EOF occurs of Rx channel 0</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR_CH</name>
+              <description>This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_ERR_EOF_DES_ADDR_CH%s</name>
+          <description>Inlink descriptor address when errors occur of Rx channel 0</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_ERR_EOF_DES_ADDR_CH</name>
+              <description>This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_DSCR_CH%s</name>
+          <description>Current inlink descriptor address of Rx channel 0</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_CH</name>
+              <description>The address of the current inlink descriptor x.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_DSCR_BF0_CH%s</name>
+          <description>The last inlink descriptor address of Rx channel 0</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0_CH</name>
+              <description>The address of the last inlink descriptor x-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_DSCR_BF1_CH%s</name>
+          <description>The second-to-last inlink descriptor address of Rx channel 0</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1_CH</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_PRI_CH%s</name>
+          <description>Priority register of Rx channel 0</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_PRI_CH</name>
+              <description>The priority of Rx channel 0. The larger of the value the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_PERI_SEL_CH%s</name>
+          <description>Peripheral selection of Rx channel 0</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_IN_SEL_CH</name>
+              <description>This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_CONF1_CH%s</name>
+          <description>Configure 1 register of Tx channel 0</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_CHECK_OWNER_CH</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUTFIFO_STATUS_CH%s</name>
+          <description>Transmit FIFO status of Tx channel 0</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800002</resetValue>
+          <fields>
+            <field>
+              <name>OUTFIFO_FULL_CH</name>
+              <description>L1 Tx FIFO full signal for Tx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY_CH</name>
+              <description>L1 Tx FIFO empty signal for Tx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT_CH</name>
+              <description>The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_1B_CH</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_2B_CH</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_3B_CH</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_4B_CH</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_PUSH_CH%s</name>
+          <description>Push control register of Rx channel 0</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA_CH</name>
+              <description>This register stores the data that need to be pushed into DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH_CH</name>
+              <description>Set this bit to push data into DMA FIFO.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_LINK_CH%s</name>
+          <description>Link descriptor configure and control register of Tx channel 0</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR_CH</name>
+              <description>This register stores the 20 least significant bits of the first outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP_CH</name>
+              <description>Set this bit to stop dealing with the outlink descriptors.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_START_CH</name>
+              <description>Set this bit to start dealing with the outlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART_CH</name>
+              <description>Set this bit to restart a new outlink from the last address.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK_CH</name>
+              <description>1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_STATE_CH%s</name>
+          <description>Transmit status of Tx channel 0</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_ADDR_CH</name>
+              <description>This register stores the current outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_STATE_CH</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_STATE_CH</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_EOF_DES_ADDR_CH%s</name>
+          <description>Outlink descriptor address when EOF occurs of Tx channel 0</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR_CH</name>
+              <description>This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_EOF_BFR_DES_ADDR_CH%s</name>
+          <description>The last outlink descriptor address when EOF occurs of Tx channel 0</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR_CH</name>
+              <description>This register stores the address of the outlink descriptor before the last outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_DSCR_CH%s</name>
+          <description>Current inlink descriptor address of Tx channel 0</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_CH</name>
+              <description>The address of the current outlink descriptor y.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_DSCR_BF0_CH%s</name>
+          <description>The last inlink descriptor address of Tx channel 0</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0_CH</name>
+              <description>The address of the last outlink descriptor y-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_DSCR_BF1_CH%s</name>
+          <description>The second-to-last inlink descriptor address of Tx channel 0</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1_CH</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_PRI_CH%s</name>
+          <description>Priority register of Tx channel 0.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_PRI_CH</name>
+              <description>The priority of Tx channel 0. The larger of the value the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_PERI_SEL_CH%s</name>
+          <description>Peripheral selection of Tx channel 0</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_OUT_SEL_CH</name>
+              <description>This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_CONF0_CH%s</name>
+          <description>Configure 0 register of Tx channel 1</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>OUT_RST_CH</name>
+              <description>This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST_CH</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK_CH</name>
+              <description>Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE_CH</name>
+              <description>EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN_CH</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN_CH</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_ETM_EN_CH</name>
+              <description>Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DS</name>
+      <description>Digital Signature</description>
+      <groupName>DS</groupName>
+      <baseAddress>0x6008C000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA5C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Y_MEM[%s]</name>
+          <description>memory that stores Y</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>memory that stores M</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>RB_MEM[%s]</name>
+          <description>memory that stores Rb</description>
+          <addressOffset>0x400</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>48</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>BOX_MEM[%s]</name>
+          <description>memory that stores BOX</description>
+          <addressOffset>0x600</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>IV_MEM[%s]</name>
+          <description>memory that stores IV</description>
+          <addressOffset>0x630</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>X_MEM[%s]</name>
+          <description>memory that stores X</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Z_MEM[%s]</name>
+          <description>memory that stores Z</description>
+          <addressOffset>0xA00</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>SET_START</name>
+          <description>DS start control register</description>
+          <addressOffset>0xE00</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>set this bit to start DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_CONTINUE</name>
+          <description>DS continue control register</description>
+          <addressOffset>0xE04</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_CONTINUE</name>
+              <description>set this bit to continue DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_FINISH</name>
+          <description>DS finish control register</description>
+          <addressOffset>0xE08</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_FINISH</name>
+              <description>Set this bit to finish DS process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>DS query busy register</description>
+          <addressOffset>0xE0C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_BUSY</name>
+              <description>digital signature state. 1'b0: idle, 1'b1: busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_KEY_WRONG</name>
+          <description>DS query key-wrong counter register</description>
+          <addressOffset>0xE10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_KEY_WRONG</name>
+              <description>digital signature key wrong counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_CHECK</name>
+          <description>DS query check result register</description>
+          <addressOffset>0xE14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MD_ERROR</name>
+              <description>MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PADDING_BAD</name>
+              <description>padding checkout result. 1'b0: a good padding, 1'b1: a bad padding</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>DS version control register</description>
+          <addressOffset>0xE20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200618</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>ds version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ECC</name>
+      <description>Peripheral ECC</description>
+      <groupName>ECC</groupName>
+      <baseAddress>0x6008B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x78</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ECC</name>
+        <value>76</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MULT_INT_RAW</name>
+          <description>ECC interrupt raw register, valid in level.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the ecc_calc_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_INT_ST</name>
+          <description>ECC interrupt status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the ecc_calc_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_INT_ENA</name>
+          <description>ECC interrupt enable register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the ecc_calc_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_INT_CLR</name>
+          <description>ECC interrupt clear register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_CLR</name>
+              <description>Set this bit to clear the ecc_calc_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_CONF</name>
+          <description>ECC configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESET</name>
+              <description>Write 1 to reset ECC Accelerator.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>KEY_LENGTH</name>
+              <description>The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SECURITY_MODE</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Write 1 to force on register clock gate.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WORK_MODE</name>
+              <description>The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VERIFICATION_RESULT</name>
+              <description>The verification result bit of ECC Accelerator, only valid when calculation is done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_CLOCK_GATE_FORCE_ON</name>
+              <description>ECC memory clock gate force on register</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201240</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>ECC mult version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>K_MEM[%s]</name>
+          <description>The memory that stores k.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PX_MEM[%s]</name>
+          <description>The memory that stores Px.</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PY_MEM[%s]</name>
+          <description>The memory that stores Py.</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x8</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EFUSE</name>
+      <description>eFuse Controller</description>
+      <groupName>EFUSE</groupName>
+      <baseAddress>0x600B0800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1D0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EFUSE</name>
+        <value>14</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PGM_DATA0</name>
+          <description>Register 0 that stores data to be programmed.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_0</name>
+              <description>Configures the 0th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA1</name>
+          <description>Register 1 that stores data to be programmed.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_1</name>
+              <description>Configures the 1st 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA2</name>
+          <description>Register 2 that stores data to be programmed.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_2</name>
+              <description>Configures the 2nd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA3</name>
+          <description>Register 3 that stores data to be programmed.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_3</name>
+              <description>Configures the 3rd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA4</name>
+          <description>Register 4 that stores data to be programmed.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_4</name>
+              <description>Configures the 4th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA5</name>
+          <description>Register 5 that stores data to be programmed.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_5</name>
+              <description>Configures the 5th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA6</name>
+          <description>Register 6 that stores data to be programmed.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_6</name>
+              <description>Configures the 6th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA7</name>
+          <description>Register 7 that stores data to be programmed.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_7</name>
+              <description>Configures the 7th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE0</name>
+          <description>Register 0 that stores the RS code to be programmed.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_0</name>
+              <description>Configures the 0th 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE1</name>
+          <description>Register 1 that stores the RS code to be programmed.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_1</name>
+              <description>Configures the 1st 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE2</name>
+          <description>Register 2 that stores the RS code to be programmed.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_2</name>
+              <description>Configures the 2nd 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_WR_DIS</name>
+          <description>BLOCK0 data register 0.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_DIS</name>
+              <description>Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA0</name>
+          <description>BLOCK0 data register 1.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS</name>
+              <description>Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWAP_UART_SDIO_EN</name>
+              <description>Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE</name>
+              <description>Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_JTAG</name>
+              <description>Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE</name>
+              <description>Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_SERIAL_JTAG</name>
+              <description>Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD</name>
+              <description>Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOWNLOAD_MSPI_DIS</name>
+              <description>Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_CAN</name>
+              <description>Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>JTAG_SEL_ENABLE</name>
+              <description>Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG</name>
+              <description>Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG</name>
+              <description>Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH</name>
+              <description>Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL</name>
+              <description>Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS</name>
+              <description>Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_AS_GPIO</name>
+              <description>Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_2</name>
+              <description>Reserved.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_1</name>
+              <description>Reserved.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_0</name>
+              <description>Reserved.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA1</name>
+          <description>BLOCK0 data register 2.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED1_0</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL</name>
+              <description>Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT</name>
+              <description>Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0</name>
+              <description>Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1</name>
+              <description>Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2</name>
+              <description>Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0</name>
+              <description>Represents the purpose of Key0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1</name>
+              <description>Represents the purpose of Key1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA2</name>
+          <description>BLOCK0 data register 3.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00080000</resetValue>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2</name>
+              <description>Represents the purpose of Key2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3</name>
+              <description>Represents the purpose of Key3.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4</name>
+              <description>Represents the purpose of Key4.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5</name>
+              <description>Represents the purpose of Key5.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPA_SEC_LEVEL</name>
+              <description>Represents the spa secure level by configuring the clock random divide mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED2_1</name>
+              <description>Reserved.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRYPT_DPA_ENABLE</name>
+              <description>Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN</name>
+              <description>Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE</name>
+              <description>Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED2_0</name>
+              <description>Reserved.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW</name>
+              <description>Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA3</name>
+          <description>BLOCK0 data register 4.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE</name>
+              <description>Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DIRECT_BOOT</name>
+              <description>Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_PRINT</name>
+              <description>Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_5</name>
+              <description>Reserved.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE</name>
+              <description>Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD</name>
+              <description>Represents whether security download is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL</name>
+              <description>Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_4</name>
+              <description>Reserved.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_3</name>
+              <description>Reserved.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_2</name>
+              <description>Reserved.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_1</name>
+              <description>Reserved.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME</name>
+              <description>Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION</name>
+              <description>Represents the version used by ESP-IDF anti-rollback feature.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_DISABLE_FAST_WAKE</name>
+              <description>Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_0</name>
+              <description>Reserved.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA4</name>
+          <description>BLOCK0 data register 5.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED4_1</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED4_0</name>
+              <description>Reserved.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_0</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_0</name>
+              <description>Stores the low 32 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_1</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_1</name>
+              <description>Stores the high 16 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAC_EXT</name>
+              <description>Stores the extended bits of MAC address.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_2</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_SPI_RESERVED</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_PAD_CONF_1</name>
+              <description>Stores the first part of SPI_PAD_CONF.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_3</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_PAD_CONF_2</name>
+              <description>Stores the second part of SPI_PAD_CONF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_DATA_PART0_0</name>
+              <description>Stores the first 14 bits of the zeroth part of system data.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_4</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_1</name>
+              <description>Stores the first 32 bits of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_5</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_2</name>
+              <description>Stores the second 32 bits of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA0</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_0</name>
+              <description>Stores the zeroth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA1</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_1</name>
+              <description>Stores the first 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA2</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_2</name>
+              <description>Stores the second 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA3</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_3</name>
+              <description>Stores the third 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA4</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_4</name>
+              <description>Stores the fourth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA5</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_5</name>
+              <description>Stores the fifth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA6</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_6</name>
+              <description>Stores the sixth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA7</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_7</name>
+              <description>Stores the seventh 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA0</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA0</name>
+              <description>Stores the zeroth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA1</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA1</name>
+              <description>Stores the first 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA2</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA2</name>
+              <description>Stores the second 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA3</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA3</name>
+              <description>Stores the third 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA4</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA4</name>
+              <description>Stores the fourth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA5</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA5</name>
+              <description>Stores the fifth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA6</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA6</name>
+              <description>Stores the sixth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA7</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA7</name>
+              <description>Stores the seventh 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA0</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA1</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA1</name>
+              <description>Stores the first 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA2</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA2</name>
+              <description>Stores the second 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA3</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA3</name>
+              <description>Stores the third 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA4</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA5</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA6</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA7</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA0</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA1</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA1</name>
+              <description>Stores the first 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA2</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA2</name>
+              <description>Stores the second 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA3</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA3</name>
+              <description>Stores the third 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA4</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA5</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA6</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA7</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA0</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA1</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA1</name>
+              <description>Stores the first 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA2</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA2</name>
+              <description>Stores the second 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA3</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA3</name>
+              <description>Stores the third 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA4</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA5</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA6</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA7</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA0</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA1</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA1</name>
+              <description>Stores the first 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA2</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA2</name>
+              <description>Stores the second 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA3</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA3</name>
+              <description>Stores the third 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA4</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA5</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA6</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA7</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA0</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA1</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA1</name>
+              <description>Stores the first 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA2</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA2</name>
+              <description>Stores the second 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA3</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA3</name>
+              <description>Stores the third 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA4</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA5</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA6</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA7</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA0</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA1</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA1</name>
+              <description>Stores the first 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA2</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA2</name>
+              <description>Stores the second 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA3</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA3</name>
+              <description>Stores the third 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA4</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA5</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA6</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA7</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA0</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_0</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA1</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_1</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA2</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_2</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA3</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_3</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA4</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_4</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA5</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_5</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA6</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_6</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA7</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_7</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR0</name>
+          <description>Programming error record register 0 of BLOCK0.</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS_ERR</name>
+              <description>Indicates a programming error of RD_DIS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWAP_UART_SDIO_EN_ERR</name>
+              <description>Indicates a programming error of SWAP_UART_SDIO_EN.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE_ERR</name>
+              <description>Indicates a programming error of DIS_ICACHE.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_JTAG_ERR</name>
+              <description>Indicates a programming error of DIS_USB_JTAG.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE_ERR</name>
+              <description>Indicates a programming error of DIS_DOWNLOAD_ICACHE.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_SERIAL_JTAG_ERR</name>
+              <description>Indicates a programming error of DIS_USB_DEVICE.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD_ERR</name>
+              <description>Indicates a programming error of DIS_FORCE_DOWNLOAD.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOWNLOAD_MSPI_DIS_ERR</name>
+              <description>Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_TWAI_ERR</name>
+              <description>Indicates a programming error of DIS_CAN.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>JTAG_SEL_ENABLE_ERR</name>
+              <description>Indicates a programming error of JTAG_SEL_ENABLE.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG_ERR</name>
+              <description>Indicates a programming error of SOFT_DIS_JTAG.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG_ERR</name>
+              <description>Indicates a programming error of DIS_PAD_JTAG.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR</name>
+              <description>Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH_ERR</name>
+              <description>Indicates a programming error of USB_DREFH.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL_ERR</name>
+              <description>Indicates a programming error of USB_DREFL.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS_ERR</name>
+              <description>Indicates a programming error of USB_EXCHG_PINS.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_AS_GPIO_ERR</name>
+              <description>Indicates a programming error of VDD_SPI_AS_GPIO.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR_2</name>
+              <description>Reserved.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR_1</name>
+              <description>Reserved.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR_0</name>
+              <description>Reserved.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR1</name>
+          <description>Programming error record register 1 of BLOCK0.</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED1_ERR_0</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL_ERR</name>
+              <description>Indicates a programming error of WDT_DELAY_SEL.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT_ERR</name>
+              <description>Indicates a programming error of SPI_BOOT_CRYPT_CNT.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR2</name>
+          <description>Programming error record register 2 of BLOCK0.</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_3.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_4.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_5.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEC_DPA_LEVEL_ERR</name>
+              <description>Indicates a programming error of SEC_DPA_LEVEL.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED2_ERR_1</name>
+              <description>Reserved.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRYPT_DPA_ENABLE_ERR</name>
+              <description>Indicates a programming error of CRYPT_DPA_ENABLE.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_EN.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED2_ERR_0</name>
+              <description>Reserved.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW_ERR</name>
+              <description>Indicates a programming error of FLASH_TPUW.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR3</name>
+          <description>Programming error record register 3 of BLOCK0.</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE_ERR</name>
+              <description>Indicates a programming error of DIS_DOWNLOAD_MODE.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DIRECT_BOOT_ERR</name>
+              <description>Indicates a programming error of DIS_DIRECT_BOOT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_PRINT_ERR</name>
+              <description>Indicates a programming error of UART_PRINT_CHANNEL.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_ERR_5</name>
+              <description>Reserved.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR</name>
+              <description>Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD_ERR</name>
+              <description>Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL_ERR</name>
+              <description>Indicates a programming error of UART_PRINT_CONTROL.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_ERR_4</name>
+              <description>Reserved.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_ERR_3</name>
+              <description>Reserved.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_ERR_2</name>
+              <description>Reserved.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_ERR_1</name>
+              <description>Reserved.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME_ERR</name>
+              <description>Indicates a programming error of FORCE_SEND_RESUME.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION_ERR</name>
+              <description>Indicates a programming error of SECURE_VERSION.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_ERR_0</name>
+              <description>Reserved.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR4</name>
+          <description>Programming error record register 4 of BLOCK0.</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED4_ERR_1</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED4_ERR_0</name>
+              <description>Reserved.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR0</name>
+          <description>Programming error record register 0 of BLOCK1-10.</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_SPI_8M_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAC_SPI_8M_FAIL</name>
+              <description>0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_FAIL</name>
+              <description>0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_FAIL</name>
+              <description>0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_FAIL</name>
+              <description>0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_FAIL</name>
+              <description>0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_FAIL</name>
+              <description>0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_FAIL</name>
+              <description>0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_FAIL</name>
+              <description>0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR1</name>
+          <description>Programming error record register 1 of BLOCK1-10.</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY5_FAIL</name>
+              <description>0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_FAIL</name>
+              <description>0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>eFuse clcok configuration register.</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to force eFuse SRAM into power-saving mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>Set this bit and force to activate clock signal of eFuse SRAM.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>Set this bit to force eFuse SRAM into working mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Set this bit to force enable eFuse register configuration clock signal.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>eFuse operation mode configuraiton register</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OP_CODE</name>
+              <description>0x5A5A:  programming operation command 0x5AA5: read operation command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>eFuse status register.</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Indicates the state of the eFuse state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_LOAD_SW</name>
+              <description>The value of OTP_LOAD_SW.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_C_SYNC2</name>
+              <description>The value of OTP_VDDQ_C_SYNC2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_STROBE_SW</name>
+              <description>The value of OTP_STROBE_SW.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_CSB_SW</name>
+              <description>The value of OTP_CSB_SW.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_PGENB_SW</name>
+              <description>The value of OTP_PGENB_SW.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_IS_SW</name>
+              <description>The value of OTP_VDDQ_IS_SW.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK0_VALID_BIT_CNT</name>
+              <description>Indicates the number of block valid bit.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>eFuse command register.</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_CMD</name>
+              <description>Set this bit to send read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_CMD</name>
+              <description>Set this bit to send programming command.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BLK_NUM</name>
+              <description>The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>eFuse raw interrupt register.</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_RAW</name>
+              <description>The raw bit signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_RAW</name>
+              <description>The raw bit signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>eFuse interrupt status register.</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ST</name>
+              <description>The status signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ST</name>
+              <description>The status signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>eFuse interrupt enable register.</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ENA</name>
+              <description>The enable signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ENA</name>
+              <description>The enable signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>eFuse interrupt clear register.</description>
+          <addressOffset>0x1E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_CLR</name>
+              <description>The clear signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_CLR</name>
+              <description>The clear signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAC_CONF</name>
+          <description>Controls the eFuse programming voltage.</description>
+          <addressOffset>0x1E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001FE1C</resetValue>
+          <fields>
+            <field>
+              <name>DAC_CLK_DIV</name>
+              <description>Controls the division factor of the rising clock of the programming voltage.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_PAD_SEL</name>
+              <description>Don't care.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_NUM</name>
+              <description>Controls the rising period of the programming voltage.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OE_CLR</name>
+              <description>Reduces the power supply of the programming voltage.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_TIM_CONF</name>
+          <description>Configures read timing parameters.</description>
+          <addressOffset>0x1EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x12010201</resetValue>
+          <fields>
+            <field>
+              <name>THR_A</name>
+              <description>Configures the read hold time.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRD</name>
+              <description>Configures the read time.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSUR_A</name>
+              <description>Configures the read setup time.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>READ_INIT_NUM</name>
+              <description>Configures the waiting time of reading eFuse memory.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF1</name>
+          <description>Configurarion register 1 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01300001</resetValue>
+          <fields>
+            <field>
+              <name>TSUP_A</name>
+              <description>Configures the programming setup time.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWR_ON_NUM</name>
+              <description>Configures the power up time for VDDQ.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THP_A</name>
+              <description>Configures the programming hold time.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF2</name>
+          <description>Configurarion register 2 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C80190</resetValue>
+          <fields>
+            <field>
+              <name>PWR_OFF_NUM</name>
+              <description>Configures the power outage time for VDDQ.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TPGM</name>
+              <description>Configures the active programming time.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF0_RS_BYPASS</name>
+          <description>Configurarion register0 of eFuse programming time parameters and rs bypass operation.</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002000</resetValue>
+          <fields>
+            <field>
+              <name>BYPASS_RS_CORRECTION</name>
+              <description>Set this bit to bypass reed solomon correction step.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BYPASS_RS_BLK_NUM</name>
+              <description>Configures block number of programming twice operation.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UPDATE</name>
+              <description>Set this bit to update multi-bit register signals.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TPGM_INACTIVE</name>
+              <description>Configures the inactive programming time.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>eFuse version register.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206300</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Stores eFuse version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EXTMEM</name>
+      <description>External Memory</description>
+      <groupName>EXTMEM</groupName>
+      <baseAddress>0x600C8000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x3C8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>L1_ICACHE_CTRL</name>
+          <description>L1 instruction Cache(L1-ICache) control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE_SHUT_IBUS0</name>
+              <description>The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_SHUT_IBUS1</name>
+              <description>The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_SHUT_IBUS2</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_SHUT_IBUS3</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_UNDEF_OP</name>
+              <description>Reserved</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_CTRL</name>
+          <description>L1 data Cache(L1-Cache) control register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_SHUT_BUS0</name>
+              <description>The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_SHUT_BUS1</name>
+              <description>The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_SHUT_DBUS2</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_SHUT_DBUS3</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_SHUT_DMA</name>
+              <description>The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_UNDEF_OP</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_BYPASS_CACHE_CONF</name>
+          <description>Bypass Cache configure register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BYPASS_L1_ICACHE0_EN</name>
+              <description>The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYPASS_L1_ICACHE1_EN</name>
+              <description>The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYPASS_L1_ICACHE2_EN</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYPASS_L1_ICACHE3_EN</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYPASS_L1_DCACHE_EN</name>
+              <description>The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ATOMIC_CONF</name>
+          <description>L1 Cache atomic feature configure register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_ATOMIC_EN</name>
+              <description>The bit is used to enable atomic feature on L1-Cache when multiple cores access L1-Cache.  1: disable, 1: enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE_CACHESIZE_CONF</name>
+          <description>L1 instruction Cache CacheSize mode configure register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_1K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_2K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_4K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_8K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_16K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_32K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_64K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_128K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_256K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_512K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_1024K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_2048K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 2048k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_CACHESIZE_4096K</name>
+              <description>The field is used to configure cachesize of L1-ICache as 4096k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE_BLOCKSIZE_CONF</name>
+          <description>L1 instruction Cache BlockSize mode configure register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE_BLOCKSIZE_8</name>
+              <description>The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_BLOCKSIZE_16</name>
+              <description>The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_BLOCKSIZE_32</name>
+              <description>The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_BLOCKSIZE_64</name>
+              <description>The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_BLOCKSIZE_128</name>
+              <description>The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE_BLOCKSIZE_256</name>
+              <description>The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_CACHESIZE_CONF</name>
+          <description>L1 data Cache CacheSize mode configure register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>L1_CACHE_CACHESIZE_1K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 1k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_2K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 2k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_4K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 4k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_8K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 8k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_16K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 16k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_32K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 32k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_64K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 64k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_128K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 128k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_256K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 256k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_512K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 512k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_1024K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_2048K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_CACHESIZE_4096K</name>
+              <description>The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_BLOCKSIZE_CONF</name>
+          <description>L1 data Cache BlockSize mode configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>L1_CACHE_BLOCKSIZE_8</name>
+              <description>The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_BLOCKSIZE_16</name>
+              <description>The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_BLOCKSIZE_32</name>
+              <description>The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_BLOCKSIZE_64</name>
+              <description>The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_BLOCKSIZE_128</name>
+              <description>The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_BLOCKSIZE_256</name>
+              <description>The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_WRAP_AROUND_CTRL</name>
+          <description>Cache wrap around control register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_WRAP</name>
+              <description>Set this bit as 1 to enable L1-ICache0 wrap around mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_WRAP</name>
+              <description>Set this bit as 1 to enable L1-ICache1 wrap around mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_WRAP</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_WRAP</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_WRAP</name>
+              <description>Set this bit as 1 to enable L1-DCache wrap around mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_TAG_MEM_POWER_CTRL</name>
+          <description>Cache tag memory power control register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00055555</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_TAG_MEM_FORCE_ON</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_TAG_MEM_FORCE_PD</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_TAG_MEM_FORCE_PU</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_TAG_MEM_FORCE_ON</name>
+              <description>Reserved</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_TAG_MEM_FORCE_PD</name>
+              <description>Reserved</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_TAG_MEM_FORCE_PU</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_DATA_MEM_POWER_CTRL</name>
+          <description>Cache data memory power control register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00055555</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_DATA_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_DATA_MEM_FORCE_PD</name>
+              <description>The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_DATA_MEM_FORCE_PU</name>
+              <description>The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_DATA_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_DATA_MEM_FORCE_PD</name>
+              <description>The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_DATA_MEM_FORCE_PU</name>
+              <description>The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_DATA_MEM_FORCE_ON</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_DATA_MEM_FORCE_PD</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_DATA_MEM_FORCE_PU</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_DATA_MEM_FORCE_ON</name>
+              <description>Reserved</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_DATA_MEM_FORCE_PD</name>
+              <description>Reserved</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_DATA_MEM_FORCE_PU</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_DATA_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_DATA_MEM_FORCE_PD</name>
+              <description>The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_DATA_MEM_FORCE_PU</name>
+              <description>The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_FREEZE_CTRL</name>
+          <description>Cache Freeze control register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_FREEZE_EN</name>
+              <description>The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_FREEZE_MODE</name>
+              <description>The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_FREEZE_DONE</name>
+              <description>The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_FREEZE_EN</name>
+              <description>The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_FREEZE_MODE</name>
+              <description>The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_FREEZE_DONE</name>
+              <description>The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_FREEZE_EN</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_FREEZE_MODE</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_FREEZE_DONE</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_FREEZE_EN</name>
+              <description>Reserved</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_FREEZE_MODE</name>
+              <description>Reserved</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_FREEZE_DONE</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_FREEZE_EN</name>
+              <description>The bit is used to enable freeze operation on L1-Cache. It can be cleared by software.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_FREEZE_MODE</name>
+              <description>The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_FREEZE_DONE</name>
+              <description>The bit is used to indicate whether freeze operation on L1-Cache is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_DATA_MEM_ACS_CONF</name>
+          <description>Cache data memory access configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00033333</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_DATA_MEM_RD_EN</name>
+              <description>The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_DATA_MEM_WR_EN</name>
+              <description>The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_DATA_MEM_RD_EN</name>
+              <description>The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_DATA_MEM_WR_EN</name>
+              <description>The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_DATA_MEM_RD_EN</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_DATA_MEM_WR_EN</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_DATA_MEM_RD_EN</name>
+              <description>Reserved</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_DATA_MEM_WR_EN</name>
+              <description>Reserved</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_DATA_MEM_RD_EN</name>
+              <description>The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_DATA_MEM_WR_EN</name>
+              <description>The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_TAG_MEM_ACS_CONF</name>
+          <description>Cache tag memory access configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00033333</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_TAG_MEM_RD_EN</name>
+              <description>The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_TAG_MEM_WR_EN</name>
+              <description>The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_TAG_MEM_RD_EN</name>
+              <description>The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_TAG_MEM_WR_EN</name>
+              <description>The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_TAG_MEM_RD_EN</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_TAG_MEM_WR_EN</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_TAG_MEM_RD_EN</name>
+              <description>Reserved</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_TAG_MEM_WR_EN</name>
+              <description>Reserved</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_TAG_MEM_RD_EN</name>
+              <description>The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_TAG_MEM_WR_EN</name>
+              <description>The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_PRELOCK_CONF</name>
+          <description>L1 instruction Cache 0 prelock configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PRELOCK_SCT0_EN</name>
+              <description>The bit is used to enable the first section of prelock function on L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PRELOCK_SCT1_EN</name>
+              <description>The bit is used to enable the second section of prelock function on L1-ICache0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PRELOCK_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache0 prelock.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_PRELOCK_SCT0_ADDR</name>
+          <description>L1 instruction Cache 0 prelock section0 address configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PRELOCK_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_PRELOCK_SCT1_ADDR</name>
+          <description>L1 instruction Cache 0 prelock section1 address configure register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PRELOCK_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_PRELOCK_SCT_SIZE</name>
+          <description>L1 instruction Cache 0 prelock section size configure register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3FFF3FFF</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PRELOCK_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PRELOCK_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_PRELOCK_CONF</name>
+          <description>L1 instruction Cache 1 prelock configure register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_PRELOCK_SCT0_EN</name>
+              <description>The bit is used to enable the first section of prelock function on L1-ICache1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PRELOCK_SCT1_EN</name>
+              <description>The bit is used to enable the second section of prelock function on L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PRELOCK_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache1 prelock.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_PRELOCK_SCT0_ADDR</name>
+          <description>L1 instruction Cache 1 prelock section0 address configure register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_PRELOCK_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_PRELOCK_SCT1_ADDR</name>
+          <description>L1 instruction Cache 1 prelock section1 address configure register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_PRELOCK_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_PRELOCK_SCT_SIZE</name>
+          <description>L1 instruction Cache 1 prelock section size configure register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3FFF3FFF</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_PRELOCK_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PRELOCK_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_PRELOCK_CONF</name>
+          <description>L1 instruction Cache 2 prelock configure register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_PRELOCK_SCT0_EN</name>
+              <description>The bit is used to enable the first section of prelock function on L1-ICache2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PRELOCK_SCT1_EN</name>
+              <description>The bit is used to enable the second section of prelock function on L1-ICache2.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PRELOCK_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache2 prelock.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_PRELOCK_SCT0_ADDR</name>
+          <description>L1 instruction Cache 2 prelock section0 address configure register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_PRELOCK_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_PRELOCK_SCT1_ADDR</name>
+          <description>L1 instruction Cache 2 prelock section1 address configure register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_PRELOCK_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_PRELOCK_SCT_SIZE</name>
+          <description>L1 instruction Cache 2 prelock section size configure register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3FFF3FFF</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_PRELOCK_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PRELOCK_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_PRELOCK_CONF</name>
+          <description>L1 instruction Cache 3 prelock configure register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_PRELOCK_SCT0_EN</name>
+              <description>The bit is used to enable the first section of prelock function on L1-ICache3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PRELOCK_SCT1_EN</name>
+              <description>The bit is used to enable the second section of prelock function on L1-ICache3.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PRELOCK_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache3 prelock.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_PRELOCK_SCT0_ADDR</name>
+          <description>L1 instruction Cache 3 prelock section0 address configure register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_PRELOCK_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_PRELOCK_SCT1_ADDR</name>
+          <description>L1 instruction Cache 3 prelock section1 address configure register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_PRELOCK_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_PRELOCK_SCT_SIZE</name>
+          <description>L1 instruction Cache 3 prelock section size configure register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3FFF3FFF</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_PRELOCK_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PRELOCK_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_PRELOCK_CONF</name>
+          <description>L1 Cache prelock configure register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_PRELOCK_SCT0_EN</name>
+              <description>The bit is used to enable the first section of prelock function on L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PRELOCK_SCT1_EN</name>
+              <description>The bit is used to enable the second section of prelock function on L1-Cache.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PRELOCK_RGID</name>
+              <description>The bit is used to set  the gid of l1 cache prelock.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_PRELOCK_SCT0_ADDR</name>
+          <description>L1 Cache prelock section0 address configure register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_PRELOCK_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DCACHE_PRELOCK_SCT1_ADDR</name>
+          <description>L1 Cache prelock section1 address configure register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_PRELOCK_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DCACHE_PRELOCK_SCT_SIZE</name>
+          <description>L1  Cache prelock section size configure register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3FFF3FFF</resetValue>
+          <fields>
+            <field>
+              <name>L1_CACHE_PRELOCK_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PRELOCK_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_LOCK_CTRL</name>
+          <description>Lock-class (manual lock) operation control register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_LOCK_ENA</name>
+              <description>The bit is used to enable lock operation. It will be cleared by hardware after lock operation done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_UNLOCK_ENA</name>
+              <description>The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_LOCK_DONE</name>
+              <description>The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_LOCK_RGID</name>
+              <description>The bit is used to set  the gid of cache lock/unlock.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_LOCK_MAP</name>
+          <description>Lock (manual lock) map configure register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_LOCK_MAP</name>
+              <description>Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [4]: L1-Cache</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_LOCK_ADDR</name>
+          <description>Lock (manual lock) address configure register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_LOCK_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_LOCK_SIZE</name>
+          <description>Lock (manual lock) size configure register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_LOCK_SIZE</name>
+              <description>Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SYNC_CTRL</name>
+          <description>Sync-class operation control register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_INVALIDATE_ENA</name>
+              <description>The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_CLEAN_ENA</name>
+              <description>The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_WRITEBACK_ENA</name>
+              <description>The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_WRITEBACK_INVALIDATE_ENA</name>
+              <description>The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_DONE</name>
+              <description>The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_RGID</name>
+              <description>The bit is used to set  the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate)</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SYNC_MAP</name>
+          <description>Sync map configure register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_SYNC_MAP</name>
+              <description>Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation.  [4]: L1-Cache</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SYNC_ADDR</name>
+          <description>Sync address configure register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_SYNC_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SYNC_SIZE</name>
+          <description>Sync size configure register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_SYNC_SIZE</name>
+              <description>Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_PRELOAD_CTRL</name>
+          <description>L1 instruction Cache 0 preload-operation control register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PRELOAD_DONE</name>
+              <description>The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PRELOAD_ORDER</name>
+              <description>The bit is used to configure the direction of preload operation. 0: ascending, 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PRELOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache0 preload.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_PRELOAD_ADDR</name>
+          <description>L1 instruction Cache 0 preload address configure register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PRELOAD_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_PRELOAD_SIZE</name>
+          <description>L1 instruction Cache 0 preload size configure register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PRELOAD_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_PRELOAD_CTRL</name>
+          <description>L1 instruction Cache 1 preload-operation control register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PRELOAD_DONE</name>
+              <description>The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PRELOAD_ORDER</name>
+              <description>The bit is used to configure the direction of preload operation. 0: ascending, 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PRELOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache1 preload.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_PRELOAD_ADDR</name>
+          <description>L1 instruction Cache 1 preload address configure register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_PRELOAD_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_PRELOAD_SIZE</name>
+          <description>L1 instruction Cache 1 preload size configure register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_PRELOAD_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_PRELOAD_CTRL</name>
+          <description>L1 instruction Cache 2 preload-operation control register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PRELOAD_DONE</name>
+              <description>The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PRELOAD_ORDER</name>
+              <description>The bit is used to configure the direction of preload operation. 0: ascending, 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PRELOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache2 preload.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_PRELOAD_ADDR</name>
+          <description>L1 instruction Cache 2 preload address configure register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_PRELOAD_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_PRELOAD_SIZE</name>
+          <description>L1 instruction Cache 2 preload size configure register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_PRELOAD_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_PRELOAD_CTRL</name>
+          <description>L1 instruction Cache 3 preload-operation control register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PRELOAD_DONE</name>
+              <description>The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PRELOAD_ORDER</name>
+              <description>The bit is used to configure the direction of preload operation. 0: ascending, 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PRELOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache3 preload.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_PRELOAD_ADDR</name>
+          <description>L1 instruction Cache 3 preload address configure register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_PRELOAD_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_PRELOAD_SIZE</name>
+          <description>L1 instruction Cache 3 preload size configure register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_PRELOAD_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_PRELOAD_CTRL</name>
+          <description>L1 Cache  preload-operation control register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_CACHE_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation on L1-Cache. It will be cleared by hardware automatically after preload operation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PRELOAD_DONE</name>
+              <description>The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PRELOAD_ORDER</name>
+              <description>The bit is used to configure the direction of preload operation. 0: ascending, 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PRELOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 cache preload.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DCACHE_PRELOAD_ADDR</name>
+          <description>L1 Cache  preload address configure register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_PRELOAD_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of preload on L1-Cache, which should be used together with L1_CACHE_PRELOAD_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DCACHE_PRELOAD_SIZE</name>
+          <description>L1 Cache  preload size configure register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_PRELOAD_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_AUTOLOAD_CTRL</name>
+          <description>L1 instruction Cache 0 autoload-operation control register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable, 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_ORDER</name>
+              <description>The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_TRIGGER_MODE</name>
+              <description>The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_SCT0_ENA</name>
+              <description>The bit is used to enable the first section for autoload operation on L1-ICache0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_SCT1_ENA</name>
+              <description>The bit is used to enable the second section for autoload operation on L1-ICache0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache0 autoload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_AUTOLOAD_SCT0_ADDR</name>
+          <description>L1 instruction Cache 0 autoload section 0 address configure register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_AUTOLOAD_SCT0_SIZE</name>
+          <description>L1 instruction Cache 0 autoload section 0 size configure register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_AUTOLOAD_SCT1_ADDR</name>
+          <description>L1 instruction Cache 0 autoload section 1 address configure register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_AUTOLOAD_SCT1_SIZE</name>
+          <description>L1 instruction Cache 0 autoload section 1 size configure register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_AUTOLOAD_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_AUTOLOAD_CTRL</name>
+          <description>L1 instruction Cache 1 autoload-operation control register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable, 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_ORDER</name>
+              <description>The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_TRIGGER_MODE</name>
+              <description>The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_SCT0_ENA</name>
+              <description>The bit is used to enable the first section for autoload operation on L1-ICache1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_SCT1_ENA</name>
+              <description>The bit is used to enable the second section for autoload operation on L1-ICache1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache1 autoload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_AUTOLOAD_SCT0_ADDR</name>
+          <description>L1 instruction Cache 1 autoload section 0 address configure register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_AUTOLOAD_SCT0_SIZE</name>
+          <description>L1 instruction Cache 1 autoload section 0 size configure register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_AUTOLOAD_SCT1_ADDR</name>
+          <description>L1 instruction Cache 1 autoload section 1 address configure register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_AUTOLOAD_SCT1_SIZE</name>
+          <description>L1 instruction Cache 1 autoload section 1 size configure register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_AUTOLOAD_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_AUTOLOAD_CTRL</name>
+          <description>L1 instruction Cache 2 autoload-operation control register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable, 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_ORDER</name>
+              <description>The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_TRIGGER_MODE</name>
+              <description>The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_SCT0_ENA</name>
+              <description>The bit is used to enable the first section for autoload operation on L1-ICache2.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_SCT1_ENA</name>
+              <description>The bit is used to enable the second section for autoload operation on L1-ICache2.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache2 autoload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_AUTOLOAD_SCT0_ADDR</name>
+          <description>L1 instruction Cache 2 autoload section 0 address configure register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_AUTOLOAD_SCT0_SIZE</name>
+          <description>L1 instruction Cache 2 autoload section 0 size configure register</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_AUTOLOAD_SCT1_ADDR</name>
+          <description>L1 instruction Cache 2 autoload section 1 address configure register</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_AUTOLOAD_SCT1_SIZE</name>
+          <description>L1 instruction Cache 2 autoload section 1 size configure register</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_AUTOLOAD_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_AUTOLOAD_CTRL</name>
+          <description>L1 instruction Cache 3 autoload-operation control register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable, 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_ORDER</name>
+              <description>The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_TRIGGER_MODE</name>
+              <description>The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_SCT0_ENA</name>
+              <description>The bit is used to enable the first section for autoload operation on L1-ICache3.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_SCT1_ENA</name>
+              <description>The bit is used to enable the second section for autoload operation on L1-ICache3.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 icache3 autoload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_AUTOLOAD_SCT0_ADDR</name>
+          <description>L1 instruction Cache 3 autoload section 0 address configure register</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_AUTOLOAD_SCT0_SIZE</name>
+          <description>L1 instruction Cache 3 autoload section 0 size configure register</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_AUTOLOAD_SCT1_ADDR</name>
+          <description>L1 instruction Cache 3 autoload section 1 address configure register</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_AUTOLOAD_SCT1_SIZE</name>
+          <description>L1 instruction Cache 3 autoload section 1 size configure register</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_AUTOLOAD_SCT1_SIZE</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_CTRL</name>
+          <description>L1 Cache autoload-operation control register</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable autoload operation on L1-Cache.  1: enable, 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate whether autoload operation on L1-Cache is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_ORDER</name>
+              <description>The bit is used to configure the direction of autoload operation on L1-Cache. 0: ascending. 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_TRIGGER_MODE</name>
+              <description>The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT0_ENA</name>
+              <description>The bit is used to enable the first section for autoload operation on L1-Cache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT1_ENA</name>
+              <description>The bit is used to enable the second section for autoload operation on L1-Cache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT2_ENA</name>
+              <description>The bit is used to enable the third section for autoload operation on L1-Cache.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT3_ENA</name>
+              <description>The bit is used to enable the fourth section for autoload operation on L1-Cache.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_RGID</name>
+              <description>The bit is used to set  the gid of l1 cache autoload.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_SCT0_ADDR</name>
+          <description>L1 Cache autoload section 0 address configure register</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_SCT0_SIZE</name>
+          <description>L1 Cache autoload section 0 size configure register</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_SCT1_ADDR</name>
+          <description>L1 Cache autoload section 1 address configure register</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_SCT1_SIZE</name>
+          <description>L1 Cache autoload section 1 size configure register</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_SCT2_ADDR</name>
+          <description>L1 Cache autoload section 2 address configure register</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT2_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the third section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_SCT2_SIZE</name>
+          <description>L1 Cache autoload section 2 size configure register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT2_SIZE</name>
+              <description>Those bits are used to configure the size of the third section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_SCT3_ADDR</name>
+          <description>L1 Cache autoload section 1 address configure register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT3_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_SCT3_SIZE</name>
+          <description>L1 Cache autoload section 1 size configure register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_AUTOLOAD_SCT3_SIZE</name>
+              <description>Those bits are used to configure the size of the fourth section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_CNT_INT_ENA</name>
+          <description>Cache Access Counter Interrupt enable register</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS0_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS1_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS2_OVF_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS3_OVF_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_BUS0_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_BUS1_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_DBUS2_OVF_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS3_OVF_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_CNT_INT_CLR</name>
+          <description>Cache Access Counter Interrupt clear register</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS0_OVF_INT_CLR</name>
+              <description>The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS1_OVF_INT_CLR</name>
+              <description>The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS2_OVF_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS3_OVF_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_BUS0_OVF_INT_CLR</name>
+              <description>The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>L1_BUS1_OVF_INT_CLR</name>
+              <description>The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS2_OVF_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS3_OVF_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_CNT_INT_RAW</name>
+          <description>Cache Access Counter Interrupt raw register</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS0_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS1_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS2_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS3_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_BUS0_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_BUS1_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS2_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS3_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_CNT_INT_ST</name>
+          <description>Cache Access Counter Interrupt status register</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS0_OVF_INT_ST</name>
+              <description>The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS1_OVF_INT_ST</name>
+              <description>The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS2_OVF_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS3_OVF_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_BUS0_OVF_INT_ST</name>
+              <description>The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_BUS1_OVF_INT_ST</name>
+              <description>The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS2_OVF_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS3_OVF_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_FAIL_INT_ENA</name>
+          <description>Cache Access Fail Interrupt enable register</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_FAIL_INT_ENA</name>
+              <description>The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_FAIL_INT_ENA</name>
+              <description>The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_FAIL_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_FAIL_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_FAIL_INT_ENA</name>
+              <description>The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_FAIL_INT_CLR</name>
+          <description>L1-Cache Access Fail Interrupt clear register</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_FAIL_INT_CLR</name>
+              <description>The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_FAIL_INT_CLR</name>
+              <description>The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_FAIL_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_FAIL_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_FAIL_INT_CLR</name>
+              <description>The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_FAIL_INT_RAW</name>
+          <description>Cache Access Fail Interrupt raw register</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_FAIL_INT_RAW</name>
+              <description>The raw bit of the interrupt of access fail that occurs in L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_FAIL_INT_RAW</name>
+              <description>The raw bit of the interrupt of access fail that occurs in L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_FAIL_INT_RAW</name>
+              <description>The raw bit of the interrupt of access fail that occurs in L1-ICache2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_FAIL_INT_RAW</name>
+              <description>The raw bit of the interrupt of access fail that occurs in L1-ICache3.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_FAIL_INT_RAW</name>
+              <description>The raw bit of the interrupt of access fail that occurs in L1-DCache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_FAIL_INT_ST</name>
+          <description>Cache Access Fail Interrupt status register</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_FAIL_INT_ST</name>
+              <description>The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_FAIL_INT_ST</name>
+              <description>The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_FAIL_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_FAIL_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_FAIL_INT_ST</name>
+              <description>The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_CNT_CTRL</name>
+          <description>Cache Access Counter enable and clear register</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS0_CNT_ENA</name>
+              <description>The bit is used to enable ibus0 counter in L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS1_CNT_ENA</name>
+              <description>The bit is used to enable ibus1 counter in L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS2_CNT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS3_CNT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_BUS0_CNT_ENA</name>
+              <description>The bit is used to enable dbus0 counter in L1-DCache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_BUS1_CNT_ENA</name>
+              <description>The bit is used to enable dbus1 counter in L1-DCache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_DBUS2_CNT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS3_CNT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS0_CNT_CLR</name>
+              <description>The bit is used to clear ibus0 counter in L1-ICache0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS1_CNT_CLR</name>
+              <description>The bit is used to clear ibus1 counter in L1-ICache1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS2_CNT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_IBUS3_CNT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_BUS0_CNT_CLR</name>
+              <description>The bit is used to clear dbus0 counter in L1-DCache.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>L1_BUS1_CNT_CLR</name>
+              <description>The bit is used to clear dbus1 counter in L1-DCache.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS2_CNT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_DBUS3_CNT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS0_ACS_HIT_CNT</name>
+          <description>L1-ICache bus0 Hit-Access Counter register</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS0_HIT_CNT</name>
+              <description>The register records the number of hits when bus0 accesses L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS0_ACS_MISS_CNT</name>
+          <description>L1-ICache bus0 Miss-Access Counter register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS0_MISS_CNT</name>
+              <description>The register records the number of missing when bus0 accesses L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS0_ACS_CONFLICT_CNT</name>
+          <description>L1-ICache bus0 Conflict-Access Counter register</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS0_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when bus0 accesses L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS0_ACS_NXTLVL_CNT</name>
+          <description>L1-ICache bus0 Next-Level-Access Counter register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS0_NXTLVL_CNT</name>
+              <description>The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS1_ACS_HIT_CNT</name>
+          <description>L1-ICache bus1 Hit-Access Counter register</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS1_HIT_CNT</name>
+              <description>The register records the number of hits when bus1 accesses L1-ICache1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS1_ACS_MISS_CNT</name>
+          <description>L1-ICache bus1 Miss-Access Counter register</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS1_MISS_CNT</name>
+              <description>The register records the number of missing when bus1 accesses L1-ICache1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS1_ACS_CONFLICT_CNT</name>
+          <description>L1-ICache bus1 Conflict-Access Counter register</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS1_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when bus1 accesses L1-ICache1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS1_ACS_NXTLVL_CNT</name>
+          <description>L1-ICache bus1 Next-Level-Access Counter register</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS1_NXTLVL_CNT</name>
+              <description>The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS2_ACS_HIT_CNT</name>
+          <description>L1-ICache bus2 Hit-Access Counter register</description>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS2_HIT_CNT</name>
+              <description>The register records the number of hits when bus2 accesses L1-ICache2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS2_ACS_MISS_CNT</name>
+          <description>L1-ICache bus2 Miss-Access Counter register</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS2_MISS_CNT</name>
+              <description>The register records the number of missing when bus2 accesses L1-ICache2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS2_ACS_CONFLICT_CNT</name>
+          <description>L1-ICache bus2 Conflict-Access Counter register</description>
+          <addressOffset>0x1A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS2_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when bus2 accesses L1-ICache2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS2_ACS_NXTLVL_CNT</name>
+          <description>L1-ICache bus2 Next-Level-Access Counter register</description>
+          <addressOffset>0x1A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS2_NXTLVL_CNT</name>
+              <description>The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS3_ACS_HIT_CNT</name>
+          <description>L1-ICache bus3 Hit-Access Counter register</description>
+          <addressOffset>0x1AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS3_HIT_CNT</name>
+              <description>The register records the number of hits when bus3 accesses L1-ICache3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS3_ACS_MISS_CNT</name>
+          <description>L1-ICache bus3 Miss-Access Counter register</description>
+          <addressOffset>0x1B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS3_MISS_CNT</name>
+              <description>The register records the number of missing when bus3 accesses L1-ICache3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS3_ACS_CONFLICT_CNT</name>
+          <description>L1-ICache bus3 Conflict-Access Counter register</description>
+          <addressOffset>0x1B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS3_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when bus3 accesses L1-ICache3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_IBUS3_ACS_NXTLVL_CNT</name>
+          <description>L1-ICache bus3 Next-Level-Access Counter register</description>
+          <addressOffset>0x1B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_IBUS3_NXTLVL_CNT</name>
+              <description>The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_BUS0_ACS_HIT_CNT</name>
+          <description>L1-Cache bus0 Hit-Access Counter register</description>
+          <addressOffset>0x1BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_BUS0_HIT_CNT</name>
+              <description>The register records the number of hits when bus0 accesses L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_BUS0_ACS_MISS_CNT</name>
+          <description>L1-Cache bus0 Miss-Access Counter register</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_BUS0_MISS_CNT</name>
+              <description>The register records the number of missing when bus0 accesses L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_BUS0_ACS_CONFLICT_CNT</name>
+          <description>L1-Cache bus0 Conflict-Access Counter register</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_BUS0_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when bus0 accesses L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_BUS0_ACS_NXTLVL_CNT</name>
+          <description>L1-Cache bus0 Next-Level-Access Counter register</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_BUS0_NXTLVL_CNT</name>
+              <description>The register records the number of times that L1-Cache accesses L2-Cache due to bus0 accessing L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_BUS1_ACS_HIT_CNT</name>
+          <description>L1-Cache bus1 Hit-Access Counter register</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_BUS1_HIT_CNT</name>
+              <description>The register records the number of hits when bus1 accesses L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_BUS1_ACS_MISS_CNT</name>
+          <description>L1-Cache bus1 Miss-Access Counter register</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_BUS1_MISS_CNT</name>
+              <description>The register records the number of missing when bus1 accesses L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_BUS1_ACS_CONFLICT_CNT</name>
+          <description>L1-Cache bus1 Conflict-Access Counter register</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_BUS1_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when bus1 accesses L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_BUS1_ACS_NXTLVL_CNT</name>
+          <description>L1-Cache bus1 Next-Level-Access Counter register</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_BUS1_NXTLVL_CNT</name>
+              <description>The register records the number of times that L1-Cache accesses L2-Cache due to bus1 accessing L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DBUS2_ACS_HIT_CNT</name>
+          <description>L1-DCache bus2 Hit-Access Counter register</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_DBUS2_HIT_CNT</name>
+              <description>The register records the number of hits when bus2 accesses L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DBUS2_ACS_MISS_CNT</name>
+          <description>L1-DCache bus2 Miss-Access Counter register</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_DBUS2_MISS_CNT</name>
+              <description>The register records the number of missing when bus2 accesses L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DBUS2_ACS_CONFLICT_CNT</name>
+          <description>L1-DCache bus2 Conflict-Access Counter register</description>
+          <addressOffset>0x1E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_DBUS2_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when bus2 accesses L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DBUS2_ACS_NXTLVL_CNT</name>
+          <description>L1-DCache bus2 Next-Level-Access Counter register</description>
+          <addressOffset>0x1E8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_DBUS2_NXTLVL_CNT</name>
+              <description>The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DBUS3_ACS_HIT_CNT</name>
+          <description>L1-DCache bus3 Hit-Access Counter register</description>
+          <addressOffset>0x1EC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_DBUS3_HIT_CNT</name>
+              <description>The register records the number of hits when bus3 accesses L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DBUS3_ACS_MISS_CNT</name>
+          <description>L1-DCache bus3 Miss-Access Counter register</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_DBUS3_MISS_CNT</name>
+              <description>The register records the number of missing when bus3 accesses L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DBUS3_ACS_CONFLICT_CNT</name>
+          <description>L1-DCache bus3 Conflict-Access Counter register</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_DBUS3_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when bus3 accesses L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DBUS3_ACS_NXTLVL_CNT</name>
+          <description>L1-DCache bus3 Next-Level-Access Counter register</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_DBUS3_NXTLVL_CNT</name>
+              <description>The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_ACS_FAIL_ID_ATTR</name>
+          <description>L1-ICache0 Access Fail ID/attribution information register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_FAIL_ID</name>
+              <description>The register records the ID of fail-access when cache0 accesses L1-ICache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_FAIL_ATTR</name>
+              <description>The register records the attribution of fail-access when cache0 accesses L1-ICache.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE0_ACS_FAIL_ADDR</name>
+          <description>L1-ICache0 Access Fail Address information register</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_FAIL_ADDR</name>
+              <description>The register records the address of fail-access when cache0 accesses L1-ICache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_ACS_FAIL_ID_ATTR</name>
+          <description>L1-ICache0 Access Fail ID/attribution information register</description>
+          <addressOffset>0x204</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_FAIL_ID</name>
+              <description>The register records the ID of fail-access when cache1 accesses L1-ICache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_FAIL_ATTR</name>
+              <description>The register records the attribution of fail-access when cache1 accesses L1-ICache.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE1_ACS_FAIL_ADDR</name>
+          <description>L1-ICache0 Access Fail Address information register</description>
+          <addressOffset>0x208</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE1_FAIL_ADDR</name>
+              <description>The register records the address of fail-access when cache1 accesses L1-ICache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_ACS_FAIL_ID_ATTR</name>
+          <description>L1-ICache0 Access Fail ID/attribution information register</description>
+          <addressOffset>0x20C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_FAIL_ID</name>
+              <description>The register records the ID of fail-access when cache2 accesses L1-ICache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_FAIL_ATTR</name>
+              <description>The register records the attribution of fail-access when cache2 accesses L1-ICache.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE2_ACS_FAIL_ADDR</name>
+          <description>L1-ICache0 Access Fail Address information register</description>
+          <addressOffset>0x210</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE2_FAIL_ADDR</name>
+              <description>The register records the address of fail-access when cache2 accesses L1-ICache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_ACS_FAIL_ID_ATTR</name>
+          <description>L1-ICache0 Access Fail ID/attribution information register</description>
+          <addressOffset>0x214</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_FAIL_ID</name>
+              <description>The register records the ID of fail-access when cache3 accesses L1-ICache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_FAIL_ATTR</name>
+              <description>The register records the attribution of fail-access when cache3 accesses L1-ICache.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_ICACHE3_ACS_FAIL_ADDR</name>
+          <description>L1-ICache0 Access Fail Address information register</description>
+          <addressOffset>0x218</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE3_FAIL_ADDR</name>
+              <description>The register records the address of fail-access when cache3 accesses L1-ICache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_ACS_FAIL_ID_ATTR</name>
+          <description>L1-Cache Access Fail ID/attribution information register</description>
+          <addressOffset>0x21C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_FAIL_ID</name>
+              <description>The register records the ID of fail-access when cache accesses L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_FAIL_ATTR</name>
+              <description>The register records the attribution of fail-access when cache accesses L1-Cache.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_DCACHE_ACS_FAIL_ADDR</name>
+          <description>L1-Cache Access Fail Address information register</description>
+          <addressOffset>0x220</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_FAIL_ADDR</name>
+              <description>The register records the address of fail-access when cache accesses L1-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_SYNC_PRELOAD_INT_ENA</name>
+          <description>L1-Cache Access Fail Interrupt enable register</description>
+          <addressOffset>0x224</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PLD_DONE_INT_ENA</name>
+              <description>The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_DONE_INT_ENA</name>
+              <description>The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_DONE_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_DONE_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_DONE_INT_ENA</name>
+              <description>The bit is used to enable interrupt of L1-Cache preload-operation. If preload operation is done, interrupt occurs.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_DONE_INT_ENA</name>
+              <description>The bit is used to enable interrupt of Cache sync-operation done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PLD_ERR_INT_ENA</name>
+              <description>The bit is used to enable interrupt of L1-ICache0 preload-operation error.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_ERR_INT_ENA</name>
+              <description>The bit is used to enable interrupt of L1-ICache1 preload-operation error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_ERR_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_ERR_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_ERR_INT_ENA</name>
+              <description>The bit is used to enable interrupt of L1-Cache preload-operation error.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_ERR_INT_ENA</name>
+              <description>The bit is used to enable interrupt of Cache sync-operation error.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_SYNC_PRELOAD_INT_CLR</name>
+          <description>Sync Preload operation Interrupt clear register</description>
+          <addressOffset>0x228</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PLD_DONE_INT_CLR</name>
+              <description>The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_DONE_INT_CLR</name>
+              <description>The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_DONE_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_DONE_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_DONE_INT_CLR</name>
+              <description>The bit is used to clear interrupt that occurs only when L1-Cache preload-operation is done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_DONE_INT_CLR</name>
+              <description>The bit is used to clear interrupt that occurs only when Cache sync-operation is done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PLD_ERR_INT_CLR</name>
+              <description>The bit is used to clear interrupt of L1-ICache0 preload-operation error.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_ERR_INT_CLR</name>
+              <description>The bit is used to clear interrupt of L1-ICache1 preload-operation error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_ERR_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_ERR_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_ERR_INT_CLR</name>
+              <description>The bit is used to clear interrupt of L1-Cache preload-operation error.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_ERR_INT_CLR</name>
+              <description>The bit is used to clear interrupt of Cache sync-operation error.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_SYNC_PRELOAD_INT_RAW</name>
+          <description>Sync Preload operation Interrupt raw register</description>
+          <addressOffset>0x22C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PLD_DONE_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_DONE_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_DONE_INT_RAW</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_DONE_INT_RAW</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_DONE_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when L1-Cache preload-operation is done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_DONE_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when Cache sync-operation is done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PLD_ERR_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_ERR_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_ERR_INT_RAW</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_ERR_INT_RAW</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_ERR_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when L1-Cache preload-operation error occurs.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_ERR_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when Cache sync-operation error occurs.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_SYNC_PRELOAD_INT_ST</name>
+          <description>L1-Cache Access Fail Interrupt status register</description>
+          <addressOffset>0x230</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PLD_DONE_INT_ST</name>
+              <description>The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_DONE_INT_ST</name>
+              <description>The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_DONE_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_DONE_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_DONE_INT_ST</name>
+              <description>The bit indicates the status of the interrupt that occurs only when L1-Cache preload-operation is done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_DONE_INT_ST</name>
+              <description>The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_PLD_ERR_INT_ST</name>
+              <description>The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_ERR_INT_ST</name>
+              <description>The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_ERR_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_ERR_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_ERR_INT_ST</name>
+              <description>The bit indicates the status of the interrupt of L1-Cache preload-operation error.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_ERR_INT_ST</name>
+              <description>The bit indicates the status of the interrupt of Cache sync-operation error.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_SYNC_PRELOAD_EXCEPTION</name>
+          <description>Cache Sync/Preload Operation exception register</description>
+          <addressOffset>0x234</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PLD_ERR_CODE</name>
+              <description>The value 2 is Only available which means preload size is error in L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_ERR_CODE</name>
+              <description>The value 2 is Only available which means preload size is error in L1-ICache1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_ERR_CODE</name>
+              <description>Reserved</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_ERR_CODE</name>
+              <description>Reserved</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_ERR_CODE</name>
+              <description>The value 2 is Only available which means preload size is error in L1-Cache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_SYNC_ERR_CODE</name>
+              <description>The values 0-2 are available which means sync map, command conflict and size are error in Cache System.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_SYNC_RST_CTRL</name>
+          <description>Cache Sync Reset control register</description>
+          <addressOffset>0x238</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_SYNC_RST</name>
+              <description>set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_SYNC_RST</name>
+              <description>set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_SYNC_RST</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_SYNC_RST</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_SYNC_RST</name>
+              <description>set this bit to reset sync-logic inside L1-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_PRELOAD_RST_CTRL</name>
+          <description>Cache Preload Reset control register</description>
+          <addressOffset>0x23C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_PLD_RST</name>
+              <description>set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_PLD_RST</name>
+              <description>set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_PLD_RST</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_PLD_RST</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_PLD_RST</name>
+              <description>set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_AUTOLOAD_BUF_CLR_CTRL</name>
+          <description>Cache Autoload buffer clear control register</description>
+          <addressOffset>0x240</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_ALD_BUF_CLR</name>
+              <description>set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_ALD_BUF_CLR</name>
+              <description>set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_ALD_BUF_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_ALD_BUF_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_ALD_BUF_CLR</name>
+              <description>set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, autoload will not work in L1-Cache. This bit should not be active when autoload works in L1-Cache.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_UNALLOCATE_BUFFER_CLEAR</name>
+          <description>Unallocate request buffer clear registers</description>
+          <addressOffset>0x244</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_UNALLOC_CLR</name>
+              <description>The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_UNALLOC_CLR</name>
+              <description>The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_UNALLOC_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_UNALLOC_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_UNALLOC_CLR</name>
+              <description>The bit is used to clear the unallocate request buffer of l1 cache where the unallocate request is responsed but not completed.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_OBJECT_CTRL</name>
+          <description>Cache Tag and Data memory Object control register</description>
+          <addressOffset>0x248</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_ICACHE0_TAG_OBJECT</name>
+              <description>Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_TAG_OBJECT</name>
+              <description>Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_TAG_OBJECT</name>
+              <description>Reserved</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_TAG_OBJECT</name>
+              <description>Reserved</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_TAG_OBJECT</name>
+              <description>Set this bit to set L1-Cache tag memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L1_ICACHE0_MEM_OBJECT</name>
+              <description>Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE1_MEM_OBJECT</name>
+              <description>Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE2_MEM_OBJECT</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_ICACHE3_MEM_OBJECT</name>
+              <description>Reserved</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1_CACHE_MEM_OBJECT</name>
+              <description>Set this bit to set L1-Cache data memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_WAY_OBJECT</name>
+          <description>Cache Tag and Data memory way register</description>
+          <addressOffset>0x24C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L1_CACHE_WAY_OBJECT</name>
+              <description>Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_VADDR</name>
+          <description>Cache Vaddr register</description>
+          <addressOffset>0x250</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>L1_CACHE_VADDR</name>
+              <description>Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L1_CACHE_DEBUG_BUS</name>
+          <description>Cache Tag/data memory content register</description>
+          <addressOffset>0x254</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000254</resetValue>
+          <fields>
+            <field>
+              <name>L1_CACHE_DEBUG_BUS</name>
+              <description>This is a constant place where we can write data to or read data from the tag/data memory on the specified cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LEVEL_SPLIT0</name>
+          <description>USED TO SPLIT L1 CACHE AND L2 CACHE</description>
+          <addressOffset>0x258</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000258</resetValue>
+          <fields>
+            <field>
+              <name>LEVEL_SPLIT0</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_CTRL</name>
+          <description>L2 Cache(L2-Cache) control register</description>
+          <addressOffset>0x25C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_SHUT_DMA</name>
+              <description>The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_UNDEF_OP</name>
+              <description>Reserved</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_BYPASS_CACHE_CONF</name>
+          <description>Bypass Cache configure register</description>
+          <addressOffset>0x260</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BYPASS_L2_CACHE_EN</name>
+              <description>The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_CACHESIZE_CONF</name>
+          <description>L2 Cache CacheSize mode configure register</description>
+          <addressOffset>0x264</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_CACHESIZE_1K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_2K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_4K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_8K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_16K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_32K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_64K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_128K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_256K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_512K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_1024K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_2048K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_CACHESIZE_4096K</name>
+              <description>The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_BLOCKSIZE_CONF</name>
+          <description>L2 Cache BlockSize mode configure register</description>
+          <addressOffset>0x268</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_BLOCKSIZE_8</name>
+              <description>The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_BLOCKSIZE_16</name>
+              <description>The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_BLOCKSIZE_32</name>
+              <description>The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_BLOCKSIZE_64</name>
+              <description>The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_BLOCKSIZE_128</name>
+              <description>The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_BLOCKSIZE_256</name>
+              <description>The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_WRAP_AROUND_CTRL</name>
+          <description>Cache wrap around control register</description>
+          <addressOffset>0x26C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_WRAP</name>
+              <description>Set this bit as 1 to enable L2-Cache wrap around mode.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_TAG_MEM_POWER_CTRL</name>
+          <description>Cache tag memory power control register</description>
+          <addressOffset>0x270</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_DATA_MEM_POWER_CTRL</name>
+          <description>Cache data memory power control register</description>
+          <addressOffset>0x274</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_DATA_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_DATA_MEM_FORCE_PD</name>
+              <description>The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_DATA_MEM_FORCE_PU</name>
+              <description>The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_FREEZE_CTRL</name>
+          <description>Cache Freeze control register</description>
+          <addressOffset>0x278</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_FREEZE_EN</name>
+              <description>The bit is used to enable freeze operation on L2-Cache. It can be cleared by software.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_FREEZE_MODE</name>
+              <description>The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_FREEZE_DONE</name>
+              <description>The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_DATA_MEM_ACS_CONF</name>
+          <description>Cache data memory access configure register</description>
+          <addressOffset>0x27C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_DATA_MEM_RD_EN</name>
+              <description>The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_DATA_MEM_WR_EN</name>
+              <description>The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_TAG_MEM_ACS_CONF</name>
+          <description>Cache tag memory access configure register</description>
+          <addressOffset>0x280</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_TAG_MEM_RD_EN</name>
+              <description>The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_TAG_MEM_WR_EN</name>
+              <description>The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_PRELOCK_CONF</name>
+          <description>L2 Cache prelock configure register</description>
+          <addressOffset>0x284</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PRELOCK_SCT0_EN</name>
+              <description>The bit is used to enable the first section of prelock function on L2-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PRELOCK_SCT1_EN</name>
+              <description>The bit is used to enable the second section of prelock function on L2-Cache.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PRELOCK_RGID</name>
+              <description>The bit is used to set  the gid of l2 cache prelock.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_PRELOCK_SCT0_ADDR</name>
+          <description>L2 Cache prelock section0 address configure register</description>
+          <addressOffset>0x288</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PRELOCK_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_PRELOCK_SCT1_ADDR</name>
+          <description>L2 Cache prelock section1 address configure register</description>
+          <addressOffset>0x28C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PRELOCK_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_PRELOCK_SCT_SIZE</name>
+          <description>L2 Cache prelock section size configure register</description>
+          <addressOffset>0x290</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>L2_CACHE_PRELOCK_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PRELOCK_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_PRELOAD_CTRL</name>
+          <description>L2 Cache preload-operation control register</description>
+          <addressOffset>0x294</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L2_CACHE_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PRELOAD_DONE</name>
+              <description>The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PRELOAD_ORDER</name>
+              <description>The bit is used to configure the direction of preload operation. 0: ascending, 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PRELOAD_RGID</name>
+              <description>The bit is used to set  the gid of l2 cache preload.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_PRELOAD_ADDR</name>
+          <description>L2 Cache preload address configure register</description>
+          <addressOffset>0x298</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PRELOAD_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_PRELOAD_SIZE</name>
+          <description>L2 Cache preload size configure register</description>
+          <addressOffset>0x29C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PRELOAD_SIZE</name>
+              <description>Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_CTRL</name>
+          <description>L2 Cache autoload-operation control register</description>
+          <addressOffset>0x2A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable autoload operation on L2-Cache.  1: enable, 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_ORDER</name>
+              <description>The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_TRIGGER_MODE</name>
+              <description>The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT0_ENA</name>
+              <description>The bit is used to enable the first section for autoload operation on L2-Cache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT1_ENA</name>
+              <description>The bit is used to enable the second section for autoload operation on L2-Cache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT2_ENA</name>
+              <description>The bit is used to enable the third section for autoload operation on L2-Cache.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT3_ENA</name>
+              <description>The bit is used to enable the fourth section for autoload operation on L2-Cache.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_RGID</name>
+              <description>The bit is used to set  the gid of l2 cache autoload.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_SCT0_ADDR</name>
+          <description>L2 Cache autoload section 0 address configure register</description>
+          <addressOffset>0x2A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT0_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_SCT0_SIZE</name>
+          <description>L2 Cache autoload section 0 size configure register</description>
+          <addressOffset>0x2A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT0_SIZE</name>
+              <description>Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_SCT1_ADDR</name>
+          <description>L2 Cache autoload section 1 address configure register</description>
+          <addressOffset>0x2AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT1_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_SCT1_SIZE</name>
+          <description>L2 Cache autoload section 1 size configure register</description>
+          <addressOffset>0x2B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT1_SIZE</name>
+              <description>Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_SCT2_ADDR</name>
+          <description>L2 Cache autoload section 2 address configure register</description>
+          <addressOffset>0x2B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT2_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_SCT2_SIZE</name>
+          <description>L2 Cache autoload section 2 size configure register</description>
+          <addressOffset>0x2B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT2_SIZE</name>
+              <description>Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_SCT3_ADDR</name>
+          <description>L2 Cache autoload section 3 address configure register</description>
+          <addressOffset>0x2BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT3_ADDR</name>
+              <description>Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_SCT3_SIZE</name>
+          <description>L2 Cache autoload section 3 size configure register</description>
+          <addressOffset>0x2C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_AUTOLOAD_SCT3_SIZE</name>
+              <description>Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_CNT_INT_ENA</name>
+          <description>Cache Access Counter Interrupt enable register</description>
+          <addressOffset>0x2C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS0_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS1_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS2_OVF_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS3_OVF_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS0_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS1_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS2_OVF_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS3_OVF_INT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_CNT_INT_CLR</name>
+          <description>Cache Access Counter Interrupt clear register</description>
+          <addressOffset>0x2C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS0_OVF_INT_CLR</name>
+              <description>The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS1_OVF_INT_CLR</name>
+              <description>The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS2_OVF_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS3_OVF_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS0_OVF_INT_CLR</name>
+              <description>The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS1_OVF_INT_CLR</name>
+              <description>The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS2_OVF_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS3_OVF_INT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_CNT_INT_RAW</name>
+          <description>Cache Access Counter Interrupt raw register</description>
+          <addressOffset>0x2CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS0_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS1_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS2_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS3_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS0_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS1_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS2_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS3_OVF_INT_RAW</name>
+              <description>The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_CNT_INT_ST</name>
+          <description>Cache Access Counter Interrupt status register</description>
+          <addressOffset>0x2D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS0_OVF_INT_ST</name>
+              <description>The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS1_OVF_INT_ST</name>
+              <description>The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS2_OVF_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS3_OVF_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS0_OVF_INT_ST</name>
+              <description>The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS1_OVF_INT_ST</name>
+              <description>The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS2_OVF_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS3_OVF_INT_ST</name>
+              <description>Reserved</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_FAIL_INT_ENA</name>
+          <description>Cache Access Fail Interrupt enable register</description>
+          <addressOffset>0x2D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_FAIL_INT_ENA</name>
+              <description>The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_FAIL_INT_CLR</name>
+          <description>L1-Cache Access Fail Interrupt clear register</description>
+          <addressOffset>0x2D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_FAIL_INT_CLR</name>
+              <description>The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_FAIL_INT_RAW</name>
+          <description>Cache Access Fail Interrupt raw register</description>
+          <addressOffset>0x2DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_FAIL_INT_RAW</name>
+              <description>The raw bit of the interrupt of access fail that occurs in L2-Cache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_FAIL_INT_ST</name>
+          <description>Cache Access Fail Interrupt status register</description>
+          <addressOffset>0x2E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_FAIL_INT_ST</name>
+              <description>The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_CNT_CTRL</name>
+          <description>Cache Access Counter enable and clear register</description>
+          <addressOffset>0x2E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS0_CNT_ENA</name>
+              <description>The bit is used to enable ibus0 counter in L2-Cache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS1_CNT_ENA</name>
+              <description>The bit is used to enable ibus1 counter in L2-Cache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS2_CNT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS3_CNT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS0_CNT_ENA</name>
+              <description>The bit is used to enable dbus0 counter in L2-Cache.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS1_CNT_ENA</name>
+              <description>The bit is used to enable dbus1 counter in L2-Cache.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS2_CNT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS3_CNT_ENA</name>
+              <description>Reserved</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS0_CNT_CLR</name>
+              <description>The bit is used to clear ibus0 counter in L2-Cache.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS1_CNT_CLR</name>
+              <description>The bit is used to clear ibus1 counter in L2-Cache.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS2_CNT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_IBUS3_CNT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS0_CNT_CLR</name>
+              <description>The bit is used to clear dbus0 counter in L2-Cache.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS1_CNT_CLR</name>
+              <description>The bit is used to clear dbus1 counter in L2-Cache.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS2_CNT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_DBUS3_CNT_CLR</name>
+              <description>Reserved</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS0_ACS_HIT_CNT</name>
+          <description>L2-Cache bus0 Hit-Access Counter register</description>
+          <addressOffset>0x2E8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS0_HIT_CNT</name>
+              <description>The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS0_ACS_MISS_CNT</name>
+          <description>L2-Cache bus0 Miss-Access Counter register</description>
+          <addressOffset>0x2EC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS0_MISS_CNT</name>
+              <description>The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS0_ACS_CONFLICT_CNT</name>
+          <description>L2-Cache bus0 Conflict-Access Counter register</description>
+          <addressOffset>0x2F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS0_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS0_ACS_NXTLVL_CNT</name>
+          <description>L2-Cache bus0 Next-Level-Access Counter register</description>
+          <addressOffset>0x2F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS0_NXTLVL_CNT</name>
+              <description>The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS1_ACS_HIT_CNT</name>
+          <description>L2-Cache bus1 Hit-Access Counter register</description>
+          <addressOffset>0x2F8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS1_HIT_CNT</name>
+              <description>The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS1_ACS_MISS_CNT</name>
+          <description>L2-Cache bus1 Miss-Access Counter register</description>
+          <addressOffset>0x2FC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS1_MISS_CNT</name>
+              <description>The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS1_ACS_CONFLICT_CNT</name>
+          <description>L2-Cache bus1 Conflict-Access Counter register</description>
+          <addressOffset>0x300</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS1_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS1_ACS_NXTLVL_CNT</name>
+          <description>L2-Cache bus1 Next-Level-Access Counter register</description>
+          <addressOffset>0x304</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS1_NXTLVL_CNT</name>
+              <description>The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS2_ACS_HIT_CNT</name>
+          <description>L2-Cache bus2 Hit-Access Counter register</description>
+          <addressOffset>0x308</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS2_HIT_CNT</name>
+              <description>The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS2_ACS_MISS_CNT</name>
+          <description>L2-Cache bus2 Miss-Access Counter register</description>
+          <addressOffset>0x30C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS2_MISS_CNT</name>
+              <description>The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS2_ACS_CONFLICT_CNT</name>
+          <description>L2-Cache bus2 Conflict-Access Counter register</description>
+          <addressOffset>0x310</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS2_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS2_ACS_NXTLVL_CNT</name>
+          <description>L2-Cache bus2 Next-Level-Access Counter register</description>
+          <addressOffset>0x314</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS2_NXTLVL_CNT</name>
+              <description>The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS3_ACS_HIT_CNT</name>
+          <description>L2-Cache bus3 Hit-Access Counter register</description>
+          <addressOffset>0x318</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS3_HIT_CNT</name>
+              <description>The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS3_ACS_MISS_CNT</name>
+          <description>L2-Cache bus3 Miss-Access Counter register</description>
+          <addressOffset>0x31C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS3_MISS_CNT</name>
+              <description>The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS3_ACS_CONFLICT_CNT</name>
+          <description>L2-Cache bus3 Conflict-Access Counter register</description>
+          <addressOffset>0x320</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS3_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_IBUS3_ACS_NXTLVL_CNT</name>
+          <description>L2-Cache bus3 Next-Level-Access Counter register</description>
+          <addressOffset>0x324</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_IBUS3_NXTLVL_CNT</name>
+              <description>The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS0_ACS_HIT_CNT</name>
+          <description>L2-Cache bus0 Hit-Access Counter register</description>
+          <addressOffset>0x328</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS0_HIT_CNT</name>
+              <description>The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS0_ACS_MISS_CNT</name>
+          <description>L2-Cache bus0 Miss-Access Counter register</description>
+          <addressOffset>0x32C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS0_MISS_CNT</name>
+              <description>The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS0_ACS_CONFLICT_CNT</name>
+          <description>L2-Cache bus0 Conflict-Access Counter register</description>
+          <addressOffset>0x330</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS0_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS0_ACS_NXTLVL_CNT</name>
+          <description>L2-Cache bus0 Next-Level-Access Counter register</description>
+          <addressOffset>0x334</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS0_NXTLVL_CNT</name>
+              <description>The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS1_ACS_HIT_CNT</name>
+          <description>L2-Cache bus1 Hit-Access Counter register</description>
+          <addressOffset>0x338</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS1_HIT_CNT</name>
+              <description>The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS1_ACS_MISS_CNT</name>
+          <description>L2-Cache bus1 Miss-Access Counter register</description>
+          <addressOffset>0x33C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS1_MISS_CNT</name>
+              <description>The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS1_ACS_CONFLICT_CNT</name>
+          <description>L2-Cache bus1 Conflict-Access Counter register</description>
+          <addressOffset>0x340</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS1_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS1_ACS_NXTLVL_CNT</name>
+          <description>L2-Cache bus1 Next-Level-Access Counter register</description>
+          <addressOffset>0x344</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS1_NXTLVL_CNT</name>
+              <description>The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS2_ACS_HIT_CNT</name>
+          <description>L2-Cache bus2 Hit-Access Counter register</description>
+          <addressOffset>0x348</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS2_HIT_CNT</name>
+              <description>The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS2_ACS_MISS_CNT</name>
+          <description>L2-Cache bus2 Miss-Access Counter register</description>
+          <addressOffset>0x34C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS2_MISS_CNT</name>
+              <description>The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS2_ACS_CONFLICT_CNT</name>
+          <description>L2-Cache bus2 Conflict-Access Counter register</description>
+          <addressOffset>0x350</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS2_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS2_ACS_NXTLVL_CNT</name>
+          <description>L2-Cache bus2 Next-Level-Access Counter register</description>
+          <addressOffset>0x354</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS2_NXTLVL_CNT</name>
+              <description>The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS3_ACS_HIT_CNT</name>
+          <description>L2-Cache bus3 Hit-Access Counter register</description>
+          <addressOffset>0x358</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS3_HIT_CNT</name>
+              <description>The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS3_ACS_MISS_CNT</name>
+          <description>L2-Cache bus3 Miss-Access Counter register</description>
+          <addressOffset>0x35C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS3_MISS_CNT</name>
+              <description>The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS3_ACS_CONFLICT_CNT</name>
+          <description>L2-Cache bus3 Conflict-Access Counter register</description>
+          <addressOffset>0x360</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS3_CONFLICT_CNT</name>
+              <description>The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_DBUS3_ACS_NXTLVL_CNT</name>
+          <description>L2-Cache bus3 Next-Level-Access Counter register</description>
+          <addressOffset>0x364</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_DBUS3_NXTLVL_CNT</name>
+              <description>The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_FAIL_ID_ATTR</name>
+          <description>L2-Cache Access Fail ID/attribution information register</description>
+          <addressOffset>0x368</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_FAIL_ID</name>
+              <description>The register records the ID of fail-access when L1-Cache accesses L2-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_FAIL_ATTR</name>
+              <description>The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACS_FAIL_ADDR</name>
+          <description>L2-Cache Access Fail Address information register</description>
+          <addressOffset>0x36C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_FAIL_ADDR</name>
+              <description>The register records the address of fail-access when L1-Cache accesses L2-Cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_SYNC_PRELOAD_INT_ENA</name>
+          <description>L1-Cache Access Fail Interrupt enable register</description>
+          <addressOffset>0x370</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PLD_DONE_INT_ENA</name>
+              <description>The bit is used to enable interrupt of L2-Cache preload-operation done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PLD_ERR_INT_ENA</name>
+              <description>The bit is used to enable interrupt of L2-Cache preload-operation error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_SYNC_PRELOAD_INT_CLR</name>
+          <description>Sync Preload operation Interrupt clear register</description>
+          <addressOffset>0x374</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PLD_DONE_INT_CLR</name>
+              <description>The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PLD_ERR_INT_CLR</name>
+              <description>The bit is used to clear interrupt of L2-Cache preload-operation error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_SYNC_PRELOAD_INT_RAW</name>
+          <description>Sync Preload operation Interrupt raw register</description>
+          <addressOffset>0x378</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PLD_DONE_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PLD_ERR_INT_RAW</name>
+              <description>The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_SYNC_PRELOAD_INT_ST</name>
+          <description>L1-Cache Access Fail Interrupt status register</description>
+          <addressOffset>0x37C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PLD_DONE_INT_ST</name>
+              <description>The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_PLD_ERR_INT_ST</name>
+              <description>The bit indicates the status of the interrupt of L2-Cache preload-operation error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_SYNC_PRELOAD_EXCEPTION</name>
+          <description>Cache Sync/Preload Operation exception register</description>
+          <addressOffset>0x380</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PLD_ERR_CODE</name>
+              <description>The value 2 is Only available which means preload size is error in L2-Cache.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_SYNC_RST_CTRL</name>
+          <description>Cache Sync Reset control register</description>
+          <addressOffset>0x384</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_SYNC_RST</name>
+              <description>set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_PRELOAD_RST_CTRL</name>
+          <description>Cache Preload Reset control register</description>
+          <addressOffset>0x388</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_PLD_RST</name>
+              <description>set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_AUTOLOAD_BUF_CLR_CTRL</name>
+          <description>Cache Autoload buffer clear control register</description>
+          <addressOffset>0x38C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_ALD_BUF_CLR</name>
+              <description>set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_UNALLOCATE_BUFFER_CLEAR</name>
+          <description>Unallocate request buffer clear registers</description>
+          <addressOffset>0x390</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_UNALLOC_CLR</name>
+              <description>The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_ACCESS_ATTR_CTRL</name>
+          <description>L1 Cache access Attribute propagation control register</description>
+          <addressOffset>0x394</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>L2_CACHE_ACCESS_FORCE_CC</name>
+              <description>Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_ACCESS_FORCE_WB</name>
+              <description>Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_ACCESS_FORCE_WMA</name>
+              <description>Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_ACCESS_FORCE_RMA</name>
+              <description>Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_OBJECT_CTRL</name>
+          <description>Cache Tag and Data memory Object control register</description>
+          <addressOffset>0x398</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_TAG_OBJECT</name>
+              <description>Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L2_CACHE_MEM_OBJECT</name>
+              <description>Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_WAY_OBJECT</name>
+          <description>Cache Tag and Data memory way register</description>
+          <addressOffset>0x39C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>L2_CACHE_WAY_OBJECT</name>
+              <description>Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_VADDR</name>
+          <description>Cache Vaddr register</description>
+          <addressOffset>0x3A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>L2_CACHE_VADDR</name>
+              <description>Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>L2_CACHE_DEBUG_BUS</name>
+          <description>Cache Tag/data memory content register</description>
+          <addressOffset>0x3A4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000003A4</resetValue>
+          <fields>
+            <field>
+              <name>L2_CACHE_DEBUG_BUS</name>
+              <description>This is a constant place where we can write data to or read data from the tag/data memory on the specified cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LEVEL_SPLIT1</name>
+          <description>USED TO SPLIT L1 CACHE AND L2 CACHE</description>
+          <addressOffset>0x3A8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000003A8</resetValue>
+          <fields>
+            <field>
+              <name>LEVEL_SPLIT1</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>Clock gate control register</description>
+          <addressOffset>0x3AC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>The bit is used to enable clock gate when access all registers in this module.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDUNDANCY_SIG0</name>
+          <description>Cache redundancy signal 0 register</description>
+          <addressOffset>0x3B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_REDCY_SIG0</name>
+              <description>Those bits are prepared for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDUNDANCY_SIG1</name>
+          <description>Cache redundancy signal 1 register</description>
+          <addressOffset>0x3B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_REDCY_SIG1</name>
+              <description>Those bits are prepared for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDUNDANCY_SIG2</name>
+          <description>Cache redundancy signal 2 register</description>
+          <addressOffset>0x3B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_REDCY_SIG2</name>
+              <description>Those bits are prepared for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDUNDANCY_SIG3</name>
+          <description>Cache redundancy signal 3 register</description>
+          <addressOffset>0x3BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_REDCY_SIG3</name>
+              <description>Those bits are prepared for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDUNDANCY_SIG4</name>
+          <description>Cache redundancy signal 0 register</description>
+          <addressOffset>0x3C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_REDCY_SIG4</name>
+              <description>Those bits are prepared for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02202080</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version control register. Note that this default value stored is the latest date when the hardware logic was updated.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <baseAddress>0x60091000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x314</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>GPIO_PRO</name>
+        <value>30</value>
+      </interrupt>
+      <interrupt>
+        <name>GPIO_PRO_NMI</name>
+        <value>31</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BT_SELECT</name>
+          <description>GPIO bit select register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_SEL</name>
+              <description>GPIO bit select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT</name>
+          <description>GPIO output register for GPIO0-31</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_ORIG</name>
+              <description>GPIO output register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TS</name>
+          <description>GPIO output set register for GPIO0-31</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TS</name>
+              <description>GPIO output set register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TC</name>
+          <description>GPIO output clear register for GPIO0-31</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TC</name>
+              <description>GPIO output clear register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1</name>
+          <description>GPIO output register for GPIO32-34</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_ORIG</name>
+              <description>GPIO output register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1_W1TS</name>
+          <description>GPIO output set register for GPIO32-34</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT1_W1TS</name>
+              <description>GPIO output set register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1_W1TC</name>
+          <description>GPIO output clear register for GPIO32-34</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT1_W1TC</name>
+              <description>GPIO output clear register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SELECT</name>
+          <description>GPIO sdio select register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_SEL</name>
+              <description>GPIO sdio select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE</name>
+          <description>GPIO output enable register for GPIO0-31</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO output enable register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TS</name>
+          <description>GPIO output enable set register for GPIO0-31</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TS</name>
+              <description>GPIO output enable set register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <description>GPIO output enable clear register for GPIO0-31</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TC</name>
+              <description>GPIO output enable clear register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1</name>
+          <description>GPIO output enable register for GPIO32-34</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO output enable register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1_W1TS</name>
+          <description>GPIO output enable set register for GPIO32-34</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE1_W1TS</name>
+              <description>GPIO output enable set register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1_W1TC</name>
+          <description>GPIO output enable clear register for GPIO32-34</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE1_W1TC</name>
+              <description>GPIO output enable clear register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STRAP</name>
+          <description>pad strapping register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRAPPING</name>
+              <description>pad strapping register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <description>GPIO input register for GPIO0-31</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO input register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN1</name>
+          <description>GPIO input register for GPIO32-34</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO input register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>GPIO interrupt status register for GPIO0-31</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>GPIO interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TS</name>
+          <description>GPIO interrupt status set register for GPIO0-31</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TS</name>
+              <description>GPIO interrupt status set register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TC</name>
+          <description>GPIO interrupt status clear register for GPIO0-31</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TC</name>
+              <description>GPIO interrupt status clear register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1</name>
+          <description>GPIO interrupt status register for GPIO32-34</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>GPIO interrupt status register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1_W1TS</name>
+          <description>GPIO interrupt status set register for GPIO32-34</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS1_W1TS</name>
+              <description>GPIO interrupt status set register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1_W1TC</name>
+          <description>GPIO interrupt status clear register for GPIO32-34</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS1_W1TC</name>
+              <description>GPIO interrupt status clear register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT</name>
+          <description>GPIO PRO_CPU interrupt status register for GPIO0-31</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT</name>
+              <description>GPIO PRO_CPU interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT</name>
+          <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT</name>
+              <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT</name>
+          <description>GPIO CPUSDIO interrupt status register for GPIO0-31</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT</name>
+              <description>GPIO CPUSDIO interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT1</name>
+          <description>GPIO PRO_CPU interrupt status register for GPIO32-34</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT1</name>
+              <description>GPIO PRO_CPU interrupt status register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT1</name>
+          <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT1</name>
+              <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT1</name>
+          <description>GPIO CPUSDIO interrupt status register for GPIO32-34</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT1</name>
+              <description>GPIO CPUSDIO interrupt status register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>35</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>PIN%s</name>
+          <description>GPIO pin configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYNC2_BYPASS</name>
+              <description>set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>set this bit to select pad driver. 1:open-drain. 0:normal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC1_BYPASS</name>
+              <description>set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TYPE</name>
+              <description>set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENABLE</name>
+              <description>set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONFIG</name>
+              <description>reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_ENA</name>
+              <description>set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_NEXT</name>
+          <description>GPIO interrupt source register for GPIO0-31</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INTERRUPT_NEXT</name>
+              <description>GPIO interrupt source register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_NEXT1</name>
+          <description>GPIO interrupt source register for GPIO32-34</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INTERRUPT_NEXT1</name>
+              <description>GPIO interrupt source register for GPIO32-34</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC0_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC0_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC0_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG0_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC6_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC6_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC6_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG6_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC7_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC7_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC7_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG7_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC8_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC8_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC8_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG8_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC9_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>FUNC9_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC9_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG9_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC10_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC10_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC10_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG10_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC11_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC11_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC11_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG11_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC12_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC12_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC12_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG12_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC13_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC13_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC13_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG13_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC14_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC14_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC14_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG14_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC15_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC15_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC15_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG15_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC16_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC16_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC16_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG16_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC17_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC17_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC17_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG17_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC19_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC19_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC19_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG19_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC28_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC28_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC28_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG28_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC29_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC29_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC29_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG29_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC30_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC30_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC30_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG30_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC31_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC31_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC31_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG31_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC32_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC32_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC32_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG32_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC33_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC33_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC33_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG33_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC34_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC34_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC34_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG34_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC35_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC35_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC35_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG35_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC40_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC40_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC40_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG40_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC41_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC41_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC41_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG41_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC42_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC42_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC42_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG42_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC45_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x208</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>FUNC45_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC45_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG45_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC46_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x20C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>FUNC46_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC46_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG46_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC47_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x210</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC47_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC47_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG47_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC48_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x214</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC48_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC48_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG48_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC49_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x218</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC49_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC49_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG49_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC50_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x21C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC50_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC50_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG50_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC51_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x220</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC51_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC51_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG51_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC52_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x224</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC52_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC52_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG52_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC53_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x228</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC53_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC53_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG53_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC54_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x22C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC54_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC54_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG54_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC55_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x230</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC55_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC55_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG55_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC56_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x234</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC56_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC56_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG56_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC57_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x238</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC57_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC57_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG57_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC58_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x23C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC58_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC58_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG58_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC59_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x240</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC59_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC59_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG59_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC60_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x244</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC60_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC60_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG60_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC61_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x248</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC61_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC61_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG61_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC62_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x24C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC62_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC62_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG62_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC63_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x250</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC63_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC63_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG63_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC64_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x254</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC64_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC64_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG64_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC65_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x258</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC65_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC65_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG65_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC66_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x25C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC66_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC66_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG66_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC67_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x260</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC67_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC67_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG67_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC68_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x264</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC68_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC68_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG68_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC69_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x268</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC69_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC69_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG69_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC70_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x26C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC70_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC70_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG70_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC71_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x270</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC71_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC71_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG71_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC72_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x274</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC72_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC72_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG72_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC73_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x278</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>FUNC73_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC73_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG73_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC77_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x288</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>FUNC77_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC77_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG77_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC81_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x298</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC81_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC81_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG81_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC82_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x29C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC82_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC82_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG82_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC87_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2B0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC87_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC87_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG87_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC88_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2B4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC88_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC88_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG88_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC89_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2B8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC89_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC89_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG89_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC90_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2BC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC90_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC90_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG90_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC91_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2C0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC91_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC91_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG91_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC92_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC92_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC92_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG92_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC93_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC93_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC93_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG93_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC94_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC94_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC94_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG94_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC95_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2D0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC95_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC95_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG95_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC97_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2D8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC97_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC97_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG97_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC98_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC98_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC98_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG98_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC99_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2E0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC99_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC99_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG99_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC100_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2E4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC100_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC100_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG100_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC101_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC101_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC101_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG101_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC102_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC102_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC102_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG102_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC103_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC103_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC103_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG103_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC104_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC104_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC104_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG104_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC105_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC105_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC105_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG105_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC106_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC106_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC106_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG106_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC107_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x300</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC107_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC107_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG107_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC108_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x304</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC108_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC108_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG108_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC109_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x308</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC109_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC109_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG109_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC110_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x30C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC110_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC110_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG110_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC111_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x310</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC111_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC111_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG111_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC112_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x314</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC112_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC112_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG112_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC113_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x318</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC113_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC113_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG113_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC114_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x31C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC114_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC114_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG114_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC115_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x320</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC115_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC115_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG115_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC116_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x324</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC116_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC116_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG116_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC117_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x328</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC117_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC117_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG117_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC118_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x32C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC118_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC118_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG118_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC119_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x330</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC119_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC119_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG119_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC120_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x334</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC120_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC120_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG120_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC121_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x338</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC121_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC121_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG121_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC122_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x33C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC122_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC122_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG122_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC123_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x340</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC123_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC123_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG123_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC124_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x344</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>FUNC124_IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC124_IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG124_IN_SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>35</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>FUNC%s_OUT_SEL_CFG</name>
+          <description>GPIO output function select register</description>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>FUNC_OUT_SEL</name>
+              <description>The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC_OUT_INV_SEL</name>
+              <description>set this bit to invert output signal.1:invert.0:not invert.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC_OEN_SEL</name>
+              <description>set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC_OEN_INV_SEL</name>
+              <description>set this bit to invert output enable signal.1:invert.0:not invert.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>GPIO clock gate register</description>
+          <addressOffset>0x62C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>set this bit to enable GPIO clock gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>GPIO version register</description>
+          <addressOffset>0x6FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201120</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIOSD</name>
+      <description>Sigma-Delta Modulation</description>
+      <groupName>GPIOSD</groupName>
+      <baseAddress>0x60004F00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x7C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SIGMADELTA%s</name>
+          <description>Duty Cycle Configure Register of SDM%s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD0_IN</name>
+              <description>This field is used to configure the duty cycle of sigma delta modulation output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD0_PRESCALE</name>
+              <description>This field is used to set a divider value to divide APB clock.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>Clock Gating Configure Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Clock enable bit of configuration registers for sigma delta modulation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_MISC</name>
+          <description>MISC Register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FUNCTION_CLK_EN</name>
+              <description>Clock enable bit of sigma delta modulation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SWAP</name>
+              <description>Reserved.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>GLITCH_FILTER_CH%s</name>
+          <description>Glitch Filter Configure Register of Channel%s</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FILTER_CH0_EN</name>
+              <description>Glitch Filter channel enable bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_CH0_INPUT_IO_NUM</name>
+              <description>Glitch Filter input io number.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_CH0_WINDOW_THRES</name>
+              <description>Glitch Filter window threshold.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_CH0_WINDOW_WIDTH</name>
+              <description>Glitch Filter window width.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>ETM_EVENT_CH%s_CFG</name>
+          <description>Etm Config register of Channel%s</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_CH0_EVENT_SEL</name>
+              <description>Etm event channel select gpio.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_CH0_EVENT_EN</name>
+              <description>Etm event send enable bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_TASK_P0_CFG</name>
+          <description>Etm Configure Register to decide which GPIO been chosen</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_TASK_GPIO0_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO0_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO1_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO1_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO2_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO2_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO3_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO3_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_TASK_P1_CFG</name>
+          <description>Etm Configure Register to decide which GPIO been chosen</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_TASK_GPIO4_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO4_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO5_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO5_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO6_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO6_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO7_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO7_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_TASK_P2_CFG</name>
+          <description>Etm Configure Register to decide which GPIO been chosen</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_TASK_GPIO8_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO8_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO9_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO9_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO10_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO10_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO11_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO11_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_TASK_P3_CFG</name>
+          <description>Etm Configure Register to decide which GPIO been chosen</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_TASK_GPIO12_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO12_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO13_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO13_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO14_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO14_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO15_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO15_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_TASK_P4_CFG</name>
+          <description>Etm Configure Register to decide which GPIO been chosen</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_TASK_GPIO16_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO16_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO17_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO17_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO18_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO18_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO19_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO19_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_TASK_P5_CFG</name>
+          <description>Etm Configure Register to decide which GPIO been chosen</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_TASK_GPIO20_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO20_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO21_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO21_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO22_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO22_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO23_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO23_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_TASK_P6_CFG</name>
+          <description>Etm Configure Register to decide which GPIO been chosen</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_TASK_GPIO24_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO24_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO25_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO25_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO26_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO26_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO27_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO27_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_TASK_P7_CFG</name>
+          <description>Etm Configure Register to decide which GPIO been chosen</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_TASK_GPIO28_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO28_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO29_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO29_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO30_EN</name>
+              <description>Enable bit of GPIO response etm task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_TASK_GPIO30_SEL</name>
+              <description>GPIO choose a etm task channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VERSION</name>
+          <description>Version Control Register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02203050</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_SD_DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HINF</name>
+      <description>Peripheral HINF</description>
+      <groupName>HINF</groupName>
+      <baseAddress>0x60016000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x54</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CFG_DATA0</name>
+          <description>Configure sdio cis content</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00926666</resetValue>
+          <fields>
+            <field>
+              <name>DEVICE_ID_FN1</name>
+              <description>configure device id of function1 in cis</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USER_ID_FN1</name>
+              <description>configure user id of function1 in cis</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG_DATA1</name>
+          <description>SDIO configuration register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00232011</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_ENABLE</name>
+              <description>Sdio clock enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IOREADY1</name>
+              <description>sdio function1 io ready signal in cis</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HIGHSPEED_ENABLE</name>
+              <description>Highspeed enable in cccr</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HIGHSPEED_MODE</name>
+              <description>highspeed mode status in cccr</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_CD_ENABLE</name>
+              <description>sdio card detect enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IOREADY2</name>
+              <description>sdio function1 io ready signal in cis</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_INT_MASK</name>
+              <description>mask sdio interrupt in cccr, high active</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IOENABLE2</name>
+              <description>ioe2 status in cccr</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CD_DISABLE</name>
+              <description>card disable status in cccr</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FUNC1_EPS</name>
+              <description>function1 eps status in fbr</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EMP</name>
+              <description>empc status in cccr</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IOENABLE1</name>
+              <description>ioe1 status in cccr</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_VER</name>
+              <description>sdio version in cccr</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUNC2_EPS</name>
+              <description>function2 eps status in fbr</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO20_CONF</name>
+              <description>[29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat in delayed cycles control,0:no delay, 1:delay 1 cycle.
+[25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed mode.
+[26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when [12]=0,posedge when highspeed mode enable.
+[27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.
+[28]: sdio data pad pull up enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG_TIMING</name>
+          <description>Timing configuration registers</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x15780812</resetValue>
+          <fields>
+            <field>
+              <name>NCRC</name>
+              <description>configure Ncrc parameter in sdr50/104 mode, no more than 6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PST_END_CMD_LOW_VALUE</name>
+              <description>configure cycles to lower cmd after voltage is changed to 1.8V.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PST_END_DATA_LOW_VALUE</name>
+              <description>configure cycles to lower data after voltage is changed to 1.8V.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDCLK_STOP_THRES</name>
+              <description>Configure the number of cycles of module clk to judge sdclk has stopped</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAMPLE_CLK_DIVIDER</name>
+              <description>module clk divider to sample sdclk</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG_UPDATE</name>
+          <description>update sdio configurations</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONF_UPDATE</name>
+              <description>update the timing configurations</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG_DATA7</name>
+          <description>SDIO configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x23820000</resetValue>
+          <fields>
+            <field>
+              <name>PIN_STATE</name>
+              <description>configure cis addr 318 and 574</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHIP_STATE</name>
+              <description>configure cis addr 312, 315, 568 and 571</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_RST</name>
+              <description>soft reset control for sdio module</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IOREADY0</name>
+              <description>sdio io ready, high enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_MEM_PD</name>
+              <description>sdio memory power down, high active</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESDIO_DATA1_INT_EN</name>
+              <description>enable sdio interrupt on data1 line</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_SWITCH_VOLT_SW</name>
+              <description>control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DDR50_BLK_LEN_FIX_EN</name>
+              <description>enable block length to be fixed to 512 bytes in ddr50 mode</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>sdio apb clock for configuration force on control:0-gating,1-force on.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDDR50</name>
+              <description>configure if support sdr50 mode in cccr</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SSDR104</name>
+              <description>configure if support sdr104 mode in cccr</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SSDR50</name>
+              <description>configure if support ddr50 mode in cccr</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDTD</name>
+              <description>configure if support driver type D in cccr</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDTA</name>
+              <description>configure if support driver type A in cccr</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDTC</name>
+              <description>configure if support driver type C in cccr</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAI</name>
+              <description>configure if support asynchronous interrupt in cccr</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_WAKEUP_CLR</name>
+              <description>clear sdio_wake_up signal after the chip wakes up</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF_W0</name>
+          <description>SDIO cis configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W0</name>
+              <description>Configure cis addr 39~36</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF_W1</name>
+          <description>SDIO cis configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W1</name>
+              <description>Configure cis addr 43~40</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF_W2</name>
+          <description>SDIO cis configuration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W2</name>
+              <description>Configure cis addr 47~44</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF_W3</name>
+          <description>SDIO cis configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W3</name>
+              <description>Configure cis addr 51~48</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF_W4</name>
+          <description>SDIO cis configuration register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W4</name>
+              <description>Configure cis addr 55~52</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF_W5</name>
+          <description>SDIO cis configuration register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W5</name>
+              <description>Configure cis addr 59~56</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF_W6</name>
+          <description>SDIO cis configuration register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W6</name>
+              <description>Configure cis addr 63~60</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CIS_CONF_W7</name>
+          <description>SDIO cis configuration register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CIS_CONF_W7</name>
+              <description>Configure cis addr 67~64</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG_DATA16</name>
+          <description>SDIO cis configuration register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00927777</resetValue>
+          <fields>
+            <field>
+              <name>DEVICE_ID_FN2</name>
+              <description>configure device id of function2 in cis</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USER_ID_FN2</name>
+              <description>configure user id of function2 in cis</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CFG_UHS1_INT_MODE</name>
+          <description>configure int to start and end ahead of time in uhs1 mode</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTOE_END_AHEAD_MODE</name>
+              <description>intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_END_AHEAD_MODE</name>
+              <description>int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTOE_ST_AHEAD_MODE</name>
+              <description>intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_ST_AHEAD_MODE</name>
+              <description>int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_STATUS</name>
+          <description>func0 config0 status</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FUNC0_CONFIG0</name>
+              <description>func0 config0 (addr: 0x20f0 ) status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDR25_ST</name>
+              <description>sdr25 status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDR50_ST</name>
+              <description>sdr50 status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDR104_ST</name>
+              <description>sdr104 status</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DDR50_ST</name>
+              <description>ddr50 status</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TUNE_ST</name>
+              <description>tune_st fsm status</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_SWITCH_VOLT_ST</name>
+              <description>sdio switch voltage status:0-3.3V, 1-1.8V.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_SWITCH_END</name>
+              <description>sdio switch voltage ldo ready</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SLAVE_ECO_LOW</name>
+          <description>sdio_slave redundant control registers</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RDN_ECO_LOW</name>
+              <description>redundant registers for sdio_slave</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SLAVE_ECO_HIGH</name>
+          <description>sdio_slave redundant control registers</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>RDN_ECO_HIGH</name>
+              <description>redundant registers for sdio_slave</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SLAVE_ECO_CONF</name>
+          <description>sdio_slave redundant control registers</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_SLAVE_RDN_RESULT</name>
+              <description>redundant registers for sdio_slave</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_SLAVE_RDN_ENA</name>
+              <description>redundant registers for sdio_slave</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_SLAVE_SDIO_CLK_RDN_RESULT</name>
+              <description>redundant registers for sdio_slave</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_SLAVE_SDIO_CLK_RDN_ENA</name>
+              <description>redundant registers for sdio_slave</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_SLAVE_SDCLK_PAD_RDN_RESULT</name>
+              <description>redundant registers for sdio_slave</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_SLAVE_SDCLK_PAD_RDN_ENA</name>
+              <description>redundant registers for sdio_slave</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SLAVE_LDO_CONF</name>
+          <description>sdio slave ldo control register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000014</resetValue>
+          <fields>
+            <field>
+              <name>LDO_READY_CTL_IN_EN</name>
+              <description>control ldo ready signal by sdio slave itself</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LDO_READY_THRES</name>
+              <description>configure ldo ready counting threshold value, the actual counting target is 2^(ldo_ready_thres)-1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LDO_READY_IGNORE_EN</name>
+              <description>ignore ldo ready signal</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_DATE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02203150</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_DATE</name>
+              <description>sdio version date.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMAC</name>
+      <description>HMAC (Hash-based Message Authentication Code) Accelerator</description>
+      <groupName>HMAC</groupName>
+      <baseAddress>0x6008D000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SET_START</name>
+          <description>Process control register 0.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>Start hmac operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_PURPOSE</name>
+          <description>Configure purpose.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PURPOSE_SET</name>
+              <description>Set hmac parameter purpose.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_KEY</name>
+          <description>Configure key.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_SET</name>
+              <description>Set hmac parameter key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_FINISH</name>
+          <description>Finish initial configuration.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_PARA_END</name>
+              <description>Finish hmac configuration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ONE</name>
+          <description>Process control register 1.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ONE</name>
+              <description>Call SHA to calculate one message block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ING</name>
+          <description>Process control register 2.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ING</name>
+              <description>Continue typical hmac.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_END</name>
+          <description>Process control register 3.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_END</name>
+              <description>Start hardware padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_RESULT_FINISH</name>
+          <description>Process control register 4.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_RESULT_END</name>
+              <description>After read result from upstream, then let hmac back to idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_JTAG</name>
+          <description>Invalidate register 0.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_JTAG</name>
+              <description>Clear result from hmac downstream JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_DS</name>
+          <description>Invalidate register 1.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_DS</name>
+              <description>Clear result from hmac downstream DS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_ERROR</name>
+          <description>Error register.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUREY_CHECK</name>
+              <description>Hmac configuration state. 0: key are agree with purpose. 1: error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>Busy register.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUSY_STATE</name>
+              <description>Hmac state. 1'b0: idle. 1'b1: busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>WR_MESSAGE_MEM[%s]</name>
+          <description>Message block memory.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>RD_RESULT_MEM[%s]</name>
+          <description>Result from upstream.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>SET_MESSAGE_PAD</name>
+          <description>Process control register 5.</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_PAD</name>
+              <description>Start software padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ONE_BLOCK</name>
+          <description>Process control register 6.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_ONE_BLOCK</name>
+              <description>Don't have to do padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SOFT_JTAG_CTRL</name>
+          <description>Jtag register 0.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SOFT_JTAG_CTRL</name>
+              <description>Turn on JTAG verification.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_JTAG</name>
+          <description>Jtag register 1.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_JTAG</name>
+              <description>32-bit of key to be compared.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200618</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Hmac date information/ hmac version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HP_APM</name>
+      <description>Peripheral HP_APM</description>
+      <groupName>HP_APM</groupName>
+      <baseAddress>0x60099000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x114</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>REGION_FILTER_EN</name>
+          <description>Region filter enable register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>REGION_FILTER_EN</name>
+              <description>Region filter enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION0_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION0_ADDR_START</name>
+              <description>Start address of region0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION0_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION0_ADDR_END</name>
+              <description>End address of region0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION0_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION0_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION1_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION1_ADDR_START</name>
+              <description>Start address of region1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION1_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION1_ADDR_END</name>
+              <description>End address of region1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION1_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION1_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION2_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION2_ADDR_START</name>
+              <description>Start address of region2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION2_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION2_ADDR_END</name>
+              <description>End address of region2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION2_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION2_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION3_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION3_ADDR_START</name>
+              <description>Start address of region3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION3_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION3_ADDR_END</name>
+              <description>End address of region3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION3_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION3_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION4_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION4_ADDR_START</name>
+              <description>Start address of region4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION4_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION4_ADDR_END</name>
+              <description>End address of region4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION4_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION4_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION4_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION4_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION4_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION4_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION4_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION4_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION4_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION4_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION5_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION5_ADDR_START</name>
+              <description>Start address of region5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION5_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION5_ADDR_END</name>
+              <description>End address of region5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION5_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION5_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION5_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION5_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION5_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION5_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION5_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION5_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION5_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION5_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION6_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION6_ADDR_START</name>
+              <description>Start address of region6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION6_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION6_ADDR_END</name>
+              <description>End address of region6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION6_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION6_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION6_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION6_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION6_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION6_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION6_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION6_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION6_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION6_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION7_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION7_ADDR_START</name>
+              <description>Start address of region7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION7_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION7_ADDR_END</name>
+              <description>End address of region7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION7_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION7_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION7_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION7_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION7_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION7_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION7_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION7_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION7_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION7_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION8_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION8_ADDR_START</name>
+              <description>Start address of region8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION8_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION8_ADDR_END</name>
+              <description>End address of region8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION8_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION8_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION8_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION8_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION8_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION8_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION8_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION8_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION8_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION8_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION9_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION9_ADDR_START</name>
+              <description>Start address of region9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION9_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION9_ADDR_END</name>
+              <description>End address of region9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION9_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION9_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION9_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION9_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION9_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION9_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION9_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION9_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION9_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION9_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION10_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION10_ADDR_START</name>
+              <description>Start address of region10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION10_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION10_ADDR_END</name>
+              <description>End address of region10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION10_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION10_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION10_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION10_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION10_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION10_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION10_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION10_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION10_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION10_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION11_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION11_ADDR_START</name>
+              <description>Start address of region11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION11_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION11_ADDR_END</name>
+              <description>End address of region11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION11_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION11_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION11_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION11_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION11_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION11_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION11_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION11_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION11_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION11_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION12_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION12_ADDR_START</name>
+              <description>Start address of region12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION12_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION12_ADDR_END</name>
+              <description>End address of region12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION12_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION12_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION12_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION12_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION12_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION12_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION12_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION12_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION12_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION12_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION13_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION13_ADDR_START</name>
+              <description>Start address of region13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION13_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION13_ADDR_END</name>
+              <description>End address of region13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION13_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION13_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION13_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION13_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION13_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION13_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION13_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION13_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION13_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION13_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION14_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION14_ADDR_START</name>
+              <description>Start address of region14</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION14_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION14_ADDR_END</name>
+              <description>End address of region14</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION14_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION14_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION14_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION14_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION14_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION14_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION14_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION14_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION14_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION14_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION15_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION15_ADDR_START</name>
+              <description>Start address of region15</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION15_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION15_ADDR_END</name>
+              <description>End address of region15</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION15_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION15_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION15_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION15_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION15_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION15_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION15_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION15_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION15_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION15_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC_CTRL</name>
+          <description>PMS function control register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>M0_PMS_FUNC_EN</name>
+              <description>PMS M0 function enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M1_PMS_FUNC_EN</name>
+              <description>PMS M1 function enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M2_PMS_FUNC_EN</name>
+              <description>PMS M2 function enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M3_PMS_FUNC_EN</name>
+              <description>PMS M3 function enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_STATUS</name>
+          <description>M0 status register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_EXCEPTION_STATUS</name>
+              <description>Exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_STATUS_CLR</name>
+          <description>M0 status clear register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_REGION_STATUS_CLR</name>
+              <description>Clear exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_EXCEPTION_INFO0</name>
+          <description>M0 exception_info0 register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_EXCEPTION_REGION</name>
+              <description>Exception region</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M0_EXCEPTION_MODE</name>
+              <description>Exception mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M0_EXCEPTION_ID</name>
+              <description>Exception id information</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_EXCEPTION_INFO1</name>
+          <description>M0 exception_info1 register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_EXCEPTION_ADDR</name>
+              <description>Exception addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_STATUS</name>
+          <description>M1 status register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M1_EXCEPTION_STATUS</name>
+              <description>Exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_STATUS_CLR</name>
+          <description>M1 status clear register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M1_REGION_STATUS_CLR</name>
+              <description>Clear exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_EXCEPTION_INFO0</name>
+          <description>M1 exception_info0 register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M1_EXCEPTION_REGION</name>
+              <description>Exception region</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M1_EXCEPTION_MODE</name>
+              <description>Exception mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M1_EXCEPTION_ID</name>
+              <description>Exception id information</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_EXCEPTION_INFO1</name>
+          <description>M1 exception_info1 register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M1_EXCEPTION_ADDR</name>
+              <description>Exception addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M2_STATUS</name>
+          <description>M2 status register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M2_EXCEPTION_STATUS</name>
+              <description>Exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M2_STATUS_CLR</name>
+          <description>M2 status clear register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M2_REGION_STATUS_CLR</name>
+              <description>Clear exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M2_EXCEPTION_INFO0</name>
+          <description>M2 exception_info0 register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M2_EXCEPTION_REGION</name>
+              <description>Exception region</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M2_EXCEPTION_MODE</name>
+              <description>Exception mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M2_EXCEPTION_ID</name>
+              <description>Exception id information</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M2_EXCEPTION_INFO1</name>
+          <description>M2 exception_info1 register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M2_EXCEPTION_ADDR</name>
+              <description>Exception addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M3_STATUS</name>
+          <description>M3 status register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M3_EXCEPTION_STATUS</name>
+              <description>Exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M3_STATUS_CLR</name>
+          <description>M3 status clear register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M3_REGION_STATUS_CLR</name>
+              <description>Clear exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M3_EXCEPTION_INFO0</name>
+          <description>M3 exception_info0 register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M3_EXCEPTION_REGION</name>
+              <description>Exception region</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M3_EXCEPTION_MODE</name>
+              <description>Exception mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M3_EXCEPTION_ID</name>
+              <description>Exception id information</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M3_EXCEPTION_INFO1</name>
+          <description>M3 exception_info1 register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M3_EXCEPTION_ADDR</name>
+              <description>Exception addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_EN</name>
+          <description>APM interrupt enable register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_APM_INT_EN</name>
+              <description>APM M0 interrupt enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M1_APM_INT_EN</name>
+              <description>APM M1 interrupt enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M2_APM_INT_EN</name>
+              <description>APM M2 interrupt enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M3_APM_INT_EN</name>
+              <description>APM M3 interrupt enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock gating register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0x7FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02205240</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HP_SYS</name>
+      <description>Peripheral HP_SYS</description>
+      <groupName>HP_SYS</groupName>
+      <baseAddress>0x60095000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x5C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL</name>
+          <description>EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_SPI_MANUAL_ENCRYPT</name>
+              <description>Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_DB_ENCRYPT</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_G0CB_DECRYPT</name>
+              <description>Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_USAGE_CONF</name>
+          <description>HP memory usage configuration register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_USAGE</name>
+              <description>reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SRAM_USAGE</name>
+              <description>0: cpu use hp-memory. 1:mac-dump accessing hp-memory.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAC_DUMP_ALLOC</name>
+              <description>Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEC_DPA_CONF</name>
+          <description>HP anti-DPA security configuration register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEC_DPA_LEVEL</name>
+              <description>0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEC_DPA_CFG_SEL</name>
+              <description>This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_TIMEOUT_CONF</name>
+          <description>CPU_PERI_TIMEOUT configuration register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0002FFFF</resetValue>
+          <fields>
+            <field>
+              <name>CPU_PERI_TIMEOUT_THRES</name>
+              <description>Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_PERI_TIMEOUT_INT_CLEAR</name>
+              <description>Set this bit as 1 to clear timeout interrupt</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CPU_PERI_TIMEOUT_PROTECT_EN</name>
+              <description>Set this bit as 1 to enable timeout protection for accessing cpu peripheral registers</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_TIMEOUT_ADDR</name>
+          <description>CPU_PERI_TIMEOUT_ADDR register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PERI_TIMEOUT_ADDR</name>
+              <description>Record the address information of abnormal access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_TIMEOUT_UID</name>
+          <description>CPU_PERI_TIMEOUT_UID register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PERI_TIMEOUT_UID</name>
+              <description>Record master id[4:0] &amp; master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_PERI_TIMEOUT_CONF</name>
+          <description>HP_PERI_TIMEOUT configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0002FFFF</resetValue>
+          <fields>
+            <field>
+              <name>HP_PERI_TIMEOUT_THRES</name>
+              <description>Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_PERI_TIMEOUT_INT_CLEAR</name>
+              <description>Set this bit as 1 to clear timeout interrupt</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HP_PERI_TIMEOUT_PROTECT_EN</name>
+              <description>Set this bit as 1 to enable timeout protection for accessing hp peripheral registers</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_PERI_TIMEOUT_ADDR</name>
+          <description>HP_PERI_TIMEOUT_ADDR register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_PERI_TIMEOUT_ADDR</name>
+              <description>Record the address information of abnormal access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_PERI_TIMEOUT_UID</name>
+          <description>HP_PERI_TIMEOUT_UID register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_PERI_TIMEOUT_UID</name>
+              <description>Record master id[4:0] &amp; master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEM_PERI_TIMEOUT_CONF</name>
+          <description>MODEM_PERI_TIMEOUT configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0002FFFF</resetValue>
+          <fields>
+            <field>
+              <name>MODEM_PERI_TIMEOUT_THRES</name>
+              <description>Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODEM_PERI_TIMEOUT_INT_CLEAR</name>
+              <description>Set this bit as 1 to clear timeout interrupt</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MODEM_PERI_TIMEOUT_PROTECT_EN</name>
+              <description>Set this bit as 1 to enable timeout protection for accessing modem registers</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEM_PERI_TIMEOUT_ADDR</name>
+          <description>MODEM_PERI_TIMEOUT_ADDR register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEM_PERI_TIMEOUT_ADDR</name>
+              <description>Record the address information of abnormal access</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEM_PERI_TIMEOUT_UID</name>
+          <description>MODEM_PERI_TIMEOUT_UID register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEM_PERI_TIMEOUT_UID</name>
+              <description>Record master id[4:0] &amp; master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CTRL</name>
+          <description>SDIO Control configuration register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>DIS_SDIO_PROB</name>
+              <description>Set this bit as 1 to disable SDIO_PROB function. disable by default.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_WIN_ACCESS_EN</name>
+              <description>Enable sdio slave to access other peripherals on the chip</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CONF</name>
+          <description>Retention configuration register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RETENTION_DISABLE</name>
+              <description>Set this bit as 1 to disable retention function. Not disable by default.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_TABLE_LOCK</name>
+          <description>Rom-Table lock register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ROM_TABLE_LOCK</name>
+              <description>XXXX</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_TABLE</name>
+          <description>Rom-Table register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ROM_TABLE</name>
+              <description>XXXX</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_DEBUG_RUNSTALL_CONF</name>
+          <description>Core Debug runstall configure register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_DEBUG_RUNSTALL_ENABLE</name>
+              <description>Set this field to 1 to enable debug runstall feature between HP-core and LP-core.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_TEST_CONF</name>
+          <description>MEM_TEST configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>HP_MEM_WPULSE</name>
+              <description>This field controls hp system memory WPULSE parameter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MEM_WA</name>
+              <description>This field controls hp system memory WA parameter.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MEM_RA</name>
+              <description>This field controls hp system memory RA parameter.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RND_ECO</name>
+          <description>redcy eco register.</description>
+          <addressOffset>0x3E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_ENA</name>
+              <description>Only reserved for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDCY_RESULT</name>
+              <description>Only reserved for ECO.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RND_ECO_LOW</name>
+          <description>redcy eco low register.</description>
+          <addressOffset>0x3E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_LOW</name>
+              <description>Only reserved for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RND_ECO_HIGH</name>
+          <description>redcy eco high register.</description>
+          <addressOffset>0x3E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REDCY_HIGH</name>
+              <description>Only reserved for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>HP-SYSTEM clock gating configure register</description>
+          <addressOffset>0x3F8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit as 1 to force on clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206110</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>HP-SYSTEM date information/ HP-SYSTEM version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2C0</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x60004000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x90</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C_EXT0</name>
+        <value>50</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SCL_LOW_PERIOD</name>
+          <description>Configures the low level width of the SCL
+Clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_LOW_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTR</name>
+          <description>Transmission setting</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000208</resetValue>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>1: direct output, 0: open drain output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>1: direct output, 0: open drain output.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAMPLE_SCL_LEVEL</name>
+              <description>This register is used to select the sample mode.
+1: sample SDA data on the SCL low level.
+0: sample SDA data on the SCL high level.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FULL_ACK_LEVEL</name>
+              <description>This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>Set this bit to configure the module as an I2C Master. Clear this bit to configure the
+module as an I2C Slave.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>Set this bit to start sending the data in txfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>This bit is used to control the sending mode for data needing to be sent.
+1: send data from the least significant bit,
+0: send data from the most significant bit.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>This bit is used to control the storage mode for received data.
+1: receive data from the least significant bit,
+0: receive data from the most significant bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_EN</name>
+              <description>This is the enable bit for arbitration_lost.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FSM_RST</name>
+              <description>This register is used to reset the scl FMS.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPGATE</name>
+              <description>synchronization bit</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_TX_AUTO_START_EN</name>
+              <description>This is the enable bit for slave to send data automatically</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_RW_CHECK_EN</name>
+              <description>This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_BROADCASTING_EN</name>
+              <description>This is the enable bit to support the 7bit general call function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <description>Describe I2C work status.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C000</resetValue>
+          <fields>
+            <field>
+              <name>RESP_REC</name>
+              <description>The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW</name>
+              <description>When in slave mode, 1: master reads from slave, 0: master writes to slave.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>When the I2C controller loses control of SCL line, this register changes to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDRESSED</name>
+              <description>When configured as an I2C Slave, and the address sent by the master is
+equal to the address of the slave, then this bit will be of high level.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>This field represents the amount of data needed to be sent.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STRETCH_CAUSE</name>
+              <description>The cause of stretching SCL low in slave mode. 0:  stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>This field stores the amount of received data in RAM.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_STATE_LAST</name>
+              <description>This field indicates the states of the I2C module state machine.
+0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_STATE_LAST</name>
+              <description>This field indicates the states of the state machine used to produce SCL.
+0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TO</name>
+          <description>Setting time out control for receiving data.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TIME_OUT_VALUE</name>
+              <description>This register is used to configure the timeout for receiving a data bit in APB
+clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_EN</name>
+              <description>This is the enable bit for time out control.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_ADDR</name>
+          <description>Local slave address setting</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_ADDR</name>
+              <description>When configured as an I2C Slave, this field is used to configure the slave address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_EN</name>
+              <description>This field is used to enable the slave 10-bit addressing mode in master mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_ST</name>
+          <description>FIFO status register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RADDR</name>
+              <description>This is the offset address of the APB reading from rxfifo</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_WADDR</name>
+              <description>This is the offset address of i2c module receiving data and writing to rxfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_RADDR</name>
+              <description>This is the offset address of i2c module reading from txfifo.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WADDR</name>
+              <description>This is the offset address of APB bus writing to txfifo.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW_POINT</name>
+              <description>The received data in I2C slave mode.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_CONF</name>
+          <description>FIFO configuration register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000408B</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_EN</name>
+              <description>Set this bit to enable APB nonfifo access.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_ADDR_CFG_EN</name>
+              <description>When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RST</name>
+              <description>Set this bit to reset rx-fifo.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RST</name>
+              <description>Set this bit to reset tx-fifo.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_PRT_EN</name>
+              <description>The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Rx FIFO read data.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_RDATA</name>
+              <description>The value of rx FIFO read data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDR_UNMATCH_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <description>Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_CLR</name>
+              <description>Set this bit to clear I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_CLR</name>
+              <description>Set this bit to clear I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDR_UNMATCH_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NACK_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDR_UNMATCH_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS</name>
+          <description>Status of captured I2C communication events</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDR_UNMATCH_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_HOLD</name>
+          <description>Configures the hold time after a negative SCL edge.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time to hold the data after the negative
+edge of SCL, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_SAMPLE</name>
+          <description>Configures the sample time after a positive SCL edge.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure for how long SDA is sampled, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH_PERIOD</name>
+          <description>Configures the high level width of SCL</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_HIGH_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_WAIT_HIGH_PERIOD</name>
+              <description>This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_HOLD</name>
+          <description>Configures the delay between the SDA and SCL negative edge for a start condition</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the negative edge
+of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_RSTART_SETUP</name>
+          <description>Configures the delay between the positive
+edge of SCL and the negative edge of SDA</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive
+edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_HOLD</name>
+          <description>Configures the delay after the SCL clock
+edge for a stop condition</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the delay after the STOP condition,
+in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_SETUP</name>
+          <description>Configures the delay between the SDA and
+SCL positive edge for a stop condition</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive edge
+of SCL and the positive edge of SDA, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CFG</name>
+          <description>SCL and SDA filter configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000300</resetValue>
+          <fields>
+            <field>
+              <name>SCL_FILTER_THRES</name>
+              <description>When a pulse on the SCL input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_THRES</name>
+              <description>When a pulse on the SDA input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FILTER_EN</name>
+              <description>This is the filter enable bit for SCL.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_EN</name>
+              <description>This is the filter enable bit for SDA.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>I2C CLK configuration register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00200000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>the integral part of the fractional divisor for i2c module</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>the numerator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>the denominator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>The clock selection for i2c module:0-XTAL,1-CLK_8MHz.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_ACTIVE</name>
+              <description>The clock switch for i2c module</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMD0</name>
+          <description>I2C command register 0</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND0</name>
+              <description>This is the content of command 0. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND0_DONE</name>
+              <description>When command 0 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMD1</name>
+          <description>I2C command register 1</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND1</name>
+              <description>This is the content of command 1. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND1_DONE</name>
+              <description>When command 1 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMD2</name>
+          <description>I2C command register 2</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND2</name>
+              <description>This is the content of command 2. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND2_DONE</name>
+              <description>When command 2 is done in I2C Master mode, this bit changes to high
+Level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMD3</name>
+          <description>I2C command register 3</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND3</name>
+              <description>This is the content of command 3. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND3_DONE</name>
+              <description>When command 3 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMD4</name>
+          <description>I2C command register 4</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND4</name>
+              <description>This is the content of command 4. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND4_DONE</name>
+              <description>When command 4 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMD5</name>
+          <description>I2C command register 5</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND5</name>
+              <description>This is the content of command 5. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND5_DONE</name>
+              <description>When command 5 is done in I2C Master mode, this bit changes to high level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMD6</name>
+          <description>I2C command register 6</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND6</name>
+              <description>This is the content of command 6. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND6_DONE</name>
+              <description>When command 6 is done in I2C Master mode, this bit changes to high level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMD7</name>
+          <description>I2C command register 7</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND7</name>
+              <description>This is the content of command 7. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND7_DONE</name>
+              <description>When command 7 is done in I2C Master mode, this bit changes to high level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_ST_TIME_OUT</name>
+          <description>SCL status time out register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_ST_TO_I2C</name>
+              <description>The threshold value of SCL_FSM state unchanged period. It should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_MAIN_ST_TIME_OUT</name>
+          <description>SCL main status time out register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_MAIN_ST_TO_I2C</name>
+              <description>The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_SP_CONF</name>
+          <description>Power configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_RST_SLV_EN</name>
+              <description>When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_RST_SLV_NUM</name>
+              <description>Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_PD_EN</name>
+              <description>The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_PD_EN</name>
+              <description>The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STRETCH_CONF</name>
+          <description>Set SCL stretch of I2C slave</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRETCH_PROTECT_NUM</name>
+              <description>Configure the period of I2C slave stretching SCL line.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_EN</name>
+              <description>The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_CLR</name>
+              <description>Set this bit to clear the I2C slave SCL stretch function.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_BYTE_ACK_CTL_EN</name>
+              <description>The enable bit for slave to control ACK level function.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_BYTE_ACK_LVL</name>
+              <description>Set the ACK level when slave controlling ACK level function enables.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201172</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXFIFO_START_ADDR</name>
+          <description>I2C TXFIFO base address register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TXFIFO_START_ADDR</name>
+              <description>This is the I2C txfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXFIFO_START_ADDR</name>
+          <description>I2C RXFIFO base address register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_START_ADDR</name>
+              <description>This is the I2C rxfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S0</name>
+      <description>I2S (Inter-IC Sound) Controller</description>
+      <groupName>I2S</groupName>
+      <baseAddress>0x6000C000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x60</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S1</name>
+        <value>41</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INT_RAW</name>
+          <description>I2S interrupt raw register, valid in level.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>I2S interrupt status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>I2S interrupt enable register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>I2S interrupt clear register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CONF</name>
+          <description>I2S RX configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00009600</resetValue>
+          <fields>
+            <field>
+              <name>RX_RESET</name>
+              <description>Set this bit to reset receiver</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RESET</name>
+              <description>Set this bit to reset Rx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_START</name>
+              <description>Set this bit to start receiving data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave receiver mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO</name>
+              <description>Set this bit to enable receiver  in mono mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIG_ENDIAN</name>
+              <description>I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_UPDATE</name>
+              <description>Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_CONF</name>
+              <description>I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_BYPASS</name>
+              <description>Set this bit to bypass Compress/Decompress module for received data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_STOP_MODE</name>
+              <description>0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LEFT_ALIGN</name>
+              <description>1: I2S RX left alignment mode. 0: I2S RX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_24_FILL_EN</name>
+              <description>1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIT_ORDER</name>
+              <description>I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_EN</name>
+              <description>1: Enable I2S TDM Rx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PDM_EN</name>
+              <description>1: Enable I2S PDM Rx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CONF</name>
+          <description>I2S TX configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000B200</resetValue>
+          <fields>
+            <field>
+              <name>TX_RESET</name>
+              <description>Set this bit to reset transmitter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RESET</name>
+              <description>Set this bit to reset Tx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START</name>
+              <description>Set this bit to start transmitting data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave transmitter mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO</name>
+              <description>Set this bit to enable transmitter in mono mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHAN_EQUAL</name>
+              <description>1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIG_ENDIAN</name>
+              <description>I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_UPDATE</name>
+              <description>Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_CONF</name>
+              <description>I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_BYPASS</name>
+              <description>Set this bit to bypass  Compress/Decompress module for transmitted data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP_EN</name>
+              <description>Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LEFT_ALIGN</name>
+              <description>1: I2S TX left alignment mode. 0: I2S TX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_24_FILL_EN</name>
+              <description>1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIT_ORDER</name>
+              <description>I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_EN</name>
+              <description>1: Enable I2S TDM Tx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_EN</name>
+              <description>1: Enable I2S PDM Tx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHAN_MOD</name>
+              <description>I2S transmitter channel mode configuration bits.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_LOOPBACK</name>
+              <description>Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CONF1</name>
+          <description>I2S RX configure register 1</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x2F3DE300</resetValue>
+          <fields>
+            <field>
+              <name>RX_TDM_WS_WIDTH</name>
+              <description>The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in receiver mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HALF_SAMPLE_BITS</name>
+              <description>I2S Rx half sample bits -1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN_BITS</name>
+              <description>The Rx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MSB_SHIFT</name>
+              <description>Set this bit to enable receiver in Phillips standard mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CONF1</name>
+          <description>I2S TX configure register 1</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x6F3DE300</resetValue>
+          <fields>
+            <field>
+              <name>TX_TDM_WS_WIDTH</name>
+              <description>The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in transmitter mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HALF_SAMPLE_BITS</name>
+              <description>I2S Tx half sample bits -1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN_BITS</name>
+              <description>The Tx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MSB_SHIFT</name>
+              <description>Set this bit to enable transmitter in Phillips standard mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_NO_DLY</name>
+              <description>1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CLKM_CONF</name>
+          <description>I2S RX clock configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RX_CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLK_ACTIVE</name>
+              <description>I2S Rx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLK_SEL</name>
+              <description>Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCLK_SEL</name>
+              <description>0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CLKM_CONF</name>
+          <description>I2S TX clock configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>TX_CLKM_DIV_NUM</name>
+              <description>Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b &lt;= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLK_ACTIVE</name>
+              <description>I2S Tx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLK_SEL</name>
+              <description>Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CLKM_DIV_CONF</name>
+          <description>I2S RX module clock divider configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>RX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CLKM_DIV_CONF</name>
+          <description>I2S TX module clock divider configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>TX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_PCM2PDM_CONF</name>
+          <description>I2S TX PCM2PDM configuration register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x004AA004</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_HP_BYPASS</name>
+              <description>I2S TX PDM bypass hp filter or not. The option has been removed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_OSR2</name>
+              <description>I2S TX PDM OSR2 value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_PRESCALE</name>
+              <description>I2S TX PDM prescale for sigmadelta</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_HP_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_LP_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_DITHER2</name>
+              <description>I2S TX PDM sigmadelta dither2 value</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_DITHER</name>
+              <description>I2S TX PDM sigmadelta dither value</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_DAC_2OUT_EN</name>
+              <description>I2S TX PDM dac mode enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_DAC_MODE_EN</name>
+              <description>I2S TX PDM dac 2channel enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCM2PDM_CONV_EN</name>
+              <description>I2S TX PDM Converter enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_PCM2PDM_CONF1</name>
+          <description>I2S TX PCM2PDM configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03F783C0</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_FP</name>
+              <description>I2S TX PDM Fp</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_FS</name>
+              <description>I2S TX PDM Fs</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IIR_HP_MULT12_5</name>
+              <description>The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IIR_HP_MULT12_0</name>
+              <description>The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>RX_TDM_PDM_CHAN0_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN1_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN2_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN3_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN4_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN5_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN6_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN7_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>TX_TDM_CHAN0_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN1_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN2_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN3_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN4_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN5_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN6_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN7_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_SKIP_MSK_EN</name>
+              <description>When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_TIMING</name>
+          <description>I2S RX timing control register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_SD_IN_DM</name>
+              <description>The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_OUT_DM</name>
+              <description>The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IN_DM</name>
+              <description>The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_IN_DM</name>
+              <description>The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_TIMING</name>
+          <description>I2S TX timing control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_SD_OUT_DM</name>
+              <description>The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SD1_OUT_DM</name>
+              <description>The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_OUT_DM</name>
+              <description>The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IN_DM</name>
+              <description>The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_IN_DM</name>
+              <description>The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_HUNG_CONF</name>
+          <description>I2S HUNG configure register.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000810</resetValue>
+          <fields>
+            <field>
+              <name>LC_FIFO_TIMEOUT</name>
+              <description>the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_SHIFT</name>
+              <description>The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_ENA</name>
+              <description>The enable bit for FIFO timeout</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXEOF_NUM</name>
+          <description>I2S RX data number control register.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000040</resetValue>
+          <fields>
+            <field>
+              <name>RX_EOF_NUM</name>
+              <description>The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_SIGLE_DATA</name>
+          <description>I2S signal data register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_DATA</name>
+              <description>The configured constant channel data to be sent out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>I2S TX status register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TX_IDLE</name>
+              <description>1: i2s_tx is idle state. 0: i2s_tx is working.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_CONF</name>
+          <description>I2S ETM configure register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010040</resetValue>
+          <fields>
+            <field>
+              <name>ETM_TX_SEND_WORD_NUM</name>
+              <description>I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_RX_RECEIVE_WORD_NUM</name>
+              <description>I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201070</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>I2S version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>INTMTX_CORE0</name>
+      <description>Interrupt Core</description>
+      <groupName>INTMTX_CORE0</groupName>
+      <baseAddress>0x60010000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x148</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WIFI_MAC_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_MAC_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_MAC_NMI_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_MAC_NMI_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_PWR_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_PWR_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_MAC_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_MAC_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_BB_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_NMI_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_BB_NMI_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_TIMER_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_TIMER_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COEX_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COEX_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLE_TIMER_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLE_TIMER_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLE_SEC_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLE_SEC_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_MST_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_MST_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ZB_MAC_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ZB_MAC_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PMU_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PMU_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EFUSE_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EFUSE_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_RTC_TIMER_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_RTC_TIMER_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_UART_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_UART_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_I2C_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_I2C_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_WDT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_WDT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_PERI_TIMEOUT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_PERI_TIMEOUT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_APM_M0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_APM_M0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_APM_M1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_APM_M1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ASSIST_DEBUG_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ASSIST_DEBUG_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRACE_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRACE_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_TIMEOUT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PERI_TIMEOUT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAU_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PAU_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_PERI_TIMEOUT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_PERI_TIMEOUT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEM_PERI_TIMEOUT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEM_PERI_TIMEOUT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_APM_M0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_APM_M0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_APM_M1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_APM_M1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_APM_M2_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_APM_M2_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_APM_M3_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_APM_M3_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_APM0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_APM0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MSPI_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MSPI_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UHCI0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UHCI0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UART0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UART1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LEDC_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LEDC_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAN0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAN0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAN1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAN1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RMT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RMT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_EXT0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_EXT0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG0_T0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG0_T0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG0_T1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG0_T1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG0_WDT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG0_WDT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_T0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG1_T0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_T1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG1_T1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_WDT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TG1_WDT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET2_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET2_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADC_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_ADC_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PWM_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCNT_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PCNT_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARL_IO_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PARL_IO_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_IN_CH0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_IN_CH1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH2_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_IN_CH2_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH0_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH0_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH1_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH1_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH2_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH2_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPSPI2_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPSPI2_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AES_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AES_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SHA_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RSA_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ECC_INTR_MAP</name>
+          <description>register description</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ECC_INTR_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS_REG_0</name>
+          <description>register description</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_STATUS_0</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS_REG_1</name>
+          <description>register description</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_STATUS_1</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS_REG_2</name>
+          <description>register description</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_STATUS_2</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>register description</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>REG_CLK_EN</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT_REG_DATE</name>
+          <description>register description</description>
+          <addressOffset>0x7FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02203110</resetValue>
+          <fields>
+            <field>
+              <name>INTERRUPT_REG_DATE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>INTPRI</name>
+      <description>Peripheral INTPRI</description>
+      <groupName>INTPRI</groupName>
+      <baseAddress>0x600C5000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CORE0_CPU_INT_ENABLE</name>
+          <description>register description</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_INT_ENABLE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_TYPE</name>
+          <description>register description</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_INT_TYPE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_EIP_STATUS</name>
+          <description>register description</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_INT_EIP_STATUS</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_0</name>
+          <description>register description</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_0_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_1</name>
+          <description>register description</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_1_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_2</name>
+          <description>register description</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_2_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_3</name>
+          <description>register description</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_3_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_4</name>
+          <description>register description</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_4_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_5</name>
+          <description>register description</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_5_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_6</name>
+          <description>register description</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_6_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_7</name>
+          <description>register description</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_7_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_8</name>
+          <description>register description</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_8_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_9</name>
+          <description>register description</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_9_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_10</name>
+          <description>register description</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_10_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_11</name>
+          <description>register description</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_11_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_12</name>
+          <description>register description</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_12_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_13</name>
+          <description>register description</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_13_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_14</name>
+          <description>register description</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_14_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_15</name>
+          <description>register description</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_15_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_16</name>
+          <description>register description</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_16_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_17</name>
+          <description>register description</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_17_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_18</name>
+          <description>register description</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_18_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_19</name>
+          <description>register description</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_19_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_20</name>
+          <description>register description</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_20_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_21</name>
+          <description>register description</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_21_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_22</name>
+          <description>register description</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_22_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_23</name>
+          <description>register description</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_23_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_24</name>
+          <description>register description</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_24_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_25</name>
+          <description>register description</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_25_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_26</name>
+          <description>register description</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_26_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_27</name>
+          <description>register description</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_27_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_28</name>
+          <description>register description</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_28_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_29</name>
+          <description>register description</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_29_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_30</name>
+          <description>register description</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_30_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_PRI_31</name>
+          <description>register description</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_PRI_31_MAP</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_THRESH</name>
+          <description>register description</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_INT_THRESH</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0</name>
+          <description>register description</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1</name>
+          <description>register description</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2</name>
+          <description>register description</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3</name>
+          <description>register description</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>register description</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201090</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>register description</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_CPU_INT_CLEAR</name>
+          <description>register description</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_CPU_INT_CLEAR</name>
+              <description>Need add description</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RND_ECO</name>
+          <description>redcy eco register.</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_ENA</name>
+              <description>Only reserved for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDCY_RESULT</name>
+              <description>Only reserved for ECO.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RND_ECO_LOW</name>
+          <description>redcy eco low register.</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_LOW</name>
+              <description>Only reserved for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RND_ECO_HIGH</name>
+          <description>redcy eco high register.</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REDCY_HIGH</name>
+              <description>Only reserved for ECO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>IO_MUX</name>
+      <description>Input/Output Multiplexer</description>
+      <groupName>IO_MUX</groupName>
+      <baseAddress>0x60090000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PIN_CTRL</name>
+          <description>Clock Output Configuration Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001DEF</resetValue>
+          <fields>
+            <field>
+              <name>CLK_OUT1</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT2</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT3</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>31</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>GPIO%s</name>
+          <description>IO MUX Configure Register for pad XTAL_32K_P</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled. 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEM_DIAG_EN</name>
+          <description>GPIO MATRIX Configure Register for modem diag</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEM_DIAG_EN</name>
+              <description>bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>IO MUX Version Control Register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201060</resetValue>
+          <fields>
+            <field>
+              <name>REG_DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LEDC</name>
+      <description>LED Control PWM (Pulse Width Modulation)</description>
+      <groupName>LEDC</groupName>
+      <baseAddress>0x60007000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x154</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LEDC</name>
+        <value>45</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF0</name>
+          <description>Configuration register 0 for channel %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SEL_CH</name>
+              <description>This field is used to select one of timers for channel %s.
+
+0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_OUT_EN_CH</name>
+              <description>Set this bit to enable signal output on channel %s.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_LV_CH</name>
+              <description>This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0).</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP_CH</name>
+              <description>This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_NUM_CH</name>
+              <description>This register is used to configure the maximum times of overflow minus 1.
+
+The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_EN_CH</name>
+              <description>This bit is used to enable the ovf_cnt of channel %s.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_RESET_CH</name>
+              <description>Set this bit to reset the ovf_cnt of channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_HPOINT</name>
+          <description>High point register for channel %s</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HPOINT_CH</name>
+              <description>The output value changes to high when the selected timers has reached the value specified by this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY</name>
+          <description>Initial duty cycle for channel %s</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_CH</name>
+              <description>This register is used to change the output duty by controlling the Lpoint.
+
+The output value turns to low when the selected timers has reached the Lpoint.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF1</name>
+          <description>Configuration register 1 for channel %s</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_START_CH</name>
+              <description>Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY_R</name>
+          <description>Current duty cycle for channel %s</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_CH_R</name>
+              <description>This register stores the current duty of output signal on channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_CONF</name>
+          <description>Timer %s configuration</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000000</resetValue>
+          <fields>
+            <field>
+              <name>TIMER_DUTY_RES</name>
+              <description>This register is used to control the range of the counter in timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DIV_TIMER</name>
+              <description>This register is used to configure the divisor for the divider in timer %s.
+
+The least significant eight bits represent the fractional part.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_PAUSE</name>
+              <description>This bit is used to suspend the counter in timer %s.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_RST</name>
+              <description>This bit is used to reset timer %s. The counter will show 0 after reset.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_SEL_TIMER</name>
+              <description>This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.
+
+1'h0: SLOW_CLK 1'h1: REF_TICK</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_PARA_UP</name>
+              <description>Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_VALUE</name>
+          <description>Timer %s current counter value</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_CNT</name>
+              <description>This register stores the current counter value of timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_RAW</name>
+              <description>Triggered when the timer0 has reached its maximum counter value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_RAW</name>
+              <description>Triggered when the timer1 has reached its maximum counter value.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_RAW</name>
+              <description>Triggered when the timer2 has reached its maximum counter value.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_RAW</name>
+              <description>Triggered when the timer3 has reached its maximum counter value.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>CH%s_GAMMA_WR</name>
+          <description>Ledc ch%s gamma ram write register.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_DUTY_INC</name>
+              <description>Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s.
+
+1: Increase  0: Decrease.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_DUTY_CYCLE</name>
+              <description>Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_SCALE</name>
+              <description>Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_DUTY_NUM</name>
+              <description>Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>CH%s_GAMMA_WR_ADDR</name>
+          <description>Ledc ch%s gamma ram write address register.</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_WR_ADDR</name>
+              <description>Ledc ch%s gamma ram write address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>CH%s_GAMMA_RD_ADDR</name>
+          <description>Ledc ch%s gamma ram read address register.</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_RD_ADDR</name>
+              <description>Ledc ch%s gamma ram read address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>CH%s_GAMMA_RD_DATA</name>
+          <description>Ledc ch%s gamma ram read data register.</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_RD_DATA</name>
+              <description>Ledc ch%s gamma ram read data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_GAMMA_CONF</name>
+          <description>Ledc ch%s gamma config register.</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_ENTRY_NUM</name>
+              <description>Ledc ch%s gamma entry num.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_PAUSE</name>
+              <description>Ledc ch%s gamma pause, write 1 to pause.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_RESUME</name>
+              <description>Ledc ch%s gamma resume, write 1 to resume.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVT_TASK_EN0</name>
+          <description>Ledc event task enable bit register0.</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH0_EN</name>
+              <description>Ledc ch0 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH1_EN</name>
+              <description>Ledc ch1 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH2_EN</name>
+              <description>Ledc ch2 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH3_EN</name>
+              <description>Ledc ch3 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH4_EN</name>
+              <description>Ledc ch4 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH5_EN</name>
+              <description>Ledc ch5 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH0_EN</name>
+              <description>Ledc ch0 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH1_EN</name>
+              <description>Ledc ch1 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH2_EN</name>
+              <description>Ledc ch2 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH3_EN</name>
+              <description>Ledc ch3 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH4_EN</name>
+              <description>Ledc ch4 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH5_EN</name>
+              <description>Ledc ch5 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME_OVF_TIMER0_EN</name>
+              <description>Ledc timer0 overflow event enable register, write 1 to enable this event.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME_OVF_TIMER1_EN</name>
+              <description>Ledc timer1 overflow event enable register, write 1 to enable this event.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME_OVF_TIMER2_EN</name>
+              <description>Ledc timer2 overflow event enable register, write 1 to enable this event.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME_OVF_TIMER3_EN</name>
+              <description>Ledc timer3 overflow event enable register, write 1 to enable this event.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME0_CMP_EN</name>
+              <description>Ledc timer0 compare event enable register, write 1 to enable this event.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME1_CMP_EN</name>
+              <description>Ledc timer1 compare event enable register, write 1 to enable this event.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME2_CMP_EN</name>
+              <description>Ledc timer2 compare event enable register, write 1 to enable this event.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME3_CMP_EN</name>
+              <description>Ledc timer3 compare event enable register, write 1 to enable this event.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH0_EN</name>
+              <description>Ledc ch0 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH1_EN</name>
+              <description>Ledc ch1 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH2_EN</name>
+              <description>Ledc ch2 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH3_EN</name>
+              <description>Ledc ch3 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH4_EN</name>
+              <description>Ledc ch4 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH5_EN</name>
+              <description>Ledc ch5 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVT_TASK_EN1</name>
+          <description>Ledc event task enable bit register1.</description>
+          <addressOffset>0x1A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TASK_TIMER0_RES_UPDATE_EN</name>
+              <description>Ledc timer0 res update task enable register, write 1 to enable this task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_RES_UPDATE_EN</name>
+              <description>Ledc timer1 res update task enable register, write 1 to enable this task.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_RES_UPDATE_EN</name>
+              <description>Ledc timer2 res update task enable register, write 1 to enable this task.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER3_RES_UPDATE_EN</name>
+              <description>Ledc timer3 res update task enable register, write 1 to enable this task.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER0_CAP_EN</name>
+              <description>Ledc timer0 capture task enable register, write 1 to enable this task.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_CAP_EN</name>
+              <description>Ledc timer1 capture task enable register, write 1 to enable this task.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_CAP_EN</name>
+              <description>Ledc timer2 capture task enable register, write 1 to enable this task.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER3_CAP_EN</name>
+              <description>Ledc timer3 capture task enable register, write 1 to enable this task.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH0_EN</name>
+              <description>Ledc ch0 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH1_EN</name>
+              <description>Ledc ch1 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH2_EN</name>
+              <description>Ledc ch2 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH3_EN</name>
+              <description>Ledc ch3 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH4_EN</name>
+              <description>Ledc ch4 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH5_EN</name>
+              <description>Ledc ch5 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH0_EN</name>
+              <description>Ledc ch0 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH1_EN</name>
+              <description>Ledc ch1 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH2_EN</name>
+              <description>Ledc ch2 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH3_EN</name>
+              <description>Ledc ch3 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH4_EN</name>
+              <description>Ledc ch4 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH5_EN</name>
+              <description>Ledc ch5 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER0_RST_EN</name>
+              <description>Ledc timer0 reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_RST_EN</name>
+              <description>Ledc timer1 reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_RST_EN</name>
+              <description>Ledc timer2 reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER3_RST_EN</name>
+              <description>Ledc timer3 reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER0_PAUSE_RESUME_EN</name>
+              <description>Ledc timer0 pause resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_PAUSE_RESUME_EN</name>
+              <description>Ledc timer1 pause resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_PAUSE_RESUME_EN</name>
+              <description>Ledc timer2 pause resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER3_PAUSE_RESUME_EN</name>
+              <description>Ledc timer3 pause resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVT_TASK_EN2</name>
+          <description>Ledc event task enable bit register2.</description>
+          <addressOffset>0x1A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH0_EN</name>
+              <description>Ledc ch0 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH1_EN</name>
+              <description>Ledc ch1 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH2_EN</name>
+              <description>Ledc ch2 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH3_EN</name>
+              <description>Ledc ch3 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH4_EN</name>
+              <description>Ledc ch4 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH5_EN</name>
+              <description>Ledc ch5 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH0_EN</name>
+              <description>Ledc ch0 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH1_EN</name>
+              <description>Ledc ch1 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH2_EN</name>
+              <description>Ledc ch2 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH3_EN</name>
+              <description>Ledc ch3 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH4_EN</name>
+              <description>Ledc ch4 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH5_EN</name>
+              <description>Ledc ch5 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH0_EN</name>
+              <description>Ledc ch0 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH1_EN</name>
+              <description>Ledc ch1 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH2_EN</name>
+              <description>Ledc ch2 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH3_EN</name>
+              <description>Ledc ch3 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH4_EN</name>
+              <description>Ledc ch4 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH5_EN</name>
+              <description>Ledc ch5 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TIMER%s_CMP</name>
+          <description>Ledc timer%s compare value register.</description>
+          <addressOffset>0x1B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_CMP</name>
+              <description>This register stores ledc timer%s compare value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TIMER%s_CNT_CAP</name>
+          <description>Ledc timer%s count value capture register.</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_CNT_CAP</name>
+              <description>This register stores ledc timer%s count value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>Global ledc configuration register</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_CLK_SEL</name>
+              <description>This bit is used to select clock source for the 4 timers .
+
+2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH0</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH1</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH2</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH3</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH4</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH5</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02111150</resetValue>
+          <fields>
+            <field>
+              <name>LEDC_DATE</name>
+              <description>This is the version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LPPERI</name>
+      <description>Peripheral LPPERI</description>
+      <groupName>LPPERI</groupName>
+      <baseAddress>0x600B2800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x28</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CLK_EN</name>
+          <description>need_des</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7F000000</resetValue>
+          <fields>
+            <field>
+              <name>RNG_CK_EN</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OTP_DBG_CK_EN</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_UART_CK_EN</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_IO_CK_EN</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_EXT_I2C_CK_EN</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_ANA_I2C_CK_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_CK_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_CPU_CK_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESET_EN</name>
+          <description>need_des</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUS_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OTP_DBG_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_UART_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_IO_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_EXT_I2C_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_ANA_I2C_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_CPU_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RNG_DATA</name>
+          <description>need_des</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RND_DATA</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU</name>
+          <description>need_des</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>LPCORE_DBGM_UNAVALIABLE</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMEOUT</name>
+          <description>need_des</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xBFFFC000</resetValue>
+          <fields>
+            <field>
+              <name>LP_PERI_TIMEOUT_THRES</name>
+              <description>need_des</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_PERI_TIMEOUT_INT_CLEAR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_PERI_TIMEOUT_PROTECT_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMEOUT_ADDR</name>
+          <description>need_des</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_PERI_TIMEOUT_ADDR</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMEOUT_UID</name>
+          <description>need_des</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_PERI_TIMEOUT_UID</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CTRL</name>
+          <description>need_des</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>UART_WAKEUP_FLAG_CLR</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>UART_WAKEUP_FLAG</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_WAKEUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_FORCE_PD</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_FORCE_PU</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT_SOURCE</name>
+          <description>need_des</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_INTERRUPT_SOURCE</name>
+              <description>BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>need_des</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206130</resetValue>
+          <fields>
+            <field>
+              <name>LPPERI_DATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_ANA</name>
+      <description>Peripheral LP_ANA</description>
+      <groupName>LP_ANA</groupName>
+      <baseAddress>0x600B2C00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x34</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>BOD_MODE0_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0FFC0100</resetValue>
+          <fields>
+            <field>
+              <name>BOD_MODE0_CLOSE_FLASH_ENA</name>
+              <description>need_des</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BOD_MODE0_PD_RF_ENA</name>
+              <description>need_des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BOD_MODE0_INTR_WAIT</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BOD_MODE0_RESET_WAIT</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BOD_MODE0_CNT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BOD_MODE0_INTR_ENA</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BOD_MODE0_RESET_SEL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BOD_MODE0_RESET_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BOD_MODE1_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BOD_MODE1_RESET_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CK_GLITCH_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CK_GLITCH_RESET_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIB_ENABLE</name>
+          <description>need_des</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>ANA_FIB_ENA</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>need_des</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BOD_MODE0_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>need_des</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BOD_MODE0_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>need_des</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BOD_MODE0_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>need_des</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BOD_MODE0_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_RAW</name>
+          <description>need_des</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BOD_MODE0_LP_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_ST</name>
+          <description>need_des</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BOD_MODE0_LP_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_ENA</name>
+          <description>need_des</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BOD_MODE0_LP_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_CLR</name>
+          <description>need_des</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BOD_MODE0_LP_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>need_des</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02202260</resetValue>
+          <fields>
+            <field>
+              <name>LP_ANA_DATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_AON</name>
+      <description>Peripheral LP_AON</description>
+      <groupName>LP_AON</groupName>
+      <baseAddress>0x600B1000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x5C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>STORE0</name>
+          <description>need_des</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE0</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE1</name>
+          <description>need_des</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE1</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE2</name>
+          <description>need_des</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE2</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE3</name>
+          <description>need_des</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE3</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE4</name>
+          <description>need_des</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE4</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE5</name>
+          <description>need_des</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE5</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE6</name>
+          <description>need_des</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE6</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE7</name>
+          <description>need_des</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE7</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE8</name>
+          <description>need_des</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE8</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE9</name>
+          <description>need_des</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_STORE9</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_MUX</name>
+          <description>need_des</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_HOLD0</name>
+          <description>need_des</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_HOLD0</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_HOLD1</name>
+          <description>need_des</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_HOLD1</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYS_CFG</name>
+          <description>need_des</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FORCE_DOWNLOAD_BOOT</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HPSYS_SW_RESET</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUCORE0_CFG</name>
+          <description>need_des</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>CPU_CORE0_SW_STALL</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_CORE0_SW_RESET</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CPU_CORE0_OCD_HALT_ON_RESET</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_CORE0_STAT_VECTOR_SEL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_CORE0_DRESET_MASK</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX</name>
+          <description>need_des</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RESET_DISABLE</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_WAKEUP_STATUS</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP_STATUS_CLR</name>
+              <description>need_des</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP_LV</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP_FILTER</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB</name>
+          <description>need_des</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RESET_DISABLE</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LPBUS</name>
+          <description>need_des</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xB0200000</resetValue>
+          <fields>
+            <field>
+              <name>FAST_MEM_WPULSE</name>
+              <description>This field controls fast memory WPULSE parameter.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_MEM_WA</name>
+              <description>This field controls fast memory WA parameter.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_MEM_RA</name>
+              <description>This field controls fast memory RA parameter.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_MEM_MUX_FSM_IDLE</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAST_MEM_MUX_SEL_STATUS</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAST_MEM_MUX_SEL_UPDATE</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAST_MEM_MUX_SEL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_ACTIVE</name>
+          <description>need_des</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02800000</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_ACT_DNUM</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LPCORE</name>
+          <description>need_des</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_WAKEUP_FLAG_CLR</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ETM_WAKEUP_FLAG</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DISABLE</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_CCT</name>
+          <description>need_des</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR2_PWDET_CCT</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>need_des</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02205280</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_APM</name>
+      <description>Peripheral LP_APM</description>
+      <groupName>LP_APM</groupName>
+      <baseAddress>0x600B3800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x64</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>REGION_FILTER_EN</name>
+          <description>Region filter enable register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>REGION_FILTER_EN</name>
+              <description>Region filter enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION0_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION0_ADDR_START</name>
+              <description>Start address of region0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION0_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION0_ADDR_END</name>
+              <description>End address of region0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION0_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION0_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION1_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION1_ADDR_START</name>
+              <description>Start address of region1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION1_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION1_ADDR_END</name>
+              <description>End address of region1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION1_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION1_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION2_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION2_ADDR_START</name>
+              <description>Start address of region2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION2_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION2_ADDR_END</name>
+              <description>End address of region2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION2_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION2_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION3_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION3_ADDR_START</name>
+              <description>Start address of region3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION3_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION3_ADDR_END</name>
+              <description>End address of region3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION3_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION3_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC_CTRL</name>
+          <description>PMS function control register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M0_PMS_FUNC_EN</name>
+              <description>PMS M0 function enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M1_PMS_FUNC_EN</name>
+              <description>PMS M1 function enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_STATUS</name>
+          <description>M0 status register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_EXCEPTION_STATUS</name>
+              <description>Exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_STATUS_CLR</name>
+          <description>M0 status clear register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_REGION_STATUS_CLR</name>
+              <description>Clear exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_EXCEPTION_INFO0</name>
+          <description>M0 exception_info0 register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_EXCEPTION_REGION</name>
+              <description>Exception region</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M0_EXCEPTION_MODE</name>
+              <description>Exception mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M0_EXCEPTION_ID</name>
+              <description>Exception id information</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_EXCEPTION_INFO1</name>
+          <description>M0 exception_info1 register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_EXCEPTION_ADDR</name>
+              <description>Exception addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_STATUS</name>
+          <description>M1 status register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M1_EXCEPTION_STATUS</name>
+              <description>Exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_STATUS_CLR</name>
+          <description>M1 status clear register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M1_REGION_STATUS_CLR</name>
+              <description>Clear exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_EXCEPTION_INFO0</name>
+          <description>M1 exception_info0 register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M1_EXCEPTION_REGION</name>
+              <description>Exception region</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M1_EXCEPTION_MODE</name>
+              <description>Exception mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M1_EXCEPTION_ID</name>
+              <description>Exception id information</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_EXCEPTION_INFO1</name>
+          <description>M1 exception_info1 register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M1_EXCEPTION_ADDR</name>
+              <description>Exception addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_EN</name>
+          <description>APM interrupt enable register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_APM_INT_EN</name>
+              <description>APM M0 interrupt enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>M1_APM_INT_EN</name>
+              <description>APM M1 interrupt enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock gating register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02205240</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_APM0</name>
+      <description>Peripheral LP_APM0</description>
+      <groupName>LP_APM0</groupName>
+      <baseAddress>0x60099800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x54</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>REGION_FILTER_EN</name>
+          <description>Region filter enable register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>REGION_FILTER_EN</name>
+              <description>Region filter enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION0_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION0_ADDR_START</name>
+              <description>Start address of region0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION0_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION0_ADDR_END</name>
+              <description>End address of region0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION0_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION0_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION0_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION1_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION1_ADDR_START</name>
+              <description>Start address of region1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION1_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION1_ADDR_END</name>
+              <description>End address of region1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION1_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION1_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION1_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION2_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION2_ADDR_START</name>
+              <description>Start address of region2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION2_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION2_ADDR_END</name>
+              <description>End address of region2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION2_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION2_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION2_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION3_ADDR_START</name>
+          <description>Region address register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION3_ADDR_START</name>
+              <description>Start address of region3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION3_ADDR_END</name>
+          <description>Region address register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>REGION3_ADDR_END</name>
+              <description>End address of region3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGION3_PMS_ATTR</name>
+          <description>Region access authority attribute register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGION3_R0_PMS_X</name>
+              <description>Region execute authority in REE_MODE0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R0_PMS_W</name>
+              <description>Region write authority in REE_MODE0</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R0_PMS_R</name>
+              <description>Region read authority in REE_MODE0</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R1_PMS_X</name>
+              <description>Region execute authority in REE_MODE1</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R1_PMS_W</name>
+              <description>Region write authority in REE_MODE1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R1_PMS_R</name>
+              <description>Region read authority in REE_MODE1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R2_PMS_X</name>
+              <description>Region execute authority in REE_MODE2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R2_PMS_W</name>
+              <description>Region write authority in REE_MODE2</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGION3_R2_PMS_R</name>
+              <description>Region read authority in REE_MODE2</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC_CTRL</name>
+          <description>PMS function control register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>M0_PMS_FUNC_EN</name>
+              <description>PMS M0 function enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_STATUS</name>
+          <description>M0 status register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_EXCEPTION_STATUS</name>
+              <description>Exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_STATUS_CLR</name>
+          <description>M0 status clear register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_REGION_STATUS_CLR</name>
+              <description>Clear exception status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_EXCEPTION_INFO0</name>
+          <description>M0 exception_info0 register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_EXCEPTION_REGION</name>
+              <description>Exception region</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M0_EXCEPTION_MODE</name>
+              <description>Exception mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>M0_EXCEPTION_ID</name>
+              <description>Exception id information</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M0_EXCEPTION_INFO1</name>
+          <description>M0 exception_info1 register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_EXCEPTION_ADDR</name>
+              <description>Exception addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_EN</name>
+          <description>APM interrupt enable register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_APM_INT_EN</name>
+              <description>APM M0 interrupt enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock gating register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0x7FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02205240</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_CLKRST</name>
+      <description>Peripheral LP_CLKRST</description>
+      <groupName>LP_CLKRST</groupName>
+      <baseAddress>0x600B0400</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x34</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>LP_CLK_CONF</name>
+          <description>need_des</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>SLOW_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_PERI_DIV_NUM</name>
+              <description>need_des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_CLK_PO_EN</name>
+          <description>need_des</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>AON_SLOW_OEN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AON_FAST_OEN</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOSC_OEN</name>
+              <description>need_des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FOSC_OEN</name>
+              <description>need_des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OSC32K_OEN</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_OEN</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_EFUSE_OEN</name>
+              <description>need_des</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOW_OEN</name>
+              <description>need_des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_OEN</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RNG_OEN</name>
+              <description>need_des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPBUS_OEN</name>
+              <description>need_des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_CLK_EN</name>
+          <description>need_des</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FAST_ORI_GATE</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_RST_EN</name>
+          <description>need_des</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AON_EFUSE_CORE_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_TIMER_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANA_PERI_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESET_CAUSE</name>
+          <description>need_des</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>RESET_CAUSE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_RESET_FLAG</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_RESET_CAUSE_CLR</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_RESET_FLAG_SET</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_RESET_FLAG_CLR</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_RESET</name>
+          <description>need_des</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x04400000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_WDT_CPU_RESET_LENGTH</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_WDT_CPU_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_STALL_WAIT</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_STALL_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FOSC_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x2B000000</resetValue>
+          <fields>
+            <field>
+              <name>FOSC_DFREQ</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RC32K_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x2B000000</resetValue>
+          <fields>
+            <field>
+              <name>RC32K_DFREQ</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_TO_HP</name>
+          <description>need_des</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xF0000000</resetValue>
+          <fields>
+            <field>
+              <name>ICG_HP_XTAL32K</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICG_HP_SOSC</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICG_HP_OSC32K</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICG_HP_FOSC</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LPMEM_FORCE</name>
+          <description>need_des</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LPMEM_CLK_FORCE_ON</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LPPERI</name>
+          <description>need_des</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_I2C_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_UART_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL32K</name>
+          <description>need_des</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x66C00000</resetValue>
+          <fields>
+            <field>
+              <name>DRES_XTAL32K</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DGM_XTAL32K</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUF_XTAL32K</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_XTAL32K</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>need_des</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206090</resetValue>
+          <fields>
+            <field>
+              <name>CLKRST_DATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_I2C0</name>
+      <description>Peripheral LP_I2C0</description>
+      <groupName>LP_I2C0</groupName>
+      <baseAddress>0x600B1800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>I2C_SCL_LOW_PERIOD</name>
+          <description>Configures the low level width of the SCL
+Clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SCL_LOW_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_CTR</name>
+          <description>Transmission setting</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000208</resetValue>
+          <fields>
+            <field>
+              <name>I2C_SDA_FORCE_OUT</name>
+              <description>1: direct output, 0: open drain output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCL_FORCE_OUT</name>
+              <description>1: direct output, 0: open drain output.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SAMPLE_SCL_LEVEL</name>
+              <description>This register is used to select the sample mode.
+1: sample SDA data on the SCL low level.
+0: sample SDA data on the SCL high level.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RX_FULL_ACK_LEVEL</name>
+              <description>This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_TRANS_START</name>
+              <description>Set this bit to start sending the data in txfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_TX_LSB_FIRST</name>
+              <description>This bit is used to control the sending mode for data needing to be sent.
+1: send data from the least significant bit,
+0: send data from the most significant bit.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RX_LSB_FIRST</name>
+              <description>This bit is used to control the storage mode for received data.
+1: receive data from the least significant bit,
+0: receive data from the most significant bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_CLK_EN</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_ARBITRATION_EN</name>
+              <description>This is the enable bit for arbitration_lost.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_FSM_RST</name>
+              <description>This register is used to reset the scl FMS.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_CONF_UPGATE</name>
+              <description>synchronization bit</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SR</name>
+          <description>Describe I2C work status.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_RESP_REC</name>
+              <description>The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_ARB_LOST</name>
+              <description>When the I2C controller loses control of SCL line, this register changes to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_BUS_BUSY</name>
+              <description>1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_CNT</name>
+              <description>This field represents the amount of data needed to be sent.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_CNT</name>
+              <description>This field stores the amount of received data in RAM.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_SCL_MAIN_STATE_LAST</name>
+              <description>This field indicates the states of the I2C module state machine.
+0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_SCL_STATE_LAST</name>
+              <description>This field indicates the states of the state machine used to produce SCL.
+0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_TO</name>
+          <description>Setting time out control for receiving data.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2C_TIME_OUT_VALUE</name>
+              <description>This register is used to configure the timeout for receiving a data bit in APB
+clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_TIME_OUT_EN</name>
+              <description>This is the enable bit for time out control.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_FIFO_ST</name>
+          <description>FIFO status register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_RXFIFO_RADDR</name>
+              <description>This is the offset address of the APB reading from rxfifo</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_WADDR</name>
+              <description>This is the offset address of i2c module receiving data and writing to rxfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_RADDR</name>
+              <description>This is the offset address of i2c module reading from txfifo.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_WADDR</name>
+              <description>This is the offset address of APB bus writing to txfifo.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_FIFO_CONF</name>
+          <description>FIFO configuration register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004046</resetValue>
+          <fields>
+            <field>
+              <name>I2C_RXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_NONFIFO_EN</name>
+              <description>Set this bit to enable APB nonfifo access.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RX_FIFO_RST</name>
+              <description>Set this bit to reset rx-fifo.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_TX_FIFO_RST</name>
+              <description>Set this bit to reset tx-fifo.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_FIFO_PRT_EN</name>
+              <description>The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_DATA</name>
+          <description>Rx FIFO read data.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_FIFO_RDATA</name>
+              <description>The value of rx FIFO read data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>I2C_RXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_END_DETECT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_BYTE_TRANS_DONE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_ARBITRATION_LOST_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_MST_TXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TRANS_COMPLETE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TIME_OUT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TRANS_START_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_NACK_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_SCL_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_SCL_MAIN_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_DET_START_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_RXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_END_DETECT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_BYTE_TRANS_DONE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_ARBITRATION_LOST_INT_CLR</name>
+              <description>Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_MST_TXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_TRANS_COMPLETE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_TIME_OUT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_TRANS_START_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_NACK_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_SCL_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_SCL_MAIN_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2C_DET_START_INT_CLR</name>
+              <description>Set this bit to clear I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_RXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_END_DETECT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_BYTE_TRANS_DONE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_ARBITRATION_LOST_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_MST_TXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_TRANS_COMPLETE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_TIME_OUT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_TRANS_START_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_NACK_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCL_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCL_MAIN_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_DET_START_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_INT_STATUS</name>
+          <description>Status of captured I2C communication events</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_RXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_END_DETECT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_BYTE_TRANS_DONE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_ARBITRATION_LOST_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_MST_TXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TRANS_COMPLETE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TIME_OUT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TRANS_START_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_NACK_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_TXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_RXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_SCL_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_SCL_MAIN_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2C_DET_START_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SDA_HOLD</name>
+          <description>Configures the hold time after a negative SCL edge.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time to hold the data after the negative
+edge of SCL, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SDA_SAMPLE</name>
+          <description>Configures the sample time after a positive SCL edge.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure for how long SDA is sampled, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SCL_HIGH_PERIOD</name>
+          <description>Configures the high level width of SCL</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SCL_HIGH_PERIOD</name>
+              <description>This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCL_WAIT_HIGH_PERIOD</name>
+              <description>This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SCL_START_HOLD</name>
+          <description>Configures the delay between the SDA and SCL negative edge for a start condition</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the negative edge
+of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SCL_RSTART_SETUP</name>
+          <description>Configures the delay between the positive
+edge of SCL and the negative edge of SDA</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive
+edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SCL_STOP_HOLD</name>
+          <description>Configures the delay after the SCL clock
+edge for a stop condition</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the delay after the STOP condition,
+in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SCL_STOP_SETUP</name>
+          <description>Configures the delay between the SDA and
+SCL positive edge for a stop condition</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive edge
+of SCL and the positive edge of SDA, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_FILTER_CFG</name>
+          <description>SCL and SDA filter configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000300</resetValue>
+          <fields>
+            <field>
+              <name>I2C_SCL_FILTER_THRES</name>
+              <description>When a pulse on the SCL input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SDA_FILTER_THRES</name>
+              <description>When a pulse on the SDA input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCL_FILTER_EN</name>
+              <description>This is the filter enable bit for SCL.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SDA_FILTER_EN</name>
+              <description>This is the filter enable bit for SDA.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_CLK_CONF</name>
+          <description>I2C CLK configuration register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00200000</resetValue>
+          <fields>
+            <field>
+              <name>I2C_SCLK_DIV_NUM</name>
+              <description>the integral part of the fractional divisor for i2c module</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCLK_DIV_A</name>
+              <description>the numerator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCLK_DIV_B</name>
+              <description>the denominator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCLK_SEL</name>
+              <description>The clock selection for i2c module:0-XTAL,1-CLK_8MHz.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCLK_ACTIVE</name>
+              <description>The clock switch for i2c module</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_COMD0</name>
+          <description>I2C command register 0</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_COMMAND0</name>
+              <description>This is the content of command 0. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_COMMAND0_DONE</name>
+              <description>When command 0 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_COMD1</name>
+          <description>I2C command register 1</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_COMMAND1</name>
+              <description>This is the content of command 1. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_COMMAND1_DONE</name>
+              <description>When command 1 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_COMD2</name>
+          <description>I2C command register 2</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_COMMAND2</name>
+              <description>This is the content of command 2. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_COMMAND2_DONE</name>
+              <description>When command 2 is done in I2C Master mode, this bit changes to high
+Level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_COMD3</name>
+          <description>I2C command register 3</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_COMMAND3</name>
+              <description>This is the content of command 3. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_COMMAND3_DONE</name>
+              <description>When command 3 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_COMD4</name>
+          <description>I2C command register 4</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_COMMAND4</name>
+              <description>This is the content of command 4. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_COMMAND4_DONE</name>
+              <description>When command 4 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_COMD5</name>
+          <description>I2C command register 5</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_COMMAND5</name>
+              <description>This is the content of command 5. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_COMMAND5_DONE</name>
+              <description>When command 5 is done in I2C Master mode, this bit changes to high level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_COMD6</name>
+          <description>I2C command register 6</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_COMMAND6</name>
+              <description>This is the content of command 6. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_COMMAND6_DONE</name>
+              <description>When command 6 is done in I2C Master mode, this bit changes to high level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_COMD7</name>
+          <description>I2C command register 7</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_COMMAND7</name>
+              <description>This is the content of command 7. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_COMMAND7_DONE</name>
+              <description>When command 7 is done in I2C Master mode, this bit changes to high level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SCL_ST_TIME_OUT</name>
+          <description>SCL status time out register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2C_SCL_ST_TO_I2C</name>
+              <description>The threshold value of SCL_FSM state unchanged period. It should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SCL_MAIN_ST_TIME_OUT</name>
+          <description>SCL main status time out register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2C_SCL_MAIN_ST_TO_I2C</name>
+              <description>The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SCL_SP_CONF</name>
+          <description>Power configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SCL_RST_SLV_EN</name>
+              <description>When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCL_RST_SLV_NUM</name>
+              <description>Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCL_PD_EN</name>
+              <description>The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SDA_PD_EN</name>
+              <description>The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201143</resetValue>
+          <fields>
+            <field>
+              <name>I2C_DATE</name>
+              <description>This is the the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_TXFIFO_START_ADDR</name>
+          <description>I2C TXFIFO base address register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_TXFIFO_START_ADDR</name>
+              <description>This is the I2C txfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_RXFIFO_START_ADDR</name>
+          <description>I2C RXFIFO base address register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_RXFIFO_START_ADDR</name>
+              <description>This is the I2C rxfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_I2C_ANA_MST</name>
+      <description>Peripheral LP_I2C_ANA_MST</description>
+      <groupName>LP_I2C_ANA_MST</groupName>
+      <baseAddress>0x600B2400</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>I2C0_CTRL</name>
+          <description>need_des</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C0_CTRL</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C0_BUSY</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C0_CONF</name>
+          <description>need_des</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07000000</resetValue>
+          <fields>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C0_CONF</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C0_STATUS</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C0_DATA</name>
+          <description>need_des</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000900</resetValue>
+          <fields>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C0_RDATA</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C0_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C_MST_SEL</name>
+              <description>need  des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ANA_CONF1</name>
+          <description>need_des</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_I2C_ANA_MAST_ANA_CONF1</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NOUSE</name>
+          <description>need_des</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C_MST_NOUSE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEVICE_EN</name>
+          <description>need_des</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C_DEVICE_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>need_des</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02007301</resetValue>
+          <fields>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C_MAT_DATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_I2C_ANA_MAST_I2C_MAT_CLK_EN</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_IO</name>
+      <description>Peripheral LP_IO</description>
+      <groupName>LP_IO</groupName>
+      <baseAddress>0x600B2000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x7C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>OUT_DATA</name>
+          <description>need des</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_OUT_DATA</name>
+              <description>set lp gpio output data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DATA_W1TS</name>
+          <description>need des</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_OUT_DATA_W1TS</name>
+              <description>set one time output data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_DATA_W1TC</name>
+          <description>need des</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_OUT_DATA_W1TC</name>
+              <description>clear one time output data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_ENABLE</name>
+          <description>need des</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_ENABLE</name>
+              <description>set lp gpio output data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_ENABLE_W1TS</name>
+          <description>need des</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_ENABLE_W1TS</name>
+              <description>set one time output data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_ENABLE_W1TC</name>
+          <description>need des</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_ENABLE_W1TC</name>
+              <description>clear one time output data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>need des</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_STATUS_INTERRUPT</name>
+              <description>set lp gpio output data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TS</name>
+          <description>need des</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_STATUS_W1TS</name>
+              <description>set one time output data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TC</name>
+          <description>need des</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_STATUS_W1TC</name>
+              <description>clear one time output data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <description>need des</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_IN_DATA_NEXT</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIN0</name>
+          <description>need des</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO0_SYNC_BYPASS</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_PAD_DRIVER</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_EDGE_WAKEUP_CLR</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_INT_TYPE</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_WAKEUP_ENABLE</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_FILTER_EN</name>
+              <description>need des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIN1</name>
+          <description>need des</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO1_SYNC_BYPASS</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_PAD_DRIVER</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_EDGE_WAKEUP_CLR</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_INT_TYPE</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_WAKEUP_ENABLE</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_FILTER_EN</name>
+              <description>need des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIN2</name>
+          <description>need des</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO2_SYNC_BYPASS</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_PAD_DRIVER</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_EDGE_WAKEUP_CLR</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_INT_TYPE</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_WAKEUP_ENABLE</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_FILTER_EN</name>
+              <description>need des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIN3</name>
+          <description>need des</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO3_SYNC_BYPASS</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_PAD_DRIVER</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_EDGE_WAKEUP_CLR</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_INT_TYPE</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_WAKEUP_ENABLE</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_FILTER_EN</name>
+              <description>need des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIN4</name>
+          <description>need des</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO4_SYNC_BYPASS</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_PAD_DRIVER</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_EDGE_WAKEUP_CLR</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_INT_TYPE</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_WAKEUP_ENABLE</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_FILTER_EN</name>
+              <description>need des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIN5</name>
+          <description>need des</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO5_SYNC_BYPASS</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_PAD_DRIVER</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_EDGE_WAKEUP_CLR</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_INT_TYPE</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_WAKEUP_ENABLE</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_FILTER_EN</name>
+              <description>need des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIN6</name>
+          <description>need des</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO6_SYNC_BYPASS</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_PAD_DRIVER</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_EDGE_WAKEUP_CLR</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_INT_TYPE</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_WAKEUP_ENABLE</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_FILTER_EN</name>
+              <description>need des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PIN7</name>
+          <description>need des</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO7_SYNC_BYPASS</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_PAD_DRIVER</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_EDGE_WAKEUP_CLR</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_INT_TYPE</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_WAKEUP_ENABLE</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_FILTER_EN</name>
+              <description>need des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO0</name>
+          <description>need des</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO0_MCU_OE</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_SLP_SEL</name>
+              <description>need des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_MCU_WPD</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_MCU_WPU</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_MCU_IE</name>
+              <description>need des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_MCU_DRV</name>
+              <description>need des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_FUN_WPD</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_FUN_WPU</name>
+              <description>need des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_FUN_IE</name>
+              <description>need des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_FUN_DRV</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO0_MCU_SEL</name>
+              <description>need des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO1</name>
+          <description>need des</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO1_MCU_OE</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_SLP_SEL</name>
+              <description>need des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_MCU_WPD</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_MCU_WPU</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_MCU_IE</name>
+              <description>need des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_MCU_DRV</name>
+              <description>need des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_FUN_WPD</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_FUN_WPU</name>
+              <description>need des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_FUN_IE</name>
+              <description>need des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_FUN_DRV</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO1_MCU_SEL</name>
+              <description>need des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO2</name>
+          <description>need des</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO2_MCU_OE</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_SLP_SEL</name>
+              <description>need des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_MCU_WPD</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_MCU_WPU</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_MCU_IE</name>
+              <description>need des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_MCU_DRV</name>
+              <description>need des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_FUN_WPD</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_FUN_WPU</name>
+              <description>need des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_FUN_IE</name>
+              <description>need des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_FUN_DRV</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO2_MCU_SEL</name>
+              <description>need des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO3</name>
+          <description>need des</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO3_MCU_OE</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_SLP_SEL</name>
+              <description>need des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_MCU_WPD</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_MCU_WPU</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_MCU_IE</name>
+              <description>need des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_MCU_DRV</name>
+              <description>need des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_FUN_WPD</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_FUN_WPU</name>
+              <description>need des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_FUN_IE</name>
+              <description>need des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_FUN_DRV</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO3_MCU_SEL</name>
+              <description>need des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO4</name>
+          <description>need des</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO4_MCU_OE</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_SLP_SEL</name>
+              <description>need des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_MCU_WPD</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_MCU_WPU</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_MCU_IE</name>
+              <description>need des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_MCU_DRV</name>
+              <description>need des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_FUN_WPD</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_FUN_WPU</name>
+              <description>need des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_FUN_IE</name>
+              <description>need des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_FUN_DRV</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO4_MCU_SEL</name>
+              <description>need des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO5</name>
+          <description>need des</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO5_MCU_OE</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_SLP_SEL</name>
+              <description>need des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_MCU_WPD</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_MCU_WPU</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_MCU_IE</name>
+              <description>need des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_MCU_DRV</name>
+              <description>need des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_FUN_WPD</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_FUN_WPU</name>
+              <description>need des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_FUN_IE</name>
+              <description>need des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_FUN_DRV</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO5_MCU_SEL</name>
+              <description>need des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO6</name>
+          <description>need des</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO6_MCU_OE</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_SLP_SEL</name>
+              <description>need des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_MCU_WPD</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_MCU_WPU</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_MCU_IE</name>
+              <description>need des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_MCU_DRV</name>
+              <description>need des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_FUN_WPD</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_FUN_WPU</name>
+              <description>need des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_FUN_IE</name>
+              <description>need des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_FUN_DRV</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO6_MCU_SEL</name>
+              <description>need des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO7</name>
+          <description>need des</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO7_MCU_OE</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_SLP_SEL</name>
+              <description>need des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_MCU_WPD</name>
+              <description>need des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_MCU_WPU</name>
+              <description>need des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_MCU_IE</name>
+              <description>need des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_MCU_DRV</name>
+              <description>need des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_FUN_WPD</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_FUN_WPU</name>
+              <description>need des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_FUN_IE</name>
+              <description>need des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_FUN_DRV</name>
+              <description>need des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_GPIO7_MCU_SEL</name>
+              <description>need des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_INTERRUPT</name>
+          <description>need des</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_GPIO_STATUS_INTERRUPT_NEXT</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEBUG_SEL0</name>
+          <description>need des</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_DEBUG_SEL0</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_DEBUG_SEL1</name>
+              <description>need des</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_DEBUG_SEL2</name>
+              <description>need des</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_DEBUG_SEL3</name>
+              <description>need des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DEBUG_SEL1</name>
+          <description>need des</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_DEBUG_SEL4</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LPI2C</name>
+          <description>need des</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC0000000</resetValue>
+          <fields>
+            <field>
+              <name>LP_I2C_SDA_IE</name>
+              <description>need des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_I2C_SCL_IE</name>
+              <description>need des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>need des</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02202100</resetValue>
+          <fields>
+            <field>
+              <name>LP_IO_DATE</name>
+              <description>need des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>need des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_TEE</name>
+      <description>Peripheral LP_TEE</description>
+      <groupName>LP_TEE</groupName>
+      <baseAddress>0x600B3400</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x10</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>M0_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M0_MODE</name>
+              <description>M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>Clock gating register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FORCE_ACC_HP</name>
+          <description>need_des</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_AON_FORCE_ACC_HPMEM_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02205270</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_tee_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_TIMER</name>
+      <description>Peripheral LP_TIMER</description>
+      <groupName>LP_TIMER</groupName>
+      <baseAddress>0x600B0C00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>TAR0_LOW</name>
+          <description>need_des</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_TAR_LOW0</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TAR0_HIGH</name>
+          <description>need_des</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_TAR_HIGH0</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_TAR_EN0</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TAR1_LOW</name>
+          <description>need_des</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_TAR_LOW1</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TAR1_HIGH</name>
+          <description>need_des</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_TAR_HIGH1</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_TAR_EN1</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UPDATE</name>
+          <description>need_des</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_UPDATE</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_XTAL_OFF</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_SYS_STALL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_SYS_RST</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAIN_BUF0_LOW</name>
+          <description>need_des</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_BUF0_LOW</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAIN_BUF0_HIGH</name>
+          <description>need_des</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_BUF0_HIGH</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAIN_BUF1_LOW</name>
+          <description>need_des</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_BUF1_LOW</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAIN_BUF1_HIGH</name>
+          <description>need_des</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_BUF1_HIGH</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAIN_OVERFLOW</name>
+          <description>need_des</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_ALARM_LOAD</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>need_des</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OVERFLOW_RAW</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOC_WAKEUP_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>need_des</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OVERFLOW_ST</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOC_WAKEUP_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>need_des</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OVERFLOW_ENA</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOC_WAKEUP_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>need_des</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OVERFLOW_CLR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SOC_WAKEUP_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_RAW</name>
+          <description>need_des</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_OVERFLOW_LP_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_LP_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_ST</name>
+          <description>need_des</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_OVERFLOW_LP_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_LP_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_ENA</name>
+          <description>need_des</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_OVERFLOW_LP_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_LP_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_CLR</name>
+          <description>need_des</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAIN_TIMER_OVERFLOW_LP_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_LP_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>need_des</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02111150</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_UART</name>
+      <description>Peripheral LP_UART</description>
+      <groupName>LP_UART</groupName>
+      <baseAddress>0x600B1400</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x84</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>FIFO</name>
+          <description>FIFO data register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RD_BYTE</name>
+              <description>UART 0 accesses FIFO via this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error in the data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error .</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters after all data in Tx-FIFO are sent.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ST</name>
+              <description>This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ST</name>
+              <description>This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ST</name>
+              <description>This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ST</name>
+              <description>This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ST</name>
+              <description>This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ST</name>
+              <description>This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ST</name>
+              <description>This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ST</name>
+              <description>This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ST</name>
+              <description>This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ST</name>
+              <description>This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ST</name>
+              <description>This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ST</name>
+              <description>This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ST</name>
+              <description>This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_full_int_st register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ENA</name>
+              <description>This is the enable bit for txfifo_empty_int_st register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for parity_err_int_st register.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for frm_err_int_st register.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_ovf_int_st register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ENA</name>
+              <description>This is the enable bit for dsr_chg_int_st register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ENA</name>
+              <description>This is the enable bit for cts_chg_int_st register.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ENA</name>
+              <description>This is the enable bit for brk_det_int_st register.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_tout_int_st register.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ENA</name>
+              <description>This is the enable bit for sw_xon_int_st register.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ENA</name>
+              <description>This is the enable bit for sw_xoff_int_st register.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>This is the enable bit for glitch_det_int_st register.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_done_int_st register.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_idle_done_int_st register.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_done_int_st register.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ENA</name>
+              <description>This is the enable bit for at_cmd_char_det_int_st register.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ENA</name>
+              <description>This is the enable bit for uart_wakeup_int_st register.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_full_int_raw interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear txfifo_empty_int_raw interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear parity_err_int_raw interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear frm_err_int_raw interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear rxfifo_ovf_int_raw interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_CLR</name>
+              <description>Set this bit to clear the dsr_chg_int_raw interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear the cts_chg_int_raw interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_CLR</name>
+              <description>Set this bit to clear the brk_det_int_raw interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_tout_int_raw interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_CLR</name>
+              <description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_CLR</name>
+              <description>Set this bit to clear the sw_xoff_int_raw interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Set this bit to clear the glitch_det_int_raw interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_done_int_raw interrupt..</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_idle_done_int_raw interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_done_int_raw interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_CLR</name>
+              <description>Set this bit to clear the at_cmd_char_det_int_raw interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_CLR</name>
+              <description>Set this bit to clear the uart_wakeup_int_raw interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV_SYNC</name>
+          <description>Clock divider configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000002B6</resetValue>
+          <fields>
+            <field>
+              <name>CLKDIV</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKDIV_FRAG</name>
+              <description>The decimal part of the frequency divider factor.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_FILT</name>
+          <description>Rx Filter configuration</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>GLITCH_FILT</name>
+              <description>when input pulse width is lower than this value the pulse is ignored.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_FILT_EN</name>
+              <description>Set this bit to enable Rx signal filter.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>UART status register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xE000C000</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>Stores the byte number of valid data in Rx-FIFO.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSRN</name>
+              <description>The register represent the level value of the internal uart dsr signal.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTSN</name>
+              <description>This register represent the level value of the internal uart cts signal.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXD</name>
+              <description>This register represent the  level value of the internal uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>Stores the byte number of data in Tx-FIFO.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTRN</name>
+              <description>This bit represents the level of the internal uart dtr signal.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTSN</name>
+              <description>This bit represents the level of the internal uart rts signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXD</name>
+              <description>This bit represents the  level of the internal uart txd signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0_SYNC</name>
+          <description>Configuration register 0</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0010001C</resetValue>
+          <fields>
+            <field>
+              <name>PARITY</name>
+              <description>This register is used to configure the parity check mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_EN</name>
+              <description>Set this bit to enable uart parity check.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIT_NUM</name>
+              <description>This register is used to set the length of data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOP_BIT_NUM</name>
+              <description>This register is used to set the length of  stop bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_BRK</name>
+              <description>Set this bit to enbale transmitter to  send NULL when the process of sending data is done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOPBACK</name>
+              <description>Set this bit to enable uart loopback test mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FLOW_EN</name>
+              <description>Set this bit to enable flow control function for transmitter.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXD_INV</name>
+              <description>Set this bit to inverse the level value of uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_INV</name>
+              <description>Set this bit to inverse the level value of uart txd signal.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIS_RX_DAT_OVF</name>
+              <description>Disable UART Rx data overflow detect.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WR_MASK</name>
+              <description>1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_EN</name>
+              <description>UART memory clock gate enable signal.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_RTS</name>
+              <description>This register is used to configure the software rts signal which is used in software flow control.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>Set this bit to reset the uart receive-FIFO.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_RST</name>
+              <description>Set this bit to reset the uart transmit-FIFO.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>Configuration register 1</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00006060</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_THRHD</name>
+              <description>It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_THRHD</name>
+              <description>It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_INV</name>
+              <description>Set this bit to inverse the level value of uart cts signal.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_INV</name>
+              <description>Set this bit to inverse the level value of uart dsr signal.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTS_INV</name>
+              <description>Set this bit to inverse the level value of uart rts signal.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTR_INV</name>
+              <description>Set this bit to inverse the level value of uart dtr signal.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_DTR</name>
+              <description>This register is used to configure the software dtr signal which is used in software flow control.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HWFC_CONF_SYNC</name>
+          <description>Hardware flow-control configuration</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_FLOW_THRHD</name>
+              <description>This register is used to configure the maximum amount of data that can be received  when hardware flow control works.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_EN</name>
+              <description>This is the flow enable bit for UART receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF0</name>
+          <description>UART sleep configure register 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WK_CHAR1</name>
+              <description>This register restores the specified wake up char1 to wake up</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR2</name>
+              <description>This register restores the specified wake up char2 to wake up</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR3</name>
+              <description>This register restores the specified wake up char3 to wake up</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR4</name>
+              <description>This register restores the specified wake up char4 to wake up</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF1</name>
+          <description>UART sleep configure register 1</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WK_CHAR0</name>
+              <description>This register restores the specified char0 to wake up</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF2</name>
+          <description>UART sleep configure register 2</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001420F0</resetValue>
+          <fields>
+            <field>
+              <name>ACTIVE_THRESHOLD</name>
+              <description>The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WAKE_UP_THRHD</name>
+              <description>In wake up mode 1 this field is used to set the received data number threshold to wake up chip.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR_NUM</name>
+              <description>This register is used to select number of wake up char.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR_MASK</name>
+              <description>This register is used to mask  wake up char.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_MODE_SEL</name>
+              <description>This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF0_SYNC</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001311</resetValue>
+          <fields>
+            <field>
+              <name>XON_CHAR</name>
+              <description>This register stores the Xon flow control char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_CHAR</name>
+              <description>This register stores the Xoff flow control char.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XON_XOFF_STILL_SEND</name>
+              <description>In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_FLOW_CON_EN</name>
+              <description>Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XONOFF_DEL</name>
+              <description>Set this bit to remove flow control char from the received data.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XON</name>
+              <description>Set this bit to enable the transmitter to go on sending data.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XOFF</name>
+              <description>Set this bit to stop the  transmitter from sending data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XON</name>
+              <description>Set this bit to send Xon char. It is cleared by hardware automatically.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XOFF</name>
+              <description>Set this bit to send Xoff char. It is cleared by hardware automatically.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF1</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00006000</resetValue>
+          <fields>
+            <field>
+              <name>XON_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1  it will send a Xon char.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1  it will send a Xoff char.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXBRK_CONF_SYNC</name>
+          <description>Tx Break character configuration</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>TX_BRK_NUM</name>
+              <description>This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_CONF_SYNC</name>
+          <description>Frame-end idle configuration</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040100</resetValue>
+          <fields>
+            <field>
+              <name>RX_IDLE_THRHD</name>
+              <description>It will produce frame end signal when receiver takes more time to receive one byte data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between transfers.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RS485_CONF_SYNC</name>
+          <description>RS485 mode configuration</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DL0_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL1_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_PRECNT_SYNC</name>
+          <description>Pre-sequence timing configuration</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>PRE_IDLE_NUM</name>
+              <description>This register is used to configure the idle duration time before the first at_cmd is received by receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_POSTCNT_SYNC</name>
+          <description>Post-sequence timing configuration</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>POST_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between the last at_cmd and the next data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_GAPTOUT_SYNC</name>
+          <description>Timeout configuration</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>RX_GAP_TOUT</name>
+              <description>This register is used to configure the duration time between the at_cmd chars.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_CHAR_SYNC</name>
+          <description>AT escape sequence detection configuration</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000032B</resetValue>
+          <fields>
+            <field>
+              <name>AT_CMD_CHAR</name>
+              <description>This register is used to configure the content of at_cmd char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAR_NUM</name>
+              <description>This register is used to configure the num of continuous at_cmd chars received by receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>UART memory power configuration</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to force power down UART memory.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>Set this bit to force power up UART memory.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUT_CONF_SYNC</name>
+          <description>UART threshold and allocation configuration</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000028</resetValue>
+          <fields>
+            <field>
+              <name>RX_TOUT_EN</name>
+              <description>This is the enble bit for uart receiver's timeout function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_FLOW_DIS</name>
+              <description>Set this bit to stop accumulating idle_cnt when hardware flow control works.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_THRHD</name>
+              <description>This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_TX_STATUS</name>
+          <description>Tx-SRAM write and read offset address.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_SRAM_WADDR</name>
+              <description>This register stores the offset write address in Tx-SRAM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_SRAM_RADDR</name>
+              <description>This register stores the offset read address in Tx-SRAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_RX_STATUS</name>
+          <description>Rx-SRAM write and read offset address.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010080</resetValue>
+          <fields>
+            <field>
+              <name>RX_SRAM_RADDR</name>
+              <description>This register stores the offset read address in RX-SRAM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_SRAM_WADDR</name>
+              <description>This register stores the offset write address in Rx-SRAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_STATUS</name>
+          <description>UART transmit and receive status.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST_URX_OUT</name>
+              <description>This is the status register of receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ST_UTX_OUT</name>
+              <description>This is the status register of transmitter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>UART core clock configuration</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03701000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>The  denominator of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>The numerator of the frequency divider factor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_EN</name>
+              <description>Set this bit to enable UART Tx/Rx clock.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_CORE</name>
+              <description>Write 1 then write 0 to this bit to reset UART Tx/Rx.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SCLK_EN</name>
+              <description>Set this bit to enable UART Tx clock.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SCLK_EN</name>
+              <description>Set this bit to enable UART Rx clock.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit to reset UART Tx.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit to reset UART Rx.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UART Version register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201260</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AFIFO_STATUS</name>
+          <description>UART AFIFO Status</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>TX_AFIFO_FULL</name>
+              <description>Full signal of APB TX AFIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_AFIFO_EMPTY</name>
+              <description>Empty signal of APB TX AFIFO.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_AFIFO_FULL</name>
+              <description>Full signal of APB RX AFIFO.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_AFIFO_EMPTY</name>
+              <description>Empty signal of APB RX AFIFO.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_UPDATE</name>
+          <description>UART Registers Configuration Update register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REG_UPDATE</name>
+              <description>Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ID</name>
+          <description>UART ID register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000500</resetValue>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>This register is used to configure the uart_id.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LP_WDT</name>
+      <description>Peripheral LP_WDT</description>
+      <groupName>LP_WDT</groupName>
+      <baseAddress>0x600B1C00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x38</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CONFIG0</name>
+          <description>need_des</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013214</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CHIP_RESET_WIDTH</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CHIP_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PAUSE_IN_SLP</name>
+              <description>need_des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>need_des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>need_des</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>need_des</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG1</name>
+          <description>need_des</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030D40</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG2</name>
+          <description>need_des</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013880</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG3</name>
+          <description>need_des</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG4</name>
+          <description>need_des</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FEED</name>
+          <description>need_des</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_WDT_FEED</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WPROTECT</name>
+          <description>need_des</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_CONFIG</name>
+          <description>need_des</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x12C00000</resetValue>
+          <fields>
+            <field>
+              <name>SWD_RESET_FLAG</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_AUTO_FEED_EN</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_RST_FLAG_CLR</name>
+              <description>need_des</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_SIGNAL_WIDTH</name>
+              <description>need_des</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_DISABLE</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_FEED</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_WPROTECT</name>
+          <description>need_des</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SWD_WKEY</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>need_des</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SUPER_WDT_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LP_WDT_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>need_des</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SUPER_WDT_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LP_WDT_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>need_des</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SUPER_WDT_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_WDT_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>need_des</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SUPER_WDT_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LP_WDT_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>need_des</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02112080</resetValue>
+          <fields>
+            <field>
+              <name>LP_WDT_DATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MCPWM</name>
+      <description>Peripheral MCPWM</description>
+      <groupName>MCPWM</groupName>
+      <baseAddress>0x60014000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x130</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CLK_CFG</name>
+          <description>PWM clock prescaler register.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_PRESCALE</name>
+              <description>Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_CFG0</name>
+          <description>PWM timer0 period and update method configuration register.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>TIMER0_PRESCALE</name>
+              <description>period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PERIOD</name>
+              <description>period shadow register of PWM timer0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PERIOD_UPMETHOD</name>
+              <description>Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_CFG1</name>
+          <description>PWM timer0 working mode and start/stop control configuration register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_START</name>
+              <description>PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_MOD</name>
+              <description>PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_SYNC</name>
+          <description>PWM timer0 sync function configuration register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_SYNCI_EN</name>
+              <description>When set, timer reloading with phase on sync input event is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW</name>
+              <description>Toggling this bit will trigger a software sync.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_SYNCO_SEL</name>
+              <description>PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PHASE</name>
+              <description>phase for timer reload on sync event</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PHASE_DIRECTION</name>
+              <description>Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_STATUS</name>
+          <description>PWM timer0 status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_VALUE</name>
+              <description>current PWM timer0 counter value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_DIRECTION</name>
+              <description>current PWM timer0 counter direction, 0: increment 1: decrement</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_CFG0</name>
+          <description>PWM timer1 period and update method configuration register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>TIMER1_PRESCALE</name>
+              <description>period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PERIOD</name>
+              <description>period shadow register of PWM timer1</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PERIOD_UPMETHOD</name>
+              <description>Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_CFG1</name>
+          <description>PWM timer1 working mode and start/stop control configuration register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER1_START</name>
+              <description>PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_MOD</name>
+              <description>PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_SYNC</name>
+          <description>PWM timer1 sync function configuration register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER1_SYNCI_EN</name>
+              <description>When set, timer reloading with phase on sync input event is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW</name>
+              <description>Toggling this bit will trigger a software sync.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_SYNCO_SEL</name>
+              <description>PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer1_sync_sw bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PHASE</name>
+              <description>phase for timer reload on sync event</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PHASE_DIRECTION</name>
+              <description>Configure the PWM timer1's direction when timer1 mode is up-down mode: 0-increase,1-decrease</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_STATUS</name>
+          <description>PWM timer1 status register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER1_VALUE</name>
+              <description>current PWM timer1 counter value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_DIRECTION</name>
+              <description>current PWM timer1 counter direction, 0: increment 1: decrement</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_CFG0</name>
+          <description>PWM timer2 period and update method configuration register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>TIMER2_PRESCALE</name>
+              <description>period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PERIOD</name>
+              <description>period shadow register of PWM timer2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PERIOD_UPMETHOD</name>
+              <description>Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_CFG1</name>
+          <description>PWM timer2 working mode and start/stop control configuration register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER2_START</name>
+              <description>PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_MOD</name>
+              <description>PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_SYNC</name>
+          <description>PWM timer2 sync function configuration register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER2_SYNCI_EN</name>
+              <description>When set, timer reloading with phase on sync input event is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW</name>
+              <description>Toggling this bit will trigger a software sync.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_SYNCO_SEL</name>
+              <description>PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PHASE</name>
+              <description>phase for timer reload on sync event</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PHASE_DIRECTION</name>
+              <description>Configure the PWM timer2's direction when timer2 mode is up-down mode: 0-increase,1-decrease</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_STATUS</name>
+          <description>PWM timer2 status register.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER2_VALUE</name>
+              <description>current PWM timer2 counter value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_DIRECTION</name>
+              <description>current PWM timer2 counter direction, 0: increment 1: decrement</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_SYNCI_CFG</name>
+          <description>Synchronization input selection for three PWM timers.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_SYNCISEL</name>
+              <description>select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_SYNCISEL</name>
+              <description>select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_SYNCISEL</name>
+              <description>select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTERNAL_SYNCI0_INVERT</name>
+              <description>invert SYNC0 from GPIO matrix</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTERNAL_SYNCI1_INVERT</name>
+              <description>invert SYNC1 from GPIO matrix</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTERNAL_SYNCI2_INVERT</name>
+              <description>invert SYNC2 from GPIO matrix</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OPERATOR_TIMERSEL</name>
+          <description>Select specific timer for PWM operators.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OPERATOR0_TIMERSEL</name>
+              <description>Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OPERATOR1_TIMERSEL</name>
+              <description>Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OPERATOR2_TIMERSEL</name>
+              <description>Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_STMP_CFG</name>
+          <description>Transfer status and update method for time stamp registers A and B</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR0_A_UPMETHOD</name>
+              <description>Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR0_B_UPMETHOD</name>
+              <description>Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR0_A_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR0_B_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_TSTMP_A</name>
+          <description>Shadow register for register A.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR0_A</name>
+              <description>PWM generator 0 time stamp A's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_TSTMP_B</name>
+          <description>Shadow register for register B.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR0_B</name>
+              <description>PWM generator 0 time stamp B's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_CFG0</name>
+          <description>Fault event T0 and T1 handling</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN0_CFG_UPMETHOD</name>
+              <description>Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_T0_SEL</name>
+              <description>Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_T1_SEL</name>
+              <description>Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_FORCE</name>
+          <description>Permissives to force PWM0A and PWM0B outputs by software</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>GEN0_CNTUFORCE_UPMETHOD</name>
+              <description>Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_A</name>
+          <description>Actions triggered by events on PWM0A</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM0A triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM0A triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM0A triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM0A triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM0A triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM0A triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM0A triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM0A triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM0A triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM0A triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM0A triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_B</name>
+          <description>Actions triggered by events on PWM0B</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM0B triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM0B triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM0B triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM0B triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM0B triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM0B triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM0B triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM0B triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM0B triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM0B triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM0B triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT0_CFG</name>
+          <description>dead time type selection and configuration</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>DB0_FED_UPMETHOD</name>
+              <description>Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when bit3 is set to 1: disable the update</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_RED_UPMETHOD</name>
+              <description>Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when bit3 is set to 1: disable the update</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_DEB_MODE</name>
+              <description>S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_A_OUTSWAP</name>
+              <description>S6 in table</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_B_OUTSWAP</name>
+              <description>S7 in table</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_RED_INSEL</name>
+              <description>S4 in table</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_FED_INSEL</name>
+              <description>S5 in table</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_RED_OUTINVERT</name>
+              <description>S2 in table</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_FED_OUTINVERT</name>
+              <description>S3 in table</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_A_OUTBYPASS</name>
+              <description>S1 in table</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_B_OUTBYPASS</name>
+              <description>S0 in table</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_CLK_SEL</name>
+              <description>Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT0_FED_CFG</name>
+          <description>Shadow register for falling edge delay (FED).</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB0_FED</name>
+              <description>Shadow register for FED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT0_RED_CFG</name>
+          <description>Shadow register for rising edge delay (RED).</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB0_RED</name>
+              <description>Shadow register for RED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CARRIER0_CFG</name>
+          <description>Carrier enable and configuratoin</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHOPPER0_EN</name>
+              <description>When set, carrier0 function is enabled. When cleared, carrier0 is bypassed</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_PRESCALE</name>
+              <description>PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_DUTY</name>
+              <description>carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_OSHTWTH</name>
+              <description>width of the first pulse in number of periods of the carrier</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_OUT_INVERT</name>
+              <description>when set, invert the output of PWM0A and PWM0B for this submodule</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_IN_INVERT</name>
+              <description>when set, invert the input of PWM0A and PWM0B for this submodule</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH0_CFG0</name>
+          <description>Actions on PWM0A and PWM0B trip events</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ0_SW_CBC</name>
+              <description>Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F2_CBC</name>
+              <description>event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F1_CBC</name>
+              <description>event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F0_CBC</name>
+              <description>event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_SW_OST</name>
+              <description>Enable register for software force one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F2_OST</name>
+              <description>event_f2 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F1_OST</name>
+              <description>event_f1 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F0_OST</name>
+              <description>event_f0 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_A_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_A_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_A_OST_D</name>
+              <description>One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_A_OST_U</name>
+              <description>One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_B_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_B_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_B_OST_D</name>
+              <description>One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_B_OST_U</name>
+              <description>One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH0_CFG1</name>
+          <description>Software triggers for fault handler actions</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ0_CLR_OST</name>
+              <description>a rising edge will clear on going one-shot mode action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_CBCPULSE</name>
+              <description>cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_FORCE_CBC</name>
+              <description>a toggle trigger a cycle-by-cycle mode action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_FORCE_OST</name>
+              <description>a toggle (software negate its value) triggers a one-shot mode action</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH0_STATUS</name>
+          <description>Status of fault events.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ0_CBC_ON</name>
+              <description>Set and reset by hardware. If set, a cycle-by-cycle mode action is on going</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_OST_ON</name>
+              <description>Set and reset by hardware. If set, an one-shot mode action is on going</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_STMP_CFG</name>
+          <description>Transfer status and update method for time stamp registers A and B</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR1_A_UPMETHOD</name>
+              <description>Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR1_B_UPMETHOD</name>
+              <description>Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR1_A_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR1_B_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_TSTMP_A</name>
+          <description>Shadow register for register A.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR1_A</name>
+              <description>PWM generator 1 time stamp A's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_TSTMP_B</name>
+          <description>Shadow register for register B.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR1_B</name>
+              <description>PWM generator 1 time stamp B's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_CFG0</name>
+          <description>Fault event T0 and T1 handling</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN1_CFG_UPMETHOD</name>
+              <description>Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_T0_SEL</name>
+              <description>Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_T1_SEL</name>
+              <description>Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_FORCE</name>
+          <description>Permissives to force PWM1A and PWM1B outputs by software</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>GEN1_CNTUFORCE_UPMETHOD</name>
+              <description>Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_A</name>
+          <description>Actions triggered by events on PWM1A</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM1A triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM1A triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM1A triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM1A triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM1A triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM1A triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM1A triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM1A triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM1A triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM1A triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM1A triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_B</name>
+          <description>Actions triggered by events on PWM1B</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM1B triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM1B triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM1B triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM1B triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM1B triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM1B triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM1B triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM1B triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM1B triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM1B triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM1B triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT1_CFG</name>
+          <description>dead time type selection and configuration</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>DB1_FED_UPMETHOD</name>
+              <description>Update method for FED (falling edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when bit3 is set to 1: disable the update</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_RED_UPMETHOD</name>
+              <description>Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when bit3 is set to 1: disable the update</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_DEB_MODE</name>
+              <description>S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_A_OUTSWAP</name>
+              <description>S6 in table</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_B_OUTSWAP</name>
+              <description>S7 in table</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_RED_INSEL</name>
+              <description>S4 in table</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_FED_INSEL</name>
+              <description>S5 in table</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_RED_OUTINVERT</name>
+              <description>S2 in table</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_FED_OUTINVERT</name>
+              <description>S3 in table</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_A_OUTBYPASS</name>
+              <description>S1 in table</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_B_OUTBYPASS</name>
+              <description>S0 in table</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_CLK_SEL</name>
+              <description>Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT1_FED_CFG</name>
+          <description>Shadow register for falling edge delay (FED).</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB1_FED</name>
+              <description>Shadow register for FED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT1_RED_CFG</name>
+          <description>Shadow register for rising edge delay (RED).</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB1_RED</name>
+              <description>Shadow register for RED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CARRIER1_CFG</name>
+          <description>Carrier enable and configuratoin</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHOPPER1_EN</name>
+              <description>When set, carrier1 function is enabled. When cleared, carrier1 is bypassed</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_PRESCALE</name>
+              <description>PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_DUTY</name>
+              <description>carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_OSHTWTH</name>
+              <description>width of the first pulse in number of periods of the carrier</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_OUT_INVERT</name>
+              <description>when set, invert the output of PWM1A and PWM1B for this submodule</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_IN_INVERT</name>
+              <description>when set, invert the input of PWM1A and PWM1B for this submodule</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH1_CFG0</name>
+          <description>Actions on PWM1A and PWM1B trip events</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ1_SW_CBC</name>
+              <description>Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F2_CBC</name>
+              <description>event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F1_CBC</name>
+              <description>event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F0_CBC</name>
+              <description>event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_SW_OST</name>
+              <description>Enable register for software force one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F2_OST</name>
+              <description>event_f2 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F1_OST</name>
+              <description>event_f1 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F0_OST</name>
+              <description>event_f0 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_A_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_A_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_A_OST_D</name>
+              <description>One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing,1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_A_OST_U</name>
+              <description>One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_B_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_B_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_B_OST_D</name>
+              <description>One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_B_OST_U</name>
+              <description>One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH1_CFG1</name>
+          <description>Software triggers for fault handler actions</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ1_CLR_OST</name>
+              <description>a rising edge will clear on going one-shot mode action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_CBCPULSE</name>
+              <description>cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_FORCE_CBC</name>
+              <description>a toggle trigger a cycle-by-cycle mode action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_FORCE_OST</name>
+              <description>a toggle (software negate its value) triggers a one-shot mode action</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH1_STATUS</name>
+          <description>Status of fault events.</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ1_CBC_ON</name>
+              <description>Set and reset by hardware. If set, a cycle-by-cycle mode action is on going</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_OST_ON</name>
+              <description>Set and reset by hardware. If set, an one-shot mode action is on going</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_STMP_CFG</name>
+          <description>Transfer status and update method for time stamp registers A and B</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR2_A_UPMETHOD</name>
+              <description>Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR2_B_UPMETHOD</name>
+              <description>Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR2_A_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR2_B_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_TSTMP_A</name>
+          <description>Shadow register for register A.</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR2_A</name>
+              <description>PWM generator 2 time stamp A's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_TSTMP_B</name>
+          <description>Shadow register for register B.</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR2_B</name>
+              <description>PWM generator 2 time stamp B's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_CFG0</name>
+          <description>Fault event T0 and T1 handling</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN2_CFG_UPMETHOD</name>
+              <description>Update method for PWM generator 2's active register of configuration. 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_T0_SEL</name>
+              <description>Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_T1_SEL</name>
+              <description>Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_FORCE</name>
+          <description>Permissives to force PWM2A and PWM2B outputs by software</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>GEN2_CNTUFORCE_UPMETHOD</name>
+              <description>Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_A</name>
+          <description>Actions triggered by events on PWM2A</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM2A triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM2A triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM2A triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM2A triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM2A triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM2A triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM2A triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM2A triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM2A triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM2A triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM2A triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_B</name>
+          <description>Actions triggered by events on PWM2B</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM2B triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM2B triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM2B triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM2B triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM2B triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM2B triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM2B triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM2B triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM2B triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM2B triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM2B triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT2_CFG</name>
+          <description>dead time type selection and configuration</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>DB2_FED_UPMETHOD</name>
+              <description>Update method for FED (falling edge delay) active register.  0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when bit3 is set to 1: disable the update</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_RED_UPMETHOD</name>
+              <description>Update method for RED (rising edge delay) active register.  0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when bit3 is set to 1: disable the update</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_DEB_MODE</name>
+              <description>S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_A_OUTSWAP</name>
+              <description>S6 in table</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_B_OUTSWAP</name>
+              <description>S7 in table</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_RED_INSEL</name>
+              <description>S4 in table</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_FED_INSEL</name>
+              <description>S5 in table</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_RED_OUTINVERT</name>
+              <description>S2 in table</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_FED_OUTINVERT</name>
+              <description>S3 in table</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_A_OUTBYPASS</name>
+              <description>S1 in table</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_B_OUTBYPASS</name>
+              <description>S0 in table</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_CLK_SEL</name>
+              <description>Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT2_FED_CFG</name>
+          <description>Shadow register for falling edge delay (FED).</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB2_FED</name>
+              <description>Shadow register for FED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DT2_RED_CFG</name>
+          <description>Shadow register for rising edge delay (RED).</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB2_RED</name>
+              <description>Shadow register for RED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CARRIER2_CFG</name>
+          <description>Carrier enable and configuratoin</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHOPPER2_EN</name>
+              <description>When set, carrier2 function is enabled. When cleared, carrier2 is bypassed</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_PRESCALE</name>
+              <description>PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_DUTY</name>
+              <description>carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_OSHTWTH</name>
+              <description>width of the first pulse in number of periods of the carrier</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_OUT_INVERT</name>
+              <description>when set, invert the output of PWM2A and PWM2B for this submodule</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_IN_INVERT</name>
+              <description>when set, invert the input of PWM2A and PWM2B for this submodule</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH2_CFG0</name>
+          <description>Actions on PWM2A and PWM2B trip events</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ2_SW_CBC</name>
+              <description>Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F2_CBC</name>
+              <description>event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F1_CBC</name>
+              <description>event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F0_CBC</name>
+              <description>event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_SW_OST</name>
+              <description>Enable register for software force one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F2_OST</name>
+              <description>event_f2 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F1_OST</name>
+              <description>event_f1 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F0_OST</name>
+              <description>event_f0 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_A_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_A_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_A_OST_D</name>
+              <description>One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_A_OST_U</name>
+              <description>One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_B_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_B_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_B_OST_D</name>
+              <description>One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_B_OST_U</name>
+              <description>One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH2_CFG1</name>
+          <description>Software triggers for fault handler actions</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ2_CLR_OST</name>
+              <description>a rising edge will clear on going one-shot mode action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_CBCPULSE</name>
+              <description>cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_FORCE_CBC</name>
+              <description>a toggle trigger a cycle-by-cycle mode action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_FORCE_OST</name>
+              <description>a toggle (software negate its value) triggers a one-shot mode action</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FH2_STATUS</name>
+          <description>Status of fault events.</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ2_CBC_ON</name>
+              <description>Set and reset by hardware. If set, a cycle-by-cycle mode action is on going</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_OST_ON</name>
+              <description>Set and reset by hardware. If set, an one-shot mode action is on going</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FAULT_DETECT</name>
+          <description>Fault detection configuration and status</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>F0_EN</name>
+              <description>When set, event_f0 generation is enabled</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F1_EN</name>
+              <description>When set, event_f1 generation is enabled</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F2_EN</name>
+              <description>When set, event_f2 generation is enabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F0_POLE</name>
+              <description>Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F1_POLE</name>
+              <description>Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F2_POLE</name>
+              <description>Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVENT_F0</name>
+              <description>Set and reset by hardware. If set, event_f0 is on going</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EVENT_F1</name>
+              <description>Set and reset by hardware. If set, event_f1 is on going</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EVENT_F2</name>
+              <description>Set and reset by hardware. If set, event_f2 is on going</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_TIMER_CFG</name>
+          <description>Configure capture timer</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP_TIMER_EN</name>
+              <description>When set, capture timer incrementing under APB_clk is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP_SYNCI_EN</name>
+              <description>When set, capture timer sync is enabled.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP_SYNCI_SEL</name>
+              <description>capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP_SYNC_SW</name>
+              <description>When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture timer is loaded with value in phase register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_TIMER_PHASE</name>
+          <description>Phase for capture timer sync</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP_PHASE</name>
+              <description>Phase value for capture timer sync operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH0_CFG</name>
+          <description>Capture channel 0 configuration and enable</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP0_EN</name>
+              <description>When set, capture on channel 0 is enabled</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_MODE</name>
+              <description>Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_PRESCALE</name>
+              <description>Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_IN_INVERT</name>
+              <description>when set, CAP0 form GPIO matrix is inverted before prescale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_SW</name>
+              <description>Write 1 will trigger a software forced capture on channel 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH1_CFG</name>
+          <description>Capture channel 1 configuration and enable</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP1_EN</name>
+              <description>When set, capture on channel 2 is enabled</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_MODE</name>
+              <description>Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_PRESCALE</name>
+              <description>Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_IN_INVERT</name>
+              <description>when set, CAP1 form GPIO matrix is inverted before prescale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_SW</name>
+              <description>Write 1 will trigger a software forced capture on channel 1</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH2_CFG</name>
+          <description>Capture channel 2 configuration and enable</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP2_EN</name>
+              <description>When set, capture on channel 2 is enabled</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_MODE</name>
+              <description>Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_PRESCALE</name>
+              <description>Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_IN_INVERT</name>
+              <description>when set, CAP2 form GPIO matrix is inverted before prescale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_SW</name>
+              <description>Write 1 will trigger a software forced capture on channel 2</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH0</name>
+          <description>ch0 capture value status register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP0_VALUE</name>
+              <description>Value of last capture on channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH1</name>
+          <description>ch1 capture value status register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP1_VALUE</name>
+              <description>Value of last capture on channel 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH2</name>
+          <description>ch2 capture value status register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP2_VALUE</name>
+              <description>Value of last capture on channel 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_STATUS</name>
+          <description>Edge of last capture trigger</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP0_EDGE</name>
+              <description>Edge of last capture trigger on channel 0, 0: posedge, 1: negedge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP1_EDGE</name>
+              <description>Edge of last capture trigger on channel 1, 0: posedge, 1: negedge</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP2_EDGE</name>
+              <description>Edge of last capture trigger on channel 2, 0: posedge, 1: negedge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UPDATE_CFG</name>
+          <description>Enable update.</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000055</resetValue>
+          <fields>
+            <field>
+              <name>GLOBAL_UP_EN</name>
+              <description>The global enable of update of all active registers in MCPWM module</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLOBAL_FORCE_UP</name>
+              <description>a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP0_UP_EN</name>
+              <description>When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP0_FORCE_UP</name>
+              <description>a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP1_UP_EN</name>
+              <description>When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP1_FORCE_UP</name>
+              <description>a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP2_UP_EN</name>
+              <description>When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP2_FORCE_UP</name>
+              <description>a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when the timer 0 stops.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when the timer 1 stops.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when the timer 2 stops.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 0 TEP event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 1 TEP event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 2 TEP event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f0 starts.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f1 starts.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f2 starts.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f0 ends.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f1 ends.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f2 ends.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR0_TEA_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 0 TEA event</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR1_TEA_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 1 TEA event</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR2_TEA_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 2 TEA event</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR0_TEB_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 0 TEB event</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR1_TEB_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 1 TEB event</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR2_TEB_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 2 TEB event</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_CBC_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_CBC_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_CBC_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_OST_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a one-shot mode action on PWM0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_OST_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a one-shot mode action on PWM1.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_OST_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a one-shot mode action on PWM2.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by capture on channel 0.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by capture on channel 1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by capture on channel 2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when the timer 0 stops.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when the timer 1 stops.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when the timer 2 stops.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f0 starts.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f1 starts.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f2 starts.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f0 ends.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f1 ends.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f2 ends.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEA_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 0 TEA event</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEA_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 1 TEA event</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEA_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 2 TEA event</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEB_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 0 TEB event</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEB_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 1 TEB event</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEB_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 2 TEB event</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_CBC_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_CBC_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_CBC_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_OST_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_OST_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_OST_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP0_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by capture on channel 0.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP1_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by capture on channel 1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP2_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by capture on channel 2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when the timer 0 stops.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when the timer 1 stops.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when the timer 2 stops.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f0 starts.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f1 starts.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f2 starts.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f0 ends.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f1 ends.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f2 ends.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEA_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 0 TEA event</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEA_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 1 TEA event</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEA_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 2 TEA event</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEB_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 0 TEB event</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEB_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 1 TEB event</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEB_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 2 TEB event</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_CBC_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_CBC_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_CBC_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_OST_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_OST_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_OST_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP0_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by capture on channel 0.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP1_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by capture on channel 1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP2_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by capture on channel 2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when the timer 0 stops.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when the timer 1 stops.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when the timer 2 stops.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f0 starts.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f1 starts.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f2 starts.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f0 ends.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f1 ends.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f2 ends.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEA_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEA_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEA_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEB_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEB_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEB_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ0_CBC_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ1_CBC_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ2_CBC_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ0_OST_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ1_OST_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ2_OST_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAP0_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by capture on channel 0.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAP1_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by capture on channel 1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAP2_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by capture on channel 2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVT_EN</name>
+          <description>MCPWM event enable register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EVT_TIMER0_STOP_EN</name>
+              <description>set this bit high to enable timer0 stop event generate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIMER1_STOP_EN</name>
+              <description>set this bit high to enable timer1 stop event generate</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIMER2_STOP_EN</name>
+              <description>set this bit high to enable timer2 stop event generate</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIMER0_TEZ_EN</name>
+              <description>set this bit high to enable timer0 equal zero event generate</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIMER1_TEZ_EN</name>
+              <description>set this bit high to enable timer1 equal zero event generate</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIMER2_TEZ_EN</name>
+              <description>set this bit high to enable timer2 equal zero event generate</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIMER0_TEP_EN</name>
+              <description>set this bit high to enable timer0 equal period event generate</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIMER1_TEP_EN</name>
+              <description>set this bit high to enable timer1 equal period event generate</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIMER2_TEP_EN</name>
+              <description>set this bit high to enable timer2 equal period event generate</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OP0_TEA_EN</name>
+              <description>set this bit high to enable PWM generator0 timer equal a event generate</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OP1_TEA_EN</name>
+              <description>set this bit high to enable PWM generator1 timer equal a event generate</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OP2_TEA_EN</name>
+              <description>set this bit high to enable PWM generator2 timer equal a event generate</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OP0_TEB_EN</name>
+              <description>set this bit high to enable PWM generator0 timer equal b event generate</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OP1_TEB_EN</name>
+              <description>set this bit high to enable PWM generator1 timer equal b event generate</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OP2_TEB_EN</name>
+              <description>set this bit high to enable PWM generator2 timer equal b event generate</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_F0_EN</name>
+              <description>set this bit high to enable fault0 event generate</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_F1_EN</name>
+              <description>set this bit high to enable fault1 event generate</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_F2_EN</name>
+              <description>set this bit high to enable fault2 event generate</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_F0_CLR_EN</name>
+              <description>set this bit high to enable fault0 clear event generate</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_F1_CLR_EN</name>
+              <description>set this bit high to enable fault1 clear event generate</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_F2_CLR_EN</name>
+              <description>set this bit high to enable fault2 clear event generate</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TZ0_CBC_EN</name>
+              <description>set this bit high to enable cycle by cycle trip0 event generate</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TZ1_CBC_EN</name>
+              <description>set this bit high to enable cycle by cycle trip1 event generate</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TZ2_CBC_EN</name>
+              <description>set this bit high to enable cycle by cycle trip2 event generate</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TZ0_OST_EN</name>
+              <description>set this bit high to enable one shot trip0 event generate</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TZ1_OST_EN</name>
+              <description>set this bit high to enable one shot trip1 event generate</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TZ2_OST_EN</name>
+              <description>set this bit high to enable one shot trip2 event generate</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_CAP0_EN</name>
+              <description>set this bit high to enable capture0 event generate</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_CAP1_EN</name>
+              <description>set this bit high to enable capture1 event generate</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_CAP2_EN</name>
+              <description>set this bit high to enable capture2 event generate</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TASK_EN</name>
+          <description>MCPWM task enable register</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TASK_CMPR0_A_UP_EN</name>
+              <description>set this bit high to enable PWM generator0 timer stamp A's shadow register update task receive</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CMPR1_A_UP_EN</name>
+              <description>set this bit high to enable PWM generator1 timer stamp A's shadow register update task receive</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CMPR2_A_UP_EN</name>
+              <description>set this bit high to enable PWM generator2 timer stamp A's shadow register update task receive</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CMPR0_B_UP_EN</name>
+              <description>set this bit high to enable PWM generator0 timer stamp B's shadow register update task receive</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CMPR1_B_UP_EN</name>
+              <description>set this bit high to enable PWM generator1 timer stamp B's shadow register update task receive</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CMPR2_B_UP_EN</name>
+              <description>set this bit high to enable PWM generator2 timer stamp B's shadow register update task receive</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GEN_STOP_EN</name>
+              <description>set this bit high to enable all PWM generate stop task receive</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER0_SYNC_EN</name>
+              <description>set this bit high to enable timer0 sync task receive</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_SYNC_EN</name>
+              <description>set this bit high to enable timer1 sync task receive</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_SYNC_EN</name>
+              <description>set this bit high to enable timer2 sync task receive</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER0_PERIOD_UP_EN</name>
+              <description>set this bit high to enable timer0 period update task receive</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_PERIOD_UP_EN</name>
+              <description>set this bit high to enable timer1 period update task receive</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_PERIOD_UP_EN</name>
+              <description>set this bit high to enable timer2 period update task receive</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TZ0_OST_EN</name>
+              <description>set this bit high to enable one shot trip0 task receive</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TZ1_OST_EN</name>
+              <description>set this bit high to enable one shot trip1 task receive</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TZ2_OST_EN</name>
+              <description>set this bit high to enable one shot trip2 task receive</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CLR0_OST_EN</name>
+              <description>set this bit high to enable one shot trip0 clear task receive</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CLR1_OST_EN</name>
+              <description>set this bit high to enable one shot trip1 clear task receive</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CLR2_OST_EN</name>
+              <description>set this bit high to enable one shot trip2 clear task receive</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CAP0_EN</name>
+              <description>set this bit high to enable capture0 task receive</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CAP1_EN</name>
+              <description>set this bit high to enable capture1 task receive</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_CAP2_EN</name>
+              <description>set this bit high to enable capture2 task receive</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>MCPWM APB configuration register</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>Force clock on for this register file</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VERSION</name>
+          <description>Version register.</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201240</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version of this register file</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>MEM_MONITOR</name>
+      <description>Peripheral MEM_MONITOR</description>
+      <groupName>MEM_MONITOR</groupName>
+      <baseAddress>0x60092000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x30</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>LOG_SETTING</name>
+          <description>log config regsiter</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>LOG_ENA</name>
+              <description>enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOG_MODE</name>
+              <description>This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: HALFWORD monitor, 4'b1000: BYTE monitor.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOG_MEM_LOOP_ENABLE</name>
+              <description>Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_CHECK_DATA</name>
+          <description>check data regsiter</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_CHECK_DATA</name>
+              <description>The special check data, when write this special data, it will trigger logging.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_DATA_MASK</name>
+          <description>check data mask register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_DATA_MASK</name>
+              <description>byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MIN</name>
+          <description>log boundary regsiter</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MIN</name>
+              <description>the min address of log range</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MAX</name>
+          <description>log boundary regsiter</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MAX</name>
+              <description>the max address of log range</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_START</name>
+          <description>log message store range register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_START</name>
+              <description>the start address of writing logging message</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_END</name>
+          <description>log message store range register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_END</name>
+              <description>the end address of writing logging message</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_CURRENT_ADDR</name>
+          <description>current writing address.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_CURRENT_ADDR</name>
+              <description>means next writing address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_ADDR_UPDATE</name>
+          <description>writing address update</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_ADDR_UPDATE</name>
+              <description>Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_FULL_FLAG</name>
+          <description>full flag status register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_FULL_FLAG</name>
+              <description>1 means memory write loop at least one time at the range of MEM_START and MEM_END</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLR_LOG_MEM_FULL_FLAG</name>
+              <description>Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock gate force on register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set 1 to force on the clk of mem_monitor register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02202140</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>OTP_DEBUG</name>
+      <description>Peripheral OTP_DEBUG</description>
+      <groupName>OTP_DEBUG</groupName>
+      <baseAddress>0x600B3C00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x210</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WR_DIS</name>
+          <description>Otp debuger block0 data register1.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK0_WR_DIS</name>
+              <description>Otp block0 write disable data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP1_W1</name>
+          <description>Otp debuger block0 data register2.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP1_W1</name>
+              <description>Otp block0 backup1 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP1_W2</name>
+          <description>Otp debuger block0 data register3.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP1_W2</name>
+              <description>Otp block0 backup1 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP1_W3</name>
+          <description>Otp debuger block0 data register4.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP1_W3</name>
+              <description>Otp block0 backup1 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP1_W4</name>
+          <description>Otp debuger block0 data register5.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP1_W4</name>
+              <description>Otp block0 backup1 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP1_W5</name>
+          <description>Otp debuger block0 data register6.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP1_W5</name>
+              <description>Otp block0 backup1 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP2_W1</name>
+          <description>Otp debuger block0 data register7.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP2_W1</name>
+              <description>Otp block0 backup2 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP2_W2</name>
+          <description>Otp debuger block0 data register8.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP2_W2</name>
+              <description>Otp block0 backup2 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP2_W3</name>
+          <description>Otp debuger block0 data register9.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP2_W3</name>
+              <description>Otp block0 backup2 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP2_W4</name>
+          <description>Otp debuger block0 data register10.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP2_W4</name>
+              <description>Otp block0 backup2 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP2_W5</name>
+          <description>Otp debuger block0 data register11.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP2_W5</name>
+              <description>Otp block0 backup2 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP3_W1</name>
+          <description>Otp debuger block0 data register12.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP3_W1</name>
+              <description>Otp block0 backup3 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP3_W2</name>
+          <description>Otp debuger block0 data register13.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP3_W2</name>
+              <description>Otp block0 backup3 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP3_W3</name>
+          <description>Otp debuger block0 data register14.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP3_W3</name>
+              <description>Otp block0 backup3 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP3_W4</name>
+          <description>Otp debuger block0 data register15.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP3_W4</name>
+              <description>Otp block0 backup3 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP3_W5</name>
+          <description>Otp debuger block0 data register16.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP3_W5</name>
+              <description>Otp block0 backup3 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP4_W1</name>
+          <description>Otp debuger block0 data register17.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP4_W1</name>
+              <description>Otp block0 backup4 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP4_W2</name>
+          <description>Otp debuger block0 data register18.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP4_W2</name>
+              <description>Otp block0 backup4 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP4_W3</name>
+          <description>Otp debuger block0 data register19.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP4_W3</name>
+              <description>Otp block0 backup4 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP4_W4</name>
+          <description>Otp debuger block0 data register20.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP4_W4</name>
+              <description>Otp block0 backup4 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK0_BACKUP4_W5</name>
+          <description>Otp debuger block0 data register21.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OTP_BEBUG_BLOCK0_BACKUP4_W5</name>
+              <description>Otp block0 backup4 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_W1</name>
+          <description>Otp debuger block1 data register1.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK1_W1</name>
+              <description>Otp block1  word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_W2</name>
+          <description>Otp debuger block1 data register2.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK1_W2</name>
+              <description>Otp block1  word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_W3</name>
+          <description>Otp debuger block1 data register3.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK1_W3</name>
+              <description>Otp block1  word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_W4</name>
+          <description>Otp debuger block1 data register4.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK1_W4</name>
+              <description>Otp block1  word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_W5</name>
+          <description>Otp debuger block1 data register5.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK1_W5</name>
+              <description>Otp block1  word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_W6</name>
+          <description>Otp debuger block1 data register6.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK1_W6</name>
+              <description>Otp block1  word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_W7</name>
+          <description>Otp debuger block1 data register7.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK1_W7</name>
+              <description>Otp block1  word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_W8</name>
+          <description>Otp debuger block1 data register8.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK1_W8</name>
+              <description>Otp block1  word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK1_W9</name>
+          <description>Otp debuger block1 data register9.</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK1_W9</name>
+              <description>Otp block1  word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W1</name>
+          <description>Otp debuger block2 data register1.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W1</name>
+              <description>Otp block2 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W2</name>
+          <description>Otp debuger block2 data register2.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W2</name>
+              <description>Otp block2 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W3</name>
+          <description>Otp debuger block2 data register3.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W3</name>
+              <description>Otp block2 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W4</name>
+          <description>Otp debuger block2 data register4.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W4</name>
+              <description>Otp block2 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W5</name>
+          <description>Otp debuger block2 data register5.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W5</name>
+              <description>Otp block2 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W6</name>
+          <description>Otp debuger block2 data register6.</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W6</name>
+              <description>Otp block2 word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W7</name>
+          <description>Otp debuger block2 data register7.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W7</name>
+              <description>Otp block2 word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W8</name>
+          <description>Otp debuger block2 data register8.</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W8</name>
+              <description>Otp block2 word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W9</name>
+          <description>Otp debuger block2 data register9.</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W9</name>
+              <description>Otp block2 word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W10</name>
+          <description>Otp debuger block2 data register10.</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W10</name>
+              <description>Otp block2 word10 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK2_W11</name>
+          <description>Otp debuger block2 data register11.</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK2_W11</name>
+              <description>Otp block2 word11 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W1</name>
+          <description>Otp debuger block3 data register1.</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W1</name>
+              <description>Otp block3 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W2</name>
+          <description>Otp debuger block3 data register2.</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W2</name>
+              <description>Otp block3 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W3</name>
+          <description>Otp debuger block3 data register3.</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W3</name>
+              <description>Otp block3 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W4</name>
+          <description>Otp debuger block3 data register4.</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W4</name>
+              <description>Otp block3 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W5</name>
+          <description>Otp debuger block3 data register5.</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W5</name>
+              <description>Otp block3 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W6</name>
+          <description>Otp debuger block3 data register6.</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W6</name>
+              <description>Otp block3 word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W7</name>
+          <description>Otp debuger block3 data register7.</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W7</name>
+              <description>Otp block3 word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W8</name>
+          <description>Otp debuger block3 data register8.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W8</name>
+              <description>Otp block3 word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W9</name>
+          <description>Otp debuger block3 data register9.</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W9</name>
+              <description>Otp block3 word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W10</name>
+          <description>Otp debuger block3 data register10.</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W10</name>
+              <description>Otp block3 word10 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK3_W11</name>
+          <description>Otp debuger block3 data register11.</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK3_W11</name>
+              <description>Otp block3 word11 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W1</name>
+          <description>Otp debuger block4 data register1.</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W1</name>
+              <description>Otp block4 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W2</name>
+          <description>Otp debuger block4 data register2.</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W2</name>
+              <description>Otp block4 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W3</name>
+          <description>Otp debuger block4 data register3.</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W3</name>
+              <description>Otp block4 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W4</name>
+          <description>Otp debuger block4 data register4.</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W4</name>
+              <description>Otp block4 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W5</name>
+          <description>Otp debuger block4 data register5.</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W5</name>
+              <description>Otp block4 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W6</name>
+          <description>Otp debuger block4 data register6.</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W6</name>
+              <description>Otp block4 word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W7</name>
+          <description>Otp debuger block4 data register7.</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W7</name>
+              <description>Otp block4 word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W8</name>
+          <description>Otp debuger block4 data register8.</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W8</name>
+              <description>Otp block4 word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W9</name>
+          <description>Otp debuger block4 data register9.</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W9</name>
+              <description>Otp block4 word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W10</name>
+          <description>Otp debuger block4 data registe10.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W10</name>
+              <description>Otp block4 word10 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK4_W11</name>
+          <description>Otp debuger block4 data register11.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK4_W11</name>
+              <description>Otp block4 word11 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W1</name>
+          <description>Otp debuger block5 data register1.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W1</name>
+              <description>Otp block5 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W2</name>
+          <description>Otp debuger block5 data register2.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W2</name>
+              <description>Otp block5 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W3</name>
+          <description>Otp debuger block5 data register3.</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W3</name>
+              <description>Otp block5 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W4</name>
+          <description>Otp debuger block5 data register4.</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W4</name>
+              <description>Otp block5 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W5</name>
+          <description>Otp debuger block5 data register5.</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W5</name>
+              <description>Otp block5 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W6</name>
+          <description>Otp debuger block5 data register6.</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W6</name>
+              <description>Otp block5 word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W7</name>
+          <description>Otp debuger block5 data register7.</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W7</name>
+              <description>Otp block5 word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W8</name>
+          <description>Otp debuger block5 data register8.</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W8</name>
+              <description>Otp block5 word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W9</name>
+          <description>Otp debuger block5 data register9.</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W9</name>
+              <description>Otp block5 word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W10</name>
+          <description>Otp debuger block5 data register10.</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W10</name>
+              <description>Otp block5 word10 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK5_W11</name>
+          <description>Otp debuger block5 data register11.</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK5_W11</name>
+              <description>Otp block5 word11 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W1</name>
+          <description>Otp debuger block6 data register1.</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W1</name>
+              <description>Otp block6 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W2</name>
+          <description>Otp debuger block6 data register2.</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W2</name>
+              <description>Otp block6 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W3</name>
+          <description>Otp debuger block6 data register3.</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W3</name>
+              <description>Otp block6 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W4</name>
+          <description>Otp debuger block6 data register4.</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W4</name>
+              <description>Otp block6 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W5</name>
+          <description>Otp debuger block6 data register5.</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W5</name>
+              <description>Otp block6 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W6</name>
+          <description>Otp debuger block6 data register6.</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W6</name>
+              <description>Otp block6 word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W7</name>
+          <description>Otp debuger block6 data register7.</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W7</name>
+              <description>Otp block6 word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W8</name>
+          <description>Otp debuger block6 data register8.</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W8</name>
+              <description>Otp block6 word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W9</name>
+          <description>Otp debuger block6 data register9.</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W9</name>
+              <description>Otp block6 word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W10</name>
+          <description>Otp debuger block6 data register10.</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W10</name>
+              <description>Otp block6 word10 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK6_W11</name>
+          <description>Otp debuger block6 data register11.</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK6_W11</name>
+              <description>Otp block6 word11 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W1</name>
+          <description>Otp debuger block7 data register1.</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W1</name>
+              <description>Otp block7 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W2</name>
+          <description>Otp debuger block7 data register2.</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W2</name>
+              <description>Otp block7 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W3</name>
+          <description>Otp debuger block7 data register3.</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W3</name>
+              <description>Otp block7 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W4</name>
+          <description>Otp debuger block7 data register4.</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W4</name>
+              <description>Otp block7 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W5</name>
+          <description>Otp debuger block7 data register5.</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W5</name>
+              <description>Otp block7 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W6</name>
+          <description>Otp debuger block7 data register6.</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W6</name>
+              <description>Otp block7 word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W7</name>
+          <description>Otp debuger block7 data register7.</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W7</name>
+              <description>Otp block7 word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W8</name>
+          <description>Otp debuger block7 data register8.</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W8</name>
+              <description>Otp block7 word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W9</name>
+          <description>Otp debuger block7 data register9.</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W9</name>
+              <description>Otp block7 word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W10</name>
+          <description>Otp debuger block7 data register10.</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W10</name>
+              <description>Otp block7 word10 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK7_W11</name>
+          <description>Otp debuger block7 data register11.</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK7_W11</name>
+              <description>Otp block7 word11 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W1</name>
+          <description>Otp debuger block8 data register1.</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W1</name>
+              <description>Otp block8 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W2</name>
+          <description>Otp debuger block8 data register2.</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W2</name>
+              <description>Otp block8 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W3</name>
+          <description>Otp debuger block8 data register3.</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W3</name>
+              <description>Otp block8 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W4</name>
+          <description>Otp debuger block8 data register4.</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W4</name>
+              <description>Otp block8 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W5</name>
+          <description>Otp debuger block8 data register5.</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W5</name>
+              <description>Otp block8 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W6</name>
+          <description>Otp debuger block8 data register6.</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W6</name>
+              <description>Otp block8 word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W7</name>
+          <description>Otp debuger block8 data register7.</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W7</name>
+              <description>Otp block8 word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W8</name>
+          <description>Otp debuger block8 data register8.</description>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W8</name>
+              <description>Otp block8 word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W9</name>
+          <description>Otp debuger block8 data register9.</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W9</name>
+              <description>Otp block8 word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W10</name>
+          <description>Otp debuger block8 data register10.</description>
+          <addressOffset>0x1A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W10</name>
+              <description>Otp block8 word10 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK8_W11</name>
+          <description>Otp debuger block8 data register11.</description>
+          <addressOffset>0x1A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK8_W11</name>
+              <description>Otp block8 word11 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W1</name>
+          <description>Otp debuger block9 data register1.</description>
+          <addressOffset>0x1AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W1</name>
+              <description>Otp block9 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W2</name>
+          <description>Otp debuger block9 data register2.</description>
+          <addressOffset>0x1B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W2</name>
+              <description>Otp block9 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W3</name>
+          <description>Otp debuger block9 data register3.</description>
+          <addressOffset>0x1B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W3</name>
+              <description>Otp block9 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W4</name>
+          <description>Otp debuger block9 data register4.</description>
+          <addressOffset>0x1B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W4</name>
+              <description>Otp block9 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W5</name>
+          <description>Otp debuger block9 data register5.</description>
+          <addressOffset>0x1BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W5</name>
+              <description>Otp block9 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W6</name>
+          <description>Otp debuger block9 data register6.</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W6</name>
+              <description>Otp block9 word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W7</name>
+          <description>Otp debuger block9 data register7.</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W7</name>
+              <description>Otp block9 word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W8</name>
+          <description>Otp debuger block9 data register8.</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W8</name>
+              <description>Otp block9 word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W9</name>
+          <description>Otp debuger block9 data register9.</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W9</name>
+              <description>Otp block9 word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W10</name>
+          <description>Otp debuger block9 data register10.</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W10</name>
+              <description>Otp block9 word10 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK9_W11</name>
+          <description>Otp debuger block9 data register11.</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK9_W11</name>
+              <description>Otp block9 word11 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W1</name>
+          <description>Otp debuger block10 data register1.</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W1</name>
+              <description>Otp block10 word1 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W2</name>
+          <description>Otp debuger block10 data register2.</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W2</name>
+              <description>Otp block10 word2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W3</name>
+          <description>Otp debuger block10 data register3.</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W3</name>
+              <description>Otp block10 word3 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W4</name>
+          <description>Otp debuger block10 data register4.</description>
+          <addressOffset>0x1E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W4</name>
+              <description>Otp block10 word4 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W5</name>
+          <description>Otp debuger block10 data register5.</description>
+          <addressOffset>0x1E8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W5</name>
+              <description>Otp block10 word5 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W6</name>
+          <description>Otp debuger block10 data register6.</description>
+          <addressOffset>0x1EC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W6</name>
+              <description>Otp block10 word6 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W7</name>
+          <description>Otp debuger block10 data register7.</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W7</name>
+              <description>Otp block10 word7 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W8</name>
+          <description>Otp debuger block10 data register8.</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W8</name>
+              <description>Otp block10 word8 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W9</name>
+          <description>Otp debuger block10 data register9.</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W9</name>
+              <description>Otp block10 word9 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W10</name>
+          <description>Otp debuger block10 data register10.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK19_W10</name>
+              <description>Otp block10 word10 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLK10_W11</name>
+          <description>Otp debuger block10 data register11.</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK10_W11</name>
+              <description>Otp block10 word11 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>Otp debuger clk_en configuration register.</description>
+          <addressOffset>0x204</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>Force clock on for this register file.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB2OTP_EN</name>
+          <description>Otp_debuger apb2otp enable configuration register.</description>
+          <addressOffset>0x208</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB2OTP_EN</name>
+              <description>Debug mode enable signal.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>eFuse version register.</description>
+          <addressOffset>0x20C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20211028</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Stores otp_debug version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PARL_IO</name>
+      <description>Peripheral PARL_IO</description>
+      <groupName>PARL_IO</groupName>
+      <baseAddress>0x60015000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x2C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PARL_IO</name>
+        <value>63</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>RX_CFG0</name>
+          <description>Parallel RX module configuration register0.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_EOF_GEN_SEL</name>
+              <description>Write 0 to select eof generated manchnism by configured data byte length. Write 1 to select eof generated manchnism by external enable signal.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_START</name>
+              <description>Write 1 to start rx global data sampling.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DATA_BYTELEN</name>
+              <description>Configures rx receieved data byte length.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SW_EN</name>
+              <description>Write 1 to enable software data sampling.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PULSE_SUBMODE_SEL</name>
+              <description>Pulse submode selection.
+0000: positive pulse start(data bit included) &amp;&amp;  positive pulse end(data bit included)
+0001: positive pulse start(data bit included) &amp;&amp; positive pulse end (data bit excluded)
+0010: positive pulse start(data bit excluded) &amp;&amp; positive pulse end (data bit included)
+0011: positive pulse start(data bit excluded) &amp;&amp; positive pulse end (data bit excluded)
+0100: positive pulse start(data bit included) &amp;&amp; length end
+0101: positive pulse start(data bit excluded) &amp;&amp; length end
+0110: negative pulse start(data bit included) &amp;&amp;  negative pulse end(data bit included)
+0111: negative pulse start(data bit included) &amp;&amp; negative pulse end (data bit excluded)
+1000: negative pulse start(data bit excluded) &amp;&amp; negative pulse end (data bit included)
+1001: negative pulse start(data bit excluded) &amp;&amp; negative pulse end (data bit excluded)
+1010: negative pulse start(data bit included) &amp;&amp; length end
+1011: negative pulse start(data bit excluded) &amp;&amp; length end</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LEVEL_SUBMODE_SEL</name>
+              <description>Write 0 to sample data at high level of external enable signal. Write 1 to sample data at low level of external enable signal.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SMP_MODE_SEL</name>
+              <description>Rx data sampling mode selection.
+000: external level enable mode
+001: external pulse enable mode
+010: internal software enable mode</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLK_EDGE_SEL</name>
+              <description>Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable sampling data on the falling edge of rx clock.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIT_PACK_ORDER</name>
+              <description>Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to pack bits into 1byte from LSB when data bus width is 4/2/1 bits.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BUS_WID_SEL</name>
+              <description>Rx data bus width selection.
+100: bus width is 1 bit
+011: bus width is 2 bits
+010: bus width is 4 bits
+001: bus width is 8 bits
+000: bus width is 16 bits</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_SRST</name>
+              <description>Write 1 to enable soft reset of async fifo in rx module.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CFG1</name>
+          <description>Parallel RX module configuration register1.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0FFFF008</resetValue>
+          <fields>
+            <field>
+              <name>RX_REG_UPDATE</name>
+              <description>Write 1 to update rx register configuration signals.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_TIMEOUT_EN</name>
+              <description>Write 1 to enable timeout count to generate error eof.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_EXT_EN_SEL</name>
+              <description>Configures rx external enable signal selection from 16 data lines.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TIMEOUT_THRESHOLD</name>
+              <description>Configures rx threshold of timeout counter.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CFG0</name>
+          <description>Parallel TX module configuration register0.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTELEN</name>
+              <description>Configures tx sending data byte length.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_GATING_EN</name>
+              <description>Write 1 to enable output tx clock gating.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_START</name>
+              <description>Write 1 to start tx global data output.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HW_VALID_EN</name>
+              <description>Write 1 to enable tx hardware data valid signal.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SMP_EDGE_SEL</name>
+              <description>Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable sampling data on the falling edge of tx clock.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIT_UNPACK_ORDER</name>
+              <description>Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BUS_WID_SEL</name>
+              <description>Tx data bus width selection.
+100: bus width is 1 bit
+011: bus width is 2 bits
+010: bus width is 4 bits
+001: bus width is 8 bits
+000: bus width is 16 bits</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_SRST</name>
+              <description>Write 1 to enable soft reset of async fifo in tx module.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CFG1</name>
+          <description>Parallel TX module configuration register1.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_IDLE_VALUE</name>
+              <description>Configures data value on tx bus when IDLE state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ST</name>
+          <description>Parallel IO module status register0.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_READY</name>
+              <description>Represents the status that tx is ready.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Parallel IO interrupt enable singal configuration register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_FIFO_REMPTY_INT_ENA</name>
+              <description>Write 1 to enable TX_FIFO_REMPTY_INTR.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_WFULL_INT_ENA</name>
+              <description>Write 1 to enable RX_FIFO_WFULL_INTR.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_EOF_INT_ENA</name>
+              <description>Write 1 to enable TX_EOF_INTR.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Parallel IO interrupt raw singal status register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_FIFO_REMPTY_INT_RAW</name>
+              <description>The raw interrupt status of TX_FIFO_REMPTY_INTR.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_WFULL_INT_RAW</name>
+              <description>The raw interrupt status of RX_FIFO_WFULL_INTR.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_EOF_INT_RAW</name>
+              <description>The raw interrupt status of TX_EOF_INTR.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Parallel IO interrupt singal status register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_FIFO_REMPTY_INT_ST</name>
+              <description>The masked interrupt status of TX_FIFO_REMPTY_INTR.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_WFULL_INT_ST</name>
+              <description>The masked interrupt status of RX_FIFO_WFULL_INTR.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_EOF_INT_ST</name>
+              <description>The masked interrupt status of TX_EOF_INTR.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Parallel IO interrupt  clear singal configuration register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_FIFO_REMPTY_INT_CLR</name>
+              <description>Write 1 to clear TX_FIFO_REMPTY_INTR.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_WFULL_INT_CLR</name>
+              <description>Write 1 to clear RX_FIFO_WFULL_INTR.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_EOF_INT_CLR</name>
+              <description>Write 1 to clear TX_EOF_INTR.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>Parallel IO clk configuration register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>Force clock on for this register file</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VERSION</name>
+          <description>Version register.</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02202240</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version of this register file</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PAU</name>
+      <description>Peripheral PAU</description>
+      <groupName>PAU</groupName>
+      <baseAddress>0x60093000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PAU</name>
+        <value>32</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>REGDMA_CONF</name>
+          <description>Peri backup control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FLOW_ERR</name>
+              <description>backup error type</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>backup start signal</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TO_MEM</name>
+              <description>backup direction(reg to mem / mem to reg)</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LINK_SEL</name>
+              <description>Link select</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START_MAC</name>
+              <description>mac sw backup start signal</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TO_MEM_MAC</name>
+              <description>mac sw backup direction(reg to mem / mem to reg)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL_MAC</name>
+              <description>mac hw/sw select</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_CLK_CONF</name>
+          <description>Clock control register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>clock enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_ETM_CTRL</name>
+          <description>ETM start ctrl reg</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ETM_START_0</name>
+              <description>etm_start_0 reg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ETM_START_1</name>
+              <description>etm_start_1 reg</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ETM_START_2</name>
+              <description>etm_start_2 reg</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ETM_START_3</name>
+              <description>etm_start_3 reg</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_LINK_0_ADDR</name>
+          <description>link_0_addr</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINK_ADDR_0</name>
+              <description>link_0_addr reg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_LINK_1_ADDR</name>
+          <description>Link_1_addr</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINK_ADDR_1</name>
+              <description>Link_1_addr reg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_LINK_2_ADDR</name>
+          <description>Link_2_addr</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINK_ADDR_2</name>
+              <description>Link_2_addr reg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_LINK_3_ADDR</name>
+          <description>Link_3_addr</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINK_ADDR_3</name>
+              <description>Link_3_addr reg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_LINK_MAC_ADDR</name>
+          <description>Link_mac_addr</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINK_ADDR_MAC</name>
+              <description>Link_mac_addr reg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_CURRENT_LINK_ADDR</name>
+          <description>current link addr</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CURRENT_LINK_ADDR</name>
+              <description>current link addr reg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_BACKUP_ADDR</name>
+          <description>Backup addr</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_ADDR</name>
+              <description>backup addr reg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_MEM_ADDR</name>
+          <description>mem addr</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_ADDR</name>
+              <description>mem addr reg</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_BKP_CONF</name>
+          <description>backup config</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7D101920</resetValue>
+          <fields>
+            <field>
+              <name>READ_INTERVAL</name>
+              <description>Link read_interval</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LINK_TOUT_THRES</name>
+              <description>link wait timeout threshold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BURST_LIMIT</name>
+              <description>burst limit</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_TOUT_THRES</name>
+              <description>Backup timeout threshold</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_LINK_BASE</name>
+          <description>retention dma link base</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINK_BASE_ADDR</name>
+              <description>retention dma link base</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CFG</name>
+          <description>retention_cfg</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>RET_INV_CFG</name>
+              <description>retention inv scan out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Read only register for error and done</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DONE_INT_ENA</name>
+              <description>backup done flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERROR_INT_ENA</name>
+              <description>error flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Read only register for error and done</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DONE_INT_RAW</name>
+              <description>backup done flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR_INT_RAW</name>
+              <description>error flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Read only register for error and done</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DONE_INT_CLR</name>
+              <description>backup done flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ERROR_INT_CLR</name>
+              <description>error flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Read only register for error and done</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DONE_INT_ST</name>
+              <description>backup done flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERROR_INT_ST</name>
+              <description>error flag</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02203070</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>REGDMA date information/ REGDMA version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PCNT</name>
+      <description>Pulse Counter</description>
+      <groupName>PCNT</groupName>
+      <baseAddress>0x60012000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PCNT</name>
+        <value>62</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF0</name>
+          <description>Configuration register 0 for unit %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U</name>
+              <description>This sets the maximum threshold, in APB_CLK cycles, for the filter.
+
+Any pulses with width less than this will be ignored when the filter is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U</name>
+              <description>This is the enable bit for unit %s's input filter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U</name>
+              <description>This is the enable bit for unit %s's zero comparator.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U</name>
+              <description>This is the enable bit for unit %s's thr_h_lim comparator.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U</name>
+              <description>This is the enable bit for unit %s's thr_l_lim comparator.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U</name>
+              <description>This is the enable bit for unit %s's thres0 comparator.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U</name>
+              <description>This is the enable bit for unit %s's thres1 comparator.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 0 detects a negative edge.
+
+1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 0 detects a positive edge.
+
+1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.
+
+0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.
+
+0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 1 detects a negative edge.
+
+1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 1 detects a positive edge.
+
+1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.
+
+0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.
+
+0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF1</name>
+          <description>Configuration register 1 for unit %s</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U</name>
+              <description>This register is used to configure the thres0 value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U</name>
+              <description>This register is used to configure the thres1 value for unit %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF2</name>
+          <description>Configuration register 2 for unit %s</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U</name>
+              <description>This register is used to configure the thr_h_lim value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U</name>
+              <description>This register is used to configure the thr_l_lim value for unit %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>U%s_CNT</name>
+          <description>Counter value for unit %s</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PULSE_CNT_U</name>
+              <description>This register stores the current pulse count value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt raw status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Interrupt status register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>U%s_STATUS</name>
+          <description>PNCT UNIT%s status register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_ZERO_MODE_U</name>
+              <description>The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_THRES1_LAT_U</name>
+              <description>The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_THRES0_LAT_U</name>
+              <description>The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_L_LIM_LAT_U</name>
+              <description>The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_H_LIM_LAT_U</name>
+              <description>The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_ZERO_LAT_U</name>
+              <description>The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>Control register for all counters</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PULSE_CNT_RST_U0</name>
+              <description>Set this bit to clear unit 0's counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U0</name>
+              <description>Set this bit to freeze unit 0's counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U1</name>
+              <description>Set this bit to clear unit 1's counter.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U1</name>
+              <description>Set this bit to freeze unit 1's counter.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U2</name>
+              <description>Set this bit to clear unit 2's counter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U2</name>
+              <description>Set this bit to freeze unit 2's counter.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U3</name>
+              <description>Set this bit to clear unit 3's counter.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U3</name>
+              <description>Set this bit to freeze unit 3's counter.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>PCNT version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19072601</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the PCNT version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PCR</name>
+      <description>Peripheral PCR</description>
+      <groupName>PCR</groupName>
+      <baseAddress>0x60096000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x14C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>UART0_CONF</name>
+          <description>UART0 configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>UART0_CLK_EN</name>
+              <description>Set 1 to enable uart0 apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_RST_EN</name>
+              <description>Set 0 to reset uart0 module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART0_SCLK_CONF</name>
+          <description>UART0_SCLK configuration register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00700000</resetValue>
+          <fields>
+            <field>
+              <name>UART0_SCLK_DIV_A</name>
+              <description>The  denominator of the frequency divider factor of the uart0 function clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_SCLK_DIV_B</name>
+              <description>The numerator of the frequency divider factor of the uart0 function clock.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_SCLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor of the uart0 function clock.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_SCLK_SEL</name>
+              <description>set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_SCLK_EN</name>
+              <description>Set 1 to enable uart0 function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART0_PD_CTRL</name>
+          <description>UART0 power control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>UART0_MEM_FORCE_PU</name>
+              <description>Set this bit to force power down UART0 memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_MEM_FORCE_PD</name>
+              <description>Set this bit to force power up UART0 memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART1_CONF</name>
+          <description>UART1 configuration register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>UART1_CLK_EN</name>
+              <description>Set 1 to enable uart1 apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_RST_EN</name>
+              <description>Set 0 to reset uart1 module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART1_SCLK_CONF</name>
+          <description>UART1_SCLK configuration register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00700000</resetValue>
+          <fields>
+            <field>
+              <name>UART1_SCLK_DIV_A</name>
+              <description>The  denominator of the frequency divider factor of the uart1 function clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_SCLK_DIV_B</name>
+              <description>The numerator of the frequency divider factor of the uart1 function clock.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_SCLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor of the uart1 function clock.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_SCLK_SEL</name>
+              <description>set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_SCLK_EN</name>
+              <description>Set 1 to enable uart0 function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART1_PD_CTRL</name>
+          <description>UART1 power control register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>UART1_MEM_FORCE_PU</name>
+              <description>Set this bit to force power down UART1 memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_MEM_FORCE_PD</name>
+              <description>Set this bit to force power up UART1 memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MSPI_CONF</name>
+          <description>MSPI configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>MSPI_CLK_EN</name>
+              <description>Set 1 to enable mspi clock, include mspi pll clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MSPI_RST_EN</name>
+              <description>Set 0 to reset mspi module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MSPI_PLL_CLK_EN</name>
+              <description>Set 1 to enable mspi pll clock</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MSPI_CLK_CONF</name>
+          <description>MSPI_CLK configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000300</resetValue>
+          <fields>
+            <field>
+              <name>MSPI_FAST_LS_DIV_NUM</name>
+              <description>Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a low-speed clock-source such as XTAL/FOSC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MSPI_FAST_HS_DIV_NUM</name>
+              <description>Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a high-speed clock-source such as SPLL.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_CONF</name>
+          <description>I2C configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>I2C_CLK_EN</name>
+              <description>Set 1 to enable i2c apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RST_EN</name>
+              <description>Set 0 to reset i2c module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_SCLK_CONF</name>
+          <description>I2C_SCLK configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>I2C_SCLK_DIV_A</name>
+              <description>The  denominator of the frequency divider factor of the i2c function clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCLK_DIV_B</name>
+              <description>The numerator of the frequency divider factor of the i2c function clock.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor of the i2c function clock.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: FOSC.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SCLK_EN</name>
+              <description>Set 1 to enable i2c function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UHCI_CONF</name>
+          <description>UHCI configuration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>UHCI_CLK_EN</name>
+              <description>Set 1 to enable uhci clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI_RST_EN</name>
+              <description>Set 0 to reset uhci module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RMT_CONF</name>
+          <description>RMT configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RMT_CLK_EN</name>
+              <description>Set 1 to enable rmt apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_RST_EN</name>
+              <description>Set 0 to reset rmt module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RMT_SCLK_CONF</name>
+          <description>RMT_SCLK configuration register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00501000</resetValue>
+          <fields>
+            <field>
+              <name>RMT_SCLK_DIV_A</name>
+              <description>The  denominator of the frequency divider factor of the rmt function clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_DIV_B</name>
+              <description>The numerator of the frequency divider factor of the rmt function clock.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor of the rmt function clock.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_SEL</name>
+              <description>set this field to select clock-source. 0: do not select anyone clock, 1(default): 80MHz, 2: FOSC, 3: XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_EN</name>
+              <description>Set 1 to enable rmt function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LEDC_CONF</name>
+          <description>LEDC configuration register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>LEDC_CLK_EN</name>
+              <description>Set 1 to enable ledc apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_RST_EN</name>
+              <description>Set 0 to reset ledc module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LEDC_SCLK_CONF</name>
+          <description>LEDC_SCLK configuration register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>LEDC_SCLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): do not select anyone clock, 1: 80MHz, 2: FOSC, 3: XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_SCLK_EN</name>
+              <description>Set 1 to enable ledc function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMERGROUP0_CONF</name>
+          <description>TIMERGROUP0 configuration register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TG0_CLK_EN</name>
+              <description>Set 1 to enable timer_group0 apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TG0_RST_EN</name>
+              <description>Set 0 to reset timer_group0 module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMERGROUP0_TIMER_CLK_CONF</name>
+          <description>TIMERGROUP0_TIMER_CLK configuration register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>TG0_TIMER_CLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TG0_TIMER_CLK_EN</name>
+              <description>Set 1 to enable timer_group0 timer clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMERGROUP0_WDT_CLK_CONF</name>
+          <description>TIMERGROUP0_WDT_CLK configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>TG0_WDT_CLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TG0_WDT_CLK_EN</name>
+              <description>Set 1 to enable timer_group0 wdt clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMERGROUP1_CONF</name>
+          <description>TIMERGROUP1 configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TG1_CLK_EN</name>
+              <description>Set 1 to enable timer_group1 apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TG1_RST_EN</name>
+              <description>Set 0 to reset timer_group1 module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMERGROUP1_TIMER_CLK_CONF</name>
+          <description>TIMERGROUP1_TIMER_CLK configuration register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>TG1_TIMER_CLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TG1_TIMER_CLK_EN</name>
+              <description>Set 1 to enable timer_group1 timer clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMERGROUP1_WDT_CLK_CONF</name>
+          <description>TIMERGROUP1_WDT_CLK configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>TG1_WDT_CLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TG1_WDT_CLK_EN</name>
+              <description>Set 1 to enable timer_group0 wdt clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_CONF</name>
+          <description>SYSTIMER configuration register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_CLK_EN</name>
+              <description>Set 1 to enable systimer apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_RST_EN</name>
+              <description>Set 0 to reset systimer module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_FUNC_CLK_CONF</name>
+          <description>SYSTIMER_FUNC_CLK configuration register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_FUNC_CLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: FOSC.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_FUNC_CLK_EN</name>
+              <description>Set 1 to enable systimer function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TWAI0_CONF</name>
+          <description>TWAI0 configuration register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TWAI0_CLK_EN</name>
+              <description>Set 1 to enable twai0 apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TWAI0_RST_EN</name>
+              <description>Set 0 to reset twai0 module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TWAI0_FUNC_CLK_CONF</name>
+          <description>TWAI0_FUNC_CLK configuration register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>TWAI0_FUNC_CLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: FOSC.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TWAI0_FUNC_CLK_EN</name>
+              <description>Set 1 to enable twai0 function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TWAI1_CONF</name>
+          <description>TWAI1 configuration register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TWAI1_CLK_EN</name>
+              <description>Set 1 to enable twai1 apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TWAI1_RST_EN</name>
+              <description>Set 0 to reset twai1 module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TWAI1_FUNC_CLK_CONF</name>
+          <description>TWAI1_FUNC_CLK configuration register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>TWAI1_FUNC_CLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: FOSC.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TWAI1_FUNC_CLK_EN</name>
+              <description>Set 1 to enable twai1 function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_CONF</name>
+          <description>I2S configuration register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>I2S_CLK_EN</name>
+              <description>Set 1 to enable i2s apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RST_EN</name>
+              <description>Set 0 to reset i2s module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_TX_CLKM_CONF</name>
+          <description>I2S_TX_CLKM configuration register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00402000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_TX_CLKM_DIV_NUM</name>
+              <description>Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b &lt;= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLKM_SEL</name>
+              <description>Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLKM_EN</name>
+              <description>Set 1 to enable i2s_tx function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_TX_CLKM_DIV_CONF</name>
+          <description>I2S_TX_CLKM_DIV configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>I2S_TX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_RX_CLKM_CONF</name>
+          <description>I2S_RX_CLKM configuration register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00402000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_RX_CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLKM_SEL</name>
+              <description>Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLKM_EN</name>
+              <description>Set 1 to enable i2s_rx function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_MCLK_SEL</name>
+              <description>This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_RX_CLKM_DIV_CONF</name>
+          <description>I2S_RX_CLKM_DIV configuration register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>I2S_RX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SARADC_CONF</name>
+          <description>SARADC configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_CLK_EN</name>
+              <description>no use</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_RST_EN</name>
+              <description>Set 0 to reset function_register of saradc module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_REG_CLK_EN</name>
+              <description>Set 1 to enable saradc apb clock</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_REG_RST_EN</name>
+              <description>Set 0 to reset apb_register of saradc module</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SARADC_CLKM_CONF</name>
+          <description>SARADC_CLKM configuration register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00404000</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_CLKM_DIV_A</name>
+              <description>The  denominator of the frequency divider factor of the saradc function clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_CLKM_DIV_B</name>
+              <description>The numerator of the frequency divider factor of the saradc function clock.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_CLKM_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor of the saradc function clock.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_CLKM_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: reserved.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_CLKM_EN</name>
+              <description>Set 1 to enable saradc function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TSENS_CLK_CONF</name>
+          <description>TSENS_CLK configuration register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_CLK_SEL</name>
+              <description>set this field to select clock-source. 0(default): FOSC, 1: XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_EN</name>
+              <description>Set 1 to enable tsens clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_RST_EN</name>
+              <description>Set 0 to reset tsens module</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_DEVICE_CONF</name>
+          <description>USB_DEVICE configuration register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_DEVICE_CLK_EN</name>
+              <description>Set 1 to enable usb_device clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DEVICE_RST_EN</name>
+              <description>Set 0 to reset usb_device module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTMTX_CONF</name>
+          <description>INTMTX configuration register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>INTMTX_CLK_EN</name>
+              <description>Set 1 to enable intmtx clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTMTX_RST_EN</name>
+              <description>Set 0 to reset intmtx module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCNT_CONF</name>
+          <description>PCNT configuration register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PCNT_CLK_EN</name>
+              <description>Set 1 to enable pcnt clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCNT_RST_EN</name>
+              <description>Set 0 to reset pcnt module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_CONF</name>
+          <description>ETM configuration register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ETM_CLK_EN</name>
+              <description>Set 1 to enable etm clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_RST_EN</name>
+              <description>Set 0 to reset etm module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM_CONF</name>
+          <description>PWM configuration register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PWM_CLK_EN</name>
+              <description>Set 1 to enable pwm clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM_RST_EN</name>
+              <description>Set 0 to reset pwm module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM_CLK_CONF</name>
+          <description>PWM_CLK configuration register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00404000</resetValue>
+          <fields>
+            <field>
+              <name>PWM_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor of the pwm function clock.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM_CLKM_SEL</name>
+              <description>set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM_CLKM_EN</name>
+              <description>set this field as 1 to activate pwm clkm.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARL_IO_CONF</name>
+          <description>PARL_IO configuration register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PARL_CLK_EN</name>
+              <description>Set 1 to enable parl apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARL_RST_EN</name>
+              <description>Set 0 to reset parl apb reg</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARL_CLK_RX_CONF</name>
+          <description>PARL_CLK_RX configuration register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040000</resetValue>
+          <fields>
+            <field>
+              <name>PARL_CLK_RX_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor of the parl rx clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARL_CLK_RX_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARL_CLK_RX_EN</name>
+              <description>Set 1 to enable parl rx clock</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARL_RX_RST_EN</name>
+              <description>Set 0 to reset parl rx module</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PARL_CLK_TX_CONF</name>
+          <description>PARL_CLK_TX configuration register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040000</resetValue>
+          <fields>
+            <field>
+              <name>PARL_CLK_TX_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor of the parl tx clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARL_CLK_TX_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARL_CLK_TX_EN</name>
+              <description>Set 1 to enable parl tx clock</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARL_TX_RST_EN</name>
+              <description>Set 0 to reset parl tx module</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SLAVE_CONF</name>
+          <description>SDIO_SLAVE configuration register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_SLAVE_CLK_EN</name>
+              <description>Set 1 to enable sdio_slave clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_SLAVE_RST_EN</name>
+              <description>Set 0 to reset sdio_slave module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PVT_MONITOR_CONF</name>
+          <description>PVT_MONITOR configuration register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000001D</resetValue>
+          <fields>
+            <field>
+              <name>PVT_MONITOR_CLK_EN</name>
+              <description>Set 1 to enable apb clock of pvt module</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVT_MONITOR_RST_EN</name>
+              <description>Set 0 to reset all pvt monitor module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVT_MONITOR_SITE1_CLK_EN</name>
+              <description>Set 1 to enable function clock of modem pvt module</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVT_MONITOR_SITE2_CLK_EN</name>
+              <description>Set 1 to enable function clock of cpu pvt module</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVT_MONITOR_SITE3_CLK_EN</name>
+              <description>Set 1 to enable function clock of hp_peri pvt module</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PVT_MONITOR_FUNC_CLK_CONF</name>
+          <description>PVT_MONITOR function clock configuration register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>PVT_MONITOR_FUNC_CLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor of the pvt_monitor function clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVT_MONITOR_FUNC_CLK_SEL</name>
+              <description>set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL divided by 3.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVT_MONITOR_FUNC_CLK_EN</name>
+              <description>Set 1 to enable source clock of pvt sitex</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GDMA_CONF</name>
+          <description>GDMA configuration register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>GDMA_CLK_EN</name>
+              <description>Set 1 to enable gdma clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GDMA_RST_EN</name>
+              <description>Set 0 to reset gdma module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI2_CONF</name>
+          <description>SPI2 configuration register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SPI2_CLK_EN</name>
+              <description>Set 1 to enable spi2 apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_RST_EN</name>
+              <description>Set 0 to reset spi2 module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI2_CLKM_CONF</name>
+          <description>SPI2_CLKM configuration register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>SPI2_CLKM_SEL</name>
+              <description>set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_CLKM_EN</name>
+              <description>Set 1 to enable spi2 function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AES_CONF</name>
+          <description>AES configuration register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>AES_CLK_EN</name>
+              <description>Set 1 to enable aes clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AES_RST_EN</name>
+              <description>Set 0 to reset aes module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA_CONF</name>
+          <description>SHA configuration register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SHA_CLK_EN</name>
+              <description>Set 1 to enable sha clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SHA_RST_EN</name>
+              <description>Set 0 to reset sha module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_CONF</name>
+          <description>RSA configuration register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RSA_CLK_EN</name>
+              <description>Set 1 to enable rsa clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_RST_EN</name>
+              <description>Set 0 to reset rsa module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_PD_CTRL</name>
+          <description>RSA power control register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RSA_MEM_PD</name>
+              <description>Set this bit to power down rsa internal memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PU</name>
+              <description>Set this bit to force power up rsa internal memory</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PD</name>
+              <description>Set this bit to force power down rsa internal memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ECC_CONF</name>
+          <description>ECC configuration register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ECC_CLK_EN</name>
+              <description>Set 1 to enable ecc clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ECC_RST_EN</name>
+              <description>Set 0 to reset ecc module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ECC_PD_CTRL</name>
+          <description>ECC power control register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>ECC_MEM_PD</name>
+              <description>Set this bit to power down ecc internal memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ECC_MEM_FORCE_PU</name>
+              <description>Set this bit to force power up ecc internal memory</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ECC_MEM_FORCE_PD</name>
+              <description>Set this bit to force power down ecc internal memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DS_CONF</name>
+          <description>DS configuration register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>DS_CLK_EN</name>
+              <description>Set 1 to enable ds clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DS_RST_EN</name>
+              <description>Set 0 to reset ds module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HMAC_CONF</name>
+          <description>HMAC configuration register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>HMAC_CLK_EN</name>
+              <description>Set 1 to enable hmac clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HMAC_RST_EN</name>
+              <description>Set 0 to reset hmac module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IOMUX_CONF</name>
+          <description>IOMUX configuration register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IOMUX_CLK_EN</name>
+              <description>Set 1 to enable iomux apb clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IOMUX_RST_EN</name>
+              <description>Set 0 to reset iomux module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IOMUX_CLK_CONF</name>
+          <description>IOMUX_CLK configuration register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00700000</resetValue>
+          <fields>
+            <field>
+              <name>IOMUX_FUNC_CLK_SEL</name>
+              <description>set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IOMUX_FUNC_CLK_EN</name>
+              <description>Set 1 to enable iomux function clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_MONITOR_CONF</name>
+          <description>MEM_MONITOR configuration register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>MEM_MONITOR_CLK_EN</name>
+              <description>Set 1 to enable mem_monitor clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_MONITOR_RST_EN</name>
+              <description>Set 0 to reset mem_monitor module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGDMA_CONF</name>
+          <description>REGDMA configuration register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGDMA_CLK_EN</name>
+              <description>Set 1 to enable regdma clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGDMA_RST_EN</name>
+              <description>Set 0 to reset regdma module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CONF</name>
+          <description>retention configuration register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RETENTION_CLK_EN</name>
+              <description>Set 1 to enable retention clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_RST_EN</name>
+              <description>Set 0 to reset retention module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRACE_CONF</name>
+          <description>TRACE configuration register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TRACE_CLK_EN</name>
+              <description>Set 1 to enable trace clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRACE_RST_EN</name>
+              <description>Set 0 to reset trace module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ASSIST_CONF</name>
+          <description>ASSIST configuration register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ASSIST_CLK_EN</name>
+              <description>Set 1 to enable assist clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ASSIST_RST_EN</name>
+              <description>Set 0 to reset assist module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CONF</name>
+          <description>CACHE configuration register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_CLK_EN</name>
+              <description>Set 1 to enable cache clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_RST_EN</name>
+              <description>Set 0 to reset cache module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEM_APB_CONF</name>
+          <description>MODEM_APB configuration register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>MODEM_APB_CLK_EN</name>
+              <description>This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODEM_RST_EN</name>
+              <description>Set this file as 1 to reset modem-subsystem.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMEOUT_CONF</name>
+          <description>TIMEOUT configuration register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_TIMEOUT_RST_EN</name>
+              <description>Set 0 to reset cpu_peri timeout module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_TIMEOUT_RST_EN</name>
+              <description>Set 0 to reset hp_peri timeout module and hp_modem timeout module</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSCLK_CONF</name>
+          <description>SYSCLK configuration register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x28000200</resetValue>
+          <fields>
+            <field>
+              <name>LS_DIV_NUM</name>
+              <description>clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed clock-source such as XTAL/FOSC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HS_DIV_NUM</name>
+              <description>clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOC_CLK_SEL</name>
+              <description>This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_XTAL_FREQ</name>
+              <description>This field indicates the frequency(MHz) of XTAL.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_WAITI_CONF</name>
+          <description>CPU_WAITI configuration register</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000D</resetValue>
+          <fields>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <description>Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PLL_FREQ_SEL</name>
+              <description>Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CPU_WAIT_MODE_FORCE_ON</name>
+              <description>Set 1 to force cpu_waiti_clk enable.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_WAITI_DELAY_NUM</name>
+              <description>This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_FREQ_CONF</name>
+          <description>CPU_FREQ configuration register</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_LS_DIV_NUM</name>
+              <description>Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_HS_DIV_NUM</name>
+              <description>Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_HS_120M_FORCE</name>
+              <description>Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_FREQ_CONF</name>
+          <description>AHB_FREQ configuration register</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000300</resetValue>
+          <fields>
+            <field>
+              <name>AHB_LS_DIV_NUM</name>
+              <description>Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_CPU_LS_DIV_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_HS_DIV_NUM</name>
+              <description>Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_FREQ_CONF</name>
+          <description>APB_FREQ configuration register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_DECREASE_DIV_NUM</name>
+              <description>If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be automatically down to clk_apb_decrease only when no access is on apb-bus, and will recover to the previous frequency when a new access appears on apb-bus. Set as one within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note that enable this function will reduce performance. Users can set this field as zero to disable the auto-decrease-apb-freq function. By default, this function is disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_DIV_NUM</name>
+              <description>Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is div1(default)/div2/div4 of clk_ahb.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSCLK_FREQ_QUERY_0</name>
+          <description>SYSCLK frequency query 0 register</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001E014</resetValue>
+          <fields>
+            <field>
+              <name>FOSC_FREQ</name>
+              <description>This field indicates the frequency(MHz) of FOSC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PLL_FREQ</name>
+              <description>This field indicates the frequency(MHz) of SPLL.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PLL_DIV_CLK_EN</name>
+          <description>SPLL DIV clock-gating configuration register</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000007F</resetValue>
+          <fields>
+            <field>
+              <name>PLL_240M_CLK_EN</name>
+              <description>This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_160M_CLK_EN</name>
+              <description>This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_120M_CLK_EN</name>
+              <description>This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_80M_CLK_EN</name>
+              <description>This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_48M_CLK_EN</name>
+              <description>This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_40M_CLK_EN</name>
+              <description>This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_20M_CLK_EN</name>
+              <description>This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL_CLK_OUT_EN</name>
+          <description>CLK_OUT_EN configuration register</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>CLK20_OEN</name>
+              <description>Set 1 to enable 20m clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK22_OEN</name>
+              <description>Set 1 to enable 22m clock</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK44_OEN</name>
+              <description>Set 1 to enable 44m clock</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_BB_OEN</name>
+              <description>Set 1 to enable bb clock</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK80_OEN</name>
+              <description>Set 1 to enable 80m clock</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK160_OEN</name>
+              <description>Set 1 to enable 160m clock</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_320M_OEN</name>
+              <description>Set 1 to enable 320m clock</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_ADC_INF_OEN</name>
+              <description>Reserved</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DAC_CPU_OEN</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK40X_BB_OEN</name>
+              <description>Set 1 to enable 40x_bb clock</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_XTAL_OEN</name>
+              <description>Set 1 to enable xtal clock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL_TICK_CONF</name>
+          <description>TICK configuration register</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010727</resetValue>
+          <fields>
+            <field>
+              <name>XTAL_TICK_NUM</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FOSC_TICK_NUM</name>
+              <description>******* Description ***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_ENABLE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_TICK_CNT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL_32K_CONF</name>
+          <description>32KHz clock configuration register</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>_32K_SEL</name>
+              <description>This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_POWER_CONF</name>
+          <description>HP SRAM/ROM configuration register</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000700F</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_FORCE_PU</name>
+              <description>Set this bit to force power up SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_FORCE_PD</name>
+              <description>Set this bit to force power down SRAM.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_CLKGATE_FORCE_ON</name>
+              <description>1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A gate-clock will be used when accessing the SRAM.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM_FORCE_PU</name>
+              <description>Set this bit to force power up ROM</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM_FORCE_PD</name>
+              <description>Set this bit to force power down ROM.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM_CLKGATE_FORCE_ON</name>
+              <description>1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A gate-clock will be used when accessing the ROM.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESET_EVENT_BYPASS</name>
+          <description>reset event bypass backdoor configuration register</description>
+          <addressOffset>0xFF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>APM</name>
+              <description>This field is used to control reset event relationship for tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, but also some reset event.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESET_EVENT_BYPASS</name>
+              <description>This field is used to control reset event relationship for system-bus. 1: system bus (including arbiter/router) will only be reset by power-reset. some reset event will be bypass. 0: system bus (including arbiter/router) will not only be reset by power-reset, but also some reset event.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FPGA_DEBUG</name>
+          <description>fpga debug register</description>
+          <addressOffset>0xFF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>FPGA_DEBUG</name>
+              <description>Only used in fpga debug.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>PCR clock gating configure register</description>
+          <addressOffset>0xFF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit as 1 to force on clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206150</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>PCR version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PMU</name>
+      <description>Peripheral PMU</description>
+      <groupName>PMU</groupName>
+      <baseAddress>0x600B0000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1A8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PMU</name>
+        <value>13</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>HP_ACTIVE_DIG_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_VDD_SPI_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_HP_MEM_DSLP</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_PD_HP_MEM_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_PD_HP_WIFI_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_PD_HP_CPU_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_PD_HP_AON_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_PD_TOP_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_ICG_HP_FUNC</name>
+          <description>need_des</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_DIG_ICG_FUNC_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_ICG_HP_APB</name>
+          <description>need_des</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_DIG_ICG_APB_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_ICG_MODEM</name>
+          <description>need_des</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_DIG_ICG_MODEM_CODE</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_HP_SYS_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_UART_WAKEUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_LP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_HP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_DIG_PAD_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_DIG_PAUSE_WDT</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_DIG_CPU_STALL</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_HP_CK_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_I2C_ISO_EN</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_I2C_RETENTION</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_XPD_BB_I2C</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_XPD_BBPLL_I2C</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_XPD_BBPLL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_BIAS</name>
+          <description>need_des</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_XPD_BIAS</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_DBG_ATTEN</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_PD_CUR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_BACKUP</name>
+          <description>need_des</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE</name>
+              <description>need_des</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_RETENTION_MODE</name>
+              <description>need_des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP2ACTIVE_RETENTION_EN</name>
+              <description>need_des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM2ACTIVE_RETENTION_EN</name>
+              <description>need_des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP2ACTIVE_BACKUP_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM2ACTIVE_BACKUP_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP2ACTIVE_BACKUP_MODE</name>
+              <description>need_des</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM2ACTIVE_BACKUP_MODE</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP2ACTIVE_BACKUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM2ACTIVE_BACKUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_BACKUP_CLK</name>
+          <description>need_des</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_BACKUP_ICG_FUNC_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_SYSCLK</name>
+          <description>need_des</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_DIG_SYS_CLK_NO_DIV</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_ICG_SYS_CLOCK_EN</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_SYS_CLK_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_ICG_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_DIG_SYS_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_HP_REGULATOR0</name>
+          <description>need_des</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC6677180</resetValue>
+          <fields>
+            <field>
+              <name>LP_DBIAS_VOL</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HP_DBIAS_VOL</name>
+              <description>need_des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIG_REGULATOR0_DBIAS_SEL</name>
+              <description>need_des</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_DBIAS_INIT</name>
+              <description>need_des</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD</name>
+              <description>need_des</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_HP_REGULATOR_XPD</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE_HP_REGULATOR_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_HP_REGULATOR1</name>
+          <description>need_des</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_HP_REGULATOR_DRV_B</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_ACTIVE_XTAL</name>
+          <description>need_des</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>HP_ACTIVE_XPD_XTAL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_DIG_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_MODEM_VDD_SPI_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_HP_MEM_DSLP</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_PD_HP_MEM_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_PD_HP_WIFI_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_PD_HP_CPU_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_PD_HP_AON_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_PD_TOP_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_ICG_HP_FUNC</name>
+          <description>need_des</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>HP_MODEM_DIG_ICG_FUNC_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_ICG_HP_APB</name>
+          <description>need_des</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>HP_MODEM_DIG_ICG_APB_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_ICG_MODEM</name>
+          <description>need_des</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_MODEM_DIG_ICG_MODEM_CODE</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_HP_SYS_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_MODEM_UART_WAKEUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_LP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_HP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_DIG_PAD_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_DIG_PAUSE_WDT</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_DIG_CPU_STALL</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_HP_CK_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_MODEM_I2C_ISO_EN</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_I2C_RETENTION</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_XPD_BB_I2C</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_XPD_BBPLL_I2C</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_XPD_BBPLL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_BIAS</name>
+          <description>need_des</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_MODEM_XPD_BIAS</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_DBG_ATTEN</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_PD_CUR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_BACKUP</name>
+          <description>need_des</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_RETENTION_MODE</name>
+              <description>need_des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP2MODEM_RETENTION_EN</name>
+              <description>need_des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP2MODEM_BACKUP_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP2MODEM_BACKUP_MODE</name>
+              <description>need_des</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP2MODEM_BACKUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_BACKUP_CLK</name>
+          <description>need_des</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_MODEM_BACKUP_ICG_FUNC_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_SYSCLK</name>
+          <description>need_des</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_MODEM_DIG_SYS_CLK_NO_DIV</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_ICG_SYS_CLOCK_EN</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_SYS_CLK_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_ICG_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_DIG_SYS_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_HP_REGULATOR0</name>
+          <description>need_des</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC6670000</resetValue>
+          <fields>
+            <field>
+              <name>HP_MODEM_HP_REGULATOR_SLP_MEM_XPD</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD</name>
+              <description>need_des</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_HP_REGULATOR_XPD</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM_HP_REGULATOR_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_HP_REGULATOR1</name>
+          <description>need_des</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_MODEM_HP_REGULATOR_DRV_B</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_MODEM_XTAL</name>
+          <description>need_des</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>HP_MODEM_XPD_XTAL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_DIG_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_VDD_SPI_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_HP_MEM_DSLP</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_PD_HP_MEM_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_PD_HP_WIFI_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_PD_HP_CPU_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_PD_HP_AON_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_PD_TOP_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_ICG_HP_FUNC</name>
+          <description>need_des</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>HP_SLEEP_DIG_ICG_FUNC_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_ICG_HP_APB</name>
+          <description>need_des</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>HP_SLEEP_DIG_ICG_APB_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_ICG_MODEM</name>
+          <description>need_des</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_DIG_ICG_MODEM_CODE</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_HP_SYS_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_UART_WAKEUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_LP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_HP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_DIG_PAD_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_DIG_PAUSE_WDT</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_DIG_CPU_STALL</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_HP_CK_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_I2C_ISO_EN</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_I2C_RETENTION</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_XPD_BB_I2C</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_XPD_BBPLL_I2C</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_XPD_BBPLL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_BIAS</name>
+          <description>need_des</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_XPD_BIAS</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_DBG_ATTEN</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_PD_CUR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_BACKUP</name>
+          <description>need_des</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE</name>
+              <description>need_des</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_RETENTION_MODE</name>
+              <description>need_des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM2SLEEP_RETENTION_EN</name>
+              <description>need_des</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE2SLEEP_RETENTION_EN</name>
+              <description>need_des</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM2SLEEP_BACKUP_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE2SLEEP_BACKUP_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM2SLEEP_BACKUP_MODE</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE2SLEEP_BACKUP_MODE</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MODEM2SLEEP_BACKUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_ACTIVE2SLEEP_BACKUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_BACKUP_CLK</name>
+          <description>need_des</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_BACKUP_ICG_FUNC_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_SYSCLK</name>
+          <description>need_des</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_DIG_SYS_CLK_NO_DIV</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_ICG_SYS_CLOCK_EN</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_SYS_CLK_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_ICG_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_DIG_SYS_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_HP_REGULATOR0</name>
+          <description>need_des</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC6670000</resetValue>
+          <fields>
+            <field>
+              <name>HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD</name>
+              <description>need_des</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_HP_REGULATOR_XPD</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_HP_REGULATOR_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_HP_REGULATOR1</name>
+          <description>need_des</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_HP_REGULATOR_DRV_B</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_XTAL</name>
+          <description>need_des</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>HP_SLEEP_XPD_XTAL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_LP_REGULATOR0</name>
+          <description>need_des</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC6600000</resetValue>
+          <fields>
+            <field>
+              <name>HP_SLEEP_LP_REGULATOR_SLP_XPD</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_LP_REGULATOR_XPD</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_LP_REGULATOR_SLP_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_LP_REGULATOR_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_LP_REGULATOR1</name>
+          <description>need_des</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_LP_REGULATOR_DRV_B</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_LP_DCDC_RESERVE</name>
+          <description>need_des</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_LP_DCDC_RESERVE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_LP_DIG_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_SLEEP_LP_MEM_DSLP</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_PD_LP_PERI_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_SLEEP_LP_CK_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>HP_SLEEP_XPD_XTAL32K</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_XPD_RC32K</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_XPD_FOSC_CLK</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SLEEP_PD_OSC_CLK</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_SLEEP_LP_BIAS_RESERVE</name>
+          <description>need_des</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_SLEEP_LP_BIAS_RESERVE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_SLEEP_LP_REGULATOR0</name>
+          <description>need_des</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC6600000</resetValue>
+          <fields>
+            <field>
+              <name>LP_SLEEP_LP_REGULATOR_SLP_XPD</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_SLEEP_LP_REGULATOR_XPD</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_SLEEP_LP_REGULATOR_SLP_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_SLEEP_LP_REGULATOR_DBIAS</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_SLEEP_LP_REGULATOR1</name>
+          <description>need_des</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_SLEEP_LP_REGULATOR_DRV_B</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_SLEEP_XTAL</name>
+          <description>need_des</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>LP_SLEEP_XPD_XTAL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_SLEEP_LP_DIG_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_SLEEP_LP_MEM_DSLP</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_SLEEP_PD_LP_PERI_PD_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_SLEEP_LP_CK_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>LP_SLEEP_XPD_XTAL32K</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_SLEEP_XPD_RC32K</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_SLEEP_XPD_FOSC_CLK</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_SLEEP_PD_OSC_CLK</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_SLEEP_BIAS</name>
+          <description>need_des</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_SLEEP_XPD_BIAS</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_SLEEP_DBG_ATTEN</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_SLEEP_PD_CUR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMM_HP_CK_POWER</name>
+          <description>need_des</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIE_LOW_GLOBAL_BBPLL_ICG</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_GLOBAL_XTAL_ICG</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_I2C_RETENTION</name>
+              <description>need_des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_XPD_BB_I2C</name>
+              <description>need_des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_XPD_BBPLL_I2C</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_XPD_BBPLL</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_XPD_XTAL</name>
+              <description>need_des</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_GLOBAL_BBPLL_ICG</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_GLOBAL_XTAL_ICG</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_I2C_RETENTION</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_XPD_BB_I2C</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_XPD_BBPLL_I2C</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_XPD_BBPLL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_XPD_XTAL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMM_SLEEP_SYSCLK</name>
+          <description>need_des</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UPDATE_DIG_ICG_SWITCH</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_ICG_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_ICG_SLP_SEL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>UPDATE_DIG_SYS_CLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMM_HP_FUNC_ICG</name>
+          <description>need_des</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UPDATE_DIG_ICG_FUNC_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMM_HP_APB_ICG</name>
+          <description>need_des</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UPDATE_DIG_ICG_APB_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMM_MODEM_ICG</name>
+          <description>need_des</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UPDATE_DIG_ICG_MODEM_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMM_LP_ICG</name>
+          <description>need_des</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIE_LOW_LP_ROOTCLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_LP_ROOTCLK_SEL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMM_PAD_HOLD_ALL</name>
+          <description>need_des</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIE_HIGH_LP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_LP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_HIGH_HP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_HP_PAD_HOLD_ALL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IMM_I2C_ISO</name>
+          <description>need_des</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIE_HIGH_I2C_ISO_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIE_LOW_I2C_ISO_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_WAIT_TIMER0</name>
+          <description>need_des</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7FBFDFE0</resetValue>
+          <fields>
+            <field>
+              <name>DG_HP_POWERDOWN_TIMER</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_HP_POWERUP_TIMER</name>
+              <description>need_des</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_HP_WAIT_TIMER</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_WAIT_TIMER1</name>
+          <description>need_des</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7FFFFE00</resetValue>
+          <fields>
+            <field>
+              <name>DG_LP_POWERDOWN_TIMER</name>
+              <description>need_des</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_LP_POWERUP_TIMER</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_LP_WAIT_TIMER</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_PD_TOP_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000001C</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_TOP_RESET</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_TOP_ISO</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_TOP_PU</name>
+              <description>need_des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_TOP_NO_RESET</name>
+              <description>need_des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_TOP_NO_ISO</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_TOP_PD</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_TOP_MASK</name>
+              <description>need_des</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_TOP_PD_MASK</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_PD_HPAON_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000001C</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_HP_AON_RESET</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_AON_ISO</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_AON_PU</name>
+              <description>need_des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_AON_NO_RESET</name>
+              <description>need_des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_AON_NO_ISO</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_AON_PD</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_AON_MASK</name>
+              <description>need_des</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_AON_PD_MASK</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_PD_HPCPU_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000001C</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_HP_CPU_RESET</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_CPU_ISO</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_CPU_PU</name>
+              <description>need_des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_CPU_NO_RESET</name>
+              <description>need_des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_CPU_NO_ISO</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_CPU_PD</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_CPU_MASK</name>
+              <description>need_des</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_CPU_PD_MASK</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_PD_HPPERI_RESERVE</name>
+          <description>need_des</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HP_PERI_RESERVE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_PD_HPWIFI_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000001C</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_HP_WIFI_RESET</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_WIFI_ISO</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_WIFI_PU</name>
+              <description>need_des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_WIFI_NO_RESET</name>
+              <description>need_des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_WIFI_NO_ISO</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_WIFI_PD</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_WIFI_MASK</name>
+              <description>need_des</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_WIFI_PD_MASK</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_PD_LPPERI_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000001C</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_LP_PERI_RESET</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_LP_PERI_ISO</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_LP_PERI_PU</name>
+              <description>need_des</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_LP_PERI_NO_RESET</name>
+              <description>need_des</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_LP_PERI_NO_ISO</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_LP_PERI_PD</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_PD_MEM_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFF000000</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_HP_MEM_ISO</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_MEM_PD</name>
+              <description>need_des</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_MEM_NO_ISO</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_MEM_PU</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_PD_MEM_MASK</name>
+          <description>need_des</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PD_HP_MEM2_PD_MASK</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_MEM1_PD_MASK</name>
+              <description>need_des</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_MEM0_PD_MASK</name>
+              <description>need_des</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_MEM2_MASK</name>
+              <description>need_des</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_MEM1_MASK</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_HP_MEM0_MASK</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_HP_PAD</name>
+          <description>need_des</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FORCE_HP_PAD_NO_ISO_ALL</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_HP_PAD_ISO_ALL</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_VDD_SPI_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x63FC0000</resetValue>
+          <fields>
+            <field>
+              <name>VDD_SPI_PWR_WAIT</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VDD_SPI_PWR_SW</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VDD_SPI_PWR_SEL_SW</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POWER_CK_WAIT_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000100</resetValue>
+          <fields>
+            <field>
+              <name>WAIT_XTL_STABLE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_PLL_STABLE</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CNTL0</name>
+          <description>need_des</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLEEP_REQ</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CNTL1</name>
+          <description>need_des</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLEEP_REJECT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CNTL2</name>
+          <description>need_des</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WAKEUP_ENA</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CNTL3</name>
+          <description>need_des</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_MIN_SLP_VAL</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_MIN_SLP_VAL</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_PRT_SEL</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CNTL4</name>
+          <description>need_des</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_REJECT_CAUSE_CLR</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CNTL5</name>
+          <description>need_des</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000080</resetValue>
+          <fields>
+            <field>
+              <name>MODEM_WAIT_TARGET</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_ANA_WAIT_TARGET</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CNTL6</name>
+          <description>need_des</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>SOC_WAKEUP_WAIT</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOC_WAKEUP_WAIT_CFG</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CNTL7</name>
+          <description>need_des</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>ANA_WAIT_TARGET</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_STATUS0</name>
+          <description>need_des</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WAKEUP_CAUSE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_STATUS1</name>
+          <description>need_des</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REJECT_CAUSE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_CK_POWERON</name>
+          <description>need_des</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000032</resetValue>
+          <fields>
+            <field>
+              <name>I2C_POR_WAIT_TARGET</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_CK_CNTL</name>
+          <description>need_des</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000A0A</resetValue>
+          <fields>
+            <field>
+              <name>MODIFY_ICG_CNTL_WAIT</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWITCH_ICG_CNTL_WAIT</name>
+              <description>need_des</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POR_STATUS</name>
+          <description>need_des</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>POR_DONE</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RF_PWC</name>
+          <description>need_des</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08000000</resetValue>
+          <fields>
+            <field>
+              <name>PERIF_I2C_RSTB</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_PERIF_I2C</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_TXRF_I2C</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_RFRX_PBUS</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_CKGEN_I2C</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_PLL_I2C</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_CFG</name>
+          <description>need_des</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_SYS_CLK_NO_DIV</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>need_des</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_CPU_EXC_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOC_SLEEP_REJECT_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOC_WAKEUP_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_INT_ST</name>
+          <description>need_des</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_CPU_EXC_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOC_SLEEP_REJECT_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOC_WAKEUP_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_INT_ENA</name>
+          <description>need_des</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_CPU_EXC_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOC_SLEEP_REJECT_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOC_WAKEUP_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_INT_CLR</name>
+          <description>need_des</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_CPU_EXC_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SOC_SLEEP_REJECT_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SOC_WAKEUP_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_RAW</name>
+          <description>need_des</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_CPU_WAKEUP_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_ACTIVE_END_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_ACTIVE_END_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_MODEM_END_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_SLEEP_END_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACTIVE_SWITCH_SLEEP_END_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_ACTIVE_START_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_ACTIVE_START_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_MODEM_START_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_SLEEP_START_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACTIVE_SWITCH_SLEEP_START_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HP_SW_TRIGGER_INT_RAW</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_ST</name>
+          <description>need_des</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_CPU_WAKEUP_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_ACTIVE_END_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_ACTIVE_END_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_MODEM_END_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_SLEEP_END_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACTIVE_SWITCH_SLEEP_END_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_ACTIVE_START_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_ACTIVE_START_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_MODEM_START_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_SLEEP_START_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACTIVE_SWITCH_SLEEP_START_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HP_SW_TRIGGER_INT_ST</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_ENA</name>
+          <description>need_des</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_CPU_WAKEUP_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_ACTIVE_END_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_ACTIVE_END_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_MODEM_END_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_SLEEP_END_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ACTIVE_SWITCH_SLEEP_END_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_ACTIVE_START_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_ACTIVE_START_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_MODEM_START_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_SLEEP_START_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ACTIVE_SWITCH_SLEEP_START_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HP_SW_TRIGGER_INT_ENA</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_INT_CLR</name>
+          <description>need_des</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_CPU_WAKEUP_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_ACTIVE_END_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_ACTIVE_END_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_MODEM_END_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_SLEEP_END_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACTIVE_SWITCH_SLEEP_END_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_ACTIVE_START_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_ACTIVE_START_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLEEP_SWITCH_MODEM_START_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MODEM_SWITCH_SLEEP_START_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACTIVE_SWITCH_SLEEP_START_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HP_SW_TRIGGER_INT_CLR</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_CPU_PWR0</name>
+          <description>need_des</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1FF00000</resetValue>
+          <fields>
+            <field>
+              <name>LP_CPU_WAITI_RDY</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LP_CPU_STALL_RDY</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LP_CPU_FORCE_STALL</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_CPU_SLP_WAITI_FLAG_EN</name>
+              <description>need_des</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_CPU_SLP_STALL_FLAG_EN</name>
+              <description>need_des</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_CPU_SLP_STALL_WAIT</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_CPU_SLP_STALL_EN</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_CPU_SLP_RESET_EN</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_CPU_SLP_BYPASS_INTR_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LP_CPU_PWR1</name>
+          <description>need_des</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_CPU_WAKEUP_EN</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LP_CPU_SLEEP_REQ</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_LP_CPU_COMM</name>
+          <description>need_des</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LP_TRIGGER_HP</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>HP_TRIGGER_LP</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HP_REGULATOR_CFG</name>
+          <description>need_des</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIG_REGULATOR_EN_CAL</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAIN_STATE</name>
+          <description>need_des</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08100800</resetValue>
+          <fields>
+            <field>
+              <name>MAIN_LAST_ST_STATE</name>
+              <description>need_des</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TAR_ST_STATE</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_CUR_ST_STATE</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWR_STATE</name>
+          <description>need_des</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00802000</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_ST_STATE</name>
+              <description>need_des</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LP_PWR_ST_STATE</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HP_PWR_ST_STATE</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_STATE0</name>
+          <description>need_des</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>STABLE_XPD_BBPLL_STATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STABLE_XPD_XTAL_STATE</name>
+              <description>need_des</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_CLK_SLP_SEL_STATE</name>
+              <description>need_des</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_CLK_SEL_STATE</name>
+              <description>need_des</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_CLK_NO_DIV_STATE</name>
+              <description>need_des</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICG_SYS_CLK_EN_STATE</name>
+              <description>need_des</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICG_MODEM_SWITCH_STATE</name>
+              <description>need_des</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICG_MODEM_CODE_STATE</name>
+              <description>need_des</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICG_SLP_SEL_STATE</name>
+              <description>need_des</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICG_GLOBAL_XTAL_STATE</name>
+              <description>need_des</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICG_GLOBAL_PLL_STATE</name>
+              <description>need_des</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ANA_I2C_ISO_EN_STATE</name>
+              <description>need_des</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ANA_I2C_RETENTION_STATE</name>
+              <description>need_des</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ANA_XPD_BB_I2C_STATE</name>
+              <description>need_des</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ANA_XPD_BBPLL_I2C_STATE</name>
+              <description>need_des</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ANA_XPD_BBPLL_STATE</name>
+              <description>need_des</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ANA_XPD_XTAL_STATE</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_STATE1</name>
+          <description>need_des</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>ICG_FUNC_EN_STATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_STATE2</name>
+          <description>need_des</description>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>ICG_APB_EN_STATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VDD_SPI_STATUS</name>
+          <description>need_des</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STABLE_VDD_SPI_PWR_DRV</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>need_des</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206250</resetValue>
+          <fields>
+            <field>
+              <name>PMU_DATE</name>
+              <description>need_des</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>need_des</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RMT</name>
+      <description>Remote Control Peripheral</description>
+      <groupName>RMT</groupName>
+      <baseAddress>0x60006000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x78</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RMT</name>
+        <value>49</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TX_CH%sDATA</name>
+          <description>The read and write  data register for CHANNEL%s by apb fifo access.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHDATA</name>
+              <description>Read and write data for channel %s via APB FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TX_CH%sCONF0</name>
+          <description>Channel %s configure register 0</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00710200</resetValue>
+          <fields>
+            <field>
+              <name>TX_START_CH0</name>
+              <description>Set this bit to start sending data on CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_RD_RST_CH0</name>
+              <description>Set this bit to reset read ram address for CHANNEL%s by accessing transmitter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST_CH0</name>
+              <description>Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_CONTI_MODE_CH0</name>
+              <description>Set this bit to restart transmission  from the first data to the last data in CHANNEL%s.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TX_WRAP_EN_CH0</name>
+              <description>This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_LV_CH0</name>
+              <description>This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_EN_CH0</name>
+              <description>This is the output enable-control bit for CHANNEL%s in IDLE state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP_CH0</name>
+              <description>Set this bit to stop the transmitter of CHANNEL%s sending data out.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIV_CNT_CH0</name>
+              <description>This register is used to configure the divider for clock of CHANNEL%s.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE_CH0</name>
+              <description>This register is used to configure the maximum size of memory allocated to CHANNEL%s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EFF_EN_CH0</name>
+              <description>1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN_CH0</name>
+              <description>This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV_CH0</name>
+              <description>This bit is used to configure the position of carrier wave for CHANNEL%s.
+
+1'h0: add carrier wave on low level.
+
+1'h1: add carrier wave on high level.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFIFO_RST_CH0</name>
+              <description>Reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPDATE_CH0</name>
+              <description>synchronization bit for CHANNEL%s</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>RX_CH%sCONF0</name>
+          <description>Channel %s configure register 0</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x30FFFF02</resetValue>
+          <fields>
+            <field>
+              <name>DIV_CNT_CH2</name>
+              <description>This register is used to configure the divider for clock of CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_THRES_CH2</name>
+              <description>When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE_CH2</name>
+              <description>This register is used to configure the maximum size of memory allocated to CHANNEL%s.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN_CH2</name>
+              <description>This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV_CH2</name>
+              <description>This bit is used to configure the position of carrier wave for CHANNEL%s.
+
+1'h0: add carrier wave on low level.
+
+1'h1: add carrier wave on high level.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>RX_CH%sCONF1</name>
+          <description>Channel %s configure register 1</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001E8</resetValue>
+          <fields>
+            <field>
+              <name>RX_EN_CH2</name>
+              <description>Set this bit to enable receiver to receive data on CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_WR_RST_CH2</name>
+              <description>Set this bit to reset write ram address for CHANNEL%s by accessing receiver.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST_CH2</name>
+              <description>Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_CH2</name>
+              <description>This register marks the ownership of CHANNEL%s's ram block.
+
+1'h1: Receiver is using the ram.
+
+1'h0: APB bus is using the ram.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_EN_CH2</name>
+              <description>This is the receive filter's enable bit for CHANNEL%s.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_THRES_CH2</name>
+              <description>Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode).</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_RX_WRAP_EN_CH2</name>
+              <description>This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFIFO_RST_CH2</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPDATE_CH2</name>
+              <description>synchronization bit for CHANNEL%s</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TX_CH%sSTATUS</name>
+          <description>Channel %s status register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_RADDR_EX_CH0</name>
+              <description>This register records the memory address offset when transmitter of CHANNEL%s is using the RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE_CH0</name>
+              <description>This register records the FSM status of CHANNEL%s.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WADDR_CH0</name>
+              <description>This register records the memory address offset when writes RAM over APB bus.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR_CH0</name>
+              <description>This status bit will be set if the offset address out of memory size when reading via APB bus.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY_CH0</name>
+              <description>This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR_CH0</name>
+              <description>This status bit will be set if the offset address out of memory size when writes via APB bus.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR_CH0</name>
+              <description>This register records the memory address offset when reading RAM over APB bus.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RX_CH%sSTATUS</name>
+          <description>Channel %s status register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_WADDR_EX_CH2</name>
+              <description>This register records the memory address offset when receiver of CHANNEL%s is using the RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR_CH2</name>
+              <description>This register records the memory address offset when reads RAM over APB bus.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE_CH2</name>
+              <description>This register records the FSM status of CHANNEL%s.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR_CH2</name>
+              <description>This status bit will be set when the ownership of memory block is wrong.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL_CH2</name>
+              <description>This status bit will be set if the receiver receives more data than the memory size.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR_CH2</name>
+              <description>This status bit will be set if the offset address out of memory size when reads via APB bus.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_TX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL0. Triggered when transmission done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL1. Triggered when transmission done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL2. Triggered when reception done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL3. Triggered when reception done.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH0_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL4. Triggered when error occurs.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH1_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL5. Triggered when error occurs.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH2_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL6. Triggered when error occurs.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH3_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL7. Triggered when error occurs.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than configured value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_LOOP_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_LOOP_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_TX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH0_TX_END_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH1_TX_END_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH2_RX_END_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH3_RX_END_INT.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH0_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH4_ERR_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH1_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH5_ERR_INT.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH2_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH6_ERR_INT.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH3_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH7_ERR_INT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH0_TX_THR_EVENT_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH1_TX_THR_EVENT_INT.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH2_RX_THR_EVENT_INT.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH3_RX_THR_EVENT_INT.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_LOOP_INT_ST</name>
+              <description>The masked interrupt status bit for CH0_TX_LOOP_INT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_LOOP_INT_ST</name>
+              <description>The masked interrupt status bit for CH1_TX_LOOP_INT.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_TX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH0_TX_END_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_TX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH1_TX_END_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2_RX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH2_RX_END_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3_RX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH3_RX_END_INT.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH4_ERR_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH5_ERR_INT.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH6_ERR_INT.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH7_ERR_INT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_TX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH0_TX_THR_EVENT_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_TX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH1_TX_THR_EVENT_INT.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH2_RX_THR_EVENT_INT.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH3_RX_THR_EVENT_INT.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_TX_LOOP_INT_ENA</name>
+              <description>The interrupt enable bit for CH0_TX_LOOP_INT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_TX_LOOP_INT_ENA</name>
+              <description>The interrupt enable bit for CH1_TX_LOOP_INT.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_TX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH0_TX_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH1_TX_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH2_RX_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH3_RX_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_CH0_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH4_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_CH1_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_CH2_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH6_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_CH3_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH7_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_LOOP_INT_CLR</name>
+              <description>Set this bit to clear theCH0_TX_LOOP_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_LOOP_INT_CLR</name>
+              <description>Set this bit to clear theCH1_TX_LOOP_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%sCARRIER_DUTY</name>
+          <description>Channel %s duty cycle configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW_CH0</name>
+              <description>This register is used to configure carrier wave 's low level clock period for CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH_CH0</name>
+              <description>This register is used to configure carrier wave 's high level clock period for CHANNEL%s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_RX_CARRIER_RM</name>
+          <description>Channel %s carrier remove register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARRIER_LOW_THRES_CH2</name>
+              <description>The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH_THRES_CH2</name>
+              <description>The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_TX_LIM</name>
+          <description>Channel %s Tx event configuration register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>TX_LIM_CH0</name>
+              <description>This register is used to configure the maximum entries that CHANNEL%s can send out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_NUM_CH0</name>
+              <description>This register is used to configure the maximum loop count when tx_conti_mode is valid.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_CNT_EN_CH0</name>
+              <description>This register is the enabled bit for loop count.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOP_COUNT_RESET_CH0</name>
+              <description>This register is used to reset the loop count when tx_conti_mode is valid.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LOOP_STOP_EN_CH0</name>
+              <description>This bit is used to enable the loop send stop function after the loop counter counts to  loop number for CHANNEL%s.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_RX_LIM</name>
+          <description>Channel %s Rx event configuration register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>RMT_RX_LIM_CH2</name>
+              <description>This register is used to configure the maximum entries that CHANNEL%s can receive.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYS_CONF</name>
+          <description>RMT apb configuration register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x05000010</resetValue>
+          <fields>
+            <field>
+              <name>APB_FIFO_MASK</name>
+              <description>1'h1: access memory directly.   1'h0: access memory by FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>Set this bit to enable the clock for RMT memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_MEM_FORCE_PD</name>
+              <description>Set this bit to power down RMT memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_MEM_FORCE_PU</name>
+              <description>1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_DIV_NUM</name>
+              <description>the integral part of the fractional divisor</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_DIV_A</name>
+              <description>the numerator of the fractional part of the fractional divisor</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_DIV_B</name>
+              <description>the denominator of the fractional part of the fractional divisor</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_SEL</name>
+              <description>choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_ACTIVE</name>
+              <description>rmt_sclk switch</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_SIM</name>
+          <description>RMT TX synchronous register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0</name>
+              <description>Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1</name>
+              <description>Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>This register is used to enable multiple of channels to start sending data synchronously.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REF_CNT_RST</name>
+          <description>RMT clock divider reset register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_REF_CNT_RST_CH0</name>
+              <description>This register is used to reset the clock divider of CHANNEL0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_REF_CNT_RST_CH1</name>
+              <description>This register is used to reset the clock divider of CHANNEL1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_REF_CNT_RST_CH2</name>
+              <description>This register is used to reset the clock divider of CHANNEL2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_REF_CNT_RST_CH3</name>
+              <description>This register is used to reset the clock divider of CHANNEL3.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>RMT version register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02108213</resetValue>
+          <fields>
+            <field>
+              <name>RMT_DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RNG</name>
+      <description>Hardware random number generator</description>
+      <groupName>RNG</groupName>
+      <baseAddress>0x600B2800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>DATA</name>
+          <description>Random number data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RSA</name>
+      <description>RSA (Rivest Shamir Adleman) Accelerator</description>
+      <groupName>RSA</groupName>
+      <baseAddress>0x6008A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x74</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RSA</name>
+        <value>75</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>The memory that stores M</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Z_MEM[%s]</name>
+          <description>The memory that stores Z</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Y_MEM[%s]</name>
+          <description>The memory that stores Y</description>
+          <addressOffset>0x400</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>X_MEM[%s]</name>
+          <description>The memory that stores X</description>
+          <addressOffset>0x600</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>M_PRIME</name>
+          <description>RSA M_prime register</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M_PRIME</name>
+              <description>Those bits stores m'</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>RSA mode register</description>
+          <addressOffset>0x804</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>rsa mode (rsa length).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_CLEAN</name>
+          <description>RSA query clean register</description>
+          <addressOffset>0x808</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_CLEAN</name>
+              <description>query clean</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_START_MODEXP</name>
+          <description>RSA modular exponentiation trigger register.</description>
+          <addressOffset>0x80C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START_MODEXP</name>
+              <description>start modular exponentiation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_START_MODMULT</name>
+          <description>RSA modular multiplication trigger register.</description>
+          <addressOffset>0x810</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START_MODMULT</name>
+              <description>start modular multiplication</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_START_MULT</name>
+          <description>RSA normal multiplication trigger register.</description>
+          <addressOffset>0x814</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START_MULT</name>
+              <description>start multiplicaiton</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_IDLE</name>
+          <description>RSA query idle register</description>
+          <addressOffset>0x818</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_IDLE</name>
+              <description>query rsa idle. 1'b0: busy, 1'b1: idle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>RSA interrupt clear register</description>
+          <addressOffset>0x81C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>set this bit to clear RSA interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONSTANT_TIME</name>
+          <description>RSA constant time option register</description>
+          <addressOffset>0x820</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CONSTANT_TIME</name>
+              <description>Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_ENABLE</name>
+          <description>RSA search option</description>
+          <addressOffset>0x824</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_ENABLE</name>
+              <description>Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_POS</name>
+          <description>RSA search position configure register</description>
+          <addressOffset>0x828</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_POS</name>
+              <description>Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>RSA interrupt enable register</description>
+          <addressOffset>0x82C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_ENA</name>
+              <description>Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>RSA version control register</description>
+          <addressOffset>0x830</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200618</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>rsa version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SHA</name>
+      <description>SHA (Secure Hash Algorithm) Accelerator</description>
+      <groupName>SHA</groupName>
+      <baseAddress>0x60089000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SHA</name>
+        <value>74</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Initial configuration register.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Sha mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_STRING</name>
+          <description>SHA 512/t configuration register 0.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_STRING</name>
+              <description>Sha t_string (used if and only if mode == SHA_512/t).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_LENGTH</name>
+          <description>SHA 512/t configuration register 1.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LENGTH</name>
+              <description>Sha t_length (used if and only if mode == SHA_512/t).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_BLOCK_NUM</name>
+          <description>DMA configuration register 0.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_BLOCK_NUM</name>
+              <description>Dma-sha block number.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>START</name>
+          <description>Typical SHA configuration register 0.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE</name>
+          <description>Typical SHA configuration register 1.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSY</name>
+          <description>Busy register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Sha busy state. 1'b0: idle. 1'b1: busy.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_START</name>
+          <description>DMA configuration register 1.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_START</name>
+              <description>Start dma-sha.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONTINUE</name>
+          <description>DMA configuration register 2.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CONTINUE</name>
+              <description>Continue dma-sha.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR_IRQ</name>
+          <description>Interrupt clear register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>Clear sha interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IRQ_ENA</name>
+          <description>Interrupt enable register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT_ENA</name>
+              <description>Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20201229</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Sha date information/ sha version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>H_MEM[%s]</name>
+          <description>Sha H memory which contains intermediate hash or finial hash.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>Sha M memory which contains message.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SLCHOST</name>
+      <description>Peripheral SLCHOST</description>
+      <groupName>SLCHOST</groupName>
+      <baseAddress>0x60017000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x104</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>FUNC2_0</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC_FUNC2_INT</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC2_1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC_FUNC2_INT_EN</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC2_2</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SLC_FUNC1_MDSTAT</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_STATUS0</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_SDIO_INT0</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_STATUS1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_SDIO_INT1</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_IN0</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_SDIO_IN0</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_IN1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_SDIO_IN1</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_TOKEN_RDATA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOKEN0</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_PF_VALID</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOSTSLCHOST_SLC0_TOKEN1</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_PF_EOF</name>
+              <description>*******Description***********</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0_HOST_PF</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_PF_DATA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1_HOST_PF</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_PF_DATA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_INT_RAW</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOHOST_BIT0_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT1_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT2_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT3_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT4_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT5_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT6_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT7_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_0TO1_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_0TO1_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_SOF_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_EOF_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_START_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_TX_START_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_PF_VALID_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT0_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT1_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT2_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT3_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_NEW_PACKET_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_RETRY_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO_SDIO_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_INT_RAW</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TOHOST_BIT0_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT1_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT2_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT3_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT4_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT5_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT6_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT7_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_0TO1_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_0TO1_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_SOF_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_EOF_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_START_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TX_START_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_PF_VALID_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT0_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT1_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT2_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT3_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_WIFI_RX_NEW_PACKET_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_RETRY_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_BT_RX_NEW_PACKET_INT_RAW</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_INT_ST</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOHOST_BIT0_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT1_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT2_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT3_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT4_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT5_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT6_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT7_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_0TO1_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_0TO1_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_SOF_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_EOF_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_START_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_TX_START_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_PF_VALID_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT0_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT1_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT2_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT3_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_NEW_PACKET_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_RETRY_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO_SDIO_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_INT_ST</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TOHOST_BIT0_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT1_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT2_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT3_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT4_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT5_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT6_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT7_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_0TO1_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_0TO1_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_SOF_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_EOF_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_START_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TX_START_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_PF_VALID_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT0_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT1_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT2_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT3_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_WIFI_RX_NEW_PACKET_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_RETRY_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_BT_RX_NEW_PACKET_INT_ST</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_LEN</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOSTSLCHOST_SLC0_LEN</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOSTSLCHOST_SLC0_LEN_CHECK</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE_W0</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_STATE0</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLCHOST_STATE1</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLCHOST_STATE2</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLCHOST_STATE3</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE_W1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_STATE4</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLCHOST_STATE5</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLCHOST_STATE6</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLCHOST_STATE7</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W0</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF0</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF1</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF2</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF3</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF4</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF5</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF6</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF7</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W2</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF8</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF9</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF10</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF11</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W3</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000C0</resetValue>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF12</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF13</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF14</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF15</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W4</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001FF</resetValue>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF16</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF17</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF18</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF19</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W5</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF20</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF21</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF22</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF23</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIN_CMD</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_WIN_CMD</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W6</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF24</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF25</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF26</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF27</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W7</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF28</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF29</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF30</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF31</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_LEN0</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOSTSLCHOST_SLC0_LEN0</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOSTSLCHOST_SLC0_LEN0_CHECK</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_LEN1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOSTSLCHOST_SLC0_LEN1</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOSTSLCHOST_SLC0_LEN1_CHECK</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_LEN2</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HOSTSLCHOST_SLC0_LEN2</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOSTSLCHOST_SLC0_LEN2_CHECK</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W8</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF32</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF33</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF34</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF35</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W9</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF36</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF37</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF38</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF39</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W10</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF40</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF41</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF42</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF43</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W11</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF44</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF45</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF46</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF47</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W12</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF48</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF49</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF50</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF51</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W13</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF52</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF53</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF54</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF55</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W14</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF56</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF57</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF58</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF59</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_W15</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CONF60</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF61</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF62</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_CONF63</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHECK_SUM0</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLCHOST_CHECK_SUM0</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHECK_SUM1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000013F</resetValue>
+          <fields>
+            <field>
+              <name>SLCHOST_CHECK_SUM1</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_TOKEN_RDATA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TOKEN0</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_PF_VALID</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HOSTSLCHOST_SLC1_TOKEN1</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_PF_EOF</name>
+              <description>*******Description***********</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_TOKEN_WDATA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0HOST_TOKEN0_WD</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0HOST_TOKEN1_WD</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_TOKEN_WDATA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1HOST_TOKEN0_WD</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TOKEN1_WD</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOKEN_CON</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0HOST_TOKEN0_DEC</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_TOKEN1_DEC</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_TOKEN0_WR</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_TOKEN1_WR</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TOKEN0_DEC</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TOKEN1_DEC</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TOKEN0_WR</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TOKEN1_WR</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_LEN_WR</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_INT_CLR</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOHOST_BIT0_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT1_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT2_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT3_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT4_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT5_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT6_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT7_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_0TO1_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_0TO1_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_SOF_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_EOF_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_START_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0HOST_TX_START_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_PF_VALID_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT0_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT1_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT2_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT3_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_RX_NEW_PACKET_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_RETRY_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPIO_SDIO_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_INT_CLR</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TOHOST_BIT0_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT1_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT2_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT3_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT4_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT5_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT6_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT7_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_0TO1_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_0TO1_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_SOF_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_EOF_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_START_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TX_START_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_RX_PF_VALID_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT0_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT1_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT2_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT3_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_WIFI_RX_NEW_PACKET_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_RETRY_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLC1_BT_RX_NEW_PACKET_INT_CLR</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_FUNC1_INT_ENA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FN1_SLC0_TOHOST_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOHOST_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOHOST_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOHOST_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOHOST_BIT4_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOHOST_BIT5_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOHOST_BIT6_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOHOST_BIT7_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOKEN0_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOKEN1_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOKEN0_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TOKEN1_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0HOST_RX_SOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0HOST_RX_EOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0HOST_RX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0HOST_TX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_RX_UDF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_TX_OVF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_RX_PF_VALID_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_EXT_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_EXT_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_EXT_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_EXT_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_RX_NEW_PACKET_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC0_HOST_RD_RETRY_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_GPIO_SDIO_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_FUNC1_INT_ENA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FN1_SLC1_TOHOST_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOHOST_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOHOST_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOHOST_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOHOST_BIT4_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOHOST_BIT5_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOHOST_BIT6_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOHOST_BIT7_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOKEN0_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOKEN1_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOKEN0_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TOKEN1_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1HOST_RX_SOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1HOST_RX_EOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1HOST_RX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1HOST_TX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_RX_UDF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_TX_OVF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_RX_PF_VALID_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_EXT_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_EXT_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_EXT_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_EXT_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_HOST_RD_RETRY_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_FUNC2_INT_ENA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FN2_SLC0_TOHOST_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOHOST_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOHOST_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOHOST_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOHOST_BIT4_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOHOST_BIT5_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOHOST_BIT6_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOHOST_BIT7_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOKEN0_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOKEN1_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOKEN0_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TOKEN1_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0HOST_RX_SOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0HOST_RX_EOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0HOST_RX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0HOST_TX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_RX_UDF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_TX_OVF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_RX_PF_VALID_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_EXT_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_EXT_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_EXT_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_EXT_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_RX_NEW_PACKET_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC0_HOST_RD_RETRY_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_GPIO_SDIO_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_FUNC2_INT_ENA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FN2_SLC1_TOHOST_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOHOST_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOHOST_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOHOST_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOHOST_BIT4_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOHOST_BIT5_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOHOST_BIT6_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOHOST_BIT7_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOKEN0_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOKEN1_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOKEN0_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TOKEN1_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1HOST_RX_SOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1HOST_RX_EOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1HOST_RX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1HOST_TX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_RX_UDF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_TX_OVF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_RX_PF_VALID_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_EXT_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_EXT_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_EXT_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_EXT_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_HOST_RD_RETRY_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_INT_ENA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOHOST_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT4_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT5_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT6_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT7_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_SOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_EOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0HOST_TX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_PF_VALID_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_NEW_PACKET_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_RETRY_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_SDIO_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_INT_ENA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TOHOST_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT4_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT5_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT6_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT7_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_0TO1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_SOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_EOF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TX_START_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_PF_VALID_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT0_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT1_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT2_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT3_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_WIFI_RX_NEW_PACKET_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_RETRY_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_BT_RX_NEW_PACKET_INT_ENA</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_RX_INFOR</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0HOST_RX_INFOR</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_RX_INFOR</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1HOST_RX_INFOR</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_LEN_WD</name>
+          <description>*******Description***********</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0HOST_LEN_WD</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_APBWIN_WDATA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC_APBWIN_WDATA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_APBWIN_CONF</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC_APBWIN_ADDR</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_APBWIN_WR</name>
+              <description>*******Description***********</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_APBWIN_START</name>
+              <description>*******Description***********</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_APBWIN_RDATA</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC_APBWIN_RDATA</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RDCLR0</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003C044</resetValue>
+          <fields>
+            <field>
+              <name>SLCHOST_SLC0_BIT7_CLRADDR</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_SLC0_BIT6_CLRADDR</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RDCLR1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003C1E0</resetValue>
+          <fields>
+            <field>
+              <name>SLCHOST_SLC1_BIT7_CLRADDR</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLCHOST_SLC1_BIT6_CLRADDR</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0HOST_INT_ENA1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC0_TOHOST_BIT0_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT1_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT2_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT3_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT4_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT5_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT6_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOHOST_BIT7_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_1TO0_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_1TO0_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN0_0TO1_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TOKEN1_0TO1_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_SOF_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_EOF_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0HOST_RX_START_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0HOST_TX_START_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_UDF_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_TX_OVF_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_PF_VALID_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT0_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT1_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT2_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_EXT_BIT3_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_RX_NEW_PACKET_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC0_HOST_RD_RETRY_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_SDIO_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1HOST_INT_ENA1</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLC1_TOHOST_BIT0_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT1_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT2_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT3_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT4_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT5_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT6_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOHOST_BIT7_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_1TO0_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_1TO0_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN0_0TO1_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TOKEN1_0TO1_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_SOF_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_EOF_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1HOST_RX_START_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1HOST_TX_START_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_UDF_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_TX_OVF_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_RX_PF_VALID_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT0_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT1_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT2_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_EXT_BIT3_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_WIFI_RX_NEW_PACKET_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_HOST_RD_RETRY_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC1_BT_RX_NEW_PACKET_INT_ENA1</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLCHOSTDATE</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x21060700</resetValue>
+          <fields>
+            <field>
+              <name>SLCHOST_DATE</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLCHOSTID</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000600</resetValue>
+          <fields>
+            <field>
+              <name>SLCHOST_ID</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FRC_SDIO11</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRC_SDIO20</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRC_NEG_SAMP</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRC_POS_SAMP</name>
+              <description>*******Description***********</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRC_QUICK_IN</name>
+              <description>*******Description***********</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO20_INT_DELAY</name>
+              <description>*******Description***********</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_PAD_PULLUP</name>
+              <description>*******Description***********</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSPEED_CON_EN</name>
+              <description>*******Description***********</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INF_ST</name>
+          <description>*******Description***********</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO20_MODE</name>
+              <description>*******Description***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_NEG_SAMP</name>
+              <description>*******Description***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_QUICK_IN</name>
+              <description>*******Description***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DLL_ON_SW</name>
+              <description>dll is controlled by software</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DLL_ON</name>
+              <description>Software dll on</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_MODE_SW</name>
+              <description>dll clock mode is controlled by software</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_MODE</name>
+              <description>Software set clock mode</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SOC_ETM</name>
+      <description>Peripheral SOC_ETM</description>
+      <groupName>SOC_ETM</groupName>
+      <baseAddress>0x60013000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1B0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CH_ENA_AD0</name>
+          <description>channel enable register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_ENA0</name>
+              <description>ch0 enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA1</name>
+              <description>ch1 enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA2</name>
+              <description>ch2 enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA3</name>
+              <description>ch3 enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA4</name>
+              <description>ch4 enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA5</name>
+              <description>ch5 enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA6</name>
+              <description>ch6 enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA7</name>
+              <description>ch7 enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA8</name>
+              <description>ch8 enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA9</name>
+              <description>ch9 enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA10</name>
+              <description>ch10 enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA11</name>
+              <description>ch11 enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA12</name>
+              <description>ch12 enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA13</name>
+              <description>ch13 enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA14</name>
+              <description>ch14 enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA15</name>
+              <description>ch15 enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA16</name>
+              <description>ch16 enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA17</name>
+              <description>ch17 enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA18</name>
+              <description>ch18 enable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA19</name>
+              <description>ch19 enable</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA20</name>
+              <description>ch20 enable</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA21</name>
+              <description>ch21 enable</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA22</name>
+              <description>ch22 enable</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA23</name>
+              <description>ch23 enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA24</name>
+              <description>ch24 enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA25</name>
+              <description>ch25 enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA26</name>
+              <description>ch26 enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA27</name>
+              <description>ch27 enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA28</name>
+              <description>ch28 enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA29</name>
+              <description>ch29 enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA30</name>
+              <description>ch30 enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA31</name>
+              <description>ch31 enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH_ENA_AD0_SET</name>
+          <description>channel enable set register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_SET0</name>
+              <description>ch0 set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET1</name>
+              <description>ch1 set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET2</name>
+              <description>ch2 set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET3</name>
+              <description>ch3 set</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET4</name>
+              <description>ch4 set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET5</name>
+              <description>ch5 set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET6</name>
+              <description>ch6 set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET7</name>
+              <description>ch7 set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET8</name>
+              <description>ch8 set</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET9</name>
+              <description>ch9 set</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET10</name>
+              <description>ch10 set</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET11</name>
+              <description>ch11 set</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET12</name>
+              <description>ch12 set</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET13</name>
+              <description>ch13 set</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET14</name>
+              <description>ch14 set</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET15</name>
+              <description>ch15 set</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET16</name>
+              <description>ch16 set</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET17</name>
+              <description>ch17 set</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET18</name>
+              <description>ch18 set</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET19</name>
+              <description>ch19 set</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET20</name>
+              <description>ch20 set</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET21</name>
+              <description>ch21 set</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET22</name>
+              <description>ch22 set</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET23</name>
+              <description>ch23 set</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET24</name>
+              <description>ch24 set</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET25</name>
+              <description>ch25 set</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET26</name>
+              <description>ch26 set</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET27</name>
+              <description>ch27 set</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET28</name>
+              <description>ch28 set</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET29</name>
+              <description>ch29 set</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET30</name>
+              <description>ch30 set</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET31</name>
+              <description>ch31 set</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH_ENA_AD0_CLR</name>
+          <description>channel enable clear register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_CLR0</name>
+              <description>ch0 clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR1</name>
+              <description>ch1 clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR2</name>
+              <description>ch2 clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR3</name>
+              <description>ch3 clear</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR4</name>
+              <description>ch4 clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR5</name>
+              <description>ch5 clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR6</name>
+              <description>ch6 clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR7</name>
+              <description>ch7 clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR8</name>
+              <description>ch8 clear</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR9</name>
+              <description>ch9 clear</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR10</name>
+              <description>ch10 clear</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR11</name>
+              <description>ch11 clear</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR12</name>
+              <description>ch12 clear</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR13</name>
+              <description>ch13 clear</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR14</name>
+              <description>ch14 clear</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR15</name>
+              <description>ch15 clear</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR16</name>
+              <description>ch16 clear</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR17</name>
+              <description>ch17 clear</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR18</name>
+              <description>ch18 clear</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR19</name>
+              <description>ch19 clear</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR20</name>
+              <description>ch20 clear</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR21</name>
+              <description>ch21 clear</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR22</name>
+              <description>ch22 clear</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR23</name>
+              <description>ch23 clear</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR24</name>
+              <description>ch24 clear</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR25</name>
+              <description>ch25 clear</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR26</name>
+              <description>ch26 clear</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR27</name>
+              <description>ch27 clear</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR28</name>
+              <description>ch28 clear</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR29</name>
+              <description>ch29 clear</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR30</name>
+              <description>ch30 clear</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR31</name>
+              <description>ch31 clear</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH_ENA_AD1</name>
+          <description>channel enable register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_ENA32</name>
+              <description>ch32 enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA33</name>
+              <description>ch33 enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA34</name>
+              <description>ch34 enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA35</name>
+              <description>ch35 enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA36</name>
+              <description>ch36 enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA37</name>
+              <description>ch37 enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA38</name>
+              <description>ch38 enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA39</name>
+              <description>ch39 enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA40</name>
+              <description>ch40 enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA41</name>
+              <description>ch41 enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA42</name>
+              <description>ch42 enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA43</name>
+              <description>ch43 enable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA44</name>
+              <description>ch44 enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA45</name>
+              <description>ch45 enable</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA46</name>
+              <description>ch46 enable</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA47</name>
+              <description>ch47 enable</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA48</name>
+              <description>ch48 enable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_ENA49</name>
+              <description>ch49 enable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH_ENA_AD1_SET</name>
+          <description>channel enable set register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_SET32</name>
+              <description>ch32 set</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET33</name>
+              <description>ch33 set</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET34</name>
+              <description>ch34 set</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET35</name>
+              <description>ch35 set</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET36</name>
+              <description>ch36 set</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET37</name>
+              <description>ch37 set</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET38</name>
+              <description>ch38 set</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET39</name>
+              <description>ch39 set</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET40</name>
+              <description>ch40 set</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET41</name>
+              <description>ch41 set</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET42</name>
+              <description>ch42 set</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET43</name>
+              <description>ch43 set</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET44</name>
+              <description>ch44 set</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET45</name>
+              <description>ch45 set</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET46</name>
+              <description>ch46 set</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET47</name>
+              <description>ch47 set</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET48</name>
+              <description>ch48 set</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_SET49</name>
+              <description>ch49 set</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH_ENA_AD1_CLR</name>
+          <description>channel enable clear register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_CLR32</name>
+              <description>ch32 clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR33</name>
+              <description>ch33 clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR34</name>
+              <description>ch34 clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR35</name>
+              <description>ch35 clear</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR36</name>
+              <description>ch36 clear</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR37</name>
+              <description>ch37 clear</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR38</name>
+              <description>ch38 clear</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR39</name>
+              <description>ch39 clear</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR40</name>
+              <description>ch40 clear</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR41</name>
+              <description>ch41 clear</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR42</name>
+              <description>ch42 clear</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR43</name>
+              <description>ch43 clear</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR44</name>
+              <description>ch44 clear</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR45</name>
+              <description>ch45 clear</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR46</name>
+              <description>ch46 clear</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR47</name>
+              <description>ch47 clear</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR48</name>
+              <description>ch48 clear</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_CLR49</name>
+              <description>ch49 clear</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH0_EVT_ID</name>
+          <description>channel0 event id register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_EVT_ID</name>
+              <description>ch0_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH0_TASK_ID</name>
+          <description>channel0 task id register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_TASK_ID</name>
+              <description>ch0_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH1_EVT_ID</name>
+          <description>channel1 event id register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH1_EVT_ID</name>
+              <description>ch1_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH1_TASK_ID</name>
+          <description>channel1 task id register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH1_TASK_ID</name>
+              <description>ch1_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH2_EVT_ID</name>
+          <description>channel2 event id register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH2_EVT_ID</name>
+              <description>ch2_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH2_TASK_ID</name>
+          <description>channel2 task id register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH2_TASK_ID</name>
+              <description>ch2_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH3_EVT_ID</name>
+          <description>channel3 event id register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH3_EVT_ID</name>
+              <description>ch3_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH3_TASK_ID</name>
+          <description>channel3 task id register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH3_TASK_ID</name>
+              <description>ch3_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH4_EVT_ID</name>
+          <description>channel4 event id register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH4_EVT_ID</name>
+              <description>ch4_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH4_TASK_ID</name>
+          <description>channel4 task id register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH4_TASK_ID</name>
+              <description>ch4_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH5_EVT_ID</name>
+          <description>channel5 event id register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH5_EVT_ID</name>
+              <description>ch5_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH5_TASK_ID</name>
+          <description>channel5 task id register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH5_TASK_ID</name>
+              <description>ch5_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH6_EVT_ID</name>
+          <description>channel6 event id register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH6_EVT_ID</name>
+              <description>ch6_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH6_TASK_ID</name>
+          <description>channel6 task id register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH6_TASK_ID</name>
+              <description>ch6_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH7_EVT_ID</name>
+          <description>channel7 event id register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH7_EVT_ID</name>
+              <description>ch7_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH7_TASK_ID</name>
+          <description>channel7 task id register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH7_TASK_ID</name>
+              <description>ch7_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH8_EVT_ID</name>
+          <description>channel8 event id register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH8_EVT_ID</name>
+              <description>ch8_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH8_TASK_ID</name>
+          <description>channel8 task id register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH8_TASK_ID</name>
+              <description>ch8_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH9_EVT_ID</name>
+          <description>channel9 event id register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH9_EVT_ID</name>
+              <description>ch9_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH9_TASK_ID</name>
+          <description>channel9 task id register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH9_TASK_ID</name>
+              <description>ch9_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH10_EVT_ID</name>
+          <description>channel10 event id register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH10_EVT_ID</name>
+              <description>ch10_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH10_TASK_ID</name>
+          <description>channel10 task id register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH10_TASK_ID</name>
+              <description>ch10_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH11_EVT_ID</name>
+          <description>channel11 event id register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH11_EVT_ID</name>
+              <description>ch11_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH11_TASK_ID</name>
+          <description>channel11 task id register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH11_TASK_ID</name>
+              <description>ch11_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH12_EVT_ID</name>
+          <description>channel12 event id register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH12_EVT_ID</name>
+              <description>ch12_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH12_TASK_ID</name>
+          <description>channel12 task id register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH12_TASK_ID</name>
+              <description>ch12_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH13_EVT_ID</name>
+          <description>channel13 event id register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH13_EVT_ID</name>
+              <description>ch13_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH13_TASK_ID</name>
+          <description>channel13 task id register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH13_TASK_ID</name>
+              <description>ch13_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH14_EVT_ID</name>
+          <description>channel14 event id register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH14_EVT_ID</name>
+              <description>ch14_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH14_TASK_ID</name>
+          <description>channel14 task id register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH14_TASK_ID</name>
+              <description>ch14_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH15_EVT_ID</name>
+          <description>channel15 event id register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH15_EVT_ID</name>
+              <description>ch15_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH15_TASK_ID</name>
+          <description>channel15 task id register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH15_TASK_ID</name>
+              <description>ch15_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH16_EVT_ID</name>
+          <description>channel16 event id register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH16_EVT_ID</name>
+              <description>ch16_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH16_TASK_ID</name>
+          <description>channel16 task id register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH16_TASK_ID</name>
+              <description>ch16_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH17_EVT_ID</name>
+          <description>channel17 event id register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH17_EVT_ID</name>
+              <description>ch17_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH17_TASK_ID</name>
+          <description>channel17 task id register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH17_TASK_ID</name>
+              <description>ch17_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH18_EVT_ID</name>
+          <description>channel18 event id register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH18_EVT_ID</name>
+              <description>ch18_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH18_TASK_ID</name>
+          <description>channel18 task id register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH18_TASK_ID</name>
+              <description>ch18_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH19_EVT_ID</name>
+          <description>channel19 event id register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH19_EVT_ID</name>
+              <description>ch19_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH19_TASK_ID</name>
+          <description>channel19 task id register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH19_TASK_ID</name>
+              <description>ch19_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH20_EVT_ID</name>
+          <description>channel20 event id register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH20_EVT_ID</name>
+              <description>ch20_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH20_TASK_ID</name>
+          <description>channel20 task id register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH20_TASK_ID</name>
+              <description>ch20_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH21_EVT_ID</name>
+          <description>channel21 event id register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH21_EVT_ID</name>
+              <description>ch21_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH21_TASK_ID</name>
+          <description>channel21 task id register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH21_TASK_ID</name>
+              <description>ch21_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH22_EVT_ID</name>
+          <description>channel22 event id register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH22_EVT_ID</name>
+              <description>ch22_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH22_TASK_ID</name>
+          <description>channel22 task id register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH22_TASK_ID</name>
+              <description>ch22_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH23_EVT_ID</name>
+          <description>channel23 event id register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH23_EVT_ID</name>
+              <description>ch23_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH23_TASK_ID</name>
+          <description>channel23 task id register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH23_TASK_ID</name>
+              <description>ch23_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH24_EVT_ID</name>
+          <description>channel24 event id register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH24_EVT_ID</name>
+              <description>ch24_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH24_TASK_ID</name>
+          <description>channel24 task id register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH24_TASK_ID</name>
+              <description>ch24_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH25_EVT_ID</name>
+          <description>channel25 event id register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH25_EVT_ID</name>
+              <description>ch25_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH25_TASK_ID</name>
+          <description>channel25 task id register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH25_TASK_ID</name>
+              <description>ch25_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH26_EVT_ID</name>
+          <description>channel26 event id register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH26_EVT_ID</name>
+              <description>ch26_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH26_TASK_ID</name>
+          <description>channel26 task id register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH26_TASK_ID</name>
+              <description>ch26_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH27_EVT_ID</name>
+          <description>channel27 event id register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH27_EVT_ID</name>
+              <description>ch27_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH27_TASK_ID</name>
+          <description>channel27 task id register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH27_TASK_ID</name>
+              <description>ch27_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH28_EVT_ID</name>
+          <description>channel28 event id register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH28_EVT_ID</name>
+              <description>ch28_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH28_TASK_ID</name>
+          <description>channel28 task id register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH28_TASK_ID</name>
+              <description>ch28_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH29_EVT_ID</name>
+          <description>channel29 event id register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH29_EVT_ID</name>
+              <description>ch29_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH29_TASK_ID</name>
+          <description>channel29 task id register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH29_TASK_ID</name>
+              <description>ch29_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH30_EVT_ID</name>
+          <description>channel30 event id register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH30_EVT_ID</name>
+              <description>ch30_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH30_TASK_ID</name>
+          <description>channel30 task id register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH30_TASK_ID</name>
+              <description>ch30_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH31_EVT_ID</name>
+          <description>channel31 event id register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH31_EVT_ID</name>
+              <description>ch31_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH31_TASK_ID</name>
+          <description>channel31 task id register</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH31_TASK_ID</name>
+              <description>ch31_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH32_EVT_ID</name>
+          <description>channel32 event id register</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH32_EVT_ID</name>
+              <description>ch32_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH32_TASK_ID</name>
+          <description>channel32 task id register</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH32_TASK_ID</name>
+              <description>ch32_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH33_EVT_ID</name>
+          <description>channel33 event id register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH33_EVT_ID</name>
+              <description>ch33_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH33_TASK_ID</name>
+          <description>channel33 task id register</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH33_TASK_ID</name>
+              <description>ch33_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH34_EVT_ID</name>
+          <description>channel34 event id register</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH34_EVT_ID</name>
+              <description>ch34_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH34_TASK_ID</name>
+          <description>channel34 task id register</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH34_TASK_ID</name>
+              <description>ch34_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH35_EVT_ID</name>
+          <description>channel35 event id register</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH35_EVT_ID</name>
+              <description>ch35_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH35_TASK_ID</name>
+          <description>channel35 task id register</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH35_TASK_ID</name>
+              <description>ch35_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH36_EVT_ID</name>
+          <description>channel36 event id register</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH36_EVT_ID</name>
+              <description>ch36_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH36_TASK_ID</name>
+          <description>channel36 task id register</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH36_TASK_ID</name>
+              <description>ch36_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH37_EVT_ID</name>
+          <description>channel37 event id register</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH37_EVT_ID</name>
+              <description>ch37_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH37_TASK_ID</name>
+          <description>channel37 task id register</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH37_TASK_ID</name>
+              <description>ch37_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH38_EVT_ID</name>
+          <description>channel38 event id register</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH38_EVT_ID</name>
+              <description>ch38_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH38_TASK_ID</name>
+          <description>channel38 task id register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH38_TASK_ID</name>
+              <description>ch38_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH39_EVT_ID</name>
+          <description>channel39 event id register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH39_EVT_ID</name>
+              <description>ch39_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH39_TASK_ID</name>
+          <description>channel39 task id register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH39_TASK_ID</name>
+              <description>ch39_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH40_EVT_ID</name>
+          <description>channel40 event id register</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH40_EVT_ID</name>
+              <description>ch40_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH40_TASK_ID</name>
+          <description>channel40 task id register</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH40_TASK_ID</name>
+              <description>ch40_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH41_EVT_ID</name>
+          <description>channel41 event id register</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH41_EVT_ID</name>
+              <description>ch41_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH41_TASK_ID</name>
+          <description>channel41 task id register</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH41_TASK_ID</name>
+              <description>ch41_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH42_EVT_ID</name>
+          <description>channel42 event id register</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH42_EVT_ID</name>
+              <description>ch42_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH42_TASK_ID</name>
+          <description>channel42 task id register</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH42_TASK_ID</name>
+              <description>ch42_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH43_EVT_ID</name>
+          <description>channel43 event id register</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH43_EVT_ID</name>
+              <description>ch43_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH43_TASK_ID</name>
+          <description>channel43 task id register</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH43_TASK_ID</name>
+              <description>ch43_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH44_EVT_ID</name>
+          <description>channel44 event id register</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH44_EVT_ID</name>
+              <description>ch44_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH44_TASK_ID</name>
+          <description>channel44 task id register</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH44_TASK_ID</name>
+              <description>ch44_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH45_EVT_ID</name>
+          <description>channel45 event id register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH45_EVT_ID</name>
+              <description>ch45_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH45_TASK_ID</name>
+          <description>channel45 task id register</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH45_TASK_ID</name>
+              <description>ch45_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH46_EVT_ID</name>
+          <description>channel46 event id register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH46_EVT_ID</name>
+              <description>ch46_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH46_TASK_ID</name>
+          <description>channel46 task id register</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH46_TASK_ID</name>
+              <description>ch46_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH47_EVT_ID</name>
+          <description>channel47 event id register</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH47_EVT_ID</name>
+              <description>ch47_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH47_TASK_ID</name>
+          <description>channel47 task id register</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH47_TASK_ID</name>
+              <description>ch47_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH48_EVT_ID</name>
+          <description>channel48 event id register</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH48_EVT_ID</name>
+              <description>ch48_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH48_TASK_ID</name>
+          <description>channel48 task id register</description>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH48_TASK_ID</name>
+              <description>ch48_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH49_EVT_ID</name>
+          <description>channel49 event id register</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH49_EVT_ID</name>
+              <description>ch49_evt_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CH49_TASK_ID</name>
+          <description>channel49 task id register</description>
+          <addressOffset>0x1A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH49_TASK_ID</name>
+              <description>ch49_task_id</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_EN</name>
+          <description>etm clock enable register</description>
+          <addressOffset>0x1A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>clock enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>etm date register</description>
+          <addressOffset>0x1AC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02203092</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI0</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI0</groupName>
+      <baseAddress>0x60002000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x138</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SPI_MEM_CMD</name>
+          <description>SPI0 FSM status register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_MST_ST</name>
+              <description>The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST</name>
+              <description>The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR</name>
+              <description>SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL</name>
+          <description>SPI0 control register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x802C200C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_WDUMMY_DQS_ALWAYS_OUT</name>
+              <description>In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WDUMMY_ALWAYS_OUT</name>
+              <description>In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDUMMY_RIN</name>
+              <description>In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDUMMY_WOUT</name>
+              <description>In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_OCT</name>
+              <description>Apply 8 signals during write-data phase 1:enable 0: disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_OCT</name>
+              <description>Apply 8 signals during read-data phase 1:enable 0: disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_OCT</name>
+              <description>Apply 8 signals during address phase 1:enable 0: disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCMD_OCT</name>
+              <description>Apply 8 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FASTRD_MODE</name>
+              <description>This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_DIO</name>
+              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_QIO</name>
+              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DQS_IE_ALWAYS_ON</name>
+              <description>When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DATA_IE_ALWAYS_ON</name>
+              <description>When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL1</name>
+          <description>SPI0 control1 register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x28E00000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_AR_SIZE0_1_SUPPORT_EN</name>
+              <description>1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_AW_SIZE0_1_SUPPORT_EN</name>
+              <description>1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_AXI_RDATA_BACK_FAST</name>
+              <description>1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RRESP_ECC_ERR_EN</name>
+              <description>1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AR_SPLICE_EN</name>
+              <description>Set this bit to enable AXI Read Splice-transfer.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AW_SPLICE_EN</name>
+              <description>Set this bit to enable AXI Write Splice-transfer.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RAM0_EN</name>
+              <description>When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be accessed at the same time.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DUAL_RAM_EN</name>
+              <description>Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FAST_WRITE_EN</name>
+              <description>Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in  tx_bus_fifo_l2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RXFIFO_RST</name>
+              <description>The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI.  Set this bit to reset these FIFO.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_TXFIFO_RST</name>
+              <description>The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL2</name>
+          <description>SPI0 control2 register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002C21</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CS_SETUP_TIME</name>
+              <description>(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_HOLD_TIME</name>
+              <description>SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_CS_HOLD_TIME</name>
+              <description>SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_SKIP_PAGE_CORNER</name>
+              <description>1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_16TO18_BYTE_EN</name>
+              <description>Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SPLIT_TRANS_EN</name>
+              <description>Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_HOLD_DELAY</name>
+              <description>These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SYNC_RESET</name>
+              <description>The spi0_mst_st and spi0_slv_st will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CLOCK</name>
+          <description>SPI clock division control register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLK_EQU_SYSCLK</name>
+              <description>1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER</name>
+          <description>SPI0 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CK_OUT_EDGE</name>
+              <description>The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER1</name>
+          <description>SPI0 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000047</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DBYTELEN</name>
+              <description>SPI0 USR_CMD read or write data byte length -1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER2</name>
+          <description>SPI0 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_COMMAND_VALUE</name>
+              <description>The value of  command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_RD_STATUS</name>
+          <description>SPI0 read control register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MISC</name>
+          <description>SPI0 misc register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_FSUB_PIN</name>
+              <description>For SPI0,  flash is connected to SUBPINs.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SSUB_PIN</name>
+              <description>For SPI0,  sram is connected to SUBPINs.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CK_IDLE_EDGE</name>
+              <description>1: SPI_CLK line is high when idle     0: spi clk line is low when idle</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_KEEP_ACTIVE</name>
+              <description>SPI_CS line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CACHE_FCTRL</name>
+          <description>SPI0 bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC0000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_AXI_REQ_EN</name>
+              <description>For SPI0, AXI master access enable, 1: enable, 0:disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_USR_ADDR_4BYTE</name>
+              <description>For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_FLASH_USR_CMD</name>
+              <description>For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_DUAL</name>
+              <description>For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_DUAL</name>
+              <description>For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_DUAL</name>
+              <description>For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_QUAD</name>
+              <description>For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_QUAD</name>
+              <description>For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_QUAD</name>
+              <description>For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SAME_AW_AR_ADDR_CHK_EN</name>
+              <description>Set this bit to check AXI read/write the same address region.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_CLOSE_AXI_INF_EN</name>
+              <description>Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CACHE_SCTRL</name>
+          <description>SPI0 external RAM control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0055C070</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CACHE_USR_SADDR_4BYTE</name>
+              <description>For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_SRAM_DIO</name>
+              <description>For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_SRAM_QIO</name>
+              <description>For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_WR_SRAM_DUMMY</name>
+              <description>For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_RD_SRAM_DUMMY</name>
+              <description>For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_RCMD</name>
+              <description>For SPI0, In the external RAM mode cache read external RAM for user define command.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SRAM_RDUMMY_CYCLELEN</name>
+              <description>For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SRAM_ADDR_BITLEN</name>
+              <description>For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_WCMD</name>
+              <description>For SPI0, In the external RAM mode cache write sram for user define command</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SRAM_OCT</name>
+              <description>reserved</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SRAM_WDUMMY_CYCLELEN</name>
+              <description>For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SRAM_CMD</name>
+          <description>SPI0 external RAM mode control register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC0400000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_SCLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SWB_MODE</name>
+              <description>Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDIN_DUAL</name>
+              <description>For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDOUT_DUAL</name>
+              <description>For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SADDR_DUAL</name>
+              <description>For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDIN_QUAD</name>
+              <description>For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDOUT_QUAD</name>
+              <description>For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SADDR_QUAD</name>
+              <description>For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCMD_QUAD</name>
+              <description>For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDIN_OCT</name>
+              <description>For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDOUT_OCT</name>
+              <description>For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SADDR_OCT</name>
+              <description>For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCMD_OCT</name>
+              <description>For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDUMMY_RIN</name>
+              <description>In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDUMMY_WOUT</name>
+              <description>In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT</name>
+              <description>In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_WDUMMY_ALWAYS_OUT</name>
+              <description>In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DQS_IE_ALWAYS_ON</name>
+              <description>When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DATA_IE_ALWAYS_ON</name>
+              <description>When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SRAM_DRD_CMD</name>
+          <description>SPI0 external RAM DDR read command control register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE</name>
+              <description>For SPI0,When cache mode is enable it is the read command value of command phase for sram.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN</name>
+              <description>For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SRAM_DWR_CMD</name>
+          <description>SPI0 external RAM DDR write command control register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE</name>
+              <description>For SPI0,When cache mode is enable it is the write command value of command phase for sram.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN</name>
+              <description>For SPI0,When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SRAM_CLK</name>
+          <description>SPI0 external RAM clock control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_SCLKCNT_L</name>
+              <description>For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCLKCNT_H</name>
+              <description>For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCLKCNT_N</name>
+              <description>For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCLK_EQU_SYSCLK</name>
+              <description>For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_FSM</name>
+          <description>SPI0 FSM status register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_LOCK_DELAY_TIME</name>
+              <description>The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_ENA</name>
+          <description>SPI0 interrupt enable register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_REJECT_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_RADDR_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WADDR_ERR_INT__ENA</name>
+              <description>The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_CLR</name>
+          <description>SPI0 interrupt clear register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_REJECT_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_RADDR_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WADDR_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_RAW</name>
+          <description>SPI0 interrupt raw register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_REJECT_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_RADDR_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WADDR_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_ST</name>
+          <description>SPI0 interrupt status register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_INT_ST</name>
+              <description>The status bit for SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_REJECT_INT_ST</name>
+              <description>The status bit for SPI_MEM_PMS_REJECT_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_RADDR_ERR_INT_ST</name>
+              <description>The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WR_FLASH_ERR_INT_ST</name>
+              <description>The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WADDR_ERR_INT_ST</name>
+              <description>The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DDR</name>
+          <description>SPI0 flash DDR mode control register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003020</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_DDR_EN</name>
+              <description>1: in DDR mode,  0 in SDR mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_VAR_DUMMY</name>
+              <description>Set the bit to enable variable dummy cycle in spi DDR mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_RDAT_SWP</name>
+              <description>Set the bit to reorder rx data of the word in spi DDR mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_WDAT_SWP</name>
+              <description>Set the bit to reorder tx data of the word in spi DDR mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_CMD_DIS</name>
+              <description>the bit is used to disable dual edge in command phase when DDR mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OUTMINBYTELEN</name>
+              <description>It is the minimum output data length in the panda device.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_TX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_RX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_USR_DDR_DQS_THD</name>
+              <description>The delay number of data strobe which from memory based on SPI clock.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_DQS_LOOP</name>
+              <description>1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_EN</name>
+              <description>Set this bit to enable the differential SPI_CLK#.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DQS_CA_IN</name>
+              <description>Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_DUMMY_2X</name>
+              <description>Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_INV</name>
+              <description>Set this bit to invert SPI_DIFF when accesses to flash. .</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OCTA_RAM_ADDR</name>
+              <description>Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_CA</name>
+              <description>Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DDR</name>
+          <description>SPI0 external RAM DDR mode control register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003020</resetValue>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>1: in DDR mode,  0 in SDR mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_VAR_DUMMY</name>
+              <description>Set the bit to enable variable dummy cycle in spi DDR mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RDAT_SWP</name>
+              <description>Set the bit to reorder rx data of the word in spi DDR mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDAT_SWP</name>
+              <description>Set the bit to reorder tx data of the word in spi DDR mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMD_DIS</name>
+              <description>the bit is used to disable dual edge in command phase when DDR mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_OUTMINBYTELEN</name>
+              <description>It is the minimum output data length in the DDR psram.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_TX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_RX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_USR_DDR_DQS_THD</name>
+              <description>The delay number of data strobe which from memory based on SPI clock.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DQS_LOOP</name>
+              <description>1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CLK_DIFF_EN</name>
+              <description>Set this bit to enable the differential SPI_CLK#.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DQS_CA_IN</name>
+              <description>Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_HYPERBUS_DUMMY_2X</name>
+              <description>Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CLK_DIFF_INV</name>
+              <description>Set this bit to invert SPI_DIFF when accesses to external RAM. .</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_OCTA_RAM_ADDR</name>
+              <description>Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_HYPERBUS_CA</name>
+              <description>Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_FMEM_PMS%s_ATTR</name>
+          <description>MSPI flash ACE section %s attribute register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_PMS_RD_ATTR</name>
+              <description>1: SPI1 flash ACE section %s read accessible. 0: Not allowed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_PMS_WR_ATTR</name>
+              <description>1: SPI1 flash ACE section %s write accessible. 0: Not allowed.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_PMS_ECC</name>
+              <description>SPI1 flash ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_FMEM_PMS%s_ADDR</name>
+          <description>SPI1 flash ACE section %s start address register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>SPI1 flash ACE section %s start address value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_FMEM_PMS%s_SIZE</name>
+          <description>SPI1 flash ACE section %s start address register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_PMS_SIZE</name>
+              <description>SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_SMEM_PMS%s_ATTR</name>
+          <description>SPI1 flash ACE section %s start address register</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_PMS_RD_ATTR</name>
+              <description>1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_PMS_WR_ATTR</name>
+              <description>1: SPI1 external RAM ACE section %s write accessible. 0: Not allowed.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_PMS_ECC</name>
+              <description>SPI1 external RAM ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_SMEM_PMS%s_ADDR</name>
+          <description>SPI1 external RAM ACE section %s start address register</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>SPI1 external RAM ACE section %s start address value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_SMEM_PMS%s_SIZE</name>
+          <description>SPI1 external RAM ACE section %s start address register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_PMS_SIZE</name>
+              <description>SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_PMS_REJECT</name>
+          <description>SPI1 access reject register</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_ADDR</name>
+              <description>This bits show the first SPI1 access error address. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PM_EN</name>
+              <description>Set this bit to enable SPI0/1 transfer permission control function.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_LD</name>
+              <description>1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_ST</name>
+              <description>1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_MULTI_HIT</name>
+              <description>1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_IVD</name>
+              <description>1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_ECC_CTRL</name>
+          <description>MSPI ECC control register</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01005000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_ECC_ERR_INT_NUM</name>
+              <description>Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_ECC_ERR_INT_EN</name>
+              <description>Set this bit to calculate the error times of MSPI ECC read when accesses to flash.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_PAGE_SIZE</name>
+              <description>Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_ECC_ADDR_EN</name>
+              <description>Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_ECC_ADDR_EN</name>
+              <description>Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN</name>
+              <description>1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_BITS</name>
+              <description>Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_ECC_ERR_ADDR</name>
+          <description>MSPI ECC error address register</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_ECC_ERR_ADDR</name>
+              <description>This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_CNT</name>
+              <description>This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_AXI_ERR_ADDR</name>
+          <description>SPI0 AXI request error address.</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFC000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_AXI_ERR_ADDR</name>
+              <description>This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ALL_FIFO_EMPTY</name>
+              <description>The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_RDATA_AFIFO_REMPTY</name>
+              <description>1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_RADDR_AFIFO_REMPTY</name>
+              <description>1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_WDATA_AFIFO_REMPTY</name>
+              <description>1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_WBLEN_AFIFO_REMPTY</name>
+              <description>1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_ALL_AXI_TRANS_AFIFO_EMPTY</name>
+              <description>This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_ECC_CTRL</name>
+          <description>MSPI ECC control register</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00080000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_ECC_ERR_INT_EN</name>
+              <description>Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_PAGE_SIZE</name>
+              <description>Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_ADDR_EN</name>
+              <description>Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_TIMING_CALI</name>
+          <description>SPI0 flash timing calibration register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_TIMING_CLK_ENA</name>
+              <description>The bit is used to enable timing adjust clock for all reading operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_TIMING_CALI</name>
+              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_EXTRA_DUMMY_CYCLELEN</name>
+              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DLL_TIMING_CALI</name>
+              <description>Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UPDATE</name>
+              <description>Set this bit to update delay mode, delay num and extra dummy in MSPI.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DIN_MODE</name>
+          <description>MSPI flash input timing delay mode control register</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_DIN0_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN1_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN2_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN3_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN4_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN5_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN6_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN7_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DINS_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DIN_NUM</name>
+          <description>MSPI flash input timing delay number control register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_DIN0_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN1_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN2_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN3_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN4_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN5_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN6_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN7_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DINS_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DOUT_MODE</name>
+          <description>MSPI flash output timing adjustment control register</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_DOUT0_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT1_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT2_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT3_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT4_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT5_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT6_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT7_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUTS_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_TIMING_CALI</name>
+          <description>MSPI external RAM timing calibration register</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_TIMING_CLK_ENA</name>
+              <description>For sram, the bit is used to enable timing adjust clock for all reading operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_TIMING_CALI</name>
+              <description>For sram, the bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_EXTRA_DUMMY_CYCLELEN</name>
+              <description>For sram, add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DLL_TIMING_CALI</name>
+              <description>Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DIN_MODE</name>
+          <description>MSPI external RAM input timing delay mode control register</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_DIN0_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN1_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN2_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN3_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN4_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN5_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN6_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN7_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DINS_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DIN_NUM</name>
+          <description>MSPI external RAM input timing delay number control register</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_DIN0_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN1_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN2_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN3_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN4_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN5_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN6_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN7_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DINS_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DOUT_MODE</name>
+          <description>MSPI external RAM output timing adjustment control register</description>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_DOUT0_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT1_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT2_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT3_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT4_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT5_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT6_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT7_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUTS_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_AC</name>
+          <description>MSPI external RAM ECC and SPI CS timing control register</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x8000B084</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_CS_SETUP</name>
+              <description>For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_HOLD</name>
+              <description>For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_SETUP_TIME</name>
+              <description>For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_HOLD_TIME</name>
+              <description>For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_CS_HOLD_TIME</name>
+              <description>SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_SKIP_PAGE_CORNER</name>
+              <description>1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_16TO18_BYTE_EN</name>
+              <description>Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_HOLD_DELAY</name>
+              <description>These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_SPLIT_TRANS_EN</name>
+              <description>Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CLOCK_GATE</name>
+          <description>SPI0 clock gate register</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_PLAIN_BASE</name>
+          <description>The base address of the memory that stores plaintext in Manual Encryption</description>
+          <addressOffset>0x300</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_PLAIN</name>
+              <description>This field is only used to generate include file in c case. This field is useless. Please do not use this field.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_LINESIZE</name>
+          <description>Manual Encryption Line-Size register</description>
+          <addressOffset>0x340</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_LINESIZE</name>
+              <description>This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_DESTINATION</name>
+          <description>Manual Encryption destination register</description>
+          <addressOffset>0x344</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_DESTINATION</name>
+              <description>This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_PHYSICAL_ADDRESS</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x348</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_PHYSICAL_ADDRESS</name>
+              <description>This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_TRIGGER</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x34C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_TRIGGER</name>
+              <description>Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_RELEASE</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x350</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_RELEASE</name>
+              <description>Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_DESTROY</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x354</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_DESTROY</name>
+              <description>Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_STATE</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x358</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_STATE</name>
+              <description>This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_DATE</name>
+          <description>Manual Encryption version register</description>
+          <addressOffset>0x35C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20201010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_XTS_DATE</name>
+              <description>This bits stores the last modified-time of manual encryption feature.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MMU_ITEM_CONTENT</name>
+          <description>MSPI-MMU item content register</description>
+          <addressOffset>0x37C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000037C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MMU_ITEM_CONTENT</name>
+              <description>MSPI-MMU item content</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MMU_ITEM_INDEX</name>
+          <description>MSPI-MMU item index register</description>
+          <addressOffset>0x380</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MMU_ITEM_INDEX</name>
+              <description>MSPI-MMU item index</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MMU_POWER_CTRL</name>
+          <description>MSPI MMU power control register</description>
+          <addressOffset>0x384</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x13200004</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MMU_MEM_FORCE_ON</name>
+              <description>Set this bit to enable mmu-memory clock force on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MMU_MEM_FORCE_PD</name>
+              <description>Set this bit to force mmu-memory powerdown</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MMU_MEM_FORCE_PU</name>
+              <description>Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MMU_PAGE_SIZE</name>
+              <description>0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AUX_CTRL</name>
+              <description>MMU PSRAM aux control register</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RDN_ENA</name>
+              <description>ECO register enable bit</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RDN_RESULT</name>
+              <description>MSPI module clock domain and AXI clock domain ECO register result register</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DPA_CTRL</name>
+          <description>SPI memory cryption DPA register</description>
+          <addressOffset>0x388</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CRYPT_SECURITY_LEVEL</name>
+              <description>Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CRYPT_CALC_D_DPA_EN</name>
+              <description>Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CRYPT_DPA_SELECT_REGISTER</name>
+              <description>1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REGISTERRND_ECO_HIGH</name>
+          <description>MSPI ECO high register</description>
+          <addressOffset>0x3F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000037C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_REGISTERRND_ECO_HIGH</name>
+              <description>ECO high register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REGISTERRND_ECO_LOW</name>
+          <description>MSPI ECO low register</description>
+          <addressOffset>0x3F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000037C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_REGISTERRND_ECO_LOW</name>
+              <description>ECO low register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DATE</name>
+          <description>SPI0 version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02203030</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_DATE</name>
+              <description>SPI0 register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI1</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI1</groupName>
+      <baseAddress>0x60003000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xAC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SPI_MEM_CMD</name>
+          <description>SPI1 memory command register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_MST_ST</name>
+              <description>The current status of SPI1 master FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST</name>
+              <description>The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PE</name>
+              <description>In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_HPM</name>
+              <description>Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_RES</name>
+              <description>This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_DP</name>
+              <description>Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_CE</name>
+              <description>Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_BE</name>
+              <description>Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_SE</name>
+              <description>Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PP</name>
+              <description>Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_WRSR</name>
+              <description>Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_RDSR</name>
+              <description>Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_RDID</name>
+              <description>Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_WRDI</name>
+              <description>Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_WREN</name>
+              <description>Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_READ</name>
+              <description>Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_ADDR</name>
+          <description>SPI1 address register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_ADDR_VALUE</name>
+              <description>In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL</name>
+          <description>SPI1 control register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x002CA00C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_FDUMMY_RIN</name>
+              <description>In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDUMMY_WOUT</name>
+              <description>In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_OCT</name>
+              <description>Apply 8 signals during write-data phase 1:enable 0: disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_OCT</name>
+              <description>Apply 8 signals during read-data phase 1:enable 0: disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_OCT</name>
+              <description>Apply 8 signals during address phase 1:enable 0: disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCMD_OCT</name>
+              <description>Apply 8 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCS_CRC_EN</name>
+              <description>For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_TX_CRC_EN</name>
+              <description>For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FASTRD_MODE</name>
+              <description>This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RESANDRES</name>
+              <description>The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WRSR_2B</name>
+              <description>two bytes data will be written to status register when it is set. 1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_DIO</name>
+              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_QIO</name>
+              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL1</name>
+          <description>SPI1 control1 register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFC</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_HOLD_DLY_RES</name>
+              <description>After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL2</name>
+          <description>SPI1 control2 register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SYNC_RESET</name>
+              <description>The FSM will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CLOCK</name>
+          <description>SPI1 clock division control register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLK_EQU_SYSCLK</name>
+              <description>reserved</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER</name>
+          <description>SPI1 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FWRITE_DIO</name>
+              <description>In the write operations address phase and read-data phase apply 2 signals.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FWRITE_QIO</name>
+              <description>In the write operations address phase and read-data phase apply 4 signals.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DUMMY_IDLE</name>
+              <description>SPI clock is disable in dummy phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_ADDR</name>
+              <description>This bit enable the address phase of an operation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER1</name>
+          <description>SPI1 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000007</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER2</name>
+          <description>SPI1 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_COMMAND_VALUE</name>
+              <description>The value of  command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MOSI_DLEN</name>
+          <description>SPI1 send data bit length control register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_MOSI_DBITLEN</name>
+              <description>The length in bits of write-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MISO_DLEN</name>
+          <description>SPI1 receive data bit length control register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_MISO_DBITLEN</name>
+              <description>The length in bits of  read-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_RD_STATUS</name>
+          <description>SPI1 status register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_STATUS</name>
+              <description>The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MISC</name>
+          <description>SPI1 misc register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CS0_DIS</name>
+              <description>SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS1_DIS</name>
+              <description>SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_TX_CRC</name>
+          <description>SPI1 TX CRC data register.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>For SPI1, the value of crc32.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CACHE_FCTRL</name>
+          <description>SPI1 bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_CACHE_USR_ADDR_4BYTE</name>
+              <description>For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_DUAL</name>
+              <description>For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_DUAL</name>
+              <description>For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_DUAL</name>
+              <description>For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_QUAD</name>
+              <description>For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_QUAD</name>
+              <description>For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_QUAD</name>
+              <description>For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W0</name>
+          <description>SPI1 memory data buffer0</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W1</name>
+          <description>SPI1 memory data buffer1</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W2</name>
+          <description>SPI1 memory data buffer2</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W3</name>
+          <description>SPI1 memory data buffer3</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W4</name>
+          <description>SPI1 memory data buffer4</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W5</name>
+          <description>SPI1 memory data buffer5</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W6</name>
+          <description>SPI1 memory data buffer6</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W7</name>
+          <description>SPI1 memory data buffer7</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W8</name>
+          <description>SPI1 memory data buffer8</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W9</name>
+          <description>SPI1 memory data buffer9</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W10</name>
+          <description>SPI1 memory data buffer10</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W11</name>
+          <description>SPI1 memory data buffer11</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W12</name>
+          <description>SPI1 memory data buffer12</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W13</name>
+          <description>SPI1 memory data buffer13</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W14</name>
+          <description>SPI1 memory data buffer14</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W15</name>
+          <description>SPI1 memory data buffer15</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_FLASH_WAITI_CTRL</name>
+          <description>SPI1 wait idle control register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00050001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_WAITI_EN</name>
+              <description>1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_DUMMY</name>
+              <description>The dummy phase enable when wait flash idle (RDSR)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_ADDR_EN</name>
+              <description>1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_ADDR_CYCLELEN</name>
+              <description>When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_CMD_2B</name>
+              <description>1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_DUMMY_CYCLELEN</name>
+              <description>The dummy cycle length when wait flash idle(RDSR).</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_CMD</name>
+              <description>The command value to wait flash idle(RDSR).</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_FLASH_SUS_CTRL</name>
+          <description>SPI1 flash suspend control register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08002000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_FLASH_PER</name>
+              <description>program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PES</name>
+              <description>program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PER_WAIT_EN</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PES_WAIT_EN</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_PER_EN</name>
+              <description>Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PES_EN</name>
+              <description>Set this bit to enable Auto-suspending function.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PESR_END_MSK</name>
+              <description>The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_RD_SUS_2B</name>
+              <description>1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PER_END_EN</name>
+              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_EN</name>
+              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SUS_TIMEOUT_CNT</name>
+              <description>When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_FLASH_SUS_CMD</name>
+          <description>SPI1 flash suspend command register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00057575</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_FLASH_PES_COMMAND</name>
+              <description>Program/Erase suspend command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAIT_PESR_COMMAND</name>
+              <description>Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SUS_STATUS</name>
+          <description>SPI1 flash suspend status register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7A7A0000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_FLASH_SUS</name>
+              <description>The status of flash suspend, only used in SPI1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAIT_PESR_CMD_2B</name>
+              <description>1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_HPM_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_RES_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_DP_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PER_DLY_128</name>
+              <description>Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PES_DLY_128</name>
+              <description>Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SPI0_LOCK_EN</name>
+              <description>1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PESR_CMD_2B</name>
+              <description>1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PER_COMMAND</name>
+              <description>Program/Erase resume command.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_ENA</name>
+          <description>SPI1 interrupt enable register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_PER_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WPE_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_BROWN_OUT_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_CLR</name>
+          <description>SPI1 interrupt clear register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_PER_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WPE_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_BROWN_OUT_INT_CLR</name>
+              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_RAW</name>
+          <description>SPI1 interrupt raw register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_PER_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WPE_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_BROWN_OUT_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_ST</name>
+          <description>SPI1 interrupt status register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_PER_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WPE_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_BROWN_OUT_INT_ST</name>
+              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DDR</name>
+          <description>SPI1 DDR control register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_DDR_EN</name>
+              <description>1: in ddr mode,  0 in sdr mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_VAR_DUMMY</name>
+              <description>Set the bit to enable variable dummy cycle in spi ddr mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_RDAT_SWP</name>
+              <description>Set the bit to reorder rx data of the word in spi ddr mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_WDAT_SWP</name>
+              <description>Set the bit to reorder tx data of the word in spi ddr mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_CMD_DIS</name>
+              <description>the bit is used to disable dual edge in command phase when ddr mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OUTMINBYTELEN</name>
+              <description>It is the minimum output data length in the panda device.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_USR_DDR_DQS_THD</name>
+              <description>The delay number of data strobe which from memory based on SPI clock.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_DQS_LOOP</name>
+              <description>1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_EN</name>
+              <description>Set this bit to enable the differential SPI_CLK#.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DQS_CA_IN</name>
+              <description>Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_DUMMY_2X</name>
+              <description>Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_INV</name>
+              <description>Set this bit to invert SPI_DIFF when accesses to flash. .</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OCTA_RAM_ADDR</name>
+              <description>Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_CA</name>
+              <description>Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_TIMING_CALI</name>
+          <description>SPI1 timing control register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_TIMING_CALI</name>
+              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_EXTRA_DUMMY_CYCLELEN</name>
+              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CLOCK_GATE</name>
+          <description>SPI1 clk_gate register</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02202160</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI2</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI2</groupName>
+      <baseAddress>0x60081000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x98</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI2</name>
+        <value>72</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SPI_CMD</name>
+          <description>Command control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_CONF_BITLEN</name>
+              <description>Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_UPDATE</name>
+              <description>Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_ADDR</name>
+          <description>Address value register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_USR_ADDR_VALUE</name>
+              <description>Address to slave. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CTRL</name>
+          <description>SPI control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003C0000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_DUMMY_OUT</name>
+              <description>0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FADDR_DUAL</name>
+              <description>Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FADDR_QUAD</name>
+              <description>Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FADDR_OCT</name>
+              <description>Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FCMD_DUAL</name>
+              <description>Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FCMD_OCT</name>
+              <description>Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FREAD_OCT</name>
+              <description>In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_HOLD_POL</name>
+              <description>SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_WP_POL</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RD_BIT_ORDER</name>
+              <description>In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_WR_BIT_ORDER</name>
+              <description>In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CLOCK</name>
+          <description>SPI clock control register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80003043</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLKDIV_PRE</name>
+              <description>In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLK_EQU_SYSCLK</name>
+              <description>In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER</name>
+          <description>SPI USER control register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x800000C0</resetValue>
+          <fields>
+            <field>
+              <name>SPI_DOUTDIN</name>
+              <description>Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_QPI_MODE</name>
+              <description>Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_OPI_MODE</name>
+              <description>Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_TSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals. Can be configured in CONF state.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FWRITE_OCT</name>
+              <description>In the write operations read-data phase apply 8 signals. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_USR_CONF_NXT</name>
+              <description>1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SIO</name>
+              <description>Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_ADDR</name>
+              <description>This bit enable the address phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER1</name>
+          <description>SPI USER control register 1</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xB8410007</resetValue>
+          <fields>
+            <field>
+              <name>SPI_USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_WFULL_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_SETUP_TIME</name>
+              <description>(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_HOLD_TIME</name>
+              <description>delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER2</name>
+          <description>SPI USER control register 2</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x78000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_USR_COMMAND_VALUE</name>
+              <description>The value of  command. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_REMPTY_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MS_DLEN</name>
+          <description>SPI data bit length control register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MS_DATA_BITLEN</name>
+              <description>The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MISC</name>
+          <description>SPI misc register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003E</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CS0_DIS</name>
+              <description>SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS1_DIS</name>
+              <description>SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS2_DIS</name>
+              <description>SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS3_DIS</name>
+              <description>SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS4_DIS</name>
+              <description>SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS5_DIS</name>
+              <description>SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CK_DIS</name>
+              <description>1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MASTER_CS_POL</name>
+              <description>In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLK_DATA_DTR_EN</name>
+              <description>1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DATA_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_ADDR_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_CMD_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLAVE_CS_POL</name>
+              <description>spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DQS_IDLE_EDGE</name>
+              <description>The default value of spi_dqs. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_QUAD_DIN_PIN_SWAP</name>
+              <description>1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DIN_MODE</name>
+          <description>SPI input delay mode configuration</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DIN0_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN1_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN2_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN3_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN4_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN5_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN6_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN7_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_TIMING_HCLK_ACTIVE</name>
+              <description>1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DIN_NUM</name>
+          <description>SPI input delay number configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DIN0_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN1_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN2_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN3_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN4_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN5_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN6_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN7_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DOUT_MODE</name>
+          <description>SPI output delay mode configuration</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DOUT0_MODE</name>
+              <description>The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DOUT1_MODE</name>
+              <description>The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DOUT2_MODE</name>
+              <description>The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DOUT3_MODE</name>
+              <description>The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DOUT4_MODE</name>
+              <description>The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOUT5_MODE</name>
+              <description>The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOUT6_MODE</name>
+              <description>The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOUT7_MODE</name>
+              <description>The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_D_DQS_MODE</name>
+              <description>The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_CONF</name>
+          <description>SPI DMA control register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY</name>
+              <description>Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL</name>
+              <description>Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SLV_SEG_TRANS_EN</name>
+              <description>Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_TX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RX_EOF_EN</name>
+              <description>1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_RX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled receive data mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_TX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled send data mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RX_AFIFO_RST</name>
+              <description>Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_BUF_AFIFO_RST</name>
+              <description>Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_AFIFO_RST</name>
+              <description>Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_ENA</name>
+          <description>SPI interrupt enable register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_ENA</name>
+              <description>The enable bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_ENA</name>
+              <description>The enable bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_ENA</name>
+              <description>The enable bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_CLR</name>
+          <description>SPI interrupt clear register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_CLR</name>
+              <description>The clear bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_CLR</name>
+              <description>The clear bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_CLR</name>
+              <description>The clear bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_RAW</name>
+          <description>SPI interrupt raw register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_RAW</name>
+              <description>The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_RAW</name>
+              <description>The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_RAW</name>
+              <description>The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_ST</name>
+          <description>SPI interrupt status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_ST</name>
+              <description>The status bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_ST</name>
+              <description>The status bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_ST</name>
+              <description>The status bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_ST</name>
+              <description>The status bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_ST</name>
+              <description>The status bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_ST</name>
+              <description>The status bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_ST</name>
+              <description>The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_ST</name>
+              <description>The status bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_ST</name>
+              <description>The status bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_SET</name>
+          <description>SPI interrupt software set register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_SET</name>
+              <description>The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET</name>
+              <description>The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_SET</name>
+              <description>The software set bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_SET</name>
+              <description>The software set bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_SET</name>
+              <description>The software set bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_SET</name>
+              <description>The software set bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_SET</name>
+              <description>The software set bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_SET</name>
+              <description>The software set bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_SET</name>
+              <description>The software set bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_SET</name>
+              <description>The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET</name>
+              <description>The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET</name>
+              <description>The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_SET</name>
+              <description>The software set bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_SET</name>
+              <description>The software set bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W0</name>
+          <description>SPI CPU-controlled buffer0</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W1</name>
+          <description>SPI CPU-controlled buffer1</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W2</name>
+          <description>SPI CPU-controlled buffer2</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W3</name>
+          <description>SPI CPU-controlled buffer3</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W4</name>
+          <description>SPI CPU-controlled buffer4</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W5</name>
+          <description>SPI CPU-controlled buffer5</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W6</name>
+          <description>SPI CPU-controlled buffer6</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W7</name>
+          <description>SPI CPU-controlled buffer7</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W8</name>
+          <description>SPI CPU-controlled buffer8</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W9</name>
+          <description>SPI CPU-controlled buffer9</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W10</name>
+          <description>SPI CPU-controlled buffer10</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W11</name>
+          <description>SPI CPU-controlled buffer11</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W12</name>
+          <description>SPI CPU-controlled buffer12</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W13</name>
+          <description>SPI CPU-controlled buffer13</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W14</name>
+          <description>SPI CPU-controlled buffer14</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W15</name>
+          <description>SPI CPU-controlled buffer15</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE</name>
+          <description>SPI slave control register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02800000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLK_MODE_13</name>
+              <description>{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RSCK_DATA_OUT</name>
+              <description>It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RDDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WRDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RDBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WRBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_MAGIC_VALUE</name>
+              <description>The magic value of BM table in master DMA seg-trans.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Set SPI work mode. 1: slave mode 0: master mode.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SOFT_RESET</name>
+              <description>Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_USR_CONF</name>
+              <description>1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_FD_WAIT_DMA_TX_DATA</name>
+              <description>In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE1</name>
+          <description>SPI slave control register 1</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SLV_DATA_BITLEN</name>
+              <description>The transferred data bit length in SPI slave FD and HD mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_LAST_COMMAND</name>
+              <description>In the slave mode it is the value of command.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_LAST_ADDR</name>
+              <description>In the slave mode it is the value of address.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CLK_GATE</name>
+          <description>SPI module clock and register clock control</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_CLK_ACTIVE</name>
+              <description>Set this bit to power on the SPI module clock.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_CLK_SEL</name>
+              <description>This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DATE</name>
+          <description>Version control</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201300</resetValue>
+          <fields>
+            <field>
+              <name>SPI_DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SYSTIMER</name>
+      <description>System Timer</description>
+      <groupName>SYSTIMER</groupName>
+      <baseAddress>0x6000A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x90</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSTIMER_TARGET0</name>
+        <value>57</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET1</name>
+        <value>58</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET2</name>
+        <value>59</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF</name>
+          <description>Configure system timer clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x46000000</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_CLK_FO</name>
+              <description>systimer clock force on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_EN</name>
+              <description>enable systimer's etm task and event</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_WORK_EN</name>
+              <description>target2 work enable</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_WORK_EN</name>
+              <description>target1 work enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_WORK_EN</name>
+              <description>target0 work enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE1_STALL_EN</name>
+              <description>If timer unit1 is stalled when core1 stalled</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE0_STALL_EN</name>
+              <description>If timer unit1 is stalled when core0 stalled</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE1_STALL_EN</name>
+              <description>If timer unit0 is stalled when core1 stalled</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE0_STALL_EN</name>
+              <description>If timer unit0 is stalled when core0 stalled</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_WORK_EN</name>
+              <description>timer unit1 work enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_WORK_EN</name>
+              <description>timer unit0 work enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>register file clk gating</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_OP</name>
+          <description>system timer unit0 value update register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_VALID</name>
+              <description>timer value is sync and valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_UPDATE</name>
+              <description>update timer_unit0</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_OP</name>
+          <description>system timer unit1 value update register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_VALID</name>
+              <description>timer value is sync and valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_UPDATE</name>
+              <description>update timer unit1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_HI</name>
+          <description>system timer unit0 value high load register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_HI</name>
+              <description>timer unit0 load high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_LO</name>
+          <description>system timer unit0 value low load register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_LO</name>
+              <description>timer unit0 load low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_HI</name>
+          <description>system timer unit1 value high load register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_HI</name>
+              <description>timer unit1 load high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_LO</name>
+          <description>system timer unit1 value low load register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_LO</name>
+              <description>timer unit1 load low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_HI</name>
+          <description>system timer comp0 value high register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_HI</name>
+              <description>timer taget0 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_LO</name>
+          <description>system timer comp0 value low register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_LO</name>
+              <description>timer taget0 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_HI</name>
+          <description>system timer comp1 value high register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_HI</name>
+              <description>timer taget1 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_LO</name>
+          <description>system timer comp1 value low register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_LO</name>
+              <description>timer taget1 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_HI</name>
+          <description>system timer comp2 value high register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_HI</name>
+              <description>timer taget2 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_LO</name>
+          <description>system timer comp2 value low register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_LO</name>
+              <description>timer taget2 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_CONF</name>
+          <description>system timer comp0 target mode register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_PERIOD</name>
+              <description>target0 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_PERIOD_MODE</name>
+              <description>Set target0 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_CONF</name>
+          <description>system timer comp1 target mode register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_PERIOD</name>
+              <description>target1 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_PERIOD_MODE</name>
+              <description>Set target1 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_CONF</name>
+          <description>system timer comp2 target mode register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_PERIOD</name>
+              <description>target2 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_PERIOD_MODE</name>
+              <description>Set target2 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_HI</name>
+          <description>system timer unit0 value high register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_HI</name>
+              <description>timer read value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_LO</name>
+          <description>system timer unit0 value low register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_LO</name>
+              <description>timer read value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_HI</name>
+          <description>system timer unit1 value high register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_HI</name>
+              <description>timer read value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_LO</name>
+          <description>system timer unit1 value low register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_LO</name>
+              <description>timer read value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP0_LOAD</name>
+          <description>system timer comp0 conf sync register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP0_LOAD</name>
+              <description>timer comp0 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP1_LOAD</name>
+          <description>system timer comp1 conf sync register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP1_LOAD</name>
+              <description>timer comp1 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP2_LOAD</name>
+          <description>system timer comp2 conf sync register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP2_LOAD</name>
+              <description>timer comp2 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD</name>
+          <description>system timer unit0 conf sync register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD</name>
+              <description>timer unit0 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD</name>
+          <description>system timer unit1 conf sync register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD</name>
+              <description>timer unit1 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>systimer interrupt enable register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ENA</name>
+              <description>interupt0 enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ENA</name>
+              <description>interupt1 enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ENA</name>
+              <description>interupt2 enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>systimer interrupt raw register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_RAW</name>
+              <description>interupt0 raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_RAW</name>
+              <description>interupt1 raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_RAW</name>
+              <description>interupt2 raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>systimer interrupt clear register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_CLR</name>
+              <description>interupt0 clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_CLR</name>
+              <description>interupt1 clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_CLR</name>
+              <description>interupt2 clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>systimer interrupt status register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ST</name>
+              <description>interupt0 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ST</name>
+              <description>interupt1 status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ST</name>
+              <description>interupt2 status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET0_LO</name>
+          <description>system timer comp0 actual target value low register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_LO_RO</name>
+              <description>actual target value value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET0_HI</name>
+          <description>system timer comp0 actual target value high register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_HI_RO</name>
+              <description>actual target value value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET1_LO</name>
+          <description>system timer comp1 actual target value low register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_LO_RO</name>
+              <description>actual target value value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET1_HI</name>
+          <description>system timer comp1 actual target value high register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_HI_RO</name>
+              <description>actual target value value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET2_LO</name>
+          <description>system timer comp2 actual target value low register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_LO_RO</name>
+              <description>actual target value value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET2_HI</name>
+          <description>system timer comp2 actual target value high register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_HI_RO</name>
+              <description>actual target value value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>system timer version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201073</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>systimer register version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TEE</name>
+      <description>Peripheral TEE</description>
+      <groupName>TEE</groupName>
+      <baseAddress>0x60098000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>M0_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_MODE</name>
+              <description>M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M1_MODE</name>
+              <description>M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M2_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M2_MODE</name>
+              <description>M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M3_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M3_MODE</name>
+              <description>M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M4_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M4_MODE</name>
+              <description>M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M5_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M5_MODE</name>
+              <description>M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M6_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M6_MODE</name>
+              <description>M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M7_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M7_MODE</name>
+              <description>M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M8_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M8_MODE</name>
+              <description>M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M9_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M9_MODE</name>
+              <description>M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M10_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M10_MODE</name>
+              <description>M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M11_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M11_MODE</name>
+              <description>M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M12_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M12_MODE</name>
+              <description>M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M13_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M13_MODE</name>
+              <description>M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M14_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M14_MODE</name>
+              <description>M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M15_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M15_MODE</name>
+              <description>M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M16_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M16_MODE</name>
+              <description>M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M17_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M17_MODE</name>
+              <description>M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M18_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M18_MODE</name>
+              <description>M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M19_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M19_MODE</name>
+              <description>M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M20_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M20_MODE</name>
+              <description>M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M21_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M21_MODE</name>
+              <description>M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M22_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M22_MODE</name>
+              <description>M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M23_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M23_MODE</name>
+              <description>M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M24_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M24_MODE</name>
+              <description>M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M25_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M25_MODE</name>
+              <description>M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M26_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M26_MODE</name>
+              <description>M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M27_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M27_MODE</name>
+              <description>M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M28_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M28_MODE</name>
+              <description>M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M29_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M29_MODE</name>
+              <description>M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M30_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M30_MODE</name>
+              <description>M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M31_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M31_MODE</name>
+              <description>M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>Clock gating register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02205282</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_tee_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TIMG0</name>
+      <description>Timer Group</description>
+      <groupName>TIMG</groupName>
+      <baseAddress>0x60008000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TG0_T0</name>
+        <value>51</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_T1</name>
+        <value>52</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_WDT</name>
+        <value>53</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>T0CONFIG</name>
+          <description>Timer %s configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002000</resetValue>
+          <fields>
+            <field>
+              <name>T_USE_XTAL</name>
+              <description>1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_ALARM_EN</name>
+              <description>When set, the alarm is enabled. This bit is automatically cleared once an
+alarm occurs.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_DIVCNT_RST</name>
+              <description>When set, Timer %s 's clock divider counter will be reset.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>T_DIVIDER</name>
+              <description>Timer %s clock (T%s_clk) prescaler value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_AUTORELOAD</name>
+              <description>When set, timer %s auto-reload at alarm is enabled.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_INCREASE</name>
+              <description>When set, the timer %s time-base counter will increment every clock tick. When
+cleared, the timer %s time-base counter will decrement.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_EN</name>
+              <description>When set, the timer %s time-base counter is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LO</name>
+          <description>Timer %s current value, low 32 bits</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LO</name>
+              <description>After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter
+of timer %s can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0HI</name>
+          <description>Timer %s current value, high 22 bits</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_HI</name>
+              <description>After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter
+of timer %s can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0UPDATE</name>
+          <description>Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_UPDATE</name>
+              <description>After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMLO</name>
+          <description>Timer %s alarm value, low 32 bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_ALARM_LO</name>
+              <description>Timer %s alarm trigger time-base counter value, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMHI</name>
+          <description>Timer %s alarm value, high bits</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_ALARM_HI</name>
+              <description>Timer %s alarm trigger time-base counter value, high 22 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADLO</name>
+          <description>Timer %s reload value, low 32 bits</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LOAD_LO</name>
+              <description>Low 32 bits of the value that a reload will load onto timer %s time-base
+Counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADHI</name>
+          <description>Timer %s reload value, high 22 bits</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LOAD_HI</name>
+              <description>High 22 bits of the value that a reload will load onto timer %s time-base
+counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOAD</name>
+          <description>Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LOAD</name>
+              <description>
+Write any value to trigger a timer %s time-base counter reload.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>Watchdog timer configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0004C000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>WDT reset CPU enable.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>WDT reset CPU enable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>When set, Flash boot protection is enabled.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>System reset signal length selection. 0: 100 ns, 1: 200 ns,
+2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_USE_XTAL</name>
+              <description>choose WDT clock:0-apb_clk, 1-xtal_clk.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CONF_UPDATE_EN</name>
+              <description>update the WDT configuration registers</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>When set, MWDT is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>Watchdog timer prescaler register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_DIVCNT_RST</name>
+              <description>When set, WDT 's clock divider counter will be reset.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_CLK_PRESCALE</name>
+              <description>MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+TIMG_WDT_CLK_PRESCALE.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>Watchdog timer stage 0 timeout value</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x018CBA80</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>Stage 0 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>Watchdog timer stage 1 timeout value</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>Stage 1 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>Watchdog timer stage 2 timeout value</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>Stage 2 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG5</name>
+          <description>Watchdog timer stage 3 timeout value</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>Stage 3 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>Write to feed the watchdog timer</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>Write any value to feed the MWDT. (WO)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>Watchdog write protect register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>If the register contains a different value than its reset value, write
+protection is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG</name>
+          <description>RTC calibration configure register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00011000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_START_CYCLING</name>
+              <description>0: one-shot frequency calculation,1: periodic frequency calculation,</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_CLK_SEL</name>
+              <description>0:rtc slow clock. 1:clk_8m, 2:xtal_32k.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_RDY</name>
+              <description>indicate one-shot frequency calculation is done.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_MAX</name>
+              <description>Configure the time to calculate RTC slow clock's frequency.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_START</name>
+              <description>Set this bit to start one-shot frequency calculation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG1</name>
+          <description>RTC calibration configure1 register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_CALI_CYCLING_DATA_VLD</name>
+              <description>indicate periodic frequency calculation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_VALUE</name>
+              <description>When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_TIMERS</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_TIMERS</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_TIMERS</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_TIMERS</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG2</name>
+          <description>Timer group calibration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFF98</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_TIMEOUT</name>
+              <description>RTC calibration timeout indicator</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_RST_CNT</name>
+              <description>Cycles that release calibration timeout reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_THRES</name>
+              <description>Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NTIMERS_DATE</name>
+          <description>Timer version control register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206072</resetValue>
+          <fields>
+            <field>
+              <name>NTIMGS_DATE</name>
+              <description>Timer version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGCLK</name>
+          <description>Timer group clock gate register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>ETM_EN</name>
+              <description>enable timer's etm task and event</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CLK_IS_ACTIVE</name>
+              <description>enable WDT's clock</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_CLK_IS_ACTIVE</name>
+              <description>enable Timer 30's clock</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMG0">
+      <name>TIMG1</name>
+      <description>Timer Group</description>
+      <baseAddress>0x60009000</baseAddress>
+      <interrupt>
+        <name>TG1_T0</name>
+        <value>54</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_T1</name>
+        <value>55</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_WDT</name>
+        <value>56</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TRACE</name>
+      <description>Peripheral TRACE</description>
+      <groupName>TRACE</groupName>
+      <baseAddress>0x600C0000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x30</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TRACE</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MEM_START_ADDR</name>
+          <description>mem start addr</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_STAET_ADDR</name>
+              <description>The start address of trace memory</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_END_ADDR</name>
+          <description>mem end addr</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>MEM_END_ADDR</name>
+              <description>The end address of trace memory</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CURRENT_ADDR</name>
+          <description>mem current addr</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_CURRENT_ADDR</name>
+              <description>current_mem_addr,indicate that next writing addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_ADDR_UPDATE</name>
+          <description>mem addr update</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_CURRENT_ADDR_UPDATE</name>
+              <description>when set this reg, the current_mem_addr will update to start_addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_STATUS</name>
+          <description>fifo status register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>FIFO_EMPTY</name>
+              <description>1 indicate that fifo is empty</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WORK_STATUS</name>
+              <description>mem_full interrupt status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_ENA</name>
+          <description>interrupt enable register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_OVERFLOW_INTR_ENA</name>
+              <description>Set 1 enable fifo_overflow interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FULL_INTR_ENA</name>
+              <description>Set 1 enable mem_full interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_RAW</name>
+          <description>interrupt status register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_OVERFLOW_INTR_RAW</name>
+              <description>fifo_overflow interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL_INTR_RAW</name>
+              <description>mem_full interrupt status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_CLR</name>
+          <description>interrupt clear register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_OVERFLOW_INTR_CLR</name>
+              <description>Set 1 clr fifo overflow interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL_INTR_CLR</name>
+              <description>Set 1 clr mem full interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>trigger register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000C</resetValue>
+          <fields>
+            <field>
+              <name>ON</name>
+              <description>[0] set 1 start trace.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OFF</name>
+              <description>set 1 stop trace.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_LOOP</name>
+              <description>if this reg is 1, trace will loop wrtie trace_mem.  If is 0, when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESTART_ENA</name>
+              <description>enable encoder auto-restart, when lost package, the encoder will end, if enable auto-restart, when fifo empty, encoder will restart and send a sync package.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESYNC_PROLONGED</name>
+          <description>resync configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>RESYNC_PROLONGED</name>
+              <description>count number, when count to this value, send a sync package</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESYNC_MODE</name>
+              <description>resyc mode sel: 0: default, cycle count   1: package num count</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>Clock gate control register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>The bit is used to enable clock gate when access all registers in this module.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02203030</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version control register. Note that this default value stored is the latest date when the hardware logic was updated.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TWAI0</name>
+      <description>Two-Wire Automotive Interface</description>
+      <groupName>TWAI</groupName>
+      <baseAddress>0x6000B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TWAI0</name>
+        <value>46</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>TWAI mode register.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RESET_MODE</name>
+              <description>1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LISTEN_ONLY_MODE</name>
+              <description>1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SELF_TEST_MODE</name>
+              <description>1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ACCEPTANCE_FILTER_MODE</name>
+              <description>1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active).</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>TWAI command register.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_REQUEST</name>
+              <description>1: present, a message shall be transmitted. 0: absent</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ABORT_TX</name>
+              <description>1: present, if not already in progress, a pending transmission request is cancelled. 0: absent</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RELEASE_BUFFER</name>
+              <description>1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CLEAR_DATA_OVERRUN</name>
+              <description>1: clear, the data overrun status bit is cleared. 0: no action.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SELF_RX_REQUEST</name>
+              <description>1: present, a message shall be transmitted and received simultaneously. 0: absent.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>TWAI status register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECEIVE_BUFFER</name>
+              <description>1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANSMIT_BUFFER</name>
+              <description>1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANSMISSION_COMPLETE</name>
+              <description>1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RECEIVE</name>
+              <description>1: receive, the TWAI controller is receiving a message. 0: idle</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANSMIT</name>
+              <description>1: transmit, the TWAI controller is transmitting a message. 0: idle</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NODE_BUS_OFF</name>
+              <description>1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MISS</name>
+              <description>1: current message is destroyed because of FIFO overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT</name>
+          <description>Interrupt signals' register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECEIVE_INT_ST</name>
+              <description>1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANSMIT_INT_ST</name>
+              <description>1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_WARNING_INT_ST</name>
+              <description>1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DATA_OVERRUN_INT_ST</name>
+              <description>1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ST</name>
+              <description>1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ST</name>
+              <description>1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDLE_INT_ST</name>
+              <description>1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT_ENABLE</name>
+          <description>Interrupt enable register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_RECEIVE_INT_ENA</name>
+              <description>1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_TRANSMIT_INT_ENA</name>
+              <description>1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_ERR_WARNING_INT_ENA</name>
+              <description>1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_DATA_OVERRUN_INT_ENA</name>
+              <description>1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ENA</name>
+              <description>1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ENA</name>
+              <description>1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_INT_ENA</name>
+              <description>1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_0</name>
+          <description>Bit timing configuration register 0.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BAUD_PRESC</name>
+              <description>The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC_JUMP_WIDTH</name>
+              <description>The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_1</name>
+          <description>Bit timing configuration register 1.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_SEGMENT1</name>
+              <description>The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SEGMENT2</name>
+              <description>The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SAMPLING</name>
+              <description>1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_LOST_CAP</name>
+          <description>TWAI arbiter lost capture register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ARBITRATION_LOST_CAPTURE</name>
+              <description>This register contains information about the bit position of losing arbitration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_CODE_CAP</name>
+          <description>TWAI error info capture register.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ERR_CAPTURE_CODE_SEGMENT</name>
+              <description>This register contains information about the location of errors on the bus.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_CAPTURE_CODE_DIRECTION</name>
+              <description>1: RX, error occurred during reception. 0: TX, error occurred during transmission.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_CAPTURE_CODE_TYPE</name>
+              <description>00: bit error. 01: form error. 10:stuff error. 11:other type of error.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_WARNING_LIMIT</name>
+          <description>TWAI error threshold configuration register.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000060</resetValue>
+          <fields>
+            <field>
+              <name>ERR_WARNING_LIMIT</name>
+              <description>The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_ERR_CNT</name>
+          <description>Rx error counter register.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CNT</name>
+              <description>The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_ERR_CNT</name>
+          <description>Tx error counter register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_ERR_CNT</name>
+              <description>The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_0</name>
+          <description>Data register 0.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_0</name>
+              <description>In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_1</name>
+          <description>Data register 1.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_1</name>
+              <description>In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_2</name>
+          <description>Data register 2.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_2</name>
+              <description>In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_3</name>
+          <description>Data register 3.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_3</name>
+              <description>In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_4</name>
+          <description>Data register 4.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_4</name>
+              <description>In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_5</name>
+          <description>Data register 5.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_5</name>
+              <description>In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_6</name>
+          <description>Data register 6.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_6</name>
+              <description>In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_7</name>
+          <description>Data register 7.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_7</name>
+              <description>In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_8</name>
+          <description>Data register 8.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_8</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_9</name>
+          <description>Data register 9.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_9</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_10</name>
+          <description>Data register 10.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_10</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_11</name>
+          <description>Data register 11.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_11</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_12</name>
+          <description>Data register 12.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_12</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_MESSAGE_COUNTER</name>
+          <description>Received message counter register.</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_MESSAGE_COUNTER</name>
+              <description>Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_DIVIDER</name>
+          <description>Clock divider register.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CD</name>
+              <description>These bits are used to define the frequency at the external CLKOUT pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLOCK_OFF</name>
+              <description>1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SW_STANDBY_CFG</name>
+          <description>Software configure standby pin directly.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>SW_STANDBY_EN</name>
+              <description>Enable standby pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STANDBY_CLR</name>
+              <description>Clear standby pin.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HW_CFG</name>
+          <description>Hardware configure standby pin.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HW_STANDBY_EN</name>
+              <description>Enable function that hardware control standby pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HW_STANDBY_CNT</name>
+          <description>Configure standby counter.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STANDBY_WAIT_CNT</name>
+              <description>Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_INTR_CNT</name>
+          <description>Configure idle interrupt counter.</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IDLE_INTR_CNT</name>
+              <description>Configure the number of cycles before triggering idle interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ECO_CFG</name>
+          <description>ECO configuration register.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RDN_ENA</name>
+              <description>Enable eco module.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDN_RESULT</name>
+              <description>Output of eco module.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TWAI0">
+      <name>TWAI1</name>
+      <description>Two-Wire Automotive Interface</description>
+      <baseAddress>0x6000D000</baseAddress>
+      <interrupt>
+        <name>TWAI1</name>
+        <value>47</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>UART0</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x60000000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x98</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART0</name>
+        <value>43</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>FIFO</name>
+          <description>FIFO data register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RD_BYTE</name>
+              <description>UART 0 accesses FIFO via this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error in the data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error .</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters after all data in Tx-FIFO are sent.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ST</name>
+              <description>This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ST</name>
+              <description>This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ST</name>
+              <description>This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ST</name>
+              <description>This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ST</name>
+              <description>This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ST</name>
+              <description>This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ST</name>
+              <description>This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ST</name>
+              <description>This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ST</name>
+              <description>This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ST</name>
+              <description>This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ST</name>
+              <description>This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ST</name>
+              <description>This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ST</name>
+              <description>This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ST</name>
+              <description>This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_full_int_st register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ENA</name>
+              <description>This is the enable bit for txfifo_empty_int_st register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for parity_err_int_st register.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for frm_err_int_st register.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_ovf_int_st register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ENA</name>
+              <description>This is the enable bit for dsr_chg_int_st register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ENA</name>
+              <description>This is the enable bit for cts_chg_int_st register.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ENA</name>
+              <description>This is the enable bit for brk_det_int_st register.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_tout_int_st register.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ENA</name>
+              <description>This is the enable bit for sw_xon_int_st register.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ENA</name>
+              <description>This is the enable bit for sw_xoff_int_st register.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>This is the enable bit for glitch_det_int_st register.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_done_int_st register.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_idle_done_int_st register.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_done_int_st register.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ENA</name>
+              <description>This is the enable bit for rs485_clash_int_st register.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ENA</name>
+              <description>This is the enable bit for at_cmd_char_det_int_st register.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ENA</name>
+              <description>This is the enable bit for uart_wakeup_int_st register.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_full_int_raw interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear txfifo_empty_int_raw interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear parity_err_int_raw interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear frm_err_int_raw interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear rxfifo_ovf_int_raw interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_CLR</name>
+              <description>Set this bit to clear the dsr_chg_int_raw interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear the cts_chg_int_raw interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_CLR</name>
+              <description>Set this bit to clear the brk_det_int_raw interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_tout_int_raw interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_CLR</name>
+              <description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_CLR</name>
+              <description>Set this bit to clear the sw_xoff_int_raw interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Set this bit to clear the glitch_det_int_raw interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_done_int_raw interrupt..</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_idle_done_int_raw interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_done_int_raw interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_parity_err_int_raw interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_frm_err_int_raw interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_CLR</name>
+              <description>Set this bit to clear the rs485_clash_int_raw interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_CLR</name>
+              <description>Set this bit to clear the at_cmd_char_det_int_raw interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_CLR</name>
+              <description>Set this bit to clear the uart_wakeup_int_raw interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV_SYNC</name>
+          <description>Clock divider configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000002B6</resetValue>
+          <fields>
+            <field>
+              <name>CLKDIV</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKDIV_FRAG</name>
+              <description>The decimal part of the frequency divider factor.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_FILT</name>
+          <description>Rx Filter configuration</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>GLITCH_FILT</name>
+              <description>when input pulse width is lower than this value the pulse is ignored.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_FILT_EN</name>
+              <description>Set this bit to enable Rx signal filter.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>UART status register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xE000C000</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>Stores the byte number of valid data in Rx-FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSRN</name>
+              <description>The register represent the level value of the internal uart dsr signal.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTSN</name>
+              <description>This register represent the level value of the internal uart cts signal.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXD</name>
+              <description>This register represent the  level value of the internal uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>Stores the byte number of data in Tx-FIFO.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTRN</name>
+              <description>This bit represents the level of the internal uart dtr signal.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTSN</name>
+              <description>This bit represents the level of the internal uart rts signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXD</name>
+              <description>This bit represents the  level of the internal uart txd signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0_SYNC</name>
+          <description>a</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0010001C</resetValue>
+          <fields>
+            <field>
+              <name>PARITY</name>
+              <description>This register is used to configure the parity check mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_EN</name>
+              <description>Set this bit to enable uart parity check.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIT_NUM</name>
+              <description>This register is used to set the length of data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOP_BIT_NUM</name>
+              <description>This register is used to set the length of  stop bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_BRK</name>
+              <description>Set this bit to enbale transmitter to  send NULL when the process of sending data is done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_DPLX</name>
+              <description>Set this bit to enable IrDA loopback mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_EN</name>
+              <description>This is the start enable bit for IrDA transmitter.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_WCTL</name>
+              <description>1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_INV</name>
+              <description>Set this bit to invert the level of  IrDA transmitter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_RX_INV</name>
+              <description>Set this bit to invert the level of IrDA receiver.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOPBACK</name>
+              <description>Set this bit to enable uart loopback test mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FLOW_EN</name>
+              <description>Set this bit to enable flow control function for transmitter.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_EN</name>
+              <description>Set this bit to enable IrDA protocol.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXD_INV</name>
+              <description>Set this bit to inverse the level value of uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_INV</name>
+              <description>Set this bit to inverse the level value of uart txd signal.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIS_RX_DAT_OVF</name>
+              <description>Disable UART Rx data overflow detect.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WR_MASK</name>
+              <description>1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTOBAUD_EN</name>
+              <description>This is the enable bit for detecting baudrate.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_EN</name>
+              <description>UART memory clock gate enable signal.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_RTS</name>
+              <description>This register is used to configure the software rts signal which is used in software flow control.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>Set this bit to reset the uart receive-FIFO.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_RST</name>
+              <description>Set this bit to reset the uart transmit-FIFO.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>Configuration register 1</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00006060</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_THRHD</name>
+              <description>It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_THRHD</name>
+              <description>It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_INV</name>
+              <description>Set this bit to inverse the level value of uart cts signal.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_INV</name>
+              <description>Set this bit to inverse the level value of uart dsr signal.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTS_INV</name>
+              <description>Set this bit to inverse the level value of uart rts signal.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTR_INV</name>
+              <description>Set this bit to inverse the level value of uart dtr signal.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_DTR</name>
+              <description>This register is used to configure the software dtr signal which is used in software flow control.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HWFC_CONF_SYNC</name>
+          <description>Hardware flow-control configuration</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_FLOW_THRHD</name>
+              <description>This register is used to configure the maximum amount of data that can be received  when hardware flow control works.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_EN</name>
+              <description>This is the flow enable bit for UART receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF0</name>
+          <description>UART sleep configure register 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WK_CHAR1</name>
+              <description>This register restores the specified wake up char1 to wake up</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR2</name>
+              <description>This register restores the specified wake up char2 to wake up</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR3</name>
+              <description>This register restores the specified wake up char3 to wake up</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR4</name>
+              <description>This register restores the specified wake up char4 to wake up</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF1</name>
+          <description>UART sleep configure register 1</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WK_CHAR0</name>
+              <description>This register restores the specified char0 to wake up</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF2</name>
+          <description>UART sleep configure register 2</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001404F0</resetValue>
+          <fields>
+            <field>
+              <name>ACTIVE_THRESHOLD</name>
+              <description>The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WAKE_UP_THRHD</name>
+              <description>In wake up mode 1 this field is used to set the received data number threshold to wake up chip.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR_NUM</name>
+              <description>This register is used to select number of wake up char.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR_MASK</name>
+              <description>This register is used to mask  wake up char.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_MODE_SEL</name>
+              <description>This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF0_SYNC</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001311</resetValue>
+          <fields>
+            <field>
+              <name>XON_CHAR</name>
+              <description>This register stores the Xon flow control char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_CHAR</name>
+              <description>This register stores the Xoff flow control char.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XON_XOFF_STILL_SEND</name>
+              <description>In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_FLOW_CON_EN</name>
+              <description>Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XONOFF_DEL</name>
+              <description>Set this bit to remove flow control char from the received data.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XON</name>
+              <description>Set this bit to enable the transmitter to go on sending data.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XOFF</name>
+              <description>Set this bit to stop the  transmitter from sending data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XON</name>
+              <description>Set this bit to send Xon char. It is cleared by hardware automatically.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XOFF</name>
+              <description>Set this bit to send Xoff char. It is cleared by hardware automatically.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF1</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000E000</resetValue>
+          <fields>
+            <field>
+              <name>XON_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1  it will send a Xon char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1  it will send a Xoff char.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXBRK_CONF_SYNC</name>
+          <description>Tx Break character configuration</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>TX_BRK_NUM</name>
+              <description>This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_CONF_SYNC</name>
+          <description>Frame-end idle configuration</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040100</resetValue>
+          <fields>
+            <field>
+              <name>RX_IDLE_THRHD</name>
+              <description>It will produce frame end signal when receiver takes more time to receive one byte data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between transfers.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RS485_CONF_SYNC</name>
+          <description>RS485 mode configuration</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RS485_EN</name>
+              <description>Set this bit to choose the rs485 mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL0_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL1_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485TX_RX_EN</name>
+              <description>Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485RXBY_TX_EN</name>
+              <description>1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_RX_DLY_NUM</name>
+              <description>This register is used to delay the receiver's internal data signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_TX_DLY_NUM</name>
+              <description>This register is used to delay the transmitter's internal data signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_PRECNT_SYNC</name>
+          <description>Pre-sequence timing configuration</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>PRE_IDLE_NUM</name>
+              <description>This register is used to configure the idle duration time before the first at_cmd is received by receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_POSTCNT_SYNC</name>
+          <description>Post-sequence timing configuration</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>POST_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between the last at_cmd and the next data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_GAPTOUT_SYNC</name>
+          <description>Timeout configuration</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>RX_GAP_TOUT</name>
+              <description>This register is used to configure the duration time between the at_cmd chars.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_CHAR_SYNC</name>
+          <description>AT escape sequence detection configuration</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000032B</resetValue>
+          <fields>
+            <field>
+              <name>AT_CMD_CHAR</name>
+              <description>This register is used to configure the content of at_cmd char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAR_NUM</name>
+              <description>This register is used to configure the num of continuous at_cmd chars received by receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>UART memory power configuration</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to force power down UART memory.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>Set this bit to force power up UART memory.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUT_CONF_SYNC</name>
+          <description>UART threshold and allocation configuration</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000028</resetValue>
+          <fields>
+            <field>
+              <name>RX_TOUT_EN</name>
+              <description>This is the enble bit for uart receiver's timeout function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_FLOW_DIS</name>
+              <description>Set this bit to stop accumulating idle_cnt when hardware flow control works.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_THRHD</name>
+              <description>This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_TX_STATUS</name>
+          <description>Tx-SRAM write and read offset address.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_SRAM_WADDR</name>
+              <description>This register stores the offset write address in Tx-SRAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_SRAM_RADDR</name>
+              <description>This register stores the offset read address in Tx-SRAM.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_RX_STATUS</name>
+          <description>Rx-SRAM write and read offset address.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010080</resetValue>
+          <fields>
+            <field>
+              <name>RX_SRAM_RADDR</name>
+              <description>This register stores the offset read address in RX-SRAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_SRAM_WADDR</name>
+              <description>This register stores the offset write address in Rx-SRAM.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_STATUS</name>
+          <description>UART transmit and receive status.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST_URX_OUT</name>
+              <description>This is the status register of receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ST_UTX_OUT</name>
+              <description>This is the status register of transmitter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POSPULSE</name>
+          <description>Autobaud high pulse register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>POSEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NEGPULSE</name>
+          <description>Autobaud low pulse register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>NEGEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOWPULSE</name>
+          <description>Autobaud minimum low pulse duration register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HIGHPULSE</name>
+          <description>Autobaud minimum high pulse duration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXD_CNT</name>
+          <description>Autobaud edge change count register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXD_EDGE_CNT</name>
+              <description>This register stores the count of rxd edge change. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>UART core clock configuration</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03701000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>The  denominator of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>The numerator of the frequency divider factor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_EN</name>
+              <description>Set this bit to enable UART Tx/Rx clock.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_CORE</name>
+              <description>Write 1 then write 0 to this bit to reset UART Tx/Rx.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SCLK_EN</name>
+              <description>Set this bit to enable UART Tx clock.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SCLK_EN</name>
+              <description>Set this bit to enable UART Rx clock.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit to reset UART Tx.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit to reset UART Rx.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UART Version register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201260</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AFIFO_STATUS</name>
+          <description>UART AFIFO Status</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>TX_AFIFO_FULL</name>
+              <description>Full signal of APB TX AFIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_AFIFO_EMPTY</name>
+              <description>Empty signal of APB TX AFIFO.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_AFIFO_FULL</name>
+              <description>Full signal of APB RX AFIFO.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_AFIFO_EMPTY</name>
+              <description>Empty signal of APB RX AFIFO.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_UPDATE</name>
+          <description>UART Registers Configuration Update register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REG_UPDATE</name>
+              <description>Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ID</name>
+          <description>UART ID register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000500</resetValue>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>This register is used to configure the uart_id.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <name>UART1</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <baseAddress>0x60001000</baseAddress>
+      <interrupt>
+        <name>UART1</name>
+        <value>44</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>UHCI0</name>
+      <description>Universal Host Controller Interface</description>
+      <groupName>UHCI</groupName>
+      <baseAddress>0x60005000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x84</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UHCI0</name>
+        <value>42</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF0</name>
+          <description>UHCI Configuration Register0</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000006E0</resetValue>
+          <fields>
+            <field>
+              <name>TX_RST</name>
+              <description>Write 1 then write 0 to this bit to reset decode state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST</name>
+              <description>Write 1 then write 0 to this bit to reset encode state machine.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_CE</name>
+              <description>Set this bit to link up HCI and UART0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CE</name>
+              <description>Set this bit to link up HCI and UART1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_EN</name>
+              <description>Set this bit to separate the data frame using a special char.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HEAD_EN</name>
+              <description>Set this bit to encode the data packet with a formatting header.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_REC_EN</name>
+              <description>Set this bit to enable UHCI to receive the 16 bit CRC.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_IDLE_EOF_EN</name>
+              <description>If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEN_EOF_EN</name>
+              <description>If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCODE_CRC_EN</name>
+              <description>Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RX_BRK_EOF_EN</name>
+              <description>If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>UHCI Interrupt Raw Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_RAW</name>
+              <description>Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_RAW</name>
+              <description>Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data  exceeds the configuration value.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data  exceeds the configuration value.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_RAW</name>
+              <description>Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_RAW</name>
+              <description>Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <description>Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_RAW</name>
+              <description>Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_RAW</name>
+              <description>Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>UHCI Interrupt Status Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ST</name>
+              <description>Indicates the interrupt status of UHCI_RX_START_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ST</name>
+              <description>Indicates the interrupt status of UHCI_TX_START_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>Indicates the interrupt status of UHCI_RX_HUNG_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>Indicates the interrupt status of UHCI_TX_HUNG_INT.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ST</name>
+              <description>Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ST</name>
+              <description>Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ST</name>
+              <description>Indicates the interrupt status of UHCI_OUT_EOF_INT.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_ST</name>
+              <description>Indicates the interrupt status of UHCI_APP_CTRL0_INT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_ST</name>
+              <description>Indicates the interrupt status of UHCI_APP_CTRL1_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>UHCI Interrupt Enable Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ENA</name>
+              <description>Set this bit to enable the interrupt of UHCI_RX_START_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ENA</name>
+              <description>Set this bit to enable the interrupt of UHCI_TX_START_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>Set this bit to enable the interrupt of UHCI_RX_HUNG_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>Set this bit to enable the interrupt of UHCI_TX_HUNG_INT.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ENA</name>
+              <description>Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ENA</name>
+              <description>Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ENA</name>
+              <description>Set this bit to enable the interrupt of UHCI_OUT_EOF_INT.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_ENA</name>
+              <description>Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_ENA</name>
+              <description>Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>UHCI Interrupt Clear Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_CLR</name>
+              <description>Set this bit to clear the raw interrupt of UHCI_RX_START_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_CLR</name>
+              <description>Set this bit to clear the raw interrupt of UHCI_TX_START_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_CLR</name>
+              <description>Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_CLR</name>
+              <description>Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_CLR</name>
+              <description>Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_CLR</name>
+              <description>Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_CLR</name>
+              <description>Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>UHCI Configuration Register1</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>CHECK_SUM_EN</name>
+              <description>Set this bit to enable head checksum check when receiving.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_SEQ_EN</name>
+              <description>Set this bit to  enable sequence number check when receiving.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_DISABLE</name>
+              <description>Set this bit to support CRC calculation, and data integrity check bit should 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAVE_HEAD</name>
+              <description>Set this bit to save data packet head when UHCI receive data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHECK_SUM_RE</name>
+              <description>Set this bit to encode data packet with checksum.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_ACK_NUM_RE</name>
+              <description>Set this bit to encode data packet with ACK when reliable data packet is ready.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_SW_START</name>
+              <description>Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_START</name>
+              <description>Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <description>UHCI Receive Status Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CAUSE</name>
+              <description>Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DECODE_STATE</name>
+              <description>Indicates UHCI decoder status.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE1</name>
+          <description>UHCI Transmit Status Register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENCODE_STATE</name>
+              <description>Indicates UHCI encoder status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESCAPE_CONF</name>
+          <description>UHCI Escapes Configuration Register0</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>TX_C0_ESC_EN</name>
+              <description>Set this bit to enable resolve char 0xC0 when DMA receiving data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DB_ESC_EN</name>
+              <description>Set this bit to enable resolve char 0xDB when DMA receiving data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_11_ESC_EN</name>
+              <description>Set this bit to enable resolve flow control char 0x11 when DMA receiving data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_13_ESC_EN</name>
+              <description>Set this bit to enable resolve flow control char 0x13 when DMA receiving data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_C0_ESC_EN</name>
+              <description>Set this bit to enable replacing 0xC0 with special char when DMA receiving data.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DB_ESC_EN</name>
+              <description>Set this bit to enable replacing 0xDB with special char when DMA receiving data.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_11_ESC_EN</name>
+              <description>Set this bit to enable replacing 0x11 with special char when DMA receiving data.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_13_ESC_EN</name>
+              <description>Set this bit to enable replacing 0x13 with special char when DMA receiving data.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HUNG_CONF</name>
+          <description>UHCI Hung Configuration Register0</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00810810</resetValue>
+          <fields>
+            <field>
+              <name>TXFIFO_TIMEOUT</name>
+              <description>Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_SHIFT</name>
+              <description>Configures the maximum counter value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_ENA</name>
+              <description>Set this bit to enable TX FIFO timeout when receiving.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT</name>
+              <description>Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_SHIFT</name>
+              <description>Configures the maximum counter value.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_ENA</name>
+              <description>Set this bit to enable TX FIFO timeout when DMA sending data.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACK_NUM</name>
+          <description>UHCI Ack Value Configuration Register0</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ACK_NUM</name>
+              <description>Indicates the ACK number during software flow control.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>Set this bit to load the ACK value of UHCI_ACK_NUM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_HEAD</name>
+          <description>UHCI Head Register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_HEAD</name>
+              <description>Stores the head of received packet.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUICK_SENT</name>
+          <description>UCHI Quick send Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_SEND_NUM</name>
+              <description>Configures single_send mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SINGLE_SEND_EN</name>
+              <description>Set this bit to enable sending short packet with single_send mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_NUM</name>
+              <description>Configures always_send mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_EN</name>
+              <description>Set this bit to enable sending short packet with always_send mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q0_WORD0</name>
+          <description>UHCI Q0_WORD0 Quick Send Register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD0</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q0_WORD1</name>
+          <description>UHCI Q0_WORD1 Quick Send Register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD1</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q1_WORD0</name>
+          <description>UHCI Q1_WORD0 Quick Send Register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD0</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q1_WORD1</name>
+          <description>UHCI Q1_WORD1 Quick Send Register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD1</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q2_WORD0</name>
+          <description>UHCI Q2_WORD0 Quick Send Register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD0</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q2_WORD1</name>
+          <description>UHCI Q2_WORD1 Quick Send Register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD1</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q3_WORD0</name>
+          <description>UHCI Q3_WORD0 Quick Send Register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD0</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q3_WORD1</name>
+          <description>UHCI Q3_WORD1 Quick Send Register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD1</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q4_WORD0</name>
+          <description>UHCI Q4_WORD0 Quick Send Register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD0</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q4_WORD1</name>
+          <description>UHCI Q4_WORD1 Quick Send Register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD1</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q5_WORD0</name>
+          <description>UHCI Q5_WORD0 Quick Send Register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD0</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q5_WORD1</name>
+          <description>UHCI Q5_WORD1 Quick Send Register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD1</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q6_WORD0</name>
+          <description>UHCI Q6_WORD0 Quick Send Register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD0</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q6_WORD1</name>
+          <description>UHCI Q6_WORD1 Quick Send Register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD1</name>
+              <description>Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF0</name>
+          <description>UHCI Escapes Sequence Configuration Register0</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DCDBC0</resetValue>
+          <fields>
+            <field>
+              <name>SEPER_CHAR</name>
+              <description>Configures the delimiter for encoding, default value is 0xC0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR0</name>
+              <description>Configures the first char of SLIP escape character, default value is 0xDB.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR1</name>
+              <description>Configures the second char of SLIP escape character, default value is 0xDC.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF1</name>
+          <description>UHCI Escapes Sequence Configuration Register1</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DDDBDB</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ0</name>
+              <description>Configures the char needing encoding, which is 0xDB as flow control char by default.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR0</name>
+              <description>Configures the first char of SLIP escape character, default value is 0xDB.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR1</name>
+              <description>Configures the second char of SLIP escape character, default value is 0xDD.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF2</name>
+          <description>UHCI Escapes Sequence Configuration Register2</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DEDB11</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ1</name>
+              <description>Configures the char needing encoding, which is 0x11 as flow control char by default.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR0</name>
+              <description>Configures the first char of SLIP escape character, default value is 0xDB.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR1</name>
+              <description>Configures the second char of SLIP escape character, default value is 0xDE.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF3</name>
+          <description>UHCI Escapes Sequence Configuration Register3</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DFDB13</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ2</name>
+              <description>Configures the char needing encoding, which is 0x13 as flow control char by default.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR0</name>
+              <description>Configures the first char of SLIP escape character, default value is 0xDB.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR1</name>
+              <description>Configures the second char of SLIP escape character, default value is 0xDF.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_THRES</name>
+          <description>UCHI Packet Length Configuration Register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>PKT_THRS</name>
+              <description>Configures the data packet's maximum length when UHCI_HEAD_EN is 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UHCI Version Register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201100</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Configures version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>USB_DEVICE</name>
+      <description>Full-speed USB Serial/JTAG Controller</description>
+      <groupName>USB_DEVICE</groupName>
+      <baseAddress>0x6000F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x70</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB</name>
+        <value>48</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>EP1</name>
+          <description>FIFO access for the CDC-ACM data IN and OUT endpoints.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_RDWR_BYTE</name>
+              <description>Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EP1_CONF</name>
+          <description>Configuration and control registers for the CDC-ACM FIFOs.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_WR_DONE</name>
+              <description>Set this bit to indicate writing byte data to UART Tx FIFO is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE</name>
+              <description>1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL</name>
+              <description>1'b1: Indicate there is data in UART Rx FIFO.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt raw status register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when SOF frame is received.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PID_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when pid error is detected.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC5_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when CRC5 error is detected.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC16_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when CRC16 error is detected.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_STUFF_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when stuff error is detected.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when usb bus reset is detected.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS_CHG_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR_CHG_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when level of GET LINE CODING request is received.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when level of SET LINE CODING request is received.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Interrupt status register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PID_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC5_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC16_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_STUFF_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS_CHG_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR_CHG_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PID_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC5_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC16_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_STUFF_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS_CHG_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR_CHG_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear status register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PID_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC5_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC16_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_STUFF_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR_CHG_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0</name>
+          <description>PHY hardware configuration.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004200</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_PHY_SEL</name>
+              <description>Select internal/external PHY</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE</name>
+              <description>Enable software control USB D+ D- exchange</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_EXCHG_PINS</name>
+              <description>USB D+ D- exchange</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_VREFH</name>
+              <description>Control single-end input high threshold,1.76V to 2V, step 80mV</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_VREFL</name>
+              <description>Control single-end input low threshold,0.8V to 1.04V, step 80mV</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_VREF_OVERRIDE</name>
+              <description>Enable software control input  threshold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PAD_PULL_OVERRIDE</name>
+              <description>Enable software control USB D+ D- pullup pulldown</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DP_PULLUP</name>
+              <description>Control USB D+ pull up.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DP_PULLDOWN</name>
+              <description>Control USB D+ pull down.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DM_PULLUP</name>
+              <description>Control USB D- pull up.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DM_PULLDOWN</name>
+              <description>Control USB D- pull down.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PULLUP_VALUE</name>
+              <description>Control pull up value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_PAD_ENABLE</name>
+              <description>Enable USB pad function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN</name>
+              <description>Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEST</name>
+          <description>Registers used for debugging the PHY.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000030</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_ENABLE</name>
+              <description>Enable test of the USB pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_USB_OE</name>
+              <description>USB pad oen in test</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_TX_DP</name>
+              <description>USB D+ tx value in test</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_TX_DM</name>
+              <description>USB D- tx value in test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_RX_RCV</name>
+              <description>USB RCV value in test</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_RX_DP</name>
+              <description>USB D+ rx value in test</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_RX_DM</name>
+              <description>USB D- rx value in test</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JFIFO_ST</name>
+          <description>JTAG FIFO status and control registers.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000044</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_FIFO_CNT</name>
+              <description>JTAT in fifo counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_FIFO_EMPTY</name>
+              <description>1: JTAG in fifo is empty.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_FIFO_FULL</name>
+              <description>1: JTAG in fifo is full.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_FIFO_CNT</name>
+              <description>JTAT out fifo counter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_FIFO_EMPTY</name>
+              <description>1: JTAG out fifo is empty.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_FIFO_FULL</name>
+              <description>1: JTAG out fifo is full.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_FIFO_RESET</name>
+              <description>Write 1 to reset JTAG in fifo.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_FIFO_RESET</name>
+              <description>Write 1 to reset JTAG out fifo.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRAM_NUM</name>
+          <description>Last received SOF frame index register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_FRAME_INDEX</name>
+              <description>Frame index of received SOF frame.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP0_ST</name>
+          <description>Control IN endpoint status information.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP0_STATE</name>
+              <description>State of IN Endpoint 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP0_WR_ADDR</name>
+              <description>Write data address of IN endpoint 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP0_RD_ADDR</name>
+              <description>Read data address of IN endpoint 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP1_ST</name>
+          <description>CDC-ACM IN endpoint status information.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP1_STATE</name>
+              <description>State of IN Endpoint 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP1_WR_ADDR</name>
+              <description>Write data address of IN endpoint 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP1_RD_ADDR</name>
+              <description>Read data address of IN endpoint 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP2_ST</name>
+          <description>CDC-ACM interrupt IN endpoint status information.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP2_STATE</name>
+              <description>State of IN Endpoint 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP2_WR_ADDR</name>
+              <description>Write data address of IN endpoint 2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP2_RD_ADDR</name>
+              <description>Read data address of IN endpoint 2.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP3_ST</name>
+          <description>JTAG IN endpoint status information.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP3_STATE</name>
+              <description>State of IN Endpoint 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP3_WR_ADDR</name>
+              <description>Write data address of IN endpoint 3.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP3_RD_ADDR</name>
+              <description>Read data address of IN endpoint 3.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP0_ST</name>
+          <description>Control OUT endpoint status information.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP0_STATE</name>
+              <description>State of OUT Endpoint 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP0_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP0_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP1_ST</name>
+          <description>CDC-ACM OUT endpoint status information.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_STATE</name>
+              <description>State of OUT Endpoint 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT</name>
+              <description>Data count in OUT endpoint 1 when one packet is received.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP2_ST</name>
+          <description>JTAG OUT endpoint status information.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_STATE</name>
+              <description>State of OUT Endpoint 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 2.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC_CONF</name>
+          <description>Clock enable control</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>Memory power control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_MEM_PD</name>
+              <description>1: power down usb memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_MEM_CLK_EN</name>
+              <description>1: Force clock on for usb memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHIP_RST</name>
+          <description>CDC-ACM chip reset control.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS</name>
+              <description>1: Chip reset is detected from usb serial channel. Software write 1 to clear it.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR</name>
+              <description>1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS</name>
+              <description>Set this bit to disable chip reset from usb serial channel to reset chip.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_LINE_CODE_W0</name>
+          <description>W0 of SET_LINE_CODING command.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_DW_DTE_RATE</name>
+              <description>The value of dwDTERate set by host through SET_LINE_CODING command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_LINE_CODE_W1</name>
+          <description>W1 of SET_LINE_CODING command.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_BCHAR_FORMAT</name>
+              <description>The value of bCharFormat set by host through SET_LINE_CODING command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_BPARITY_TYPE</name>
+              <description>The value of bParityTpye set by host through SET_LINE_CODING command.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_BDATA_BITS</name>
+              <description>The value of bDataBits set by host through SET_LINE_CODING command.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GET_LINE_CODE_W0</name>
+          <description>W0 of GET_LINE_CODING command.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_DW_DTE_RATE</name>
+              <description>The value of dwDTERate set by software which is requested by GET_LINE_CODING command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GET_LINE_CODE_W1</name>
+          <description>W1 of GET_LINE_CODING command.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_BDATA_BITS</name>
+              <description>The value of bCharFormat set by software which is requested by GET_LINE_CODING command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_BPARITY_TYPE</name>
+              <description>The value of bParityTpye set by software which is requested by GET_LINE_CODING command.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_BCHAR_FORMAT</name>
+              <description>The value of bDataBits set by software which is requested by GET_LINE_CODING command.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG_UPDATE</name>
+          <description>Configuration registers' value update</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_CONFIG_UPDATE</name>
+              <description>Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SER_AFIFO_CONFIG</name>
+          <description>Serial AFIFO configure register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR</name>
+              <description>Write 1 to reset CDC_ACM IN async FIFO write clock domain.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD</name>
+              <description>Write 1 to reset CDC_ACM IN async FIFO read clock domain.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR</name>
+              <description>Write 1 to reset CDC_ACM OUT async FIFO write clock domain.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD</name>
+              <description>Write 1 to reset CDC_ACM OUT async FIFO read clock domain.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY</name>
+              <description>CDC_ACM OUTOUT async FIFO empty signal in read clock domain.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL</name>
+              <description>CDC_ACM OUT IN async FIFO empty signal in write clock domain.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_RESET_ST</name>
+          <description>USB Bus reset status register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_ST</name>
+              <description>USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02109220</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_DATE</name>
+              <description>register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/tools/ide-debug/svd/esp32h2.svd b/tools/ide-debug/svd/esp32h2.svd
new file mode 100644
index 00000000000..a19fad06bf0
--- /dev/null
+++ b/tools/ide-debug/svd/esp32h2.svd
@@ -0,0 +1,29571 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+  <vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
+  <vendorID>ESPRESSIF</vendorID>
+  <name>ESP32-H2</name>
+  <series>ESP32 H-Series</series>
+  <version>1</version>
+  <description>32-bit RISC-V MCU &amp; IEEE 802.15.4 &amp; Bluetooth 5 (LE)</description>
+  <licenseText>
+    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+</licenseText>
+  <cpu>
+    <name>RV32IMC</name>
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <nvicPrioBits>4</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>32</addressUnitBits>
+  <width>32</width>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AES</name>
+      <description>AES (Advanced Encryption Standard) Accelerator</description>
+      <groupName>AES</groupName>
+      <baseAddress>0x6003A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xBC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AES</name>
+        <value>48</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>KEY_0</name>
+          <description>Key material key_0 configure register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_0</name>
+              <description>This bits stores key_0 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_1</name>
+          <description>Key material key_1 configure register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_1</name>
+              <description>This bits stores key_1 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_2</name>
+          <description>Key material key_2 configure register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_2</name>
+              <description>This bits stores key_2 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_3</name>
+          <description>Key material key_3 configure register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_3</name>
+              <description>This bits stores key_3 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_4</name>
+          <description>Key material key_4 configure register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_4</name>
+              <description>This bits stores key_4 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_5</name>
+          <description>Key material key_5 configure register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_5</name>
+              <description>This bits stores key_5 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_6</name>
+          <description>Key material key_6 configure register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_6</name>
+              <description>This bits stores key_6 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>KEY_7</name>
+          <description>Key material key_7 configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_7</name>
+              <description>This bits stores key_7 that is a part of key material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_0</name>
+          <description>source text material text_in_0 configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_0</name>
+              <description>This bits stores text_in_0 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_1</name>
+          <description>source text material text_in_1 configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_1</name>
+              <description>This bits stores text_in_1 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_2</name>
+          <description>source text material text_in_2 configure register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_2</name>
+              <description>This bits stores text_in_2 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_IN_3</name>
+          <description>source text material text_in_3 configure register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_3</name>
+              <description>This bits stores text_in_3 that is a part of source text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_0</name>
+          <description>result text material text_out_0 configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_0</name>
+              <description>This bits stores text_out_0 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_1</name>
+          <description>result text material text_out_1 configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_1</name>
+              <description>This bits stores text_out_1 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_2</name>
+          <description>result text material text_out_2 configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_2</name>
+              <description>This bits stores text_out_2 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEXT_OUT_3</name>
+          <description>result text material text_out_3 configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_3</name>
+              <description>This bits stores text_out_3 that is a part of result text material.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>AES Mode register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENDIAN</name>
+          <description>AES Endian configure register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENDIAN</name>
+              <description>endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out endian or out_stream endian</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>AES trigger register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRIGGER</name>
+              <description>Set this bit to start AES calculation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>AES state register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>IV_MEM[%s]</name>
+          <description>The memory that stores initialization vector</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>H_MEM[%s]</name>
+          <description>The memory that stores GCM hash subkey</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>J0_MEM[%s]</name>
+          <description>The memory that stores J0</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>T0_MEM[%s]</name>
+          <description>The memory that stores T0</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>DMA_ENABLE</name>
+          <description>DMA-AES working mode register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_ENABLE</name>
+              <description>1'b0: typical AES working mode, 1'b1: DMA-AES working mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_MODE</name>
+          <description>AES cipher block mode register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_MODE</name>
+              <description>Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_NUM</name>
+          <description>AES block number register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_NUM</name>
+              <description>Those bits stores the number of Plaintext/ciphertext block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INC_SEL</name>
+          <description>Standard incrementing function configure register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INC_SEL</name>
+              <description>This bit decides the standard incrementing function. 0: INC32. 1: INC128.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AAD_BLOCK_NUM</name>
+          <description>Additional Authential Data block number register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AAD_BLOCK_NUM</name>
+              <description>Those bits stores the number of AAD block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REMAINDER_BIT_NUM</name>
+          <description>AES remainder bit number register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REMAINDER_BIT_NUM</name>
+              <description>Those bits stores the number of remainder bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE</name>
+          <description>AES continue register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE</name>
+              <description>Set this bit to continue GCM operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLEAR</name>
+          <description>AES Interrupt clear register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_CLEAR</name>
+              <description>Set this bit to clear the AES interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>AES Interrupt enable register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_ENA</name>
+              <description>Set this bit to enable interrupt that occurs when DMA-AES calculation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>AES version control register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20191210</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This bits stores the version information of AES.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_EXIT</name>
+          <description>AES-DMA exit config</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_EXIT</name>
+              <description>Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>APB_SARADC</name>
+      <description>Successive Approximation Register Analog to Digital Converter</description>
+      <groupName>APB_SARADC</groupName>
+      <baseAddress>0x60040000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x70</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>APB_ADC</name>
+        <value>43</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40038240</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_START_FORCE</name>
+              <description>select software enable saradc sample</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_START</name>
+              <description>software enable saradc sample</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_GATED</name>
+              <description>SAR clock gated</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_DIV</name>
+              <description>SAR clock divider</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_PATT_P_CLEAR</name>
+              <description>clear the pointer of pattern table for DIG ADC1 CTRL</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_XPD_SAR_FORCE</name>
+              <description>force option to xpd sar blocks</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC2_PWDET_DRV</name>
+              <description>enable saradc2 power detect driven func.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_WAIT_ARB_CYCLE</name>
+              <description>wait arbit signal stable after sar_done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000A1FE</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_MEAS_NUM_LIMIT</name>
+              <description>enable max meas num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_MAX_MEAS_NUM</name>
+              <description>max conversion number</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_INV</name>
+              <description>1: data to DIG ADC1 CTRL is inverted, otherwise not</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_INV</name>
+              <description>1: data to DIG ADC2 CTRL is inverted, otherwise not</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_TARGET</name>
+              <description>to set saradc timer target</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_EN</name>
+              <description>to enable saradc timer trigger</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL1</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_FILTER_FACTOR1</name>
+              <description>Factor of saradc filter1</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_FILTER_FACTOR0</name>
+              <description>Factor of saradc filter0</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_WAIT</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FF0808</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_XPD_WAIT</name>
+              <description>saradc_xpd_wait</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_RSTB_WAIT</name>
+              <description>saradc_rstb_wait</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_STANDBY_WAIT</name>
+              <description>saradc_standby_wait</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20000000</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_STATUS</name>
+              <description>saradc1 status about data and channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20000000</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_STATUS</name>
+              <description>saradc2 status about data and channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PATT_TAB1</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PATT_TAB2</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_SAR_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ONETIME_SAMPLE</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1A000000</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_ONETIME_ATTEN</name>
+              <description>configure onetime atten</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_ONETIME_CHANNEL</name>
+              <description>configure onetime channel</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_ONETIME_START</name>
+              <description>trigger adc onetime sample</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC2_ONETIME_SAMPLE</name>
+              <description>enable adc2 onetime sample</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC1_ONETIME_SAMPLE</name>
+              <description>enable adc1 onetime sample</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000900</resetValue>
+          <fields>
+            <field>
+              <name>ADC_ARB_APB_FORCE</name>
+              <description>adc2 arbiter force to enableapb controller</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_FORCE</name>
+              <description>adc2 arbiter force to enable rtc controller</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_FORCE</name>
+              <description>adc2 arbiter force to enable wifi controller</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_GRANT_FORCE</name>
+              <description>adc2 arbiter force grant</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_APB_PRIORITY</name>
+              <description>Set adc2 arbiterapb priority</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_PRIORITY</name>
+              <description>Set adc2 arbiter rtc priority</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_PRIORITY</name>
+              <description>Set adc2 arbiter wifi priority</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_FIX_PRIORITY</name>
+              <description>adc2 arbiter uses fixed priority</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL0</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03740000</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_FILTER_CHANNEL1</name>
+              <description>configure filter1 to adc channel</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_FILTER_CHANNEL0</name>
+              <description>configure filter0 to adc channel</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_FILTER_RESET</name>
+              <description>enable apb_adc1_filter</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1DATA_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC1_DATA</name>
+              <description>saradc1 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2DATA_STATUS</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC2_DATA</name>
+              <description>saradc2 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES0_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES0_CHANNEL</name>
+              <description>configure thres0 to adc channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH</name>
+              <description>saradc thres0 monitor thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW</name>
+              <description>saradc thres0 monitor thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES1_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES1_CHANNEL</name>
+              <description>configure thres1 to adc channel</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH</name>
+              <description>saradc thres1 monitor thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW</name>
+              <description>saradc thres1 monitor thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES_CTRL</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_THRES_ALL_EN</name>
+              <description>enable thres to all channel</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_EN</name>
+              <description>enable thres1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_EN</name>
+              <description>enable thres0</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_TSENS_INT_ENA</name>
+              <description>tsens low  interrupt enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_ENA</name>
+              <description>saradc thres1 low  interrupt enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_ENA</name>
+              <description>saradc thres0 low interrupt enable</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_ENA</name>
+              <description>saradc thres1 high interrupt enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_ENA</name>
+              <description>saradc thres0 high interrupt enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ENA</name>
+              <description>saradc2 done interrupt enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ENA</name>
+              <description>saradc1 done interrupt enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_TSENS_INT_RAW</name>
+              <description>saradc tsens  interrupt raw</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_RAW</name>
+              <description>saradc thres1 low  interrupt raw</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_RAW</name>
+              <description>saradc thres0 low interrupt raw</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_RAW</name>
+              <description>saradc thres1 high interrupt raw</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_RAW</name>
+              <description>saradc thres0 high interrupt raw</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_RAW</name>
+              <description>saradc2 done interrupt raw</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_RAW</name>
+              <description>saradc1 done interrupt raw</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_TSENS_INT_ST</name>
+              <description>saradc tsens  interrupt state</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_ST</name>
+              <description>saradc thres1 low  interrupt state</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_ST</name>
+              <description>saradc thres0 low interrupt state</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_ST</name>
+              <description>saradc thres1 high interrupt state</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_ST</name>
+              <description>saradc thres0 high interrupt state</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ST</name>
+              <description>saradc2 done interrupt state</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ST</name>
+              <description>saradc1 done interrupt state</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>digital saradc int register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC_TSENS_INT_CLR</name>
+              <description>saradc tsens  interrupt clear</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_LOW_INT_CLR</name>
+              <description>saradc thres1 low  interrupt clear</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_LOW_INT_CLR</name>
+              <description>saradc thres0 low interrupt clear</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES1_HIGH_INT_CLR</name>
+              <description>saradc thres1 high interrupt clear</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC_THRES0_HIGH_INT_CLR</name>
+              <description>saradc thres0 high interrupt clear</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_CLR</name>
+              <description>saradc2 done interrupt clear</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_CLR</name>
+              <description>saradc1 done interrupt clear</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>APB_ADC_EOF_NUM</name>
+              <description>the dma_in_suc_eof gen when sample cnt = spi_eof_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_RESET_FSM</name>
+              <description>reset_apb_adc_state</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_TRANS</name>
+              <description>enable apb_adc use spi_dma</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKM_CONF</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_B</name>
+              <description>Fractional clock divider numerator value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_A</name>
+              <description>Fractional clock divider denominator value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg clk en</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_SEL</name>
+              <description>Set this bit to enable clk_apll</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_TSENS_CTRL</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018080</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_OUT</name>
+              <description>temperature sensor data out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_IN_INV</name>
+              <description>invert temperature sensor data</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_DIV</name>
+              <description>temperature sensor clock divider</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_PU</name>
+              <description>temperature sensor power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TSENS_CTRL2</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004002</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_XPD_WAIT</name>
+              <description>the time that power up tsens need wait</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_XPD_FORCE</name>
+              <description>force power up tsens</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_INV</name>
+              <description>inv tsens clk</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_SEL</name>
+              <description>tsens clk select</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CALI</name>
+          <description>digital saradc configure register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>APB_SARADC_CALI_CFG</name>
+              <description>saradc cali factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_TSENS_WAKE</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>WAKEUP_TH_LOW</name>
+              <description>reg_wakeup_th_low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_TH_HIGH</name>
+              <description>reg_wakeup_th_high</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_OVER_UPPER_TH</name>
+              <description>reg_wakeup_over_upper_th</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_MODE</name>
+              <description>reg_wakeup_mode</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_EN</name>
+              <description>reg_wakeup_en</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_TSENS_SAMPLE</name>
+          <description>digital tsens configure register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000014</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_SAMPLE_RATE</name>
+              <description>HW sample rate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_SAMPLE_EN</name>
+              <description>HW sample en</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL_DATE</name>
+          <description>version</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206240</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ASSIST_DEBUG</name>
+      <description>Debug Assist</description>
+      <groupName>ASSIST_DEBUG</groupName>
+      <baseAddress>0x600CE000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>C0RE_0_INTR_ENA</name>
+          <description>core0 monitor enable configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_ENA</name>
+              <description>Core0 dram0 area0 read monitor enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_ENA</name>
+              <description>Core0 dram0 area0 write monitor enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_ENA</name>
+              <description>Core0 dram0 area1 read monitor enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_ENA</name>
+              <description>Core0 dram0 area1 write monitor enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_ENA</name>
+              <description>Core0 PIF area0 read monitor enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_ENA</name>
+              <description>Core0 PIF area0 write monitor enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_ENA</name>
+              <description>Core0 PIF area1 read monitor enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_ENA</name>
+              <description>Core0 PIF area1 write monitor enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_ENA</name>
+              <description>Core0 stackpoint underflow monitor enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_ENA</name>
+              <description>Core0 stackpoint overflow monitor enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>IBUS busy monitor enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>DBUS busy monitor enbale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_RAW</name>
+          <description>core0 monitor interrupt status register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_RAW</name>
+              <description>Core0 dram0 area0 read monitor interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_RAW</name>
+              <description>Core0 dram0 area0 write monitor interrupt status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_RAW</name>
+              <description>Core0 dram0 area1 read monitor interrupt status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_RAW</name>
+              <description>Core0 dram0 area1 write monitor interrupt status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_RAW</name>
+              <description>Core0 PIF area0 read monitor interrupt status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_RAW</name>
+              <description>Core0 PIF area0 write monitor interrupt status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_RAW</name>
+              <description>Core0 PIF area1 read monitor interrupt status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_RAW</name>
+              <description>Core0 PIF area1 write monitor interrupt status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_RAW</name>
+              <description>Core0 stackpoint underflow monitor interrupt status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_RAW</name>
+              <description>Core0 stackpoint overflow monitor interrupt status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>IBUS busy monitor interrupt status</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>DBUS busy monitor initerrupt status</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_RLS</name>
+          <description>core0 monitor interrupt enable register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_RLS</name>
+              <description>Core0 dram0 area0 read monitor interrupt enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_RLS</name>
+              <description>Core0 dram0 area0 write monitor interrupt enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_RLS</name>
+              <description>Core0 dram0 area1 read monitor interrupt enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_RLS</name>
+              <description>Core0 dram0 area1 write monitor interrupt enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_RLS</name>
+              <description>Core0 PIF area0 read monitor interrupt enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_RLS</name>
+              <description>Core0 PIF area0 write monitor interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_RLS</name>
+              <description>Core0 PIF area1 read monitor interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_RLS</name>
+              <description>Core0 PIF area1 write monitor interrupt enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_RLS</name>
+              <description>Core0 stackpoint underflow monitor interrupt enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_RLS</name>
+              <description>Core0 stackpoint overflow monitor interrupt enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>IBUS busy monitor interrupt enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>DBUS busy monitor interrupt enbale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTR_CLR</name>
+          <description>core0 monitor interrupt clr register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_CLR</name>
+              <description>Core0 dram0 area0 read monitor interrupt clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_CLR</name>
+              <description>Core0 dram0 area0 write monitor interrupt clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_CLR</name>
+              <description>Core0 dram0 area1 read monitor interrupt clr</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_CLR</name>
+              <description>Core0 dram0 area1 write monitor interrupt clr</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_CLR</name>
+              <description>Core0 PIF area0 read monitor interrupt clr</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_CLR</name>
+              <description>Core0 PIF area0 write monitor interrupt clr</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_CLR</name>
+              <description>Core0 PIF area1 read monitor interrupt clr</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_CLR</name>
+              <description>Core0 PIF area1 write monitor interrupt clr</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_CLR</name>
+              <description>Core0 stackpoint underflow monitor interrupt clr</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_CLR</name>
+              <description>Core0 stackpoint overflow monitor interrupt clr</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>IBUS busy monitor interrupt clr</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>DBUS busy monitor interrupt clr</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_0_MIN</name>
+          <description>core0 dram0 region0 addr configuration register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_MIN</name>
+              <description>Core0 dram0 region0 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_0_MAX</name>
+          <description>core0 dram0 region0 addr configuration register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_MAX</name>
+              <description>Core0 dram0 region0 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_1_MIN</name>
+          <description>core0 dram0 region1 addr configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_MIN</name>
+              <description>Core0 dram0 region1 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_1_MAX</name>
+          <description>core0 dram0 region1 addr configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_MAX</name>
+              <description>Core0 dram0 region1 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_0_MIN</name>
+          <description>core0 PIF region0 addr configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_0_MIN</name>
+              <description>Core0 PIF region0 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_0_MAX</name>
+          <description>core0 PIF region0 addr configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_0_MAX</name>
+              <description>Core0 PIF region0 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_1_MIN</name>
+          <description>core0 PIF region1 addr configuration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_1_MIN</name>
+              <description>Core0 PIF region1 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_1_MAX</name>
+          <description>core0 PIF region1 addr configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_1_MAX</name>
+              <description>Core0 PIF region1 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PC</name>
+          <description>core0 area pc status register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PC</name>
+              <description>the stackpointer when first touch region monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_SP</name>
+          <description>core0 area sp status register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_SP</name>
+              <description>the PC when first touch region monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MIN</name>
+          <description>stack min value</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MIN</name>
+              <description>core0 sp region configuration regsiter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MAX</name>
+          <description>stack max value</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MAX</name>
+              <description>core0 sp pc status register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_PC</name>
+          <description>stack monitor pc status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_PC</name>
+              <description>This regsiter stores the PC when trigger stack monitor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_EN</name>
+          <description>record enable configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_RECORDEN</name>
+              <description>Set 1 to enable record PC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_RCD_PDEBUGEN</name>
+              <description>Set 1 to enable cpu pdebug function, must set this bit can get cpu PC</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGPC</name>
+          <description>record status regsiter</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGPC</name>
+              <description>recorded PC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGSP</name>
+          <description>record status regsiter</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGSP</name>
+              <description>recorded sp</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_EXCEPTION_MONITOR_0</name>
+          <description>exception monitor status register0</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_ADDR_0</name>
+              <description>reg_core_0_iram0_recording_addr_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_WR_0</name>
+              <description>reg_core_0_iram0_recording_wr_0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_LOADSTORE_0</name>
+              <description>reg_core_0_iram0_recording_loadstore_0</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_EXCEPTION_MONITOR_1</name>
+          <description>exception monitor status register1</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_ADDR_1</name>
+              <description>reg_core_0_iram0_recording_addr_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_WR_1</name>
+              <description>reg_core_0_iram0_recording_wr_1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_LOADSTORE_1</name>
+              <description>reg_core_0_iram0_recording_loadstore_1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_0</name>
+          <description>exception monitor status register2</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_ADDR_0</name>
+              <description>reg_core_0_dram0_recording_addr_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_WR_0</name>
+              <description>reg_core_0_dram0_recording_wr_0</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_BYTEEN_0</name>
+              <description>reg_core_0_dram0_recording_byteen_0</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_1</name>
+          <description>exception monitor status register3</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_PC_0</name>
+              <description>reg_core_0_dram0_recording_pc_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_2</name>
+          <description>exception monitor status register4</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_ADDR_1</name>
+              <description>reg_core_0_dram0_recording_addr_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_WR_1</name>
+              <description>reg_core_0_dram0_recording_wr_1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_BYTEEN_1</name>
+              <description>reg_core_0_dram0_recording_byteen_1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_3</name>
+          <description>exception monitor status register5</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_PC_1</name>
+              <description>reg_core_0_dram0_recording_pc_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0</name>
+          <description>exception monitor status register6</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0</name>
+              <description>reg_core_x_iram0_dram0_limit_cycle_0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1</name>
+          <description>exception monitor status register7</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1</name>
+              <description>reg_core_x_iram0_dram0_limit_cycle_1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C0RE_0_LASTPC_BEFORE_EXCEPTION</name>
+          <description>cpu status register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_LASTPC_BEFORE_EXC</name>
+              <description>cpu's lastpc before exception</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>C0RE_0_DEBUG_MODE</name>
+          <description>cpu status register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DEBUG_MODE</name>
+              <description>cpu debug mode status, 1 means cpu enter debug mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DEBUG_MODULE_ACTIVE</name>
+              <description>cpu debug_module active status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set 1 force on the clock gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02109130</resetValue>
+          <fields>
+            <field>
+              <name>ASSIST_DEBUG_DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GDMA</name>
+      <description>DMA (Direct Memory Access) Controller</description>
+      <groupName>DMA</groupName>
+      <baseAddress>0x6003F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1A4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMA_CH0</name>
+        <value>44</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_CH1</name>
+        <value>45</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>IN_INT_RAW_CH%s</name>
+          <description>Raw status interrupt of channel 0</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_CH_INT_RAW</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_CH_INT_RAW</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>IN_INT_ST_CH%s</name>
+          <description>Masked interrupt of channel 0</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>IN_INT_ENA_CH%s</name>
+          <description>Interrupt enable bits of channel 0</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>IN_INT_CLR_CH%s</name>
+          <description>Interrupt clear bits of channel 0</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_CH_INT_CLR</name>
+              <description>Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_CH_INT_CLR</name>
+              <description>Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_CH_INT_CLR</name>
+              <description>Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>OUT_INT_RAW_CH%s</name>
+          <description>Raw status interrupt of channel 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_CH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_CH_INT_RAW</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_CH_INT_RAW</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>OUT_INT_ST_CH%s</name>
+          <description>Masked interrupt of channel 0</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_CH_INT_ST</name>
+              <description>The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>OUT_INT_ENA_CH%s</name>
+          <description>Interrupt enable bits of channel 0</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_CH_INT_ENA</name>
+              <description>The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>OUT_INT_CLR_CH%s</name>
+          <description>Interrupt clear bits of channel 0</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_CH_INT_CLR</name>
+              <description>Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_TEST</name>
+          <description>reserved</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHB_TESTMODE</name>
+              <description>reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_TESTADDR</name>
+              <description>reserved</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC_CONF</name>
+          <description>MISC register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHBM_RST_INTER</name>
+              <description>Set this bit then clear this bit to reset the internal ahb FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_PRI_DIS</name>
+              <description>Set this bit to disable priority arbitration function.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02202250</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_CONF0_CH%s</name>
+          <description>Configure 0 register of Rx channel 0</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_RST_CH</name>
+              <description>This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST_CH</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN_CH</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DATA_BURST_EN_CH</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN_CH</name>
+              <description>Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ETM_EN_CH</name>
+              <description>Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_CONF1_CH%s</name>
+          <description>Configure 1 register of Rx channel 0</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_CHECK_OWNER_CH</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>INFIFO_STATUS_CH%s</name>
+          <description>Receive FIFO status of Rx channel 0</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800003</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_FULL_CH</name>
+              <description>L1 Rx FIFO full signal for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_EMPTY_CH</name>
+              <description>L1 Rx FIFO empty signal for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT_CH</name>
+              <description>The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_1B_CH</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_2B_CH</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_3B_CH</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_4B_CH</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_BUF_HUNGRY_CH</name>
+              <description>reserved</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_POP_CH%s</name>
+          <description>Pop control register of Rx channel 0</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA_CH</name>
+              <description>This register stores the data popping from DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP_CH</name>
+              <description>Set this bit to pop data from DMA FIFO.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_LINK_CH%s</name>
+          <description>Link descriptor configure and control register of Rx channel 0</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01100000</resetValue>
+          <fields>
+            <field>
+              <name>INLINK_ADDR_CH</name>
+              <description>This register stores the 20 least significant bits of the first inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET_CH</name>
+              <description>Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP_CH</name>
+              <description>Set this bit to stop dealing with the inlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INLINK_START_CH</name>
+              <description>Set this bit to start dealing with the inlink descriptors.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART_CH</name>
+              <description>Set this bit to mount a new inlink descriptor.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INLINK_PARK_CH</name>
+              <description>1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_STATE_CH%s</name>
+          <description>Receive status of Rx channel 0</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_ADDR_CH</name>
+              <description>This register stores the current inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_STATE_CH</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_STATE_CH</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_SUC_EOF_DES_ADDR_CH%s</name>
+          <description>Inlink descriptor address when EOF occurs of Rx channel 0</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR_CH</name>
+              <description>This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_ERR_EOF_DES_ADDR_CH%s</name>
+          <description>Inlink descriptor address when errors occur of Rx channel 0</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_ERR_EOF_DES_ADDR_CH</name>
+              <description>This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_DSCR_CH%s</name>
+          <description>Current inlink descriptor address of Rx channel 0</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_CH</name>
+              <description>The address of the current inlink descriptor x.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_DSCR_BF0_CH%s</name>
+          <description>The last inlink descriptor address of Rx channel 0</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0_CH</name>
+              <description>The address of the last inlink descriptor x-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_DSCR_BF1_CH%s</name>
+          <description>The second-to-last inlink descriptor address of Rx channel 0</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1_CH</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_PRI_CH%s</name>
+          <description>Priority register of Rx channel 0</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_PRI_CH</name>
+              <description>The priority of Rx channel 0. The larger of the value the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_PERI_SEL_CH%s</name>
+          <description>Peripheral selection of Rx channel 0</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_IN_SEL_CH</name>
+              <description>This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_CONF1_CH%s</name>
+          <description>Configure 1 register of Tx channel 0</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_CHECK_OWNER_CH</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUTFIFO_STATUS_CH%s</name>
+          <description>Transmit FIFO status of Tx channel 0</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07800002</resetValue>
+          <fields>
+            <field>
+              <name>OUTFIFO_FULL_CH</name>
+              <description>L1 Tx FIFO full signal for Tx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY_CH</name>
+              <description>L1 Tx FIFO empty signal for Tx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT_CH</name>
+              <description>The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_1B_CH</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_2B_CH</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_3B_CH</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_4B_CH</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_PUSH_CH%s</name>
+          <description>Push control register of Rx channel 0</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA_CH</name>
+              <description>This register stores the data that need to be pushed into DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH_CH</name>
+              <description>Set this bit to push data into DMA FIFO.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_LINK_CH%s</name>
+          <description>Link descriptor configure and control register of Tx channel 0</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR_CH</name>
+              <description>This register stores the 20 least significant bits of the first outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP_CH</name>
+              <description>Set this bit to stop dealing with the outlink descriptors.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_START_CH</name>
+              <description>Set this bit to start dealing with the outlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART_CH</name>
+              <description>Set this bit to restart a new outlink from the last address.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK_CH</name>
+              <description>1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_STATE_CH%s</name>
+          <description>Transmit status of Tx channel 0</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_ADDR_CH</name>
+              <description>This register stores the current outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_STATE_CH</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_STATE_CH</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_EOF_DES_ADDR_CH%s</name>
+          <description>Outlink descriptor address when EOF occurs of Tx channel 0</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR_CH</name>
+              <description>This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_EOF_BFR_DES_ADDR_CH%s</name>
+          <description>The last outlink descriptor address when EOF occurs of Tx channel 0</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR_CH</name>
+              <description>This register stores the address of the outlink descriptor before the last outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_DSCR_CH%s</name>
+          <description>Current inlink descriptor address of Tx channel 0</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_CH</name>
+              <description>The address of the current outlink descriptor y.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_DSCR_BF0_CH%s</name>
+          <description>The last inlink descriptor address of Tx channel 0</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0_CH</name>
+              <description>The address of the last outlink descriptor y-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_DSCR_BF1_CH%s</name>
+          <description>The second-to-last inlink descriptor address of Tx channel 0</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1_CH</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_PRI_CH%s</name>
+          <description>Priority register of Tx channel 0.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_PRI_CH</name>
+              <description>The priority of Tx channel 0. The larger of the value the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_PERI_SEL_CH%s</name>
+          <description>Peripheral selection of Tx channel 0</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_OUT_SEL_CH</name>
+              <description>This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_CONF0_CH%s</name>
+          <description>Configure 0 register of Tx channel 1</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>OUT_RST_CH</name>
+              <description>This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST_CH</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK_CH</name>
+              <description>Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE_CH</name>
+              <description>EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN_CH</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN_CH</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_ETM_EN_CH</name>
+              <description>Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DS</name>
+      <description>Digital Signature</description>
+      <groupName>DS</groupName>
+      <baseAddress>0x6008C000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA5C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Y_MEM[%s]</name>
+          <description>memory that stores Y</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>memory that stores M</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>RB_MEM[%s]</name>
+          <description>memory that stores Rb</description>
+          <addressOffset>0x400</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>48</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>BOX_MEM[%s]</name>
+          <description>memory that stores BOX</description>
+          <addressOffset>0x600</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>IV_MEM[%s]</name>
+          <description>memory that stores IV</description>
+          <addressOffset>0x630</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>X_MEM[%s]</name>
+          <description>memory that stores X</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Z_MEM[%s]</name>
+          <description>memory that stores Z</description>
+          <addressOffset>0xA00</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>SET_START</name>
+          <description>DS start control register</description>
+          <addressOffset>0xE00</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>set this bit to start DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_CONTINUE</name>
+          <description>DS continue control register</description>
+          <addressOffset>0xE04</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_CONTINUE</name>
+              <description>set this bit to continue DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_FINISH</name>
+          <description>DS finish control register</description>
+          <addressOffset>0xE08</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_FINISH</name>
+              <description>Set this bit to finish DS process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>DS query busy register</description>
+          <addressOffset>0xE0C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_BUSY</name>
+              <description>digital signature state. 1'b0: idle, 1'b1: busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_KEY_WRONG</name>
+          <description>DS query key-wrong counter register</description>
+          <addressOffset>0xE10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_KEY_WRONG</name>
+              <description>digital signature key wrong counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_CHECK</name>
+          <description>DS query check result register</description>
+          <addressOffset>0xE14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MD_ERROR</name>
+              <description>MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PADDING_BAD</name>
+              <description>padding checkout result. 1'b0: a good padding, 1'b1: a bad padding</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>DS version control register</description>
+          <addressOffset>0xE20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200618</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>ds version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>ECC</name>
+      <description>ECC (ECC Hardware Accelerator)</description>
+      <groupName>ECC</groupName>
+      <baseAddress>0x60039000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x78</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>MULT_INT_RAW</name>
+          <description>ECC interrupt raw register, valid in level.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the ecc_calc_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_INT_ST</name>
+          <description>ECC interrupt status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the ecc_calc_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_INT_ENA</name>
+          <description>ECC interrupt enable register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the ecc_calc_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_INT_CLR</name>
+          <description>ECC interrupt clear register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CALC_DONE_INT_CLR</name>
+              <description>Set this bit to clear the ecc_calc_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_CONF</name>
+          <description>ECC configure register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESET</name>
+              <description>Write 1 to reset ECC Accelerator.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>KEY_LENGTH</name>
+              <description>The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MOD_BASE</name>
+              <description>The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve)</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WORK_MODE</name>
+              <description>The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SECURITY_MODE</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VERIFICATION_RESULT</name>
+              <description>The verification result bit of ECC Accelerator, only valid when calculation is done.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Write 1 to force on register clock gate.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLOCK_GATE_FORCE_ON</name>
+              <description>ECC memory clock gate force on register</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02207180</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>ECC mult version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>K_MEM[%s]</name>
+          <description>The memory that stores k.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PX_MEM[%s]</name>
+          <description>The memory that stores Px.</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>PY_MEM[%s]</name>
+          <description>The memory that stores Py.</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x8</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EFUSE</name>
+      <description>eFuse Controller</description>
+      <groupName>EFUSE</groupName>
+      <baseAddress>0x6001A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1D0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EFUSE</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PGM_DATA0</name>
+          <description>Register 0 that stores data to be programmed.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_0</name>
+              <description>Configures the 0th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA1</name>
+          <description>Register 1 that stores data to be programmed.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_1</name>
+              <description>Configures the 1st 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA2</name>
+          <description>Register 2 that stores data to be programmed.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_2</name>
+              <description>Configures the 2nd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA3</name>
+          <description>Register 3 that stores data to be programmed.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_3</name>
+              <description>Configures the 3rd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA4</name>
+          <description>Register 4 that stores data to be programmed.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_4</name>
+              <description>Configures the 4th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA5</name>
+          <description>Register 5 that stores data to be programmed.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_5</name>
+              <description>Configures the 5th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA6</name>
+          <description>Register 6 that stores data to be programmed.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_6</name>
+              <description>Configures the 6th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA7</name>
+          <description>Register 7 that stores data to be programmed.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_7</name>
+              <description>Configures the 7th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE0</name>
+          <description>Register 0 that stores the RS code to be programmed.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_0</name>
+              <description>Configures the 0th 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE1</name>
+          <description>Register 1 that stores the RS code to be programmed.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_1</name>
+              <description>Configures the 1st 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE2</name>
+          <description>Register 2 that stores the RS code to be programmed.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_2</name>
+              <description>Configures the 2nd 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_WR_DIS</name>
+          <description>BLOCK0 data register 0.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_DIS</name>
+              <description>Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA0</name>
+          <description>BLOCK0 data register 1.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS</name>
+              <description>Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_4</name>
+              <description>Reserved.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE</name>
+              <description>Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_JTAG</name>
+              <description>Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWERGLITCH_EN</name>
+              <description>Represents whether power glitch function is enabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_SERIAL_JTAG</name>
+              <description>Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD</name>
+              <description>Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOWNLOAD_MSPI_DIS</name>
+              <description>Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_CAN</name>
+              <description>Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>JTAG_SEL_ENABLE</name>
+              <description>Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG</name>
+              <description>Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG</name>
+              <description>Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH</name>
+              <description>Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL</name>
+              <description>Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS</name>
+              <description>Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_AS_GPIO</name>
+              <description>Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_2</name>
+              <description>Reserved.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_1</name>
+              <description>Reserved.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_0</name>
+              <description>Reserved.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA1</name>
+          <description>BLOCK0 data register 2.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED1_1</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL</name>
+              <description>Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT</name>
+              <description>Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0</name>
+              <description>Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1</name>
+              <description>Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2</name>
+              <description>Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0</name>
+              <description>Represents the purpose of Key0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1</name>
+              <description>Represents the purpose of Key1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA2</name>
+          <description>BLOCK0 data register 3.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000C0000</resetValue>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2</name>
+              <description>Represents the purpose of Key2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3</name>
+              <description>Represents the purpose of Key3.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4</name>
+              <description>Represents the purpose of Key4.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5</name>
+              <description>Represents the purpose of Key5.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEC_DPA_LEVEL</name>
+              <description>Represents the spa secure level by configuring the clock random divide mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECDSA_FORCE_USE_HARDWARE_K</name>
+              <description>Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRYPT_DPA_ENABLE</name>
+              <description>Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN</name>
+              <description>Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE</name>
+              <description>Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED2_0</name>
+              <description>Reserved.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW</name>
+              <description>Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA3</name>
+          <description>BLOCK0 data register 4.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE</name>
+              <description>Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DIRECT_BOOT</name>
+              <description>Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_PRINT</name>
+              <description>Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_5</name>
+              <description>Reserved.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE</name>
+              <description>Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD</name>
+              <description>Represents whether security download is enabled or disabled. 1: enabled. 0: disabled.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL</name>
+              <description>Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME</name>
+              <description>Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION</name>
+              <description>Represents the version used by ESP-IDF anti-rollback feature.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_DISABLE_FAST_WAKE</name>
+              <description>Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HYS_EN_PAD0</name>
+              <description>Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA4</name>
+          <description>BLOCK0 data register 5.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HYS_EN_PAD1</name>
+              <description>Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED4_1</name>
+              <description>Reserved.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED4_0</name>
+              <description>Reserved.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SYS_0</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_0</name>
+              <description>Stores the low 32 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SYS_1</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_1</name>
+              <description>Stores the high 16 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAC_EXT</name>
+              <description>Stores the extended bits of MAC address.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SYS_2</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_RESERVED_1</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAC_RESERVED_0</name>
+              <description>Reserved.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SYS_3</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_RESERVED_2</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_DATA_PART0_0</name>
+              <description>Stores the first 14 bits of the zeroth part of system data.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SYS_4</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_1</name>
+              <description>Stores the first 32 bits of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SYS_5</name>
+          <description>BLOCK1 data register $n.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_2</name>
+              <description>Stores the second 32 bits of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA0</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_0</name>
+              <description>Stores the zeroth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA1</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_1</name>
+              <description>Stores the first 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA2</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_2</name>
+              <description>Stores the second 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA3</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_3</name>
+              <description>Stores the third 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA4</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_4</name>
+              <description>Stores the fourth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA5</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_5</name>
+              <description>Stores the fifth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA6</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_6</name>
+              <description>Stores the sixth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA7</name>
+          <description>Register $n of BLOCK2 (system).</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_7</name>
+              <description>Stores the seventh 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA0</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA0</name>
+              <description>Stores the zeroth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA1</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA1</name>
+              <description>Stores the first 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA2</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA2</name>
+              <description>Stores the second 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA3</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA3</name>
+              <description>Stores the third 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA4</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA4</name>
+              <description>Stores the fourth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA5</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA5</name>
+              <description>Stores the fifth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA6</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA6</name>
+              <description>Stores the sixth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA7</name>
+          <description>Register $n of BLOCK3 (user).</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA7</name>
+              <description>Stores the seventh 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA0</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA1</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA1</name>
+              <description>Stores the first 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA2</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA2</name>
+              <description>Stores the second 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA3</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA3</name>
+              <description>Stores the third 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA4</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA5</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA6</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA7</name>
+          <description>Register $n of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA0</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA1</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA1</name>
+              <description>Stores the first 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA2</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA2</name>
+              <description>Stores the second 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA3</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA3</name>
+              <description>Stores the third 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA4</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA5</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA6</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA7</name>
+          <description>Register $n of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA0</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA1</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA1</name>
+              <description>Stores the first 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA2</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA2</name>
+              <description>Stores the second 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA3</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA3</name>
+              <description>Stores the third 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA4</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA5</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA6</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA7</name>
+          <description>Register $n of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA0</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA1</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA1</name>
+              <description>Stores the first 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA2</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA2</name>
+              <description>Stores the second 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA3</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA3</name>
+              <description>Stores the third 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA4</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA5</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA6</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA7</name>
+          <description>Register $n of BLOCK7 (KEY3).</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA0</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA1</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA1</name>
+              <description>Stores the first 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA2</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA2</name>
+              <description>Stores the second 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA3</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA3</name>
+              <description>Stores the third 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA4</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA5</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA6</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA7</name>
+          <description>Register $n of BLOCK8 (KEY4).</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA0</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA1</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA1</name>
+              <description>Stores the first 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA2</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA2</name>
+              <description>Stores the second 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA3</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA3</name>
+              <description>Stores the third 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA4</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA5</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA6</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA7</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA0</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_0</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA1</name>
+          <description>Register $n of BLOCK9 (KEY5).</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_1</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA2</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_2</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA3</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_3</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA4</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_4</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA5</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_5</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA6</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_6</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA7</name>
+          <description>Register $n of BLOCK10 (system).</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_7</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR0</name>
+          <description>Programming error record register 0 of BLOCK0.</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS_ERR</name>
+              <description>Indicates a programming error of RD_DIS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR_4</name>
+              <description>Reserved.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE_ERR</name>
+              <description>Indicates a programming error of DIS_ICACHE.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_JTAG_ERR</name>
+              <description>Indicates a programming error of DIS_USB_JTAG.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWERGLITCH_EN_ERR</name>
+              <description>Indicates a programming error of POWERGLITCH_EN.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_SERIAL_JTAG_ERR</name>
+              <description>Indicates a programming error of DIS_USB_DEVICE.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD_ERR</name>
+              <description>Indicates a programming error of DIS_FORCE_DOWNLOAD.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOWNLOAD_MSPI_DIS_ERR</name>
+              <description>Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_TWAI_ERR</name>
+              <description>Indicates a programming error of DIS_CAN.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>JTAG_SEL_ENABLE_ERR</name>
+              <description>Indicates a programming error of JTAG_SEL_ENABLE.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG_ERR</name>
+              <description>Indicates a programming error of SOFT_DIS_JTAG.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG_ERR</name>
+              <description>Indicates a programming error of DIS_PAD_JTAG.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR</name>
+              <description>Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH_ERR</name>
+              <description>Indicates a programming error of USB_DREFH.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL_ERR</name>
+              <description>Indicates a programming error of USB_DREFL.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS_ERR</name>
+              <description>Indicates a programming error of USB_EXCHG_PINS.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_AS_GPIO_ERR</name>
+              <description>Indicates a programming error of VDD_SPI_AS_GPIO.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR_2</name>
+              <description>Reserved.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR_1</name>
+              <description>Reserved.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR_0</name>
+              <description>Reserved.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR1</name>
+          <description>Programming error record register 1 of BLOCK0.</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED1_ERR_0</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL_ERR</name>
+              <description>Indicates a programming error of WDT_DELAY_SEL.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT_ERR</name>
+              <description>Indicates a programming error of SPI_BOOT_CRYPT_CNT.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR2</name>
+          <description>Programming error record register 2 of BLOCK0.</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_3.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_4.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5_ERR</name>
+              <description>Indicates a programming error of KEY_PURPOSE_5.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEC_DPA_LEVEL_ERR</name>
+              <description>Indicates a programming error of SEC_DPA_LEVEL.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED2_ERR_1</name>
+              <description>Reserved.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRYPT_DPA_ENABLE_ERR</name>
+              <description>Indicates a programming error of CRYPT_DPA_ENABLE.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_EN.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED2_ERR_0</name>
+              <description>Reserved.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW_ERR</name>
+              <description>Indicates a programming error of FLASH_TPUW.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR3</name>
+          <description>Programming error record register 3 of BLOCK0.</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE_ERR</name>
+              <description>Indicates a programming error of DIS_DOWNLOAD_MODE.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DIRECT_BOOT_ERR</name>
+              <description>Indicates a programming error of DIS_DIRECT_BOOT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_PRINT_ERR</name>
+              <description>Indicates a programming error of UART_PRINT_CHANNEL.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_ERR_5</name>
+              <description>Reserved.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR</name>
+              <description>Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD_ERR</name>
+              <description>Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL_ERR</name>
+              <description>Indicates a programming error of UART_PRINT_CONTROL.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME_ERR</name>
+              <description>Indicates a programming error of FORCE_SEND_RESUME.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION_ERR</name>
+              <description>Indicates a programming error of SECURE VERSION.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_DISABLE_FAST_WAKE_ERR</name>
+              <description>Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HYS_EN_PAD0_ERR</name>
+              <description>Indicates a programming error of HYS_EN_PAD0.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR4</name>
+          <description>Programming error record register 4 of BLOCK0.</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HYS_EN_PAD1_ERR</name>
+              <description>Indicates a programming error of HYS_EN_PAD1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED4_ERR_1</name>
+              <description>Reserved.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED4_ERR_0</name>
+              <description>Reserved.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR0</name>
+          <description>Programming error record register 0 of BLOCK1-10.</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_SPI_8M_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAC_SPI_8M_FAIL</name>
+              <description>0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_FAIL</name>
+              <description>0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_FAIL</name>
+              <description>0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_FAIL</name>
+              <description>0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_FAIL</name>
+              <description>0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_FAIL</name>
+              <description>0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_FAIL</name>
+              <description>0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_FAIL</name>
+              <description>0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR1</name>
+          <description>Programming error record register 1 of BLOCK1-10.</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY5_FAIL</name>
+              <description>0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_FAIL</name>
+              <description>0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>eFuse clcok configuration register.</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to force eFuse SRAM into power-saving mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>Set this bit and force to activate clock signal of eFuse SRAM.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>Set this bit to force eFuse SRAM into working mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Set this bit to force enable eFuse register configuration clock signal.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>eFuse operation mode configuraiton register</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OP_CODE</name>
+              <description>0x5A5A:  programming operation command 0x5AA5: read operation command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CFG_ECDSA_BLK</name>
+              <description>Configures which block to use for ECDSA key output.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>eFuse status register.</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Indicates the state of the eFuse state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_LOAD_SW</name>
+              <description>The value of OTP_LOAD_SW.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_C_SYNC2</name>
+              <description>The value of OTP_VDDQ_C_SYNC2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_STROBE_SW</name>
+              <description>The value of OTP_STROBE_SW.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_CSB_SW</name>
+              <description>The value of OTP_CSB_SW.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_PGENB_SW</name>
+              <description>The value of OTP_PGENB_SW.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_IS_SW</name>
+              <description>The value of OTP_VDDQ_IS_SW.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BLK0_VALID_BIT_CNT</name>
+              <description>Indicates the number of block valid bit.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CUR_ECDSA_BLK</name>
+              <description>Indicates which block is used for ECDSA key output.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>eFuse command register.</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_CMD</name>
+              <description>Set this bit to send read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_CMD</name>
+              <description>Set this bit to send programming command.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BLK_NUM</name>
+              <description>The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>eFuse raw interrupt register.</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_RAW</name>
+              <description>The raw bit signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_RAW</name>
+              <description>The raw bit signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>eFuse interrupt status register.</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ST</name>
+              <description>The status signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ST</name>
+              <description>The status signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>eFuse interrupt enable register.</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ENA</name>
+              <description>The enable signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ENA</name>
+              <description>The enable signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>eFuse interrupt clear register.</description>
+          <addressOffset>0x1E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_CLR</name>
+              <description>The clear signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_CLR</name>
+              <description>The clear signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAC_CONF</name>
+          <description>Controls the eFuse programming voltage.</description>
+          <addressOffset>0x1E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001FE17</resetValue>
+          <fields>
+            <field>
+              <name>DAC_CLK_DIV</name>
+              <description>Controls the division factor of the rising clock of the programming voltage.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_PAD_SEL</name>
+              <description>Don't care.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_NUM</name>
+              <description>Controls the rising period of the programming voltage.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OE_CLR</name>
+              <description>Reduces the power supply of the programming voltage.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_TIM_CONF</name>
+          <description>Configures read timing parameters.</description>
+          <addressOffset>0x1EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F010201</resetValue>
+          <fields>
+            <field>
+              <name>THR_A</name>
+              <description>Configures the read hold time.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRD</name>
+              <description>Configures the read time.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSUR_A</name>
+              <description>Configures the read setup time.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>READ_INIT_NUM</name>
+              <description>Configures the waiting time of reading eFuse memory.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF1</name>
+          <description>Configurarion register 1 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01266701</resetValue>
+          <fields>
+            <field>
+              <name>TSUP_A</name>
+              <description>Configures the programming setup time.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWR_ON_NUM</name>
+              <description>Configures the power up time for VDDQ.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THP_A</name>
+              <description>Configures the programming hold time.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF2</name>
+          <description>Configurarion register 2 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00A00140</resetValue>
+          <fields>
+            <field>
+              <name>PWR_OFF_NUM</name>
+              <description>Configures the power outage time for VDDQ.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TPGM</name>
+              <description>Configures the active programming time.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF0_RS_BYPASS</name>
+          <description>Configurarion register0 of eFuse programming time parameters and rs bypass operation.</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002000</resetValue>
+          <fields>
+            <field>
+              <name>BYPASS_RS_CORRECTION</name>
+              <description>Set this bit to bypass reed solomon correction step.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BYPASS_RS_BLK_NUM</name>
+              <description>Configures block number of programming twice operation.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UPDATE</name>
+              <description>Set this bit to update multi-bit register signals.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TPGM_INACTIVE</name>
+              <description>Configures the inactive programming time.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>eFuse version register.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02208120</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Stores eFuse version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <baseAddress>0x60004000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x2A8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>GPIO</name>
+        <value>16</value>
+      </interrupt>
+      <interrupt>
+        <name>GPIO_NMI</name>
+        <value>17</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BT_SELECT</name>
+          <description>GPIO bit select register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_SEL</name>
+              <description>GPIO bit select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT</name>
+          <description>GPIO output register for GPIO0-31</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_ORIG</name>
+              <description>GPIO output register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TS</name>
+          <description>GPIO output set register for GPIO0-31</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TS</name>
+              <description>GPIO output set register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TC</name>
+          <description>GPIO output clear register for GPIO0-31</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TC</name>
+              <description>GPIO output clear register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SELECT</name>
+          <description>GPIO sdio select register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_SEL</name>
+              <description>GPIO sdio select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE</name>
+          <description>GPIO output enable register for GPIO0-31</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO output enable register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TS</name>
+          <description>GPIO output enable set register for GPIO0-31</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TS</name>
+              <description>GPIO output enable set register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <description>GPIO output enable clear register for GPIO0-31</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TC</name>
+              <description>GPIO output enable clear register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STRAP</name>
+          <description>pad strapping register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRAPPING</name>
+              <description>pad strapping register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <description>GPIO input register for GPIO0-31</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO input register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>GPIO interrupt status register for GPIO0-31</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>GPIO interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TS</name>
+          <description>GPIO interrupt status set register for GPIO0-31</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TS</name>
+              <description>GPIO interrupt status set register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TC</name>
+          <description>GPIO interrupt status clear register for GPIO0-31</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TC</name>
+              <description>GPIO interrupt status clear register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT</name>
+          <description>GPIO PRO_CPU interrupt status register for GPIO0-31</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT</name>
+              <description>GPIO PRO_CPU interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT</name>
+          <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT</name>
+              <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT</name>
+          <description>GPIO CPUSDIO interrupt status register for GPIO0-31</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT</name>
+              <description>GPIO CPUSDIO interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>PIN%s</name>
+          <description>GPIO pin configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYNC2_BYPASS</name>
+              <description>set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>set this bit to select pad driver. 1:open-drain. 0:normal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC1_BYPASS</name>
+              <description>set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TYPE</name>
+              <description>set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENABLE</name>
+              <description>set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONFIG</name>
+              <description>reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_ENA</name>
+              <description>set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_NEXT</name>
+          <description>GPIO interrupt source register for GPIO0-31</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INTERRUPT_NEXT</name>
+              <description>GPIO interrupt source register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC0_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC6_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC7_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC8_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC9_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC10_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC11_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC12_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC13_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC14_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC15_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC16_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC17_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC19_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC28_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC29_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC30_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC31_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC32_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC33_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC34_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC35_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC40_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC41_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC42_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC45_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x208</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC46_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x20C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC47_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x210</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC48_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x214</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC49_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x218</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC50_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x21C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC51_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x220</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC52_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x224</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC53_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x228</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC54_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x22C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC55_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x230</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC56_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x234</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC63_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x250</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC64_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x254</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC65_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x258</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC66_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x25C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC67_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x260</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC68_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x264</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC69_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x268</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC70_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x26C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC71_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x270</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC72_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x274</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC73_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x278</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000038</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC81_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x298</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC82_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x29C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC87_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2B0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC88_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2B4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC89_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2B8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC90_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2BC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC91_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2C0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC92_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC93_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC94_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC95_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2D0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC97_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2D8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC98_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC99_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2E0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC100_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2E4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC101_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC102_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC103_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC104_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC105_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC106_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x2FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC107_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x300</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC108_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x304</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC109_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x308</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC110_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x30C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC111_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x310</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC112_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x314</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC113_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x318</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC114_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x31C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC115_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x320</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC116_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x324</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC117_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x328</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC118_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x32C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC119_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x330</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC120_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x334</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC121_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x338</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC122_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x33C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC123_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x340</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FUNC124_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x344</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003C</resetValue>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>FUNC%s_OUT_SEL_CFG</name>
+          <description>GPIO output function select register</description>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>OUT_SEL</name>
+              <description>The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INV_SEL</name>
+              <description>set this bit to invert output signal.1:invert.0:not invert.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_SEL</name>
+              <description>set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_INV_SEL</name>
+              <description>set this bit to invert output enable signal.1:invert.0:not invert.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>GPIO clock gate register</description>
+          <addressOffset>0x62C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>set this bit to enable GPIO clock gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>GPIO version register</description>
+          <addressOffset>0x6FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201120</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMAC</name>
+      <description>HMAC (Hash-based Message Authentication Code) Accelerator</description>
+      <groupName>HMAC</groupName>
+      <baseAddress>0x6003E000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SET_START</name>
+          <description>Process control register 0.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>Start hmac operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_PURPOSE</name>
+          <description>Configure purpose.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PURPOSE_SET</name>
+              <description>Set hmac parameter purpose.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_KEY</name>
+          <description>Configure key.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_SET</name>
+              <description>Set hmac parameter key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_FINISH</name>
+          <description>Finish initial configuration.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_PARA_END</name>
+              <description>Finish hmac configuration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ONE</name>
+          <description>Process control register 1.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ONE</name>
+              <description>Call SHA to calculate one message block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ING</name>
+          <description>Process control register 2.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ING</name>
+              <description>Continue typical hmac.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_END</name>
+          <description>Process control register 3.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_END</name>
+              <description>Start hardware padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_RESULT_FINISH</name>
+          <description>Process control register 4.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_RESULT_END</name>
+              <description>After read result from upstream, then let hmac back to idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_JTAG</name>
+          <description>Invalidate register 0.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_JTAG</name>
+              <description>Clear result from hmac downstream JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_DS</name>
+          <description>Invalidate register 1.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_DS</name>
+              <description>Clear result from hmac downstream DS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_ERROR</name>
+          <description>Error register.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUREY_CHECK</name>
+              <description>Hmac configuration state. 0: key are agree with purpose. 1: error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>Busy register.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUSY_STATE</name>
+              <description>Hmac state. 1'b0: idle. 1'b1: busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>WR_MESSAGE_MEM[%s]</name>
+          <description>Message block memory.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>RD_RESULT_MEM[%s]</name>
+          <description>Result from upstream.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>SET_MESSAGE_PAD</name>
+          <description>Process control register 5.</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_PAD</name>
+              <description>Start software padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ONE_BLOCK</name>
+          <description>Process control register 6.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_ONE_BLOCK</name>
+              <description>Don't have to do padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SOFT_JTAG_CTRL</name>
+          <description>Jtag register 0.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SOFT_JTAG_CTRL</name>
+              <description>Turn on JTAG verification.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_JTAG</name>
+          <description>Jtag register 1.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_JTAG</name>
+              <description>32-bit of key to be compared.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200618</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Hmac date information/ hmac version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2C0</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x60013000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x90</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C</name>
+        <value>11</value>
+      </interrupt>
+      <interrupt>
+        <name>I2C_EXT0</name>
+        <value>29</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SCL_LOW_PERIOD</name>
+          <description>Configures the low level width of the SCL
+Clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_LOW_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTR</name>
+          <description>Transmission setting</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000208</resetValue>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>1: direct output, 0: open drain output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>1: direct output, 0: open drain output.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAMPLE_SCL_LEVEL</name>
+              <description>This register is used to select the sample mode.
+1: sample SDA data on the SCL low level.
+0: sample SDA data on the SCL high level.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FULL_ACK_LEVEL</name>
+              <description>This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>Set this bit to configure the module as an I2C Master. Clear this bit to configure the
+module as an I2C Slave.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>Set this bit to start sending the data in txfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>This bit is used to control the sending mode for data needing to be sent.
+1: send data from the least significant bit,
+0: send data from the most significant bit.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>This bit is used to control the storage mode for received data.
+1: receive data from the least significant bit,
+0: receive data from the most significant bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_EN</name>
+              <description>This is the enable bit for arbitration_lost.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FSM_RST</name>
+              <description>This register is used to reset the scl FMS.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPGATE</name>
+              <description>synchronization bit</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_TX_AUTO_START_EN</name>
+              <description>This is the enable bit for slave to send data automatically</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_RW_CHECK_EN</name>
+              <description>This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_BROADCASTING_EN</name>
+              <description>This is the enable bit to support the 7bit general call function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <description>Describe I2C work status.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C000</resetValue>
+          <fields>
+            <field>
+              <name>RESP_REC</name>
+              <description>The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW</name>
+              <description>When in slave mode, 1: master reads from slave, 0: master writes to slave.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>When the I2C controller loses control of SCL line, this register changes to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDRESSED</name>
+              <description>When configured as an I2C Slave, and the address sent by the master is
+equal to the address of the slave, then this bit will be of high level.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>This field represents the amount of data needed to be sent.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STRETCH_CAUSE</name>
+              <description>The cause of stretching SCL low in slave mode. 0:  stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>This field stores the amount of received data in RAM.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_STATE_LAST</name>
+              <description>This field indicates the states of the I2C module state machine.
+0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_STATE_LAST</name>
+              <description>This field indicates the states of the state machine used to produce SCL.
+0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TO</name>
+          <description>Setting time out control for receiving data.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TIME_OUT_VALUE</name>
+              <description>This register is used to configure the timeout for receiving a data bit in APB
+clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_EN</name>
+              <description>This is the enable bit for time out control.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_ADDR</name>
+          <description>Local slave address setting</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_ADDR</name>
+              <description>When configured as an I2C Slave, this field is used to configure the slave address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_EN</name>
+              <description>This field is used to enable the slave 10-bit addressing mode in master mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_ST</name>
+          <description>FIFO status register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RADDR</name>
+              <description>This is the offset address of the APB reading from rxfifo</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_WADDR</name>
+              <description>This is the offset address of i2c module receiving data and writing to rxfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_RADDR</name>
+              <description>This is the offset address of i2c module reading from txfifo.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WADDR</name>
+              <description>This is the offset address of APB bus writing to txfifo.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW_POINT</name>
+              <description>The received data in I2C slave mode.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_CONF</name>
+          <description>FIFO configuration register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000408B</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_EN</name>
+              <description>Set this bit to enable APB nonfifo access.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_ADDR_CFG_EN</name>
+              <description>When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RST</name>
+              <description>Set this bit to reset rx-fifo.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RST</name>
+              <description>Set this bit to reset tx-fifo.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_PRT_EN</name>
+              <description>The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Rx FIFO read data.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_RDATA</name>
+              <description>The value of rx FIFO read data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDR_UNMATCH_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <description>Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_CLR</name>
+              <description>Set this bit to clear I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_CLR</name>
+              <description>Set this bit to clear I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDR_UNMATCH_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NACK_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDR_UNMATCH_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS</name>
+          <description>Status of captured I2C communication events</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDR_UNMATCH_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_HOLD</name>
+          <description>Configures the hold time after a negative SCL edge.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time to hold the data after the negative
+edge of SCL, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_SAMPLE</name>
+          <description>Configures the sample time after a positive SCL edge.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure for how long SDA is sampled, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH_PERIOD</name>
+          <description>Configures the high level width of SCL</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_HIGH_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_WAIT_HIGH_PERIOD</name>
+              <description>This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_HOLD</name>
+          <description>Configures the delay between the SDA and SCL negative edge for a start condition</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the negative edge
+of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_RSTART_SETUP</name>
+          <description>Configures the delay between the positive
+edge of SCL and the negative edge of SDA</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive
+edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_HOLD</name>
+          <description>Configures the delay after the SCL clock
+edge for a stop condition</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the delay after the STOP condition,
+in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_SETUP</name>
+          <description>Configures the delay between the SDA and
+SCL positive edge for a stop condition</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive edge
+of SCL and the positive edge of SDA, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CFG</name>
+          <description>SCL and SDA filter configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000300</resetValue>
+          <fields>
+            <field>
+              <name>SCL_FILTER_THRES</name>
+              <description>When a pulse on the SCL input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_THRES</name>
+              <description>When a pulse on the SDA input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FILTER_EN</name>
+              <description>This is the filter enable bit for SCL.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_EN</name>
+              <description>This is the filter enable bit for SDA.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>I2C CLK configuration register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00200000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>the integral part of the fractional divisor for i2c module</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>the numerator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>the denominator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>The clock selection for i2c module:0-XTAL,1-CLK_8MHz.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_ACTIVE</name>
+              <description>The clock switch for i2c module</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>COMD%s</name>
+          <description>I2C command register %s</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND0</name>
+              <description>This is the content of command 0. It consists of three parts:
+op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND0_DONE</name>
+              <description>When command 0 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_ST_TIME_OUT</name>
+          <description>SCL status time out register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_ST_TO_I2C</name>
+              <description>The threshold value of SCL_FSM state unchanged period. It should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_MAIN_ST_TIME_OUT</name>
+          <description>SCL main status time out register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_MAIN_ST_TO_I2C</name>
+              <description>The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_SP_CONF</name>
+          <description>Power configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_RST_SLV_EN</name>
+              <description>When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_RST_SLV_NUM</name>
+              <description>Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_PD_EN</name>
+              <description>The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_PD_EN</name>
+              <description>The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STRETCH_CONF</name>
+          <description>Set SCL stretch of I2C slave</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRETCH_PROTECT_NUM</name>
+              <description>Configure the period of I2C slave stretching SCL line.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_EN</name>
+              <description>The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_CLR</name>
+              <description>Set this bit to clear the I2C slave SCL stretch function.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_BYTE_ACK_CTL_EN</name>
+              <description>The enable bit for slave to control ACK level function.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_BYTE_ACK_LVL</name>
+              <description>Set the ACK level when slave controlling ACK level function enables.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201172</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXFIFO_START_ADDR</name>
+          <description>I2C TXFIFO base address register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TXFIFO_START_ADDR</name>
+              <description>This is the I2C txfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXFIFO_START_ADDR</name>
+          <description>I2C RXFIFO base address register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_START_ADDR</name>
+              <description>This is the I2C rxfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S0</name>
+      <description>I2S (Inter-IC Sound) Controller</description>
+      <groupName>I2S</groupName>
+      <baseAddress>0x6002D000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x60</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S1</name>
+        <value>20</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INT_RAW</name>
+          <description>I2S interrupt raw register, valid in level.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>I2S interrupt status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>I2S interrupt enable register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>I2S interrupt clear register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CONF</name>
+          <description>I2S RX configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C0B600</resetValue>
+          <fields>
+            <field>
+              <name>RX_RESET</name>
+              <description>Set this bit to reset receiver</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RESET</name>
+              <description>Set this bit to reset Rx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_START</name>
+              <description>Set this bit to start receiving data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave receiver mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_STOP_MODE</name>
+              <description>0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO</name>
+              <description>Set this bit to enable receiver  in mono mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIG_ENDIAN</name>
+              <description>I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_UPDATE</name>
+              <description>Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_CONF</name>
+              <description>I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_BYPASS</name>
+              <description>Set this bit to bypass Compress/Decompress module for received data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MSB_SHIFT</name>
+              <description>Set this bit to enable receiver in Phillips standard mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LEFT_ALIGN</name>
+              <description>1: I2S RX left alignment mode. 0: I2S RX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_24_FILL_EN</name>
+              <description>1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIT_ORDER</name>
+              <description>I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_EN</name>
+              <description>1: Enable I2S TDM Rx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PDM_EN</name>
+              <description>1: Enable I2S PDM Rx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in receiver mode.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CONF</name>
+          <description>I2S TX configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C0F210</resetValue>
+          <fields>
+            <field>
+              <name>TX_RESET</name>
+              <description>Set this bit to reset transmitter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RESET</name>
+              <description>Set this bit to reset Tx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START</name>
+              <description>Set this bit to start transmitting data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave transmitter mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP_EN</name>
+              <description>Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHAN_EQUAL</name>
+              <description>1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO</name>
+              <description>Set this bit to enable transmitter in mono mode</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIG_ENDIAN</name>
+              <description>I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_UPDATE</name>
+              <description>Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_CONF</name>
+              <description>I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_BYPASS</name>
+              <description>Set this bit to bypass  Compress/Decompress module for transmitted data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MSB_SHIFT</name>
+              <description>Set this bit to enable transmitter in Phillips standard mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_NO_DLY</name>
+              <description>1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LEFT_ALIGN</name>
+              <description>1: I2S TX left alignment mode. 0: I2S TX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_24_FILL_EN</name>
+              <description>1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIT_ORDER</name>
+              <description>I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_EN</name>
+              <description>1: Enable I2S TDM Tx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_EN</name>
+              <description>1: Enable I2S PDM Tx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in transmitter mode.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHAN_MOD</name>
+              <description>I2S transmitter channel mode configuration bits.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_LOOPBACK</name>
+              <description>Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CONF1</name>
+          <description>I2S RX configure register 1</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x787BC000</resetValue>
+          <fields>
+            <field>
+              <name>RX_TDM_WS_WIDTH</name>
+              <description>The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HALF_SAMPLE_BITS</name>
+              <description>I2S Rx half sample bits -1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN_BITS</name>
+              <description>The Rx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CONF1</name>
+          <description>I2S TX configure register 1</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x787BC000</resetValue>
+          <fields>
+            <field>
+              <name>TX_TDM_WS_WIDTH</name>
+              <description>The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HALF_SAMPLE_BITS</name>
+              <description>I2S Tx half sample bits -1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN_BITS</name>
+              <description>The Tx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CLKM_CONF</name>
+          <description>I2S RX clock configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RX_CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLK_ACTIVE</name>
+              <description>I2S Rx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLK_SEL</name>
+              <description>Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCLK_SEL</name>
+              <description>0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CLKM_CONF</name>
+          <description>I2S TX clock configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>TX_CLKM_DIV_NUM</name>
+              <description>Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b &lt;= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLK_ACTIVE</name>
+              <description>I2S Tx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLK_SEL</name>
+              <description>Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CLKM_DIV_CONF</name>
+          <description>I2S RX module clock divider configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>RX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CLKM_DIV_CONF</name>
+          <description>I2S TX module clock divider configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>TX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_PCM2PDM_CONF</name>
+          <description>I2S TX PCM2PDM configuration register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x004AA004</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_HP_BYPASS</name>
+              <description>I2S TX PDM bypass hp filter or not. The option has been removed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_OSR2</name>
+              <description>I2S TX PDM OSR2 value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_PRESCALE</name>
+              <description>I2S TX PDM prescale for sigmadelta</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_HP_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_LP_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_DITHER2</name>
+              <description>I2S TX PDM sigmadelta dither2 value</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_DITHER</name>
+              <description>I2S TX PDM sigmadelta dither value</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_DAC_2OUT_EN</name>
+              <description>I2S TX PDM dac mode enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_DAC_MODE_EN</name>
+              <description>I2S TX PDM dac 2channel enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCM2PDM_CONV_EN</name>
+              <description>I2S TX PDM Converter enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_PCM2PDM_CONF1</name>
+          <description>I2S TX PCM2PDM configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03F783C0</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_FP</name>
+              <description>I2S TX PDM Fp</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_FS</name>
+              <description>I2S TX PDM Fs</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IIR_HP_MULT12_5</name>
+              <description>The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IIR_HP_MULT12_0</name>
+              <description>The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>RX_TDM_PDM_CHAN0_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN1_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN2_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN3_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN4_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN5_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN6_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN7_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>TX_TDM_CHAN0_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN1_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN2_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN3_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN4_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN5_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN6_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN7_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_SKIP_MSK_EN</name>
+              <description>When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_TIMING</name>
+          <description>I2S RX timing control register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_SD_IN_DM</name>
+              <description>The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_OUT_DM</name>
+              <description>The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IN_DM</name>
+              <description>The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_IN_DM</name>
+              <description>The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_TIMING</name>
+          <description>I2S TX timing control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_SD_OUT_DM</name>
+              <description>The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SD1_OUT_DM</name>
+              <description>The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_OUT_DM</name>
+              <description>The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IN_DM</name>
+              <description>The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_IN_DM</name>
+              <description>The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_HUNG_CONF</name>
+          <description>I2S HUNG configure register.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000810</resetValue>
+          <fields>
+            <field>
+              <name>LC_FIFO_TIMEOUT</name>
+              <description>the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_SHIFT</name>
+              <description>The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_ENA</name>
+              <description>The enable bit for FIFO timeout</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXEOF_NUM</name>
+          <description>I2S RX data number control register.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000040</resetValue>
+          <fields>
+            <field>
+              <name>RX_EOF_NUM</name>
+              <description>The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_SIGLE_DATA</name>
+          <description>I2S signal data register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_DATA</name>
+              <description>The configured constant channel data to be sent out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>I2S TX status register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TX_IDLE</name>
+              <description>1: i2s_tx is idle state. 0: i2s_tx is working.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ETM_CONF</name>
+          <description>I2S ETM configure register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010040</resetValue>
+          <fields>
+            <field>
+              <name>ETM_TX_SEND_WORD_NUM</name>
+              <description>I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_RX_RECEIVE_WORD_NUM</name>
+              <description>I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02208250</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>I2S version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>IO_MUX</name>
+      <description>Input/Output Multiplexer</description>
+      <groupName>IO_MUX</groupName>
+      <baseAddress>0x60009000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x7C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PIN_CTRL</name>
+          <description>Clock Output Configuration Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001DEF</resetValue>
+          <fields>
+            <field>
+              <name>CLK_OUT1</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT2</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT3</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>28</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>GPIO%s</name>
+          <description>IO MUX Configure Register for pad GPIO0</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_DRV</name>
+              <description>Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled. 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HYS_EN</name>
+              <description>Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: Hysteresis disabled.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HYS_SEL</name>
+              <description>Select enabling signals of the pad from software and efuse hardware. 1: Select enabling siganl from slftware. 0: Select enabling signal from efuse hardware.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEM_DIAG_EN</name>
+          <description>GPIO MATRIX Configure Register for modem diag</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEM_DIAG_EN</name>
+              <description>bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>IO MUX Version Control Register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02207270</resetValue>
+          <fields>
+            <field>
+              <name>REG_DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LEDC</name>
+      <description>LED Control PWM (Pulse Width Modulation)</description>
+      <groupName>LEDC</groupName>
+      <baseAddress>0x60019000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x154</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LEDC</name>
+        <value>23</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF0</name>
+          <description>Configuration register 0 for channel %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SEL_CH</name>
+              <description>This field is used to select one of timers for channel %s.
+
+0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_OUT_EN_CH</name>
+              <description>Set this bit to enable signal output on channel %s.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_LV_CH</name>
+              <description>This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0).</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP_CH</name>
+              <description>This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_NUM_CH</name>
+              <description>This register is used to configure the maximum times of overflow minus 1.
+
+The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_EN_CH</name>
+              <description>This bit is used to enable the ovf_cnt of channel %s.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_RESET_CH</name>
+              <description>Set this bit to reset the ovf_cnt of channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_HPOINT</name>
+          <description>High point register for channel %s</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HPOINT_CH</name>
+              <description>The output value changes to high when the selected timers has reached the value specified by this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY</name>
+          <description>Initial duty cycle for channel %s</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_CH</name>
+              <description>This register is used to change the output duty by controlling the Lpoint.
+
+The output value turns to low when the selected timers has reached the Lpoint.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF1</name>
+          <description>Configuration register 1 for channel %s</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_START_CH</name>
+              <description>Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY_R</name>
+          <description>Current duty cycle for channel %s</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_CH_R</name>
+              <description>This register stores the current duty of output signal on channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_CONF</name>
+          <description>Timer %s configuration</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000000</resetValue>
+          <fields>
+            <field>
+              <name>TIMER_DUTY_RES</name>
+              <description>This register is used to control the range of the counter in timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DIV_TIMER</name>
+              <description>This register is used to configure the divisor for the divider in timer %s.
+
+The least significant eight bits represent the fractional part.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_PAUSE</name>
+              <description>This bit is used to suspend the counter in timer %s.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_RST</name>
+              <description>This bit is used to reset timer %s. The counter will show 0 after reset.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_SEL_TIMER</name>
+              <description>This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.
+
+1'h0: SLOW_CLK 1'h1: REF_TICK</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_PARA_UP</name>
+              <description>Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_VALUE</name>
+          <description>Timer %s current counter value</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_CNT</name>
+              <description>This register stores the current counter value of timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_RAW</name>
+              <description>Triggered when the timer0 has reached its maximum counter value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_RAW</name>
+              <description>Triggered when the timer1 has reached its maximum counter value.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_RAW</name>
+              <description>Triggered when the timer2 has reached its maximum counter value.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_RAW</name>
+              <description>Triggered when the timer3 has reached its maximum counter value.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>CH%s_GAMMA_WR</name>
+          <description>Ledc ch%s gamma ram write register.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_DUTY_INC</name>
+              <description>Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s.
+
+1: Increase  0: Decrease.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_DUTY_CYCLE</name>
+              <description>Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_SCALE</name>
+              <description>Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_DUTY_NUM</name>
+              <description>Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>CH%s_GAMMA_WR_ADDR</name>
+          <description>Ledc ch%s gamma ram write address register.</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_WR_ADDR</name>
+              <description>Ledc ch%s gamma ram write address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>CH%s_GAMMA_RD_ADDR</name>
+          <description>Ledc ch%s gamma ram read address register.</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_RD_ADDR</name>
+              <description>Ledc ch%s gamma ram read address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x10</dimIncrement>
+          <name>CH%s_GAMMA_RD_DATA</name>
+          <description>Ledc ch%s gamma ram read data register.</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_RD_DATA</name>
+              <description>Ledc ch%s gamma ram read data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>6</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_GAMMA_CONF</name>
+          <description>Ledc ch%s gamma config register.</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_GAMMA_ENTRY_NUM</name>
+              <description>Ledc ch%s gamma entry num.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_PAUSE</name>
+              <description>Ledc ch%s gamma pause, write 1 to pause.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH_GAMMA_RESUME</name>
+              <description>Ledc ch%s gamma resume, write 1 to resume.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVT_TASK_EN0</name>
+          <description>Ledc event task enable bit register0.</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH0_EN</name>
+              <description>Ledc ch0 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH1_EN</name>
+              <description>Ledc ch1 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH2_EN</name>
+              <description>Ledc ch2 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH3_EN</name>
+              <description>Ledc ch3 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH4_EN</name>
+              <description>Ledc ch4 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_DUTY_CHNG_END_CH5_EN</name>
+              <description>Ledc ch5 duty change end event enable register, write 1 to enable this event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH0_EN</name>
+              <description>Ledc ch0 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH1_EN</name>
+              <description>Ledc ch1 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH2_EN</name>
+              <description>Ledc ch2 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH3_EN</name>
+              <description>Ledc ch3 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH4_EN</name>
+              <description>Ledc ch4 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_OVF_CNT_PLS_CH5_EN</name>
+              <description>Ledc ch5 overflow count pulse event enable register, write 1 to enable this event.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME_OVF_TIMER0_EN</name>
+              <description>Ledc timer0 overflow event enable register, write 1 to enable this event.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME_OVF_TIMER1_EN</name>
+              <description>Ledc timer1 overflow event enable register, write 1 to enable this event.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME_OVF_TIMER2_EN</name>
+              <description>Ledc timer2 overflow event enable register, write 1 to enable this event.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME_OVF_TIMER3_EN</name>
+              <description>Ledc timer3 overflow event enable register, write 1 to enable this event.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME0_CMP_EN</name>
+              <description>Ledc timer0 compare event enable register, write 1 to enable this event.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME1_CMP_EN</name>
+              <description>Ledc timer1 compare event enable register, write 1 to enable this event.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME2_CMP_EN</name>
+              <description>Ledc timer2 compare event enable register, write 1 to enable this event.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVT_TIME3_CMP_EN</name>
+              <description>Ledc timer3 compare event enable register, write 1 to enable this event.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH0_EN</name>
+              <description>Ledc ch0 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH1_EN</name>
+              <description>Ledc ch1 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH2_EN</name>
+              <description>Ledc ch2 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH3_EN</name>
+              <description>Ledc ch3 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH4_EN</name>
+              <description>Ledc ch4 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_DUTY_SCALE_UPDATE_CH5_EN</name>
+              <description>Ledc ch5 duty scale update task enable register, write 1 to enable this task.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVT_TASK_EN1</name>
+          <description>Ledc event task enable bit register1.</description>
+          <addressOffset>0x1A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TASK_TIMER0_RES_UPDATE_EN</name>
+              <description>Ledc timer0 res update task enable register, write 1 to enable this task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_RES_UPDATE_EN</name>
+              <description>Ledc timer1 res update task enable register, write 1 to enable this task.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_RES_UPDATE_EN</name>
+              <description>Ledc timer2 res update task enable register, write 1 to enable this task.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER3_RES_UPDATE_EN</name>
+              <description>Ledc timer3 res update task enable register, write 1 to enable this task.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER0_CAP_EN</name>
+              <description>Ledc timer0 capture task enable register, write 1 to enable this task.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_CAP_EN</name>
+              <description>Ledc timer1 capture task enable register, write 1 to enable this task.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_CAP_EN</name>
+              <description>Ledc timer2 capture task enable register, write 1 to enable this task.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER3_CAP_EN</name>
+              <description>Ledc timer3 capture task enable register, write 1 to enable this task.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH0_EN</name>
+              <description>Ledc ch0 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH1_EN</name>
+              <description>Ledc ch1 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH2_EN</name>
+              <description>Ledc ch2 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH3_EN</name>
+              <description>Ledc ch3 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH4_EN</name>
+              <description>Ledc ch4 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_SIG_OUT_DIS_CH5_EN</name>
+              <description>Ledc ch5 signal out disable task enable register, write 1 to enable this task.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH0_EN</name>
+              <description>Ledc ch0 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH1_EN</name>
+              <description>Ledc ch1 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH2_EN</name>
+              <description>Ledc ch2 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH3_EN</name>
+              <description>Ledc ch3 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH4_EN</name>
+              <description>Ledc ch4 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_OVF_CNT_RST_CH5_EN</name>
+              <description>Ledc ch5 overflow count reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER0_RST_EN</name>
+              <description>Ledc timer0 reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_RST_EN</name>
+              <description>Ledc timer1 reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_RST_EN</name>
+              <description>Ledc timer2 reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER3_RST_EN</name>
+              <description>Ledc timer3 reset task enable register, write 1 to enable this task.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER0_PAUSE_RESUME_EN</name>
+              <description>Ledc timer0 pause resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER1_PAUSE_RESUME_EN</name>
+              <description>Ledc timer1 pause resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER2_PAUSE_RESUME_EN</name>
+              <description>Ledc timer2 pause resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_TIMER3_PAUSE_RESUME_EN</name>
+              <description>Ledc timer3 pause resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EVT_TASK_EN2</name>
+          <description>Ledc event task enable bit register2.</description>
+          <addressOffset>0x1A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH0_EN</name>
+              <description>Ledc ch0 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH1_EN</name>
+              <description>Ledc ch1 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH2_EN</name>
+              <description>Ledc ch2 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH3_EN</name>
+              <description>Ledc ch3 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH4_EN</name>
+              <description>Ledc ch4 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESTART_CH5_EN</name>
+              <description>Ledc ch5 gamma restart task enable register, write 1 to enable this task.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH0_EN</name>
+              <description>Ledc ch0 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH1_EN</name>
+              <description>Ledc ch1 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH2_EN</name>
+              <description>Ledc ch2 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH3_EN</name>
+              <description>Ledc ch3 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH4_EN</name>
+              <description>Ledc ch4 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_PAUSE_CH5_EN</name>
+              <description>Ledc ch5 gamma pause task enable register, write 1 to enable this task.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH0_EN</name>
+              <description>Ledc ch0 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH1_EN</name>
+              <description>Ledc ch1 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH2_EN</name>
+              <description>Ledc ch2 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH3_EN</name>
+              <description>Ledc ch3 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH4_EN</name>
+              <description>Ledc ch4 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TASK_GAMMA_RESUME_CH5_EN</name>
+              <description>Ledc ch5 gamma resume task enable register, write 1 to enable this task.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TIMER%s_CMP</name>
+          <description>Ledc timer%s compare value register.</description>
+          <addressOffset>0x1B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_CMP</name>
+              <description>This register stores ledc timer%s compare value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TIMER%s_CNT_CAP</name>
+          <description>Ledc timer%s count value capture register.</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_CNT_CAP</name>
+              <description>This register stores ledc timer%s count value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>Global ledc configuration register</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_CLK_SEL</name>
+              <description>This bit is used to select clock source for the 4 timers .
+
+2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH0</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH1</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH2</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH3</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH4</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GAMMA_RAM_CLK_EN_CH5</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02111150</resetValue>
+          <fields>
+            <field>
+              <name>LEDC_DATE</name>
+              <description>This is the version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PCNT</name>
+      <description>Pulse Counter</description>
+      <groupName>PCNT</groupName>
+      <baseAddress>0x60017000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF0</name>
+          <description>Configuration register 0 for unit %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U</name>
+              <description>This sets the maximum threshold, in APB_CLK cycles, for the filter.
+
+Any pulses with width less than this will be ignored when the filter is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U</name>
+              <description>This is the enable bit for unit %s's input filter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U</name>
+              <description>This is the enable bit for unit %s's zero comparator.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U</name>
+              <description>This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U</name>
+              <description>This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U</name>
+              <description>This is the enable bit for unit %s's thres0 comparator.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U</name>
+              <description>This is the enable bit for unit %s's thres1 comparator.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 0 detects a negative edge.
+
+1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 0 detects a positive edge.
+
+1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.
+
+0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.
+
+0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 1 detects a negative edge.
+
+1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 1 detects a positive edge.
+
+1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.
+
+0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.
+
+0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF1</name>
+          <description>Configuration register 1 for unit %s</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U</name>
+              <description>This register is used to configure the thres0 value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U</name>
+              <description>This register is used to configure the thres1 value for unit %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF2</name>
+          <description>Configuration register 2 for unit %s</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U</name>
+              <description>This register is used to configure the thr_h_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U</name>
+              <description>This register is used to configure the thr_l_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>U%s_CNT</name>
+          <description>Counter value for unit %s</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PULSE_CNT_U</name>
+              <description>This register stores the current pulse count value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt raw status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Interrupt status register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>U%s_STATUS</name>
+          <description>PNCT UNIT%s status register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_ZERO_MODE_U</name>
+              <description>The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_THRES1_LAT_U</name>
+              <description>The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_THRES0_LAT_U</name>
+              <description>The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_L_LIM_LAT_U</name>
+              <description>The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_H_LIM_LAT_U</name>
+              <description>The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_ZERO_LAT_U</name>
+              <description>The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>Control register for all counters</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PULSE_CNT_RST_U0</name>
+              <description>Set this bit to clear unit 0's counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U0</name>
+              <description>Set this bit to freeze unit 0's counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U1</name>
+              <description>Set this bit to clear unit 1's counter.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U1</name>
+              <description>Set this bit to freeze unit 1's counter.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U2</name>
+              <description>Set this bit to clear unit 2's counter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U2</name>
+              <description>Set this bit to freeze unit 2's counter.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U3</name>
+              <description>Set this bit to clear unit 3's counter.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U3</name>
+              <description>Set this bit to freeze unit 3's counter.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>PCNT version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x18072600</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the PCNT version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RMT</name>
+      <description>Remote Control Peripheral</description>
+      <groupName>RMT</groupName>
+      <baseAddress>0x60016000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x78</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RMT</name>
+        <value>28</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TX_CH%sDATA</name>
+          <description>The read and write  data register for CHANNEL%s by apb fifo access.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHDATA</name>
+              <description>Read and write data for channel %s via APB FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TX_CH%sCONF0</name>
+          <description>Channel %s configure register 0</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00710200</resetValue>
+          <fields>
+            <field>
+              <name>TX_START_CH0</name>
+              <description>Set this bit to start sending data on CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_RD_RST_CH0</name>
+              <description>Set this bit to reset read ram address for CHANNEL%s by accessing transmitter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST_CH0</name>
+              <description>Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_CONTI_MODE_CH0</name>
+              <description>Set this bit to restart transmission  from the first data to the last data in CHANNEL%s.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TX_WRAP_EN_CH0</name>
+              <description>This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_LV_CH0</name>
+              <description>This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_EN_CH0</name>
+              <description>This is the output enable-control bit for CHANNEL%s in IDLE state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP_CH0</name>
+              <description>Set this bit to stop the transmitter of CHANNEL%s sending data out.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIV_CNT_CH0</name>
+              <description>This register is used to configure the divider for clock of CHANNEL%s.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE_CH0</name>
+              <description>This register is used to configure the maximum size of memory allocated to CHANNEL%s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EFF_EN_CH0</name>
+              <description>1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN_CH0</name>
+              <description>This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV_CH0</name>
+              <description>This bit is used to configure the position of carrier wave for CHANNEL%s.
+
+1'h0: add carrier wave on low level.
+
+1'h1: add carrier wave on high level.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFIFO_RST_CH0</name>
+              <description>Reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPDATE_CH0</name>
+              <description>synchronization bit for CHANNEL%s</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>RX_CH%sCONF0</name>
+          <description>Channel %s configure register 0</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x30FFFF02</resetValue>
+          <fields>
+            <field>
+              <name>DIV_CNT_CH2</name>
+              <description>This register is used to configure the divider for clock of CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_THRES_CH2</name>
+              <description>When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE_CH2</name>
+              <description>This register is used to configure the maximum size of memory allocated to CHANNEL%s.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN_CH2</name>
+              <description>This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV_CH2</name>
+              <description>This bit is used to configure the position of carrier wave for CHANNEL%s.
+
+1'h0: add carrier wave on low level.
+
+1'h1: add carrier wave on high level.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>RX_CH%sCONF1</name>
+          <description>Channel %s configure register 1</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001E8</resetValue>
+          <fields>
+            <field>
+              <name>RX_EN_CH2</name>
+              <description>Set this bit to enable receiver to receive data on CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_WR_RST_CH2</name>
+              <description>Set this bit to reset write ram address for CHANNEL%s by accessing receiver.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST_CH2</name>
+              <description>Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_CH2</name>
+              <description>This register marks the ownership of CHANNEL%s's ram block.
+
+1'h1: Receiver is using the ram.
+
+1'h0: APB bus is using the ram.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_EN_CH2</name>
+              <description>This is the receive filter's enable bit for CHANNEL%s.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_THRES_CH2</name>
+              <description>Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode).</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_RX_WRAP_EN_CH2</name>
+              <description>This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFIFO_RST_CH2</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPDATE_CH2</name>
+              <description>synchronization bit for CHANNEL%s</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TX_CH%sSTATUS</name>
+          <description>Channel %s status register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_RADDR_EX_CH0</name>
+              <description>This register records the memory address offset when transmitter of CHANNEL%s is using the RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE_CH0</name>
+              <description>This register records the FSM status of CHANNEL%s.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WADDR_CH0</name>
+              <description>This register records the memory address offset when writes RAM over APB bus.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR_CH0</name>
+              <description>This status bit will be set if the offset address out of memory size when reading via APB bus.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY_CH0</name>
+              <description>This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR_CH0</name>
+              <description>This status bit will be set if the offset address out of memory size when writes via APB bus.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR_CH0</name>
+              <description>This register records the memory address offset when reading RAM over APB bus.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RX_CH%sSTATUS</name>
+          <description>Channel %s status register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_WADDR_EX_CH2</name>
+              <description>This register records the memory address offset when receiver of CHANNEL%s is using the RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR_CH2</name>
+              <description>This register records the memory address offset when reads RAM over APB bus.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE_CH2</name>
+              <description>This register records the FSM status of CHANNEL%s.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR_CH2</name>
+              <description>This status bit will be set when the ownership of memory block is wrong.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL_CH2</name>
+              <description>This status bit will be set if the receiver receives more data than the memory size.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR_CH2</name>
+              <description>This status bit will be set if the offset address out of memory size when reads via APB bus.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_TX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL0. Triggered when transmission done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL1. Triggered when transmission done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL2. Triggered when reception done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL3. Triggered when reception done.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH0_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL4. Triggered when error occurs.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH1_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL5. Triggered when error occurs.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH2_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL6. Triggered when error occurs.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH3_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL7. Triggered when error occurs.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than configured value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_LOOP_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_LOOP_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_TX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH0_TX_END_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH1_TX_END_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH2_RX_END_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH3_RX_END_INT.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH0_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH4_ERR_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH1_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH5_ERR_INT.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH2_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH6_ERR_INT.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH3_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH7_ERR_INT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH0_TX_THR_EVENT_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH1_TX_THR_EVENT_INT.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH2_RX_THR_EVENT_INT.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH3_RX_THR_EVENT_INT.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_LOOP_INT_ST</name>
+              <description>The masked interrupt status bit for CH0_TX_LOOP_INT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_LOOP_INT_ST</name>
+              <description>The masked interrupt status bit for CH1_TX_LOOP_INT.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_TX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH0_TX_END_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_TX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH1_TX_END_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2_RX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH2_RX_END_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3_RX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH3_RX_END_INT.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH4_ERR_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH5_ERR_INT.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH6_ERR_INT.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH7_ERR_INT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_TX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH0_TX_THR_EVENT_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_TX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH1_TX_THR_EVENT_INT.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH2_RX_THR_EVENT_INT.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH3_RX_THR_EVENT_INT.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_TX_LOOP_INT_ENA</name>
+              <description>The interrupt enable bit for CH0_TX_LOOP_INT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_TX_LOOP_INT_ENA</name>
+              <description>The interrupt enable bit for CH1_TX_LOOP_INT.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0_TX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH0_TX_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH1_TX_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH2_RX_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH3_RX_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_CH0_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH4_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_CH1_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_CH2_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH6_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_CH3_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH7_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH2_RX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH3_RX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH0_TX_LOOP_INT_CLR</name>
+              <description>Set this bit to clear theCH0_TX_LOOP_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH1_TX_LOOP_INT_CLR</name>
+              <description>Set this bit to clear theCH1_TX_LOOP_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%sCARRIER_DUTY</name>
+          <description>Channel %s duty cycle configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW_CH0</name>
+              <description>This register is used to configure carrier wave 's low level clock period for CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH_CH0</name>
+              <description>This register is used to configure carrier wave 's high level clock period for CHANNEL%s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_RX_CARRIER_RM</name>
+          <description>Channel %s carrier remove register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARRIER_LOW_THRES_CH2</name>
+              <description>The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH_THRES_CH2</name>
+              <description>The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_TX_LIM</name>
+          <description>Channel %s Tx event configuration register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>TX_LIM_CH0</name>
+              <description>This register is used to configure the maximum entries that CHANNEL%s can send out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_NUM_CH0</name>
+              <description>This register is used to configure the maximum loop count when tx_conti_mode is valid.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_CNT_EN_CH0</name>
+              <description>This register is the enabled bit for loop count.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOP_COUNT_RESET_CH0</name>
+              <description>This register is used to reset the loop count when tx_conti_mode is valid.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LOOP_STOP_EN_CH0</name>
+              <description>This bit is used to enable the loop send stop function after the loop counter counts to  loop number for CHANNEL%s.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_RX_LIM</name>
+          <description>Channel %s Rx event configuration register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>RMT_RX_LIM_CH2</name>
+              <description>This register is used to configure the maximum entries that CHANNEL%s can receive.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYS_CONF</name>
+          <description>RMT apb configuration register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x05000010</resetValue>
+          <fields>
+            <field>
+              <name>APB_FIFO_MASK</name>
+              <description>1'h1: access memory directly.   1'h0: access memory by FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>Set this bit to enable the clock for RMT memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_MEM_FORCE_PD</name>
+              <description>Set this bit to power down RMT memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_MEM_FORCE_PU</name>
+              <description>1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_DIV_NUM</name>
+              <description>the integral part of the fractional divisor</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_DIV_A</name>
+              <description>the numerator of the fractional part of the fractional divisor</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_DIV_B</name>
+              <description>the denominator of the fractional part of the fractional divisor</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_SEL</name>
+              <description>choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_SCLK_ACTIVE</name>
+              <description>rmt_sclk switch</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_SIM</name>
+          <description>RMT TX synchronous register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0</name>
+              <description>Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1</name>
+              <description>Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>This register is used to enable multiple of channels to start sending data synchronously.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REF_CNT_RST</name>
+          <description>RMT clock divider reset register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_REF_CNT_RST_CH0</name>
+              <description>This register is used to reset the clock divider of CHANNEL0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_REF_CNT_RST_CH1</name>
+              <description>This register is used to reset the clock divider of CHANNEL1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_REF_CNT_RST_CH2</name>
+              <description>This register is used to reset the clock divider of CHANNEL2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_REF_CNT_RST_CH3</name>
+              <description>This register is used to reset the clock divider of CHANNEL3.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>RMT version register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02108213</resetValue>
+          <fields>
+            <field>
+              <name>RMT_DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RNG</name>
+      <description>Hardware random number generator</description>
+      <groupName>RNG</groupName>
+      <baseAddress>0x600260B0</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>DATA</name>
+          <description>Random number data</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RSA</name>
+      <description>RSA (Rivest Shamir Adleman) Accelerator</description>
+      <groupName>RSA</groupName>
+      <baseAddress>0x6003C000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x74</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RSA</name>
+        <value>47</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>Represents M</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Z_MEM[%s]</name>
+          <description>Represents Z</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Y_MEM[%s]</name>
+          <description>Represents Y</description>
+          <addressOffset>0x400</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>X_MEM[%s]</name>
+          <description>Represents X</description>
+          <addressOffset>0x600</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>M_PRIME</name>
+          <description>Represents M’</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M_PRIME</name>
+              <description>Represents M’</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>Configures RSA length</description>
+          <addressOffset>0x804</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Configures the RSA length.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_CLEAN</name>
+          <description>RSA clean register</description>
+          <addressOffset>0x808</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_CLEAN</name>
+              <description>Represents whether or not the RSA memory completes initialization.
+
+0: Not complete
+
+1: Completed
+
+</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_START_MODEXP</name>
+          <description>Starts modular exponentiation</description>
+          <addressOffset>0x80C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START_MODEXP</name>
+              <description>Configure whether or not to start the modular exponentiation.
+
+0: No effect
+
+1: Start
+
+</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_START_MODMULT</name>
+          <description>Starts modular multiplication</description>
+          <addressOffset>0x810</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START_MODMULT</name>
+              <description>Configure whether or not to start the modular multiplication.
+
+0: No effect
+
+1: Start
+
+</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_START_MULT</name>
+          <description>Starts multiplication</description>
+          <addressOffset>0x814</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START_MULT</name>
+              <description>Configure whether or not to start the multiplication.
+
+0: No effect
+
+1: Start
+
+</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_IDLE</name>
+          <description>Represents the RSA status</description>
+          <addressOffset>0x818</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_IDLE</name>
+              <description>Represents the RSA status.
+
+0: Busy
+
+1: Idle
+
+</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Clears RSA interrupt</description>
+          <addressOffset>0x81C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>Write 1 to clear the RSA interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONSTANT_TIME</name>
+          <description>Configures the constant_time option</description>
+          <addressOffset>0x820</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CONSTANT_TIME</name>
+              <description>Configures the constant_time option.
+
+0: Acceleration
+
+1: No acceleration (default)
+
+</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_ENABLE</name>
+          <description>Configures the search option</description>
+          <addressOffset>0x824</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_ENABLE</name>
+              <description>Configure the search option.
+
+0: No acceleration (default)
+
+1: Acceleration
+
+This option should be used together with RSA_SEARCH_POS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_POS</name>
+          <description>Configures the search position</description>
+          <addressOffset>0x828</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_POS</name>
+              <description>Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Enables the RSA interrupt</description>
+          <addressOffset>0x82C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_ENA</name>
+              <description>Write 1 to enable the RSA interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x830</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200618</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SHA</name>
+      <description>SHA (Secure Hash Algorithm) Accelerator</description>
+      <groupName>SHA</groupName>
+      <baseAddress>0x6003B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SHA</name>
+        <value>49</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Initial configuration register.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Sha mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_STRING</name>
+          <description>SHA 512/t configuration register 0.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_STRING</name>
+              <description>Sha t_string (used if and only if mode == SHA_512/t).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_LENGTH</name>
+          <description>SHA 512/t configuration register 1.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LENGTH</name>
+              <description>Sha t_length (used if and only if mode == SHA_512/t).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_BLOCK_NUM</name>
+          <description>DMA configuration register 0.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_BLOCK_NUM</name>
+              <description>Dma-sha block number.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>START</name>
+          <description>Typical SHA configuration register 0.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE</name>
+          <description>Typical SHA configuration register 1.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSY</name>
+          <description>Busy register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Sha busy state. 1'b0: idle. 1'b1: busy.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_START</name>
+          <description>DMA configuration register 1.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_START</name>
+              <description>Start dma-sha.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONTINUE</name>
+          <description>DMA configuration register 2.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CONTINUE</name>
+              <description>Continue dma-sha.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR_IRQ</name>
+          <description>Interrupt clear register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>Clear sha interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IRQ_ENA</name>
+          <description>Interrupt enable register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT_ENA</name>
+              <description>Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20201229</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Sha date information/ sha version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>H_MEM[%s]</name>
+          <description>Sha H memory which contains intermediate hash or finial hash.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>Sha M memory which contains message.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI0</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI0</groupName>
+      <baseAddress>0x60003000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x138</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI_MEM_REJECT_CACHE</name>
+        <value>40</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SPI_MEM_CMD</name>
+          <description>SPI0 FSM status register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_MST_ST</name>
+              <description>The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST</name>
+              <description>The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR</name>
+              <description>SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL</name>
+          <description>SPI0 control register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x802C200C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_WDUMMY_DQS_ALWAYS_OUT</name>
+              <description>In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WDUMMY_ALWAYS_OUT</name>
+              <description>In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDUMMY_RIN</name>
+              <description>In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDUMMY_WOUT</name>
+              <description>In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_OCT</name>
+              <description>Apply 8 signals during write-data phase 1:enable 0: disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_OCT</name>
+              <description>Apply 8 signals during read-data phase 1:enable 0: disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_OCT</name>
+              <description>Apply 8 signals during address phase 1:enable 0: disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCMD_OCT</name>
+              <description>Apply 8 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FASTRD_MODE</name>
+              <description>This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_DIO</name>
+              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_QIO</name>
+              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DQS_IE_ALWAYS_ON</name>
+              <description>When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DATA_IE_ALWAYS_ON</name>
+              <description>When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL1</name>
+          <description>SPI0 control1 register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x28E00000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_AR_SIZE0_1_SUPPORT_EN</name>
+              <description>1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_AW_SIZE0_1_SUPPORT_EN</name>
+              <description>1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_AXI_RDATA_BACK_FAST</name>
+              <description>1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RRESP_ECC_ERR_EN</name>
+              <description>1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AR_SPLICE_EN</name>
+              <description>Set this bit to enable AXI Read Splice-transfer.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AW_SPLICE_EN</name>
+              <description>Set this bit to enable AXI Write Splice-transfer.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RAM0_EN</name>
+              <description>When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be accessed at the same time.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DUAL_RAM_EN</name>
+              <description>Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FAST_WRITE_EN</name>
+              <description>Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in  tx_bus_fifo_l2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RXFIFO_RST</name>
+              <description>The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI.  Set this bit to reset these FIFO.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_TXFIFO_RST</name>
+              <description>The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL2</name>
+          <description>SPI0 control2 register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002C21</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CS_SETUP_TIME</name>
+              <description>(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_HOLD_TIME</name>
+              <description>SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_CS_HOLD_TIME</name>
+              <description>SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_SKIP_PAGE_CORNER</name>
+              <description>1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_16TO18_BYTE_EN</name>
+              <description>Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SPLIT_TRANS_EN</name>
+              <description>Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_HOLD_DELAY</name>
+              <description>These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SYNC_RESET</name>
+              <description>The spi0_mst_st and spi0_slv_st will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CLOCK</name>
+          <description>SPI clock division control register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLK_EQU_SYSCLK</name>
+              <description>1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER</name>
+          <description>SPI0 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CK_OUT_EDGE</name>
+              <description>The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER1</name>
+          <description>SPI0 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000047</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DBYTELEN</name>
+              <description>SPI0 USR_CMD read or write data byte length -1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER2</name>
+          <description>SPI0 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_COMMAND_VALUE</name>
+              <description>The value of  command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_RD_STATUS</name>
+          <description>SPI0 read control register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MISC</name>
+          <description>SPI0 misc register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_FSUB_PIN</name>
+              <description>For SPI0,  flash is connected to SUBPINs.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SSUB_PIN</name>
+              <description>For SPI0,  sram is connected to SUBPINs.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CK_IDLE_EDGE</name>
+              <description>1: SPI_CLK line is high when idle     0: spi clk line is low when idle</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_KEEP_ACTIVE</name>
+              <description>SPI_CS line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CACHE_FCTRL</name>
+          <description>SPI0 bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC0000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_AXI_REQ_EN</name>
+              <description>For SPI0, AXI master access enable, 1: enable, 0:disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_USR_ADDR_4BYTE</name>
+              <description>For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_FLASH_USR_CMD</name>
+              <description>For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_DUAL</name>
+              <description>For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_DUAL</name>
+              <description>For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_DUAL</name>
+              <description>For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_QUAD</name>
+              <description>For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_QUAD</name>
+              <description>For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_QUAD</name>
+              <description>For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SAME_AW_AR_ADDR_CHK_EN</name>
+              <description>Set this bit to check AXI read/write the same address region.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_CLOSE_AXI_INF_EN</name>
+              <description>Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CACHE_SCTRL</name>
+          <description>SPI0 external RAM control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0055C070</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CACHE_USR_SADDR_4BYTE</name>
+              <description>For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_SRAM_DIO</name>
+              <description>For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_SRAM_QIO</name>
+              <description>For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_WR_SRAM_DUMMY</name>
+              <description>For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_RD_SRAM_DUMMY</name>
+              <description>For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_RCMD</name>
+              <description>For SPI0, In the external RAM mode cache read external RAM for user define command.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SRAM_RDUMMY_CYCLELEN</name>
+              <description>For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SRAM_ADDR_BITLEN</name>
+              <description>For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_WCMD</name>
+              <description>For SPI0, In the external RAM mode cache write sram for user define command</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SRAM_OCT</name>
+              <description>reserved</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SRAM_WDUMMY_CYCLELEN</name>
+              <description>For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SRAM_CMD</name>
+          <description>SPI0 external RAM mode control register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xC0400000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_SCLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SWB_MODE</name>
+              <description>Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDIN_DUAL</name>
+              <description>For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDOUT_DUAL</name>
+              <description>For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SADDR_DUAL</name>
+              <description>For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDIN_QUAD</name>
+              <description>For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDOUT_QUAD</name>
+              <description>For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SADDR_QUAD</name>
+              <description>For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCMD_QUAD</name>
+              <description>For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDIN_OCT</name>
+              <description>For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDOUT_OCT</name>
+              <description>For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SADDR_OCT</name>
+              <description>For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCMD_OCT</name>
+              <description>For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDUMMY_RIN</name>
+              <description>In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SDUMMY_WOUT</name>
+              <description>In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT</name>
+              <description>In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_WDUMMY_ALWAYS_OUT</name>
+              <description>In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DQS_IE_ALWAYS_ON</name>
+              <description>When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DATA_IE_ALWAYS_ON</name>
+              <description>When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SRAM_DRD_CMD</name>
+          <description>SPI0 external RAM DDR read command control register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE</name>
+              <description>For SPI0,When cache mode is enable it is the read command value of command phase for sram.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN</name>
+              <description>For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SRAM_DWR_CMD</name>
+          <description>SPI0 external RAM DDR write command control register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE</name>
+              <description>For SPI0,When cache mode is enable it is the write command value of command phase for sram.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN</name>
+              <description>For SPI0,When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SRAM_CLK</name>
+          <description>SPI0 external RAM clock control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_SCLKCNT_L</name>
+              <description>For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCLKCNT_H</name>
+              <description>For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCLKCNT_N</name>
+              <description>For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SCLK_EQU_SYSCLK</name>
+              <description>For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_FSM</name>
+          <description>SPI0 FSM status register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_LOCK_DELAY_TIME</name>
+              <description>The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_ENA</name>
+          <description>SPI0 interrupt enable register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_REJECT_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_RADDR_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WADDR_ERR_INT__ENA</name>
+              <description>The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_CLR</name>
+          <description>SPI0 interrupt clear register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_REJECT_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_RADDR_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WADDR_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_RAW</name>
+          <description>SPI0 interrupt raw register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_REJECT_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_RADDR_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WADDR_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_ST</name>
+          <description>SPI0 interrupt status register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_INT_ST</name>
+              <description>The status bit for SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_REJECT_INT_ST</name>
+              <description>The status bit for SPI_MEM_PMS_REJECT_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_RADDR_ERR_INT_ST</name>
+              <description>The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WR_FLASH_ERR_INT_ST</name>
+              <description>The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AXI_WADDR_ERR_INT_ST</name>
+              <description>The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DDR</name>
+          <description>SPI0 flash DDR mode control register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003020</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_DDR_EN</name>
+              <description>1: in DDR mode,  0 in SDR mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_VAR_DUMMY</name>
+              <description>Set the bit to enable variable dummy cycle in spi DDR mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_RDAT_SWP</name>
+              <description>Set the bit to reorder rx data of the word in spi DDR mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_WDAT_SWP</name>
+              <description>Set the bit to reorder tx data of the word in spi DDR mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_CMD_DIS</name>
+              <description>the bit is used to disable dual edge in command phase when DDR mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OUTMINBYTELEN</name>
+              <description>It is the minimum output data length in the panda device.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_TX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_RX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_USR_DDR_DQS_THD</name>
+              <description>The delay number of data strobe which from memory based on SPI clock.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_DQS_LOOP</name>
+              <description>1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_EN</name>
+              <description>Set this bit to enable the differential SPI_CLK#.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DQS_CA_IN</name>
+              <description>Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_DUMMY_2X</name>
+              <description>Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_INV</name>
+              <description>Set this bit to invert SPI_DIFF when accesses to flash. .</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OCTA_RAM_ADDR</name>
+              <description>Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_CA</name>
+              <description>Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DDR</name>
+          <description>SPI0 external RAM DDR mode control register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003020</resetValue>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>1: in DDR mode,  0 in SDR mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_VAR_DUMMY</name>
+              <description>Set the bit to enable variable dummy cycle in spi DDR mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RDAT_SWP</name>
+              <description>Set the bit to reorder rx data of the word in spi DDR mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDAT_SWP</name>
+              <description>Set the bit to reorder tx data of the word in spi DDR mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMD_DIS</name>
+              <description>the bit is used to disable dual edge in command phase when DDR mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_OUTMINBYTELEN</name>
+              <description>It is the minimum output data length in the DDR psram.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_TX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_RX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_USR_DDR_DQS_THD</name>
+              <description>The delay number of data strobe which from memory based on SPI clock.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DQS_LOOP</name>
+              <description>1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CLK_DIFF_EN</name>
+              <description>Set this bit to enable the differential SPI_CLK#.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DQS_CA_IN</name>
+              <description>Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_HYPERBUS_DUMMY_2X</name>
+              <description>Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CLK_DIFF_INV</name>
+              <description>Set this bit to invert SPI_DIFF when accesses to external RAM. .</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_OCTA_RAM_ADDR</name>
+              <description>Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_HYPERBUS_CA</name>
+              <description>Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_FMEM_PMS%s_ATTR</name>
+          <description>MSPI flash ACE section %s attribute register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_PMS_RD_ATTR</name>
+              <description>1: SPI1 flash ACE section %s read accessible. 0: Not allowed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_PMS_WR_ATTR</name>
+              <description>1: SPI1 flash ACE section %s write accessible. 0: Not allowed.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_PMS_ECC</name>
+              <description>SPI1 flash ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_FMEM_PMS%s_ADDR</name>
+          <description>SPI1 flash ACE section %s start address register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>SPI1 flash ACE section %s start address value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_FMEM_PMS%s_SIZE</name>
+          <description>SPI1 flash ACE section %s start address register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_PMS_SIZE</name>
+              <description>SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_SMEM_PMS%s_ATTR</name>
+          <description>SPI1 flash ACE section %s start address register</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_PMS_RD_ATTR</name>
+              <description>1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_PMS_WR_ATTR</name>
+              <description>1: SPI1 external RAM ACE section %s write accessible. 0: Not allowed.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_PMS_ECC</name>
+              <description>SPI1 external RAM ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_SMEM_PMS%s_ADDR</name>
+          <description>SPI1 external RAM ACE section %s start address register</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>SPI1 external RAM ACE section %s start address value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SPI_SMEM_PMS%s_SIZE</name>
+          <description>SPI1 external RAM ACE section %s start address register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_PMS_SIZE</name>
+              <description>SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_PMS_REJECT</name>
+          <description>SPI1 access reject register</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_ADDR</name>
+              <description>This bits show the first SPI1 access error address. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PM_EN</name>
+              <description>Set this bit to enable SPI0/1 transfer permission control function.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_LD</name>
+              <description>1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_ST</name>
+              <description>1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_MULTI_HIT</name>
+              <description>1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PMS_IVD</name>
+              <description>1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_ECC_CTRL</name>
+          <description>MSPI ECC control register</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01005000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_ECC_ERR_INT_NUM</name>
+              <description>Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_ECC_ERR_INT_EN</name>
+              <description>Set this bit to calculate the error times of MSPI ECC read when accesses to flash.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_PAGE_SIZE</name>
+              <description>Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_ECC_ADDR_EN</name>
+              <description>Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_ECC_ADDR_EN</name>
+              <description>Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN</name>
+              <description>1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_BITS</name>
+              <description>Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_ECC_ERR_ADDR</name>
+          <description>MSPI ECC error address register</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_ECC_ERR_ADDR</name>
+              <description>This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ECC_ERR_CNT</name>
+              <description>This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_AXI_ERR_ADDR</name>
+          <description>SPI0 AXI request error address.</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFC000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_AXI_ERR_ADDR</name>
+              <description>This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_ALL_FIFO_EMPTY</name>
+              <description>The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_RDATA_AFIFO_REMPTY</name>
+              <description>1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_RADDR_AFIFO_REMPTY</name>
+              <description>1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_WDATA_AFIFO_REMPTY</name>
+              <description>1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_WBLEN_AFIFO_REMPTY</name>
+              <description>1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_ALL_AXI_TRANS_AFIFO_EMPTY</name>
+              <description>This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_ECC_CTRL</name>
+          <description>MSPI ECC control register</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00080000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_ECC_ERR_INT_EN</name>
+              <description>Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_PAGE_SIZE</name>
+              <description>Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_ADDR_EN</name>
+              <description>Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_TIMING_CALI</name>
+          <description>SPI0 flash timing calibration register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_TIMING_CLK_ENA</name>
+              <description>The bit is used to enable timing adjust clock for all reading operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_TIMING_CALI</name>
+              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_EXTRA_DUMMY_CYCLELEN</name>
+              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DLL_TIMING_CALI</name>
+              <description>Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UPDATE</name>
+              <description>Set this bit to update delay mode, delay num and extra dummy in MSPI.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DIN_MODE</name>
+          <description>MSPI flash input timing delay mode control register</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_DIN0_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN1_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN2_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN3_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN4_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN5_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN6_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN7_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DINS_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DIN_NUM</name>
+          <description>MSPI flash input timing delay number control register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_DIN0_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN1_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN2_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN3_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN4_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN5_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN6_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DIN7_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DINS_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DOUT_MODE</name>
+          <description>MSPI flash output timing adjustment control register</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_DOUT0_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT1_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT2_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT3_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT4_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT5_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT6_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUT7_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_DOUTS_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_TIMING_CALI</name>
+          <description>MSPI external RAM timing calibration register</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_TIMING_CLK_ENA</name>
+              <description>For sram, the bit is used to enable timing adjust clock for all reading operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_TIMING_CALI</name>
+              <description>For sram, the bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_EXTRA_DUMMY_CYCLELEN</name>
+              <description>For sram, add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DLL_TIMING_CALI</name>
+              <description>Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DIN_MODE</name>
+          <description>MSPI external RAM input timing delay mode control register</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_DIN0_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN1_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN2_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN3_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN4_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN5_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN6_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN7_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DINS_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DIN_NUM</name>
+          <description>MSPI external RAM input timing delay number control register</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_DIN0_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN1_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN2_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN3_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN4_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN5_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN6_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN7_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DINS_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DOUT_MODE</name>
+          <description>MSPI external RAM output timing adjustment control register</description>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_DOUT0_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT1_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT2_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT3_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT4_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT5_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT6_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT7_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUTS_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_AC</name>
+          <description>MSPI external RAM ECC and SPI CS timing control register</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x8000B084</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_CS_SETUP</name>
+              <description>For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_HOLD</name>
+              <description>For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_SETUP_TIME</name>
+              <description>For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_HOLD_TIME</name>
+              <description>For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_CS_HOLD_TIME</name>
+              <description>SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_SKIP_PAGE_CORNER</name>
+              <description>1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_16TO18_BYTE_EN</name>
+              <description>Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_HOLD_DELAY</name>
+              <description>These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_SPLIT_TRANS_EN</name>
+              <description>Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CLOCK_GATE</name>
+          <description>SPI0 clock gate register</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_PLAIN_BASE</name>
+          <description>The base address of the memory that stores plaintext in Manual Encryption</description>
+          <addressOffset>0x300</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_PLAIN</name>
+              <description>This field is only used to generate include file in c case. This field is useless. Please do not use this field.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_LINESIZE</name>
+          <description>Manual Encryption Line-Size register</description>
+          <addressOffset>0x340</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_LINESIZE</name>
+              <description>This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_DESTINATION</name>
+          <description>Manual Encryption destination register</description>
+          <addressOffset>0x344</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_DESTINATION</name>
+              <description>This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_PHYSICAL_ADDRESS</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x348</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_PHYSICAL_ADDRESS</name>
+              <description>This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_TRIGGER</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x34C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_TRIGGER</name>
+              <description>Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_RELEASE</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x350</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_RELEASE</name>
+              <description>Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_DESTROY</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x354</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_DESTROY</name>
+              <description>Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_STATE</name>
+          <description>Manual Encryption physical address register</description>
+          <addressOffset>0x358</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_XTS_STATE</name>
+              <description>This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_XTS_DATE</name>
+          <description>Manual Encryption version register</description>
+          <addressOffset>0x35C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20201010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_XTS_DATE</name>
+              <description>This bits stores the last modified-time of manual encryption feature.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MMU_ITEM_CONTENT</name>
+          <description>MSPI-MMU item content register</description>
+          <addressOffset>0x37C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000037C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MMU_ITEM_CONTENT</name>
+              <description>MSPI-MMU item content</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MMU_ITEM_INDEX</name>
+          <description>MSPI-MMU item index register</description>
+          <addressOffset>0x380</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MMU_ITEM_INDEX</name>
+              <description>MSPI-MMU item index</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MMU_POWER_CTRL</name>
+          <description>MSPI MMU power control register</description>
+          <addressOffset>0x384</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x13200004</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MMU_MEM_FORCE_ON</name>
+              <description>Set this bit to enable mmu-memory clock force on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MMU_MEM_FORCE_PD</name>
+              <description>Set this bit to force mmu-memory powerdown</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MMU_MEM_FORCE_PU</name>
+              <description>Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MMU_PAGE_SIZE</name>
+              <description>0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_AUX_CTRL</name>
+              <description>MMU PSRAM aux control register</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RDN_ENA</name>
+              <description>ECO register enable bit</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RDN_RESULT</name>
+              <description>MSPI module clock domain and AXI clock domain ECO register result register</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DPA_CTRL</name>
+          <description>SPI memory cryption DPA register</description>
+          <addressOffset>0x388</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CRYPT_SECURITY_LEVEL</name>
+              <description>Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CRYPT_CALC_D_DPA_EN</name>
+              <description>Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CRYPT_DPA_SELECT_REGISTER</name>
+              <description>1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REGISTERRND_ECO_HIGH</name>
+          <description>MSPI ECO high register</description>
+          <addressOffset>0x3F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000037C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_REGISTERRND_ECO_HIGH</name>
+              <description>ECO high register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REGISTERRND_ECO_LOW</name>
+          <description>MSPI ECO low register</description>
+          <addressOffset>0x3F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000037C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_REGISTERRND_ECO_LOW</name>
+              <description>ECO low register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DATE</name>
+          <description>SPI0 version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02203030</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_DATE</name>
+              <description>SPI0 register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI1</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI1</groupName>
+      <baseAddress>0x60002000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xAC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI1</name>
+        <value>18</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SPI_MEM_CMD</name>
+          <description>SPI1 memory command register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_MST_ST</name>
+              <description>The current status of SPI1 master FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST</name>
+              <description>The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PE</name>
+              <description>In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_HPM</name>
+              <description>Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_RES</name>
+              <description>This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_DP</name>
+              <description>Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_CE</name>
+              <description>Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_BE</name>
+              <description>Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_SE</name>
+              <description>Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PP</name>
+              <description>Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_WRSR</name>
+              <description>Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_RDSR</name>
+              <description>Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_RDID</name>
+              <description>Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_WRDI</name>
+              <description>Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_WREN</name>
+              <description>Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_READ</name>
+              <description>Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_ADDR</name>
+          <description>SPI1 address register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_ADDR_VALUE</name>
+              <description>In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL</name>
+          <description>SPI1 control register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x002CA00C</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_FDUMMY_RIN</name>
+              <description>In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDUMMY_WOUT</name>
+              <description>In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_OCT</name>
+              <description>Apply 8 signals during write-data phase 1:enable 0: disable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_OCT</name>
+              <description>Apply 8 signals during read-data phase 1:enable 0: disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_OCT</name>
+              <description>Apply 8 signals during address phase 1:enable 0: disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCMD_OCT</name>
+              <description>Apply 8 signals during command phase 1:enable 0: disable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FCS_CRC_EN</name>
+              <description>For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_TX_CRC_EN</name>
+              <description>For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FASTRD_MODE</name>
+              <description>This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_RESANDRES</name>
+              <description>The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WRSR_2B</name>
+              <description>two bytes data will be written to status register when it is set. 1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_DIO</name>
+              <description>In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FREAD_QIO</name>
+              <description>In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL1</name>
+          <description>SPI1 control1 register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFC</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_HOLD_DLY_RES</name>
+              <description>After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CTRL2</name>
+          <description>SPI1 control2 register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_SYNC_RESET</name>
+              <description>The FSM will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CLOCK</name>
+          <description>SPI1 clock division control register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_mem_clkcnt_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CLK_EQU_SYSCLK</name>
+              <description>reserved</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER</name>
+          <description>SPI1 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FWRITE_DIO</name>
+              <description>In the write operations address phase and read-data phase apply 2 signals.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FWRITE_QIO</name>
+              <description>In the write operations address phase and read-data phase apply 4 signals.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DUMMY_IDLE</name>
+              <description>SPI clock is disable in dummy phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_ADDR</name>
+              <description>This bit enable the address phase of an operation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER1</name>
+          <description>SPI1 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000007</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_USER2</name>
+          <description>SPI1 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_COMMAND_VALUE</name>
+              <description>The value of  command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MOSI_DLEN</name>
+          <description>SPI1 send data bit length control register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_MOSI_DBITLEN</name>
+              <description>The length in bits of write-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MISO_DLEN</name>
+          <description>SPI1 receive data bit length control register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_USR_MISO_DBITLEN</name>
+              <description>The length in bits of  read-data. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_RD_STATUS</name>
+          <description>SPI1 status register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_STATUS</name>
+              <description>The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_MISC</name>
+          <description>SPI1 misc register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CS0_DIS</name>
+              <description>SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS1_DIS</name>
+              <description>SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_TX_CRC</name>
+          <description>SPI1 TX CRC data register.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>For SPI1, the value of crc32.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CACHE_FCTRL</name>
+          <description>SPI1 bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_CACHE_USR_ADDR_4BYTE</name>
+              <description>For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_DUAL</name>
+              <description>For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_DUAL</name>
+              <description>For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_DUAL</name>
+              <description>For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDIN_QUAD</name>
+              <description>For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FDOUT_QUAD</name>
+              <description>For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FADDR_QUAD</name>
+              <description>For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W0</name>
+          <description>SPI1 memory data buffer0</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W1</name>
+          <description>SPI1 memory data buffer1</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W2</name>
+          <description>SPI1 memory data buffer2</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W3</name>
+          <description>SPI1 memory data buffer3</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W4</name>
+          <description>SPI1 memory data buffer4</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W5</name>
+          <description>SPI1 memory data buffer5</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W6</name>
+          <description>SPI1 memory data buffer6</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W7</name>
+          <description>SPI1 memory data buffer7</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W8</name>
+          <description>SPI1 memory data buffer8</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W9</name>
+          <description>SPI1 memory data buffer9</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W10</name>
+          <description>SPI1 memory data buffer10</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W11</name>
+          <description>SPI1 memory data buffer11</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W12</name>
+          <description>SPI1 memory data buffer12</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W13</name>
+          <description>SPI1 memory data buffer13</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W14</name>
+          <description>SPI1 memory data buffer14</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_W15</name>
+          <description>SPI1 memory data buffer15</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_FLASH_WAITI_CTRL</name>
+          <description>SPI1 wait idle control register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00050001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_WAITI_EN</name>
+              <description>1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_DUMMY</name>
+              <description>The dummy phase enable when wait flash idle (RDSR)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_ADDR_EN</name>
+              <description>1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_ADDR_CYCLELEN</name>
+              <description>When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_CMD_2B</name>
+              <description>1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_DUMMY_CYCLELEN</name>
+              <description>The dummy cycle length when wait flash idle(RDSR).</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAITI_CMD</name>
+              <description>The command value to wait flash idle(RDSR).</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_FLASH_SUS_CTRL</name>
+          <description>SPI1 flash suspend control register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08002000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_FLASH_PER</name>
+              <description>program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PES</name>
+              <description>program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PER_WAIT_EN</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PES_WAIT_EN</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_PER_EN</name>
+              <description>Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PES_EN</name>
+              <description>Set this bit to enable Auto-suspending function.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PESR_END_MSK</name>
+              <description>The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_RD_SUS_2B</name>
+              <description>1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PER_END_EN</name>
+              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_EN</name>
+              <description>1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SUS_TIMEOUT_CNT</name>
+              <description>When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_FLASH_SUS_CMD</name>
+          <description>SPI1 flash suspend command register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00057575</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_FLASH_PES_COMMAND</name>
+              <description>Program/Erase suspend command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAIT_PESR_COMMAND</name>
+              <description>Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_SUS_STATUS</name>
+          <description>SPI1 flash suspend status register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7A7A0000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_FLASH_SUS</name>
+              <description>The status of flash suspend, only used in SPI1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WAIT_PESR_CMD_2B</name>
+              <description>1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_HPM_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_RES_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_DP_DLY_128</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PER_DLY_128</name>
+              <description>Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PES_DLY_128</name>
+              <description>Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SPI0_LOCK_EN</name>
+              <description>1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PESR_CMD_2B</name>
+              <description>1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_FLASH_PER_COMMAND</name>
+              <description>Program/Erase resume command.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_ENA</name>
+          <description>SPI1 interrupt enable register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_PER_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WPE_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_BROWN_OUT_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_CLR</name>
+          <description>SPI1 interrupt clear register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_PER_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WPE_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_BROWN_OUT_INT_CLR</name>
+              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_RAW</name>
+          <description>SPI1 interrupt raw register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_PER_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WPE_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_BROWN_OUT_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_INT_ST</name>
+          <description>SPI1 interrupt status register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_PER_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_PES_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_WPE_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_WPE_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_SLV_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_SLV_ST_END_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_MST_ST_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_MST_ST_END_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_BROWN_OUT_INT_ST</name>
+              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DDR</name>
+          <description>SPI1 DDR control register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_DDR_EN</name>
+              <description>1: in ddr mode,  0 in sdr mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_VAR_DUMMY</name>
+              <description>Set the bit to enable variable dummy cycle in spi ddr mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_RDAT_SWP</name>
+              <description>Set the bit to reorder rx data of the word in spi ddr mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_WDAT_SWP</name>
+              <description>Set the bit to reorder tx data of the word in spi ddr mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_CMD_DIS</name>
+              <description>the bit is used to disable dual edge in command phase when ddr mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OUTMINBYTELEN</name>
+              <description>It is the minimum output data length in the panda device.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_USR_DDR_DQS_THD</name>
+              <description>The delay number of data strobe which from memory based on SPI clock.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_DQS_LOOP</name>
+              <description>1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_EN</name>
+              <description>Set this bit to enable the differential SPI_CLK#.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DQS_CA_IN</name>
+              <description>Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_DUMMY_2X</name>
+              <description>Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_INV</name>
+              <description>Set this bit to invert SPI_DIFF when accesses to flash. .</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OCTA_RAM_ADDR</name>
+              <description>Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_CA</name>
+              <description>Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_TIMING_CALI</name>
+          <description>SPI1 timing control register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_TIMING_CALI</name>
+              <description>The bit is used to enable timing auto-calibration for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MEM_EXTRA_DUMMY_CYCLELEN</name>
+              <description>add extra dummy spi clock cycle length for spi clock calibration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_CLOCK_GATE</name>
+          <description>SPI1 clk_gate register</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02202160</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI2</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI2</groupName>
+      <baseAddress>0x60024000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x98</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI2</name>
+        <value>19</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SPI_CMD</name>
+          <description>Command control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_CONF_BITLEN</name>
+              <description>Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_UPDATE</name>
+              <description>Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_ADDR</name>
+          <description>Address value register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_USR_ADDR_VALUE</name>
+              <description>Address to slave. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CTRL</name>
+          <description>SPI control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003C0000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_DUMMY_OUT</name>
+              <description>0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FADDR_DUAL</name>
+              <description>Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FADDR_QUAD</name>
+              <description>Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FADDR_OCT</name>
+              <description>Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FCMD_DUAL</name>
+              <description>Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FCMD_OCT</name>
+              <description>Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FREAD_OCT</name>
+              <description>In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_HOLD_POL</name>
+              <description>SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_WP_POL</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RD_BIT_ORDER</name>
+              <description>In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_WR_BIT_ORDER</name>
+              <description>In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CLOCK</name>
+          <description>SPI clock control register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80003043</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLKDIV_PRE</name>
+              <description>In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLK_EQU_SYSCLK</name>
+              <description>In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER</name>
+          <description>SPI USER control register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x800000C0</resetValue>
+          <fields>
+            <field>
+              <name>SPI_DOUTDIN</name>
+              <description>Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_QPI_MODE</name>
+              <description>Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_OPI_MODE</name>
+              <description>Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_TSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals. Can be configured in CONF state.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FWRITE_OCT</name>
+              <description>In the write operations read-data phase apply 8 signals. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_USR_CONF_NXT</name>
+              <description>1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SIO</name>
+              <description>Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_ADDR</name>
+              <description>This bit enable the address phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER1</name>
+          <description>SPI USER control register 1</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xB8410007</resetValue>
+          <fields>
+            <field>
+              <name>SPI_USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_WFULL_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_SETUP_TIME</name>
+              <description>(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_HOLD_TIME</name>
+              <description>delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER2</name>
+          <description>SPI USER control register 2</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x78000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_USR_COMMAND_VALUE</name>
+              <description>The value of  command. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_REMPTY_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MS_DLEN</name>
+          <description>SPI data bit length control register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MS_DATA_BITLEN</name>
+              <description>The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MISC</name>
+          <description>SPI misc register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003E</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CS0_DIS</name>
+              <description>SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS1_DIS</name>
+              <description>SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS2_DIS</name>
+              <description>SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS3_DIS</name>
+              <description>SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS4_DIS</name>
+              <description>SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS5_DIS</name>
+              <description>SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CK_DIS</name>
+              <description>1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MASTER_CS_POL</name>
+              <description>In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLK_DATA_DTR_EN</name>
+              <description>1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DATA_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_ADDR_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_CMD_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLAVE_CS_POL</name>
+              <description>spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DQS_IDLE_EDGE</name>
+              <description>The default value of spi_dqs. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_QUAD_DIN_PIN_SWAP</name>
+              <description>1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DIN_MODE</name>
+          <description>SPI input delay mode configuration</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DIN0_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN1_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN2_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN3_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN4_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN5_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN6_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN7_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_TIMING_HCLK_ACTIVE</name>
+              <description>1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DIN_NUM</name>
+          <description>SPI input delay number configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DIN0_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN1_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN2_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN3_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DIN4_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN5_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN6_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DIN7_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DOUT_MODE</name>
+          <description>SPI output delay mode configuration</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DOUT0_MODE</name>
+              <description>The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DOUT1_MODE</name>
+              <description>The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DOUT2_MODE</name>
+              <description>The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DOUT3_MODE</name>
+              <description>The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DOUT4_MODE</name>
+              <description>The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOUT5_MODE</name>
+              <description>The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOUT6_MODE</name>
+              <description>The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DOUT7_MODE</name>
+              <description>The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_D_DQS_MODE</name>
+              <description>The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_CONF</name>
+          <description>SPI DMA control register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY</name>
+              <description>Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL</name>
+              <description>Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SLV_SEG_TRANS_EN</name>
+              <description>Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_TX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RX_EOF_EN</name>
+              <description>1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_RX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled receive data mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_TX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled send data mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RX_AFIFO_RST</name>
+              <description>Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_BUF_AFIFO_RST</name>
+              <description>Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_AFIFO_RST</name>
+              <description>Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_ENA</name>
+          <description>SPI interrupt enable register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_ENA</name>
+              <description>The enable bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_ENA</name>
+              <description>The enable bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_ENA</name>
+              <description>The enable bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_CLR</name>
+          <description>SPI interrupt clear register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_CLR</name>
+              <description>The clear bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_CLR</name>
+              <description>The clear bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_CLR</name>
+              <description>The clear bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_RAW</name>
+          <description>SPI interrupt raw register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_RAW</name>
+              <description>The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_RAW</name>
+              <description>The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_RAW</name>
+              <description>The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_ST</name>
+          <description>SPI interrupt status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_ST</name>
+              <description>The status bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_ST</name>
+              <description>The status bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_ST</name>
+              <description>The status bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_ST</name>
+              <description>The status bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_ST</name>
+              <description>The status bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_ST</name>
+              <description>The status bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_ST</name>
+              <description>The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_ST</name>
+              <description>The status bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_ST</name>
+              <description>The status bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DMA_INT_SET</name>
+          <description>SPI interrupt software set register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_DMA_INFIFO_FULL_ERR_INT_SET</name>
+              <description>The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET</name>
+              <description>The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EX_QPI_INT_SET</name>
+              <description>The software set bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_EN_QPI_INT_SET</name>
+              <description>The software set bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD7_INT_SET</name>
+              <description>The software set bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD8_INT_SET</name>
+              <description>The software set bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD9_INT_SET</name>
+              <description>The software set bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMDA_INT_SET</name>
+              <description>The software set bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_DMA_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_DMA_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RD_BUF_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WR_BUF_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_TRANS_DONE_INT_SET</name>
+              <description>The software set bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_TRANS_DONE_INT_SET</name>
+              <description>The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SEG_MAGIC_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_BUF_ADDR_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_SLV_CMD_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET</name>
+              <description>The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET</name>
+              <description>The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_APP2_INT_SET</name>
+              <description>The software set bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_APP1_INT_SET</name>
+              <description>The software set bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W0</name>
+          <description>SPI CPU-controlled buffer0</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W1</name>
+          <description>SPI CPU-controlled buffer1</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W2</name>
+          <description>SPI CPU-controlled buffer2</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W3</name>
+          <description>SPI CPU-controlled buffer3</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W4</name>
+          <description>SPI CPU-controlled buffer4</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W5</name>
+          <description>SPI CPU-controlled buffer5</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W6</name>
+          <description>SPI CPU-controlled buffer6</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W7</name>
+          <description>SPI CPU-controlled buffer7</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W8</name>
+          <description>SPI CPU-controlled buffer8</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W9</name>
+          <description>SPI CPU-controlled buffer9</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W10</name>
+          <description>SPI CPU-controlled buffer10</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W11</name>
+          <description>SPI CPU-controlled buffer11</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W12</name>
+          <description>SPI CPU-controlled buffer12</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W13</name>
+          <description>SPI CPU-controlled buffer13</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W14</name>
+          <description>SPI CPU-controlled buffer14</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W15</name>
+          <description>SPI CPU-controlled buffer15</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE</name>
+          <description>SPI slave control register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02800000</resetValue>
+          <fields>
+            <field>
+              <name>SPI_CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_CLK_MODE_13</name>
+              <description>{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_RSCK_DATA_OUT</name>
+              <description>It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RDDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WRDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_RDBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_WRBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_DMA_SEG_MAGIC_VALUE</name>
+              <description>The magic value of BM table in master DMA seg-trans.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Set SPI work mode. 1: slave mode 0: master mode.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SOFT_RESET</name>
+              <description>Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_USR_CONF</name>
+              <description>1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_FD_WAIT_DMA_TX_DATA</name>
+              <description>In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE1</name>
+          <description>SPI slave control register 1</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SLV_DATA_BITLEN</name>
+              <description>The transferred data bit length in SPI slave FD and HD mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_LAST_COMMAND</name>
+              <description>In the slave mode it is the value of command.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SLV_LAST_ADDR</name>
+              <description>In the slave mode it is the value of address.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CLK_GATE</name>
+          <description>SPI module clock and register clock control</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_CLK_ACTIVE</name>
+              <description>Set this bit to power on the SPI module clock.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_MST_CLK_SEL</name>
+              <description>This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_DATE</name>
+          <description>Version control</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201300</resetValue>
+          <fields>
+            <field>
+              <name>SPI_DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SPI2">
+      <name>SPI3</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x60025000</baseAddress>
+    </peripheral>
+    <peripheral derivedFrom="SPI2">
+      <name>SPI4</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x60037000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>SYSTIMER</name>
+      <description>System Timer</description>
+      <groupName>SYSTIMER</groupName>
+      <baseAddress>0x60023000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x90</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSTIMER_TARGET0_EDGE</name>
+        <value>37</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET1_EDGE</name>
+        <value>38</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET2_EDGE</name>
+        <value>39</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF</name>
+          <description>Configure system timer clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x46000000</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_CLK_FO</name>
+              <description>systimer clock force on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ETM_EN</name>
+              <description>enable systimer's etm task and event</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_WORK_EN</name>
+              <description>target2 work enable</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_WORK_EN</name>
+              <description>target1 work enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_WORK_EN</name>
+              <description>target0 work enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE1_STALL_EN</name>
+              <description>If timer unit1 is stalled when core1 stalled</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE0_STALL_EN</name>
+              <description>If timer unit1 is stalled when core0 stalled</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE1_STALL_EN</name>
+              <description>If timer unit0 is stalled when core1 stalled</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE0_STALL_EN</name>
+              <description>If timer unit0 is stalled when core0 stalled</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_WORK_EN</name>
+              <description>timer unit1 work enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_WORK_EN</name>
+              <description>timer unit0 work enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>register file clk gating</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_OP</name>
+          <description>system timer unit0 value update register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_VALID</name>
+              <description>timer value is sync and valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_UPDATE</name>
+              <description>update timer_unit0</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_OP</name>
+          <description>system timer unit1 value update register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_VALID</name>
+              <description>timer value is sync and valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_UPDATE</name>
+              <description>update timer unit1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_HI</name>
+          <description>system timer unit0 value high load register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_HI</name>
+              <description>timer unit0 load high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_LO</name>
+          <description>system timer unit0 value low load register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_LO</name>
+              <description>timer unit0 load low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_HI</name>
+          <description>system timer unit1 value high load register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_HI</name>
+              <description>timer unit1 load high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_LO</name>
+          <description>system timer unit1 value low load register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_LO</name>
+              <description>timer unit1 load low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_HI</name>
+          <description>system timer comp0 value high register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_HI</name>
+              <description>timer taget0 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_LO</name>
+          <description>system timer comp0 value low register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_LO</name>
+              <description>timer taget0 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_HI</name>
+          <description>system timer comp1 value high register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_HI</name>
+              <description>timer taget1 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_LO</name>
+          <description>system timer comp1 value low register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_LO</name>
+              <description>timer taget1 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_HI</name>
+          <description>system timer comp2 value high register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_HI</name>
+              <description>timer taget2 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_LO</name>
+          <description>system timer comp2 value low register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_LO</name>
+              <description>timer taget2 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_CONF</name>
+          <description>system timer comp0 target mode register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_PERIOD</name>
+              <description>target0 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_PERIOD_MODE</name>
+              <description>Set target0 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_CONF</name>
+          <description>system timer comp1 target mode register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_PERIOD</name>
+              <description>target1 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_PERIOD_MODE</name>
+              <description>Set target1 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_CONF</name>
+          <description>system timer comp2 target mode register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_PERIOD</name>
+              <description>target2 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_PERIOD_MODE</name>
+              <description>Set target2 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_HI</name>
+          <description>system timer unit0 value high register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_HI</name>
+              <description>timer read value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_LO</name>
+          <description>system timer unit0 value low register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_LO</name>
+              <description>timer read value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_HI</name>
+          <description>system timer unit1 value high register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_HI</name>
+              <description>timer read value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_LO</name>
+          <description>system timer unit1 value low register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_LO</name>
+              <description>timer read value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP0_LOAD</name>
+          <description>system timer comp0 conf sync register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP0_LOAD</name>
+              <description>timer comp0 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP1_LOAD</name>
+          <description>system timer comp1 conf sync register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP1_LOAD</name>
+              <description>timer comp1 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP2_LOAD</name>
+          <description>system timer comp2 conf sync register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP2_LOAD</name>
+              <description>timer comp2 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD</name>
+          <description>system timer unit0 conf sync register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD</name>
+              <description>timer unit0 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD</name>
+          <description>system timer unit1 conf sync register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD</name>
+              <description>timer unit1 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>systimer interrupt enable register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ENA</name>
+              <description>interupt0 enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ENA</name>
+              <description>interupt1 enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ENA</name>
+              <description>interupt2 enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>systimer interrupt raw register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_RAW</name>
+              <description>interupt0 raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_RAW</name>
+              <description>interupt1 raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_RAW</name>
+              <description>interupt2 raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>systimer interrupt clear register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_CLR</name>
+              <description>interupt0 clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_CLR</name>
+              <description>interupt1 clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_CLR</name>
+              <description>interupt2 clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>systimer interrupt status register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ST</name>
+              <description>interupt0 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ST</name>
+              <description>interupt1 status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ST</name>
+              <description>interupt2 status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET0_LO</name>
+          <description>system timer comp0 actual target value low register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_LO_RO</name>
+              <description>actual target value value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET0_HI</name>
+          <description>system timer comp0 actual target value high register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_HI_RO</name>
+              <description>actual target value value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET1_LO</name>
+          <description>system timer comp1 actual target value low register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_LO_RO</name>
+              <description>actual target value value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET1_HI</name>
+          <description>system timer comp1 actual target value high register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_HI_RO</name>
+              <description>actual target value value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET2_LO</name>
+          <description>system timer comp2 actual target value low register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_LO_RO</name>
+              <description>actual target value value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET2_HI</name>
+          <description>system timer comp2 actual target value high register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_HI_RO</name>
+              <description>actual target value value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>system timer version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201073</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>systimer register version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TEE</name>
+      <description>Peripheral TEE</description>
+      <groupName>TEE</groupName>
+      <baseAddress>0x60098000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>M0_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M0_MODE</name>
+              <description>M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M1_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M1_MODE</name>
+              <description>M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M2_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M2_MODE</name>
+              <description>M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M3_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M3_MODE</name>
+              <description>M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M4_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M4_MODE</name>
+              <description>M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M5_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M5_MODE</name>
+              <description>M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M6_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M6_MODE</name>
+              <description>M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M7_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M7_MODE</name>
+              <description>M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M8_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M8_MODE</name>
+              <description>M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M9_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M9_MODE</name>
+              <description>M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M10_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M10_MODE</name>
+              <description>M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M11_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M11_MODE</name>
+              <description>M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M12_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M12_MODE</name>
+              <description>M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M13_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M13_MODE</name>
+              <description>M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M14_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M14_MODE</name>
+              <description>M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M15_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M15_MODE</name>
+              <description>M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M16_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M16_MODE</name>
+              <description>M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M17_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M17_MODE</name>
+              <description>M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M18_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M18_MODE</name>
+              <description>M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M19_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M19_MODE</name>
+              <description>M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M20_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M20_MODE</name>
+              <description>M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M21_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M21_MODE</name>
+              <description>M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M22_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M22_MODE</name>
+              <description>M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M23_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M23_MODE</name>
+              <description>M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M24_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M24_MODE</name>
+              <description>M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M25_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M25_MODE</name>
+              <description>M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M26_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M26_MODE</name>
+              <description>M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M27_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M27_MODE</name>
+              <description>M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M28_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M28_MODE</name>
+              <description>M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M29_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M29_MODE</name>
+              <description>M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M30_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M30_MODE</name>
+              <description>M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>M31_MODE_CTRL</name>
+          <description>Tee mode control register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>M31_MODE</name>
+              <description>M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>Clock gating register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>reg_clk_en</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02205282</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>reg_tee_date</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TIMG0</name>
+      <description>Timer Group</description>
+      <groupName>TIMG</groupName>
+      <baseAddress>0x6001F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TG0_T0_LEVEL</name>
+        <value>32</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_WDT_LEVEL</name>
+        <value>33</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>T0CONFIG</name>
+          <description>Timer %s configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002000</resetValue>
+          <fields>
+            <field>
+              <name>T_USE_XTAL</name>
+              <description>1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_ALARM_EN</name>
+              <description>When set, the alarm is enabled. This bit is automatically cleared once an
+alarm occurs.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_DIVCNT_RST</name>
+              <description>When set, Timer %s 's clock divider counter will be reset.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>T_DIVIDER</name>
+              <description>Timer %s clock (T%s_clk) prescaler value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_AUTORELOAD</name>
+              <description>When set, timer %s auto-reload at alarm is enabled.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_INCREASE</name>
+              <description>When set, the timer %s time-base counter will increment every clock tick. When
+cleared, the timer %s time-base counter will decrement.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T_EN</name>
+              <description>When set, the timer %s time-base counter is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LO</name>
+          <description>Timer %s current value, low 32 bits</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LO</name>
+              <description>After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter
+of timer %s can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0HI</name>
+          <description>Timer %s current value, high 22 bits</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_HI</name>
+              <description>After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter
+of timer %s can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0UPDATE</name>
+          <description>Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_UPDATE</name>
+              <description>After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMLO</name>
+          <description>Timer %s alarm value, low 32 bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_ALARM_LO</name>
+              <description>Timer %s alarm trigger time-base counter value, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0ALARMHI</name>
+          <description>Timer %s alarm value, high bits</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_ALARM_HI</name>
+              <description>Timer %s alarm trigger time-base counter value, high 22 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADLO</name>
+          <description>Timer %s reload value, low 32 bits</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LOAD_LO</name>
+              <description>Low 32 bits of the value that a reload will load onto timer %s time-base
+Counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOADHI</name>
+          <description>Timer %s reload value, high 22 bits</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LOAD_HI</name>
+              <description>High 22 bits of the value that a reload will load onto timer %s time-base
+counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T0LOAD</name>
+          <description>Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LOAD</name>
+              <description>
+Write any value to trigger a timer %s time-base counter reload.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>Watchdog timer configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0004C000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>WDT reset CPU enable.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>WDT reset CPU enable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>When set, Flash boot protection is enabled.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>System reset signal length selection. 0: 100 ns, 1: 200 ns,
+2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_USE_XTAL</name>
+              <description>choose WDT clock:0-apb_clk, 1-xtal_clk.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CONF_UPDATE_EN</name>
+              <description>update the WDT configuration registers</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>When set, MWDT is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>Watchdog timer prescaler register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_DIVCNT_RST</name>
+              <description>When set, WDT 's clock divider counter will be reset.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_CLK_PRESCALE</name>
+              <description>MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+TIMG_WDT_CLK_PRESCALE.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>Watchdog timer stage 0 timeout value</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x018CBA80</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>Stage 0 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>Watchdog timer stage 1 timeout value</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>Stage 1 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>Watchdog timer stage 2 timeout value</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>Stage 2 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG5</name>
+          <description>Watchdog timer stage 3 timeout value</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>Stage 3 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>Write to feed the watchdog timer</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>Write any value to feed the MWDT. (WO)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>Watchdog write protect register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>If the register contains a different value than its reset value, write
+protection is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG</name>
+          <description>RTC calibration configure register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00011000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_START_CYCLING</name>
+              <description>0: one-shot frequency calculation,1: periodic frequency calculation,</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_CLK_SEL</name>
+              <description>0:rtc slow clock. 1:clk_8m, 2:xtal_32k.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_RDY</name>
+              <description>indicate one-shot frequency calculation is done.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_MAX</name>
+              <description>Configure the time to calculate RTC slow clock's frequency.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_START</name>
+              <description>Set this bit to start one-shot frequency calculation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG1</name>
+          <description>RTC calibration configure1 register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_CALI_CYCLING_DATA_VLD</name>
+              <description>indicate periodic frequency calculation is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_VALUE</name>
+              <description>When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_TIMERS</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_TIMERS</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_TIMERS</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_TIMERS</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG2</name>
+          <description>Timer group calibration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFF98</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_TIMEOUT</name>
+              <description>RTC calibration timeout indicator</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_RST_CNT</name>
+              <description>Cycles that release calibration timeout reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_THRES</name>
+              <description>Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NTIMERS_DATE</name>
+          <description>Timer version control register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02206072</resetValue>
+          <fields>
+            <field>
+              <name>NTIMGS_DATE</name>
+              <description>Timer version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGCLK</name>
+          <description>Timer group clock gate register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>ETM_EN</name>
+              <description>enable timer's etm task and event</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CLK_IS_ACTIVE</name>
+              <description>enable WDT's clock</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_CLK_IS_ACTIVE</name>
+              <description>enable Timer 30's clock</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMG0">
+      <name>TIMG1</name>
+      <description>Timer Group</description>
+      <baseAddress>0x60020000</baseAddress>
+      <interrupt>
+        <name>TG1_T0_LEVEL</name>
+        <value>34</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_WDT_LEVEL</name>
+        <value>35</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TWAI</name>
+      <description>Two-Wire Automotive Interface</description>
+      <groupName>TWAI</groupName>
+      <baseAddress>0x6002B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x80</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TWAI</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>TWAI mode register.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RESET_MODE</name>
+              <description>1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LISTEN_ONLY_MODE</name>
+              <description>1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SELF_TEST_MODE</name>
+              <description>1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ACCEPTANCE_FILTER_MODE</name>
+              <description>1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active).</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>TWAI command register.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_REQUEST</name>
+              <description>1: present, a message shall be transmitted. 0: absent</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ABORT_TX</name>
+              <description>1: present, if not already in progress, a pending transmission request is cancelled. 0: absent</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RELEASE_BUFFER</name>
+              <description>1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CLEAR_DATA_OVERRUN</name>
+              <description>1: clear, the data overrun status bit is cleared. 0: no action.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SELF_RX_REQUEST</name>
+              <description>1: present, a message shall be transmitted and received simultaneously. 0: absent.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>TWAI status register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECEIVE_BUFFER</name>
+              <description>1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN</name>
+              <description>1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANSMIT_BUFFER</name>
+              <description>1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANSMISSION_COMPLETE</name>
+              <description>1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RECEIVE</name>
+              <description>1: receive, the TWAI controller is receiving a message. 0: idle</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANSMIT</name>
+              <description>1: transmit, the TWAI controller is transmitting a message. 0: idle</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR</name>
+              <description>1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NODE_BUS_OFF</name>
+              <description>1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MISS</name>
+              <description>1: current message is destroyed because of FIFO overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT</name>
+          <description>Interrupt signals' register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECEIVE_INT_ST</name>
+              <description>1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANSMIT_INT_ST</name>
+              <description>1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_WARNING_INT_ST</name>
+              <description>1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DATA_OVERRUN_INT_ST</name>
+              <description>1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ST</name>
+              <description>1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ST</name>
+              <description>1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IDLE_INT_ST</name>
+              <description>1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT_ENABLE</name>
+          <description>Interrupt enable register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_RECEIVE_INT_ENA</name>
+              <description>1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_TRANSMIT_INT_ENA</name>
+              <description>1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_ERR_WARNING_INT_ENA</name>
+              <description>1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_DATA_OVERRUN_INT_ENA</name>
+              <description>1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ENA</name>
+              <description>1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ENA</name>
+              <description>1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_INT_ENA</name>
+              <description>1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_0</name>
+          <description>Bit timing configuration register 0.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BAUD_PRESC</name>
+              <description>The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC_JUMP_WIDTH</name>
+              <description>The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_1</name>
+          <description>Bit timing configuration register 1.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_SEGMENT1</name>
+              <description>The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SEGMENT2</name>
+              <description>The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SAMPLING</name>
+              <description>1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_LOST_CAP</name>
+          <description>TWAI arbiter lost capture register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ARBITRATION_LOST_CAPTURE</name>
+              <description>This register contains information about the bit position of losing arbitration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_CODE_CAP</name>
+          <description>TWAI error info capture register.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ERR_CAPTURE_CODE_SEGMENT</name>
+              <description>This register contains information about the location of errors on the bus.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_CAPTURE_CODE_DIRECTION</name>
+              <description>1: RX, error occurred during reception. 0: TX, error occurred during transmission.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_CAPTURE_CODE_TYPE</name>
+              <description>00: bit error. 01: form error. 10:stuff error. 11:other type of error.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_WARNING_LIMIT</name>
+          <description>TWAI error threshold configuration register.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000060</resetValue>
+          <fields>
+            <field>
+              <name>ERR_WARNING_LIMIT</name>
+              <description>The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_ERR_CNT</name>
+          <description>Rx error counter register.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CNT</name>
+              <description>The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_ERR_CNT</name>
+          <description>Tx error counter register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_ERR_CNT</name>
+              <description>The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_0</name>
+          <description>Data register 0.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_0</name>
+              <description>In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_1</name>
+          <description>Data register 1.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_1</name>
+              <description>In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_2</name>
+          <description>Data register 2.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_2</name>
+              <description>In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_3</name>
+          <description>Data register 3.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_3</name>
+              <description>In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_4</name>
+          <description>Data register 4.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_4</name>
+              <description>In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_5</name>
+          <description>Data register 5.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_5</name>
+              <description>In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_6</name>
+          <description>Data register 6.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_6</name>
+              <description>In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_7</name>
+          <description>Data register 7.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_7</name>
+              <description>In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_8</name>
+          <description>Data register 8.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_8</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_9</name>
+          <description>Data register 9.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_9</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_10</name>
+          <description>Data register 10.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_10</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_11</name>
+          <description>Data register 11.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_11</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_12</name>
+          <description>Data register 12.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_12</name>
+              <description>In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_MESSAGE_COUNTER</name>
+          <description>Received message counter register.</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_MESSAGE_COUNTER</name>
+              <description>Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_DIVIDER</name>
+          <description>Clock divider register.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CD</name>
+              <description>These bits are used to define the frequency at the external CLKOUT pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLOCK_OFF</name>
+              <description>1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SW_STANDBY_CFG</name>
+          <description>Software configure standby pin directly.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>SW_STANDBY_EN</name>
+              <description>Enable standby pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STANDBY_CLR</name>
+              <description>Clear standby pin.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HW_CFG</name>
+          <description>Hardware configure standby pin.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HW_STANDBY_EN</name>
+              <description>Enable function that hardware control standby pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HW_STANDBY_CNT</name>
+          <description>Configure standby counter.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>STANDBY_WAIT_CNT</name>
+              <description>Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_INTR_CNT</name>
+          <description>Configure idle interrupt counter.</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IDLE_INTR_CNT</name>
+              <description>Configure the number of cycles before triggering idle interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ECO_CFG</name>
+          <description>ECO configuration register.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RDN_ENA</name>
+              <description>Enable eco module.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDN_RESULT</name>
+              <description>Output of eco module.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>UART0</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x60000000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x98</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART0</name>
+        <value>21</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>FIFO</name>
+          <description>FIFO data register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RD_BYTE</name>
+              <description>UART 0 accesses FIFO via this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error in the data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error .</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters after all data in Tx-FIFO are sent.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ST</name>
+              <description>This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ST</name>
+              <description>This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ST</name>
+              <description>This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ST</name>
+              <description>This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ST</name>
+              <description>This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ST</name>
+              <description>This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ST</name>
+              <description>This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ST</name>
+              <description>This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ST</name>
+              <description>This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ST</name>
+              <description>This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ST</name>
+              <description>This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ST</name>
+              <description>This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ST</name>
+              <description>This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ST</name>
+              <description>This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_full_int_st register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ENA</name>
+              <description>This is the enable bit for txfifo_empty_int_st register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for parity_err_int_st register.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for frm_err_int_st register.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_ovf_int_st register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ENA</name>
+              <description>This is the enable bit for dsr_chg_int_st register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ENA</name>
+              <description>This is the enable bit for cts_chg_int_st register.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ENA</name>
+              <description>This is the enable bit for brk_det_int_st register.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_tout_int_st register.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ENA</name>
+              <description>This is the enable bit for sw_xon_int_st register.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ENA</name>
+              <description>This is the enable bit for sw_xoff_int_st register.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>This is the enable bit for glitch_det_int_st register.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_done_int_st register.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_idle_done_int_st register.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_done_int_st register.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ENA</name>
+              <description>This is the enable bit for rs485_clash_int_st register.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ENA</name>
+              <description>This is the enable bit for at_cmd_char_det_int_st register.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ENA</name>
+              <description>This is the enable bit for uart_wakeup_int_st register.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_full_int_raw interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear txfifo_empty_int_raw interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear parity_err_int_raw interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear frm_err_int_raw interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear rxfifo_ovf_int_raw interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_CLR</name>
+              <description>Set this bit to clear the dsr_chg_int_raw interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear the cts_chg_int_raw interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_CLR</name>
+              <description>Set this bit to clear the brk_det_int_raw interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_tout_int_raw interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_CLR</name>
+              <description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_CLR</name>
+              <description>Set this bit to clear the sw_xoff_int_raw interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Set this bit to clear the glitch_det_int_raw interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_done_int_raw interrupt..</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_idle_done_int_raw interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_done_int_raw interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_parity_err_int_raw interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_frm_err_int_raw interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_CLR</name>
+              <description>Set this bit to clear the rs485_clash_int_raw interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_CLR</name>
+              <description>Set this bit to clear the at_cmd_char_det_int_raw interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_CLR</name>
+              <description>Set this bit to clear the uart_wakeup_int_raw interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV_SYNC</name>
+          <description>Clock divider configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000002B6</resetValue>
+          <fields>
+            <field>
+              <name>CLKDIV</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKDIV_FRAG</name>
+              <description>The decimal part of the frequency divider factor.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_FILT</name>
+          <description>Rx Filter configuration</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>GLITCH_FILT</name>
+              <description>when input pulse width is lower than this value the pulse is ignored.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_FILT_EN</name>
+              <description>Set this bit to enable Rx signal filter.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>UART status register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xE000C000</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>Stores the byte number of valid data in Rx-FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSRN</name>
+              <description>The register represent the level value of the internal uart dsr signal.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTSN</name>
+              <description>This register represent the level value of the internal uart cts signal.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXD</name>
+              <description>This register represent the  level value of the internal uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>Stores the byte number of data in Tx-FIFO.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTRN</name>
+              <description>This bit represents the level of the internal uart dtr signal.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTSN</name>
+              <description>This bit represents the level of the internal uart rts signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXD</name>
+              <description>This bit represents the  level of the internal uart txd signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0_SYNC</name>
+          <description>a</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0010001C</resetValue>
+          <fields>
+            <field>
+              <name>PARITY</name>
+              <description>This register is used to configure the parity check mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_EN</name>
+              <description>Set this bit to enable uart parity check.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIT_NUM</name>
+              <description>This register is used to set the length of data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOP_BIT_NUM</name>
+              <description>This register is used to set the length of  stop bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_BRK</name>
+              <description>Set this bit to enbale transmitter to  send NULL when the process of sending data is done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_DPLX</name>
+              <description>Set this bit to enable IrDA loopback mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_EN</name>
+              <description>This is the start enable bit for IrDA transmitter.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_WCTL</name>
+              <description>1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_INV</name>
+              <description>Set this bit to invert the level of  IrDA transmitter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_RX_INV</name>
+              <description>Set this bit to invert the level of IrDA receiver.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOPBACK</name>
+              <description>Set this bit to enable uart loopback test mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FLOW_EN</name>
+              <description>Set this bit to enable flow control function for transmitter.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_EN</name>
+              <description>Set this bit to enable IrDA protocol.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXD_INV</name>
+              <description>Set this bit to inverse the level value of uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_INV</name>
+              <description>Set this bit to inverse the level value of uart txd signal.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIS_RX_DAT_OVF</name>
+              <description>Disable UART Rx data overflow detect.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WR_MASK</name>
+              <description>1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTOBAUD_EN</name>
+              <description>This is the enable bit for detecting baudrate.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_EN</name>
+              <description>UART memory clock gate enable signal.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_RTS</name>
+              <description>This register is used to configure the software rts signal which is used in software flow control.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>Set this bit to reset the uart receive-FIFO.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_RST</name>
+              <description>Set this bit to reset the uart transmit-FIFO.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>Configuration register 1</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00006060</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_THRHD</name>
+              <description>It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_THRHD</name>
+              <description>It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_INV</name>
+              <description>Set this bit to inverse the level value of uart cts signal.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_INV</name>
+              <description>Set this bit to inverse the level value of uart dsr signal.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTS_INV</name>
+              <description>Set this bit to inverse the level value of uart rts signal.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTR_INV</name>
+              <description>Set this bit to inverse the level value of uart dtr signal.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_DTR</name>
+              <description>This register is used to configure the software dtr signal which is used in software flow control.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HWFC_CONF_SYNC</name>
+          <description>Hardware flow-control configuration</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_FLOW_THRHD</name>
+              <description>This register is used to configure the maximum amount of data that can be received  when hardware flow control works.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_EN</name>
+              <description>This is the flow enable bit for UART receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF0</name>
+          <description>UART sleep configure register 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WK_CHAR1</name>
+              <description>This register restores the specified wake up char1 to wake up</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR2</name>
+              <description>This register restores the specified wake up char2 to wake up</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR3</name>
+              <description>This register restores the specified wake up char3 to wake up</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR4</name>
+              <description>This register restores the specified wake up char4 to wake up</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF1</name>
+          <description>UART sleep configure register 1</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WK_CHAR0</name>
+              <description>This register restores the specified char0 to wake up</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF2</name>
+          <description>UART sleep configure register 2</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001404F0</resetValue>
+          <fields>
+            <field>
+              <name>ACTIVE_THRESHOLD</name>
+              <description>The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WAKE_UP_THRHD</name>
+              <description>In wake up mode 1 this field is used to set the received data number threshold to wake up chip.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR_NUM</name>
+              <description>This register is used to select number of wake up char.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_CHAR_MASK</name>
+              <description>This register is used to mask  wake up char.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WK_MODE_SEL</name>
+              <description>This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF0_SYNC</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001311</resetValue>
+          <fields>
+            <field>
+              <name>XON_CHAR</name>
+              <description>This register stores the Xon flow control char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_CHAR</name>
+              <description>This register stores the Xoff flow control char.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XON_XOFF_STILL_SEND</name>
+              <description>In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_FLOW_CON_EN</name>
+              <description>Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XONOFF_DEL</name>
+              <description>Set this bit to remove flow control char from the received data.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XON</name>
+              <description>Set this bit to enable the transmitter to go on sending data.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XOFF</name>
+              <description>Set this bit to stop the  transmitter from sending data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XON</name>
+              <description>Set this bit to send Xon char. It is cleared by hardware automatically.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XOFF</name>
+              <description>Set this bit to send Xoff char. It is cleared by hardware automatically.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF1</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000E000</resetValue>
+          <fields>
+            <field>
+              <name>XON_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1  it will send a Xon char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1  it will send a Xoff char.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXBRK_CONF_SYNC</name>
+          <description>Tx Break character configuration</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>TX_BRK_NUM</name>
+              <description>This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_CONF_SYNC</name>
+          <description>Frame-end idle configuration</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040100</resetValue>
+          <fields>
+            <field>
+              <name>RX_IDLE_THRHD</name>
+              <description>It will produce frame end signal when receiver takes more time to receive one byte data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between transfers.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RS485_CONF_SYNC</name>
+          <description>RS485 mode configuration</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RS485_EN</name>
+              <description>Set this bit to choose the rs485 mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL0_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL1_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485TX_RX_EN</name>
+              <description>Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485RXBY_TX_EN</name>
+              <description>1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_RX_DLY_NUM</name>
+              <description>This register is used to delay the receiver's internal data signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_TX_DLY_NUM</name>
+              <description>This register is used to delay the transmitter's internal data signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_PRECNT_SYNC</name>
+          <description>Pre-sequence timing configuration</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>PRE_IDLE_NUM</name>
+              <description>This register is used to configure the idle duration time before the first at_cmd is received by receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_POSTCNT_SYNC</name>
+          <description>Post-sequence timing configuration</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>POST_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between the last at_cmd and the next data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_GAPTOUT_SYNC</name>
+          <description>Timeout configuration</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>RX_GAP_TOUT</name>
+              <description>This register is used to configure the duration time between the at_cmd chars.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_CHAR_SYNC</name>
+          <description>AT escape sequence detection configuration</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000032B</resetValue>
+          <fields>
+            <field>
+              <name>AT_CMD_CHAR</name>
+              <description>This register is used to configure the content of at_cmd char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAR_NUM</name>
+              <description>This register is used to configure the num of continuous at_cmd chars received by receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>UART memory power configuration</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to force power down UART memory.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>Set this bit to force power up UART memory.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUT_CONF_SYNC</name>
+          <description>UART threshold and allocation configuration</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000028</resetValue>
+          <fields>
+            <field>
+              <name>RX_TOUT_EN</name>
+              <description>This is the enble bit for uart receiver's timeout function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_FLOW_DIS</name>
+              <description>Set this bit to stop accumulating idle_cnt when hardware flow control works.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_THRHD</name>
+              <description>This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_TX_STATUS</name>
+          <description>Tx-SRAM write and read offset address.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_SRAM_WADDR</name>
+              <description>This register stores the offset write address in Tx-SRAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_SRAM_RADDR</name>
+              <description>This register stores the offset read address in Tx-SRAM.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_RX_STATUS</name>
+          <description>Rx-SRAM write and read offset address.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010080</resetValue>
+          <fields>
+            <field>
+              <name>RX_SRAM_RADDR</name>
+              <description>This register stores the offset read address in RX-SRAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_SRAM_WADDR</name>
+              <description>This register stores the offset write address in Rx-SRAM.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_STATUS</name>
+          <description>UART transmit and receive status.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST_URX_OUT</name>
+              <description>This is the status register of receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ST_UTX_OUT</name>
+              <description>This is the status register of transmitter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POSPULSE</name>
+          <description>Autobaud high pulse register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>POSEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NEGPULSE</name>
+          <description>Autobaud low pulse register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>NEGEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOWPULSE</name>
+          <description>Autobaud minimum low pulse duration register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HIGHPULSE</name>
+          <description>Autobaud minimum high pulse duration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXD_CNT</name>
+          <description>Autobaud edge change count register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXD_EDGE_CNT</name>
+              <description>This register stores the count of rxd edge change. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>UART core clock configuration</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03000000</resetValue>
+          <fields>
+            <field>
+              <name>TX_SCLK_EN</name>
+              <description>Set this bit to enable UART Tx clock.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SCLK_EN</name>
+              <description>Set this bit to enable UART Rx clock.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit to reset UART Tx.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit to reset UART Rx.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UART Version register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02207250</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AFIFO_STATUS</name>
+          <description>UART AFIFO Status</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>TX_AFIFO_FULL</name>
+              <description>Full signal of APB TX AFIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_AFIFO_EMPTY</name>
+              <description>Empty signal of APB TX AFIFO.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_AFIFO_FULL</name>
+              <description>Full signal of APB RX AFIFO.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_AFIFO_EMPTY</name>
+              <description>Empty signal of APB RX AFIFO.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_UPDATE</name>
+          <description>UART Registers Configuration Update register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REG_UPDATE</name>
+              <description>Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ID</name>
+          <description>UART ID register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000500</resetValue>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>This register is used to configure the uart_id.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <name>UART1</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <baseAddress>0x60010000</baseAddress>
+      <interrupt>
+        <name>UART1</name>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>UHCI0</name>
+      <description>Universal Host Controller Interface</description>
+      <groupName>UHCI</groupName>
+      <baseAddress>0x60014000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x84</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UHCI0</name>
+        <value>15</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF0</name>
+          <description>a</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000006E0</resetValue>
+          <fields>
+            <field>
+              <name>TX_RST</name>
+              <description>Write 1 then write 0 to this bit to reset decode state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST</name>
+              <description>Write 1 then write 0 to this bit to reset encode state machine.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_CE</name>
+              <description>Set this bit to link up HCI and UART0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CE</name>
+              <description>Set this bit to link up HCI and UART1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_EN</name>
+              <description>Set this bit to separate the data frame using a special char.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HEAD_EN</name>
+              <description>Set this bit to encode the data packet with a formatting header.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_REC_EN</name>
+              <description>Set this bit to enable UHCI to receive the 16 bit CRC.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_IDLE_EOF_EN</name>
+              <description>If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEN_EOF_EN</name>
+              <description>If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCODE_CRC_EN</name>
+              <description>Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RX_BRK_EOF_EN</name>
+              <description>If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>a</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_RAW</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when there are some errors in EOF in the</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_RAW</name>
+              <description>Soft control int raw bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_RAW</name>
+              <description>Soft control int raw bit.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>a</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ST</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ST</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ST</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ST</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ST</name>
+              <description>a</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_ST</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_ST</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>a</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_ENA</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>a</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_CLR</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>a</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>CHECK_SUM_EN</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_SEQ_EN</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_DISABLE</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAVE_HEAD</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHECK_SUM_RE</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_ACK_NUM_RE</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_SW_START</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_START</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <description>a</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CAUSE</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DECODE_STATE</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE1</name>
+          <description>a</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENCODE_STATE</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESCAPE_CONF</name>
+          <description>a</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>TX_C0_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DB_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_11_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_13_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_C0_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DB_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_11_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_13_ESC_EN</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HUNG_CONF</name>
+          <description>a</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00810810</resetValue>
+          <fields>
+            <field>
+              <name>TXFIFO_TIMEOUT</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_SHIFT</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_ENA</name>
+              <description>a</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT</name>
+              <description>a</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_SHIFT</name>
+              <description>a</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_ENA</name>
+              <description>a</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACK_NUM</name>
+          <description>a</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ACK_NUM</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_HEAD</name>
+          <description>a</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_HEAD</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUICK_SENT</name>
+          <description>a</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_SEND_NUM</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SINGLE_SEND_EN</name>
+              <description>a</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_NUM</name>
+              <description>a</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_EN</name>
+              <description>a</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q0_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q0_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q1_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q1_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q2_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q2_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q3_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q3_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q4_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q4_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q5_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q5_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q6_WORD0</name>
+          <description>a</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q6_WORD1</name>
+          <description>a</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF0</name>
+          <description>a</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DCDBC0</resetValue>
+          <fields>
+            <field>
+              <name>SEPER_CHAR</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR0</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR1</name>
+              <description>a</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF1</name>
+          <description>a</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DDDBDB</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ0</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR0</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR1</name>
+              <description>a</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF2</name>
+          <description>a</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DEDB11</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ1</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR0</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR1</name>
+              <description>a</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF3</name>
+          <description>a</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DFDB13</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ2</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR0</name>
+              <description>a</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR1</name>
+              <description>a</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_THRES</name>
+          <description>a</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>PKT_THRS</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>a</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02201100</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>a</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UHCI0">
+      <name>UHCI1</name>
+      <description>Universal Host Controller Interface</description>
+      <baseAddress>0x6000C000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>USB_DEVICE</name>
+      <description>Full-speed USB Serial/JTAG Controller</description>
+      <groupName>USB_DEVICE</groupName>
+      <baseAddress>0x60043000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x70</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB</name>
+        <value>26</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>EP1</name>
+          <description>FIFO access for the CDC-ACM data IN and OUT endpoints.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_RDWR_BYTE</name>
+              <description>Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EP1_CONF</name>
+          <description>Configuration and control registers for the CDC-ACM FIFOs.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_WR_DONE</name>
+              <description>Set this bit to indicate writing byte data to UART Tx FIFO is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE</name>
+              <description>1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL</name>
+              <description>1'b1: Indicate there is data in UART Rx FIFO.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt raw status register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when SOF frame is received.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PID_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when pid error is detected.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC5_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when CRC5 error is detected.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC16_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when CRC16 error is detected.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_STUFF_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when stuff error is detected.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when usb bus reset is detected.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS_CHG_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR_CHG_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when level of GET LINE CODING request is received.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when level of SET LINE CODING request is received.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Interrupt status register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PID_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC5_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC16_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_STUFF_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS_CHG_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR_CHG_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PID_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC5_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC16_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_STUFF_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS_CHG_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR_CHG_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear status register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PID_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC5_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_CRC16_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_STUFF_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR_CHG_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0</name>
+          <description>PHY hardware configuration.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004200</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_PHY_SEL</name>
+              <description>Select internal/external PHY</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE</name>
+              <description>Enable software control USB D+ D- exchange</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_EXCHG_PINS</name>
+              <description>USB D+ D- exchange</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_VREFH</name>
+              <description>Control single-end input high threshold,1.76V to 2V, step 80mV</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_VREFL</name>
+              <description>Control single-end input low threshold,0.8V to 1.04V, step 80mV</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_VREF_OVERRIDE</name>
+              <description>Enable software control input  threshold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PAD_PULL_OVERRIDE</name>
+              <description>Enable software control USB D+ D- pullup pulldown</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DP_PULLUP</name>
+              <description>Control USB D+ pull up.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DP_PULLDOWN</name>
+              <description>Control USB D+ pull down.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DM_PULLUP</name>
+              <description>Control USB D- pull up.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DM_PULLDOWN</name>
+              <description>Control USB D- pull down.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_PULLUP_VALUE</name>
+              <description>Control pull up value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_PAD_ENABLE</name>
+              <description>Enable USB pad function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN</name>
+              <description>Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEST</name>
+          <description>Registers used for debugging the PHY.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000030</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_ENABLE</name>
+              <description>Enable test of the USB pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_USB_OE</name>
+              <description>USB pad oen in test</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_TX_DP</name>
+              <description>USB D+ tx value in test</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_TX_DM</name>
+              <description>USB D- tx value in test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_RX_RCV</name>
+              <description>USB RCV value in test</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_RX_DP</name>
+              <description>USB D+ rx value in test</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_TEST_RX_DM</name>
+              <description>USB D- rx value in test</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JFIFO_ST</name>
+          <description>JTAG FIFO status and control registers.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000044</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_FIFO_CNT</name>
+              <description>JTAT in fifo counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_FIFO_EMPTY</name>
+              <description>1: JTAG in fifo is empty.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_FIFO_FULL</name>
+              <description>1: JTAG in fifo is full.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_FIFO_CNT</name>
+              <description>JTAT out fifo counter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_FIFO_EMPTY</name>
+              <description>1: JTAG out fifo is empty.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_FIFO_FULL</name>
+              <description>1: JTAG out fifo is full.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_FIFO_RESET</name>
+              <description>Write 1 to reset JTAG in fifo.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_FIFO_RESET</name>
+              <description>Write 1 to reset JTAG out fifo.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRAM_NUM</name>
+          <description>Last received SOF frame index register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_SOF_FRAME_INDEX</name>
+              <description>Frame index of received SOF frame.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP0_ST</name>
+          <description>Control IN endpoint status information.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP0_STATE</name>
+              <description>State of IN Endpoint 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP0_WR_ADDR</name>
+              <description>Write data address of IN endpoint 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP0_RD_ADDR</name>
+              <description>Read data address of IN endpoint 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP1_ST</name>
+          <description>CDC-ACM IN endpoint status information.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP1_STATE</name>
+              <description>State of IN Endpoint 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP1_WR_ADDR</name>
+              <description>Write data address of IN endpoint 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP1_RD_ADDR</name>
+              <description>Read data address of IN endpoint 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP2_ST</name>
+          <description>CDC-ACM interrupt IN endpoint status information.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP2_STATE</name>
+              <description>State of IN Endpoint 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP2_WR_ADDR</name>
+              <description>Write data address of IN endpoint 2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP2_RD_ADDR</name>
+              <description>Read data address of IN endpoint 2.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP3_ST</name>
+          <description>JTAG IN endpoint status information.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP3_STATE</name>
+              <description>State of IN Endpoint 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP3_WR_ADDR</name>
+              <description>Write data address of IN endpoint 3.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_IN_EP3_RD_ADDR</name>
+              <description>Read data address of IN endpoint 3.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP0_ST</name>
+          <description>Control OUT endpoint status information.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP0_STATE</name>
+              <description>State of OUT Endpoint 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP0_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP0_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP1_ST</name>
+          <description>CDC-ACM OUT endpoint status information.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_STATE</name>
+              <description>State of OUT Endpoint 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT</name>
+              <description>Data count in OUT endpoint 1 when one packet is received.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP2_ST</name>
+          <description>JTAG OUT endpoint status information.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_STATE</name>
+              <description>State of OUT Endpoint 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_OUT_EP2_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 2.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC_CONF</name>
+          <description>Clock enable control</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>Memory power control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_MEM_PD</name>
+              <description>1: power down usb memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_MEM_CLK_EN</name>
+              <description>1: Force clock on for usb memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHIP_RST</name>
+          <description>CDC-ACM chip reset control.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_RTS</name>
+              <description>1: Chip reset is detected from usb serial channel. Software write 1 to clear it.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_DTR</name>
+              <description>1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS</name>
+              <description>Set this bit to disable chip reset from usb serial channel to reset chip.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_LINE_CODE_W0</name>
+          <description>W0 of SET_LINE_CODING command.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_DW_DTE_RATE</name>
+              <description>The value of dwDTERate set by host through SET_LINE_CODING command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_LINE_CODE_W1</name>
+          <description>W1 of SET_LINE_CODING command.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_BCHAR_FORMAT</name>
+              <description>The value of bCharFormat set by host through SET_LINE_CODING command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_BPARITY_TYPE</name>
+              <description>The value of bParityTpye set by host through SET_LINE_CODING command.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_BDATA_BITS</name>
+              <description>The value of bDataBits set by host through SET_LINE_CODING command.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GET_LINE_CODE_W0</name>
+          <description>W0 of GET_LINE_CODING command.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_DW_DTE_RATE</name>
+              <description>The value of dwDTERate set by software which is requested by GET_LINE_CODING command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GET_LINE_CODE_W1</name>
+          <description>W1 of GET_LINE_CODING command.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_BDATA_BITS</name>
+              <description>The value of bCharFormat set by software which is requested by GET_LINE_CODING command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_BPARITY_TYPE</name>
+              <description>The value of bParityTpye set by software which is requested by GET_LINE_CODING command.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_GET_BCHAR_FORMAT</name>
+              <description>The value of bDataBits set by software which is requested by GET_LINE_CODING command.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONFIG_UPDATE</name>
+          <description>Configuration registers' value update</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_CONFIG_UPDATE</name>
+              <description>Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SER_AFIFO_CONFIG</name>
+          <description>Serial AFIFO configure register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR</name>
+              <description>Write 1 to reset CDC_ACM IN async FIFO write clock domain.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD</name>
+              <description>Write 1 to reset CDC_ACM IN async FIFO read clock domain.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR</name>
+              <description>Write 1 to reset CDC_ACM OUT async FIFO write clock domain.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD</name>
+              <description>Write 1 to reset CDC_ACM OUT async FIFO read clock domain.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY</name>
+              <description>CDC_ACM OUTOUT async FIFO empty signal in read clock domain.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL</name>
+              <description>CDC_ACM OUT IN async FIFO empty signal in write clock domain.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_RESET_ST</name>
+          <description>USB Bus reset status register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_USB_BUS_RESET_ST</name>
+              <description>USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02109220</resetValue>
+          <fields>
+            <field>
+              <name>USB_SERIAL_JTAG_DATE</name>
+              <description>register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/tools/ide-debug/svd/esp32s2.svd b/tools/ide-debug/svd/esp32s2.svd
new file mode 100644
index 00000000000..e3a9efba868
--- /dev/null
+++ b/tools/ide-debug/svd/esp32s2.svd
@@ -0,0 +1,45743 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+  <vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
+  <vendorID>ESPRESSIF</vendorID>
+  <name>ESP32-S2</name>
+  <series>ESP32-S2</series>
+  <version>11</version>
+  <description>32-bit MCU &amp; 2.4 GHz Wi-Fi</description>
+  <licenseText>
+    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+</licenseText>
+  <cpu>
+    <name>Xtensa LX7</name>
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>false</fpuPresent>
+    <nvicPrioBits>3</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>32</addressUnitBits>
+  <width>32</width>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AES</name>
+      <description>AES (Advanced Encryption Standard) Accelerator</description>
+      <groupName>AES</groupName>
+      <baseAddress>0x6003A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xBC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AES</name>
+        <value>56</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>KEY_%s</name>
+          <description>AES key register %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_0</name>
+              <description>Stores AES keys.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TEXT_IN_%s</name>
+          <description>Source data register %s</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_0</name>
+              <description>Stores the source data when the AES Accelerator operates in the Typical AES working mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TEXT_OUT_%s</name>
+          <description>Result data register %s</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_0</name>
+              <description>Stores the result data when the AES Accelerator operates in the Typical AES working mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>AES working mode configuration register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Defines the operation type of the AES Accelerator operating under the Typical AES working mode.
+&amp;
+0x0(AES_EN_128): AES-EN-128 #
+0x1(AES_EN_192): AES-EN-192 #
+0x2(AES_EN_256): AES-EN-256 #
+0x4(AES_DE_128): AES-DE-128 #
+0x5(AES_DE_192): AES-DE-192 #
+0x6(AES_DE_256): AES-DE-256
+&amp;</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENDIAN</name>
+          <description>Endian configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENDIAN</name>
+              <description>Defines the endianness of input and output texts.
+&amp;
+[1:0] key endian #
+[3:2] text_in endian or in_stream endian #
+[5:4] text_out endian or out_stream endian #
+&amp;</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>Operation start controlling register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRIGGER</name>
+              <description>Set this bit to 1 to start AES operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>Operation status register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Stores the working status of the AES Accelerator. For details, see Table 3 for Typical AES working mode and Table 9 for DMA AES working mode.
+For typical AES; 0 = idle; 1 = busy.
+For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>IV_%s</name>
+          <description>initialization vector</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IV_0</name>
+              <description>This register stores the %sth 32-bit piece of 128-bit initialization vector</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>H_%s</name>
+          <description>GCM hash subkey</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_0</name>
+              <description>GCM hash subkey</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>J0_%s</name>
+          <description>J0</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>J0_0</name>
+              <description>This register stores the %sth 32-bit piece of 128-bit J0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>T0_%s</name>
+          <description>T0</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_0</name>
+              <description>This register stores the %sth 32-bit piece of 128-bit T0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_ENABLE</name>
+          <description>DMA enable register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_ENABLE</name>
+              <description>Defines the working mode of the AES Accelerator. For details, see Table 1.
+1'h0: typical AES operation
+1'h1: DMA-AES operation</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_MODE</name>
+          <description>Block operation type register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_MODE</name>
+              <description>Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8.
+&amp;
+3'h0(BLOCK_MODE_ECB): ECB #
+3'h1(BLOCK_MODE_CBC): CBC #
+3'h2(BLOCK_MODE_OFB): OFB #
+3'h3(BLOCK_MODE_CTR): CTR #
+3'h4(BLOCK_MODE_CFB8): CFB-8 #
+3'h5(BLOCK_MODE_CFB128): CFB-128 #
+3'h6(BLOCK_MODE_GCM): GCM
+&amp;</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_NUM</name>
+          <description>Block number configuration register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_NUM</name>
+              <description>Stores the Block Number of plaintext or cipertext when the AES Accelerator operates under the DMA-AES working mode. For details, see Section 1.5.4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INC_SEL</name>
+          <description>Standard incrementing function register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INC_SEL</name>
+              <description>Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC 32 or INC 128 .</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AAD_BLOCK_NUM</name>
+          <description>AAD block number configuration register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AAD_BLOCK_NUM</name>
+              <description>Stores the ADD Block Number for the GCM operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REMAINDER_BIT_NUM</name>
+          <description>Remainder bit number of plaintext/ciphertext</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REMAINDER_BIT_NUM</name>
+              <description>Stores the Remainder Bit Number for the GCM operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE_OP</name>
+          <description>Operation continue controlling register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE_OP</name>
+              <description>Set this bit to 1 to continue AES operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>DMA-AES interrupt clear register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_CLR</name>
+              <description>Set this bit to 1 to clear AES interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>DMA-AES interrupt enable register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_ENA</name>
+              <description>Set this bit to 1 to enable AES interrupt and 0 to disable interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20190514</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_EXIT</name>
+          <description>Operation exit controlling register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_EXIT</name>
+              <description>Set this bit to 1 to exit AES operation. This register is only effective for DMA-AES operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>APB_SARADC</name>
+      <description>Successive Approximation Register Analog to Digital Converter</description>
+      <groupName>APB_SARADC</groupName>
+      <baseAddress>0x3F440000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>APB_ADC</name>
+        <value>89</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>DIG ADC common configuration</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x407F8240</resetValue>
+          <fields>
+            <field>
+              <name>START_FORCE</name>
+              <description>0: select FSM to start SAR ADC. 1: select software to start SAR ADC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>Start SAR ADC by software.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WORK_MODE</name>
+              <description>0: single-channel scan mode. 1: double-channel scan mode. 2:
+alternate-channel scan mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SEL</name>
+              <description>0: select SAR ADC1. 1: select SAR ADC2, only work for single-channel scan mode.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_CLK_GATED</name>
+              <description>SAR clock gate enable bit.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_CLK_DIV</name>
+              <description>SAR clock divider</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_PATT_P_CLEAR</name>
+              <description>Clear the pointer of pattern table for DIG ADC1 CTRL.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_PATT_P_CLEAR</name>
+              <description>Clear the pointer of pattern table for DIG ADC2 CTRL.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_SAR_SEL</name>
+              <description>1: sar_sel will be coded to the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_TO_I2S</name>
+              <description>1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SAR_FORCE</name>
+              <description>Force option to xpd sar blocks.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_ARB_CYCLE</name>
+              <description>Wait arbit signal stable after sar_done.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>DIG ADC common configuration</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000A1FE</resetValue>
+          <fields>
+            <field>
+              <name>MEAS_NUM_LIMIT</name>
+              <description>Enable limit times of SAR ADC sample.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAX_MEAS_NUM</name>
+              <description>Set maximum conversion number.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_INV</name>
+              <description>1: data to DIG ADC1 CTRL is inverted, otherwise not.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_INV</name>
+              <description>1: data to DIG ADC2 CTRL is inverted, otherwise not.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_SEL</name>
+              <description>1: select saradc timer 0: i2s_ws trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_TARGET</name>
+              <description>Set SAR ADC timer target.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_EN</name>
+              <description>Enable SAR ADC timer trigger.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM</name>
+          <description>digital adc control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02000000</resetValue>
+          <fields>
+            <field>
+              <name>SAMPLE_NUM</name>
+              <description>sample number</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAMPLE_CYCLE</name>
+              <description>sample cycles</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_WAIT</name>
+          <description>configure saradc fsm internal parameter base on test</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FF0808</resetValue>
+          <fields>
+            <field>
+              <name>XPD_WAIT</name>
+              <description>xpd wait</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSTB_WAIT</name>
+              <description>reset time</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STANDBY_WAIT</name>
+              <description>standby wait</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_STATUS</name>
+          <description>digital adc1 status</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR1_STATUS</name>
+              <description>digital adc1 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_STATUS</name>
+          <description>digital adc2 status</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR2_STATUS</name>
+              <description>digital adc2 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_PATT_TAB1</name>
+          <description>item 0 ~ 3 for pattern table 1 (each item one byte)</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_PATT_TAB2</name>
+          <description>Item 4 ~ 7 for pattern table 1 (each item one byte)</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_PATT_TAB3</name>
+          <description>Item 8 ~ 11 for pattern table 1 (each item one byte)</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_PATT_TAB3</name>
+              <description>Item 8 ~ 11 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_PATT_TAB4</name>
+          <description>Item 12 ~ 15 for pattern table 1 (each item one byte)</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_PATT_TAB4</name>
+              <description>Item 12 ~ 15 for pattern table 1 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_PATT_TAB1</name>
+          <description>item 0 ~ 3 for pattern table 2 (each item one byte)</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SAR2_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 2 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_PATT_TAB2</name>
+          <description>Item 4 ~ 7 for pattern table 2 (each item one byte)</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SAR2_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 2 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_PATT_TAB3</name>
+          <description>Item 8 ~ 11 for pattern table 2 (each item one byte)</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SAR2_PATT_TAB3</name>
+              <description>Item 8 ~ 11 for pattern table 2 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_PATT_TAB4</name>
+          <description>Item 12 ~ 15 for pattern table 2 (each item one byte)</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F0F0F0F</resetValue>
+          <fields>
+            <field>
+              <name>SAR2_PATT_TAB4</name>
+              <description>Item 12 ~ 15 for pattern table 2 (each item one byte)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_CTRL</name>
+          <description>Configure the settings of DIG ADC2 arbiter</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000900</resetValue>
+          <fields>
+            <field>
+              <name>ADC_ARB_APB_FORCE</name>
+              <description>ADC2 arbiter forces to enable DIG ADC2 CTRL.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_FORCE</name>
+              <description>ADC2 arbiter forces to enable RTC ADC2 CTRL.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_FORCE</name>
+              <description>ADC2 arbiter forces to enable PWDET/PKDET CTRL.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_GRANT_FORCE</name>
+              <description>ADC2 arbiter force grant.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_APB_PRIORITY</name>
+              <description>Set DIG ADC2 CTRL priority.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_PRIORITY</name>
+              <description>Set RTC ADC2 CTRL priority.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_PRIORITY</name>
+              <description>Set PWDET/PKDET CTRL priority.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_FIX_PRIORITY</name>
+              <description>ADC2 arbiter uses fixed priority.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL</name>
+          <description>Configure the settings of DIG ADC2 filter</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20400000</resetValue>
+          <fields>
+            <field>
+              <name>ADC2_FILTER_RESET</name>
+              <description>Reset ADC2 filter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_FILTER_RESET</name>
+              <description>Reset ADC1 filter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_FILTER_FACTOR</name>
+              <description>Set filter factor for DIG ADC2 CRTL.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_FILTER_FACTOR</name>
+              <description>Set filter factor for DIG ADC1 CRTL.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_FILTER_EN</name>
+              <description>Enable DIG ADC2 CRTL filter.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_FILTER_EN</name>
+              <description>Enable DIG ADC1 CRTL filter.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_STATUS</name>
+          <description>Data status of DIG ADC2 filter</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC2_FILTER_DATA</name>
+              <description>ADC2 filter data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADC1_FILTER_DATA</name>
+              <description>ADC1 filter data.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES_CTRL</name>
+          <description>Configure monitor threshold for DIG ADC2</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Clock gate enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_THRES_MODE</name>
+              <description>1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_THRES_MODE</name>
+              <description>1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA &lt; threshold, generate interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_THRES</name>
+              <description>ADC2 threshold.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_THRES</name>
+              <description>ADC1 threshold.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_THRES_EN</name>
+              <description>Enable ADC2 threshold monitor.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_THRES_EN</name>
+              <description>Enable ADC1 threshold monitor.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Enable DIG ADC interrupts</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC2_THRES_INT_ENA</name>
+              <description>Enable bit of APB_SARADC_ADC2_THRES_INT interrupt.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_THRES_INT_ENA</name>
+              <description>Enable bit of APB_SARADC_ADC1_THRES_INT interrupt.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_DONE_INT_ENA</name>
+              <description>Enable bit of APB_SARADC_ADC2_DONE_INT interrupt.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC1_DONE_INT_ENA</name>
+              <description>Enable bit of APB_SARADC_ADC1_DONE_INT interrupt.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>DIG ADC interrupt raw bits</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC2_THRES_INT_RAW</name>
+              <description>Raw bit of APB_SARADC_ADC2_THRES_INT interrupt.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADC1_THRES_INT_RAW</name>
+              <description>Raw bit of APB_SARADC_ADC1_THRES_INT interrupt.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADC2_DONE_INT_RAW</name>
+              <description>Raw bit of APB_SARADC_ADC2_DONE_INT interrupt.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADC1_DONE_INT_RAW</name>
+              <description>Raw bit of APB_SARADC_ADC1_DONE_INT interrupt.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>DIG ADC interrupt status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC2_THRES_INT_ST</name>
+              <description>Status of APB_SARADC_ADC2_THRES_INT interrupt.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADC1_THRES_INT_ST</name>
+              <description>Status of APB_SARADC_ADC1_THRES_INT interrupt.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADC2_DONE_INT_ST</name>
+              <description>Status of APB_SARADC_ADC2_DONE_INT interrupt.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADC1_DONE_INT_ST</name>
+              <description>Status of APB_SARADC_ADC1_DONE_INT interrupt.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Clear DIG ADC interrupts</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ADC2_THRES_INT_CLR</name>
+              <description>Clear bit of APB_SARADC_ADC2_THRES_INT interrupt.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ADC1_THRES_INT_CLR</name>
+              <description>Clear bit of APB_SARADC_ADC1_THRES_INT interrupt.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ADC2_DONE_INT_CLR</name>
+              <description>Clear bit of APB_SARADC_ADC2_DONE_INT interrupt.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ADC1_DONE_INT_CLR</name>
+              <description>Clear bit of APB_SARADC_ADC1_DONE_INT interrupt.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>Configure digital ADC DMA path</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>APB_ADC_EOF_NUM</name>
+              <description>Generate dma_in_suc_eof when sample cnt = spi_eof_num.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_RESET_FSM</name>
+              <description>Reset DIG ADC CTRL status.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_TRANS</name>
+              <description>Set this bit, DIG ADC CTRL uses SPI DMA.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKM_CONF</name>
+          <description>Configure DIG ADC clock</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>CLKM_DIV_NUM</name>
+              <description>Integral DIG_ADC clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_B</name>
+              <description>Fractional clock divider numerator value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_A</name>
+              <description>Fractional clock divider denominator value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_SEL</name>
+              <description>1: select APLL. 2: select APB_CLK. Other values: disable clock.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_DAC_CTRL</name>
+          <description>Configure DAC settings</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002064</resetValue>
+          <fields>
+            <field>
+              <name>DAC_TIMER_TARGET</name>
+              <description>Set DAC timer target.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_TIMER_EN</name>
+              <description>Enable read dac data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_DAC_ALTER_MODE</name>
+              <description>Enable DAC alter mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_DAC_TRANS</name>
+              <description>Enable DMA_DAC.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_RESET_FIFO</name>
+              <description>Reset DIG DAC FIFO.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_DAC_RST</name>
+              <description>Reset DIG DAC by software.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_CTRL_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01907162</resetValue>
+          <fields>
+            <field>
+              <name>APB_CTRL_DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DEDICATED_GPIO</name>
+      <description>Dedicated GPIO</description>
+      <groupName>DEDIC_GPIO</groupName>
+      <baseAddress>0x3F4CF000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x30</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DEDICATED_GPIO</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>OUT_DRT</name>
+          <description>Dedicated GPIO directive output register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>VLAUE</name>
+              <description>This register is used to configure directive output value of 8-channel dedicated GPIO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_MSK</name>
+          <description>Dedicated GPIO mask output register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_VALUE</name>
+              <description>This register is used to configure updated output value of 8-channel dedicated GPIO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_MSK</name>
+              <description>This register is used to configure channels which would be updated. 1: corresponding channel's output would be updated.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_IDV</name>
+          <description>Dedicated GPIO individual output register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0</name>
+              <description>Configure channel 0 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH1</name>
+              <description>Configure channel 1 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH2</name>
+              <description>Configure channel 2 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH3</name>
+              <description>Configure channel 3 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH4</name>
+              <description>Configure channel 4 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH5</name>
+              <description>Configure channel 5 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH6</name>
+              <description>Configure channel 6 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH7</name>
+              <description>Configure channel 7 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_SCAN</name>
+          <description>Dedicated GPIO output status register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_STATUS</name>
+              <description>GPIO out value configured by DEDIC_GPIO_OUT_DRT_REG, DEDIC_GPIO_OUT_MSK_REG, DEDIC_GPIO_OUT_IDV_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_CPU</name>
+          <description>Dedicated GPIO output mode selection register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL0</name>
+              <description>Select GPIO out value configured by registers or CPU instructions for channel 0. 0: Configured by registers. 1: configured by CPU instructions.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL1</name>
+              <description>Select GPIO out value configured by registers or CPU instructions for channel 1. 0: Configured by registers. 1: configured by CPU instructions.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL2</name>
+              <description>Select GPIO out value configured by registers or CPU instructions for channel 2. 0: Configured by registers. 1: configured by CPU instructions.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL3</name>
+              <description>Select GPIO out value configured by registers or CPU instructions for channel 3. 0: Configured by registers. 1: configured by CPU instructions.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL4</name>
+              <description>Select GPIO out value configured by registers or CPU instructions for channel 4. 0: Configured by registers. 1: configured by CPU instructions.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL5</name>
+              <description>Select GPIO out value configured by registers or CPU instructions for channel 5. 0: Configured by registers. 1: configured by CPU instructions.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL6</name>
+              <description>Select GPIO out value configured by registers or CPU instructions for channel 6. 0: Configured by registers. 1: configured by CPU instructions.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL7</name>
+              <description>Select GPIO out value configured by registers or CPU instructions for channel 7. 0: Configured by registers. 1: configured by CPU instructions.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_DLY</name>
+          <description>Dedicated GPIO input delay configuration register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0</name>
+              <description>Configure GPIO0 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1</name>
+              <description>Configure GPIO1 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2</name>
+              <description>Configure GPIO2 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3</name>
+              <description>Configure GPIO3 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH4</name>
+              <description>Configure GPIO4 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH5</name>
+              <description>Configure GPIO5 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH6</name>
+              <description>Configure GPIO6 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH7</name>
+              <description>Configure GPIO7 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_SCAN</name>
+          <description>Dedicated GPIO input status register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_STATUS</name>
+              <description>GPIO input value after configured by DEDIC_GPIO_IN_DLY_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_RCGN</name>
+          <description>Dedicated GPIO interrupts generation mode register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_MODE_CH0</name>
+              <description>Configure channel 0 interrupt generate mode.
+0/1: do not generate interrupt.
+2: low level trigger.
+3: high level trigger.
+4: falling edge trigger.
+5: raising edge trigger.
+6/7: falling and raising edge trigger.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTR_MODE_CH1</name>
+              <description>Configure channel 1 interrupt generate mode.
+0/1: do not generate interrupt.
+2: low level trigger.
+3: high level trigger.
+4: falling edge trigger.
+5: raising edge trigger.
+6/7: falling and raising edge trigger.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTR_MODE_CH2</name>
+              <description>Configure channel 2 interrupt generate mode.
+0/1: do not generate interrupt.
+2: low level trigger.
+3: high level trigger.
+4: falling edge trigger.
+5: raising edge trigger.
+6/7: falling and raising edge trigger.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTR_MODE_CH3</name>
+              <description>Configure channel 3 interrupt generate mode.
+0/1: do not generate interrupt.
+2: low level trigger.
+3: high level trigger.
+4: falling edge trigger.
+5: raising edge trigger.
+6/7: falling and raising edge trigger.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTR_MODE_CH4</name>
+              <description>Configure channel 4 interrupt generate mode.
+0/1: do not generate interrupt.
+2: low level trigger.
+3: high level trigger.
+4: falling edge trigger.
+5: raising edge trigger.
+6/7: falling and raising edge trigger.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTR_MODE_CH5</name>
+              <description>Configure channel 5 interrupt generate mode.
+0/1: do not generate interrupt.
+2: low level trigger.
+3: high level trigger.
+4: falling edge trigger.
+5: raising edge trigger.
+6/7: falling and raising edge trigger.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTR_MODE_CH6</name>
+              <description>Configure channel 6 interrupt generate mode.
+0/1: do not generate interrupt.
+2: low level trigger.
+3: high level trigger.
+4: falling edge trigger.
+5: raising edge trigger.
+6/7: falling and raising edge trigger.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTR_MODE_CH7</name>
+              <description>Configure channel 7 interrupt generate mode.
+0/1: do not generate interrupt.
+2: low level trigger.
+3: high level trigger.
+4: falling edge trigger.
+5: raising edge trigger.
+6/7: falling and raising edge trigger.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO0</name>
+              <description>This interrupt raw bit turns to high level when dedicated GPIO0 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO1</name>
+              <description>This interrupt raw bit turns to high level when dedicated GPIO1 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO2</name>
+              <description>This interrupt raw bit turns to high level when dedicated GPIO2 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO3</name>
+              <description>This interrupt raw bit turns to high level when dedicated GPIO3 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO4</name>
+              <description>This interrupt raw bit turns to high level when dedicated GPIO4 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO5</name>
+              <description>This interrupt raw bit turns to high level when dedicated GPIO5 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO6</name>
+              <description>This interrupt raw bit turns to high level when dedicated GPIO6 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO7</name>
+              <description>This interrupt raw bit turns to high level when dedicated GPIO7 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_RLS</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO0_INT_ENA</name>
+              <description>The enable bit for DEDIC_GPIO0_INT_ST register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO1_INT_ENA</name>
+              <description>The enable bit for DEDIC_GPIO1_INT_ST register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO2_INT_ENA</name>
+              <description>The enable bit for DEDIC_GPIO2_INT_ST register.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO3_INT_ENA</name>
+              <description>The enable bit for DEDIC_GPIO3_INT_ST register.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO4_INT_ENA</name>
+              <description>The enable bit for DEDIC_GPIO4_INT_ST register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO5_INT_ENA</name>
+              <description>The enable bit for DEDIC_GPIO5_INT_ST register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO6_INT_ENA</name>
+              <description>The enable bit for DEDIC_GPIO6_INT_ST register.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO7_INT_ENA</name>
+              <description>The enable bit for DEDIC_GPIO7_INT_ST register.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO0_INT_ST</name>
+              <description>This is the status bit for DEDIC_GPIO0_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO1_INT_ST</name>
+              <description>This is the status bit for DEDIC_GPIO1_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO2_INT_ST</name>
+              <description>This is the status bit for DEDIC_GPIO2_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO3_INT_ST</name>
+              <description>This is the status bit for DEDIC_GPIO3_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO4_INT_ST</name>
+              <description>This is the status bit for DEDIC_GPIO4_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO5_INT_ST</name>
+              <description>This is the status bit for DEDIC_GPIO5_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO6_INT_ST</name>
+              <description>This is the status bit for DEDIC_GPIO6_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GPIO7_INT_ST</name>
+              <description>This is the status bit for DEDIC_GPIO7_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTR_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO0_INT_CLR</name>
+              <description>Set this bit to clear the DEDIC_GPIO0_INT_RAW interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPIO1_INT_CLR</name>
+              <description>Set this bit to clear the DEDIC_GPIO1_INT_RAW interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPIO2_INT_CLR</name>
+              <description>Set this bit to clear the DEDIC_GPIO2_INT_RAW interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPIO3_INT_CLR</name>
+              <description>Set this bit to clear the DEDIC_GPIO3_INT_RAW interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPIO4_INT_CLR</name>
+              <description>Set this bit to clear the DEDIC_GPIO4_INT_RAW interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPIO5_INT_CLR</name>
+              <description>Set this bit to clear the DEDIC_GPIO5_INT_RAW interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPIO6_INT_CLR</name>
+              <description>Set this bit to clear the DEDIC_GPIO6_INT_RAW interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GPIO7_INT_CLR</name>
+              <description>Set this bit to clear the DEDIC_GPIO7_INT_RAW interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DS</name>
+      <description>Digital Signature</description>
+      <groupName>DS</groupName>
+      <baseAddress>0x6003D000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA5C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>1584</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>C_MEM[%s]</name>
+          <description>memory C</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>IV_%s</name>
+          <description>IV block data.</description>
+          <addressOffset>0x630</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IV_0</name>
+              <description>IV block data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>X_MEM[%s]</name>
+          <description>memory X</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Z_MEM[%s]</name>
+          <description>memory Z</description>
+          <addressOffset>0xA00</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>SET_START</name>
+          <description>Activates the DS peripheral</description>
+          <addressOffset>0xE00</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>Write 1 to this register to activate the DS peripheral.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_ME</name>
+          <description>Starts DS operation</description>
+          <addressOffset>0xE04</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_ME</name>
+              <description>Write 1 to this register to start DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_FINISH</name>
+          <description>Ends DS operation</description>
+          <addressOffset>0xE08</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_FINISH</name>
+              <description>Write 1 to this register to end DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>Status of the DS</description>
+          <addressOffset>0xE0C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_BUSY</name>
+              <description>1: The DS peripheral is busy. 0: The DS peripheral is idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_KEY_WRONG</name>
+          <description>Checks the reason why DS_KEY is not ready.</description>
+          <addressOffset>0xE10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_KEY_WRONG</name>
+              <description>1-15: HMAC was activated, but the DS peripheral did not successfully receive the DS_KEY value from the HMAC peripheral. The biggest value is 15. 0: HMAC is not activated.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_CHECK</name>
+          <description>Queries DS check result</description>
+          <addressOffset>0xE14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MD_ERROR</name>
+              <description>1: MD check fails. 0: MD check passes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PADDING_BAD</name>
+              <description>1: The padding check fails. 0: The padding check passes.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xE20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20190418</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EFUSE</name>
+      <description>eFuse Controller</description>
+      <groupName>EFUSE</groupName>
+      <baseAddress>0x3F41A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1D0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EFUSE</name>
+        <value>46</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>PGM_DATA%s</name>
+          <description>Register %s that stores data to be programmed.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_0</name>
+              <description>The content of the %sth 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>3</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>PGM_CHECK_VALUE%s</name>
+          <description>Register %s that stores the RS code to be programmed.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_0</name>
+              <description>The content of the %sth 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_WR_DIS</name>
+          <description>Register 0 of BLOCK0.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_DIS</name>
+              <description>Disables programming of individual eFuses.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA0</name>
+          <description>Register 1 of BLOCK0.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS</name>
+              <description>Disables software reading from individual eFuse blocks (BLOCK4-10).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_RTC_RAM_BOOT</name>
+              <description>Reserved.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE</name>
+              <description>Set this bit to disable Icache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DCACHE</name>
+              <description>Set this bit to disable Dcache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE</name>
+              <description>Disables Icache when SoC is in Download mode.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_DCACHE</name>
+              <description>Disables Dcache when SoC is in Download mode.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD</name>
+              <description>Set this bit to disable the function that forces chip into download mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB</name>
+              <description>Set this bit to disable USB OTG function.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_CAN</name>
+              <description>Set this bit to disable the TWAI Controller function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_BOOT_REMAP</name>
+              <description>Disables capability to Remap RAM to ROM address space.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED5</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG</name>
+              <description>Software disables JTAG. When software disabled, JTAG can be activated temporarily by HMAC peripheral.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HARD_DIS_JTAG</name>
+              <description>Hardware disables JTAG permanently.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>Disables flash encryption when in download boot modes.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH</name>
+              <description>Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL</name>
+              <description>Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS</name>
+              <description>Set this bit to exchange USB D+ and D- pins.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EXT_PHY_ENABLE</name>
+              <description>Set this bit to enable external USB PHY.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_FORCE_NOPERSIST</name>
+              <description>If set, forces USB BVALID to 1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_MODECURLIM</name>
+              <description>SPI regulator switches current limit mode.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DREFH</name>
+              <description>SPI regulator high voltage reference.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA1</name>
+          <description>Register 2 of BLOCK0.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>VDD_SPI_DREFM</name>
+              <description>SPI regulator medium voltage reference.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DREFL</name>
+              <description>SPI regulator low voltage reference.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_XPD</name>
+              <description>If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_TIEH</name>
+              <description>If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V LDO. 1: VDD_SPI connects to VDD_RTC_IO.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_FORCE</name>
+              <description>Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_EN_INIT</name>
+              <description>Set SPI regulator to 0 to configure init[1:0]=0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_ENCURLIM</name>
+              <description>Set SPI regulator to 1 to enable output current limit.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DCURLIM</name>
+              <description>Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_INIT</name>
+              <description>Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DCAP</name>
+              <description>Prevents SPI regulator from overshoot.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL</name>
+              <description>Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock cycles.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT</name>
+              <description>Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled 1 or 3 bits are set in the eFuse, disabled otherwise.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0</name>
+              <description>If set, revokes use of secure boot key digest 0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1</name>
+              <description>If set, revokes use of secure boot key digest 1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2</name>
+              <description>If set, revokes use of secure boot key digest 2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0</name>
+              <description>Purpose of KEY0. Refer to Table Key Purpose Values.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1</name>
+              <description>Purpose of KEY1. Refer to Table Key Purpose Values.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA2</name>
+          <description>Register 3 of BLOCK0.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2</name>
+              <description>Purpose of KEY2. Refer to Table Key Purpose Values.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3</name>
+              <description>Purpose of KEY3. Refer to Table Key Purpose Values.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4</name>
+              <description>Purpose of KEY4. Refer to Table Key Purpose Values.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5</name>
+              <description>Purpose of KEY5. Refer to Table Key Purpose Values.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_6</name>
+              <description>Purpose of KEY6. Refer to Table Key Purpose Values.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN</name>
+              <description>Set this bit to enable secure boot.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE</name>
+              <description>Set this bit to enable aggressive secure boot key revocation mode.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED1</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW</name>
+              <description>Configures flash startup delay after SoC power-up, in unit of (ms/2). When the value is 15, delay is 7.5 ms.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA3</name>
+          <description>Register 4 of BLOCK0.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE</name>
+              <description>Set this bit to disable all download boot modes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_LEGACY_SPI_BOOT</name>
+              <description>Set this bit to disable Legacy SPI boot mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CHANNEL</name>
+              <description>Selects the default UART for printing boot messages. 0: UART0. 1: UART1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DOWNLOAD_MODE</name>
+              <description>Set this bit to disable use of USB OTG in UART download boot mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD</name>
+              <description>Set this bit to enable secure UART download mode (read/write flash only).</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL</name>
+              <description>Set the default UART boot message output mode. 00: Enabled. 01: Enable when GPIO46 is low at reset. 10: Enable when GPIO46 is high at reset. 11: Disabled.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIN_POWER_SELECTION</name>
+              <description>Set default power supply for GPIO33-GPIO37, set when SPI flash is initialized. 0: VDD3P3_CPU. 1: VDD_SPI.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TYPE</name>
+              <description>SPI flash type. 0: maximum four data lines, 1: eight data lines.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME</name>
+              <description>If set, forces ROM code to send an SPI flash resume command during SPI boot.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION</name>
+              <description>Secure version (used by ESP-IDF anti-rollback feature).</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED2</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA4</name>
+          <description>Register 5 of BLOCK0.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED4</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_0</name>
+          <description>Register 0 of BLOCK1.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_0</name>
+              <description>Stores the low 32 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_1</name>
+          <description>Register 1 of BLOCK1.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_1</name>
+              <description>Stores the high 16 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_PAD_CONF_0</name>
+              <description>Stores the zeroth part of SPI_PAD_CONF.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_2</name>
+          <description>Register 2 of BLOCK1.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_PAD_CONF_1</name>
+              <description>Stores the first part of SPI_PAD_CONF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_3</name>
+          <description>Register 3 of BLOCK1.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_PAD_CONF_2</name>
+              <description>Stores the second part of SPI_PAD_CONF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_DATA_PART0_0</name>
+              <description>Stores the zeroth part  of the zeroth part of system data.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_4</name>
+          <description>Register 4 of BLOCK1.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_1</name>
+              <description>Stores the fist part of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_5</name>
+          <description>Register 5 of BLOCK1.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_2</name>
+              <description>Stores the second part of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_SYS_DATA_PART1_%s</name>
+          <description>Register %s of BLOCK2 (system).</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_0</name>
+              <description>Stores the %sth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_USR_DATA%s</name>
+          <description>Register %s of BLOCK3 (user).</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA0</name>
+              <description>Stores the %sth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_KEY0_DATA%s</name>
+          <description>Register %s of BLOCK4 (KEY0).</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA0</name>
+              <description>Stores the %sth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_KEY1_DATA%s</name>
+          <description>Register %s of BLOCK5 (KEY1).</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA0</name>
+              <description>Stores the %sth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_KEY2_DATA%s</name>
+          <description>Register %s of BLOCK6 (KEY2).</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA0</name>
+              <description>Stores the %sth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_KEY3_DATA%s</name>
+          <description>Register %s of BLOCK7 (KEY3).</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA0</name>
+              <description>Stores the %sth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_KEY4_DATA%s</name>
+          <description>Register %s of BLOCK8 (KEY4).</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA0</name>
+              <description>Stores the %sth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_KEY5_DATA%s</name>
+          <description>Register %s of BLOCK9 (KEY5).</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA0</name>
+              <description>Stores the %sth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_SYS_DATA_PART2_%s</name>
+          <description>Register %s of BLOCK10 (system).</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_0</name>
+              <description>Stores the %sth 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR0</name>
+          <description>Programming error record register 0 of BLOCK0.</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_RD_DIS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_RTC_RAM_BOOT_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_RTC_RAM_BOOT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_ICACHE.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DCACHE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_DCACHE.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_ICACHE.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_DCACHE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_DCACHE.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_FORCE_DOWNLOAD.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_CAN_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_CAN.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_BOOT_REMAP_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_BOOT_REMAP.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED5_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED5.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_SOFT_DIS_JTAG.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HARD_DIS_JTAG_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_HARD_DIS_JTAG.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFH.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFL.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_USB_EXCHG_PINS.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EXT_PHY_ENABLE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_EXT_PHY_ENABLE.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_FORCE_NOPERSIST_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_USB_FORCE_NOPERSIST.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED0.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_MODECURLIM_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_MODECURLIM.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DREFH_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFH.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR1</name>
+          <description>Programming error record register 1 of BLOCK0.</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>VDD_SPI_DREFM_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DREFL_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFL.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_XPD_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_XPD.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_TIEH_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_TIEH.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_FORCE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_FORCE.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_EN_INIT_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_EN_INIT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_ENCURLIM_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_ENCURLIM.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DCURLIM_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCURLIM.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_INIT_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_INIT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DCAP_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCAP.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_WDT_DELAY_SEL.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_SPI_BOOT_CRYPT_CNT.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR2</name>
+          <description>Programming error record register 2 of BLOCK0.</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_3.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_4.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_5.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_6_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_6.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_EN.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED1_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TPUW.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR3</name>
+          <description>Programming error record register 3 of BLOCK0.</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MODE.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_LEGACY_SPI_BOOT_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_LEGACY_SPI_BOOT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CHANNEL_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CHANNEL.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED3_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED3.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DOWNLOAD_MODE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB_DOWNLOAD_MODE.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_ENABLE_SECURITY_DOWNLOAD.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CONTROL.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIN_POWER_SELECTION_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_PIN_POWER_SELECTION.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TYPE_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TYPE.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_FORCE_SEND_RESUME.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_SECURE_VERSION.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED2_ERR</name>
+              <description>Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED2.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR4</name>
+          <description>Programming error record register 4 of BLOCK0.</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED4_ERR</name>
+              <description>If any bit in RPT4_RESERVED4 is 1, there is a programming error in EFUSE_RPT4_RESERVED4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR0</name>
+          <description>Programming error record register 0 of BLOCK1-10.</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_SPI_8M_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in BLOCK1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAC_SPI_8M_FAIL</name>
+              <description>0: Means no failure and that the data of BLOCK1 is reliable. 1: Means that programming BLOCK1 data failed and the number of error bytes is over 5.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_NUM</name>
+              <description>The value of this signal means the number of error bytes in BLOCK2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_FAIL</name>
+              <description>0: Means no failure and that the data of BLOCK2 is reliable. 1: Means that programming BLOCK2 data failed and the number of error bytes is over 5.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in BLOCK3.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_FAIL</name>
+              <description>0: Means no failure and that the data of BLOCK3 is reliable. 1: Means that programming BLOCK3 data failed and the number of error bytes is over 5.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in KEY0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_FAIL</name>
+              <description>0: Means no failure and that the data of KEY0 is reliable. 1: Means that programming KEY0 failed and the number of error bytes is over 5.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in KEY1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_FAIL</name>
+              <description>0: Means no failure and that the data of KEY1 is reliable. 1: Means that programming KEY1 failed and the number of error bytes is over 5.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in KEY2.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_FAIL</name>
+              <description>0: Means no failure and that the data of KEY2 is reliable. 1: Means that programming KEY2 failed and the number of error bytes is over 5.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in KEY3.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_FAIL</name>
+              <description>0: Means no failure and that the data of KEY3 is reliable. 1: Means that programming KEY3 failed and the number of error bytes is over 5.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in KEY4.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_FAIL</name>
+              <description>0: Means no failure and that the data of KEY4 is reliable. 1: Means that programming KEY4 failed and the number of error bytes is over 5.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR1</name>
+          <description>Programming error record register 1 of BLOCK1-10.</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY5_FAIL</name>
+              <description>0: Means no failure and that the data of KEY5 is reliable. 1: Means that programming user data failed and the number of error bytes is over 5.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes in BLOCK10.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_FAIL</name>
+              <description>0: Means no failure and that the data of BLOCK10 is reliable. 1: Means that programming BLOCK10 data failed and the number of error bytes is over 5.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>eFuse clock configuration register.</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EFUSE_MEM_FORCE_PD</name>
+              <description>If set, forces eFuse SRAM into power-saving mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>If set, forces to activate clock signal of eFuse SRAM.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_MEM_FORCE_PU</name>
+              <description>If set, forces eFuse SRAM into working mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>If set, forces to enable clock signal of eFuse memory.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>eFuse operation mode configuration register.</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OP_CODE</name>
+              <description>0x5A5A: Operate programming command. 0x5AA5: Operate read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>eFuse status register.</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Indicates the state of the eFuse state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_LOAD_SW</name>
+              <description>The value of OTP_LOAD_SW.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_C_SYNC2</name>
+              <description>The value of OTP_VDDQ_C_SYNC2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_STROBE_SW</name>
+              <description>The value of OTP_STROBE_SW.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_CSB_SW</name>
+              <description>The value of OTP_CSB_SW.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_PGENB_SW</name>
+              <description>The value of OTP_PGENB_SW.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_IS_SW</name>
+              <description>The value of OTP_VDDQ_IS_SW.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REPEAT_ERR_CNT</name>
+              <description>Indicates the number of error bits during programming BLOCK0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>eFuse command register.</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_CMD</name>
+              <description>Set this bit to send read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_CMD</name>
+              <description>Set this bit to send programming command.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BLK_NUM</name>
+              <description>The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>eFuse raw interrupt register.</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_RAW</name>
+              <description>The raw bit signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_RAW</name>
+              <description>The raw bit signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>eFuse interrupt status register.</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ST</name>
+              <description>The status signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ST</name>
+              <description>The status signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>eFuse interrupt enable register.</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ENA</name>
+              <description>The enable signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ENA</name>
+              <description>The enable signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>eFuse interrupt clear register.</description>
+          <addressOffset>0x1E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_CLR</name>
+              <description>The clear signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_CLR</name>
+              <description>The clear signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAC_CONF</name>
+          <description>Controls the eFuse programming voltage.</description>
+          <addressOffset>0x1E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001FE1C</resetValue>
+          <fields>
+            <field>
+              <name>DAC_CLK_DIV</name>
+              <description>Controls the division factor of the rising clock of the programming voltage.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_PAD_SEL</name>
+              <description>Don't care.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_NUM</name>
+              <description>Controls the rising period of the programming voltage.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OE_CLR</name>
+              <description>Reduces the power supply of the programming voltage.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_TIM_CONF</name>
+          <description>Configures read timing parameters.</description>
+          <addressOffset>0x1EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x12010101</resetValue>
+          <fields>
+            <field>
+              <name>THR_A</name>
+              <description>Configures the hold time of read operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRD</name>
+              <description>Configures the length of pulse of read operation.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSUR_A</name>
+              <description>Configures the setup time of read operation.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>READ_INIT_NUM</name>
+              <description>Configures the initial read time of eFuse.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF0</name>
+          <description>Configuration register 0 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C80101</resetValue>
+          <fields>
+            <field>
+              <name>THP_A</name>
+              <description>Configures the hold time of programming operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TPGM_INACTIVE</name>
+              <description>Configures the length of pulse during programming 0 to eFuse.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TPGM</name>
+              <description>Configures the length of pulse during programming 1 to eFuse.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF1</name>
+          <description>Configuration register 1 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00288001</resetValue>
+          <fields>
+            <field>
+              <name>TSUP_A</name>
+              <description>Configures the setup time of programming operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWR_ON_NUM</name>
+              <description>Configures the power up time for VDDQ.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF2</name>
+          <description>Configuration register 2 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000190</resetValue>
+          <fields>
+            <field>
+              <name>PWR_OFF_NUM</name>
+              <description>Configures the power outage time for VDDQ.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19081100</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EXTMEM</name>
+      <description>External Memory</description>
+      <groupName>EXTMEM</groupName>
+      <baseAddress>0x61800000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x140</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PRO_DCACHE_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_ENABLE</name>
+              <description>The bit is used to activate the data cache. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_SETSIZE_MODE</name>
+              <description>The bit is used to configure cache memory size.0: 8KB, 1: 16KB</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_BLOCKSIZE_MODE</name>
+              <description>The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_INVALIDATE_ENA</name>
+              <description>The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_INVALIDATE_DONE</name>
+              <description>The bit is used to indicate invalidate operation is finished.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_FLUSH_ENA</name>
+              <description>The bit is used to enable flush operation. It will be cleared by hardware after flush operation done.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_FLUSH_DONE</name>
+              <description>The bit is used to indicate flush operation is finished.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_CLEAN_ENA</name>
+              <description>The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_CLEAN_DONE</name>
+              <description>The bit is used to indicate clean operation is finished.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_LOCK0_EN</name>
+              <description>The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK0_ADDR_REG and PRO_DCACHE_LOCK0_SIZE_REG.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_LOCK1_EN</name>
+              <description>The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK1_ADDR_REG and PRO_DCACHE_LOCK1_SIZE_REG.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate conditional-preload operation is finished.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_PRELOAD_DONE</name>
+              <description>The bit is used to indicate preload operation is finished.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_UNLOCK_ENA</name>
+              <description>The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_UNLOCK_DONE</name>
+              <description>The bit is used to indicate unlock operation is finished.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_LOCK_ENA</name>
+              <description>The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_LOCK_DONE</name>
+              <description>The bit is used to indicate lock operation is finished.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_CTRL1</name>
+          <description>register description</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_MASK_BUS0</name>
+              <description>The bit is used to disable dbus0, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_MASK_BUS1</name>
+              <description>The bit is used to disable dbus1, 0: enable, 1: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_MASK_BUS2</name>
+              <description>The bit is used to disable dbus2, 0: enable, 1: disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_TAG_POWER_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power dcache tag memory down, 0: follow  rtc_lslp_pd, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power dcache tag memory down, 0: follow  rtc_lslp_pd, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_LOCK0_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_LOCK0_ADDR</name>
+              <description>The bits are used to configure the first start virtual address of data locking, which is combined with PRO_DCACHE_LOCK0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_LOCK0_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_LOCK0_SIZE</name>
+              <description>The bits are used to configure the first length of data locking, which is combined with PRO_DCACHE_LOCK0_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_LOCK1_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_LOCK1_ADDR</name>
+              <description>The bits are used to configure the second start virtual address of data locking, which is combined with PRO_DCACHE_LOCK1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_LOCK1_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_LOCK1_SIZE</name>
+              <description>The bits are used to configure the second length of data locking, which is combined with PRO_DCACHE_LOCK1_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_MEM_SYNC0</name>
+          <description>register description</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_MEMSYNC_ADDR</name>
+              <description>The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_MEM_SYNC1</name>
+          <description>register description</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_MEMSYNC_SIZE</name>
+              <description>The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_PRELOAD_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_PRELOAD_ADDR</name>
+              <description>The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_PRELOAD_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_PRELOAD_SIZE</name>
+              <description>The bits are used to configure the length for manual pre-load operation.  It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_PRELOAD_ORDER</name>
+              <description>The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_AUTOLOAD_CFG</name>
+          <description>register description</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_MODE</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_STEP</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_ORDER</name>
+              <description>The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_RQST</name>
+              <description>The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_SIZE</name>
+              <description>The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_SCT0_ENA</name>
+              <description>The bits are used to enable the second section for conditional pre-load operation.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_SCT1_ENA</name>
+              <description>The bits are used to enable the first section for conditional pre-load operation.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_AUTOLOAD_SECTION0_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_SCT0_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_AUTOLOAD_SECTION0_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_SCT0_SIZE</name>
+              <description>The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_AUTOLOAD_SECTION1_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_SCT1_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_AUTOLOAD_SECTION1_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_AUTOLOAD_SCT1_SIZE</name>
+              <description>The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_ENABLE</name>
+              <description>The bit is used to activate the data cache. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_SETSIZE_MODE</name>
+              <description>The bit is used to configure cache memory size.0: 8KB, 1: 16KB</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_BLOCKSIZE_MODE</name>
+              <description>The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_INVALIDATE_ENA</name>
+              <description>The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_INVALIDATE_DONE</name>
+              <description>The bit is used to indicate invalidate operation is finished.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_LOCK0_EN</name>
+              <description>The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_LOCK1_EN</name>
+              <description>The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate conditional-preload operation is finished.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_PRELOAD_DONE</name>
+              <description>The bit is used to indicate preload operation is finished.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_UNLOCK_ENA</name>
+              <description>The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_UNLOCK_DONE</name>
+              <description>The bit is used to indicate unlock operation is finished.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_LOCK_ENA</name>
+              <description>The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_LOCK_DONE</name>
+              <description>The bit is used to indicate lock operation is finished.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_CTRL1</name>
+          <description>register description</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_MASK_BUS0</name>
+              <description>The bit is used to disable ibus0, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_MASK_BUS1</name>
+              <description>The bit is used to disable ibus1, 0: enable, 1: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_MASK_BUS2</name>
+              <description>The bit is used to disable ibus2, 0: enable, 1: disable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_TAG_POWER_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_LOCK0_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_LOCK0_ADDR</name>
+              <description>The bits are used to configure the first start virtual address of data locking, which is combined with PRO_ICACHE_LOCK0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_LOCK0_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_LOCK0_SIZE</name>
+              <description>The bits are used to configure the first length of data locking, which is combined with PRO_ICACHE_LOCK0_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_LOCK1_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_LOCK1_ADDR</name>
+              <description>The bits are used to configure the second start virtual address of data locking, which is combined with PRO_ICACHE_LOCK1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_LOCK1_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_LOCK1_SIZE</name>
+              <description>The bits are used to configure the second length of data locking, which is combined with PRO_ICACHE_LOCK1_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_MEM_SYNC0</name>
+          <description>register description</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_MEMSYNC_ADDR</name>
+              <description>The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_MEM_SYNC1</name>
+          <description>register description</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_MEMSYNC_SIZE</name>
+              <description>The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_PRELOAD_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_PRELOAD_ADDR</name>
+              <description>The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_PRELOAD_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_PRELOAD_SIZE</name>
+              <description>The bits are used to configure the length for manual pre-load operation.  It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_PRELOAD_ORDER</name>
+              <description>The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_AUTOLOAD_CFG</name>
+          <description>register description</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_MODE</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_STEP</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_ORDER</name>
+              <description>The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_RQST</name>
+              <description>The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_SIZE</name>
+              <description>The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_SCT0_ENA</name>
+              <description>The bits are used to enable the second section for conditional pre-load operation.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_SCT1_ENA</name>
+              <description>The bits are used to enable the first section for conditional pre-load operation.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_AUTOLOAD_SECTION0_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_SCT0_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_AUTOLOAD_SECTION0_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_SCT0_SIZE</name>
+              <description>The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_AUTOLOAD_SECTION1_ADDR</name>
+          <description>register description</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_SCT1_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_AUTOLOAD_SECTION1_SIZE</name>
+          <description>register description</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_AUTOLOAD_SCT1_SIZE</name>
+              <description>The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IC_PRELOAD_CNT</name>
+          <description>register description</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IC_PRELOAD_CNT</name>
+              <description>The bits are used to count the number of issued pre-load which include manual pre-load and conditional pre-load.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IC_PRELOAD_MISS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IC_PRELOAD_MISS_CNT</name>
+              <description>The bits are used to count the number of missed pre-load which include manual pre-load and conditional pre-load.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS2_ABANDON_CNT</name>
+          <description>register description</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS2_ABANDON_CNT</name>
+              <description>The bits are used to count the number of the abandoned ibus2 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS1_ABANDON_CNT</name>
+          <description>register description</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS1_ABANDON_CNT</name>
+              <description>The bits are used to count the number of the abandoned ibus1 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS0_ABANDON_CNT</name>
+          <description>register description</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS0_ABANDON_CNT</name>
+              <description>The bits are used to count the number of the abandoned ibus0 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS2_ACS_MISS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS2_ACS_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by ibus2 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS1_ACS_MISS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS1_ACS_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by ibus1 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS0_ACS_MISS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS0_ACS_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by ibus0 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS2_ACS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS2_ACS_CNT</name>
+              <description>The bits are used to count the number of ibus2 access icache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS1_ACS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS1_ACS_CNT</name>
+              <description>The bits are used to count the number of ibus1 access icache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS0_ACS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS0_ACS_CNT</name>
+              <description>The bits are used to count the number of ibus0 access icache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DC_PRELOAD_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DC_PRELOAD_CNT</name>
+              <description>The bits are used to count the number of issued pre-load which include manual pre-load and conditional pre-load.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DC_PRELOAD_EVICT_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DC_PRELOAD_EVICT_CNT</name>
+              <description>The bits are used to count the number of cache evictions by pre-load which include manual pre-load and conditional pre-load.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DC_PRELOAD_MISS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DC_PRELOAD_MISS_CNT</name>
+              <description>The bits are used to count the number of missed pre-load which include manual pre-load and conditional pre-load.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS2_ABANDON_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS2_ABANDON_CNT</name>
+              <description>The bits are used to count the number of the abandoned dbus2 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS1_ABANDON_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS1_ABANDON_CNT</name>
+              <description>The bits are used to count the number of the abandoned dbus1 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS0_ABANDON_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS0_ABANDON_CNT</name>
+              <description>The bits are used to count the number of the abandoned dbus0 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS2_ACS_WB_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS2_ACS_WB_CNT</name>
+              <description>The bits are used to count the number of cache evictions by dbus2 access cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS1_ACS_WB_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS1_ACS_WB_CNT</name>
+              <description>The bits are used to count the number of cache evictions by dbus1 access cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS0_ACS_WB_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS0_ACS_WB_CNT</name>
+              <description>The bits are used to count the number of cache evictions by dbus0 access cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS2_ACS_MISS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS2_ACS_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by dbus2 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS1_ACS_MISS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS1_ACS_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by dbus1 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS0_ACS_MISS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS0_ACS_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by dbus0 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS2_ACS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS2_ACS_CNT</name>
+              <description>The bits are used to count the number of dbus2 access dcache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS1_ACS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS1_ACS_CNT</name>
+              <description>The bits are used to count the number of dbus1 access dcache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS0_ACS_CNT</name>
+          <description>register description</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS0_ACS_CNT</name>
+              <description>The bits are used to count the number of dbus0 access dcache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_DBG_INT_ENA</name>
+          <description>register description</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_DBG_EN</name>
+              <description>The bit is used to activate the cache track function. 1: enable, 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IBUS_ACS_MSK_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IBUS_CNT_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt by ibus counter overflow.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IC_SYNC_SIZE_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by manual sync configurations fault.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IC_PRELOAD_SIZE_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by manual pre-load configurations fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SET_PRELOAD_ILG_INT_ENA</name>
+              <description>The bit is used to enable interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SET_SYNC_ILG_INT_ENA</name>
+              <description>The bit is used to enable interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SET_LOCK_ILG_INT_ENA</name>
+              <description>The bit is used to enable interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_MSK_DC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUS_CNT_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt by dbus counter overflow.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DC_SYNC_SIZE_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by manual sync configurations fault.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DC_PRELOAD_SIZE_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by manual pre-load configurations fault.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_WRITE_FLASH_INT_ENA</name>
+              <description>The bit is used to enable interrupt by dcache trying to write flash.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_SET_PRELOAD_ILG_INT_ENA</name>
+              <description>The bit is used to enable interrupt by illegal writing preload registers of dcache while dcache is busy to issue lock,sync and pre-load operations.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_SET_SYNC_ILG_INT_ENA</name>
+              <description>The bit is used to enable interrupt by illegal writing sync registers of dcache while dcache is busy to issue lock,sync and pre-load operations.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_SET_LOCK_ILG_INT_ENA</name>
+              <description>The bit is used to enable interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by mmu entry fault.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_DBG_INT_CLR</name>
+          <description>register description</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS_ACS_MSK_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IBUS_CNT_OVF_INT_CLR</name>
+              <description>The bit is used to clear interrupt by ibus counter overflow.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IC_SYNC_SIZE_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by manual sync configurations fault.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IC_PRELOAD_SIZE_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by manual pre-load configurations fault.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ICACHE_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ICACHE_SET_ILG_INT_CLR</name>
+              <description>The bit is used to clear interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_MSK_DC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DBUS_CNT_OVF_INT_CLR</name>
+              <description>The bit is used to clear interrupt by dbus counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DC_SYNC_SIZE_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by manual sync configurations fault.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DC_PRELOAD_SIZE_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by manual pre-load configurations fault.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DCACHE_WRITE_FLASH_INT_CLR</name>
+              <description>The bit is used to clear interrupt by dcache trying to write flash.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DCACHE_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DCACHE_SET_ILG_INT_CLR</name>
+              <description>The bit is used to clear interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by mmu entry fault.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_DBG_STATUS0</name>
+          <description>register description</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS0_ACS_MSK_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access icache while the ibus0 is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS1_ACS_MSK_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access icache while the ibus1 is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS2_ACS_MSK_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access icache while the ibus2 is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS0_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus0 counter overflow.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS1_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus1 counter overflow.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS2_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus2 counter overflow.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS0_ACS_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus0 miss counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS1_ACS_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus1 miss counter overflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS2_ACS_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus2 miss counter overflow.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS0_ABANDON_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus0 abandon counter overflow.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS1_ABANDON_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus1 abandon counter overflow.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS2_ABANDON_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus2 abandon counter overflow.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IC_PRELOAD_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by pre-load miss counter overflow.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IC_PRELOAD_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by pre-load counter overflow.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IC_SYNC_SIZE_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by manual sync configurations fault.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IC_PRELOAD_SIZE_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by manual pre-load configurations fault.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_SET_PRELOAD_ILG_ST</name>
+              <description>The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_SET_SYNC_ILG_ST</name>
+              <description>The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_SET_LOCK_ILG_ST</name>
+              <description>The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_DBG_STATUS1</name>
+          <description>register description</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS0_ACS_MSK_DCACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access dcache while the dbus0 is disabled or dcache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS1_ACS_MSK_DCACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access dcache while the dbus1 is disabled or dcache is disabled which include speculative access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS2_ACS_MSK_DCACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access dcache while the dbus2 is disabled or dcache is disabled which include speculative access.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS0_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus0 counter overflow.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS1_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus1 counter overflow.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS2_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus2 counter overflow.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS0_ACS_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus0 miss counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS1_ACS_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus1 miss counter overflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS2_ACS_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus2 miss counter overflow.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS0_ACS_WB_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus0 eviction counter overflow.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS1_ACS_WB_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus1 eviction counter overflow.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS2_ACS_WB_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus2 eviction counter overflow.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS0_ABANDON_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus0 abandon counter overflow.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS1_ABANDON_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus1 abandon counter overflow.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS2_ABANDON_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus2 abandon counter overflow.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DC_PRELOAD_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by pre-load miss counter overflow.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DC_PRELOAD_EVICT_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by pre-load eviction counter overflow.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DC_PRELOAD_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by pre-load counter overflow.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DC_SYNC_SIZE_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by manual sync configurations fault.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DC_PRELOAD_SIZE_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by manual pre-load configurations fault.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_WRITE_FLASH_ST</name>
+              <description>The bit is used to indicate interrupt by dcache trying to write flash.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_SET_PRELOAD_ILG_ST</name>
+              <description>The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_SET_SYNC_ILG_ST</name>
+              <description>The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_SET_LOCK_ILG_ST</name>
+              <description>The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by mmu entry fault.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_ACS_CNT_CLR</name>
+          <description>register description</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_ACS_CNT_CLR</name>
+              <description>The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG, DC_PRELOAD_EVICT_CNT_REG, DC_PRELOAD_MISS_CNT_REG, DBUS0-2_ABANDON_CNT_REG, DBUS0-2_ACS_WB_CNT_REG, DBUS0-2_ACS_MISS_CNT_REG and DBUS0-2_ACS_CNT_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_ACS_CNT_CLR</name>
+              <description>The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG, IC_PRELOAD_MISS_CNT_REG, IBUS0-2_ABANDON_CNT_REG, IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_REJECT_ST</name>
+          <description>register description</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_TAG_ATTR</name>
+              <description>The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_CPU_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access dcache when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_REJECT_VADDR</name>
+          <description>register description</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_CPU_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access dcache when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_REJECT_ST</name>
+          <description>register description</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_TAG_ATTR</name>
+              <description>The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_CPU_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access icache when authentication fail. 0: invalidate, 1: execute-able, 2: read-able</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_REJECT_VADDR</name>
+          <description>register description</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_CPU_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access icache when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_MMU_FAULT_CONTENT</name>
+          <description>register description</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_MMU_FAULT_CONTENT</name>
+              <description>The bits are used to indicate the content of mmu entry which cause mmu fault..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MMU_FAULT_CODE</name>
+              <description>The bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: flush, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_MMU_FAULT_VADDR</name>
+          <description>register description</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_MMU_FAULT_VADDR</name>
+              <description>The bits are used to indicate the virtual address which cause mmu fault..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_WRAP_AROUND_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_FLASH_WRAP_AROUND</name>
+              <description>The bit is used to enable wrap around mode when read data from flash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_SRAM_RD_WRAP_AROUND</name>
+              <description>The bit is used to enable wrap around mode when read data from spiram.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_MMU_POWER_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CACHE_MMU_MEM_FORCE_ON</name>
+              <description>The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MMU_MEM_FORCE_PD</name>
+              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_MMU_MEM_FORCE_PU</name>
+              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_STATE</name>
+          <description>register description</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_STATE</name>
+              <description>The bit is used to indicate icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_STATE</name>
+              <description>The bit is used to indicate dcache main fsm is in idle state or not. 1: in idle state,  0: not in idle state</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE</name>
+          <description>register description</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_DISABLE_DB_ENCRYPT</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_DISABLE_G0CB_DECRYPT</name>
+              <description>Reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON</name>
+          <description>register description</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>CLK_FORCE_ON_DB_ENCRYPT</name>
+              <description>The bit is used to close clock gating of encrypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_FORCE_ON_G0CB_DECRYPT</name>
+              <description>The bit is used to close clock gating of decrypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT</name>
+              <description>The bit is used to close clock gating of encrypt and decrypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_BRIDGE_ARBITER_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALLOC_WB_HOLD_ARBITER</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_PRELOAD_INT_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_PRELOAD_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by icache pre-load done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_PRELOAD_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by icache pre-load done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_PRELOAD_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by icache pre-load done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_PRELOAD_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by dcache pre-load done.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_PRELOAD_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by dcache pre-load done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_PRELOAD_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by dcache pre-load done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SYNC_INT_CTRL</name>
+          <description>register description</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_SYNC_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by icache sync done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_SYNC_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by icache sync done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_ICACHE_SYNC_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by icache sync done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_SYNC_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by dcache sync done.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_SYNC_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by dcache sync done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_SYNC_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by dcache sync done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CONF_MISC</name>
+          <description>register description</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT</name>
+              <description>The bit is used to disable checking mmu entry fault by preload operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT</name>
+              <description>The bit is used to disable checking mmu entry fault by sync operation.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>register description</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_EXTMEM_REG_DATE</name>
+          <description>register description</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01904180</resetValue>
+          <fields>
+            <field>
+              <name>PRO_EXTMEM_REG_DATE</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <baseAddress>0x3F404000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x634</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>GPIO</name>
+        <value>23</value>
+      </interrupt>
+      <interrupt>
+        <name>GPIO_NMI</name>
+        <value>24</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BT_SELECT</name>
+          <description>GPIO bit select register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_SEL</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT</name>
+          <description>GPIO0 ~ 31 output register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_ORIG</name>
+              <description>GPIO0 ~ 31 output value in simple GPIO output mode. The values of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31 respectively. Bit22 ~ bit25 are invalid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TS</name>
+          <description>GPIO0 ~ 31 output bit set register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TS</name>
+              <description>GPIO0 ~ 31 output set register. If the value 1 is written to a bit here, the corre- sponding bit in GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TC</name>
+          <description>GPIO0 ~ 31 output bit clear register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TC</name>
+              <description>GPIO0 ~ 31 output clear register. If the value 1 is written to a bit here, the cor- responding bit in GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1</name>
+          <description>GPIO32 ~ 53 output register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_ORIG</name>
+              <description>GPIO32 ~ 53 output value in simple GPIO output mode. The values of bit0 ~ bit13 correspond to GPIO32 ~ GPIO45. Bit14 ~ bit21 are invalid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1_W1TS</name>
+          <description>GPIO32 ~ 53 output bit set register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT1_W1TS</name>
+              <description>GPIO32 ~ 53 output value set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT1_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1_W1TC</name>
+          <description>GPIO32 ~ 53 output bit clear register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT1_W1TC</name>
+              <description>GPIO32 ~ 53 output value clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT1_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SELECT</name>
+          <description>GPIO SDIO selection register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_SEL</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE</name>
+          <description>GPIO0 ~ 31 output enable register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO0~31 output enable register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TS</name>
+          <description>GPIO0 ~ 31 output enable bit set register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TS</name>
+              <description>GPIO0 ~ 31 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <description>GPIO0 ~ 31 output enable bit clear register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TC</name>
+              <description>GPIO0 ~ 31 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1</name>
+          <description>GPIO32 ~ 53 output enable register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO32~53 output enable register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1_W1TS</name>
+          <description>GPIO32 ~ 53 output enable bit set register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE1_W1TS</name>
+              <description>GPIO32 ~ 53 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE1_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1_W1TC</name>
+          <description>GPIO32 ~ 53 output enable bit clear register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE1_W1TC</name>
+              <description>GPIO32 ~ 53 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE1_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STRAP</name>
+          <description>Bootstrap pin value register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRAPPING</name>
+              <description>GPIO strapping values: bit4 ~ bit2 correspond to stripping pins GPIO45, GPIO0, and GPIO46 respectively.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <description>GPIO0 ~ 31 input register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO0 ~ 31 input value. Each bit represents a pad input value, 1 for high level and 0 for low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN1</name>
+          <description>GPIO32 ~ 53 input register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DATA1_NEXT</name>
+              <description>GPIO32 ~ 53 input value. Each bit represents a pad input value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>GPIO0 ~ 31 interrupt status register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>GPIO0 ~ 31 interrupt status register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TS</name>
+          <description>GPIO0 ~ 31 interrupt status bit set register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TS</name>
+              <description>GPIO0 ~ 31 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set to 1. Recommended operation: use this register to set GPIO_STATUS_INTERRUPT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TC</name>
+          <description>GPIO0 ~ 31 interrupt status bit clear register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TC</name>
+              <description>GPIO0 ~ 31 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. Recommended operation: use this register to clear GPIO_STATUS_INTERRUPT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1</name>
+          <description>GPIO32 ~ 53 interrupt status register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>GPIO32 ~ 53 interrupt status register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1_W1TS</name>
+          <description>GPIO32 ~ 53 interrupt status bit set register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS1_W1TS</name>
+              <description>GPIO32 ~ 53 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be set to 1. Recommended operation: use this register to set GPIO_STATUS1_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1_W1TC</name>
+          <description>GPIO32 ~ 53 interrupt status bit clear register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS1_W1TC</name>
+              <description>GPIO32 ~ 53 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be cleared. Recommended operation: use this register to clear GPIO_STATUS1_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT</name>
+          <description>GPIO0 ~ 31 PRO_CPU interrupt status register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT</name>
+              <description>GPIO0 ~ 31 PRO_CPU interrupt status. This interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit13 of GPIO_PINn_REG).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT</name>
+          <description>GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT</name>
+              <description>GPIO0 ~ 31 PRO_CPU non-maskable interrupt status. This interrupt sta- tus is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit 14 of GPIO_PINn_REG).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT</name>
+          <description>GPIO0 ~ 31 CPU SDIO interrupt status register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT</name>
+              <description>GPIO0~31 CPU SDIO interrupt status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT1</name>
+          <description>GPIO32 ~ 53 PRO_CPU interrupt status register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU1_INT</name>
+              <description>GPIO32 ~ 53 PRO_CPU interrupt status. This interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high) enable signal (bit 13 of GPIO_PINn_REG).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT1</name>
+          <description>GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI1_INT</name>
+              <description>GPIO32 ~ 53 PRO_CPU non-maskable interrupt status. This interrupt status is corresponding to bit in GPIO_STATUS1_REG when assert (high) enable signal (bit 14 of GPIO_PINn_REG).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT1</name>
+          <description>GPIO32 ~ 53 CPU SDIO interrupt status register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO1_INT</name>
+              <description>GPIO32~53 CPU SDIO interrupt status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>54</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>PIN%s</name>
+          <description>Configuration for GPIO pin %s</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYNC2_BYPASS</name>
+              <description>For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>Pad driver selection. 0: normal output; 1: open drain output..</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC1_BYPASS</name>
+              <description>For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TYPE</name>
+              <description>Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENABLE</name>
+              <description>GPIO wake-up enable bit, only wakes up the CPU from Light-sleep.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONFIG</name>
+              <description>Reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_ENA</name>
+              <description>Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_NEXT</name>
+          <description>GPIO0 ~ 31 interrupt source register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INTERRUPT_NEXT</name>
+              <description>Interrupt source signal of GPIO0 ~ 31, could be rising edge interrupt, falling edge interrupt, level sensitive interrupt and any edge interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_NEXT1</name>
+          <description>GPIO32 ~ 53 interrupt source register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS1_INTERRUPT_NEXT</name>
+              <description>Interrupt source signal of GPIO32 ~ 53.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>256</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>FUNC%s_IN_SEL_CFG</name>
+          <description>Peripheral function %s input selection register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>Selection control for peripheral input signal m, selects a pad from the 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a constantly high input or 0x3C for a constantly low input.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>Invert the input value. 1: invert enabled; 0: invert disabled.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals directly to peripheral configured in IO_MUX.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>54</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>FUNC%s_OUT_SEL_CFG</name>
+          <description>Peripheral output selection for GPIO %s</description>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>OUT_SEL</name>
+              <description>Selection control for GPIO output n. If a value s (0&lt;=s&lt;256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INV_SEL</name>
+              <description>0: Do not invert the output value; 1: Invert the output value.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_SEL</name>
+              <description>0: Use output enable signal from peripheral; 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_INV_SEL</name>
+              <description>0: Do not invert the output enable signal; 1: Invert the output enable signal.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>GPIO clock gating register</description>
+          <addressOffset>0x62C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Clock gating enable bit. If set to 1, the clock is free running.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x6FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01905061</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO_SD</name>
+      <description>Sigma-Delta Modulation</description>
+      <groupName>GPIOSD</groupName>
+      <baseAddress>0x3F404F00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x2C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SIGMADELTA%s</name>
+          <description>Duty-cycle configuration register of SDM%s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD0_IN</name>
+              <description>This field is used to configure the duty cycle of sigma delta modulation output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD0_PRESCALE</name>
+              <description>This field is used to set a divider value to divide APB clock.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_CG</name>
+          <description>Clock gating configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Clock enable bit of configuration registers for sigma delta modulation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_MISC</name>
+          <description>MISC register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FUNCTION_CLK_EN</name>
+              <description>Clock enable bit of sigma delta modulation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SWAP</name>
+              <description>Reserved.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_VERSION</name>
+          <description>Version control register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01802260</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_SD_DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMAC</name>
+      <description>HMAC (Hash-based Message Authentication Code) Accelerator</description>
+      <groupName>HMAC</groupName>
+      <baseAddress>0x6003E000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x9C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SET_START</name>
+          <description>HMAC start control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>Set this bit to enable HMAC.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_PURPOSE</name>
+          <description>HMAC parameter configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PURPOSE_SET</name>
+              <description>Set hmac purpose.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_KEY</name>
+          <description>HMAC key configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_SET</name>
+              <description>Select hmac key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_FINISH</name>
+          <description>HMAC configuration completion register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_PARA_END</name>
+              <description>Set this bit to finish HMAC configuration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ONE</name>
+          <description>HMAC one message control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ONE</name>
+              <description>Call SHA to calculate one message block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ING</name>
+          <description>HMAC message continue register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ING</name>
+              <description>Set this bit to show there are still some message blocks to be processed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_END</name>
+          <description>HMAC message end register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_END</name>
+              <description>Set this bit to start hardware padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_RESULT_FINISH</name>
+          <description>HMAC read result completion register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_RESULT_END</name>
+              <description>Set this bit to end upstream and clear the calculation result.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_JTAG</name>
+          <description>Invalidate JTAG result register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_JTAG</name>
+              <description>Set this bit to clear calculation results in JTAG re-enable function under downstream mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_DS</name>
+          <description>Invalidate digital signature result register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_DS</name>
+              <description>Set this bit to clear calculation results in DS function under downstream mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_ERROR</name>
+          <description>The matching result between key and purpose user configured</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUREY_CHECK</name>
+              <description>Hmac error status.
+
+0: hmac key and purpose match.
+
+1: error.
+
+</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>The busy state of HMAC module</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUSY_STATE</name>
+              <description>The state of Hmac.
+
+1'b0: idle.
+
+1'b1: busy.
+
+</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>WR_MESSAGE_%s</name>
+          <description>Message register %s</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDATA</name>
+              <description>Store the %sth 32-bit of message.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RD_RESULT_%s</name>
+          <description>Hash result register %s</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RDATA</name>
+              <description>Read the %sth 32-bit of hash result.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_PAD</name>
+          <description>Software padding register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_PAD</name>
+              <description>Set this bit to let software do padding job.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ONE_BLOCK</name>
+          <description>One block message register.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_ONE_BLOCK</name>
+              <description>Set this bit to show no padding is required.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20190402</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2C0</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x3F413000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C_EXT0</name>
+        <value>52</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SCL_LOW_PERIOD</name>
+          <description>Configures the low level width of the SCL clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_LOW_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTR</name>
+          <description>Transmission setting</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000A0B</resetValue>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>0: direct output. 1: open drain output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>0: direct output. 1: open drain output.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAMPLE_SCL_LEVEL</name>
+              <description>This register is used to select the sample mode.
+
+1: sample SDA data on the SCL low level.
+
+0: sample SDA data on the SCL high level.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FULL_ACK_LEVEL</name>
+              <description>This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>Set this bit to start sending the data in TX FIFO.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>This bit is used to control the sending mode for data needing to be sent.
+
+1: send data from the least significant bit.
+
+0: send data from the most significant bit.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>This bit is used to control the storage mode for received data.
+
+1: receive data from the least significant bit.
+
+0: receive data from the most significant bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_EN</name>
+              <description>This is the enable bit for I2C bus arbitration function.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FSM_RST</name>
+              <description>This register is used to reset the SCL_FSM.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REF_ALWAYS_ON</name>
+              <description>This register is used to control the REF_TICK.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <description>Describe I2C work status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RESP_REC</name>
+              <description>The received ACK value in master mode or slave mode. 0: ACK. 1: NACK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW</name>
+              <description>When in slave mode, 1: master reads from slave. 0: master writes to slave.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT</name>
+              <description>When the I2C controller takes more than I2C_TIME_OUT clocks to receive a data bit, this field changes to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>When the I2C controller loses control of SCL line, this register changes to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>1: the I2C bus is busy transferring data. 0: the I2C bus is in idle state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDRESSED</name>
+              <description>When configured as an I2C Slave, and the address sent by the master is equal to the address of the slave, then this bit will be of high level.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS</name>
+              <description>This field changes to 1 when one byte is transferred.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>This field represents the amount of data needed to be sent.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STRETCH_CAUSE</name>
+              <description>The cause of stretching SCL low in slave mode. 0:  stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C TX FIFO is empty in slave mode. 2: stretching SCL low when I2C RX FIFO is full in slave mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>This field stores the amount of received data in RAM.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_STATE_LAST</name>
+              <description>This field indicates the states of the I2C module state machine.
+
+0: Idle. 1: Address shift. 2: ACK address. 3: RX data. 4: TX data. 5: Send ACK. 6: Wait ACK</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_STATE_LAST</name>
+              <description>This field indicates the states of the state machine used to produce SCL.
+
+0: Idle. 1: Start. 2: Negative edge. 3: Low. 4: Positive edge. 5: High. 6: Stop</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TO</name>
+          <description>Setting time out control for receiving data</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_OUT_VALUE</name>
+              <description>This register is used to configure the timeout for receiving a data bit in APB clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_EN</name>
+              <description>This is the enable bit for time out control.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_ADDR</name>
+          <description>Local slave address setting</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_ADDR</name>
+              <description>When configured as an I2C Slave, this field is used to configure the slave address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_EN</name>
+              <description>This field is used to enable the slave 10-bit addressing mode in master mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_ST</name>
+          <description>FIFO status register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_START_ADDR</name>
+              <description>This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_END_ADDR</name>
+              <description>This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES. This value refreshes when an I2C_RXFIFO_UDF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_START_ADDR</name>
+              <description>This is the offset address of the first sent data, as described in I2C_NONFIFO_TX_THRES.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_END_ADDR</name>
+              <description>This is the offset address of the last sent data, as described in  I2C_NONFIFO_TX_THRES.
+
+The value refreshes when an I2C_TXFIFO_OVF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_UPDATE</name>
+              <description>Write 0 or 1 to I2C_RX_UPDATE to update the value of I2C_RXFIFO_END_ADDR and I2C_RXFIFO_START_ADDR.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_UPDATE</name>
+              <description>Write 0 or 1 to I2C_TX_UPDATE to update the value of I2C_TXFIFO_END_ADDR and I2C_TXFIFO_START_ADDR.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW_POINT</name>
+              <description>The received data in I2C slave mode.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_CONF</name>
+          <description>FIFO configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0555408B</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], I2C_RXFIFO_WM_INT_RAW bit will be valid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD[4:0], I2C_TXFIFO_WM_INT_RAW bit will be valid.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_EN</name>
+              <description>Set this bit to enable APB non-FIFO mode.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_ADDR_CFG_EN</name>
+              <description>When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RST</name>
+              <description>Set this bit to reset RX FIFO.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RST</name>
+              <description>Set this bit to reset TX FIFO.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_RX_THRES</name>
+              <description>When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_TX_THRES</name>
+              <description>When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_PRT_EN</name>
+              <description>The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>RX FIFO read data</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_RDATA</name>
+              <description>The value of RX FIFO read data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <description>Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_CLR</name>
+              <description>Set this bit to clear I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ENA</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ENA</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ENA</name>
+              <description>The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ENA</name>
+              <description>The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ENA</name>
+              <description>The raw interrupt bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NACK_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ENA</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS</name>
+          <description>Status of captured I2C communication events</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_HOLD</name>
+          <description>Configures the hold time after a negative SCL edge</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the interval between changing the SDA output level and the falling edge of SCL, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_SAMPLE</name>
+          <description>Configures the sample time after a positive SCL edge</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the interval between the rising edge of SCL and the level sampling time of SDA, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH_PERIOD</name>
+          <description>Configures the high level width of the SCL clock</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_HIGH_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_WAIT_HIGH_PERIOD</name>
+              <description>This register is used to configure for the SCL_FSM's waiting period for SCL to go high in master mode, in I2C module clock cycles.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_HOLD</name>
+          <description>Configures the interval between pulling SDA low and pulling SCL low when the master generates a START condition</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure  interval between pulling SDA low and pulling SCL low when the master generates a START condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_RSTART_SETUP</name>
+          <description>Configures the interval between the positive edge of SCL and the negative edge of SDA</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the interval between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_HOLD</name>
+          <description>Configures the delay after the SCL clock edge for a stop condition</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the delay after the STOP condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_SETUP</name>
+          <description>Configures the delay between the SDA and SCL positive edge for a stop condition</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_FILTER_CFG</name>
+          <description>SCL filter configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_FILTER_THRES</name>
+              <description>When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FILTER_EN</name>
+              <description>This is the filter enable bit for SCL.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_FILTER_CFG</name>
+          <description>SDA filter configuration register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SDA_FILTER_THRES</name>
+              <description>When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_EN</name>
+              <description>This is the filter enable bit for SDA.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-15</dimIndex>
+          <name>COMD%s</name>
+          <description>I2C command register %s</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND</name>
+              <description>This is the content of command 0. It consists of three parts:
+
+op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END.
+
+byte_num represents the number of bytes that need to be sent or received.
+
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND_DONE</name>
+              <description>When command 0 is done in I2C Master mode, this bit changes to high level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_ST_TIME_OUT</name>
+          <description>SCL status time out register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>SCL_ST_TO</name>
+              <description>The threshold value of SCL_FSM state unchanged period.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_MAIN_ST_TIME_OUT</name>
+          <description>SCL main status time out register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>SCL_MAIN_ST_TO</name>
+              <description>The threshold value of SCL_MAIN_FSM state unchanged period.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_SP_CONF</name>
+          <description>Power configuration register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_RST_SLV_EN</name>
+              <description>When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_RST_SLV_NUM</name>
+              <description>Configure the pulses of SCL generated in I2C master mode. Valid when I2C_SCL_RST_SLV_EN is 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_PD_EN</name>
+              <description>The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set I2C_SCL_FORCE_OUT and I2C_SCL_PD_EN to 1 to stretch SCL low.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_PD_EN</name>
+              <description>The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set I2C_SDA_FORCE_OUT and I2C_SDA_PD_EN to 1 to stretch SDA low.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STRETCH_CONF</name>
+          <description>Set SCL stretch of I2C slave</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRETCH_PROTECT_NUM</name>
+              <description>Configure the period of I2C slave stretching SCL line.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_EN</name>
+              <description>The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The stretch cause can be seen in I2C_STRETCH_CAUSE.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_CLR</name>
+              <description>Set this bit to clear the I2C slave SCL stretch function.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19052000</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the the version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="I2C0">
+      <name>I2C1</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <baseAddress>0x3F427000</baseAddress>
+      <interrupt>
+        <name>I2C_EXT1</name>
+        <value>53</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <description>I2S (Inter-IC Sound) Controller</description>
+      <groupName>I2S</groupName>
+      <baseAddress>0x3F40F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CONF</name>
+          <description>I2S configuration register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000C0300</resetValue>
+          <fields>
+            <field>
+              <name>TX_RESET</name>
+              <description>Set this bit to reset transmitter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_RESET</name>
+              <description>Set this bit to reset receiver.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RESET</name>
+              <description>Set this bit to reset TX FIFO.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RESET</name>
+              <description>Set this bit to reset RX FIFO.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START</name>
+              <description>Set this bit to start transmitting data.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_START</name>
+              <description>Set this bit to start receiving data.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave transmitter mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave receiver mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_RIGHT_FIRST</name>
+              <description>Set this bit to transmit right channel data first.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RIGHT_FIRST</name>
+              <description>Set this bit to receive right channel data first.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MSB_SHIFT</name>
+              <description>Set this bit to enable transmitter in Phillips standard mode.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MSB_SHIFT</name>
+              <description>Set this bit to enable receiver in Phillips standard mode.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SHORT_SYNC</name>
+              <description>Set this bit to enable transmitter in PCM standard mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SHORT_SYNC</name>
+              <description>Set this bit to enable receiver in PCM standard mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO</name>
+              <description>Set this bit to enable transmitter in mono mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO</name>
+              <description>Set this bit to enable receiver  in mono mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MSB_RIGHT</name>
+              <description>Set this bit to place right channel data at the MSB in TX FIFO.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MSB_RIGHT</name>
+              <description>Set this bit to place right channel data at the MSB in RX FIFO.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST_DMA</name>
+              <description>1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST_DMA</name>
+              <description>1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_LOOPBACK</name>
+              <description>Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RESET_ST</name>
+              <description>I2S TX FIFO reset status. 1: I2S_TX_FIFO_RESET is not completed. 0: I2S_TX_FIFO_RESET is completed.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RESET_ST</name>
+              <description>I2S RX FIFO reset status. 1: I2S_RX_FIFO_RESET is not completed. 0: I2S_RX_FIFO_RESET is completed.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_RESET_ST</name>
+              <description>I2S TX reset status. 1: I2S_TX_RESET is not completed. 0: I2S_TX_RESET is completed.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DMA_EQUAL</name>
+              <description>1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DMA_EQUAL</name>
+              <description>1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRE_REQ_EN</name>
+              <description>Set this bit to enable I2S to prepare data earlier.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIG_ENDIAN</name>
+              <description>I2S TX byte endianness.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIG_ENDIAN</name>
+              <description>I2S RX byte endianness.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RESET_ST</name>
+              <description>I2S RX reset status. 1: I2S_RX_RESET is not completed. 0: I2S_RX_RESET is completed.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_TAKE_DATA_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_RX_TAKE_DATA_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_PUT_DATA_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_TX_PUT_DATA_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_WFULL_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_RX_WFULL_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_REMPTY_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_RX_REMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_WFULL_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_TX_WFULL_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_REMPTY_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_TX_REMPTY_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_RX_HUNG_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_TX_HUNG_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_IN_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_IN_SUC_EOF_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_RAW</name>
+              <description>Reserved.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_OUT_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_OUT_EOF_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_IN_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_OUT_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_IN_DSCR_EMPTY_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_OUT_TOTAL_EOF_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>V_SYNC_INT_RAW</name>
+              <description>The raw interrupt status bit  for I2S_V_SYNC_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_TAKE_DATA_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_RX_TAKE_DATA_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_PUT_DATA_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_TX_PUT_DATA_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_WFULL_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_RX_WFULL_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_REMPTY_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_RX_REMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_WFULL_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_TX_WFULL_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_REMPTY_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_TX_REMPTY_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_RX_HUNG_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_TX_HUNG_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_IN_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_IN_SUC_EOF_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ST</name>
+              <description>Reserved.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_OUT_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_OUT_EOF_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_IN_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_OUT_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_IN_DSCR_EMPTY_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_OUT_TOTAL_EOF_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>V_SYNC_INT_ST</name>
+              <description>The masked interrupt status bit  for I2S_V_SYNC_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_TAKE_DATA_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_RX_TAKE_DATA_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PUT_DATA_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_TX_PUT_DATA_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WFULL_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_RX_WFULL_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_REMPTY_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_RX_REMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WFULL_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_TX_WFULL_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_REMPTY_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_TX_REMPTY_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_RX_HUNG_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_TX_HUNG_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_IN_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_IN_SUC_EOF_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ENA</name>
+              <description>Reserved.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_OUT_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_OUT_EOF_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_IN_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_OUT_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_IN_DSCR_EMPTY_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_OUT_TOTAL_EOF_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>V_SYNC_INT_ENA</name>
+              <description>The interrupt enable bit  for I2S_V_SYNC_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TAKE_DATA_INT_CLR</name>
+              <description>Set this bit to clear I2S_RX_TAKE_DATA_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PUT_DATA_INT_CLR</name>
+              <description>Set this bit to clear I2S_TX_PUT_DATA_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_WFULL_INT_CLR</name>
+              <description>Set this bit to clear I2S_RX_WFULL_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_REMPTY_INT_CLR</name>
+              <description>Set this bit to clear I2S_RX_REMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_WFULL_INT_CLR</name>
+              <description>Set this bit to clear I2S_TX_WFULL_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_REMPTY_INT_CLR</name>
+              <description>Set this bit to clear I2S_TX_REMPTY_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear I2S_RX_HUNG_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear I2S_TX_HUNG_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_CLR</name>
+              <description>Set this bit to clear I2S_IN_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_CLR</name>
+              <description>Set this bit to clear I2S_IN_SUC_EOF_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_CLR</name>
+              <description>Reserved.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_CLR</name>
+              <description>Set this bit to clear I2S_OUT_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_CLR</name>
+              <description>Set this bit to clear I2S_OUT_EOF_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_CLR</name>
+              <description>Set this bit to clear I2S_IN_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_CLR</name>
+              <description>Set this bit to clear I2S_OUT_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear I2S_IN_DSCR_EMPTY_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_CLR</name>
+              <description>Set this bit to clear I2S_OUT_TOTAL_EOF_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>V_SYNC_INT_CLR</name>
+              <description>Set this bit to clear I2S_V_SYNC_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMING</name>
+          <description>I2S timing register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BCK_IN_DELAY</name>
+              <description>Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IN_DELAY</name>
+              <description>Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_IN_DELAY</name>
+              <description>Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IN_DELAY</name>
+              <description>Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SD_IN_DELAY</name>
+              <description>Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_OUT_DELAY</name>
+              <description>Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_OUT_DELAY</name>
+              <description>Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SD_OUT_DELAY</name>
+              <description>Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_OUT_DELAY</name>
+              <description>Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_OUT_DELAY</name>
+              <description>Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DSYNC_SW</name>
+              <description>Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DSYNC_SW</name>
+              <description>Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_ENABLE_DELAY</name>
+              <description>Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_IN_INV</name>
+              <description>Set this bit to invert BCK signal input to the slave transmitter.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_CONF</name>
+          <description>I2S FIFO configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001820</resetValue>
+          <fields>
+            <field>
+              <name>RX_DATA_NUM</name>
+              <description>I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM[5:0]. (RX FIFO is almost full threshold.)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DATA_NUM</name>
+              <description>I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM[5:0]. (TX FIFO is almost empty threshold.)</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSCR_EN</name>
+              <description>Set this bit to enable I2S DMA mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_MOD</name>
+              <description>Transmitter FIFO mode configuration bits</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_MOD</name>
+              <description>Receiver FIFO mode configuration bits</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_MOD_FORCE_EN</name>
+              <description>The bit should always be set to 1</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_MOD_FORCE_EN</name>
+              <description>The bit should always be set to 1</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_SYNC</name>
+              <description>force write back rx data to memory</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_24MSB_EN</name>
+              <description>Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo   0: the low 24 bits are effective in i2s fifo</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_24MSB_EN</name>
+              <description>Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo   0: the low 24 bits are effective in i2s fifo</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXEOF_NUM</name>
+          <description>I2S DMA RX EOF data length</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000040</resetValue>
+          <fields>
+            <field>
+              <name>RX_EOF_NUM</name>
+              <description>The length of data to be received. It will trigger I2S_IN_SUC_EOF_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_SIGLE_DATA</name>
+          <description>Constant single channel data</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SIGLE_DATA</name>
+              <description>The right channel or left channel transmits constant value stored in this register according to I2S_TX_CHAN_MOD and I2S_TX_MSB_RIGHT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_CHAN</name>
+          <description>I2S channel configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_CHAN_MOD</name>
+              <description>I2S transmitter channel mode configuration bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CHAN_MOD</name>
+              <description>I2S receiver channel mode configuration bits.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_LINK</name>
+          <description>I2S DMA TX configuration register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>The address of first outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set this bit to stop outlink descriptor.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set this bit to start outlink descriptor.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set this bit to restart outlink descriptor.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_LINK</name>
+          <description>I2S DMA RX configuration register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>The address of first inlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set this bit to stop inlink descriptor.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set this bit to start inlink descriptor.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set this bit to restart inlink descriptor.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_DES_ADDR</name>
+          <description>Address of outlink descriptor that produces EOF</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR</name>
+              <description>The address of outlink descriptor that produces EOF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EOF_DES_ADDR</name>
+          <description>Address of inlink descriptor that produces EOF</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR</name>
+              <description>The address of inlink descriptor that produces EOF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_BFR_DES_ADDR</name>
+          <description>Address of buffer relative to the outlink descriptor that produces EOF</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR</name>
+              <description>The address of buffer relative to the outlink descriptor that produces EOF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR</name>
+          <description>Address of current inlink descriptor</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR</name>
+              <description>The address of current inlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR_BF0</name>
+          <description>Address of next inlink descriptor</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0</name>
+              <description>The address of next inlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR_BF1</name>
+          <description>Address of next inlink data buffer</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1</name>
+              <description>The address of next inlink data buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR</name>
+          <description>Address of current outlink descriptor</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR</name>
+              <description>The address of current outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR_BF0</name>
+          <description>Address of next outlink descriptor</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0</name>
+              <description>The address of next outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR_BF1</name>
+          <description>Address of next outlink data buffer</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1</name>
+              <description>The address of next outlink data buffer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_CONF</name>
+          <description>I2S DMA configuration register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>Set this bit to reset in-DMA FSM. Set this bit before the DMA configuration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_RST</name>
+              <description>Set this bit to reset out-DMA FSM. Set this bit before the DMA configuration.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_FIFO_RST</name>
+              <description>Set this bit to reset AHB interface cmdFIFO of DMA. Set this bit before the DMA configuration.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_RST</name>
+              <description>Set this bit to reset AHB interface of DMA. Set this bit before the DMA configuration.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>Set this bit to loop test inlink.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>Set this bit to loop test outlink.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>Set this bit to enable outlink-written-back automatically when out buffer is transmitted done.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_NO_RESTART_CLR</name>
+              <description>Reserved.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>DMA out EOF flag generation mode. 1: When DMA has popped all data from the FIFO. 0: When AHB has pushed all data to the FIFO.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>DMA outlink descriptor transfer mode configuration bit. 1: Prepare outlink descriptor with burst mode. 0: Prepare outlink descriptor with byte mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>DMA inlink descriptor transfer mode configuration bit. 1: Prepare inlink descriptor with burst mode. 0: Prepare inlink descriptor with byte mode.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <description>Transmitter data transfer mode configuration bit. 1: Prepare out data with burst mode. 0: Prepare out data with byte mode.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_OWNER</name>
+              <description>Set this bit to enable check owner bit by hardware.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_MEM_BK_SIZE</name>
+              <description>DMA access external memory block size. 0: 16 bytes. 1: 32 bytes. 2: 64 bytes. 3: reserved.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTFIFO_PUSH</name>
+          <description>APB out FIFO mode register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA</name>
+              <description>APB out FIFO write data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH</name>
+              <description>APB out FIFO  push.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INFIFO_POP</name>
+          <description>APB in FIFO mode register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA</name>
+              <description>APB in FIFO  read data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP</name>
+              <description>APB in FIFO  pop.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_STATE0</name>
+          <description>I2S DMA TX status</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_ADDR</name>
+              <description>I2S DMA out descriptor address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_STATE</name>
+              <description>I2S DMA out descriptor state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_STATE</name>
+              <description>I2S DMA out data state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT</name>
+              <description>The remains of I2S DMA outfifo data.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_FULL</name>
+              <description>I2S DMA outfifo is full.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EMPTY</name>
+              <description>I2S DMA outfifo is empty.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_STATE1</name>
+          <description>I2S DMA RX status</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_ADDR</name>
+              <description>I2S DMA in descriptor address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_STATE</name>
+              <description>I2S DMA in descriptor state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_STATE</name>
+              <description>I2S DMA in data state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT_DEBUG</name>
+              <description>The remains of I2S DMA infifo data.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_FULL</name>
+              <description>I2S DMA infifo is full.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EMPTY</name>
+              <description>I2S DMA infifo is empty.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_HUNG_CONF</name>
+          <description>I2S Hung configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000810</resetValue>
+          <fields>
+            <field>
+              <name>LC_FIFO_TIMEOUT</name>
+              <description>I2S_TX_HUNG_INT interrupt or I2S_RX_HUNG_INT interrupt will be triggered when FIFO hung counter is equal to this value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_SHIFT</name>
+              <description>The bits are used to set the tick counter threshold. The tick counter is clocked by APB_CLK. The tick counter threshold is 88000/2^I2S_LC_FIFO_TIMEOUT_SHIFT. The tick counter is reset when it reaches the threshold.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_ENA</name>
+              <description>The enable bit for FIFO timeout.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>I2S configuration register 1</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000089</resetValue>
+          <fields>
+            <field>
+              <name>TX_PCM_CONF</name>
+              <description>Compress/Decompress module configuration bits. 0: decompress transmitted data  1:compress transmitted data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_BYPASS</name>
+              <description>Set this bit to bypass  Compress/Decompress module for transmitted data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_CONF</name>
+              <description>Compress/Decompress module configuration bits. 0: decompress received data  1:compress received data</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_BYPASS</name>
+              <description>Set this bit to bypass Compress/Decompress module for received data.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP_EN</name>
+              <description>Set this bit to stop the output of BCK signal and WS signal when TX FIFO is empty.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_ZEROS_RM_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_CONF</name>
+          <description>I2S power-down configuration register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000002A</resetValue>
+          <fields>
+            <field>
+              <name>FIFO_FORCE_PD</name>
+              <description>Force FIFO power-down.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_FORCE_PU</name>
+              <description>Force FIFO power-up.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLC_MEM_FORCE_PD</name>
+              <description>Force I2S memory power-down.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLC_MEM_FORCE_PU</name>
+              <description>Force I2S memory power-up.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RAM_FORCE_PD</name>
+              <description>Force DMA FIFO power-down.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RAM_FORCE_PU</name>
+              <description>Force DMA FIFO power-up.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RAM_CLK_FO</name>
+              <description>Set this bit to force on DMA RAM clock.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF2</name>
+          <description>I2S configuration register 2</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAMERA_EN</name>
+              <description>Set this bit to enable camera mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_TX_WRX2_EN</name>
+              <description>LCD WR double for one datum.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_TX_SDX2_EN</name>
+              <description>Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_ENABLE_TEST_EN</name>
+              <description>for debug camera mode enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_ENABLE</name>
+              <description>for debug camera mode enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_EN</name>
+              <description>Set this bit to enable LCD mode.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_ADC_START_EN</name>
+              <description>Set this bit to enable the function that ADC mode is triggered by external signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_VALID_EN</name>
+              <description>Set this bit to enable camera VGA reducing-resolution mode: only receive two consecutive cycle data in four consecutive clocks.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_SYNC_FIFO_RESET</name>
+              <description>Set this bit to reset FIFO in camera mode.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CLK_LOOPBACK</name>
+              <description>Set this bit to loopback PCLK from I2S0I_WS_out.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VSYNC_FILTER_EN</name>
+              <description>Set this bit to enable I2S VSYNC filter function.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VSYNC_FILTER_THRES</name>
+              <description>Configure the I2S VSYNC filter threshold value.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKM_CONF</name>
+          <description>I2S module clock configuration register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_B</name>
+              <description>Fractional clock divider numerator value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_A</name>
+              <description>Fractional clock divider denominator value.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clock gate.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_SEL</name>
+              <description>Set this bit to select I2S module clock source. 0: No clock. 1: APLL_CLK. 2: PLL_160M_CLK. 3: No clock.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAMPLE_RATE_CONF</name>
+          <description>I2S sample rate register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00410186</resetValue>
+          <fields>
+            <field>
+              <name>TX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in transmitter mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in receiver mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BITS_MOD</name>
+              <description>Set the bits to configure bit length of I2S transmitter channel, the value of which can only be 8, 16, 24 and 32.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BITS_MOD</name>
+              <description>Set the bits to configure bit length of I2S receiver channel, the value of which can only be 8, 16, 24 and 32.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>I2S TX status register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TX_IDLE</name>
+              <description>1: I2S TX is in idle state. 0: I2S TX is at work.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19052500</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>INTERRUPT</name>
+      <description>Interrupt</description>
+      <groupName>INTERRUPT</groupName>
+      <baseAddress>0x3F4C2000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x190</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WIFI_MAC</name>
+        <value>0</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_MAC_NMI</name>
+        <value>1</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_PWR</name>
+        <value>2</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_BB</name>
+        <value>3</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_MAC</name>
+        <value>4</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_BB</name>
+        <value>5</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_BB_NMI</name>
+        <value>6</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBT</name>
+        <value>7</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBLE</name>
+        <value>8</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBT_NMI</name>
+        <value>9</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBLE_NMI</name>
+        <value>10</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PRO_MAC_INTR_MAP</name>
+          <description>MAC_INTR interrupt configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MAC_INTR_MAP</name>
+              <description>This register is used to map MAC_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_MAC_NMI_MAP</name>
+          <description>MAC_NMI interrupt configuration register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MAC_NMI_MAP</name>
+              <description>This register is used to map MAC_NMI interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PWR_INTR_MAP</name>
+          <description>PWR_INTR interrupt configuration register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PWR_INTR_MAP</name>
+              <description>This register is used to map PWR_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BB_INT_MAP</name>
+          <description>BB_INT interrupt configuration register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_BB_INT_MAP</name>
+              <description>This register is used to map BB_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BT_MAC_INT_MAP</name>
+          <description>BT_MAC_INT interrupt configuration register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_BT_MAC_INT_MAP</name>
+              <description>This register is used to map BT_MAC_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BT_BB_INT_MAP</name>
+          <description>BT_BB_INT interrupt configuration register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_BT_BB_INT_MAP</name>
+              <description>This register is used to map BT_BB_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BT_BB_NMI_MAP</name>
+          <description>BT_BB_NMI interrupt configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_BT_BB_NMI_MAP</name>
+              <description>This register is used to map BT_BB_NMI interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RWBT_IRQ_MAP</name>
+          <description>RWBT_IRQ interrupt configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RWBT_IRQ_MAP</name>
+              <description>This register is used to map RWBT_IRQ interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RWBLE_IRQ_MAP</name>
+          <description>RWBLE_IRQ interrupt configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RWBLE_IRQ_MAP</name>
+              <description>This register is used to map RWBLE_IRQ interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RWBT_NMI_MAP</name>
+          <description>RWBT_NMI interrupt configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RWBT_NMI_MAP</name>
+              <description>This register is used to map RWBT_NMI interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RWBLE_NMI_MAP</name>
+          <description>RWBLE_NMI interrupt configuration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RWBLE_NMI_MAP</name>
+              <description>This register is used to map RWBLE_NMI interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SLC0_INTR_MAP</name>
+          <description>SLC0_INTR interrupt configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SLC0_INTR_MAP</name>
+              <description>This register is used to map SLC0_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SLC1_INTR_MAP</name>
+          <description>SLC1_INTR interrupt configuration register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SLC1_INTR_MAP</name>
+              <description>This register is used to map SLC1_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UHCI0_INTR_MAP</name>
+          <description>UHCI0_INTR interrupt configuration register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UHCI0_INTR_MAP</name>
+              <description>This register is used to map UHCI0_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UHCI1_INTR_MAP</name>
+          <description>UHCI1_INTR interrupt configuration register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UHCI1_INTR_MAP</name>
+              <description>This register is used to map UHCI1_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_T0_LEVEL_INT_MAP</name>
+          <description>TG_T0_LEVEL_INT interrupt configuration register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_T0_LEVEL_INT_MAP</name>
+              <description>This register is used to map TG_T0_LEVEL_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_T1_LEVEL_INT_MAP</name>
+          <description>TG_T1_LEVEL_INT interrupt configuration register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_T1_LEVEL_INT_MAP</name>
+              <description>This register is used to map TG_T1_LEVEL_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_WDT_LEVEL_INT_MAP</name>
+          <description>TG_WDT_LEVEL_INT interrupt configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_WDT_LEVEL_INT_MAP</name>
+              <description>This register is used to map TG_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_LACT_LEVEL_INT_MAP</name>
+          <description>TG_LACT_LEVEL_INT interrupt configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_LACT_LEVEL_INT_MAP</name>
+              <description>This register is used to map TG_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_T0_LEVEL_INT_MAP</name>
+          <description>TG1_T0_LEVEL_INT interrupt configuration register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_T0_LEVEL_INT_MAP</name>
+              <description>This register is used to map TG1_T0_LEVEL_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_T1_LEVEL_INT_MAP</name>
+          <description>TG1_T1_LEVEL_INT interrupt configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_T1_LEVEL_INT_MAP</name>
+              <description>This register is used to map TG1_T1_LEVEL_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_WDT_LEVEL_INT_MAP</name>
+          <description>TG1_WDT_LEVEL_INT interrupt configuration register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_WDT_LEVEL_INT_MAP</name>
+              <description>This register is used to map TG1_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_LACT_LEVEL_INT_MAP</name>
+          <description>TG1_LACT_LEVEL_INT interrupt configuration register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_LACT_LEVEL_INT_MAP</name>
+              <description>This register is used to map TG1_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_GPIO_INTERRUPT_PRO_MAP</name>
+          <description>GPIO_INTERRUPT_PRO interrupt configuration register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_GPIO_INTERRUPT_PRO_MAP</name>
+              <description>This register is used to map GPIO_INTERRUPT_PRO interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_GPIO_INTERRUPT_PRO_NMI_MAP</name>
+          <description>GPIO_INTERRUPT_PRO_NMI interrupt configuration register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_GPIO_INTERRUPT_PRO_NMI_MAP</name>
+              <description>This register is used to map GPIO_INTERRUPT_PRO_NMI interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_GPIO_INTERRUPT_APP_MAP</name>
+          <description>GPIO_INTERRUPT_APP interrupt configuration register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_GPIO_INTERRUPT_APP_MAP</name>
+              <description>This register is used to map GPIO_INTERRUPT_APP interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_GPIO_INTERRUPT_APP_NMI_MAP</name>
+          <description>GPIO_INTERRUPT_APP_NMI interrupt configuration register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_GPIO_INTERRUPT_APP_NMI_MAP</name>
+              <description>This register is used to map GPIO_INTERRUPT_APP_NMI interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DEDICATED_GPIO_IN_INTR_MAP</name>
+          <description>DEDICATED_GPIO_IN_INTR interrupt configuration register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DEDICATED_GPIO_IN_INTR_MAP</name>
+              <description>This register is used to map DEDICATED_GPIO_IN_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_INTR_FROM_CPU_0_MAP</name>
+          <description>CPU_INTR_FROM_CPU_0 interrupt configuration register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_INTR_FROM_CPU_0_MAP</name>
+              <description>This register is used to map CPU_INTR_FROM_CPU_0 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_INTR_FROM_CPU_1_MAP</name>
+          <description>CPU_INTR_FROM_CPU_1 interrupt configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_INTR_FROM_CPU_1_MAP</name>
+              <description>This register is used to map CPU_INTR_FROM_CPU_1 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_INTR_FROM_CPU_2_MAP</name>
+          <description>CPU_INTR_FROM_CPU_2 interrupt configuration register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_INTR_FROM_CPU_2_MAP</name>
+              <description>This register is used to map CPU_INTR_FROM_CPU_2 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_INTR_FROM_CPU_3_MAP</name>
+          <description>CPU_INTR_FROM_CPU_3 interrupt configuration register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_INTR_FROM_CPU_3_MAP</name>
+              <description>This register is used to map CPU_INTR_FROM_CPU_3 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI_INTR_1_MAP</name>
+          <description>SPI_INTR_1 interrupt configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI_INTR_1_MAP</name>
+              <description>This register is used to map SPI_INTR_1 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI_INTR_2_MAP</name>
+          <description>SPI_INTR_2 interrupt configuration register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI_INTR_2_MAP</name>
+              <description>This register is used to map SPI_INTR_2 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI_INTR_3_MAP</name>
+          <description>SPI_INTR_3 interrupt configuration register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI_INTR_3_MAP</name>
+              <description>This register is used to map SPI_INTR_3 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_I2S0_INT_MAP</name>
+          <description>I2S0_INT interrupt configuration register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I2S0_INT_MAP</name>
+              <description>This register is used to map I2S0_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_I2S1_INT_MAP</name>
+          <description>I2S1_INT interrupt configuration register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I2S1_INT_MAP</name>
+              <description>This register is used to map I2S1_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UART_INTR_MAP</name>
+          <description>UART_INT interrupt configuration register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UART_INTR_MAP</name>
+              <description>This register is used to map UART_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UART1_INTR_MAP</name>
+          <description>UART1_INT interrupt configuration register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UART1_INTR_MAP</name>
+              <description>This register is used to map UART1_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_UART2_INTR_MAP</name>
+          <description>UART2_INT interrupt configuration register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_UART2_INTR_MAP</name>
+              <description>This register is used to map UART2_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SDIO_HOST_INTERRUPT_MAP</name>
+          <description>SDIO_HOST_INTERRUPT configuration register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SDIO_HOST_INTERRUPT_MAP</name>
+              <description>This register is used to map SDIO_HOST_INTERRUPT signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PWM0_INTR_MAP</name>
+          <description>PWM0_INTR interrupt configuration register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PWM0_INTR_MAP</name>
+              <description>This register is used to map PWM0_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PWM1_INTR_MAP</name>
+          <description>PWM1_INTR interrupt configuration register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PWM1_INTR_MAP</name>
+              <description>This register is used to map PWM1_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PWM2_INTR_MAP</name>
+          <description>PWM2_INTR interrupt configuration register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PWM2_INTR_MAP</name>
+              <description>This register is used to map PWM2_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PWM3_INTR_MAP</name>
+          <description>PWM3_INTR interrupt configuration register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PWM3_INTR_MAP</name>
+              <description>This register is used to map PWM3_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_LEDC_INT_MAP</name>
+          <description>LEDC_INTR interrupt configuration register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_LEDC_INT_MAP</name>
+              <description>This register is used to map LEDC_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_EFUSE_INT_MAP</name>
+          <description>EFUSE_INT interrupt configuration register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_EFUSE_INT_MAP</name>
+              <description>This register is used to map EFUSE_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CAN_INT_MAP</name>
+          <description>CAN_INT interrupt configuration register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CAN_INT_MAP</name>
+              <description>This register is used to map CAN_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_USB_INTR_MAP</name>
+          <description>USB_INT interrupt configuration register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_USB_INTR_MAP</name>
+              <description>This register is used to map USB_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RTC_CORE_INTR_MAP</name>
+          <description>RTC_CORE_INTR interrupt configuration register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RTC_CORE_INTR_MAP</name>
+              <description>This register is used to map RTC_CORE_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RMT_INTR_MAP</name>
+          <description>RMT_INTR interrupt configuration register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RMT_INTR_MAP</name>
+              <description>This register is used to map RMT_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PCNT_INTR_MAP</name>
+          <description>PCNT_INTR interrupt configuration register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PCNT_INTR_MAP</name>
+              <description>This register is used to map PCNT_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_I2C_EXT0_INTR_MAP</name>
+          <description>I2C_EXT0_INTR interrupt configuration register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I2C_EXT0_INTR_MAP</name>
+              <description>This register is used to map I2C_EXT0_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_I2C_EXT1_INTR_MAP</name>
+          <description>I2C_EXT1_INTR interrupt configuration register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I2C_EXT1_INTR_MAP</name>
+              <description>This register is used to map I2C_EXT1_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_RSA_INTR_MAP</name>
+          <description>RSA_INTR interrupt configuration register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_RSA_INTR_MAP</name>
+              <description>This register is used to map RSA_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SHA_INTR_MAP</name>
+          <description>SHA_INTR interrupt configuration register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SHA_INTR_MAP</name>
+              <description>This register is used to map SHA_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_AES_INTR_MAP</name>
+          <description>AES_INTR interrupt configuration register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_AES_INTR_MAP</name>
+              <description>This register is used to map AES_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI2_DMA_INT_MAP</name>
+          <description>SPI2_DMA_INT interrupt configuration register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI2_DMA_INT_MAP</name>
+              <description>This register is used to map AES_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI3_DMA_INT_MAP</name>
+          <description>SPI3_DMA_INT interrupt configuration register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI3_DMA_INT_MAP</name>
+              <description>This register is used to map SPI3_DMA_INT dma interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_WDG_INT_MAP</name>
+          <description>WDG_INT interrupt configuration register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_WDG_INT_MAP</name>
+              <description>This register is used to map WDG_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TIMER_INT1_MAP</name>
+          <description>TIMER_INT1 interrupt configuration register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TIMER_INT1_MAP</name>
+              <description>This register is used to map TIMER_INT1 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TIMER_INT2_MAP</name>
+          <description>TIMER_INT2 interrupt configuration register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TIMER_INT2_MAP</name>
+              <description>This register is used to map TIMER_INT2 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_T0_EDGE_INT_MAP</name>
+          <description>TG_T0_EDGE_INT interrupt configuration register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_T0_EDGE_INT_MAP</name>
+              <description>This register is used to map TG_T0_EDGE_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_T1_EDGE_INT_MAP</name>
+          <description>TG_T1_EDGE_INT interrupt configuration register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_T1_EDGE_INT_MAP</name>
+              <description>This register is used to map TG_T1_EDGE_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_WDT_EDGE_INT_MAP</name>
+          <description>TG_WDT_EDGE_INT interrupt configuration register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_WDT_EDGE_INT_MAP</name>
+              <description>This register is used to map TG_WDT_EDGE_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG_LACT_EDGE_INT_MAP</name>
+          <description>TG_LACT_EDGE_INT interrupt configuration register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG_LACT_EDGE_INT_MAP</name>
+              <description>This register is used to map TG_LACT_EDGE_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_T0_EDGE_INT_MAP</name>
+          <description>TG1_T0_EDGE_INT interrupt configuration register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_T0_EDGE_INT_MAP</name>
+              <description>This register is used to map TG1_T0_EDGE_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_T1_EDGE_INT_MAP</name>
+          <description>TG1_T1_EDGE_INT interrupt configuration register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_T1_EDGE_INT_MAP</name>
+              <description>This register is used to map TG1_T1_EDGE_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_WDT_EDGE_INT_MAP</name>
+          <description>TG1_WDT_EDGE_INT interrupt configuration register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_WDT_EDGE_INT_MAP</name>
+              <description>This register is used to map TG1_WDT_EDGE_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TG1_LACT_EDGE_INT_MAP</name>
+          <description>TG1_LACT_EDGE_INT interrupt configuration register</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_TG1_LACT_EDGE_INT_MAP</name>
+              <description>This register is used to map TG1_LACT_EDGE_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_IA_INT_MAP</name>
+          <description>CACHE_IA_INT interrupt configuration register</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CACHE_IA_INT_MAP</name>
+              <description>This register is used to map CACHE_IA_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SYSTIMER_TARGET0_INT_MAP</name>
+          <description>SYSTIMER_TARGET0_INT interrupt configuration register</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SYSTIMER_TARGET0_INT_MAP</name>
+              <description>This register is used to map SYSTIMER_TARGET0_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SYSTIMER_TARGET1_INT_MAP</name>
+          <description>SYSTIMER_TARGET1_INT interrupt configuration register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SYSTIMER_TARGET1_INT_MAP</name>
+              <description>This register is used to map SYSTIMER_TARGET1_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SYSTIMER_TARGET2_INT_MAP</name>
+          <description>SYSTIMER_TARGET2_INT interrupt configuration register</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SYSTIMER_TARGET2_INT_MAP</name>
+              <description>This register is used to map SYSTIMER_TARGET2_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ASSIST_DEBUG_INTR_MAP</name>
+          <description>ASSIST_DEBUG_INTR interrupt configuration register</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ASSIST_DEBUG_INTR_MAP</name>
+              <description>This register is used to map ASSIST_DEBUG_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PMS_PRO_IRAM0_ILG_INTR_MAP</name>
+          <description>PMS_PRO_IRAM0_ILG interrupt configuration register</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PMS_PRO_IRAM0_ILG_INTR_MAP</name>
+              <description>This register is used to map PMS_PRO_IRAM0_ILG interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PMS_PRO_DRAM0_ILG_INTR_MAP</name>
+          <description>PMS_PRO_DRAM0_ILG interrupt configuration register</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PMS_PRO_DRAM0_ILG_INTR_MAP</name>
+              <description>This register is used to map PMS_PRO_DRAM0_ILG interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PMS_PRO_DPORT_ILG_INTR_MAP</name>
+          <description>PMS_PRO_DPORT_ILG interrupt configuration register</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PMS_PRO_DPORT_ILG_INTR_MAP</name>
+              <description>This register is used to map PMS_PRO_DPORT_ILG interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PMS_PRO_AHB_ILG_INTR_MAP</name>
+          <description>PMS_PRO_AHB_ILG interrupt configuration register</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PMS_PRO_AHB_ILG_INTR_MAP</name>
+              <description>This register is used to map PMS_PRO_AHB_ILG interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PMS_PRO_CACHE_ILG_INTR_MAP</name>
+          <description>PMS_PRO_CACHE_ILG interrupt configuration register</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PMS_PRO_CACHE_ILG_INTR_MAP</name>
+              <description>This register is used to map PMS_PRO_CACHE_ILG interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PMS_DMA_APB_I_ILG_INTR_MAP</name>
+          <description>PMS_DMA_APB_I_ILG  interrupt configuration register</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PMS_DMA_APB_I_ILG_INTR_MAP</name>
+              <description>This register is used to map PMS_DMA_APB_I_ILG interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PMS_DMA_RX_I_ILG_INTR_MAP</name>
+          <description>PMS_DMA_RX_I_ILG interrupt configuration register</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PMS_DMA_RX_I_ILG_INTR_MAP</name>
+              <description>This register is used to map PMS_DMA_RX_I_ILG interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_PMS_DMA_TX_I_ILG_INTR_MAP</name>
+          <description>PMS_DMA_TX_I_ILG interrupt configuration register</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_PMS_DMA_TX_I_ILG_INTR_MAP</name>
+              <description>This register is used to map PMS_DMA_TX_I_ILG interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI_MEM_REJECT_INTR_MAP</name>
+          <description>SPI_MEM_REJECT_INTR interrupt configuration register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI_MEM_REJECT_INTR_MAP</name>
+              <description>This register is used to map SPI_MEM_REJECT_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DMA_COPY_INTR_MAP</name>
+          <description>DMA_COPY_INTR interrupt configuration register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DMA_COPY_INTR_MAP</name>
+              <description>This register is used to map DMA_COPY_INTR interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI4_DMA_INT_MAP</name>
+          <description>SPI4_DMA_INT interrupt configuration register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI4_DMA_INT_MAP</name>
+              <description>This register is used to map SPI4_DMA_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_SPI_INTR_4_MAP</name>
+          <description>SPI_INTR_4 interrupt configuration register</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_SPI_INTR_4_MAP</name>
+              <description>This register is used to map SPI_INTR_4 interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_PRELOAD_INT_MAP</name>
+          <description>DCACHE_PRELOAD_INT interrupt configuration register</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_PRELOAD_INT_MAP</name>
+              <description>This register is used to map DCACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_PRELOAD_INT_MAP</name>
+          <description>ICACHE_PRELOAD_INT interrupt configuration register</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_PRELOAD_INT_MAP</name>
+              <description>This register is used to map ICACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_APB_ADC_INT_MAP</name>
+          <description>APB_ADC_INT interrupt configuration register</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_APB_ADC_INT_MAP</name>
+              <description>This register is used to map APB_ADC_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CRYPTO_DMA_INT_MAP</name>
+          <description>CRYPTO_DMA_INT interrupt configuration register</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CRYPTO_DMA_INT_MAP</name>
+              <description>This register is used to map CRYPTO_DMA_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CPU_PERI_ERROR_INT_MAP</name>
+          <description>CPU_PERI_ERROR_INT interrupt configuration register</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_CPU_PERI_ERROR_INT_MAP</name>
+              <description>This register is used to map CPU_PERI_ERROR_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_APB_PERI_ERROR_INT_MAP</name>
+          <description>APB_PERI_ERROR_INT interrupt configuration register</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_APB_PERI_ERROR_INT_MAP</name>
+              <description>This register is used to map APB_PERI_ERROR_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DCACHE_SYNC_INT_MAP</name>
+          <description>DCACHE_SYNC_INT interrupt configuration register</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DCACHE_SYNC_INT_MAP</name>
+              <description>This register is used to map DCACHE_SYNC_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_ICACHE_SYNC_INT_MAP</name>
+          <description>ICACHE_SYNC_INT interrupt configuration register</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_SYNC_INT_MAP</name>
+              <description>This register is used to map ICACHE_SYNC_INT interrupt signal to one of the CPU interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_0</name>
+          <description>Interrupt status register 0</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_INTR_STATUS_0</name>
+              <description>This register stores the status of the first 32 input interrupt sources.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_1</name>
+          <description>Interrupt status register 1</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_INTR_STATUS_1</name>
+              <description>This register stores the status of the second 32 input interrupt sources.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_2</name>
+          <description>Interrupt status register 2</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_INTR_STATUS_2</name>
+              <description>This register stores the status of the last 31 input interrupt sources.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>NMI interrupt signals mask register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_NMI_MASK_HW</name>
+              <description>This bit is used to disable all NMI interrupt signals to CPU.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01904180</resetValue>
+          <fields>
+            <field>
+              <name>INTERRUPT_REG_DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>IO_MUX</name>
+      <description>Input/Output Multiplexer</description>
+      <groupName>IO_MUX</groupName>
+      <baseAddress>0x3F409000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PIN_CTRL</name>
+          <description>Clock output configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000027FF</resetValue>
+          <fields>
+            <field>
+              <name>PIN_CLK_OUT1</name>
+              <description>Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PIN_CLK_OUT2</name>
+              <description>Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PIN_CLK_OUT3</name>
+              <description>Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWITCH_PRT_NUM</name>
+              <description>IO pin power switch delay, delay unit is one APB clock.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_POWER_CTRL</name>
+              <description>Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO0</name>
+          <description>Configuration register for pin GPIO0</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO1</name>
+          <description>Configuration register for pin GPIO1</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO2</name>
+          <description>Configuration register for pin GPIO2</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO3</name>
+          <description>Configuration register for pin GPIO3</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO4</name>
+          <description>Configuration register for pin GPIO4</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO5</name>
+          <description>Configuration register for pin GPIO5</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO6</name>
+          <description>Configuration register for pin GPIO6</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO7</name>
+          <description>Configuration register for pin GPIO7</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO8</name>
+          <description>Configuration register for pin GPIO8</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO9</name>
+          <description>Configuration register for pin GPIO9</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO10</name>
+          <description>Configuration register for pin GPIO10</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO11</name>
+          <description>Configuration register for pin GPIO11</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO12</name>
+          <description>Configuration register for pin GPIO12</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO13</name>
+          <description>Configuration register for pin GPIO13</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO14</name>
+          <description>Configuration register for pin GPIO14</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO19</name>
+          <description>Configuration register for pin GPIO19</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO20</name>
+          <description>Configuration register for pin GPIO20</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO21</name>
+          <description>Configuration register for pin GPIO21</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO33</name>
+          <description>Configuration register for pin GPIO33</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO34</name>
+          <description>Configuration register for pin GPIO34</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO35</name>
+          <description>Configuration register for pin GPIO35</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO36</name>
+          <description>Configuration register for pin GPIO36</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO37</name>
+          <description>Configuration register for pin GPIO37</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO38</name>
+          <description>Configuration register for pin GPIO38</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO45</name>
+          <description>Configuration register for pin GPIO45</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO46</name>
+          <description>Configuration register for pin GPIO46</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01907160</resetValue>
+          <fields>
+            <field>
+              <name>VERSION</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO15</name>
+          <description>Configuration register for pin GPIO15</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO16</name>
+          <description>Configuration register for pin GPIO16</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO17</name>
+          <description>Configuration register for pin GPIO17</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO18</name>
+          <description>Configuration register for pin GPIO18</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO26</name>
+          <description>Configuration register for pin GPIO26</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO27</name>
+          <description>Configuration register for pin GPIO27</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO28</name>
+          <description>Configuration register for pin GPIO28</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO29</name>
+          <description>Configuration register for pin GPIO29</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO30</name>
+          <description>Configuration register for pin GPIO30</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO31</name>
+          <description>Configuration register for pin GPIO31</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO32</name>
+          <description>Configuration register for pin GPIO32</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO39</name>
+          <description>Configuration register for pin GPIO39</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO40</name>
+          <description>Configuration register for pin GPIO40</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO41</name>
+          <description>Configuration register for pin GPIO41</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO42</name>
+          <description>Configuration register for pin GPIO42</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO43</name>
+          <description>Configuration register for pin GPIO43</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO44</name>
+          <description>Configuration register for pin GPIO44</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pin. 1: Input enabled. 0: Input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LEDC</name>
+      <description>LED PWM (Pulse Width Modulation) Controller</description>
+      <groupName>LEDC</groupName>
+      <baseAddress>0x3F419000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xD8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LEDC</name>
+        <value>45</value>
+      </interrupt>
+      <interrupt>
+        <name>TIMER1</name>
+        <value>60</value>
+      </interrupt>
+      <interrupt>
+        <name>TIMER2</name>
+        <value>61</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF0</name>
+          <description>Configuration register 0 for channel %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SEL</name>
+              <description>This field is used to select one of timers for channel %s.
+
+0: select timer 0.
+
+1: select timer 1.
+
+2: select timer 2.
+
+3: select timer 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_OUT_EN</name>
+              <description>Set this bit to enable signal output on channel %s.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_LV</name>
+              <description>This bit is used to control the output value when channel %s is inactive.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>This bit is used to update register LEDC_CH%s_HPOINT and LEDC_CH%s_DUTY for channel %s.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_NUM</name>
+              <description>This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_EN</name>
+              <description>This bit is used to enable the ovf_cnt of channel %s.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_RESET</name>
+              <description>Set this bit to reset the ovf_cnt of channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_RESET_ST</name>
+              <description>This is the status bit of LEDC_OVF_CNT_RESET_CH%s.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_HPOINT</name>
+          <description>High point register for channel %s</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HPOINT</name>
+              <description>The output value changes to high when the selected timers has reached the value specified by this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY</name>
+          <description>Initial duty cycle for channel %s</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY</name>
+              <description>This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF1</name>
+          <description>Configuration register 1 for channel %s</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_SCALE</name>
+              <description>This register is used to configure the changing step scale of duty on channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CYCLE</name>
+              <description>The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_NUM</name>
+              <description>This register is used to control the number of times the duty cycle will be changed.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_INC</name>
+              <description>This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase. 0: Decrease.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_START</name>
+              <description>Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY_R</name>
+          <description>Current duty cycle for channel %s</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_R</name>
+              <description>This register stores the current duty of output signal on channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_CONF</name>
+          <description>Timer %s configuration</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_RES</name>
+              <description>This register is used to control the range of the counter in timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DIV</name>
+              <description>This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAUSE</name>
+              <description>This bit is used to suspend the counter in timer %s.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>This bit is used to reset timer %s. The counter will show 0 after reset.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_SEL</name>
+              <description>This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 0: LEDC_PWM_CLK. 1: REF_TICK.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_VALUE</name>
+          <description>Timer %s current counter value</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>This register stores the current counter value of timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_RAW</name>
+              <description>Triggered when the timer0 has reached its maximum counter value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_RAW</name>
+              <description>Triggered when the timer1 has reached its maximum counter value.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_RAW</name>
+              <description>Triggered when the timer2 has reached its maximum counter value.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_RAW</name>
+              <description>Triggered when the timer3 has reached its maximum counter value.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH6_INT_RAW</name>
+              <description>Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH7_INT_RAW</name>
+              <description>Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH6_INT_RAW</name>
+              <description>Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH7_INT_RAW</name>
+              <description>Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH6_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt when LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH7_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt when LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH6_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH7_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH6_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH7_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH6_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH7_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH6_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH7_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH6_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH7_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>Global ledc configuration register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_CLK_SEL</name>
+              <description>This bit is used to select clock source for the 4 timers . 1: APB_CLK. 2: RTC8M_CLK. 3: XTAL_CLK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>This bit is used to control clock. 1: Force clock on for register. 0: Support clock only when application writes registers.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19072601</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PCNT</name>
+      <description>Pulse Count Controller</description>
+      <groupName>PCNT</groupName>
+      <baseAddress>0x3F417000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PCNT</name>
+        <value>51</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF0</name>
+          <description>Configuration register 0 for unit %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U0</name>
+              <description>This sets the maximum threshold, in APB_CLK cycles, for the filter.
+Any pulses with width less than this will be ignored when the filter is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U0</name>
+              <description>This is the enable bit for unit %s's input filter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U0</name>
+              <description>This is the enable bit for unit %s's zero comparator.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U0</name>
+              <description>This is the enable bit for unit %s's thr_h_lim comparator.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U0</name>
+              <description>This is the enable bit for unit %s's thr_l_lim comparator.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U0</name>
+              <description>This is the enable bit for unit %s's thres0 comparator.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U0</name>
+              <description>This is the enable bit for unit %s's thres1 comparator.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U0</name>
+              <description>This register sets the behavior when the signal input of channel 0 detects a negative edge.
+1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U0</name>
+              <description>This register sets the behavior when the signal input of channel 0 detects a positive edge.
+1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U0</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.
+0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U0</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.
+0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U0</name>
+              <description>This register sets the behavior when the signal input of channel 1 detects a negative edge.
+1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U0</name>
+              <description>This register sets the behavior when the signal input of channel 1 detects a positive edge.
+1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U0</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.
+0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U0</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.
+0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF1</name>
+          <description>Configuration register 1 for unit %s</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U0</name>
+              <description>This register is used to configure the thres0 value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U0</name>
+              <description>This register is used to configure the thres1 value for unit %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF2</name>
+          <description>Configuration register 2 for unit %s</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U0</name>
+              <description>This register is used to configure the thr_h_lim value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U0</name>
+              <description>This register is used to configure the thr_l_lim value for unit %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>U%s_CNT</name>
+          <description>Counter value for unit %s</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PULSE_CNT_U0</name>
+              <description>This register stores the current pulse count value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt raw status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Interrupt status register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>U%s_STATUS</name>
+          <description>PNCT UNIT%s status register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_ZERO_MODE_U0</name>
+              <description>The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_THRES1_LAT_U0</name>
+              <description>The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_THRES0_LAT_U0</name>
+              <description>The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_L_LIM_LAT_U0</name>
+              <description>The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_H_LIM_LAT_U0</name>
+              <description>The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_ZERO_LAT_U0</name>
+              <description>The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>Control register for all counters</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000055</resetValue>
+          <fields>
+            <field>
+              <name>PULSE_CNT_RST_U0</name>
+              <description>Set this bit to clear unit 0's counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U0</name>
+              <description>Set this bit to freeze unit 1's counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U1</name>
+              <description>Set this bit to clear unit 2's counter.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U1</name>
+              <description>Set this bit to freeze unit 3's counter.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U2</name>
+              <description>Set this bit to clear unit 4's counter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U2</name>
+              <description>Set this bit to freeze unit 5's counter.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U3</name>
+              <description>Set this bit to clear unit 6's counter.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U3</name>
+              <description>Set this bit to freeze unit 7's counter.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>PCNT version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19072601</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the PCNT version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PMS</name>
+      <description>Permissions Controller</description>
+      <groupName>PMS</groupName>
+      <baseAddress>0x3F4C1000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x10C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SDIO_0</name>
+          <description>SDIO permission control register 0.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_LOCK</name>
+              <description>Lock register. Setting to 1 locks SDIO permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_1</name>
+          <description>SDIO permission control register 1.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_DISABLE</name>
+              <description>Setting to 1 disables the SDIO function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAC_DUMP_0</name>
+          <description>MAC dump permission control register 0.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_DUMP_LOCK</name>
+              <description>Lock register. Setting to 1 locks MAC dump permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAC_DUMP_1</name>
+          <description>MAC dump permission control register 1.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000E4</resetValue>
+          <fields>
+            <field>
+              <name>MAC_DUMP_CONNECT</name>
+              <description>Configure MAC dump connection.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_IRAM0_0</name>
+          <description>IBUS permission control register 0.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_IRAM0_LOCK</name>
+              <description>Lock register. Setting to 1 locks IBUS permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_IRAM0_1</name>
+          <description>IBUS permission control register 1.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>PRO_IRAM0_SRAM_0_F</name>
+              <description>Setting to 1 grants IBUS permission to fetch SRAM Block 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_0_R</name>
+              <description>Setting to 1 grants IBUS permission to read SRAM Block 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_0_W</name>
+              <description>Setting to 1 grants IBUS permission to write SRAM Block 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_1_F</name>
+              <description>Setting to 1 grants IBUS permission to fetch SRAM Block 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_1_R</name>
+              <description>Setting to 1 grants IBUS permission to read SRAM Block 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_1_W</name>
+              <description>Setting to 1 grants IBUS permission to write SRAM Block 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_2_F</name>
+              <description>Setting to 1 grants IBUS permission to fetch SRAM Block 2.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_2_R</name>
+              <description>Setting to 1 grants IBUS permission to read SRAM Block 2.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_2_W</name>
+              <description>Setting to 1 grants IBUS permission to write SRAM Block 2.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_3_F</name>
+              <description>Setting to 1 grants IBUS permission to fetch SRAM Block 3.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_3_R</name>
+              <description>Setting to 1 grants IBUS permission to read SRAM Block 3.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_3_W</name>
+              <description>Setting to 1 grants IBUS permission to write SRAM Block 3.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_IRAM0_2</name>
+          <description>IBUS permission control register 2.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x007E0000</resetValue>
+          <fields>
+            <field>
+              <name>PRO_IRAM0_SRAM_4_SPLTADDR</name>
+              <description>Configure the split address of SRAM Block 4-21 for IBUS access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_4_L_F</name>
+              <description>Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 low address region.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_4_L_R</name>
+              <description>Setting to 1 grants IBUS permission to read SRAM Block 4-21 low address region.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_4_L_W</name>
+              <description>Setting to 1 grants IBUS permission to write SRAM Block 4-21 low address region.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_4_H_F</name>
+              <description>Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 high address region.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_4_H_R</name>
+              <description>Setting to 1 grants IBUS permission to read SRAM Block 4-21 high address region.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_SRAM_4_H_W</name>
+              <description>Setting to 1 grants IBUS permission to write SRAM Block 4-21 high address region.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_IRAM0_3</name>
+          <description>IBUS permission control register 3.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001F800</resetValue>
+          <fields>
+            <field>
+              <name>PRO_IRAM0_RTCFAST_SPLTADDR</name>
+              <description>Configure the split address of RTC FAST for IBUS access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_RTCFAST_L_F</name>
+              <description>Setting to 1 grants IBUS permission to fetch RTC FAST low address region.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_RTCFAST_L_R</name>
+              <description>Setting to 1 grants IBUS permission to read RTC FAST low address region.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_RTCFAST_L_W</name>
+              <description>Setting to 1 grants IBUS permission to write RTC FAST low address region.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_RTCFAST_H_F</name>
+              <description>Setting to 1 grants IBUS permission to fetch RTC FAST high address region.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_RTCFAST_H_R</name>
+              <description>Setting to 1 grants IBUS permission to read RTC FAST high address region.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_RTCFAST_H_W</name>
+              <description>Setting to 1 grants IBUS permission to write RTC FAST high address region.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_IRAM0_4</name>
+          <description>IBUS permission control register 4.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_IRAM0_ILG_CLR</name>
+              <description>The clear signal for IBUS access interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_ILG_EN</name>
+              <description>The enable signal for IBUS access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_IRAM0_ILG_INTR</name>
+              <description>IBUS access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_IRAM0_5</name>
+          <description>IBUS status register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_IRAM0_ILG_ST</name>
+              <description>Record the illegitimate information of IBUS. [21:2]: store the bits [21:2] of IBUS address. [1]: 1 means data access, 0 means instruction access. [0]: 1 means write operation, 0 means read operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DRAM0_0</name>
+          <description>DBUS permission control register 0.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DRAM0_LOCK</name>
+              <description>Lock register. Setting to 1 locks DBUS0 permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DRAM0_1</name>
+          <description>DBUS permission control register 1.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1E0000FF</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DRAM0_SRAM_0_R</name>
+              <description>Setting to 1 grants DBUS0 permission to read SRAM Block 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_0_W</name>
+              <description>Setting to 1 grants DBUS0 permission to write SRAM Block 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_1_R</name>
+              <description>Setting to 1 grants DBUS0 permission to read SRAM Block 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_1_W</name>
+              <description>Setting to 1 grants DBUS0 permission to write SRAM Block 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_2_R</name>
+              <description>Setting to 1 grants DBUS0 permission to read SRAM Block 2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_2_W</name>
+              <description>Setting to 1 grants DBUS0 permission to write SRAM Block 2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_3_R</name>
+              <description>Setting to 1 grants DBUS0 permission to read SRAM Block 3.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_3_W</name>
+              <description>Setting to 1 grants DBUS0 permission to write SRAM Block 3.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_4_SPLTADDR</name>
+              <description>Configure the split address of SRAM Block 4-21 for DBUS0 access.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_4_L_R</name>
+              <description>Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 low address region.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_4_L_W</name>
+              <description>Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 low address region.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_4_H_R</name>
+              <description>Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 high address region.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_SRAM_4_H_W</name>
+              <description>Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 high address region.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DRAM0_2</name>
+          <description>DBUS permission control register 2.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00007800</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DRAM0_RTCFAST_SPLTADDR</name>
+              <description>Configure the split address of RTC FAST for DBUS0 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_RTCFAST_L_R</name>
+              <description>Setting to 1 grants DBUS0 permission to read RTC FAST low address region.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_RTCFAST_L_W</name>
+              <description>Setting to 1 grants DBUS0 permission to write RTC FAST low address region.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_RTCFAST_H_R</name>
+              <description>Setting to 1 grants DBUS0 permission to read RTC FAST high address region.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_RTCFAST_H_W</name>
+              <description>Setting to 1 grants DBUS0 permission to write RTC FAST high address region.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DRAM0_3</name>
+          <description>DBUS permission control register 3.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DRAM0_ILG_CLR</name>
+              <description>The clear signal for DBUS0 access interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_ILG_EN</name>
+              <description>The enable signal for DBUS0 access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRAM0_ILG_INTR</name>
+              <description>DBUS0 access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DRAM0_4</name>
+          <description>DBUS status register.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DRAM0_ILG_ST</name>
+              <description>Record the illegitimate information of DBUS. [25:6]: store the bits [21:2] of DBUS address. [5]: 1 means atomic access, 0 means nonatomic access. [4]: 1 means write operation, 0 means read operation. [3:0]: DBUS0 bus byte enables.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_0</name>
+          <description>PeriBus1 permission control register 0.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DPORT_LOCK</name>
+              <description>Lock register. Setting to 1 locks PeriBus1 permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_1</name>
+          <description>PeriBus1 permission control register 1.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000F000</resetValue>
+          <fields>
+            <field>
+              <name>PRO_DPORT_APB_PERIPHERAL_FORBID</name>
+              <description>Setting to 1 denies PeriBus1 bus???s access to APB peripheral.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DPORT_RTCSLOW_SPLTADDR</name>
+              <description>Configure the split address of RTC FAST for PeriBus1 access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DPORT_RTCSLOW_L_R</name>
+              <description>Setting to 1 grants PeriBus1 permission to read RTC FAST low address region.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DPORT_RTCSLOW_L_W</name>
+              <description>Setting to 1 grants PeriBus1 permission to write RTC FAST low address region.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DPORT_RTCSLOW_H_R</name>
+              <description>Setting to 1 grants PeriBus1 permission to read RTC FAST high address region.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DPORT_RTCSLOW_H_W</name>
+              <description>Setting to 1 grants PeriBus1 permission to write RTC FAST high address region.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DPORT_RESERVE_FIFO_VALID</name>
+              <description>Configure whether to enable read protection for user-configured FIFO address.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_2</name>
+          <description>PeriBus1 permission control register 2.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DPORT_RESERVE_FIFO_0</name>
+              <description>Configure read-protection address 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_3</name>
+          <description>PeriBus1 permission control register 3.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DPORT_RESERVE_FIFO_1</name>
+              <description>Configure read-protection address 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_4</name>
+          <description>PeriBus1 permission control register 4.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DPORT_RESERVE_FIFO_2</name>
+              <description>Configure read-protection address 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_5</name>
+          <description>PeriBus1 permission control register 5.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DPORT_RESERVE_FIFO_3</name>
+              <description>Configure read-protection address 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_6</name>
+          <description>PeriBus1 permission control register 6.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DPORT_ILG_CLR</name>
+              <description>The clear signal for PeriBus1 access interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DPORT_ILG_EN</name>
+              <description>The enable signal for PeriBus1 access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DPORT_ILG_INTR</name>
+              <description>PeriBus1 access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_DPORT_7</name>
+          <description>PeriBus1 status register.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_DPORT_ILG_ST</name>
+              <description>Record the illegitimate information of PeriBus1. [25:6]: store the bits [21:2] of PeriBus1 address. [5]: 1 means atomic access, 0 means nonatomic access. [4]: if bits [31:22] of PeriBus1 address are 0xfd, then the bit value is 1, otherwise it is 0. [3:0]: PeriBus1 byte enables.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_AHB_0</name>
+          <description>PeriBus2 permission control register 0.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_AHB_LOCK</name>
+              <description>Lock register. Setting to 1 locks PeriBus2 permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_AHB_1</name>
+          <description>PeriBus2 permission control register 1.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001F800</resetValue>
+          <fields>
+            <field>
+              <name>PRO_AHB_RTCSLOW_0_SPLTADDR</name>
+              <description>Configure the split address of RTCSlow_0 for PeriBus2 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_0_L_F</name>
+              <description>Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 low address region.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_0_L_R</name>
+              <description>Setting to 1 grants PeriBus2 permission to read RTCSlow_0 low address region.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_0_L_W</name>
+              <description>Setting to 1 grants PeriBus2 permission to write RTCSlow_0 low address region.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_0_H_F</name>
+              <description>Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 high address region.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_0_H_R</name>
+              <description>Setting to 1 grants PeriBus2 permission to read RTCSlow_0 high address region.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_0_H_W</name>
+              <description>Setting to 1 grants PeriBus2 permission to write RTCSlow_0 high address region.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_AHB_2</name>
+          <description>PeriBus2 permission control register 2.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001F800</resetValue>
+          <fields>
+            <field>
+              <name>PRO_AHB_RTCSLOW_1_SPLTADDR</name>
+              <description>Configure the split address of RTCSlow_1 for PeriBus2 access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_1_L_F</name>
+              <description>Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 low address region.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_1_L_R</name>
+              <description>Setting to 1 grants PeriBus2 permission to read RTCSlow_1 low address region.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_1_L_W</name>
+              <description>Setting to 1 grants PeriBus2 permission to write RTCSlow_1 low address region.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_1_H_F</name>
+              <description>Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 high address region.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_1_H_R</name>
+              <description>Setting to 1 grants PeriBus2 permission to read RTCSlow_1 high address region.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_RTCSLOW_1_H_W</name>
+              <description>Setting to 1 grants PeriBus2 permission to write RTCSlow_1 high address region.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_AHB_3</name>
+          <description>PeriBus2 permission control register 3.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_AHB_ILG_CLR</name>
+              <description>The clear signal for PeriBus2 access interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_ILG_EN</name>
+              <description>The enable signal for PeriBus2 access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_AHB_ILG_INTR</name>
+              <description>PeriBus2 access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_AHB_4</name>
+          <description>PeriBus2 status register.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_AHB_ILG_ST</name>
+              <description>Record the illegitimate information of PeriBus2. [31:2]: store the bits [31:2] of PeriBus2 address. [1]: 1 means data access, 0 means instruction access. [0]: 1 means write operation, 0 means read operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TRACE_0</name>
+          <description>Trace memory permission control register 0.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_TRACE_LOCK</name>
+              <description>Lock register. Setting to 1 locks trace function permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_TRACE_1</name>
+          <description>Trace memory permission control register 1.</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_TRACE_DISABLE</name>
+              <description>Setting to 1 disables the trace memory function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_0</name>
+          <description>Cache permission control register 0.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_LOCK</name>
+              <description>Lock register. Setting to 1 locks cache permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_1</name>
+          <description>Cache permission control register 1.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_CONNECT</name>
+              <description>Configure which SRAM Block will be occupied by Icache or Dcache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_2</name>
+          <description>Cache permission control register 2.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_ILG_CLR</name>
+              <description>The clear signal for cache access interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_ILG_EN</name>
+              <description>The enable signal for cache access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_ILG_INTR</name>
+              <description>Cache access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_3</name>
+          <description>Icache status register.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_ILG_ST_I</name>
+              <description>Record the illegitimate information of ICache to access memory. [16]: access enable, active low. [15:4]: store the bits [11:0] of address. [3:0]: Icache bus write byte enables, active low.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_CACHE_4</name>
+          <description>Dcache status register.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_ILG_ST_D</name>
+              <description>Record the illegitimate information of Dcache to access memory. [16]: access enable, active low. [15:4]: store the bits [11:0] of address. [3:0]: Dcache bus write byte enables, active low.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APB_I_0</name>
+          <description>Internal DMA permission control register 0.</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APB_I_LOCK</name>
+              <description>Lock register. Setting to 1 locks internal DMA permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APB_I_1</name>
+          <description>Internal DMA permission control register 1.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1E0000FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APB_I_SRAM_0_R</name>
+              <description>Setting to 1 grants internal DMA permission to read SRAM Block 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_0_W</name>
+              <description>Setting to 1 grants internal DMA permission to write SRAM Block 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_1_R</name>
+              <description>Setting to 1 grants internal DMA permission to read SRAM Block 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_1_W</name>
+              <description>Setting to 1 grants internal DMA permission to write SRAM Block 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_2_R</name>
+              <description>Setting to 1 grants internal DMA permission to read SRAM Block 2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_2_W</name>
+              <description>Setting to 1 grants internal DMA permission to write SRAM Block 2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_3_R</name>
+              <description>Setting to 1 grants internal DMA permission to read SRAM Block 3.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_3_W</name>
+              <description>Setting to 1 grants internal DMA permission to write SRAM Block 3.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_4_SPLTADDR</name>
+              <description>Configure the split address of SRAM Block 4-21 for internal DMA access.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_4_L_R</name>
+              <description>Setting to 1 grants internal DMA permission to read SRAM Block 4-21 low address region.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_4_L_W</name>
+              <description>Setting to 1 grants internal DMA permission to write SRAM Block 4-21 low address region.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_4_H_R</name>
+              <description>Setting to 1 grants internal DMA permission to read SRAM Block 4-21 high address region.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_SRAM_4_H_W</name>
+              <description>Setting to 1 grants internal DMA permission to write SRAM Block 4-21 high address region.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APB_I_2</name>
+          <description>Internal DMA permission control register 2.</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APB_I_ILG_CLR</name>
+              <description>The clear signal for internal DMA access interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_ILG_EN</name>
+              <description>The enable signal for internal DMA access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APB_I_ILG_INTR</name>
+              <description>Internal DMA access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APB_I_3</name>
+          <description>Internal DMA status register.</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APB_I_ILG_ST</name>
+              <description>Record the illegitimate information of Internal DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: Internal DMA bus byte enables.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_RX_I_0</name>
+          <description>RX Copy DMA permission control register 0.</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_RX_I_LOCK</name>
+              <description>Lock register. Setting to 1 locks RX Copy DMA permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_RX_I_1</name>
+          <description>RX Copy DMA permission control register 1.</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1E0000FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_RX_I_SRAM_0_R</name>
+              <description>Setting to 1 grants RX Copy DMA permission to read SRAM Block 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_0_W</name>
+              <description>Setting to 1 grants RX Copy DMA permission to write SRAM Block 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_1_R</name>
+              <description>Setting to 1 grants RX Copy DMA permission to read SRAM Block 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_1_W</name>
+              <description>Setting to 1 grants RX Copy DMA permission to write SRAM Block 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_2_R</name>
+              <description>Setting to 1 grants RX Copy DMA permission to read SRAM Block 2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_2_W</name>
+              <description>Setting to 1 grants RX Copy DMA permission to write SRAM Block 2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_3_R</name>
+              <description>Setting to 1 grants RX Copy DMA permission to read SRAM Block 3.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_3_W</name>
+              <description>Setting to 1 grants RX Copy DMA permission to write SRAM Block 3.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_4_SPLTADDR</name>
+              <description>Configure the split address of SRAM Block 4-21 for RX Copy DMA access.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_4_L_R</name>
+              <description>Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 low address region.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_4_L_W</name>
+              <description>Setting to 1 grants RX Copy DMA permission to write SRAM Block 4-21 low address region.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_4_H_R</name>
+              <description>Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 high address region.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_SRAM_4_H_W</name>
+              <description>Setting to 1 grants RX Copy DMA permission to write SRAM Block 4~21 high address region.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_RX_I_2</name>
+          <description>RX Copy DMA permission control register 2.</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_RX_I_ILG_CLR</name>
+              <description>The clear signal for RX Copy DMA access interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_ILG_EN</name>
+              <description>The enable signal for RX Copy DMA access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_I_ILG_INTR</name>
+              <description>RX Copy DMA access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_RX_I_3</name>
+          <description>RX Copy DMA status register.</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_RX_I_ILG_ST</name>
+              <description>Record the illegitimate information of RX Copy DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: RX Copy DMA bus byte enables.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_TX_I_0</name>
+          <description>TX Copy DMA permission control register 0.</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_TX_I_LOCK</name>
+              <description>Lock register. Setting to 1 locks TX Copy DMA permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_TX_I_1</name>
+          <description>TX Copy DMA permission control register 1.</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1E0000FF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_TX_I_SRAM_0_R</name>
+              <description>Setting to 1 grants TX Copy DMA permission to read SRAM Block 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_0_W</name>
+              <description>Setting to 1 grants TX Copy DMA permission to write SRAM Block 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_1_R</name>
+              <description>Setting to 1 grants TX Copy DMA permission to read SRAM Block 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_1_W</name>
+              <description>Setting to 1 grants TX Copy DMA permission to write SRAM Block 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_2_R</name>
+              <description>Setting to 1 grants TX Copy DMA permission to read SRAM Block 2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_2_W</name>
+              <description>Setting to 1 grants TX Copy DMA permission to write SRAM Block 2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_3_R</name>
+              <description>Setting to 1 grants TX Copy DMA permission to read SRAM Block 3.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_3_W</name>
+              <description>Setting to 1 grants TX Copy DMA permission to write SRAM Block 3.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_4_SPLTADDR</name>
+              <description>Configure the split address of SRAM Block 4-21 for TX Copy DMA access.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_4_L_R</name>
+              <description>Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 low address region.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_4_L_W</name>
+              <description>Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 low address region.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_4_H_R</name>
+              <description>Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 high address region.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_SRAM_4_H_W</name>
+              <description>Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 high address region.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_TX_I_2</name>
+          <description>TX Copy DMA permission control register 2.</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_TX_I_ILG_CLR</name>
+              <description>The clear signal for TX Copy DMA access interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_ILG_EN</name>
+              <description>The enable signal for TX Copy DMA access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_I_ILG_INTR</name>
+              <description>TX Copy DMA access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_TX_I_3</name>
+          <description>TX Copy DMA status register.</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_TX_I_ILG_ST</name>
+              <description>Record the illegitimate information of TX Copy DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: TX Copy DMA bus byte enables.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BOOT_LOCATION_0</name>
+          <description>Boot permission control register 0.</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_BOOT_LOCATION_LOCK</name>
+              <description>Lock register. Setting to 1 locks boot remap permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_BOOT_LOCATION_1</name>
+          <description>Boot permission control register 1.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_BOOT_REMAP</name>
+              <description>If set to 1, enable boot remap function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SOURCE_0</name>
+          <description>Cache access permission control register 0.</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_SOURCE_LOCK</name>
+              <description>Lock register. Setting to 1 locks cache access permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SOURCE_1</name>
+          <description>Cache access permission control register 1.</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_CACHE_I_SOURCE_PRO_IRAM1</name>
+              <description>xx</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_I_SOURCE_PRO_IROM0</name>
+              <description>xx</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_I_SOURCE_PRO_DROM0</name>
+              <description>xx</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_D_SOURCE_PRO_DRAM0</name>
+              <description>xx</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_D_SOURCE_PRO_DPORT</name>
+              <description>xx</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_D_SOURCE_PRO_DROM0</name>
+              <description>xx</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_0</name>
+          <description>Peripheral access permission control register 0.</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_PERIPHERAL_LOCK</name>
+              <description>Lock register. Setting to 1 locks TX Copy DMA permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_1</name>
+          <description>Peripheral access permission control register 1.</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>APB_PERIPHERAL_SPLIT_BURST</name>
+              <description>Setting to 1 splits the data phase of the last access and the address phase of following access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OCCUPY_0</name>
+          <description>Occupy permission control register 0.</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OCCUPY_LOCK</name>
+              <description>Lock register. Setting to 1 locks occupy permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OCCUPY_1</name>
+          <description>Occupy permission control register 1.</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OCCUPY_CACHE</name>
+              <description>Configure whether SRAM Block 0-3 is used as cache memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OCCUPY_2</name>
+          <description>Occupy permission control register 2.</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OCCUPY_MAC_DUMP</name>
+              <description>Configure whether SRAM Block 18-21 is used as mac dump.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OCCUPY_3</name>
+          <description>Occupy permission control register 3.</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OCCUPY_PRO_TRACE</name>
+              <description>Configure one block of SRAM Block 4-21 is used as trace memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_ACCESS_0</name>
+          <description>Cache tag permission control register 0.</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_TAG_ACCESS_LOCK</name>
+              <description>Lock register. Setting to 1 locks cache tag permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_ACCESS_1</name>
+          <description>Cache tag permission control register 1.</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRO_I_TAG_RD_ACS</name>
+              <description>Setting to 1 permits read access to Icache tag memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_I_TAG_WR_ACS</name>
+              <description>Setting to 1 permits write access to Icache tag memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_D_TAG_RD_ACS</name>
+              <description>Setting to 1 permits read access to Dcache tag memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_D_TAG_WR_ACS</name>
+              <description>Setting to 1 permits write access to Dcache tag memory.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_ACCESS_0</name>
+          <description>Cache MMU permission control register 0.</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_ACCESS_LOCK</name>
+              <description>Lock register. Setting to 1 locks cache MMU permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_ACCESS_1</name>
+          <description>Cache MMU permission control register 1.</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MMU_RD_ACS</name>
+              <description>Setting to 1 permits read access to MMU memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_MMU_WR_ACS</name>
+              <description>Setting to 1 permits write access to MMU memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_INTR</name>
+          <description>PeribBus2 permission control register.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_PERI_BYTE_ERROR_CLR</name>
+              <description>The clear signal for APB peripheral interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_PERI_BYTE_ERROR_EN</name>
+              <description>The enable signal for APB peripheral access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_PERI_BYTE_ERROR_INTR</name>
+              <description>APB peripheral access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_STATUS</name>
+          <description>PeribBus2 peripheral access status register.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_PERI_BYTE_ERROR_ADDR</name>
+              <description>Record the illegitimate address of  APB peripheral.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERIPHERAL_INTR</name>
+          <description>PeribBus1 permission control register.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PERI_BYTE_ERROR_CLR</name>
+              <description>The clear signal for CPU peripheral access interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_PERI_BYTE_ERROR_EN</name>
+              <description>The enable signal for CPU peripheral access interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_PERI_BYTE_ERROR_INTR</name>
+              <description>CPU peripheral access interrupt signal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERIPHERAL_STATUS</name>
+          <description>PeribBus1 peripheral access status register.</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_PERI_BYTE_ERROR_ADDR</name>
+              <description>Record the illegitimate address of CPU peripheral.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE_REG</name>
+          <description>Clock gate register of permission control.</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Enable the clock of permission control module when set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register.</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01905090</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RMT</name>
+      <description>Remote Control Peripheral</description>
+      <groupName>RMT</groupName>
+      <baseAddress>0x3F416000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RMT</name>
+        <value>50</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%sDATA</name>
+          <description>The read and write  data register for CHANNEL%s by apb fifo access.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH_DATA</name>
+              <description>The read and write  data register for CHANNEL%s by apb fifo access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>CH%sCONF0</name>
+          <description>Channel %s configure register 0</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x39100002</resetValue>
+          <fields>
+            <field>
+              <name>DIV_CNT</name>
+              <description>This register is used to configure the divider for clock of CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_THRES</name>
+              <description>When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE</name>
+              <description>This register is used to configure the maximum size of memory allocated to CHANNEL%s.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EFF_EN</name>
+              <description>1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN</name>
+              <description>This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV</name>
+              <description>This bit is used to configure the position of carrier wave for CHANNEL%s.
+
+1'h0: add carrier wave on low level.
+
+1'h1: add carrier wave on high level.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>CH%sCONF1</name>
+          <description>Channel %s configure register 1</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000F20</resetValue>
+          <fields>
+            <field>
+              <name>TX_START</name>
+              <description>Set this bit to start sending data on CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_EN</name>
+              <description>Set this bit to enable receiver to receive data on CHANNEL%s.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_WR_RST</name>
+              <description>Set this bit to reset write ram address for CHANNEL%s by accessing receiver.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_RD_RST</name>
+              <description>Set this bit to reset read ram address for CHANNEL%s by accessing transmitter.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST</name>
+              <description>Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER</name>
+              <description>This register marks the ownership of CHANNEL%s's ram block.
+
+1'h1: Receiver is using the ram.
+
+1'h0: Transmitter is using the ram.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CONTI_MODE</name>
+              <description>Set this bit to restart transmission  from the first data to the last data in CHANNEL%s.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_EN</name>
+              <description>This is the receive filter's enable bit for CHANNEL%s.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_THRES</name>
+              <description>Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHK_RX_CARRIER_EN</name>
+              <description>Set this bit to enable memory loop read mode when carrier modulation is enabled for channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REF_ALWAYS_ON</name>
+              <description>This bit is used to select the base clock for CHANNEL%s.
+
+1'h1: clk_apb    1'h0:clk_ref</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_LV</name>
+              <description>This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_EN</name>
+              <description>This is the output enable-control bit for CHANNEL%s in IDLE state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP</name>
+              <description>Set this bit to stop the transmitter of CHANNEL%s sending data out.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%sSTATUS</name>
+          <description>Channel %s status register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>This register records the memory address offset when receiver of CHANNEL%s is using the RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>This register records the memory address offset when transmitter of CHANNEL%s is using the RAM.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>This register records the FSM status of CHANNEL%s.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>This status bit will be set when the ownership of memory block is wrong.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>This status bit will be set if the receiver receives more data than the memory size.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>This status bit will be set if the offset address out of memory size when writes via APB bus.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>This status bit will be set if the offset address out of memory size when reads via APB bus.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%sADDR</name>
+          <description>Channel %s address register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_MEM_WADDR</name>
+              <description>This register records the memory address offset when writes RAM over APB bus.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR</name>
+              <description>This register records the memory address offset when reads RAM over APB bus.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL%s. Triggered when transmission done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_RX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL%s. Triggered when reception done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL%s. Triggered when error occurs.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_LOOP_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH%s_TX_END_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_RX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH%s_RX_END_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH%s_ERR_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH%s_TX_THR_EVENT_INT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_LOOP_INT_ST</name>
+              <description>The masked interrupt status bit for CH%s_TX_LOOP_INT.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_END_INT_ENA</name>
+              <description>The interrupt enabled bit  for CH%s_TX_END_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_RX_END_INT_ENA</name>
+              <description>The interrupt enabled bit  for CH%s_RX_END_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_ERR_INT_ENA</name>
+              <description>The interrupt enabled bit  for CH%s_ERR_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enabled bit for CH%s_TX_THR_EVENT_INT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_LOOP_INT_ENA</name>
+              <description>The interrupt enabled bit  for CH%s_TX_LOOP_INT.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_END_INT_CLR</name>
+              <description>Set this bit to clear the CH%s_TX_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_RX_END_INT_CLR</name>
+              <description>Set this bit to clear the CH%s_RX_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x3</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_ERR_INT_CLR</name>
+              <description>Set this bit to clear the CH%s_ERR_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear the CH%s_TX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_LOOP_INT_CLR</name>
+              <description>Set this bit to clear the CH%s_TX_LOOP_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%sCARRIER_DUTY</name>
+          <description>Channel %s duty cycle configuration register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave 's low level clock period for CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave 's high level clock period for CHANNEL%s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_TX_LIM</name>
+          <description>Channel %s Tx event configuration register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>TX_LIM</name>
+              <description>This register is used to configure the maximum entries that CHANNEL%s can send out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_NUM</name>
+              <description>This register is used to configure the maximum loop count when tx_conti_mode is valid.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_CNT_EN</name>
+              <description>This register is the enabled bit for loop count.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOP_COUNT_RESET</name>
+              <description>This register is used to reset the loop count when tx_conti_mode is valid.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_CONF</name>
+          <description>RMT apb configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>APB_FIFO_MASK</name>
+              <description>1'h1: access memory directly.   1'h0: access memory by FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TX_WRAP_EN</name>
+              <description>This is the enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>Set this bit to enable the clock for RMT memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to power down RMT memory.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_SIM</name>
+          <description>RMT TX synchronous register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0</name>
+              <description>Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1</name>
+              <description>Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2</name>
+              <description>Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3</name>
+              <description>Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>This register is used to enable multiple of channels to start sending data synchronously.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REF_CNT_RST</name>
+          <description>RMT clock divider reset register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0</name>
+              <description>This register is used to reset the clock divider of CHANNEL0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1</name>
+              <description>This register is used to reset the clock divider of CHANNEL1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2</name>
+              <description>This register is used to reset the clock divider of CHANNEL2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3</name>
+              <description>This register is used to reset the clock divider of CHANNEL3.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_RX_CARRIER_RM</name>
+          <description>Channel %s carrier remove register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARRIER_LOW_THRES</name>
+              <description>The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH_THRES</name>
+              <description>The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>RMT version register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19072601</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RNG</name>
+      <description>Hardware random number generator</description>
+      <groupName>RNG</groupName>
+      <baseAddress>0x60035000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>DATA</name>
+          <description>Random number data</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RSA</name>
+      <description>RSA (Rivest Shamir Adleman) Accelerator</description>
+      <groupName>RSA</groupName>
+      <baseAddress>0x6003C000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x34</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RSA</name>
+        <value>54</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>M_PRIME</name>
+          <description>Register to store M'</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M_PRIME</name>
+              <description>Stores M'.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>RSA length mode</description>
+          <addressOffset>0x804</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Stores the mode of modular exponentiation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAN</name>
+          <description>RSA clean register</description>
+          <addressOffset>0x808</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAN</name>
+              <description>The content of this bit is 1 when memories complete initialization.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEXP_START</name>
+          <description>Modular exponentiation starting bit</description>
+          <addressOffset>0x80C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEXP_START</name>
+              <description>Set this bit to 1 to start the modular exponentiation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODMULT_START</name>
+          <description>Modular multiplication starting bit</description>
+          <addressOffset>0x810</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODMULT_START</name>
+              <description>Set this bit to 1 to start the modular multiplication.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_START</name>
+          <description>Normal multiplication starting bit</description>
+          <addressOffset>0x814</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MULT_START</name>
+              <description>Set this bit to 1 to start the multiplication.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE</name>
+          <description>RSA idle register</description>
+          <addressOffset>0x818</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>The content of this bit is 1 when the RSA accelerator is idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR_INTERRUPT</name>
+          <description>RSA clear interrupt register</description>
+          <addressOffset>0x81C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>Set this bit to 1 to clear the RSA interrupts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONSTANT_TIME</name>
+          <description>The constant_time option</description>
+          <addressOffset>0x820</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CONSTANT_TIME</name>
+              <description>Set this bit to 0 to enable the acceleration option of constant_time for modular exponentiation. Set to 1 to disable the acceleration (by default).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_ENABLE</name>
+          <description>The search option</description>
+          <addressOffset>0x824</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_ENABLE</name>
+              <description>Set this bit to 1 to enable the acceleration option of search for modular exponentiation. Set to 0 to disable the acceleration (by default).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_POS</name>
+          <description>The search position</description>
+          <addressOffset>0x828</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_POS</name>
+              <description>Is used to configure the starting address when the acceleration option of search is used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT_ENA</name>
+          <description>RSA interrupt enable register</description>
+          <addressOffset>0x82C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>INTERRUPT_ENA</name>
+              <description>Set this bit to 1 to enable the RSA interrupt. This option is enabled by default.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x830</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20190425</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTCIO</name>
+      <description>Peripheral RTCIO</description>
+      <groupName>RTCIO</groupName>
+      <baseAddress>0x3F408400</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xF0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>RTC_GPIO_OUT</name>
+          <description>RTC GPIO output register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_OUT_DATA</name>
+              <description>GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_OUT_W1TS</name>
+          <description>RTC GPIO output bit set register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_OUT_DATA_W1TS</name>
+              <description>GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_OUT_W1TC</name>
+          <description>RTC GPIO output bit clear register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_OUT_DATA_W1TC</name>
+              <description>GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_ENABLE</name>
+          <description>RTC GPIO output enable register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REG_RTCIO_REG_GPIO_ENABLE</name>
+              <description>GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_ENABLE_W1TS</name>
+          <description>RTC GPIO output enable bit set register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REG_RTCIO_REG_GPIO_ENABLE_W1TS</name>
+              <description>GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <description>RTC GPIO output enable bit clear register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TC</name>
+              <description>GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_STATUS</name>
+          <description>RTC GPIO interrupt status register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_STATUS_INT</name>
+              <description>GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_STATUS_W1TS</name>
+          <description>RTC GPIO interrupt status bit set register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_STATUS_INT_W1TS</name>
+              <description>GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_STATUS_W1TC</name>
+          <description>RTC GPIO interrupt status bit clear register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_STATUS_INT_W1TC</name>
+              <description>GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_IN</name>
+          <description>RTC GPIO input register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_IN_NEXT</name>
+              <description>GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. Each bit represents a pad input value, 1 for high level, and 0 for low level.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>22</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>PIN%s</name>
+          <description>RTC configuration for pin %s</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>Pad driver selection. 0: normal output. 1: open drain.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_INT_TYPE</name>
+              <description>GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_WAKEUP_ENABLE</name>
+              <description>GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_DEBUG_SEL</name>
+          <description>RTC debug select register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_DEBUG_SEL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_SEL1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_SEL2</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_SEL3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_SEL4</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_12M_NO_GATING</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>15</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TOUCH_PAD%s</name>
+          <description>Touch pad %s configuration register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x52000000</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_PAD0_FUN_IE</name>
+              <description>Input enable in normal execution.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_SLP_OE</name>
+              <description>Output enable in sleep mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_SLP_IE</name>
+              <description>Input enable in sleep mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_SLP_SEL</name>
+              <description>0: no sleep mode. 1: enable sleep mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_FUN_SEL</name>
+              <description>Function selection.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_MUX_SEL</name>
+              <description>Connect the RTC pad input to digital pad input.  0 is available.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_XPD</name>
+              <description>Touch sensor power on.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_TIE_OPT</name>
+              <description>The tie option of touch sensor. 0: tie low. 1: tie high.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_START</name>
+              <description>Start touch sensor.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_DAC</name>
+              <description>Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_RUE</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_RDE</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL_32P_PAD</name>
+          <description>32KHz crystal P-pad configuration register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>X32P_FUN_IE</name>
+              <description>Input enable in normal execution.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_SLP_OE</name>
+              <description>output enable in sleep mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_SLP_IE</name>
+              <description>input enable in sleep mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_SLP_SEL</name>
+              <description>1: enable sleep mode. 0: no sleep mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_FUN_SEL</name>
+              <description>Function selection.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_MUX_SEL</name>
+              <description>1: use RTC GPIO. 0: use digital GPIO.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_RUE</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_RDE</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL_32N_PAD</name>
+          <description>32KHz crystal N-pad configuration register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>X32N_FUN_IE</name>
+              <description>Input enable in normal execution.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_SLP_OE</name>
+              <description>Output enable in sleep mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_SLP_IE</name>
+              <description>Input enable in sleep mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_SLP_SEL</name>
+              <description>1: enable sleep mode. 0: no sleep mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_FUN_SEL</name>
+              <description>Function selection.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_MUX_SEL</name>
+              <description>1: use RTC GPIO. 0: use digital GPIO.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_RUE</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_RDE</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_DAC1</name>
+          <description>DAC1 configuration register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>PDAC1_DAC</name>
+              <description>Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_XPD_DAC</name>
+              <description>When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output. 0: disable DAC_1 output.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_DAC_XPD_FORCE</name>
+              <description>1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output. 0: use SAR ADC FSM to control DAC_1 output.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_FUN_IE</name>
+              <description>Input enable in normal execution.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_SLP_OE</name>
+              <description>Output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_SLP_IE</name>
+              <description>Input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_SLP_SEL</name>
+              <description>1: enable sleep mode. 0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_FUN_SEL</name>
+              <description>DAC_1 function selection.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_MUX_SEL</name>
+              <description>1: use RTC GPIO. 0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_RUE</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_RDE</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_DAC2</name>
+          <description>DAC2 configuration register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>PDAC2_DAC</name>
+              <description>Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_XPD_DAC</name>
+              <description>When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output. 0: disable DAC_2 output.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_DAC_XPD_FORCE</name>
+              <description>1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output. 0: use SAR ADC FSM to control DAC_2 output.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_FUN_IE</name>
+              <description>Input enable in normal execution.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_SLP_OE</name>
+              <description>Output enable in sleep mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_SLP_IE</name>
+              <description>Input enable in sleep mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_SLP_SEL</name>
+              <description>1: enable sleep mode. 0: no sleep mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_FUN_SEL</name>
+              <description>DAC_2 function selection.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_MUX_SEL</name>
+              <description>1: use RTC GPIO. 0: use digital GPIO.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_RUE</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_RDE</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_PAD19</name>
+          <description>Touch pad 19 configuration register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable in normal execution.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>Output enable in sleep mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>Input enable in sleep mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode. 0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>Function selection.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO. 0: use digital GPIO.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_PAD20</name>
+          <description>Touch pad 20 configuration register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable in normal execution.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>Output enable in sleep mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>Input enable in sleep mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode. 0: no sleep mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>Function selection.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO. 0: use digital GPIO.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_PAD21</name>
+          <description>Touch pad 21 configuration register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable in normal execution.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>Output enable in sleep mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>Input enable in sleep mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode. 0: no sleep mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>Function selection.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO. 0: use digital GPIO.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP0</name>
+          <description>External wake up configuration register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode.
+0: select GPIO0; 1: select GPIO2, etc</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTL_EXT_CTR</name>
+          <description>Crystal power down enable GPIO source</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_I2C_IO</name>
+          <description>RTC I2C pad selection</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_DEBUG_BIT_SEL</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SCL_SEL</name>
+              <description>Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0. 1: use TOUCH PAD2.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SDA_SEL</name>
+              <description>Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1. 1: use TOUCH PAD3.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_IO_TOUCH_CTRL</name>
+          <description>Touch control register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IO_TOUCH_BUFSEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IO_TOUCH_BUFMODE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_IO_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01903170</resetValue>
+          <fields>
+            <field>
+              <name>IO_DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC_CNTL</name>
+      <description>Real Time Controller</description>
+      <groupName>RTC_CNTL</groupName>
+      <baseAddress>0x3F408000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x138</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_CORE</name>
+        <value>49</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>OPTIONS0</name>
+          <description>Sets the power options of crystal and PLL clocks, and initiates reset by software</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1C002000</resetValue>
+          <fields>
+            <field>
+              <name>SW_STALL_APPCPU_C0</name>
+              <description>{reg_sw_stall_appcpu_c1[5:0] , reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STALL_PROCPU_C0</name>
+              <description>When RTC_CNTL_REG_SW_STALL_PROCPU_C1 is configured to 0x21, setting this bit to 0x2 stalls the CPU by SW.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_APPCPU_RST</name>
+              <description>APP CPU SW reset. (Note, we don’t have APP CPU for ESP32-S2)</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_PROCPU_RST</name>
+              <description>Set this bit to reset the CPU by SW.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PD</name>
+              <description>Set this bit to FPD BB_I2C.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PU</name>
+              <description>Set this bit to FPU BB_I2C.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PD</name>
+              <description>Set this bit to FPD BB_PLL _I2C.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PU</name>
+              <description>Set this bit to FPU BB_PLL _I2C.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PD</name>
+              <description>Set this bit to FPD BB_PLL.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PU</name>
+              <description>Set this bit to FPU BB_PLL.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PD</name>
+              <description>Set this bit to FPD the crystal oscillator.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PU</name>
+              <description>Set this bit to FPU the crystal oscillator.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_ISO</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FORCE_ISO</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_ISO</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_NOISO</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FORCE_NOISO</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_NOISO</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_RST</name>
+              <description>Set this bit to force reset the digital system in deep-sleep.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NORST</name>
+              <description>Set this bit to disable force reset to digital system in deep-sleep.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_SYS_RST</name>
+              <description>Set this bit to reset the system via SW.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER0</name>
+          <description>RTC timer threshold register 0</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_LO</name>
+              <description>Sets the lower 32 bits of the trigger threshold for the RTC timer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER1</name>
+          <description>RTC timer threshold register 1</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_HI</name>
+              <description>Sets the higher 16 bits of the trigger threshold for the RTC timer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_ALARM_EN</name>
+              <description>Sets this bit to enable the timer alarm.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_UPDATE</name>
+          <description>RTC timer update control register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SYS_STALL</name>
+              <description>Selects the triggering condition for the RTC timer. See details in Table 1-2.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_XTL_OFF</name>
+              <description>Selects the triggering condition for the RTC timer. See details in Table 1-2.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_SYS_RST</name>
+              <description>Selects the triggering condition for the RTC timer. See details in Table 1-2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_UPDATE</name>
+              <description>Selects the triggering condition for the RTC timer. See details in Table 1-2.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_LOW0</name>
+          <description>Stores the lower 32 bits of RTC timer 0.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE0_LOW</name>
+              <description>Stores the lower 32 bits of RTC timer 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_HIGH0</name>
+          <description>Stores the higher 16 bits of RTC timer 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE0_HIGH</name>
+              <description>Stores the higher 16 bits of RTC timer 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <description>Configures the sleep / reject / wakeup state</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_CPU_INT</name>
+              <description>Sends a SW RTC interrupt to CPU.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_CAUSE_CLR</name>
+              <description>Clears the RTC reject-to-sleep cause.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB2RTC_BRIDGE_SEL</name>
+              <description>1: APB to RTC using bridge    0: APB to RTC using sync</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_ACTIVE_IND</name>
+              <description>Indicates the SDIO is active.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_WAKEUP</name>
+              <description>Sleep wakeup bit.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT</name>
+              <description>Sleep reject bit.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_EN</name>
+              <description>Sends the chip to sleep.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1</name>
+          <description>Configures CPU stall options</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x28140403</resetValue>
+          <fields>
+            <field>
+              <name>CPU_STALL_EN</name>
+              <description>Enables CPU stalling.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_STALL_WAIT</name>
+              <description>Sets the CPU stall waiting cycle (using the RTC fast clock).</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_WAIT</name>
+              <description>Sets the 8 MHz clock  waiting (using the RTC slow clock).</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_BUF_WAIT</name>
+              <description>Sets the XTAL waiting cycle (using the RTC slow clock).</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_BUF_WAIT</name>
+              <description>Sets the PLL waiting cycle (using the RTC slow clock).</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2</name>
+          <description>Configures RTC slow clock and touch controller</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01080000</resetValue>
+          <fields>
+            <field>
+              <name>ULPCP_TOUCH_START_WAIT</name>
+              <description>Sets the waiting cycle (using the RTC slow clock) before the ULP co-processor / touch controller start to work.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN_TIME_CK8M_OFF</name>
+              <description>Sets the minimal cycle for  8 MHz clock (using the RTC slow clock) when powered down.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER3</name>
+          <description>configure some wait time for power on</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x14160A08</resetValue>
+          <fields>
+            <field>
+              <name>WIFI_WAIT_TIMER</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_POWERUP_TIMER</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM_RAM_WAIT_TIMER</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM_RAM_POWERUP_TIMER</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER4</name>
+          <description>configure some wait time for power on</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10200A08</resetValue>
+          <fields>
+            <field>
+              <name>WAIT_TIMER</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWERUP_TIMER</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_WAIT_TIMER</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_POWERUP_TIMER</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER5</name>
+          <description>Configures the minimal sleep cycles</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x12148000</resetValue>
+          <fields>
+            <field>
+              <name>MIN_SLP_VAL</name>
+              <description>Sets the minimal sleep cycles (using the RTC slow clock).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTCMEM_WAIT_TIMER</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTCMEM_POWERUP_TIMER</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER6</name>
+          <description>Configure minimal sleep cycles register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10200000</resetValue>
+          <fields>
+            <field>
+              <name>DG_DCDC_WAIT_TIMER</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_DCDC_POWERUP_TIMER</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ANA_CONF</name>
+          <description>Configures the power options for I2C and PLLA</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00A40000</resetValue>
+          <fields>
+            <field>
+              <name>I2C_RESET_POR_FORCE_PD</name>
+              <description>SLEEP_I2CPOR force pd</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RESET_POR_FORCE_PU</name>
+              <description>SLEEP_I2CPOR force pu</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_RST_EN</name>
+              <description>Set this bit to enable a reset when the system detects a glitch.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_FORCE_PD</name>
+              <description>Sets this bit to FPD the SAR_I2C.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_FORCE_PU</name>
+              <description>Sets this bit to FPU the SAR_I2C.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLA_FORCE_PD</name>
+              <description>Sets this bit to FPD the PLLA.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLA_FORCE_PU</name>
+              <description>Sets this bit to FPU the PLLA.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_SLP_START</name>
+              <description>start BBPLL calibration during sleep</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVTMON_PU</name>
+              <description>1: PVTMON power up    ,  otherwise power down</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXRF_I2C_PU</name>
+              <description>1: TXRF_I2C power up    ,    otherwise power down</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RFRX_PBUS_PU</name>
+              <description>1: RFRX_PBUS power up   ,   otherwise power down</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CKGEN_I2C_PU</name>
+              <description>1: CKGEN_I2C power up   , otherwise power down</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_I2C_PU</name>
+              <description>1. PLL_I2C power up ,otherwise power down</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESET_STATE</name>
+          <description>Indicates the CPU reset source. For more information about the reset cause, please refer to Table \ref{table:resetreasons} in Chapter \ref{module:ResetandClock} \textit{\nameref{module:ResetandClock}}.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003000</resetValue>
+          <fields>
+            <field>
+              <name>RESET_CAUSE_PROCPU</name>
+              <description>Stores the CPU reset cause.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESET_CAUSE_APPCPU</name>
+              <description>reset cause of APP CPU</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APPCPU_STAT_VECTOR_SEL</name>
+              <description>APP CPU state vector sel</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PROCPU_STAT_VECTOR_SEL</name>
+              <description>Selects the CPU state vector.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP_STATE</name>
+          <description>Wakeup bitmap enabling register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00060000</resetValue>
+          <fields>
+            <field>
+              <name>WAKEUP_ENA</name>
+              <description>Enables the wakeup bitmap.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC</name>
+          <description>RTC interrupt enabling register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA</name>
+              <description>Enables interruption when the chip wakes up from sleep.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA</name>
+              <description>Enables interruption when the chip rejects to go to sleep.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ENA</name>
+              <description>Enables interruption when the SDIO idles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>Enables the RTC watchdog interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_ENA</name>
+              <description>Enables interruption upon the completion of a touch scanning.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_ENA</name>
+              <description>Enables the ULP co-processor interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_ENA</name>
+              <description>Enables interruption upon the completion of a single touch.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_ENA</name>
+              <description>Enables interruption when a touch is detected.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_ENA</name>
+              <description>Enables interruption when a touch is released.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA</name>
+              <description>Enables the brown out interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA</name>
+              <description>Enables the RTC main timer interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_ENA</name>
+              <description>Enables the SAR ADC 1 interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_INT_ENA</name>
+              <description>Enables the touch sensor interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_INT_ENA</name>
+              <description>Enables the ULP-RISCV interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_ENA</name>
+              <description>Enables the SAR ADC 2 interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_INT_ENA</name>
+              <description>Enables the super watchdog interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ENA</name>
+              <description>Enables interruption when the 32 kHz crystal is dead.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_ENA</name>
+              <description>Enables interruption when the ULP-RISCV is trapped.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_ENA</name>
+              <description>Enables interruption when touch sensor times out.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>Enables interruption when a glitch is detected.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_RTC</name>
+          <description>RTC interrupt raw register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_RAW</name>
+              <description>Stores the raw interrupt triggered when the chip wakes up from sleep.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_RAW</name>
+              <description>Stores the raw interrupt triggered when the chip rejects to go to sleep.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_RAW</name>
+              <description>Stores the raw interrupt triggered when the SDIO idles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>Stores the raw RTC watchdog interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_RAW</name>
+              <description>Stores the raw interrupt triggered upon the completion of a touch scanning.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_RAW</name>
+              <description>Stores the raw ULP co-processor interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_RAW</name>
+              <description>Stores the raw interrupt triggered upon the completion of a single touch.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_RAW</name>
+              <description>Stores the raw interrupt triggered when a touch is detected.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_RAW</name>
+              <description>Stores the raw interrupt triggered when a touch is released.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_RAW</name>
+              <description>Stores the raw brown out interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_RAW</name>
+              <description>Stores the raw RTC main timer interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_RAW</name>
+              <description>Stores the raw SAR ADC 1 interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_INT_RAW</name>
+              <description>Stores the raw touch sensor interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_INT_RAW</name>
+              <description>Stores the raw ULP-RISCV interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_RAW</name>
+              <description>Stores the raw SAR ADC 2 interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_RAW</name>
+              <description>Stores the raw super watchdog interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_RAW</name>
+              <description>Stores the raw interrupt triggered when the 32 kHz crystal is dead.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_RAW</name>
+              <description>Stores the raw interrupt triggered when the ULP-RISCV is trapped.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_RAW</name>
+              <description>Stores the raw interrupt triggered when touch sensor times out.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>Stores the raw interrupt triggered when a glitch is detected.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_RTC</name>
+          <description>RTC interrupt state register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ST</name>
+              <description>Stores the status of the interrupt triggered when the chip wakes up from sleep.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ST</name>
+              <description>Stores the status of the interrupt triggered when the chip rejects to go to sleep.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ST</name>
+              <description>Stores the status of the interrupt triggered when the SDIO idles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>Stores the status of the RTC watchdog interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_ST</name>
+              <description>Stores the status of the interrupt triggered upon the completion of a touch scanning.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_ST</name>
+              <description>Stores the status of the ULP co-processor interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_ST</name>
+              <description>Stores the status of the interrupt triggered upon the completion of a single touch.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_ST</name>
+              <description>Stores the status of the interrupt triggered when a touch is detected.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_ST</name>
+              <description>Stores the status of the interrupt triggered when a touch is released.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ST</name>
+              <description>Stores the status of the brown out interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ST</name>
+              <description>Stores the status of the RTC main timer interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_ST</name>
+              <description>Stores the status of the SAR ADC 1 interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_INT_ST</name>
+              <description>Stores the status of the touch sensor interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_INT_ST</name>
+              <description>Stores the status of the ULP-RISCV interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_ST</name>
+              <description>Stores the status of the SAR ADC 2 interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_ST</name>
+              <description>Stores the status of the super watchdog interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ST</name>
+              <description>Stores the status of the interrupt triggered when the 32 kHz crystal is dead.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_ST</name>
+              <description>Stores the status of the interrupt triggered when the ULP-RISCV is trapped.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_ST</name>
+              <description>Stores the status of the interrupt triggered when touch sensor times out.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>Stores the status of the interrupt triggered when a glitch is detected.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_RTC</name>
+          <description>RTC interrupt clear register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_CLR</name>
+              <description>Clears the interrupt triggered when the chip wakes up from sleep.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_CLR</name>
+              <description>Clears the interrupt triggered when the chip rejects to go to sleep.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_CLR</name>
+              <description>Clears the interrupt triggered when the SDIO idles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Enables the RTC watchdog interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_CLR</name>
+              <description>Clears the interrupt triggered upon the completion of a touch scanning.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_CLR</name>
+              <description>Enables the ULP co-processor interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_CLR</name>
+              <description>Clears the interrupt triggered upon the completion of a single touch.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_CLR</name>
+              <description>Clears the interrupt triggered when a touch is detected.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_CLR</name>
+              <description>Clears the interrupt triggered when a touch is released.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_CLR</name>
+              <description>Clears the brown out interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_CLR</name>
+              <description>Clears the RTC main timer interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_CLR</name>
+              <description>Clears the SAR ADC 1 interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TSENS_INT_CLR</name>
+              <description>Clears the touch sensor interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_INT_CLR</name>
+              <description>Clears the ULP-RISCV interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_CLR</name>
+              <description>Clears the SAR ADC 2 interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_CLR</name>
+              <description>Clears the super watchdog interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_CLR</name>
+              <description>Clears the interrupt triggered when the 32 kHz crystal is dead.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_CLR</name>
+              <description>Clears the interrupt triggered when the ULP-RISCV is trapped.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_CLR</name>
+              <description>Clears the interrupt triggered when touch sensor times out.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Clears the interrupt triggered when a glitch is detected.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE0</name>
+          <description>Reservation register 0</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH0</name>
+              <description>Reservation register 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE1</name>
+          <description>Reservation register 1</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH1</name>
+              <description>Reservation register 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE2</name>
+          <description>Reservation register 2</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH2</name>
+              <description>Reservation register 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE3</name>
+          <description>Reservation register 3</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH3</name>
+              <description>Reservation register 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_XTL_CONF</name>
+          <description>32 kHz crystal oscillator configuration register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00066C80</resetValue>
+          <fields>
+            <field>
+              <name>XTAL32K_WDT_EN</name>
+              <description>Set this bit to enable the 32 kHz crystal watchdog.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_WDT_CLK_FO</name>
+              <description>Set this bit to FPU the 32 kHz crystal watchdog clock.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_WDT_RESET</name>
+              <description>Set this bit to reset the 32 kHz crystal watchdog by SW.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_EXT_CLK_FO</name>
+              <description>Set this bit to FPU the external clock of 32 kHz crystal.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_AUTO_BACKUP</name>
+              <description>Set this bit to switch to the backup clock when the 32 kHz crystal is dead.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_AUTO_RESTART</name>
+              <description>Set this bit to restart the 32 kHz crystal automatically when the 32 kHz crystal is dead.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_AUTO_RETURN</name>
+              <description>Set this bit to switch back to 32 kHz crystal when the 32 kHz crystal is restarted.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_XPD_FORCE</name>
+              <description>Set 1 to allow the software to FPD the 32 kHz crystal.  Set 0 to allow the FSM to FPD the 32 kHz crystal. (R/W)</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCKINIT_XTAL_32K</name>
+              <description>Applies an internal clock to help the 32 kHz crystal to start.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUF_XTAL_32K</name>
+              <description>0: single-end buffer 1: differential buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DGM_XTAL_32K</name>
+              <description>xtal_32k gm control</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRES_XTAL_32K</name>
+              <description>DRES_XTAL_32K</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_XTAL_32K</name>
+              <description>XPD_XTAL_32K</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_XTAL_32K</name>
+              <description>DAC_XTAL_32K</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STATE</name>
+              <description>Stores the status of the 32 kHz watchdog.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_GPIO_SEL</name>
+              <description>Selects the 32 kHz crystal clock. 0: selects the external 32 kHz clock.  1: selects clock from the RTC GPIO X32P_C.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_LV</name>
+              <description>0: powers down XTAL at high level  1: powers down XTAL at low level</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_EN</name>
+              <description>Enables the GPIO to power down the crystal oscillator.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP_CONF</name>
+          <description>GPIO wakeup configuration register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_WAKEUP_FILTER</name>
+              <description>Set this bit to enable the GPIO wakeup event filter.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP0_LV</name>
+              <description>0: external wakeup 0 at low level     1: external wakeup 0 at high level</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP1_LV</name>
+              <description>0: external wakeup 1 at low level     1: external wakeup 1 at high level</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_REJECT_CONF</name>
+          <description>Configures sleep / reject options</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLEEP_REJECT_ENA</name>
+              <description>Set this bit to enable reject-to-sleep.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LIGHT_SLP_REJECT_EN</name>
+              <description>Set this bit to enable reject-to-light-sleep.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEEP_SLP_REJECT_EN</name>
+              <description>Set this bit to enable reject-to-deep-sleep.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERIOD_CONF</name>
+          <description>CPU sel option</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPUSEL_CONF</name>
+              <description>CPU sel option</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_ACT_CONF</name>
+          <description>configure sdio active register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_ACT_DNUM</name>
+              <description>configure sdio act dnum</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>RTC clock configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01583218</resetValue>
+          <fields>
+            <field>
+              <name>CK8M_DIV_SEL_VLD</name>
+              <description>Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV</name>
+              <description>Set the CK8M_D256_OUT divider. 00: divided by 128   01: divided by 256   10: divided by 512  11: divided by 1024.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_CK8M</name>
+              <description>Set this bit to disable CK8M and CK8M_D256_OUT.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_CK8M_DIV</name>
+              <description>Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_XTAL32K_EN</name>
+              <description>Set this bit to enable CK_XTAL_32K clock for the digital core.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_D256_EN</name>
+              <description>Set this bit to enable CK8M_D256_OUT clock for the digital core.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_EN</name>
+              <description>Set this bit to enable 8 MHz clock for the digital core.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV_SEL</name>
+              <description>Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_FORCE_NOGATING</name>
+              <description>Set this bit to force no gating to crystal during sleep</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_NOGATING</name>
+              <description>Set this bit to disable force gating to 8 MHz crystal during sleep.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DFREQ</name>
+              <description>CK8M_DFREQ</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PD</name>
+              <description>Set this bit to FPD the 8 MHz clock.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PU</name>
+              <description>Set this bit to FPU the 8 MHz clock.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_CLK_RTC_SEL</name>
+              <description>Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANA_CLK_RTC_SEL</name>
+              <description>Set this bit to select the RTC slow clock. 0: 90K rtc_clk  1: 32k XTAL  2: 8md256.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLOW_CLK_CONF</name>
+          <description>RTC slow clock configuration register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>ANA_CLK_DIV_VLD</name>
+              <description>Synchronizes the reg_rtc_ana_clk_div bus. Note that you have to invalidate the bus before switching clock, and validate the new clock.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANA_CLK_DIV</name>
+              <description>Set the rtc_clk divider.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOW_CLK_NEXT_EDGE</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CONF</name>
+          <description>configure vddsdio register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02B0BE0A</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_TIMER_TARGET</name>
+              <description>timer count to apply reg_sdio_dcap after sdio power on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DTHDRV</name>
+              <description>Tieh = 1 mode drive ability. Initially set to 0 to limit charge current  set to 3 after several us.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DCAP</name>
+              <description>ability to prevent LDO from overshoot</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_INITI</name>
+              <description>add resistor from ldo output to ground. 0: no res  1: 6k  2: 4k   3: 2k</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_EN_INITI</name>
+              <description>0 to set init[1:0]=0</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DCURLIM</name>
+              <description>tune current limit threshold when tieh = 0. About 800mA/(8+d)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_MODECURLIM</name>
+              <description>select current limit mode</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_ENCURLIM</name>
+              <description>enable current limit</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_REG_PD_EN</name>
+              <description>power down SDIO_REG in sleep. Only active when reg_sdio_force = 0</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_FORCE</name>
+              <description>1: use SW option to control SDIO_REG   0: use state machine</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_TIEH</name>
+              <description>SW option for SDIO_TIEH. Only active when reg_sdio_force = 1</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG1P8_READY</name>
+              <description>read only register for REG1P8_READY</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DREFL_SDIO</name>
+              <description>SW option for DREFL_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DREFM_SDIO</name>
+              <description>SW option for DREFM_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DREFH_SDIO</name>
+              <description>SW option for DREFH_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SDIO</name>
+              <description>SW option for XPD_VOOSDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BIAS_CONF</name>
+          <description>configure power register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010800</resetValue>
+          <fields>
+            <field>
+              <name>BIAS_BUF_IDLE</name>
+              <description>open bias buf when system in active</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_WAKE</name>
+              <description>open bias buf when rtc in wakeup</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_DEEP_SLP</name>
+              <description>open bias buf when rtc in deep sleep</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_MONITOR</name>
+              <description>open bias buf when rtc in monitor state</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_CUR_DEEP_SLP</name>
+              <description>xpd cur when rtc in sleep_state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_CUR_MONITOR</name>
+              <description>xpd cur when rtc in monitor state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_SLEEP_DEEP_SLP</name>
+              <description>bias_sleep when rtc in sleep_state</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_SLEEP_MONITOR</name>
+              <description>bias_sleep when rtc in monitor state</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_DEEP_SLP</name>
+              <description>DBG_ATTEN when rtc in sleep state</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_MONITOR</name>
+              <description>DBG_ATTEN when rtc in monitor state</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_SCK_XTAL</name>
+              <description>ENB_SCK_XTAL</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INC_HEARTBEAT_REFRESH</name>
+              <description>INC_HEARTBEAT_REFRESH</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEC_HEARTBEAT_PERIOD</name>
+              <description>DEC_HEARTBEAT_PERIOD</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INC_HEARTBEAT_PERIOD</name>
+              <description>INC_HEARTBEAT_PERIOD</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEC_HEARTBEAT_WIDTH</name>
+              <description>DEC_HEARTBEAT_WIDTH</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_BIAS_I2C</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG</name>
+          <description>RTC/DIG regulator configuration register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xA9002400</resetValue>
+          <fields>
+            <field>
+              <name>DIG_REG_DBIAS_SLP</name>
+              <description>Configures the regulation factor for the digital system voltage regulator when the CPU is in sleep status.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_REG_DBIAS_WAK</name>
+              <description>Configures the regulation factor for the digital system voltage regulator when the CPU is in active status.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCK_DCAP</name>
+              <description>Configures the frequency of the RTC clocks.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBIAS_SLP</name>
+              <description>Configures the regulation factor for the low-power voltage regulator when the CPU is in sleep status.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBIAS_WAK</name>
+              <description>Configures the regulation factor for the low-power voltage regulator when the CPU is in active status.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBOOST_FORCE_PD</name>
+              <description>RTC_DBOOST force power down</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBOOST_FORCE_PU</name>
+              <description>RTC_DBOOST force power up</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGULATOR_FORCE_PD</name>
+              <description>Set this bit to FPD the RTC_REG, which means decreasing its voltage to 0.8 V or lower.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGULATOR_FORCE_PU</name>
+              <description>Set this bit to FPU the RTC_REG.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWC</name>
+          <description>RTC power configuraiton register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00012925</resetValue>
+          <fields>
+            <field>
+              <name>FASTMEM_FORCE_NOISO</name>
+              <description>Set this bit to disable the force isolation to the RTC fast memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_ISO</name>
+              <description>Set this bit to force isolate the RTC fast memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_NOISO</name>
+              <description>Set this bit to disable the force isolation to the RTC slow memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_ISO</name>
+              <description>Set this bit to force isolate the RTC slow memory.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_ISO</name>
+              <description>Set this bit to force isolate the RTC peripherals.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_NOISO</name>
+              <description>Set this bit to disable the force isolation to the RTC peripherals.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FOLW_CPU</name>
+              <description>Set 1 to FPD the RTC fast memory when the CPU is powered down.  Set 0 to FPD the RTC fast memory when the RTC main state machine is powered down.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_LPD</name>
+              <description>Set this bit to force not retain the RTC fast memory.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_LPU</name>
+              <description>Set this bit to force retain the RTC fast memory.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FOLW_CPU</name>
+              <description>Set 1 to FPD the RTC slow memory when the CPU is powered down.  Set 0 to FPD the RTC slow memory when the RTC main state machine is powered down.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_LPD</name>
+              <description>Set this bit to force not retain the RTC slow memory.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_LPU</name>
+              <description>Set this bit to force retain the RTC slow memory.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_PD</name>
+              <description>Set this bit to FPD the RTC fast memory.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_PU</name>
+              <description>Set this bit to FPU the RTC fast memory.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_PD_EN</name>
+              <description>Set this bit to enable PD for the RTC fast memory in sleep.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_PD</name>
+              <description>Set this bit to FPD the RTC slow memory.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_PU</name>
+              <description>Set this bit to FPU the RTC slow memory.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_PD_EN</name>
+              <description>Set this bit to enable PD for the RTC slow memory in sleep.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_PD</name>
+              <description>Set this bit to FPD the RTC peripherals.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_PU</name>
+              <description>Set this bit to FPU the RTC peripherals.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_EN</name>
+              <description>Set this bit to enable PD for the RTC peripherals in sleep.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_FORCE_HOLD</name>
+              <description>Set this bit the force hold the RTC GPIOs.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PWC</name>
+          <description>Digital system power configuraiton register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00555550</resetValue>
+          <fields>
+            <field>
+              <name>LSLP_MEM_FORCE_PD</name>
+              <description>Set this bit to FPD the memories in the digital system in sleep.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSLP_MEM_FORCE_PU</name>
+              <description>Set this bit to FPU the memories in the digital system.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_FORCE_PD</name>
+              <description>ROM force power down</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_FORCE_PU</name>
+              <description>ROM force power up</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_FORCE_PD</name>
+              <description>internal SRAM 0 force power down</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_FORCE_PU</name>
+              <description>internal SRAM 0 force power up</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_FORCE_PD</name>
+              <description>internal SRAM 1 force power down</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_FORCE_PU</name>
+              <description>internal SRAM 1 force power up</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_FORCE_PD</name>
+              <description>internal SRAM 2 force power down</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_FORCE_PU</name>
+              <description>internal SRAM 2 force power up</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_FORCE_PD</name>
+              <description>internal SRAM 3 force power down</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_FORCE_PU</name>
+              <description>internal SRAM 3 force power up</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_FORCE_PD</name>
+              <description>internal SRAM 4 force power down</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_FORCE_PU</name>
+              <description>internal SRAM 4 force power up</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_PD</name>
+              <description>Set this bit to FPD the Wi-Fi circuit.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_PU</name>
+              <description>Set this bit to FPU the Wi-Fi circuit.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PD</name>
+              <description>Set this bit to FPD the digital system.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PU</name>
+              <description>Set this bit to FPD the DC-DC convertor in the digital system.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_DCDC_FORCE_PD</name>
+              <description>Set this bit to FPD the DC-DC convertor in the digital system.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_DCDC_FORCE_PU</name>
+              <description>Set this bit to FPU the DC-DC convertor in the digital system.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_DCDC_PD_EN</name>
+              <description>Set this bit to enable PD for the DC-DC convertor in the digital system.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_PD_EN</name>
+              <description>enable power down ROM in sleep</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_PD_EN</name>
+              <description>enable power down internal SRAM 0 in sleep</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_PD_EN</name>
+              <description>enable power down internal SRAM 1 in sleep</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_PD_EN</name>
+              <description>enable power down internal SRAM 2 in sleep</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_PD_EN</name>
+              <description>enable power down internal SRAM 3 in sleep</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_PD_EN</name>
+              <description>enable power down internal SRAM 4 in sleep</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_PD_EN</name>
+              <description>Set this bit to enable PD for the Wi-Fi circuit in sleep.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_PD_EN</name>
+              <description>Set this bit to enable PD for the digital system in sleep.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_ISO</name>
+          <description>Digital system ISO configuration register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xAAAA5000</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_OFF</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_ON</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD</name>
+              <description>Indicates the auto-hold status of the digital GPIOs.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLR_DG_PAD_AUTOHOLD</name>
+              <description>Se this bit to clear the auto-hold enabler for the digital GPIOs.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD_EN</name>
+              <description>Se this bit to allow the digital GPIOs to enter the autohold status.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_NOISO</name>
+              <description>Set this bit to disable the force isolation to the digital GPIOs.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_ISO</name>
+              <description>Set this bit to force isolate the digital GPIOs.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_UNHOLD</name>
+              <description>Set this bit the force unhold the digital GPIOs.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_HOLD</name>
+              <description>Set this bit the force hold the digital GPIOs.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_FORCE_ISO</name>
+              <description>ROM force ISO</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM0_FORCE_NOISO</name>
+              <description>ROM force no ISO</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_FORCE_ISO</name>
+              <description>internal SRAM 0 force ISO</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM0_FORCE_NOISO</name>
+              <description>internal SRAM 0 force no ISO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_FORCE_ISO</name>
+              <description>internal SRAM 1 force ISO</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM1_FORCE_NOISO</name>
+              <description>internal SRAM 1 force no ISO</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_FORCE_ISO</name>
+              <description>internal SRAM 2 force ISO</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM2_FORCE_NOISO</name>
+              <description>internal SRAM 2 force no ISO</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_FORCE_ISO</name>
+              <description>internal SRAM 3 force ISO</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM3_FORCE_NOISO</name>
+              <description>internal SRAM 3 force no ISO</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_FORCE_ISO</name>
+              <description>internal SRAM 4 force ISO</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTER_RAM4_FORCE_NOISO</name>
+              <description>internal SRAM 4 force no ISO</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_ISO</name>
+              <description>Set this bit to force isolate the Wi-Fi circuits.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_NOISO</name>
+              <description>Set this bit to disable the force isolation to the Wi-Fi circuits.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_ISO</name>
+              <description>Set this bit to force isolate the digital system.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NOISO</name>
+              <description>Set this bit to disable the force isolation to the digital system.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>RTC watchdog configuration register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013214</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CHIP_RESET_WIDTH</name>
+              <description>chip reset siginal pulse width</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CHIP_RESET_EN</name>
+              <description>wdt reset whole chip enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PAUSE_IN_SLP</name>
+              <description>Set this bit to pause the watchdog in sleep.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>enable WDT reset APP CPU</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>Set this bit to allow the watchdog to be able to reset CPU.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>Set this bit to enable watchdog when the chip boots from flash.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>Sets the length of the system reset counter.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>Sets the length of the CPU reset counter.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>1: enable at the interrupt stage 2: enable at the CPU stage  3: enable at the system stage 4: enable at the system and RTC stage.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>1: enable at the interrupt stage 2: enable at the CPU stage  3: enable at the system stage 4: enable at the system and RTC stage.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>1: enable at the interrupt stage 2: enable at the CPU stage  3: enable at the system stage 4: enable at the system and RTC stage.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>1: enable at the interrupt stage 2: enable at the CPU stage  3: enable at the system stage 4: enable at the system and RTC stage.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>Set this bit to enable the RTC watchdog.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>Configures the hold time of RTC watchdog at level 1</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030D40</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>Configures the hold time of RTC watchdog at level 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>Configures the hold time of RTC watchdog at level 2</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013880</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>Configures the hold time of RTC watchdog at level 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>Configures the hold time of RTC watchdog at level 3</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>Configures the hold time of RTC watchdog at level 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>Configures the hold time of RTC watchdog at level 4</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>Configures the hold time of RTC watchdog at level 4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>RTC watchdog SW feed configuration register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>Set 1 to feed the RTC watchdog.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>RTC watchdog write protection configuration register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>Sets the write protection key of the watchdog.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_CONF</name>
+          <description>Super watchdog configuration register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x04B00000</resetValue>
+          <fields>
+            <field>
+              <name>SWD_RESET_FLAG</name>
+              <description>Indicates the super watchdog reset flag.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_FEED_INT</name>
+              <description>Receiving this interrupt leads to feeding the super watchdog via SW.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_SIGNAL_WIDTH</name>
+              <description>Adjusts the signal width sent to the super watchdog.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_RST_FLAG_CLR</name>
+              <description>Set to reset the super watchdog reset flag.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_FEED</name>
+              <description>Set to feed the super watchdog via SW.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_DISABLE</name>
+              <description>Set this bit to disable super watchdog.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_AUTO_FEED_EN</name>
+              <description>Set this bit to enable automatic watchdog feeding upon interrupts.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_WPROTECT</name>
+          <description>Super watchdog write protection configuration register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x8F1D312A</resetValue>
+          <fields>
+            <field>
+              <name>SWD_WKEY</name>
+              <description>Sets the write protection key of the super watchdog.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SW_CPU_STALL</name>
+          <description>CPU stall configuration register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_STALL_APPCPU_C1</name>
+              <description>{reg_sw_stall_appcpu_c1[5:0]  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STALL_PROCPU_C1</name>
+              <description>Set this bit to allow the SW to be able to send the CPU into stalling.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE4</name>
+          <description>Reservation register 4</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH4</name>
+              <description>Reservation register 4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE5</name>
+          <description>Reservation register 5</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH5</name>
+              <description>Reservation register 5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE6</name>
+          <description>Reservation register 6</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH6</name>
+              <description>Reservation register 6.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE7</name>
+          <description>Reservation register 7</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH7</name>
+              <description>Reservation register 7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOW_POWER_ST</name>
+          <description>RTC main state machine status register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XPD_ROM0</name>
+              <description>rom0 power down</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_DIG_DCDC</name>
+              <description>External DCDC power down</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERI_ISO</name>
+              <description>rtc peripheral iso</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_RTC_PERI</name>
+              <description>rtc peripheral power down</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WIFI_ISO</name>
+              <description>wifi iso</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_WIFI</name>
+              <description>wifi wrap power down</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIG_ISO</name>
+              <description>digital wrap iso</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_DIG</name>
+              <description>digital wrap power down</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_START</name>
+              <description>touch should start to work</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_SWITCH</name>
+              <description>touch is about to working. Switch rtc main state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_SLP</name>
+              <description>touch is in sleep state</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_DONE</name>
+              <description>touch is done</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_START</name>
+              <description>ulp/cocpu should start to work</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_SWITCH</name>
+              <description>ulp/cocpu is about to working. Switch rtc main state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_SLP</name>
+              <description>ulp/cocpu is in sleep state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_DONE</name>
+              <description>ulp/cocpu is done</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_XTAL_ISO</name>
+              <description>no use any more</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_PLL_ON</name>
+              <description>rtc main state machine is in states that pll should be running</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RDY_FOR_WAKEUP</name>
+              <description>Indicates the RTC is ready to be triggered by any wakeup source.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_WAIT_END</name>
+              <description>rtc main state machine has been waited for some cycles</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_WAKEUP_STATE</name>
+              <description>rtc main state machine is in the states of wakeup process</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_LOW_POWER_STATE</name>
+              <description>rtc main state machine is in the states of low power</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_8M</name>
+              <description>rtc main state machine is in wait 8m state</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_PLL</name>
+              <description>rtc main state machine is in wait pll state</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_XTL</name>
+              <description>rtc main state machine is in wait xtal state</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_SLP</name>
+              <description>rtc main state machine is in sleep state</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_IDLE</name>
+              <description>rtc main state machine is in idle state</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE</name>
+              <description>rtc main state machine status</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIAG0</name>
+          <description>debug register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOW_POWER_DIAG1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_HOLD</name>
+          <description>Configures the hold options for RTC GPIOs</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD0_HOLD</name>
+              <description>Sets the touch GPIO 0 to hold.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD1_HOLD</name>
+              <description>Sets the touch GPIO 1 to hold.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD2_HOLD</name>
+              <description>Sets the touch GPIO 2 to hold.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD3_HOLD</name>
+              <description>Sets the touch GPIO 3 to hold.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD4_HOLD</name>
+              <description>Sets the touch GPIO 4 to hold.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD5_HOLD</name>
+              <description>Sets the touch GPIO 5 to hold.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD6_HOLD</name>
+              <description>Sets the touch GPIO 6 to hold.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD7_HOLD</name>
+              <description>Sets the touch GPIO 7 to hold.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD8_HOLD</name>
+              <description>Sets the touch GPIO 8 to hold.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD9_HOLD</name>
+              <description>Sets the touch GPIO 9 to hold.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD10_HOLD</name>
+              <description>Sets the touch GPIO 10 to hold.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD11_HOLD</name>
+              <description>Sets the touch GPIO 11 to hold.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD12_HOLD</name>
+              <description>Sets the touch GPIO 12 to hold.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD13_HOLD</name>
+              <description>Sets the touch GPIO 13 to hold.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD14_HOLD</name>
+              <description>Sets the touch GPIO 14 to hold.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_HOLD</name>
+              <description>Sets the x32p to hold.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_HOLD</name>
+              <description>Sets the x32n to hold.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_HOLD</name>
+              <description>Sets the pdac1 to hold.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_HOLD</name>
+              <description>Sets the pdac2 to hold.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD19_HOLD</name>
+              <description>Sets the RTG GPIO 19 to hold.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD20_HOLD</name>
+              <description>Sets the RTG GPIO 20 to hold.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD21_HOLD</name>
+              <description>Sets the RTG GPIO 21 to hold.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PAD_HOLD</name>
+          <description>Configures the hold option for digital GPIOs</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIG_PAD_HOLD</name>
+              <description>Set GPIO 21 to GPIO 45 to hold. (See bitmap to locate any GPIO).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP1</name>
+          <description>EXT1 wakeup configuration register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>Selects a RTC GPIO to be the EXT1 wakeup source.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STATUS_CLR</name>
+              <description>Clears the EXT1 wakeup status.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP1_STATUS</name>
+          <description>EXT1 wakeup source register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_WAKEUP1_STATUS</name>
+              <description>Indicates the EXT1 wakeup status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BROWN_OUT</name>
+          <description>Brownout configuration register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03FF2FF1</resetValue>
+          <fields>
+            <field>
+              <name>BROWN_OUT2_ENA</name>
+              <description>Enables the brown_out2 to initiate a chip reset.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_WAIT</name>
+              <description>Configures the waiting cycle before sending an interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLOSE_FLASH_ENA</name>
+              <description>Set this bit to enable PD the flash when a brown-out happens.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_RF_ENA</name>
+              <description>Set this bit to enable PD the RF circuits when a brown-out happens.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_WAIT</name>
+              <description>Configures the waiting cycle before the reset after a brown-out.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_ENA</name>
+              <description>Enables to reset brown-out.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_SEL</name>
+              <description>Selects the reset type when a brown-out happens. 1: chip reset  0: system reset.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_CLR</name>
+              <description>Clears the brown-out counter.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ENA</name>
+              <description>Set this bit to enable brown-out detection.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET</name>
+              <description>Indicates the status of the brown-out signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_LOW1</name>
+          <description>Stores the lower 32 bits of RTC timer 1</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE1_LOW</name>
+              <description>Stores the lower 32 bits of RTC timer 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_HIGH1</name>
+          <description>Stores the higher 16 bits of RTC timer 1</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE1_HIGH</name>
+              <description>Stores the higher 16 bits of RTC timer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL32K_CLK_FACTOR</name>
+          <description>Configures the divider factor for the backup clock of 32 kHz crystal oscillator</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XTAL32K_CLK_FACTOR</name>
+              <description>Configures the divider factor for the 32 kHz crystal oscillator.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL32K_CONF</name>
+          <description>32 kHz crystal oscillator configuration register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0FF00000</resetValue>
+          <fields>
+            <field>
+              <name>XTAL32K_RETURN_WAIT</name>
+              <description>Defines the waiting cycles before returning to the normal 32 kHz crystal oscillator.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_RESTART_WAIT</name>
+              <description>Defines the maximum waiting cycle before restarting the 32 kHz crystal oscillator.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_WDT_TIMEOUT</name>
+              <description>Defines the maximum waiting period for clock detection. If no clock is detected after this period, the 32 kHz crystal oscillator can be regarded as dead.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_STABLE_THRES</name>
+              <description>Defines the maximum allowed restarting period, within which the 32 kHz crystal oscillator can be regarded as stable.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_TIMER</name>
+          <description>Configure coprocessor timer</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ULP_CP_PC_INIT</name>
+              <description>ULP coprocessor PC initial address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_GPIO_WAKEUP_ENA</name>
+              <description>Enable the option of ULP coprocessor woken up by
+RTC GPIO</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_GPIO_WAKEUP_CLR</name>
+              <description>Disable the option of ULP coprocessor woken up by
+RTC GPIO</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_SLP_TIMER_EN</name>
+              <description>ULP coprocessor timer enable bit. 0: Disable hardware
+Timer. 1: Enable hardware timer</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_CTRL</name>
+          <description>ULP-FSM configuration register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00100200</resetValue>
+          <fields>
+            <field>
+              <name>ULP_CP_MEM_ADDR_INIT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_MEM_ADDR_SIZE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_MEM_OFFSET_CLR</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_CLK_FO</name>
+              <description>ULP-FSM clock force on</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_RESET</name>
+              <description>ULP-FSM clock software reset</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_FORCE_START_TOP</name>
+              <description>Write 1 to start ULP-FSM by software</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_START_TOP</name>
+              <description>Write 1 to start ULP-FSM</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COCPU_CTRL</name>
+          <description>ULP-RISCV configuration register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x008A0810</resetValue>
+          <fields>
+            <field>
+              <name>COCPU_CLK_FO</name>
+              <description>ULP-RISCV clock force on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_START_2_RESET_DIS</name>
+              <description>Time from ULP-RISCV startup to pull down reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_START_2_INTR_EN</name>
+              <description>Time from ULP-RISCV startup to send out
+RISCV_START_INT interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SHUT</name>
+              <description>Shut down ULP-RISCV</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SHUT_2_CLK_DIS</name>
+              <description>Time from shut down ULP-RISCV to disable clock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SHUT_RESET_EN</name>
+              <description>This bit is used to reset ULP-RISCV</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SEL</name>
+              <description>0: select ULP-RISCV. 1: select ULP-FSM</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_DONE_FORCE</name>
+              <description>0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE
+signal</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_DONE</name>
+              <description>DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the
+timer starts counting</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SW_INT_TRIGGER</name>
+              <description>Trigger ULP-RISCV register interrupt</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_CTRL1</name>
+          <description>Touch control register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000100</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_SLEEP_CYCLES</name>
+              <description>Set sleep cycles for touch timer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_NUM</name>
+              <description>Configure measurement length (in 8 MHz), i.e., charge/discharge times.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_CTRL2</name>
+          <description>Touch control register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000840CC</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_DRANGE</name>
+              <description>TOUCH attenuation.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DREFL</name>
+              <description>TOUCH reference voltage low. 0: 0.5 V 1: 0.6 V 2: 0.7 V 3: 0.8 V.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DREFH</name>
+              <description>TOUCH reference voltage high. 0: 2.4 V 1: 2.5 V 2: 2.6 V 3: 2.7 V.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_XPD_BIAS</name>
+              <description>TOUCH BIAS power switch.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_REFC</name>
+              <description>Touch pad 0 reference capacitance.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DBIAS</name>
+              <description>0: Use bandgap bias. 1: Use self bias.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_TIMER_EN</name>
+              <description>Touch timer enable bit.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_START_FSM_EN</name>
+              <description>0: TOUCH_START and TOUCH_XPD are controlled by soft- ware. 1: TOUCH_START and TOUCH_XPD are controlled by the Touch FSM.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_START_EN</name>
+              <description>1: Start the Touch FSM, only valid when RTC_CNTL_TOUCH_START_FORCE = 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_START_FORCE</name>
+              <description>0: Start the Touch FSM by timer. 1: Start Touch FSM by software.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_XPD_WAIT</name>
+              <description>The waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_CYC_DIV</name>
+              <description>When a touch pad is active, sleep cycle could be divided by this number.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMER_FORCE_DONE</name>
+              <description>Force touch timer done.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_RESET</name>
+              <description>Reset TOUCH FSM via software.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_CLK_FO</name>
+              <description>Touch clock force on.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_CLKGATE_EN</name>
+              <description>Touch clock enable bit.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_SCAN_CTRL</name>
+          <description>Configure touch scan settings</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xF0000102</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_DENOISE_RES</name>
+              <description>Denoise resolution. 0: 12-bit; 1: 10-bit; 2: 8-bit; 3: 4-bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DENOISE_EN</name>
+              <description>Touch pad 0 will be used to denoise.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_CONNECTION</name>
+              <description>Inactive touch pads connect to 0: HighZ, 1: GND.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SHIELD_PAD_EN</name>
+              <description>Touch pad 14 will be used as shield_pad.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_PAD_MAP</name>
+              <description>Pad enable map for touch scan mode.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_BUFDRV</name>
+              <description>Touch 14 buffer driver strength.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_OUT_RING</name>
+              <description>Select out one pad as guard_ring.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_SLP_THRES</name>
+          <description>Configure the settings of touch sleep pad</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x78000000</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_SLP_TH</name>
+              <description>Set the threshold for touch sleep pad.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_APPROACH_EN</name>
+              <description>Enable the proximity mode of touch sleep pad.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_PAD</name>
+              <description>Select sleep pad.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_APPROACH</name>
+          <description>Configure touch approach settings</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_SLP_CHANNEL_CLR</name>
+              <description>Clear touch sleep channel.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEAS_TIME</name>
+              <description>Set the total measurement times for the pads in
+proximity mode. Range: 0 – 255.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_FILTER_CTRL</name>
+          <description>Configure touch filter settings</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x96AA8800</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_SMOOTH_LVL</name>
+              <description>0: Raw data. 1: IIR1/2. 2: IIR1/4. 3: IIR1/8.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_JITTER_STEP</name>
+              <description>Touch jitter step. Range: 0 – 15.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_NEG_NOISE_LIMIT</name>
+              <description>Negative threshold counter limit.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_NEG_NOISE_THRES</name>
+              <description>Negative noise threshold.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_NOISE_THRES</name>
+              <description>Active noise threshold.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_HYSTERESIS</name>
+              <description>Touch hysteresis.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DEBOUNCE</name>
+              <description>Debounce counter.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_FILTER_MODE</name>
+              <description>Set filter mode. 0: IIR 1/2; 1: IIR 1/4; 2: IIR 1/8; 3: IIR 1/16; 4: IIR 1/32; 5: IIR 1/64; 6: IIR 1/128; 7: Jitter.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_FILTER_EN</name>
+              <description>Enable touch filter.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_CONF</name>
+          <description>configure usb control register</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_VREFH</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_VREFL</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_VREF_OVERRIDE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_PULL_OVERRIDE</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DP_PULLUP</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DP_PULLDOWN</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DM_PULLUP</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DM_PULLDOWN</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PULLUP_VALUE</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_ENABLE_OVERRIDE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_ENABLE</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_TXM</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_TXP</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_TX_EN</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_TX_EN_OVERRIDE</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_RESET_DISABLE</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IO_MUX_RESET_DISABLE</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_TIMEOUT_CTRL</name>
+          <description>Configure touch timeout settings</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x007FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_TIMEOUT_NUM</name>
+              <description>Set touch timeout threshold.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_EN</name>
+              <description>Enable touch timeout.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_REJECT_CAUSE</name>
+          <description>Stores the reject-to-sleep cause.</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REJECT_CAUSE</name>
+              <description>Stores the reject-to-sleep cause.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OPTIONS1</name>
+          <description>RTC option register</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FORCE_DOWNLOAD_BOOT</name>
+              <description>Set this bit to force the chip to boot from the download mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CAUSE</name>
+          <description>Stores the sleep-to-wakeup cause.</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WAKEUP_CAUSE</name>
+              <description>Stores the wakeup cause.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_TIMER_1</name>
+          <description>Configure sleep cycle of the timer</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C800</resetValue>
+          <fields>
+            <field>
+              <name>ULP_CP_TIMER_SLP_CYCLE</name>
+              <description>Set sleep cycles for ULP coprocessor timer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01906191</resetValue>
+          <fields>
+            <field>
+              <name>CNTL_DATE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC_I2C</name>
+      <description>Peripheral RTC_I2C</description>
+      <groupName>RTC_I2C</groupName>
+      <baseAddress>0x3F408C00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x7C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCL_LOW</name>
+          <description>Configure the low level width of SCL</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>PERIOD</name>
+              <description>This register is used to configure how many clock cycles SCL
+remains low.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>Transmission setting</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>SDA output mode. 0: open drain. 1: push pull.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>SCL output mode. 0: open drain. 1: push pull.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>Set this bit to configure RTC I²C as a master.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>Set this bit to 1, RTC I2C starts sending data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>This bit is used to control the sending mode. 0: send data from the most
+significant bit. 1: send data from the least significant bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>This bit is used to control the storage mode for received data. 0: receive
+data from the most significant bit. 1: receive data from the least significant bit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_GATE_EN</name>
+              <description>RTC I²C controller clock gate.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESET</name>
+              <description>RTC I²C software reset.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>rtc i2c reg clk gating</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>RTC I2C status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ACK_REC</name>
+              <description>The received ACK value. 0: ACK. 1: NACK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW</name>
+              <description>0: master writes to slave. 1: master reads from slave.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>When the RTC I2C loses control of SCL line, the register changes to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>0: RTC I2C bus is in idle state. 1: RTC I2C bus is busy transferring data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDRESSED</name>
+              <description>When the address sent by the master matches the address of the
+slave, then this bit will be set.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS</name>
+              <description>This field changes to 1 when one byte is transferred.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP_CNT</name>
+              <description>Indicate which operation is working.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SHIFT</name>
+              <description>shifter content</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_STATE_LAST</name>
+              <description>i2c last main status</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_STATE_LAST</name>
+              <description>scl last status</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TO</name>
+          <description>Configure RTC I2C timeout</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>TIME_OUT</name>
+              <description>Timeout threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_ADDR</name>
+          <description>Configure slave address</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_ADDR</name>
+              <description>slave address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_EN</name>
+              <description>This field is used to enable the slave 10-bit addressing mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH</name>
+          <description>Configure the high level width of SCL</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>PERIOD</name>
+              <description>This register is used to configure how many cycles SCL remains high.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_DUTY</name>
+          <description>Configure the SDA hold time after a negative
+SCL edge</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>NUM</name>
+              <description>The number of clock cycles between the SDA switch and the falling
+edge of SCL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_PERIOD</name>
+          <description>Configure the delay between the SDA and SCL
+negative edge for a start condition</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>SCL_START_PERIOD</name>
+              <description>Number of clock cycles to wait after generating a start condition.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_PERIOD</name>
+          <description>Configure the delay between SDA and SCL positive edge for a stop condition</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>SCL_STOP_PERIOD</name>
+              <description>Number of clock cycles to wait before generating a stop condition.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Clear RTC I2C interrupt</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_CLR</name>
+              <description>RTC_I2C_SLAVE_TRAN_COMP_INT interrupt clear bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <description>RTC_I2C_ARBITRATION_LOST_INT interrupt clear bit</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_CLR</name>
+              <description>RTC_I2C_MASTER_TRAN_COMP_INT interrupt
+clear bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <description>RTC_I2C_TRANS_COMPLETE_INT interrupt clear bit</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <description>RTC_I2C_TIME_OUT_INT interrupt clear bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_CLR</name>
+              <description>RTC_I2C_ACK_ERR_INT interrupt clear bit</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_DATA_INT_CLR</name>
+              <description>RTC_I2C_RX_DATA_INT interrupt clear bit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DATA_INT_CLR</name>
+              <description>RTC_I2C_TX_DATA_INT interrupt clear bit</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DETECT_START_INT_CLR</name>
+              <description>RTC_I2C_DETECT_START_INT interrupt clear bit</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>RTC I2C raw interrupt</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_RAW</name>
+              <description>RTC_I2C_SLAVE_TRAN_COMP_INT interrupt raw bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>RTC_I2C_ARBITRATION_LOST_INT interrupt raw bit</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_RAW</name>
+              <description>RTC_I2C_MASTER_TRAN_COMP_INT interrupt raw bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>RTC_I2C_TRANS_COMPLETE_INT interrupt raw bit</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>RTC_I2C_TIME_OUT_INT interrupt raw bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_RAW</name>
+              <description>RTC_I2C_ACK_ERR_INT interrupt raw bit</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_DATA_INT_RAW</name>
+              <description>RTC_I2C_RX_DATA_INT interrupt raw bit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DATA_INT_RAW</name>
+              <description>RTC_I2C_TX_DATA_INT interrupt raw bit</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DETECT_START_INT_RAW</name>
+              <description>RTC_I2C_DETECT_START_INT interrupt raw bit</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>RTC I2C interrupt status</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_ST</name>
+              <description>RTC_I2C_SLAVE_TRAN_COMP_INT interrupt status bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>RTC_I2C_ARBITRATION_LOST_INT interrupt status bit</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_ST</name>
+              <description>RTC_I2C_MASTER_TRAN_COMP_INT interrupt status bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ST</name>
+              <description>RTC_I2C_TRANS_COMPLETE_INT interrupt status bit</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ST</name>
+              <description>RTC_I2C_TIME_OUT_INT interrupt status bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_ST</name>
+              <description>RTC_I2C_ACK_ERR_INT interrupt status bit</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_DATA_INT_ST</name>
+              <description>RTC_I2C_RX_DATA_INT interrupt status bit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DATA_INT_ST</name>
+              <description>RTC_I2C_TX_DATA_INT interrupt status bit</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DETECT_START_INT_ST</name>
+              <description>RTC_I2C_DETECT_START_INT interrupt status bit</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Enable RTC I2C interrupt</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_ENA</name>
+              <description>RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>RTC_I2C_ARBITRATION_LOST_INT interrupt enable bit</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_ENA</name>
+              <description>RTC_I2C_MASTER_TRAN_COMP_INT interrupt enable bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ENA</name>
+              <description>RTC_I2C_TRANS_COMPLETE_INT interrupt enable bit</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ENA</name>
+              <description>RTC_I2C_TIME_OUT_INT interrupt enable bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_ENA</name>
+              <description>RTC_I2C_ACK_ERR_INT interrupt enable bit</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DATA_INT_ENA</name>
+              <description>RTC_I2C_RX_DATA_INT interrupt enable bit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DATA_INT_ENA</name>
+              <description>RTC_I2C_TX_DATA_INT interrupt enable bit</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DETECT_START_INT_ENA</name>
+              <description>RTC_I2C_DETECT_START_INT interrupt enable bit</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>RTC I2C read data</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RDATA</name>
+              <description>Data received</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_TX_DATA</name>
+              <description>The data sent by slave</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DONE</name>
+              <description>RTC I2C transmission is done.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-15</dimIndex>
+          <name>CMD%s</name>
+          <description>RTC I2C Command %s</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000903</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND</name>
+              <description>Content of command 0. For more information, please refer to the register
+I2C_COMD0_REG in Chapter I²C Controller</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND_DONE</name>
+              <description>When command 0 is done, this bit changes to 1.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01905310</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SENS</name>
+      <description>Peripheral SENS</description>
+      <groupName>SENS</groupName>
+      <baseAddress>0x3F408800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x110</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SAR_READER1_CTRL</name>
+          <description>RTC ADC1 data and sampling control</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20040002</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_CLK_DIV</name>
+              <description>Clock divider.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_CLK_GATED</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_SAMPLE_NUM</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_DATA_INV</name>
+              <description>Invert SAR ADC1 data.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_INT_EN</name>
+              <description>Enable SAR ADC1 to send out interrupt.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_READER1_STATUS</name>
+          <description>saradc1 status for debug</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR1_READER_STATUS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS1_CTRL1</name>
+          <description>Configure RTC ADC1 controller</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_SARADC_RESET</name>
+              <description>SAR ADC software reset.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_SARADC_CLKGATE_EN</name>
+              <description>Enable bit of SAR ADC clock gate.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XPD_AMP</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_RST_FB_FORCE</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_FORCE</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_GND_FORCE</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS1_CTRL2</name>
+          <description>Control RTC ADC1 conversion and status</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEAS1_DATA_SAR</name>
+              <description>SAR ADC1 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEAS1_DONE_SAR</name>
+              <description>Indicate SAR ADC1 conversion is done.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEAS1_START_SAR</name>
+              <description>SAR ADC1 controller (in RTC) starts conversion, active only when SENS_MEAS1_START_FORCE = 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEAS1_START_FORCE</name>
+              <description>1: SAR ADC1 controller (in RTC) is started by software. 0: SAR ADC1 controller is started by ULP coprocessor.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_EN_PAD</name>
+              <description>SAR ADC1 pad enable bitmap, active only when SENS_SAR1_EN_PAD_FORCE = 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR1_EN_PAD_FORCE</name>
+              <description>1: SAR ADC1 pad enable bitmap is controlled by software. 0: SAR ADC1 pad enable bitmap is controlled by ULP coprocessor.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS1_MUX</name>
+          <description>Select the controller for SAR ADC1</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR1_DIG_FORCE</name>
+              <description>1: SAR ADC1 controlled by DIG ADC1 CTRL</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_ATTEN1</name>
+          <description>Configure SAR ADC1 attenuation</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_ATTEN</name>
+              <description>2-bit attenuation for each pad. [1:0] is used for channel 0, [3:2] is used for channel 1, etc.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_AMP_CTRL1</name>
+          <description>AMP control</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A000A</resetValue>
+          <fields>
+            <field>
+              <name>SAR_AMP_WAIT1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_WAIT2</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_AMP_CTRL2</name>
+          <description>AMP control</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A0000</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_DAC_XPD_FSM_IDLE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SAR_AMP_FSM_IDLE</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_RST_FB_FSM_IDLE</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_FSM_IDLE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_GND_FSM_IDLE</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SAR_FSM_IDLE</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_RSTB_FSM_IDLE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_WAIT3</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_AMP_CTRL3</name>
+          <description>AMP control register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x007338F3</resetValue>
+          <fields>
+            <field>
+              <name>SAR1_DAC_XPD_FSM</name>
+              <description>Control of DAC. 4’b0010: disable DAC. 4’b0000: power up DAC by FSM. 4’b0011: power up DAC by software.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SAR_AMP_FSM</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_RST_FB_FSM</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_FSM</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AMP_SHORT_REF_GND_FSM</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SAR_FSM</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_RSTB_FSM</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_READER2_CTRL</name>
+          <description>RTC ADC2 data and sampling control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40050002</resetValue>
+          <fields>
+            <field>
+              <name>SAR2_CLK_DIV</name>
+              <description>clock divider</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_WAIT_ARB_CYCLE</name>
+              <description>wait arbit stable after sar_done</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_CLK_GATED</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_SAMPLE_NUM</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_DATA_INV</name>
+              <description>Invert SAR ADC2 data</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_INT_EN</name>
+              <description>enable saradc2 to send out interrupt</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_READER2_STATUS</name>
+          <description>saradc2 status for debug</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR2_READER_STATUS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS2_CTRL1</name>
+          <description>configure rtc saradc2</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07020200</resetValue>
+          <fields>
+            <field>
+              <name>SAR2_CNTL_STATE</name>
+              <description>saradc2_cntl_fsm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR2_PWDET_CAL_EN</name>
+              <description>rtc control pwdet enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_PKDET_CAL_EN</name>
+              <description>rtc control pkdet enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_EN_TEST</name>
+              <description>SAR2_EN_TEST</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_RSTB_FORCE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_STANDBY_WAIT</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_RSTB_WAIT</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_XPD_WAIT</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS2_CTRL2</name>
+          <description>Control RTC ADC2 conversion and status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEAS2_DATA_SAR</name>
+              <description>SAR ADC2 data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEAS2_DONE_SAR</name>
+              <description>Indicate SAR ADC2 conversion is done.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEAS2_START_SAR</name>
+              <description>SAR ADC2 controller (in RTC) starts conversion, active only when SENS_MEAS2_START_FORCE = 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEAS2_START_FORCE</name>
+              <description>1: SAR ADC2 controller (in RTC) is started by software. 0: SAR ADC2 controller is started by ULP coprocessor.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_EN_PAD</name>
+              <description>SAR ADC2 pad enable bitmap, active only whenSENS_SAR2_EN_PAD_FORCE = 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_EN_PAD_FORCE</name>
+              <description>1: SAR ADC2 pad enable bitmap is controlled by software. 0: SAR ADC2 pad enable bitmap is controlled by ULP coprocessor.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS2_MUX</name>
+          <description>Select the controller for SAR ADC2</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR2_PWDET_CCT</name>
+              <description>SAR2_PWDET_CCT, PA power detector capacitance tuning.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR2_RTC_FORCE</name>
+              <description>In sleep, force to use RTC to control ADC.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_ATTEN2</name>
+          <description>Configure SAR ADC2 attenuation</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SAR2_ATTEN</name>
+              <description>2-bit attenuation for each pad. [1:0] is used for channel 0, [3:2] is used for channel 1, etc.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_POWER_XPD_SAR</name>
+          <description>configure saradc’s power by sw</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FORCE_XPD_SAR</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARCLK_EN</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR1</name>
+          <description>Configure slave addresses 0-1 of RTC I2C</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SLAVE_ADDR1</name>
+              <description>RTC I2C slave address 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SLAVE_ADDR0</name>
+              <description>RTC I2C slave address 0</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEAS_STATUS</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR2</name>
+          <description>Configure slave addresses 2-3 of RTC I2C</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SLAVE_ADDR3</name>
+              <description>RTC I2C slave address 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SLAVE_ADDR2</name>
+              <description>RTC I2C slave address 2</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR3</name>
+          <description>Configure slave addresses 4-5 of RTC I2C</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SLAVE_ADDR5</name>
+              <description>RTC I2C slave address 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SLAVE_ADDR4</name>
+              <description>RTC I2C slave address 4</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR4</name>
+          <description>Configure slave addresses 6-7 of RTC I2C</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_SLAVE_ADDR7</name>
+              <description>RTC I2C slave address 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_SLAVE_ADDR6</name>
+              <description>RTC I2C slave address 6</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TSENS_CTRL</name>
+          <description>Temperature sensor data control</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00019000</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_OUT</name>
+              <description>Temperature sensor data out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_READY</name>
+              <description>Indicate temperature sensor out ready.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_INT_EN</name>
+              <description>Enable temperature sensor to send out interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_IN_INV</name>
+              <description>Invert temperature sensor data.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_DIV</name>
+              <description>Temperature sensor clock divider.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_POWER_UP</name>
+              <description>Temperature sensor power up.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_POWER_UP_FORCE</name>
+              <description>1: dump out and power up controlled by software. 0: by FSM.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_DUMP_OUT</name>
+              <description>Temperature sensor dump out only active when SENS_TSENS_POWER_UP_FORCE = 1.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TSENS_CTRL2</name>
+          <description>Temperature sensor control</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004002</resetValue>
+          <fields>
+            <field>
+              <name>TSENS_XPD_WAIT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_XPD_FORCE</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLK_INV</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_CLKGATE_EN</name>
+              <description>Enable temperature sensor clock.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_RESET</name>
+              <description>Reset temperature sensor.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_I2C_CTRL</name>
+          <description>Configure RTC I2C transmission</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_I2C_CTRL</name>
+              <description>RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE =
+1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_START</name>
+              <description>Start RTC I2C. Active only when SENS_SAR_I2C_START_FORCE = 1</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_START_FORCE</name>
+              <description>0: RTC I2C started by FSM. 1: RTC I2C started by software.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_CONF</name>
+          <description>Touch sensor configuration register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFF07FFF</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_OUTEN</name>
+              <description>Enable touch controller output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_STATUS_CLR</name>
+              <description>Clear all touch active status.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_DATA_SEL</name>
+              <description>0 and 1: touch_raw_data; 2: base_line; 3: touch_smooth_data.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DENOISE_END</name>
+              <description>Touch denoise done.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_UNIT_END</name>
+              <description>Indicate the completion of sampling.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_PAD2</name>
+              <description>Indicate which pad is selected as proximity pad2</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_PAD1</name>
+              <description>Indicate which pad is selected as proximity pad1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_PAD0</name>
+              <description>Indicate which pad is selected as proximity pad0</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES1</name>
+          <description>Finger threshold for touch pad 1</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH1</name>
+              <description>Finger threshold for touch pad 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES2</name>
+          <description>Finger threshold for touch pad 2</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH2</name>
+              <description>Finger threshold for touch pad 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES3</name>
+          <description>Finger threshold for touch pad 3</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH3</name>
+              <description>Finger threshold for touch pad 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES4</name>
+          <description>Finger threshold for touch pad 4</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH4</name>
+              <description>Finger threshold for touch pad 4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES5</name>
+          <description>Finger threshold for touch pad 5</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH5</name>
+              <description>Finger threshold for touch pad 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES6</name>
+          <description>Finger threshold for touch pad 6</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH6</name>
+              <description>Finger threshold for touch pad 6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES7</name>
+          <description>Finger threshold for touch pad 7</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH7</name>
+              <description>Finger threshold for touch pad 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES8</name>
+          <description>Finger threshold for touch pad 8</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH8</name>
+              <description>Finger threshold for touch pad 8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES9</name>
+          <description>Finger threshold for touch pad 9</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH9</name>
+              <description>Finger threshold for touch pad 9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES10</name>
+          <description>Finger threshold for touch pad 10</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH10</name>
+              <description>Finger threshold for touch pad 10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES11</name>
+          <description>Finger threshold for touch pad 11</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH11</name>
+              <description>Finger threshold for touch pad 11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES12</name>
+          <description>Finger threshold for touch pad 12</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH12</name>
+              <description>Finger threshold for touch pad 12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES13</name>
+          <description>Finger threshold for touch pad 13</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH13</name>
+              <description>Finger threshold for touch pad 13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES14</name>
+          <description>Finger threshold for touch pad 14</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_OUT_TH14</name>
+              <description>Finger threshold for touch pad 14</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_CHN_ST</name>
+          <description>Touch channel status register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD_ACTIVE</name>
+              <description>Touch active status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_CHANNEL_CLR</name>
+              <description>Clear touch channel</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_DONE</name>
+              <description>Signal flag that indicates one touch pad is done.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS0</name>
+          <description>Status of touch controller</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_DENOISE_DATA</name>
+              <description>Denoise measure value from touch sensor 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_CURR</name>
+              <description>Current pad in scan status</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS1</name>
+          <description>Touch pad 1 status</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD1_DATA</name>
+              <description>The data of touch pad 1, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD1_DEBOUNCE</name>
+              <description>Touch pad 1 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS2</name>
+          <description>Touch pad 2 status</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD2_DATA</name>
+              <description>The data of touch pad 2, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD2_DEBOUNCE</name>
+              <description>Touch pad 2 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS3</name>
+          <description>Touch pad 3 status</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD3_DATA</name>
+              <description>The data of touch pad 3, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD3_DEBOUNCE</name>
+              <description>Touch pad 3 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS4</name>
+          <description>Touch pad 4 status</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD4_DATA</name>
+              <description>The data of touch pad 4, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD4_DEBOUNCE</name>
+              <description>Touch pad 4 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS5</name>
+          <description>Touch pad 5 status</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD5_DATA</name>
+              <description>The data of touch pad 5, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD5_DEBOUNCE</name>
+              <description>Touch pad 5 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS6</name>
+          <description>Touch pad 6 status</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD6_DATA</name>
+              <description>The data of touch pad 6, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD6_DEBOUNCE</name>
+              <description>Touch pad 6 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS7</name>
+          <description>Touch pad 7 status</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD7_DATA</name>
+              <description>The data of touch pad 7, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD7_DEBOUNCE</name>
+              <description>Touch pad 7 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS8</name>
+          <description>Touch pad 8 status</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD8_DATA</name>
+              <description>The data of touch pad 8, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD8_DEBOUNCE</name>
+              <description>Touch pad 8 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS9</name>
+          <description>Touch pad 9 status</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD9_DATA</name>
+              <description>The data of touch pad 9, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD9_DEBOUNCE</name>
+              <description>Touch pad 9 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS10</name>
+          <description>Touch pad 10 status</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD10_DATA</name>
+              <description>The data of touch pad 10, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD10_DEBOUNCE</name>
+              <description>Touch pad 10 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS11</name>
+          <description>Touch pad 11 status</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD11_DATA</name>
+              <description>The data of touch pad 11, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD11_DEBOUNCE</name>
+              <description>Touch pad 11 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS12</name>
+          <description>Touch pad 12 status</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD12_DATA</name>
+              <description>The data of touch pad 12, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD12_DEBOUNCE</name>
+              <description>Touch pad 12 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS13</name>
+          <description>Touch pad 13 status</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD13_DATA</name>
+              <description>The data of touch pad 13, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD13_DEBOUNCE</name>
+              <description>Touch pad 13 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS14</name>
+          <description>Touch pad 14 status</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD14_DATA</name>
+              <description>The data of touch pad 14, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD14_DEBOUNCE</name>
+              <description>Touch pad 14 debounce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS15</name>
+          <description>Touch sleep pad status</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_SLP_DATA</name>
+              <description>The data of touch sleep pad, depending on the setting of SENS_TOUCH_DATA_SEL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_DEBOUNCE</name>
+              <description>Touch sleep pad debouce value.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS16</name>
+          <description>Touch approach count status</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_APPROACH_PAD2_CNT</name>
+              <description>Count status of proximity pad 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_PAD1_CNT</name>
+              <description>Count status of proximity pad 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_PAD0_CNT</name>
+              <description>Count status of proximity pad 0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_APPROACH_CNT</name>
+              <description>Count status of sleep pad in proximity mode.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_DAC_CTRL1</name>
+          <description>DAC control</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_FSTEP</name>
+              <description>Frequency step for CW generator can be used to adjust the frequency.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_TONE_EN</name>
+              <description>0: disable CW generator. 1: enable CW generator.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEBUG_BIT_SEL</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_DIG_FORCE</name>
+              <description>0: DAC1 and DAC2 do not use DMA. 1: DAC1 and DAC2 use DMA.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_FORCE_LOW</name>
+              <description>1: force PDAC_CLK to low</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_FORCE_HIGH</name>
+              <description>1: force PDAC_CLK to high</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_INV</name>
+              <description>1: invert PDAC_CLK.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_RESET</name>
+              <description>Reset DAC by software.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLKGATE_EN</name>
+              <description>DAC clock gate enable bit.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_DAC_CTRL2</name>
+          <description>DAC output control</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03000000</resetValue>
+          <fields>
+            <field>
+              <name>DAC_DC1</name>
+              <description>DC offset for DAC1 CW generator.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_DC2</name>
+              <description>DC offset for DAC2 CW generator.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_SCALE1</name>
+              <description>DAC1 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_SCALE2</name>
+              <description>DAC2 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_INV1</name>
+              <description>Invert DAC1. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_INV2</name>
+              <description>Invert DAC2. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CW_EN1</name>
+              <description>1: select CW generator as source for PDAC1_DAC. 0: select register RT- CIO_PDAC1_DAC as source for PDAC1_DAC.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CW_EN2</name>
+              <description>1: select CW generator as source for PDAC2_DAC. 0: select register RT- CIO_PDAC2_DAC as source for PDAC2_DAC.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_STATE</name>
+          <description>ULP-RISCV status</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COCPU_DBG_TRIGGER</name>
+              <description>Trigger ULP-RISCV debug registers</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_CLK_EN</name>
+              <description>Check ULP-RISCV whether clk on</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_RESET_N</name>
+              <description>Check ULP-RISCV whether in reset state</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_EOI</name>
+              <description>Check ULP-RISCV whether in interrupt state</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP</name>
+              <description>Check ULP-RISCV whether in trap state</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_EBREAK</name>
+              <description>Check ULP-RISCV whether in ebreak</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_RAW</name>
+          <description>Interrupt raw bit of ULP-RISCV</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COCPU_TOUCH_DONE_INT_RAW</name>
+              <description>TOUCH_DONE_INT interrupt raw bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TOUCH_INACTIVE_INT_RAW</name>
+              <description>TOUCH_INACTIVE_INT interrupt raw bit</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TOUCH_ACTIVE_INT_RAW</name>
+              <description>TOUCH_ACTIVE_INT interrupt raw bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_SARADC1_INT_RAW</name>
+              <description>SARADC1_DONE_INT interrupt raw bit</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_SARADC2_INT_RAW</name>
+              <description>SARADC2_DONE_INT interrupt raw bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TSENS_INT_RAW</name>
+              <description>TSENS_DONE_INT interrupt raw bit</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_START_INT_RAW</name>
+              <description>RISCV_START_INT interrupt raw bit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_SW_INT_RAW</name>
+              <description>SW_INT interrupt raw bit</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_SWD_INT_RAW</name>
+              <description>SWD_INT interrupt raw bit</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_ENA</name>
+          <description>Interrupt enable bit of ULP-RISCV</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COCPU_TOUCH_DONE_INT_ENA</name>
+              <description>TOUCH_DONE_INT interrupt enable bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_TOUCH_INACTIVE_INT_ENA</name>
+              <description>TOUCH_INACTIVE_INT interrupt enable bit</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_TOUCH_ACTIVE_INT_ENA</name>
+              <description>TOUCH_ACTIVE_INT interrupt enable bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SARADC1_INT_ENA</name>
+              <description>SARADC1_DONE_INT interrupt enable bit</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SARADC2_INT_ENA</name>
+              <description>SARADC2_DONE_INT interrupt enable bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_TSENS_INT_ENA</name>
+              <description>TSENS_DONE_INT interrupt enable bit</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_START_INT_ENA</name>
+              <description>RISCV_START_INT interrupt enable bit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SW_INT_ENA</name>
+              <description>SW_INT interrupt enable bit</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SWD_INT_ENA</name>
+              <description>SWD_INT interrupt enable bit</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_ST</name>
+          <description>Interrupt status bit of ULP-RISCV</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COCPU_TOUCH_DONE_INT_ST</name>
+              <description>TOUCH_DONE_INT interrupt status bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TOUCH_INACTIVE_INT_ST</name>
+              <description>TOUCH_INACTIVE_INT interrupt status bit</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TOUCH_ACTIVE_INT_ST</name>
+              <description>TOUCH_ACTIVE_INT interrupt status bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_SARADC1_INT_ST</name>
+              <description>SARADC1_DONE_INT interrupt status bit</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_SARADC2_INT_ST</name>
+              <description>SARADC2_DONE_INT interrupt status bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TSENS_INT_ST</name>
+              <description>TSENS_DONE_INT interrupt status bit</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_START_INT_ST</name>
+              <description>RISCV_START_INT interrupt status bit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_SW_INT_ST</name>
+              <description>SW_INT interrupt status bit</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_SWD_INT_ST</name>
+              <description>SWD_INT interrupt status bit</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_CLR</name>
+          <description>Interrupt clear bit of ULP-RISCV</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COCPU_TOUCH_DONE_INT_CLR</name>
+              <description>TOUCH_DONE_INT interrupt clear bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_TOUCH_INACTIVE_INT_CLR</name>
+              <description>TOUCH_INACTIVE_INT interrupt clear bit</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_TOUCH_ACTIVE_INT_CLR</name>
+              <description>TOUCH_ACTIVE_INT interrupt clear bit</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_SARADC1_INT_CLR</name>
+              <description>SARADC1_DONE_INT interrupt clear bit</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_SARADC2_INT_CLR</name>
+              <description>SARADC2_DONE_INT interrupt clear bit</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_TSENS_INT_CLR</name>
+              <description>TSENS_DONE_INT interrupt clear bit</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_START_INT_CLR</name>
+              <description>RISCV_START_INT interrupt clear bit</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_SW_INT_CLR</name>
+              <description>SW_INT interrupt clear bit</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_SWD_INT_CLR</name>
+              <description>SWD_INT interrupt clear bit</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_DEBUG</name>
+          <description>ULP-RISCV debug register</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COCPU_PC</name>
+              <description>ULP-RISCV Program counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_MEM_VLD</name>
+              <description>ULP-RISCV memory valid output</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_MEM_RDY</name>
+              <description>ULP-RISCV memory ready input</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_MEM_WEN</name>
+              <description>ULP-RISCV memory write enable output</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_MEM_ADDR</name>
+              <description>ULP-RISCV memory address output</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_HALL_CTRL</name>
+          <description>hall control</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xA0000000</resetValue>
+          <fields>
+            <field>
+              <name>XPD_HALL</name>
+              <description>Power on hall sensor and connect to VP and VN</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_HALL_FORCE</name>
+              <description>1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HALL_PHASE</name>
+              <description>Reverse phase of hall sensor</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HALL_PHASE_FORCE</name>
+              <description>1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled by FSM in ULP-coprocessor</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_NOUSE</name>
+          <description>sar nouse</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_NOUSE</name>
+              <description>sar nouse</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_IO_MUX_CONF</name>
+          <description>Configure and reset IO MUX</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IOMUX_RESET</name>
+              <description>Reset IO MUX by software</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IOMUX_CLK_GATE_EN</name>
+              <description>IO MUX clock gate enable bit</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SARDATE</name>
+          <description>Version Control Register</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01906140</resetValue>
+          <fields>
+            <field>
+              <name>SAR_DATE</name>
+              <description>Version Control Register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SHA</name>
+      <description>SHA (Secure Hash Algorithm) Accelerator</description>
+      <groupName>SHA</groupName>
+      <baseAddress>0x6003B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xF0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SHA</name>
+        <value>55</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Defines the algorithm of SHA accelerator</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Defines the SHA algorithm.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_STRING</name>
+          <description>String content register for calculating initial Hash Value (only effective for SHA-512/t)</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_STRING</name>
+              <description>Defines t_string for calculating the initial Hash value for SHA-512/t.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_LENGTH</name>
+          <description>String length register for calculating initial Hash Value (only effective for SHA-512/t)</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LENGTH</name>
+              <description>Defines t_length for calculating the initial Hash value for SHA-512/t.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_BLOCK_NUM</name>
+          <description>Block number register (only effective for DMA-SHA)</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_BLOCK_NUM</name>
+              <description>Defines the DMA-SHA block number.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>START</name>
+          <description>Starts the SHA accelerator for Typical SHA operation</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>Write 1 to start Typical SHA calculation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE_OP</name>
+          <description>Continues SHA operation (only effective in Typical SHA mode)</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE_OP</name>
+              <description>Write 1 to continue Typical SHA calculation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSY</name>
+          <description>Indicates if SHA Accelerator is busy or not</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Indicates the states of SHA accelerator.
+1'h0: idle
+1'h1: busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_START</name>
+          <description>Starts the SHA accelerator for DMA-SHA operation</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_START</name>
+              <description>Write 1 to start DMA-SHA calculation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONTINUE</name>
+          <description>Continues SHA operation (only effective in DMA-SHA mode)</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CONTINUE</name>
+              <description>Write 1 to continue DMA-SHA calculation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLEAR</name>
+          <description>DMA-SHA interrupt clear register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>Clears DMA-SHA interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>DMA-SHA interrupt enable register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT_ENA</name>
+              <description>Enables DMA-SHA interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20190402</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>H_%s</name>
+          <description>Hash value</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_0</name>
+              <description>Stores the %sth 32-bit piece of the Hash value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>M_%s</name>
+          <description>Message</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M_0</name>
+              <description>Stores the %sth 32-bit piece of the message.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI0</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI</groupName>
+      <baseAddress>0x3F403000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x108</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CMD</name>
+          <description>Command control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONF_BITLEN</name>
+              <description>Define the spi_clk cycles of  SPI_CONF state. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address value</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_ADDR_VALUE</name>
+              <description>[31:8]:address to slave, [7:0]:Reserved. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>SPI control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x002C0000</resetValue>
+          <fields>
+            <field>
+              <name>EXT_HOLD_EN</name>
+              <description>Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUMMY_OUT</name>
+              <description>In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_OCT</name>
+              <description>Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_OCT</name>
+              <description>Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_OCT</name>
+              <description>In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_BIT_ORDER</name>
+              <description>In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WR_BIT_ORDER</name>
+              <description>In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL1</name>
+          <description>SPI control register 1</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004010</resetValue>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_MODE_13</name>
+              <description>{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSCK_DATA_OUT</name>
+              <description>It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>W16_17_WR_ENA</name>
+              <description>1:SPI_BUF16~SPI_BUF17 can be written   0:SPI_BUF16~SPI_BUF17 can not  be written. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_DELAY</name>
+              <description>SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>SPI control register 2</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002000</resetValue>
+          <fields>
+            <field>
+              <name>CS_SETUP_TIME</name>
+              <description>(cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_TIME</name>
+              <description>delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_DELAY_MODE</name>
+              <description>spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle  else delayed by one cycle 2: if SPI_CK_OUT_EDGE or  SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_DELAY_NUM</name>
+              <description>spi_cs signal is delayed by system clock cycles. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI clock control register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80003043</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>In the master mode it must be equal to SPI_CLKCNT_N. In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>In the master mode it must be floor((SPI_CLKCNT_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(SPI_CLKDIV_PRE+1)/(SPI_CLKCNT_N+1). Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKDIV_PRE</name>
+              <description>In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI USER control register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x800000C0</resetValue>
+          <fields>
+            <field>
+              <name>DOUTDIN</name>
+              <description>Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>QPI_MODE</name>
+              <description>Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OPI_MODE</name>
+              <description>Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_BYTE_ORDER</name>
+              <description>In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WR_BYTE_ORDER</name>
+              <description>In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DUAL</name>
+              <description>In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QUAD</name>
+              <description>In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_OCT</name>
+              <description>In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_CONF_NXT</name>
+              <description>1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIO</name>
+              <description>Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_HOLD_POL</name>
+              <description>It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DOUT_HOLD</name>
+              <description>spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DIN_HOLD</name>
+              <description>spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_HOLD</name>
+              <description>spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_HOLD</name>
+              <description>spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_CMD_HOLD</name>
+              <description>spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_PREP_HOLD</name>
+              <description>spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR</name>
+              <description>This bit enable the address phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI USER control register 1</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xB8000007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI USER control register 2</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of  command. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MOSI_DLEN</name>
+          <description>MOSI length</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MOSI_DBITLEN</name>
+              <description>The length in bits of write-data. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISO_DLEN</name>
+          <description>MISO length</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MISO_DBITLEN</name>
+              <description>The length in bits of  read-data. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI misc register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003E</resetValue>
+          <fields>
+            <field>
+              <name>CS0_DIS</name>
+              <description>SPI CS0 pin enable, 1: disable CS0, 0: SPI_CS0 signal is from/to CS0 pin. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS1_DIS</name>
+              <description>SPI CS1 pin enable, 1: disable CS1, 0: SPI_CS1 signal is from/to CS1 pin. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS2_DIS</name>
+              <description>SPI CS2 pin enable, 1: disable CS2, 0: SPI_CS2 signal is from/to CS2 pin. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS3_DIS</name>
+              <description>SPI CS3 pin enable, 1: disable CS3, 0: SPI_CS3 signal is from/to CS3 pin. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS4_DIS</name>
+              <description>SPI CS4 pin enable, 1: disable CS4, 0: SPI_CS4 signal is from/to CS4 pin. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS5_DIS</name>
+              <description>SPI CS5 pin enable, 1: disable CS5, 0: SPI_CS5 signal is from/to CS5 pin. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_DIS</name>
+              <description>1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_CS_POL</name>
+              <description>In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DATA_DTR_EN</name>
+              <description>1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMD_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CD_DATA_SET</name>
+              <description>1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DOUT or SPI_DIN state.  0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CD_DUMMY_SET</name>
+              <description>1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DUMMY state.  0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CD_ADDR_SET</name>
+              <description>1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_ADDR state.  0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_CS_POL</name>
+              <description>spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DQS_IDLE_EDGE</name>
+              <description>The default value of spi_dqs. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CD_CMD_SET</name>
+              <description>1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_CMD state.  0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CD_IDLE_EDGE</name>
+              <description>The default value of spi_cd. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>QUAD_DIN_PIN_SWAP</name>
+              <description>1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE</name>
+          <description>SPI slave control register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>TRANS_DONE</name>
+              <description>The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.  Can not be changed by CONF_buf.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_RD_BUF_DONE_EN</name>
+              <description>SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_WR_BUF_DONE_EN</name>
+              <description>SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_RD_DMA_DONE_EN</name>
+              <description>SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_WR_DMA_DONE_EN</name>
+              <description>SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TRANS_DONE_EN</name>
+              <description>SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_DMA_SEG_TRANS_EN</name>
+              <description>SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_EN</name>
+              <description>1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_CNT</name>
+              <description>The operations counter in both the master mode and the slave mode.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_AUTO_CLR_EN</name>
+              <description>SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE.  0:disable. 1: enable. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Set SPI work mode. 1: slave mode 0: master mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOFT_RESET</name>
+              <description>Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE1</name>
+          <description>SPI slave control register 1</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_ADDR_ERR_CLR</name>
+              <description>1: Clear SPI_SLV_ADDR_ERR. 0: not valid. Can be changed by CONF_buf.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_CLR</name>
+              <description>1: Clear SPI_SLV_CMD_ERR. 0: not valid.  Can be changed by CONF_buf.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_NO_QPI_EN</name>
+              <description>1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_ADDR_ERR</name>
+              <description>1: The address value of the last SPI transfer is not supported by SPI slave. 0: The address value is supported or no address value is received.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR</name>
+              <description>1: The command value of the last SPI transfer is not supported by SPI slave. 0: The command value is supported or no command value is received.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE</name>
+              <description>The interrupt raw bit for the completion of dma write operation in the slave mode.  Can not be changed by CONF_buf.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_COMMAND</name>
+              <description>In the slave mode it is the value of command.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_ADDR</name>
+              <description>In the slave mode it is the value of address.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLV_WRBUF_DLEN</name>
+          <description>SPI slave Wr_BUF interrupt and CONF control register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xD8000000</resetValue>
+          <fields>
+            <field>
+              <name>SLV_WR_BUF_DONE</name>
+              <description>The interrupt raw bit for the completion of write-buffer operation in the slave mode.  Can not be changed by CONF_buf.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONF_BASE_BITLEN</name>
+              <description>The basic spi_clk cycles of CONF state. The real cycle length of CONF state, if SPI_USR_CONF is enabled, is SPI_CONF_BASE_BITLEN[6:0] + SPI_CONF_BITLEN[23:0].</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLV_RDBUF_DLEN</name>
+          <description>SPI magic error and slave control register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_DMA_RD_BYTELEN</name>
+              <description>In the slave mode it is the length in bytes for read operations. The register value shall be byte_num.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE</name>
+              <description>The interrupt raw bit for the completion of read-buffer operation in the slave mode.  Can not be changed by CONF_buf.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR</name>
+              <description>1: The recent magic value in CONF buffer is not right in master DMA seg-trans mode. 0: others.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLV_RD_BYTE</name>
+          <description>SPI interrupt control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0A000000</resetValue>
+          <fields>
+            <field>
+              <name>SLV_DATA_BYTELEN</name>
+              <description>The full-duplex or half-duplex data byte length of the last SPI transfer in slave mode. In half-duplex mode, this value is controlled by bits [23:20].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDDMA_BYTELEN_EN</name>
+              <description>1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRDMA_BYTELEN_EN</name>
+              <description>1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDBUF_BYTELEN_EN</name>
+              <description>1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRBUF_BYTELEN_EN</name>
+              <description>1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_MAGIC_VALUE</name>
+              <description>The magic value of BM table in master DMA seg-trans.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE</name>
+              <description>The interrupt raw bit for the completion of Rd-DMA operation in the slave mode.  Can not be changed by CONF_buf.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_CONF</name>
+              <description>1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM</name>
+          <description>SPI master status and DMA read byte control register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST</name>
+              <description>The status of spi state machine. 0: idle state, 1: preparation state, 2: send command state, 3: send data state, 4: red data state, 5:write data state, 6: wait state, 7: done state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_DMA_RD_BYTELEN</name>
+              <description>Define the master DMA read byte length in non seg-conf-trans or seg-conf-trans mode. Invalid when SPI_RX_EOF_EN is 0. Can be configured in CONF state..</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOLD</name>
+          <description>SPI hold register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_HOLD_ENA</name>
+              <description>This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set, if the other SPI is busy, the SPI will be hold. 1(3): hold at  idle  phase 2: hold at  prepare  phase. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VAL</name>
+              <description>spi hold output value, which should be used with SPI_HOLD_OUT_EN. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EN</name>
+              <description>Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with SPI_EXT_HOLD_EN and other usr hold signals. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TIME</name>
+              <description>set the hold cycles of output spi_hold signal when SPI_HOLD_OUT_EN is enable. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE</name>
+              <description>1:  spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-trans is not ended or not occurred.  Can not be changed by CONF_buf.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>SPI DMA control register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>The bit is used to reset in dma fsm and in data fifo pointer.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_RST</name>
+              <description>The bit is used to reset out dma fsm and out data fifo pointer.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_FIFO_RST</name>
+              <description>Reset spi dma ahb master fifo pointer.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_RST</name>
+              <description>Reset spi dma ahb master.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>Set bit to test in link.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>Set bit to test out link.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>when the bit is set, DMA continue to use the next inlink node when the length of inlink is 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>out eof flag generation mode . 1: when dma pop all data from fifo  0:when ahb push all data to fifo.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>read descriptor use burst mode when read data for memory.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>read descriptor use burst mode when write data to memory.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <description>spi dma read data from memory in burst mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <description>1: Internal memory data transfer enable bit. Send SPI DMA RX buffer data to SPI DMA TX buffer. 0: Disable this function.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_STOP</name>
+              <description>spi dma read data stop  when in continue tx/rx mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_STOP</name>
+              <description>spi dma write data stop when in continue tx/rx mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_CONTINUE</name>
+              <description>spi dma continue tx/rx data.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_SEG_POP_CLR</name>
+              <description>1: Clear spi_slv_seg_frt_pop_mask. 0 : others</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SLV_SEG_TRANS_EN</name>
+              <description>Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_infifo_full_vld is cleared by spi slave CMD5. 0: spi_dma_infifo_full_vld is cleared by SPI_TRANS_DONE.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_TX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_outfifo_empty_vld is cleared by spi slave CMD6. 0: spi_dma_outfifo_empty_vld is cleared by SPI_TRANS_DONE.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_EOF_EN</name>
+              <description>1: SPI_IN_SUC_EOF_INT_RAW is set when the number of dma pushed data bytes is equal to the value of SPI_SLV_DMA_RD_BYTELEN[19:0]/ SPI_MST_DMA_RD_BYTELEN[19:0] in spi dma transition.  0: SPI_IN_SUC_EOF_INT_RAW is set by SPI_TRANS_DONE in non-seg-trans or SPI_DMA_SEG_TRANS_DONE in seg-trans.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_CLR</name>
+              <description>1:Clear spi_dma_infifo_full_vld. 0: Do not control it.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_CLR</name>
+              <description>1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_MEM_BK_SIZE</name>
+              <description>Select the external memory block size.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_CLR</name>
+              <description>1: End slave seg-trans, which acts as 0x05 command. 2 or more end seg-trans signals will induce error in DMA RX.  0: others. Will be cleared in 1 APB CLK cycles by hardware..</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_LINK</name>
+          <description>SPI DMA TX link configuration</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>The address of the first outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set the bit to stop to use outlink descriptor.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set the bit to start to use outlink descriptor.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set the bit to mount on new outlink descriptors.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_ENA</name>
+              <description>spi dma write data status bit.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_LINK</name>
+          <description>SPI DMA RX link configuration</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>The address of the first inlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET</name>
+              <description>when the bit is set, the inlink descriptor returns to the first link node when a packet is error.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set the bit to stop to use inlink descriptor.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set the bit to start to use inlink descriptor.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set the bit to mount on new inlink descriptors.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_ENA</name>
+              <description>SPI DMA read data status bit.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ENA</name>
+          <description>SPI DMA interrupt enable register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_EMPTY_INT_ENA</name>
+              <description>The enable bit for lack of enough inlink descriptors. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_DSCR_ERROR_INT_ENA</name>
+              <description>The enable bit for outlink descriptor error. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_DSCR_ERROR_INT_ENA</name>
+              <description>The enable bit for inlink descriptor error. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ENA</name>
+              <description>The enable bit for completing usage of a inlink descriptor. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ENA</name>
+              <description>The enable bit for receiving error. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ENA</name>
+              <description>The enable bit for completing receiving all the packets from host. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ENA</name>
+              <description>The enable bit for completing usage of a outlink descriptor . Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ENA</name>
+              <description>The enable bit for sending a packet to host done. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ENA</name>
+              <description>The enable bit for sending all the packets to host done. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_FULL_ERR_INT_ENA</name>
+              <description>The enable bit for infifo full error interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for outfifo empty error interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD6_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD6 interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_ENA</name>
+              <description>The enable bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_RAW</name>
+          <description>SPI DMA interrupt raw register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_EMPTY_INT_RAW</name>
+              <description>The raw bit for lack of enough inlink descriptors. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_DSCR_ERROR_INT_RAW</name>
+              <description>The raw bit for outlink descriptor error. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INLINK_DSCR_ERROR_INT_RAW</name>
+              <description>The raw bit for inlink descriptor error. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_RAW</name>
+              <description>The raw bit for completing usage of a inlink descriptor. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_RAW</name>
+              <description>The raw bit for receiving error. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_RAW</name>
+              <description>The raw bit for completing receiving all the packets from host. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_RAW</name>
+              <description>The raw bit for completing usage of a outlink descriptor. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <description>The raw bit for sending a packet to host done. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_RAW</name>
+              <description>The raw bit for sending all the packets to host done. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_FULL_ERR_INT_RAW</name>
+              <description>1:SPI_DMA_INFIFO_FULL and spi_push_data_prep are valid, which means that DMA Rx buffer is full but push is valid.  0: Others.  Can not be changed by CONF_buf.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY_ERR_INT_RAW</name>
+              <description>1:SPI_DMA_OUTFIFO_EMPTY and spi_pop_data_prep are valid, which means that there is no data to pop but pop is valid.  0: Others.  Can not be changed by CONF_buf.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD6_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD6 interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_RAW</name>
+              <description>The raw bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ST</name>
+          <description>SPI DMA interrupt status register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_EMPTY_INT_ST</name>
+              <description>The status bit for lack of enough inlink descriptors.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_DSCR_ERROR_INT_ST</name>
+              <description>The status bit for outlink descriptor error.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INLINK_DSCR_ERROR_INT_ST</name>
+              <description>The status bit for inlink descriptor error.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ST</name>
+              <description>The status bit for completing usage of a inlink descriptor.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ST</name>
+              <description>The status bit for receiving error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ST</name>
+              <description>The status bit for completing receiving all the packets from host.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ST</name>
+              <description>The status bit for completing usage of a outlink descriptor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ST</name>
+              <description>The status bit for sending a packet to host done.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ST</name>
+              <description>The status bit for sending all the packets to host done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_FULL_ERR_INT_ST</name>
+              <description>The status bit for infifo full error.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY_ERR_INT_ST</name>
+              <description>The status bit for outfifo empty error.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD6_INT_ST</name>
+              <description>The status bit for SPI slave CMD6 interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_ST</name>
+              <description>The status bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_ST</name>
+              <description>The status bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_ST</name>
+              <description>The status bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_ST</name>
+              <description>The status bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_CLR</name>
+          <description>SPI DMA interrupt clear register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_EMPTY_INT_CLR</name>
+              <description>The clear bit for lack of enough inlink descriptors. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_DSCR_ERROR_INT_CLR</name>
+              <description>The clear bit for outlink descriptor error. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_DSCR_ERROR_INT_CLR</name>
+              <description>The clear bit for inlink descriptor error. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_CLR</name>
+              <description>The clear bit for completing usage of a inlink descriptor. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_CLR</name>
+              <description>The clear bit for receiving error. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_CLR</name>
+              <description>The clear bit for completing receiving all the packets from host. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_CLR</name>
+              <description>The clear bit for completing usage of a outlink descriptor. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_CLR</name>
+              <description>The clear bit for sending a packet to host done. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_CLR</name>
+              <description>The clear bit for sending all the packets to host done. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_FULL_ERR_INT_CLR</name>
+              <description>1: Clear SPI_INFIFO_FULL_ERR_INT_RAW. 0: not valid. Can be changed by CONF_buf.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY_ERR_INT_CLR</name>
+              <description>1: Clear SPI_OUTFIFO_EMPTY_ERR_INT_RAW signal. 0: not valid. Can be changed by CONF_buf.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD6_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD6 interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_CLR</name>
+              <description>The clear bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_ERR_EOF_DES_ADDR</name>
+          <description>The latest SPI DMA  RX descriptor address receiving error</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_IN_ERR_EOF_DES_ADDR</name>
+              <description>The inlink descriptor address when spi dma produce receiving error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_SUC_EOF_DES_ADDR</name>
+          <description>The latest SPI DMA  eof RX descriptor address</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_IN_SUC_EOF_DES_ADDR</name>
+              <description>The last inlink descriptor address when spi dma produce from_suc_eof.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR</name>
+          <description>Current SPI DMA RX descriptor pointer</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INLINK_DSCR</name>
+              <description>The content of current in descriptor pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR_BF0</name>
+          <description>Next SPI DMA RX descriptor pointer</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INLINK_DSCR_BF0</name>
+              <description>The content of next in descriptor pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INLINK_DSCR_BF1</name>
+          <description>Current SPI DMA RX buffer pointer</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INLINK_DSCR_BF1</name>
+              <description>The content of current in descriptor data buffer pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_BFR_DES_ADDR</name>
+          <description>The latest SPI DMA  eof TX buffer address</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUT_EOF_BFR_DES_ADDR</name>
+              <description>The address of buffer relative to the outlink descriptor that produce eof.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EOF_DES_ADDR</name>
+          <description>The latest SPI DMA  eof TX descriptor address</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUT_EOF_DES_ADDR</name>
+              <description>The last outlink descriptor address when spi dma produce to_eof.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR</name>
+          <description>Current SPI DMA TX descriptor pointer</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUTLINK_DSCR</name>
+              <description>The content of current out descriptor pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR_BF0</name>
+          <description>Next SPI DMA TX descriptor pointer</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUTLINK_DSCR_BF0</name>
+              <description>The content of next out descriptor pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUTLINK_DSCR_BF1</name>
+          <description>Current SPI DMA TX buffer pointer</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_OUTLINK_DSCR_BF1</name>
+              <description>The content of current out descriptor data buffer pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUTSTATUS</name>
+          <description>SPI DMA TX status</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUTDSCR_ADDR</name>
+              <description>SPI dma out descriptor address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTDSCR_STATE</name>
+              <description>SPI dma out descriptor state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUT_STATE</name>
+              <description>SPI dma out data state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_CNT</name>
+              <description>The remains of SPI dma outfifo data.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_FULL</name>
+              <description>SPI dma outfifo is full.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY</name>
+              <description>SPI dma outfifo is empty.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INSTATUS</name>
+          <description>SPI DMA RX status</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>DMA_INDSCR_ADDR</name>
+              <description>SPI dma in descriptor address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INDSCR_STATE</name>
+              <description>SPI dma in descriptor state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_IN_STATE</name>
+              <description>SPI dma in data state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_CNT</name>
+              <description>The remains of SPI dma infifo data.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL</name>
+              <description>SPI dma infifo is full.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_EMPTY</name>
+              <description>SPI dma infifo is empty.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W0</name>
+          <description>Data buffer 0</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF0</name>
+              <description>32 bits data buffer 0, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W1</name>
+          <description>Data buffer 1</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF1</name>
+              <description>32 bits data buffer 1, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W2</name>
+          <description>Data buffer 2</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF2</name>
+              <description>32 bits data buffer 2, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W3</name>
+          <description>Data buffer 3</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF3</name>
+              <description>32 bits data buffer 3, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W4</name>
+          <description>Data buffer 4</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF4</name>
+              <description>32 bits data buffer 4, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W5</name>
+          <description>Data buffer 5</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF5</name>
+              <description>32 bits data buffer 5, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W6</name>
+          <description>Data buffer 6</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF6</name>
+              <description>32 bits data buffer 6, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W7</name>
+          <description>Data buffer 7</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF7</name>
+              <description>32 bits data buffer 7, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W8</name>
+          <description>Data buffer 8</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF8</name>
+              <description>32 bits data buffer 8, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W9</name>
+          <description>Data buffer 9</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF9</name>
+              <description>32 bits data buffer 9, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W10</name>
+          <description>Data buffer 10</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF10</name>
+              <description>32 bits data buffer 10, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W11</name>
+          <description>Data buffer 11</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF11</name>
+              <description>32 bits data buffer 11, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W12</name>
+          <description>Data buffer 12</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF12</name>
+              <description>32 bits data buffer 12, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W13</name>
+          <description>Data buffer 13</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF13</name>
+              <description>32 bits data buffer 13, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W14</name>
+          <description>Data buffer 14</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF14</name>
+              <description>32 bits data buffer 14, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W15</name>
+          <description>Data buffer 15</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF15</name>
+              <description>32 bits data buffer 15, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W16</name>
+          <description>Data buffer 16</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF16</name>
+              <description>32 bits data buffer 16, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W17</name>
+          <description>Data buffer 17</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF17</name>
+              <description>32 bits data buffer 17, transferred in the unit of byte. Byte addressable in slave half-duplex mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_MODE</name>
+          <description>SPI input delay mode configuration</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN4_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN5_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN6_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN7_MODE</name>
+              <description>the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMING_CLK_ENA</name>
+              <description>1:enable hclk in spi_timing.v.  0: disable it. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_NUM</name>
+          <description>SPI input delay number configuration</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN4_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN5_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN6_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN7_NUM</name>
+              <description>the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOUT_MODE</name>
+          <description>SPI output delay mode configuration</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DOUT0_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT1_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT2_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT3_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT4_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT5_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT6_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT7_MODE</name>
+              <description>the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOUT_NUM</name>
+          <description>SPI output delay number configuration</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DOUT0_NUM</name>
+              <description>the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT1_NUM</name>
+              <description>the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT2_NUM</name>
+              <description>the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT3_NUM</name>
+              <description>the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT4_NUM</name>
+              <description>the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT5_NUM</name>
+              <description>the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT6_NUM</name>
+              <description>the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT7_NUM</name>
+              <description>the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_CTRL</name>
+          <description>LCD frame control register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_HB_FRONT</name>
+              <description>It is the horizontal blank front porch of a frame. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_VA_HEIGHT</name>
+              <description>It is the vertical active height of a frame. Can be configured in CONF state.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_VT_HEIGHT</name>
+              <description>It is the vertical total height of a frame. Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_MODE_EN</name>
+              <description>1: Enable LCD mode output vsync, hsync, de. 0: Disable. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_CTRL1</name>
+          <description>LCD frame control1 register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_VB_FRONT</name>
+              <description>It is the vertical blank front porch of a frame. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HA_WIDTH</name>
+              <description>It is the horizontal active width of a frame. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HT_WIDTH</name>
+              <description>It is the horizontal total width of a frame. Can be configured in CONF state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_CTRL2</name>
+          <description>LCD frame control2 register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010001</resetValue>
+          <fields>
+            <field>
+              <name>LCD_VSYNC_WIDTH</name>
+              <description>It is the position of spi_vsync active pulse in a line. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VSYNC_IDLE_POL</name>
+              <description>It is the idle value of spi_vsync. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HSYNC_WIDTH</name>
+              <description>It is the position of spi_hsync active pulse in a line. Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSYNC_IDLE_POL</name>
+              <description>It is the idle value of spi_hsync. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HSYNC_POSITION</name>
+              <description>It is the position of spi_hsync active pulse in a line. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_D_MODE</name>
+          <description>LCD delay number</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DQS_MODE</name>
+              <description>the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CD_MODE</name>
+              <description>the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_DE_MODE</name>
+              <description>the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_HSYNC_MODE</name>
+              <description>the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_VSYNC_MODE</name>
+              <description>the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DE_IDLE_POL</name>
+              <description>It is the idle value of spi_de.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HS_BLANK_EN</name>
+              <description>1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_D_NUM</name>
+          <description>LCD delay mode</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DQS_NUM</name>
+              <description>the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CD_NUM</name>
+              <description>the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_DE_NUM</name>
+              <description>the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_HSYNC_NUM</name>
+              <description>the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_VSYNC_NUM</name>
+              <description>the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_DATE</name>
+          <description>SPI version control</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01907240</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+      <name>SPI1</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x3F402000</baseAddress>
+      <interrupt>
+        <name>SPI1</name>
+        <value>32</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+      <name>SPI2</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x3F424000</baseAddress>
+      <interrupt>
+        <name>SPI2</name>
+        <value>33</value>
+      </interrupt>
+      <interrupt>
+        <name>SPI2_DMA</name>
+        <value>57</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+      <name>SPI3</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x3F425000</baseAddress>
+      <interrupt>
+        <name>SPI3</name>
+        <value>34</value>
+      </interrupt>
+      <interrupt>
+        <name>SPI3_DMA</name>
+        <value>58</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="SPI0">
+      <name>SPI4</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x3F437000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>SYSTEM</name>
+      <description>System</description>
+      <groupName>SYSTEM</groupName>
+      <baseAddress>0x3F4C0000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x94</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>ROM_CTRL_0</name>
+          <description>System ROM configuration register 0</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>ROM_FO</name>
+              <description>This field is used to force on clock gate of internal ROM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ROM_CTRL_1</name>
+          <description>System ROM configuration register 1</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000C</resetValue>
+          <fields>
+            <field>
+              <name>ROM_FORCE_PD</name>
+              <description>This field is used to power down internal ROM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ROM_FORCE_PU</name>
+              <description>This field is used to power up internal ROM.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_CTRL_0</name>
+          <description>System SRAM configuration register 0</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_FO</name>
+              <description>This field is used to force on clock gate of internal SRAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_CTRL_1</name>
+          <description>System SRAM configuration register 1</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SRAM_FORCE_PD</name>
+              <description>This field is used to power down internal SRAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_CLK_EN</name>
+          <description>CPU peripheral clock enable register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN_DEDICATED_GPIO</name>
+              <description>Set this bit to enable clock of DEDICATED GPIO module.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_RST_EN</name>
+          <description>CPU peripheral reset register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>RST_EN_DEDICATED_GPIO</name>
+              <description>Set this bit to reset DEDICATED GPIO module.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PER_CONF</name>
+          <description>CPU peripheral clock configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000C</resetValue>
+          <fields>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <description>This field is used to select the clock frequency of CPU or CPU period.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FREQ_SEL</name>
+              <description>This field is used to select the PLL clock frequency based on CPU period.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_WAIT_MODE_FORCE_ON</name>
+              <description>Set this bit to force on CPU wait mode. In this mode, the clock gate of CPU is turned off until any interrupts happen. This mode could also be force on via WAITI instruction.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_WAITI_DELAY_NUM</name>
+              <description>Sets the number of delay cycles to enter CPU wait mode after a WAITI instruction.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JTAG_CTRL_0</name>
+          <description>JTAG configuration register 0</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0</name>
+              <description>Stores the 0 to 31 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JTAG_CTRL_1</name>
+          <description>JTAG configuration register 1</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1</name>
+              <description>Stores the 32 to 63 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JTAG_CTRL_2</name>
+          <description>JTAG configuration register 2</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2</name>
+              <description>Stores the 64 to 95 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JTAG_CTRL_3</name>
+          <description>JTAG configuration register 3</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3</name>
+              <description>Stores the 96 to 127 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JTAG_CTRL_4</name>
+          <description>JTAG configuration register 4</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4</name>
+              <description>Stores the 128 to 159 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JTAG_CTRL_5</name>
+          <description>JTAG configuration register 5</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5</name>
+              <description>Stores the 160 to 191 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JTAG_CTRL_6</name>
+          <description>JTAG configuration register 6</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6</name>
+              <description>Stores the 192 to 223 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JTAG_CTRL_7</name>
+          <description>JTAG configuration register 7</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7</name>
+              <description>Stores the 0 to 224 bits of the 255 bits register used to cancel the temporary disable of eFuse to JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_PD_MASK</name>
+          <description>Memory power-related controlling register (under low-sleep)</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>LSLP_MEM_PD_MASK</name>
+              <description>Set this bit to allow the memory to work as usual when the chip enters the light-sleep state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_CLK_EN0</name>
+          <description>System peripheral clock (for hardware accelerators) enable register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xF9C1E06F</resetValue>
+          <fields>
+            <field>
+              <name>TIMERS_CLK_EN</name>
+              <description>Set this bit to enable clock of timers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI01_CLK_EN</name>
+              <description>Set this bit to enable clock of SPI0 and SPI1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_CLK_EN</name>
+              <description>Set this bit to enable clock of UART0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDG_CLK_EN</name>
+              <description>Set this bit to enable clock of WDG.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S0_CLK_EN</name>
+              <description>Set this bit to enable clock of I2S0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CLK_EN</name>
+              <description>Set this bit to enable clock of UART1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_CLK_EN</name>
+              <description>Set this bit to enable clock of SPI2.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT0_CLK_EN</name>
+              <description>Set this bit to enable clock of I2C EXT0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI0_CLK_EN</name>
+              <description>Set this bit to enable clock of UHCI0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_CLK_EN</name>
+              <description>Set this bit to enable clock of remote controller.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCNT_CLK_EN</name>
+              <description>Set this bit to enable clock of pulse count.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_CLK_EN</name>
+              <description>Set this bit to enable clock of LED PWM.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI1_CLK_EN</name>
+              <description>Set this bit to enable clock of UHCI1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_CLK_EN</name>
+              <description>Set this bit to enable clock of timer group0.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_CLK_EN</name>
+              <description>Set this bit to enable clock of eFuse.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP1_CLK_EN</name>
+              <description>Set this bit to enable clock of timer group1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_CLK_EN</name>
+              <description>Set this bit to enable clock of SPI3.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM0_CLK_EN</name>
+              <description>Set this bit to enable clock of PWM0.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT1_CLK_EN</name>
+              <description>Set this bit to enable clock of I2C EXT1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAN_CLK_EN</name>
+              <description>Set this bit to enable clock of CAN.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM1_CLK_EN</name>
+              <description>Set this bit to enable clock of PWM1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S1_CLK_EN</name>
+              <description>Set this bit to enable clock of I2S1.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_DMA_CLK_EN</name>
+              <description>Set this bit to enable clock of SPI2 DMA.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_CLK_EN</name>
+              <description>Set this bit to enable clock of USB.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_CLK_EN</name>
+              <description>Set this bit to enable clock of UART memory.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM2_CLK_EN</name>
+              <description>Set this bit to enable clock of PWM2.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM3_CLK_EN</name>
+              <description>Set this bit to enable clock of PWM3.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_DMA_CLK_EN</name>
+              <description>Set this bit to enable clock of SPI3 DMA.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_CLK_EN</name>
+              <description>Set this bit to enable clock of SAR ADC.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_CLK_EN</name>
+              <description>Set this bit to enable clock of system timer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_ARB_CLK_EN</name>
+              <description>Set this bit to enable clock of aribiter of ADC2.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI4_CLK_EN</name>
+              <description>Set this bit to enable clock of SPI4.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_CLK_EN1</name>
+          <description>System peripheral clock  (for hardware accelerators) enable register 1</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CRYPTO_AES_CLK_EN</name>
+              <description>Set this bit to enable clock of cryptography AES.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_SHA_CLK_EN</name>
+              <description>Set this bit to enable clock of cryptography SHA.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_RSA_CLK_EN</name>
+              <description>Set this bit to enable clock of cryptography RSA.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_DS_CLK_EN</name>
+              <description>Set this bit to enable clock of cryptography Digital Signature.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_HMAC_CLK_EN</name>
+              <description>Set this bit to enable clock of cryptography HMAC.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_DMA_CLK_EN</name>
+              <description>Set this bit to enable clock of cryptography DMA.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_RST_EN0</name>
+          <description>System peripheral (hardware accelerators) reset register 0</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMERS_RST</name>
+              <description>Set this bit to reset timers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI01_RST</name>
+              <description>Set this bit to reset SPI0 and SPI1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RST</name>
+              <description>Set this bit to reset UART0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDG_RST</name>
+              <description>Set this bit to reset WDG.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S0_RST</name>
+              <description>Set this bit to reset I2S0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_RST</name>
+              <description>Set this bit to reset UART1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_RST</name>
+              <description>Set this bit to reset SPI2.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT0_RST</name>
+              <description>Set this bit to reset I2C EXT0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI0_RST</name>
+              <description>Set this bit to reset UHCI0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_RST</name>
+              <description>Set this bit to reset remote controller.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCNT_RST</name>
+              <description>Set this bit to reset pulse count.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_RST</name>
+              <description>Set this bit to reset LED PWM.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI1_RST</name>
+              <description>Set this bit to reset UHCI1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_RST</name>
+              <description>Set this bit to reset timer group0.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_RST</name>
+              <description>Set this bit to reset eFuse.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP1_RST</name>
+              <description>Set this bit to reset timer group1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_RST</name>
+              <description>Set this bit to reset SPI3.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM0_RST</name>
+              <description>Set this bit to reset PWM0.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT1_RST</name>
+              <description>Set this bit to reset I2C EXT1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAN_RST</name>
+              <description>Set this bit to reset CAN.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM1_RST</name>
+              <description>Set this bit to reset PWM1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S1_RST</name>
+              <description>Set this bit to reset I2S1.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_DMA_RST</name>
+              <description>Set this bit to reset SPI2 DMA.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_RST</name>
+              <description>Set this bit to reset USB.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_RST</name>
+              <description>Set this bit to reset UART memory.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM2_RST</name>
+              <description>Set this bit to reset PWM2.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM3_RST</name>
+              <description>Set this bit to reset PWM3.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_DMA_RST</name>
+              <description>Set this bit to reset SPI3 DMA.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_RST</name>
+              <description>Set this bit to reset SAR ADC.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_RST</name>
+              <description>Set this bit to reset system timer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_ARB_RST</name>
+              <description>Set this bit to reset aribiter of ADC2.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI4_RST</name>
+              <description>Set this bit to reset SPI4.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_RST_EN1</name>
+          <description>System peripheral (hardware accelerators) reset register 1</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000007E</resetValue>
+          <fields>
+            <field>
+              <name>CRYPTO_AES_RST</name>
+              <description>Set this bit to reset cryptography AES.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_SHA_RST</name>
+              <description>Set this bit to reset cryptography SHA.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_RSA_RST</name>
+              <description>Set this bit to reset cryptography RSA.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_DS_RST</name>
+              <description>Set this bit to reset cryptography digital signature.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_HMAC_RST</name>
+              <description>Set this bit to reset cryptography HMAC.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_DMA_RST</name>
+              <description>Set this bit to reset cryptography DMA.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LPCK_DIV_INT</name>
+          <description>Low power clock divider integer register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>LPCK_DIV_NUM</name>
+              <description>This field is used to set the integer number of the divider value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_LPCK_DIV_FRAC</name>
+          <description>Divider fraction configuration register for low-power clock</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02000000</resetValue>
+          <fields>
+            <field>
+              <name>LPCLK_SEL_RTC_SLOW</name>
+              <description>Set this bit to select RTC slow clock as the low power clock.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_8M</name>
+              <description>Set this bit to select 8m clock as the low power clock.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL</name>
+              <description>Set this bit to select xtal clock as the low power clock.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL32K</name>
+              <description>Set this bit to select xtal32k clock as the low power clock.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_RTC_EN</name>
+              <description>Set this bit to enable the RTC low power clock.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0</name>
+          <description>CPU interrupt controlling register 0</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0</name>
+              <description>Set this bit to generate CPU interrupt 0. This bit needs to be reset by software in the ISR process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1</name>
+          <description>CPU interrupt controlling register 1</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1</name>
+              <description>Set this bit to generate CPU interrupt 1. This bit needs to be reset by software in the ISR process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2</name>
+          <description>CPU interrupt controlling register 2</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2</name>
+              <description>Set this bit to generate CPU interrupt 2. This bit needs to be reset by software in the ISR process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3</name>
+          <description>CPU interrupt controlling register 3</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3</name>
+              <description>Set this bit to generate CPU interrupt 3. This bit needs to be reset by software in the ISR process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_PD_CTRL</name>
+          <description>RSA memory remapping register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RSA_MEM_PD</name>
+              <description>Set this bit to power down RSA memory. This bit has the lowest priority. When Digital Signature occupies the RSA, this bit is invalid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PU</name>
+              <description>Set this bit to force power up RSA memory. This bit has the second highest priority.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PD</name>
+              <description>Set this bit to force power down RSA memory. This bit has the highest priority.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSTOEXTMEM_ENA</name>
+          <description>EDMA enable register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>BUSTOEXTMEM_ENA</name>
+              <description>Set this bit to enable bus to EDMA.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CONTROL</name>
+          <description>Cache control register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>PRO_ICACHE_CLK_ON</name>
+              <description>Set this bit to enable clock of i-cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DCACHE_CLK_ON</name>
+              <description>Set this bit to enable clock of d-cache.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_CACHE_RESET</name>
+              <description>Set this bit to reset cache.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL</name>
+          <description>External memory encrypt and decrypt controlling register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_SPI_MANUAL_ENCRYPT</name>
+              <description>Set this bit to enable Manual Encryption under SPI Boot mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_DB_ENCRYPT</name>
+              <description>Set this bit to enable Auto Encryption under Download Boot mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_G0CB_DECRYPT</name>
+              <description>Set this bit to enable Auto Decryption under Download Boot mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>Set this bit to enable Manual Encryption under Download Boot mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_FASTMEM_CONFIG</name>
+          <description>RTC fast memory configuration register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7FF00000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_MEM_CRC_START</name>
+              <description>Set this bit to start the CRC of RTC memory.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_ADDR</name>
+              <description>This field is used to set address of RTC memory for CRC.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_LEN</name>
+              <description>This field is used to set length of RTC memory for CRC based on start address.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_FINISH</name>
+              <description>This bit stores the status of RTC memory CRC. High level means finished while low level means not finished.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_FASTMEM_CRC</name>
+          <description>RTC fast memory CRC controlling register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_MEM_CRC_RES</name>
+              <description>This field stores the CRC result of RTC memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Redundant_ECO_Ctrl</name>
+          <description>Redundant ECO control register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDUNDANT_ECO_DRIVE</name>
+              <description>The redundant ECO drive bit to avoid optimization in circuits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDUNDANT_ECO_RESULT</name>
+              <description>The redundant ECO result bit to avoid optimization in circuits.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>Clock gate control register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clock of this module.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_CTRL_2</name>
+          <description>System SRAM configuration register 2</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_FORCE_PU</name>
+              <description>This field is used to power up internal SRAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSCLK_CONF</name>
+          <description>SoC clock configuration register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PRE_DIV_CNT</name>
+              <description>This field is used to set the count of prescaler of XTAL\_CLK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOC_CLK_SEL</name>
+              <description>This field is used to select SOC clock.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_XTAL_FREQ</name>
+              <description>This field is used to read XTAL frequency in MHz.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLK_DIV_EN</name>
+              <description>Not used, extends from ESP32.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01908020</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SYSTIMER</name>
+      <description>System Timer</description>
+      <groupName>SYSTIMER</groupName>
+      <baseAddress>0x3F423000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x54</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSTIMER_TARGET0</name>
+        <value>71</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET1</name>
+        <value>72</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET2</name>
+        <value>73</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF</name>
+          <description>Configure system timer clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_FO</name>
+              <description>System timer clock force enable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock enable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOAD</name>
+          <description>Load value to system timer</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_LOAD</name>
+              <description>Set this bit to 1, the value stored in SYSTIMER_TIMER_LOAD_HI and in
+SYSTIMER_TIMER_LOAD_LO will be loaded to system timer</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOAD_HI</name>
+          <description>High 32 bits to be loaded to system timer</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_LOAD_HI</name>
+              <description>The value to be loaded into system timer, high 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOAD_LO</name>
+          <description>Low 32 bits to be loaded to system timer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_LOAD_LO</name>
+              <description>The value to be loaded into system timer, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STEP</name>
+          <description>System timer accumulation step</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000450</resetValue>
+          <fields>
+            <field>
+              <name>TIMER_XTAL_STEP</name>
+              <description>Set system timer increment step when using XTAL_CLK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_PLL_STEP</name>
+              <description>Set system timer increment step when using PLL_CLK</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_HI</name>
+          <description>System timer target 0, high 32 bits</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_HI</name>
+              <description>System timer target 0, high 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_LO</name>
+          <description>System timer target 0, low 32 bits</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_LO</name>
+              <description>System timer target 0, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_HI</name>
+          <description>System timer target 1, high 32 bits</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_HI</name>
+              <description>System timer target 1, high 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_LO</name>
+          <description>System timer target 1, low 32 bits</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_LO</name>
+              <description>System timer target 1, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_HI</name>
+          <description>System timer target 2, high 32 bits</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_HI</name>
+              <description>System timer target 2, high 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_LO</name>
+          <description>System timer target 2, low 32 bits</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_LO</name>
+              <description>System timer target 2, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_CONF</name>
+          <description>Configure work mode for system timer target 0</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_PERIOD</name>
+              <description>Set alarm period for system timer target 0, only valid in periodic
+alarms mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_PERIOD_MODE</name>
+              <description>Set work mode for system timer target 0. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_WORK_EN</name>
+              <description>System timer target 0 work enable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_CONF</name>
+          <description>Configure work mode for system timer target 1</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_PERIOD</name>
+              <description>Set alarm period for system timer target 1, only valid in periodic
+alarms mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_PERIOD_MODE</name>
+              <description>Set work mode for system timer target 1. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_WORK_EN</name>
+              <description>System timer target 1 work enable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_CONF</name>
+          <description>Configure work mode for system timer target 2</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_PERIOD</name>
+              <description>Set alarm period for system timer target 2, only valid in periodic
+alarms mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_PERIOD_MODE</name>
+              <description>Set work mode for system timer target 2. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_WORK_EN</name>
+              <description>System timer target 2 work enable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_OP</name>
+          <description>Read out system timer value</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_VALID</name>
+              <description>Check if it is valid to read out timer value from registers. 0: Not
+ready to read timer value from registers; 1: Ready to read timer value from registers</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_UPDATE</name>
+              <description>Update system timer value to registers.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_HI</name>
+          <description>System timer value, high 32 bits</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE_HI</name>
+              <description>System timer value, high 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_LO</name>
+          <description>System timer value, low 32 bits</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE_LO</name>
+              <description>System timer value, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>System timer interrupt enable</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ENA</name>
+              <description>Interrupt enable bit of system timer target 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ENA</name>
+              <description>Interrupt enable bit of system timer target 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ENA</name>
+              <description>Interrupt enable bit of system timer target 2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>System timer interrupt raw</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT0_RAW</name>
+              <description>Interrupt raw bit of system timer target 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INT1_RAW</name>
+              <description>Interrupt raw bit of system timer target 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INT2_RAW</name>
+              <description>Interrupt raw bit of system timer target 2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>System timer interrupt clear</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_CLR</name>
+              <description>Interrupt clear bit of system timer target 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_CLR</name>
+              <description>Interrupt clear bit of system timer target 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_CLR</name>
+              <description>Interrupt clear bit of system timer target 2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01807160</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TIMG0</name>
+      <description>Timer Group</description>
+      <groupName>TIMG</groupName>
+      <baseAddress>0x3F41F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TG0_T0_LEVEL</name>
+        <value>15</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_T1_LEVEL</name>
+        <value>16</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_WDT_LEVEL</name>
+        <value>17</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_LACT_LEVEL</name>
+        <value>18</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_T0_EDGE</name>
+        <value>62</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_T1_EDGE</name>
+        <value>63</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_WDT_EDGE</name>
+        <value>64</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_LACT_EDGE</name>
+        <value>65</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sCONFIG</name>
+          <description>Timer %s configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002000</resetValue>
+          <fields>
+            <field>
+              <name>USE_XTAL</name>
+              <description>1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALARM_EN</name>
+              <description>When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEVEL_INT_EN</name>
+              <description>When set, an alarm will generate a level type interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EDGE_INT_EN</name>
+              <description>When set, an alarm will generate an edge type interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIVIDER</name>
+              <description>Timer %s clock (T%s_clk) prescaler value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTORELOAD</name>
+              <description>When set, timer %s auto-reload at alarm is enabled.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCREASE</name>
+              <description>When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>When set, the timer %s time-base counter is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sLO</name>
+          <description>Timer %s current value, low 32 bits</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LO</name>
+              <description>After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sHI</name>
+          <description>Timer %s current value, high 32 bits</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HI</name>
+              <description>After writing to TIMG_T%sUPDATE_REG, the high 32 bits of the time-base counter of timer %s can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sUPDATE</name>
+          <description>Write to copy current timer value to TIMG_T%sLO_REG or TIMGn_T%sHI_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UPDATE</name>
+              <description>After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sALARMLO</name>
+          <description>Timer %s alarm value, low 32 bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_LO</name>
+              <description>Timer %s alarm trigger time-base counter value, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sALARMHI</name>
+          <description>Timer %s alarm value, high bits</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_HI</name>
+              <description>
+Timer %s alarm trigger time-base counter value, high 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sLOADLO</name>
+          <description>Timer %s reload value, low 32 bits</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_LO</name>
+              <description>Low 32 bits of the value that a reload will load onto timer %s time-base counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sLOADHI</name>
+          <description>Timer %s reload value, high 32 bits</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_HI</name>
+              <description>High 32 bits of the value that a reload will load onto timer %s time-base counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sLOAD</name>
+          <description>Write to reload timer from TIMG_T%sLOADLO_REG or TIMG_T%sLOADHI_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD</name>
+              <description>Write any value to trigger a timer %s time-base counter reload.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>Watchdog timer configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0004C000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>WDT reset CPU enable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>When set, Flash boot protection is enabled.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>System reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>CPU reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_LEVEL_INT_EN</name>
+              <description>When set, a level type interrupt will occur at the timeout of a stage configured to generate an interrupt.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EDGE_INT_EN</name>
+              <description>When set, an edge type interrupt will occur at the timeout of a stage configured to generate an interrupt.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>Stage 3 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>Stage 2 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>Stage 1 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>Stage 0 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>When set, MWDT is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>Watchdog timer prescaler register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CLK_PRESCALE</name>
+              <description>MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>Watchdog timer stage 0 timeout value</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x018CBA80</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>Stage 0 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>Watchdog timer stage 1 timeout value</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>Stage 1 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>Watchdog timer stage 2 timeout value</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>Stage 2 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG5</name>
+          <description>Watchdog timer stage 3 timeout value</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>Stage 3 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>Write to feed the watchdog timer</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>Write any value to feed the MWDT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>Watchdog write protect register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>If the register contains a different value than its reset value, write protection is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG</name>
+          <description>RTC calibration configuration register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_START_CYCLING</name>
+              <description>When set, periodic calibration is enabled.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_CLK_SEL</name>
+              <description>Used to select the clock to be calibrated. 0: RTC_CLK. 1: RTC20M_D256_CLK. 2: XTAL32K_CLK.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_RDY</name>
+              <description>Set this bit to mark the completion of calibration.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_MAX</name>
+              <description>Calibration time, in cycles of the clock to be calibrated.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_START</name>
+              <description>Set this bit to starts calibration.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG1</name>
+          <description>RTC calibration configuration register 1</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_CALI_CYCLING_DATA_VLD</name>
+              <description>Periodic calibration valid signal.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_VALUE</name>
+              <description>Calibration value when cycles of clock to be calibrated reach TIMG_RTC_CALI_MAX, in unit of XTAL_CLK clock cycles.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTCONFIG</name>
+          <description>LACT configuration register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002300</resetValue>
+          <fields>
+            <field>
+              <name>LACT_USE_REFTICK</name>
+              <description>Reserved.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_RTC_ONLY</name>
+              <description>Reserved.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_CPST_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_LAC_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_ALARM_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_LEVEL_INT_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_EDGE_INT_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_DIVIDER</name>
+              <description>Reserved.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_AUTORELOAD</name>
+              <description>Reserved.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_INCREASE</name>
+              <description>Reserved.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTRTC</name>
+          <description>LACT RTC register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_RTC_STEP_LEN</name>
+              <description>Reserved.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTLO</name>
+          <description>LACT low register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_LO</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTHI</name>
+          <description>LACT high register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_HI</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTUPDATE</name>
+          <description>LACT update register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_UPDATE</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTALARMLO</name>
+          <description>LACT alarm low register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_ALARM_LO</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTALARMHI</name>
+          <description>LACT alarm high register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_ALARM_HI</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTLOADLO</name>
+          <description>LACT load low register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_LOAD_LO</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTLOADHI</name>
+          <description>Timer LACT load high register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_LOAD_HI</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LACTLOAD</name>
+          <description>Timer LACT load register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LACT_LOAD</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_TIMERS</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_T1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LACT_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_LACT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_TIMERS</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>T1_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_T1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LACT_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_LACT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_TIMERS</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>T1_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_T1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LACT_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_LACT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_TIMERS</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>T1_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_T1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LACT_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_LACT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG2</name>
+          <description>Timer group calibration register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFF98</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_TIMEOUT</name>
+              <description>RTC calibration timeout indicator</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_RST_CNT</name>
+              <description>Cycles that release calibration timeout reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_THRES</name>
+              <description>Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMERS_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01907261</resetValue>
+          <fields>
+            <field>
+              <name>TIMERS_DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGCLK</name>
+          <description>Timer group clock gate register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMG0">
+      <name>TIMG1</name>
+      <description>Timer Group</description>
+      <baseAddress>0x3F420000</baseAddress>
+      <interrupt>
+        <name>TG1_T0_LEVEL</name>
+        <value>19</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_T1_LEVEL</name>
+        <value>20</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_WDT_LEVEL</name>
+        <value>21</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_LACT_LEVEL</name>
+        <value>22</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_T0_EDGE</name>
+        <value>66</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_T1_EDGE</name>
+        <value>67</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_WDT_EDGE</name>
+        <value>68</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_LACT_EDGE</name>
+        <value>69</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TWAI</name>
+      <description>Two-Wire Automotive Interface</description>
+      <groupName>TWAI</groupName>
+      <baseAddress>0x3F42B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x6C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TWAI</name>
+        <value>47</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Mode Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RESET_MODE</name>
+              <description>This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LISTEN_ONLY_MODE</name>
+              <description>1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SELF_TEST_MODE</name>
+              <description>1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_MODE</name>
+              <description>This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>Command Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_REQ</name>
+              <description>Set the bit to 1 to allow the driving nodes start transmission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ABORT_TX</name>
+              <description>Set the bit to 1 to cancel a pending transmission request.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RELEASE_BUF</name>
+              <description>Set the bit to 1 to release the RX buffer.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CLR_OVERRUN</name>
+              <description>Set the bit to 1 to clear the data overrun status bit.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SELF_RX_REQ</name>
+              <description>Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_BUF_ST</name>
+              <description>1: The data in the RX buffer is not empty, with at least one received data packet.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN_ST</name>
+              <description>1: The RX FIFO is full and data overrun has occurred.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BUF_ST</name>
+              <description>1: The TX buffer is empty, the CPU may write a message into it.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_COMPLETE</name>
+              <description>1: The TWAI controller has successfully received a packet from the bus.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_ST</name>
+              <description>1: The TWAI Controller is receiving a message from the bus.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_ST</name>
+              <description>1: The TWAI Controller is transmitting a message to the bus.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_ST</name>
+              <description>1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_OFF_ST</name>
+              <description>1: In bus-off status, the TWAI Controller is no longer involved in bus activities.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MISS_ST</name>
+              <description>This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_INT_ST</name>
+              <description>Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_INT_ST</name>
+              <description>Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_WARN_INT_ST</name>
+              <description>Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN_INT_ST</name>
+              <description>Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ST</name>
+              <description>Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST_INT_ST</name>
+              <description>Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ST</name>
+              <description>Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt Enable Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_INT_ENA</name>
+              <description>Set this bit to 1 to enable receive interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_INT_ENA</name>
+              <description>Set this bit to 1 to enable transmit interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WARN_INT_ENA</name>
+              <description>Set this bit to 1 to enable error warning interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVERRUN_INT_ENA</name>
+              <description>Set this bit to 1 to enable data overrun interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ENA</name>
+              <description>Set this bit to 1 to enable error passive interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_LOST_INT_ENA</name>
+              <description>Set this bit to 1 to enable arbitration lost interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ENA</name>
+              <description>Set this bit to 1 to enable error interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_0</name>
+          <description>Bus Timing Register 0</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BAUD_PRESC</name>
+              <description>Baud Rate Prescaler, determines the frequency dividing ratio.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC_JUMP_WIDTH</name>
+              <description>Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_1</name>
+          <description>Bus Timing Register 1</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_SEG1</name>
+              <description>The width of PBS1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SEG2</name>
+              <description>The width of PBS2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SAMP</name>
+              <description>The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_LOST_CAP</name>
+          <description>Arbitration Lost Capture Register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ARB_LOST_CAP</name>
+              <description>This register contains information about the bit position of lost arbitration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_CODE_CAP</name>
+          <description>Error Code Capture Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ECC_SEGMENT</name>
+              <description>This register contains information about the location of errors, see Table 181 for details.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_DIRECTION</name>
+              <description>This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_TYPE</name>
+              <description>This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_WARNING_LIMIT</name>
+          <description>Error Warning Limit Register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000060</resetValue>
+          <fields>
+            <field>
+              <name>ERR_WARNING_LIMIT</name>
+              <description>Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_ERR_CNT</name>
+          <description>Receive Error Counter Register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CNT</name>
+              <description>The RX error counter register, reflects value changes under reception status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_ERR_CNT</name>
+          <description>Transmit Error Counter Register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_ERR_CNT</name>
+              <description>The TX error counter register, reflects value changes under transmission status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_0</name>
+          <description>Data register 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_0</name>
+              <description>In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_1</name>
+          <description>Data register 1</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_1</name>
+              <description>In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_2</name>
+          <description>Data register 2</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_2</name>
+              <description>In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_3</name>
+          <description>Data register 3</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_3</name>
+              <description>In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_4</name>
+          <description>Data register 4</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_4</name>
+              <description>In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_5</name>
+          <description>Data register 5</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_5</name>
+              <description>In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_6</name>
+          <description>Data register 6</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_6</name>
+              <description>In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_7</name>
+          <description>Data register 7</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_7</name>
+              <description>In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_8</name>
+          <description>Data register 8</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_8</name>
+              <description>Stored the 8th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_9</name>
+          <description>Data register 9</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_9</name>
+              <description>Stored the 9th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_10</name>
+          <description>Data register 10</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_10</name>
+              <description>Stored the 10th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_11</name>
+          <description>Data register 11</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_11</name>
+              <description>Stored the 11th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_12</name>
+          <description>Data register 12</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_12</name>
+              <description>Stored the 12th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_MESSAGE_CNT</name>
+          <description>Receive Message Counter Register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_MESSAGE_COUNTER</name>
+              <description>This register reflects the number of messages available within the RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_DIVIDER</name>
+          <description>Clock Divider register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CD</name>
+              <description>These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLOCK_OFF</name>
+              <description>This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>UART0</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x3F400000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x7C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART0</name>
+        <value>37</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>FIFO</name>
+          <description>FIFO data register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RD_BYTE</name>
+              <description>UART 0 accesses FIFO via this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver receives more data than what UART_RXFIFO_FULL_THRHD specifies.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the amount of data in TX FIFO is less than what UART_TXFIFO_EMPTY_THRHD specifies.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver detects a parity error in the data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver detects a data frame error.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver receives more data than the capacity of RX FIFO.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver detects the edge change of DSRn signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver detects the edge change of CTSn signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver detects a 0 after the stop bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver takes more time than UART_RX_TOUT_THRHD to receive a byte.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver receives an XON character and UART_SW_FLOW_CON_EN is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver receives an XOFF character and UART_SW_FLOW_CON_EN is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver detects a glitch in the middle of a start bit.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the transmitter completes  sending  NULL characters, after all data in TX FIFO are sent.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the transmitter has kept the shortest duration after sending the  last data.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the transmitter has sent out all data in FIFO.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver detects a parity error from the echo of the transmitter in RS485 mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver detects a data frame error from the echo of the transmitter in RS485 mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when a collision is detected between the transmitter and the receiver in RS485 mode.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the receiver detects the configured UART_AT_CMD CHAR.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when input RXD edge changes more times than what UART_ACTIVE_THRESHOLD specifies in Light-sleep mode.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ST</name>
+              <description>This is the status bit for UART_RXFIFO_FULL_INT when UART_RXFIFO_FULL_INT_ENA is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ST</name>
+              <description>This is the status bit for UART_TXFIFO_EMPTY_INT when UART_TXFIFO_EMPTY_INT_ENA is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for UART_PARITY_ERR_INT when UART_PARITY_ERR_INT_ENA is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ST</name>
+              <description>This is the status bit for UART_FRM_ERR_INT when UART_FRM_ERR_INT_ENA is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>This is the status bit for UART_RXFIFO_OVF_INT when UART_RXFIFO_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ST</name>
+              <description>This is the status bit for UART_DSR_CHG_INT when UART_DSR_CHG_INT_ENA is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ST</name>
+              <description>This is the status bit for UART_CTS_CHG_INT when UART_CTS_CHG_INT_ENA is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ST</name>
+              <description>This is the status bit for UART_BRK_DET_INT when UART_BRK_DET_INT_ENA is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ST</name>
+              <description>This is the status bit for UART_RXFIFO_TOUT_INT when UART_RXFIFO_TOUT_INT_ENA is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ST</name>
+              <description>This is the status bit for UART_SW_XON_INT when UART_SW_XON_INT_ENA is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ST</name>
+              <description>This is the status bit for UART_SW_XOFF_INT when UART_SW_XOFF_INT_ENA is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>This is the status bit for UART_GLITCH_DET_INT when UART_GLITCH_DET_INT_ENA is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ST</name>
+              <description>This is the status bit for UART_TX_BRK_DONE_INT when UART_TX_BRK_DONE_INT_ENA is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ST</name>
+              <description>This is the status bit for UART_TX_BRK_IDLE_DONE_INT when UART_TX_BRK_IDLE_DONE_INT_ENA is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>This is the status bit for UART_TX_DONE_INT when UART_TX_DONE_INT_ENA is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for UART_RS485_PARITY_ERR_INT when UART_RS485_PARITY_INT_ENA is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ST</name>
+              <description>This is the status bit for UART_RS485_FRM_ERR_INT when UART_RS485_FRM_ERR_INT_ENA is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ST</name>
+              <description>This is the status bit for UART_RS485_CLASH_INT when UART_RS485_CLASH_INT_ENA is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ST</name>
+              <description>This is the status bit for UART_AT_CMD_CHAR_DET_INT when UART_AT_CMD_CHAR_DET_INT_ENA is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ST</name>
+              <description>This is the status bit for UART_WAKEUP_INT when UART_WAKEUP_INT_ENA is set to 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ENA</name>
+              <description>This is the enable bit for UART_RXFIFO_FULL_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ENA</name>
+              <description>This is the enable bit for UART_TXFIFO_EMPTY_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for UART_PARITY_ERR_INT.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for UART_FRM_ERR_INT.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>This is the enable bit for UART_RXFIFO_OVF_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ENA</name>
+              <description>This is the enable bit for UART_DSR_CHG_INT.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ENA</name>
+              <description>This is the enable bit for UART_CTS_CHG_INT.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ENA</name>
+              <description>This is the enable bit for UART_BRK_DET_INT.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ENA</name>
+              <description>This is the enable bit for UART_RXFIFO_TOUT_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ENA</name>
+              <description>This is the enable bit for UART_SW_XON_INT.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ENA</name>
+              <description>This is the enable bit for UART_SW_XOFF_INT.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>This is the enable bit for UART_GLITCH_DET_INT.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ENA</name>
+              <description>This is the enable bit for UART_TX_BRK_DONE_INT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ENA</name>
+              <description>This is the enable bit for UART_TX_BRK_IDLE_DONE_INT.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>This is the enable bit for UART_TX_DONE_INT.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for UART_RS485_PARITY_ERR_INT.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for UART_RS485_PARITY_ERR_INT.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ENA</name>
+              <description>This is the enable bit for UART_RS485_CLASH_INT.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ENA</name>
+              <description>This is the enable bit for UART_AT_CMD_CHAR_DET_INT.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ENA</name>
+              <description>This is the enable bit for UART_WAKEUP_INT.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_CLR</name>
+              <description>Set this bit to clear UART_THE RXFIFO_FULL_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear UART_TXFIFO_EMPTY_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear UART_PARITY_ERR_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear UART_FRM_ERR_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear UART_UART_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_CLR</name>
+              <description>Set this bit to clear UART_DSR_CHG_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear UART_CTS_CHG_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_CLR</name>
+              <description>Set this bit to clear UART_BRK_DET_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_CLR</name>
+              <description>Set this bit to clear UART_RXFIFO_TOUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_CLR</name>
+              <description>Set this bit to clear UART_SW_XON_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_CLR</name>
+              <description>Set this bit to clear UART_SW_XOFF_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Set this bit to clear UART_GLITCH_DET_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_CLR</name>
+              <description>Set this bit to clear UART_TX_BRK_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_CLR</name>
+              <description>Set this bit to clear UART_TX_BRK_IDLE_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear UART_TX_DONE_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear UART_RS485_PARITY_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear UART_RS485_FRM_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_CLR</name>
+              <description>Set this bit to clear UART_RS485_CLASH_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_CLR</name>
+              <description>Set this bit to clear UART_AT_CMD_CHAR_DET_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_CLR</name>
+              <description>Set this bit to clear UART_WAKEUP_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV</name>
+          <description>Clock divider configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000002B6</resetValue>
+          <fields>
+            <field>
+              <name>CLKDIV</name>
+              <description>The integral part of the frequency divisor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRAG</name>
+              <description>The fractional part of the frequency divisor.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AUTOBAUD</name>
+          <description>Autobaud configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>This is the enable bit for baud rate detection.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_FILT</name>
+              <description>When input pulse width is lower than this value, the pulse is ignored.
+This register is used in autobaud detection.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>UART status register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>Stores the number of valid data bytes in RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSRN</name>
+              <description>This register represents the level of the internal UART DSR signal.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTSN</name>
+              <description>This register represents the level of the internal UART CTS signal.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXD</name>
+              <description>This register represents the level of the internal UART RXD signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>Stores the number of data bytes in TX FIFO.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTRN</name>
+              <description>This bit represents the level of the internal UART DTR signal.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTSN</name>
+              <description>This bit represents the level of the internal UART RTS signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXD</name>
+              <description>This bit represents the level of the internal UART TXD signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0</name>
+          <description>Configuration register 0</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1800001C</resetValue>
+          <fields>
+            <field>
+              <name>PARITY</name>
+              <description>This register is used to configure the parity check mode.
+0: even. 1: odd.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_EN</name>
+              <description>Set this bit to enable UART parity check.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIT_NUM</name>
+              <description>This register is used to set the length of data.
+0: 5 bits. 1: 6 bits. 2: 7 bits. 3: 8 bits.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOP_BIT_NUM</name>
+              <description>This register is used to set the length of  stop bit.
+1: 1 bit. 2: 1.5 bits. 3: 2 bits.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_RTS</name>
+              <description>This register is used to configure the software RTS signal which is used in software flow control.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_DTR</name>
+              <description>This register is used to configure the software DTR signal which is used in software flow control.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_BRK</name>
+              <description>Set this bit to enable the transmitter to send NULL characters when the process of sending data is done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_DPLX</name>
+              <description>Set this bit to enable IrDA loopback mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_EN</name>
+              <description>This is the start enable bit for IrDA transmitter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_WCTL</name>
+              <description>1: The IrDA transmitter's 11th bit is the same as 10th bit. 0: Set IrDA transmitter's 11th bit to 0.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_INV</name>
+              <description>Set this bit to invert the level of IrDA transmitter.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_RX_INV</name>
+              <description>Set this bit to invert the level of IrDA receiver.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOPBACK</name>
+              <description>Set this bit to enable UART loopback test mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FLOW_EN</name>
+              <description>Set this bit to enable flow control function for the transmitter.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_EN</name>
+              <description>Set this bit to enable IrDA protocol.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>Set this bit to reset the UART RX FIFO.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_RST</name>
+              <description>Set this bit to reset the UART TX FIFO.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXD_INV</name>
+              <description>Set this bit to invert the level of UART RXD signal.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_INV</name>
+              <description>Set this bit to invert the level of UART CTS signal.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_INV</name>
+              <description>Set this bit to invert the level of UART DSR signal.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_INV</name>
+              <description>Set this bit to invert the level of UART TXD signal.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTS_INV</name>
+              <description>Set this bit to invert the level of UART RTS signal.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTR_INV</name>
+              <description>Set this bit to invert the level of UART DTR signal.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1: Force clock on for registers. 0: Support clock only when application writes registers.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WR_MASK</name>
+              <description>1: The receiver stops storing data into FIFO when data is wrong. 0: The receiver stores the data even if the  received data is wrong.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_REF_ALWAYS_ON</name>
+              <description>This register is used to select the clock.
+1: APB_CLK.
+0: REF_TICK.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_EN</name>
+              <description>The signal to enable UART RAM clock gating.
+1: UART RAM powers on, the data of which can be read and written.
+0: UART RAM powers down.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>Configuration register 1</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C060</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_THRHD</name>
+              <description>An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_THRHD</name>
+              <description>An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register's value.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_FLOW_DIS</name>
+              <description>Set this bit to stop accumulating idle_cnt when hardware flow control works.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_EN</name>
+              <description>This is the flow enable bit for UART receiver.
+1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_EN</name>
+              <description>This is the enable bit for UART receiver's timeout function.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOWPULSE</name>
+          <description>Autobaud minimum low pulse duration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate detection.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HIGHPULSE</name>
+          <description>Autobaud minimum high pulse duration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores  the value of the maximum duration time for the high level pulse. It is used in baud rate detection.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXD_CNT</name>
+          <description>Autobaud edge change count register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXD_EDGE_CNT</name>
+              <description>This register stores the count of RXD edge change.  It is used in baud rate detection. As baud rate registers UART_REG_LOWPULSE_MIN_CNT, UART_REG_HIGHPULSE_MIN_CNT, UART_REG_POSEDGE_MIN_CNT, and UART_REG_NEGEDGE_MIN_CNT always record the minimal value, UART_REG_RXD_EDGE_CNT indicates the statistic number of RXD edge to find out the minimal value for these baud rate registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW_CONF</name>
+          <description>Software flow control configuration</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_FLOW_CON_EN</name>
+              <description>Set this bit to enable software flow control. When UART receives flow control characters XON or XOFF, which can be configured by UART_XON_CHAR or UART_XOFF_CHAR respectively, UART_SW_XON_INT or UART_SW_XOFF_INT interrupts can be triggered if enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XONOFF_DEL</name>
+              <description>Set this bit to remove flow control characters from the received data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XON</name>
+              <description>Set this bit to force the transmitter to send data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XOFF</name>
+              <description>Set this bit to stop the transmitter from sending data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XON</name>
+              <description>Set this bit to send an XON character. This bit is cleared by hardware automatically.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XOFF</name>
+              <description>Set this bit to send an XOFF character. This bit is cleared by hardware automatically.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF</name>
+          <description>Sleep mode configuration</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000F0</resetValue>
+          <fields>
+            <field>
+              <name>ACTIVE_THRESHOLD</name>
+              <description>The UART is activated from Light-sleep mode when the input RXD edge changes more times than this register's value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF0</name>
+          <description>Software flow control character configuration</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000026E0</resetValue>
+          <fields>
+            <field>
+              <name>XOFF_THRESHOLD</name>
+              <description>When the number of data bytes in RX FIFO is more than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XOFF character.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_CHAR</name>
+              <description>This register stores the XOFF flow control character.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF1</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002200</resetValue>
+          <fields>
+            <field>
+              <name>XON_THRESHOLD</name>
+              <description>When the number of data bytes in RX FIFO is less than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XON character.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XON_CHAR</name>
+              <description>This register stores the XON flow control character.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_CONF</name>
+          <description>Frame end idle time configuration</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00A40100</resetValue>
+          <fields>
+            <field>
+              <name>RX_IDLE_THRHD</name>
+              <description>A frame end signal is generated when the receiver takes more time to receive one byte data than this register's value, in the unit of bit time (the time it takes to transfer one bit).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between transfers, in the unit of bit time (the time it takes to transfer one bit).</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_NUM</name>
+              <description>This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when UART_TXD_BRK is set to 1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RS485_CONF</name>
+          <description>RS485 mode configuration</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RS485_EN</name>
+              <description>Set this bit to choose RS485 mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL0_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL1_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485TX_RX_EN</name>
+              <description>Set this bit to enable the receiver could receive data when the transmitter is transmitting data in RS485 mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485RXBY_TX_EN</name>
+              <description>1: enable RS485 transmitter to send data when RS485 receiver line is busy.
+0: RS485 transmitter should not send data when its receiver is busy.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_RX_DLY_NUM</name>
+              <description>This register is used to delay the receiver's internal data signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_TX_DLY_NUM</name>
+              <description>This register is used to delay the transmitter's internal data signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_PRECNT</name>
+          <description>Pre-sequence timing configuration</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>PRE_IDLE_NUM</name>
+              <description>This register is used to configure the idle duration time before the first AT_CMD is received by the receiver.
+It will not take the next data received as AT_CMD character when the duration is less than this register's value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_POSTCNT</name>
+          <description>Post-sequence timing configuration</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>POST_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between the last AT_CMD and the next data.
+It will not take the previous data as AT_CMD character when the duration is less than this register's value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_GAPTOUT</name>
+          <description>Timeout configuration</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>RX_GAP_TOUT</name>
+              <description>This register is used to configure the duration time between the AT_CMD characters.
+It will not take the data as continuous AT_CMD characters when the duration time is less than this register's value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_CHAR</name>
+          <description>AT escape sequence selection configuration</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000032B</resetValue>
+          <fields>
+            <field>
+              <name>AT_CMD_CHAR</name>
+              <description>This register is used to configure the content of AT_CMD character.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAR_NUM</name>
+              <description>This register is used to configure the number of continuous AT_CMD characters received by the receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>UART threshold and allocation configuration</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A0012</resetValue>
+          <fields>
+            <field>
+              <name>RX_SIZE</name>
+              <description>This register is used to configure the amount of RAM allocated for RX FIFO. The default number is 128 bytes.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SIZE</name>
+              <description>This register is used to configure the amount of RAM allocated for TX FIFO. The default number is 128 bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_THRHD</name>
+              <description>This register is used to configure the maximum amount of data bytes that can be received  when hardware flow control works.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_THRHD</name>
+              <description>This register is used to configure the threshold time that the receiver takes to receive one byte, in the unit of bit time (the time it takes to transfer one bit).
+The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes more time to receive one byte with UART RX_TOUT_EN set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to force power down UART RAM.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>Set this bit to force power up UART RAM.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_TX_STATUS</name>
+          <description>TX FIFO write and read offset address</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_TX_WADDR</name>
+              <description>This register stores the offset address in TX FIFO when software writes TX FIFO via APB.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_RADDR</name>
+              <description>This register stores the offset address in TX FIFO when TX FSM reads data via Tx_FIFO_Ctrl.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_RX_STATUS</name>
+          <description>RX FIFO write and read offset address</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_RX_RADDR</name>
+              <description>This register stores the offset address in RX_FIFO when software reads data from RX FIFO via APB.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_WADDR</name>
+              <description>This register stores the offset address in RX FIFO when Rx_FIFO_Ctrl writes RX FIFO.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_STATUS</name>
+          <description>UART transmitter and receiver status</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST_URX_OUT</name>
+              <description>This is the status register of the receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ST_UTX_OUT</name>
+              <description>This is the status register of the transmitter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POSPULSE</name>
+          <description>Autobaud high pulse register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>POSEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two positive edges. It is used in baud rate detection.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NEGPULSE</name>
+          <description>Autobaud low pulse register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>NEGEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two negative edges. It is used in baud rate detection.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UART version control register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x18082800</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ID</name>
+          <description>UART ID register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000500</resetValue>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>This register is used to configure the UART_ID.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <name>UART1</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <baseAddress>0x3F410000</baseAddress>
+      <interrupt>
+        <name>UART1</name>
+        <value>38</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>UHCI0</name>
+      <description>Universal Host Controller Interface</description>
+      <groupName>UHCI</groupName>
+      <baseAddress>0x3F414000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xBC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UHCI0</name>
+        <value>13</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF0</name>
+          <description>UHCI configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00370100</resetValue>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>Set this bit to reset in DMA FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_RST</name>
+              <description>Set this bit to reset out DMA FSM.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_FIFO_RST</name>
+              <description>Set this bit to reset AHB interface cmdFIFO of DMA.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_RST</name>
+              <description>Set this bit to reset AHB interface of DMA.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>Reserved.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>Reserved.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>Set this bit to enable automatic outlink writeback when all the data in TX FIFO has been transmitted.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_NO_RESTART_CLR</name>
+              <description>Reserved.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>This register is used to specify the generation mode of UHCI_OUT_EOF_INT interrupt.
+1: When DMA has popped all data from FIFO.
+0: When AHB has pushed all data to FIFO.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_CE</name>
+              <description>Set this bit to link up UHCI and UART0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CE</name>
+              <description>Set this bit to link up UHCI and UART1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>This register is used to specify DMA transmit descriptor transfer mode.
+1: burst mode.
+0: byte mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>This register is used to specify DMA receive descriptor transfer mode.
+1: burst mode.
+0: byte mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <description>1: UHCI transmitted data would be write back into DMA INFIFO.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_EN</name>
+              <description>Set this bit to separate the data frame using a special character.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HEAD_EN</name>
+              <description>Set this bit to encode the data packet with a formatting header.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_REC_EN</name>
+              <description>Set this bit to enable UHCI to receive the 16 bit CRC.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_IDLE_EOF_EN</name>
+              <description>If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEN_EOF_EN</name>
+              <description>If this bit is set to 1, UHCI decoder stops receiving payload data when the number of received data bytes has reached the specified value.
+The value is payload length indicated by UCHI packet header when UHCI_HEAD_EN is 1 or the value is a configuration value when UHCI_HEAD_EN is 0.
+If this bit is set to 0, UHCI decoder stops receiving payload data  upon receiving 0xC0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCODE_CRC_EN</name>
+              <description>Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to the end of the payload.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1: Force clock on for registers. 0: Support clock only when application writes registers.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RX_BRK_EOF_EN</name>
+              <description>If this bit is set to 1, UHCI stops receiving payload data when a NULL frame is received by UART.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_RX_START_INT interrupt. The interrupt is triggered when a separator has been sent.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_TX_START_INT  interrupt. The interrupt is triggered when DMA detects a separator.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_RX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to receive data than the configure value.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_TX_HUNG_INT  interrupt. The interrupt is triggered when DMA takes more time to read data from RAM than the configured value.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_IN_DONE_INT  interrupt. The interrupt is triggered when an receive descriptor is completed.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_IN_SUC_EOF_INT interrupt. The interrupt is triggered when a data packet has been received successfully.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_IN_ERR_EOF_INT interrupt. The interrupt is triggered when there are some errors in EOF in the receive descriptor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_OUT_DONE_INT interrupt. The interrupt is triggered when an transmit descriptor is completed.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_OUT_EOF_INT interrupt. The interrupt is triggered when the current descriptor's EOF bit is 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_IN_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the receive descriptor.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_OUT_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the transmit descriptor.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_IN_DSCR_EMPTY_INT interrupt. The interrupt is triggered when there are not enough inlinks for DMA.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. The interrupt is triggered when there are some errors in EOF in the transmit descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_OUT_TOTAL_EOF_INT interrupt. The interrupt is triggered when all data in the last buffer address has been sent out.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_SEND_S_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using single_send mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_SEND_A_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using always_send mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_WM_INT_RAW</name>
+              <description>This is the interrupt raw bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. The interrupt is triggered when the number of data bytes in DMA RX FIFO has reached the configured threshold value.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_IN_DONE_INT interrupt when UHCI_IN_DONE_INT_ENA is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_IN_SUC_EOF_INT interrupt when UHCI_IN_SUC_EOF_INT_ENA is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_IN_ERR_EOF_INT interrupt when UHCI_IN_ERR_EOF_INT_ENA is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_OUT_DONE_INT interrupt when UHCI_OUT_DONE_INT_ENA is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_OUT_EOF_INT interrupt when UHCI_OUT_EOF_INT_ENA is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_IN_DSCR_ERR_INT interrupt when UHCI_IN_DSCR_ERR_INT is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_OUT_DSCR_ERR_INT interrupt when UHCI_OUT_DSCR_ERR_INT_ENA is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_IN_DSCR_EMPTY_INT interrupt when UHCI_IN_DSCR_EMPTY_INT_ENA is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ST</name>
+              <description>This is the masked interrupt bit for  UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ST</name>
+              <description>This is the masked interrupt bit for  UHCI_OUT_TOTAL_EOF_INT interrupt when UHCI_OUT_TOTAL_EOF_INT_ENA is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ST</name>
+              <description>This is the masked interrupt bit for  UHCI_SEND_S_REG_Q_INT interrupt when UHCI_SEND_S_REG_Q_INT_ENA is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_SEND_A_REG_Q_INT interrupt when UHCI_SEND_A_REG_Q_INT_ENA is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_WM_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_DMA_INFIFO_FULL_WM_INT INTERRUPT when UHCI_DMA_INFIFO_FULL_WM_INT_ENA is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_RX_START_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_TX_START_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_IN_DONE_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_IN_SUC_EOF_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_IN_ERR_EOF_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_OUT_DONE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_OUT_EOF_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_IN_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_OUT_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_IN_DSCR_EMPTY_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_OUT_TOTAL_EOF_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_SEND_S_REG_Q_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_SEND_A_REG_Q_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_WM_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_CLR</name>
+              <description>Set this bit to clear UHCI_RX_START_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_CLR</name>
+              <description>Set this bit to clear UHCI_TX_START_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear UHCI_RX_HUNG_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear UHCI_TX_HUNG_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DONE_INT_CLR</name>
+              <description>Set this bit to clear UHCI_IN_DONE_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF_INT_CLR</name>
+              <description>Set this bit to clear UHCI_IN_SUC_EOF_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF_INT_CLR</name>
+              <description>Set this bit to clear UHCI_IN_ERR_EOF_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DONE_INT_CLR</name>
+              <description>Set this bit to clear UHCI_OUT_DONE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_CLR</name>
+              <description>Set this bit to clear UHCI_OUT_EOF_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR_INT_CLR</name>
+              <description>Set this bit to clear UHCI_IN_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR_INT_CLR</name>
+              <description>Set this bit to clear UHCI_OUT_DSCR_ERR_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear UHCI_IN_DSCR_EMPTY_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_CLR</name>
+              <description>Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF_INT_CLR</name>
+              <description>Set this bit to clear UHCI_OUT_TOTAL_EOF_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_CLR</name>
+              <description>Set this bit to clear UHCI_SEND_S_REG_Q_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_CLR</name>
+              <description>Set this bit to clear UHCI_SEND_A_REG_Q_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_WM_INT_CLR</name>
+              <description>Set this bit to clear UHCI_DMA_INFIFO_FULL_WM_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_STATUS</name>
+          <description>DMA data-output status register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>OUT_FULL</name>
+              <description>1: DMA TX FIFO is full.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EMPTY</name>
+              <description>1: DMA TX FIFO is empty.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_PUSH</name>
+          <description>Push control register of TX FIFO</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA</name>
+              <description>This is the data that need to be pushed into TX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH</name>
+              <description>Set this bit to push data into TX FIFO.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_STATUS</name>
+          <description>UHCI data-input status register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>IN_FULL</name>
+              <description>Data-input FIFO full signal.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EMPTY</name>
+              <description>Data-input FIFO empty signal.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_ERR_CAUSE</name>
+              <description>This register indicates the error type when DMA has received a packet with error.
+3'b001: Checksum error in the HCI packet;
+3'b010: Sequence number error in the HCI packet;
+3'b011: CRC bit error in the HCI packet;
+3'b100: 0xC0 is found but the received HCI packet is not end;
+3'b101: 0xC0 is not found when the HCI packet has been received;
+3'b110: CRC check error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_POP</name>
+          <description>Pop control register of RX FIFO</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA</name>
+              <description>This register stores the data popping from RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP</name>
+              <description>Set this bit to pop data from  RX FIFO.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_LINK</name>
+          <description>Link descriptor address and control</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>This register is used to specify the least significant 20 bits of the first transmit descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set this bit to stop dealing with the transmit descriptor.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set this bit to start a new transmit descriptor.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set this bit to restart the transmit descriptor from the last address.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK</name>
+              <description>1: the transmit descriptor's FSM is in idle state.
+0: the transmit descriptor's FSM is working.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_LINK</name>
+          <description>Link descriptor address and control</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00100000</resetValue>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>This register is used to specify the least significant 20 bits of the first receive descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET</name>
+              <description>This is the enable bit to return to current receive descriptor's address, when there are some errors in current packet.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set this bit to stop dealing with the receive descriptors.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set this bit to start dealing with the receive descriptors.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set this bit to restart new receive descriptors.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_PARK</name>
+              <description>1: the receive descriptor's FSM is in idle state.
+0: the receive descriptor's FSM is working.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>UHCI configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>CHECK_SUM_EN</name>
+              <description>This is the enable bit to check header checksum when UHCI receives a data packet.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_SEQ_EN</name>
+              <description>This is the enable bit to check sequence number when UHCI receives a data packet.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_DISABLE</name>
+              <description>Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAVE_HEAD</name>
+              <description>Set this bit to save the packet header when UHCI receives a data packet.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHECK_SUM_RE</name>
+              <description>Set this bit to encode the data packet with a checksum.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_ACK_NUM_RE</name>
+              <description>Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_OWNER</name>
+              <description>1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_SW_START</name>
+              <description>The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_START</name>
+              <description>If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_THRS</name>
+              <description>This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <description>UHCI decoder status register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_ADDR</name>
+              <description>This register stores the current receive descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_STATE</name>
+              <description>Reserved.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_STATE</name>
+              <description>Reserved.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT_DEBUG</name>
+              <description>This register stores the number of data bytes in RX FIFO.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DECODE_STATE</name>
+              <description>UHCI decoder status.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE1</name>
+          <description>UHCI encoder status register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_ADDR</name>
+              <description>This register stores the current transmit descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_STATE</name>
+              <description>Reserved.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_STATE</name>
+              <description>Reserved.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT</name>
+              <description>This register stores the number of data bytes in TX FIFO.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENCODE_STATE</name>
+              <description>UHCI encoder status.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_EOF_DES_ADDR</name>
+          <description>Outlink descriptor address when EOF occurs</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR</name>
+              <description>This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_SUC_EOF_DES_ADDR</name>
+          <description>Inlink descriptor address when EOF occurs</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR</name>
+              <description>This register stores the address of the receive descriptor when received successful EOF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_ERR_EOF_DES_ADDR</name>
+          <description>Inlink descriptor address when errors occur</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_ERR_EOF_DES_ADDR</name>
+              <description>This register stores the address of the receive descriptor when there are some errors in this descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_EOF_BFR_DES_ADDR</name>
+          <description>Outlink descriptor address before the last transmit descriptor</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR</name>
+              <description>This register stores the address of the transmit descriptor before the last transmit descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_TEST</name>
+          <description>AHB test register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHB_TESTMODE</name>
+              <description>Reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_TESTADDR</name>
+              <description>Reserved.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_DSCR</name>
+          <description>The third word of the next receive descriptor</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR</name>
+              <description>This register stores the third word of the next receive descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_DSCR_BF0</name>
+          <description>The third word of current receive descriptor</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0</name>
+              <description>This register stores the third word of the current receive descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_DSCR</name>
+          <description>The third word of the next transmit descriptor</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR</name>
+              <description>This register stores the third word of the next transmit descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_DSCR_BF0</name>
+          <description>The third word of current transmit descriptor</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0</name>
+              <description>This register stores the third word of the current transmit descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESCAPE_CONF</name>
+          <description>Escape character configuration</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>TX_C0_ESC_EN</name>
+              <description>Set this bit to decode character 0xC0 when DMA receives data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DB_ESC_EN</name>
+              <description>Set this bit to decode character 0xDB when DMA receives data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_11_ESC_EN</name>
+              <description>Set this bit to decode flow control character 0x11 when DMA receives data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_13_ESC_EN</name>
+              <description>Set this bit to decode flow control character 0x13 when DMA receives data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_C0_ESC_EN</name>
+              <description>Set this bit to replace 0xC0 by special characters when DMA sends data.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DB_ESC_EN</name>
+              <description>Set this bit to replace 0xDB by special characters when DMA sends data.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_11_ESC_EN</name>
+              <description>Set this bit to replace flow control character 0x11 by special characters when DMA sends data.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_13_ESC_EN</name>
+              <description>Set this bit to replace flow control character 0x13 by special characters when DMA sends data.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HUNG_CONF</name>
+          <description>Timeout configuration</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00810810</resetValue>
+          <fields>
+            <field>
+              <name>TXFIFO_TIMEOUT</name>
+              <description>This register stores the timeout value. UHCI produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_SHIFT</name>
+              <description>This register is used to configure the maximum tick count.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_ENA</name>
+              <description>This is the enable bit for TX FIFO receive timeout.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT</name>
+              <description>This register stores the timeout value. UHCI produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_SHIFT</name>
+              <description>This register is used to configure the maximum tick count.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_ENA</name>
+              <description>This is the enable bit for DMA send timeout.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_HEAD</name>
+          <description>UHCI packet header register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_HEAD</name>
+              <description>This register stores the header of the current received packet.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUICK_SENT</name>
+          <description>UHCI quick_sent configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_SEND_NUM</name>
+              <description>This register is used to specify the single_send mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SINGLE_SEND_EN</name>
+              <description>Set this bit to enable single_send mode to send short packets.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_NUM</name>
+              <description>This register is used to specify the always_send mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_EN</name>
+              <description>Set this bit to enable always_send mode to send short packets.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q0_WORD0</name>
+          <description>Q0_WORD0 quick_sent register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD0</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q0_WORD1</name>
+          <description>Q0_WORD1 quick_sent register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD1</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q1_WORD0</name>
+          <description>Q1_WORD0 quick_sent register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD0</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q1_WORD1</name>
+          <description>Q1_WORD1 quick_sent register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD1</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q2_WORD0</name>
+          <description>Q2_WORD0 quick_sent register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD0</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q2_WORD1</name>
+          <description>Q2_WORD1 quick_sent register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD1</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q3_WORD0</name>
+          <description>Q3_WORD0 quick_sent register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD0</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q3_WORD1</name>
+          <description>Q3_WORD1 quick_sent register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD1</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q4_WORD0</name>
+          <description>Q4_WORD0 quick_sent register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD0</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q4_WORD1</name>
+          <description>Q4_WORD1 quick_sent register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD1</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q5_WORD0</name>
+          <description>Q5_WORD0 quick_sent register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD0</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q5_WORD1</name>
+          <description>Q5_WORD1 quick_sent register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD1</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q6_WORD0</name>
+          <description>Q6_WORD0 quick_sent register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD0</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Q6_WORD1</name>
+          <description>Q6_WORD1 quick_sent register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD1</name>
+              <description>This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF0</name>
+          <description>Escape sequence configuration register 0</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DCDBC0</resetValue>
+          <fields>
+            <field>
+              <name>SEPER_CHAR</name>
+              <description>This register is used to define separators to encode data packets. The default value is 0xC0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR0</name>
+              <description>This register is used to define the first character of SLIP escape sequence. The default value is 0xDB.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR1</name>
+              <description>This register is used to define the second character of SLIP escape sequence. The default value is 0xDC.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF1</name>
+          <description>Escape sequence configuration register 1</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DDDBDB</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ0</name>
+              <description>This register is used to define a character that need to be encoded. The default value is 0xDB that used as the first character of SLIP escape sequence.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR0</name>
+              <description>This register is used to define the first character of SLIP escape sequence. The default value is 0xDB.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR1</name>
+              <description>This register is used to define the second character of SLIP escape sequence. The default value is 0xDD.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF2</name>
+          <description>Escape sequence configuration register 2</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DEDB11</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ1</name>
+              <description>This register is used to define a character that need to be encoded. The default value is 0x11 that used as a flow control character.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR0</name>
+              <description>This register is used to define the first character of SLIP escape sequence. The default value is 0xDB.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR1</name>
+              <description>This register is used to define the second character of SLIP escape sequence. The default value is 0xDE.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF3</name>
+          <description>Escape sequence configuration register 3</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DFDB13</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ2</name>
+              <description>This register is used to define a character that need to be decoded. The default value is 0x13 that used as a flow control character.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR0</name>
+              <description>This register is used to define the first character of SLIP escape sequence. The default value is 0xDB.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR1</name>
+              <description>This register is used to define the second character of SLIP escape sequence. The default value is 0xDF.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_THRES</name>
+          <description>Configure register for packet length</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>PKT_THRS</name>
+              <description>This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UHCI version  control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x18073001</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>USB0</name>
+      <description>USB OTG (On-The-Go)</description>
+      <groupName>USB</groupName>
+      <baseAddress>0x60080000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x2A0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>GOTGCTL</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SESREQSCS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SESREQ</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VBVALIDOVEN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VBVALIDOVVAL</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AVALIDOVEN</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AVALIDOVVAL</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BVALIDOVEN</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BVALIDOVVAL</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTNEGSCS</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HNPREQ</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTSETHNPEN</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEVHNPEN</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EHEN</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBNCEFLTRBYPASS</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONIDSTS</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBNCTIME</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ASESVLD</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BSESVLD</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTGVER</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CURMOD</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GOTGINT</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SESENDDET</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SESREQSUCSTSCHNG</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTNEGSUCSTSCHNG</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTNEGDET</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADEVTOUTCHG</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBNCEDONE</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAHBCFG</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GLBLLNTRMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HBSTLEN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMAEN</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NPTXFEMPLVL</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PTXFEMPLVL</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REMMEMSUPP</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NOTIALLDMAWRIT</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBSINGLE</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INVDESCENDIANESS</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GUSBCFG</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001440</resetValue>
+          <fields>
+            <field>
+              <name>TOUTCAL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHYIF</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULPI_UTMI_SEL</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FSINTF</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHYSEL</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SRPCAP</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HNPCAP</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBTRDTIM</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TERMSELDLPULSE</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXENDDELAY</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCEHSTMODE</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCEDEVMODE</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORRUPTTXPKT</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GRSTCTL</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CSFTRST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PIUFSSFTRST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRMCNTRRST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFFLSH</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFFLSH</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFNUM</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMAREQ</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AHBIDLE</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GINTSTS</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CURMOD_INT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEMIS</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OTGINT</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOF</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFLVI</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NPTXFEMP</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GINNAKEFF</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GOUTNAKEFF</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERLYSUSP</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBSUSP</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBRST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENUMDONE</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ISOOUTDROP</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EOPF</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPMIS</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IEPINT</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OEPINT</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INCOMPISOIN</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCOMPIP</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FETSUSP</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESETDET</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTLNT</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HCHLNT</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PTXFEMP</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CONIDSTSCHNG</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISCONNINT</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SESSREQINT</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WKUPINT</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GINTMSK</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEMISMSK</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OTGINTMSK</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOFMSK</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFLVIMSK</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NPTXFEMPMSK</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GINNAKEFFMSK</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GOUTNACKEFFMSK</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERLYSUSPMSK</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBSUSPMSK</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBRSTMSK</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENUMDONEMSK</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ISOOUTDROPMSK</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EOPFMSK</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPMISMSK</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IEPINTMSK</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEPINTMSK</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCOMPISOINMSK</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCOMPIPMSK</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FETSUSPMSK</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESETDETMSK</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTLNTMSK</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HCHINTMSK</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PTXFEMPMSK</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONIDSTSCHNGMSK</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISCONNINTMSK</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SESSREQINTMSK</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WKUPINTMSK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GRXSTSR</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>G_CHNUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_BCNT</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_DPID</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_PKTSTS</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_FN</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GRXSTSP</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHNUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BCNT</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPID</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PKTSTS</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FN</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GRXFSIZ</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>RXFDEP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GNPTXFSIZ</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000100</resetValue>
+          <fields>
+            <field>
+              <name>NPTXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NPTXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GNPTXSTS</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040100</resetValue>
+          <fields>
+            <field>
+              <name>NPTXFSPCAVAIL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NPTXQSPCAVAIL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NPTXQTOP</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GSNPSID</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x4F54400A</resetValue>
+          <fields>
+            <field>
+              <name>SYNOPSYSID</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GHWCFG1</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EPDIR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GHWCFG2</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x224DD930</resetValue>
+          <fields>
+            <field>
+              <name>OTGMODE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTGARCH</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SINGPNT</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSPHYTYPE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FSPHYTYPE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NUMDEVEPS</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NUMHSTCHNL</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERIOSUPPORT</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DYNFIFOSIZING</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MULTIPROCINTRPT</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NPTXQDEPTH</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PTXQDEPTH</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TKNQDEPTH</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTG_ENABLE_IC_USB</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GHWCFG3</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x010004B5</resetValue>
+          <fields>
+            <field>
+              <name>XFERSIZEWIDTH</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PKTSIZEWIDTH</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTGEN</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2CINTSEL</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VNDCTLSUPT</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OPTFEATURE</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RSTTYPE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADPSUPPORT</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSICMODE</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BCSUPPORT</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LPMMODE</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFIFODEPTH</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GHWCFG4</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xD3F0A030</resetValue>
+          <fields>
+            <field>
+              <name>G_NUMDEVPERIOEPS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_PARTIALPWRDN</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_AHBFREQ</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_HIBERNATION</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_EXTENDEDHIBERNATION</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_ACGSUPT</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_ENHANCEDLPMSUPT</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_PHYDATAWIDTH</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_NUMCTLEPS</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_IDDQFLTR</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_VBUSVALIDFLTR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_AVALIDFLTR</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_BVALIDFLTR</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_SESSENDFLTR</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_DEDFIFOMODE</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_INEPS</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_DESCDMAENABLED</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_DESCDMA</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GDFIFOCFG</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GDFIFOCFG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPINFOBASEADDR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HPTXFSIZ</name>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>PTXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PTXFSIZE</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTXF1</name>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>INEP1TXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEP1TXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTXF2</name>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>INEP2TXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEP2TXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTXF3</name>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>INEP3TXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEP3TXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTXF4</name>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>INEP4TXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEP4TXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCFG</name>
+          <addressOffset>0x400</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_FSLSPCLKSEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FSLSSUPP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ENA32KHZS</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESCDMA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRLISTEN</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PERSCHEDENA</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_MODECHTIMEN</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HFIR</name>
+          <addressOffset>0x404</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000017D7</resetValue>
+          <fields>
+            <field>
+              <name>FRINT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HFIRRLDCTRL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HFNUM</name>
+          <addressOffset>0x408</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003FFF</resetValue>
+          <fields>
+            <field>
+              <name>FRNUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRREM</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HPTXSTS</name>
+          <addressOffset>0x410</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00080100</resetValue>
+          <fields>
+            <field>
+              <name>PTXFSPCAVAIL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PTXQSPCAVAIL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PTXQTOP</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HAINT</name>
+          <addressOffset>0x414</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HAINT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HAINTMSK</name>
+          <addressOffset>0x418</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HAINTMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HFLBADDR</name>
+          <addressOffset>0x41C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HFLBADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HPRT</name>
+          <addressOffset>0x440</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRTCONNSTS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRTCONNDET</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTENCHNG</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTOVRCURRACT</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRTOVRCURRCHNG</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTRES</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTSUSP</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTRST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTLNSTS</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRTPWR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTTSTCTL</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTSPD</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR0</name>
+          <addressOffset>0x500</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR0</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV0</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE0</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC0</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR0</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM0</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS0</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA0</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT0</name>
+          <addressOffset>0x508</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD0</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL0</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK0</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET0</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR0</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN0</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR0</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR0</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK0</name>
+          <addressOffset>0x50C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK0</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK0</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK0</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK0</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK0</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK0</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK0</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ0</name>
+          <addressOffset>0x510</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT0</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID0</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG0</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA0</name>
+          <addressOffset>0x514</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB0</name>
+          <addressOffset>0x51C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR1</name>
+          <addressOffset>0x520</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS1</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA1</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT1</name>
+          <addressOffset>0x528</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK1</name>
+          <addressOffset>0x52C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ1</name>
+          <addressOffset>0x530</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG1</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA1</name>
+          <addressOffset>0x534</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB1</name>
+          <addressOffset>0x53C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR2</name>
+          <addressOffset>0x540</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR2</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV2</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC2</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR2</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS2</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA2</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT2</name>
+          <addressOffset>0x548</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD2</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL2</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK2</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK2</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET2</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR2</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR2</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN2</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR2</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR2</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR2</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK2</name>
+          <addressOffset>0x54C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK2</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK2</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK2</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK2</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK2</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK2</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK2</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK2</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK2</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK2</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ2</name>
+          <addressOffset>0x550</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT2</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG2</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA2</name>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB2</name>
+          <addressOffset>0x55C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR3</name>
+          <addressOffset>0x560</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV3</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE3</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC3</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR3</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS3</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA3</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT3</name>
+          <addressOffset>0x568</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD3</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR3</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK3</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK3</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET3</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR3</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR3</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN3</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR3</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR3</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR3</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK3</name>
+          <addressOffset>0x56C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK3</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK3</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK3</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK3</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK3</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK3</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK3</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK3</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK3</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK3</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ3</name>
+          <addressOffset>0x570</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG3</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA3</name>
+          <addressOffset>0x574</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB3</name>
+          <addressOffset>0x57C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR4</name>
+          <addressOffset>0x580</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR4</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV4</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE4</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC4</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR4</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS4</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA4</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT4</name>
+          <addressOffset>0x588</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD4</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR4</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL4</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK4</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET4</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR4</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR4</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN4</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR4</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR4</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR4</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK4</name>
+          <addressOffset>0x58C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK4</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK4</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK4</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK4</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK4</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK4</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK4</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK4</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK4</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK4</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ4</name>
+          <addressOffset>0x590</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT4</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG4</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA4</name>
+          <addressOffset>0x594</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB4</name>
+          <addressOffset>0x59C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR5</name>
+          <addressOffset>0x5A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR5</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV5</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE5</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR5</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS5</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA5</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT5</name>
+          <addressOffset>0x5A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD5</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR5</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL5</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK5</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET5</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR5</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN5</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR5</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR5</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR5</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK5</name>
+          <addressOffset>0x5AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK5</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK5</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK5</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK5</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK5</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK5</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK5</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK5</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK5</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ5</name>
+          <addressOffset>0x5B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT5</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG5</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA5</name>
+          <addressOffset>0x5B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB5</name>
+          <addressOffset>0x5BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR6</name>
+          <addressOffset>0x5C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR6</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV6</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE6</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC6</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR6</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS6</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA6</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT6</name>
+          <addressOffset>0x5C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD6</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR6</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL6</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK6</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK6</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR6</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR6</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN6</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR6</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR6</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR6</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK6</name>
+          <addressOffset>0x5CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK6</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK6</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK6</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK6</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK6</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK6</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK6</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK6</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK6</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK6</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ6</name>
+          <addressOffset>0x5D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT6</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG6</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA6</name>
+          <addressOffset>0x5D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB6</name>
+          <addressOffset>0x5DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR7</name>
+          <addressOffset>0x5E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM7</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR7</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV7</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE7</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC7</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR7</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM7</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS7</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA7</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT7</name>
+          <addressOffset>0x5E8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD7</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR7</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL7</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK7</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK7</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET7</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR7</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR7</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN7</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR7</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR7</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR7</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR7</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK7</name>
+          <addressOffset>0x5EC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK7</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK7</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK7</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK7</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK7</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK7</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK7</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK7</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK7</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK7</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK7</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK7</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ7</name>
+          <addressOffset>0x5F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT7</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID7</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG7</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA7</name>
+          <addressOffset>0x5F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB7</name>
+          <addressOffset>0x5FC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCFG</name>
+          <addressOffset>0x800</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08100000</resetValue>
+          <fields>
+            <field>
+              <name>NZSTSOUTHSHK</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEVADDR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERFRLINT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENDEVOUTNAK</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XCVRDLY</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERRATICINTMSK</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPMISCNT</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DESCDMA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERSCHINTVL</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESVALID</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCTL</name>
+          <addressOffset>0x804</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002000</resetValue>
+          <fields>
+            <field>
+              <name>RMTWKUPSIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SFTDISCON</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GNPINNAKSTS</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GOUTNAKSTS</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSTCTL</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SGNPINNAK</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CGNPINNAK</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SGOUTNAK</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CGOUTNAK</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PWRONPRGDONE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GMC</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IGNRFRMNUM</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKONBBLE</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCOUNTONBNA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEEPSLEEPBESLREJECT</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DSTS</name>
+          <addressOffset>0x808</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>SUSPSTS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENUMSPD</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERRTICERR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFFN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DEVLNSTS</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPMSK</name>
+          <addressOffset>0x810</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DI_XFERCOMPLMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_EPDISBLDMSK</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_AHBERMSK</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMEOUTMSK</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTKNTXFEMPMSK</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTKNEPMISMSK</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPNAKEFFMSK</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFOUNDRNMSK</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAININTRMSK</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_NAKMSK</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPMSK</name>
+          <addressOffset>0x814</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPLMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLDMSK</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERMSK</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUPMSK</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDISMSK</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVDMSK</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERRMSK</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAOUTINTRMSK</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERRMSK</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKMSK</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYETMSK</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAINT</name>
+          <addressOffset>0x818</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INEPINT0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT0</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT4</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT6</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAINTMSK</name>
+          <addressOffset>0x81C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INEPMSK0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK0</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK4</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK6</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DVBUSDIS</name>
+          <addressOffset>0x828</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000017D7</resetValue>
+          <fields>
+            <field>
+              <name>DVBUSDIS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DVBUSPULSE</name>
+          <addressOffset>0x82C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000005B8</resetValue>
+          <fields>
+            <field>
+              <name>DVBUSPULSE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTHRCTL</name>
+          <addressOffset>0x830</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08020020</resetValue>
+          <fields>
+            <field>
+              <name>NONISOTHREN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ISOTHREN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXTHRLEN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBTHRRATIO</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXTHREN</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXTHRLEN</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBPRKEN</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPEMPMSK</name>
+          <addressOffset>0x834</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFEMPMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL0</name>
+          <addressOffset>0x900</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP0</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS0</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE0</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL0</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM0</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK0</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK0</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS0</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA0</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT0</name>
+          <addressOffset>0x908</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD0</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT0</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS0</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF0</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP0</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR0</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR0</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT0</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ0</name>
+          <addressOffset>0x910</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT0</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA0</name>
+          <addressOffset>0x914</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS0</name>
+          <addressOffset>0x918</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB0</name>
+          <addressOffset>0x91C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL1</name>
+          <addressOffset>0x920</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK1</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK1</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID1</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS1</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA1</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT1</name>
+          <addressOffset>0x928</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ1</name>
+          <addressOffset>0x930</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA1</name>
+          <addressOffset>0x934</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS1</name>
+          <addressOffset>0x938</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB1</name>
+          <addressOffset>0x93C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL2</name>
+          <addressOffset>0x940</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP2</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS2</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL2</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM2</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK2</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK2</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID2</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS2</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA2</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT2</name>
+          <addressOffset>0x948</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD2</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT2</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP2</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS2</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF2</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP2</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN2</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR2</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR2</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT2</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT2</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ2</name>
+          <addressOffset>0x950</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT2</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA2</name>
+          <addressOffset>0x954</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS2</name>
+          <addressOffset>0x958</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB2</name>
+          <addressOffset>0x95C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL3</name>
+          <addressOffset>0x960</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>DI_MPS3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_USBACTEP3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_NAKSTS3</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_EPTYPE3</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_STALL3</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_TXFNUM3</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_CNAK3</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK3</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID3</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_EPDIS3</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_EPENA3</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT3</name>
+          <addressOffset>0x968</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD3</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR3</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP3</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS3</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF3</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP3</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN3</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR3</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR3</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT3</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT3</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ3</name>
+          <addressOffset>0x970</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA3</name>
+          <addressOffset>0x974</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS3</name>
+          <addressOffset>0x978</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB3</name>
+          <addressOffset>0x97C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL4</name>
+          <addressOffset>0x980</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP4</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS4</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE4</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL4</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM4</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK4</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK4</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID4</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS4</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA4</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT4</name>
+          <addressOffset>0x988</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD4</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR4</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT4</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS4</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF4</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP4</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN4</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR4</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR4</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT4</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT4</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ4</name>
+          <addressOffset>0x990</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT4</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA4</name>
+          <addressOffset>0x994</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS4</name>
+          <addressOffset>0x998</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB4</name>
+          <addressOffset>0x99C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL5</name>
+          <addressOffset>0x9A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>DI_MPS5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_USBACTEP5</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_NAKSTS5</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_EPTYPE5</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_STALL5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_TXFNUM5</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_CNAK5</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK5</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID5</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_EPDIS5</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_EPENA5</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT5</name>
+          <addressOffset>0x9A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD5</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR5</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT5</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP5</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF5</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP5</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR5</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR5</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT5</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT5</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ5</name>
+          <addressOffset>0x9B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT5</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA5</name>
+          <addressOffset>0x9B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS5</name>
+          <addressOffset>0x9B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB5</name>
+          <addressOffset>0x9BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL6</name>
+          <addressOffset>0x9C0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP6</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS6</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE6</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL6</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM6</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK6</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK6</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID6</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS6</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA6</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT6</name>
+          <addressOffset>0x9C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD6</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR6</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT6</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP6</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS6</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP6</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN6</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR6</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR6</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT6</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT6</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ6</name>
+          <addressOffset>0x9D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT6</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA6</name>
+          <addressOffset>0x9D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS6</name>
+          <addressOffset>0x9D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB6</name>
+          <addressOffset>0x9DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL0</name>
+          <addressOffset>0xB00</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP0</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS0</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE0</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP0</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK0</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK0</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS0</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA0</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT0</name>
+          <addressOffset>0xB08</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD0</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP0</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD0</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP0</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR0</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR0</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT0</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD0</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ0</name>
+          <addressOffset>0xB10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT0</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT0</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA0</name>
+          <addressOffset>0xB14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB0</name>
+          <addressOffset>0xB1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL1</name>
+          <addressOffset>0xB20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP1</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK1</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK1</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID1</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS1</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA1</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT1</name>
+          <addressOffset>0xB28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ1</name>
+          <addressOffset>0xB30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA1</name>
+          <addressOffset>0xB34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB1</name>
+          <addressOffset>0xB3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL2</name>
+          <addressOffset>0xB40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP2</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS2</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP2</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL2</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK2</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK2</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID2</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS2</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA2</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT2</name>
+          <addressOffset>0xB48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD2</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP2</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS2</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD2</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP2</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR2</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR2</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR2</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT2</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT2</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD2</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ2</name>
+          <addressOffset>0xB50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT2</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA2</name>
+          <addressOffset>0xB54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB2</name>
+          <addressOffset>0xB5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL3</name>
+          <addressOffset>0xB60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS3</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE3</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP3</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL3</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK3</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK3</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID3</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS3</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA3</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT3</name>
+          <addressOffset>0xB68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD3</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR3</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS3</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD3</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP3</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR3</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR3</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR3</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT3</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT3</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ3</name>
+          <addressOffset>0xB70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA3</name>
+          <addressOffset>0xB74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB3</name>
+          <addressOffset>0xB7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL4</name>
+          <addressOffset>0xB80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP4</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS4</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE4</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP4</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL4</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK4</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK4</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID4</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS4</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA4</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT4</name>
+          <addressOffset>0xB88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD4</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR4</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP4</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD4</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP4</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR4</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR4</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR4</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT4</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT4</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD4</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ4</name>
+          <addressOffset>0xB90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT4</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA4</name>
+          <addressOffset>0xB94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB4</name>
+          <addressOffset>0xB9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL5</name>
+          <addressOffset>0xBA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP5</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS5</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE5</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP5</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK5</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK5</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID5</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS5</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA5</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT5</name>
+          <addressOffset>0xBA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD5</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR5</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP5</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS5</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP5</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR5</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR5</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT5</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT5</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD5</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ5</name>
+          <addressOffset>0xBB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT5</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA5</name>
+          <addressOffset>0xBB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB5</name>
+          <addressOffset>0xBBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL6</name>
+          <addressOffset>0xBC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP6</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS6</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE6</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP6</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL6</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK6</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK6</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID6</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS6</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA6</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT6</name>
+          <addressOffset>0xBC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD6</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR6</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP6</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS6</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD6</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR6</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR6</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR6</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT6</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT6</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD6</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ6</name>
+          <addressOffset>0xBD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT6</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA6</name>
+          <addressOffset>0xBD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB6</name>
+          <addressOffset>0xBDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCGCCTL</name>
+          <addressOffset>0xE00</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STOPPCLK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GATEHCLK</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWRCLMP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSTPDWNMODULE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHYSLEEP</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1SUSPENDED</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESETAFTERSUSP</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>USB_WRAP</name>
+      <description>Peripheral USB_WRAP</description>
+      <groupName>USB_WRAP</groupName>
+      <baseAddress>0x3F439000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>OTG_CONF</name>
+          <description>USB OTG Wrapper Configure Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001C0000</resetValue>
+          <fields>
+            <field>
+              <name>SRP_SESSEND_OVERRIDE</name>
+              <description>This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRP_SESSEND_VALUE</name>
+              <description>Software over-ride value of srp session end signal.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHY_SEL</name>
+              <description>Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DFIFO_FORCE_PD</name>
+              <description>Force the dfifo to go into low power mode. The data in dfifo will not lost.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBNCE_FLTR_BYPASS</name>
+              <description>Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXCHG_PINS_OVERRIDE</name>
+              <description>Enable software controlle USB D+ D- exchange</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXCHG_PINS</name>
+              <description>USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREFH</name>
+              <description>Control single-end input high threshold,1.76V to 2V, step 80mV</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREFL</name>
+              <description>Control single-end input low threshold,0.8V to 1.04V, step 80mV</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREF_OVERRIDE</name>
+              <description>Enable software controlle input  threshold</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_PULL_OVERRIDE</name>
+              <description>Enable software controlle USB D+ D- pullup pulldown</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DP_PULLUP</name>
+              <description>Controlle USB D+ pullup</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DP_PULLDOWN</name>
+              <description>Controlle USB D+ pulldown</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DM_PULLUP</name>
+              <description>Controlle USB D+ pullup</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DM_PULLDOWN</name>
+              <description>Controlle USB D+ pulldown</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULLUP_VALUE</name>
+              <description>Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_ENABLE</name>
+              <description>Enable USB pad function</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_CLK_FORCE_ON</name>
+              <description>Force ahb clock always on</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHY_CLK_FORCE_ON</name>
+              <description>Force phy clock always on</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHY_TX_EDGE_SEL</name>
+              <description>Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DFIFO_FORCE_PU</name>
+              <description>Disable the dfifo to go into low power mode. The data in dfifo will not lost.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Disable auto clock gating of CSR registers</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEST_CONF</name>
+          <description>USB Internal PHY Testing Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEST_ENABLE</name>
+              <description>Enable test of the USB pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TEST_USB_OE</name>
+              <description>USB pad oen in test</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TEST_TX_DP</name>
+              <description>USB D+ tx value in test</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TEST_TX_DM</name>
+              <description>USB D- tx value in test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TEST_RX_RCV</name>
+              <description>USB differential rx value in test</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TEST_RX_DP</name>
+              <description>USB D+ rx value in test</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TEST_RX_DM</name>
+              <description>USB D- rx value in test</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version Control Register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02102010</resetValue>
+          <fields>
+            <field>
+              <name>USB_WRAP_DATE</name>
+              <description>Date register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>XTS_AES</name>
+      <description>XTS-AES-128 Flash Encryption</description>
+      <groupName>XTS_AES</groupName>
+      <baseAddress>0x6003A100</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x60</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>PLAIN_%s</name>
+          <description>Plaintext register %s</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLAIN_0</name>
+              <description>This register stores %sth 32-bit piece of plaintext.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LINESIZE</name>
+          <description>Configures the size of target memory space</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINESIZE</name>
+              <description>Configures the data size of a single encryption. 0: 128 bits. 1: 256 bits. 2: 512 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESTINATION</name>
+          <description>Configures the type of the external memory</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DESTINATION</name>
+              <description>Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occur if users write 1. 0: flash. 1: external RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PHYSICAL_ADDRESS</name>
+          <description>Physical address</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PHYSICAL_ADDRESS</name>
+              <description>Physical address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>Activates AES algorithm</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRIGGER</name>
+              <description>Set to enable manual encryption.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RELEASE</name>
+          <description>Release control</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RELEASE</name>
+              <description>Set to grant SPI1 access to encrypted result.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESTROY</name>
+          <description>Destroys control</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DESTROY</name>
+              <description>Set to destroy encrypted result.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>Status register</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Indicates the status of the Manual Encryption block. 0x0 (XTS_AES_IDLE): idle. 0x1 (XTS_AES_BUSY): busy with encryption. 0x2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_RELEASE): encrypted result is accessible to SPI.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20190514</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/tools/ide-debug/svd/esp32s3.svd b/tools/ide-debug/svd/esp32s3.svd
new file mode 100644
index 00000000000..a36e851ac7a
--- /dev/null
+++ b/tools/ide-debug/svd/esp32s3.svd
@@ -0,0 +1,67571 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+  <vendor>ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.</vendor>
+  <vendorID>ESPRESSIF</vendorID>
+  <name>ESP32-S3</name>
+  <series>ESP32-S3</series>
+  <version>12</version>
+  <description>32-bit MCU &amp; 2.4 GHz Wi-Fi &amp; Bluetooth 5 (LE)</description>
+  <licenseText>
+    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+</licenseText>
+  <cpu>
+    <name>Xtensa LX7</name>
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>true</fpuPresent>
+    <nvicPrioBits>3</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>32</addressUnitBits>
+  <width>32</width>
+  <resetValue>0x00000000</resetValue>
+  <resetMask>0xFFFFFFFF</resetMask>
+  <peripherals>
+    <peripheral>
+      <name>AES</name>
+      <description>AES (Advanced Encryption Standard) Accelerator</description>
+      <groupName>AES</groupName>
+      <baseAddress>0x6003A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>AES</name>
+        <value>77</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>KEY_%s</name>
+          <description>AES key register %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_0</name>
+              <description>Stores AES keys.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TEXT_IN_%s</name>
+          <description>Source data register %s</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_IN_0</name>
+              <description>Stores the source data when the AES accelerator operates in the Typical AES working mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TEXT_OUT_%s</name>
+          <description>Result data register %s</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEXT_OUT_0</name>
+              <description>Stores the result data when the AES accelerator operates in the Typical AES working mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>AES Mode register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Defines the key length and the encryption/decryption of the AES accelerator.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>AES trigger register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRIGGER</name>
+              <description>Set this bit to 1 to start AES calculation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>AES state register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Stores the working status of the AES accelerator. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>IV_MEM[%s]</name>
+          <description>The memory that stores initialization vector</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>H_MEM[%s]</name>
+          <description>The memory that stores GCM hash subkey</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>J0_MEM[%s]</name>
+          <description>The memory that stores J0</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>T0_MEM[%s]</name>
+          <description>The memory that stores T0</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>DMA_ENABLE</name>
+          <description>AES accelerator working mode register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_ENABLE</name>
+              <description>Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_MODE</name>
+          <description>AES cipher block mode register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_MODE</name>
+              <description>Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BLOCK_NUM</name>
+          <description>AES block number register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BLOCK_NUM</name>
+              <description>Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INC_SEL</name>
+          <description>Standard incrementing function configure register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INC_SEL</name>
+              <description>Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AAD_BLOCK_NUM</name>
+          <description>Additional Authential Data block number register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AAD_BLOCK_NUM</name>
+              <description>Those bits stores the number of AAD block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REMAINDER_BIT_NUM</name>
+          <description>AES remainder bit number register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REMAINDER_BIT_NUM</name>
+              <description>Those bits stores the number of remainder bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE</name>
+          <description>AES continue register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE</name>
+              <description>Set this bit to 1 to continue GCM operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>AES Interrupt clear register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_CLEAR</name>
+              <description>Set this bit to 1 to clear AES interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>DMA-AES Interrupt enable register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT_ENA</name>
+              <description>Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>AES version control register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20191210</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This bits stores the version information of AES.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_EXIT</name>
+          <description>AES-DMA exit config</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_EXIT</name>
+              <description>Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>APB_CTRL</name>
+      <description>Advanced Peripheral Bus Controller</description>
+      <groupName>APB_CTRL</groupName>
+      <baseAddress>0x60026000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xCC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SYSCLK_CONF</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PRE_DIV_CNT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_320M_EN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_TICK_CNT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TICK_CONF</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010727</resetValue>
+          <fields>
+            <field>
+              <name>XTAL_TICK_NUM</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_TICK_NUM</name>
+              <description>******* Description ***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_ENABLE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_OUT_EN</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>CLK20_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK22_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK44_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_BB_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK80_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK160_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_320M_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_ADC_INF_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DAC_CPU_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK40X_BB_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_XTAL_OEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_CFG</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_CFG</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_BB_CFG_2</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_BB_CFG_2</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_CLK_EN</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFCE030</resetValue>
+          <fields>
+            <field>
+              <name>WIFI_CLK_EN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WIFI_RST_EN</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WIFI_RST</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HOST_INF_SEL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PERI_IO_SWAP</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_MEM_PMS_LOCK</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_MEM_PMS_LOCK</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_MEM_WRITEBACK_BYPASS</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WRITEBACK_BYPASS</name>
+              <description>Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE0_ATTR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE0_ATTR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE1_ATTR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE1_ATTR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE2_ATTR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE2_ATTR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE3_ATTR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE3_ATTR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE0_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE1_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE2_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20000000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE3_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x30000000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE0_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE0_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE1_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE1_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE2_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE2_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_ACE3_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_ACE3_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE0_ATTR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_ACE0_ATTR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE1_ATTR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_ACE1_ATTR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE2_ATTR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_ACE2_ATTR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE3_ATTR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_ACE3_ATTR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE0_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE1_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE2_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20000000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE3_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x30000000</resetValue>
+          <fields>
+            <field>
+              <name>S</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE0_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_ACE0_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE1_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_ACE1_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE2_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_ACE2_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_ACE3_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001000</resetValue>
+          <fields>
+            <field>
+              <name>SRAM_ACE3_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_PMS_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_INT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_REJECT_CLR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SPI_MEM_REJECT_CDE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REJECT_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_ADDR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_WIN_ACCESS_EN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDCY_SIG0</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_SIG0</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDCY_ANDOR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDCY_SIG1</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDCY_SIG1</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDCY_NANDOR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRONT_END_MEM_PD</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000055</resetValue>
+          <fields>
+            <field>
+              <name>AGC_MEM_FORCE_PU</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AGC_MEM_FORCE_PD</name>
+              <description>******* Description ***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBUS_MEM_FORCE_PU</name>
+              <description>******* Description ***********</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PBUS_MEM_FORCE_PD</name>
+              <description>******* Description ***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DC_MEM_FORCE_PU</name>
+              <description>******* Description ***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DC_MEM_FORCE_PD</name>
+              <description>******* Description ***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREQ_MEM_FORCE_PU</name>
+              <description>******* Description ***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREQ_MEM_FORCE_PD</name>
+              <description>******* Description ***********</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_ECC_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00200000</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_PAGE_SIZE</name>
+              <description>Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_PAGE_SIZE</name>
+              <description>Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKGATE_FORCE_ON</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003FFF</resetValue>
+          <fields>
+            <field>
+              <name>ROM_CLKGATE_FORCE_ON</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_CLKGATE_FORCE_ON</name>
+              <description>******* Description ***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_POWER_DOWN</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ROM_POWER_DOWN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_POWER_DOWN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_POWER_UP</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003FFF</resetValue>
+          <fields>
+            <field>
+              <name>ROM_POWER_UP</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_POWER_UP</name>
+              <description>******* Description ***********</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RETENTION_CPU_LINK_ADDR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NOBYPASS_CPU_ISO_RST</name>
+              <description>******* Description ***********</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL1</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RETENTION_TAG_LINK_ADDR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL2</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001FEFF0</resetValue>
+          <fields>
+            <field>
+              <name>RET_ICACHE_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RET_ICACHE_VLD_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RET_ICACHE_START_POINT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RET_ICACHE_ENABLE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL3</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFF0</resetValue>
+          <fields>
+            <field>
+              <name>RET_DCACHE_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RET_DCACHE_VLD_SIZE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RET_DCACHE_START_POINT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RET_DCACHE_ENABLE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL4</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>RETENTION_INV_CFG</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL5</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RETENTION_DISABLE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101150</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version control</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>APB_SARADC</name>
+      <description>Successive Approximation Register Analog to Digital Converter</description>
+      <groupName>APB_SARADC</groupName>
+      <baseAddress>0x60040000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x70</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>APB_ADC</name>
+        <value>65</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>configure apb saradc controller</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x407F8240</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_START_FORCE</name>
+              <description>enable start saradc by sw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_START</name>
+              <description>start saradc by sw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_WORK_MODE</name>
+              <description>0: single mode, 1: double mode, 2: alternate mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_SEL</name>
+              <description>0: SAR1, 1: SAR2, only work for single SAR mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_GATED</name>
+              <description>enable SAR CLK gate when saradc idle</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR_CLK_DIV</name>
+              <description>SAR clock divider</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_PATT_LEN</name>
+              <description>0 ~ 15 means length 1 ~ 16</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_PATT_P_CLEAR</name>
+              <description>clear the pointer of pattern table for DIG ADC1 CTRL</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_PATT_P_CLEAR</name>
+              <description>clear the pointer of pattern table for DIG ADC2 CTRL</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_DATA_SAR_SEL</name>
+              <description>1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_DATA_TO_I2S</name>
+              <description>1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_XPD_SAR_FORCE</name>
+              <description>force option to xpd sar blocks</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_WAIT_ARB_CYCLE</name>
+              <description>wait arbit signal stable after sar_done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>configure apb saradc controller</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000A1FE</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_MEAS_NUM_LIMIT</name>
+              <description>enable apb saradc limit the sample num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_MAX_MEAS_NUM</name>
+              <description>max conversion number</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR1_INV</name>
+              <description>1: data to DIG ADC1 CTRL is inverted, otherwise not</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_SAR2_INV</name>
+              <description>1: data to DIG ADC2 CTRL is inverted, otherwise not</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_SEL</name>
+              <description>1: select saradc timer 0: i2s_ws trigger</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_TARGET</name>
+              <description>to set saradc timer target</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_TIMER_EN</name>
+              <description>to enable saradc timer trigger</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL1</name>
+          <description>configure saradc filter</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FILTER_FACTOR1</name>
+              <description>apb saradc factor1</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_FACTOR0</name>
+              <description>apb saradc factor0</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_WAIT</name>
+          <description>configure apb saradc fsm</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00FF0808</resetValue>
+          <fields>
+            <field>
+              <name>SARADC_XPD_WAIT</name>
+              <description>the cycle which saradc controller in xpd state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_RSTB_WAIT</name>
+              <description>the cycle which saradc controller in rst state</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC_STANDBY_WAIT</name>
+              <description>the cycle which saradc controller in standby state</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_STATUS</name>
+          <description>saradc1 status for debug</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_STATUS</name>
+              <description>saradc1 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_STATUS</name>
+          <description>saradc2 status for debug</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_STATUS</name>
+              <description>saradc2 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_PATT_TAB1</name>
+          <description>configure apb saradc pattern table</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 1 (each item 6bit)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_PATT_TAB2</name>
+          <description>configure apb saradc pattern table</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 1 (each item 6bit)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_PATT_TAB3</name>
+          <description>configure apb saradc pattern table</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_PATT_TAB3</name>
+              <description>Item 8 ~ 11 for pattern table 1 (each item 6bit)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR1_PATT_TAB4</name>
+          <description>configure apb saradc pattern table</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR1_PATT_TAB4</name>
+              <description>Item 12 ~ 15 for pattern table 1 (each item 6bit)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_PATT_TAB1</name>
+          <description>configure apb saradc pattern table</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_PATT_TAB1</name>
+              <description>item 0 ~ 3 for pattern table 2 (each item 6bit)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_PATT_TAB2</name>
+          <description>configure apb saradc pattern table</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_PATT_TAB2</name>
+              <description>Item 4 ~ 7 for pattern table 2 (each item 6bit)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_PATT_TAB3</name>
+          <description>configure apb saradc pattern table</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_PATT_TAB3</name>
+              <description>Item 8 ~ 11 for pattern table 2 (each item 6bit)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR2_PATT_TAB4</name>
+          <description>configure apb saradc pattern table</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SARADC_SAR2_PATT_TAB4</name>
+              <description>Item 12 ~ 15 for pattern table 2 (each item 6bit)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADC_ARB_CTRL</name>
+          <description>configure apb saradc arbit</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000900</resetValue>
+          <fields>
+            <field>
+              <name>ADC_ARB_APB_FORCE</name>
+              <description>adc2 arbiter force to enableapb controller</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_FORCE</name>
+              <description>adc2 arbiter force to enable rtc controller</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_FORCE</name>
+              <description>adc2 arbiter force to enable wifi controller</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_GRANT_FORCE</name>
+              <description>adc2 arbiter force grant</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_APB_PRIORITY</name>
+              <description>Set adc2 arbiterapb priority</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_RTC_PRIORITY</name>
+              <description>Set adc2 arbiter rtc priority</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_WIFI_PRIORITY</name>
+              <description>Set adc2 arbiter wifi priority</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC_ARB_FIX_PRIORITY</name>
+              <description>adc2 arbiter uses fixed priority</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CTRL0</name>
+          <description>configure apb saradc arbit</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x006B4000</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_CHANNEL1</name>
+              <description>configure the filter1 channel</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_CHANNEL0</name>
+              <description>configure the filter0 channel</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_RESET</name>
+              <description>enable apb_adc1_filter</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC1_DATA_STATUS</name>
+          <description>get apb saradc sample data</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC1_DATA</name>
+              <description>apbsaradc sample data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES0_CTRL</name>
+          <description>configure apb saradc thres monitor</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>THRES0_CHANNEL</name>
+              <description>configure which channel thres0 monitor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH</name>
+              <description>thres0 monitor high thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_LOW</name>
+              <description>thres0 monitor low thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES1_CTRL</name>
+          <description>configure apb saradc thres monitor</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0003FFED</resetValue>
+          <fields>
+            <field>
+              <name>THRES1_CHANNEL</name>
+              <description>configure which channel thres0 monitor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH</name>
+              <description>thres1 monitor high thres</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES1_LOW</name>
+              <description>thres1 monitor low thres</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>THRES_CTRL</name>
+          <description>configure thres monitor enable</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES_ALL_EN</name>
+              <description>enable thres0 to monitor all channel</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES3_EN</name>
+              <description>no public</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES2_EN</name>
+              <description>no public</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES1_EN</name>
+              <description>enable thres1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_EN</name>
+              <description>enable thres0</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>enable interrupt</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES1_LOW_INT_ENA</name>
+              <description>interrupt of thres1 low</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_LOW_INT_ENA</name>
+              <description>interrupt of thres0 low</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH_INT_ENA</name>
+              <description>interrupt of thres1 high</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH_INT_ENA</name>
+              <description>interrupt of thres0 high</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ENA</name>
+              <description>interrupt of sar2 done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ENA</name>
+              <description>interrupt of sar1 done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>raw of interrupt</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES1_LOW_INT_RAW</name>
+              <description>interrupt of thres1 low</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES0_LOW_INT_RAW</name>
+              <description>interrupt of thres0 low</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH_INT_RAW</name>
+              <description>interrupt of thres1 high</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH_INT_RAW</name>
+              <description>interrupt of thres0 high</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_RAW</name>
+              <description>interrupt of sar2 done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_RAW</name>
+              <description>interrupt of sar1 done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>state of interrupt</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES1_LOW_INT_ST</name>
+              <description>interrupt of thres1 low</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES0_LOW_INT_ST</name>
+              <description>interrupt of thres0 low</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH_INT_ST</name>
+              <description>interrupt of thres1 high</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH_INT_ST</name>
+              <description>interrupt of thres0 high</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_ST</name>
+              <description>interrupt of sar2 done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_ST</name>
+              <description>interrupt of sar1 done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>clear interrupt</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>THRES1_LOW_INT_CLR</name>
+              <description>interrupt of thres1 low</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>THRES0_LOW_INT_CLR</name>
+              <description>interrupt of thres0 low</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>THRES1_HIGH_INT_CLR</name>
+              <description>interrupt of thres1 high</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>THRES0_HIGH_INT_CLR</name>
+              <description>interrupt of thres0 high</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC2_DONE_INT_CLR</name>
+              <description>interrupt of sar2 done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_SARADC1_DONE_INT_CLR</name>
+              <description>interrupt of sar1 done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>configure apb saradc dma</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>APB_ADC_EOF_NUM</name>
+              <description>the dma_in_suc_eof gen when sample cnt = spi_eof_num</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_RESET_FSM</name>
+              <description>reset_apb_adc_state</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_ADC_TRANS</name>
+              <description>enable apb_adc use spi_dma</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADC_CLKM_CONF</name>
+          <description>configure apb saradc clock</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>CLKM_DIV_NUM</name>
+              <description>Integral  clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_B</name>
+              <description>Fractional clock divider numerator value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKM_DIV_A</name>
+              <description>Fractional clock divider denominator value</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>no public</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_SEL</name>
+              <description>Set this bit to enable clk_apll</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_SARADC2_DATA_STATUS</name>
+          <description>get apb saradc2 sample data</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_SARADC2_DATA</name>
+              <description>apb saradc2 sample data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_CTRL_DATE</name>
+          <description>version</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101180</resetValue>
+          <fields>
+            <field>
+              <name>APB_CTRL_DATE</name>
+              <description>version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DEBUG_ASSIST</name>
+      <description>Debug Assist</description>
+      <groupName>DEBUG_ASSIST</groupName>
+      <baseAddress>0x600CE000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x15C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>ASSIST_DEBUG</name>
+        <value>83</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CORE_0_INTERRUPT_ENA</name>
+          <description>core0 monitor enable configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_ENA</name>
+              <description>Core0 dram0 area0 read monitor enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_ENA</name>
+              <description>Core0 dram0 area0 write monitor enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_ENA</name>
+              <description>Core0 dram0 area1 read monitor enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_ENA</name>
+              <description>Core0 dram0 area1 write monitor enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_ENA</name>
+              <description>Core0 PIF area0 read monitor enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_ENA</name>
+              <description>Core0 PIF area0 write monitor enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_ENA</name>
+              <description>Core0 PIF area1 read monitor enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_ENA</name>
+              <description>Core0 PIF area1 write monitor enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_ENA</name>
+              <description>Core0 stackpoint overflow monitor enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_ENA</name>
+              <description>Core0 stackpoint underflow monitor enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>IBUS busy monitor enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>DBUS busy monitor enbale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTERRUPT_RAW</name>
+          <description>core0 monitor interrupt status register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_RAW</name>
+              <description>Core0 dram0 area0 read monitor interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_RAW</name>
+              <description>Core0 dram0 area0 write monitor interrupt status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_RAW</name>
+              <description>Core0 dram0 area1 read monitor interrupt status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_RAW</name>
+              <description>Core0 dram0 area1 write monitor interrupt status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_RAW</name>
+              <description>Core0 PIF area0 read monitor interrupt status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_RAW</name>
+              <description>Core0 PIF area0 write monitor interrupt status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_RAW</name>
+              <description>Core0 PIF area1 read monitor interrupt status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_RAW</name>
+              <description>Core0 PIF area1 write monitor interrupt status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_RAW</name>
+              <description>Core0 stackpoint overflow monitor interrupt status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_RAW</name>
+              <description>Core0 stackpoint underflow monitor interrupt status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>IBUS busy monitor interrupt status</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>DBUS busy monitor initerrupt status</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTERRUPT_RLS</name>
+          <description>core0 monitor interrupt enable register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_RLS</name>
+              <description>Core0 dram0 area0 read monitor interrupt enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_RLS</name>
+              <description>Core0 dram0 area0 write monitor interrupt enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_RLS</name>
+              <description>Core0 dram0 area1 read monitor interrupt enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_RLS</name>
+              <description>Core0 dram0 area1 write monitor interrupt enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_RLS</name>
+              <description>Core0 PIF area0 read monitor interrupt enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_RLS</name>
+              <description>Core0 PIF area0 write monitor interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_RLS</name>
+              <description>Core0 PIF area1 read monitor interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_RLS</name>
+              <description>Core0 PIF area1 write monitor interrupt enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_RLS</name>
+              <description>Core0 stackpoint overflow monitor interrupt enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_RLS</name>
+              <description>Core0 stackpoint underflow monitor interrupt enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>IBUS busy monitor interrupt enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>DBUS busy monitor interrupt enbale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_INTERRUPT_CLR</name>
+          <description>core0 monitor interrupt clr register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_RD_CLR</name>
+              <description>Core0 dram0 area0 read monitor interrupt clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_WR_CLR</name>
+              <description>Core0 dram0 area0 write monitor interrupt clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_RD_CLR</name>
+              <description>Core0 dram0 area1 read monitor interrupt clr</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_WR_CLR</name>
+              <description>Core0 dram0 area1 write monitor interrupt clr</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_RD_CLR</name>
+              <description>Core0 PIF area0 read monitor interrupt clr</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_0_WR_CLR</name>
+              <description>Core0 PIF area0 write monitor interrupt clr</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_RD_CLR</name>
+              <description>Core0 PIF area1 read monitor interrupt clr</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_AREA_PIF_1_WR_CLR</name>
+              <description>Core0 PIF area1 write monitor interrupt clr</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MIN_CLR</name>
+              <description>Core0 stackpoint overflow monitor interrupt clr</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_SP_SPILL_MAX_CLR</name>
+              <description>Core0 stackpoint underflow monitor interrupt clr</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>IBUS busy monitor interrupt clr</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>DBUS busy monitor interrupt clr</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_0_MIN</name>
+          <description>core0 dram0 region0 addr configuration register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_MIN</name>
+              <description>Core0 dram0 region0 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_0_MAX</name>
+          <description>core0 dram0 region0 addr configuration register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_0_MAX</name>
+              <description>Core0 dram0 region0 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_1_MIN</name>
+          <description>core0 dram0 region1 addr configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_MIN</name>
+              <description>Core0 dram0 region1 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_DRAM0_1_MAX</name>
+          <description>core0 dram0 region1 addr configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_DRAM0_1_MAX</name>
+              <description>Core0 dram0 region1 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_0_MIN</name>
+          <description>core0 PIF region0 addr configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_0_MIN</name>
+              <description>Core0 PIF region0 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_0_MAX</name>
+          <description>core0 PIF region0 addr configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_0_MAX</name>
+              <description>Core0 PIF region0 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_1_MIN</name>
+          <description>core0 PIF region1 addr configuration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_1_MIN</name>
+              <description>Core0 PIF region1 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PIF_1_MAX</name>
+          <description>core0 PIF region1 addr configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PIF_1_MAX</name>
+              <description>Core0 PIF region1 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_SP</name>
+          <description>core0 area sp status register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_SP</name>
+              <description>the stackpointer when first touch region monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_AREA_PC</name>
+          <description>core0 area pc status register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_AREA_PC</name>
+              <description>the PC when first touch region monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_UNSTABLE</name>
+          <description>core0 sp unstable configuration register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_SP_UNSTABLE</name>
+              <description>unstable period when window change,during this period no check stackpointer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MIN</name>
+          <description>core0 sp region configuration regsiter</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MIN</name>
+              <description>stack min value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_MAX</name>
+          <description>core0 sp region configuration regsiter</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_SP_MAX</name>
+              <description>stack max value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_SP_PC</name>
+          <description>core0 sp pc status register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_SP_PC</name>
+              <description>the PC when first touch stack monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGENABLE</name>
+          <description>core0 pdebug configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGENABLE</name>
+              <description>Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_RECORDING</name>
+          <description>core0 pdebug status register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_RECORDING</name>
+              <description>Pdebug record enable,set 1 to record core0 pdebug interface signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGINST</name>
+          <description>core0 pdebug status register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGINST</name>
+              <description>core0 pdebuginst</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGSTATUS</name>
+          <description>core0 pdebug status register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGSTATUS</name>
+              <description>core0 pdebugstatus</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGDATA</name>
+          <description>core0 pdebug status register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGDATA</name>
+              <description>core0_pdebugdata</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGPC</name>
+          <description>core0 pdebug status register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGPC</name>
+              <description>core0_pdebugPC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGLS0STAT</name>
+          <description>core0 pdebug status register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGLS0STAT</name>
+              <description>core0_pdebug_s0stat</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGLS0ADDR</name>
+          <description>core0 pdebug status register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGLS0ADDR</name>
+              <description>core0_pdebug_s0addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_PDEBUGLS0DATA</name>
+          <description>core0 pdebug status register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_PDEBUGLS0DATA</name>
+              <description>core0_pdebug_s0data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_RCD_SP</name>
+          <description>core0 pdebug status register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_RCD_SP</name>
+              <description>core0_stack pointer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_EXCEPTION_MONITOR_0</name>
+          <description>core0 bus busy status regsiter</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_ADDR_0</name>
+              <description>The first iram0's addr[25:2] status when trigger IRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_WR_0</name>
+              <description>The first iram0's wr status when trigger IRAM busy interrupt</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_LOADSTORE_0</name>
+              <description>The first iram0's loadstore status when trigger IRAM busy interrupt</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_EXCEPTION_MONITOR_1</name>
+          <description>core0 bus busy status regsiter</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_ADDR_1</name>
+              <description>The second iram0's addr[25:2] status when trigger IRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_WR_1</name>
+              <description>The second iram0's wr status when trigger IRAM busy interrupt</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_RECORDING_LOADSTORE_1</name>
+              <description>The second iram0's loadstore status when trigger IRAM busy interrupt</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_0</name>
+          <description>core0 bus busy status regsiter</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_ADDR_0</name>
+              <description>The first dram0's addr[25:4] status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_WR_0</name>
+              <description>The first dram0's wr status when trigger DRAM busy interrupt</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_1</name>
+          <description>core0 bus busy status regsiter</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_BYTEEN_0</name>
+              <description>The first dram0's byteen status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_2</name>
+          <description>core0 bus busy status regsiter</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_PC_0</name>
+              <description>The first dram0's PC status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_3</name>
+          <description>core0 bus busy status regsiter</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_ADDR_1</name>
+              <description>The second dram0's addr[25:4] status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_WR_1</name>
+              <description>The second dram0's wr status when trigger DRAM busy interrupt</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_4</name>
+          <description>core0 bus busy configuration regsiter</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_BYTEEN_1</name>
+              <description>The second dram0's byteen status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_EXCEPTION_MONITOR_5</name>
+          <description>core0 bus busy configuration regsiter</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_RECORDING_PC_1</name>
+              <description>The second dram0's PC status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_INTERRUPT_ENA</name>
+          <description>Core1 monitor enable configuration register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_RD_ENA</name>
+              <description>Core1 dram0 area0 read monitor enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_WR_ENA</name>
+              <description>Core1 dram0 area0 write monitor enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_RD_ENA</name>
+              <description>Core1 dram0 area1 read monitor enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_WR_ENA</name>
+              <description>Core1 dram0 area1 write monitor enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_0_RD_ENA</name>
+              <description>Core1 PIF area0 read monitor enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_0_WR_ENA</name>
+              <description>Core1 PIF area0 write monitor enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_1_RD_ENA</name>
+              <description>Core1 PIF area1 read monitor enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_1_WR_ENA</name>
+              <description>Core1 PIF area1 write monitor enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_SP_SPILL_MIN_ENA</name>
+              <description>Core1 stackpoint overflow monitor enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_SP_SPILL_MAX_ENA</name>
+              <description>Core1 stackpoint underflow monitor enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>IBUS busy monitor enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_EXCEPTION_MONITOR_ENA</name>
+              <description>DBUS busy monitor enbale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_INTERRUPT_RAW</name>
+          <description>Core1 monitor interrupt status register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_RD_RAW</name>
+              <description>Core1 dram0 area0 read monitor interrupt status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_WR_RAW</name>
+              <description>Core1 dram0 area0 write monitor interrupt status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_RD_RAW</name>
+              <description>Core1 dram0 area1 read monitor interrupt status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_WR_RAW</name>
+              <description>Core1 dram0 area1 write monitor interrupt status</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_0_RD_RAW</name>
+              <description>Core1 PIF area0 read monitor interrupt status</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_0_WR_RAW</name>
+              <description>Core1 PIF area0 write monitor interrupt status</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_1_RD_RAW</name>
+              <description>Core1 PIF area1 read monitor interrupt status</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_1_WR_RAW</name>
+              <description>Core1 PIF area1 write monitor interrupt status</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_SP_SPILL_MIN_RAW</name>
+              <description>Core1 stackpoint overflow monitor interrupt status</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_SP_SPILL_MAX_RAW</name>
+              <description>Core1 stackpoint underflow monitor interrupt status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>IBUS busy monitor interrupt status</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_EXCEPTION_MONITOR_RAW</name>
+              <description>DBUS busy monitor initerrupt status</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_INTERRUPT_RLS</name>
+          <description>Core1 monitor interrupt enable register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_RD_RLS</name>
+              <description>Core1 dram0 area0 read monitor interrupt enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_WR_RLS</name>
+              <description>Core1 dram0 area0 write monitor interrupt enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_RD_RLS</name>
+              <description>Core1 dram0 area1 read monitor interrupt enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_WR_RLS</name>
+              <description>Core1 dram0 area1 write monitor interrupt enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_0_RD_RLS</name>
+              <description>Core1 PIF area0 read monitor interrupt enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_0_WR_RLS</name>
+              <description>Core1 PIF area0 write monitor interrupt enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_1_RD_RLS</name>
+              <description>Core1 PIF area1 read monitor interrupt enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_1_WR_RLS</name>
+              <description>Core1 PIF area1 write monitor interrupt enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_SP_SPILL_MIN_RLS</name>
+              <description>Core1 stackpoint overflow monitor interrupt enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_SP_SPILL_MAX_RLS</name>
+              <description>Core1 stackpoint underflow monitor interrupt enable</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>IBUS busy monitor interrupt enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_EXCEPTION_MONITOR_RLS</name>
+              <description>DBUS busy monitor interrupt enbale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_INTERRUPT_CLR</name>
+          <description>Core1 monitor interrupt clr register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_RD_CLR</name>
+              <description>Core1 dram0 area0 read monitor interrupt clr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_WR_CLR</name>
+              <description>Core1 dram0 area0 write monitor interrupt clr</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_RD_CLR</name>
+              <description>Core1 dram0 area1 read monitor interrupt clr</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_WR_CLR</name>
+              <description>Core1 dram0 area1 write monitor interrupt clr</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_0_RD_CLR</name>
+              <description>Core1 PIF area0 read monitor interrupt clr</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_0_WR_CLR</name>
+              <description>Core1 PIF area0 write monitor interrupt clr</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_1_RD_CLR</name>
+              <description>Core1 PIF area1 read monitor interrupt clr</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_AREA_PIF_1_WR_CLR</name>
+              <description>Core1 PIF area1 write monitor interrupt clr</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_SP_SPILL_MIN_CLR</name>
+              <description>Core1 stackpoint overflow monitor interrupt clr</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_SP_SPILL_MAX_CLR</name>
+              <description>Core1 stackpoint underflow monitor interrupt clr</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>IBUS busy monitor interrupt clr</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_EXCEPTION_MONITOR_CLR</name>
+              <description>DBUS busy monitor interrupt clr</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_DRAM0_0_MIN</name>
+          <description>Core1 dram0 region0 addr configuration register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_MIN</name>
+              <description>Core1 dram0 region0 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_DRAM0_0_MAX</name>
+          <description>Core1 dram0 region0 addr configuration register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_DRAM0_0_MAX</name>
+              <description>Core1 dram0 region0 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_DRAM0_1_MIN</name>
+          <description>Core1 dram0 region1 addr configuration register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_MIN</name>
+              <description>Core1 dram0 region1 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_DRAM0_1_MAX</name>
+          <description>Core1 dram0 region1 addr configuration register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_DRAM0_1_MAX</name>
+              <description>Core1 dram0 region1 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_PIF_0_MIN</name>
+          <description>Core1 PIF region0 addr configuration register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_PIF_0_MIN</name>
+              <description>Core1 PIF region0 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_PIF_0_MAX</name>
+          <description>Core1 PIF region0 addr configuration register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_PIF_0_MAX</name>
+              <description>Core1 PIF region0 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_PIF_1_MIN</name>
+          <description>Core1 PIF region1 addr configuration register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_PIF_1_MIN</name>
+              <description>Core1 PIF region1 start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_PIF_1_MAX</name>
+          <description>Core1 PIF region1 addr configuration register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_PIF_1_MAX</name>
+              <description>Core1 PIF region1 end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_PC</name>
+          <description>Core1 area sp status register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_PC</name>
+              <description>the stackpointer when first touch region monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_AREA_SP</name>
+          <description>Core1 area pc status register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_AREA_SP</name>
+              <description>the PC when first touch region monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_SP_UNSTABLE</name>
+          <description>Core1 sp unstable configuration register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_SP_UNSTABLE</name>
+              <description>unstable period when window change,during this period no check stackpointer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_SP_MIN</name>
+          <description>Core1 sp region configuration regsiter</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_SP_MIN</name>
+              <description>stack min value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_SP_MAX</name>
+          <description>Core1 sp region configuration regsiter</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_SP_MAX</name>
+              <description>stack max value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_SP_PC</name>
+          <description>Core1 sp pc status register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_SP_PC</name>
+              <description>the PC when first touch stack monitor interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_PDEBUGENABLE</name>
+          <description>Core1 pdebug configuration register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_PDEBUGENABLE</name>
+              <description>Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_RECORDING</name>
+          <description>Core1 pdebug status register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_RECORDING</name>
+              <description>Pdebug record enable,set 1 to record Core1 pdebug interface signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_PDEBUGINST</name>
+          <description>Core1 pdebug status register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_PDEBUGINST</name>
+              <description>Core1 pdebuginst</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_PDEBUGSTATUS</name>
+          <description>Core1 pdebug status register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_PDEBUGSTATUS</name>
+              <description>Core1 pdebugstatus</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_PDEBUGDATA</name>
+          <description>Core1 pdebug status register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_PDEBUGDATA</name>
+              <description>Core1_pdebugdata</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_PDEBUGPC</name>
+          <description>Core1 pdebug status register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_PDEBUGPC</name>
+              <description>Core1_pdebugPC</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_PDEBUGLS0STAT</name>
+          <description>Core1 pdebug status register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_PDEBUGLS0STAT</name>
+              <description>Core1_pdebug_s0stat</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_PDEBUGLS0ADDR</name>
+          <description>Core1 pdebug status register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_PDEBUGLS0ADDR</name>
+              <description>Core1_pdebug_s0addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_PDEBUGLS0DATA</name>
+          <description>Core1 pdebug status register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_PDEBUGLS0DATA</name>
+              <description>Core1_pdebug_s0data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_RCD_SP</name>
+          <description>Core1 pdebug status register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_RCD_SP</name>
+              <description>Core1_stack pointer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_IRAM0_EXCEPTION_MONITOR_0</name>
+          <description>Core1 bus busy status regsiter</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_IRAM0_RECORDING_ADDR_0</name>
+              <description>The first iram0's addr[25:2] status when trigger IRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_RECORDING_WR_0</name>
+              <description>The first iram0's wr status when trigger IRAM busy interrupt</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_RECORDING_LOADSTORE_0</name>
+              <description>The first iram0's loadstore status when trigger IRAM busy interrupt</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_IRAM0_EXCEPTION_MONITOR_1</name>
+          <description>Core1 bus busy status regsiter</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_IRAM0_RECORDING_ADDR_1</name>
+              <description>The second iram0's addr[25:2] status when trigger IRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_RECORDING_WR_1</name>
+              <description>The second iram0's wr status when trigger IRAM busy interrupt</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_RECORDING_LOADSTORE_1</name>
+              <description>The second iram0's loadstore status when trigger IRAM busy interrupt</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_EXCEPTION_MONITOR_0</name>
+          <description>Core1 bus busy status regsiter</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_RECORDING_ADDR_0</name>
+              <description>The first dram0's addr[25:4] status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_RECORDING_WR_0</name>
+              <description>The first dram0's wr status when trigger DRAM busy interrupt</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_EXCEPTION_MONITOR_1</name>
+          <description>Core1 bus busy status regsiter</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_RECORDING_BYTEEN_0</name>
+              <description>The first dram0's byteen status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_EXCEPTION_MONITOR_2</name>
+          <description>Core1 bus busy status regsiter</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_RECORDING_PC_0</name>
+              <description>The first dram0's PC status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_EXCEPTION_MONITOR_3</name>
+          <description>Core1 bus busy status regsiter</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_RECORDING_ADDR_1</name>
+              <description>The second dram0's addr[25:4] status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_RECORDING_WR_1</name>
+              <description>The second dram0's wr status when trigger DRAM busy interrupt</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_EXCEPTION_MONITOR_4</name>
+          <description>Core1 bus busy status regsiter</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_RECORDING_BYTEEN_1</name>
+              <description>The second dram0's byteen status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_EXCEPTION_MONITOR_5</name>
+          <description>Core1 bus busy status regsiter</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_RECORDING_PC_1</name>
+              <description>The second dram0's PC status when trigger DRAM busy interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0</name>
+          <description>bus busy configuration register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0</name>
+              <description>busy monitor window cycle</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1</name>
+          <description>bus busy configuration register</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1</name>
+              <description>non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_SETTING</name>
+          <description>log set register</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000040</resetValue>
+          <fields>
+            <field>
+              <name>LOG_ENA</name>
+              <description>bus moniter enable: [0]Core1,[1]core1,[2]dma</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOG_MODE</name>
+              <description>check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOG_MEM_LOOP_ENABLE</name>
+              <description>mem_loop enable,1 means that loop write</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_DATA_0</name>
+          <description>log check data register</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_DATA_0</name>
+              <description>check data0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_DATA_1</name>
+          <description>log check data register</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_DATA_1</name>
+              <description>check data1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_DATA_2</name>
+          <description>log check data register</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_DATA_2</name>
+              <description>check data2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_DATA_3</name>
+          <description>log check data register</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_DATA_3</name>
+              <description>check data3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_DATA_MASK</name>
+          <description>log check data mask register</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_DATA_SIZE</name>
+              <description>data mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MIN</name>
+          <description>log check region configuration register</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MIN</name>
+              <description>check region min addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MAX</name>
+          <description>log check region configuration register</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MAX</name>
+              <description>check region max addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_START</name>
+          <description>log mem region configuration register</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_START</name>
+              <description>mem start addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_END</name>
+          <description>log mem region configuration register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_END</name>
+              <description>mem end addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_WRITING_ADDR</name>
+          <description>log mem addr status register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_WRITING_ADDR</name>
+              <description>mem current addr, it means next writing addr</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOG_MEM_FULL_FLAG</name>
+          <description>log mem status register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOG_MEM_FULL_FLAG</name>
+              <description>when it's 1,show that mem write loop morte than one time.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02003040</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DMA</name>
+      <description>DMA (Direct Memory Access) Controller</description>
+      <groupName>DMA</groupName>
+      <baseAddress>0x6003F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x320</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>DMA_IN_CH0</name>
+        <value>66</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_IN_CH1</name>
+        <value>67</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_IN_CH2</name>
+        <value>68</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_IN_CH3</name>
+        <value>69</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_IN_CH4</name>
+        <value>70</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_OUT_CH0</name>
+        <value>71</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_OUT_CH1</name>
+        <value>72</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_OUT_CH2</name>
+        <value>73</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_OUT_CH3</name>
+        <value>74</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_OUT_CH4</name>
+        <value>75</value>
+      </interrupt>
+      <interrupt>
+        <name>APB_PMS_MONITOR_VIOLATE</name>
+        <value>84</value>
+      </interrupt>
+      <interrupt>
+        <name>DMA_EXTMEM_REJECT</name>
+        <value>98</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_CONF0_CH%s</name>
+          <description>Configure 0 register of Rx channel 0</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_RST</name>
+              <description>This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TRANS_EN</name>
+              <description>Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_CONF1_CH%s</name>
+          <description>Configure 1 register of Rx channel 0</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000C</resetValue>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_THRS</name>
+              <description>This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_EXT_MEM_BK_SIZE</name>
+              <description>Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes      1: 32 bytes    2/3:reserved</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_INT_RAW_CH%s</name>
+          <description>Raw status interrupt of Rx channel 0</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_FULL_WM</name>
+              <description>The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_L1</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_L1</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_L3</name>
+              <description>This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_L3</name>
+              <description>This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_INT_ST_CH%s</name>
+          <description>Masked interrupt of Rx channel 0</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The raw interrupt status bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_FULL_WM</name>
+              <description>The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_L1</name>
+              <description>The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_L1</name>
+              <description>The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_L3</name>
+              <description>The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_L3</name>
+              <description>The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_INT_ENA_CH%s</name>
+          <description>Interrupt enable bits of Rx channel 0</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>The interrupt enable bit for the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_FULL_WM</name>
+              <description>The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_L1</name>
+              <description>The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_L1</name>
+              <description>The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_L3</name>
+              <description>The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_L3</name>
+              <description>The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_INT_CLR_CH%s</name>
+          <description>Interrupt clear bits of Rx channel 0</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_DONE</name>
+              <description>Set this bit to clear the IN_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_SUC_EOF</name>
+              <description>Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_ERR_EOF</name>
+              <description>Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_ERR</name>
+              <description>Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_EMPTY</name>
+              <description>Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL_WM</name>
+              <description>Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_L1</name>
+              <description>Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_L1</name>
+              <description>Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_OVF_L3</name>
+              <description>Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>INFIFO_UDF_L3</name>
+              <description>Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>INFIFO_STATUS_CH%s</name>
+          <description>Receive FIFO status of Rx channel 0</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0F00003A</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_FULL_L1</name>
+              <description>L1 Rx FIFO full signal for Rx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_EMPTY_L1</name>
+              <description>L1 Rx FIFO empty signal for Rx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_FULL_L2</name>
+              <description>L2 Rx FIFO full signal for Rx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_EMPTY_L2</name>
+              <description>L2 Rx FIFO empty signal for Rx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_FULL_L3</name>
+              <description>L3 Rx FIFO full signal for Rx channel 0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_EMPTY_L3</name>
+              <description>L3 Rx FIFO empty signal for Rx channel 0.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT_L1</name>
+              <description>The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT_L2</name>
+              <description>The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_CNT_L3</name>
+              <description>The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_1B_L3</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_2B_L3</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_3B_L3</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_REMAIN_UNDER_4B_L3</name>
+              <description>reserved</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_BUF_HUNGRY</name>
+              <description>reserved</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_POP_CH%s</name>
+          <description>Pop control register of Rx channel 0</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>INFIFO_RDATA</name>
+              <description>This register stores the data popping from DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INFIFO_POP</name>
+              <description>Set this bit to pop data from DMA FIFO.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_LINK_CH%s</name>
+          <description>Link descriptor configure and control register of Rx channel 0</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01100000</resetValue>
+          <fields>
+            <field>
+              <name>INLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_AUTO_RET</name>
+              <description>Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_STOP</name>
+              <description>Set this bit to stop dealing with the inlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_START</name>
+              <description>Set this bit to start dealing with the inlink descriptors.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_RESTART</name>
+              <description>Set this bit to mount a new inlink descriptor.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INLINK_PARK</name>
+              <description>1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_STATE_CH%s</name>
+          <description>Receive status of Rx channel 0</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_ADDR</name>
+              <description>This register stores the current inlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_SUC_EOF_DES_ADDR_CH%s</name>
+          <description>Inlink descriptor address when EOF occurs of Rx channel 0</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SUC_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_ERR_EOF_DES_ADDR_CH%s</name>
+          <description>Inlink descriptor address when errors occur of Rx channel 0</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_ERR_EOF_DES_ADDR</name>
+              <description>This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_DSCR_CH%s</name>
+          <description>Current inlink descriptor address of Rx channel 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR</name>
+              <description>The address of the current inlink descriptor x.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_DSCR_BF0_CH%s</name>
+          <description>The last inlink descriptor address of Rx channel 0</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF0</name>
+              <description>The address of the last inlink descriptor x-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_DSCR_BF1_CH%s</name>
+          <description>The second-to-last inlink descriptor address of Rx channel 0</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_WIGHT_CH%s</name>
+          <description>Weight register of Rx channel 0</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000F00</resetValue>
+          <fields>
+            <field>
+              <name>RX_WEIGHT</name>
+              <description>The weight of Rx channel 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_PRI_CH%s</name>
+          <description>Priority register of Rx channel 0</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_PRI</name>
+              <description>The priority of Rx channel 0. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>IN_PERI_SEL_CH%s</name>
+          <description>Peripheral selection of Rx channel 0</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_IN_SEL</name>
+              <description>This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_CONF0_CH%s</name>
+          <description>Configure 0 register of Tx channel 0</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>OUT_RST</name>
+              <description>This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_LOOP_TEST</name>
+              <description>reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_AUTO_WRBACK</name>
+              <description>Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF_MODE</name>
+              <description>EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTDSCR_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DATA_BURST_EN</name>
+              <description>Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_CONF1_CH%s</name>
+          <description>Configure 1 register of Tx channel 0</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_CHECK_OWNER</name>
+              <description>Set this bit to enable checking the owner attribute of the link descriptor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EXT_MEM_BK_SIZE</name>
+              <description>Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes      1: 32 bytes    2/3:reserved</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_INT_RAW_CH%s</name>
+          <description>Raw status interrupt of Tx channel 0</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_L1</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_L1</name>
+              <description>This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_L3</name>
+              <description>This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_L3</name>
+              <description>This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_INT_ST_CH%s</name>
+          <description>Masked interrupt of Tx channel 0</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_L1</name>
+              <description>The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_L1</name>
+              <description>The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_L3</name>
+              <description>The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_L3</name>
+              <description>The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_INT_ENA_CH%s</name>
+          <description>Interrupt enable bits of Tx channel 0</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE</name>
+              <description>The interrupt enable bit for the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>The interrupt enable bit for the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_L1</name>
+              <description>The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_L1</name>
+              <description>The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_L3</name>
+              <description>The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_L3</name>
+              <description>The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_INT_CLR_CH%s</name>
+          <description>Interrupt clear bits of Tx channel 0</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_DONE</name>
+              <description>Set this bit to clear the OUT_DONE_CH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF</name>
+              <description>Set this bit to clear the OUT_EOF_CH_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_ERR</name>
+              <description>Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_TOTAL_EOF</name>
+              <description>Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_L1</name>
+              <description>Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_L1</name>
+              <description>Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_OVF_L3</name>
+              <description>Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_UDF_L3</name>
+              <description>Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUTFIFO_STATUS_CH%s</name>
+          <description>Transmit FIFO status of Tx channel 0</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0780002A</resetValue>
+          <fields>
+            <field>
+              <name>OUTFIFO_FULL_L1</name>
+              <description>L1 Tx FIFO full signal for Tx channel 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY_L1</name>
+              <description>L1 Tx FIFO empty signal for Tx channel 0.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_FULL_L2</name>
+              <description>L2 Tx FIFO full signal for Tx channel 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY_L2</name>
+              <description>L2 Tx FIFO empty signal for Tx channel 0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_FULL_L3</name>
+              <description>L3 Tx FIFO full signal for Tx channel 0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_EMPTY_L3</name>
+              <description>L3 Tx FIFO empty signal for Tx channel 0.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT_L1</name>
+              <description>The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT_L2</name>
+              <description>The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTFIFO_CNT_L3</name>
+              <description>The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_1B_L3</name>
+              <description>reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_2B_L3</name>
+              <description>reserved</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_3B_L3</name>
+              <description>reserved</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_REMAIN_UNDER_4B_L3</name>
+              <description>reserved</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_PUSH_CH%s</name>
+          <description>Push control register of Rx channel 0</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTFIFO_WDATA</name>
+              <description>This register stores the data that need to be pushed into DMA FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTFIFO_PUSH</name>
+              <description>Set this bit to push data into DMA FIFO.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_LINK_CH%s</name>
+          <description>Link descriptor configure and control register of Tx channel 0</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>OUTLINK_ADDR</name>
+              <description>This register stores the 20 least significant bits of the first outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_STOP</name>
+              <description>Set this bit to stop dealing with the outlink descriptors.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_START</name>
+              <description>Set this bit to start dealing with the outlink descriptors.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_RESTART</name>
+              <description>Set this bit to restart a new outlink from the last address.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_PARK</name>
+              <description>1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_STATE_CH%s</name>
+          <description>Transmit status of Tx channel 0</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_ADDR</name>
+              <description>This register stores the current outlink descriptor's address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_DSCR_STATE</name>
+              <description>reserved</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_STATE</name>
+              <description>reserved</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_EOF_DES_ADDR_CH%s</name>
+          <description>Outlink descriptor address when EOF occurs of Tx channel 0</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_EOF_BFR_DES_ADDR_CH%s</name>
+          <description>The last outlink descriptor address when EOF occurs of Tx channel 0</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EOF_BFR_DES_ADDR</name>
+              <description>This register stores the address of the outlink descriptor before the last outlink descriptor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_DSCR_CH%s</name>
+          <description>Current inlink descriptor address of Tx channel 0</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR</name>
+              <description>The address of the current outlink descriptor y.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_DSCR_BF0_CH%s</name>
+          <description>The last inlink descriptor address of Tx channel 0</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF0</name>
+              <description>The address of the last outlink descriptor y-1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_DSCR_BF1_CH%s</name>
+          <description>The second-to-last inlink descriptor address of Tx channel 0</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUTLINK_DSCR_BF1</name>
+              <description>The address of the second-to-last inlink descriptor x-2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_WIGHT_CH%s</name>
+          <description>Weight register of Rx channel 0</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000F00</resetValue>
+          <fields>
+            <field>
+              <name>TX_WEIGHT</name>
+              <description>The weight of Tx channel 0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_PRI_CH%s</name>
+          <description>Priority register of Tx channel 0.</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_PRI</name>
+              <description>The priority of Tx channel 0. The larger of the value, the higher of the priority.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0xC0</dimIncrement>
+          <name>OUT_PERI_SEL_CH%s</name>
+          <description>Peripheral selection of Tx channel 0</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>PERI_OUT_SEL</name>
+              <description>This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AHB_TEST</name>
+          <description>reserved</description>
+          <addressOffset>0x3C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHB_TESTMODE</name>
+              <description>reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_TESTADDR</name>
+              <description>reserved</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PD_CONF</name>
+          <description>reserved</description>
+          <addressOffset>0x3C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>DMA_RAM_FORCE_PD</name>
+              <description>Set this bit to force power down DMA internal memory.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RAM_FORCE_PU</name>
+              <description>Set this bit to force power up DMA internal memory</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RAM_CLK_FO</name>
+              <description>1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC_CONF</name>
+          <description>MISC register</description>
+          <addressOffset>0x3C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>AHBM_RST_INTER</name>
+              <description>Set this bit, then clear this bit to reset the internal ahb FSM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBM_RST_EXTER</name>
+              <description>Set this bit, then clear this bit to reset the external ahb FSM.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_PRI_DIS</name>
+              <description>Set this bit to disable priority arbitration function.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>IN_SRAM_SIZE_CH%s</name>
+          <description>Receive L2 FIFO depth of Rx channel 0</description>
+          <addressOffset>0x3CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000E</resetValue>
+          <fields>
+            <field>
+              <name>IN_SIZE</name>
+              <description>This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>5</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>OUT_SRAM_SIZE_CH%s</name>
+          <description>Transmit L2 FIFO depth of Tx channel 0</description>
+          <addressOffset>0x3D0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000E</resetValue>
+          <fields>
+            <field>
+              <name>OUT_SIZE</name>
+              <description>This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTMEM_REJECT_ADDR</name>
+          <description>Reject address accessing external RAM</description>
+          <addressOffset>0x3F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXTMEM_REJECT_ADDR</name>
+              <description>This register store the first address rejected by permission control when accessing external RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTMEM_REJECT_ST</name>
+          <description>Reject status accessing external RAM</description>
+          <addressOffset>0x3F8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXTMEM_REJECT_ATRR</name>
+              <description>The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EXTMEM_REJECT_CHANNEL_NUM</name>
+              <description>The register indicate the reject accessing from which channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EXTMEM_REJECT_PERI_NUM</name>
+              <description>This register indicate reject accessing from which peripheral.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTMEM_REJECT_INT_RAW</name>
+          <description>Raw interrupt status of external RAM permission</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXTMEM_REJECT_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTMEM_REJECT_INT_ST</name>
+          <description>Masked interrupt status of external RAM permission</description>
+          <addressOffset>0x400</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXTMEM_REJECT_INT_ST</name>
+              <description>The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTMEM_REJECT_INT_ENA</name>
+          <description>Interrupt enable bits of external RAM permission</description>
+          <addressOffset>0x404</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXTMEM_REJECT_INT_ENA</name>
+              <description>The interrupt enable bit for the EXTMEM_REJECT_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTMEM_REJECT_INT_CLR</name>
+          <description>Interrupt clear bits of external RAM permission</description>
+          <addressOffset>0x408</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXTMEM_REJECT_INT_CLR</name>
+              <description>Set this bit to clear the EXTMEM_REJECT_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x40C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101180</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>DS</name>
+      <description>Digital Signature</description>
+      <groupName>DS</groupName>
+      <baseAddress>0x6003D000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA5C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>1584</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>C_MEM[%s]</name>
+          <description>Memory C</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>IV_%s</name>
+          <description>IV block data</description>
+          <addressOffset>0x630</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IV_0</name>
+              <description>Stores IV block data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>X_MEM[%s]</name>
+          <description>Memory X</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Z_MEM[%s]</name>
+          <description>Memory Z</description>
+          <addressOffset>0xA00</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>SET_START</name>
+          <description>Activates the DS peripheral</description>
+          <addressOffset>0xE00</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>Write 1 to this register to active the DS peripheral</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_ME</name>
+          <description>Starts DS operation</description>
+          <addressOffset>0xE04</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_ME</name>
+              <description>Write 1 to this register to start DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_FINISH</name>
+          <description>Ends DS operation</description>
+          <addressOffset>0xE08</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_FINISH</name>
+              <description>Write 1 to this register to end DS operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>Status of the DS perihperal</description>
+          <addressOffset>0xE0C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_BUSY</name>
+              <description>Stores the status of the DS peripheral. 1: The DS peripheral is busy. 0: The DS peripheral is idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_KEY_WRONG</name>
+          <description>Checks the reason why DS_KEY is not ready</description>
+          <addressOffset>0xE10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUERY_KEY_WRONG</name>
+              <description>1-15: HMAC was activated, but the DS peripheral did not successfully receive the DS_KEY from the HMAC peripheral. (The biggest value is 15). 0: HMAC is not activated.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_CHECK</name>
+          <description>Queries DS check result</description>
+          <addressOffset>0xE14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MD_ERROR</name>
+              <description>MD checkout result. 1: The MD check fails. 0: The MD check passes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PADDING_BAD</name>
+              <description>padding checkout result. 1: The padding check fails. 0: The padding check passes.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>DS version control register</description>
+          <addressOffset>0xE20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20191217</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>ds version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EFUSE</name>
+      <description>eFuse Controller</description>
+      <groupName>EFUSE</groupName>
+      <baseAddress>0x60007000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1CC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>EFUSE</name>
+        <value>36</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PGM_DATA0</name>
+          <description>Register 0 that stores data to be programmed.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_0</name>
+              <description>The content of the 0th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA1</name>
+          <description>Register 1 that stores data to be programmed.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_1</name>
+              <description>The content of the 1st 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA2</name>
+          <description>Register 2 that stores data to be programmed.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_2</name>
+              <description>The content of the 2nd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA3</name>
+          <description>Register 3 that stores data to be programmed.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_3</name>
+              <description>The content of the 3rd 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA4</name>
+          <description>Register 4 that stores data to be programmed.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_4</name>
+              <description>The content of the 4th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA5</name>
+          <description>Register 5 that stores data to be programmed.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_5</name>
+              <description>The content of the 5th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA6</name>
+          <description>Register 6 that stores data to be programmed.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_6</name>
+              <description>The content of the 6th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_DATA7</name>
+          <description>Register 7 that stores data to be programmed.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_DATA_7</name>
+              <description>The content of the 7th 32-bit data to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE0</name>
+          <description>Register 0 that stores the RS code to be programmed.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_0</name>
+              <description>The content of the 0th 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE1</name>
+          <description>Register 1 that stores the RS code to be programmed.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_1</name>
+              <description>The content of the 1st 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PGM_CHECK_VALUE2</name>
+          <description>Register 2 that stores the RS code to be programmed.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PGM_RS_DATA_2</name>
+              <description>The content of the 2nd 32-bit RS code to be programmed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_WR_DIS</name>
+          <description>BLOCK0 data register 0.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_DIS</name>
+              <description>Disable programming of individual eFuses.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA0</name>
+          <description>BLOCK0 data register 1.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS</name>
+              <description>Set this bit to disable reading from BlOCK4-10.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_RTC_RAM_BOOT</name>
+              <description>Set this bit to disable boot from RTC RAM.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE</name>
+              <description>Set this bit to disable Icache.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DCACHE</name>
+              <description>Set this bit to disable Dcache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE</name>
+              <description>Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_DCACHE</name>
+              <description>Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7).</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD</name>
+              <description>Set this bit to disable the function that forces chip into download mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB</name>
+              <description>Set this bit to disable USB function.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_CAN</name>
+              <description>Set this bit to disable CAN function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_APP_CPU</name>
+              <description>Disable app cpu.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG</name>
+              <description>Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG</name>
+              <description>Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>Set this bit to disable flash encryption when in download boot modes.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH</name>
+              <description>Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL</name>
+              <description>Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS</name>
+              <description>Set this bit to exchange USB D+ and D- pins.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EXT_PHY_ENABLE</name>
+              <description>Set this bit to enable external PHY.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTLC_GPIO_ENABLE</name>
+              <description>Bluetooth GPIO signal output security level control.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_MODECURLIM</name>
+              <description>SPI regulator switches current limit mode.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DREFH</name>
+              <description>SPI regulator high voltage reference.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA1</name>
+          <description>BLOCK0 data register 2.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>VDD_SPI_DREFM</name>
+              <description>SPI regulator medium voltage reference.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DREFL</name>
+              <description>SPI regulator low voltage reference.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_XPD</name>
+              <description>SPI regulator power up signal.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_TIEH</name>
+              <description>SPI regulator output is short connected to VDD3P3_RTC_IO.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_FORCE</name>
+              <description>Set this bit and force to use the configuration of eFuse to configure VDD_SPI.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_EN_INIT</name>
+              <description>Set SPI regulator to 0 to configure init[1:0]=0.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_ENCURLIM</name>
+              <description>Set SPI regulator to 1 to enable output current limit.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DCURLIM</name>
+              <description>Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_INIT</name>
+              <description>Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DCAP</name>
+              <description>Prevents SPI regulator from overshoot.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL</name>
+              <description>Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT</name>
+              <description>Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0</name>
+              <description>Set this bit to enable revoking first secure boot key.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1</name>
+              <description>Set this bit to enable revoking second secure boot key.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2</name>
+              <description>Set this bit to enable revoking third secure boot key.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0</name>
+              <description>Purpose of Key0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1</name>
+              <description>Purpose of Key1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA2</name>
+          <description>BLOCK0 data register 3.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2</name>
+              <description>Purpose of Key2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3</name>
+              <description>Purpose of Key3.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4</name>
+              <description>Purpose of Key4.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5</name>
+              <description>Purpose of Key5.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN</name>
+              <description>Set this bit to enable secure boot.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE</name>
+              <description>Set this bit to enable revoking aggressive secure boot.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_JTAG</name>
+              <description>Set this bit to disable function of usb switch to jtag in module of usb device.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DEVICE</name>
+              <description>Set this bit to disable usb device.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STRAP_JTAG_SEL</name>
+              <description>Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_PHY_SEL</name>
+              <description>This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_DSENSE</name>
+              <description>Sample delay configuration of power glitch.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW</name>
+              <description>Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value.  Otherwise, the waiting time is twice the configurable value.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA3</name>
+          <description>BLOCK0 data register 4.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE</name>
+              <description>Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_LEGACY_SPI_BOOT</name>
+              <description>Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CHANNEL</name>
+              <description>Selectes the default UART print channel. 0: UART0. 1: UART1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_ECC_MODE</name>
+              <description>Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DOWNLOAD_MODE</name>
+              <description>Set this bit to disable UART download mode through USB.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD</name>
+              <description>Set this bit to enable secure UART download mode.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL</name>
+              <description>Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIN_POWER_SELECTION</name>
+              <description>GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TYPE</name>
+              <description>Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_PAGE_SIZE</name>
+              <description>Set Flash page size.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_ECC_EN</name>
+              <description>Set 1 to enable ECC for flash boot.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME</name>
+              <description>Set this bit to force ROM code to send a resume command during SPI boot.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION</name>
+              <description>Secure version (used by ESP-IDF anti-rollback feature).</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWERGLITCH_EN</name>
+              <description>Set this bit to enable power glitch function.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED1</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_DATA4</name>
+          <description>BLOCK0 data register 5.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED2</name>
+              <description>Reserved (used for four backups method).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_0</name>
+          <description>BLOCK1 data register 0.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_0</name>
+              <description>Stores the low 32 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_1</name>
+          <description>BLOCK1 data register 1.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_1</name>
+              <description>Stores the high 16 bits of MAC address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_PAD_CONF_0</name>
+              <description>Stores the zeroth part of SPI_PAD_CONF.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_2</name>
+          <description>BLOCK1 data register 2.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_PAD_CONF_1</name>
+              <description>Stores the first part of SPI_PAD_CONF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_3</name>
+          <description>BLOCK1 data register 3.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_PAD_CONF_2</name>
+              <description>Stores the second part of SPI_PAD_CONF.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_DATA_PART0_0</name>
+              <description>Stores the fist 14 bits of the zeroth part of system data.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_4</name>
+          <description>BLOCK1 data register 4.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_1</name>
+              <description>Stores the fist 32 bits of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_MAC_SPI_SYS_5</name>
+          <description>BLOCK1 data register 5.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART0_2</name>
+              <description>Stores the second 32 bits of the zeroth part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA0</name>
+          <description>Register 0 of BLOCK2 (system).</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_0</name>
+              <description>Stores the zeroth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA1</name>
+          <description>Register 1 of BLOCK2 (system).</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_1</name>
+              <description>Stores the first 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA2</name>
+          <description>Register 2 of BLOCK2 (system).</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_2</name>
+              <description>Stores the second 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA3</name>
+          <description>Register 3 of BLOCK2 (system).</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_3</name>
+              <description>Stores the third 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA4</name>
+          <description>Register 4 of BLOCK2 (system).</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_4</name>
+              <description>Stores the fourth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA5</name>
+          <description>Register 5 of BLOCK2 (system).</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_5</name>
+              <description>Stores the fifth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA6</name>
+          <description>Register 6 of BLOCK2 (system).</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_6</name>
+              <description>Stores the sixth 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART1_DATA7</name>
+          <description>Register 7 of BLOCK2 (system).</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART1_7</name>
+              <description>Stores the seventh 32 bits of the first part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA0</name>
+          <description>Register 0 of BLOCK3 (user).</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA0</name>
+              <description>Stores the zeroth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA1</name>
+          <description>Register 1 of BLOCK3 (user).</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA1</name>
+              <description>Stores the first 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA2</name>
+          <description>Register 2 of BLOCK3 (user).</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA2</name>
+              <description>Stores the second 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA3</name>
+          <description>Register 3 of BLOCK3 (user).</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA3</name>
+              <description>Stores the third 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA4</name>
+          <description>Register 4 of BLOCK3 (user).</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA4</name>
+              <description>Stores the fourth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA5</name>
+          <description>Register 5 of BLOCK3 (user).</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA5</name>
+              <description>Stores the fifth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA6</name>
+          <description>Register 6 of BLOCK3 (user).</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA6</name>
+              <description>Stores the sixth 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_USR_DATA7</name>
+          <description>Register 7 of BLOCK3 (user).</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_DATA7</name>
+              <description>Stores the seventh 32 bits of BLOCK3 (user).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA0</name>
+          <description>Register 0 of BLOCK4 (KEY0).</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA1</name>
+          <description>Register 1 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA1</name>
+              <description>Stores the first 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA2</name>
+          <description>Register 2 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA2</name>
+              <description>Stores the second 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA3</name>
+          <description>Register 3 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA3</name>
+              <description>Stores the third 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA4</name>
+          <description>Register 4 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA5</name>
+          <description>Register 5 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA6</name>
+          <description>Register 6 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY0_DATA7</name>
+          <description>Register 7 of BLOCK4 (KEY0).</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY0_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA0</name>
+          <description>Register 0 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA1</name>
+          <description>Register 1 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA1</name>
+              <description>Stores the first 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA2</name>
+          <description>Register 2 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA2</name>
+              <description>Stores the second 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA3</name>
+          <description>Register 3 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA3</name>
+              <description>Stores the third 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA4</name>
+          <description>Register 4 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA5</name>
+          <description>Register 5 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA6</name>
+          <description>Register 6 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY1_DATA7</name>
+          <description>Register 7 of BLOCK5 (KEY1).</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY1_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA0</name>
+          <description>Register 0 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA1</name>
+          <description>Register 1 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA1</name>
+              <description>Stores the first 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA2</name>
+          <description>Register 2 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA2</name>
+              <description>Stores the second 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA3</name>
+          <description>Register 3 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA3</name>
+              <description>Stores the third 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA4</name>
+          <description>Register 4 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA5</name>
+          <description>Register 5 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA6</name>
+          <description>Register 6 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY2_DATA7</name>
+          <description>Register 7 of BLOCK6 (KEY2).</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY2_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA0</name>
+          <description>Register 0 of BLOCK7 (KEY3).</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA1</name>
+          <description>Register 1 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA1</name>
+              <description>Stores the first 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA2</name>
+          <description>Register 2 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA2</name>
+              <description>Stores the second 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA3</name>
+          <description>Register 3 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA3</name>
+              <description>Stores the third 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA4</name>
+          <description>Register 4 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA5</name>
+          <description>Register 5 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA6</name>
+          <description>Register 6 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY3_DATA7</name>
+          <description>Register 7 of BLOCK7 (KEY3).</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY3_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA0</name>
+          <description>Register 0 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA1</name>
+          <description>Register 1 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA1</name>
+              <description>Stores the first 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA2</name>
+          <description>Register 2 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA2</name>
+              <description>Stores the second 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA3</name>
+          <description>Register 3 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA3</name>
+              <description>Stores the third 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA4</name>
+          <description>Register 4 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA5</name>
+          <description>Register 5 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA6</name>
+          <description>Register 6 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY4_DATA7</name>
+          <description>Register 7 of BLOCK8 (KEY4).</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY4_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY4.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA0</name>
+          <description>Register 0 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA0</name>
+              <description>Stores the zeroth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA1</name>
+          <description>Register 1 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA1</name>
+              <description>Stores the first 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA2</name>
+          <description>Register 2 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA2</name>
+              <description>Stores the second 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA3</name>
+          <description>Register 3 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA3</name>
+              <description>Stores the third 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA4</name>
+          <description>Register 4 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA4</name>
+              <description>Stores the fourth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA5</name>
+          <description>Register 5 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA5</name>
+              <description>Stores the fifth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA6</name>
+          <description>Register 6 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA6</name>
+              <description>Stores the sixth 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_KEY5_DATA7</name>
+          <description>Register 7 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_DATA7</name>
+              <description>Stores the seventh 32 bits of KEY5.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA0</name>
+          <description>Register 0 of BLOCK10 (system).</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_0</name>
+              <description>Stores the 0th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA1</name>
+          <description>Register 1 of BLOCK9 (KEY5).</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_1</name>
+              <description>Stores the 1st 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA2</name>
+          <description>Register 2 of BLOCK10 (system).</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_2</name>
+              <description>Stores the 2nd 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA3</name>
+          <description>Register 3 of BLOCK10 (system).</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_3</name>
+              <description>Stores the 3rd 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA4</name>
+          <description>Register 4 of BLOCK10 (system).</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_4</name>
+              <description>Stores the 4th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA5</name>
+          <description>Register 5 of BLOCK10 (system).</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_5</name>
+              <description>Stores the 5th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA6</name>
+          <description>Register 6 of BLOCK10 (system).</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_6</name>
+              <description>Stores the 6th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_SYS_PART2_DATA7</name>
+          <description>Register 7 of BLOCK10 (system).</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYS_DATA_PART2_7</name>
+              <description>Stores the 7th 32 bits of the 2nd part of system data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR0</name>
+          <description>Programming error record register 0 of BLOCK0.</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RD_DIS_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_RTC_RAM_BOOT_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_ICACHE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DCACHE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_ICACHE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_DCACHE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_FORCE_DOWNLOAD_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_CAN_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_APP_CPU_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFT_DIS_JTAG_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_PAD_JTAG_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFH_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_DREFL_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_EXCHG_PINS_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EXT_PHY_ENABLE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BTLC_GPIO_ENABLE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_MODECURLIM_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DREFH_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR1</name>
+          <description>Programming error record register 1 of BLOCK0.</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>VDD_SPI_DREFM_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DREFL_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_XPD_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_TIEH_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_FORCE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_EN_INIT_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_ENCURLIM_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DCURLIM_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_INIT_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VDD_SPI_DCAP_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_DELAY_SEL_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SPI_BOOT_CRYPT_CNT_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE0_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE1_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_KEY_REVOKE2_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_0_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_1_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR2</name>
+          <description>Programming error record register 2 of BLOCK0.</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_PURPOSE_2_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_3_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_4_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY_PURPOSE_5_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED0_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_EN_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_BOOT_AGGRESSIVE_REVOKE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_JTAG_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DEVICE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STRAP_JTAG_SEL_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_PHY_SEL_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_DSENSE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TPUW_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR3</name>
+          <description>Programming error record register 3 of BLOCK0.</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_DOWNLOAD_MODE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_LEGACY_SPI_BOOT_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CHANNEL_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_ECC_MODE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIS_USB_DOWNLOAD_MODE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENABLE_SECURITY_DOWNLOAD_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>UART_PRINT_CONTROL_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PIN_POWER_SELECTION_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_TYPE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_PAGE_SIZE_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FLASH_ECC_EN_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FORCE_SEND_RESUME_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SECURE_VERSION_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>POWERGLITCH_EN_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RPT4_RESERVED1_ERR</name>
+              <description>Reserved.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_REPEAT_ERR4</name>
+          <description>Programming error record register 4 of BLOCK0.</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RPT4_RESERVED2_ERR</name>
+              <description>If any bits in this filed are 1, then it indicates a programming error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR0</name>
+          <description>Programming error record register 0 of BLOCK1-10.</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAC_SPI_8M_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAC_SPI_8M_FAIL</name>
+              <description>0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART1_FAIL</name>
+              <description>0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USR_DATA_FAIL</name>
+              <description>0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY0_FAIL</name>
+              <description>0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY1_FAIL</name>
+              <description>0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY2_FAIL</name>
+              <description>0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY3_FAIL</name>
+              <description>0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY4_FAIL</name>
+              <description>0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_RS_ERR1</name>
+          <description>Programming error record register 1 of BLOCK1-10.</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY5_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>KEY5_FAIL</name>
+              <description>0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_ERR_NUM</name>
+              <description>The value of this signal means the number of error bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SYS_PART2_FAIL</name>
+              <description>0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>eFuse clcok configuration register.</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>EFUSE_MEM_FORCE_PD</name>
+              <description>Set this bit to force eFuse SRAM into power-saving mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>Set this bit and force to activate clock signal of eFuse SRAM.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_MEM_FORCE_PU</name>
+              <description>Set this bit to force eFuse SRAM into working mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>Set this bit and force to enable clock signal of eFuse memory.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>eFuse operation mode configuraiton register</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OP_CODE</name>
+              <description>0x5A5A: Operate programming command 0x5AA5: Operate read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>eFuse status register.</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Indicates the state of the eFuse state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_LOAD_SW</name>
+              <description>The value of OTP_LOAD_SW.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_C_SYNC2</name>
+              <description>The value of OTP_VDDQ_C_SYNC2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_STROBE_SW</name>
+              <description>The value of OTP_STROBE_SW.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_CSB_SW</name>
+              <description>The value of OTP_CSB_SW.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_PGENB_SW</name>
+              <description>The value of OTP_PGENB_SW.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTP_VDDQ_IS_SW</name>
+              <description>The value of OTP_VDDQ_IS_SW.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>REPEAT_ERR_CNT</name>
+              <description>Indicates the number of error bits during programming BLOCK0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>eFuse command register.</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_CMD</name>
+              <description>Set this bit to send read command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_CMD</name>
+              <description>Set this bit to send programming command.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BLK_NUM</name>
+              <description>The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>eFuse raw interrupt register.</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_RAW</name>
+              <description>The raw bit signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_RAW</name>
+              <description>The raw bit signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>eFuse interrupt status register.</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ST</name>
+              <description>The status signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ST</name>
+              <description>The status signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>eFuse interrupt enable register.</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_ENA</name>
+              <description>The enable signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_ENA</name>
+              <description>The enable signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>eFuse interrupt clear register.</description>
+          <addressOffset>0x1E4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>READ_DONE_INT_CLR</name>
+              <description>The clear signal for read_done interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PGM_DONE_INT_CLR</name>
+              <description>The clear signal for pgm_done interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAC_CONF</name>
+          <description>Controls the eFuse programming voltage.</description>
+          <addressOffset>0x1E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0001FE1C</resetValue>
+          <fields>
+            <field>
+              <name>DAC_CLK_DIV</name>
+              <description>Controls the division factor of the rising clock of the programming voltage.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_CLK_PAD_SEL</name>
+              <description>Don't care.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_NUM</name>
+              <description>Controls the rising period of the programming voltage.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OE_CLR</name>
+              <description>Reduces the power supply of the programming voltage.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_TIM_CONF</name>
+          <description>Configures read timing parameters.</description>
+          <addressOffset>0x1EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x12000000</resetValue>
+          <fields>
+            <field>
+              <name>READ_INIT_NUM</name>
+              <description>Configures the initial read time of eFuse.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF1</name>
+          <description>Configurarion register 1 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00288000</resetValue>
+          <fields>
+            <field>
+              <name>PWR_ON_NUM</name>
+              <description>Configures the power up time for VDDQ.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_TIM_CONF2</name>
+          <description>Configurarion register 2 of eFuse programming timing parameters.</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000190</resetValue>
+          <fields>
+            <field>
+              <name>PWR_OFF_NUM</name>
+              <description>Configures the power outage time for VDDQ.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>eFuse version register.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101290</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Stores eFuse version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EXTMEM</name>
+      <description>External Memory</description>
+      <groupName>EXTMEM</groupName>
+      <baseAddress>0x600C4000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x17C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>DCACHE_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_ENABLE</name>
+              <description>The bit is used to activate the data cache. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_SIZE_MODE</name>
+              <description>The bit is used to configure cache memory size.0: 32KB, 1: 64KB</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_BLOCKSIZE_MODE</name>
+              <description>The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_CTRL1</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_SHUT_CORE0_BUS</name>
+              <description>The bit is used to disable core0 dbus, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_SHUT_CORE1_BUS</name>
+              <description>The bit is used to disable core1 dbus, 0: enable, 1: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_TAG_POWER_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power dcache tag memory down, 0: follow  rtc_lslp_pd, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power dcache tag memory up, 0: follow  rtc_lslp_pd, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_PRELOCK_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_PRELOCK_SCT0_EN</name>
+              <description>The bit is used to enable the first section of prelock function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOCK_SCT1_EN</name>
+              <description>The bit is used to enable the second section of prelock function.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_PRELOCK_SCT0_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_PRELOCK_SCT0_ADDR</name>
+              <description>The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_PRELOCK_SCT1_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_PRELOCK_SCT1_ADDR</name>
+              <description>The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_PRELOCK_SCT_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_PRELOCK_SCT1_SIZE</name>
+              <description>The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOCK_SCT0_SIZE</name>
+              <description>The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_LOCK_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_LOCK_ENA</name>
+              <description>The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_UNLOCK_ENA</name>
+              <description>The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_LOCK_DONE</name>
+              <description>The bit is used to indicate unlock/lock operation is finished.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_LOCK_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_LOCK_ADDR</name>
+              <description>The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_LOCK_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_LOCK_SIZE</name>
+              <description>The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_SYNC_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_INVALIDATE_ENA</name>
+              <description>The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_WRITEBACK_ENA</name>
+              <description>The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_CLEAN_ENA</name>
+              <description>The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_SYNC_DONE</name>
+              <description>The bit is used to indicate clean/writeback/invalidate operation is finished.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_SYNC_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_SYNC_ADDR</name>
+              <description>The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_SYNC_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_SYNC_SIZE</name>
+              <description>The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_OCCUPY_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_OCCUPY_ENA</name>
+              <description>The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_OCCUPY_DONE</name>
+              <description>The bit is used to indicate occupy operation is finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_OCCUPY_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_OCCUPY_ADDR</name>
+              <description>The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_OCCUPY_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_OCCUPY_SIZE</name>
+              <description>The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_PRELOAD_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOAD_DONE</name>
+              <description>The bit is used to indicate preload operation is finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOAD_ORDER</name>
+              <description>The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_PRELOAD_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_PRELOAD_ADDR</name>
+              <description>The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_PRELOAD_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_PRELOAD_SIZE</name>
+              <description>The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_AUTOLOAD_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_AUTOLOAD_SCT0_ENA</name>
+              <description>The bits are used to enable the first section for autoload operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_AUTOLOAD_SCT1_ENA</name>
+              <description>The bits are used to enable the second section for autoload operation.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate autoload operation is finished.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_AUTOLOAD_ORDER</name>
+              <description>The bits are used to configure the direction of autoload. 1: descending, 0: ascending.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_AUTOLOAD_RQST</name>
+              <description>The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_AUTOLOAD_SIZE</name>
+              <description>The bits are used to configure the numbers of the cache block for the issuing autoload operation.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_AUTOLOAD_BUFFER_CLEAR</name>
+              <description>The bit is used to clear autoload buffer in dcache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_AUTOLOAD_SCT0_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_AUTOLOAD_SCT0_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_AUTOLOAD_SCT0_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_AUTOLOAD_SCT0_SIZE</name>
+              <description>The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_AUTOLOAD_SCT1_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_AUTOLOAD_SCT1_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_AUTOLOAD_SCT1_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_AUTOLOAD_SCT1_SIZE</name>
+              <description>The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_ENABLE</name>
+              <description>The bit is used to activate the data cache. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_WAY_MODE</name>
+              <description>The bit is used to configure cache way mode.0: 4-way, 1: 8-way</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SIZE_MODE</name>
+              <description>The bit is used to configure cache memory size.0: 16KB, 1: 32KB</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_BLOCKSIZE_MODE</name>
+              <description>The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_CTRL1</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_SHUT_CORE0_BUS</name>
+              <description>The bit is used to disable core0 ibus, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SHUT_CORE1_BUS</name>
+              <description>The bit is used to disable core1 ibus, 0: enable, 1: disable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_TAG_POWER_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_TAG_MEM_FORCE_ON</name>
+              <description>The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_TAG_MEM_FORCE_PD</name>
+              <description>The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_TAG_MEM_FORCE_PU</name>
+              <description>The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOCK_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOCK_SCT0_EN</name>
+              <description>The bit is used to enable the first section of prelock function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOCK_SCT1_EN</name>
+              <description>The bit is used to enable the second section of prelock function.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOCK_SCT0_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOCK_SCT0_ADDR</name>
+              <description>The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOCK_SCT1_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOCK_SCT1_ADDR</name>
+              <description>The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOCK_SCT_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOCK_SCT1_SIZE</name>
+              <description>The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOCK_SCT0_SIZE</name>
+              <description>The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_LOCK_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_LOCK_ENA</name>
+              <description>The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_UNLOCK_ENA</name>
+              <description>The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_LOCK_DONE</name>
+              <description>The bit is used to indicate unlock/lock operation is finished.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_LOCK_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_LOCK_ADDR</name>
+              <description>The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_LOCK_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_LOCK_SIZE</name>
+              <description>The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_INVALIDATE_ENA</name>
+              <description>The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SYNC_DONE</name>
+              <description>The bit is used to indicate invalidate operation is finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_ADDR</name>
+              <description>The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_SIZE</name>
+              <description>The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_ENA</name>
+              <description>The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_DONE</name>
+              <description>The bit is used to indicate preload operation is finished.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_ORDER</name>
+              <description>The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_ADDR</name>
+              <description>The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_SIZE</name>
+              <description>The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT0_ENA</name>
+              <description>The bits are used to enable the first section for autoload operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT1_ENA</name>
+              <description>The bits are used to enable the second section for autoload operation.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_ENA</name>
+              <description>The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_DONE</name>
+              <description>The bit is used to indicate autoload operation is finished.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_ORDER</name>
+              <description>The bits are used to configure the direction of autoload. 1: descending, 0: ascending.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_RQST</name>
+              <description>The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_SIZE</name>
+              <description>The bits are used to configure the numbers of the cache block for the issuing autoload operation.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_AUTOLOAD_BUFFER_CLEAR</name>
+              <description>The bit is used to clear autoload buffer in icache.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_SCT0_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT0_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_SCT0_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT0_SIZE</name>
+              <description>The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_SCT1_ADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT1_ADDR</name>
+              <description>The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_AUTOLOAD_SCT1_SIZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_AUTOLOAD_SCT1_SIZE</name>
+              <description>The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>27</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_TO_FLASH_START_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x44000000</resetValue>
+          <fields>
+            <field>
+              <name>IBUS_TO_FLASH_START_VADDR</name>
+              <description>The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_TO_FLASH_END_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x47FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>IBUS_TO_FLASH_END_VADDR</name>
+              <description>The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_TO_FLASH_START_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS_TO_FLASH_START_VADDR</name>
+              <description>The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_TO_FLASH_END_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS_TO_FLASH_END_VADDR</name>
+              <description>The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ACS_CNT_CLR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DCACHE_ACS_CNT_CLR</name>
+              <description>The bit is used to clear dcache counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ICACHE_ACS_CNT_CLR</name>
+              <description>The bit is used to clear icache counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_ACS_MISS_CNT</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS_ACS_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by ibus access flash/spiram.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IBUS_ACS_CNT</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IBUS_ACS_CNT</name>
+              <description>The bits are used to count the number of ibus access flash/spiram through icache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_ACS_FLASH_MISS_CNT</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS_ACS_FLASH_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by dbus access flash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_ACS_SPIRAM_MISS_CNT</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS_ACS_SPIRAM_MISS_CNT</name>
+              <description>The bits are used to count the number of the cache miss caused by dbus access spiram.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DBUS_ACS_CNT</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DBUS_ACS_CNT</name>
+              <description>The bits are used to count the number of dbus access flash/spiram through dcache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ILG_INT_ENA</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_OP_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by sync configurations fault.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_OP_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by preload configurations fault.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_SYNC_OP_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by sync configurations fault.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOAD_OP_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by preload configurations fault.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_WRITE_FLASH_INT_ENA</name>
+              <description>The bit is used to enable interrupt by dcache trying to write flash.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by mmu entry fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_OCCUPY_EXC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IBUS_CNT_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt by ibus counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUS_CNT_OVF_INT_ENA</name>
+              <description>The bit is used to enable interrupt by dbus counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ILG_INT_CLR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_OP_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by sync configurations fault.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_OP_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by preload configurations fault.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DCACHE_SYNC_OP_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by sync configurations fault.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOAD_OP_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by preload configurations fault.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DCACHE_WRITE_FLASH_INT_CLR</name>
+              <description>The bit is used to clear interrupt by dcache trying to write flash.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by mmu entry fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DCACHE_OCCUPY_EXC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IBUS_CNT_OVF_INT_CLR</name>
+              <description>The bit is used to clear interrupt by ibus counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DBUS_CNT_OVF_INT_CLR</name>
+              <description>The bit is used to clear interrupt by dbus counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ILG_INT_ST</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_OP_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by sync configurations fault.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_OP_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by preload configurations fault.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_SYNC_OP_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by sync configurations fault.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOAD_OP_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by preload configurations fault.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_WRITE_FLASH_ST</name>
+              <description>The bit is used to indicate interrupt by dcache trying to write flash.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MMU_ENTRY_FAULT_ST</name>
+              <description>The bit is used to indicate interrupt by mmu entry fault.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_OCCUPY_EXC_ST</name>
+              <description>The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IBUS_ACS_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_FLASH_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus access flash miss counter overflow.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST</name>
+              <description>The bit is used to indicate interrupt by dbus access spiram miss counter overflow.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_ACS_CACHE_INT_ENA</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ACS_MSK_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WR_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ACS_MSK_DC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_ACS_CACHE_INT_CLR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ACS_MSK_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WR_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ACS_MSK_DC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_ACS_CACHE_INT_ST</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_ACS_MSK_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WR_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ACS_MSK_DCACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE1_ACS_CACHE_INT_ENA</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE1_IBUS_ACS_MSK_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE1_IBUS_WR_IC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE1_IBUS_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE1_DBUS_ACS_MSK_DC_INT_ENA</name>
+              <description>The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE1_DBUS_REJECT_INT_ENA</name>
+              <description>The bit is used to enable interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE1_ACS_CACHE_INT_CLR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE1_IBUS_ACS_MSK_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE1_IBUS_WR_IC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE1_IBUS_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE1_DBUS_ACS_MSK_DC_INT_CLR</name>
+              <description>The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CORE1_DBUS_REJECT_INT_CLR</name>
+              <description>The bit is used to clear interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE1_ACS_CACHE_INT_ST</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE1_IBUS_ACS_MSK_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access  icache while the core1_ibus is disabled or  icache is disabled which include speculative access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE1_IBUS_WR_ICACHE_ST</name>
+              <description>The bit is used to indicate interrupt by ibus trying to write icache</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE1_IBUS_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE1_DBUS_ACS_MSK_DCACHE_ST</name>
+              <description>The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE1_DBUS_REJECT_ST</name>
+              <description>The bit is used to indicate interrupt by authentication fail.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_DBUS_REJECT_ST</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_DBUS_TAG_ATTR</name>
+              <description>The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_DBUS_WORLD</name>
+              <description>The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_DBUS_REJECT_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE0_DBUS_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access dbus when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_IBUS_REJECT_ST</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_TAG_ATTR</name>
+              <description>The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE0_IBUS_WORLD</name>
+              <description>The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE0_IBUS_REJECT_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE0_IBUS_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE1_DBUS_REJECT_ST</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE1_DBUS_TAG_ATTR</name>
+              <description>The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE1_DBUS_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE1_DBUS_WORLD</name>
+              <description>The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE1_DBUS_REJECT_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE1_DBUS_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access dbus when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE1_IBUS_REJECT_ST</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE1_IBUS_TAG_ATTR</name>
+              <description>The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE1_IBUS_ATTR</name>
+              <description>The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE1_IBUS_WORLD</name>
+              <description>The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE1_IBUS_REJECT_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE1_IBUS_VADDR</name>
+              <description>The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_FAULT_CONTENT</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_FAULT_CONTENT</name>
+              <description>The bits are used to indicate the content of mmu entry which cause mmu fault..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_FAULT_CODE</name>
+              <description>The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_FAULT_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_FAULT_VADDR</name>
+              <description>The bits are used to indicate the virtual address which cause mmu fault..</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_WRAP_AROUND_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_FLASH_WRAP_AROUND</name>
+              <description>The bit is used to enable wrap around mode when read data from flash.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SRAM_RD_WRAP_AROUND</name>
+              <description>The bit is used to enable wrap around mode when read data from spiram.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_POWER_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_MMU_MEM_FORCE_ON</name>
+              <description>The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_MEM_FORCE_PD</name>
+              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_MMU_MEM_FORCE_PU</name>
+              <description>The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_STATE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_STATE</name>
+              <description>The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_STATE</name>
+              <description>The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state,  0: not in idle state</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RECORD_DISABLE_DB_ENCRYPT</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RECORD_DISABLE_G0CB_DECRYPT</name>
+              <description>Reserved</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>CLK_FORCE_ON_MANUAL_CRYPT</name>
+              <description>The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_FORCE_ON_AUTO_CRYPT</name>
+              <description>The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_FORCE_ON_CRYPT</name>
+              <description>The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_BRIDGE_ARBITER_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALLOC_WB_HOLD_ARBITER</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_PRELOAD_INT_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by  icache pre-load done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by  icache pre-load done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_PRELOAD_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by  icache pre-load done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOAD_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by dcache pre-load done.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOAD_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by dcache pre-load done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_PRELOAD_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by dcache pre-load done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SYNC_INT_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by  icache sync done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ICACHE_SYNC_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by  icache sync done.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_SYNC_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by  icache sync done.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DCACHE_SYNC_INT_ST</name>
+              <description>The bit is used to indicate the interrupt by dcache sync done.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DCACHE_SYNC_INT_ENA</name>
+              <description>The bit is used to enable the interrupt by dcache sync done.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_SYNC_INT_CLR</name>
+              <description>The bit is used to clear the interrupt by dcache sync done.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_OWNER</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_OWNER</name>
+              <description>The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CONF_MISC</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT</name>
+              <description>The bit is used to disable checking mmu entry fault by preload operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT</name>
+              <description>The bit is used to disable checking mmu entry fault by sync operation.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_TRACE_ENA</name>
+              <description>The bit is used to enable cache trace function.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_FREEZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>ENA</name>
+              <description>The bit is used to enable dcache freeze mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DONE</name>
+              <description>The bit is used to indicate dcache freeze success</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_FREEZE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>ENA</name>
+              <description>The bit is used to enable icache freeze mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DONE</name>
+              <description>The bit is used to indicate icache freeze success</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_ATOMIC_OPERATE_ENA</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_ATOMIC_OPERATE_ENA</name>
+              <description>The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_ATOMIC_OPERATE_ENA</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_ATOMIC_OPERATE_ENA</name>
+              <description>The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_REQUEST</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BYPASS</name>
+              <description>The bit is used to disable request recording which could cause performance issue</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_OBJECT_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ICACHE_TAG_OBJECT</name>
+              <description>Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_TAG_OBJECT</name>
+              <description>Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_WAY_OBJECT</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_TAG_WAY_OBJECT</name>
+              <description>Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_VADDR</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_VADDR</name>
+              <description>Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_CONTENT</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_TAG_CONTENT</name>
+              <description>This is a constant place where we can write data to or read data from the tag memory on the specified cache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02012310</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO</name>
+      <description>General Purpose Input/Output</description>
+      <groupName>GPIO</groupName>
+      <baseAddress>0x60004000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x634</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>GPIO</name>
+        <value>16</value>
+      </interrupt>
+      <interrupt>
+        <name>GPIO_NMI</name>
+        <value>17</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>BT_SELECT</name>
+          <description>GPIO bit select register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BT_SEL</name>
+              <description>GPIO bit select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT</name>
+          <description>GPIO output register for GPIO0-31</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_ORIG</name>
+              <description>GPIO output register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TS</name>
+          <description>GPIO output set register for GPIO0-31</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TS</name>
+              <description>GPIO output set register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_W1TC</name>
+          <description>GPIO output clear register for GPIO0-31</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_W1TC</name>
+              <description>GPIO output clear register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1</name>
+          <description>GPIO output register for GPIO32-53</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_ORIG</name>
+              <description>GPIO output register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1_W1TS</name>
+          <description>GPIO output set register for GPIO32-53</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT1_W1TS</name>
+              <description>GPIO output set register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT1_W1TC</name>
+          <description>GPIO output clear register for GPIO32-53</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT1_W1TC</name>
+              <description>GPIO output clear register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_SELECT</name>
+          <description>GPIO sdio select register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_SEL</name>
+              <description>GPIO sdio select register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE</name>
+          <description>GPIO output enable register for GPIO0-31</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO output enable register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TS</name>
+          <description>GPIO output enable set register for GPIO0-31</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TS</name>
+              <description>GPIO output enable set register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <description>GPIO output enable clear register for GPIO0-31</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TC</name>
+              <description>GPIO output enable clear register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1</name>
+          <description>GPIO output enable register for GPIO32-53</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>GPIO output enable register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1_W1TS</name>
+          <description>GPIO output enable set register for GPIO32-53</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE1_W1TS</name>
+              <description>GPIO output enable set register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE1_W1TC</name>
+          <description>GPIO output enable clear register for GPIO32-53</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE1_W1TC</name>
+              <description>GPIO output enable clear register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STRAP</name>
+          <description>pad strapping register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRAPPING</name>
+              <description>pad strapping register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN</name>
+          <description>GPIO input register for GPIO0-31</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO input register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN1</name>
+          <description>GPIO input register for GPIO32-53</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA_NEXT</name>
+              <description>GPIO input register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>GPIO interrupt status register for GPIO0-31</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>GPIO interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TS</name>
+          <description>GPIO interrupt status set register for GPIO0-31</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TS</name>
+              <description>GPIO interrupt status set register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_W1TC</name>
+          <description>GPIO interrupt status clear register for GPIO0-31</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_W1TC</name>
+              <description>GPIO interrupt status clear register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1</name>
+          <description>GPIO interrupt status register for GPIO32-53</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT</name>
+              <description>GPIO interrupt status register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1_W1TS</name>
+          <description>GPIO interrupt status set register for GPIO32-53</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS1_W1TS</name>
+              <description>GPIO interrupt status set register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS1_W1TC</name>
+          <description>GPIO interrupt status clear register for GPIO32-53</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS1_W1TC</name>
+              <description>GPIO interrupt status clear register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT</name>
+          <description>GPIO PRO_CPU interrupt status register for GPIO0-31</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT</name>
+              <description>GPIO PRO_CPU interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT</name>
+          <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT</name>
+              <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT</name>
+          <description>GPIO CPUSDIO interrupt status register for GPIO0-31</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT</name>
+              <description>GPIO CPUSDIO interrupt status register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_INT1</name>
+          <description>GPIO PRO_CPU interrupt status register for GPIO32-53</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_INT1</name>
+              <description>GPIO PRO_CPU interrupt status register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCPU_NMI_INT1</name>
+          <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PROCPU_NMI_INT1</name>
+              <description>GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPUSDIO_INT1</name>
+          <description>GPIO CPUSDIO interrupt status register for GPIO32-53</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_INT1</name>
+              <description>GPIO CPUSDIO interrupt status register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>54</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-53</dimIndex>
+          <name>PIN%s</name>
+          <description>GPIO pin configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYNC2_BYPASS</name>
+              <description>set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>set this bit to select pad driver. 1:open-drain. 0:normal.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC1_BYPASS</name>
+              <description>set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TYPE</name>
+              <description>set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENABLE</name>
+              <description>set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONFIG</name>
+              <description>reserved</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_ENA</name>
+              <description>set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_NEXT</name>
+          <description>GPIO interrupt source register for GPIO0-31</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INTERRUPT_NEXT</name>
+              <description>GPIO interrupt source register for GPIO0-31</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS_NEXT1</name>
+          <description>GPIO interrupt source register for GPIO32-53</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS_INTERRUPT_NEXT1</name>
+              <description>GPIO interrupt source register for GPIO32-53</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>256</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-255</dimIndex>
+          <name>FUNC%s_IN_SEL_CFG</name>
+          <description>GPIO input function configuration register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IN_SEL</name>
+              <description>set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_INV_SEL</name>
+              <description>set this bit to invert input signal. 1:invert. 0:not invert.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEL</name>
+              <description>set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>54</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-53</dimIndex>
+          <name>FUNC%s_OUT_SEL_CFG</name>
+          <description>GPIO output function select register</description>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>OUT_SEL</name>
+              <description>The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INV_SEL</name>
+              <description>set this bit to invert output signal.1:invert.0:not invert.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_SEL</name>
+              <description>set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEN_INV_SEL</name>
+              <description>set this bit to invert output enable signal.1:invert.0:not invert.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>GPIO clock gate register</description>
+          <addressOffset>0x62C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>set this bit to enable GPIO clock gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_DATE</name>
+          <description>GPIO version register</description>
+          <addressOffset>0x6FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01907040</resetValue>
+          <fields>
+            <field>
+              <name>REG_DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIOSD</name>
+      <description>Sigma-Delta Modulation</description>
+      <groupName>GPIOSD</groupName>
+      <baseAddress>0x60004F00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x2C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>SIGMADELTA%s</name>
+          <description>Duty Cycle Configure Register of SDM%s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>SD_IN</name>
+              <description>This field is used to configure the duty cycle of sigma delta modulation output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SD_PRESCALE</name>
+              <description>This field is used to set a divider value to divide APB clock.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_CG</name>
+          <description>Clock Gating Configure Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Clock enable bit of configuration registers for sigma delta modulation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_MISC</name>
+          <description>MISC Register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FUNCTION_CLK_EN</name>
+              <description>Clock enable bit of sigma delta modulation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SWAP</name>
+              <description>Reserved.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SIGMADELTA_VERSION</name>
+          <description>Version Control Register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01802260</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_SD_DATE</name>
+              <description>Version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>HMAC</name>
+      <description>HMAC (Hash-based Message Authentication Code) Accelerator</description>
+      <groupName>HMAC</groupName>
+      <baseAddress>0x6003E000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SET_START</name>
+          <description>Process control register 0.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_START</name>
+              <description>Start hmac operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_PURPOSE</name>
+          <description>Configure purpose.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PURPOSE_SET</name>
+              <description>Set hmac parameter purpose.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_KEY</name>
+          <description>Configure key.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>KEY_SET</name>
+              <description>Set hmac parameter key.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_PARA_FINISH</name>
+          <description>Finish initial configuration.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_PARA_END</name>
+              <description>Finish hmac configuration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ONE</name>
+          <description>Process control register 1.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ONE</name>
+              <description>Call SHA to calculate one message block.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_ING</name>
+          <description>Process control register 2.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_ING</name>
+              <description>Continue typical hmac.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_MESSAGE_END</name>
+          <description>Process control register 3.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_END</name>
+              <description>Start hardware padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_RESULT_FINISH</name>
+          <description>Process control register 4.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_RESULT_END</name>
+              <description>After read result from upstream, then let hmac back to idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_JTAG</name>
+          <description>Invalidate register 0.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_JTAG</name>
+              <description>Clear result from hmac downstream JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SET_INVALIDATE_DS</name>
+          <description>Invalidate register 1.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_INVALIDATE_DS</name>
+              <description>Clear result from hmac downstream DS.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_ERROR</name>
+          <description>Error register.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>QUREY_CHECK</name>
+              <description>Hmac configuration state. 0: key are agree with purpose. 1: error</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUERY_BUSY</name>
+          <description>Busy register.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUSY_STATE</name>
+              <description>Hmac state. 1'b0: idle. 1'b1: busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>WR_MESSAGE_MEM[%s]</name>
+          <description>Message block memory.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>32</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>RD_RESULT_MEM[%s]</name>
+          <description>Result from upstream.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>SET_MESSAGE_PAD</name>
+          <description>Process control register 5.</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_TEXT_PAD</name>
+              <description>Start software padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ONE_BLOCK</name>
+          <description>Process control register 6.</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SET_ONE_BLOCK</name>
+              <description>Don't have to do padding.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SOFT_JTAG_CTRL</name>
+          <description>Jtag register 0.</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SOFT_JTAG_CTRL</name>
+              <description>Turn on JTAG verification.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WR_JTAG</name>
+          <description>Jtag register 1.</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WR_JTAG</name>
+              <description>32-bit of key to be compared.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101070</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Hmac date information/ hmac version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2C0</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <groupName>I2C</groupName>
+      <baseAddress>0x60013000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x90</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2C_MST</name>
+        <value>11</value>
+      </interrupt>
+      <interrupt>
+        <name>I2C_EXT0</name>
+        <value>42</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>SCL_LOW_PERIOD</name>
+          <description>Configures the low level width of the SCL
+Clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_LOW_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTR</name>
+          <description>Transmission setting</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000020B</resetValue>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>0: direct output; 1: open drain output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>0: direct output; 1: open drain output.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAMPLE_SCL_LEVEL</name>
+              <description>This register is used to select the sample mode.
+1: sample SDA data on the SCL low level.
+0: sample SDA data on the SCL high level.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FULL_ACK_LEVEL</name>
+              <description>This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>Set this bit to configure the module as an I2C Master. Clear this bit to configure the
+module as an I2C Slave.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>Set this bit to start sending the data in txfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>This bit is used to control the sending mode for data needing to be sent.
+1: send data from the least significant bit;
+0: send data from the most significant bit.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>This bit is used to control the storage mode for received data.
+1: receive data from the least significant bit;
+0: receive data from the most significant bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Reserved</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_EN</name>
+              <description>This is the enable bit for arbitration_lost.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FSM_RST</name>
+              <description>This register is used to reset the scl FMS.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPGATE</name>
+              <description>synchronization bit</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_TX_AUTO_START_EN</name>
+              <description>This is the enable bit for slave to send data automatically</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_RW_CHECK_EN</name>
+              <description>This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_BROADCASTING_EN</name>
+              <description>This is the enable bit to support the 7bit general call function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SR</name>
+          <description>Describe I2C work status.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C000</resetValue>
+          <fields>
+            <field>
+              <name>RESP_REC</name>
+              <description>The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW</name>
+              <description>When in slave mode, 1: master reads from slave; 0: master writes to slave.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>When the I2C controller loses control of SCL line, this register changes to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDRESSED</name>
+              <description>When configured as an I2C Slave, and the address sent by the master is
+equal to the address of the slave, then this bit will be of high level.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>This field represents the amount of data needed to be sent.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STRETCH_CAUSE</name>
+              <description>The cause of stretching SCL low in slave mode. 0:  stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>This field stores the amount of received data in RAM.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_STATE_LAST</name>
+              <description>This field indicates the states of the I2C module state machine.
+0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_STATE_LAST</name>
+              <description>This field indicates the states of the state machine used to produce SCL.
+0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TO</name>
+          <description>Setting time out control for receiving data.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TIME_OUT_VALUE</name>
+              <description>This register is used to configure the timeout for receiving a data bit in APB
+clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_EN</name>
+              <description>This is the enable bit for time out control.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_ADDR</name>
+          <description>Local slave address setting</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_ADDR</name>
+              <description>When configured as an I2C Slave, this field is used to configure the slave address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_EN</name>
+              <description>This field is used to enable the slave 10-bit addressing mode in master mode.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_ST</name>
+          <description>FIFO status register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RADDR</name>
+              <description>This is the offset address of the APB reading from rxfifo</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_WADDR</name>
+              <description>This is the offset address of i2c module receiving data and writing to rxfifo.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_RADDR</name>
+              <description>This is the offset address of i2c module reading from txfifo.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WADDR</name>
+              <description>This is the offset address of APB bus writing to txfifo.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW_POINT</name>
+              <description>The received data in I2C slave mode.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIFO_CONF</name>
+          <description>FIFO configuration register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000408B</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_THRHD</name>
+              <description>The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NONFIFO_EN</name>
+              <description>Set this bit to enable APB nonfifo access.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_ADDR_CFG_EN</name>
+              <description>When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RST</name>
+              <description>Set this bit to reset rx-fifo.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RST</name>
+              <description>Set this bit to reset tx-fifo.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FIFO_PRT_EN</name>
+              <description>The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>Rx FIFO read data.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FIFO_RDATA</name>
+              <description>The value of rx FIFO read data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_RAW</name>
+              <description>The raw interrupt bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_RAW</name>
+              <description>The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <description>Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_CLR</name>
+              <description>Set this bit to clear the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_CLR</name>
+              <description>Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_CLR</name>
+              <description>Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_CLR</name>
+              <description>Set this bit to clear I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_CLR</name>
+              <description>Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_CLR</name>
+              <description>Set this bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ENA</name>
+              <description>The interrupt enable bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NACK_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_ENA</name>
+              <description>The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_STATUS</name>
+          <description>Status of captured I2C communication events</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_WM_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>END_DETECT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS_DONE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_START_INT_ST</name>
+              <description>The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NACK_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_OVF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_UDF_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_ST_TO_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DET_START_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_DET_START_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_STRETCH_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GENERAL_CALL_INT_ST</name>
+              <description>The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_HOLD</name>
+          <description>Configures the hold time after a negative SCL edge.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time to hold the data after the negative
+edge of SCL, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_SAMPLE</name>
+          <description>Configures the sample time after a positive SCL edge.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure for how long SDA is sampled, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH_PERIOD</name>
+          <description>Configures the high level width of SCL</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_HIGH_PERIOD</name>
+              <description>This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_WAIT_HIGH_PERIOD</name>
+              <description>This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_HOLD</name>
+          <description>Configures the delay between the SDA and SCL negative edge for a start condition</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the negative edge
+of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_RSTART_SETUP</name>
+          <description>Configures the delay between the positive
+edge of SCL and the negative edge of SDA</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive
+edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_HOLD</name>
+          <description>Configures the delay after the SCL clock
+edge for a stop condition</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the delay after the STOP condition,
+in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_SETUP</name>
+          <description>Configures the delay between the SDA and
+SCL positive edge for a stop condition</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>TIME</name>
+              <description>This register is used to configure the time between the positive edge
+of SCL and the positive edge of SDA, in I2C module clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FILTER_CFG</name>
+          <description>SCL and SDA filter configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000300</resetValue>
+          <fields>
+            <field>
+              <name>SCL_FILTER_THRES</name>
+              <description>When a pulse on the SCL input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_THRES</name>
+              <description>When a pulse on the SDA input has smaller width than this register value
+in I2C module clock cycles, the I2C controller will ignore that pulse.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FILTER_EN</name>
+              <description>This is the filter enable bit for SCL.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_FILTER_EN</name>
+              <description>This is the filter enable bit for SDA.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>I2C CLK configuration register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00200000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>the integral part of the fractional divisor for i2c module</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>the numerator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>the denominator of the fractional part of the fractional divisor for i2c module</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>The clock selection for i2c module:0-XTAL;1-CLK_8MHz.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_ACTIVE</name>
+              <description>The clock switch for i2c module</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-7</dimIndex>
+          <name>COMD%s</name>
+          <description>I2C command register %s</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND</name>
+              <description>This is the content of command 0. It consists of three parts:
+op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+Byte_num represents the number of bytes that need to be sent or received.
+ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more
+Information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND_DONE</name>
+              <description>When command 0 is done in I2C Master mode, this bit changes to high
+level.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_ST_TIME_OUT</name>
+          <description>SCL status time out register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_ST_TO_I2C</name>
+              <description>The threshold value of SCL_FSM state unchanged period. It should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_MAIN_ST_TIME_OUT</name>
+          <description>SCL main status time out register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SCL_MAIN_ST_TO_I2C</name>
+              <description>The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_SP_CONF</name>
+          <description>Power configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCL_RST_SLV_EN</name>
+              <description>When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_RST_SLV_NUM</name>
+              <description>Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_PD_EN</name>
+              <description>The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDA_PD_EN</name>
+              <description>The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STRETCH_CONF</name>
+          <description>Set SCL stretch of I2C slave</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STRETCH_PROTECT_NUM</name>
+              <description>Configure the period of I2C slave stretching SCL line.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_EN</name>
+              <description>The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_SCL_STRETCH_CLR</name>
+              <description>Set this bit to clear the I2C slave SCL stretch function.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLAVE_BYTE_ACK_CTL_EN</name>
+              <description>The enable bit for slave to control ACK level function.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_BYTE_ACK_LVL</name>
+              <description>Set the ACK level when slave controlling ACK level function enables.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20070201</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXFIFO_START_ADDR</name>
+          <description>I2C TXFIFO base address register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TXFIFO_START_ADDR</name>
+              <description>This is the I2C txfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXFIFO_START_ADDR</name>
+          <description>I2C RXFIFO base address register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_START_ADDR</name>
+              <description>This is the I2C rxfifo first address.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="I2C0">
+      <name>I2C1</name>
+      <description>I2C (Inter-Integrated Circuit) Controller</description>
+      <baseAddress>0x60027000</baseAddress>
+      <interrupt>
+        <name>I2C_EXT1</name>
+        <value>43</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>I2S0</name>
+      <description>I2S (Inter-IC Sound) Controller</description>
+      <groupName>I2S</groupName>
+      <baseAddress>0x6000F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x5C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S0</name>
+        <value>25</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>INT_RAW</name>
+          <description>I2S interrupt raw register, valid in level.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>I2S interrupt status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>I2S interrupt enable register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>I2S interrupt clear register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CONF</name>
+          <description>I2S RX configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00009600</resetValue>
+          <fields>
+            <field>
+              <name>RX_RESET</name>
+              <description>Set this bit to reset receiver</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_FIFO_RESET</name>
+              <description>Set this bit to reset Rx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_START</name>
+              <description>Set this bit to start receiving data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave receiver mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO</name>
+              <description>Set this bit to enable receiver  in mono mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIG_ENDIAN</name>
+              <description>I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_UPDATE</name>
+              <description>Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_CONF</name>
+              <description>I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PCM_BYPASS</name>
+              <description>Set this bit to bypass Compress/Decompress module for received data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_STOP_MODE</name>
+              <description>0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LEFT_ALIGN</name>
+              <description>1: I2S RX left alignment mode. 0: I2S RX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_24_FILL_EN</name>
+              <description>1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BIT_ORDER</name>
+              <description>I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_EN</name>
+              <description>1: Enable I2S TDM Rx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PDM_EN</name>
+              <description>1: Enable I2S PDM Rx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PDM2PCM_EN</name>
+              <description>1: Enable PDM2PCM RX mode. 0: DIsable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_PDM_SINC_DSR_16_EN</name>
+              <description>Configure the down sampling rate of PDM RX filter group1 module. 1: The  down sampling rate is 128. 0: down sampling rate is 64.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CONF</name>
+          <description>I2S TX configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000B200</resetValue>
+          <fields>
+            <field>
+              <name>TX_RESET</name>
+              <description>Set this bit to reset transmitter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_FIFO_RESET</name>
+              <description>Set this bit to reset Tx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START</name>
+              <description>Set this bit to start transmitting data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave transmitter mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO</name>
+              <description>Set this bit to enable transmitter in mono mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHAN_EQUAL</name>
+              <description>1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIG_ENDIAN</name>
+              <description>I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_UPDATE</name>
+              <description>Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_CONF</name>
+              <description>I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PCM_BYPASS</name>
+              <description>Set this bit to bypass  Compress/Decompress module for transmitted data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP_EN</name>
+              <description>Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LEFT_ALIGN</name>
+              <description>1: I2S TX left alignment mode. 0: I2S TX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_24_FILL_EN</name>
+              <description>1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BIT_ORDER</name>
+              <description>I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_EN</name>
+              <description>1: Enable I2S TDM Tx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_EN</name>
+              <description>1: Enable I2S PDM Tx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHAN_MOD</name>
+              <description>I2S transmitter channel mode configuration bits.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_LOOPBACK</name>
+              <description>Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CONF1</name>
+          <description>I2S RX configure register 1</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x2F3DE300</resetValue>
+          <fields>
+            <field>
+              <name>RX_TDM_WS_WIDTH</name>
+              <description>The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in receiver mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HALF_SAMPLE_BITS</name>
+              <description>I2S Rx half sample bits -1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN_BITS</name>
+              <description>The Rx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_MSB_SHIFT</name>
+              <description>Set this bit to enable receiver in Phillips standard mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CONF1</name>
+          <description>I2S TX configure register 1</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x6F3DE300</resetValue>
+          <fields>
+            <field>
+              <name>TX_TDM_WS_WIDTH</name>
+              <description>The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in transmitter mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HALF_SAMPLE_BITS</name>
+              <description>I2S Tx half sample bits -1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN_BITS</name>
+              <description>The Tx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_MSB_SHIFT</name>
+              <description>Set this bit to enable transmitter in Phillips standard mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_NO_DLY</name>
+              <description>1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CLKM_CONF</name>
+          <description>I2S RX clock configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RX_CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLK_ACTIVE</name>
+              <description>I2S Rx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLK_SEL</name>
+              <description>Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCLK_SEL</name>
+              <description>0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CLKM_CONF</name>
+          <description>I2S TX clock configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>TX_CLKM_DIV_NUM</name>
+              <description>Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b &lt;= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLK_ACTIVE</name>
+              <description>I2S Tx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLK_SEL</name>
+              <description>Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_CLKM_DIV_CONF</name>
+          <description>I2S RX module clock divider configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>RX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CLKM_DIV_CONF</name>
+          <description>I2S TX module clock divider configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>TX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_PCM2PDM_CONF</name>
+          <description>I2S TX PCM2PDM configuration register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x004AA004</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_HP_BYPASS</name>
+              <description>I2S TX PDM bypass hp filter or not. The option has been removed.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_OSR2</name>
+              <description>I2S TX PDM OSR2 value</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_PRESCALE</name>
+              <description>I2S TX PDM prescale for sigmadelta</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_HP_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_LP_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SINC_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_IN_SHIFT</name>
+              <description>I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_DITHER2</name>
+              <description>I2S TX PDM sigmadelta dither2 value</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_SIGMADELTA_DITHER</name>
+              <description>I2S TX PDM sigmadelta dither value</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_DAC_2OUT_EN</name>
+              <description>I2S TX PDM dac mode enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_DAC_MODE_EN</name>
+              <description>I2S TX PDM dac 2channel enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCM2PDM_CONV_EN</name>
+              <description>I2S TX PDM Converter enable</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_PCM2PDM_CONF1</name>
+          <description>I2S TX PCM2PDM configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03F783C0</resetValue>
+          <fields>
+            <field>
+              <name>TX_PDM_FP</name>
+              <description>I2S TX PDM Fp</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_PDM_FS</name>
+              <description>I2S TX PDM Fs</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IIR_HP_MULT12_5</name>
+              <description>The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IIR_HP_MULT12_0</name>
+              <description>The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>RX_TDM_PDM_CHAN0_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN1_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN2_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN3_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN4_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN5_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN6_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_PDM_CHAN7_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>TX_TDM_CHAN0_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN1_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN2_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN3_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN4_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN5_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN6_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN7_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_TDM_SKIP_MSK_EN</name>
+              <description>When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_TIMING</name>
+          <description>I2S RX timing control register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_SD_IN_DM</name>
+              <description>The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SD1_IN_DM</name>
+              <description>The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SD2_IN_DM</name>
+              <description>The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SD3_IN_DM</name>
+              <description>The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_OUT_DM</name>
+              <description>The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_WS_IN_DM</name>
+              <description>The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_BCK_IN_DM</name>
+              <description>The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_TIMING</name>
+          <description>I2S TX timing control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_SD_OUT_DM</name>
+              <description>The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SD1_OUT_DM</name>
+              <description>The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_OUT_DM</name>
+              <description>The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_WS_IN_DM</name>
+              <description>The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BCK_IN_DM</name>
+              <description>The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_HUNG_CONF</name>
+          <description>I2S HUNG configure register.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000810</resetValue>
+          <fields>
+            <field>
+              <name>LC_FIFO_TIMEOUT</name>
+              <description>the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_SHIFT</name>
+              <description>The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LC_FIFO_TIMEOUT_ENA</name>
+              <description>The enable bit for FIFO timeout</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXEOF_NUM</name>
+          <description>I2S RX data number control register.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000040</resetValue>
+          <fields>
+            <field>
+              <name>RX_EOF_NUM</name>
+              <description>The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF_SIGLE_DATA</name>
+          <description>I2S signal data register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_DATA</name>
+              <description>The configured constant channel data to be sent out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>I2S TX status register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>TX_IDLE</name>
+              <description>1: i2s_tx is idle state. 0: i2s_tx is working.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02009070</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>I2S version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S1</name>
+      <description>I2S (Inter-IC Sound) Controller</description>
+      <groupName>I2S1</groupName>
+      <baseAddress>0x6002D000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x54</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>I2S1</name>
+        <value>26</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>I2S_INT_RAW</name>
+          <description>I2S interrupt raw register, valid in level.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S_RX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2S_TX_DONE_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2S_RX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2S_TX_HUNG_INT_RAW</name>
+              <description>The raw interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_INT_ST</name>
+          <description>I2S interrupt status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S_RX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2S_TX_DONE_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2S_RX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2S_TX_HUNG_INT_ST</name>
+              <description>The masked interrupt status bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_INT_ENA</name>
+          <description>I2S interrupt enable register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S_RX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_DONE_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_HUNG_INT_ENA</name>
+              <description>The interrupt enable bit  for the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_INT_CLR</name>
+          <description>I2S interrupt clear register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S_RX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_done_int interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2S_TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_done_int interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2S_RX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_rx_hung_int interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2S_TX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear the i2s_tx_hung_int interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_RX_CONF</name>
+          <description>I2S RX configure register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00009600</resetValue>
+          <fields>
+            <field>
+              <name>I2S_RX_RESET</name>
+              <description>Set this bit to reset receiver</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2S_RX_FIFO_RESET</name>
+              <description>Set this bit to reset Rx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2S_RX_START</name>
+              <description>Set this bit to start receiving data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave receiver mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_MONO</name>
+              <description>Set this bit to enable receiver  in mono mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_BIG_ENDIAN</name>
+              <description>I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_UPDATE</name>
+              <description>Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_PCM_CONF</name>
+              <description>I2S RX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_PCM_BYPASS</name>
+              <description>Set this bit to bypass Compress/Decompress module for received data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_STOP_MODE</name>
+              <description>0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_LEFT_ALIGN</name>
+              <description>1: I2S RX left alignment mode. 0: I2S RX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_24_FILL_EN</name>
+              <description>1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_BIT_ORDER</name>
+              <description>I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_EN</name>
+              <description>1: Enable I2S TDM Rx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_PDM_EN</name>
+              <description>1: Enable I2S PDM Rx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_TX_CONF</name>
+          <description>I2S TX configure register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000B200</resetValue>
+          <fields>
+            <field>
+              <name>I2S_TX_RESET</name>
+              <description>Set this bit to reset transmitter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2S_TX_FIFO_RESET</name>
+              <description>Set this bit to reset Tx AFIFO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>I2S_TX_START</name>
+              <description>Set this bit to start transmitting data</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_SLAVE_MOD</name>
+              <description>Set this bit to enable slave transmitter mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_MONO</name>
+              <description>Set this bit to enable transmitter in mono mode</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CHAN_EQUAL</name>
+              <description>1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_BIG_ENDIAN</name>
+              <description>I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_UPDATE</name>
+              <description>Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_MONO_FST_VLD</name>
+              <description>1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_PCM_CONF</name>
+              <description>I2S TX compress/decompress configuration bit. &amp; 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &amp;</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_PCM_BYPASS</name>
+              <description>Set this bit to bypass  Compress/Decompress module for transmitted data.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_STOP_EN</name>
+              <description>Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_LEFT_ALIGN</name>
+              <description>1: I2S TX left alignment mode. 0: I2S TX right alignment mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_24_FILL_EN</name>
+              <description>1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_WS_IDLE_POL</name>
+              <description>0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_BIT_ORDER</name>
+              <description>I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_EN</name>
+              <description>1: Enable I2S TDM Tx mode . 0: Disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_PDM_EN</name>
+              <description>1: Enable I2S PDM Tx mode . 0: Disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CHAN_MOD</name>
+              <description>I2S transmitter channel mode configuration bits.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_SIG_LOOPBACK</name>
+              <description>Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_RX_CONF1</name>
+          <description>I2S RX configure register 1</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x2F3DE300</resetValue>
+          <fields>
+            <field>
+              <name>I2S_RX_TDM_WS_WIDTH</name>
+              <description>The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in receiver mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_HALF_SAMPLE_BITS</name>
+              <description>I2S Rx half sample bits -1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_CHAN_BITS</name>
+              <description>The Rx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_MSB_SHIFT</name>
+              <description>Set this bit to enable receiver in Phillips standard mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_TX_CONF1</name>
+          <description>I2S TX configure register 1</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x6F3DE300</resetValue>
+          <fields>
+            <field>
+              <name>I2S_TX_TDM_WS_WIDTH</name>
+              <description>The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_BCK_DIV_NUM</name>
+              <description>Bit clock configuration bits in transmitter mode.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_BITS_MOD</name>
+              <description>Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_HALF_SAMPLE_BITS</name>
+              <description>I2S Tx half sample bits -1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN_BITS</name>
+              <description>The Tx bit number for each channel minus 1in TDM mode.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_MSB_SHIFT</name>
+              <description>Set this bit to enable transmitter in Phillips standard mode</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_BCK_NO_DLY</name>
+              <description>1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_RX_CLKM_CONF</name>
+          <description>I2S RX clock configure register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>I2S_RX_CLKM_DIV_NUM</name>
+              <description>Integral I2S clock divider value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLK_ACTIVE</name>
+              <description>I2S Rx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLK_SEL</name>
+              <description>Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_MCLK_SEL</name>
+              <description>0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_TX_CLKM_CONF</name>
+          <description>I2S TX clock configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>I2S_TX_CLKM_DIV_NUM</name>
+              <description>Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b &lt;= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLK_ACTIVE</name>
+              <description>I2S Tx module clock enable signal.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLK_SEL</name>
+              <description>Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_RX_CLKM_DIV_CONF</name>
+          <description>I2S RX module clock divider configure register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>I2S_RX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_TX_CLKM_DIV_CONF</name>
+          <description>I2S TX module clock divider configure register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000200</resetValue>
+          <fields>
+            <field>
+              <name>I2S_TX_CLKM_DIV_Z</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLKM_DIV_Y</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLKM_DIV_X</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_CLKM_DIV_YN1</name>
+              <description>For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_RX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>I2S_RX_TDM_PDM_CHAN0_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_PDM_CHAN1_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_PDM_CHAN2_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_PDM_CHAN3_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_PDM_CHAN4_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_PDM_CHAN5_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_PDM_CHAN6_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_PDM_CHAN7_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_TX_TDM_CTRL</name>
+          <description>I2S TX TDM mode control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FFFF</resetValue>
+          <fields>
+            <field>
+              <name>I2S_TX_TDM_CHAN0_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN1_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN2_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN3_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN4_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN5_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN6_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN7_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN8_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN9_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN10_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN11_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN12_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN13_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN14_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_CHAN15_EN</name>
+              <description>1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_TOT_CHAN_NUM</name>
+              <description>The total channel number of I2S TX TDM mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_TDM_SKIP_MSK_EN</name>
+              <description>When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_RX_TIMING</name>
+          <description>I2S RX timing control register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S_RX_SD_IN_DM</name>
+              <description>The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_WS_OUT_DM</name>
+              <description>The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_WS_IN_DM</name>
+              <description>The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RX_BCK_IN_DM</name>
+              <description>The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_TX_TIMING</name>
+          <description>I2S TX timing control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S_TX_SD_OUT_DM</name>
+              <description>The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_SD1_OUT_DM</name>
+              <description>The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_WS_OUT_DM</name>
+              <description>The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_BCK_OUT_DM</name>
+              <description>The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_WS_IN_DM</name>
+              <description>The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TX_BCK_IN_DM</name>
+              <description>The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_LC_HUNG_CONF</name>
+          <description>I2S HUNG configure register.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000810</resetValue>
+          <fields>
+            <field>
+              <name>I2S_LC_FIFO_TIMEOUT</name>
+              <description>the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_LC_FIFO_TIMEOUT_SHIFT</name>
+              <description>The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_LC_FIFO_TIMEOUT_ENA</name>
+              <description>The enable bit for FIFO timeout</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_RXEOF_NUM</name>
+          <description>I2S RX data number control register.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000040</resetValue>
+          <fields>
+            <field>
+              <name>I2S_RX_EOF_NUM</name>
+              <description>The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_CONF_SIGLE_DATA</name>
+          <description>I2S signal data register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2S_SINGLE_DATA</name>
+              <description>The configured constant channel data to be sent out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_STATE</name>
+          <description>I2S TX status register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>I2S_TX_IDLE</name>
+              <description>1: i2s_tx is idle state. 0: i2s_tx is working.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02009070</resetValue>
+          <fields>
+            <field>
+              <name>I2S_DATE</name>
+              <description>I2S version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>INTERRUPT_CORE0</name>
+      <description>Interrupt Core</description>
+      <groupName>INTERRUPT_CORE0</groupName>
+      <baseAddress>0x600C2000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1A4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>WIFI_MAC</name>
+        <value>0</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_NMI</name>
+        <value>1</value>
+      </interrupt>
+      <interrupt>
+        <name>WIFI_BB</name>
+        <value>2</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_MAC</name>
+        <value>3</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_BB</name>
+        <value>4</value>
+      </interrupt>
+      <interrupt>
+        <name>BT_BB_NMI</name>
+        <value>5</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBT</name>
+        <value>6</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBLE</name>
+        <value>7</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBT_NMI</name>
+        <value>8</value>
+      </interrupt>
+      <interrupt>
+        <name>RWBLE_NMI</name>
+        <value>9</value>
+      </interrupt>
+      <interrupt>
+        <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE</name>
+        <value>85</value>
+      </interrupt>
+      <interrupt>
+        <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE</name>
+        <value>86</value>
+      </interrupt>
+      <interrupt>
+        <name>CORE_0_PIF_PMS_MONITOR_VIOLATE</name>
+        <value>87</value>
+      </interrupt>
+      <interrupt>
+        <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE</name>
+        <value>88</value>
+      </interrupt>
+      <interrupt>
+        <name>CACHE_CORE0_ACS</name>
+        <value>94</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>PRO_MAC_INTR_MAP</name>
+          <description>mac interrupt configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>MAC_INTR_MAP</name>
+              <description>this register used to map mac interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAC_NMI_MAP</name>
+          <description>mac_nmi interrupt configuration register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>MAC_NMI_MAP</name>
+              <description>this register used to map_nmi interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWR_INTR_MAP</name>
+          <description>pwr interrupt configuration register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWR_INTR_MAP</name>
+              <description>this register used to map pwr interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BB_INT_MAP</name>
+          <description>bb interrupt configuration register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BB_INT_MAP</name>
+              <description>this register used to map bb interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_MAC_INT_MAP</name>
+          <description>bb_mac interrupt configuration register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BT_MAC_INT_MAP</name>
+              <description>this register used to map bb_mac interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_INT_MAP</name>
+          <description>bt_bb interrupt configuration register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BT_BB_INT_MAP</name>
+              <description>this register used to map bt_bb interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_NMI_MAP</name>
+          <description>bt_bb_nmi interrupt configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BT_BB_NMI_MAP</name>
+              <description>this register used to map bb_bt_nmi interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBT_IRQ_MAP</name>
+          <description>rwbt_irq interrupt configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RWBT_IRQ_MAP</name>
+              <description>this register used to map rwbt_irq interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBLE_IRQ_MAP</name>
+          <description>rwble_irq interrupt configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RWBLE_IRQ_MAP</name>
+              <description>this register used to map rwble_irq interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBT_NMI_MAP</name>
+          <description>rwbt_nmi interrupt configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RWBT_NMI_MAP</name>
+              <description>this register used to map mac rwbt_nmi to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBLE_NMI_MAP</name>
+          <description>rwble_nmi interrupt configuration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RWBLE_NMI_MAP</name>
+              <description>this register used to map rwble_nmi interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_MST_INT_MAP</name>
+          <description>i2c_mst interrupt configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2C_MST_INT_MAP</name>
+              <description>this register used to map i2c_mst interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0_INTR_MAP</name>
+          <description>slc0 interrupt configuration register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_INTR_MAP</name>
+              <description>this register used to map slc0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1_INTR_MAP</name>
+          <description>slc1 interrupt configuration register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SLC1_INTR_MAP</name>
+              <description>this register used to map slc1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UHCI0_INTR_MAP</name>
+          <description>uhci0 interrupt configuration register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UHCI0_INTR_MAP</name>
+              <description>this register used to map uhci0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UHCI1_INTR_MAP</name>
+          <description>uhci1 interrupt configuration register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UHCI1_INTR_MAP</name>
+              <description>this register used to map uhci1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_MAP</name>
+          <description>gpio_interrupt_pro interrupt configuration register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_MAP</name>
+              <description>this register used to map gpio_interrupt_pro interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+          <description>gpio_interrupt_pro_nmi interrupt configuration register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+              <description>this register used to map gpio_interrupt_pro_nmi interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_APP_MAP</name>
+          <description>gpio_interrupt_app interrupt configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_APP_MAP</name>
+              <description>this register used to map gpio_interrupt_app interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_APP_NMI_MAP</name>
+          <description>gpio_interrupt_app_nmi interrupt configuration register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_APP_NMI_MAP</name>
+              <description>this register used to map gpio_interrupt_app_nmi interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_1_MAP</name>
+          <description>spi_intr_1 interrupt configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_INTR_1_MAP</name>
+              <description>this register used to map spi_intr_1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_2_MAP</name>
+          <description>spi_intr_2 interrupt configuration register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_INTR_2_MAP</name>
+              <description>this register used to map spi_intr_2 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_3_MAP</name>
+          <description>spi_intr_3 interrupt configuration register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_INTR_3_MAP</name>
+              <description>this register used to map spi_intr_3 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_4_MAP</name>
+          <description>spi_intr_4 interrupt configuration register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_INTR_4_MAP</name>
+              <description>this register used to map spi_intr_4 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_CAM_INT_MAP</name>
+          <description>lcd_cam interrupt configuration register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>LCD_CAM_INT_MAP</name>
+              <description>this register used to map lcd_cam interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S0_INT_MAP</name>
+          <description>i2s0 interrupt configuration register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2S0_INT_MAP</name>
+              <description>this register used to map i2s0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S1_INT_MAP</name>
+          <description>i2s1 interrupt configuration register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2S1_INT_MAP</name>
+              <description>this register used to map i2s1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INTR_MAP</name>
+          <description>uart interrupt configuration register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UART_INTR_MAP</name>
+              <description>this register used to map uart interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART1_INTR_MAP</name>
+          <description>uart1 interrupt configuration register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UART1_INTR_MAP</name>
+              <description>this register used to map uart1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART2_INTR_MAP</name>
+          <description>uart2 interrupt configuration register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UART2_INTR_MAP</name>
+              <description>this register used to map uart2 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_HOST_INTERRUPT_MAP</name>
+          <description>sdio_host interrupt configuration register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_HOST_INTERRUPT_MAP</name>
+              <description>this register used to map sdio_host interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM0_INTR_MAP</name>
+          <description>pwm0 interrupt configuration register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWM0_INTR_MAP</name>
+              <description>this register used to map pwm0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM1_INTR_MAP</name>
+          <description>pwm1 interrupt configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWM1_INTR_MAP</name>
+              <description>this register used to map pwm1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM2_INTR_MAP</name>
+          <description>pwm2 interrupt configuration register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWM2_INTR_MAP</name>
+              <description>this register used to map pwm2 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM3_INTR_MAP</name>
+          <description>pwm3 interrupt configuration register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWM3_INTR_MAP</name>
+              <description>this register used to map pwm3 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LEDC_INT_MAP</name>
+          <description>ledc interrupt configuration register</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>LEDC_INT_MAP</name>
+              <description>this register used to map ledc interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EFUSE_INT_MAP</name>
+          <description>efuse interrupt configuration register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>EFUSE_INT_MAP</name>
+              <description>this register used to map efuse interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAN_INT_MAP</name>
+          <description>can interrupt configuration register</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CAN_INT_MAP</name>
+              <description>this register used to map can interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_INTR_MAP</name>
+          <description>usb interrupt configuration register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>USB_INTR_MAP</name>
+              <description>this register used to map usb interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_CORE_INTR_MAP</name>
+          <description>rtc_core interrupt configuration register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CORE_INTR_MAP</name>
+              <description>this register used to map rtc_core interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RMT_INTR_MAP</name>
+          <description>rmt interrupt configuration register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RMT_INTR_MAP</name>
+              <description>this register used to map rmt interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCNT_INTR_MAP</name>
+          <description>pcnt interrupt configuration register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PCNT_INTR_MAP</name>
+              <description>this register used to map pcnt interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_EXT0_INTR_MAP</name>
+          <description>i2c_ext0 interrupt configuration register</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2C_EXT0_INTR_MAP</name>
+              <description>this register used to map i2c_ext0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_EXT1_INTR_MAP</name>
+          <description>i2c_ext1 interrupt configuration register</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2C_EXT1_INTR_MAP</name>
+              <description>this register used to map i2c_ext1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI2_DMA_INT_MAP</name>
+          <description>spi2_dma interrupt configuration register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI2_DMA_INT_MAP</name>
+              <description>this register used to map spi2_dma interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI3_DMA_INT_MAP</name>
+          <description>spi3_dma interrupt configuration register</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI3_DMA_INT_MAP</name>
+              <description>this register used to map spi3_dma interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI4_DMA_INT_MAP</name>
+          <description>spi4_dma interrupt configuration register</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI4_DMA_INT_MAP</name>
+              <description>this register used to map spi4_dma interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDG_INT_MAP</name>
+          <description>wdg interrupt configuration register</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>WDG_INT_MAP</name>
+              <description>this register used to map wdg interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_INT1_MAP</name>
+          <description>timer_int1 interrupt configuration register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TIMER_INT1_MAP</name>
+              <description>this register used to map timer_int1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_INT2_MAP</name>
+          <description>timer_int2 interrupt configuration register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TIMER_INT2_MAP</name>
+              <description>this register used to map timer_int2 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_T0_INT_MAP</name>
+          <description>tg_t0 interrupt configuration register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG_T0_INT_MAP</name>
+              <description>this register used to map tg_t0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_T1_INT_MAP</name>
+          <description>tg_t1 interrupt configuration register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG_T1_INT_MAP</name>
+              <description>this register used to map tg_t1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_WDT_INT_MAP</name>
+          <description>tg_wdt interrupt configuration register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG_WDT_INT_MAP</name>
+              <description>this register used to map rg_wdt interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_T0_INT_MAP</name>
+          <description>tg1_t0 interrupt configuration register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG1_T0_INT_MAP</name>
+              <description>this register used to map tg1_t0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_T1_INT_MAP</name>
+          <description>tg1_t1 interrupt configuration register</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG1_T1_INT_MAP</name>
+              <description>this register used to map tg1_t1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_WDT_INT_MAP</name>
+          <description>tg1_wdt interrupt configuration register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG1_WDT_INT_MAP</name>
+              <description>this register used to map tg1_wdt interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_IA_INT_MAP</name>
+          <description>cache_ia interrupt configuration register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_IA_INT_MAP</name>
+              <description>this register used to map cache_ia interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET0_INT_MAP</name>
+          <description>systimer_target0 interrupt configuration register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET0_INT_MAP</name>
+              <description>this register used to map systimer_target0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET1_INT_MAP</name>
+          <description>systimer_target1 interrupt configuration register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET1_INT_MAP</name>
+              <description>this register used to map systimer_target1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET2_INT_MAP</name>
+          <description>systimer_target2 interrupt configuration register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET2_INT_MAP</name>
+              <description>this register used to map systimer_target2 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REJECT_INTR_MAP</name>
+          <description>spi_mem_reject interrupt configuration register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_INTR_MAP</name>
+              <description>this register used to map spi_mem_reject interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_PRELOAD_INT_MAP</name>
+          <description>dcache_prelaod interrupt configuration register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_PRELOAD_INT_MAP</name>
+              <description>this register used to map dcache_prelaod interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_INT_MAP</name>
+          <description>icache_preload interrupt configuration register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_INT_MAP</name>
+              <description>this register used to map icache_preload interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_SYNC_INT_MAP</name>
+          <description>dcache_sync interrupt configuration register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_SYNC_INT_MAP</name>
+              <description>this register used to map dcache_sync interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_INT_MAP</name>
+          <description>icache_sync interrupt configuration register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_INT_MAP</name>
+              <description>this register used to map icache_sync interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADC_INT_MAP</name>
+          <description>apb_adc interrupt configuration register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APB_ADC_INT_MAP</name>
+              <description>this register used to map apb_adc interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH0_INT_MAP</name>
+          <description>dma_in_ch0 interrupt configuration register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH0_INT_MAP</name>
+              <description>this register used to map dma_in_ch0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH1_INT_MAP</name>
+          <description>dma_in_ch1 interrupt configuration register</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH1_INT_MAP</name>
+              <description>this register used to map dma_in_ch1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH2_INT_MAP</name>
+          <description>dma_in_ch2 interrupt configuration register</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH2_INT_MAP</name>
+              <description>this register used to map dma_in_ch2 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH3_INT_MAP</name>
+          <description>dma_in_ch3 interrupt configuration register</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH3_INT_MAP</name>
+              <description>this register used to map dma_in_ch3 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH4_INT_MAP</name>
+          <description>dma_in_ch4 interrupt configuration register</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH4_INT_MAP</name>
+              <description>this register used to map dma_in_ch4 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH0_INT_MAP</name>
+          <description>dma_out_ch0 interrupt configuration register</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH0_INT_MAP</name>
+              <description>this register used to map dma_out_ch0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH1_INT_MAP</name>
+          <description>dma_out_ch1 interrupt configuration register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH1_INT_MAP</name>
+              <description>this register used to map dma_out_ch1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH2_INT_MAP</name>
+          <description>dma_out_ch2 interrupt configuration register</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH2_INT_MAP</name>
+              <description>this register used to map dma_out_ch2 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH3_INT_MAP</name>
+          <description>dma_out_ch3 interrupt configuration register</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH3_INT_MAP</name>
+              <description>this register used to map dma_out_ch3 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH4_INT_MAP</name>
+          <description>dma_out_ch4 interrupt configuration register</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH4_INT_MAP</name>
+              <description>this register used to map dma_out_ch4 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_INT_MAP</name>
+          <description>rsa interrupt configuration register</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RSA_INT_MAP</name>
+              <description>this register used to map rsa interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AES_INT_MAP</name>
+          <description>aes interrupt configuration register</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>AES_INT_MAP</name>
+              <description>this register used to map aes interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA_INT_MAP</name>
+          <description>sha interrupt configuration register</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SHA_INT_MAP</name>
+              <description>this register used to map sha interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0_MAP</name>
+          <description>cpu_intr_from_cpu_0 interrupt configuration register</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0_MAP</name>
+              <description>this register used to map cpu_intr_from_cpu_0 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1_MAP</name>
+          <description>cpu_intr_from_cpu_1 interrupt configuration register</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1_MAP</name>
+              <description>this register used to map cpu_intr_from_cpu_1 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2_MAP</name>
+          <description>cpu_intr_from_cpu_2 interrupt configuration register</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2_MAP</name>
+              <description>this register used to map cpu_intr_from_cpu_2 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3_MAP</name>
+          <description>cpu_intr_from_cpu_3 interrupt configuration register</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3_MAP</name>
+              <description>this register used to map cpu_intr_from_cpu_3 interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ASSIST_DEBUG_INTR_MAP</name>
+          <description>assist_debug interrupt configuration register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>ASSIST_DEBUG_INTR_MAP</name>
+              <description>this register used to map assist_debug interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>dma_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map dma_pms_monitor_violatile interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core0_IRam0_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core0_DRam0_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core0_PIF_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+          <description>core0_PIF_pms_monitor_violatile_size interrupt configuration register</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+              <description>this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core1_IRam0_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core1_DRam0_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core1_PIF_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+          <description>core1_PIF_pms_monitor_violatile_size interrupt configuration register</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+              <description>this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_PMS_VIOLATE_INTR_MAP</name>
+          <description>backup_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_PMS_VIOLATE_INTR_MAP</name>
+              <description>this register used to map backup_pms_monitor_violatile interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CORE0_ACS_INT_MAP</name>
+          <description>cache_core0_acs interrupt configuration register</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_CORE0_ACS_INT_MAP</name>
+              <description>this register used to map cache_core0_acs interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CORE1_ACS_INT_MAP</name>
+          <description>cache_core1_acs interrupt configuration register</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_CORE1_ACS_INT_MAP</name>
+              <description>this register used to map cache_core1_acs interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_DEVICE_INT_MAP</name>
+          <description>usb_device interrupt configuration register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>USB_DEVICE_INT_MAP</name>
+              <description>this register used to map usb_device interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_MAP</name>
+          <description>peri_backup interrupt configuration register</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_INT_MAP</name>
+              <description>this register used to map peri_backup interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_EXTMEM_REJECT_INT_MAP</name>
+          <description>dma_extmem_reject interrupt configuration register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_EXTMEM_REJECT_INT_MAP</name>
+              <description>this register used to map dma_extmem_reject interrupt to one of core0's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_0</name>
+          <description>interrupt status register</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_0</name>
+              <description>this register store the status of the first 32 interrupt source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_1</name>
+          <description>interrupt status register</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_1</name>
+              <description>this register store the status of the first 32 interrupt source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_2</name>
+          <description>interrupt status register</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_2</name>
+              <description>this register store the status of the first 32 interrupt source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PRO_INTR_STATUS_3</name>
+          <description>interrupt status register</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_3</name>
+              <description>this register store the status of the first 32 interrupt source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock gate register</description>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>REG_CLK_EN</name>
+              <description>this register uesd to control clock-gating interupt martrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0x7FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02012300</resetValue>
+          <fields>
+            <field>
+              <name>INTERRUPT_REG_DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>INTERRUPT_CORE1</name>
+      <description>Interrupt Core</description>
+      <groupName>INTERRUPT_CORE1</groupName>
+      <baseAddress>0x600C2800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x1A4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE</name>
+        <value>89</value>
+      </interrupt>
+      <interrupt>
+        <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE</name>
+        <value>90</value>
+      </interrupt>
+      <interrupt>
+        <name>CORE_1_PIF_PMS_MONITOR_VIOLATE</name>
+        <value>91</value>
+      </interrupt>
+      <interrupt>
+        <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE</name>
+        <value>92</value>
+      </interrupt>
+      <interrupt>
+        <name>CACHE_CORE1_ACS</name>
+        <value>95</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>APP_MAC_INTR_MAP</name>
+          <description>mac interrupt configuration register</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>MAC_INTR_MAP</name>
+              <description>this register used to map mac interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MAC_NMI_MAP</name>
+          <description>mac_nmi interrupt configuration register</description>
+          <addressOffset>0x804</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>MAC_NMI_MAP</name>
+              <description>this register used to map_nmi interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWR_INTR_MAP</name>
+          <description>pwr interrupt configuration register</description>
+          <addressOffset>0x808</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWR_INTR_MAP</name>
+              <description>this register used to map pwr interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BB_INT_MAP</name>
+          <description>bb interrupt configuration register</description>
+          <addressOffset>0x80C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BB_INT_MAP</name>
+              <description>this register used to map bb interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_MAC_INT_MAP</name>
+          <description>bb_mac interrupt configuration register</description>
+          <addressOffset>0x810</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BT_MAC_INT_MAP</name>
+              <description>this register used to map bb_mac interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_INT_MAP</name>
+          <description>bt_bb interrupt configuration register</description>
+          <addressOffset>0x814</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BT_BB_INT_MAP</name>
+              <description>this register used to map bt_bb interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_BB_NMI_MAP</name>
+          <description>bt_bb_nmi interrupt configuration register</description>
+          <addressOffset>0x818</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BT_BB_NMI_MAP</name>
+              <description>this register used to map bb_bt_nmi interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBT_IRQ_MAP</name>
+          <description>rwbt_irq interrupt configuration register</description>
+          <addressOffset>0x81C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RWBT_IRQ_MAP</name>
+              <description>this register used to map rwbt_irq interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBLE_IRQ_MAP</name>
+          <description>rwble_irq interrupt configuration register</description>
+          <addressOffset>0x820</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RWBLE_IRQ_MAP</name>
+              <description>this register used to map rwble_irq interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBT_NMI_MAP</name>
+          <description>rwbt_nmi interrupt configuration register</description>
+          <addressOffset>0x824</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RWBT_NMI_MAP</name>
+              <description>this register used to map rwbt_nmi interupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RWBLE_NMI_MAP</name>
+          <description>rwble_nmi interrupt configuration register</description>
+          <addressOffset>0x828</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RWBLE_NMI_MAP</name>
+              <description>this register used to map rwble_nmi interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_MST_INT_MAP</name>
+          <description>i2c_mst interrupt configuration register</description>
+          <addressOffset>0x82C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2C_MST_INT_MAP</name>
+              <description>this register used to map i2c_mst interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC0_INTR_MAP</name>
+          <description>slc0 interrupt configuration register</description>
+          <addressOffset>0x830</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SLC0_INTR_MAP</name>
+              <description>this register used to map slc0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC1_INTR_MAP</name>
+          <description>slc1 interrupt configuration register</description>
+          <addressOffset>0x834</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SLC1_INTR_MAP</name>
+              <description>this register used to map slc1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UHCI0_INTR_MAP</name>
+          <description>uhci0 interrupt configuration register</description>
+          <addressOffset>0x838</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UHCI0_INTR_MAP</name>
+              <description>this register used to map uhci0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UHCI1_INTR_MAP</name>
+          <description>uhci1 interrupt configuration register</description>
+          <addressOffset>0x83C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UHCI1_INTR_MAP</name>
+              <description>this register used to map uhci1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_MAP</name>
+          <description>gpio_interrupt_pro interrupt configuration register</description>
+          <addressOffset>0x840</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_MAP</name>
+              <description>this register used to map gpio_interrupt_pro interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+          <description>gpio_interrupt_pro_nmi interrupt configuration register</description>
+          <addressOffset>0x844</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_PRO_NMI_MAP</name>
+              <description>this register used to map gpio_interrupt_pro_nmi interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_APP_MAP</name>
+          <description>gpio_interrupt_app interrupt configuration register</description>
+          <addressOffset>0x848</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_APP_MAP</name>
+              <description>this register used to map gpio_interrupt_app interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_INTERRUPT_APP_NMI_MAP</name>
+          <description>gpio_interrupt_app_nmi interrupt configuration register</description>
+          <addressOffset>0x84C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_INTERRUPT_APP_NMI_MAP</name>
+              <description>this register used to map gpio_interrupt_app_nmi interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_1_MAP</name>
+          <description>spi_intr_1 interrupt configuration register</description>
+          <addressOffset>0x850</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_INTR_1_MAP</name>
+              <description>this register used to map spi_intr_1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_2_MAP</name>
+          <description>spi_intr_2 interrupt configuration register</description>
+          <addressOffset>0x854</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_INTR_2_MAP</name>
+              <description>this register used to map spi_intr_2 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_3_MAP</name>
+          <description>spi_intr_3 interrupt configuration register</description>
+          <addressOffset>0x858</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_INTR_3_MAP</name>
+              <description>this register used to map spi_intr_3 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_INTR_4_MAP</name>
+          <description>spi_intr_4 interrupt configuration register</description>
+          <addressOffset>0x85C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_INTR_4_MAP</name>
+              <description>this register used to map spi_intr_4 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_CAM_INT_MAP</name>
+          <description>lcd_cam interrupt configuration register</description>
+          <addressOffset>0x860</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>LCD_CAM_INT_MAP</name>
+              <description>this register used to map lcd_cam interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S0_INT_MAP</name>
+          <description>i2s0 interrupt configuration register</description>
+          <addressOffset>0x864</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2S0_INT_MAP</name>
+              <description>this register used to map i2s0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S1_INT_MAP</name>
+          <description>i2s1 interrupt configuration register</description>
+          <addressOffset>0x868</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2S1_INT_MAP</name>
+              <description>this register used to map i2s1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INTR_MAP</name>
+          <description>uart interrupt configuration register</description>
+          <addressOffset>0x86C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UART_INTR_MAP</name>
+              <description>this register used to map uart interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART1_INTR_MAP</name>
+          <description>uart1 interrupt configuration register</description>
+          <addressOffset>0x870</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UART1_INTR_MAP</name>
+              <description>this register used to map uart1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART2_INTR_MAP</name>
+          <description>uart2 interrupt configuration register</description>
+          <addressOffset>0x874</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>UART2_INTR_MAP</name>
+              <description>this register used to map uart2 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_HOST_INTERRUPT_MAP</name>
+          <description>sdio_host interrupt configuration register</description>
+          <addressOffset>0x878</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_HOST_INTERRUPT_MAP</name>
+              <description>this register used to map sdio_host interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM0_INTR_MAP</name>
+          <description>pwm0 interrupt configuration register</description>
+          <addressOffset>0x87C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWM0_INTR_MAP</name>
+              <description>this register used to map pwm0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM1_INTR_MAP</name>
+          <description>pwm1 interrupt configuration register</description>
+          <addressOffset>0x880</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWM1_INTR_MAP</name>
+              <description>this register used to map pwm1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM2_INTR_MAP</name>
+          <description>pwm2 interrupt configuration register</description>
+          <addressOffset>0x884</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWM2_INTR_MAP</name>
+              <description>this register used to map pwm2 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWM3_INTR_MAP</name>
+          <description>pwm3 interrupt configuration register</description>
+          <addressOffset>0x888</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PWM3_INTR_MAP</name>
+              <description>this register used to map pwm3 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LEDC_INT_MAP</name>
+          <description>ledc interrupt configuration register</description>
+          <addressOffset>0x88C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>LEDC_INT_MAP</name>
+              <description>this register used to map ledc interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EFUSE_INT_MAP</name>
+          <description>efuse interrupt configuration register</description>
+          <addressOffset>0x890</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>EFUSE_INT_MAP</name>
+              <description>this register used to map efuse interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAN_INT_MAP</name>
+          <description>can interrupt configuration register</description>
+          <addressOffset>0x894</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CAN_INT_MAP</name>
+              <description>this register used to map can interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_INTR_MAP</name>
+          <description>usb interrupt configuration register</description>
+          <addressOffset>0x898</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>USB_INTR_MAP</name>
+              <description>this register used to map usb interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_CORE_INTR_MAP</name>
+          <description>rtc_core interrupt configuration register</description>
+          <addressOffset>0x89C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CORE_INTR_MAP</name>
+              <description>this register used to map rtc_core interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RMT_INTR_MAP</name>
+          <description>rmt interrupt configuration register</description>
+          <addressOffset>0x8A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RMT_INTR_MAP</name>
+              <description>this register used to map rmt interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCNT_INTR_MAP</name>
+          <description>pcnt interrupt configuration register</description>
+          <addressOffset>0x8A4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PCNT_INTR_MAP</name>
+              <description>this register used to map pcnt interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_EXT0_INTR_MAP</name>
+          <description>i2c_ext0 interrupt configuration register</description>
+          <addressOffset>0x8A8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2C_EXT0_INTR_MAP</name>
+              <description>this register used to map i2c_ext0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2C_EXT1_INTR_MAP</name>
+          <description>i2c_ext1 interrupt configuration register</description>
+          <addressOffset>0x8AC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>I2C_EXT1_INTR_MAP</name>
+              <description>this register used to map i2c_ext1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI2_DMA_INT_MAP</name>
+          <description>spi2_dma interrupt configuration register</description>
+          <addressOffset>0x8B0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI2_DMA_INT_MAP</name>
+              <description>this register used to map spi2_dma interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI3_DMA_INT_MAP</name>
+          <description>spi3_dma interrupt configuration register</description>
+          <addressOffset>0x8B4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI3_DMA_INT_MAP</name>
+              <description>this register used to map spi3_dma interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI4_DMA_INT_MAP</name>
+          <description>spi4_dma interrupt configuration register</description>
+          <addressOffset>0x8B8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI4_DMA_INT_MAP</name>
+              <description>this register used to map spi4_dma interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDG_INT_MAP</name>
+          <description>wdg interrupt configuration register</description>
+          <addressOffset>0x8BC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>WDG_INT_MAP</name>
+              <description>this register used to map wdg interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_INT1_MAP</name>
+          <description>timer_int1 interrupt configuration register</description>
+          <addressOffset>0x8C0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TIMER_INT1_MAP</name>
+              <description>this register used to map timer_int1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_INT2_MAP</name>
+          <description>timer_int2 interrupt configuration register</description>
+          <addressOffset>0x8C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TIMER_INT2_MAP</name>
+              <description>this register used to map timer_int2 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_T0_INT_MAP</name>
+          <description>tg_t0 interrupt configuration register</description>
+          <addressOffset>0x8C8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG_T0_INT_MAP</name>
+              <description>this register used to map tg_t0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_T1_INT_MAP</name>
+          <description>tg_t1 interrupt configuration register</description>
+          <addressOffset>0x8CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG_T1_INT_MAP</name>
+              <description>this register used to map tg_t1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG_WDT_INT_MAP</name>
+          <description>tg_wdt interrupt configuration register</description>
+          <addressOffset>0x8D0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG_WDT_INT_MAP</name>
+              <description>this register used to map rg_wdt interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_T0_INT_MAP</name>
+          <description>tg1_t0 interrupt configuration register</description>
+          <addressOffset>0x8D4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG1_T0_INT_MAP</name>
+              <description>this register used to map tg1_t0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_T1_INT_MAP</name>
+          <description>tg1_t1 interrupt configuration register</description>
+          <addressOffset>0x8D8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG1_T1_INT_MAP</name>
+              <description>this register used to map tg1_t1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TG1_WDT_INT_MAP</name>
+          <description>tg1_wdt interrupt configuration register</description>
+          <addressOffset>0x8DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>TG1_WDT_INT_MAP</name>
+              <description>this register used to map tg1_wdt interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_IA_INT_MAP</name>
+          <description>cache_ia interrupt configuration register</description>
+          <addressOffset>0x8E0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_IA_INT_MAP</name>
+              <description>this register used to map cache_ia interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET0_INT_MAP</name>
+          <description>systimer_target0 interrupt configuration register</description>
+          <addressOffset>0x8E4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET0_INT_MAP</name>
+              <description>this register used to map systimer_target0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET1_INT_MAP</name>
+          <description>systimer_target1 interrupt configuration register</description>
+          <addressOffset>0x8E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET1_INT_MAP</name>
+              <description>this register used to map systimer_target1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSTIMER_TARGET2_INT_MAP</name>
+          <description>systimer_target2 interrupt configuration register</description>
+          <addressOffset>0x8EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_TARGET2_INT_MAP</name>
+              <description>this register used to map systimer_target2 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_MEM_REJECT_INTR_MAP</name>
+          <description>spi_mem_reject interrupt configuration register</description>
+          <addressOffset>0x8F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SPI_MEM_REJECT_INTR_MAP</name>
+              <description>this register used to map spi_mem_reject interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_PRELOAD_INT_MAP</name>
+          <description>dcache_prelaod interrupt configuration register</description>
+          <addressOffset>0x8F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_PRELOAD_INT_MAP</name>
+              <description>this register used to map dcache_prelaod interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_PRELOAD_INT_MAP</name>
+          <description>icache_preload interrupt configuration register</description>
+          <addressOffset>0x8F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_PRELOAD_INT_MAP</name>
+              <description>this register used to map icache_preload interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCACHE_SYNC_INT_MAP</name>
+          <description>dcache_sync interrupt configuration register</description>
+          <addressOffset>0x8FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DCACHE_SYNC_INT_MAP</name>
+              <description>this register used to map dcache_sync interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ICACHE_SYNC_INT_MAP</name>
+          <description>icache_sync interrupt configuration register</description>
+          <addressOffset>0x900</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_SYNC_INT_MAP</name>
+              <description>this register used to map icache_sync interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADC_INT_MAP</name>
+          <description>apb_adc interrupt configuration register</description>
+          <addressOffset>0x904</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>APB_ADC_INT_MAP</name>
+              <description>this register used to map apb_adc interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH0_INT_MAP</name>
+          <description>dma_in_ch0 interrupt configuration register</description>
+          <addressOffset>0x908</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH0_INT_MAP</name>
+              <description>this register used to map dma_in_ch0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH1_INT_MAP</name>
+          <description>dma_in_ch1 interrupt configuration register</description>
+          <addressOffset>0x90C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH1_INT_MAP</name>
+              <description>this register used to map dma_in_ch1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH2_INT_MAP</name>
+          <description>dma_in_ch2 interrupt configuration register</description>
+          <addressOffset>0x910</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH2_INT_MAP</name>
+              <description>this register used to map dma_in_ch2 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH3_INT_MAP</name>
+          <description>dma_in_ch3 interrupt configuration register</description>
+          <addressOffset>0x914</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH3_INT_MAP</name>
+              <description>this register used to map dma_in_ch3 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_IN_CH4_INT_MAP</name>
+          <description>dma_in_ch4 interrupt configuration register</description>
+          <addressOffset>0x918</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_IN_CH4_INT_MAP</name>
+              <description>this register used to map dma_in_ch4 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH0_INT_MAP</name>
+          <description>dma_out_ch0 interrupt configuration register</description>
+          <addressOffset>0x91C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH0_INT_MAP</name>
+              <description>this register used to map dma_out_ch0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH1_INT_MAP</name>
+          <description>dma_out_ch1 interrupt configuration register</description>
+          <addressOffset>0x920</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH1_INT_MAP</name>
+              <description>this register used to map dma_out_ch1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH2_INT_MAP</name>
+          <description>dma_out_ch2 interrupt configuration register</description>
+          <addressOffset>0x924</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH2_INT_MAP</name>
+              <description>this register used to map dma_out_ch2 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH3_INT_MAP</name>
+          <description>dma_out_ch3 interrupt configuration register</description>
+          <addressOffset>0x928</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH3_INT_MAP</name>
+              <description>this register used to map dma_out_ch3 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_OUT_CH4_INT_MAP</name>
+          <description>dma_out_ch4 interrupt configuration register</description>
+          <addressOffset>0x92C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUT_CH4_INT_MAP</name>
+              <description>this register used to map dma_out_ch4 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_INT_MAP</name>
+          <description>rsa interrupt configuration register</description>
+          <addressOffset>0x930</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>RSA_INT_MAP</name>
+              <description>this register used to map rsa interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AES_INT_MAP</name>
+          <description>aes interrupt configuration register</description>
+          <addressOffset>0x934</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>AES_INT_MAP</name>
+              <description>this register used to map aes interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SHA_INT_MAP</name>
+          <description>sha interrupt configuration register</description>
+          <addressOffset>0x938</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>SHA_INT_MAP</name>
+              <description>this register used to map sha interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0_MAP</name>
+          <description>cpu_intr_from_cpu_0 interrupt configuration register</description>
+          <addressOffset>0x93C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0_MAP</name>
+              <description>this register used to map cpu_intr_from_cpu_0 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1_MAP</name>
+          <description>cpu_intr_from_cpu_1 interrupt configuration register</description>
+          <addressOffset>0x940</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1_MAP</name>
+              <description>this register used to map cpu_intr_from_cpu_1 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2_MAP</name>
+          <description>cpu_intr_from_cpu_2 interrupt configuration register</description>
+          <addressOffset>0x944</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2_MAP</name>
+              <description>this register used to map cpu_intr_from_cpu_2 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3_MAP</name>
+          <description>cpu_intr_from_cpu_3 interrupt configuration register</description>
+          <addressOffset>0x948</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3_MAP</name>
+              <description>this register used to map cpu_intr_from_cpu_3 interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ASSIST_DEBUG_INTR_MAP</name>
+          <description>assist_debug interrupt configuration register</description>
+          <addressOffset>0x94C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>ASSIST_DEBUG_INTR_MAP</name>
+              <description>this register used to map assist_debug interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>dma_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x950</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map dma_pms_monitor_violatile interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core0_IRam0_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x954</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core0_DRam0_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x958</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core0_PIF_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x95C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+          <description>core0_PIF_pms_monitor_violatile_size interrupt configuration register</description>
+          <addressOffset>0x960</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+              <description>this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core1_IRam0_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x964</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core1_DRam0_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x968</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+          <description>core1_PIF_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x96C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP</name>
+              <description>this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+          <description>core1_PIF_pms_monitor_violatile_size interrupt configuration register</description>
+          <addressOffset>0x970</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP</name>
+              <description>this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_PMS_VIOLATE_INTR_MAP</name>
+          <description>backup_pms_monitor_violatile interrupt configuration register</description>
+          <addressOffset>0x974</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_PMS_VIOLATE_INTR_MAP</name>
+              <description>this register used to map backup_pms_monitor_violatile interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CORE0_ACS_INT_MAP</name>
+          <description>cache_core0_acs interrupt configuration register</description>
+          <addressOffset>0x978</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_CORE0_ACS_INT_MAP</name>
+              <description>this register used to map cache_core0_acs interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CORE1_ACS_INT_MAP</name>
+          <description>cache_core1_acs interrupt configuration register</description>
+          <addressOffset>0x97C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_CORE1_ACS_INT_MAP</name>
+              <description>this register used to map cache_core1_acs interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_DEVICE_INT_MAP</name>
+          <description>usb_device interrupt configuration register</description>
+          <addressOffset>0x980</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>USB_DEVICE_INT_MAP</name>
+              <description>this register used to map usb_device interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERI_BACKUP_INT_MAP</name>
+          <description>peri_backup interrupt configuration register</description>
+          <addressOffset>0x984</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_INT_MAP</name>
+              <description>this register used to map peri_backup interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_EXTMEM_REJECT_INT_MAP</name>
+          <description>dma_extmem_reject interrupt configuration register</description>
+          <addressOffset>0x988</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>DMA_EXTMEM_REJECT_INT_MAP</name>
+              <description>this register used to map dma_extmem_reject interrupt to one of core1's external interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INTR_STATUS_0</name>
+          <description>interrupt status register</description>
+          <addressOffset>0x98C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_0</name>
+              <description>this register store the status of the first 32 interrupt source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INTR_STATUS_1</name>
+          <description>interrupt status register</description>
+          <addressOffset>0x990</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_1</name>
+              <description>this register store the status of the first 32 interrupt source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INTR_STATUS_2</name>
+          <description>interrupt status register</description>
+          <addressOffset>0x994</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_2</name>
+              <description>this register store the status of the first 32 interrupt source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INTR_STATUS_3</name>
+          <description>interrupt status register</description>
+          <addressOffset>0x998</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTR_STATUS_3</name>
+              <description>this register store the status of the first 32 interrupt source</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>clock gate register</description>
+          <addressOffset>0x99C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>REG_CLK_EN</name>
+              <description>this register uesd to control clock-gating interupt martrix</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02012300</resetValue>
+          <fields>
+            <field>
+              <name>INTERRUPT_DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>IO_MUX</name>
+      <description>Input/Output Multiplexer</description>
+      <groupName>IO_MUX</groupName>
+      <baseAddress>0x60009000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xCC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>PIN_CTRL</name>
+          <description>Clock Output Configuration Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>CLK_OUT1</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT2</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_OUT3</name>
+              <description>If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>49</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>GPIO%s</name>
+          <description>IO MUX Configure Register for pad GPIO0</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000B00</resetValue>
+          <fields>
+            <field>
+              <name>MCU_OE</name>
+              <description>Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPD</name>
+              <description>Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_WPU</name>
+              <description>Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_IE</name>
+              <description>Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPD</name>
+              <description>Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_WPU</name>
+              <description>Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_IE</name>
+              <description>Input enable of the pad. 1: input enabled; 0: input disabled.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_DRV</name>
+              <description>Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MCU_SEL</name>
+              <description>Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN</name>
+              <description>Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>IO MUX Version Control Register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01907160</resetValue>
+          <fields>
+            <field>
+              <name>REG_DATE</name>
+              <description>Version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LCD_CAM</name>
+      <description>Peripheral LCD_CAM</description>
+      <groupName>LCD_CAM</groupName>
+      <baseAddress>0x60041000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x48</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>LCD_CLOCK</name>
+          <description>LCD clock register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000843</resetValue>
+          <fields>
+            <field>
+              <name>LCD_CLKCNT_N</name>
+              <description>f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CLK_EQU_SYSCLK</name>
+              <description>1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CK_IDLE_EDGE</name>
+              <description>1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CK_OUT_EDGE</name>
+              <description>1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CLKM_DIV_NUM</name>
+              <description>Integral LCD clock divider value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CLKM_DIV_B</name>
+              <description>Fractional clock divider numerator value</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CLKM_DIV_A</name>
+              <description>Fractional clock divider denominator value</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CLK_SEL</name>
+              <description>Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAM_CTRL</name>
+          <description>Camera configuration register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000800</resetValue>
+          <fields>
+            <field>
+              <name>CAM_STOP_EN</name>
+              <description>Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_VSYNC_FILTER_THRES</name>
+              <description>Filter threshold value for CAM_VSYNC signal.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_UPDATE</name>
+              <description>1: Update Camera registers, will be cleared by hardware. 0 : Not care.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_BYTE_ORDER</name>
+              <description>1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_BIT_ORDER</name>
+              <description>1: invert data byte order, only valid in 2 byte mode. 0: Not change.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_LINE_INT_EN</name>
+              <description>1: Enable to generate CAM_HS_INT. 0: Disable.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_VS_EOF_EN</name>
+              <description>1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CLKM_DIV_NUM</name>
+              <description>Integral Camera clock divider value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CLKM_DIV_B</name>
+              <description>Fractional clock divider numerator value</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CLKM_DIV_A</name>
+              <description>Fractional clock divider denominator value</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CLK_SEL</name>
+              <description>Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAM_CTRL1</name>
+          <description>Camera configuration register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAM_REC_DATA_BYTELEN</name>
+              <description>Camera receive data byte length minus 1 to set DMA in_suc_eof_int.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_LINE_INT_NUM</name>
+              <description>The line number minus 1 to generate cam_hs_int.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CLK_INV</name>
+              <description>1: Invert  the input signal CAM_PCLK. 0: Not invert.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_VSYNC_FILTER_EN</name>
+              <description>1: Enable CAM_VSYNC filter function. 0: bypass.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_2BYTE_EN</name>
+              <description>1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_DE_INV</name>
+              <description>CAM_DE invert enable signal, valid in high level.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_HSYNC_INV</name>
+              <description>CAM_HSYNC invert enable signal, valid in high level.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_VSYNC_INV</name>
+              <description>CAM_VSYNC invert enable signal, valid in high level.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_VH_DE_MODE_EN</name>
+              <description>1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 the the same time.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_START</name>
+              <description>Camera module start signal.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_RESET</name>
+              <description>Camera module reset signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAM_AFIFO_RESET</name>
+              <description>Camera AFIFO reset signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAM_RGB_YUV</name>
+          <description>Camera configuration register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C00000</resetValue>
+          <fields>
+            <field>
+              <name>CAM_CONV_8BITS_DATA_INV</name>
+              <description>1:invert every two 8bits input data. 2. disabled.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CONV_YUV2YUV_MODE</name>
+              <description>0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CONV_YUV_MODE</name>
+              <description>0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CONV_PROTOCOL_MODE</name>
+              <description>0:BT601. 1:BT709.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CONV_DATA_OUT_MODE</name>
+              <description>LIMIT or FULL mode of Data out. 0: limit. 1: full</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CONV_DATA_IN_MODE</name>
+              <description>LIMIT or FULL mode of Data in. 0: limit. 1: full</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CONV_MODE_8BITS_ON</name>
+              <description>0: 16bits mode. 1: 8bits mode.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CONV_TRANS_MODE</name>
+              <description>0: YUV to RGB. 1: RGB to YUV.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_CONV_BYPASS</name>
+              <description>0: Bypass converter. 1: Enable converter.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_RGB_YUV</name>
+          <description>LCD configuration register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00C00000</resetValue>
+          <fields>
+            <field>
+              <name>LCD_CONV_8BITS_DATA_INV</name>
+              <description>1:invert every two 8bits input data. 2. disabled.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CONV_TXTORX</name>
+              <description>0: txtorx mode off. 1: txtorx mode on.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CONV_YUV2YUV_MODE</name>
+              <description>0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode, trans_mode must be set to 1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CONV_YUV_MODE</name>
+              <description>0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CONV_PROTOCOL_MODE</name>
+              <description>0:BT601. 1:BT709.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CONV_DATA_OUT_MODE</name>
+              <description>LIMIT or FULL mode of Data out. 0: limit. 1: full</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CONV_DATA_IN_MODE</name>
+              <description>LIMIT or FULL mode of Data in. 0: limit. 1: full</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CONV_MODE_8BITS_ON</name>
+              <description>0: 16bits mode. 1: 8bits mode.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CONV_TRANS_MODE</name>
+              <description>0: YUV to RGB. 1: RGB to YUV.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CONV_BYPASS</name>
+              <description>0: Bypass converter. 1: Enable converter.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_USER</name>
+          <description>LCD configuration register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>LCD_DOUT_CYCLELEN</name>
+              <description>The output data cycles minus 1 of LCD module.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_ALWAYS_OUT_EN</name>
+              <description>LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_8BITS_ORDER</name>
+              <description>1: invert every two data byte, valid in 1 byte mode. 0: Not change.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_UPDATE</name>
+              <description>1: Update LCD registers, will be cleared by hardware. 0 : Not care.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_BIT_ORDER</name>
+              <description>1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_BYTE_ORDER</name>
+              <description>1: invert data byte order, only valid in 2 byte mode. 0: Not change.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_2BYTE_EN</name>
+              <description>1: The bit number of output LCD data is 9~16.  0: The bit number of output LCD data is 0~8.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_DOUT</name>
+              <description>1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_DUMMY</name>
+              <description>1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CMD</name>
+              <description>1: Be able to send command in LCD sequence when LCD starts. 0: Disable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_START</name>
+              <description>LCD start sending data enable signal, valid in high level.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_RESET</name>
+              <description>The value of  command.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LCD_DUMMY_CYCLELEN</name>
+              <description>The dummy cycle length minus 1.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CMD_2_CYCLE_EN</name>
+              <description>The cycle length of command phase.  1: 2 cycles. 0: 1 cycle.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_MISC</name>
+          <description>LCD configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000D6</resetValue>
+          <fields>
+            <field>
+              <name>LCD_AFIFO_THRESHOLD_NUM</name>
+              <description>The awfull threshold number of lcd_afifo.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_VFK_CYCLELEN</name>
+              <description>The setup cycle length minus 1 in LCD non-RGB mode.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_VBK_CYCLELEN</name>
+              <description>The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_NEXT_FRAME_EN</name>
+              <description>1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_BK_EN</name>
+              <description>1: Enable blank region when LCD sends data out. 0: No blank region.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_AFIFO_RESET</name>
+              <description>LCD AFIFO reset signal.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LCD_CD_DATA_SET</name>
+              <description>1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD = reg_cd_idle_edge.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CD_DUMMY_SET</name>
+              <description>1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD = reg_cd_idle_edge.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CD_CMD_SET</name>
+              <description>1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD = reg_cd_idle_edge.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CD_IDLE_EDGE</name>
+              <description>The default value of LCD_CD.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_CTRL</name>
+          <description>LCD configuration register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_HB_FRONT</name>
+              <description>It is the horizontal blank front porch of a frame.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_VA_HEIGHT</name>
+              <description>It is the vertical active height of a frame.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_VT_HEIGHT</name>
+              <description>It is the vertical total height of a frame.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_RGB_MODE_EN</name>
+              <description>1: Enable reg mode input vsync, hsync, de. 0: Disable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_CTRL1</name>
+          <description>LCD configuration register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_VB_FRONT</name>
+              <description>It is the vertical blank front porch of a frame.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HA_WIDTH</name>
+              <description>It is the horizontal active width of a frame.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HT_WIDTH</name>
+              <description>It is the horizontal total width of a frame.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_CTRL2</name>
+          <description>LCD configuration register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010001</resetValue>
+          <fields>
+            <field>
+              <name>LCD_VSYNC_WIDTH</name>
+              <description>It is the position of LCD_VSYNC active pulse in a line.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_VSYNC_IDLE_POL</name>
+              <description>It is the idle value of LCD_VSYNC.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_DE_IDLE_POL</name>
+              <description>It is the idle value of LCD_DE.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HS_BLANK_EN</name>
+              <description>1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HSYNC_WIDTH</name>
+              <description>It is the position of LCD_HSYNC active pulse in a line.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HSYNC_IDLE_POL</name>
+              <description>It is the idle value of LCD_HSYNC.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HSYNC_POSITION</name>
+              <description>It is the position of LCD_HSYNC active pulse in a line.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_CMD_VAL</name>
+          <description>LCD configuration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_CMD_VALUE</name>
+              <description>The LCD write command value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_DLY_MODE</name>
+          <description>LCD configuration register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_CD_MODE</name>
+              <description>The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_DE_MODE</name>
+              <description>The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_HSYNC_MODE</name>
+              <description>The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_VSYNC_MODE</name>
+              <description>The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LCD_DATA_DOUT_MODE</name>
+          <description>LCD configuration register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DOUT0_MODE</name>
+              <description>The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT1_MODE</name>
+              <description>The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT2_MODE</name>
+              <description>The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT3_MODE</name>
+              <description>The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT4_MODE</name>
+              <description>The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT5_MODE</name>
+              <description>The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT6_MODE</name>
+              <description>The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT7_MODE</name>
+              <description>The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT8_MODE</name>
+              <description>The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT9_MODE</name>
+              <description>The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT10_MODE</name>
+              <description>The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT11_MODE</name>
+              <description>The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT12_MODE</name>
+              <description>The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT13_MODE</name>
+              <description>The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT14_MODE</name>
+              <description>The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT15_MODE</name>
+              <description>The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_DMA_INT_ENA</name>
+          <description>LCD_camera DMA inturrupt enable register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_VSYNC_INT_ENA</name>
+              <description>The enable bit for LCD frame end interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for lcd transfer end interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_VSYNC_INT_ENA</name>
+              <description>The enable bit for Camera frame end interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAM_HS_INT_ENA</name>
+              <description>The enable bit for Camera line interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_DMA_INT_RAW</name>
+          <description>LCD_camera DMA raw inturrupt status register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_VSYNC_INT_RAW</name>
+              <description>The raw bit for LCD frame end interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LCD_TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for lcd transfer end interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAM_VSYNC_INT_RAW</name>
+              <description>The raw bit for Camera frame end interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAM_HS_INT_RAW</name>
+              <description>The raw bit for Camera line interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_DMA_INT_ST</name>
+          <description>LCD_camera DMA masked inturrupt status register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_VSYNC_INT_ST</name>
+              <description>The status bit for LCD frame end interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LCD_TRANS_DONE_INT_ST</name>
+              <description>The status bit for lcd transfer end interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAM_VSYNC_INT_ST</name>
+              <description>The status bit for Camera frame end interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAM_HS_INT_ST</name>
+              <description>The status bit for Camera transfer end interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_DMA_INT_CLR</name>
+          <description>LCD_camera DMA inturrupt clear register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LCD_VSYNC_INT_CLR</name>
+              <description>The clear bit for LCD frame end interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LCD_TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for lcd transfer end interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAM_VSYNC_INT_CLR</name>
+              <description>The clear bit for Camera frame end interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAM_HS_INT_CLR</name>
+              <description>The clear bit for Camera line interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LC_REG_DATE</name>
+          <description>Version register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02003020</resetValue>
+          <fields>
+            <field>
+              <name>LC_DATE</name>
+              <description>LCD_CAM version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>LEDC</name>
+      <description>LED PWM (Pulse Width Modulation) Controller</description>
+      <groupName>LEDC</groupName>
+      <baseAddress>0x60019000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xD8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>LEDC</name>
+        <value>35</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF0</name>
+          <description>Configuration register 0 for channel %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SEL</name>
+              <description>This field is used to select one of timers for channel %s.
+
+0: select timer0
+
+1: select timer1
+
+2: select timer2
+
+3: select timer3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIG_OUT_EN</name>
+              <description>Set this bit to enable signal output on channel %s.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_LV</name>
+              <description>This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0).</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_NUM</name>
+              <description>This register is used to configure the maximum times of overflow minus 1.
+
+The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_EN</name>
+              <description>This bit is used to enable the ovf_cnt of channel %s.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_RESET</name>
+              <description>Set this bit to reset the ovf_cnt of channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_RESET_ST</name>
+              <description>This is the status bit of LEDC_OVF_CNT_RESET_CH%s.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_HPOINT</name>
+          <description>High point register for channel %s</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HPOINT</name>
+              <description>The output value changes to high when the selected timers has reached the value specified by this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY</name>
+          <description>Initial duty cycle for channel %s</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY</name>
+              <description>This register is used to change the output duty by controlling the Lpoint.
+
+The output value turns to low when the selected timers has reached the Lpoint.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_CONF1</name>
+          <description>Configuration register 1 for channel %s</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_SCALE</name>
+              <description>This register is used to configure the changing step scale of duty on channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CYCLE</name>
+              <description>The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_NUM</name>
+              <description>This register is used to control the number of times the duty cycle will be changed.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_INC</name>
+              <description>This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_START</name>
+              <description>Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>8</dim>
+          <dimIncrement>0x14</dimIncrement>
+          <name>CH%s_DUTY_R</name>
+          <description>Current duty cycle for channel %s</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DUTY_R</name>
+              <description>This register stores the current duty of output signal on channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_CONF</name>
+          <description>Timer %s configuration</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00800000</resetValue>
+          <fields>
+            <field>
+              <name>DUTY_RES</name>
+              <description>This register is used to control the range of the counter in timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DIV</name>
+              <description>This register is used to configure the divisor for the divider in timer %s.
+
+The least significant eight bits represent the fractional part.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAUSE</name>
+              <description>This bit is used to suspend the counter in timer %s.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST</name>
+              <description>This bit is used to reset timer %s. The counter will show 0 after reset.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TICK_SEL</name>
+              <description>This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.
+
+1'h0: SLOW_CLK 1'h1: REF_TICK</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARA_UP</name>
+              <description>Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>TIMER%s_VALUE</name>
+          <description>Timer %s current counter value</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT</name>
+              <description>This register stores the current counter value of timer %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_RAW</name>
+              <description>Triggered when the timer0 has reached its maximum counter value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_RAW</name>
+              <description>Triggered when the timer1 has reached its maximum counter value.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_RAW</name>
+              <description>Triggered when the timer2 has reached its maximum counter value.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_RAW</name>
+              <description>Triggered when the timer3 has reached its maximum counter value.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH6_INT_RAW</name>
+              <description>Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH7_INT_RAW</name>
+              <description>Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_RAW</name>
+              <description>Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_RAW</name>
+              <description>Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_RAW</name>
+              <description>Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_RAW</name>
+              <description>Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_RAW</name>
+              <description>Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_RAW</name>
+              <description>Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH6_INT_RAW</name>
+              <description>Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH7_INT_RAW</name>
+              <description>Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH6_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt when LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH7_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt when LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH6_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH7_INT_ST</name>
+              <description>This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH6_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH7_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH6_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH7_INT_ENA</name>
+              <description>The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER3_OVF_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH6_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DUTY_CHNG_END_CH7_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH0_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH1_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH2_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH3_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH4_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH5_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH6_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OVF_CNT_CH7_INT_CLR</name>
+              <description>Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF</name>
+          <description>Global ledc configuration register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_CLK_SEL</name>
+              <description>This bit is used to select clock source for the 4 timers .
+
+2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>This bit is used to control clock.
+
+1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19040200</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PCNT</name>
+      <description>Pulse Count Controller</description>
+      <groupName>PCNT</groupName>
+      <baseAddress>0x60017000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x68</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PCNT</name>
+        <value>41</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF0</name>
+          <description>Configuration register 0 for unit %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003C10</resetValue>
+          <fields>
+            <field>
+              <name>FILTER_THRES_U</name>
+              <description>This sets the maximum threshold, in APB_CLK cycles, for the filter.
+
+Any pulses with width less than this will be ignored when the filter is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FILTER_EN_U</name>
+              <description>This is the enable bit for unit %s's input filter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_ZERO_EN_U</name>
+              <description>This is the enable bit for unit %s's zero comparator.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_H_LIM_EN_U</name>
+              <description>This is the enable bit for unit %s's thr_h_lim comparator.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_L_LIM_EN_U</name>
+              <description>This is the enable bit for unit %s's thr_l_lim comparator.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES0_EN_U</name>
+              <description>This is the enable bit for unit %s's thres0 comparator.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>THR_THRES1_EN_U</name>
+              <description>This is the enable bit for unit %s's thres1 comparator.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_NEG_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 0 detects a negative edge.
+
+1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_POS_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 0 detects a positive edge.
+
+1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_HCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.
+
+0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH0_LCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.
+
+0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_NEG_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 1 detects a negative edge.
+
+1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_POS_MODE_U</name>
+              <description>This register sets the behavior when the signal input of channel 1 detects a positive edge.
+
+1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_HCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.
+
+0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1_LCTRL_MODE_U</name>
+              <description>This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.
+
+0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF1</name>
+          <description>Configuration register 1 for unit %s</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THRES0_U</name>
+              <description>This register is used to configure the thres0 value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THRES1_U</name>
+              <description>This register is used to configure the thres1 value for unit %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0xC</dimIncrement>
+          <name>U%s_CONF2</name>
+          <description>Configuration register 2 for unit %s</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_H_LIM_U</name>
+              <description>This register is used to configure the thr_h_lim value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_L_LIM_U</name>
+              <description>This register is used to configure the thr_l_lim value for unit %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>U%s_CNT</name>
+          <description>Counter value for unit %s</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PULSE_CNT_U</name>
+              <description>This register stores the current pulse count value for unit %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt raw status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_RAW</name>
+              <description>The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Interrupt status register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ST</name>
+              <description>The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_ENA</name>
+              <description>The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_EVENT_U0_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U1_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U2_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_EVENT_U3_INT_CLR</name>
+              <description>Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>U%s_STATUS</name>
+          <description>PNCT UNIT%s status register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CNT_THR_ZERO_MODE_U</name>
+              <description>The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_THRES1_LAT_U</name>
+              <description>The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_THRES0_LAT_U</name>
+              <description>The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_L_LIM_LAT_U</name>
+              <description>The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_H_LIM_LAT_U</name>
+              <description>The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CNT_THR_ZERO_LAT_U</name>
+              <description>The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>Control register for all counters</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PULSE_CNT_RST_U0</name>
+              <description>Set this bit to clear unit 0's counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U0</name>
+              <description>Set this bit to freeze unit 0's counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U1</name>
+              <description>Set this bit to clear unit 1's counter.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U1</name>
+              <description>Set this bit to freeze unit 1's counter.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U2</name>
+              <description>Set this bit to clear unit 2's counter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U2</name>
+              <description>Set this bit to freeze unit 2's counter.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULSE_CNT_RST_U3</name>
+              <description>Set this bit to clear unit 3's counter.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNT_PAUSE_U3</name>
+              <description>Set this bit to freeze unit 3's counter.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>PCNT version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x19072601</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the PCNT version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PERI_BACKUP</name>
+      <description>Peripheral PERI_BACKUP</description>
+      <groupName>PERI_BACKUP</groupName>
+      <baseAddress>0x6002A000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x30</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PERI_BACKUP</name>
+        <value>97</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONFIG</name>
+          <description>x</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00006480</resetValue>
+          <fields>
+            <field>
+              <name>FLOW_ERR</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADDR_MAP_MODE</name>
+              <description>x</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BURST_LIMIT</name>
+              <description>x</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUT_THRES</name>
+              <description>x</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIZE</name>
+              <description>x</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>x</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TO_MEM</name>
+              <description>x</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENA</name>
+              <description>x</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_ADDR</name>
+          <description>x</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_START_ADDR</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_ADDR</name>
+          <description>x</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_START_ADDR</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_MAP0</name>
+          <description>x</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAP0</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_MAP1</name>
+          <description>x</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAP1</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_MAP2</name>
+          <description>x</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAP2</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_MAP3</name>
+          <description>x</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MAP3</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>x</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DONE_INT_RAW</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_INT_RAW</name>
+              <description>x</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>x</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DONE_INT_ST</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_INT_ST</name>
+              <description>x</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>x</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DONE_INT_ENA</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_INT_ENA</name>
+              <description>x</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>x</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DONE_INT_CLR</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ERR_INT_CLR</name>
+              <description>x</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>x</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02012300</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>x</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>register file clk gating</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>PWM0</name>
+      <description>Peripheral PWM0</description>
+      <groupName>PWM</groupName>
+      <baseAddress>0x6001E000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x128</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>PWM0</name>
+        <value>31</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CLK_CFG</name>
+          <description>PWM clock prescaler register.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_PRESCALE</name>
+              <description>Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_CFG0</name>
+          <description>PWM timer0 period and update method configuration register.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>TIMER0_PRESCALE</name>
+              <description>period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PERIOD</name>
+              <description>period shadow register of PWM timer0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PERIOD_UPMETHOD</name>
+              <description>Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_CFG1</name>
+          <description>PWM timer0 working mode and start/stop control configuration register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_START</name>
+              <description>PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_MOD</name>
+              <description>PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_SYNC</name>
+          <description>PWM timer0 sync function configuration register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_SYNCI_EN</name>
+              <description>When set, timer reloading with phase on sync input event is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW</name>
+              <description>Toggling this bit will trigger a software sync.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_SYNCO_SEL</name>
+              <description>PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_PHASE</name>
+              <description>phase for timer reload on sync event</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER0_STATUS</name>
+          <description>PWM timer0 status register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_VALUE</name>
+              <description>current PWM timer0 counter value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_DIRECTION</name>
+              <description>current PWM timer0 counter direction, 0: increment 1: decrement</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_CFG0</name>
+          <description>PWM timer1 period and update method configuration register.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>TIMER1_PRESCALE</name>
+              <description>period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PERIOD</name>
+              <description>period shadow register of PWM timer1</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PERIOD_UPMETHOD</name>
+              <description>Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_CFG1</name>
+          <description>PWM timer1 working mode and start/stop control configuration register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER1_START</name>
+              <description>PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_MOD</name>
+              <description>PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_SYNC</name>
+          <description>PWM timer1 sync function configuration register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER1_SYNCI_EN</name>
+              <description>When set, timer reloading with phase on sync input event is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW</name>
+              <description>Toggling this bit will trigger a software sync.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_SYNCO_SEL</name>
+              <description>PWM timer1 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_PHASE</name>
+              <description>phase for timer reload on sync event</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1_STATUS</name>
+          <description>PWM timer1 status register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER1_VALUE</name>
+              <description>current PWM timer1 counter value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_DIRECTION</name>
+              <description>current PWM timer1 counter direction, 0: increment 1: decrement</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_CFG0</name>
+          <description>PWM timer2 period and update method configuration register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000FF00</resetValue>
+          <fields>
+            <field>
+              <name>TIMER2_PRESCALE</name>
+              <description>period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PERIOD</name>
+              <description>period shadow register of PWM timer2</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PERIOD_UPMETHOD</name>
+              <description>Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_CFG1</name>
+          <description>PWM timer2 working mode and start/stop control configuration register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER2_START</name>
+              <description>PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_MOD</name>
+              <description>PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_SYNC</name>
+          <description>PWM timer2 sync function configuration register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER2_SYNCI_EN</name>
+              <description>When set, timer reloading with phase on sync input event is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW</name>
+              <description>Toggling this bit will trigger a software sync.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_SYNCO_SEL</name>
+              <description>PWM timer2 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_PHASE</name>
+              <description>phase for timer reload on sync event</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2_STATUS</name>
+          <description>PWM timer2 status register.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER2_VALUE</name>
+              <description>current PWM timer2 counter value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_DIRECTION</name>
+              <description>current PWM timer2 counter direction, 0: increment 1: decrement</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER_SYNCI_CFG</name>
+          <description>Synchronization input selection for three PWM timers.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_SYNCISEL</name>
+              <description>select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_SYNCISEL</name>
+              <description>select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_SYNCISEL</name>
+              <description>select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTERNAL_SYNCI0_INVERT</name>
+              <description>invert SYNC0 from GPIO matrix</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTERNAL_SYNCI1_INVERT</name>
+              <description>invert SYNC1 from GPIO matrix</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTERNAL_SYNCI2_INVERT</name>
+              <description>invert SYNC2 from GPIO matrix</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OPERATOR_TIMERSEL</name>
+          <description>Select specific timer for PWM operators.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OPERATOR0_TIMERSEL</name>
+              <description>Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OPERATOR1_TIMERSEL</name>
+              <description>Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OPERATOR2_TIMERSEL</name>
+              <description>Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMPR0_CFG</name>
+          <description>Transfer status and update method for time stamp registers A and B</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR0_A_UPMETHOD</name>
+              <description>Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR0_B_UPMETHOD</name>
+              <description>Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR0_A_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR0_B_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMPR0_VALUE0</name>
+          <description>Shadow register for register A.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR0_A</name>
+              <description>PWM generator 0 time stamp A's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMPR0_VALUE1</name>
+          <description>Shadow register for register B.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR0_B</name>
+              <description>PWM generator 0 time stamp B's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_CFG0</name>
+          <description>Fault event T0 and T1 handling</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN0_CFG_UPMETHOD</name>
+              <description>Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_T0_SEL</name>
+              <description>Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_T1_SEL</name>
+              <description>Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_FORCE</name>
+          <description>Permissives to force PWM0A and PWM0B outputs by software</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>GEN0_CNTUFORCE_UPMETHOD</name>
+              <description>Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_A_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN0_B_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_A</name>
+          <description>Actions triggered by events on PWM0A</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM0A triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM0A triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM0A triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM0A triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM0A triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM0A triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM0A triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM0A triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM0A triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM0A triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM0A triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN0_B</name>
+          <description>Actions triggered by events on PWM0B</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM0B triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM0B triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM0B triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM0B triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM0B triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM0B triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM0B triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM0B triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM0B triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM0B triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM0B triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DB0_CFG</name>
+          <description>dead time type selection and configuration</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>DB0_FED_UPMETHOD</name>
+              <description>Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_RED_UPMETHOD</name>
+              <description>Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_DEB_MODE</name>
+              <description>S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_A_OUTSWAP</name>
+              <description>S6 in documentation</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_B_OUTSWAP</name>
+              <description>S7 in documentation</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_RED_INSEL</name>
+              <description>S4 in documentation</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_FED_INSEL</name>
+              <description>S5 in documentation</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_RED_OUTINVERT</name>
+              <description>S2 in documentation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_FED_OUTINVERT</name>
+              <description>S3 in documentation</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_A_OUTBYPASS</name>
+              <description>S1 in documentation</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_B_OUTBYPASS</name>
+              <description>S0 in documentation</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB0_CLK_SEL</name>
+              <description>Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DB0_FED_CFG</name>
+          <description>Shadow register for falling edge delay (FED).</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB0_FED</name>
+              <description>Shadow register for FED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DB0_RED_CFG</name>
+          <description>Shadow register for rising edge delay (RED).</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB0_RED</name>
+              <description>Shadow register for RED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHOPPER0_CFG</name>
+          <description>Carrier enable and configuratoin</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHOPPER0_EN</name>
+              <description>When set, carrier0 function is enabled. When cleared, carrier0 is bypassed</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_PRESCALE</name>
+              <description>PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_DUTY</name>
+              <description>carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_OSHTWTH</name>
+              <description>width of the fist pulse in number of periods of the carrier</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_OUT_INVERT</name>
+              <description>when set, invert the output of PWM0A and PWM0B for this submodule</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER0_IN_INVERT</name>
+              <description>when set, invert the input of PWM0A and PWM0B for this submodule</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TZ0_CFG0</name>
+          <description>Actions on PWM0A and PWM0B trip events</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ0_SW_CBC</name>
+              <description>Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F2_CBC</name>
+              <description>event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F1_CBC</name>
+              <description>event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F0_CBC</name>
+              <description>event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_SW_OST</name>
+              <description>Enable register for software force one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F2_OST</name>
+              <description>event_f2 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F1_OST</name>
+              <description>event_f1 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_F0_OST</name>
+              <description>event_f0 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_A_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_A_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_A_OST_D</name>
+              <description>One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_A_OST_U</name>
+              <description>One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_B_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_B_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_B_OST_D</name>
+              <description>One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_B_OST_U</name>
+              <description>One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TZ0_CFG1</name>
+          <description>Software triggers for fault handler actions</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ0_CLR_OST</name>
+              <description>a rising edge will clear on going one-shot mode action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_CBCPULSE</name>
+              <description>cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_FORCE_CBC</name>
+              <description>a toggle trigger a cycle-by-cycle mode action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_FORCE_OST</name>
+              <description>a toggle (software negate its value) triggers a one-shot mode action</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TZ0_STATUS</name>
+          <description>Status of fault events.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ0_CBC_ON</name>
+              <description>Set and reset by hardware. If set, a cycle-by-cycle mode action is on going</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_OST_ON</name>
+              <description>Set and reset by hardware. If set, an one-shot mode action is on going</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMPR1_CFG</name>
+          <description>Transfer status and update method for time stamp registers A and B</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR1_A_UPMETHOD</name>
+              <description>Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR1_B_UPMETHOD</name>
+              <description>Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR1_A_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR1_B_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMPR1_VALUE0</name>
+          <description>Shadow register for register A.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR1_A</name>
+              <description>PWM generator 1 time stamp A's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMPR1_VALUE1</name>
+          <description>Shadow register for register B.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR1_B</name>
+              <description>PWM generator 1 time stamp B's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_CFG0</name>
+          <description>Fault event T0 and T1 handling</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN1_CFG_UPMETHOD</name>
+              <description>Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_T0_SEL</name>
+              <description>Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_T1_SEL</name>
+              <description>Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_FORCE</name>
+          <description>Permissives to force PWM1A and PWM1B outputs by software</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>GEN1_CNTUFORCE_UPMETHOD</name>
+              <description>Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_A_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN1_B_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_A</name>
+          <description>Actions triggered by events on PWM1A</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM1A triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM1A triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM1A triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM1A triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM1A triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM1A triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM1A triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM1A triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM1A triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM1A triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM1A triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN1_B</name>
+          <description>Actions triggered by events on PWM1B</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM1B triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM1B triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM1B triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM1B triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM1B triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM1B triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM1B triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM1B triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM1B triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM1B triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM1B triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DB1_CFG</name>
+          <description>dead time type selection and configuration</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>DB1_FED_UPMETHOD</name>
+              <description>Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_RED_UPMETHOD</name>
+              <description>Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_DEB_MODE</name>
+              <description>S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_A_OUTSWAP</name>
+              <description>S6 in documentation</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_B_OUTSWAP</name>
+              <description>S7 in documentation</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_RED_INSEL</name>
+              <description>S4 in documentation</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_FED_INSEL</name>
+              <description>S5 in documentation</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_RED_OUTINVERT</name>
+              <description>S2 in documentation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_FED_OUTINVERT</name>
+              <description>S3 in documentation</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_A_OUTBYPASS</name>
+              <description>S1 in documentation</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_B_OUTBYPASS</name>
+              <description>S0 in documentation</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB1_CLK_SEL</name>
+              <description>Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DB1_FED_CFG</name>
+          <description>Shadow register for falling edge delay (FED).</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB1_FED</name>
+              <description>Shadow register for FED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DB1_RED_CFG</name>
+          <description>Shadow register for rising edge delay (RED).</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB1_RED</name>
+              <description>Shadow register for RED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHOPPER1_CFG</name>
+          <description>Carrier enable and configuratoin</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHOPPER1_EN</name>
+              <description>When set, carrier0 function is enabled. When cleared, carrier0 is bypassed</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_PRESCALE</name>
+              <description>PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_DUTY</name>
+              <description>carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_OSHTWTH</name>
+              <description>width of the fist pulse in number of periods of the carrier</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_OUT_INVERT</name>
+              <description>when set, invert the output of PWM1A and PWM1B for this submodule</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER1_IN_INVERT</name>
+              <description>when set, invert the input of PWM1A and PWM1B for this submodule</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TZ1_CFG0</name>
+          <description>Actions on PWM1A and PWM1B trip events</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ1_SW_CBC</name>
+              <description>Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F2_CBC</name>
+              <description>event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F1_CBC</name>
+              <description>event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F0_CBC</name>
+              <description>event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_SW_OST</name>
+              <description>Enable register for software force one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F2_OST</name>
+              <description>event_f2 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F1_OST</name>
+              <description>event_f1 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_F0_OST</name>
+              <description>event_f0 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_A_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_A_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_A_OST_D</name>
+              <description>One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_A_OST_U</name>
+              <description>One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_B_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_B_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_B_OST_D</name>
+              <description>One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_B_OST_U</name>
+              <description>One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TZ1_CFG1</name>
+          <description>Software triggers for fault handler actions</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ1_CLR_OST</name>
+              <description>a rising edge will clear on going one-shot mode action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_CBCPULSE</name>
+              <description>cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_FORCE_CBC</name>
+              <description>a toggle trigger a cycle-by-cycle mode action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_FORCE_OST</name>
+              <description>a toggle (software negate its value) triggers a one-shot mode action</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TZ1_STATUS</name>
+          <description>Status of fault events.</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ1_CBC_ON</name>
+              <description>Set and reset by hardware. If set, a cycle-by-cycle mode action is on going</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_OST_ON</name>
+              <description>Set and reset by hardware. If set, an one-shot mode action is on going</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMPR2_CFG</name>
+          <description>Transfer status and update method for time stamp registers A and B</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR2_A_UPMETHOD</name>
+              <description>Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR2_B_UPMETHOD</name>
+              <description>Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR2_A_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR2_B_SHDW_FULL</name>
+              <description>Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMPR2_VALUE0</name>
+          <description>Shadow register for register A.</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR2_A</name>
+              <description>PWM generator 2 time stamp A's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMPR2_VALUE1</name>
+          <description>Shadow register for register B.</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CMPR2_B</name>
+              <description>PWM generator 2 time stamp B's shadow register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_CFG0</name>
+          <description>Fault event T0 and T1 handling</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GEN2_CFG_UPMETHOD</name>
+              <description>Update method for PWM generator 2's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_T0_SEL</name>
+              <description>Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_T1_SEL</name>
+              <description>Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_FORCE</name>
+          <description>Permissives to force PWM2A and PWM2B outputs by software</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>GEN2_CNTUFORCE_UPMETHOD</name>
+              <description>Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_CNTUFORCE_MODE</name>
+              <description>Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_A_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_NCIFORCE</name>
+              <description>Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GEN2_B_NCIFORCE_MODE</name>
+              <description>non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_A</name>
+          <description>Actions triggered by events on PWM2A</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM2A triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM2A triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM2A triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM2A triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM2A triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM2A triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM2A triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM2A triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM2A triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM2A triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM2A triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GEN2_B</name>
+          <description>Actions triggered by events on PWM2B</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UTEZ</name>
+              <description>Action on PWM2B triggered by event TEZ when timer increasing</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEP</name>
+              <description>Action on PWM2B triggered by event TEP when timer increasing</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEA</name>
+              <description>Action on PWM2B triggered by event TEA when timer increasing</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UTEB</name>
+              <description>Action on PWM2B triggered by event TEB when timer increasing</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT0</name>
+              <description>Action on PWM2B triggered by event_t0 when timer increasing</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UT1</name>
+              <description>Action on PWM2B triggered by event_t1 when timer increasing</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEZ</name>
+              <description>Action on PWM2B triggered by event TEZ when timer decreasing</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEP</name>
+              <description>Action on PWM2B triggered by event TEP when timer decreasing</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEA</name>
+              <description>Action on PWM2B triggered by event TEA when timer decreasing</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTEB</name>
+              <description>Action on PWM2B triggered by event TEB when timer decreasing</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT0</name>
+              <description>Action on PWM2B triggered by event_t0 when timer decreasing</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DT1</name>
+              <description>Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DB2_CFG</name>
+          <description>dead time type selection and configuration</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018000</resetValue>
+          <fields>
+            <field>
+              <name>DB2_FED_UPMETHOD</name>
+              <description>Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_RED_UPMETHOD</name>
+              <description>Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_DEB_MODE</name>
+              <description>S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_A_OUTSWAP</name>
+              <description>S6 in documentation</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_B_OUTSWAP</name>
+              <description>S7 in documentation</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_RED_INSEL</name>
+              <description>S4 in documentation</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_FED_INSEL</name>
+              <description>S5 in documentation</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_RED_OUTINVERT</name>
+              <description>S2 in documentation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_FED_OUTINVERT</name>
+              <description>S3 in documentation</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_A_OUTBYPASS</name>
+              <description>S1 in documentation</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_B_OUTBYPASS</name>
+              <description>S0 in documentation</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DB2_CLK_SEL</name>
+              <description>Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DB2_FED_CFG</name>
+          <description>Shadow register for falling edge delay (FED).</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB2_FED</name>
+              <description>Shadow register for FED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DB2_RED_CFG</name>
+          <description>Shadow register for rising edge delay (RED).</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DB2_RED</name>
+              <description>Shadow register for RED</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CHOPPER2_CFG</name>
+          <description>Carrier enable and configuratoin</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHOPPER2_EN</name>
+              <description>When set, carrier0 function is enabled. When cleared, carrier0 is bypassed</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_PRESCALE</name>
+              <description>PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_DUTY</name>
+              <description>carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_OSHTWTH</name>
+              <description>width of the fist pulse in number of periods of the carrier</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_OUT_INVERT</name>
+              <description>when set, invert the output of PWM2A and PWM2B for this submodule</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHOPPER2_IN_INVERT</name>
+              <description>when set, invert the input of PWM2A and PWM2B for this submodule</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TZ2_CFG0</name>
+          <description>Actions on PWM2A and PWM2B trip events</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ2_SW_CBC</name>
+              <description>Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F2_CBC</name>
+              <description>event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F1_CBC</name>
+              <description>event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F0_CBC</name>
+              <description>event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_SW_OST</name>
+              <description>Enable register for software force one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F2_OST</name>
+              <description>event_f2 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F1_OST</name>
+              <description>event_f1 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_F0_OST</name>
+              <description>event_f0 will trigger one-shot mode action. 0: disable, 1: enable</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_A_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_A_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_A_OST_D</name>
+              <description>One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_A_OST_U</name>
+              <description>One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_B_CBC_D</name>
+              <description>Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_B_CBC_U</name>
+              <description>Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_B_OST_D</name>
+              <description>One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_B_OST_U</name>
+              <description>One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TZ2_CFG1</name>
+          <description>Software triggers for fault handler actions</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ2_CLR_OST</name>
+              <description>a rising edge will clear on going one-shot mode action</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_CBCPULSE</name>
+              <description>cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_FORCE_CBC</name>
+              <description>a toggle trigger a cycle-by-cycle mode action</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_FORCE_OST</name>
+              <description>a toggle (software negate its value) triggers a one-shot mode action</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TZ2_STATUS</name>
+          <description>Status of fault events.</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TZ2_CBC_ON</name>
+              <description>Set and reset by hardware. If set, a cycle-by-cycle mode action is on going</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_OST_ON</name>
+              <description>Set and reset by hardware. If set, an one-shot mode action is on going</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FAULT_DETECT</name>
+          <description>Fault detection configuration and status</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>F0_EN</name>
+              <description>When set, event_f0 generation is enabled</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F1_EN</name>
+              <description>When set, event_f1 generation is enabled</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F2_EN</name>
+              <description>When set, event_f2 generation is enabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F0_POLE</name>
+              <description>Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F1_POLE</name>
+              <description>Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>F2_POLE</name>
+              <description>Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EVENT_F0</name>
+              <description>Set and reset by hardware. If set, event_f0 is on going</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EVENT_F1</name>
+              <description>Set and reset by hardware. If set, event_f1 is on going</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EVENT_F2</name>
+              <description>Set and reset by hardware. If set, event_f2 is on going</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_TIMER_CFG</name>
+          <description>Configure capture timer</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP_TIMER_EN</name>
+              <description>When set, capture timer incrementing under APB_clk is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP_SYNCI_EN</name>
+              <description>When set, capture timer sync is enabled.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP_SYNCI_SEL</name>
+              <description>capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP_SYNC_SW</name>
+              <description>Write 1 will force a capture timer sync, capture timer is loaded with value in phase register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_TIMER_PHASE</name>
+          <description>Phase for capture timer sync</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP_PHASE</name>
+              <description>Phase value for capture timer sync operation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH0_CFG</name>
+          <description>Capture channel 0 configuration and enable</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP0_EN</name>
+              <description>When set, capture on channel 0 is enabled</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_MODE</name>
+              <description>Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_PRESCALE</name>
+              <description>Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_IN_INVERT</name>
+              <description>when set, CAP0 form GPIO matrix is inverted before prescale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_SW</name>
+              <description>Write 1 will trigger a software forced capture on channel 0</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH1_CFG</name>
+          <description>Capture channel 1 configuration and enable</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP1_EN</name>
+              <description>When set, capture on channel 2 is enabled</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_MODE</name>
+              <description>Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_PRESCALE</name>
+              <description>Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_IN_INVERT</name>
+              <description>when set, CAP1 form GPIO matrix is inverted before prescale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_SW</name>
+              <description>Write 1 will trigger a software forced capture on channel 1</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH2_CFG</name>
+          <description>Capture channel 2 configuration and enable</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP2_EN</name>
+              <description>When set, capture on channel 2 is enabled</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_MODE</name>
+              <description>Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_PRESCALE</name>
+              <description>Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_IN_INVERT</name>
+              <description>when set, CAP2 form GPIO matrix is inverted before prescale</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_SW</name>
+              <description>Write 1 will trigger a software forced capture on channel 2</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH0</name>
+          <description>Value of last capture on channel 0</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP0_VALUE</name>
+              <description>Value of last capture on channel 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH1</name>
+          <description>Value of last capture on channel 1</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP1_VALUE</name>
+              <description>Value of last capture on channel 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_CH2</name>
+          <description>Value of last capture on channel 2</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP2_VALUE</name>
+              <description>Value of last capture on channel 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CAP_STATUS</name>
+          <description>Edge of last capture trigger</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CAP0_EDGE</name>
+              <description>Edge of last capture trigger on channel 0, 0: posedge, 1: negedge</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP1_EDGE</name>
+              <description>Edge of last capture trigger on channel 1, 0: posedge, 1: negedge</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP2_EDGE</name>
+              <description>Edge of last capture trigger on channel 2, 0: posedge, 1: negedge</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UPDATE_CFG</name>
+          <description>Enable update.</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000055</resetValue>
+          <fields>
+            <field>
+              <name>GLOBAL_UP_EN</name>
+              <description>The global enable of update of all active registers in MCPWM module</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLOBAL_FORCE_UP</name>
+              <description>a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP0_UP_EN</name>
+              <description>When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP0_FORCE_UP</name>
+              <description>a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP1_UP_EN</name>
+              <description>When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP1_FORCE_UP</name>
+              <description>a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP2_UP_EN</name>
+              <description>When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OP2_FORCE_UP</name>
+              <description>a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when the timer 0 stops.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when the timer 1 stops.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when the timer 2 stops.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 0 TEP event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 1 TEP event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM timer 2 TEP event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f0 starts.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f1 starts.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f2 starts.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f0 ends.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f1 ends.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered when event_f2 ends.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR0_TEA_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 0 TEA event</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR1_TEA_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 1 TEA event</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR2_TEA_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 2 TEA event</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR0_TEB_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 0 TEB event</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR1_TEB_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 1 TEB event</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMPR2_TEB_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a PWM operator 2 TEB event</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_CBC_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_CBC_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_CBC_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ0_OST_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a one-shot mode action on PWM0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ1_OST_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a one-shot mode action on PWM1.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TZ2_OST_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by a one-shot mode action on PWM2.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP0_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by capture on channel 0.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP1_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by capture on channel 1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAP2_INT_ENA</name>
+              <description>The enable bit for the interrupt triggered by capture on channel 2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when the timer 0 stops.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when the timer 1 stops.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when the timer 2 stops.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f0 starts.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f1 starts.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f2 starts.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f0 ends.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f1 ends.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered when event_f2 ends.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEA_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 0 TEA event</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEA_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 1 TEA event</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEA_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 2 TEA event</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEB_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 0 TEB event</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEB_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 1 TEB event</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEB_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a PWM operator 2 TEB event</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_CBC_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_CBC_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_CBC_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_OST_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_OST_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_OST_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP0_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by capture on channel 0.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP1_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by capture on channel 1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP2_INT_RAW</name>
+              <description>The raw status bit for the interrupt triggered by capture on channel 2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when the timer 0 stops.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when the timer 1 stops.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when the timer 2 stops.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f0 starts.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f1 starts.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f2 starts.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f0 ends.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f1 ends.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered when event_f2 ends.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEA_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 0 TEA event</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEA_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 1 TEA event</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEA_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 2 TEA event</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEB_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 0 TEB event</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEB_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 1 TEB event</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEB_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a PWM operator 2 TEB event</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_CBC_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_CBC_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_CBC_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ0_OST_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ1_OST_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TZ2_OST_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP0_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by capture on channel 0.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP1_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by capture on channel 1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CAP2_INT_ST</name>
+              <description>The masked status bit for the interrupt triggered by capture on channel 2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER0_STOP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when the timer 0 stops.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_STOP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when the timer 1 stops.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_STOP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when the timer 2 stops.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEZ_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEZ_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEZ_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER0_TEP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER1_TEP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIMER2_TEP_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT0_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f0 starts.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT1_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f1 starts.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT2_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f2 starts.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT0_CLR_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f0 ends.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT1_CLR_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f1 ends.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FAULT2_CLR_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered when event_f2 ends.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEA_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEA_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEA_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR0_TEB_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR1_TEB_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CMPR2_TEB_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ0_CBC_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ1_CBC_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ2_CBC_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ0_OST_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ1_OST_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TZ2_OST_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAP0_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by capture on channel 0.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAP1_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by capture on channel 1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CAP2_INT_CLR</name>
+              <description>Set this bit to clear the interrupt triggered by capture on channel 2.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK</name>
+          <description>MCPWM APB configuration register</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>Force clock on for this register file</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>VERSION</name>
+          <description>Version register.</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01509110</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Version of this register file</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="PWM0">
+      <name>PWM1</name>
+      <baseAddress>0x6002C000</baseAddress>
+      <interrupt>
+        <name>PWM1</name>
+        <value>32</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>RMT</name>
+      <description>Remote control</description>
+      <groupName>RMT</groupName>
+      <baseAddress>0x60016000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xD0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RMT</name>
+        <value>40</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>TX_CH%sDATA</name>
+          <description>The read and write  data register for CHANNEL%s by apb fifo access.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHDATA</name>
+              <description>Read and write data for channel %s via APB FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>RX_CH%sDATA</name>
+          <description>The read and write  data register for CHANNEL$n by apb fifo access.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHDATA</name>
+              <description>Read and write data for channel 0 via APB FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_TX_CONF0</name>
+          <description>Channel %s configure register 0</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00710200</resetValue>
+          <fields>
+            <field>
+              <name>TX_START</name>
+              <description>Set this bit to start sending data on CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_RD_RST</name>
+              <description>Set this bit to reset read ram address for CHANNEL%s by accessing transmitter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST</name>
+              <description>Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_CONTI_MODE</name>
+              <description>Set this bit to restart transmission  from the first data to the last data in CHANNEL%s.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TX_WRAP_EN</name>
+              <description>This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_LV</name>
+              <description>This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_OUT_EN</name>
+              <description>This is the output enable-control bit for CHANNEL%s in IDLE state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_STOP</name>
+              <description>Set this bit to stop the transmitter of CHANNEL%s sending data out.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIV_CNT</name>
+              <description>This register is used to configure the divider for clock of CHANNEL%s.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE</name>
+              <description>This register is used to configure the maximum size of memory allocated to CHANNEL%s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EFF_EN</name>
+              <description>1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN</name>
+              <description>This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV</name>
+              <description>This bit is used to configure the position of carrier wave for CHANNEL%s.
+
+1'h0: add carrier wave on low level.
+
+1'h1: add carrier wave on high level.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFIFO_RST</name>
+              <description>Reserved</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPDATE</name>
+              <description>synchronization bit for CHANNEL%s</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>CH%s_RX_CONF0</name>
+          <description>Channel %s configure register 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x317FFF02</resetValue>
+          <fields>
+            <field>
+              <name>DIV_CNT</name>
+              <description>This register is used to configure the divider for clock of CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IDLE_THRES</name>
+              <description>When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_SIZE</name>
+              <description>This register is used to configure the maximum size of memory allocated to CHANNEL%s.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_EN</name>
+              <description>This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_OUT_LV</name>
+              <description>This bit is used to configure the position of carrier wave for CHANNEL%s.
+
+1'h0: add carrier wave on low level.
+
+1'h1: add carrier wave on high level.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x8</dimIncrement>
+          <name>CH%s_RX_CONF1</name>
+          <description>Channel %s configure register 1</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001E8</resetValue>
+          <fields>
+            <field>
+              <name>RX_EN</name>
+              <description>Set this bit to enable receiver to receive data on CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_WR_RST</name>
+              <description>Set this bit to reset write ram address for CHANNEL%s by accessing receiver.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RST</name>
+              <description>Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER</name>
+              <description>This register marks the ownership of CHANNEL%s's ram block.
+
+1'h1: Receiver is using the ram.
+
+1'h0: APB bus is using the ram.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_EN</name>
+              <description>This is the receive filter's enable bit for CHANNEL%s.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_THRES</name>
+              <description>Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode).</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_RX_WRAP_EN</name>
+              <description>This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AFIFO_RST</name>
+              <description>Reserved</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CONF_UPDATE</name>
+              <description>synchronization bit for CHANNEL%s</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_TX_STATUS</name>
+          <description>Channel %s status register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MEM_RADDR_EX</name>
+              <description>This register records the memory address offset when transmitter of CHANNEL%s is using the RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WADDR</name>
+              <description>This register records the memory address offset when writes RAM over APB bus.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>This register records the FSM status of CHANNEL%s.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_EMPTY</name>
+              <description>This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_WR_ERR</name>
+              <description>This status bit will be set if the offset address out of memory size when writes via APB bus.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_RX_STATUS</name>
+          <description>Channel %s status register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000600C0</resetValue>
+          <fields>
+            <field>
+              <name>MEM_WADDR_EX</name>
+              <description>This register records the memory address offset when receiver of CHANNEL%s is using the RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RADDR</name>
+              <description>This register records the memory address offset when reads RAM over APB bus.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STATE</name>
+              <description>This register records the FSM status of CHANNEL%s.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_OWNER_ERR</name>
+              <description>This status bit will be set when the ownership of memory block is wrong.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_FULL</name>
+              <description>This status bit will be set if the receiver receives more data than the memory size.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APB_MEM_RD_ERR</name>
+              <description>This status bit will be set if the offset address out of memory size when reads via APB bus.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL%s. Triggered when transmission done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL%s. Triggered when error occurs.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_LOOP_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>4-7</dimIndex>
+              <name>CH%s_RX_END_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL4. Triggered when reception done.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>4-7</dimIndex>
+              <name>CH%s_RX_ERR_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL4. Triggered when error occurs.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH4_RX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH5_RX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH6_RX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH7_RX_THR_EVENT_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH3_DMA_ACCESS_FAIL_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH7_DMA_ACCESS_FAIL_INT_RAW</name>
+              <description>The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH%s_TX_END_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH%s_ERR_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH%s_TX_THR_EVENT_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_LOOP_INT_ST</name>
+              <description>The masked interrupt status bit for CH%s_TX_LOOP_INT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>4-7</dimIndex>
+              <name>CH%s_RX_END_INT_ST</name>
+              <description>The masked interrupt status bit for CH4_RX_END_INT.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>4-7</dimIndex>
+              <name>CH%s_RX_ERR_INT_ST</name>
+              <description>The masked interrupt status bit for CH4_ERR_INT.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH4_RX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH4_RX_THR_EVENT_INT.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH5_RX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH5_RX_THR_EVENT_INT.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH6_RX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH6_RX_THR_EVENT_INT.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CH7_RX_THR_EVENT_INT_ST</name>
+              <description>The masked interrupt status bit for CH7_RX_THR_EVENT_INT.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_CH3_DMA_ACCESS_FAIL_INT_ST</name>
+              <description>The masked interrupt status bit for  CH3_DMA_ACCESS_FAIL_INT.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_CH7_DMA_ACCESS_FAIL_INT_ST</name>
+              <description>The masked interrupt status bit for  CH7_DMA_ACCESS_FAIL_INT.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH%s_TX_END_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH%s_ERR_INT.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH%s_TX_THR_EVENT_INT.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_LOOP_INT_ENA</name>
+              <description>The interrupt enable bit for CH%s_TX_LOOP_INT.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>4-7</dimIndex>
+              <name>CH%s_RX_END_INT_ENA</name>
+              <description>The interrupt enable bit for CH4_RX_END_INT.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>4-7</dimIndex>
+              <name>CH%s_RX_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for CH4_ERR_INT.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH4_RX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH4_RX_THR_EVENT_INT.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH5_RX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH5_RX_THR_EVENT_INT.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH6_RX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH6_RX_THR_EVENT_INT.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH7_RX_THR_EVENT_INT_ENA</name>
+              <description>The interrupt enable bit for CH7_RX_THR_EVENT_INT.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CH3_DMA_ACCESS_FAIL_INT_ENA</name>
+              <description>The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_CH7_DMA_ACCESS_FAIL_INT_ENA</name>
+              <description>The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH%s_TX_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH%s_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>0-3</dimIndex>
+              <name>CH%s_TX_LOOP_INT_CLR</name>
+              <description>Set this bit to clear theCH%s_TX_LOOP_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>4-7</dimIndex>
+              <name>CH%s_RX_END_INT_CLR</name>
+              <description>Set this bit to clear theCH4_RX_END_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <dim>4</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>RX_CH4,RX_CH5,RX_CH6,RX_CH7</dimIndex>
+              <name>CH%s_RX_ERR_INT_CLR</name>
+              <description>Set this bit to clear theCH4_ERR_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH4_RX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH5_RX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH6_RX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CH7_RX_THR_EVENT_INT_CLR</name>
+              <description>Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_CH3_DMA_ACCESS_FAIL_INT_CLR</name>
+              <description>Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_CH7_DMA_ACCESS_FAIL_INT_CLR</name>
+              <description>Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%sCARRIER_DUTY</name>
+          <description>Channel %s duty cycle configuration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400040</resetValue>
+          <fields>
+            <field>
+              <name>CARRIER_LOW</name>
+              <description>This register is used to configure carrier wave 's low level clock period for CHANNEL%s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH</name>
+              <description>This register is used to configure carrier wave 's high level clock period for CHANNEL%s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_RX_CARRIER_RM</name>
+          <description>Channel %s carrier remove register</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CARRIER_LOW_THRES</name>
+              <description>The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CARRIER_HIGH_THRES</name>
+              <description>The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_TX_LIM</name>
+          <description>Channel %s Tx event configuration register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>TX_LIM</name>
+              <description>This register is used to configure the maximum entries that CHANNEL%s can send out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_NUM</name>
+              <description>This register is used to configure the maximum loop count when tx_conti_mode is valid.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LOOP_CNT_EN</name>
+              <description>This register is the enabled bit for loop count.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOP_COUNT_RESET</name>
+              <description>This register is used to reset the loop count when tx_conti_mode is valid.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>LOOP_STOP_EN</name>
+              <description>This bit is used to enable the loop send stop function after the loop counter counts to  loop number for CHANNEL%s.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>4</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>CH%s_RX_LIM</name>
+          <description>Channel %s Rx event configuration register</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>RX_LIM</name>
+              <description>This register is used to configure the maximum entries that CHANNEL%s can receive.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYS_CONF</name>
+          <description>RMT apb configuration register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x05000010</resetValue>
+          <fields>
+            <field>
+              <name>APB_FIFO_MASK</name>
+              <description>1'h1: access memory directly.   1'h0: access memory by FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_FORCE_ON</name>
+              <description>Set this bit to enable the clock for RMT memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to power down RMT memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>the integral part of the fractional divisor</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>the numerator of the fractional part of the fractional divisor</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>the denominator of the fractional part of the fractional divisor</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_ACTIVE</name>
+              <description>rmt_sclk switch</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_SIM</name>
+          <description>RMT TX synchronous register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CH0</name>
+              <description>Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH1</name>
+              <description>Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH2</name>
+              <description>Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CH3</name>
+              <description>Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>This register is used to enable multiple of channels to start sending data synchronously.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REF_CNT_RST</name>
+          <description>RMT clock divider reset register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <dim>8</dim>
+              <dimIncrement>0x1</dimIncrement>
+              <dimIndex>TX_REF_CNT_RST_CH0,TX_REF_CNT_RST_CH1,TX_REF_CNT_RST_CH2,TX_REF_CNT_RST_CH3,RX_REF_CNT_RST_CH4,RX_REF_CNT_RST_CH5,RX_REF_CNT_RST_CH6,RX_REF_CNT_RST_CH7</dimIndex>
+              <name>CH%s</name>
+              <description>This register is used to reset the clock divider of CHANNEL0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>RMT version register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101181</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RNG</name>
+      <description>Hardware random number generator</description>
+      <groupName>RNG</groupName>
+      <baseAddress>0x60034F6C</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>DATA</name>
+          <description>Random number data</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RSA</name>
+      <description>RSA (Rivest Shamir Adleman) Accelerator</description>
+      <groupName>RSA</groupName>
+      <baseAddress>0x6003C000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x834</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RSA</name>
+        <value>76</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>Memory M</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Z_MEM[%s]</name>
+          <description>Memory Z</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>Y_MEM[%s]</name>
+          <description>Memory Y</description>
+          <addressOffset>0x400</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>512</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>X_MEM[%s]</name>
+          <description>Memory X</description>
+          <addressOffset>0x600</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <name>M_PRIME</name>
+          <description>RSA M' register</description>
+          <addressOffset>0x800</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>M_PRIME</name>
+              <description>Stores M'</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODE</name>
+          <description>RSA length mode register</description>
+          <addressOffset>0x804</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>Stores the RSA length mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAN</name>
+          <description>RSA clean register</description>
+          <addressOffset>0x808</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAN</name>
+              <description>The content of this bit is 1 when memories complete initialization.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODEXP_START</name>
+          <description>Modular exponentiation trigger register.</description>
+          <addressOffset>0x80C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEXP_START</name>
+              <description>Set this bit to 1 to start the modular exponentiation.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MODMULT_START</name>
+          <description>Modular multiplication trigger register.</description>
+          <addressOffset>0x810</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODMULT_START</name>
+              <description>Set this bit to 1 to start the modular multiplication</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MULT_START</name>
+          <description>Normal multiplication trigger register.</description>
+          <addressOffset>0x814</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MULT_START</name>
+              <description>Set this bit to 1 to start the multiplicaiton.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE</name>
+          <description>RSA idle register</description>
+          <addressOffset>0x818</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IDLE</name>
+              <description>The content of this bit is 1 when the RSA accelerator is idle.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR_INTERRUPT</name>
+          <description>RSA interrupt clear register</description>
+          <addressOffset>0x81C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>set this bit to 1 to clear the RSA interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONSTANT_TIME</name>
+          <description>CONSTANT_TIME option control register</description>
+          <addressOffset>0x820</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CONSTANT_TIME</name>
+              <description>Controls the CONSTANT_TIME option. 0: acceleration. 1: no acceleration(by default).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_ENABLE</name>
+          <description>SEARCH option enable register</description>
+          <addressOffset>0x824</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_ENABLE</name>
+              <description>Controls the SEARCH option. 0: no acceleration(by default). 1: acceleration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SEARCH_POS</name>
+          <description>RSA search position configure register</description>
+          <addressOffset>0x828</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEARCH_POS</name>
+              <description>This field is used to configure the starting search position when the acceleration option of SEARCH is used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERRUPT_ENA</name>
+          <description>RSA interrupt enable register</description>
+          <addressOffset>0x82C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT_ENA</name>
+              <description>Set this bit to 1 to enable the RSA interrupt. This option is enabled by default.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>RSA version control register</description>
+          <addressOffset>0x830</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20191231</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>rsa version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC_CNTL</name>
+      <description>Real Time Controller</description>
+      <groupName>RTC_CNTL</groupName>
+      <baseAddress>0x60008000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x15C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>RTC_CORE</name>
+        <value>39</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>OPTIONS0</name>
+          <description>RTC common configure register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1C00A000</resetValue>
+          <fields>
+            <field>
+              <name>SW_STALL_APPCPU_C0</name>
+              <description>{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STALL_PROCPU_C0</name>
+              <description>{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_APPCPU_RST</name>
+              <description>APP CPU SW reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_PROCPU_RST</name>
+              <description>PRO CPU SW reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PD</name>
+              <description>BB_I2C force power down</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BB_I2C_FORCE_PU</name>
+              <description>BB_I2C force power up</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PD</name>
+              <description>BB_PLL _I2C force power down</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_I2C_FORCE_PU</name>
+              <description>BB_PLL_I2C force power up</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PD</name>
+              <description>BB_PLL force power down</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_FORCE_PU</name>
+              <description>BB_PLL force power up</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PD</name>
+              <description>crystall force power down</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_PU</name>
+              <description>crystall force power up</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EN_WAIT</name>
+              <description>wait bias_sleep and current source wakeup</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_ISO</name>
+              <description>No public</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FORCE_ISO</name>
+              <description>No public</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_ISO</name>
+              <description>No public</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_FORCE_NOISO</name>
+              <description>No public</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FORCE_NOISO</name>
+              <description>No public</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_FORCE_NOISO</name>
+              <description>No public</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_RST</name>
+              <description>digital wrap force reset in deep sleep</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NORST</name>
+              <description>digital core force no reset in deep sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_SYS_RST</name>
+              <description>SW system reset</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER0</name>
+          <description>configure min sleep time</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_LO</name>
+              <description>RTC sleep timer low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_TIMER1</name>
+          <description>configure sleep time hi</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_VAL_HI</name>
+              <description>RTC sleep timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_ALARM_EN</name>
+              <description>timer alarm enable bit</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_UPDATE</name>
+          <description>update rtc main timer</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_SYS_STALL</name>
+              <description>Enable to record system stall time</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_XTL_OFF</name>
+              <description>Enable to record 40M XTAL OFF time</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_SYS_RST</name>
+              <description>enable to record system reset time</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_UPDATE</name>
+              <description>Set 1: to update register with RTC timer</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_LOW0</name>
+          <description>read rtc_main timer low bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE0_LOW</name>
+              <description>RTC timer low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_HIGH0</name>
+          <description>read rtc_main timer high bits</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE0_HIGH</name>
+              <description>RTC timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <description>configure chip sleep</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_CPU_INT</name>
+              <description>rtc software interrupt to main cpu</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_CAUSE_CLR</name>
+              <description>clear rtc sleep reject cause</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APB2RTC_BRIDGE_SEL</name>
+              <description>1: APB to RTC using bridge,  0: APB to RTC using sync</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_ACTIVE_IND</name>
+              <description>SDIO active indication</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_WAKEUP</name>
+              <description>leep wakeup bit</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT</name>
+              <description>leep reject bit</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLEEP_EN</name>
+              <description>sleep enable bit</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER1</name>
+          <description>rtc state wait time</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x28140403</resetValue>
+          <fields>
+            <field>
+              <name>CPU_STALL_EN</name>
+              <description>CPU stall enable bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_STALL_WAIT</name>
+              <description>CPU stall wait cycles in fast_clk_rtc</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_WAIT</name>
+              <description>CK8M wait cycles in slow_clk_rtc</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_BUF_WAIT</name>
+              <description>XTAL wait cycles in slow_clk_rtc</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_BUF_WAIT</name>
+              <description>PLL wait cycles in slow_clk_rtc</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2</name>
+          <description>rtc monitor state delay time</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01080000</resetValue>
+          <fields>
+            <field>
+              <name>ULPCP_TOUCH_START_WAIT</name>
+              <description>wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MIN_TIME_CK8M_OFF</name>
+              <description>minimal cycles in slow_clk_rtc for CK8M in power down state</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER3</name>
+          <description>No public</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x14160A08</resetValue>
+          <fields>
+            <field>
+              <name>WIFI_WAIT_TIMER</name>
+              <description>No public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_POWERUP_TIMER</name>
+              <description>No public</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_WAIT_TIMER</name>
+              <description>No public</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_POWERUP_TIMER</name>
+              <description>No public</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER4</name>
+          <description>No public</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10200A08</resetValue>
+          <fields>
+            <field>
+              <name>WAIT_TIMER</name>
+              <description>No public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWERUP_TIMER</name>
+              <description>No public</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_WAIT_TIMER</name>
+              <description>No public</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_POWERUP_TIMER</name>
+              <description>No public</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER5</name>
+          <description>configure min sleep time</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MIN_SLP_VAL</name>
+              <description>minimal sleep cycles in slow_clk_rtc</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER6</name>
+          <description>No public</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10200A08</resetValue>
+          <fields>
+            <field>
+              <name>CPU_TOP_WAIT_TIMER</name>
+              <description>No public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_POWERUP_TIMER</name>
+              <description>No public</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_WAIT_TIMER</name>
+              <description>No public</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_POWERUP_TIMER</name>
+              <description>No public</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ANA_CONF</name>
+          <description>analog configure register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00440000</resetValue>
+          <fields>
+            <field>
+              <name>I2C_RESET_POR_FORCE_PD</name>
+              <description>force down I2C_RESET_POR</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RESET_POR_FORCE_PU</name>
+              <description>force on I2C_RESET_POR</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_RST_EN</name>
+              <description>enable clk glitch</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_PU</name>
+              <description>PLLA force power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_TOP_ISO_SLEEP</name>
+              <description>PLLA force power down</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANALOG_TOP_ISO_MONITOR</name>
+              <description>PLLA force power up</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBPLL_CAL_SLP_START</name>
+              <description>start BBPLL calibration during sleep</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PVTMON_PU</name>
+              <description>1: PVTMON power up,  otherwise power down</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXRF_I2C_PU</name>
+              <description>1: TXRF_I2C power up,  otherwise power down</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RFRX_PBUS_PU</name>
+              <description>1: RFRX_PBUS power up,  otherwise power down</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CKGEN_I2C_PU</name>
+              <description>1: CKGEN_I2C power up,  otherwise power down</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_I2C_PU</name>
+              <description>power on pll i2c</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RESET_STATE</name>
+          <description>get reset state</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003000</resetValue>
+          <fields>
+            <field>
+              <name>RESET_CAUSE_PROCPU</name>
+              <description>reset cause of PRO CPU</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESET_CAUSE_APPCPU</name>
+              <description>reset cause of APP CPU</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APPCPU_STAT_VECTOR_SEL</name>
+              <description>APP CPU state vector sel</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PROCPU_STAT_VECTOR_SEL</name>
+              <description>PRO CPU state vector sel</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESET_FLAG_PROCPU</name>
+              <description>PRO CPU reset_flag</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESET_FLAG_APPCPU</name>
+              <description>APP CPU reset flag</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESET_FLAG_PROCPU_CLR</name>
+              <description>clear PRO CPU reset_flag</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RESET_FLAG_APPCPU_CLR</name>
+              <description>clear APP CPU reset flag</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APPCPU_OCD_HALT_ON_RESET</name>
+              <description>APPCPU OcdHaltOnReset</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PROCPU_OCD_HALT_ON_RESET</name>
+              <description>PROCPU OcdHaltOnReset</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESET_FLAG_JTAG_PROCPU</name>
+              <description>jtag reset flag</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESET_FLAG_JTAG_APPCPU</name>
+              <description>jtag reset flag</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESET_FLAG_JTAG_PROCPU_CLR</name>
+              <description>clear jtag reset flag</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RESET_FLAG_JTAG_APPCPU_CLR</name>
+              <description>clear jtag reset flag</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_DRESET_MASK</name>
+              <description>bypass cpu1 dreset</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_DRESET_MASK</name>
+              <description>bypass cpu0 dreset</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WAKEUP_STATE</name>
+          <description>configure wakeup state</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00060000</resetValue>
+          <fields>
+            <field>
+              <name>WAKEUP_ENA</name>
+              <description>wakeup enable bitmap</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC</name>
+          <description>configure rtc interrupt register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA</name>
+              <description>enable sleep wakeup interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA</name>
+              <description>enable sleep reject interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ENA</name>
+              <description>enable SDIO idle interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>enable RTC WDT interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_ENA</name>
+              <description>enable touch scan done interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_ENA</name>
+              <description>enable ULP-coprocessor interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_ENA</name>
+              <description>enable touch done interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_ENA</name>
+              <description>enable touch active interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_ENA</name>
+              <description>enable touch inactive interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA</name>
+              <description>enable brown out interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA</name>
+              <description>enable RTC main timer interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_ENA</name>
+              <description>enable saradc1 interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSENS_INT_ENA</name>
+              <description>enable tsens interrupt</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_INT_ENA</name>
+              <description>enable riscV cocpu interrupt</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_ENA</name>
+              <description>enable saradc2 interrupt</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_INT_ENA</name>
+              <description>enable super watch dog interrupt</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ENA</name>
+              <description>enable xtal32k_dead  interrupt</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_ENA</name>
+              <description>enable cocpu trap interrupt</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_ENA</name>
+              <description>enable touch timeout interrupt</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>enbale gitch det interrupt</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_LOOP_DONE_INT_ENA</name>
+              <description>touch approach mode loop interrupt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_RTC</name>
+          <description>rtc interrupt register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_RAW</name>
+              <description>sleep wakeup interrupt raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_RAW</name>
+              <description>sleep reject interrupt raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_RAW</name>
+              <description>SDIO idle interrupt raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>RTC WDT interrupt raw</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_RAW</name>
+              <description>enable touch scan done interrupt raw</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_RAW</name>
+              <description>ULP-coprocessor interrupt raw</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_RAW</name>
+              <description>touch interrupt raw</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_RAW</name>
+              <description>touch active interrupt raw</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_RAW</name>
+              <description>touch inactive interrupt raw</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_RAW</name>
+              <description>brown out interrupt raw</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_RAW</name>
+              <description>RTC main timer interrupt raw</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_RAW</name>
+              <description>saradc1 interrupt raw</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_INT_RAW</name>
+              <description>tsens interrupt raw</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_INT_RAW</name>
+              <description>riscV cocpu interrupt raw</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_RAW</name>
+              <description>saradc2 interrupt raw</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_RAW</name>
+              <description>super watch dog interrupt raw</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_RAW</name>
+              <description>xtal32k dead detection interrupt raw</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_RAW</name>
+              <description>cocpu trap interrupt raw</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_RAW</name>
+              <description>touch timeout interrupt raw</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>glitch_det_interrupt_raw</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_LOOP_DONE_INT_RAW</name>
+              <description>touch approach mode loop interrupt raw</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_RTC</name>
+          <description>rtc interrupt register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ST</name>
+              <description>sleep wakeup interrupt state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ST</name>
+              <description>sleep reject interrupt state</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ST</name>
+              <description>SDIO idle interrupt state</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>RTC WDT interrupt state</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_ST</name>
+              <description>enable touch scan done interrupt raw</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_ST</name>
+              <description>ULP-coprocessor interrupt state</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_ST</name>
+              <description>touch done interrupt state</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_ST</name>
+              <description>touch active interrupt state</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_ST</name>
+              <description>touch inactive interrupt state</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ST</name>
+              <description>brown out interrupt state</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ST</name>
+              <description>RTC main timer interrupt state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_ST</name>
+              <description>saradc1 interrupt state</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSENS_INT_ST</name>
+              <description>tsens interrupt state</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_INT_ST</name>
+              <description>riscV cocpu interrupt state</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_ST</name>
+              <description>saradc2 interrupt state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_ST</name>
+              <description>super watch dog interrupt state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ST</name>
+              <description>xtal32k dead detection interrupt state</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_ST</name>
+              <description>cocpu trap interrupt state</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_ST</name>
+              <description>Touch timeout interrupt state</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>glitch_det_interrupt state</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_LOOP_DONE_INT_ST</name>
+              <description>touch approach mode loop interrupt state</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_RTC</name>
+          <description>rtc interrupt register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_CLR</name>
+              <description>Clear sleep wakeup interrupt state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_CLR</name>
+              <description>Clear sleep reject interrupt state</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_CLR</name>
+              <description>Clear SDIO idle interrupt state</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Clear RTC WDT interrupt state</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_CLR</name>
+              <description>clear touch scan done interrupt raw</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_CLR</name>
+              <description>Clear ULP-coprocessor interrupt state</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_CLR</name>
+              <description>Clear touch done interrupt state</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_CLR</name>
+              <description>Clear touch active interrupt state</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_CLR</name>
+              <description>Clear touch inactive interrupt state</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_CLR</name>
+              <description>Clear brown out interrupt state</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_CLR</name>
+              <description>Clear RTC main timer interrupt state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_CLR</name>
+              <description>Clear saradc1 interrupt state</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TSENS_INT_CLR</name>
+              <description>Clear tsens interrupt state</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_INT_CLR</name>
+              <description>Clear riscV cocpu interrupt state</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_CLR</name>
+              <description>Clear saradc2 interrupt state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_CLR</name>
+              <description>Clear super watch dog interrupt state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_CLR</name>
+              <description>Clear RTC WDT interrupt state</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_CLR</name>
+              <description>Clear cocpu trap interrupt state</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_CLR</name>
+              <description>Clear touch timeout interrupt state</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Clear glitch det interrupt state</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_LOOP_DONE_INT_CLR</name>
+              <description>cleartouch approach mode loop interrupt state</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE0</name>
+          <description>Reserved register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH0</name>
+              <description>Reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE1</name>
+          <description>Reserved register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH1</name>
+              <description>Reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE2</name>
+          <description>Reserved register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH2</name>
+              <description>Reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE3</name>
+          <description>Reserved register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH3</name>
+              <description>Reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_XTL_CONF</name>
+          <description>Reserved register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00066C80</resetValue>
+          <fields>
+            <field>
+              <name>XTAL32K_WDT_EN</name>
+              <description>xtal 32k watch dog enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_WDT_CLK_FO</name>
+              <description>xtal 32k watch dog clock force on</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_WDT_RESET</name>
+              <description>xtal 32k watch dog sw reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_EXT_CLK_FO</name>
+              <description>xtal 32k external xtal clock force on</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_AUTO_BACKUP</name>
+              <description>xtal 32k switch to back up clock when xtal is dead</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_AUTO_RESTART</name>
+              <description>xtal 32k restart xtal when xtal is dead</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_AUTO_RETURN</name>
+              <description>xtal 32k switch back xtal when xtal is restarted</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_XPD_FORCE</name>
+              <description>Xtal 32k xpd control by sw or fsm</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCKINIT_XTAL_32K</name>
+              <description>apply an internal clock to help xtal 32k to start</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBUF_XTAL_32K</name>
+              <description>0: single-end buffer 1: differential buffer</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DGM_XTAL_32K</name>
+              <description>xtal_32k gm control</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRES_XTAL_32K</name>
+              <description>DRES_XTAL_32K</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_XTAL_32K</name>
+              <description>XPD_XTAL_32K</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DAC_XTAL_32K</name>
+              <description>DAC_XTAL_32K</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STATE</name>
+              <description>state of 32k_wdt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_GPIO_SEL</name>
+              <description>XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_LV</name>
+              <description>0: power down XTAL at high level, 1: power down XTAL at low level</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTL_EXT_CTR_EN</name>
+              <description>Reserved register</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP_CONF</name>
+          <description>ext wakeup configure</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GPIO_WAKEUP_FILTER</name>
+              <description>enable filter for gpio wakeup event</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP0_LV</name>
+              <description>0: external wakeup at low level, 1: external wakeup at high level</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP1_LV</name>
+              <description>0: external wakeup at low level, 1: external wakeup at high level</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_REJECT_CONF</name>
+          <description>reject sleep register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLEEP_REJECT_ENA</name>
+              <description>sleep reject enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LIGHT_SLP_REJECT_EN</name>
+              <description>enable reject for light sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEEP_SLP_REJECT_EN</name>
+              <description>enable reject for deep sleep</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERIOD_CONF</name>
+          <description>conigure cpu freq</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPUSEL_CONF</name>
+              <description>CPU sel option</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <description>conigure cpu freq</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_ACT_CONF</name>
+          <description>No public</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDIO_ACT_DNUM</name>
+              <description>No public</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>configure clock register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1158321C</resetValue>
+          <fields>
+            <field>
+              <name>EFUSE_CLK_FORCE_GATING</name>
+              <description>force efuse clk gating</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_CLK_FORCE_NOGATING</name>
+              <description>force efuse clk nogating</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV_SEL_VLD</name>
+              <description>used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV</name>
+              <description>CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_CK8M</name>
+              <description>disable CK8M and CK8M_D256_OUT</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENB_CK8M_DIV</name>
+              <description>1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_XTAL32K_EN</name>
+              <description>enable CK_XTAL_32K for digital core (no relationship with RTC core)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_D256_EN</name>
+              <description>enable CK8M_D256_OUT for digital core (no relationship with RTC core)</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIG_CLK8M_EN</name>
+              <description>enable CK8M for digital core (no relationship with RTC core)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DIV_SEL</name>
+              <description>divider = reg_ck8m_div_sel + 1</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_FORCE_NOGATING</name>
+              <description>XTAL force no gating during sleep</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_NOGATING</name>
+              <description>CK8M force no gating during sleep</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_DFREQ</name>
+              <description>CK8M_DFREQ</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PD</name>
+              <description>CK8M force power down</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK8M_FORCE_PU</name>
+              <description>CK8M force power up</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_GLOBAL_FORCE_GATING</name>
+              <description>force global xtal  gating</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL_GLOBAL_FORCE_NOGATING</name>
+              <description>force global xtal no gating</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FAST_CLK_RTC_SEL</name>
+              <description>fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANA_CLK_RTC_SEL</name>
+              <description>select slow clock</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLOW_CLK_CONF</name>
+          <description>configure slow clk</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00400000</resetValue>
+          <fields>
+            <field>
+              <name>ANA_CLK_DIV_VLD</name>
+              <description>used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ANA_CLK_DIV</name>
+              <description>rtc clk div</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOW_CLK_NEXT_EDGE</name>
+              <description>No public</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDIO_CONF</name>
+          <description>configure flash power</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0AB0BE0A</resetValue>
+          <fields>
+            <field>
+              <name>SDIO_TIMER_TARGET</name>
+              <description>timer count to apply reg_sdio_dcap after sdio power on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DTHDRV</name>
+              <description>Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DCAP</name>
+              <description>ability to prevent LDO from overshoot</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_INITI</name>
+              <description>add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_EN_INITI</name>
+              <description>0 to set init[1:0]=0</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_DCURLIM</name>
+              <description>tune current limit threshold when tieh = 0. About 800mA/(8+d)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_MODECURLIM</name>
+              <description>select current limit mode</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_ENCURLIM</name>
+              <description>enable current limit</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_REG_PD_EN</name>
+              <description>power down SDIO_REG in sleep. Only active when reg_sdio_force = 0</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_FORCE</name>
+              <description>1: use SW option to control SDIO_REG, 0: use state machine</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_TIEH</name>
+              <description>SW option for SDIO_TIEH. Only active when reg_sdio_force = 1</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG1P8_READY</name>
+              <description>read only register for REG1P8_READY</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DREFL_SDIO</name>
+              <description>SW option for DREFL_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DREFM_SDIO</name>
+              <description>SW option for DREFM_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DREFH_SDIO</name>
+              <description>SW option for DREFH_SDIO. Only active when reg_sdio_force = 1</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD_SDIO</name>
+              <description>power on flash regulator</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BIAS_CONF</name>
+          <description>No public</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010800</resetValue>
+          <fields>
+            <field>
+              <name>BIAS_BUF_IDLE</name>
+              <description>No public</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_WAKE</name>
+              <description>No public</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_DEEP_SLP</name>
+              <description>No public</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_BUF_MONITOR</name>
+              <description>No public</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_CUR_DEEP_SLP</name>
+              <description>xpd cur when rtc in sleep_state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_CUR_MONITOR</name>
+              <description>xpd cur when rtc in monitor state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_SLEEP_DEEP_SLP</name>
+              <description>bias_sleep when rtc in sleep_state</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIAS_SLEEP_MONITOR</name>
+              <description>bias_sleep when rtc in monitor state</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_DEEP_SLP</name>
+              <description>DBG_ATTEN when rtc in sleep state</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_MONITOR</name>
+              <description>DBG_ATTEN when rtc in monitor state</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBG_ATTEN_WAKEUP</name>
+              <description>No public</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC</name>
+          <description>configure rtc regulator</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xA0000000</resetValue>
+          <fields>
+            <field>
+              <name>DIG_REG_CAL_EN</name>
+              <description>enable dig regulator cali</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCK_DCAP</name>
+              <description>SCK_DCAP</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBOOST_FORCE_PD</name>
+              <description>RTC_DBOOST force power down</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBOOST_FORCE_PU</name>
+              <description>RTC_DBOOST force power up</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGULATOR_FORCE_PD</name>
+              <description>RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGULATOR_FORCE_PU</name>
+              <description>RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower )</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PWC</name>
+          <description>configure rtc power</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000925</resetValue>
+          <fields>
+            <field>
+              <name>FASTMEM_FORCE_NOISO</name>
+              <description>Fast RTC memory force no ISO</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_ISO</name>
+              <description>Fast RTC memory force ISO</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_NOISO</name>
+              <description>RTC memory force no ISO</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_ISO</name>
+              <description>RTC memory force ISO</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_ISO</name>
+              <description>rtc_peri force ISO</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_NOISO</name>
+              <description>rtc_peri force no ISO</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FOLW_CPU</name>
+              <description>1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_LPD</name>
+              <description>Fast RTC memory force PD</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTMEM_FORCE_LPU</name>
+              <description>Fast RTC memory force no PD</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FOLW_CPU</name>
+              <description>1: RTC memory  PD following CPU, 0: RTC memory PD following RTC state machine</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_LPD</name>
+              <description>RTC memory force PD</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLOWMEM_FORCE_LPU</name>
+              <description>RTC memory force no PD</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_PD</name>
+              <description>rtc_peri force power down</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_PU</name>
+              <description>rtc_peri force power up</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PD_EN</name>
+              <description>enable power down rtc_peri in sleep</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_FORCE_HOLD</name>
+              <description>rtc pad force hold</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGULATOR_DRV_CTRL</name>
+          <description>No public</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REGULATOR_DRV_B_MONITOR</name>
+              <description>No public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REGULATOR_DRV_B_SLP</name>
+              <description>No public</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_VDD_DRV_B_SLP</name>
+              <description>No public</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_VDD_DRV_B_MONITOR</name>
+              <description>No public</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PWC</name>
+          <description>configure digital power</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00545010</resetValue>
+          <fields>
+            <field>
+              <name>LSLP_MEM_FORCE_PD</name>
+              <description>memories in digital core force PD in sleep</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LSLP_MEM_FORCE_PU</name>
+              <description>memories in digital core force no PD in sleep</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_FORCE_PD</name>
+              <description>internal SRAM 2 force power down</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_FORCE_PU</name>
+              <description>internal SRAM 2 force power up</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_FORCE_PD</name>
+              <description>internal SRAM 3 force power down</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_FORCE_PU</name>
+              <description>internal SRAM 3 force power up</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_PD</name>
+              <description>wifi force power down</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_PU</name>
+              <description>wifi force power up</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PD</name>
+              <description>digital core force power down</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_PU</name>
+              <description>digital core force power up</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_FORCE_PD</name>
+              <description>digital dcdc force power down</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_FORCE_PU</name>
+              <description>digital dcdc force power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_PD_EN</name>
+              <description>enable power down internal SRAM 2 in sleep</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_PD_EN</name>
+              <description>enable power down internal SRAM 3 in sleep</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_PD_EN</name>
+              <description>enable power down internal SRAM 4 in sleep</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_PD_EN</name>
+              <description>enable power down wifi in sleep</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_PD_EN</name>
+              <description>enable power down all digital logic</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_ISO</name>
+          <description>congigure digital power isolation</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xAA805080</resetValue>
+          <fields>
+            <field>
+              <name>FORCE_OFF</name>
+              <description>No public</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_ON</name>
+              <description>No public</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD</name>
+              <description>read only register to indicate digital pad auto-hold status</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLR_DG_PAD_AUTOHOLD</name>
+              <description>wtite only register to clear digital pad auto-hold</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DG_PAD_AUTOHOLD_EN</name>
+              <description>digital pad enable auto-hold</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_NOISO</name>
+              <description>digital pad force no ISO</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_ISO</name>
+              <description>digital pad force ISO</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_UNHOLD</name>
+              <description>digital pad force un-hold</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PAD_FORCE_HOLD</name>
+              <description>digital pad force hold</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_FORCE_ISO</name>
+              <description>internal SRAM 2 force ISO</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_FORCE_NOISO</name>
+              <description>internal SRAM 2 force no ISO</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_FORCE_ISO</name>
+              <description>internal SRAM 3 force ISO</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_PERI_FORCE_NOISO</name>
+              <description>internal SRAM 3 force no ISO</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_FORCE_ISO</name>
+              <description>internal SRAM 4 force ISO</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_TOP_FORCE_NOISO</name>
+              <description>internal SRAM 4 force no ISO</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_ISO</name>
+              <description>wifi force ISO</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WIFI_FORCE_NOISO</name>
+              <description>wifi force no ISO</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_ISO</name>
+              <description>digital core force ISO</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DG_WRAP_FORCE_NOISO</name>
+              <description>digita core force no ISO</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>configure rtc watch dog</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013214</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CHIP_RESET_WIDTH</name>
+              <description>chip reset siginal pulse width</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CHIP_RESET_EN</name>
+              <description>wdt reset whole chip enable</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PAUSE_IN_SLP</name>
+              <description>pause WDT in sleep</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>enable WDT reset APP CPU</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>enable WDT reset PRO CPU</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>enable WDT in flash boot</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>system reset counter length</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>CPU reset counter length</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>enable rtc watch dog</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>stage0 hold time</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030D40</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>stage0 hold time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>stage1 hold time</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013880</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>stage1 hold time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>stage2 hold time</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>stage2 hold time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>stage3 hold time</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>stage3 hold time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>rtc wdt feed</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>rtc wdt feed</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>configure rtc watch dog</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>rtc watch dog key</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_CONF</name>
+          <description>congfigure super watch dog</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x04B00000</resetValue>
+          <fields>
+            <field>
+              <name>SWD_RESET_FLAG</name>
+              <description>swd reset flag</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_FEED_INT</name>
+              <description>swd interrupt for feeding</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SWD_BYPASS_RST</name>
+              <description>bypass super watch dog reset</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_SIGNAL_WIDTH</name>
+              <description>adjust signal width send to swd</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_RST_FLAG_CLR</name>
+              <description>reset swd reset flag</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_FEED</name>
+              <description>Sw feed swd</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_DISABLE</name>
+              <description>disabel SWD</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWD_AUTO_FEED_EN</name>
+              <description>automatically feed swd when int comes</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWD_WPROTECT</name>
+          <description>super watch dog key</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x8F1D312A</resetValue>
+          <fields>
+            <field>
+              <name>SWD_WKEY</name>
+              <description>super watch dog key</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SW_CPU_STALL</name>
+          <description>configure cpu stall by sw</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_STALL_APPCPU_C1</name>
+              <description>{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_STALL_PROCPU_C1</name>
+              <description>{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE4</name>
+          <description>reserved register</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH4</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE5</name>
+          <description>reserved register</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH5</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE6</name>
+          <description>reserved register</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH6</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STORE7</name>
+          <description>reserved register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCRATCH7</name>
+              <description>reserved register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOW_POWER_ST</name>
+          <description>reserved register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XPD_ROM0</name>
+              <description>rom0 power down</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_DIG_DCDC</name>
+              <description>External DCDC power down</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERI_ISO</name>
+              <description>rtc peripheral iso</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_RTC_PERI</name>
+              <description>rtc peripheral power down</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WIFI_ISO</name>
+              <description>wifi iso</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_WIFI</name>
+              <description>wifi wrap power down</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DIG_ISO</name>
+              <description>digital wrap iso</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>XPD_DIG</name>
+              <description>digital wrap power down</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_START</name>
+              <description>touch should start to work</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_SWITCH</name>
+              <description>touch is about to working. Switch rtc main state</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_SLP</name>
+              <description>touch is in sleep state</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOUCH_STATE_DONE</name>
+              <description>touch is done</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_START</name>
+              <description>ulp/cocpu should start to work</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_SWITCH</name>
+              <description>ulp/cocpu is about to working. Switch rtc main state</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_SLP</name>
+              <description>ulp/cocpu is in sleep state</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>COCPU_STATE_DONE</name>
+              <description>ulp/cocpu is done</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_XTAL_ISO</name>
+              <description>no use any more</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_PLL_ON</name>
+              <description>rtc main state machine is in states that pll should be running</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RDY_FOR_WAKEUP</name>
+              <description>rtc is ready to receive wake up trigger from wake up source</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_WAIT_END</name>
+              <description>rtc main state machine has been waited for some cycles</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_WAKEUP_STATE</name>
+              <description>rtc main state machine is in the states of wakeup process</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_LOW_POWER_STATE</name>
+              <description>rtc main state machine is in the states of low power</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_8M</name>
+              <description>rtc main state machine is in wait 8m state</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_PLL</name>
+              <description>rtc main state machine is in wait pll state</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_WAIT_XTL</name>
+              <description>rtc main state machine is in wait xtal state</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_SLP</name>
+              <description>rtc main state machine is in sleep state</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE_IN_IDLE</name>
+              <description>rtc main state machine is in idle state</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MAIN_STATE</name>
+              <description>rtc main state machine status</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIAG0</name>
+          <description>No public</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOW_POWER_DIAG1</name>
+              <description>No public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_HOLD</name>
+          <description>rtc pad hold configure</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD0_HOLD</name>
+              <description>hold rtc pad0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD1_HOLD</name>
+              <description>hold rtc pad-1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD2_HOLD</name>
+              <description>hold rtc pad-2</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD3_HOLD</name>
+              <description>hold rtc pad-3</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD4_HOLD</name>
+              <description>hold rtc pad-4</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD5_HOLD</name>
+              <description>hold rtc pad-5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD6_HOLD</name>
+              <description>hold rtc pad-6</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD7_HOLD</name>
+              <description>hold rtc pad-7</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD8_HOLD</name>
+              <description>hold rtc pad-8</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD9_HOLD</name>
+              <description>hold rtc pad-9</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD10_HOLD</name>
+              <description>hold rtc pad-10</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD11_HOLD</name>
+              <description>hold rtc pad-11</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD12_HOLD</name>
+              <description>hold rtc pad-12</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD13_HOLD</name>
+              <description>hold rtc pad-13</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD14_HOLD</name>
+              <description>hold rtc pad-14</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_HOLD</name>
+              <description>hold rtc pad-15</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_HOLD</name>
+              <description>hold rtc pad-16</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_HOLD</name>
+              <description>hold rtc pad-17</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_HOLD</name>
+              <description>hold rtc pad-18</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD19_HOLD</name>
+              <description>hold rtc pad-19</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD20_HOLD</name>
+              <description>hold rtc pad-20</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD21_HOLD</name>
+              <description>hold rtc pad-21</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIG_PAD_HOLD</name>
+          <description>configure digtal pad hold</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIG_PAD_HOLD</name>
+              <description>configure digtal pad hold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP1</name>
+          <description>configure ext1 wakeup</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_WAKEUP1_SEL</name>
+              <description>Bitmap to select RTC pads for ext wakeup1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXT_WAKEUP1_STATUS_CLR</name>
+              <description>clear ext wakeup1 status</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP1_STATUS</name>
+          <description>check ext wakeup1 status</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_WAKEUP1_STATUS</name>
+              <description>ext wakeup1 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BROWN_OUT</name>
+          <description>congfigure brownout</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x43FF0010</resetValue>
+          <fields>
+            <field>
+              <name>BROWN_OUT_INT_WAIT</name>
+              <description>brown out interrupt wait cycles</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_CLOSE_FLASH_ENA</name>
+              <description>enable close flash when brown out happens</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_PD_RF_ENA</name>
+              <description>enable power down RF when brown out happens</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_RST_WAIT</name>
+              <description>brown out reset wait cycles</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_RST_ENA</name>
+              <description>enable brown out reset</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_RST_SEL</name>
+              <description>1:  4-pos reset,    0:  sys_reset</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_ANA_RST_EN</name>
+              <description>enable brown out reset en</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_CNT_CLR</name>
+              <description>clear brown out counter</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_ENA</name>
+              <description>enable brown out</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DET</name>
+              <description>get brown out detect</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_LOW1</name>
+          <description>RTC timer low 32 bits</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE1_LOW</name>
+              <description>RTC timer low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIME_HIGH1</name>
+          <description>RTC timer high 16 bits</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_VALUE1_HIGH</name>
+              <description>RTC timer high 16 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL32K_CLK_FACTOR</name>
+          <description>xtal 32k watch dog backup clock factor</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XTAL32K_CLK_FACTOR</name>
+              <description>xtal 32k watch dog backup clock factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL32K_CONF</name>
+          <description>configure xtal32k</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0FF00000</resetValue>
+          <fields>
+            <field>
+              <name>XTAL32K_RETURN_WAIT</name>
+              <description>cycles to wait to return noral xtal 32k</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_RESTART_WAIT</name>
+              <description>cycles to wait to repower on xtal 32k</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_WDT_TIMEOUT</name>
+              <description>If no clock detected for this amount of time 32k is regarded as dead</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XTAL32K_STABLE_THRES</name>
+              <description>if restarted xtal32k period is smaller than this, it is regarded as stable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_TIMER</name>
+          <description>configure ulp</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ULP_CP_PC_INIT</name>
+              <description>ULP-coprocessor PC initial address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_GPIO_WAKEUP_ENA</name>
+              <description>ULP-coprocessor wakeup by GPIO enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_GPIO_WAKEUP_CLR</name>
+              <description>ULP-coprocessor wakeup by GPIO state clear</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_SLP_TIMER_EN</name>
+              <description>ULP-coprocessor timer enable bit</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_CTRL</name>
+          <description>configure ulp</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00100200</resetValue>
+          <fields>
+            <field>
+              <name>ULP_CP_MEM_ADDR_INIT</name>
+              <description>No public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_MEM_ADDR_SIZE</name>
+              <description>No public</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_MEM_OFFST_CLR</name>
+              <description>No public</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_CLK_FO</name>
+              <description>ulp coprocessor clk force on</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_RESET</name>
+              <description>ulp coprocessor clk software reset</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_FORCE_START_TOP</name>
+              <description>1: ULP-coprocessor is started by SW</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULP_CP_START_TOP</name>
+              <description>Write 1 to start ULP-coprocessor</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COCPU_CTRL</name>
+          <description>configure ulp-riscv</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x008A0810</resetValue>
+          <fields>
+            <field>
+              <name>COCPU_CLK_FO</name>
+              <description>cocpu clk force on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_START_2_RESET_DIS</name>
+              <description>time from start cocpu to pull down reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_START_2_INTR_EN</name>
+              <description>time from start cocpu to give start interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SHUT</name>
+              <description>to shut cocpu</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SHUT_2_CLK_DIS</name>
+              <description>time from shut cocpu to disable clk</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SHUT_RESET_EN</name>
+              <description>to reset cocpu</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SEL</name>
+              <description>1: old ULP 0: new riscV</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_DONE_FORCE</name>
+              <description>1: select riscv done 0: select ulp done</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_DONE</name>
+              <description>done signal used by riscv to control timer.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COCPU_SW_INT_TRIGGER</name>
+              <description>trigger cocpu register interrupt</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_CLKGATE_EN</name>
+              <description>open ulp-riscv clk gate</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_CTRL1</name>
+          <description>configure touch controller</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000100</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_SLEEP_CYCLES</name>
+              <description>sleep cycles for timer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_MEAS_NUM</name>
+              <description>the meas length (in 8MHz)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_CTRL2</name>
+          <description>configure touch controller</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000840CC</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_DRANGE</name>
+              <description>TOUCH_DRANGE</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DREFL</name>
+              <description>TOUCH_DREFL</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DREFH</name>
+              <description>TOUCH_DREFH</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_XPD_BIAS</name>
+              <description>TOUCH_XPD_BIAS</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_REFC</name>
+              <description>TOUCH pad0 reference cap</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DBIAS</name>
+              <description>1:use self bias 0:use bandgap bias</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_TIMER_EN</name>
+              <description>touch timer enable bit</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_START_FSM_EN</name>
+              <description>1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_START_EN</name>
+              <description>1: start touch fsm</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_START_FORCE</name>
+              <description>1: to start touch fsm by SW</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_XPD_WAIT</name>
+              <description>the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_CYC_DIV</name>
+              <description>when a touch pad is active sleep cycle could be divided by this number</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMER_FORCE_DONE</name>
+              <description>force touch timer done</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_RESET</name>
+              <description>reset upgrade touch</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_CLK_FO</name>
+              <description>touch clock force on</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_CLKGATE_EN</name>
+              <description>touch clock enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_SCAN_CTRL</name>
+          <description>configure touch controller</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xF0000102</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_DENOISE_RES</name>
+              <description>De-noise resolution: 12/10/8/4 bit</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DENOISE_EN</name>
+              <description>touch pad0 will be used to de-noise</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_CONNECTION</name>
+              <description>inactive touch pads connect to 1: gnd 0: HighZ</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SHIELD_PAD_EN</name>
+              <description>touch pad14 will be used as shield</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_PAD_MAP</name>
+              <description>touch scan mode pad enable map</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_BUFDRV</name>
+              <description>touch7 buffer driver strength</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_OUT_RING</name>
+              <description>select out ring pad</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_SLP_THRES</name>
+          <description>configure touch controller</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x78000000</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_SLP_TH</name>
+              <description>the threshold for sleep touch pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_APPROACH_EN</name>
+              <description>sleep pad approach function enable</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SLP_PAD</name>
+              <description>configure which pad as slp pad</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_APPROACH</name>
+          <description>configure touch controller</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_SLP_CHANNEL_CLR</name>
+              <description>clear touch slp channel</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_MEAS_TIME</name>
+              <description>approach pads total meas times</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_FILTER_CTRL</name>
+          <description>configure touch controller</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x96AA8800</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_BYPASS_NEG_NOISE_THRES</name>
+              <description>bypass neg noise thres</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_BYPASS_NOISE_THRES</name>
+              <description>bypaas noise thres</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_SMOOTH_LVL</name>
+              <description>smooth filter factor</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_JITTER_STEP</name>
+              <description>touch jitter step</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_NEG_NOISE_LIMIT</name>
+              <description>negative threshold counter limit</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_NEG_NOISE_THRES</name>
+              <description>neg noise thres</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_NOISE_THRES</name>
+              <description>noise thres</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_HYSTERESIS</name>
+              <description>hysteresis</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_DEBOUNCE</name>
+              <description>debounce counter</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_FILTER_MODE</name>
+              <description>0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_FILTER_EN</name>
+              <description>touch filter enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USB_CONF</name>
+          <description>usb configure</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USB_VREFH</name>
+              <description>reg_usb_vrefh</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_VREFL</name>
+              <description>reg_usb_vrefl</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_VREF_OVERRIDE</name>
+              <description>reg_usb_vref_override</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_PULL_OVERRIDE</name>
+              <description>reg_usb_pad_pull_override</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DP_PULLUP</name>
+              <description>reg_usb_dp_pullup</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DP_PULLDOWN</name>
+              <description>reg_usb_dp_pulldown</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DM_PULLUP</name>
+              <description>reg_usb_dm_pullup</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DM_PULLDOWN</name>
+              <description>reg_usb_dm_pulldown</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PULLUP_VALUE</name>
+              <description>reg_usb_pullup_value</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_ENABLE_OVERRIDE</name>
+              <description>reg_usb_pad_enable_override</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_ENABLE</name>
+              <description>reg_usb_pad_enable</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_TXM</name>
+              <description>reg_usb_txm</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_TXP</name>
+              <description>reg_usb_txp</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_TX_EN</name>
+              <description>reg_usb_tx_en</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_TX_EN_OVERRIDE</name>
+              <description>reg_usb_tx_en_override</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_RESET_DISABLE</name>
+              <description>reg_usb_reset_disable</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IO_MUX_RESET_DISABLE</name>
+              <description>reg_io_mux_reset_disable</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_USB_PHY_SEL</name>
+              <description>reg_sw_usb_phy_sel</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_HW_USB_PHY_SEL</name>
+              <description>reg_sw_hw_usb_phy_sel</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_TIMEOUT_CTRL</name>
+          <description>configure touch controller</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x007FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>TOUCH_TIMEOUT_NUM</name>
+              <description>configure touch timerout time</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_EN</name>
+              <description>enable touch timerout</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_REJECT_CAUSE</name>
+          <description>get reject casue</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REJECT_CAUSE</name>
+              <description>sleep reject cause</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OPTION1</name>
+          <description>rtc common configure</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FORCE_DOWNLOAD_BOOT</name>
+              <description>force chip entry download boot by sw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLP_WAKEUP_CAUSE</name>
+          <description>get wakeup cause</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WAKEUP_CAUSE</name>
+              <description>sleep wakeup cause</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>17</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ULP_CP_TIMER_1</name>
+          <description>configure ulp sleep time</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000C800</resetValue>
+          <fields>
+            <field>
+              <name>ULP_CP_TIMER_SLP_CYCLE</name>
+              <description>sleep cycles for ULP-coprocessor timer</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC_W1TS</name>
+          <description>oneset rtc interrupt</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA_W1TS</name>
+              <description>enable sleep wakeup interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA_W1TS</name>
+              <description>enable sleep reject interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ENA_W1TS</name>
+              <description>enable SDIO idle interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA_W1TS</name>
+              <description>enable RTC WDT interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_ENA_W1TS</name>
+              <description>enable touch scan done interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_ENA_W1TS</name>
+              <description>enable ULP-coprocessor interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_ENA_W1TS</name>
+              <description>enable touch done interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_ENA_W1TS</name>
+              <description>enable touch active interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_ENA_W1TS</name>
+              <description>enable touch inactive interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA_W1TS</name>
+              <description>enable brown out interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA_W1TS</name>
+              <description>enable RTC main timer interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_ENA_W1TS</name>
+              <description>enable saradc1 interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TSENS_INT_ENA_W1TS</name>
+              <description>enable tsens interrupt</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_INT_ENA_W1TS</name>
+              <description>enable riscV cocpu interrupt</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_ENA_W1TS</name>
+              <description>enable saradc2 interrupt</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_ENA_W1TS</name>
+              <description>enable super watch dog interrupt</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ENA_W1TS</name>
+              <description>enable xtal32k_dead  interrupt</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_ENA_W1TS</name>
+              <description>enable cocpu trap interrupt</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_ENA_W1TS</name>
+              <description>enable touch timeout interrupt</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA_W1TS</name>
+              <description>enbale gitch det interrupt</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS</name>
+              <description>enbale touch approach_loop done interrupt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_RTC_W1TC</name>
+          <description>oneset clr rtc interrupt enable</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLP_WAKEUP_INT_ENA_W1TC</name>
+              <description>enable sleep wakeup interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLP_REJECT_INT_ENA_W1TC</name>
+              <description>enable sleep reject interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SDIO_IDLE_INT_ENA_W1TC</name>
+              <description>enable SDIO idle interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA_W1TC</name>
+              <description>enable RTC WDT interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_SCAN_DONE_INT_ENA_W1TC</name>
+              <description>enable touch scan done interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ULP_CP_INT_ENA_W1TC</name>
+              <description>enable ULP-coprocessor interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_DONE_INT_ENA_W1TC</name>
+              <description>enable touch done interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_ACTIVE_INT_ENA_W1TC</name>
+              <description>enable touch active interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_INACTIVE_INT_ENA_W1TC</name>
+              <description>enable touch inactive interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA_W1TC</name>
+              <description>enable brown out interrupt</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MAIN_TIMER_INT_ENA_W1TC</name>
+              <description>enable RTC main timer interrupt</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SARADC1_INT_ENA_W1TC</name>
+              <description>enable saradc1 interrupt</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TSENS_INT_ENA_W1TC</name>
+              <description>enable tsens interrupt</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_INT_ENA_W1TC</name>
+              <description>enable riscV cocpu interrupt</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SARADC2_INT_ENA_W1TC</name>
+              <description>enable saradc2 interrupt</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SWD_INT_ENA_W1TC</name>
+              <description>enable super watch dog interrupt</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>XTAL32K_DEAD_INT_ENA_W1TC</name>
+              <description>enable xtal32k_dead  interrupt</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COCPU_TRAP_INT_ENA_W1TC</name>
+              <description>enable cocpu trap interrupt</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_TIMEOUT_INT_ENA_W1TC</name>
+              <description>enable touch timeout interrupt</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA_W1TC</name>
+              <description>enbale gitch det interrupt</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC</name>
+              <description>enbale touch approach_loop done interrupt</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_CTRL</name>
+          <description>configure retention</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x28340000</resetValue>
+          <fields>
+            <field>
+              <name>RETENTION_TAG_MODE</name>
+              <description>No public</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_TARGET</name>
+              <description>congfigure retention target cpu and/or tag</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_CLK_SEL</name>
+              <description>No public</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_DONE_WAIT</name>
+              <description>wait retention done cycle</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_CLKOFF_WAIT</name>
+              <description>wait clk off cycle</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_EN</name>
+              <description>enable retention</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RETENTION_WAIT</name>
+              <description>wait cycles for rention operation</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PG_CTRL</name>
+          <description>configure power glitch</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>POWER_GLITCH_DSENSE</name>
+              <description>GLITCH_DSENSE</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_FORCE_PD</name>
+              <description>force power glitch disable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_FORCE_PU</name>
+              <description>force power glitch enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_EFUSE_SEL</name>
+              <description>select use analog fib signal</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>POWER_GLITCH_EN</name>
+              <description>enable power glitch</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FIB_SEL</name>
+          <description>No public</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000007</resetValue>
+          <fields>
+            <field>
+              <name>FIB_SEL</name>
+              <description>No public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_DAC</name>
+          <description>configure touch dac</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD9_DAC</name>
+              <description>configure touch pad dac9</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD8_DAC</name>
+              <description>configure touch pad dac8</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD7_DAC</name>
+              <description>configure touch pad dac7</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD6_DAC</name>
+              <description>configure touch pad dac6</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD5_DAC</name>
+              <description>configure touch pad dac5</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD4_DAC</name>
+              <description>configure touch pad dac4</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD3_DAC</name>
+              <description>configure touch pad dac3</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD2_DAC</name>
+              <description>configure touch pad dac2</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD1_DAC</name>
+              <description>configure touch pad dac1</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD0_DAC</name>
+              <description>configure touch pad dac0</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_DAC1</name>
+          <description>configure touch dac</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOUCH_PAD14_DAC</name>
+              <description>configure touch pad dac14</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD13_DAC</name>
+              <description>configure touch pad dac13</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD12_DAC</name>
+              <description>configure touch pad dac12</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD11_DAC</name>
+              <description>configure touch pad dac11</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOUCH_PAD10_DAC</name>
+              <description>configure touch pad dac10</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COCPU_DISABLE</name>
+          <description>configure ulp diable</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DISABLE_RTC_CPU</name>
+              <description>configure ulp diable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101271</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC_I2C</name>
+      <description>Peripheral RTC_I2C</description>
+      <groupName>RTC_I2C</groupName>
+      <baseAddress>0x60008C00</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x7C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SCL_LOW</name>
+          <description>configure low scl period</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>PERIOD</name>
+              <description>time period that scl =0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>configure i2c ctrl</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SDA_FORCE_OUT</name>
+              <description>1=push pull,0=open drain</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCL_FORCE_OUT</name>
+              <description>1=push pull,0=open drain</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MS_MODE</name>
+              <description>1=master,0=slave</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_START</name>
+              <description>force start</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_LSB_FIRST</name>
+              <description>transit lsb first</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_LSB_FIRST</name>
+              <description>receive lsb first</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_CTRL_CLK_GATE_EN</name>
+              <description>configure i2c ctrl clk enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_RESET</name>
+              <description>rtc i2c sw reset</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2CCLK_EN</name>
+              <description>rtc i2c reg clk gating</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>get i2c status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ACK_REC</name>
+              <description>ack response</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_RW</name>
+              <description>slave read or write</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST</name>
+              <description>arbitration is lost</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_BUSY</name>
+              <description>bus is busy</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_ADDRESSED</name>
+              <description>slave reg sub address</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BYTE_TRANS</name>
+              <description>One byte transit done</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OP_CNT</name>
+              <description>which operation is working</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SHIFT</name>
+              <description>shifter content</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_MAIN_STATE_LAST</name>
+              <description>i2c last main status</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SCL_STATE_LAST</name>
+              <description>scl last status</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TO</name>
+          <description>configure time out</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>TIME_OUT</name>
+              <description>time out threshold</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE_ADDR</name>
+          <description>configure slave id</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_ADDR</name>
+              <description>slave address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_10BIT_EN</name>
+              <description>i2c 10bit mode enable</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_HIGH</name>
+          <description>configure high scl period</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>PERIOD</name>
+              <description>time period that scl = 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SDA_DUTY</name>
+          <description>configure sda duty</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000010</resetValue>
+          <fields>
+            <field>
+              <name>NUM</name>
+              <description>time period for SDA to toggle after SCL goes low</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_START_PERIOD</name>
+          <description>configure scl start period</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>SCL_START_PERIOD</name>
+              <description>time period for SCL to toggle after I2C start is triggered</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SCL_STOP_PERIOD</name>
+          <description>configure scl stop period</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>SCL_STOP_PERIOD</name>
+              <description>time period for SCL to stop after I2C end is triggered</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>interrupt clear register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_CLR</name>
+              <description>clear slave transit complete interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_CLR</name>
+              <description>clear arbitration lost interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_CLR</name>
+              <description>clear master transit complete interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_CLR</name>
+              <description>clear transit complete interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_CLR</name>
+              <description>clear time out interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_CLR</name>
+              <description>clear ack error interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_DATA_INT_CLR</name>
+              <description>clear receive data interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DATA_INT_CLR</name>
+              <description>clear transit load data complete interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DETECT_START_INT_CLR</name>
+              <description>clear detect start interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>interrupt raw register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_RAW</name>
+              <description>slave transit complete interrupt raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_RAW</name>
+              <description>arbitration lost interrupt raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_RAW</name>
+              <description>master transit complete interrupt raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_RAW</name>
+              <description>transit complete interrupt raw</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_RAW</name>
+              <description>time out interrupt raw</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_RAW</name>
+              <description>ack error interrupt raw</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_DATA_INT_RAW</name>
+              <description>receive data interrupt raw</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DATA_INT_RAW</name>
+              <description>transit data interrupt raw</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DETECT_START_INT_RAW</name>
+              <description>detect start interrupt raw</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>interrupt state register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_ST</name>
+              <description>slave transit complete interrupt state</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ST</name>
+              <description>arbitration lost interrupt state</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_ST</name>
+              <description>master transit complete interrupt state</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ST</name>
+              <description>transit complete interrupt state</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ST</name>
+              <description>time out interrupt state</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_ST</name>
+              <description>ack error interrupt state</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_DATA_INT_ST</name>
+              <description>receive data interrupt state</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DATA_INT_ST</name>
+              <description>transit data interrupt state</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DETECT_START_INT_ST</name>
+              <description>detect start interrupt state</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>interrupt enable register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLAVE_TRAN_COMP_INT_ENA</name>
+              <description>enable slave transit complete interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBITRATION_LOST_INT_ENA</name>
+              <description>enable arbitration lost interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_TRAN_COMP_INT_ENA</name>
+              <description>enable master transit complete interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_COMPLETE_INT_ENA</name>
+              <description>enable transit complete interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_OUT_INT_ENA</name>
+              <description>enable time out interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ACK_ERR_INT_ENA</name>
+              <description>enable eack error interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DATA_INT_ENA</name>
+              <description>enable receive data interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DATA_INT_ENA</name>
+              <description>enable transit data interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DETECT_START_INT_ENA</name>
+              <description>enable detect start interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA</name>
+          <description>get i2c data status</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>I2C_RDATA</name>
+              <description>data received</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLAVE_TX_DATA</name>
+              <description>data sent by slave</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_DONE</name>
+              <description>i2c done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD0</name>
+          <description>i2c commond0 register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000903</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND0</name>
+              <description>command0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND0_DONE</name>
+              <description>command0_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD1</name>
+          <description>i2c commond1 register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001901</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND1</name>
+              <description>command1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND1_DONE</name>
+              <description>command1_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD2</name>
+          <description>i2c commond2 register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000902</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND2</name>
+              <description>command2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND2_DONE</name>
+              <description>command2_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD3</name>
+          <description>i2c commond3 register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000101</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND3</name>
+              <description>command3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND3_DONE</name>
+              <description>command3_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD4</name>
+          <description>i2c commond4 register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND4</name>
+              <description>command4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND4_DONE</name>
+              <description>command4_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD5</name>
+          <description>i2c commond5_register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001701</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND5</name>
+              <description>command5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND5_DONE</name>
+              <description>command5_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD6</name>
+          <description>i2c commond6 register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001901</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND6</name>
+              <description>command6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND6_DONE</name>
+              <description>command6_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD7</name>
+          <description>i2c commond7 register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000904</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND7</name>
+              <description>command7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND7_DONE</name>
+              <description>command7_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD8</name>
+          <description>i2c commond8 register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001901</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND8</name>
+              <description>command8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND8_DONE</name>
+              <description>command8_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD9</name>
+          <description>i2c commond9 register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000903</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND9</name>
+              <description>command9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND9_DONE</name>
+              <description>command9_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD10</name>
+          <description>i2c commond10 register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000101</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND10</name>
+              <description>command10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND10_DONE</name>
+              <description>command10_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD11</name>
+          <description>i2c commond11 register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND11</name>
+              <description>command11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND11_DONE</name>
+              <description>command11_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD12</name>
+          <description>i2c commond12 register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001701</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND12</name>
+              <description>command12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND12_DONE</name>
+              <description>command12_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD13</name>
+          <description>i2c commond13 register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001901</resetValue>
+          <fields>
+            <field>
+              <name>COMMAND13</name>
+              <description>command13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND13_DONE</name>
+              <description>command13_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD14</name>
+          <description>i2c commond14 register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND14</name>
+              <description>command14</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND14_DONE</name>
+              <description>command14_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD15</name>
+          <description>i2c commond15 register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMMAND15</name>
+              <description>command15</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMMAND15_DONE</name>
+              <description>command15_done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01905310</resetValue>
+          <fields>
+            <field>
+              <name>I2C_DATE</name>
+              <description>version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTCIO</name>
+      <description>Peripheral RTC_IO</description>
+      <groupName>RTC_IO</groupName>
+      <baseAddress>0x60008400</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xF0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>RTC_GPIO_OUT</name>
+          <description>RTC GPIO 0 ~ 21 output data register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>RTC GPIO 0 ~ 21 output data</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_OUT_W1TS</name>
+          <description>one set RTC GPIO output data</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_GPIO_OUT_DATA_W1TS</name>
+              <description>RTC GPIO 0 ~ 21 output data write 1 to set</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_OUT_W1TC</name>
+          <description>one clear RTC GPIO output data</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_GPIO_OUT_DATA_W1TC</name>
+              <description>RTC GPIO 0 ~ 21 output data write 1 to clear</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_ENABLE</name>
+          <description>Configure RTC GPIO output enable</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_GPIO_ENABLE</name>
+              <description>RTC GPIO 0 ~ 21 enable</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_ENABLE_W1TS</name>
+          <description>one set RTC GPIO output enable</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_GPIO_ENABLE_W1TS</name>
+              <description>RTC GPIO 0 ~ 21 enable write 1 to set</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ENABLE_W1TC</name>
+          <description>one clear RTC GPIO output enable</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_W1TC</name>
+              <description>RTC GPIO 0 ~ 21 enable write 1 to clear</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_STATUS</name>
+          <description>RTC GPIO 0 ~ 21 interrupt status</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INT</name>
+              <description>RTC GPIO 0 ~ 21 interrupt status</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_STATUS_W1TS</name>
+          <description>One set RTC GPIO 0 ~ 21 interrupt status</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_GPIO_STATUS_INT_W1TS</name>
+              <description>RTC GPIO 0 ~ 21 interrupt status write 1 to set</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_STATUS_W1TC</name>
+          <description>One clear RTC GPIO 0 ~ 21 interrupt status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_GPIO_STATUS_INT_W1TC</name>
+              <description>RTC GPIO 0 ~ 21 interrupt status write 1 to clear</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_GPIO_IN</name>
+          <description>RTC GPIO input data</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>NEXT</name>
+              <description>RTC GPIO input data</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>22</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <dimIndex>0-21</dimIndex>
+          <name>PIN%s</name>
+          <description>configure RTC GPIO%s</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PAD_DRIVER</name>
+              <description>if set to 0: normal output, if set to 1: open drain</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INT_TYPE</name>
+              <description>if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger,  if set to 5: high level trigger</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_ENABLE</name>
+              <description>RTC GPIO wakeup enable bit</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_DEBUG_SEL</name>
+          <description>configure rtc debug</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_DEBUG_SEL0</name>
+              <description>configure rtc debug</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_SEL1</name>
+              <description>configure rtc debug</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_SEL2</name>
+              <description>configure rtc debug</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_SEL3</name>
+              <description>configure rtc debug</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_SEL4</name>
+              <description>configure rtc debug</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_DEBUG_12M_NO_GATING</name>
+              <description>configure rtc debug</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD0</name>
+          <description>configure RTC  PAD0</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD1</name>
+          <description>configure RTC  PAD1</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x48000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD2</name>
+          <description>configure RTC  PAD2</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD3</name>
+          <description>configure RTC  PAD3</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x48000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD4</name>
+          <description>configure RTC  PAD4</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD5</name>
+          <description>configure RTC  PAD5</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD6</name>
+          <description>configure RTC  PAD6</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x48000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD7</name>
+          <description>configure RTC  PAD7</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD8</name>
+          <description>configure RTC  PAD8</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD9</name>
+          <description>configure RTC  PAD9</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD10</name>
+          <description>configure RTC  PAD10</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD11</name>
+          <description>configure RTC  PAD11</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD12</name>
+          <description>configure RTC  PAD12</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD13</name>
+          <description>configure RTC  PAD13</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_PAD14</name>
+          <description>configure RTC  PAD14</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XPD</name>
+              <description>TOUCH_XPD</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIE_OPT</name>
+              <description>TOUCH_TIE_OPT</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>START</name>
+              <description>TOUCH_START</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL_32P_PAD</name>
+          <description>configure RTC  PAD15</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>X32P_FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32P_DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTAL_32N_PAD</name>
+          <description>configure RTC  PAD16</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>X32N_FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>X32N_DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_DAC1</name>
+          <description>configure RTC  PAD17</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>PDAC1_DAC</name>
+              <description>PDAC1_DAC</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_XPD_DAC</name>
+              <description>PDAC1_XPD_DAC</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_DAC_XPD_FORCE</name>
+              <description>1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_FUN_SEL</name>
+              <description>PDAC1 function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_RUE</name>
+              <description>PDAC1_RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_RDE</name>
+              <description>PDAC1_RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC1_DRV</name>
+              <description>PDAC1_DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PAD_DAC2</name>
+          <description>configure RTC  PAD18</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000000</resetValue>
+          <fields>
+            <field>
+              <name>PDAC2_DAC</name>
+              <description>PDAC2_DAC</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_XPD_DAC</name>
+              <description>PDAC2_XPD_DAC</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_DAC_XPD_FORCE</name>
+              <description>1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_FUN_SEL</name>
+              <description>PDAC1 function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_RUE</name>
+              <description>PDAC2_RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_RDE</name>
+              <description>PDAC2_RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PDAC2_DRV</name>
+              <description>PDAC2_DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_PAD19</name>
+          <description>configure RTC  PAD19</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_PAD20</name>
+          <description>configure RTC  PAD20</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_PAD21</name>
+          <description>configure RTC  PAD21</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50000000</resetValue>
+          <fields>
+            <field>
+              <name>FUN_IE</name>
+              <description>input enable in work mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_OE</name>
+              <description>output enable in sleep mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_IE</name>
+              <description>input enable in sleep mode</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLP_SEL</name>
+              <description>1: enable sleep mode during sleep,0: no sleep mode</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FUN_SEL</name>
+              <description>function sel</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MUX_SEL</name>
+              <description>1: use RTC GPIO,0: use digital GPIO</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RUE</name>
+              <description>RUE</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDE</name>
+              <description>RDE</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DRV</name>
+              <description>DRV</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_WAKEUP0</name>
+          <description>configure EXT0 wakeup</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>******* Description configure***</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>XTL_EXT_CTR</name>
+          <description>configure gpio pd XTAL</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEL</name>
+              <description>select RTC GPIO 0 ~ 17 to control XTAL</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_I2C_IO</name>
+          <description>configure rtc i2c mux</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_DEBUG_BIT_SEL</name>
+              <description>******* Description configure***</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SCL_SEL</name>
+              <description>******* Description configure***</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SDA_SEL</name>
+              <description>******* Description configure***</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TOUCH_CTRL</name>
+          <description>configure touch pad bufmode</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>IO_TOUCH_BUFSEL</name>
+              <description>BUF_SEL when touch work without fsm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IO_TOUCH_BUFMODE</name>
+              <description>BUF_MODE when touch work without fsm</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101180</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SENS</name>
+      <description>Peripheral SENS</description>
+      <groupName>SENS</groupName>
+      <baseAddress>0x60008800</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x11C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SAR_READER1_CTRL</name>
+          <description>configure saradc1 reader</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20040002</resetValue>
+          <fields>
+            <field>
+              <name>SAR_SAR1_CLK_DIV</name>
+              <description>clock divider</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR1_CLK_GATED</name>
+              <description>no public</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR1_SAMPLE_NUM</name>
+              <description>no public</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR1_DATA_INV</name>
+              <description>Invert SAR ADC1 data</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR1_INT_EN</name>
+              <description>enable saradc1 to send out interrupt</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_READER1_STATUS</name>
+          <description>get saradc1 reader controller status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_SAR1_READER_STATUS</name>
+              <description>get saradc1 reader controller status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS1_CTRL1</name>
+          <description>no public</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_FORCE_XPD_AMP</name>
+              <description>no public</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_RST_FB_FORCE</name>
+              <description>no public</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_SHORT_REF_FORCE</name>
+              <description>no public</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_SHORT_REF_GND_FORCE</name>
+              <description>no public</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS1_CTRL2</name>
+          <description>configure saradc1 controller</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_MEAS1_DATA_SAR</name>
+              <description>SAR ADC1 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_MEAS1_DONE_SAR</name>
+              <description>SAR ADC1 conversion done indication</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_MEAS1_START_SAR</name>
+              <description>SAR ADC1 controller (in RTC) starts conversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_MEAS1_START_FORCE</name>
+              <description>1: SAR ADC1 controller (in RTC) is started by SW</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR1_EN_PAD</name>
+              <description>SAR ADC1 pad enable bitmap</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR1_EN_PAD_FORCE</name>
+              <description>1: SAR ADC1 pad enable bitmap is controlled by SW</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS1_MUX</name>
+          <description>configure saradc1 controller</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_SAR1_DIG_FORCE</name>
+              <description>1: SAR ADC1 controlled by DIG ADC1 CTRL</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_ATTEN1</name>
+          <description>configure saradc1 controller</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SAR_SAR1_ATTEN</name>
+              <description>2-bit attenuation for each pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_AMP_CTRL1</name>
+          <description>no public</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A000A</resetValue>
+          <fields>
+            <field>
+              <name>SAR_AMP_WAIT1</name>
+              <description>no public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_WAIT2</name>
+              <description>no public</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_AMP_CTRL2</name>
+          <description>no public</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000A0000</resetValue>
+          <fields>
+            <field>
+              <name>SAR_SAR1_DAC_XPD_FSM_IDLE</name>
+              <description>no public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_XPD_SAR_AMP_FSM_IDLE</name>
+              <description>no public</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_RST_FB_FSM_IDLE</name>
+              <description>no public</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_SHORT_REF_FSM_IDLE</name>
+              <description>no public</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_SHORT_REF_GND_FSM_IDLE</name>
+              <description>no public</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_XPD_SAR_FSM_IDLE</name>
+              <description>no public</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_RSTB_FSM_IDLE</name>
+              <description>no public</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_WAIT3</name>
+              <description>no public</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_AMP_CTRL3</name>
+          <description>no public</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x007338F3</resetValue>
+          <fields>
+            <field>
+              <name>SAR_SAR1_DAC_XPD_FSM</name>
+              <description>no public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_XPD_SAR_AMP_FSM</name>
+              <description>no public</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_RST_FB_FSM</name>
+              <description>no public</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_SHORT_REF_FSM</name>
+              <description>no public</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_AMP_SHORT_REF_GND_FSM</name>
+              <description>no public</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_XPD_SAR_FSM</name>
+              <description>no public</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_RSTB_FSM</name>
+              <description>no public</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_READER2_CTRL</name>
+          <description>configure saradc2 reader</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40050002</resetValue>
+          <fields>
+            <field>
+              <name>SAR_SAR2_CLK_DIV</name>
+              <description>clock divider</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_WAIT_ARB_CYCLE</name>
+              <description>wait arbit stable after sar_done</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_CLK_GATED</name>
+              <description>******* Description ***********</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_SAMPLE_NUM</name>
+              <description>******* Description ***********</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_DATA_INV</name>
+              <description>Invert SAR ADC2 data</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_INT_EN</name>
+              <description>enable saradc2 to send out interrupt</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_READER2_STATUS</name>
+          <description>get saradc1 reader controller status</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_SAR2_READER_STATUS</name>
+              <description>get saradc1 reader controller status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS2_CTRL1</name>
+          <description>configure saradc2 controller</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07020200</resetValue>
+          <fields>
+            <field>
+              <name>SAR_SAR2_CNTL_STATE</name>
+              <description>saradc2_cntl_fsm</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_PWDET_CAL_EN</name>
+              <description>rtc control pwdet enable</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_PKDET_CAL_EN</name>
+              <description>rtc control pkdet enable</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_EN_TEST</name>
+              <description>SAR2_EN_TEST</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_RSTB_FORCE</name>
+              <description>no public</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_STANDBY_WAIT</name>
+              <description>no public</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_RSTB_WAIT</name>
+              <description>no public</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_XPD_WAIT</name>
+              <description>no public</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS2_CTRL2</name>
+          <description>configure saradc2 controller</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_MEAS2_DATA_SAR</name>
+              <description>SAR ADC2 data</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_MEAS2_DONE_SAR</name>
+              <description>SAR ADC2 conversion done indication</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_MEAS2_START_SAR</name>
+              <description>SAR ADC2 controller (in RTC) starts conversion</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_MEAS2_START_FORCE</name>
+              <description>1: SAR ADC2 controller (in RTC) is started by SW</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_EN_PAD</name>
+              <description>SAR ADC2 pad enable bitmap</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_EN_PAD_FORCE</name>
+              <description>1: SAR ADC2 pad enable bitmap is controlled by SW</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_MEAS2_MUX</name>
+          <description>configure saradc2 controller</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_SAR2_PWDET_CCT</name>
+              <description>SAR2_PWDET_CCT</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SAR2_RTC_FORCE</name>
+              <description>in sleep, force to use rtc to control ADC</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_ATTEN2</name>
+          <description>configure saradc2 controller</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>SAR_SAR2_ATTEN</name>
+              <description>2-bit attenuation for each pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_POWER_XPD_SAR</name>
+          <description>configure power of saradc</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_FORCE_XPD_SAR</name>
+              <description>force power on/off saradc</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SARCLK_EN</name>
+              <description>no public</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR1</name>
+          <description>configure i2c slave address</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_I2C_SLAVE_ADDR1</name>
+              <description>configure i2c slave address1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SLAVE_ADDR0</name>
+              <description>configure i2c slave address0</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SARADC_MEAS_STATUS</name>
+              <description>no public</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR2</name>
+          <description>configure i2c slave address</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_I2C_SLAVE_ADDR3</name>
+              <description>configure i2c slave address3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SLAVE_ADDR2</name>
+              <description>configure i2c slave address2</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR3</name>
+          <description>configure i2c slave address</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_I2C_SLAVE_ADDR5</name>
+              <description>configure i2c slave address5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SLAVE_ADDR4</name>
+              <description>configure i2c slave address4</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SLAVE_ADDR4</name>
+          <description>configure i2c slave address</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_I2C_SLAVE_ADDR7</name>
+              <description>configure i2c slave address7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_SLAVE_ADDR6</name>
+              <description>configure i2c slave address6</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TSENS_CTRL</name>
+          <description>configure tsens controller</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00019000</resetValue>
+          <fields>
+            <field>
+              <name>SAR_TSENS_OUT</name>
+              <description>temperature sensor data out</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_READY</name>
+              <description>indicate temperature sensor out ready</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_INT_EN</name>
+              <description>enable temperature sensor to send out interrupt</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_IN_INV</name>
+              <description>invert temperature sensor data</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_CLK_DIV</name>
+              <description>temperature sensor clock divider</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_POWER_UP</name>
+              <description>temperature sensor power up</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_POWER_UP_FORCE</name>
+              <description>1: dump out &amp; power up controlled by SW 0: by FSM</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_DUMP_OUT</name>
+              <description>temperature sensor dump out only active when reg_tsens_power_up_force = 1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TSENS_CTRL2</name>
+          <description>configure tsens controller</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004002</resetValue>
+          <fields>
+            <field>
+              <name>SAR_TSENS_XPD_WAIT</name>
+              <description>no public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_XPD_FORCE</name>
+              <description>no public</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_CLK_INV</name>
+              <description>no public</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_I2C_CTRL</name>
+          <description>configure rtc i2c controller by sw</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_I2C_CTRL</name>
+              <description>I2C control data  only active when reg_sar_i2c_start_force = 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_START</name>
+              <description>start I2C  only active when reg_sar_i2c_start_force = 1</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_I2C_START_FORCE</name>
+              <description>1: I2C started by SW  0: I2C started by FSM</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_CONF</name>
+          <description>configure touch controller</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFF07FFF</resetValue>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUTEN</name>
+              <description>touch controller output enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_STATUS_CLR</name>
+              <description>clear all touch active status</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_DATA_SEL</name>
+              <description>3: smooth data 2: baseline 1,0: raw_data</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_DENOISE_END</name>
+              <description>touch_denoise_done</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_UNIT_END</name>
+              <description>touch_unit_done</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_APPROACH_PAD2</name>
+              <description>indicate which pad is approach pad2</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_APPROACH_PAD1</name>
+              <description>indicate which pad is approach pad1</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_APPROACH_PAD0</name>
+              <description>indicate which pad is approach pad0</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_DENOISE</name>
+          <description>configure touch controller</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>configure touch controller</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES1</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH1</name>
+              <description>Finger threshold for touch pad 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES2</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH2</name>
+              <description>Finger threshold for touch pad 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES3</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH3</name>
+              <description>Finger threshold for touch pad 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES4</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH4</name>
+              <description>Finger threshold for touch pad 4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES5</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH5</name>
+              <description>Finger threshold for touch pad 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES6</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH6</name>
+              <description>Finger threshold for touch pad 6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES7</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH7</name>
+              <description>Finger threshold for touch pad 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES8</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH8</name>
+              <description>Finger threshold for touch pad 8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES9</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH9</name>
+              <description>Finger threshold for touch pad 9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES10</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH10</name>
+              <description>Finger threshold for touch pad 10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES11</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH11</name>
+              <description>Finger threshold for touch pad 11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES12</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH12</name>
+              <description>Finger threshold for touch pad 12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES13</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH13</name>
+              <description>Finger threshold for touch pad 13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_THRES14</name>
+          <description>configure touch thres of touch pad</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_OUT_TH14</name>
+              <description>Finger threshold for touch pad 14</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_CHN_ST</name>
+          <description>Get touch channel status</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD_ACTIVE</name>
+              <description>touch active status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_CHANNEL_CLR</name>
+              <description>Clear touch channel</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_MEAS_DONE</name>
+              <description>get touch meas done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS0</name>
+          <description>get touch scan status</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_SCAN_CURR</name>
+              <description>current sample channel</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS1</name>
+          <description>touch channel status of touch pad 1</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD1_DATA</name>
+              <description>touch data debounce of touch pad 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD1_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 1</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS2</name>
+          <description>touch channel status of touch pad 2</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD2_DATA</name>
+              <description>touch data debounce of touch pad 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD2_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS3</name>
+          <description>touch channel status of touch pad 3</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD3_DATA</name>
+              <description>touch data debounce of touch pad 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD3_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 3</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS4</name>
+          <description>touch channel status of touch pad 4</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD4_DATA</name>
+              <description>touch data debounce of touch pad 4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD4_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 4</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS5</name>
+          <description>touch channel status of touch pad 5</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD5_DATA</name>
+              <description>touch data debounce of touch pad 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD5_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 5</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS6</name>
+          <description>touch channel status of touch pad 6</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD6_DATA</name>
+              <description>touch data debounce of touch pad 6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD6_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 6</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS7</name>
+          <description>touch channel status of touch pad 7</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD7_DATA</name>
+              <description>touch data debounce of touch pad 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD7_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 7</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS8</name>
+          <description>touch channel status of touch pad 8</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD8_DATA</name>
+              <description>touch data debounce of touch pad 8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD8_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 8</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS9</name>
+          <description>touch channel status of touch pad 9</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD9_DATA</name>
+              <description>touch data debounce of touch pad 9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD9_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 9</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS10</name>
+          <description>touch channel status of touch pad 10</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD10_DATA</name>
+              <description>touch data debounce of touch pad 10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD10_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 10</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS11</name>
+          <description>touch channel status of touch pad 11</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD11_DATA</name>
+              <description>touch data debounce of touch pad 11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD11_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 11</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS12</name>
+          <description>touch channel status of touch pad 12</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD12_DATA</name>
+              <description>touch data debounce of touch pad 12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD12_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 12</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS13</name>
+          <description>touch channel status of touch pad 13</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD13_DATA</name>
+              <description>touch data debounce of touch pad 13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD13_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 13</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS14</name>
+          <description>touch channel status of touch pad 14</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_PAD14_DATA</name>
+              <description>touch data debounce of touch pad 14</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_PAD14_DEBOUNCE</name>
+              <description>touch current debounce of touch pad 14</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS15</name>
+          <description>touch channel status of sleep pad</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_SLP_DATA</name>
+              <description>touch data debounce of sleep pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_SLP_DEBOUNCE</name>
+              <description>touch current debounce of sleep pad</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_TOUCH_STATUS16</name>
+          <description>touch channel status of approach mode</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_TOUCH_APPROACH_PAD2_CNT</name>
+              <description>touch current approach count of approach pad2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_APPROACH_PAD1_CNT</name>
+              <description>touch current approach count of approach pad1</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_APPROACH_PAD0_CNT</name>
+              <description>touch current approach count of approach pad0</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_TOUCH_SLP_APPROACH_CNT</name>
+              <description>touch current approach count of slp pad</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_STATE</name>
+          <description>get cocpu status</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_COCPU_DBG_TRIGGER</name>
+              <description>trigger cocpu debug registers</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_CLK_EN_ST</name>
+              <description>check cocpu whether clk on</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_RESET_N</name>
+              <description>check cocpu whether in reset state</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_EOI</name>
+              <description>check cocpu whether in interrupt state</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TRAP</name>
+              <description>check cocpu whether in trap state</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_EBREAK</name>
+              <description>check cocpu whether in ebreak</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_RAW</name>
+          <description>the interrupt raw of ulp</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_COCPU_TOUCH_DONE_INT_RAW</name>
+              <description>int from touch done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_INACTIVE_INT_RAW</name>
+              <description>int from touch inactive</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_ACTIVE_INT_RAW</name>
+              <description>int from touch active</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC1_INT_RAW</name>
+              <description>int from saradc1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC2_INT_RAW</name>
+              <description>int from saradc2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TSENS_INT_RAW</name>
+              <description>int from tsens</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_START_INT_RAW</name>
+              <description>int from start</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SW_INT_RAW</name>
+              <description>int from software</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SWD_INT_RAW</name>
+              <description>int from super watch dog</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_TIMEOUT_INT_RAW</name>
+              <description>int from timeout done</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW</name>
+              <description>int from approach loop done</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW</name>
+              <description>int from touch scan done</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_ENA</name>
+          <description>the interrupt enable of ulp</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_COCPU_TOUCH_DONE_INT_ENA</name>
+              <description>int enable of touch done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_INACTIVE_INT_ENA</name>
+              <description>int enable of from touch inactive</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_ACTIVE_INT_ENA</name>
+              <description>int enable of touch active</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC1_INT_ENA</name>
+              <description>int enable of from saradc1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC2_INT_ENA</name>
+              <description>int enable of from saradc2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TSENS_INT_ENA</name>
+              <description>int enable of tsens</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_START_INT_ENA</name>
+              <description>int enable of start</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SW_INT_ENA</name>
+              <description>int enable of  software</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SWD_INT_ENA</name>
+              <description>int enable of super watch dog</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_TIMEOUT_INT_ENA</name>
+              <description>int enable of timeout done</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA</name>
+              <description>int enable of approach loop done</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA</name>
+              <description>int enable of touch scan done</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_ST</name>
+          <description>the interrupt state of ulp</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_COCPU_TOUCH_DONE_INT_ST</name>
+              <description>int state of touch done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_INACTIVE_INT_ST</name>
+              <description>int state of from touch inactive</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_ACTIVE_INT_ST</name>
+              <description>int state of touch active</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC1_INT_ST</name>
+              <description>int state of from saradc1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC2_INT_ST</name>
+              <description>int state of from saradc2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TSENS_INT_ST</name>
+              <description>int state of tsens</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_START_INT_ST</name>
+              <description>int state of start</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SW_INT_ST</name>
+              <description>int state of  software</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SWD_INT_ST</name>
+              <description>int state of super watch dog</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_TIMEOUT_INT_ST</name>
+              <description>int state of timeout done</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST</name>
+              <description>int state of approach loop done</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_SCAN_DONE_INT_ST</name>
+              <description>int state of touch scan done</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_CLR</name>
+          <description>the interrupt clear of ulp</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_COCPU_TOUCH_DONE_INT_CLR</name>
+              <description>int clear of touch done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_INACTIVE_INT_CLR</name>
+              <description>int clear of from touch inactive</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_ACTIVE_INT_CLR</name>
+              <description>int clear of touch active</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC1_INT_CLR</name>
+              <description>int clear of from saradc1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC2_INT_CLR</name>
+              <description>int clear of from saradc2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TSENS_INT_CLR</name>
+              <description>int clear of tsens</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_START_INT_CLR</name>
+              <description>int clear of start</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SW_INT_CLR</name>
+              <description>int clear of  software</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SWD_INT_CLR</name>
+              <description>int clear of super watch dog</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_TIMEOUT_INT_CLR</name>
+              <description>int clear of timeout done</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR</name>
+              <description>int clear of approach loop done</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR</name>
+              <description>int clear of touch scan done</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_DEBUG</name>
+          <description>Ulp-riscv debug signal</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_COCPU_PC</name>
+              <description>cocpu Program counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_MEM_VLD</name>
+              <description>cocpu mem valid output</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_MEM_RDY</name>
+              <description>cocpu mem ready input</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_MEM_WEN</name>
+              <description>cocpu mem write enable output</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_MEM_ADDR</name>
+              <description>cocpu mem address output</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_HALL_CTRL</name>
+          <description>no public</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xA0000000</resetValue>
+          <fields>
+            <field>
+              <name>SAR_XPD_HALL</name>
+              <description>Power on hall sensor and connect to VP and VN</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_XPD_HALL_FORCE</name>
+              <description>1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_HALL_PHASE</name>
+              <description>Reverse phase of hall sensor</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_HALL_PHASE_FORCE</name>
+              <description>1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled by FSM in ULP-coprocessor</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_NOUSE</name>
+          <description>no public</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_NOUSE</name>
+              <description>no public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PERI_CLK_GATE_CONF</name>
+          <description>the peri clock gate of rtc  peri</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_RTC_I2C_CLK_EN</name>
+              <description>enable rtc i2c clock</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_CLK_EN</name>
+              <description>enable tsens clock</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SARADC_CLK_EN</name>
+              <description>enbale saradc clock</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_IOMUX_CLK_EN</name>
+              <description>enable io_mux clock</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_PERI_RESET_CONF</name>
+          <description>the peri reset of rtc  peri</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_COCPU_RESET</name>
+              <description>enable ulp-riscv reset</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_RTC_I2C_RESET</name>
+              <description>Reserved.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_TSENS_RESET</name>
+              <description>enbale saradc reset</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAR_SARADC_RESET</name>
+              <description>enable io_mux reset</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_ENA_W1TS</name>
+          <description>the interrupt enable of ulp</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS</name>
+              <description>int enable of touch done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS</name>
+              <description>int enable of from touch inactive</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS</name>
+              <description>int enable of touch active</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC1_INT_ENA_W1TS</name>
+              <description>int enable of from saradc1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC2_INT_ENA_W1TS</name>
+              <description>int enable of from saradc2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TSENS_INT_ENA_W1TS</name>
+              <description>int enable of tsens</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_START_INT_ENA_W1TS</name>
+              <description>int enable of start</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SW_INT_ENA_W1TS</name>
+              <description>int enable of  software</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SWD_INT_ENA_W1TS</name>
+              <description>int enable of super watch dog</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS</name>
+              <description>int enable of timeout done</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS</name>
+              <description>int enable of approach loop done</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS</name>
+              <description>int enable of touch scan done</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_COCPU_INT_ENA_W1TC</name>
+          <description>the interrupt enable clear of ulp</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC</name>
+              <description>Clear int enable of touch done</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC</name>
+              <description>Clear int enable of from touch inactive</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC</name>
+              <description>Clear int enable of touch active</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC1_INT_ENA_W1TC</name>
+              <description>Clear int enable of from saradc1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SARADC2_INT_ENA_W1TC</name>
+              <description>Clear int enable of from saradc2</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TSENS_INT_ENA_W1TC</name>
+              <description>Clear int enable of tsens</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_START_INT_ENA_W1TC</name>
+              <description>Clear int enable of start</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SW_INT_ENA_W1TC</name>
+              <description>Clear int enable of  software</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_SWD_INT_ENA_W1TC</name>
+              <description>Clear int enable of super watch dog</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC</name>
+              <description>Clear int enable of timeout done</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC</name>
+              <description>Clear int enable of approach loop done</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC</name>
+              <description>Clear int enable of touch scan done</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_DEBUG_CONF</name>
+          <description>rtc peri debug configure</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SAR_DEBUG_BIT_SEL</name>
+              <description>no public</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SAR_SARDATE</name>
+          <description>version</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101180</resetValue>
+          <fields>
+            <field>
+              <name>SAR_DATE</name>
+              <description>version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SENSITIVE</name>
+      <description>Peripheral SENSITIVE</description>
+      <groupName>SENSITIVE</groupName>
+      <baseAddress>0x600C1000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x314</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CACHE_DATAARRAY_CONNECT_0</name>
+          <description>Cache data array configuration register 0.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_DATAARRAY_CONNECT_LOCK</name>
+              <description>Set 1 to lock cache data array registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_DATAARRAY_CONNECT_1</name>
+          <description>Cache data array configuration register 1.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_DATAARRAY_CONNECT_FLATTEN</name>
+              <description>Cache data array connection configuration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_ACCESS_0</name>
+          <description>APB peripheral configuration register 0.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_PERIPHERAL_ACCESS_LOCK</name>
+              <description>Set 1 to lock APB peripheral Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APB_PERIPHERAL_ACCESS_1</name>
+          <description>APB peripheral configuration register 1.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>APB_PERIPHERAL_ACCESS_SPLIT_BURST</name>
+              <description>Set 1 to support split function for AHB access to APB peripherals.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_0</name>
+          <description>Internal SRAM configuration register 0.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_USAGE_LOCK</name>
+              <description>Set 1 to lock internal SRAM Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_1</name>
+          <description>Internal SRAM configuration register 1.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_ICACHE_USAGE</name>
+              <description>Set 1 to someone bit means corresponding internal SRAM level can be accessed by icache.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_DCACHE_USAGE</name>
+              <description>Set 1 to someone bit means corresponding internal SRAM level can be accessed by dcache.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_CPU_USAGE</name>
+              <description>Set 1 to someone bit means corresponding internal SRAM level can be accessed by cpu.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_2</name>
+          <description>Internal SRAM configuration register 2.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_CORE0_TRACE_USAGE</name>
+              <description>Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_CORE1_TRACE_USAGE</name>
+              <description>Set 1 to someone bit means corresponding internal SRAM level can be accessed by core1 trace bus.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_CORE0_TRACE_ALLOC</name>
+              <description>Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace bus.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTERNAL_SRAM_CORE1_TRACE_ALLOC</name>
+              <description>Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace bus.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_3</name>
+          <description>Internal SRAM configuration register 3.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_MAC_DUMP_USAGE</name>
+              <description>Set 1 to someone bit means corresponding internal SRAM level can be accessed by mac dump.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INTERNAL_SRAM_USAGE_4</name>
+          <description>Internal SRAM configuration register 4.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERNAL_SRAM_LOG_USAGE</name>
+              <description>Set 1 to someone bit means corresponding internal SRAM level can be accessed by log bus.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RETENTION_DISABLE</name>
+          <description>Retention configuration register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RETENTION_DISABLE</name>
+              <description>Set 1 to disable retention function and lock disable state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_ACCESS_0</name>
+          <description>Cache tag configuration register 0.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_TAG_ACCESS_LOCK</name>
+              <description>Set 1 to lock cache tag Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_TAG_ACCESS_1</name>
+          <description>Cache tag configuration register 1.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>PRO_I_TAG_RD_ACS</name>
+              <description>Set 1 to enable Icache read access tag memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_I_TAG_WR_ACS</name>
+              <description>Set 1 to enable Icache wrtie access tag memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_D_TAG_RD_ACS</name>
+              <description>Set 1 to enable Dcache read access tag memory.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_D_TAG_WR_ACS</name>
+              <description>Set 1 to enable Dcache wrtie access tag memory.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_ACCESS_0</name>
+          <description>Cache MMU configuration register 0.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_MMU_ACCESS_LOCK</name>
+              <description>Set 1 to lock cache MMU registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_MMU_ACCESS_1</name>
+          <description>Cache MMU configuration register 1.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>PRO_MMU_RD_ACS</name>
+              <description>Set 1 to enable read access MMU memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRO_MMU_WR_ACS</name>
+              <description>Set 1 to enable write access MMU memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_0</name>
+          <description>spi2 dma permission configuration register 0.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock spi2 dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_1</name>
+          <description>spi2 dma permission configuration register 1.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>spi2's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>spi2's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>spi2's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>spi2's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>spi2's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>spi2's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SPI3_PMS_CONSTRAIN_0</name>
+          <description>spi3 dma permission configuration register 0.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock spi3 dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SPI3_PMS_CONSTRAIN_1</name>
+          <description>spi3 dma permission configuration register 1.</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>spi3's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>spi3's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>spi3's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>spi3's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>spi3's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>spi3's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0</name>
+          <description>uhci0 dma permission configuration register 0.</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock uhci0 dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1</name>
+          <description>uhci0 dma permission configuration register 1.</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>uhci0's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>uhci0's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>uhci0's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>uhci0's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>uhci0's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>uhci0's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_0</name>
+          <description>i2s0 dma permission configuration register 0.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock i2s0 dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_1</name>
+          <description>i2s0 dma permission configuration register 1.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>i2s0's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>i2s0's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>i2s0's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>i2s0's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>i2s0's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>i2s0's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_I2S1_PMS_CONSTRAIN_0</name>
+          <description>i2s1 dma permission configuration register 0.</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock i2s1 dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_I2S1_PMS_CONSTRAIN_1</name>
+          <description>i2s1 dma permission configuration register 1.</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>i2s1's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>i2s1's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>i2s1's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>i2s1's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>i2s1's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>i2s1's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_0</name>
+          <description>mac dma permission configuration register 0.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock mac dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_1</name>
+          <description>mac dma permission configuration register 1.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>mac's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>mac's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>mac's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>mac's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>mac's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>mac's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0</name>
+          <description>backup dma permission configuration register 0.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock backup dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1</name>
+          <description>backup dma permission configuration register 1.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>backup's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>backup's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>backup's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>backup's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>backup's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>backup's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_AES_PMS_CONSTRAIN_0</name>
+          <description>aes dma permission configuration register 0.</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock aes dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_AES_PMS_CONSTRAIN_1</name>
+          <description>aes dma permission configuration register 1.</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>aes's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>aes's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>aes's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>aes's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>aes's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>aes's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_0</name>
+          <description>sha dma permission configuration register 0.</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock sha dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_1</name>
+          <description>sha dma permission configuration register 1.</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>sha's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>sha's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>sha's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>sha's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>sha's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>sha's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0</name>
+          <description>adc_dac dma permission configuration register 0.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock adc_dac dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1</name>
+          <description>adc_dac dma permission configuration register 1.</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>adc_dac's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>adc_dac's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>adc_dac's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>adc_dac's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>adc_dac's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>adc_dac's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_RMT_PMS_CONSTRAIN_0</name>
+          <description>rmt dma permission configuration register 0.</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock rmt dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_RMT_PMS_CONSTRAIN_1</name>
+          <description>rmt dma permission configuration register 1.</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>rmt's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>rmt's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>rmt's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>rmt's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>rmt's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>rmt's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0</name>
+          <description>lcd_cam dma permission configuration register 0.</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock lcd_cam dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1</name>
+          <description>lcd_cam dma permission configuration register 1.</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>lcd_cam's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>lcd_cam's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>lcd_cam's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>lcd_cam's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>lcd_cam's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>lcd_cam's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_USB_PMS_CONSTRAIN_0</name>
+          <description>usb dma permission configuration register 0.</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock usb dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_USB_PMS_CONSTRAIN_1</name>
+          <description>usb dma permission configuration register 1.</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>usb's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>usb's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>usb's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>usb's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>usb's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>usb's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_LC_PMS_CONSTRAIN_0</name>
+          <description>lc dma permission configuration register 0.</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock lc dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_LC_PMS_CONSTRAIN_1</name>
+          <description>lc dma permission configuration register 1.</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>lc's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>lc's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>lc's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>lc's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>lc's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>lc's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SDIO_PMS_CONSTRAIN_0</name>
+          <description>sdio dma permission configuration register 0.</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock sdio dma permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_SDIO_PMS_CONSTRAIN_1</name>
+          <description>sdio dma permission configuration register 1.</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0</name>
+              <description>sdio's permission(store,load) in data region0 of SRAM</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1</name>
+              <description>sdio's permission(store,load) in data region1 of SRAM</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2</name>
+              <description>sdio's permission(store,load) in data region2 of SRAM</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3</name>
+              <description>sdio's permission(store,load) in data region3 of SRAM</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0</name>
+              <description>sdio's permission(store,load) in dcache data sram block0</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1</name>
+              <description>sdio's permission(store,load) in dcache data sram block1</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_0</name>
+          <description>dma permission monitor configuration register 0.</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_LOCK</name>
+              <description>Set 1 to lock  dma permission monitor Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_1</name>
+          <description>dma permission monitor configuration register 1.</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>Set 1 to clear dma_pms_monitor_violate interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_EN</name>
+              <description>Set 1 to enable dma pms monitor, if dma access violated permission, will trigger interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_2</name>
+          <description>dma permission monitor configuration register 2.</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>recorded dma's interrupt status when dma access violated permission</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD</name>
+              <description>recorded dma's world status when dma access violated permission</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR</name>
+              <description>recorded dma's address bit[25:4] status when dma access violated permission, real address is 0x3c00_0000+addr*16</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_APBPERI_PMS_MONITOR_3</name>
+          <description>dma permission monitor configuration register 3.</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR</name>
+              <description>recorded dma's write status when dma access violated permission, 1(write), 0(read)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN</name>
+              <description>recorded dma's byte enable status when dma access violated permission</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0</name>
+          <description>sram split line configuration register 0</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock sram split configuration register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1</name>
+          <description>sram split line configuration register 1</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0</name>
+              <description>category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1</name>
+              <description>category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2</name>
+              <description>category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3</name>
+              <description>category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4</name>
+              <description>category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5</name>
+              <description>category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6</name>
+              <description>category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR</name>
+              <description>splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2</name>
+          <description>sram split line configuration register 1</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0</name>
+              <description>category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1</name>
+              <description>category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2</name>
+              <description>category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3</name>
+              <description>category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4</name>
+              <description>category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5</name>
+              <description>category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6</name>
+              <description>category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR</name>
+              <description>splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3</name>
+          <description>sram split line configuration register 1</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0</name>
+              <description>category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1</name>
+              <description>category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2</name>
+              <description>category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3</name>
+              <description>category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4</name>
+              <description>category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5</name>
+              <description>category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6</name>
+              <description>category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR</name>
+              <description>splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4</name>
+          <description>sram split line configuration register 1</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0</name>
+              <description>category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1</name>
+              <description>category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2</name>
+              <description>category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3</name>
+              <description>category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4</name>
+              <description>category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5</name>
+              <description>category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6</name>
+              <description>category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR</name>
+              <description>splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5</name>
+          <description>sram split line configuration register 1</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0</name>
+              <description>category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1</name>
+              <description>category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2</name>
+              <description>category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3</name>
+              <description>category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4</name>
+              <description>category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5</name>
+              <description>category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6</name>
+              <description>category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR</name>
+              <description>splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_PMS_CONSTRAIN_0</name>
+          <description>corex iram0 permission configuration register 0</description>
+          <addressOffset>0xD8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock corex iram0 permission configuration register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_PMS_CONSTRAIN_1</name>
+          <description>corex iram0 permission configuration register 0</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>core0/core1's permission of instruction region0 of SRAM in world1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>core0/core1's permission of instruction region1 of SRAM in world1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>core0/core1's permission of instruction region2 of SRAM in world1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>core0/core1's permission of instruction region3 of SRAM in world1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0</name>
+              <description>core0/core1's permission of icache data sram block0 in world1</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1</name>
+              <description>core0/core1's permission of icache data sram block1 in world1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS</name>
+              <description>core0/core1's permission of rom in world1</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_IRAM0_PMS_CONSTRAIN_2</name>
+          <description>corex iram0 permission configuration register 1</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>core0/core1's permission of instruction region0 of SRAM in world1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>core0/core1's permission of instruction region1 of SRAM in world1</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>core0/core1's permission of instruction region2 of SRAM in world1</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>core0/core1's permission of instruction region3 of SRAM in world1</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0</name>
+              <description>core0/core1's permission of icache data sram block0 in world1</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1</name>
+              <description>core0/core1's permission of icache data sram block1 in world1</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS</name>
+              <description>core0/core1's permission of rom in world1</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_PMS_MONITOR_0</name>
+          <description>core0 iram0 permission monitor configuration register 0</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_LOCK</name>
+              <description>Set 1 to lock core0 iram0 permission monitor register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_PMS_MONITOR_1</name>
+          <description>core0 iram0 permission monitor configuration register 1</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>Set 1 to clear core0 iram0 permission violated interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN</name>
+              <description>Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_IRAM0_PMS_MONITOR_2</name>
+          <description>core0 iram0 permission monitor configuration register 2</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>recorded core0 iram0 pms monitor interrupt status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR</name>
+              <description>recorded core0 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load).</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE</name>
+              <description>recorded core0 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store).</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD</name>
+              <description>recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR</name>
+              <description>recorded core0 iram0 address [25:2] status when core0 iram0 violated permission, the real address is 0x40000000+addr*4</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_IRAM0_PMS_MONITOR_0</name>
+          <description>core1 iram0 permission monitor configuration register 0</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_LOCK</name>
+              <description>Set 1 to lock core1 iram0 permission monitor register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_IRAM0_PMS_MONITOR_1</name>
+          <description>core1 iram0 permission monitor configuration register 1</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>Set 1 to clear core1 iram0 permission violated interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN</name>
+              <description>Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_IRAM0_PMS_MONITOR_2</name>
+          <description>core1 iram0 permission monitor configuration register 2</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>recorded core1 iram0 pms monitor interrupt status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR</name>
+              <description>recorded core1 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load).</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE</name>
+              <description>recorded core1 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store).</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD</name>
+              <description>recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR</name>
+              <description>recorded core1 iram0 address [25:2] status when core1 iram0 violated permission, the real address is 0x40000000+addr*4</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>24</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_DRAM0_PMS_CONSTRAIN_0</name>
+          <description>corex dram0 permission configuration register 0</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock corex dram0 permission configuration register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_X_DRAM0_PMS_CONSTRAIN_1</name>
+          <description>corex dram0 permission configuration register 1</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0FFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0</name>
+              <description>core0/core1's permission of data region0 of SRAM in world0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1</name>
+              <description>core0/core1's permission of data region1 of SRAM in world0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2</name>
+              <description>core0/core1's permission of data region2 of SRAM in world0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3</name>
+              <description>core0/core1's permission of data region3 of SRAM in world0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0</name>
+              <description>core0/core1's permission of dcache data sram block0 in world0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1</name>
+              <description>core0/core1's permission of dcache data sram block1 in world0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0</name>
+              <description>core0/core1's permission of data region0 of SRAM in world1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1</name>
+              <description>core0/core1's permission of data region1 of SRAM in world1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2</name>
+              <description>core0/core1's permission of data region2 of SRAM in world1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3</name>
+              <description>core0/core1's permission of data region3 of SRAM in world1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0</name>
+              <description>core0/core1's permission of dcache data sram block0 in world1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1</name>
+              <description>core0/core1's permission of dcache data sram block1 in world1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS</name>
+              <description>core0/core1's permission(sotre,load) of rom in world0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS</name>
+              <description>core0/core1's permission(sotre,load) of rom in world1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_0</name>
+          <description>core0 dram0 permission monitor configuration register 0</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_LOCK</name>
+              <description>Set 1 to lock core0 dram0 permission monitor configuration register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_1</name>
+          <description>core0 dram0 permission monitor configuration register 1</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>Set 1 to clear core0 dram0 permission monior interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN</name>
+              <description>Set 1 to enable core0 dram0 permission monitor interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_2</name>
+          <description>core0 dram0 permission monitor configuration register 2.</description>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>recorded core0 dram0 permission monitor interrupt status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK</name>
+              <description>recorded core0 dram0 lock status, 1 means s32c1i access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD</name>
+              <description>recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR</name>
+              <description>recorded core0 dram0 address[25:4] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_DRAM0_PMS_MONITOR_3</name>
+          <description>core0 dram0 permission monitor configuration register 3.</description>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR</name>
+              <description>recorded core0 dram0 wr status, 1 means store, 0 means load.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN</name>
+              <description>recorded core0 dram0 byteen status.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_PMS_MONITOR_0</name>
+          <description>core1 dram0 permission monitor configuration register 0</description>
+          <addressOffset>0x114</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_LOCK</name>
+              <description>Set 1 to lock core1 dram0 permission monitor configuration register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_PMS_MONITOR_1</name>
+          <description>core1 dram0 permission monitor configuration register 1</description>
+          <addressOffset>0x118</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>Set 1 to clear core1 dram0 permission monior interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN</name>
+              <description>Set 1 to enable core1 dram0 permission monitor interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_PMS_MONITOR_2</name>
+          <description>core1 dram0 permission monitor configuration register 2.</description>
+          <addressOffset>0x11C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>recorded core1 dram0 permission monitor interrupt status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK</name>
+              <description>recorded core1 dram0 lock status, 1 means s32c1i access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD</name>
+              <description>recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR</name>
+              <description>recorded core1 dram0 address[25:4] status when core1 dram0 violated permission,the real address is 0x3c000000+addr*16</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_DRAM0_PMS_MONITOR_3</name>
+          <description>core1 dram0 permission monitor configuration register 3.</description>
+          <addressOffset>0x120</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR</name>
+              <description>recorded core1 dram0 wr status, 1 means store, 0 means load.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN</name>
+              <description>recorded core1 dram0 byteen status.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_0</name>
+          <description>Core0 access peripherals permission configuration register 0.</description>
+          <addressOffset>0x124</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock core0 access peripherals permission Configuration Register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_1</name>
+          <description>Core0 access peripherals permission configuration register 1.</description>
+          <addressOffset>0x128</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFF33CFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART</name>
+              <description>Core0 access uart permission in world0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1</name>
+              <description>Core0 access g0spi_1 permission in world0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0</name>
+              <description>Core0 access g0spi_0 permission in world0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO</name>
+              <description>Core0 access gpio permission in world0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2</name>
+              <description>Core0 access fe2 permission in world0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE</name>
+              <description>Core0 access fe permission in world0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC</name>
+              <description>Core0 access rtc permission in world0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX</name>
+              <description>Core0 access io_mux permission in world0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF</name>
+              <description>Core0 access hinf permission in world0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC</name>
+              <description>Core0 access misc permission in world0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C</name>
+              <description>Core0 access i2c permission in world0.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0</name>
+              <description>Core0 access i2s0 permission in world0.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1</name>
+              <description>Core0 access uart1 permission in world0.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_2</name>
+          <description>Core0 access peripherals permission configuration register 2.</description>
+          <addressOffset>0x12C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFCFFFF3</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT</name>
+              <description>Core0 access bt permission in world0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0</name>
+              <description>Core0 access i2c_ext0 permission in world0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0</name>
+              <description>Core0 access uhci0 permission in world0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST</name>
+              <description>Core0 access slchost permission in world0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT</name>
+              <description>Core0 access rmt permission in world0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT</name>
+              <description>Core0 access pcnt permission in world0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC</name>
+              <description>Core0 access slc permission in world0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC</name>
+              <description>Core0 access ledc permission in world0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP</name>
+              <description>Core0 access backup permission in world0.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB</name>
+              <description>Core0 access bb permission in world0.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0</name>
+              <description>Core0 access pwm0 permission in world0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP</name>
+              <description>Core0 access timergroup permission in world0.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1</name>
+              <description>Core0 access timergroup1 permission in world0.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER</name>
+              <description>Core0 access systimer permission in world0.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_3</name>
+          <description>Core0 access peripherals permission configuration register 3.</description>
+          <addressOffset>0x130</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3CC3FFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2</name>
+              <description>Core0 access spi_2 permission in world0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3</name>
+              <description>Core0 access spi_3 permission in world0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL</name>
+              <description>Core0 access apb_ctrl permission in world0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1</name>
+              <description>Core0 access i2c_ext1 permission in world0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST</name>
+              <description>Core0 access sdio_host permission in world0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN</name>
+              <description>Core0 access can permission in world0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1</name>
+              <description>Core0 access pwm1 permission in world0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1</name>
+              <description>Core0 access i2s1 permission in world0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2</name>
+              <description>Core0 access uart2 permission in world0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT</name>
+              <description>Core0 access rwbt permission in world0.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC</name>
+              <description>Core0 access wifimac permission in world0.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR</name>
+              <description>Core0 access pwr permission in world0.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_4</name>
+          <description>Core0 access peripherals permission configuration register 4.</description>
+          <addressOffset>0x134</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE</name>
+              <description>Core0 access usb_device permission in world0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP</name>
+              <description>Core0 access usb_wrap permission in world0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI</name>
+              <description>Core0 access crypto_peri permission in world0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA</name>
+              <description>Core0 access crypto_dma permission in world0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC</name>
+              <description>Core0 access apb_adc permission in world0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM</name>
+              <description>Core0 access lcd_cam permission in world0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR</name>
+              <description>Core0 access bt_pwr permission in world0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB</name>
+              <description>Core0 access usb permission in world0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM</name>
+              <description>Core0 access system permission in world0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE</name>
+              <description>Core0 access sensitive permission in world0.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT</name>
+              <description>Core0 access interrupt permission in world0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY</name>
+              <description>Core0 access dma_copy permission in world0.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG</name>
+              <description>Core0 access cache_config permission in world0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD</name>
+              <description>Core0 access ad permission in world0.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO</name>
+              <description>Core0 access dio permission in world0.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER</name>
+              <description>Core0 access world_controller permission in world0.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_5</name>
+          <description>Core0 access peripherals permission configuration register 5.</description>
+          <addressOffset>0x138</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFF33CFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART</name>
+              <description>Core0 access uart permission in world1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1</name>
+              <description>Core0 access g0spi_1 permission in world1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0</name>
+              <description>Core0 access g0spi_0 permission in world1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO</name>
+              <description>Core0 access gpio permission in world1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2</name>
+              <description>Core0 access fe2 permission in world1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE</name>
+              <description>Core0 access fe permission in world1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC</name>
+              <description>Core0 access rtc permission in world1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX</name>
+              <description>Core0 access io_mux permission in world1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF</name>
+              <description>Core0 access hinf permission in world1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC</name>
+              <description>Core0 access misc permission in world1.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C</name>
+              <description>Core0 access i2c permission in world1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0</name>
+              <description>Core0 access i2s0 permission in world1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1</name>
+              <description>Core0 access uart1 permission in world1.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_6</name>
+          <description>Core0 access peripherals permission configuration register 6.</description>
+          <addressOffset>0x13C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFCFFFF3</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT</name>
+              <description>Core0 access bt permission in world1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0</name>
+              <description>Core0 access i2c_ext0 permission in world1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0</name>
+              <description>Core0 access uhci0 permission in world1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST</name>
+              <description>Core0 access slchost permission in world1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT</name>
+              <description>Core0 access rmt permission in world1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT</name>
+              <description>Core0 access pcnt permission in world1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC</name>
+              <description>Core0 access slc permission in world1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC</name>
+              <description>Core0 access ledc permission in world1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP</name>
+              <description>Core0 access backup permission in world1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB</name>
+              <description>Core0 access bb permission in world1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0</name>
+              <description>Core0 access pwm0 permission in world1.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP</name>
+              <description>Core0 access timergroup permission in world1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1</name>
+              <description>Core0 access timergroup1 permission in world1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER</name>
+              <description>Core0 access systimer permission in world1.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_7</name>
+          <description>Core0 access peripherals permission configuration register 7.</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3CC3FFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2</name>
+              <description>Core0 access spi_2 permission in world1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3</name>
+              <description>Core0 access spi_3 permission in world1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL</name>
+              <description>Core0 access apb_ctrl permission in world1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1</name>
+              <description>Core0 access i2c_ext1 permission in world1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST</name>
+              <description>Core0 access sdio_host permission in world1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN</name>
+              <description>Core0 access can permission in world1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1</name>
+              <description>Core0 access pwm1 permission in world1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1</name>
+              <description>Core0 access i2s1 permission in world1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2</name>
+              <description>Core0 access uart2 permission in world1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT</name>
+              <description>Core0 access rwbt permission in world1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC</name>
+              <description>Core0 access wifimac permission in world1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR</name>
+              <description>Core0 access pwr permission in world1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_8</name>
+          <description>Core0 access peripherals permission configuration register 8.</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE</name>
+              <description>Core0 access usb_device permission in world1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP</name>
+              <description>Core0 access usb_wrap permission in world1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI</name>
+              <description>Core0 access crypto_peri permission in world1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA</name>
+              <description>Core0 access crypto_dma permission in world1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC</name>
+              <description>Core0 access apb_adc permission in world1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM</name>
+              <description>Core0 access lcd_cam permission in world1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR</name>
+              <description>Core0 access bt_pwr permission in world1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB</name>
+              <description>Core0 access usb permission in world1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM</name>
+              <description>Core0 access system permission in world1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE</name>
+              <description>Core0 access sensitive permission in world1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT</name>
+              <description>Core0 access interrupt permission in world1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY</name>
+              <description>Core0 access dma_copy permission in world1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG</name>
+              <description>Core0 access cache_config permission in world1.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD</name>
+              <description>Core0 access ad permission in world1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO</name>
+              <description>Core0 access dio permission in world1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER</name>
+              <description>Core0 access world_controller permission in world1.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_9</name>
+          <description>Core0 access peripherals permission configuration register 9.</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0</name>
+              <description>RTCFast memory split address in world 0 for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1</name>
+              <description>RTCFast memory split address in world 1 for core0.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_10</name>
+          <description>Core0 access peripherals permission configuration register 10.</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L</name>
+              <description>RTCFast memory low region permission in world 0 for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H</name>
+              <description>RTCFast memory high region permission in world 0 for core0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L</name>
+              <description>RTCFast memory low region permission in world 1 for core0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H</name>
+              <description>RTCFast memory high region permission in world 1 for core0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_11</name>
+          <description>Core0 access peripherals permission configuration register 11.</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0</name>
+              <description>RTCSlow_0 memory split address in world 0 for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1</name>
+              <description>RTCSlow_0 memory split address in world 1 for core0.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_12</name>
+          <description>Core0 access peripherals permission configuration register 12.</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L</name>
+              <description>RTCSlow_0 memory low region permission in world 0 for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H</name>
+              <description>RTCSlow_0 memory high region permission in world 0 for core0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L</name>
+              <description>RTCSlow_0 memory low region permission in world 1 for core0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H</name>
+              <description>RTCSlow_0 memory high region permission in world 1 for core0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_13</name>
+          <description>Core0 access peripherals permission configuration register 13.</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0</name>
+              <description>RTCSlow_1 memory split address in world 0 for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1</name>
+              <description>RTCSlow_1 memory split address in world 1 for core0.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_CONSTRAIN_14</name>
+          <description>Core0 access peripherals permission configuration register 14.</description>
+          <addressOffset>0x15C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L</name>
+              <description>RTCSlow_1 memory low region permission in world 0 for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H</name>
+              <description>RTCSlow_1 memory high region permission in world 0 for core0.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L</name>
+              <description>RTCSlow_1 memory low region permission in world 1 for core0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H</name>
+              <description>RTCSlow_1 memory high region permission in world 1 for core0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_0</name>
+          <description>Core0 region permission register 0.</description>
+          <addressOffset>0x160</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock core0 region permission registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_1</name>
+          <description>Core0 region permission register 1.</description>
+          <addressOffset>0x164</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0</name>
+              <description>Region 0 permission in world 0 for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1</name>
+              <description>Region 1 permission in world 0 for core0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2</name>
+              <description>Region 2 permission in world 0 for core0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3</name>
+              <description>Region 3 permission in world 0 for core0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4</name>
+              <description>Region 4 permission in world 0 for core0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5</name>
+              <description>Region 5 permission in world 0 for core0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6</name>
+              <description>Region 6 permission in world 0 for core0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7</name>
+              <description>Region 7 permission in world 0 for core0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8</name>
+              <description>Region 8 permission in world 0 for core0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9</name>
+              <description>Region 9 permission in world 0 for core0.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10</name>
+              <description>Region 10 permission in world 0 for core0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_2</name>
+          <description>Core0 region permission register 2.</description>
+          <addressOffset>0x168</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0</name>
+              <description>Region 0 permission in world 1 for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1</name>
+              <description>Region 1 permission in world 1 for core0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2</name>
+              <description>Region 2 permission in world 1 for core0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3</name>
+              <description>Region 3 permission in world 1 for core0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4</name>
+              <description>Region 4 permission in world 1 for core0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5</name>
+              <description>Region 5 permission in world 1 for core0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6</name>
+              <description>Region 6 permission in world 1 for core0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7</name>
+              <description>Region 7 permission in world 1 for core0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8</name>
+              <description>Region 8 permission in world 1 for core0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9</name>
+              <description>Region 9 permission in world 1 for core0.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10</name>
+              <description>Region 10 permission in world 1 for core0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_3</name>
+          <description>Core0 region permission register 3.</description>
+          <addressOffset>0x16C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_0</name>
+              <description>Region 0 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_4</name>
+          <description>Core0 region permission register 4.</description>
+          <addressOffset>0x170</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_1</name>
+              <description>Region 0 end address and Region 1 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_5</name>
+          <description>Core0 region permission register 5.</description>
+          <addressOffset>0x174</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_2</name>
+              <description>Region 1 end address and Region 2 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_6</name>
+          <description>Core0 region permission register 6.</description>
+          <addressOffset>0x178</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_3</name>
+              <description>Region 2 end address and Region 3 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_7</name>
+          <description>Core0 region permission register 7.</description>
+          <addressOffset>0x17C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_4</name>
+              <description>Region 3 end address and Region 4 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_8</name>
+          <description>Core0 region permission register 8.</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_5</name>
+              <description>Region 4 end address and Region 5 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_9</name>
+          <description>Core0 region permission register 9.</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_6</name>
+              <description>Region 5 end address and Region 6 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_10</name>
+          <description>Core0 region permission register 10.</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_7</name>
+              <description>Region 6 end address and Region 7 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_11</name>
+          <description>Core0 region permission register 11.</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_8</name>
+              <description>Region 7 end address and Region 8 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_12</name>
+          <description>Core0 region permission register 12.</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_9</name>
+              <description>Region 8 end address and Region 9 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_13</name>
+          <description>Core0 region permission register 13.</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_10</name>
+              <description>Region 9 end address and Region 10 start address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_REGION_PMS_CONSTRAIN_14</name>
+          <description>Core0 region permission register 14.</description>
+          <addressOffset>0x198</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_REGION_PMS_CONSTRAIN_ADDR_11</name>
+              <description>Region 10 end address for core0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_0</name>
+          <description>Core0 permission report register 0.</description>
+          <addressOffset>0x19C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_LOCK</name>
+              <description>Set 1 to lock core0 permission report registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_1</name>
+          <description>Core0 permission report register 1.</description>
+          <addressOffset>0x1A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>Set 1 to clear interrupt that core0 initiate illegal PIF bus access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_EN</name>
+              <description>Set 1 to enable interrupt that core0 initiate illegal PIF bus access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_2</name>
+          <description>Core0 permission report register 2.</description>
+          <addressOffset>0x1A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>Record core0 illegal access interrupt state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0</name>
+              <description>Record hport information when core0 initiate illegal access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE</name>
+              <description>Record access type when core0 initate illegal access.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE</name>
+              <description>Record access direction when core0 initiate illegal access.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD</name>
+              <description>Record world information when core0 initiate illegal access.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_3</name>
+          <description>Core0 permission report register 3.</description>
+          <addressOffset>0x1A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR</name>
+              <description>Record address information when core0 initiate illegal access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_4</name>
+          <description>Core0 permission report register 4.</description>
+          <addressOffset>0x1AC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR</name>
+              <description>Set 1 to clear interrupt that core0 initiate unsupported access type.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN</name>
+              <description>Set 1 to enable interrupt that core0 initiate unsupported access type.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_5</name>
+          <description>Core0 permission report register 5.</description>
+          <addressOffset>0x1B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR</name>
+              <description>Record core0 unsupported access type interrupt state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE</name>
+              <description>Record access type when core0 initiate unsupported access type.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD</name>
+              <description>Record world information when core0 initiate unsupported access type.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_PIF_PMS_MONITOR_6</name>
+          <description>Core0 permission report register 6.</description>
+          <addressOffset>0x1B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR</name>
+              <description>Record address information when core0 initiate unsupported access type.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_VECBASE_OVERRIDE_LOCK</name>
+          <description>core0 vecbase override configuration register 0</description>
+          <addressOffset>0x1B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_VECBASE_OVERRIDE_LOCK</name>
+              <description>Set 1 to lock core0 vecbase configuration register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_VECBASE_OVERRIDE_0</name>
+          <description>core0 vecbase override configuration register 0</description>
+          <addressOffset>0x1BC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_VECBASE_WORLD_MASK</name>
+              <description>Set 1 to mask world, then only world0_value will work.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_VECBASE_OVERRIDE_1</name>
+          <description>core0 vecbase override configuration register 1</description>
+          <addressOffset>0x1C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE</name>
+              <description>world0 vecbase_override register, when core0 in world0 use this register to override vecbase register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_VECBASE_OVERRIDE_SEL</name>
+              <description>Set 0x3 to sel vecbase_override to override vecbase register.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_VECBASE_OVERRIDE_2</name>
+          <description>core0 vecbase override configuration register 1</description>
+          <addressOffset>0x1C4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE</name>
+              <description>world1 vecbase_override register, when core0 in world1 use this register to override vecbase register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0</name>
+          <description>core0 toomanyexception override configuration register 0.</description>
+          <addressOffset>0x1C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK</name>
+              <description>Set 1 to lock core0 toomanyexception override configuration register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1</name>
+          <description>core0 toomanyexception override configuration register 1.</description>
+          <addressOffset>0x1CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE</name>
+              <description>Set 1 to mask toomanyexception.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_0</name>
+          <description>Core1 access peripherals permission configuration register 0.</description>
+          <addressOffset>0x1D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock core1 pif permission configuration register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_1</name>
+          <description>Core1 access peripherals permission configuration register 1.</description>
+          <addressOffset>0x1D4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFF33CFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART</name>
+              <description>Core1 access uart permission in world0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1</name>
+              <description>Core1 access g0spi_1 permission in world0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0</name>
+              <description>Core1 access g0spi_0 permission in world0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO</name>
+              <description>Core1 access gpio permission in world0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2</name>
+              <description>Core1 access fe2 permission in world0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE</name>
+              <description>Core1 access fe permission in world0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC</name>
+              <description>Core1 access rtc permission in world0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX</name>
+              <description>Core1 access io_mux permission in world0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF</name>
+              <description>Core1 access hinf permission in world0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC</name>
+              <description>Core1 access misc permission in world0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C</name>
+              <description>Core1 access i2c permission in world0.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0</name>
+              <description>Core1 access i2s0 permission in world0.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1</name>
+              <description>Core1 access uart1 permission in world0.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_2</name>
+          <description>Core1 access peripherals permission configuration register 2.</description>
+          <addressOffset>0x1D8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFCFFFF3</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT</name>
+              <description>Core1 access bt permission in world0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0</name>
+              <description>Core1 access i2c_ext0 permission in world0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0</name>
+              <description>Core1 access uhci0 permission in world0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST</name>
+              <description>Core1 access slchost permission in world0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT</name>
+              <description>Core1 access rmt permission in world0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT</name>
+              <description>Core1 access pcnt permission in world0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC</name>
+              <description>Core1 access slc permission in world0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC</name>
+              <description>Core1 access ledc permission in world0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP</name>
+              <description>Core1 access backup permission in world0.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB</name>
+              <description>Core1 access bb permission in world0.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0</name>
+              <description>Core1 access pwm0 permission in world0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP</name>
+              <description>Core1 access timergroup permission in world0.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1</name>
+              <description>Core1 access timergroup1 permission in world0.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER</name>
+              <description>Core1 access systimer permission in world0.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_3</name>
+          <description>Core1 access peripherals permission configuration register 3.</description>
+          <addressOffset>0x1DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3CC3FFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2</name>
+              <description>Core1 access spi_2 permission in world0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3</name>
+              <description>Core1 access spi_3 permission in world0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL</name>
+              <description>Core1 access apb_ctrl permission in world0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1</name>
+              <description>Core1 access i2c_ext1 permission in world0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST</name>
+              <description>Core1 access sdio_host permission in world0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN</name>
+              <description>Core1 access can permission in world0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1</name>
+              <description>Core1 access pwm1 permission in world0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1</name>
+              <description>Core1 access i2s1 permission in world0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2</name>
+              <description>Core1 access uart2 permission in world0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT</name>
+              <description>Core1 access rwbt permission in world0.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC</name>
+              <description>Core1 access wifimac permission in world0.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR</name>
+              <description>Core1 access pwr permission in world0.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_4</name>
+          <description>Core1 access peripherals permission configuration register 4.</description>
+          <addressOffset>0x1E0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE</name>
+              <description>Core1 access usb_device permission in world0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP</name>
+              <description>Core1 access usb_wrap permission in world0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI</name>
+              <description>Core1 access crypto_peri permission in world0.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA</name>
+              <description>Core1 access crypto_dma permission in world0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC</name>
+              <description>Core1 access apb_adc permission in world0.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM</name>
+              <description>Core1 access lcd_cam permission in world0.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR</name>
+              <description>Core1 access bt_pwr permission in world0.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB</name>
+              <description>Core1 access usb permission in world0.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM</name>
+              <description>Core1 access system permission in world0.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE</name>
+              <description>Core1 access sensitive permission in world0.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT</name>
+              <description>Core1 access interrupt permission in world0.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY</name>
+              <description>Core1 access dma_copy permission in world0.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG</name>
+              <description>Core1 access cache_config permission in world0.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD</name>
+              <description>Core1 access ad permission in world0.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO</name>
+              <description>Core1 access dio permission in world0.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER</name>
+              <description>Core1 access world_controller permission in world0.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_5</name>
+          <description>Core1 access peripherals permission configuration register 5.</description>
+          <addressOffset>0x1E4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFF33CFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART</name>
+              <description>Core1 access uart permission in world1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1</name>
+              <description>Core1 access g0spi_1 permission in world1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0</name>
+              <description>Core1 access g0spi_0 permission in world1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO</name>
+              <description>Core1 access gpio permission in world1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2</name>
+              <description>Core1 access fe2 permission in world1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE</name>
+              <description>Core1 access fe permission in world1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC</name>
+              <description>Core1 access rtc permission in world1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX</name>
+              <description>Core1 access io_mux permission in world1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF</name>
+              <description>Core1 access hinf permission in world1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC</name>
+              <description>Core1 access misc permission in world1.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C</name>
+              <description>Core1 access i2c permission in world1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0</name>
+              <description>Core1 access i2s0 permission in world1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1</name>
+              <description>Core1 access uart1 permission in world1.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_6</name>
+          <description>Core1 access peripherals permission configuration register 6.</description>
+          <addressOffset>0x1E8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFCFFFF3</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT</name>
+              <description>Core1 access bt permission in world1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0</name>
+              <description>Core1 access i2c_ext0 permission in world1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0</name>
+              <description>Core1 access uhci0 permission in world1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST</name>
+              <description>Core1 access slchost permission in world1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT</name>
+              <description>Core1 access rmt permission in world1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT</name>
+              <description>Core1 access pcnt permission in world1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC</name>
+              <description>Core1 access slc permission in world1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC</name>
+              <description>Core1 access ledc permission in world1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP</name>
+              <description>Core1 access backup permission in world1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB</name>
+              <description>Core1 access bb permission in world1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0</name>
+              <description>Core1 access pwm0 permission in world1.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP</name>
+              <description>Core1 access timergroup permission in world1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1</name>
+              <description>Core1 access timergroup1 permission in world1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER</name>
+              <description>Core1 access systimer permission in world1.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_7</name>
+          <description>Core1 access peripherals permission configuration register 7.</description>
+          <addressOffset>0x1EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3CC3FFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2</name>
+              <description>Core1 access spi_2 permission in world1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3</name>
+              <description>Core1 access spi_3 permission in world1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL</name>
+              <description>Core1 access apb_ctrl permission in world1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1</name>
+              <description>Core1 access i2c_ext1 permission in world1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST</name>
+              <description>Core1 access sdio_host permission in world1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN</name>
+              <description>Core1 access can permission in world1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1</name>
+              <description>Core1 access pwm1 permission in world1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1</name>
+              <description>Core1 access i2s1 permission in world1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2</name>
+              <description>Core1 access uart2 permission in world1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT</name>
+              <description>Core1 access rwbt permission in world1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC</name>
+              <description>Core1 access wifimac permission in world1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR</name>
+              <description>Core1 access pwr permission in world1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_8</name>
+          <description>Core1 access peripherals permission configuration register 8.</description>
+          <addressOffset>0x1F0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE</name>
+              <description>Core1 access usb_device permission in world1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP</name>
+              <description>Core1 access usb_wrap permission in world1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI</name>
+              <description>Core1 access crypto_peri permission in world1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA</name>
+              <description>Core1 access crypto_dma permission in world1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC</name>
+              <description>Core1 access apb_adc permission in world1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM</name>
+              <description>Core1 access lcd_cam permission in world1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR</name>
+              <description>Core1 access bt_pwr permission in world1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB</name>
+              <description>Core1 access usb permission in world1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM</name>
+              <description>Core1 access system permission in world1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE</name>
+              <description>Core1 access sensitive permission in world1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT</name>
+              <description>Core1 access interrupt permission in world1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY</name>
+              <description>Core1 access dma_copy permission in world1.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG</name>
+              <description>Core1 access cache_config permission in world1.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD</name>
+              <description>Core1 access ad permission in world1.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO</name>
+              <description>Core1 access dio permission in world1.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER</name>
+              <description>Core1 access world_controller permission in world1.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_9</name>
+          <description>Core1 access peripherals permission configuration register 9.</description>
+          <addressOffset>0x1F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0</name>
+              <description>RTCFast memory split address in world 0 for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1</name>
+              <description>RTCFast memory split address in world 1 for core1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_10</name>
+          <description>core1 access peripherals permission configuration register 10.</description>
+          <addressOffset>0x1F8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L</name>
+              <description>RTCFast memory low region permission in world 0 for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H</name>
+              <description>RTCFast memory high region permission in world 0 for core1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L</name>
+              <description>RTCFast memory low region permission in world 1 for core1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H</name>
+              <description>RTCFast memory high region permission in world 1 for core1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_11</name>
+          <description>core1 access peripherals permission configuration register 11.</description>
+          <addressOffset>0x1FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0</name>
+              <description>RTCSlow_0 memory split address in world 0 for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1</name>
+              <description>RTCSlow_0 memory split address in world 1 for core1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_12</name>
+          <description>core1 access peripherals permission configuration register 12.</description>
+          <addressOffset>0x200</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L</name>
+              <description>RTCSlow_0 memory low region permission in world 0 for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H</name>
+              <description>RTCSlow_0 memory high region permission in world 0 for core1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L</name>
+              <description>RTCSlow_0 memory low region permission in world 1 for core1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H</name>
+              <description>RTCSlow_0 memory high region permission in world 1 for core1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_13</name>
+          <description>core1 access peripherals permission configuration register 13.</description>
+          <addressOffset>0x204</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0</name>
+              <description>RTCSlow_1 memory split address in world 0 for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1</name>
+              <description>RTCSlow_1 memory split address in world 1 for core1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_CONSTRAIN_14</name>
+          <description>core1 access peripherals permission configuration register 14.</description>
+          <addressOffset>0x208</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L</name>
+              <description>RTCSlow_1 memory low region permission in world 0 for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H</name>
+              <description>RTCSlow_1 memory high region permission in world 0 for core1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L</name>
+              <description>RTCSlow_1 memory low region permission in world 1 for core1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H</name>
+              <description>RTCSlow_1 memory high region permission in world 1 for core1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_0</name>
+          <description>core1 region permission register 0.</description>
+          <addressOffset>0x20C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock core1 region permission registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_1</name>
+          <description>core1 region permission register 1.</description>
+          <addressOffset>0x210</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0</name>
+              <description>Region 0 permission in world 0 for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1</name>
+              <description>Region 1 permission in world 0 for core1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2</name>
+              <description>Region 2 permission in world 0 for core1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3</name>
+              <description>Region 3 permission in world 0 for core1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4</name>
+              <description>Region 4 permission in world 0 for core1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5</name>
+              <description>Region 5 permission in world 0 for core1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6</name>
+              <description>Region 6 permission in world 0 for core1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7</name>
+              <description>Region 7 permission in world 0 for core1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8</name>
+              <description>Region 8 permission in world 0 for core1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9</name>
+              <description>Region 9 permission in world 0 for core1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10</name>
+              <description>Region 10 permission in world 0 for core1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_2</name>
+          <description>core1 region permission register 2.</description>
+          <addressOffset>0x214</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0</name>
+              <description>Region 0 permission in world 1 for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1</name>
+              <description>Region 1 permission in world 1 for core1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2</name>
+              <description>Region 2 permission in world 1 for core1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3</name>
+              <description>Region 3 permission in world 1 for core1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4</name>
+              <description>Region 4 permission in world 1 for core1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5</name>
+              <description>Region 5 permission in world 1 for core1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6</name>
+              <description>Region 6 permission in world 1 for core1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7</name>
+              <description>Region 7 permission in world 1 for core1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8</name>
+              <description>Region 8 permission in world 1 for core1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9</name>
+              <description>Region 9 permission in world 1 for core1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10</name>
+              <description>Region 10 permission in world 1 for core1.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_3</name>
+          <description>core1 region permission register 3.</description>
+          <addressOffset>0x218</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_0</name>
+              <description>Region 0 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_4</name>
+          <description>core1 region permission register 4.</description>
+          <addressOffset>0x21C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_1</name>
+              <description>Region 0 end address and Region 1 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_5</name>
+          <description>core1 region permission register 5.</description>
+          <addressOffset>0x220</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_2</name>
+              <description>Region 1 end address and Region 2 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_6</name>
+          <description>core1 region permission register 6.</description>
+          <addressOffset>0x224</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_3</name>
+              <description>Region 2 end address and Region 3 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_7</name>
+          <description>core1 region permission register 7.</description>
+          <addressOffset>0x228</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_4</name>
+              <description>Region 3 end address and Region 4 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_8</name>
+          <description>core1 region permission register 8.</description>
+          <addressOffset>0x22C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_5</name>
+              <description>Region 4 end address and Region 5 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_9</name>
+          <description>core1 region permission register 9.</description>
+          <addressOffset>0x230</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_6</name>
+              <description>Region 5 end address and Region 6 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_10</name>
+          <description>core1 region permission register 10.</description>
+          <addressOffset>0x234</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_7</name>
+              <description>Region 6 end address and Region 7 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_11</name>
+          <description>core1 region permission register 11.</description>
+          <addressOffset>0x238</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_8</name>
+              <description>Region 7 end address and Region 8 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_12</name>
+          <description>core1 region permission register 12.</description>
+          <addressOffset>0x23C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_9</name>
+              <description>Region 8 end address and Region 9 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_13</name>
+          <description>core1 region permission register 13.</description>
+          <addressOffset>0x240</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_10</name>
+              <description>Region 9 end address and Region 10 start address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_REGION_PMS_CONSTRAIN_14</name>
+          <description>core1 region permission register 14.</description>
+          <addressOffset>0x244</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_REGION_PMS_CONSTRAIN_ADDR_11</name>
+              <description>Region 10 end address for core1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_0</name>
+          <description>core1 permission report register 0.</description>
+          <addressOffset>0x248</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_LOCK</name>
+              <description>Set 1 to lock core1 permission report registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_1</name>
+          <description>core1 permission report register 1.</description>
+          <addressOffset>0x24C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>Set 1 to clear interrupt that core1 initiate illegal PIF bus access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_EN</name>
+              <description>Set 1 to enable interrupt that core1 initiate illegal PIF bus access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_2</name>
+          <description>core1 permission report register 2.</description>
+          <addressOffset>0x250</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>Record core1 illegal access interrupt state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0</name>
+              <description>Record hport information when core1 initiate illegal access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE</name>
+              <description>Record access type when core1 initate illegal access.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE</name>
+              <description>Record access direction when core1 initiate illegal access.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD</name>
+              <description>Record world information when core1 initiate illegal access.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_3</name>
+          <description>core1 permission report register 3.</description>
+          <addressOffset>0x254</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR</name>
+              <description>Record address information when core1 initiate illegal access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_4</name>
+          <description>core1 permission report register 4.</description>
+          <addressOffset>0x258</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR</name>
+              <description>Set 1 to clear interrupt that core1 initiate unsupported access type.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN</name>
+              <description>Set 1 to enable interrupt that core1 initiate unsupported access type.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_5</name>
+          <description>core1 permission report register 5.</description>
+          <addressOffset>0x25C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR</name>
+              <description>Record core1 unsupported access type interrupt state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE</name>
+              <description>Record access type when core1 initiate unsupported access type.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD</name>
+              <description>Record world information when core1 initiate unsupported access type.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_PIF_PMS_MONITOR_6</name>
+          <description>core1 permission report register 6.</description>
+          <addressOffset>0x260</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR</name>
+              <description>Record address information when core1 initiate unsupported access type.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_VECBASE_OVERRIDE_LOCK</name>
+          <description>core1 vecbase override configuration register 0</description>
+          <addressOffset>0x264</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_VECBASE_OVERRIDE_LOCK</name>
+              <description>Set 1 to lock core1 vecbase configuration register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_VECBASE_OVERRIDE_0</name>
+          <description>core1 vecbase override configuration register 0</description>
+          <addressOffset>0x268</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_VECBASE_WORLD_MASK</name>
+              <description>Set 1 to mask world, then only world0_value will work.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_VECBASE_OVERRIDE_1</name>
+          <description>core1 vecbase override configuration register 1</description>
+          <addressOffset>0x26C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE</name>
+              <description>world0 vecbase_override register, when core1 in world0 use this register to override vecbase register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_VECBASE_OVERRIDE_SEL</name>
+              <description>Set 0x3 to sel vecbase_override to override vecbase register.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_VECBASE_OVERRIDE_2</name>
+          <description>core1 vecbase override configuration register 1</description>
+          <addressOffset>0x270</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE</name>
+              <description>world1 vecbase_override register, when core1 in world1 use this register to override vecbase register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0</name>
+          <description>core1 toomanyexception override configuration register 0.</description>
+          <addressOffset>0x274</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK</name>
+              <description>Set 1 to lock core1 toomanyexception override configuration register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1</name>
+          <description>core1 toomanyexception override configuration register 1.</description>
+          <addressOffset>0x278</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE</name>
+              <description>Set 1 to mask toomanyexception.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_0</name>
+          <description>BackUp access peripherals permission configuration register 0.</description>
+          <addressOffset>0x27C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_LOCK</name>
+              <description>Set 1 to lock BackUp permission configuration registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_1</name>
+          <description>BackUp access peripherals permission configuration register 1.</description>
+          <addressOffset>0x280</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFF33CFFF</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_UART</name>
+              <description>BackUp access uart permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1</name>
+              <description>BackUp access g0spi_1 permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0</name>
+              <description>BackUp access g0spi_0 permission.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_GPIO</name>
+              <description>BackUp access gpio permission.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_FE2</name>
+              <description>BackUp access fe2 permission.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_FE</name>
+              <description>BackUp access fe permission.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_RTC</name>
+              <description>BackUp access rtc permission.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_IO_MUX</name>
+              <description>BackUp access io_mux permission.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_HINF</name>
+              <description>BackUp access hinf permission.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_MISC</name>
+              <description>BackUp access misc permission.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_I2C</name>
+              <description>BackUp access i2c permission.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_I2S0</name>
+              <description>BackUp access i2s0 permission.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_UART1</name>
+              <description>BackUp access uart1 permission.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_2</name>
+          <description>BackUp access peripherals permission configuration register 2.</description>
+          <addressOffset>0x284</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFCFFFF3</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_BT</name>
+              <description>BackUp access bt permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0</name>
+              <description>BackUp access i2c_ext0 permission.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_UHCI0</name>
+              <description>BackUp access uhci0 permission.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SLCHOST</name>
+              <description>BackUp access slchost permission.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_RMT</name>
+              <description>BackUp access rmt permission.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_PCNT</name>
+              <description>BackUp access pcnt permission.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SLC</name>
+              <description>BackUp access slc permission.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_LEDC</name>
+              <description>BackUp access ledc permission.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_BACKUP</name>
+              <description>BackUp access backup permission.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_BB</name>
+              <description>BackUp access bb permission.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_PWM0</name>
+              <description>BackUp access pwm0 permission.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP</name>
+              <description>BackUp access timergroup permission.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1</name>
+              <description>BackUp access timergroup1 permission.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER</name>
+              <description>BackUp access systimer permission.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_3</name>
+          <description>BackUp access peripherals permission configuration register 3.</description>
+          <addressOffset>0x288</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x3CC3FFFF</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SPI_2</name>
+              <description>BackUp access spi_2 permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SPI_3</name>
+              <description>BackUp access spi_3 permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL</name>
+              <description>BackUp access apb_ctrl permission.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1</name>
+              <description>BackUp access i2c_ext1 permission.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST</name>
+              <description>BackUp access sdio_host permission.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_CAN</name>
+              <description>BackUp access can permission.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_PWM1</name>
+              <description>BackUp access pwm1 permission.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_I2S1</name>
+              <description>BackUp access i2s1 permission.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_UART2</name>
+              <description>BackUp access uart2 permission.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_RWBT</name>
+              <description>BackUp access rwbt permission.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC</name>
+              <description>BackUp access wifimac permission.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_PWR</name>
+              <description>BackUp access pwr permission.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_4</name>
+          <description>BackUp access peripherals permission configuration register 4.</description>
+          <addressOffset>0x28C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE</name>
+              <description>BackUp access usb_device permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP</name>
+              <description>BackUp access usb_wrap permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI</name>
+              <description>BackUp access crypto_peri permission.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA</name>
+              <description>BackUp access crypto_dma permission.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_APB_ADC</name>
+              <description>BackUp access apb_adc permission.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM</name>
+              <description>BackUp access lcd_cam permission.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_BT_PWR</name>
+              <description>BackUp access bt_pwr permission.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_USB</name>
+              <description>BackUp access usb permission.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SYSTEM</name>
+              <description>BackUp access system permission.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE</name>
+              <description>BackUp access sensitive permission.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT</name>
+              <description>BackUp access interrupt permission.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY</name>
+              <description>BackUp access dma_copy permission.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG</name>
+              <description>BackUp access cache_config permission.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_AD</name>
+              <description>BackUp access ad permission.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_DIO</name>
+              <description>BackUp access dio permission.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER</name>
+              <description>BackUp access world_controller permission.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_5</name>
+          <description>BackUp access peripherals permission configuration register 5.</description>
+          <addressOffset>0x290</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000007FF</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR</name>
+              <description>BackUp access rtcfast_spltaddr permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_CONSTRAIN_6</name>
+          <description>BackUp access peripherals permission configuration register 6.</description>
+          <addressOffset>0x294</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003F</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L</name>
+              <description>BackUp access rtcfast_l permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H</name>
+              <description>BackUp access rtcfast_h permission.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_MONITOR_0</name>
+          <description>BackUp permission report register 0.</description>
+          <addressOffset>0x298</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_LOCK</name>
+              <description>Set 1 to lock BackUp permission report registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_MONITOR_1</name>
+          <description>BackUp permission report register 1.</description>
+          <addressOffset>0x29C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR</name>
+              <description>Set 1 to clear interrupt that BackUp initiate illegal access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_EN</name>
+              <description>Set 1 to enable interrupt that BackUp initiate illegal access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_MONITOR_2</name>
+          <description>BackUp permission report register 2.</description>
+          <addressOffset>0x2A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR</name>
+              <description>Record BackUp illegal access interrupt state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS</name>
+              <description>Record htrans when BackUp initate illegal access.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE</name>
+              <description>Record access type when BackUp initate illegal access.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE</name>
+              <description>Record access direction when BackUp initiate illegal access.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BACKUP_BUS_PMS_MONITOR_3</name>
+          <description>BackUp permission report register 3.</description>
+          <addressOffset>0x2A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR</name>
+              <description>Record address information when BackUp initiate illegal access.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_BOUNDARY_LOCK</name>
+          <description>EDMA boundary lock register.</description>
+          <addressOffset>0x2A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_BOUNDARY_LOCK</name>
+              <description>Set 1 to lock EDMA boundary registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_BOUNDARY_0</name>
+          <description>EDMA boundary 0 configuration</description>
+          <addressOffset>0x2AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_BOUNDARY_0</name>
+              <description>This field is used to configure the boundary 0 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_BOUNDARY_1</name>
+          <description>EDMA boundary 1 configuration</description>
+          <addressOffset>0x2B0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002000</resetValue>
+          <fields>
+            <field>
+              <name>EDMA_BOUNDARY_1</name>
+              <description>This field is used to configure the boundary 1 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_BOUNDARY_2</name>
+          <description>EDMA boundary 2 configuration</description>
+          <addressOffset>0x2B4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002000</resetValue>
+          <fields>
+            <field>
+              <name>EDMA_BOUNDARY_2</name>
+              <description>This field is used to configure the boundary 2 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_SPI2_LOCK</name>
+          <description>EDMA-SPI2 permission lock register.</description>
+          <addressOffset>0x2B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_SPI2_LOCK</name>
+              <description>Set 1 to lock EDMA-SPI2 permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_SPI2</name>
+          <description>EDMA-SPI2 permission control register.</description>
+          <addressOffset>0x2BC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_SPI3_LOCK</name>
+          <description>EDMA-SPI3 permission lock register.</description>
+          <addressOffset>0x2C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_SPI3_LOCK</name>
+              <description>Set 1 to lock EDMA-SPI3 permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_SPI3</name>
+          <description>EDMA-SPI3 permission control register.</description>
+          <addressOffset>0x2C4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_UHCI0_LOCK</name>
+          <description>EDMA-UHCI0 permission lock register.</description>
+          <addressOffset>0x2C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_UHCI0_LOCK</name>
+              <description>Set 1 to lock EDMA-UHCI0 permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_UHCI0</name>
+          <description>EDMA-UHCI0 permission control register.</description>
+          <addressOffset>0x2CC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_I2S0_LOCK</name>
+          <description>EDMA-I2S0 permission lock register.</description>
+          <addressOffset>0x2D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_I2S0_LOCK</name>
+              <description>Set 1 to lock EDMA-I2S0 permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_I2S0</name>
+          <description>EDMA-I2S0 permission control register.</description>
+          <addressOffset>0x2D4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_I2S1_LOCK</name>
+          <description>EDMA-I2S1 permission lock register.</description>
+          <addressOffset>0x2D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_I2S1_LOCK</name>
+              <description>Set 1 to lock EDMA-I2S1 permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_I2S1</name>
+          <description>EDMA-I2S1 permission control register.</description>
+          <addressOffset>0x2DC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_LCD_CAM_LOCK</name>
+          <description>EDMA-LCD/CAM permission lock register.</description>
+          <addressOffset>0x2E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_LCD_CAM_LOCK</name>
+              <description>Set 1 to lock EDMA-LCD/CAM permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_LCD_CAM</name>
+          <description>EDMA-LCD/CAM permission control register.</description>
+          <addressOffset>0x2E4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_AES_LOCK</name>
+          <description>EDMA-AES permission lock register.</description>
+          <addressOffset>0x2E8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_AES_LOCK</name>
+              <description>Set 1 to lock EDMA-AES permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_AES</name>
+          <description>EDMA-AES permission control register.</description>
+          <addressOffset>0x2EC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of AES accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of AES accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_SHA_LOCK</name>
+          <description>EDMA-SHA permission lock register.</description>
+          <addressOffset>0x2F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_SHA_LOCK</name>
+              <description>Set 1 to lock EDMA-SHA permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_SHA</name>
+          <description>EDMA-SHA permission control register.</description>
+          <addressOffset>0x2F4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of SHA accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of SHA accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_ADC_DAC_LOCK</name>
+          <description>EDMA-ADC/DAC permission lock register.</description>
+          <addressOffset>0x2F8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_ADC_DAC_LOCK</name>
+              <description>Set 1 to lock EDMA-ADC/DAC permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_ADC_DAC</name>
+          <description>EDMA-ADC/DAC permission control register.</description>
+          <addressOffset>0x2FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_RMT_LOCK</name>
+          <description>EDMA-RMT permission lock register.</description>
+          <addressOffset>0x300</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EDMA_PMS_RMT_LOCK</name>
+              <description>Set 1 to lock EDMA-RMT permission control registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_PMS_RMT</name>
+          <description>EDMA-RMT permission control register.</description>
+          <addressOffset>0x304</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000F</resetValue>
+          <fields>
+            <field>
+              <name>ATTR1</name>
+              <description>This field is used to configure the permission of RMT accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ATTR2</name>
+              <description>This field is used to configure the permission of RMT accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE_REG</name>
+          <description>Sensitive module clock gate configuration register.</description>
+          <addressOffset>0x308</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>REG_CLK_EN</name>
+              <description>Set 1 to enable clock gate function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_PMS</name>
+          <description>RTC coprocessor permission register.</description>
+          <addressOffset>0x30C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIS_RTC_CPU</name>
+              <description>Set 1 to disable rtc coprocessor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Sensitive version register.</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101280</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Sensitive Date register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SHA</name>
+      <description>SHA (Secure Hash Algorithm) Accelerator</description>
+      <groupName>SHA</groupName>
+      <baseAddress>0x6003B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SHA</name>
+        <value>78</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Initial configuration register.</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODE</name>
+              <description>sha mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_STRING</name>
+          <description>SHA 512/t configuration register 0.</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_STRING</name>
+              <description>sha t_string(used if and only if mode == sha_256/t)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>T_LENGTH</name>
+          <description>SHA 512/t configuration register 1.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T_LENGTH</name>
+              <description>sha t_length(used if and only if mode == sha_256/t)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_BLOCK_NUM</name>
+          <description>DMA configuration register 0.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_BLOCK_NUM</name>
+              <description>dma-sha block number</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>START</name>
+          <description>Typical SHA configuration register 0.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>START</name>
+              <description>reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONTINUE</name>
+          <description>Typical SHA configuration register 1.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTINUE</name>
+              <description>reserved.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>31</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUSY</name>
+          <description>Busy register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>sha busy state. 1'b0: idle 1'b1: busy</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_START</name>
+          <description>DMA configuration register 1.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_START</name>
+              <description>start dma-sha</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONTINUE</name>
+          <description>DMA configuration register 2.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_CONTINUE</name>
+              <description>continue dma-sha</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLEAR_IRQ</name>
+          <description>Interrupt clear register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLEAR_INTERRUPT</name>
+              <description>clear sha interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IRQ_ENA</name>
+          <description>Interrupt enable register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INTERRUPT_ENA</name>
+              <description>sha interrupt enable register. 1'b0: disable(default) 1'b1: enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Date register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20190402</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>sha date information/ sha version information</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>H_MEM[%s]</name>
+          <description>Sha H memory which contains intermediate hash or finial hash.</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x8</size>
+        </register>
+        <register>
+          <dim>64</dim>
+          <dimIncrement>0x1</dimIncrement>
+          <name>M_MEM[%s]</name>
+          <description>Sha M memory which contains message.</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x8</size>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI0</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI0</groupName>
+      <baseAddress>0x60003000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x98</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI_MEM_REJECT</name>
+        <value>60</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CTRL</name>
+          <description>SPI0 control register.</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x002C2000</resetValue>
+          <fields>
+            <field>
+              <name>FDUMMY_OUT</name>
+              <description>In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_OCT</name>
+              <description>Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_OCT</name>
+              <description>Set this bit to enable 8-bit-mode(8-bm) in DIN phase.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_OCT</name>
+              <description>Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Set this bit to enable 2-bit-mode(2-bm) in CMD phase.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Set this bit to enable 4-bit-mode(4-bm) in CMD phase.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_OCT</name>
+              <description>Set this bit to enable 8-bit-mode(8-bm) in CMD phase.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTRD_MODE</name>
+              <description>This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DIO</name>
+              <description>In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QIO</name>
+              <description>In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL1</name>
+          <description>SPI0 control 1 register.</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>SPI0 control 2 register.</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002C21</resetValue>
+          <fields>
+            <field>
+              <name>CS_SETUP_TIME</name>
+              <description>(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_TIME</name>
+              <description>SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ECC_CS_HOLD_TIME</name>
+              <description>SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ECC_SKIP_PAGE_CORNER</name>
+              <description>1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ECC_16TO18_BYTE_EN</name>
+              <description>Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_DELAY</name>
+              <description>These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC_RESET</name>
+              <description>The FSM will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI_CLK clock division register when SPI0 accesses to flash.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>It must equal to the value of SPI_MEM_CLKCNT_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI0 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CS_HOLD</name>
+              <description>Set this bit to keep SPI_CS low when MSPI is in DONE state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP</name>
+              <description>Set this bit to keep SPI_CS low when MSPI is in PREP state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the DUMMY phase of an SPI transfer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI0 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The SPI_CLK cycle length minus 1 of DUMMY phase.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of ADDR phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI0 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of user defined(USR) command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of CMD phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_STATUS</name>
+          <description>SPI0 read control register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with SPI_MEM_FASTRD_MODE bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_ADDR</name>
+          <description>SPI0 extended address register.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_ADDR</name>
+              <description>The register are the higher 32bits in the 64 bits address mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI0 misc register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FSUB_PIN</name>
+              <description>Flash is connected to SPI SUBPIN bus.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SSUB_PIN</name>
+              <description>Ext_RAM is connected to SPI SUBPIN bus.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>SPI_CS line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_FCTRL</name>
+          <description>SPI0 external RAM bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_REQ_EN</name>
+              <description>Set this bit to enable Cache's access and SPI0's transfer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_USR_CMD_4BYTE</name>
+              <description>Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_FLASH_USR_CMD</name>
+              <description>1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_DUAL</name>
+              <description>When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_DUAL</name>
+              <description>When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_QUAD</name>
+              <description>When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_QUAD</name>
+              <description>When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_SCTRL</name>
+          <description>SPI0 external RAM control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0055C070</resetValue>
+          <fields>
+            <field>
+              <name>CACHE_USR_SCMD_4BYTE</name>
+              <description>Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_SRAM_DIO</name>
+              <description>Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_SRAM_QIO</name>
+              <description>Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_WR_SRAM_DUMMY</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_RD_SRAM_DUMMY</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SRAM_USR_RCMD</name>
+              <description>1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_RDUMMY_CYCLELEN</name>
+              <description>When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_ADDR_BITLEN</name>
+              <description>When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SRAM_USR_WCMD</name>
+              <description>1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_OCT</name>
+              <description>Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRAM_WDUMMY_CYCLELEN</name>
+              <description>When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_CMD</name>
+          <description>SPI0 external RAM mode control register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SCLK_MODE</name>
+              <description>SPI_CLK mode bits  when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SWB_MODE</name>
+              <description>Mode bits when SPI0 accesses to Ext_RAM.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIN_DUAL</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDOUT_DUAL</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SADDR_DUAL</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCMD_DUAL</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIN_QUAD</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDOUT_QUAD</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SADDR_QUAD</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCMD_QUAD</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIN_OCT</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDOUT_OCT</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SADDR_OCT</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCMD_OCT</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDUMMY_OUT</name>
+              <description>When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_DRD_CMD</name>
+          <description>SPI0 external RAM DDR read command control register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_SRAM_USR_RD_CMD_VALUE</name>
+              <description>When SPI0 reads Ext_RAM, it is the command value of CMD phase.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SRAM_USR_RD_CMD_BITLEN</name>
+              <description>When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_DWR_CMD</name>
+          <description>SPI0 external RAM DDR write command control register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_SRAM_USR_WR_CMD_VALUE</name>
+              <description>When SPI0 writes Ext_RAM, it is the command value of CMD phase.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CACHE_SRAM_USR_WR_CMD_BITLEN</name>
+              <description>When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SRAM_CLK</name>
+          <description>SPI_CLK clock division register when SPI0 accesses to Ext_RAM.</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>SCLKCNT_L</name>
+              <description>It must equal to the value of SPI_MEM_SCLKCNT_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLKCNT_H</name>
+              <description>It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLKCNT_N</name>
+              <description>When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_EQU_SYSCLK</name>
+              <description>When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM</name>
+          <description>SPI0 state machine(FSM) status register.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST</name>
+              <description>The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMING_CALI</name>
+          <description>SPI0 timing compensation register when accesses to flash.</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMING_CLK_ENA</name>
+              <description>Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMING_CALI</name>
+              <description>Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTRA_DUMMY_CYCLELEN</name>
+              <description>Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_MODE</name>
+          <description>MSPI input timing delay mode control register when accesses to flash.</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_MODE</name>
+              <description>SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_MODE</name>
+              <description>SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_MODE</name>
+              <description>SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_MODE</name>
+              <description>SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN4_MODE</name>
+              <description>SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN5_MODE</name>
+              <description>SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN6_MODE</name>
+              <description>SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN7_MODE</name>
+              <description>SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DINS_MODE</name>
+              <description>SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_NUM</name>
+          <description>MSPI input timing delay number control register when accesses to flash.</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_NUM</name>
+              <description>SPI_D input delay number.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_NUM</name>
+              <description>SPI_Q input delay number.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_NUM</name>
+              <description>SPI_WP input delay number.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_NUM</name>
+              <description>SPI_HD input delay number.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN4_NUM</name>
+              <description>SPI_IO4 input delay number.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN5_NUM</name>
+              <description>SPI_IO5 input delay number.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN6_NUM</name>
+              <description>SPI_IO6 input delay number.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN7_NUM</name>
+              <description>SPI_IO7 input delay number.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DINS_NUM</name>
+              <description>SPI_DQS input delay number.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOUT_MODE</name>
+          <description>MSPI output timing delay mode control register when accesses to flash.</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DOUT0_MODE</name>
+              <description>SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT1_MODE</name>
+              <description>SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT2_MODE</name>
+              <description>SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT3_MODE</name>
+              <description>SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT4_MODE</name>
+              <description>SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT5_MODE</name>
+              <description>SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT6_MODE</name>
+              <description>SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT7_MODE</name>
+              <description>SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUTS_MODE</name>
+              <description>SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_TIMING_CALI</name>
+          <description>SPI0 Ext_RAM timing compensation register.</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_TIMING_CLK_ENA</name>
+              <description>Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_TIMING_CALI</name>
+              <description>Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_EXTRA_DUMMY_CYCLELEN</name>
+              <description>Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DIN_MODE</name>
+          <description>MSPI input timing delay mode control register when accesses to Ext_RAM.</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_DIN0_MODE</name>
+              <description>SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN1_MODE</name>
+              <description>SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN2_MODE</name>
+              <description>SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN3_MODE</name>
+              <description>SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN4_MODE</name>
+              <description>SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN5_MODE</name>
+              <description>SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN6_MODE</name>
+              <description>SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN7_MODE</name>
+              <description>SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DINS_MODE</name>
+              <description>SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DIN_NUM</name>
+          <description>MSPI input timing delay number control register when accesses to Ext_RAM.</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_DIN0_NUM</name>
+              <description>SPI_D input delay number.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN1_NUM</name>
+              <description>SPI_Q input delay number.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN2_NUM</name>
+              <description>SPI_WP input delay number.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN3_NUM</name>
+              <description>SPI_HD input delay number.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN4_NUM</name>
+              <description>SPI_IO4 input delay number.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN5_NUM</name>
+              <description>SPI_IO5 input delay number.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN6_NUM</name>
+              <description>SPI_IO6 input delay number.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DIN7_NUM</name>
+              <description>SPI_IO7 input delay number.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DINS_NUM</name>
+              <description>SPI_DQS input delay number.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DOUT_MODE</name>
+          <description>MSPI output timing delay mode control register when accesses to Ext_RAM.</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SPI_SMEM_DOUT0_MODE</name>
+              <description>SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT1_MODE</name>
+              <description>SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT2_MODE</name>
+              <description>SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT3_MODE</name>
+              <description>SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT4_MODE</name>
+              <description>SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT5_MODE</name>
+              <description>SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT6_MODE</name>
+              <description>SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUT7_MODE</name>
+              <description>SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DOUTS_MODE</name>
+              <description>SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ECC_CTRL</name>
+          <description>MSPI ECC control register</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>ECC_ERR_INT_NUM</name>
+              <description>Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_ECC_ERR_INT_EN</name>
+              <description>Set this bit to calculate the error times of MSPI ECC read when accesses to flash.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ECC_ERR_ADDR</name>
+          <description>MSPI ECC error address register</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ECC_ERR_ADDR</name>
+              <description>These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte error and data error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ECC_ERR_BIT</name>
+          <description>MSPI ECC error bits register</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ECC_DATA_ERR_BIT</name>
+              <description>It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_CHK_ERR_BIT</name>
+              <description>When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_BYTE_ERR</name>
+              <description>It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_ERR_CNT</name>
+              <description>This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_AC</name>
+          <description>MSPI external RAM ECC and SPI CS timing control register</description>
+          <addressOffset>0xDC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000B084</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_CS_SETUP</name>
+              <description>Set this bit to keep SPI_CS low when MSPI is in PREP state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_HOLD</name>
+              <description>Set this bit to keep SPI_CS low when MSPI is in DONE state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_SETUP_TIME</name>
+              <description>(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_HOLD_TIME</name>
+              <description>SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_CS_HOLD_TIME</name>
+              <description>SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_SKIP_PAGE_CORNER</name>
+              <description>1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_16TO18_BYTE_EN</name>
+              <description>Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_ECC_ERR_INT_EN</name>
+              <description>Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CS_HOLD_DELAY</name>
+              <description>These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DDR</name>
+          <description>SPI0 flash DDR mode control register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003020</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_DDR_EN</name>
+              <description>1: in ddr mode,  0 in sdr mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_VAR_DUMMY</name>
+              <description>Set the bit to enable variable dummy cycle in DDR mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_RDAT_SWP</name>
+              <description>Set the bit to reorder RX data of the word in DDR mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_WDAT_SWP</name>
+              <description>Set the bit to swap TX data of a word in DDR mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_CMD_DIS</name>
+              <description>the bit is used to disable dual edge in CMD phase when ddr mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OUTMINBYTELEN</name>
+              <description>It is the minimum output data length in the panda device.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_TX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_RX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_USR_DDR_DQS_THD</name>
+              <description>The delay number of data strobe which from memory based on SPI_CLK.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_DQS_LOOP</name>
+              <description>1: Use internal signal  as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_DQS_LOOP_MODE</name>
+              <description>When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK  as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is not active.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_EN</name>
+              <description>Set this bit to enable the differential SPI_CLK#.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_MODE</name>
+              <description>Set this bit to enable the SPI HyperBus mode.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DQS_CA_IN</name>
+              <description>Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_DUMMY_2X</name>
+              <description>Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_INV</name>
+              <description>Set this bit to invert SPI_DIFF when accesses to flash. .</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OCTA_RAM_ADDR</name>
+              <description>Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_CA</name>
+              <description>Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SMEM_DDR</name>
+          <description>SPI0 external RAM DDR mode control register</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003020</resetValue>
+          <fields>
+            <field>
+              <name>EN</name>
+              <description>1: in ddr mode,  0 in sdr mode</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_VAR_DUMMY</name>
+              <description>Set the bit to enable variable dummy cycle in spi ddr mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RDAT_SWP</name>
+              <description>Set the bit to reorder rx data of the word in spi ddr mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDAT_SWP</name>
+              <description>Set the bit to reorder tx data of the word in spi ddr mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMD_DIS</name>
+              <description>the bit is used to disable dual edge in CMD phase when ddr mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_OUTMINBYTELEN</name>
+              <description>It is the minimum output data length in the ddr psram.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_TX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_RX_DDR_MSK_EN</name>
+              <description>Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_USR_DDR_DQS_THD</name>
+              <description>The delay number of data strobe which from memory based on SPI_CLK.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DQS_LOOP</name>
+              <description>1: Use internal signal  as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DQS_LOOP_MODE</name>
+              <description>When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK  as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is not active.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CLK_DIFF_EN</name>
+              <description>Set this bit to enable the differential SPI_CLK#.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_HYPERBUS_MODE</name>
+              <description>Set this bit to enable the SPI HyperBus mode.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_DQS_CA_IN</name>
+              <description>Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_HYPERBUS_DUMMY_2X</name>
+              <description>Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_CLK_DIFF_INV</name>
+              <description>Set this bit to invert SPI_DIFF when accesses to external RAM. .</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_OCTA_RAM_ADDR</name>
+              <description>Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SMEM_HYPERBUS_CA</name>
+              <description>Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>SPI0 clk_gate register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_CLK_SEL</name>
+          <description>SPI0 module clock select register</description>
+          <addressOffset>0xEC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_CLK_SEL</name>
+              <description>When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz.  2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz.  2: MSPI_CORE_CLK 160MHz. 3: Not used.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>SPI1 interrupt enable register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOTAL_TRANS_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ECC_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>SPI1 interrupt clear register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOTAL_TRANS_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ECC_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>SPI1 interrupt raw register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOTAL_TRANS_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success.  0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and  APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and  APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and  APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and  APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>SPI1 interrupt status register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TOTAL_TRANS_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_ERR_INT_ST</name>
+              <description>The status bit for SPI_MEM_ECC_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>SPI0 version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101040</resetValue>
+          <fields>
+            <field>
+              <name>SPI_SMEM_SPICLK_FUN_DRV</name>
+              <description>The driver of SPI_CLK PAD  is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_SPICLK_FUN_DRV</name>
+              <description>The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_SPICLK_PAD_DRV_CTL_EN</name>
+              <description>SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD  is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI1</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI1</groupName>
+      <baseAddress>0x60002000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xB4</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI1</name>
+        <value>20</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CMD</name>
+          <description>SPI1 memory command register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FLASH_PE</name>
+              <description>In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_HPM</name>
+              <description>Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RES</name>
+              <description>This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_DP</name>
+              <description>Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_CE</name>
+              <description>Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_BE</name>
+              <description>Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_SE</name>
+              <description>Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PP</name>
+              <description>Page program enable(1 byte ~64 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WRSR</name>
+              <description>Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RDSR</name>
+              <description>Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RDID</name>
+              <description>Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WRDI</name>
+              <description>Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_WREN</name>
+              <description>Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_READ</name>
+              <description>Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>SPI1 address register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_ADDR_VALUE</name>
+              <description>In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>SPI1 control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x002CA000</resetValue>
+          <fields>
+            <field>
+              <name>FDUMMY_OUT</name>
+              <description>In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_OCT</name>
+              <description>Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_OCT</name>
+              <description>Set this bit to enable 8-bit-mode(8-bm) in DIN phase.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_OCT</name>
+              <description>Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Set this bit to enable 2-bit-mode(2-bm) in CMD phase.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Set this bit to enable 4-bit-mode(4-bm) in CMD phase.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_OCT</name>
+              <description>Set this bit to enable 8-bit-mode(8-bm) in CMD phase.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCS_CRC_EN</name>
+              <description>For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CRC_EN</name>
+              <description>For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FASTRD_MODE</name>
+              <description>This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESANDRES</name>
+              <description>The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WRSR_2B</name>
+              <description>Two bytes data will be written to status register when it is set. 1: enable 0: disable.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DIO</name>
+              <description>In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QIO</name>
+              <description>In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL1</name>
+          <description>SPI1 control1 register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFC</resetValue>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_DLY_RES</name>
+              <description>After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL2</name>
+          <description>SPI1 control2 register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SYNC_RESET</name>
+              <description>The FSM will be reset.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM.</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00030103</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>It must equal to the value of SPI_MEM_CLKCNT_N.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI1 user register.</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80000000</resetValue>
+          <fields>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DUAL</name>
+              <description>Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QUAD</name>
+              <description>Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DIO</name>
+              <description>Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QIO</name>
+              <description>Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO_HIGHPART</name>
+              <description>DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI_HIGHPART</name>
+              <description>DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI</name>
+              <description>Set this bit to enable the DOUT phase of an write-data operation.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO</name>
+              <description>Set this bit to enable enable the DIN phase of a read-data operation.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>Set this bit to enable enable the DUMMY phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR</name>
+              <description>Set this bit to enable enable the ADDR phase of an operation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND</name>
+              <description>Set this bit to enable enable the CMD phase of an operation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI1 user1 register.</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x5C000007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The SPI_CLK cycle length minus 1 of DUMMY phase.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of ADDR phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI1 user2 register.</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x70000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of user defined(USR) command.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of CMD phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MOSI_DLEN</name>
+          <description>SPI1 write-data bit length register.</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MOSI_DBITLEN</name>
+              <description>The length in bits of DOUT phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISO_DLEN</name>
+          <description>SPI1 read-data bit length register.</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_MISO_DBITLEN</name>
+              <description>The length in bits of DIN phase. The register value shall be (bit_num-1).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RD_STATUS</name>
+          <description>SPI1 read control register.</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATUS</name>
+              <description>The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WB_MODE</name>
+              <description>Mode bits in the flash fast read mode  it is combined with SPI_MEM_FASTRD_MODE bit.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXT_ADDR</name>
+          <description>SPI1 extended address register.</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EXT_ADDR</name>
+              <description>The register are the higher 32bits in the 64 bits address mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI1 misc register.</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>CS0_DIS</name>
+              <description>Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS1_DIS</name>
+              <description>Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>SPI_CS line keep low when the bit is set.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTO_PER</name>
+              <description>Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_CRC</name>
+          <description>SPI1 CRC data register.</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>DATA</name>
+              <description>For SPI1, the value of crc32.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_FCTRL</name>
+          <description>SPI1 bit mode control register.</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CACHE_USR_CMD_4BYTE</name>
+              <description>Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_DUAL</name>
+              <description>When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_DUAL</name>
+              <description>When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDIN_QUAD</name>
+              <description>When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FDOUT_QUAD</name>
+              <description>When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM</name>
+          <description>SPI1 state machine(FSM) status register.</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST</name>
+              <description>The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W0</name>
+          <description>SPI1 memory data buffer0</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W1</name>
+          <description>SPI1 memory data buffer1</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W2</name>
+          <description>SPI1 memory data buffer2</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W3</name>
+          <description>SPI1 memory data buffer3</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W4</name>
+          <description>SPI1 memory data buffer4</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W5</name>
+          <description>SPI1 memory data buffer5</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W6</name>
+          <description>SPI1 memory data buffer6</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W7</name>
+          <description>SPI1 memory data buffer7</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W8</name>
+          <description>SPI1 memory data buffer8</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W9</name>
+          <description>SPI1 memory data buffer9</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W10</name>
+          <description>SPI1 memory data buffer10</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W11</name>
+          <description>SPI1 memory data buffer11</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W12</name>
+          <description>SPI1 memory data buffer12</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W13</name>
+          <description>SPI1 memory data buffer13</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W14</name>
+          <description>SPI1 memory data buffer14</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W15</name>
+          <description>SPI1 memory data buffer15</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_WAITI_CTRL</name>
+          <description>SPI1 wait idle control register</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000014</resetValue>
+          <fields>
+            <field>
+              <name>WAITI_EN</name>
+              <description>Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAITI_DUMMY</name>
+              <description>Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR).</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAITI_CMD</name>
+              <description>The command value of auto wait flash idle transfer(RDSR).</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAITI_DUMMY_CYCLELEN</name>
+              <description>The dummy cycle length when wait flash idle(RDSR).</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_SUS_CMD</name>
+          <description>SPI1 flash suspend control register</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FLASH_PER</name>
+              <description>program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES</name>
+              <description>program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PER_WAIT_EN</name>
+              <description>Set this bit to add delay time after program erase resume(PER) is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_WAIT_EN</name>
+              <description>Set this bit to add delay time after program erase suspend(PES) command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PES_PER_EN</name>
+              <description>Set this bit to enable PES transfer trigger PES transfer option.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PESR_IDLE_EN</name>
+              <description>1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLASH_SUS_CTRL</name>
+          <description>SPI1 flash suspend command register</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000EAF4</resetValue>
+          <fields>
+            <field>
+              <name>FLASH_PES_EN</name>
+              <description>Set this bit to enable auto-suspend function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PER_COMMAND</name>
+              <description>Program/Erase resume command value.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_COMMAND</name>
+              <description>Program/Erase suspend command value.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SUS_STATUS</name>
+          <description>SPI1 flash suspend status register</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>FLASH_SUS</name>
+              <description>The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_HPM_DLY_256</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_RES_DLY_256</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_DP_DLY_256</name>
+              <description>1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PER_DLY_256</name>
+              <description>Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FLASH_PES_DLY_256</name>
+              <description>Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMING_CALI</name>
+          <description>SPI1 timing compensation register when accesses to flash or Ext_RAM.</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMING_CALI</name>
+              <description>Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXTRA_DUMMY_CYCLELEN</name>
+              <description>Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DDR</name>
+          <description>SPI1 DDR control register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000020</resetValue>
+          <fields>
+            <field>
+              <name>SPI_FMEM_DDR_EN</name>
+              <description>1: in DDR mode,  0: in SDR mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_VAR_DUMMY</name>
+              <description>Set the bit to enable variable dummy cycle in DDRmode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_RDAT_SWP</name>
+              <description>Set the bit to reorder RX data of the word in DDR mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_WDAT_SWP</name>
+              <description>Set the bit to reorder TX data of the word in DDR mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_CMD_DIS</name>
+              <description>the bit is used to disable dual edge in command phase when DDR mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OUTMINBYTELEN</name>
+              <description>It is the minimum output data length in the panda device.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_USR_DDR_DQS_THD</name>
+              <description>The delay number of data strobe which from memory based on SPI_CLK.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_DQS_LOOP</name>
+              <description>1: Use internal signal  as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DDR_DQS_LOOP_MODE</name>
+              <description>When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK  as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is not active.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_EN</name>
+              <description>Set this bit to enable the differential SPI_CLK#.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_MODE</name>
+              <description>Set this bit to enable the SPI HyperBus mode.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_DQS_CA_IN</name>
+              <description>Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_DUMMY_2X</name>
+              <description>Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_CLK_DIFF_INV</name>
+              <description>Set this bit to invert SPI_DIFF when accesses to flash. .</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_OCTA_RAM_ADDR</name>
+              <description>Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI_FMEM_HYPERBUS_CA</name>
+              <description>Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>SPI1 clk_gate register</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate enable signal. 1: Enable. 0: Disable.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>SPI1 interrupt enable register</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PES_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TOTAL_TRANS_END_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ENA</name>
+              <description>The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>SPI1 interrupt clear register</description>
+          <addressOffset>0xF4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PES_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TOTAL_TRANS_END_INT_CLR</name>
+              <description>The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_CLR</name>
+              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>SPI1 interrupt raw register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PES_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOTAL_TRANS_END_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success.  0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_RAW</name>
+              <description>The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>SPI1 interrupt status register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PER_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PER_END_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PES_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_PES_END_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TOTAL_TRANS_END_INT_ST</name>
+              <description>The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BROWN_OUT_INT_ST</name>
+              <description>The status bit for SPI_MEM_BROWN_OUT_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>SPI0 version control register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101040</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI2</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <groupName>SPI2</groupName>
+      <baseAddress>0x60024000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x98</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SPI2</name>
+        <value>21</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CMD</name>
+          <description>Command control register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONF_BITLEN</name>
+              <description>Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UPDATE</name>
+              <description>Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR</name>
+              <description>User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ADDR</name>
+          <description>Address value register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>USR_ADDR_VALUE</name>
+              <description>Address to slave. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CTRL</name>
+          <description>SPI control register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x003C0000</resetValue>
+          <fields>
+            <field>
+              <name>DUMMY_OUT</name>
+              <description>0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_DUAL</name>
+              <description>Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_QUAD</name>
+              <description>Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FADDR_OCT</name>
+              <description>Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_DUAL</name>
+              <description>Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_QUAD</name>
+              <description>Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FCMD_OCT</name>
+              <description>Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_DUAL</name>
+              <description>In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_QUAD</name>
+              <description>In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FREAD_OCT</name>
+              <description>In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>Q_POL</name>
+              <description>The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_POL</name>
+              <description>The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HOLD_POL</name>
+              <description>SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WP_POL</name>
+              <description>Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RD_BIT_ORDER</name>
+              <description>In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WR_BIT_ORDER</name>
+              <description>In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK</name>
+          <description>SPI clock control register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x80003043</resetValue>
+          <fields>
+            <field>
+              <name>CLKCNT_L</name>
+              <description>In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_H</name>
+              <description>In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKCNT_N</name>
+              <description>In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLKDIV_PRE</name>
+              <description>In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EQU_SYSCLK</name>
+              <description>In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER</name>
+          <description>SPI USER control register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x800000C0</resetValue>
+          <fields>
+            <field>
+              <name>DOUTDIN</name>
+              <description>Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>QPI_MODE</name>
+              <description>Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OPI_MODE</name>
+              <description>Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD</name>
+              <description>spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP</name>
+              <description>spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSCK_I_EDGE</name>
+              <description>In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_OUT_EDGE</name>
+              <description>the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_DUAL</name>
+              <description>In the write operations read-data phase apply 2 signals. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_QUAD</name>
+              <description>In the write operations read-data phase apply 4 signals. Can be configured in CONF state.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FWRITE_OCT</name>
+              <description>In the write operations read-data phase apply 8 signals. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_CONF_NXT</name>
+              <description>1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIO</name>
+              <description>Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO_HIGHPART</name>
+              <description>read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI_HIGHPART</name>
+              <description>write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY_IDLE</name>
+              <description>spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MOSI</name>
+              <description>This bit enable the write-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_MISO</name>
+              <description>This bit enable the read-data phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_DUMMY</name>
+              <description>This bit enable the dummy phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR</name>
+              <description>This bit enable the address phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND</name>
+              <description>This bit enable the command phase of an operation. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER1</name>
+          <description>SPI USER control register 1</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xB8410007</resetValue>
+          <fields>
+            <field>
+              <name>USR_DUMMY_CYCLELEN</name>
+              <description>The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_WFULL_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_SETUP_TIME</name>
+              <description>(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_HOLD_TIME</name>
+              <description>delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_ADDR_BITLEN</name>
+              <description>The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>USER2</name>
+          <description>SPI USER control register 2</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x78000000</resetValue>
+          <fields>
+            <field>
+              <name>USR_COMMAND_VALUE</name>
+              <description>The value of  command. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_REMPTY_ERR_END_EN</name>
+              <description>1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USR_COMMAND_BITLEN</name>
+              <description>The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MS_DLEN</name>
+          <description>SPI data bit length control register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MS_DATA_BITLEN</name>
+              <description>The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC</name>
+          <description>SPI misc register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000003E</resetValue>
+          <fields>
+            <field>
+              <name>CS0_DIS</name>
+              <description>SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS1_DIS</name>
+              <description>SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS2_DIS</name>
+              <description>SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS3_DIS</name>
+              <description>SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS4_DIS</name>
+              <description>SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS5_DIS</name>
+              <description>SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_DIS</name>
+              <description>1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MASTER_CS_POL</name>
+              <description>In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_DATA_DTR_EN</name>
+              <description>1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DATA_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADDR_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CMD_DTR_EN</name>
+              <description>1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLAVE_CS_POL</name>
+              <description>spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DQS_IDLE_EDGE</name>
+              <description>The default value of spi_dqs. Can be configured in CONF state.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CK_IDLE_EDGE</name>
+              <description>1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CS_KEEP_ACTIVE</name>
+              <description>spi cs line keep low when the bit is set. Can be configured in CONF state.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>QUAD_DIN_PIN_SWAP</name>
+              <description>1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_MODE</name>
+          <description>SPI input delay mode configuration</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN4_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN5_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN6_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN7_MODE</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMING_HCLK_ACTIVE</name>
+              <description>1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIN_NUM</name>
+          <description>SPI input delay number configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DIN0_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN1_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN2_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN3_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN4_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN5_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN6_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIN7_NUM</name>
+              <description>the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOUT_MODE</name>
+          <description>SPI output delay mode configuration</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DOUT0_MODE</name>
+              <description>The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT1_MODE</name>
+              <description>The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT2_MODE</name>
+              <description>The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT3_MODE</name>
+              <description>The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT4_MODE</name>
+              <description>The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT5_MODE</name>
+              <description>The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT6_MODE</name>
+              <description>The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DOUT7_MODE</name>
+              <description>The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_DQS_MODE</name>
+              <description>The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_CONF</name>
+          <description>SPI DMA control register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY</name>
+              <description>Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_INFIFO_FULL</name>
+              <description>Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_SLV_SEG_TRANS_EN</name>
+              <description>Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_TX_SEG_TRANS_CLR_EN</name>
+              <description>1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_EOF_EN</name>
+              <description>1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled receive data mode.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_TX_ENA</name>
+              <description>Set this bit to enable SPI DMA controlled send data mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_AFIFO_RST</name>
+              <description>Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BUF_AFIFO_RST</name>
+              <description>Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_AFIFO_RST</name>
+              <description>Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ENA</name>
+          <description>SPI interrupt enable register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_ENA</name>
+              <description>The enable bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_ENA</name>
+              <description>The enable bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_ENA</name>
+              <description>The enable bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_ENA</name>
+              <description>The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_ENA</name>
+              <description>The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP2_INT_ENA</name>
+              <description>The enable bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP1_INT_ENA</name>
+              <description>The enable bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_CLR</name>
+          <description>SPI interrupt clear register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_CLR</name>
+              <description>The clear bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_CLR</name>
+              <description>The clear bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_CLR</name>
+              <description>The clear bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_CLR</name>
+              <description>The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_CLR</name>
+              <description>The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_CLR</name>
+              <description>The clear bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_CLR</name>
+              <description>The clear bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_RAW</name>
+          <description>SPI interrupt raw register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_RAW</name>
+              <description>1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_RAW</name>
+              <description>The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_RAW</name>
+              <description>The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_RAW</name>
+              <description>The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_RAW</name>
+              <description>The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_RAW</name>
+              <description>The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_RAW</name>
+              <description>The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_RAW</name>
+              <description>The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_ST</name>
+          <description>SPI interrupt status register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_ST</name>
+              <description>The status bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_ST</name>
+              <description>The status bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_ST</name>
+              <description>The status bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_ST</name>
+              <description>The status bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_ST</name>
+              <description>The status bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_ST</name>
+              <description>The status bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_ST</name>
+              <description>The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_ST</name>
+              <description>The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_ST</name>
+              <description>The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_ST</name>
+              <description>The status bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_ST</name>
+              <description>The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_ST</name>
+              <description>The status bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_ST</name>
+              <description>The status bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DMA_INT_SET</name>
+          <description>SPI interrupt software set register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMA_INFIFO_FULL_ERR_INT_SET</name>
+              <description>The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_OUTFIFO_EMPTY_ERR_INT_SET</name>
+              <description>The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EX_QPI_INT_SET</name>
+              <description>The software set bit for SPI slave Ex_QPI interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_EN_QPI_INT_SET</name>
+              <description>The software set bit for SPI slave En_QPI interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD7_INT_SET</name>
+              <description>The software set bit for SPI slave CMD7 interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD8_INT_SET</name>
+              <description>The software set bit for SPI slave CMD8 interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD9_INT_SET</name>
+              <description>The software set bit for SPI slave CMD9 interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMDA_INT_SET</name>
+              <description>The software set bit for SPI slave CMDA interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_DMA_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_DMA_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_RD_BUF_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_WR_BUF_DONE_INT_SET</name>
+              <description>The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TRANS_DONE_INT_SET</name>
+              <description>The software set bit for SPI_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DMA_SEG_TRANS_DONE_INT_SET</name>
+              <description>The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEG_MAGIC_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_BUF_ADDR_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SLV_CMD_ERR_INT_SET</name>
+              <description>The software set bit for SPI_SLV_CMD_ERR_INT interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_RX_AFIFO_WFULL_ERR_INT_SET</name>
+              <description>The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MST_TX_AFIFO_REMPTY_ERR_INT_SET</name>
+              <description>The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP2_INT_SET</name>
+              <description>The software set bit for SPI_APP2_INT interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP1_INT_SET</name>
+              <description>The software set bit for SPI_APP1_INT interrupt.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W0</name>
+          <description>SPI CPU-controlled buffer0</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF0</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W1</name>
+          <description>SPI CPU-controlled buffer1</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF1</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W2</name>
+          <description>SPI CPU-controlled buffer2</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF2</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W3</name>
+          <description>SPI CPU-controlled buffer3</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF3</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W4</name>
+          <description>SPI CPU-controlled buffer4</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF4</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W5</name>
+          <description>SPI CPU-controlled buffer5</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF5</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W6</name>
+          <description>SPI CPU-controlled buffer6</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF6</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W7</name>
+          <description>SPI CPU-controlled buffer7</description>
+          <addressOffset>0xB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF7</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W8</name>
+          <description>SPI CPU-controlled buffer8</description>
+          <addressOffset>0xB8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF8</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W9</name>
+          <description>SPI CPU-controlled buffer9</description>
+          <addressOffset>0xBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF9</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W10</name>
+          <description>SPI CPU-controlled buffer10</description>
+          <addressOffset>0xC0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF10</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W11</name>
+          <description>SPI CPU-controlled buffer11</description>
+          <addressOffset>0xC4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF11</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W12</name>
+          <description>SPI CPU-controlled buffer12</description>
+          <addressOffset>0xC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF12</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W13</name>
+          <description>SPI CPU-controlled buffer13</description>
+          <addressOffset>0xCC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF13</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W14</name>
+          <description>SPI CPU-controlled buffer14</description>
+          <addressOffset>0xD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF14</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>W15</name>
+          <description>SPI CPU-controlled buffer15</description>
+          <addressOffset>0xD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BUF15</name>
+              <description>data buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE</name>
+          <description>SPI slave control register</description>
+          <addressOffset>0xE0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02800000</resetValue>
+          <fields>
+            <field>
+              <name>CLK_MODE</name>
+              <description>SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_MODE_13</name>
+              <description>{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSCK_DATA_OUT</name>
+              <description>It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRDMA_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_RDBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_WRBUF_BITLEN_EN</name>
+              <description>1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_SEG_MAGIC_VALUE</name>
+              <description>The magic value of BM table in master DMA seg-trans.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MODE</name>
+              <description>Set SPI work mode. 1: slave mode 0: master mode.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOFT_RESET</name>
+              <description>Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USR_CONF</name>
+              <description>1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLAVE1</name>
+          <description>SPI slave control register 1</description>
+          <addressOffset>0xE4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SLV_DATA_BITLEN</name>
+              <description>The transferred data bit length in SPI slave FD and HD mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>18</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_COMMAND</name>
+              <description>In the slave mode it is the value of command.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLV_LAST_ADDR</name>
+              <description>In the slave mode it is the value of address.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_GATE</name>
+          <description>SPI module clock and register clock control</description>
+          <addressOffset>0xE8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Set this bit to enable clk gate</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_CLK_ACTIVE</name>
+              <description>Set this bit to power on the SPI module clock.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MST_CLK_SEL</name>
+              <description>This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control</description>
+          <addressOffset>0xF0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101190</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>SPI register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="SPI2">
+      <name>SPI3</name>
+      <description>SPI (Serial Peripheral Interface) Controller</description>
+      <baseAddress>0x60025000</baseAddress>
+      <interrupt>
+        <name>SPI3</name>
+        <value>22</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>SYSTEM</name>
+      <description>System</description>
+      <groupName>SYSTEM</groupName>
+      <baseAddress>0x600C0000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xA8</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>CORE_1_CONTROL_0</name>
+          <description>Core0 control regiter 0</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000004</resetValue>
+          <fields>
+            <field>
+              <name>CONTROL_CORE_1_RUNSTALL</name>
+              <description>Set 1 to stall core1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONTROL_CORE_1_CLKGATE_EN</name>
+              <description>Set 1 to open core1 clock</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONTROL_CORE_1_RESETING</name>
+              <description>Set 1 to let core1 reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CORE_1_CONTROL_1</name>
+          <description>Core0 control regiter 1</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CONTROL_CORE_1_MESSAGE</name>
+              <description>it's only a R/W register, no function, software can write any value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_CLK_EN</name>
+          <description>cpu_peripheral clock configuration register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN_ASSIST_DEBUG</name>
+              <description>Set 1 to open assist_debug module clock</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN_DEDICATED_GPIO</name>
+              <description>Set 1 to open dedicated_gpio module clk</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PERI_RST_EN</name>
+          <description>cpu_peripheral reset configuration regsiter</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000C0</resetValue>
+          <fields>
+            <field>
+              <name>RST_EN_ASSIST_DEBUG</name>
+              <description>Set 1 to let assist_debug module reset</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_EN_DEDICATED_GPIO</name>
+              <description>Set 1 to let dedicated_gpio module reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_PER_CONF</name>
+          <description>cpu peripheral clock configuration register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000C</resetValue>
+          <fields>
+            <field>
+              <name>CPUPERIOD_SEL</name>
+              <description>This field used to sel cpu clock frequent.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLL_FREQ_SEL</name>
+              <description>This field used to sel pll frequent.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_WAIT_MODE_FORCE_ON</name>
+              <description>Set 1 to force cpu_waiti_clk enable.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CPU_WAITI_DELAY_NUM</name>
+              <description>This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_PD_MASK</name>
+          <description>memory power down mask configuration register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>LSLP_MEM_PD_MASK</name>
+              <description>Set 1 to mask memory power down.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_CLK_EN0</name>
+          <description>peripheral clock configuration regsiter 0</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xF9C1E06F</resetValue>
+          <fields>
+            <field>
+              <name>TIMERS_CLK_EN</name>
+              <description>Set 1 to enable TIMERS clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI01_CLK_EN</name>
+              <description>Set 1 to enable SPI01 clock</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_CLK_EN</name>
+              <description>Set 1 to enable UART clock</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDG_CLK_EN</name>
+              <description>Set 1 to enable WDG clock</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S0_CLK_EN</name>
+              <description>Set 1 to enable I2S0 clock</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CLK_EN</name>
+              <description>Set 1 to enable UART1 clock</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_CLK_EN</name>
+              <description>Set 1 to enable SPI2 clock</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT0_CLK_EN</name>
+              <description>Set 1 to enable I2C_EXT0 clock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI0_CLK_EN</name>
+              <description>Set 1 to enable UHCI0 clock</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_CLK_EN</name>
+              <description>Set 1 to enable RMT clock</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCNT_CLK_EN</name>
+              <description>Set 1 to enable PCNT clock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_CLK_EN</name>
+              <description>Set 1 to enable LEDC clock</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI1_CLK_EN</name>
+              <description>Set 1 to enable UHCI1 clock</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_CLK_EN</name>
+              <description>Set 1 to enable TIMERGROUP clock</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_CLK_EN</name>
+              <description>Set 1 to enable EFUSE clock</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP1_CLK_EN</name>
+              <description>Set 1 to enable TIMERGROUP1 clock</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_CLK_EN</name>
+              <description>Set 1 to enable SPI3 clock</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM0_CLK_EN</name>
+              <description>Set 1 to enable PWM0 clock</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT1_CLK_EN</name>
+              <description>Set 1 to enable I2C_EXT1 clock</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAN_CLK_EN</name>
+              <description>Set 1 to enable CAN clock</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM1_CLK_EN</name>
+              <description>Set 1 to enable PWM1 clock</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S1_CLK_EN</name>
+              <description>Set 1 to enable I2S1 clock</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_DMA_CLK_EN</name>
+              <description>Set 1 to enable SPI2_DMA clock</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_CLK_EN</name>
+              <description>Set 1 to enable USB clock</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_CLK_EN</name>
+              <description>Set 1 to enable UART_MEM clock</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM2_CLK_EN</name>
+              <description>Set 1 to enable PWM2 clock</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM3_CLK_EN</name>
+              <description>Set 1 to enable PWM3 clock</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_DMA_CLK_EN</name>
+              <description>Set 1 to enable SPI4 clock</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_CLK_EN</name>
+              <description>Set 1 to enable APB_SARADC clock</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_CLK_EN</name>
+              <description>Set 1 to enable SYSTEMTIMER clock</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_ARB_CLK_EN</name>
+              <description>Set 1 to enable ADC2_ARB clock</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI4_CLK_EN</name>
+              <description>Set 1 to enable SPI4 clock</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_CLK_EN1</name>
+          <description>peripheral clock configuration regsiter 1</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000600</resetValue>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_CLK_EN</name>
+              <description>Set 1 to enable BACKUP clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_AES_CLK_EN</name>
+              <description>Set 1 to enable AES clock</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_SHA_CLK_EN</name>
+              <description>Set 1 to enable SHA clock</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_RSA_CLK_EN</name>
+              <description>Set 1 to enable RSA clock</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_DS_CLK_EN</name>
+              <description>Set 1 to enable DS clock</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_HMAC_CLK_EN</name>
+              <description>Set 1 to enable HMAC clock</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_CLK_EN</name>
+              <description>Set 1 to enable DMA clock</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_HOST_CLK_EN</name>
+              <description>Set 1 to enable SDIO_HOST clock</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CAM_CLK_EN</name>
+              <description>Set 1 to enable LCD_CAM clock</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART2_CLK_EN</name>
+              <description>Set 1 to enable UART2 clock</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DEVICE_CLK_EN</name>
+              <description>Set 1 to enable USB_DEVICE clock</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_RST_EN0</name>
+          <description>peripheral reset configuration register0</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMERS_RST</name>
+              <description>Set 1 to let TIMERS reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI01_RST</name>
+              <description>Set 1 to let SPI01 reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RST</name>
+              <description>Set 1 to let UART reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDG_RST</name>
+              <description>Set 1 to let WDG reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S0_RST</name>
+              <description>Set 1 to let I2S0 reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_RST</name>
+              <description>Set 1 to let UART1 reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_RST</name>
+              <description>Set 1 to let SPI2 reset</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT0_RST</name>
+              <description>Set 1 to let I2C_EXT0 reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI0_RST</name>
+              <description>Set 1 to let UHCI0 reset</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RMT_RST</name>
+              <description>Set 1 to let RMT reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PCNT_RST</name>
+              <description>Set 1 to let PCNT reset</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEDC_RST</name>
+              <description>Set 1 to let LEDC reset</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UHCI1_RST</name>
+              <description>Set 1 to let UHCI1 reset</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP_RST</name>
+              <description>Set 1 to let TIMERGROUP reset</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EFUSE_RST</name>
+              <description>Set 1 to let EFUSE reset</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMERGROUP1_RST</name>
+              <description>Set 1 to let TIMERGROUP1 reset</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_RST</name>
+              <description>Set 1 to let SPI3 reset</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM0_RST</name>
+              <description>Set 1 to let PWM0 reset</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2C_EXT1_RST</name>
+              <description>Set 1 to let I2C_EXT1 reset</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CAN_RST</name>
+              <description>Set 1 to let CAN reset</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM1_RST</name>
+              <description>Set 1 to let PWM1 reset</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S1_RST</name>
+              <description>Set 1 to let I2S1 reset</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI2_DMA_RST</name>
+              <description>Set 1 to let SPI2 reset</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_RST</name>
+              <description>Set 1 to let USB reset</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_MEM_RST</name>
+              <description>Set 1 to let UART_MEM reset</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM2_RST</name>
+              <description>Set 1 to let PWM2 reset</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWM3_RST</name>
+              <description>Set 1 to let PWM3 reset</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI3_DMA_RST</name>
+              <description>Set 1 to let SPI3 reset</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APB_SARADC_RST</name>
+              <description>Set 1 to let APB_SARADC reset</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYSTIMER_RST</name>
+              <description>Set 1 to let SYSTIMER reset</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADC2_ARB_RST</name>
+              <description>Set 1 to let ADC2_ARB reset</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI4_RST</name>
+              <description>Set 1 to let SPI4 reset</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PERIP_RST_EN1</name>
+          <description>peripheral reset configuration regsiter 1</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000001FE</resetValue>
+          <fields>
+            <field>
+              <name>PERI_BACKUP_RST</name>
+              <description>Set 1 to let BACKUP reset</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_AES_RST</name>
+              <description>Set 1 to let CRYPTO_AES reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_SHA_RST</name>
+              <description>Set 1 to let CRYPTO_SHA reset</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_RSA_RST</name>
+              <description>Set 1 to let CRYPTO_RSA reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_DS_RST</name>
+              <description>Set 1 to let CRYPTO_DS reset</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRYPTO_HMAC_RST</name>
+              <description>Set 1 to let CRYPTO_HMAC reset</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMA_RST</name>
+              <description>Set 1 to let DMA reset</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SDIO_HOST_RST</name>
+              <description>Set 1 to let SDIO_HOST reset</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LCD_CAM_RST</name>
+              <description>Set 1 to let LCD_CAM reset</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART2_RST</name>
+              <description>Set 1 to let UART2 reset</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_DEVICE_RST</name>
+              <description>Set 1 to let USB_DEVICE reset</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_LPCK_DIV_INT</name>
+          <description>low power clock frequent division factor configuration regsiter</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000FF</resetValue>
+          <fields>
+            <field>
+              <name>BT_LPCK_DIV_NUM</name>
+              <description>This field is lower power clock frequent division factor</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BT_LPCK_DIV_FRAC</name>
+          <description>low power clock configuration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02001001</resetValue>
+          <fields>
+            <field>
+              <name>BT_LPCK_DIV_B</name>
+              <description>This field is lower power clock frequent division factor b</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BT_LPCK_DIV_A</name>
+              <description>This field is lower power clock frequent division factor a</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_RTC_SLOW</name>
+              <description>Set 1 to select rtc-slow clock as rtc low power clock</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_8M</name>
+              <description>Set 1 to select 8m clock as rtc low power clock</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL</name>
+              <description>Set 1 to select xtal clock as rtc low power clock</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_SEL_XTAL32K</name>
+              <description>Set 1 to select xtal32k clock as low power clock</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LPCLK_RTC_EN</name>
+              <description>Set 1 to enable RTC low power clock</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_0</name>
+          <description>interrupt source register 0</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_0</name>
+              <description>Set 1 to generate cpu interrupt 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_1</name>
+          <description>interrupt source register 1</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_1</name>
+              <description>Set 1 to generate cpu interrupt 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_2</name>
+          <description>interrupt source register 2</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_2</name>
+              <description>Set 1 to generate cpu interrupt 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CPU_INTR_FROM_CPU_3</name>
+          <description>interrupt source register 3</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CPU_INTR_FROM_CPU_3</name>
+              <description>Set 1 to generate cpu interrupt 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RSA_PD_CTRL</name>
+          <description>rsa memory power control register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RSA_MEM_PD</name>
+              <description>Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PU</name>
+              <description>Set 1 to force power up RSA memory, this bit has the second highest priority.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSA_MEM_FORCE_PD</name>
+              <description>Set 1 to force power down RSA memory,this bit has the highest priority.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EDMA_CTRL</name>
+          <description>EDMA control register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>EDMA_CLK_ON</name>
+              <description>Set 1 to enable EDMA clock.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EDMA_RESET</name>
+              <description>Set 1 to let EDMA reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CACHE_CONTROL</name>
+          <description>Cache control register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000005</resetValue>
+          <fields>
+            <field>
+              <name>ICACHE_CLK_ON</name>
+              <description>Set 1 to enable icache clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ICACHE_RESET</name>
+              <description>Set 1 to let icache reset</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_CLK_ON</name>
+              <description>Set 1 to enable dcache clock</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DCACHE_RESET</name>
+              <description>Set 1 to let dcache reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL</name>
+          <description>External memory encrypt and decrypt control register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE_SPI_MANUAL_ENCRYPT</name>
+              <description>Set 1 to enable the SPI manual encrypt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_DB_ENCRYPT</name>
+              <description>Set 1 to enable download DB encrypt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_G0CB_DECRYPT</name>
+              <description>Set 1 to enable download G0CB decrypt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENABLE_DOWNLOAD_MANUAL_ENCRYPT</name>
+              <description>Set 1 to enable download manual encrypt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_FASTMEM_CONFIG</name>
+          <description>RTC fast memory configuration register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x7FF00000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_MEM_CRC_START</name>
+              <description>Set 1 to start the CRC of RTC memory</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_ADDR</name>
+              <description>This field is used to set address of RTC memory for CRC.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_LEN</name>
+              <description>This field is used to set length of RTC memory for CRC based on start address.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_MEM_CRC_FINISH</name>
+              <description>This bit stores the status of RTC memory CRC.1 means finished.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_FASTMEM_CRC</name>
+          <description>RTC fast memory CRC control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_MEM_CRC_RES</name>
+              <description>This field stores the CRC result of RTC memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REDUNDANT_ECO_CTRL</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>REDUNDANT_ECO_DRIVE</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REDUNDANT_ECO_RESULT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_GATE</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SYSCLK_CONF</name>
+          <description>System clock configuration register.</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>PRE_DIV_CNT</name>
+              <description>This field is used to set the count of prescaler of XTAL_CLK.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOC_CLK_SEL</name>
+              <description>This field is used to select soc clock.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_XTAL_FREQ</name>
+              <description>This field is used to read xtal frequency in MHz.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CLK_DIV_EN</name>
+              <description>Reserved.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_PVT</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>MEM_PATH_LEN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_ERR_CNT_CLR</name>
+              <description>******* Description ***********</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>MONITOR_EN</name>
+              <description>******* Description ***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_TIMING_ERR_CNT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MEM_VT_SEL</name>
+              <description>******* Description ***********</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_LVT_CONF</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>COMB_PATH_LEN_LVT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMB_ERR_CNT_CLR_LVT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COMB_PVT_MONITOR_EN_LVT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_NVT_CONF</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>COMB_PATH_LEN_NVT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMB_ERR_CNT_CLR_NVT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COMB_PVT_MONITOR_EN_NVT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_HVT_CONF</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000003</resetValue>
+          <fields>
+            <field>
+              <name>COMB_PATH_LEN_HVT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>COMB_ERR_CNT_CLR_HVT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>COMB_PVT_MONITOR_EN_HVT</name>
+              <description>******* Description ***********</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE0</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE0</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE0</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE0</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE0</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE0</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE1</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE1</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE1</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE1</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE1</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE1</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE2</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE2</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE2</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE2</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE2</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE2</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_LVT_SITE3</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_LVT_SITE3</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_NVT_SITE3</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_NVT_SITE3</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMB_PVT_ERR_HVT_SITE3</name>
+          <description>******* Description ***********</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>COMB_TIMING_ERR_CNT_HVT_SITE3</name>
+              <description>******* Description ***********</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>version register</description>
+          <addressOffset>0xFFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101220</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>version register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SYSTIMER</name>
+      <description>System Timer</description>
+      <groupName>SYSTIMER</groupName>
+      <baseAddress>0x60023000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x90</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>SYSTIMER_TARGET0</name>
+        <value>57</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET1</name>
+        <value>58</value>
+      </interrupt>
+      <interrupt>
+        <name>SYSTIMER_TARGET2</name>
+        <value>59</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF</name>
+          <description>Configure system timer clock</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x46000000</resetValue>
+          <fields>
+            <field>
+              <name>SYSTIMER_CLK_FO</name>
+              <description>systimer clock force on</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_WORK_EN</name>
+              <description>target2 work enable</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_WORK_EN</name>
+              <description>target1 work enable</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_WORK_EN</name>
+              <description>target0 work enable</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE1_STALL_EN</name>
+              <description>If timer unit1 is stalled when core1 stalled</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_CORE0_STALL_EN</name>
+              <description>If timer unit1 is stalled when core0 stalled</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE1_STALL_EN</name>
+              <description>If timer unit0 is stalled when core1 stalled</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_CORE0_STALL_EN</name>
+              <description>If timer unit0 is stalled when core0 stalled</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_WORK_EN</name>
+              <description>timer unit1 work enable</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_WORK_EN</name>
+              <description>timer unit0 work enable</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>register file clk gating</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_OP</name>
+          <description>system timer unit0 value update register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_VALID</name>
+              <description>timer value is sync and valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT0_UPDATE</name>
+              <description>update timer_unit0</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_OP</name>
+          <description>system timer unit1 value update register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_VALID</name>
+              <description>timer value is sync and valid</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TIMER_UNIT1_UPDATE</name>
+              <description>update timer unit1</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_HI</name>
+          <description>system timer unit0 value high load register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_HI</name>
+              <description>timer unit0 load high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD_LO</name>
+          <description>system timer unit0 value low load register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD_LO</name>
+              <description>timer unit0 load low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_HI</name>
+          <description>system timer unit1 value high load register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_HI</name>
+              <description>timer unit1 load high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD_LO</name>
+          <description>system timer unit1 value low load register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD_LO</name>
+              <description>timer unit1 load low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_HI</name>
+          <description>system timer comp0 value high register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_HI</name>
+              <description>timer taget0 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_LO</name>
+          <description>system timer comp0 value low register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET0_LO</name>
+              <description>timer taget0 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_HI</name>
+          <description>system timer comp1 value high register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_HI</name>
+              <description>timer taget1 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_LO</name>
+          <description>system timer comp1 value low register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET1_LO</name>
+              <description>timer taget1 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_HI</name>
+          <description>system timer comp2 value high register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_HI</name>
+              <description>timer taget2 high 20 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_LO</name>
+          <description>system timer comp2 value low register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_TARGET2_LO</name>
+              <description>timer taget2 low 32 bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET0_CONF</name>
+          <description>system timer comp0 target mode register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_PERIOD</name>
+              <description>target0 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_PERIOD_MODE</name>
+              <description>Set target0 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET0_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET1_CONF</name>
+          <description>system timer comp1 target mode register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_PERIOD</name>
+              <description>target1 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_PERIOD_MODE</name>
+              <description>Set target1 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TARGET2_CONF</name>
+          <description>system timer comp2 target mode register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_PERIOD</name>
+              <description>target2 period</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>26</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_PERIOD_MODE</name>
+              <description>Set target2 to period mode</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_TIMER_UNIT_SEL</name>
+              <description>select which unit to compare</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_HI</name>
+          <description>system timer unit0 value high register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_HI</name>
+              <description>timer read value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_VALUE_LO</name>
+          <description>system timer unit0 value low register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_VALUE_LO</name>
+              <description>timer read value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_HI</name>
+          <description>system timer unit1 value high register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_HI</name>
+              <description>timer read value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_VALUE_LO</name>
+          <description>system timer unit1 value low register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_VALUE_LO</name>
+              <description>timer read value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP0_LOAD</name>
+          <description>system timer comp0 conf sync register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP0_LOAD</name>
+              <description>timer comp0 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP1_LOAD</name>
+          <description>system timer comp1 conf sync register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP1_LOAD</name>
+              <description>timer comp1 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>COMP2_LOAD</name>
+          <description>system timer comp2 conf sync register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_COMP2_LOAD</name>
+              <description>timer comp2 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT0_LOAD</name>
+          <description>system timer unit0 conf sync register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT0_LOAD</name>
+              <description>timer unit0 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UNIT1_LOAD</name>
+          <description>system timer unit1 conf sync register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIMER_UNIT1_LOAD</name>
+              <description>timer unit1 sync enable signal</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>systimer interrupt enable register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ENA</name>
+              <description>interupt0 enable</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ENA</name>
+              <description>interupt1 enable</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ENA</name>
+              <description>interupt2 enable</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>systimer interrupt raw register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_RAW</name>
+              <description>interupt0 raw</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_RAW</name>
+              <description>interupt1 raw</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_RAW</name>
+              <description>interupt2 raw</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>systimer interrupt clear register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_CLR</name>
+              <description>interupt0 clear</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_CLR</name>
+              <description>interupt1 clear</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_CLR</name>
+              <description>interupt2 clear</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>systimer interrupt status register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_INT_ST</name>
+              <description>interupt0 status</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET1_INT_ST</name>
+              <description>interupt1 status</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TARGET2_INT_ST</name>
+              <description>interupt2 status</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET0_LO</name>
+          <description>system timer comp0 actual target value low register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_LO_RO</name>
+              <description>actual target value value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET0_HI</name>
+          <description>system timer comp0 actual target value high register</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET0_HI_RO</name>
+              <description>actual target value value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET1_LO</name>
+          <description>system timer comp1 actual target value low register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_LO_RO</name>
+              <description>actual target value value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET1_HI</name>
+          <description>system timer comp1 actual target value high register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET1_HI_RO</name>
+              <description>actual target value value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET2_LO</name>
+          <description>system timer comp2 actual target value low register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_LO_RO</name>
+              <description>actual target value value low 32bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REAL_TARGET2_HI</name>
+          <description>system timer comp2 actual target value high register</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TARGET2_HI_RO</name>
+              <description>actual target value value high 20bits</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>system timer version control register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02012251</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>systimer register version</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TIMG0</name>
+      <description>Timer Group</description>
+      <groupName>TIMG</groupName>
+      <baseAddress>0x6001F000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x8C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TG0_T0_LEVEL</name>
+        <value>50</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_T1_LEVEL</name>
+        <value>51</value>
+      </interrupt>
+      <interrupt>
+        <name>TG0_WDT_LEVEL</name>
+        <value>52</value>
+      </interrupt>
+      <registers>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sCONFIG</name>
+          <description>Timer %s configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x60002000</resetValue>
+          <fields>
+            <field>
+              <name>USE_XTAL</name>
+              <description>1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALARM_EN</name>
+              <description>When set, the alarm is enabled. This bit is automatically cleared once an
+alarm occurs.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIVIDER</name>
+              <description>Timer %s clock (T%s_clk) prescaler value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTORELOAD</name>
+              <description>When set, timer %s auto-reload at alarm is enabled.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCREASE</name>
+              <description>When set, the timer %s time-base counter will increment every clock tick. When
+cleared, the timer %s time-base counter will decrement.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EN</name>
+              <description>When set, the timer %s time-base counter is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sLO</name>
+          <description>Timer %s current value, low 32 bits</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LO</name>
+              <description>After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter
+of timer %s can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sHI</name>
+          <description>Timer %s current value, high 22 bits</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HI</name>
+              <description>After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter
+of timer %s can be read here.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sUPDATE</name>
+          <description>Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>UPDATE</name>
+              <description>After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sALARMLO</name>
+          <description>Timer %s alarm value, low 32 bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_LO</name>
+              <description>Timer %s alarm trigger time-base counter value, low 32 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sALARMHI</name>
+          <description>Timer %s alarm value, high bits</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ALARM_HI</name>
+              <description>Timer %s alarm trigger time-base counter value, high 22 bits.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sLOADLO</name>
+          <description>Timer %s reload value, low 32 bits</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_LO</name>
+              <description>Low 32 bits of the value that a reload will load onto timer %s time-base
+Counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sLOADHI</name>
+          <description>Timer %s reload value, high 22 bits</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD_HI</name>
+              <description>High 22 bits of the value that a reload will load onto timer %s time-base
+counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>22</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <dim>2</dim>
+          <dimIncrement>0x24</dimIncrement>
+          <name>T%sLOAD</name>
+          <description>Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LOAD</name>
+              <description>
+Write any value to trigger a timer %s time-base counter reload.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG0</name>
+          <description>Watchdog timer configuration register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0004C000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_APPCPU_RESET_EN</name>
+              <description>Reserved</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_PROCPU_RESET_EN</name>
+              <description>WDT reset CPU enable.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_FLASHBOOT_MOD_EN</name>
+              <description>When set, Flash boot protection is enabled.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_SYS_RESET_LENGTH</name>
+              <description>System reset signal length selection. 0: 100 ns, 1: 200 ns,
+2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_CPU_RESET_LENGTH</name>
+              <description>CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
+2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG3</name>
+              <description>Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG2</name>
+              <description>Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG1</name>
+              <description>Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_STG0</name>
+              <description>Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
+</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_EN</name>
+              <description>When set, MWDT is enabled.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG1</name>
+          <description>Watchdog timer prescaler register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00010000</resetValue>
+          <fields>
+            <field>
+              <name>WDT_CLK_PRESCALE</name>
+              <description>MWDT clock prescaler value. MWDT clock period = 12.5 ns *
+TIMG_WDT_CLK_PRESCALE.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG2</name>
+          <description>Watchdog timer stage 0 timeout value</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x018CBA80</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG0_HOLD</name>
+              <description>Stage 0 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG3</name>
+          <description>Watchdog timer stage 1 timeout value</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x07FFFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG1_HOLD</name>
+              <description>Stage 1 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG4</name>
+          <description>Watchdog timer stage 2 timeout value</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG2_HOLD</name>
+              <description>Stage 2 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTCONFIG5</name>
+          <description>Watchdog timer stage 3 timeout value</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000FFFFF</resetValue>
+          <fields>
+            <field>
+              <name>WDT_STG3_HOLD</name>
+              <description>Stage 3 timeout value, in MWDT clock cycles.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTFEED</name>
+          <description>Write to feed the watchdog timer</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>WDT_FEED</name>
+              <description>Write any value to feed the MWDT. (WO)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDTWPROTECT</name>
+          <description>Watchdog write protect register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x50D83AA1</resetValue>
+          <fields>
+            <field>
+              <name>WDT_WKEY</name>
+              <description>If the register contains a different value than its reset value, write
+protection is enabled.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG</name>
+          <description>RTC calibration configure register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00013000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_START_CYCLING</name>
+              <description>Reserved</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_CLK_SEL</name>
+              <description>0:rtc slow clock. 1:clk_80m.  2:xtal_32k.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_RDY</name>
+              <description>Reserved</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_MAX</name>
+              <description>Reserved</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>15</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_START</name>
+              <description>Reserved</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG1</name>
+          <description>RTC calibration configure1 register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RTC_CALI_CYCLING_DATA_VLD</name>
+              <description>Reserved</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_VALUE</name>
+              <description>Reserved</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA_TIMERS</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>T1_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_T1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WDT_INT_ENA</name>
+              <description>The interrupt enable bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW_TIMERS</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>T1_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_T1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_RAW</name>
+              <description>The raw interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST_TIMERS</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>T1_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_T1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_ST</name>
+              <description>The masked interrupt status bit for the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR_TIMERS</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>T0_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_T0_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>T1_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_T1_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WDT_INT_CLR</name>
+              <description>Set this bit to clear the TIMG_WDT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTCCALICFG2</name>
+          <description>Timer group calibration register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xFFFFFF98</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALI_TIMEOUT</name>
+              <description>RTC calibration timeout indicator</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_RST_CNT</name>
+              <description>Cycles that release calibration timeout reset</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALI_TIMEOUT_THRES</name>
+              <description>Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>25</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NTIMERS_DATE</name>
+          <description>Timer version control register</description>
+          <addressOffset>0xF8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02003071</resetValue>
+          <fields>
+            <field>
+              <name>NTIMERS_DATE</name>
+              <description>Timer version control register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>28</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REGCLK</name>
+          <description>Timer group clock gate register</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>Register clock gate signal. 1: The clock for software to read and write registers is always on. 0: The clock for software to read and write registers only exits when the operation happens.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="TIMG0">
+      <name>TIMG1</name>
+      <description>Timer Group</description>
+      <baseAddress>0x60020000</baseAddress>
+      <interrupt>
+        <name>TG1_T0_LEVEL</name>
+        <value>53</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_T1_LEVEL</name>
+        <value>54</value>
+      </interrupt>
+      <interrupt>
+        <name>TG1_WDT_LEVEL</name>
+        <value>55</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>TWAI</name>
+      <description>Two-Wire Automotive Interface</description>
+      <groupName>TWAI</groupName>
+      <baseAddress>0x6002B000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x6C</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>TWAI</name>
+        <value>45</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>MODE</name>
+          <description>Mode Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>RESET_MODE</name>
+              <description>This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LISTEN_ONLY_MODE</name>
+              <description>1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SELF_TEST_MODE</name>
+              <description>1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FILTER_MODE</name>
+              <description>This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CMD</name>
+          <description>Command Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_REQ</name>
+              <description>Set the bit to 1 to allow the driving nodes start transmission.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>ABORT_TX</name>
+              <description>Set the bit to 1 to cancel a pending transmission request.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RELEASE_BUF</name>
+              <description>Set the bit to 1 to release the RX buffer.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CLR_OVERRUN</name>
+              <description>Set the bit to 1 to clear the data overrun status bit.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SELF_RX_REQ</name>
+              <description>Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>Status register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_BUF_ST</name>
+              <description>1: The data in the RX buffer is not empty, with at least one received data packet.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN_ST</name>
+              <description>1: The RX FIFO is full and data overrun has occurred.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BUF_ST</name>
+              <description>1: The TX buffer is empty, the CPU may write a message into it.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_COMPLETE</name>
+              <description>1: The TWAI controller has successfully received a packet from the bus.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_ST</name>
+              <description>1: The TWAI Controller is receiving a message from the bus.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_ST</name>
+              <description>1: The TWAI Controller is transmitting a message to the bus.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_ST</name>
+              <description>1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_OFF_ST</name>
+              <description>1: In bus-off status, the TWAI Controller is no longer involved in bus activities.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MISS_ST</name>
+              <description>This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Interrupt Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_INT_ST</name>
+              <description>Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_INT_ST</name>
+              <description>Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_WARN_INT_ST</name>
+              <description>Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OVERRUN_INT_ST</name>
+              <description>Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ST</name>
+              <description>Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ARB_LOST_INT_ST</name>
+              <description>Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ST</name>
+              <description>Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt Enable Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_INT_ENA</name>
+              <description>Set this bit to 1 to enable receive interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_INT_ENA</name>
+              <description>Set this bit to 1 to enable transmit interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WARN_INT_ENA</name>
+              <description>Set this bit to 1 to enable error warning interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OVERRUN_INT_ENA</name>
+              <description>Set this bit to 1 to enable data overrun interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_PASSIVE_INT_ENA</name>
+              <description>Set this bit to 1 to enable error passive interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARB_LOST_INT_ENA</name>
+              <description>Set this bit to 1 to enable arbitration lost interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BUS_ERR_INT_ENA</name>
+              <description>Set this bit to 1 to enable error interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_0</name>
+          <description>Bus Timing Register 0</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>BAUD_PRESC</name>
+              <description>Baud Rate Prescaler, determines the frequency dividing ratio.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SYNC_JUMP_WIDTH</name>
+              <description>Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>BUS_TIMING_1</name>
+          <description>Bus Timing Register 1</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TIME_SEG1</name>
+              <description>The width of PBS1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SEG2</name>
+              <description>The width of PBS2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIME_SAMP</name>
+              <description>The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ARB_LOST_CAP</name>
+          <description>Arbitration Lost Capture Register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ARB_LOST_CAP</name>
+              <description>This register contains information about the bit position of lost arbitration.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_CODE_CAP</name>
+          <description>Error Code Capture Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ECC_SEGMENT</name>
+              <description>This register contains information about the location of errors, see Table 181 for details.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_DIRECTION</name>
+              <description>This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ECC_TYPE</name>
+              <description>This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ERR_WARNING_LIMIT</name>
+          <description>Error Warning Limit Register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000060</resetValue>
+          <fields>
+            <field>
+              <name>ERR_WARNING_LIMIT</name>
+              <description>Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_ERR_CNT</name>
+          <description>Receive Error Counter Register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CNT</name>
+              <description>The RX error counter register, reflects value changes under reception status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TX_ERR_CNT</name>
+          <description>Transmit Error Counter Register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_ERR_CNT</name>
+              <description>The TX error counter register, reflects value changes under transmission status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_0</name>
+          <description>Data register 0</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_0</name>
+              <description>In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_1</name>
+          <description>Data register 1</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_1</name>
+              <description>In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_2</name>
+          <description>Data register 2</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_2</name>
+              <description>In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_3</name>
+          <description>Data register 3</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_3</name>
+              <description>In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_4</name>
+          <description>Data register 4</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_4</name>
+              <description>In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_5</name>
+          <description>Data register 5</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_5</name>
+              <description>In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_6</name>
+          <description>Data register 6</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_6</name>
+              <description>In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_7</name>
+          <description>Data register 7</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_7</name>
+              <description>In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_8</name>
+          <description>Data register 8</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_8</name>
+              <description>Stored the 8th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_9</name>
+          <description>Data register 9</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_9</name>
+              <description>Stored the 9th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_10</name>
+          <description>Data register 10</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_10</name>
+              <description>Stored the 10th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_11</name>
+          <description>Data register 11</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_11</name>
+              <description>Stored the 11th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATA_12</name>
+          <description>Data register 12</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TX_BYTE_12</name>
+              <description>Stored the 12th byte information of the data to be transmitted under operating mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_MESSAGE_CNT</name>
+          <description>Receive Message Counter Register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_MESSAGE_COUNTER</name>
+              <description>This register reflects the number of messages available within the RX FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLOCK_DIVIDER</name>
+          <description>Clock Divider register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CD</name>
+              <description>These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLOCK_OFF</name>
+              <description>This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>UART0</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <groupName>UART</groupName>
+      <baseAddress>0x60000000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x84</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UART0</name>
+        <value>27</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>FIFO</name>
+          <description>FIFO data register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_RD_BYTE</name>
+              <description>UART 0 accesses FIFO via this register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error in the data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error .</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_RAW</name>
+              <description>This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ST</name>
+              <description>This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ST</name>
+              <description>This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ST</name>
+              <description>This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ST</name>
+              <description>This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ST</name>
+              <description>This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ST</name>
+              <description>This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ST</name>
+              <description>This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ST</name>
+              <description>This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ST</name>
+              <description>This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ST</name>
+              <description>This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ST</name>
+              <description>This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ST</name>
+              <description>This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ST</name>
+              <description>This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ST</name>
+              <description>This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ST</name>
+              <description>This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ST</name>
+              <description>This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ST</name>
+              <description>This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ST</name>
+              <description>This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_full_int_st register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_ENA</name>
+              <description>This is the enable bit for txfifo_empty_int_st register.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for parity_err_int_st register.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for frm_err_int_st register.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_ovf_int_st register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_ENA</name>
+              <description>This is the enable bit for dsr_chg_int_st register.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_ENA</name>
+              <description>This is the enable bit for cts_chg_int_st register.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_ENA</name>
+              <description>This is the enable bit for brk_det_int_st register.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_ENA</name>
+              <description>This is the enable bit for rxfifo_tout_int_st register.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_ENA</name>
+              <description>This is the enable bit for sw_xon_int_st register.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_ENA</name>
+              <description>This is the enable bit for sw_xoff_int_st register.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_ENA</name>
+              <description>This is the enable bit for glitch_det_int_st register.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_done_int_st register.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_brk_idle_done_int_st register.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_ENA</name>
+              <description>This is the enable bit for tx_done_int_st register.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_ENA</name>
+              <description>This is the enable bit for rs485_parity_err_int_st register.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_ENA</name>
+              <description>This is the enable bit for rs485_clash_int_st register.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_ENA</name>
+              <description>This is the enable bit for at_cmd_char_det_int_st register.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_ENA</name>
+              <description>This is the enable bit for uart_wakeup_int_st register.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_full_int_raw interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear txfifo_empty_int_raw interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear parity_err_int_raw interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear frm_err_int_raw interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_OVF_INT_CLR</name>
+              <description>Set this bit to clear rxfifo_ovf_int_raw interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DSR_CHG_INT_CLR</name>
+              <description>Set this bit to clear the dsr_chg_int_raw interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CTS_CHG_INT_CLR</name>
+              <description>Set this bit to clear the cts_chg_int_raw interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>BRK_DET_INT_CLR</name>
+              <description>Set this bit to clear the brk_det_int_raw interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RXFIFO_TOUT_INT_CLR</name>
+              <description>Set this bit to clear the rxfifo_tout_int_raw interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XON_INT_CLR</name>
+              <description>Set this bit to clear the sw_xon_int_raw interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SW_XOFF_INT_CLR</name>
+              <description>Set this bit to clear the sw_xoff_int_raw interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>GLITCH_DET_INT_CLR</name>
+              <description>Set this bit to clear the glitch_det_int_raw interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_done_int_raw interrupt..</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_BRK_IDLE_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_brk_idle_done_int_raw interrupt.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_DONE_INT_CLR</name>
+              <description>Set this bit to clear the tx_done_int_raw interrupt.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_PARITY_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_parity_err_int_raw interrupt.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_FRM_ERR_INT_CLR</name>
+              <description>Set this bit to clear the rs485_frm_err_int_raw interrupt.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RS485_CLASH_INT_CLR</name>
+              <description>Set this bit to clear the rs485_clash_int_raw interrupt.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>AT_CMD_CHAR_DET_INT_CLR</name>
+              <description>Set this bit to clear the at_cmd_char_det_int_raw interrupt.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>WAKEUP_INT_CLR</name>
+              <description>Set this bit to clear the uart_wakeup_int_raw interrupt.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLKDIV</name>
+          <description>Clock divider configuration</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000002B6</resetValue>
+          <fields>
+            <field>
+              <name>CLKDIV</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRAG</name>
+              <description>The decimal part of the frequency divider factor.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_FILT</name>
+          <description>Rx Filter configuration</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>GLITCH_FILT</name>
+              <description>when input pulse width is lower than this value, the pulse is ignored.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GLITCH_FILT_EN</name>
+              <description>Set this bit to enable Rx signal filter.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATUS</name>
+          <description>UART status register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xE000C000</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_CNT</name>
+              <description>Stores the byte number of valid data in Rx-FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DSRN</name>
+              <description>The register represent the level value of the internal uart dsr signal.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CTSN</name>
+              <description>This register represent the level value of the internal uart cts signal.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RXD</name>
+              <description>This register represent the  level value of the internal uart rxd signal.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXFIFO_CNT</name>
+              <description>Stores the byte number of data in Tx-FIFO.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DTRN</name>
+              <description>This bit represents the level of the internal uart dtr signal.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RTSN</name>
+              <description>This bit represents the level of the internal uart rts signal.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TXD</name>
+              <description>This bit represents the  level of the internal uart txd signal.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0</name>
+          <description>a</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x1000001C</resetValue>
+          <fields>
+            <field>
+              <name>PARITY</name>
+              <description>This register is used to configure the parity check mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PARITY_EN</name>
+              <description>Set this bit to enable uart parity check.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BIT_NUM</name>
+              <description>This register is used to set the length of data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STOP_BIT_NUM</name>
+              <description>This register is used to set the length of  stop bit.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_RTS</name>
+              <description>This register is used to configure the software rts signal which is used in software flow control.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_DTR</name>
+              <description>This register is used to configure the software dtr signal which is used in software flow control.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_BRK</name>
+              <description>Set this bit to enbale transmitter to  send NULL when the process of sending data is done.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_DPLX</name>
+              <description>Set this bit to enable IrDA loopback mode.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_EN</name>
+              <description>This is the start enable bit for IrDA transmitter.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_WCTL</name>
+              <description>1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_TX_INV</name>
+              <description>Set this bit to invert the level of  IrDA transmitter.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_RX_INV</name>
+              <description>Set this bit to invert the level of IrDA receiver.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOOPBACK</name>
+              <description>Set this bit to enable uart loopback test mode.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_FLOW_EN</name>
+              <description>Set this bit to enable flow control function for transmitter.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IRDA_EN</name>
+              <description>Set this bit to enable IrDA protocol.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_RST</name>
+              <description>Set this bit to reset the uart receive-FIFO.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_RST</name>
+              <description>Set this bit to reset the uart transmit-FIFO.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXD_INV</name>
+              <description>Set this bit to inverse the level value of uart rxd signal.</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CTS_INV</name>
+              <description>Set this bit to inverse the level value of uart cts signal.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DSR_INV</name>
+              <description>Set this bit to inverse the level value of uart dsr signal.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXD_INV</name>
+              <description>Set this bit to inverse the level value of uart txd signal.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTS_INV</name>
+              <description>Set this bit to inverse the level value of uart rts signal.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DTR_INV</name>
+              <description>Set this bit to inverse the level value of uart dtr signal.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERR_WR_MASK</name>
+              <description>1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AUTOBAUD_EN</name>
+              <description>This is the enable bit for detecting baudrate.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_CLK_EN</name>
+              <description>UART memory clock gate enable signal.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>Configuration register 1</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00018060</resetValue>
+          <fields>
+            <field>
+              <name>RXFIFO_FULL_THRHD</name>
+              <description>It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_EMPTY_THRHD</name>
+              <description>It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DIS_RX_DAT_OVF</name>
+              <description>Disable UART Rx data overflow detect.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_FLOW_DIS</name>
+              <description>Set this bit to stop accumulating idle_cnt when hardware flow control works.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_EN</name>
+              <description>This is the flow enable bit for UART receiver.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_EN</name>
+              <description>This is the enble bit for uart receiver's timeout function.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LOWPULSE</name>
+          <description>Autobaud minimum low pulse duration register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HIGHPULSE</name>
+          <description>Autobaud minimum high pulse duration register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>MIN_CNT</name>
+              <description>This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RXD_CNT</name>
+          <description>Autobaud edge change count register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RXD_EDGE_CNT</name>
+              <description>This register stores the count of rxd edge change. It is used in baud rate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FLOW_CONF</name>
+          <description>Software flow-control configuration</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SW_FLOW_CON_EN</name>
+              <description>Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XONOFF_DEL</name>
+              <description>Set this bit to remove flow control char from the received data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XON</name>
+              <description>Set this bit to enable the transmitter to go on sending data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCE_XOFF</name>
+              <description>Set this bit to stop the  transmitter from sending data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XON</name>
+              <description>Set this bit to send Xon char. It is cleared by hardware automatically.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_XOFF</name>
+              <description>Set this bit to send Xoff char. It is cleared by hardware automatically.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLEEP_CONF</name>
+          <description>Sleep-mode configuration</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000000F0</resetValue>
+          <fields>
+            <field>
+              <name>ACTIVE_THRESHOLD</name>
+              <description>The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF0</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004CE0</resetValue>
+          <fields>
+            <field>
+              <name>XOFF_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XOFF_CHAR</name>
+              <description>This register stores the Xoff flow control char.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SWFC_CONF1</name>
+          <description>Software flow-control character configuration</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004400</resetValue>
+          <fields>
+            <field>
+              <name>XON_THRESHOLD</name>
+              <description>When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XON_CHAR</name>
+              <description>This register stores the Xon flow control char.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TXBRK_CONF</name>
+          <description>Tx Break character configuration</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000A</resetValue>
+          <fields>
+            <field>
+              <name>TX_BRK_NUM</name>
+              <description>This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IDLE_CONF</name>
+          <description>Frame-end idle configuration</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040100</resetValue>
+          <fields>
+            <field>
+              <name>RX_IDLE_THRHD</name>
+              <description>It will produce frame end signal when receiver takes more time to receive one byte data than this register value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between transfers.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RS485_CONF</name>
+          <description>RS485 mode configuration</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RS485_EN</name>
+              <description>Set this bit to choose the rs485 mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL0_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DL1_EN</name>
+              <description>Set this bit to delay the stop bit by 1 bit.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485TX_RX_EN</name>
+              <description>Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485RXBY_TX_EN</name>
+              <description>1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_RX_DLY_NUM</name>
+              <description>This register is used to delay the receiver's internal data signal.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RS485_TX_DLY_NUM</name>
+              <description>This register is used to delay the transmitter's internal data signal.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_PRECNT</name>
+          <description>Pre-sequence timing configuration</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>PRE_IDLE_NUM</name>
+              <description>This register is used to configure the idle duration time before the first at_cmd is received by receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_POSTCNT</name>
+          <description>Post-sequence timing configuration</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000901</resetValue>
+          <fields>
+            <field>
+              <name>POST_IDLE_NUM</name>
+              <description>This register is used to configure the duration time between the last at_cmd and the next data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_GAPTOUT</name>
+          <description>Timeout configuration</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000000B</resetValue>
+          <fields>
+            <field>
+              <name>RX_GAP_TOUT</name>
+              <description>This register is used to configure the duration time between the at_cmd chars.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>AT_CMD_CHAR</name>
+          <description>AT escape sequence detection configuration</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x0000032B</resetValue>
+          <fields>
+            <field>
+              <name>AT_CMD_CHAR</name>
+              <description>This register is used to configure the content of at_cmd char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHAR_NUM</name>
+              <description>This register is used to configure the num of continuous at_cmd chars received by receiver.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>UART threshold and allocation configuration</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00140012</resetValue>
+          <fields>
+            <field>
+              <name>RX_SIZE</name>
+              <description>This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SIZE</name>
+              <description>This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_FLOW_THRHD</name>
+              <description>This register is used to configure the maximum amount of data that can be received  when hardware flow control works.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_TOUT_THRHD</name>
+              <description>This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PD</name>
+              <description>Set this bit to force power down UART memory.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>MEM_FORCE_PU</name>
+              <description>Set this bit to force power up UART memory.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_TX_STATUS</name>
+          <description>Tx-FIFO write and read offset address.</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APB_TX_WADDR</name>
+              <description>This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_RADDR</name>
+              <description>This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_RX_STATUS</name>
+          <description>Rx-FIFO write and read offset address.</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00100200</resetValue>
+          <fields>
+            <field>
+              <name>APB_RX_RADDR</name>
+              <description>This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_WADDR</name>
+              <description>This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FSM_STATUS</name>
+          <description>UART transmit and receive status.</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ST_URX_OUT</name>
+              <description>This is the status register of receiver.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ST_UTX_OUT</name>
+              <description>This is the status register of transmitter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>POSPULSE</name>
+          <description>Autobaud high pulse register</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>POSEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>NEGPULSE</name>
+          <description>Autobaud low pulse register</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000FFF</resetValue>
+          <fields>
+            <field>
+              <name>NEGEDGE_MIN_CNT</name>
+              <description>This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CLK_CONF</name>
+          <description>UART core clock configuration</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x03701000</resetValue>
+          <fields>
+            <field>
+              <name>SCLK_DIV_B</name>
+              <description>The  denominator of the frequency divider factor.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_A</name>
+              <description>The numerator of the frequency divider factor.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_DIV_NUM</name>
+              <description>The integral part of the frequency divider factor.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_SEL</name>
+              <description>UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SCLK_EN</name>
+              <description>Set this bit to enable UART Tx/Rx clock.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RST_CORE</name>
+              <description>Write 1 then write 0 to this bit, reset UART Tx/Rx.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_SCLK_EN</name>
+              <description>Set this bit to enable UART Tx clock.</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_SCLK_EN</name>
+              <description>Set this bit to enable UART Rx clock.</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit, reset UART Tx.</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST_CORE</name>
+              <description>Write 1 then write 0 to this bit, reset UART Rx.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UART Version register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02008270</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ID</name>
+          <description>UART ID register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x40000500</resetValue>
+          <fields>
+            <field>
+              <name>ID</name>
+              <description>This register is used to configure the uart_id.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HIGH_SPEED</name>
+              <description>This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REG_UPDATE</name>
+              <description>Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <name>UART1</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <baseAddress>0x60010000</baseAddress>
+      <interrupt>
+        <name>UART1</name>
+        <value>28</value>
+      </interrupt>
+    </peripheral>
+    <peripheral derivedFrom="UART0">
+      <name>UART2</name>
+      <description>UART (Universal Asynchronous Receiver-Transmitter) Controller</description>
+      <baseAddress>0x6002E000</baseAddress>
+      <interrupt>
+        <name>UART2</name>
+        <value>29</value>
+      </interrupt>
+    </peripheral>
+    <peripheral>
+      <name>UHCI0</name>
+      <description>Universal Host Controller Interface</description>
+      <groupName>UHCI</groupName>
+      <baseAddress>0x60014000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x88</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>UHCI0</name>
+        <value>14</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>CONF0</name>
+          <description>UHCI configuration register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000006E0</resetValue>
+          <fields>
+            <field>
+              <name>TX_RST</name>
+              <description>Write 1, then write 0 to this bit to reset decode state machine.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RST</name>
+              <description>Write 1, then write 0 to this bit to reset encode state machine.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART0_CE</name>
+              <description>Set this bit to link up HCI and UART0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART1_CE</name>
+              <description>Set this bit to link up HCI and UART1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART2_CE</name>
+              <description>Set this bit to link up HCI and UART2.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_EN</name>
+              <description>Set this bit to separate the data frame using a special char.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HEAD_EN</name>
+              <description>Set this bit to encode the data packet with a formatting header.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_REC_EN</name>
+              <description>Set this bit to enable UHCI to receive the 16 bit CRC.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_IDLE_EOF_EN</name>
+              <description>If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LEN_EOF_EN</name>
+              <description>If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCODE_CRC_EN</name>
+              <description>Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>UART_RX_BRK_EOF_EN</name>
+              <description>If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw interrupt status</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when a separator char has been sent.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when UHCI detects a separator char.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EOF_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_RAW</name>
+              <description>This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt status</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA  is set to 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA  is set to 1.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA  is set to 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA  is set to 1.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA  is set to 1.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA  is set to 1.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA  is set to 1.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA  is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_ST</name>
+              <description>This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA  is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_RX_START_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_START_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_TX_START_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_ENA</name>
+              <description>This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_START_INT_CLR</name>
+              <description>Set this bit to clear UHCI_RX_START_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_START_INT_CLR</name>
+              <description>Set this bit to clear UHCI_TX_START_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>RX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear UHCI_RX_HUNG_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>TX_HUNG_INT_CLR</name>
+              <description>Set this bit to clear UHCI_TX_HUNG_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_S_REG_Q_INT_CLR</name>
+              <description>Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SEND_A_REG_Q_INT_CLR</name>
+              <description>Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUTLINK_EOF_ERR_INT_CLR</name>
+              <description>Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL0_INT_CLR</name>
+              <description>Set this bit to clear UHCI_APP_CTRL0_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_CLR</name>
+              <description>Set this bit to clear UHCI_APP_CTRL1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>APP_INT_SET</name>
+          <description>Software interrupt trigger source</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>APP_CTRL0_INT_SET</name>
+              <description>This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>APP_CTRL1_INT_SET</name>
+              <description>This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF1</name>
+          <description>UHCI configuration register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>CHECK_SUM_EN</name>
+              <description>This is the enable bit to check header checksum when UHCI receives a data packet.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CHECK_SEQ_EN</name>
+              <description>This is the enable bit to check sequence number when UHCI receives a data packet.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC_DISABLE</name>
+              <description>Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SAVE_HEAD</name>
+              <description>Set this bit to save the packet header when HCI receives a data packet.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_CHECK_SUM_RE</name>
+              <description>Set this bit to encode the data packet with a checksum.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_ACK_NUM_RE</name>
+              <description>Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WAIT_SW_START</name>
+              <description>The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SW_START</name>
+              <description>If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE0</name>
+          <description>UHCI receive status</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_ERR_CAUSE</name>
+              <description>This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in HCI packet. 3'b010: Sequence number error in HCI packet. 3'b011: CRC bit error in HCI packet. 3'b100: 0xc0 is found but received HCI packet is not end. 3'b101: 0xc0 is not found when receiving HCI packet is end. 3'b110: CRC check error.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DECODE_STATE</name>
+              <description>UHCI decoder status.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE1</name>
+          <description>UHCI transmit status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENCODE_STATE</name>
+              <description>UHCI encoder status.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESCAPE_CONF</name>
+          <description>Escape character configuration</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000033</resetValue>
+          <fields>
+            <field>
+              <name>TX_C0_ESC_EN</name>
+              <description>Set this bit to enable decoding char 0xc0 when DMA receives data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DB_ESC_EN</name>
+              <description>Set this bit to enable decoding char 0xdb when DMA receives data.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_11_ESC_EN</name>
+              <description>Set this bit to enable decoding flow control char 0x11 when DMA receives data.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_13_ESC_EN</name>
+              <description>Set this bit to enable decoding flow control char 0x13 when DMA receives data.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_C0_ESC_EN</name>
+              <description>Set this bit to enable replacing 0xc0 by special char when DMA sends data.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_DB_ESC_EN</name>
+              <description>Set this bit to enable replacing 0xdb by special char when DMA sends data.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_11_ESC_EN</name>
+              <description>Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_13_ESC_EN</name>
+              <description>Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HUNG_CONF</name>
+          <description>Timeout configuration</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00810810</resetValue>
+          <fields>
+            <field>
+              <name>TXFIFO_TIMEOUT</name>
+              <description>This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_SHIFT</name>
+              <description>This register is used to configure the tick count maximum value.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFO_TIMEOUT_ENA</name>
+              <description>This is the enable bit for Tx-FIFO receive-data timeout.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT</name>
+              <description>This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_SHIFT</name>
+              <description>This register is used to configure the tick count maximum value.</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFIFO_TIMEOUT_ENA</name>
+              <description>This is the enable bit for DMA send-data timeout.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ACK_NUM</name>
+          <description>UHCI ACK number configuration</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>ACK_NUM</name>
+              <description>This ACK number used in software flow control.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>LOAD</name>
+              <description>Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RX_HEAD</name>
+          <description>UHCI packet header register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RX_HEAD</name>
+              <description>This register stores the header of the current received packet.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>QUICK_SENT</name>
+          <description>UHCI quick send configuration register</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SINGLE_SEND_NUM</name>
+              <description>This register is used to specify the single_send register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SINGLE_SEND_EN</name>
+              <description>Set this bit to enable single_send mode to send short packet.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_NUM</name>
+              <description>This register is used to specify the always_send register.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ALWAYS_SEND_EN</name>
+              <description>Set this bit to enable always_send mode to send short packet.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q0_WORD0</name>
+          <description>Q0_WORD0 quick_sent register</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD0</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q0_WORD1</name>
+          <description>Q0_WORD1 quick_sent register</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q0_WORD1</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q1_WORD0</name>
+          <description>Q1_WORD0 quick_sent register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD0</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q1_WORD1</name>
+          <description>Q1_WORD1 quick_sent register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q1_WORD1</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q2_WORD0</name>
+          <description>Q2_WORD0 quick_sent register</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD0</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q2_WORD1</name>
+          <description>Q2_WORD1 quick_sent register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q2_WORD1</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q3_WORD0</name>
+          <description>Q3_WORD0 quick_sent register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD0</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q3_WORD1</name>
+          <description>Q3_WORD1 quick_sent register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q3_WORD1</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q4_WORD0</name>
+          <description>Q4_WORD0 quick_sent register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD0</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q4_WORD1</name>
+          <description>Q4_WORD1 quick_sent register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q4_WORD1</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q5_WORD0</name>
+          <description>Q5_WORD0 quick_sent register</description>
+          <addressOffset>0x60</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD0</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q5_WORD1</name>
+          <description>Q5_WORD1 quick_sent register</description>
+          <addressOffset>0x64</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q5_WORD1</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q6_WORD0</name>
+          <description>Q6_WORD0 quick_sent register</description>
+          <addressOffset>0x68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD0</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>REG_Q6_WORD1</name>
+          <description>Q6_WORD1 quick_sent register</description>
+          <addressOffset>0x6C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SEND_Q6_WORD1</name>
+              <description>This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF0</name>
+          <description>Escape sequence configuration register 0</description>
+          <addressOffset>0x70</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DCDBC0</resetValue>
+          <fields>
+            <field>
+              <name>SEPER_CHAR</name>
+              <description>This register is used to define the separate char that need to be encoded, default is 0xc0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR0</name>
+              <description>This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SEPER_ESC_CHAR1</name>
+              <description>This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF1</name>
+          <description>Escape sequence configuration register 1</description>
+          <addressOffset>0x74</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DDDBDB</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ0</name>
+              <description>This register is used to define a char that need to be encoded, default is 0xdb that used as the first char of slip escape sequence.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR0</name>
+              <description>This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdb.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ0_CHAR1</name>
+              <description>This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdd.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF2</name>
+          <description>Escape sequence configuration register 2</description>
+          <addressOffset>0x78</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DEDB11</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ1</name>
+              <description>This register is used to define a char that need to be encoded, default is 0x11 that used as flow control char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR0</name>
+              <description>This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xdb.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ1_CHAR1</name>
+              <description>This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xde.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>ESC_CONF3</name>
+          <description>Escape sequence configuration register 3</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00DFDB13</resetValue>
+          <fields>
+            <field>
+              <name>ESC_SEQ2</name>
+              <description>This register is used to define a char that need to be decoded, default is 0x13 that used as flow control char.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR0</name>
+              <description>This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdb.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ESC_SEQ2_CHAR1</name>
+              <description>This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdf.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PKT_THRES</name>
+          <description>Configure register for packet length</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000080</resetValue>
+          <fields>
+            <field>
+              <name>PKT_THRS</name>
+              <description>This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>UHCI version  control register</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02010090</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>This is the version control register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral derivedFrom="UHCI0">
+      <name>UHCI1</name>
+      <description>Universal Host Controller Interface</description>
+      <baseAddress>0x6000C000</baseAddress>
+    </peripheral>
+    <peripheral>
+      <name>USB0</name>
+      <description>USB OTG (On-The-Go)</description>
+      <groupName>USB</groupName>
+      <baseAddress>0x60080000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x2A0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>GOTGCTL</name>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SESREQSCS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SESREQ</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VBVALIDOVEN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VBVALIDOVVAL</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AVALIDOVEN</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AVALIDOVVAL</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BVALIDOVEN</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BVALIDOVVAL</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTNEGSCS</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HNPREQ</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTSETHNPEN</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEVHNPEN</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EHEN</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBNCEFLTRBYPASS</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONIDSTS</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DBNCTIME</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ASESVLD</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BSESVLD</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTGVER</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CURMOD</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GOTGINT</name>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SESENDDET</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SESREQSUCSTSCHNG</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTNEGSUCSTSCHNG</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HSTNEGDET</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ADEVTOUTCHG</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBNCEDONE</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GAHBCFG</name>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GLBLLNTRMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HBSTLEN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMAEN</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NPTXFEMPLVL</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PTXFEMPLVL</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>REMMEMSUPP</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NOTIALLDMAWRIT</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBSINGLE</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INVDESCENDIANESS</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GUSBCFG</name>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00001440</resetValue>
+          <fields>
+            <field>
+              <name>TOUTCAL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHYIF</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ULPI_UTMI_SEL</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FSINTF</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHYSEL</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SRPCAP</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HNPCAP</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBTRDTIM</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TERMSELDLPULSE</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXENDDELAY</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCEHSTMODE</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FORCEDEVMODE</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORRUPTTXPKT</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GRSTCTL</name>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CSFTRST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PIUFSSFTRST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FRMCNTRRST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFFLSH</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFFLSH</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFNUM</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DMAREQ</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>AHBIDLE</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GINTSTS</name>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CURMOD_INT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MODEMIS</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OTGINT</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOF</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFLVI</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NPTXFEMP</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GINNAKEFF</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GOUTNAKEFF</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERLYSUSP</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBSUSP</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBRST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENUMDONE</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ISOOUTDROP</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EOPF</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPMIS</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IEPINT</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OEPINT</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INCOMPISOIN</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCOMPIP</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FETSUSP</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESETDET</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTLNT</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HCHLNT</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PTXFEMP</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CONIDSTSCHNG</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISCONNINT</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SESSREQINT</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WKUPINT</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GINTMSK</name>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>MODEMISMSK</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OTGINTMSK</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOFMSK</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXFLVIMSK</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NPTXFEMPMSK</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GINNAKEFFMSK</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GOUTNACKEFFMSK</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERLYSUSPMSK</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBSUSPMSK</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USBRSTMSK</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENUMDONEMSK</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ISOOUTDROPMSK</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EOPFMSK</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPMISMSK</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IEPINTMSK</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OEPINTMSK</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCOMPISOINMSK</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INCOMPIPMSK</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>FETSUSPMSK</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESETDETMSK</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTLNTMSK</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HCHINTMSK</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PTXFEMPMSK</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CONIDSTSCHNGMSK</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DISCONNINTMSK</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SESSREQINTMSK</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>WKUPINTMSK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GRXSTSR</name>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>G_CHNUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_BCNT</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_DPID</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_PKTSTS</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_FN</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GRXSTSP</name>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CHNUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BCNT</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DPID</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PKTSTS</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FN</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GRXFSIZ</name>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000100</resetValue>
+          <fields>
+            <field>
+              <name>RXFDEP</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GNPTXFSIZ</name>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x01000100</resetValue>
+          <fields>
+            <field>
+              <name>NPTXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NPTXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GNPTXSTS</name>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00040100</resetValue>
+          <fields>
+            <field>
+              <name>NPTXFSPCAVAIL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NPTXQSPCAVAIL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NPTXQTOP</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GSNPSID</name>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x4F54400A</resetValue>
+          <fields>
+            <field>
+              <name>SYNOPSYSID</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GHWCFG1</name>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>EPDIR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GHWCFG2</name>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x224DD930</resetValue>
+          <fields>
+            <field>
+              <name>OTGMODE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTGARCH</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SINGPNT</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSPHYTYPE</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FSPHYTYPE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NUMDEVEPS</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NUMHSTCHNL</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PERIOSUPPORT</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DYNFIFOSIZING</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>MULTIPROCINTRPT</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NPTXQDEPTH</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PTXQDEPTH</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TKNQDEPTH</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTG_ENABLE_IC_USB</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GHWCFG3</name>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x010004B5</resetValue>
+          <fields>
+            <field>
+              <name>XFERSIZEWIDTH</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PKTSIZEWIDTH</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OTGEN</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>I2CINTSEL</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>VNDCTLSUPT</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OPTFEATURE</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RSTTYPE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ADPSUPPORT</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>HSICMODE</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>BCSUPPORT</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>LPMMODE</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DFIFODEPTH</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GHWCFG4</name>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <resetValue>0xD3F0A030</resetValue>
+          <fields>
+            <field>
+              <name>G_NUMDEVPERIOEPS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_PARTIALPWRDN</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_AHBFREQ</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_HIBERNATION</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_EXTENDEDHIBERNATION</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_ACGSUPT</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_ENHANCEDLPMSUPT</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_PHYDATAWIDTH</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_NUMCTLEPS</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_IDDQFLTR</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_VBUSVALIDFLTR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_AVALIDFLTR</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_BVALIDFLTR</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_SESSENDFLTR</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_DEDFIFOMODE</name>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_INEPS</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_DESCDMAENABLED</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>G_DESCDMA</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GDFIFOCFG</name>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>GDFIFOCFG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPINFOBASEADDR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HPTXFSIZ</name>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>PTXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PTXFSIZE</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTXF1</name>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>INEP1TXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEP1TXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTXF2</name>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>INEP2TXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEP2TXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTXF3</name>
+          <addressOffset>0x10C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>INEP3TXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEP3TXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTXF4</name>
+          <addressOffset>0x110</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x10000200</resetValue>
+          <fields>
+            <field>
+              <name>INEP4TXFSTADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEP4TXFDEP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCFG</name>
+          <addressOffset>0x400</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_FSLSPCLKSEL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FSLSSUPP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ENA32KHZS</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESCDMA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRLISTEN</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PERSCHEDENA</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_MODECHTIMEN</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HFIR</name>
+          <addressOffset>0x404</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000017D7</resetValue>
+          <fields>
+            <field>
+              <name>FRINT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>HFIRRLDCTRL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HFNUM</name>
+          <addressOffset>0x408</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00003FFF</resetValue>
+          <fields>
+            <field>
+              <name>FRNUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>FRREM</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HPTXSTS</name>
+          <addressOffset>0x410</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00080100</resetValue>
+          <fields>
+            <field>
+              <name>PTXFSPCAVAIL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PTXQSPCAVAIL</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PTXQTOP</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HAINT</name>
+          <addressOffset>0x414</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HAINT</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HAINTMSK</name>
+          <addressOffset>0x418</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HAINTMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HFLBADDR</name>
+          <addressOffset>0x41C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>HFLBADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HPRT</name>
+          <addressOffset>0x440</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PRTCONNSTS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRTCONNDET</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTENCHNG</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTOVRCURRACT</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRTOVRCURRCHNG</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTRES</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTSUSP</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTRST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTLNSTS</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PRTPWR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTTSTCTL</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PRTSPD</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR0</name>
+          <addressOffset>0x500</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR0</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV0</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE0</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC0</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR0</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM0</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS0</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA0</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT0</name>
+          <addressOffset>0x508</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD0</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL0</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK0</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET0</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR0</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN0</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR0</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR0</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK0</name>
+          <addressOffset>0x50C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK0</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK0</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK0</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK0</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK0</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK0</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK0</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ0</name>
+          <addressOffset>0x510</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT0</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID0</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG0</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA0</name>
+          <addressOffset>0x514</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB0</name>
+          <addressOffset>0x51C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR1</name>
+          <addressOffset>0x520</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS1</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA1</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT1</name>
+          <addressOffset>0x528</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK1</name>
+          <addressOffset>0x52C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK1</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ1</name>
+          <addressOffset>0x530</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG1</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA1</name>
+          <addressOffset>0x534</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB1</name>
+          <addressOffset>0x53C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR2</name>
+          <addressOffset>0x540</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR2</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV2</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC2</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR2</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS2</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA2</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT2</name>
+          <addressOffset>0x548</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD2</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL2</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK2</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK2</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET2</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR2</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR2</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN2</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR2</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR2</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR2</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK2</name>
+          <addressOffset>0x54C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK2</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK2</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK2</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK2</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK2</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK2</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK2</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK2</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK2</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK2</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ2</name>
+          <addressOffset>0x550</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT2</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG2</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA2</name>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB2</name>
+          <addressOffset>0x55C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR3</name>
+          <addressOffset>0x560</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV3</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE3</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC3</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR3</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS3</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA3</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT3</name>
+          <addressOffset>0x568</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD3</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR3</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK3</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK3</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET3</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR3</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR3</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN3</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR3</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR3</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR3</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK3</name>
+          <addressOffset>0x56C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK3</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK3</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK3</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK3</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK3</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK3</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK3</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK3</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK3</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK3</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ3</name>
+          <addressOffset>0x570</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG3</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA3</name>
+          <addressOffset>0x574</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB3</name>
+          <addressOffset>0x57C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR4</name>
+          <addressOffset>0x580</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR4</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV4</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE4</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC4</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR4</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS4</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA4</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT4</name>
+          <addressOffset>0x588</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD4</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR4</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL4</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK4</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET4</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR4</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR4</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN4</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR4</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR4</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR4</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK4</name>
+          <addressOffset>0x58C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK4</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK4</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK4</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK4</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK4</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK4</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK4</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK4</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK4</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK4</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ4</name>
+          <addressOffset>0x590</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT4</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG4</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA4</name>
+          <addressOffset>0x594</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB4</name>
+          <addressOffset>0x59C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR5</name>
+          <addressOffset>0x5A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR5</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV5</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE5</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR5</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS5</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA5</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT5</name>
+          <addressOffset>0x5A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD5</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR5</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL5</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK5</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET5</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR5</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN5</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR5</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR5</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR5</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK5</name>
+          <addressOffset>0x5AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK5</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK5</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK5</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK5</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK5</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK5</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK5</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK5</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK5</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ5</name>
+          <addressOffset>0x5B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT5</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG5</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA5</name>
+          <addressOffset>0x5B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB5</name>
+          <addressOffset>0x5BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR6</name>
+          <addressOffset>0x5C0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR6</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV6</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE6</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC6</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR6</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS6</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA6</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT6</name>
+          <addressOffset>0x5C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD6</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR6</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL6</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK6</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK6</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR6</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR6</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN6</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR6</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR6</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR6</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK6</name>
+          <addressOffset>0x5CC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK6</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK6</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK6</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK6</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK6</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK6</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK6</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK6</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK6</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK6</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ6</name>
+          <addressOffset>0x5D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT6</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG6</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA6</name>
+          <addressOffset>0x5D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB6</name>
+          <addressOffset>0x5DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCCHAR7</name>
+          <addressOffset>0x5E0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_MPS7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPNUM7</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPDIR7</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_LSPDDEV7</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EPTYPE7</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_EC7</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DEVADDR7</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ODDFRM7</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHDIS7</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHENA7</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINT7</name>
+          <addressOffset>0x5E8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPL7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTD7</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERR7</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALL7</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NACK7</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACK7</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYET7</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERR7</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERR7</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUN7</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERR7</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTR7</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XCS_XACT_ERR7</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTR7</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCINTMSK7</name>
+          <addressOffset>0x5EC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERCOMPLMSK7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_CHHLTDMSK7</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_AHBERRMSK7</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_STALLMSK7</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NAKMSK7</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_ACKMSK7</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_NYETMSK7</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_XACTERRMSK7</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BBLERRMSK7</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_FRMOVRUNMSK7</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DATATGLERRMSK7</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_BNAINTRMSK7</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DESC_LST_ROLLINTRMSK7</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCTSIZ7</name>
+          <addressOffset>0x5F0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_XFERSIZE7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>19</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PKTCNT7</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_PID7</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>H_DOPNG7</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMA7</name>
+          <addressOffset>0x5F4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_DMAADDR7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>HCDMAB7</name>
+          <addressOffset>0x5FC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>H_HCDMAB7</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCFG</name>
+          <addressOffset>0x800</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08100000</resetValue>
+          <fields>
+            <field>
+              <name>NZSTSOUTHSHK</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEVADDR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERFRLINT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENDEVOUTNAK</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>XCVRDLY</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ERRATICINTMSK</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPMISCNT</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DESCDMA</name>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PERSCHINTVL</name>
+              <bitOffset>24</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RESVALID</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DCTL</name>
+          <addressOffset>0x804</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00002000</resetValue>
+          <fields>
+            <field>
+              <name>RMTWKUPSIG</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SFTDISCON</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GNPINNAKSTS</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>GOUTNAKSTS</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TSTCTL</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SGNPINNAK</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CGNPINNAK</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SGOUTNAK</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CGOUTNAK</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PWRONPRGDONE</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GMC</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IGNRFRMNUM</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKONBBLE</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ENCOUNTONBNA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DEEPSLEEPBESLREJECT</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DSTS</name>
+          <addressOffset>0x808</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>SUSPSTS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ENUMSPD</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ERRTICERR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOFFN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>14</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DEVLNSTS</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPMSK</name>
+          <addressOffset>0x810</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DI_XFERCOMPLMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_EPDISBLDMSK</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_AHBERMSK</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TIMEOUTMSK</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTKNTXFEMPMSK</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INTKNEPMISMSK</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPNAKEFFMSK</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXFIFOUNDRNMSK</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAININTRMSK</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_NAKMSK</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPMSK</name>
+          <addressOffset>0x814</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPLMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLDMSK</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERMSK</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUPMSK</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDISMSK</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVDMSK</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERRMSK</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAOUTINTRMSK</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERRMSK</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKMSK</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYETMSK</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAINT</name>
+          <addressOffset>0x818</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INEPINT0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>INEPINT6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT0</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT4</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUTEPINT6</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DAINTMSK</name>
+          <addressOffset>0x81C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>INEPMSK0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>INEPMSK6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK0</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK4</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTEPMSK6</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DVBUSDIS</name>
+          <addressOffset>0x828</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000017D7</resetValue>
+          <fields>
+            <field>
+              <name>DVBUSDIS</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DVBUSPULSE</name>
+          <addressOffset>0x82C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x000005B8</resetValue>
+          <fields>
+            <field>
+              <name>DVBUSPULSE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTHRCTL</name>
+          <addressOffset>0x830</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x08020020</resetValue>
+          <fields>
+            <field>
+              <name>NONISOTHREN</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ISOTHREN</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TXTHRLEN</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBTHRRATIO</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXTHREN</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RXTHRLEN</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>ARBPRKEN</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPEMPMSK</name>
+          <addressOffset>0x834</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFEMPMSK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL0</name>
+          <addressOffset>0x900</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP0</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS0</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE0</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL0</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM0</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK0</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK0</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS0</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA0</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT0</name>
+          <addressOffset>0x908</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD0</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT0</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS0</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF0</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP0</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR0</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR0</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT0</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ0</name>
+          <addressOffset>0x910</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT0</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA0</name>
+          <addressOffset>0x914</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS0</name>
+          <addressOffset>0x918</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB0</name>
+          <addressOffset>0x91C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL1</name>
+          <addressOffset>0x920</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM1</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK1</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK1</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID1</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS1</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA1</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT1</name>
+          <addressOffset>0x928</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP1</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ1</name>
+          <addressOffset>0x930</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA1</name>
+          <addressOffset>0x934</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS1</name>
+          <addressOffset>0x938</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB1</name>
+          <addressOffset>0x93C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL2</name>
+          <addressOffset>0x940</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP2</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS2</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL2</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM2</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK2</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK2</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID2</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS2</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA2</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT2</name>
+          <addressOffset>0x948</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD2</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT2</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP2</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS2</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF2</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP2</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN2</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR2</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR2</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT2</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT2</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ2</name>
+          <addressOffset>0x950</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT2</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA2</name>
+          <addressOffset>0x954</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS2</name>
+          <addressOffset>0x958</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB2</name>
+          <addressOffset>0x95C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL3</name>
+          <addressOffset>0x960</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>DI_MPS3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_USBACTEP3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_NAKSTS3</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_EPTYPE3</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_STALL3</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_TXFNUM3</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_CNAK3</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK3</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID3</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_EPDIS3</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_EPENA3</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT3</name>
+          <addressOffset>0x968</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD3</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR3</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP3</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS3</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF3</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP3</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN3</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR3</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR3</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT3</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT3</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ3</name>
+          <addressOffset>0x970</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA3</name>
+          <addressOffset>0x974</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS3</name>
+          <addressOffset>0x978</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB3</name>
+          <addressOffset>0x97C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL4</name>
+          <addressOffset>0x980</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP4</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS4</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE4</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL4</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM4</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK4</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK4</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID4</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS4</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA4</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT4</name>
+          <addressOffset>0x988</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD4</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR4</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT4</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS4</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF4</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP4</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN4</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR4</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR4</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT4</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT4</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ4</name>
+          <addressOffset>0x990</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT4</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA4</name>
+          <addressOffset>0x994</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS4</name>
+          <addressOffset>0x998</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB4</name>
+          <addressOffset>0x99C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL5</name>
+          <addressOffset>0x9A0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>DI_MPS5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_USBACTEP5</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_NAKSTS5</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_EPTYPE5</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>DI_STALL5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_TXFNUM5</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_CNAK5</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK5</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID5</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_EPDIS5</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DI_EPENA5</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT5</name>
+          <addressOffset>0x9A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD5</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR5</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT5</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP5</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF5</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP5</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR5</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR5</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT5</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT5</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ5</name>
+          <addressOffset>0x9B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT5</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA5</name>
+          <addressOffset>0x9B4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS5</name>
+          <addressOffset>0x9B8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB5</name>
+          <addressOffset>0x9BC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPCTL6</name>
+          <addressOffset>0x9C0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>D_MPS6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_USBACTEP6</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_NAKSTS6</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_EPTYPE6</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_STALL6</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFNUM6</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_CNAK6</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SNAK6</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD0PID6</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DI_SETD1PID6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>D_EPDIS6</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPENA6</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPINT6</name>
+          <addressOffset>0x9C8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERCOMPL6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_EPDISBLD6</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_AHBERR6</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TIMEOUT6</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNTXFEMP6</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INTKNEPMIS6</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_INEPNAKEFF6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_TXFEMP6</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>D_TXFIFOUNDRN6</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BNAINTR6</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTDRPSTS6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_BBLEERR6</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NAKINTRPT6</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_NYETINTRPT6</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPTSIZ6</name>
+          <addressOffset>0x9D0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_XFERSIZE6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>D_PKTCNT6</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMA6</name>
+          <addressOffset>0x9D4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMAADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DTXFSTS6</name>
+          <addressOffset>0x9D8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_INEPTXFSPCAVAIL6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DIEPDMAB6</name>
+          <addressOffset>0x9DC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>D_DMABUFFERADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL0</name>
+          <addressOffset>0xB00</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP0</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS0</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE0</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP0</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL0</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK0</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK0</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS0</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA0</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT0</name>
+          <addressOffset>0xB08</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD0</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR0</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP0</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS0</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD0</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP0</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR0</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR0</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS0</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR0</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT0</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT0</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD0</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ0</name>
+          <addressOffset>0xB10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT0</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT0</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA0</name>
+          <addressOffset>0xB14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB0</name>
+          <addressOffset>0xB1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR0</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL1</name>
+          <addressOffset>0xB20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS1</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE1</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP1</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL1</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK1</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK1</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID1</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS1</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA1</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT1</name>
+          <addressOffset>0xB28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD1</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR1</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP1</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS1</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD1</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP1</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR1</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR1</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS1</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR1</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT1</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT1</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD1</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ1</name>
+          <addressOffset>0xB30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT1</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT1</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA1</name>
+          <addressOffset>0xB34</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB1</name>
+          <addressOffset>0xB3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR1</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL2</name>
+          <addressOffset>0xB40</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP2</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS2</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE2</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP2</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL2</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK2</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK2</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID2</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS2</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA2</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT2</name>
+          <addressOffset>0xB48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD2</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR2</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP2</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS2</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD2</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP2</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR2</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR2</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS2</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR2</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT2</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT2</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD2</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ2</name>
+          <addressOffset>0xB50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT2</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT2</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA2</name>
+          <addressOffset>0xB54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB2</name>
+          <addressOffset>0xB5C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR2</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL3</name>
+          <addressOffset>0xB60</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS3</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE3</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP3</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL3</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK3</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK3</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID3</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS3</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA3</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT3</name>
+          <addressOffset>0xB68</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD3</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR3</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP3</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS3</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD3</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP3</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR3</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR3</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS3</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR3</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT3</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT3</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD3</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ3</name>
+          <addressOffset>0xB70</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT3</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT3</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA3</name>
+          <addressOffset>0xB74</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB3</name>
+          <addressOffset>0xB7C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR3</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL4</name>
+          <addressOffset>0xB80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP4</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS4</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE4</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP4</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL4</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK4</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK4</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID4</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS4</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA4</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT4</name>
+          <addressOffset>0xB88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD4</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR4</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP4</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS4</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD4</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP4</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR4</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR4</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS4</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR4</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT4</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT4</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD4</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ4</name>
+          <addressOffset>0xB90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT4</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT4</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA4</name>
+          <addressOffset>0xB94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB4</name>
+          <addressOffset>0xB9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR4</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL5</name>
+          <addressOffset>0xBA0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP5</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS5</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE5</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP5</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL5</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK5</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK5</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID5</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS5</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA5</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT5</name>
+          <addressOffset>0xBA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD5</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR5</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP5</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS5</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD5</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP5</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR5</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR5</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS5</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR5</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT5</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT5</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD5</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ5</name>
+          <addressOffset>0xBB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT5</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT5</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA5</name>
+          <addressOffset>0xBB4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB5</name>
+          <addressOffset>0xBBC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR5</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPCTL6</name>
+          <addressOffset>0xBC0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00008000</resetValue>
+          <fields>
+            <field>
+              <name>MPS6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USBACTEP6</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>NAKSTS6</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPTYPE6</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SNP6</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STALL6</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CNAK6</name>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SNAK6</name>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD0PID6</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>DO_SETD1PID6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>EPDIS6</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>EPENA6</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPINT6</name>
+          <addressOffset>0xBC8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERCOMPL6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EPDISBLD6</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHBERR6</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SETUP6</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTTKNEPDIS6</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STSPHSERCVD6</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BACK2BACKSETUP6</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUTPKTERR6</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BNAINTR6</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTDRPSTS6</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>BBLEERR6</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NAKINTRPT6</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>NYEPINTRPT6</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUPPKTRCVD6</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPTSIZ6</name>
+          <addressOffset>0xBD0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>XFERSIZE6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PKTCNT6</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SUPCNT6</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMA6</name>
+          <addressOffset>0xBD4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMAADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DOEPDMAB6</name>
+          <addressOffset>0xBDC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DMABUFFERADDR6</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PCGCCTL</name>
+          <addressOffset>0xE00</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STOPPCLK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GATEHCLK</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PWRCLMP</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RSTPDWNMODULE</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHYSLEEP</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>L1SUSPENDED</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RESETAFTERSUSP</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>USB_DEVICE</name>
+      <description>Peripheral USB_DEVICE</description>
+      <groupName>USB_DEVICE</groupName>
+      <baseAddress>0x60038000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x50</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <interrupt>
+        <name>USB_DEVICE</name>
+        <value>96</value>
+      </interrupt>
+      <registers>
+        <register>
+          <name>EP1</name>
+          <description>Endpoint 1 FIFO register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RDWR_BYTE</name>
+              <description>Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EP1_CONF</name>
+          <description>Endpoint 1 configure and status register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>WR_DONE</name>
+              <description>Set this bit to indicate writing byte data to UART Tx FIFO is done.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EP_DATA_FREE</name>
+              <description>1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_EP_DATA_AVAIL</name>
+              <description>1'b1: Indicate there is data in UART Rx FIFO.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_RAW</name>
+          <description>Raw status interrupt</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000008</resetValue>
+          <fields>
+            <field>
+              <name>JTAG_IN_FLUSH_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOF_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when SOF frame is received.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_RECV_PKT_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EMPTY_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PID_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when pid error is detected.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRC5_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when CRC5 error is detected.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRC16_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when CRC16 error is detected.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STUFF_ERR_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when stuff error is detected.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_TOKEN_REC_IN_EP1_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_BUS_RESET_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when usb bus reset is detected.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_ZERO_PAYLOAD_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_ZERO_PAYLOAD_INT_RAW</name>
+              <description>The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ST</name>
+          <description>Masked interrupt</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>JTAG_IN_FLUSH_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SOF_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_RECV_PKT_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EMPTY_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>PID_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRC5_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CRC16_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>STUFF_ERR_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_TOKEN_REC_IN_EP1_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>USB_BUS_RESET_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_ZERO_PAYLOAD_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_ZERO_PAYLOAD_INT_ST</name>
+              <description>The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_ENA</name>
+          <description>Interrupt enable bits</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>JTAG_IN_FLUSH_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SOF_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_RECV_PKT_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EMPTY_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PID_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC5_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CRC16_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>STUFF_ERR_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>IN_TOKEN_REC_IN_EP1_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_BUS_RESET_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EP1_ZERO_PAYLOAD_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_EP2_ZERO_PAYLOAD_INT_ENA</name>
+              <description>The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>INT_CLR</name>
+          <description>Interrupt clear bits</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>JTAG_IN_FLUSH_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SOF_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SERIAL_OUT_RECV_PKT_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>SERIAL_IN_EMPTY_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>PID_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC5_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>CRC16_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>STUFF_ERR_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>IN_TOKEN_REC_IN_EP1_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>USB_BUS_RESET_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_ZERO_PAYLOAD_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_ZERO_PAYLOAD_INT_CLR</name>
+              <description>Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>CONF0</name>
+          <description>Configure 0 register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00004200</resetValue>
+          <fields>
+            <field>
+              <name>PHY_SEL</name>
+              <description>Select internal/external PHY</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXCHG_PINS_OVERRIDE</name>
+              <description>Enable software control USB D+ D- exchange</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXCHG_PINS</name>
+              <description>USB D+ D- exchange</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREFH</name>
+              <description>Control single-end input high threshold,1.76V to 2V, step 80mV</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREFL</name>
+              <description>Control single-end input low threshold,0.8V to 1.04V, step 80mV</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREF_OVERRIDE</name>
+              <description>Enable software control input  threshold</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_PULL_OVERRIDE</name>
+              <description>Enable software control USB D+ D- pullup pulldown</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DP_PULLUP</name>
+              <description>Control USB D+ pull up.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DP_PULLDOWN</name>
+              <description>Control USB D+ pull down.</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DM_PULLUP</name>
+              <description>Control USB D- pull up.</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DM_PULLDOWN</name>
+              <description>Control USB D- pull down.</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULLUP_VALUE</name>
+              <description>Control pull up value.</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_ENABLE</name>
+              <description>Enable USB pad function.</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHY_TX_EDGE_SEL</name>
+              <description>0: TX output at clock negedge. 1: Tx output at clock posedge.</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_JTAG_BRIDGE_EN</name>
+              <description>Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEST</name>
+          <description>USB Internal PHY test register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>ENABLE</name>
+              <description>Enable test of the USB pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_OE</name>
+              <description>USB pad oen in test</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DP</name>
+              <description>USB D+ tx value in test</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TX_DM</name>
+              <description>USB D- tx value in test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RX_RCV</name>
+              <description>USB differential rx value in test</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_DP</name>
+              <description>USB D+ rx value in test</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>RX_DM</name>
+              <description>USB D- rx value in test</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>JFIFO_ST</name>
+          <description>USB-JTAG FIFO status</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000044</resetValue>
+          <fields>
+            <field>
+              <name>IN_FIFO_CNT</name>
+              <description>JTAT in fifo counter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_FIFO_EMPTY</name>
+              <description>1: JTAG in fifo is empty.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_FIFO_FULL</name>
+              <description>1: JTAG in fifo is full.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_FIFO_CNT</name>
+              <description>JTAT out fifo counter.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_FIFO_EMPTY</name>
+              <description>1: JTAG out fifo is empty.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_FIFO_FULL</name>
+              <description>1: JTAG out fifo is full.</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_FIFO_RESET</name>
+              <description>Write 1 to reset JTAG in fifo.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>OUT_FIFO_RESET</name>
+              <description>Write 1 to reset JTAG out fifo.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRAM_NUM</name>
+          <description>SOF frame number</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>SOF_FRAME_INDEX</name>
+              <description>Frame index of received SOF frame.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP0_ST</name>
+          <description>IN Endpoint 0 status</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IN_EP0_STATE</name>
+              <description>State of IN Endpoint 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP0_WR_ADDR</name>
+              <description>Write data address of IN endpoint 0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP0_RD_ADDR</name>
+              <description>Read data address of IN endpoint 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP1_ST</name>
+          <description>IN Endpoint 1 status</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IN_EP1_STATE</name>
+              <description>State of IN Endpoint 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP1_WR_ADDR</name>
+              <description>Write data address of IN endpoint 1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP1_RD_ADDR</name>
+              <description>Read data address of IN endpoint 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP2_ST</name>
+          <description>IN Endpoint 2 status</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IN_EP2_STATE</name>
+              <description>State of IN Endpoint 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP2_WR_ADDR</name>
+              <description>Write data address of IN endpoint 2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP2_RD_ADDR</name>
+              <description>Read data address of IN endpoint 2.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IN_EP3_ST</name>
+          <description>IN Endpoint 3 status</description>
+          <addressOffset>0x34</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000001</resetValue>
+          <fields>
+            <field>
+              <name>IN_EP3_STATE</name>
+              <description>State of IN Endpoint 3.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP3_WR_ADDR</name>
+              <description>Write data address of IN endpoint 3.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>IN_EP3_RD_ADDR</name>
+              <description>Read data address of IN endpoint 3.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP0_ST</name>
+          <description>OUT Endpoint 0 status</description>
+          <addressOffset>0x38</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EP0_STATE</name>
+              <description>State of OUT Endpoint 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP0_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP0_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 0.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP1_ST</name>
+          <description>OUT Endpoint 1 status</description>
+          <addressOffset>0x3C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EP1_STATE</name>
+              <description>State of OUT Endpoint 1.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 1.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP1_REC_DATA_CNT</name>
+              <description>Data count in OUT endpoint 1 when one packet is received.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>OUT_EP2_ST</name>
+          <description>OUT Endpoint 2 status</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>OUT_EP2_STATE</name>
+              <description>State of OUT Endpoint 2.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_WR_ADDR</name>
+              <description>Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>OUT_EP2_RD_ADDR</name>
+              <description>Read data address of OUT endpoint 2.</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MISC_CONF</name>
+          <description>MISC register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CLK_EN</name>
+              <description>1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>MEM_CONF</name>
+          <description>Power control</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>USB_MEM_PD</name>
+              <description>1: power down usb memory.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_MEM_CLK_EN</name>
+              <description>1: Force clock on for usb memory.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version control register</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02101200</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>register version.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>USB_WRAP</name>
+      <description>Peripheral USB_WRAP</description>
+      <groupName>USB_WRAP</groupName>
+      <baseAddress>0x60039000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0xC</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>OTG_CONF</name>
+          <description>USB OTG Wrapper Configure Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x001C0000</resetValue>
+          <fields>
+            <field>
+              <name>SRP_SESSEND_OVERRIDE</name>
+              <description>This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SRP_SESSEND_VALUE</name>
+              <description>Software over-ride value of srp session end signal.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHY_SEL</name>
+              <description>Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DFIFO_FORCE_PD</name>
+              <description>Force the dfifo to go into low power mode. The data in dfifo will not lost.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DBNCE_FLTR_BYPASS</name>
+              <description>Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXCHG_PINS_OVERRIDE</name>
+              <description>Enable software controlle USB D+ D- exchange</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>EXCHG_PINS</name>
+              <description>USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREFH</name>
+              <description>Control single-end input high threshold,1.76V to 2V, step 80mV</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREFL</name>
+              <description>Control single-end input low threshold,0.8V to 1.04V, step 80mV</description>
+              <bitOffset>9</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>VREF_OVERRIDE</name>
+              <description>Enable software controlle input  threshold</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PAD_PULL_OVERRIDE</name>
+              <description>Enable software controlle USB D+ D- pullup pulldown</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DP_PULLUP</name>
+              <description>Controlle USB D+ pullup</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DP_PULLDOWN</name>
+              <description>Controlle USB D+ pulldown</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DM_PULLUP</name>
+              <description>Controlle USB D+ pullup</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DM_PULLDOWN</name>
+              <description>Controlle USB D+ pulldown</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PULLUP_VALUE</name>
+              <description>Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K.</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>USB_PAD_ENABLE</name>
+              <description>Enable USB pad function</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>AHB_CLK_FORCE_ON</name>
+              <description>Force ahb clock always on</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHY_CLK_FORCE_ON</name>
+              <description>Force phy clock always on</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PHY_TX_EDGE_SEL</name>
+              <description>Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge.</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>DFIFO_FORCE_PU</name>
+              <description>Disable the dfifo to go into low power mode. The data in dfifo will not lost.</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CLK_EN</name>
+              <description>Disable auto clock gating of CSR registers</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TEST_CONF</name>
+          <description>USB Internal PHY Testing Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TEST_ENABLE</name>
+              <description>Enable test of the USB pad</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TEST_USB_OE</name>
+              <description>USB pad oen in test</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TEST_TX_DP</name>
+              <description>USB D+ tx value in test</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TEST_TX_DM</name>
+              <description>USB D- tx value in test</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>TEST_RX_RCV</name>
+              <description>USB differential rx value in test</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TEST_RX_DP</name>
+              <description>USB D+ rx value in test</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>TEST_RX_DM</name>
+              <description>USB D- rx value in test</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>Version Control Register</description>
+          <addressOffset>0x3FC</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x02102010</resetValue>
+          <fields>
+            <field>
+              <name>USB_WRAP_DATE</name>
+              <description>Date register</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WCL</name>
+      <description>Peripheral WCL</description>
+      <groupName>WCL</groupName>
+      <baseAddress>0x600D0000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x160</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>Core_0_ENTRY_1_ADDR</name>
+          <description>Core_0 Entry 1 address configuration Register</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_1_ADDR</name>
+              <description>Core_0 Entry 1 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_2_ADDR</name>
+          <description>Core_0 Entry 2 address configuration Register</description>
+          <addressOffset>0x4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_2_ADDR</name>
+              <description>Core_0 Entry 2 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_3_ADDR</name>
+          <description>Core_0 Entry 3 address configuration Register</description>
+          <addressOffset>0x8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_3_ADDR</name>
+              <description>Core_0 Entry 3 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_4_ADDR</name>
+          <description>Core_0 Entry 4 address configuration Register</description>
+          <addressOffset>0xC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_4_ADDR</name>
+              <description>Core_0 Entry 4 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_5_ADDR</name>
+          <description>Core_0 Entry 5 address configuration Register</description>
+          <addressOffset>0x10</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_5_ADDR</name>
+              <description>Core_0 Entry 5 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_6_ADDR</name>
+          <description>Core_0 Entry 6 address configuration Register</description>
+          <addressOffset>0x14</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_6_ADDR</name>
+              <description>Core_0 Entry 6 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_7_ADDR</name>
+          <description>Core_0 Entry 7 address configuration Register</description>
+          <addressOffset>0x18</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_7_ADDR</name>
+              <description>Core_0 Entry 7 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_8_ADDR</name>
+          <description>Core_0 Entry 8 address configuration Register</description>
+          <addressOffset>0x1C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_8_ADDR</name>
+              <description>Core_0 Entry 8 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_9_ADDR</name>
+          <description>Core_0 Entry 9 address configuration Register</description>
+          <addressOffset>0x20</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_9_ADDR</name>
+              <description>Core_0 Entry 9 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_10_ADDR</name>
+          <description>Core_0 Entry 10 address configuration Register</description>
+          <addressOffset>0x24</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_10_ADDR</name>
+              <description>Core_0 Entry 10 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_11_ADDR</name>
+          <description>Core_0 Entry 11 address configuration Register</description>
+          <addressOffset>0x28</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_11_ADDR</name>
+              <description>Core_0 Entry 11 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_12_ADDR</name>
+          <description>Core_0 Entry 12 address configuration Register</description>
+          <addressOffset>0x2C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_12_ADDR</name>
+              <description>Core_0 Entry 12 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_13_ADDR</name>
+          <description>Core_0 Entry 13 address configuration Register</description>
+          <addressOffset>0x30</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_13_ADDR</name>
+              <description>Core_0 Entry 13 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_ENTRY_CHECK</name>
+          <description>Core_0 Entry check configuration Register</description>
+          <addressOffset>0x7C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>CORE_0_ENTRY_CHECK</name>
+              <description>This filed is used to enable entry address check</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE1</name>
+          <description>Status register of world switch of entry 1</description>
+          <addressOffset>0x80</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_1</name>
+              <description>This bit is used to confirm world before enter entry 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_1</name>
+              <description>This filed is used to confirm in which entry before enter entry 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_1</name>
+              <description>This bit is used to confirm whether the current state is in entry 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE2</name>
+          <description>Status register of world switch of entry 2</description>
+          <addressOffset>0x84</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_2</name>
+              <description>This bit is used to confirm world before enter entry 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_2</name>
+              <description>This filed is used to confirm in which entry before enter entry 2</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_2</name>
+              <description>This bit is used to confirm whether the current state is in entry 2</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE3</name>
+          <description>Status register of world switch of entry 3</description>
+          <addressOffset>0x88</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_3</name>
+              <description>This bit is used to confirm world before enter entry 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_3</name>
+              <description>This filed is used to confirm in which entry before enter entry 3</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_3</name>
+              <description>This bit is used to confirm whether the current state is in entry 3</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE4</name>
+          <description>Status register of world switch of entry 4</description>
+          <addressOffset>0x8C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_4</name>
+              <description>This bit is used to confirm world before enter entry 4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_4</name>
+              <description>This filed is used to confirm in which entry before enter entry 4</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_4</name>
+              <description>This bit is used to confirm whether the current state is in entry 4</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE5</name>
+          <description>Status register of world switch of entry 5</description>
+          <addressOffset>0x90</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_5</name>
+              <description>This bit is used to confirm world before enter entry 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_5</name>
+              <description>This filed is used to confirm in which entry before enter entry 5</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_5</name>
+              <description>This bit is used to confirm whether the current state is in entry 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE6</name>
+          <description>Status register of world switch of entry 6</description>
+          <addressOffset>0x94</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_6</name>
+              <description>This bit is used to confirm world before enter entry 6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_6</name>
+              <description>This filed is used to confirm in which entry before enter entry 6</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_6</name>
+              <description>This bit is used to confirm whether the current state is in entry 6</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE7</name>
+          <description>Status register of world switch of entry 7</description>
+          <addressOffset>0x98</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_7</name>
+              <description>This bit is used to confirm world before enter entry 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_7</name>
+              <description>This filed is used to confirm in which entry before enter entry 7</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_7</name>
+              <description>This bit is used to confirm whether the current state is in entry 7</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE8</name>
+          <description>Status register of world switch of entry 8</description>
+          <addressOffset>0x9C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_8</name>
+              <description>This bit is used to confirm world before enter entry 8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_8</name>
+              <description>This filed is used to confirm in which entry before enter entry 8</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_8</name>
+              <description>This bit is used to confirm whether the current state is in entry 8</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE9</name>
+          <description>Status register of world switch of entry 9</description>
+          <addressOffset>0xA0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_9</name>
+              <description>This bit is used to confirm world before enter entry 9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_9</name>
+              <description>This filed is used to confirm in which entry before enter entry 9</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_9</name>
+              <description>This bit is used to confirm whether the current state is in entry 9</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE10</name>
+          <description>Status register of world switch of entry 10</description>
+          <addressOffset>0xA4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_10</name>
+              <description>This bit is used to confirm world before enter entry 10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_10</name>
+              <description>This filed is used to confirm in which entry before enter entry 10</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_10</name>
+              <description>This bit is used to confirm whether the current state is in entry 10</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE11</name>
+          <description>Status register of world switch of entry 11</description>
+          <addressOffset>0xA8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_11</name>
+              <description>This bit is used to confirm world before enter entry 11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_11</name>
+              <description>This filed is used to confirm in which entry before enter entry 11</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_11</name>
+              <description>This bit is used to confirm whether the current state is in entry 11</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE12</name>
+          <description>Status register of world switch of entry 12</description>
+          <addressOffset>0xAC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_12</name>
+              <description>This bit is used to confirm world before enter entry 12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_12</name>
+              <description>This filed is used to confirm in which entry before enter entry 12</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_12</name>
+              <description>This bit is used to confirm whether the current state is in entry 12</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE13</name>
+          <description>Status register of world switch of entry 13</description>
+          <addressOffset>0xB0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_FROM_WORLD_13</name>
+              <description>This bit is used to confirm world before enter entry 13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_FROM_ENTRY_13</name>
+              <description>This filed is used to confirm in which entry before enter entry 13</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_0_CURRENT_13</name>
+              <description>This bit is used to confirm whether the current state is in entry 13</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_STATUSTABLE_CURRENT</name>
+          <description>Status register of statustable current</description>
+          <addressOffset>0xFC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_STATUSTABLE_CURRENT</name>
+              <description>This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 represents the current field of STATUSTABLE2</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_MESSAGE_ADDR</name>
+          <description>Clear writer_buffer write address configuration register</description>
+          <addressOffset>0x100</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_MESSAGE_ADDR</name>
+              <description>This field is used to set address that need to write when enter WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_MESSAGE_MAX</name>
+          <description>Clear writer_buffer write number configuration register</description>
+          <addressOffset>0x104</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_MESSAGE_MAX</name>
+              <description>This filed is used to set the max value of clear write_buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_MESSAGE_PHASE</name>
+          <description>Clear writer_buffer status register</description>
+          <addressOffset>0x108</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_MESSAGE_MATCH</name>
+              <description>This bit indicates whether the check is successful</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_MESSAGE_EXPECT</name>
+              <description>This field indicates the data to be written next time</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_MESSAGE_DATAPHASE</name>
+              <description>If this bit is 1, it means that is checking clear write_buffer operation,and is checking data</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_0_MESSAGE_ADDRESSPHASE</name>
+              <description>If this bit is 1, it means that is checking clear write_buffer operation,and is checking address.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_World_TRIGGER_ADDR</name>
+          <description>Core_0 trigger address configuration Register</description>
+          <addressOffset>0x140</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_WORLD_TRIGGER_ADDR</name>
+              <description>This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_World_PREPARE</name>
+          <description>Core_0 prepare world configuration Register</description>
+          <addressOffset>0x144</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_WORLD_PREPARE</name>
+              <description>This field to used to set world to enter,  2'b01 means WORLD0, 2'b10 means WORLD1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_World_UPDATE</name>
+          <description>Core_0 configuration update register</description>
+          <addressOffset>0x148</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_UPDATE</name>
+              <description>This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_World_Cancel</name>
+          <description>Core_0 configuration cancel register</description>
+          <addressOffset>0x14C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_WORLD_CANCEL</name>
+              <description>This field is used to cancel switch world configuration,if the trigger address and update configuration complete,use this register to cancel world switch, jujst need write any value,the hardware only checks the write operation of this register and does not case about its value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_World_IRam0</name>
+          <description>Core_0 Iram0 world register</description>
+          <addressOffset>0x150</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_WORLD_IRAM0</name>
+              <description>this field is used to read current world of Iram0 bus</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_World_DRam0_PIF</name>
+          <description>Core_0 dram0 and PIF world register</description>
+          <addressOffset>0x154</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_WORLD_DRAM0_PIF</name>
+              <description>this field is used to read current world of Dram0 bus and PIF bus</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_World_Phase</name>
+          <description>Core_0 world status register</description>
+          <addressOffset>0x158</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_WORLD_PHASE</name>
+              <description>This bit indicates whether is preparing to switch to WORLD1, 1 means value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_NMI_MASK_ENABLE</name>
+          <description>Core_0 NMI mask enable register</description>
+          <addressOffset>0x180</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_NMI_MASK_ENABLE</name>
+              <description>this field is used to set NMI mask,it can write any value,when write this register,the hardware start masking NMI interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_NMI_MASK_TRIGGER_ADDR</name>
+          <description>Core_0 NMI mask trigger address register</description>
+          <addressOffset>0x184</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_NMI_MASK_TRIGGER_ADDR</name>
+              <description>this field to used to set trigger address, when CPU executes to this address,NMI mask automatically fails</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_NMI_MASK_DISABLE</name>
+          <description>Core_0 NMI mask disable register</description>
+          <addressOffset>0x188</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_NMI_MASK_DISABLE</name>
+              <description>this field is used to disable NMI mask,it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_NMI_MASK_CANCLE</name>
+          <description>Core_0 NMI mask disable register</description>
+          <addressOffset>0x18C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_NMI_MASK_CANCEL</name>
+              <description>this field is used to cancel NMI mask disable function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_NMI_MASK</name>
+          <description>Core_0 NMI mask register</description>
+          <addressOffset>0x190</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_NMI_MASK</name>
+              <description>this bit is used to mask NMI interrupt,it can directly mask NMI interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_0_NMI_MASK_PHASE</name>
+          <description>Core_0 NMI mask phase register</description>
+          <addressOffset>0x194</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_0_NMI_MASK_PHASE</name>
+              <description>this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_1_ADDR</name>
+          <description>Core_1 Entry 1 address configuration Register</description>
+          <addressOffset>0x400</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_1_ADDR</name>
+              <description>Core_1 Entry 1 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_2_ADDR</name>
+          <description>Core_1 Entry 2 address configuration Register</description>
+          <addressOffset>0x404</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_2_ADDR</name>
+              <description>Core_1 Entry 2 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_3_ADDR</name>
+          <description>Core_1 Entry 3 address configuration Register</description>
+          <addressOffset>0x408</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_3_ADDR</name>
+              <description>Core_1 Entry 3 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_4_ADDR</name>
+          <description>Core_1 Entry 4 address configuration Register</description>
+          <addressOffset>0x40C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_4_ADDR</name>
+              <description>Core_1 Entry 4 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_5_ADDR</name>
+          <description>Core_1 Entry 5 address configuration Register</description>
+          <addressOffset>0x410</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_5_ADDR</name>
+              <description>Core_1 Entry 5 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_6_ADDR</name>
+          <description>Core_1 Entry 6 address configuration Register</description>
+          <addressOffset>0x414</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_6_ADDR</name>
+              <description>Core_1 Entry 6 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_7_ADDR</name>
+          <description>Core_1 Entry 7 address configuration Register</description>
+          <addressOffset>0x418</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_7_ADDR</name>
+              <description>Core_1 Entry 7 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_8_ADDR</name>
+          <description>Core_1 Entry 8 address configuration Register</description>
+          <addressOffset>0x41C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_8_ADDR</name>
+              <description>Core_1 Entry 8 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_9_ADDR</name>
+          <description>Core_1 Entry 9 address configuration Register</description>
+          <addressOffset>0x420</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_9_ADDR</name>
+              <description>Core_1 Entry 9 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_10_ADDR</name>
+          <description>Core_1 Entry 10 address configuration Register</description>
+          <addressOffset>0x424</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_10_ADDR</name>
+              <description>Core_1 Entry 10 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_11_ADDR</name>
+          <description>Core_1 Entry 11 address configuration Register</description>
+          <addressOffset>0x428</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_11_ADDR</name>
+              <description>Core_1 Entry 11 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_12_ADDR</name>
+          <description>Core_1 Entry 12 address configuration Register</description>
+          <addressOffset>0x42C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_12_ADDR</name>
+              <description>Core_1 Entry 12 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_13_ADDR</name>
+          <description>Core_1 Entry 13 address configuration Register</description>
+          <addressOffset>0x430</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_13_ADDR</name>
+              <description>Core_1 Entry 13 address from WORLD1 to WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_ENTRY_CHECK</name>
+          <description>Core_1 Entry check configuration Register</description>
+          <addressOffset>0x47C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x00000002</resetValue>
+          <fields>
+            <field>
+              <name>CORE_1_ENTRY_CHECK</name>
+              <description>This filed is used to enable entry address check</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE1</name>
+          <description>Status register of world switch of entry 1</description>
+          <addressOffset>0x480</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_1</name>
+              <description>This bit is used to confirm world before enter entry 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_1</name>
+              <description>This filed is used to confirm in which entry before enter entry 1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_1</name>
+              <description>This bit is used to confirm whether the current state is in entry 1</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE2</name>
+          <description>Status register of world switch of entry 2</description>
+          <addressOffset>0x484</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_2</name>
+              <description>This bit is used to confirm world before enter entry 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_2</name>
+              <description>This filed is used to confirm in which entry before enter entry 2</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_2</name>
+              <description>This bit is used to confirm whether the current state is in entry 2</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE3</name>
+          <description>Status register of world switch of entry 3</description>
+          <addressOffset>0x488</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_3</name>
+              <description>This bit is used to confirm world before enter entry 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_3</name>
+              <description>This filed is used to confirm in which entry before enter entry 3</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_3</name>
+              <description>This bit is used to confirm whether the current state is in entry 3</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE4</name>
+          <description>Status register of world switch of entry 4</description>
+          <addressOffset>0x48C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_4</name>
+              <description>This bit is used to confirm world before enter entry 4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_4</name>
+              <description>This filed is used to confirm in which entry before enter entry 4</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_4</name>
+              <description>This bit is used to confirm whether the current state is in entry 4</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE5</name>
+          <description>Status register of world switch of entry 5</description>
+          <addressOffset>0x490</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_5</name>
+              <description>This bit is used to confirm world before enter entry 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_5</name>
+              <description>This filed is used to confirm in which entry before enter entry 5</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_5</name>
+              <description>This bit is used to confirm whether the current state is in entry 5</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE6</name>
+          <description>Status register of world switch of entry 6</description>
+          <addressOffset>0x494</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_6</name>
+              <description>This bit is used to confirm world before enter entry 6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_6</name>
+              <description>This filed is used to confirm in which entry before enter entry 6</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_6</name>
+              <description>This bit is used to confirm whether the current state is in entry 6</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE7</name>
+          <description>Status register of world switch of entry 7</description>
+          <addressOffset>0x498</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_7</name>
+              <description>This bit is used to confirm world before enter entry 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_7</name>
+              <description>This filed is used to confirm in which entry before enter entry 7</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_7</name>
+              <description>This bit is used to confirm whether the current state is in entry 7</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE8</name>
+          <description>Status register of world switch of entry 8</description>
+          <addressOffset>0x49C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_8</name>
+              <description>This bit is used to confirm world before enter entry 8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_8</name>
+              <description>This filed is used to confirm in which entry before enter entry 8</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_8</name>
+              <description>This bit is used to confirm whether the current state is in entry 8</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE9</name>
+          <description>Status register of world switch of entry 9</description>
+          <addressOffset>0x4A0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_9</name>
+              <description>This bit is used to confirm world before enter entry 9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_9</name>
+              <description>This filed is used to confirm in which entry before enter entry 9</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_9</name>
+              <description>This bit is used to confirm whether the current state is in entry 9</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE10</name>
+          <description>Status register of world switch of entry 10</description>
+          <addressOffset>0x4A4</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_10</name>
+              <description>This bit is used to confirm world before enter entry 10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_10</name>
+              <description>This filed is used to confirm in which entry before enter entry 10</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_10</name>
+              <description>This bit is used to confirm whether the current state is in entry 10</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE11</name>
+          <description>Status register of world switch of entry 11</description>
+          <addressOffset>0x4A8</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_11</name>
+              <description>This bit is used to confirm world before enter entry 11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_11</name>
+              <description>This filed is used to confirm in which entry before enter entry 11</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_11</name>
+              <description>This bit is used to confirm whether the current state is in entry 11</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE12</name>
+          <description>Status register of world switch of entry 12</description>
+          <addressOffset>0x4AC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_12</name>
+              <description>This bit is used to confirm world before enter entry 12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_12</name>
+              <description>This filed is used to confirm in which entry before enter entry 12</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_12</name>
+              <description>This bit is used to confirm whether the current state is in entry 12</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE13</name>
+          <description>Status register of world switch of entry 13</description>
+          <addressOffset>0x4B0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_FROM_WORLD_13</name>
+              <description>This bit is used to confirm world before enter entry 13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_FROM_ENTRY_13</name>
+              <description>This filed is used to confirm in which entry before enter entry 13</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>CORE_1_CURRENT_13</name>
+              <description>This bit is used to confirm whether the current state is in entry 13</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_STATUSTABLE_CURRENT</name>
+          <description>Status register of statustable current</description>
+          <addressOffset>0x4FC</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_STATUSTABLE_CURRENT</name>
+              <description>This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_MESSAGE_ADDR</name>
+          <description>Clear writer_buffer write address configuration register</description>
+          <addressOffset>0x500</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_MESSAGE_ADDR</name>
+              <description>This field is used to set address that need to write when enter WORLD0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_MESSAGE_MAX</name>
+          <description>Clear writer_buffer write number configuration register</description>
+          <addressOffset>0x504</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_MESSAGE_MAX</name>
+              <description>This filed is used to set the max value of clear write_buffer</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_MESSAGE_PHASE</name>
+          <description>Clear writer_buffer status register</description>
+          <addressOffset>0x508</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_MESSAGE_MATCH</name>
+              <description>This bit indicates whether the check is successful</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_MESSAGE_EXPECT</name>
+              <description>This field indicates the data to be written next time</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_MESSAGE_DATAPHASE</name>
+              <description>If this bit is 1, it means that is checking clear write_buffer operation, and is checking data</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>CORE_1_MESSAGE_ADDRESSPHASE</name>
+              <description>If this bit is 1, it means that is checking clear write_buffer operation, and is checking address.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_World_TRIGGER_ADDR</name>
+          <description>Core_1 trigger address configuration Register</description>
+          <addressOffset>0x540</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_WORLD_TRIGGER_ADDR</name>
+              <description>This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_World_PREPARE</name>
+          <description>Core_1 prepare world configuration Register</description>
+          <addressOffset>0x544</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_WORLD_PREPARE</name>
+              <description>This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_World_UPDATE</name>
+          <description>Core_1 configuration update register</description>
+          <addressOffset>0x548</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_UPDATE</name>
+              <description>This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_World_Cancel</name>
+          <description>Core_1 configuration cancel register</description>
+          <addressOffset>0x54C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_WORLD_CANCEL</name>
+              <description>This field is used to cancel switch world configuration,if the trigger address and update configuration complete,can use this register to cancel world switch. can write any value, the hardware only checks the write operation of this register and does not case about its value</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_World_IRam0</name>
+          <description>Core_1 Iram0 world register</description>
+          <addressOffset>0x550</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_WORLD_IRAM0</name>
+              <description>this field is used to read current world of Iram0 bus</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_World_DRam0_PIF</name>
+          <description>Core_1 dram0 and PIF world register</description>
+          <addressOffset>0x554</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_WORLD_DRAM0_PIF</name>
+              <description>this field is used to read current world of Dram0 bus and PIF bus</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_World_Phase</name>
+          <description>Core_0 world status register</description>
+          <addressOffset>0x558</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_WORLD_PHASE</name>
+              <description>This bit indicates whether is preparing to switch to WORLD1,1 means value.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_NMI_MASK_ENABLE</name>
+          <description>Core_1 NMI mask enable register</description>
+          <addressOffset>0x580</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_NMI_MASK_ENABLE</name>
+              <description>this field is used to set NMI mask, it can write any value, when write this register,the hardware start masking NMI interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_NMI_MASK_TRIGGER_ADDR</name>
+          <description>Core_1 NMI mask trigger addr register</description>
+          <addressOffset>0x584</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_NMI_MASK_TRIGGER_ADDR</name>
+              <description>this field to used to set trigger address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_NMI_MASK_DISABLE</name>
+          <description>Core_1 NMI mask disable register</description>
+          <addressOffset>0x588</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_NMI_MASK_DISABLE</name>
+              <description>this field is used to disable NMI mask, it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_NMI_MASK_CANCLE</name>
+          <description>Core_1 NMI mask disable register</description>
+          <addressOffset>0x58C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_NMI_MASK_CANCEL</name>
+              <description>this field is used to cancel NMI mask disable function.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_NMI_MASK</name>
+          <description>Core_1 NMI mask register</description>
+          <addressOffset>0x590</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_NMI_MASK</name>
+              <description>this bit is used to mask NMI interrupt,it can directly mask NMI interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>Core_1_NMI_MASK_PHASE</name>
+          <description>Core_1 NMI mask phase register</description>
+          <addressOffset>0x594</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>CORE_1_NMI_MASK_PHASE</name>
+              <description>this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>XTS_AES</name>
+      <description>XTS-AES-128 Flash Encryption</description>
+      <groupName>XTS_AES</groupName>
+      <baseAddress>0x600CC000</baseAddress>
+      <addressBlock>
+        <offset>0x0</offset>
+        <size>0x60</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <dim>16</dim>
+          <dimIncrement>0x4</dimIncrement>
+          <name>PLAIN_%s</name>
+          <description>Plaintext register %s</description>
+          <addressOffset>0x0</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PLAIN_0</name>
+              <description>Stores the nth 32-bit piece of plaintext.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>LINESIZE</name>
+          <description>XTS-AES line-size register</description>
+          <addressOffset>0x40</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>LINESIZE</name>
+              <description>Configures the data size of one encryption.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESTINATION</name>
+          <description>XTS-AES destination register</description>
+          <addressOffset>0x44</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DESTINATION</name>
+              <description>Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>PHYSICAL_ADDRESS</name>
+          <description>physical address</description>
+          <addressOffset>0x48</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>PHYSICAL_ADDRESS</name>
+              <description>Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TRIGGER</name>
+          <description>XTS-AES trigger register</description>
+          <addressOffset>0x4C</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>TRIGGER</name>
+              <description>Write 1 to activate manual encryption.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RELEASE</name>
+          <description>XTS-AES release control register</description>
+          <addressOffset>0x50</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>RELEASE</name>
+              <description>Write 1 to grant SPI1 access to encrypted result.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DESTROY</name>
+          <description>XTS-AES destroy control register</description>
+          <addressOffset>0x54</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>DESTROY</name>
+              <description>Write 1 to destroy encrypted result.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>STATE</name>
+          <description>XTS-AES status register</description>
+          <addressOffset>0x58</addressOffset>
+          <size>0x20</size>
+          <fields>
+            <field>
+              <name>STATE</name>
+              <description>Those bits indicates the status of the Manual Encryption block. 0X0 (XTS_AES_IDLE): idle. 0X1 (XTS_AES_BUSY): busy with encryption. 0X2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_AVAILABLE) encrypted result is accessible and available to SPI.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DATE</name>
+          <description>XTS-AES version control register</description>
+          <addressOffset>0x5C</addressOffset>
+          <size>0x20</size>
+          <resetValue>0x20200111</resetValue>
+          <fields>
+            <field>
+              <name>DATE</name>
+              <description>Manual Encryption block version information.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>30</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/tools/ide-debug/svd/esp8266.svd b/tools/ide-debug/svd/esp8266.svd
new file mode 100644
index 00000000000..ea9df2d1e24
--- /dev/null
+++ b/tools/ide-debug/svd/esp8266.svd
@@ -0,0 +1,6446 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<device schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1.0.xsd" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+  <name>ESP8266</name>
+  <version>1.0</version>
+  <description>ESP8266</description>
+  <addressUnitBits>8</addressUnitBits>
+  <width>32</width>
+  <cpu>
+    <name>Xtensa LX106</name>
+    <revision>1</revision>
+    <endian>little</endian>
+    <mpuPresent>false</mpuPresent>
+    <fpuPresent>true</fpuPresent>
+    <nvicPrioBits>3</nvicPrioBits>
+    <vendorSystickConfig>false</vendorSystickConfig>
+  </cpu>
+  <peripherals>
+    <peripheral>
+      <name>DPORT</name>
+      <baseAddress>0x3ff00000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>EDGE_INT_ENABLE</name>
+          <addressOffset>0x4</addressOffset>
+          <description>EDGE_INT_ENABLE</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>DPORT_CTL</name>
+          <addressOffset>0x14</addressOffset>
+          <description>DPORT_CTL</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>DPORT_CTL_DOUBLE_CLK</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>EFUSE</name>
+      <baseAddress>0x3ff00050</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000080</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>EFUSE_DATA0</name>
+          <addressOffset>0x0</addressOffset>
+          <description>EFUSE_DATA0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EFUSE_DATA1</name>
+          <addressOffset>0x4</addressOffset>
+          <description>EFUSE_DATA1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EFUSE_DATA2</name>
+          <addressOffset>0x8</addressOffset>
+          <description>EFUSE_DATA2</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>EFUSE_DATA3</name>
+          <addressOffset>0xc</addressOffset>
+          <description>EFUSE_DATA3</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>GPIO</name>
+      <baseAddress>0x60000300</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x000003a0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>GPIO_OUT</name>
+          <addressOffset>0x0</addressOffset>
+          <description>BT-Coexist Selection register</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_BT_SEL</name>
+              <description>BT-Coexist Selection register</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_OUT_DATA</name>
+              <description>The output value when the GPIO pin is set as output.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_OUT_W1TS</name>
+          <addressOffset>0x4</addressOffset>
+          <description>GPIO_OUT_W1TS</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_OUT_DATA_W1TS</name>
+              <description>Writing 1 into a bit in this register will set the related bit in GPIO_OUT_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_OUT_W1TC</name>
+          <addressOffset>0x8</addressOffset>
+          <description>GPIO_OUT_W1TC</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_OUT_DATA_W1TC</name>
+              <description>Writing 1 into a bit in this register will clear the related bit in GPIO_OUT_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_ENABLE</name>
+          <addressOffset>0xc</addressOffset>
+          <description>GPIO_ENABLE</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_SDIO_SEL</name>
+              <description>SDIO-dis selection register</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_ENABLE_DATA</name>
+              <description>The output enable register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_ENABLE_W1TS</name>
+          <addressOffset>0x10</addressOffset>
+          <description>GPIO_ENABLE_W1TS</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_ENABLE_DATA_W1TS</name>
+              <description>Writing 1 into a bit in this register will set the related bit in GPIO_ENABLE_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_ENABLE_W1TC</name>
+          <addressOffset>0x14</addressOffset>
+          <description>GPIO_ENABLE_W1TC</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_ENABLE_DATA_W1TC</name>
+              <description>Writing 1 into a bit in this register will clear the related bit in GPIO_ENABLE_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_IN</name>
+          <addressOffset>0x18</addressOffset>
+          <description>The values of the strapping pins.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_STRAPPING</name>
+              <description>The values of the strapping pins.</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_IN_DATA</name>
+              <description>The values of the GPIO pins when the GPIO pin is set as input.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_STATUS</name>
+          <addressOffset>0x1c</addressOffset>
+          <description>GPIO_STATUS</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_STATUS_INTERRUPT</name>
+              <description>Interrupt enable register.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_STATUS_W1TS</name>
+          <addressOffset>0x20</addressOffset>
+          <description>GPIO_STATUS_W1TS</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_STATUS_INTERRUPT_W1TS</name>
+              <description>Writing 1 into a bit in this register will set the related bit in GPIO_STATUS_INTERRUPT</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_STATUS_W1TC</name>
+          <addressOffset>0x24</addressOffset>
+          <description>GPIO_STATUS_W1TC</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_STATUS_INTERRUPT_W1TC</name>
+              <description>Writing 1 into a bit in this register will clear the related bit in GPIO_STATUS_INTERRUPT</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN0</name>
+          <addressOffset>0x28</addressOffset>
+          <description>GPIO_PIN0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN0_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN0_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN1</name>
+          <addressOffset>0x2c</addressOffset>
+          <description>GPIO_PIN1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN1_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN1_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN2</name>
+          <addressOffset>0x30</addressOffset>
+          <description>GPIO_PIN2</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN2_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN2_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN3</name>
+          <addressOffset>0x34</addressOffset>
+          <description>GPIO_PIN3</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN3_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN3_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN4</name>
+          <addressOffset>0x38</addressOffset>
+          <description>GPIO_PIN4</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN4_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN4_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN5</name>
+          <addressOffset>0x3c</addressOffset>
+          <description>GPIO_PIN5</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN5_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN5_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN6</name>
+          <addressOffset>0x40</addressOffset>
+          <description>GPIO_PIN6</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN6_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN6_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN6_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN6_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN7</name>
+          <addressOffset>0x44</addressOffset>
+          <description>GPIO_PIN7</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN7_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN7_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN7_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN7_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN8</name>
+          <addressOffset>0x48</addressOffset>
+          <description>GPIO_PIN8</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN8_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN8_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN8_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN8_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN9</name>
+          <addressOffset>0x4c</addressOffset>
+          <description>GPIO_PIN9</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN9_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN9_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN9_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN9_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN10</name>
+          <addressOffset>0x50</addressOffset>
+          <description>GPIO_PIN10</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN10_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN10_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN10_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN10_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN11</name>
+          <addressOffset>0x54</addressOffset>
+          <description>GPIO_PIN11</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN11_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN11_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN11_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN11_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN12</name>
+          <addressOffset>0x58</addressOffset>
+          <description>GPIO_PIN12</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN12_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN12_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN12_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN12_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN13</name>
+          <addressOffset>0x5c</addressOffset>
+          <description>GPIO_PIN13</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN13_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN13_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN13_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN13_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN14</name>
+          <addressOffset>0x60</addressOffset>
+          <description>GPIO_PIN14</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN14_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN14_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN14_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN14_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_PIN15</name>
+          <addressOffset>0x64</addressOffset>
+          <description>GPIO_PIN15</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>GPIO_PIN15_WAKEUP_ENABLE</name>
+              <description>0: disable; 1: enable GPIO wakeup CPU, only when GPIO_PIN0_INT_TYPE is 0x4 or 0x5</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN15_INT_TYPE</name>
+              <description>0: disable; 1: positive edge; 2: negative edge; 3: both types of edge; 4: low-level; 5: high-level</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN15_DRIVER</name>
+              <description>1: open drain; 0: normal</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>GPIO_PIN15_SOURCE</name>
+              <description>1: sigma-delta; 0: GPIO_DATA</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_SIGMA_DELTA</name>
+          <addressOffset>0x68</addressOffset>
+          <description>GPIO_SIGMA_DELTA</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SIGMA_DELTA_ENABLE</name>
+              <description>1: enable sigma-delta; 0: disable</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIGMA_DELTA_PRESCALAR</name>
+              <description>Clock pre-divider for sigma-delta.</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SIGMA_DELTA_TARGET</name>
+              <description>target level of the sigma-delta. It is a signed byte.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_RTC_CALIB_SYNC</name>
+          <addressOffset>0x6c</addressOffset>
+          <description>Positvie edge of this bit will trigger the RTC-clock-calibration process.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALIB_START</name>
+              <description>Positvie edge of this bit will trigger the RTC-clock-calibration process.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_PERIOD_NUM</name>
+              <description>The cycle number of RTC-clock during RTC-clock-calibration</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>GPIO_RTC_CALIB_VALUE</name>
+          <addressOffset>0x70</addressOffset>
+          <description>0: during RTC-clock-calibration; 1: RTC-clock-calibration is done</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>RTC_CALIB_RDY</name>
+              <description>0: during RTC-clock-calibration; 1: RTC-clock-calibration is done</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALIB_RDY_REAL</name>
+              <description>0: during RTC-clock-calibration; 1: RTC-clock-calibration is done</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>RTC_CALIB_VALUE</name>
+              <description>The cycle number of clk_xtal (crystal clock) for the RTC_PERIOD_NUM cycles of RTC-clock</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>I2S</name>
+      <baseAddress>0x60000e00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000160</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>I2STXFIFO</name>
+          <addressOffset>0x0</addressOffset>
+          <description>I2STXFIFO</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2SRXFIFO</name>
+          <addressOffset>0x4</addressOffset>
+          <description>I2SRXFIFO</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2SCONF</name>
+          <addressOffset>0x8</addressOffset>
+          <description>I2SCONF</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_BCK_DIV_NUM</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_CLKM_DIV_NUM</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_BITS_MOD</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RECE_MSB_SHIFT</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TRANS_MSB_SHIFT</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_START</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_START</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_MSB_RIGHT</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RIGHT_FIRST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RECE_SLAVE_MOD</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TRANS_SLAVE_MOD</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_FIFO_RESET</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_FIFO_RESET</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_RESET</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_RESET</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2SINT_RAW</name>
+          <addressOffset>0xc</addressOffset>
+          <description>I2SINT_RAW</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_I2S_TX_REMPTY_INT_RAW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_WFULL_INT_RAW</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_REMPTY_INT_RAW</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_WFULL_INT_RAW</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_PUT_DATA_INT_RAW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_TAKE_DATA_INT_RAW</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2SINT_ST</name>
+          <addressOffset>0x10</addressOffset>
+          <description>I2SINT_ST</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_I2S_TX_REMPTY_INT_ST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_WFULL_INT_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_REMPTY_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_WFULL_INT_ST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_PUT_DATA_INT_ST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_TAKE_DATA_INT_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2SINT_ENA</name>
+          <addressOffset>0x14</addressOffset>
+          <description>I2SINT_ENA</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_I2S_TX_REMPTY_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_WFULL_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_REMPTY_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_WFULL_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_PUT_DATA_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_TAKE_DATA_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2SINT_CLR</name>
+          <addressOffset>0x18</addressOffset>
+          <description>I2SINT_CLR</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_I2S_TX_REMPTY_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_WFULL_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_REMPTY_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_WFULL_INT_CLR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_PUT_DATA_INT_CLR</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TAKE_DATA_INT_CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2STIMING</name>
+          <addressOffset>0x1c</addressOffset>
+          <description>I2STIMING</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_TRANS_BCK_IN_INV</name>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RECE_DSYNC_SW</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TRANS_DSYNC_SW</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RECE_BCK_OUT_DELAY</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RECE_WS_OUT_DELAY</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TRANS_SD_OUT_DELAY</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TRANS_WS_OUT_DELAY</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TRANS_BCK_OUT_DELAY</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RECE_SD_IN_DELAY</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RECE_WS_IN_DELAY</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_RECE_BCK_IN_DELAY</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TRANS_WS_IN_DELAY</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_TRANS_BCK_IN_DELAY</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2S_FIFO_CONF</name>
+          <addressOffset>0x20</addressOffset>
+          <description>I2S_FIFO_CONF</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_I2S_RX_FIFO_MOD</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_FIFO_MOD</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_DSCR_EN</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_TX_DATA_NUM</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>I2S_I2S_RX_DATA_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2SRXEOF_NUM</name>
+          <addressOffset>0x24</addressOffset>
+          <description>I2SRXEOF_NUM</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_I2S_RX_EOF_NUM</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>I2SCONF_SIGLE_DATA</name>
+          <addressOffset>0x28</addressOffset>
+          <description>I2SCONF_SIGLE_DATA</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>I2S_I2S_SIGLE_DATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>IO_MUX</name>
+      <baseAddress>0x60000800</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000220</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>IO_MUX_CONF</name>
+          <addressOffset>0x0</addressOffset>
+          <description>IO_MUX_CONF</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SPI0_CLK_EQU_SYS_CLK</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SPI1_CLK_EQU_SYS_CLK</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_MTDI</name>
+          <addressOffset>0x4</addressOffset>
+          <description>IO_MUX_MTDI</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_MTCK</name>
+          <addressOffset>0x8</addressOffset>
+          <description>IO_MUX_MTCK</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_MTMS</name>
+          <addressOffset>0xc</addressOffset>
+          <description>IO_MUX_MTMS</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_MTDO</name>
+          <addressOffset>0x10</addressOffset>
+          <description>IO_MUX_MTDO</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_U0RXD</name>
+          <addressOffset>0x14</addressOffset>
+          <description>IO_MUX_U0RXD</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_U0TXD</name>
+          <addressOffset>0x18</addressOffset>
+          <description>IO_MUX_U0TXD</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_SD_CLK</name>
+          <addressOffset>0x1c</addressOffset>
+          <description>IO_MUX_SD_CLK</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_SD_DATA0</name>
+          <addressOffset>0x20</addressOffset>
+          <description>IO_MUX_SD_DATA0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_SD_DATA1</name>
+          <addressOffset>0x24</addressOffset>
+          <description>IO_MUX_SD_DATA1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_SD_DATA2</name>
+          <addressOffset>0x28</addressOffset>
+          <description>IO_MUX_SD_DATA2</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_SD_DATA3</name>
+          <addressOffset>0x2c</addressOffset>
+          <description>IO_MUX_SD_DATA3</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_SD_CMD</name>
+          <addressOffset>0x30</addressOffset>
+          <description>IO_MUX_SD_CMD</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_GPIO0</name>
+          <addressOffset>0x34</addressOffset>
+          <description>IO_MUX_GPIO0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_GPIO2</name>
+          <addressOffset>0x38</addressOffset>
+          <description>IO_MUX_GPIO2</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_GPIO4</name>
+          <addressOffset>0x3c</addressOffset>
+          <description>IO_MUX_GPIO4</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>IO_MUX_GPIO5</name>
+          <addressOffset>0x40</addressOffset>
+          <description>IO_MUX_GPIO5</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>RTC</name>
+      <baseAddress>0x60000700</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000040</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>RTC_STORE0</name>
+          <addressOffset>0x30</addressOffset>
+          <description>RTC_STORE0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>RTC_STATE1</name>
+          <addressOffset>0x14</addressOffset>
+          <description>RTC_STATE1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SLC</name>
+      <baseAddress>0x60000b00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SLC_CONF0</name>
+          <addressOffset>0x0</addressOffset>
+          <description>SLC_CONF0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_MODE</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_DATA_BURST_EN</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_DSCR_BURST_EN</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_NO_RESTART_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_AUTO_WRBACK</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_LOOP_TEST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_LOOP_TEST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_AHBM_RST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_AHBM_FIFO_RST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RXLINK_RST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TXLINK_RST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_INT_RAW</name>
+          <addressOffset>0x4</addressOffset>
+          <description>SLC_INT_RAW</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TX_DSCR_EMPTY_INT_RAW</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_DSCR_ERR_INT_RAW</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_DSCR_ERR_INT_RAW</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOHOST_INT_RAW</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_EOF_INT_RAW</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_DONE_INT_RAW</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_EOF_INT_RAW</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_DONE_INT_RAW</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN1_1TO0_INT_RAW</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN0_1TO0_INT_RAW</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_OVF_INT_RAW</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_UDF_INT_RAW</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_START_INT_RAW</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_START_INT_RAW</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT7_INT_RAW</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT6_INT_RAW</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT5_INT_RAW</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT4_INT_RAW</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT3_INT_RAW</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT2_INT_RAW</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT1_INT_RAW</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT0_INT_RAW</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_INT_STATUS</name>
+          <addressOffset>0x8</addressOffset>
+          <description>SLC_INT_STATUS</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TX_DSCR_EMPTY_INT_ST</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_DSCR_ERR_INT_ST</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_DSCR_ERR_INT_ST</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOHOST_INT_ST</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_EOF_INT_ST</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_DONE_INT_ST</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_EOF_INT_ST</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_DONE_INT_ST</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN1_1TO0_INT_ST</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN0_1TO0_INT_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_OVF_INT_ST</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_UDF_INT_ST</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_START_INT_ST</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_START_INT_ST</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT7_INT_ST</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT6_INT_ST</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT5_INT_ST</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT4_INT_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT3_INT_ST</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT2_INT_ST</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT1_INT_ST</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT0_INT_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_INT_ENA</name>
+          <addressOffset>0xc</addressOffset>
+          <description>SLC_INT_ENA</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TX_DSCR_EMPTY_INT_ENA</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_DSCR_ERR_INT_ENA</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_DSCR_ERR_INT_ENA</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOHOST_INT_ENA</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_EOF_INT_ENA</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_DONE_INT_ENA</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_EOF_INT_ENA</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_DONE_INT_ENA</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN1_1TO0_INT_ENA</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN0_1TO0_INT_ENA</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_OVF_INT_ENA</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_UDF_INT_ENA</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_START_INT_ENA</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_START_INT_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT7_INT_ENA</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT6_INT_ENA</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT5_INT_ENA</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT4_INT_ENA</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT3_INT_ENA</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT2_INT_ENA</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT1_INT_ENA</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT0_INT_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_INT_CLR</name>
+          <addressOffset>0x10</addressOffset>
+          <description>SLC_INT_CLR</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TX_DSCR_EMPTY_INT_CLR</name>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_DSCR_ERR_INT_CLR</name>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_DSCR_ERR_INT_CLR</name>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOHOST_INT_CLR</name>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_EOF_INT_CLR</name>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_DONE_INT_CLR</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_EOF_INT_CLR</name>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_DONE_INT_CLR</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN1_1TO0_INT_CLR</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN0_1TO0_INT_CLR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_OVF_INT_CLR</name>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_UDF_INT_CLR</name>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_START_INT_CLR</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_START_INT_CLR</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT7_INT_CLR</name>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT6_INT_CLR</name>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT5_INT_CLR</name>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT4_INT_CLR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT3_INT_CLR</name>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT2_INT_CLR</name>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT1_INT_CLR</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FRHOST_BIT0_INT_CLR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_RX_STATUS</name>
+          <addressOffset>0x14</addressOffset>
+          <description>SLC_RX_STATUS</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_RX_EMPTY</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RX_FULL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_RX_FIFO_PUSH</name>
+          <addressOffset>0x18</addressOffset>
+          <description>SLC_RX_FIFO_PUSH</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_RXFIFO_PUSH</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RXFIFO_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_TX_STATUS</name>
+          <addressOffset>0x1c</addressOffset>
+          <description>SLC_TX_STATUS</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TX_EMPTY</name>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_FULL</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_TX_FIFO_POP</name>
+          <addressOffset>0x20</addressOffset>
+          <description>SLC_TX_FIFO_POP</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TXFIFO_POP</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TXFIFO_RDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>11</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_RX_LINK</name>
+          <addressOffset>0x24</addressOffset>
+          <description>SLC_RX_LINK</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_RXLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RXLINK_RESTART</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RXLINK_START</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RXLINK_STOP</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_RXLINK_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_TX_LINK</name>
+          <addressOffset>0x28</addressOffset>
+          <description>SLC_TX_LINK</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TXLINK_PARK</name>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TXLINK_RESTART</name>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TXLINK_START</name>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TXLINK_STOP</name>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TXLINK_ADDR</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_INTVEC_TOHOST</name>
+          <addressOffset>0x2c</addressOffset>
+          <description>SLC_INTVEC_TOHOST</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TOHOST_INTVEC</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_TOKEN0</name>
+          <addressOffset>0x30</addressOffset>
+          <description>SLC_TOKEN0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TOKEN0</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN0_LOCAL_INC_MORE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN0_LOCAL_INC</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN0_LOCAL_WR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN0_LOCAL_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_TOKEN1</name>
+          <addressOffset>0x34</addressOffset>
+          <description>SLC_TOKEN1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TOKEN1</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN1_LOCAL_INC_MORE</name>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN1_LOCAL_INC</name>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN1_LOCAL_WR</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN1_LOCAL_WDATA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>12</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_CONF1</name>
+          <addressOffset>0x38</addressOffset>
+          <description>SLC_CONF1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_STATE0</name>
+          <addressOffset>0x3c</addressOffset>
+          <description>SLC_STATE0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_STATE1</name>
+          <addressOffset>0x40</addressOffset>
+          <description>SLC_STATE1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_BRIDGE_CONF</name>
+          <addressOffset>0x44</addressOffset>
+          <description>SLC_BRIDGE_CONF</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_TX_PUSH_IDLE_NUM</name>
+              <bitOffset>16</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TX_DUMMY_MODE</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FIFO_MAP_ENA</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TXEOF_ENA</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_RX_EOF_DES_ADDR</name>
+          <addressOffset>0x48</addressOffset>
+          <description>SLC_RX_EOF_DES_ADDR</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_TX_EOF_DES_ADDR</name>
+          <addressOffset>0x4c</addressOffset>
+          <description>SLC_TX_EOF_DES_ADDR</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_RX_EOF_BFR_DES_ADDR</name>
+          <addressOffset>0x50</addressOffset>
+          <description>SLC_RX_EOF_BFR_DES_ADDR</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_AHB_TEST</name>
+          <addressOffset>0x54</addressOffset>
+          <description>SLC_AHB_TEST</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_AHB_TESTADDR</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_AHB_TESTMODE</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_SDIO_ST</name>
+          <addressOffset>0x58</addressOffset>
+          <description>SLC_SDIO_ST</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_BUS_ST</name>
+              <bitOffset>12</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_SDIO_WAKEUP</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_FUNC_ST</name>
+              <bitOffset>4</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_CMD_ST</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_RX_DSCR_CONF</name>
+          <addressOffset>0x5c</addressOffset>
+          <description>SLC_RX_DSCR_CONF</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>SLC_INFOR_NO_REPLACE</name>
+              <bitOffset>9</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>SLC_TOKEN_NO_REPLACE</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_TXLINK_DSCR</name>
+          <addressOffset>0x60</addressOffset>
+          <description>SLC_TXLINK_DSCR</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_TXLINK_DSCR_BF0</name>
+          <addressOffset>0x64</addressOffset>
+          <description>SLC_TXLINK_DSCR_BF0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_TXLINK_DSCR_BF1</name>
+          <addressOffset>0x68</addressOffset>
+          <description>SLC_TXLINK_DSCR_BF1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_RXLINK_DSCR</name>
+          <addressOffset>0x6c</addressOffset>
+          <description>SLC_RXLINK_DSCR</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_RXLINK_DSCR_BF0</name>
+          <addressOffset>0x70</addressOffset>
+          <description>SLC_RXLINK_DSCR_BF0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_RXLINK_DSCR_BF1</name>
+          <addressOffset>0x74</addressOffset>
+          <description>SLC_RXLINK_DSCR_BF1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_DATE</name>
+          <addressOffset>0x78</addressOffset>
+          <description>SLC_DATE</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SLC_ID</name>
+          <addressOffset>0x7c</addressOffset>
+          <description>SLC_ID</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI0</name>
+      <baseAddress>0x60000200</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SPI_CMD</name>
+          <addressOffset>0x0</addressOffset>
+          <description>In the master mode, it is the start bit of a single operation. Self-clear by hardware</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_usr</name>
+              <description>In the master mode, it is the start bit of a single operation. Self-clear by hardware</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_ADDR</name>
+          <addressOffset>0x4</addressOffset>
+          <description>In the master mode, it is the value of address in "address"  phase.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>iodata_start_addr</name>
+              <description>In the master mode, it is the value of address in "address"  phase.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CTRL</name>
+          <addressOffset>0x8</addressOffset>
+          <description>SPI_CTRL</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_wr_bit_order</name>
+              <description>In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB first</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_rd_bit_order</name>
+              <description>In "read-data" (MISO) phase, 1: LSB first; 0: MSB first</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_qio_mode</name>
+              <description>In the read operations, "address" phase and "read-data" phase apply 4 signals</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_dio_mode</name>
+              <description>In the read operations, "address" phase and "read-data" phase apply 2 signals</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_qout_mode</name>
+              <description>In the read operations, "read-data" phase apply 4 signals</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_dout_mode</name>
+              <description>In the read operations, "read-data" phase apply 2 signals</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fastrd_mode</name>
+              <description>this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_RD_STATUS</name>
+          <addressOffset>0x10</addressOffset>
+          <description>In the slave mode, this register are the status register for the master to read out.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_rd_status</name>
+              <description>In the slave mode, this register are the status register for the master to read out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CTRL2</name>
+          <addressOffset>0x14</addressOffset>
+          <description>spi_cs signal is delayed by 80MHz clock cycles</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_cs_delay_num</name>
+              <description>spi_cs signal is delayed by 80MHz clock cycles</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_cs_delay_mode</name>
+              <description>spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_mosi_delay_num</name>
+              <description>MOSI signals are delayed by 80MHz clock cycles</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_mosi_delay_mode</name>
+              <description>MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_miso_delay_num</name>
+              <description>MISO signals are delayed by 80MHz clock cycles</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_miso_delay_mode</name>
+              <description>MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CLOCK</name>
+          <addressOffset>0x18</addressOffset>
+          <description>In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_clk_equ_sysclk</name>
+              <description>In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_clkdiv_pre</name>
+              <description>In the master mode, it is pre-divider of spi_clk.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_clkcnt_N</name>
+              <description>In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_clkcnt_H</name>
+              <description>In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_clkcnt_L</name>
+              <description>In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER</name>
+          <addressOffset>0x1c</addressOffset>
+          <description>This bit enable the "command" phase of an operation.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_usr_command</name>
+              <description>This bit enable the "command" phase of an operation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_usr_addr</name>
+              <description>This bit enable the "address" phase of an operation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_usr_dummy</name>
+              <description>This bit enable the "dummy" phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_usr_miso</name>
+              <description>This bit enable the "read-data" phase of an operation.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_usr_mosi</name>
+              <description>This bit enable the "write-data" phase of an operation.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_mosi_highpart</name>
+              <description>1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_miso_highpart</name>
+              <description>1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_sio</name>
+              <description>1: mosi and miso signals share the same pin</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fwrite_qio</name>
+              <description>In the write operations, "address" phase and "read-data" phase apply 4 signals</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fwrite_dio</name>
+              <description>In the write operations, "address" phase and "read-data" phase apply 2 signals</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fwrite_quad</name>
+              <description>In the write operations, "read-data" phase apply 4 signals</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fwrite_dual</name>
+              <description>In the write operations, "read-data" phase apply 2 signals</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_wr_byte_order</name>
+              <description>In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: big_endian</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_rd_byte_order</name>
+              <description>In "read-data" (MISO) phase, 1: little-endian; 0: big_endian</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_ck_i_edge</name>
+              <description>In the slave mode, 1: rising-edge; 0: falling-edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER1</name>
+          <addressOffset>0x20</addressOffset>
+          <description>The length in bits of "address" phase. The register value shall be (bit_num-1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>reg_usr_addr_bitlen</name>
+              <description>The length in bits of "address" phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_mosi_bitlen</name>
+              <description>The length in bits of "write-data" phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_miso_bitlen</name>
+              <description>The length in bits of "read-data" phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_dummy_cyclelen</name>
+              <description>The length in spi_clk cycles of "dummy" phase. The register value shall be (cycle_num-1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER2</name>
+          <addressOffset>0x24</addressOffset>
+          <description>The length in bits of "command" phase. The register value shall be (bit_num-1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>reg_usr_command_bitlen</name>
+              <description>The length in bits of "command" phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_command_value</name>
+              <description>The value of "command" phase</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_WR_STATUS</name>
+          <addressOffset>0x28</addressOffset>
+          <description>In the slave mode, this register are the status register for the master to write into.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_wr_status</name>
+              <description>In the slave mode, this register are the status register for the master to write into.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_PIN</name>
+          <addressOffset>0x2c</addressOffset>
+          <description>1: disable CS2; 0: spi_cs signal is from/to CS2 pin</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_cs2_dis</name>
+              <description>1: disable CS2; 0: spi_cs signal is from/to CS2 pin</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_cs1_dis</name>
+              <description>1: disable CS1; 0: spi_cs signal is from/to CS1 pin</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_cs0_dis</name>
+              <description>1: disable CS0; 0: spi_cs signal is from/to CS0 pin</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE</name>
+          <addressOffset>0x30</addressOffset>
+          <description>It is the synchronous reset signal of the module. This bit is self-cleared by hardware.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_sync_reset</name>
+              <description>It is the synchronous reset signal of the module. This bit is self-cleared by hardware.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_slave_mode</name>
+              <description>1: slave mode, 0: master mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_cmd_define</name>
+              <description>1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer".</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_trans_cnt</name>
+              <description>The operations counter in both the master mode and the slave mode.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>spi_int_en</name>
+              <description>Interrupt enable bits for the below 5 sources</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_trans_done</name>
+              <description>The interrupt raw bit for the completement of any operation in both the master mode and the slave mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wr_sta_done</name>
+              <description>The interrupt raw bit for the completement of "write-status" operation in the slave mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rd_sta_done</name>
+              <description>The interrupt raw bit for the completement of "read-status" operation in the slave mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wr_buf_done</name>
+              <description>The interrupt raw bit for the completement of "write-buffer" operation in the slave mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rd_buf_done</name>
+              <description>The interrupt raw bit for the completement of "read-buffer" operation in the slave mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE1</name>
+          <addressOffset>0x34</addressOffset>
+          <description>In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_status_bitlen</name>
+              <description>In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_buf_bitlen</name>
+              <description>In the slave mode, it is the length in bits for "write-buffer" and "read-buffer" operations. The register value shallbe (bit_num-1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rd_addr_bitlen</name>
+              <description>In the slave mode, it is the address length in bits for "read-buffer" operation. The register value shall be(bit_num-1)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wr_addr_bitlen</name>
+              <description>In the slave mode, it is the address length in bits for "write-buffer" operation. The register value shall be(bit_num-1)</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wrsta_dummy_en</name>
+              <description>In the slave mode, it is the enable bit of "dummy" phase for "write-status" operations.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdsta_dummy_en</name>
+              <description>In the slave mode, it is the enable bit of "dummy" phase for "read-status" operations.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wrbuf_dummy_en</name>
+              <description>In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdbuf_dummy_en</name>
+              <description>In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE2</name>
+          <addressOffset>0x38</addressOffset>
+          <description>In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_wrbuf_dummy_cyclelen</name>
+              <description>In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdbuf_dummy_cyclelen</name>
+              <description>In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-buffer" operations. The registervalue shall be (cycle_num-1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wrsta_dummy_cyclelen</name>
+              <description>In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "write-status" operations. Theregister value shall be (cycle_num-1)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdsta_dummy_cyclelen</name>
+              <description>In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-status" operations. Theregister value shall be (cycle_num-1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE3</name>
+          <addressOffset>0x3c</addressOffset>
+          <description>In slave mode, it is the value of "write-status" command</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_wrsta_cmd_value</name>
+              <description>In slave mode, it is the value of "write-status" command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdsta_cmd_value</name>
+              <description>In slave mode, it is the value of "read-status" command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wrbuf_cmd_value</name>
+              <description>In slave mode, it is the value of "write-buffer" command</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdbuf_cmd_value</name>
+              <description>In slave mode, it is the value of "read-buffer" command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_EXT3</name>
+          <addressOffset>0xfc</addressOffset>
+          <description>This register is for two SPI masters to share the same cs, clock and data signals.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>reg_int_hold_ena</name>
+              <description>This register is for two SPI masters to share the same cs, clock and data signals.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W0</name>
+          <addressOffset>0x40</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w0</name>
+              <description>the data inside the buffer of the SPI module, word 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W1</name>
+          <addressOffset>0x44</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w1</name>
+              <description>the data inside the buffer of the SPI module, word 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W2</name>
+          <addressOffset>0x48</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 2</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w2</name>
+              <description>the data inside the buffer of the SPI module, word 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W3</name>
+          <addressOffset>0x4c</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 3</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w3</name>
+              <description>the data inside the buffer of the SPI module, word 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W4</name>
+          <addressOffset>0x50</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 4</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w4</name>
+              <description>the data inside the buffer of the SPI module, word 4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W5</name>
+          <addressOffset>0x54</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 5</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w5</name>
+              <description>the data inside the buffer of the SPI module, word 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W6</name>
+          <addressOffset>0x58</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 6</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w6</name>
+              <description>the data inside the buffer of the SPI module, word 6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W7</name>
+          <addressOffset>0x5c</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 7</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w7</name>
+              <description>the data inside the buffer of the SPI module, word 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W8</name>
+          <addressOffset>0x60</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 8</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w8</name>
+              <description>the data inside the buffer of the SPI module, word 8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W9</name>
+          <addressOffset>0x64</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 9</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w9</name>
+              <description>the data inside the buffer of the SPI module, word 9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W10</name>
+          <addressOffset>0x68</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 10</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w10</name>
+              <description>the data inside the buffer of the SPI module, word 10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W11</name>
+          <addressOffset>0x6c</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 11</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w11</name>
+              <description>the data inside the buffer of the SPI module, word 11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W12</name>
+          <addressOffset>0x70</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 12</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w12</name>
+              <description>the data inside the buffer of the SPI module, word 12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W13</name>
+          <addressOffset>0x74</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 13</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w13</name>
+              <description>the data inside the buffer of the SPI module, word 13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W14</name>
+          <addressOffset>0x78</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 14</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w14</name>
+              <description>the data inside the buffer of the SPI module, word 14</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W15</name>
+          <addressOffset>0x7c</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 15</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w15</name>
+              <description>the data inside the buffer of the SPI module, word 15</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>SPI1</name>
+      <baseAddress>0x60000100</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000400</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>SPI_CMD</name>
+          <addressOffset>0x0</addressOffset>
+          <description>In the master mode, it is the start bit of a single operation. Self-clear by hardware</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_usr</name>
+              <description>In the master mode, it is the start bit of a single operation. Self-clear by hardware</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_ADDR</name>
+          <addressOffset>0x4</addressOffset>
+          <description>In the master mode, it is the value of address in "address"  phase.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>iodata_start_addr</name>
+              <description>In the master mode, it is the value of address in "address"  phase.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CTRL</name>
+          <addressOffset>0x8</addressOffset>
+          <description>SPI_CTRL</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_wr_bit_order</name>
+              <description>In "command", "address", "write-data" (MOSI) phases, 1: LSB first; 0: MSB first</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_rd_bit_order</name>
+              <description>In "read-data" (MISO) phase, 1: LSB first; 0: MSB first</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_qio_mode</name>
+              <description>In the read operations, "address" phase and "read-data" phase apply 4 signals</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_dio_mode</name>
+              <description>In the read operations, "address" phase and "read-data" phase apply 2 signals</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_qout_mode</name>
+              <description>In the read operations, "read-data" phase apply 4 signals</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_dout_mode</name>
+              <description>In the read operations, "read-data" phase apply 2 signals</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fastrd_mode</name>
+              <description>this bit enable the bits: spi_qio_mode, spi_dio_mode, spi_qout_mode and spi_dout_mode</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_RD_STATUS</name>
+          <addressOffset>0x10</addressOffset>
+          <description>In the slave mode, this register are the status register for the master to read out.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_rd_status</name>
+              <description>In the slave mode, this register are the status register for the master to read out.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CTRL2</name>
+          <addressOffset>0x14</addressOffset>
+          <description>spi_cs signal is delayed by 80MHz clock cycles</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_cs_delay_num</name>
+              <description>spi_cs signal is delayed by 80MHz clock cycles</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_cs_delay_mode</name>
+              <description>spi_cs signal is delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_mosi_delay_num</name>
+              <description>MOSI signals are delayed by 80MHz clock cycles</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_mosi_delay_mode</name>
+              <description>MOSI signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_miso_delay_num</name>
+              <description>MISO signals are delayed by 80MHz clock cycles</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>3</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_miso_delay_mode</name>
+              <description>MISO signals are delayed by spi_clk. 0: zero; 1: half cycle; 2: one cycle</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_CLOCK</name>
+          <addressOffset>0x18</addressOffset>
+          <description>In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_clk_equ_sysclk</name>
+              <description>In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_clkdiv_pre</name>
+              <description>In the master mode, it is pre-divider of spi_clk.</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>13</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_clkcnt_N</name>
+              <description>In the master mode, it is the divider of spi_clk. So spi_clk frequency is 80MHz/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_clkcnt_H</name>
+              <description>In the master mode, it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode, it must be 0.</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_clkcnt_L</name>
+              <description>In the master mode, it must be eqaul to spi_clkcnt_N. In the slave mode, it must be 0.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER</name>
+          <addressOffset>0x1c</addressOffset>
+          <description>This bit enable the "command" phase of an operation.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_usr_command</name>
+              <description>This bit enable the "command" phase of an operation.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_usr_addr</name>
+              <description>This bit enable the "address" phase of an operation.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_usr_dummy</name>
+              <description>This bit enable the "dummy" phase of an operation.</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_usr_miso</name>
+              <description>This bit enable the "read-data" phase of an operation.</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_usr_mosi</name>
+              <description>This bit enable the "write-data" phase of an operation.</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_mosi_highpart</name>
+              <description>1: "write-data" phase only access to high-part of the buffer spi_w8~spi_w15</description>
+              <bitOffset>25</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_miso_highpart</name>
+              <description>1: "read-data" phase only access to high-part of the buffer spi_w8~spi_w15</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_sio</name>
+              <description>1: mosi and miso signals share the same pin</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fwrite_qio</name>
+              <description>In the write operations, "address" phase and "read-data" phase apply 4 signals</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fwrite_dio</name>
+              <description>In the write operations, "address" phase and "read-data" phase apply 2 signals</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fwrite_quad</name>
+              <description>In the write operations, "read-data" phase apply 4 signals</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_fwrite_dual</name>
+              <description>In the write operations, "read-data" phase apply 2 signals</description>
+              <bitOffset>12</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_wr_byte_order</name>
+              <description>In "command", "address", "write-data" (MOSI) phases, 1: little-endian; 0: big_endian</description>
+              <bitOffset>11</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_rd_byte_order</name>
+              <description>In "read-data" (MISO) phase, 1: little-endian; 0: big_endian</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_ck_i_edge</name>
+              <description>In the slave mode, 1: rising-edge; 0: falling-edge</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER1</name>
+          <addressOffset>0x20</addressOffset>
+          <description>The length in bits of "address" phase. The register value shall be (bit_num-1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>reg_usr_addr_bitlen</name>
+              <description>The length in bits of "address" phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>26</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_mosi_bitlen</name>
+              <description>The length in bits of "write-data" phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_miso_bitlen</name>
+              <description>The length in bits of "read-data" phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_dummy_cyclelen</name>
+              <description>The length in spi_clk cycles of "dummy" phase. The register value shall be (cycle_num-1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_USER2</name>
+          <addressOffset>0x24</addressOffset>
+          <description>The length in bits of "command" phase. The register value shall be (bit_num-1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>reg_usr_command_bitlen</name>
+              <description>The length in bits of "command" phase. The register value shall be (bit_num-1)</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>reg_usr_command_value</name>
+              <description>The value of "command" phase</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>16</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_WR_STATUS</name>
+          <addressOffset>0x28</addressOffset>
+          <description>In the slave mode, this register are the status register for the master to write into.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_wr_status</name>
+              <description>In the slave mode, this register are the status register for the master to write into.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_PIN</name>
+          <addressOffset>0x2c</addressOffset>
+          <description>1: disable CS2; 0: spi_cs signal is from/to CS2 pin</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_cs2_dis</name>
+              <description>1: disable CS2; 0: spi_cs signal is from/to CS2 pin</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_cs1_dis</name>
+              <description>1: disable CS1; 0: spi_cs signal is from/to CS1 pin</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_cs0_dis</name>
+              <description>1: disable CS0; 0: spi_cs signal is from/to CS0 pin</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE</name>
+          <addressOffset>0x30</addressOffset>
+          <description>It is the synchronous reset signal of the module. This bit is self-cleared by hardware.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_sync_reset</name>
+              <description>It is the synchronous reset signal of the module. This bit is self-cleared by hardware.</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_slave_mode</name>
+              <description>1: slave mode, 0: master mode.</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_cmd_define</name>
+              <description>1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as 1: "write-status"; 4: "read-status"; 2: "write-buffer" and 3: "read-buffer".</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_trans_cnt</name>
+              <description>The operations counter in both the master mode and the slave mode.</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>4</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>spi_int_en</name>
+              <description>Interrupt enable bits for the below 5 sources</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>spi_trans_done</name>
+              <description>The interrupt raw bit for the completement of any operation in both the master mode and the slave mode.</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wr_sta_done</name>
+              <description>The interrupt raw bit for the completement of "write-status" operation in the slave mode.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rd_sta_done</name>
+              <description>The interrupt raw bit for the completement of "read-status" operation in the slave mode.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wr_buf_done</name>
+              <description>The interrupt raw bit for the completement of "write-buffer" operation in the slave mode.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rd_buf_done</name>
+              <description>The interrupt raw bit for the completement of "read-buffer" operation in the slave mode.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE1</name>
+          <addressOffset>0x34</addressOffset>
+          <description>In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_status_bitlen</name>
+              <description>In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)</description>
+              <bitOffset>27</bitOffset>
+              <bitWidth>5</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_buf_bitlen</name>
+              <description>In the slave mode, it is the length in bits for "write-buffer" and "read-buffer" operations. The register value shallbe (bit_num-1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>9</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rd_addr_bitlen</name>
+              <description>In the slave mode, it is the address length in bits for "read-buffer" operation. The register value shall be(bit_num-1)</description>
+              <bitOffset>10</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wr_addr_bitlen</name>
+              <description>In the slave mode, it is the address length in bits for "write-buffer" operation. The register value shall be(bit_num-1)</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>6</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wrsta_dummy_en</name>
+              <description>In the slave mode, it is the enable bit of "dummy" phase for "write-status" operations.</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdsta_dummy_en</name>
+              <description>In the slave mode, it is the enable bit of "dummy" phase for "read-status" operations.</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wrbuf_dummy_en</name>
+              <description>In the slave mode, it is the enable bit of "dummy" phase for "write-buffer" operations.</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdbuf_dummy_en</name>
+              <description>In the slave mode, it is the enable bit of "dummy" phase for "read-buffer" operations.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE2</name>
+          <addressOffset>0x38</addressOffset>
+          <description>In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_wrbuf_dummy_cyclelen</name>
+              <description>In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdbuf_dummy_cyclelen</name>
+              <description>In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-buffer" operations. The registervalue shall be (cycle_num-1)</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wrsta_dummy_cyclelen</name>
+              <description>In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "write-status" operations. Theregister value shall be (cycle_num-1)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdsta_dummy_cyclelen</name>
+              <description>In the slave mode, it is the length in spi_clk cycles of "dummy" phase for "read-status" operations. Theregister value shall be (cycle_num-1)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_SLAVE3</name>
+          <addressOffset>0x3c</addressOffset>
+          <description>In slave mode, it is the value of "write-status" command</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>slv_wrsta_cmd_value</name>
+              <description>In slave mode, it is the value of "write-status" command</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdsta_cmd_value</name>
+              <description>In slave mode, it is the value of "read-status" command</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_wrbuf_cmd_value</name>
+              <description>In slave mode, it is the value of "write-buffer" command</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>slv_rdbuf_cmd_value</name>
+              <description>In slave mode, it is the value of "read-buffer" command</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_EXT3</name>
+          <addressOffset>0xfc</addressOffset>
+          <description>This register is for two SPI masters to share the same cs, clock and data signals.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>reg_int_hold_ena</name>
+              <description>This register is for two SPI masters to share the same cs, clock and data signals.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W0</name>
+          <addressOffset>0x40</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 0</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w0</name>
+              <description>the data inside the buffer of the SPI module, word 0</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W1</name>
+          <addressOffset>0x44</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 1</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w1</name>
+              <description>the data inside the buffer of the SPI module, word 1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W2</name>
+          <addressOffset>0x48</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 2</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w2</name>
+              <description>the data inside the buffer of the SPI module, word 2</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W3</name>
+          <addressOffset>0x4c</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 3</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w3</name>
+              <description>the data inside the buffer of the SPI module, word 3</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W4</name>
+          <addressOffset>0x50</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 4</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w4</name>
+              <description>the data inside the buffer of the SPI module, word 4</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W5</name>
+          <addressOffset>0x54</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 5</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w5</name>
+              <description>the data inside the buffer of the SPI module, word 5</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W6</name>
+          <addressOffset>0x58</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 6</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w6</name>
+              <description>the data inside the buffer of the SPI module, word 6</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W7</name>
+          <addressOffset>0x5c</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 7</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w7</name>
+              <description>the data inside the buffer of the SPI module, word 7</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W8</name>
+          <addressOffset>0x60</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 8</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w8</name>
+              <description>the data inside the buffer of the SPI module, word 8</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W9</name>
+          <addressOffset>0x64</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 9</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w9</name>
+              <description>the data inside the buffer of the SPI module, word 9</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W10</name>
+          <addressOffset>0x68</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 10</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w10</name>
+              <description>the data inside the buffer of the SPI module, word 10</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W11</name>
+          <addressOffset>0x6c</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 11</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w11</name>
+              <description>the data inside the buffer of the SPI module, word 11</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W12</name>
+          <addressOffset>0x70</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 12</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w12</name>
+              <description>the data inside the buffer of the SPI module, word 12</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W13</name>
+          <addressOffset>0x74</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 13</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w13</name>
+              <description>the data inside the buffer of the SPI module, word 13</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W14</name>
+          <addressOffset>0x78</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 14</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w14</name>
+              <description>the data inside the buffer of the SPI module, word 14</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>SPI_W15</name>
+          <addressOffset>0x7c</addressOffset>
+          <description>the data inside the buffer of the SPI module, word 15</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>spi_w15</name>
+              <description>the data inside the buffer of the SPI module, word 15</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>TIMER</name>
+      <baseAddress>0x60000600</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000120</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>FRC1_LOAD</name>
+          <addressOffset>0x0</addressOffset>
+          <description>the load value into the counter</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>frc1_load_value</name>
+              <description>the load value into the counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRC1_COUNT</name>
+          <addressOffset>0x4</addressOffset>
+          <description>the current value of the counter. It is a decreasingcounter.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>frc1_count</name>
+              <description>the current value of the counter. It is a decreasingcounter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>23</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRC1_CTRL</name>
+          <addressOffset>0x8</addressOffset>
+          <description>FRC1_CTRL</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>frc1_int</name>
+              <description>the status of the interrupt, when the count isdereased to zero</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>frc1_ctrl</name>
+              <description>bit[7]: timer enable, bit[6]: automatically reload, when the counter  isequal to zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit[0]: interrupt type, 0:edge, 1:level</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRC1_INT</name>
+          <addressOffset>0xc</addressOffset>
+          <description>FRC1_INT</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>frc1_int_clr_mask</name>
+              <description>write to clear the status of the interrupt, if theinterrupt type is "level"</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRC2_LOAD</name>
+          <addressOffset>0x20</addressOffset>
+          <description>the load value into the counter</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>frc2_load_value</name>
+              <description>the load value into the counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRC2_COUNT</name>
+          <addressOffset>0x24</addressOffset>
+          <description>the current value of the counter. It is a increasingcounter.</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>frc2_count</name>
+              <description>the current value of the counter. It is a increasingcounter.</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRC2_CTRL</name>
+          <addressOffset>0x28</addressOffset>
+          <description>FRC2_CTRL</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>frc2_int</name>
+              <description>the status of the interrupt, when the count is equal tothe alarm value</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>frc2_ctrl</name>
+              <description>bit[7]: timer enable, bit[6]: automatically reload, when the counter  isequal to zero, bit[3:2]: prescale-divider, 0: divided by 1, 1: dividedby 16, 2 or 3: divided by 256, bit[0]: interrupt type, 0:edge, 1:level</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRC2_INT</name>
+          <addressOffset>0x2c</addressOffset>
+          <description>FRC2_INT</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>frc2_int_clr_mask</name>
+              <description>write to clear the status of the interrupt, if theinterrupt type is "level"</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>FRC2_ALARM</name>
+          <addressOffset>0x30</addressOffset>
+          <description>the alarm value for the counter</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>frc2_alarm</name>
+              <description>the alarm value for the counter</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>UART0</name>
+      <baseAddress>0x60000000</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x000001e0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>UART_FIFO</name>
+          <addressOffset>0x0</addressOffset>
+          <description>UART FIFO,length 128</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_rd_byte</name>
+              <description>R/W share the same address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INT_RAW</name>
+          <addressOffset>0x4</addressOffset>
+          <description>UART INTERRUPT RAW STATE</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_tout_int_raw</name>
+              <description>The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>brk_det_int_raw</name>
+              <description>The interrupt raw bit for Rx byte start error</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>cts_chg_int_raw</name>
+              <description>The interrupt raw bit for CTS changing level</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>dsr_chg_int_raw</name>
+              <description>The interrupt raw bit for DSR changing level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_ovf_int_raw</name>
+              <description>The interrupt raw bit for rx fifo overflow</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>frm_err_int_raw</name>
+              <description>The interrupt raw bit for other rx error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>parity_err_int_raw</name>
+              <description>The interrupt raw bit for parity check error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>txfifo_empty_int_raw</name>
+              <description>The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_full_int_raw</name>
+              <description>The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INT_ST</name>
+          <addressOffset>0x8</addressOffset>
+          <description>UART INTERRUPT STATEREGISTERUART_INT_RAW&amp;UART_INT_ENA</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_tout_int_st</name>
+              <description>The interrupt state bit for Rx time-out event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>brk_det_int_st</name>
+              <description>The interrupt state bit for rx byte start error</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>cts_chg_int_st</name>
+              <description>The interrupt state bit for CTS changing level</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>dsr_chg_int_st</name>
+              <description>The interrupt state bit for DSR changing level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_ovf_int_st</name>
+              <description>The interrupt state bit for RX fifo overflow</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>frm_err_int_st</name>
+              <description>The interrupt state for other rx error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>parity_err_int_st</name>
+              <description>The interrupt state bit for rx parity error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>txfifo_empty_int_st</name>
+              <description>The interrupt state bit for TX fifo empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_full_int_st</name>
+              <description>The interrupt state bit for RX fifo full event</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INT_ENA</name>
+          <addressOffset>0xc</addressOffset>
+          <description>UART INTERRUPT ENABLE REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_tout_int_ena</name>
+              <description>The interrupt enable bit for rx time-out interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>brk_det_int_ena</name>
+              <description>The interrupt enable bit for rx byte start error</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>cts_chg_int_ena</name>
+              <description>The interrupt enable bit for CTS changing level</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>dsr_chg_int_ena</name>
+              <description>The interrupt enable bit for DSR changing level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rxfifo_ovf_int_ena</name>
+              <description>The interrupt enable bit for rx fifo overflow</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>frm_err_int_ena</name>
+              <description>The interrupt enable bit for other rx error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>parity_err_int_ena</name>
+              <description>The interrupt enable bit for parity error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>txfifo_empty_int_ena</name>
+              <description>The interrupt enable bit for tx fifo empty event</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rxfifo_full_int_ena</name>
+              <description>The interrupt enable bit for rx fifo full event</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INT_CLR</name>
+          <addressOffset>0x10</addressOffset>
+          <description>UART INTERRUPT CLEAR REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_tout_int_clr</name>
+              <description>Set this bit to clear the rx time-out interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>brk_det_int_clr</name>
+              <description>Set this bit to clear the rx byte start interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>cts_chg_int_clr</name>
+              <description>Set this bit to clear the CTS changing interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>dsr_chg_int_clr</name>
+              <description>Set this bit to clear the DSR changing interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>rxfifo_ovf_int_clr</name>
+              <description>Set this bit to clear the rx fifo over-flow interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>frm_err_int_clr</name>
+              <description>Set this bit to clear other rx error interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>parity_err_int_clr</name>
+              <description>Set this bit to clear the parity error interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>txfifo_empty_int_clr</name>
+              <description>Set this bit to clear the tx fifo empty interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>rxfifo_full_int_clr</name>
+              <description>Set this bit to clear the rx fifo full interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_CLKDIV</name>
+          <addressOffset>0x14</addressOffset>
+          <description>UART CLK DIV REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>uart_clkdiv</name>
+              <description>BAUDRATE = UART_CLK_FREQ / UART_CLKDIV</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_AUTOBAUD</name>
+          <addressOffset>0x18</addressOffset>
+          <description>UART BAUDRATE DETECT REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>glitch_filt</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>autobaud_en</name>
+              <description>Set this bit to enable baudrate detect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_STATUS</name>
+          <addressOffset>0x1c</addressOffset>
+          <description>UART STATUS REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>txd</name>
+              <description>The level of the uart txd pin</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rtsn</name>
+              <description>The level of uart rts pin</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>dtrn</name>
+              <description>The level of uart dtr pin</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>txfifo_cnt</name>
+              <description>Number of data in UART TX fifo</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxd</name>
+              <description>The level of uart rxd pin</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ctsn</name>
+              <description>The level of uart cts pin</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>dsrn</name>
+              <description>The level of uart dsr pin</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_cnt</name>
+              <description>Number of data in uart rx fifo</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_CONF0</name>
+          <addressOffset>0x20</addressOffset>
+          <description>UART CONFIG0(UART0 and UART1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>uart_dtr_inv</name>
+              <description>Set this bit to inverse uart dtr level</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_rts_inv</name>
+              <description>Set this bit to inverse uart rts level</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_txd_inv</name>
+              <description>Set this bit to inverse uart txd level</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_dsr_inv</name>
+              <description>Set this bit to inverse uart dsr level</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_cts_inv</name>
+              <description>Set this bit to inverse uart cts level</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_rxd_inv</name>
+              <description>Set this bit to inverse uart rxd level</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>txfifo_rst</name>
+              <description>Set this bit to reset uart tx fifo</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rxfifo_rst</name>
+              <description>Set this bit to reset uart rx fifo</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>tx_flow_en</name>
+              <description>Set this bit to enable uart tx hardware flow control</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_loopback</name>
+              <description>Set this bit to enable uart loopback test mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>txd_brk</name>
+              <description>RESERVED, DO NOT CHANGE THIS BIT</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>sw_dtr</name>
+              <description>sw dtr</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>sw_rts</name>
+              <description>sw rts</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>stop_bit_num</name>
+              <description>Set stop bit: 1:1bit  2:1.5bits  3:2bits</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>bit_num</name>
+              <description>Set bit num:  0:5bits 1:6bits 2:7bits 3:8bits</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>parity_en</name>
+              <description>Set this bit to enable uart parity check</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>parity</name>
+              <description>Set parity check:  0:even 1:odd, UART CONFIG1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_CONF1</name>
+          <addressOffset>0x24</addressOffset>
+          <description>Set this bit to enable rx time-out function</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rx_tout_en</name>
+              <description>Set this bit to enable rx time-out function</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rx_tout_thrhd</name>
+              <description>Config bits for rx time-out threshold,uint: byte,0-127</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rx_flow_en</name>
+              <description>Set this bit to enable rx hardware flow control</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rx_flow_thrhd</name>
+              <description>The config bits for rx flow control threshold,0-127</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>txfifo_empty_thrhd</name>
+              <description>The config bits for tx fifo empty threshold,0-127</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rxfifo_full_thrhd</name>
+              <description>The config bits for rx fifo full threshold,0-127</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_LOWPULSE</name>
+          <addressOffset>0x28</addressOffset>
+          <description>UART_LOWPULSE</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>lowpulse_min_cnt</name>
+              <description>used in baudrate detect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_HIGHPULSE</name>
+          <addressOffset>0x2c</addressOffset>
+          <description>UART_HIGHPULSE</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>highpulse_min_cnt</name>
+              <description>used in baudrate detect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_RXD_CNT</name>
+          <addressOffset>0x30</addressOffset>
+          <description>UART_RXD_CNT</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxd_edge_cnt</name>
+              <description>used in baudrate detect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_DATE</name>
+          <addressOffset>0x78</addressOffset>
+          <description>UART HW INFO</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>uart_date</name>
+              <description>UART HW INFO</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_ID</name>
+          <addressOffset>0x7c</addressOffset>
+          <description>UART_ID</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>uart_id</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>UART1</name>
+      <baseAddress>0x60000f00</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x000001e0</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>UART_FIFO</name>
+          <addressOffset>0x0</addressOffset>
+          <description>UART FIFO,length 128</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_rd_byte</name>
+              <description>R/W share the same address</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INT_RAW</name>
+          <addressOffset>0x4</addressOffset>
+          <description>UART INTERRUPT RAW STATE</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_tout_int_raw</name>
+              <description>The interrupt raw bit for Rx time-out interrupt(depands on theUART_RX_TOUT_THRHD)</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>brk_det_int_raw</name>
+              <description>The interrupt raw bit for Rx byte start error</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>cts_chg_int_raw</name>
+              <description>The interrupt raw bit for CTS changing level</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>dsr_chg_int_raw</name>
+              <description>The interrupt raw bit for DSR changing level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_ovf_int_raw</name>
+              <description>The interrupt raw bit for rx fifo overflow</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>frm_err_int_raw</name>
+              <description>The interrupt raw bit for other rx error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>parity_err_int_raw</name>
+              <description>The interrupt raw bit for parity check error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>txfifo_empty_int_raw</name>
+              <description>The interrupt raw bit for tx fifo empty interrupt(depands onUART_TXFIFO_EMPTY_THRHD bits)</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_full_int_raw</name>
+              <description>The interrupt raw bit for rx fifo full interrupt(depands onUART_RXFIFO_FULL_THRHD bits)</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INT_ST</name>
+          <addressOffset>0x8</addressOffset>
+          <description>UART INTERRUPT STATEREGISTERUART_INT_RAW&amp;UART_INT_ENA</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_tout_int_st</name>
+              <description>The interrupt state bit for Rx time-out event</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>brk_det_int_st</name>
+              <description>The interrupt state bit for rx byte start error</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>cts_chg_int_st</name>
+              <description>The interrupt state bit for CTS changing level</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>dsr_chg_int_st</name>
+              <description>The interrupt state bit for DSR changing level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_ovf_int_st</name>
+              <description>The interrupt state bit for RX fifo overflow</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>frm_err_int_st</name>
+              <description>The interrupt state for other rx error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>parity_err_int_st</name>
+              <description>The interrupt state bit for rx parity error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>txfifo_empty_int_st</name>
+              <description>The interrupt state bit for TX fifo empty</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_full_int_st</name>
+              <description>The interrupt state bit for RX fifo full event</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INT_ENA</name>
+          <addressOffset>0xc</addressOffset>
+          <description>UART INTERRUPT ENABLE REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_tout_int_ena</name>
+              <description>The interrupt enable bit for rx time-out interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>brk_det_int_ena</name>
+              <description>The interrupt enable bit for rx byte start error</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>cts_chg_int_ena</name>
+              <description>The interrupt enable bit for CTS changing level</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>dsr_chg_int_ena</name>
+              <description>The interrupt enable bit for DSR changing level</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rxfifo_ovf_int_ena</name>
+              <description>The interrupt enable bit for rx fifo overflow</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>frm_err_int_ena</name>
+              <description>The interrupt enable bit for other rx error</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>parity_err_int_ena</name>
+              <description>The interrupt enable bit for parity error</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>txfifo_empty_int_ena</name>
+              <description>The interrupt enable bit for tx fifo empty event</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rxfifo_full_int_ena</name>
+              <description>The interrupt enable bit for rx fifo full event</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_INT_CLR</name>
+          <addressOffset>0x10</addressOffset>
+          <description>UART INTERRUPT CLEAR REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxfifo_tout_int_clr</name>
+              <description>Set this bit to clear the rx time-out interrupt</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>brk_det_int_clr</name>
+              <description>Set this bit to clear the rx byte start interrupt</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>cts_chg_int_clr</name>
+              <description>Set this bit to clear the CTS changing interrupt</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>dsr_chg_int_clr</name>
+              <description>Set this bit to clear the DSR changing interrupt</description>
+              <bitOffset>5</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>rxfifo_ovf_int_clr</name>
+              <description>Set this bit to clear the rx fifo over-flow interrupt</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>frm_err_int_clr</name>
+              <description>Set this bit to clear other rx error interrupt</description>
+              <bitOffset>3</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>parity_err_int_clr</name>
+              <description>Set this bit to clear the parity error interrupt</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>txfifo_empty_int_clr</name>
+              <description>Set this bit to clear the tx fifo empty interrupt</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+            <field>
+              <name>rxfifo_full_int_clr</name>
+              <description>Set this bit to clear the rx fifo full interrupt</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>write-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_CLKDIV</name>
+          <addressOffset>0x14</addressOffset>
+          <description>UART CLK DIV REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>uart_clkdiv</name>
+              <description>BAUDRATE = UART_CLK_FREQ / UART_CLKDIV</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_AUTOBAUD</name>
+          <addressOffset>0x18</addressOffset>
+          <description>UART BAUDRATE DETECT REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>glitch_filt</name>
+              <bitOffset>8</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>autobaud_en</name>
+              <description>Set this bit to enable baudrate detect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_STATUS</name>
+          <addressOffset>0x1c</addressOffset>
+          <description>UART STATUS REGISTER</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>txd</name>
+              <description>The level of the uart txd pin</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rtsn</name>
+              <description>The level of uart rts pin</description>
+              <bitOffset>30</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>dtrn</name>
+              <description>The level of uart dtr pin</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>txfifo_cnt</name>
+              <description>Number of data in UART TX fifo</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxd</name>
+              <description>The level of uart rxd pin</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>ctsn</name>
+              <description>The level of uart cts pin</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>dsrn</name>
+              <description>The level of uart dsr pin</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-only</access>
+            </field>
+            <field>
+              <name>rxfifo_cnt</name>
+              <description>Number of data in uart rx fifo</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>8</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_CONF0</name>
+          <addressOffset>0x20</addressOffset>
+          <description>UART CONFIG0(UART0 and UART1)</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>uart_dtr_inv</name>
+              <description>Set this bit to inverse uart dtr level</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_rts_inv</name>
+              <description>Set this bit to inverse uart rts level</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_txd_inv</name>
+              <description>Set this bit to inverse uart txd level</description>
+              <bitOffset>22</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_dsr_inv</name>
+              <description>Set this bit to inverse uart dsr level</description>
+              <bitOffset>21</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_cts_inv</name>
+              <description>Set this bit to inverse uart cts level</description>
+              <bitOffset>20</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_rxd_inv</name>
+              <description>Set this bit to inverse uart rxd level</description>
+              <bitOffset>19</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>txfifo_rst</name>
+              <description>Set this bit to reset uart tx fifo</description>
+              <bitOffset>18</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rxfifo_rst</name>
+              <description>Set this bit to reset uart rx fifo</description>
+              <bitOffset>17</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>tx_flow_en</name>
+              <description>Set this bit to enable uart tx hardware flow control</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>uart_loopback</name>
+              <description>Set this bit to enable uart loopback test mode</description>
+              <bitOffset>14</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>txd_brk</name>
+              <description>RESERVED, DO NOT CHANGE THIS BIT</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>sw_dtr</name>
+              <description>sw dtr</description>
+              <bitOffset>7</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>sw_rts</name>
+              <description>sw rts</description>
+              <bitOffset>6</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>stop_bit_num</name>
+              <description>Set stop bit: 1:1bit  2:1.5bits  3:2bits</description>
+              <bitOffset>4</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>bit_num</name>
+              <description>Set bit num:  0:5bits 1:6bits 2:7bits 3:8bits</description>
+              <bitOffset>2</bitOffset>
+              <bitWidth>2</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>parity_en</name>
+              <description>Set this bit to enable uart parity check</description>
+              <bitOffset>1</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>parity</name>
+              <description>Set parity check:  0:even 1:odd, UART CONFIG1</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_CONF1</name>
+          <addressOffset>0x24</addressOffset>
+          <description>Set this bit to enable rx time-out function</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rx_tout_en</name>
+              <description>Set this bit to enable rx time-out function</description>
+              <bitOffset>31</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rx_tout_thrhd</name>
+              <description>Config bits for rx time-out threshold,uint: byte,0-127</description>
+              <bitOffset>24</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rx_flow_en</name>
+              <description>Set this bit to enable rx hardware flow control</description>
+              <bitOffset>23</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rx_flow_thrhd</name>
+              <description>The config bits for rx flow control threshold,0-127</description>
+              <bitOffset>16</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>txfifo_empty_thrhd</name>
+              <description>The config bits for tx fifo empty threshold,0-127</description>
+              <bitOffset>8</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>rxfifo_full_thrhd</name>
+              <description>The config bits for rx fifo full threshold,0-127</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>7</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_LOWPULSE</name>
+          <addressOffset>0x28</addressOffset>
+          <description>UART_LOWPULSE</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>lowpulse_min_cnt</name>
+              <description>used in baudrate detect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_HIGHPULSE</name>
+          <addressOffset>0x2c</addressOffset>
+          <description>UART_HIGHPULSE</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>highpulse_min_cnt</name>
+              <description>used in baudrate detect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>20</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_RXD_CNT</name>
+          <addressOffset>0x30</addressOffset>
+          <description>UART_RXD_CNT</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>rxd_edge_cnt</name>
+              <description>used in baudrate detect</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>10</bitWidth>
+              <access>read-only</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_DATE</name>
+          <addressOffset>0x78</addressOffset>
+          <description>UART HW INFO</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>uart_date</name>
+              <description>UART HW INFO</description>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>UART_ID</name>
+          <addressOffset>0x7c</addressOffset>
+          <description>UART_ID</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>uart_id</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+    <peripheral>
+      <name>WDT</name>
+      <baseAddress>0x60000900</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>0x00000080</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>WDT_CTL</name>
+          <addressOffset>0x0</addressOffset>
+          <description>WDT_CTL</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDT_OP</name>
+          <addressOffset>0x4</addressOffset>
+          <description>WDT_OP</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDT_OP_ND</name>
+          <addressOffset>0x8</addressOffset>
+          <description>WDT_OP_ND</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>WDT_RST</name>
+          <addressOffset>0x14</addressOffset>
+          <description>WDT_RST</description>
+          <size>32</size>
+          <resetValue>0x00000000</resetValue>
+          <fields>
+            <field>
+              <name>Register</name>
+              <bitOffset>0</bitOffset>
+              <bitWidth>32</bitWidth>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>
diff --git a/tools/partitions/app3M_fat9M_16MB.csv b/tools/partitions/app3M_fat9M_16MB.csv
index 0f67e69fbfe..b1dbf158601 100644
--- a/tools/partitions/app3M_fat9M_16MB.csv
+++ b/tools/partitions/app3M_fat9M_16MB.csv
@@ -3,5 +3,6 @@ nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x300000,
 app1,     app,  ota_1,   0x310000,0x300000,
-ffat,     data, fat,     0x610000,0x9F0000,
+ffat,     data, fat,     0x610000,0x9E0000,
+coredump, data, coredump,0xFF0000,0x10000,
 # to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage
diff --git a/tools/partitions/app3M_fat9M_fact512k_16MB.csv b/tools/partitions/app3M_fat9M_fact512k_16MB.csv
new file mode 100644
index 00000000000..dac4603e01a
--- /dev/null
+++ b/tools/partitions/app3M_fat9M_fact512k_16MB.csv
@@ -0,0 +1,9 @@
+# Name,   Type, SubType,  Offset,   Size,     Flags
+nvs,      data, nvs,        0x9000,   0x5000,
+otadata,  data, ota,        0xe000,   0x2000,
+app0,     app,  ota_0,     0x10000, 0x300000,
+app1,     app,  ota_1,    0x310000, 0x300000,
+ffat,     data, fat,      0x610000, 0x960000,
+factory,  app,  factory,  0xF70000,  0x80000,
+coredump, data, coredump, 0xFF0000,  0x10000,
+# to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage
diff --git a/tools/partitions/app3M_spiffs9M_fact512k_16MB.csv b/tools/partitions/app3M_spiffs9M_fact512k_16MB.csv
new file mode 100644
index 00000000000..3b8909da325
--- /dev/null
+++ b/tools/partitions/app3M_spiffs9M_fact512k_16MB.csv
@@ -0,0 +1,8 @@
+# Name,   Type, SubType,  Offset,   Size,     Flags
+nvs,      data, nvs,        0x9000,   0x5000,
+otadata,  data, ota,        0xe000,   0x2000,
+app0,     app,  ota_0,     0x10000, 0x300000,
+app1,     app,  ota_1,    0x310000, 0x300000,
+spiffs,   data, spiffs,   0x610000, 0x960000,
+factory,  app,  factory,  0xF70000,  0x80000,
+coredump, data, coredump, 0xFF0000,  0x10000,
diff --git a/tools/partitions/bare_minimum_2MB.csv b/tools/partitions/bare_minimum_2MB.csv
new file mode 100644
index 00000000000..e688a47cfa2
--- /dev/null
+++ b/tools/partitions/bare_minimum_2MB.csv
@@ -0,0 +1,3 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     36K,     20K,
+factory,  app,  factory, 64K,     1900K,
diff --git a/tools/partitions/default.csv b/tools/partitions/default.csv
index e9772b6f891..960469b8233 100644
--- a/tools/partitions/default.csv
+++ b/tools/partitions/default.csv
@@ -3,4 +3,5 @@ nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x140000,
 app1,     app,  ota_1,   0x150000,0x140000,
-spiffs,   data, spiffs,  0x290000,0x170000,
+spiffs,   data, spiffs,  0x290000,0x160000,
+coredump, data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/default_16MB.csv b/tools/partitions/default_16MB.csv
index 7b89daee9f0..67d773728e9 100644
--- a/tools/partitions/default_16MB.csv
+++ b/tools/partitions/default_16MB.csv
@@ -3,4 +3,5 @@ nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x640000,
 app1,     app,  ota_1,   0x650000,0x640000,
-spiffs,   data, spiffs,  0xc90000,0x370000,
+spiffs,   data, spiffs,  0xc90000,0x360000,
+coredump, data, coredump,0xFF0000,0x10000,
diff --git a/tools/partitions/default_32MB.csv b/tools/partitions/default_32MB.csv
new file mode 100644
index 00000000000..dd07ac32185
--- /dev/null
+++ b/tools/partitions/default_32MB.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0xC80000,
+app1,     app,  ota_1,   0xC90000,0xC80000,
+spiffs,   data, spiffs,  0x1910000,0x6C0000,
+coredump, data, coredump,0x1FF0000,0x10000,
diff --git a/tools/partitions/default_8MB.csv b/tools/partitions/default_8MB.csv
index d21c7f6b177..4e92afa6936 100644
--- a/tools/partitions/default_8MB.csv
+++ b/tools/partitions/default_8MB.csv
@@ -3,4 +3,5 @@ nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x330000,
 app1,     app,  ota_1,   0x340000,0x330000,
-spiffs,   data, spiffs,  0x670000,0x190000,
+spiffs,   data, spiffs,  0x670000,0x180000,
+coredump, data, coredump,0x7F0000,0x10000,
diff --git a/tools/partitions/default_ffat.csv b/tools/partitions/default_ffat.csv
index d921c9fe3d9..008bd390f70 100644
--- a/tools/partitions/default_ffat.csv
+++ b/tools/partitions/default_ffat.csv
@@ -3,4 +3,5 @@ nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x140000,
 app1,     app,  ota_1,   0x150000,0x140000,
-ffat,     data, fat,     0x290000,0x170000,
+ffat,     data, fat,     0x290000,0x160000,
+coredump, data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/default_ffat_8MB.csv b/tools/partitions/default_ffat_8MB.csv
new file mode 100644
index 00000000000..2791bf7912e
--- /dev/null
+++ b/tools/partitions/default_ffat_8MB.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0x330000,
+app1,     app,  ota_1,   0x340000,0x330000,
+ffat,     data, fat,     0x670000,0x180000,
+coredump, data, coredump,0x7F0000,0x10000,
diff --git a/tools/partitions/esp_sr_16.csv b/tools/partitions/esp_sr_16.csv
new file mode 100644
index 00000000000..97e41c45276
--- /dev/null
+++ b/tools/partitions/esp_sr_16.csv
@@ -0,0 +1,8 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,       0x9000,   0x5000,
+otadata,  data, ota,       0xe000,   0x2000,
+app0,     app,  ota_0,    0x10000, 0x300000,
+app1,     app,  ota_1,   0x310000, 0x300000,
+spiffs,   data, spiffs,  0x610000, 0x700000,
+model,    data, spiffs,  0xD10000, 0x2E0000,
+coredump, data, coredump,0xFF0000,  0x10000,
diff --git a/tools/partitions/ffat.csv b/tools/partitions/ffat.csv
index b98bf0c3034..189f70c1513 100644
--- a/tools/partitions/ffat.csv
+++ b/tools/partitions/ffat.csv
@@ -3,5 +3,6 @@ nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x200000,
 app1,     app,  ota_1,   0x210000,0x200000,
-ffat,     data, fat,     0x410000,0xBF0000,
+ffat,     data, fat,     0x410000,0xBE0000,
+coredump, data, coredump,0xFF0000,0x10000,
 # to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage
diff --git a/tools/partitions/huge_app.csv b/tools/partitions/huge_app.csv
index 290a7cc738b..1d00925f6e8 100644
--- a/tools/partitions/huge_app.csv
+++ b/tools/partitions/huge_app.csv
@@ -2,4 +2,5 @@
 nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x300000,
-spiffs,   data, spiffs,  0x310000,0xF0000,
+spiffs,   data, spiffs,  0x310000,0xE0000,
+coredump, data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/large_fat_32MB.csv b/tools/partitions/large_fat_32MB.csv
new file mode 100644
index 00000000000..70b73fefc19
--- /dev/null
+++ b/tools/partitions/large_fat_32MB.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0x480000,
+app1,     app,  ota_1,   0x490000,0x480000,
+ffat,     data, fat,     0x910000,0x16E0000,
+coredump, data, coredump,0x1FF0000,0x10000,
diff --git a/tools/partitions/large_ffat_8MB.csv b/tools/partitions/large_ffat_8MB.csv
new file mode 100644
index 00000000000..20632d6c512
--- /dev/null
+++ b/tools/partitions/large_ffat_8MB.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0x140000,
+app1,     app,  ota_1,   0x150000,0x140000,
+ffat,     data, fat,     0x290000,0x560000,
+coredump, data, coredump,0x7F0000,0x10000,
diff --git a/tools/partitions/large_littlefs_32MB.csv b/tools/partitions/large_littlefs_32MB.csv
new file mode 100644
index 00000000000..34d4254ff4e
--- /dev/null
+++ b/tools/partitions/large_littlefs_32MB.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0x480000,
+app1,     app,  ota_1,   0x490000,0x480000,
+spiffs,   data, spiffs,  0x910000,0x16E0000,
+coredump, data, coredump,0x1FF0000,0x10000,
diff --git a/tools/partitions/large_spiffs_16MB.csv b/tools/partitions/large_spiffs_16MB.csv
index 7974c9eb140..a0483430726 100644
--- a/tools/partitions/large_spiffs_16MB.csv
+++ b/tools/partitions/large_spiffs_16MB.csv
@@ -3,4 +3,5 @@ nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x480000,
 app1,     app,  ota_1,   0x490000,0x480000,
-spiffs,   data, spiffs,  0x910000,0x6F0000,
+spiffs,   data, spiffs,  0x910000,0x6E0000,
+coredump, data, coredump,0xFF0000,0x10000,
diff --git a/tools/partitions/large_spiffs_8MB.csv b/tools/partitions/large_spiffs_8MB.csv
new file mode 100644
index 00000000000..ecf87c6d280
--- /dev/null
+++ b/tools/partitions/large_spiffs_8MB.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0x140000,
+app1,     app,  ota_1,   0x150000,0x140000,
+spiffs,   data, spiffs,  0x290000,0x560000,
+coredump, data, coredump,0x7F0000,0x10000,
diff --git a/tools/partitions/m5stack_partitions_16MB_factory_4_apps.csv b/tools/partitions/m5stack_partitions_16MB_factory_4_apps.csv
new file mode 100644
index 00000000000..f3781c2f423
--- /dev/null
+++ b/tools/partitions/m5stack_partitions_16MB_factory_4_apps.csv
@@ -0,0 +1,11 @@
+## 4 Apps + Factory
+## Name,   Type, SubType,    Offset,     Size
+nvs,      data, nvs,        0x9000,   0x5000
+otadata,  data, ota,        0xe000,   0x2000
+ota_0,    0,    ota_0,     0x10000, 0x300000
+ota_1,    0,    ota_1,    0x310000, 0x300000
+ota_2,    0,    ota_2,    0x610000, 0x300000
+ota_3,    0,    ota_3,    0x910000, 0x300000
+firmware, app,  factory,  0xC10000, 0x0F0000
+spiffs,   data, spiffs,   0xD00000, 0x2F0000
+coredump, data, coredump, 0xFF0000,  0x10000
diff --git a/tools/partitions/m5stack_partitions_16MB_factory_6_apps.csv b/tools/partitions/m5stack_partitions_16MB_factory_6_apps.csv
new file mode 100644
index 00000000000..6840e864945
--- /dev/null
+++ b/tools/partitions/m5stack_partitions_16MB_factory_6_apps.csv
@@ -0,0 +1,13 @@
+# 6 Apps + Factory
+# Name,   Type, SubType,    Offset,     Size
+nvs,      data, nvs,        0x9000,   0x5000
+otadata,  data, ota,        0xe000,   0x2000
+ota_0,    0,    ota_0,     0x10000, 0x200000
+ota_1,    0,    ota_1,    0x210000, 0x200000
+ota_2,    0,    ota_2,    0x410000, 0x200000
+ota_3,    0,    ota_3,    0x610000, 0x200000
+ota_4,    0,    ota_4,    0x810000, 0x200000
+ota_5,    0,    ota_5,    0xA10000, 0x200000
+firmware, app,  factory,  0xC10000, 0x0F0000
+spiffs,   data, spiffs,   0xD00000, 0x2F0000
+coredump, data, coredump, 0xFF0000,  0x10000
diff --git a/tools/partitions/max_app_4MB.csv b/tools/partitions/max_app_4MB.csv
new file mode 100644
index 00000000000..ec30c10065b
--- /dev/null
+++ b/tools/partitions/max_app_4MB.csv
@@ -0,0 +1,5 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  factory, 0x10000, 0x3E0000,
+coredump, data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/max_app_8MB.csv b/tools/partitions/max_app_8MB.csv
new file mode 100644
index 00000000000..502d9fe9fa2
--- /dev/null
+++ b/tools/partitions/max_app_8MB.csv
@@ -0,0 +1,5 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  factory, 0x10000, 0x7E0000,
+coredump, data, coredump,0x7F0000,0x10000,
diff --git a/tools/partitions/min_spiffs.csv b/tools/partitions/min_spiffs.csv
index 0b6a9ffd01e..0990a3b469e 100644
--- a/tools/partitions/min_spiffs.csv
+++ b/tools/partitions/min_spiffs.csv
@@ -3,4 +3,5 @@ nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x1E0000,
 app1,     app,  ota_1,   0x1F0000,0x1E0000,
-spiffs,   data, spiffs,  0x3D0000,0x30000,
+spiffs,   data, spiffs,  0x3D0000,0x20000,
+coredump, data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/minimal.csv b/tools/partitions/minimal.csv
index 6ebeeb32dc2..32c70abc1d7 100644
--- a/tools/partitions/minimal.csv
+++ b/tools/partitions/minimal.csv
@@ -2,4 +2,5 @@
 nvs,      data, nvs,     0x9000,   0x5000,
 otadata,  data, ota,     0xe000,   0x2000,
 app0,     app,  ota_0,   0x10000,  0x140000,
-spiffs,   data, spiffs,  0x150000, 0xB0000,
+spiffs,   data, spiffs,  0x150000, 0xA0000,
+coredump, data, coredump,0x1F0000, 0x10000,
diff --git a/tools/partitions/no_fs.csv b/tools/partitions/no_fs.csv
new file mode 100644
index 00000000000..a9078ee522f
--- /dev/null
+++ b/tools/partitions/no_fs.csv
@@ -0,0 +1,6 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0x1F0000,
+app1,     app,  ota_1,   0x200000,0x1F0000,
+coredump, data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/no_ota.csv b/tools/partitions/no_ota.csv
index 3314273b884..173a4e1d7f7 100644
--- a/tools/partitions/no_ota.csv
+++ b/tools/partitions/no_ota.csv
@@ -2,4 +2,5 @@
 nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x200000,
-spiffs,   data, spiffs,  0x210000,0x1F0000,
+spiffs,   data, spiffs,  0x210000,0x1E0000,
+coredump, data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/noota_3g.csv b/tools/partitions/noota_3g.csv
index a684385bdc8..71d9f5e7da4 100644
--- a/tools/partitions/noota_3g.csv
+++ b/tools/partitions/noota_3g.csv
@@ -2,4 +2,5 @@
 nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x100000,
-spiffs,   data, spiffs,  0x110000,0x2F0000,
+spiffs,   data, spiffs,  0x110000,0x2E0000,
+coredump, data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/noota_3gffat.csv b/tools/partitions/noota_3gffat.csv
index f008c277897..4712dd1ac96 100644
--- a/tools/partitions/noota_3gffat.csv
+++ b/tools/partitions/noota_3gffat.csv
@@ -2,5 +2,6 @@
 nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x100000,
-ffat,     data, fat,     0x110000,0x2F0000,
+ffat,     data, fat,     0x110000,0x2E0000,
+coredump, data, coredump,0x3F0000,0x10000,
 # to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage
diff --git a/tools/partitions/noota_ffat.csv b/tools/partitions/noota_ffat.csv
index 69d702f80b2..86c3067dfcb 100644
--- a/tools/partitions/noota_ffat.csv
+++ b/tools/partitions/noota_ffat.csv
@@ -2,5 +2,6 @@
 nvs,      data, nvs,     0x9000,  0x5000,
 otadata,  data, ota,     0xe000,  0x2000,
 app0,     app,  ota_0,   0x10000, 0x200000,
-ffat,     data, fat,     0x210000,0x1F0000,
+ffat,     data, fat,     0x210000,0x1E0000,
+coredump, data, coredump,0x3F0000,0x10000,
 # to create/use ffat, see https://github.com/marcmerlin/esp32_fatfsimage
diff --git a/tools/partitions/ota_nofs_4MB.csv b/tools/partitions/ota_nofs_4MB.csv
new file mode 100644
index 00000000000..04240badb49
--- /dev/null
+++ b/tools/partitions/ota_nofs_4MB.csv
@@ -0,0 +1,6 @@
+#   Name, Type,  SubType,   Offset,      Size, Flags
+     nvs, data,      nvs,   0x9000,    0x5000,
+ otadata, data,      ota,   0xE000,    0x2000,
+    app0,  app,    ota_0,  0x10000,  0x1F0000,
+    app1,  app,    ota_1, 0x200000,  0x1F0000,
+coredump, data, coredump, 0x3F0000,   0x10000,
diff --git a/tools/partitions/rainmaker.csv b/tools/partitions/rainmaker.csv
new file mode 100644
index 00000000000..1eabd86b827
--- /dev/null
+++ b/tools/partitions/rainmaker.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,       data,  nvs,     0x9000,   0x5000,
+otadata,   data,  ota,     0xe000,   0x2000,
+ota_0,     app,   ota_0,   0x10000,  0x1E0000,
+ota_1,     app,   ota_1,   0x1F0000, 0x1E0000,
+fctry,     data,  nvs,     0x3D0000, 0x6000,
+coredump,  data,  coredump,0x3F0000, 0x10000,
diff --git a/tools/partitions/rainmaker_4MB_no_ota.csv b/tools/partitions/rainmaker_4MB_no_ota.csv
new file mode 100644
index 00000000000..ec10004d158
--- /dev/null
+++ b/tools/partitions/rainmaker_4MB_no_ota.csv
@@ -0,0 +1,6 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,       data,  nvs,     0x9000,   0x5000,
+otadata,   data,  ota,     0xe000,   0x2000,
+ota_0,     app,   ota_0,   0x10000,  0x3DA000,
+fctry,     data,  nvs,     0x3EA000, 0x6000,
+coredump,  data,  coredump,0x3F0000, 0x10000,
diff --git a/tools/partitions/rainmaker_8MB.csv b/tools/partitions/rainmaker_8MB.csv
new file mode 100644
index 00000000000..6d65333063f
--- /dev/null
+++ b/tools/partitions/rainmaker_8MB.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,       data,  nvs,     0x9000,   0x5000,
+otadata,   data,  ota,     0xe000,   0x2000,
+ota_0,     app,   ota_0,   0x10000,  0x3ED000,
+ota_1,     app,   ota_1,   0x3FD000, 0x3ED000,
+fctry,     data,  nvs,     0x7EA000, 0x6000,
+coredump,  data,  coredump,0x7F0000, 0x10000,
diff --git a/tools/partitions/tinyuf2-partitions-16MB-noota.csv b/tools/partitions/tinyuf2-partitions-16MB-noota.csv
new file mode 100644
index 00000000000..0df597271ef
--- /dev/null
+++ b/tools/partitions/tinyuf2-partitions-16MB-noota.csv
@@ -0,0 +1,9 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    app,  ota_0,   0x10000,  4096K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  11968K,
diff --git a/tools/partitions/tinyuf2-partitions-16MB.csv b/tools/partitions/tinyuf2-partitions-16MB.csv
new file mode 100644
index 00000000000..55f6c2b8d76
--- /dev/null
+++ b/tools/partitions/tinyuf2-partitions-16MB.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    app,  ota_0,   0x10000,  2048K,
+ota_1,    app,  ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  11968K,
diff --git a/tools/partitions/tinyuf2-partitions-4MB-noota.csv b/tools/partitions/tinyuf2-partitions-4MB-noota.csv
new file mode 100644
index 00000000000..ab7fa8669d0
--- /dev/null
+++ b/tools/partitions/tinyuf2-partitions-4MB-noota.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,          0x8000, 4K
+
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    app,  ota_0,   0x10000,  2816K,
+uf2,      app,  factory,0x2d0000,  256K,
+ffat,     data, fat,    0x310000,  960K,
diff --git a/tools/partitions/tinyuf2-partitions-4MB.csv b/tools/partitions/tinyuf2-partitions-4MB.csv
new file mode 100644
index 00000000000..f3112a23b11
--- /dev/null
+++ b/tools/partitions/tinyuf2-partitions-4MB.csv
@@ -0,0 +1,11 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,          0x8000, 4K
+
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    app,  ota_0,   0x10000,  1408K,
+ota_1,    app,  ota_1,  0x170000,  1408K,
+uf2,      app,  factory,0x2d0000,  256K,
+ffat,     data, fat,    0x310000,  960K,
diff --git a/tools/partitions/tinyuf2-partitions-8MB-noota.csv b/tools/partitions/tinyuf2-partitions-8MB-noota.csv
new file mode 100644
index 00000000000..cef43294f46
--- /dev/null
+++ b/tools/partitions/tinyuf2-partitions-8MB-noota.csv
@@ -0,0 +1,9 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    app,    ota_0,   0x10000,  4096K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/tools/partitions/tinyuf2-partitions-8MB.csv b/tools/partitions/tinyuf2-partitions-8MB.csv
new file mode 100644
index 00000000000..a68b39e9fa7
--- /dev/null
+++ b/tools/partitions/tinyuf2-partitions-8MB.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    app,    ota_0,   0x10000,  2048K,
+ota_1,    app,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/tools/partitions/zigbee.csv b/tools/partitions/zigbee.csv
new file mode 100644
index 00000000000..938d59b01f3
--- /dev/null
+++ b/tools/partitions/zigbee.csv
@@ -0,0 +1,9 @@
+# Name,     Type, SubType, Offset,  Size, Flags
+nvs,        data, nvs,     0x9000,  0x5000,
+otadata,    data, ota,     0xe000,  0x2000,
+app0,       app,  ota_0,   0x10000, 0x140000,
+app1,       app,  ota_1,   0x150000,0x140000,
+spiffs,     data, spiffs,  0x290000,0x15B000,
+zb_storage, data, fat,     0x3EB000,0x4000,
+zb_fct,     data, fat,     0x3EF000,0x1000,
+coredump,   data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/zigbee_2MB.csv b/tools/partitions/zigbee_2MB.csv
new file mode 100644
index 00000000000..7034f9bd49b
--- /dev/null
+++ b/tools/partitions/zigbee_2MB.csv
@@ -0,0 +1,7 @@
+# Name,     Type, SubType, Offset,  Size, Flags
+nvs,        data, nvs,     0x9000,  0x5000,
+factory,    app,  factory, 0x10000, 0x140000,
+spiffs,     data, spiffs,  0x150000,0x9B000,
+zb_storage, data, fat,     0x1EB000,0x4000,
+zb_fct,     data, fat,     0x1EF000,0x1000,
+coredump,   data, coredump,0x1F0000,0x10000,
diff --git a/tools/partitions/zigbee_8MB.csv b/tools/partitions/zigbee_8MB.csv
new file mode 100644
index 00000000000..fdf46fb59d1
--- /dev/null
+++ b/tools/partitions/zigbee_8MB.csv
@@ -0,0 +1,9 @@
+# Name,     Type, SubType, Offset,  Size, Flags
+nvs,        data, nvs,     0x9000,  0x5000,
+otadata,    data, ota,     0xe000,  0x2000,
+app0,       app,  ota_0,   0x10000, 0x340000,
+app1,       app,  ota_1,   0x350000,0x340000,
+spiffs,     data, spiffs,  0x690000,0x15B000,
+zb_storage, data, fat,     0x7EB000,0x4000,
+zb_fct,     data, fat,     0x7EF000,0x1000,
+coredump,   data, coredump,0x7F0000,0x10000,
diff --git a/tools/partitions/zigbee_zczr.csv b/tools/partitions/zigbee_zczr.csv
new file mode 100644
index 00000000000..e734e1d66c5
--- /dev/null
+++ b/tools/partitions/zigbee_zczr.csv
@@ -0,0 +1,10 @@
+# Name,     Type, SubType, Offset,  Size, Flags
+nvs,        data, nvs,     0x9000,  0x5000,
+otadata,    data, ota,     0xe000,  0x2000,
+app0,       app,  ota_0,   0x10000, 0x140000,
+app1,       app,  ota_1,   0x150000,0x140000,
+spiffs,     data, spiffs,  0x290000,0x15A000,
+zb_storage, data, fat,     0x3EA000,0x4000,
+zb_fct,     data, fat,     0x3EE000,0x1000,
+rcp_fw,     data, spiffs,  0x3EF000,0x1000,
+coredump,   data, coredump,0x3F0000,0x10000,
diff --git a/tools/partitions/zigbee_zczr_2MB.csv b/tools/partitions/zigbee_zczr_2MB.csv
new file mode 100644
index 00000000000..10484eeed87
--- /dev/null
+++ b/tools/partitions/zigbee_zczr_2MB.csv
@@ -0,0 +1,8 @@
+# Name,     Type, SubType, Offset,  Size, Flags
+nvs,        data, nvs,     0x9000,  0x5000,
+factory,    app,  factory, 0x10000, 0x140000,
+spiffs,     data, spiffs,  0x150000,0x9A000,
+zb_storage, data, fat,     0x1EA000,0x4000,
+zb_fct,     data, fat,     0x1EE000,0x1000,
+rcp_fw,     data, spiffs,  0x1EF000,0x1000,
+coredump,   data, coredump,0x1F0000,0x10000,
diff --git a/tools/partitions/zigbee_zczr_8MB.csv b/tools/partitions/zigbee_zczr_8MB.csv
new file mode 100644
index 00000000000..70dd680dc1a
--- /dev/null
+++ b/tools/partitions/zigbee_zczr_8MB.csv
@@ -0,0 +1,10 @@
+# Name,     Type, SubType, Offset,  Size, Flags
+nvs,        data, nvs,     0x9000,  0x5000,
+otadata,    data, ota,     0xe000,  0x2000,
+app0,       app,  ota_0,   0x10000, 0x340000,
+app1,       app,  ota_1,   0x350000,0x340000,
+spiffs,     data, spiffs,  0x690000,0x15A000,
+zb_storage, data, fat,     0x7EA000,0x4000,
+zb_fct,     data, fat,     0x7EE000,0x1000,
+rcp_fw,     data, spiffs,  0x7EF000,0x1000,
+coredump,   data, coredump,0x7F0000,0x10000,
diff --git a/tools/pioarduino-build.py b/tools/pioarduino-build.py
new file mode 100644
index 00000000000..3335a716888
--- /dev/null
+++ b/tools/pioarduino-build.py
@@ -0,0 +1,251 @@
+# Copyright 2014-present PlatformIO <contact@platformio.org>
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#    http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+Arduino
+
+Arduino Wiring-based Framework allows writing cross-platform software to
+control devices attached to a wide range of Arduino boards to create all
+kinds of creative coding, interactive objects, spaces or physical experiences.
+
+http://arduino.cc/en/Reference/HomePage
+"""
+
+# Extends: https://github.com/pioarduino/platform-espressif32/blob/develop/builder/main.py
+
+from os.path import abspath, basename, isdir, isfile, join
+from copy import deepcopy
+from SCons.Script import DefaultEnvironment, SConscript
+
+env = DefaultEnvironment()
+platform = env.PioPlatform()
+board_config = env.BoardConfig()
+build_mcu = board_config.get("build.mcu", "").lower()
+partitions_name = board_config.get("build.partitions", board_config.get("build.arduino.partitions", ""))
+
+FRAMEWORK_DIR = platform.get_package_dir("framework-arduinoespressif32")
+FRAMEWORK_LIBS_DIR = platform.get_package_dir("framework-arduinoespressif32-libs")
+assert isdir(FRAMEWORK_DIR)
+
+
+#
+# Helpers
+#
+
+
+def get_partition_table_csv(variants_dir):
+    fwpartitions_dir = join(FRAMEWORK_DIR, "tools", "partitions")
+    variant_partitions_dir = join(variants_dir, board_config.get("build.variant", ""))
+
+    if partitions_name:
+        # A custom partitions file is selected
+        if isfile(env.subst(join(variant_partitions_dir, partitions_name))):
+            return join(variant_partitions_dir, partitions_name)
+
+        return abspath(
+            join(fwpartitions_dir, partitions_name)
+            if isfile(env.subst(join(fwpartitions_dir, partitions_name)))
+            else partitions_name
+        )
+
+    variant_partitions = join(variant_partitions_dir, "partitions.csv")
+    return variant_partitions if isfile(env.subst(variant_partitions)) else join(fwpartitions_dir, "default.csv")
+
+
+def get_bootloader_image(variants_dir):
+    bootloader_image_file = "bootloader.bin"
+    if partitions_name.endswith("tinyuf2.csv"):
+        bootloader_image_file = "bootloader-tinyuf2.bin"
+
+    variant_bootloader = join(
+        variants_dir,
+        board_config.get("build.variant", ""),
+        board_config.get("build.arduino.custom_bootloader", bootloader_image_file),
+    )
+
+    return (
+        variant_bootloader
+        if isfile(env.subst(variant_bootloader))
+        else generate_bootloader_image(
+            join(
+                FRAMEWORK_LIBS_DIR,
+                build_mcu,
+                "bin",
+                "bootloader_${__get_board_boot_mode(__env__)}_${__get_board_f_boot(__env__)}.elf",
+            )
+        )
+    )
+
+
+def generate_bootloader_image(bootloader_elf):
+    bootloader_cmd = env.Command(
+        join("$BUILD_DIR", "bootloader.bin"),
+        bootloader_elf,
+        env.VerboseAction(
+            " ".join(
+                [
+                    '"$PYTHONEXE" "$OBJCOPY"',
+                    "--chip",
+                    build_mcu,
+                    "elf2image",
+                    "--flash_mode",
+                    "${__get_board_flash_mode(__env__)}",
+                    "--flash_freq",
+                    "${__get_board_f_image(__env__)}",
+                    "--flash_size",
+                    board_config.get("upload.flash_size", "4MB"),
+                    "-o",
+                    "$TARGET",
+                    "$SOURCES",
+                ]
+            ),
+            "Building $TARGET",
+        ),
+    )
+
+    env.Depends("$BUILD_DIR/$PROGNAME$PROGSUFFIX", bootloader_cmd)
+
+    # Because the Command always returns a NodeList, we have to
+    # access the first element in the list to get the Node object
+    # that actually represents the bootloader image.
+    # Also, this file is later used in generic Python code, so the
+    # Node object in converted to a generic string
+    return str(bootloader_cmd[0])
+
+
+def add_tinyuf2_extra_image():
+    tinuf2_image = board_config.get(
+        "upload.arduino.tinyuf2_image",
+        join(variants_dir, board_config.get("build.variant", ""), "tinyuf2.bin"),
+    )
+
+    # Add the UF2 image only if it exists and it's not already added
+    if not isfile(env.subst(tinuf2_image)):
+        print("Warning! The `%s` UF2 bootloader image doesn't exist" % env.subst(tinuf2_image))
+        return
+
+    if any("tinyuf2.bin" == basename(extra_image[1]) for extra_image in env.get("FLASH_EXTRA_IMAGES", [])):
+        print("Warning! An extra UF2 bootloader image is already added!")
+        return
+
+    env.Append(
+        FLASH_EXTRA_IMAGES=[
+            (
+                board_config.get(
+                    "upload.arduino.uf2_bootloader_offset",
+                    ("0x2d0000" if env.subst("$BOARD").startswith("adafruit") else "0x410000"),
+                ),
+                tinuf2_image,
+            ),
+        ]
+    )
+
+
+#
+# Run target-specific script to populate the environment with proper build flags
+#
+
+SConscript(
+    join(
+        FRAMEWORK_LIBS_DIR,
+        build_mcu,
+        "pioarduino-build.py",
+    )
+)
+
+#
+# Additional flags specific to Arduino core (not based on IDF)
+#
+
+env.Append(
+    CFLAGS=["-Werror=return-type"],
+    CXXFLAGS=["-Werror=return-type"],
+)
+
+#
+# Target: Build Core Library
+#
+
+# Set -DARDUINO_CORE_BUILD only for the core library
+corelib_env = env.Clone()
+corelib_env.Append(CPPDEFINES=["ARDUINO_CORE_BUILD"])
+
+libs = []
+
+variants_dir = join(FRAMEWORK_DIR, "variants")
+
+if "build.variants_dir" in board_config:
+    variants_dir = join("$PROJECT_DIR", board_config.get("build.variants_dir"))
+
+if "build.variant" in board_config:
+    env.Append(CPPPATH=[join(variants_dir, board_config.get("build.variant"))])
+    corelib_env.Append(CPPPATH=[join(variants_dir, board_config.get("build.variant"))])
+    corelib_env.BuildSources(
+        join("$BUILD_DIR", "FrameworkArduinoVariant"),
+        join(variants_dir, board_config.get("build.variant")),
+    )
+
+libs.append(
+    corelib_env.BuildLibrary(
+        join("$BUILD_DIR", "FrameworkArduino"),
+        join(FRAMEWORK_DIR, "cores", board_config.get("build.core")),
+    )
+)
+
+env.Prepend(LIBS=libs)
+
+#
+# Process framework extra images
+#
+
+env.Append(
+    LIBSOURCE_DIRS=[join(FRAMEWORK_DIR, "libraries")],
+    FLASH_EXTRA_IMAGES=[
+        (
+            "0x1000" if build_mcu in ["esp32", "esp32s2"] else ("0x2000" if build_mcu in ["esp32p4"] else "0x0000"),
+            get_bootloader_image(variants_dir),
+        ),
+        ("0x8000", join(env.subst("$BUILD_DIR"), "partitions.bin")),
+        ("0xe000", join(FRAMEWORK_DIR, "tools", "partitions", "boot_app0.bin")),
+    ]
+    + [(offset, join(FRAMEWORK_DIR, img)) for offset, img in board_config.get("upload.arduino.flash_extra_images", [])],
+)
+
+# Add an extra UF2 image if the 'TinyUF2' partition is selected
+if partitions_name.endswith("tinyuf2.csv") or board_config.get("upload.arduino.tinyuf2_image", ""):
+    add_tinyuf2_extra_image()
+
+#
+# Generate partition table
+#
+
+env.Replace(PARTITIONS_TABLE_CSV=get_partition_table_csv(variants_dir))
+
+partition_table = env.Command(
+    join("$BUILD_DIR", "partitions.bin"),
+    "$PARTITIONS_TABLE_CSV",
+    env.VerboseAction(
+        '"$PYTHONEXE" "%s" -q $SOURCE $TARGET' % join(FRAMEWORK_DIR, "tools", "gen_esp32part.py"),
+        "Generating partitions $TARGET",
+    ),
+)
+env.Depends("$BUILD_DIR/$PROGNAME$PROGSUFFIX", partition_table)
+
+#
+#  Adjust the `esptoolpy` command in the `ElfToBin` builder with firmware checksum offset
+#
+
+action = deepcopy(env["BUILDERS"]["ElfToBin"].action)
+action.cmd_list = env["BUILDERS"]["ElfToBin"].action.cmd_list.replace("-o", "--elf-sha256-offset 0xb0 -o")
+env["BUILDERS"]["ElfToBin"].action = action
diff --git a/tools/platformio-build.py b/tools/platformio-build.py
deleted file mode 100644
index 209391569c0..00000000000
--- a/tools/platformio-build.py
+++ /dev/null
@@ -1,239 +0,0 @@
-# Copyright 2014-present PlatformIO <contact@platformio.org>
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-
-"""
-Arduino
-
-Arduino Wiring-based Framework allows writing cross-platform software to
-control devices attached to a wide range of Arduino boards to create all
-kinds of creative coding, interactive objects, spaces or physical experiences.
-
-http://arduino.cc/en/Reference/HomePage
-"""
-
-# Extends: https://github.com/platformio/platform-espressif32/blob/develop/builder/main.py
-
-from os.path import abspath, isdir, isfile, join
-
-from SCons.Script import DefaultEnvironment
-
-env = DefaultEnvironment()
-platform = env.PioPlatform()
-
-FRAMEWORK_DIR = platform.get_package_dir("framework-arduinoespressif32")
-assert isdir(FRAMEWORK_DIR)
-
-env.Append(
-    ASFLAGS=["-x", "assembler-with-cpp", "-mlongcalls"],
-
-    CFLAGS=[
-        "-std=gnu99",
-        "-Wno-old-style-declaration"
-    ],
-
-    CCFLAGS=[
-        "-Os",
-        "-g3",
-        "-Wall",
-        "-nostdlib",
-        "-Wpointer-arith",
-        "-Wno-error=unused-but-set-variable",
-        "-Wno-error=unused-variable",
-        "-mlongcalls",
-        "-ffunction-sections",
-        "-fdata-sections",
-        "-fstrict-volatile-bitfields",
-        "-Wno-error=deprecated-declarations",
-        "-Wno-error=unused-function",
-        "-Wno-unused-parameter",
-        "-Wno-sign-compare",
-        "-fstack-protector",
-        "-fexceptions",
-        "-Werror=reorder"
-    ],
-
-    CXXFLAGS=[
-        "-fno-rtti",
-        "-fno-exceptions",
-        "-std=gnu++11"
-    ],
-
-    LINKFLAGS=[
-        "-nostdlib",
-        "-Wl,-static",
-        "-u", "call_user_start_cpu0",
-        "-Wl,--undefined=uxTopUsedPriority",
-        "-Wl,--gc-sections",
-        "-Wl,-EL",
-        "-T", "esp32.project.ld",
-        "-T", "esp32.rom.ld",
-        "-T", "esp32.peripherals.ld",
-        "-T", "esp32.rom.libgcc.ld",
-        "-T", "esp32.rom.spiram_incompatible_fns.ld",
-        "-u", "ld_include_panic_highint_hdl",
-        "-u", "__cxa_guard_dummy",
-        "-u", "__cxx_fatal_exception"
-    ],
-
-    CPPDEFINES=[
-        "ESP32",
-        "ESP_PLATFORM",
-        ("F_CPU", "$BOARD_F_CPU"),
-        "HAVE_CONFIG_H",
-        ("MBEDTLS_CONFIG_FILE", '\\"mbedtls/esp_config.h\\"'),
-        ("ARDUINO", 10805),
-        "ARDUINO_ARCH_ESP32",
-        ("ARDUINO_VARIANT", '\\"%s\\"' % env.BoardConfig().get("build.variant").replace('"', "")),
-        ("ARDUINO_BOARD", '\\"%s\\"' % env.BoardConfig().get("name").replace('"', ""))
-    ],
-
-    CPPPATH=[
-       join(FRAMEWORK_DIR, "tools", "sdk", "include", "config"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "app_trace"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "app_update"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "asio"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "bootloader_support"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "bt"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "coap"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "console"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "driver"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "efuse"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp-tls"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp32"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp_adc_cal"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp_event"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp_http_client"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp_http_server"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp_https_ota"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp_https_server"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp_ringbuf"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp_websocket_client"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "espcoredump"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "ethernet"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "expat"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "fatfs"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "freemodbus"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "freertos"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "heap"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "idf_test"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "jsmn"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "json"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "libsodium"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "log"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "lwip"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "mbedtls"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "mdns"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "micro-ecc"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "mqtt"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "newlib"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "nghttp"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "nimble"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "nvs_flash"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "openssl"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "protobuf-c"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "protocomm"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "pthread"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "sdmmc"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "smartconfig_ack"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "soc"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "spi_flash"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "spiffs"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "tcp_transport"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "tcpip_adapter"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "ulp"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "unity"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "vfs"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "wear_levelling"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "wifi_provisioning"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "wpa_supplicant"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "xtensa-debug-module"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp-face"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp32-camera"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "esp-face"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "include", "fb_gfx"),
-        join(FRAMEWORK_DIR, "cores", env.BoardConfig().get("build.core"))
-    ],
-
-    LIBPATH=[
-        join(FRAMEWORK_DIR, "tools", "sdk", "lib"),
-        join(FRAMEWORK_DIR, "tools", "sdk", "ld")
-    ],
-
-    LIBS=[
-        "-lgcc", "-lopenssl", "-lbtdm_app", "-lfatfs", "-lwps", "-lcoexist", "-lwear_levelling", "-lesp_http_client", "-lprotobuf-c", "-lhal", "-lnewlib", "-ldriver", "-lbootloader_support", "-lpp", "-lfreemodbus", "-lmesh", "-lsmartconfig", "-ljsmn", "-lwpa", "-lethernet", "-lphy", "-lapp_trace", "-lconsole", "-lulp", "-lwpa_supplicant", "-lfreertos", "-lbt", "-lmicro-ecc", "-lesp32-camera", "-lcxx", "-lxtensa-debug-module", "-ltcp_transport", "-lod", "-lmdns", "-ldetection", "-lvfs", "-lpe", "-lesp_websocket_client", "-lespcoredump", "-lesp_ringbuf", "-lsoc", "-lcore", "-lfb_gfx", "-lsdmmc", "-llibsodium", "-lcoap", "-ltcpip_adapter", "-lprotocomm", "-lesp_event", "-limage_util", "-lc_nano", "-lesp-tls", "-lasio", "-lrtc", "-lspi_flash", "-lwpa2", "-lwifi_provisioning", "-lesp32", "-lface_recognition", "-lapp_update", "-lnghttp", "-ldl", "-lspiffs", "-lface_detection", "-lefuse", "-lunity", "-lesp_https_server", "-lespnow", "-lnvs_flash", "-lesp_adc_cal", "-llog", "-ldetection_cat_face", "-lsmartconfig_ack", "-lexpat", "-lm", "-lfr", "-lmqtt", "-lc", "-lheap", "-lmbedtls", "-llwip", "-lnet80211", "-lesp_http_server", "-lpthread", "-ljson", "-lesp_https_ota", "-lfd", "-lstdc++"
-    ],
-
-    LIBSOURCE_DIRS=[
-        join(FRAMEWORK_DIR, "libraries")
-    ],
-
-    FLASH_EXTRA_IMAGES=[
-        ("0x1000", join(FRAMEWORK_DIR, "tools", "sdk", "bin", "bootloader_${BOARD_FLASH_MODE}_${__get_board_f_flash(__env__)}.bin")),
-        ("0x8000", join(env.subst("$BUILD_DIR"), "partitions.bin")),
-        ("0xe000", join(FRAMEWORK_DIR, "tools", "partitions", "boot_app0.bin"))
-    ]
-)
-
-if not env.BoardConfig().get("build.ldscript", ""):
-    env.Replace(LDSCRIPT_PATH=env.BoardConfig().get("build.arduino.ldscript", ""))
-
-#
-# Target: Build Core Library
-#
-
-libs = []
-
-variants_dir = join(FRAMEWORK_DIR, "variants")
-
-if "build.variants_dir" in env.BoardConfig():
-    variants_dir = join("$PROJECT_DIR", env.BoardConfig().get("build.variants_dir"))
-
-if "build.variant" in env.BoardConfig():
-    env.Append(
-        CPPPATH=[
-            join(variants_dir, env.BoardConfig().get("build.variant"))
-        ]
-    )
-    libs.append(env.BuildLibrary(
-        join("$BUILD_DIR", "FrameworkArduinoVariant"),
-        join(variants_dir, env.BoardConfig().get("build.variant"))
-    ))
-
-envsafe = env.Clone()
-
-libs.append(envsafe.BuildLibrary(
-    join("$BUILD_DIR", "FrameworkArduino"),
-    join(FRAMEWORK_DIR, "cores", env.BoardConfig().get("build.core"))
-))
-
-env.Prepend(LIBS=libs)
-
-#
-# Generate partition table
-#
-
-fwpartitions_dir = join(FRAMEWORK_DIR, "tools", "partitions")
-partitions_csv = env.BoardConfig().get("build.partitions", "default.csv")
-env.Replace(
-    PARTITIONS_TABLE_CSV=abspath(
-        join(fwpartitions_dir, partitions_csv) if isfile(
-            join(fwpartitions_dir, partitions_csv)) else partitions_csv))
-
-partition_table = env.Command(
-    join("$BUILD_DIR", "partitions.bin"),
-    "$PARTITIONS_TABLE_CSV",
-    env.VerboseAction('"$PYTHONEXE" "%s" -q $SOURCE $TARGET' % join(
-        FRAMEWORK_DIR, "tools", "gen_esp32part.py"),
-                      "Generating partitions $TARGET"))
-env.Depends("$BUILD_DIR/$PROGNAME$PROGSUFFIX", partition_table)
diff --git a/tools/pre-commit/requirements.txt b/tools/pre-commit/requirements.txt
new file mode 100644
index 00000000000..aca4a61191f
--- /dev/null
+++ b/tools/pre-commit/requirements.txt
@@ -0,0 +1,2 @@
+pre-commit==4.0.1
+docutils==0.16
diff --git a/tools/sdk/bin/bootloader_dio_40m.bin b/tools/sdk/bin/bootloader_dio_40m.bin
deleted file mode 100644
index f2d94dc3c8f..00000000000
Binary files a/tools/sdk/bin/bootloader_dio_40m.bin and /dev/null differ
diff --git a/tools/sdk/bin/bootloader_dio_80m.bin b/tools/sdk/bin/bootloader_dio_80m.bin
deleted file mode 100644
index 0da9aa991fc..00000000000
Binary files a/tools/sdk/bin/bootloader_dio_80m.bin and /dev/null differ
diff --git a/tools/sdk/bin/bootloader_dout_40m.bin b/tools/sdk/bin/bootloader_dout_40m.bin
deleted file mode 100644
index ced40a4d901..00000000000
Binary files a/tools/sdk/bin/bootloader_dout_40m.bin and /dev/null differ
diff --git a/tools/sdk/bin/bootloader_dout_80m.bin b/tools/sdk/bin/bootloader_dout_80m.bin
deleted file mode 100644
index 84920601075..00000000000
Binary files a/tools/sdk/bin/bootloader_dout_80m.bin and /dev/null differ
diff --git a/tools/sdk/bin/bootloader_qio_40m.bin b/tools/sdk/bin/bootloader_qio_40m.bin
deleted file mode 100644
index 8299f444980..00000000000
Binary files a/tools/sdk/bin/bootloader_qio_40m.bin and /dev/null differ
diff --git a/tools/sdk/bin/bootloader_qio_80m.bin b/tools/sdk/bin/bootloader_qio_80m.bin
deleted file mode 100644
index 592e62b417e..00000000000
Binary files a/tools/sdk/bin/bootloader_qio_80m.bin and /dev/null differ
diff --git a/tools/sdk/bin/bootloader_qout_40m.bin b/tools/sdk/bin/bootloader_qout_40m.bin
deleted file mode 100644
index f2d94dc3c8f..00000000000
Binary files a/tools/sdk/bin/bootloader_qout_40m.bin and /dev/null differ
diff --git a/tools/sdk/bin/bootloader_qout_80m.bin b/tools/sdk/bin/bootloader_qout_80m.bin
deleted file mode 100644
index 592e62b417e..00000000000
Binary files a/tools/sdk/bin/bootloader_qout_80m.bin and /dev/null differ
diff --git a/tools/sdk/include/app_trace/esp_app_trace.h b/tools/sdk/include/app_trace/esp_app_trace.h
deleted file mode 100644
index a623ada7fa0..00000000000
--- a/tools/sdk/include/app_trace/esp_app_trace.h
+++ /dev/null
@@ -1,265 +0,0 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef ESP_APP_TRACE_H_
-#define ESP_APP_TRACE_H_
-
-#include <stdarg.h>
-#include "esp_err.h"
-#include "esp_app_trace_util.h" // ESP_APPTRACE_TMO_INFINITE
-
-/**
- * Application trace data destinations bits.
- */
-typedef enum {
-    ESP_APPTRACE_DEST_TRAX = 0x1,	///< JTAG destination
-    ESP_APPTRACE_DEST_UART0 = 0x2,	///< UART destination
-} esp_apptrace_dest_t;
-
-/**
- * @brief  Initializes application tracing module.
- *
- * @note   Should be called before any esp_apptrace_xxx call.
- *
- * @return ESP_OK on success, otherwise see esp_err_t
- */
-esp_err_t esp_apptrace_init();
-
-/**
- * @brief Configures down buffer.
- *        @note Needs to be called before initiating any data transfer using esp_apptrace_buffer_get and esp_apptrace_write.
- *              This function does not protect internal data by lock.
- *
- * @param buf Address of buffer to use for down channel (host to target) data.
- * @param size Size of the buffer.
- */
-void esp_apptrace_down_buffer_config(uint8_t *buf, uint32_t size);
-
-/**
- * @brief Allocates buffer for trace data.
- *        After data in buffer are ready to be sent off esp_apptrace_buffer_put must be called to indicate it.
- *
- * @param dest Indicates HW interface to send data.
- * @param size Size of data to write to trace buffer.
- * @param tmo  Timeout for operation (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinitely.
- *
- * @return non-NULL on success, otherwise NULL.
- */
-uint8_t *esp_apptrace_buffer_get(esp_apptrace_dest_t dest, uint32_t size, uint32_t tmo);
-
-/**
- * @brief Indicates that the data in buffer are ready to be sent off.
- *        This function is a counterpart of and must be preceeded by esp_apptrace_buffer_get.
- *
- * @param dest Indicates HW interface to send data. Should be identical to the same parameter in call to esp_apptrace_buffer_get.
- * @param ptr  Address of trace buffer to release. Should be the value returned by call to esp_apptrace_buffer_get.
- * @param tmo  Timeout for operation (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinitely.
- *
- * @return ESP_OK on success, otherwise see esp_err_t
- */
-esp_err_t esp_apptrace_buffer_put(esp_apptrace_dest_t dest, uint8_t *ptr, uint32_t tmo);
-
-/**
- * @brief  Writes data to trace buffer.
- *
- * @param dest Indicates HW interface to send data.
- * @param data Address of data to write to trace buffer.
- * @param size Size of data to write to trace buffer.
- * @param tmo  Timeout for operation (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinitely.
- *
- * @return ESP_OK on success, otherwise see esp_err_t
- */
-esp_err_t esp_apptrace_write(esp_apptrace_dest_t dest, const void *data, uint32_t size, uint32_t tmo);
-
-/**
- * @brief vprintf-like function to sent log messages to host via specified HW interface.
- *
- * @param dest Indicates HW interface to send data.
- * @param tmo  Timeout for operation (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinitely.
- * @param fmt  Address of format string.
- * @param ap   List of arguments.
- *
- * @return Number of bytes written.
- */
-int esp_apptrace_vprintf_to(esp_apptrace_dest_t dest, uint32_t tmo, const char *fmt, va_list ap);
-
-/**
- * @brief vprintf-like function to sent log messages to host.
- *
- * @param fmt  Address of format string.
- * @param ap   List of arguments.
- *
- * @return Number of bytes written.
- */
-int esp_apptrace_vprintf(const char *fmt, va_list ap);
-
-/**
- * @brief Flushes remaining data in trace buffer to host.
- *
- * @param dest Indicates HW interface to flush data on.
- * @param tmo  Timeout for operation (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinitely.
- *
- * @return ESP_OK on success, otherwise see esp_err_t
- */
-esp_err_t esp_apptrace_flush(esp_apptrace_dest_t dest, uint32_t tmo);
-
-/**
- * @brief Flushes remaining data in trace buffer to host without locking internal data.
- *        This is special version of esp_apptrace_flush which should be called from panic handler.
- *
- * @param dest   Indicates HW interface to flush data on.
- * @param min_sz Threshold for flushing data. If current filling level is above this value, data will be flushed. TRAX destinations only.
- * @param tmo    Timeout for operation (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinitely.
- *
- * @return ESP_OK on success, otherwise see esp_err_t
- */
-esp_err_t esp_apptrace_flush_nolock(esp_apptrace_dest_t dest, uint32_t min_sz, uint32_t tmo);
-
-/**
- * @brief Reads host data from trace buffer.
- *
- * @param dest Indicates HW interface to read the data on.
- * @param data Address of buffer to put data from trace buffer.
- * @param size Pointer to store size of read data. Before call to this function pointed memory must hold requested size of data
- * @param tmo  Timeout for operation (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinitely.
- *
- * @return ESP_OK on success, otherwise see esp_err_t
- */
-esp_err_t esp_apptrace_read(esp_apptrace_dest_t dest, void *data, uint32_t *size, uint32_t tmo);
-
-/**
- * @brief Retrieves incoming data buffer if any.
- *        After data in buffer are processed esp_apptrace_down_buffer_put must be called to indicate it.
- *
- * @param dest Indicates HW interface to receive data.
- * @param size Address to store size of available data in down buffer. Must be initialized with requested value.
- * @param tmo  Timeout for operation (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinitely.
- *
- * @return non-NULL on success, otherwise NULL.
- */
-uint8_t *esp_apptrace_down_buffer_get(esp_apptrace_dest_t dest, uint32_t *size, uint32_t tmo);
-
-/**
- * @brief Indicates that the data in down buffer are processed.
- *        This function is a counterpart of and must be preceeded by esp_apptrace_down_buffer_get.
- *
- * @param dest Indicates HW interface to receive data. Should be identical to the same parameter in call to esp_apptrace_down_buffer_get.
- * @param ptr  Address of trace buffer to release. Should be the value returned by call to esp_apptrace_down_buffer_get.
- * @param tmo  Timeout for operation (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinitely.
- *
- * @return ESP_OK on success, otherwise see esp_err_t
- */
-esp_err_t esp_apptrace_down_buffer_put(esp_apptrace_dest_t dest, uint8_t *ptr, uint32_t tmo);
-
-/**
- * @brief Checks whether host is connected.
- *
- * @param dest Indicates HW interface to use.
- *
- * @return true if host is connected, otherwise false
- */
-bool esp_apptrace_host_is_connected(esp_apptrace_dest_t dest);
-
-/**
- * @brief Opens file on host.
- *		  This function has the same semantic as 'fopen' except for the first argument.
- *
- * @param dest Indicates HW interface to use.
- * @param path Path to file.
- * @param mode Mode string. See fopen for details.
- *
- * @return non zero file handle on success, otherwise 0
- */
-void *esp_apptrace_fopen(esp_apptrace_dest_t dest, const char *path, const char *mode);
-
-/**
- * @brief Closes file on host.
- *		  This function has the same semantic as 'fclose' except for the first argument.
- *
- * @param dest   Indicates HW interface to use.
- * @param stream File handle returned by esp_apptrace_fopen.
- *
- * @return Zero on success, otherwise non-zero. See fclose for details.
- */
-int esp_apptrace_fclose(esp_apptrace_dest_t dest, void *stream);
-
-/**
- * @brief Writes to file on host.
- *		  This function has the same semantic as 'fwrite' except for the first argument.
- *
- * @param dest   Indicates HW interface to use.
- * @param ptr 	 Address of data to write.
- * @param size 	 Size of an item.
- * @param nmemb  Number of items to write.
- * @param stream File handle returned by esp_apptrace_fopen.
- *
- * @return Number of written items. See fwrite for details.
- */
-size_t esp_apptrace_fwrite(esp_apptrace_dest_t dest, const void *ptr, size_t size, size_t nmemb, void *stream);
-
-/**
- * @brief Read file on host.
- *		  This function has the same semantic as 'fread' except for the first argument.
- *
- * @param dest   Indicates HW interface to use.
- * @param ptr 	 Address to store read data.
- * @param size 	 Size of an item.
- * @param nmemb  Number of items to read.
- * @param stream File handle returned by esp_apptrace_fopen.
- *
- * @return Number of read items. See fread for details.
- */
-size_t esp_apptrace_fread(esp_apptrace_dest_t dest, void *ptr, size_t size, size_t nmemb, void *stream);
-
-/**
- * @brief Set position indicator in file on host.
- *		  This function has the same semantic as 'fseek' except for the first argument.
- *
- * @param dest   Indicates HW interface to use.
- * @param stream File handle returned by esp_apptrace_fopen.
- * @param offset Offset. See fseek for details.
- * @param whence Position in file. See fseek for details.
- *
- * @return Zero on success, otherwise non-zero. See fseek for details.
- */
-int esp_apptrace_fseek(esp_apptrace_dest_t dest, void *stream, long offset, int whence);
-
-/**
- * @brief Get current position indicator for file on host.
- *		  This function has the same semantic as 'ftell' except for the first argument.
- *
- * @param dest   Indicates HW interface to use.
- * @param stream File handle returned by esp_apptrace_fopen.
- *
- * @return Current position in file. See ftell for details.
- */
-int esp_apptrace_ftell(esp_apptrace_dest_t dest, void *stream);
-
-/**
- * @brief Indicates to the host that all file operations are completed.
- *		  This function should be called after all file operations are finished and
- *		  indicate to the host that it can perform cleanup operations (close open files etc.).
- *
- * @param dest   Indicates HW interface to use.
- *
- * @return ESP_OK on success, otherwise see esp_err_t
- */
-int esp_apptrace_fstop(esp_apptrace_dest_t dest);
-
-/**
- * @brief Triggers gcov info dump.
- *		  This function waits for the host to connect to target before dumping data.
- */
-void esp_gcov_dump(void);
-
-#endif
diff --git a/tools/sdk/include/app_trace/esp_app_trace_util.h b/tools/sdk/include/app_trace/esp_app_trace_util.h
deleted file mode 100644
index 6376008c2f6..00000000000
--- a/tools/sdk/include/app_trace/esp_app_trace_util.h
+++ /dev/null
@@ -1,167 +0,0 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef ESP_APP_TRACE_UTIL_H_
-#define ESP_APP_TRACE_UTIL_H_
-
-#include "freertos/FreeRTOS.h"
-#include "esp_err.h"
-
-/** Infinite waiting timeout */
-#define ESP_APPTRACE_TMO_INFINITE               ((uint32_t)-1)
-
-/** Structure which holds data necessary for measuring time intervals. 
- *
- *  After initialization via esp_apptrace_tmo_init() user needs to call esp_apptrace_tmo_check()
- *  periodically to check timeout for expiration.
- */
-typedef struct {
-    uint32_t   start;   ///< time interval start (in CPU ticks)
-    uint32_t   tmo;     ///< timeout value (in us)
-    uint32_t   elapsed; ///< elapsed time (in us)
-} esp_apptrace_tmo_t;
-
-/**
- * @brief Initializes timeout structure.
- *
- * @param tmo       Pointer to timeout structure to be initialized.
- * @param user_tmo  Timeout value (in us). Use ESP_APPTRACE_TMO_INFINITE to wait indefinetly.
-*/
-static inline void esp_apptrace_tmo_init(esp_apptrace_tmo_t *tmo, uint32_t user_tmo)
-{
-    tmo->start = portGET_RUN_TIME_COUNTER_VALUE();
-    tmo->tmo = user_tmo;
-    tmo->elapsed = 0;
-}
-
-/**
- * @brief Checks timeout for expiration.
- *
- * @param tmo Pointer to timeout structure to be initialized.
- *
- * @return ESP_OK on success, otherwise \see esp_err_t
- */
-esp_err_t esp_apptrace_tmo_check(esp_apptrace_tmo_t *tmo);
-
-static inline uint32_t esp_apptrace_tmo_remaining_us(esp_apptrace_tmo_t *tmo)
-{
-    return tmo->tmo != ESP_APPTRACE_TMO_INFINITE ? (tmo->elapsed - tmo->tmo) : ESP_APPTRACE_TMO_INFINITE;
-}
-
-/** Tracing module synchronization lock */
-typedef struct {
-    portMUX_TYPE mux;
-    unsigned int_state;
-} esp_apptrace_lock_t;
-
-/**
- * @brief Initializes lock structure.
- *
- * @param lock Pointer to lock structure to be initialized.
- */
-static inline void esp_apptrace_lock_init(esp_apptrace_lock_t *lock)
-{
-    vPortCPUInitializeMutex(&lock->mux);
-    lock->int_state = 0;
-}
-
-/**
- * @brief Tries to acquire lock in specified time period.
- *
- * @param lock Pointer to lock structure.
- * @param tmo  Pointer to timeout struct.
- *
- * @return ESP_OK on success, otherwise \see esp_err_t
- */
-esp_err_t esp_apptrace_lock_take(esp_apptrace_lock_t *lock, esp_apptrace_tmo_t *tmo);
-
-/**
- * @brief Releases lock.
- *
- * @param lock Pointer to lock structure.
- *
- * @return ESP_OK on success, otherwise \see esp_err_t
- */
-esp_err_t esp_apptrace_lock_give(esp_apptrace_lock_t *lock);
-
-/** Ring buffer control structure.
- *
- * @note For purposes of application tracing module if there is no enough space for user data and write pointer can be wrapped 
- *       current ring buffer size can be temporarily shrinked in order to provide buffer with requested size.
- */
-typedef struct {
-    uint8_t *data;      ///< pointer to data storage
-    volatile uint32_t size;      ///< size of data storage
-    volatile uint32_t cur_size;  ///< current size of data storage
-    volatile uint32_t rd;        ///< read pointer
-    volatile uint32_t wr;        ///< write pointer
-} esp_apptrace_rb_t;
-
-/**
- * @brief Initializes ring buffer control  structure.
- *
- * @param rb   Pointer to ring buffer structure to be initialized.
- * @param data Pointer to buffer to be used as ring buffer's data storage.
- * @param size Size of buffer to be used as ring buffer's data storage.
- */
-static inline void esp_apptrace_rb_init(esp_apptrace_rb_t *rb, uint8_t *data, uint32_t size)
-{
-    rb->data = data;
-    rb->size = rb->cur_size = size;
-    rb->rd = 0;
-    rb->wr = 0;
-}
-
-/**
- * @brief Allocates memory chunk in ring buffer.
- *
- * @param rb   Pointer to ring buffer structure.
- * @param size Size of the memory to allocate.
- *
- * @return Pointer to the allocated memory or NULL in case of failure.
- */
-uint8_t *esp_apptrace_rb_produce(esp_apptrace_rb_t *rb, uint32_t size);
-
-/**
- * @brief Consumes memory chunk in ring buffer.
- *
- * @param rb   Pointer to ring buffer structure.
- * @param size Size of the memory to consume.
- *
- * @return Pointer to consumed memory chunk or NULL in case of failure.
- */
-uint8_t *esp_apptrace_rb_consume(esp_apptrace_rb_t *rb, uint32_t size);
-
-/**
- * @brief Gets size of memory which can consumed with single call to esp_apptrace_rb_consume().
- *
- * @param rb Pointer to ring buffer structure.
- *
- * @return Size of memory which can consumed.
- *
- * @note Due to read pointer wrapping returned size can be less then the total size of available data.
- */
-uint32_t esp_apptrace_rb_read_size_get(esp_apptrace_rb_t *rb);
-
-/**
- * @brief Gets size of memory which can produced with single call to esp_apptrace_rb_produce().
- *
- * @param rb Pointer to ring buffer structure.
- *
- * @return Size of memory which can produced.
- *
- * @note Due to write pointer wrapping returned size can be less then the total size of available data.
- */
-uint32_t esp_apptrace_rb_write_size_get(esp_apptrace_rb_t *rb);
-
-#endif //ESP_APP_TRACE_UTIL_H_
diff --git a/tools/sdk/include/app_update/esp_ota_ops.h b/tools/sdk/include/app_update/esp_ota_ops.h
deleted file mode 100644
index 635144638dd..00000000000
--- a/tools/sdk/include/app_update/esp_ota_ops.h
+++ /dev/null
@@ -1,283 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _OTA_OPS_H
-#define _OTA_OPS_H
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include "esp_err.h"
-#include "esp_partition.h"
-#include "esp_image_format.h"
-#include "esp_flash_data_types.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#define OTA_SIZE_UNKNOWN 0xffffffff /*!< Used for esp_ota_begin() if new image size is unknown */
-
-#define ESP_ERR_OTA_BASE                         0x1500                     /*!< Base error code for ota_ops api */
-#define ESP_ERR_OTA_PARTITION_CONFLICT           (ESP_ERR_OTA_BASE + 0x01)  /*!< Error if request was to write or erase the current running partition */
-#define ESP_ERR_OTA_SELECT_INFO_INVALID          (ESP_ERR_OTA_BASE + 0x02)  /*!< Error if OTA data partition contains invalid content */
-#define ESP_ERR_OTA_VALIDATE_FAILED              (ESP_ERR_OTA_BASE + 0x03)  /*!< Error if OTA app image is invalid */
-#define ESP_ERR_OTA_SMALL_SEC_VER                (ESP_ERR_OTA_BASE + 0x04)  /*!< Error if the firmware has a secure version less than the running firmware. */
-#define ESP_ERR_OTA_ROLLBACK_FAILED              (ESP_ERR_OTA_BASE + 0x05)  /*!< Error if flash does not have valid firmware in passive partition and hence rollback is not possible */
-#define ESP_ERR_OTA_ROLLBACK_INVALID_STATE       (ESP_ERR_OTA_BASE + 0x06)  /*!< Error if current active firmware is still marked in pending validation state (ESP_OTA_IMG_PENDING_VERIFY), essentially first boot of firmware image post upgrade and hence firmware upgrade is not possible */
-
-
-/**
- * @brief Opaque handle for an application OTA update
- *
- * esp_ota_begin() returns a handle which is then used for subsequent
- * calls to esp_ota_write() and esp_ota_end().
- */
-typedef uint32_t esp_ota_handle_t;
-
-/**
- * @brief   Return esp_app_desc structure. This structure includes app version.
- * 
- * Return description for running app.
- * @return Pointer to esp_app_desc structure.
- */
-const esp_app_desc_t *esp_ota_get_app_description(void);
-
-/**
- * @brief   Fill the provided buffer with SHA256 of the ELF file, formatted as hexadecimal, null-terminated.
- * If the buffer size is not sufficient to fit the entire SHA256 in hex plus a null terminator,
- * the largest possible number of bytes will be written followed by a null.
- * @param dst   Destination buffer
- * @param size  Size of the buffer
- * @return      Number of bytes written to dst (including null terminator)
- */
-int esp_ota_get_app_elf_sha256(char* dst, size_t size);
-
-/**
- * @brief   Commence an OTA update writing to the specified partition.
-
- * The specified partition is erased to the specified image size.
- *
- * If image size is not yet known, pass OTA_SIZE_UNKNOWN which will
- * cause the entire partition to be erased.
- *
- * On success, this function allocates memory that remains in use
- * until esp_ota_end() is called with the returned handle.
- *
- * Note: If the rollback option is enabled and the running application has the ESP_OTA_IMG_PENDING_VERIFY state then
- * it will lead to the ESP_ERR_OTA_ROLLBACK_INVALID_STATE error. Confirm the running app before to run download a new app,
- * use esp_ota_mark_app_valid_cancel_rollback() function for it (this should be done as early as possible when you first download a new application).
- *
- * @param partition Pointer to info for partition which will receive the OTA update. Required.
- * @param image_size Size of new OTA app image. Partition will be erased in order to receive this size of image. If 0 or OTA_SIZE_UNKNOWN, the entire partition is erased.
- * @param out_handle On success, returns a handle which should be used for subsequent esp_ota_write() and esp_ota_end() calls.
-
- * @return
- *    - ESP_OK: OTA operation commenced successfully.
- *    - ESP_ERR_INVALID_ARG: partition or out_handle arguments were NULL, or partition doesn't point to an OTA app partition.
- *    - ESP_ERR_NO_MEM: Cannot allocate memory for OTA operation.
- *    - ESP_ERR_OTA_PARTITION_CONFLICT: Partition holds the currently running firmware, cannot update in place.
- *    - ESP_ERR_NOT_FOUND: Partition argument not found in partition table.
- *    - ESP_ERR_OTA_SELECT_INFO_INVALID: The OTA data partition contains invalid data.
- *    - ESP_ERR_INVALID_SIZE: Partition doesn't fit in configured flash size.
- *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
- *    - ESP_ERR_OTA_ROLLBACK_INVALID_STATE: If the running app has not confirmed state. Before performing an update, the application must be valid.
- */
-esp_err_t esp_ota_begin(const esp_partition_t* partition, size_t image_size, esp_ota_handle_t* out_handle);
-
-/**
- * @brief   Write OTA update data to partition
- *
- * This function can be called multiple times as
- * data is received during the OTA operation. Data is written
- * sequentially to the partition.
- *
- * @param handle  Handle obtained from esp_ota_begin
- * @param data    Data buffer to write
- * @param size    Size of data buffer in bytes.
- *
- * @return
- *    - ESP_OK: Data was written to flash successfully.
- *    - ESP_ERR_INVALID_ARG: handle is invalid.
- *    - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid app image magic byte.
- *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
- *    - ESP_ERR_OTA_SELECT_INFO_INVALID: OTA data partition has invalid contents
- */
-esp_err_t esp_ota_write(esp_ota_handle_t handle, const void* data, size_t size);
-
-/**
- * @brief Finish OTA update and validate newly written app image.
- *
- * @param handle  Handle obtained from esp_ota_begin().
- *
- * @note After calling esp_ota_end(), the handle is no longer valid and any memory associated with it is freed (regardless of result).
- *
- * @return
- *    - ESP_OK: Newly written OTA app image is valid.
- *    - ESP_ERR_NOT_FOUND: OTA handle was not found.
- *    - ESP_ERR_INVALID_ARG: Handle was never written to.
- *    - ESP_ERR_OTA_VALIDATE_FAILED: OTA image is invalid (either not a valid app image, or - if secure boot is enabled - signature failed to verify.)
- *    - ESP_ERR_INVALID_STATE: If flash encryption is enabled, this result indicates an internal error writing the final encrypted bytes to flash.
- */
-esp_err_t esp_ota_end(esp_ota_handle_t handle);
-
-/**
- * @brief Configure OTA data for a new boot partition
- *
- * @note If this function returns ESP_OK, calling esp_restart() will boot the newly configured app partition.
- *
- * @param partition Pointer to info for partition containing app image to boot.
- *
- * @return
- *    - ESP_OK: OTA data updated, next reboot will use specified partition.
- *    - ESP_ERR_INVALID_ARG: partition argument was NULL or didn't point to a valid OTA partition of type "app".
- *    - ESP_ERR_OTA_VALIDATE_FAILED: Partition contained invalid app image. Also returned if secure boot is enabled and signature validation failed.
- *    - ESP_ERR_NOT_FOUND: OTA data partition not found.
- *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash erase or write failed.
- */
-esp_err_t esp_ota_set_boot_partition(const esp_partition_t* partition);
-
-/**
- * @brief Get partition info of currently configured boot app
- *
- * If esp_ota_set_boot_partition() has been called, the partition which was set by that function will be returned.
- *
- * If esp_ota_set_boot_partition() has not been called, the result is usually the same as esp_ota_get_running_partition().
- * The two results are not equal if the configured boot partition does not contain a valid app (meaning that the running partition
- * will be an app that the bootloader chose via fallback).
- *
- * If the OTA data partition is not present or not valid then the result is the first app partition found in the
- * partition table. In priority order, this means: the factory app, the first OTA app slot, or the test app partition.
- *
- * Note that there is no guarantee the returned partition is a valid app. Use esp_image_verify(ESP_IMAGE_VERIFY, ...) to verify if the
- * returned partition contains a bootable image.
- *
- * @return Pointer to info for partition structure, or NULL if partition table is invalid or a flash read operation failed. Any returned pointer is valid for the lifetime of the application.
- */
-const esp_partition_t* esp_ota_get_boot_partition(void);
-
-
-/**
- * @brief Get partition info of currently running app
- *
- * This function is different to esp_ota_get_boot_partition() in that
- * it ignores any change of selected boot partition caused by
- * esp_ota_set_boot_partition(). Only the app whose code is currently
- * running will have its partition information returned.
- *
- * The partition returned by this function may also differ from esp_ota_get_boot_partition() if the configured boot
- * partition is somehow invalid, and the bootloader fell back to a different app partition at boot.
- *
- * @return Pointer to info for partition structure, or NULL if no partition is found or flash read operation failed. Returned pointer is valid for the lifetime of the application.
- */
-const esp_partition_t* esp_ota_get_running_partition(void);
-
-
-/**
- * @brief Return the next OTA app partition which should be written with a new firmware.
- *
- * Call this function to find an OTA app partition which can be passed to esp_ota_begin().
- *
- * Finds next partition round-robin, starting from the current running partition.
- *
- * @param start_from If set, treat this partition info as describing the current running partition. Can be NULL, in which case esp_ota_get_running_partition() is used to find the currently running partition. The result of this function is never the same as this argument.
- *
- * @return Pointer to info for partition which should be updated next. NULL result indicates invalid OTA data partition, or that no eligible OTA app slot partition was found.
- *
- */
-const esp_partition_t* esp_ota_get_next_update_partition(const esp_partition_t *start_from);
-
-/**
- * @brief Returns esp_app_desc structure for app partition. This structure includes app version.
- * 
- * Returns a description for the requested app partition.
- * @param[in] partition     Pointer to app partition. (only app partition)
- * @param[out] app_desc     Structure of info about app.
- * @return
- *  - ESP_OK                Successful.
- *  - ESP_ERR_NOT_FOUND     app_desc structure is not found. Magic word is incorrect.
- *  - ESP_ERR_NOT_SUPPORTED Partition is not application.
- *  - ESP_ERR_INVALID_ARG   Arguments is NULL or if partition's offset exceeds partition size.
- *  - ESP_ERR_INVALID_SIZE  Read would go out of bounds of the partition.
- *  - or one of error codes from lower-level flash driver.
- */
-esp_err_t esp_ota_get_partition_description(const esp_partition_t *partition, esp_app_desc_t *app_desc);
-
-/**
- * @brief This function is called to indicate that the running app is working well.
- *
- * @return
- *  - ESP_OK: if successful.
- */
-esp_err_t esp_ota_mark_app_valid_cancel_rollback();
-
-/**
- * @brief This function is called to roll back to the previously workable app with reboot.
- *
- * If rollback is successful then device will reset else API will return with error code.
- * Checks applications on a flash drive that can be booted in case of rollback.
- * If the flash does not have at least one app (except the running app) then rollback is not possible.
- * @return
- *  - ESP_FAIL: if not successful.
- *  - ESP_ERR_OTA_ROLLBACK_FAILED: The rollback is not possible due to flash does not have any apps.
- */
-esp_err_t esp_ota_mark_app_invalid_rollback_and_reboot();
-
-/**
- * @brief Returns last partition with invalid state (ESP_OTA_IMG_INVALID or ESP_OTA_IMG_ABORTED).
- *
- * @return partition.
- */
-const esp_partition_t* esp_ota_get_last_invalid_partition();
-
-/**
- * @brief Returns state for given partition.
- *
- * @param[in] partition  Pointer to partition.
- * @param[out] ota_state state of partition (if this partition has a record in otadata).
- * @return
- *        - ESP_OK:                 Successful.
- *        - ESP_ERR_INVALID_ARG:    partition or ota_state arguments were NULL.
- *        - ESP_ERR_NOT_SUPPORTED:  partition is not ota.
- *        - ESP_ERR_NOT_FOUND:      Partition table does not have otadata or state was not found for given partition.
- */
-esp_err_t esp_ota_get_state_partition(const esp_partition_t *partition, esp_ota_img_states_t *ota_state);
-
-/**
- * @brief Erase previous boot app partition and corresponding otadata select for this partition.
- *
- * When current app is marked to as valid then you can erase previous app partition.
- * @return
- *        - ESP_OK:   Successful, otherwise ESP_ERR.
- */
-esp_err_t esp_ota_erase_last_boot_app_partition(void);
-
-/**
- * @brief Checks applications on the slots which can be booted in case of rollback.
- *
- * These applications should be valid (marked in otadata as not UNDEFINED, INVALID or ABORTED and crc is good) and be able booted,
- * and secure_version of app >= secure_version of efuse (if anti-rollback is enabled).
- *
- * @return
- *        - True: Returns true if the slots have at least one app (except the running app).
- *        - False: The rollback is not possible.
- */
-bool esp_ota_check_rollback_is_possible(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* OTA_OPS_H */
diff --git a/tools/sdk/include/asio/asio.hpp b/tools/sdk/include/asio/asio.hpp
deleted file mode 100644
index 6a58006b6ed..00000000000
--- a/tools/sdk/include/asio/asio.hpp
+++ /dev/null
@@ -1,156 +0,0 @@
-//
-// asio.hpp
-// ~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_HPP
-#define ASIO_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#if defined(ESP_PLATFORM)
-# include "esp_asio_config.h"
-#endif // defined(ESP_PLATFORM)
-
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/async_result.hpp"
-#include "asio/basic_datagram_socket.hpp"
-#include "asio/basic_deadline_timer.hpp"
-#include "asio/basic_io_object.hpp"
-#include "asio/basic_raw_socket.hpp"
-#include "asio/basic_seq_packet_socket.hpp"
-#include "asio/basic_serial_port.hpp"
-#include "asio/basic_signal_set.hpp"
-#include "asio/basic_socket_acceptor.hpp"
-#include "asio/basic_socket_iostream.hpp"
-#include "asio/basic_socket_streambuf.hpp"
-#include "asio/basic_stream_socket.hpp"
-#include "asio/basic_streambuf.hpp"
-#include "asio/basic_waitable_timer.hpp"
-#include "asio/bind_executor.hpp"
-#include "asio/buffer.hpp"
-#include "asio/buffered_read_stream_fwd.hpp"
-#include "asio/buffered_read_stream.hpp"
-#include "asio/buffered_stream_fwd.hpp"
-#include "asio/buffered_stream.hpp"
-#include "asio/buffered_write_stream_fwd.hpp"
-#include "asio/buffered_write_stream.hpp"
-#include "asio/buffers_iterator.hpp"
-#include "asio/completion_condition.hpp"
-#include "asio/connect.hpp"
-#include "asio/coroutine.hpp"
-#include "asio/datagram_socket_service.hpp"
-#include "asio/deadline_timer_service.hpp"
-#include "asio/deadline_timer.hpp"
-#include "asio/defer.hpp"
-#include "asio/dispatch.hpp"
-#include "asio/error.hpp"
-#include "asio/error_code.hpp"
-#include "asio/execution_context.hpp"
-#include "asio/executor.hpp"
-#include "asio/executor_work_guard.hpp"
-#include "asio/generic/basic_endpoint.hpp"
-#include "asio/generic/datagram_protocol.hpp"
-#include "asio/generic/raw_protocol.hpp"
-#include "asio/generic/seq_packet_protocol.hpp"
-#include "asio/generic/stream_protocol.hpp"
-#include "asio/handler_alloc_hook.hpp"
-#include "asio/handler_continuation_hook.hpp"
-#include "asio/handler_invoke_hook.hpp"
-#include "asio/handler_type.hpp"
-#include "asio/high_resolution_timer.hpp"
-#include "asio/io_context.hpp"
-#include "asio/io_context_strand.hpp"
-#include "asio/io_service.hpp"
-#include "asio/io_service_strand.hpp"
-#include "asio/ip/address.hpp"
-#include "asio/ip/address_v4.hpp"
-#include "asio/ip/address_v4_iterator.hpp"
-#include "asio/ip/address_v4_range.hpp"
-#include "asio/ip/address_v6.hpp"
-#include "asio/ip/address_v6_iterator.hpp"
-#include "asio/ip/address_v6_range.hpp"
-#include "asio/ip/bad_address_cast.hpp"
-#include "asio/ip/basic_endpoint.hpp"
-#include "asio/ip/basic_resolver.hpp"
-#include "asio/ip/basic_resolver_entry.hpp"
-#include "asio/ip/basic_resolver_iterator.hpp"
-#include "asio/ip/basic_resolver_query.hpp"
-#include "asio/ip/host_name.hpp"
-#include "asio/ip/icmp.hpp"
-#include "asio/ip/multicast.hpp"
-#include "asio/ip/resolver_base.hpp"
-#include "asio/ip/resolver_query_base.hpp"
-#include "asio/ip/resolver_service.hpp"
-#include "asio/ip/tcp.hpp"
-#include "asio/ip/udp.hpp"
-#include "asio/ip/unicast.hpp"
-#include "asio/ip/v6_only.hpp"
-#include "asio/is_executor.hpp"
-#include "asio/is_read_buffered.hpp"
-#include "asio/is_write_buffered.hpp"
-#include "asio/local/basic_endpoint.hpp"
-#include "asio/local/connect_pair.hpp"
-#include "asio/local/datagram_protocol.hpp"
-#include "asio/local/stream_protocol.hpp"
-#include "asio/packaged_task.hpp"
-#include "asio/placeholders.hpp"
-#include "asio/posix/basic_descriptor.hpp"
-#include "asio/posix/basic_stream_descriptor.hpp"
-#include "asio/posix/descriptor.hpp"
-#include "asio/posix/descriptor_base.hpp"
-#include "asio/posix/stream_descriptor.hpp"
-#include "asio/posix/stream_descriptor_service.hpp"
-#include "asio/post.hpp"
-#include "asio/raw_socket_service.hpp"
-#include "asio/read.hpp"
-#include "asio/read_at.hpp"
-#include "asio/read_until.hpp"
-#include "asio/seq_packet_socket_service.hpp"
-#include "asio/serial_port.hpp"
-#include "asio/serial_port_base.hpp"
-#include "asio/serial_port_service.hpp"
-#include "asio/signal_set.hpp"
-#include "asio/signal_set_service.hpp"
-#include "asio/socket_acceptor_service.hpp"
-#include "asio/socket_base.hpp"
-#include "asio/steady_timer.hpp"
-#include "asio/strand.hpp"
-#include "asio/stream_socket_service.hpp"
-#include "asio/streambuf.hpp"
-#include "asio/system_context.hpp"
-#include "asio/system_error.hpp"
-#include "asio/system_executor.hpp"
-#include "asio/system_timer.hpp"
-#include "asio/thread.hpp"
-#include "asio/thread_pool.hpp"
-#include "asio/time_traits.hpp"
-#include "asio/use_future.hpp"
-#include "asio/uses_executor.hpp"
-#include "asio/version.hpp"
-#include "asio/wait_traits.hpp"
-#include "asio/waitable_timer_service.hpp"
-#include "asio/windows/basic_handle.hpp"
-#include "asio/windows/basic_object_handle.hpp"
-#include "asio/windows/basic_random_access_handle.hpp"
-#include "asio/windows/basic_stream_handle.hpp"
-#include "asio/windows/object_handle.hpp"
-#include "asio/windows/object_handle_service.hpp"
-#include "asio/windows/overlapped_handle.hpp"
-#include "asio/windows/overlapped_ptr.hpp"
-#include "asio/windows/random_access_handle.hpp"
-#include "asio/windows/random_access_handle_service.hpp"
-#include "asio/windows/stream_handle.hpp"
-#include "asio/windows/stream_handle_service.hpp"
-#include "asio/write.hpp"
-#include "asio/write_at.hpp"
-
-#endif // ASIO_HPP
diff --git a/tools/sdk/include/asio/asio/associated_allocator.hpp b/tools/sdk/include/asio/asio/associated_allocator.hpp
deleted file mode 100644
index 8b488bb344e..00000000000
--- a/tools/sdk/include/asio/asio/associated_allocator.hpp
+++ /dev/null
@@ -1,131 +0,0 @@
-//
-// associated_allocator.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_ASSOCIATED_ALLOCATOR_HPP
-#define ASIO_ASSOCIATED_ALLOCATOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <memory>
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename>
-struct associated_allocator_check
-{
-  typedef void type;
-};
-
-template <typename T, typename E, typename = void>
-struct associated_allocator_impl
-{
-  typedef E type;
-
-  static type get(const T&, const E& e) ASIO_NOEXCEPT
-  {
-    return e;
-  }
-};
-
-template <typename T, typename E>
-struct associated_allocator_impl<T, E,
-  typename associated_allocator_check<typename T::allocator_type>::type>
-{
-  typedef typename T::allocator_type type;
-
-  static type get(const T& t, const E&) ASIO_NOEXCEPT
-  {
-    return t.get_allocator();
-  }
-};
-
-} // namespace detail
-
-/// Traits type used to obtain the allocator associated with an object.
-/**
- * A program may specialise this traits type if the @c T template parameter in
- * the specialisation is a user-defined type. The template parameter @c
- * Allocator shall be a type meeting the Allocator requirements.
- *
- * Specialisations shall meet the following requirements, where @c t is a const
- * reference to an object of type @c T, and @c a is an object of type @c
- * Allocator.
- *
- * @li Provide a nested typedef @c type that identifies a type meeting the
- * Allocator requirements.
- *
- * @li Provide a noexcept static member function named @c get, callable as @c
- * get(t) and with return type @c type.
- *
- * @li Provide a noexcept static member function named @c get, callable as @c
- * get(t,a) and with return type @c type.
- */
-template <typename T, typename Allocator = std::allocator<void> >
-struct associated_allocator
-{
-  /// If @c T has a nested type @c allocator_type, <tt>T::allocator_type</tt>.
-  /// Otherwise @c Allocator.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef see_below type;
-#else // defined(GENERATING_DOCUMENTATION)
-  typedef typename detail::associated_allocator_impl<T, Allocator>::type type;
-#endif // defined(GENERATING_DOCUMENTATION)
-
-  /// If @c T has a nested type @c allocator_type, returns
-  /// <tt>t.get_allocator()</tt>. Otherwise returns @c a.
-  static type get(const T& t,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return detail::associated_allocator_impl<T, Allocator>::get(t, a);
-  }
-};
-
-/// Helper function to obtain an object's associated allocator.
-/**
- * @returns <tt>associated_allocator<T>::get(t)</tt>
- */
-template <typename T>
-inline typename associated_allocator<T>::type
-get_associated_allocator(const T& t) ASIO_NOEXCEPT
-{
-  return associated_allocator<T>::get(t);
-}
-
-/// Helper function to obtain an object's associated allocator.
-/**
- * @returns <tt>associated_allocator<T, Allocator>::get(t, a)</tt>
- */
-template <typename T, typename Allocator>
-inline typename associated_allocator<T, Allocator>::type
-get_associated_allocator(const T& t, const Allocator& a) ASIO_NOEXCEPT
-{
-  return associated_allocator<T, Allocator>::get(t, a);
-}
-
-#if defined(ASIO_HAS_ALIAS_TEMPLATES)
-
-template <typename T, typename Allocator = std::allocator<void> >
-using associated_allocator_t
-  = typename associated_allocator<T, Allocator>::type;
-
-#endif // defined(ASIO_HAS_ALIAS_TEMPLATES)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_ASSOCIATED_ALLOCATOR_HPP
diff --git a/tools/sdk/include/asio/asio/associated_executor.hpp b/tools/sdk/include/asio/asio/associated_executor.hpp
deleted file mode 100644
index 4c5c2078848..00000000000
--- a/tools/sdk/include/asio/asio/associated_executor.hpp
+++ /dev/null
@@ -1,149 +0,0 @@
-//
-// associated_executor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_ASSOCIATED_EXECUTOR_HPP
-#define ASIO_ASSOCIATED_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/is_executor.hpp"
-#include "asio/system_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename>
-struct associated_executor_check
-{
-  typedef void type;
-};
-
-template <typename T, typename E, typename = void>
-struct associated_executor_impl
-{
-  typedef E type;
-
-  static type get(const T&, const E& e) ASIO_NOEXCEPT
-  {
-    return e;
-  }
-};
-
-template <typename T, typename E>
-struct associated_executor_impl<T, E,
-  typename associated_executor_check<typename T::executor_type>::type>
-{
-  typedef typename T::executor_type type;
-
-  static type get(const T& t, const E&) ASIO_NOEXCEPT
-  {
-    return t.get_executor();
-  }
-};
-
-} // namespace detail
-
-/// Traits type used to obtain the executor associated with an object.
-/**
- * A program may specialise this traits type if the @c T template parameter in
- * the specialisation is a user-defined type. The template parameter @c
- * Executor shall be a type meeting the Executor requirements.
- *
- * Specialisations shall meet the following requirements, where @c t is a const
- * reference to an object of type @c T, and @c e is an object of type @c
- * Executor.
- *
- * @li Provide a nested typedef @c type that identifies a type meeting the
- * Executor requirements.
- *
- * @li Provide a noexcept static member function named @c get, callable as @c
- * get(t) and with return type @c type.
- *
- * @li Provide a noexcept static member function named @c get, callable as @c
- * get(t,e) and with return type @c type.
- */
-template <typename T, typename Executor = system_executor>
-struct associated_executor
-{
-  /// If @c T has a nested type @c executor_type, <tt>T::executor_type</tt>.
-  /// Otherwise @c Executor.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef see_below type;
-#else // defined(GENERATING_DOCUMENTATION)
-  typedef typename detail::associated_executor_impl<T, Executor>::type type;
-#endif // defined(GENERATING_DOCUMENTATION)
-
-  /// If @c T has a nested type @c executor_type, returns
-  /// <tt>t.get_executor()</tt>. Otherwise returns @c ex.
-  static type get(const T& t,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return detail::associated_executor_impl<T, Executor>::get(t, ex);
-  }
-};
-
-/// Helper function to obtain an object's associated executor.
-/**
- * @returns <tt>associated_executor<T>::get(t)</tt>
- */
-template <typename T>
-inline typename associated_executor<T>::type
-get_associated_executor(const T& t) ASIO_NOEXCEPT
-{
-  return associated_executor<T>::get(t);
-}
-
-/// Helper function to obtain an object's associated executor.
-/**
- * @returns <tt>associated_executor<T, Executor>::get(t, ex)</tt>
- */
-template <typename T, typename Executor>
-inline typename associated_executor<T, Executor>::type
-get_associated_executor(const T& t, const Executor& ex,
-    typename enable_if<is_executor<
-      Executor>::value>::type* = 0) ASIO_NOEXCEPT
-{
-  return associated_executor<T, Executor>::get(t, ex);
-}
-
-/// Helper function to obtain an object's associated executor.
-/**
- * @returns <tt>associated_executor<T, typename
- * ExecutionContext::executor_type>::get(t, ctx.get_executor())</tt>
- */
-template <typename T, typename ExecutionContext>
-inline typename associated_executor<T,
-  typename ExecutionContext::executor_type>::type
-get_associated_executor(const T& t, ExecutionContext& ctx,
-    typename enable_if<is_convertible<ExecutionContext&,
-      execution_context&>::value>::type* = 0) ASIO_NOEXCEPT
-{
-  return associated_executor<T,
-    typename ExecutionContext::executor_type>::get(t, ctx.get_executor());
-}
-
-#if defined(ASIO_HAS_ALIAS_TEMPLATES)
-
-template <typename T, typename Executor = system_executor>
-using associated_executor_t = typename associated_executor<T, Executor>::type;
-
-#endif // defined(ASIO_HAS_ALIAS_TEMPLATES)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_ASSOCIATED_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/async_result.hpp b/tools/sdk/include/asio/asio/async_result.hpp
deleted file mode 100644
index 18acdf20a20..00000000000
--- a/tools/sdk/include/asio/asio/async_result.hpp
+++ /dev/null
@@ -1,221 +0,0 @@
-//
-// async_result.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_ASYNC_RESULT_HPP
-#define ASIO_ASYNC_RESULT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/handler_type.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// An interface for customising the behaviour of an initiating function.
-/**
- * The async_result traits class is used for determining:
- *
- * @li the concrete completion handler type to be called at the end of the
- * asynchronous operation;
- *
- * @li the initiating function return type; and
- *
- * @li how the return value of the initiating function is obtained.
- *
- * The trait allows the handler and return types to be determined at the point
- * where the specific completion handler signature is known.
- *
- * This template may be specialised for user-defined completion token types.
- * The primary template assumes that the CompletionToken is the completion
- * handler.
- */
-#if defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-template <typename CompletionToken, typename Signature>
-#else // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-template <typename CompletionToken, typename Signature = void>
-#endif // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-class async_result
-{
-public:
-#if defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-  /// The concrete completion handler type for the specific signature.
-  typedef CompletionToken completion_handler_type;
-
-  /// The return type of the initiating function.
-  typedef void return_type;
-#else // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-  // For backward compatibility, determine the concrete completion handler type
-  // by using the legacy handler_type trait.
-  typedef typename handler_type<CompletionToken, Signature>::type
-    completion_handler_type;
-
-  // For backward compatibility, determine the initiating function return type
-  // using the legacy single-parameter version of async_result.
-  typedef typename async_result<completion_handler_type>::type return_type;
-#endif // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-
-  /// Construct an async result from a given handler.
-  /**
-   * When using a specalised async_result, the constructor has an opportunity
-   * to initialise some state associated with the completion handler, which is
-   * then returned from the initiating function.
-   */
-  explicit async_result(completion_handler_type& h)
-#if defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-    // No data members to initialise.
-#else // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-    : legacy_result_(h)
-#endif // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-  {
-    (void)h;
-  }
-
-  /// Obtain the value to be returned from the initiating function.
-  return_type get()
-  {
-#if defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-    // Nothing to do.
-#else // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-    return legacy_result_.get();
-#endif // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-  }
-
-private:
-  async_result(const async_result&) ASIO_DELETED;
-  async_result& operator=(const async_result&) ASIO_DELETED;
-
-#if defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-  // No data members.
-#else // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-  async_result<completion_handler_type> legacy_result_;
-#endif // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-/// (Deprecated: Use two-parameter version of async_result.) An interface for
-/// customising the behaviour of an initiating function.
-/**
- * This template may be specialised for user-defined handler types.
- */
-template <typename Handler>
-class async_result<Handler>
-{
-public:
-  /// The return type of the initiating function.
-  typedef void type;
-
-  /// Construct an async result from a given handler.
-  /**
-   * When using a specalised async_result, the constructor has an opportunity
-   * to initialise some state associated with the handler, which is then
-   * returned from the initiating function.
-   */
-  explicit async_result(Handler&)
-  {
-  }
-
-  /// Obtain the value to be returned from the initiating function.
-  type get()
-  {
-  }
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-/// Helper template to deduce the handler type from a CompletionToken, capture
-/// a local copy of the handler, and then create an async_result for the
-/// handler.
-template <typename CompletionToken, typename Signature>
-struct async_completion
-{
-  /// The real handler type to be used for the asynchronous operation.
-  typedef typename asio::async_result<
-    typename decay<CompletionToken>::type,
-      Signature>::completion_handler_type completion_handler_type;
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Constructor.
-  /**
-   * The constructor creates the concrete completion handler and makes the link
-   * between the handler and the asynchronous result.
-   */
-  explicit async_completion(CompletionToken& token)
-    : completion_handler(static_cast<typename conditional<
-        is_same<CompletionToken, completion_handler_type>::value,
-        completion_handler_type&, CompletionToken&&>::type>(token)),
-      result(completion_handler)
-  {
-  }
-#else // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  explicit async_completion(typename decay<CompletionToken>::type& token)
-    : completion_handler(token),
-      result(completion_handler)
-  {
-  }
-
-  explicit async_completion(const typename decay<CompletionToken>::type& token)
-    : completion_handler(token),
-      result(completion_handler)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// A copy of, or reference to, a real handler object.
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  typename conditional<
-    is_same<CompletionToken, completion_handler_type>::value,
-    completion_handler_type&, completion_handler_type>::type completion_handler;
-#else // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  completion_handler_type completion_handler;
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// The result of the asynchronous operation's initiating function.
-  async_result<typename decay<CompletionToken>::type, Signature> result;
-};
-
-namespace detail {
-
-template <typename CompletionToken, typename Signature>
-struct async_result_helper
-  : async_result<typename decay<CompletionToken>::type, Signature>
-{
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(GENERATING_DOCUMENTATION)
-# define ASIO_INITFN_RESULT_TYPE(ct, sig) \
-  void_or_deduced
-#elif defined(_MSC_VER) && (_MSC_VER < 1500)
-# define ASIO_INITFN_RESULT_TYPE(ct, sig) \
-  typename ::asio::detail::async_result_helper< \
-    ct, sig>::return_type
-#define ASIO_HANDLER_TYPE(ct, sig) \
-  typename ::asio::detail::async_result_helper< \
-    ct, sig>::completion_handler_type
-#else
-# define ASIO_INITFN_RESULT_TYPE(ct, sig) \
-  typename ::asio::async_result< \
-    typename ::asio::decay<ct>::type, sig>::return_type
-#define ASIO_HANDLER_TYPE(ct, sig) \
-  typename ::asio::async_result< \
-    typename ::asio::decay<ct>::type, sig>::completion_handler_type
-#endif
-
-#endif // ASIO_ASYNC_RESULT_HPP
diff --git a/tools/sdk/include/asio/asio/basic_datagram_socket.hpp b/tools/sdk/include/asio/asio/basic_datagram_socket.hpp
deleted file mode 100644
index 346cc353f5f..00000000000
--- a/tools/sdk/include/asio/asio/basic_datagram_socket.hpp
+++ /dev/null
@@ -1,1040 +0,0 @@
-//
-// basic_datagram_socket.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_DATAGRAM_SOCKET_HPP
-#define ASIO_BASIC_DATAGRAM_SOCKET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/basic_socket.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/datagram_socket_service.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides datagram-oriented socket functionality.
-/**
- * The basic_datagram_socket class template provides asynchronous and blocking
- * datagram-oriented socket functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename Protocol
-    ASIO_SVC_TPARAM_DEF1(= datagram_socket_service<Protocol>)>
-class basic_datagram_socket
-  : public basic_socket<Protocol ASIO_SVC_TARG>
-{
-public:
-  /// The native representation of a socket.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename basic_socket<
-    Protocol ASIO_SVC_TARG>::native_handle_type native_handle_type;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  /// Construct a basic_datagram_socket without opening it.
-  /**
-   * This constructor creates a datagram socket without opening it. The open()
-   * function must be called before data can be sent or received on the socket.
-   *
-   * @param io_context The io_context object that the datagram socket will use
-   * to dispatch handlers for any asynchronous operations performed on the
-   * socket.
-   */
-  explicit basic_datagram_socket(asio::io_context& io_context)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context)
-  {
-  }
-
-  /// Construct and open a basic_datagram_socket.
-  /**
-   * This constructor creates and opens a datagram socket.
-   *
-   * @param io_context The io_context object that the datagram socket will use
-   * to dispatch handlers for any asynchronous operations performed on the
-   * socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_datagram_socket(asio::io_context& io_context,
-      const protocol_type& protocol)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context, protocol)
-  {
-  }
-
-  /// Construct a basic_datagram_socket, opening it and binding it to the given
-  /// local endpoint.
-  /**
-   * This constructor creates a datagram socket and automatically opens it bound
-   * to the specified endpoint on the local machine. The protocol used is the
-   * protocol associated with the given endpoint.
-   *
-   * @param io_context The io_context object that the datagram socket will use
-   * to dispatch handlers for any asynchronous operations performed on the
-   * socket.
-   *
-   * @param endpoint An endpoint on the local machine to which the datagram
-   * socket will be bound.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_datagram_socket(asio::io_context& io_context,
-      const endpoint_type& endpoint)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context, endpoint)
-  {
-  }
-
-  /// Construct a basic_datagram_socket on an existing native socket.
-  /**
-   * This constructor creates a datagram socket object to hold an existing
-   * native socket.
-   *
-   * @param io_context The io_context object that the datagram socket will use
-   * to dispatch handlers for any asynchronous operations performed on the
-   * socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @param native_socket The new underlying socket implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_datagram_socket(asio::io_context& io_context,
-      const protocol_type& protocol, const native_handle_type& native_socket)
-    : basic_socket<Protocol ASIO_SVC_TARG>(
-        io_context, protocol, native_socket)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_datagram_socket from another.
-  /**
-   * This constructor moves a datagram socket from one object to another.
-   *
-   * @param other The other basic_datagram_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_datagram_socket(io_context&) constructor.
-   */
-  basic_datagram_socket(basic_datagram_socket&& other)
-    : basic_socket<Protocol ASIO_SVC_TARG>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_datagram_socket from another.
-  /**
-   * This assignment operator moves a datagram socket from one object to
-   * another.
-   *
-   * @param other The other basic_datagram_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_datagram_socket(io_context&) constructor.
-   */
-  basic_datagram_socket& operator=(basic_datagram_socket&& other)
-  {
-    basic_socket<Protocol ASIO_SVC_TARG>::operator=(std::move(other));
-    return *this;
-  }
-
-  /// Move-construct a basic_datagram_socket from a socket of another protocol
-  /// type.
-  /**
-   * This constructor moves a datagram socket from one object to another.
-   *
-   * @param other The other basic_datagram_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_datagram_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  basic_datagram_socket(
-      basic_datagram_socket<Protocol1 ASIO_SVC_TARG1>&& other,
-      typename enable_if<is_convertible<Protocol1, Protocol>::value>::type* = 0)
-    : basic_socket<Protocol ASIO_SVC_TARG>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_datagram_socket from a socket of another protocol
-  /// type.
-  /**
-   * This assignment operator moves a datagram socket from one object to
-   * another.
-   *
-   * @param other The other basic_datagram_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_datagram_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  typename enable_if<is_convertible<Protocol1, Protocol>::value,
-      basic_datagram_socket>::type& operator=(
-        basic_datagram_socket<Protocol1 ASIO_SVC_TARG1>&& other)
-  {
-    basic_socket<Protocol ASIO_SVC_TARG>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroys the socket.
-  /**
-   * This function destroys the socket, cancelling any outstanding asynchronous
-   * operations associated with the socket as if by calling @c cancel.
-   */
-  ~basic_datagram_socket()
-  {
-  }
-
-  /// Send some data on a connected socket.
-  /**
-   * This function is used to send data on the datagram socket. The function
-   * call will block until the data has been sent successfully or an error
-   * occurs.
-   *
-   * @param buffers One ore more data buffers to be sent on the socket.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The send operation can only be used with a connected socket. Use
-   * the send_to function to send data on an unconnected datagram socket.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code socket.send(asio::buffer(data, size)); @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send(
-        this->get_implementation(), buffers, 0, ec);
-    asio::detail::throw_error(ec, "send");
-    return s;
-  }
-
-  /// Send some data on a connected socket.
-  /**
-   * This function is used to send data on the datagram socket. The function
-   * call will block until the data has been sent successfully or an error
-   * occurs.
-   *
-   * @param buffers One ore more data buffers to be sent on the socket.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The send operation can only be used with a connected socket. Use
-   * the send_to function to send data on an unconnected datagram socket.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send(
-        this->get_implementation(), buffers, flags, ec);
-    asio::detail::throw_error(ec, "send");
-    return s;
-  }
-
-  /// Send some data on a connected socket.
-  /**
-   * This function is used to send data on the datagram socket. The function
-   * call will block until the data has been sent successfully or an error
-   * occurs.
-   *
-   * @param buffers One or more data buffers to be sent on the socket.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @note The send operation can only be used with a connected socket. Use
-   * the send_to function to send data on an unconnected datagram socket.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return this->get_service().send(
-        this->get_implementation(), buffers, flags, ec);
-  }
-
-  /// Start an asynchronous send on a connected socket.
-  /**
-   * This function is used to asynchronously send data on the datagram socket.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be sent on the socket. Although
-   * the buffers object may be copied as necessary, ownership of the underlying
-   * memory blocks is retained by the caller, which must guarantee that they
-   * remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The async_send operation can only be used with a connected socket.
-   * Use the async_send_to function to send data on an unconnected datagram
-   * socket.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.async_send(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send(this->get_implementation(),
-        buffers, 0, ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send(this->get_implementation(),
-        buffers, 0, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous send on a connected socket.
-  /**
-   * This function is used to asynchronously send data on the datagram socket.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be sent on the socket. Although
-   * the buffers object may be copied as necessary, ownership of the underlying
-   * memory blocks is retained by the caller, which must guarantee that they
-   * remain valid until the handler is called.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The async_send operation can only be used with a connected socket.
-   * Use the async_send_to function to send data on an unconnected datagram
-   * socket.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send(this->get_implementation(),
-        buffers, flags, ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send(this->get_implementation(),
-        buffers, flags, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Send a datagram to the specified endpoint.
-  /**
-   * This function is used to send a datagram to the specified remote endpoint.
-   * The function call will block until the data has been sent successfully or
-   * an error occurs.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * asio::ip::udp::endpoint destination(
-   *     asio::ip::address::from_string("1.2.3.4"), 12345);
-   * socket.send_to(asio::buffer(data, size), destination);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send_to(
-        this->get_implementation(), buffers, destination, 0, ec);
-    asio::detail::throw_error(ec, "send_to");
-    return s;
-  }
-
-  /// Send a datagram to the specified endpoint.
-  /**
-   * This function is used to send a datagram to the specified remote endpoint.
-   * The function call will block until the data has been sent successfully or
-   * an error occurs.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination, socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send_to(
-        this->get_implementation(), buffers, destination, flags, ec);
-    asio::detail::throw_error(ec, "send_to");
-    return s;
-  }
-
-  /// Send a datagram to the specified endpoint.
-  /**
-   * This function is used to send a datagram to the specified remote endpoint.
-   * The function call will block until the data has been sent successfully or
-   * an error occurs.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes sent.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination, socket_base::message_flags flags,
-      asio::error_code& ec)
-  {
-    return this->get_service().send_to(this->get_implementation(),
-        buffers, destination, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  /**
-   * This function is used to asynchronously send a datagram to the specified
-   * remote endpoint. The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   * Copies will be made of the endpoint as required.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * asio::ip::udp::endpoint destination(
-   *     asio::ip::address::from_string("1.2.3.4"), 12345);
-   * socket.async_send_to(
-   *     asio::buffer(data, size), destination, handler);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send_to(
-        this->get_implementation(), buffers, destination, 0,
-        ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send_to(
-        this->get_implementation(), buffers, destination, 0,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous send.
-  /**
-   * This function is used to asynchronously send a datagram to the specified
-   * remote endpoint. The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   * Copies will be made of the endpoint as required.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination, socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send_to(
-        this->get_implementation(), buffers, destination, flags,
-        ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send_to(
-        this->get_implementation(), buffers, destination, flags,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Receive some data on a connected socket.
-  /**
-   * This function is used to receive data on the datagram socket. The function
-   * call will block until data has been received successfully or an error
-   * occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The receive operation can only be used with a connected socket. Use
-   * the receive_from function to receive data on an unconnected datagram
-   * socket.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code socket.receive(asio::buffer(data, size)); @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive(
-        this->get_implementation(), buffers, 0, ec);
-    asio::detail::throw_error(ec, "receive");
-    return s;
-  }
-
-  /// Receive some data on a connected socket.
-  /**
-   * This function is used to receive data on the datagram socket. The function
-   * call will block until data has been received successfully or an error
-   * occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The receive operation can only be used with a connected socket. Use
-   * the receive_from function to receive data on an unconnected datagram
-   * socket.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive(
-        this->get_implementation(), buffers, flags, ec);
-    asio::detail::throw_error(ec, "receive");
-    return s;
-  }
-
-  /// Receive some data on a connected socket.
-  /**
-   * This function is used to receive data on the datagram socket. The function
-   * call will block until data has been received successfully or an error
-   * occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes received.
-   *
-   * @note The receive operation can only be used with a connected socket. Use
-   * the receive_from function to receive data on an unconnected datagram
-   * socket.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return this->get_service().receive(
-        this->get_implementation(), buffers, flags, ec);
-  }
-
-  /// Start an asynchronous receive on a connected socket.
-  /**
-   * This function is used to asynchronously receive data from the datagram
-   * socket. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The async_receive operation can only be used with a connected socket.
-   * Use the async_receive_from function to receive data on an unconnected
-   * datagram socket.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.async_receive(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive(this->get_implementation(),
-        buffers, 0, ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive(this->get_implementation(),
-        buffers, 0, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous receive on a connected socket.
-  /**
-   * This function is used to asynchronously receive data from the datagram
-   * socket. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The async_receive operation can only be used with a connected socket.
-   * Use the async_receive_from function to receive data on an unconnected
-   * datagram socket.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive(this->get_implementation(),
-        buffers, flags, ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive(this->get_implementation(),
-        buffers, flags, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Receive a datagram with the endpoint of the sender.
-  /**
-   * This function is used to receive a datagram. The function call will block
-   * until data has been received successfully or an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the datagram.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * asio::ip::udp::endpoint sender_endpoint;
-   * socket.receive_from(
-   *     asio::buffer(data, size), sender_endpoint);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive_from(
-        this->get_implementation(), buffers, sender_endpoint, 0, ec);
-    asio::detail::throw_error(ec, "receive_from");
-    return s;
-  }
-  
-  /// Receive a datagram with the endpoint of the sender.
-  /**
-   * This function is used to receive a datagram. The function call will block
-   * until data has been received successfully or an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the datagram.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint, socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive_from(
-        this->get_implementation(), buffers, sender_endpoint, flags, ec);
-    asio::detail::throw_error(ec, "receive_from");
-    return s;
-  }
-  
-  /// Receive a datagram with the endpoint of the sender.
-  /**
-   * This function is used to receive a datagram. The function call will block
-   * until data has been received successfully or an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the datagram.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes received.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint, socket_base::message_flags flags,
-      asio::error_code& ec)
-  {
-    return this->get_service().receive_from(this->get_implementation(),
-        buffers, sender_endpoint, flags, ec);
-  }
-
-  /// Start an asynchronous receive.
-  /**
-   * This function is used to asynchronously receive a datagram. The function
-   * call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the datagram. Ownership of the sender_endpoint object
-   * is retained by the caller, which must guarantee that it is valid until the
-   * handler is called.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code socket.async_receive_from(
-   *     asio::buffer(data, size), sender_endpoint, handler); @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive_from(
-        this->get_implementation(), buffers, sender_endpoint, 0,
-        ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive_from(
-        this->get_implementation(), buffers, sender_endpoint, 0,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous receive.
-  /**
-   * This function is used to asynchronously receive a datagram. The function
-   * call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the datagram. Ownership of the sender_endpoint object
-   * is retained by the caller, which must guarantee that it is valid until the
-   * handler is called.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint, socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive_from(
-        this->get_implementation(), buffers, sender_endpoint, flags,
-        ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive_from(
-        this->get_implementation(), buffers, sender_endpoint, flags,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_BASIC_DATAGRAM_SOCKET_HPP
diff --git a/tools/sdk/include/asio/asio/basic_deadline_timer.hpp b/tools/sdk/include/asio/asio/basic_deadline_timer.hpp
deleted file mode 100644
index 5b20066dff7..00000000000
--- a/tools/sdk/include/asio/asio/basic_deadline_timer.hpp
+++ /dev/null
@@ -1,628 +0,0 @@
-//
-// basic_deadline_timer.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_DEADLINE_TIMER_HPP
-#define ASIO_BASIC_DEADLINE_TIMER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/time_traits.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/deadline_timer_service.hpp"
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/detail/deadline_timer_service.hpp"
-# define ASIO_SVC_T detail::deadline_timer_service<TimeTraits>
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides waitable timer functionality.
-/**
- * The basic_deadline_timer class template provides the ability to perform a
- * blocking or asynchronous wait for a timer to expire.
- *
- * A deadline timer is always in one of two states: "expired" or "not expired".
- * If the wait() or async_wait() function is called on an expired timer, the
- * wait operation will complete immediately.
- *
- * Most applications will use the asio::deadline_timer typedef.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Examples
- * Performing a blocking wait:
- * @code
- * // Construct a timer without setting an expiry time.
- * asio::deadline_timer timer(io_context);
- *
- * // Set an expiry time relative to now.
- * timer.expires_from_now(boost::posix_time::seconds(5));
- *
- * // Wait for the timer to expire.
- * timer.wait();
- * @endcode
- *
- * @par 
- * Performing an asynchronous wait:
- * @code
- * void handler(const asio::error_code& error)
- * {
- *   if (!error)
- *   {
- *     // Timer expired.
- *   }
- * }
- *
- * ...
- *
- * // Construct a timer with an absolute expiry time.
- * asio::deadline_timer timer(io_context,
- *     boost::posix_time::time_from_string("2005-12-07 23:59:59.000"));
- *
- * // Start an asynchronous wait.
- * timer.async_wait(handler);
- * @endcode
- *
- * @par Changing an active deadline_timer's expiry time
- *
- * Changing the expiry time of a timer while there are pending asynchronous
- * waits causes those wait operations to be cancelled. To ensure that the action
- * associated with the timer is performed only once, use something like this:
- * used:
- *
- * @code
- * void on_some_event()
- * {
- *   if (my_timer.expires_from_now(seconds(5)) > 0)
- *   {
- *     // We managed to cancel the timer. Start new asynchronous wait.
- *     my_timer.async_wait(on_timeout);
- *   }
- *   else
- *   {
- *     // Too late, timer has already expired!
- *   }
- * }
- *
- * void on_timeout(const asio::error_code& e)
- * {
- *   if (e != asio::error::operation_aborted)
- *   {
- *     // Timer was not cancelled, take necessary action.
- *   }
- * }
- * @endcode
- *
- * @li The asio::basic_deadline_timer::expires_from_now() function
- * cancels any pending asynchronous waits, and returns the number of
- * asynchronous waits that were cancelled. If it returns 0 then you were too
- * late and the wait handler has already been executed, or will soon be
- * executed. If it returns 1 then the wait handler was successfully cancelled.
- *
- * @li If a wait handler is cancelled, the asio::error_code passed to
- * it contains the value asio::error::operation_aborted.
- */
-template <typename Time,
-    typename TimeTraits = asio::time_traits<Time>
-    ASIO_SVC_TPARAM_DEF2(= deadline_timer_service<Time, TimeTraits>)>
-class basic_deadline_timer
-  : ASIO_SVC_ACCESS basic_io_object<ASIO_SVC_T>
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// The time traits type.
-  typedef TimeTraits traits_type;
-
-  /// The time type.
-  typedef typename traits_type::time_type time_type;
-
-  /// The duration type.
-  typedef typename traits_type::duration_type duration_type;
-
-  /// Constructor.
-  /**
-   * This constructor creates a timer without setting an expiry time. The
-   * expires_at() or expires_from_now() functions must be called to set an
-   * expiry time before the timer can be waited on.
-   *
-   * @param io_context The io_context object that the timer will use to dispatch
-   * handlers for any asynchronous operations performed on the timer.
-   */
-  explicit basic_deadline_timer(asio::io_context& io_context)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-  }
-
-  /// Constructor to set a particular expiry time as an absolute time.
-  /**
-   * This constructor creates a timer and sets the expiry time.
-   *
-   * @param io_context The io_context object that the timer will use to dispatch
-   * handlers for any asynchronous operations performed on the timer.
-   *
-   * @param expiry_time The expiry time to be used for the timer, expressed
-   * as an absolute time.
-   */
-  basic_deadline_timer(asio::io_context& io_context,
-      const time_type& expiry_time)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().expires_at(this->get_implementation(), expiry_time, ec);
-    asio::detail::throw_error(ec, "expires_at");
-  }
-
-  /// Constructor to set a particular expiry time relative to now.
-  /**
-   * This constructor creates a timer and sets the expiry time.
-   *
-   * @param io_context The io_context object that the timer will use to dispatch
-   * handlers for any asynchronous operations performed on the timer.
-   *
-   * @param expiry_time The expiry time to be used for the timer, relative to
-   * now.
-   */
-  basic_deadline_timer(asio::io_context& io_context,
-      const duration_type& expiry_time)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().expires_from_now(
-        this->get_implementation(), expiry_time, ec);
-    asio::detail::throw_error(ec, "expires_from_now");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_deadline_timer from another.
-  /**
-   * This constructor moves a timer from one object to another.
-   *
-   * @param other The other basic_deadline_timer object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_deadline_timer(io_context&) constructor.
-   */
-  basic_deadline_timer(basic_deadline_timer&& other)
-    : basic_io_object<ASIO_SVC_T>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_deadline_timer from another.
-  /**
-   * This assignment operator moves a timer from one object to another. Cancels
-   * any outstanding asynchronous operations associated with the target object.
-   *
-   * @param other The other basic_deadline_timer object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_deadline_timer(io_context&) constructor.
-   */
-  basic_deadline_timer& operator=(basic_deadline_timer&& other)
-  {
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroys the timer.
-  /**
-   * This function destroys the timer, cancelling any outstanding asynchronous
-   * wait operations associated with the timer as if by calling @c cancel.
-   */
-  ~basic_deadline_timer()
-  {
-  }
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  // These functions are provided by basic_io_object<>.
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<ASIO_SVC_T>::get_executor();
-  }
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-  /// Cancel any asynchronous operations that are waiting on the timer.
-  /**
-   * This function forces the completion of any pending asynchronous wait
-   * operations against the timer. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * Cancelling the timer does not change the expiry time.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If the timer has already expired when cancel() is called, then the
-   * handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t cancel()
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-    return s;
-  }
-
-  /// Cancel any asynchronous operations that are waiting on the timer.
-  /**
-   * This function forces the completion of any pending asynchronous wait
-   * operations against the timer. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * Cancelling the timer does not change the expiry time.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @note If the timer has already expired when cancel() is called, then the
-   * handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t cancel(asio::error_code& ec)
-  {
-    return this->get_service().cancel(this->get_implementation(), ec);
-  }
-
-  /// Cancels one asynchronous operation that is waiting on the timer.
-  /**
-   * This function forces the completion of one pending asynchronous wait
-   * operation against the timer. Handlers are cancelled in FIFO order. The
-   * handler for the cancelled operation will be invoked with the
-   * asio::error::operation_aborted error code.
-   *
-   * Cancelling the timer does not change the expiry time.
-   *
-   * @return The number of asynchronous operations that were cancelled. That is,
-   * either 0 or 1.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If the timer has already expired when cancel_one() is called, then
-   * the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t cancel_one()
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().cancel_one(
-        this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel_one");
-    return s;
-  }
-
-  /// Cancels one asynchronous operation that is waiting on the timer.
-  /**
-   * This function forces the completion of one pending asynchronous wait
-   * operation against the timer. Handlers are cancelled in FIFO order. The
-   * handler for the cancelled operation will be invoked with the
-   * asio::error::operation_aborted error code.
-   *
-   * Cancelling the timer does not change the expiry time.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of asynchronous operations that were cancelled. That is,
-   * either 0 or 1.
-   *
-   * @note If the timer has already expired when cancel_one() is called, then
-   * the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t cancel_one(asio::error_code& ec)
-  {
-    return this->get_service().cancel_one(this->get_implementation(), ec);
-  }
-
-  /// Get the timer's expiry time as an absolute time.
-  /**
-   * This function may be used to obtain the timer's current expiry time.
-   * Whether the timer has expired or not does not affect this value.
-   */
-  time_type expires_at() const
-  {
-    return this->get_service().expires_at(this->get_implementation());
-  }
-
-  /// Set the timer's expiry time as an absolute time.
-  /**
-   * This function sets the expiry time. Any pending asynchronous wait
-   * operations will be cancelled. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If the timer has already expired when expires_at() is called, then
-   * the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t expires_at(const time_type& expiry_time)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().expires_at(
-        this->get_implementation(), expiry_time, ec);
-    asio::detail::throw_error(ec, "expires_at");
-    return s;
-  }
-
-  /// Set the timer's expiry time as an absolute time.
-  /**
-   * This function sets the expiry time. Any pending asynchronous wait
-   * operations will be cancelled. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @note If the timer has already expired when expires_at() is called, then
-   * the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t expires_at(const time_type& expiry_time,
-      asio::error_code& ec)
-  {
-    return this->get_service().expires_at(
-        this->get_implementation(), expiry_time, ec);
-  }
-
-  /// Get the timer's expiry time relative to now.
-  /**
-   * This function may be used to obtain the timer's current expiry time.
-   * Whether the timer has expired or not does not affect this value.
-   */
-  duration_type expires_from_now() const
-  {
-    return this->get_service().expires_from_now(this->get_implementation());
-  }
-
-  /// Set the timer's expiry time relative to now.
-  /**
-   * This function sets the expiry time. Any pending asynchronous wait
-   * operations will be cancelled. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If the timer has already expired when expires_from_now() is called,
-   * then the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t expires_from_now(const duration_type& expiry_time)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().expires_from_now(
-        this->get_implementation(), expiry_time, ec);
-    asio::detail::throw_error(ec, "expires_from_now");
-    return s;
-  }
-
-  /// Set the timer's expiry time relative to now.
-  /**
-   * This function sets the expiry time. Any pending asynchronous wait
-   * operations will be cancelled. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @note If the timer has already expired when expires_from_now() is called,
-   * then the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t expires_from_now(const duration_type& expiry_time,
-      asio::error_code& ec)
-  {
-    return this->get_service().expires_from_now(
-        this->get_implementation(), expiry_time, ec);
-  }
-
-  /// Perform a blocking wait on the timer.
-  /**
-   * This function is used to wait for the timer to expire. This function
-   * blocks and does not return until the timer has expired.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void wait()
-  {
-    asio::error_code ec;
-    this->get_service().wait(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "wait");
-  }
-
-  /// Perform a blocking wait on the timer.
-  /**
-   * This function is used to wait for the timer to expire. This function
-   * blocks and does not return until the timer has expired.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  void wait(asio::error_code& ec)
-  {
-    this->get_service().wait(this->get_implementation(), ec);
-  }
-
-  /// Start an asynchronous wait on the timer.
-  /**
-   * This function may be used to initiate an asynchronous wait against the
-   * timer. It always returns immediately.
-   *
-   * For each call to async_wait(), the supplied handler will be called exactly
-   * once. The handler will be called when:
-   *
-   * @li The timer has expired.
-   *
-   * @li The timer was cancelled, in which case the handler is passed the error
-   * code asio::error::operation_aborted.
-   *
-   * @param handler The handler to be called when the timer expires. Copies
-   * will be made of the handler as required. The function signature of the
-   * handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WaitHandler.
-    ASIO_WAIT_HANDLER_CHECK(WaitHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_wait(this->get_implementation(),
-        ASIO_MOVE_CAST(WaitHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    this->get_service().async_wait(this->get_implementation(),
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-# undef ASIO_SVC_T
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_BASIC_DEADLINE_TIMER_HPP
diff --git a/tools/sdk/include/asio/asio/basic_io_object.hpp b/tools/sdk/include/asio/asio/basic_io_object.hpp
deleted file mode 100644
index 442e85429dc..00000000000
--- a/tools/sdk/include/asio/asio/basic_io_object.hpp
+++ /dev/null
@@ -1,290 +0,0 @@
-//
-// basic_io_object.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_IO_OBJECT_HPP
-#define ASIO_BASIC_IO_OBJECT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-#if defined(ASIO_HAS_MOVE)
-namespace detail
-{
-  // Type trait used to determine whether a service supports move.
-  template <typename IoObjectService>
-  class service_has_move
-  {
-  private:
-    typedef IoObjectService service_type;
-    typedef typename service_type::implementation_type implementation_type;
-
-    template <typename T, typename U>
-    static auto asio_service_has_move_eval(T* t, U* u)
-      -> decltype(t->move_construct(*u, *u), char());
-    static char (&asio_service_has_move_eval(...))[2];
-
-  public:
-    static const bool value =
-      sizeof(asio_service_has_move_eval(
-        static_cast<service_type*>(0),
-        static_cast<implementation_type*>(0))) == 1;
-  };
-}
-#endif // defined(ASIO_HAS_MOVE)
-
-/// Base class for all I/O objects.
-/**
- * @note All I/O objects are non-copyable. However, when using C++0x, certain
- * I/O objects do support move construction and move assignment.
- */
-#if !defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-template <typename IoObjectService>
-#else
-template <typename IoObjectService,
-    bool Movable = detail::service_has_move<IoObjectService>::value>
-#endif
-class basic_io_object
-{
-public:
-  /// The type of the service that will be used to provide I/O operations.
-  typedef IoObjectService service_type;
-
-  /// The underlying implementation type of I/O object.
-  typedef typename service_type::implementation_type implementation_type;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return service_.get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return service_.get_io_context();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// The type of the executor associated with the object.
-  typedef asio::io_context::executor_type executor_type;
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return service_.get_io_context().get_executor();
-  }
-
-protected:
-  /// Construct a basic_io_object.
-  /**
-   * Performs:
-   * @code get_service().construct(get_implementation()); @endcode
-   */
-  explicit basic_io_object(asio::io_context& io_context)
-    : service_(asio::use_service<IoObjectService>(io_context))
-  {
-    service_.construct(implementation_);
-  }
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_io_object.
-  /**
-   * Performs:
-   * @code get_service().move_construct(
-   *     get_implementation(), other.get_implementation()); @endcode
-   *
-   * @note Available only for services that support movability,
-   */
-  basic_io_object(basic_io_object&& other);
-
-  /// Move-assign a basic_io_object.
-  /**
-   * Performs:
-   * @code get_service().move_assign(get_implementation(),
-   *     other.get_service(), other.get_implementation()); @endcode
-   *
-   * @note Available only for services that support movability,
-   */
-  basic_io_object& operator=(basic_io_object&& other);
-
-  /// Perform a converting move-construction of a basic_io_object.
-  template <typename IoObjectService1>
-  basic_io_object(IoObjectService1& other_service,
-      typename IoObjectService1::implementation_type& other_implementation);
-#endif // defined(GENERATING_DOCUMENTATION)
-
-  /// Protected destructor to prevent deletion through this type.
-  /**
-   * Performs:
-   * @code get_service().destroy(get_implementation()); @endcode
-   */
-  ~basic_io_object()
-  {
-    service_.destroy(implementation_);
-  }
-
-  /// Get the service associated with the I/O object.
-  service_type& get_service()
-  {
-    return service_;
-  }
-
-  /// Get the service associated with the I/O object.
-  const service_type& get_service() const
-  {
-    return service_;
-  }
-
-  /// Get the underlying implementation of the I/O object.
-  implementation_type& get_implementation()
-  {
-    return implementation_;
-  }
-
-  /// Get the underlying implementation of the I/O object.
-  const implementation_type& get_implementation() const
-  {
-    return implementation_;
-  }
-
-private:
-  basic_io_object(const basic_io_object&);
-  basic_io_object& operator=(const basic_io_object&);
-
-  // The service associated with the I/O object.
-  service_type& service_;
-
-  /// The underlying implementation of the I/O object.
-  implementation_type implementation_;
-};
-
-#if defined(ASIO_HAS_MOVE)
-// Specialisation for movable objects.
-template <typename IoObjectService>
-class basic_io_object<IoObjectService, true>
-{
-public:
-  typedef IoObjectService service_type;
-  typedef typename service_type::implementation_type implementation_type;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  asio::io_context& get_io_context()
-  {
-    return service_->get_io_context();
-  }
-
-  asio::io_context& get_io_service()
-  {
-    return service_->get_io_context();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  typedef asio::io_context::executor_type executor_type;
-
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return service_->get_io_context().get_executor();
-  }
-
-protected:
-  explicit basic_io_object(asio::io_context& io_context)
-    : service_(&asio::use_service<IoObjectService>(io_context))
-  {
-    service_->construct(implementation_);
-  }
-
-  basic_io_object(basic_io_object&& other)
-    : service_(&other.get_service())
-  {
-    service_->move_construct(implementation_, other.implementation_);
-  }
-
-  template <typename IoObjectService1>
-  basic_io_object(IoObjectService1& other_service,
-      typename IoObjectService1::implementation_type& other_implementation)
-    : service_(&asio::use_service<IoObjectService>(
-          other_service.get_io_context()))
-  {
-    service_->converting_move_construct(implementation_,
-        other_service, other_implementation);
-  }
-
-  ~basic_io_object()
-  {
-    service_->destroy(implementation_);
-  }
-
-  basic_io_object& operator=(basic_io_object&& other)
-  {
-    service_->move_assign(implementation_,
-        *other.service_, other.implementation_);
-    service_ = other.service_;
-    return *this;
-  }
-
-  service_type& get_service()
-  {
-    return *service_;
-  }
-
-  const service_type& get_service() const
-  {
-    return *service_;
-  }
-
-  implementation_type& get_implementation()
-  {
-    return implementation_;
-  }
-
-  const implementation_type& get_implementation() const
-  {
-    return implementation_;
-  }
-
-private:
-  basic_io_object(const basic_io_object&);
-  void operator=(const basic_io_object&);
-
-  IoObjectService* service_;
-  implementation_type implementation_;
-};
-#endif // defined(ASIO_HAS_MOVE)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_BASIC_IO_OBJECT_HPP
diff --git a/tools/sdk/include/asio/asio/basic_raw_socket.hpp b/tools/sdk/include/asio/asio/basic_raw_socket.hpp
deleted file mode 100644
index 0de7c776618..00000000000
--- a/tools/sdk/include/asio/asio/basic_raw_socket.hpp
+++ /dev/null
@@ -1,1030 +0,0 @@
-//
-// basic_raw_socket.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_RAW_SOCKET_HPP
-#define ASIO_BASIC_RAW_SOCKET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/basic_socket.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/raw_socket_service.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides raw-oriented socket functionality.
-/**
- * The basic_raw_socket class template provides asynchronous and blocking
- * raw-oriented socket functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename Protocol
-    ASIO_SVC_TPARAM_DEF1(= raw_socket_service<Protocol>)>
-class basic_raw_socket
-  : public basic_socket<Protocol ASIO_SVC_TARG>
-{
-public:
-  /// The native representation of a socket.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename basic_socket<
-    Protocol ASIO_SVC_TARG>::native_handle_type native_handle_type;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  /// Construct a basic_raw_socket without opening it.
-  /**
-   * This constructor creates a raw socket without opening it. The open()
-   * function must be called before data can be sent or received on the socket.
-   *
-   * @param io_context The io_context object that the raw socket will use
-   * to dispatch handlers for any asynchronous operations performed on the
-   * socket.
-   */
-  explicit basic_raw_socket(asio::io_context& io_context)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context)
-  {
-  }
-
-  /// Construct and open a basic_raw_socket.
-  /**
-   * This constructor creates and opens a raw socket.
-   *
-   * @param io_context The io_context object that the raw socket will use
-   * to dispatch handlers for any asynchronous operations performed on the
-   * socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_raw_socket(asio::io_context& io_context,
-      const protocol_type& protocol)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context, protocol)
-  {
-  }
-
-  /// Construct a basic_raw_socket, opening it and binding it to the given
-  /// local endpoint.
-  /**
-   * This constructor creates a raw socket and automatically opens it bound
-   * to the specified endpoint on the local machine. The protocol used is the
-   * protocol associated with the given endpoint.
-   *
-   * @param io_context The io_context object that the raw socket will use
-   * to dispatch handlers for any asynchronous operations performed on the
-   * socket.
-   *
-   * @param endpoint An endpoint on the local machine to which the raw
-   * socket will be bound.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_raw_socket(asio::io_context& io_context,
-      const endpoint_type& endpoint)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context, endpoint)
-  {
-  }
-
-  /// Construct a basic_raw_socket on an existing native socket.
-  /**
-   * This constructor creates a raw socket object to hold an existing
-   * native socket.
-   *
-   * @param io_context The io_context object that the raw socket will use
-   * to dispatch handlers for any asynchronous operations performed on the
-   * socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @param native_socket The new underlying socket implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_raw_socket(asio::io_context& io_context,
-      const protocol_type& protocol, const native_handle_type& native_socket)
-    : basic_socket<Protocol ASIO_SVC_TARG>(
-        io_context, protocol, native_socket)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_raw_socket from another.
-  /**
-   * This constructor moves a raw socket from one object to another.
-   *
-   * @param other The other basic_raw_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_raw_socket(io_context&) constructor.
-   */
-  basic_raw_socket(basic_raw_socket&& other)
-    : basic_socket<Protocol ASIO_SVC_TARG>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_raw_socket from another.
-  /**
-   * This assignment operator moves a raw socket from one object to another.
-   *
-   * @param other The other basic_raw_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_raw_socket(io_context&) constructor.
-   */
-  basic_raw_socket& operator=(basic_raw_socket&& other)
-  {
-    basic_socket<Protocol ASIO_SVC_TARG>::operator=(std::move(other));
-    return *this;
-  }
-
-  /// Move-construct a basic_raw_socket from a socket of another protocol type.
-  /**
-   * This constructor moves a raw socket from one object to another.
-   *
-   * @param other The other basic_raw_socket object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_raw_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  basic_raw_socket(basic_raw_socket<Protocol1 ASIO_SVC_TARG1>&& other,
-      typename enable_if<is_convertible<Protocol1, Protocol>::value>::type* = 0)
-    : basic_socket<Protocol ASIO_SVC_TARG>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_raw_socket from a socket of another protocol type.
-  /**
-   * This assignment operator moves a raw socket from one object to another.
-   *
-   * @param other The other basic_raw_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_raw_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  typename enable_if<is_convertible<Protocol1, Protocol>::value,
-      basic_raw_socket>::type& operator=(
-        basic_raw_socket<Protocol1 ASIO_SVC_TARG1>&& other)
-  {
-    basic_socket<Protocol ASIO_SVC_TARG>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroys the socket.
-  /**
-   * This function destroys the socket, cancelling any outstanding asynchronous
-   * operations associated with the socket as if by calling @c cancel.
-   */
-  ~basic_raw_socket()
-  {
-  }
-
-  /// Send some data on a connected socket.
-  /**
-   * This function is used to send data on the raw socket. The function call
-   * will block until the data has been sent successfully or an error occurs.
-   *
-   * @param buffers One ore more data buffers to be sent on the socket.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The send operation can only be used with a connected socket. Use
-   * the send_to function to send data on an unconnected raw socket.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code socket.send(asio::buffer(data, size)); @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send(
-        this->get_implementation(), buffers, 0, ec);
-    asio::detail::throw_error(ec, "send");
-    return s;
-  }
-
-  /// Send some data on a connected socket.
-  /**
-   * This function is used to send data on the raw socket. The function call
-   * will block until the data has been sent successfully or an error occurs.
-   *
-   * @param buffers One ore more data buffers to be sent on the socket.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The send operation can only be used with a connected socket. Use
-   * the send_to function to send data on an unconnected raw socket.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send(
-        this->get_implementation(), buffers, flags, ec);
-    asio::detail::throw_error(ec, "send");
-    return s;
-  }
-
-  /// Send some data on a connected socket.
-  /**
-   * This function is used to send data on the raw socket. The function call
-   * will block until the data has been sent successfully or an error occurs.
-   *
-   * @param buffers One or more data buffers to be sent on the socket.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @note The send operation can only be used with a connected socket. Use
-   * the send_to function to send data on an unconnected raw socket.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return this->get_service().send(
-        this->get_implementation(), buffers, flags, ec);
-  }
-
-  /// Start an asynchronous send on a connected socket.
-  /**
-   * This function is used to send data on the raw socket. The function call
-   * will block until the data has been sent successfully or an error occurs.
-   *
-   * @param buffers One or more data buffers to be sent on the socket. Although
-   * the buffers object may be copied as necessary, ownership of the underlying
-   * memory blocks is retained by the caller, which must guarantee that they
-   * remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The async_send operation can only be used with a connected socket.
-   * Use the async_send_to function to send data on an unconnected raw
-   * socket.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.async_send(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send(this->get_implementation(),
-        buffers, 0, ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send(this->get_implementation(),
-        buffers, 0, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous send on a connected socket.
-  /**
-   * This function is used to send data on the raw socket. The function call
-   * will block until the data has been sent successfully or an error occurs.
-   *
-   * @param buffers One or more data buffers to be sent on the socket. Although
-   * the buffers object may be copied as necessary, ownership of the underlying
-   * memory blocks is retained by the caller, which must guarantee that they
-   * remain valid until the handler is called.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The async_send operation can only be used with a connected socket.
-   * Use the async_send_to function to send data on an unconnected raw
-   * socket.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send(this->get_implementation(),
-        buffers, flags, ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send(this->get_implementation(),
-        buffers, flags, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Send raw data to the specified endpoint.
-  /**
-   * This function is used to send raw data to the specified remote endpoint.
-   * The function call will block until the data has been sent successfully or
-   * an error occurs.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * asio::ip::udp::endpoint destination(
-   *     asio::ip::address::from_string("1.2.3.4"), 12345);
-   * socket.send_to(asio::buffer(data, size), destination);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send_to(
-        this->get_implementation(), buffers, destination, 0, ec);
-    asio::detail::throw_error(ec, "send_to");
-    return s;
-  }
-
-  /// Send raw data to the specified endpoint.
-  /**
-   * This function is used to send raw data to the specified remote endpoint.
-   * The function call will block until the data has been sent successfully or
-   * an error occurs.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination, socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send_to(
-        this->get_implementation(), buffers, destination, flags, ec);
-    asio::detail::throw_error(ec, "send_to");
-    return s;
-  }
-
-  /// Send raw data to the specified endpoint.
-  /**
-   * This function is used to send raw data to the specified remote endpoint.
-   * The function call will block until the data has been sent successfully or
-   * an error occurs.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes sent.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination, socket_base::message_flags flags,
-      asio::error_code& ec)
-  {
-    return this->get_service().send_to(this->get_implementation(),
-        buffers, destination, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  /**
-   * This function is used to asynchronously send raw data to the specified
-   * remote endpoint. The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   * Copies will be made of the endpoint as required.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * asio::ip::udp::endpoint destination(
-   *     asio::ip::address::from_string("1.2.3.4"), 12345);
-   * socket.async_send_to(
-   *     asio::buffer(data, size), destination, handler);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send_to(this->get_implementation(),
-        buffers, destination, 0, ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send_to(this->get_implementation(),
-        buffers, destination, 0, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous send.
-  /**
-   * This function is used to asynchronously send raw data to the specified
-   * remote endpoint. The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be sent to the remote endpoint.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param destination The remote endpoint to which the data will be sent.
-   * Copies will be made of the endpoint as required.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send_to(const ConstBufferSequence& buffers,
-      const endpoint_type& destination, socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send_to(
-        this->get_implementation(), buffers, destination, flags,
-        ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send_to(
-        this->get_implementation(), buffers, destination, flags,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Receive some data on a connected socket.
-  /**
-   * This function is used to receive data on the raw socket. The function
-   * call will block until data has been received successfully or an error
-   * occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The receive operation can only be used with a connected socket. Use
-   * the receive_from function to receive data on an unconnected raw
-   * socket.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code socket.receive(asio::buffer(data, size)); @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive(
-        this->get_implementation(), buffers, 0, ec);
-    asio::detail::throw_error(ec, "receive");
-    return s;
-  }
-
-  /// Receive some data on a connected socket.
-  /**
-   * This function is used to receive data on the raw socket. The function
-   * call will block until data has been received successfully or an error
-   * occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The receive operation can only be used with a connected socket. Use
-   * the receive_from function to receive data on an unconnected raw
-   * socket.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive(
-        this->get_implementation(), buffers, flags, ec);
-    asio::detail::throw_error(ec, "receive");
-    return s;
-  }
-
-  /// Receive some data on a connected socket.
-  /**
-   * This function is used to receive data on the raw socket. The function
-   * call will block until data has been received successfully or an error
-   * occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes received.
-   *
-   * @note The receive operation can only be used with a connected socket. Use
-   * the receive_from function to receive data on an unconnected raw
-   * socket.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return this->get_service().receive(
-        this->get_implementation(), buffers, flags, ec);
-  }
-
-  /// Start an asynchronous receive on a connected socket.
-  /**
-   * This function is used to asynchronously receive data from the raw
-   * socket. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The async_receive operation can only be used with a connected socket.
-   * Use the async_receive_from function to receive data on an unconnected
-   * raw socket.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.async_receive(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive(this->get_implementation(),
-        buffers, 0, ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive(this->get_implementation(),
-        buffers, 0, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous receive on a connected socket.
-  /**
-   * This function is used to asynchronously receive data from the raw
-   * socket. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The async_receive operation can only be used with a connected socket.
-   * Use the async_receive_from function to receive data on an unconnected
-   * raw socket.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive(this->get_implementation(),
-        buffers, flags, ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive(this->get_implementation(),
-        buffers, flags, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Receive raw data with the endpoint of the sender.
-  /**
-   * This function is used to receive raw data. The function call will block
-   * until data has been received successfully or an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the data.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * asio::ip::udp::endpoint sender_endpoint;
-   * socket.receive_from(
-   *     asio::buffer(data, size), sender_endpoint);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive_from(
-        this->get_implementation(), buffers, sender_endpoint, 0, ec);
-    asio::detail::throw_error(ec, "receive_from");
-    return s;
-  }
-  
-  /// Receive raw data with the endpoint of the sender.
-  /**
-   * This function is used to receive raw data. The function call will block
-   * until data has been received successfully or an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the data.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint, socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive_from(
-        this->get_implementation(), buffers, sender_endpoint, flags, ec);
-    asio::detail::throw_error(ec, "receive_from");
-    return s;
-  }
-  
-  /// Receive raw data with the endpoint of the sender.
-  /**
-   * This function is used to receive raw data. The function call will block
-   * until data has been received successfully or an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the data.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes received.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint, socket_base::message_flags flags,
-      asio::error_code& ec)
-  {
-    return this->get_service().receive_from(this->get_implementation(),
-        buffers, sender_endpoint, flags, ec);
-  }
-
-  /// Start an asynchronous receive.
-  /**
-   * This function is used to asynchronously receive raw data. The function
-   * call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the data. Ownership of the sender_endpoint object
-   * is retained by the caller, which must guarantee that it is valid until the
-   * handler is called.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code socket.async_receive_from(
-   *     asio::buffer(data, size), 0, sender_endpoint, handler); @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive_from(
-        this->get_implementation(), buffers, sender_endpoint, 0,
-        ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive_from(
-        this->get_implementation(), buffers, sender_endpoint, 0,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous receive.
-  /**
-   * This function is used to asynchronously receive raw data. The function
-   * call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param sender_endpoint An endpoint object that receives the endpoint of
-   * the remote sender of the data. Ownership of the sender_endpoint object
-   * is retained by the caller, which must guarantee that it is valid until the
-   * handler is called.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive_from(const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint, socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive_from(
-        this->get_implementation(), buffers, sender_endpoint, flags,
-        ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive_from(
-        this->get_implementation(), buffers, sender_endpoint, flags,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_BASIC_RAW_SOCKET_HPP
diff --git a/tools/sdk/include/asio/asio/basic_seq_packet_socket.hpp b/tools/sdk/include/asio/asio/basic_seq_packet_socket.hpp
deleted file mode 100644
index 3655d881cc3..00000000000
--- a/tools/sdk/include/asio/asio/basic_seq_packet_socket.hpp
+++ /dev/null
@@ -1,618 +0,0 @@
-//
-// basic_seq_packet_socket.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_SEQ_PACKET_SOCKET_HPP
-#define ASIO_BASIC_SEQ_PACKET_SOCKET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/basic_socket.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/seq_packet_socket_service.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides sequenced packet socket functionality.
-/**
- * The basic_seq_packet_socket class template provides asynchronous and blocking
- * sequenced packet socket functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename Protocol
-    ASIO_SVC_TPARAM_DEF1(= seq_packet_socket_service<Protocol>)>
-class basic_seq_packet_socket
-  : public basic_socket<Protocol ASIO_SVC_TARG>
-{
-public:
-  /// The native representation of a socket.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename basic_socket<
-    Protocol ASIO_SVC_TARG>::native_handle_type native_handle_type;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  /// Construct a basic_seq_packet_socket without opening it.
-  /**
-   * This constructor creates a sequenced packet socket without opening it. The
-   * socket needs to be opened and then connected or accepted before data can
-   * be sent or received on it.
-   *
-   * @param io_context The io_context object that the sequenced packet socket
-   * will use to dispatch handlers for any asynchronous operations performed on
-   * the socket.
-   */
-  explicit basic_seq_packet_socket(asio::io_context& io_context)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context)
-  {
-  }
-
-  /// Construct and open a basic_seq_packet_socket.
-  /**
-   * This constructor creates and opens a sequenced_packet socket. The socket
-   * needs to be connected or accepted before data can be sent or received on
-   * it.
-   *
-   * @param io_context The io_context object that the sequenced packet socket
-   * will use to dispatch handlers for any asynchronous operations performed on
-   * the socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_seq_packet_socket(asio::io_context& io_context,
-      const protocol_type& protocol)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context, protocol)
-  {
-  }
-
-  /// Construct a basic_seq_packet_socket, opening it and binding it to the
-  /// given local endpoint.
-  /**
-   * This constructor creates a sequenced packet socket and automatically opens
-   * it bound to the specified endpoint on the local machine. The protocol used
-   * is the protocol associated with the given endpoint.
-   *
-   * @param io_context The io_context object that the sequenced packet socket
-   * will use to dispatch handlers for any asynchronous operations performed on
-   * the socket.
-   *
-   * @param endpoint An endpoint on the local machine to which the sequenced
-   * packet socket will be bound.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_seq_packet_socket(asio::io_context& io_context,
-      const endpoint_type& endpoint)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context, endpoint)
-  {
-  }
-
-  /// Construct a basic_seq_packet_socket on an existing native socket.
-  /**
-   * This constructor creates a sequenced packet socket object to hold an
-   * existing native socket.
-   *
-   * @param io_context The io_context object that the sequenced packet socket
-   * will use to dispatch handlers for any asynchronous operations performed on
-   * the socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @param native_socket The new underlying socket implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_seq_packet_socket(asio::io_context& io_context,
-      const protocol_type& protocol, const native_handle_type& native_socket)
-    : basic_socket<Protocol ASIO_SVC_TARG>(
-        io_context, protocol, native_socket)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_seq_packet_socket from another.
-  /**
-   * This constructor moves a sequenced packet socket from one object to
-   * another.
-   *
-   * @param other The other basic_seq_packet_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_seq_packet_socket(io_context&) constructor.
-   */
-  basic_seq_packet_socket(basic_seq_packet_socket&& other)
-    : basic_socket<Protocol ASIO_SVC_TARG>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_seq_packet_socket from another.
-  /**
-   * This assignment operator moves a sequenced packet socket from one object to
-   * another.
-   *
-   * @param other The other basic_seq_packet_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_seq_packet_socket(io_context&) constructor.
-   */
-  basic_seq_packet_socket& operator=(basic_seq_packet_socket&& other)
-  {
-    basic_socket<Protocol ASIO_SVC_TARG>::operator=(std::move(other));
-    return *this;
-  }
-
-  /// Move-construct a basic_seq_packet_socket from a socket of another protocol
-  /// type.
-  /**
-   * This constructor moves a sequenced packet socket from one object to
-   * another.
-   *
-   * @param other The other basic_seq_packet_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_seq_packet_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  basic_seq_packet_socket(
-      basic_seq_packet_socket<Protocol1 ASIO_SVC_TARG1>&& other,
-      typename enable_if<is_convertible<Protocol1, Protocol>::value>::type* = 0)
-    : basic_socket<Protocol ASIO_SVC_TARG>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_seq_packet_socket from a socket of another protocol
-  /// type.
-  /**
-   * This assignment operator moves a sequenced packet socket from one object to
-   * another.
-   *
-   * @param other The other basic_seq_packet_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_seq_packet_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  typename enable_if<is_convertible<Protocol1, Protocol>::value,
-      basic_seq_packet_socket>::type& operator=(
-        basic_seq_packet_socket<Protocol1 ASIO_SVC_TARG1>&& other)
-  {
-    basic_socket<Protocol ASIO_SVC_TARG>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroys the socket.
-  /**
-   * This function destroys the socket, cancelling any outstanding asynchronous
-   * operations associated with the socket as if by calling @c cancel.
-   */
-  ~basic_seq_packet_socket()
-  {
-  }
-
-  /// Send some data on the socket.
-  /**
-   * This function is used to send data on the sequenced packet socket. The
-   * function call will block until the data has been sent successfully, or an
-   * until error occurs.
-   *
-   * @param buffers One or more data buffers to be sent on the socket.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.send(asio::buffer(data, size), 0);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send(
-        this->get_implementation(), buffers, flags, ec);
-    asio::detail::throw_error(ec, "send");
-    return s;
-  }
-
-  /// Send some data on the socket.
-  /**
-   * This function is used to send data on the sequenced packet socket. The
-   * function call will block the data has been sent successfully, or an until
-   * error occurs.
-   *
-   * @param buffers One or more data buffers to be sent on the socket.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes sent. Returns 0 if an error occurred.
-   *
-   * @note The send operation may not transmit all of the data to the peer.
-   * Consider using the @ref write function if you need to ensure that all data
-   * is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return this->get_service().send(
-        this->get_implementation(), buffers, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  /**
-   * This function is used to asynchronously send data on the sequenced packet
-   * socket. The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be sent on the socket. Although
-   * the buffers object may be copied as necessary, ownership of the underlying
-   * memory blocks is retained by the caller, which must guarantee that they
-   * remain valid until the handler is called.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.async_send(asio::buffer(data, size), 0, handler);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send(this->get_implementation(),
-        buffers, flags, ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send(this->get_implementation(),
-        buffers, flags, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Receive some data on the socket.
-  /**
-   * This function is used to receive data on the sequenced packet socket. The
-   * function call will block until data has been received successfully, or
-   * until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param out_flags After the receive call completes, contains flags
-   * associated with the received data. For example, if the
-   * socket_base::message_end_of_record bit is set then the received data marks
-   * the end of a record.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.receive(asio::buffer(data, size), out_flags);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags& out_flags)
-  {
-    asio::error_code ec;
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    std::size_t s = this->get_service().receive(
-        this->get_implementation(), buffers, 0, out_flags, ec);
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    std::size_t s = this->get_service().receive_with_flags(
-        this->get_implementation(), buffers, 0, out_flags, ec);
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-    asio::detail::throw_error(ec, "receive");
-    return s;
-  }
-
-  /// Receive some data on the socket.
-  /**
-   * This function is used to receive data on the sequenced packet socket. The
-   * function call will block until data has been received successfully, or
-   * until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param in_flags Flags specifying how the receive call is to be made.
-   *
-   * @param out_flags After the receive call completes, contains flags
-   * associated with the received data. For example, if the
-   * socket_base::message_end_of_record bit is set then the received data marks
-   * the end of a record.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The receive operation may not receive all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that the
-   * requested amount of data is read before the blocking operation completes.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.receive(asio::buffer(data, size), 0, out_flags);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags)
-  {
-    asio::error_code ec;
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    std::size_t s = this->get_service().receive(
-        this->get_implementation(), buffers, in_flags, out_flags, ec);
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    std::size_t s = this->get_service().receive_with_flags(
-        this->get_implementation(), buffers, in_flags, out_flags, ec);
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-    asio::detail::throw_error(ec, "receive");
-    return s;
-  }
-
-  /// Receive some data on a connected socket.
-  /**
-   * This function is used to receive data on the sequenced packet socket. The
-   * function call will block until data has been received successfully, or
-   * until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param in_flags Flags specifying how the receive call is to be made.
-   *
-   * @param out_flags After the receive call completes, contains flags
-   * associated with the received data. For example, if the
-   * socket_base::message_end_of_record bit is set then the received data marks
-   * the end of a record.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes received. Returns 0 if an error occurred.
-   *
-   * @note The receive operation may not receive all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that the
-   * requested amount of data is read before the blocking operation completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, asio::error_code& ec)
-  {
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().receive(this->get_implementation(),
-        buffers, in_flags, out_flags, ec);
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().receive_with_flags(this->get_implementation(),
-        buffers, in_flags, out_flags, ec);
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous receive.
-  /**
-   * This function is used to asynchronously receive data from the sequenced
-   * packet socket. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param out_flags Once the asynchronous operation completes, contains flags
-   * associated with the received data. For example, if the
-   * socket_base::message_end_of_record bit is set then the received data marks
-   * the end of a record. The caller must guarantee that the referenced
-   * variable remains valid until the handler is called.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.async_receive(asio::buffer(data, size), out_flags, handler);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags& out_flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive(
-        this->get_implementation(), buffers, 0, out_flags,
-        ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive_with_flags(
-        this->get_implementation(), buffers, 0, out_flags,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous receive.
-  /**
-   * This function is used to asynchronously receive data from the sequenced
-   * data socket. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param in_flags Flags specifying how the receive call is to be made.
-   *
-   * @param out_flags Once the asynchronous operation completes, contains flags
-   * associated with the received data. For example, if the
-   * socket_base::message_end_of_record bit is set then the received data marks
-   * the end of a record. The caller must guarantee that the referenced
-   * variable remains valid until the handler is called.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.async_receive(
-   *     asio::buffer(data, size),
-   *     0, out_flags, handler);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive(
-        this->get_implementation(), buffers, in_flags, out_flags,
-        ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive_with_flags(
-        this->get_implementation(), buffers, in_flags, out_flags,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_BASIC_SEQ_PACKET_SOCKET_HPP
diff --git a/tools/sdk/include/asio/asio/basic_serial_port.hpp b/tools/sdk/include/asio/asio/basic_serial_port.hpp
deleted file mode 100644
index 32262f84295..00000000000
--- a/tools/sdk/include/asio/asio/basic_serial_port.hpp
+++ /dev/null
@@ -1,688 +0,0 @@
-//
-// basic_serial_port.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Rep Invariant Systems, Inc. (info@repinvariant.com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_SERIAL_PORT_HPP
-#define ASIO_BASIC_SERIAL_PORT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_SERIAL_PORT) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <string>
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/serial_port_base.hpp"
-#include "asio/serial_port_service.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides serial port functionality.
-/**
- * The basic_serial_port class template provides functionality that is common
- * to all serial ports.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename SerialPortService = serial_port_service>
-class basic_serial_port
-  : public basic_io_object<SerialPortService>,
-    public serial_port_base
-{
-public:
-  /// The native representation of a serial port.
-  typedef typename SerialPortService::native_handle_type native_handle_type;
-
-  /// A basic_serial_port is always the lowest layer.
-  typedef basic_serial_port<SerialPortService> lowest_layer_type;
-
-  /// Construct a basic_serial_port without opening it.
-  /**
-   * This constructor creates a serial port without opening it.
-   *
-   * @param io_context The io_context object that the serial port will use to
-   * dispatch handlers for any asynchronous operations performed on the port.
-   */
-  explicit basic_serial_port(asio::io_context& io_context)
-    : basic_io_object<SerialPortService>(io_context)
-  {
-  }
-
-  /// Construct and open a basic_serial_port.
-  /**
-   * This constructor creates and opens a serial port for the specified device
-   * name.
-   *
-   * @param io_context The io_context object that the serial port will use to
-   * dispatch handlers for any asynchronous operations performed on the port.
-   *
-   * @param device The platform-specific device name for this serial
-   * port.
-   */
-  explicit basic_serial_port(asio::io_context& io_context,
-      const char* device)
-    : basic_io_object<SerialPortService>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), device, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Construct and open a basic_serial_port.
-  /**
-   * This constructor creates and opens a serial port for the specified device
-   * name.
-   *
-   * @param io_context The io_context object that the serial port will use to
-   * dispatch handlers for any asynchronous operations performed on the port.
-   *
-   * @param device The platform-specific device name for this serial
-   * port.
-   */
-  explicit basic_serial_port(asio::io_context& io_context,
-      const std::string& device)
-    : basic_io_object<SerialPortService>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), device, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Construct a basic_serial_port on an existing native serial port.
-  /**
-   * This constructor creates a serial port object to hold an existing native
-   * serial port.
-   *
-   * @param io_context The io_context object that the serial port will use to
-   * dispatch handlers for any asynchronous operations performed on the port.
-   *
-   * @param native_serial_port A native serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_serial_port(asio::io_context& io_context,
-      const native_handle_type& native_serial_port)
-    : basic_io_object<SerialPortService>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        native_serial_port, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_serial_port from another.
-  /**
-   * This constructor moves a serial port from one object to another.
-   *
-   * @param other The other basic_serial_port object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_serial_port(io_context&) constructor.
-   */
-  basic_serial_port(basic_serial_port&& other)
-    : basic_io_object<SerialPortService>(
-        ASIO_MOVE_CAST(basic_serial_port)(other))
-  {
-  }
-
-  /// Move-assign a basic_serial_port from another.
-  /**
-   * This assignment operator moves a serial port from one object to another.
-   *
-   * @param other The other basic_serial_port object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_serial_port(io_context&) constructor.
-   */
-  basic_serial_port& operator=(basic_serial_port&& other)
-  {
-    basic_io_object<SerialPortService>::operator=(
-        ASIO_MOVE_CAST(basic_serial_port)(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * layers. Since a basic_serial_port cannot contain any further layers, it
-   * simply returns a reference to itself.
-   *
-   * @return A reference to the lowest layer in the stack of layers. Ownership
-   * is not transferred to the caller.
-   */
-  lowest_layer_type& lowest_layer()
-  {
-    return *this;
-  }
-
-  /// Get a const reference to the lowest layer.
-  /**
-   * This function returns a const reference to the lowest layer in a stack of
-   * layers. Since a basic_serial_port cannot contain any further layers, it
-   * simply returns a reference to itself.
-   *
-   * @return A const reference to the lowest layer in the stack of layers.
-   * Ownership is not transferred to the caller.
-   */
-  const lowest_layer_type& lowest_layer() const
-  {
-    return *this;
-  }
-
-  /// Open the serial port using the specified device name.
-  /**
-   * This function opens the serial port for the specified device name.
-   *
-   * @param device The platform-specific device name.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void open(const std::string& device)
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), device, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Open the serial port using the specified device name.
-  /**
-   * This function opens the serial port using the given platform-specific
-   * device name.
-   *
-   * @param device The platform-specific device name.
-   *
-   * @param ec Set the indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID open(const std::string& device,
-      asio::error_code& ec)
-  {
-    this->get_service().open(this->get_implementation(), device, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assign an existing native serial port to the serial port.
-  /*
-   * This function opens the serial port to hold an existing native serial port.
-   *
-   * @param native_serial_port A native serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void assign(const native_handle_type& native_serial_port)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        native_serial_port, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-  /// Assign an existing native serial port to the serial port.
-  /*
-   * This function opens the serial port to hold an existing native serial port.
-   *
-   * @param native_serial_port A native serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID assign(const native_handle_type& native_serial_port,
-      asio::error_code& ec)
-  {
-    this->get_service().assign(this->get_implementation(),
-        native_serial_port, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the serial port is open.
-  bool is_open() const
-  {
-    return this->get_service().is_open(this->get_implementation());
-  }
-
-  /// Close the serial port.
-  /**
-   * This function is used to close the serial port. Any asynchronous read or
-   * write operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void close()
-  {
-    asio::error_code ec;
-    this->get_service().close(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "close");
-  }
-
-  /// Close the serial port.
-  /**
-   * This function is used to close the serial port. Any asynchronous read or
-   * write operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    this->get_service().close(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native serial port representation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * serial port. This is intended to allow access to native serial port
-   * functionality that is not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return this->get_service().native_handle(this->get_implementation());
-  }
-
-  /// Cancel all asynchronous operations associated with the serial port.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all asynchronous operations associated with the serial port.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Send a break sequence to the serial port.
-  /**
-   * This function causes a break sequence of platform-specific duration to be
-   * sent out the serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void send_break()
-  {
-    asio::error_code ec;
-    this->get_service().send_break(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "send_break");
-  }
-
-  /// Send a break sequence to the serial port.
-  /**
-   * This function causes a break sequence of platform-specific duration to be
-   * sent out the serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID send_break(asio::error_code& ec)
-  {
-    this->get_service().send_break(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Set an option on the serial port.
-  /**
-   * This function is used to set an option on the serial port.
-   *
-   * @param option The option value to be set on the serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa SettableSerialPortOption @n
-   * asio::serial_port_base::baud_rate @n
-   * asio::serial_port_base::flow_control @n
-   * asio::serial_port_base::parity @n
-   * asio::serial_port_base::stop_bits @n
-   * asio::serial_port_base::character_size
-   */
-  template <typename SettableSerialPortOption>
-  void set_option(const SettableSerialPortOption& option)
-  {
-    asio::error_code ec;
-    this->get_service().set_option(this->get_implementation(), option, ec);
-    asio::detail::throw_error(ec, "set_option");
-  }
-
-  /// Set an option on the serial port.
-  /**
-   * This function is used to set an option on the serial port.
-   *
-   * @param option The option value to be set on the serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa SettableSerialPortOption @n
-   * asio::serial_port_base::baud_rate @n
-   * asio::serial_port_base::flow_control @n
-   * asio::serial_port_base::parity @n
-   * asio::serial_port_base::stop_bits @n
-   * asio::serial_port_base::character_size
-   */
-  template <typename SettableSerialPortOption>
-  ASIO_SYNC_OP_VOID set_option(const SettableSerialPortOption& option,
-      asio::error_code& ec)
-  {
-    this->get_service().set_option(this->get_implementation(), option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get an option from the serial port.
-  /**
-   * This function is used to get the current value of an option on the serial
-   * port.
-   *
-   * @param option The option value to be obtained from the serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa GettableSerialPortOption @n
-   * asio::serial_port_base::baud_rate @n
-   * asio::serial_port_base::flow_control @n
-   * asio::serial_port_base::parity @n
-   * asio::serial_port_base::stop_bits @n
-   * asio::serial_port_base::character_size
-   */
-  template <typename GettableSerialPortOption>
-  void get_option(GettableSerialPortOption& option)
-  {
-    asio::error_code ec;
-    this->get_service().get_option(this->get_implementation(), option, ec);
-    asio::detail::throw_error(ec, "get_option");
-  }
-
-  /// Get an option from the serial port.
-  /**
-   * This function is used to get the current value of an option on the serial
-   * port.
-   *
-   * @param option The option value to be obtained from the serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa GettableSerialPortOption @n
-   * asio::serial_port_base::baud_rate @n
-   * asio::serial_port_base::flow_control @n
-   * asio::serial_port_base::parity @n
-   * asio::serial_port_base::stop_bits @n
-   * asio::serial_port_base::character_size
-   */
-  template <typename GettableSerialPortOption>
-  ASIO_SYNC_OP_VOID get_option(GettableSerialPortOption& option,
-      asio::error_code& ec)
-  {
-    this->get_service().get_option(this->get_implementation(), option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Write some data to the serial port.
-  /**
-   * This function is used to write data to the serial port. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the serial port.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * serial_port.write_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "write_some");
-    return s;
-  }
-
-  /// Write some data to the serial port.
-  /**
-   * This function is used to write data to the serial port. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous write.
-  /**
-   * This function is used to asynchronously write data to the serial port.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be written to the serial port.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The write operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write function if you need to ensure that all
-   * data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * serial_port.async_write_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-    return this->get_service().async_write_some(this->get_implementation(),
-        buffers, ASIO_MOVE_CAST(WriteHandler)(handler));
-  }
-
-  /// Read some data from the serial port.
-  /**
-   * This function is used to read data from the serial port. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * serial_port.read_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "read_some");
-    return s;
-  }
-
-  /// Read some data from the serial port.
-  /**
-   * This function is used to read data from the serial port. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous read.
-  /**
-   * This function is used to asynchronously read data from the serial port.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The read operation may not read all of the requested number of bytes.
-   * Consider using the @ref async_read function if you need to ensure that the
-   * requested amount of data is read before the asynchronous operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * serial_port.async_read_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-    return this->get_service().async_read_some(this->get_implementation(),
-        buffers, ASIO_MOVE_CAST(ReadHandler)(handler));
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_SERIAL_PORT)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_BASIC_SERIAL_PORT_HPP
diff --git a/tools/sdk/include/asio/asio/basic_signal_set.hpp b/tools/sdk/include/asio/asio/basic_signal_set.hpp
deleted file mode 100644
index cf34643f8f3..00000000000
--- a/tools/sdk/include/asio/asio/basic_signal_set.hpp
+++ /dev/null
@@ -1,391 +0,0 @@
-//
-// basic_signal_set.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_SIGNAL_SET_HPP
-#define ASIO_BASIC_SIGNAL_SET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/signal_set_service.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides signal functionality.
-/**
- * The basic_signal_set class template provides the ability to perform an
- * asynchronous wait for one or more signals to occur.
- *
- * Most applications will use the asio::signal_set typedef.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Example
- * Performing an asynchronous wait:
- * @code
- * void handler(
- *     const asio::error_code& error,
- *     int signal_number)
- * {
- *   if (!error)
- *   {
- *     // A signal occurred.
- *   }
- * }
- *
- * ...
- *
- * // Construct a signal set registered for process termination.
- * asio::signal_set signals(io_context, SIGINT, SIGTERM);
- *
- * // Start an asynchronous wait for one of the signals to occur.
- * signals.async_wait(handler);
- * @endcode
- *
- * @par Queueing of signal notifications
- *
- * If a signal is registered with a signal_set, and the signal occurs when
- * there are no waiting handlers, then the signal notification is queued. The
- * next async_wait operation on that signal_set will dequeue the notification.
- * If multiple notifications are queued, subsequent async_wait operations
- * dequeue them one at a time. Signal notifications are dequeued in order of
- * ascending signal number.
- *
- * If a signal number is removed from a signal_set (using the @c remove or @c
- * erase member functions) then any queued notifications for that signal are
- * discarded.
- *
- * @par Multiple registration of signals
- *
- * The same signal number may be registered with different signal_set objects.
- * When the signal occurs, one handler is called for each signal_set object.
- *
- * Note that multiple registration only works for signals that are registered
- * using Asio. The application must not also register a signal handler using
- * functions such as @c signal() or @c sigaction().
- *
- * @par Signal masking on POSIX platforms
- *
- * POSIX allows signals to be blocked using functions such as @c sigprocmask()
- * and @c pthread_sigmask(). For signals to be delivered, programs must ensure
- * that any signals registered using signal_set objects are unblocked in at
- * least one thread.
- */
-template <typename SignalSetService = signal_set_service>
-class basic_signal_set
-  : public basic_io_object<SignalSetService>
-{
-public:
-  /// Construct a signal set without adding any signals.
-  /**
-   * This constructor creates a signal set without registering for any signals.
-   *
-   * @param io_context The io_context object that the signal set will use to
-   * dispatch handlers for any asynchronous operations performed on the set.
-   */
-  explicit basic_signal_set(asio::io_context& io_context)
-    : basic_io_object<SignalSetService>(io_context)
-  {
-  }
-
-  /// Construct a signal set and add one signal.
-  /**
-   * This constructor creates a signal set and registers for one signal.
-   *
-   * @param io_context The io_context object that the signal set will use to
-   * dispatch handlers for any asynchronous operations performed on the set.
-   *
-   * @param signal_number_1 The signal number to be added.
-   *
-   * @note This constructor is equivalent to performing:
-   * @code asio::signal_set signals(io_context);
-   * signals.add(signal_number_1); @endcode
-   */
-  basic_signal_set(asio::io_context& io_context, int signal_number_1)
-    : basic_io_object<SignalSetService>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().add(this->get_implementation(), signal_number_1, ec);
-    asio::detail::throw_error(ec, "add");
-  }
-
-  /// Construct a signal set and add two signals.
-  /**
-   * This constructor creates a signal set and registers for two signals.
-   *
-   * @param io_context The io_context object that the signal set will use to
-   * dispatch handlers for any asynchronous operations performed on the set.
-   *
-   * @param signal_number_1 The first signal number to be added.
-   *
-   * @param signal_number_2 The second signal number to be added.
-   *
-   * @note This constructor is equivalent to performing:
-   * @code asio::signal_set signals(io_context);
-   * signals.add(signal_number_1);
-   * signals.add(signal_number_2); @endcode
-   */
-  basic_signal_set(asio::io_context& io_context, int signal_number_1,
-      int signal_number_2)
-    : basic_io_object<SignalSetService>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().add(this->get_implementation(), signal_number_1, ec);
-    asio::detail::throw_error(ec, "add");
-    this->get_service().add(this->get_implementation(), signal_number_2, ec);
-    asio::detail::throw_error(ec, "add");
-  }
-
-  /// Construct a signal set and add three signals.
-  /**
-   * This constructor creates a signal set and registers for three signals.
-   *
-   * @param io_context The io_context object that the signal set will use to
-   * dispatch handlers for any asynchronous operations performed on the set.
-   *
-   * @param signal_number_1 The first signal number to be added.
-   *
-   * @param signal_number_2 The second signal number to be added.
-   *
-   * @param signal_number_3 The third signal number to be added.
-   *
-   * @note This constructor is equivalent to performing:
-   * @code asio::signal_set signals(io_context);
-   * signals.add(signal_number_1);
-   * signals.add(signal_number_2);
-   * signals.add(signal_number_3); @endcode
-   */
-  basic_signal_set(asio::io_context& io_context, int signal_number_1,
-      int signal_number_2, int signal_number_3)
-    : basic_io_object<SignalSetService>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().add(this->get_implementation(), signal_number_1, ec);
-    asio::detail::throw_error(ec, "add");
-    this->get_service().add(this->get_implementation(), signal_number_2, ec);
-    asio::detail::throw_error(ec, "add");
-    this->get_service().add(this->get_implementation(), signal_number_3, ec);
-    asio::detail::throw_error(ec, "add");
-  }
-
-  /// Add a signal to a signal_set.
-  /**
-   * This function adds the specified signal to the set. It has no effect if the
-   * signal is already in the set.
-   *
-   * @param signal_number The signal to be added to the set.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void add(int signal_number)
-  {
-    asio::error_code ec;
-    this->get_service().add(this->get_implementation(), signal_number, ec);
-    asio::detail::throw_error(ec, "add");
-  }
-
-  /// Add a signal to a signal_set.
-  /**
-   * This function adds the specified signal to the set. It has no effect if the
-   * signal is already in the set.
-   *
-   * @param signal_number The signal to be added to the set.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID add(int signal_number, asio::error_code& ec)
-  {
-    this->get_service().add(this->get_implementation(), signal_number, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Remove a signal from a signal_set.
-  /**
-   * This function removes the specified signal from the set. It has no effect
-   * if the signal is not in the set.
-   *
-   * @param signal_number The signal to be removed from the set.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Removes any notifications that have been queued for the specified
-   * signal number.
-   */
-  void remove(int signal_number)
-  {
-    asio::error_code ec;
-    this->get_service().remove(this->get_implementation(), signal_number, ec);
-    asio::detail::throw_error(ec, "remove");
-  }
-
-  /// Remove a signal from a signal_set.
-  /**
-   * This function removes the specified signal from the set. It has no effect
-   * if the signal is not in the set.
-   *
-   * @param signal_number The signal to be removed from the set.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Removes any notifications that have been queued for the specified
-   * signal number.
-   */
-  ASIO_SYNC_OP_VOID remove(int signal_number,
-      asio::error_code& ec)
-  {
-    this->get_service().remove(this->get_implementation(), signal_number, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Remove all signals from a signal_set.
-  /**
-   * This function removes all signals from the set. It has no effect if the set
-   * is already empty.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Removes all queued notifications.
-   */
-  void clear()
-  {
-    asio::error_code ec;
-    this->get_service().clear(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "clear");
-  }
-
-  /// Remove all signals from a signal_set.
-  /**
-   * This function removes all signals from the set. It has no effect if the set
-   * is already empty.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Removes all queued notifications.
-   */
-  ASIO_SYNC_OP_VOID clear(asio::error_code& ec)
-  {
-    this->get_service().clear(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Cancel all operations associated with the signal set.
-  /**
-   * This function forces the completion of any pending asynchronous wait
-   * operations against the signal set. The handler for each cancelled
-   * operation will be invoked with the asio::error::operation_aborted
-   * error code.
-   *
-   * Cancellation does not alter the set of registered signals.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If a registered signal occurred before cancel() is called, then the
-   * handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all operations associated with the signal set.
-  /**
-   * This function forces the completion of any pending asynchronous wait
-   * operations against the signal set. The handler for each cancelled
-   * operation will be invoked with the asio::error::operation_aborted
-   * error code.
-   *
-   * Cancellation does not alter the set of registered signals.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note If a registered signal occurred before cancel() is called, then the
-   * handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous operation to wait for a signal to be delivered.
-  /**
-   * This function may be used to initiate an asynchronous wait against the
-   * signal set. It always returns immediately.
-   *
-   * For each call to async_wait(), the supplied handler will be called exactly
-   * once. The handler will be called when:
-   *
-   * @li One of the registered signals in the signal set occurs; or
-   *
-   * @li The signal set was cancelled, in which case the handler is passed the
-   * error code asio::error::operation_aborted.
-   *
-   * @param handler The handler to be called when the signal occurs. Copies
-   * will be made of the handler as required. The function signature of the
-   * handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   int signal_number // Indicates which signal occurred.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename SignalHandler>
-  ASIO_INITFN_RESULT_TYPE(SignalHandler,
-      void (asio::error_code, int))
-  async_wait(ASIO_MOVE_ARG(SignalHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a SignalHandler.
-    ASIO_SIGNAL_HANDLER_CHECK(SignalHandler, handler) type_check;
-
-    return this->get_service().async_wait(this->get_implementation(),
-        ASIO_MOVE_CAST(SignalHandler)(handler));
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_BASIC_SIGNAL_SET_HPP
diff --git a/tools/sdk/include/asio/asio/basic_socket.hpp b/tools/sdk/include/asio/asio/basic_socket.hpp
deleted file mode 100644
index 3dfacb42496..00000000000
--- a/tools/sdk/include/asio/asio/basic_socket.hpp
+++ /dev/null
@@ -1,1757 +0,0 @@
-//
-// basic_socket.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_SOCKET_HPP
-#define ASIO_BASIC_SOCKET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/async_result.hpp"
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-#include "asio/post.hpp"
-#include "asio/socket_base.hpp"
-
-#if defined(ASIO_HAS_MOVE)
-# include <utility>
-#endif // defined(ASIO_HAS_MOVE)
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-# if defined(ASIO_WINDOWS_RUNTIME)
-#  include "asio/detail/winrt_ssocket_service.hpp"
-#  define ASIO_SVC_T detail::winrt_ssocket_service<Protocol>
-# elif defined(ASIO_HAS_IOCP)
-#  include "asio/detail/win_iocp_socket_service.hpp"
-#  define ASIO_SVC_T detail::win_iocp_socket_service<Protocol>
-# else
-#  include "asio/detail/reactive_socket_service.hpp"
-#  define ASIO_SVC_T detail::reactive_socket_service<Protocol>
-# endif
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides socket functionality.
-/**
- * The basic_socket class template provides functionality that is common to both
- * stream-oriented and datagram-oriented sockets.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename Protocol ASIO_SVC_TPARAM>
-class basic_socket
-  : ASIO_SVC_ACCESS basic_io_object<ASIO_SVC_T>,
-    public socket_base
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// The native representation of a socket.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename ASIO_SVC_T::native_handle_type native_handle_type;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-#if !defined(ASIO_NO_EXTENSIONS)
-  /// A basic_socket is always the lowest layer.
-  typedef basic_socket<Protocol ASIO_SVC_TARG> lowest_layer_type;
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-  /// Construct a basic_socket without opening it.
-  /**
-   * This constructor creates a socket without opening it.
-   *
-   * @param io_context The io_context object that the socket will use to
-   * dispatch handlers for any asynchronous operations performed on the socket.
-   */
-  explicit basic_socket(asio::io_context& io_context)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-  }
-
-  /// Construct and open a basic_socket.
-  /**
-   * This constructor creates and opens a socket.
-   *
-   * @param io_context The io_context object that the socket will use to
-   * dispatch handlers for any asynchronous operations performed on the socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_socket(asio::io_context& io_context,
-      const protocol_type& protocol)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), protocol, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Construct a basic_socket, opening it and binding it to the given local
-  /// endpoint.
-  /**
-   * This constructor creates a socket and automatically opens it bound to the
-   * specified endpoint on the local machine. The protocol used is the protocol
-   * associated with the given endpoint.
-   *
-   * @param io_context The io_context object that the socket will use to
-   * dispatch handlers for any asynchronous operations performed on the socket.
-   *
-   * @param endpoint An endpoint on the local machine to which the socket will
-   * be bound.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_socket(asio::io_context& io_context,
-      const endpoint_type& endpoint)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    const protocol_type protocol = endpoint.protocol();
-    this->get_service().open(this->get_implementation(), protocol, ec);
-    asio::detail::throw_error(ec, "open");
-    this->get_service().bind(this->get_implementation(), endpoint, ec);
-    asio::detail::throw_error(ec, "bind");
-  }
-
-  /// Construct a basic_socket on an existing native socket.
-  /**
-   * This constructor creates a socket object to hold an existing native socket.
-   *
-   * @param io_context The io_context object that the socket will use to
-   * dispatch handlers for any asynchronous operations performed on the socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @param native_socket A native socket.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_socket(asio::io_context& io_context,
-      const protocol_type& protocol, const native_handle_type& native_socket)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        protocol, native_socket, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_socket from another.
-  /**
-   * This constructor moves a socket from one object to another.
-   *
-   * @param other The other basic_socket object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_socket(io_context&) constructor.
-   */
-  basic_socket(basic_socket&& other)
-    : basic_io_object<ASIO_SVC_T>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_socket from another.
-  /**
-   * This assignment operator moves a socket from one object to another.
-   *
-   * @param other The other basic_socket object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_socket(io_context&) constructor.
-   */
-  basic_socket& operator=(basic_socket&& other)
-  {
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(other));
-    return *this;
-  }
-
-  // All sockets have access to each other's implementations.
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  friend class basic_socket;
-
-  /// Move-construct a basic_socket from a socket of another protocol type.
-  /**
-   * This constructor moves a socket from one object to another.
-   *
-   * @param other The other basic_socket object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  basic_socket(basic_socket<Protocol1 ASIO_SVC_TARG1>&& other,
-      typename enable_if<is_convertible<Protocol1, Protocol>::value>::type* = 0)
-    : basic_io_object<ASIO_SVC_T>(
-        other.get_service(), other.get_implementation())
-  {
-  }
-
-  /// Move-assign a basic_socket from a socket of another protocol type.
-  /**
-   * This assignment operator moves a socket from one object to another.
-   *
-   * @param other The other basic_socket object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  typename enable_if<is_convertible<Protocol1, Protocol>::value,
-      basic_socket>::type& operator=(
-        basic_socket<Protocol1 ASIO_SVC_TARG1>&& other)
-  {
-    basic_socket tmp(std::move(other));
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(tmp));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  // These functions are provided by basic_io_object<>.
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<ASIO_SVC_T>::get_executor();
-  }
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if !defined(ASIO_NO_EXTENSIONS)
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * layers. Since a basic_socket cannot contain any further layers, it simply
-   * returns a reference to itself.
-   *
-   * @return A reference to the lowest layer in the stack of layers. Ownership
-   * is not transferred to the caller.
-   */
-  lowest_layer_type& lowest_layer()
-  {
-    return *this;
-  }
-
-  /// Get a const reference to the lowest layer.
-  /**
-   * This function returns a const reference to the lowest layer in a stack of
-   * layers. Since a basic_socket cannot contain any further layers, it simply
-   * returns a reference to itself.
-   *
-   * @return A const reference to the lowest layer in the stack of layers.
-   * Ownership is not transferred to the caller.
-   */
-  const lowest_layer_type& lowest_layer() const
-  {
-    return *this;
-  }
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-  /// Open the socket using the specified protocol.
-  /**
-   * This function opens the socket so that it will use the specified protocol.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * socket.open(asio::ip::tcp::v4());
-   * @endcode
-   */
-  void open(const protocol_type& protocol = protocol_type())
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), protocol, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Open the socket using the specified protocol.
-  /**
-   * This function opens the socket so that it will use the specified protocol.
-   *
-   * @param protocol An object specifying which protocol is to be used.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * asio::error_code ec;
-   * socket.open(asio::ip::tcp::v4(), ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID open(const protocol_type& protocol,
-      asio::error_code& ec)
-  {
-    this->get_service().open(this->get_implementation(), protocol, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assign an existing native socket to the socket.
-  /*
-   * This function opens the socket to hold an existing native socket.
-   *
-   * @param protocol An object specifying which protocol is to be used.
-   *
-   * @param native_socket A native socket.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void assign(const protocol_type& protocol,
-      const native_handle_type& native_socket)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        protocol, native_socket, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-  /// Assign an existing native socket to the socket.
-  /*
-   * This function opens the socket to hold an existing native socket.
-   *
-   * @param protocol An object specifying which protocol is to be used.
-   *
-   * @param native_socket A native socket.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID assign(const protocol_type& protocol,
-      const native_handle_type& native_socket, asio::error_code& ec)
-  {
-    this->get_service().assign(this->get_implementation(),
-        protocol, native_socket, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is open.
-  bool is_open() const
-  {
-    return this->get_service().is_open(this->get_implementation());
-  }
-
-  /// Close the socket.
-  /**
-   * This function is used to close the socket. Any asynchronous send, receive
-   * or connect operations will be cancelled immediately, and will complete
-   * with the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure. Note that, even if
-   * the function indicates an error, the underlying descriptor is closed.
-   *
-   * @note For portable behaviour with respect to graceful closure of a
-   * connected socket, call shutdown() before closing the socket.
-   */
-  void close()
-  {
-    asio::error_code ec;
-    this->get_service().close(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "close");
-  }
-
-  /// Close the socket.
-  /**
-   * This function is used to close the socket. Any asynchronous send, receive
-   * or connect operations will be cancelled immediately, and will complete
-   * with the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any. Note that, even if
-   * the function indicates an error, the underlying descriptor is closed.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::error_code ec;
-   * socket.close(ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   *
-   * @note For portable behaviour with respect to graceful closure of a
-   * connected socket, call shutdown() before closing the socket.
-   */
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    this->get_service().close(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Release ownership of the underlying native socket.
-  /**
-   * This function causes all outstanding asynchronous connect, send and receive
-   * operations to finish immediately, and the handlers for cancelled operations
-   * will be passed the asio::error::operation_aborted error. Ownership
-   * of the native socket is then transferred to the caller.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note This function is unsupported on Windows versions prior to Windows
-   * 8.1, and will fail with asio::error::operation_not_supported on
-   * these platforms.
-   */
-#if defined(ASIO_MSVC) && (ASIO_MSVC >= 1400) \
-  && (!defined(_WIN32_WINNT) || _WIN32_WINNT < 0x0603)
-  __declspec(deprecated("This function always fails with "
-        "operation_not_supported when used on Windows versions "
-        "prior to Windows 8.1."))
-#endif
-  native_handle_type release()
-  {
-    asio::error_code ec;
-    native_handle_type s = this->get_service().release(
-        this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "release");
-    return s;
-  }
-
-  /// Release ownership of the underlying native socket.
-  /**
-   * This function causes all outstanding asynchronous connect, send and receive
-   * operations to finish immediately, and the handlers for cancelled operations
-   * will be passed the asio::error::operation_aborted error. Ownership
-   * of the native socket is then transferred to the caller.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note This function is unsupported on Windows versions prior to Windows
-   * 8.1, and will fail with asio::error::operation_not_supported on
-   * these platforms.
-   */
-#if defined(ASIO_MSVC) && (ASIO_MSVC >= 1400) \
-  && (!defined(_WIN32_WINNT) || _WIN32_WINNT < 0x0603)
-  __declspec(deprecated("This function always fails with "
-        "operation_not_supported when used on Windows versions "
-        "prior to Windows 8.1."))
-#endif
-  native_handle_type release(asio::error_code& ec)
-  {
-    return this->get_service().release(this->get_implementation(), ec);
-  }
-
-  /// Get the native socket representation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * socket. This is intended to allow access to native socket functionality
-   * that is not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return this->get_service().native_handle(this->get_implementation());
-  }
-
-  /// Cancel all asynchronous operations associated with the socket.
-  /**
-   * This function causes all outstanding asynchronous connect, send and receive
-   * operations to finish immediately, and the handlers for cancelled operations
-   * will be passed the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls to cancel() will always fail with
-   * asio::error::operation_not_supported when run on Windows XP, Windows
-   * Server 2003, and earlier versions of Windows, unless
-   * ASIO_ENABLE_CANCELIO is defined. However, the CancelIo function has
-   * two issues that should be considered before enabling its use:
-   *
-   * @li It will only cancel asynchronous operations that were initiated in the
-   * current thread.
-   *
-   * @li It can appear to complete without error, but the request to cancel the
-   * unfinished operations may be silently ignored by the operating system.
-   * Whether it works or not seems to depend on the drivers that are installed.
-   *
-   * For portable cancellation, consider using one of the following
-   * alternatives:
-   *
-   * @li Disable asio's I/O completion port backend by defining
-   * ASIO_DISABLE_IOCP.
-   *
-   * @li Use the close() function to simultaneously cancel the outstanding
-   * operations and close the socket.
-   *
-   * When running on Windows Vista, Windows Server 2008, and later, the
-   * CancelIoEx function is always used. This function does not have the
-   * problems described above.
-   */
-#if defined(ASIO_MSVC) && (ASIO_MSVC >= 1400) \
-  && (!defined(_WIN32_WINNT) || _WIN32_WINNT < 0x0600) \
-  && !defined(ASIO_ENABLE_CANCELIO)
-  __declspec(deprecated("By default, this function always fails with "
-        "operation_not_supported when used on Windows XP, Windows Server 2003, "
-        "or earlier. Consult documentation for details."))
-#endif
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all asynchronous operations associated with the socket.
-  /**
-   * This function causes all outstanding asynchronous connect, send and receive
-   * operations to finish immediately, and the handlers for cancelled operations
-   * will be passed the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls to cancel() will always fail with
-   * asio::error::operation_not_supported when run on Windows XP, Windows
-   * Server 2003, and earlier versions of Windows, unless
-   * ASIO_ENABLE_CANCELIO is defined. However, the CancelIo function has
-   * two issues that should be considered before enabling its use:
-   *
-   * @li It will only cancel asynchronous operations that were initiated in the
-   * current thread.
-   *
-   * @li It can appear to complete without error, but the request to cancel the
-   * unfinished operations may be silently ignored by the operating system.
-   * Whether it works or not seems to depend on the drivers that are installed.
-   *
-   * For portable cancellation, consider using one of the following
-   * alternatives:
-   *
-   * @li Disable asio's I/O completion port backend by defining
-   * ASIO_DISABLE_IOCP.
-   *
-   * @li Use the close() function to simultaneously cancel the outstanding
-   * operations and close the socket.
-   *
-   * When running on Windows Vista, Windows Server 2008, and later, the
-   * CancelIoEx function is always used. This function does not have the
-   * problems described above.
-   */
-#if defined(ASIO_MSVC) && (ASIO_MSVC >= 1400) \
-  && (!defined(_WIN32_WINNT) || _WIN32_WINNT < 0x0600) \
-  && !defined(ASIO_ENABLE_CANCELIO)
-  __declspec(deprecated("By default, this function always fails with "
-        "operation_not_supported when used on Windows XP, Windows Server 2003, "
-        "or earlier. Consult documentation for details."))
-#endif
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is at the out-of-band data mark.
-  /**
-   * This function is used to check whether the socket input is currently
-   * positioned at the out-of-band data mark.
-   *
-   * @return A bool indicating whether the socket is at the out-of-band data
-   * mark.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  bool at_mark() const
-  {
-    asio::error_code ec;
-    bool b = this->get_service().at_mark(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "at_mark");
-    return b;
-  }
-
-  /// Determine whether the socket is at the out-of-band data mark.
-  /**
-   * This function is used to check whether the socket input is currently
-   * positioned at the out-of-band data mark.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return A bool indicating whether the socket is at the out-of-band data
-   * mark.
-   */
-  bool at_mark(asio::error_code& ec) const
-  {
-    return this->get_service().at_mark(this->get_implementation(), ec);
-  }
-
-  /// Determine the number of bytes available for reading.
-  /**
-   * This function is used to determine the number of bytes that may be read
-   * without blocking.
-   *
-   * @return The number of bytes that may be read without blocking, or 0 if an
-   * error occurs.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  std::size_t available() const
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().available(
-        this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "available");
-    return s;
-  }
-
-  /// Determine the number of bytes available for reading.
-  /**
-   * This function is used to determine the number of bytes that may be read
-   * without blocking.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of bytes that may be read without blocking, or 0 if an
-   * error occurs.
-   */
-  std::size_t available(asio::error_code& ec) const
-  {
-    return this->get_service().available(this->get_implementation(), ec);
-  }
-
-  /// Bind the socket to the given local endpoint.
-  /**
-   * This function binds the socket to the specified endpoint on the local
-   * machine.
-   *
-   * @param endpoint An endpoint on the local machine to which the socket will
-   * be bound.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * socket.open(asio::ip::tcp::v4());
-   * socket.bind(asio::ip::tcp::endpoint(
-   *       asio::ip::tcp::v4(), 12345));
-   * @endcode
-   */
-  void bind(const endpoint_type& endpoint)
-  {
-    asio::error_code ec;
-    this->get_service().bind(this->get_implementation(), endpoint, ec);
-    asio::detail::throw_error(ec, "bind");
-  }
-
-  /// Bind the socket to the given local endpoint.
-  /**
-   * This function binds the socket to the specified endpoint on the local
-   * machine.
-   *
-   * @param endpoint An endpoint on the local machine to which the socket will
-   * be bound.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * socket.open(asio::ip::tcp::v4());
-   * asio::error_code ec;
-   * socket.bind(asio::ip::tcp::endpoint(
-   *       asio::ip::tcp::v4(), 12345), ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID bind(const endpoint_type& endpoint,
-      asio::error_code& ec)
-  {
-    this->get_service().bind(this->get_implementation(), endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Connect the socket to the specified endpoint.
-  /**
-   * This function is used to connect a socket to the specified remote endpoint.
-   * The function call will block until the connection is successfully made or
-   * an error occurs.
-   *
-   * The socket is automatically opened if it is not already open. If the
-   * connect fails, and the socket was automatically opened, the socket is
-   * not returned to the closed state.
-   *
-   * @param peer_endpoint The remote endpoint to which the socket will be
-   * connected.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * asio::ip::tcp::endpoint endpoint(
-   *     asio::ip::address::from_string("1.2.3.4"), 12345);
-   * socket.connect(endpoint);
-   * @endcode
-   */
-  void connect(const endpoint_type& peer_endpoint)
-  {
-    asio::error_code ec;
-    if (!is_open())
-    {
-      this->get_service().open(this->get_implementation(),
-          peer_endpoint.protocol(), ec);
-      asio::detail::throw_error(ec, "connect");
-    }
-    this->get_service().connect(this->get_implementation(), peer_endpoint, ec);
-    asio::detail::throw_error(ec, "connect");
-  }
-
-  /// Connect the socket to the specified endpoint.
-  /**
-   * This function is used to connect a socket to the specified remote endpoint.
-   * The function call will block until the connection is successfully made or
-   * an error occurs.
-   *
-   * The socket is automatically opened if it is not already open. If the
-   * connect fails, and the socket was automatically opened, the socket is
-   * not returned to the closed state.
-   *
-   * @param peer_endpoint The remote endpoint to which the socket will be
-   * connected.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * asio::ip::tcp::endpoint endpoint(
-   *     asio::ip::address::from_string("1.2.3.4"), 12345);
-   * asio::error_code ec;
-   * socket.connect(endpoint, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID connect(const endpoint_type& peer_endpoint,
-      asio::error_code& ec)
-  {
-    if (!is_open())
-    {
-      this->get_service().open(this->get_implementation(),
-            peer_endpoint.protocol(), ec);
-      if (ec)
-      {
-        ASIO_SYNC_OP_VOID_RETURN(ec);
-      }
-    }
-
-    this->get_service().connect(this->get_implementation(), peer_endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous connect.
-  /**
-   * This function is used to asynchronously connect a socket to the specified
-   * remote endpoint. The function call always returns immediately.
-   *
-   * The socket is automatically opened if it is not already open. If the
-   * connect fails, and the socket was automatically opened, the socket is
-   * not returned to the closed state.
-   *
-   * @param peer_endpoint The remote endpoint to which the socket will be
-   * connected. Copies will be made of the endpoint object as required.
-   *
-   * @param handler The handler to be called when the connection operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void connect_handler(const asio::error_code& error)
-   * {
-   *   if (!error)
-   *   {
-   *     // Connect succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::ip::tcp::socket socket(io_context);
-   * asio::ip::tcp::endpoint endpoint(
-   *     asio::ip::address::from_string("1.2.3.4"), 12345);
-   * socket.async_connect(endpoint, connect_handler);
-   * @endcode
-   */
-  template <typename ConnectHandler>
-  ASIO_INITFN_RESULT_TYPE(ConnectHandler,
-      void (asio::error_code))
-  async_connect(const endpoint_type& peer_endpoint,
-      ASIO_MOVE_ARG(ConnectHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ConnectHandler.
-    ASIO_CONNECT_HANDLER_CHECK(ConnectHandler, handler) type_check;
-
-    if (!is_open())
-    {
-      asio::error_code ec;
-      const protocol_type protocol = peer_endpoint.protocol();
-      this->get_service().open(this->get_implementation(), protocol, ec);
-      if (ec)
-      {
-        async_completion<ConnectHandler,
-          void (asio::error_code)> init(handler);
-
-        asio::post(this->get_executor(),
-            asio::detail::bind_handler(
-              ASIO_MOVE_CAST(ASIO_HANDLER_TYPE(
-                ConnectHandler, void (asio::error_code)))(
-                  init.completion_handler), ec));
-
-        return init.result.get();
-      }
-    }
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_connect(this->get_implementation(),
-        peer_endpoint, ASIO_MOVE_CAST(ConnectHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ConnectHandler,
-      void (asio::error_code)> init(handler);
-
-    this->get_service().async_connect(
-        this->get_implementation(), peer_endpoint, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Set an option on the socket.
-  /**
-   * This function is used to set an option on the socket.
-   *
-   * @param option The new option value to be set on the socket.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa SettableSocketOption @n
-   * asio::socket_base::broadcast @n
-   * asio::socket_base::do_not_route @n
-   * asio::socket_base::keep_alive @n
-   * asio::socket_base::linger @n
-   * asio::socket_base::receive_buffer_size @n
-   * asio::socket_base::receive_low_watermark @n
-   * asio::socket_base::reuse_address @n
-   * asio::socket_base::send_buffer_size @n
-   * asio::socket_base::send_low_watermark @n
-   * asio::ip::multicast::join_group @n
-   * asio::ip::multicast::leave_group @n
-   * asio::ip::multicast::enable_loopback @n
-   * asio::ip::multicast::outbound_interface @n
-   * asio::ip::multicast::hops @n
-   * asio::ip::tcp::no_delay
-   *
-   * @par Example
-   * Setting the IPPROTO_TCP/TCP_NODELAY option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::ip::tcp::no_delay option(true);
-   * socket.set_option(option);
-   * @endcode
-   */
-  template <typename SettableSocketOption>
-  void set_option(const SettableSocketOption& option)
-  {
-    asio::error_code ec;
-    this->get_service().set_option(this->get_implementation(), option, ec);
-    asio::detail::throw_error(ec, "set_option");
-  }
-
-  /// Set an option on the socket.
-  /**
-   * This function is used to set an option on the socket.
-   *
-   * @param option The new option value to be set on the socket.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa SettableSocketOption @n
-   * asio::socket_base::broadcast @n
-   * asio::socket_base::do_not_route @n
-   * asio::socket_base::keep_alive @n
-   * asio::socket_base::linger @n
-   * asio::socket_base::receive_buffer_size @n
-   * asio::socket_base::receive_low_watermark @n
-   * asio::socket_base::reuse_address @n
-   * asio::socket_base::send_buffer_size @n
-   * asio::socket_base::send_low_watermark @n
-   * asio::ip::multicast::join_group @n
-   * asio::ip::multicast::leave_group @n
-   * asio::ip::multicast::enable_loopback @n
-   * asio::ip::multicast::outbound_interface @n
-   * asio::ip::multicast::hops @n
-   * asio::ip::tcp::no_delay
-   *
-   * @par Example
-   * Setting the IPPROTO_TCP/TCP_NODELAY option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::ip::tcp::no_delay option(true);
-   * asio::error_code ec;
-   * socket.set_option(option, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  template <typename SettableSocketOption>
-  ASIO_SYNC_OP_VOID set_option(const SettableSocketOption& option,
-      asio::error_code& ec)
-  {
-    this->get_service().set_option(this->get_implementation(), option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get an option from the socket.
-  /**
-   * This function is used to get the current value of an option on the socket.
-   *
-   * @param option The option value to be obtained from the socket.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa GettableSocketOption @n
-   * asio::socket_base::broadcast @n
-   * asio::socket_base::do_not_route @n
-   * asio::socket_base::keep_alive @n
-   * asio::socket_base::linger @n
-   * asio::socket_base::receive_buffer_size @n
-   * asio::socket_base::receive_low_watermark @n
-   * asio::socket_base::reuse_address @n
-   * asio::socket_base::send_buffer_size @n
-   * asio::socket_base::send_low_watermark @n
-   * asio::ip::multicast::join_group @n
-   * asio::ip::multicast::leave_group @n
-   * asio::ip::multicast::enable_loopback @n
-   * asio::ip::multicast::outbound_interface @n
-   * asio::ip::multicast::hops @n
-   * asio::ip::tcp::no_delay
-   *
-   * @par Example
-   * Getting the value of the SOL_SOCKET/SO_KEEPALIVE option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::ip::tcp::socket::keep_alive option;
-   * socket.get_option(option);
-   * bool is_set = option.value();
-   * @endcode
-   */
-  template <typename GettableSocketOption>
-  void get_option(GettableSocketOption& option) const
-  {
-    asio::error_code ec;
-    this->get_service().get_option(this->get_implementation(), option, ec);
-    asio::detail::throw_error(ec, "get_option");
-  }
-
-  /// Get an option from the socket.
-  /**
-   * This function is used to get the current value of an option on the socket.
-   *
-   * @param option The option value to be obtained from the socket.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa GettableSocketOption @n
-   * asio::socket_base::broadcast @n
-   * asio::socket_base::do_not_route @n
-   * asio::socket_base::keep_alive @n
-   * asio::socket_base::linger @n
-   * asio::socket_base::receive_buffer_size @n
-   * asio::socket_base::receive_low_watermark @n
-   * asio::socket_base::reuse_address @n
-   * asio::socket_base::send_buffer_size @n
-   * asio::socket_base::send_low_watermark @n
-   * asio::ip::multicast::join_group @n
-   * asio::ip::multicast::leave_group @n
-   * asio::ip::multicast::enable_loopback @n
-   * asio::ip::multicast::outbound_interface @n
-   * asio::ip::multicast::hops @n
-   * asio::ip::tcp::no_delay
-   *
-   * @par Example
-   * Getting the value of the SOL_SOCKET/SO_KEEPALIVE option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::ip::tcp::socket::keep_alive option;
-   * asio::error_code ec;
-   * socket.get_option(option, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * bool is_set = option.value();
-   * @endcode
-   */
-  template <typename GettableSocketOption>
-  ASIO_SYNC_OP_VOID get_option(GettableSocketOption& option,
-      asio::error_code& ec) const
-  {
-    this->get_service().get_option(this->get_implementation(), option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the socket.
-  /**
-   * This function is used to execute an IO control command on the socket.
-   *
-   * @param command The IO control command to be performed on the socket.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa IoControlCommand @n
-   * asio::socket_base::bytes_readable @n
-   * asio::socket_base::non_blocking_io
-   *
-   * @par Example
-   * Getting the number of bytes ready to read:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::ip::tcp::socket::bytes_readable command;
-   * socket.io_control(command);
-   * std::size_t bytes_readable = command.get();
-   * @endcode
-   */
-  template <typename IoControlCommand>
-  void io_control(IoControlCommand& command)
-  {
-    asio::error_code ec;
-    this->get_service().io_control(this->get_implementation(), command, ec);
-    asio::detail::throw_error(ec, "io_control");
-  }
-
-  /// Perform an IO control command on the socket.
-  /**
-   * This function is used to execute an IO control command on the socket.
-   *
-   * @param command The IO control command to be performed on the socket.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa IoControlCommand @n
-   * asio::socket_base::bytes_readable @n
-   * asio::socket_base::non_blocking_io
-   *
-   * @par Example
-   * Getting the number of bytes ready to read:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::ip::tcp::socket::bytes_readable command;
-   * asio::error_code ec;
-   * socket.io_control(command, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * std::size_t bytes_readable = command.get();
-   * @endcode
-   */
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(IoControlCommand& command,
-      asio::error_code& ec)
-  {
-    this->get_service().io_control(this->get_implementation(), command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the socket.
-  /**
-   * @returns @c true if the socket's synchronous operations will fail with
-   * asio::error::would_block if they are unable to perform the requested
-   * operation immediately. If @c false, synchronous operations will block
-   * until complete.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  bool non_blocking() const
-  {
-    return this->get_service().non_blocking(this->get_implementation());
-  }
-
-  /// Sets the non-blocking mode of the socket.
-  /**
-   * @param mode If @c true, the socket's synchronous operations will fail with
-   * asio::error::would_block if they are unable to perform the requested
-   * operation immediately. If @c false, synchronous operations will block
-   * until complete.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  void non_blocking(bool mode)
-  {
-    asio::error_code ec;
-    this->get_service().non_blocking(this->get_implementation(), mode, ec);
-    asio::detail::throw_error(ec, "non_blocking");
-  }
-
-  /// Sets the non-blocking mode of the socket.
-  /**
-   * @param mode If @c true, the socket's synchronous operations will fail with
-   * asio::error::would_block if they are unable to perform the requested
-   * operation immediately. If @c false, synchronous operations will block
-   * until complete.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  ASIO_SYNC_OP_VOID non_blocking(
-      bool mode, asio::error_code& ec)
-  {
-    this->get_service().non_blocking(this->get_implementation(), mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native socket implementation.
-  /**
-   * This function is used to retrieve the non-blocking mode of the underlying
-   * native socket. This mode has no effect on the behaviour of the socket
-   * object's synchronous operations.
-   *
-   * @returns @c true if the underlying socket is in non-blocking mode and
-   * direct system calls may fail with asio::error::would_block (or the
-   * equivalent system error).
-   *
-   * @note The current non-blocking mode is cached by the socket object.
-   * Consequently, the return value may be incorrect if the non-blocking mode
-   * was set directly on the native socket.
-   *
-   * @par Example
-   * This function is intended to allow the encapsulation of arbitrary
-   * non-blocking system calls as asynchronous operations, in a way that is
-   * transparent to the user of the socket object. The following example
-   * illustrates how Linux's @c sendfile system call might be encapsulated:
-   * @code template <typename Handler>
-   * struct sendfile_op
-   * {
-   *   tcp::socket& sock_;
-   *   int fd_;
-   *   Handler handler_;
-   *   off_t offset_;
-   *   std::size_t total_bytes_transferred_;
-   *
-   *   // Function call operator meeting WriteHandler requirements.
-   *   // Used as the handler for the async_write_some operation.
-   *   void operator()(asio::error_code ec, std::size_t)
-   *   {
-   *     // Put the underlying socket into non-blocking mode.
-   *     if (!ec)
-   *       if (!sock_.native_non_blocking())
-   *         sock_.native_non_blocking(true, ec);
-   *
-   *     if (!ec)
-   *     {
-   *       for (;;)
-   *       {
-   *         // Try the system call.
-   *         errno = 0;
-   *         int n = ::sendfile(sock_.native_handle(), fd_, &offset_, 65536);
-   *         ec = asio::error_code(n < 0 ? errno : 0,
-   *             asio::error::get_system_category());
-   *         total_bytes_transferred_ += ec ? 0 : n;
-   *
-   *         // Retry operation immediately if interrupted by signal.
-   *         if (ec == asio::error::interrupted)
-   *           continue;
-   *
-   *         // Check if we need to run the operation again.
-   *         if (ec == asio::error::would_block
-   *             || ec == asio::error::try_again)
-   *         {
-   *           // We have to wait for the socket to become ready again.
-   *           sock_.async_wait(tcp::socket::wait_write, *this);
-   *           return;
-   *         }
-   *
-   *         if (ec || n == 0)
-   *         {
-   *           // An error occurred, or we have reached the end of the file.
-   *           // Either way we must exit the loop so we can call the handler.
-   *           break;
-   *         }
-   *
-   *         // Loop around to try calling sendfile again.
-   *       }
-   *     }
-   *
-   *     // Pass result back to user's handler.
-   *     handler_(ec, total_bytes_transferred_);
-   *   }
-   * };
-   *
-   * template <typename Handler>
-   * void async_sendfile(tcp::socket& sock, int fd, Handler h)
-   * {
-   *   sendfile_op<Handler> op = { sock, fd, h, 0, 0 };
-   *   sock.async_wait(tcp::socket::wait_write, op);
-   * } @endcode
-   */
-  bool native_non_blocking() const
-  {
-    return this->get_service().native_non_blocking(this->get_implementation());
-  }
-
-  /// Sets the non-blocking mode of the native socket implementation.
-  /**
-   * This function is used to modify the non-blocking mode of the underlying
-   * native socket. It has no effect on the behaviour of the socket object's
-   * synchronous operations.
-   *
-   * @param mode If @c true, the underlying socket is put into non-blocking
-   * mode and direct system calls may fail with asio::error::would_block
-   * (or the equivalent system error).
-   *
-   * @throws asio::system_error Thrown on failure. If the @c mode is
-   * @c false, but the current value of @c non_blocking() is @c true, this
-   * function fails with asio::error::invalid_argument, as the
-   * combination does not make sense.
-   *
-   * @par Example
-   * This function is intended to allow the encapsulation of arbitrary
-   * non-blocking system calls as asynchronous operations, in a way that is
-   * transparent to the user of the socket object. The following example
-   * illustrates how Linux's @c sendfile system call might be encapsulated:
-   * @code template <typename Handler>
-   * struct sendfile_op
-   * {
-   *   tcp::socket& sock_;
-   *   int fd_;
-   *   Handler handler_;
-   *   off_t offset_;
-   *   std::size_t total_bytes_transferred_;
-   *
-   *   // Function call operator meeting WriteHandler requirements.
-   *   // Used as the handler for the async_write_some operation.
-   *   void operator()(asio::error_code ec, std::size_t)
-   *   {
-   *     // Put the underlying socket into non-blocking mode.
-   *     if (!ec)
-   *       if (!sock_.native_non_blocking())
-   *         sock_.native_non_blocking(true, ec);
-   *
-   *     if (!ec)
-   *     {
-   *       for (;;)
-   *       {
-   *         // Try the system call.
-   *         errno = 0;
-   *         int n = ::sendfile(sock_.native_handle(), fd_, &offset_, 65536);
-   *         ec = asio::error_code(n < 0 ? errno : 0,
-   *             asio::error::get_system_category());
-   *         total_bytes_transferred_ += ec ? 0 : n;
-   *
-   *         // Retry operation immediately if interrupted by signal.
-   *         if (ec == asio::error::interrupted)
-   *           continue;
-   *
-   *         // Check if we need to run the operation again.
-   *         if (ec == asio::error::would_block
-   *             || ec == asio::error::try_again)
-   *         {
-   *           // We have to wait for the socket to become ready again.
-   *           sock_.async_wait(tcp::socket::wait_write, *this);
-   *           return;
-   *         }
-   *
-   *         if (ec || n == 0)
-   *         {
-   *           // An error occurred, or we have reached the end of the file.
-   *           // Either way we must exit the loop so we can call the handler.
-   *           break;
-   *         }
-   *
-   *         // Loop around to try calling sendfile again.
-   *       }
-   *     }
-   *
-   *     // Pass result back to user's handler.
-   *     handler_(ec, total_bytes_transferred_);
-   *   }
-   * };
-   *
-   * template <typename Handler>
-   * void async_sendfile(tcp::socket& sock, int fd, Handler h)
-   * {
-   *   sendfile_op<Handler> op = { sock, fd, h, 0, 0 };
-   *   sock.async_wait(tcp::socket::wait_write, op);
-   * } @endcode
-   */
-  void native_non_blocking(bool mode)
-  {
-    asio::error_code ec;
-    this->get_service().native_non_blocking(
-        this->get_implementation(), mode, ec);
-    asio::detail::throw_error(ec, "native_non_blocking");
-  }
-
-  /// Sets the non-blocking mode of the native socket implementation.
-  /**
-   * This function is used to modify the non-blocking mode of the underlying
-   * native socket. It has no effect on the behaviour of the socket object's
-   * synchronous operations.
-   *
-   * @param mode If @c true, the underlying socket is put into non-blocking
-   * mode and direct system calls may fail with asio::error::would_block
-   * (or the equivalent system error).
-   *
-   * @param ec Set to indicate what error occurred, if any. If the @c mode is
-   * @c false, but the current value of @c non_blocking() is @c true, this
-   * function fails with asio::error::invalid_argument, as the
-   * combination does not make sense.
-   *
-   * @par Example
-   * This function is intended to allow the encapsulation of arbitrary
-   * non-blocking system calls as asynchronous operations, in a way that is
-   * transparent to the user of the socket object. The following example
-   * illustrates how Linux's @c sendfile system call might be encapsulated:
-   * @code template <typename Handler>
-   * struct sendfile_op
-   * {
-   *   tcp::socket& sock_;
-   *   int fd_;
-   *   Handler handler_;
-   *   off_t offset_;
-   *   std::size_t total_bytes_transferred_;
-   *
-   *   // Function call operator meeting WriteHandler requirements.
-   *   // Used as the handler for the async_write_some operation.
-   *   void operator()(asio::error_code ec, std::size_t)
-   *   {
-   *     // Put the underlying socket into non-blocking mode.
-   *     if (!ec)
-   *       if (!sock_.native_non_blocking())
-   *         sock_.native_non_blocking(true, ec);
-   *
-   *     if (!ec)
-   *     {
-   *       for (;;)
-   *       {
-   *         // Try the system call.
-   *         errno = 0;
-   *         int n = ::sendfile(sock_.native_handle(), fd_, &offset_, 65536);
-   *         ec = asio::error_code(n < 0 ? errno : 0,
-   *             asio::error::get_system_category());
-   *         total_bytes_transferred_ += ec ? 0 : n;
-   *
-   *         // Retry operation immediately if interrupted by signal.
-   *         if (ec == asio::error::interrupted)
-   *           continue;
-   *
-   *         // Check if we need to run the operation again.
-   *         if (ec == asio::error::would_block
-   *             || ec == asio::error::try_again)
-   *         {
-   *           // We have to wait for the socket to become ready again.
-   *           sock_.async_wait(tcp::socket::wait_write, *this);
-   *           return;
-   *         }
-   *
-   *         if (ec || n == 0)
-   *         {
-   *           // An error occurred, or we have reached the end of the file.
-   *           // Either way we must exit the loop so we can call the handler.
-   *           break;
-   *         }
-   *
-   *         // Loop around to try calling sendfile again.
-   *       }
-   *     }
-   *
-   *     // Pass result back to user's handler.
-   *     handler_(ec, total_bytes_transferred_);
-   *   }
-   * };
-   *
-   * template <typename Handler>
-   * void async_sendfile(tcp::socket& sock, int fd, Handler h)
-   * {
-   *   sendfile_op<Handler> op = { sock, fd, h, 0, 0 };
-   *   sock.async_wait(tcp::socket::wait_write, op);
-   * } @endcode
-   */
-  ASIO_SYNC_OP_VOID native_non_blocking(
-      bool mode, asio::error_code& ec)
-  {
-    this->get_service().native_non_blocking(
-        this->get_implementation(), mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the local endpoint of the socket.
-  /**
-   * This function is used to obtain the locally bound endpoint of the socket.
-   *
-   * @returns An object that represents the local endpoint of the socket.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::ip::tcp::endpoint endpoint = socket.local_endpoint();
-   * @endcode
-   */
-  endpoint_type local_endpoint() const
-  {
-    asio::error_code ec;
-    endpoint_type ep = this->get_service().local_endpoint(
-        this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "local_endpoint");
-    return ep;
-  }
-
-  /// Get the local endpoint of the socket.
-  /**
-   * This function is used to obtain the locally bound endpoint of the socket.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns An object that represents the local endpoint of the socket.
-   * Returns a default-constructed endpoint object if an error occurred.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::error_code ec;
-   * asio::ip::tcp::endpoint endpoint = socket.local_endpoint(ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  endpoint_type local_endpoint(asio::error_code& ec) const
-  {
-    return this->get_service().local_endpoint(this->get_implementation(), ec);
-  }
-
-  /// Get the remote endpoint of the socket.
-  /**
-   * This function is used to obtain the remote endpoint of the socket.
-   *
-   * @returns An object that represents the remote endpoint of the socket.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::ip::tcp::endpoint endpoint = socket.remote_endpoint();
-   * @endcode
-   */
-  endpoint_type remote_endpoint() const
-  {
-    asio::error_code ec;
-    endpoint_type ep = this->get_service().remote_endpoint(
-        this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "remote_endpoint");
-    return ep;
-  }
-
-  /// Get the remote endpoint of the socket.
-  /**
-   * This function is used to obtain the remote endpoint of the socket.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns An object that represents the remote endpoint of the socket.
-   * Returns a default-constructed endpoint object if an error occurred.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::error_code ec;
-   * asio::ip::tcp::endpoint endpoint = socket.remote_endpoint(ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  endpoint_type remote_endpoint(asio::error_code& ec) const
-  {
-    return this->get_service().remote_endpoint(this->get_implementation(), ec);
-  }
-
-  /// Disable sends or receives on the socket.
-  /**
-   * This function is used to disable send operations, receive operations, or
-   * both.
-   *
-   * @param what Determines what types of operation will no longer be allowed.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * Shutting down the send side of the socket:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * socket.shutdown(asio::ip::tcp::socket::shutdown_send);
-   * @endcode
-   */
-  void shutdown(shutdown_type what)
-  {
-    asio::error_code ec;
-    this->get_service().shutdown(this->get_implementation(), what, ec);
-    asio::detail::throw_error(ec, "shutdown");
-  }
-
-  /// Disable sends or receives on the socket.
-  /**
-   * This function is used to disable send operations, receive operations, or
-   * both.
-   *
-   * @param what Determines what types of operation will no longer be allowed.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * Shutting down the send side of the socket:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::error_code ec;
-   * socket.shutdown(asio::ip::tcp::socket::shutdown_send, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID shutdown(shutdown_type what,
-      asio::error_code& ec)
-  {
-    this->get_service().shutdown(this->get_implementation(), what, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Wait for the socket to become ready to read, ready to write, or to have
-  /// pending error conditions.
-  /**
-   * This function is used to perform a blocking wait for a socket to enter
-   * a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired socket state.
-   *
-   * @par Example
-   * Waiting for a socket to become readable.
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * socket.wait(asio::ip::tcp::socket::wait_read);
-   * @endcode
-   */
-  void wait(wait_type w)
-  {
-    asio::error_code ec;
-    this->get_service().wait(this->get_implementation(), w, ec);
-    asio::detail::throw_error(ec, "wait");
-  }
-
-  /// Wait for the socket to become ready to read, ready to write, or to have
-  /// pending error conditions.
-  /**
-   * This function is used to perform a blocking wait for a socket to enter
-   * a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired socket state.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * Waiting for a socket to become readable.
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::error_code ec;
-   * socket.wait(asio::ip::tcp::socket::wait_read, ec);
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID wait(wait_type w, asio::error_code& ec)
-  {
-    this->get_service().wait(this->get_implementation(), w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the socket to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  /**
-   * This function is used to perform an asynchronous wait for a socket to enter
-   * a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired socket state.
-   *
-   * @param handler The handler to be called when the wait operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void wait_handler(const asio::error_code& error)
-   * {
-   *   if (!error)
-   *   {
-   *     // Wait succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * socket.async_wait(asio::ip::tcp::socket::wait_read, wait_handler);
-   * @endcode
-   */
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(wait_type w, ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WaitHandler.
-    ASIO_WAIT_HANDLER_CHECK(WaitHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_wait(this->get_implementation(),
-        w, ASIO_MOVE_CAST(WaitHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    this->get_service().async_wait(this->get_implementation(),
-        w, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  /**
-   * This function destroys the socket, cancelling any outstanding asynchronous
-   * operations associated with the socket as if by calling @c cancel.
-   */
-  ~basic_socket()
-  {
-  }
-
-private:
-  // Disallow copying and assignment.
-  basic_socket(const basic_socket&) ASIO_DELETED;
-  basic_socket& operator=(const basic_socket&) ASIO_DELETED;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-# undef ASIO_SVC_T
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_BASIC_SOCKET_HPP
diff --git a/tools/sdk/include/asio/asio/basic_socket_acceptor.hpp b/tools/sdk/include/asio/asio/basic_socket_acceptor.hpp
deleted file mode 100644
index ed201bbcaec..00000000000
--- a/tools/sdk/include/asio/asio/basic_socket_acceptor.hpp
+++ /dev/null
@@ -1,1986 +0,0 @@
-//
-// basic_socket_acceptor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_SOCKET_ACCEPTOR_HPP
-#define ASIO_BASIC_SOCKET_ACCEPTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/basic_io_object.hpp"
-#include "asio/basic_socket.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-#include "asio/socket_base.hpp"
-
-#if defined(ASIO_HAS_MOVE)
-# include <utility>
-#endif // defined(ASIO_HAS_MOVE)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/socket_acceptor_service.hpp"
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-# if defined(ASIO_WINDOWS_RUNTIME)
-#  include "asio/detail/null_socket_service.hpp"
-#  define ASIO_SVC_T detail::null_socket_service<Protocol>
-# elif defined(ASIO_HAS_IOCP)
-#  include "asio/detail/win_iocp_socket_service.hpp"
-#  define ASIO_SVC_T detail::win_iocp_socket_service<Protocol>
-# else
-#  include "asio/detail/reactive_socket_service.hpp"
-#  define ASIO_SVC_T detail::reactive_socket_service<Protocol>
-# endif
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides the ability to accept new connections.
-/**
- * The basic_socket_acceptor class template is used for accepting new socket
- * connections.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Example
- * Opening a socket acceptor with the SO_REUSEADDR option enabled:
- * @code
- * asio::ip::tcp::acceptor acceptor(io_context);
- * asio::ip::tcp::endpoint endpoint(asio::ip::tcp::v4(), port);
- * acceptor.open(endpoint.protocol());
- * acceptor.set_option(asio::ip::tcp::acceptor::reuse_address(true));
- * acceptor.bind(endpoint);
- * acceptor.listen();
- * @endcode
- */
-template <typename Protocol
-    ASIO_SVC_TPARAM_DEF1(= socket_acceptor_service<Protocol>)>
-class basic_socket_acceptor
-  : ASIO_SVC_ACCESS basic_io_object<ASIO_SVC_T>,
-    public socket_base
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// The native representation of an acceptor.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename ASIO_SVC_T::native_handle_type native_handle_type;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  /// Construct an acceptor without opening it.
-  /**
-   * This constructor creates an acceptor without opening it to listen for new
-   * connections. The open() function must be called before the acceptor can
-   * accept new socket connections.
-   *
-   * @param io_context The io_context object that the acceptor will use to
-   * dispatch handlers for any asynchronous operations performed on the
-   * acceptor.
-   */
-  explicit basic_socket_acceptor(asio::io_context& io_context)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-  }
-
-  /// Construct an open acceptor.
-  /**
-   * This constructor creates an acceptor and automatically opens it.
-   *
-   * @param io_context The io_context object that the acceptor will use to
-   * dispatch handlers for any asynchronous operations performed on the
-   * acceptor.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_socket_acceptor(asio::io_context& io_context,
-      const protocol_type& protocol)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), protocol, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Construct an acceptor opened on the given endpoint.
-  /**
-   * This constructor creates an acceptor and automatically opens it to listen
-   * for new connections on the specified endpoint.
-   *
-   * @param io_context The io_context object that the acceptor will use to
-   * dispatch handlers for any asynchronous operations performed on the
-   * acceptor.
-   *
-   * @param endpoint An endpoint on the local machine on which the acceptor
-   * will listen for new connections.
-   *
-   * @param reuse_addr Whether the constructor should set the socket option
-   * socket_base::reuse_address.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note This constructor is equivalent to the following code:
-   * @code
-   * basic_socket_acceptor<Protocol> acceptor(io_context);
-   * acceptor.open(endpoint.protocol());
-   * if (reuse_addr)
-   *   acceptor.set_option(socket_base::reuse_address(true));
-   * acceptor.bind(endpoint);
-   * acceptor.listen(listen_backlog);
-   * @endcode
-   */
-  basic_socket_acceptor(asio::io_context& io_context,
-      const endpoint_type& endpoint, bool reuse_addr = true)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    const protocol_type protocol = endpoint.protocol();
-    this->get_service().open(this->get_implementation(), protocol, ec);
-    asio::detail::throw_error(ec, "open");
-    if (reuse_addr)
-    {
-      this->get_service().set_option(this->get_implementation(),
-          socket_base::reuse_address(true), ec);
-      asio::detail::throw_error(ec, "set_option");
-    }
-    this->get_service().bind(this->get_implementation(), endpoint, ec);
-    asio::detail::throw_error(ec, "bind");
-    this->get_service().listen(this->get_implementation(),
-        socket_base::max_listen_connections, ec);
-    asio::detail::throw_error(ec, "listen");
-  }
-
-  /// Construct a basic_socket_acceptor on an existing native acceptor.
-  /**
-   * This constructor creates an acceptor object to hold an existing native
-   * acceptor.
-   *
-   * @param io_context The io_context object that the acceptor will use to
-   * dispatch handlers for any asynchronous operations performed on the
-   * acceptor.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @param native_acceptor A native acceptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_socket_acceptor(asio::io_context& io_context,
-      const protocol_type& protocol, const native_handle_type& native_acceptor)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        protocol, native_acceptor, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_socket_acceptor from another.
-  /**
-   * This constructor moves an acceptor from one object to another.
-   *
-   * @param other The other basic_socket_acceptor object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_socket_acceptor(io_context&) constructor.
-   */
-  basic_socket_acceptor(basic_socket_acceptor&& other)
-    : basic_io_object<ASIO_SVC_T>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_socket_acceptor from another.
-  /**
-   * This assignment operator moves an acceptor from one object to another.
-   *
-   * @param other The other basic_socket_acceptor object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_socket_acceptor(io_context&) constructor.
-   */
-  basic_socket_acceptor& operator=(basic_socket_acceptor&& other)
-  {
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(other));
-    return *this;
-  }
-
-  // All socket acceptors have access to each other's implementations.
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  friend class basic_socket_acceptor;
-
-  /// Move-construct a basic_socket_acceptor from an acceptor of another
-  /// protocol type.
-  /**
-   * This constructor moves an acceptor from one object to another.
-   *
-   * @param other The other basic_socket_acceptor object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  basic_socket_acceptor(
-      basic_socket_acceptor<Protocol1 ASIO_SVC_TARG1>&& other,
-      typename enable_if<is_convertible<Protocol1, Protocol>::value>::type* = 0)
-    : basic_io_object<ASIO_SVC_T>(
-        other.get_service(), other.get_implementation())
-  {
-  }
-
-  /// Move-assign a basic_socket_acceptor from an acceptor of another protocol
-  /// type.
-  /**
-   * This assignment operator moves an acceptor from one object to another.
-   *
-   * @param other The other basic_socket_acceptor object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  typename enable_if<is_convertible<Protocol1, Protocol>::value,
-      basic_socket_acceptor>::type& operator=(
-        basic_socket_acceptor<Protocol1 ASIO_SVC_TARG1>&& other)
-  {
-    basic_socket_acceptor tmp(std::move(other));
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(tmp));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroys the acceptor.
-  /**
-   * This function destroys the acceptor, cancelling any outstanding
-   * asynchronous operations associated with the acceptor as if by calling
-   * @c cancel.
-   */
-  ~basic_socket_acceptor()
-  {
-  }
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  // These functions are provided by basic_io_object<>.
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<ASIO_SVC_T>::get_executor();
-  }
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-  /// Open the acceptor using the specified protocol.
-  /**
-   * This function opens the socket acceptor so that it will use the specified
-   * protocol.
-   *
-   * @param protocol An object specifying which protocol is to be used.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * acceptor.open(asio::ip::tcp::v4());
-   * @endcode
-   */
-  void open(const protocol_type& protocol = protocol_type())
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), protocol, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Open the acceptor using the specified protocol.
-  /**
-   * This function opens the socket acceptor so that it will use the specified
-   * protocol.
-   *
-   * @param protocol An object specifying which protocol is to be used.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * asio::error_code ec;
-   * acceptor.open(asio::ip::tcp::v4(), ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID open(const protocol_type& protocol,
-      asio::error_code& ec)
-  {
-    this->get_service().open(this->get_implementation(), protocol, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assigns an existing native acceptor to the acceptor.
-  /*
-   * This function opens the acceptor to hold an existing native acceptor.
-   *
-   * @param protocol An object specifying which protocol is to be used.
-   *
-   * @param native_acceptor A native acceptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void assign(const protocol_type& protocol,
-      const native_handle_type& native_acceptor)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        protocol, native_acceptor, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-  /// Assigns an existing native acceptor to the acceptor.
-  /*
-   * This function opens the acceptor to hold an existing native acceptor.
-   *
-   * @param protocol An object specifying which protocol is to be used.
-   *
-   * @param native_acceptor A native acceptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID assign(const protocol_type& protocol,
-      const native_handle_type& native_acceptor, asio::error_code& ec)
-  {
-    this->get_service().assign(this->get_implementation(),
-        protocol, native_acceptor, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the acceptor is open.
-  bool is_open() const
-  {
-    return this->get_service().is_open(this->get_implementation());
-  }
-
-  /// Bind the acceptor to the given local endpoint.
-  /**
-   * This function binds the socket acceptor to the specified endpoint on the
-   * local machine.
-   *
-   * @param endpoint An endpoint on the local machine to which the socket
-   * acceptor will be bound.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * asio::ip::tcp::endpoint endpoint(asio::ip::tcp::v4(), 12345);
-   * acceptor.open(endpoint.protocol());
-   * acceptor.bind(endpoint);
-   * @endcode
-   */
-  void bind(const endpoint_type& endpoint)
-  {
-    asio::error_code ec;
-    this->get_service().bind(this->get_implementation(), endpoint, ec);
-    asio::detail::throw_error(ec, "bind");
-  }
-
-  /// Bind the acceptor to the given local endpoint.
-  /**
-   * This function binds the socket acceptor to the specified endpoint on the
-   * local machine.
-   *
-   * @param endpoint An endpoint on the local machine to which the socket
-   * acceptor will be bound.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * asio::ip::tcp::endpoint endpoint(asio::ip::tcp::v4(), 12345);
-   * acceptor.open(endpoint.protocol());
-   * asio::error_code ec;
-   * acceptor.bind(endpoint, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID bind(const endpoint_type& endpoint,
-      asio::error_code& ec)
-  {
-    this->get_service().bind(this->get_implementation(), endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Place the acceptor into the state where it will listen for new
-  /// connections.
-  /**
-   * This function puts the socket acceptor into the state where it may accept
-   * new connections.
-   *
-   * @param backlog The maximum length of the queue of pending connections.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void listen(int backlog = socket_base::max_listen_connections)
-  {
-    asio::error_code ec;
-    this->get_service().listen(this->get_implementation(), backlog, ec);
-    asio::detail::throw_error(ec, "listen");
-  }
-
-  /// Place the acceptor into the state where it will listen for new
-  /// connections.
-  /**
-   * This function puts the socket acceptor into the state where it may accept
-   * new connections.
-   *
-   * @param backlog The maximum length of the queue of pending connections.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::error_code ec;
-   * acceptor.listen(asio::socket_base::max_listen_connections, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID listen(int backlog, asio::error_code& ec)
-  {
-    this->get_service().listen(this->get_implementation(), backlog, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Close the acceptor.
-  /**
-   * This function is used to close the acceptor. Any asynchronous accept
-   * operations will be cancelled immediately.
-   *
-   * A subsequent call to open() is required before the acceptor can again be
-   * used to again perform socket accept operations.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void close()
-  {
-    asio::error_code ec;
-    this->get_service().close(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "close");
-  }
-
-  /// Close the acceptor.
-  /**
-   * This function is used to close the acceptor. Any asynchronous accept
-   * operations will be cancelled immediately.
-   *
-   * A subsequent call to open() is required before the acceptor can again be
-   * used to again perform socket accept operations.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::error_code ec;
-   * acceptor.close(ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    this->get_service().close(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Release ownership of the underlying native acceptor.
-  /**
-   * This function causes all outstanding asynchronous accept operations to
-   * finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error. Ownership of the
-   * native acceptor is then transferred to the caller.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note This function is unsupported on Windows versions prior to Windows
-   * 8.1, and will fail with asio::error::operation_not_supported on
-   * these platforms.
-   */
-#if defined(ASIO_MSVC) && (ASIO_MSVC >= 1400) \
-  && (!defined(_WIN32_WINNT) || _WIN32_WINNT < 0x0603)
-  __declspec(deprecated("This function always fails with "
-        "operation_not_supported when used on Windows versions "
-        "prior to Windows 8.1."))
-#endif
-  native_handle_type release()
-  {
-    asio::error_code ec;
-    native_handle_type s = this->get_service().release(
-        this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "release");
-    return s;
-  }
-
-  /// Release ownership of the underlying native acceptor.
-  /**
-   * This function causes all outstanding asynchronous accept operations to
-   * finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error. Ownership of the
-   * native acceptor is then transferred to the caller.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note This function is unsupported on Windows versions prior to Windows
-   * 8.1, and will fail with asio::error::operation_not_supported on
-   * these platforms.
-   */
-#if defined(ASIO_MSVC) && (ASIO_MSVC >= 1400) \
-  && (!defined(_WIN32_WINNT) || _WIN32_WINNT < 0x0603)
-  __declspec(deprecated("This function always fails with "
-        "operation_not_supported when used on Windows versions "
-        "prior to Windows 8.1."))
-#endif
-  native_handle_type release(asio::error_code& ec)
-  {
-    return this->get_service().release(this->get_implementation(), ec);
-  }
-
-  /// Get the native acceptor representation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * acceptor. This is intended to allow access to native acceptor functionality
-   * that is not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return this->get_service().native_handle(this->get_implementation());
-  }
-
-  /// Cancel all asynchronous operations associated with the acceptor.
-  /**
-   * This function causes all outstanding asynchronous connect, send and receive
-   * operations to finish immediately, and the handlers for cancelled operations
-   * will be passed the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all asynchronous operations associated with the acceptor.
-  /**
-   * This function causes all outstanding asynchronous connect, send and receive
-   * operations to finish immediately, and the handlers for cancelled operations
-   * will be passed the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Set an option on the acceptor.
-  /**
-   * This function is used to set an option on the acceptor.
-   *
-   * @param option The new option value to be set on the acceptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa SettableSocketOption @n
-   * asio::socket_base::reuse_address
-   * asio::socket_base::enable_connection_aborted
-   *
-   * @par Example
-   * Setting the SOL_SOCKET/SO_REUSEADDR option:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::acceptor::reuse_address option(true);
-   * acceptor.set_option(option);
-   * @endcode
-   */
-  template <typename SettableSocketOption>
-  void set_option(const SettableSocketOption& option)
-  {
-    asio::error_code ec;
-    this->get_service().set_option(this->get_implementation(), option, ec);
-    asio::detail::throw_error(ec, "set_option");
-  }
-
-  /// Set an option on the acceptor.
-  /**
-   * This function is used to set an option on the acceptor.
-   *
-   * @param option The new option value to be set on the acceptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa SettableSocketOption @n
-   * asio::socket_base::reuse_address
-   * asio::socket_base::enable_connection_aborted
-   *
-   * @par Example
-   * Setting the SOL_SOCKET/SO_REUSEADDR option:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::acceptor::reuse_address option(true);
-   * asio::error_code ec;
-   * acceptor.set_option(option, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  template <typename SettableSocketOption>
-  ASIO_SYNC_OP_VOID set_option(const SettableSocketOption& option,
-      asio::error_code& ec)
-  {
-    this->get_service().set_option(this->get_implementation(), option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get an option from the acceptor.
-  /**
-   * This function is used to get the current value of an option on the
-   * acceptor.
-   *
-   * @param option The option value to be obtained from the acceptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa GettableSocketOption @n
-   * asio::socket_base::reuse_address
-   *
-   * @par Example
-   * Getting the value of the SOL_SOCKET/SO_REUSEADDR option:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::acceptor::reuse_address option;
-   * acceptor.get_option(option);
-   * bool is_set = option.get();
-   * @endcode
-   */
-  template <typename GettableSocketOption>
-  void get_option(GettableSocketOption& option) const
-  {
-    asio::error_code ec;
-    this->get_service().get_option(this->get_implementation(), option, ec);
-    asio::detail::throw_error(ec, "get_option");
-  }
-
-  /// Get an option from the acceptor.
-  /**
-   * This function is used to get the current value of an option on the
-   * acceptor.
-   *
-   * @param option The option value to be obtained from the acceptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa GettableSocketOption @n
-   * asio::socket_base::reuse_address
-   *
-   * @par Example
-   * Getting the value of the SOL_SOCKET/SO_REUSEADDR option:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::acceptor::reuse_address option;
-   * asio::error_code ec;
-   * acceptor.get_option(option, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * bool is_set = option.get();
-   * @endcode
-   */
-  template <typename GettableSocketOption>
-  ASIO_SYNC_OP_VOID get_option(GettableSocketOption& option,
-      asio::error_code& ec) const
-  {
-    this->get_service().get_option(this->get_implementation(), option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the acceptor.
-  /**
-   * This function is used to execute an IO control command on the acceptor.
-   *
-   * @param command The IO control command to be performed on the acceptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa IoControlCommand @n
-   * asio::socket_base::non_blocking_io
-   *
-   * @par Example
-   * Getting the number of bytes ready to read:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::acceptor::non_blocking_io command(true);
-   * socket.io_control(command);
-   * @endcode
-   */
-  template <typename IoControlCommand>
-  void io_control(IoControlCommand& command)
-  {
-    asio::error_code ec;
-    this->get_service().io_control(this->get_implementation(), command, ec);
-    asio::detail::throw_error(ec, "io_control");
-  }
-
-  /// Perform an IO control command on the acceptor.
-  /**
-   * This function is used to execute an IO control command on the acceptor.
-   *
-   * @param command The IO control command to be performed on the acceptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa IoControlCommand @n
-   * asio::socket_base::non_blocking_io
-   *
-   * @par Example
-   * Getting the number of bytes ready to read:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::acceptor::non_blocking_io command(true);
-   * asio::error_code ec;
-   * socket.io_control(command, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(IoControlCommand& command,
-      asio::error_code& ec)
-  {
-    this->get_service().io_control(this->get_implementation(), command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the acceptor.
-  /**
-   * @returns @c true if the acceptor's synchronous operations will fail with
-   * asio::error::would_block if they are unable to perform the requested
-   * operation immediately. If @c false, synchronous operations will block
-   * until complete.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  bool non_blocking() const
-  {
-    return this->get_service().non_blocking(this->get_implementation());
-  }
-
-  /// Sets the non-blocking mode of the acceptor.
-  /**
-   * @param mode If @c true, the acceptor's synchronous operations will fail
-   * with asio::error::would_block if they are unable to perform the
-   * requested operation immediately. If @c false, synchronous operations will
-   * block until complete.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  void non_blocking(bool mode)
-  {
-    asio::error_code ec;
-    this->get_service().non_blocking(this->get_implementation(), mode, ec);
-    asio::detail::throw_error(ec, "non_blocking");
-  }
-
-  /// Sets the non-blocking mode of the acceptor.
-  /**
-   * @param mode If @c true, the acceptor's synchronous operations will fail
-   * with asio::error::would_block if they are unable to perform the
-   * requested operation immediately. If @c false, synchronous operations will
-   * block until complete.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  ASIO_SYNC_OP_VOID non_blocking(
-      bool mode, asio::error_code& ec)
-  {
-    this->get_service().non_blocking(this->get_implementation(), mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native acceptor implementation.
-  /**
-   * This function is used to retrieve the non-blocking mode of the underlying
-   * native acceptor. This mode has no effect on the behaviour of the acceptor
-   * object's synchronous operations.
-   *
-   * @returns @c true if the underlying acceptor is in non-blocking mode and
-   * direct system calls may fail with asio::error::would_block (or the
-   * equivalent system error).
-   *
-   * @note The current non-blocking mode is cached by the acceptor object.
-   * Consequently, the return value may be incorrect if the non-blocking mode
-   * was set directly on the native acceptor.
-   */
-  bool native_non_blocking() const
-  {
-    return this->get_service().native_non_blocking(this->get_implementation());
-  }
-
-  /// Sets the non-blocking mode of the native acceptor implementation.
-  /**
-   * This function is used to modify the non-blocking mode of the underlying
-   * native acceptor. It has no effect on the behaviour of the acceptor object's
-   * synchronous operations.
-   *
-   * @param mode If @c true, the underlying acceptor is put into non-blocking
-   * mode and direct system calls may fail with asio::error::would_block
-   * (or the equivalent system error).
-   *
-   * @throws asio::system_error Thrown on failure. If the @c mode is
-   * @c false, but the current value of @c non_blocking() is @c true, this
-   * function fails with asio::error::invalid_argument, as the
-   * combination does not make sense.
-   */
-  void native_non_blocking(bool mode)
-  {
-    asio::error_code ec;
-    this->get_service().native_non_blocking(
-        this->get_implementation(), mode, ec);
-    asio::detail::throw_error(ec, "native_non_blocking");
-  }
-
-  /// Sets the non-blocking mode of the native acceptor implementation.
-  /**
-   * This function is used to modify the non-blocking mode of the underlying
-   * native acceptor. It has no effect on the behaviour of the acceptor object's
-   * synchronous operations.
-   *
-   * @param mode If @c true, the underlying acceptor is put into non-blocking
-   * mode and direct system calls may fail with asio::error::would_block
-   * (or the equivalent system error).
-   *
-   * @param ec Set to indicate what error occurred, if any. If the @c mode is
-   * @c false, but the current value of @c non_blocking() is @c true, this
-   * function fails with asio::error::invalid_argument, as the
-   * combination does not make sense.
-   */
-  ASIO_SYNC_OP_VOID native_non_blocking(
-      bool mode, asio::error_code& ec)
-  {
-    this->get_service().native_non_blocking(
-        this->get_implementation(), mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the local endpoint of the acceptor.
-  /**
-   * This function is used to obtain the locally bound endpoint of the acceptor.
-   *
-   * @returns An object that represents the local endpoint of the acceptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::endpoint endpoint = acceptor.local_endpoint();
-   * @endcode
-   */
-  endpoint_type local_endpoint() const
-  {
-    asio::error_code ec;
-    endpoint_type ep = this->get_service().local_endpoint(
-        this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "local_endpoint");
-    return ep;
-  }
-
-  /// Get the local endpoint of the acceptor.
-  /**
-   * This function is used to obtain the locally bound endpoint of the acceptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns An object that represents the local endpoint of the acceptor.
-   * Returns a default-constructed endpoint object if an error occurred and the
-   * error handler did not throw an exception.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::error_code ec;
-   * asio::ip::tcp::endpoint endpoint = acceptor.local_endpoint(ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  endpoint_type local_endpoint(asio::error_code& ec) const
-  {
-    return this->get_service().local_endpoint(this->get_implementation(), ec);
-  }
-
-  /// Wait for the acceptor to become ready to read, ready to write, or to have
-  /// pending error conditions.
-  /**
-   * This function is used to perform a blocking wait for an acceptor to enter
-   * a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired acceptor state.
-   *
-   * @par Example
-   * Waiting for an acceptor to become readable.
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * acceptor.wait(asio::ip::tcp::acceptor::wait_read);
-   * @endcode
-   */
-  void wait(wait_type w)
-  {
-    asio::error_code ec;
-    this->get_service().wait(this->get_implementation(), w, ec);
-    asio::detail::throw_error(ec, "wait");
-  }
-
-  /// Wait for the acceptor to become ready to read, ready to write, or to have
-  /// pending error conditions.
-  /**
-   * This function is used to perform a blocking wait for an acceptor to enter
-   * a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired acceptor state.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * Waiting for an acceptor to become readable.
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::error_code ec;
-   * acceptor.wait(asio::ip::tcp::acceptor::wait_read, ec);
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID wait(wait_type w, asio::error_code& ec)
-  {
-    this->get_service().wait(this->get_implementation(), w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the acceptor to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  /**
-   * This function is used to perform an asynchronous wait for an acceptor to
-   * enter a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired acceptor state.
-   *
-   * @param handler The handler to be called when the wait operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void wait_handler(const asio::error_code& error)
-   * {
-   *   if (!error)
-   *   {
-   *     // Wait succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * acceptor.async_wait(
-   *     asio::ip::tcp::acceptor::wait_read,
-   *     wait_handler);
-   * @endcode
-   */
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(wait_type w, ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WaitHandler.
-    ASIO_WAIT_HANDLER_CHECK(WaitHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_wait(this->get_implementation(),
-        w, ASIO_MOVE_CAST(WaitHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    this->get_service().async_wait(this->get_implementation(),
-        w, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-#if !defined(ASIO_NO_EXTENSIONS)
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer into the
-   * given socket. The function call will block until a new connection has been
-   * accepted successfully or an error occurs.
-   *
-   * @param peer The socket into which the new connection will be accepted.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::socket socket(io_context);
-   * acceptor.accept(socket);
-   * @endcode
-   */
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename Protocol1, typename SocketService>
-  void accept(basic_socket<Protocol1, SocketService>& peer,
-      typename enable_if<is_convertible<Protocol, Protocol1>::value>::type* = 0)
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename Protocol1>
-  void accept(basic_socket<Protocol1>& peer,
-      typename enable_if<is_convertible<Protocol, Protocol1>::value>::type* = 0)
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  {
-    asio::error_code ec;
-    this->get_service().accept(this->get_implementation(),
-        peer, static_cast<endpoint_type*>(0), ec);
-    asio::detail::throw_error(ec, "accept");
-  }
-
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer into the
-   * given socket. The function call will block until a new connection has been
-   * accepted successfully or an error occurs.
-   *
-   * @param peer The socket into which the new connection will be accepted.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::socket socket(io_context);
-   * asio::error_code ec;
-   * acceptor.accept(socket, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename Protocol1, typename SocketService>
-  ASIO_SYNC_OP_VOID accept(
-      basic_socket<Protocol1, SocketService>& peer,
-      asio::error_code& ec,
-      typename enable_if<is_convertible<Protocol, Protocol1>::value>::type* = 0)
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename Protocol1>
-  ASIO_SYNC_OP_VOID accept(
-      basic_socket<Protocol1>& peer, asio::error_code& ec,
-      typename enable_if<is_convertible<Protocol, Protocol1>::value>::type* = 0)
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  {
-    this->get_service().accept(this->get_implementation(),
-        peer, static_cast<endpoint_type*>(0), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous accept.
-  /**
-   * This function is used to asynchronously accept a new connection into a
-   * socket. The function call always returns immediately.
-   *
-   * @param peer The socket into which the new connection will be accepted.
-   * Ownership of the peer object is retained by the caller, which must
-   * guarantee that it is valid until the handler is called.
-   *
-   * @param handler The handler to be called when the accept operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void accept_handler(const asio::error_code& error)
-   * {
-   *   if (!error)
-   *   {
-   *     // Accept succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::socket socket(io_context);
-   * acceptor.async_accept(socket, accept_handler);
-   * @endcode
-   */
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename Protocol1, typename SocketService, typename AcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(AcceptHandler,
-      void (asio::error_code))
-  async_accept(basic_socket<Protocol1, SocketService>& peer,
-      ASIO_MOVE_ARG(AcceptHandler) handler,
-      typename enable_if<is_convertible<Protocol, Protocol1>::value>::type* = 0)
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename Protocol1, typename AcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(AcceptHandler,
-      void (asio::error_code))
-  async_accept(basic_socket<Protocol1>& peer,
-      ASIO_MOVE_ARG(AcceptHandler) handler,
-      typename enable_if<is_convertible<Protocol, Protocol1>::value>::type* = 0)
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a AcceptHandler.
-    ASIO_ACCEPT_HANDLER_CHECK(AcceptHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_accept(this->get_implementation(),
-        peer, static_cast<endpoint_type*>(0),
-        ASIO_MOVE_CAST(AcceptHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<AcceptHandler,
-      void (asio::error_code)> init(handler);
-
-    this->get_service().async_accept(this->get_implementation(),
-        peer, static_cast<endpoint_type*>(0), init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Accept a new connection and obtain the endpoint of the peer
-  /**
-   * This function is used to accept a new connection from a peer into the
-   * given socket, and additionally provide the endpoint of the remote peer.
-   * The function call will block until a new connection has been accepted
-   * successfully or an error occurs.
-   *
-   * @param peer The socket into which the new connection will be accepted.
-   *
-   * @param peer_endpoint An endpoint object which will receive the endpoint of
-   * the remote peer.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::socket socket(io_context);
-   * asio::ip::tcp::endpoint endpoint;
-   * acceptor.accept(socket, endpoint);
-   * @endcode
-   */
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename SocketService>
-  void accept(basic_socket<protocol_type, SocketService>& peer,
-      endpoint_type& peer_endpoint)
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-  void accept(basic_socket<protocol_type>& peer, endpoint_type& peer_endpoint)
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  {
-    asio::error_code ec;
-    this->get_service().accept(this->get_implementation(),
-        peer, &peer_endpoint, ec);
-    asio::detail::throw_error(ec, "accept");
-  }
-
-  /// Accept a new connection and obtain the endpoint of the peer
-  /**
-   * This function is used to accept a new connection from a peer into the
-   * given socket, and additionally provide the endpoint of the remote peer.
-   * The function call will block until a new connection has been accepted
-   * successfully or an error occurs.
-   *
-   * @param peer The socket into which the new connection will be accepted.
-   *
-   * @param peer_endpoint An endpoint object which will receive the endpoint of
-   * the remote peer.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::socket socket(io_context);
-   * asio::ip::tcp::endpoint endpoint;
-   * asio::error_code ec;
-   * acceptor.accept(socket, endpoint, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename SocketService>
-  ASIO_SYNC_OP_VOID accept(
-      basic_socket<protocol_type, SocketService>& peer,
-      endpoint_type& peer_endpoint, asio::error_code& ec)
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-  ASIO_SYNC_OP_VOID accept(basic_socket<protocol_type>& peer,
-      endpoint_type& peer_endpoint, asio::error_code& ec)
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  {
-    this->get_service().accept(
-        this->get_implementation(), peer, &peer_endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous accept.
-  /**
-   * This function is used to asynchronously accept a new connection into a
-   * socket, and additionally obtain the endpoint of the remote peer. The
-   * function call always returns immediately.
-   *
-   * @param peer The socket into which the new connection will be accepted.
-   * Ownership of the peer object is retained by the caller, which must
-   * guarantee that it is valid until the handler is called.
-   *
-   * @param peer_endpoint An endpoint object into which the endpoint of the
-   * remote peer will be written. Ownership of the peer_endpoint object is
-   * retained by the caller, which must guarantee that it is valid until the
-   * handler is called.
-   *
-   * @param handler The handler to be called when the accept operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename SocketService, typename AcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(AcceptHandler,
-      void (asio::error_code))
-  async_accept(basic_socket<protocol_type, SocketService>& peer,
-      endpoint_type& peer_endpoint, ASIO_MOVE_ARG(AcceptHandler) handler)
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-  template <typename AcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(AcceptHandler,
-      void (asio::error_code))
-  async_accept(basic_socket<protocol_type>& peer,
-      endpoint_type& peer_endpoint, ASIO_MOVE_ARG(AcceptHandler) handler)
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a AcceptHandler.
-    ASIO_ACCEPT_HANDLER_CHECK(AcceptHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_accept(this->get_implementation(), peer,
-        &peer_endpoint, ASIO_MOVE_CAST(AcceptHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<AcceptHandler,
-      void (asio::error_code)> init(handler);
-
-    this->get_service().async_accept(this->get_implementation(),
-        peer, &peer_endpoint, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer. The function
-   * call will block until a new connection has been accepted successfully or
-   * an error occurs.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @returns A socket object representing the newly accepted connection.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::socket socket(acceptor.accept());
-   * @endcode
-   */
-  typename Protocol::socket accept()
-  {
-    asio::error_code ec;
-    typename Protocol::socket peer(
-        this->get_service().accept(
-          this->get_implementation(), 0, 0, ec));
-    asio::detail::throw_error(ec, "accept");
-    return peer;
-  }
-
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer. The function
-   * call will block until a new connection has been accepted successfully or
-   * an error occurs.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns On success, a socket object representing the newly accepted
-   * connection. On error, a socket object where is_open() is false.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::socket socket(acceptor.accept(ec));
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  typename Protocol::socket accept(asio::error_code& ec)
-  {
-    return this->get_service().accept(this->get_implementation(), 0, 0, ec);
-  }
-
-  /// Start an asynchronous accept.
-  /**
-   * This function is used to asynchronously accept a new connection. The
-   * function call always returns immediately.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param handler The handler to be called when the accept operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   typename Protocol::socket peer // On success, the newly accepted socket.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void accept_handler(const asio::error_code& error,
-   *     asio::ip::tcp::socket peer)
-   * {
-   *   if (!error)
-   *   {
-   *     // Accept succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * acceptor.async_accept(accept_handler);
-   * @endcode
-   */
-  template <typename MoveAcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(MoveAcceptHandler,
-      void (asio::error_code, typename Protocol::socket))
-  async_accept(ASIO_MOVE_ARG(MoveAcceptHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a MoveAcceptHandler.
-    ASIO_MOVE_ACCEPT_HANDLER_CHECK(MoveAcceptHandler,
-        handler, typename Protocol::socket) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_accept(
-        this->get_implementation(), static_cast<asio::io_context*>(0),
-        static_cast<endpoint_type*>(0),
-        ASIO_MOVE_CAST(MoveAcceptHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<MoveAcceptHandler,
-      void (asio::error_code,
-        typename Protocol::socket)> init(handler);
-
-    this->get_service().async_accept(
-        this->get_implementation(), static_cast<asio::io_context*>(0),
-        static_cast<endpoint_type*>(0), init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer. The function
-   * call will block until a new connection has been accepted successfully or
-   * an error occurs.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param io_context The io_context object to be used for the newly accepted
-   * socket.
-   *
-   * @returns A socket object representing the newly accepted connection.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::socket socket(acceptor.accept());
-   * @endcode
-   */
-  typename Protocol::socket accept(asio::io_context& io_context)
-  {
-    asio::error_code ec;
-    typename Protocol::socket peer(
-        this->get_service().accept(this->get_implementation(),
-          &io_context, static_cast<endpoint_type*>(0), ec));
-    asio::detail::throw_error(ec, "accept");
-    return peer;
-  }
-
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer. The function
-   * call will block until a new connection has been accepted successfully or
-   * an error occurs.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param io_context The io_context object to be used for the newly accepted
-   * socket.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns On success, a socket object representing the newly accepted
-   * connection. On error, a socket object where is_open() is false.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::socket socket(acceptor.accept(io_context2, ec));
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  typename Protocol::socket accept(
-      asio::io_context& io_context, asio::error_code& ec)
-  {
-    return this->get_service().accept(this->get_implementation(),
-        &io_context, static_cast<endpoint_type*>(0), ec);
-  }
-
-  /// Start an asynchronous accept.
-  /**
-   * This function is used to asynchronously accept a new connection. The
-   * function call always returns immediately.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param io_context The io_context object to be used for the newly accepted
-   * socket.
-   *
-   * @param handler The handler to be called when the accept operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   typename Protocol::socket peer // On success, the newly accepted socket.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void accept_handler(const asio::error_code& error,
-   *     asio::ip::tcp::socket peer)
-   * {
-   *   if (!error)
-   *   {
-   *     // Accept succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * acceptor.async_accept(io_context2, accept_handler);
-   * @endcode
-   */
-  template <typename MoveAcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(MoveAcceptHandler,
-      void (asio::error_code, typename Protocol::socket))
-  async_accept(asio::io_context& io_context,
-      ASIO_MOVE_ARG(MoveAcceptHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a MoveAcceptHandler.
-    ASIO_MOVE_ACCEPT_HANDLER_CHECK(MoveAcceptHandler,
-        handler, typename Protocol::socket) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_accept(this->get_implementation(),
-        &io_context, static_cast<endpoint_type*>(0),
-        ASIO_MOVE_CAST(MoveAcceptHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<MoveAcceptHandler,
-      void (asio::error_code,
-        typename Protocol::socket)> init(handler);
-
-    this->get_service().async_accept(this->get_implementation(),
-        &io_context, static_cast<endpoint_type*>(0), init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer. The function
-   * call will block until a new connection has been accepted successfully or
-   * an error occurs.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param peer_endpoint An endpoint object into which the endpoint of the
-   * remote peer will be written.
-   *
-   * @returns A socket object representing the newly accepted connection.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::endpoint endpoint;
-   * asio::ip::tcp::socket socket(acceptor.accept(endpoint));
-   * @endcode
-   */
-  typename Protocol::socket accept(endpoint_type& peer_endpoint)
-  {
-    asio::error_code ec;
-    typename Protocol::socket peer(
-        this->get_service().accept(this->get_implementation(),
-          static_cast<asio::io_context*>(0), &peer_endpoint, ec));
-    asio::detail::throw_error(ec, "accept");
-    return peer;
-  }
-
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer. The function
-   * call will block until a new connection has been accepted successfully or
-   * an error occurs.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param peer_endpoint An endpoint object into which the endpoint of the
-   * remote peer will be written.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns On success, a socket object representing the newly accepted
-   * connection. On error, a socket object where is_open() is false.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::endpoint endpoint;
-   * asio::ip::tcp::socket socket(acceptor.accept(endpoint, ec));
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  typename Protocol::socket accept(
-      endpoint_type& peer_endpoint, asio::error_code& ec)
-  {
-    return this->get_service().accept(this->get_implementation(),
-        static_cast<asio::io_context*>(0), &peer_endpoint, ec);
-  }
-
-  /// Start an asynchronous accept.
-  /**
-   * This function is used to asynchronously accept a new connection. The
-   * function call always returns immediately.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param peer_endpoint An endpoint object into which the endpoint of the
-   * remote peer will be written. Ownership of the peer_endpoint object is
-   * retained by the caller, which must guarantee that it is valid until the
-   * handler is called.
-   *
-   * @param handler The handler to be called when the accept operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   typename Protocol::socket peer // On success, the newly accepted socket.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void accept_handler(const asio::error_code& error,
-   *     asio::ip::tcp::socket peer)
-   * {
-   *   if (!error)
-   *   {
-   *     // Accept succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::endpoint endpoint;
-   * acceptor.async_accept(endpoint, accept_handler);
-   * @endcode
-   */
-  template <typename MoveAcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(MoveAcceptHandler,
-      void (asio::error_code, typename Protocol::socket))
-  async_accept(endpoint_type& peer_endpoint,
-      ASIO_MOVE_ARG(MoveAcceptHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a MoveAcceptHandler.
-    ASIO_MOVE_ACCEPT_HANDLER_CHECK(MoveAcceptHandler,
-        handler, typename Protocol::socket) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_accept(this->get_implementation(),
-        static_cast<asio::io_context*>(0), &peer_endpoint,
-        ASIO_MOVE_CAST(MoveAcceptHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<MoveAcceptHandler,
-      void (asio::error_code,
-        typename Protocol::socket)> init(handler);
-
-    this->get_service().async_accept(this->get_implementation(),
-        static_cast<asio::io_context*>(0), &peer_endpoint,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer. The function
-   * call will block until a new connection has been accepted successfully or
-   * an error occurs.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param io_context The io_context object to be used for the newly accepted
-   * socket.
-   *
-   * @param peer_endpoint An endpoint object into which the endpoint of the
-   * remote peer will be written.
-   *
-   * @returns A socket object representing the newly accepted connection.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::endpoint endpoint;
-   * asio::ip::tcp::socket socket(
-   *     acceptor.accept(io_context2, endpoint));
-   * @endcode
-   */
-  typename Protocol::socket accept(
-      asio::io_context& io_context, endpoint_type& peer_endpoint)
-  {
-    asio::error_code ec;
-    typename Protocol::socket peer(
-        this->get_service().accept(this->get_implementation(),
-          &io_context, &peer_endpoint, ec));
-    asio::detail::throw_error(ec, "accept");
-    return peer;
-  }
-
-  /// Accept a new connection.
-  /**
-   * This function is used to accept a new connection from a peer. The function
-   * call will block until a new connection has been accepted successfully or
-   * an error occurs.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param io_context The io_context object to be used for the newly accepted
-   * socket.
-   *
-   * @param peer_endpoint An endpoint object into which the endpoint of the
-   * remote peer will be written.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns On success, a socket object representing the newly accepted
-   * connection. On error, a socket object where is_open() is false.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::endpoint endpoint;
-   * asio::ip::tcp::socket socket(
-   *     acceptor.accept(io_context2, endpoint, ec));
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * @endcode
-   */
-  typename Protocol::socket accept(asio::io_context& io_context,
-      endpoint_type& peer_endpoint, asio::error_code& ec)
-  {
-    return this->get_service().accept(this->get_implementation(),
-        &io_context, &peer_endpoint, ec);
-  }
-
-  /// Start an asynchronous accept.
-  /**
-   * This function is used to asynchronously accept a new connection. The
-   * function call always returns immediately.
-   *
-   * This overload requires that the Protocol template parameter satisfy the
-   * AcceptableProtocol type requirements.
-   *
-   * @param io_context The io_context object to be used for the newly accepted
-   * socket.
-   *
-   * @param peer_endpoint An endpoint object into which the endpoint of the
-   * remote peer will be written. Ownership of the peer_endpoint object is
-   * retained by the caller, which must guarantee that it is valid until the
-   * handler is called.
-   *
-   * @param handler The handler to be called when the accept operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   typename Protocol::socket peer // On success, the newly accepted socket.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void accept_handler(const asio::error_code& error,
-   *     asio::ip::tcp::socket peer)
-   * {
-   *   if (!error)
-   *   {
-   *     // Accept succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::ip::tcp::acceptor acceptor(io_context);
-   * ...
-   * asio::ip::tcp::endpoint endpoint;
-   * acceptor.async_accept(io_context2, endpoint, accept_handler);
-   * @endcode
-   */
-  template <typename MoveAcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(MoveAcceptHandler,
-      void (asio::error_code, typename Protocol::socket))
-  async_accept(asio::io_context& io_context,
-      endpoint_type& peer_endpoint,
-      ASIO_MOVE_ARG(MoveAcceptHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a MoveAcceptHandler.
-    ASIO_MOVE_ACCEPT_HANDLER_CHECK(MoveAcceptHandler,
-        handler, typename Protocol::socket) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_accept(
-        this->get_implementation(), &io_context, &peer_endpoint,
-        ASIO_MOVE_CAST(MoveAcceptHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<MoveAcceptHandler,
-      void (asio::error_code,
-        typename Protocol::socket)> init(handler);
-
-    this->get_service().async_accept(this->get_implementation(),
-        &io_context, &peer_endpoint, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-# undef ASIO_SVC_T
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_BASIC_SOCKET_ACCEPTOR_HPP
diff --git a/tools/sdk/include/asio/asio/basic_socket_iostream.hpp b/tools/sdk/include/asio/asio/basic_socket_iostream.hpp
deleted file mode 100644
index 6681367fdfa..00000000000
--- a/tools/sdk/include/asio/asio/basic_socket_iostream.hpp
+++ /dev/null
@@ -1,430 +0,0 @@
-//
-// basic_socket_iostream.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_SOCKET_IOSTREAM_HPP
-#define ASIO_BASIC_SOCKET_IOSTREAM_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include <istream>
-#include <ostream>
-#include "asio/basic_socket_streambuf.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/stream_socket_service.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-# include "asio/detail/variadic_templates.hpp"
-
-// A macro that should expand to:
-//   template <typename T1, ..., typename Tn>
-//   explicit basic_socket_iostream(T1 x1, ..., Tn xn)
-//     : std::basic_iostream<char>(
-//         &this->detail::socket_iostream_base<
-//           Protocol ASIO_SVC_TARG, Clock,
-//           WaitTraits ASIO_SVC_TARG1>::streambuf_)
-//   {
-//     if (rdbuf()->connect(x1, ..., xn) == 0)
-//       this->setstate(std::ios_base::failbit);
-//   }
-// This macro should only persist within this file.
-
-# define ASIO_PRIVATE_CTR_DEF(n) \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  explicit basic_socket_iostream(ASIO_VARIADIC_BYVAL_PARAMS(n)) \
-    : std::basic_iostream<char>( \
-        &this->detail::socket_iostream_base< \
-          Protocol ASIO_SVC_TARG, Clock, \
-          WaitTraits ASIO_SVC_TARG1>::streambuf_) \
-  { \
-    this->setf(std::ios_base::unitbuf); \
-    if (rdbuf()->connect(ASIO_VARIADIC_BYVAL_ARGS(n)) == 0) \
-      this->setstate(std::ios_base::failbit); \
-  } \
-  /**/
-
-// A macro that should expand to:
-//   template <typename T1, ..., typename Tn>
-//   void connect(T1 x1, ..., Tn xn)
-//   {
-//     if (rdbuf()->connect(x1, ..., xn) == 0)
-//       this->setstate(std::ios_base::failbit);
-//   }
-// This macro should only persist within this file.
-
-# define ASIO_PRIVATE_CONNECT_DEF(n) \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  void connect(ASIO_VARIADIC_BYVAL_PARAMS(n)) \
-  { \
-    if (rdbuf()->connect(ASIO_VARIADIC_BYVAL_ARGS(n)) == 0) \
-      this->setstate(std::ios_base::failbit); \
-  } \
-  /**/
-
-#endif // !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// A separate base class is used to ensure that the streambuf is initialised
-// prior to the basic_socket_iostream's basic_iostream base class.
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Clock, typename WaitTraits ASIO_SVC_TPARAM1>
-class socket_iostream_base
-{
-protected:
-  socket_iostream_base()
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  socket_iostream_base(socket_iostream_base&& other)
-    : streambuf_(std::move(other.streambuf_))
-  {
-  }
-
-  socket_iostream_base(basic_stream_socket<Protocol> s)
-    : streambuf_(std::move(s))
-  {
-  }
-
-  socket_iostream_base& operator=(socket_iostream_base&& other)
-  {
-    streambuf_ = std::move(other.streambuf_);
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  basic_socket_streambuf<Protocol ASIO_SVC_TARG,
-    Clock, WaitTraits ASIO_SVC_TARG1> streambuf_;
-};
-
-} // namespace detail
-
-#if !defined(ASIO_BASIC_SOCKET_IOSTREAM_FWD_DECL)
-#define ASIO_BASIC_SOCKET_IOSTREAM_FWD_DECL
-
-// Forward declaration with defaulted arguments.
-template <typename Protocol
-    ASIO_SVC_TPARAM_DEF1(= stream_socket_service<Protocol>),
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-    typename Clock = boost::posix_time::ptime,
-    typename WaitTraits = time_traits<Clock>
-    ASIO_SVC_TPARAM1_DEF2(= deadline_timer_service<Clock, WaitTraits>)>
-#else // defined(ASIO_HAS_BOOST_DATE_TIME)
-      // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-    typename Clock = chrono::steady_clock,
-    typename WaitTraits = wait_traits<Clock>
-    ASIO_SVC_TPARAM1_DEF1(= steady_timer::service_type)>
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-class basic_socket_iostream;
-
-#endif // !defined(ASIO_BASIC_SOCKET_IOSTREAM_FWD_DECL)
-
-/// Iostream interface for a socket.
-#if defined(GENERATING_DOCUMENTATION)
-template <typename Protocol,
-    typename Clock = chrono::steady_clock,
-    typename WaitTraits = wait_traits<Clock> >
-#else // defined(GENERATING_DOCUMENTATION)
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Clock, typename WaitTraits ASIO_SVC_TPARAM1>
-#endif // defined(GENERATING_DOCUMENTATION)
-class basic_socket_iostream
-  : private detail::socket_iostream_base<Protocol
-        ASIO_SVC_TARG, Clock, WaitTraits ASIO_SVC_TARG1>,
-    public std::basic_iostream<char>
-{
-private:
-  // These typedefs are intended keep this class's implementation independent
-  // of whether it's using Boost.DateClock, Boost.Chrono or std::chrono.
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-  typedef WaitTraits traits_helper;
-#else // defined(ASIO_HAS_BOOST_DATE_TIME)
-      // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-  typedef detail::chrono_time_traits<Clock, WaitTraits> traits_helper;
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-
-public:
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  /// The clock type.
-  typedef Clock clock_type;
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// (Deprecated: Use time_point.) The time type.
-  typedef typename WaitTraits::time_type time_type;
-
-  /// The time type.
-  typedef typename WaitTraits::time_point time_point;
-
-  /// (Deprecated: Use duration.) The duration type.
-  typedef typename WaitTraits::duration_type duration_type;
-
-  /// The duration type.
-  typedef typename WaitTraits::duration duration;
-#else
-# if !defined(ASIO_NO_DEPRECATED)
-  typedef typename traits_helper::time_type time_type;
-  typedef typename traits_helper::duration_type duration_type;
-# endif // !defined(ASIO_NO_DEPRECATED)
-  typedef typename traits_helper::time_type time_point;
-  typedef typename traits_helper::duration_type duration;
-#endif
-
-  /// Construct a basic_socket_iostream without establishing a connection.
-  basic_socket_iostream()
-    : std::basic_iostream<char>(
-        &this->detail::socket_iostream_base<
-          Protocol ASIO_SVC_TARG, Clock,
-          WaitTraits ASIO_SVC_TARG1>::streambuf_)
-  {
-    this->setf(std::ios_base::unitbuf);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Construct a basic_socket_iostream from the supplied socket.
-  explicit basic_socket_iostream(basic_stream_socket<protocol_type> s)
-    : detail::socket_iostream_base<
-        Protocol ASIO_SVC_TARG, Clock,
-        WaitTraits ASIO_SVC_TARG1>(std::move(s)),
-      std::basic_iostream<char>(
-        &this->detail::socket_iostream_base<
-          Protocol ASIO_SVC_TARG, Clock,
-          WaitTraits ASIO_SVC_TARG1>::streambuf_)
-  {
-    this->setf(std::ios_base::unitbuf);
-  }
-
-#if defined(ASIO_HAS_STD_IOSTREAM_MOVE) \
-  || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_socket_iostream from another.
-  basic_socket_iostream(basic_socket_iostream&& other)
-    : detail::socket_iostream_base<
-        Protocol ASIO_SVC_TARG, Clock,
-        WaitTraits ASIO_SVC_TARG1>(std::move(other)),
-      std::basic_iostream<char>(std::move(other))
-  {
-    this->set_rdbuf(&this->detail::socket_iostream_base<
-          Protocol ASIO_SVC_TARG, Clock,
-          WaitTraits ASIO_SVC_TARG1>::streambuf_);
-  }
-
-  /// Move-assign a basic_socket_iostream from another.
-  basic_socket_iostream& operator=(basic_socket_iostream&& other)
-  {
-    std::basic_iostream<char>::operator=(std::move(other));
-    detail::socket_iostream_base<
-        Protocol ASIO_SVC_TARG, Clock,
-        WaitTraits ASIO_SVC_TARG1>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_STD_IOSTREAM_MOVE)
-       //   || defined(GENERATING_DOCUMENTATION)
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// Establish a connection to an endpoint corresponding to a resolver query.
-  /**
-   * This constructor automatically establishes a connection based on the
-   * supplied resolver query parameters. The arguments are used to construct
-   * a resolver query object.
-   */
-  template <typename T1, ..., typename TN>
-  explicit basic_socket_iostream(T1 t1, ..., TN tn);
-#elif defined(ASIO_HAS_VARIADIC_TEMPLATES)
-  template <typename... T>
-  explicit basic_socket_iostream(T... x)
-    : std::basic_iostream<char>(
-        &this->detail::socket_iostream_base<
-          Protocol ASIO_SVC_TARG, Clock,
-          WaitTraits ASIO_SVC_TARG1>::streambuf_)
-  {
-    this->setf(std::ios_base::unitbuf);
-    if (rdbuf()->connect(x...) == 0)
-      this->setstate(std::ios_base::failbit);
-  }
-#else
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_CTR_DEF)
-#endif
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// Establish a connection to an endpoint corresponding to a resolver query.
-  /**
-   * This function automatically establishes a connection based on the supplied
-   * resolver query parameters. The arguments are used to construct a resolver
-   * query object.
-   */
-  template <typename T1, ..., typename TN>
-  void connect(T1 t1, ..., TN tn);
-#elif defined(ASIO_HAS_VARIADIC_TEMPLATES)
-  template <typename... T>
-  void connect(T... x)
-  {
-    if (rdbuf()->connect(x...) == 0)
-      this->setstate(std::ios_base::failbit);
-  }
-#else
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_CONNECT_DEF)
-#endif
-
-  /// Close the connection.
-  void close()
-  {
-    if (rdbuf()->close() == 0)
-      this->setstate(std::ios_base::failbit);
-  }
-
-  /// Return a pointer to the underlying streambuf.
-  basic_socket_streambuf<Protocol ASIO_SVC_TARG,
-    Clock, WaitTraits ASIO_SVC_TARG1>* rdbuf() const
-  {
-    return const_cast<basic_socket_streambuf<Protocol ASIO_SVC_TARG,
-      Clock, WaitTraits ASIO_SVC_TARG1>*>(
-        &this->detail::socket_iostream_base<
-          Protocol ASIO_SVC_TARG, Clock,
-          WaitTraits ASIO_SVC_TARG1>::streambuf_);
-  }
-
-  /// Get a reference to the underlying socket.
-  basic_socket<Protocol ASIO_SVC_TARG>& socket()
-  {
-    return rdbuf()->socket();
-  }
-
-  /// Get the last error associated with the stream.
-  /**
-   * @return An \c error_code corresponding to the last error from the stream.
-   *
-   * @par Example
-   * To print the error associated with a failure to establish a connection:
-   * @code tcp::iostream s("www.boost.org", "http");
-   * if (!s)
-   * {
-   *   std::cout << "Error: " << s.error().message() << std::endl;
-   * } @endcode
-   */
-  const asio::error_code& error() const
-  {
-    return rdbuf()->error();
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use expiry().) Get the stream's expiry time as an absolute
-  /// time.
-  /**
-   * @return An absolute time value representing the stream's expiry time.
-   */
-  time_point expires_at() const
-  {
-    return rdbuf()->expires_at();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the stream's expiry time as an absolute time.
-  /**
-   * @return An absolute time value representing the stream's expiry time.
-   */
-  time_point expiry() const
-  {
-    return rdbuf()->expiry();
-  }
-
-  /// Set the stream's expiry time as an absolute time.
-  /**
-   * This function sets the expiry time associated with the stream. Stream
-   * operations performed after this time (where the operations cannot be
-   * completed using the internal buffers) will fail with the error
-   * asio::error::operation_aborted.
-   *
-   * @param expiry_time The expiry time to be used for the stream.
-   */
-  void expires_at(const time_point& expiry_time)
-  {
-    rdbuf()->expires_at(expiry_time);
-  }
-
-  /// Set the stream's expiry time relative to now.
-  /**
-   * This function sets the expiry time associated with the stream. Stream
-   * operations performed after this time (where the operations cannot be
-   * completed using the internal buffers) will fail with the error
-   * asio::error::operation_aborted.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   */
-  void expires_after(const duration& expiry_time)
-  {
-    rdbuf()->expires_after(expiry_time);
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use expiry().) Get the stream's expiry time relative to now.
-  /**
-   * @return A relative time value representing the stream's expiry time.
-   */
-  duration expires_from_now() const
-  {
-    return rdbuf()->expires_from_now();
-  }
-
-  /// (Deprecated: Use expires_after().) Set the stream's expiry time relative
-  /// to now.
-  /**
-   * This function sets the expiry time associated with the stream. Stream
-   * operations performed after this time (where the operations cannot be
-   * completed using the internal buffers) will fail with the error
-   * asio::error::operation_aborted.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   */
-  void expires_from_now(const duration& expiry_time)
-  {
-    rdbuf()->expires_from_now(expiry_time);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-private:
-  // Disallow copying and assignment.
-  basic_socket_iostream(const basic_socket_iostream&) ASIO_DELETED;
-  basic_socket_iostream& operator=(
-      const basic_socket_iostream&) ASIO_DELETED;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-# undef ASIO_PRIVATE_CTR_DEF
-# undef ASIO_PRIVATE_CONNECT_DEF
-#endif // !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_BASIC_SOCKET_IOSTREAM_HPP
diff --git a/tools/sdk/include/asio/asio/basic_socket_streambuf.hpp b/tools/sdk/include/asio/asio/basic_socket_streambuf.hpp
deleted file mode 100644
index 56a3637dccc..00000000000
--- a/tools/sdk/include/asio/asio/basic_socket_streambuf.hpp
+++ /dev/null
@@ -1,707 +0,0 @@
-//
-// basic_socket_streambuf.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_SOCKET_STREAMBUF_HPP
-#define ASIO_BASIC_SOCKET_STREAMBUF_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include <streambuf>
-#include <vector>
-#include "asio/basic_socket.hpp"
-#include "asio/basic_stream_socket.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/stream_socket_service.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-# if defined(ASIO_ENABLE_OLD_SERVICES)
-#  include "asio/deadline_timer_service.hpp"
-# else // defined(ASIO_ENABLE_OLD_SERVICES)
-#  include "asio/detail/deadline_timer_service.hpp"
-# endif // defined(ASIO_ENABLE_OLD_SERVICES)
-#else // defined(ASIO_HAS_BOOST_DATE_TIME)
-      // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-# include "asio/steady_timer.hpp"
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-
-#if !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-# include "asio/detail/variadic_templates.hpp"
-
-// A macro that should expand to:
-//   template <typename T1, ..., typename Tn>
-//   basic_socket_streambuf* connect(T1 x1, ..., Tn xn)
-//   {
-//     init_buffers();
-//     typedef typename Protocol::resolver resolver_type;
-//     resolver_type resolver(socket().get_executor().context());
-//     connect_to_endpoints(
-//         resolver.resolve(x1, ..., xn, ec_));
-//     return !ec_ ? this : 0;
-//   }
-// This macro should only persist within this file.
-
-# define ASIO_PRIVATE_CONNECT_DEF(n) \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  basic_socket_streambuf* connect(ASIO_VARIADIC_BYVAL_PARAMS(n)) \
-  { \
-    init_buffers(); \
-    typedef typename Protocol::resolver resolver_type; \
-    resolver_type resolver(socket().get_executor().context()); \
-    connect_to_endpoints( \
-        resolver.resolve(ASIO_VARIADIC_BYVAL_ARGS(n), ec_)); \
-    return !ec_ ? this : 0; \
-  } \
-  /**/
-
-#endif // !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-# define ASIO_SVC_T1 detail::deadline_timer_service<traits_helper>
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// A separate base class is used to ensure that the io_context member is
-// initialised prior to the basic_socket_streambuf's basic_socket base class.
-class socket_streambuf_io_context
-{
-protected:
-  socket_streambuf_io_context(io_context* ctx)
-    : default_io_context_(ctx)
-  {
-  }
-
-  shared_ptr<io_context> default_io_context_;
-};
-
-// A separate base class is used to ensure that the dynamically allocated
-// buffers are constructed prior to the basic_socket_streambuf's basic_socket
-// base class. This makes moving the socket is the last potentially throwing
-// step in the streambuf's move constructor, giving the constructor a strong
-// exception safety guarantee.
-class socket_streambuf_buffers
-{
-protected:
-  socket_streambuf_buffers()
-    : get_buffer_(buffer_size),
-      put_buffer_(buffer_size)
-  {
-  }
-
-  enum { buffer_size = 512 };
-  std::vector<char> get_buffer_;
-  std::vector<char> put_buffer_;
-};
-
-} // namespace detail
-
-#if !defined(ASIO_BASIC_SOCKET_STREAMBUF_FWD_DECL)
-#define ASIO_BASIC_SOCKET_STREAMBUF_FWD_DECL
-
-// Forward declaration with defaulted arguments.
-template <typename Protocol
-    ASIO_SVC_TPARAM_DEF1(= stream_socket_service<Protocol>),
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-    typename Clock = boost::posix_time::ptime,
-    typename WaitTraits = time_traits<Clock>
-    ASIO_SVC_TPARAM1_DEF2(= deadline_timer_service<Clock, WaitTraits>)>
-#else // defined(ASIO_HAS_BOOST_DATE_TIME)
-      // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-    typename Clock = chrono::steady_clock,
-    typename WaitTraits = wait_traits<Clock>
-    ASIO_SVC_TPARAM1_DEF1(= steady_timer::service_type)>
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-class basic_socket_streambuf;
-
-#endif // !defined(ASIO_BASIC_SOCKET_STREAMBUF_FWD_DECL)
-
-/// Iostream streambuf for a socket.
-#if defined(GENERATING_DOCUMENTATION)
-template <typename Protocol,
-    typename Clock = chrono::steady_clock,
-    typename WaitTraits = wait_traits<Clock> >
-#else // defined(GENERATING_DOCUMENTATION)
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Clock, typename WaitTraits ASIO_SVC_TPARAM1>
-#endif // defined(GENERATING_DOCUMENTATION)
-class basic_socket_streambuf
-  : public std::streambuf,
-    private detail::socket_streambuf_io_context,
-    private detail::socket_streambuf_buffers,
-#if defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-    private basic_socket<Protocol ASIO_SVC_TARG>
-#else // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-    public basic_socket<Protocol ASIO_SVC_TARG>
-#endif // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-{
-private:
-  // These typedefs are intended keep this class's implementation independent
-  // of whether it's using Boost.DateClock, Boost.Chrono or std::chrono.
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-  typedef WaitTraits traits_helper;
-#else // defined(ASIO_HAS_BOOST_DATE_TIME)
-      // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-  typedef detail::chrono_time_traits<Clock, WaitTraits> traits_helper;
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-
-public:
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  /// The clock type.
-  typedef Clock clock_type;
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// (Deprecated: Use time_point.) The time type.
-  typedef typename WaitTraits::time_type time_type;
-
-  /// The time type.
-  typedef typename WaitTraits::time_point time_point;
-
-  /// (Deprecated: Use duration.) The duration type.
-  typedef typename WaitTraits::duration_type duration_type;
-
-  /// The duration type.
-  typedef typename WaitTraits::duration duration;
-#else
-# if !defined(ASIO_NO_DEPRECATED)
-  typedef typename traits_helper::time_type time_type;
-  typedef typename traits_helper::duration_type duration_type;
-# endif // !defined(ASIO_NO_DEPRECATED)
-  typedef typename traits_helper::time_type time_point;
-  typedef typename traits_helper::duration_type duration;
-#endif
-
-  /// Construct a basic_socket_streambuf without establishing a connection.
-  basic_socket_streambuf()
-    : detail::socket_streambuf_io_context(new io_context),
-      basic_socket<Protocol ASIO_SVC_TARG>(*default_io_context_),
-      expiry_time_(max_expiry_time())
-  {
-    init_buffers();
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Construct a basic_socket_streambuf from the supplied socket.
-  explicit basic_socket_streambuf(basic_stream_socket<protocol_type> s)
-    : detail::socket_streambuf_io_context(0),
-      basic_socket<Protocol ASIO_SVC_TARG>(std::move(s)),
-      expiry_time_(max_expiry_time())
-  {
-    init_buffers();
-  }
-
-  /// Move-construct a basic_socket_streambuf from another.
-  basic_socket_streambuf(basic_socket_streambuf&& other)
-    : detail::socket_streambuf_io_context(other),
-      basic_socket<Protocol ASIO_SVC_TARG>(std::move(other.socket())),
-      ec_(other.ec_),
-      expiry_time_(other.expiry_time_)
-  {
-    get_buffer_.swap(other.get_buffer_);
-    put_buffer_.swap(other.put_buffer_);
-    setg(other.eback(), other.gptr(), other.egptr());
-    setp(other.pptr(), other.epptr());
-    other.ec_ = asio::error_code();
-    other.expiry_time_ = max_expiry_time();
-    other.init_buffers();
-  }
-
-  /// Move-assign a basic_socket_streambuf from another.
-  basic_socket_streambuf& operator=(basic_socket_streambuf&& other)
-  {
-    this->close();
-    socket() = std::move(other.socket());
-    detail::socket_streambuf_io_context::operator=(other);
-    ec_ = other.ec_;
-    expiry_time_ = other.expiry_time_;
-    get_buffer_.swap(other.get_buffer_);
-    put_buffer_.swap(other.put_buffer_);
-    setg(other.eback(), other.gptr(), other.egptr());
-    setp(other.pptr(), other.epptr());
-    other.ec_ = asio::error_code();
-    other.expiry_time_ = max_expiry_time();
-    other.put_buffer_.resize(buffer_size);
-    other.init_buffers();
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destructor flushes buffered data.
-  virtual ~basic_socket_streambuf()
-  {
-    if (pptr() != pbase())
-      overflow(traits_type::eof());
-  }
-
-  /// Establish a connection.
-  /**
-   * This function establishes a connection to the specified endpoint.
-   *
-   * @return \c this if a connection was successfully established, a null
-   * pointer otherwise.
-   */
-  basic_socket_streambuf* connect(const endpoint_type& endpoint)
-  {
-    init_buffers();
-    ec_ = asio::error_code();
-    this->connect_to_endpoints(&endpoint, &endpoint + 1);
-    return !ec_ ? this : 0;
-  }
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// Establish a connection.
-  /**
-   * This function automatically establishes a connection based on the supplied
-   * resolver query parameters. The arguments are used to construct a resolver
-   * query object.
-   *
-   * @return \c this if a connection was successfully established, a null
-   * pointer otherwise.
-   */
-  template <typename T1, ..., typename TN>
-  basic_socket_streambuf* connect(T1 t1, ..., TN tn);
-#elif defined(ASIO_HAS_VARIADIC_TEMPLATES)
-  template <typename... T>
-  basic_socket_streambuf* connect(T... x)
-  {
-    init_buffers();
-    typedef typename Protocol::resolver resolver_type;
-    resolver_type resolver(socket().get_executor().context());
-    connect_to_endpoints(resolver.resolve(x..., ec_));
-    return !ec_ ? this : 0;
-  }
-#else
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_CONNECT_DEF)
-#endif
-
-  /// Close the connection.
-  /**
-   * @return \c this if a connection was successfully established, a null
-   * pointer otherwise.
-   */
-  basic_socket_streambuf* close()
-  {
-    sync();
-    socket().close(ec_);
-    if (!ec_)
-      init_buffers();
-    return !ec_ ? this : 0;
-  }
-
-  /// Get a reference to the underlying socket.
-  basic_socket<Protocol ASIO_SVC_TARG>& socket()
-  {
-    return *this;
-  }
-
-  /// Get the last error associated with the stream buffer.
-  /**
-   * @return An \c error_code corresponding to the last error from the stream
-   * buffer.
-   */
-  const asio::error_code& error() const
-  {
-    return ec_;
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use error().) Get the last error associated with the stream
-  /// buffer.
-  /**
-   * @return An \c error_code corresponding to the last error from the stream
-   * buffer.
-   */
-  const asio::error_code& puberror() const
-  {
-    return error();
-  }
-
-  /// (Deprecated: Use expiry().) Get the stream buffer's expiry time as an
-  /// absolute time.
-  /**
-   * @return An absolute time value representing the stream buffer's expiry
-   * time.
-   */
-  time_point expires_at() const
-  {
-    return expiry_time_;
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the stream buffer's expiry time as an absolute time.
-  /**
-   * @return An absolute time value representing the stream buffer's expiry
-   * time.
-   */
-  time_point expiry() const
-  {
-    return expiry_time_;
-  }
-
-  /// Set the stream buffer's expiry time as an absolute time.
-  /**
-   * This function sets the expiry time associated with the stream. Stream
-   * operations performed after this time (where the operations cannot be
-   * completed using the internal buffers) will fail with the error
-   * asio::error::operation_aborted.
-   *
-   * @param expiry_time The expiry time to be used for the stream.
-   */
-  void expires_at(const time_point& expiry_time)
-  {
-    expiry_time_ = expiry_time;
-  }
-
-  /// Set the stream buffer's expiry time relative to now.
-  /**
-   * This function sets the expiry time associated with the stream. Stream
-   * operations performed after this time (where the operations cannot be
-   * completed using the internal buffers) will fail with the error
-   * asio::error::operation_aborted.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   */
-  void expires_after(const duration& expiry_time)
-  {
-    expiry_time_ = traits_helper::add(traits_helper::now(), expiry_time);
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use expiry().) Get the stream buffer's expiry time relative
-  /// to now.
-  /**
-   * @return A relative time value representing the stream buffer's expiry time.
-   */
-  duration expires_from_now() const
-  {
-    return traits_helper::subtract(expires_at(), traits_helper::now());
-  }
-
-  /// (Deprecated: Use expires_after().) Set the stream buffer's expiry time
-  /// relative to now.
-  /**
-   * This function sets the expiry time associated with the stream. Stream
-   * operations performed after this time (where the operations cannot be
-   * completed using the internal buffers) will fail with the error
-   * asio::error::operation_aborted.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   */
-  void expires_from_now(const duration& expiry_time)
-  {
-    expiry_time_ = traits_helper::add(traits_helper::now(), expiry_time);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-protected:
-  int_type underflow()
-  {
-#if defined(ASIO_WINDOWS_RUNTIME)
-    ec_ = asio::error::operation_not_supported;
-    return traits_type::eof();
-#else // defined(ASIO_WINDOWS_RUNTIME)
-    if (gptr() != egptr())
-      return traits_type::eof();
-
-    for (;;)
-    {
-      // Check if we are past the expiry time.
-      if (traits_helper::less_than(expiry_time_, traits_helper::now()))
-      {
-        ec_ = asio::error::timed_out;
-        return traits_type::eof();
-      }
-
-      // Try to complete the operation without blocking.
-      if (!socket().native_non_blocking())
-        socket().native_non_blocking(true, ec_);
-      detail::buffer_sequence_adapter<mutable_buffer, mutable_buffer>
-        bufs(asio::buffer(get_buffer_) + putback_max);
-      detail::signed_size_type bytes = detail::socket_ops::recv(
-          socket().native_handle(), bufs.buffers(), bufs.count(), 0, ec_);
-
-      // Check if operation succeeded.
-      if (bytes > 0)
-      {
-        setg(&get_buffer_[0], &get_buffer_[0] + putback_max,
-            &get_buffer_[0] + putback_max + bytes);
-        return traits_type::to_int_type(*gptr());
-      }
-
-      // Check for EOF.
-      if (bytes == 0)
-      {
-        ec_ = asio::error::eof;
-        return traits_type::eof();
-      }
-
-      // Operation failed.
-      if (ec_ != asio::error::would_block
-          && ec_ != asio::error::try_again)
-        return traits_type::eof();
-
-      // Wait for socket to become ready.
-      if (detail::socket_ops::poll_read(
-            socket().native_handle(), 0, timeout(), ec_) < 0)
-        return traits_type::eof();
-    }
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-  }
-
-  int_type overflow(int_type c)
-  {
-#if defined(ASIO_WINDOWS_RUNTIME)
-    ec_ = asio::error::operation_not_supported;
-    return traits_type::eof();
-#else // defined(ASIO_WINDOWS_RUNTIME)
-    char_type ch = traits_type::to_char_type(c);
-
-    // Determine what needs to be sent.
-    const_buffer output_buffer;
-    if (put_buffer_.empty())
-    {
-      if (traits_type::eq_int_type(c, traits_type::eof()))
-        return traits_type::not_eof(c); // Nothing to do.
-      output_buffer = asio::buffer(&ch, sizeof(char_type));
-    }
-    else
-    {
-      output_buffer = asio::buffer(pbase(),
-          (pptr() - pbase()) * sizeof(char_type));
-    }
-
-    while (output_buffer.size() > 0)
-    {
-      // Check if we are past the expiry time.
-      if (traits_helper::less_than(expiry_time_, traits_helper::now()))
-      {
-        ec_ = asio::error::timed_out;
-        return traits_type::eof();
-      }
-
-      // Try to complete the operation without blocking.
-      if (!socket().native_non_blocking())
-        socket().native_non_blocking(true, ec_);
-      detail::buffer_sequence_adapter<
-        const_buffer, const_buffer> bufs(output_buffer);
-      detail::signed_size_type bytes = detail::socket_ops::send(
-          socket().native_handle(), bufs.buffers(), bufs.count(), 0, ec_);
-
-      // Check if operation succeeded.
-      if (bytes > 0)
-      {
-        output_buffer += static_cast<std::size_t>(bytes);
-        continue;
-      }
-
-      // Operation failed.
-      if (ec_ != asio::error::would_block
-          && ec_ != asio::error::try_again)
-        return traits_type::eof();
-
-      // Wait for socket to become ready.
-      if (detail::socket_ops::poll_write(
-            socket().native_handle(), 0, timeout(), ec_) < 0)
-        return traits_type::eof();
-    }
-
-    if (!put_buffer_.empty())
-    {
-      setp(&put_buffer_[0], &put_buffer_[0] + put_buffer_.size());
-
-      // If the new character is eof then our work here is done.
-      if (traits_type::eq_int_type(c, traits_type::eof()))
-        return traits_type::not_eof(c);
-
-      // Add the new character to the output buffer.
-      *pptr() = ch;
-      pbump(1);
-    }
-
-    return c;
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-  }
-
-  int sync()
-  {
-    return overflow(traits_type::eof());
-  }
-
-  std::streambuf* setbuf(char_type* s, std::streamsize n)
-  {
-    if (pptr() == pbase() && s == 0 && n == 0)
-    {
-      put_buffer_.clear();
-      setp(0, 0);
-      sync();
-      return this;
-    }
-
-    return 0;
-  }
-
-private:
-  // Disallow copying and assignment.
-  basic_socket_streambuf(const basic_socket_streambuf&) ASIO_DELETED;
-  basic_socket_streambuf& operator=(
-      const basic_socket_streambuf&) ASIO_DELETED;
-
-  void init_buffers()
-  {
-    setg(&get_buffer_[0],
-        &get_buffer_[0] + putback_max,
-        &get_buffer_[0] + putback_max);
-
-    if (put_buffer_.empty())
-      setp(0, 0);
-    else
-      setp(&put_buffer_[0], &put_buffer_[0] + put_buffer_.size());
-  }
-
-  int timeout() const
-  {
-    int64_t msec = traits_helper::to_posix_duration(
-        traits_helper::subtract(expiry_time_,
-          traits_helper::now())).total_milliseconds();
-    if (msec > (std::numeric_limits<int>::max)())
-      msec = (std::numeric_limits<int>::max)();
-    else if (msec < 0)
-      msec = 0;
-    return static_cast<int>(msec);
-  }
-
-  template <typename EndpointSequence>
-  void connect_to_endpoints(const EndpointSequence& endpoints)
-  {
-    this->connect_to_endpoints(endpoints.begin(), endpoints.end());
-  }
-
-  template <typename EndpointIterator>
-  void connect_to_endpoints(EndpointIterator begin, EndpointIterator end)
-  {
-#if defined(ASIO_WINDOWS_RUNTIME)
-    ec_ = asio::error::operation_not_supported;
-#else // defined(ASIO_WINDOWS_RUNTIME)
-    if (ec_)
-      return;
-
-    ec_ = asio::error::not_found;
-    for (EndpointIterator i = begin; i != end; ++i)
-    {
-      // Check if we are past the expiry time.
-      if (traits_helper::less_than(expiry_time_, traits_helper::now()))
-      {
-        ec_ = asio::error::timed_out;
-        return;
-      }
-
-      // Close and reopen the socket.
-      typename Protocol::endpoint ep(*i);
-      socket().close(ec_);
-      socket().open(ep.protocol(), ec_);
-      if (ec_)
-        continue;
-
-      // Try to complete the operation without blocking.
-      if (!socket().native_non_blocking())
-        socket().native_non_blocking(true, ec_);
-      detail::socket_ops::connect(socket().native_handle(),
-          ep.data(), ep.size(), ec_);
-
-      // Check if operation succeeded.
-      if (!ec_)
-        return;
-
-      // Operation failed.
-      if (ec_ != asio::error::in_progress
-          && ec_ != asio::error::would_block)
-        continue;
-
-      // Wait for socket to become ready.
-      if (detail::socket_ops::poll_connect(
-            socket().native_handle(), timeout(), ec_) < 0)
-        continue;
-
-      // Get the error code from the connect operation.
-      int connect_error = 0;
-      size_t connect_error_len = sizeof(connect_error);
-      if (detail::socket_ops::getsockopt(socket().native_handle(), 0,
-            SOL_SOCKET, SO_ERROR, &connect_error, &connect_error_len, ec_)
-          == detail::socket_error_retval)
-        return;
-
-      // Check the result of the connect operation.
-      ec_ = asio::error_code(connect_error,
-          asio::error::get_system_category());
-      if (!ec_)
-        return;
-    }
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-  }
-
-  // Helper function to get the maximum expiry time.
-  static time_point max_expiry_time()
-  {
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-    return boost::posix_time::pos_infin;
-#else // defined(ASIO_HAS_BOOST_DATE_TIME)
-      // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-    return (time_point::max)();
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // && defined(ASIO_USE_BOOST_DATE_TIME_FOR_SOCKET_IOSTREAM)
-  }
-
-  enum { putback_max = 8 };
-  asio::error_code ec_;
-  time_point expiry_time_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-# undef ASIO_SVC_T1
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-# undef ASIO_PRIVATE_CONNECT_DEF
-#endif // !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_BASIC_SOCKET_STREAMBUF_HPP
diff --git a/tools/sdk/include/asio/asio/basic_stream_socket.hpp b/tools/sdk/include/asio/asio/basic_stream_socket.hpp
deleted file mode 100644
index eea88627462..00000000000
--- a/tools/sdk/include/asio/asio/basic_stream_socket.hpp
+++ /dev/null
@@ -1,921 +0,0 @@
-//
-// basic_stream_socket.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_STREAM_SOCKET_HPP
-#define ASIO_BASIC_STREAM_SOCKET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/basic_socket.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/stream_socket_service.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides stream-oriented socket functionality.
-/**
- * The basic_stream_socket class template provides asynchronous and blocking
- * stream-oriented socket functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * AsyncReadStream, AsyncWriteStream, Stream, SyncReadStream, SyncWriteStream.
- */
-template <typename Protocol
-    ASIO_SVC_TPARAM_DEF1(= stream_socket_service<Protocol>)>
-class basic_stream_socket
-  : public basic_socket<Protocol ASIO_SVC_TARG>
-{
-public:
-  /// The native representation of a socket.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename basic_socket<
-    Protocol ASIO_SVC_TARG>::native_handle_type native_handle_type;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  /// Construct a basic_stream_socket without opening it.
-  /**
-   * This constructor creates a stream socket without opening it. The socket
-   * needs to be opened and then connected or accepted before data can be sent
-   * or received on it.
-   *
-   * @param io_context The io_context object that the stream socket will use to
-   * dispatch handlers for any asynchronous operations performed on the socket.
-   */
-  explicit basic_stream_socket(asio::io_context& io_context)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context)
-  {
-  }
-
-  /// Construct and open a basic_stream_socket.
-  /**
-   * This constructor creates and opens a stream socket. The socket needs to be
-   * connected or accepted before data can be sent or received on it.
-   *
-   * @param io_context The io_context object that the stream socket will use to
-   * dispatch handlers for any asynchronous operations performed on the socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_stream_socket(asio::io_context& io_context,
-      const protocol_type& protocol)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context, protocol)
-  {
-  }
-
-  /// Construct a basic_stream_socket, opening it and binding it to the given
-  /// local endpoint.
-  /**
-   * This constructor creates a stream socket and automatically opens it bound
-   * to the specified endpoint on the local machine. The protocol used is the
-   * protocol associated with the given endpoint.
-   *
-   * @param io_context The io_context object that the stream socket will use to
-   * dispatch handlers for any asynchronous operations performed on the socket.
-   *
-   * @param endpoint An endpoint on the local machine to which the stream
-   * socket will be bound.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_stream_socket(asio::io_context& io_context,
-      const endpoint_type& endpoint)
-    : basic_socket<Protocol ASIO_SVC_TARG>(io_context, endpoint)
-  {
-  }
-
-  /// Construct a basic_stream_socket on an existing native socket.
-  /**
-   * This constructor creates a stream socket object to hold an existing native
-   * socket.
-   *
-   * @param io_context The io_context object that the stream socket will use to
-   * dispatch handlers for any asynchronous operations performed on the socket.
-   *
-   * @param protocol An object specifying protocol parameters to be used.
-   *
-   * @param native_socket The new underlying socket implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_stream_socket(asio::io_context& io_context,
-      const protocol_type& protocol, const native_handle_type& native_socket)
-    : basic_socket<Protocol ASIO_SVC_TARG>(
-        io_context, protocol, native_socket)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_stream_socket from another.
-  /**
-   * This constructor moves a stream socket from one object to another.
-   *
-   * @param other The other basic_stream_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_stream_socket(io_context&) constructor.
-   */
-  basic_stream_socket(basic_stream_socket&& other)
-    : basic_socket<Protocol ASIO_SVC_TARG>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_stream_socket from another.
-  /**
-   * This assignment operator moves a stream socket from one object to another.
-   *
-   * @param other The other basic_stream_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_stream_socket(io_context&) constructor.
-   */
-  basic_stream_socket& operator=(basic_stream_socket&& other)
-  {
-    basic_socket<Protocol ASIO_SVC_TARG>::operator=(std::move(other));
-    return *this;
-  }
-
-  /// Move-construct a basic_stream_socket from a socket of another protocol
-  /// type.
-  /**
-   * This constructor moves a stream socket from one object to another.
-   *
-   * @param other The other basic_stream_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_stream_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  basic_stream_socket(
-      basic_stream_socket<Protocol1 ASIO_SVC_TARG1>&& other,
-      typename enable_if<is_convertible<Protocol1, Protocol>::value>::type* = 0)
-    : basic_socket<Protocol ASIO_SVC_TARG>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_stream_socket from a socket of another protocol type.
-  /**
-   * This assignment operator moves a stream socket from one object to another.
-   *
-   * @param other The other basic_stream_socket object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_stream_socket(io_context&) constructor.
-   */
-  template <typename Protocol1 ASIO_SVC_TPARAM1>
-  typename enable_if<is_convertible<Protocol1, Protocol>::value,
-      basic_stream_socket>::type& operator=(
-        basic_stream_socket<Protocol1 ASIO_SVC_TARG1>&& other)
-  {
-    basic_socket<Protocol ASIO_SVC_TARG>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroys the socket.
-  /**
-   * This function destroys the socket, cancelling any outstanding asynchronous
-   * operations associated with the socket as if by calling @c cancel.
-   */
-  ~basic_stream_socket()
-  {
-  }
-
-  /// Send some data on the socket.
-  /**
-   * This function is used to send data on the stream socket. The function
-   * call will block until one or more bytes of the data has been sent
-   * successfully, or an until error occurs.
-   *
-   * @param buffers One or more data buffers to be sent on the socket.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The send operation may not transmit all of the data to the peer.
-   * Consider using the @ref write function if you need to ensure that all data
-   * is written before the blocking operation completes.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.send(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send(
-        this->get_implementation(), buffers, 0, ec);
-    asio::detail::throw_error(ec, "send");
-    return s;
-  }
-
-  /// Send some data on the socket.
-  /**
-   * This function is used to send data on the stream socket. The function
-   * call will block until one or more bytes of the data has been sent
-   * successfully, or an until error occurs.
-   *
-   * @param buffers One or more data buffers to be sent on the socket.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @returns The number of bytes sent.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The send operation may not transmit all of the data to the peer.
-   * Consider using the @ref write function if you need to ensure that all data
-   * is written before the blocking operation completes.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.send(asio::buffer(data, size), 0);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send(
-        this->get_implementation(), buffers, flags, ec);
-    asio::detail::throw_error(ec, "send");
-    return s;
-  }
-
-  /// Send some data on the socket.
-  /**
-   * This function is used to send data on the stream socket. The function
-   * call will block until one or more bytes of the data has been sent
-   * successfully, or an until error occurs.
-   *
-   * @param buffers One or more data buffers to be sent on the socket.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes sent. Returns 0 if an error occurred.
-   *
-   * @note The send operation may not transmit all of the data to the peer.
-   * Consider using the @ref write function if you need to ensure that all data
-   * is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return this->get_service().send(
-        this->get_implementation(), buffers, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  /**
-   * This function is used to asynchronously send data on the stream socket.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be sent on the socket. Although
-   * the buffers object may be copied as necessary, ownership of the underlying
-   * memory blocks is retained by the caller, which must guarantee that they
-   * remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The send operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write function if you need to ensure that all
-   * data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.async_send(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send(
-        this->get_implementation(), buffers, 0,
-        ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send(
-        this->get_implementation(), buffers, 0,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous send.
-  /**
-   * This function is used to asynchronously send data on the stream socket.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be sent on the socket. Although
-   * the buffers object may be copied as necessary, ownership of the underlying
-   * memory blocks is retained by the caller, which must guarantee that they
-   * remain valid until the handler is called.
-   *
-   * @param flags Flags specifying how the send call is to be made.
-   *
-   * @param handler The handler to be called when the send operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes sent.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The send operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write function if you need to ensure that all
-   * data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To send a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.async_send(asio::buffer(data, size), 0, handler);
-   * @endcode
-   * See the @ref buffer documentation for information on sending multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(const ConstBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send(
-        this->get_implementation(), buffers, flags,
-        ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send(
-        this->get_implementation(), buffers, flags,
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Receive some data on the socket.
-  /**
-   * This function is used to receive data on the stream socket. The function
-   * call will block until one or more bytes of data has been received
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The receive operation may not receive all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that the
-   * requested amount of data is read before the blocking operation completes.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.receive(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive(
-        this->get_implementation(), buffers, 0, ec);
-    asio::detail::throw_error(ec, "receive");
-    return s;
-  }
-
-  /// Receive some data on the socket.
-  /**
-   * This function is used to receive data on the stream socket. The function
-   * call will block until one or more bytes of data has been received
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @returns The number of bytes received.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The receive operation may not receive all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that the
-   * requested amount of data is read before the blocking operation completes.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.receive(asio::buffer(data, size), 0);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags flags)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive(
-        this->get_implementation(), buffers, flags, ec);
-    asio::detail::throw_error(ec, "receive");
-    return s;
-  }
-
-  /// Receive some data on a connected socket.
-  /**
-   * This function is used to receive data on the stream socket. The function
-   * call will block until one or more bytes of data has been received
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes received. Returns 0 if an error occurred.
-   *
-   * @note The receive operation may not receive all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that the
-   * requested amount of data is read before the blocking operation completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return this->get_service().receive(
-        this->get_implementation(), buffers, flags, ec);
-  }
-
-  /// Start an asynchronous receive.
-  /**
-   * This function is used to asynchronously receive data from the stream
-   * socket. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The receive operation may not receive all of the requested number of
-   * bytes. Consider using the @ref async_read function if you need to ensure
-   * that the requested amount of data is received before the asynchronous
-   * operation completes.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.async_receive(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive(this->get_implementation(),
-        buffers, 0, ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive(this->get_implementation(),
-        buffers, 0, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Start an asynchronous receive.
-  /**
-   * This function is used to asynchronously receive data from the stream
-   * socket. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be received.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param flags Flags specifying how the receive call is to be made.
-   *
-   * @param handler The handler to be called when the receive operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes received.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The receive operation may not receive all of the requested number of
-   * bytes. Consider using the @ref async_read function if you need to ensure
-   * that the requested amount of data is received before the asynchronous
-   * operation completes.
-   *
-   * @par Example
-   * To receive into a single data buffer use the @ref buffer function as
-   * follows:
-   * @code
-   * socket.async_receive(asio::buffer(data, size), 0, handler);
-   * @endcode
-   * See the @ref buffer documentation for information on receiving into
-   * multiple buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(const MutableBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive(this->get_implementation(),
-        buffers, flags, ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive(this->get_implementation(),
-        buffers, flags, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Write some data to the socket.
-  /**
-   * This function is used to write data to the stream socket. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the socket.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.write_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().send(
-        this->get_implementation(), buffers, 0, ec);
-    asio::detail::throw_error(ec, "write_some");
-    return s;
-  }
-
-  /// Write some data to the socket.
-  /**
-   * This function is used to write data to the stream socket. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the socket.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().send(this->get_implementation(), buffers, 0, ec);
-  }
-
-  /// Start an asynchronous write.
-  /**
-   * This function is used to asynchronously write data to the stream socket.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be written to the socket.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The write operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write function if you need to ensure that all
-   * data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.async_write_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_send(this->get_implementation(),
-        buffers, 0, ASIO_MOVE_CAST(WriteHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_send(this->get_implementation(),
-        buffers, 0, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Read some data from the socket.
-  /**
-   * This function is used to read data from the stream socket. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.read_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().receive(
-        this->get_implementation(), buffers, 0, ec);
-    asio::detail::throw_error(ec, "read_some");
-    return s;
-  }
-
-  /// Read some data from the socket.
-  /**
-   * This function is used to read data from the stream socket. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().receive(
-        this->get_implementation(), buffers, 0, ec);
-  }
-
-  /// Start an asynchronous read.
-  /**
-   * This function is used to asynchronously read data from the stream socket.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The read operation may not read all of the requested number of bytes.
-   * Consider using the @ref async_read function if you need to ensure that the
-   * requested amount of data is read before the asynchronous operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * socket.async_read_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_receive(this->get_implementation(),
-        buffers, 0, ASIO_MOVE_CAST(ReadHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_receive(this->get_implementation(),
-        buffers, 0, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_BASIC_STREAM_SOCKET_HPP
diff --git a/tools/sdk/include/asio/asio/basic_streambuf.hpp b/tools/sdk/include/asio/asio/basic_streambuf.hpp
deleted file mode 100644
index 14f85d22fcf..00000000000
--- a/tools/sdk/include/asio/asio/basic_streambuf.hpp
+++ /dev/null
@@ -1,452 +0,0 @@
-//
-// basic_streambuf.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_STREAMBUF_HPP
-#define ASIO_BASIC_STREAMBUF_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include <algorithm>
-#include <cstring>
-#include <stdexcept>
-#include <streambuf>
-#include <vector>
-#include "asio/basic_streambuf_fwd.hpp"
-#include "asio/buffer.hpp"
-#include "asio/detail/limits.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/throw_exception.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Automatically resizable buffer class based on std::streambuf.
-/**
- * The @c basic_streambuf class is derived from @c std::streambuf to associate
- * the streambuf's input and output sequences with one or more character
- * arrays. These character arrays are internal to the @c basic_streambuf
- * object, but direct access to the array elements is provided to permit them
- * to be used efficiently with I/O operations. Characters written to the output
- * sequence of a @c basic_streambuf object are appended to the input sequence
- * of the same object.
- *
- * The @c basic_streambuf class's public interface is intended to permit the
- * following implementation strategies:
- *
- * @li A single contiguous character array, which is reallocated as necessary
- * to accommodate changes in the size of the character sequence. This is the
- * implementation approach currently used in Asio.
- *
- * @li A sequence of one or more character arrays, where each array is of the
- * same size. Additional character array objects are appended to the sequence
- * to accommodate changes in the size of the character sequence.
- *
- * @li A sequence of one or more character arrays of varying sizes. Additional
- * character array objects are appended to the sequence to accommodate changes
- * in the size of the character sequence.
- *
- * The constructor for basic_streambuf accepts a @c size_t argument specifying
- * the maximum of the sum of the sizes of the input sequence and output
- * sequence. During the lifetime of the @c basic_streambuf object, the following
- * invariant holds:
- * @code size() <= max_size()@endcode
- * Any member function that would, if successful, cause the invariant to be
- * violated shall throw an exception of class @c std::length_error.
- *
- * The constructor for @c basic_streambuf takes an Allocator argument. A copy
- * of this argument is used for any memory allocation performed, by the
- * constructor and by all member functions, during the lifetime of each @c
- * basic_streambuf object.
- *
- * @par Examples
- * Writing directly from an streambuf to a socket:
- * @code
- * asio::streambuf b;
- * std::ostream os(&b);
- * os << "Hello, World!\n";
- *
- * // try sending some data in input sequence
- * size_t n = sock.send(b.data());
- *
- * b.consume(n); // sent data is removed from input sequence
- * @endcode
- *
- * Reading from a socket directly into a streambuf:
- * @code
- * asio::streambuf b;
- *
- * // reserve 512 bytes in output sequence
- * asio::streambuf::mutable_buffers_type bufs = b.prepare(512);
- *
- * size_t n = sock.receive(bufs);
- *
- * // received data is "committed" from output sequence to input sequence
- * b.commit(n);
- *
- * std::istream is(&b);
- * std::string s;
- * is >> s;
- * @endcode
- */
-#if defined(GENERATING_DOCUMENTATION)
-template <typename Allocator = std::allocator<char> >
-#else
-template <typename Allocator>
-#endif
-class basic_streambuf
-  : public std::streambuf,
-    private noncopyable
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The type used to represent the input sequence as a list of buffers.
-  typedef implementation_defined const_buffers_type;
-
-  /// The type used to represent the output sequence as a list of buffers.
-  typedef implementation_defined mutable_buffers_type;
-#else
-  typedef ASIO_CONST_BUFFER const_buffers_type;
-  typedef ASIO_MUTABLE_BUFFER mutable_buffers_type;
-#endif
-
-  /// Construct a basic_streambuf object.
-  /**
-   * Constructs a streambuf with the specified maximum size. The initial size
-   * of the streambuf's input sequence is 0.
-   */
-  explicit basic_streambuf(
-      std::size_t maximum_size = (std::numeric_limits<std::size_t>::max)(),
-      const Allocator& allocator = Allocator())
-    : max_size_(maximum_size),
-      buffer_(allocator)
-  {
-    std::size_t pend = (std::min<std::size_t>)(max_size_, buffer_delta);
-    buffer_.resize((std::max<std::size_t>)(pend, 1));
-    setg(&buffer_[0], &buffer_[0], &buffer_[0]);
-    setp(&buffer_[0], &buffer_[0] + pend);
-  }
-
-  /// Get the size of the input sequence.
-  /**
-   * @returns The size of the input sequence. The value is equal to that
-   * calculated for @c s in the following code:
-   * @code
-   * size_t s = 0;
-   * const_buffers_type bufs = data();
-   * const_buffers_type::const_iterator i = bufs.begin();
-   * while (i != bufs.end())
-   * {
-   *   const_buffer buf(*i++);
-   *   s += buf.size();
-   * }
-   * @endcode
-   */
-  std::size_t size() const ASIO_NOEXCEPT
-  {
-    return pptr() - gptr();
-  }
-
-  /// Get the maximum size of the basic_streambuf.
-  /**
-   * @returns The allowed maximum of the sum of the sizes of the input sequence
-   * and output sequence.
-   */
-  std::size_t max_size() const ASIO_NOEXCEPT
-  {
-    return max_size_;
-  }
-
-  /// Get the current capacity of the basic_streambuf.
-  /**
-   * @returns The current total capacity of the streambuf, i.e. for both the
-   * input sequence and output sequence.
-   */
-  std::size_t capacity() const ASIO_NOEXCEPT
-  {
-    return buffer_.capacity();
-  }
-
-  /// Get a list of buffers that represents the input sequence.
-  /**
-   * @returns An object of type @c const_buffers_type that satisfies
-   * ConstBufferSequence requirements, representing all character arrays in the
-   * input sequence.
-   *
-   * @note The returned object is invalidated by any @c basic_streambuf member
-   * function that modifies the input sequence or output sequence.
-   */
-  const_buffers_type data() const ASIO_NOEXCEPT
-  {
-    return asio::buffer(asio::const_buffer(gptr(),
-          (pptr() - gptr()) * sizeof(char_type)));
-  }
-
-  /// Get a list of buffers that represents the output sequence, with the given
-  /// size.
-  /**
-   * Ensures that the output sequence can accommodate @c n characters,
-   * reallocating character array objects as necessary.
-   *
-   * @returns An object of type @c mutable_buffers_type that satisfies
-   * MutableBufferSequence requirements, representing character array objects
-   * at the start of the output sequence such that the sum of the buffer sizes
-   * is @c n.
-   *
-   * @throws std::length_error If <tt>size() + n > max_size()</tt>.
-   *
-   * @note The returned object is invalidated by any @c basic_streambuf member
-   * function that modifies the input sequence or output sequence.
-   */
-  mutable_buffers_type prepare(std::size_t n)
-  {
-    reserve(n);
-    return asio::buffer(asio::mutable_buffer(
-          pptr(), n * sizeof(char_type)));
-  }
-
-  /// Move characters from the output sequence to the input sequence.
-  /**
-   * Appends @c n characters from the start of the output sequence to the input
-   * sequence. The beginning of the output sequence is advanced by @c n
-   * characters.
-   *
-   * Requires a preceding call <tt>prepare(x)</tt> where <tt>x >= n</tt>, and
-   * no intervening operations that modify the input or output sequence.
-   *
-   * @note If @c n is greater than the size of the output sequence, the entire
-   * output sequence is moved to the input sequence and no error is issued.
-   */
-  void commit(std::size_t n)
-  {
-    n = std::min<std::size_t>(n, epptr() - pptr());
-    pbump(static_cast<int>(n));
-    setg(eback(), gptr(), pptr());
-  }
-
-  /// Remove characters from the input sequence.
-  /**
-   * Removes @c n characters from the beginning of the input sequence.
-   *
-   * @note If @c n is greater than the size of the input sequence, the entire
-   * input sequence is consumed and no error is issued.
-   */
-  void consume(std::size_t n)
-  {
-    if (egptr() < pptr())
-      setg(&buffer_[0], gptr(), pptr());
-    if (gptr() + n > pptr())
-      n = pptr() - gptr();
-    gbump(static_cast<int>(n));
-  }
-
-protected:
-  enum { buffer_delta = 128 };
-
-  /// Override std::streambuf behaviour.
-  /**
-   * Behaves according to the specification of @c std::streambuf::underflow().
-   */
-  int_type underflow()
-  {
-    if (gptr() < pptr())
-    {
-      setg(&buffer_[0], gptr(), pptr());
-      return traits_type::to_int_type(*gptr());
-    }
-    else
-    {
-      return traits_type::eof();
-    }
-  }
-
-  /// Override std::streambuf behaviour.
-  /**
-   * Behaves according to the specification of @c std::streambuf::overflow(),
-   * with the specialisation that @c std::length_error is thrown if appending
-   * the character to the input sequence would require the condition
-   * <tt>size() > max_size()</tt> to be true.
-   */
-  int_type overflow(int_type c)
-  {
-    if (!traits_type::eq_int_type(c, traits_type::eof()))
-    {
-      if (pptr() == epptr())
-      {
-        std::size_t buffer_size = pptr() - gptr();
-        if (buffer_size < max_size_ && max_size_ - buffer_size < buffer_delta)
-        {
-          reserve(max_size_ - buffer_size);
-        }
-        else
-        {
-          reserve(buffer_delta);
-        }
-      }
-
-      *pptr() = traits_type::to_char_type(c);
-      pbump(1);
-      return c;
-    }
-
-    return traits_type::not_eof(c);
-  }
-
-  void reserve(std::size_t n)
-  {
-    // Get current stream positions as offsets.
-    std::size_t gnext = gptr() - &buffer_[0];
-    std::size_t pnext = pptr() - &buffer_[0];
-    std::size_t pend = epptr() - &buffer_[0];
-
-    // Check if there is already enough space in the put area.
-    if (n <= pend - pnext)
-    {
-      return;
-    }
-
-    // Shift existing contents of get area to start of buffer.
-    if (gnext > 0)
-    {
-      pnext -= gnext;
-      std::memmove(&buffer_[0], &buffer_[0] + gnext, pnext);
-    }
-
-    // Ensure buffer is large enough to hold at least the specified size.
-    if (n > pend - pnext)
-    {
-      if (n <= max_size_ && pnext <= max_size_ - n)
-      {
-        pend = pnext + n;
-        buffer_.resize((std::max<std::size_t>)(pend, 1));
-      }
-      else
-      {
-        std::length_error ex("asio::streambuf too long");
-        asio::detail::throw_exception(ex);
-      }
-    }
-
-    // Update stream positions.
-    setg(&buffer_[0], &buffer_[0], &buffer_[0] + pnext);
-    setp(&buffer_[0] + pnext, &buffer_[0] + pend);
-  }
-
-private:
-  std::size_t max_size_;
-  std::vector<char_type, Allocator> buffer_;
-
-  // Helper function to get the preferred size for reading data.
-  friend std::size_t read_size_helper(
-      basic_streambuf& sb, std::size_t max_size)
-  {
-    return std::min<std::size_t>(
-        std::max<std::size_t>(512, sb.buffer_.capacity() - sb.size()),
-        std::min<std::size_t>(max_size, sb.max_size() - sb.size()));
-  }
-};
-
-/// Adapts basic_streambuf to the dynamic buffer sequence type requirements.
-#if defined(GENERATING_DOCUMENTATION)
-template <typename Allocator = std::allocator<char> >
-#else
-template <typename Allocator>
-#endif
-class basic_streambuf_ref
-{
-public:
-  /// The type used to represent the input sequence as a list of buffers.
-  typedef typename basic_streambuf<Allocator>::const_buffers_type
-    const_buffers_type;
-
-  /// The type used to represent the output sequence as a list of buffers.
-  typedef typename basic_streambuf<Allocator>::mutable_buffers_type
-    mutable_buffers_type;
-
-  /// Construct a basic_streambuf_ref for the given basic_streambuf object.
-  explicit basic_streambuf_ref(basic_streambuf<Allocator>& sb)
-    : sb_(sb)
-  {
-  }
-
-  /// Copy construct a basic_streambuf_ref.
-  basic_streambuf_ref(const basic_streambuf_ref& other) ASIO_NOEXCEPT
-    : sb_(other.sb_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move construct a basic_streambuf_ref.
-  basic_streambuf_ref(basic_streambuf_ref&& other) ASIO_NOEXCEPT
-    : sb_(other.sb_)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Get the size of the input sequence.
-  std::size_t size() const ASIO_NOEXCEPT
-  {
-    return sb_.size();
-  }
-
-  /// Get the maximum size of the dynamic buffer.
-  std::size_t max_size() const ASIO_NOEXCEPT
-  {
-    return sb_.max_size();
-  }
-
-  /// Get the current capacity of the dynamic buffer.
-  std::size_t capacity() const ASIO_NOEXCEPT
-  {
-    return sb_.capacity();
-  }
-
-  /// Get a list of buffers that represents the input sequence.
-  const_buffers_type data() const ASIO_NOEXCEPT
-  {
-    return sb_.data();
-  }
-
-  /// Get a list of buffers that represents the output sequence, with the given
-  /// size.
-  mutable_buffers_type prepare(std::size_t n)
-  {
-    return sb_.prepare(n);
-  }
-
-  /// Move bytes from the output sequence to the input sequence.
-  void commit(std::size_t n)
-  {
-    return sb_.commit(n);
-  }
-
-  /// Remove characters from the input sequence.
-  void consume(std::size_t n)
-  {
-    return sb_.consume(n);
-  }
-
-private:
-  basic_streambuf<Allocator>& sb_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_BASIC_STREAMBUF_HPP
diff --git a/tools/sdk/include/asio/asio/basic_streambuf_fwd.hpp b/tools/sdk/include/asio/asio/basic_streambuf_fwd.hpp
deleted file mode 100644
index ed54fe95645..00000000000
--- a/tools/sdk/include/asio/asio/basic_streambuf_fwd.hpp
+++ /dev/null
@@ -1,36 +0,0 @@
-//
-// basic_streambuf_fwd.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_STREAMBUF_FWD_HPP
-#define ASIO_BASIC_STREAMBUF_FWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include <memory>
-
-namespace asio {
-
-template <typename Allocator = std::allocator<char> >
-class basic_streambuf;
-
-template <typename Allocator = std::allocator<char> >
-class basic_streambuf_ref;
-
-} // namespace asio
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_BASIC_STREAMBUF_FWD_HPP
diff --git a/tools/sdk/include/asio/asio/basic_waitable_timer.hpp b/tools/sdk/include/asio/asio/basic_waitable_timer.hpp
deleted file mode 100644
index 22b85a698ed..00000000000
--- a/tools/sdk/include/asio/asio/basic_waitable_timer.hpp
+++ /dev/null
@@ -1,705 +0,0 @@
-//
-// basic_waitable_timer.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BASIC_WAITABLE_TIMER_HPP
-#define ASIO_BASIC_WAITABLE_TIMER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/wait_traits.hpp"
-
-#if defined(ASIO_HAS_MOVE)
-# include <utility>
-#endif // defined(ASIO_HAS_MOVE)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/waitable_timer_service.hpp"
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/detail/chrono_time_traits.hpp"
-# include "asio/detail/deadline_timer_service.hpp"
-# define ASIO_SVC_T \
-    detail::deadline_timer_service< \
-      detail::chrono_time_traits<Clock, WaitTraits> >
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-#if !defined(ASIO_BASIC_WAITABLE_TIMER_FWD_DECL)
-#define ASIO_BASIC_WAITABLE_TIMER_FWD_DECL
-
-// Forward declaration with defaulted arguments.
-template <typename Clock,
-    typename WaitTraits = asio::wait_traits<Clock>
-    ASIO_SVC_TPARAM_DEF2(= waitable_timer_service<Clock, WaitTraits>)>
-class basic_waitable_timer;
-
-#endif // !defined(ASIO_BASIC_WAITABLE_TIMER_FWD_DECL)
-
-/// Provides waitable timer functionality.
-/**
- * The basic_waitable_timer class template provides the ability to perform a
- * blocking or asynchronous wait for a timer to expire.
- *
- * A waitable timer is always in one of two states: "expired" or "not expired".
- * If the wait() or async_wait() function is called on an expired timer, the
- * wait operation will complete immediately.
- *
- * Most applications will use one of the asio::steady_timer,
- * asio::system_timer or asio::high_resolution_timer typedefs.
- *
- * @note This waitable timer functionality is for use with the C++11 standard
- * library's @c &lt;chrono&gt; facility, or with the Boost.Chrono library.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Examples
- * Performing a blocking wait (C++11):
- * @code
- * // Construct a timer without setting an expiry time.
- * asio::steady_timer timer(io_context);
- *
- * // Set an expiry time relative to now.
- * timer.expires_after(std::chrono::seconds(5));
- *
- * // Wait for the timer to expire.
- * timer.wait();
- * @endcode
- *
- * @par 
- * Performing an asynchronous wait (C++11):
- * @code
- * void handler(const asio::error_code& error)
- * {
- *   if (!error)
- *   {
- *     // Timer expired.
- *   }
- * }
- *
- * ...
- *
- * // Construct a timer with an absolute expiry time.
- * asio::steady_timer timer(io_context,
- *     std::chrono::steady_clock::now() + std::chrono::seconds(60));
- *
- * // Start an asynchronous wait.
- * timer.async_wait(handler);
- * @endcode
- *
- * @par Changing an active waitable timer's expiry time
- *
- * Changing the expiry time of a timer while there are pending asynchronous
- * waits causes those wait operations to be cancelled. To ensure that the action
- * associated with the timer is performed only once, use something like this:
- * used:
- *
- * @code
- * void on_some_event()
- * {
- *   if (my_timer.expires_after(seconds(5)) > 0)
- *   {
- *     // We managed to cancel the timer. Start new asynchronous wait.
- *     my_timer.async_wait(on_timeout);
- *   }
- *   else
- *   {
- *     // Too late, timer has already expired!
- *   }
- * }
- *
- * void on_timeout(const asio::error_code& e)
- * {
- *   if (e != asio::error::operation_aborted)
- *   {
- *     // Timer was not cancelled, take necessary action.
- *   }
- * }
- * @endcode
- *
- * @li The asio::basic_waitable_timer::expires_after() function
- * cancels any pending asynchronous waits, and returns the number of
- * asynchronous waits that were cancelled. If it returns 0 then you were too
- * late and the wait handler has already been executed, or will soon be
- * executed. If it returns 1 then the wait handler was successfully cancelled.
- *
- * @li If a wait handler is cancelled, the asio::error_code passed to
- * it contains the value asio::error::operation_aborted.
- */
-template <typename Clock, typename WaitTraits ASIO_SVC_TPARAM>
-class basic_waitable_timer
-  : ASIO_SVC_ACCESS basic_io_object<ASIO_SVC_T>
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// The clock type.
-  typedef Clock clock_type;
-
-  /// The duration type of the clock.
-  typedef typename clock_type::duration duration;
-
-  /// The time point type of the clock.
-  typedef typename clock_type::time_point time_point;
-
-  /// The wait traits type.
-  typedef WaitTraits traits_type;
-
-  /// Constructor.
-  /**
-   * This constructor creates a timer without setting an expiry time. The
-   * expires_at() or expires_after() functions must be called to set an expiry
-   * time before the timer can be waited on.
-   *
-   * @param io_context The io_context object that the timer will use to dispatch
-   * handlers for any asynchronous operations performed on the timer.
-   */
-  explicit basic_waitable_timer(asio::io_context& io_context)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-  }
-
-  /// Constructor to set a particular expiry time as an absolute time.
-  /**
-   * This constructor creates a timer and sets the expiry time.
-   *
-   * @param io_context The io_context object that the timer will use to dispatch
-   * handlers for any asynchronous operations performed on the timer.
-   *
-   * @param expiry_time The expiry time to be used for the timer, expressed
-   * as an absolute time.
-   */
-  basic_waitable_timer(asio::io_context& io_context,
-      const time_point& expiry_time)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().expires_at(this->get_implementation(), expiry_time, ec);
-    asio::detail::throw_error(ec, "expires_at");
-  }
-
-  /// Constructor to set a particular expiry time relative to now.
-  /**
-   * This constructor creates a timer and sets the expiry time.
-   *
-   * @param io_context The io_context object that the timer will use to dispatch
-   * handlers for any asynchronous operations performed on the timer.
-   *
-   * @param expiry_time The expiry time to be used for the timer, relative to
-   * now.
-   */
-  basic_waitable_timer(asio::io_context& io_context,
-      const duration& expiry_time)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().expires_after(
-        this->get_implementation(), expiry_time, ec);
-    asio::detail::throw_error(ec, "expires_after");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_waitable_timer from another.
-  /**
-   * This constructor moves a timer from one object to another.
-   *
-   * @param other The other basic_waitable_timer object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_waitable_timer(io_context&) constructor.
-   */
-  basic_waitable_timer(basic_waitable_timer&& other)
-    : basic_io_object<ASIO_SVC_T>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_waitable_timer from another.
-  /**
-   * This assignment operator moves a timer from one object to another. Cancels
-   * any outstanding asynchronous operations associated with the target object.
-   *
-   * @param other The other basic_waitable_timer object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_waitable_timer(io_context&) constructor.
-   */
-  basic_waitable_timer& operator=(basic_waitable_timer&& other)
-  {
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroys the timer.
-  /**
-   * This function destroys the timer, cancelling any outstanding asynchronous
-   * wait operations associated with the timer as if by calling @c cancel.
-   */
-  ~basic_waitable_timer()
-  {
-  }
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  // These functions are provided by basic_io_object<>.
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<ASIO_SVC_T>::get_executor();
-  }
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-  /// Cancel any asynchronous operations that are waiting on the timer.
-  /**
-   * This function forces the completion of any pending asynchronous wait
-   * operations against the timer. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * Cancelling the timer does not change the expiry time.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If the timer has already expired when cancel() is called, then the
-   * handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t cancel()
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-    return s;
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use non-error_code overload.) Cancel any asynchronous
-  /// operations that are waiting on the timer.
-  /**
-   * This function forces the completion of any pending asynchronous wait
-   * operations against the timer. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * Cancelling the timer does not change the expiry time.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @note If the timer has already expired when cancel() is called, then the
-   * handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t cancel(asio::error_code& ec)
-  {
-    return this->get_service().cancel(this->get_implementation(), ec);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Cancels one asynchronous operation that is waiting on the timer.
-  /**
-   * This function forces the completion of one pending asynchronous wait
-   * operation against the timer. Handlers are cancelled in FIFO order. The
-   * handler for the cancelled operation will be invoked with the
-   * asio::error::operation_aborted error code.
-   *
-   * Cancelling the timer does not change the expiry time.
-   *
-   * @return The number of asynchronous operations that were cancelled. That is,
-   * either 0 or 1.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If the timer has already expired when cancel_one() is called, then
-   * the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t cancel_one()
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().cancel_one(
-        this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel_one");
-    return s;
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use non-error_code overload.) Cancels one asynchronous
-  /// operation that is waiting on the timer.
-  /**
-   * This function forces the completion of one pending asynchronous wait
-   * operation against the timer. Handlers are cancelled in FIFO order. The
-   * handler for the cancelled operation will be invoked with the
-   * asio::error::operation_aborted error code.
-   *
-   * Cancelling the timer does not change the expiry time.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of asynchronous operations that were cancelled. That is,
-   * either 0 or 1.
-   *
-   * @note If the timer has already expired when cancel_one() is called, then
-   * the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t cancel_one(asio::error_code& ec)
-  {
-    return this->get_service().cancel_one(this->get_implementation(), ec);
-  }
-
-  /// (Deprecated: Use expiry().) Get the timer's expiry time as an absolute
-  /// time.
-  /**
-   * This function may be used to obtain the timer's current expiry time.
-   * Whether the timer has expired or not does not affect this value.
-   */
-  time_point expires_at() const
-  {
-    return this->get_service().expires_at(this->get_implementation());
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the timer's expiry time as an absolute time.
-  /**
-   * This function may be used to obtain the timer's current expiry time.
-   * Whether the timer has expired or not does not affect this value.
-   */
-  time_point expiry() const
-  {
-    return this->get_service().expiry(this->get_implementation());
-  }
-
-  /// Set the timer's expiry time as an absolute time.
-  /**
-   * This function sets the expiry time. Any pending asynchronous wait
-   * operations will be cancelled. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If the timer has already expired when expires_at() is called, then
-   * the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t expires_at(const time_point& expiry_time)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().expires_at(
-        this->get_implementation(), expiry_time, ec);
-    asio::detail::throw_error(ec, "expires_at");
-    return s;
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use non-error_code overload.) Set the timer's expiry time as
-  /// an absolute time.
-  /**
-   * This function sets the expiry time. Any pending asynchronous wait
-   * operations will be cancelled. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @note If the timer has already expired when expires_at() is called, then
-   * the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t expires_at(const time_point& expiry_time,
-      asio::error_code& ec)
-  {
-    return this->get_service().expires_at(
-        this->get_implementation(), expiry_time, ec);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Set the timer's expiry time relative to now.
-  /**
-   * This function sets the expiry time. Any pending asynchronous wait
-   * operations will be cancelled. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If the timer has already expired when expires_after() is called,
-   * then the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t expires_after(const duration& expiry_time)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().expires_after(
-        this->get_implementation(), expiry_time, ec);
-    asio::detail::throw_error(ec, "expires_after");
-    return s;
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use expiry().) Get the timer's expiry time relative to now.
-  /**
-   * This function may be used to obtain the timer's current expiry time.
-   * Whether the timer has expired or not does not affect this value.
-   */
-  duration expires_from_now() const
-  {
-    return this->get_service().expires_from_now(this->get_implementation());
-  }
-
-  /// (Deprecated: Use expires_after().) Set the timer's expiry time relative
-  /// to now.
-  /**
-   * This function sets the expiry time. Any pending asynchronous wait
-   * operations will be cancelled. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If the timer has already expired when expires_from_now() is called,
-   * then the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t expires_from_now(const duration& expiry_time)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().expires_from_now(
-        this->get_implementation(), expiry_time, ec);
-    asio::detail::throw_error(ec, "expires_from_now");
-    return s;
-  }
-
-  /// (Deprecated: Use expires_after().) Set the timer's expiry time relative
-  /// to now.
-  /**
-   * This function sets the expiry time. Any pending asynchronous wait
-   * operations will be cancelled. The handler for each cancelled operation will
-   * be invoked with the asio::error::operation_aborted error code.
-   *
-   * @param expiry_time The expiry time to be used for the timer.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of asynchronous operations that were cancelled.
-   *
-   * @note If the timer has already expired when expires_from_now() is called,
-   * then the handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  std::size_t expires_from_now(const duration& expiry_time,
-      asio::error_code& ec)
-  {
-    return this->get_service().expires_from_now(
-        this->get_implementation(), expiry_time, ec);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Perform a blocking wait on the timer.
-  /**
-   * This function is used to wait for the timer to expire. This function
-   * blocks and does not return until the timer has expired.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void wait()
-  {
-    asio::error_code ec;
-    this->get_service().wait(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "wait");
-  }
-
-  /// Perform a blocking wait on the timer.
-  /**
-   * This function is used to wait for the timer to expire. This function
-   * blocks and does not return until the timer has expired.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  void wait(asio::error_code& ec)
-  {
-    this->get_service().wait(this->get_implementation(), ec);
-  }
-
-  /// Start an asynchronous wait on the timer.
-  /**
-   * This function may be used to initiate an asynchronous wait against the
-   * timer. It always returns immediately.
-   *
-   * For each call to async_wait(), the supplied handler will be called exactly
-   * once. The handler will be called when:
-   *
-   * @li The timer has expired.
-   *
-   * @li The timer was cancelled, in which case the handler is passed the error
-   * code asio::error::operation_aborted.
-   *
-   * @param handler The handler to be called when the timer expires. Copies
-   * will be made of the handler as required. The function signature of the
-   * handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WaitHandler.
-    ASIO_WAIT_HANDLER_CHECK(WaitHandler, handler) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_wait(this->get_implementation(),
-        ASIO_MOVE_CAST(WaitHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    this->get_service().async_wait(this->get_implementation(),
-        init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-private:
-  // Disallow copying and assignment.
-  basic_waitable_timer(const basic_waitable_timer&) ASIO_DELETED;
-  basic_waitable_timer& operator=(
-      const basic_waitable_timer&) ASIO_DELETED;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-# undef ASIO_SVC_T
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_BASIC_WAITABLE_TIMER_HPP
diff --git a/tools/sdk/include/asio/asio/bind_executor.hpp b/tools/sdk/include/asio/asio/bind_executor.hpp
deleted file mode 100644
index 9e2094b5443..00000000000
--- a/tools/sdk/include/asio/asio/bind_executor.hpp
+++ /dev/null
@@ -1,611 +0,0 @@
-//
-// bind_executor.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BIND_EXECUTOR_HPP
-#define ASIO_BIND_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/detail/variadic_templates.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/async_result.hpp"
-#include "asio/execution_context.hpp"
-#include "asio/is_executor.hpp"
-#include "asio/uses_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-struct executor_binder_check
-{
-  typedef void type;
-};
-
-// Helper to automatically define nested typedef result_type.
-
-template <typename T, typename = void>
-struct executor_binder_result_type
-{
-protected:
-  typedef void result_type_or_void;
-};
-
-template <typename T>
-struct executor_binder_result_type<T,
-  typename executor_binder_check<typename T::result_type>::type>
-{
-  typedef typename T::result_type result_type;
-protected:
-  typedef result_type result_type_or_void;
-};
-
-template <typename R>
-struct executor_binder_result_type<R(*)()>
-{
-  typedef R result_type;
-protected:
-  typedef result_type result_type_or_void;
-};
-
-template <typename R>
-struct executor_binder_result_type<R(&)()>
-{
-  typedef R result_type;
-protected:
-  typedef result_type result_type_or_void;
-};
-
-template <typename R, typename A1>
-struct executor_binder_result_type<R(*)(A1)>
-{
-  typedef R result_type;
-protected:
-  typedef result_type result_type_or_void;
-};
-
-template <typename R, typename A1>
-struct executor_binder_result_type<R(&)(A1)>
-{
-  typedef R result_type;
-protected:
-  typedef result_type result_type_or_void;
-};
-
-template <typename R, typename A1, typename A2>
-struct executor_binder_result_type<R(*)(A1, A2)>
-{
-  typedef R result_type;
-protected:
-  typedef result_type result_type_or_void;
-};
-
-template <typename R, typename A1, typename A2>
-struct executor_binder_result_type<R(&)(A1, A2)>
-{
-  typedef R result_type;
-protected:
-  typedef result_type result_type_or_void;
-};
-
-// Helper to automatically define nested typedef argument_type.
-
-template <typename T, typename = void>
-struct executor_binder_argument_type {};
-
-template <typename T>
-struct executor_binder_argument_type<T,
-  typename executor_binder_check<typename T::argument_type>::type>
-{
-  typedef typename T::argument_type argument_type;
-};
-
-template <typename R, typename A1>
-struct executor_binder_argument_type<R(*)(A1)>
-{
-  typedef A1 argument_type;
-};
-
-template <typename R, typename A1>
-struct executor_binder_argument_type<R(&)(A1)>
-{
-  typedef A1 argument_type;
-};
-
-// Helper to automatically define nested typedefs first_argument_type and
-// second_argument_type.
-
-template <typename T, typename = void>
-struct executor_binder_argument_types {};
-
-template <typename T>
-struct executor_binder_argument_types<T,
-  typename executor_binder_check<typename T::first_argument_type>::type>
-{
-  typedef typename T::first_argument_type first_argument_type;
-  typedef typename T::second_argument_type second_argument_type;
-};
-
-template <typename R, typename A1, typename A2>
-struct executor_binder_argument_type<R(*)(A1, A2)>
-{
-  typedef A1 first_argument_type;
-  typedef A2 second_argument_type;
-};
-
-template <typename R, typename A1, typename A2>
-struct executor_binder_argument_type<R(&)(A1, A2)>
-{
-  typedef A1 first_argument_type;
-  typedef A2 second_argument_type;
-};
-
-// Helper to:
-// - Apply the empty base optimisation to the executor.
-// - Perform uses_executor construction of the target type, if required.
-
-template <typename T, typename Executor, bool UsesExecutor>
-class executor_binder_base;
-
-template <typename T, typename Executor>
-class executor_binder_base<T, Executor, true>
-  : protected Executor
-{
-protected:
-  template <typename E, typename U>
-  executor_binder_base(ASIO_MOVE_ARG(E) e, ASIO_MOVE_ARG(U) u)
-    : executor_(ASIO_MOVE_CAST(E)(e)),
-      target_(executor_arg_t(), executor_, ASIO_MOVE_CAST(U)(u))
-  {
-  }
-
-  Executor executor_;
-  T target_;
-};
-
-template <typename T, typename Executor>
-class executor_binder_base<T, Executor, false>
-{
-protected:
-  template <typename E, typename U>
-  executor_binder_base(ASIO_MOVE_ARG(E) e, ASIO_MOVE_ARG(U) u)
-    : executor_(ASIO_MOVE_CAST(E)(e)),
-      target_(ASIO_MOVE_CAST(U)(u))
-  {
-  }
-
-  Executor executor_;
-  T target_;
-};
-
-// Helper to enable SFINAE on zero-argument operator() below.
-
-template <typename T, typename = void>
-struct executor_binder_result_of0
-{
-  typedef void type;
-};
-
-template <typename T>
-struct executor_binder_result_of0<T,
-  typename executor_binder_check<typename result_of<T()>::type>::type>
-{
-  typedef typename result_of<T()>::type type;
-};
-
-} // namespace detail
-
-/// A call wrapper type to bind an executor of type @c Executor to an object of
-/// type @c T.
-template <typename T, typename Executor>
-class executor_binder
-#if !defined(GENERATING_DOCUMENTATION)
-  : public detail::executor_binder_result_type<T>,
-    public detail::executor_binder_argument_type<T>,
-    public detail::executor_binder_argument_types<T>,
-    private detail::executor_binder_base<
-      T, Executor, uses_executor<T, Executor>::value>
-#endif // !defined(GENERATING_DOCUMENTATION)
-{
-public:
-  /// The type of the target object.
-  typedef T target_type;
-
-  /// The type of the associated executor.
-  typedef Executor executor_type;
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// The return type if a function.
-  /**
-   * The type of @c result_type is based on the type @c T of the wrapper's
-   * target object:
-   *
-   * @li if @c T is a pointer to function type, @c result_type is a synonym for
-   * the return type of @c T;
-   *
-   * @li if @c T is a class type with a member type @c result_type, then @c
-   * result_type is a synonym for @c T::result_type;
-   *
-   * @li otherwise @c result_type is not defined.
-   */
-  typedef see_below result_type;
-
-  /// The type of the function's argument.
-  /**
-   * The type of @c argument_type is based on the type @c T of the wrapper's
-   * target object:
-   *
-   * @li if @c T is a pointer to a function type accepting a single argument,
-   * @c argument_type is a synonym for the return type of @c T;
-   *
-   * @li if @c T is a class type with a member type @c argument_type, then @c
-   * argument_type is a synonym for @c T::argument_type;
-   *
-   * @li otherwise @c argument_type is not defined.
-   */
-  typedef see_below argument_type;
-
-  /// The type of the function's first argument.
-  /**
-   * The type of @c first_argument_type is based on the type @c T of the
-   * wrapper's target object:
-   *
-   * @li if @c T is a pointer to a function type accepting two arguments, @c
-   * first_argument_type is a synonym for the return type of @c T;
-   *
-   * @li if @c T is a class type with a member type @c first_argument_type,
-   * then @c first_argument_type is a synonym for @c T::first_argument_type;
-   *
-   * @li otherwise @c first_argument_type is not defined.
-   */
-  typedef see_below first_argument_type;
-
-  /// The type of the function's second argument.
-  /**
-   * The type of @c second_argument_type is based on the type @c T of the
-   * wrapper's target object:
-   *
-   * @li if @c T is a pointer to a function type accepting two arguments, @c
-   * second_argument_type is a synonym for the return type of @c T;
-   *
-   * @li if @c T is a class type with a member type @c first_argument_type,
-   * then @c second_argument_type is a synonym for @c T::second_argument_type;
-   *
-   * @li otherwise @c second_argument_type is not defined.
-   */
-  typedef see_below second_argument_type;
-#endif // defined(GENERATING_DOCUMENTATION)
-
-  /// Construct an executor wrapper for the specified object.
-  /**
-   * This constructor is only valid if the type @c T is constructible from type
-   * @c U.
-   */
-  template <typename U>
-  executor_binder(executor_arg_t, const executor_type& e,
-      ASIO_MOVE_ARG(U) u)
-    : base_type(e, ASIO_MOVE_CAST(U)(u))
-  {
-  }
-
-  /// Copy constructor.
-  executor_binder(const executor_binder& other)
-    : base_type(other.get_executor(), other.get())
-  {
-  }
-
-  /// Construct a copy, but specify a different executor.
-  executor_binder(executor_arg_t, const executor_type& e,
-      const executor_binder& other)
-    : base_type(e, other.get())
-  {
-  }
-
-  /// Construct a copy of a different executor wrapper type.
-  /**
-   * This constructor is only valid if the @c Executor type is constructible
-   * from type @c OtherExecutor, and the type @c T is constructible from type
-   * @c U.
-   */
-  template <typename U, typename OtherExecutor>
-  executor_binder(const executor_binder<U, OtherExecutor>& other)
-    : base_type(other.get_executor(), other.get())
-  {
-  }
-
-  /// Construct a copy of a different executor wrapper type, but specify a
-  /// different executor.
-  /**
-   * This constructor is only valid if the type @c T is constructible from type
-   * @c U.
-   */
-  template <typename U, typename OtherExecutor>
-  executor_binder(executor_arg_t, const executor_type& e,
-      const executor_binder<U, OtherExecutor>& other)
-    : base_type(e, other.get())
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Move constructor.
-  executor_binder(executor_binder&& other)
-    : base_type(ASIO_MOVE_CAST(executor_type)(other.get_executor()),
-        ASIO_MOVE_CAST(T)(other.get()))
-  {
-  }
-
-  /// Move construct the target object, but specify a different executor.
-  executor_binder(executor_arg_t, const executor_type& e,
-      executor_binder&& other)
-    : base_type(e, ASIO_MOVE_CAST(T)(other.get()))
-  {
-  }
-
-  /// Move construct from a different executor wrapper type.
-  template <typename U, typename OtherExecutor>
-  executor_binder(executor_binder<U, OtherExecutor>&& other)
-    : base_type(ASIO_MOVE_CAST(OtherExecutor)(other.get_executor()),
-        ASIO_MOVE_CAST(U)(other.get()))
-  {
-  }
-
-  /// Move construct from a different executor wrapper type, but specify a
-  /// different executor.
-  template <typename U, typename OtherExecutor>
-  executor_binder(executor_arg_t, const executor_type& e,
-      executor_binder<U, OtherExecutor>&& other)
-    : base_type(e, ASIO_MOVE_CAST(U)(other.get()))
-  {
-  }
-
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destructor.
-  ~executor_binder()
-  {
-  }
-
-  /// Obtain a reference to the target object.
-  target_type& get() ASIO_NOEXCEPT
-  {
-    return this->target_;
-  }
-
-  /// Obtain a reference to the target object.
-  const target_type& get() const ASIO_NOEXCEPT
-  {
-    return this->target_;
-  }
-
-  /// Obtain the associated executor.
-  executor_type get_executor() const ASIO_NOEXCEPT
-  {
-    return this->executor_;
-  }
-
-#if defined(GENERATING_DOCUMENTATION)
-
-  template <typename... Args> auto operator()(Args&& ...);
-  template <typename... Args> auto operator()(Args&& ...) const;
-
-#elif defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  /// Forwarding function call operator.
-  template <typename... Args>
-  typename result_of<T(Args...)>::type operator()(
-      ASIO_MOVE_ARG(Args)... args)
-  {
-    return this->target_(ASIO_MOVE_CAST(Args)(args)...);
-  }
-
-  /// Forwarding function call operator.
-  template <typename... Args>
-  typename result_of<T(Args...)>::type operator()(
-      ASIO_MOVE_ARG(Args)... args) const
-  {
-    return this->target_(ASIO_MOVE_CAST(Args)(args)...);
-  }
-
-#elif defined(ASIO_HAS_STD_TYPE_TRAITS) && !defined(_MSC_VER)
-
-  typename detail::executor_binder_result_of0<T>::type operator()()
-  {
-    return this->target_();
-  }
-
-  typename detail::executor_binder_result_of0<T>::type operator()() const
-  {
-    return this->target_();
-  }
-
-#define ASIO_PRIVATE_BIND_EXECUTOR_CALL_DEF(n) \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  typename result_of<T(ASIO_VARIADIC_TARGS(n))>::type operator()( \
-      ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  { \
-    return this->target_(ASIO_VARIADIC_MOVE_ARGS(n)); \
-  } \
-  \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  typename result_of<T(ASIO_VARIADIC_TARGS(n))>::type operator()( \
-      ASIO_VARIADIC_MOVE_PARAMS(n)) const \
-  { \
-    return this->target_(ASIO_VARIADIC_MOVE_ARGS(n)); \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_BIND_EXECUTOR_CALL_DEF)
-#undef ASIO_PRIVATE_BIND_EXECUTOR_CALL_DEF
-
-#else // defined(ASIO_HAS_STD_TYPE_TRAITS) && !defined(_MSC_VER)
-
-  typedef typename detail::executor_binder_result_type<T>::result_type_or_void
-    result_type_or_void;
-
-  result_type_or_void operator()()
-  {
-    return this->target_();
-  }
-
-  result_type_or_void operator()() const
-  {
-    return this->target_();
-  }
-
-#define ASIO_PRIVATE_BIND_EXECUTOR_CALL_DEF(n) \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  result_type_or_void operator()( \
-      ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  { \
-    return this->target_(ASIO_VARIADIC_MOVE_ARGS(n)); \
-  } \
-  \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  result_type_or_void operator()( \
-      ASIO_VARIADIC_MOVE_PARAMS(n)) const \
-  { \
-    return this->target_(ASIO_VARIADIC_MOVE_ARGS(n)); \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_BIND_EXECUTOR_CALL_DEF)
-#undef ASIO_PRIVATE_BIND_EXECUTOR_CALL_DEF
-
-#endif // defined(ASIO_HAS_STD_TYPE_TRAITS) && !defined(_MSC_VER)
-
-private:
-  typedef detail::executor_binder_base<T, Executor,
-    uses_executor<T, Executor>::value> base_type;
-};
-
-/// Associate an object of type @c T with an executor of type @c Executor.
-template <typename Executor, typename T>
-inline executor_binder<typename decay<T>::type, Executor>
-bind_executor(const Executor& ex, ASIO_MOVE_ARG(T) t,
-    typename enable_if<is_executor<Executor>::value>::type* = 0)
-{
-  return executor_binder<typename decay<T>::type, Executor>(
-      executor_arg_t(), ex, ASIO_MOVE_CAST(T)(t));
-}
-
-/// Associate an object of type @c T with an execution context's executor.
-template <typename ExecutionContext, typename T>
-inline executor_binder<typename decay<T>::type,
-  typename ExecutionContext::executor_type>
-bind_executor(ExecutionContext& ctx, ASIO_MOVE_ARG(T) t,
-    typename enable_if<is_convertible<
-      ExecutionContext&, execution_context&>::value>::type* = 0)
-{
-  return executor_binder<typename decay<T>::type,
-    typename ExecutionContext::executor_type>(
-      executor_arg_t(), ctx.get_executor(), ASIO_MOVE_CAST(T)(t));
-}
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename T, typename Executor>
-struct uses_executor<executor_binder<T, Executor>, Executor>
-  : true_type {};
-
-template <typename T, typename Executor, typename Signature>
-class async_result<executor_binder<T, Executor>, Signature>
-{
-public:
-  typedef executor_binder<
-    typename async_result<T, Signature>::completion_handler_type, Executor>
-      completion_handler_type;
-
-  typedef typename async_result<T, Signature>::return_type return_type;
-
-  explicit async_result(executor_binder<T, Executor>& b)
-    : target_(b.get())
-  {
-  }
-
-  return_type get()
-  {
-    return target_.get();
-  }
-
-private:
-  async_result(const async_result&) ASIO_DELETED;
-  async_result& operator=(const async_result&) ASIO_DELETED;
-
-  async_result<T, Signature> target_;
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-template <typename T, typename Executor, typename Signature>
-struct handler_type<executor_binder<T, Executor>, Signature>
-{
-  typedef executor_binder<
-    typename handler_type<T, Signature>::type, Executor> type;
-};
-
-template <typename T, typename Executor>
-class async_result<executor_binder<T, Executor> >
-{
-public:
-  typedef typename async_result<T>::type type;
-
-  explicit async_result(executor_binder<T, Executor>& b)
-    : target_(b.get())
-  {
-  }
-
-  type get()
-  {
-    return target_.get();
-  }
-
-private:
-  async_result<T> target_;
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename T, typename Executor, typename Allocator>
-struct associated_allocator<executor_binder<T, Executor>, Allocator>
-{
-  typedef typename associated_allocator<T, Allocator>::type type;
-
-  static type get(const executor_binder<T, Executor>& b,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<T, Allocator>::get(b.get(), a);
-  }
-};
-
-template <typename T, typename Executor, typename Executor1>
-struct associated_executor<executor_binder<T, Executor>, Executor1>
-{
-  typedef Executor type;
-
-  static type get(const executor_binder<T, Executor>& b,
-      const Executor1& = Executor1()) ASIO_NOEXCEPT
-  {
-    return b.get_executor();
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_BIND_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/buffer.hpp b/tools/sdk/include/asio/asio/buffer.hpp
deleted file mode 100644
index a9aa8aad272..00000000000
--- a/tools/sdk/include/asio/asio/buffer.hpp
+++ /dev/null
@@ -1,2162 +0,0 @@
-//
-// buffer.hpp
-// ~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BUFFER_HPP
-#define ASIO_BUFFER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <cstring>
-#include <limits>
-#include <stdexcept>
-#include <string>
-#include <vector>
-#include "asio/detail/array_fwd.hpp"
-#include "asio/detail/is_buffer_sequence.hpp"
-#include "asio/detail/string_view.hpp"
-#include "asio/detail/throw_exception.hpp"
-#include "asio/detail/type_traits.hpp"
-
-#if defined(ASIO_MSVC) && (ASIO_MSVC >= 1700)
-# if defined(_HAS_ITERATOR_DEBUGGING) && (_HAS_ITERATOR_DEBUGGING != 0)
-#  if !defined(ASIO_DISABLE_BUFFER_DEBUGGING)
-#   define ASIO_ENABLE_BUFFER_DEBUGGING
-#  endif // !defined(ASIO_DISABLE_BUFFER_DEBUGGING)
-# endif // defined(_HAS_ITERATOR_DEBUGGING)
-#endif // defined(ASIO_MSVC) && (ASIO_MSVC >= 1700)
-
-#if defined(__GNUC__)
-# if defined(_GLIBCXX_DEBUG)
-#  if !defined(ASIO_DISABLE_BUFFER_DEBUGGING)
-#   define ASIO_ENABLE_BUFFER_DEBUGGING
-#  endif // !defined(ASIO_DISABLE_BUFFER_DEBUGGING)
-# endif // defined(_GLIBCXX_DEBUG)
-#endif // defined(__GNUC__)
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-# include "asio/detail/functional.hpp"
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-
-#if defined(ASIO_HAS_BOOST_WORKAROUND)
-# include <boost/detail/workaround.hpp>
-# if BOOST_WORKAROUND(__BORLANDC__, BOOST_TESTED_AT(0x582)) \
-    || BOOST_WORKAROUND(__SUNPRO_CC, BOOST_TESTED_AT(0x590))
-#  define ASIO_ENABLE_ARRAY_BUFFER_WORKAROUND
-# endif // BOOST_WORKAROUND(__BORLANDC__, BOOST_TESTED_AT(0x582))
-        // || BOOST_WORKAROUND(__SUNPRO_CC, BOOST_TESTED_AT(0x590))
-#endif // defined(ASIO_HAS_BOOST_WORKAROUND)
-
-#if defined(ASIO_ENABLE_ARRAY_BUFFER_WORKAROUND)
-# include "asio/detail/type_traits.hpp"
-#endif // defined(ASIO_ENABLE_ARRAY_BUFFER_WORKAROUND)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-class mutable_buffer;
-class const_buffer;
-
-/// Holds a buffer that can be modified.
-/**
- * The mutable_buffer class provides a safe representation of a buffer that can
- * be modified. It does not own the underlying data, and so is cheap to copy or
- * assign.
- *
- * @par Accessing Buffer Contents
- *
- * The contents of a buffer may be accessed using the @c data() and @c size()
- * member functions:
- *
- * @code asio::mutable_buffer b1 = ...;
- * std::size_t s1 = b1.size();
- * unsigned char* p1 = static_cast<unsigned char*>(b1.data());
- * @endcode
- *
- * The @c data() member function permits violations of type safety, so uses of
- * it in application code should be carefully considered.
- */
-class mutable_buffer
-{
-public:
-  /// Construct an empty buffer.
-  mutable_buffer() ASIO_NOEXCEPT
-    : data_(0),
-      size_(0)
-  {
-  }
-
-  /// Construct a buffer to represent a given memory range.
-  mutable_buffer(void* data, std::size_t size) ASIO_NOEXCEPT
-    : data_(data),
-      size_(size)
-  {
-  }
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-  mutable_buffer(void* data, std::size_t size,
-      asio::detail::function<void()> debug_check)
-    : data_(data),
-      size_(size),
-      debug_check_(debug_check)
-  {
-  }
-
-  const asio::detail::function<void()>& get_debug_check() const
-  {
-    return debug_check_;
-  }
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-
-  /// Get a pointer to the beginning of the memory range.
-  void* data() const ASIO_NOEXCEPT
-  {
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    if (size_ && debug_check_)
-      debug_check_();
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-    return data_;
-  }
-
-  /// Get the size of the memory range.
-  std::size_t size() const ASIO_NOEXCEPT
-  {
-    return size_;
-  }
-
-  /// Move the start of the buffer by the specified number of bytes.
-  mutable_buffer& operator+=(std::size_t n) ASIO_NOEXCEPT
-  {
-    std::size_t offset = n < size_ ? n : size_;
-    data_ = static_cast<char*>(data_) + offset;
-    size_ -= offset;
-    return *this;
-  }
-
-private:
-  void* data_;
-  std::size_t size_;
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-  asio::detail::function<void()> debug_check_;
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-/// (Deprecated: Use mutable_buffer.) Adapts a single modifiable buffer so that
-/// it meets the requirements of the MutableBufferSequence concept.
-class mutable_buffers_1
-  : public mutable_buffer
-{
-public:
-  /// The type for each element in the list of buffers.
-  typedef mutable_buffer value_type;
-
-  /// A random-access iterator type that may be used to read elements.
-  typedef const mutable_buffer* const_iterator;
-
-  /// Construct to represent a given memory range.
-  mutable_buffers_1(void* data, std::size_t size) ASIO_NOEXCEPT
-    : mutable_buffer(data, size)
-  {
-  }
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-  mutable_buffers_1(void* data, std::size_t size,
-      asio::detail::function<void()> debug_check)
-    : mutable_buffer(data, size, debug_check)
-  {
-  }
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-
-  /// Construct to represent a single modifiable buffer.
-  explicit mutable_buffers_1(const mutable_buffer& b) ASIO_NOEXCEPT
-    : mutable_buffer(b)
-  {
-  }
-
-  /// Get a random-access iterator to the first element.
-  const_iterator begin() const ASIO_NOEXCEPT
-  {
-    return this;
-  }
-
-  /// Get a random-access iterator for one past the last element.
-  const_iterator end() const ASIO_NOEXCEPT
-  {
-    return begin() + 1;
-  }
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-/// Holds a buffer that cannot be modified.
-/**
- * The const_buffer class provides a safe representation of a buffer that cannot
- * be modified. It does not own the underlying data, and so is cheap to copy or
- * assign.
- *
- * @par Accessing Buffer Contents
- *
- * The contents of a buffer may be accessed using the @c data() and @c size()
- * member functions:
- *
- * @code asio::const_buffer b1 = ...;
- * std::size_t s1 = b1.size();
- * const unsigned char* p1 = static_cast<const unsigned char*>(b1.data());
- * @endcode
- *
- * The @c data() member function permits violations of type safety, so uses of
- * it in application code should be carefully considered.
- */
-class const_buffer
-{
-public:
-  /// Construct an empty buffer.
-  const_buffer() ASIO_NOEXCEPT
-    : data_(0),
-      size_(0)
-  {
-  }
-
-  /// Construct a buffer to represent a given memory range.
-  const_buffer(const void* data, std::size_t size) ASIO_NOEXCEPT
-    : data_(data),
-      size_(size)
-  {
-  }
-
-  /// Construct a non-modifiable buffer from a modifiable one.
-  const_buffer(const mutable_buffer& b) ASIO_NOEXCEPT
-    : data_(b.data()),
-      size_(b.size())
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , debug_check_(b.get_debug_check())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-  {
-  }
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-  const_buffer(const void* data, std::size_t size,
-      asio::detail::function<void()> debug_check)
-    : data_(data),
-      size_(size),
-      debug_check_(debug_check)
-  {
-  }
-
-  const asio::detail::function<void()>& get_debug_check() const
-  {
-    return debug_check_;
-  }
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-
-  /// Get a pointer to the beginning of the memory range.
-  const void* data() const ASIO_NOEXCEPT
-  {
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    if (size_ && debug_check_)
-      debug_check_();
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-    return data_;
-  }
-
-  /// Get the size of the memory range.
-  std::size_t size() const ASIO_NOEXCEPT
-  {
-    return size_;
-  }
-
-  /// Move the start of the buffer by the specified number of bytes.
-  const_buffer& operator+=(std::size_t n) ASIO_NOEXCEPT
-  {
-    std::size_t offset = n < size_ ? n : size_;
-    data_ = static_cast<const char*>(data_) + offset;
-    size_ -= offset;
-    return *this;
-  }
-
-private:
-  const void* data_;
-  std::size_t size_;
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-  asio::detail::function<void()> debug_check_;
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-/// (Deprecated: Use const_buffer.) Adapts a single non-modifiable buffer so
-/// that it meets the requirements of the ConstBufferSequence concept.
-class const_buffers_1
-  : public const_buffer
-{
-public:
-  /// The type for each element in the list of buffers.
-  typedef const_buffer value_type;
-
-  /// A random-access iterator type that may be used to read elements.
-  typedef const const_buffer* const_iterator;
-
-  /// Construct to represent a given memory range.
-  const_buffers_1(const void* data, std::size_t size) ASIO_NOEXCEPT
-    : const_buffer(data, size)
-  {
-  }
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-  const_buffers_1(const void* data, std::size_t size,
-      asio::detail::function<void()> debug_check)
-    : const_buffer(data, size, debug_check)
-  {
-  }
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-
-  /// Construct to represent a single non-modifiable buffer.
-  explicit const_buffers_1(const const_buffer& b) ASIO_NOEXCEPT
-    : const_buffer(b)
-  {
-  }
-
-  /// Get a random-access iterator to the first element.
-  const_iterator begin() const ASIO_NOEXCEPT
-  {
-    return this;
-  }
-
-  /// Get a random-access iterator for one past the last element.
-  const_iterator end() const ASIO_NOEXCEPT
-  {
-    return begin() + 1;
-  }
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-/// Trait to determine whether a type satisfies the MutableBufferSequence
-/// requirements.
-template <typename T>
-struct is_mutable_buffer_sequence
-#if defined(GENERATING_DOCUMENTATION)
-  : integral_constant<bool, automatically_determined>
-#else // defined(GENERATING_DOCUMENTATION)
-  : asio::detail::is_buffer_sequence<T, mutable_buffer>
-#endif // defined(GENERATING_DOCUMENTATION)
-{
-};
-
-/// Trait to determine whether a type satisfies the ConstBufferSequence
-/// requirements.
-template <typename T>
-struct is_const_buffer_sequence
-#if defined(GENERATING_DOCUMENTATION)
-  : integral_constant<bool, automatically_determined>
-#else // defined(GENERATING_DOCUMENTATION)
-  : asio::detail::is_buffer_sequence<T, const_buffer>
-#endif // defined(GENERATING_DOCUMENTATION)
-{
-};
-
-/// Trait to determine whether a type satisfies the DynamicBuffer requirements.
-template <typename T>
-struct is_dynamic_buffer
-#if defined(GENERATING_DOCUMENTATION)
-  : integral_constant<bool, automatically_determined>
-#else // defined(GENERATING_DOCUMENTATION)
-  : asio::detail::is_dynamic_buffer<T>
-#endif // defined(GENERATING_DOCUMENTATION)
-{
-};
-
-/// (Deprecated: Use the socket/descriptor wait() and async_wait() member
-/// functions.) An implementation of both the ConstBufferSequence and
-/// MutableBufferSequence concepts to represent a null buffer sequence.
-class null_buffers
-{
-public:
-  /// The type for each element in the list of buffers.
-  typedef mutable_buffer value_type;
-
-  /// A random-access iterator type that may be used to read elements.
-  typedef const mutable_buffer* const_iterator;
-
-  /// Get a random-access iterator to the first element.
-  const_iterator begin() const ASIO_NOEXCEPT
-  {
-    return &buf_;
-  }
-
-  /// Get a random-access iterator for one past the last element.
-  const_iterator end() const ASIO_NOEXCEPT
-  {
-    return &buf_;
-  }
-
-private:
-  mutable_buffer buf_;
-};
-
-/** @defgroup buffer_sequence_begin asio::buffer_sequence_begin
- *
- * @brief The asio::buffer_sequence_begin function returns an iterator
- * pointing to the first element in a buffer sequence.
- */
-/*@{*/
-
-/// Get an iterator to the first element in a buffer sequence.
-inline const mutable_buffer* buffer_sequence_begin(const mutable_buffer& b)
-{
-  return &b;
-}
-
-/// Get an iterator to the first element in a buffer sequence.
-inline const const_buffer* buffer_sequence_begin(const const_buffer& b)
-{
-  return &b;
-}
-
-#if defined(ASIO_HAS_DECLTYPE) || defined(GENERATING_DOCUMENTATION)
-
-/// Get an iterator to the first element in a buffer sequence.
-template <typename C>
-inline auto buffer_sequence_begin(C& c) -> decltype(c.begin())
-{
-  return c.begin();
-}
-
-/// Get an iterator to the first element in a buffer sequence.
-template <typename C>
-inline auto buffer_sequence_begin(const C& c) -> decltype(c.begin())
-{
-  return c.begin();
-}
-
-#else // defined(ASIO_HAS_DECLTYPE) || defined(GENERATING_DOCUMENTATION)
-
-template <typename C>
-inline typename C::iterator buffer_sequence_begin(C& c)
-{
-  return c.begin();
-}
-
-template <typename C>
-inline typename C::const_iterator buffer_sequence_begin(const C& c)
-{
-  return c.begin();
-}
-
-#endif // defined(ASIO_HAS_DECLTYPE) || defined(GENERATING_DOCUMENTATION)
-
-/*@}*/
-
-/** @defgroup buffer_sequence_end asio::buffer_sequence_end
- *
- * @brief The asio::buffer_sequence_end function returns an iterator
- * pointing to one past the end element in a buffer sequence.
- */
-/*@{*/
-
-/// Get an iterator to one past the end element in a buffer sequence.
-inline const mutable_buffer* buffer_sequence_end(const mutable_buffer& b)
-{
-  return &b + 1;
-}
-
-/// Get an iterator to one past the end element in a buffer sequence.
-inline const const_buffer* buffer_sequence_end(const const_buffer& b)
-{
-  return &b + 1;
-}
-
-#if defined(ASIO_HAS_DECLTYPE) || defined(GENERATING_DOCUMENTATION)
-
-/// Get an iterator to one past the end element in a buffer sequence.
-template <typename C>
-inline auto buffer_sequence_end(C& c) -> decltype(c.end())
-{
-  return c.end();
-}
-
-/// Get an iterator to one past the end element in a buffer sequence.
-template <typename C>
-inline auto buffer_sequence_end(const C& c) -> decltype(c.end())
-{
-  return c.end();
-}
-
-#else // defined(ASIO_HAS_DECLTYPE) || defined(GENERATING_DOCUMENTATION)
-
-template <typename C>
-inline typename C::iterator buffer_sequence_end(C& c)
-{
-  return c.end();
-}
-
-template <typename C>
-inline typename C::const_iterator buffer_sequence_end(const C& c)
-{
-  return c.end();
-}
-
-#endif // defined(ASIO_HAS_DECLTYPE) || defined(GENERATING_DOCUMENTATION)
-
-/*@}*/
-
-namespace detail {
-
-// Tag types used to select appropriately optimised overloads.
-struct one_buffer {};
-struct multiple_buffers {};
-
-// Helper trait to detect single buffers.
-template <typename BufferSequence>
-struct buffer_sequence_cardinality :
-  conditional<
-    is_same<BufferSequence, mutable_buffer>::value
-#if !defined(ASIO_NO_DEPRECATED)
-      || is_same<BufferSequence, mutable_buffers_1>::value
-      || is_same<BufferSequence, const_buffers_1>::value
-#endif // !defined(ASIO_NO_DEPRECATED)
-      || is_same<BufferSequence, const_buffer>::value,
-    one_buffer, multiple_buffers>::type {};
-
-template <typename Iterator>
-inline std::size_t buffer_size(one_buffer,
-    Iterator begin, Iterator) ASIO_NOEXCEPT
-{
-  return const_buffer(*begin).size();
-}
-
-template <typename Iterator>
-inline std::size_t buffer_size(multiple_buffers,
-    Iterator begin, Iterator end) ASIO_NOEXCEPT
-{
-  std::size_t total_buffer_size = 0;
-
-  Iterator iter = begin;
-  for (; iter != end; ++iter)
-  {
-    const_buffer b(*iter);
-    total_buffer_size += b.size();
-  }
-
-  return total_buffer_size;
-}
-
-} // namespace detail
-
-/// Get the total number of bytes in a buffer sequence.
-/**
- * The @c buffer_size function determines the total size of all buffers in the
- * buffer sequence, as if computed as follows:
- *
- * @code size_t total_size = 0;
- * auto i = asio::buffer_sequence_begin(buffers);
- * auto end = asio::buffer_sequence_end(buffers);
- * for (; i != end; ++i)
- * {
- *   const_buffer b(*i);
- *   total_size += b.size();
- * }
- * return total_size; @endcode
- *
- * The @c BufferSequence template parameter may meet either of the @c
- * ConstBufferSequence or @c MutableBufferSequence type requirements.
- */
-template <typename BufferSequence>
-inline std::size_t buffer_size(const BufferSequence& b) ASIO_NOEXCEPT
-{
-  return detail::buffer_size(
-      detail::buffer_sequence_cardinality<BufferSequence>(),
-      asio::buffer_sequence_begin(b),
-      asio::buffer_sequence_end(b));
-}
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-/** @defgroup buffer_cast asio::buffer_cast
- *
- * @brief (Deprecated: Use the @c data() member function.) The
- * asio::buffer_cast function is used to obtain a pointer to the
- * underlying memory region associated with a buffer.
- *
- * @par Examples:
- *
- * To access the memory of a non-modifiable buffer, use:
- * @code asio::const_buffer b1 = ...;
- * const unsigned char* p1 = asio::buffer_cast<const unsigned char*>(b1);
- * @endcode
- *
- * To access the memory of a modifiable buffer, use:
- * @code asio::mutable_buffer b2 = ...;
- * unsigned char* p2 = asio::buffer_cast<unsigned char*>(b2);
- * @endcode
- *
- * The asio::buffer_cast function permits violations of type safety, so
- * uses of it in application code should be carefully considered.
- */
-/*@{*/
-
-/// Cast a non-modifiable buffer to a specified pointer to POD type.
-template <typename PointerToPodType>
-inline PointerToPodType buffer_cast(const mutable_buffer& b) ASIO_NOEXCEPT
-{
-  return static_cast<PointerToPodType>(b.data());
-}
-
-/// Cast a non-modifiable buffer to a specified pointer to POD type.
-template <typename PointerToPodType>
-inline PointerToPodType buffer_cast(const const_buffer& b) ASIO_NOEXCEPT
-{
-  return static_cast<PointerToPodType>(b.data());
-}
-
-/*@}*/
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-/// Create a new modifiable buffer that is offset from the start of another.
-/**
- * @relates mutable_buffer
- */
-inline mutable_buffer operator+(const mutable_buffer& b,
-    std::size_t n) ASIO_NOEXCEPT
-{
-  std::size_t offset = n < b.size() ? n : b.size();
-  char* new_data = static_cast<char*>(b.data()) + offset;
-  std::size_t new_size = b.size() - offset;
-  return mutable_buffer(new_data, new_size
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , b.get_debug_check()
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new modifiable buffer that is offset from the start of another.
-/**
- * @relates mutable_buffer
- */
-inline mutable_buffer operator+(std::size_t n,
-    const mutable_buffer& b) ASIO_NOEXCEPT
-{
-  return b + n;
-}
-
-/// Create a new non-modifiable buffer that is offset from the start of another.
-/**
- * @relates const_buffer
- */
-inline const_buffer operator+(const const_buffer& b,
-    std::size_t n) ASIO_NOEXCEPT
-{
-  std::size_t offset = n < b.size() ? n : b.size();
-  const char* new_data = static_cast<const char*>(b.data()) + offset;
-  std::size_t new_size = b.size() - offset;
-  return const_buffer(new_data, new_size
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , b.get_debug_check()
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new non-modifiable buffer that is offset from the start of another.
-/**
- * @relates const_buffer
- */
-inline const_buffer operator+(std::size_t n,
-    const const_buffer& b) ASIO_NOEXCEPT
-{
-  return b + n;
-}
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-namespace detail {
-
-template <typename Iterator>
-class buffer_debug_check
-{
-public:
-  buffer_debug_check(Iterator iter)
-    : iter_(iter)
-  {
-  }
-
-  ~buffer_debug_check()
-  {
-#if defined(ASIO_MSVC) && (ASIO_MSVC == 1400)
-    // MSVC 8's string iterator checking may crash in a std::string::iterator
-    // object's destructor when the iterator points to an already-destroyed
-    // std::string object, unless the iterator is cleared first.
-    iter_ = Iterator();
-#endif // defined(ASIO_MSVC) && (ASIO_MSVC == 1400)
-  }
-
-  void operator()()
-  {
-    (void)*iter_;
-  }
-
-private:
-  Iterator iter_;
-};
-
-} // namespace detail
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-
-/** @defgroup buffer asio::buffer
- *
- * @brief The asio::buffer function is used to create a buffer object to
- * represent raw memory, an array of POD elements, a vector of POD elements,
- * or a std::string.
- *
- * A buffer object represents a contiguous region of memory as a 2-tuple
- * consisting of a pointer and size in bytes. A tuple of the form <tt>{void*,
- * size_t}</tt> specifies a mutable (modifiable) region of memory. Similarly, a
- * tuple of the form <tt>{const void*, size_t}</tt> specifies a const
- * (non-modifiable) region of memory. These two forms correspond to the classes
- * mutable_buffer and const_buffer, respectively. To mirror C++'s conversion
- * rules, a mutable_buffer is implicitly convertible to a const_buffer, and the
- * opposite conversion is not permitted.
- *
- * The simplest use case involves reading or writing a single buffer of a
- * specified size:
- *
- * @code sock.send(asio::buffer(data, size)); @endcode
- *
- * In the above example, the return value of asio::buffer meets the
- * requirements of the ConstBufferSequence concept so that it may be directly
- * passed to the socket's write function. A buffer created for modifiable
- * memory also meets the requirements of the MutableBufferSequence concept.
- *
- * An individual buffer may be created from a builtin array, std::vector,
- * std::array or boost::array of POD elements. This helps prevent buffer
- * overruns by automatically determining the size of the buffer:
- *
- * @code char d1[128];
- * size_t bytes_transferred = sock.receive(asio::buffer(d1));
- *
- * std::vector<char> d2(128);
- * bytes_transferred = sock.receive(asio::buffer(d2));
- *
- * std::array<char, 128> d3;
- * bytes_transferred = sock.receive(asio::buffer(d3));
- *
- * boost::array<char, 128> d4;
- * bytes_transferred = sock.receive(asio::buffer(d4)); @endcode
- *
- * In all three cases above, the buffers created are exactly 128 bytes long.
- * Note that a vector is @e never automatically resized when creating or using
- * a buffer. The buffer size is determined using the vector's <tt>size()</tt>
- * member function, and not its capacity.
- *
- * @par Accessing Buffer Contents
- *
- * The contents of a buffer may be accessed using the @c data() and @c size()
- * member functions:
- *
- * @code asio::mutable_buffer b1 = ...;
- * std::size_t s1 = b1.size();
- * unsigned char* p1 = static_cast<unsigned char*>(b1.data());
- *
- * asio::const_buffer b2 = ...;
- * std::size_t s2 = b2.size();
- * const void* p2 = b2.data(); @endcode
- *
- * The @c data() member function permits violations of type safety, so
- * uses of it in application code should be carefully considered.
- *
- * For convenience, a @ref buffer_size function is provided that works with
- * both buffers and buffer sequences (that is, types meeting the
- * ConstBufferSequence or MutableBufferSequence type requirements). In this
- * case, the function returns the total size of all buffers in the sequence.
- *
- * @par Buffer Copying
- *
- * The @ref buffer_copy function may be used to copy raw bytes between
- * individual buffers and buffer sequences.
-*
- * In particular, when used with the @ref buffer_size function, the @ref
- * buffer_copy function can be used to linearise a sequence of buffers. For
- * example:
- *
- * @code vector<const_buffer> buffers = ...;
- *
- * vector<unsigned char> data(asio::buffer_size(buffers));
- * asio::buffer_copy(asio::buffer(data), buffers); @endcode
- *
- * Note that @ref buffer_copy is implemented in terms of @c memcpy, and
- * consequently it cannot be used to copy between overlapping memory regions.
- *
- * @par Buffer Invalidation
- *
- * A buffer object does not have any ownership of the memory it refers to. It
- * is the responsibility of the application to ensure the memory region remains
- * valid until it is no longer required for an I/O operation. When the memory
- * is no longer available, the buffer is said to have been invalidated.
- *
- * For the asio::buffer overloads that accept an argument of type
- * std::vector, the buffer objects returned are invalidated by any vector
- * operation that also invalidates all references, pointers and iterators
- * referring to the elements in the sequence (C++ Std, 23.2.4)
- *
- * For the asio::buffer overloads that accept an argument of type
- * std::basic_string, the buffer objects returned are invalidated according to
- * the rules defined for invalidation of references, pointers and iterators
- * referring to elements of the sequence (C++ Std, 21.3).
- *
- * @par Buffer Arithmetic
- *
- * Buffer objects may be manipulated using simple arithmetic in a safe way
- * which helps prevent buffer overruns. Consider an array initialised as
- * follows:
- *
- * @code boost::array<char, 6> a = { 'a', 'b', 'c', 'd', 'e' }; @endcode
- *
- * A buffer object @c b1 created using:
- *
- * @code b1 = asio::buffer(a); @endcode
- *
- * represents the entire array, <tt>{ 'a', 'b', 'c', 'd', 'e' }</tt>. An
- * optional second argument to the asio::buffer function may be used to
- * limit the size, in bytes, of the buffer:
- *
- * @code b2 = asio::buffer(a, 3); @endcode
- *
- * such that @c b2 represents the data <tt>{ 'a', 'b', 'c' }</tt>. Even if the
- * size argument exceeds the actual size of the array, the size of the buffer
- * object created will be limited to the array size.
- *
- * An offset may be applied to an existing buffer to create a new one:
- *
- * @code b3 = b1 + 2; @endcode
- *
- * where @c b3 will set to represent <tt>{ 'c', 'd', 'e' }</tt>. If the offset
- * exceeds the size of the existing buffer, the newly created buffer will be
- * empty.
- *
- * Both an offset and size may be specified to create a buffer that corresponds
- * to a specific range of bytes within an existing buffer:
- *
- * @code b4 = asio::buffer(b1 + 1, 3); @endcode
- *
- * so that @c b4 will refer to the bytes <tt>{ 'b', 'c', 'd' }</tt>.
- *
- * @par Buffers and Scatter-Gather I/O
- *
- * To read or write using multiple buffers (i.e. scatter-gather I/O), multiple
- * buffer objects may be assigned into a container that supports the
- * MutableBufferSequence (for read) or ConstBufferSequence (for write) concepts:
- *
- * @code
- * char d1[128];
- * std::vector<char> d2(128);
- * boost::array<char, 128> d3;
- *
- * boost::array<mutable_buffer, 3> bufs1 = {
- *   asio::buffer(d1),
- *   asio::buffer(d2),
- *   asio::buffer(d3) };
- * bytes_transferred = sock.receive(bufs1);
- *
- * std::vector<const_buffer> bufs2;
- * bufs2.push_back(asio::buffer(d1));
- * bufs2.push_back(asio::buffer(d2));
- * bufs2.push_back(asio::buffer(d3));
- * bytes_transferred = sock.send(bufs2); @endcode
- */
-/*@{*/
-
-#if defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-# define ASIO_MUTABLE_BUFFER mutable_buffer
-# define ASIO_CONST_BUFFER const_buffer
-#else // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-# define ASIO_MUTABLE_BUFFER mutable_buffers_1
-# define ASIO_CONST_BUFFER const_buffers_1
-#endif // defined(ASIO_NO_DEPRECATED) || defined(GENERATING_DOCUMENTATION)
-
-/// Create a new modifiable buffer from an existing buffer.
-/**
- * @returns <tt>mutable_buffer(b)</tt>.
- */
-inline ASIO_MUTABLE_BUFFER buffer(
-    const mutable_buffer& b) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(b);
-}
-
-/// Create a new modifiable buffer from an existing buffer.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     b.data(),
- *     min(b.size(), max_size_in_bytes)); @endcode
- */
-inline ASIO_MUTABLE_BUFFER buffer(const mutable_buffer& b,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(
-      mutable_buffer(b.data(),
-        b.size() < max_size_in_bytes
-        ? b.size() : max_size_in_bytes
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-        , b.get_debug_check()
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-        ));
-}
-
-/// Create a new non-modifiable buffer from an existing buffer.
-/**
- * @returns <tt>const_buffer(b)</tt>.
- */
-inline ASIO_CONST_BUFFER buffer(
-    const const_buffer& b) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(b);
-}
-
-/// Create a new non-modifiable buffer from an existing buffer.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     b.data(),
- *     min(b.size(), max_size_in_bytes)); @endcode
- */
-inline ASIO_CONST_BUFFER buffer(const const_buffer& b,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(b.data(),
-      b.size() < max_size_in_bytes
-      ? b.size() : max_size_in_bytes
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , b.get_debug_check()
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new modifiable buffer that represents the given memory range.
-/**
- * @returns <tt>mutable_buffer(data, size_in_bytes)</tt>.
- */
-inline ASIO_MUTABLE_BUFFER buffer(void* data,
-    std::size_t size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(data, size_in_bytes);
-}
-
-/// Create a new non-modifiable buffer that represents the given memory range.
-/**
- * @returns <tt>const_buffer(data, size_in_bytes)</tt>.
- */
-inline ASIO_CONST_BUFFER buffer(const void* data,
-    std::size_t size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data, size_in_bytes);
-}
-
-/// Create a new modifiable buffer that represents the given POD array.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     static_cast<void*>(data),
- *     N * sizeof(PodType)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_MUTABLE_BUFFER buffer(PodType (&data)[N]) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(data, N * sizeof(PodType));
-}
- 
-/// Create a new modifiable buffer that represents the given POD array.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     static_cast<void*>(data),
- *     min(N * sizeof(PodType), max_size_in_bytes)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_MUTABLE_BUFFER buffer(PodType (&data)[N],
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(data,
-      N * sizeof(PodType) < max_size_in_bytes
-      ? N * sizeof(PodType) : max_size_in_bytes);
-}
- 
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     static_cast<const void*>(data),
- *     N * sizeof(PodType)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(
-    const PodType (&data)[N]) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data, N * sizeof(PodType));
-}
-
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     static_cast<const void*>(data),
- *     min(N * sizeof(PodType), max_size_in_bytes)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(const PodType (&data)[N],
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data,
-      N * sizeof(PodType) < max_size_in_bytes
-      ? N * sizeof(PodType) : max_size_in_bytes);
-}
-
-#if defined(ASIO_ENABLE_ARRAY_BUFFER_WORKAROUND)
-
-// Borland C++ and Sun Studio think the overloads:
-//
-//   unspecified buffer(boost::array<PodType, N>& array ...);
-//
-// and
-//
-//   unspecified buffer(boost::array<const PodType, N>& array ...);
-//
-// are ambiguous. This will be worked around by using a buffer_types traits
-// class that contains typedefs for the appropriate buffer and container
-// classes, based on whether PodType is const or non-const.
-
-namespace detail {
-
-template <bool IsConst>
-struct buffer_types_base;
-
-template <>
-struct buffer_types_base<false>
-{
-  typedef mutable_buffer buffer_type;
-  typedef ASIO_MUTABLE_BUFFER container_type;
-};
-
-template <>
-struct buffer_types_base<true>
-{
-  typedef const_buffer buffer_type;
-  typedef ASIO_CONST_BUFFER container_type;
-};
-
-template <typename PodType>
-struct buffer_types
-  : public buffer_types_base<is_const<PodType>::value>
-{
-};
-
-} // namespace detail
-
-template <typename PodType, std::size_t N>
-inline typename detail::buffer_types<PodType>::container_type
-buffer(boost::array<PodType, N>& data) ASIO_NOEXCEPT
-{
-  typedef typename asio::detail::buffer_types<PodType>::buffer_type
-    buffer_type;
-  typedef typename asio::detail::buffer_types<PodType>::container_type
-    container_type;
-  return container_type(
-      buffer_type(data.c_array(), data.size() * sizeof(PodType)));
-}
-
-template <typename PodType, std::size_t N>
-inline typename detail::buffer_types<PodType>::container_type
-buffer(boost::array<PodType, N>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  typedef typename asio::detail::buffer_types<PodType>::buffer_type
-    buffer_type;
-  typedef typename asio::detail::buffer_types<PodType>::container_type
-    container_type;
-  return container_type(
-      buffer_type(data.c_array(),
-        data.size() * sizeof(PodType) < max_size_in_bytes
-        ? data.size() * sizeof(PodType) : max_size_in_bytes));
-}
-
-#else // defined(ASIO_ENABLE_ARRAY_BUFFER_WORKAROUND)
-
-/// Create a new modifiable buffer that represents the given POD array.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     data.data(),
- *     data.size() * sizeof(PodType)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_MUTABLE_BUFFER buffer(
-    boost::array<PodType, N>& data) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(
-      data.c_array(), data.size() * sizeof(PodType));
-}
-
-/// Create a new modifiable buffer that represents the given POD array.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     data.data(),
- *     min(data.size() * sizeof(PodType), max_size_in_bytes)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_MUTABLE_BUFFER buffer(boost::array<PodType, N>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(data.c_array(),
-      data.size() * sizeof(PodType) < max_size_in_bytes
-      ? data.size() * sizeof(PodType) : max_size_in_bytes);
-}
-
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.data(),
- *     data.size() * sizeof(PodType)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(
-    boost::array<const PodType, N>& data) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(), data.size() * sizeof(PodType));
-}
-
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.data(),
- *     min(data.size() * sizeof(PodType), max_size_in_bytes)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(boost::array<const PodType, N>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(),
-      data.size() * sizeof(PodType) < max_size_in_bytes
-      ? data.size() * sizeof(PodType) : max_size_in_bytes);
-}
-
-#endif // defined(ASIO_ENABLE_ARRAY_BUFFER_WORKAROUND)
-
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.data(),
- *     data.size() * sizeof(PodType)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(
-    const boost::array<PodType, N>& data) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(), data.size() * sizeof(PodType));
-}
-
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.data(),
- *     min(data.size() * sizeof(PodType), max_size_in_bytes)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(const boost::array<PodType, N>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(),
-      data.size() * sizeof(PodType) < max_size_in_bytes
-      ? data.size() * sizeof(PodType) : max_size_in_bytes);
-}
-
-#if defined(ASIO_HAS_STD_ARRAY) || defined(GENERATING_DOCUMENTATION)
-
-/// Create a new modifiable buffer that represents the given POD array.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     data.data(),
- *     data.size() * sizeof(PodType)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_MUTABLE_BUFFER buffer(
-    std::array<PodType, N>& data) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(data.data(), data.size() * sizeof(PodType));
-}
-
-/// Create a new modifiable buffer that represents the given POD array.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     data.data(),
- *     min(data.size() * sizeof(PodType), max_size_in_bytes)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_MUTABLE_BUFFER buffer(std::array<PodType, N>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(data.data(),
-      data.size() * sizeof(PodType) < max_size_in_bytes
-      ? data.size() * sizeof(PodType) : max_size_in_bytes);
-}
-
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.data(),
- *     data.size() * sizeof(PodType)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(
-    std::array<const PodType, N>& data) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(), data.size() * sizeof(PodType));
-}
-
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.data(),
- *     min(data.size() * sizeof(PodType), max_size_in_bytes)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(std::array<const PodType, N>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(),
-      data.size() * sizeof(PodType) < max_size_in_bytes
-      ? data.size() * sizeof(PodType) : max_size_in_bytes);
-}
-
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.data(),
- *     data.size() * sizeof(PodType)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(
-    const std::array<PodType, N>& data) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(), data.size() * sizeof(PodType));
-}
-
-/// Create a new non-modifiable buffer that represents the given POD array.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.data(),
- *     min(data.size() * sizeof(PodType), max_size_in_bytes)); @endcode
- */
-template <typename PodType, std::size_t N>
-inline ASIO_CONST_BUFFER buffer(const std::array<PodType, N>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(),
-      data.size() * sizeof(PodType) < max_size_in_bytes
-      ? data.size() * sizeof(PodType) : max_size_in_bytes);
-}
-
-#endif // defined(ASIO_HAS_STD_ARRAY) || defined(GENERATING_DOCUMENTATION)
-
-/// Create a new modifiable buffer that represents the given POD vector.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     data.size() ? &data[0] : 0,
- *     data.size() * sizeof(PodType)); @endcode
- *
- * @note The buffer is invalidated by any vector operation that would also
- * invalidate iterators.
- */
-template <typename PodType, typename Allocator>
-inline ASIO_MUTABLE_BUFFER buffer(
-    std::vector<PodType, Allocator>& data) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(
-      data.size() ? &data[0] : 0, data.size() * sizeof(PodType)
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename std::vector<PodType, Allocator>::iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new modifiable buffer that represents the given POD vector.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     data.size() ? &data[0] : 0,
- *     min(data.size() * sizeof(PodType), max_size_in_bytes)); @endcode
- *
- * @note The buffer is invalidated by any vector operation that would also
- * invalidate iterators.
- */
-template <typename PodType, typename Allocator>
-inline ASIO_MUTABLE_BUFFER buffer(std::vector<PodType, Allocator>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(data.size() ? &data[0] : 0,
-      data.size() * sizeof(PodType) < max_size_in_bytes
-      ? data.size() * sizeof(PodType) : max_size_in_bytes
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename std::vector<PodType, Allocator>::iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new non-modifiable buffer that represents the given POD vector.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.size() ? &data[0] : 0,
- *     data.size() * sizeof(PodType)); @endcode
- *
- * @note The buffer is invalidated by any vector operation that would also
- * invalidate iterators.
- */
-template <typename PodType, typename Allocator>
-inline ASIO_CONST_BUFFER buffer(
-    const std::vector<PodType, Allocator>& data) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(
-      data.size() ? &data[0] : 0, data.size() * sizeof(PodType)
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename std::vector<PodType, Allocator>::const_iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new non-modifiable buffer that represents the given POD vector.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.size() ? &data[0] : 0,
- *     min(data.size() * sizeof(PodType), max_size_in_bytes)); @endcode
- *
- * @note The buffer is invalidated by any vector operation that would also
- * invalidate iterators.
- */
-template <typename PodType, typename Allocator>
-inline ASIO_CONST_BUFFER buffer(
-    const std::vector<PodType, Allocator>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.size() ? &data[0] : 0,
-      data.size() * sizeof(PodType) < max_size_in_bytes
-      ? data.size() * sizeof(PodType) : max_size_in_bytes
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename std::vector<PodType, Allocator>::const_iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new modifiable buffer that represents the given string.
-/**
- * @returns <tt>mutable_buffer(data.size() ? &data[0] : 0,
- * data.size() * sizeof(Elem))</tt>.
- *
- * @note The buffer is invalidated by any non-const operation called on the
- * given string object.
- */
-template <typename Elem, typename Traits, typename Allocator>
-inline ASIO_MUTABLE_BUFFER buffer(
-    std::basic_string<Elem, Traits, Allocator>& data) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(data.size() ? &data[0] : 0,
-      data.size() * sizeof(Elem)
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename std::basic_string<Elem, Traits, Allocator>::iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new non-modifiable buffer that represents the given string.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     data.size() ? &data[0] : 0,
- *     min(data.size() * sizeof(Elem), max_size_in_bytes)); @endcode
- *
- * @note The buffer is invalidated by any non-const operation called on the
- * given string object.
- */
-template <typename Elem, typename Traits, typename Allocator>
-inline ASIO_MUTABLE_BUFFER buffer(
-    std::basic_string<Elem, Traits, Allocator>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_MUTABLE_BUFFER(data.size() ? &data[0] : 0,
-      data.size() * sizeof(Elem) < max_size_in_bytes
-      ? data.size() * sizeof(Elem) : max_size_in_bytes
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename std::basic_string<Elem, Traits, Allocator>::iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new non-modifiable buffer that represents the given string.
-/**
- * @returns <tt>const_buffer(data.data(), data.size() * sizeof(Elem))</tt>.
- *
- * @note The buffer is invalidated by any non-const operation called on the
- * given string object.
- */
-template <typename Elem, typename Traits, typename Allocator>
-inline ASIO_CONST_BUFFER buffer(
-    const std::basic_string<Elem, Traits, Allocator>& data) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(), data.size() * sizeof(Elem)
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename std::basic_string<Elem, Traits, Allocator>::const_iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new non-modifiable buffer that represents the given string.
-/**
- * @returns A const_buffer value equivalent to:
- * @code const_buffer(
- *     data.data(),
- *     min(data.size() * sizeof(Elem), max_size_in_bytes)); @endcode
- *
- * @note The buffer is invalidated by any non-const operation called on the
- * given string object.
- */
-template <typename Elem, typename Traits, typename Allocator>
-inline ASIO_CONST_BUFFER buffer(
-    const std::basic_string<Elem, Traits, Allocator>& data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.data(),
-      data.size() * sizeof(Elem) < max_size_in_bytes
-      ? data.size() * sizeof(Elem) : max_size_in_bytes
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename std::basic_string<Elem, Traits, Allocator>::const_iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-#if defined(ASIO_HAS_STRING_VIEW) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Create a new modifiable buffer that represents the given string_view.
-/**
- * @returns <tt>mutable_buffer(data.size() ? &data[0] : 0,
- * data.size() * sizeof(Elem))</tt>.
- */
-template <typename Elem, typename Traits>
-inline ASIO_CONST_BUFFER buffer(
-    basic_string_view<Elem, Traits> data) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.size() ? &data[0] : 0,
-      data.size() * sizeof(Elem)
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename basic_string_view<Elem, Traits>::iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-/// Create a new non-modifiable buffer that represents the given string.
-/**
- * @returns A mutable_buffer value equivalent to:
- * @code mutable_buffer(
- *     data.size() ? &data[0] : 0,
- *     min(data.size() * sizeof(Elem), max_size_in_bytes)); @endcode
- */
-template <typename Elem, typename Traits>
-inline ASIO_CONST_BUFFER buffer(
-    basic_string_view<Elem, Traits> data,
-    std::size_t max_size_in_bytes) ASIO_NOEXCEPT
-{
-  return ASIO_CONST_BUFFER(data.size() ? &data[0] : 0,
-      data.size() * sizeof(Elem) < max_size_in_bytes
-      ? data.size() * sizeof(Elem) : max_size_in_bytes
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-      , detail::buffer_debug_check<
-          typename basic_string_view<Elem, Traits>::iterator
-        >(data.begin())
-#endif // ASIO_ENABLE_BUFFER_DEBUGGING
-      );
-}
-
-#endif // defined(ASIO_HAS_STRING_VIEW)
-       //  || defined(GENERATING_DOCUMENTATION)
-
-/*@}*/
-
-/// Adapt a basic_string to the DynamicBuffer requirements.
-/**
- * Requires that <tt>sizeof(Elem) == 1</tt>.
- */
-template <typename Elem, typename Traits, typename Allocator>
-class dynamic_string_buffer
-{
-public:
-  /// The type used to represent the input sequence as a list of buffers.
-  typedef ASIO_CONST_BUFFER const_buffers_type;
-
-  /// The type used to represent the output sequence as a list of buffers.
-  typedef ASIO_MUTABLE_BUFFER mutable_buffers_type;
-
-  /// Construct a dynamic buffer from a string.
-  /**
-   * @param s The string to be used as backing storage for the dynamic buffer.
-   * Any existing data in the string is treated as the dynamic buffer's input
-   * sequence. The object stores a reference to the string and the user is
-   * responsible for ensuring that the string object remains valid until the
-   * dynamic_string_buffer object is destroyed.
-   *
-   * @param maximum_size Specifies a maximum size for the buffer, in bytes.
-   */
-  explicit dynamic_string_buffer(std::basic_string<Elem, Traits, Allocator>& s,
-      std::size_t maximum_size =
-        (std::numeric_limits<std::size_t>::max)()) ASIO_NOEXCEPT
-    : string_(s),
-      size_(string_.size()),
-      max_size_(maximum_size)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move construct a dynamic buffer.
-  dynamic_string_buffer(dynamic_string_buffer&& other) ASIO_NOEXCEPT
-    : string_(other.string_),
-      size_(other.size_),
-      max_size_(other.max_size_)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Get the size of the input sequence.
-  std::size_t size() const ASIO_NOEXCEPT
-  {
-    return size_;
-  }
-
-  /// Get the maximum size of the dynamic buffer.
-  /**
-   * @returns The allowed maximum of the sum of the sizes of the input sequence
-   * and output sequence.
-   */
-  std::size_t max_size() const ASIO_NOEXCEPT
-  {
-    return max_size_;
-  }
-
-  /// Get the current capacity of the dynamic buffer.
-  /**
-   * @returns The current total capacity of the buffer, i.e. for both the input
-   * sequence and output sequence.
-   */
-  std::size_t capacity() const ASIO_NOEXCEPT
-  {
-    return string_.capacity();
-  }
-
-  /// Get a list of buffers that represents the input sequence.
-  /**
-   * @returns An object of type @c const_buffers_type that satisfies
-   * ConstBufferSequence requirements, representing the basic_string memory in
-   * input sequence.
-   *
-   * @note The returned object is invalidated by any @c dynamic_string_buffer
-   * or @c basic_string member function that modifies the input sequence or
-   * output sequence.
-   */
-  const_buffers_type data() const ASIO_NOEXCEPT
-  {
-    return const_buffers_type(asio::buffer(string_, size_));
-  }
-
-  /// Get a list of buffers that represents the output sequence, with the given
-  /// size.
-  /**
-   * Ensures that the output sequence can accommodate @c n bytes, resizing the
-   * basic_string object as necessary.
-   *
-   * @returns An object of type @c mutable_buffers_type that satisfies
-   * MutableBufferSequence requirements, representing basic_string memory
-   * at the start of the output sequence of size @c n.
-   *
-   * @throws std::length_error If <tt>size() + n > max_size()</tt>.
-   *
-   * @note The returned object is invalidated by any @c dynamic_string_buffer
-   * or @c basic_string member function that modifies the input sequence or
-   * output sequence.
-   */
-  mutable_buffers_type prepare(std::size_t n)
-  {
-    if (size () > max_size() || max_size() - size() < n)
-    {
-      std::length_error ex("dynamic_string_buffer too long");
-      asio::detail::throw_exception(ex);
-    }
-
-    string_.resize(size_ + n);
-
-    return asio::buffer(asio::buffer(string_) + size_, n);
-  }
-
-  /// Move bytes from the output sequence to the input sequence.
-  /**
-   * @param n The number of bytes to append from the start of the output
-   * sequence to the end of the input sequence. The remainder of the output
-   * sequence is discarded.
-   *
-   * Requires a preceding call <tt>prepare(x)</tt> where <tt>x >= n</tt>, and
-   * no intervening operations that modify the input or output sequence.
-   *
-   * @note If @c n is greater than the size of the output sequence, the entire
-   * output sequence is moved to the input sequence and no error is issued.
-   */
-  void commit(std::size_t n)
-  {
-    size_ += (std::min)(n, string_.size() - size_);
-    string_.resize(size_);
-  }
-
-  /// Remove characters from the input sequence.
-  /**
-   * Removes @c n characters from the beginning of the input sequence.
-   *
-   * @note If @c n is greater than the size of the input sequence, the entire
-   * input sequence is consumed and no error is issued.
-   */
-  void consume(std::size_t n)
-  {
-    std::size_t consume_length = (std::min)(n, size_);
-    string_.erase(0, consume_length);
-    size_ -= consume_length;
-  }
-
-private:
-  std::basic_string<Elem, Traits, Allocator>& string_;
-  std::size_t size_;
-  const std::size_t max_size_;
-};
-
-/// Adapt a vector to the DynamicBuffer requirements.
-/**
- * Requires that <tt>sizeof(Elem) == 1</tt>.
- */
-template <typename Elem, typename Allocator>
-class dynamic_vector_buffer
-{
-public:
-  /// The type used to represent the input sequence as a list of buffers.
-  typedef ASIO_CONST_BUFFER const_buffers_type;
-
-  /// The type used to represent the output sequence as a list of buffers.
-  typedef ASIO_MUTABLE_BUFFER mutable_buffers_type;
-
-  /// Construct a dynamic buffer from a string.
-  /**
-   * @param v The vector to be used as backing storage for the dynamic buffer.
-   * Any existing data in the vector is treated as the dynamic buffer's input
-   * sequence. The object stores a reference to the vector and the user is
-   * responsible for ensuring that the vector object remains valid until the
-   * dynamic_vector_buffer object is destroyed.
-   *
-   * @param maximum_size Specifies a maximum size for the buffer, in bytes.
-   */
-  explicit dynamic_vector_buffer(std::vector<Elem, Allocator>& v,
-      std::size_t maximum_size =
-        (std::numeric_limits<std::size_t>::max)()) ASIO_NOEXCEPT
-    : vector_(v),
-      size_(vector_.size()),
-      max_size_(maximum_size)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move construct a dynamic buffer.
-  dynamic_vector_buffer(dynamic_vector_buffer&& other) ASIO_NOEXCEPT
-    : vector_(other.vector_),
-      size_(other.size_),
-      max_size_(other.max_size_)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Get the size of the input sequence.
-  std::size_t size() const ASIO_NOEXCEPT
-  {
-    return size_;
-  }
-
-  /// Get the maximum size of the dynamic buffer.
-  /**
-   * @returns The allowed maximum of the sum of the sizes of the input sequence
-   * and output sequence.
-   */
-  std::size_t max_size() const ASIO_NOEXCEPT
-  {
-    return max_size_;
-  }
-
-  /// Get the current capacity of the dynamic buffer.
-  /**
-   * @returns The current total capacity of the buffer, i.e. for both the input
-   * sequence and output sequence.
-   */
-  std::size_t capacity() const ASIO_NOEXCEPT
-  {
-    return vector_.capacity();
-  }
-
-  /// Get a list of buffers that represents the input sequence.
-  /**
-   * @returns An object of type @c const_buffers_type that satisfies
-   * ConstBufferSequence requirements, representing the basic_string memory in
-   * input sequence.
-   *
-   * @note The returned object is invalidated by any @c dynamic_vector_buffer
-   * or @c basic_string member function that modifies the input sequence or
-   * output sequence.
-   */
-  const_buffers_type data() const ASIO_NOEXCEPT
-  {
-    return const_buffers_type(asio::buffer(vector_, size_));
-  }
-
-  /// Get a list of buffers that represents the output sequence, with the given
-  /// size.
-  /**
-   * Ensures that the output sequence can accommodate @c n bytes, resizing the
-   * basic_string object as necessary.
-   *
-   * @returns An object of type @c mutable_buffers_type that satisfies
-   * MutableBufferSequence requirements, representing basic_string memory
-   * at the start of the output sequence of size @c n.
-   *
-   * @throws std::length_error If <tt>size() + n > max_size()</tt>.
-   *
-   * @note The returned object is invalidated by any @c dynamic_vector_buffer
-   * or @c basic_string member function that modifies the input sequence or
-   * output sequence.
-   */
-  mutable_buffers_type prepare(std::size_t n)
-  {
-    if (size () > max_size() || max_size() - size() < n)
-    {
-      std::length_error ex("dynamic_vector_buffer too long");
-      asio::detail::throw_exception(ex);
-    }
-
-    vector_.resize(size_ + n);
-
-    return asio::buffer(asio::buffer(vector_) + size_, n);
-  }
-
-  /// Move bytes from the output sequence to the input sequence.
-  /**
-   * @param n The number of bytes to append from the start of the output
-   * sequence to the end of the input sequence. The remainder of the output
-   * sequence is discarded.
-   *
-   * Requires a preceding call <tt>prepare(x)</tt> where <tt>x >= n</tt>, and
-   * no intervening operations that modify the input or output sequence.
-   *
-   * @note If @c n is greater than the size of the output sequence, the entire
-   * output sequence is moved to the input sequence and no error is issued.
-   */
-  void commit(std::size_t n)
-  {
-    size_ += (std::min)(n, vector_.size() - size_);
-    vector_.resize(size_);
-  }
-
-  /// Remove characters from the input sequence.
-  /**
-   * Removes @c n characters from the beginning of the input sequence.
-   *
-   * @note If @c n is greater than the size of the input sequence, the entire
-   * input sequence is consumed and no error is issued.
-   */
-  void consume(std::size_t n)
-  {
-    std::size_t consume_length = (std::min)(n, size_);
-    vector_.erase(vector_.begin(), vector_.begin() + consume_length);
-    size_ -= consume_length;
-  }
-
-private:
-  std::vector<Elem, Allocator>& vector_;
-  std::size_t size_;
-  const std::size_t max_size_;
-};
-
-/** @defgroup dynamic_buffer asio::dynamic_buffer
- *
- * @brief The asio::dynamic_buffer function is used to create a
- * dynamically resized buffer from a @c std::basic_string or @c std::vector.
- */
-/*@{*/
-
-/// Create a new dynamic buffer that represents the given string.
-/**
- * @returns <tt>dynamic_string_buffer<Elem, Traits, Allocator>(data)</tt>.
- */
-template <typename Elem, typename Traits, typename Allocator>
-inline dynamic_string_buffer<Elem, Traits, Allocator> dynamic_buffer(
-    std::basic_string<Elem, Traits, Allocator>& data) ASIO_NOEXCEPT
-{
-  return dynamic_string_buffer<Elem, Traits, Allocator>(data);
-}
-
-/// Create a new dynamic buffer that represents the given string.
-/**
- * @returns <tt>dynamic_string_buffer<Elem, Traits, Allocator>(data,
- * max_size)</tt>.
- */
-template <typename Elem, typename Traits, typename Allocator>
-inline dynamic_string_buffer<Elem, Traits, Allocator> dynamic_buffer(
-    std::basic_string<Elem, Traits, Allocator>& data,
-    std::size_t max_size) ASIO_NOEXCEPT
-{
-  return dynamic_string_buffer<Elem, Traits, Allocator>(data, max_size);
-}
-
-/// Create a new dynamic buffer that represents the given vector.
-/**
- * @returns <tt>dynamic_vector_buffer<Elem, Allocator>(data)</tt>.
- */
-template <typename Elem, typename Allocator>
-inline dynamic_vector_buffer<Elem, Allocator> dynamic_buffer(
-    std::vector<Elem, Allocator>& data) ASIO_NOEXCEPT
-{
-  return dynamic_vector_buffer<Elem, Allocator>(data);
-}
-
-/// Create a new dynamic buffer that represents the given vector.
-/**
- * @returns <tt>dynamic_vector_buffer<Elem, Allocator>(data, max_size)</tt>.
- */
-template <typename Elem, typename Allocator>
-inline dynamic_vector_buffer<Elem, Allocator> dynamic_buffer(
-    std::vector<Elem, Allocator>& data,
-    std::size_t max_size) ASIO_NOEXCEPT
-{
-  return dynamic_vector_buffer<Elem, Allocator>(data, max_size);
-}
-
-/*@}*/
-
-/** @defgroup buffer_copy asio::buffer_copy
- *
- * @brief The asio::buffer_copy function is used to copy bytes from a
- * source buffer (or buffer sequence) to a target buffer (or buffer sequence).
- *
- * The @c buffer_copy function is available in two forms:
- *
- * @li A 2-argument form: @c buffer_copy(target, source)
- *
- * @li A 3-argument form: @c buffer_copy(target, source, max_bytes_to_copy)
- *
- * Both forms return the number of bytes actually copied. The number of bytes
- * copied is the lesser of:
- *
- * @li @c buffer_size(target)
- *
- * @li @c buffer_size(source)
- *
- * @li @c If specified, @c max_bytes_to_copy.
- *
- * This prevents buffer overflow, regardless of the buffer sizes used in the
- * copy operation.
- *
- * Note that @ref buffer_copy is implemented in terms of @c memcpy, and
- * consequently it cannot be used to copy between overlapping memory regions.
- */
-/*@{*/
-
-namespace detail {
-
-inline std::size_t buffer_copy_1(const mutable_buffer& target,
-    const const_buffer& source)
-{
-  using namespace std; // For memcpy.
-  std::size_t target_size = target.size();
-  std::size_t source_size = source.size();
-  std::size_t n = target_size < source_size ? target_size : source_size;
-  if (n > 0)
-    memcpy(target.data(), source.data(), n);
-  return n;
-}
-
-template <typename TargetIterator, typename SourceIterator>
-inline std::size_t buffer_copy(one_buffer, one_buffer,
-    TargetIterator target_begin, TargetIterator,
-    SourceIterator source_begin, SourceIterator) ASIO_NOEXCEPT
-{
-  return (buffer_copy_1)(*target_begin, *source_begin);
-}
-
-template <typename TargetIterator, typename SourceIterator>
-inline std::size_t buffer_copy(one_buffer, one_buffer,
-    TargetIterator target_begin, TargetIterator,
-    SourceIterator source_begin, SourceIterator,
-    std::size_t max_bytes_to_copy) ASIO_NOEXCEPT
-{
-  return (buffer_copy_1)(*target_begin,
-      asio::buffer(*source_begin, max_bytes_to_copy));
-}
-
-template <typename TargetIterator, typename SourceIterator>
-std::size_t buffer_copy(one_buffer, multiple_buffers,
-    TargetIterator target_begin, TargetIterator,
-    SourceIterator source_begin, SourceIterator source_end,
-    std::size_t max_bytes_to_copy
-      = (std::numeric_limits<std::size_t>::max)()) ASIO_NOEXCEPT
-{
-  std::size_t total_bytes_copied = 0;
-  SourceIterator source_iter = source_begin;
-
-  for (mutable_buffer target_buffer(
-        asio::buffer(*target_begin, max_bytes_to_copy));
-      target_buffer.size() && source_iter != source_end; ++source_iter)
-  {
-    const_buffer source_buffer(*source_iter);
-    std::size_t bytes_copied = (buffer_copy_1)(target_buffer, source_buffer);
-    total_bytes_copied += bytes_copied;
-    target_buffer += bytes_copied;
-  }
-
-  return total_bytes_copied;
-}
-
-template <typename TargetIterator, typename SourceIterator>
-std::size_t buffer_copy(multiple_buffers, one_buffer,
-    TargetIterator target_begin, TargetIterator target_end,
-    SourceIterator source_begin, SourceIterator,
-    std::size_t max_bytes_to_copy
-      = (std::numeric_limits<std::size_t>::max)()) ASIO_NOEXCEPT
-{
-  std::size_t total_bytes_copied = 0;
-  TargetIterator target_iter = target_begin;
-
-  for (const_buffer source_buffer(
-        asio::buffer(*source_begin, max_bytes_to_copy));
-      source_buffer.size() && target_iter != target_end; ++target_iter)
-  {
-    mutable_buffer target_buffer(*target_iter);
-    std::size_t bytes_copied = (buffer_copy_1)(target_buffer, source_buffer);
-    total_bytes_copied += bytes_copied;
-    source_buffer += bytes_copied;
-  }
-
-  return total_bytes_copied;
-}
-
-template <typename TargetIterator, typename SourceIterator>
-std::size_t buffer_copy(multiple_buffers, multiple_buffers,
-    TargetIterator target_begin, TargetIterator target_end,
-    SourceIterator source_begin, SourceIterator source_end) ASIO_NOEXCEPT
-{
-  std::size_t total_bytes_copied = 0;
-
-  TargetIterator target_iter = target_begin;
-  std::size_t target_buffer_offset = 0;
-
-  SourceIterator source_iter = source_begin;
-  std::size_t source_buffer_offset = 0;
-
-  while (target_iter != target_end && source_iter != source_end)
-  {
-    mutable_buffer target_buffer =
-      mutable_buffer(*target_iter) + target_buffer_offset;
-
-    const_buffer source_buffer =
-      const_buffer(*source_iter) + source_buffer_offset;
-
-    std::size_t bytes_copied = (buffer_copy_1)(target_buffer, source_buffer);
-    total_bytes_copied += bytes_copied;
-
-    if (bytes_copied == target_buffer.size())
-    {
-      ++target_iter;
-      target_buffer_offset = 0;
-    }
-    else
-      target_buffer_offset += bytes_copied;
-
-    if (bytes_copied == source_buffer.size())
-    {
-      ++source_iter;
-      source_buffer_offset = 0;
-    }
-    else
-      source_buffer_offset += bytes_copied;
-  }
-
-  return total_bytes_copied;
-}
-
-template <typename TargetIterator, typename SourceIterator>
-std::size_t buffer_copy(multiple_buffers, multiple_buffers,
-    TargetIterator target_begin, TargetIterator target_end,
-    SourceIterator source_begin, SourceIterator source_end,
-    std::size_t max_bytes_to_copy) ASIO_NOEXCEPT
-{
-  std::size_t total_bytes_copied = 0;
-
-  TargetIterator target_iter = target_begin;
-  std::size_t target_buffer_offset = 0;
-
-  SourceIterator source_iter = source_begin;
-  std::size_t source_buffer_offset = 0;
-
-  while (total_bytes_copied != max_bytes_to_copy
-      && target_iter != target_end && source_iter != source_end)
-  {
-    mutable_buffer target_buffer =
-      mutable_buffer(*target_iter) + target_buffer_offset;
-
-    const_buffer source_buffer =
-      const_buffer(*source_iter) + source_buffer_offset;
-
-    std::size_t bytes_copied = (buffer_copy_1)(
-        target_buffer, asio::buffer(source_buffer,
-          max_bytes_to_copy - total_bytes_copied));
-    total_bytes_copied += bytes_copied;
-
-    if (bytes_copied == target_buffer.size())
-    {
-      ++target_iter;
-      target_buffer_offset = 0;
-    }
-    else
-      target_buffer_offset += bytes_copied;
-
-    if (bytes_copied == source_buffer.size())
-    {
-      ++source_iter;
-      source_buffer_offset = 0;
-    }
-    else
-      source_buffer_offset += bytes_copied;
-  }
-
-  return total_bytes_copied;
-}
-
-} // namespace detail
-
-/// Copies bytes from a source buffer sequence to a target buffer sequence.
-/**
- * @param target A modifiable buffer sequence representing the memory regions to
- * which the bytes will be copied.
- *
- * @param source A non-modifiable buffer sequence representing the memory
- * regions from which the bytes will be copied.
- *
- * @returns The number of bytes copied.
- *
- * @note The number of bytes copied is the lesser of:
- *
- * @li @c buffer_size(target)
- *
- * @li @c buffer_size(source)
- *
- * This function is implemented in terms of @c memcpy, and consequently it
- * cannot be used to copy between overlapping memory regions.
- */
-template <typename MutableBufferSequence, typename ConstBufferSequence>
-inline std::size_t buffer_copy(const MutableBufferSequence& target,
-    const ConstBufferSequence& source) ASIO_NOEXCEPT
-{
-  return detail::buffer_copy(
-      detail::buffer_sequence_cardinality<MutableBufferSequence>(),
-      detail::buffer_sequence_cardinality<ConstBufferSequence>(),
-      asio::buffer_sequence_begin(target),
-      asio::buffer_sequence_end(target),
-      asio::buffer_sequence_begin(source),
-      asio::buffer_sequence_end(source));
-}
-
-/// Copies a limited number of bytes from a source buffer sequence to a target
-/// buffer sequence.
-/**
- * @param target A modifiable buffer sequence representing the memory regions to
- * which the bytes will be copied.
- *
- * @param source A non-modifiable buffer sequence representing the memory
- * regions from which the bytes will be copied.
- *
- * @param max_bytes_to_copy The maximum number of bytes to be copied.
- *
- * @returns The number of bytes copied.
- *
- * @note The number of bytes copied is the lesser of:
- *
- * @li @c buffer_size(target)
- *
- * @li @c buffer_size(source)
- *
- * @li @c max_bytes_to_copy
- *
- * This function is implemented in terms of @c memcpy, and consequently it
- * cannot be used to copy between overlapping memory regions.
- */
-template <typename MutableBufferSequence, typename ConstBufferSequence>
-inline std::size_t buffer_copy(const MutableBufferSequence& target,
-    const ConstBufferSequence& source,
-    std::size_t max_bytes_to_copy) ASIO_NOEXCEPT
-{
-  return detail::buffer_copy(
-      detail::buffer_sequence_cardinality<MutableBufferSequence>(),
-      detail::buffer_sequence_cardinality<ConstBufferSequence>(),
-      asio::buffer_sequence_begin(target),
-      asio::buffer_sequence_end(target),
-      asio::buffer_sequence_begin(source),
-      asio::buffer_sequence_end(source), max_bytes_to_copy);
-}
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_BUFFER_HPP
diff --git a/tools/sdk/include/asio/asio/buffered_read_stream.hpp b/tools/sdk/include/asio/asio/buffered_read_stream.hpp
deleted file mode 100644
index c3e7f0b57e2..00000000000
--- a/tools/sdk/include/asio/asio/buffered_read_stream.hpp
+++ /dev/null
@@ -1,257 +0,0 @@
-//
-// buffered_read_stream.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BUFFERED_READ_STREAM_HPP
-#define ASIO_BUFFERED_READ_STREAM_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/buffered_read_stream_fwd.hpp"
-#include "asio/buffer.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_resize_guard.hpp"
-#include "asio/detail/buffered_stream_storage.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Adds buffering to the read-related operations of a stream.
-/**
- * The buffered_read_stream class template can be used to add buffering to the
- * synchronous and asynchronous read operations of a stream.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * AsyncReadStream, AsyncWriteStream, Stream, SyncReadStream, SyncWriteStream.
- */
-template <typename Stream>
-class buffered_read_stream
-  : private noncopyable
-{
-public:
-  /// The type of the next layer.
-  typedef typename remove_reference<Stream>::type next_layer_type;
-
-  /// The type of the lowest layer.
-  typedef typename next_layer_type::lowest_layer_type lowest_layer_type;
-
-  /// The type of the executor associated with the object.
-  typedef typename lowest_layer_type::executor_type executor_type;
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// The default buffer size.
-  static const std::size_t default_buffer_size = implementation_defined;
-#else
-  ASIO_STATIC_CONSTANT(std::size_t, default_buffer_size = 1024);
-#endif
-
-  /// Construct, passing the specified argument to initialise the next layer.
-  template <typename Arg>
-  explicit buffered_read_stream(Arg& a)
-    : next_layer_(a),
-      storage_(default_buffer_size)
-  {
-  }
-
-  /// Construct, passing the specified argument to initialise the next layer.
-  template <typename Arg>
-  buffered_read_stream(Arg& a, std::size_t buffer_size)
-    : next_layer_(a),
-      storage_(buffer_size)
-  {
-  }
-
-  /// Get a reference to the next layer.
-  next_layer_type& next_layer()
-  {
-    return next_layer_;
-  }
-
-  /// Get a reference to the lowest layer.
-  lowest_layer_type& lowest_layer()
-  {
-    return next_layer_.lowest_layer();
-  }
-
-  /// Get a const reference to the lowest layer.
-  const lowest_layer_type& lowest_layer() const
-  {
-    return next_layer_.lowest_layer();
-  }
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return next_layer_.lowest_layer().get_executor();
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  asio::io_context& get_io_context()
-  {
-    return next_layer_.get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  asio::io_context& get_io_service()
-  {
-    return next_layer_.get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Close the stream.
-  void close()
-  {
-    next_layer_.close();
-  }
-
-  /// Close the stream.
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    next_layer_.close(ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Write the given data to the stream. Returns the number of bytes written.
-  /// Throws an exception on failure.
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    return next_layer_.write_some(buffers);
-  }
-
-  /// Write the given data to the stream. Returns the number of bytes written,
-  /// or 0 if an error occurred.
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return next_layer_.write_some(buffers, ec);
-  }
-
-  /// Start an asynchronous write. The data being written must be valid for the
-  /// lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    return next_layer_.async_write_some(buffers,
-        ASIO_MOVE_CAST(WriteHandler)(handler));
-  }
-
-  /// Fill the buffer with some data. Returns the number of bytes placed in the
-  /// buffer as a result of the operation. Throws an exception on failure.
-  std::size_t fill();
-
-  /// Fill the buffer with some data. Returns the number of bytes placed in the
-  /// buffer as a result of the operation, or 0 if an error occurred.
-  std::size_t fill(asio::error_code& ec);
-
-  /// Start an asynchronous fill.
-  template <typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_fill(ASIO_MOVE_ARG(ReadHandler) handler);
-
-  /// Read some data from the stream. Returns the number of bytes read. Throws
-  /// an exception on failure.
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers);
-
-  /// Read some data from the stream. Returns the number of bytes read or 0 if
-  /// an error occurred.
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec);
-
-  /// Start an asynchronous read. The buffer into which the data will be read
-  /// must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler);
-
-  /// Peek at the incoming data on the stream. Returns the number of bytes read.
-  /// Throws an exception on failure.
-  template <typename MutableBufferSequence>
-  std::size_t peek(const MutableBufferSequence& buffers);
-
-  /// Peek at the incoming data on the stream. Returns the number of bytes read,
-  /// or 0 if an error occurred.
-  template <typename MutableBufferSequence>
-  std::size_t peek(const MutableBufferSequence& buffers,
-      asio::error_code& ec);
-
-  /// Determine the amount of data that may be read without blocking.
-  std::size_t in_avail()
-  {
-    return storage_.size();
-  }
-
-  /// Determine the amount of data that may be read without blocking.
-  std::size_t in_avail(asio::error_code& ec)
-  {
-    ec = asio::error_code();
-    return storage_.size();
-  }
-
-private:
-  /// Copy data out of the internal buffer to the specified target buffer.
-  /// Returns the number of bytes copied.
-  template <typename MutableBufferSequence>
-  std::size_t copy(const MutableBufferSequence& buffers)
-  {
-    std::size_t bytes_copied = asio::buffer_copy(
-        buffers, storage_.data(), storage_.size());
-    storage_.consume(bytes_copied);
-    return bytes_copied;
-  }
-
-  /// Copy data from the internal buffer to the specified target buffer, without
-  /// removing the data from the internal buffer. Returns the number of bytes
-  /// copied.
-  template <typename MutableBufferSequence>
-  std::size_t peek_copy(const MutableBufferSequence& buffers)
-  {
-    return asio::buffer_copy(buffers, storage_.data(), storage_.size());
-  }
-
-  /// The next layer.
-  Stream next_layer_;
-
-  // The data in the buffer.
-  detail::buffered_stream_storage storage_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/buffered_read_stream.hpp"
-
-#endif // ASIO_BUFFERED_READ_STREAM_HPP
diff --git a/tools/sdk/include/asio/asio/buffered_read_stream_fwd.hpp b/tools/sdk/include/asio/asio/buffered_read_stream_fwd.hpp
deleted file mode 100644
index 334b88a5c0a..00000000000
--- a/tools/sdk/include/asio/asio/buffered_read_stream_fwd.hpp
+++ /dev/null
@@ -1,25 +0,0 @@
-//
-// buffered_read_stream_fwd.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BUFFERED_READ_STREAM_FWD_HPP
-#define ASIO_BUFFERED_READ_STREAM_FWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-namespace asio {
-
-template <typename Stream>
-class buffered_read_stream;
-
-} // namespace asio
-
-#endif // ASIO_BUFFERED_READ_STREAM_FWD_HPP
diff --git a/tools/sdk/include/asio/asio/buffered_stream.hpp b/tools/sdk/include/asio/asio/buffered_stream.hpp
deleted file mode 100644
index 8014fa4dd94..00000000000
--- a/tools/sdk/include/asio/asio/buffered_stream.hpp
+++ /dev/null
@@ -1,278 +0,0 @@
-//
-// buffered_stream.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BUFFERED_STREAM_HPP
-#define ASIO_BUFFERED_STREAM_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/buffered_read_stream.hpp"
-#include "asio/buffered_write_stream.hpp"
-#include "asio/buffered_stream_fwd.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Adds buffering to the read- and write-related operations of a stream.
-/**
- * The buffered_stream class template can be used to add buffering to the
- * synchronous and asynchronous read and write operations of a stream.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * AsyncReadStream, AsyncWriteStream, Stream, SyncReadStream, SyncWriteStream.
- */
-template <typename Stream>
-class buffered_stream
-  : private noncopyable
-{
-public:
-  /// The type of the next layer.
-  typedef typename remove_reference<Stream>::type next_layer_type;
-
-  /// The type of the lowest layer.
-  typedef typename next_layer_type::lowest_layer_type lowest_layer_type;
-
-  /// The type of the executor associated with the object.
-  typedef typename lowest_layer_type::executor_type executor_type;
-
-  /// Construct, passing the specified argument to initialise the next layer.
-  template <typename Arg>
-  explicit buffered_stream(Arg& a)
-    : inner_stream_impl_(a),
-      stream_impl_(inner_stream_impl_)
-  {
-  }
-
-  /// Construct, passing the specified argument to initialise the next layer.
-  template <typename Arg>
-  explicit buffered_stream(Arg& a, std::size_t read_buffer_size,
-      std::size_t write_buffer_size)
-    : inner_stream_impl_(a, write_buffer_size),
-      stream_impl_(inner_stream_impl_, read_buffer_size)
-  {
-  }
-
-  /// Get a reference to the next layer.
-  next_layer_type& next_layer()
-  {
-    return stream_impl_.next_layer().next_layer();
-  }
-
-  /// Get a reference to the lowest layer.
-  lowest_layer_type& lowest_layer()
-  {
-    return stream_impl_.lowest_layer();
-  }
-
-  /// Get a const reference to the lowest layer.
-  const lowest_layer_type& lowest_layer() const
-  {
-    return stream_impl_.lowest_layer();
-  }
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return stream_impl_.lowest_layer().get_executor();
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  asio::io_context& get_io_context()
-  {
-    return stream_impl_.get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  asio::io_context& get_io_service()
-  {
-    return stream_impl_.get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Close the stream.
-  void close()
-  {
-    stream_impl_.close();
-  }
-
-  /// Close the stream.
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    stream_impl_.close(ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Flush all data from the buffer to the next layer. Returns the number of
-  /// bytes written to the next layer on the last write operation. Throws an
-  /// exception on failure.
-  std::size_t flush()
-  {
-    return stream_impl_.next_layer().flush();
-  }
-
-  /// Flush all data from the buffer to the next layer. Returns the number of
-  /// bytes written to the next layer on the last write operation, or 0 if an
-  /// error occurred.
-  std::size_t flush(asio::error_code& ec)
-  {
-    return stream_impl_.next_layer().flush(ec);
-  }
-
-  /// Start an asynchronous flush.
-  template <typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_flush(ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    return stream_impl_.next_layer().async_flush(
-        ASIO_MOVE_CAST(WriteHandler)(handler));
-  }
-
-  /// Write the given data to the stream. Returns the number of bytes written.
-  /// Throws an exception on failure.
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    return stream_impl_.write_some(buffers);
-  }
-
-  /// Write the given data to the stream. Returns the number of bytes written,
-  /// or 0 if an error occurred.
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return stream_impl_.write_some(buffers, ec);
-  }
-
-  /// Start an asynchronous write. The data being written must be valid for the
-  /// lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    return stream_impl_.async_write_some(buffers,
-        ASIO_MOVE_CAST(WriteHandler)(handler));
-  }
-
-  /// Fill the buffer with some data. Returns the number of bytes placed in the
-  /// buffer as a result of the operation. Throws an exception on failure.
-  std::size_t fill()
-  {
-    return stream_impl_.fill();
-  }
-
-  /// Fill the buffer with some data. Returns the number of bytes placed in the
-  /// buffer as a result of the operation, or 0 if an error occurred.
-  std::size_t fill(asio::error_code& ec)
-  {
-    return stream_impl_.fill(ec);
-  }
-
-  /// Start an asynchronous fill.
-  template <typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_fill(ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    return stream_impl_.async_fill(ASIO_MOVE_CAST(ReadHandler)(handler));
-  }
-
-  /// Read some data from the stream. Returns the number of bytes read. Throws
-  /// an exception on failure.
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    return stream_impl_.read_some(buffers);
-  }
-
-  /// Read some data from the stream. Returns the number of bytes read or 0 if
-  /// an error occurred.
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return stream_impl_.read_some(buffers, ec);
-  }
-
-  /// Start an asynchronous read. The buffer into which the data will be read
-  /// must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    return stream_impl_.async_read_some(buffers,
-        ASIO_MOVE_CAST(ReadHandler)(handler));
-  }
-
-  /// Peek at the incoming data on the stream. Returns the number of bytes read.
-  /// Throws an exception on failure.
-  template <typename MutableBufferSequence>
-  std::size_t peek(const MutableBufferSequence& buffers)
-  {
-    return stream_impl_.peek(buffers);
-  }
-
-  /// Peek at the incoming data on the stream. Returns the number of bytes read,
-  /// or 0 if an error occurred.
-  template <typename MutableBufferSequence>
-  std::size_t peek(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return stream_impl_.peek(buffers, ec);
-  }
-
-  /// Determine the amount of data that may be read without blocking.
-  std::size_t in_avail()
-  {
-    return stream_impl_.in_avail();
-  }
-
-  /// Determine the amount of data that may be read without blocking.
-  std::size_t in_avail(asio::error_code& ec)
-  {
-    return stream_impl_.in_avail(ec);
-  }
-
-private:
-  // The buffered write stream.
-  typedef buffered_write_stream<Stream> write_stream_type;
-  write_stream_type inner_stream_impl_;
-
-  // The buffered read stream.
-  typedef buffered_read_stream<write_stream_type&> read_stream_type;
-  read_stream_type stream_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_BUFFERED_STREAM_HPP
diff --git a/tools/sdk/include/asio/asio/buffered_stream_fwd.hpp b/tools/sdk/include/asio/asio/buffered_stream_fwd.hpp
deleted file mode 100644
index 3492979d2b1..00000000000
--- a/tools/sdk/include/asio/asio/buffered_stream_fwd.hpp
+++ /dev/null
@@ -1,25 +0,0 @@
-//
-// buffered_stream_fwd.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BUFFERED_STREAM_FWD_HPP
-#define ASIO_BUFFERED_STREAM_FWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-namespace asio {
-
-template <typename Stream>
-class buffered_stream;
-
-} // namespace asio
-
-#endif // ASIO_BUFFERED_STREAM_FWD_HPP
diff --git a/tools/sdk/include/asio/asio/buffered_write_stream.hpp b/tools/sdk/include/asio/asio/buffered_write_stream.hpp
deleted file mode 100644
index aac33d38f47..00000000000
--- a/tools/sdk/include/asio/asio/buffered_write_stream.hpp
+++ /dev/null
@@ -1,249 +0,0 @@
-//
-// buffered_write_stream.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BUFFERED_WRITE_STREAM_HPP
-#define ASIO_BUFFERED_WRITE_STREAM_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/buffered_write_stream_fwd.hpp"
-#include "asio/buffer.hpp"
-#include "asio/completion_condition.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffered_stream_storage.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/write.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Adds buffering to the write-related operations of a stream.
-/**
- * The buffered_write_stream class template can be used to add buffering to the
- * synchronous and asynchronous write operations of a stream.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * AsyncReadStream, AsyncWriteStream, Stream, SyncReadStream, SyncWriteStream.
- */
-template <typename Stream>
-class buffered_write_stream
-  : private noncopyable
-{
-public:
-  /// The type of the next layer.
-  typedef typename remove_reference<Stream>::type next_layer_type;
-
-  /// The type of the lowest layer.
-  typedef typename next_layer_type::lowest_layer_type lowest_layer_type;
-
-  /// The type of the executor associated with the object.
-  typedef typename lowest_layer_type::executor_type executor_type;
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// The default buffer size.
-  static const std::size_t default_buffer_size = implementation_defined;
-#else
-  ASIO_STATIC_CONSTANT(std::size_t, default_buffer_size = 1024);
-#endif
-
-  /// Construct, passing the specified argument to initialise the next layer.
-  template <typename Arg>
-  explicit buffered_write_stream(Arg& a)
-    : next_layer_(a),
-      storage_(default_buffer_size)
-  {
-  }
-
-  /// Construct, passing the specified argument to initialise the next layer.
-  template <typename Arg>
-  buffered_write_stream(Arg& a, std::size_t buffer_size)
-    : next_layer_(a),
-      storage_(buffer_size)
-  {
-  }
-
-  /// Get a reference to the next layer.
-  next_layer_type& next_layer()
-  {
-    return next_layer_;
-  }
-
-  /// Get a reference to the lowest layer.
-  lowest_layer_type& lowest_layer()
-  {
-    return next_layer_.lowest_layer();
-  }
-
-  /// Get a const reference to the lowest layer.
-  const lowest_layer_type& lowest_layer() const
-  {
-    return next_layer_.lowest_layer();
-  }
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return next_layer_.lowest_layer().get_executor();
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  asio::io_context& get_io_context()
-  {
-    return next_layer_.get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  asio::io_context& get_io_service()
-  {
-    return next_layer_.get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Close the stream.
-  void close()
-  {
-    next_layer_.close();
-  }
-
-  /// Close the stream.
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    next_layer_.close(ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Flush all data from the buffer to the next layer. Returns the number of
-  /// bytes written to the next layer on the last write operation. Throws an
-  /// exception on failure.
-  std::size_t flush();
-
-  /// Flush all data from the buffer to the next layer. Returns the number of
-  /// bytes written to the next layer on the last write operation, or 0 if an
-  /// error occurred.
-  std::size_t flush(asio::error_code& ec);
-
-  /// Start an asynchronous flush.
-  template <typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_flush(ASIO_MOVE_ARG(WriteHandler) handler);
-
-  /// Write the given data to the stream. Returns the number of bytes written.
-  /// Throws an exception on failure.
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers);
-
-  /// Write the given data to the stream. Returns the number of bytes written,
-  /// or 0 if an error occurred and the error handler did not throw.
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec);
-
-  /// Start an asynchronous write. The data being written must be valid for the
-  /// lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler);
-
-  /// Read some data from the stream. Returns the number of bytes read. Throws
-  /// an exception on failure.
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    return next_layer_.read_some(buffers);
-  }
-
-  /// Read some data from the stream. Returns the number of bytes read or 0 if
-  /// an error occurred.
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return next_layer_.read_some(buffers, ec);
-  }
-
-  /// Start an asynchronous read. The buffer into which the data will be read
-  /// must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    return next_layer_.async_read_some(buffers,
-        ASIO_MOVE_CAST(ReadHandler)(handler));
-  }
-
-  /// Peek at the incoming data on the stream. Returns the number of bytes read.
-  /// Throws an exception on failure.
-  template <typename MutableBufferSequence>
-  std::size_t peek(const MutableBufferSequence& buffers)
-  {
-    return next_layer_.peek(buffers);
-  }
-
-  /// Peek at the incoming data on the stream. Returns the number of bytes read,
-  /// or 0 if an error occurred.
-  template <typename MutableBufferSequence>
-  std::size_t peek(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return next_layer_.peek(buffers, ec);
-  }
-
-  /// Determine the amount of data that may be read without blocking.
-  std::size_t in_avail()
-  {
-    return next_layer_.in_avail();
-  }
-
-  /// Determine the amount of data that may be read without blocking.
-  std::size_t in_avail(asio::error_code& ec)
-  {
-    return next_layer_.in_avail(ec);
-  }
-
-private:
-  /// Copy data into the internal buffer from the specified source buffer.
-  /// Returns the number of bytes copied.
-  template <typename ConstBufferSequence>
-  std::size_t copy(const ConstBufferSequence& buffers);
-
-  /// The next layer.
-  Stream next_layer_;
-
-  // The data in the buffer.
-  detail::buffered_stream_storage storage_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/buffered_write_stream.hpp"
-
-#endif // ASIO_BUFFERED_WRITE_STREAM_HPP
diff --git a/tools/sdk/include/asio/asio/buffered_write_stream_fwd.hpp b/tools/sdk/include/asio/asio/buffered_write_stream_fwd.hpp
deleted file mode 100644
index 6ef54ba0d6c..00000000000
--- a/tools/sdk/include/asio/asio/buffered_write_stream_fwd.hpp
+++ /dev/null
@@ -1,25 +0,0 @@
-//
-// buffered_write_stream_fwd.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BUFFERED_WRITE_STREAM_FWD_HPP
-#define ASIO_BUFFERED_WRITE_STREAM_FWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-namespace asio {
-
-template <typename Stream>
-class buffered_write_stream;
-
-} // namespace asio
-
-#endif // ASIO_BUFFERED_WRITE_STREAM_FWD_HPP
diff --git a/tools/sdk/include/asio/asio/buffers_iterator.hpp b/tools/sdk/include/asio/asio/buffers_iterator.hpp
deleted file mode 100644
index f5c9d4c3548..00000000000
--- a/tools/sdk/include/asio/asio/buffers_iterator.hpp
+++ /dev/null
@@ -1,521 +0,0 @@
-//
-// buffers_iterator.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_BUFFERS_ITERATOR_HPP
-#define ASIO_BUFFERS_ITERATOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <iterator>
-#include "asio/buffer.hpp"
-#include "asio/detail/assert.hpp"
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail
-{
-  template <bool IsMutable>
-  struct buffers_iterator_types_helper;
-
-  template <>
-  struct buffers_iterator_types_helper<false>
-  {
-    typedef const_buffer buffer_type;
-    template <typename ByteType>
-    struct byte_type
-    {
-      typedef typename add_const<ByteType>::type type;
-    };
-  };
-
-  template <>
-  struct buffers_iterator_types_helper<true>
-  {
-    typedef mutable_buffer buffer_type;
-    template <typename ByteType>
-    struct byte_type
-    {
-      typedef ByteType type;
-    };
-  };
-
-  template <typename BufferSequence, typename ByteType>
-  struct buffers_iterator_types
-  {
-    enum
-    {
-      is_mutable = is_convertible<
-          typename BufferSequence::value_type,
-          mutable_buffer>::value
-    };
-    typedef buffers_iterator_types_helper<is_mutable> helper;
-    typedef typename helper::buffer_type buffer_type;
-    typedef typename helper::template byte_type<ByteType>::type byte_type;
-    typedef typename BufferSequence::const_iterator const_iterator;
-  };
-
-  template <typename ByteType>
-  struct buffers_iterator_types<mutable_buffer, ByteType>
-  {
-    typedef mutable_buffer buffer_type;
-    typedef ByteType byte_type;
-    typedef const mutable_buffer* const_iterator;
-  };
-
-  template <typename ByteType>
-  struct buffers_iterator_types<const_buffer, ByteType>
-  {
-    typedef const_buffer buffer_type;
-    typedef typename add_const<ByteType>::type byte_type;
-    typedef const const_buffer* const_iterator;
-  };
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-  template <typename ByteType>
-  struct buffers_iterator_types<mutable_buffers_1, ByteType>
-  {
-    typedef mutable_buffer buffer_type;
-    typedef ByteType byte_type;
-    typedef const mutable_buffer* const_iterator;
-  };
-
-  template <typename ByteType>
-  struct buffers_iterator_types<const_buffers_1, ByteType>
-  {
-    typedef const_buffer buffer_type;
-    typedef typename add_const<ByteType>::type byte_type;
-    typedef const const_buffer* const_iterator;
-  };
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-}
-
-/// A random access iterator over the bytes in a buffer sequence.
-template <typename BufferSequence, typename ByteType = char>
-class buffers_iterator
-{
-private:
-  typedef typename detail::buffers_iterator_types<
-      BufferSequence, ByteType>::buffer_type buffer_type;
-
-  typedef typename detail::buffers_iterator_types<BufferSequence,
-          ByteType>::const_iterator buffer_sequence_iterator_type;
-
-public:
-  /// The type used for the distance between two iterators.
-  typedef std::ptrdiff_t difference_type;
-
-  /// The type of the value pointed to by the iterator.
-  typedef ByteType value_type;
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// The type of the result of applying operator->() to the iterator.
-  /**
-   * If the buffer sequence stores buffer objects that are convertible to
-   * mutable_buffer, this is a pointer to a non-const ByteType. Otherwise, a
-   * pointer to a const ByteType.
-   */
-  typedef const_or_non_const_ByteType* pointer;
-#else // defined(GENERATING_DOCUMENTATION)
-  typedef typename detail::buffers_iterator_types<
-      BufferSequence, ByteType>::byte_type* pointer;
-#endif // defined(GENERATING_DOCUMENTATION)
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// The type of the result of applying operator*() to the iterator.
-  /**
-   * If the buffer sequence stores buffer objects that are convertible to
-   * mutable_buffer, this is a reference to a non-const ByteType. Otherwise, a
-   * reference to a const ByteType.
-   */
-  typedef const_or_non_const_ByteType& reference;
-#else // defined(GENERATING_DOCUMENTATION)
-  typedef typename detail::buffers_iterator_types<
-      BufferSequence, ByteType>::byte_type& reference;
-#endif // defined(GENERATING_DOCUMENTATION)
-
-  /// The iterator category.
-  typedef std::random_access_iterator_tag iterator_category;
-
-  /// Default constructor. Creates an iterator in an undefined state.
-  buffers_iterator()
-    : current_buffer_(),
-      current_buffer_position_(0),
-      begin_(),
-      current_(),
-      end_(),
-      position_(0)
-  {
-  }
-
-  /// Construct an iterator representing the beginning of the buffers' data.
-  static buffers_iterator begin(const BufferSequence& buffers)
-#if defined(__GNUC__) && (__GNUC__ == 4) && (__GNUC_MINOR__ == 3)
-    __attribute__ ((__noinline__))
-#endif // defined(__GNUC__) && (__GNUC__ == 4) && (__GNUC_MINOR__ == 3)
-  {
-    buffers_iterator new_iter;
-    new_iter.begin_ = asio::buffer_sequence_begin(buffers);
-    new_iter.current_ = asio::buffer_sequence_begin(buffers);
-    new_iter.end_ = asio::buffer_sequence_end(buffers);
-    while (new_iter.current_ != new_iter.end_)
-    {
-      new_iter.current_buffer_ = *new_iter.current_;
-      if (new_iter.current_buffer_.size() > 0)
-        break;
-      ++new_iter.current_;
-    }
-    return new_iter;
-  }
-
-  /// Construct an iterator representing the end of the buffers' data.
-  static buffers_iterator end(const BufferSequence& buffers)
-#if defined(__GNUC__) && (__GNUC__ == 4) && (__GNUC_MINOR__ == 3)
-    __attribute__ ((__noinline__))
-#endif // defined(__GNUC__) && (__GNUC__ == 4) && (__GNUC_MINOR__ == 3)
-  {
-    buffers_iterator new_iter;
-    new_iter.begin_ = asio::buffer_sequence_begin(buffers);
-    new_iter.current_ = asio::buffer_sequence_begin(buffers);
-    new_iter.end_ = asio::buffer_sequence_end(buffers);
-    while (new_iter.current_ != new_iter.end_)
-    {
-      buffer_type buffer = *new_iter.current_;
-      new_iter.position_ += buffer.size();
-      ++new_iter.current_;
-    }
-    return new_iter;
-  }
-
-  /// Dereference an iterator.
-  reference operator*() const
-  {
-    return dereference();
-  }
-
-  /// Dereference an iterator.
-  pointer operator->() const
-  {
-    return &dereference();
-  }
-
-  /// Access an individual element.
-  reference operator[](std::ptrdiff_t difference) const
-  {
-    buffers_iterator tmp(*this);
-    tmp.advance(difference);
-    return *tmp;
-  }
-
-  /// Increment operator (prefix).
-  buffers_iterator& operator++()
-  {
-    increment();
-    return *this;
-  }
-
-  /// Increment operator (postfix).
-  buffers_iterator operator++(int)
-  {
-    buffers_iterator tmp(*this);
-    ++*this;
-    return tmp;
-  }
-
-  /// Decrement operator (prefix).
-  buffers_iterator& operator--()
-  {
-    decrement();
-    return *this;
-  }
-
-  /// Decrement operator (postfix).
-  buffers_iterator operator--(int)
-  {
-    buffers_iterator tmp(*this);
-    --*this;
-    return tmp;
-  }
-
-  /// Addition operator.
-  buffers_iterator& operator+=(std::ptrdiff_t difference)
-  {
-    advance(difference);
-    return *this;
-  }
-
-  /// Subtraction operator.
-  buffers_iterator& operator-=(std::ptrdiff_t difference)
-  {
-    advance(-difference);
-    return *this;
-  }
-
-  /// Addition operator.
-  friend buffers_iterator operator+(const buffers_iterator& iter,
-      std::ptrdiff_t difference)
-  {
-    buffers_iterator tmp(iter);
-    tmp.advance(difference);
-    return tmp;
-  }
-
-  /// Addition operator.
-  friend buffers_iterator operator+(std::ptrdiff_t difference,
-      const buffers_iterator& iter)
-  {
-    buffers_iterator tmp(iter);
-    tmp.advance(difference);
-    return tmp;
-  }
-
-  /// Subtraction operator.
-  friend buffers_iterator operator-(const buffers_iterator& iter,
-      std::ptrdiff_t difference)
-  {
-    buffers_iterator tmp(iter);
-    tmp.advance(-difference);
-    return tmp;
-  }
-
-  /// Subtraction operator.
-  friend std::ptrdiff_t operator-(const buffers_iterator& a,
-      const buffers_iterator& b)
-  {
-    return b.distance_to(a);
-  }
-
-  /// Test two iterators for equality.
-  friend bool operator==(const buffers_iterator& a, const buffers_iterator& b)
-  {
-    return a.equal(b);
-  }
-
-  /// Test two iterators for inequality.
-  friend bool operator!=(const buffers_iterator& a, const buffers_iterator& b)
-  {
-    return !a.equal(b);
-  }
-
-  /// Compare two iterators.
-  friend bool operator<(const buffers_iterator& a, const buffers_iterator& b)
-  {
-    return a.distance_to(b) > 0;
-  }
-
-  /// Compare two iterators.
-  friend bool operator<=(const buffers_iterator& a, const buffers_iterator& b)
-  {
-    return !(b < a);
-  }
-
-  /// Compare two iterators.
-  friend bool operator>(const buffers_iterator& a, const buffers_iterator& b)
-  {
-    return b < a;
-  }
-
-  /// Compare two iterators.
-  friend bool operator>=(const buffers_iterator& a, const buffers_iterator& b)
-  {
-    return !(a < b);
-  }
-
-private:
-  // Dereference the iterator.
-  reference dereference() const
-  {
-    return static_cast<pointer>(
-        current_buffer_.data())[current_buffer_position_];
-  }
-
-  // Compare two iterators for equality.
-  bool equal(const buffers_iterator& other) const
-  {
-    return position_ == other.position_;
-  }
-
-  // Increment the iterator.
-  void increment()
-  {
-    ASIO_ASSERT(current_ != end_ && "iterator out of bounds");
-    ++position_;
-
-    // Check if the increment can be satisfied by the current buffer.
-    ++current_buffer_position_;
-    if (current_buffer_position_ != current_buffer_.size())
-      return;
-
-    // Find the next non-empty buffer.
-    ++current_;
-    current_buffer_position_ = 0;
-    while (current_ != end_)
-    {
-      current_buffer_ = *current_;
-      if (current_buffer_.size() > 0)
-        return;
-      ++current_;
-    }
-  }
-
-  // Decrement the iterator.
-  void decrement()
-  {
-    ASIO_ASSERT(position_ > 0 && "iterator out of bounds");
-    --position_;
-
-    // Check if the decrement can be satisfied by the current buffer.
-    if (current_buffer_position_ != 0)
-    {
-      --current_buffer_position_;
-      return;
-    }
-
-    // Find the previous non-empty buffer.
-    buffer_sequence_iterator_type iter = current_;
-    while (iter != begin_)
-    {
-      --iter;
-      buffer_type buffer = *iter;
-      std::size_t buffer_size = buffer.size();
-      if (buffer_size > 0)
-      {
-        current_ = iter;
-        current_buffer_ = buffer;
-        current_buffer_position_ = buffer_size - 1;
-        return;
-      }
-    }
-  }
-
-  // Advance the iterator by the specified distance.
-  void advance(std::ptrdiff_t n)
-  {
-    if (n > 0)
-    {
-      ASIO_ASSERT(current_ != end_ && "iterator out of bounds");
-      for (;;)
-      {
-        std::ptrdiff_t current_buffer_balance
-          = current_buffer_.size() - current_buffer_position_;
-
-        // Check if the advance can be satisfied by the current buffer.
-        if (current_buffer_balance > n)
-        {
-          position_ += n;
-          current_buffer_position_ += n;
-          return;
-        }
-
-        // Update position.
-        n -= current_buffer_balance;
-        position_ += current_buffer_balance;
-
-        // Move to next buffer. If it is empty then it will be skipped on the
-        // next iteration of this loop.
-        if (++current_ == end_)
-        {
-          ASIO_ASSERT(n == 0 && "iterator out of bounds");
-          current_buffer_ = buffer_type();
-          current_buffer_position_ = 0;
-          return;
-        }
-        current_buffer_ = *current_;
-        current_buffer_position_ = 0;
-      }
-    }
-    else if (n < 0)
-    {
-      std::size_t abs_n = -n;
-      ASIO_ASSERT(position_ >= abs_n && "iterator out of bounds");
-      for (;;)
-      {
-        // Check if the advance can be satisfied by the current buffer.
-        if (current_buffer_position_ >= abs_n)
-        {
-          position_ -= abs_n;
-          current_buffer_position_ -= abs_n;
-          return;
-        }
-
-        // Update position.
-        abs_n -= current_buffer_position_;
-        position_ -= current_buffer_position_;
-
-        // Check if we've reached the beginning of the buffers.
-        if (current_ == begin_)
-        {
-          ASIO_ASSERT(abs_n == 0 && "iterator out of bounds");
-          current_buffer_position_ = 0;
-          return;
-        }
-
-        // Find the previous non-empty buffer.
-        buffer_sequence_iterator_type iter = current_;
-        while (iter != begin_)
-        {
-          --iter;
-          buffer_type buffer = *iter;
-          std::size_t buffer_size = buffer.size();
-          if (buffer_size > 0)
-          {
-            current_ = iter;
-            current_buffer_ = buffer;
-            current_buffer_position_ = buffer_size;
-            break;
-          }
-        }
-      }
-    }
-  }
-
-  // Determine the distance between two iterators.
-  std::ptrdiff_t distance_to(const buffers_iterator& other) const
-  {
-    return other.position_ - position_;
-  }
-
-  buffer_type current_buffer_;
-  std::size_t current_buffer_position_;
-  buffer_sequence_iterator_type begin_;
-  buffer_sequence_iterator_type current_;
-  buffer_sequence_iterator_type end_;
-  std::size_t position_;
-};
-
-/// Construct an iterator representing the beginning of the buffers' data.
-template <typename BufferSequence>
-inline buffers_iterator<BufferSequence> buffers_begin(
-    const BufferSequence& buffers)
-{
-  return buffers_iterator<BufferSequence>::begin(buffers);
-}
-
-/// Construct an iterator representing the end of the buffers' data.
-template <typename BufferSequence>
-inline buffers_iterator<BufferSequence> buffers_end(
-    const BufferSequence& buffers)
-{
-  return buffers_iterator<BufferSequence>::end(buffers);
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_BUFFERS_ITERATOR_HPP
diff --git a/tools/sdk/include/asio/asio/completion_condition.hpp b/tools/sdk/include/asio/asio/completion_condition.hpp
deleted file mode 100644
index 563f417d1a5..00000000000
--- a/tools/sdk/include/asio/asio/completion_condition.hpp
+++ /dev/null
@@ -1,218 +0,0 @@
-//
-// completion_condition.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_COMPLETION_CONDITION_HPP
-#define ASIO_COMPLETION_CONDITION_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail {
-
-// The default maximum number of bytes to transfer in a single operation.
-enum default_max_transfer_size_t { default_max_transfer_size = 65536 };
-
-// Adapt result of old-style completion conditions (which had a bool result
-// where true indicated that the operation was complete).
-inline std::size_t adapt_completion_condition_result(bool result)
-{
-  return result ? 0 : default_max_transfer_size;
-}
-
-// Adapt result of current completion conditions (which have a size_t result
-// where 0 means the operation is complete, and otherwise the result is the
-// maximum number of bytes to transfer on the next underlying operation).
-inline std::size_t adapt_completion_condition_result(std::size_t result)
-{
-  return result;
-}
-
-class transfer_all_t
-{
-public:
-  typedef std::size_t result_type;
-
-  template <typename Error>
-  std::size_t operator()(const Error& err, std::size_t)
-  {
-    return !!err ? 0 : default_max_transfer_size;
-  }
-};
-
-class transfer_at_least_t
-{
-public:
-  typedef std::size_t result_type;
-
-  explicit transfer_at_least_t(std::size_t minimum)
-    : minimum_(minimum)
-  {
-  }
-
-  template <typename Error>
-  std::size_t operator()(const Error& err, std::size_t bytes_transferred)
-  {
-    return (!!err || bytes_transferred >= minimum_)
-      ? 0 : default_max_transfer_size;
-  }
-
-private:
-  std::size_t minimum_;
-};
-
-class transfer_exactly_t
-{
-public:
-  typedef std::size_t result_type;
-
-  explicit transfer_exactly_t(std::size_t size)
-    : size_(size)
-  {
-  }
-
-  template <typename Error>
-  std::size_t operator()(const Error& err, std::size_t bytes_transferred)
-  {
-    return (!!err || bytes_transferred >= size_) ? 0 :
-      (size_ - bytes_transferred < default_max_transfer_size
-        ? size_ - bytes_transferred : std::size_t(default_max_transfer_size));
-  }
-
-private:
-  std::size_t size_;
-};
-
-} // namespace detail
-
-/**
- * @defgroup completion_condition Completion Condition Function Objects
- *
- * Function objects used for determining when a read or write operation should
- * complete.
- */
-/*@{*/
-
-/// Return a completion condition function object that indicates that a read or
-/// write operation should continue until all of the data has been transferred,
-/// or until an error occurs.
-/**
- * This function is used to create an object, of unspecified type, that meets
- * CompletionCondition requirements.
- *
- * @par Example
- * Reading until a buffer is full:
- * @code
- * boost::array<char, 128> buf;
- * asio::error_code ec;
- * std::size_t n = asio::read(
- *     sock, asio::buffer(buf),
- *     asio::transfer_all(), ec);
- * if (ec)
- * {
- *   // An error occurred.
- * }
- * else
- * {
- *   // n == 128
- * }
- * @endcode
- */
-#if defined(GENERATING_DOCUMENTATION)
-unspecified transfer_all();
-#else
-inline detail::transfer_all_t transfer_all()
-{
-  return detail::transfer_all_t();
-}
-#endif
-
-/// Return a completion condition function object that indicates that a read or
-/// write operation should continue until a minimum number of bytes has been
-/// transferred, or until an error occurs.
-/**
- * This function is used to create an object, of unspecified type, that meets
- * CompletionCondition requirements.
- *
- * @par Example
- * Reading until a buffer is full or contains at least 64 bytes:
- * @code
- * boost::array<char, 128> buf;
- * asio::error_code ec;
- * std::size_t n = asio::read(
- *     sock, asio::buffer(buf),
- *     asio::transfer_at_least(64), ec);
- * if (ec)
- * {
- *   // An error occurred.
- * }
- * else
- * {
- *   // n >= 64 && n <= 128
- * }
- * @endcode
- */
-#if defined(GENERATING_DOCUMENTATION)
-unspecified transfer_at_least(std::size_t minimum);
-#else
-inline detail::transfer_at_least_t transfer_at_least(std::size_t minimum)
-{
-  return detail::transfer_at_least_t(minimum);
-}
-#endif
-
-/// Return a completion condition function object that indicates that a read or
-/// write operation should continue until an exact number of bytes has been
-/// transferred, or until an error occurs.
-/**
- * This function is used to create an object, of unspecified type, that meets
- * CompletionCondition requirements.
- *
- * @par Example
- * Reading until a buffer is full or contains exactly 64 bytes:
- * @code
- * boost::array<char, 128> buf;
- * asio::error_code ec;
- * std::size_t n = asio::read(
- *     sock, asio::buffer(buf),
- *     asio::transfer_exactly(64), ec);
- * if (ec)
- * {
- *   // An error occurred.
- * }
- * else
- * {
- *   // n == 64
- * }
- * @endcode
- */
-#if defined(GENERATING_DOCUMENTATION)
-unspecified transfer_exactly(std::size_t size);
-#else
-inline detail::transfer_exactly_t transfer_exactly(std::size_t size)
-{
-  return detail::transfer_exactly_t(size);
-}
-#endif
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_COMPLETION_CONDITION_HPP
diff --git a/tools/sdk/include/asio/asio/connect.hpp b/tools/sdk/include/asio/asio/connect.hpp
deleted file mode 100644
index 487ce3e0856..00000000000
--- a/tools/sdk/include/asio/asio/connect.hpp
+++ /dev/null
@@ -1,1059 +0,0 @@
-//
-// connect.hpp
-// ~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_CONNECT_HPP
-#define ASIO_CONNECT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/async_result.hpp"
-#include "asio/basic_socket.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail
-{
-  char (&has_iterator_helper(...))[2];
-
-  template <typename T>
-  char has_iterator_helper(T*, typename T::iterator* = 0);
-
-  template <typename T>
-  struct has_iterator_typedef
-  {
-    enum { value = (sizeof((has_iterator_helper)((T*)(0))) == 1) };
-  };
-} // namespace detail
-
-/// Type trait used to determine whether a type is an endpoint sequence that can
-/// be used with with @c connect and @c async_connect.
-template <typename T>
-struct is_endpoint_sequence
-{
-#if defined(GENERATING_DOCUMENTATION)
-  /// The value member is true if the type may be used as an endpoint sequence.
-  static const bool value;
-#else
-  enum
-  {
-    value = detail::has_iterator_typedef<T>::value
-  };
-#endif
-};
-
-/**
- * @defgroup connect asio::connect
- *
- * @brief Establishes a socket connection by trying each endpoint in a sequence.
- */
-/*@{*/
-
-/// Establishes a socket connection by trying each endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param endpoints A sequence of endpoints.
- *
- * @returns The successfully connected endpoint.
- *
- * @throws asio::system_error Thrown on failure. If the sequence is
- * empty, the associated @c error_code is asio::error::not_found.
- * Otherwise, contains the error from the last connection attempt.
- *
- * @par Example
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::socket s(io_context);
- * asio::connect(s, r.resolve(q)); @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM, typename EndpointSequence>
-typename Protocol::endpoint connect(
-    basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type* = 0);
-
-/// Establishes a socket connection by trying each endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param endpoints A sequence of endpoints.
- *
- * @param ec Set to indicate what error occurred, if any. If the sequence is
- * empty, set to asio::error::not_found. Otherwise, contains the error
- * from the last connection attempt.
- *
- * @returns On success, the successfully connected endpoint. Otherwise, a
- * default-constructed endpoint.
- *
- * @par Example
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::socket s(io_context);
- * asio::error_code ec;
- * asio::connect(s, r.resolve(q), ec);
- * if (ec)
- * {
- *   // An error occurred.
- * } @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM, typename EndpointSequence>
-typename Protocol::endpoint connect(
-    basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints, asio::error_code& ec,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type* = 0);
-
-#if !defined(ASIO_NO_DEPRECATED)
-/// (Deprecated.) Establishes a socket connection by trying each endpoint in a
-/// sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @returns On success, an iterator denoting the successfully connected
- * endpoint. Otherwise, the end iterator.
- *
- * @throws asio::system_error Thrown on failure. If the sequence is
- * empty, the associated @c error_code is asio::error::not_found.
- * Otherwise, contains the error from the last connection attempt.
- *
- * @note This overload assumes that a default constructed object of type @c
- * Iterator represents the end of the sequence. This is a valid assumption for
- * iterator types such as @c asio::ip::tcp::resolver::iterator.
- */
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s, Iterator begin,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type* = 0);
-
-/// (Deprecated.) Establishes a socket connection by trying each endpoint in a
-/// sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param ec Set to indicate what error occurred, if any. If the sequence is
- * empty, set to asio::error::not_found. Otherwise, contains the error
- * from the last connection attempt.
- *
- * @returns On success, an iterator denoting the successfully connected
- * endpoint. Otherwise, the end iterator.
- *
- * @note This overload assumes that a default constructed object of type @c
- * Iterator represents the end of the sequence. This is a valid assumption for
- * iterator types such as @c asio::ip::tcp::resolver::iterator.
- */
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, asio::error_code& ec,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type* = 0);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-/// Establishes a socket connection by trying each endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param end An iterator pointing to the end of a sequence of endpoints.
- *
- * @returns An iterator denoting the successfully connected endpoint.
- *
- * @throws asio::system_error Thrown on failure. If the sequence is
- * empty, the associated @c error_code is asio::error::not_found.
- * Otherwise, contains the error from the last connection attempt.
- *
- * @par Example
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::resolver::results_type e = r.resolve(q);
- * tcp::socket s(io_context);
- * asio::connect(s, e.begin(), e.end()); @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end);
-
-/// Establishes a socket connection by trying each endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param end An iterator pointing to the end of a sequence of endpoints.
- *
- * @param ec Set to indicate what error occurred, if any. If the sequence is
- * empty, set to asio::error::not_found. Otherwise, contains the error
- * from the last connection attempt.
- *
- * @returns On success, an iterator denoting the successfully connected
- * endpoint. Otherwise, the end iterator.
- *
- * @par Example
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::resolver::results_type e = r.resolve(q);
- * tcp::socket s(io_context);
- * asio::error_code ec;
- * asio::connect(s, e.begin(), e.end(), ec);
- * if (ec)
- * {
- *   // An error occurred.
- * } @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end, asio::error_code& ec);
-
-/// Establishes a socket connection by trying each endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param endpoints A sequence of endpoints.
- *
- * @param connect_condition A function object that is called prior to each
- * connection attempt. The signature of the function object must be:
- * @code bool connect_condition(
- *     const asio::error_code& ec,
- *     const typename Protocol::endpoint& next); @endcode
- * The @c ec parameter contains the result from the most recent connect
- * operation. Before the first connection attempt, @c ec is always set to
- * indicate success. The @c next parameter is the next endpoint to be tried.
- * The function object should return true if the next endpoint should be tried,
- * and false if it should be skipped.
- *
- * @returns The successfully connected endpoint.
- *
- * @throws asio::system_error Thrown on failure. If the sequence is
- * empty, the associated @c error_code is asio::error::not_found.
- * Otherwise, contains the error from the last connection attempt.
- *
- * @par Example
- * The following connect condition function object can be used to output
- * information about the individual connection attempts:
- * @code struct my_connect_condition
- * {
- *   bool operator()(
- *       const asio::error_code& ec,
- *       const::tcp::endpoint& next)
- *   {
- *     if (ec) std::cout << "Error: " << ec.message() << std::endl;
- *     std::cout << "Trying: " << next << std::endl;
- *     return true;
- *   }
- * }; @endcode
- * It would be used with the asio::connect function as follows:
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::socket s(io_context);
- * tcp::endpoint e = asio::connect(s,
- *     r.resolve(q), my_connect_condition());
- * std::cout << "Connected to: " << e << std::endl; @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename EndpointSequence, typename ConnectCondition>
-typename Protocol::endpoint connect(
-    basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints, ConnectCondition connect_condition,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type* = 0);
-
-/// Establishes a socket connection by trying each endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param endpoints A sequence of endpoints.
- *
- * @param connect_condition A function object that is called prior to each
- * connection attempt. The signature of the function object must be:
- * @code bool connect_condition(
- *     const asio::error_code& ec,
- *     const typename Protocol::endpoint& next); @endcode
- * The @c ec parameter contains the result from the most recent connect
- * operation. Before the first connection attempt, @c ec is always set to
- * indicate success. The @c next parameter is the next endpoint to be tried.
- * The function object should return true if the next endpoint should be tried,
- * and false if it should be skipped.
- *
- * @param ec Set to indicate what error occurred, if any. If the sequence is
- * empty, set to asio::error::not_found. Otherwise, contains the error
- * from the last connection attempt.
- *
- * @returns On success, the successfully connected endpoint. Otherwise, a
- * default-constructed endpoint.
- *
- * @par Example
- * The following connect condition function object can be used to output
- * information about the individual connection attempts:
- * @code struct my_connect_condition
- * {
- *   bool operator()(
- *       const asio::error_code& ec,
- *       const::tcp::endpoint& next)
- *   {
- *     if (ec) std::cout << "Error: " << ec.message() << std::endl;
- *     std::cout << "Trying: " << next << std::endl;
- *     return true;
- *   }
- * }; @endcode
- * It would be used with the asio::connect function as follows:
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::socket s(io_context);
- * asio::error_code ec;
- * tcp::endpoint e = asio::connect(s,
- *     r.resolve(q), my_connect_condition(), ec);
- * if (ec)
- * {
- *   // An error occurred.
- * }
- * else
- * {
- *   std::cout << "Connected to: " << e << std::endl;
- * } @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename EndpointSequence, typename ConnectCondition>
-typename Protocol::endpoint connect(
-    basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints, ConnectCondition connect_condition,
-    asio::error_code& ec,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type* = 0);
-
-#if !defined(ASIO_NO_DEPRECATED)
-/// (Deprecated.) Establishes a socket connection by trying each endpoint in a
-/// sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param connect_condition A function object that is called prior to each
- * connection attempt. The signature of the function object must be:
- * @code bool connect_condition(
- *     const asio::error_code& ec,
- *     const typename Protocol::endpoint& next); @endcode
- * The @c ec parameter contains the result from the most recent connect
- * operation. Before the first connection attempt, @c ec is always set to
- * indicate success. The @c next parameter is the next endpoint to be tried.
- * The function object should return true if the next endpoint should be tried,
- * and false if it should be skipped.
- *
- * @returns On success, an iterator denoting the successfully connected
- * endpoint. Otherwise, the end iterator.
- *
- * @throws asio::system_error Thrown on failure. If the sequence is
- * empty, the associated @c error_code is asio::error::not_found.
- * Otherwise, contains the error from the last connection attempt.
- *
- * @note This overload assumes that a default constructed object of type @c
- * Iterator represents the end of the sequence. This is a valid assumption for
- * iterator types such as @c asio::ip::tcp::resolver::iterator.
- */
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, ConnectCondition connect_condition,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type* = 0);
-
-/// (Deprecated.) Establishes a socket connection by trying each endpoint in a
-/// sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param connect_condition A function object that is called prior to each
- * connection attempt. The signature of the function object must be:
- * @code bool connect_condition(
- *     const asio::error_code& ec,
- *     const typename Protocol::endpoint& next); @endcode
- * The @c ec parameter contains the result from the most recent connect
- * operation. Before the first connection attempt, @c ec is always set to
- * indicate success. The @c next parameter is the next endpoint to be tried.
- * The function object should return true if the next endpoint should be tried,
- * and false if it should be skipped.
- *
- * @param ec Set to indicate what error occurred, if any. If the sequence is
- * empty, set to asio::error::not_found. Otherwise, contains the error
- * from the last connection attempt.
- *
- * @returns On success, an iterator denoting the successfully connected
- * endpoint. Otherwise, the end iterator.
- *
- * @note This overload assumes that a default constructed object of type @c
- * Iterator represents the end of the sequence. This is a valid assumption for
- * iterator types such as @c asio::ip::tcp::resolver::iterator.
- */
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s, Iterator begin,
-    ConnectCondition connect_condition, asio::error_code& ec,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type* = 0);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-/// Establishes a socket connection by trying each endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param end An iterator pointing to the end of a sequence of endpoints.
- *
- * @param connect_condition A function object that is called prior to each
- * connection attempt. The signature of the function object must be:
- * @code bool connect_condition(
- *     const asio::error_code& ec,
- *     const typename Protocol::endpoint& next); @endcode
- * The @c ec parameter contains the result from the most recent connect
- * operation. Before the first connection attempt, @c ec is always set to
- * indicate success. The @c next parameter is the next endpoint to be tried.
- * The function object should return true if the next endpoint should be tried,
- * and false if it should be skipped.
- *
- * @returns An iterator denoting the successfully connected endpoint.
- *
- * @throws asio::system_error Thrown on failure. If the sequence is
- * empty, the associated @c error_code is asio::error::not_found.
- * Otherwise, contains the error from the last connection attempt.
- *
- * @par Example
- * The following connect condition function object can be used to output
- * information about the individual connection attempts:
- * @code struct my_connect_condition
- * {
- *   bool operator()(
- *       const asio::error_code& ec,
- *       const::tcp::endpoint& next)
- *   {
- *     if (ec) std::cout << "Error: " << ec.message() << std::endl;
- *     std::cout << "Trying: " << next << std::endl;
- *     return true;
- *   }
- * }; @endcode
- * It would be used with the asio::connect function as follows:
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::resolver::results_type e = r.resolve(q);
- * tcp::socket s(io_context);
- * tcp::resolver::results_type::iterator i = asio::connect(
- *     s, e.begin(), e.end(), my_connect_condition());
- * std::cout << "Connected to: " << i->endpoint() << std::endl; @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s, Iterator begin,
-    Iterator end, ConnectCondition connect_condition);
-
-/// Establishes a socket connection by trying each endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c connect member
- * function, once for each endpoint in the sequence, until a connection is
- * successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param end An iterator pointing to the end of a sequence of endpoints.
- *
- * @param connect_condition A function object that is called prior to each
- * connection attempt. The signature of the function object must be:
- * @code bool connect_condition(
- *     const asio::error_code& ec,
- *     const typename Protocol::endpoint& next); @endcode
- * The @c ec parameter contains the result from the most recent connect
- * operation. Before the first connection attempt, @c ec is always set to
- * indicate success. The @c next parameter is the next endpoint to be tried.
- * The function object should return true if the next endpoint should be tried,
- * and false if it should be skipped.
- *
- * @param ec Set to indicate what error occurred, if any. If the sequence is
- * empty, set to asio::error::not_found. Otherwise, contains the error
- * from the last connection attempt.
- *
- * @returns On success, an iterator denoting the successfully connected
- * endpoint. Otherwise, the end iterator.
- *
- * @par Example
- * The following connect condition function object can be used to output
- * information about the individual connection attempts:
- * @code struct my_connect_condition
- * {
- *   bool operator()(
- *       const asio::error_code& ec,
- *       const::tcp::endpoint& next)
- *   {
- *     if (ec) std::cout << "Error: " << ec.message() << std::endl;
- *     std::cout << "Trying: " << next << std::endl;
- *     return true;
- *   }
- * }; @endcode
- * It would be used with the asio::connect function as follows:
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::resolver::results_type e = r.resolve(q);
- * tcp::socket s(io_context);
- * asio::error_code ec;
- * tcp::resolver::results_type::iterator i = asio::connect(
- *     s, e.begin(), e.end(), my_connect_condition());
- * if (ec)
- * {
- *   // An error occurred.
- * }
- * else
- * {
- *   std::cout << "Connected to: " << i->endpoint() << std::endl;
- * } @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end, ConnectCondition connect_condition,
-    asio::error_code& ec);
-
-/*@}*/
-
-/**
- * @defgroup async_connect asio::async_connect
- *
- * @brief Asynchronously establishes a socket connection by trying each
- * endpoint in a sequence.
- */
-/*@{*/
-
-/// Asynchronously establishes a socket connection by trying each endpoint in a
-/// sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c async_connect
- * member function, once for each endpoint in the sequence, until a connection
- * is successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param endpoints A sequence of endpoints.
- *
- * @param handler The handler to be called when the connect operation
- * completes. Copies will be made of the handler as required. The function
- * signature of the handler must be:
- * @code void handler(
- *   // Result of operation. if the sequence is empty, set to
- *   // asio::error::not_found. Otherwise, contains the
- *   // error from the last connection attempt.
- *   const asio::error_code& error,
- *
- *   // On success, the successfully connected endpoint.
- *   // Otherwise, a default-constructed endpoint.
- *   const typename Protocol::endpoint& endpoint
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation
- * of the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::socket s(io_context);
- *
- * // ...
- *
- * r.async_resolve(q, resolve_handler);
- *
- * // ...
- *
- * void resolve_handler(
- *     const asio::error_code& ec,
- *     tcp::resolver::results_type results)
- * {
- *   if (!ec)
- *   {
- *     asio::async_connect(s, results, connect_handler);
- *   }
- * }
- *
- * // ...
- *
- * void connect_handler(
- *     const asio::error_code& ec,
- *     const tcp::endpoint& endpoint)
- * {
- *   // ...
- * } @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename EndpointSequence, typename RangeConnectHandler>
-ASIO_INITFN_RESULT_TYPE(RangeConnectHandler,
-    void (asio::error_code, typename Protocol::endpoint))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints,
-    ASIO_MOVE_ARG(RangeConnectHandler) handler,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type* = 0);
-
-#if !defined(ASIO_NO_DEPRECATED)
-/// (Deprecated.) Asynchronously establishes a socket connection by trying each
-/// endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c async_connect
- * member function, once for each endpoint in the sequence, until a connection
- * is successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param handler The handler to be called when the connect operation
- * completes. Copies will be made of the handler as required. The function
- * signature of the handler must be:
- * @code void handler(
- *   // Result of operation. if the sequence is empty, set to
- *   // asio::error::not_found. Otherwise, contains the
- *   // error from the last connection attempt.
- *   const asio::error_code& error,
- *
- *   // On success, an iterator denoting the successfully
- *   // connected endpoint. Otherwise, the end iterator.
- *   Iterator iterator
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation
- * of the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note This overload assumes that a default constructed object of type @c
- * Iterator represents the end of the sequence. This is a valid assumption for
- * iterator types such as @c asio::ip::tcp::resolver::iterator.
- */
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename IteratorConnectHandler>
-ASIO_INITFN_RESULT_TYPE(IteratorConnectHandler,
-    void (asio::error_code, Iterator))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, ASIO_MOVE_ARG(IteratorConnectHandler) handler,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type* = 0);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-/// Asynchronously establishes a socket connection by trying each endpoint in a
-/// sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c async_connect
- * member function, once for each endpoint in the sequence, until a connection
- * is successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param end An iterator pointing to the end of a sequence of endpoints.
- *
- * @param handler The handler to be called when the connect operation
- * completes. Copies will be made of the handler as required. The function
- * signature of the handler must be:
- * @code void handler(
- *   // Result of operation. if the sequence is empty, set to
- *   // asio::error::not_found. Otherwise, contains the
- *   // error from the last connection attempt.
- *   const asio::error_code& error,
- *
- *   // On success, an iterator denoting the successfully
- *   // connected endpoint. Otherwise, the end iterator.
- *   Iterator iterator
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation
- * of the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * @code std::vector<tcp::endpoint> endpoints = ...;
- * tcp::socket s(io_context);
- * asio::async_connect(s,
- *     endpoints.begin(), endpoints.end(),
- *     connect_handler);
- *
- * // ...
- *
- * void connect_handler(
- *     const asio::error_code& ec,
- *     std::vector<tcp::endpoint>::iterator i)
- * {
- *   // ...
- * } @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename IteratorConnectHandler>
-ASIO_INITFN_RESULT_TYPE(IteratorConnectHandler,
-    void (asio::error_code, Iterator))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end,
-    ASIO_MOVE_ARG(IteratorConnectHandler) handler);
-
-/// Asynchronously establishes a socket connection by trying each endpoint in a
-/// sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c async_connect
- * member function, once for each endpoint in the sequence, until a connection
- * is successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param endpoints A sequence of endpoints.
- *
- * @param connect_condition A function object that is called prior to each
- * connection attempt. The signature of the function object must be:
- * @code bool connect_condition(
- *     const asio::error_code& ec,
- *     const typename Protocol::endpoint& next); @endcode
- * The @c ec parameter contains the result from the most recent connect
- * operation. Before the first connection attempt, @c ec is always set to
- * indicate success. The @c next parameter is the next endpoint to be tried.
- * The function object should return true if the next endpoint should be tried,
- * and false if it should be skipped.
- *
- * @param handler The handler to be called when the connect operation
- * completes. Copies will be made of the handler as required. The function
- * signature of the handler must be:
- * @code void handler(
- *   // Result of operation. if the sequence is empty, set to
- *   // asio::error::not_found. Otherwise, contains the
- *   // error from the last connection attempt.
- *   const asio::error_code& error,
- *
- *   // On success, an iterator denoting the successfully
- *   // connected endpoint. Otherwise, the end iterator.
- *   Iterator iterator
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation
- * of the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * The following connect condition function object can be used to output
- * information about the individual connection attempts:
- * @code struct my_connect_condition
- * {
- *   bool operator()(
- *       const asio::error_code& ec,
- *       const::tcp::endpoint& next)
- *   {
- *     if (ec) std::cout << "Error: " << ec.message() << std::endl;
- *     std::cout << "Trying: " << next << std::endl;
- *     return true;
- *   }
- * }; @endcode
- * It would be used with the asio::connect function as follows:
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::socket s(io_context);
- *
- * // ...
- *
- * r.async_resolve(q, resolve_handler);
- *
- * // ...
- *
- * void resolve_handler(
- *     const asio::error_code& ec,
- *     tcp::resolver::results_type results)
- * {
- *   if (!ec)
- *   {
- *     asio::async_connect(s, results,
- *         my_connect_condition(),
- *         connect_handler);
- *   }
- * }
- *
- * // ...
- *
- * void connect_handler(
- *     const asio::error_code& ec,
- *     const tcp::endpoint& endpoint)
- * {
- *   if (ec)
- *   {
- *     // An error occurred.
- *   }
- *   else
- *   {
- *     std::cout << "Connected to: " << endpoint << std::endl;
- *   }
- * } @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM, typename EndpointSequence,
-    typename ConnectCondition, typename RangeConnectHandler>
-ASIO_INITFN_RESULT_TYPE(RangeConnectHandler,
-    void (asio::error_code, typename Protocol::endpoint))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints, ConnectCondition connect_condition,
-    ASIO_MOVE_ARG(RangeConnectHandler) handler,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type* = 0);
-
-#if !defined(ASIO_NO_DEPRECATED)
-/// (Deprecated.) Asynchronously establishes a socket connection by trying each
-/// endpoint in a sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c async_connect
- * member function, once for each endpoint in the sequence, until a connection
- * is successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param connect_condition A function object that is called prior to each
- * connection attempt. The signature of the function object must be:
- * @code bool connect_condition(
- *     const asio::error_code& ec,
- *     const typename Protocol::endpoint& next); @endcode
- * The @c ec parameter contains the result from the most recent connect
- * operation. Before the first connection attempt, @c ec is always set to
- * indicate success. The @c next parameter is the next endpoint to be tried.
- * The function object should return true if the next endpoint should be tried,
- * and false if it should be skipped.
- *
- * @param handler The handler to be called when the connect operation
- * completes. Copies will be made of the handler as required. The function
- * signature of the handler must be:
- * @code void handler(
- *   // Result of operation. if the sequence is empty, set to
- *   // asio::error::not_found. Otherwise, contains the
- *   // error from the last connection attempt.
- *   const asio::error_code& error,
- *
- *   // On success, an iterator denoting the successfully
- *   // connected endpoint. Otherwise, the end iterator.
- *   Iterator iterator
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation
- * of the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note This overload assumes that a default constructed object of type @c
- * Iterator represents the end of the sequence. This is a valid assumption for
- * iterator types such as @c asio::ip::tcp::resolver::iterator.
- */
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator,
-    typename ConnectCondition, typename IteratorConnectHandler>
-ASIO_INITFN_RESULT_TYPE(IteratorConnectHandler,
-    void (asio::error_code, Iterator))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s, Iterator begin,
-    ConnectCondition connect_condition,
-    ASIO_MOVE_ARG(IteratorConnectHandler) handler,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type* = 0);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-/// Asynchronously establishes a socket connection by trying each endpoint in a
-/// sequence.
-/**
- * This function attempts to connect a socket to one of a sequence of
- * endpoints. It does this by repeated calls to the socket's @c async_connect
- * member function, once for each endpoint in the sequence, until a connection
- * is successfully established.
- *
- * @param s The socket to be connected. If the socket is already open, it will
- * be closed.
- *
- * @param begin An iterator pointing to the start of a sequence of endpoints.
- *
- * @param end An iterator pointing to the end of a sequence of endpoints.
- *
- * @param connect_condition A function object that is called prior to each
- * connection attempt. The signature of the function object must be:
- * @code bool connect_condition(
- *     const asio::error_code& ec,
- *     const typename Protocol::endpoint& next); @endcode
- * The @c ec parameter contains the result from the most recent connect
- * operation. Before the first connection attempt, @c ec is always set to
- * indicate success. The @c next parameter is the next endpoint to be tried.
- * The function object should return true if the next endpoint should be tried,
- * and false if it should be skipped.
- *
- * @param handler The handler to be called when the connect operation
- * completes. Copies will be made of the handler as required. The function
- * signature of the handler must be:
- * @code void handler(
- *   // Result of operation. if the sequence is empty, set to
- *   // asio::error::not_found. Otherwise, contains the
- *   // error from the last connection attempt.
- *   const asio::error_code& error,
- *
- *   // On success, an iterator denoting the successfully
- *   // connected endpoint. Otherwise, the end iterator.
- *   Iterator iterator
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation
- * of the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * The following connect condition function object can be used to output
- * information about the individual connection attempts:
- * @code struct my_connect_condition
- * {
- *   bool operator()(
- *       const asio::error_code& ec,
- *       const::tcp::endpoint& next)
- *   {
- *     if (ec) std::cout << "Error: " << ec.message() << std::endl;
- *     std::cout << "Trying: " << next << std::endl;
- *     return true;
- *   }
- * }; @endcode
- * It would be used with the asio::connect function as follows:
- * @code tcp::resolver r(io_context);
- * tcp::resolver::query q("host", "service");
- * tcp::socket s(io_context);
- *
- * // ...
- *
- * r.async_resolve(q, resolve_handler);
- *
- * // ...
- *
- * void resolve_handler(
- *     const asio::error_code& ec,
- *     tcp::resolver::iterator i)
- * {
- *   if (!ec)
- *   {
- *     tcp::resolver::iterator end;
- *     asio::async_connect(s, i, end,
- *         my_connect_condition(),
- *         connect_handler);
- *   }
- * }
- *
- * // ...
- *
- * void connect_handler(
- *     const asio::error_code& ec,
- *     tcp::resolver::iterator i)
- * {
- *   if (ec)
- *   {
- *     // An error occurred.
- *   }
- *   else
- *   {
- *     std::cout << "Connected to: " << i->endpoint() << std::endl;
- *   }
- * } @endcode
- */
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator,
-    typename ConnectCondition, typename IteratorConnectHandler>
-ASIO_INITFN_RESULT_TYPE(IteratorConnectHandler,
-    void (asio::error_code, Iterator))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end, ConnectCondition connect_condition,
-    ASIO_MOVE_ARG(IteratorConnectHandler) handler);
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/connect.hpp"
-
-#endif
diff --git a/tools/sdk/include/asio/asio/coroutine.hpp b/tools/sdk/include/asio/asio/coroutine.hpp
deleted file mode 100644
index cd2d99e536a..00000000000
--- a/tools/sdk/include/asio/asio/coroutine.hpp
+++ /dev/null
@@ -1,328 +0,0 @@
-//
-// coroutine.hpp
-// ~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_COROUTINE_HPP
-#define ASIO_COROUTINE_HPP
-
-namespace asio {
-namespace detail {
-
-class coroutine_ref;
-
-} // namespace detail
-
-/// Provides support for implementing stackless coroutines.
-/**
- * The @c coroutine class may be used to implement stackless coroutines. The
- * class itself is used to store the current state of the coroutine.
- *
- * Coroutines are copy-constructible and assignable, and the space overhead is
- * a single int. They can be used as a base class:
- *
- * @code class session : coroutine
- * {
- *   ...
- * }; @endcode
- *
- * or as a data member:
- *
- * @code class session
- * {
- *   ...
- *   coroutine coro_;
- * }; @endcode
- *
- * or even bound in as a function argument using lambdas or @c bind(). The
- * important thing is that as the application maintains a copy of the object
- * for as long as the coroutine must be kept alive.
- *
- * @par Pseudo-keywords
- *
- * A coroutine is used in conjunction with certain "pseudo-keywords", which
- * are implemented as macros. These macros are defined by a header file:
- *
- * @code #include <asio/yield.hpp>@endcode
- *
- * and may conversely be undefined as follows:
- *
- * @code #include <asio/unyield.hpp>@endcode
- *
- * <b>reenter</b>
- *
- * The @c reenter macro is used to define the body of a coroutine. It takes a
- * single argument: a pointer or reference to a coroutine object. For example,
- * if the base class is a coroutine object you may write:
- *
- * @code reenter (this)
- * {
- *   ... coroutine body ...
- * } @endcode
- *
- * and if a data member or other variable you can write:
- *
- * @code reenter (coro_)
- * {
- *   ... coroutine body ...
- * } @endcode
- *
- * When @c reenter is executed at runtime, control jumps to the location of the
- * last @c yield or @c fork.
- *
- * The coroutine body may also be a single statement, such as:
- *
- * @code reenter (this) for (;;)
- * {
- *   ...
- * } @endcode
- *
- * @b Limitation: The @c reenter macro is implemented using a switch. This
- * means that you must take care when using local variables within the
- * coroutine body. The local variable is not allowed in a position where
- * reentering the coroutine could bypass the variable definition.
- *
- * <b>yield <em>statement</em></b>
- *
- * This form of the @c yield keyword is often used with asynchronous operations:
- *
- * @code yield socket_->async_read_some(buffer(*buffer_), *this); @endcode
- *
- * This divides into four logical steps:
- *
- * @li @c yield saves the current state of the coroutine.
- * @li The statement initiates the asynchronous operation.
- * @li The resume point is defined immediately following the statement.
- * @li Control is transferred to the end of the coroutine body.
- *
- * When the asynchronous operation completes, the function object is invoked
- * and @c reenter causes control to transfer to the resume point. It is
- * important to remember to carry the coroutine state forward with the
- * asynchronous operation. In the above snippet, the current class is a
- * function object object with a coroutine object as base class or data member.
- *
- * The statement may also be a compound statement, and this permits us to
- * define local variables with limited scope:
- *
- * @code yield
- * {
- *   mutable_buffers_1 b = buffer(*buffer_);
- *   socket_->async_read_some(b, *this);
- * } @endcode
- *
- * <b>yield return <em>expression</em> ;</b>
- *
- * This form of @c yield is often used in generators or coroutine-based parsers.
- * For example, the function object:
- *
- * @code struct interleave : coroutine
- * {
- *   istream& is1;
- *   istream& is2;
- *   char operator()(char c)
- *   {
- *     reenter (this) for (;;)
- *     {
- *       yield return is1.get();
- *       yield return is2.get();
- *     }
- *   }
- * }; @endcode
- *
- * defines a trivial coroutine that interleaves the characters from two input
- * streams.
- *
- * This type of @c yield divides into three logical steps:
- *
- * @li @c yield saves the current state of the coroutine.
- * @li The resume point is defined immediately following the semicolon.
- * @li The value of the expression is returned from the function.
- *
- * <b>yield ;</b>
- *
- * This form of @c yield is equivalent to the following steps:
- *
- * @li @c yield saves the current state of the coroutine.
- * @li The resume point is defined immediately following the semicolon.
- * @li Control is transferred to the end of the coroutine body.
- *
- * This form might be applied when coroutines are used for cooperative
- * threading and scheduling is explicitly managed. For example:
- *
- * @code struct task : coroutine
- * {
- *   ...
- *   void operator()()
- *   {
- *     reenter (this)
- *     {
- *       while (... not finished ...)
- *       {
- *         ... do something ...
- *         yield;
- *         ... do some more ...
- *         yield;
- *       }
- *     }
- *   }
- *   ...
- * };
- * ...
- * task t1, t2;
- * for (;;)
- * {
- *   t1();
- *   t2();
- * } @endcode
- *
- * <b>yield break ;</b>
- *
- * The final form of @c yield is used to explicitly terminate the coroutine.
- * This form is comprised of two steps:
- *
- * @li @c yield sets the coroutine state to indicate termination.
- * @li Control is transferred to the end of the coroutine body.
- *
- * Once terminated, calls to is_complete() return true and the coroutine cannot
- * be reentered.
- *
- * Note that a coroutine may also be implicitly terminated if the coroutine
- * body is exited without a yield, e.g. by return, throw or by running to the
- * end of the body.
- *
- * <b>fork <em>statement</em></b>
- *
- * The @c fork pseudo-keyword is used when "forking" a coroutine, i.e. splitting
- * it into two (or more) copies. One use of @c fork is in a server, where a new
- * coroutine is created to handle each client connection:
- * 
- * @code reenter (this)
- * {
- *   do
- *   {
- *     socket_.reset(new tcp::socket(io_context_));
- *     yield acceptor->async_accept(*socket_, *this);
- *     fork server(*this)();
- *   } while (is_parent());
- *   ... client-specific handling follows ...
- * } @endcode
- * 
- * The logical steps involved in a @c fork are:
- * 
- * @li @c fork saves the current state of the coroutine.
- * @li The statement creates a copy of the coroutine and either executes it
- *     immediately or schedules it for later execution.
- * @li The resume point is defined immediately following the semicolon.
- * @li For the "parent", control immediately continues from the next line.
- *
- * The functions is_parent() and is_child() can be used to differentiate
- * between parent and child. You would use these functions to alter subsequent
- * control flow.
- *
- * Note that @c fork doesn't do the actual forking by itself. It is the
- * application's responsibility to create a clone of the coroutine and call it.
- * The clone can be called immediately, as above, or scheduled for delayed
- * execution using something like io_context::post().
- *
- * @par Alternate macro names
- *
- * If preferred, an application can use macro names that follow a more typical
- * naming convention, rather than the pseudo-keywords. These are:
- *
- * @li @c ASIO_CORO_REENTER instead of @c reenter
- * @li @c ASIO_CORO_YIELD instead of @c yield
- * @li @c ASIO_CORO_FORK instead of @c fork
- */
-class coroutine
-{
-public:
-  /// Constructs a coroutine in its initial state.
-  coroutine() : value_(0) {}
-
-  /// Returns true if the coroutine is the child of a fork.
-  bool is_child() const { return value_ < 0; }
-
-  /// Returns true if the coroutine is the parent of a fork.
-  bool is_parent() const { return !is_child(); }
-
-  /// Returns true if the coroutine has reached its terminal state.
-  bool is_complete() const { return value_ == -1; }
-
-private:
-  friend class detail::coroutine_ref;
-  int value_;
-};
-
-
-namespace detail {
-
-class coroutine_ref
-{
-public:
-  coroutine_ref(coroutine& c) : value_(c.value_), modified_(false) {}
-  coroutine_ref(coroutine* c) : value_(c->value_), modified_(false) {}
-  ~coroutine_ref() { if (!modified_) value_ = -1; }
-  operator int() const { return value_; }
-  int& operator=(int v) { modified_ = true; return value_ = v; }
-private:
-  void operator=(const coroutine_ref&);
-  int& value_;
-  bool modified_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#define ASIO_CORO_REENTER(c) \
-  switch (::asio::detail::coroutine_ref _coro_value = c) \
-    case -1: if (_coro_value) \
-    { \
-      goto terminate_coroutine; \
-      terminate_coroutine: \
-      _coro_value = -1; \
-      goto bail_out_of_coroutine; \
-      bail_out_of_coroutine: \
-      break; \
-    } \
-    else /* fall-through */ case 0:
-
-#define ASIO_CORO_YIELD_IMPL(n) \
-  for (_coro_value = (n);;) \
-    if (_coro_value == 0) \
-    { \
-      case (n): ; \
-      break; \
-    } \
-    else \
-      switch (_coro_value ? 0 : 1) \
-        for (;;) \
-          /* fall-through */ case -1: if (_coro_value) \
-            goto terminate_coroutine; \
-          else for (;;) \
-            /* fall-through */ case 1: if (_coro_value) \
-              goto bail_out_of_coroutine; \
-            else /* fall-through */ case 0:
-
-#define ASIO_CORO_FORK_IMPL(n) \
-  for (_coro_value = -(n);; _coro_value = (n)) \
-    if (_coro_value == (n)) \
-    { \
-      case -(n): ; \
-      break; \
-    } \
-    else
-
-#if defined(_MSC_VER)
-# define ASIO_CORO_YIELD ASIO_CORO_YIELD_IMPL(__COUNTER__ + 1)
-# define ASIO_CORO_FORK ASIO_CORO_FORK_IMPL(__COUNTER__ + 1)
-#else // defined(_MSC_VER)
-# define ASIO_CORO_YIELD ASIO_CORO_YIELD_IMPL(__LINE__)
-# define ASIO_CORO_FORK ASIO_CORO_FORK_IMPL(__LINE__)
-#endif // defined(_MSC_VER)
-
-#endif // ASIO_COROUTINE_HPP
diff --git a/tools/sdk/include/asio/asio/datagram_socket_service.hpp b/tools/sdk/include/asio/asio/datagram_socket_service.hpp
deleted file mode 100644
index 7dc1a3b34a7..00000000000
--- a/tools/sdk/include/asio/asio/datagram_socket_service.hpp
+++ /dev/null
@@ -1,466 +0,0 @@
-//
-// datagram_socket_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DATAGRAM_SOCKET_SERVICE_HPP
-#define ASIO_DATAGRAM_SOCKET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/null_socket_service.hpp"
-#elif defined(ASIO_HAS_IOCP)
-# include "asio/detail/win_iocp_socket_service.hpp"
-#else
-# include "asio/detail/reactive_socket_service.hpp"
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default service implementation for a datagram socket.
-template <typename Protocol>
-class datagram_socket_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<datagram_socket_service<Protocol> >
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-private:
-  // The type of the platform-specific implementation.
-#if defined(ASIO_WINDOWS_RUNTIME)
-  typedef detail::null_socket_service<Protocol> service_impl_type;
-#elif defined(ASIO_HAS_IOCP)
-  typedef detail::win_iocp_socket_service<Protocol> service_impl_type;
-#else
-  typedef detail::reactive_socket_service<Protocol> service_impl_type;
-#endif
-
-public:
-  /// The type of a datagram socket.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef typename service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native socket type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new datagram socket service for the specified io_context.
-  explicit datagram_socket_service(asio::io_context& io_context)
-    : asio::detail::service_base<
-        datagram_socket_service<Protocol> >(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new datagram socket implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new datagram socket implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another datagram socket implementation.
-  void move_assign(implementation_type& impl,
-      datagram_socket_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-
-  // All socket services have access to each other's implementations.
-  template <typename Protocol1> friend class datagram_socket_service;
-
-  /// Move-construct a new datagram socket implementation from another protocol
-  /// type.
-  template <typename Protocol1>
-  void converting_move_construct(implementation_type& impl,
-      datagram_socket_service<Protocol1>& other_service,
-      typename datagram_socket_service<
-        Protocol1>::implementation_type& other_impl,
-      typename enable_if<is_convertible<
-        Protocol1, Protocol>::value>::type* = 0)
-  {
-    service_impl_.template converting_move_construct<Protocol1>(
-        impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a datagram socket implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  // Open a new datagram socket implementation.
-  ASIO_SYNC_OP_VOID open(implementation_type& impl,
-      const protocol_type& protocol, asio::error_code& ec)
-  {
-    if (protocol.type() == ASIO_OS_DEF(SOCK_DGRAM))
-      service_impl_.open(impl, protocol, ec);
-    else
-      ec = asio::error::invalid_argument;
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assign an existing native socket to a datagram socket.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const protocol_type& protocol, const native_handle_type& native_socket,
-      asio::error_code& ec)
-  {
-    service_impl_.assign(impl, protocol, native_socket, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Close a datagram socket implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Release ownership of the underlying socket.
-  native_handle_type release(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return service_impl_.release(impl, ec);
-  }
-
-  /// Get the native socket implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the socket.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is at the out-of-band data mark.
-  bool at_mark(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.at_mark(impl, ec);
-  }
-
-  /// Determine the number of bytes available for reading.
-  std::size_t available(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.available(impl, ec);
-  }
-
-  // Bind the datagram socket to the specified local endpoint.
-  ASIO_SYNC_OP_VOID bind(implementation_type& impl,
-      const endpoint_type& endpoint, asio::error_code& ec)
-  {
-    service_impl_.bind(impl, endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Connect the datagram socket to the specified endpoint.
-  ASIO_SYNC_OP_VOID connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, asio::error_code& ec)
-  {
-    service_impl_.connect(impl, peer_endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous connect.
-  template <typename ConnectHandler>
-  ASIO_INITFN_RESULT_TYPE(ConnectHandler,
-      void (asio::error_code))
-  async_connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint,
-      ASIO_MOVE_ARG(ConnectHandler) handler)
-  {
-    async_completion<ConnectHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_connect(impl, peer_endpoint, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Set a socket option.
-  template <typename SettableSocketOption>
-  ASIO_SYNC_OP_VOID set_option(implementation_type& impl,
-      const SettableSocketOption& option, asio::error_code& ec)
-  {
-    service_impl_.set_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get a socket option.
-  template <typename GettableSocketOption>
-  ASIO_SYNC_OP_VOID get_option(const implementation_type& impl,
-      GettableSocketOption& option, asio::error_code& ec) const
-  {
-    service_impl_.get_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the socket.
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(implementation_type& impl,
-      IoControlCommand& command, asio::error_code& ec)
-  {
-    service_impl_.io_control(impl, command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the socket.
-  bool non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the socket.
-  ASIO_SYNC_OP_VOID non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native socket implementation.
-  bool native_non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.native_non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the native socket implementation.
-  ASIO_SYNC_OP_VOID native_non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.native_non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the local endpoint.
-  endpoint_type local_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.local_endpoint(impl, ec);
-  }
-
-  /// Get the remote endpoint.
-  endpoint_type remote_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.remote_endpoint(impl, ec);
-  }
-
-  /// Disable sends or receives on the socket.
-  ASIO_SYNC_OP_VOID shutdown(implementation_type& impl,
-      socket_base::shutdown_type what, asio::error_code& ec)
-  {
-    service_impl_.shutdown(impl, what, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Wait for the socket to become ready to read, ready to write, or to have
-  /// pending error conditions.
-  ASIO_SYNC_OP_VOID wait(implementation_type& impl,
-      socket_base::wait_type w, asio::error_code& ec)
-  {
-    service_impl_.wait(impl, w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the socket to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(implementation_type& impl, socket_base::wait_type w,
-      ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_wait(impl, w, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Send the given data to the peer.
-  template <typename ConstBufferSequence>
-  std::size_t send(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.send(impl, buffers, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(implementation_type& impl, const ConstBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_send(impl, buffers, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Send a datagram to the specified endpoint.
-  template <typename ConstBufferSequence>
-  std::size_t send_to(implementation_type& impl,
-      const ConstBufferSequence& buffers, const endpoint_type& destination,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.send_to(impl, buffers, destination, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send_to(implementation_type& impl,
-      const ConstBufferSequence& buffers, const endpoint_type& destination,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_send_to(impl, buffers,
-        destination, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Receive some data from the peer.
-  template <typename MutableBufferSequence>
-  std::size_t receive(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.receive(impl, buffers, flags, ec);
-  }
-
-  /// Start an asynchronous receive.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_receive(impl, buffers, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Receive a datagram with the endpoint of the sender.
-  template <typename MutableBufferSequence>
-  std::size_t receive_from(implementation_type& impl,
-      const MutableBufferSequence& buffers, endpoint_type& sender_endpoint,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.receive_from(impl, buffers, sender_endpoint, flags,
-        ec);
-  }
-
-  /// Start an asynchronous receive that will get the endpoint of the sender.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive_from(implementation_type& impl,
-      const MutableBufferSequence& buffers, endpoint_type& sender_endpoint,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_receive_from(impl, buffers,
-        sender_endpoint, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_DATAGRAM_SOCKET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/deadline_timer.hpp b/tools/sdk/include/asio/asio/deadline_timer.hpp
deleted file mode 100644
index 5a2155474a5..00000000000
--- a/tools/sdk/include/asio/asio/deadline_timer.hpp
+++ /dev/null
@@ -1,38 +0,0 @@
-//
-// deadline_timer.hpp
-// ~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DEADLINE_TIMER_HPP
-#define ASIO_DEADLINE_TIMER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/detail/socket_types.hpp" // Must come before posix_time.
-#include "asio/basic_deadline_timer.hpp"
-
-#include <boost/date_time/posix_time/posix_time_types.hpp>
-
-namespace asio {
-
-/// Typedef for the typical usage of timer. Uses a UTC clock.
-typedef basic_deadline_timer<boost::posix_time::ptime> deadline_timer;
-
-} // namespace asio
-
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_DEADLINE_TIMER_HPP
diff --git a/tools/sdk/include/asio/asio/deadline_timer_service.hpp b/tools/sdk/include/asio/asio/deadline_timer_service.hpp
deleted file mode 100644
index 2dcc83e2f92..00000000000
--- a/tools/sdk/include/asio/asio/deadline_timer_service.hpp
+++ /dev/null
@@ -1,173 +0,0 @@
-//
-// deadline_timer_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DEADLINE_TIMER_SERVICE_HPP
-#define ASIO_DEADLINE_TIMER_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/deadline_timer_service.hpp"
-#include "asio/io_context.hpp"
-#include "asio/time_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default service implementation for a timer.
-template <typename TimeType,
-    typename TimeTraits = asio::time_traits<TimeType> >
-class deadline_timer_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<
-      deadline_timer_service<TimeType, TimeTraits> >
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-  /// The time traits type.
-  typedef TimeTraits traits_type;
-
-  /// The time type.
-  typedef typename traits_type::time_type time_type;
-
-  /// The duration type.
-  typedef typename traits_type::duration_type duration_type;
-
-private:
-  // The type of the platform-specific implementation.
-  typedef detail::deadline_timer_service<traits_type> service_impl_type;
-
-public:
-  /// The implementation type of the deadline timer.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef typename service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// Construct a new timer service for the specified io_context.
-  explicit deadline_timer_service(asio::io_context& io_context)
-    : asio::detail::service_base<
-        deadline_timer_service<TimeType, TimeTraits> >(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new timer implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-  /// Destroy a timer implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Cancel any asynchronous wait operations associated with the timer.
-  std::size_t cancel(implementation_type& impl, asio::error_code& ec)
-  {
-    return service_impl_.cancel(impl, ec);
-  }
-
-  /// Cancels one asynchronous wait operation associated with the timer.
-  std::size_t cancel_one(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return service_impl_.cancel_one(impl, ec);
-  }
-
-  /// Get the expiry time for the timer as an absolute time.
-  time_type expires_at(const implementation_type& impl) const
-  {
-    return service_impl_.expiry(impl);
-  }
-
-  /// Set the expiry time for the timer as an absolute time.
-  std::size_t expires_at(implementation_type& impl,
-      const time_type& expiry_time, asio::error_code& ec)
-  {
-    return service_impl_.expires_at(impl, expiry_time, ec);
-  }
-
-  /// Get the expiry time for the timer relative to now.
-  duration_type expires_from_now(const implementation_type& impl) const
-  {
-    return TimeTraits::subtract(service_impl_.expiry(impl), TimeTraits::now());
-  }
-
-  /// Set the expiry time for the timer relative to now.
-  std::size_t expires_from_now(implementation_type& impl,
-      const duration_type& expiry_time, asio::error_code& ec)
-  {
-    return service_impl_.expires_after(impl, expiry_time, ec);
-  }
-
-  // Perform a blocking wait on the timer.
-  void wait(implementation_type& impl, asio::error_code& ec)
-  {
-    service_impl_.wait(impl, ec);
-  }
-
-  // Start an asynchronous wait on the timer.
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(implementation_type& impl,
-      ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_wait(impl, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_DEADLINE_TIMER_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/defer.hpp b/tools/sdk/include/asio/asio/defer.hpp
deleted file mode 100644
index a0897f2f83f..00000000000
--- a/tools/sdk/include/asio/asio/defer.hpp
+++ /dev/null
@@ -1,107 +0,0 @@
-//
-// defer.hpp
-// ~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DEFER_HPP
-#define ASIO_DEFER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/async_result.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/execution_context.hpp"
-#include "asio/is_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Submits a completion token or function object for execution.
-/**
- * This function submits an object for execution using the object's associated
- * executor. The function object is queued for execution, and is never called
- * from the current thread prior to returning from <tt>defer()</tt>.
- *
- * This function has the following effects:
- *
- * @li Constructs a function object handler of type @c Handler, initialized
- * with <tt>handler(forward<CompletionToken>(token))</tt>.
- *
- * @li Constructs an object @c result of type <tt>async_result<Handler></tt>,
- * initializing the object as <tt>result(handler)</tt>.
- *
- * @li Obtains the handler's associated executor object @c ex by performing
- * <tt>get_associated_executor(handler)</tt>.
- *
- * @li Obtains the handler's associated allocator object @c alloc by performing
- * <tt>get_associated_allocator(handler)</tt>.
- *
- * @li Performs <tt>ex.defer(std::move(handler), alloc)</tt>.
- *
- * @li Returns <tt>result.get()</tt>.
- */
-template <typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) defer(
-    ASIO_MOVE_ARG(CompletionToken) token);
-
-/// Submits a completion token or function object for execution.
-/**
- * This function submits an object for execution using the specified executor.
- * The function object is queued for execution, and is never called from the
- * current thread prior to returning from <tt>defer()</tt>.
- *
- * This function has the following effects:
- *
- * @li Constructs a function object handler of type @c Handler, initialized
- * with <tt>handler(forward<CompletionToken>(token))</tt>.
- *
- * @li Constructs an object @c result of type <tt>async_result<Handler></tt>,
- * initializing the object as <tt>result(handler)</tt>.
- *
- * @li Obtains the handler's associated executor object @c ex1 by performing
- * <tt>get_associated_executor(handler)</tt>.
- *
- * @li Creates a work object @c w by performing <tt>make_work(ex1)</tt>.
- *
- * @li Obtains the handler's associated allocator object @c alloc by performing
- * <tt>get_associated_allocator(handler)</tt>.
- *
- * @li Constructs a function object @c f with a function call operator that
- * performs <tt>ex1.dispatch(std::move(handler), alloc)</tt> followed by
- * <tt>w.reset()</tt>.
- *
- * @li Performs <tt>Executor(ex).defer(std::move(f), alloc)</tt>.
- *
- * @li Returns <tt>result.get()</tt>.
- */
-template <typename Executor, typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) defer(
-    const Executor& ex, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_executor<Executor>::value>::type* = 0);
-
-/// Submits a completion token or function object for execution.
-/**
- * @returns <tt>defer(ctx.get_executor(), forward<CompletionToken>(token))</tt>.
- */
-template <typename ExecutionContext, typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) defer(
-    ExecutionContext& ctx, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_convertible<
-      ExecutionContext&, execution_context&>::value>::type* = 0);
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/defer.hpp"
-
-#endif // ASIO_DEFER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/array.hpp b/tools/sdk/include/asio/asio/detail/array.hpp
deleted file mode 100644
index ba4297462ca..00000000000
--- a/tools/sdk/include/asio/asio/detail/array.hpp
+++ /dev/null
@@ -1,38 +0,0 @@
-//
-// detail/array.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_ARRAY_HPP
-#define ASIO_DETAIL_ARRAY_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_ARRAY)
-# include <array>
-#else // defined(ASIO_HAS_STD_ARRAY)
-# include <boost/array.hpp>
-#endif // defined(ASIO_HAS_STD_ARRAY)
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_HAS_STD_ARRAY)
-using std::array;
-#else // defined(ASIO_HAS_STD_ARRAY)
-using boost::array;
-#endif // defined(ASIO_HAS_STD_ARRAY)
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_ARRAY_HPP
diff --git a/tools/sdk/include/asio/asio/detail/array_fwd.hpp b/tools/sdk/include/asio/asio/detail/array_fwd.hpp
deleted file mode 100644
index 4161db0dbde..00000000000
--- a/tools/sdk/include/asio/asio/detail/array_fwd.hpp
+++ /dev/null
@@ -1,34 +0,0 @@
-//
-// detail/array_fwd.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_ARRAY_FWD_HPP
-#define ASIO_DETAIL_ARRAY_FWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-namespace boost {
-
-template<class T, std::size_t N>
-class array;
-
-} // namespace boost
-
-// Standard library components can't be forward declared, so we'll have to
-// include the array header. Fortunately, it's fairly lightweight and doesn't
-// add significantly to the compile time.
-#if defined(ASIO_HAS_STD_ARRAY)
-# include <array>
-#endif // defined(ASIO_HAS_STD_ARRAY)
-
-#endif // ASIO_DETAIL_ARRAY_FWD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/assert.hpp b/tools/sdk/include/asio/asio/detail/assert.hpp
deleted file mode 100644
index a952a441f2c..00000000000
--- a/tools/sdk/include/asio/asio/detail/assert.hpp
+++ /dev/null
@@ -1,32 +0,0 @@
-//
-// detail/assert.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_ASSERT_HPP
-#define ASIO_DETAIL_ASSERT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_BOOST_ASSERT)
-# include <boost/assert.hpp>
-#else // defined(ASIO_HAS_BOOST_ASSERT)
-# include <cassert>
-#endif // defined(ASIO_HAS_BOOST_ASSERT)
-
-#if defined(ASIO_HAS_BOOST_ASSERT)
-# define ASIO_ASSERT(expr) BOOST_ASSERT(expr)
-#else // defined(ASIO_HAS_BOOST_ASSERT)
-# define ASIO_ASSERT(expr) assert(expr)
-#endif // defined(ASIO_HAS_BOOST_ASSERT)
-
-#endif // ASIO_DETAIL_ASSERT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/atomic_count.hpp b/tools/sdk/include/asio/asio/detail/atomic_count.hpp
deleted file mode 100644
index 2bf75a5355e..00000000000
--- a/tools/sdk/include/asio/asio/detail/atomic_count.hpp
+++ /dev/null
@@ -1,45 +0,0 @@
-//
-// detail/atomic_count.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_ATOMIC_COUNT_HPP
-#define ASIO_DETAIL_ATOMIC_COUNT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-// Nothing to include.
-#elif defined(ASIO_HAS_STD_ATOMIC)
-# include <atomic>
-#else // defined(ASIO_HAS_STD_ATOMIC)
-# include <boost/detail/atomic_count.hpp>
-#endif // defined(ASIO_HAS_STD_ATOMIC)
-
-namespace asio {
-namespace detail {
-
-#if !defined(ASIO_HAS_THREADS)
-typedef long atomic_count;
-inline void increment(atomic_count& a, long b) { a += b; }
-#elif defined(ASIO_HAS_STD_ATOMIC)
-typedef std::atomic<long> atomic_count;
-inline void increment(atomic_count& a, long b) { a += b; }
-#else // defined(ASIO_HAS_STD_ATOMIC)
-typedef boost::detail::atomic_count atomic_count;
-inline void increment(atomic_count& a, long b) { while (b > 0) ++a, --b; }
-#endif // defined(ASIO_HAS_STD_ATOMIC)
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_ATOMIC_COUNT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/base_from_completion_cond.hpp b/tools/sdk/include/asio/asio/detail/base_from_completion_cond.hpp
deleted file mode 100644
index 73b4a957f3a..00000000000
--- a/tools/sdk/include/asio/asio/detail/base_from_completion_cond.hpp
+++ /dev/null
@@ -1,68 +0,0 @@
-//
-// detail/base_from_completion_cond.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_BASE_FROM_COMPLETION_COND_HPP
-#define ASIO_DETAIL_BASE_FROM_COMPLETION_COND_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/completion_condition.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename CompletionCondition>
-class base_from_completion_cond
-{
-protected:
-  explicit base_from_completion_cond(CompletionCondition completion_condition)
-    : completion_condition_(completion_condition)
-  {
-  }
-
-  std::size_t check_for_completion(
-      const asio::error_code& ec,
-      std::size_t total_transferred)
-  {
-    return detail::adapt_completion_condition_result(
-        completion_condition_(ec, total_transferred));
-  }
-
-private:
-  CompletionCondition completion_condition_;
-};
-
-template <>
-class base_from_completion_cond<transfer_all_t>
-{
-protected:
-  explicit base_from_completion_cond(transfer_all_t)
-  {
-  }
-
-  static std::size_t check_for_completion(
-      const asio::error_code& ec,
-      std::size_t total_transferred)
-  {
-    return transfer_all_t()(ec, total_transferred);
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_BASE_FROM_COMPLETION_COND_HPP
diff --git a/tools/sdk/include/asio/asio/detail/bind_handler.hpp b/tools/sdk/include/asio/asio/detail/bind_handler.hpp
deleted file mode 100644
index 0f4f066d837..00000000000
--- a/tools/sdk/include/asio/asio/detail/bind_handler.hpp
+++ /dev/null
@@ -1,816 +0,0 @@
-//
-// detail/bind_handler.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_BIND_HANDLER_HPP
-#define ASIO_DETAIL_BIND_HANDLER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler, typename Arg1>
-class binder1
-{
-public:
-  template <typename T>
-  binder1(int, ASIO_MOVE_ARG(T) handler, const Arg1& arg1)
-    : handler_(ASIO_MOVE_CAST(T)(handler)),
-      arg1_(arg1)
-  {
-  }
-
-  binder1(Handler& handler, const Arg1& arg1)
-    : handler_(ASIO_MOVE_CAST(Handler)(handler)),
-      arg1_(arg1)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  binder1(const binder1& other)
-    : handler_(other.handler_),
-      arg1_(other.arg1_)
-  {
-  }
-
-  binder1(binder1&& other)
-    : handler_(ASIO_MOVE_CAST(Handler)(other.handler_)),
-      arg1_(ASIO_MOVE_CAST(Arg1)(other.arg1_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  void operator()()
-  {
-    handler_(static_cast<const Arg1&>(arg1_));
-  }
-
-  void operator()() const
-  {
-    handler_(arg1_);
-  }
-
-//private:
-  Handler handler_;
-  Arg1 arg1_;
-};
-
-template <typename Handler, typename Arg1>
-inline void* asio_handler_allocate(std::size_t size,
-    binder1<Handler, Arg1>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    binder1<Handler, Arg1>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1>
-inline bool asio_handler_is_continuation(
-    binder1<Handler, Arg1>* this_handler)
-{
-  return asio_handler_cont_helpers::is_continuation(
-      this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1>
-inline void asio_handler_invoke(Function& function,
-    binder1<Handler, Arg1>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1>
-inline void asio_handler_invoke(const Function& function,
-    binder1<Handler, Arg1>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1>
-inline binder1<typename decay<Handler>::type, Arg1> bind_handler(
-    ASIO_MOVE_ARG(Handler) handler, const Arg1& arg1)
-{
-  return binder1<typename decay<Handler>::type, Arg1>(0,
-      ASIO_MOVE_CAST(Handler)(handler), arg1);
-}
-
-template <typename Handler, typename Arg1, typename Arg2>
-class binder2
-{
-public:
-  template <typename T>
-  binder2(int, ASIO_MOVE_ARG(T) handler,
-      const Arg1& arg1, const Arg2& arg2)
-    : handler_(ASIO_MOVE_CAST(T)(handler)),
-      arg1_(arg1),
-      arg2_(arg2)
-  {
-  }
-
-  binder2(Handler& handler, const Arg1& arg1, const Arg2& arg2)
-    : handler_(ASIO_MOVE_CAST(Handler)(handler)),
-      arg1_(arg1),
-      arg2_(arg2)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  binder2(const binder2& other)
-    : handler_(other.handler_),
-      arg1_(other.arg1_),
-      arg2_(other.arg2_)
-  {
-  }
-
-  binder2(binder2&& other)
-    : handler_(ASIO_MOVE_CAST(Handler)(other.handler_)),
-      arg1_(ASIO_MOVE_CAST(Arg1)(other.arg1_)),
-      arg2_(ASIO_MOVE_CAST(Arg2)(other.arg2_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  void operator()()
-  {
-    handler_(static_cast<const Arg1&>(arg1_),
-        static_cast<const Arg2&>(arg2_));
-  }
-
-  void operator()() const
-  {
-    handler_(arg1_, arg2_);
-  }
-
-//private:
-  Handler handler_;
-  Arg1 arg1_;
-  Arg2 arg2_;
-};
-
-template <typename Handler, typename Arg1, typename Arg2>
-inline void* asio_handler_allocate(std::size_t size,
-    binder2<Handler, Arg1, Arg2>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    binder2<Handler, Arg1, Arg2>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2>
-inline bool asio_handler_is_continuation(
-    binder2<Handler, Arg1, Arg2>* this_handler)
-{
-  return asio_handler_cont_helpers::is_continuation(
-      this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1, typename Arg2>
-inline void asio_handler_invoke(Function& function,
-    binder2<Handler, Arg1, Arg2>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1, typename Arg2>
-inline void asio_handler_invoke(const Function& function,
-    binder2<Handler, Arg1, Arg2>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2>
-inline binder2<typename decay<Handler>::type, Arg1, Arg2> bind_handler(
-    ASIO_MOVE_ARG(Handler) handler, const Arg1& arg1, const Arg2& arg2)
-{
-  return binder2<typename decay<Handler>::type, Arg1, Arg2>(0,
-      ASIO_MOVE_CAST(Handler)(handler), arg1, arg2);
-}
-
-template <typename Handler, typename Arg1, typename Arg2, typename Arg3>
-class binder3
-{
-public:
-  template <typename T>
-  binder3(int, ASIO_MOVE_ARG(T) handler, const Arg1& arg1,
-      const Arg2& arg2, const Arg3& arg3)
-    : handler_(ASIO_MOVE_CAST(T)(handler)),
-      arg1_(arg1),
-      arg2_(arg2),
-      arg3_(arg3)
-  {
-  }
-
-  binder3(Handler& handler, const Arg1& arg1,
-      const Arg2& arg2, const Arg3& arg3)
-    : handler_(ASIO_MOVE_CAST(Handler)(handler)),
-      arg1_(arg1),
-      arg2_(arg2),
-      arg3_(arg3)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  binder3(const binder3& other)
-    : handler_(other.handler_),
-      arg1_(other.arg1_),
-      arg2_(other.arg2_),
-      arg3_(other.arg3_)
-  {
-  }
-
-  binder3(binder3&& other)
-    : handler_(ASIO_MOVE_CAST(Handler)(other.handler_)),
-      arg1_(ASIO_MOVE_CAST(Arg1)(other.arg1_)),
-      arg2_(ASIO_MOVE_CAST(Arg2)(other.arg2_)),
-      arg3_(ASIO_MOVE_CAST(Arg3)(other.arg3_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  void operator()()
-  {
-    handler_(static_cast<const Arg1&>(arg1_),
-        static_cast<const Arg2&>(arg2_), static_cast<const Arg3&>(arg3_));
-  }
-
-  void operator()() const
-  {
-    handler_(arg1_, arg2_, arg3_);
-  }
-
-//private:
-  Handler handler_;
-  Arg1 arg1_;
-  Arg2 arg2_;
-  Arg3 arg3_;
-};
-
-template <typename Handler, typename Arg1, typename Arg2, typename Arg3>
-inline void* asio_handler_allocate(std::size_t size,
-    binder3<Handler, Arg1, Arg2, Arg3>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2, typename Arg3>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    binder3<Handler, Arg1, Arg2, Arg3>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2, typename Arg3>
-inline bool asio_handler_is_continuation(
-    binder3<Handler, Arg1, Arg2, Arg3>* this_handler)
-{
-  return asio_handler_cont_helpers::is_continuation(
-      this_handler->handler_);
-}
-
-template <typename Function, typename Handler,
-    typename Arg1, typename Arg2, typename Arg3>
-inline void asio_handler_invoke(Function& function,
-    binder3<Handler, Arg1, Arg2, Arg3>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Function, typename Handler,
-    typename Arg1, typename Arg2, typename Arg3>
-inline void asio_handler_invoke(const Function& function,
-    binder3<Handler, Arg1, Arg2, Arg3>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2, typename Arg3>
-inline binder3<typename decay<Handler>::type, Arg1, Arg2, Arg3> bind_handler(
-    ASIO_MOVE_ARG(Handler) handler, const Arg1& arg1, const Arg2& arg2,
-    const Arg3& arg3)
-{
-  return binder3<typename decay<Handler>::type, Arg1, Arg2, Arg3>(0,
-      ASIO_MOVE_CAST(Handler)(handler), arg1, arg2, arg3);
-}
-
-template <typename Handler, typename Arg1,
-    typename Arg2, typename Arg3, typename Arg4>
-class binder4
-{
-public:
-  template <typename T>
-  binder4(int, ASIO_MOVE_ARG(T) handler, const Arg1& arg1,
-      const Arg2& arg2, const Arg3& arg3, const Arg4& arg4)
-    : handler_(ASIO_MOVE_CAST(T)(handler)),
-      arg1_(arg1),
-      arg2_(arg2),
-      arg3_(arg3),
-      arg4_(arg4)
-  {
-  }
-
-  binder4(Handler& handler, const Arg1& arg1,
-      const Arg2& arg2, const Arg3& arg3, const Arg4& arg4)
-    : handler_(ASIO_MOVE_CAST(Handler)(handler)),
-      arg1_(arg1),
-      arg2_(arg2),
-      arg3_(arg3),
-      arg4_(arg4)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  binder4(const binder4& other)
-    : handler_(other.handler_),
-      arg1_(other.arg1_),
-      arg2_(other.arg2_),
-      arg3_(other.arg3_),
-      arg4_(other.arg4_)
-  {
-  }
-
-  binder4(binder4&& other)
-    : handler_(ASIO_MOVE_CAST(Handler)(other.handler_)),
-      arg1_(ASIO_MOVE_CAST(Arg1)(other.arg1_)),
-      arg2_(ASIO_MOVE_CAST(Arg2)(other.arg2_)),
-      arg3_(ASIO_MOVE_CAST(Arg3)(other.arg3_)),
-      arg4_(ASIO_MOVE_CAST(Arg4)(other.arg4_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  void operator()()
-  {
-    handler_(static_cast<const Arg1&>(arg1_),
-        static_cast<const Arg2&>(arg2_), static_cast<const Arg3&>(arg3_),
-        static_cast<const Arg4&>(arg4_));
-  }
-
-  void operator()() const
-  {
-    handler_(arg1_, arg2_, arg3_, arg4_);
-  }
-
-//private:
-  Handler handler_;
-  Arg1 arg1_;
-  Arg2 arg2_;
-  Arg3 arg3_;
-  Arg4 arg4_;
-};
-
-template <typename Handler, typename Arg1,
-    typename Arg2, typename Arg3, typename Arg4>
-inline void* asio_handler_allocate(std::size_t size,
-    binder4<Handler, Arg1, Arg2, Arg3, Arg4>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1,
-    typename Arg2, typename Arg3, typename Arg4>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    binder4<Handler, Arg1, Arg2, Arg3, Arg4>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1,
-    typename Arg2, typename Arg3, typename Arg4>
-inline bool asio_handler_is_continuation(
-    binder4<Handler, Arg1, Arg2, Arg3, Arg4>* this_handler)
-{
-  return asio_handler_cont_helpers::is_continuation(
-      this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1,
-    typename Arg2, typename Arg3, typename Arg4>
-inline void asio_handler_invoke(Function& function,
-    binder4<Handler, Arg1, Arg2, Arg3, Arg4>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1,
-    typename Arg2, typename Arg3, typename Arg4>
-inline void asio_handler_invoke(const Function& function,
-    binder4<Handler, Arg1, Arg2, Arg3, Arg4>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1,
-    typename Arg2, typename Arg3, typename Arg4>
-inline binder4<typename decay<Handler>::type, Arg1, Arg2, Arg3, Arg4>
-bind_handler(ASIO_MOVE_ARG(Handler) handler, const Arg1& arg1,
-    const Arg2& arg2, const Arg3& arg3, const Arg4& arg4)
-{
-  return binder4<typename decay<Handler>::type, Arg1, Arg2, Arg3, Arg4>(0,
-      ASIO_MOVE_CAST(Handler)(handler), arg1, arg2, arg3, arg4);
-}
-
-template <typename Handler, typename Arg1, typename Arg2,
-    typename Arg3, typename Arg4, typename Arg5>
-class binder5
-{
-public:
-  template <typename T>
-  binder5(int, ASIO_MOVE_ARG(T) handler, const Arg1& arg1,
-      const Arg2& arg2, const Arg3& arg3, const Arg4& arg4, const Arg5& arg5)
-    : handler_(ASIO_MOVE_CAST(T)(handler)),
-      arg1_(arg1),
-      arg2_(arg2),
-      arg3_(arg3),
-      arg4_(arg4),
-      arg5_(arg5)
-  {
-  }
-
-  binder5(Handler& handler, const Arg1& arg1, const Arg2& arg2,
-      const Arg3& arg3, const Arg4& arg4, const Arg5& arg5)
-    : handler_(ASIO_MOVE_CAST(Handler)(handler)),
-      arg1_(arg1),
-      arg2_(arg2),
-      arg3_(arg3),
-      arg4_(arg4),
-      arg5_(arg5)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  binder5(const binder5& other)
-    : handler_(other.handler_),
-      arg1_(other.arg1_),
-      arg2_(other.arg2_),
-      arg3_(other.arg3_),
-      arg4_(other.arg4_),
-      arg5_(other.arg5_)
-  {
-  }
-
-  binder5(binder5&& other)
-    : handler_(ASIO_MOVE_CAST(Handler)(other.handler_)),
-      arg1_(ASIO_MOVE_CAST(Arg1)(other.arg1_)),
-      arg2_(ASIO_MOVE_CAST(Arg2)(other.arg2_)),
-      arg3_(ASIO_MOVE_CAST(Arg3)(other.arg3_)),
-      arg4_(ASIO_MOVE_CAST(Arg4)(other.arg4_)),
-      arg5_(ASIO_MOVE_CAST(Arg5)(other.arg5_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  void operator()()
-  {
-    handler_(static_cast<const Arg1&>(arg1_),
-        static_cast<const Arg2&>(arg2_), static_cast<const Arg3&>(arg3_),
-        static_cast<const Arg4&>(arg4_), static_cast<const Arg5&>(arg5_));
-  }
-
-  void operator()() const
-  {
-    handler_(arg1_, arg2_, arg3_, arg4_, arg5_);
-  }
-
-//private:
-  Handler handler_;
-  Arg1 arg1_;
-  Arg2 arg2_;
-  Arg3 arg3_;
-  Arg4 arg4_;
-  Arg5 arg5_;
-};
-
-template <typename Handler, typename Arg1, typename Arg2,
-    typename Arg3, typename Arg4, typename Arg5>
-inline void* asio_handler_allocate(std::size_t size,
-    binder5<Handler, Arg1, Arg2, Arg3, Arg4, Arg5>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2,
-    typename Arg3, typename Arg4, typename Arg5>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    binder5<Handler, Arg1, Arg2, Arg3, Arg4, Arg5>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2,
-    typename Arg3, typename Arg4, typename Arg5>
-inline bool asio_handler_is_continuation(
-    binder5<Handler, Arg1, Arg2, Arg3, Arg4, Arg5>* this_handler)
-{
-  return asio_handler_cont_helpers::is_continuation(
-      this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1,
-    typename Arg2, typename Arg3, typename Arg4, typename Arg5>
-inline void asio_handler_invoke(Function& function,
-    binder5<Handler, Arg1, Arg2, Arg3, Arg4, Arg5>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1,
-    typename Arg2, typename Arg3, typename Arg4, typename Arg5>
-inline void asio_handler_invoke(const Function& function,
-    binder5<Handler, Arg1, Arg2, Arg3, Arg4, Arg5>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2,
-    typename Arg3, typename Arg4, typename Arg5>
-inline binder5<typename decay<Handler>::type, Arg1, Arg2, Arg3, Arg4, Arg5>
-bind_handler(ASIO_MOVE_ARG(Handler) handler, const Arg1& arg1,
-    const Arg2& arg2, const Arg3& arg3, const Arg4& arg4, const Arg5& arg5)
-{
-  return binder5<typename decay<Handler>::type, Arg1, Arg2, Arg3, Arg4, Arg5>(0,
-      ASIO_MOVE_CAST(Handler)(handler), arg1, arg2, arg3, arg4, arg5);
-}
-
-#if defined(ASIO_HAS_MOVE)
-
-template <typename Handler, typename Arg1>
-class move_binder1
-{
-public:
-  move_binder1(int, ASIO_MOVE_ARG(Handler) handler,
-      ASIO_MOVE_ARG(Arg1) arg1)
-    : handler_(ASIO_MOVE_CAST(Handler)(handler)),
-      arg1_(ASIO_MOVE_CAST(Arg1)(arg1))
-  {
-  }
-
-  move_binder1(move_binder1&& other)
-    : handler_(ASIO_MOVE_CAST(Handler)(other.handler_)),
-      arg1_(ASIO_MOVE_CAST(Arg1)(other.arg1_))
-  {
-  }
-
-  void operator()()
-  {
-    handler_(ASIO_MOVE_CAST(Arg1)(arg1_));
-  }
-
-//private:
-  Handler handler_;
-  Arg1 arg1_;
-};
-
-template <typename Handler, typename Arg1>
-inline void* asio_handler_allocate(std::size_t size,
-    move_binder1<Handler, Arg1>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    move_binder1<Handler, Arg1>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1>
-inline bool asio_handler_is_continuation(
-    move_binder1<Handler, Arg1>* this_handler)
-{
-  return asio_handler_cont_helpers::is_continuation(
-      this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1>
-inline void asio_handler_invoke(ASIO_MOVE_ARG(Function) function,
-    move_binder1<Handler, Arg1>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      ASIO_MOVE_CAST(Function)(function), this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2>
-class move_binder2
-{
-public:
-  move_binder2(int, ASIO_MOVE_ARG(Handler) handler,
-      const Arg1& arg1, ASIO_MOVE_ARG(Arg2) arg2)
-    : handler_(ASIO_MOVE_CAST(Handler)(handler)),
-      arg1_(arg1),
-      arg2_(ASIO_MOVE_CAST(Arg2)(arg2))
-  {
-  }
-
-  move_binder2(move_binder2&& other)
-    : handler_(ASIO_MOVE_CAST(Handler)(other.handler_)),
-      arg1_(ASIO_MOVE_CAST(Arg1)(other.arg1_)),
-      arg2_(ASIO_MOVE_CAST(Arg2)(other.arg2_))
-  {
-  }
-
-  void operator()()
-  {
-    handler_(static_cast<const Arg1&>(arg1_),
-        ASIO_MOVE_CAST(Arg2)(arg2_));
-  }
-
-//private:
-  Handler handler_;
-  Arg1 arg1_;
-  Arg2 arg2_;
-};
-
-template <typename Handler, typename Arg1, typename Arg2>
-inline void* asio_handler_allocate(std::size_t size,
-    move_binder2<Handler, Arg1, Arg2>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    move_binder2<Handler, Arg1, Arg2>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Handler, typename Arg1, typename Arg2>
-inline bool asio_handler_is_continuation(
-    move_binder2<Handler, Arg1, Arg2>* this_handler)
-{
-  return asio_handler_cont_helpers::is_continuation(
-      this_handler->handler_);
-}
-
-template <typename Function, typename Handler, typename Arg1, typename Arg2>
-inline void asio_handler_invoke(ASIO_MOVE_ARG(Function) function,
-    move_binder2<Handler, Arg1, Arg2>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      ASIO_MOVE_CAST(Function)(function), this_handler->handler_);
-}
-
-#endif // defined(ASIO_HAS_MOVE)
-
-} // namespace detail
-
-template <typename Handler, typename Arg1, typename Allocator>
-struct associated_allocator<detail::binder1<Handler, Arg1>, Allocator>
-{
-  typedef typename associated_allocator<Handler, Allocator>::type type;
-
-  static type get(const detail::binder1<Handler, Arg1>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<Handler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename Handler, typename Arg1, typename Arg2, typename Allocator>
-struct associated_allocator<detail::binder2<Handler, Arg1, Arg2>, Allocator>
-{
-  typedef typename associated_allocator<Handler, Allocator>::type type;
-
-  static type get(const detail::binder2<Handler, Arg1, Arg2>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<Handler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename Handler, typename Arg1, typename Executor>
-struct associated_executor<detail::binder1<Handler, Arg1>, Executor>
-{
-  typedef typename associated_executor<Handler, Executor>::type type;
-
-  static type get(const detail::binder1<Handler, Arg1>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<Handler, Executor>::get(h.handler_, ex);
-  }
-};
-
-template <typename Handler, typename Arg1, typename Arg2, typename Executor>
-struct associated_executor<detail::binder2<Handler, Arg1, Arg2>, Executor>
-{
-  typedef typename associated_executor<Handler, Executor>::type type;
-
-  static type get(const detail::binder2<Handler, Arg1, Arg2>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<Handler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#if defined(ASIO_HAS_MOVE)
-
-template <typename Handler, typename Arg1, typename Allocator>
-struct associated_allocator<detail::move_binder1<Handler, Arg1>, Allocator>
-{
-  typedef typename associated_allocator<Handler, Allocator>::type type;
-
-  static type get(const detail::move_binder1<Handler, Arg1>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<Handler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename Handler, typename Arg1, typename Arg2, typename Allocator>
-struct associated_allocator<
-    detail::move_binder2<Handler, Arg1, Arg2>, Allocator>
-{
-  typedef typename associated_allocator<Handler, Allocator>::type type;
-
-  static type get(const detail::move_binder2<Handler, Arg1, Arg2>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<Handler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename Handler, typename Arg1, typename Executor>
-struct associated_executor<detail::move_binder1<Handler, Arg1>, Executor>
-{
-  typedef typename associated_executor<Handler, Executor>::type type;
-
-  static type get(const detail::move_binder1<Handler, Arg1>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<Handler, Executor>::get(h.handler_, ex);
-  }
-};
-
-template <typename Handler, typename Arg1, typename Arg2, typename Executor>
-struct associated_executor<detail::move_binder2<Handler, Arg1, Arg2>, Executor>
-{
-  typedef typename associated_executor<Handler, Executor>::type type;
-
-  static type get(const detail::move_binder2<Handler, Arg1, Arg2>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<Handler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // defined(ASIO_HAS_MOVE)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_BIND_HANDLER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/buffer_resize_guard.hpp b/tools/sdk/include/asio/asio/detail/buffer_resize_guard.hpp
deleted file mode 100644
index 58ebc4cc79c..00000000000
--- a/tools/sdk/include/asio/asio/detail/buffer_resize_guard.hpp
+++ /dev/null
@@ -1,66 +0,0 @@
-//
-// detail/buffer_resize_guard.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_BUFFER_RESIZE_GUARD_HPP
-#define ASIO_DETAIL_BUFFER_RESIZE_GUARD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/limits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Helper class to manage buffer resizing in an exception safe way.
-template <typename Buffer>
-class buffer_resize_guard
-{
-public:
-  // Constructor.
-  buffer_resize_guard(Buffer& buffer)
-    : buffer_(buffer),
-      old_size_(buffer.size())
-  {
-  }
-
-  // Destructor rolls back the buffer resize unless commit was called.
-  ~buffer_resize_guard()
-  {
-    if (old_size_ != (std::numeric_limits<size_t>::max)())
-    {
-      buffer_.resize(old_size_);
-    }
-  }
-
-  // Commit the resize transaction.
-  void commit()
-  {
-    old_size_ = (std::numeric_limits<size_t>::max)();
-  }
-
-private:
-  // The buffer being managed.
-  Buffer& buffer_;
-
-  // The size of the buffer at the time the guard was constructed.
-  size_t old_size_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_BUFFER_RESIZE_GUARD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/buffer_sequence_adapter.hpp b/tools/sdk/include/asio/asio/detail/buffer_sequence_adapter.hpp
deleted file mode 100644
index 92a8e3d2faf..00000000000
--- a/tools/sdk/include/asio/asio/detail/buffer_sequence_adapter.hpp
+++ /dev/null
@@ -1,544 +0,0 @@
-//
-// detail/buffer_sequence_adapter.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_BUFFER_SEQUENCE_ADAPTER_HPP
-#define ASIO_DETAIL_BUFFER_SEQUENCE_ADAPTER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/buffer.hpp"
-#include "asio/detail/array_fwd.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class buffer_sequence_adapter_base
-{
-#if defined(ASIO_WINDOWS_RUNTIME)
-public:
-  // The maximum number of buffers to support in a single operation.
-  enum { max_buffers = 1 };
-
-protected:
-  typedef Windows::Storage::Streams::IBuffer^ native_buffer_type;
-
-  ASIO_DECL static void init_native_buffer(
-      native_buffer_type& buf,
-      const asio::mutable_buffer& buffer);
-
-  ASIO_DECL static void init_native_buffer(
-      native_buffer_type& buf,
-      const asio::const_buffer& buffer);
-#elif defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-public:
-  // The maximum number of buffers to support in a single operation.
-  enum { max_buffers = 64 < max_iov_len ? 64 : max_iov_len };
-
-protected:
-  typedef WSABUF native_buffer_type;
-
-  static void init_native_buffer(WSABUF& buf,
-      const asio::mutable_buffer& buffer)
-  {
-    buf.buf = static_cast<char*>(buffer.data());
-    buf.len = static_cast<ULONG>(buffer.size());
-  }
-
-  static void init_native_buffer(WSABUF& buf,
-      const asio::const_buffer& buffer)
-  {
-    buf.buf = const_cast<char*>(static_cast<const char*>(buffer.data()));
-    buf.len = static_cast<ULONG>(buffer.size());
-  }
-#else // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-public:
-  // The maximum number of buffers to support in a single operation.
-  enum { max_buffers = 64 < max_iov_len ? 64 : max_iov_len };
-
-protected:
-  typedef iovec native_buffer_type;
-
-  static void init_iov_base(void*& base, void* addr)
-  {
-    base = addr;
-  }
-
-  template <typename T>
-  static void init_iov_base(T& base, void* addr)
-  {
-    base = static_cast<T>(addr);
-  }
-
-  static void init_native_buffer(iovec& iov,
-      const asio::mutable_buffer& buffer)
-  {
-    init_iov_base(iov.iov_base, buffer.data());
-    iov.iov_len = buffer.size();
-  }
-
-  static void init_native_buffer(iovec& iov,
-      const asio::const_buffer& buffer)
-  {
-    init_iov_base(iov.iov_base, const_cast<void*>(buffer.data()));
-    iov.iov_len = buffer.size();
-  }
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-};
-
-// Helper class to translate buffers into the native buffer representation.
-template <typename Buffer, typename Buffers>
-class buffer_sequence_adapter
-  : buffer_sequence_adapter_base
-{
-public:
-  explicit buffer_sequence_adapter(const Buffers& buffer_sequence)
-    : count_(0), total_buffer_size_(0)
-  {
-    buffer_sequence_adapter::init(
-        asio::buffer_sequence_begin(buffer_sequence),
-        asio::buffer_sequence_end(buffer_sequence));
-  }
-
-  native_buffer_type* buffers()
-  {
-    return buffers_;
-  }
-
-  std::size_t count() const
-  {
-    return count_;
-  }
-
-  std::size_t total_size() const
-  {
-    return total_buffer_size_;
-  }
-
-  bool all_empty() const
-  {
-    return total_buffer_size_ == 0;
-  }
-
-  static bool all_empty(const Buffers& buffer_sequence)
-  {
-    return buffer_sequence_adapter::all_empty(
-        asio::buffer_sequence_begin(buffer_sequence),
-        asio::buffer_sequence_end(buffer_sequence));
-  }
-
-  static void validate(const Buffers& buffer_sequence)
-  {
-    buffer_sequence_adapter::validate(
-        asio::buffer_sequence_begin(buffer_sequence),
-        asio::buffer_sequence_end(buffer_sequence));
-  }
-
-  static Buffer first(const Buffers& buffer_sequence)
-  {
-    return buffer_sequence_adapter::first(
-        asio::buffer_sequence_begin(buffer_sequence),
-        asio::buffer_sequence_end(buffer_sequence));
-  }
-
-private:
-  template <typename Iterator>
-  void init(Iterator begin, Iterator end)
-  {
-    Iterator iter = begin;
-    for (; iter != end && count_ < max_buffers; ++iter, ++count_)
-    {
-      Buffer buffer(*iter);
-      init_native_buffer(buffers_[count_], buffer);
-      total_buffer_size_ += buffer.size();
-    }
-  }
-
-  template <typename Iterator>
-  static bool all_empty(Iterator begin, Iterator end)
-  {
-    Iterator iter = begin;
-    std::size_t i = 0;
-    for (; iter != end && i < max_buffers; ++iter, ++i)
-      if (Buffer(*iter).size() > 0)
-        return false;
-    return true;
-  }
-
-  template <typename Iterator>
-  static void validate(Iterator begin, Iterator end)
-  {
-    Iterator iter = begin;
-    for (; iter != end; ++iter)
-    {
-      Buffer buffer(*iter);
-      buffer.data();
-    }
-  }
-
-  template <typename Iterator>
-  static Buffer first(Iterator begin, Iterator end)
-  {
-    Iterator iter = begin;
-    for (; iter != end; ++iter)
-    {
-      Buffer buffer(*iter);
-      if (buffer.size() != 0)
-        return buffer;
-    }
-    return Buffer();
-  }
-
-  native_buffer_type buffers_[max_buffers];
-  std::size_t count_;
-  std::size_t total_buffer_size_;
-};
-
-template <typename Buffer>
-class buffer_sequence_adapter<Buffer, asio::mutable_buffer>
-  : buffer_sequence_adapter_base
-{
-public:
-  explicit buffer_sequence_adapter(
-      const asio::mutable_buffer& buffer_sequence)
-  {
-    init_native_buffer(buffer_, Buffer(buffer_sequence));
-    total_buffer_size_ = buffer_sequence.size();
-  }
-
-  native_buffer_type* buffers()
-  {
-    return &buffer_;
-  }
-
-  std::size_t count() const
-  {
-    return 1;
-  }
-
-  std::size_t total_size() const
-  {
-    return total_buffer_size_;
-  }
-
-  bool all_empty() const
-  {
-    return total_buffer_size_ == 0;
-  }
-
-  static bool all_empty(const asio::mutable_buffer& buffer_sequence)
-  {
-    return buffer_sequence.size() == 0;
-  }
-
-  static void validate(const asio::mutable_buffer& buffer_sequence)
-  {
-    buffer_sequence.data();
-  }
-
-  static Buffer first(const asio::mutable_buffer& buffer_sequence)
-  {
-    return Buffer(buffer_sequence);
-  }
-
-private:
-  native_buffer_type buffer_;
-  std::size_t total_buffer_size_;
-};
-
-template <typename Buffer>
-class buffer_sequence_adapter<Buffer, asio::const_buffer>
-  : buffer_sequence_adapter_base
-{
-public:
-  explicit buffer_sequence_adapter(
-      const asio::const_buffer& buffer_sequence)
-  {
-    init_native_buffer(buffer_, Buffer(buffer_sequence));
-    total_buffer_size_ = buffer_sequence.size();
-  }
-
-  native_buffer_type* buffers()
-  {
-    return &buffer_;
-  }
-
-  std::size_t count() const
-  {
-    return 1;
-  }
-
-  std::size_t total_size() const
-  {
-    return total_buffer_size_;
-  }
-
-  bool all_empty() const
-  {
-    return total_buffer_size_ == 0;
-  }
-
-  static bool all_empty(const asio::const_buffer& buffer_sequence)
-  {
-    return buffer_sequence.size() == 0;
-  }
-
-  static void validate(const asio::const_buffer& buffer_sequence)
-  {
-    buffer_sequence.data();
-  }
-
-  static Buffer first(const asio::const_buffer& buffer_sequence)
-  {
-    return Buffer(buffer_sequence);
-  }
-
-private:
-  native_buffer_type buffer_;
-  std::size_t total_buffer_size_;
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-template <typename Buffer>
-class buffer_sequence_adapter<Buffer, asio::mutable_buffers_1>
-  : buffer_sequence_adapter_base
-{
-public:
-  explicit buffer_sequence_adapter(
-      const asio::mutable_buffers_1& buffer_sequence)
-  {
-    init_native_buffer(buffer_, Buffer(buffer_sequence));
-    total_buffer_size_ = buffer_sequence.size();
-  }
-
-  native_buffer_type* buffers()
-  {
-    return &buffer_;
-  }
-
-  std::size_t count() const
-  {
-    return 1;
-  }
-
-  std::size_t total_size() const
-  {
-    return total_buffer_size_;
-  }
-
-  bool all_empty() const
-  {
-    return total_buffer_size_ == 0;
-  }
-
-  static bool all_empty(const asio::mutable_buffers_1& buffer_sequence)
-  {
-    return buffer_sequence.size() == 0;
-  }
-
-  static void validate(const asio::mutable_buffers_1& buffer_sequence)
-  {
-    buffer_sequence.data();
-  }
-
-  static Buffer first(const asio::mutable_buffers_1& buffer_sequence)
-  {
-    return Buffer(buffer_sequence);
-  }
-
-private:
-  native_buffer_type buffer_;
-  std::size_t total_buffer_size_;
-};
-
-template <typename Buffer>
-class buffer_sequence_adapter<Buffer, asio::const_buffers_1>
-  : buffer_sequence_adapter_base
-{
-public:
-  explicit buffer_sequence_adapter(
-      const asio::const_buffers_1& buffer_sequence)
-  {
-    init_native_buffer(buffer_, Buffer(buffer_sequence));
-    total_buffer_size_ = buffer_sequence.size();
-  }
-
-  native_buffer_type* buffers()
-  {
-    return &buffer_;
-  }
-
-  std::size_t count() const
-  {
-    return 1;
-  }
-
-  std::size_t total_size() const
-  {
-    return total_buffer_size_;
-  }
-
-  bool all_empty() const
-  {
-    return total_buffer_size_ == 0;
-  }
-
-  static bool all_empty(const asio::const_buffers_1& buffer_sequence)
-  {
-    return buffer_sequence.size() == 0;
-  }
-
-  static void validate(const asio::const_buffers_1& buffer_sequence)
-  {
-    buffer_sequence.data();
-  }
-
-  static Buffer first(const asio::const_buffers_1& buffer_sequence)
-  {
-    return Buffer(buffer_sequence);
-  }
-
-private:
-  native_buffer_type buffer_;
-  std::size_t total_buffer_size_;
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Buffer, typename Elem>
-class buffer_sequence_adapter<Buffer, boost::array<Elem, 2> >
-  : buffer_sequence_adapter_base
-{
-public:
-  explicit buffer_sequence_adapter(
-      const boost::array<Elem, 2>& buffer_sequence)
-  {
-    init_native_buffer(buffers_[0], Buffer(buffer_sequence[0]));
-    init_native_buffer(buffers_[1], Buffer(buffer_sequence[1]));
-    total_buffer_size_ = buffer_sequence[0].size() + buffer_sequence[1].size();
-  }
-
-  native_buffer_type* buffers()
-  {
-    return buffers_;
-  }
-
-  std::size_t count() const
-  {
-    return 2;
-  }
-
-  std::size_t total_size() const
-  {
-    return total_buffer_size_;
-  }
-
-  bool all_empty() const
-  {
-    return total_buffer_size_ == 0;
-  }
-
-  static bool all_empty(const boost::array<Elem, 2>& buffer_sequence)
-  {
-    return buffer_sequence[0].size() == 0 && buffer_sequence[1].size() == 0;
-  }
-
-  static void validate(const boost::array<Elem, 2>& buffer_sequence)
-  {
-    buffer_sequence[0].data();
-    buffer_sequence[1].data();
-  }
-
-  static Buffer first(const boost::array<Elem, 2>& buffer_sequence)
-  {
-    return Buffer(buffer_sequence[0].size() != 0
-        ? buffer_sequence[0] : buffer_sequence[1]);
-  }
-
-private:
-  native_buffer_type buffers_[2];
-  std::size_t total_buffer_size_;
-};
-
-#if defined(ASIO_HAS_STD_ARRAY)
-
-template <typename Buffer, typename Elem>
-class buffer_sequence_adapter<Buffer, std::array<Elem, 2> >
-  : buffer_sequence_adapter_base
-{
-public:
-  explicit buffer_sequence_adapter(
-      const std::array<Elem, 2>& buffer_sequence)
-  {
-    init_native_buffer(buffers_[0], Buffer(buffer_sequence[0]));
-    init_native_buffer(buffers_[1], Buffer(buffer_sequence[1]));
-    total_buffer_size_ = buffer_sequence[0].size() + buffer_sequence[1].size();
-  }
-
-  native_buffer_type* buffers()
-  {
-    return buffers_;
-  }
-
-  std::size_t count() const
-  {
-    return 2;
-  }
-
-  std::size_t total_size() const
-  {
-    return total_buffer_size_;
-  }
-
-  bool all_empty() const
-  {
-    return total_buffer_size_ == 0;
-  }
-
-  static bool all_empty(const std::array<Elem, 2>& buffer_sequence)
-  {
-    return buffer_sequence[0].size() == 0 && buffer_sequence[1].size() == 0;
-  }
-
-  static void validate(const std::array<Elem, 2>& buffer_sequence)
-  {
-    buffer_sequence[0].data();
-    buffer_sequence[1].data();
-  }
-
-  static Buffer first(const std::array<Elem, 2>& buffer_sequence)
-  {
-    return Buffer(buffer_sequence[0].size() != 0
-        ? buffer_sequence[0] : buffer_sequence[1]);
-  }
-
-private:
-  native_buffer_type buffers_[2];
-  std::size_t total_buffer_size_;
-};
-
-#endif // defined(ASIO_HAS_STD_ARRAY)
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/buffer_sequence_adapter.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_BUFFER_SEQUENCE_ADAPTER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/buffered_stream_storage.hpp b/tools/sdk/include/asio/asio/detail/buffered_stream_storage.hpp
deleted file mode 100644
index c5eb081d9a3..00000000000
--- a/tools/sdk/include/asio/asio/detail/buffered_stream_storage.hpp
+++ /dev/null
@@ -1,126 +0,0 @@
-//
-// detail/buffered_stream_storage.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_BUFFERED_STREAM_STORAGE_HPP
-#define ASIO_DETAIL_BUFFERED_STREAM_STORAGE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/buffer.hpp"
-#include "asio/detail/assert.hpp"
-#include <cstddef>
-#include <cstring>
-#include <vector>
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class buffered_stream_storage
-{
-public:
-  // The type of the bytes stored in the buffer.
-  typedef unsigned char byte_type;
-
-  // The type used for offsets into the buffer.
-  typedef std::size_t size_type;
-
-  // Constructor.
-  explicit buffered_stream_storage(std::size_t buffer_capacity)
-    : begin_offset_(0),
-      end_offset_(0),
-      buffer_(buffer_capacity)
-  {
-  }
-
-  /// Clear the buffer.
-  void clear()
-  {
-    begin_offset_ = 0;
-    end_offset_ = 0;
-  }
-
-  // Return a pointer to the beginning of the unread data.
-  mutable_buffer data()
-  {
-    return asio::buffer(buffer_) + begin_offset_;
-  }
-
-  // Return a pointer to the beginning of the unread data.
-  const_buffer data() const
-  {
-    return asio::buffer(buffer_) + begin_offset_;
-  }
-
-  // Is there no unread data in the buffer.
-  bool empty() const
-  {
-    return begin_offset_ == end_offset_;
-  }
-
-  // Return the amount of unread data the is in the buffer.
-  size_type size() const
-  {
-    return end_offset_ - begin_offset_;
-  }
-
-  // Resize the buffer to the specified length.
-  void resize(size_type length)
-  {
-    ASIO_ASSERT(length <= capacity());
-    if (begin_offset_ + length <= capacity())
-    {
-      end_offset_ = begin_offset_ + length;
-    }
-    else
-    {
-      using namespace std; // For memmove.
-      memmove(&buffer_[0], &buffer_[0] + begin_offset_, size());
-      end_offset_ = length;
-      begin_offset_ = 0;
-    }
-  }
-
-  // Return the maximum size for data in the buffer.
-  size_type capacity() const
-  {
-    return buffer_.size();
-  }
-
-  // Consume multiple bytes from the beginning of the buffer.
-  void consume(size_type count)
-  {
-    ASIO_ASSERT(begin_offset_ + count <= end_offset_);
-    begin_offset_ += count;
-    if (empty())
-      clear();
-  }
-
-private:
-  // The offset to the beginning of the unread data.
-  size_type begin_offset_;
-
-  // The offset to the end of the unread data.
-  size_type end_offset_;
-  
-  // The data in the buffer.
-  std::vector<byte_type> buffer_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_BUFFERED_STREAM_STORAGE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/call_stack.hpp b/tools/sdk/include/asio/asio/detail/call_stack.hpp
deleted file mode 100644
index 5725a10a22f..00000000000
--- a/tools/sdk/include/asio/asio/detail/call_stack.hpp
+++ /dev/null
@@ -1,125 +0,0 @@
-//
-// detail/call_stack.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CALL_STACK_HPP
-#define ASIO_DETAIL_CALL_STACK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/tss_ptr.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Helper class to determine whether or not the current thread is inside an
-// invocation of io_context::run() for a specified io_context object.
-template <typename Key, typename Value = unsigned char>
-class call_stack
-{
-public:
-  // Context class automatically pushes the key/value pair on to the stack.
-  class context
-    : private noncopyable
-  {
-  public:
-    // Push the key on to the stack.
-    explicit context(Key* k)
-      : key_(k),
-        next_(call_stack<Key, Value>::top_)
-    {
-      value_ = reinterpret_cast<unsigned char*>(this);
-      call_stack<Key, Value>::top_ = this;
-    }
-
-    // Push the key/value pair on to the stack.
-    context(Key* k, Value& v)
-      : key_(k),
-        value_(&v),
-        next_(call_stack<Key, Value>::top_)
-    {
-      call_stack<Key, Value>::top_ = this;
-    }
-
-    // Pop the key/value pair from the stack.
-    ~context()
-    {
-      call_stack<Key, Value>::top_ = next_;
-    }
-
-    // Find the next context with the same key.
-    Value* next_by_key() const
-    {
-      context* elem = next_;
-      while (elem)
-      {
-        if (elem->key_ == key_)
-          return elem->value_;
-        elem = elem->next_;
-      }
-      return 0;
-    }
-
-  private:
-    friend class call_stack<Key, Value>;
-
-    // The key associated with the context.
-    Key* key_;
-
-    // The value associated with the context.
-    Value* value_;
-
-    // The next element in the stack.
-    context* next_;
-  };
-
-  friend class context;
-
-  // Determine whether the specified owner is on the stack. Returns address of
-  // key if present, 0 otherwise.
-  static Value* contains(Key* k)
-  {
-    context* elem = top_;
-    while (elem)
-    {
-      if (elem->key_ == k)
-        return elem->value_;
-      elem = elem->next_;
-    }
-    return 0;
-  }
-
-  // Obtain the value at the top of the stack.
-  static Value* top()
-  {
-    context* elem = top_;
-    return elem ? elem->value_ : 0;
-  }
-
-private:
-  // The top of the stack of calls for the current thread.
-  static tss_ptr<context> top_;
-};
-
-template <typename Key, typename Value>
-tss_ptr<typename call_stack<Key, Value>::context>
-call_stack<Key, Value>::top_;
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_CALL_STACK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/chrono.hpp b/tools/sdk/include/asio/asio/detail/chrono.hpp
deleted file mode 100644
index 8f56beed5fa..00000000000
--- a/tools/sdk/include/asio/asio/detail/chrono.hpp
+++ /dev/null
@@ -1,66 +0,0 @@
-//
-// detail/chrono.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CHRONO_HPP
-#define ASIO_DETAIL_CHRONO_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_CHRONO)
-# include <chrono>
-#elif defined(ASIO_HAS_BOOST_CHRONO)
-# include <boost/chrono/system_clocks.hpp>
-#endif // defined(ASIO_HAS_BOOST_CHRONO)
-
-namespace asio {
-namespace chrono {
-
-#if defined(ASIO_HAS_STD_CHRONO)
-using std::chrono::duration;
-using std::chrono::time_point;
-using std::chrono::duration_cast;
-using std::chrono::nanoseconds;
-using std::chrono::microseconds;
-using std::chrono::milliseconds;
-using std::chrono::seconds;
-using std::chrono::minutes;
-using std::chrono::hours;
-using std::chrono::time_point_cast;
-#if defined(ASIO_HAS_STD_CHRONO_MONOTONIC_CLOCK)
-typedef std::chrono::monotonic_clock steady_clock;
-#else // defined(ASIO_HAS_STD_CHRONO_MONOTONIC_CLOCK)
-using std::chrono::steady_clock;
-#endif // defined(ASIO_HAS_STD_CHRONO_MONOTONIC_CLOCK)
-using std::chrono::system_clock;
-using std::chrono::high_resolution_clock;
-#elif defined(ASIO_HAS_BOOST_CHRONO)
-using boost::chrono::duration;
-using boost::chrono::time_point;
-using boost::chrono::duration_cast;
-using boost::chrono::nanoseconds;
-using boost::chrono::microseconds;
-using boost::chrono::milliseconds;
-using boost::chrono::seconds;
-using boost::chrono::minutes;
-using boost::chrono::hours;
-using boost::chrono::time_point_cast;
-using boost::chrono::system_clock;
-using boost::chrono::steady_clock;
-using boost::chrono::high_resolution_clock;
-#endif // defined(ASIO_HAS_BOOST_CHRONO)
-
-} // namespace chrono
-} // namespace asio
-
-#endif // ASIO_DETAIL_CHRONO_HPP
diff --git a/tools/sdk/include/asio/asio/detail/chrono_time_traits.hpp b/tools/sdk/include/asio/asio/detail/chrono_time_traits.hpp
deleted file mode 100644
index d1528f70db3..00000000000
--- a/tools/sdk/include/asio/asio/detail/chrono_time_traits.hpp
+++ /dev/null
@@ -1,190 +0,0 @@
-//
-// detail/chrono_time_traits.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CHRONO_TIME_TRAITS_HPP
-#define ASIO_DETAIL_CHRONO_TIME_TRAITS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/cstdint.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Helper template to compute the greatest common divisor.
-template <int64_t v1, int64_t v2>
-struct gcd { enum { value = gcd<v2, v1 % v2>::value }; };
-
-template <int64_t v1>
-struct gcd<v1, 0> { enum { value = v1 }; };
-
-// Adapts std::chrono clocks for use with a deadline timer.
-template <typename Clock, typename WaitTraits>
-struct chrono_time_traits
-{
-  // The clock type.
-  typedef Clock clock_type;
-
-  // The duration type of the clock.
-  typedef typename clock_type::duration duration_type;
-
-  // The time point type of the clock.
-  typedef typename clock_type::time_point time_type;
-
-  // The period of the clock.
-  typedef typename duration_type::period period_type;
-
-  // Get the current time.
-  static time_type now()
-  {
-    return clock_type::now();
-  }
-
-  // Add a duration to a time.
-  static time_type add(const time_type& t, const duration_type& d)
-  {
-    const time_type epoch;
-    if (t >= epoch)
-    {
-      if ((time_type::max)() - t < d)
-        return (time_type::max)();
-    }
-    else // t < epoch
-    {
-      if (-(t - (time_type::min)()) > d)
-        return (time_type::min)();
-    }
-
-    return t + d;
-  }
-
-  // Subtract one time from another.
-  static duration_type subtract(const time_type& t1, const time_type& t2)
-  {
-    const time_type epoch;
-    if (t1 >= epoch)
-    {
-      if (t2 >= epoch)
-      {
-        return t1 - t2;
-      }
-      else if (t2 == (time_type::min)())
-      {
-        return (duration_type::max)();
-      }
-      else if ((time_type::max)() - t1 < epoch - t2)
-      {
-        return (duration_type::max)();
-      }
-      else
-      {
-        return t1 - t2;
-      }
-    }
-    else // t1 < epoch
-    {
-      if (t2 < epoch)
-      {
-        return t1 - t2;
-      }
-      else if (t1 == (time_type::min)())
-      {
-        return (duration_type::min)();
-      }
-      else if ((time_type::max)() - t2 < epoch - t1)
-      {
-        return (duration_type::min)();
-      }
-      else
-      {
-        return -(t2 - t1);
-      }
-    }
-  }
-
-  // Test whether one time is less than another.
-  static bool less_than(const time_type& t1, const time_type& t2)
-  {
-    return t1 < t2;
-  }
-
-  // Implement just enough of the posix_time::time_duration interface to supply
-  // what the timer_queue requires.
-  class posix_time_duration
-  {
-  public:
-    explicit posix_time_duration(const duration_type& d)
-      : d_(d)
-    {
-    }
-
-    int64_t ticks() const
-    {
-      return d_.count();
-    }
-
-    int64_t total_seconds() const
-    {
-      return duration_cast<1, 1>();
-    }
-
-    int64_t total_milliseconds() const
-    {
-      return duration_cast<1, 1000>();
-    }
-
-    int64_t total_microseconds() const
-    {
-      return duration_cast<1, 1000000>();
-    }
-
-  private:
-    template <int64_t Num, int64_t Den>
-    int64_t duration_cast() const
-    {
-      const int64_t num1 = period_type::num / gcd<period_type::num, Num>::value;
-      const int64_t num2 = Num / gcd<period_type::num, Num>::value;
-
-      const int64_t den1 = period_type::den / gcd<period_type::den, Den>::value;
-      const int64_t den2 = Den / gcd<period_type::den, Den>::value;
-
-      const int64_t num = num1 * den2;
-      const int64_t den = num2 * den1;
-
-      if (num == 1 && den == 1)
-        return ticks();
-      else if (num != 1 && den == 1)
-        return ticks() * num;
-      else if (num == 1 && period_type::den != 1)
-        return ticks() / den;
-      else
-        return ticks() * num / den;
-    }
-
-    duration_type d_;
-  };
-
-  // Convert to POSIX duration type.
-  static posix_time_duration to_posix_duration(const duration_type& d)
-  {
-    return posix_time_duration(WaitTraits::to_wait_duration(d));
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_CHRONO_TIME_TRAITS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/completion_handler.hpp b/tools/sdk/include/asio/asio/detail/completion_handler.hpp
deleted file mode 100644
index 58a2e6db984..00000000000
--- a/tools/sdk/include/asio/asio/detail/completion_handler.hpp
+++ /dev/null
@@ -1,83 +0,0 @@
-//
-// detail/completion_handler.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_COMPLETION_HANDLER_HPP
-#define ASIO_DETAIL_COMPLETION_HANDLER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_work.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class completion_handler : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(completion_handler);
-
-  completion_handler(Handler& h)
-    : operation(&completion_handler::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(h))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    completion_handler* h(static_cast<completion_handler*>(base));
-    ptr p = { asio::detail::addressof(h->handler_), h, h };
-    handler_work<Handler> w(h->handler_);
-
-    ASIO_HANDLER_COMPLETION((*h));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    Handler handler(ASIO_MOVE_CAST(Handler)(h->handler_));
-    p.h = asio::detail::addressof(handler);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN(());
-      w.complete(handler, handler);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_COMPLETION_HANDLER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/concurrency_hint.hpp b/tools/sdk/include/asio/asio/detail/concurrency_hint.hpp
deleted file mode 100644
index 229124d3765..00000000000
--- a/tools/sdk/include/asio/asio/detail/concurrency_hint.hpp
+++ /dev/null
@@ -1,94 +0,0 @@
-//
-// detail/concurrency_hint.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CONCURRENCY_HINT_HPP
-#define ASIO_DETAIL_CONCURRENCY_HINT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/noncopyable.hpp"
-
-// The concurrency hint ID and mask are used to identify when a "well-known"
-// concurrency hint value has been passed to the io_context.
-#define ASIO_CONCURRENCY_HINT_ID 0xA5100000u
-#define ASIO_CONCURRENCY_HINT_ID_MASK 0xFFFF0000u
-
-// If set, this bit indicates that the scheduler should perform locking.
-#define ASIO_CONCURRENCY_HINT_LOCKING_SCHEDULER 0x1u
-
-// If set, this bit indicates that the reactor should perform locking when
-// managing descriptor registrations.
-#define ASIO_CONCURRENCY_HINT_LOCKING_REACTOR_REGISTRATION 0x2u
-
-// If set, this bit indicates that the reactor should perform locking for I/O.
-#define ASIO_CONCURRENCY_HINT_LOCKING_REACTOR_IO 0x4u
-
-// Helper macro to determine if we have a special concurrency hint.
-#define ASIO_CONCURRENCY_HINT_IS_SPECIAL(hint) \
-  ((static_cast<unsigned>(hint) \
-    & ASIO_CONCURRENCY_HINT_ID_MASK) \
-      == ASIO_CONCURRENCY_HINT_ID)
-
-// Helper macro to determine if locking is enabled for a given facility.
-#define ASIO_CONCURRENCY_HINT_IS_LOCKING(facility, hint) \
-  (((static_cast<unsigned>(hint) \
-    & (ASIO_CONCURRENCY_HINT_ID_MASK \
-      | ASIO_CONCURRENCY_HINT_LOCKING_ ## facility)) \
-        ^ ASIO_CONCURRENCY_HINT_ID) != 0)
-
-// This special concurrency hint disables locking in both the scheduler and
-// reactor I/O. This hint has the following restrictions:
-//
-// - Care must be taken to ensure that all operations on the io_context and any
-//   of its associated I/O objects (such as sockets and timers) occur in only
-//   one thread at a time.
-//
-// - Asynchronous resolve operations fail with operation_not_supported.
-//
-// - If a signal_set is used with the io_context, signal_set objects cannot be
-//   used with any other io_context in the program.
-#define ASIO_CONCURRENCY_HINT_UNSAFE \
-  static_cast<int>(ASIO_CONCURRENCY_HINT_ID)
-
-// This special concurrency hint disables locking in the reactor I/O. This hint
-// has the following restrictions:
-//
-// - Care must be taken to ensure that run functions on the io_context, and all
-//   operations on the io_context's associated I/O objects (such as sockets and
-//   timers), occur in only one thread at a time.
-#define ASIO_CONCURRENCY_HINT_UNSAFE_IO \
-  static_cast<int>(ASIO_CONCURRENCY_HINT_ID \
-      | ASIO_CONCURRENCY_HINT_LOCKING_SCHEDULER \
-      | ASIO_CONCURRENCY_HINT_LOCKING_REACTOR_REGISTRATION)
-
-// The special concurrency hint provides full thread safety.
-#define ASIO_CONCURRENCY_HINT_SAFE \
-  static_cast<int>(ASIO_CONCURRENCY_HINT_ID \
-      | ASIO_CONCURRENCY_HINT_LOCKING_SCHEDULER \
-      | ASIO_CONCURRENCY_HINT_LOCKING_REACTOR_REGISTRATION \
-      | ASIO_CONCURRENCY_HINT_LOCKING_REACTOR_IO)
-
-// This #define may be overridden at compile time to specify a program-wide
-// default concurrency hint, used by the zero-argument io_context constructor.
-#if !defined(ASIO_CONCURRENCY_HINT_DEFAULT)
-# define ASIO_CONCURRENCY_HINT_DEFAULT -1
-#endif // !defined(ASIO_CONCURRENCY_HINT_DEFAULT)
-
-// This #define may be overridden at compile time to specify a program-wide
-// concurrency hint, used by the one-argument io_context constructor when
-// passed a value of 1.
-#if !defined(ASIO_CONCURRENCY_HINT_1)
-# define ASIO_CONCURRENCY_HINT_1 1
-#endif // !defined(ASIO_CONCURRENCY_HINT_DEFAULT)
-
-#endif // ASIO_DETAIL_CONCURRENCY_HINT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/conditionally_enabled_event.hpp b/tools/sdk/include/asio/asio/detail/conditionally_enabled_event.hpp
deleted file mode 100644
index 0fda401e3bb..00000000000
--- a/tools/sdk/include/asio/asio/detail/conditionally_enabled_event.hpp
+++ /dev/null
@@ -1,112 +0,0 @@
-//
-// detail/conditionally_enabled_event.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CONDITIONALLY_ENABLED_EVENT_HPP
-#define ASIO_DETAIL_CONDITIONALLY_ENABLED_EVENT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/conditionally_enabled_mutex.hpp"
-#include "asio/detail/event.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/null_event.hpp"
-#include "asio/detail/scoped_lock.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Mutex adapter used to conditionally enable or disable locking.
-class conditionally_enabled_event
-  : private noncopyable
-{
-public:
-  // Constructor.
-  conditionally_enabled_event()
-  {
-  }
-
-  // Destructor.
-  ~conditionally_enabled_event()
-  {
-  }
-
-  // Signal the event. (Retained for backward compatibility.)
-  void signal(conditionally_enabled_mutex::scoped_lock& lock)
-  {
-    if (lock.mutex_.enabled_)
-      event_.signal(lock);
-  }
-
-  // Signal all waiters.
-  void signal_all(conditionally_enabled_mutex::scoped_lock& lock)
-  {
-    if (lock.mutex_.enabled_)
-      event_.signal_all(lock);
-  }
-
-  // Unlock the mutex and signal one waiter.
-  void unlock_and_signal_one(
-      conditionally_enabled_mutex::scoped_lock& lock)
-  {
-    if (lock.mutex_.enabled_)
-      event_.unlock_and_signal_one(lock);
-  }
-
-  // If there's a waiter, unlock the mutex and signal it.
-  bool maybe_unlock_and_signal_one(
-      conditionally_enabled_mutex::scoped_lock& lock)
-  {
-    if (lock.mutex_.enabled_)
-      return event_.maybe_unlock_and_signal_one(lock);
-    else
-      return false;
-  }
-
-  // Reset the event.
-  void clear(conditionally_enabled_mutex::scoped_lock& lock)
-  {
-    if (lock.mutex_.enabled_)
-      event_.clear(lock);
-  }
-
-  // Wait for the event to become signalled.
-  void wait(conditionally_enabled_mutex::scoped_lock& lock)
-  {
-    if (lock.mutex_.enabled_)
-      event_.wait(lock);
-    else
-      null_event().wait(lock);
-  }
-
-  // Timed wait for the event to become signalled.
-  bool wait_for_usec(
-      conditionally_enabled_mutex::scoped_lock& lock, long usec)
-  {
-    if (lock.mutex_.enabled_)
-      return event_.wait_for_usec(lock, usec);
-    else
-      return null_event().wait_for_usec(lock, usec);
-  }
-
-private:
-  asio::detail::event event_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_CONDITIONALLY_ENABLED_EVENT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/conditionally_enabled_mutex.hpp b/tools/sdk/include/asio/asio/detail/conditionally_enabled_mutex.hpp
deleted file mode 100644
index 2872db98be9..00000000000
--- a/tools/sdk/include/asio/asio/detail/conditionally_enabled_mutex.hpp
+++ /dev/null
@@ -1,149 +0,0 @@
-//
-// detail/conditionally_enabled_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CONDITIONALLY_ENABLED_MUTEX_HPP
-#define ASIO_DETAIL_CONDITIONALLY_ENABLED_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/scoped_lock.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Mutex adapter used to conditionally enable or disable locking.
-class conditionally_enabled_mutex
-  : private noncopyable
-{
-public:
-  // Helper class to lock and unlock a mutex automatically.
-  class scoped_lock
-    : private noncopyable
-  {
-  public:
-    // Tag type used to distinguish constructors.
-    enum adopt_lock_t { adopt_lock };
-
-    // Constructor adopts a lock that is already held.
-    scoped_lock(conditionally_enabled_mutex& m, adopt_lock_t)
-      : mutex_(m),
-        locked_(m.enabled_)
-    {
-    }
-
-    // Constructor acquires the lock.
-    explicit scoped_lock(conditionally_enabled_mutex& m)
-      : mutex_(m)
-    {
-      if (m.enabled_)
-      {
-        mutex_.mutex_.lock();
-        locked_ = true;
-      }
-      else
-        locked_ = false;
-    }
-
-    // Destructor releases the lock.
-    ~scoped_lock()
-    {
-      if (locked_)
-        mutex_.mutex_.unlock();
-    }
-
-    // Explicitly acquire the lock.
-    void lock()
-    {
-      if (mutex_.enabled_ && !locked_)
-      {
-        mutex_.mutex_.lock();
-        locked_ = true;
-      }
-    }
-
-    // Explicitly release the lock.
-    void unlock()
-    {
-      if (locked_)
-      {
-        mutex_.unlock();
-        locked_ = false;
-      }
-    }
-
-    // Test whether the lock is held.
-    bool locked() const
-    {
-      return locked_;
-    }
-
-    // Get the underlying mutex.
-    asio::detail::mutex& mutex()
-    {
-      return mutex_.mutex_;
-    }
-
-  private:
-    friend class conditionally_enabled_event;
-    conditionally_enabled_mutex& mutex_;
-    bool locked_;
-  };
-
-  // Constructor.
-  explicit conditionally_enabled_mutex(bool enabled)
-    : enabled_(enabled)
-  {
-  }
-
-  // Destructor.
-  ~conditionally_enabled_mutex()
-  {
-  }
-
-  // Determine whether locking is enabled.
-  bool enabled() const
-  {
-    return enabled_;
-  }
-
-  // Lock the mutex.
-  void lock()
-  {
-    if (enabled_)
-      mutex_.lock();
-  }
-
-  // Unlock the mutex.
-  void unlock()
-  {
-    if (enabled_)
-      mutex_.unlock();
-  }
-
-private:
-  friend class scoped_lock;
-  friend class conditionally_enabled_event;
-  asio::detail::mutex mutex_;
-  const bool enabled_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_CONDITIONALLY_ENABLED_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/config.hpp b/tools/sdk/include/asio/asio/detail/config.hpp
deleted file mode 100644
index 949d67f2a87..00000000000
--- a/tools/sdk/include/asio/asio/detail/config.hpp
+++ /dev/null
@@ -1,1441 +0,0 @@
-//
-// detail/config.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CONFIG_HPP
-#define ASIO_DETAIL_CONFIG_HPP
-
-#if defined(ESP_PLATFORM)
-# include "esp_asio_config.h"
-#endif // defined(ESP_PLATFORM)
-
-#if defined(ASIO_STANDALONE)
-# define ASIO_DISABLE_BOOST_ARRAY 1
-# define ASIO_DISABLE_BOOST_ASSERT 1
-# define ASIO_DISABLE_BOOST_BIND 1
-# define ASIO_DISABLE_BOOST_CHRONO 1
-# define ASIO_DISABLE_BOOST_DATE_TIME 1
-# define ASIO_DISABLE_BOOST_LIMITS 1
-# define ASIO_DISABLE_BOOST_REGEX 1
-# define ASIO_DISABLE_BOOST_STATIC_CONSTANT 1
-# define ASIO_DISABLE_BOOST_THROW_EXCEPTION 1
-# define ASIO_DISABLE_BOOST_WORKAROUND 1
-#else // defined(ASIO_STANDALONE)
-# include <boost/config.hpp>
-# include <boost/version.hpp>
-# define ASIO_HAS_BOOST_CONFIG 1
-#endif // defined(ASIO_STANDALONE)
-
-// Default to a header-only implementation. The user must specifically request
-// separate compilation by defining either ASIO_SEPARATE_COMPILATION or
-// ASIO_DYN_LINK (as a DLL/shared library implies separate compilation).
-#if !defined(ASIO_HEADER_ONLY)
-# if !defined(ASIO_SEPARATE_COMPILATION)
-#  if !defined(ASIO_DYN_LINK)
-#   define ASIO_HEADER_ONLY 1
-#  endif // !defined(ASIO_DYN_LINK)
-# endif // !defined(ASIO_SEPARATE_COMPILATION)
-#endif // !defined(ASIO_HEADER_ONLY)
-
-#if defined(ASIO_HEADER_ONLY)
-# define ASIO_DECL inline
-#else // defined(ASIO_HEADER_ONLY)
-# if defined(_MSC_VER) || defined(__BORLANDC__) || defined(__CODEGEARC__)
-// We need to import/export our code only if the user has specifically asked
-// for it by defining ASIO_DYN_LINK.
-#  if defined(ASIO_DYN_LINK)
-// Export if this is our own source, otherwise import.
-#   if defined(ASIO_SOURCE)
-#    define ASIO_DECL __declspec(dllexport)
-#   else // defined(ASIO_SOURCE)
-#    define ASIO_DECL __declspec(dllimport)
-#   endif // defined(ASIO_SOURCE)
-#  endif // defined(ASIO_DYN_LINK)
-# endif // defined(_MSC_VER) || defined(__BORLANDC__) || defined(__CODEGEARC__)
-#endif // defined(ASIO_HEADER_ONLY)
-
-// If ASIO_DECL isn't defined yet define it now.
-#if !defined(ASIO_DECL)
-# define ASIO_DECL
-#endif // !defined(ASIO_DECL)
-
-// Microsoft Visual C++ detection.
-#if !defined(ASIO_MSVC)
-# if defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_MSVC)
-#  define ASIO_MSVC BOOST_MSVC
-# elif defined(_MSC_VER) && (defined(__INTELLISENSE__) \
-      || (!defined(__MWERKS__) && !defined(__EDG_VERSION__)))
-#  define ASIO_MSVC _MSC_VER
-# endif // defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_MSVC)
-#endif // !defined(ASIO_MSVC)
-#if defined(ASIO_MSVC)
-# include <ciso646> // Needed for _HAS_CXX17.
-#endif // defined(ASIO_MSVC)
-
-// Clang / libc++ detection.
-#if defined(__clang__)
-# if (__cplusplus >= 201103)
-#  if __has_include(<__config>)
-#   include <__config>
-#   if defined(_LIBCPP_VERSION)
-#    define ASIO_HAS_CLANG_LIBCXX 1
-#   endif // defined(_LIBCPP_VERSION)
-#  endif // __has_include(<__config>)
-# endif // (__cplusplus >= 201103)
-#endif // defined(__clang__)
-
-// Android platform detection.
-#if defined(__ANDROID__)
-# include <android/api-level.h>
-#endif // defined(__ANDROID__)
-
-// Support move construction and assignment on compilers known to allow it.
-#if !defined(ASIO_HAS_MOVE)
-# if !defined(ASIO_DISABLE_MOVE)
-#  if defined(__clang__)
-#   if __has_feature(__cxx_rvalue_references__)
-#    define ASIO_HAS_MOVE 1
-#   endif // __has_feature(__cxx_rvalue_references__)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_MOVE 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_MOVE 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_MOVE)
-#endif // !defined(ASIO_HAS_MOVE)
-
-// If ASIO_MOVE_CAST isn't defined, and move support is available, define
-// ASIO_MOVE_ARG and ASIO_MOVE_CAST to take advantage of rvalue
-// references and perfect forwarding.
-#if defined(ASIO_HAS_MOVE) && !defined(ASIO_MOVE_CAST)
-# define ASIO_MOVE_ARG(type) type&&
-# define ASIO_MOVE_ARG2(type1, type2) type1, type2&&
-# define ASIO_MOVE_CAST(type) static_cast<type&&>
-# define ASIO_MOVE_CAST2(type1, type2) static_cast<type1, type2&&>
-#endif // defined(ASIO_HAS_MOVE) && !defined(ASIO_MOVE_CAST)
-
-// If ASIO_MOVE_CAST still isn't defined, default to a C++03-compatible
-// implementation. Note that older g++ and MSVC versions don't like it when you
-// pass a non-member function through a const reference, so for most compilers
-// we'll play it safe and stick with the old approach of passing the handler by
-// value.
-#if !defined(ASIO_MOVE_CAST)
-# if defined(__GNUC__)
-#  if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)) || (__GNUC__ > 4)
-#   define ASIO_MOVE_ARG(type) const type&
-#  else // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)) || (__GNUC__ > 4)
-#   define ASIO_MOVE_ARG(type) type
-#  endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 1)) || (__GNUC__ > 4)
-# elif defined(ASIO_MSVC)
-#  if (_MSC_VER >= 1400)
-#   define ASIO_MOVE_ARG(type) const type&
-#  else // (_MSC_VER >= 1400)
-#   define ASIO_MOVE_ARG(type) type
-#  endif // (_MSC_VER >= 1400)
-# else
-#  define ASIO_MOVE_ARG(type) type
-# endif
-# define ASIO_MOVE_CAST(type) static_cast<const type&>
-# define ASIO_MOVE_CAST2(type1, type2) static_cast<const type1, type2&>
-#endif // !defined(ASIO_MOVE_CAST)
-
-// Support variadic templates on compilers known to allow it.
-#if !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-# if !defined(ASIO_DISABLE_VARIADIC_TEMPLATES)
-#  if defined(__clang__)
-#   if __has_feature(__cxx_variadic_templates__)
-#    define ASIO_HAS_VARIADIC_TEMPLATES 1
-#   endif // __has_feature(__cxx_variadic_templates__)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_VARIADIC_TEMPLATES 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1900)
-#    define ASIO_HAS_VARIADIC_TEMPLATES 1
-#   endif // (_MSC_VER >= 1900)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_VARIADIC_TEMPLATES)
-#endif // !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-// Support deleted functions on compilers known to allow it.
-#if !defined(ASIO_DELETED)
-# if defined(__GNUC__)
-#  if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#   if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#    define ASIO_DELETED = delete
-#   endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#  endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-# endif // defined(__GNUC__)
-# if defined(__clang__)
-#  if __has_feature(__cxx_deleted_functions__)
-#   define ASIO_DELETED = delete
-#  endif // __has_feature(__cxx_deleted_functions__)
-# endif // defined(__clang__)
-# if defined(ASIO_MSVC)
-#  if (_MSC_VER >= 1900)
-#   define ASIO_DELETED = delete
-#  endif // (_MSC_VER >= 1900)
-# endif // defined(ASIO_MSVC)
-# if !defined(ASIO_DELETED)
-#  define ASIO_DELETED
-# endif // !defined(ASIO_DELETED)
-#endif // !defined(ASIO_DELETED)
-
-// Support constexpr on compilers known to allow it.
-#if !defined(ASIO_HAS_CONSTEXPR)
-# if !defined(ASIO_DISABLE_CONSTEXPR)
-#  if defined(__clang__)
-#   if __has_feature(__cxx_constexpr__)
-#    define ASIO_HAS_CONSTEXPR 1
-#   endif // __has_feature(__cxx_constexr__)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_CONSTEXPR 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1900)
-#    define ASIO_HAS_CONSTEXPR 1
-#   endif // (_MSC_VER >= 1900)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_CONSTEXPR)
-#endif // !defined(ASIO_HAS_CONSTEXPR)
-#if !defined(ASIO_CONSTEXPR)
-# if defined(ASIO_HAS_CONSTEXPR)
-#  define ASIO_CONSTEXPR constexpr
-# else // defined(ASIO_HAS_CONSTEXPR)
-#  define ASIO_CONSTEXPR
-# endif // defined(ASIO_HAS_CONSTEXPR)
-#endif // !defined(ASIO_CONSTEXPR)
-
-// Support noexcept on compilers known to allow it.
-#if !defined(ASIO_NOEXCEPT)
-# if !defined(ASIO_DISABLE_NOEXCEPT)
-#  if (BOOST_VERSION >= 105300)
-#   define ASIO_NOEXCEPT BOOST_NOEXCEPT
-#   define ASIO_NOEXCEPT_OR_NOTHROW BOOST_NOEXCEPT_OR_NOTHROW
-#  elif defined(__clang__)
-#   if __has_feature(__cxx_noexcept__)
-#    define ASIO_NOEXCEPT noexcept(true)
-#    define ASIO_NOEXCEPT_OR_NOTHROW noexcept(true)
-#   endif // __has_feature(__cxx_noexcept__)
-#  elif defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#      define ASIO_NOEXCEPT noexcept(true)
-#      define ASIO_NOEXCEPT_OR_NOTHROW noexcept(true)
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#  elif defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1900)
-#    define ASIO_NOEXCEPT noexcept(true)
-#    define ASIO_NOEXCEPT_OR_NOTHROW noexcept(true)
-#   endif // (_MSC_VER >= 1900)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_NOEXCEPT)
-# if !defined(ASIO_NOEXCEPT)
-#  define ASIO_NOEXCEPT
-# endif // !defined(ASIO_NOEXCEPT)
-# if !defined(ASIO_NOEXCEPT_OR_NOTHROW)
-#  define ASIO_NOEXCEPT_OR_NOTHROW throw()
-# endif // !defined(ASIO_NOEXCEPT_OR_NOTHROW)
-#endif // !defined(ASIO_NOEXCEPT)
-
-// Support automatic type deduction on compilers known to support it.
-#if !defined(ASIO_HAS_DECLTYPE)
-# if !defined(ASIO_DISABLE_DECLTYPE)
-#  if defined(__clang__)
-#   if __has_feature(__cxx_decltype__)
-#    define ASIO_HAS_DECLTYPE 1
-#   endif // __has_feature(__cxx_decltype__)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_DECLTYPE 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_DECLTYPE 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_DECLTYPE)
-#endif // !defined(ASIO_HAS_DECLTYPE)
-
-// Support alias templates on compilers known to allow it.
-#if !defined(ASIO_HAS_ALIAS_TEMPLATES)
-# if !defined(ASIO_DISABLE_ALIAS_TEMPLATES)
-#  if defined(__clang__)
-#   if __has_feature(__cxx_alias_templates__)
-#    define ASIO_HAS_ALIAS_TEMPLATES 1
-#   endif // __has_feature(__cxx_alias_templates__)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_ALIAS_TEMPLATES 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1900)
-#    define ASIO_HAS_ALIAS_TEMPLATES 1
-#   endif // (_MSC_VER >= 1900)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_ALIAS_TEMPLATES)
-#endif // !defined(ASIO_HAS_ALIAS_TEMPLATES)
-
-// Standard library support for system errors.
-#if !defined(ASIO_HAS_STD_SYSTEM_ERROR)
-# if !defined(ASIO_DISABLE_STD_SYSTEM_ERROR)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_SYSTEM_ERROR 1
-#   elif (__cplusplus >= 201103)
-#    if __has_include(<system_error>)
-#     define ASIO_HAS_STD_SYSTEM_ERROR 1
-#    endif // __has_include(<system_error>)
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_SYSTEM_ERROR 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_SYSTEM_ERROR 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_SYSTEM_ERROR)
-#endif // !defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-// Compliant C++11 compilers put noexcept specifiers on error_category members.
-#if !defined(ASIO_ERROR_CATEGORY_NOEXCEPT)
-# if (BOOST_VERSION >= 105300)
-#  define ASIO_ERROR_CATEGORY_NOEXCEPT BOOST_NOEXCEPT
-# elif defined(__clang__)
-#  if __has_feature(__cxx_noexcept__)
-#   define ASIO_ERROR_CATEGORY_NOEXCEPT noexcept(true)
-#  endif // __has_feature(__cxx_noexcept__)
-# elif defined(__GNUC__)
-#  if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#   if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_ERROR_CATEGORY_NOEXCEPT noexcept(true)
-#   endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#  endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-# elif defined(ASIO_MSVC)
-#  if (_MSC_VER >= 1900)
-#   define ASIO_ERROR_CATEGORY_NOEXCEPT noexcept(true)
-#  endif // (_MSC_VER >= 1900)
-# endif // defined(ASIO_MSVC)
-# if !defined(ASIO_ERROR_CATEGORY_NOEXCEPT)
-#  define ASIO_ERROR_CATEGORY_NOEXCEPT
-# endif // !defined(ASIO_ERROR_CATEGORY_NOEXCEPT)
-#endif // !defined(ASIO_ERROR_CATEGORY_NOEXCEPT)
-
-// Standard library support for arrays.
-#if !defined(ASIO_HAS_STD_ARRAY)
-# if !defined(ASIO_DISABLE_STD_ARRAY)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_ARRAY 1
-#   elif (__cplusplus >= 201103)
-#    if __has_include(<array>)
-#     define ASIO_HAS_STD_ARRAY 1
-#    endif // __has_include(<array>)
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_ARRAY 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1600)
-#    define ASIO_HAS_STD_ARRAY 1
-#   endif // (_MSC_VER >= 1600)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_ARRAY)
-#endif // !defined(ASIO_HAS_STD_ARRAY)
-
-// Standard library support for shared_ptr and weak_ptr.
-#if !defined(ASIO_HAS_STD_SHARED_PTR)
-# if !defined(ASIO_DISABLE_STD_SHARED_PTR)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_SHARED_PTR 1
-#   elif (__cplusplus >= 201103)
-#    define ASIO_HAS_STD_SHARED_PTR 1
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_SHARED_PTR 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1600)
-#    define ASIO_HAS_STD_SHARED_PTR 1
-#   endif // (_MSC_VER >= 1600)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_SHARED_PTR)
-#endif // !defined(ASIO_HAS_STD_SHARED_PTR)
-
-// Standard library support for allocator_arg_t.
-#if !defined(ASIO_HAS_STD_ALLOCATOR_ARG)
-# if !defined(ASIO_DISABLE_STD_ALLOCATOR_ARG)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_ALLOCATOR_ARG 1
-#   elif (__cplusplus >= 201103)
-#    define ASIO_HAS_STD_ALLOCATOR_ARG 1
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_ALLOCATOR_ARG 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1600)
-#    define ASIO_HAS_STD_ALLOCATOR_ARG 1
-#   endif // (_MSC_VER >= 1600)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_ALLOCATOR_ARG)
-#endif // !defined(ASIO_HAS_STD_ALLOCATOR_ARG)
-
-// Standard library support for atomic operations.
-#if !defined(ASIO_HAS_STD_ATOMIC)
-# if !defined(ASIO_DISABLE_STD_ATOMIC)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_ATOMIC 1
-#   elif (__cplusplus >= 201103)
-#    if __has_include(<atomic>)
-#     define ASIO_HAS_STD_ATOMIC 1
-#    endif // __has_include(<atomic>)
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_ATOMIC 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_ATOMIC 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_ATOMIC)
-#endif // !defined(ASIO_HAS_STD_ATOMIC)
-
-// Standard library support for chrono. Some standard libraries (such as the
-// libstdc++ shipped with gcc 4.6) provide monotonic_clock as per early C++0x
-// drafts, rather than the eventually standardised name of steady_clock.
-#if !defined(ASIO_HAS_STD_CHRONO)
-# if !defined(ASIO_DISABLE_STD_CHRONO)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_CHRONO 1
-#   elif (__cplusplus >= 201103)
-#    if __has_include(<chrono>)
-#     define ASIO_HAS_STD_CHRONO 1
-#    endif // __has_include(<chrono>)
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_CHRONO 1
-#     if ((__GNUC__ == 4) && (__GNUC_MINOR__ == 6))
-#      define ASIO_HAS_STD_CHRONO_MONOTONIC_CLOCK 1
-#     endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ == 6))
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_CHRONO 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_CHRONO)
-#endif // !defined(ASIO_HAS_STD_CHRONO)
-
-// Boost support for chrono.
-#if !defined(ASIO_HAS_BOOST_CHRONO)
-# if !defined(ASIO_DISABLE_BOOST_CHRONO)
-#  if (BOOST_VERSION >= 104700)
-#   define ASIO_HAS_BOOST_CHRONO 1
-#  endif // (BOOST_VERSION >= 104700)
-# endif // !defined(ASIO_DISABLE_BOOST_CHRONO)
-#endif // !defined(ASIO_HAS_BOOST_CHRONO)
-
-// Some form of chrono library is available.
-#if !defined(ASIO_HAS_CHRONO)
-# if defined(ASIO_HAS_STD_CHRONO) \
-    || defined(ASIO_HAS_BOOST_CHRONO)
-#  define ASIO_HAS_CHRONO 1
-# endif // defined(ASIO_HAS_STD_CHRONO)
-        // || defined(ASIO_HAS_BOOST_CHRONO)
-#endif // !defined(ASIO_HAS_CHRONO)
-
-// Boost support for the DateTime library.
-#if !defined(ASIO_HAS_BOOST_DATE_TIME)
-# if !defined(ASIO_DISABLE_BOOST_DATE_TIME)
-#  define ASIO_HAS_BOOST_DATE_TIME 1
-# endif // !defined(ASIO_DISABLE_BOOST_DATE_TIME)
-#endif // !defined(ASIO_HAS_BOOST_DATE_TIME)
-
-// Standard library support for addressof.
-#if !defined(ASIO_HAS_STD_ADDRESSOF)
-# if !defined(ASIO_DISABLE_STD_ADDRESSOF)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_ADDRESSOF 1
-#   elif (__cplusplus >= 201103)
-#    define ASIO_HAS_STD_ADDRESSOF 1
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_ADDRESSOF 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_ADDRESSOF 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_ADDRESSOF)
-#endif // !defined(ASIO_HAS_STD_ADDRESSOF)
-
-// Standard library support for the function class.
-#if !defined(ASIO_HAS_STD_FUNCTION)
-# if !defined(ASIO_DISABLE_STD_FUNCTION)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_FUNCTION 1
-#   elif (__cplusplus >= 201103)
-#    define ASIO_HAS_STD_FUNCTION 1
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_FUNCTION 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_FUNCTION 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_FUNCTION)
-#endif // !defined(ASIO_HAS_STD_FUNCTION)
-
-// Standard library support for type traits.
-#if !defined(ASIO_HAS_STD_TYPE_TRAITS)
-# if !defined(ASIO_DISABLE_STD_TYPE_TRAITS)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_TYPE_TRAITS 1
-#   elif (__cplusplus >= 201103)
-#    if __has_include(<type_traits>)
-#     define ASIO_HAS_STD_TYPE_TRAITS 1
-#    endif // __has_include(<type_traits>)
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_TYPE_TRAITS 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_TYPE_TRAITS 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_TYPE_TRAITS)
-#endif // !defined(ASIO_HAS_STD_TYPE_TRAITS)
-
-// Standard library support for the nullptr_t type.
-#if !defined(ASIO_HAS_NULLPTR)
-# if !defined(ASIO_DISABLE_NULLPTR)
-#  if defined(__clang__)
-#   if __has_feature(__cxx_nullptr__)
-#    define ASIO_HAS_NULLPTR 1
-#   endif // __has_feature(__cxx_rvalue_references__)
-#  elif defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_NULLPTR 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 6)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_NULLPTR 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_NULLPTR)
-#endif // !defined(ASIO_HAS_NULLPTR)
-
-// Standard library support for the C++11 allocator additions.
-#if !defined(ASIO_HAS_CXX11_ALLOCATORS)
-# if !defined(ASIO_DISABLE_CXX11_ALLOCATORS)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_CXX11_ALLOCATORS 1
-#   elif (__cplusplus >= 201103)
-#    define ASIO_HAS_CXX11_ALLOCATORS 1
-#   endif // (__cplusplus >= 201103)
-#  elif defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_CXX11_ALLOCATORS 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1800)
-#    define ASIO_HAS_CXX11_ALLOCATORS 1
-#   endif // (_MSC_VER >= 1800)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_CXX11_ALLOCATORS)
-#endif // !defined(ASIO_HAS_CXX11_ALLOCATORS)
-
-// Standard library support for the cstdint header.
-#if !defined(ASIO_HAS_CSTDINT)
-# if !defined(ASIO_DISABLE_CSTDINT)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_CSTDINT 1
-#   elif (__cplusplus >= 201103)
-#    define ASIO_HAS_CSTDINT 1
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_CSTDINT 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_CSTDINT 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_CSTDINT)
-#endif // !defined(ASIO_HAS_CSTDINT)
-
-// Standard library support for the thread class.
-#if !defined(ASIO_HAS_STD_THREAD)
-# if !defined(ASIO_DISABLE_STD_THREAD)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_THREAD 1
-#   elif (__cplusplus >= 201103)
-#    if __has_include(<thread>)
-#     define ASIO_HAS_STD_THREAD 1
-#    endif // __has_include(<thread>)
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_THREAD 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_THREAD 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_THREAD)
-#endif // !defined(ASIO_HAS_STD_THREAD)
-
-// Standard library support for the mutex and condition variable classes.
-#if !defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-# if !defined(ASIO_DISABLE_STD_MUTEX_AND_CONDVAR)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_MUTEX_AND_CONDVAR 1
-#   elif (__cplusplus >= 201103)
-#    if __has_include(<mutex>)
-#     define ASIO_HAS_STD_MUTEX_AND_CONDVAR 1
-#    endif // __has_include(<mutex>)
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_MUTEX_AND_CONDVAR 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_MUTEX_AND_CONDVAR 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_MUTEX_AND_CONDVAR)
-#endif // !defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-
-// Standard library support for the call_once function.
-#if !defined(ASIO_HAS_STD_CALL_ONCE)
-# if !defined(ASIO_DISABLE_STD_CALL_ONCE)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_CALL_ONCE 1
-#   elif (__cplusplus >= 201103)
-#    if __has_include(<mutex>)
-#     define ASIO_HAS_STD_CALL_ONCE 1
-#    endif // __has_include(<mutex>)
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_CALL_ONCE 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_CALL_ONCE 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_CALL_ONCE)
-#endif // !defined(ASIO_HAS_STD_CALL_ONCE)
-
-// Standard library support for futures.
-#if !defined(ASIO_HAS_STD_FUTURE)
-# if !defined(ASIO_DISABLE_STD_FUTURE)
-#  if defined(__clang__)
-#   if defined(ASIO_HAS_CLANG_LIBCXX)
-#    define ASIO_HAS_STD_FUTURE 1
-#   elif (__cplusplus >= 201103)
-#    if __has_include(<future>)
-#     define ASIO_HAS_STD_FUTURE 1
-#    endif // __has_include(<mutex>)
-#   endif // (__cplusplus >= 201103)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     if defined(_GLIBCXX_HAS_GTHREADS)
-#      define ASIO_HAS_STD_FUTURE 1
-#     endif // defined(_GLIBCXX_HAS_GTHREADS)
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 7)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_FUTURE 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_FUTURE)
-#endif // !defined(ASIO_HAS_STD_FUTURE)
-
-// Standard library support for std::string_view.
-#if !defined(ASIO_HAS_STD_STRING_VIEW)
-# if !defined(ASIO_DISABLE_STD_STRING_VIEW)
-#  if defined(__clang__)
-#   if (__cplusplus >= 201703)
-#    if __has_include(<string_view>)
-#     define ASIO_HAS_STD_STRING_VIEW 1
-#    endif // __has_include(<string_view>)
-#   endif // (__cplusplus >= 201703)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if (__GNUC__ >= 7)
-#    if (__cplusplus >= 201703)
-#     define ASIO_HAS_STD_STRING_VIEW 1
-#    endif // (__cplusplus >= 201703)
-#   endif // (__GNUC__ >= 7)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1910 && _HAS_CXX17)
-#    define ASIO_HAS_STD_STRING_VIEW
-#   endif // (_MSC_VER >= 1910 && _HAS_CXX17)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_STRING_VIEW)
-#endif // !defined(ASIO_HAS_STD_STRING_VIEW)
-
-// Standard library support for std::experimental::string_view.
-#if !defined(ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW)
-# if !defined(ASIO_DISABLE_STD_EXPERIMENTAL_STRING_VIEW)
-#  if defined(__clang__)
-#   if (__cplusplus >= 201402)
-#    if __has_include(<experimental/string_view>)
-#     define ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW 1
-#    endif // __has_include(<experimental/string_view>)
-#   endif // (__cplusplus >= 201402)
-#  endif // defined(__clang__)
-#  if defined(__GNUC__)
-#   if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 9)) || (__GNUC__ > 4)
-#    if (__cplusplus >= 201402)
-#     define ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW 1
-#    endif // (__cplusplus >= 201402)
-#   endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 9)) || (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-# endif // !defined(ASIO_DISABLE_STD_EXPERIMENTAL_STRING_VIEW)
-#endif // !defined(ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW)
-
-// Standard library has a string_view that we can use.
-#if !defined(ASIO_HAS_STRING_VIEW)
-# if !defined(ASIO_DISABLE_STRING_VIEW)
-#  if defined(ASIO_HAS_STD_STRING_VIEW)
-#   define ASIO_HAS_STRING_VIEW 1
-#  elif defined(ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW)
-#   define ASIO_HAS_STRING_VIEW 1
-#  endif // defined(ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW)
-# endif // !defined(ASIO_DISABLE_STRING_VIEW)
-#endif // !defined(ASIO_HAS_STRING_VIEW)
-
-// Standard library support for iostream move construction and assignment.
-#if !defined(ASIO_HAS_STD_IOSTREAM_MOVE)
-# if !defined(ASIO_DISABLE_STD_IOSTREAM_MOVE)
-#  if defined(__GNUC__)
-#   if (__GNUC__ > 4)
-#    if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#     define ASIO_HAS_STD_IOSTREAM_MOVE 1
-#    endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#   endif // (__GNUC__ > 4)
-#  endif // defined(__GNUC__)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1700)
-#    define ASIO_HAS_STD_IOSTREAM_MOVE 1
-#   endif // (_MSC_VER >= 1700)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_IOSTREAM_MOVE)
-#endif // !defined(ASIO_HAS_STD_IOSTREAM_MOVE)
-
-// Standard library has invoke_result (which supersedes result_of).
-#if !defined(ASIO_HAS_STD_INVOKE_RESULT)
-# if !defined(ASIO_DISABLE_STD_INVOKE_RESULT)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_VER >= 1910 && _HAS_CXX17)
-#    define ASIO_HAS_STD_INVOKE_RESULT 1
-#   endif // (_MSC_VER >= 1910 && _HAS_CXX17)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_STD_INVOKE_RESULT)
-#endif // !defined(ASIO_HAS_STD_INVOKE_RESULT)
-
-// Windows App target. Windows but with a limited API.
-#if !defined(ASIO_WINDOWS_APP)
-# if defined(_WIN32_WINNT) && (_WIN32_WINNT >= 0x0603)
-#  include <winapifamily.h>
-#  if WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_APP) \
-   && !WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP)
-#   define ASIO_WINDOWS_APP 1
-#  endif // WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_APP)
-         // && !WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP)
-# endif // defined(_WIN32_WINNT) && (_WIN32_WINNT >= 0x0603)
-#endif // !defined(ASIO_WINDOWS_APP)
-
-// Legacy WinRT target. Windows App is preferred.
-#if !defined(ASIO_WINDOWS_RUNTIME)
-# if !defined(ASIO_WINDOWS_APP)
-#  if defined(__cplusplus_winrt)
-#   include <winapifamily.h>
-#   if WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_APP) \
-    && !WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP)
-#    define ASIO_WINDOWS_RUNTIME 1
-#   endif // WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_APP)
-          // && !WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP)
-#  endif // defined(__cplusplus_winrt)
-# endif // !defined(ASIO_WINDOWS_APP)
-#endif // !defined(ASIO_WINDOWS_RUNTIME)
-
-// Windows target. Excludes WinRT but includes Windows App targets.
-#if !defined(ASIO_WINDOWS)
-# if !defined(ASIO_WINDOWS_RUNTIME)
-#  if defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_WINDOWS)
-#   define ASIO_WINDOWS 1
-#  elif defined(WIN32) || defined(_WIN32) || defined(__WIN32__)
-#   define ASIO_WINDOWS 1
-#  elif defined(ASIO_WINDOWS_APP)
-#   define ASIO_WINDOWS 1
-#  endif // defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_WINDOWS)
-# endif // !defined(ASIO_WINDOWS_RUNTIME)
-#endif // !defined(ASIO_WINDOWS)
-
-// Windows: target OS version.
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-# if !defined(_WIN32_WINNT) && !defined(_WIN32_WINDOWS)
-#  if defined(_MSC_VER) || defined(__BORLANDC__)
-#   pragma message( \
-  "Please define _WIN32_WINNT or _WIN32_WINDOWS appropriately. For example:\n"\
-  "- add -D_WIN32_WINNT=0x0501 to the compiler command line; or\n"\
-  "- add _WIN32_WINNT=0x0501 to your project's Preprocessor Definitions.\n"\
-  "Assuming _WIN32_WINNT=0x0501 (i.e. Windows XP target).")
-#  else // defined(_MSC_VER) || defined(__BORLANDC__)
-#   warning Please define _WIN32_WINNT or _WIN32_WINDOWS appropriately.
-#   warning For example, add -D_WIN32_WINNT=0x0501 to the compiler command line.
-#   warning Assuming _WIN32_WINNT=0x0501 (i.e. Windows XP target).
-#  endif // defined(_MSC_VER) || defined(__BORLANDC__)
-#  define _WIN32_WINNT 0x0501
-# endif // !defined(_WIN32_WINNT) && !defined(_WIN32_WINDOWS)
-# if defined(_MSC_VER)
-#  if defined(_WIN32) && !defined(WIN32)
-#   if !defined(_WINSOCK2API_)
-#    define WIN32 // Needed for correct types in winsock2.h
-#   else // !defined(_WINSOCK2API_)
-#    error Please define the macro WIN32 in your compiler options
-#   endif // !defined(_WINSOCK2API_)
-#  endif // defined(_WIN32) && !defined(WIN32)
-# endif // defined(_MSC_VER)
-# if defined(__BORLANDC__)
-#  if defined(__WIN32__) && !defined(WIN32)
-#   if !defined(_WINSOCK2API_)
-#    define WIN32 // Needed for correct types in winsock2.h
-#   else // !defined(_WINSOCK2API_)
-#    error Please define the macro WIN32 in your compiler options
-#   endif // !defined(_WINSOCK2API_)
-#  endif // defined(__WIN32__) && !defined(WIN32)
-# endif // defined(__BORLANDC__)
-# if defined(__CYGWIN__)
-#  if !defined(__USE_W32_SOCKETS)
-#   error You must add -D__USE_W32_SOCKETS to your compiler options.
-#  endif // !defined(__USE_W32_SOCKETS)
-# endif // defined(__CYGWIN__)
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-// Windows: minimise header inclusion.
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-# if !defined(ASIO_NO_WIN32_LEAN_AND_MEAN)
-#  if !defined(WIN32_LEAN_AND_MEAN)
-#   define WIN32_LEAN_AND_MEAN
-#  endif // !defined(WIN32_LEAN_AND_MEAN)
-# endif // !defined(ASIO_NO_WIN32_LEAN_AND_MEAN)
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-// Windows: suppress definition of "min" and "max" macros.
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-# if !defined(ASIO_NO_NOMINMAX)
-#  if !defined(NOMINMAX)
-#   define NOMINMAX 1
-#  endif // !defined(NOMINMAX)
-# endif // !defined(ASIO_NO_NOMINMAX)
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-// Windows: IO Completion Ports.
-#if !defined(ASIO_HAS_IOCP)
-# if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-#  if defined(_WIN32_WINNT) && (_WIN32_WINNT >= 0x0400)
-#   if !defined(UNDER_CE) && !defined(ASIO_WINDOWS_APP)
-#    if !defined(ASIO_DISABLE_IOCP)
-#     define ASIO_HAS_IOCP 1
-#    endif // !defined(ASIO_DISABLE_IOCP)
-#   endif // !defined(UNDER_CE) && !defined(ASIO_WINDOWS_APP)
-#  endif // defined(_WIN32_WINNT) && (_WIN32_WINNT >= 0x0400)
-# endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-#endif // !defined(ASIO_HAS_IOCP)
-
-// On POSIX (and POSIX-like) platforms we need to include unistd.h in order to
-// get access to the various platform feature macros, e.g. to be able to test
-// for threads support.
-#if !defined(ASIO_HAS_UNISTD_H)
-# if !defined(ASIO_HAS_BOOST_CONFIG)
-#  if defined(unix) \
-   || defined(__unix) \
-   || defined(_XOPEN_SOURCE) \
-   || defined(_POSIX_SOURCE) \
-   || (defined(__MACH__) && defined(__APPLE__)) \
-   || defined(__FreeBSD__) \
-   || defined(__NetBSD__) \
-   || defined(__OpenBSD__) \
-   || defined(__linux__)
-#   define ASIO_HAS_UNISTD_H 1
-#  endif
-# endif // !defined(ASIO_HAS_BOOST_CONFIG)
-#endif // !defined(ASIO_HAS_UNISTD_H)
-#if defined(ASIO_HAS_UNISTD_H)
-# include <unistd.h>
-#endif // defined(ASIO_HAS_UNISTD_H)
-
-// Linux: epoll, eventfd and timerfd.
-#if defined(__linux__)
-# include <linux/version.h>
-# if !defined(ASIO_HAS_EPOLL)
-#  if !defined(ASIO_DISABLE_EPOLL)
-#   if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,45)
-#    define ASIO_HAS_EPOLL 1
-#   endif // LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,45)
-#  endif // !defined(ASIO_DISABLE_EPOLL)
-# endif // !defined(ASIO_HAS_EPOLL)
-# if !defined(ASIO_HAS_EVENTFD)
-#  if !defined(ASIO_DISABLE_EVENTFD)
-#   if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
-#    define ASIO_HAS_EVENTFD 1
-#   endif // LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
-#  endif // !defined(ASIO_DISABLE_EVENTFD)
-# endif // !defined(ASIO_HAS_EVENTFD)
-# if !defined(ASIO_HAS_TIMERFD)
-#  if defined(ASIO_HAS_EPOLL)
-#   if (__GLIBC__ > 2) || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 8)
-#    define ASIO_HAS_TIMERFD 1
-#   endif // (__GLIBC__ > 2) || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 8)
-#  endif // defined(ASIO_HAS_EPOLL)
-# endif // !defined(ASIO_HAS_TIMERFD)
-#endif // defined(__linux__)
-
-// Mac OS X, FreeBSD, NetBSD, OpenBSD: kqueue.
-#if (defined(__MACH__) && defined(__APPLE__)) \
-  || defined(__FreeBSD__) \
-  || defined(__NetBSD__) \
-  || defined(__OpenBSD__)
-# if !defined(ASIO_HAS_KQUEUE)
-#  if !defined(ASIO_DISABLE_KQUEUE)
-#   define ASIO_HAS_KQUEUE 1
-#  endif // !defined(ASIO_DISABLE_KQUEUE)
-# endif // !defined(ASIO_HAS_KQUEUE)
-#endif // (defined(__MACH__) && defined(__APPLE__))
-       //   || defined(__FreeBSD__)
-       //   || defined(__NetBSD__)
-       //   || defined(__OpenBSD__)
-
-// Solaris: /dev/poll.
-#if defined(__sun)
-# if !defined(ASIO_HAS_DEV_POLL)
-#  if !defined(ASIO_DISABLE_DEV_POLL)
-#   define ASIO_HAS_DEV_POLL 1
-#  endif // !defined(ASIO_DISABLE_DEV_POLL)
-# endif // !defined(ASIO_HAS_DEV_POLL)
-#endif // defined(__sun)
-
-// Serial ports.
-#if !defined(ASIO_HAS_SERIAL_PORT)
-# if defined(ASIO_HAS_IOCP) \
-  || !defined(ASIO_WINDOWS) \
-  && !defined(ASIO_WINDOWS_RUNTIME) \
-  && !defined(__CYGWIN__)
-#  if !defined(__SYMBIAN32__)
-#   if !defined(ASIO_DISABLE_SERIAL_PORT)
-#    define ASIO_HAS_SERIAL_PORT 1
-#   endif // !defined(ASIO_DISABLE_SERIAL_PORT)
-#  endif // !defined(__SYMBIAN32__)
-# endif // defined(ASIO_HAS_IOCP)
-        //   || !defined(ASIO_WINDOWS)
-        //   && !defined(ASIO_WINDOWS_RUNTIME)
-        //   && !defined(__CYGWIN__)
-#endif // !defined(ASIO_HAS_SERIAL_PORT)
-
-// Windows: stream handles.
-#if !defined(ASIO_HAS_WINDOWS_STREAM_HANDLE)
-# if !defined(ASIO_DISABLE_WINDOWS_STREAM_HANDLE)
-#  if defined(ASIO_HAS_IOCP)
-#   define ASIO_HAS_WINDOWS_STREAM_HANDLE 1
-#  endif // defined(ASIO_HAS_IOCP)
-# endif // !defined(ASIO_DISABLE_WINDOWS_STREAM_HANDLE)
-#endif // !defined(ASIO_HAS_WINDOWS_STREAM_HANDLE)
-
-// Windows: random access handles.
-#if !defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE)
-# if !defined(ASIO_DISABLE_WINDOWS_RANDOM_ACCESS_HANDLE)
-#  if defined(ASIO_HAS_IOCP)
-#   define ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE 1
-#  endif // defined(ASIO_HAS_IOCP)
-# endif // !defined(ASIO_DISABLE_WINDOWS_RANDOM_ACCESS_HANDLE)
-#endif // !defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE)
-
-// Windows: object handles.
-#if !defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE)
-# if !defined(ASIO_DISABLE_WINDOWS_OBJECT_HANDLE)
-#  if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-#   if !defined(UNDER_CE) && !defined(ASIO_WINDOWS_APP)
-#    define ASIO_HAS_WINDOWS_OBJECT_HANDLE 1
-#   endif // !defined(UNDER_CE) && !defined(ASIO_WINDOWS_APP)
-#  endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-# endif // !defined(ASIO_DISABLE_WINDOWS_OBJECT_HANDLE)
-#endif // !defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE)
-
-// Windows: OVERLAPPED wrapper.
-#if !defined(ASIO_HAS_WINDOWS_OVERLAPPED_PTR)
-# if !defined(ASIO_DISABLE_WINDOWS_OVERLAPPED_PTR)
-#  if defined(ASIO_HAS_IOCP)
-#   define ASIO_HAS_WINDOWS_OVERLAPPED_PTR 1
-#  endif // defined(ASIO_HAS_IOCP)
-# endif // !defined(ASIO_DISABLE_WINDOWS_OVERLAPPED_PTR)
-#endif // !defined(ASIO_HAS_WINDOWS_OVERLAPPED_PTR)
-
-// POSIX: stream-oriented file descriptors.
-#if !defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR)
-# if !defined(ASIO_DISABLE_POSIX_STREAM_DESCRIPTOR)
-#  if !defined(ASIO_WINDOWS) \
-  && !defined(ASIO_WINDOWS_RUNTIME) \
-  && !defined(__CYGWIN__)
-#   define ASIO_HAS_POSIX_STREAM_DESCRIPTOR 1
-#  endif // !defined(ASIO_WINDOWS)
-         //   && !defined(ASIO_WINDOWS_RUNTIME)
-         //   && !defined(__CYGWIN__)
-# endif // !defined(ASIO_DISABLE_POSIX_STREAM_DESCRIPTOR)
-#endif // !defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR)
-
-// UNIX domain sockets.
-#if !defined(ASIO_HAS_LOCAL_SOCKETS)
-# if !defined(ASIO_DISABLE_LOCAL_SOCKETS)
-#  if !defined(ASIO_WINDOWS) \
-  && !defined(ASIO_WINDOWS_RUNTIME) \
-  && !defined(__CYGWIN__)
-#   define ASIO_HAS_LOCAL_SOCKETS 1
-#  endif // !defined(ASIO_WINDOWS)
-         //   && !defined(ASIO_WINDOWS_RUNTIME)
-         //   && !defined(__CYGWIN__)
-# endif // !defined(ASIO_DISABLE_LOCAL_SOCKETS)
-#endif // !defined(ASIO_HAS_LOCAL_SOCKETS)
-
-// Can use sigaction() instead of signal().
-#if !defined(ASIO_HAS_SIGACTION)
-# if !defined(ASIO_DISABLE_SIGACTION)
-#  if !defined(ASIO_WINDOWS) \
-  && !defined(ASIO_WINDOWS_RUNTIME) \
-  && !defined(__CYGWIN__)
-#   define ASIO_HAS_SIGACTION 1
-#  endif // !defined(ASIO_WINDOWS)
-         //   && !defined(ASIO_WINDOWS_RUNTIME)
-         //   && !defined(__CYGWIN__)
-# endif // !defined(ASIO_DISABLE_SIGACTION)
-#endif // !defined(ASIO_HAS_SIGACTION)
-
-// Can use signal().
-#if !defined(ASIO_HAS_SIGNAL)
-# if !defined(ASIO_DISABLE_SIGNAL)
-#  if !defined(UNDER_CE)
-#   define ASIO_HAS_SIGNAL 1
-#  endif // !defined(UNDER_CE)
-# endif // !defined(ASIO_DISABLE_SIGNAL)
-#endif // !defined(ASIO_HAS_SIGNAL)
-
-// Can use getaddrinfo() and getnameinfo().
-#if !defined(ASIO_HAS_GETADDRINFO)
-# if !defined(ASIO_DISABLE_GETADDRINFO)
-#  if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-#   if defined(_WIN32_WINNT) && (_WIN32_WINNT >= 0x0501)
-#    define ASIO_HAS_GETADDRINFO 1
-#   elif defined(UNDER_CE)
-#    define ASIO_HAS_GETADDRINFO 1
-#   endif // defined(UNDER_CE)
-#  elif defined(__MACH__) && defined(__APPLE__)
-#   if defined(__MAC_OS_X_VERSION_MIN_REQUIRED)
-#    if (__MAC_OS_X_VERSION_MIN_REQUIRED >= 1050)
-#     define ASIO_HAS_GETADDRINFO 1
-#    endif // (__MAC_OS_X_VERSION_MIN_REQUIRED >= 1050)
-#   else // defined(__MAC_OS_X_VERSION_MIN_REQUIRED)
-#    define ASIO_HAS_GETADDRINFO 1
-#   endif // defined(__MAC_OS_X_VERSION_MIN_REQUIRED)
-#  else // defined(__MACH__) && defined(__APPLE__)
-#   define ASIO_HAS_GETADDRINFO 1
-#  endif // defined(__MACH__) && defined(__APPLE__)
-# endif // !defined(ASIO_DISABLE_GETADDRINFO)
-#endif // !defined(ASIO_HAS_GETADDRINFO)
-
-// Whether standard iostreams are disabled.
-#if !defined(ASIO_NO_IOSTREAM)
-# if defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_NO_IOSTREAM)
-#  define ASIO_NO_IOSTREAM 1
-# endif // !defined(BOOST_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-// Whether exception handling is disabled.
-#if !defined(ASIO_NO_EXCEPTIONS)
-# if defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_NO_EXCEPTIONS)
-#  define ASIO_NO_EXCEPTIONS 1
-# endif // !defined(BOOST_NO_EXCEPTIONS)
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-
-// Whether the typeid operator is supported.
-#if !defined(ASIO_NO_TYPEID)
-# if defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_NO_TYPEID)
-#  define ASIO_NO_TYPEID 1
-# endif // !defined(BOOST_NO_TYPEID)
-#endif // !defined(ASIO_NO_TYPEID)
-
-// Threads.
-#if !defined(ASIO_HAS_THREADS)
-# if !defined(ASIO_DISABLE_THREADS)
-#  if defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_HAS_THREADS)
-#   define ASIO_HAS_THREADS 1
-#  elif defined(__GNUC__) && !defined(__MINGW32__) \
-     && !defined(linux) && !defined(__linux) && !defined(__linux__)
-#   define ASIO_HAS_THREADS 1
-#  elif defined(_MT) || defined(__MT__)
-#   define ASIO_HAS_THREADS 1
-#  elif defined(_REENTRANT)
-#   define ASIO_HAS_THREADS 1
-#  elif defined(__APPLE__)
-#   define ASIO_HAS_THREADS 1
-#  elif defined(_POSIX_THREADS) && (_POSIX_THREADS + 0 >= 0)
-#   define ASIO_HAS_THREADS 1
-#  elif defined(_PTHREADS)
-#   define ASIO_HAS_THREADS 1
-#  endif // defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_HAS_THREADS)
-# endif // !defined(ASIO_DISABLE_THREADS)
-#endif // !defined(ASIO_HAS_THREADS)
-
-// POSIX threads.
-#if !defined(ASIO_HAS_PTHREADS)
-# if defined(ASIO_HAS_THREADS)
-#  if defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_HAS_PTHREADS)
-#   define ASIO_HAS_PTHREADS 1
-#  elif defined(_POSIX_THREADS) && (_POSIX_THREADS + 0 >= 0)
-#   define ASIO_HAS_PTHREADS 1
-#  endif // defined(ASIO_HAS_BOOST_CONFIG) && defined(BOOST_HAS_PTHREADS)
-# endif // defined(ASIO_HAS_THREADS)
-#endif // !defined(ASIO_HAS_PTHREADS)
-
-// Helper to prevent macro expansion.
-#define ASIO_PREVENT_MACRO_SUBSTITUTION
-
-// Helper to define in-class constants.
-#if !defined(ASIO_STATIC_CONSTANT)
-# if !defined(ASIO_DISABLE_BOOST_STATIC_CONSTANT)
-#  define ASIO_STATIC_CONSTANT(type, assignment) \
-    BOOST_STATIC_CONSTANT(type, assignment)
-# else // !defined(ASIO_DISABLE_BOOST_STATIC_CONSTANT)
-#  define ASIO_STATIC_CONSTANT(type, assignment) \
-    static const type assignment
-# endif // !defined(ASIO_DISABLE_BOOST_STATIC_CONSTANT)
-#endif // !defined(ASIO_STATIC_CONSTANT)
-
-// Boost array library.
-#if !defined(ASIO_HAS_BOOST_ARRAY)
-# if !defined(ASIO_DISABLE_BOOST_ARRAY)
-#  define ASIO_HAS_BOOST_ARRAY 1
-# endif // !defined(ASIO_DISABLE_BOOST_ARRAY)
-#endif // !defined(ASIO_HAS_BOOST_ARRAY)
-
-// Boost assert macro.
-#if !defined(ASIO_HAS_BOOST_ASSERT)
-# if !defined(ASIO_DISABLE_BOOST_ASSERT)
-#  define ASIO_HAS_BOOST_ASSERT 1
-# endif // !defined(ASIO_DISABLE_BOOST_ASSERT)
-#endif // !defined(ASIO_HAS_BOOST_ASSERT)
-
-// Boost limits header.
-#if !defined(ASIO_HAS_BOOST_LIMITS)
-# if !defined(ASIO_DISABLE_BOOST_LIMITS)
-#  define ASIO_HAS_BOOST_LIMITS 1
-# endif // !defined(ASIO_DISABLE_BOOST_LIMITS)
-#endif // !defined(ASIO_HAS_BOOST_LIMITS)
-
-// Boost throw_exception function.
-#if !defined(ASIO_HAS_BOOST_THROW_EXCEPTION)
-# if !defined(ASIO_DISABLE_BOOST_THROW_EXCEPTION)
-#  define ASIO_HAS_BOOST_THROW_EXCEPTION 1
-# endif // !defined(ASIO_DISABLE_BOOST_THROW_EXCEPTION)
-#endif // !defined(ASIO_HAS_BOOST_THROW_EXCEPTION)
-
-// Boost regex library.
-#if !defined(ASIO_HAS_BOOST_REGEX)
-# if !defined(ASIO_DISABLE_BOOST_REGEX)
-#  define ASIO_HAS_BOOST_REGEX 1
-# endif // !defined(ASIO_DISABLE_BOOST_REGEX)
-#endif // !defined(ASIO_HAS_BOOST_REGEX)
-
-// Boost bind function.
-#if !defined(ASIO_HAS_BOOST_BIND)
-# if !defined(ASIO_DISABLE_BOOST_BIND)
-#  define ASIO_HAS_BOOST_BIND 1
-# endif // !defined(ASIO_DISABLE_BOOST_BIND)
-#endif // !defined(ASIO_HAS_BOOST_BIND)
-
-// Boost's BOOST_WORKAROUND macro.
-#if !defined(ASIO_HAS_BOOST_WORKAROUND)
-# if !defined(ASIO_DISABLE_BOOST_WORKAROUND)
-#  define ASIO_HAS_BOOST_WORKAROUND 1
-# endif // !defined(ASIO_DISABLE_BOOST_WORKAROUND)
-#endif // !defined(ASIO_HAS_BOOST_WORKAROUND)
-
-// Microsoft Visual C++'s secure C runtime library.
-#if !defined(ASIO_HAS_SECURE_RTL)
-# if !defined(ASIO_DISABLE_SECURE_RTL)
-#  if defined(ASIO_MSVC) \
-    && (ASIO_MSVC >= 1400) \
-    && !defined(UNDER_CE)
-#   define ASIO_HAS_SECURE_RTL 1
-#  endif // defined(ASIO_MSVC)
-         // && (ASIO_MSVC >= 1400)
-         // && !defined(UNDER_CE)
-# endif // !defined(ASIO_DISABLE_SECURE_RTL)
-#endif // !defined(ASIO_HAS_SECURE_RTL)
-
-// Handler hooking. Disabled for ancient Borland C++ and gcc compilers.
-#if !defined(ASIO_HAS_HANDLER_HOOKS)
-# if !defined(ASIO_DISABLE_HANDLER_HOOKS)
-#  if defined(__GNUC__)
-#   if (__GNUC__ >= 3)
-#    define ASIO_HAS_HANDLER_HOOKS 1
-#   endif // (__GNUC__ >= 3)
-#  elif !defined(__BORLANDC__)
-#   define ASIO_HAS_HANDLER_HOOKS 1
-#  endif // !defined(__BORLANDC__)
-# endif // !defined(ASIO_DISABLE_HANDLER_HOOKS)
-#endif // !defined(ASIO_HAS_HANDLER_HOOKS)
-
-// Support for the __thread keyword extension.
-#if !defined(ASIO_DISABLE_THREAD_KEYWORD_EXTENSION)
-# if defined(__linux__)
-#  if defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
-#   if ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3)
-#    if !defined(__INTEL_COMPILER) && !defined(__ICL) \
-       && !(defined(__clang__) && defined(__ANDROID__))
-#     define ASIO_HAS_THREAD_KEYWORD_EXTENSION 1
-#     define ASIO_THREAD_KEYWORD __thread
-#    elif defined(__INTEL_COMPILER) && (__INTEL_COMPILER >= 1100)
-#     define ASIO_HAS_THREAD_KEYWORD_EXTENSION 1
-#    endif // defined(__INTEL_COMPILER) && (__INTEL_COMPILER >= 1100)
-           // && !(defined(__clang__) && defined(__ANDROID__))
-#   endif // ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3)
-#  endif // defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
-# endif // defined(__linux__)
-# if defined(ASIO_MSVC) && defined(ASIO_WINDOWS_RUNTIME)
-#  if (_MSC_VER >= 1700)
-#   define ASIO_HAS_THREAD_KEYWORD_EXTENSION 1
-#   define ASIO_THREAD_KEYWORD __declspec(thread)
-#  endif // (_MSC_VER >= 1700)
-# endif // defined(ASIO_MSVC) && defined(ASIO_WINDOWS_RUNTIME)
-#endif // !defined(ASIO_DISABLE_THREAD_KEYWORD_EXTENSION)
-#if !defined(ASIO_THREAD_KEYWORD)
-# define ASIO_THREAD_KEYWORD __thread
-#endif // !defined(ASIO_THREAD_KEYWORD)
-
-// Support for POSIX ssize_t typedef.
-#if !defined(ASIO_DISABLE_SSIZE_T)
-# if defined(__linux__) \
-   || (defined(__MACH__) && defined(__APPLE__))
-#  define ASIO_HAS_SSIZE_T 1
-# endif // defined(__linux__)
-        //   || (defined(__MACH__) && defined(__APPLE__))
-#endif // !defined(ASIO_DISABLE_SSIZE_T)
-
-// Helper macros to manage the transition away from the old services-based API.
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# define ASIO_SVC_TPARAM , typename Service
-# define ASIO_SVC_TPARAM_DEF1(d1) , typename Service d1
-# define ASIO_SVC_TPARAM_DEF2(d1, d2) , typename Service d1, d2
-# define ASIO_SVC_TARG , Service
-# define ASIO_SVC_T Service
-# define ASIO_SVC_TPARAM1 , typename Service1
-# define ASIO_SVC_TPARAM1_DEF1(d1) , typename Service1 d1
-# define ASIO_SVC_TPARAM1_DEF2(d1, d2) , typename Service1 d1, d2
-# define ASIO_SVC_TARG1 , Service1
-# define ASIO_SVC_T1 Service1
-# define ASIO_SVC_ACCESS public
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-# define ASIO_SVC_TPARAM
-# define ASIO_SVC_TPARAM_DEF1(d1)
-# define ASIO_SVC_TPARAM_DEF2(d1, d2)
-# define ASIO_SVC_TARG
-// ASIO_SVC_T is defined at each point of use.
-# define ASIO_SVC_TPARAM1
-# define ASIO_SVC_TPARAM1_DEF1(d1)
-# define ASIO_SVC_TPARAM1_DEF2(d1, d2)
-# define ASIO_SVC_TARG1
-// ASIO_SVC_T1 is defined at each point of use.
-# define ASIO_SVC_ACCESS protected
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-// Helper macros to manage transition away from error_code return values.
-#if defined(ASIO_NO_DEPRECATED)
-# define ASIO_SYNC_OP_VOID void
-# define ASIO_SYNC_OP_VOID_RETURN(e) return
-#else // defined(ASIO_NO_DEPRECATED)
-# define ASIO_SYNC_OP_VOID asio::error_code
-# define ASIO_SYNC_OP_VOID_RETURN(e) return e
-#endif // defined(ASIO_NO_DEPRECATED)
-
-// Newer gcc, clang need special treatment to suppress unused typedef warnings.
-#if defined(__clang__)
-# if defined(__apple_build_version__)
-#  if (__clang_major__ >= 7)
-#   define ASIO_UNUSED_TYPEDEF __attribute__((__unused__))
-#  endif // (__clang_major__ >= 7)
-# elif ((__clang_major__ == 3) && (__clang_minor__ >= 6)) \
-    || (__clang_major__ > 3)
-#  define ASIO_UNUSED_TYPEDEF __attribute__((__unused__))
-# endif // ((__clang_major__ == 3) && (__clang_minor__ >= 6))
-        //   || (__clang_major__ > 3)
-#elif defined(__GNUC__)
-# if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 8)) || (__GNUC__ > 4)
-#  define ASIO_UNUSED_TYPEDEF __attribute__((__unused__))
-# endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 8)) || (__GNUC__ > 4)
-#endif // defined(__GNUC__)
-#if !defined(ASIO_UNUSED_TYPEDEF)
-# define ASIO_UNUSED_TYPEDEF
-#endif // !defined(ASIO_UNUSED_TYPEDEF)
-
-// Some versions of gcc generate spurious warnings about unused variables.
-#if defined(__GNUC__)
-# if (__GNUC__ >= 4)
-#  define ASIO_UNUSED_VARIABLE __attribute__((__unused__))
-# endif // (__GNUC__ >= 4)
-#endif // defined(__GNUC__)
-#if !defined(ASIO_UNUSED_VARIABLE)
-# define ASIO_UNUSED_VARIABLE
-#endif // !defined(ASIO_UNUSED_VARIABLE)
-
-// Support co_await on compilers known to allow it.
-#if !defined(ASIO_HAS_CO_AWAIT)
-# if !defined(ASIO_DISABLE_CO_AWAIT)
-#  if defined(ASIO_MSVC)
-#   if (_MSC_FULL_VER >= 190023506)
-#    if defined(_RESUMABLE_FUNCTIONS_SUPPORTED)
-#     define ASIO_HAS_CO_AWAIT 1
-#    endif // defined(_RESUMABLE_FUNCTIONS_SUPPORTED)
-#   endif // (_MSC_FULL_VER >= 190023506)
-#  endif // defined(ASIO_MSVC)
-# endif // !defined(ASIO_DISABLE_CO_AWAIT)
-# if defined(__clang__)
-#  if (__cpp_coroutines >= 201703)
-#   if __has_include(<experimental/coroutine>)
-#    define ASIO_HAS_CO_AWAIT 1
-#   endif // __has_include(<experimental/coroutine>)
-#  endif // (__cpp_coroutines >= 201703)
-# endif // defined(__clang__)
-#endif // !defined(ASIO_HAS_CO_AWAIT)
-
-#endif // ASIO_DETAIL_CONFIG_HPP
diff --git a/tools/sdk/include/asio/asio/detail/consuming_buffers.hpp b/tools/sdk/include/asio/asio/detail/consuming_buffers.hpp
deleted file mode 100644
index 8127ae75ca2..00000000000
--- a/tools/sdk/include/asio/asio/detail/consuming_buffers.hpp
+++ /dev/null
@@ -1,414 +0,0 @@
-//
-// detail/consuming_buffers.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CONSUMING_BUFFERS_HPP
-#define ASIO_DETAIL_CONSUMING_BUFFERS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/buffer.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/limits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Helper template to determine the maximum number of prepared buffers.
-template <typename Buffers>
-struct prepared_buffers_max
-{
-  enum { value = buffer_sequence_adapter_base::max_buffers };
-};
-
-template <typename Elem, std::size_t N>
-struct prepared_buffers_max<boost::array<Elem, N> >
-{
-  enum { value = N };
-};
-
-#if defined(ASIO_HAS_STD_ARRAY)
-
-template <typename Elem, std::size_t N>
-struct prepared_buffers_max<std::array<Elem, N> >
-{
-  enum { value = N };
-};
-
-#endif // defined(ASIO_HAS_STD_ARRAY)
-
-// A buffer sequence used to represent a subsequence of the buffers.
-template <typename Buffer, std::size_t MaxBuffers>
-struct prepared_buffers
-{
-  typedef Buffer value_type;
-  typedef const Buffer* const_iterator;
-
-  enum { max_buffers = MaxBuffers < 16 ? MaxBuffers : 16 };
-
-  prepared_buffers() : count(0) {}
-  const_iterator begin() const { return elems; }
-  const_iterator end() const { return elems + count; }
-
-  Buffer elems[max_buffers];
-  std::size_t count;
-};
-
-// A proxy for a sub-range in a list of buffers.
-template <typename Buffer, typename Buffers, typename Buffer_Iterator>
-class consuming_buffers
-{
-public:
-  typedef prepared_buffers<Buffer, prepared_buffers_max<Buffers>::value>
-    prepared_buffers_type;
-
-  // Construct to represent the entire list of buffers.
-  explicit consuming_buffers(const Buffers& buffers)
-    : buffers_(buffers),
-      total_consumed_(0),
-      next_elem_(0),
-      next_elem_offset_(0)
-  {
-    using asio::buffer_size;
-    total_size_ = buffer_size(buffers);
-  }
-
-  // Determine if we are at the end of the buffers.
-  bool empty() const
-  {
-    return total_consumed_ >= total_size_;
-  }
-
-  // Get the buffer for a single transfer, with a size.
-  prepared_buffers_type prepare(std::size_t max_size)
-  {
-    prepared_buffers_type result;
-
-    Buffer_Iterator next = asio::buffer_sequence_begin(buffers_);
-    Buffer_Iterator end = asio::buffer_sequence_end(buffers_);
-
-    std::advance(next, next_elem_);
-    std::size_t elem_offset = next_elem_offset_;
-    while (next != end && max_size > 0 && (result.count) < result.max_buffers)
-    {
-      Buffer next_buf = Buffer(*next) + elem_offset;
-      result.elems[result.count] = asio::buffer(next_buf, max_size);
-      max_size -= result.elems[result.count].size();
-      elem_offset = 0;
-      if (result.elems[result.count].size() > 0)
-        ++result.count;
-      ++next;
-    }
-
-    return result;
-  }
-
-  // Consume the specified number of bytes from the buffers.
-  void consume(std::size_t size)
-  {
-    total_consumed_ += size;
-
-    Buffer_Iterator next = asio::buffer_sequence_begin(buffers_);
-    Buffer_Iterator end = asio::buffer_sequence_end(buffers_);
-
-    std::advance(next, next_elem_);
-    while (next != end && size > 0)
-    {
-      Buffer next_buf = Buffer(*next) + next_elem_offset_;
-      if (size < next_buf.size())
-      {
-        next_elem_offset_ += size;
-        size = 0;
-      }
-      else
-      {
-        size -= next_buf.size();
-        next_elem_offset_ = 0;
-        ++next_elem_;
-        ++next;
-      }
-    }
-  }
-
-  // Get the total number of bytes consumed from the buffers.
-  std::size_t total_consumed() const
-  {
-    return total_consumed_;
-  }
-
-private:
-  Buffers buffers_;
-  std::size_t total_size_;
-  std::size_t total_consumed_;
-  std::size_t next_elem_;
-  std::size_t next_elem_offset_;
-};
-
-// Base class of all consuming_buffers specialisations for single buffers.
-template <typename Buffer>
-class consuming_single_buffer
-{
-public:
-  // Construct to represent the entire list of buffers.
-  template <typename Buffer1>
-  explicit consuming_single_buffer(const Buffer1& buffer)
-    : buffer_(buffer),
-      total_consumed_(0)
-  {
-  }
-
-  // Determine if we are at the end of the buffers.
-  bool empty() const
-  {
-    return total_consumed_ >= buffer_.size();
-  }
-
-  // Get the buffer for a single transfer, with a size.
-  Buffer prepare(std::size_t max_size)
-  {
-    return asio::buffer(buffer_ + total_consumed_, max_size);
-  }
-
-  // Consume the specified number of bytes from the buffers.
-  void consume(std::size_t size)
-  {
-    total_consumed_ += size;
-  }
-
-  // Get the total number of bytes consumed from the buffers.
-  std::size_t total_consumed() const
-  {
-    return total_consumed_;
-  }
-
-private:
-  Buffer buffer_;
-  std::size_t total_consumed_;
-};
-
-template <>
-class consuming_buffers<mutable_buffer, mutable_buffer, const mutable_buffer*>
-  : public consuming_single_buffer<ASIO_MUTABLE_BUFFER>
-{
-public:
-  explicit consuming_buffers(const mutable_buffer& buffer)
-    : consuming_single_buffer<ASIO_MUTABLE_BUFFER>(buffer)
-  {
-  }
-};
-
-template <>
-class consuming_buffers<const_buffer, mutable_buffer, const mutable_buffer*>
-  : public consuming_single_buffer<ASIO_CONST_BUFFER>
-{
-public:
-  explicit consuming_buffers(const mutable_buffer& buffer)
-    : consuming_single_buffer<ASIO_CONST_BUFFER>(buffer)
-  {
-  }
-};
-
-template <>
-class consuming_buffers<const_buffer, const_buffer, const const_buffer*>
-  : public consuming_single_buffer<ASIO_CONST_BUFFER>
-{
-public:
-  explicit consuming_buffers(const const_buffer& buffer)
-    : consuming_single_buffer<ASIO_CONST_BUFFER>(buffer)
-  {
-  }
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-template <>
-class consuming_buffers<mutable_buffer,
-    mutable_buffers_1, const mutable_buffer*>
-  : public consuming_single_buffer<ASIO_MUTABLE_BUFFER>
-{
-public:
-  explicit consuming_buffers(const mutable_buffers_1& buffer)
-    : consuming_single_buffer<ASIO_MUTABLE_BUFFER>(buffer)
-  {
-  }
-};
-
-template <>
-class consuming_buffers<const_buffer, mutable_buffers_1, const mutable_buffer*>
-  : public consuming_single_buffer<ASIO_CONST_BUFFER>
-{
-public:
-  explicit consuming_buffers(const mutable_buffers_1& buffer)
-    : consuming_single_buffer<ASIO_CONST_BUFFER>(buffer)
-  {
-  }
-};
-
-template <>
-class consuming_buffers<const_buffer, const_buffers_1, const const_buffer*>
-  : public consuming_single_buffer<ASIO_CONST_BUFFER>
-{
-public:
-  explicit consuming_buffers(const const_buffers_1& buffer)
-    : consuming_single_buffer<ASIO_CONST_BUFFER>(buffer)
-  {
-  }
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Buffer, typename Elem>
-class consuming_buffers<Buffer, boost::array<Elem, 2>,
-    typename boost::array<Elem, 2>::const_iterator>
-{
-public:
-  // Construct to represent the entire list of buffers.
-  explicit consuming_buffers(const boost::array<Elem, 2>& buffers)
-    : buffers_(buffers),
-      total_consumed_(0)
-  {
-  }
-
-  // Determine if we are at the end of the buffers.
-  bool empty() const
-  {
-    return total_consumed_ >=
-      Buffer(buffers_[0]).size() + Buffer(buffers_[1]).size();
-  }
-
-  // Get the buffer for a single transfer, with a size.
-  boost::array<Buffer, 2> prepare(std::size_t max_size)
-  {
-    boost::array<Buffer, 2> result = {{
-      Buffer(buffers_[0]), Buffer(buffers_[1]) }};
-    std::size_t buffer0_size = result[0].size();
-    result[0] = asio::buffer(result[0] + total_consumed_, max_size);
-    result[1] = asio::buffer(
-        result[1] + (total_consumed_ < buffer0_size
-          ? 0 : total_consumed_ - buffer0_size),
-        max_size - result[0].size());
-    return result;
-  }
-
-  // Consume the specified number of bytes from the buffers.
-  void consume(std::size_t size)
-  {
-    total_consumed_ += size;
-  }
-
-  // Get the total number of bytes consumed from the buffers.
-  std::size_t total_consumed() const
-  {
-    return total_consumed_;
-  }
-
-private:
-  boost::array<Elem, 2> buffers_;
-  std::size_t total_consumed_;
-};
-
-#if defined(ASIO_HAS_STD_ARRAY)
-
-template <typename Buffer, typename Elem>
-class consuming_buffers<Buffer, std::array<Elem, 2>,
-    typename std::array<Elem, 2>::const_iterator>
-{
-public:
-  // Construct to represent the entire list of buffers.
-  explicit consuming_buffers(const std::array<Elem, 2>& buffers)
-    : buffers_(buffers),
-      total_consumed_(0)
-  {
-  }
-
-  // Determine if we are at the end of the buffers.
-  bool empty() const
-  {
-    return total_consumed_ >=
-      Buffer(buffers_[0]).size() + Buffer(buffers_[1]).size();
-  }
-
-  // Get the buffer for a single transfer, with a size.
-  std::array<Buffer, 2> prepare(std::size_t max_size)
-  {
-    std::array<Buffer, 2> result = {{
-      Buffer(buffers_[0]), Buffer(buffers_[1]) }};
-    std::size_t buffer0_size = result[0].size();
-    result[0] = asio::buffer(result[0] + total_consumed_, max_size);
-    result[1] = asio::buffer(
-        result[1] + (total_consumed_ < buffer0_size
-          ? 0 : total_consumed_ - buffer0_size),
-        max_size - result[0].size());
-    return result;
-  }
-
-  // Consume the specified number of bytes from the buffers.
-  void consume(std::size_t size)
-  {
-    total_consumed_ += size;
-  }
-
-  // Get the total number of bytes consumed from the buffers.
-  std::size_t total_consumed() const
-  {
-    return total_consumed_;
-  }
-
-private:
-  std::array<Elem, 2> buffers_;
-  std::size_t total_consumed_;
-};
-
-#endif // defined(ASIO_HAS_STD_ARRAY)
-
-// Specialisation for null_buffers to ensure that the null_buffers type is
-// always passed through to the underlying read or write operation.
-template <typename Buffer>
-class consuming_buffers<Buffer, null_buffers, const mutable_buffer*>
-  : public asio::null_buffers
-{
-public:
-  consuming_buffers(const null_buffers&)
-  {
-    // No-op.
-  }
-
-  bool empty()
-  {
-    return false;
-  }
-
-  null_buffers prepare(std::size_t)
-  {
-    return null_buffers();
-  }
-
-  void consume(std::size_t)
-  {
-    // No-op.
-  }
-
-  std::size_t total_consumed() const
-  {
-    return 0;
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_CONSUMING_BUFFERS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/cstddef.hpp b/tools/sdk/include/asio/asio/detail/cstddef.hpp
deleted file mode 100644
index 3912da40df2..00000000000
--- a/tools/sdk/include/asio/asio/detail/cstddef.hpp
+++ /dev/null
@@ -1,31 +0,0 @@
-//
-// detail/cstddef.hpp
-// ~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CSTDDEF_HPP
-#define ASIO_DETAIL_CSTDDEF_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-
-namespace asio {
-
-#if defined(ASIO_HAS_NULLPTR)
-using std::nullptr_t;
-#else // defined(ASIO_HAS_NULLPTR)
-struct nullptr_t {};
-#endif // defined(ASIO_HAS_NULLPTR)
-
-} // namespace asio
-
-#endif // ASIO_DETAIL_CSTDDEF_HPP
diff --git a/tools/sdk/include/asio/asio/detail/cstdint.hpp b/tools/sdk/include/asio/asio/detail/cstdint.hpp
deleted file mode 100644
index 62342b2d2c1..00000000000
--- a/tools/sdk/include/asio/asio/detail/cstdint.hpp
+++ /dev/null
@@ -1,60 +0,0 @@
-//
-// detail/cstdint.hpp
-// ~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_CSTDINT_HPP
-#define ASIO_DETAIL_CSTDINT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_CSTDINT)
-# include <cstdint>
-#else // defined(ASIO_HAS_CSTDINT)
-# include <boost/cstdint.hpp>
-#endif // defined(ASIO_HAS_CSTDINT)
-
-namespace asio {
-
-#if defined(ASIO_HAS_CSTDINT)
-using std::int16_t;
-using std::int_least16_t;
-using std::uint16_t;
-using std::uint_least16_t;
-using std::int32_t;
-using std::int_least32_t;
-using std::uint32_t;
-using std::uint_least32_t;
-using std::int64_t;
-using std::int_least64_t;
-using std::uint64_t;
-using std::uint_least64_t;
-using std::uintmax_t;
-#else // defined(ASIO_HAS_CSTDINT)
-using boost::int16_t;
-using boost::int_least16_t;
-using boost::uint16_t;
-using boost::uint_least16_t;
-using boost::int32_t;
-using boost::int_least32_t;
-using boost::uint32_t;
-using boost::uint_least32_t;
-using boost::int64_t;
-using boost::int_least64_t;
-using boost::uint64_t;
-using boost::uint_least64_t;
-using boost::uintmax_t;
-#endif // defined(ASIO_HAS_CSTDINT)
-
-} // namespace asio
-
-#endif // ASIO_DETAIL_CSTDINT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/date_time_fwd.hpp b/tools/sdk/include/asio/asio/detail/date_time_fwd.hpp
deleted file mode 100644
index a159562eb5c..00000000000
--- a/tools/sdk/include/asio/asio/detail/date_time_fwd.hpp
+++ /dev/null
@@ -1,34 +0,0 @@
-//
-// detail/date_time_fwd.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_DATE_TIME_FWD_HPP
-#define ASIO_DETAIL_DATE_TIME_FWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-namespace boost {
-namespace date_time {
-
-template<class T, class TimeSystem>
-class base_time;
-
-} // namespace date_time
-namespace posix_time {
-
-class ptime;
-
-} // namespace posix_time
-} // namespace boost
-
-#endif // ASIO_DETAIL_DATE_TIME_FWD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/deadline_timer_service.hpp b/tools/sdk/include/asio/asio/detail/deadline_timer_service.hpp
deleted file mode 100644
index f58a6e0e764..00000000000
--- a/tools/sdk/include/asio/asio/detail/deadline_timer_service.hpp
+++ /dev/null
@@ -1,278 +0,0 @@
-//
-// detail/deadline_timer_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_DEADLINE_TIMER_SERVICE_HPP
-#define ASIO_DETAIL_DEADLINE_TIMER_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/timer_queue.hpp"
-#include "asio/detail/timer_queue_ptime.hpp"
-#include "asio/detail/timer_scheduler.hpp"
-#include "asio/detail/wait_handler.hpp"
-#include "asio/detail/wait_op.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include <chrono>
-# include <thread>
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Time_Traits>
-class deadline_timer_service
-  : public service_base<deadline_timer_service<Time_Traits> >
-{
-public:
-  // The time type.
-  typedef typename Time_Traits::time_type time_type;
-
-  // The duration type.
-  typedef typename Time_Traits::duration_type duration_type;
-
-  // The implementation type of the timer. This type is dependent on the
-  // underlying implementation of the timer service.
-  struct implementation_type
-    : private asio::detail::noncopyable
-  {
-    time_type expiry;
-    bool might_have_pending_waits;
-    typename timer_queue<Time_Traits>::per_timer_data timer_data;
-  };
-
-  // Constructor.
-  deadline_timer_service(asio::io_context& io_context)
-    : service_base<deadline_timer_service<Time_Traits> >(io_context),
-      scheduler_(asio::use_service<timer_scheduler>(io_context))
-  {
-    scheduler_.init_task();
-    scheduler_.add_timer_queue(timer_queue_);
-  }
-
-  // Destructor.
-  ~deadline_timer_service()
-  {
-    scheduler_.remove_timer_queue(timer_queue_);
-  }
-
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-  }
-
-  // Construct a new timer implementation.
-  void construct(implementation_type& impl)
-  {
-    impl.expiry = time_type();
-    impl.might_have_pending_waits = false;
-  }
-
-  // Destroy a timer implementation.
-  void destroy(implementation_type& impl)
-  {
-    asio::error_code ec;
-    cancel(impl, ec);
-  }
-
-  // Move-construct a new serial port implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    scheduler_.move_timer(timer_queue_, impl.timer_data, other_impl.timer_data);
-
-    impl.expiry = other_impl.expiry;
-    other_impl.expiry = time_type();
-
-    impl.might_have_pending_waits = other_impl.might_have_pending_waits;
-    other_impl.might_have_pending_waits = false;
-  }
-
-  // Move-assign from another serial port implementation.
-  void move_assign(implementation_type& impl,
-      deadline_timer_service& other_service,
-      implementation_type& other_impl)
-  {
-    if (this != &other_service)
-      if (impl.might_have_pending_waits)
-        scheduler_.cancel_timer(timer_queue_, impl.timer_data);
-
-    other_service.scheduler_.move_timer(other_service.timer_queue_,
-        impl.timer_data, other_impl.timer_data);
-
-    impl.expiry = other_impl.expiry;
-    other_impl.expiry = time_type();
-
-    impl.might_have_pending_waits = other_impl.might_have_pending_waits;
-    other_impl.might_have_pending_waits = false;
-  }
-
-  // Cancel any asynchronous wait operations associated with the timer.
-  std::size_t cancel(implementation_type& impl, asio::error_code& ec)
-  {
-    if (!impl.might_have_pending_waits)
-    {
-      ec = asio::error_code();
-      return 0;
-    }
-
-    ASIO_HANDLER_OPERATION((scheduler_.context(),
-          "deadline_timer", &impl, 0, "cancel"));
-
-    std::size_t count = scheduler_.cancel_timer(timer_queue_, impl.timer_data);
-    impl.might_have_pending_waits = false;
-    ec = asio::error_code();
-    return count;
-  }
-
-  // Cancels one asynchronous wait operation associated with the timer.
-  std::size_t cancel_one(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    if (!impl.might_have_pending_waits)
-    {
-      ec = asio::error_code();
-      return 0;
-    }
-
-    ASIO_HANDLER_OPERATION((scheduler_.context(),
-          "deadline_timer", &impl, 0, "cancel_one"));
-
-    std::size_t count = scheduler_.cancel_timer(
-        timer_queue_, impl.timer_data, 1);
-    if (count == 0)
-      impl.might_have_pending_waits = false;
-    ec = asio::error_code();
-    return count;
-  }
-
-  // Get the expiry time for the timer as an absolute time.
-  time_type expiry(const implementation_type& impl) const
-  {
-    return impl.expiry;
-  }
-
-  // Get the expiry time for the timer as an absolute time.
-  time_type expires_at(const implementation_type& impl) const
-  {
-    return impl.expiry;
-  }
-
-  // Get the expiry time for the timer relative to now.
-  duration_type expires_from_now(const implementation_type& impl) const
-  {
-    return Time_Traits::subtract(this->expiry(impl), Time_Traits::now());
-  }
-
-  // Set the expiry time for the timer as an absolute time.
-  std::size_t expires_at(implementation_type& impl,
-      const time_type& expiry_time, asio::error_code& ec)
-  {
-    std::size_t count = cancel(impl, ec);
-    impl.expiry = expiry_time;
-    ec = asio::error_code();
-    return count;
-  }
-
-  // Set the expiry time for the timer relative to now.
-  std::size_t expires_after(implementation_type& impl,
-      const duration_type& expiry_time, asio::error_code& ec)
-  {
-    return expires_at(impl,
-        Time_Traits::add(Time_Traits::now(), expiry_time), ec);
-  }
-
-  // Set the expiry time for the timer relative to now.
-  std::size_t expires_from_now(implementation_type& impl,
-      const duration_type& expiry_time, asio::error_code& ec)
-  {
-    return expires_at(impl,
-        Time_Traits::add(Time_Traits::now(), expiry_time), ec);
-  }
-
-  // Perform a blocking wait on the timer.
-  void wait(implementation_type& impl, asio::error_code& ec)
-  {
-    time_type now = Time_Traits::now();
-    ec = asio::error_code();
-    while (Time_Traits::less_than(now, impl.expiry) && !ec)
-    {
-      this->do_wait(Time_Traits::to_posix_duration(
-            Time_Traits::subtract(impl.expiry, now)), ec);
-      now = Time_Traits::now();
-    }
-  }
-
-  // Start an asynchronous wait on the timer.
-  template <typename Handler>
-  void async_wait(implementation_type& impl, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef wait_handler<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    impl.might_have_pending_waits = true;
-
-    ASIO_HANDLER_CREATION((scheduler_.context(),
-          *p.p, "deadline_timer", &impl, 0, "async_wait"));
-
-    scheduler_.schedule_timer(timer_queue_, impl.expiry, impl.timer_data, p.p);
-    p.v = p.p = 0;
-  }
-
-private:
-  // Helper function to wait given a duration type. The duration type should
-  // either be of type boost::posix_time::time_duration, or implement the
-  // required subset of its interface.
-  template <typename Duration>
-  void do_wait(const Duration& timeout, asio::error_code& ec)
-  {
-#if defined(ASIO_WINDOWS_RUNTIME)
-    std::this_thread::sleep_for(
-        std::chrono::seconds(timeout.total_seconds())
-        + std::chrono::microseconds(timeout.total_microseconds()));
-    ec = asio::error_code();
-#else // defined(ASIO_WINDOWS_RUNTIME)
-    ::timeval tv;
-    tv.tv_sec = timeout.total_seconds();
-    tv.tv_usec = timeout.total_microseconds() % 1000000;
-    socket_ops::select(0, 0, 0, 0, &tv, ec);
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-  }
-
-  // The queue of timers.
-  timer_queue<Time_Traits> timer_queue_;
-
-  // The object that schedules and executes timers. Usually a reactor.
-  timer_scheduler& scheduler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_DEADLINE_TIMER_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/dependent_type.hpp b/tools/sdk/include/asio/asio/detail/dependent_type.hpp
deleted file mode 100644
index 85b41c8935f..00000000000
--- a/tools/sdk/include/asio/asio/detail/dependent_type.hpp
+++ /dev/null
@@ -1,36 +0,0 @@
-//
-// detail/dependent_type.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_DEPENDENT_TYPE_HPP
-#define ASIO_DETAIL_DEPENDENT_TYPE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename DependsOn, typename T>
-struct dependent_type
-{
-  typedef T type;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_DEPENDENT_TYPE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/descriptor_ops.hpp b/tools/sdk/include/asio/asio/detail/descriptor_ops.hpp
deleted file mode 100644
index 9c0560aa2c9..00000000000
--- a/tools/sdk/include/asio/asio/detail/descriptor_ops.hpp
+++ /dev/null
@@ -1,121 +0,0 @@
-//
-// detail/descriptor_ops.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_DESCRIPTOR_OPS_HPP
-#define ASIO_DETAIL_DESCRIPTOR_OPS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS) \
-  && !defined(ASIO_WINDOWS_RUNTIME) \
-  && !defined(__CYGWIN__)
-
-#include <cstddef>
-#include "asio/error.hpp"
-#include "asio/error_code.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-namespace descriptor_ops {
-
-// Descriptor state bits.
-enum
-{
-  // The user wants a non-blocking descriptor.
-  user_set_non_blocking = 1,
-
-  // The descriptor has been set non-blocking.
-  internal_non_blocking = 2,
-
-  // Helper "state" used to determine whether the descriptor is non-blocking.
-  non_blocking = user_set_non_blocking | internal_non_blocking,
-
-  // The descriptor may have been dup()-ed.
-  possible_dup = 4
-};
-
-typedef unsigned char state_type;
-
-template <typename ReturnType>
-inline ReturnType error_wrapper(ReturnType return_value,
-    asio::error_code& ec)
-{
-  ec = asio::error_code(errno,
-      asio::error::get_system_category());
-  return return_value;
-}
-
-ASIO_DECL int open(const char* path, int flags,
-    asio::error_code& ec);
-
-ASIO_DECL int close(int d, state_type& state,
-    asio::error_code& ec);
-
-ASIO_DECL bool set_user_non_blocking(int d,
-    state_type& state, bool value, asio::error_code& ec);
-
-ASIO_DECL bool set_internal_non_blocking(int d,
-    state_type& state, bool value, asio::error_code& ec);
-
-typedef iovec buf;
-
-ASIO_DECL std::size_t sync_read(int d, state_type state, buf* bufs,
-    std::size_t count, bool all_empty, asio::error_code& ec);
-
-ASIO_DECL bool non_blocking_read(int d, buf* bufs, std::size_t count,
-    asio::error_code& ec, std::size_t& bytes_transferred);
-
-ASIO_DECL std::size_t sync_write(int d, state_type state,
-    const buf* bufs, std::size_t count, bool all_empty,
-    asio::error_code& ec);
-
-ASIO_DECL bool non_blocking_write(int d,
-    const buf* bufs, std::size_t count,
-    asio::error_code& ec, std::size_t& bytes_transferred);
-
-ASIO_DECL int ioctl(int d, state_type& state, long cmd,
-    ioctl_arg_type* arg, asio::error_code& ec);
-
-ASIO_DECL int fcntl(int d, int cmd, asio::error_code& ec);
-
-ASIO_DECL int fcntl(int d, int cmd,
-    long arg, asio::error_code& ec);
-
-ASIO_DECL int poll_read(int d,
-    state_type state, asio::error_code& ec);
-
-ASIO_DECL int poll_write(int d,
-    state_type state, asio::error_code& ec);
-
-ASIO_DECL int poll_error(int d,
-    state_type state, asio::error_code& ec);
-
-} // namespace descriptor_ops
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/descriptor_ops.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // !defined(ASIO_WINDOWS)
-       //   && !defined(ASIO_WINDOWS_RUNTIME)
-       //   && !defined(__CYGWIN__)
-
-#endif // ASIO_DETAIL_DESCRIPTOR_OPS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/descriptor_read_op.hpp b/tools/sdk/include/asio/asio/detail/descriptor_read_op.hpp
deleted file mode 100644
index 6db4bfb958e..00000000000
--- a/tools/sdk/include/asio/asio/detail/descriptor_read_op.hpp
+++ /dev/null
@@ -1,128 +0,0 @@
-//
-// detail/descriptor_read_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_DESCRIPTOR_READ_OP_HPP
-#define ASIO_DETAIL_DESCRIPTOR_READ_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/descriptor_ops.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_work.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename MutableBufferSequence>
-class descriptor_read_op_base : public reactor_op
-{
-public:
-  descriptor_read_op_base(int descriptor,
-      const MutableBufferSequence& buffers, func_type complete_func)
-    : reactor_op(&descriptor_read_op_base::do_perform, complete_func),
-      descriptor_(descriptor),
-      buffers_(buffers)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    descriptor_read_op_base* o(static_cast<descriptor_read_op_base*>(base));
-
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(o->buffers_);
-
-    status result = descriptor_ops::non_blocking_read(o->descriptor_,
-        bufs.buffers(), bufs.count(), o->ec_, o->bytes_transferred_)
-      ? done : not_done;
-
-    ASIO_HANDLER_REACTOR_OPERATION((*o, "non_blocking_read",
-          o->ec_, o->bytes_transferred_));
-
-    return result;
-  }
-
-private:
-  int descriptor_;
-  MutableBufferSequence buffers_;
-};
-
-template <typename MutableBufferSequence, typename Handler>
-class descriptor_read_op
-  : public descriptor_read_op_base<MutableBufferSequence>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(descriptor_read_op);
-
-  descriptor_read_op(int descriptor,
-      const MutableBufferSequence& buffers, Handler& handler)
-    : descriptor_read_op_base<MutableBufferSequence>(
-        descriptor, buffers, &descriptor_read_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    descriptor_read_op* o(static_cast<descriptor_read_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, o->bytes_transferred_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-#endif // ASIO_DETAIL_DESCRIPTOR_READ_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/descriptor_write_op.hpp b/tools/sdk/include/asio/asio/detail/descriptor_write_op.hpp
deleted file mode 100644
index a9ec2a97624..00000000000
--- a/tools/sdk/include/asio/asio/detail/descriptor_write_op.hpp
+++ /dev/null
@@ -1,128 +0,0 @@
-//
-// detail/descriptor_write_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_DESCRIPTOR_WRITE_OP_HPP
-#define ASIO_DETAIL_DESCRIPTOR_WRITE_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/descriptor_ops.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_work.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename ConstBufferSequence>
-class descriptor_write_op_base : public reactor_op
-{
-public:
-  descriptor_write_op_base(int descriptor,
-      const ConstBufferSequence& buffers, func_type complete_func)
-    : reactor_op(&descriptor_write_op_base::do_perform, complete_func),
-      descriptor_(descriptor),
-      buffers_(buffers)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    descriptor_write_op_base* o(static_cast<descriptor_write_op_base*>(base));
-
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(o->buffers_);
-
-    status result = descriptor_ops::non_blocking_write(o->descriptor_,
-        bufs.buffers(), bufs.count(), o->ec_, o->bytes_transferred_)
-      ? done : not_done;
-
-    ASIO_HANDLER_REACTOR_OPERATION((*o, "non_blocking_write",
-          o->ec_, o->bytes_transferred_));
-
-    return result;
-  }
-
-private:
-  int descriptor_;
-  ConstBufferSequence buffers_;
-};
-
-template <typename ConstBufferSequence, typename Handler>
-class descriptor_write_op
-  : public descriptor_write_op_base<ConstBufferSequence>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(descriptor_write_op);
-
-  descriptor_write_op(int descriptor,
-      const ConstBufferSequence& buffers, Handler& handler)
-    : descriptor_write_op_base<ConstBufferSequence>(
-        descriptor, buffers, &descriptor_write_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    descriptor_write_op* o(static_cast<descriptor_write_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, o->bytes_transferred_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-#endif // ASIO_DETAIL_DESCRIPTOR_WRITE_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/dev_poll_reactor.hpp b/tools/sdk/include/asio/asio/detail/dev_poll_reactor.hpp
deleted file mode 100644
index e9e4e29e04b..00000000000
--- a/tools/sdk/include/asio/asio/detail/dev_poll_reactor.hpp
+++ /dev/null
@@ -1,218 +0,0 @@
-//
-// detail/dev_poll_reactor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_DEV_POLL_REACTOR_HPP
-#define ASIO_DETAIL_DEV_POLL_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_DEV_POLL)
-
-#include <cstddef>
-#include <vector>
-#include <sys/devpoll.h>
-#include "asio/detail/hash_map.hpp"
-#include "asio/detail/limits.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/reactor_op_queue.hpp"
-#include "asio/detail/select_interrupter.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/timer_queue_base.hpp"
-#include "asio/detail/timer_queue_set.hpp"
-#include "asio/detail/wait_op.hpp"
-#include "asio/execution_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class dev_poll_reactor
-  : public execution_context_service_base<dev_poll_reactor>
-{
-public:
-  enum op_types { read_op = 0, write_op = 1,
-    connect_op = 1, except_op = 2, max_ops = 3 };
-
-  // Per-descriptor data.
-  struct per_descriptor_data
-  {
-  };
-
-  // Constructor.
-  ASIO_DECL dev_poll_reactor(asio::execution_context& ctx);
-
-  // Destructor.
-  ASIO_DECL ~dev_poll_reactor();
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Recreate internal descriptors following a fork.
-  ASIO_DECL void notify_fork(
-      asio::execution_context::fork_event fork_ev);
-
-  // Initialise the task.
-  ASIO_DECL void init_task();
-
-  // Register a socket with the reactor. Returns 0 on success, system error
-  // code on failure.
-  ASIO_DECL int register_descriptor(socket_type, per_descriptor_data&);
-
-  // Register a descriptor with an associated single operation. Returns 0 on
-  // success, system error code on failure.
-  ASIO_DECL int register_internal_descriptor(
-      int op_type, socket_type descriptor,
-      per_descriptor_data& descriptor_data, reactor_op* op);
-
-  // Move descriptor registration from one descriptor_data object to another.
-  ASIO_DECL void move_descriptor(socket_type descriptor,
-      per_descriptor_data& target_descriptor_data,
-      per_descriptor_data& source_descriptor_data);
-
-  // Post a reactor operation for immediate completion.
-  void post_immediate_completion(reactor_op* op, bool is_continuation)
-  {
-    scheduler_.post_immediate_completion(op, is_continuation);
-  }
-
-  // Start a new operation. The reactor operation will be performed when the
-  // given descriptor is flagged as ready, or an error has occurred.
-  ASIO_DECL void start_op(int op_type, socket_type descriptor,
-      per_descriptor_data&, reactor_op* op,
-      bool is_continuation, bool allow_speculative);
-
-  // Cancel all operations associated with the given descriptor. The
-  // handlers associated with the descriptor will be invoked with the
-  // operation_aborted error.
-  ASIO_DECL void cancel_ops(socket_type descriptor, per_descriptor_data&);
-
-  // Cancel any operations that are running against the descriptor and remove
-  // its registration from the reactor. The reactor resources associated with
-  // the descriptor must be released by calling cleanup_descriptor_data.
-  ASIO_DECL void deregister_descriptor(socket_type descriptor,
-      per_descriptor_data&, bool closing);
-
-  // Remove the descriptor's registration from the reactor. The reactor
-  // resources associated with the descriptor must be released by calling
-  // cleanup_descriptor_data.
-  ASIO_DECL void deregister_internal_descriptor(
-      socket_type descriptor, per_descriptor_data&);
-
-  // Perform any post-deregistration cleanup tasks associated with the
-  // descriptor data.
-  ASIO_DECL void cleanup_descriptor_data(per_descriptor_data&);
-
-  // Add a new timer queue to the reactor.
-  template <typename Time_Traits>
-  void add_timer_queue(timer_queue<Time_Traits>& queue);
-
-  // Remove a timer queue from the reactor.
-  template <typename Time_Traits>
-  void remove_timer_queue(timer_queue<Time_Traits>& queue);
-
-  // Schedule a new operation in the given timer queue to expire at the
-  // specified absolute time.
-  template <typename Time_Traits>
-  void schedule_timer(timer_queue<Time_Traits>& queue,
-      const typename Time_Traits::time_type& time,
-      typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op);
-
-  // Cancel the timer operations associated with the given token. Returns the
-  // number of operations that have been posted or dispatched.
-  template <typename Time_Traits>
-  std::size_t cancel_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& timer,
-      std::size_t max_cancelled = (std::numeric_limits<std::size_t>::max)());
-
-  // Move the timer operations associated with the given timer.
-  template <typename Time_Traits>
-  void move_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& target,
-      typename timer_queue<Time_Traits>::per_timer_data& source);
-
-  // Run /dev/poll once until interrupted or events are ready to be dispatched.
-  ASIO_DECL void run(long usec, op_queue<operation>& ops);
-
-  // Interrupt the select loop.
-  ASIO_DECL void interrupt();
-
-private:
-  // Create the /dev/poll file descriptor. Throws an exception if the descriptor
-  // cannot be created.
-  ASIO_DECL static int do_dev_poll_create();
-
-  // Helper function to add a new timer queue.
-  ASIO_DECL void do_add_timer_queue(timer_queue_base& queue);
-
-  // Helper function to remove a timer queue.
-  ASIO_DECL void do_remove_timer_queue(timer_queue_base& queue);
-
-  // Get the timeout value for the /dev/poll DP_POLL operation. The timeout
-  // value is returned as a number of milliseconds. A return value of -1
-  // indicates that the poll should block indefinitely.
-  ASIO_DECL int get_timeout(int msec);
-
-  // Cancel all operations associated with the given descriptor. The do_cancel
-  // function of the handler objects will be invoked. This function does not
-  // acquire the dev_poll_reactor's mutex.
-  ASIO_DECL void cancel_ops_unlocked(socket_type descriptor,
-      const asio::error_code& ec);
-
-  // Add a pending event entry for the given descriptor.
-  ASIO_DECL ::pollfd& add_pending_event_change(int descriptor);
-
-  // The scheduler implementation used to post completions.
-  scheduler& scheduler_;
-
-  // Mutex to protect access to internal data.
-  asio::detail::mutex mutex_;
-
-  // The /dev/poll file descriptor.
-  int dev_poll_fd_;
-
-  // Vector of /dev/poll events waiting to be written to the descriptor.
-  std::vector< ::pollfd> pending_event_changes_;
-
-  // Hash map to associate a descriptor with a pending event change index.
-  hash_map<int, std::size_t> pending_event_change_index_;
-
-  // The interrupter is used to break a blocking DP_POLL operation.
-  select_interrupter interrupter_;
-
-  // The queues of read, write and except operations.
-  reactor_op_queue<socket_type> op_queue_[max_ops];
-
-  // The timer queues.
-  timer_queue_set timer_queues_;
-
-  // Whether the service has been shut down.
-  bool shutdown_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/detail/impl/dev_poll_reactor.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/dev_poll_reactor.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_DEV_POLL)
-
-#endif // ASIO_DETAIL_DEV_POLL_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/epoll_reactor.hpp b/tools/sdk/include/asio/asio/detail/epoll_reactor.hpp
deleted file mode 100644
index 5f58109930b..00000000000
--- a/tools/sdk/include/asio/asio/detail/epoll_reactor.hpp
+++ /dev/null
@@ -1,266 +0,0 @@
-//
-// detail/epoll_reactor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_EPOLL_REACTOR_HPP
-#define ASIO_DETAIL_EPOLL_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_EPOLL)
-
-#include "asio/detail/atomic_count.hpp"
-#include "asio/detail/conditionally_enabled_mutex.hpp"
-#include "asio/detail/limits.hpp"
-#include "asio/detail/object_pool.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/select_interrupter.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/timer_queue_base.hpp"
-#include "asio/detail/timer_queue_set.hpp"
-#include "asio/detail/wait_op.hpp"
-#include "asio/execution_context.hpp"
-
-#if defined(ASIO_HAS_TIMERFD)
-# include <sys/timerfd.h>
-#endif // defined(ASIO_HAS_TIMERFD)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class epoll_reactor
-  : public execution_context_service_base<epoll_reactor>
-{
-private:
-  // The mutex type used by this reactor.
-  typedef conditionally_enabled_mutex mutex;
-
-public:
-  enum op_types { read_op = 0, write_op = 1,
-    connect_op = 1, except_op = 2, max_ops = 3 };
-
-  // Per-descriptor queues.
-  class descriptor_state : operation
-  {
-    friend class epoll_reactor;
-    friend class object_pool_access;
-
-    descriptor_state* next_;
-    descriptor_state* prev_;
-
-    mutex mutex_;
-    epoll_reactor* reactor_;
-    int descriptor_;
-    uint32_t registered_events_;
-    op_queue<reactor_op> op_queue_[max_ops];
-    bool try_speculative_[max_ops];
-    bool shutdown_;
-
-    ASIO_DECL descriptor_state(bool locking);
-    void set_ready_events(uint32_t events) { task_result_ = events; }
-    void add_ready_events(uint32_t events) { task_result_ |= events; }
-    ASIO_DECL operation* perform_io(uint32_t events);
-    ASIO_DECL static void do_complete(
-        void* owner, operation* base,
-        const asio::error_code& ec, std::size_t bytes_transferred);
-  };
-
-  // Per-descriptor data.
-  typedef descriptor_state* per_descriptor_data;
-
-  // Constructor.
-  ASIO_DECL epoll_reactor(asio::execution_context& ctx);
-
-  // Destructor.
-  ASIO_DECL ~epoll_reactor();
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Recreate internal descriptors following a fork.
-  ASIO_DECL void notify_fork(
-      asio::execution_context::fork_event fork_ev);
-
-  // Initialise the task.
-  ASIO_DECL void init_task();
-
-  // Register a socket with the reactor. Returns 0 on success, system error
-  // code on failure.
-  ASIO_DECL int register_descriptor(socket_type descriptor,
-      per_descriptor_data& descriptor_data);
-
-  // Register a descriptor with an associated single operation. Returns 0 on
-  // success, system error code on failure.
-  ASIO_DECL int register_internal_descriptor(
-      int op_type, socket_type descriptor,
-      per_descriptor_data& descriptor_data, reactor_op* op);
-
-  // Move descriptor registration from one descriptor_data object to another.
-  ASIO_DECL void move_descriptor(socket_type descriptor,
-      per_descriptor_data& target_descriptor_data,
-      per_descriptor_data& source_descriptor_data);
-
-  // Post a reactor operation for immediate completion.
-  void post_immediate_completion(reactor_op* op, bool is_continuation)
-  {
-    scheduler_.post_immediate_completion(op, is_continuation);
-  }
-
-  // Start a new operation. The reactor operation will be performed when the
-  // given descriptor is flagged as ready, or an error has occurred.
-  ASIO_DECL void start_op(int op_type, socket_type descriptor,
-      per_descriptor_data& descriptor_data, reactor_op* op,
-      bool is_continuation, bool allow_speculative);
-
-  // Cancel all operations associated with the given descriptor. The
-  // handlers associated with the descriptor will be invoked with the
-  // operation_aborted error.
-  ASIO_DECL void cancel_ops(socket_type descriptor,
-      per_descriptor_data& descriptor_data);
-
-  // Cancel any operations that are running against the descriptor and remove
-  // its registration from the reactor. The reactor resources associated with
-  // the descriptor must be released by calling cleanup_descriptor_data.
-  ASIO_DECL void deregister_descriptor(socket_type descriptor,
-      per_descriptor_data& descriptor_data, bool closing);
-
-  // Remove the descriptor's registration from the reactor. The reactor
-  // resources associated with the descriptor must be released by calling
-  // cleanup_descriptor_data.
-  ASIO_DECL void deregister_internal_descriptor(
-      socket_type descriptor, per_descriptor_data& descriptor_data);
-
-  // Perform any post-deregistration cleanup tasks associated with the
-  // descriptor data.
-  ASIO_DECL void cleanup_descriptor_data(
-      per_descriptor_data& descriptor_data);
-
-  // Add a new timer queue to the reactor.
-  template <typename Time_Traits>
-  void add_timer_queue(timer_queue<Time_Traits>& timer_queue);
-
-  // Remove a timer queue from the reactor.
-  template <typename Time_Traits>
-  void remove_timer_queue(timer_queue<Time_Traits>& timer_queue);
-
-  // Schedule a new operation in the given timer queue to expire at the
-  // specified absolute time.
-  template <typename Time_Traits>
-  void schedule_timer(timer_queue<Time_Traits>& queue,
-      const typename Time_Traits::time_type& time,
-      typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op);
-
-  // Cancel the timer operations associated with the given token. Returns the
-  // number of operations that have been posted or dispatched.
-  template <typename Time_Traits>
-  std::size_t cancel_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& timer,
-      std::size_t max_cancelled = (std::numeric_limits<std::size_t>::max)());
-
-  // Move the timer operations associated with the given timer.
-  template <typename Time_Traits>
-  void move_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& target,
-      typename timer_queue<Time_Traits>::per_timer_data& source);
-
-  // Run epoll once until interrupted or events are ready to be dispatched.
-  ASIO_DECL void run(long usec, op_queue<operation>& ops);
-
-  // Interrupt the select loop.
-  ASIO_DECL void interrupt();
-
-private:
-  // The hint to pass to epoll_create to size its data structures.
-  enum { epoll_size = 20000 };
-
-  // Create the epoll file descriptor. Throws an exception if the descriptor
-  // cannot be created.
-  ASIO_DECL static int do_epoll_create();
-
-  // Create the timerfd file descriptor. Does not throw.
-  ASIO_DECL static int do_timerfd_create();
-
-  // Allocate a new descriptor state object.
-  ASIO_DECL descriptor_state* allocate_descriptor_state();
-
-  // Free an existing descriptor state object.
-  ASIO_DECL void free_descriptor_state(descriptor_state* s);
-
-  // Helper function to add a new timer queue.
-  ASIO_DECL void do_add_timer_queue(timer_queue_base& queue);
-
-  // Helper function to remove a timer queue.
-  ASIO_DECL void do_remove_timer_queue(timer_queue_base& queue);
-
-  // Called to recalculate and update the timeout.
-  ASIO_DECL void update_timeout();
-
-  // Get the timeout value for the epoll_wait call. The timeout value is
-  // returned as a number of milliseconds. A return value of -1 indicates
-  // that epoll_wait should block indefinitely.
-  ASIO_DECL int get_timeout(int msec);
-
-#if defined(ASIO_HAS_TIMERFD)
-  // Get the timeout value for the timer descriptor. The return value is the
-  // flag argument to be used when calling timerfd_settime.
-  ASIO_DECL int get_timeout(itimerspec& ts);
-#endif // defined(ASIO_HAS_TIMERFD)
-
-  // The scheduler implementation used to post completions.
-  scheduler& scheduler_;
-
-  // Mutex to protect access to internal data.
-  mutex mutex_;
-
-  // The interrupter is used to break a blocking epoll_wait call.
-  select_interrupter interrupter_;
-
-  // The epoll file descriptor.
-  int epoll_fd_;
-
-  // The timer file descriptor.
-  int timer_fd_;
-
-  // The timer queues.
-  timer_queue_set timer_queues_;
-
-  // Whether the service has been shut down.
-  bool shutdown_;
-
-  // Mutex to protect access to the registered descriptors.
-  mutex registered_descriptors_mutex_;
-
-  // Keep track of all registered descriptors.
-  object_pool<descriptor_state> registered_descriptors_;
-
-  // Helper class to do post-perform_io cleanup.
-  struct perform_io_cleanup_on_block_exit;
-  friend struct perform_io_cleanup_on_block_exit;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/detail/impl/epoll_reactor.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/epoll_reactor.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_EPOLL)
-
-#endif // ASIO_DETAIL_EPOLL_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/event.hpp b/tools/sdk/include/asio/asio/detail/event.hpp
deleted file mode 100644
index da8fa770b35..00000000000
--- a/tools/sdk/include/asio/asio/detail/event.hpp
+++ /dev/null
@@ -1,48 +0,0 @@
-//
-// detail/event.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_EVENT_HPP
-#define ASIO_DETAIL_EVENT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-# include "asio/detail/null_event.hpp"
-#elif defined(ASIO_WINDOWS)
-# include "asio/detail/win_event.hpp"
-#elif defined(ASIO_HAS_PTHREADS)
-# include "asio/detail/posix_event.hpp"
-#elif defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-# include "asio/detail/std_event.hpp"
-#else
-# error Only Windows, POSIX and std::condition_variable are supported!
-#endif
-
-namespace asio {
-namespace detail {
-
-#if !defined(ASIO_HAS_THREADS)
-typedef null_event event;
-#elif defined(ASIO_WINDOWS)
-typedef win_event event;
-#elif defined(ASIO_HAS_PTHREADS)
-typedef posix_event event;
-#elif defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-typedef std_event event;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_EVENT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/eventfd_select_interrupter.hpp b/tools/sdk/include/asio/asio/detail/eventfd_select_interrupter.hpp
deleted file mode 100644
index f6e594b6112..00000000000
--- a/tools/sdk/include/asio/asio/detail/eventfd_select_interrupter.hpp
+++ /dev/null
@@ -1,83 +0,0 @@
-//
-// detail/eventfd_select_interrupter.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Roelof Naude (roelof.naude at gmail dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_EVENTFD_SELECT_INTERRUPTER_HPP
-#define ASIO_DETAIL_EVENTFD_SELECT_INTERRUPTER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_EVENTFD)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class eventfd_select_interrupter
-{
-public:
-  // Constructor.
-  ASIO_DECL eventfd_select_interrupter();
-
-  // Destructor.
-  ASIO_DECL ~eventfd_select_interrupter();
-
-  // Recreate the interrupter's descriptors. Used after a fork.
-  ASIO_DECL void recreate();
-
-  // Interrupt the select call.
-  ASIO_DECL void interrupt();
-
-  // Reset the select interrupt. Returns true if the call was interrupted.
-  ASIO_DECL bool reset();
-
-  // Get the read descriptor to be passed to select.
-  int read_descriptor() const
-  {
-    return read_descriptor_;
-  }
-
-private:
-  // Open the descriptors. Throws on error.
-  ASIO_DECL void open_descriptors();
-
-  // Close the descriptors.
-  ASIO_DECL void close_descriptors();
-
-  // The read end of a connection used to interrupt the select call. This file
-  // descriptor is passed to select such that when it is time to stop, a single
-  // 64bit value will be written on the other end of the connection and this
-  // descriptor will become readable.
-  int read_descriptor_;
-
-  // The write end of a connection used to interrupt the select call. A single
-  // 64bit non-zero value may be written to this to wake up the select which is
-  // waiting for the other end to become readable. This descriptor will only
-  // differ from the read descriptor when a pipe is used.
-  int write_descriptor_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/eventfd_select_interrupter.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_EVENTFD)
-
-#endif // ASIO_DETAIL_EVENTFD_SELECT_INTERRUPTER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/executor_op.hpp b/tools/sdk/include/asio/asio/detail/executor_op.hpp
deleted file mode 100644
index 2d5c7e8b89d..00000000000
--- a/tools/sdk/include/asio/asio/detail/executor_op.hpp
+++ /dev/null
@@ -1,84 +0,0 @@
-//
-// detail/executor_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_EXECUTOR_OP_HPP
-#define ASIO_DETAIL_EXECUTOR_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/scheduler_operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler, typename Alloc,
-    typename Operation = scheduler_operation>
-class executor_op : public Operation
-{
-public:
-  ASIO_DEFINE_HANDLER_ALLOCATOR_PTR(executor_op);
-
-  template <typename H>
-  executor_op(ASIO_MOVE_ARG(H) h, const Alloc& allocator)
-    : Operation(&executor_op::do_complete),
-      handler_(ASIO_MOVE_CAST(H)(h)),
-      allocator_(allocator)
-  {
-  }
-
-  static void do_complete(void* owner, Operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    executor_op* o(static_cast<executor_op*>(base));
-    Alloc allocator(o->allocator_);
-    ptr p = { detail::addressof(allocator), o, o };
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    Handler handler(ASIO_MOVE_CAST(Handler)(o->handler_));
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN(());
-      asio_handler_invoke_helpers::invoke(handler, handler);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-  Alloc allocator_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_EXECUTOR_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/fd_set_adapter.hpp b/tools/sdk/include/asio/asio/detail/fd_set_adapter.hpp
deleted file mode 100644
index fd373dae1f3..00000000000
--- a/tools/sdk/include/asio/asio/detail/fd_set_adapter.hpp
+++ /dev/null
@@ -1,39 +0,0 @@
-//
-// detail/fd_set_adapter.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_FD_SET_ADAPTER_HPP
-#define ASIO_DETAIL_FD_SET_ADAPTER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/posix_fd_set_adapter.hpp"
-#include "asio/detail/win_fd_set_adapter.hpp"
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-typedef win_fd_set_adapter fd_set_adapter;
-#else
-typedef posix_fd_set_adapter fd_set_adapter;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // !defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_FD_SET_ADAPTER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/fenced_block.hpp b/tools/sdk/include/asio/asio/detail/fenced_block.hpp
deleted file mode 100644
index dc34bd9fb47..00000000000
--- a/tools/sdk/include/asio/asio/detail/fenced_block.hpp
+++ /dev/null
@@ -1,80 +0,0 @@
-//
-// detail/fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS) \
-  || defined(ASIO_DISABLE_FENCED_BLOCK)
-# include "asio/detail/null_fenced_block.hpp"
-#elif defined(ASIO_HAS_STD_ATOMIC)
-# include "asio/detail/std_fenced_block.hpp"
-#elif defined(__MACH__) && defined(__APPLE__)
-# include "asio/detail/macos_fenced_block.hpp"
-#elif defined(__sun)
-# include "asio/detail/solaris_fenced_block.hpp"
-#elif defined(__GNUC__) && defined(__arm__) \
-  && !defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4)
-# include "asio/detail/gcc_arm_fenced_block.hpp"
-#elif defined(__GNUC__) && (defined(__hppa) || defined(__hppa__))
-# include "asio/detail/gcc_hppa_fenced_block.hpp"
-#elif defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
-# include "asio/detail/gcc_x86_fenced_block.hpp"
-#elif defined(__GNUC__) \
-  && ((__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)) \
-  && !defined(__INTEL_COMPILER) && !defined(__ICL) \
-  && !defined(__ICC) && !defined(__ECC) && !defined(__PATHSCALE__)
-# include "asio/detail/gcc_sync_fenced_block.hpp"
-#elif defined(ASIO_WINDOWS) && !defined(UNDER_CE)
-# include "asio/detail/win_fenced_block.hpp"
-#else
-# include "asio/detail/null_fenced_block.hpp"
-#endif
-
-namespace asio {
-namespace detail {
-
-#if !defined(ASIO_HAS_THREADS) \
-  || defined(ASIO_DISABLE_FENCED_BLOCK)
-typedef null_fenced_block fenced_block;
-#elif defined(ASIO_HAS_STD_ATOMIC)
-typedef std_fenced_block fenced_block;
-#elif defined(__MACH__) && defined(__APPLE__)
-typedef macos_fenced_block fenced_block;
-#elif defined(__sun)
-typedef solaris_fenced_block fenced_block;
-#elif defined(__GNUC__) && defined(__arm__) \
-  && !defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4)
-typedef gcc_arm_fenced_block fenced_block;
-#elif defined(__GNUC__) && (defined(__hppa) || defined(__hppa__))
-typedef gcc_hppa_fenced_block fenced_block;
-#elif defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
-typedef gcc_x86_fenced_block fenced_block;
-#elif defined(__GNUC__) \
-  && ((__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)) \
-  && !defined(__INTEL_COMPILER) && !defined(__ICL) \
-  && !defined(__ICC) && !defined(__ECC) && !defined(__PATHSCALE__)
-typedef gcc_sync_fenced_block fenced_block;
-#elif defined(ASIO_WINDOWS) && !defined(UNDER_CE)
-typedef win_fenced_block fenced_block;
-#else
-typedef null_fenced_block fenced_block;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/functional.hpp b/tools/sdk/include/asio/asio/detail/functional.hpp
deleted file mode 100644
index a37e9e63186..00000000000
--- a/tools/sdk/include/asio/asio/detail/functional.hpp
+++ /dev/null
@@ -1,38 +0,0 @@
-//
-// detail/functional.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_FUNCTIONAL_HPP
-#define ASIO_DETAIL_FUNCTIONAL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <functional>
-
-#if !defined(ASIO_HAS_STD_FUNCTION)
-# include <boost/function.hpp>
-#endif // !defined(ASIO_HAS_STD_FUNCTION)
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_HAS_STD_FUNCTION)
-using std::function;
-#else // defined(ASIO_HAS_STD_FUNCTION)
-using boost::function;
-#endif // defined(ASIO_HAS_STD_FUNCTION)
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_FUNCTIONAL_HPP
diff --git a/tools/sdk/include/asio/asio/detail/gcc_arm_fenced_block.hpp b/tools/sdk/include/asio/asio/detail/gcc_arm_fenced_block.hpp
deleted file mode 100644
index 7919a551c70..00000000000
--- a/tools/sdk/include/asio/asio/detail/gcc_arm_fenced_block.hpp
+++ /dev/null
@@ -1,91 +0,0 @@
-//
-// detail/gcc_arm_fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_GCC_ARM_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_GCC_ARM_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(__GNUC__) && defined(__arm__)
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class gcc_arm_fenced_block
-  : private noncopyable
-{
-public:
-  enum half_t { half };
-  enum full_t { full };
-
-  // Constructor for a half fenced block.
-  explicit gcc_arm_fenced_block(half_t)
-  {
-  }
-
-  // Constructor for a full fenced block.
-  explicit gcc_arm_fenced_block(full_t)
-  {
-    barrier();
-  }
-
-  // Destructor.
-  ~gcc_arm_fenced_block()
-  {
-    barrier();
-  }
-
-private:
-  static void barrier()
-  {
-#if defined(__ARM_ARCH_4__) \
-    || defined(__ARM_ARCH_4T__) \
-    || defined(__ARM_ARCH_5__) \
-    || defined(__ARM_ARCH_5E__) \
-    || defined(__ARM_ARCH_5T__) \
-    || defined(__ARM_ARCH_5TE__) \
-    || defined(__ARM_ARCH_5TEJ__) \
-    || defined(__ARM_ARCH_6__) \
-    || defined(__ARM_ARCH_6J__) \
-    || defined(__ARM_ARCH_6K__) \
-    || defined(__ARM_ARCH_6Z__) \
-    || defined(__ARM_ARCH_6ZK__) \
-    || defined(__ARM_ARCH_6T2__)
-# if defined(__thumb__)
-    // This is just a placeholder and almost certainly not sufficient.
-    __asm__ __volatile__ ("" : : : "memory");
-# else // defined(__thumb__)
-    int a = 0, b = 0;
-    __asm__ __volatile__ ("swp %0, %1, [%2]"
-        : "=&r"(a) : "r"(1), "r"(&b) : "memory", "cc");
-# endif // defined(__thumb__)
-#else
-    // ARMv7 and later.
-    __asm__ __volatile__ ("dmb" : : : "memory");
-#endif
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(__GNUC__) && defined(__arm__)
-
-#endif // ASIO_DETAIL_GCC_ARM_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/gcc_hppa_fenced_block.hpp b/tools/sdk/include/asio/asio/detail/gcc_hppa_fenced_block.hpp
deleted file mode 100644
index d3957ce33e6..00000000000
--- a/tools/sdk/include/asio/asio/detail/gcc_hppa_fenced_block.hpp
+++ /dev/null
@@ -1,68 +0,0 @@
-//
-// detail/gcc_hppa_fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_GCC_HPPA_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_GCC_HPPA_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(__GNUC__) && (defined(__hppa) || defined(__hppa__))
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class gcc_hppa_fenced_block
-  : private noncopyable
-{
-public:
-  enum half_t { half };
-  enum full_t { full };
-
-  // Constructor for a half fenced block.
-  explicit gcc_hppa_fenced_block(half_t)
-  {
-  }
-
-  // Constructor for a full fenced block.
-  explicit gcc_hppa_fenced_block(full_t)
-  {
-    barrier();
-  }
-
-  // Destructor.
-  ~gcc_hppa_fenced_block()
-  {
-    barrier();
-  }
-
-private:
-  static void barrier()
-  {
-    // This is just a placeholder and almost certainly not sufficient.
-    __asm__ __volatile__ ("" : : : "memory");
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(__GNUC__) && (defined(__hppa) || defined(__hppa__))
-
-#endif // ASIO_DETAIL_GCC_HPPA_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/gcc_sync_fenced_block.hpp b/tools/sdk/include/asio/asio/detail/gcc_sync_fenced_block.hpp
deleted file mode 100644
index 90d176f12ae..00000000000
--- a/tools/sdk/include/asio/asio/detail/gcc_sync_fenced_block.hpp
+++ /dev/null
@@ -1,65 +0,0 @@
-//
-// detail/gcc_sync_fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_GCC_SYNC_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_GCC_SYNC_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(__GNUC__) \
-  && ((__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)) \
-  && !defined(__INTEL_COMPILER) && !defined(__ICL) \
-  && !defined(__ICC) && !defined(__ECC) && !defined(__PATHSCALE__)
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class gcc_sync_fenced_block
-  : private noncopyable
-{
-public:
-  enum half_or_full_t { half, full };
-
-  // Constructor.
-  explicit gcc_sync_fenced_block(half_or_full_t)
-    : value_(0)
-  {
-    __sync_lock_test_and_set(&value_, 1);
-  }
-
-  // Destructor.
-  ~gcc_sync_fenced_block()
-  {
-    __sync_lock_release(&value_);
-  }
-
-private:
-  int value_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(__GNUC__)
-       // && ((__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4))
-       // && !defined(__INTEL_COMPILER) && !defined(__ICL)
-       // && !defined(__ICC) && !defined(__ECC) && !defined(__PATHSCALE__)
-
-#endif // ASIO_DETAIL_GCC_SYNC_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/gcc_x86_fenced_block.hpp b/tools/sdk/include/asio/asio/detail/gcc_x86_fenced_block.hpp
deleted file mode 100644
index 1366def74e6..00000000000
--- a/tools/sdk/include/asio/asio/detail/gcc_x86_fenced_block.hpp
+++ /dev/null
@@ -1,99 +0,0 @@
-//
-// detail/gcc_x86_fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_GCC_X86_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_GCC_X86_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class gcc_x86_fenced_block
-  : private noncopyable
-{
-public:
-  enum half_t { half };
-  enum full_t { full };
-
-  // Constructor for a half fenced block.
-  explicit gcc_x86_fenced_block(half_t)
-  {
-  }
-
-  // Constructor for a full fenced block.
-  explicit gcc_x86_fenced_block(full_t)
-  {
-    lbarrier();
-  }
-
-  // Destructor.
-  ~gcc_x86_fenced_block()
-  {
-    sbarrier();
-  }
-
-private:
-  static int barrier()
-  {
-    int r = 0, m = 1;
-    __asm__ __volatile__ (
-        "xchgl %0, %1" :
-        "=r"(r), "=m"(m) :
-        "0"(1), "m"(m) :
-        "memory", "cc");
-    return r;
-  }
-
-  static void lbarrier()
-  {
-#if defined(__SSE2__)
-# if (__GNUC__ >= 4) && !defined(__INTEL_COMPILER) && !defined(__ICL)
-    __builtin_ia32_lfence();
-# else // (__GNUC__ >= 4) && !defined(__INTEL_COMPILER) && !defined(__ICL)
-    __asm__ __volatile__ ("lfence" ::: "memory");
-# endif // (__GNUC__ >= 4) && !defined(__INTEL_COMPILER) && !defined(__ICL)
-#else // defined(__SSE2__)
-    barrier();
-#endif // defined(__SSE2__)
-  }
-
-  static void sbarrier()
-  {
-#if defined(__SSE2__)
-# if (__GNUC__ >= 4) && !defined(__INTEL_COMPILER) && !defined(__ICL)
-    __builtin_ia32_sfence();
-# else // (__GNUC__ >= 4) && !defined(__INTEL_COMPILER) && !defined(__ICL)
-    __asm__ __volatile__ ("sfence" ::: "memory");
-# endif // (__GNUC__ >= 4) && !defined(__INTEL_COMPILER) && !defined(__ICL)
-#else // defined(__SSE2__)
-    barrier();
-#endif // defined(__SSE2__)
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
-
-#endif // ASIO_DETAIL_GCC_X86_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/global.hpp b/tools/sdk/include/asio/asio/detail/global.hpp
deleted file mode 100644
index 085ac643d6c..00000000000
--- a/tools/sdk/include/asio/asio/detail/global.hpp
+++ /dev/null
@@ -1,52 +0,0 @@
-//
-// detail/global.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_GLOBAL_HPP
-#define ASIO_DETAIL_GLOBAL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-# include "asio/detail/null_global.hpp"
-#elif defined(ASIO_WINDOWS)
-# include "asio/detail/win_global.hpp"
-#elif defined(ASIO_HAS_PTHREADS)
-# include "asio/detail/posix_global.hpp"
-#elif defined(ASIO_HAS_STD_CALL_ONCE)
-# include "asio/detail/std_global.hpp"
-#else
-# error Only Windows, POSIX and std::call_once are supported!
-#endif
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-inline T& global()
-{
-#if !defined(ASIO_HAS_THREADS)
-  return null_global<T>();
-#elif defined(ASIO_WINDOWS)
-  return win_global<T>();
-#elif defined(ASIO_HAS_PTHREADS)
-  return posix_global<T>();
-#elif defined(ASIO_HAS_STD_CALL_ONCE)
-  return std_global<T>();
-#endif
-}
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_GLOBAL_HPP
diff --git a/tools/sdk/include/asio/asio/detail/handler_alloc_helpers.hpp b/tools/sdk/include/asio/asio/detail/handler_alloc_helpers.hpp
deleted file mode 100644
index afefb4d12d6..00000000000
--- a/tools/sdk/include/asio/asio/detail/handler_alloc_helpers.hpp
+++ /dev/null
@@ -1,235 +0,0 @@
-//
-// detail/handler_alloc_helpers.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_HANDLER_ALLOC_HELPERS_HPP
-#define ASIO_DETAIL_HANDLER_ALLOC_HELPERS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/recycling_allocator.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/handler_alloc_hook.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-// Calls to asio_handler_allocate and asio_handler_deallocate must be made from
-// a namespace that does not contain any overloads of these functions. The
-// asio_handler_alloc_helpers namespace is defined here for that purpose.
-namespace asio_handler_alloc_helpers {
-
-template <typename Handler>
-inline void* allocate(std::size_t s, Handler& h)
-{
-#if !defined(ASIO_HAS_HANDLER_HOOKS)
-  return ::operator new(s);
-#else
-  using asio::asio_handler_allocate;
-  return asio_handler_allocate(s, asio::detail::addressof(h));
-#endif
-}
-
-template <typename Handler>
-inline void deallocate(void* p, std::size_t s, Handler& h)
-{
-#if !defined(ASIO_HAS_HANDLER_HOOKS)
-  ::operator delete(p);
-#else
-  using asio::asio_handler_deallocate;
-  asio_handler_deallocate(p, s, asio::detail::addressof(h));
-#endif
-}
-
-} // namespace asio_handler_alloc_helpers
-
-namespace asio {
-namespace detail {
-
-template <typename Handler, typename T>
-class hook_allocator
-{
-public:
-  typedef T value_type;
-
-  template <typename U>
-  struct rebind
-  {
-    typedef hook_allocator<Handler, U> other;
-  };
-
-  explicit hook_allocator(Handler& h)
-    : handler_(h)
-  {
-  }
-
-  template <typename U>
-  hook_allocator(const hook_allocator<Handler, U>& a)
-    : handler_(a.handler_)
-  {
-  }
-
-  T* allocate(std::size_t n)
-  {
-    return static_cast<T*>(
-        asio_handler_alloc_helpers::allocate(sizeof(T) * n, handler_));
-  }
-
-  void deallocate(T* p, std::size_t n)
-  {
-    asio_handler_alloc_helpers::deallocate(p, sizeof(T) * n, handler_);
-  }
-
-//private:
-  Handler& handler_;
-};
-
-template <typename Handler>
-class hook_allocator<Handler, void>
-{
-public:
-  typedef void value_type;
-
-  template <typename U>
-  struct rebind
-  {
-    typedef hook_allocator<Handler, U> other;
-  };
-
-  explicit hook_allocator(Handler& h)
-    : handler_(h)
-  {
-  }
-
-  template <typename U>
-  hook_allocator(const hook_allocator<Handler, U>& a)
-    : handler_(a.handler_)
-  {
-  }
-
-//private:
-  Handler& handler_;
-};
-
-template <typename Handler, typename Allocator>
-struct get_hook_allocator
-{
-  typedef Allocator type;
-
-  static type get(Handler&, const Allocator& a)
-  {
-    return a;
-  }
-};
-
-template <typename Handler, typename T>
-struct get_hook_allocator<Handler, std::allocator<T> >
-{
-  typedef hook_allocator<Handler, T> type;
-
-  static type get(Handler& handler, const std::allocator<T>&)
-  {
-    return type(handler);
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#define ASIO_DEFINE_HANDLER_PTR(op) \
-  struct ptr \
-  { \
-    Handler* h; \
-    op* v; \
-    op* p; \
-    ~ptr() \
-    { \
-      reset(); \
-    } \
-    static op* allocate(Handler& handler) \
-    { \
-      typedef typename ::asio::associated_allocator< \
-        Handler>::type associated_allocator_type; \
-      typedef typename ::asio::detail::get_hook_allocator< \
-        Handler, associated_allocator_type>::type hook_allocator_type; \
-      ASIO_REBIND_ALLOC(hook_allocator_type, op) a( \
-            ::asio::detail::get_hook_allocator< \
-              Handler, associated_allocator_type>::get( \
-                handler, ::asio::get_associated_allocator(handler))); \
-      return a.allocate(1); \
-    } \
-    void reset() \
-    { \
-      if (p) \
-      { \
-        p->~op(); \
-        p = 0; \
-      } \
-      if (v) \
-      { \
-        typedef typename ::asio::associated_allocator< \
-          Handler>::type associated_allocator_type; \
-        typedef typename ::asio::detail::get_hook_allocator< \
-          Handler, associated_allocator_type>::type hook_allocator_type; \
-        ASIO_REBIND_ALLOC(hook_allocator_type, op) a( \
-              ::asio::detail::get_hook_allocator< \
-                Handler, associated_allocator_type>::get( \
-                  *h, ::asio::get_associated_allocator(*h))); \
-        a.deallocate(static_cast<op*>(v), 1); \
-        v = 0; \
-      } \
-    } \
-  } \
-  /**/
-
-#define ASIO_DEFINE_HANDLER_ALLOCATOR_PTR(op) \
-  struct ptr \
-  { \
-    const Alloc* a; \
-    void* v; \
-    op* p; \
-    ~ptr() \
-    { \
-      reset(); \
-    } \
-    static op* allocate(const Alloc& a) \
-    { \
-      typedef typename ::asio::detail::get_recycling_allocator< \
-        Alloc>::type recycling_allocator_type; \
-      ASIO_REBIND_ALLOC(recycling_allocator_type, op) a1( \
-            ::asio::detail::get_recycling_allocator<Alloc>::get(a)); \
-      return a1.allocate(1); \
-    } \
-    void reset() \
-    { \
-      if (p) \
-      { \
-        p->~op(); \
-        p = 0; \
-      } \
-      if (v) \
-      { \
-        typedef typename ::asio::detail::get_recycling_allocator< \
-          Alloc>::type recycling_allocator_type; \
-        ASIO_REBIND_ALLOC(recycling_allocator_type, op) a1( \
-              ::asio::detail::get_recycling_allocator<Alloc>::get(*a)); \
-        a1.deallocate(static_cast<op*>(v), 1); \
-        v = 0; \
-      } \
-    } \
-  } \
-  /**/
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_HANDLER_ALLOC_HELPERS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/handler_cont_helpers.hpp b/tools/sdk/include/asio/asio/detail/handler_cont_helpers.hpp
deleted file mode 100644
index 110ba944f9f..00000000000
--- a/tools/sdk/include/asio/asio/detail/handler_cont_helpers.hpp
+++ /dev/null
@@ -1,45 +0,0 @@
-//
-// detail/handler_cont_helpers.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_HANDLER_CONT_HELPERS_HPP
-#define ASIO_DETAIL_HANDLER_CONT_HELPERS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/handler_continuation_hook.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-// Calls to asio_handler_is_continuation must be made from a namespace that
-// does not contain overloads of this function. This namespace is defined here
-// for that purpose.
-namespace asio_handler_cont_helpers {
-
-template <typename Context>
-inline bool is_continuation(Context& context)
-{
-#if !defined(ASIO_HAS_HANDLER_HOOKS)
-  return false;
-#else
-  using asio::asio_handler_is_continuation;
-  return asio_handler_is_continuation(
-      asio::detail::addressof(context));
-#endif
-}
-
-} // namespace asio_handler_cont_helpers
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_HANDLER_CONT_HELPERS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/handler_invoke_helpers.hpp b/tools/sdk/include/asio/asio/detail/handler_invoke_helpers.hpp
deleted file mode 100644
index 4c65c4c530c..00000000000
--- a/tools/sdk/include/asio/asio/detail/handler_invoke_helpers.hpp
+++ /dev/null
@@ -1,57 +0,0 @@
-//
-// detail/handler_invoke_helpers.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_HANDLER_INVOKE_HELPERS_HPP
-#define ASIO_DETAIL_HANDLER_INVOKE_HELPERS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/handler_invoke_hook.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-// Calls to asio_handler_invoke must be made from a namespace that does not
-// contain overloads of this function. The asio_handler_invoke_helpers
-// namespace is defined here for that purpose.
-namespace asio_handler_invoke_helpers {
-
-template <typename Function, typename Context>
-inline void invoke(Function& function, Context& context)
-{
-#if !defined(ASIO_HAS_HANDLER_HOOKS)
-  Function tmp(function);
-  tmp();
-#else
-  using asio::asio_handler_invoke;
-  asio_handler_invoke(function, asio::detail::addressof(context));
-#endif
-}
-
-template <typename Function, typename Context>
-inline void invoke(const Function& function, Context& context)
-{
-#if !defined(ASIO_HAS_HANDLER_HOOKS)
-  Function tmp(function);
-  tmp();
-#else
-  using asio::asio_handler_invoke;
-  asio_handler_invoke(function, asio::detail::addressof(context));
-#endif
-}
-
-} // namespace asio_handler_invoke_helpers
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_HANDLER_INVOKE_HELPERS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/handler_tracking.hpp b/tools/sdk/include/asio/asio/detail/handler_tracking.hpp
deleted file mode 100644
index 83f820eca95..00000000000
--- a/tools/sdk/include/asio/asio/detail/handler_tracking.hpp
+++ /dev/null
@@ -1,238 +0,0 @@
-//
-// detail/handler_tracking.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_HANDLER_TRACKING_HPP
-#define ASIO_DETAIL_HANDLER_TRACKING_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-namespace asio {
-
-class execution_context;
-
-} // namespace asio
-
-#if defined(ASIO_CUSTOM_HANDLER_TRACKING)
-# include ASIO_CUSTOM_HANDLER_TRACKING
-#elif defined(ASIO_ENABLE_HANDLER_TRACKING)
-# include "asio/error_code.hpp"
-# include "asio/detail/cstdint.hpp"
-# include "asio/detail/static_mutex.hpp"
-# include "asio/detail/tss_ptr.hpp"
-#endif // defined(ASIO_ENABLE_HANDLER_TRACKING)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_CUSTOM_HANDLER_TRACKING)
-
-// The user-specified header must define the following macros:
-// - ASIO_INHERIT_TRACKED_HANDLER
-// - ASIO_ALSO_INHERIT_TRACKED_HANDLER
-// - ASIO_HANDLER_TRACKING_INIT
-// - ASIO_HANDLER_CREATION(args)
-// - ASIO_HANDLER_COMPLETION(args)
-// - ASIO_HANDLER_INVOCATION_BEGIN(args)
-// - ASIO_HANDLER_INVOCATION_END
-// - ASIO_HANDLER_OPERATION(args)
-// - ASIO_HANDLER_REACTOR_REGISTRATION(args)
-// - ASIO_HANDLER_REACTOR_DEREGISTRATION(args)
-// - ASIO_HANDLER_REACTOR_READ_EVENT
-// - ASIO_HANDLER_REACTOR_WRITE_EVENT
-// - ASIO_HANDLER_REACTOR_ERROR_EVENT
-// - ASIO_HANDLER_REACTOR_EVENTS(args)
-// - ASIO_HANDLER_REACTOR_OPERATION(args)
-
-# if !defined(ASIO_ENABLE_HANDLER_TRACKING)
-#  define ASIO_ENABLE_HANDLER_TRACKING 1
-# endif /// !defined(ASIO_ENABLE_HANDLER_TRACKING)
-
-#elif defined(ASIO_ENABLE_HANDLER_TRACKING)
-
-class handler_tracking
-{
-public:
-  class completion;
-
-  // Base class for objects containing tracked handlers.
-  class tracked_handler
-  {
-  private:
-    // Only the handler_tracking class will have access to the id.
-    friend class handler_tracking;
-    friend class completion;
-    uint64_t id_;
-
-  protected:
-    // Constructor initialises with no id.
-    tracked_handler() : id_(0) {}
-
-    // Prevent deletion through this type.
-    ~tracked_handler() {}
-  };
-
-  // Initialise the tracking system.
-  ASIO_DECL static void init();
-
-  // Record the creation of a tracked handler.
-  ASIO_DECL static void creation(
-      execution_context& context, tracked_handler& h,
-      const char* object_type, void* object,
-      uintmax_t native_handle, const char* op_name);
-
-  class completion
-  {
-  public:
-    // Constructor records that handler is to be invoked with no arguments.
-    ASIO_DECL explicit completion(const tracked_handler& h);
-
-    // Destructor records only when an exception is thrown from the handler, or
-    // if the memory is being freed without the handler having been invoked.
-    ASIO_DECL ~completion();
-
-    // Records that handler is to be invoked with no arguments.
-    ASIO_DECL void invocation_begin();
-
-    // Records that handler is to be invoked with one arguments.
-    ASIO_DECL void invocation_begin(const asio::error_code& ec);
-
-    // Constructor records that handler is to be invoked with two arguments.
-    ASIO_DECL void invocation_begin(
-        const asio::error_code& ec, std::size_t bytes_transferred);
-
-    // Constructor records that handler is to be invoked with two arguments.
-    ASIO_DECL void invocation_begin(
-        const asio::error_code& ec, int signal_number);
-
-    // Constructor records that handler is to be invoked with two arguments.
-    ASIO_DECL void invocation_begin(
-        const asio::error_code& ec, const char* arg);
-
-    // Record that handler invocation has ended.
-    ASIO_DECL void invocation_end();
-
-  private:
-    friend class handler_tracking;
-    uint64_t id_;
-    bool invoked_;
-    completion* next_;
-  };
-
-  // Record an operation that is not directly associated with a handler.
-  ASIO_DECL static void operation(execution_context& context,
-      const char* object_type, void* object,
-      uintmax_t native_handle, const char* op_name);
-
-  // Record that a descriptor has been registered with the reactor.
-  ASIO_DECL static void reactor_registration(execution_context& context,
-      uintmax_t native_handle, uintmax_t registration);
-
-  // Record that a descriptor has been deregistered from the reactor.
-  ASIO_DECL static void reactor_deregistration(execution_context& context,
-      uintmax_t native_handle, uintmax_t registration);
-
-  // Record a reactor-based operation that is associated with a handler.
-  ASIO_DECL static void reactor_events(execution_context& context,
-      uintmax_t registration, unsigned events);
-
-  // Record a reactor-based operation that is associated with a handler.
-  ASIO_DECL static void reactor_operation(
-      const tracked_handler& h, const char* op_name,
-      const asio::error_code& ec);
-
-  // Record a reactor-based operation that is associated with a handler.
-  ASIO_DECL static void reactor_operation(
-      const tracked_handler& h, const char* op_name,
-      const asio::error_code& ec, std::size_t bytes_transferred);
-
-  // Write a line of output.
-  ASIO_DECL static void write_line(const char* format, ...);
-
-private:
-  struct tracking_state;
-  ASIO_DECL static tracking_state* get_state();
-};
-
-# define ASIO_INHERIT_TRACKED_HANDLER \
-  : public asio::detail::handler_tracking::tracked_handler
-
-# define ASIO_ALSO_INHERIT_TRACKED_HANDLER \
-  , public asio::detail::handler_tracking::tracked_handler
-
-# define ASIO_HANDLER_TRACKING_INIT \
-  asio::detail::handler_tracking::init()
-
-# define ASIO_HANDLER_CREATION(args) \
-  asio::detail::handler_tracking::creation args
-
-# define ASIO_HANDLER_COMPLETION(args) \
-  asio::detail::handler_tracking::completion tracked_completion args
-
-# define ASIO_HANDLER_INVOCATION_BEGIN(args) \
-  tracked_completion.invocation_begin args
-
-# define ASIO_HANDLER_INVOCATION_END \
-  tracked_completion.invocation_end()
-
-# define ASIO_HANDLER_OPERATION(args) \
-  asio::detail::handler_tracking::operation args
-
-# define ASIO_HANDLER_REACTOR_REGISTRATION(args) \
-  asio::detail::handler_tracking::reactor_registration args
-
-# define ASIO_HANDLER_REACTOR_DEREGISTRATION(args) \
-  asio::detail::handler_tracking::reactor_deregistration args
-
-# define ASIO_HANDLER_REACTOR_READ_EVENT 1
-# define ASIO_HANDLER_REACTOR_WRITE_EVENT 2
-# define ASIO_HANDLER_REACTOR_ERROR_EVENT 4
-
-# define ASIO_HANDLER_REACTOR_EVENTS(args) \
-  asio::detail::handler_tracking::reactor_events args
-
-# define ASIO_HANDLER_REACTOR_OPERATION(args) \
-  asio::detail::handler_tracking::reactor_operation args
-
-#else // defined(ASIO_ENABLE_HANDLER_TRACKING)
-
-# define ASIO_INHERIT_TRACKED_HANDLER
-# define ASIO_ALSO_INHERIT_TRACKED_HANDLER
-# define ASIO_HANDLER_TRACKING_INIT (void)0
-# define ASIO_HANDLER_CREATION(args) (void)0
-# define ASIO_HANDLER_COMPLETION(args) (void)0
-# define ASIO_HANDLER_INVOCATION_BEGIN(args) (void)0
-# define ASIO_HANDLER_INVOCATION_END (void)0
-# define ASIO_HANDLER_OPERATION(args) (void)0
-# define ASIO_HANDLER_REACTOR_REGISTRATION(args) (void)0
-# define ASIO_HANDLER_REACTOR_DEREGISTRATION(args) (void)0
-# define ASIO_HANDLER_REACTOR_READ_EVENT 0
-# define ASIO_HANDLER_REACTOR_WRITE_EVENT 0
-# define ASIO_HANDLER_REACTOR_ERROR_EVENT 0
-# define ASIO_HANDLER_REACTOR_EVENTS(args) (void)0
-# define ASIO_HANDLER_REACTOR_OPERATION(args) (void)0
-
-#endif // defined(ASIO_ENABLE_HANDLER_TRACKING)
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/handler_tracking.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_HANDLER_TRACKING_HPP
diff --git a/tools/sdk/include/asio/asio/detail/handler_type_requirements.hpp b/tools/sdk/include/asio/asio/detail/handler_type_requirements.hpp
deleted file mode 100644
index 9181bc515e2..00000000000
--- a/tools/sdk/include/asio/asio/detail/handler_type_requirements.hpp
+++ /dev/null
@@ -1,556 +0,0 @@
-//
-// detail/handler_type_requirements.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_HANDLER_TYPE_REQUIREMENTS_HPP
-#define ASIO_DETAIL_HANDLER_TYPE_REQUIREMENTS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-// Older versions of gcc have difficulty compiling the sizeof expressions where
-// we test the handler type requirements. We'll disable checking of handler type
-// requirements for those compilers, but otherwise enable it by default.
-#if !defined(ASIO_DISABLE_HANDLER_TYPE_REQUIREMENTS)
-# if !defined(__GNUC__) || (__GNUC__ >= 4)
-#  define ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS 1
-# endif // !defined(__GNUC__) || (__GNUC__ >= 4)
-#endif // !defined(ASIO_DISABLE_HANDLER_TYPE_REQUIREMENTS)
-
-// With C++0x we can use a combination of enhanced SFINAE and static_assert to
-// generate better template error messages. As this technique is not yet widely
-// portable, we'll only enable it for tested compilers.
-#if !defined(ASIO_DISABLE_HANDLER_TYPE_REQUIREMENTS_ASSERT)
-# if defined(__GNUC__)
-#  if ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-#   if defined(__GXX_EXPERIMENTAL_CXX0X__)
-#    define ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS_ASSERT 1
-#   endif // defined(__GXX_EXPERIMENTAL_CXX0X__)
-#  endif // ((__GNUC__ == 4) && (__GNUC_MINOR__ >= 5)) || (__GNUC__ > 4)
-# endif // defined(__GNUC__)
-# if defined(ASIO_MSVC)
-#  if (_MSC_VER >= 1600)
-#   define ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS_ASSERT 1
-#  endif // (_MSC_VER >= 1600)
-# endif // defined(ASIO_MSVC)
-# if defined(__clang__)
-#  if __has_feature(__cxx_static_assert__)
-#   define ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS_ASSERT 1
-#  endif // __has_feature(cxx_static_assert)
-# endif // defined(__clang__)
-#endif // !defined(ASIO_DISABLE_HANDLER_TYPE_REQUIREMENTS)
-
-#if defined(ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS)
-# include "asio/async_result.hpp"
-#endif // defined(ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS)
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS)
-
-# if defined(ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS_ASSERT)
-
-template <typename Handler>
-auto zero_arg_copyable_handler_test(Handler h, void*)
-  -> decltype(
-    sizeof(Handler(static_cast<const Handler&>(h))),
-    ((h)()),
-    char(0));
-
-template <typename Handler>
-char (&zero_arg_copyable_handler_test(Handler, ...))[2];
-
-template <typename Handler, typename Arg1>
-auto one_arg_handler_test(Handler h, Arg1* a1)
-  -> decltype(
-    sizeof(Handler(ASIO_MOVE_CAST(Handler)(h))),
-    ((h)(*a1)),
-    char(0));
-
-template <typename Handler>
-char (&one_arg_handler_test(Handler h, ...))[2];
-
-template <typename Handler, typename Arg1, typename Arg2>
-auto two_arg_handler_test(Handler h, Arg1* a1, Arg2* a2)
-  -> decltype(
-    sizeof(Handler(ASIO_MOVE_CAST(Handler)(h))),
-    ((h)(*a1, *a2)),
-    char(0));
-
-template <typename Handler>
-char (&two_arg_handler_test(Handler, ...))[2];
-
-template <typename Handler, typename Arg1, typename Arg2>
-auto two_arg_move_handler_test(Handler h, Arg1* a1, Arg2* a2)
-  -> decltype(
-    sizeof(Handler(ASIO_MOVE_CAST(Handler)(h))),
-    ((h)(*a1, ASIO_MOVE_CAST(Arg2)(*a2))),
-    char(0));
-
-template <typename Handler>
-char (&two_arg_move_handler_test(Handler, ...))[2];
-
-#  define ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT(expr, msg) \
-     static_assert(expr, msg);
-
-# else // defined(ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS_ASSERT)
-
-#  define ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT(expr, msg)
-
-# endif // defined(ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS_ASSERT)
-
-template <typename T> T& lvref();
-template <typename T> T& lvref(T);
-template <typename T> const T& clvref();
-template <typename T> const T& clvref(T);
-#if defined(ASIO_HAS_MOVE)
-template <typename T> T rvref();
-template <typename T> T rvref(T);
-#else // defined(ASIO_HAS_MOVE)
-template <typename T> const T& rvref();
-template <typename T> const T& rvref(T);
-#endif // defined(ASIO_HAS_MOVE)
-template <typename T> char argbyv(T);
-
-template <int>
-struct handler_type_requirements
-{
-};
-
-#define ASIO_LEGACY_COMPLETION_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void()) asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::zero_arg_copyable_handler_test( \
-          asio::detail::clvref< \
-            asio_true_handler_type>(), 0)) == 1, \
-      "CompletionHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::clvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()(), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_READ_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code, std::size_t)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::two_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0), \
-          static_cast<const std::size_t*>(0))) == 1, \
-      "ReadHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>(), \
-            asio::detail::lvref<const std::size_t>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_WRITE_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code, std::size_t)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::two_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0), \
-          static_cast<const std::size_t*>(0))) == 1, \
-      "WriteHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>(), \
-            asio::detail::lvref<const std::size_t>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_ACCEPT_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::one_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0))) == 1, \
-      "AcceptHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_MOVE_ACCEPT_HANDLER_CHECK( \
-    handler_type, handler, socket_type) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code, socket_type)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::two_arg_move_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0), \
-          static_cast<socket_type*>(0))) == 1, \
-      "MoveAcceptHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>(), \
-            asio::detail::rvref<socket_type>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_CONNECT_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::one_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0))) == 1, \
-      "ConnectHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_RANGE_CONNECT_HANDLER_CHECK( \
-    handler_type, handler, endpoint_type) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code, endpoint_type)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::two_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0), \
-          static_cast<const endpoint_type*>(0))) == 1, \
-      "RangeConnectHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>(), \
-            asio::detail::lvref<const endpoint_type>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_ITERATOR_CONNECT_HANDLER_CHECK( \
-    handler_type, handler, iter_type) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code, iter_type)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::two_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0), \
-          static_cast<const iter_type*>(0))) == 1, \
-      "IteratorConnectHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>(), \
-            asio::detail::lvref<const iter_type>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_RESOLVE_HANDLER_CHECK( \
-    handler_type, handler, range_type) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code, range_type)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::two_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0), \
-          static_cast<const range_type*>(0))) == 1, \
-      "ResolveHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>(), \
-            asio::detail::lvref<const range_type>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_WAIT_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::one_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0))) == 1, \
-      "WaitHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_SIGNAL_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code, int)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::two_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0), \
-          static_cast<const int*>(0))) == 1, \
-      "SignalHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>(), \
-            asio::detail::lvref<const int>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_HANDSHAKE_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::one_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0))) == 1, \
-      "HandshakeHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_BUFFERED_HANDSHAKE_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code, std::size_t)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::two_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0), \
-          static_cast<const std::size_t*>(0))) == 1, \
-      "BufferedHandshakeHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-          asio::detail::lvref<const asio::error_code>(), \
-          asio::detail::lvref<const std::size_t>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#define ASIO_SHUTDOWN_HANDLER_CHECK( \
-    handler_type, handler) \
-  \
-  typedef ASIO_HANDLER_TYPE(handler_type, \
-      void(asio::error_code)) \
-    asio_true_handler_type; \
-  \
-  ASIO_HANDLER_TYPE_REQUIREMENTS_ASSERT( \
-      sizeof(asio::detail::one_arg_handler_test( \
-          asio::detail::rvref< \
-            asio_true_handler_type>(), \
-          static_cast<const asio::error_code*>(0))) == 1, \
-      "ShutdownHandler type requirements not met") \
-  \
-  typedef asio::detail::handler_type_requirements< \
-      sizeof( \
-        asio::detail::argbyv( \
-          asio::detail::rvref< \
-            asio_true_handler_type>())) + \
-      sizeof( \
-        asio::detail::lvref< \
-          asio_true_handler_type>()( \
-            asio::detail::lvref<const asio::error_code>()), \
-        char(0))> ASIO_UNUSED_TYPEDEF
-
-#else // !defined(ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS)
-
-#define ASIO_LEGACY_COMPLETION_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_READ_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_WRITE_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_ACCEPT_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_MOVE_ACCEPT_HANDLER_CHECK( \
-    handler_type, handler, socket_type) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_CONNECT_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_RANGE_CONNECT_HANDLER_CHECK( \
-    handler_type, handler, iter_type) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_ITERATOR_CONNECT_HANDLER_CHECK( \
-    handler_type, handler, iter_type) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_RESOLVE_HANDLER_CHECK( \
-    handler_type, handler, iter_type) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_WAIT_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_SIGNAL_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_HANDSHAKE_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_BUFFERED_HANDSHAKE_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#define ASIO_SHUTDOWN_HANDLER_CHECK( \
-    handler_type, handler) \
-  typedef int ASIO_UNUSED_TYPEDEF
-
-#endif // !defined(ASIO_ENABLE_HANDLER_TYPE_REQUIREMENTS)
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_HANDLER_TYPE_REQUIREMENTS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/handler_work.hpp b/tools/sdk/include/asio/asio/detail/handler_work.hpp
deleted file mode 100644
index cce5c4b6de2..00000000000
--- a/tools/sdk/include/asio/asio/detail/handler_work.hpp
+++ /dev/null
@@ -1,95 +0,0 @@
-//
-// detail/handler_work.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_HANDLER_WORK_HPP
-#define ASIO_DETAIL_HANDLER_WORK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// A helper class template to allow completion handlers to be dispatched
-// through either the new executors framework or the old invocaton hook. The
-// primary template uses the new executors framework.
-template <typename Handler, typename Executor
-    = typename associated_executor<Handler>::type>
-class handler_work
-{
-public:
-  explicit handler_work(Handler& handler) ASIO_NOEXCEPT
-    : executor_(associated_executor<Handler>::get(handler))
-  {
-  }
-
-  static void start(Handler& handler) ASIO_NOEXCEPT
-  {
-    Executor ex(associated_executor<Handler>::get(handler));
-    ex.on_work_started();
-  }
-
-  ~handler_work()
-  {
-    executor_.on_work_finished();
-  }
-
-  template <typename Function>
-  void complete(Function& function, Handler& handler)
-  {
-    executor_.dispatch(ASIO_MOVE_CAST(Function)(function),
-        associated_allocator<Handler>::get(handler));
-  }
-
-private:
-  // Disallow copying and assignment.
-  handler_work(const handler_work&);
-  handler_work& operator=(const handler_work&);
-
-  typename associated_executor<Handler>::type executor_;
-};
-
-// This specialisation dispatches a handler through the old invocation hook.
-// The specialisation is not strictly required for correctness, as the
-// system_executor will dispatch through the hook anyway. However, by doing
-// this we avoid an extra copy of the handler.
-template <typename Handler>
-class handler_work<Handler, system_executor>
-{
-public:
-  explicit handler_work(Handler&) ASIO_NOEXCEPT {}
-  static void start(Handler&) ASIO_NOEXCEPT {}
-  ~handler_work() {}
-
-  template <typename Function>
-  void complete(Function& function, Handler& handler)
-  {
-    asio_handler_invoke_helpers::invoke(function, handler);
-  }
-
-private:
-  // Disallow copying and assignment.
-  handler_work(const handler_work&);
-  handler_work& operator=(const handler_work&);
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_HANDLER_WORK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/hash_map.hpp b/tools/sdk/include/asio/asio/detail/hash_map.hpp
deleted file mode 100644
index e70970d6b14..00000000000
--- a/tools/sdk/include/asio/asio/detail/hash_map.hpp
+++ /dev/null
@@ -1,331 +0,0 @@
-//
-// detail/hash_map.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_HASH_MAP_HPP
-#define ASIO_DETAIL_HASH_MAP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <list>
-#include <utility>
-#include "asio/detail/assert.hpp"
-#include "asio/detail/noncopyable.hpp"
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-# include "asio/detail/socket_types.hpp"
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-inline std::size_t calculate_hash_value(int i)
-{
-  return static_cast<std::size_t>(i);
-}
-
-inline std::size_t calculate_hash_value(void* p)
-{
-  return reinterpret_cast<std::size_t>(p)
-    + (reinterpret_cast<std::size_t>(p) >> 3);
-}
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-inline std::size_t calculate_hash_value(SOCKET s)
-{
-  return static_cast<std::size_t>(s);
-}
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-// Note: assumes K and V are POD types.
-template <typename K, typename V>
-class hash_map
-  : private noncopyable
-{
-public:
-  // The type of a value in the map.
-  typedef std::pair<K, V> value_type;
-
-  // The type of a non-const iterator over the hash map.
-  typedef typename std::list<value_type>::iterator iterator;
-
-  // The type of a const iterator over the hash map.
-  typedef typename std::list<value_type>::const_iterator const_iterator;
-
-  // Constructor.
-  hash_map()
-    : size_(0),
-      buckets_(0),
-      num_buckets_(0)
-  {
-  }
-
-  // Destructor.
-  ~hash_map()
-  {
-    delete[] buckets_;
-  }
-
-  // Get an iterator for the beginning of the map.
-  iterator begin()
-  {
-    return values_.begin();
-  }
-
-  // Get an iterator for the beginning of the map.
-  const_iterator begin() const
-  {
-    return values_.begin();
-  }
-
-  // Get an iterator for the end of the map.
-  iterator end()
-  {
-    return values_.end();
-  }
-
-  // Get an iterator for the end of the map.
-  const_iterator end() const
-  {
-    return values_.end();
-  }
-
-  // Check whether the map is empty.
-  bool empty() const
-  {
-    return values_.empty();
-  }
-
-  // Find an entry in the map.
-  iterator find(const K& k)
-  {
-    if (num_buckets_)
-    {
-      size_t bucket = calculate_hash_value(k) % num_buckets_;
-      iterator it = buckets_[bucket].first;
-      if (it == values_.end())
-        return values_.end();
-      iterator end_it = buckets_[bucket].last;
-      ++end_it;
-      while (it != end_it)
-      {
-        if (it->first == k)
-          return it;
-        ++it;
-      }
-    }
-    return values_.end();
-  }
-
-  // Find an entry in the map.
-  const_iterator find(const K& k) const
-  {
-    if (num_buckets_)
-    {
-      size_t bucket = calculate_hash_value(k) % num_buckets_;
-      const_iterator it = buckets_[bucket].first;
-      if (it == values_.end())
-        return it;
-      const_iterator end_it = buckets_[bucket].last;
-      ++end_it;
-      while (it != end_it)
-      {
-        if (it->first == k)
-          return it;
-        ++it;
-      }
-    }
-    return values_.end();
-  }
-
-  // Insert a new entry into the map.
-  std::pair<iterator, bool> insert(const value_type& v)
-  {
-    if (size_ + 1 >= num_buckets_)
-      rehash(hash_size(size_ + 1));
-    size_t bucket = calculate_hash_value(v.first) % num_buckets_;
-    iterator it = buckets_[bucket].first;
-    if (it == values_.end())
-    {
-      buckets_[bucket].first = buckets_[bucket].last =
-        values_insert(values_.end(), v);
-      ++size_;
-      return std::pair<iterator, bool>(buckets_[bucket].last, true);
-    }
-    iterator end_it = buckets_[bucket].last;
-    ++end_it;
-    while (it != end_it)
-    {
-      if (it->first == v.first)
-        return std::pair<iterator, bool>(it, false);
-      ++it;
-    }
-    buckets_[bucket].last = values_insert(end_it, v);
-    ++size_;
-    return std::pair<iterator, bool>(buckets_[bucket].last, true);
-  }
-
-  // Erase an entry from the map.
-  void erase(iterator it)
-  {
-    ASIO_ASSERT(it != values_.end());
-    ASIO_ASSERT(num_buckets_ != 0);
-
-    size_t bucket = calculate_hash_value(it->first) % num_buckets_;
-    bool is_first = (it == buckets_[bucket].first);
-    bool is_last = (it == buckets_[bucket].last);
-    if (is_first && is_last)
-      buckets_[bucket].first = buckets_[bucket].last = values_.end();
-    else if (is_first)
-      ++buckets_[bucket].first;
-    else if (is_last)
-      --buckets_[bucket].last;
-
-    values_erase(it);
-    --size_;
-  }
-
-  // Erase a key from the map.
-  void erase(const K& k)
-  {
-    iterator it = find(k);
-    if (it != values_.end())
-      erase(it);
-  }
-
-  // Remove all entries from the map.
-  void clear()
-  {
-    // Clear the values.
-    values_.clear();
-    size_ = 0;
-
-    // Initialise all buckets to empty.
-    iterator end_it = values_.end();
-    for (size_t i = 0; i < num_buckets_; ++i)
-      buckets_[i].first = buckets_[i].last = end_it;
-  }
-
-private:
-  // Calculate the hash size for the specified number of elements.
-  static std::size_t hash_size(std::size_t num_elems)
-  {
-    static std::size_t sizes[] =
-    {
-#if defined(ASIO_HASH_MAP_BUCKETS)
-      ASIO_HASH_MAP_BUCKETS
-#else // ASIO_HASH_MAP_BUCKETS
-      3, 13, 23, 53, 97, 193, 389, 769, 1543, 3079, 6151, 12289, 24593,
-      49157, 98317, 196613, 393241, 786433, 1572869, 3145739, 6291469,
-      12582917, 25165843
-#endif // ASIO_HASH_MAP_BUCKETS
-    };
-    const std::size_t nth_size = sizeof(sizes) / sizeof(std::size_t) - 1;
-    for (std::size_t i = 0; i < nth_size; ++i)
-      if (num_elems < sizes[i])
-        return sizes[i];
-    return sizes[nth_size];
-  }
-
-  // Re-initialise the hash from the values already contained in the list.
-  void rehash(std::size_t num_buckets)
-  {
-    if (num_buckets == num_buckets_)
-      return;
-    ASIO_ASSERT(num_buckets != 0);
-
-    iterator end_iter = values_.end();
-
-    // Update number of buckets and initialise all buckets to empty.
-    bucket_type* tmp = new bucket_type[num_buckets];
-    delete[] buckets_;
-    buckets_ = tmp;
-    num_buckets_ = num_buckets;
-    for (std::size_t i = 0; i < num_buckets_; ++i)
-      buckets_[i].first = buckets_[i].last = end_iter;
-
-    // Put all values back into the hash.
-    iterator iter = values_.begin();
-    while (iter != end_iter)
-    {
-      std::size_t bucket = calculate_hash_value(iter->first) % num_buckets_;
-      if (buckets_[bucket].last == end_iter)
-      {
-        buckets_[bucket].first = buckets_[bucket].last = iter++;
-      }
-      else if (++buckets_[bucket].last == iter)
-      {
-        ++iter;
-      }
-      else
-      {
-        values_.splice(buckets_[bucket].last, values_, iter++);
-        --buckets_[bucket].last;
-      }
-    }
-  }
-
-  // Insert an element into the values list by splicing from the spares list,
-  // if a spare is available, and otherwise by inserting a new element.
-  iterator values_insert(iterator it, const value_type& v)
-  {
-    if (spares_.empty())
-    {
-      return values_.insert(it, v);
-    }
-    else
-    {
-      spares_.front() = v;
-      values_.splice(it, spares_, spares_.begin());
-      return --it;
-    }
-  }
-
-  // Erase an element from the values list by splicing it to the spares list.
-  void values_erase(iterator it)
-  {
-    *it = value_type();
-    spares_.splice(spares_.begin(), values_, it);
-  }
-
-  // The number of elements in the hash.
-  std::size_t size_;
-
-  // The list of all values in the hash map.
-  std::list<value_type> values_;
-
-  // The list of spare nodes waiting to be recycled. Assumes that POD types only
-  // are stored in the hash map.
-  std::list<value_type> spares_;
-
-  // The type for a bucket in the hash table.
-  struct bucket_type
-  {
-    iterator first;
-    iterator last;
-  };
-
-  // The buckets in the hash.
-  bucket_type* buckets_;
-
-  // The number of buckets in the hash.
-  std::size_t num_buckets_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_HASH_MAP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/impl/dev_poll_reactor.hpp b/tools/sdk/include/asio/asio/detail/impl/dev_poll_reactor.hpp
deleted file mode 100644
index 4cd8aafec21..00000000000
--- a/tools/sdk/include/asio/asio/detail/impl/dev_poll_reactor.hpp
+++ /dev/null
@@ -1,91 +0,0 @@
-//
-// detail/impl/dev_poll_reactor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IMPL_DEV_POLL_REACTOR_HPP
-#define ASIO_DETAIL_IMPL_DEV_POLL_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_DEV_POLL)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Time_Traits>
-void dev_poll_reactor::add_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_add_timer_queue(queue);
-}
-
-template <typename Time_Traits>
-void dev_poll_reactor::remove_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_remove_timer_queue(queue);
-}
-
-template <typename Time_Traits>
-void dev_poll_reactor::schedule_timer(timer_queue<Time_Traits>& queue,
-    const typename Time_Traits::time_type& time,
-    typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op)
-{
-  asio::detail::mutex::scoped_lock lock(mutex_);
-
-  if (shutdown_)
-  {
-    scheduler_.post_immediate_completion(op, false);
-    return;
-  }
-
-  bool earliest = queue.enqueue_timer(time, timer, op);
-  scheduler_.work_started();
-  if (earliest)
-    interrupter_.interrupt();
-}
-
-template <typename Time_Traits>
-std::size_t dev_poll_reactor::cancel_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& timer,
-    std::size_t max_cancelled)
-{
-  asio::detail::mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  std::size_t n = queue.cancel_timer(timer, ops, max_cancelled);
-  lock.unlock();
-  scheduler_.post_deferred_completions(ops);
-  return n;
-}
-
-template <typename Time_Traits>
-void dev_poll_reactor::move_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& target,
-    typename timer_queue<Time_Traits>::per_timer_data& source)
-{
-  asio::detail::mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  queue.cancel_timer(target, ops);
-  queue.move_timer(target, source);
-  lock.unlock();
-  scheduler_.post_deferred_completions(ops);
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_DEV_POLL)
-
-#endif // ASIO_DETAIL_IMPL_DEV_POLL_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/impl/epoll_reactor.hpp b/tools/sdk/include/asio/asio/detail/impl/epoll_reactor.hpp
deleted file mode 100644
index f990059d828..00000000000
--- a/tools/sdk/include/asio/asio/detail/impl/epoll_reactor.hpp
+++ /dev/null
@@ -1,89 +0,0 @@
-//
-// detail/impl/epoll_reactor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IMPL_EPOLL_REACTOR_HPP
-#define ASIO_DETAIL_IMPL_EPOLL_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#if defined(ASIO_HAS_EPOLL)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Time_Traits>
-void epoll_reactor::add_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_add_timer_queue(queue);
-}
-
-template <typename Time_Traits>
-void epoll_reactor::remove_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_remove_timer_queue(queue);
-}
-
-template <typename Time_Traits>
-void epoll_reactor::schedule_timer(timer_queue<Time_Traits>& queue,
-    const typename Time_Traits::time_type& time,
-    typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op)
-{
-  mutex::scoped_lock lock(mutex_);
-
-  if (shutdown_)
-  {
-    scheduler_.post_immediate_completion(op, false);
-    return;
-  }
-
-  bool earliest = queue.enqueue_timer(time, timer, op);
-  scheduler_.work_started();
-  if (earliest)
-    update_timeout();
-}
-
-template <typename Time_Traits>
-std::size_t epoll_reactor::cancel_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& timer,
-    std::size_t max_cancelled)
-{
-  mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  std::size_t n = queue.cancel_timer(timer, ops, max_cancelled);
-  lock.unlock();
-  scheduler_.post_deferred_completions(ops);
-  return n;
-}
-
-template <typename Time_Traits>
-void epoll_reactor::move_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& target,
-    typename timer_queue<Time_Traits>::per_timer_data& source)
-{
-  mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  queue.cancel_timer(target, ops);
-  queue.move_timer(target, source);
-  lock.unlock();
-  scheduler_.post_deferred_completions(ops);
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_EPOLL)
-
-#endif // ASIO_DETAIL_IMPL_EPOLL_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/impl/kqueue_reactor.hpp b/tools/sdk/include/asio/asio/detail/impl/kqueue_reactor.hpp
deleted file mode 100644
index 136d1678d34..00000000000
--- a/tools/sdk/include/asio/asio/detail/impl/kqueue_reactor.hpp
+++ /dev/null
@@ -1,93 +0,0 @@
-//
-// detail/impl/kqueue_reactor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2005 Stefan Arentz (stefan at soze dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IMPL_KQUEUE_REACTOR_HPP
-#define ASIO_DETAIL_IMPL_KQUEUE_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_KQUEUE)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Time_Traits>
-void kqueue_reactor::add_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_add_timer_queue(queue);
-}
-
-// Remove a timer queue from the reactor.
-template <typename Time_Traits>
-void kqueue_reactor::remove_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_remove_timer_queue(queue);
-}
-
-template <typename Time_Traits>
-void kqueue_reactor::schedule_timer(timer_queue<Time_Traits>& queue,
-    const typename Time_Traits::time_type& time,
-    typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op)
-{
-  mutex::scoped_lock lock(mutex_);
-
-  if (shutdown_)
-  {
-    scheduler_.post_immediate_completion(op, false);
-    return;
-  }
-
-  bool earliest = queue.enqueue_timer(time, timer, op);
-  scheduler_.work_started();
-  if (earliest)
-    interrupt();
-}
-
-template <typename Time_Traits>
-std::size_t kqueue_reactor::cancel_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& timer,
-    std::size_t max_cancelled)
-{
-  mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  std::size_t n = queue.cancel_timer(timer, ops, max_cancelled);
-  lock.unlock();
-  scheduler_.post_deferred_completions(ops);
-  return n;
-}
-
-template <typename Time_Traits>
-void kqueue_reactor::move_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& target,
-    typename timer_queue<Time_Traits>::per_timer_data& source)
-{
-  mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  queue.cancel_timer(target, ops);
-  queue.move_timer(target, source);
-  lock.unlock();
-  scheduler_.post_deferred_completions(ops);
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_KQUEUE)
-
-#endif // ASIO_DETAIL_IMPL_KQUEUE_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/impl/select_reactor.hpp b/tools/sdk/include/asio/asio/detail/impl/select_reactor.hpp
deleted file mode 100644
index 04a04d49f8c..00000000000
--- a/tools/sdk/include/asio/asio/detail/impl/select_reactor.hpp
+++ /dev/null
@@ -1,100 +0,0 @@
-//
-// detail/impl/select_reactor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IMPL_SELECT_REACTOR_HPP
-#define ASIO_DETAIL_IMPL_SELECT_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP) \
-  || (!defined(ASIO_HAS_DEV_POLL) \
-      && !defined(ASIO_HAS_EPOLL) \
-      && !defined(ASIO_HAS_KQUEUE) \
-      && !defined(ASIO_WINDOWS_RUNTIME))
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Time_Traits>
-void select_reactor::add_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_add_timer_queue(queue);
-}
-
-// Remove a timer queue from the reactor.
-template <typename Time_Traits>
-void select_reactor::remove_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_remove_timer_queue(queue);
-}
-
-template <typename Time_Traits>
-void select_reactor::schedule_timer(timer_queue<Time_Traits>& queue,
-    const typename Time_Traits::time_type& time,
-    typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op)
-{
-  asio::detail::mutex::scoped_lock lock(mutex_);
-
-  if (shutdown_)
-  {
-    scheduler_.post_immediate_completion(op, false);
-    return;
-  }
-
-  bool earliest = queue.enqueue_timer(time, timer, op);
-  scheduler_.work_started();
-  if (earliest)
-    interrupter_.interrupt();
-}
-
-template <typename Time_Traits>
-std::size_t select_reactor::cancel_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& timer,
-    std::size_t max_cancelled)
-{
-  asio::detail::mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  std::size_t n = queue.cancel_timer(timer, ops, max_cancelled);
-  lock.unlock();
-  scheduler_.post_deferred_completions(ops);
-  return n;
-}
-
-template <typename Time_Traits>
-void select_reactor::move_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& target,
-    typename timer_queue<Time_Traits>::per_timer_data& source)
-{
-  asio::detail::mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  queue.cancel_timer(target, ops);
-  queue.move_timer(target, source);
-  lock.unlock();
-  scheduler_.post_deferred_completions(ops);
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-       //   || (!defined(ASIO_HAS_DEV_POLL)
-       //       && !defined(ASIO_HAS_EPOLL)
-       //       && !defined(ASIO_HAS_KQUEUE)
-       //       && !defined(ASIO_WINDOWS_RUNTIME))
-
-#endif // ASIO_DETAIL_IMPL_SELECT_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/impl/service_registry.hpp b/tools/sdk/include/asio/asio/detail/impl/service_registry.hpp
deleted file mode 100644
index d4db589947b..00000000000
--- a/tools/sdk/include/asio/asio/detail/impl/service_registry.hpp
+++ /dev/null
@@ -1,94 +0,0 @@
-//
-// detail/impl/service_registry.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IMPL_SERVICE_REGISTRY_HPP
-#define ASIO_DETAIL_IMPL_SERVICE_REGISTRY_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Service>
-Service& service_registry::use_service()
-{
-  execution_context::service::key key;
-  init_key<Service>(key, 0);
-  factory_type factory = &service_registry::create<Service, execution_context>;
-  return *static_cast<Service*>(do_use_service(key, factory, &owner_));
-}
-
-template <typename Service>
-Service& service_registry::use_service(io_context& owner)
-{
-  execution_context::service::key key;
-  init_key<Service>(key, 0);
-  factory_type factory = &service_registry::create<Service, io_context>;
-  return *static_cast<Service*>(do_use_service(key, factory, &owner));
-}
-
-template <typename Service>
-void service_registry::add_service(Service* new_service)
-{
-  execution_context::service::key key;
-  init_key<Service>(key, 0);
-  return do_add_service(key, new_service);
-}
-
-template <typename Service>
-bool service_registry::has_service() const
-{
-  execution_context::service::key key;
-  init_key<Service>(key, 0);
-  return do_has_service(key);
-}
-
-template <typename Service>
-inline void service_registry::init_key(
-    execution_context::service::key& key, ...)
-{
-  init_key_from_id(key, Service::id);
-}
-
-#if !defined(ASIO_NO_TYPEID)
-template <typename Service>
-void service_registry::init_key(execution_context::service::key& key,
-    typename enable_if<
-      is_base_of<typename Service::key_type, Service>::value>::type*)
-{
-  key.type_info_ = &typeid(typeid_wrapper<Service>);
-  key.id_ = 0;
-}
-
-template <typename Service>
-void service_registry::init_key_from_id(execution_context::service::key& key,
-    const service_id<Service>& /*id*/)
-{
-  key.type_info_ = &typeid(typeid_wrapper<Service>);
-  key.id_ = 0;
-}
-#endif // !defined(ASIO_NO_TYPEID)
-
-template <typename Service, typename Owner>
-execution_context::service* service_registry::create(void* owner)
-{
-  return new Service(*static_cast<Owner*>(owner));
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_IMPL_SERVICE_REGISTRY_HPP
diff --git a/tools/sdk/include/asio/asio/detail/impl/strand_executor_service.hpp b/tools/sdk/include/asio/asio/detail/impl/strand_executor_service.hpp
deleted file mode 100644
index 0e18ca05ec9..00000000000
--- a/tools/sdk/include/asio/asio/detail/impl/strand_executor_service.hpp
+++ /dev/null
@@ -1,179 +0,0 @@
-//
-// detail/impl/strand_executor_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IMPL_STRAND_EXECUTOR_SERVICE_HPP
-#define ASIO_DETAIL_IMPL_STRAND_EXECUTOR_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/call_stack.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/recycling_allocator.hpp"
-#include "asio/executor_work_guard.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Executor>
-class strand_executor_service::invoker
-{
-public:
-  invoker(const implementation_type& impl, Executor& ex)
-    : impl_(impl),
-      work_(ex)
-  {
-  }
-
-  invoker(const invoker& other)
-    : impl_(other.impl_),
-      work_(other.work_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  invoker(invoker&& other)
-    : impl_(ASIO_MOVE_CAST(implementation_type)(other.impl_)),
-      work_(ASIO_MOVE_CAST(executor_work_guard<Executor>)(other.work_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  struct on_invoker_exit
-  {
-    invoker* this_;
-
-    ~on_invoker_exit()
-    {
-      this_->impl_->mutex_->lock();
-      this_->impl_->ready_queue_.push(this_->impl_->waiting_queue_);
-      bool more_handlers = this_->impl_->locked_ =
-        !this_->impl_->ready_queue_.empty();
-      this_->impl_->mutex_->unlock();
-
-      if (more_handlers)
-      {
-        Executor ex(this_->work_.get_executor());
-        recycling_allocator<void> allocator;
-        ex.post(ASIO_MOVE_CAST(invoker)(*this_), allocator);
-      }
-    }
-  };
-
-  void operator()()
-  {
-    // Indicate that this strand is executing on the current thread.
-    call_stack<strand_impl>::context ctx(impl_.get());
-
-    // Ensure the next handler, if any, is scheduled on block exit.
-    on_invoker_exit on_exit = { this };
-    (void)on_exit;
-
-    // Run all ready handlers. No lock is required since the ready queue is
-    // accessed only within the strand.
-    asio::error_code ec;
-    while (scheduler_operation* o = impl_->ready_queue_.front())
-    {
-      impl_->ready_queue_.pop();
-      o->complete(impl_.get(), ec, 0);
-    }
-  }
-
-private:
-  implementation_type impl_;
-  executor_work_guard<Executor> work_;
-};
-
-template <typename Executor, typename Function, typename Allocator>
-void strand_executor_service::dispatch(const implementation_type& impl,
-    Executor& ex, ASIO_MOVE_ARG(Function) function, const Allocator& a)
-{
-  typedef typename decay<Function>::type function_type;
-
-  // If we are already in the strand then the function can run immediately.
-  if (call_stack<strand_impl>::contains(impl.get()))
-  {
-    // Make a local, non-const copy of the function.
-    function_type tmp(ASIO_MOVE_CAST(Function)(function));
-
-    fenced_block b(fenced_block::full);
-    asio_handler_invoke_helpers::invoke(tmp, tmp);
-    return;
-  }
-
-  // Allocate and construct an operation to wrap the function.
-  typedef executor_op<function_type, Allocator> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(function), a);
-
-  ASIO_HANDLER_CREATION((impl->service_->context(), *p.p,
-        "strand_executor", impl.get(), 0, "dispatch"));
-
-  // Add the function to the strand and schedule the strand if required.
-  bool first = enqueue(impl, p.p);
-  p.v = p.p = 0;
-  if (first)
-    ex.dispatch(invoker<Executor>(impl, ex), a);
-}
-
-// Request invocation of the given function and return immediately.
-template <typename Executor, typename Function, typename Allocator>
-void strand_executor_service::post(const implementation_type& impl,
-    Executor& ex, ASIO_MOVE_ARG(Function) function, const Allocator& a)
-{
-  typedef typename decay<Function>::type function_type;
-
-  // Allocate and construct an operation to wrap the function.
-  typedef executor_op<function_type, Allocator> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(function), a);
-
-  ASIO_HANDLER_CREATION((impl->service_->context(), *p.p,
-        "strand_executor", impl.get(), 0, "post"));
-
-  // Add the function to the strand and schedule the strand if required.
-  bool first = enqueue(impl, p.p);
-  p.v = p.p = 0;
-  if (first)
-    ex.post(invoker<Executor>(impl, ex), a);
-}
-
-// Request invocation of the given function and return immediately.
-template <typename Executor, typename Function, typename Allocator>
-void strand_executor_service::defer(const implementation_type& impl,
-    Executor& ex, ASIO_MOVE_ARG(Function) function, const Allocator& a)
-{
-  typedef typename decay<Function>::type function_type;
-
-  // Allocate and construct an operation to wrap the function.
-  typedef executor_op<function_type, Allocator> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(function), a);
-
-  ASIO_HANDLER_CREATION((impl->service_->context(), *p.p,
-        "strand_executor", impl.get(), 0, "defer"));
-
-  // Add the function to the strand and schedule the strand if required.
-  bool first = enqueue(impl, p.p);
-  p.v = p.p = 0;
-  if (first)
-    ex.defer(invoker<Executor>(impl, ex), a);
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_IMPL_STRAND_EXECUTOR_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/impl/strand_service.hpp b/tools/sdk/include/asio/asio/detail/impl/strand_service.hpp
deleted file mode 100644
index da5b716946f..00000000000
--- a/tools/sdk/include/asio/asio/detail/impl/strand_service.hpp
+++ /dev/null
@@ -1,118 +0,0 @@
-//
-// detail/impl/strand_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IMPL_STRAND_SERVICE_HPP
-#define ASIO_DETAIL_IMPL_STRAND_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/call_stack.hpp"
-#include "asio/detail/completion_handler.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-inline strand_service::strand_impl::strand_impl()
-  : operation(&strand_service::do_complete),
-    locked_(false)
-{
-}
-
-struct strand_service::on_dispatch_exit
-{
-  io_context_impl* io_context_;
-  strand_impl* impl_;
-
-  ~on_dispatch_exit()
-  {
-    impl_->mutex_.lock();
-    impl_->ready_queue_.push(impl_->waiting_queue_);
-    bool more_handlers = impl_->locked_ = !impl_->ready_queue_.empty();
-    impl_->mutex_.unlock();
-
-    if (more_handlers)
-      io_context_->post_immediate_completion(impl_, false);
-  }
-};
-
-template <typename Handler>
-void strand_service::dispatch(strand_service::implementation_type& impl,
-    Handler& handler)
-{
-  // If we are already in the strand then the handler can run immediately.
-  if (call_stack<strand_impl>::contains(impl))
-  {
-    fenced_block b(fenced_block::full);
-    asio_handler_invoke_helpers::invoke(handler, handler);
-    return;
-  }
-
-  // Allocate and construct an operation to wrap the handler.
-  typedef completion_handler<Handler> op;
-  typename op::ptr p = { asio::detail::addressof(handler),
-    op::ptr::allocate(handler), 0 };
-  p.p = new (p.v) op(handler);
-
-  ASIO_HANDLER_CREATION((this->context(),
-        *p.p, "strand", impl, 0, "dispatch"));
-
-  bool dispatch_immediately = do_dispatch(impl, p.p);
-  operation* o = p.p;
-  p.v = p.p = 0;
-
-  if (dispatch_immediately)
-  {
-    // Indicate that this strand is executing on the current thread.
-    call_stack<strand_impl>::context ctx(impl);
-
-    // Ensure the next handler, if any, is scheduled on block exit.
-    on_dispatch_exit on_exit = { &io_context_, impl };
-    (void)on_exit;
-
-    completion_handler<Handler>::do_complete(
-        &io_context_, o, asio::error_code(), 0);
-  }
-}
-
-// Request the io_context to invoke the given handler and return immediately.
-template <typename Handler>
-void strand_service::post(strand_service::implementation_type& impl,
-    Handler& handler)
-{
-  bool is_continuation =
-    asio_handler_cont_helpers::is_continuation(handler);
-
-  // Allocate and construct an operation to wrap the handler.
-  typedef completion_handler<Handler> op;
-  typename op::ptr p = { asio::detail::addressof(handler),
-    op::ptr::allocate(handler), 0 };
-  p.p = new (p.v) op(handler);
-
-  ASIO_HANDLER_CREATION((this->context(),
-        *p.p, "strand", impl, 0, "post"));
-
-  do_post(impl, p.p, is_continuation);
-  p.v = p.p = 0;
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_IMPL_STRAND_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/impl/win_iocp_io_context.hpp b/tools/sdk/include/asio/asio/detail/impl/win_iocp_io_context.hpp
deleted file mode 100644
index 44887d7c219..00000000000
--- a/tools/sdk/include/asio/asio/detail/impl/win_iocp_io_context.hpp
+++ /dev/null
@@ -1,103 +0,0 @@
-//
-// detail/impl/win_iocp_io_context.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IMPL_WIN_IOCP_IO_CONTEXT_HPP
-#define ASIO_DETAIL_IMPL_WIN_IOCP_IO_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/completion_handler.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Time_Traits>
-void win_iocp_io_context::add_timer_queue(
-    timer_queue<Time_Traits>& queue)
-{
-  do_add_timer_queue(queue);
-}
-
-template <typename Time_Traits>
-void win_iocp_io_context::remove_timer_queue(
-    timer_queue<Time_Traits>& queue)
-{
-  do_remove_timer_queue(queue);
-}
-
-template <typename Time_Traits>
-void win_iocp_io_context::schedule_timer(timer_queue<Time_Traits>& queue,
-    const typename Time_Traits::time_type& time,
-    typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op)
-{
-  // If the service has been shut down we silently discard the timer.
-  if (::InterlockedExchangeAdd(&shutdown_, 0) != 0)
-  {
-    post_immediate_completion(op, false);
-    return;
-  }
-
-  mutex::scoped_lock lock(dispatch_mutex_);
-
-  bool earliest = queue.enqueue_timer(time, timer, op);
-  work_started();
-  if (earliest)
-    update_timeout();
-}
-
-template <typename Time_Traits>
-std::size_t win_iocp_io_context::cancel_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& timer,
-    std::size_t max_cancelled)
-{
-  // If the service has been shut down we silently ignore the cancellation.
-  if (::InterlockedExchangeAdd(&shutdown_, 0) != 0)
-    return 0;
-
-  mutex::scoped_lock lock(dispatch_mutex_);
-  op_queue<win_iocp_operation> ops;
-  std::size_t n = queue.cancel_timer(timer, ops, max_cancelled);
-  post_deferred_completions(ops);
-  return n;
-}
-
-template <typename Time_Traits>
-void win_iocp_io_context::move_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& to,
-    typename timer_queue<Time_Traits>::per_timer_data& from)
-{
-  asio::detail::mutex::scoped_lock lock(dispatch_mutex_);
-  op_queue<operation> ops;
-  queue.cancel_timer(to, ops);
-  queue.move_timer(to, from);
-  lock.unlock();
-  post_deferred_completions(ops);
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_IMPL_WIN_IOCP_IO_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/impl/winrt_timer_scheduler.hpp b/tools/sdk/include/asio/asio/detail/impl/winrt_timer_scheduler.hpp
deleted file mode 100644
index 856378feb09..00000000000
--- a/tools/sdk/include/asio/asio/detail/impl/winrt_timer_scheduler.hpp
+++ /dev/null
@@ -1,92 +0,0 @@
-//
-// detail/impl/winrt_timer_scheduler.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IMPL_WINRT_TIMER_SCHEDULER_HPP
-#define ASIO_DETAIL_IMPL_WINRT_TIMER_SCHEDULER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Time_Traits>
-void winrt_timer_scheduler::add_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_add_timer_queue(queue);
-}
-
-// Remove a timer queue from the reactor.
-template <typename Time_Traits>
-void winrt_timer_scheduler::remove_timer_queue(timer_queue<Time_Traits>& queue)
-{
-  do_remove_timer_queue(queue);
-}
-
-template <typename Time_Traits>
-void winrt_timer_scheduler::schedule_timer(timer_queue<Time_Traits>& queue,
-    const typename Time_Traits::time_type& time,
-    typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op)
-{
-  asio::detail::mutex::scoped_lock lock(mutex_);
-
-  if (shutdown_)
-  {
-    io_context_.post_immediate_completion(op, false);
-    return;
-  }
-
-  bool earliest = queue.enqueue_timer(time, timer, op);
-  io_context_.work_started();
-  if (earliest)
-    event_.signal(lock);
-}
-
-template <typename Time_Traits>
-std::size_t winrt_timer_scheduler::cancel_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& timer,
-    std::size_t max_cancelled)
-{
-  asio::detail::mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  std::size_t n = queue.cancel_timer(timer, ops, max_cancelled);
-  lock.unlock();
-  io_context_.post_deferred_completions(ops);
-  return n;
-}
-
-template <typename Time_Traits>
-void winrt_timer_scheduler::move_timer(timer_queue<Time_Traits>& queue,
-    typename timer_queue<Time_Traits>::per_timer_data& to,
-    typename timer_queue<Time_Traits>::per_timer_data& from)
-{
-  asio::detail::mutex::scoped_lock lock(mutex_);
-  op_queue<operation> ops;
-  queue.cancel_timer(to, ops);
-  queue.move_timer(to, from);
-  lock.unlock();
-  scheduler_.post_deferred_completions(ops);
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_IMPL_WINRT_TIMER_SCHEDULER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/io_control.hpp b/tools/sdk/include/asio/asio/detail/io_control.hpp
deleted file mode 100644
index 12f35e096fb..00000000000
--- a/tools/sdk/include/asio/asio/detail/io_control.hpp
+++ /dev/null
@@ -1,84 +0,0 @@
-//
-// detail/io_control.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IO_CONTROL_HPP
-#define ASIO_DETAIL_IO_CONTROL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-namespace io_control {
-
-// I/O control command for getting number of bytes available.
-class bytes_readable
-{
-public:
-  // Default constructor.
-  bytes_readable()
-    : value_(0)
-  {
-  }
-
-  // Construct with a specific command value.
-  bytes_readable(std::size_t value)
-    : value_(static_cast<detail::ioctl_arg_type>(value))
-  {
-  }
-
-  // Get the name of the IO control command.
-  int name() const
-  {
-    return static_cast<int>(ASIO_OS_DEF(FIONREAD));
-  }
-
-  // Set the value of the I/O control command.
-  void set(std::size_t value)
-  {
-    value_ = static_cast<detail::ioctl_arg_type>(value);
-  }
-
-  // Get the current value of the I/O control command.
-  std::size_t get() const
-  {
-    return static_cast<std::size_t>(value_);
-  }
-
-  // Get the address of the command data.
-  detail::ioctl_arg_type* data()
-  {
-    return &value_;
-  }
-
-  // Get the address of the command data.
-  const detail::ioctl_arg_type* data() const
-  {
-    return &value_;
-  }
-
-private:
-  detail::ioctl_arg_type value_;
-};
-
-} // namespace io_control
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_IO_CONTROL_HPP
diff --git a/tools/sdk/include/asio/asio/detail/is_buffer_sequence.hpp b/tools/sdk/include/asio/asio/detail/is_buffer_sequence.hpp
deleted file mode 100644
index 42ad0ebe1a2..00000000000
--- a/tools/sdk/include/asio/asio/detail/is_buffer_sequence.hpp
+++ /dev/null
@@ -1,239 +0,0 @@
-//
-// detail/is_buffer_sequence.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IS_BUFFER_SEQUENCE_HPP
-#define ASIO_DETAIL_IS_BUFFER_SEQUENCE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-class mutable_buffer;
-class const_buffer;
-
-namespace detail {
-
-struct buffer_sequence_memfns_base
-{
-  void begin();
-  void end();
-  void size();
-  void max_size();
-  void capacity();
-  void data();
-  void prepare();
-  void commit();
-  void consume();
-};
-
-template <typename T>
-struct buffer_sequence_memfns_derived
-  : T, buffer_sequence_memfns_base
-{
-};
-
-template <typename T, T>
-struct buffer_sequence_memfns_check
-{
-};
-
-template <typename>
-char (&begin_memfn_helper(...))[2];
-
-template <typename T>
-char begin_memfn_helper(
-    buffer_sequence_memfns_check<
-      void (buffer_sequence_memfns_base::*)(),
-      &buffer_sequence_memfns_derived<T>::begin>*);
-
-template <typename>
-char (&end_memfn_helper(...))[2];
-
-template <typename T>
-char end_memfn_helper(
-    buffer_sequence_memfns_check<
-      void (buffer_sequence_memfns_base::*)(),
-      &buffer_sequence_memfns_derived<T>::end>*);
-
-template <typename>
-char (&size_memfn_helper(...))[2];
-
-template <typename T>
-char size_memfn_helper(
-    buffer_sequence_memfns_check<
-      void (buffer_sequence_memfns_base::*)(),
-      &buffer_sequence_memfns_derived<T>::size>*);
-
-template <typename>
-char (&max_size_memfn_helper(...))[2];
-
-template <typename T>
-char max_size_memfn_helper(
-    buffer_sequence_memfns_check<
-      void (buffer_sequence_memfns_base::*)(),
-      &buffer_sequence_memfns_derived<T>::max_size>*);
-
-template <typename>
-char (&capacity_memfn_helper(...))[2];
-
-template <typename T>
-char capacity_memfn_helper(
-    buffer_sequence_memfns_check<
-      void (buffer_sequence_memfns_base::*)(),
-      &buffer_sequence_memfns_derived<T>::capacity>*);
-
-template <typename>
-char (&data_memfn_helper(...))[2];
-
-template <typename T>
-char data_memfn_helper(
-    buffer_sequence_memfns_check<
-      void (buffer_sequence_memfns_base::*)(),
-      &buffer_sequence_memfns_derived<T>::data>*);
-
-template <typename>
-char (&prepare_memfn_helper(...))[2];
-
-template <typename T>
-char prepare_memfn_helper(
-    buffer_sequence_memfns_check<
-      void (buffer_sequence_memfns_base::*)(),
-      &buffer_sequence_memfns_derived<T>::prepare>*);
-
-template <typename>
-char (&commit_memfn_helper(...))[2];
-
-template <typename T>
-char commit_memfn_helper(
-    buffer_sequence_memfns_check<
-      void (buffer_sequence_memfns_base::*)(),
-      &buffer_sequence_memfns_derived<T>::commit>*);
-
-template <typename>
-char (&consume_memfn_helper(...))[2];
-
-template <typename T>
-char consume_memfn_helper(
-    buffer_sequence_memfns_check<
-      void (buffer_sequence_memfns_base::*)(),
-      &buffer_sequence_memfns_derived<T>::consume>*);
-
-template <typename, typename>
-char (&buffer_element_type_helper(...))[2];
-
-#if defined(ASIO_HAS_DECL_TYPE)
-
-template <typename T, typename Buffer>
-char buffer_element_type_helper(T* t,
-    typename enable_if<is_convertible<
-      decltype(*buffer_sequence_begin(*t)),
-        Buffer>::value>::type*);
-
-#else // defined(ASIO_HAS_DECL_TYPE)
-
-template <typename T, typename Buffer>
-char buffer_element_type_helper(
-    typename T::const_iterator*,
-    typename enable_if<is_convertible<
-      typename T::value_type, Buffer>::value>::type*);
-
-#endif // defined(ASIO_HAS_DECL_TYPE)
-
-template <typename>
-char (&const_buffers_type_typedef_helper(...))[2];
-
-template <typename T>
-char const_buffers_type_typedef_helper(
-    typename T::const_buffers_type*);
-
-template <typename>
-char (&mutable_buffers_type_typedef_helper(...))[2];
-
-template <typename T>
-char mutable_buffers_type_typedef_helper(
-    typename T::mutable_buffers_type*);
-
-template <typename T, typename Buffer>
-struct is_buffer_sequence_class
-  : integral_constant<bool,
-      sizeof(begin_memfn_helper<T>(0)) != 1 &&
-      sizeof(end_memfn_helper<T>(0)) != 1 &&
-      sizeof(buffer_element_type_helper<T, Buffer>(0, 0)) == 1>
-{
-};
-
-template <typename T, typename Buffer>
-struct is_buffer_sequence
-  : conditional<is_class<T>::value,
-      is_buffer_sequence_class<T, Buffer>,
-      false_type>::type
-{
-};
-
-template <>
-struct is_buffer_sequence<mutable_buffer, mutable_buffer>
-  : true_type
-{
-};
-
-template <>
-struct is_buffer_sequence<mutable_buffer, const_buffer>
-  : true_type
-{
-};
-
-template <>
-struct is_buffer_sequence<const_buffer, const_buffer>
-  : true_type
-{
-};
-
-template <>
-struct is_buffer_sequence<const_buffer, mutable_buffer>
-  : false_type
-{
-};
-
-template <typename T>
-struct is_dynamic_buffer_class
-  : integral_constant<bool,
-      sizeof(size_memfn_helper<T>(0)) != 1 &&
-      sizeof(max_size_memfn_helper<T>(0)) != 1 &&
-      sizeof(capacity_memfn_helper<T>(0)) != 1 &&
-      sizeof(data_memfn_helper<T>(0)) != 1 &&
-      sizeof(consume_memfn_helper<T>(0)) != 1 &&
-      sizeof(prepare_memfn_helper<T>(0)) != 1 &&
-      sizeof(commit_memfn_helper<T>(0)) != 1 &&
-      sizeof(const_buffers_type_typedef_helper<T>(0)) == 1 &&
-      sizeof(mutable_buffers_type_typedef_helper<T>(0)) == 1>
-{
-};
-
-template <typename T>
-struct is_dynamic_buffer
-  : conditional<is_class<T>::value,
-      is_dynamic_buffer_class<T>,
-      false_type>::type
-{
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_IS_BUFFER_SEQUENCE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/is_executor.hpp b/tools/sdk/include/asio/asio/detail/is_executor.hpp
deleted file mode 100644
index 4584dd04bf6..00000000000
--- a/tools/sdk/include/asio/asio/detail/is_executor.hpp
+++ /dev/null
@@ -1,126 +0,0 @@
-//
-// detail/is_executor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_IS_EXECUTOR_HPP
-#define ASIO_DETAIL_IS_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-struct executor_memfns_base
-{
-  void context();
-  void on_work_started();
-  void on_work_finished();
-  void dispatch();
-  void post();
-  void defer();
-};
-
-template <typename T>
-struct executor_memfns_derived
-  : T, executor_memfns_base
-{
-};
-
-template <typename T, T>
-struct executor_memfns_check
-{
-};
-
-template <typename>
-char (&context_memfn_helper(...))[2];
-
-template <typename T>
-char context_memfn_helper(
-    executor_memfns_check<
-      void (executor_memfns_base::*)(),
-      &executor_memfns_derived<T>::context>*);
-
-template <typename>
-char (&on_work_started_memfn_helper(...))[2];
-
-template <typename T>
-char on_work_started_memfn_helper(
-    executor_memfns_check<
-      void (executor_memfns_base::*)(),
-      &executor_memfns_derived<T>::on_work_started>*);
-
-template <typename>
-char (&on_work_finished_memfn_helper(...))[2];
-
-template <typename T>
-char on_work_finished_memfn_helper(
-    executor_memfns_check<
-      void (executor_memfns_base::*)(),
-      &executor_memfns_derived<T>::on_work_finished>*);
-
-template <typename>
-char (&dispatch_memfn_helper(...))[2];
-
-template <typename T>
-char dispatch_memfn_helper(
-    executor_memfns_check<
-      void (executor_memfns_base::*)(),
-      &executor_memfns_derived<T>::dispatch>*);
-
-template <typename>
-char (&post_memfn_helper(...))[2];
-
-template <typename T>
-char post_memfn_helper(
-    executor_memfns_check<
-      void (executor_memfns_base::*)(),
-      &executor_memfns_derived<T>::post>*);
-
-template <typename>
-char (&defer_memfn_helper(...))[2];
-
-template <typename T>
-char defer_memfn_helper(
-    executor_memfns_check<
-      void (executor_memfns_base::*)(),
-      &executor_memfns_derived<T>::defer>*);
-
-template <typename T>
-struct is_executor_class
-  : integral_constant<bool,
-      sizeof(context_memfn_helper<T>(0)) != 1 &&
-      sizeof(on_work_started_memfn_helper<T>(0)) != 1 &&
-      sizeof(on_work_finished_memfn_helper<T>(0)) != 1 &&
-      sizeof(dispatch_memfn_helper<T>(0)) != 1 &&
-      sizeof(post_memfn_helper<T>(0)) != 1 &&
-      sizeof(defer_memfn_helper<T>(0)) != 1>
-{
-};
-
-template <typename T>
-struct is_executor
-  : conditional<is_class<T>::value,
-      is_executor_class<T>,
-      false_type>::type
-{
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_IS_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/keyword_tss_ptr.hpp b/tools/sdk/include/asio/asio/detail/keyword_tss_ptr.hpp
deleted file mode 100644
index 2ae651ab282..00000000000
--- a/tools/sdk/include/asio/asio/detail/keyword_tss_ptr.hpp
+++ /dev/null
@@ -1,70 +0,0 @@
-//
-// detail/keyword_tss_ptr.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_KEYWORD_TSS_PTR_HPP
-#define ASIO_DETAIL_KEYWORD_TSS_PTR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_THREAD_KEYWORD_EXTENSION)
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-class keyword_tss_ptr
-  : private noncopyable
-{
-public:
-  // Constructor.
-  keyword_tss_ptr()
-  {
-  }
-
-  // Destructor.
-  ~keyword_tss_ptr()
-  {
-  }
-
-  // Get the value.
-  operator T*() const
-  {
-    return value_;
-  }
-
-  // Set the value.
-  void operator=(T* value)
-  {
-    value_ = value;
-  }
-
-private:
-  static ASIO_THREAD_KEYWORD T* value_;
-};
-
-template <typename T>
-ASIO_THREAD_KEYWORD T* keyword_tss_ptr<T>::value_;
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_THREAD_KEYWORD_EXTENSION)
-
-#endif // ASIO_DETAIL_KEYWORD_TSS_PTR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/kqueue_reactor.hpp b/tools/sdk/include/asio/asio/detail/kqueue_reactor.hpp
deleted file mode 100644
index 43cb9f9351c..00000000000
--- a/tools/sdk/include/asio/asio/detail/kqueue_reactor.hpp
+++ /dev/null
@@ -1,242 +0,0 @@
-//
-// detail/kqueue_reactor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2005 Stefan Arentz (stefan at soze dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_KQUEUE_REACTOR_HPP
-#define ASIO_DETAIL_KQUEUE_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_KQUEUE)
-
-#include <cstddef>
-#include <sys/types.h>
-#include <sys/event.h>
-#include <sys/time.h>
-#include "asio/detail/limits.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/object_pool.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/select_interrupter.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/timer_queue_base.hpp"
-#include "asio/detail/timer_queue_set.hpp"
-#include "asio/detail/wait_op.hpp"
-#include "asio/error.hpp"
-#include "asio/execution_context.hpp"
-
-// Older versions of Mac OS X may not define EV_OOBAND.
-#if !defined(EV_OOBAND)
-# define EV_OOBAND EV_FLAG1
-#endif // !defined(EV_OOBAND)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class scheduler;
-
-class kqueue_reactor
-  : public execution_context_service_base<kqueue_reactor>
-{
-private:
-  // The mutex type used by this reactor.
-  typedef conditionally_enabled_mutex mutex;
-
-public:
-  enum op_types { read_op = 0, write_op = 1,
-    connect_op = 1, except_op = 2, max_ops = 3 };
-
-  // Per-descriptor queues.
-  struct descriptor_state
-  {
-    descriptor_state(bool locking) : mutex_(locking) {}
-
-    friend class kqueue_reactor;
-    friend class object_pool_access;
-
-    descriptor_state* next_;
-    descriptor_state* prev_;
-
-    mutex mutex_;
-    int descriptor_;
-    int num_kevents_; // 1 == read only, 2 == read and write
-    op_queue<reactor_op> op_queue_[max_ops];
-    bool shutdown_;
-  };
-
-  // Per-descriptor data.
-  typedef descriptor_state* per_descriptor_data;
-
-  // Constructor.
-  ASIO_DECL kqueue_reactor(asio::execution_context& ctx);
-
-  // Destructor.
-  ASIO_DECL ~kqueue_reactor();
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Recreate internal descriptors following a fork.
-  ASIO_DECL void notify_fork(
-      asio::execution_context::fork_event fork_ev);
-
-  // Initialise the task.
-  ASIO_DECL void init_task();
-
-  // Register a socket with the reactor. Returns 0 on success, system error
-  // code on failure.
-  ASIO_DECL int register_descriptor(socket_type descriptor,
-      per_descriptor_data& descriptor_data);
-
-  // Register a descriptor with an associated single operation. Returns 0 on
-  // success, system error code on failure.
-  ASIO_DECL int register_internal_descriptor(
-      int op_type, socket_type descriptor,
-      per_descriptor_data& descriptor_data, reactor_op* op);
-
-  // Move descriptor registration from one descriptor_data object to another.
-  ASIO_DECL void move_descriptor(socket_type descriptor,
-      per_descriptor_data& target_descriptor_data,
-      per_descriptor_data& source_descriptor_data);
-
-  // Post a reactor operation for immediate completion.
-  void post_immediate_completion(reactor_op* op, bool is_continuation)
-  {
-    scheduler_.post_immediate_completion(op, is_continuation);
-  }
-
-  // Start a new operation. The reactor operation will be performed when the
-  // given descriptor is flagged as ready, or an error has occurred.
-  ASIO_DECL void start_op(int op_type, socket_type descriptor,
-      per_descriptor_data& descriptor_data, reactor_op* op,
-      bool is_continuation, bool allow_speculative);
-
-  // Cancel all operations associated with the given descriptor. The
-  // handlers associated with the descriptor will be invoked with the
-  // operation_aborted error.
-  ASIO_DECL void cancel_ops(socket_type descriptor,
-      per_descriptor_data& descriptor_data);
-
-  // Cancel any operations that are running against the descriptor and remove
-  // its registration from the reactor. The reactor resources associated with
-  // the descriptor must be released by calling cleanup_descriptor_data.
-  ASIO_DECL void deregister_descriptor(socket_type descriptor,
-      per_descriptor_data& descriptor_data, bool closing);
-
-  // Remove the descriptor's registration from the reactor. The reactor
-  // resources associated with the descriptor must be released by calling
-  // cleanup_descriptor_data.
-  ASIO_DECL void deregister_internal_descriptor(
-      socket_type descriptor, per_descriptor_data& descriptor_data);
-
-  // Perform any post-deregistration cleanup tasks associated with the
-  // descriptor data.
-  ASIO_DECL void cleanup_descriptor_data(
-      per_descriptor_data& descriptor_data);
-
-  // Add a new timer queue to the reactor.
-  template <typename Time_Traits>
-  void add_timer_queue(timer_queue<Time_Traits>& queue);
-
-  // Remove a timer queue from the reactor.
-  template <typename Time_Traits>
-  void remove_timer_queue(timer_queue<Time_Traits>& queue);
-
-  // Schedule a new operation in the given timer queue to expire at the
-  // specified absolute time.
-  template <typename Time_Traits>
-  void schedule_timer(timer_queue<Time_Traits>& queue,
-      const typename Time_Traits::time_type& time,
-      typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op);
-
-  // Cancel the timer operations associated with the given token. Returns the
-  // number of operations that have been posted or dispatched.
-  template <typename Time_Traits>
-  std::size_t cancel_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& timer,
-      std::size_t max_cancelled = (std::numeric_limits<std::size_t>::max)());
-
-  // Move the timer operations associated with the given timer.
-  template <typename Time_Traits>
-  void move_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& target,
-      typename timer_queue<Time_Traits>::per_timer_data& source);
-
-  // Run the kqueue loop.
-  ASIO_DECL void run(long usec, op_queue<operation>& ops);
-
-  // Interrupt the kqueue loop.
-  ASIO_DECL void interrupt();
-
-private:
-  // Create the kqueue file descriptor. Throws an exception if the descriptor
-  // cannot be created.
-  ASIO_DECL static int do_kqueue_create();
-
-  // Allocate a new descriptor state object.
-  ASIO_DECL descriptor_state* allocate_descriptor_state();
-
-  // Free an existing descriptor state object.
-  ASIO_DECL void free_descriptor_state(descriptor_state* s);
-
-  // Helper function to add a new timer queue.
-  ASIO_DECL void do_add_timer_queue(timer_queue_base& queue);
-
-  // Helper function to remove a timer queue.
-  ASIO_DECL void do_remove_timer_queue(timer_queue_base& queue);
-
-  // Get the timeout value for the kevent call.
-  ASIO_DECL timespec* get_timeout(long usec, timespec& ts);
-
-  // The scheduler used to post completions.
-  scheduler& scheduler_;
-
-  // Mutex to protect access to internal data.
-  mutex mutex_;
-
-  // The kqueue file descriptor.
-  int kqueue_fd_;
-
-  // The interrupter is used to break a blocking kevent call.
-  select_interrupter interrupter_;
-
-  // The timer queues.
-  timer_queue_set timer_queues_;
-
-  // Whether the service has been shut down.
-  bool shutdown_;
-
-  // Mutex to protect access to the registered descriptors.
-  mutex registered_descriptors_mutex_;
-
-  // Keep track of all registered descriptors.
-  object_pool<descriptor_state> registered_descriptors_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/detail/impl/kqueue_reactor.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/kqueue_reactor.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_KQUEUE)
-
-#endif // ASIO_DETAIL_KQUEUE_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/limits.hpp b/tools/sdk/include/asio/asio/detail/limits.hpp
deleted file mode 100644
index d32470d2d35..00000000000
--- a/tools/sdk/include/asio/asio/detail/limits.hpp
+++ /dev/null
@@ -1,26 +0,0 @@
-//
-// detail/limits.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2011 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_LIMITS_HPP
-#define ASIO_DETAIL_LIMITS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_BOOST_LIMITS)
-# include <boost/limits.hpp>
-#else // defined(ASIO_HAS_BOOST_LIMITS)
-# include <limits>
-#endif // defined(ASIO_HAS_BOOST_LIMITS)
-
-#endif // ASIO_DETAIL_LIMITS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/local_free_on_block_exit.hpp b/tools/sdk/include/asio/asio/detail/local_free_on_block_exit.hpp
deleted file mode 100644
index eba6b7771d0..00000000000
--- a/tools/sdk/include/asio/asio/detail/local_free_on_block_exit.hpp
+++ /dev/null
@@ -1,59 +0,0 @@
-//
-// detail/local_free_on_block_exit.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_LOCAL_FREE_ON_BLOCK_EXIT_HPP
-#define ASIO_DETAIL_LOCAL_FREE_ON_BLOCK_EXIT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-#if !defined(ASIO_WINDOWS_APP)
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class local_free_on_block_exit
-  : private noncopyable
-{
-public:
-  // Constructor blocks all signals for the calling thread.
-  explicit local_free_on_block_exit(void* p)
-    : p_(p)
-  {
-  }
-
-  // Destructor restores the previous signal mask.
-  ~local_free_on_block_exit()
-  {
-    ::LocalFree(p_);
-  }
-
-private:
-  void* p_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_WINDOWS_APP)
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-#endif // ASIO_DETAIL_LOCAL_FREE_ON_BLOCK_EXIT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/macos_fenced_block.hpp b/tools/sdk/include/asio/asio/detail/macos_fenced_block.hpp
deleted file mode 100644
index bbac270a46c..00000000000
--- a/tools/sdk/include/asio/asio/detail/macos_fenced_block.hpp
+++ /dev/null
@@ -1,62 +0,0 @@
-//
-// detail/macos_fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_MACOS_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_MACOS_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(__MACH__) && defined(__APPLE__)
-
-#include <libkern/OSAtomic.h>
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class macos_fenced_block
-  : private noncopyable
-{
-public:
-  enum half_t { half };
-  enum full_t { full };
-
-  // Constructor for a half fenced block.
-  explicit macos_fenced_block(half_t)
-  {
-  }
-
-  // Constructor for a full fenced block.
-  explicit macos_fenced_block(full_t)
-  {
-    OSMemoryBarrier();
-  }
-
-  // Destructor.
-  ~macos_fenced_block()
-  {
-    OSMemoryBarrier();
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(__MACH__) && defined(__APPLE__)
-
-#endif // ASIO_DETAIL_MACOS_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/memory.hpp b/tools/sdk/include/asio/asio/detail/memory.hpp
deleted file mode 100644
index b1ec4975faf..00000000000
--- a/tools/sdk/include/asio/asio/detail/memory.hpp
+++ /dev/null
@@ -1,70 +0,0 @@
-//
-// detail/memory.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_MEMORY_HPP
-#define ASIO_DETAIL_MEMORY_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <memory>
-
-#if !defined(ASIO_HAS_STD_SHARED_PTR)
-# include <boost/shared_ptr.hpp>
-# include <boost/weak_ptr.hpp>
-#endif // !defined(ASIO_HAS_STD_SHARED_PTR)
-
-#if !defined(ASIO_HAS_STD_ADDRESSOF)
-# include <boost/utility/addressof.hpp>
-#endif // !defined(ASIO_HAS_STD_ADDRESSOF)
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_HAS_STD_SHARED_PTR)
-using std::shared_ptr;
-using std::weak_ptr;
-#else // defined(ASIO_HAS_STD_SHARED_PTR)
-using boost::shared_ptr;
-using boost::weak_ptr;
-#endif // defined(ASIO_HAS_STD_SHARED_PTR)
-
-#if defined(ASIO_HAS_STD_ADDRESSOF)
-using std::addressof;
-#else // defined(ASIO_HAS_STD_ADDRESSOF)
-using boost::addressof;
-#endif // defined(ASIO_HAS_STD_ADDRESSOF)
-
-} // namespace detail
-
-#if defined(ASIO_HAS_CXX11_ALLOCATORS)
-using std::allocator_arg_t;
-# define ASIO_USES_ALLOCATOR(t) \
-  namespace std { \
-    template <typename Allocator> \
-    struct uses_allocator<t, Allocator> : true_type {}; \
-  } \
-  /**/
-# define ASIO_REBIND_ALLOC(alloc, t) \
-  typename std::allocator_traits<alloc>::template rebind_alloc<t>
-  /**/
-#else // defined(ASIO_HAS_CXX11_ALLOCATORS)
-struct allocator_arg_t {};
-# define ASIO_USES_ALLOCATOR(t)
-# define ASIO_REBIND_ALLOC(alloc, t) \
-  typename alloc::template rebind<t>::other
-  /**/
-#endif // defined(ASIO_HAS_CXX11_ALLOCATORS)
-
-} // namespace asio
-
-#endif // ASIO_DETAIL_MEMORY_HPP
diff --git a/tools/sdk/include/asio/asio/detail/mutex.hpp b/tools/sdk/include/asio/asio/detail/mutex.hpp
deleted file mode 100644
index 2f8f0b1329b..00000000000
--- a/tools/sdk/include/asio/asio/detail/mutex.hpp
+++ /dev/null
@@ -1,48 +0,0 @@
-//
-// detail/mutex.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_MUTEX_HPP
-#define ASIO_DETAIL_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-# include "asio/detail/null_mutex.hpp"
-#elif defined(ASIO_WINDOWS)
-# include "asio/detail/win_mutex.hpp"
-#elif defined(ASIO_HAS_PTHREADS)
-# include "asio/detail/posix_mutex.hpp"
-#elif defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-# include "asio/detail/std_mutex.hpp"
-#else
-# error Only Windows, POSIX and std::mutex are supported!
-#endif
-
-namespace asio {
-namespace detail {
-
-#if !defined(ASIO_HAS_THREADS)
-typedef null_mutex mutex;
-#elif defined(ASIO_WINDOWS)
-typedef win_mutex mutex;
-#elif defined(ASIO_HAS_PTHREADS)
-typedef posix_mutex mutex;
-#elif defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-typedef std_mutex mutex;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/noncopyable.hpp b/tools/sdk/include/asio/asio/detail/noncopyable.hpp
deleted file mode 100644
index 0c038e11ed0..00000000000
--- a/tools/sdk/include/asio/asio/detail/noncopyable.hpp
+++ /dev/null
@@ -1,43 +0,0 @@
-//
-// detail/noncopyable.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NONCOPYABLE_HPP
-#define ASIO_DETAIL_NONCOPYABLE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class noncopyable
-{
-protected:
-  noncopyable() {}
-  ~noncopyable() {}
-private:
-  noncopyable(const noncopyable&);
-  const noncopyable& operator=(const noncopyable&);
-};
-
-} // namespace detail
-
-using asio::detail::noncopyable;
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_NONCOPYABLE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_event.hpp b/tools/sdk/include/asio/asio/detail/null_event.hpp
deleted file mode 100644
index 5686a41e74a..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_event.hpp
+++ /dev/null
@@ -1,100 +0,0 @@
-//
-// detail/null_event.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_EVENT_HPP
-#define ASIO_DETAIL_NULL_EVENT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class null_event
-  : private noncopyable
-{
-public:
-  // Constructor.
-  null_event()
-  {
-  }
-
-  // Destructor.
-  ~null_event()
-  {
-  }
-
-  // Signal the event. (Retained for backward compatibility.)
-  template <typename Lock>
-  void signal(Lock&)
-  {
-  }
-
-  // Signal all waiters.
-  template <typename Lock>
-  void signal_all(Lock&)
-  {
-  }
-
-  // Unlock the mutex and signal one waiter.
-  template <typename Lock>
-  void unlock_and_signal_one(Lock&)
-  {
-  }
-
-  // If there's a waiter, unlock the mutex and signal it.
-  template <typename Lock>
-  bool maybe_unlock_and_signal_one(Lock&)
-  {
-    return false;
-  }
-
-  // Reset the event.
-  template <typename Lock>
-  void clear(Lock&)
-  {
-  }
-
-  // Wait for the event to become signalled.
-  template <typename Lock>
-  void wait(Lock&)
-  {
-    do_wait();
-  }
-
-  // Timed wait for the event to become signalled.
-  template <typename Lock>
-  bool wait_for_usec(Lock&, long usec)
-  {
-    do_wait_for_usec(usec);
-    return true;
-  }
-
-private:
-  ASIO_DECL static void do_wait();
-  ASIO_DECL static void do_wait_for_usec(long usec);
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/null_event.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_NULL_EVENT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_fenced_block.hpp b/tools/sdk/include/asio/asio/detail/null_fenced_block.hpp
deleted file mode 100644
index 0275326b177..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_fenced_block.hpp
+++ /dev/null
@@ -1,47 +0,0 @@
-//
-// detail/null_fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_NULL_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class null_fenced_block
-  : private noncopyable
-{
-public:
-  enum half_or_full_t { half, full };
-
-  // Constructor.
-  explicit null_fenced_block(half_or_full_t)
-  {
-  }
-
-  // Destructor.
-  ~null_fenced_block()
-  {
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_NULL_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_global.hpp b/tools/sdk/include/asio/asio/detail/null_global.hpp
deleted file mode 100644
index 727dd3f4989..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_global.hpp
+++ /dev/null
@@ -1,59 +0,0 @@
-//
-// detail/null_global.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_GLOBAL_HPP
-#define ASIO_DETAIL_NULL_GLOBAL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-struct null_global_impl
-{
-  null_global_impl()
-    : ptr_(0)
-  {
-  }
-
-  // Destructor automatically cleans up the global.
-  ~null_global_impl()
-  {
-    delete ptr_;
-  }
-
-  static null_global_impl instance_;
-  T* ptr_;
-};
-
-template <typename T>
-null_global_impl<T> null_global_impl<T>::instance_;
-
-template <typename T>
-T& null_global()
-{
-  if (null_global_impl<T>::instance_.ptr_ == 0)
-    null_global_impl<T>::instance_.ptr_ = new T;
-  return *null_global_impl<T>::instance_.ptr_;
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_NULL_GLOBAL_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_mutex.hpp b/tools/sdk/include/asio/asio/detail/null_mutex.hpp
deleted file mode 100644
index afe3fc03251..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_mutex.hpp
+++ /dev/null
@@ -1,64 +0,0 @@
-//
-// detail/null_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_MUTEX_HPP
-#define ASIO_DETAIL_NULL_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/scoped_lock.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class null_mutex
-  : private noncopyable
-{
-public:
-  typedef asio::detail::scoped_lock<null_mutex> scoped_lock;
-
-  // Constructor.
-  null_mutex()
-  {
-  }
-
-  // Destructor.
-  ~null_mutex()
-  {
-  }
-
-  // Lock the mutex.
-  void lock()
-  {
-  }
-
-  // Unlock the mutex.
-  void unlock()
-  {
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_HAS_THREADS)
-
-#endif // ASIO_DETAIL_NULL_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_reactor.hpp b/tools/sdk/include/asio/asio/detail/null_reactor.hpp
deleted file mode 100644
index ca3c5fde662..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_reactor.hpp
+++ /dev/null
@@ -1,68 +0,0 @@
-//
-// detail/null_reactor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_REACTOR_HPP
-#define ASIO_DETAIL_NULL_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP) || defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/scheduler_operation.hpp"
-#include "asio/execution_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class null_reactor
-  : public execution_context_service_base<null_reactor>
-{
-public:
-  // Constructor.
-  null_reactor(asio::execution_context& ctx)
-    : execution_context_service_base<null_reactor>(ctx)
-  {
-  }
-
-  // Destructor.
-  ~null_reactor()
-  {
-  }
-
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-  }
-
-  // No-op because should never be called.
-  void run(long /*usec*/, op_queue<scheduler_operation>& /*ops*/)
-  {
-  }
-
-  // No-op.
-  void interrupt()
-  {
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP) || defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_NULL_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_signal_blocker.hpp b/tools/sdk/include/asio/asio/detail/null_signal_blocker.hpp
deleted file mode 100644
index edfe820519e..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_signal_blocker.hpp
+++ /dev/null
@@ -1,69 +0,0 @@
-//
-// detail/null_signal_blocker.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_SIGNAL_BLOCKER_HPP
-#define ASIO_DETAIL_NULL_SIGNAL_BLOCKER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS) \
-  || defined(ASIO_WINDOWS) \
-  || defined(ASIO_WINDOWS_RUNTIME) \
-  || defined(__CYGWIN__) \
-  || defined(__SYMBIAN32__)
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class null_signal_blocker
-  : private noncopyable
-{
-public:
-  // Constructor blocks all signals for the calling thread.
-  null_signal_blocker()
-  {
-  }
-
-  // Destructor restores the previous signal mask.
-  ~null_signal_blocker()
-  {
-  }
-
-  // Block all signals for the calling thread.
-  void block()
-  {
-  }
-
-  // Restore the previous signal mask.
-  void unblock()
-  {
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_HAS_THREADS)
-       // || defined(ASIO_WINDOWS)
-       // || defined(ASIO_WINDOWS_RUNTIME)
-       // || defined(__CYGWIN__)
-       // || defined(__SYMBIAN32__)
-
-#endif // ASIO_DETAIL_NULL_SIGNAL_BLOCKER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_socket_service.hpp b/tools/sdk/include/asio/asio/detail/null_socket_service.hpp
deleted file mode 100644
index 109c6c7bd36..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_socket_service.hpp
+++ /dev/null
@@ -1,508 +0,0 @@
-//
-// detail/null_socket_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_SOCKET_SERVICE_HPP
-#define ASIO_DETAIL_NULL_SOCKET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/buffer.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/socket_base.hpp"
-#include "asio/detail/bind_handler.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Protocol>
-class null_socket_service :
-  public service_base<null_socket_service<Protocol> >
-{
-public:
-  // The protocol type.
-  typedef Protocol protocol_type;
-
-  // The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  // The native type of a socket.
-  typedef int native_handle_type;
-
-  // The implementation type of the socket.
-  struct implementation_type
-  {
-  };
-
-  // Constructor.
-  null_socket_service(asio::io_context& io_context)
-    : service_base<null_socket_service<Protocol> >(io_context),
-      io_context_(io_context)
-  {
-  }
-
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-  }
-
-  // Construct a new socket implementation.
-  void construct(implementation_type&)
-  {
-  }
-
-  // Move-construct a new socket implementation.
-  void move_construct(implementation_type&, implementation_type&)
-  {
-  }
-
-  // Move-assign from another socket implementation.
-  void move_assign(implementation_type&,
-      null_socket_service&, implementation_type&)
-  {
-  }
-
-  // Move-construct a new socket implementation from another protocol type.
-  template <typename Protocol1>
-  void converting_move_construct(implementation_type&,
-      null_socket_service<Protocol1>&,
-      typename null_socket_service<Protocol1>::implementation_type&)
-  {
-  }
-
-  // Destroy a socket implementation.
-  void destroy(implementation_type&)
-  {
-  }
-
-  // Open a new socket implementation.
-  asio::error_code open(implementation_type&,
-      const protocol_type&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Assign a native socket to a socket implementation.
-  asio::error_code assign(implementation_type&, const protocol_type&,
-      const native_handle_type&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Determine whether the socket is open.
-  bool is_open(const implementation_type&) const
-  {
-    return false;
-  }
-
-  // Destroy a socket implementation.
-  asio::error_code close(implementation_type&,
-      asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Release ownership of the socket.
-  native_handle_type release(implementation_type&,
-      asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Get the native socket representation.
-  native_handle_type native_handle(implementation_type&)
-  {
-    return 0;
-  }
-
-  // Cancel all operations associated with the socket.
-  asio::error_code cancel(implementation_type&,
-      asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Determine whether the socket is at the out-of-band data mark.
-  bool at_mark(const implementation_type&,
-      asio::error_code& ec) const
-  {
-    ec = asio::error::operation_not_supported;
-    return false;
-  }
-
-  // Determine the number of bytes available for reading.
-  std::size_t available(const implementation_type&,
-      asio::error_code& ec) const
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Place the socket into the state where it will listen for new connections.
-  asio::error_code listen(implementation_type&,
-      int, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Perform an IO control command on the socket.
-  template <typename IO_Control_Command>
-  asio::error_code io_control(implementation_type&,
-      IO_Control_Command&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the socket.
-  bool non_blocking(const implementation_type&) const
-  {
-    return false;
-  }
-
-  // Sets the non-blocking mode of the socket.
-  asio::error_code non_blocking(implementation_type&,
-      bool, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the native socket implementation.
-  bool native_non_blocking(const implementation_type&) const
-  {
-    return false;
-  }
-
-  // Sets the non-blocking mode of the native socket implementation.
-  asio::error_code native_non_blocking(implementation_type&,
-      bool, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Disable sends or receives on the socket.
-  asio::error_code shutdown(implementation_type&,
-      socket_base::shutdown_type, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Bind the socket to the specified local endpoint.
-  asio::error_code bind(implementation_type&,
-      const endpoint_type&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Set a socket option.
-  template <typename Option>
-  asio::error_code set_option(implementation_type&,
-      const Option&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Set a socket option.
-  template <typename Option>
-  asio::error_code get_option(const implementation_type&,
-      Option&, asio::error_code& ec) const
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Get the local endpoint.
-  endpoint_type local_endpoint(const implementation_type&,
-      asio::error_code& ec) const
-  {
-    ec = asio::error::operation_not_supported;
-    return endpoint_type();
-  }
-
-  // Get the remote endpoint.
-  endpoint_type remote_endpoint(const implementation_type&,
-      asio::error_code& ec) const
-  {
-    ec = asio::error::operation_not_supported;
-    return endpoint_type();
-  }
-
-  // Send the given data to the peer.
-  template <typename ConstBufferSequence>
-  std::size_t send(implementation_type&, const ConstBufferSequence&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Wait until data can be sent without blocking.
-  std::size_t send(implementation_type&, const null_buffers&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Start an asynchronous send. The data being sent must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_send(implementation_type&, const ConstBufferSequence&,
-      socket_base::message_flags, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Start an asynchronous wait until data can be sent without blocking.
-  template <typename Handler>
-  void async_send(implementation_type&, const null_buffers&,
-      socket_base::message_flags, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Receive some data from the peer. Returns the number of bytes received.
-  template <typename MutableBufferSequence>
-  std::size_t receive(implementation_type&, const MutableBufferSequence&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Wait until data can be received without blocking.
-  std::size_t receive(implementation_type&, const null_buffers&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received
-  // must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive(implementation_type&, const MutableBufferSequence&,
-      socket_base::message_flags, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive(implementation_type&, const null_buffers&,
-      socket_base::message_flags, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Receive some data with associated flags. Returns the number of bytes
-  // received.
-  template <typename MutableBufferSequence>
-  std::size_t receive_with_flags(implementation_type&,
-      const MutableBufferSequence&, socket_base::message_flags,
-      socket_base::message_flags&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Wait until data can be received without blocking.
-  std::size_t receive_with_flags(implementation_type&,
-      const null_buffers&, socket_base::message_flags,
-      socket_base::message_flags&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received
-  // must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive_with_flags(implementation_type&,
-      const MutableBufferSequence&, socket_base::message_flags,
-      socket_base::message_flags&, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive_with_flags(implementation_type&,
-      const null_buffers&, socket_base::message_flags,
-      socket_base::message_flags&, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Send a datagram to the specified endpoint. Returns the number of bytes
-  // sent.
-  template <typename ConstBufferSequence>
-  std::size_t send_to(implementation_type&, const ConstBufferSequence&,
-      const endpoint_type&, socket_base::message_flags,
-      asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Wait until data can be sent without blocking.
-  std::size_t send_to(implementation_type&, const null_buffers&,
-      const endpoint_type&, socket_base::message_flags,
-      asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Start an asynchronous send. The data being sent must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_send_to(implementation_type&, const ConstBufferSequence&,
-      const endpoint_type&, socket_base::message_flags,
-      Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Start an asynchronous wait until data can be sent without blocking.
-  template <typename Handler>
-  void async_send_to(implementation_type&, const null_buffers&,
-      const endpoint_type&, socket_base::message_flags, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Receive a datagram with the endpoint of the sender. Returns the number of
-  // bytes received.
-  template <typename MutableBufferSequence>
-  std::size_t receive_from(implementation_type&, const MutableBufferSequence&,
-      endpoint_type&, socket_base::message_flags,
-      asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Wait until data can be received without blocking.
-  std::size_t receive_from(implementation_type&, const null_buffers&,
-      endpoint_type&, socket_base::message_flags,
-      asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received and
-  // the sender_endpoint object must both be valid for the lifetime of the
-  // asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive_from(implementation_type&,
-      const MutableBufferSequence&, endpoint_type&,
-      socket_base::message_flags, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive_from(implementation_type&,
-      const null_buffers&, endpoint_type&,
-      socket_base::message_flags, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.post(detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Accept a new connection.
-  template <typename Socket>
-  asio::error_code accept(implementation_type&,
-      Socket&, endpoint_type*, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Start an asynchronous accept. The peer and peer_endpoint objects
-  // must be valid until the accept's handler is invoked.
-  template <typename Socket, typename Handler>
-  void async_accept(implementation_type&, Socket&,
-      endpoint_type*, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    io_context_.post(detail::bind_handler(handler, ec));
-  }
-
-  // Connect the socket to the specified endpoint.
-  asio::error_code connect(implementation_type&,
-      const endpoint_type&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Start an asynchronous connect.
-  template <typename Handler>
-  void async_connect(implementation_type&,
-      const endpoint_type&, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    io_context_.post(detail::bind_handler(handler, ec));
-  }
-
-private:
-  asio::io_context& io_context_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_NULL_SOCKET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_static_mutex.hpp b/tools/sdk/include/asio/asio/detail/null_static_mutex.hpp
deleted file mode 100644
index 36ec04f7e3d..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_static_mutex.hpp
+++ /dev/null
@@ -1,60 +0,0 @@
-//
-// detail/null_static_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_STATIC_MUTEX_HPP
-#define ASIO_DETAIL_NULL_STATIC_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-
-#include "asio/detail/scoped_lock.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-struct null_static_mutex
-{
-  typedef asio::detail::scoped_lock<null_static_mutex> scoped_lock;
-
-  // Initialise the mutex.
-  void init()
-  {
-  }
-
-  // Lock the mutex.
-  void lock()
-  {
-  }
-
-  // Unlock the mutex.
-  void unlock()
-  {
-  }
-
-  int unused_;
-};
-
-#define ASIO_NULL_STATIC_MUTEX_INIT { 0 }
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_HAS_THREADS)
-
-#endif // ASIO_DETAIL_NULL_STATIC_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_thread.hpp b/tools/sdk/include/asio/asio/detail/null_thread.hpp
deleted file mode 100644
index 7291ba3841d..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_thread.hpp
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// detail/null_thread.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_THREAD_HPP
-#define ASIO_DETAIL_NULL_THREAD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class null_thread
-  : private noncopyable
-{
-public:
-  // Constructor.
-  template <typename Function>
-  null_thread(Function, unsigned int = 0)
-  {
-    asio::detail::throw_error(
-        asio::error::operation_not_supported, "thread");
-  }
-
-  // Destructor.
-  ~null_thread()
-  {
-  }
-
-  // Wait for the thread to exit.
-  void join()
-  {
-  }
-
-  // Get number of CPUs.
-  static std::size_t hardware_concurrency()
-  {
-    return 1;
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_HAS_THREADS)
-
-#endif // ASIO_DETAIL_NULL_THREAD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/null_tss_ptr.hpp b/tools/sdk/include/asio/asio/detail/null_tss_ptr.hpp
deleted file mode 100644
index 323967d6cf4..00000000000
--- a/tools/sdk/include/asio/asio/detail/null_tss_ptr.hpp
+++ /dev/null
@@ -1,68 +0,0 @@
-//
-// detail/null_tss_ptr.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_NULL_TSS_PTR_HPP
-#define ASIO_DETAIL_NULL_TSS_PTR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-class null_tss_ptr
-  : private noncopyable
-{
-public:
-  // Constructor.
-  null_tss_ptr()
-    : value_(0)
-  {
-  }
-
-  // Destructor.
-  ~null_tss_ptr()
-  {
-  }
-
-  // Get the value.
-  operator T*() const
-  {
-    return value_;
-  }
-
-  // Set the value.
-  void operator=(T* value)
-  {
-    value_ = value;
-  }
-
-private:
-  T* value_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_HAS_THREADS)
-
-#endif // ASIO_DETAIL_NULL_TSS_PTR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/object_pool.hpp b/tools/sdk/include/asio/asio/detail/object_pool.hpp
deleted file mode 100644
index e1a3c5482a9..00000000000
--- a/tools/sdk/include/asio/asio/detail/object_pool.hpp
+++ /dev/null
@@ -1,171 +0,0 @@
-//
-// detail/object_pool.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_OBJECT_POOL_HPP
-#define ASIO_DETAIL_OBJECT_POOL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Object>
-class object_pool;
-
-class object_pool_access
-{
-public:
-  template <typename Object>
-  static Object* create()
-  {
-    return new Object;
-  }
-
-  template <typename Object, typename Arg>
-  static Object* create(Arg arg)
-  {
-    return new Object(arg);
-  }
-
-  template <typename Object>
-  static void destroy(Object* o)
-  {
-    delete o;
-  }
-
-  template <typename Object>
-  static Object*& next(Object* o)
-  {
-    return o->next_;
-  }
-
-  template <typename Object>
-  static Object*& prev(Object* o)
-  {
-    return o->prev_;
-  }
-};
-
-template <typename Object>
-class object_pool
-  : private noncopyable
-{
-public:
-  // Constructor.
-  object_pool()
-    : live_list_(0),
-      free_list_(0)
-  {
-  }
-
-  // Destructor destroys all objects.
-  ~object_pool()
-  {
-    destroy_list(live_list_);
-    destroy_list(free_list_);
-  }
-
-  // Get the object at the start of the live list.
-  Object* first()
-  {
-    return live_list_;
-  }
-
-  // Allocate a new object.
-  Object* alloc()
-  {
-    Object* o = free_list_;
-    if (o)
-      free_list_ = object_pool_access::next(free_list_);
-    else
-      o = object_pool_access::create<Object>();
-
-    object_pool_access::next(o) = live_list_;
-    object_pool_access::prev(o) = 0;
-    if (live_list_)
-      object_pool_access::prev(live_list_) = o;
-    live_list_ = o;
-
-    return o;
-  }
-
-  // Allocate a new object with an argument.
-  template <typename Arg>
-  Object* alloc(Arg arg)
-  {
-    Object* o = free_list_;
-    if (o)
-      free_list_ = object_pool_access::next(free_list_);
-    else
-      o = object_pool_access::create<Object>(arg);
-
-    object_pool_access::next(o) = live_list_;
-    object_pool_access::prev(o) = 0;
-    if (live_list_)
-      object_pool_access::prev(live_list_) = o;
-    live_list_ = o;
-
-    return o;
-  }
-
-  // Free an object. Moves it to the free list. No destructors are run.
-  void free(Object* o)
-  {
-    if (live_list_ == o)
-      live_list_ = object_pool_access::next(o);
-
-    if (object_pool_access::prev(o))
-    {
-      object_pool_access::next(object_pool_access::prev(o))
-        = object_pool_access::next(o);
-    }
-
-    if (object_pool_access::next(o))
-    {
-      object_pool_access::prev(object_pool_access::next(o))
-        = object_pool_access::prev(o);
-    }
-
-    object_pool_access::next(o) = free_list_;
-    object_pool_access::prev(o) = 0;
-    free_list_ = o;
-  }
-
-private:
-  // Helper function to destroy all elements in a list.
-  void destroy_list(Object* list)
-  {
-    while (list)
-    {
-      Object* o = list;
-      list = object_pool_access::next(o);
-      object_pool_access::destroy(o);
-    }
-  }
-
-  // The list of live objects.
-  Object* live_list_;
-
-  // The free list.
-  Object* free_list_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_OBJECT_POOL_HPP
diff --git a/tools/sdk/include/asio/asio/detail/old_win_sdk_compat.hpp b/tools/sdk/include/asio/asio/detail/old_win_sdk_compat.hpp
deleted file mode 100644
index bfb109e7f7b..00000000000
--- a/tools/sdk/include/asio/asio/detail/old_win_sdk_compat.hpp
+++ /dev/null
@@ -1,214 +0,0 @@
-//
-// detail/old_win_sdk_compat.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_OLD_WIN_SDK_COMPAT_HPP
-#define ASIO_DETAIL_OLD_WIN_SDK_COMPAT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-// Guess whether we are building against on old Platform SDK.
-#if !defined(IN6ADDR_ANY_INIT)
-#define ASIO_HAS_OLD_WIN_SDK 1
-#endif // !defined(IN6ADDR_ANY_INIT)
-
-#if defined(ASIO_HAS_OLD_WIN_SDK)
-
-// Emulation of types that are missing from old Platform SDKs.
-//
-// N.B. this emulation is also used if building for a Windows 2000 target with
-// a recent (i.e. Vista or later) SDK, as the SDK does not provide IPv6 support
-// in that case.
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-enum
-{
-  sockaddr_storage_maxsize = 128, // Maximum size.
-  sockaddr_storage_alignsize = (sizeof(__int64)), // Desired alignment.
-  sockaddr_storage_pad1size = (sockaddr_storage_alignsize - sizeof(short)),
-  sockaddr_storage_pad2size = (sockaddr_storage_maxsize -
-      (sizeof(short) + sockaddr_storage_pad1size + sockaddr_storage_alignsize))
-};
-
-struct sockaddr_storage_emulation
-{
-  short ss_family;
-  char __ss_pad1[sockaddr_storage_pad1size];
-  __int64 __ss_align;
-  char __ss_pad2[sockaddr_storage_pad2size];
-};
-
-struct in6_addr_emulation
-{
-  union
-  {
-    u_char Byte[16];
-    u_short Word[8];
-  } u;
-};
-
-#if !defined(s6_addr)
-# define _S6_un u
-# define _S6_u8 Byte
-# define s6_addr _S6_un._S6_u8
-#endif // !defined(s6_addr)
-
-struct sockaddr_in6_emulation
-{
-  short sin6_family;
-  u_short sin6_port;
-  u_long sin6_flowinfo;
-  in6_addr_emulation sin6_addr;
-  u_long sin6_scope_id;
-};
-
-struct ipv6_mreq_emulation
-{
-  in6_addr_emulation ipv6mr_multiaddr;
-  unsigned int ipv6mr_interface;
-};
-
-struct addrinfo_emulation
-{
-  int ai_flags;
-  int ai_family;
-  int ai_socktype;
-  int ai_protocol;
-  size_t ai_addrlen;
-  char* ai_canonname;
-  sockaddr* ai_addr;
-  addrinfo_emulation* ai_next;
-};
-
-#if !defined(AI_PASSIVE)
-# define AI_PASSIVE 0x1
-#endif
-
-#if !defined(AI_CANONNAME)
-# define AI_CANONNAME 0x2
-#endif
-
-#if !defined(AI_NUMERICHOST)
-# define AI_NUMERICHOST 0x4
-#endif
-
-#if !defined(EAI_AGAIN)
-# define EAI_AGAIN WSATRY_AGAIN
-#endif
-
-#if !defined(EAI_BADFLAGS)
-# define EAI_BADFLAGS WSAEINVAL
-#endif
-
-#if !defined(EAI_FAIL)
-# define EAI_FAIL WSANO_RECOVERY
-#endif
-
-#if !defined(EAI_FAMILY)
-# define EAI_FAMILY WSAEAFNOSUPPORT
-#endif
-
-#if !defined(EAI_MEMORY)
-# define EAI_MEMORY WSA_NOT_ENOUGH_MEMORY
-#endif
-
-#if !defined(EAI_NODATA)
-# define EAI_NODATA WSANO_DATA
-#endif
-
-#if !defined(EAI_NONAME)
-# define EAI_NONAME WSAHOST_NOT_FOUND
-#endif
-
-#if !defined(EAI_SERVICE)
-# define EAI_SERVICE WSATYPE_NOT_FOUND
-#endif
-
-#if !defined(EAI_SOCKTYPE)
-# define EAI_SOCKTYPE WSAESOCKTNOSUPPORT
-#endif
-
-#if !defined(NI_NOFQDN)
-# define NI_NOFQDN 0x01
-#endif
-
-#if !defined(NI_NUMERICHOST)
-# define NI_NUMERICHOST 0x02
-#endif
-
-#if !defined(NI_NAMEREQD)
-# define NI_NAMEREQD 0x04
-#endif
-
-#if !defined(NI_NUMERICSERV)
-# define NI_NUMERICSERV 0x08
-#endif
-
-#if !defined(NI_DGRAM)
-# define NI_DGRAM 0x10
-#endif
-
-#if !defined(IPPROTO_IPV6)
-# define IPPROTO_IPV6 41
-#endif
-
-#if !defined(IPV6_UNICAST_HOPS)
-# define IPV6_UNICAST_HOPS 4
-#endif
-
-#if !defined(IPV6_MULTICAST_IF)
-# define IPV6_MULTICAST_IF 9
-#endif
-
-#if !defined(IPV6_MULTICAST_HOPS)
-# define IPV6_MULTICAST_HOPS 10
-#endif
-
-#if !defined(IPV6_MULTICAST_LOOP)
-# define IPV6_MULTICAST_LOOP 11
-#endif
-
-#if !defined(IPV6_JOIN_GROUP)
-# define IPV6_JOIN_GROUP 12
-#endif
-
-#if !defined(IPV6_LEAVE_GROUP)
-# define IPV6_LEAVE_GROUP 13
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_OLD_WIN_SDK)
-
-// Even newer Platform SDKs that support IPv6 may not define IPV6_V6ONLY.
-#if !defined(IPV6_V6ONLY)
-# define IPV6_V6ONLY 27
-#endif
-
-// Some SDKs (e.g. Windows CE) don't define IPPROTO_ICMPV6.
-#if !defined(IPPROTO_ICMPV6)
-# define IPPROTO_ICMPV6 58
-#endif
-
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-#endif // ASIO_DETAIL_OLD_WIN_SDK_COMPAT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/op_queue.hpp b/tools/sdk/include/asio/asio/detail/op_queue.hpp
deleted file mode 100644
index 6219f797d7f..00000000000
--- a/tools/sdk/include/asio/asio/detail/op_queue.hpp
+++ /dev/null
@@ -1,162 +0,0 @@
-//
-// detail/op_queue.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_OP_QUEUE_HPP
-#define ASIO_DETAIL_OP_QUEUE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Operation>
-class op_queue;
-
-class op_queue_access
-{
-public:
-  template <typename Operation>
-  static Operation* next(Operation* o)
-  {
-    return static_cast<Operation*>(o->next_);
-  }
-
-  template <typename Operation1, typename Operation2>
-  static void next(Operation1*& o1, Operation2* o2)
-  {
-    o1->next_ = o2;
-  }
-
-  template <typename Operation>
-  static void destroy(Operation* o)
-  {
-    o->destroy();
-  }
-
-  template <typename Operation>
-  static Operation*& front(op_queue<Operation>& q)
-  {
-    return q.front_;
-  }
-
-  template <typename Operation>
-  static Operation*& back(op_queue<Operation>& q)
-  {
-    return q.back_;
-  }
-};
-
-template <typename Operation>
-class op_queue
-  : private noncopyable
-{
-public:
-  // Constructor.
-  op_queue()
-    : front_(0),
-      back_(0)
-  {
-  }
-
-  // Destructor destroys all operations.
-  ~op_queue()
-  {
-    while (Operation* op = front_)
-    {
-      pop();
-      op_queue_access::destroy(op);
-    }
-  }
-
-  // Get the operation at the front of the queue.
-  Operation* front()
-  {
-    return front_;
-  }
-
-  // Pop an operation from the front of the queue.
-  void pop()
-  {
-    if (front_)
-    {
-      Operation* tmp = front_;
-      front_ = op_queue_access::next(front_);
-      if (front_ == 0)
-        back_ = 0;
-      op_queue_access::next(tmp, static_cast<Operation*>(0));
-    }
-  }
-
-  // Push an operation on to the back of the queue.
-  void push(Operation* h)
-  {
-    op_queue_access::next(h, static_cast<Operation*>(0));
-    if (back_)
-    {
-      op_queue_access::next(back_, h);
-      back_ = h;
-    }
-    else
-    {
-      front_ = back_ = h;
-    }
-  }
-
-  // Push all operations from another queue on to the back of the queue. The
-  // source queue may contain operations of a derived type.
-  template <typename OtherOperation>
-  void push(op_queue<OtherOperation>& q)
-  {
-    if (Operation* other_front = op_queue_access::front(q))
-    {
-      if (back_)
-        op_queue_access::next(back_, other_front);
-      else
-        front_ = other_front;
-      back_ = op_queue_access::back(q);
-      op_queue_access::front(q) = 0;
-      op_queue_access::back(q) = 0;
-    }
-  }
-
-  // Whether the queue is empty.
-  bool empty() const
-  {
-    return front_ == 0;
-  }
-
-  // Test whether an operation is already enqueued.
-  bool is_enqueued(Operation* o) const
-  {
-    return op_queue_access::next(o) != 0 || back_ == o;
-  }
-
-private:
-  friend class op_queue_access;
-
-  // The front of the queue.
-  Operation* front_;
-
-  // The back of the queue.
-  Operation* back_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_OP_QUEUE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/operation.hpp b/tools/sdk/include/asio/asio/detail/operation.hpp
deleted file mode 100644
index 811e54d4aa7..00000000000
--- a/tools/sdk/include/asio/asio/detail/operation.hpp
+++ /dev/null
@@ -1,38 +0,0 @@
-//
-// detail/operation.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_OPERATION_HPP
-#define ASIO_DETAIL_OPERATION_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-# include "asio/detail/win_iocp_operation.hpp"
-#else
-# include "asio/detail/scheduler_operation.hpp"
-#endif
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_HAS_IOCP)
-typedef win_iocp_operation operation;
-#else
-typedef scheduler_operation operation;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_OPERATION_HPP
diff --git a/tools/sdk/include/asio/asio/detail/pipe_select_interrupter.hpp b/tools/sdk/include/asio/asio/detail/pipe_select_interrupter.hpp
deleted file mode 100644
index 55d7db4916e..00000000000
--- a/tools/sdk/include/asio/asio/detail/pipe_select_interrupter.hpp
+++ /dev/null
@@ -1,89 +0,0 @@
-//
-// detail/pipe_select_interrupter.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_PIPE_SELECT_INTERRUPTER_HPP
-#define ASIO_DETAIL_PIPE_SELECT_INTERRUPTER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS)
-#if !defined(ASIO_WINDOWS_RUNTIME)
-#if !defined(__CYGWIN__)
-#if !defined(__SYMBIAN32__)
-#if !defined(ASIO_HAS_EVENTFD)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class pipe_select_interrupter
-{
-public:
-  // Constructor.
-  ASIO_DECL pipe_select_interrupter();
-
-  // Destructor.
-  ASIO_DECL ~pipe_select_interrupter();
-
-  // Recreate the interrupter's descriptors. Used after a fork.
-  ASIO_DECL void recreate();
-
-  // Interrupt the select call.
-  ASIO_DECL void interrupt();
-
-  // Reset the select interrupt. Returns true if the call was interrupted.
-  ASIO_DECL bool reset();
-
-  // Get the read descriptor to be passed to select.
-  int read_descriptor() const
-  {
-    return read_descriptor_;
-  }
-
-private:
-  // Open the descriptors. Throws on error.
-  ASIO_DECL void open_descriptors();
-
-  // Close the descriptors.
-  ASIO_DECL void close_descriptors();
-
-  // The read end of a connection used to interrupt the select call. This file
-  // descriptor is passed to select such that when it is time to stop, a single
-  // byte will be written on the other end of the connection and this
-  // descriptor will become readable.
-  int read_descriptor_;
-
-  // The write end of a connection used to interrupt the select call. A single
-  // byte may be written to this to wake up the select which is waiting for the
-  // other end to become readable.
-  int write_descriptor_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/pipe_select_interrupter.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // !defined(ASIO_HAS_EVENTFD)
-#endif // !defined(__SYMBIAN32__)
-#endif // !defined(__CYGWIN__)
-#endif // !defined(ASIO_WINDOWS_RUNTIME)
-#endif // !defined(ASIO_WINDOWS)
-
-#endif // ASIO_DETAIL_PIPE_SELECT_INTERRUPTER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/pop_options.hpp b/tools/sdk/include/asio/asio/detail/pop_options.hpp
deleted file mode 100644
index 1045612bf40..00000000000
--- a/tools/sdk/include/asio/asio/detail/pop_options.hpp
+++ /dev/null
@@ -1,135 +0,0 @@
-//
-// detail/pop_options.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-// No header guard
-
-#if defined(__COMO__)
-
-// Comeau C++
-
-#elif defined(__DMC__)
-
-// Digital Mars C++
-
-#elif defined(__INTEL_COMPILER) || defined(__ICL) \
-  || defined(__ICC) || defined(__ECC)
-
-// Intel C++
-
-# if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-#  pragma GCC visibility pop
-# endif // (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-
-#elif defined(__clang__)
-
-// Clang
-
-# if defined(__OBJC__)
-#  if !defined(__APPLE_CC__) || (__APPLE_CC__ <= 1)
-#   if defined(ASIO_OBJC_WORKAROUND)
-#    undef Protocol
-#    undef id
-#    undef ASIO_OBJC_WORKAROUND
-#   endif
-#  endif
-# endif
-
-# if !defined(_WIN32) && !defined(__WIN32__) && !defined(WIN32)
-#  pragma GCC visibility pop
-# endif // !defined(_WIN32) && !defined(__WIN32__) && !defined(WIN32)
-
-#elif defined(__GNUC__)
-
-// GNU C++
-
-# if defined(__MINGW32__) || defined(__CYGWIN__)
-#  pragma pack (pop)
-# endif
-
-# if defined(__OBJC__)
-#  if !defined(__APPLE_CC__) || (__APPLE_CC__ <= 1)
-#   if defined(ASIO_OBJC_WORKAROUND)
-#    undef Protocol
-#    undef id
-#    undef ASIO_OBJC_WORKAROUND
-#   endif
-#  endif
-# endif
-
-# if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-#  pragma GCC visibility pop
-# endif // (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-
-# if (__GNUC__ >= 7)
-#  pragma GCC diagnostic pop
-# endif // (__GNUC__ >= 7)
-
-#elif defined(__KCC)
-
-// Kai C++
-
-#elif defined(__sgi)
-
-// SGI MIPSpro C++
-
-#elif defined(__DECCXX)
-
-// Compaq Tru64 Unix cxx
-
-#elif defined(__ghs)
-
-// Greenhills C++
-
-#elif defined(__BORLANDC__)
-
-// Borland C++
-
-# pragma option pop
-# pragma nopushoptwarn
-# pragma nopackwarning
-
-#elif defined(__MWERKS__)
-
-// Metrowerks CodeWarrior
-
-#elif defined(__SUNPRO_CC)
-
-// Sun Workshop Compiler C++
-
-#elif defined(__HP_aCC)
-
-// HP aCC
-
-#elif defined(__MRC__) || defined(__SC__)
-
-// MPW MrCpp or SCpp
-
-#elif defined(__IBMCPP__)
-
-// IBM Visual Age
-
-#elif defined(_MSC_VER)
-
-// Microsoft Visual C++
-//
-// Must remain the last #elif since some other vendors (Metrowerks, for example)
-// also #define _MSC_VER
-
-# pragma warning (pop)
-# pragma pack (pop)
-
-# if defined(__cplusplus_cli) || defined(__cplusplus_winrt)
-#  if defined(ASIO_CLR_WORKAROUND)
-#   undef generic
-#   undef ASIO_CLR_WORKAROUND
-#  endif
-# endif
-
-#endif
diff --git a/tools/sdk/include/asio/asio/detail/posix_event.hpp b/tools/sdk/include/asio/asio/detail/posix_event.hpp
deleted file mode 100644
index 121065efbbc..00000000000
--- a/tools/sdk/include/asio/asio/detail/posix_event.hpp
+++ /dev/null
@@ -1,162 +0,0 @@
-//
-// detail/posix_event.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_POSIX_EVENT_HPP
-#define ASIO_DETAIL_POSIX_EVENT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_PTHREADS)
-
-#include <pthread.h>
-#include "asio/detail/assert.hpp"
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class posix_event
-  : private noncopyable
-{
-public:
-  // Constructor.
-  ASIO_DECL posix_event();
-
-  // Destructor.
-  ~posix_event()
-  {
-    ::pthread_cond_destroy(&cond_);
-  }
-
-  // Signal the event. (Retained for backward compatibility.)
-  template <typename Lock>
-  void signal(Lock& lock)
-  {
-    this->signal_all(lock);
-  }
-
-  // Signal all waiters.
-  template <typename Lock>
-  void signal_all(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    (void)lock;
-    state_ |= 1;
-    ::pthread_cond_broadcast(&cond_); // Ignore EINVAL.
-  }
-
-  // Unlock the mutex and signal one waiter.
-  template <typename Lock>
-  void unlock_and_signal_one(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    state_ |= 1;
-    bool have_waiters = (state_ > 1);
-    lock.unlock();
-    if (have_waiters)
-      ::pthread_cond_signal(&cond_); // Ignore EINVAL.
-  }
-
-  // If there's a waiter, unlock the mutex and signal it.
-  template <typename Lock>
-  bool maybe_unlock_and_signal_one(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    state_ |= 1;
-    if (state_ > 1)
-    {
-      lock.unlock();
-      ::pthread_cond_signal(&cond_); // Ignore EINVAL.
-      return true;
-    }
-    return false;
-  }
-
-  // Reset the event.
-  template <typename Lock>
-  void clear(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    (void)lock;
-    state_ &= ~std::size_t(1);
-  }
-
-  // Wait for the event to become signalled.
-  template <typename Lock>
-  void wait(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    while ((state_ & 1) == 0)
-    {
-      state_ += 2;
-      ::pthread_cond_wait(&cond_, &lock.mutex().mutex_); // Ignore EINVAL.
-      state_ -= 2;
-    }
-  }
-
-  // Timed wait for the event to become signalled.
-  template <typename Lock>
-  bool wait_for_usec(Lock& lock, long usec)
-  {
-    ASIO_ASSERT(lock.locked());
-    if ((state_ & 1) == 0)
-    {
-      state_ += 2;
-      timespec ts;
-#if (defined(__MACH__) && defined(__APPLE__)) \
-      || (defined(__ANDROID__) && (__ANDROID_API__ < 21) \
-          && defined(HAVE_PTHREAD_COND_TIMEDWAIT_RELATIVE))
-      ts.tv_sec = usec / 1000000;
-      ts.tv_nsec = (usec % 1000000) * 1000;
-      ::pthread_cond_timedwait_relative_np(
-          &cond_, &lock.mutex().mutex_, &ts); // Ignore EINVAL.
-#else // (defined(__MACH__) && defined(__APPLE__))
-      // || (defined(__ANDROID__) && (__ANDROID_API__ < 21)
-      //     && defined(HAVE_PTHREAD_COND_TIMEDWAIT_RELATIVE))
-      if (::clock_gettime(CLOCK_MONOTONIC, &ts) == 0)
-      {
-        ts.tv_sec += usec / 1000000;
-        ts.tv_nsec = (usec % 1000000) * 1000;
-        ts.tv_sec += ts.tv_nsec / 1000000000;
-        ts.tv_nsec = ts.tv_nsec % 1000000000;
-        ::pthread_cond_timedwait(&cond_,
-            &lock.mutex().mutex_, &ts); // Ignore EINVAL.
-      }
-#endif // (defined(__MACH__) && defined(__APPLE__))
-       // || (defined(__ANDROID__) && (__ANDROID_API__ < 21)
-       //     && defined(HAVE_PTHREAD_COND_TIMEDWAIT_RELATIVE))
-      state_ -= 2;
-    }
-    return (state_ & 1) != 0;
-  }
-
-private:
-  ::pthread_cond_t cond_;
-  std::size_t state_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/posix_event.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_PTHREADS)
-
-#endif // ASIO_DETAIL_POSIX_EVENT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/posix_fd_set_adapter.hpp b/tools/sdk/include/asio/asio/detail/posix_fd_set_adapter.hpp
deleted file mode 100644
index 95042d66314..00000000000
--- a/tools/sdk/include/asio/asio/detail/posix_fd_set_adapter.hpp
+++ /dev/null
@@ -1,118 +0,0 @@
-//
-// detail/posix_fd_set_adapter.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_POSIX_FD_SET_ADAPTER_HPP
-#define ASIO_DETAIL_POSIX_FD_SET_ADAPTER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS) \
-  && !defined(__CYGWIN__) \
-  && !defined(ASIO_WINDOWS_RUNTIME)
-
-#include <cstring>
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/reactor_op_queue.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Adapts the FD_SET type to meet the Descriptor_Set concept's requirements.
-class posix_fd_set_adapter : noncopyable
-{
-public:
-  posix_fd_set_adapter()
-    : max_descriptor_(invalid_socket)
-  {
-    using namespace std; // Needed for memset on Solaris.
-    FD_ZERO(&fd_set_);
-  }
-
-  void reset()
-  {
-    using namespace std; // Needed for memset on Solaris.
-    FD_ZERO(&fd_set_);
-  }
-
-  bool set(socket_type descriptor)
-  {
-    if (descriptor < (socket_type)FD_SETSIZE)
-    {
-      if (max_descriptor_ == invalid_socket || descriptor > max_descriptor_)
-        max_descriptor_ = descriptor;
-      FD_SET(descriptor, &fd_set_);
-      return true;
-    }
-    return false;
-  }
-
-  void set(reactor_op_queue<socket_type>& operations, op_queue<operation>& ops)
-  {
-    reactor_op_queue<socket_type>::iterator i = operations.begin();
-    while (i != operations.end())
-    {
-      reactor_op_queue<socket_type>::iterator op_iter = i++;
-      if (!set(op_iter->first))
-      {
-        asio::error_code ec(error::fd_set_failure);
-        operations.cancel_operations(op_iter, ops, ec);
-      }
-    }
-  }
-
-  bool is_set(socket_type descriptor) const
-  {
-    return FD_ISSET(descriptor, &fd_set_) != 0;
-  }
-
-  operator fd_set*()
-  {
-    return &fd_set_;
-  }
-
-  socket_type max_descriptor() const
-  {
-    return max_descriptor_;
-  }
-
-  void perform(reactor_op_queue<socket_type>& operations,
-      op_queue<operation>& ops) const
-  {
-    reactor_op_queue<socket_type>::iterator i = operations.begin();
-    while (i != operations.end())
-    {
-      reactor_op_queue<socket_type>::iterator op_iter = i++;
-      if (is_set(op_iter->first))
-        operations.perform_operations(op_iter, ops);
-    }
-  }
-
-private:
-  mutable fd_set fd_set_;
-  socket_type max_descriptor_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_WINDOWS)
-       // && !defined(__CYGWIN__)
-       // && !defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_POSIX_FD_SET_ADAPTER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/posix_global.hpp b/tools/sdk/include/asio/asio/detail/posix_global.hpp
deleted file mode 100644
index 7ee0a715450..00000000000
--- a/tools/sdk/include/asio/asio/detail/posix_global.hpp
+++ /dev/null
@@ -1,80 +0,0 @@
-//
-// detail/posix_global.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_POSIX_GLOBAL_HPP
-#define ASIO_DETAIL_POSIX_GLOBAL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_PTHREADS)
-
-#include <exception>
-#include <pthread.h>
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-struct posix_global_impl
-{
-  // Helper function to perform initialisation.
-  static void do_init()
-  {
-    instance_.static_ptr_ = instance_.ptr_ = new T;
-  }
-
-  // Destructor automatically cleans up the global.
-  ~posix_global_impl()
-  {
-    delete static_ptr_;
-  }
-
-  static ::pthread_once_t init_once_;
-  static T* static_ptr_;
-  static posix_global_impl instance_;
-  T* ptr_;
-};
-
-template <typename T>
-::pthread_once_t posix_global_impl<T>::init_once_ = PTHREAD_ONCE_INIT;
-
-template <typename T>
-T* posix_global_impl<T>::static_ptr_ = 0;
-
-template <typename T>
-posix_global_impl<T> posix_global_impl<T>::instance_;
-
-template <typename T>
-T& posix_global()
-{
-  int result = ::pthread_once(
-      &posix_global_impl<T>::init_once_,
-      &posix_global_impl<T>::do_init);
-
-  if (result != 0)
-    std::terminate();
-
-  return *posix_global_impl<T>::instance_.ptr_;
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_PTHREADS)
-
-#endif // ASIO_DETAIL_POSIX_GLOBAL_HPP
diff --git a/tools/sdk/include/asio/asio/detail/posix_mutex.hpp b/tools/sdk/include/asio/asio/detail/posix_mutex.hpp
deleted file mode 100644
index c0d9fc9b777..00000000000
--- a/tools/sdk/include/asio/asio/detail/posix_mutex.hpp
+++ /dev/null
@@ -1,76 +0,0 @@
-//
-// detail/posix_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_POSIX_MUTEX_HPP
-#define ASIO_DETAIL_POSIX_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_PTHREADS)
-
-#include <pthread.h>
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/scoped_lock.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class posix_event;
-
-class posix_mutex
-  : private noncopyable
-{
-public:
-  typedef asio::detail::scoped_lock<posix_mutex> scoped_lock;
-
-  // Constructor.
-  ASIO_DECL posix_mutex();
-
-  // Destructor.
-  ~posix_mutex()
-  {
-    ::pthread_mutex_destroy(&mutex_); // Ignore EBUSY.
-  }
-
-  // Lock the mutex.
-  void lock()
-  {
-    (void)::pthread_mutex_lock(&mutex_); // Ignore EINVAL.
-  }
-
-  // Unlock the mutex.
-  void unlock()
-  {
-    (void)::pthread_mutex_unlock(&mutex_); // Ignore EINVAL.
-  }
-
-private:
-  friend class posix_event;
-  ::pthread_mutex_t mutex_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/posix_mutex.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_PTHREADS)
-
-#endif // ASIO_DETAIL_POSIX_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/posix_signal_blocker.hpp b/tools/sdk/include/asio/asio/detail/posix_signal_blocker.hpp
deleted file mode 100644
index fab5eb1296c..00000000000
--- a/tools/sdk/include/asio/asio/detail/posix_signal_blocker.hpp
+++ /dev/null
@@ -1,85 +0,0 @@
-//
-// detail/posix_signal_blocker.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_POSIX_SIGNAL_BLOCKER_HPP
-#define ASIO_DETAIL_POSIX_SIGNAL_BLOCKER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_PTHREADS)
-
-#include <csignal>
-#include <pthread.h>
-#include <signal.h>
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class posix_signal_blocker
-  : private noncopyable
-{
-public:
-  // Constructor blocks all signals for the calling thread.
-  posix_signal_blocker()
-    : blocked_(false)
-  {
-    sigset_t new_mask;
-    sigfillset(&new_mask);
-    blocked_ = (pthread_sigmask(SIG_BLOCK, &new_mask, &old_mask_) == 0);
-  }
-
-  // Destructor restores the previous signal mask.
-  ~posix_signal_blocker()
-  {
-    if (blocked_)
-      pthread_sigmask(SIG_SETMASK, &old_mask_, 0);
-  }
-
-  // Block all signals for the calling thread.
-  void block()
-  {
-    if (!blocked_)
-    {
-      sigset_t new_mask;
-      sigfillset(&new_mask);
-      blocked_ = (pthread_sigmask(SIG_BLOCK, &new_mask, &old_mask_) == 0);
-    }
-  }
-
-  // Restore the previous signal mask.
-  void unblock()
-  {
-    if (blocked_)
-      blocked_ = (pthread_sigmask(SIG_SETMASK, &old_mask_, 0) != 0);
-  }
-
-private:
-  // Have signals been blocked.
-  bool blocked_;
-
-  // The previous signal mask.
-  sigset_t old_mask_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_PTHREADS)
-
-#endif // ASIO_DETAIL_POSIX_SIGNAL_BLOCKER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/posix_static_mutex.hpp b/tools/sdk/include/asio/asio/detail/posix_static_mutex.hpp
deleted file mode 100644
index 59b86c1885c..00000000000
--- a/tools/sdk/include/asio/asio/detail/posix_static_mutex.hpp
+++ /dev/null
@@ -1,64 +0,0 @@
-//
-// detail/posix_static_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_POSIX_STATIC_MUTEX_HPP
-#define ASIO_DETAIL_POSIX_STATIC_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_PTHREADS)
-
-#include <pthread.h>
-#include "asio/detail/scoped_lock.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-struct posix_static_mutex
-{
-  typedef asio::detail::scoped_lock<posix_static_mutex> scoped_lock;
-
-  // Initialise the mutex.
-  void init()
-  {
-    // Nothing to do.
-  }
-
-  // Lock the mutex.
-  void lock()
-  {
-    (void)::pthread_mutex_lock(&mutex_); // Ignore EINVAL.
-  }
-
-  // Unlock the mutex.
-  void unlock()
-  {
-    (void)::pthread_mutex_unlock(&mutex_); // Ignore EINVAL.
-  }
-
-  ::pthread_mutex_t mutex_;
-};
-
-#define ASIO_POSIX_STATIC_MUTEX_INIT { PTHREAD_MUTEX_INITIALIZER }
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_PTHREADS)
-
-#endif // ASIO_DETAIL_POSIX_STATIC_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/posix_thread.hpp b/tools/sdk/include/asio/asio/detail/posix_thread.hpp
deleted file mode 100644
index 1817af28d40..00000000000
--- a/tools/sdk/include/asio/asio/detail/posix_thread.hpp
+++ /dev/null
@@ -1,109 +0,0 @@
-//
-// detail/posix_thread.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_POSIX_THREAD_HPP
-#define ASIO_DETAIL_POSIX_THREAD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_PTHREADS)
-
-#include <cstddef>
-#include <pthread.h>
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-extern "C"
-{
-  ASIO_DECL void* asio_detail_posix_thread_function(void* arg);
-}
-
-class posix_thread
-  : private noncopyable
-{
-public:
-  // Constructor.
-  template <typename Function>
-  posix_thread(Function f, unsigned int = 0)
-    : joined_(false)
-  {
-    start_thread(new func<Function>(f));
-  }
-
-  // Destructor.
-  ASIO_DECL ~posix_thread();
-
-  // Wait for the thread to exit.
-  ASIO_DECL void join();
-
-  // Get number of CPUs.
-  ASIO_DECL static std::size_t hardware_concurrency();
-
-private:
-  friend void* asio_detail_posix_thread_function(void* arg);
-
-  class func_base
-  {
-  public:
-    virtual ~func_base() {}
-    virtual void run() = 0;
-  };
-
-  struct auto_func_base_ptr
-  {
-    func_base* ptr;
-    ~auto_func_base_ptr() { delete ptr; }
-  };
-
-  template <typename Function>
-  class func
-    : public func_base
-  {
-  public:
-    func(Function f)
-      : f_(f)
-    {
-    }
-
-    virtual void run()
-    {
-      f_();
-    }
-
-  private:
-    Function f_;
-  };
-
-  ASIO_DECL void start_thread(func_base* arg);
-
-  ::pthread_t thread_;
-  bool joined_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/posix_thread.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_PTHREADS)
-
-#endif // ASIO_DETAIL_POSIX_THREAD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/posix_tss_ptr.hpp b/tools/sdk/include/asio/asio/detail/posix_tss_ptr.hpp
deleted file mode 100644
index a3096b43e6c..00000000000
--- a/tools/sdk/include/asio/asio/detail/posix_tss_ptr.hpp
+++ /dev/null
@@ -1,79 +0,0 @@
-//
-// detail/posix_tss_ptr.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_POSIX_TSS_PTR_HPP
-#define ASIO_DETAIL_POSIX_TSS_PTR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_PTHREADS)
-
-#include <pthread.h>
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Helper function to create thread-specific storage.
-ASIO_DECL void posix_tss_ptr_create(pthread_key_t& key);
-
-template <typename T>
-class posix_tss_ptr
-  : private noncopyable
-{
-public:
-  // Constructor.
-  posix_tss_ptr()
-  {
-    posix_tss_ptr_create(tss_key_);
-  }
-
-  // Destructor.
-  ~posix_tss_ptr()
-  {
-    ::pthread_key_delete(tss_key_);
-  }
-
-  // Get the value.
-  operator T*() const
-  {
-    return static_cast<T*>(::pthread_getspecific(tss_key_));
-  }
-
-  // Set the value.
-  void operator=(T* value)
-  {
-    ::pthread_setspecific(tss_key_, value);
-  }
-
-private:
-  // Thread-specific storage to allow unlocked access to determine whether a
-  // thread is a member of the pool.
-  pthread_key_t tss_key_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/posix_tss_ptr.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_PTHREADS)
-
-#endif // ASIO_DETAIL_POSIX_TSS_PTR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/push_options.hpp b/tools/sdk/include/asio/asio/detail/push_options.hpp
deleted file mode 100644
index 0a3e9798049..00000000000
--- a/tools/sdk/include/asio/asio/detail/push_options.hpp
+++ /dev/null
@@ -1,175 +0,0 @@
-//
-// detail/push_options.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-// No header guard
-
-#if defined(__COMO__)
-
-// Comeau C++
-
-#elif defined(__DMC__)
-
-// Digital Mars C++
-
-#elif defined(__INTEL_COMPILER) || defined(__ICL) \
-  || defined(__ICC) || defined(__ECC)
-
-// Intel C++
-
-# if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-#  pragma GCC visibility push (default)
-# endif // (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-
-#elif defined(__clang__)
-
-// Clang
-
-# if defined(__OBJC__)
-#  if !defined(__APPLE_CC__) || (__APPLE_CC__ <= 1)
-#   if !defined(ASIO_DISABLE_OBJC_WORKAROUND)
-#    if !defined(Protocol) && !defined(id)
-#     define Protocol cpp_Protocol
-#     define id cpp_id
-#     define ASIO_OBJC_WORKAROUND
-#    endif
-#   endif
-#  endif
-# endif
-
-# if !defined(_WIN32) && !defined(__WIN32__) && !defined(WIN32)
-#  pragma GCC visibility push (default)
-# endif // !defined(_WIN32) && !defined(__WIN32__) && !defined(WIN32)
-
-#elif defined(__GNUC__)
-
-// GNU C++
-
-# if defined(__MINGW32__) || defined(__CYGWIN__)
-#  pragma pack (push, 8)
-# endif
-
-# if defined(__OBJC__)
-#  if !defined(__APPLE_CC__) || (__APPLE_CC__ <= 1)
-#   if !defined(ASIO_DISABLE_OBJC_WORKAROUND)
-#    if !defined(Protocol) && !defined(id)
-#     define Protocol cpp_Protocol
-#     define id cpp_id
-#     define ASIO_OBJC_WORKAROUND
-#    endif
-#   endif
-#  endif
-# endif
-
-# if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-#  pragma GCC visibility push (default)
-# endif // (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-
-# if (__GNUC__ >= 7)
-#  pragma GCC diagnostic push
-#  pragma GCC diagnostic ignored "-Wimplicit-fallthrough"
-# endif // (__GNUC__ >= 7)
-
-#elif defined(__KCC)
-
-// Kai C++
-
-#elif defined(__sgi)
-
-// SGI MIPSpro C++
-
-#elif defined(__DECCXX)
-
-// Compaq Tru64 Unix cxx
-
-#elif defined(__ghs)
-
-// Greenhills C++
-
-#elif defined(__BORLANDC__)
-
-// Borland C++
-
-# pragma option push -a8 -b -Ve- -Vx- -w-inl -vi-
-# pragma nopushoptwarn
-# pragma nopackwarning
-# if !defined(__MT__)
-#  error Multithreaded RTL must be selected.
-# endif // !defined(__MT__)
-
-#elif defined(__MWERKS__)
-
-// Metrowerks CodeWarrior
-
-#elif defined(__SUNPRO_CC)
-
-// Sun Workshop Compiler C++
-
-#elif defined(__HP_aCC)
-
-// HP aCC
-
-#elif defined(__MRC__) || defined(__SC__)
-
-// MPW MrCpp or SCpp
-
-#elif defined(__IBMCPP__)
-
-// IBM Visual Age
-
-#elif defined(_MSC_VER)
-
-// Microsoft Visual C++
-//
-// Must remain the last #elif since some other vendors (Metrowerks, for example)
-// also #define _MSC_VER
-
-# pragma warning (disable:4103)
-# pragma warning (push)
-# pragma warning (disable:4127)
-# pragma warning (disable:4180)
-# pragma warning (disable:4244)
-# pragma warning (disable:4355)
-# pragma warning (disable:4510)
-# pragma warning (disable:4512)
-# pragma warning (disable:4610)
-# pragma warning (disable:4675)
-# if (_MSC_VER < 1600)
-// Visual Studio 2008 generates spurious warnings about unused parameters.
-#  pragma warning (disable:4100)
-# endif // (_MSC_VER < 1600)
-# if defined(_M_IX86) && defined(_Wp64)
-// The /Wp64 option is broken. If you want to check 64 bit portability, use a
-// 64 bit compiler!
-#  pragma warning (disable:4311)
-#  pragma warning (disable:4312)
-# endif // defined(_M_IX86) && defined(_Wp64)
-# pragma pack (push, 8)
-// Note that if the /Og optimisation flag is enabled with MSVC6, the compiler
-// has a tendency to incorrectly optimise away some calls to member template
-// functions, even though those functions contain code that should not be
-// optimised away! Therefore we will always disable this optimisation option
-// for the MSVC6 compiler.
-# if (_MSC_VER < 1300)
-#  pragma optimize ("g", off)
-# endif
-# if !defined(_MT)
-#  error Multithreaded RTL must be selected.
-# endif // !defined(_MT)
-
-# if defined(__cplusplus_cli) || defined(__cplusplus_winrt)
-#  if !defined(ASIO_DISABLE_CLR_WORKAROUND)
-#   if !defined(generic)
-#    define generic cpp_generic
-#    define ASIO_CLR_WORKAROUND
-#   endif
-#  endif
-# endif
-
-#endif
diff --git a/tools/sdk/include/asio/asio/detail/reactive_descriptor_service.hpp b/tools/sdk/include/asio/asio/detail/reactive_descriptor_service.hpp
deleted file mode 100644
index e8668639968..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_descriptor_service.hpp
+++ /dev/null
@@ -1,388 +0,0 @@
-//
-// detail/reactive_descriptor_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_DESCRIPTOR_SERVICE_HPP
-#define ASIO_DETAIL_REACTIVE_DESCRIPTOR_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS) \
-  && !defined(ASIO_WINDOWS_RUNTIME) \
-  && !defined(__CYGWIN__)
-
-#include "asio/buffer.hpp"
-#include "asio/io_context.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/descriptor_ops.hpp"
-#include "asio/detail/descriptor_read_op.hpp"
-#include "asio/detail/descriptor_write_op.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/reactive_null_buffers_op.hpp"
-#include "asio/detail/reactive_wait_op.hpp"
-#include "asio/detail/reactor.hpp"
-#include "asio/posix/descriptor_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class reactive_descriptor_service :
-  public service_base<reactive_descriptor_service>
-{
-public:
-  // The native type of a descriptor.
-  typedef int native_handle_type;
-
-  // The implementation type of the descriptor.
-  class implementation_type
-    : private asio::detail::noncopyable
-  {
-  public:
-    // Default constructor.
-    implementation_type()
-      : descriptor_(-1),
-        state_(0)
-    {
-    }
-
-  private:
-    // Only this service will have access to the internal values.
-    friend class reactive_descriptor_service;
-
-    // The native descriptor representation.
-    int descriptor_;
-
-    // The current state of the descriptor.
-    descriptor_ops::state_type state_;
-
-    // Per-descriptor data used by the reactor.
-    reactor::per_descriptor_data reactor_data_;
-  };
-
-  // Constructor.
-  ASIO_DECL reactive_descriptor_service(
-      asio::io_context& io_context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Construct a new descriptor implementation.
-  ASIO_DECL void construct(implementation_type& impl);
-
-  // Move-construct a new descriptor implementation.
-  ASIO_DECL void move_construct(implementation_type& impl,
-      implementation_type& other_impl);
-
-  // Move-assign from another descriptor implementation.
-  ASIO_DECL void move_assign(implementation_type& impl,
-      reactive_descriptor_service& other_service,
-      implementation_type& other_impl);
-
-  // Destroy a descriptor implementation.
-  ASIO_DECL void destroy(implementation_type& impl);
-
-  // Assign a native descriptor to a descriptor implementation.
-  ASIO_DECL asio::error_code assign(implementation_type& impl,
-      const native_handle_type& native_descriptor,
-      asio::error_code& ec);
-
-  // Determine whether the descriptor is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return impl.descriptor_ != -1;
-  }
-
-  // Destroy a descriptor implementation.
-  ASIO_DECL asio::error_code close(implementation_type& impl,
-      asio::error_code& ec);
-
-  // Get the native descriptor representation.
-  native_handle_type native_handle(const implementation_type& impl) const
-  {
-    return impl.descriptor_;
-  }
-
-  // Release ownership of the native descriptor representation.
-  ASIO_DECL native_handle_type release(implementation_type& impl);
-
-  // Cancel all operations associated with the descriptor.
-  ASIO_DECL asio::error_code cancel(implementation_type& impl,
-      asio::error_code& ec);
-
-  // Perform an IO control command on the descriptor.
-  template <typename IO_Control_Command>
-  asio::error_code io_control(implementation_type& impl,
-      IO_Control_Command& command, asio::error_code& ec)
-  {
-    descriptor_ops::ioctl(impl.descriptor_, impl.state_,
-        command.name(), static_cast<ioctl_arg_type*>(command.data()), ec);
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the descriptor.
-  bool non_blocking(const implementation_type& impl) const
-  {
-    return (impl.state_ & descriptor_ops::user_set_non_blocking) != 0;
-  }
-
-  // Sets the non-blocking mode of the descriptor.
-  asio::error_code non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    descriptor_ops::set_user_non_blocking(
-        impl.descriptor_, impl.state_, mode, ec);
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the native descriptor implementation.
-  bool native_non_blocking(const implementation_type& impl) const
-  {
-    return (impl.state_ & descriptor_ops::internal_non_blocking) != 0;
-  }
-
-  // Sets the non-blocking mode of the native descriptor implementation.
-  asio::error_code native_non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    descriptor_ops::set_internal_non_blocking(
-        impl.descriptor_, impl.state_, mode, ec);
-    return ec;
-  }
-
-  // Wait for the descriptor to become ready to read, ready to write, or to have
-  // pending error conditions.
-  asio::error_code wait(implementation_type& impl,
-      posix::descriptor_base::wait_type w, asio::error_code& ec)
-  {
-    switch (w)
-    {
-    case posix::descriptor_base::wait_read:
-      descriptor_ops::poll_read(impl.descriptor_, impl.state_, ec);
-      break;
-    case posix::descriptor_base::wait_write:
-      descriptor_ops::poll_write(impl.descriptor_, impl.state_, ec);
-      break;
-    case posix::descriptor_base::wait_error:
-      descriptor_ops::poll_error(impl.descriptor_, impl.state_, ec);
-      break;
-    default:
-      ec = asio::error::invalid_argument;
-      break;
-    }
-
-    return ec;
-  }
-
-  // Asynchronously wait for the descriptor to become ready to read, ready to
-  // write, or to have pending error conditions.
-  template <typename Handler>
-  void async_wait(implementation_type& impl,
-      posix::descriptor_base::wait_type w, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_wait_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "descriptor",
-          &impl, impl.descriptor_, "async_wait"));
-
-    int op_type;
-    switch (w)
-    {
-    case posix::descriptor_base::wait_read:
-        op_type = reactor::read_op;
-        break;
-    case posix::descriptor_base::wait_write:
-        op_type = reactor::write_op;
-        break;
-    case posix::descriptor_base::wait_error:
-        op_type = reactor::except_op;
-        break;
-      default:
-        p.p->ec_ = asio::error::invalid_argument;
-        reactor_.post_immediate_completion(p.p, is_continuation);
-        p.v = p.p = 0;
-        return;
-    }
-
-    start_op(impl, op_type, p.p, is_continuation, false, false);
-    p.v = p.p = 0;
-  }
-
-  // Write some data to the descriptor.
-  template <typename ConstBufferSequence>
-  size_t write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(buffers);
-
-    return descriptor_ops::sync_write(impl.descriptor_, impl.state_,
-        bufs.buffers(), bufs.count(), bufs.all_empty(), ec);
-  }
-
-  // Wait until data can be written without blocking.
-  size_t write_some(implementation_type& impl,
-      const null_buffers&, asio::error_code& ec)
-  {
-    // Wait for descriptor to become ready.
-    descriptor_ops::poll_write(impl.descriptor_, impl.state_, ec);
-
-    return 0;
-  }
-
-  // Start an asynchronous write. The data being sent must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef descriptor_write_op<ConstBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.descriptor_, buffers, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "descriptor",
-          &impl, impl.descriptor_, "async_write_some"));
-
-    start_op(impl, reactor::write_op, p.p, is_continuation, true,
-        buffer_sequence_adapter<asio::const_buffer,
-          ConstBufferSequence>::all_empty(buffers));
-    p.v = p.p = 0;
-  }
-
-  // Start an asynchronous wait until data can be written without blocking.
-  template <typename Handler>
-  void async_write_some(implementation_type& impl,
-      const null_buffers&, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "descriptor",
-          &impl, impl.descriptor_, "async_write_some(null_buffers)"));
-
-    start_op(impl, reactor::write_op, p.p, is_continuation, false, false);
-    p.v = p.p = 0;
-  }
-
-  // Read some data from the stream. Returns the number of bytes read.
-  template <typename MutableBufferSequence>
-  size_t read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    return descriptor_ops::sync_read(impl.descriptor_, impl.state_,
-        bufs.buffers(), bufs.count(), bufs.all_empty(), ec);
-  }
-
-  // Wait until data can be read without blocking.
-  size_t read_some(implementation_type& impl,
-      const null_buffers&, asio::error_code& ec)
-  {
-    // Wait for descriptor to become ready.
-    descriptor_ops::poll_read(impl.descriptor_, impl.state_, ec);
-
-    return 0;
-  }
-
-  // Start an asynchronous read. The buffer for the data being read must be
-  // valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef descriptor_read_op<MutableBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.descriptor_, buffers, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "descriptor",
-          &impl, impl.descriptor_, "async_read_some"));
-
-    start_op(impl, reactor::read_op, p.p, is_continuation, true,
-        buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::all_empty(buffers));
-    p.v = p.p = 0;
-  }
-
-  // Wait until data can be read without blocking.
-  template <typename Handler>
-  void async_read_some(implementation_type& impl,
-      const null_buffers&, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "descriptor",
-          &impl, impl.descriptor_, "async_read_some(null_buffers)"));
-
-    start_op(impl, reactor::read_op, p.p, is_continuation, false, false);
-    p.v = p.p = 0;
-  }
-
-private:
-  // Start the asynchronous operation.
-  ASIO_DECL void start_op(implementation_type& impl, int op_type,
-      reactor_op* op, bool is_continuation, bool is_non_blocking, bool noop);
-
-  // The selector that performs event demultiplexing for the service.
-  reactor& reactor_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/reactive_descriptor_service.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // !defined(ASIO_WINDOWS)
-       //   && !defined(ASIO_WINDOWS_RUNTIME)
-       //   && !defined(__CYGWIN__)
-
-#endif // ASIO_DETAIL_REACTIVE_DESCRIPTOR_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_null_buffers_op.hpp b/tools/sdk/include/asio/asio/detail/reactive_null_buffers_op.hpp
deleted file mode 100644
index 740826928dd..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_null_buffers_op.hpp
+++ /dev/null
@@ -1,90 +0,0 @@
-//
-// detail/reactive_null_buffers_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_NULL_BUFFERS_OP_HPP
-#define ASIO_DETAIL_REACTIVE_NULL_BUFFERS_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class reactive_null_buffers_op : public reactor_op
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_null_buffers_op);
-
-  reactive_null_buffers_op(Handler& handler)
-    : reactor_op(&reactive_null_buffers_op::do_perform,
-        &reactive_null_buffers_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static status do_perform(reactor_op*)
-  {
-    return done;
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_null_buffers_op* o(static_cast<reactive_null_buffers_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, o->bytes_transferred_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTIVE_NULL_BUFFERS_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_serial_port_service.hpp b/tools/sdk/include/asio/asio/detail/reactive_serial_port_service.hpp
deleted file mode 100644
index 6fddd9f1aac..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_serial_port_service.hpp
+++ /dev/null
@@ -1,236 +0,0 @@
-//
-// detail/reactive_serial_port_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Rep Invariant Systems, Inc. (info@repinvariant.com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SERIAL_PORT_SERVICE_HPP
-#define ASIO_DETAIL_REACTIVE_SERIAL_PORT_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_SERIAL_PORT)
-#if !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-#include <string>
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/serial_port_base.hpp"
-#include "asio/detail/descriptor_ops.hpp"
-#include "asio/detail/reactive_descriptor_service.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Extend reactive_descriptor_service to provide serial port support.
-class reactive_serial_port_service :
-  public service_base<reactive_serial_port_service>
-{
-public:
-  // The native type of a serial port.
-  typedef reactive_descriptor_service::native_handle_type native_handle_type;
-
-  // The implementation type of the serial port.
-  typedef reactive_descriptor_service::implementation_type implementation_type;
-
-  ASIO_DECL reactive_serial_port_service(
-      asio::io_context& io_context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Construct a new serial port implementation.
-  void construct(implementation_type& impl)
-  {
-    descriptor_service_.construct(impl);
-  }
-
-  // Move-construct a new serial port implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    descriptor_service_.move_construct(impl, other_impl);
-  }
-
-  // Move-assign from another serial port implementation.
-  void move_assign(implementation_type& impl,
-      reactive_serial_port_service& other_service,
-      implementation_type& other_impl)
-  {
-    descriptor_service_.move_assign(impl,
-        other_service.descriptor_service_, other_impl);
-  }
-
-  // Destroy a serial port implementation.
-  void destroy(implementation_type& impl)
-  {
-    descriptor_service_.destroy(impl);
-  }
-
-  // Open the serial port using the specified device name.
-  ASIO_DECL asio::error_code open(implementation_type& impl,
-      const std::string& device, asio::error_code& ec);
-
-  // Assign a native descriptor to a serial port implementation.
-  asio::error_code assign(implementation_type& impl,
-      const native_handle_type& native_descriptor,
-      asio::error_code& ec)
-  {
-    return descriptor_service_.assign(impl, native_descriptor, ec);
-  }
-
-  // Determine whether the serial port is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return descriptor_service_.is_open(impl);
-  }
-
-  // Destroy a serial port implementation.
-  asio::error_code close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return descriptor_service_.close(impl, ec);
-  }
-
-  // Get the native serial port representation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return descriptor_service_.native_handle(impl);
-  }
-
-  // Cancel all operations associated with the serial port.
-  asio::error_code cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return descriptor_service_.cancel(impl, ec);
-  }
-
-  // Set an option on the serial port.
-  template <typename SettableSerialPortOption>
-  asio::error_code set_option(implementation_type& impl,
-      const SettableSerialPortOption& option, asio::error_code& ec)
-  {
-    return do_set_option(impl,
-        &reactive_serial_port_service::store_option<SettableSerialPortOption>,
-        &option, ec);
-  }
-
-  // Get an option from the serial port.
-  template <typename GettableSerialPortOption>
-  asio::error_code get_option(const implementation_type& impl,
-      GettableSerialPortOption& option, asio::error_code& ec) const
-  {
-    return do_get_option(impl,
-        &reactive_serial_port_service::load_option<GettableSerialPortOption>,
-        &option, ec);
-  }
-
-  // Send a break sequence to the serial port.
-  asio::error_code send_break(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    errno = 0;
-    descriptor_ops::error_wrapper(::tcsendbreak(
-          descriptor_service_.native_handle(impl), 0), ec);
-    return ec;
-  }
-
-  // Write the given data. Returns the number of bytes sent.
-  template <typename ConstBufferSequence>
-  size_t write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    return descriptor_service_.write_some(impl, buffers, ec);
-  }
-
-  // Start an asynchronous write. The data being written must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, Handler& handler)
-  {
-    descriptor_service_.async_write_some(impl, buffers, handler);
-  }
-
-  // Read some data. Returns the number of bytes received.
-  template <typename MutableBufferSequence>
-  size_t read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    return descriptor_service_.read_some(impl, buffers, ec);
-  }
-
-  // Start an asynchronous read. The buffer for the data being received must be
-  // valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, Handler& handler)
-  {
-    descriptor_service_.async_read_some(impl, buffers, handler);
-  }
-
-private:
-  // Function pointer type for storing a serial port option.
-  typedef asio::error_code (*store_function_type)(
-      const void*, termios&, asio::error_code&);
-
-  // Helper function template to store a serial port option.
-  template <typename SettableSerialPortOption>
-  static asio::error_code store_option(const void* option,
-      termios& storage, asio::error_code& ec)
-  {
-    static_cast<const SettableSerialPortOption*>(option)->store(storage, ec);
-    return ec;
-  }
-
-  // Helper function to set a serial port option.
-  ASIO_DECL asio::error_code do_set_option(
-      implementation_type& impl, store_function_type store,
-      const void* option, asio::error_code& ec);
-
-  // Function pointer type for loading a serial port option.
-  typedef asio::error_code (*load_function_type)(
-      void*, const termios&, asio::error_code&);
-
-  // Helper function template to load a serial port option.
-  template <typename GettableSerialPortOption>
-  static asio::error_code load_option(void* option,
-      const termios& storage, asio::error_code& ec)
-  {
-    static_cast<GettableSerialPortOption*>(option)->load(storage, ec);
-    return ec;
-  }
-
-  // Helper function to get a serial port option.
-  ASIO_DECL asio::error_code do_get_option(
-      const implementation_type& impl, load_function_type load,
-      void* option, asio::error_code& ec) const;
-
-  // The implementation used for initiating asynchronous operations.
-  reactive_descriptor_service descriptor_service_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/reactive_serial_port_service.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-#endif // defined(ASIO_HAS_SERIAL_PORT)
-
-#endif // ASIO_DETAIL_REACTIVE_SERIAL_PORT_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_socket_accept_op.hpp b/tools/sdk/include/asio/asio/detail/reactive_socket_accept_op.hpp
deleted file mode 100644
index 4a98f047f78..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_socket_accept_op.hpp
+++ /dev/null
@@ -1,217 +0,0 @@
-//
-// detail/reactive_socket_accept_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SOCKET_ACCEPT_OP_HPP
-#define ASIO_DETAIL_REACTIVE_SOCKET_ACCEPT_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_holder.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Socket, typename Protocol>
-class reactive_socket_accept_op_base : public reactor_op
-{
-public:
-  reactive_socket_accept_op_base(socket_type socket,
-      socket_ops::state_type state, Socket& peer, const Protocol& protocol,
-      typename Protocol::endpoint* peer_endpoint, func_type complete_func)
-    : reactor_op(&reactive_socket_accept_op_base::do_perform, complete_func),
-      socket_(socket),
-      state_(state),
-      peer_(peer),
-      protocol_(protocol),
-      peer_endpoint_(peer_endpoint),
-      addrlen_(peer_endpoint ? peer_endpoint->capacity() : 0)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    reactive_socket_accept_op_base* o(
-        static_cast<reactive_socket_accept_op_base*>(base));
-
-    socket_type new_socket = invalid_socket;
-    status result = socket_ops::non_blocking_accept(o->socket_,
-        o->state_, o->peer_endpoint_ ? o->peer_endpoint_->data() : 0,
-        o->peer_endpoint_ ? &o->addrlen_ : 0, o->ec_, new_socket)
-    ? done : not_done;
-    o->new_socket_.reset(new_socket);
-
-    ASIO_HANDLER_REACTOR_OPERATION((*o, "non_blocking_accept", o->ec_));
-
-    return result;
-  }
-
-  void do_assign()
-  {
-    if (new_socket_.get() != invalid_socket)
-    {
-      if (peer_endpoint_)
-        peer_endpoint_->resize(addrlen_);
-      peer_.assign(protocol_, new_socket_.get(), ec_);
-      if (!ec_)
-        new_socket_.release();
-    }
-  }
-
-private:
-  socket_type socket_;
-  socket_ops::state_type state_;
-  socket_holder new_socket_;
-  Socket& peer_;
-  Protocol protocol_;
-  typename Protocol::endpoint* peer_endpoint_;
-  std::size_t addrlen_;
-};
-
-template <typename Socket, typename Protocol, typename Handler>
-class reactive_socket_accept_op :
-  public reactive_socket_accept_op_base<Socket, Protocol>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_socket_accept_op);
-
-  reactive_socket_accept_op(socket_type socket,
-      socket_ops::state_type state, Socket& peer, const Protocol& protocol,
-      typename Protocol::endpoint* peer_endpoint, Handler& handler)
-    : reactive_socket_accept_op_base<Socket, Protocol>(socket, state, peer,
-        protocol, peer_endpoint, &reactive_socket_accept_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_socket_accept_op* o(static_cast<reactive_socket_accept_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    // On success, assign new connection to peer socket object.
-    if (owner)
-      o->do_assign();
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder1<Handler, asio::error_code>
-      handler(o->handler_, o->ec_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-#if defined(ASIO_HAS_MOVE)
-
-template <typename Protocol, typename Handler>
-class reactive_socket_move_accept_op :
-  private Protocol::socket,
-  public reactive_socket_accept_op_base<typename Protocol::socket, Protocol>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_socket_move_accept_op);
-
-  reactive_socket_move_accept_op(io_context& ioc, socket_type socket,
-      socket_ops::state_type state, const Protocol& protocol,
-      typename Protocol::endpoint* peer_endpoint, Handler& handler)
-    : Protocol::socket(ioc),
-      reactive_socket_accept_op_base<typename Protocol::socket, Protocol>(
-        socket, state, *this, protocol, peer_endpoint,
-        &reactive_socket_move_accept_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_socket_move_accept_op* o(
-        static_cast<reactive_socket_move_accept_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    // On success, assign new connection to peer socket object.
-    if (owner)
-      o->do_assign();
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::move_binder2<Handler,
-      asio::error_code, typename Protocol::socket>
-        handler(0, ASIO_MOVE_CAST(Handler)(o->handler_), o->ec_,
-          ASIO_MOVE_CAST(typename Protocol::socket)(*o));
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, "..."));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-#endif // defined(ASIO_HAS_MOVE)
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTIVE_SOCKET_ACCEPT_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_socket_connect_op.hpp b/tools/sdk/include/asio/asio/detail/reactive_socket_connect_op.hpp
deleted file mode 100644
index 76164b2a8ed..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_socket_connect_op.hpp
+++ /dev/null
@@ -1,113 +0,0 @@
-//
-// detail/reactive_socket_connect_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SOCKET_CONNECT_OP_HPP
-#define ASIO_DETAIL_REACTIVE_SOCKET_CONNECT_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class reactive_socket_connect_op_base : public reactor_op
-{
-public:
-  reactive_socket_connect_op_base(socket_type socket, func_type complete_func)
-    : reactor_op(&reactive_socket_connect_op_base::do_perform, complete_func),
-      socket_(socket)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    reactive_socket_connect_op_base* o(
-        static_cast<reactive_socket_connect_op_base*>(base));
-
-    status result = socket_ops::non_blocking_connect(
-        o->socket_, o->ec_) ? done : not_done;
-
-    ASIO_HANDLER_REACTOR_OPERATION((*o, "non_blocking_connect", o->ec_));
-
-    return result;
-  }
-
-private:
-  socket_type socket_;
-};
-
-template <typename Handler>
-class reactive_socket_connect_op : public reactive_socket_connect_op_base
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_socket_connect_op);
-
-  reactive_socket_connect_op(socket_type socket, Handler& handler)
-    : reactive_socket_connect_op_base(socket,
-        &reactive_socket_connect_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_socket_connect_op* o
-      (static_cast<reactive_socket_connect_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder1<Handler, asio::error_code>
-      handler(o->handler_, o->ec_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTIVE_SOCKET_CONNECT_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_socket_recv_op.hpp b/tools/sdk/include/asio/asio/detail/reactive_socket_recv_op.hpp
deleted file mode 100644
index 04bd266f9cf..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_socket_recv_op.hpp
+++ /dev/null
@@ -1,135 +0,0 @@
-//
-// detail/reactive_socket_recv_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SOCKET_RECV_OP_HPP
-#define ASIO_DETAIL_REACTIVE_SOCKET_RECV_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename MutableBufferSequence>
-class reactive_socket_recv_op_base : public reactor_op
-{
-public:
-  reactive_socket_recv_op_base(socket_type socket,
-      socket_ops::state_type state, const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, func_type complete_func)
-    : reactor_op(&reactive_socket_recv_op_base::do_perform, complete_func),
-      socket_(socket),
-      state_(state),
-      buffers_(buffers),
-      flags_(flags)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    reactive_socket_recv_op_base* o(
-        static_cast<reactive_socket_recv_op_base*>(base));
-
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(o->buffers_);
-
-    status result = socket_ops::non_blocking_recv(o->socket_,
-        bufs.buffers(), bufs.count(), o->flags_,
-        (o->state_ & socket_ops::stream_oriented) != 0,
-        o->ec_, o->bytes_transferred_) ? done : not_done;
-
-    if (result == done)
-      if ((o->state_ & socket_ops::stream_oriented) != 0)
-        if (o->bytes_transferred_ == 0)
-          result = done_and_exhausted;
-
-    ASIO_HANDLER_REACTOR_OPERATION((*o, "non_blocking_recv",
-          o->ec_, o->bytes_transferred_));
-
-    return result;
-  }
-
-private:
-  socket_type socket_;
-  socket_ops::state_type state_;
-  MutableBufferSequence buffers_;
-  socket_base::message_flags flags_;
-};
-
-template <typename MutableBufferSequence, typename Handler>
-class reactive_socket_recv_op :
-  public reactive_socket_recv_op_base<MutableBufferSequence>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_socket_recv_op);
-
-  reactive_socket_recv_op(socket_type socket,
-      socket_ops::state_type state, const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, Handler& handler)
-    : reactive_socket_recv_op_base<MutableBufferSequence>(socket, state,
-        buffers, flags, &reactive_socket_recv_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_socket_recv_op* o(static_cast<reactive_socket_recv_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, o->bytes_transferred_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTIVE_SOCKET_RECV_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_socket_recvfrom_op.hpp b/tools/sdk/include/asio/asio/detail/reactive_socket_recvfrom_op.hpp
deleted file mode 100644
index 3d4fa4cadf7..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_socket_recvfrom_op.hpp
+++ /dev/null
@@ -1,138 +0,0 @@
-//
-// detail/reactive_socket_recvfrom_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SOCKET_RECVFROM_OP_HPP
-#define ASIO_DETAIL_REACTIVE_SOCKET_RECVFROM_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename MutableBufferSequence, typename Endpoint>
-class reactive_socket_recvfrom_op_base : public reactor_op
-{
-public:
-  reactive_socket_recvfrom_op_base(socket_type socket, int protocol_type,
-      const MutableBufferSequence& buffers, Endpoint& endpoint,
-      socket_base::message_flags flags, func_type complete_func)
-    : reactor_op(&reactive_socket_recvfrom_op_base::do_perform, complete_func),
-      socket_(socket),
-      protocol_type_(protocol_type),
-      buffers_(buffers),
-      sender_endpoint_(endpoint),
-      flags_(flags)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    reactive_socket_recvfrom_op_base* o(
-        static_cast<reactive_socket_recvfrom_op_base*>(base));
-
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(o->buffers_);
-
-    std::size_t addr_len = o->sender_endpoint_.capacity();
-    status result = socket_ops::non_blocking_recvfrom(o->socket_,
-        bufs.buffers(), bufs.count(), o->flags_,
-        o->sender_endpoint_.data(), &addr_len,
-        o->ec_, o->bytes_transferred_) ? done : not_done;
-
-    if (result && !o->ec_)
-      o->sender_endpoint_.resize(addr_len);
-
-    ASIO_HANDLER_REACTOR_OPERATION((*o, "non_blocking_recvfrom",
-          o->ec_, o->bytes_transferred_));
-
-    return result;
-  }
-
-private:
-  socket_type socket_;
-  int protocol_type_;
-  MutableBufferSequence buffers_;
-  Endpoint& sender_endpoint_;
-  socket_base::message_flags flags_;
-};
-
-template <typename MutableBufferSequence, typename Endpoint, typename Handler>
-class reactive_socket_recvfrom_op :
-  public reactive_socket_recvfrom_op_base<MutableBufferSequence, Endpoint>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_socket_recvfrom_op);
-
-  reactive_socket_recvfrom_op(socket_type socket, int protocol_type,
-      const MutableBufferSequence& buffers, Endpoint& endpoint,
-      socket_base::message_flags flags, Handler& handler)
-    : reactive_socket_recvfrom_op_base<MutableBufferSequence, Endpoint>(
-        socket, protocol_type, buffers, endpoint, flags,
-        &reactive_socket_recvfrom_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_socket_recvfrom_op* o(
-        static_cast<reactive_socket_recvfrom_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, o->bytes_transferred_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTIVE_SOCKET_RECVFROM_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_socket_recvmsg_op.hpp b/tools/sdk/include/asio/asio/detail/reactive_socket_recvmsg_op.hpp
deleted file mode 100644
index f473274724a..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_socket_recvmsg_op.hpp
+++ /dev/null
@@ -1,132 +0,0 @@
-//
-// detail/reactive_socket_recvmsg_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SOCKET_RECVMSG_OP_HPP
-#define ASIO_DETAIL_REACTIVE_SOCKET_RECVMSG_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/socket_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename MutableBufferSequence>
-class reactive_socket_recvmsg_op_base : public reactor_op
-{
-public:
-  reactive_socket_recvmsg_op_base(socket_type socket,
-      const MutableBufferSequence& buffers, socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, func_type complete_func)
-    : reactor_op(&reactive_socket_recvmsg_op_base::do_perform, complete_func),
-      socket_(socket),
-      buffers_(buffers),
-      in_flags_(in_flags),
-      out_flags_(out_flags)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    reactive_socket_recvmsg_op_base* o(
-        static_cast<reactive_socket_recvmsg_op_base*>(base));
-
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(o->buffers_);
-
-    status result = socket_ops::non_blocking_recvmsg(o->socket_,
-        bufs.buffers(), bufs.count(),
-        o->in_flags_, o->out_flags_,
-        o->ec_, o->bytes_transferred_) ? done : not_done;
-
-    ASIO_HANDLER_REACTOR_OPERATION((*o, "non_blocking_recvmsg",
-          o->ec_, o->bytes_transferred_));
-
-    return result;
-  }
-
-private:
-  socket_type socket_;
-  MutableBufferSequence buffers_;
-  socket_base::message_flags in_flags_;
-  socket_base::message_flags& out_flags_;
-};
-
-template <typename MutableBufferSequence, typename Handler>
-class reactive_socket_recvmsg_op :
-  public reactive_socket_recvmsg_op_base<MutableBufferSequence>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_socket_recvmsg_op);
-
-  reactive_socket_recvmsg_op(socket_type socket,
-      const MutableBufferSequence& buffers, socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, Handler& handler)
-    : reactive_socket_recvmsg_op_base<MutableBufferSequence>(socket, buffers,
-        in_flags, out_flags, &reactive_socket_recvmsg_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_socket_recvmsg_op* o(
-        static_cast<reactive_socket_recvmsg_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, o->bytes_transferred_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTIVE_SOCKET_RECVMSG_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_socket_send_op.hpp b/tools/sdk/include/asio/asio/detail/reactive_socket_send_op.hpp
deleted file mode 100644
index bd550d9c5ea..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_socket_send_op.hpp
+++ /dev/null
@@ -1,134 +0,0 @@
-//
-// detail/reactive_socket_send_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SOCKET_SEND_OP_HPP
-#define ASIO_DETAIL_REACTIVE_SOCKET_SEND_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename ConstBufferSequence>
-class reactive_socket_send_op_base : public reactor_op
-{
-public:
-  reactive_socket_send_op_base(socket_type socket,
-      socket_ops::state_type state, const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, func_type complete_func)
-    : reactor_op(&reactive_socket_send_op_base::do_perform, complete_func),
-      socket_(socket),
-      state_(state),
-      buffers_(buffers),
-      flags_(flags)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    reactive_socket_send_op_base* o(
-        static_cast<reactive_socket_send_op_base*>(base));
-
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(o->buffers_);
-
-    status result = socket_ops::non_blocking_send(o->socket_,
-          bufs.buffers(), bufs.count(), o->flags_,
-          o->ec_, o->bytes_transferred_) ? done : not_done;
-
-    if (result == done)
-      if ((o->state_ & socket_ops::stream_oriented) != 0)
-        if (o->bytes_transferred_ < bufs.total_size())
-          result = done_and_exhausted;
-
-    ASIO_HANDLER_REACTOR_OPERATION((*o, "non_blocking_send",
-          o->ec_, o->bytes_transferred_));
-
-    return result;
-  }
-
-private:
-  socket_type socket_;
-  socket_ops::state_type state_;
-  ConstBufferSequence buffers_;
-  socket_base::message_flags flags_;
-};
-
-template <typename ConstBufferSequence, typename Handler>
-class reactive_socket_send_op :
-  public reactive_socket_send_op_base<ConstBufferSequence>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_socket_send_op);
-
-  reactive_socket_send_op(socket_type socket,
-      socket_ops::state_type state, const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, Handler& handler)
-    : reactive_socket_send_op_base<ConstBufferSequence>(socket,
-        state, buffers, flags, &reactive_socket_send_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_socket_send_op* o(static_cast<reactive_socket_send_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, o->bytes_transferred_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTIVE_SOCKET_SEND_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_socket_sendto_op.hpp b/tools/sdk/include/asio/asio/detail/reactive_socket_sendto_op.hpp
deleted file mode 100644
index c97554d7b68..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_socket_sendto_op.hpp
+++ /dev/null
@@ -1,130 +0,0 @@
-//
-// detail/reactive_socket_sendto_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SOCKET_SENDTO_OP_HPP
-#define ASIO_DETAIL_REACTIVE_SOCKET_SENDTO_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename ConstBufferSequence, typename Endpoint>
-class reactive_socket_sendto_op_base : public reactor_op
-{
-public:
-  reactive_socket_sendto_op_base(socket_type socket,
-      const ConstBufferSequence& buffers, const Endpoint& endpoint,
-      socket_base::message_flags flags, func_type complete_func)
-    : reactor_op(&reactive_socket_sendto_op_base::do_perform, complete_func),
-      socket_(socket),
-      buffers_(buffers),
-      destination_(endpoint),
-      flags_(flags)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    reactive_socket_sendto_op_base* o(
-        static_cast<reactive_socket_sendto_op_base*>(base));
-
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(o->buffers_);
-
-    status result = socket_ops::non_blocking_sendto(o->socket_,
-          bufs.buffers(), bufs.count(), o->flags_,
-          o->destination_.data(), o->destination_.size(),
-          o->ec_, o->bytes_transferred_) ? done : not_done;
-
-    ASIO_HANDLER_REACTOR_OPERATION((*o, "non_blocking_sendto",
-          o->ec_, o->bytes_transferred_));
-
-    return result;
-  }
-
-private:
-  socket_type socket_;
-  ConstBufferSequence buffers_;
-  Endpoint destination_;
-  socket_base::message_flags flags_;
-};
-
-template <typename ConstBufferSequence, typename Endpoint, typename Handler>
-class reactive_socket_sendto_op :
-  public reactive_socket_sendto_op_base<ConstBufferSequence, Endpoint>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_socket_sendto_op);
-
-  reactive_socket_sendto_op(socket_type socket,
-      const ConstBufferSequence& buffers, const Endpoint& endpoint,
-      socket_base::message_flags flags, Handler& handler)
-    : reactive_socket_sendto_op_base<ConstBufferSequence, Endpoint>(socket,
-        buffers, endpoint, flags, &reactive_socket_sendto_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_socket_sendto_op* o(static_cast<reactive_socket_sendto_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, o->bytes_transferred_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTIVE_SOCKET_SENDTO_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_socket_service.hpp b/tools/sdk/include/asio/asio/detail/reactive_socket_service.hpp
deleted file mode 100644
index 15a4fdb588e..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_socket_service.hpp
+++ /dev/null
@@ -1,526 +0,0 @@
-//
-// detail/reactive_socket_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SOCKET_SERVICE_HPP
-#define ASIO_DETAIL_REACTIVE_SOCKET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_IOCP)
-
-#include "asio/buffer.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/socket_base.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/reactive_null_buffers_op.hpp"
-#include "asio/detail/reactive_socket_accept_op.hpp"
-#include "asio/detail/reactive_socket_connect_op.hpp"
-#include "asio/detail/reactive_socket_recvfrom_op.hpp"
-#include "asio/detail/reactive_socket_sendto_op.hpp"
-#include "asio/detail/reactive_socket_service_base.hpp"
-#include "asio/detail/reactor.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_holder.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Protocol>
-class reactive_socket_service :
-  public service_base<reactive_socket_service<Protocol> >,
-  public reactive_socket_service_base
-{
-public:
-  // The protocol type.
-  typedef Protocol protocol_type;
-
-  // The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  // The native type of a socket.
-  typedef socket_type native_handle_type;
-
-  // The implementation type of the socket.
-  struct implementation_type :
-    reactive_socket_service_base::base_implementation_type
-  {
-    // Default constructor.
-    implementation_type()
-      : protocol_(endpoint_type().protocol())
-    {
-    }
-
-    // The protocol associated with the socket.
-    protocol_type protocol_;
-  };
-
-  // Constructor.
-  reactive_socket_service(asio::io_context& io_context)
-    : service_base<reactive_socket_service<Protocol> >(io_context),
-      reactive_socket_service_base(io_context)
-  {
-  }
-
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    this->base_shutdown();
-  }
-
-  // Move-construct a new socket implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    this->base_move_construct(impl, other_impl);
-
-    impl.protocol_ = other_impl.protocol_;
-    other_impl.protocol_ = endpoint_type().protocol();
-  }
-
-  // Move-assign from another socket implementation.
-  void move_assign(implementation_type& impl,
-      reactive_socket_service_base& other_service,
-      implementation_type& other_impl)
-  {
-    this->base_move_assign(impl, other_service, other_impl);
-
-    impl.protocol_ = other_impl.protocol_;
-    other_impl.protocol_ = endpoint_type().protocol();
-  }
-
-  // Move-construct a new socket implementation from another protocol type.
-  template <typename Protocol1>
-  void converting_move_construct(implementation_type& impl,
-      reactive_socket_service<Protocol1>&,
-      typename reactive_socket_service<
-        Protocol1>::implementation_type& other_impl)
-  {
-    this->base_move_construct(impl, other_impl);
-
-    impl.protocol_ = protocol_type(other_impl.protocol_);
-    other_impl.protocol_ = typename Protocol1::endpoint().protocol();
-  }
-
-  // Open a new socket implementation.
-  asio::error_code open(implementation_type& impl,
-      const protocol_type& protocol, asio::error_code& ec)
-  {
-    if (!do_open(impl, protocol.family(),
-          protocol.type(), protocol.protocol(), ec))
-      impl.protocol_ = protocol;
-    return ec;
-  }
-
-  // Assign a native socket to a socket implementation.
-  asio::error_code assign(implementation_type& impl,
-      const protocol_type& protocol, const native_handle_type& native_socket,
-      asio::error_code& ec)
-  {
-    if (!do_assign(impl, protocol.type(), native_socket, ec))
-      impl.protocol_ = protocol;
-    return ec;
-  }
-
-  // Get the native socket representation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return impl.socket_;
-  }
-
-  // Bind the socket to the specified local endpoint.
-  asio::error_code bind(implementation_type& impl,
-      const endpoint_type& endpoint, asio::error_code& ec)
-  {
-    socket_ops::bind(impl.socket_, endpoint.data(), endpoint.size(), ec);
-    return ec;
-  }
-
-  // Set a socket option.
-  template <typename Option>
-  asio::error_code set_option(implementation_type& impl,
-      const Option& option, asio::error_code& ec)
-  {
-    socket_ops::setsockopt(impl.socket_, impl.state_,
-        option.level(impl.protocol_), option.name(impl.protocol_),
-        option.data(impl.protocol_), option.size(impl.protocol_), ec);
-    return ec;
-  }
-
-  // Set a socket option.
-  template <typename Option>
-  asio::error_code get_option(const implementation_type& impl,
-      Option& option, asio::error_code& ec) const
-  {
-    std::size_t size = option.size(impl.protocol_);
-    socket_ops::getsockopt(impl.socket_, impl.state_,
-        option.level(impl.protocol_), option.name(impl.protocol_),
-        option.data(impl.protocol_), &size, ec);
-    if (!ec)
-      option.resize(impl.protocol_, size);
-    return ec;
-  }
-
-  // Get the local endpoint.
-  endpoint_type local_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    endpoint_type endpoint;
-    std::size_t addr_len = endpoint.capacity();
-    if (socket_ops::getsockname(impl.socket_, endpoint.data(), &addr_len, ec))
-      return endpoint_type();
-    endpoint.resize(addr_len);
-    return endpoint;
-  }
-
-  // Get the remote endpoint.
-  endpoint_type remote_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    endpoint_type endpoint;
-    std::size_t addr_len = endpoint.capacity();
-    if (socket_ops::getpeername(impl.socket_,
-          endpoint.data(), &addr_len, false, ec))
-      return endpoint_type();
-    endpoint.resize(addr_len);
-    return endpoint;
-  }
-
-  // Disable sends or receives on the socket.
-  asio::error_code shutdown(base_implementation_type& impl,
-      socket_base::shutdown_type what, asio::error_code& ec)
-  {
-    socket_ops::shutdown(impl.socket_, what, ec);
-    return ec;
-  }
-
-  // Send a datagram to the specified endpoint. Returns the number of bytes
-  // sent.
-  template <typename ConstBufferSequence>
-  size_t send_to(implementation_type& impl, const ConstBufferSequence& buffers,
-      const endpoint_type& destination, socket_base::message_flags flags,
-      asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(buffers);
-
-    return socket_ops::sync_sendto(impl.socket_, impl.state_,
-        bufs.buffers(), bufs.count(), flags,
-        destination.data(), destination.size(), ec);
-  }
-
-  // Wait until data can be sent without blocking.
-  size_t send_to(implementation_type& impl, const null_buffers&,
-      const endpoint_type&, socket_base::message_flags,
-      asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_write(impl.socket_, impl.state_, -1, ec);
-
-    return 0;
-  }
-
-  // Start an asynchronous send. The data being sent must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_send_to(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      const endpoint_type& destination, socket_base::message_flags flags,
-      Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_socket_sendto_op<ConstBufferSequence,
-        endpoint_type, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.socket_, buffers, destination, flags, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_send_to"));
-
-    start_op(impl, reactor::write_op, p.p, is_continuation, true, false);
-    p.v = p.p = 0;
-  }
-
-  // Start an asynchronous wait until data can be sent without blocking.
-  template <typename Handler>
-  void async_send_to(implementation_type& impl, const null_buffers&,
-      const endpoint_type&, socket_base::message_flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_send_to(null_buffers)"));
-
-    start_op(impl, reactor::write_op, p.p, is_continuation, false, false);
-    p.v = p.p = 0;
-  }
-
-  // Receive a datagram with the endpoint of the sender. Returns the number of
-  // bytes received.
-  template <typename MutableBufferSequence>
-  size_t receive_from(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint, socket_base::message_flags flags,
-      asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    std::size_t addr_len = sender_endpoint.capacity();
-    std::size_t bytes_recvd = socket_ops::sync_recvfrom(
-        impl.socket_, impl.state_, bufs.buffers(), bufs.count(),
-        flags, sender_endpoint.data(), &addr_len, ec);
-
-    if (!ec)
-      sender_endpoint.resize(addr_len);
-
-    return bytes_recvd;
-  }
-
-  // Wait until data can be received without blocking.
-  size_t receive_from(implementation_type& impl, const null_buffers&,
-      endpoint_type& sender_endpoint, socket_base::message_flags,
-      asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_read(impl.socket_, impl.state_, -1, ec);
-
-    // Reset endpoint since it can be given no sensible value at this time.
-    sender_endpoint = endpoint_type();
-
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received and
-  // the sender_endpoint object must both be valid for the lifetime of the
-  // asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive_from(implementation_type& impl,
-      const MutableBufferSequence& buffers, endpoint_type& sender_endpoint,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_socket_recvfrom_op<MutableBufferSequence,
-        endpoint_type, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    int protocol = impl.protocol_.type();
-    p.p = new (p.v) op(impl.socket_, protocol,
-        buffers, sender_endpoint, flags, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_receive_from"));
-
-    start_op(impl,
-        (flags & socket_base::message_out_of_band)
-          ? reactor::except_op : reactor::read_op,
-        p.p, is_continuation, true, false);
-    p.v = p.p = 0;
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive_from(implementation_type& impl,
-      const null_buffers&, endpoint_type& sender_endpoint,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_receive_from(null_buffers)"));
-
-    // Reset endpoint since it can be given no sensible value at this time.
-    sender_endpoint = endpoint_type();
-
-    start_op(impl,
-        (flags & socket_base::message_out_of_band)
-          ? reactor::except_op : reactor::read_op,
-        p.p, is_continuation, false, false);
-    p.v = p.p = 0;
-  }
-
-  // Accept a new connection.
-  template <typename Socket>
-  asio::error_code accept(implementation_type& impl,
-      Socket& peer, endpoint_type* peer_endpoint, asio::error_code& ec)
-  {
-    // We cannot accept a socket that is already open.
-    if (peer.is_open())
-    {
-      ec = asio::error::already_open;
-      return ec;
-    }
-
-    std::size_t addr_len = peer_endpoint ? peer_endpoint->capacity() : 0;
-    socket_holder new_socket(socket_ops::sync_accept(impl.socket_,
-          impl.state_, peer_endpoint ? peer_endpoint->data() : 0,
-          peer_endpoint ? &addr_len : 0, ec));
-
-    // On success, assign new connection to peer socket object.
-    if (new_socket.get() != invalid_socket)
-    {
-      if (peer_endpoint)
-        peer_endpoint->resize(addr_len);
-      peer.assign(impl.protocol_, new_socket.get(), ec);
-      if (!ec)
-        new_socket.release();
-    }
-
-    return ec;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  // Accept a new connection.
-  typename Protocol::socket accept(implementation_type& impl,
-      io_context* peer_io_context, endpoint_type* peer_endpoint,
-      asio::error_code& ec)
-  {
-    typename Protocol::socket peer(
-        peer_io_context ? *peer_io_context : io_context_);
-
-    std::size_t addr_len = peer_endpoint ? peer_endpoint->capacity() : 0;
-    socket_holder new_socket(socket_ops::sync_accept(impl.socket_,
-          impl.state_, peer_endpoint ? peer_endpoint->data() : 0,
-          peer_endpoint ? &addr_len : 0, ec));
-
-    // On success, assign new connection to peer socket object.
-    if (new_socket.get() != invalid_socket)
-    {
-      if (peer_endpoint)
-        peer_endpoint->resize(addr_len);
-      peer.assign(impl.protocol_, new_socket.get(), ec);
-      if (!ec)
-        new_socket.release();
-    }
-
-    return peer;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  // Start an asynchronous accept. The peer and peer_endpoint objects must be
-  // valid until the accept's handler is invoked.
-  template <typename Socket, typename Handler>
-  void async_accept(implementation_type& impl, Socket& peer,
-      endpoint_type* peer_endpoint, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_socket_accept_op<Socket, Protocol, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.socket_, impl.state_, peer,
-        impl.protocol_, peer_endpoint, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_accept"));
-
-    start_accept_op(impl, p.p, is_continuation, peer.is_open());
-    p.v = p.p = 0;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  // Start an asynchronous accept. The peer_endpoint object must be valid until
-  // the accept's handler is invoked.
-  template <typename Handler>
-  void async_accept(implementation_type& impl,
-      asio::io_context* peer_io_context,
-      endpoint_type* peer_endpoint, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_socket_move_accept_op<Protocol, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(peer_io_context ? *peer_io_context : io_context_,
-        impl.socket_, impl.state_, impl.protocol_, peer_endpoint, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_accept"));
-
-    start_accept_op(impl, p.p, is_continuation, false);
-    p.v = p.p = 0;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  // Connect the socket to the specified endpoint.
-  asio::error_code connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, asio::error_code& ec)
-  {
-    socket_ops::sync_connect(impl.socket_,
-        peer_endpoint.data(), peer_endpoint.size(), ec);
-    return ec;
-  }
-
-  // Start an asynchronous connect.
-  template <typename Handler>
-  void async_connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_socket_connect_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.socket_, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_connect"));
-
-    start_connect_op(impl, p.p, is_continuation,
-        peer_endpoint.data(), peer_endpoint.size());
-    p.v = p.p = 0;
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_REACTIVE_SOCKET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_socket_service_base.hpp b/tools/sdk/include/asio/asio/detail/reactive_socket_service_base.hpp
deleted file mode 100644
index ccd497e8013..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_socket_service_base.hpp
+++ /dev/null
@@ -1,511 +0,0 @@
-//
-// detail/reactive_socket_service_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_SOCKET_SERVICE_BASE_HPP
-#define ASIO_DETAIL_REACTIVE_SOCKET_SERVICE_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_IOCP) \
-  && !defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/buffer.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/socket_base.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactive_null_buffers_op.hpp"
-#include "asio/detail/reactive_socket_recv_op.hpp"
-#include "asio/detail/reactive_socket_recvmsg_op.hpp"
-#include "asio/detail/reactive_socket_send_op.hpp"
-#include "asio/detail/reactive_wait_op.hpp"
-#include "asio/detail/reactor.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_holder.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class reactive_socket_service_base
-{
-public:
-  // The native type of a socket.
-  typedef socket_type native_handle_type;
-
-  // The implementation type of the socket.
-  struct base_implementation_type
-  {
-    // The native socket representation.
-    socket_type socket_;
-
-    // The current state of the socket.
-    socket_ops::state_type state_;
-
-    // Per-descriptor data used by the reactor.
-    reactor::per_descriptor_data reactor_data_;
-  };
-
-  // Constructor.
-  ASIO_DECL reactive_socket_service_base(
-      asio::io_context& io_context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void base_shutdown();
-
-  // Construct a new socket implementation.
-  ASIO_DECL void construct(base_implementation_type& impl);
-
-  // Move-construct a new socket implementation.
-  ASIO_DECL void base_move_construct(base_implementation_type& impl,
-      base_implementation_type& other_impl);
-
-  // Move-assign from another socket implementation.
-  ASIO_DECL void base_move_assign(base_implementation_type& impl,
-      reactive_socket_service_base& other_service,
-      base_implementation_type& other_impl);
-
-  // Destroy a socket implementation.
-  ASIO_DECL void destroy(base_implementation_type& impl);
-
-  // Determine whether the socket is open.
-  bool is_open(const base_implementation_type& impl) const
-  {
-    return impl.socket_ != invalid_socket;
-  }
-
-  // Destroy a socket implementation.
-  ASIO_DECL asio::error_code close(
-      base_implementation_type& impl, asio::error_code& ec);
-
-  // Release ownership of the socket.
-  ASIO_DECL socket_type release(
-      base_implementation_type& impl, asio::error_code& ec);
-
-  // Get the native socket representation.
-  native_handle_type native_handle(base_implementation_type& impl)
-  {
-    return impl.socket_;
-  }
-
-  // Cancel all operations associated with the socket.
-  ASIO_DECL asio::error_code cancel(
-      base_implementation_type& impl, asio::error_code& ec);
-
-  // Determine whether the socket is at the out-of-band data mark.
-  bool at_mark(const base_implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return socket_ops::sockatmark(impl.socket_, ec);
-  }
-
-  // Determine the number of bytes available for reading.
-  std::size_t available(const base_implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return socket_ops::available(impl.socket_, ec);
-  }
-
-  // Place the socket into the state where it will listen for new connections.
-  asio::error_code listen(base_implementation_type& impl,
-      int backlog, asio::error_code& ec)
-  {
-    socket_ops::listen(impl.socket_, backlog, ec);
-    return ec;
-  }
-
-  // Perform an IO control command on the socket.
-  template <typename IO_Control_Command>
-  asio::error_code io_control(base_implementation_type& impl,
-      IO_Control_Command& command, asio::error_code& ec)
-  {
-    socket_ops::ioctl(impl.socket_, impl.state_, command.name(),
-        static_cast<ioctl_arg_type*>(command.data()), ec);
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the socket.
-  bool non_blocking(const base_implementation_type& impl) const
-  {
-    return (impl.state_ & socket_ops::user_set_non_blocking) != 0;
-  }
-
-  // Sets the non-blocking mode of the socket.
-  asio::error_code non_blocking(base_implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    socket_ops::set_user_non_blocking(impl.socket_, impl.state_, mode, ec);
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the native socket implementation.
-  bool native_non_blocking(const base_implementation_type& impl) const
-  {
-    return (impl.state_ & socket_ops::internal_non_blocking) != 0;
-  }
-
-  // Sets the non-blocking mode of the native socket implementation.
-  asio::error_code native_non_blocking(base_implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    socket_ops::set_internal_non_blocking(impl.socket_, impl.state_, mode, ec);
-    return ec;
-  }
-
-  // Wait for the socket to become ready to read, ready to write, or to have
-  // pending error conditions.
-  asio::error_code wait(base_implementation_type& impl,
-      socket_base::wait_type w, asio::error_code& ec)
-  {
-    switch (w)
-    {
-    case socket_base::wait_read:
-      socket_ops::poll_read(impl.socket_, impl.state_, -1, ec);
-      break;
-    case socket_base::wait_write:
-      socket_ops::poll_write(impl.socket_, impl.state_, -1, ec);
-      break;
-    case socket_base::wait_error:
-      socket_ops::poll_error(impl.socket_, impl.state_, -1, ec);
-      break;
-    default:
-      ec = asio::error::invalid_argument;
-      break;
-    }
-
-    return ec;
-  }
-
-  // Asynchronously wait for the socket to become ready to read, ready to
-  // write, or to have pending error conditions.
-  template <typename Handler>
-  void async_wait(base_implementation_type& impl,
-      socket_base::wait_type w, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_wait_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_wait"));
-
-    int op_type;
-    switch (w)
-    {
-      case socket_base::wait_read:
-        op_type = reactor::read_op;
-        break;
-      case socket_base::wait_write:
-        op_type = reactor::write_op;
-        break;
-      case socket_base::wait_error:
-        op_type = reactor::except_op;
-        break;
-      default:
-        p.p->ec_ = asio::error::invalid_argument;
-        reactor_.post_immediate_completion(p.p, is_continuation);
-        p.v = p.p = 0;
-        return;
-    }
-
-    start_op(impl, op_type, p.p, is_continuation, false, false);
-    p.v = p.p = 0;
-  }
-
-  // Send the given data to the peer.
-  template <typename ConstBufferSequence>
-  size_t send(base_implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(buffers);
-
-    return socket_ops::sync_send(impl.socket_, impl.state_,
-        bufs.buffers(), bufs.count(), flags, bufs.all_empty(), ec);
-  }
-
-  // Wait until data can be sent without blocking.
-  size_t send(base_implementation_type& impl, const null_buffers&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_write(impl.socket_, impl.state_, -1, ec);
-
-    return 0;
-  }
-
-  // Start an asynchronous send. The data being sent must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_send(base_implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_socket_send_op<ConstBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.socket_, impl.state_, buffers, flags, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_send"));
-
-    start_op(impl, reactor::write_op, p.p, is_continuation, true,
-        ((impl.state_ & socket_ops::stream_oriented)
-          && buffer_sequence_adapter<asio::const_buffer,
-            ConstBufferSequence>::all_empty(buffers)));
-    p.v = p.p = 0;
-  }
-
-  // Start an asynchronous wait until data can be sent without blocking.
-  template <typename Handler>
-  void async_send(base_implementation_type& impl, const null_buffers&,
-      socket_base::message_flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_send(null_buffers)"));
-
-    start_op(impl, reactor::write_op, p.p, is_continuation, false, false);
-    p.v = p.p = 0;
-  }
-
-  // Receive some data from the peer. Returns the number of bytes received.
-  template <typename MutableBufferSequence>
-  size_t receive(base_implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    return socket_ops::sync_recv(impl.socket_, impl.state_,
-        bufs.buffers(), bufs.count(), flags, bufs.all_empty(), ec);
-  }
-
-  // Wait until data can be received without blocking.
-  size_t receive(base_implementation_type& impl, const null_buffers&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_read(impl.socket_, impl.state_, -1, ec);
-
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received
-  // must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive(base_implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_socket_recv_op<MutableBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.socket_, impl.state_, buffers, flags, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_receive"));
-
-    start_op(impl,
-        (flags & socket_base::message_out_of_band)
-          ? reactor::except_op : reactor::read_op,
-        p.p, is_continuation,
-        (flags & socket_base::message_out_of_band) == 0,
-        ((impl.state_ & socket_ops::stream_oriented)
-          && buffer_sequence_adapter<asio::mutable_buffer,
-            MutableBufferSequence>::all_empty(buffers)));
-    p.v = p.p = 0;
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive(base_implementation_type& impl, const null_buffers&,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_receive(null_buffers)"));
-
-    start_op(impl,
-        (flags & socket_base::message_out_of_band)
-          ? reactor::except_op : reactor::read_op,
-        p.p, is_continuation, false, false);
-    p.v = p.p = 0;
-  }
-
-  // Receive some data with associated flags. Returns the number of bytes
-  // received.
-  template <typename MutableBufferSequence>
-  size_t receive_with_flags(base_implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    return socket_ops::sync_recvmsg(impl.socket_, impl.state_,
-        bufs.buffers(), bufs.count(), in_flags, out_flags, ec);
-  }
-
-  // Wait until data can be received without blocking.
-  size_t receive_with_flags(base_implementation_type& impl,
-      const null_buffers&, socket_base::message_flags,
-      socket_base::message_flags& out_flags, asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_read(impl.socket_, impl.state_, -1, ec);
-
-    // Clear out_flags, since we cannot give it any other sensible value when
-    // performing a null_buffers operation.
-    out_flags = 0;
-
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received
-  // must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive_with_flags(base_implementation_type& impl,
-      const MutableBufferSequence& buffers, socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_socket_recvmsg_op<MutableBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.socket_, buffers, in_flags, out_flags, handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_receive_with_flags"));
-
-    start_op(impl,
-        (in_flags & socket_base::message_out_of_band)
-          ? reactor::except_op : reactor::read_op,
-        p.p, is_continuation,
-        (in_flags & socket_base::message_out_of_band) == 0, false);
-    p.v = p.p = 0;
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive_with_flags(base_implementation_type& impl,
-      const null_buffers&, socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef reactive_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((reactor_.context(), *p.p, "socket",
-          &impl, impl.socket_, "async_receive_with_flags(null_buffers)"));
-
-    // Clear out_flags, since we cannot give it any other sensible value when
-    // performing a null_buffers operation.
-    out_flags = 0;
-
-    start_op(impl,
-        (in_flags & socket_base::message_out_of_band)
-          ? reactor::except_op : reactor::read_op,
-        p.p, is_continuation, false, false);
-    p.v = p.p = 0;
-  }
-
-protected:
-  // Open a new socket implementation.
-  ASIO_DECL asio::error_code do_open(
-      base_implementation_type& impl, int af,
-      int type, int protocol, asio::error_code& ec);
-
-  // Assign a native socket to a socket implementation.
-  ASIO_DECL asio::error_code do_assign(
-      base_implementation_type& impl, int type,
-      const native_handle_type& native_socket, asio::error_code& ec);
-
-  // Start the asynchronous read or write operation.
-  ASIO_DECL void start_op(base_implementation_type& impl, int op_type,
-      reactor_op* op, bool is_continuation, bool is_non_blocking, bool noop);
-
-  // Start the asynchronous accept operation.
-  ASIO_DECL void start_accept_op(base_implementation_type& impl,
-      reactor_op* op, bool is_continuation, bool peer_is_open);
-
-  // Start the asynchronous connect operation.
-  ASIO_DECL void start_connect_op(base_implementation_type& impl,
-      reactor_op* op, bool is_continuation,
-      const socket_addr_type* addr, size_t addrlen);
-
-  // The io_context that owns this socket service.
-  io_context& io_context_;
-
-  // The selector that performs event demultiplexing for the service.
-  reactor& reactor_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/reactive_socket_service_base.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // !defined(ASIO_HAS_IOCP)
-       //   && !defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_REACTIVE_SOCKET_SERVICE_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactive_wait_op.hpp b/tools/sdk/include/asio/asio/detail/reactive_wait_op.hpp
deleted file mode 100644
index 616d8b11504..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactive_wait_op.hpp
+++ /dev/null
@@ -1,90 +0,0 @@
-//
-// detail/reactive_wait_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTIVE_WAIT_OP_HPP
-#define ASIO_DETAIL_REACTIVE_WAIT_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class reactive_wait_op : public reactor_op
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(reactive_wait_op);
-
-  reactive_wait_op(Handler& handler)
-    : reactor_op(&reactive_wait_op::do_perform,
-        &reactive_wait_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static status do_perform(reactor_op*)
-  {
-    return done;
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    reactive_wait_op* o(static_cast<reactive_wait_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder1<Handler, asio::error_code>
-      handler(o->handler_, o->ec_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTIVE_WAIT_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactor.hpp b/tools/sdk/include/asio/asio/detail/reactor.hpp
deleted file mode 100644
index 47502764f05..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactor.hpp
+++ /dev/null
@@ -1,32 +0,0 @@
-//
-// detail/reactor.hpp
-// ~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTOR_HPP
-#define ASIO_DETAIL_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/reactor_fwd.hpp"
-
-#if defined(ASIO_HAS_EPOLL)
-# include "asio/detail/epoll_reactor.hpp"
-#elif defined(ASIO_HAS_KQUEUE)
-# include "asio/detail/kqueue_reactor.hpp"
-#elif defined(ASIO_HAS_DEV_POLL)
-# include "asio/detail/dev_poll_reactor.hpp"
-#elif defined(ASIO_HAS_IOCP) || defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/null_reactor.hpp"
-#else
-# include "asio/detail/select_reactor.hpp"
-#endif
-
-#endif // ASIO_DETAIL_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactor_fwd.hpp b/tools/sdk/include/asio/asio/detail/reactor_fwd.hpp
deleted file mode 100644
index a4555c3db00..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactor_fwd.hpp
+++ /dev/null
@@ -1,40 +0,0 @@
-//
-// detail/reactor_fwd.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTOR_FWD_HPP
-#define ASIO_DETAIL_REACTOR_FWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_HAS_IOCP) || defined(ASIO_WINDOWS_RUNTIME)
-typedef class null_reactor reactor;
-#elif defined(ASIO_HAS_IOCP)
-typedef class select_reactor reactor;
-#elif defined(ASIO_HAS_EPOLL)
-typedef class epoll_reactor reactor;
-#elif defined(ASIO_HAS_KQUEUE)
-typedef class kqueue_reactor reactor;
-#elif defined(ASIO_HAS_DEV_POLL)
-typedef class dev_poll_reactor reactor;
-#else
-typedef class select_reactor reactor;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_REACTOR_FWD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactor_op.hpp b/tools/sdk/include/asio/asio/detail/reactor_op.hpp
deleted file mode 100644
index faad1a775cc..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactor_op.hpp
+++ /dev/null
@@ -1,65 +0,0 @@
-//
-// detail/reactor_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTOR_OP_HPP
-#define ASIO_DETAIL_REACTOR_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class reactor_op
-  : public operation
-{
-public:
-  // The error code to be passed to the completion handler.
-  asio::error_code ec_;
-
-  // The number of bytes transferred, to be passed to the completion handler.
-  std::size_t bytes_transferred_;
-
-  // Status returned by perform function. May be used to decide whether it is
-  // worth performing more operations on the descriptor immediately.
-  enum status { not_done, done, done_and_exhausted };
-
-  // Perform the operation. Returns true if it is finished.
-  status perform()
-  {
-    return perform_func_(this);
-  }
-
-protected:
-  typedef status (*perform_func_type)(reactor_op*);
-
-  reactor_op(perform_func_type perform_func, func_type complete_func)
-    : operation(complete_func),
-      bytes_transferred_(0),
-      perform_func_(perform_func)
-  {
-  }
-
-private:
-  perform_func_type perform_func_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTOR_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/reactor_op_queue.hpp b/tools/sdk/include/asio/asio/detail/reactor_op_queue.hpp
deleted file mode 100644
index 898f31d1c6c..00000000000
--- a/tools/sdk/include/asio/asio/detail/reactor_op_queue.hpp
+++ /dev/null
@@ -1,168 +0,0 @@
-//
-// detail/reactor_op_queue.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REACTOR_OP_QUEUE_HPP
-#define ASIO_DETAIL_REACTOR_OP_QUEUE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/hash_map.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Descriptor>
-class reactor_op_queue
-  : private noncopyable
-{
-public:
-  typedef Descriptor key_type;
-
-  struct mapped_type : op_queue<reactor_op>
-  {
-    mapped_type() {}
-    mapped_type(const mapped_type&) {}
-    void operator=(const mapped_type&) {}
-  };
-
-  typedef typename hash_map<key_type, mapped_type>::value_type value_type;
-  typedef typename hash_map<key_type, mapped_type>::iterator iterator;
-
-  // Constructor.
-  reactor_op_queue()
-    : operations_()
-  {
-  }
-
-  // Obtain iterators to all registered descriptors.
-  iterator begin() { return operations_.begin(); }
-  iterator end() { return operations_.end(); }
-
-  // Add a new operation to the queue. Returns true if this is the only
-  // operation for the given descriptor, in which case the reactor's event
-  // demultiplexing function call may need to be interrupted and restarted.
-  bool enqueue_operation(Descriptor descriptor, reactor_op* op)
-  {
-    std::pair<iterator, bool> entry =
-      operations_.insert(value_type(descriptor, mapped_type()));
-    entry.first->second.push(op);
-    return entry.second;
-  }
-
-  // Cancel all operations associated with the descriptor identified by the
-  // supplied iterator. Any operations pending for the descriptor will be
-  // cancelled. Returns true if any operations were cancelled, in which case
-  // the reactor's event demultiplexing function may need to be interrupted and
-  // restarted.
-  bool cancel_operations(iterator i, op_queue<operation>& ops,
-      const asio::error_code& ec =
-        asio::error::operation_aborted)
-  {
-    if (i != operations_.end())
-    {
-      while (reactor_op* op = i->second.front())
-      {
-        op->ec_ = ec;
-        i->second.pop();
-        ops.push(op);
-      }
-      operations_.erase(i);
-      return true;
-    }
-
-    return false;
-  }
-
-  // Cancel all operations associated with the descriptor. Any operations
-  // pending for the descriptor will be cancelled. Returns true if any
-  // operations were cancelled, in which case the reactor's event
-  // demultiplexing function may need to be interrupted and restarted.
-  bool cancel_operations(Descriptor descriptor, op_queue<operation>& ops,
-      const asio::error_code& ec =
-        asio::error::operation_aborted)
-  {
-    return this->cancel_operations(operations_.find(descriptor), ops, ec);
-  }
-
-  // Whether there are no operations in the queue.
-  bool empty() const
-  {
-    return operations_.empty();
-  }
-
-  // Determine whether there are any operations associated with the descriptor.
-  bool has_operation(Descriptor descriptor) const
-  {
-    return operations_.find(descriptor) != operations_.end();
-  }
-
-  // Perform the operations corresponding to the descriptor identified by the
-  // supplied iterator. Returns true if there are still unfinished operations
-  // queued for the descriptor.
-  bool perform_operations(iterator i, op_queue<operation>& ops)
-  {
-    if (i != operations_.end())
-    {
-      while (reactor_op* op = i->second.front())
-      {
-        if (op->perform())
-        {
-          i->second.pop();
-          ops.push(op);
-        }
-        else
-        {
-          return true;
-        }
-      }
-      operations_.erase(i);
-    }
-    return false;
-  }
-
-  // Perform the operations corresponding to the descriptor. Returns true if
-  // there are still unfinished operations queued for the descriptor.
-  bool perform_operations(Descriptor descriptor, op_queue<operation>& ops)
-  {
-    return this->perform_operations(operations_.find(descriptor), ops);
-  }
-
-  // Get all operations owned by the queue.
-  void get_all_operations(op_queue<operation>& ops)
-  {
-    iterator i = operations_.begin();
-    while (i != operations_.end())
-    {
-      iterator op_iter = i++;
-      ops.push(op_iter->second);
-      operations_.erase(op_iter);
-    }
-  }
-
-private:
-  // The operations that are currently executing asynchronously.
-  hash_map<key_type, mapped_type> operations_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_REACTOR_OP_QUEUE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/recycling_allocator.hpp b/tools/sdk/include/asio/asio/detail/recycling_allocator.hpp
deleted file mode 100644
index 964af1da6f1..00000000000
--- a/tools/sdk/include/asio/asio/detail/recycling_allocator.hpp
+++ /dev/null
@@ -1,104 +0,0 @@
-//
-// detail/recycling_allocator.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_RECYCLING_ALLOCATOR_HPP
-#define ASIO_DETAIL_RECYCLING_ALLOCATOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/thread_context.hpp"
-#include "asio/detail/thread_info_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-class recycling_allocator
-{
-public:
-  typedef T value_type;
-
-  template <typename U>
-  struct rebind
-  {
-    typedef recycling_allocator<U> other;
-  };
-
-  recycling_allocator()
-  {
-  }
-
-  template <typename U>
-  recycling_allocator(const recycling_allocator<U>&)
-  {
-  }
-
-  T* allocate(std::size_t n)
-  {
-    typedef thread_context::thread_call_stack call_stack;
-    void* p = thread_info_base::allocate(call_stack::top(), sizeof(T) * n);
-    return static_cast<T*>(p);
-  }
-
-  void deallocate(T* p, std::size_t n)
-  {
-    typedef thread_context::thread_call_stack call_stack;
-    thread_info_base::deallocate(call_stack::top(), p, sizeof(T) * n);
-  }
-};
-
-template <>
-class recycling_allocator<void>
-{
-public:
-  typedef void value_type;
-
-  template <typename U>
-  struct rebind
-  {
-    typedef recycling_allocator<U> other;
-  };
-
-  recycling_allocator()
-  {
-  }
-
-  template <typename U>
-  recycling_allocator(const recycling_allocator<U>&)
-  {
-  }
-};
-
-template <typename Allocator>
-struct get_recycling_allocator
-{
-  typedef Allocator type;
-  static type get(const Allocator& a) { return a; }
-};
-
-template <typename T>
-struct get_recycling_allocator<std::allocator<T> >
-{
-  typedef recycling_allocator<T> type;
-  static type get(const std::allocator<T>&) { return type(); }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_RECYCLING_ALLOCATOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/regex_fwd.hpp b/tools/sdk/include/asio/asio/detail/regex_fwd.hpp
deleted file mode 100644
index dcf7d06e3c7..00000000000
--- a/tools/sdk/include/asio/asio/detail/regex_fwd.hpp
+++ /dev/null
@@ -1,35 +0,0 @@
-//
-// detail/regex_fwd.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_REGEX_FWD_HPP
-#define ASIO_DETAIL_REGEX_FWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#if defined(ASIO_HAS_BOOST_REGEX)
-
-#include <boost/regex_fwd.hpp>
-#include <boost/regex/v4/match_flags.hpp>
-
-namespace boost {
-
-template <class BidiIterator>
-struct sub_match;
-
-template <class BidiIterator, class Allocator>
-class match_results;
-
-} // namespace boost
-
-#endif // defined(ASIO_HAS_BOOST_REGEX)
-
-#endif // ASIO_DETAIL_REGEX_FWD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/resolve_endpoint_op.hpp b/tools/sdk/include/asio/asio/detail/resolve_endpoint_op.hpp
deleted file mode 100644
index 8eee2f98bf4..00000000000
--- a/tools/sdk/include/asio/asio/detail/resolve_endpoint_op.hpp
+++ /dev/null
@@ -1,122 +0,0 @@
-//
-// detail/resolve_endpoint_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_RESOLVER_ENDPOINT_OP_HPP
-#define ASIO_DETAIL_RESOLVER_ENDPOINT_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/ip/basic_resolver_results.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/resolve_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Protocol, typename Handler>
-class resolve_endpoint_op : public resolve_op
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(resolve_endpoint_op);
-
-  typedef typename Protocol::endpoint endpoint_type;
-  typedef asio::ip::basic_resolver_results<Protocol> results_type;
-
-  resolve_endpoint_op(socket_ops::weak_cancel_token_type cancel_token,
-      const endpoint_type& endpoint, io_context_impl& ioc, Handler& handler)
-    : resolve_op(&resolve_endpoint_op::do_complete),
-      cancel_token_(cancel_token),
-      endpoint_(endpoint),
-      io_context_impl_(ioc),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the operation object.
-    resolve_endpoint_op* o(static_cast<resolve_endpoint_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    if (owner && owner != &o->io_context_impl_)
-    {
-      // The operation is being run on the worker io_context. Time to perform
-      // the resolver operation.
-    
-      // Perform the blocking endpoint resolution operation.
-      char host_name[NI_MAXHOST];
-      char service_name[NI_MAXSERV];
-      socket_ops::background_getnameinfo(o->cancel_token_, o->endpoint_.data(),
-          o->endpoint_.size(), host_name, NI_MAXHOST, service_name, NI_MAXSERV,
-          o->endpoint_.protocol().type(), o->ec_);
-      o->results_ = results_type::create(o->endpoint_, host_name, service_name);
-
-      // Pass operation back to main io_context for completion.
-      o->io_context_impl_.post_deferred_completion(o);
-      p.v = p.p = 0;
-    }
-    else
-    {
-      // The operation has been returned to the main io_context. The completion
-      // handler is ready to be delivered.
-
-      ASIO_HANDLER_COMPLETION((*o));
-
-      // Make a copy of the handler so that the memory can be deallocated
-      // before the upcall is made. Even if we're not about to make an upcall,
-      // a sub-object of the handler may be the true owner of the memory
-      // associated with the handler. Consequently, a local copy of the handler
-      // is required to ensure that any owning sub-object remains valid until
-      // after we have deallocated the memory here.
-      detail::binder2<Handler, asio::error_code, results_type>
-        handler(o->handler_, o->ec_, o->results_);
-      p.h = asio::detail::addressof(handler.handler_);
-      p.reset();
-
-      if (owner)
-      {
-        fenced_block b(fenced_block::half);
-        ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, "..."));
-        w.complete(handler, handler.handler_);
-        ASIO_HANDLER_INVOCATION_END;
-      }
-    }
-  }
-
-private:
-  socket_ops::weak_cancel_token_type cancel_token_;
-  endpoint_type endpoint_;
-  io_context_impl& io_context_impl_;
-  Handler handler_;
-  results_type results_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_RESOLVER_ENDPOINT_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/resolve_op.hpp b/tools/sdk/include/asio/asio/detail/resolve_op.hpp
deleted file mode 100644
index a528aa825f3..00000000000
--- a/tools/sdk/include/asio/asio/detail/resolve_op.hpp
+++ /dev/null
@@ -1,45 +0,0 @@
-//
-// detail/resolve_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_RESOLVE_OP_HPP
-#define ASIO_DETAIL_RESOLVE_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/error.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class resolve_op : public operation
-{
-public:
-  // The error code to be passed to the completion handler.
-  asio::error_code ec_;
-
-protected:
-  resolve_op(func_type complete_func)
-    : operation(complete_func)
-  {
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_RESOLVE_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/resolve_query_op.hpp b/tools/sdk/include/asio/asio/detail/resolve_query_op.hpp
deleted file mode 100644
index 0ec5a32101c..00000000000
--- a/tools/sdk/include/asio/asio/detail/resolve_query_op.hpp
+++ /dev/null
@@ -1,134 +0,0 @@
-//
-// detail/resolve_query_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_RESOLVE_QUERY_OP_HPP
-#define ASIO_DETAIL_RESOLVE_QUERY_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/ip/basic_resolver_query.hpp"
-#include "asio/ip/basic_resolver_results.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/resolve_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Protocol, typename Handler>
-class resolve_query_op : public resolve_op
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(resolve_query_op);
-
-  typedef asio::ip::basic_resolver_query<Protocol> query_type;
-  typedef asio::ip::basic_resolver_results<Protocol> results_type;
-
-  resolve_query_op(socket_ops::weak_cancel_token_type cancel_token,
-      const query_type& query, io_context_impl& ioc, Handler& handler)
-    : resolve_op(&resolve_query_op::do_complete),
-      cancel_token_(cancel_token),
-      query_(query),
-      io_context_impl_(ioc),
-      handler_(ASIO_MOVE_CAST(Handler)(handler)),
-      addrinfo_(0)
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  ~resolve_query_op()
-  {
-    if (addrinfo_)
-      socket_ops::freeaddrinfo(addrinfo_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the operation object.
-    resolve_query_op* o(static_cast<resolve_query_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-
-    if (owner && owner != &o->io_context_impl_)
-    {
-      // The operation is being run on the worker io_context. Time to perform
-      // the resolver operation.
-    
-      // Perform the blocking host resolution operation.
-      socket_ops::background_getaddrinfo(o->cancel_token_,
-          o->query_.host_name().c_str(), o->query_.service_name().c_str(),
-          o->query_.hints(), &o->addrinfo_, o->ec_);
-
-      // Pass operation back to main io_context for completion.
-      o->io_context_impl_.post_deferred_completion(o);
-      p.v = p.p = 0;
-    }
-    else
-    {
-      // The operation has been returned to the main io_context. The completion
-      // handler is ready to be delivered.
-
-      // Take ownership of the operation's outstanding work.
-      handler_work<Handler> w(o->handler_);
-
-      ASIO_HANDLER_COMPLETION((*o));
-
-      // Make a copy of the handler so that the memory can be deallocated
-      // before the upcall is made. Even if we're not about to make an upcall,
-      // a sub-object of the handler may be the true owner of the memory
-      // associated with the handler. Consequently, a local copy of the handler
-      // is required to ensure that any owning sub-object remains valid until
-      // after we have deallocated the memory here.
-      detail::binder2<Handler, asio::error_code, results_type>
-        handler(o->handler_, o->ec_, results_type());
-      p.h = asio::detail::addressof(handler.handler_);
-      if (o->addrinfo_)
-      {
-        handler.arg2_ = results_type::create(o->addrinfo_,
-            o->query_.host_name(), o->query_.service_name());
-      }
-      p.reset();
-
-      if (owner)
-      {
-        fenced_block b(fenced_block::half);
-        ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, "..."));
-        w.complete(handler, handler.handler_);
-        ASIO_HANDLER_INVOCATION_END;
-      }
-    }
-  }
-
-private:
-  socket_ops::weak_cancel_token_type cancel_token_;
-  query_type query_;
-  io_context_impl& io_context_impl_;
-  Handler handler_;
-  asio::detail::addrinfo_type* addrinfo_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_RESOLVE_QUERY_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/resolver_service.hpp b/tools/sdk/include/asio/asio/detail/resolver_service.hpp
deleted file mode 100644
index 11a94d1353d..00000000000
--- a/tools/sdk/include/asio/asio/detail/resolver_service.hpp
+++ /dev/null
@@ -1,145 +0,0 @@
-//
-// detail/resolver_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_RESOLVER_SERVICE_HPP
-#define ASIO_DETAIL_RESOLVER_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/ip/basic_resolver_query.hpp"
-#include "asio/ip/basic_resolver_results.hpp"
-#include "asio/detail/concurrency_hint.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/resolve_endpoint_op.hpp"
-#include "asio/detail/resolve_query_op.hpp"
-#include "asio/detail/resolver_service_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Protocol>
-class resolver_service :
-  public service_base<resolver_service<Protocol> >,
-  public resolver_service_base
-{
-public:
-  // The implementation type of the resolver. A cancellation token is used to
-  // indicate to the background thread that the operation has been cancelled.
-  typedef socket_ops::shared_cancel_token_type implementation_type;
-
-  // The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  // The query type.
-  typedef asio::ip::basic_resolver_query<Protocol> query_type;
-
-  // The results type.
-  typedef asio::ip::basic_resolver_results<Protocol> results_type;
-
-  // Constructor.
-  resolver_service(asio::io_context& io_context)
-    : service_base<resolver_service<Protocol> >(io_context),
-      resolver_service_base(io_context)
-  {
-  }
-
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    this->base_shutdown();
-  }
-
-  // Perform any fork-related housekeeping.
-  void notify_fork(asio::io_context::fork_event fork_ev)
-  {
-    this->base_notify_fork(fork_ev);
-  }
-
-  // Resolve a query to a list of entries.
-  results_type resolve(implementation_type&, const query_type& query,
-      asio::error_code& ec)
-  {
-    asio::detail::addrinfo_type* address_info = 0;
-
-    socket_ops::getaddrinfo(query.host_name().c_str(),
-        query.service_name().c_str(), query.hints(), &address_info, ec);
-    auto_addrinfo auto_address_info(address_info);
-
-    return ec ? results_type() : results_type::create(
-        address_info, query.host_name(), query.service_name());
-  }
-
-  // Asynchronously resolve a query to a list of entries.
-  template <typename Handler>
-  void async_resolve(implementation_type& impl,
-      const query_type& query, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef resolve_query_op<Protocol, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl, query, io_context_impl_, handler);
-
-    ASIO_HANDLER_CREATION((io_context_impl_.context(),
-          *p.p, "resolver", &impl, 0, "async_resolve"));
-
-    start_resolve_op(p.p);
-    p.v = p.p = 0;
-  }
-
-  // Resolve an endpoint to a list of entries.
-  results_type resolve(implementation_type&,
-      const endpoint_type& endpoint, asio::error_code& ec)
-  {
-    char host_name[NI_MAXHOST];
-    char service_name[NI_MAXSERV];
-    socket_ops::sync_getnameinfo(endpoint.data(), endpoint.size(),
-        host_name, NI_MAXHOST, service_name, NI_MAXSERV,
-        endpoint.protocol().type(), ec);
-
-    return ec ? results_type() : results_type::create(
-        endpoint, host_name, service_name);
-  }
-
-  // Asynchronously resolve an endpoint to a list of entries.
-  template <typename Handler>
-  void async_resolve(implementation_type& impl,
-      const endpoint_type& endpoint, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef resolve_endpoint_op<Protocol, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl, endpoint, io_context_impl_, handler);
-
-    ASIO_HANDLER_CREATION((io_context_impl_.context(),
-          *p.p, "resolver", &impl, 0, "async_resolve"));
-
-    start_resolve_op(p.p);
-    p.v = p.p = 0;
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_RESOLVER_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/resolver_service_base.hpp b/tools/sdk/include/asio/asio/detail/resolver_service_base.hpp
deleted file mode 100644
index 10a792241c5..00000000000
--- a/tools/sdk/include/asio/asio/detail/resolver_service_base.hpp
+++ /dev/null
@@ -1,140 +0,0 @@
-//
-// detail/resolver_service_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_RESOLVER_SERVICE_BASE_HPP
-#define ASIO_DETAIL_RESOLVER_SERVICE_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/error.hpp"
-#include "asio/executor_work_guard.hpp"
-#include "asio/io_context.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/resolve_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/scoped_ptr.hpp"
-#include "asio/detail/thread.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class resolver_service_base
-{
-public:
-  // The implementation type of the resolver. A cancellation token is used to
-  // indicate to the background thread that the operation has been cancelled.
-  typedef socket_ops::shared_cancel_token_type implementation_type;
-
-  // Constructor.
-  ASIO_DECL resolver_service_base(asio::io_context& io_context);
-
-  // Destructor.
-  ASIO_DECL ~resolver_service_base();
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void base_shutdown();
-
-  // Perform any fork-related housekeeping.
-  ASIO_DECL void base_notify_fork(
-      asio::io_context::fork_event fork_ev);
-
-  // Construct a new resolver implementation.
-  ASIO_DECL void construct(implementation_type& impl);
-
-  // Destroy a resolver implementation.
-  ASIO_DECL void destroy(implementation_type&);
-
-  // Move-construct a new resolver implementation.
-  ASIO_DECL void move_construct(implementation_type& impl,
-      implementation_type& other_impl);
-
-  // Move-assign from another resolver implementation.
-  ASIO_DECL void move_assign(implementation_type& impl,
-      resolver_service_base& other_service,
-      implementation_type& other_impl);
-
-  // Cancel pending asynchronous operations.
-  ASIO_DECL void cancel(implementation_type& impl);
-
-protected:
-  // Helper function to start an asynchronous resolve operation.
-  ASIO_DECL void start_resolve_op(resolve_op* op);
-
-#if !defined(ASIO_WINDOWS_RUNTIME)
-  // Helper class to perform exception-safe cleanup of addrinfo objects.
-  class auto_addrinfo
-    : private asio::detail::noncopyable
-  {
-  public:
-    explicit auto_addrinfo(asio::detail::addrinfo_type* ai)
-      : ai_(ai)
-    {
-    }
-
-    ~auto_addrinfo()
-    {
-      if (ai_)
-        socket_ops::freeaddrinfo(ai_);
-    }
-
-    operator asio::detail::addrinfo_type*()
-    {
-      return ai_;
-    }
-
-  private:
-    asio::detail::addrinfo_type* ai_;
-  };
-#endif // !defined(ASIO_WINDOWS_RUNTIME)
-
-  // Helper class to run the work io_context in a thread.
-  class work_io_context_runner;
-
-  // Start the work thread if it's not already running.
-  ASIO_DECL void start_work_thread();
-
-  // The io_context implementation used to post completions.
-  io_context_impl& io_context_impl_;
-
-private:
-  // Mutex to protect access to internal data.
-  asio::detail::mutex mutex_;
-
-  // Private io_context used for performing asynchronous host resolution.
-  asio::detail::scoped_ptr<asio::io_context> work_io_context_;
-
-  // The work io_context implementation used to post completions.
-  io_context_impl& work_io_context_impl_;
-
-  // Work for the private io_context to perform.
-  asio::executor_work_guard<
-      asio::io_context::executor_type> work_;
-
-  // Thread used for running the work io_context's run loop.
-  asio::detail::scoped_ptr<asio::detail::thread> work_thread_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/resolver_service_base.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_RESOLVER_SERVICE_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/scheduler.hpp b/tools/sdk/include/asio/asio/detail/scheduler.hpp
deleted file mode 100644
index 10c29b7edf2..00000000000
--- a/tools/sdk/include/asio/asio/detail/scheduler.hpp
+++ /dev/null
@@ -1,213 +0,0 @@
-//
-// detail/scheduler.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SCHEDULER_HPP
-#define ASIO_DETAIL_SCHEDULER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/error_code.hpp"
-#include "asio/execution_context.hpp"
-#include "asio/detail/atomic_count.hpp"
-#include "asio/detail/conditionally_enabled_event.hpp"
-#include "asio/detail/conditionally_enabled_mutex.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/reactor_fwd.hpp"
-#include "asio/detail/scheduler_operation.hpp"
-#include "asio/detail/thread_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-struct scheduler_thread_info;
-
-class scheduler
-  : public execution_context_service_base<scheduler>,
-    public thread_context
-{
-public:
-  typedef scheduler_operation operation;
-
-  // Constructor. Specifies the number of concurrent threads that are likely to
-  // run the scheduler. If set to 1 certain optimisation are performed.
-  ASIO_DECL scheduler(asio::execution_context& ctx,
-      int concurrency_hint = 0);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Initialise the task, if required.
-  ASIO_DECL void init_task();
-
-  // Run the event loop until interrupted or no more work.
-  ASIO_DECL std::size_t run(asio::error_code& ec);
-
-  // Run until interrupted or one operation is performed.
-  ASIO_DECL std::size_t run_one(asio::error_code& ec);
-
-  // Run until timeout, interrupted, or one operation is performed.
-  ASIO_DECL std::size_t wait_one(
-      long usec, asio::error_code& ec);
-
-  // Poll for operations without blocking.
-  ASIO_DECL std::size_t poll(asio::error_code& ec);
-
-  // Poll for one operation without blocking.
-  ASIO_DECL std::size_t poll_one(asio::error_code& ec);
-
-  // Interrupt the event processing loop.
-  ASIO_DECL void stop();
-
-  // Determine whether the scheduler is stopped.
-  ASIO_DECL bool stopped() const;
-
-  // Restart in preparation for a subsequent run invocation.
-  ASIO_DECL void restart();
-
-  // Notify that some work has started.
-  void work_started()
-  {
-    ++outstanding_work_;
-  }
-
-  // Used to compensate for a forthcoming work_finished call. Must be called
-  // from within a scheduler-owned thread.
-  ASIO_DECL void compensating_work_started();
-
-  // Notify that some work has finished.
-  void work_finished()
-  {
-    if (--outstanding_work_ == 0)
-      stop();
-  }
-
-  // Return whether a handler can be dispatched immediately.
-  bool can_dispatch()
-  {
-    return thread_call_stack::contains(this) != 0;
-  }
-
-  // Request invocation of the given operation and return immediately. Assumes
-  // that work_started() has not yet been called for the operation.
-  ASIO_DECL void post_immediate_completion(
-      operation* op, bool is_continuation);
-
-  // Request invocation of the given operation and return immediately. Assumes
-  // that work_started() was previously called for the operation.
-  ASIO_DECL void post_deferred_completion(operation* op);
-
-  // Request invocation of the given operations and return immediately. Assumes
-  // that work_started() was previously called for each operation.
-  ASIO_DECL void post_deferred_completions(op_queue<operation>& ops);
-
-  // Enqueue the given operation following a failed attempt to dispatch the
-  // operation for immediate invocation.
-  ASIO_DECL void do_dispatch(operation* op);
-
-  // Process unfinished operations as part of a shutdownoperation. Assumes that
-  // work_started() was previously called for the operations.
-  ASIO_DECL void abandon_operations(op_queue<operation>& ops);
-
-  // Get the concurrency hint that was used to initialise the scheduler.
-  int concurrency_hint() const
-  {
-    return concurrency_hint_;
-  }
-
-private:
-  // The mutex type used by this scheduler.
-  typedef conditionally_enabled_mutex mutex;
-
-  // The event type used by this scheduler.
-  typedef conditionally_enabled_event event;
-
-  // Structure containing thread-specific data.
-  typedef scheduler_thread_info thread_info;
-
-  // Run at most one operation. May block.
-  ASIO_DECL std::size_t do_run_one(mutex::scoped_lock& lock,
-      thread_info& this_thread, const asio::error_code& ec);
-
-  // Run at most one operation with a timeout. May block.
-  ASIO_DECL std::size_t do_wait_one(mutex::scoped_lock& lock,
-      thread_info& this_thread, long usec, const asio::error_code& ec);
-
-  // Poll for at most one operation.
-  ASIO_DECL std::size_t do_poll_one(mutex::scoped_lock& lock,
-      thread_info& this_thread, const asio::error_code& ec);
-
-  // Stop the task and all idle threads.
-  ASIO_DECL void stop_all_threads(mutex::scoped_lock& lock);
-
-  // Wake a single idle thread, or the task, and always unlock the mutex.
-  ASIO_DECL void wake_one_thread_and_unlock(
-      mutex::scoped_lock& lock);
-
-  // Helper class to perform task-related operations on block exit.
-  struct task_cleanup;
-  friend struct task_cleanup;
-
-  // Helper class to call work-related operations on block exit.
-  struct work_cleanup;
-  friend struct work_cleanup;
-
-  // Whether to optimise for single-threaded use cases.
-  const bool one_thread_;
-
-  // Mutex to protect access to internal data.
-  mutable mutex mutex_;
-
-  // Event to wake up blocked threads.
-  event wakeup_event_;
-
-  // The task to be run by this service.
-  reactor* task_;
-
-  // Operation object to represent the position of the task in the queue.
-  struct task_operation : operation
-  {
-    task_operation() : operation(0) {}
-  } task_operation_;
-
-  // Whether the task has been interrupted.
-  bool task_interrupted_;
-
-  // The count of unfinished work.
-  atomic_count outstanding_work_;
-
-  // The queue of handlers that are ready to be delivered.
-  op_queue<operation> op_queue_;
-
-  // Flag to indicate that the dispatcher has been stopped.
-  bool stopped_;
-
-  // Flag to indicate that the dispatcher has been shut down.
-  bool shutdown_;
-
-  // The concurrency hint used to initialise the scheduler.
-  const int concurrency_hint_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/scheduler.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_SCHEDULER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/scheduler_operation.hpp b/tools/sdk/include/asio/asio/detail/scheduler_operation.hpp
deleted file mode 100644
index 1c2ce02ecc7..00000000000
--- a/tools/sdk/include/asio/asio/detail/scheduler_operation.hpp
+++ /dev/null
@@ -1,78 +0,0 @@
-//
-// detail/scheduler_operation.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SCHEDULER_OPERATION_HPP
-#define ASIO_DETAIL_SCHEDULER_OPERATION_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/error_code.hpp"
-#include "asio/detail/handler_tracking.hpp"
-#include "asio/detail/op_queue.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class scheduler;
-
-// Base class for all operations. A function pointer is used instead of virtual
-// functions to avoid the associated overhead.
-class scheduler_operation ASIO_INHERIT_TRACKED_HANDLER
-{
-public:
-  typedef scheduler_operation operation_type;
-
-  void complete(void* owner, const asio::error_code& ec,
-      std::size_t bytes_transferred)
-  {
-    func_(owner, this, ec, bytes_transferred);
-  }
-
-  void destroy()
-  {
-    func_(0, this, asio::error_code(), 0);
-  }
-
-protected:
-  typedef void (*func_type)(void*,
-      scheduler_operation*,
-      const asio::error_code&, std::size_t);
-
-  scheduler_operation(func_type func)
-    : next_(0),
-      func_(func),
-      task_result_(0)
-  {
-  }
-
-  // Prevents deletion through this type.
-  ~scheduler_operation()
-  {
-  }
-
-private:
-  friend class op_queue_access;
-  scheduler_operation* next_;
-  func_type func_;
-protected:
-  friend class scheduler;
-  unsigned int task_result_; // Passed into bytes transferred.
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_SCHEDULER_OPERATION_HPP
diff --git a/tools/sdk/include/asio/asio/detail/scheduler_thread_info.hpp b/tools/sdk/include/asio/asio/detail/scheduler_thread_info.hpp
deleted file mode 100644
index 2ffe013bcb1..00000000000
--- a/tools/sdk/include/asio/asio/detail/scheduler_thread_info.hpp
+++ /dev/null
@@ -1,40 +0,0 @@
-//
-// detail/scheduler_thread_info.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SCHEDULER_THREAD_INFO_HPP
-#define ASIO_DETAIL_SCHEDULER_THREAD_INFO_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/thread_info_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class scheduler;
-class scheduler_operation;
-
-struct scheduler_thread_info : public thread_info_base
-{
-  op_queue<scheduler_operation> private_op_queue;
-  long private_outstanding_work;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_SCHEDULER_THREAD_INFO_HPP
diff --git a/tools/sdk/include/asio/asio/detail/scoped_lock.hpp b/tools/sdk/include/asio/asio/detail/scoped_lock.hpp
deleted file mode 100644
index 6cbce381402..00000000000
--- a/tools/sdk/include/asio/asio/detail/scoped_lock.hpp
+++ /dev/null
@@ -1,101 +0,0 @@
-//
-// detail/scoped_lock.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SCOPED_LOCK_HPP
-#define ASIO_DETAIL_SCOPED_LOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Helper class to lock and unlock a mutex automatically.
-template <typename Mutex>
-class scoped_lock
-  : private noncopyable
-{
-public:
-  // Tag type used to distinguish constructors.
-  enum adopt_lock_t { adopt_lock };
-
-  // Constructor adopts a lock that is already held.
-  scoped_lock(Mutex& m, adopt_lock_t)
-    : mutex_(m),
-      locked_(true)
-  {
-  }
-
-  // Constructor acquires the lock.
-  explicit scoped_lock(Mutex& m)
-    : mutex_(m)
-  {
-    mutex_.lock();
-    locked_ = true;
-  }
-
-  // Destructor releases the lock.
-  ~scoped_lock()
-  {
-    if (locked_)
-      mutex_.unlock();
-  }
-
-  // Explicitly acquire the lock.
-  void lock()
-  {
-    if (!locked_)
-    {
-      mutex_.lock();
-      locked_ = true;
-    }
-  }
-
-  // Explicitly release the lock.
-  void unlock()
-  {
-    if (locked_)
-    {
-      mutex_.unlock();
-      locked_ = false;
-    }
-  }
-
-  // Test whether the lock is held.
-  bool locked() const
-  {
-    return locked_;
-  }
-
-  // Get the underlying mutex.
-  Mutex& mutex()
-  {
-    return mutex_;
-  }
-
-private:
-  // The underlying mutex.
-  Mutex& mutex_;
-
-  // Whether the mutex is currently locked or unlocked.
-  bool locked_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_SCOPED_LOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/scoped_ptr.hpp b/tools/sdk/include/asio/asio/detail/scoped_ptr.hpp
deleted file mode 100644
index 3449c53b72b..00000000000
--- a/tools/sdk/include/asio/asio/detail/scoped_ptr.hpp
+++ /dev/null
@@ -1,87 +0,0 @@
-//
-// detail/scoped_ptr.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SCOPED_PTR_HPP
-#define ASIO_DETAIL_SCOPED_PTR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-class scoped_ptr
-{
-public:
-  // Constructor.
-  explicit scoped_ptr(T* p = 0)
-    : p_(p)
-  {
-  }
-
-  // Destructor.
-  ~scoped_ptr()
-  {
-    delete p_;
-  }
-
-  // Access.
-  T* get()
-  {
-    return p_;
-  }
-
-  // Access.
-  T* operator->()
-  {
-    return p_;
-  }
-
-  // Dereference.
-  T& operator*()
-  {
-    return *p_;
-  }
-
-  // Reset pointer.
-  void reset(T* p = 0)
-  {
-    delete p_;
-    p_ = p;
-  }
-
-  // Release ownership of the pointer.
-  T* release()
-  {
-    T* tmp = p_;
-    p_ = 0;
-    return tmp;
-  }
-
-private:
-  // Disallow copying and assignment.
-  scoped_ptr(const scoped_ptr&);
-  scoped_ptr& operator=(const scoped_ptr&);
-
-  T* p_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_SCOPED_PTR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/select_interrupter.hpp b/tools/sdk/include/asio/asio/detail/select_interrupter.hpp
deleted file mode 100644
index c58327387b6..00000000000
--- a/tools/sdk/include/asio/asio/detail/select_interrupter.hpp
+++ /dev/null
@@ -1,46 +0,0 @@
-//
-// detail/select_interrupter.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SELECT_INTERRUPTER_HPP
-#define ASIO_DETAIL_SELECT_INTERRUPTER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS_RUNTIME)
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__) || defined(__SYMBIAN32__) || defined (ESP_PLATFORM)
-# include "asio/detail/socket_select_interrupter.hpp"
-#elif defined(ASIO_HAS_EVENTFD)
-# include "asio/detail/eventfd_select_interrupter.hpp"
-#else
-# include "asio/detail/pipe_select_interrupter.hpp"
-#endif
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__) || defined(__SYMBIAN32__) || defined (ESP_PLATFORM)
-typedef socket_select_interrupter select_interrupter;
-#elif defined(ASIO_HAS_EVENTFD)
-typedef eventfd_select_interrupter select_interrupter;
-#else
-typedef pipe_select_interrupter select_interrupter;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // !defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_SELECT_INTERRUPTER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/select_reactor.hpp b/tools/sdk/include/asio/asio/detail/select_reactor.hpp
deleted file mode 100644
index 09965492785..00000000000
--- a/tools/sdk/include/asio/asio/detail/select_reactor.hpp
+++ /dev/null
@@ -1,238 +0,0 @@
-//
-// detail/select_reactor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SELECT_REACTOR_HPP
-#define ASIO_DETAIL_SELECT_REACTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP) \
-  || (!defined(ASIO_HAS_DEV_POLL) \
-      && !defined(ASIO_HAS_EPOLL) \
-      && !defined(ASIO_HAS_KQUEUE) \
-      && !defined(ASIO_WINDOWS_RUNTIME))
-
-#include <cstddef>
-#include "asio/detail/fd_set_adapter.hpp"
-#include "asio/detail/limits.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/reactor_op_queue.hpp"
-#include "asio/detail/select_interrupter.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/timer_queue_base.hpp"
-#include "asio/detail/timer_queue_set.hpp"
-#include "asio/detail/wait_op.hpp"
-#include "asio/execution_context.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-# include "asio/detail/thread.hpp"
-#endif // defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class select_reactor
-  : public execution_context_service_base<select_reactor>
-{
-public:
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-  enum op_types { read_op = 0, write_op = 1, except_op = 2,
-    max_select_ops = 3, connect_op = 3, max_ops = 4 };
-#else // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-  enum op_types { read_op = 0, write_op = 1, except_op = 2,
-    max_select_ops = 3, connect_op = 1, max_ops = 3 };
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-  // Per-descriptor data.
-  struct per_descriptor_data
-  {
-  };
-
-  // Constructor.
-  ASIO_DECL select_reactor(asio::execution_context& ctx);
-
-  // Destructor.
-  ASIO_DECL ~select_reactor();
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Recreate internal descriptors following a fork.
-  ASIO_DECL void notify_fork(
-      asio::execution_context::fork_event fork_ev);
-
-  // Initialise the task, but only if the reactor is not in its own thread.
-  ASIO_DECL void init_task();
-
-  // Register a socket with the reactor. Returns 0 on success, system error
-  // code on failure.
-  ASIO_DECL int register_descriptor(socket_type, per_descriptor_data&);
-
-  // Register a descriptor with an associated single operation. Returns 0 on
-  // success, system error code on failure.
-  ASIO_DECL int register_internal_descriptor(
-      int op_type, socket_type descriptor,
-      per_descriptor_data& descriptor_data, reactor_op* op);
-
-  // Post a reactor operation for immediate completion.
-  void post_immediate_completion(reactor_op* op, bool is_continuation)
-  {
-    scheduler_.post_immediate_completion(op, is_continuation);
-  }
-
-  // Start a new operation. The reactor operation will be performed when the
-  // given descriptor is flagged as ready, or an error has occurred.
-  ASIO_DECL void start_op(int op_type, socket_type descriptor,
-      per_descriptor_data&, reactor_op* op, bool is_continuation, bool);
-
-  // Cancel all operations associated with the given descriptor. The
-  // handlers associated with the descriptor will be invoked with the
-  // operation_aborted error.
-  ASIO_DECL void cancel_ops(socket_type descriptor, per_descriptor_data&);
-
-  // Cancel any operations that are running against the descriptor and remove
-  // its registration from the reactor. The reactor resources associated with
-  // the descriptor must be released by calling cleanup_descriptor_data.
-  ASIO_DECL void deregister_descriptor(socket_type descriptor,
-      per_descriptor_data&, bool closing);
-
-  // Remove the descriptor's registration from the reactor. The reactor
-  // resources associated with the descriptor must be released by calling
-  // cleanup_descriptor_data.
-  ASIO_DECL void deregister_internal_descriptor(
-      socket_type descriptor, per_descriptor_data&);
-
-  // Perform any post-deregistration cleanup tasks associated with the
-  // descriptor data.
-  ASIO_DECL void cleanup_descriptor_data(per_descriptor_data&);
-
-  // Move descriptor registration from one descriptor_data object to another.
-  ASIO_DECL void move_descriptor(socket_type descriptor,
-      per_descriptor_data& target_descriptor_data,
-      per_descriptor_data& source_descriptor_data);
-
-  // Add a new timer queue to the reactor.
-  template <typename Time_Traits>
-  void add_timer_queue(timer_queue<Time_Traits>& queue);
-
-  // Remove a timer queue from the reactor.
-  template <typename Time_Traits>
-  void remove_timer_queue(timer_queue<Time_Traits>& queue);
-
-  // Schedule a new operation in the given timer queue to expire at the
-  // specified absolute time.
-  template <typename Time_Traits>
-  void schedule_timer(timer_queue<Time_Traits>& queue,
-      const typename Time_Traits::time_type& time,
-      typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op);
-
-  // Cancel the timer operations associated with the given token. Returns the
-  // number of operations that have been posted or dispatched.
-  template <typename Time_Traits>
-  std::size_t cancel_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& timer,
-      std::size_t max_cancelled = (std::numeric_limits<std::size_t>::max)());
-
-  // Move the timer operations associated with the given timer.
-  template <typename Time_Traits>
-  void move_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& target,
-      typename timer_queue<Time_Traits>::per_timer_data& source);
-
-  // Run select once until interrupted or events are ready to be dispatched.
-  ASIO_DECL void run(long usec, op_queue<operation>& ops);
-
-  // Interrupt the select loop.
-  ASIO_DECL void interrupt();
-
-private:
-#if defined(ASIO_HAS_IOCP)
-  // Run the select loop in the thread.
-  ASIO_DECL void run_thread();
-#endif // defined(ASIO_HAS_IOCP)
-
-  // Helper function to add a new timer queue.
-  ASIO_DECL void do_add_timer_queue(timer_queue_base& queue);
-
-  // Helper function to remove a timer queue.
-  ASIO_DECL void do_remove_timer_queue(timer_queue_base& queue);
-
-  // Get the timeout value for the select call.
-  ASIO_DECL timeval* get_timeout(long usec, timeval& tv);
-
-  // Cancel all operations associated with the given descriptor. This function
-  // does not acquire the select_reactor's mutex.
-  ASIO_DECL void cancel_ops_unlocked(socket_type descriptor,
-      const asio::error_code& ec);
-
-  // The scheduler implementation used to post completions.
-# if defined(ASIO_HAS_IOCP)
-  typedef class win_iocp_io_context scheduler_type;
-# else // defined(ASIO_HAS_IOCP)
-  typedef class scheduler scheduler_type;
-# endif // defined(ASIO_HAS_IOCP)
-  scheduler_type& scheduler_;
-
-  // Mutex to protect access to internal data.
-  asio::detail::mutex mutex_;
-
-  // The interrupter is used to break a blocking select call.
-  select_interrupter interrupter_;
-
-  // The queues of read, write and except operations.
-  reactor_op_queue<socket_type> op_queue_[max_ops];
-
-  // The file descriptor sets to be passed to the select system call.
-  fd_set_adapter fd_sets_[max_select_ops];
-
-  // The timer queues.
-  timer_queue_set timer_queues_;
-
-#if defined(ASIO_HAS_IOCP)
-  // Helper class to run the reactor loop in a thread.
-  class thread_function;
-  friend class thread_function;
-
-  // Does the reactor loop thread need to stop.
-  bool stop_thread_;
-
-  // The thread that is running the reactor loop.
-  asio::detail::thread* thread_;
-#endif // defined(ASIO_HAS_IOCP)
-
-  // Whether the service has been shut down.
-  bool shutdown_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/detail/impl/select_reactor.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/select_reactor.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_IOCP)
-       //   || (!defined(ASIO_HAS_DEV_POLL)
-       //       && !defined(ASIO_HAS_EPOLL)
-       //       && !defined(ASIO_HAS_KQUEUE)
-       //       && !defined(ASIO_WINDOWS_RUNTIME))
-
-#endif // ASIO_DETAIL_SELECT_REACTOR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/service_registry.hpp b/tools/sdk/include/asio/asio/detail/service_registry.hpp
deleted file mode 100644
index cda63072f08..00000000000
--- a/tools/sdk/include/asio/asio/detail/service_registry.hpp
+++ /dev/null
@@ -1,164 +0,0 @@
-//
-// detail/service_registry.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SERVICE_REGISTRY_HPP
-#define ASIO_DETAIL_SERVICE_REGISTRY_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <typeinfo>
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/execution_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-class io_context;
-
-namespace detail {
-
-template <typename T>
-class typeid_wrapper {};
-
-class service_registry
-  : private noncopyable
-{
-public:
-  // Constructor.
-  ASIO_DECL service_registry(execution_context& owner);
-
-  // Destructor.
-  ASIO_DECL ~service_registry();
-
-  // Shutdown all services.
-  ASIO_DECL void shutdown_services();
-
-  // Destroy all services.
-  ASIO_DECL void destroy_services();
-
-  // Notify all services of a fork event.
-  ASIO_DECL void notify_fork(execution_context::fork_event fork_ev);
-
-  // Get the service object corresponding to the specified service type. Will
-  // create a new service object automatically if no such object already
-  // exists. Ownership of the service object is not transferred to the caller.
-  template <typename Service>
-  Service& use_service();
-
-  // Get the service object corresponding to the specified service type. Will
-  // create a new service object automatically if no such object already
-  // exists. Ownership of the service object is not transferred to the caller.
-  // This overload is used for backwards compatibility with services that
-  // inherit from io_context::service.
-  template <typename Service>
-  Service& use_service(io_context& owner);
-
-  // Add a service object. Throws on error, in which case ownership of the
-  // object is retained by the caller.
-  template <typename Service>
-  void add_service(Service* new_service);
-
-  // Check whether a service object of the specified type already exists.
-  template <typename Service>
-  bool has_service() const;
-
-private:
-  // Initalise a service's key when the key_type typedef is not available.
-  template <typename Service>
-  static void init_key(execution_context::service::key& key, ...);
-
-#if !defined(ASIO_NO_TYPEID)
-  // Initalise a service's key when the key_type typedef is available.
-  template <typename Service>
-  static void init_key(execution_context::service::key& key,
-      typename enable_if<
-        is_base_of<typename Service::key_type, Service>::value>::type*);
-#endif // !defined(ASIO_NO_TYPEID)
-
-  // Initialise a service's key based on its id.
-  ASIO_DECL static void init_key_from_id(
-      execution_context::service::key& key,
-      const execution_context::id& id);
-
-#if !defined(ASIO_NO_TYPEID)
-  // Initialise a service's key based on its id.
-  template <typename Service>
-  static void init_key_from_id(execution_context::service::key& key,
-      const service_id<Service>& /*id*/);
-#endif // !defined(ASIO_NO_TYPEID)
-
-  // Check if a service matches the given id.
-  ASIO_DECL static bool keys_match(
-      const execution_context::service::key& key1,
-      const execution_context::service::key& key2);
-
-  // The type of a factory function used for creating a service instance.
-  typedef execution_context::service*(*factory_type)(void*);
-
-  // Factory function for creating a service instance.
-  template <typename Service, typename Owner>
-  static execution_context::service* create(void* owner);
-
-  // Destroy a service instance.
-  ASIO_DECL static void destroy(execution_context::service* service);
-
-  // Helper class to manage service pointers.
-  struct auto_service_ptr;
-  friend struct auto_service_ptr;
-  struct auto_service_ptr
-  {
-    execution_context::service* ptr_;
-    ~auto_service_ptr() { destroy(ptr_); }
-  };
-
-  // Get the service object corresponding to the specified service key. Will
-  // create a new service object automatically if no such object already
-  // exists. Ownership of the service object is not transferred to the caller.
-  ASIO_DECL execution_context::service* do_use_service(
-      const execution_context::service::key& key,
-      factory_type factory, void* owner);
-
-  // Add a service object. Throws on error, in which case ownership of the
-  // object is retained by the caller.
-  ASIO_DECL void do_add_service(
-      const execution_context::service::key& key,
-      execution_context::service* new_service);
-
-  // Check whether a service object with the specified key already exists.
-  ASIO_DECL bool do_has_service(
-      const execution_context::service::key& key) const;
-
-  // Mutex to protect access to internal data.
-  mutable asio::detail::mutex mutex_;
-
-  // The owner of this service registry and the services it contains.
-  execution_context& owner_;
-
-  // The first service in the list of contained services.
-  execution_context::service* first_service_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/detail/impl/service_registry.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/service_registry.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_SERVICE_REGISTRY_HPP
diff --git a/tools/sdk/include/asio/asio/detail/signal_blocker.hpp b/tools/sdk/include/asio/asio/detail/signal_blocker.hpp
deleted file mode 100644
index b684295775f..00000000000
--- a/tools/sdk/include/asio/asio/detail/signal_blocker.hpp
+++ /dev/null
@@ -1,44 +0,0 @@
-//
-// detail/signal_blocker.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SIGNAL_BLOCKER_HPP
-#define ASIO_DETAIL_SIGNAL_BLOCKER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS) || defined(ASIO_WINDOWS) \
-  || defined(ASIO_WINDOWS_RUNTIME) \
-  || defined(__CYGWIN__) || defined(__SYMBIAN32__)
-# include "asio/detail/null_signal_blocker.hpp"
-#elif defined(ASIO_HAS_PTHREADS)
-# include "asio/detail/posix_signal_blocker.hpp"
-#else
-# error Only Windows and POSIX are supported!
-#endif
-
-namespace asio {
-namespace detail {
-
-#if !defined(ASIO_HAS_THREADS) || defined(ASIO_WINDOWS) \
-  || defined(ASIO_WINDOWS_RUNTIME) \
-  || defined(__CYGWIN__) || defined(__SYMBIAN32__)
-typedef null_signal_blocker signal_blocker;
-#elif defined(ASIO_HAS_PTHREADS)
-typedef posix_signal_blocker signal_blocker;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_SIGNAL_BLOCKER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/signal_handler.hpp b/tools/sdk/include/asio/asio/detail/signal_handler.hpp
deleted file mode 100644
index d1c99105a7e..00000000000
--- a/tools/sdk/include/asio/asio/detail/signal_handler.hpp
+++ /dev/null
@@ -1,86 +0,0 @@
-//
-// detail/signal_handler.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SIGNAL_HANDLER_HPP
-#define ASIO_DETAIL_SIGNAL_HANDLER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/handler_work.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/signal_op.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class signal_handler : public signal_op
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(signal_handler);
-
-  signal_handler(Handler& h)
-    : signal_op(&signal_handler::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(h))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    signal_handler* h(static_cast<signal_handler*>(base));
-    ptr p = { asio::detail::addressof(h->handler_), h, h };
-    handler_work<Handler> w(h->handler_);
-
-    ASIO_HANDLER_COMPLETION((*h));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, int>
-      handler(h->handler_, h->ec_, h->signal_number_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_SIGNAL_HANDLER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/signal_init.hpp b/tools/sdk/include/asio/asio/detail/signal_init.hpp
deleted file mode 100644
index 814ff519624..00000000000
--- a/tools/sdk/include/asio/asio/detail/signal_init.hpp
+++ /dev/null
@@ -1,47 +0,0 @@
-//
-// detail/signal_init.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SIGNAL_INIT_HPP
-#define ASIO_DETAIL_SIGNAL_INIT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-#include <csignal>
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <int Signal = SIGPIPE>
-class signal_init
-{
-public:
-  // Constructor.
-  signal_init()
-  {
-    std::signal(Signal, SIG_IGN);
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-#endif // ASIO_DETAIL_SIGNAL_INIT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/signal_op.hpp b/tools/sdk/include/asio/asio/detail/signal_op.hpp
deleted file mode 100644
index c4e364c14e5..00000000000
--- a/tools/sdk/include/asio/asio/detail/signal_op.hpp
+++ /dev/null
@@ -1,49 +0,0 @@
-//
-// detail/signal_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SIGNAL_OP_HPP
-#define ASIO_DETAIL_SIGNAL_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class signal_op
-  : public operation
-{
-public:
-  // The error code to be passed to the completion handler.
-  asio::error_code ec_;
-
-  // The signal number to be passed to the completion handler.
-  int signal_number_;
-
-protected:
-  signal_op(func_type func)
-    : operation(func),
-      signal_number_(0)
-  {
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_SIGNAL_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/signal_set_service.hpp b/tools/sdk/include/asio/asio/detail/signal_set_service.hpp
deleted file mode 100644
index a18ab709356..00000000000
--- a/tools/sdk/include/asio/asio/detail/signal_set_service.hpp
+++ /dev/null
@@ -1,217 +0,0 @@
-//
-// detail/signal_set_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SIGNAL_SET_SERVICE_HPP
-#define ASIO_DETAIL_SIGNAL_SET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <cstddef>
-#include <signal.h>
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/signal_handler.hpp"
-#include "asio/detail/signal_op.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#if !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-# include "asio/detail/reactor.hpp"
-#endif // !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-#if defined(NSIG) && (NSIG > 0)
-enum { max_signal_number = NSIG };
-#else
-enum { max_signal_number = 128 };
-#endif
-
-extern ASIO_DECL struct signal_state* get_signal_state();
-
-extern "C" ASIO_DECL void asio_signal_handler(int signal_number);
-
-class signal_set_service :
-  public service_base<signal_set_service>
-{
-public:
-  // Type used for tracking an individual signal registration.
-  class registration
-  {
-  public:
-    // Default constructor.
-    registration()
-      : signal_number_(0),
-        queue_(0),
-        undelivered_(0),
-        next_in_table_(0),
-        prev_in_table_(0),
-        next_in_set_(0)
-    {
-    }
-
-  private:
-    // Only this service will have access to the internal values.
-    friend class signal_set_service;
-
-    // The signal number that is registered.
-    int signal_number_;
-
-    // The waiting signal handlers.
-    op_queue<signal_op>* queue_;
-
-    // The number of undelivered signals.
-    std::size_t undelivered_;
-
-    // Pointers to adjacent registrations in the registrations_ table.
-    registration* next_in_table_;
-    registration* prev_in_table_;
-
-    // Link to next registration in the signal set.
-    registration* next_in_set_;
-  };
-
-  // The implementation type of the signal_set.
-  class implementation_type
-  {
-  public:
-    // Default constructor.
-    implementation_type()
-      : signals_(0)
-    {
-    }
-
-  private:
-    // Only this service will have access to the internal values.
-    friend class signal_set_service;
-
-    // The pending signal handlers.
-    op_queue<signal_op> queue_;
-
-    // Linked list of registered signals.
-    registration* signals_;
-  };
-
-  // Constructor.
-  ASIO_DECL signal_set_service(asio::io_context& io_context);
-
-  // Destructor.
-  ASIO_DECL ~signal_set_service();
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Perform fork-related housekeeping.
-  ASIO_DECL void notify_fork(
-      asio::io_context::fork_event fork_ev);
-
-  // Construct a new signal_set implementation.
-  ASIO_DECL void construct(implementation_type& impl);
-
-  // Destroy a signal_set implementation.
-  ASIO_DECL void destroy(implementation_type& impl);
-
-  // Add a signal to a signal_set.
-  ASIO_DECL asio::error_code add(implementation_type& impl,
-      int signal_number, asio::error_code& ec);
-
-  // Remove a signal to a signal_set.
-  ASIO_DECL asio::error_code remove(implementation_type& impl,
-      int signal_number, asio::error_code& ec);
-
-  // Remove all signals from a signal_set.
-  ASIO_DECL asio::error_code clear(implementation_type& impl,
-      asio::error_code& ec);
-
-  // Cancel all operations associated with the signal set.
-  ASIO_DECL asio::error_code cancel(implementation_type& impl,
-      asio::error_code& ec);
-
-  // Start an asynchronous operation to wait for a signal to be delivered.
-  template <typename Handler>
-  void async_wait(implementation_type& impl, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef signal_handler<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((io_context_.context(),
-          *p.p, "signal_set", &impl, 0, "async_wait"));
-
-    start_wait_op(impl, p.p);
-    p.v = p.p = 0;
-  }
-
-  // Deliver notification that a particular signal occurred.
-  ASIO_DECL static void deliver_signal(int signal_number);
-
-private:
-  // Helper function to add a service to the global signal state.
-  ASIO_DECL static void add_service(signal_set_service* service);
-
-  // Helper function to remove a service from the global signal state.
-  ASIO_DECL static void remove_service(signal_set_service* service);
-
-  // Helper function to create the pipe descriptors.
-  ASIO_DECL static void open_descriptors();
-
-  // Helper function to close the pipe descriptors.
-  ASIO_DECL static void close_descriptors();
-
-  // Helper function to start a wait operation.
-  ASIO_DECL void start_wait_op(implementation_type& impl, signal_op* op);
-
-  // The io_context instance used for dispatching handlers.
-  io_context_impl& io_context_;
-
-#if !defined(ASIO_WINDOWS) \
-  && !defined(ASIO_WINDOWS_RUNTIME) \
-  && !defined(__CYGWIN__)
-  // The type used for registering for pipe reactor notifications.
-  class pipe_read_op;
-
-  // The reactor used for waiting for pipe readiness.
-  reactor& reactor_;
-
-  // The per-descriptor reactor data used for the pipe.
-  reactor::per_descriptor_data reactor_data_;
-#endif // !defined(ASIO_WINDOWS)
-       //   && !defined(ASIO_WINDOWS_RUNTIME)
-       //   && !defined(__CYGWIN__)
-
-  // A mapping from signal number to the registered signal sets.
-  registration* registrations_[max_signal_number];
-
-  // Pointers to adjacent services in linked list.
-  signal_set_service* next_;
-  signal_set_service* prev_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/signal_set_service.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_SIGNAL_SET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/socket_holder.hpp b/tools/sdk/include/asio/asio/detail/socket_holder.hpp
deleted file mode 100644
index 99b081f7129..00000000000
--- a/tools/sdk/include/asio/asio/detail/socket_holder.hpp
+++ /dev/null
@@ -1,98 +0,0 @@
-//
-// detail/socket_holder.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SOCKET_HOLDER_HPP
-#define ASIO_DETAIL_SOCKET_HOLDER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Implement the resource acquisition is initialisation idiom for sockets.
-class socket_holder
-  : private noncopyable
-{
-public:
-  // Construct as an uninitialised socket.
-  socket_holder()
-    : socket_(invalid_socket)
-  {
-  }
-
-  // Construct to take ownership of the specified socket.
-  explicit socket_holder(socket_type s)
-    : socket_(s)
-  {
-  }
-
-  // Destructor.
-  ~socket_holder()
-  {
-    if (socket_ != invalid_socket)
-    {
-      asio::error_code ec;
-      socket_ops::state_type state = 0;
-      socket_ops::close(socket_, state, true, ec);
-    }
-  }
-
-  // Get the underlying socket.
-  socket_type get() const
-  {
-    return socket_;
-  }
-
-  // Reset to an uninitialised socket.
-  void reset()
-  {
-    if (socket_ != invalid_socket)
-    {
-      asio::error_code ec;
-      socket_ops::state_type state = 0;
-      socket_ops::close(socket_, state, true, ec);
-      socket_ = invalid_socket;
-    }
-  }
-
-  // Reset to take ownership of the specified socket.
-  void reset(socket_type s)
-  {
-    reset();
-    socket_ = s;
-  }
-
-  // Release ownership of the socket.
-  socket_type release()
-  {
-    socket_type tmp = socket_;
-    socket_ = invalid_socket;
-    return tmp;
-  }
-
-private:
-  // The underlying socket.
-  socket_type socket_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_SOCKET_HOLDER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/socket_ops.hpp b/tools/sdk/include/asio/asio/detail/socket_ops.hpp
deleted file mode 100644
index 815b0d1c8e0..00000000000
--- a/tools/sdk/include/asio/asio/detail/socket_ops.hpp
+++ /dev/null
@@ -1,337 +0,0 @@
-//
-// detail/socket_ops.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SOCKET_OPS_HPP
-#define ASIO_DETAIL_SOCKET_OPS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/error_code.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-namespace socket_ops {
-
-// Socket state bits.
-enum
-{
-  // The user wants a non-blocking socket.
-  user_set_non_blocking = 1,
-
-  // The socket has been set non-blocking.
-  internal_non_blocking = 2,
-
-  // Helper "state" used to determine whether the socket is non-blocking.
-  non_blocking = user_set_non_blocking | internal_non_blocking,
-
-  // User wants connection_aborted errors, which are disabled by default.
-  enable_connection_aborted = 4,
-
-  // The user set the linger option. Needs to be checked when closing.
-  user_set_linger = 8,
-
-  // The socket is stream-oriented.
-  stream_oriented = 16,
-
-  // The socket is datagram-oriented.
-  datagram_oriented = 32,
-
-  // The socket may have been dup()-ed.
-  possible_dup = 64
-};
-
-typedef unsigned char state_type;
-
-struct noop_deleter { void operator()(void*) {} };
-typedef shared_ptr<void> shared_cancel_token_type;
-typedef weak_ptr<void> weak_cancel_token_type;
-
-#if !defined(ASIO_WINDOWS_RUNTIME)
-
-ASIO_DECL socket_type accept(socket_type s, socket_addr_type* addr,
-    std::size_t* addrlen, asio::error_code& ec);
-
-ASIO_DECL socket_type sync_accept(socket_type s,
-    state_type state, socket_addr_type* addr,
-    std::size_t* addrlen, asio::error_code& ec);
-
-#if defined(ASIO_HAS_IOCP)
-
-ASIO_DECL void complete_iocp_accept(socket_type s,
-    void* output_buffer, DWORD address_length,
-    socket_addr_type* addr, std::size_t* addrlen,
-    socket_type new_socket, asio::error_code& ec);
-
-#else // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL bool non_blocking_accept(socket_type s,
-    state_type state, socket_addr_type* addr, std::size_t* addrlen,
-    asio::error_code& ec, socket_type& new_socket);
-
-#endif // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL int bind(socket_type s, const socket_addr_type* addr,
-    std::size_t addrlen, asio::error_code& ec);
-
-ASIO_DECL int close(socket_type s, state_type& state,
-    bool destruction, asio::error_code& ec);
-
-ASIO_DECL bool set_user_non_blocking(socket_type s,
-    state_type& state, bool value, asio::error_code& ec);
-
-ASIO_DECL bool set_internal_non_blocking(socket_type s,
-    state_type& state, bool value, asio::error_code& ec);
-
-ASIO_DECL int shutdown(socket_type s,
-    int what, asio::error_code& ec);
-
-ASIO_DECL int connect(socket_type s, const socket_addr_type* addr,
-    std::size_t addrlen, asio::error_code& ec);
-
-ASIO_DECL void sync_connect(socket_type s, const socket_addr_type* addr,
-    std::size_t addrlen, asio::error_code& ec);
-
-#if defined(ASIO_HAS_IOCP)
-
-ASIO_DECL void complete_iocp_connect(socket_type s,
-    asio::error_code& ec);
-
-#endif // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL bool non_blocking_connect(socket_type s,
-    asio::error_code& ec);
-
-ASIO_DECL int socketpair(int af, int type, int protocol,
-    socket_type sv[2], asio::error_code& ec);
-
-ASIO_DECL bool sockatmark(socket_type s, asio::error_code& ec);
-
-ASIO_DECL size_t available(socket_type s, asio::error_code& ec);
-
-ASIO_DECL int listen(socket_type s,
-    int backlog, asio::error_code& ec);
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-typedef WSABUF buf;
-#else // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-typedef iovec buf;
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-ASIO_DECL void init_buf(buf& b, void* data, size_t size);
-
-ASIO_DECL void init_buf(buf& b, const void* data, size_t size);
-
-ASIO_DECL signed_size_type recv(socket_type s, buf* bufs,
-    size_t count, int flags, asio::error_code& ec);
-
-ASIO_DECL size_t sync_recv(socket_type s, state_type state, buf* bufs,
-    size_t count, int flags, bool all_empty, asio::error_code& ec);
-
-#if defined(ASIO_HAS_IOCP)
-
-ASIO_DECL void complete_iocp_recv(state_type state,
-    const weak_cancel_token_type& cancel_token, bool all_empty,
-    asio::error_code& ec, size_t bytes_transferred);
-
-#else // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL bool non_blocking_recv(socket_type s,
-    buf* bufs, size_t count, int flags, bool is_stream,
-    asio::error_code& ec, size_t& bytes_transferred);
-
-#endif // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL signed_size_type recvfrom(socket_type s, buf* bufs,
-    size_t count, int flags, socket_addr_type* addr,
-    std::size_t* addrlen, asio::error_code& ec);
-
-ASIO_DECL size_t sync_recvfrom(socket_type s, state_type state,
-    buf* bufs, size_t count, int flags, socket_addr_type* addr,
-    std::size_t* addrlen, asio::error_code& ec);
-
-#if defined(ASIO_HAS_IOCP)
-
-ASIO_DECL void complete_iocp_recvfrom(
-    const weak_cancel_token_type& cancel_token,
-    asio::error_code& ec);
-
-#else // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL bool non_blocking_recvfrom(socket_type s,
-    buf* bufs, size_t count, int flags,
-    socket_addr_type* addr, std::size_t* addrlen,
-    asio::error_code& ec, size_t& bytes_transferred);
-
-#endif // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL signed_size_type recvmsg(socket_type s, buf* bufs,
-    size_t count, int in_flags, int& out_flags,
-    asio::error_code& ec);
-
-ASIO_DECL size_t sync_recvmsg(socket_type s, state_type state,
-    buf* bufs, size_t count, int in_flags, int& out_flags,
-    asio::error_code& ec);
-
-#if defined(ASIO_HAS_IOCP)
-
-ASIO_DECL void complete_iocp_recvmsg(
-    const weak_cancel_token_type& cancel_token,
-    asio::error_code& ec);
-
-#else // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL bool non_blocking_recvmsg(socket_type s,
-    buf* bufs, size_t count, int in_flags, int& out_flags,
-    asio::error_code& ec, size_t& bytes_transferred);
-
-#endif // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL signed_size_type send(socket_type s, const buf* bufs,
-    size_t count, int flags, asio::error_code& ec);
-
-ASIO_DECL size_t sync_send(socket_type s, state_type state,
-    const buf* bufs, size_t count, int flags,
-    bool all_empty, asio::error_code& ec);
-
-#if defined(ASIO_HAS_IOCP)
-
-ASIO_DECL void complete_iocp_send(
-    const weak_cancel_token_type& cancel_token,
-    asio::error_code& ec);
-
-#else // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL bool non_blocking_send(socket_type s,
-    const buf* bufs, size_t count, int flags,
-    asio::error_code& ec, size_t& bytes_transferred);
-
-#endif // defined(ASIO_HAS_IOCP)
-
-ASIO_DECL signed_size_type sendto(socket_type s, const buf* bufs,
-    size_t count, int flags, const socket_addr_type* addr,
-    std::size_t addrlen, asio::error_code& ec);
-
-ASIO_DECL size_t sync_sendto(socket_type s, state_type state,
-    const buf* bufs, size_t count, int flags, const socket_addr_type* addr,
-    std::size_t addrlen, asio::error_code& ec);
-
-#if !defined(ASIO_HAS_IOCP)
-
-ASIO_DECL bool non_blocking_sendto(socket_type s,
-    const buf* bufs, size_t count, int flags,
-    const socket_addr_type* addr, std::size_t addrlen,
-    asio::error_code& ec, size_t& bytes_transferred);
-
-#endif // !defined(ASIO_HAS_IOCP)
-
-ASIO_DECL socket_type socket(int af, int type, int protocol,
-    asio::error_code& ec);
-
-ASIO_DECL int setsockopt(socket_type s, state_type& state,
-    int level, int optname, const void* optval,
-    std::size_t optlen, asio::error_code& ec);
-
-ASIO_DECL int getsockopt(socket_type s, state_type state,
-    int level, int optname, void* optval,
-    size_t* optlen, asio::error_code& ec);
-
-ASIO_DECL int getpeername(socket_type s, socket_addr_type* addr,
-    std::size_t* addrlen, bool cached, asio::error_code& ec);
-
-ASIO_DECL int getsockname(socket_type s, socket_addr_type* addr,
-    std::size_t* addrlen, asio::error_code& ec);
-
-ASIO_DECL int ioctl(socket_type s, state_type& state,
-    int cmd, ioctl_arg_type* arg, asio::error_code& ec);
-
-ASIO_DECL int select(int nfds, fd_set* readfds, fd_set* writefds,
-    fd_set* exceptfds, timeval* timeout, asio::error_code& ec);
-
-ASIO_DECL int poll_read(socket_type s,
-    state_type state, int msec, asio::error_code& ec);
-
-ASIO_DECL int poll_write(socket_type s,
-    state_type state, int msec, asio::error_code& ec);
-
-ASIO_DECL int poll_error(socket_type s,
-    state_type state, int msec, asio::error_code& ec);
-
-ASIO_DECL int poll_connect(socket_type s,
-    int msec, asio::error_code& ec);
-
-#endif // !defined(ASIO_WINDOWS_RUNTIME)
-
-ASIO_DECL const char* inet_ntop(int af, const void* src, char* dest,
-    size_t length, unsigned long scope_id, asio::error_code& ec);
-
-ASIO_DECL int inet_pton(int af, const char* src, void* dest,
-    unsigned long* scope_id, asio::error_code& ec);
-
-ASIO_DECL int gethostname(char* name,
-    int namelen, asio::error_code& ec);
-
-#if !defined(ASIO_WINDOWS_RUNTIME)
-
-ASIO_DECL asio::error_code getaddrinfo(const char* host,
-    const char* service, const addrinfo_type& hints,
-    addrinfo_type** result, asio::error_code& ec);
-
-ASIO_DECL asio::error_code background_getaddrinfo(
-    const weak_cancel_token_type& cancel_token, const char* host,
-    const char* service, const addrinfo_type& hints,
-    addrinfo_type** result, asio::error_code& ec);
-
-ASIO_DECL void freeaddrinfo(addrinfo_type* ai);
-
-ASIO_DECL asio::error_code getnameinfo(
-    const socket_addr_type* addr, std::size_t addrlen,
-    char* host, std::size_t hostlen, char* serv,
-    std::size_t servlen, int flags, asio::error_code& ec);
-
-ASIO_DECL asio::error_code sync_getnameinfo(
-    const socket_addr_type* addr, std::size_t addrlen,
-    char* host, std::size_t hostlen, char* serv,
-    std::size_t servlen, int sock_type, asio::error_code& ec);
-
-ASIO_DECL asio::error_code background_getnameinfo(
-    const weak_cancel_token_type& cancel_token,
-    const socket_addr_type* addr, std::size_t addrlen,
-    char* host, std::size_t hostlen, char* serv,
-    std::size_t servlen, int sock_type, asio::error_code& ec);
-
-#endif // !defined(ASIO_WINDOWS_RUNTIME)
-
-ASIO_DECL u_long_type network_to_host_long(u_long_type value);
-
-ASIO_DECL u_long_type host_to_network_long(u_long_type value);
-
-ASIO_DECL u_short_type network_to_host_short(u_short_type value);
-
-ASIO_DECL u_short_type host_to_network_short(u_short_type value);
-
-} // namespace socket_ops
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/socket_ops.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_SOCKET_OPS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/socket_option.hpp b/tools/sdk/include/asio/asio/detail/socket_option.hpp
deleted file mode 100644
index 6852d56993e..00000000000
--- a/tools/sdk/include/asio/asio/detail/socket_option.hpp
+++ /dev/null
@@ -1,316 +0,0 @@
-//
-// detail/socket_option.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SOCKET_OPTION_HPP
-#define ASIO_DETAIL_SOCKET_OPTION_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <stdexcept>
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/throw_exception.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-namespace socket_option {
-
-// Helper template for implementing boolean-based options.
-template <int Level, int Name>
-class boolean
-{
-public:
-  // Default constructor.
-  boolean()
-    : value_(0)
-  {
-  }
-
-  // Construct with a specific option value.
-  explicit boolean(bool v)
-    : value_(v ? 1 : 0)
-  {
-  }
-
-  // Set the current value of the boolean.
-  boolean& operator=(bool v)
-  {
-    value_ = v ? 1 : 0;
-    return *this;
-  }
-
-  // Get the current value of the boolean.
-  bool value() const
-  {
-    return !!value_;
-  }
-
-  // Convert to bool.
-  operator bool() const
-  {
-    return !!value_;
-  }
-
-  // Test for false.
-  bool operator!() const
-  {
-    return !value_;
-  }
-
-  // Get the level of the socket option.
-  template <typename Protocol>
-  int level(const Protocol&) const
-  {
-    return Level;
-  }
-
-  // Get the name of the socket option.
-  template <typename Protocol>
-  int name(const Protocol&) const
-  {
-    return Name;
-  }
-
-  // Get the address of the boolean data.
-  template <typename Protocol>
-  int* data(const Protocol&)
-  {
-    return &value_;
-  }
-
-  // Get the address of the boolean data.
-  template <typename Protocol>
-  const int* data(const Protocol&) const
-  {
-    return &value_;
-  }
-
-  // Get the size of the boolean data.
-  template <typename Protocol>
-  std::size_t size(const Protocol&) const
-  {
-    return sizeof(value_);
-  }
-
-  // Set the size of the boolean data.
-  template <typename Protocol>
-  void resize(const Protocol&, std::size_t s)
-  {
-    // On some platforms (e.g. Windows Vista), the getsockopt function will
-    // return the size of a boolean socket option as one byte, even though a
-    // four byte integer was passed in.
-    switch (s)
-    {
-    case sizeof(char):
-      value_ = *reinterpret_cast<char*>(&value_) ? 1 : 0;
-      break;
-    case sizeof(value_):
-      break;
-    default:
-      {
-        std::length_error ex("boolean socket option resize");
-        asio::detail::throw_exception(ex);
-      }
-    }
-  }
-
-private:
-  int value_;
-};
-
-// Helper template for implementing integer options.
-template <int Level, int Name>
-class integer
-{
-public:
-  // Default constructor.
-  integer()
-    : value_(0)
-  {
-  }
-
-  // Construct with a specific option value.
-  explicit integer(int v)
-    : value_(v)
-  {
-  }
-
-  // Set the value of the int option.
-  integer& operator=(int v)
-  {
-    value_ = v;
-    return *this;
-  }
-
-  // Get the current value of the int option.
-  int value() const
-  {
-    return value_;
-  }
-
-  // Get the level of the socket option.
-  template <typename Protocol>
-  int level(const Protocol&) const
-  {
-    return Level;
-  }
-
-  // Get the name of the socket option.
-  template <typename Protocol>
-  int name(const Protocol&) const
-  {
-    return Name;
-  }
-
-  // Get the address of the int data.
-  template <typename Protocol>
-  int* data(const Protocol&)
-  {
-    return &value_;
-  }
-
-  // Get the address of the int data.
-  template <typename Protocol>
-  const int* data(const Protocol&) const
-  {
-    return &value_;
-  }
-
-  // Get the size of the int data.
-  template <typename Protocol>
-  std::size_t size(const Protocol&) const
-  {
-    return sizeof(value_);
-  }
-
-  // Set the size of the int data.
-  template <typename Protocol>
-  void resize(const Protocol&, std::size_t s)
-  {
-    if (s != sizeof(value_))
-    {
-      std::length_error ex("integer socket option resize");
-      asio::detail::throw_exception(ex);
-    }
-  }
-
-private:
-  int value_;
-};
-
-// Helper template for implementing linger options.
-template <int Level, int Name>
-class linger
-{
-public:
-  // Default constructor.
-  linger()
-  {
-    value_.l_onoff = 0;
-    value_.l_linger = 0;
-  }
-
-  // Construct with specific option values.
-  linger(bool e, int t)
-  {
-    enabled(e);
-    timeout ASIO_PREVENT_MACRO_SUBSTITUTION(t);
-  }
-
-  // Set the value for whether linger is enabled.
-  void enabled(bool value)
-  {
-    value_.l_onoff = value ? 1 : 0;
-  }
-
-  // Get the value for whether linger is enabled.
-  bool enabled() const
-  {
-    return value_.l_onoff != 0;
-  }
-
-  // Set the value for the linger timeout.
-  void timeout ASIO_PREVENT_MACRO_SUBSTITUTION(int value)
-  {
-#if defined(WIN32)
-    value_.l_linger = static_cast<u_short>(value);
-#else
-    value_.l_linger = value;
-#endif
-  }
-
-  // Get the value for the linger timeout.
-  int timeout ASIO_PREVENT_MACRO_SUBSTITUTION() const
-  {
-    return static_cast<int>(value_.l_linger);
-  }
-
-  // Get the level of the socket option.
-  template <typename Protocol>
-  int level(const Protocol&) const
-  {
-    return Level;
-  }
-
-  // Get the name of the socket option.
-  template <typename Protocol>
-  int name(const Protocol&) const
-  {
-    return Name;
-  }
-
-  // Get the address of the linger data.
-  template <typename Protocol>
-  detail::linger_type* data(const Protocol&)
-  {
-    return &value_;
-  }
-
-  // Get the address of the linger data.
-  template <typename Protocol>
-  const detail::linger_type* data(const Protocol&) const
-  {
-    return &value_;
-  }
-
-  // Get the size of the linger data.
-  template <typename Protocol>
-  std::size_t size(const Protocol&) const
-  {
-    return sizeof(value_);
-  }
-
-  // Set the size of the int data.
-  template <typename Protocol>
-  void resize(const Protocol&, std::size_t s)
-  {
-    if (s != sizeof(value_))
-    {
-      std::length_error ex("linger socket option resize");
-      asio::detail::throw_exception(ex);
-    }
-  }
-
-private:
-  detail::linger_type value_;
-};
-
-} // namespace socket_option
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_SOCKET_OPTION_HPP
diff --git a/tools/sdk/include/asio/asio/detail/socket_select_interrupter.hpp b/tools/sdk/include/asio/asio/detail/socket_select_interrupter.hpp
deleted file mode 100644
index 540b2aebd40..00000000000
--- a/tools/sdk/include/asio/asio/detail/socket_select_interrupter.hpp
+++ /dev/null
@@ -1,92 +0,0 @@
-//
-// detail/socket_select_interrupter.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SOCKET_SELECT_INTERRUPTER_HPP
-#define ASIO_DETAIL_SOCKET_SELECT_INTERRUPTER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_WINDOWS_RUNTIME)
-
-#if defined(ASIO_WINDOWS) \
-  || defined(__CYGWIN__) \
-  || defined(__SYMBIAN32__) \
-  || defined(ESP_PLATFORM)
-
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class socket_select_interrupter
-{
-public:
-  // Constructor.
-  ASIO_DECL socket_select_interrupter();
-
-  // Destructor.
-  ASIO_DECL ~socket_select_interrupter();
-
-  // Recreate the interrupter's descriptors. Used after a fork.
-  ASIO_DECL void recreate();
-
-  // Interrupt the select call.
-  ASIO_DECL void interrupt();
-
-  // Reset the select interrupt. Returns true if the call was interrupted.
-  ASIO_DECL bool reset();
-
-  // Get the read descriptor to be passed to select.
-  socket_type read_descriptor() const
-  {
-    return read_descriptor_;
-  }
-
-private:
-  // Open the descriptors. Throws on error.
-  ASIO_DECL void open_descriptors();
-
-  // Close the descriptors.
-  ASIO_DECL void close_descriptors();
-
-  // The read end of a connection used to interrupt the select call. This file
-  // descriptor is passed to select such that when it is time to stop, a single
-  // byte will be written on the other end of the connection and this
-  // descriptor will become readable.
-  socket_type read_descriptor_;
-
-  // The write end of a connection used to interrupt the select call. A single
-  // byte may be written to this to wake up the select which is waiting for the
-  // other end to become readable.
-  socket_type write_descriptor_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/socket_select_interrupter.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_WINDOWS)
-       // || defined(__CYGWIN__)
-       // || defined(__SYMBIAN32__)
-
-#endif // !defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_SOCKET_SELECT_INTERRUPTER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/socket_types.hpp b/tools/sdk/include/asio/asio/detail/socket_types.hpp
deleted file mode 100644
index 6f1abb20536..00000000000
--- a/tools/sdk/include/asio/asio/detail/socket_types.hpp
+++ /dev/null
@@ -1,419 +0,0 @@
-//
-// detail/socket_types.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SOCKET_TYPES_HPP
-#define ASIO_DETAIL_SOCKET_TYPES_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-// Empty.
-#elif defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-# if defined(_WINSOCKAPI_) && !defined(_WINSOCK2API_)
-#  error WinSock.h has already been included
-# endif // defined(_WINSOCKAPI_) && !defined(_WINSOCK2API_)
-# if defined(__BORLANDC__)
-#  include <stdlib.h> // Needed for __errno
-#  if !defined(_WSPIAPI_H_)
-#   define _WSPIAPI_H_
-#   define ASIO_WSPIAPI_H_DEFINED
-#  endif // !defined(_WSPIAPI_H_)
-# endif // defined(__BORLANDC__)
-# include <winsock2.h>
-# include <ws2tcpip.h>
-# if defined(WINAPI_FAMILY)
-#  if ((WINAPI_FAMILY & WINAPI_PARTITION_DESKTOP) != 0)
-#   include <windows.h>
-#  endif // ((WINAPI_FAMILY & WINAPI_PARTITION_DESKTOP) != 0)
-# endif // defined(WINAPI_FAMILY)
-# if !defined(ASIO_WINDOWS_APP)
-#  include <mswsock.h>
-# endif // !defined(ASIO_WINDOWS_APP)
-# if defined(ASIO_WSPIAPI_H_DEFINED)
-#  undef _WSPIAPI_H_
-#  undef ASIO_WSPIAPI_H_DEFINED
-# endif // defined(ASIO_WSPIAPI_H_DEFINED)
-# if !defined(ASIO_NO_DEFAULT_LINKED_LIBS)
-#  if defined(UNDER_CE)
-#   pragma comment(lib, "ws2.lib")
-#  elif defined(_MSC_VER) || defined(__BORLANDC__)
-#   pragma comment(lib, "ws2_32.lib")
-#   if !defined(ASIO_WINDOWS_APP)
-#    pragma comment(lib, "mswsock.lib")
-#   endif // !defined(ASIO_WINDOWS_APP)
-#  endif // defined(_MSC_VER) || defined(__BORLANDC__)
-# endif // !defined(ASIO_NO_DEFAULT_LINKED_LIBS)
-# include "asio/detail/old_win_sdk_compat.hpp"
-#else
-# include <sys/ioctl.h>
-# if (defined(__MACH__) && defined(__APPLE__)) \
-   || defined(__FreeBSD__) || defined(__NetBSD__) \
-   || defined(__OpenBSD__) || defined(__linux__) \
-   || defined(__EMSCRIPTEN__)
-#  include <poll.h>
-# elif !defined(__SYMBIAN32__)
-#  include <sys/poll.h>
-# endif
-# include <sys/types.h>
-# include <sys/stat.h>
-# include <fcntl.h>
-# if defined(__hpux)
-#  include <sys/time.h>
-# endif
-# if !defined(__hpux) || defined(__SELECT)
-#  include <sys/select.h>
-# endif
-# include <sys/socket.h>
-# include <sys/uio.h>
-# include <sys/un.h>
-# include <netinet/in.h>
-# if !defined(__SYMBIAN32__) && !defined(ESP_PLATFORM)
-#  include <netinet/tcp.h>
-# endif
-# include <arpa/inet.h>
-# include <netdb.h>
-# include <net/if.h>
-# if defined(ESP_PLATFORM)
-#  include "esp_exception.h"
-# endif
-# include <limits.h>
-# if defined(__sun)
-#  include <sys/filio.h>
-#  include <sys/sockio.h>
-# endif
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-const int max_addr_v4_str_len = 256;
-const int max_addr_v6_str_len = 256;
-typedef unsigned __int32 u_long_type;
-typedef unsigned __int16 u_short_type;
-struct in4_addr_type { u_long_type s_addr; };
-struct in4_mreq_type { in4_addr_type imr_multiaddr, imr_interface; };
-struct in6_addr_type { unsigned char s6_addr[16]; };
-struct in6_mreq_type { in6_addr_type ipv6mr_multiaddr;
-  unsigned long ipv6mr_interface; };
-struct socket_addr_type { int sa_family; };
-struct sockaddr_in4_type { int sin_family;
-  in4_addr_type sin_addr; u_short_type sin_port; };
-struct sockaddr_in6_type { int sin6_family;
-  in6_addr_type sin6_addr; u_short_type sin6_port;
-  u_long_type sin6_flowinfo; u_long_type sin6_scope_id; };
-struct sockaddr_storage_type { int ss_family;
-  unsigned char ss_bytes[128 - sizeof(int)]; };
-struct addrinfo_type { int ai_flags;
-  int ai_family, ai_socktype, ai_protocol;
-  int ai_addrlen; const void* ai_addr;
-  const char* ai_canonname; addrinfo_type* ai_next; };
-struct linger_type { u_short_type l_onoff, l_linger; };
-typedef u_long_type ioctl_arg_type;
-typedef int signed_size_type;
-# define ASIO_OS_DEF(c) ASIO_OS_DEF_##c
-# define ASIO_OS_DEF_AF_UNSPEC 0
-# define ASIO_OS_DEF_AF_INET 2
-# define ASIO_OS_DEF_AF_INET6 23
-# define ASIO_OS_DEF_SOCK_STREAM 1
-# define ASIO_OS_DEF_SOCK_DGRAM 2
-# define ASIO_OS_DEF_SOCK_RAW 3
-# define ASIO_OS_DEF_SOCK_SEQPACKET 5
-# define ASIO_OS_DEF_IPPROTO_IP 0
-# define ASIO_OS_DEF_IPPROTO_IPV6 41
-# define ASIO_OS_DEF_IPPROTO_TCP 6
-# define ASIO_OS_DEF_IPPROTO_UDP 17
-# define ASIO_OS_DEF_IPPROTO_ICMP 1
-# define ASIO_OS_DEF_IPPROTO_ICMPV6 58
-# define ASIO_OS_DEF_FIONBIO 1
-# define ASIO_OS_DEF_FIONREAD 2
-# define ASIO_OS_DEF_INADDR_ANY 0
-# define ASIO_OS_DEF_MSG_OOB 0x1
-# define ASIO_OS_DEF_MSG_PEEK 0x2
-# define ASIO_OS_DEF_MSG_DONTROUTE 0x4
-# define ASIO_OS_DEF_MSG_EOR 0 // Not supported.
-# define ASIO_OS_DEF_SHUT_RD 0x0
-# define ASIO_OS_DEF_SHUT_WR 0x1
-# define ASIO_OS_DEF_SHUT_RDWR 0x2
-# define ASIO_OS_DEF_SOMAXCONN 0x7fffffff
-# define ASIO_OS_DEF_SOL_SOCKET 0xffff
-# define ASIO_OS_DEF_SO_BROADCAST 0x20
-# define ASIO_OS_DEF_SO_DEBUG 0x1
-# define ASIO_OS_DEF_SO_DONTROUTE 0x10
-# define ASIO_OS_DEF_SO_KEEPALIVE 0x8
-# define ASIO_OS_DEF_SO_LINGER 0x80
-# define ASIO_OS_DEF_SO_OOBINLINE 0x100
-# define ASIO_OS_DEF_SO_SNDBUF 0x1001
-# define ASIO_OS_DEF_SO_RCVBUF 0x1002
-# define ASIO_OS_DEF_SO_SNDLOWAT 0x1003
-# define ASIO_OS_DEF_SO_RCVLOWAT 0x1004
-# define ASIO_OS_DEF_SO_REUSEADDR 0x4
-# define ASIO_OS_DEF_TCP_NODELAY 0x1
-# define ASIO_OS_DEF_IP_MULTICAST_IF 2
-# define ASIO_OS_DEF_IP_MULTICAST_TTL 3
-# define ASIO_OS_DEF_IP_MULTICAST_LOOP 4
-# define ASIO_OS_DEF_IP_ADD_MEMBERSHIP 5
-# define ASIO_OS_DEF_IP_DROP_MEMBERSHIP 6
-# define ASIO_OS_DEF_IP_TTL 7
-# define ASIO_OS_DEF_IPV6_UNICAST_HOPS 4
-# define ASIO_OS_DEF_IPV6_MULTICAST_IF 9
-# define ASIO_OS_DEF_IPV6_MULTICAST_HOPS 10
-# define ASIO_OS_DEF_IPV6_MULTICAST_LOOP 11
-# define ASIO_OS_DEF_IPV6_JOIN_GROUP 12
-# define ASIO_OS_DEF_IPV6_LEAVE_GROUP 13
-# define ASIO_OS_DEF_AI_CANONNAME 0x2
-# define ASIO_OS_DEF_AI_PASSIVE 0x1
-# define ASIO_OS_DEF_AI_NUMERICHOST 0x4
-# define ASIO_OS_DEF_AI_NUMERICSERV 0x8
-# define ASIO_OS_DEF_AI_V4MAPPED 0x800
-# define ASIO_OS_DEF_AI_ALL 0x100
-# define ASIO_OS_DEF_AI_ADDRCONFIG 0x400
-#elif defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-typedef SOCKET socket_type;
-const SOCKET invalid_socket = INVALID_SOCKET;
-const int socket_error_retval = SOCKET_ERROR;
-const int max_addr_v4_str_len = 256;
-const int max_addr_v6_str_len = 256;
-typedef sockaddr socket_addr_type;
-typedef in_addr in4_addr_type;
-typedef ip_mreq in4_mreq_type;
-typedef sockaddr_in sockaddr_in4_type;
-# if defined(ASIO_HAS_OLD_WIN_SDK)
-typedef in6_addr_emulation in6_addr_type;
-typedef ipv6_mreq_emulation in6_mreq_type;
-typedef sockaddr_in6_emulation sockaddr_in6_type;
-typedef sockaddr_storage_emulation sockaddr_storage_type;
-typedef addrinfo_emulation addrinfo_type;
-# else
-typedef in6_addr in6_addr_type;
-typedef ipv6_mreq in6_mreq_type;
-typedef sockaddr_in6 sockaddr_in6_type;
-typedef sockaddr_storage sockaddr_storage_type;
-typedef addrinfo addrinfo_type;
-# endif
-typedef ::linger linger_type;
-typedef unsigned long ioctl_arg_type;
-typedef u_long u_long_type;
-typedef u_short u_short_type;
-typedef int signed_size_type;
-# define ASIO_OS_DEF(c) ASIO_OS_DEF_##c
-# define ASIO_OS_DEF_AF_UNSPEC AF_UNSPEC
-# define ASIO_OS_DEF_AF_INET AF_INET
-# define ASIO_OS_DEF_AF_INET6 AF_INET6
-# define ASIO_OS_DEF_SOCK_STREAM SOCK_STREAM
-# define ASIO_OS_DEF_SOCK_DGRAM SOCK_DGRAM
-# define ASIO_OS_DEF_SOCK_RAW SOCK_RAW
-# define ASIO_OS_DEF_SOCK_SEQPACKET SOCK_SEQPACKET
-# define ASIO_OS_DEF_IPPROTO_IP IPPROTO_IP
-# define ASIO_OS_DEF_IPPROTO_IPV6 IPPROTO_IPV6
-# define ASIO_OS_DEF_IPPROTO_TCP IPPROTO_TCP
-# define ASIO_OS_DEF_IPPROTO_UDP IPPROTO_UDP
-# define ASIO_OS_DEF_IPPROTO_ICMP IPPROTO_ICMP
-# define ASIO_OS_DEF_IPPROTO_ICMPV6 IPPROTO_ICMPV6
-# define ASIO_OS_DEF_FIONBIO FIONBIO
-# define ASIO_OS_DEF_FIONREAD FIONREAD
-# define ASIO_OS_DEF_INADDR_ANY INADDR_ANY
-# define ASIO_OS_DEF_MSG_OOB MSG_OOB
-# define ASIO_OS_DEF_MSG_PEEK MSG_PEEK
-# define ASIO_OS_DEF_MSG_DONTROUTE MSG_DONTROUTE
-# define ASIO_OS_DEF_MSG_EOR 0 // Not supported on Windows.
-# define ASIO_OS_DEF_SHUT_RD SD_RECEIVE
-# define ASIO_OS_DEF_SHUT_WR SD_SEND
-# define ASIO_OS_DEF_SHUT_RDWR SD_BOTH
-# define ASIO_OS_DEF_SOMAXCONN SOMAXCONN
-# define ASIO_OS_DEF_SOL_SOCKET SOL_SOCKET
-# define ASIO_OS_DEF_SO_BROADCAST SO_BROADCAST
-# define ASIO_OS_DEF_SO_DEBUG SO_DEBUG
-# define ASIO_OS_DEF_SO_DONTROUTE SO_DONTROUTE
-# define ASIO_OS_DEF_SO_KEEPALIVE SO_KEEPALIVE
-# define ASIO_OS_DEF_SO_LINGER SO_LINGER
-# define ASIO_OS_DEF_SO_OOBINLINE SO_OOBINLINE
-# define ASIO_OS_DEF_SO_SNDBUF SO_SNDBUF
-# define ASIO_OS_DEF_SO_RCVBUF SO_RCVBUF
-# define ASIO_OS_DEF_SO_SNDLOWAT SO_SNDLOWAT
-# define ASIO_OS_DEF_SO_RCVLOWAT SO_RCVLOWAT
-# define ASIO_OS_DEF_SO_REUSEADDR SO_REUSEADDR
-# define ASIO_OS_DEF_TCP_NODELAY TCP_NODELAY
-# define ASIO_OS_DEF_IP_MULTICAST_IF IP_MULTICAST_IF
-# define ASIO_OS_DEF_IP_MULTICAST_TTL IP_MULTICAST_TTL
-# define ASIO_OS_DEF_IP_MULTICAST_LOOP IP_MULTICAST_LOOP
-# define ASIO_OS_DEF_IP_ADD_MEMBERSHIP IP_ADD_MEMBERSHIP
-# define ASIO_OS_DEF_IP_DROP_MEMBERSHIP IP_DROP_MEMBERSHIP
-# define ASIO_OS_DEF_IP_TTL IP_TTL
-# define ASIO_OS_DEF_IPV6_UNICAST_HOPS IPV6_UNICAST_HOPS
-# define ASIO_OS_DEF_IPV6_MULTICAST_IF IPV6_MULTICAST_IF
-# define ASIO_OS_DEF_IPV6_MULTICAST_HOPS IPV6_MULTICAST_HOPS
-# define ASIO_OS_DEF_IPV6_MULTICAST_LOOP IPV6_MULTICAST_LOOP
-# define ASIO_OS_DEF_IPV6_JOIN_GROUP IPV6_JOIN_GROUP
-# define ASIO_OS_DEF_IPV6_LEAVE_GROUP IPV6_LEAVE_GROUP
-# define ASIO_OS_DEF_AI_CANONNAME AI_CANONNAME
-# define ASIO_OS_DEF_AI_PASSIVE AI_PASSIVE
-# define ASIO_OS_DEF_AI_NUMERICHOST AI_NUMERICHOST
-# if defined(AI_NUMERICSERV)
-#  define ASIO_OS_DEF_AI_NUMERICSERV AI_NUMERICSERV
-# else
-#  define ASIO_OS_DEF_AI_NUMERICSERV 0
-# endif
-# if defined(AI_V4MAPPED)
-#  define ASIO_OS_DEF_AI_V4MAPPED AI_V4MAPPED
-# else
-#  define ASIO_OS_DEF_AI_V4MAPPED 0
-# endif
-# if defined(AI_ALL)
-#  define ASIO_OS_DEF_AI_ALL AI_ALL
-# else
-#  define ASIO_OS_DEF_AI_ALL 0
-# endif
-# if defined(AI_ADDRCONFIG)
-#  define ASIO_OS_DEF_AI_ADDRCONFIG AI_ADDRCONFIG
-# else
-#  define ASIO_OS_DEF_AI_ADDRCONFIG 0
-# endif
-# if defined (_WIN32_WINNT)
-const int max_iov_len = 64;
-# else
-const int max_iov_len = 16;
-# endif
-#else
-typedef int socket_type;
-const int invalid_socket = -1;
-const int socket_error_retval = -1;
-const int max_addr_v4_str_len = INET_ADDRSTRLEN;
-#if defined(INET6_ADDRSTRLEN)
-const int max_addr_v6_str_len = INET6_ADDRSTRLEN + 1 + IF_NAMESIZE;
-#else // defined(INET6_ADDRSTRLEN)
-const int max_addr_v6_str_len = 256;
-#endif // defined(INET6_ADDRSTRLEN)
-typedef sockaddr socket_addr_type;
-typedef in_addr in4_addr_type;
-# if defined(__hpux)
-// HP-UX doesn't provide ip_mreq when _XOPEN_SOURCE_EXTENDED is defined.
-struct in4_mreq_type
-{
-  struct in_addr imr_multiaddr;
-  struct in_addr imr_interface;
-};
-# else
-typedef ip_mreq in4_mreq_type;
-# endif
-typedef sockaddr_in sockaddr_in4_type;
-typedef in6_addr in6_addr_type;
-typedef ipv6_mreq in6_mreq_type;
-typedef sockaddr_in6 sockaddr_in6_type;
-typedef sockaddr_storage sockaddr_storage_type;
-typedef sockaddr_un sockaddr_un_type;
-typedef addrinfo addrinfo_type;
-typedef ::linger linger_type;
-typedef int ioctl_arg_type;
-typedef uint32_t u_long_type;
-typedef uint16_t u_short_type;
-#if defined(ASIO_HAS_SSIZE_T)
-typedef ssize_t signed_size_type;
-#else // defined(ASIO_HAS_SSIZE_T)
-typedef int signed_size_type;
-#endif // defined(ASIO_HAS_SSIZE_T)
-# define ASIO_OS_DEF(c) ASIO_OS_DEF_##c
-# define ASIO_OS_DEF_AF_UNSPEC AF_UNSPEC
-# define ASIO_OS_DEF_AF_INET AF_INET
-# define ASIO_OS_DEF_AF_INET6 AF_INET6
-# define ASIO_OS_DEF_SOCK_STREAM SOCK_STREAM
-# define ASIO_OS_DEF_SOCK_DGRAM SOCK_DGRAM
-# define ASIO_OS_DEF_SOCK_RAW SOCK_RAW
-# define ASIO_OS_DEF_SOCK_SEQPACKET SOCK_SEQPACKET
-# define ASIO_OS_DEF_IPPROTO_IP IPPROTO_IP
-# define ASIO_OS_DEF_IPPROTO_IPV6 IPPROTO_IPV6
-# define ASIO_OS_DEF_IPPROTO_TCP IPPROTO_TCP
-# define ASIO_OS_DEF_IPPROTO_UDP IPPROTO_UDP
-# define ASIO_OS_DEF_IPPROTO_ICMP IPPROTO_ICMP
-# define ASIO_OS_DEF_IPPROTO_ICMPV6 IPPROTO_ICMPV6
-# define ASIO_OS_DEF_FIONBIO FIONBIO
-# define ASIO_OS_DEF_FIONREAD FIONREAD
-# define ASIO_OS_DEF_INADDR_ANY INADDR_ANY
-# define ASIO_OS_DEF_MSG_OOB MSG_OOB
-# define ASIO_OS_DEF_MSG_PEEK MSG_PEEK
-# define ASIO_OS_DEF_MSG_DONTROUTE MSG_DONTROUTE
-# define ASIO_OS_DEF_MSG_EOR MSG_EOR
-# define ASIO_OS_DEF_SHUT_RD SHUT_RD
-# define ASIO_OS_DEF_SHUT_WR SHUT_WR
-# define ASIO_OS_DEF_SHUT_RDWR SHUT_RDWR
-# define ASIO_OS_DEF_SOMAXCONN SOMAXCONN
-# define ASIO_OS_DEF_SOL_SOCKET SOL_SOCKET
-# define ASIO_OS_DEF_SO_BROADCAST SO_BROADCAST
-# define ASIO_OS_DEF_SO_DEBUG SO_DEBUG
-# define ASIO_OS_DEF_SO_DONTROUTE SO_DONTROUTE
-# define ASIO_OS_DEF_SO_KEEPALIVE SO_KEEPALIVE
-# define ASIO_OS_DEF_SO_LINGER SO_LINGER
-# define ASIO_OS_DEF_SO_OOBINLINE SO_OOBINLINE
-# define ASIO_OS_DEF_SO_SNDBUF SO_SNDBUF
-# define ASIO_OS_DEF_SO_RCVBUF SO_RCVBUF
-# define ASIO_OS_DEF_SO_SNDLOWAT SO_SNDLOWAT
-# define ASIO_OS_DEF_SO_RCVLOWAT SO_RCVLOWAT
-# define ASIO_OS_DEF_SO_REUSEADDR SO_REUSEADDR
-# define ASIO_OS_DEF_TCP_NODELAY TCP_NODELAY
-# define ASIO_OS_DEF_IP_MULTICAST_IF IP_MULTICAST_IF
-# define ASIO_OS_DEF_IP_MULTICAST_TTL IP_MULTICAST_TTL
-# define ASIO_OS_DEF_IP_MULTICAST_LOOP IP_MULTICAST_LOOP
-# define ASIO_OS_DEF_IP_ADD_MEMBERSHIP IP_ADD_MEMBERSHIP
-# define ASIO_OS_DEF_IP_DROP_MEMBERSHIP IP_DROP_MEMBERSHIP
-# define ASIO_OS_DEF_IP_TTL IP_TTL
-# define ASIO_OS_DEF_IPV6_UNICAST_HOPS IPV6_UNICAST_HOPS
-# define ASIO_OS_DEF_IPV6_MULTICAST_IF IPV6_MULTICAST_IF
-# define ASIO_OS_DEF_IPV6_MULTICAST_HOPS IPV6_MULTICAST_HOPS
-# define ASIO_OS_DEF_IPV6_MULTICAST_LOOP IPV6_MULTICAST_LOOP
-# define ASIO_OS_DEF_IPV6_JOIN_GROUP IPV6_JOIN_GROUP
-# define ASIO_OS_DEF_IPV6_LEAVE_GROUP IPV6_LEAVE_GROUP
-# define ASIO_OS_DEF_AI_CANONNAME AI_CANONNAME
-# define ASIO_OS_DEF_AI_PASSIVE AI_PASSIVE
-# define ASIO_OS_DEF_AI_NUMERICHOST AI_NUMERICHOST
-# if defined(AI_NUMERICSERV)
-#  define ASIO_OS_DEF_AI_NUMERICSERV AI_NUMERICSERV
-# else
-#  define ASIO_OS_DEF_AI_NUMERICSERV 0
-# endif
-// Note: QNX Neutrino 6.3 defines AI_V4MAPPED, AI_ALL and AI_ADDRCONFIG but
-// does not implement them. Therefore they are specifically excluded here.
-# if defined(AI_V4MAPPED) && !defined(__QNXNTO__)
-#  define ASIO_OS_DEF_AI_V4MAPPED AI_V4MAPPED
-# else
-#  define ASIO_OS_DEF_AI_V4MAPPED 0
-# endif
-# if defined(AI_ALL) && !defined(__QNXNTO__)
-#  define ASIO_OS_DEF_AI_ALL AI_ALL
-# else
-#  define ASIO_OS_DEF_AI_ALL 0
-# endif
-# if defined(AI_ADDRCONFIG) && !defined(__QNXNTO__)
-#  define ASIO_OS_DEF_AI_ADDRCONFIG AI_ADDRCONFIG
-# else
-#  define ASIO_OS_DEF_AI_ADDRCONFIG 0
-# endif
-# if defined(IOV_MAX)
-const int max_iov_len = IOV_MAX;
-# else
-// POSIX platforms are not required to define IOV_MAX.
-const int max_iov_len = 16;
-# endif
-#endif
-const int custom_socket_option_level = 0xA5100000;
-const int enable_connection_aborted_option = 1;
-const int always_fail_option = 2;
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_SOCKET_TYPES_HPP
diff --git a/tools/sdk/include/asio/asio/detail/solaris_fenced_block.hpp b/tools/sdk/include/asio/asio/detail/solaris_fenced_block.hpp
deleted file mode 100644
index d48f6a374cd..00000000000
--- a/tools/sdk/include/asio/asio/detail/solaris_fenced_block.hpp
+++ /dev/null
@@ -1,62 +0,0 @@
-//
-// detail/solaris_fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_SOLARIS_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_SOLARIS_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(__sun)
-
-#include <atomic.h>
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class solaris_fenced_block
-  : private noncopyable
-{
-public:
-  enum half_t { half };
-  enum full_t { full };
-
-  // Constructor for a half fenced block.
-  explicit solaris_fenced_block(half_t)
-  {
-  }
-
-  // Constructor for a full fenced block.
-  explicit solaris_fenced_block(full_t)
-  {
-    membar_consumer();
-  }
-
-  // Destructor.
-  ~solaris_fenced_block()
-  {
-    membar_producer();
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(__sun)
-
-#endif // ASIO_DETAIL_SOLARIS_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/static_mutex.hpp b/tools/sdk/include/asio/asio/detail/static_mutex.hpp
deleted file mode 100644
index 8f2bc02a084..00000000000
--- a/tools/sdk/include/asio/asio/detail/static_mutex.hpp
+++ /dev/null
@@ -1,52 +0,0 @@
-//
-// detail/static_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STATIC_MUTEX_HPP
-#define ASIO_DETAIL_STATIC_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-# include "asio/detail/null_static_mutex.hpp"
-#elif defined(ASIO_WINDOWS)
-# include "asio/detail/win_static_mutex.hpp"
-#elif defined(ASIO_HAS_PTHREADS)
-# include "asio/detail/posix_static_mutex.hpp"
-#elif defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-# include "asio/detail/std_static_mutex.hpp"
-#else
-# error Only Windows and POSIX are supported!
-#endif
-
-namespace asio {
-namespace detail {
-
-#if !defined(ASIO_HAS_THREADS)
-typedef null_static_mutex static_mutex;
-# define ASIO_STATIC_MUTEX_INIT ASIO_NULL_STATIC_MUTEX_INIT
-#elif defined(ASIO_WINDOWS)
-typedef win_static_mutex static_mutex;
-# define ASIO_STATIC_MUTEX_INIT ASIO_WIN_STATIC_MUTEX_INIT
-#elif defined(ASIO_HAS_PTHREADS)
-typedef posix_static_mutex static_mutex;
-# define ASIO_STATIC_MUTEX_INIT ASIO_POSIX_STATIC_MUTEX_INIT
-#elif defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-typedef std_static_mutex static_mutex;
-# define ASIO_STATIC_MUTEX_INIT ASIO_STD_STATIC_MUTEX_INIT
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_STATIC_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/std_event.hpp b/tools/sdk/include/asio/asio/detail/std_event.hpp
deleted file mode 100644
index 5639ecdd432..00000000000
--- a/tools/sdk/include/asio/asio/detail/std_event.hpp
+++ /dev/null
@@ -1,176 +0,0 @@
-//
-// detail/std_event.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STD_EVENT_HPP
-#define ASIO_DETAIL_STD_EVENT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-
-#include <chrono>
-#include <condition_variable>
-#include "asio/detail/assert.hpp"
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class std_event
-  : private noncopyable
-{
-public:
-  // Constructor.
-  std_event()
-    : state_(0)
-  {
-  }
-
-  // Destructor.
-  ~std_event()
-  {
-  }
-
-  // Signal the event. (Retained for backward compatibility.)
-  template <typename Lock>
-  void signal(Lock& lock)
-  {
-    this->signal_all(lock);
-  }
-
-  // Signal all waiters.
-  template <typename Lock>
-  void signal_all(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    (void)lock;
-    state_ |= 1;
-    cond_.notify_all();
-  }
-
-  // Unlock the mutex and signal one waiter.
-  template <typename Lock>
-  void unlock_and_signal_one(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    state_ |= 1;
-    bool have_waiters = (state_ > 1);
-    lock.unlock();
-    if (have_waiters)
-      cond_.notify_one();
-  }
-
-  // If there's a waiter, unlock the mutex and signal it.
-  template <typename Lock>
-  bool maybe_unlock_and_signal_one(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    state_ |= 1;
-    if (state_ > 1)
-    {
-      lock.unlock();
-      cond_.notify_one();
-      return true;
-    }
-    return false;
-  }
-
-  // Reset the event.
-  template <typename Lock>
-  void clear(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    (void)lock;
-    state_ &= ~std::size_t(1);
-  }
-
-  // Wait for the event to become signalled.
-  template <typename Lock>
-  void wait(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    unique_lock_adapter u_lock(lock);
-    while ((state_ & 1) == 0)
-    {
-      waiter w(state_);
-      cond_.wait(u_lock.unique_lock_);
-    }
-  }
-
-  // Timed wait for the event to become signalled.
-  template <typename Lock>
-  bool wait_for_usec(Lock& lock, long usec)
-  {
-    ASIO_ASSERT(lock.locked());
-    unique_lock_adapter u_lock(lock);
-    if ((state_ & 1) == 0)
-    {
-      waiter w(state_);
-      cond_.wait_for(u_lock.unique_lock_, std::chrono::microseconds(usec));
-    }
-    return (state_ & 1) != 0;
-  }
-
-private:
-  // Helper class to temporarily adapt a scoped_lock into a unique_lock so that
-  // it can be passed to std::condition_variable::wait().
-  struct unique_lock_adapter
-  {
-    template <typename Lock>
-    explicit unique_lock_adapter(Lock& lock)
-      : unique_lock_(lock.mutex().mutex_, std::adopt_lock)
-    {
-    }
-
-    ~unique_lock_adapter()
-    {
-      unique_lock_.release();
-    }
-
-    std::unique_lock<std::mutex> unique_lock_;
-  };
-
-  // Helper to increment and decrement the state to track outstanding waiters.
-  class waiter
-  {
-  public:
-    explicit waiter(std::size_t& state)
-      : state_(state)
-    {
-      state_ += 2;
-    }
-
-    ~waiter()
-    {
-      state_ -= 2;
-    }
-
-  private:
-    std::size_t& state_;
-  };
-
-  std::condition_variable cond_;
-  std::size_t state_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-
-#endif // ASIO_DETAIL_STD_EVENT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/std_fenced_block.hpp b/tools/sdk/include/asio/asio/detail/std_fenced_block.hpp
deleted file mode 100644
index 0d8ade028e6..00000000000
--- a/tools/sdk/include/asio/asio/detail/std_fenced_block.hpp
+++ /dev/null
@@ -1,62 +0,0 @@
-//
-// detail/std_fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STD_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_STD_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_ATOMIC)
-
-#include <atomic>
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class std_fenced_block
-  : private noncopyable
-{
-public:
-  enum half_t { half };
-  enum full_t { full };
-
-  // Constructor for a half fenced block.
-  explicit std_fenced_block(half_t)
-  {
-  }
-
-  // Constructor for a full fenced block.
-  explicit std_fenced_block(full_t)
-  {
-    std::atomic_thread_fence(std::memory_order_acquire);
-  }
-
-  // Destructor.
-  ~std_fenced_block()
-  {
-    std::atomic_thread_fence(std::memory_order_release);
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_STD_ATOMIC)
-
-#endif // ASIO_DETAIL_STD_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/std_global.hpp b/tools/sdk/include/asio/asio/detail/std_global.hpp
deleted file mode 100644
index 0c5173e6bd7..00000000000
--- a/tools/sdk/include/asio/asio/detail/std_global.hpp
+++ /dev/null
@@ -1,70 +0,0 @@
-//
-// detail/std_global.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STD_GLOBAL_HPP
-#define ASIO_DETAIL_STD_GLOBAL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_CALL_ONCE)
-
-#include <exception>
-#include <mutex>
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-struct std_global_impl
-{
-  // Helper function to perform initialisation.
-  static void do_init()
-  {
-    instance_.ptr_ = new T;
-  }
-
-  // Destructor automatically cleans up the global.
-  ~std_global_impl()
-  {
-    delete ptr_;
-  }
-
-  static std::once_flag init_once_;
-  static std_global_impl instance_;
-  T* ptr_;
-};
-
-template <typename T>
-std::once_flag std_global_impl<T>::init_once_;
-
-template <typename T>
-std_global_impl<T> std_global_impl<T>::instance_;
-
-template <typename T>
-T& std_global()
-{
-  std::call_once(std_global_impl<T>::init_once_, &std_global_impl<T>::do_init);
-  return *std_global_impl<T>::instance_.ptr_;
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_STD_CALL_ONCE)
-
-#endif // ASIO_DETAIL_STD_GLOBAL_HPP
diff --git a/tools/sdk/include/asio/asio/detail/std_mutex.hpp b/tools/sdk/include/asio/asio/detail/std_mutex.hpp
deleted file mode 100644
index 159049e8c29..00000000000
--- a/tools/sdk/include/asio/asio/detail/std_mutex.hpp
+++ /dev/null
@@ -1,73 +0,0 @@
-//
-// detail/std_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STD_MUTEX_HPP
-#define ASIO_DETAIL_STD_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-
-#include <mutex>
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/scoped_lock.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class std_event;
-
-class std_mutex
-  : private noncopyable
-{
-public:
-  typedef asio::detail::scoped_lock<std_mutex> scoped_lock;
-
-  // Constructor.
-  std_mutex()
-  {
-  }
-
-  // Destructor.
-  ~std_mutex()
-  {
-  }
-
-  // Lock the mutex.
-  void lock()
-  {
-    mutex_.lock();
-  }
-
-  // Unlock the mutex.
-  void unlock()
-  {
-    mutex_.unlock();
-  }
-
-private:
-  friend class std_event;
-  std::mutex mutex_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-
-#endif // ASIO_DETAIL_STD_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/std_static_mutex.hpp b/tools/sdk/include/asio/asio/detail/std_static_mutex.hpp
deleted file mode 100644
index e9c9dc5ee3a..00000000000
--- a/tools/sdk/include/asio/asio/detail/std_static_mutex.hpp
+++ /dev/null
@@ -1,81 +0,0 @@
-//
-// detail/std_static_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STD_STATIC_MUTEX_HPP
-#define ASIO_DETAIL_STD_STATIC_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-
-#include <mutex>
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/scoped_lock.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class std_event;
-
-class std_static_mutex
-  : private noncopyable
-{
-public:
-  typedef asio::detail::scoped_lock<std_static_mutex> scoped_lock;
-
-  // Constructor.
-  std_static_mutex(int)
-  {
-  }
-
-  // Destructor.
-  ~std_static_mutex()
-  {
-  }
-
-  // Initialise the mutex.
-  void init()
-  {
-    // Nothing to do.
-  }
-
-  // Lock the mutex.
-  void lock()
-  {
-    mutex_.lock();
-  }
-
-  // Unlock the mutex.
-  void unlock()
-  {
-    mutex_.unlock();
-  }
-
-private:
-  friend class std_event;
-  std::mutex mutex_;
-};
-
-#define ASIO_STD_STATIC_MUTEX_INIT 0
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_STD_MUTEX_AND_CONDVAR)
-
-#endif // ASIO_DETAIL_STD_STATIC_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/std_thread.hpp b/tools/sdk/include/asio/asio/detail/std_thread.hpp
deleted file mode 100644
index a240308d8a0..00000000000
--- a/tools/sdk/include/asio/asio/detail/std_thread.hpp
+++ /dev/null
@@ -1,71 +0,0 @@
-//
-// detail/std_thread.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STD_THREAD_HPP
-#define ASIO_DETAIL_STD_THREAD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_THREAD)
-
-#include <thread>
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class std_thread
-  : private noncopyable
-{
-public:
-  // Constructor.
-  template <typename Function>
-  std_thread(Function f, unsigned int = 0)
-    : thread_(f)
-  {
-  }
-
-  // Destructor.
-  ~std_thread()
-  {
-    join();
-  }
-
-  // Wait for the thread to exit.
-  void join()
-  {
-    if (thread_.joinable())
-      thread_.join();
-  }
-
-  // Get number of CPUs.
-  static std::size_t hardware_concurrency()
-  {
-    return std::thread::hardware_concurrency();
-  }
-
-private:
-  std::thread thread_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_STD_THREAD)
-
-#endif // ASIO_DETAIL_STD_THREAD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/strand_executor_service.hpp b/tools/sdk/include/asio/asio/detail/strand_executor_service.hpp
deleted file mode 100644
index 67e84274ba2..00000000000
--- a/tools/sdk/include/asio/asio/detail/strand_executor_service.hpp
+++ /dev/null
@@ -1,142 +0,0 @@
-//
-// detail/strand_executor_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STRAND_EXECUTOR_SERVICE_HPP
-#define ASIO_DETAIL_STRAND_EXECUTOR_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/atomic_count.hpp"
-#include "asio/detail/executor_op.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/scheduler_operation.hpp"
-#include "asio/detail/scoped_ptr.hpp"
-#include "asio/execution_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Default service implementation for a strand.
-class strand_executor_service
-  : public execution_context_service_base<strand_executor_service>
-{
-public:
-  // The underlying implementation of a strand.
-  class strand_impl
-  {
-  public:
-    ASIO_DECL ~strand_impl();
-
-  private:
-    friend class strand_executor_service;
-
-    // Mutex to protect access to internal data.
-    mutex* mutex_;
-
-    // Indicates whether the strand is currently "locked" by a handler. This
-    // means that there is a handler upcall in progress, or that the strand
-    // itself has been scheduled in order to invoke some pending handlers.
-    bool locked_;
-
-    // Indicates that the strand has been shut down and will accept no further
-    // handlers.
-    bool shutdown_;
-
-    // The handlers that are waiting on the strand but should not be run until
-    // after the next time the strand is scheduled. This queue must only be
-    // modified while the mutex is locked.
-    op_queue<scheduler_operation> waiting_queue_;
-
-    // The handlers that are ready to be run. Logically speaking, these are the
-    // handlers that hold the strand's lock. The ready queue is only modified
-    // from within the strand and so may be accessed without locking the mutex.
-    op_queue<scheduler_operation> ready_queue_;
-
-    // Pointers to adjacent handle implementations in linked list.
-    strand_impl* next_;
-    strand_impl* prev_;
-
-    // The strand service in where the implementation is held.
-    strand_executor_service* service_;
-  };
-
-  typedef shared_ptr<strand_impl> implementation_type;
-
-  // Construct a new strand service for the specified context.
-  ASIO_DECL explicit strand_executor_service(execution_context& context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Create a new strand_executor implementation.
-  ASIO_DECL implementation_type create_implementation();
-
-  // Request invocation of the given function.
-  template <typename Executor, typename Function, typename Allocator>
-  static void dispatch(const implementation_type& impl, Executor& ex,
-      ASIO_MOVE_ARG(Function) function, const Allocator& a);
-
-  // Request invocation of the given function and return immediately.
-  template <typename Executor, typename Function, typename Allocator>
-  static void post(const implementation_type& impl, Executor& ex,
-      ASIO_MOVE_ARG(Function) function, const Allocator& a);
-
-  // Request invocation of the given function and return immediately.
-  template <typename Executor, typename Function, typename Allocator>
-  static void defer(const implementation_type& impl, Executor& ex,
-      ASIO_MOVE_ARG(Function) function, const Allocator& a);
-
-  // Determine whether the strand is running in the current thread.
-  ASIO_DECL static bool running_in_this_thread(
-      const implementation_type& impl);
-
-private:
-  friend class strand_impl;
-  template <typename Executor> class invoker;
-
-  // Adds a function to the strand. Returns true if it acquires the lock.
-  ASIO_DECL static bool enqueue(const implementation_type& impl,
-      scheduler_operation* op);
-
-  // Mutex to protect access to the service-wide state.
-  mutex mutex_;
-
-  // Number of mutexes shared between all strand objects.
-  enum { num_mutexes = 193 };
-
-  // Pool of mutexes.
-  scoped_ptr<mutex> mutexes_[num_mutexes];
-
-  // Extra value used when hashing to prevent recycled memory locations from
-  // getting the same mutex.
-  std::size_t salt_;
-
-  // The head of a linked list of all implementations.
-  strand_impl* impl_list_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/detail/impl/strand_executor_service.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/strand_executor_service.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_STRAND_EXECUTOR_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/strand_service.hpp b/tools/sdk/include/asio/asio/detail/strand_service.hpp
deleted file mode 100644
index edc14a0f7d5..00000000000
--- a/tools/sdk/include/asio/asio/detail/strand_service.hpp
+++ /dev/null
@@ -1,142 +0,0 @@
-//
-// detail/strand_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STRAND_SERVICE_HPP
-#define ASIO_DETAIL_STRAND_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/io_context.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/operation.hpp"
-#include "asio/detail/scoped_ptr.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Default service implementation for a strand.
-class strand_service
-  : public asio::detail::service_base<strand_service>
-{
-private:
-  // Helper class to re-post the strand on exit.
-  struct on_do_complete_exit;
-
-  // Helper class to re-post the strand on exit.
-  struct on_dispatch_exit;
-
-public:
-
-  // The underlying implementation of a strand.
-  class strand_impl
-    : public operation
-  {
-  public:
-    strand_impl();
-
-  private:
-    // Only this service will have access to the internal values.
-    friend class strand_service;
-    friend struct on_do_complete_exit;
-    friend struct on_dispatch_exit;
-
-    // Mutex to protect access to internal data.
-    asio::detail::mutex mutex_;
-
-    // Indicates whether the strand is currently "locked" by a handler. This
-    // means that there is a handler upcall in progress, or that the strand
-    // itself has been scheduled in order to invoke some pending handlers.
-    bool locked_;
-
-    // The handlers that are waiting on the strand but should not be run until
-    // after the next time the strand is scheduled. This queue must only be
-    // modified while the mutex is locked.
-    op_queue<operation> waiting_queue_;
-
-    // The handlers that are ready to be run. Logically speaking, these are the
-    // handlers that hold the strand's lock. The ready queue is only modified
-    // from within the strand and so may be accessed without locking the mutex.
-    op_queue<operation> ready_queue_;
-  };
-
-  typedef strand_impl* implementation_type;
-
-  // Construct a new strand service for the specified io_context.
-  ASIO_DECL explicit strand_service(asio::io_context& io_context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Construct a new strand implementation.
-  ASIO_DECL void construct(implementation_type& impl);
-
-  // Request the io_context to invoke the given handler.
-  template <typename Handler>
-  void dispatch(implementation_type& impl, Handler& handler);
-
-  // Request the io_context to invoke the given handler and return immediately.
-  template <typename Handler>
-  void post(implementation_type& impl, Handler& handler);
-
-  // Determine whether the strand is running in the current thread.
-  ASIO_DECL bool running_in_this_thread(
-      const implementation_type& impl) const;
-
-private:
-  // Helper function to dispatch a handler. Returns true if the handler should
-  // be dispatched immediately.
-  ASIO_DECL bool do_dispatch(implementation_type& impl, operation* op);
-
-  // Helper fiunction to post a handler.
-  ASIO_DECL void do_post(implementation_type& impl,
-      operation* op, bool is_continuation);
-
-  ASIO_DECL static void do_complete(void* owner,
-      operation* base, const asio::error_code& ec,
-      std::size_t bytes_transferred);
-
-  // The io_context implementation used to post completions.
-  io_context_impl& io_context_;
-
-  // Mutex to protect access to the array of implementations.
-  asio::detail::mutex mutex_;
-
-  // Number of implementations shared between all strand objects.
-#if defined(ASIO_STRAND_IMPLEMENTATIONS)
-  enum { num_implementations = ASIO_STRAND_IMPLEMENTATIONS };
-#else // defined(ASIO_STRAND_IMPLEMENTATIONS)
-  enum { num_implementations = 193 };
-#endif // defined(ASIO_STRAND_IMPLEMENTATIONS)
-
-  // Pool of implementations.
-  scoped_ptr<strand_impl> implementations_[num_implementations];
-
-  // Extra value used when hashing to prevent recycled memory locations from
-  // getting the same strand implementation.
-  std::size_t salt_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/detail/impl/strand_service.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/strand_service.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_STRAND_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/string_view.hpp b/tools/sdk/include/asio/asio/detail/string_view.hpp
deleted file mode 100644
index f09cebc2b64..00000000000
--- a/tools/sdk/include/asio/asio/detail/string_view.hpp
+++ /dev/null
@@ -1,47 +0,0 @@
-//
-// detail/string_view.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_STRING_VIEW_HPP
-#define ASIO_DETAIL_STRING_VIEW_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STRING_VIEW)
-
-#if defined(ASIO_HAS_STD_STRING_VIEW)
-# include <string_view>
-#elif defined(ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW)
-# include <experimental/string_view>
-#else // defined(ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW)
-# error ASIO_HAS_STRING_VIEW is set but no string_view is available
-#endif // defined(ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW)
-
-namespace asio {
-
-#if defined(ASIO_HAS_STD_STRING_VIEW)
-using std::basic_string_view;
-using std::string_view;
-#elif defined(ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW)
-using std::experimental::basic_string_view;
-using std::experimental::string_view;
-#endif // defined(ASIO_HAS_STD_EXPERIMENTAL_STRING_VIEW)
-
-} // namespace asio
-
-# define ASIO_STRING_VIEW_PARAM asio::string_view
-#else // defined(ASIO_HAS_STRING_VIEW)
-# define ASIO_STRING_VIEW_PARAM const std::string&
-#endif // defined(ASIO_HAS_STRING_VIEW)
-
-#endif // ASIO_DETAIL_STRING_VIEW_HPP
diff --git a/tools/sdk/include/asio/asio/detail/thread.hpp b/tools/sdk/include/asio/asio/detail/thread.hpp
deleted file mode 100644
index ea556dba65f..00000000000
--- a/tools/sdk/include/asio/asio/detail/thread.hpp
+++ /dev/null
@@ -1,60 +0,0 @@
-//
-// detail/thread.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_THREAD_HPP
-#define ASIO_DETAIL_THREAD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-# include "asio/detail/null_thread.hpp"
-#elif defined(ASIO_WINDOWS)
-# if defined(UNDER_CE)
-#  include "asio/detail/wince_thread.hpp"
-# elif defined(ASIO_WINDOWS_APP)
-#  include "asio/detail/winapp_thread.hpp"
-# else
-#  include "asio/detail/win_thread.hpp"
-# endif
-#elif defined(ASIO_HAS_PTHREADS)
-# include "asio/detail/posix_thread.hpp"
-#elif defined(ASIO_HAS_STD_THREAD)
-# include "asio/detail/std_thread.hpp"
-#else
-# error Only Windows, POSIX and std::thread are supported!
-#endif
-
-namespace asio {
-namespace detail {
-
-#if !defined(ASIO_HAS_THREADS)
-typedef null_thread thread;
-#elif defined(ASIO_WINDOWS)
-# if defined(UNDER_CE)
-typedef wince_thread thread;
-# elif defined(ASIO_WINDOWS_APP)
-typedef winapp_thread thread;
-# else
-typedef win_thread thread;
-# endif
-#elif defined(ASIO_HAS_PTHREADS)
-typedef posix_thread thread;
-#elif defined(ASIO_HAS_STD_THREAD)
-typedef std_thread thread;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_THREAD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/thread_context.hpp b/tools/sdk/include/asio/asio/detail/thread_context.hpp
deleted file mode 100644
index 88b4f311571..00000000000
--- a/tools/sdk/include/asio/asio/detail/thread_context.hpp
+++ /dev/null
@@ -1,42 +0,0 @@
-//
-// detail/thread_context.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_THREAD_CONTEXT_HPP
-#define ASIO_DETAIL_THREAD_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include <climits>
-#include <cstddef>
-#include "asio/detail/call_stack.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class thread_info_base;
-
-// Base class for things that manage threads (scheduler, win_iocp_io_context).
-class thread_context
-{
-public:
-  // Per-thread call stack to track the state of each thread in the context.
-  typedef call_stack<thread_context, thread_info_base> thread_call_stack;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_THREAD_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/thread_group.hpp b/tools/sdk/include/asio/asio/detail/thread_group.hpp
deleted file mode 100644
index 1e400b03737..00000000000
--- a/tools/sdk/include/asio/asio/detail/thread_group.hpp
+++ /dev/null
@@ -1,89 +0,0 @@
-//
-// detail/thread_group.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_THREAD_GROUP_HPP
-#define ASIO_DETAIL_THREAD_GROUP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/scoped_ptr.hpp"
-#include "asio/detail/thread.hpp"
-
-namespace asio {
-namespace detail {
-
-class thread_group
-{
-public:
-  // Constructor initialises an empty thread group.
-  thread_group()
-    : first_(0)
-  {
-  }
-
-  // Destructor joins any remaining threads in the group.
-  ~thread_group()
-  {
-    join();
-  }
-
-  // Create a new thread in the group.
-  template <typename Function>
-  void create_thread(Function f)
-  {
-    first_ = new item(f, first_);
-  }
-
-  // Create new threads in the group.
-  template <typename Function>
-  void create_threads(Function f, std::size_t num_threads)
-  {
-    for (std::size_t i = 0; i < num_threads; ++i)
-      create_thread(f);
-  }
-
-  // Wait for all threads in the group to exit.
-  void join()
-  {
-    while (first_)
-    {
-      first_->thread_.join();
-      item* tmp = first_;
-      first_ = first_->next_;
-      delete tmp;
-    }
-  }
-
-private:
-  // Structure used to track a single thread in the group.
-  struct item
-  {
-    template <typename Function>
-    explicit item(Function f, item* next)
-      : thread_(f),
-        next_(next)
-    {
-    }
-
-    asio::detail::thread thread_;
-    item* next_;
-  };
-
-  // The first thread in the group.
-  item* first_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_THREAD_GROUP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/thread_info_base.hpp b/tools/sdk/include/asio/asio/detail/thread_info_base.hpp
deleted file mode 100644
index 1b2220745b2..00000000000
--- a/tools/sdk/include/asio/asio/detail/thread_info_base.hpp
+++ /dev/null
@@ -1,121 +0,0 @@
-//
-// detail/thread_info_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_THREAD_INFO_BASE_HPP
-#define ASIO_DETAIL_THREAD_INFO_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include <climits>
-#include <cstddef>
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class thread_info_base
-  : private noncopyable
-{
-public:
-  struct default_tag
-  {
-    enum { mem_index = 0 };
-  };
-
-  struct awaitee_tag
-  {
-    enum { mem_index = 1 };
-  };
-
-  thread_info_base()
-  {
-    for (int i = 0; i < max_mem_index; ++i)
-      reusable_memory_[i] = 0;
-  }
-
-  ~thread_info_base()
-  {
-    for (int i = 0; i < max_mem_index; ++i)
-      if (reusable_memory_[i])
-        ::operator delete(reusable_memory_[i]);
-  }
-
-  static void* allocate(thread_info_base* this_thread, std::size_t size)
-  {
-    return allocate(default_tag(), this_thread, size);
-  }
-
-  static void deallocate(thread_info_base* this_thread,
-      void* pointer, std::size_t size)
-  {
-    deallocate(default_tag(), this_thread, pointer, size);
-  }
-
-  template <typename Purpose>
-  static void* allocate(Purpose, thread_info_base* this_thread,
-      std::size_t size)
-  {
-    std::size_t chunks = (size + chunk_size - 1) / chunk_size;
-
-    if (this_thread && this_thread->reusable_memory_[Purpose::mem_index])
-    {
-      void* const pointer = this_thread->reusable_memory_[Purpose::mem_index];
-      this_thread->reusable_memory_[Purpose::mem_index] = 0;
-
-      unsigned char* const mem = static_cast<unsigned char*>(pointer);
-      if (static_cast<std::size_t>(mem[0]) >= chunks)
-      {
-        mem[size] = mem[0];
-        return pointer;
-      }
-
-      ::operator delete(pointer);
-    }
-
-    void* const pointer = ::operator new(chunks * chunk_size + 1);
-    unsigned char* const mem = static_cast<unsigned char*>(pointer);
-    mem[size] = (chunks <= UCHAR_MAX) ? static_cast<unsigned char>(chunks) : 0;
-    return pointer;
-  }
-
-  template <typename Purpose>
-  static void deallocate(Purpose, thread_info_base* this_thread,
-      void* pointer, std::size_t size)
-  {
-    if (size <= chunk_size * UCHAR_MAX)
-    {
-      if (this_thread && this_thread->reusable_memory_[Purpose::mem_index] == 0)
-      {
-        unsigned char* const mem = static_cast<unsigned char*>(pointer);
-        mem[0] = mem[size];
-        this_thread->reusable_memory_[Purpose::mem_index] = pointer;
-        return;
-      }
-    }
-
-    ::operator delete(pointer);
-  }
-
-private:
-  enum { chunk_size = 4 };
-  enum { max_mem_index = 2 };
-  void* reusable_memory_[max_mem_index];
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_THREAD_INFO_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/throw_error.hpp b/tools/sdk/include/asio/asio/detail/throw_error.hpp
deleted file mode 100644
index 5dd87855aad..00000000000
--- a/tools/sdk/include/asio/asio/detail/throw_error.hpp
+++ /dev/null
@@ -1,53 +0,0 @@
-//
-// detail/throw_error.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_THROW_ERROR_HPP
-#define ASIO_DETAIL_THROW_ERROR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/error_code.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-ASIO_DECL void do_throw_error(const asio::error_code& err);
-
-ASIO_DECL void do_throw_error(const asio::error_code& err,
-    const char* location);
-
-inline void throw_error(const asio::error_code& err)
-{
-  if (err)
-    do_throw_error(err);
-}
-
-inline void throw_error(const asio::error_code& err,
-    const char* location)
-{
-  if (err)
-    do_throw_error(err, location);
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/throw_error.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_THROW_ERROR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/throw_exception.hpp b/tools/sdk/include/asio/asio/detail/throw_exception.hpp
deleted file mode 100644
index f9f7bfb9f17..00000000000
--- a/tools/sdk/include/asio/asio/detail/throw_exception.hpp
+++ /dev/null
@@ -1,51 +0,0 @@
-//
-// detail/throw_exception.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_THROW_EXCEPTION_HPP
-#define ASIO_DETAIL_THROW_EXCEPTION_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_BOOST_THROW_EXCEPTION)
-# include <boost/throw_exception.hpp>
-#endif // defined(ASIO_BOOST_THROW_EXCEPTION)
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_HAS_BOOST_THROW_EXCEPTION)
-using boost::throw_exception;
-#else // defined(ASIO_HAS_BOOST_THROW_EXCEPTION)
-
-// Declare the throw_exception function for all targets.
-template <typename Exception>
-void throw_exception(const Exception& e);
-
-// Only define the throw_exception function when exceptions are enabled.
-// Otherwise, it is up to the application to provide a definition of this
-// function.
-# if !defined(ASIO_NO_EXCEPTIONS)
-template <typename Exception>
-void throw_exception(const Exception& e)
-{
-  throw e;
-}
-# endif // !defined(ASIO_NO_EXCEPTIONS)
-
-#endif // defined(ASIO_HAS_BOOST_THROW_EXCEPTION)
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_THROW_EXCEPTION_HPP
diff --git a/tools/sdk/include/asio/asio/detail/timer_queue.hpp b/tools/sdk/include/asio/asio/detail/timer_queue.hpp
deleted file mode 100644
index 380e7791eb9..00000000000
--- a/tools/sdk/include/asio/asio/detail/timer_queue.hpp
+++ /dev/null
@@ -1,358 +0,0 @@
-//
-// detail/timer_queue.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_TIMER_QUEUE_HPP
-#define ASIO_DETAIL_TIMER_QUEUE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <vector>
-#include "asio/detail/cstdint.hpp"
-#include "asio/detail/date_time_fwd.hpp"
-#include "asio/detail/limits.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/timer_queue_base.hpp"
-#include "asio/detail/wait_op.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Time_Traits>
-class timer_queue
-  : public timer_queue_base
-{
-public:
-  // The time type.
-  typedef typename Time_Traits::time_type time_type;
-
-  // The duration type.
-  typedef typename Time_Traits::duration_type duration_type;
-
-  // Per-timer data.
-  class per_timer_data
-  {
-  public:
-    per_timer_data() :
-      heap_index_((std::numeric_limits<std::size_t>::max)()),
-      next_(0), prev_(0)
-    {
-    }
-
-  private:
-    friend class timer_queue;
-
-    // The operations waiting on the timer.
-    op_queue<wait_op> op_queue_;
-
-    // The index of the timer in the heap.
-    std::size_t heap_index_;
-
-    // Pointers to adjacent timers in a linked list.
-    per_timer_data* next_;
-    per_timer_data* prev_;
-  };
-
-  // Constructor.
-  timer_queue()
-    : timers_(),
-      heap_()
-  {
-  }
-
-  // Add a new timer to the queue. Returns true if this is the timer that is
-  // earliest in the queue, in which case the reactor's event demultiplexing
-  // function call may need to be interrupted and restarted.
-  bool enqueue_timer(const time_type& time, per_timer_data& timer, wait_op* op)
-  {
-    // Enqueue the timer object.
-    if (timer.prev_ == 0 && &timer != timers_)
-    {
-      if (this->is_positive_infinity(time))
-      {
-        // No heap entry is required for timers that never expire.
-        timer.heap_index_ = (std::numeric_limits<std::size_t>::max)();
-      }
-      else
-      {
-        // Put the new timer at the correct position in the heap. This is done
-        // first since push_back() can throw due to allocation failure.
-        timer.heap_index_ = heap_.size();
-        heap_entry entry = { time, &timer };
-        heap_.push_back(entry);
-        up_heap(heap_.size() - 1);
-      }
-
-      // Insert the new timer into the linked list of active timers.
-      timer.next_ = timers_;
-      timer.prev_ = 0;
-      if (timers_)
-        timers_->prev_ = &timer;
-      timers_ = &timer;
-    }
-
-    // Enqueue the individual timer operation.
-    timer.op_queue_.push(op);
-
-    // Interrupt reactor only if newly added timer is first to expire.
-    return timer.heap_index_ == 0 && timer.op_queue_.front() == op;
-  }
-
-  // Whether there are no timers in the queue.
-  virtual bool empty() const
-  {
-    return timers_ == 0;
-  }
-
-  // Get the time for the timer that is earliest in the queue.
-  virtual long wait_duration_msec(long max_duration) const
-  {
-    if (heap_.empty())
-      return max_duration;
-
-    return this->to_msec(
-        Time_Traits::to_posix_duration(
-          Time_Traits::subtract(heap_[0].time_, Time_Traits::now())),
-        max_duration);
-  }
-
-  // Get the time for the timer that is earliest in the queue.
-  virtual long wait_duration_usec(long max_duration) const
-  {
-    if (heap_.empty())
-      return max_duration;
-
-    return this->to_usec(
-        Time_Traits::to_posix_duration(
-          Time_Traits::subtract(heap_[0].time_, Time_Traits::now())),
-        max_duration);
-  }
-
-  // Dequeue all timers not later than the current time.
-  virtual void get_ready_timers(op_queue<operation>& ops)
-  {
-    if (!heap_.empty())
-    {
-      const time_type now = Time_Traits::now();
-      while (!heap_.empty() && !Time_Traits::less_than(now, heap_[0].time_))
-      {
-        per_timer_data* timer = heap_[0].timer_;
-        ops.push(timer->op_queue_);
-        remove_timer(*timer);
-      }
-    }
-  }
-
-  // Dequeue all timers.
-  virtual void get_all_timers(op_queue<operation>& ops)
-  {
-    while (timers_)
-    {
-      per_timer_data* timer = timers_;
-      timers_ = timers_->next_;
-      ops.push(timer->op_queue_);
-      timer->next_ = 0;
-      timer->prev_ = 0;
-    }
-
-    heap_.clear();
-  }
-
-  // Cancel and dequeue operations for the given timer.
-  std::size_t cancel_timer(per_timer_data& timer, op_queue<operation>& ops,
-      std::size_t max_cancelled = (std::numeric_limits<std::size_t>::max)())
-  {
-    std::size_t num_cancelled = 0;
-    if (timer.prev_ != 0 || &timer == timers_)
-    {
-      while (wait_op* op = (num_cancelled != max_cancelled)
-          ? timer.op_queue_.front() : 0)
-      {
-        op->ec_ = asio::error::operation_aborted;
-        timer.op_queue_.pop();
-        ops.push(op);
-        ++num_cancelled;
-      }
-      if (timer.op_queue_.empty())
-        remove_timer(timer);
-    }
-    return num_cancelled;
-  }
-
-  // Move operations from one timer to another, empty timer.
-  void move_timer(per_timer_data& target, per_timer_data& source)
-  {
-    target.op_queue_.push(source.op_queue_);
-
-    target.heap_index_ = source.heap_index_;
-    source.heap_index_ = (std::numeric_limits<std::size_t>::max)();
-
-    if (target.heap_index_ < heap_.size())
-      heap_[target.heap_index_].timer_ = &target;
-
-    if (timers_ == &source)
-      timers_ = &target;
-    if (source.prev_)
-      source.prev_->next_ = &target;
-    if (source.next_)
-      source.next_->prev_= &target;
-    target.next_ = source.next_;
-    target.prev_ = source.prev_;
-    source.next_ = 0;
-    source.prev_ = 0;
-  }
-
-private:
-  // Move the item at the given index up the heap to its correct position.
-  void up_heap(std::size_t index)
-  {
-    while (index > 0)
-    {
-      std::size_t parent = (index - 1) / 2;
-      if (!Time_Traits::less_than(heap_[index].time_, heap_[parent].time_))
-        break;
-      swap_heap(index, parent);
-      index = parent;
-    }
-  }
-
-  // Move the item at the given index down the heap to its correct position.
-  void down_heap(std::size_t index)
-  {
-    std::size_t child = index * 2 + 1;
-    while (child < heap_.size())
-    {
-      std::size_t min_child = (child + 1 == heap_.size()
-          || Time_Traits::less_than(
-            heap_[child].time_, heap_[child + 1].time_))
-        ? child : child + 1;
-      if (Time_Traits::less_than(heap_[index].time_, heap_[min_child].time_))
-        break;
-      swap_heap(index, min_child);
-      index = min_child;
-      child = index * 2 + 1;
-    }
-  }
-
-  // Swap two entries in the heap.
-  void swap_heap(std::size_t index1, std::size_t index2)
-  {
-    heap_entry tmp = heap_[index1];
-    heap_[index1] = heap_[index2];
-    heap_[index2] = tmp;
-    heap_[index1].timer_->heap_index_ = index1;
-    heap_[index2].timer_->heap_index_ = index2;
-  }
-
-  // Remove a timer from the heap and list of timers.
-  void remove_timer(per_timer_data& timer)
-  {
-    // Remove the timer from the heap.
-    std::size_t index = timer.heap_index_;
-    if (!heap_.empty() && index < heap_.size())
-    {
-      if (index == heap_.size() - 1)
-      {
-        heap_.pop_back();
-      }
-      else
-      {
-        swap_heap(index, heap_.size() - 1);
-        heap_.pop_back();
-        if (index > 0 && Time_Traits::less_than(
-              heap_[index].time_, heap_[(index - 1) / 2].time_))
-          up_heap(index);
-        else
-          down_heap(index);
-      }
-    }
-
-    // Remove the timer from the linked list of active timers.
-    if (timers_ == &timer)
-      timers_ = timer.next_;
-    if (timer.prev_)
-      timer.prev_->next_ = timer.next_;
-    if (timer.next_)
-      timer.next_->prev_= timer.prev_;
-    timer.next_ = 0;
-    timer.prev_ = 0;
-  }
-
-  // Determine if the specified absolute time is positive infinity.
-  template <typename Time_Type>
-  static bool is_positive_infinity(const Time_Type&)
-  {
-    return false;
-  }
-
-  // Determine if the specified absolute time is positive infinity.
-  template <typename T, typename TimeSystem>
-  static bool is_positive_infinity(
-      const boost::date_time::base_time<T, TimeSystem>& time)
-  {
-    return time.is_pos_infinity();
-  }
-
-  // Helper function to convert a duration into milliseconds.
-  template <typename Duration>
-  long to_msec(const Duration& d, long max_duration) const
-  {
-    if (d.ticks() <= 0)
-      return 0;
-    int64_t msec = d.total_milliseconds();
-    if (msec == 0)
-      return 1;
-    if (msec > max_duration)
-      return max_duration;
-    return static_cast<long>(msec);
-  }
-
-  // Helper function to convert a duration into microseconds.
-  template <typename Duration>
-  long to_usec(const Duration& d, long max_duration) const
-  {
-    if (d.ticks() <= 0)
-      return 0;
-    int64_t usec = d.total_microseconds();
-    if (usec == 0)
-      return 1;
-    if (usec > max_duration)
-      return max_duration;
-    return static_cast<long>(usec);
-  }
-
-  // The head of a linked list of all active timers.
-  per_timer_data* timers_;
-
-  struct heap_entry
-  {
-    // The time when the timer should fire.
-    time_type time_;
-
-    // The associated timer with enqueued operations.
-    per_timer_data* timer_;
-  };
-
-  // The heap of timers, with the earliest timer at the front.
-  std::vector<heap_entry> heap_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_TIMER_QUEUE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/timer_queue_base.hpp b/tools/sdk/include/asio/asio/detail/timer_queue_base.hpp
deleted file mode 100644
index 4af995f237c..00000000000
--- a/tools/sdk/include/asio/asio/detail/timer_queue_base.hpp
+++ /dev/null
@@ -1,68 +0,0 @@
-//
-// detail/timer_queue_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_TIMER_QUEUE_BASE_HPP
-#define ASIO_DETAIL_TIMER_QUEUE_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class timer_queue_base
-  : private noncopyable
-{
-public:
-  // Constructor.
-  timer_queue_base() : next_(0) {}
-
-  // Destructor.
-  virtual ~timer_queue_base() {}
-
-  // Whether there are no timers in the queue.
-  virtual bool empty() const = 0;
-
-  // Get the time to wait until the next timer.
-  virtual long wait_duration_msec(long max_duration) const = 0;
-
-  // Get the time to wait until the next timer.
-  virtual long wait_duration_usec(long max_duration) const = 0;
-
-  // Dequeue all ready timers.
-  virtual void get_ready_timers(op_queue<operation>& ops) = 0;
-
-  // Dequeue all timers.
-  virtual void get_all_timers(op_queue<operation>& ops) = 0;
-
-private:
-  friend class timer_queue_set;
-
-  // Next timer queue in the set.
-  timer_queue_base* next_;
-};
-
-template <typename Time_Traits>
-class timer_queue;
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_TIMER_QUEUE_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/timer_queue_ptime.hpp b/tools/sdk/include/asio/asio/detail/timer_queue_ptime.hpp
deleted file mode 100644
index 84e83385e69..00000000000
--- a/tools/sdk/include/asio/asio/detail/timer_queue_ptime.hpp
+++ /dev/null
@@ -1,99 +0,0 @@
-//
-// detail/timer_queue_ptime.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_TIMER_QUEUE_PTIME_HPP
-#define ASIO_DETAIL_TIMER_QUEUE_PTIME_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME)
-
-#include "asio/time_traits.hpp"
-#include "asio/detail/timer_queue.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-struct forwarding_posix_time_traits : time_traits<boost::posix_time::ptime> {};
-
-// Template specialisation for the commonly used instantation.
-template <>
-class timer_queue<time_traits<boost::posix_time::ptime> >
-  : public timer_queue_base
-{
-public:
-  // The time type.
-  typedef boost::posix_time::ptime time_type;
-
-  // The duration type.
-  typedef boost::posix_time::time_duration duration_type;
-
-  // Per-timer data.
-  typedef timer_queue<forwarding_posix_time_traits>::per_timer_data
-    per_timer_data;
-
-  // Constructor.
-  ASIO_DECL timer_queue();
-
-  // Destructor.
-  ASIO_DECL virtual ~timer_queue();
-
-  // Add a new timer to the queue. Returns true if this is the timer that is
-  // earliest in the queue, in which case the reactor's event demultiplexing
-  // function call may need to be interrupted and restarted.
-  ASIO_DECL bool enqueue_timer(const time_type& time,
-      per_timer_data& timer, wait_op* op);
-
-  // Whether there are no timers in the queue.
-  ASIO_DECL virtual bool empty() const;
-
-  // Get the time for the timer that is earliest in the queue.
-  ASIO_DECL virtual long wait_duration_msec(long max_duration) const;
-
-  // Get the time for the timer that is earliest in the queue.
-  ASIO_DECL virtual long wait_duration_usec(long max_duration) const;
-
-  // Dequeue all timers not later than the current time.
-  ASIO_DECL virtual void get_ready_timers(op_queue<operation>& ops);
-
-  // Dequeue all timers.
-  ASIO_DECL virtual void get_all_timers(op_queue<operation>& ops);
-
-  // Cancel and dequeue operations for the given timer.
-  ASIO_DECL std::size_t cancel_timer(
-      per_timer_data& timer, op_queue<operation>& ops,
-      std::size_t max_cancelled = (std::numeric_limits<std::size_t>::max)());
-
-  // Move operations from one timer to another, empty timer.
-  ASIO_DECL void move_timer(per_timer_data& target,
-      per_timer_data& source);
-
-private:
-  timer_queue<forwarding_posix_time_traits> impl_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/timer_queue_ptime.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-
-#endif // ASIO_DETAIL_TIMER_QUEUE_PTIME_HPP
diff --git a/tools/sdk/include/asio/asio/detail/timer_queue_set.hpp b/tools/sdk/include/asio/asio/detail/timer_queue_set.hpp
deleted file mode 100644
index 0ea372ae5ad..00000000000
--- a/tools/sdk/include/asio/asio/detail/timer_queue_set.hpp
+++ /dev/null
@@ -1,66 +0,0 @@
-//
-// detail/timer_queue_set.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_TIMER_QUEUE_SET_HPP
-#define ASIO_DETAIL_TIMER_QUEUE_SET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/timer_queue_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class timer_queue_set
-{
-public:
-  // Constructor.
-  ASIO_DECL timer_queue_set();
-
-  // Add a timer queue to the set.
-  ASIO_DECL void insert(timer_queue_base* q);
-
-  // Remove a timer queue from the set.
-  ASIO_DECL void erase(timer_queue_base* q);
-
-  // Determine whether all queues are empty.
-  ASIO_DECL bool all_empty() const;
-
-  // Get the wait duration in milliseconds.
-  ASIO_DECL long wait_duration_msec(long max_duration) const;
-
-  // Get the wait duration in microseconds.
-  ASIO_DECL long wait_duration_usec(long max_duration) const;
-
-  // Dequeue all ready timers.
-  ASIO_DECL void get_ready_timers(op_queue<operation>& ops);
-
-  // Dequeue all timers.
-  ASIO_DECL void get_all_timers(op_queue<operation>& ops);
-
-private:
-  timer_queue_base* first_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/timer_queue_set.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_DETAIL_TIMER_QUEUE_SET_HPP
diff --git a/tools/sdk/include/asio/asio/detail/timer_scheduler.hpp b/tools/sdk/include/asio/asio/detail/timer_scheduler.hpp
deleted file mode 100644
index b1f8df45d4f..00000000000
--- a/tools/sdk/include/asio/asio/detail/timer_scheduler.hpp
+++ /dev/null
@@ -1,35 +0,0 @@
-//
-// detail/timer_scheduler.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_TIMER_SCHEDULER_HPP
-#define ASIO_DETAIL_TIMER_SCHEDULER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/timer_scheduler_fwd.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/winrt_timer_scheduler.hpp"
-#elif defined(ASIO_HAS_IOCP)
-# include "asio/detail/win_iocp_io_context.hpp"
-#elif defined(ASIO_HAS_EPOLL)
-# include "asio/detail/epoll_reactor.hpp"
-#elif defined(ASIO_HAS_KQUEUE)
-# include "asio/detail/kqueue_reactor.hpp"
-#elif defined(ASIO_HAS_DEV_POLL)
-# include "asio/detail/dev_poll_reactor.hpp"
-#else
-# include "asio/detail/select_reactor.hpp"
-#endif
-
-#endif // ASIO_DETAIL_TIMER_SCHEDULER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/timer_scheduler_fwd.hpp b/tools/sdk/include/asio/asio/detail/timer_scheduler_fwd.hpp
deleted file mode 100644
index 80bae5034f8..00000000000
--- a/tools/sdk/include/asio/asio/detail/timer_scheduler_fwd.hpp
+++ /dev/null
@@ -1,40 +0,0 @@
-//
-// detail/timer_scheduler_fwd.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_TIMER_SCHEDULER_FWD_HPP
-#define ASIO_DETAIL_TIMER_SCHEDULER_FWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-typedef class winrt_timer_scheduler timer_scheduler;
-#elif defined(ASIO_HAS_IOCP)
-typedef class win_iocp_io_context timer_scheduler;
-#elif defined(ASIO_HAS_EPOLL)
-typedef class epoll_reactor timer_scheduler;
-#elif defined(ASIO_HAS_KQUEUE)
-typedef class kqueue_reactor timer_scheduler;
-#elif defined(ASIO_HAS_DEV_POLL)
-typedef class dev_poll_reactor timer_scheduler;
-#else
-typedef class select_reactor timer_scheduler;
-#endif
-
-} // namespace detail
-} // namespace asio
-
-#endif // ASIO_DETAIL_TIMER_SCHEDULER_FWD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/tss_ptr.hpp b/tools/sdk/include/asio/asio/detail/tss_ptr.hpp
deleted file mode 100644
index e628abe9dfa..00000000000
--- a/tools/sdk/include/asio/asio/detail/tss_ptr.hpp
+++ /dev/null
@@ -1,69 +0,0 @@
-//
-// detail/tss_ptr.hpp
-// ~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_TSS_PTR_HPP
-#define ASIO_DETAIL_TSS_PTR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_THREADS)
-# include "asio/detail/null_tss_ptr.hpp"
-#elif defined(ASIO_HAS_THREAD_KEYWORD_EXTENSION)
-# include "asio/detail/keyword_tss_ptr.hpp"
-#elif defined(ASIO_WINDOWS)
-# include "asio/detail/win_tss_ptr.hpp"
-#elif defined(ASIO_HAS_PTHREADS)
-# include "asio/detail/posix_tss_ptr.hpp"
-#else
-# error Only Windows and POSIX are supported!
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-class tss_ptr
-#if !defined(ASIO_HAS_THREADS)
-  : public null_tss_ptr<T>
-#elif defined(ASIO_HAS_THREAD_KEYWORD_EXTENSION)
-  : public keyword_tss_ptr<T>
-#elif defined(ASIO_WINDOWS)
-  : public win_tss_ptr<T>
-#elif defined(ASIO_HAS_PTHREADS)
-  : public posix_tss_ptr<T>
-#endif
-{
-public:
-  void operator=(T* value)
-  {
-#if !defined(ASIO_HAS_THREADS)
-    null_tss_ptr<T>::operator=(value);
-#elif defined(ASIO_HAS_THREAD_KEYWORD_EXTENSION)
-    keyword_tss_ptr<T>::operator=(value);
-#elif defined(ASIO_WINDOWS)
-    win_tss_ptr<T>::operator=(value);
-#elif defined(ASIO_HAS_PTHREADS)
-    posix_tss_ptr<T>::operator=(value);
-#endif
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_TSS_PTR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/type_traits.hpp b/tools/sdk/include/asio/asio/detail/type_traits.hpp
deleted file mode 100644
index edf09281a48..00000000000
--- a/tools/sdk/include/asio/asio/detail/type_traits.hpp
+++ /dev/null
@@ -1,86 +0,0 @@
-//
-// detail/type_traits.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_TYPE_TRAITS_HPP
-#define ASIO_DETAIL_TYPE_TRAITS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_TYPE_TRAITS)
-# include <type_traits>
-#else // defined(ASIO_HAS_TYPE_TRAITS)
-# include <boost/type_traits/add_const.hpp>
-# include <boost/type_traits/conditional.hpp>
-# include <boost/type_traits/decay.hpp>
-# include <boost/type_traits/integral_constant.hpp>
-# include <boost/type_traits/is_base_of.hpp>
-# include <boost/type_traits/is_class.hpp>
-# include <boost/type_traits/is_const.hpp>
-# include <boost/type_traits/is_convertible.hpp>
-# include <boost/type_traits/is_function.hpp>
-# include <boost/type_traits/is_same.hpp>
-# include <boost/type_traits/remove_pointer.hpp>
-# include <boost/type_traits/remove_reference.hpp>
-# include <boost/utility/enable_if.hpp>
-# include <boost/utility/result_of.hpp>
-#endif // defined(ASIO_HAS_TYPE_TRAITS)
-
-namespace asio {
-
-#if defined(ASIO_HAS_STD_TYPE_TRAITS)
-using std::add_const;
-using std::conditional;
-using std::decay;
-using std::enable_if;
-using std::false_type;
-using std::integral_constant;
-using std::is_base_of;
-using std::is_class;
-using std::is_const;
-using std::is_convertible;
-using std::is_function;
-using std::is_same;
-using std::remove_pointer;
-using std::remove_reference;
-#if defined(ASIO_HAS_STD_INVOKE_RESULT)
-template <typename> struct result_of;
-template <typename F, typename... Args>
-struct result_of<F(Args...)> : std::invoke_result<F, Args...> {};
-#else // defined(ASIO_HAS_STD_INVOKE_RESULT)
-using std::result_of;
-#endif // defined(ASIO_HAS_STD_INVOKE_RESULT)
-using std::true_type;
-#else // defined(ASIO_HAS_STD_TYPE_TRAITS)
-using boost::add_const;
-template <bool Condition, typename Type = void>
-struct enable_if : boost::enable_if_c<Condition, Type> {};
-using boost::conditional;
-using boost::decay;
-using boost::false_type;
-using boost::integral_constant;
-using boost::is_base_of;
-using boost::is_class;
-using boost::is_const;
-using boost::is_convertible;
-using boost::is_function;
-using boost::is_same;
-using boost::remove_pointer;
-using boost::remove_reference;
-using boost::result_of;
-using boost::true_type;
-#endif // defined(ASIO_HAS_STD_TYPE_TRAITS)
-
-} // namespace asio
-
-#endif // ASIO_DETAIL_TYPE_TRAITS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/variadic_templates.hpp b/tools/sdk/include/asio/asio/detail/variadic_templates.hpp
deleted file mode 100644
index d54eb4e4b10..00000000000
--- a/tools/sdk/include/asio/asio/detail/variadic_templates.hpp
+++ /dev/null
@@ -1,119 +0,0 @@
-//
-// detail/variadic_templates.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_VARIADIC_TEMPLATES_HPP
-#define ASIO_DETAIL_VARIADIC_TEMPLATES_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-# define ASIO_VARIADIC_TPARAMS(n) ASIO_VARIADIC_TPARAMS_##n
-
-# define ASIO_VARIADIC_TPARAMS_1 \
-  typename T1
-# define ASIO_VARIADIC_TPARAMS_2 \
-  typename T1, typename T2
-# define ASIO_VARIADIC_TPARAMS_3 \
-  typename T1, typename T2, typename T3
-# define ASIO_VARIADIC_TPARAMS_4 \
-  typename T1, typename T2, typename T3, typename T4
-# define ASIO_VARIADIC_TPARAMS_5 \
-  typename T1, typename T2, typename T3, typename T4, typename T5
-
-# define ASIO_VARIADIC_TARGS(n) ASIO_VARIADIC_TARGS_##n
-
-# define ASIO_VARIADIC_TARGS_1 T1
-# define ASIO_VARIADIC_TARGS_2 T1, T2
-# define ASIO_VARIADIC_TARGS_3 T1, T2, T3
-# define ASIO_VARIADIC_TARGS_4 T1, T2, T3, T4
-# define ASIO_VARIADIC_TARGS_5 T1, T2, T3, T4, T5
-
-# define ASIO_VARIADIC_BYVAL_PARAMS(n) \
-  ASIO_VARIADIC_BYVAL_PARAMS_##n
-
-# define ASIO_VARIADIC_BYVAL_PARAMS_1 T1 x1
-# define ASIO_VARIADIC_BYVAL_PARAMS_2 T1 x1, T2 x2
-# define ASIO_VARIADIC_BYVAL_PARAMS_3 T1 x1, T2 x2, T3 x3
-# define ASIO_VARIADIC_BYVAL_PARAMS_4 T1 x1, T2 x2, T3 x3, T4 x4
-# define ASIO_VARIADIC_BYVAL_PARAMS_5 T1 x1, T2 x2, T3 x3, T4 x4, T5 x5
-
-# define ASIO_VARIADIC_BYVAL_ARGS(n) \
-  ASIO_VARIADIC_BYVAL_ARGS_##n
-
-# define ASIO_VARIADIC_BYVAL_ARGS_1 x1
-# define ASIO_VARIADIC_BYVAL_ARGS_2 x1, x2
-# define ASIO_VARIADIC_BYVAL_ARGS_3 x1, x2, x3
-# define ASIO_VARIADIC_BYVAL_ARGS_4 x1, x2, x3, x4
-# define ASIO_VARIADIC_BYVAL_ARGS_5 x1, x2, x3, x4, x5
-
-# define ASIO_VARIADIC_MOVE_PARAMS(n) \
-  ASIO_VARIADIC_MOVE_PARAMS_##n
-
-# define ASIO_VARIADIC_MOVE_PARAMS_1 \
-  ASIO_MOVE_ARG(T1) x1
-# define ASIO_VARIADIC_MOVE_PARAMS_2 \
-  ASIO_MOVE_ARG(T1) x1, ASIO_MOVE_ARG(T2) x2
-# define ASIO_VARIADIC_MOVE_PARAMS_3 \
-  ASIO_MOVE_ARG(T1) x1, ASIO_MOVE_ARG(T2) x2, \
-  ASIO_MOVE_ARG(T3) x3
-# define ASIO_VARIADIC_MOVE_PARAMS_4 \
-  ASIO_MOVE_ARG(T1) x1, ASIO_MOVE_ARG(T2) x2, \
-  ASIO_MOVE_ARG(T3) x3, ASIO_MOVE_ARG(T4) x4
-# define ASIO_VARIADIC_MOVE_PARAMS_5 \
-  ASIO_MOVE_ARG(T1) x1, ASIO_MOVE_ARG(T2) x2, \
-  ASIO_MOVE_ARG(T3) x3, ASIO_MOVE_ARG(T4) x4, \
-  ASIO_MOVE_ARG(T5) x5
-
-# define ASIO_VARIADIC_MOVE_ARGS(n) \
-  ASIO_VARIADIC_MOVE_ARGS_##n
-
-# define ASIO_VARIADIC_MOVE_ARGS_1 \
-  ASIO_MOVE_CAST(T1)(x1)
-# define ASIO_VARIADIC_MOVE_ARGS_2 \
-  ASIO_MOVE_CAST(T1)(x1), ASIO_MOVE_CAST(T2)(x2)
-# define ASIO_VARIADIC_MOVE_ARGS_3 \
-  ASIO_MOVE_CAST(T1)(x1), ASIO_MOVE_CAST(T2)(x2), \
-  ASIO_MOVE_CAST(T3)(x3)
-# define ASIO_VARIADIC_MOVE_ARGS_4 \
-  ASIO_MOVE_CAST(T1)(x1), ASIO_MOVE_CAST(T2)(x2), \
-  ASIO_MOVE_CAST(T3)(x3), ASIO_MOVE_CAST(T4)(x4)
-# define ASIO_VARIADIC_MOVE_ARGS_5 \
-  ASIO_MOVE_CAST(T1)(x1), ASIO_MOVE_CAST(T2)(x2), \
-  ASIO_MOVE_CAST(T3)(x3), ASIO_MOVE_CAST(T4)(x4), \
-  ASIO_MOVE_CAST(T5)(x5)
-
-# define ASIO_VARIADIC_DECAY(n) \
-  ASIO_VARIADIC_DECAY_##n
-
-# define ASIO_VARIADIC_DECAY_1 \
-  typename decay<T1>::type
-# define ASIO_VARIADIC_DECAY_2 \
-  typename decay<T1>::type, typename decay<T2>::type
-# define ASIO_VARIADIC_DECAY_3 \
-  typename decay<T1>::type, typename decay<T2>::type, \
-  typename decay<T3>::type
-# define ASIO_VARIADIC_DECAY_4 \
-  typename decay<T1>::type, typename decay<T2>::type, \
-  typename decay<T3>::type, typename decay<T4>::type
-# define ASIO_VARIADIC_DECAY_5 \
-  typename decay<T1>::type, typename decay<T2>::type, \
-  typename decay<T3>::type, typename decay<T4>::type, \
-  typename decay<T5>::type
-
-# define ASIO_VARIADIC_GENERATE(m) m(1) m(2) m(3) m(4) m(5)
-
-#endif // !defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#endif // ASIO_DETAIL_VARIADIC_TEMPLATES_HPP
diff --git a/tools/sdk/include/asio/asio/detail/wait_handler.hpp b/tools/sdk/include/asio/asio/detail/wait_handler.hpp
deleted file mode 100644
index bd3dc24419f..00000000000
--- a/tools/sdk/include/asio/asio/detail/wait_handler.hpp
+++ /dev/null
@@ -1,85 +0,0 @@
-//
-// detail/wait_handler.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WAIT_HANDLER_HPP
-#define ASIO_DETAIL_WAIT_HANDLER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/wait_op.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class wait_handler : public wait_op
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(wait_handler);
-
-  wait_handler(Handler& h)
-    : wait_op(&wait_handler::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(h))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& /*ec*/,
-      std::size_t /*bytes_transferred*/)
-  {
-    // Take ownership of the handler object.
-    wait_handler* h(static_cast<wait_handler*>(base));
-    ptr p = { asio::detail::addressof(h->handler_), h, h };
-    handler_work<Handler> w(h->handler_);
-
-    ASIO_HANDLER_COMPLETION((*h));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder1<Handler, asio::error_code>
-      handler(h->handler_, h->ec_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_WAIT_HANDLER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/wait_op.hpp b/tools/sdk/include/asio/asio/detail/wait_op.hpp
deleted file mode 100644
index 1a3017baeef..00000000000
--- a/tools/sdk/include/asio/asio/detail/wait_op.hpp
+++ /dev/null
@@ -1,45 +0,0 @@
-//
-// detail/wait_op.hpp
-// ~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WAIT_OP_HPP
-#define ASIO_DETAIL_WAIT_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class wait_op
-  : public operation
-{
-public:
-  // The error code to be passed to the completion handler.
-  asio::error_code ec_;
-
-protected:
-  wait_op(func_type func)
-    : operation(func)
-  {
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_WAIT_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_event.hpp b/tools/sdk/include/asio/asio/detail/win_event.hpp
deleted file mode 100644
index 859cdee7b92..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_event.hpp
+++ /dev/null
@@ -1,151 +0,0 @@
-//
-// detail/win_event.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_EVENT_HPP
-#define ASIO_DETAIL_WIN_EVENT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS)
-
-#include "asio/detail/assert.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class win_event
-  : private noncopyable
-{
-public:
-  // Constructor.
-  ASIO_DECL win_event();
-
-  // Destructor.
-  ASIO_DECL ~win_event();
-
-  // Signal the event. (Retained for backward compatibility.)
-  template <typename Lock>
-  void signal(Lock& lock)
-  {
-    this->signal_all(lock);
-  }
-
-  // Signal all waiters.
-  template <typename Lock>
-  void signal_all(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    (void)lock;
-    state_ |= 1;
-    ::SetEvent(events_[0]);
-  }
-
-  // Unlock the mutex and signal one waiter.
-  template <typename Lock>
-  void unlock_and_signal_one(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    state_ |= 1;
-    bool have_waiters = (state_ > 1);
-    lock.unlock();
-    if (have_waiters)
-      ::SetEvent(events_[1]);
-  }
-
-  // If there's a waiter, unlock the mutex and signal it.
-  template <typename Lock>
-  bool maybe_unlock_and_signal_one(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    state_ |= 1;
-    if (state_ > 1)
-    {
-      lock.unlock();
-      ::SetEvent(events_[1]);
-      return true;
-    }
-    return false;
-  }
-
-  // Reset the event.
-  template <typename Lock>
-  void clear(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    (void)lock;
-    ::ResetEvent(events_[0]);
-    state_ &= ~std::size_t(1);
-  }
-
-  // Wait for the event to become signalled.
-  template <typename Lock>
-  void wait(Lock& lock)
-  {
-    ASIO_ASSERT(lock.locked());
-    while ((state_ & 1) == 0)
-    {
-      state_ += 2;
-      lock.unlock();
-#if defined(ASIO_WINDOWS_APP)
-      ::WaitForMultipleObjectsEx(2, events_, false, INFINITE, false);
-#else // defined(ASIO_WINDOWS_APP)
-      ::WaitForMultipleObjects(2, events_, false, INFINITE);
-#endif // defined(ASIO_WINDOWS_APP)
-      lock.lock();
-      state_ -= 2;
-    }
-  }
-
-  // Timed wait for the event to become signalled.
-  template <typename Lock>
-  bool wait_for_usec(Lock& lock, long usec)
-  {
-    ASIO_ASSERT(lock.locked());
-    if ((state_ & 1) == 0)
-    {
-      state_ += 2;
-      lock.unlock();
-      DWORD msec = usec > 0 ? (usec < 1000 ? 1 : usec / 1000) : 0;
-#if defined(ASIO_WINDOWS_APP)
-      ::WaitForMultipleObjectsEx(2, events_, false, msec, false);
-#else // defined(ASIO_WINDOWS_APP)
-      ::WaitForMultipleObjects(2, events_, false, msec);
-#endif // defined(ASIO_WINDOWS_APP)
-      lock.lock();
-      state_ -= 2;
-    }
-    return (state_ & 1) != 0;
-  }
-
-private:
-  HANDLE events_[2];
-  std::size_t state_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_event.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_WINDOWS)
-
-#endif // ASIO_DETAIL_WIN_EVENT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_fd_set_adapter.hpp b/tools/sdk/include/asio/asio/detail/win_fd_set_adapter.hpp
deleted file mode 100644
index 8d5e700e226..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_fd_set_adapter.hpp
+++ /dev/null
@@ -1,149 +0,0 @@
-//
-// detail/win_fd_set_adapter.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_FD_SET_ADAPTER_HPP
-#define ASIO_DETAIL_WIN_FD_SET_ADAPTER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/reactor_op_queue.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Adapts the FD_SET type to meet the Descriptor_Set concept's requirements.
-class win_fd_set_adapter : noncopyable
-{
-public:
-  enum { default_fd_set_size = 1024 };
-
-  win_fd_set_adapter()
-    : capacity_(default_fd_set_size),
-      max_descriptor_(invalid_socket)
-  {
-    fd_set_ = static_cast<win_fd_set*>(::operator new(
-          sizeof(win_fd_set) - sizeof(SOCKET)
-          + sizeof(SOCKET) * (capacity_)));
-    fd_set_->fd_count = 0;
-  }
-
-  ~win_fd_set_adapter()
-  {
-    ::operator delete(fd_set_);
-  }
-
-  void reset()
-  {
-    fd_set_->fd_count = 0;
-    max_descriptor_ = invalid_socket;
-  }
-
-  bool set(socket_type descriptor)
-  {
-    for (u_int i = 0; i < fd_set_->fd_count; ++i)
-      if (fd_set_->fd_array[i] == descriptor)
-        return true;
-
-    reserve(fd_set_->fd_count + 1);
-    fd_set_->fd_array[fd_set_->fd_count++] = descriptor;
-    return true;
-  }
-
-  void set(reactor_op_queue<socket_type>& operations, op_queue<operation>&)
-  {
-    reactor_op_queue<socket_type>::iterator i = operations.begin();
-    while (i != operations.end())
-    {
-      reactor_op_queue<socket_type>::iterator op_iter = i++;
-      reserve(fd_set_->fd_count + 1);
-      fd_set_->fd_array[fd_set_->fd_count++] = op_iter->first;
-    }
-  }
-
-  bool is_set(socket_type descriptor) const
-  {
-    return !!__WSAFDIsSet(descriptor,
-        const_cast<fd_set*>(reinterpret_cast<const fd_set*>(fd_set_)));
-  }
-
-  operator fd_set*()
-  {
-    return reinterpret_cast<fd_set*>(fd_set_);
-  }
-
-  socket_type max_descriptor() const
-  {
-    return max_descriptor_;
-  }
-
-  void perform(reactor_op_queue<socket_type>& operations,
-      op_queue<operation>& ops) const
-  {
-    for (u_int i = 0; i < fd_set_->fd_count; ++i)
-      operations.perform_operations(fd_set_->fd_array[i], ops);
-  }
-
-private:
-  // This structure is defined to be compatible with the Windows API fd_set
-  // structure, but without being dependent on the value of FD_SETSIZE. We use
-  // the "struct hack" to allow the number of descriptors to be varied at
-  // runtime.
-  struct win_fd_set
-  {
-    u_int fd_count;
-    SOCKET fd_array[1];
-  };
-
-  // Increase the fd_set_ capacity to at least the specified number of elements.
-  void reserve(u_int n)
-  {
-    if (n <= capacity_)
-      return;
-
-    u_int new_capacity = capacity_ + capacity_ / 2;
-    if (new_capacity < n)
-      new_capacity = n;
-
-    win_fd_set* new_fd_set = static_cast<win_fd_set*>(::operator new(
-          sizeof(win_fd_set) - sizeof(SOCKET)
-          + sizeof(SOCKET) * (new_capacity)));
-
-    new_fd_set->fd_count = fd_set_->fd_count;
-    for (u_int i = 0; i < fd_set_->fd_count; ++i)
-      new_fd_set->fd_array[i] = fd_set_->fd_array[i];
-
-    ::operator delete(fd_set_);
-    fd_set_ = new_fd_set;
-    capacity_ = new_capacity;
-  }
-
-  win_fd_set* fd_set_;
-  u_int capacity_;
-  socket_type max_descriptor_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-#endif // ASIO_DETAIL_WIN_FD_SET_ADAPTER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_fenced_block.hpp b/tools/sdk/include/asio/asio/detail/win_fenced_block.hpp
deleted file mode 100644
index 1ce6e13b9c1..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_fenced_block.hpp
+++ /dev/null
@@ -1,90 +0,0 @@
-//
-// detail/win_fenced_block.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_FENCED_BLOCK_HPP
-#define ASIO_DETAIL_WIN_FENCED_BLOCK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS) && !defined(UNDER_CE)
-
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/noncopyable.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class win_fenced_block
-  : private noncopyable
-{
-public:
-  enum half_t { half };
-  enum full_t { full };
-
-  // Constructor for a half fenced block.
-  explicit win_fenced_block(half_t)
-  {
-  }
-
-  // Constructor for a full fenced block.
-  explicit win_fenced_block(full_t)
-  {
-#if defined(__BORLANDC__)
-    LONG barrier = 0;
-    ::InterlockedExchange(&barrier, 1);
-#elif defined(ASIO_MSVC) \
-  && ((ASIO_MSVC < 1400) || !defined(MemoryBarrier))
-# if defined(_M_IX86)
-#  pragma warning(push)
-#  pragma warning(disable:4793)
-    LONG barrier;
-    __asm { xchg barrier, eax }
-#  pragma warning(pop)
-# endif // defined(_M_IX86)
-#else
-    MemoryBarrier();
-#endif
-  }
-
-  // Destructor.
-  ~win_fenced_block()
-  {
-#if defined(__BORLANDC__)
-    LONG barrier = 0;
-    ::InterlockedExchange(&barrier, 1);
-#elif defined(ASIO_MSVC) \
-  && ((ASIO_MSVC < 1400) || !defined(MemoryBarrier))
-# if defined(_M_IX86)
-#  pragma warning(push)
-#  pragma warning(disable:4793)
-    LONG barrier;
-    __asm { xchg barrier, eax }
-#  pragma warning(pop)
-# endif // defined(_M_IX86)
-#else
-    MemoryBarrier();
-#endif
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS) && !defined(UNDER_CE)
-
-#endif // ASIO_DETAIL_WIN_FENCED_BLOCK_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_global.hpp b/tools/sdk/include/asio/asio/detail/win_global.hpp
deleted file mode 100644
index 3b15a32d301..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_global.hpp
+++ /dev/null
@@ -1,73 +0,0 @@
-//
-// detail/win_global.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_GLOBAL_HPP
-#define ASIO_DETAIL_WIN_GLOBAL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/static_mutex.hpp"
-#include "asio/detail/tss_ptr.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename T>
-struct win_global_impl
-{
-  // Destructor automatically cleans up the global.
-  ~win_global_impl()
-  {
-    delete ptr_;
-  }
-
-  static win_global_impl instance_;
-  static static_mutex mutex_;
-  static T* ptr_;
-  static tss_ptr<T> tss_ptr_;
-};
-
-template <typename T>
-win_global_impl<T> win_global_impl<T>::instance_ = { 0 };
-
-template <typename T>
-static_mutex win_global_impl<T>::mutex_ = ASIO_STATIC_MUTEX_INIT;
-
-template <typename T>
-T* win_global_impl<T>::ptr_ = 0;
-
-template <typename T>
-tss_ptr<T> win_global_impl<T>::tss_ptr_;
-
-template <typename T>
-T& win_global()
-{
-  if (static_cast<T*>(win_global_impl<T>::tss_ptr_) == 0)
-  {
-    win_global_impl<T>::mutex_.init();
-    static_mutex::scoped_lock lock(win_global_impl<T>::mutex_);
-    win_global_impl<T>::ptr_ = new T;
-    win_global_impl<T>::tss_ptr_ = win_global_impl<T>::ptr_;
-  }
-
-  return *win_global_impl<T>::tss_ptr_;
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_WIN_GLOBAL_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_handle_read_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_handle_read_op.hpp
deleted file mode 100644
index 88e3f6c7b50..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_handle_read_op.hpp
+++ /dev/null
@@ -1,111 +0,0 @@
-//
-// detail/win_iocp_handle_read_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Rep Invariant Systems, Inc. (info@repinvariant.com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_HANDLE_READ_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_HANDLE_READ_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/error.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename MutableBufferSequence, typename Handler>
-class win_iocp_handle_read_op : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_handle_read_op);
-
-  win_iocp_handle_read_op(
-      const MutableBufferSequence& buffers, Handler& handler)
-    : operation(&win_iocp_handle_read_op::do_complete),
-      buffers_(buffers),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t bytes_transferred)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_handle_read_op* o(static_cast<win_iocp_handle_read_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    if (owner)
-    {
-      // Check whether buffers are still valid.
-      buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::validate(o->buffers_);
-    }
-#endif // defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-
-    // Map non-portable errors to their portable counterparts.
-    if (ec.value() == ERROR_HANDLE_EOF)
-      ec = asio::error::eof;
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, ec, bytes_transferred);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  MutableBufferSequence buffers_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_HANDLE_READ_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_handle_service.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_handle_service.hpp
deleted file mode 100644
index 849fe8f1883..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_handle_service.hpp
+++ /dev/null
@@ -1,323 +0,0 @@
-//
-// detail/win_iocp_handle_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Rep Invariant Systems, Inc. (info@repinvariant.com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_HANDLE_SERVICE_HPP
-#define ASIO_DETAIL_WIN_IOCP_HANDLE_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/cstdint.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/operation.hpp"
-#include "asio/detail/win_iocp_handle_read_op.hpp"
-#include "asio/detail/win_iocp_handle_write_op.hpp"
-#include "asio/detail/win_iocp_io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class win_iocp_handle_service :
-  public service_base<win_iocp_handle_service>
-{
-public:
-  // The native type of a stream handle.
-  typedef HANDLE native_handle_type;
-
-  // The implementation type of the stream handle.
-  class implementation_type
-  {
-  public:
-    // Default constructor.
-    implementation_type()
-      : handle_(INVALID_HANDLE_VALUE),
-        safe_cancellation_thread_id_(0),
-        next_(0),
-        prev_(0)
-    {
-    }
-
-  private:
-    // Only this service will have access to the internal values.
-    friend class win_iocp_handle_service;
-
-    // The native stream handle representation.
-    native_handle_type handle_;
-
-    // The ID of the thread from which it is safe to cancel asynchronous
-    // operations. 0 means no asynchronous operations have been started yet.
-    // ~0 means asynchronous operations have been started from more than one
-    // thread, and cancellation is not supported for the handle.
-    DWORD safe_cancellation_thread_id_;
-
-    // Pointers to adjacent handle implementations in linked list.
-    implementation_type* next_;
-    implementation_type* prev_;
-  };
-
-  ASIO_DECL win_iocp_handle_service(asio::io_context& io_context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Construct a new handle implementation.
-  ASIO_DECL void construct(implementation_type& impl);
-
-  // Move-construct a new handle implementation.
-  ASIO_DECL void move_construct(implementation_type& impl,
-      implementation_type& other_impl);
-
-  // Move-assign from another handle implementation.
-  ASIO_DECL void move_assign(implementation_type& impl,
-      win_iocp_handle_service& other_service,
-      implementation_type& other_impl);
-
-  // Destroy a handle implementation.
-  ASIO_DECL void destroy(implementation_type& impl);
-
-  // Assign a native handle to a handle implementation.
-  ASIO_DECL asio::error_code assign(implementation_type& impl,
-      const native_handle_type& handle, asio::error_code& ec);
-
-  // Determine whether the handle is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return impl.handle_ != INVALID_HANDLE_VALUE;
-  }
-
-  // Destroy a handle implementation.
-  ASIO_DECL asio::error_code close(implementation_type& impl,
-      asio::error_code& ec);
-
-  // Get the native handle representation.
-  native_handle_type native_handle(const implementation_type& impl) const
-  {
-    return impl.handle_;
-  }
-
-  // Cancel all operations associated with the handle.
-  ASIO_DECL asio::error_code cancel(implementation_type& impl,
-      asio::error_code& ec);
-
-  // Write the given data. Returns the number of bytes written.
-  template <typename ConstBufferSequence>
-  size_t write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    return write_some_at(impl, 0, buffers, ec);
-  }
-
-  // Write the given data at the specified offset. Returns the number of bytes
-  // written.
-  template <typename ConstBufferSequence>
-  size_t write_some_at(implementation_type& impl, uint64_t offset,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    asio::const_buffer buffer =
-      buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence>::first(buffers);
-
-    return do_write(impl, offset, buffer, ec);
-  }
-
-  // Start an asynchronous write. The data being written must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_handle_write_op<ConstBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(buffers, handler);
-
-    ASIO_HANDLER_CREATION((iocp_service_.context(), *p.p, "handle", &impl,
-          reinterpret_cast<uintmax_t>(impl.handle_), "async_write_some"));
-
-    start_write_op(impl, 0,
-        buffer_sequence_adapter<asio::const_buffer,
-          ConstBufferSequence>::first(buffers), p.p);
-    p.v = p.p = 0;
-  }
-
-  // Start an asynchronous write at a specified offset. The data being written
-  // must be valid for the lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_write_some_at(implementation_type& impl, uint64_t offset,
-      const ConstBufferSequence& buffers, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_handle_write_op<ConstBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(buffers, handler);
-
-    ASIO_HANDLER_CREATION((iocp_service_.context(), *p.p, "handle", &impl,
-          reinterpret_cast<uintmax_t>(impl.handle_), "async_write_some_at"));
-
-    start_write_op(impl, offset,
-        buffer_sequence_adapter<asio::const_buffer,
-          ConstBufferSequence>::first(buffers), p.p);
-    p.v = p.p = 0;
-  }
-
-  // Read some data. Returns the number of bytes received.
-  template <typename MutableBufferSequence>
-  size_t read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    return read_some_at(impl, 0, buffers, ec);
-  }
-
-  // Read some data at a specified offset. Returns the number of bytes received.
-  template <typename MutableBufferSequence>
-  size_t read_some_at(implementation_type& impl, uint64_t offset,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    asio::mutable_buffer buffer =
-      buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence>::first(buffers);
-
-    return do_read(impl, offset, buffer, ec);
-  }
-
-  // Start an asynchronous read. The buffer for the data being received must be
-  // valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_handle_read_op<MutableBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(buffers, handler);
-
-    ASIO_HANDLER_CREATION((iocp_service_.context(), *p.p, "handle", &impl,
-          reinterpret_cast<uintmax_t>(impl.handle_), "async_read_some"));
-
-    start_read_op(impl, 0,
-        buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::first(buffers), p.p);
-    p.v = p.p = 0;
-  }
-
-  // Start an asynchronous read at a specified offset. The buffer for the data
-  // being received must be valid for the lifetime of the asynchronous
-  // operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_read_some_at(implementation_type& impl, uint64_t offset,
-      const MutableBufferSequence& buffers, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_handle_read_op<MutableBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(buffers, handler);
-
-    ASIO_HANDLER_CREATION((iocp_service_.context(), *p.p, "handle", &impl,
-          reinterpret_cast<uintmax_t>(impl.handle_), "async_read_some_at"));
-
-    start_read_op(impl, offset,
-        buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::first(buffers), p.p);
-    p.v = p.p = 0;
-  }
-
-private:
-  // Prevent the use of the null_buffers type with this service.
-  size_t write_some(implementation_type& impl,
-      const null_buffers& buffers, asio::error_code& ec);
-  size_t write_some_at(implementation_type& impl, uint64_t offset,
-      const null_buffers& buffers, asio::error_code& ec);
-  template <typename Handler>
-  void async_write_some(implementation_type& impl,
-      const null_buffers& buffers, Handler& handler);
-  template <typename Handler>
-  void async_write_some_at(implementation_type& impl, uint64_t offset,
-      const null_buffers& buffers, Handler& handler);
-  size_t read_some(implementation_type& impl,
-      const null_buffers& buffers, asio::error_code& ec);
-  size_t read_some_at(implementation_type& impl, uint64_t offset,
-      const null_buffers& buffers, asio::error_code& ec);
-  template <typename Handler>
-  void async_read_some(implementation_type& impl,
-      const null_buffers& buffers, Handler& handler);
-  template <typename Handler>
-  void async_read_some_at(implementation_type& impl, uint64_t offset,
-      const null_buffers& buffers, Handler& handler);
-
-  // Helper class for waiting for synchronous operations to complete.
-  class overlapped_wrapper;
-
-  // Helper function to perform a synchronous write operation.
-  ASIO_DECL size_t do_write(implementation_type& impl,
-      uint64_t offset, const asio::const_buffer& buffer,
-      asio::error_code& ec);
-
-  // Helper function to start a write operation.
-  ASIO_DECL void start_write_op(implementation_type& impl,
-      uint64_t offset, const asio::const_buffer& buffer,
-      operation* op);
-
-  // Helper function to perform a synchronous write operation.
-  ASIO_DECL size_t do_read(implementation_type& impl,
-      uint64_t offset, const asio::mutable_buffer& buffer,
-      asio::error_code& ec);
-
-  // Helper function to start a read operation.
-  ASIO_DECL void start_read_op(implementation_type& impl,
-      uint64_t offset, const asio::mutable_buffer& buffer,
-      operation* op);
-
-  // Update the ID of the thread from which cancellation is safe.
-  ASIO_DECL void update_cancellation_thread_id(implementation_type& impl);
-
-  // Helper function to close a handle when the associated object is being
-  // destroyed.
-  ASIO_DECL void close_for_destruction(implementation_type& impl);
-
-  // The IOCP service used for running asynchronous operations and dispatching
-  // handlers.
-  win_iocp_io_context& iocp_service_;
-
-  // Mutex to protect access to the linked list of implementations.
-  mutex mutex_;
-
-  // The head of a linked list of all implementations.
-  implementation_type* impl_list_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_iocp_handle_service.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_HANDLE_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_handle_write_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_handle_write_op.hpp
deleted file mode 100644
index d7bb9443a7c..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_handle_write_op.hpp
+++ /dev/null
@@ -1,103 +0,0 @@
-//
-// detail/win_iocp_handle_write_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Rep Invariant Systems, Inc. (info@repinvariant.com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_HANDLE_WRITE_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_HANDLE_WRITE_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/error.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename ConstBufferSequence, typename Handler>
-class win_iocp_handle_write_op : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_handle_write_op);
-
-  win_iocp_handle_write_op(const ConstBufferSequence& buffers, Handler& handler)
-    : operation(&win_iocp_handle_write_op::do_complete),
-      buffers_(buffers),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& ec, std::size_t bytes_transferred)
-  {
-    // Take ownership of the operation object.
-    win_iocp_handle_write_op* o(static_cast<win_iocp_handle_write_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    if (owner)
-    {
-      // Check whether buffers are still valid.
-      buffer_sequence_adapter<asio::const_buffer,
-          ConstBufferSequence>::validate(o->buffers_);
-    }
-#endif // defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, ec, bytes_transferred);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  ConstBufferSequence buffers_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_HANDLE_WRITE_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_io_context.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_io_context.hpp
deleted file mode 100644
index 11bf58b7d1a..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_io_context.hpp
+++ /dev/null
@@ -1,328 +0,0 @@
-//
-// detail/win_iocp_io_context.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_IO_CONTEXT_HPP
-#define ASIO_DETAIL_WIN_IOCP_IO_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/limits.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/scoped_ptr.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/thread.hpp"
-#include "asio/detail/thread_context.hpp"
-#include "asio/detail/timer_queue_base.hpp"
-#include "asio/detail/timer_queue_set.hpp"
-#include "asio/detail/wait_op.hpp"
-#include "asio/detail/win_iocp_operation.hpp"
-#include "asio/detail/win_iocp_thread_info.hpp"
-#include "asio/execution_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class wait_op;
-
-class win_iocp_io_context
-  : public execution_context_service_base<win_iocp_io_context>,
-    public thread_context
-{
-public:
-  // Constructor. Specifies a concurrency hint that is passed through to the
-  // underlying I/O completion port.
-  ASIO_DECL win_iocp_io_context(asio::execution_context& ctx,
-      int concurrency_hint = -1);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Initialise the task. Nothing to do here.
-  void init_task()
-  {
-  }
-
-  // Register a handle with the IO completion port.
-  ASIO_DECL asio::error_code register_handle(
-      HANDLE handle, asio::error_code& ec);
-
-  // Run the event loop until stopped or no more work.
-  ASIO_DECL size_t run(asio::error_code& ec);
-
-  // Run until stopped or one operation is performed.
-  ASIO_DECL size_t run_one(asio::error_code& ec);
-
-  // Run until timeout, interrupted, or one operation is performed.
-  ASIO_DECL size_t wait_one(long usec, asio::error_code& ec);
-
-  // Poll for operations without blocking.
-  ASIO_DECL size_t poll(asio::error_code& ec);
-
-  // Poll for one operation without blocking.
-  ASIO_DECL size_t poll_one(asio::error_code& ec);
-
-  // Stop the event processing loop.
-  ASIO_DECL void stop();
-
-  // Determine whether the io_context is stopped.
-  bool stopped() const
-  {
-    return ::InterlockedExchangeAdd(&stopped_, 0) != 0;
-  }
-
-  // Restart in preparation for a subsequent run invocation.
-  void restart()
-  {
-    ::InterlockedExchange(&stopped_, 0);
-  }
-
-  // Notify that some work has started.
-  void work_started()
-  {
-    ::InterlockedIncrement(&outstanding_work_);
-  }
-
-  // Notify that some work has finished.
-  void work_finished()
-  {
-    if (::InterlockedDecrement(&outstanding_work_) == 0)
-      stop();
-  }
-
-  // Return whether a handler can be dispatched immediately.
-  bool can_dispatch()
-  {
-    return thread_call_stack::contains(this) != 0;
-  }
-
-  // Request invocation of the given operation and return immediately. Assumes
-  // that work_started() has not yet been called for the operation.
-  void post_immediate_completion(win_iocp_operation* op, bool)
-  {
-    work_started();
-    post_deferred_completion(op);
-  }
-
-  // Request invocation of the given operation and return immediately. Assumes
-  // that work_started() was previously called for the operation.
-  ASIO_DECL void post_deferred_completion(win_iocp_operation* op);
-
-  // Request invocation of the given operation and return immediately. Assumes
-  // that work_started() was previously called for the operations.
-  ASIO_DECL void post_deferred_completions(
-      op_queue<win_iocp_operation>& ops);
-
-  // Request invocation of the given operation using the thread-private queue
-  // and return immediately. Assumes that work_started() has not yet been
-  // called for the operation.
-  void post_private_immediate_completion(win_iocp_operation* op)
-  {
-    post_immediate_completion(op, false);
-  }
-
-  // Request invocation of the given operation using the thread-private queue
-  // and return immediately. Assumes that work_started() was previously called
-  // for the operation.
-  void post_private_deferred_completion(win_iocp_operation* op)
-  {
-    post_deferred_completion(op);
-  }
-
-  // Enqueue the given operation following a failed attempt to dispatch the
-  // operation for immediate invocation.
-  void do_dispatch(operation* op)
-  {
-    post_immediate_completion(op, false);
-  }
-
-  // Process unfinished operations as part of a shutdown operation. Assumes
-  // that work_started() was previously called for the operations.
-  ASIO_DECL void abandon_operations(op_queue<operation>& ops);
-
-  // Called after starting an overlapped I/O operation that did not complete
-  // immediately. The caller must have already called work_started() prior to
-  // starting the operation.
-  ASIO_DECL void on_pending(win_iocp_operation* op);
-
-  // Called after starting an overlapped I/O operation that completed
-  // immediately. The caller must have already called work_started() prior to
-  // starting the operation.
-  ASIO_DECL void on_completion(win_iocp_operation* op,
-      DWORD last_error = 0, DWORD bytes_transferred = 0);
-
-  // Called after starting an overlapped I/O operation that completed
-  // immediately. The caller must have already called work_started() prior to
-  // starting the operation.
-  ASIO_DECL void on_completion(win_iocp_operation* op,
-      const asio::error_code& ec, DWORD bytes_transferred = 0);
-
-  // Add a new timer queue to the service.
-  template <typename Time_Traits>
-  void add_timer_queue(timer_queue<Time_Traits>& timer_queue);
-
-  // Remove a timer queue from the service.
-  template <typename Time_Traits>
-  void remove_timer_queue(timer_queue<Time_Traits>& timer_queue);
-
-  // Schedule a new operation in the given timer queue to expire at the
-  // specified absolute time.
-  template <typename Time_Traits>
-  void schedule_timer(timer_queue<Time_Traits>& queue,
-      const typename Time_Traits::time_type& time,
-      typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op);
-
-  // Cancel the timer associated with the given token. Returns the number of
-  // handlers that have been posted or dispatched.
-  template <typename Time_Traits>
-  std::size_t cancel_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& timer,
-      std::size_t max_cancelled = (std::numeric_limits<std::size_t>::max)());
-
-  // Move the timer operations associated with the given timer.
-  template <typename Time_Traits>
-  void move_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& to,
-      typename timer_queue<Time_Traits>::per_timer_data& from);
-
-  // Get the concurrency hint that was used to initialise the io_context.
-  int concurrency_hint() const
-  {
-    return concurrency_hint_;
-  }
-
-private:
-#if defined(WINVER) && (WINVER < 0x0500)
-  typedef DWORD dword_ptr_t;
-  typedef ULONG ulong_ptr_t;
-#else // defined(WINVER) && (WINVER < 0x0500)
-  typedef DWORD_PTR dword_ptr_t;
-  typedef ULONG_PTR ulong_ptr_t;
-#endif // defined(WINVER) && (WINVER < 0x0500)
-
-  // Dequeues at most one operation from the I/O completion port, and then
-  // executes it. Returns the number of operations that were dequeued (i.e.
-  // either 0 or 1).
-  ASIO_DECL size_t do_one(DWORD msec, asio::error_code& ec);
-
-  // Helper to calculate the GetQueuedCompletionStatus timeout.
-  ASIO_DECL static DWORD get_gqcs_timeout();
-
-  // Helper function to add a new timer queue.
-  ASIO_DECL void do_add_timer_queue(timer_queue_base& queue);
-
-  // Helper function to remove a timer queue.
-  ASIO_DECL void do_remove_timer_queue(timer_queue_base& queue);
-
-  // Called to recalculate and update the timeout.
-  ASIO_DECL void update_timeout();
-
-  // Helper class to call work_finished() on block exit.
-  struct work_finished_on_block_exit;
-
-  // Helper class for managing a HANDLE.
-  struct auto_handle
-  {
-    HANDLE handle;
-    auto_handle() : handle(0) {}
-    ~auto_handle() { if (handle) ::CloseHandle(handle); }
-  };
-
-  // The IO completion port used for queueing operations.
-  auto_handle iocp_;
-
-  // The count of unfinished work.
-  long outstanding_work_;
-
-  // Flag to indicate whether the event loop has been stopped.
-  mutable long stopped_;
-
-  // Flag to indicate whether there is an in-flight stop event. Every event
-  // posted using PostQueuedCompletionStatus consumes non-paged pool, so to
-  // avoid exhausting this resouce we limit the number of outstanding events.
-  long stop_event_posted_;
-
-  // Flag to indicate whether the service has been shut down.
-  long shutdown_;
-
-  enum
-  {
-    // Timeout to use with GetQueuedCompletionStatus on older versions of
-    // Windows. Some versions of windows have a "bug" where a call to
-    // GetQueuedCompletionStatus can appear stuck even though there are events
-    // waiting on the queue. Using a timeout helps to work around the issue.
-    default_gqcs_timeout = 500,
-
-    // Maximum waitable timer timeout, in milliseconds.
-    max_timeout_msec = 5 * 60 * 1000,
-
-    // Maximum waitable timer timeout, in microseconds.
-    max_timeout_usec = max_timeout_msec * 1000,
-
-    // Completion key value used to wake up a thread to dispatch timers or
-    // completed operations.
-    wake_for_dispatch = 1,
-
-    // Completion key value to indicate that an operation has posted with the
-    // original last_error and bytes_transferred values stored in the fields of
-    // the OVERLAPPED structure.
-    overlapped_contains_result = 2
-  };
-
-  // Timeout to use with GetQueuedCompletionStatus.
-  const DWORD gqcs_timeout_;
-
-  // Function object for processing timeouts in a background thread.
-  struct timer_thread_function;
-  friend struct timer_thread_function;
-
-  // Background thread used for processing timeouts.
-  scoped_ptr<thread> timer_thread_;
-
-  // A waitable timer object used for waiting for timeouts.
-  auto_handle waitable_timer_;
-
-  // Non-zero if timers or completed operations need to be dispatched.
-  long dispatch_required_;
-
-  // Mutex for protecting access to the timer queues and completed operations.
-  mutex dispatch_mutex_;
-
-  // The timer queues.
-  timer_queue_set timer_queues_;
-
-  // The operations that are ready to dispatch.
-  op_queue<win_iocp_operation> completed_ops_;
-
-  // The concurrency hint used to initialise the io_context.
-  const int concurrency_hint_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/detail/impl/win_iocp_io_context.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_iocp_io_context.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_IO_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_null_buffers_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_null_buffers_op.hpp
deleted file mode 100644
index db70cb28a14..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_null_buffers_op.hpp
+++ /dev/null
@@ -1,121 +0,0 @@
-//
-// detail/win_iocp_null_buffers_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_NULL_BUFFERS_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_NULL_BUFFERS_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class win_iocp_null_buffers_op : public reactor_op
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_null_buffers_op);
-
-  win_iocp_null_buffers_op(socket_ops::weak_cancel_token_type cancel_token,
-      Handler& handler)
-    : reactor_op(&win_iocp_null_buffers_op::do_perform,
-        &win_iocp_null_buffers_op::do_complete),
-      cancel_token_(cancel_token),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static status do_perform(reactor_op*)
-  {
-    return done;
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t bytes_transferred)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_null_buffers_op* o(static_cast<win_iocp_null_buffers_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // The reactor may have stored a result in the operation object.
-    if (o->ec_)
-      ec = o->ec_;
-
-    // Map non-portable errors to their portable counterparts.
-    if (ec.value() == ERROR_NETNAME_DELETED)
-    {
-      if (o->cancel_token_.expired())
-        ec = asio::error::operation_aborted;
-      else
-        ec = asio::error::connection_reset;
-    }
-    else if (ec.value() == ERROR_PORT_UNREACHABLE)
-    {
-      ec = asio::error::connection_refused;
-    }
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, ec, bytes_transferred);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  socket_ops::weak_cancel_token_type cancel_token_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_NULL_BUFFERS_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_operation.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_operation.hpp
deleted file mode 100644
index 81d43f07f64..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_operation.hpp
+++ /dev/null
@@ -1,96 +0,0 @@
-//
-// detail/win_iocp_operation.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_OPERATION_HPP
-#define ASIO_DETAIL_WIN_IOCP_OPERATION_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/handler_tracking.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/error_code.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class win_iocp_io_context;
-
-// Base class for all operations. A function pointer is used instead of virtual
-// functions to avoid the associated overhead.
-class win_iocp_operation
-  : public OVERLAPPED
-    ASIO_ALSO_INHERIT_TRACKED_HANDLER
-{
-public:
-  typedef win_iocp_operation operation_type;
-
-  void complete(void* owner, const asio::error_code& ec,
-      std::size_t bytes_transferred)
-  {
-    func_(owner, this, ec, bytes_transferred);
-  }
-
-  void destroy()
-  {
-    func_(0, this, asio::error_code(), 0);
-  }
-
-protected:
-  typedef void (*func_type)(
-      void*, win_iocp_operation*,
-      const asio::error_code&, std::size_t);
-
-  win_iocp_operation(func_type func)
-    : next_(0),
-      func_(func)
-  {
-    reset();
-  }
-
-  // Prevents deletion through this type.
-  ~win_iocp_operation()
-  {
-  }
-
-  void reset()
-  {
-    Internal = 0;
-    InternalHigh = 0;
-    Offset = 0;
-    OffsetHigh = 0;
-    hEvent = 0;
-    ready_ = 0;
-  }
-
-private:
-  friend class op_queue_access;
-  friend class win_iocp_io_context;
-  win_iocp_operation* next_;
-  func_type func_;
-  long ready_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_OPERATION_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_overlapped_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_overlapped_op.hpp
deleted file mode 100644
index 2b2cc319b22..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_overlapped_op.hpp
+++ /dev/null
@@ -1,90 +0,0 @@
-//
-// detail/win_iocp_overlapped_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_OVERLAPPED_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_OVERLAPPED_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/error.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class win_iocp_overlapped_op : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_overlapped_op);
-
-  win_iocp_overlapped_op(Handler& handler)
-    : operation(&win_iocp_overlapped_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& ec, std::size_t bytes_transferred)
-  {
-    // Take ownership of the operation object.
-    win_iocp_overlapped_op* o(static_cast<win_iocp_overlapped_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, ec, bytes_transferred);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_OVERLAPPED_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_overlapped_ptr.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_overlapped_ptr.hpp
deleted file mode 100644
index 7a191143484..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_overlapped_ptr.hpp
+++ /dev/null
@@ -1,143 +0,0 @@
-//
-// detail/win_iocp_overlapped_ptr.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_OVERLAPPED_PTR_HPP
-#define ASIO_DETAIL_WIN_IOCP_OVERLAPPED_PTR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/io_context.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/win_iocp_overlapped_op.hpp"
-#include "asio/detail/win_iocp_io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Wraps a handler to create an OVERLAPPED object for use with overlapped I/O.
-class win_iocp_overlapped_ptr
-  : private noncopyable
-{
-public:
-  // Construct an empty win_iocp_overlapped_ptr.
-  win_iocp_overlapped_ptr()
-    : ptr_(0),
-      iocp_service_(0)
-  {
-  }
-
-  // Construct an win_iocp_overlapped_ptr to contain the specified handler.
-  template <typename Handler>
-  explicit win_iocp_overlapped_ptr(
-      asio::io_context& io_context, ASIO_MOVE_ARG(Handler) handler)
-    : ptr_(0),
-      iocp_service_(0)
-  {
-    this->reset(io_context, ASIO_MOVE_CAST(Handler)(handler));
-  }
-
-  // Destructor automatically frees the OVERLAPPED object unless released.
-  ~win_iocp_overlapped_ptr()
-  {
-    reset();
-  }
-
-  // Reset to empty.
-  void reset()
-  {
-    if (ptr_)
-    {
-      ptr_->destroy();
-      ptr_ = 0;
-      iocp_service_->work_finished();
-      iocp_service_ = 0;
-    }
-  }
-
-  // Reset to contain the specified handler, freeing any current OVERLAPPED
-  // object.
-  template <typename Handler>
-  void reset(asio::io_context& io_context, Handler handler)
-  {
-    typedef win_iocp_overlapped_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((io_context, *p.p,
-          "io_context", &io_context.impl_, 0, "overlapped"));
-
-    io_context.impl_.work_started();
-    reset();
-    ptr_ = p.p;
-    p.v = p.p = 0;
-    iocp_service_ = &io_context.impl_;
-  }
-
-  // Get the contained OVERLAPPED object.
-  OVERLAPPED* get()
-  {
-    return ptr_;
-  }
-
-  // Get the contained OVERLAPPED object.
-  const OVERLAPPED* get() const
-  {
-    return ptr_;
-  }
-
-  // Release ownership of the OVERLAPPED object.
-  OVERLAPPED* release()
-  {
-    if (ptr_)
-      iocp_service_->on_pending(ptr_);
-
-    OVERLAPPED* tmp = ptr_;
-    ptr_ = 0;
-    iocp_service_ = 0;
-    return tmp;
-  }
-
-  // Post completion notification for overlapped operation. Releases ownership.
-  void complete(const asio::error_code& ec,
-      std::size_t bytes_transferred)
-  {
-    if (ptr_)
-    {
-      iocp_service_->on_completion(ptr_, ec,
-          static_cast<DWORD>(bytes_transferred));
-      ptr_ = 0;
-      iocp_service_ = 0;
-    }
-  }
-
-private:
-  win_iocp_operation* ptr_;
-  win_iocp_io_context* iocp_service_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_OVERLAPPED_PTR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_serial_port_service.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_serial_port_service.hpp
deleted file mode 100644
index ac06348ecfd..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_serial_port_service.hpp
+++ /dev/null
@@ -1,230 +0,0 @@
-//
-// detail/win_iocp_serial_port_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Rep Invariant Systems, Inc. (info@repinvariant.com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_SERIAL_PORT_SERVICE_HPP
-#define ASIO_DETAIL_WIN_IOCP_SERIAL_PORT_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP) && defined(ASIO_HAS_SERIAL_PORT)
-
-#include <string>
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/detail/win_iocp_handle_service.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Extend win_iocp_handle_service to provide serial port support.
-class win_iocp_serial_port_service :
-  public service_base<win_iocp_serial_port_service>
-{
-public:
-  // The native type of a serial port.
-  typedef win_iocp_handle_service::native_handle_type native_handle_type;
-
-  // The implementation type of the serial port.
-  typedef win_iocp_handle_service::implementation_type implementation_type;
-
-  // Constructor.
-  ASIO_DECL win_iocp_serial_port_service(
-      asio::io_context& io_context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Construct a new serial port implementation.
-  void construct(implementation_type& impl)
-  {
-    handle_service_.construct(impl);
-  }
-
-  // Move-construct a new serial port implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    handle_service_.move_construct(impl, other_impl);
-  }
-
-  // Move-assign from another serial port implementation.
-  void move_assign(implementation_type& impl,
-      win_iocp_serial_port_service& other_service,
-      implementation_type& other_impl)
-  {
-    handle_service_.move_assign(impl,
-        other_service.handle_service_, other_impl);
-  }
-
-  // Destroy a serial port implementation.
-  void destroy(implementation_type& impl)
-  {
-    handle_service_.destroy(impl);
-  }
-
-  // Open the serial port using the specified device name.
-  ASIO_DECL asio::error_code open(implementation_type& impl,
-      const std::string& device, asio::error_code& ec);
-
-  // Assign a native handle to a serial port implementation.
-  asio::error_code assign(implementation_type& impl,
-      const native_handle_type& handle, asio::error_code& ec)
-  {
-    return handle_service_.assign(impl, handle, ec);
-  }
-
-  // Determine whether the serial port is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return handle_service_.is_open(impl);
-  }
-
-  // Destroy a serial port implementation.
-  asio::error_code close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return handle_service_.close(impl, ec);
-  }
-
-  // Get the native serial port representation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return handle_service_.native_handle(impl);
-  }
-
-  // Cancel all operations associated with the handle.
-  asio::error_code cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return handle_service_.cancel(impl, ec);
-  }
-
-  // Set an option on the serial port.
-  template <typename SettableSerialPortOption>
-  asio::error_code set_option(implementation_type& impl,
-      const SettableSerialPortOption& option, asio::error_code& ec)
-  {
-    return do_set_option(impl,
-        &win_iocp_serial_port_service::store_option<SettableSerialPortOption>,
-        &option, ec);
-  }
-
-  // Get an option from the serial port.
-  template <typename GettableSerialPortOption>
-  asio::error_code get_option(const implementation_type& impl,
-      GettableSerialPortOption& option, asio::error_code& ec) const
-  {
-    return do_get_option(impl,
-        &win_iocp_serial_port_service::load_option<GettableSerialPortOption>,
-        &option, ec);
-  }
-
-  // Send a break sequence to the serial port.
-  asio::error_code send_break(implementation_type&,
-      asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Write the given data. Returns the number of bytes sent.
-  template <typename ConstBufferSequence>
-  size_t write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    return handle_service_.write_some(impl, buffers, ec);
-  }
-
-  // Start an asynchronous write. The data being written must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, Handler& handler)
-  {
-    handle_service_.async_write_some(impl, buffers, handler);
-  }
-
-  // Read some data. Returns the number of bytes received.
-  template <typename MutableBufferSequence>
-  size_t read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    return handle_service_.read_some(impl, buffers, ec);
-  }
-
-  // Start an asynchronous read. The buffer for the data being received must be
-  // valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, Handler& handler)
-  {
-    handle_service_.async_read_some(impl, buffers, handler);
-  }
-
-private:
-  // Function pointer type for storing a serial port option.
-  typedef asio::error_code (*store_function_type)(
-      const void*, ::DCB&, asio::error_code&);
-
-  // Helper function template to store a serial port option.
-  template <typename SettableSerialPortOption>
-  static asio::error_code store_option(const void* option,
-      ::DCB& storage, asio::error_code& ec)
-  {
-    static_cast<const SettableSerialPortOption*>(option)->store(storage, ec);
-    return ec;
-  }
-
-  // Helper function to set a serial port option.
-  ASIO_DECL asio::error_code do_set_option(
-      implementation_type& impl, store_function_type store,
-      const void* option, asio::error_code& ec);
-
-  // Function pointer type for loading a serial port option.
-  typedef asio::error_code (*load_function_type)(
-      void*, const ::DCB&, asio::error_code&);
-
-  // Helper function template to load a serial port option.
-  template <typename GettableSerialPortOption>
-  static asio::error_code load_option(void* option,
-      const ::DCB& storage, asio::error_code& ec)
-  {
-    static_cast<GettableSerialPortOption*>(option)->load(storage, ec);
-    return ec;
-  }
-
-  // Helper function to get a serial port option.
-  ASIO_DECL asio::error_code do_get_option(
-      const implementation_type& impl, load_function_type load,
-      void* option, asio::error_code& ec) const;
-
-  // The implementation used for initiating asynchronous operations.
-  win_iocp_handle_service handle_service_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_iocp_serial_port_service.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_IOCP) && defined(ASIO_HAS_SERIAL_PORT)
-
-#endif // ASIO_DETAIL_WIN_IOCP_SERIAL_PORT_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_socket_accept_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_socket_accept_op.hpp
deleted file mode 100644
index 18e73356ca5..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_socket_accept_op.hpp
+++ /dev/null
@@ -1,297 +0,0 @@
-//
-// detail/win_iocp_socket_accept_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_SOCKET_ACCEPT_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_SOCKET_ACCEPT_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/operation.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/win_iocp_socket_service_base.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Socket, typename Protocol, typename Handler>
-class win_iocp_socket_accept_op : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_socket_accept_op);
-
-  win_iocp_socket_accept_op(win_iocp_socket_service_base& socket_service,
-      socket_type socket, Socket& peer, const Protocol& protocol,
-      typename Protocol::endpoint* peer_endpoint,
-      bool enable_connection_aborted, Handler& handler)
-    : operation(&win_iocp_socket_accept_op::do_complete),
-      socket_service_(socket_service),
-      socket_(socket),
-      peer_(peer),
-      protocol_(protocol),
-      peer_endpoint_(peer_endpoint),
-      enable_connection_aborted_(enable_connection_aborted),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  socket_holder& new_socket()
-  {
-    return new_socket_;
-  }
-
-  void* output_buffer()
-  {
-    return output_buffer_;
-  }
-
-  DWORD address_length()
-  {
-    return sizeof(sockaddr_storage_type) + 16;
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t /*bytes_transferred*/)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_socket_accept_op* o(static_cast<win_iocp_socket_accept_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    if (owner)
-    {
-      typename Protocol::endpoint peer_endpoint;
-      std::size_t addr_len = peer_endpoint.capacity();
-      socket_ops::complete_iocp_accept(o->socket_,
-          o->output_buffer(), o->address_length(),
-          peer_endpoint.data(), &addr_len,
-          o->new_socket_.get(), ec);
-
-      // Restart the accept operation if we got the connection_aborted error
-      // and the enable_connection_aborted socket option is not set.
-      if (ec == asio::error::connection_aborted
-          && !o->enable_connection_aborted_)
-      {
-        o->reset();
-        o->socket_service_.restart_accept_op(o->socket_,
-            o->new_socket_, o->protocol_.family(),
-            o->protocol_.type(), o->protocol_.protocol(),
-            o->output_buffer(), o->address_length(), o);
-        p.v = p.p = 0;
-        return;
-      }
-
-      // If the socket was successfully accepted, transfer ownership of the
-      // socket to the peer object.
-      if (!ec)
-      {
-        o->peer_.assign(o->protocol_,
-            typename Socket::native_handle_type(
-              o->new_socket_.get(), peer_endpoint), ec);
-        if (!ec)
-          o->new_socket_.release();
-      }
-
-      // Pass endpoint back to caller.
-      if (o->peer_endpoint_)
-        *o->peer_endpoint_ = peer_endpoint;
-    }
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder1<Handler, asio::error_code>
-      handler(o->handler_, ec);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  win_iocp_socket_service_base& socket_service_;
-  socket_type socket_;
-  socket_holder new_socket_;
-  Socket& peer_;
-  Protocol protocol_;
-  typename Protocol::endpoint* peer_endpoint_;
-  unsigned char output_buffer_[(sizeof(sockaddr_storage_type) + 16) * 2];
-  bool enable_connection_aborted_;
-  Handler handler_;
-};
-
-#if defined(ASIO_HAS_MOVE)
-
-template <typename Protocol, typename Handler>
-class win_iocp_socket_move_accept_op : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_socket_move_accept_op);
-
-  win_iocp_socket_move_accept_op(
-      win_iocp_socket_service_base& socket_service, socket_type socket,
-      const Protocol& protocol, asio::io_context& peer_io_context,
-      typename Protocol::endpoint* peer_endpoint,
-      bool enable_connection_aborted, Handler& handler)
-    : operation(&win_iocp_socket_move_accept_op::do_complete),
-      socket_service_(socket_service),
-      socket_(socket),
-      peer_(peer_io_context),
-      protocol_(protocol),
-      peer_endpoint_(peer_endpoint),
-      enable_connection_aborted_(enable_connection_aborted),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  socket_holder& new_socket()
-  {
-    return new_socket_;
-  }
-
-  void* output_buffer()
-  {
-    return output_buffer_;
-  }
-
-  DWORD address_length()
-  {
-    return sizeof(sockaddr_storage_type) + 16;
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t /*bytes_transferred*/)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_socket_move_accept_op* o(
-        static_cast<win_iocp_socket_move_accept_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    if (owner)
-    {
-      typename Protocol::endpoint peer_endpoint;
-      std::size_t addr_len = peer_endpoint.capacity();
-      socket_ops::complete_iocp_accept(o->socket_,
-          o->output_buffer(), o->address_length(),
-          peer_endpoint.data(), &addr_len,
-          o->new_socket_.get(), ec);
-
-      // Restart the accept operation if we got the connection_aborted error
-      // and the enable_connection_aborted socket option is not set.
-      if (ec == asio::error::connection_aborted
-          && !o->enable_connection_aborted_)
-      {
-        o->reset();
-        o->socket_service_.restart_accept_op(o->socket_,
-            o->new_socket_, o->protocol_.family(),
-            o->protocol_.type(), o->protocol_.protocol(),
-            o->output_buffer(), o->address_length(), o);
-        p.v = p.p = 0;
-        return;
-      }
-
-      // If the socket was successfully accepted, transfer ownership of the
-      // socket to the peer object.
-      if (!ec)
-      {
-        o->peer_.assign(o->protocol_,
-            typename Protocol::socket::native_handle_type(
-              o->new_socket_.get(), peer_endpoint), ec);
-        if (!ec)
-          o->new_socket_.release();
-      }
-
-      // Pass endpoint back to caller.
-      if (o->peer_endpoint_)
-        *o->peer_endpoint_ = peer_endpoint;
-    }
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::move_binder2<Handler,
-      asio::error_code, typename Protocol::socket>
-        handler(0, ASIO_MOVE_CAST(Handler)(o->handler_), ec,
-          ASIO_MOVE_CAST(typename Protocol::socket)(o->peer_));
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, "..."));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  win_iocp_socket_service_base& socket_service_;
-  socket_type socket_;
-  socket_holder new_socket_;
-  typename Protocol::socket peer_;
-  Protocol protocol_;
-  typename Protocol::endpoint* peer_endpoint_;
-  unsigned char output_buffer_[(sizeof(sockaddr_storage_type) + 16) * 2];
-  bool enable_connection_aborted_;
-  Handler handler_;
-};
-
-#endif // defined(ASIO_HAS_MOVE)
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_SOCKET_ACCEPT_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_socket_connect_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_socket_connect_op.hpp
deleted file mode 100644
index e0c52dc9758..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_socket_connect_op.hpp
+++ /dev/null
@@ -1,127 +0,0 @@
-//
-// detail/win_iocp_socket_connect_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_SOCKET_CONNECT_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_SOCKET_CONNECT_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class win_iocp_socket_connect_op_base : public reactor_op
-{
-public:
-  win_iocp_socket_connect_op_base(socket_type socket, func_type complete_func)
-    : reactor_op(&win_iocp_socket_connect_op_base::do_perform, complete_func),
-      socket_(socket),
-      connect_ex_(false)
-  {
-  }
-
-  static status do_perform(reactor_op* base)
-  {
-    win_iocp_socket_connect_op_base* o(
-        static_cast<win_iocp_socket_connect_op_base*>(base));
-
-    return socket_ops::non_blocking_connect(
-        o->socket_, o->ec_) ? done : not_done;
-  }
-
-  socket_type socket_;
-  bool connect_ex_;
-};
-
-template <typename Handler>
-class win_iocp_socket_connect_op : public win_iocp_socket_connect_op_base
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_socket_connect_op);
-
-  win_iocp_socket_connect_op(socket_type socket, Handler& handler)
-    : win_iocp_socket_connect_op_base(socket,
-        &win_iocp_socket_connect_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t /*bytes_transferred*/)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_socket_connect_op* o(
-        static_cast<win_iocp_socket_connect_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    if (owner)
-    {
-      if (o->connect_ex_)
-        socket_ops::complete_iocp_connect(o->socket_, ec);
-      else
-        ec = o->ec_;
-    }
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder1<Handler, asio::error_code>
-      handler(o->handler_, ec);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_SOCKET_CONNECT_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_socket_recv_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_socket_recv_op.hpp
deleted file mode 100644
index 41595405db3..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_socket_recv_op.hpp
+++ /dev/null
@@ -1,117 +0,0 @@
-//
-// detail/win_iocp_socket_recv_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_SOCKET_RECV_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_SOCKET_RECV_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/operation.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename MutableBufferSequence, typename Handler>
-class win_iocp_socket_recv_op : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_socket_recv_op);
-
-  win_iocp_socket_recv_op(socket_ops::state_type state,
-      socket_ops::weak_cancel_token_type cancel_token,
-      const MutableBufferSequence& buffers, Handler& handler)
-    : operation(&win_iocp_socket_recv_op::do_complete),
-      state_(state),
-      cancel_token_(cancel_token),
-      buffers_(buffers),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t bytes_transferred)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_socket_recv_op* o(static_cast<win_iocp_socket_recv_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    // Check whether buffers are still valid.
-    if (owner)
-    {
-      buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::validate(o->buffers_);
-    }
-#endif // defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-
-    socket_ops::complete_iocp_recv(o->state_, o->cancel_token_,
-        buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::all_empty(o->buffers_),
-        ec, bytes_transferred);
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, ec, bytes_transferred);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  socket_ops::state_type state_;
-  socket_ops::weak_cancel_token_type cancel_token_;
-  MutableBufferSequence buffers_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_SOCKET_RECV_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_socket_recvfrom_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_socket_recvfrom_op.hpp
deleted file mode 100644
index 843ce5bba5f..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_socket_recvfrom_op.hpp
+++ /dev/null
@@ -1,125 +0,0 @@
-//
-// detail/win_iocp_socket_recvfrom_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_SOCKET_RECVFROM_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_SOCKET_RECVFROM_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/operation.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename MutableBufferSequence, typename Endpoint, typename Handler>
-class win_iocp_socket_recvfrom_op : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_socket_recvfrom_op);
-
-  win_iocp_socket_recvfrom_op(Endpoint& endpoint,
-      socket_ops::weak_cancel_token_type cancel_token,
-      const MutableBufferSequence& buffers, Handler& handler)
-    : operation(&win_iocp_socket_recvfrom_op::do_complete),
-      endpoint_(endpoint),
-      endpoint_size_(static_cast<int>(endpoint.capacity())),
-      cancel_token_(cancel_token),
-      buffers_(buffers),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  int& endpoint_size()
-  {
-    return endpoint_size_;
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t bytes_transferred)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_socket_recvfrom_op* o(
-        static_cast<win_iocp_socket_recvfrom_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    // Check whether buffers are still valid.
-    if (owner)
-    {
-      buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::validate(o->buffers_);
-    }
-#endif // defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-
-    socket_ops::complete_iocp_recvfrom(o->cancel_token_, ec);
-
-    // Record the size of the endpoint returned by the operation.
-    o->endpoint_.resize(o->endpoint_size_);
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, ec, bytes_transferred);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Endpoint& endpoint_;
-  int endpoint_size_;
-  socket_ops::weak_cancel_token_type cancel_token_;
-  MutableBufferSequence buffers_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_SOCKET_RECVFROM_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_socket_recvmsg_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_socket_recvmsg_op.hpp
deleted file mode 100644
index 78f36b7f343..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_socket_recvmsg_op.hpp
+++ /dev/null
@@ -1,118 +0,0 @@
-//
-// detail/win_iocp_socket_recvmsg_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_SOCKET_RECVMSG_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_SOCKET_RECVMSG_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/operation.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/error.hpp"
-#include "asio/socket_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename MutableBufferSequence, typename Handler>
-class win_iocp_socket_recvmsg_op : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_socket_recvmsg_op);
-
-  win_iocp_socket_recvmsg_op(
-      socket_ops::weak_cancel_token_type cancel_token,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags& out_flags, Handler& handler)
-    : operation(&win_iocp_socket_recvmsg_op::do_complete),
-      cancel_token_(cancel_token),
-      buffers_(buffers),
-      out_flags_(out_flags),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t bytes_transferred)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_socket_recvmsg_op* o(
-        static_cast<win_iocp_socket_recvmsg_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    // Check whether buffers are still valid.
-    if (owner)
-    {
-      buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::validate(o->buffers_);
-    }
-#endif // defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-
-    socket_ops::complete_iocp_recvmsg(o->cancel_token_, ec);
-    o->out_flags_ = 0;
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, ec, bytes_transferred);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  socket_ops::weak_cancel_token_type cancel_token_;
-  MutableBufferSequence buffers_;
-  socket_base::message_flags& out_flags_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_SOCKET_RECVMSG_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_socket_send_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_socket_send_op.hpp
deleted file mode 100644
index e1c7ab93c5c..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_socket_send_op.hpp
+++ /dev/null
@@ -1,111 +0,0 @@
-//
-// detail/win_iocp_socket_send_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_SOCKET_SEND_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_SOCKET_SEND_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/operation.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename ConstBufferSequence, typename Handler>
-class win_iocp_socket_send_op : public operation
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_socket_send_op);
-
-  win_iocp_socket_send_op(socket_ops::weak_cancel_token_type cancel_token,
-      const ConstBufferSequence& buffers, Handler& handler)
-    : operation(&win_iocp_socket_send_op::do_complete),
-      cancel_token_(cancel_token),
-      buffers_(buffers),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t bytes_transferred)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_socket_send_op* o(static_cast<win_iocp_socket_send_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    // Check whether buffers are still valid.
-    if (owner)
-    {
-      buffer_sequence_adapter<asio::const_buffer,
-          ConstBufferSequence>::validate(o->buffers_);
-    }
-#endif // defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-
-    socket_ops::complete_iocp_send(o->cancel_token_, ec);
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, ec, bytes_transferred);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  socket_ops::weak_cancel_token_type cancel_token_;
-  ConstBufferSequence buffers_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_SOCKET_SEND_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_socket_service.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_socket_service.hpp
deleted file mode 100644
index 3f01b4d3e77..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_socket_service.hpp
+++ /dev/null
@@ -1,599 +0,0 @@
-//
-// detail/win_iocp_socket_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_SOCKET_SERVICE_HPP
-#define ASIO_DETAIL_WIN_IOCP_SOCKET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include <cstring>
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/socket_base.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/operation.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/select_reactor.hpp"
-#include "asio/detail/socket_holder.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/win_iocp_io_context.hpp"
-#include "asio/detail/win_iocp_null_buffers_op.hpp"
-#include "asio/detail/win_iocp_socket_accept_op.hpp"
-#include "asio/detail/win_iocp_socket_connect_op.hpp"
-#include "asio/detail/win_iocp_socket_recvfrom_op.hpp"
-#include "asio/detail/win_iocp_socket_send_op.hpp"
-#include "asio/detail/win_iocp_socket_service_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Protocol>
-class win_iocp_socket_service :
-  public service_base<win_iocp_socket_service<Protocol> >,
-  public win_iocp_socket_service_base
-{
-public:
-  // The protocol type.
-  typedef Protocol protocol_type;
-
-  // The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  // The native type of a socket.
-  class native_handle_type
-  {
-  public:
-    native_handle_type(socket_type s)
-      : socket_(s),
-        have_remote_endpoint_(false)
-    {
-    }
-
-    native_handle_type(socket_type s, const endpoint_type& ep)
-      : socket_(s),
-        have_remote_endpoint_(true),
-        remote_endpoint_(ep)
-    {
-    }
-
-    void operator=(socket_type s)
-    {
-      socket_ = s;
-      have_remote_endpoint_ = false;
-      remote_endpoint_ = endpoint_type();
-    }
-
-    operator socket_type() const
-    {
-      return socket_;
-    }
-
-    bool have_remote_endpoint() const
-    {
-      return have_remote_endpoint_;
-    }
-
-    endpoint_type remote_endpoint() const
-    {
-      return remote_endpoint_;
-    }
-
-  private:
-    socket_type socket_;
-    bool have_remote_endpoint_;
-    endpoint_type remote_endpoint_;
-  };
-
-  // The implementation type of the socket.
-  struct implementation_type :
-    win_iocp_socket_service_base::base_implementation_type
-  {
-    // Default constructor.
-    implementation_type()
-      : protocol_(endpoint_type().protocol()),
-        have_remote_endpoint_(false),
-        remote_endpoint_()
-    {
-    }
-
-    // The protocol associated with the socket.
-    protocol_type protocol_;
-
-    // Whether we have a cached remote endpoint.
-    bool have_remote_endpoint_;
-
-    // A cached remote endpoint.
-    endpoint_type remote_endpoint_;
-  };
-
-  // Constructor.
-  win_iocp_socket_service(asio::io_context& io_context)
-    : service_base<win_iocp_socket_service<Protocol> >(io_context),
-      win_iocp_socket_service_base(io_context)
-  {
-  }
-
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    this->base_shutdown();
-  }
-
-  // Move-construct a new socket implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    this->base_move_construct(impl, other_impl);
-
-    impl.protocol_ = other_impl.protocol_;
-    other_impl.protocol_ = endpoint_type().protocol();
-
-    impl.have_remote_endpoint_ = other_impl.have_remote_endpoint_;
-    other_impl.have_remote_endpoint_ = false;
-
-    impl.remote_endpoint_ = other_impl.remote_endpoint_;
-    other_impl.remote_endpoint_ = endpoint_type();
-  }
-
-  // Move-assign from another socket implementation.
-  void move_assign(implementation_type& impl,
-      win_iocp_socket_service_base& other_service,
-      implementation_type& other_impl)
-  {
-    this->base_move_assign(impl, other_service, other_impl);
-
-    impl.protocol_ = other_impl.protocol_;
-    other_impl.protocol_ = endpoint_type().protocol();
-
-    impl.have_remote_endpoint_ = other_impl.have_remote_endpoint_;
-    other_impl.have_remote_endpoint_ = false;
-
-    impl.remote_endpoint_ = other_impl.remote_endpoint_;
-    other_impl.remote_endpoint_ = endpoint_type();
-  }
-
-  // Move-construct a new socket implementation from another protocol type.
-  template <typename Protocol1>
-  void converting_move_construct(implementation_type& impl,
-      win_iocp_socket_service<Protocol1>&,
-      typename win_iocp_socket_service<
-        Protocol1>::implementation_type& other_impl)
-  {
-    this->base_move_construct(impl, other_impl);
-
-    impl.protocol_ = protocol_type(other_impl.protocol_);
-    other_impl.protocol_ = typename Protocol1::endpoint().protocol();
-
-    impl.have_remote_endpoint_ = other_impl.have_remote_endpoint_;
-    other_impl.have_remote_endpoint_ = false;
-
-    impl.remote_endpoint_ = other_impl.remote_endpoint_;
-    other_impl.remote_endpoint_ = typename Protocol1::endpoint();
-  }
-
-  // Open a new socket implementation.
-  asio::error_code open(implementation_type& impl,
-      const protocol_type& protocol, asio::error_code& ec)
-  {
-    if (!do_open(impl, protocol.family(),
-          protocol.type(), protocol.protocol(), ec))
-    {
-      impl.protocol_ = protocol;
-      impl.have_remote_endpoint_ = false;
-      impl.remote_endpoint_ = endpoint_type();
-    }
-    return ec;
-  }
-
-  // Assign a native socket to a socket implementation.
-  asio::error_code assign(implementation_type& impl,
-      const protocol_type& protocol, const native_handle_type& native_socket,
-      asio::error_code& ec)
-  {
-    if (!do_assign(impl, protocol.type(), native_socket, ec))
-    {
-      impl.protocol_ = protocol;
-      impl.have_remote_endpoint_ = native_socket.have_remote_endpoint();
-      impl.remote_endpoint_ = native_socket.remote_endpoint();
-    }
-    return ec;
-  }
-
-  // Get the native socket representation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    if (impl.have_remote_endpoint_)
-      return native_handle_type(impl.socket_, impl.remote_endpoint_);
-    return native_handle_type(impl.socket_);
-  }
-
-  // Bind the socket to the specified local endpoint.
-  asio::error_code bind(implementation_type& impl,
-      const endpoint_type& endpoint, asio::error_code& ec)
-  {
-    socket_ops::bind(impl.socket_, endpoint.data(), endpoint.size(), ec);
-    return ec;
-  }
-
-  // Set a socket option.
-  template <typename Option>
-  asio::error_code set_option(implementation_type& impl,
-      const Option& option, asio::error_code& ec)
-  {
-    socket_ops::setsockopt(impl.socket_, impl.state_,
-        option.level(impl.protocol_), option.name(impl.protocol_),
-        option.data(impl.protocol_), option.size(impl.protocol_), ec);
-    return ec;
-  }
-
-  // Set a socket option.
-  template <typename Option>
-  asio::error_code get_option(const implementation_type& impl,
-      Option& option, asio::error_code& ec) const
-  {
-    std::size_t size = option.size(impl.protocol_);
-    socket_ops::getsockopt(impl.socket_, impl.state_,
-        option.level(impl.protocol_), option.name(impl.protocol_),
-        option.data(impl.protocol_), &size, ec);
-    if (!ec)
-      option.resize(impl.protocol_, size);
-    return ec;
-  }
-
-  // Get the local endpoint.
-  endpoint_type local_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    endpoint_type endpoint;
-    std::size_t addr_len = endpoint.capacity();
-    if (socket_ops::getsockname(impl.socket_, endpoint.data(), &addr_len, ec))
-      return endpoint_type();
-    endpoint.resize(addr_len);
-    return endpoint;
-  }
-
-  // Get the remote endpoint.
-  endpoint_type remote_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    endpoint_type endpoint = impl.remote_endpoint_;
-    std::size_t addr_len = endpoint.capacity();
-    if (socket_ops::getpeername(impl.socket_, endpoint.data(),
-          &addr_len, impl.have_remote_endpoint_, ec))
-      return endpoint_type();
-    endpoint.resize(addr_len);
-    return endpoint;
-  }
-
-  // Disable sends or receives on the socket.
-  asio::error_code shutdown(base_implementation_type& impl,
-      socket_base::shutdown_type what, asio::error_code& ec)
-  {
-    socket_ops::shutdown(impl.socket_, what, ec);
-    return ec;
-  }
-
-  // Send a datagram to the specified endpoint. Returns the number of bytes
-  // sent.
-  template <typename ConstBufferSequence>
-  size_t send_to(implementation_type& impl, const ConstBufferSequence& buffers,
-      const endpoint_type& destination, socket_base::message_flags flags,
-      asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(buffers);
-
-    return socket_ops::sync_sendto(impl.socket_, impl.state_,
-        bufs.buffers(), bufs.count(), flags,
-        destination.data(), destination.size(), ec);
-  }
-
-  // Wait until data can be sent without blocking.
-  size_t send_to(implementation_type& impl, const null_buffers&,
-      const endpoint_type&, socket_base::message_flags,
-      asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_write(impl.socket_, impl.state_, -1, ec);
-
-    return 0;
-  }
-
-  // Start an asynchronous send. The data being sent must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_send_to(implementation_type& impl,
-      const ConstBufferSequence& buffers, const endpoint_type& destination,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_socket_send_op<ConstBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.cancel_token_, buffers, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_send_to"));
-
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(buffers);
-
-    start_send_to_op(impl, bufs.buffers(), bufs.count(),
-        destination.data(), static_cast<int>(destination.size()),
-        flags, p.p);
-    p.v = p.p = 0;
-  }
-
-  // Start an asynchronous wait until data can be sent without blocking.
-  template <typename Handler>
-  void async_send_to(implementation_type& impl, const null_buffers&,
-      const endpoint_type&, socket_base::message_flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.cancel_token_, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_send_to(null_buffers)"));
-
-    start_reactor_op(impl, select_reactor::write_op, p.p);
-    p.v = p.p = 0;
-  }
-
-  // Receive a datagram with the endpoint of the sender. Returns the number of
-  // bytes received.
-  template <typename MutableBufferSequence>
-  size_t receive_from(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      endpoint_type& sender_endpoint, socket_base::message_flags flags,
-      asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    std::size_t addr_len = sender_endpoint.capacity();
-    std::size_t bytes_recvd = socket_ops::sync_recvfrom(
-        impl.socket_, impl.state_, bufs.buffers(), bufs.count(),
-        flags, sender_endpoint.data(), &addr_len, ec);
-
-    if (!ec)
-      sender_endpoint.resize(addr_len);
-
-    return bytes_recvd;
-  }
-
-  // Wait until data can be received without blocking.
-  size_t receive_from(implementation_type& impl,
-      const null_buffers&, endpoint_type& sender_endpoint,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_read(impl.socket_, impl.state_, -1, ec);
-
-    // Reset endpoint since it can be given no sensible value at this time.
-    sender_endpoint = endpoint_type();
-
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received and
-  // the sender_endpoint object must both be valid for the lifetime of the
-  // asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive_from(implementation_type& impl,
-      const MutableBufferSequence& buffers, endpoint_type& sender_endp,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_socket_recvfrom_op<
-      MutableBufferSequence, endpoint_type, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(sender_endp, impl.cancel_token_, buffers, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_receive_from"));
-
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    start_receive_from_op(impl, bufs.buffers(), bufs.count(),
-        sender_endp.data(), flags, &p.p->endpoint_size(), p.p);
-    p.v = p.p = 0;
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive_from(implementation_type& impl,
-      const null_buffers&, endpoint_type& sender_endpoint,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.cancel_token_, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_receive_from(null_buffers)"));
-
-    // Reset endpoint since it can be given no sensible value at this time.
-    sender_endpoint = endpoint_type();
-
-    start_null_buffers_receive_op(impl, flags, p.p);
-    p.v = p.p = 0;
-  }
-
-  // Accept a new connection.
-  template <typename Socket>
-  asio::error_code accept(implementation_type& impl, Socket& peer,
-      endpoint_type* peer_endpoint, asio::error_code& ec)
-  {
-    // We cannot accept a socket that is already open.
-    if (peer.is_open())
-    {
-      ec = asio::error::already_open;
-      return ec;
-    }
-
-    std::size_t addr_len = peer_endpoint ? peer_endpoint->capacity() : 0;
-    socket_holder new_socket(socket_ops::sync_accept(impl.socket_,
-          impl.state_, peer_endpoint ? peer_endpoint->data() : 0,
-          peer_endpoint ? &addr_len : 0, ec));
-
-    // On success, assign new connection to peer socket object.
-    if (new_socket.get() != invalid_socket)
-    {
-      if (peer_endpoint)
-        peer_endpoint->resize(addr_len);
-      peer.assign(impl.protocol_, new_socket.get(), ec);
-      if (!ec)
-        new_socket.release();
-    }
-
-    return ec;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  // Accept a new connection.
-  typename Protocol::socket accept(implementation_type& impl,
-      io_context* peer_io_context, endpoint_type* peer_endpoint,
-      asio::error_code& ec)
-  {
-    typename Protocol::socket peer(
-        peer_io_context ? *peer_io_context : io_context_);
-
-    std::size_t addr_len = peer_endpoint ? peer_endpoint->capacity() : 0;
-    socket_holder new_socket(socket_ops::sync_accept(impl.socket_,
-          impl.state_, peer_endpoint ? peer_endpoint->data() : 0,
-          peer_endpoint ? &addr_len : 0, ec));
-
-    // On success, assign new connection to peer socket object.
-    if (new_socket.get() != invalid_socket)
-    {
-      if (peer_endpoint)
-        peer_endpoint->resize(addr_len);
-      peer.assign(impl.protocol_, new_socket.get(), ec);
-      if (!ec)
-        new_socket.release();
-    }
-
-    return peer;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  // Start an asynchronous accept. The peer and peer_endpoint objects
-  // must be valid until the accept's handler is invoked.
-  template <typename Socket, typename Handler>
-  void async_accept(implementation_type& impl, Socket& peer,
-      endpoint_type* peer_endpoint, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_socket_accept_op<Socket, protocol_type, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    bool enable_connection_aborted =
-      (impl.state_ & socket_ops::enable_connection_aborted) != 0;
-    p.p = new (p.v) op(*this, impl.socket_, peer, impl.protocol_,
-        peer_endpoint, enable_connection_aborted, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_accept"));
-
-    start_accept_op(impl, peer.is_open(), p.p->new_socket(),
-        impl.protocol_.family(), impl.protocol_.type(),
-        impl.protocol_.protocol(), p.p->output_buffer(),
-        p.p->address_length(), p.p);
-    p.v = p.p = 0;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  // Start an asynchronous accept. The peer and peer_endpoint objects
-  // must be valid until the accept's handler is invoked.
-  template <typename Handler>
-  void async_accept(implementation_type& impl,
-      asio::io_context* peer_io_context,
-      endpoint_type* peer_endpoint, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_socket_move_accept_op<protocol_type, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    bool enable_connection_aborted =
-      (impl.state_ & socket_ops::enable_connection_aborted) != 0;
-    p.p = new (p.v) op(*this, impl.socket_, impl.protocol_,
-        peer_io_context ? *peer_io_context : io_context_,
-        peer_endpoint, enable_connection_aborted, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_accept"));
-
-    start_accept_op(impl, false, p.p->new_socket(),
-        impl.protocol_.family(), impl.protocol_.type(),
-        impl.protocol_.protocol(), p.p->output_buffer(),
-        p.p->address_length(), p.p);
-    p.v = p.p = 0;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  // Connect the socket to the specified endpoint.
-  asio::error_code connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, asio::error_code& ec)
-  {
-    socket_ops::sync_connect(impl.socket_,
-        peer_endpoint.data(), peer_endpoint.size(), ec);
-    return ec;
-  }
-
-  // Start an asynchronous connect.
-  template <typename Handler>
-  void async_connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_socket_connect_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.socket_, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_connect"));
-
-    start_connect_op(impl, impl.protocol_.family(), impl.protocol_.type(),
-        peer_endpoint.data(), static_cast<int>(peer_endpoint.size()), p.p);
-    p.v = p.p = 0;
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_SOCKET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_socket_service_base.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_socket_service_base.hpp
deleted file mode 100644
index ef1d7180e36..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_socket_service_base.hpp
+++ /dev/null
@@ -1,591 +0,0 @@
-//
-// detail/win_iocp_socket_service_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_SOCKET_SERVICE_BASE_HPP
-#define ASIO_DETAIL_WIN_IOCP_SOCKET_SERVICE_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/socket_base.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/operation.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/select_reactor.hpp"
-#include "asio/detail/socket_holder.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/win_iocp_io_context.hpp"
-#include "asio/detail/win_iocp_null_buffers_op.hpp"
-#include "asio/detail/win_iocp_socket_connect_op.hpp"
-#include "asio/detail/win_iocp_socket_send_op.hpp"
-#include "asio/detail/win_iocp_socket_recv_op.hpp"
-#include "asio/detail/win_iocp_socket_recvmsg_op.hpp"
-#include "asio/detail/win_iocp_wait_op.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class win_iocp_socket_service_base
-{
-public:
-  // The implementation type of the socket.
-  struct base_implementation_type
-  {
-    // The native socket representation.
-    socket_type socket_;
-
-    // The current state of the socket.
-    socket_ops::state_type state_;
-
-    // We use a shared pointer as a cancellation token here to work around the
-    // broken Windows support for cancellation. MSDN says that when you call
-    // closesocket any outstanding WSARecv or WSASend operations will complete
-    // with the error ERROR_OPERATION_ABORTED. In practice they complete with
-    // ERROR_NETNAME_DELETED, which means you can't tell the difference between
-    // a local cancellation and the socket being hard-closed by the peer.
-    socket_ops::shared_cancel_token_type cancel_token_;
-
-    // Per-descriptor data used by the reactor.
-    select_reactor::per_descriptor_data reactor_data_;
-
-#if defined(ASIO_ENABLE_CANCELIO)
-    // The ID of the thread from which it is safe to cancel asynchronous
-    // operations. 0 means no asynchronous operations have been started yet.
-    // ~0 means asynchronous operations have been started from more than one
-    // thread, and cancellation is not supported for the socket.
-    DWORD safe_cancellation_thread_id_;
-#endif // defined(ASIO_ENABLE_CANCELIO)
-
-    // Pointers to adjacent socket implementations in linked list.
-    base_implementation_type* next_;
-    base_implementation_type* prev_;
-  };
-
-  // Constructor.
-  ASIO_DECL win_iocp_socket_service_base(
-      asio::io_context& io_context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void base_shutdown();
-
-  // Construct a new socket implementation.
-  ASIO_DECL void construct(base_implementation_type& impl);
-
-  // Move-construct a new socket implementation.
-  ASIO_DECL void base_move_construct(base_implementation_type& impl,
-      base_implementation_type& other_impl);
-
-  // Move-assign from another socket implementation.
-  ASIO_DECL void base_move_assign(base_implementation_type& impl,
-      win_iocp_socket_service_base& other_service,
-      base_implementation_type& other_impl);
-
-  // Destroy a socket implementation.
-  ASIO_DECL void destroy(base_implementation_type& impl);
-
-  // Determine whether the socket is open.
-  bool is_open(const base_implementation_type& impl) const
-  {
-    return impl.socket_ != invalid_socket;
-  }
-
-  // Destroy a socket implementation.
-  ASIO_DECL asio::error_code close(
-      base_implementation_type& impl, asio::error_code& ec);
-
-  // Release ownership of the socket.
-  ASIO_DECL socket_type release(
-      base_implementation_type& impl, asio::error_code& ec);
-
-  // Cancel all operations associated with the socket.
-  ASIO_DECL asio::error_code cancel(
-      base_implementation_type& impl, asio::error_code& ec);
-
-  // Determine whether the socket is at the out-of-band data mark.
-  bool at_mark(const base_implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return socket_ops::sockatmark(impl.socket_, ec);
-  }
-
-  // Determine the number of bytes available for reading.
-  std::size_t available(const base_implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return socket_ops::available(impl.socket_, ec);
-  }
-
-  // Place the socket into the state where it will listen for new connections.
-  asio::error_code listen(base_implementation_type& impl,
-      int backlog, asio::error_code& ec)
-  {
-    socket_ops::listen(impl.socket_, backlog, ec);
-    return ec;
-  }
-
-  // Perform an IO control command on the socket.
-  template <typename IO_Control_Command>
-  asio::error_code io_control(base_implementation_type& impl,
-      IO_Control_Command& command, asio::error_code& ec)
-  {
-    socket_ops::ioctl(impl.socket_, impl.state_, command.name(),
-        static_cast<ioctl_arg_type*>(command.data()), ec);
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the socket.
-  bool non_blocking(const base_implementation_type& impl) const
-  {
-    return (impl.state_ & socket_ops::user_set_non_blocking) != 0;
-  }
-
-  // Sets the non-blocking mode of the socket.
-  asio::error_code non_blocking(base_implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    socket_ops::set_user_non_blocking(impl.socket_, impl.state_, mode, ec);
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the native socket implementation.
-  bool native_non_blocking(const base_implementation_type& impl) const
-  {
-    return (impl.state_ & socket_ops::internal_non_blocking) != 0;
-  }
-
-  // Sets the non-blocking mode of the native socket implementation.
-  asio::error_code native_non_blocking(base_implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    socket_ops::set_internal_non_blocking(impl.socket_, impl.state_, mode, ec);
-    return ec;
-  }
-
-  // Wait for the socket to become ready to read, ready to write, or to have
-  // pending error conditions.
-  asio::error_code wait(base_implementation_type& impl,
-      socket_base::wait_type w, asio::error_code& ec)
-  {
-    switch (w)
-    {
-    case socket_base::wait_read:
-      socket_ops::poll_read(impl.socket_, impl.state_, -1, ec);
-      break;
-    case socket_base::wait_write:
-      socket_ops::poll_write(impl.socket_, impl.state_, -1, ec);
-      break;
-    case socket_base::wait_error:
-      socket_ops::poll_error(impl.socket_, impl.state_, -1, ec);
-      break;
-    default:
-      ec = asio::error::invalid_argument;
-      break;
-    }
-
-    return ec;
-  }
-
-  // Asynchronously wait for the socket to become ready to read, ready to
-  // write, or to have pending error conditions.
-  template <typename Handler>
-  void async_wait(base_implementation_type& impl,
-      socket_base::wait_type w, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_wait_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.cancel_token_, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_wait"));
-
-    switch (w)
-    {
-      case socket_base::wait_read:
-        start_null_buffers_receive_op(impl, 0, p.p);
-        break;
-      case socket_base::wait_write:
-        start_reactor_op(impl, select_reactor::write_op, p.p);
-        break;
-      case socket_base::wait_error:
-        start_reactor_op(impl, select_reactor::except_op, p.p);
-        break;
-      default:
-        p.p->ec_ = asio::error::invalid_argument;
-        iocp_service_.post_immediate_completion(p.p, is_continuation);
-        break;
-    }
-
-    p.v = p.p = 0;
-  }
-
-  // Send the given data to the peer. Returns the number of bytes sent.
-  template <typename ConstBufferSequence>
-  size_t send(base_implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(buffers);
-
-    return socket_ops::sync_send(impl.socket_, impl.state_,
-        bufs.buffers(), bufs.count(), flags, bufs.all_empty(), ec);
-  }
-
-  // Wait until data can be sent without blocking.
-  size_t send(base_implementation_type& impl, const null_buffers&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_write(impl.socket_, impl.state_, -1, ec);
-
-    return 0;
-  }
-
-  // Start an asynchronous send. The data being sent must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_send(base_implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_socket_send_op<ConstBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.cancel_token_, buffers, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_send"));
-
-    buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence> bufs(buffers);
-
-    start_send_op(impl, bufs.buffers(), bufs.count(), flags,
-        (impl.state_ & socket_ops::stream_oriented) != 0 && bufs.all_empty(),
-        p.p);
-    p.v = p.p = 0;
-  }
-
-  // Start an asynchronous wait until data can be sent without blocking.
-  template <typename Handler>
-  void async_send(base_implementation_type& impl, const null_buffers&,
-      socket_base::message_flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.cancel_token_, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_send(null_buffers)"));
-
-    start_reactor_op(impl, select_reactor::write_op, p.p);
-    p.v = p.p = 0;
-  }
-
-  // Receive some data from the peer. Returns the number of bytes received.
-  template <typename MutableBufferSequence>
-  size_t receive(base_implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    return socket_ops::sync_recv(impl.socket_, impl.state_,
-        bufs.buffers(), bufs.count(), flags, bufs.all_empty(), ec);
-  }
-
-  // Wait until data can be received without blocking.
-  size_t receive(base_implementation_type& impl, const null_buffers&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_read(impl.socket_, impl.state_, -1, ec);
-
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received
-  // must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive(base_implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_socket_recv_op<MutableBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.state_, impl.cancel_token_, buffers, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_receive"));
-
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    start_receive_op(impl, bufs.buffers(), bufs.count(), flags,
-        (impl.state_ & socket_ops::stream_oriented) != 0 && bufs.all_empty(),
-        p.p);
-    p.v = p.p = 0;
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive(base_implementation_type& impl, const null_buffers&,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.cancel_token_, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_receive(null_buffers)"));
-
-    start_null_buffers_receive_op(impl, flags, p.p);
-    p.v = p.p = 0;
-  }
-
-  // Receive some data with associated flags. Returns the number of bytes
-  // received.
-  template <typename MutableBufferSequence>
-  size_t receive_with_flags(base_implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, asio::error_code& ec)
-  {
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    return socket_ops::sync_recvmsg(impl.socket_, impl.state_,
-        bufs.buffers(), bufs.count(), in_flags, out_flags, ec);
-  }
-
-  // Wait until data can be received without blocking.
-  size_t receive_with_flags(base_implementation_type& impl,
-      const null_buffers&, socket_base::message_flags,
-      socket_base::message_flags& out_flags, asio::error_code& ec)
-  {
-    // Wait for socket to become ready.
-    socket_ops::poll_read(impl.socket_, impl.state_, -1, ec);
-
-    // Clear out_flags, since we cannot give it any other sensible value when
-    // performing a null_buffers operation.
-    out_flags = 0;
-
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received
-  // must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive_with_flags(base_implementation_type& impl,
-      const MutableBufferSequence& buffers, socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_socket_recvmsg_op<MutableBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.cancel_token_, buffers, out_flags, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_receive_with_flags"));
-
-    buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence> bufs(buffers);
-
-    start_receive_op(impl, bufs.buffers(), bufs.count(), in_flags, false, p.p);
-    p.v = p.p = 0;
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive_with_flags(base_implementation_type& impl,
-      const null_buffers&, socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef win_iocp_null_buffers_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(impl.cancel_token_, handler);
-
-    ASIO_HANDLER_CREATION((io_context_, *p.p, "socket",
-          &impl, impl.socket_, "async_receive_with_flags(null_buffers)"));
-
-    // Reset out_flags since it can be given no sensible value at this time.
-    out_flags = 0;
-
-    start_null_buffers_receive_op(impl, in_flags, p.p);
-    p.v = p.p = 0;
-  }
-
-  // Helper function to restart an asynchronous accept operation.
-  ASIO_DECL void restart_accept_op(socket_type s,
-      socket_holder& new_socket, int family, int type, int protocol,
-      void* output_buffer, DWORD address_length, operation* op);
-
-protected:
-  // Open a new socket implementation.
-  ASIO_DECL asio::error_code do_open(
-      base_implementation_type& impl, int family, int type,
-      int protocol, asio::error_code& ec);
-
-  // Assign a native socket to a socket implementation.
-  ASIO_DECL asio::error_code do_assign(
-      base_implementation_type& impl, int type,
-      socket_type native_socket, asio::error_code& ec);
-
-  // Helper function to start an asynchronous send operation.
-  ASIO_DECL void start_send_op(base_implementation_type& impl,
-      WSABUF* buffers, std::size_t buffer_count,
-      socket_base::message_flags flags, bool noop, operation* op);
-
-  // Helper function to start an asynchronous send_to operation.
-  ASIO_DECL void start_send_to_op(base_implementation_type& impl,
-      WSABUF* buffers, std::size_t buffer_count,
-      const socket_addr_type* addr, int addrlen,
-      socket_base::message_flags flags, operation* op);
-
-  // Helper function to start an asynchronous receive operation.
-  ASIO_DECL void start_receive_op(base_implementation_type& impl,
-      WSABUF* buffers, std::size_t buffer_count,
-      socket_base::message_flags flags, bool noop, operation* op);
-
-  // Helper function to start an asynchronous null_buffers receive operation.
-  ASIO_DECL void start_null_buffers_receive_op(
-      base_implementation_type& impl,
-      socket_base::message_flags flags, reactor_op* op);
-
-  // Helper function to start an asynchronous receive_from operation.
-  ASIO_DECL void start_receive_from_op(base_implementation_type& impl,
-      WSABUF* buffers, std::size_t buffer_count, socket_addr_type* addr,
-      socket_base::message_flags flags, int* addrlen, operation* op);
-
-  // Helper function to start an asynchronous accept operation.
-  ASIO_DECL void start_accept_op(base_implementation_type& impl,
-      bool peer_is_open, socket_holder& new_socket, int family, int type,
-      int protocol, void* output_buffer, DWORD address_length, operation* op);
-
-  // Start an asynchronous read or write operation using the reactor.
-  ASIO_DECL void start_reactor_op(base_implementation_type& impl,
-      int op_type, reactor_op* op);
-
-  // Start the asynchronous connect operation using the reactor.
-  ASIO_DECL void start_connect_op(base_implementation_type& impl,
-      int family, int type, const socket_addr_type* remote_addr,
-      std::size_t remote_addrlen, win_iocp_socket_connect_op_base* op);
-
-  // Helper function to close a socket when the associated object is being
-  // destroyed.
-  ASIO_DECL void close_for_destruction(base_implementation_type& impl);
-
-  // Update the ID of the thread from which cancellation is safe.
-  ASIO_DECL void update_cancellation_thread_id(
-      base_implementation_type& impl);
-
-  // Helper function to get the reactor. If no reactor has been created yet, a
-  // new one is obtained from the io_context and a pointer to it is cached in
-  // this service.
-  ASIO_DECL select_reactor& get_reactor();
-
-  // The type of a ConnectEx function pointer, as old SDKs may not provide it.
-  typedef BOOL (PASCAL *connect_ex_fn)(SOCKET,
-      const socket_addr_type*, int, void*, DWORD, DWORD*, OVERLAPPED*);
-
-  // Helper function to get the ConnectEx pointer. If no ConnectEx pointer has
-  // been obtained yet, one is obtained using WSAIoctl and the pointer is
-  // cached. Returns a null pointer if ConnectEx is not available.
-  ASIO_DECL connect_ex_fn get_connect_ex(
-      base_implementation_type& impl, int type);
-
-  // The type of a NtSetInformationFile function pointer.
-  typedef LONG (NTAPI *nt_set_info_fn)(HANDLE, ULONG_PTR*, void*, ULONG, ULONG);
-
-  // Helper function to get the NtSetInformationFile function pointer. If no
-  // NtSetInformationFile pointer has been obtained yet, one is obtained using
-  // GetProcAddress and the pointer is cached. Returns a null pointer if
-  // NtSetInformationFile is not available.
-  ASIO_DECL nt_set_info_fn get_nt_set_info();
-
-  // Helper function to emulate InterlockedCompareExchangePointer functionality
-  // for:
-  // - very old Platform SDKs; and
-  // - platform SDKs where MSVC's /Wp64 option causes spurious warnings.
-  ASIO_DECL void* interlocked_compare_exchange_pointer(
-      void** dest, void* exch, void* cmp);
-
-  // Helper function to emulate InterlockedExchangePointer functionality for:
-  // - very old Platform SDKs; and
-  // - platform SDKs where MSVC's /Wp64 option causes spurious warnings.
-  ASIO_DECL void* interlocked_exchange_pointer(void** dest, void* val);
-
-  // The io_context used to obtain the reactor, if required.
-  asio::io_context& io_context_;
-
-  // The IOCP service used for running asynchronous operations and dispatching
-  // handlers.
-  win_iocp_io_context& iocp_service_;
-
-  // The reactor used for performing connect operations. This object is created
-  // only if needed.
-  select_reactor* reactor_;
-
-  // Pointer to ConnectEx implementation.
-  void* connect_ex_;
-
-  // Pointer to NtSetInformationFile implementation.
-  void* nt_set_info_;
-
-  // Mutex to protect access to the linked list of implementations. 
-  asio::detail::mutex mutex_;
-
-  // The head of a linked list of all implementations.
-  base_implementation_type* impl_list_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_iocp_socket_service_base.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_SOCKET_SERVICE_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_thread_info.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_thread_info.hpp
deleted file mode 100644
index 13181e2ec6d..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_thread_info.hpp
+++ /dev/null
@@ -1,34 +0,0 @@
-//
-// detail/win_iocp_thread_info.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_THREAD_INFO_HPP
-#define ASIO_DETAIL_WIN_IOCP_THREAD_INFO_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/thread_info_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-struct win_iocp_thread_info : public thread_info_base
-{
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_WIN_IOCP_THREAD_INFO_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_iocp_wait_op.hpp b/tools/sdk/include/asio/asio/detail/win_iocp_wait_op.hpp
deleted file mode 100644
index 472eea38a32..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_iocp_wait_op.hpp
+++ /dev/null
@@ -1,121 +0,0 @@
-//
-// detail/win_iocp_wait_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_IOCP_WAIT_OP_HPP
-#define ASIO_DETAIL_WIN_IOCP_WAIT_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/reactor_op.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class win_iocp_wait_op : public reactor_op
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(win_iocp_wait_op);
-
-  win_iocp_wait_op(socket_ops::weak_cancel_token_type cancel_token,
-      Handler& handler)
-    : reactor_op(&win_iocp_wait_op::do_perform,
-        &win_iocp_wait_op::do_complete),
-      cancel_token_(cancel_token),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static status do_perform(reactor_op*)
-  {
-    return done;
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code& result_ec,
-      std::size_t /*bytes_transferred*/)
-  {
-    asio::error_code ec(result_ec);
-
-    // Take ownership of the operation object.
-    win_iocp_wait_op* o(static_cast<win_iocp_wait_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // The reactor may have stored a result in the operation object.
-    if (o->ec_)
-      ec = o->ec_;
-
-    // Map non-portable errors to their portable counterparts.
-    if (ec.value() == ERROR_NETNAME_DELETED)
-    {
-      if (o->cancel_token_.expired())
-        ec = asio::error::operation_aborted;
-      else
-        ec = asio::error::connection_reset;
-    }
-    else if (ec.value() == ERROR_PORT_UNREACHABLE)
-    {
-      ec = asio::error::connection_refused;
-    }
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder1<Handler, asio::error_code>
-      handler(o->handler_, ec);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  socket_ops::weak_cancel_token_type cancel_token_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_IOCP)
-
-#endif // ASIO_DETAIL_WIN_IOCP_WAIT_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_mutex.hpp b/tools/sdk/include/asio/asio/detail/win_mutex.hpp
deleted file mode 100644
index ce52a2f7968..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_mutex.hpp
+++ /dev/null
@@ -1,78 +0,0 @@
-//
-// detail/win_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_MUTEX_HPP
-#define ASIO_DETAIL_WIN_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS)
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/scoped_lock.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class win_mutex
-  : private noncopyable
-{
-public:
-  typedef asio::detail::scoped_lock<win_mutex> scoped_lock;
-
-  // Constructor.
-  ASIO_DECL win_mutex();
-
-  // Destructor.
-  ~win_mutex()
-  {
-    ::DeleteCriticalSection(&crit_section_);
-  }
-
-  // Lock the mutex.
-  void lock()
-  {
-    ::EnterCriticalSection(&crit_section_);
-  }
-
-  // Unlock the mutex.
-  void unlock()
-  {
-    ::LeaveCriticalSection(&crit_section_);
-  }
-
-private:
-  // Initialisation must be performed in a separate function to the constructor
-  // since the compiler does not support the use of structured exceptions and
-  // C++ exceptions in the same function.
-  ASIO_DECL int do_init();
-
-  ::CRITICAL_SECTION crit_section_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_mutex.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_WINDOWS)
-
-#endif // ASIO_DETAIL_WIN_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_object_handle_service.hpp b/tools/sdk/include/asio/asio/detail/win_object_handle_service.hpp
deleted file mode 100644
index 1d8abc9c74a..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_object_handle_service.hpp
+++ /dev/null
@@ -1,184 +0,0 @@
-//
-// detail/win_object_handle_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2011 Boris Schaeling (boris@highscore.de)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_OBJECT_HANDLE_SERVICE_HPP
-#define ASIO_DETAIL_WIN_OBJECT_HANDLE_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE)
-
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/wait_handler.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class win_object_handle_service :
-  public service_base<win_object_handle_service>
-{
-public:
-  // The native type of an object handle.
-  typedef HANDLE native_handle_type;
-
-  // The implementation type of the object handle.
-  class implementation_type
-  {
-   public:
-    // Default constructor.
-    implementation_type()
-      : handle_(INVALID_HANDLE_VALUE),
-        wait_handle_(INVALID_HANDLE_VALUE),
-        owner_(0),
-        next_(0),
-        prev_(0)
-    {
-    }
-
-  private:
-    // Only this service will have access to the internal values.
-    friend class win_object_handle_service;
-
-    // The native object handle representation. May be accessed or modified
-    // without locking the mutex.
-    native_handle_type handle_;
-
-    // The handle used to unregister the wait operation. The mutex must be
-    // locked when accessing or modifying this member.
-    HANDLE wait_handle_;
-
-    // The operations waiting on the object handle. If there is a registered
-    // wait then the mutex must be locked when accessing or modifying this
-    // member
-    op_queue<wait_op> op_queue_;
-
-    // The service instance that owns the object handle implementation.
-    win_object_handle_service* owner_;
-
-    // Pointers to adjacent handle implementations in linked list. The mutex
-    // must be locked when accessing or modifying these members.
-    implementation_type* next_;
-    implementation_type* prev_;
-  };
-
-  // Constructor.
-  ASIO_DECL win_object_handle_service(
-      asio::io_context& io_context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Construct a new handle implementation.
-  ASIO_DECL void construct(implementation_type& impl);
-
-  // Move-construct a new handle implementation.
-  ASIO_DECL void move_construct(implementation_type& impl,
-      implementation_type& other_impl);
-
-  // Move-assign from another handle implementation.
-  ASIO_DECL void move_assign(implementation_type& impl,
-      win_object_handle_service& other_service,
-      implementation_type& other_impl);
-
-  // Destroy a handle implementation.
-  ASIO_DECL void destroy(implementation_type& impl);
-
-  // Assign a native handle to a handle implementation.
-  ASIO_DECL asio::error_code assign(implementation_type& impl,
-      const native_handle_type& handle, asio::error_code& ec);
-
-  // Determine whether the handle is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return impl.handle_ != INVALID_HANDLE_VALUE && impl.handle_ != 0;
-  }
-
-  // Destroy a handle implementation.
-  ASIO_DECL asio::error_code close(implementation_type& impl,
-      asio::error_code& ec);
-
-  // Get the native handle representation.
-  native_handle_type native_handle(const implementation_type& impl) const
-  {
-    return impl.handle_;
-  }
-
-  // Cancel all operations associated with the handle.
-  ASIO_DECL asio::error_code cancel(implementation_type& impl,
-      asio::error_code& ec);
-
-  // Perform a synchronous wait for the object to enter a signalled state.
-  ASIO_DECL void wait(implementation_type& impl,
-      asio::error_code& ec);
-
-  /// Start an asynchronous wait.
-  template <typename Handler>
-  void async_wait(implementation_type& impl, Handler& handler)
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef wait_handler<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((io_context_.context(), *p.p, "object_handle",
-          &impl, reinterpret_cast<uintmax_t>(impl.wait_handle_), "async_wait"));
-
-    start_wait_op(impl, p.p);
-    p.v = p.p = 0;
-  }
-
-private:
-  // Helper function to start an asynchronous wait operation.
-  ASIO_DECL void start_wait_op(implementation_type& impl, wait_op* op);
-
-  // Helper function to register a wait operation.
-  ASIO_DECL void register_wait_callback(
-      implementation_type& impl, mutex::scoped_lock& lock);
-
-  // Callback function invoked when the registered wait completes.
-  static ASIO_DECL VOID CALLBACK wait_callback(
-      PVOID param, BOOLEAN timeout);
-
-  // The io_context implementation used to post completions.
-  io_context_impl& io_context_;
-
-  // Mutex to protect access to internal state.
-  mutex mutex_;
-
-  // The head of a linked list of all implementations.
-  implementation_type* impl_list_;
-
-  // Flag to indicate that the dispatcher has been shut down.
-  bool shutdown_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_object_handle_service.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE)
-
-#endif // ASIO_DETAIL_WIN_OBJECT_HANDLE_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_static_mutex.hpp b/tools/sdk/include/asio/asio/detail/win_static_mutex.hpp
deleted file mode 100644
index b16968862cc..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_static_mutex.hpp
+++ /dev/null
@@ -1,74 +0,0 @@
-//
-// detail/win_static_mutex.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_STATIC_MUTEX_HPP
-#define ASIO_DETAIL_WIN_STATIC_MUTEX_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS)
-
-#include "asio/detail/scoped_lock.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-struct win_static_mutex
-{
-  typedef asio::detail::scoped_lock<win_static_mutex> scoped_lock;
-
-  // Initialise the mutex.
-  ASIO_DECL void init();
-
-  // Initialisation must be performed in a separate function to the "public"
-  // init() function since the compiler does not support the use of structured
-  // exceptions and C++ exceptions in the same function.
-  ASIO_DECL int do_init();
-
-  // Lock the mutex.
-  void lock()
-  {
-    ::EnterCriticalSection(&crit_section_);
-  }
-
-  // Unlock the mutex.
-  void unlock()
-  {
-    ::LeaveCriticalSection(&crit_section_);
-  }
-
-  bool initialised_;
-  ::CRITICAL_SECTION crit_section_;
-};
-
-#if defined(UNDER_CE)
-# define ASIO_WIN_STATIC_MUTEX_INIT { false, { 0, 0, 0, 0, 0 } }
-#else // defined(UNDER_CE)
-# define ASIO_WIN_STATIC_MUTEX_INIT { false, { 0, 0, 0, 0, 0, 0 } }
-#endif // defined(UNDER_CE)
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_static_mutex.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_WINDOWS)
-
-#endif // ASIO_DETAIL_WIN_STATIC_MUTEX_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_thread.hpp b/tools/sdk/include/asio/asio/detail/win_thread.hpp
deleted file mode 100644
index 8b28a90b679..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_thread.hpp
+++ /dev/null
@@ -1,147 +0,0 @@
-//
-// detail/win_thread.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_THREAD_HPP
-#define ASIO_DETAIL_WIN_THREAD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS) \
-  && !defined(ASIO_WINDOWS_APP) \
-  && !defined(UNDER_CE)
-
-#include <cstddef>
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-ASIO_DECL unsigned int __stdcall win_thread_function(void* arg);
-
-#if defined(WINVER) && (WINVER < 0x0500)
-ASIO_DECL void __stdcall apc_function(ULONG data);
-#else
-ASIO_DECL void __stdcall apc_function(ULONG_PTR data);
-#endif
-
-template <typename T>
-class win_thread_base
-{
-public:
-  static bool terminate_threads()
-  {
-    return ::InterlockedExchangeAdd(&terminate_threads_, 0) != 0;
-  }
-
-  static void set_terminate_threads(bool b)
-  {
-    ::InterlockedExchange(&terminate_threads_, b ? 1 : 0);
-  }
-
-private:
-  static long terminate_threads_;
-};
-
-template <typename T>
-long win_thread_base<T>::terminate_threads_ = 0;
-
-class win_thread
-  : private noncopyable,
-    public win_thread_base<win_thread>
-{
-public:
-  // Constructor.
-  template <typename Function>
-  win_thread(Function f, unsigned int stack_size = 0)
-    : thread_(0),
-      exit_event_(0)
-  {
-    start_thread(new func<Function>(f), stack_size);
-  }
-
-  // Destructor.
-  ASIO_DECL ~win_thread();
-
-  // Wait for the thread to exit.
-  ASIO_DECL void join();
-
-  // Get number of CPUs.
-  ASIO_DECL static std::size_t hardware_concurrency();
-
-private:
-  friend ASIO_DECL unsigned int __stdcall win_thread_function(void* arg);
-
-#if defined(WINVER) && (WINVER < 0x0500)
-  friend ASIO_DECL void __stdcall apc_function(ULONG);
-#else
-  friend ASIO_DECL void __stdcall apc_function(ULONG_PTR);
-#endif
-
-  class func_base
-  {
-  public:
-    virtual ~func_base() {}
-    virtual void run() = 0;
-    ::HANDLE entry_event_;
-    ::HANDLE exit_event_;
-  };
-
-  struct auto_func_base_ptr
-  {
-    func_base* ptr;
-    ~auto_func_base_ptr() { delete ptr; }
-  };
-
-  template <typename Function>
-  class func
-    : public func_base
-  {
-  public:
-    func(Function f)
-      : f_(f)
-    {
-    }
-
-    virtual void run()
-    {
-      f_();
-    }
-
-  private:
-    Function f_;
-  };
-
-  ASIO_DECL void start_thread(func_base* arg, unsigned int stack_size);
-
-  ::HANDLE thread_;
-  ::HANDLE exit_event_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_thread.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_WINDOWS)
-       // && !defined(ASIO_WINDOWS_APP)
-       // && !defined(UNDER_CE)
-
-#endif // ASIO_DETAIL_WIN_THREAD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/win_tss_ptr.hpp b/tools/sdk/include/asio/asio/detail/win_tss_ptr.hpp
deleted file mode 100644
index 4207108a30e..00000000000
--- a/tools/sdk/include/asio/asio/detail/win_tss_ptr.hpp
+++ /dev/null
@@ -1,79 +0,0 @@
-//
-// detail/win_tss_ptr.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WIN_TSS_PTR_HPP
-#define ASIO_DETAIL_WIN_TSS_PTR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS)
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-// Helper function to create thread-specific storage.
-ASIO_DECL DWORD win_tss_ptr_create();
-
-template <typename T>
-class win_tss_ptr
-  : private noncopyable
-{
-public:
-  // Constructor.
-  win_tss_ptr()
-    : tss_key_(win_tss_ptr_create())
-  {
-  }
-
-  // Destructor.
-  ~win_tss_ptr()
-  {
-    ::TlsFree(tss_key_);
-  }
-
-  // Get the value.
-  operator T*() const
-  {
-    return static_cast<T*>(::TlsGetValue(tss_key_));
-  }
-
-  // Set the value.
-  void operator=(T* value)
-  {
-    ::TlsSetValue(tss_key_, value);
-  }
-
-private:
-  // Thread-specific storage to allow unlocked access to determine whether a
-  // thread is a member of the pool.
-  DWORD tss_key_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/win_tss_ptr.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_WINDOWS)
-
-#endif // ASIO_DETAIL_WIN_TSS_PTR_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winapp_thread.hpp b/tools/sdk/include/asio/asio/detail/winapp_thread.hpp
deleted file mode 100644
index 69dcf08d4e1..00000000000
--- a/tools/sdk/include/asio/asio/detail/winapp_thread.hpp
+++ /dev/null
@@ -1,124 +0,0 @@
-//
-// detail/winapp_thread.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINAPP_THREAD_HPP
-#define ASIO_DETAIL_WINAPP_THREAD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS) && defined(ASIO_WINDOWS_APP)
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/scoped_ptr.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-DWORD WINAPI winapp_thread_function(LPVOID arg);
-
-class winapp_thread
-  : private noncopyable
-{
-public:
-  // Constructor.
-  template <typename Function>
-  winapp_thread(Function f, unsigned int = 0)
-  {
-    scoped_ptr<func_base> arg(new func<Function>(f));
-    DWORD thread_id = 0;
-    thread_ = ::CreateThread(0, 0, winapp_thread_function,
-        arg.get(), 0, &thread_id);
-    if (!thread_)
-    {
-      DWORD last_error = ::GetLastError();
-      asio::error_code ec(last_error,
-          asio::error::get_system_category());
-      asio::detail::throw_error(ec, "thread");
-    }
-    arg.release();
-  }
-
-  // Destructor.
-  ~winapp_thread()
-  {
-    ::CloseHandle(thread_);
-  }
-
-  // Wait for the thread to exit.
-  void join()
-  {
-    ::WaitForSingleObjectEx(thread_, INFINITE, false);
-  }
-
-  // Get number of CPUs.
-  static std::size_t hardware_concurrency()
-  {
-    SYSTEM_INFO system_info;
-    ::GetNativeSystemInfo(&system_info);
-    return system_info.dwNumberOfProcessors;
-  }
-
-private:
-  friend DWORD WINAPI winapp_thread_function(LPVOID arg);
-
-  class func_base
-  {
-  public:
-    virtual ~func_base() {}
-    virtual void run() = 0;
-  };
-
-  template <typename Function>
-  class func
-    : public func_base
-  {
-  public:
-    func(Function f)
-      : f_(f)
-    {
-    }
-
-    virtual void run()
-    {
-      f_();
-    }
-
-  private:
-    Function f_;
-  };
-
-  ::HANDLE thread_;
-};
-
-inline DWORD WINAPI winapp_thread_function(LPVOID arg)
-{
-  scoped_ptr<winapp_thread::func_base> func(
-      static_cast<winapp_thread::func_base*>(arg));
-  func->run();
-  return 0;
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS) && defined(ASIO_WINDOWS_APP)
-
-#endif // ASIO_DETAIL_WINAPP_THREAD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/wince_thread.hpp b/tools/sdk/include/asio/asio/detail/wince_thread.hpp
deleted file mode 100644
index a2863f625da..00000000000
--- a/tools/sdk/include/asio/asio/detail/wince_thread.hpp
+++ /dev/null
@@ -1,124 +0,0 @@
-//
-// detail/wince_thread.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINCE_THREAD_HPP
-#define ASIO_DETAIL_WINCE_THREAD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS) && defined(UNDER_CE)
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/scoped_ptr.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-DWORD WINAPI wince_thread_function(LPVOID arg);
-
-class wince_thread
-  : private noncopyable
-{
-public:
-  // Constructor.
-  template <typename Function>
-  wince_thread(Function f, unsigned int = 0)
-  {
-    scoped_ptr<func_base> arg(new func<Function>(f));
-    DWORD thread_id = 0;
-    thread_ = ::CreateThread(0, 0, wince_thread_function,
-        arg.get(), 0, &thread_id);
-    if (!thread_)
-    {
-      DWORD last_error = ::GetLastError();
-      asio::error_code ec(last_error,
-          asio::error::get_system_category());
-      asio::detail::throw_error(ec, "thread");
-    }
-    arg.release();
-  }
-
-  // Destructor.
-  ~wince_thread()
-  {
-    ::CloseHandle(thread_);
-  }
-
-  // Wait for the thread to exit.
-  void join()
-  {
-    ::WaitForSingleObject(thread_, INFINITE);
-  }
-
-  // Get number of CPUs.
-  static std::size_t hardware_concurrency()
-  {
-    SYSTEM_INFO system_info;
-    ::GetSystemInfo(&system_info);
-    return system_info.dwNumberOfProcessors;
-  }
-
-private:
-  friend DWORD WINAPI wince_thread_function(LPVOID arg);
-
-  class func_base
-  {
-  public:
-    virtual ~func_base() {}
-    virtual void run() = 0;
-  };
-
-  template <typename Function>
-  class func
-    : public func_base
-  {
-  public:
-    func(Function f)
-      : f_(f)
-    {
-    }
-
-    virtual void run()
-    {
-      f_();
-    }
-
-  private:
-    Function f_;
-  };
-
-  ::HANDLE thread_;
-};
-
-inline DWORD WINAPI wince_thread_function(LPVOID arg)
-{
-  scoped_ptr<wince_thread::func_base> func(
-      static_cast<wince_thread::func_base*>(arg));
-  func->run();
-  return 0;
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS) && defined(UNDER_CE)
-
-#endif // ASIO_DETAIL_WINCE_THREAD_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_async_manager.hpp b/tools/sdk/include/asio/asio/detail/winrt_async_manager.hpp
deleted file mode 100644
index e22ad52e2e7..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_async_manager.hpp
+++ /dev/null
@@ -1,294 +0,0 @@
-//
-// detail/winrt_async_manager.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_ASYNC_MANAGER_HPP
-#define ASIO_DETAIL_WINRT_ASYNC_MANAGER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include <future>
-#include "asio/detail/atomic_count.hpp"
-#include "asio/detail/winrt_async_op.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class winrt_async_manager
-  : public asio::detail::service_base<winrt_async_manager>
-{
-public:
-  // Constructor.
-  winrt_async_manager(asio::io_context& io_context)
-    : asio::detail::service_base<winrt_async_manager>(io_context),
-      io_context_(use_service<io_context_impl>(io_context)),
-      outstanding_ops_(1)
-  {
-  }
-
-  // Destructor.
-  ~winrt_async_manager()
-  {
-  }
-
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    if (--outstanding_ops_ > 0)
-    {
-      // Block until last operation is complete.
-      std::future<void> f = promise_.get_future();
-      f.wait();
-    }
-  }
-
-  void sync(Windows::Foundation::IAsyncAction^ action,
-      asio::error_code& ec)
-  {
-    using namespace Windows::Foundation;
-    using Windows::Foundation::AsyncStatus;
-
-    auto promise = std::make_shared<std::promise<asio::error_code>>();
-    auto future = promise->get_future();
-
-    action->Completed = ref new AsyncActionCompletedHandler(
-      [promise](IAsyncAction^ action, AsyncStatus status)
-      {
-        switch (status)
-        {
-        case AsyncStatus::Canceled:
-          promise->set_value(asio::error::operation_aborted);
-          break;
-        case AsyncStatus::Error:
-        case AsyncStatus::Completed:
-        default:
-          asio::error_code ec(
-              action->ErrorCode.Value,
-              asio::system_category());
-          promise->set_value(ec);
-          break;
-        }
-      });
-
-    ec = future.get();
-  }
-
-  template <typename TResult>
-  TResult sync(Windows::Foundation::IAsyncOperation<TResult>^ operation,
-      asio::error_code& ec)
-  {
-    using namespace Windows::Foundation;
-    using Windows::Foundation::AsyncStatus;
-
-    auto promise = std::make_shared<std::promise<asio::error_code>>();
-    auto future = promise->get_future();
-
-    operation->Completed = ref new AsyncOperationCompletedHandler<TResult>(
-      [promise](IAsyncOperation<TResult>^ operation, AsyncStatus status)
-      {
-        switch (status)
-        {
-        case AsyncStatus::Canceled:
-          promise->set_value(asio::error::operation_aborted);
-          break;
-        case AsyncStatus::Error:
-        case AsyncStatus::Completed:
-        default:
-          asio::error_code ec(
-              operation->ErrorCode.Value,
-              asio::system_category());
-          promise->set_value(ec);
-          break;
-        }
-      });
-
-    ec = future.get();
-    return operation->GetResults();
-  }
-
-  template <typename TResult, typename TProgress>
-  TResult sync(
-      Windows::Foundation::IAsyncOperationWithProgress<
-        TResult, TProgress>^ operation,
-      asio::error_code& ec)
-  {
-    using namespace Windows::Foundation;
-    using Windows::Foundation::AsyncStatus;
-
-    auto promise = std::make_shared<std::promise<asio::error_code>>();
-    auto future = promise->get_future();
-
-    operation->Completed
-      = ref new AsyncOperationWithProgressCompletedHandler<TResult, TProgress>(
-        [promise](IAsyncOperationWithProgress<TResult, TProgress>^ operation,
-          AsyncStatus status)
-        {
-          switch (status)
-          {
-          case AsyncStatus::Canceled:
-            promise->set_value(asio::error::operation_aborted);
-            break;
-          case AsyncStatus::Started:
-            break;
-          case AsyncStatus::Error:
-          case AsyncStatus::Completed:
-          default:
-            asio::error_code ec(
-                operation->ErrorCode.Value,
-                asio::system_category());
-            promise->set_value(ec);
-            break;
-          }
-        });
-
-    ec = future.get();
-    return operation->GetResults();
-  }
-
-  void async(Windows::Foundation::IAsyncAction^ action,
-      winrt_async_op<void>* handler)
-  {
-    using namespace Windows::Foundation;
-    using Windows::Foundation::AsyncStatus;
-
-    auto on_completed = ref new AsyncActionCompletedHandler(
-      [this, handler](IAsyncAction^ action, AsyncStatus status)
-      {
-        switch (status)
-        {
-        case AsyncStatus::Canceled:
-          handler->ec_ = asio::error::operation_aborted;
-          break;
-        case AsyncStatus::Started:
-          return;
-        case AsyncStatus::Completed:
-        case AsyncStatus::Error:
-        default:
-          handler->ec_ = asio::error_code(
-              action->ErrorCode.Value,
-              asio::system_category());
-          break;
-        }
-        io_context_.post_deferred_completion(handler);
-        if (--outstanding_ops_ == 0)
-          promise_.set_value();
-      });
-
-    io_context_.work_started();
-    ++outstanding_ops_;
-    action->Completed = on_completed;
-  }
-
-  template <typename TResult>
-  void async(Windows::Foundation::IAsyncOperation<TResult>^ operation,
-      winrt_async_op<TResult>* handler)
-  {
-    using namespace Windows::Foundation;
-    using Windows::Foundation::AsyncStatus;
-
-    auto on_completed = ref new AsyncOperationCompletedHandler<TResult>(
-      [this, handler](IAsyncOperation<TResult>^ operation, AsyncStatus status)
-      {
-        switch (status)
-        {
-        case AsyncStatus::Canceled:
-          handler->ec_ = asio::error::operation_aborted;
-          break;
-        case AsyncStatus::Started:
-          return;
-        case AsyncStatus::Completed:
-          handler->result_ = operation->GetResults();
-          // Fall through.
-        case AsyncStatus::Error:
-        default:
-          handler->ec_ = asio::error_code(
-              operation->ErrorCode.Value,
-              asio::system_category());
-          break;
-        }
-        io_context_.post_deferred_completion(handler);
-        if (--outstanding_ops_ == 0)
-          promise_.set_value();
-      });
-
-    io_context_.work_started();
-    ++outstanding_ops_;
-    operation->Completed = on_completed;
-  }
-
-  template <typename TResult, typename TProgress>
-  void async(
-      Windows::Foundation::IAsyncOperationWithProgress<
-        TResult, TProgress>^ operation,
-      winrt_async_op<TResult>* handler)
-  {
-    using namespace Windows::Foundation;
-    using Windows::Foundation::AsyncStatus;
-
-    auto on_completed
-      = ref new AsyncOperationWithProgressCompletedHandler<TResult, TProgress>(
-        [this, handler](IAsyncOperationWithProgress<
-          TResult, TProgress>^ operation, AsyncStatus status)
-        {
-          switch (status)
-          {
-          case AsyncStatus::Canceled:
-            handler->ec_ = asio::error::operation_aborted;
-            break;
-          case AsyncStatus::Started:
-            return;
-          case AsyncStatus::Completed:
-            handler->result_ = operation->GetResults();
-            // Fall through.
-          case AsyncStatus::Error:
-          default:
-            handler->ec_ = asio::error_code(
-                operation->ErrorCode.Value,
-                asio::system_category());
-            break;
-          }
-          io_context_.post_deferred_completion(handler);
-          if (--outstanding_ops_ == 0)
-            promise_.set_value();
-        });
-
-    io_context_.work_started();
-    ++outstanding_ops_;
-    operation->Completed = on_completed;
-  }
-
-private:
-  // The io_context implementation used to post completed handlers.
-  io_context_impl& io_context_;
-
-  // Count of outstanding operations.
-  atomic_count outstanding_ops_;
-
-  // Used to keep wait for outstanding operations to complete.
-  std::promise<void> promise_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_ASYNC_MANAGER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_async_op.hpp b/tools/sdk/include/asio/asio/detail/winrt_async_op.hpp
deleted file mode 100644
index 75891a4ad1a..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_async_op.hpp
+++ /dev/null
@@ -1,65 +0,0 @@
-//
-// detail/winrt_async_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_ASYNC_OP_HPP
-#define ASIO_DETAIL_WINRT_ASYNC_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/operation.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename TResult>
-class winrt_async_op
-  : public operation
-{
-public:
-  // The error code to be passed to the completion handler.
-  asio::error_code ec_;
-
-  // The result of the operation, to be passed to the completion handler.
-  TResult result_;
-
-protected:
-  winrt_async_op(func_type complete_func)
-    : operation(complete_func),
-      result_()
-  {
-  }
-};
-
-template <>
-class winrt_async_op<void>
-  : public operation
-{
-public:
-  // The error code to be passed to the completion handler.
-  asio::error_code ec_;
-
-protected:
-  winrt_async_op(func_type complete_func)
-    : operation(complete_func)
-  {
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_WINRT_ASYNC_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_resolve_op.hpp b/tools/sdk/include/asio/asio/detail/winrt_resolve_op.hpp
deleted file mode 100644
index 07efd29d20d..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_resolve_op.hpp
+++ /dev/null
@@ -1,118 +0,0 @@
-//
-// detail/winrt_resolve_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_RESOLVE_OP_HPP
-#define ASIO_DETAIL_WINRT_RESOLVE_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/winrt_async_op.hpp"
-#include "asio/ip/basic_resolver_results.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Protocol, typename Handler>
-class winrt_resolve_op :
-  public winrt_async_op<
-    Windows::Foundation::Collections::IVectorView<
-      Windows::Networking::EndpointPair^>^>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(winrt_resolve_op);
-
-  typedef typename Protocol::endpoint endpoint_type;
-  typedef asio::ip::basic_resolver_query<Protocol> query_type;
-  typedef asio::ip::basic_resolver_results<Protocol> results_type;
-
-  winrt_resolve_op(const query_type& query, Handler& handler)
-    : winrt_async_op<
-        Windows::Foundation::Collections::IVectorView<
-          Windows::Networking::EndpointPair^>^>(
-            &winrt_resolve_op::do_complete),
-      query_(query),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code&, std::size_t)
-  {
-    // Take ownership of the operation object.
-    winrt_resolve_op* o(static_cast<winrt_resolve_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    results_type results = results_type();
-    if (!o->ec_)
-    {
-      try
-      {
-        results = results_type::create(o->result_, o->query_.hints(),
-            o->query_.host_name(), o->query_.service_name());
-      }
-      catch (Platform::Exception^ e)
-      {
-        o->ec_ = asio::error_code(e->HResult,
-            asio::system_category());
-      }
-    }
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, results_type>
-      handler(o->handler_, o->ec_, results);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, "..."));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  query_type query_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_RESOLVE_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_resolver_service.hpp b/tools/sdk/include/asio/asio/detail/winrt_resolver_service.hpp
deleted file mode 100644
index aeb44485e57..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_resolver_service.hpp
+++ /dev/null
@@ -1,198 +0,0 @@
-//
-// detail/winrt_resolver_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_RESOLVER_SERVICE_HPP
-#define ASIO_DETAIL_WINRT_RESOLVER_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/ip/basic_resolver_query.hpp"
-#include "asio/ip/basic_resolver_results.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/winrt_async_manager.hpp"
-#include "asio/detail/winrt_resolve_op.hpp"
-#include "asio/detail/winrt_utils.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Protocol>
-class winrt_resolver_service :
-  public service_base<winrt_resolver_service<Protocol> >
-{
-public:
-  // The implementation type of the resolver. A cancellation token is used to
-  // indicate to the asynchronous operation that the operation has been
-  // cancelled.
-  typedef socket_ops::shared_cancel_token_type implementation_type;
-
-  // The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  // The query type.
-  typedef asio::ip::basic_resolver_query<Protocol> query_type;
-
-  // The results type.
-  typedef asio::ip::basic_resolver_results<Protocol> results_type;
-
-  // Constructor.
-  winrt_resolver_service(asio::io_context& io_context)
-    : service_base<winrt_resolver_service<Protocol> >(io_context),
-      io_context_(use_service<io_context_impl>(io_context)),
-      async_manager_(use_service<winrt_async_manager>(io_context))
-  {
-  }
-
-  // Destructor.
-  ~winrt_resolver_service()
-  {
-  }
-
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-  }
-
-  // Perform any fork-related housekeeping.
-  void notify_fork(asio::io_context::fork_event)
-  {
-  }
-
-  // Construct a new resolver implementation.
-  void construct(implementation_type&)
-  {
-  }
-
-  // Move-construct a new resolver implementation.
-  void move_construct(implementation_type&,
-      implementation_type&)
-  {
-  }
-
-  // Move-assign from another resolver implementation.
-  void move_assign(implementation_type&,
-      winrt_resolver_service&, implementation_type&)
-  {
-  }
-
-  // Destroy a resolver implementation.
-  void destroy(implementation_type&)
-  {
-  }
-
-  // Cancel pending asynchronous operations.
-  void cancel(implementation_type&)
-  {
-  }
-
-  // Resolve a query to a list of entries.
-  results_type resolve(implementation_type&,
-      const query_type& query, asio::error_code& ec)
-  {
-    try
-    {
-      using namespace Windows::Networking::Sockets;
-      auto endpoint_pairs = async_manager_.sync(
-          DatagramSocket::GetEndpointPairsAsync(
-            winrt_utils::host_name(query.host_name()),
-            winrt_utils::string(query.service_name())), ec);
-
-      if (ec)
-        return results_type();
-
-      return results_type::create(
-          endpoint_pairs, query.hints(),
-          query.host_name(), query.service_name());
-    }
-    catch (Platform::Exception^ e)
-    {
-      ec = asio::error_code(e->HResult,
-          asio::system_category());
-      return results_type();
-    }
-  }
-
-  // Asynchronously resolve a query to a list of entries.
-  template <typename Handler>
-  void async_resolve(implementation_type& impl,
-      const query_type& query, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef winrt_resolve_op<Protocol, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(query, handler);
-
-    ASIO_HANDLER_CREATION((io_context_.context(),
-          *p.p, "resolver", &impl, 0, "async_resolve"));
-    (void)impl;
-
-    try
-    {
-      using namespace Windows::Networking::Sockets;
-      async_manager_.async(DatagramSocket::GetEndpointPairsAsync(
-            winrt_utils::host_name(query.host_name()),
-            winrt_utils::string(query.service_name())), p.p);
-      p.v = p.p = 0;
-    }
-    catch (Platform::Exception^ e)
-    {
-      p.p->ec_ = asio::error_code(
-          e->HResult, asio::system_category());
-      io_context_.post_immediate_completion(p.p, is_continuation);
-      p.v = p.p = 0;
-    }
-  }
-
-  // Resolve an endpoint to a list of entries.
-  results_type resolve(implementation_type&,
-      const endpoint_type&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return results_type();
-  }
-
-  // Asynchronously resolve an endpoint to a list of entries.
-  template <typename Handler>
-  void async_resolve(implementation_type&,
-      const endpoint_type&, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const results_type results;
-    io_context_.get_io_context().post(
-        detail::bind_handler(handler, ec, results));
-  }
-
-private:
-  io_context_impl& io_context_;
-  winrt_async_manager& async_manager_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_RESOLVER_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_socket_connect_op.hpp b/tools/sdk/include/asio/asio/detail/winrt_socket_connect_op.hpp
deleted file mode 100644
index f18b445f880..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_socket_connect_op.hpp
+++ /dev/null
@@ -1,92 +0,0 @@
-//
-// detail/winrt_socket_connect_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_SOCKET_CONNECT_OP_HPP
-#define ASIO_DETAIL_WINRT_SOCKET_CONNECT_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/winrt_async_op.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class winrt_socket_connect_op :
-  public winrt_async_op<void>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(winrt_socket_connect_op);
-
-  winrt_socket_connect_op(Handler& handler)
-    : winrt_async_op<void>(&winrt_socket_connect_op::do_complete),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code&, std::size_t)
-  {
-    // Take ownership of the operation object.
-    winrt_socket_connect_op* o(static_cast<winrt_socket_connect_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder1<Handler, asio::error_code>
-      handler(o->handler_, o->ec_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_SOCKET_CONNECT_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_socket_recv_op.hpp b/tools/sdk/include/asio/asio/detail/winrt_socket_recv_op.hpp
deleted file mode 100644
index 8f1fcf576f8..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_socket_recv_op.hpp
+++ /dev/null
@@ -1,112 +0,0 @@
-//
-// detail/winrt_socket_recv_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_SOCKET_RECV_OP_HPP
-#define ASIO_DETAIL_WINRT_SOCKET_RECV_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/winrt_async_op.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename MutableBufferSequence, typename Handler>
-class winrt_socket_recv_op :
-  public winrt_async_op<Windows::Storage::Streams::IBuffer^>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(winrt_socket_recv_op);
-
-  winrt_socket_recv_op(const MutableBufferSequence& buffers, Handler& handler)
-    : winrt_async_op<Windows::Storage::Streams::IBuffer^>(
-          &winrt_socket_recv_op::do_complete),
-      buffers_(buffers),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code&, std::size_t)
-  {
-    // Take ownership of the operation object.
-    winrt_socket_recv_op* o(static_cast<winrt_socket_recv_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    // Check whether buffers are still valid.
-    if (owner)
-    {
-      buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::validate(o->buffers_);
-    }
-#endif // defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-
-    std::size_t bytes_transferred = o->result_ ? o->result_->Length : 0;
-    if (bytes_transferred == 0 && !o->ec_ &&
-        !buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::all_empty(o->buffers_))
-    {
-      o->ec_ = asio::error::eof;
-    }
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, bytes_transferred);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  MutableBufferSequence buffers_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_SOCKET_RECV_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_socket_send_op.hpp b/tools/sdk/include/asio/asio/detail/winrt_socket_send_op.hpp
deleted file mode 100644
index 1148c24e4cf..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_socket_send_op.hpp
+++ /dev/null
@@ -1,103 +0,0 @@
-//
-// detail/winrt_socket_send_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_SOCKET_SEND_OP_HPP
-#define ASIO_DETAIL_WINRT_SOCKET_SEND_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/winrt_async_op.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename ConstBufferSequence, typename Handler>
-class winrt_socket_send_op :
-  public winrt_async_op<unsigned int>
-{
-public:
-  ASIO_DEFINE_HANDLER_PTR(winrt_socket_send_op);
-
-  winrt_socket_send_op(const ConstBufferSequence& buffers, Handler& handler)
-    : winrt_async_op<unsigned int>(&winrt_socket_send_op::do_complete),
-      buffers_(buffers),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-    handler_work<Handler>::start(handler_);
-  }
-
-  static void do_complete(void* owner, operation* base,
-      const asio::error_code&, std::size_t)
-  {
-    // Take ownership of the operation object.
-    winrt_socket_send_op* o(static_cast<winrt_socket_send_op*>(base));
-    ptr p = { asio::detail::addressof(o->handler_), o, o };
-    handler_work<Handler> w(o->handler_);
-
-    ASIO_HANDLER_COMPLETION((*o));
-
-#if defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-    // Check whether buffers are still valid.
-    if (owner)
-    {
-      buffer_sequence_adapter<asio::const_buffer,
-          ConstBufferSequence>::validate(o->buffers_);
-    }
-#endif // defined(ASIO_ENABLE_BUFFER_DEBUGGING)
-
-    // Make a copy of the handler so that the memory can be deallocated before
-    // the upcall is made. Even if we're not about to make an upcall, a
-    // sub-object of the handler may be the true owner of the memory associated
-    // with the handler. Consequently, a local copy of the handler is required
-    // to ensure that any owning sub-object remains valid until after we have
-    // deallocated the memory here.
-    detail::binder2<Handler, asio::error_code, std::size_t>
-      handler(o->handler_, o->ec_, o->result_);
-    p.h = asio::detail::addressof(handler.handler_);
-    p.reset();
-
-    // Make the upcall if required.
-    if (owner)
-    {
-      fenced_block b(fenced_block::half);
-      ASIO_HANDLER_INVOCATION_BEGIN((handler.arg1_, handler.arg2_));
-      w.complete(handler, handler.handler_);
-      ASIO_HANDLER_INVOCATION_END;
-    }
-  }
-
-private:
-  ConstBufferSequence buffers_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_SOCKET_SEND_OP_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_ssocket_service.hpp b/tools/sdk/include/asio/asio/detail/winrt_ssocket_service.hpp
deleted file mode 100644
index 603724a30e6..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_ssocket_service.hpp
+++ /dev/null
@@ -1,241 +0,0 @@
-//
-// detail/winrt_ssocket_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_SSOCKET_SERVICE_HPP
-#define ASIO_DETAIL_WINRT_SSOCKET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/winrt_socket_connect_op.hpp"
-#include "asio/detail/winrt_ssocket_service_base.hpp"
-#include "asio/detail/winrt_utils.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Protocol>
-class winrt_ssocket_service :
-  public service_base<winrt_ssocket_service<Protocol> >,
-  public winrt_ssocket_service_base
-{
-public:
-  // The protocol type.
-  typedef Protocol protocol_type;
-
-  // The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-  // The native type of a socket.
-  typedef Windows::Networking::Sockets::StreamSocket^ native_handle_type;
-
-  // The implementation type of the socket.
-  struct implementation_type : base_implementation_type
-  {
-    // Default constructor.
-    implementation_type()
-      : base_implementation_type(),
-        protocol_(endpoint_type().protocol())
-    {
-    }
-
-    // The protocol associated with the socket.
-    protocol_type protocol_;
-  };
-
-  // Constructor.
-  winrt_ssocket_service(asio::io_context& io_context)
-    : service_base<winrt_ssocket_service<Protocol> >(io_context),
-      winrt_ssocket_service_base(io_context)
-  {
-  }
-
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    this->base_shutdown();
-  }
-
-  // Move-construct a new socket implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    this->base_move_construct(impl, other_impl);
-
-    impl.protocol_ = other_impl.protocol_;
-    other_impl.protocol_ = endpoint_type().protocol();
-  }
-
-  // Move-assign from another socket implementation.
-  void move_assign(implementation_type& impl,
-      winrt_ssocket_service& other_service,
-      implementation_type& other_impl)
-  {
-    this->base_move_assign(impl, other_service, other_impl);
-
-    impl.protocol_ = other_impl.protocol_;
-    other_impl.protocol_ = endpoint_type().protocol();
-  }
-
-  // Move-construct a new socket implementation from another protocol type.
-  template <typename Protocol1>
-  void converting_move_construct(implementation_type& impl,
-      winrt_ssocket_service<Protocol1>&,
-      typename winrt_ssocket_service<
-        Protocol1>::implementation_type& other_impl)
-  {
-    this->base_move_construct(impl, other_impl);
-
-    impl.protocol_ = protocol_type(other_impl.protocol_);
-    other_impl.protocol_ = typename Protocol1::endpoint().protocol();
-  }
-
-  // Open a new socket implementation.
-  asio::error_code open(implementation_type& impl,
-      const protocol_type& protocol, asio::error_code& ec)
-  {
-    if (is_open(impl))
-    {
-      ec = asio::error::already_open;
-      return ec;
-    }
-
-    try
-    {
-      impl.socket_ = ref new Windows::Networking::Sockets::StreamSocket;
-      impl.protocol_ = protocol;
-      ec = asio::error_code();
-    }
-    catch (Platform::Exception^ e)
-    {
-      ec = asio::error_code(e->HResult,
-            asio::system_category());
-    }
-
-    return ec;
-  }
-
-  // Assign a native socket to a socket implementation.
-  asio::error_code assign(implementation_type& impl,
-      const protocol_type& protocol, const native_handle_type& native_socket,
-      asio::error_code& ec)
-  {
-    if (is_open(impl))
-    {
-      ec = asio::error::already_open;
-      return ec;
-    }
-
-    impl.socket_ = native_socket;
-    impl.protocol_ = protocol;
-    ec = asio::error_code();
-
-    return ec;
-  }
-
-  // Bind the socket to the specified local endpoint.
-  asio::error_code bind(implementation_type&,
-      const endpoint_type&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Get the local endpoint.
-  endpoint_type local_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    endpoint_type endpoint;
-    endpoint.resize(do_get_endpoint(impl, true,
-          endpoint.data(), endpoint.size(), ec));
-    return endpoint;
-  }
-
-  // Get the remote endpoint.
-  endpoint_type remote_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    endpoint_type endpoint;
-    endpoint.resize(do_get_endpoint(impl, false,
-          endpoint.data(), endpoint.size(), ec));
-    return endpoint;
-  }
-
-  // Set a socket option.
-  template <typename Option>
-  asio::error_code set_option(implementation_type& impl,
-      const Option& option, asio::error_code& ec)
-  {
-    return do_set_option(impl, option.level(impl.protocol_),
-        option.name(impl.protocol_), option.data(impl.protocol_),
-        option.size(impl.protocol_), ec);
-  }
-
-  // Get a socket option.
-  template <typename Option>
-  asio::error_code get_option(const implementation_type& impl,
-      Option& option, asio::error_code& ec) const
-  {
-    std::size_t size = option.size(impl.protocol_);
-    do_get_option(impl, option.level(impl.protocol_),
-        option.name(impl.protocol_),
-        option.data(impl.protocol_), &size, ec);
-    if (!ec)
-      option.resize(impl.protocol_, size);
-    return ec;
-  }
-
-  // Connect the socket to the specified endpoint.
-  asio::error_code connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, asio::error_code& ec)
-  {
-    return do_connect(impl, peer_endpoint.data(), ec);
-  }
-
-  // Start an asynchronous connect.
-  template <typename Handler>
-  void async_connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef winrt_socket_connect_op<Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(handler);
-
-    ASIO_HANDLER_CREATION((io_context_.context(),
-          *p.p, "socket", &impl, 0, "async_connect"));
-
-    start_connect_op(impl, peer_endpoint.data(), p.p, is_continuation);
-    p.v = p.p = 0;
-  }
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_SSOCKET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_ssocket_service_base.hpp b/tools/sdk/include/asio/asio/detail/winrt_ssocket_service_base.hpp
deleted file mode 100644
index 61328d0a034..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_ssocket_service_base.hpp
+++ /dev/null
@@ -1,359 +0,0 @@
-//
-// detail/winrt_ssocket_service_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_SSOCKET_SERVICE_BASE_HPP
-#define ASIO_DETAIL_WINRT_SSOCKET_SERVICE_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/buffer.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/socket_base.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/winrt_async_manager.hpp"
-#include "asio/detail/winrt_socket_recv_op.hpp"
-#include "asio/detail/winrt_socket_send_op.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class winrt_ssocket_service_base
-{
-public:
-  // The native type of a socket.
-  typedef Windows::Networking::Sockets::StreamSocket^ native_handle_type;
-
-  // The implementation type of the socket.
-  struct base_implementation_type
-  {
-    // Default constructor.
-    base_implementation_type()
-      : socket_(nullptr),
-        next_(0),
-        prev_(0)
-    {
-    }
-
-    // The underlying native socket.
-    native_handle_type socket_;
-
-    // Pointers to adjacent socket implementations in linked list.
-    base_implementation_type* next_;
-    base_implementation_type* prev_;
-  };
-
-  // Constructor.
-  ASIO_DECL winrt_ssocket_service_base(
-      asio::io_context& io_context);
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void base_shutdown();
-
-  // Construct a new socket implementation.
-  ASIO_DECL void construct(base_implementation_type&);
-
-  // Move-construct a new socket implementation.
-  ASIO_DECL void base_move_construct(base_implementation_type& impl,
-      base_implementation_type& other_impl);
-
-  // Move-assign from another socket implementation.
-  ASIO_DECL void base_move_assign(base_implementation_type& impl,
-      winrt_ssocket_service_base& other_service,
-      base_implementation_type& other_impl);
-
-  // Destroy a socket implementation.
-  ASIO_DECL void destroy(base_implementation_type& impl);
-
-  // Determine whether the socket is open.
-  bool is_open(const base_implementation_type& impl) const
-  {
-    return impl.socket_ != nullptr;
-  }
-
-  // Destroy a socket implementation.
-  ASIO_DECL asio::error_code close(
-      base_implementation_type& impl, asio::error_code& ec);
-
-  // Release ownership of the socket.
-  ASIO_DECL native_handle_type release(
-      base_implementation_type& impl, asio::error_code& ec);
-
-  // Get the native socket representation.
-  native_handle_type native_handle(base_implementation_type& impl)
-  {
-    return impl.socket_;
-  }
-
-  // Cancel all operations associated with the socket.
-  asio::error_code cancel(base_implementation_type&,
-      asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Determine whether the socket is at the out-of-band data mark.
-  bool at_mark(const base_implementation_type&,
-      asio::error_code& ec) const
-  {
-    ec = asio::error::operation_not_supported;
-    return false;
-  }
-
-  // Determine the number of bytes available for reading.
-  std::size_t available(const base_implementation_type&,
-      asio::error_code& ec) const
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Perform an IO control command on the socket.
-  template <typename IO_Control_Command>
-  asio::error_code io_control(base_implementation_type&,
-      IO_Control_Command&, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the socket.
-  bool non_blocking(const base_implementation_type&) const
-  {
-    return false;
-  }
-
-  // Sets the non-blocking mode of the socket.
-  asio::error_code non_blocking(base_implementation_type&,
-      bool, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Gets the non-blocking mode of the native socket implementation.
-  bool native_non_blocking(const base_implementation_type&) const
-  {
-    return false;
-  }
-
-  // Sets the non-blocking mode of the native socket implementation.
-  asio::error_code native_non_blocking(base_implementation_type&,
-      bool, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Disable sends or receives on the socket.
-  asio::error_code shutdown(base_implementation_type&,
-      socket_base::shutdown_type, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return ec;
-  }
-
-  // Send the given data to the peer.
-  template <typename ConstBufferSequence>
-  std::size_t send(base_implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return do_send(impl,
-        buffer_sequence_adapter<asio::const_buffer,
-          ConstBufferSequence>::first(buffers), flags, ec);
-  }
-
-  // Wait until data can be sent without blocking.
-  std::size_t send(base_implementation_type&, const null_buffers&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Start an asynchronous send. The data being sent must be valid for the
-  // lifetime of the asynchronous operation.
-  template <typename ConstBufferSequence, typename Handler>
-  void async_send(base_implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef winrt_socket_send_op<ConstBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(buffers, handler);
-
-    ASIO_HANDLER_CREATION((io_context_.context(),
-          *p.p, "socket", &impl, 0, "async_send"));
-
-    start_send_op(impl,
-        buffer_sequence_adapter<asio::const_buffer,
-          ConstBufferSequence>::first(buffers),
-        flags, p.p, is_continuation);
-    p.v = p.p = 0;
-  }
-
-  // Start an asynchronous wait until data can be sent without blocking.
-  template <typename Handler>
-  void async_send(base_implementation_type&, const null_buffers&,
-      socket_base::message_flags, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.get_io_context().post(
-        detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-  // Receive some data from the peer. Returns the number of bytes received.
-  template <typename MutableBufferSequence>
-  std::size_t receive(base_implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return do_receive(impl,
-        buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::first(buffers), flags, ec);
-  }
-
-  // Wait until data can be received without blocking.
-  std::size_t receive(base_implementation_type&, const null_buffers&,
-      socket_base::message_flags, asio::error_code& ec)
-  {
-    ec = asio::error::operation_not_supported;
-    return 0;
-  }
-
-  // Start an asynchronous receive. The buffer for the data being received
-  // must be valid for the lifetime of the asynchronous operation.
-  template <typename MutableBufferSequence, typename Handler>
-  void async_receive(base_implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, Handler& handler)
-  {
-    bool is_continuation =
-      asio_handler_cont_helpers::is_continuation(handler);
-
-    // Allocate and construct an operation to wrap the handler.
-    typedef winrt_socket_recv_op<MutableBufferSequence, Handler> op;
-    typename op::ptr p = { asio::detail::addressof(handler),
-      op::ptr::allocate(handler), 0 };
-    p.p = new (p.v) op(buffers, handler);
-
-    ASIO_HANDLER_CREATION((io_context_.context(),
-          *p.p, "socket", &impl, 0, "async_receive"));
-
-    start_receive_op(impl,
-        buffer_sequence_adapter<asio::mutable_buffer,
-          MutableBufferSequence>::first(buffers),
-        flags, p.p, is_continuation);
-    p.v = p.p = 0;
-  }
-
-  // Wait until data can be received without blocking.
-  template <typename Handler>
-  void async_receive(base_implementation_type&, const null_buffers&,
-      socket_base::message_flags, Handler& handler)
-  {
-    asio::error_code ec = asio::error::operation_not_supported;
-    const std::size_t bytes_transferred = 0;
-    io_context_.get_io_context().post(
-        detail::bind_handler(handler, ec, bytes_transferred));
-  }
-
-protected:
-  // Helper function to obtain endpoints associated with the connection.
-  ASIO_DECL std::size_t do_get_endpoint(
-      const base_implementation_type& impl, bool local,
-      void* addr, std::size_t addr_len, asio::error_code& ec) const;
-
-  // Helper function to set a socket option.
-  ASIO_DECL asio::error_code do_set_option(
-      base_implementation_type& impl,
-      int level, int optname, const void* optval,
-      std::size_t optlen, asio::error_code& ec);
-
-  // Helper function to get a socket option.
-  ASIO_DECL void do_get_option(
-      const base_implementation_type& impl,
-      int level, int optname, void* optval,
-      std::size_t* optlen, asio::error_code& ec) const;
-
-  // Helper function to perform a synchronous connect.
-  ASIO_DECL asio::error_code do_connect(
-      base_implementation_type& impl,
-      const void* addr, asio::error_code& ec);
-
-  // Helper function to start an asynchronous connect.
-  ASIO_DECL void start_connect_op(
-      base_implementation_type& impl, const void* addr,
-      winrt_async_op<void>* op, bool is_continuation);
-
-  // Helper function to perform a synchronous send.
-  ASIO_DECL std::size_t do_send(
-      base_implementation_type& impl, const asio::const_buffer& data,
-      socket_base::message_flags flags, asio::error_code& ec);
-
-  // Helper function to start an asynchronous send.
-  ASIO_DECL void start_send_op(base_implementation_type& impl,
-      const asio::const_buffer& data, socket_base::message_flags flags,
-      winrt_async_op<unsigned int>* op, bool is_continuation);
-
-  // Helper function to perform a synchronous receive.
-  ASIO_DECL std::size_t do_receive(
-      base_implementation_type& impl, const asio::mutable_buffer& data,
-      socket_base::message_flags flags, asio::error_code& ec);
-
-  // Helper function to start an asynchronous receive.
-  ASIO_DECL void start_receive_op(base_implementation_type& impl,
-      const asio::mutable_buffer& data, socket_base::message_flags flags,
-      winrt_async_op<Windows::Storage::Streams::IBuffer^>* op,
-      bool is_continuation);
-
-  // The io_context implementation used for delivering completions.
-  io_context_impl& io_context_;
-
-  // The manager that keeps track of outstanding operations.
-  winrt_async_manager& async_manager_;
-
-  // Mutex to protect access to the linked list of implementations. 
-  asio::detail::mutex mutex_;
-
-  // The head of a linked list of all implementations.
-  base_implementation_type* impl_list_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/winrt_ssocket_service_base.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_SSOCKET_SERVICE_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_timer_scheduler.hpp b/tools/sdk/include/asio/asio/detail/winrt_timer_scheduler.hpp
deleted file mode 100644
index 5dec7c0b696..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_timer_scheduler.hpp
+++ /dev/null
@@ -1,137 +0,0 @@
-//
-// detail/winrt_timer_scheduler.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_TIMER_SCHEDULER_HPP
-#define ASIO_DETAIL_WINRT_TIMER_SCHEDULER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include <cstddef>
-#include "asio/detail/event.hpp"
-#include "asio/detail/limits.hpp"
-#include "asio/detail/mutex.hpp"
-#include "asio/detail/op_queue.hpp"
-#include "asio/detail/thread.hpp"
-#include "asio/detail/timer_queue_base.hpp"
-#include "asio/detail/timer_queue_set.hpp"
-#include "asio/detail/wait_op.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-# include "asio/detail/thread.hpp"
-#endif // defined(ASIO_HAS_IOCP)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class winrt_timer_scheduler
-  : public asio::detail::service_base<winrt_timer_scheduler>
-{
-public:
-  // Constructor.
-  ASIO_DECL winrt_timer_scheduler(asio::io_context& io_context);
-
-  // Destructor.
-  ASIO_DECL ~winrt_timer_scheduler();
-
-  // Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL void shutdown();
-
-  // Recreate internal descriptors following a fork.
-  ASIO_DECL void notify_fork(
-      asio::io_context::fork_event fork_ev);
-
-  // Initialise the task. No effect as this class uses its own thread.
-  ASIO_DECL void init_task();
-
-  // Add a new timer queue to the reactor.
-  template <typename Time_Traits>
-  void add_timer_queue(timer_queue<Time_Traits>& queue);
-
-  // Remove a timer queue from the reactor.
-  template <typename Time_Traits>
-  void remove_timer_queue(timer_queue<Time_Traits>& queue);
-
-  // Schedule a new operation in the given timer queue to expire at the
-  // specified absolute time.
-  template <typename Time_Traits>
-  void schedule_timer(timer_queue<Time_Traits>& queue,
-      const typename Time_Traits::time_type& time,
-      typename timer_queue<Time_Traits>::per_timer_data& timer, wait_op* op);
-
-  // Cancel the timer operations associated with the given token. Returns the
-  // number of operations that have been posted or dispatched.
-  template <typename Time_Traits>
-  std::size_t cancel_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& timer,
-      std::size_t max_cancelled = (std::numeric_limits<std::size_t>::max)());
-
-  // Move the timer operations associated with the given timer.
-  template <typename Time_Traits>
-  void move_timer(timer_queue<Time_Traits>& queue,
-      typename timer_queue<Time_Traits>::per_timer_data& to,
-      typename timer_queue<Time_Traits>::per_timer_data& from);
-
-private:
-  // Run the select loop in the thread.
-  ASIO_DECL void run_thread();
-
-  // Entry point for the select loop thread.
-  ASIO_DECL static void call_run_thread(winrt_timer_scheduler* reactor);
-
-  // Helper function to add a new timer queue.
-  ASIO_DECL void do_add_timer_queue(timer_queue_base& queue);
-
-  // Helper function to remove a timer queue.
-  ASIO_DECL void do_remove_timer_queue(timer_queue_base& queue);
-
-  // The io_context implementation used to post completions.
-  io_context_impl& io_context_;
-
-  // Mutex used to protect internal variables.
-  asio::detail::mutex mutex_;
-
-  // Event used to wake up background thread.
-  asio::detail::event event_;
-
-  // The timer queues.
-  timer_queue_set timer_queues_;
-
-  // The background thread that is waiting for timers to expire.
-  asio::detail::thread* thread_;
-
-  // Does the background thread need to stop.
-  bool stop_thread_;
-
-  // Whether the service has been shut down.
-  bool shutdown_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/detail/impl/winrt_timer_scheduler.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/winrt_timer_scheduler.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_TIMER_SCHEDULER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winrt_utils.hpp b/tools/sdk/include/asio/asio/detail/winrt_utils.hpp
deleted file mode 100644
index 22a24895834..00000000000
--- a/tools/sdk/include/asio/asio/detail/winrt_utils.hpp
+++ /dev/null
@@ -1,106 +0,0 @@
-//
-// detail/winrt_utils.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINRT_UTILS_HPP
-#define ASIO_DETAIL_WINRT_UTILS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-
-#include <codecvt>
-#include <cstdlib>
-#include <future>
-#include <locale>
-#include <robuffer.h>
-#include <windows.storage.streams.h>
-#include <wrl/implements.h>
-#include "asio/buffer.hpp"
-#include "asio/error_code.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/socket_ops.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-namespace winrt_utils {
-
-inline Platform::String^ string(const char* from)
-{
-  std::wstring tmp(from, from + std::strlen(from));
-  return ref new Platform::String(tmp.c_str());
-}
-
-inline Platform::String^ string(const std::string& from)
-{
-  std::wstring tmp(from.begin(), from.end());
-  return ref new Platform::String(tmp.c_str());
-}
-
-inline std::string string(Platform::String^ from)
-{
-  std::wstring_convert<std::codecvt_utf8<wchar_t>> converter;
-  return converter.to_bytes(from->Data());
-}
-
-inline Platform::String^ string(unsigned short from)
-{
-  return string(std::to_string(from));
-}
-
-template <typename T>
-inline Platform::String^ string(const T& from)
-{
-  return string(from.to_string());
-}
-
-inline int integer(Platform::String^ from)
-{
-  return _wtoi(from->Data());
-}
-
-template <typename T>
-inline Windows::Networking::HostName^ host_name(const T& from)
-{
-  return ref new Windows::Networking::HostName((string)(from));
-}
-
-template <typename ConstBufferSequence>
-inline Windows::Storage::Streams::IBuffer^ buffer_dup(
-    const ConstBufferSequence& buffers)
-{
-  using Microsoft::WRL::ComPtr;
-  using asio::buffer_size;
-  std::size_t size = buffer_size(buffers);
-  auto b = ref new Windows::Storage::Streams::Buffer(size);
-  ComPtr<IInspectable> insp = reinterpret_cast<IInspectable*>(b);
-  ComPtr<Windows::Storage::Streams::IBufferByteAccess> bacc;
-  insp.As(&bacc);
-  byte* bytes = nullptr;
-  bacc->Buffer(&bytes);
-  asio::buffer_copy(asio::buffer(bytes, size), buffers);
-  b->Length = size;
-  return b;
-}
-
-} // namespace winrt_utils
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#endif // ASIO_DETAIL_WINRT_UTILS_HPP
diff --git a/tools/sdk/include/asio/asio/detail/winsock_init.hpp b/tools/sdk/include/asio/asio/detail/winsock_init.hpp
deleted file mode 100644
index 9094363abd7..00000000000
--- a/tools/sdk/include/asio/asio/detail/winsock_init.hpp
+++ /dev/null
@@ -1,128 +0,0 @@
-//
-// detail/winsock_init.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WINSOCK_INIT_HPP
-#define ASIO_DETAIL_WINSOCK_INIT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-class winsock_init_base
-{
-protected:
-  // Structure to track result of initialisation and number of uses. POD is used
-  // to ensure that the values are zero-initialised prior to any code being run.
-  struct data
-  {
-    long init_count_;
-    long result_;
-  };
-
-  ASIO_DECL static void startup(data& d,
-      unsigned char major, unsigned char minor);
-
-  ASIO_DECL static void manual_startup(data& d);
-
-  ASIO_DECL static void cleanup(data& d);
-
-  ASIO_DECL static void manual_cleanup(data& d);
-
-  ASIO_DECL static void throw_on_error(data& d);
-};
-
-template <int Major = 2, int Minor = 0>
-class winsock_init : private winsock_init_base
-{
-public:
-  winsock_init(bool allow_throw = true)
-  {
-    startup(data_, Major, Minor);
-    if (allow_throw)
-      throw_on_error(data_);
-  }
-
-  winsock_init(const winsock_init&)
-  {
-    startup(data_, Major, Minor);
-    throw_on_error(data_);
-  }
-
-  ~winsock_init()
-  {
-    cleanup(data_);
-  }
-
-  // This class may be used to indicate that user code will manage Winsock
-  // initialisation and cleanup. This may be required in the case of a DLL, for
-  // example, where it is not safe to initialise Winsock from global object
-  // constructors.
-  //
-  // To prevent asio from initialising Winsock, the object must be constructed
-  // before any Asio's own global objects. With MSVC, this may be accomplished
-  // by adding the following code to the DLL:
-  //
-  //   #pragma warning(push)
-  //   #pragma warning(disable:4073)
-  //   #pragma init_seg(lib)
-  //   asio::detail::winsock_init<>::manual manual_winsock_init;
-  //   #pragma warning(pop)
-  class manual
-  {
-  public:
-    manual()
-    {
-      manual_startup(data_);
-    }
-
-    manual(const manual&)
-    {
-      manual_startup(data_);
-    }
-
-    ~manual()
-    {
-      manual_cleanup(data_);
-    }
-  };
-
-private:
-  friend class manual;
-  static data data_;
-};
-
-template <int Major, int Minor>
-winsock_init_base::data winsock_init<Major, Minor>::data_;
-
-// Static variable to ensure that winsock is initialised before main, and
-// therefore before any other threads can get started.
-static const winsock_init<>& winsock_init_instance = winsock_init<>(false);
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/detail/impl/winsock_init.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-
-#endif // ASIO_DETAIL_WINSOCK_INIT_HPP
diff --git a/tools/sdk/include/asio/asio/detail/work_dispatcher.hpp b/tools/sdk/include/asio/asio/detail/work_dispatcher.hpp
deleted file mode 100644
index 7abce497ba0..00000000000
--- a/tools/sdk/include/asio/asio/detail/work_dispatcher.hpp
+++ /dev/null
@@ -1,72 +0,0 @@
-//
-// detail/work_dispatcher.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WORK_DISPATCHER_HPP
-#define ASIO_DETAIL_WORK_DISPATCHER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/executor_work_guard.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Handler>
-class work_dispatcher
-{
-public:
-  work_dispatcher(Handler& handler)
-    : work_((get_associated_executor)(handler)),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  work_dispatcher(const work_dispatcher& other)
-    : work_(other.work_),
-      handler_(other.handler_)
-  {
-  }
-
-  work_dispatcher(work_dispatcher&& other)
-    : work_(ASIO_MOVE_CAST(executor_work_guard<
-        typename associated_executor<Handler>::type>)(other.work_)),
-      handler_(ASIO_MOVE_CAST(Handler)(other.handler_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  void operator()()
-  {
-    typename associated_allocator<Handler>::type alloc(
-        (get_associated_allocator)(handler_));
-    work_.get_executor().dispatch(
-        ASIO_MOVE_CAST(Handler)(handler_), alloc);
-    work_.reset();
-  }
-
-private:
-  executor_work_guard<typename associated_executor<Handler>::type> work_;
-  Handler handler_;
-};
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_WORK_DISPATCHER_HPP
diff --git a/tools/sdk/include/asio/asio/detail/wrapped_handler.hpp b/tools/sdk/include/asio/asio/detail/wrapped_handler.hpp
deleted file mode 100644
index 751f0ea830a..00000000000
--- a/tools/sdk/include/asio/asio/detail/wrapped_handler.hpp
+++ /dev/null
@@ -1,291 +0,0 @@
-//
-// detail/wrapped_handler.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DETAIL_WRAPPED_HANDLER_HPP
-#define ASIO_DETAIL_WRAPPED_HANDLER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-struct is_continuation_delegated
-{
-  template <typename Dispatcher, typename Handler>
-  bool operator()(Dispatcher&, Handler& handler) const
-  {
-    return asio_handler_cont_helpers::is_continuation(handler);
-  }
-};
-
-struct is_continuation_if_running
-{
-  template <typename Dispatcher, typename Handler>
-  bool operator()(Dispatcher& dispatcher, Handler&) const
-  {
-    return dispatcher.running_in_this_thread();
-  }
-};
-
-template <typename Dispatcher, typename Handler,
-    typename IsContinuation = is_continuation_delegated>
-class wrapped_handler
-{
-public:
-  typedef void result_type;
-
-  wrapped_handler(Dispatcher dispatcher, Handler& handler)
-    : dispatcher_(dispatcher),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  wrapped_handler(const wrapped_handler& other)
-    : dispatcher_(other.dispatcher_),
-      handler_(other.handler_)
-  {
-  }
-
-  wrapped_handler(wrapped_handler&& other)
-    : dispatcher_(other.dispatcher_),
-      handler_(ASIO_MOVE_CAST(Handler)(other.handler_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  void operator()()
-  {
-    dispatcher_.dispatch(ASIO_MOVE_CAST(Handler)(handler_));
-  }
-
-  void operator()() const
-  {
-    dispatcher_.dispatch(handler_);
-  }
-
-  template <typename Arg1>
-  void operator()(const Arg1& arg1)
-  {
-    dispatcher_.dispatch(detail::bind_handler(handler_, arg1));
-  }
-
-  template <typename Arg1>
-  void operator()(const Arg1& arg1) const
-  {
-    dispatcher_.dispatch(detail::bind_handler(handler_, arg1));
-  }
-
-  template <typename Arg1, typename Arg2>
-  void operator()(const Arg1& arg1, const Arg2& arg2)
-  {
-    dispatcher_.dispatch(detail::bind_handler(handler_, arg1, arg2));
-  }
-
-  template <typename Arg1, typename Arg2>
-  void operator()(const Arg1& arg1, const Arg2& arg2) const
-  {
-    dispatcher_.dispatch(detail::bind_handler(handler_, arg1, arg2));
-  }
-
-  template <typename Arg1, typename Arg2, typename Arg3>
-  void operator()(const Arg1& arg1, const Arg2& arg2, const Arg3& arg3)
-  {
-    dispatcher_.dispatch(detail::bind_handler(handler_, arg1, arg2, arg3));
-  }
-
-  template <typename Arg1, typename Arg2, typename Arg3>
-  void operator()(const Arg1& arg1, const Arg2& arg2, const Arg3& arg3) const
-  {
-    dispatcher_.dispatch(detail::bind_handler(handler_, arg1, arg2, arg3));
-  }
-
-  template <typename Arg1, typename Arg2, typename Arg3, typename Arg4>
-  void operator()(const Arg1& arg1, const Arg2& arg2, const Arg3& arg3,
-      const Arg4& arg4)
-  {
-    dispatcher_.dispatch(
-        detail::bind_handler(handler_, arg1, arg2, arg3, arg4));
-  }
-
-  template <typename Arg1, typename Arg2, typename Arg3, typename Arg4>
-  void operator()(const Arg1& arg1, const Arg2& arg2, const Arg3& arg3,
-      const Arg4& arg4) const
-  {
-    dispatcher_.dispatch(
-        detail::bind_handler(handler_, arg1, arg2, arg3, arg4));
-  }
-
-  template <typename Arg1, typename Arg2, typename Arg3, typename Arg4,
-      typename Arg5>
-  void operator()(const Arg1& arg1, const Arg2& arg2, const Arg3& arg3,
-      const Arg4& arg4, const Arg5& arg5)
-  {
-    dispatcher_.dispatch(
-        detail::bind_handler(handler_, arg1, arg2, arg3, arg4, arg5));
-  }
-
-  template <typename Arg1, typename Arg2, typename Arg3, typename Arg4,
-      typename Arg5>
-  void operator()(const Arg1& arg1, const Arg2& arg2, const Arg3& arg3,
-      const Arg4& arg4, const Arg5& arg5) const
-  {
-    dispatcher_.dispatch(
-        detail::bind_handler(handler_, arg1, arg2, arg3, arg4, arg5));
-  }
-
-//private:
-  Dispatcher dispatcher_;
-  Handler handler_;
-};
-
-template <typename Handler, typename Context>
-class rewrapped_handler
-{
-public:
-  explicit rewrapped_handler(Handler& handler, const Context& context)
-    : context_(context),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-  }
-
-  explicit rewrapped_handler(const Handler& handler, const Context& context)
-    : context_(context),
-      handler_(handler)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  rewrapped_handler(const rewrapped_handler& other)
-    : context_(other.context_),
-      handler_(other.handler_)
-  {
-  }
-
-  rewrapped_handler(rewrapped_handler&& other)
-    : context_(ASIO_MOVE_CAST(Context)(other.context_)),
-      handler_(ASIO_MOVE_CAST(Handler)(other.handler_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  void operator()()
-  {
-    handler_();
-  }
-
-  void operator()() const
-  {
-    handler_();
-  }
-
-//private:
-  Context context_;
-  Handler handler_;
-};
-
-template <typename Dispatcher, typename Handler, typename IsContinuation>
-inline void* asio_handler_allocate(std::size_t size,
-    wrapped_handler<Dispatcher, Handler, IsContinuation>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Dispatcher, typename Handler, typename IsContinuation>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    wrapped_handler<Dispatcher, Handler, IsContinuation>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Dispatcher, typename Handler, typename IsContinuation>
-inline bool asio_handler_is_continuation(
-    wrapped_handler<Dispatcher, Handler, IsContinuation>* this_handler)
-{
-  return IsContinuation()(this_handler->dispatcher_, this_handler->handler_);
-}
-
-template <typename Function, typename Dispatcher,
-    typename Handler, typename IsContinuation>
-inline void asio_handler_invoke(Function& function,
-    wrapped_handler<Dispatcher, Handler, IsContinuation>* this_handler)
-{
-  this_handler->dispatcher_.dispatch(
-      rewrapped_handler<Function, Handler>(
-        function, this_handler->handler_));
-}
-
-template <typename Function, typename Dispatcher,
-    typename Handler, typename IsContinuation>
-inline void asio_handler_invoke(const Function& function,
-    wrapped_handler<Dispatcher, Handler, IsContinuation>* this_handler)
-{
-  this_handler->dispatcher_.dispatch(
-      rewrapped_handler<Function, Handler>(
-        function, this_handler->handler_));
-}
-
-template <typename Handler, typename Context>
-inline void* asio_handler_allocate(std::size_t size,
-    rewrapped_handler<Handler, Context>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->context_);
-}
-
-template <typename Handler, typename Context>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    rewrapped_handler<Handler, Context>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->context_);
-}
-
-template <typename Dispatcher, typename Context>
-inline bool asio_handler_is_continuation(
-    rewrapped_handler<Dispatcher, Context>* this_handler)
-{
-  return asio_handler_cont_helpers::is_continuation(
-      this_handler->context_);
-}
-
-template <typename Function, typename Handler, typename Context>
-inline void asio_handler_invoke(Function& function,
-    rewrapped_handler<Handler, Context>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->context_);
-}
-
-template <typename Function, typename Handler, typename Context>
-inline void asio_handler_invoke(const Function& function,
-    rewrapped_handler<Handler, Context>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->context_);
-}
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_DETAIL_WRAPPED_HANDLER_HPP
diff --git a/tools/sdk/include/asio/asio/dispatch.hpp b/tools/sdk/include/asio/asio/dispatch.hpp
deleted file mode 100644
index b8dfd69102b..00000000000
--- a/tools/sdk/include/asio/asio/dispatch.hpp
+++ /dev/null
@@ -1,108 +0,0 @@
-//
-// dispatch.hpp
-// ~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_DISPATCH_HPP
-#define ASIO_DISPATCH_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/async_result.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/execution_context.hpp"
-#include "asio/is_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Submits a completion token or function object for execution.
-/**
- * This function submits an object for execution using the object's associated
- * executor. The function object is queued for execution, and is never called
- * from the current thread prior to returning from <tt>dispatch()</tt>.
- *
- * This function has the following effects:
- *
- * @li Constructs a function object handler of type @c Handler, initialized
- * with <tt>handler(forward<CompletionToken>(token))</tt>.
- *
- * @li Constructs an object @c result of type <tt>async_result<Handler></tt>,
- * initializing the object as <tt>result(handler)</tt>.
- *
- * @li Obtains the handler's associated executor object @c ex by performing
- * <tt>get_associated_executor(handler)</tt>.
- *
- * @li Obtains the handler's associated allocator object @c alloc by performing
- * <tt>get_associated_allocator(handler)</tt>.
- *
- * @li Performs <tt>ex.dispatch(std::move(handler), alloc)</tt>.
- *
- * @li Returns <tt>result.get()</tt>.
- */
-template <typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) dispatch(
-    ASIO_MOVE_ARG(CompletionToken) token);
-
-/// Submits a completion token or function object for execution.
-/**
- * This function submits an object for execution using the specified executor.
- * The function object is queued for execution, and is never called from the
- * current thread prior to returning from <tt>dispatch()</tt>.
- *
- * This function has the following effects:
- *
- * @li Constructs a function object handler of type @c Handler, initialized
- * with <tt>handler(forward<CompletionToken>(token))</tt>.
- *
- * @li Constructs an object @c result of type <tt>async_result<Handler></tt>,
- * initializing the object as <tt>result(handler)</tt>.
- *
- * @li Obtains the handler's associated executor object @c ex1 by performing
- * <tt>get_associated_executor(handler)</tt>.
- *
- * @li Creates a work object @c w by performing <tt>make_work(ex1)</tt>.
- *
- * @li Obtains the handler's associated allocator object @c alloc by performing
- * <tt>get_associated_allocator(handler)</tt>.
- *
- * @li Constructs a function object @c f with a function call operator that
- * performs <tt>ex1.dispatch(std::move(handler), alloc)</tt> followed by
- * <tt>w.reset()</tt>.
- *
- * @li Performs <tt>Executor(ex).dispatch(std::move(f), alloc)</tt>.
- *
- * @li Returns <tt>result.get()</tt>.
- */
-template <typename Executor, typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) dispatch(
-    const Executor& ex, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_executor<Executor>::value>::type* = 0);
-
-/// Submits a completion token or function object for execution.
-/**
- * @returns <tt>dispatch(ctx.get_executor(),
- * forward<CompletionToken>(token))</tt>.
- */
-template <typename ExecutionContext, typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) dispatch(
-    ExecutionContext& ctx, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_convertible<
-      ExecutionContext&, execution_context&>::value>::type* = 0);
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/dispatch.hpp"
-
-#endif // ASIO_DISPATCH_HPP
diff --git a/tools/sdk/include/asio/asio/error.hpp b/tools/sdk/include/asio/asio/error.hpp
deleted file mode 100644
index 2be9bdeed82..00000000000
--- a/tools/sdk/include/asio/asio/error.hpp
+++ /dev/null
@@ -1,356 +0,0 @@
-//
-// error.hpp
-// ~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_ERROR_HPP
-#define ASIO_ERROR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/error_code.hpp"
-#include "asio/system_error.hpp"
-#if defined(ASIO_WINDOWS) \
-  || defined(__CYGWIN__) \
-  || defined(ASIO_WINDOWS_RUNTIME)
-# include <winerror.h>
-#else
-# include <cerrno>
-# include <netdb.h>
-#endif
-
-#if defined(GENERATING_DOCUMENTATION)
-/// INTERNAL ONLY.
-# define ASIO_NATIVE_ERROR(e) implementation_defined
-/// INTERNAL ONLY.
-# define ASIO_SOCKET_ERROR(e) implementation_defined
-/// INTERNAL ONLY.
-# define ASIO_NETDB_ERROR(e) implementation_defined
-/// INTERNAL ONLY.
-# define ASIO_GETADDRINFO_ERROR(e) implementation_defined
-/// INTERNAL ONLY.
-# define ASIO_WIN_OR_POSIX(e_win, e_posix) implementation_defined
-#elif defined(ASIO_WINDOWS_RUNTIME)
-# define ASIO_NATIVE_ERROR(e) __HRESULT_FROM_WIN32(e)
-# define ASIO_SOCKET_ERROR(e) __HRESULT_FROM_WIN32(WSA ## e)
-# define ASIO_NETDB_ERROR(e) __HRESULT_FROM_WIN32(WSA ## e)
-# define ASIO_GETADDRINFO_ERROR(e) __HRESULT_FROM_WIN32(WSA ## e)
-# define ASIO_WIN_OR_POSIX(e_win, e_posix) e_win
-#elif defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-# define ASIO_NATIVE_ERROR(e) e
-# define ASIO_SOCKET_ERROR(e) WSA ## e
-# define ASIO_NETDB_ERROR(e) WSA ## e
-# define ASIO_GETADDRINFO_ERROR(e) WSA ## e
-# define ASIO_WIN_OR_POSIX(e_win, e_posix) e_win
-#else
-# define ASIO_NATIVE_ERROR(e) e
-# define ASIO_SOCKET_ERROR(e) e
-# define ASIO_NETDB_ERROR(e) e
-# define ASIO_GETADDRINFO_ERROR(e) e
-# define ASIO_WIN_OR_POSIX(e_win, e_posix) e_posix
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace error {
-
-enum basic_errors
-{
-  /// Permission denied.
-  access_denied = ASIO_SOCKET_ERROR(EACCES),
-
-  /// Address family not supported by protocol.
-  address_family_not_supported = ASIO_SOCKET_ERROR(EAFNOSUPPORT),
-
-  /// Address already in use.
-  address_in_use = ASIO_SOCKET_ERROR(EADDRINUSE),
-
-  /// Transport endpoint is already connected.
-  already_connected = ASIO_SOCKET_ERROR(EISCONN),
-
-  /// Operation already in progress.
-  already_started = ASIO_SOCKET_ERROR(EALREADY),
-
-  /// Broken pipe.
-  broken_pipe = ASIO_WIN_OR_POSIX(
-      ASIO_NATIVE_ERROR(ERROR_BROKEN_PIPE),
-      ASIO_NATIVE_ERROR(EPIPE)),
-
-  /// A connection has been aborted.
-  connection_aborted = ASIO_SOCKET_ERROR(ECONNABORTED),
-
-  /// Connection refused.
-  connection_refused = ASIO_SOCKET_ERROR(ECONNREFUSED),
-
-  /// Connection reset by peer.
-  connection_reset = ASIO_SOCKET_ERROR(ECONNRESET),
-
-  /// Bad file descriptor.
-  bad_descriptor = ASIO_SOCKET_ERROR(EBADF),
-
-  /// Bad address.
-  fault = ASIO_SOCKET_ERROR(EFAULT),
-
-  /// No route to host.
-  host_unreachable = ASIO_SOCKET_ERROR(EHOSTUNREACH),
-
-  /// Operation now in progress.
-  in_progress = ASIO_SOCKET_ERROR(EINPROGRESS),
-
-  /// Interrupted system call.
-  interrupted = ASIO_SOCKET_ERROR(EINTR),
-
-  /// Invalid argument.
-  invalid_argument = ASIO_SOCKET_ERROR(EINVAL),
-
-  /// Message too long.
-  message_size = ASIO_SOCKET_ERROR(EMSGSIZE),
-
-  /// The name was too long.
-  name_too_long = ASIO_SOCKET_ERROR(ENAMETOOLONG),
-
-  /// Network is down.
-  network_down = ASIO_SOCKET_ERROR(ENETDOWN),
-
-  /// Network dropped connection on reset.
-  network_reset = ASIO_SOCKET_ERROR(ENETRESET),
-
-  /// Network is unreachable.
-  network_unreachable = ASIO_SOCKET_ERROR(ENETUNREACH),
-
-  /// Too many open files.
-  no_descriptors = ASIO_SOCKET_ERROR(EMFILE),
-
-  /// No buffer space available.
-  no_buffer_space = ASIO_SOCKET_ERROR(ENOBUFS),
-
-  /// Cannot allocate memory.
-  no_memory = ASIO_WIN_OR_POSIX(
-      ASIO_NATIVE_ERROR(ERROR_OUTOFMEMORY),
-      ASIO_NATIVE_ERROR(ENOMEM)),
-
-  /// Operation not permitted.
-  no_permission = ASIO_WIN_OR_POSIX(
-      ASIO_NATIVE_ERROR(ERROR_ACCESS_DENIED),
-      ASIO_NATIVE_ERROR(EPERM)),
-
-  /// Protocol not available.
-  no_protocol_option = ASIO_SOCKET_ERROR(ENOPROTOOPT),
-
-  /// No such device.
-  no_such_device = ASIO_WIN_OR_POSIX(
-      ASIO_NATIVE_ERROR(ERROR_BAD_UNIT),
-      ASIO_NATIVE_ERROR(ENODEV)),
-
-  /// Transport endpoint is not connected.
-  not_connected = ASIO_SOCKET_ERROR(ENOTCONN),
-
-  /// Socket operation on non-socket.
-  not_socket = ASIO_SOCKET_ERROR(ENOTSOCK),
-
-  /// Operation cancelled.
-  operation_aborted = ASIO_WIN_OR_POSIX(
-      ASIO_NATIVE_ERROR(ERROR_OPERATION_ABORTED),
-      ASIO_NATIVE_ERROR(ECANCELED)),
-
-  /// Operation not supported.
-  operation_not_supported = ASIO_SOCKET_ERROR(EOPNOTSUPP),
-
-  /// Cannot send after transport endpoint shutdown.
-  shut_down = ASIO_SOCKET_ERROR(ESHUTDOWN),
-
-  /// Connection timed out.
-  timed_out = ASIO_SOCKET_ERROR(ETIMEDOUT),
-
-  /// Resource temporarily unavailable.
-  try_again = ASIO_WIN_OR_POSIX(
-      ASIO_NATIVE_ERROR(ERROR_RETRY),
-      ASIO_NATIVE_ERROR(EAGAIN)),
-
-  /// The socket is marked non-blocking and the requested operation would block.
-  would_block = ASIO_SOCKET_ERROR(EWOULDBLOCK)
-};
-
-enum netdb_errors
-{
-  /// Host not found (authoritative).
-  host_not_found = ASIO_NETDB_ERROR(HOST_NOT_FOUND),
-
-  /// Host not found (non-authoritative).
-  host_not_found_try_again = ASIO_NETDB_ERROR(TRY_AGAIN),
-
-  /// The query is valid but does not have associated address data.
-  no_data = ASIO_NETDB_ERROR(NO_DATA),
-
-  /// A non-recoverable error occurred.
-  no_recovery = ASIO_NETDB_ERROR(NO_RECOVERY)
-};
-
-enum addrinfo_errors
-{
-  /// The service is not supported for the given socket type.
-  service_not_found = ASIO_WIN_OR_POSIX(
-      ASIO_NATIVE_ERROR(WSATYPE_NOT_FOUND),
-      ASIO_GETADDRINFO_ERROR(EAI_SERVICE)),
-
-  /// The socket type is not supported.
-  socket_type_not_supported = ASIO_WIN_OR_POSIX(
-      ASIO_NATIVE_ERROR(WSAESOCKTNOSUPPORT),
-      ASIO_GETADDRINFO_ERROR(EAI_SOCKTYPE))
-};
-
-enum misc_errors
-{
-  /// Already open.
-  already_open = 1,
-
-  /// End of file or stream.
-  eof,
-
-  /// Element not found.
-  not_found,
-
-  /// The descriptor cannot fit into the select system call's fd_set.
-  fd_set_failure
-};
-
-inline const asio::error_category& get_system_category()
-{
-  return asio::system_category();
-}
-
-#if !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-extern ASIO_DECL
-const asio::error_category& get_netdb_category();
-
-extern ASIO_DECL
-const asio::error_category& get_addrinfo_category();
-
-#else // !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-inline const asio::error_category& get_netdb_category()
-{
-  return get_system_category();
-}
-
-inline const asio::error_category& get_addrinfo_category()
-{
-  return get_system_category();
-}
-
-#endif // !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-extern ASIO_DECL
-const asio::error_category& get_misc_category();
-
-static const asio::error_category&
-  system_category ASIO_UNUSED_VARIABLE
-  = asio::error::get_system_category();
-static const asio::error_category&
-  netdb_category ASIO_UNUSED_VARIABLE
-  = asio::error::get_netdb_category();
-static const asio::error_category&
-  addrinfo_category ASIO_UNUSED_VARIABLE
-  = asio::error::get_addrinfo_category();
-static const asio::error_category&
-  misc_category ASIO_UNUSED_VARIABLE
-  = asio::error::get_misc_category();
-
-} // namespace error
-} // namespace asio
-
-#if defined(ASIO_HAS_STD_SYSTEM_ERROR)
-namespace std {
-
-template<> struct is_error_code_enum<asio::error::basic_errors>
-{
-  static const bool value = true;
-};
-
-template<> struct is_error_code_enum<asio::error::netdb_errors>
-{
-  static const bool value = true;
-};
-
-template<> struct is_error_code_enum<asio::error::addrinfo_errors>
-{
-  static const bool value = true;
-};
-
-template<> struct is_error_code_enum<asio::error::misc_errors>
-{
-  static const bool value = true;
-};
-
-} // namespace std
-#endif // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-namespace asio {
-namespace error {
-
-inline asio::error_code make_error_code(basic_errors e)
-{
-  return asio::error_code(
-      static_cast<int>(e), get_system_category());
-}
-
-inline asio::error_code make_error_code(netdb_errors e)
-{
-  return asio::error_code(
-      static_cast<int>(e), get_netdb_category());
-}
-
-inline asio::error_code make_error_code(addrinfo_errors e)
-{
-  return asio::error_code(
-      static_cast<int>(e), get_addrinfo_category());
-}
-
-inline asio::error_code make_error_code(misc_errors e)
-{
-  return asio::error_code(
-      static_cast<int>(e), get_misc_category());
-}
-
-} // namespace error
-namespace stream_errc {
-  // Simulates the proposed stream_errc scoped enum.
-  using error::eof;
-  using error::not_found;
-} // namespace stream_errc
-namespace socket_errc {
-  // Simulates the proposed socket_errc scoped enum.
-  using error::already_open;
-  using error::not_found;
-} // namespace socket_errc
-namespace resolver_errc {
-  // Simulates the proposed resolver_errc scoped enum.
-  using error::host_not_found;
-  const error::netdb_errors try_again = error::host_not_found_try_again;
-  using error::service_not_found;
-} // namespace resolver_errc
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#undef ASIO_NATIVE_ERROR
-#undef ASIO_SOCKET_ERROR
-#undef ASIO_NETDB_ERROR
-#undef ASIO_GETADDRINFO_ERROR
-#undef ASIO_WIN_OR_POSIX
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/impl/error.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_ERROR_HPP
diff --git a/tools/sdk/include/asio/asio/error_code.hpp b/tools/sdk/include/asio/asio/error_code.hpp
deleted file mode 100644
index 042ab85388b..00000000000
--- a/tools/sdk/include/asio/asio/error_code.hpp
+++ /dev/null
@@ -1,206 +0,0 @@
-//
-// error_code.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_ERROR_CODE_HPP
-#define ASIO_ERROR_CODE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#ifdef ESP_PLATFORM
-# include "lwip/sockets.h"
-#endif
-
-#if defined(ASIO_HAS_STD_SYSTEM_ERROR)
-# include <system_error>
-#else // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-# include <string>
-# include "asio/detail/noncopyable.hpp"
-# if !defined(ASIO_NO_IOSTREAM)
-#  include <iosfwd>
-# endif // !defined(ASIO_NO_IOSTREAM)
-#endif // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-#if defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-typedef std::error_category error_category;
-
-#else // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-/// Base class for all error categories.
-class error_category : private noncopyable
-{
-public:
-  /// Destructor.
-  virtual ~error_category()
-  {
-  }
-
-  /// Returns a string naming the error gategory.
-  virtual const char* name() const = 0;
-
-  /// Returns a string describing the error denoted by @c value.
-  virtual std::string message(int value) const = 0;
-
-  /// Equality operator to compare two error categories.
-  bool operator==(const error_category& rhs) const
-  {
-    return this == &rhs;
-  }
-
-  /// Inequality operator to compare two error categories.
-  bool operator!=(const error_category& rhs) const
-  {
-    return !(*this == rhs);
-  }
-};
-
-#endif // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-/// Returns the error category used for the system errors produced by asio.
-extern ASIO_DECL const error_category& system_category();
-
-#if defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-typedef std::error_code error_code;
-
-#else // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-/// Class to represent an error code value.
-class error_code
-{
-public:
-  /// Default constructor.
-  error_code()
-    : value_(0),
-      category_(&system_category())
-  {
-  }
-
-  /// Construct with specific error code and category.
-  error_code(int v, const error_category& c)
-    : value_(v),
-      category_(&c)
-  {
-  }
-
-  /// Construct from an error code enum.
-  template <typename ErrorEnum>
-  error_code(ErrorEnum e)
-  {
-    *this = make_error_code(e);
-  }
-
-  /// Clear the error value to the default.
-  void clear()
-  {
-    value_ = 0;
-    category_ = &system_category();
-  }
-
-  /// Assign a new error value.
-  void assign(int v, const error_category& c)
-  {
-    value_ = v;
-    category_ = &c;
-  }
-
-  /// Get the error value.
-  int value() const
-  {
-    return value_;
-  }
-
-  /// Get the error category.
-  const error_category& category() const
-  {
-    return *category_;
-  }
-
-  /// Get the message associated with the error.
-  std::string message() const
-  {
-    return category_->message(value_);
-  }
-
-  struct unspecified_bool_type_t
-  {
-  };
-
-  typedef void (*unspecified_bool_type)(unspecified_bool_type_t);
-
-  static void unspecified_bool_true(unspecified_bool_type_t) {}
-
-  /// Operator returns non-null if there is a non-success error code.
-  operator unspecified_bool_type() const
-  {
-    if (value_ == 0)
-      return 0;
-    else
-      return &error_code::unspecified_bool_true;
-  }
-
-  /// Operator to test if the error represents success.
-  bool operator!() const
-  {
-    return value_ == 0;
-  }
-
-  /// Equality operator to compare two error objects.
-  friend bool operator==(const error_code& e1, const error_code& e2)
-  {
-    return e1.value_ == e2.value_ && e1.category_ == e2.category_;
-  }
-
-  /// Inequality operator to compare two error objects.
-  friend bool operator!=(const error_code& e1, const error_code& e2)
-  {
-    return e1.value_ != e2.value_ || e1.category_ != e2.category_;
-  }
-
-private:
-  // The value associated with the error code.
-  int value_;
-
-  // The category associated with the error code.
-  const error_category* category_;
-};
-
-# if !defined(ASIO_NO_IOSTREAM)
-
-/// Output an error code.
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const error_code& ec)
-{
-  os << ec.category().name() << ':' << ec.value();
-  return os;
-}
-
-# endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/impl/error_code.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_ERROR_CODE_HPP
diff --git a/tools/sdk/include/asio/asio/execution_context.hpp b/tools/sdk/include/asio/asio/execution_context.hpp
deleted file mode 100644
index 1476d19b5b4..00000000000
--- a/tools/sdk/include/asio/asio/execution_context.hpp
+++ /dev/null
@@ -1,411 +0,0 @@
-//
-// execution_context.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXECUTION_CONTEXT_HPP
-#define ASIO_EXECUTION_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <stdexcept>
-#include <typeinfo>
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/variadic_templates.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-class execution_context;
-class io_context;
-
-#if !defined(GENERATING_DOCUMENTATION)
-template <typename Service> Service& use_service(execution_context&);
-template <typename Service> Service& use_service(io_context&);
-template <typename Service> void add_service(execution_context&, Service*);
-template <typename Service> bool has_service(execution_context&);
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-namespace detail { class service_registry; }
-
-/// A context for function object execution.
-/**
- * An execution context represents a place where function objects will be
- * executed. An @c io_context is an example of an execution context.
- *
- * @par The execution_context class and services
- *
- * Class execution_context implements an extensible, type-safe, polymorphic set
- * of services, indexed by service type.
- *
- * Services exist to manage the resources that are shared across an execution
- * context. For example, timers may be implemented in terms of a single timer
- * queue, and this queue would be stored in a service.
- *
- * Access to the services of an execution_context is via three function
- * templates, use_service(), add_service() and has_service().
- *
- * In a call to @c use_service<Service>(), the type argument chooses a service,
- * making available all members of the named type. If @c Service is not present
- * in an execution_context, an object of type @c Service is created and added
- * to the execution_context. A C++ program can check if an execution_context
- * implements a particular service with the function template @c
- * has_service<Service>().
- *
- * Service objects may be explicitly added to an execution_context using the
- * function template @c add_service<Service>(). If the @c Service is already
- * present, the service_already_exists exception is thrown. If the owner of the
- * service is not the same object as the execution_context parameter, the
- * invalid_service_owner exception is thrown.
- *
- * Once a service reference is obtained from an execution_context object by
- * calling use_service(), that reference remains usable as long as the owning
- * execution_context object exists.
- *
- * All service implementations have execution_context::service as a public base
- * class. Custom services may be implemented by deriving from this class and
- * then added to an execution_context using the facilities described above.
- *
- * @par The execution_context as a base class
- *
- * Class execution_context may be used only as a base class for concrete
- * execution context types. The @c io_context is an example of such a derived
- * type.
- *
- * On destruction, a class that is derived from execution_context must perform
- * <tt>execution_context::shutdown()</tt> followed by
- * <tt>execution_context::destroy()</tt>.
- *
- * This destruction sequence permits programs to simplify their resource
- * management by using @c shared_ptr<>. Where an object's lifetime is tied to
- * the lifetime of a connection (or some other sequence of asynchronous
- * operations), a @c shared_ptr to the object would be bound into the handlers
- * for all asynchronous operations associated with it. This works as follows:
- *
- * @li When a single connection ends, all associated asynchronous operations
- * complete. The corresponding handler objects are destroyed, and all @c
- * shared_ptr references to the objects are destroyed.
- *
- * @li To shut down the whole program, the io_context function stop() is called
- * to terminate any run() calls as soon as possible. The io_context destructor
- * calls @c shutdown() and @c destroy() to destroy all pending handlers,
- * causing all @c shared_ptr references to all connection objects to be
- * destroyed.
- */
-class execution_context
-  : private noncopyable
-{
-public:
-  class id;
-  class service;
-
-protected:
-  /// Constructor.
-  ASIO_DECL execution_context();
-
-  /// Destructor.
-  ASIO_DECL ~execution_context();
-
-  /// Shuts down all services in the context.
-  /**
-   * This function is implemented as follows:
-   *
-   * @li For each service object @c svc in the execution_context set, in
-   * reverse order of the beginning of service object lifetime, performs @c
-   * svc->shutdown().
-   */
-  ASIO_DECL void shutdown();
-
-  /// Destroys all services in the context.
-  /**
-   * This function is implemented as follows:
-   *
-   * @li For each service object @c svc in the execution_context set, in
-   * reverse order * of the beginning of service object lifetime, performs
-   * <tt>delete static_cast<execution_context::service*>(svc)</tt>.
-   */
-  ASIO_DECL void destroy();
-
-public:
-  /// Fork-related event notifications.
-  enum fork_event
-  {
-    /// Notify the context that the process is about to fork.
-    fork_prepare,
-
-    /// Notify the context that the process has forked and is the parent.
-    fork_parent,
-
-    /// Notify the context that the process has forked and is the child.
-    fork_child
-  };
-
-  /// Notify the execution_context of a fork-related event.
-  /**
-   * This function is used to inform the execution_context that the process is
-   * about to fork, or has just forked. This allows the execution_context, and
-   * the services it contains, to perform any necessary housekeeping to ensure
-   * correct operation following a fork.
-   *
-   * This function must not be called while any other execution_context
-   * function, or any function associated with the execution_context's derived
-   * class, is being called in another thread. It is, however, safe to call
-   * this function from within a completion handler, provided no other thread
-   * is accessing the execution_context or its derived class.
-   *
-   * @param event A fork-related event.
-   *
-   * @throws asio::system_error Thrown on failure. If the notification
-   * fails the execution_context object should no longer be used and should be
-   * destroyed.
-   *
-   * @par Example
-   * The following code illustrates how to incorporate the notify_fork()
-   * function:
-   * @code my_execution_context.notify_fork(execution_context::fork_prepare);
-   * if (fork() == 0)
-   * {
-   *   // This is the child process.
-   *   my_execution_context.notify_fork(execution_context::fork_child);
-   * }
-   * else
-   * {
-   *   // This is the parent process.
-   *   my_execution_context.notify_fork(execution_context::fork_parent);
-   * } @endcode
-   *
-   * @note For each service object @c svc in the execution_context set,
-   * performs <tt>svc->notify_fork();</tt>. When processing the fork_prepare
-   * event, services are visited in reverse order of the beginning of service
-   * object lifetime. Otherwise, services are visited in order of the beginning
-   * of service object lifetime.
-   */
-  ASIO_DECL void notify_fork(fork_event event);
-
-  /// Obtain the service object corresponding to the given type.
-  /**
-   * This function is used to locate a service object that corresponds to the
-   * given service type. If there is no existing implementation of the service,
-   * then the execution_context will create a new instance of the service.
-   *
-   * @param e The execution_context object that owns the service.
-   *
-   * @return The service interface implementing the specified service type.
-   * Ownership of the service interface is not transferred to the caller.
-   */
-  template <typename Service>
-  friend Service& use_service(execution_context& e);
-
-  /// Obtain the service object corresponding to the given type.
-  /**
-   * This function is used to locate a service object that corresponds to the
-   * given service type. If there is no existing implementation of the service,
-   * then the io_context will create a new instance of the service.
-   *
-   * @param ioc The io_context object that owns the service.
-   *
-   * @return The service interface implementing the specified service type.
-   * Ownership of the service interface is not transferred to the caller.
-   *
-   * @note This overload is preserved for backwards compatibility with services
-   * that inherit from io_context::service.
-   */
-  template <typename Service>
-  friend Service& use_service(io_context& ioc);
-
-#if defined(GENERATING_DOCUMENTATION)
-
-  /// Creates a service object and adds it to the execution_context.
-  /**
-   * This function is used to add a service to the execution_context.
-   *
-   * @param e The execution_context object that owns the service.
-   *
-   * @param args Zero or more arguments to be passed to the service
-   * constructor.
-   *
-   * @throws asio::service_already_exists Thrown if a service of the
-   * given type is already present in the execution_context.
-   */
-  template <typename Service, typename... Args>
-  friend Service& make_service(execution_context& e, Args&&... args);
-
-#elif defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  template <typename Service, typename... Args>
-  friend Service& make_service(execution_context& e,
-      ASIO_MOVE_ARG(Args)... args);
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  template <typename Service>
-  friend Service& make_service(execution_context& e);
-
-#define ASIO_PRIVATE_MAKE_SERVICE_DEF(n) \
-  template <typename Service, ASIO_VARIADIC_TPARAMS(n)> \
-  friend Service& make_service(execution_context& e, \
-      ASIO_VARIADIC_MOVE_PARAMS(n)); \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_MAKE_SERVICE_DEF)
-#undef ASIO_PRIVATE_MAKE_SERVICE_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  /// (Deprecated: Use make_service().) Add a service object to the
-  /// execution_context.
-  /**
-   * This function is used to add a service to the execution_context.
-   *
-   * @param e The execution_context object that owns the service.
-   *
-   * @param svc The service object. On success, ownership of the service object
-   * is transferred to the execution_context. When the execution_context object
-   * is destroyed, it will destroy the service object by performing: @code
-   * delete static_cast<execution_context::service*>(svc) @endcode
-   *
-   * @throws asio::service_already_exists Thrown if a service of the
-   * given type is already present in the execution_context.
-   *
-   * @throws asio::invalid_service_owner Thrown if the service's owning
-   * execution_context is not the execution_context object specified by the
-   * @c e parameter.
-   */
-  template <typename Service>
-  friend void add_service(execution_context& e, Service* svc);
-
-  /// Determine if an execution_context contains a specified service type.
-  /**
-   * This function is used to determine whether the execution_context contains a
-   * service object corresponding to the given service type.
-   *
-   * @param e The execution_context object that owns the service.
-   *
-   * @return A boolean indicating whether the execution_context contains the
-   * service.
-   */
-  template <typename Service>
-  friend bool has_service(execution_context& e);
-
-private:
-  // The service registry.
-  asio::detail::service_registry* service_registry_;
-};
-
-/// Class used to uniquely identify a service.
-class execution_context::id
-  : private noncopyable
-{
-public:
-  /// Constructor.
-  id() {}
-};
-
-/// Base class for all io_context services.
-class execution_context::service
-  : private noncopyable
-{
-public:
-  /// Get the context object that owns the service.
-  execution_context& context();
-
-protected:
-  /// Constructor.
-  /**
-   * @param owner The execution_context object that owns the service.
-   */
-  ASIO_DECL service(execution_context& owner);
-
-  /// Destructor.
-  ASIO_DECL virtual ~service();
-
-private:
-  /// Destroy all user-defined handler objects owned by the service.
-  virtual void shutdown() = 0;
-
-  /// Handle notification of a fork-related event to perform any necessary
-  /// housekeeping.
-  /**
-   * This function is not a pure virtual so that services only have to
-   * implement it if necessary. The default implementation does nothing.
-   */
-  ASIO_DECL virtual void notify_fork(
-      execution_context::fork_event event);
-
-  friend class asio::detail::service_registry;
-  struct key
-  {
-    key() : type_info_(0), id_(0) {}
-    const std::type_info* type_info_;
-    const execution_context::id* id_;
-  } key_;
-
-  execution_context& owner_;
-  service* next_;
-};
-
-/// Exception thrown when trying to add a duplicate service to an
-/// execution_context.
-class service_already_exists
-  : public std::logic_error
-{
-public:
-  ASIO_DECL service_already_exists();
-};
-
-/// Exception thrown when trying to add a service object to an
-/// execution_context where the service has a different owner.
-class invalid_service_owner
-  : public std::logic_error
-{
-public:
-  ASIO_DECL invalid_service_owner();
-};
-
-namespace detail {
-
-// Special derived service id type to keep classes header-file only.
-template <typename Type>
-class service_id
-  : public execution_context::id
-{
-};
-
-// Special service base class to keep classes header-file only.
-template <typename Type>
-class execution_context_service_base
-  : public execution_context::service
-{
-public:
-  static service_id<Type> id;
-
-  // Constructor.
-  execution_context_service_base(execution_context& e)
-    : execution_context::service(e)
-  {
-  }
-};
-
-template <typename Type>
-service_id<Type> execution_context_service_base<Type>::id;
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/execution_context.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/impl/execution_context.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_EXECUTION_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/executor.hpp b/tools/sdk/include/asio/asio/executor.hpp
deleted file mode 100644
index e552cfbf2e3..00000000000
--- a/tools/sdk/include/asio/asio/executor.hpp
+++ /dev/null
@@ -1,341 +0,0 @@
-//
-// executor.hpp
-// ~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXECUTOR_HPP
-#define ASIO_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <typeinfo>
-#include "asio/detail/cstddef.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/throw_exception.hpp"
-#include "asio/execution_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Exception thrown when trying to access an empty polymorphic executor.
-class bad_executor
-  : public std::exception
-{
-public:
-  /// Constructor.
-  ASIO_DECL bad_executor() ASIO_NOEXCEPT;
-
-  /// Obtain message associated with exception.
-  ASIO_DECL virtual const char* what() const
-    ASIO_NOEXCEPT_OR_NOTHROW;
-};
-
-/// Polymorphic wrapper for executors.
-class executor
-{
-public:
-  /// Default constructor.
-  executor() ASIO_NOEXCEPT
-    : impl_(0)
-  {
-  }
-
-  /// Construct from nullptr.
-  executor(nullptr_t) ASIO_NOEXCEPT
-    : impl_(0)
-  {
-  }
-
-  /// Copy constructor.
-  executor(const executor& other) ASIO_NOEXCEPT
-    : impl_(other.clone())
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move constructor.
-  executor(executor&& other) ASIO_NOEXCEPT
-    : impl_(other.impl_)
-  {
-    other.impl_ = 0;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Construct a polymorphic wrapper for the specified executor.
-  template <typename Executor>
-  executor(Executor e);
-
-  /// Allocator-aware constructor to create a polymorphic wrapper for the
-  /// specified executor.
-  template <typename Executor, typename Allocator>
-  executor(allocator_arg_t, const Allocator& a, Executor e);
-
-  /// Destructor.
-  ~executor()
-  {
-    destroy();
-  }
-
-  /// Assignment operator.
-  executor& operator=(const executor& other) ASIO_NOEXCEPT
-  {
-    destroy();
-    impl_ = other.clone();
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  // Move assignment operator.
-  executor& operator=(executor&& other) ASIO_NOEXCEPT
-  {
-    destroy();
-    impl_ = other.impl_;
-    other.impl_ = 0;
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Assignment operator for nullptr_t.
-  executor& operator=(nullptr_t) ASIO_NOEXCEPT
-  {
-    destroy();
-    impl_ = 0;
-    return *this;
-  }
-
-  /// Assignment operator to create a polymorphic wrapper for the specified
-  /// executor.
-  template <typename Executor>
-  executor& operator=(ASIO_MOVE_ARG(Executor) e) ASIO_NOEXCEPT
-  {
-    executor tmp(ASIO_MOVE_CAST(Executor)(e));
-    destroy();
-    impl_ = tmp.impl_;
-    tmp.impl_ = 0;
-    return *this;
-  }
-
-  /// Obtain the underlying execution context.
-  execution_context& context() const ASIO_NOEXCEPT
-  {
-    return get_impl()->context();
-  }
-
-  /// Inform the executor that it has some outstanding work to do.
-  void on_work_started() const ASIO_NOEXCEPT
-  {
-    get_impl()->on_work_started();
-  }
-
-  /// Inform the executor that some work is no longer outstanding.
-  void on_work_finished() const ASIO_NOEXCEPT
-  {
-    get_impl()->on_work_finished();
-  }
-
-  /// Request the executor to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object is executed according to the rules of the
-   * target executor object.
-   *
-   * @param f The function object to be called. The executor will make a copy
-   * of the handler object as required. The function signature of the function
-   * object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void dispatch(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Request the executor to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object is executed according to the rules of the
-   * target executor object.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void post(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Request the executor to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object is executed according to the rules of the
-   * target executor object.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void defer(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  struct unspecified_bool_type_t {};
-  typedef void (*unspecified_bool_type)(unspecified_bool_type_t);
-  static void unspecified_bool_true(unspecified_bool_type_t) {}
-
-  /// Operator to test if the executor contains a valid target.
-  operator unspecified_bool_type() const ASIO_NOEXCEPT
-  {
-    return impl_ ? &executor::unspecified_bool_true : 0;
-  }
-
-  /// Obtain type information for the target executor object.
-  /**
-   * @returns If @c *this has a target type of type @c T, <tt>typeid(T)</tt>;
-   * otherwise, <tt>typeid(void)</tt>.
-   */
-#if !defined(ASIO_NO_TYPEID) || defined(GENERATING_DOCUMENTATION)
-  const std::type_info& target_type() const ASIO_NOEXCEPT
-  {
-    return impl_ ? impl_->target_type() : typeid(void);
-  }
-#else // !defined(ASIO_NO_TYPEID) || defined(GENERATING_DOCUMENTATION)
-  const void* target_type() const ASIO_NOEXCEPT
-  {
-    return impl_ ? impl_->target_type() : 0;
-  }
-#endif // !defined(ASIO_NO_TYPEID) || defined(GENERATING_DOCUMENTATION)
-
-  /// Obtain a pointer to the target executor object.
-  /**
-   * @returns If <tt>target_type() == typeid(T)</tt>, a pointer to the stored
-   * executor target; otherwise, a null pointer.
-   */
-  template <typename Executor>
-  Executor* target() ASIO_NOEXCEPT;
-
-  /// Obtain a pointer to the target executor object.
-  /**
-   * @returns If <tt>target_type() == typeid(T)</tt>, a pointer to the stored
-   * executor target; otherwise, a null pointer.
-   */
-  template <typename Executor>
-  const Executor* target() const ASIO_NOEXCEPT;
-
-  /// Compare two executors for equality.
-  friend bool operator==(const executor& a,
-      const executor& b) ASIO_NOEXCEPT
-  {
-    if (a.impl_ == b.impl_)
-      return true;
-    if (!a.impl_ || !b.impl_)
-      return false;
-    return a.impl_->equals(b.impl_);
-  }
-
-  /// Compare two executors for inequality.
-  friend bool operator!=(const executor& a,
-      const executor& b) ASIO_NOEXCEPT
-  {
-    return !(a == b);
-  }
-
-private:
-#if !defined(GENERATING_DOCUMENTATION)
-  class function;
-  template <typename, typename> class impl;
-
-#if !defined(ASIO_NO_TYPEID)
-  typedef const std::type_info& type_id_result_type;
-#else // !defined(ASIO_NO_TYPEID)
-  typedef const void* type_id_result_type;
-#endif // !defined(ASIO_NO_TYPEID)
-
-  template <typename T>
-  static type_id_result_type type_id()
-  {
-#if !defined(ASIO_NO_TYPEID)
-    return typeid(T);
-#else // !defined(ASIO_NO_TYPEID)
-    static int unique_id;
-    return &unique_id;
-#endif // !defined(ASIO_NO_TYPEID)
-  }
-
-  // Base class for all polymorphic executor implementations.
-  class impl_base
-  {
-  public:
-    virtual impl_base* clone() const ASIO_NOEXCEPT = 0;
-    virtual void destroy() ASIO_NOEXCEPT = 0;
-    virtual execution_context& context() ASIO_NOEXCEPT = 0;
-    virtual void on_work_started() ASIO_NOEXCEPT = 0;
-    virtual void on_work_finished() ASIO_NOEXCEPT = 0;
-    virtual void dispatch(ASIO_MOVE_ARG(function)) = 0;
-    virtual void post(ASIO_MOVE_ARG(function)) = 0;
-    virtual void defer(ASIO_MOVE_ARG(function)) = 0;
-    virtual type_id_result_type target_type() const ASIO_NOEXCEPT = 0;
-    virtual void* target() ASIO_NOEXCEPT = 0;
-    virtual const void* target() const ASIO_NOEXCEPT = 0;
-    virtual bool equals(const impl_base* e) const ASIO_NOEXCEPT = 0;
-
-  protected:
-    impl_base(bool fast_dispatch) : fast_dispatch_(fast_dispatch) {}
-    virtual ~impl_base() {}
-
-  private:
-    friend class executor;
-    const bool fast_dispatch_;
-  };
-
-  // Helper function to check and return the implementation pointer.
-  impl_base* get_impl() const
-  {
-    if (!impl_)
-    {
-      bad_executor ex;
-      asio::detail::throw_exception(ex);
-    }
-    return impl_;
-  }
-
-  // Helper function to clone another implementation.
-  impl_base* clone() const ASIO_NOEXCEPT
-  {
-    return impl_ ? impl_->clone() : 0;
-  }
-
-  // Helper function to destroy an implementation.
-  void destroy() ASIO_NOEXCEPT
-  {
-    if (impl_)
-      impl_->destroy();
-  }
-
-  impl_base* impl_;
-#endif // !defined(GENERATING_DOCUMENTATION)
-};
-
-} // namespace asio
-
-ASIO_USES_ALLOCATOR(asio::executor)
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/executor.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/impl/executor.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/executor_work_guard.hpp b/tools/sdk/include/asio/asio/executor_work_guard.hpp
deleted file mode 100644
index 1875f542b21..00000000000
--- a/tools/sdk/include/asio/asio/executor_work_guard.hpp
+++ /dev/null
@@ -1,170 +0,0 @@
-//
-// executor_work_guard.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXECUTOR_WORK_GUARD_HPP
-#define ASIO_EXECUTOR_WORK_GUARD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/is_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// An object of type @c executor_work_guard controls ownership of executor work
-/// within a scope.
-template <typename Executor>
-class executor_work_guard
-{
-public:
-  /// The underlying executor type.
-  typedef Executor executor_type;
-
-  /// Constructs a @c executor_work_guard object for the specified executor.
-  /**
-   * Stores a copy of @c e and calls <tt>on_work_started()</tt> on it.
-   */
-  explicit executor_work_guard(const executor_type& e) ASIO_NOEXCEPT
-    : executor_(e),
-      owns_(true)
-  {
-    executor_.on_work_started();
-  }
-
-  /// Copy constructor.
-  executor_work_guard(const executor_work_guard& other) ASIO_NOEXCEPT
-    : executor_(other.executor_),
-      owns_(other.owns_)
-  {
-    if (owns_)
-      executor_.on_work_started();
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move constructor.
-  executor_work_guard(executor_work_guard&& other)
-    : executor_(ASIO_MOVE_CAST(Executor)(other.executor_)),
-      owns_(other.owns_)
-  {
-    other.owns_ = false;
-  }
-#endif //  defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destructor.
-  /**
-   * Unless the object has already been reset, or is in a moved-from state,
-   * calls <tt>on_work_finished()</tt> on the stored executor.
-   */
-  ~executor_work_guard()
-  {
-    if (owns_)
-      executor_.on_work_finished();
-  }
-
-  /// Obtain the associated executor.
-  executor_type get_executor() const ASIO_NOEXCEPT
-  {
-    return executor_;
-  }
-
-  /// Whether the executor_work_guard object owns some outstanding work.
-  bool owns_work() const ASIO_NOEXCEPT
-  {
-    return owns_;
-  }
-
-  /// Indicate that the work is no longer outstanding.
-  /*
-   * Unless the object has already been reset, or is in a moved-from state,
-   * calls <tt>on_work_finished()</tt> on the stored executor.
-   */
-  void reset() ASIO_NOEXCEPT
-  {
-    if (owns_)
-    {
-      executor_.on_work_finished();
-      owns_ = false;
-    }
-  }
-
-private:
-  // Disallow assignment.
-  executor_work_guard& operator=(const executor_work_guard&);
-
-  executor_type executor_;
-  bool owns_;
-};
-
-/// Create an @ref executor_work_guard object.
-template <typename Executor>
-inline executor_work_guard<Executor> make_work_guard(const Executor& ex,
-    typename enable_if<is_executor<Executor>::value>::type* = 0)
-{
-  return executor_work_guard<Executor>(ex);
-}
-
-/// Create an @ref executor_work_guard object.
-template <typename ExecutionContext>
-inline executor_work_guard<typename ExecutionContext::executor_type>
-make_work_guard(ExecutionContext& ctx,
-    typename enable_if<
-      is_convertible<ExecutionContext&, execution_context&>::value>::type* = 0)
-{
-  return executor_work_guard<typename ExecutionContext::executor_type>(
-      ctx.get_executor());
-}
-
-/// Create an @ref executor_work_guard object.
-template <typename T>
-inline executor_work_guard<typename associated_executor<T>::type>
-make_work_guard(const T& t,
-    typename enable_if<!is_executor<T>::value &&
-      !is_convertible<T&, execution_context&>::value>::type* = 0)
-{
-  return executor_work_guard<typename associated_executor<T>::type>(
-      associated_executor<T>::get(t));
-}
-
-/// Create an @ref executor_work_guard object.
-template <typename T, typename Executor>
-inline executor_work_guard<typename associated_executor<T, Executor>::type>
-make_work_guard(const T& t, const Executor& ex,
-    typename enable_if<is_executor<Executor>::value>::type* = 0)
-{
-  return executor_work_guard<typename associated_executor<T, Executor>::type>(
-      associated_executor<T, Executor>::get(t, ex));
-}
-
-/// Create an @ref executor_work_guard object.
-template <typename T, typename ExecutionContext>
-inline executor_work_guard<typename associated_executor<T,
-  typename ExecutionContext::executor_type>::type>
-make_work_guard(const T& t, ExecutionContext& ctx,
-    typename enable_if<!is_executor<T>::value &&
-      !is_convertible<T&, execution_context&>::value &&
-      is_convertible<ExecutionContext&, execution_context&>::value>::type* = 0)
-{
-  return executor_work_guard<typename associated_executor<T,
-    typename ExecutionContext::executor_type>::type>(
-      associated_executor<T, typename ExecutionContext::executor_type>::get(
-        t, ctx.get_executor()));
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_EXECUTOR_WORK_GUARD_HPP
diff --git a/tools/sdk/include/asio/asio/experimental.hpp b/tools/sdk/include/asio/asio/experimental.hpp
deleted file mode 100644
index 5765c37d0ee..00000000000
--- a/tools/sdk/include/asio/asio/experimental.hpp
+++ /dev/null
@@ -1,22 +0,0 @@
-//
-// experimental.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2017 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXPERIMENTAL_HPP
-#define ASIO_EXPERIMENTAL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/experimental/co_spawn.hpp"
-#include "asio/experimental/detached.hpp"
-#include "asio/experimental/redirect_error.hpp"
-
-#endif // ASIO_EXPERIMENTAL_HPP
diff --git a/tools/sdk/include/asio/asio/experimental/co_spawn.hpp b/tools/sdk/include/asio/asio/experimental/co_spawn.hpp
deleted file mode 100644
index cbf5bc525e1..00000000000
--- a/tools/sdk/include/asio/asio/experimental/co_spawn.hpp
+++ /dev/null
@@ -1,226 +0,0 @@
-//
-// experimental/co_spawn.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXPERIMENTAL_CO_SPAWN_HPP
-#define ASIO_EXPERIMENTAL_CO_SPAWN_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_CO_AWAIT) || defined(GENERATING_DOCUMENTATION)
-
-#include <experimental/coroutine>
-#include "asio/executor.hpp"
-#include "asio/strand.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace experimental {
-namespace detail {
-
-using std::experimental::coroutine_handle;
-
-template <typename> class awaiter;
-template <typename> class awaitee_base;
-template <typename, typename> class awaitee;
-template <typename, typename> class await_handler_base;
-template <typename Executor, typename F, typename CompletionToken>
-auto co_spawn(const Executor& ex, F&& f, CompletionToken&& token);
-
-} // namespace detail
-
-namespace this_coro {
-
-/// Awaitable type that returns a completion token for the current coroutine.
-struct token_t {};
-
-/// Awaitable object that returns a completion token for the current coroutine.
-constexpr inline token_t token() { return {}; }
-
-/// Awaitable type that returns the executor of the current coroutine.
-struct executor_t {};
-
-/// Awaitable object that returns the executor of the current coroutine.
-constexpr inline executor_t executor() { return {}; }
-
-} // namespace this_coro
-
-/// A completion token that represents the currently executing coroutine.
-/**
- * The await_token class is used to represent the currently executing
- * coroutine. An await_token may be passed as a handler to an asynchronous
- * operation. For example:
- *
- * @code awaitable<void> my_coroutine()
- * {
- *   await_token token = co_await this_coro::token();
- *   ...
- *   std::size_t n = co_await my_socket.async_read_some(buffer, token);
- *   ...
- * } @endcode
- *
- * The initiating function (async_read_some in the above example) suspends the
- * current coroutine. The coroutine is resumed when the asynchronous operation
- * completes, and the result of the operation is returned.
- */
-template <typename Executor>
-class await_token
-{
-public:
-  /// The associated executor type.
-  typedef Executor executor_type;
-
-  /// Copy constructor.
-  await_token(const await_token& other) noexcept
-    : awaiter_(other.awaiter_)
-  {
-  }
-
-  /// Move constructor.
-  await_token(await_token&& other) noexcept
-    : awaiter_(std::exchange(other.awaiter_, nullptr))
-  {
-  }
-
-  /// Get the associated executor.
-  executor_type get_executor() const noexcept
-  {
-    return awaiter_->get_executor();
-  }
-
-private:
-  // No assignment allowed.
-  await_token& operator=(const await_token&) = delete;
-
-  template <typename> friend class detail::awaitee_base;
-  template <typename, typename> friend class detail::await_handler_base;
-
-  // Private constructor used by awaitee_base.
-  explicit await_token(detail::awaiter<Executor>* a)
-    : awaiter_(a)
-  {
-  }
-
-  detail::awaiter<Executor>* awaiter_;
-};
-
-/// The return type of a coroutine or asynchronous operation.
-template <typename T, typename Executor = strand<executor>>
-class awaitable
-{
-public:
-  /// The type of the awaited value.
-  typedef T value_type;
-
-  /// The executor type that will be used for the coroutine.
-  typedef Executor executor_type;
-
-  /// Move constructor.
-  awaitable(awaitable&& other) noexcept
-    : awaitee_(std::exchange(other.awaitee_, nullptr))
-  {
-  }
-
-  /// Destructor
-  ~awaitable()
-  {
-    if (awaitee_)
-    {
-      detail::coroutine_handle<
-        detail::awaitee<T, Executor>>::from_promise(
-          *awaitee_).destroy();
-    }
-  }
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-  // Support for co_await keyword.
-  bool await_ready() const noexcept
-  {
-    return awaitee_->ready();
-  }
-
-  // Support for co_await keyword.
-  void await_suspend(detail::coroutine_handle<detail::awaiter<Executor>> h)
-  {
-    awaitee_->attach_caller(h);
-  }
-
-  // Support for co_await keyword.
-  template <class U>
-  void await_suspend(detail::coroutine_handle<detail::awaitee<U, Executor>> h)
-  {
-    awaitee_->attach_caller(h);
-  }
-
-  // Support for co_await keyword.
-  T await_resume()
-  {
-    return awaitee_->get();
-  }
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-private:
-  template <typename, typename> friend class detail::awaitee;
-  template <typename, typename> friend class detail::await_handler_base;
-
-  // Not copy constructible or copy assignable.
-  awaitable(const awaitable&) = delete;
-  awaitable& operator=(const awaitable&) = delete;
-
-  // Construct the awaitable from a coroutine's promise object.
-  explicit awaitable(detail::awaitee<T, Executor>* a) : awaitee_(a) {}
-
-  detail::awaitee<T, Executor>* awaitee_;
-};
-
-/// Spawn a new thread of execution.
-template <typename Executor, typename F, typename CompletionToken,
-    typename = typename enable_if<is_executor<Executor>::value>::type>
-inline auto co_spawn(const Executor& ex, F&& f, CompletionToken&& token)
-{
-  return detail::co_spawn(ex, std::forward<F>(f),
-      std::forward<CompletionToken>(token));
-}
-
-/// Spawn a new thread of execution.
-template <typename ExecutionContext, typename F, typename CompletionToken,
-    typename = typename enable_if<
-      is_convertible<ExecutionContext&, execution_context&>::value>::type>
-inline auto co_spawn(ExecutionContext& ctx, F&& f, CompletionToken&& token)
-{
-  return detail::co_spawn(ctx.get_executor(), std::forward<F>(f),
-      std::forward<CompletionToken>(token));
-}
-
-/// Spawn a new thread of execution.
-template <typename Executor, typename F, typename CompletionToken>
-inline auto co_spawn(const await_token<Executor>& parent,
-    F&& f, CompletionToken&& token)
-{
-  return detail::co_spawn(parent.get_executor(), std::forward<F>(f),
-      std::forward<CompletionToken>(token));
-}
-
-} // namespace experimental
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/experimental/impl/co_spawn.hpp"
-
-#endif // defined(ASIO_HAS_CO_AWAIT) || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_EXPERIMENTAL_CO_SPAWN_HPP
diff --git a/tools/sdk/include/asio/asio/experimental/detached.hpp b/tools/sdk/include/asio/asio/experimental/detached.hpp
deleted file mode 100644
index d484f18fbaf..00000000000
--- a/tools/sdk/include/asio/asio/experimental/detached.hpp
+++ /dev/null
@@ -1,65 +0,0 @@
-//
-// experimental/detached.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXPERIMENTAL_DETACHED_HPP
-#define ASIO_EXPERIMENTAL_DETACHED_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <memory>
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace experimental {
-
-/// Class used to specify that an asynchronous operation is detached.
-/**
-
- * The detached_t class is used to indicate that an asynchronous operation is
- * detached. That is, there is no completion handler waiting for the
- * operation's result. A detached_t object may be passed as a handler to an
- * asynchronous operation, typically using the special value
- * @c asio::experimental::detached. For example:
-
- * @code my_socket.async_send(my_buffer, asio::experimental::detached);
- * @endcode
- */
-class detached_t
-{
-public:
-  /// Constructor. 
-  ASIO_CONSTEXPR detached_t()
-  {
-  }
-};
-
-/// A special value, similar to std::nothrow.
-/**
- * See the documentation for asio::experimental::detached_t for a usage
- * example.
- */
-#if defined(ASIO_HAS_CONSTEXPR) || defined(GENERATING_DOCUMENTATION)
-constexpr detached_t detached;
-#elif defined(ASIO_MSVC)
-__declspec(selectany) detached_t detached;
-#endif
-
-} // namespace experimental
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/experimental/impl/detached.hpp"
-
-#endif // ASIO_EXPERIMENTAL_DETACHED_HPP
diff --git a/tools/sdk/include/asio/asio/experimental/impl/co_spawn.hpp b/tools/sdk/include/asio/asio/experimental/impl/co_spawn.hpp
deleted file mode 100644
index 8263eff96a5..00000000000
--- a/tools/sdk/include/asio/asio/experimental/impl/co_spawn.hpp
+++ /dev/null
@@ -1,876 +0,0 @@
-//
-// experimental/impl/co_spawn.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXPERIMENTAL_IMPL_CO_SPAWN_HPP
-#define ASIO_EXPERIMENTAL_IMPL_CO_SPAWN_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <exception>
-#include <functional>
-#include <memory>
-#include <new>
-#include <tuple>
-#include <utility>
-#include "asio/async_result.hpp"
-#include "asio/detail/thread_context.hpp"
-#include "asio/detail/thread_info_base.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/dispatch.hpp"
-#include "asio/post.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace experimental {
-namespace detail {
-
-// Promise object for coroutine at top of thread-of-execution "stack".
-template <typename Executor>
-class awaiter
-{
-public:
-  struct deleter
-  {
-    void operator()(awaiter* a)
-    {
-      if (a)
-        a->release();
-    }
-  };
-
-  typedef std::unique_ptr<awaiter, deleter> ptr;
-
-  typedef Executor executor_type;
-
-  ~awaiter()
-  {
-    if (has_executor_)
-      static_cast<Executor*>(static_cast<void*>(executor_))->~Executor();
-  }
-
-  void set_executor(const Executor& ex)
-  {
-    new (&executor_) Executor(ex);
-    has_executor_ = true;
-  }
-
-  executor_type get_executor() const noexcept
-  {
-    return *static_cast<const Executor*>(static_cast<const void*>(executor_));
-  }
-
-  awaiter* get_return_object()
-  {
-    return this;
-  }
-
-  auto initial_suspend()
-  {
-    return std::experimental::suspend_always();
-  }
-
-  auto final_suspend()
-  {
-    return std::experimental::suspend_always();
-  }
-
-  void return_void()
-  {
-  }
-
-  awaiter* add_ref()
-  {
-    ++ref_count_;
-    return this;
-  }
-
-  void release()
-  {
-    if (--ref_count_ == 0)
-      coroutine_handle<awaiter>::from_promise(*this).destroy();
-  }
-
-  void unhandled_exception()
-  {
-    pending_exception_ = std::current_exception();
-  }
-
-  void rethrow_unhandled_exception()
-  {
-    if (pending_exception_)
-    {
-      std::exception_ptr ex = std::exchange(pending_exception_, nullptr);
-      std::rethrow_exception(ex);
-    }
-  }
-
-private:
-  std::size_t ref_count_ = 0;
-  std::exception_ptr pending_exception_ = nullptr;
-  alignas(Executor) unsigned char executor_[sizeof(Executor)];
-  bool has_executor_ = false;
-};
-
-// Base promise for coroutines further down the thread-of-execution "stack".
-template <typename Executor>
-class awaitee_base
-{
-public:
-#if !defined(ASIO_DISABLE_AWAITEE_RECYCLING)
-  void* operator new(std::size_t size)
-  {
-    return asio::detail::thread_info_base::allocate(
-        asio::detail::thread_info_base::awaitee_tag(),
-        asio::detail::thread_context::thread_call_stack::top(),
-        size);
-  }
-
-  void operator delete(void* pointer, std::size_t size)
-  {
-    asio::detail::thread_info_base::deallocate(
-        asio::detail::thread_info_base::awaitee_tag(),
-        asio::detail::thread_context::thread_call_stack::top(),
-        pointer, size);
-  }
-#endif // !defined(ASIO_DISABLE_AWAITEE_RECYCLING)
-
-  auto initial_suspend()
-  {
-    return std::experimental::suspend_never();
-  }
-
-  struct final_suspender
-  {
-    awaitee_base* this_;
-
-    bool await_ready() const noexcept
-    {
-      return false;
-    }
-
-    void await_suspend(coroutine_handle<void>)
-    {
-      this_->wake_caller();
-    }
-
-    void await_resume() const noexcept
-    {
-    }
-  };
-
-  auto final_suspend()
-  {
-    return final_suspender{this};
-  }
-
-  void set_except(std::exception_ptr e)
-  {
-    pending_exception_ = e;
-  }
-
-  void unhandled_exception()
-  {
-    set_except(std::current_exception());
-  }
-
-  void rethrow_exception()
-  {
-    if (pending_exception_)
-    {
-      std::exception_ptr ex = std::exchange(pending_exception_, nullptr);
-      std::rethrow_exception(ex);
-    }
-  }
-
-  awaiter<Executor>* top()
-  {
-    return awaiter_;
-  }
-
-  coroutine_handle<void> caller()
-  {
-    return caller_;
-  }
-
-  bool ready() const
-  {
-    return ready_;
-  }
-
-  void wake_caller()
-  {
-    if (caller_)
-      caller_.resume();
-    else
-      ready_ = true;
-  }
-
-  class awaitable_executor
-  {
-  public:
-    explicit awaitable_executor(awaitee_base* a)
-      : this_(a)
-    {
-    }
-
-    bool await_ready() const noexcept
-    {
-      return this_->awaiter_ != nullptr;
-    }
-
-    template <typename U, typename Ex>
-    void await_suspend(coroutine_handle<detail::awaitee<U, Ex>> h) noexcept
-    {
-      this_->resume_on_attach_ = h;
-    }
-
-    Executor await_resume()
-    {
-      return this_->awaiter_->get_executor();
-    }
-
-  private:
-    awaitee_base* this_;
-  };
-
-  awaitable_executor await_transform(this_coro::executor_t) noexcept
-  {
-    return awaitable_executor(this);
-  }
-
-  class awaitable_token
-  {
-  public:
-    explicit awaitable_token(awaitee_base* a)
-      : this_(a)
-    {
-    }
-
-    bool await_ready() const noexcept
-    {
-      return this_->awaiter_ != nullptr;
-    }
-
-    template <typename U, typename Ex>
-    void await_suspend(coroutine_handle<detail::awaitee<U, Ex>> h) noexcept
-    {
-      this_->resume_on_attach_ = h;
-    }
-
-    await_token<Executor> await_resume()
-    {
-      return await_token<Executor>(this_->awaiter_);
-    }
-
-  private:
-    awaitee_base* this_;
-  };
-
-  awaitable_token await_transform(this_coro::token_t) noexcept
-  {
-    return awaitable_token(this);
-  }
-
-  template <typename T>
-  awaitable<T, Executor> await_transform(awaitable<T, Executor>& t) const
-  {
-    return std::move(t);
-  }
-
-  template <typename T>
-  awaitable<T, Executor> await_transform(awaitable<T, Executor>&& t) const
-  {
-    return std::move(t);
-  }
-
-  std::experimental::suspend_always await_transform(
-      std::experimental::suspend_always) const
-  {
-    return std::experimental::suspend_always();
-  }
-
-  void attach_caller(coroutine_handle<awaiter<Executor>> h)
-  {
-    this->caller_ = h;
-    this->attach_callees(&h.promise());
-  }
-
-  template <typename U>
-  void attach_caller(coroutine_handle<awaitee<U, Executor>> h)
-  {
-    this->caller_ = h;
-    if (h.promise().awaiter_)
-      this->attach_callees(h.promise().awaiter_);
-    else
-      h.promise().unattached_callee_ = this;
-  }
-
-  void attach_callees(awaiter<Executor>* a)
-  {
-    for (awaitee_base* curr = this; curr != nullptr;
-        curr = std::exchange(curr->unattached_callee_, nullptr))
-    {
-      curr->awaiter_ = a;
-      if (curr->resume_on_attach_)
-        return std::exchange(curr->resume_on_attach_, nullptr).resume();
-    }
-  }
-
-protected:
-  awaiter<Executor>* awaiter_ = nullptr;
-  coroutine_handle<void> caller_ = nullptr;
-  awaitee_base<Executor>* unattached_callee_ = nullptr;
-  std::exception_ptr pending_exception_ = nullptr;
-  coroutine_handle<void> resume_on_attach_ = nullptr;
-  bool ready_ = false;
-};
-
-// Promise object for coroutines further down the thread-of-execution "stack".
-template <typename T, typename Executor>
-class awaitee
-  : public awaitee_base<Executor>
-{
-public:
-  awaitee()
-  {
-  }
-
-  awaitee(awaitee&& other) noexcept
-    : awaitee_base<Executor>(std::move(other))
-  {
-  }
-
-  ~awaitee()
-  {
-    if (has_result_)
-      static_cast<T*>(static_cast<void*>(result_))->~T();
-  }
-
-  awaitable<T, Executor> get_return_object()
-  {
-    return awaitable<T, Executor>(this);
-  };
-
-  template <typename U>
-  void return_value(U&& u)
-  {
-    new (&result_) T(std::forward<U>(u));
-    has_result_ = true;
-  }
-
-  T get()
-  {
-    this->caller_ = nullptr;
-    this->rethrow_exception();
-    return std::move(*static_cast<T*>(static_cast<void*>(result_)));
-  }
-
-private:
-  alignas(T) unsigned char result_[sizeof(T)];
-  bool has_result_ = false;
-};
-
-// Promise object for coroutines further down the thread-of-execution "stack".
-template <typename Executor>
-class awaitee<void, Executor>
-  : public awaitee_base<Executor>
-{
-public:
-  awaitable<void, Executor> get_return_object()
-  {
-    return awaitable<void, Executor>(this);
-  };
-
-  void return_void()
-  {
-  }
-
-  void get()
-  {
-    this->caller_ = nullptr;
-    this->rethrow_exception();
-  }
-};
-
-template <typename Executor>
-class awaiter_task
-{
-public:
-  typedef Executor executor_type;
-
-  awaiter_task(awaiter<Executor>* a)
-    : awaiter_(a->add_ref())
-  {
-  }
-
-  awaiter_task(awaiter_task&& other) noexcept
-    : awaiter_(std::exchange(other.awaiter_, nullptr))
-  {
-  }
-
-  ~awaiter_task()
-  {
-    if (awaiter_)
-    {
-      // Coroutine "stack unwinding" must be performed through the executor.
-      executor_type ex(awaiter_->get_executor());
-      (post)(ex,
-          [a = std::move(awaiter_)]() mutable
-          {
-            typename awaiter<Executor>::ptr(std::move(a));
-          });
-    }
-  }
-
-  executor_type get_executor() const noexcept
-  {
-    return awaiter_->get_executor();
-  }
-
-protected:
-  typename awaiter<Executor>::ptr awaiter_;
-};
-
-template <typename Executor>
-class co_spawn_handler : public awaiter_task<Executor>
-{
-public:
-  using awaiter_task<Executor>::awaiter_task;
-
-  void operator()()
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    coroutine_handle<awaiter<Executor>>::from_promise(*ptr.get()).resume();
-  }
-};
-
-template <typename Executor, typename T>
-class await_handler_base : public awaiter_task<Executor>
-{
-public:
-  typedef awaitable<T, Executor> awaitable_type;
-
-  await_handler_base(await_token<Executor> token)
-    : awaiter_task<Executor>(token.awaiter_),
-      awaitee_(nullptr)
-  {
-  }
-
-  await_handler_base(await_handler_base&& other) noexcept
-    : awaiter_task<Executor>(std::move(other)),
-      awaitee_(std::exchange(other.awaitee_, nullptr))
-  {
-  }
-
-  void attach_awaitee(const awaitable<T, Executor>& a)
-  {
-    awaitee_ = a.awaitee_;
-  }
-
-protected:
-  awaitee<T, Executor>* awaitee_;
-};
-
-template <typename, typename...> class await_handler;
-
-template <typename Executor>
-class await_handler<Executor, void>
-  : public await_handler_base<Executor, void>
-{
-public:
-  using await_handler_base<Executor, void>::await_handler_base;
-
-  void operator()()
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    this->awaitee_->return_void();
-    this->awaitee_->wake_caller();
-    ptr->rethrow_unhandled_exception();
-  }
-};
-
-template <typename Executor>
-class await_handler<Executor, asio::error_code>
-  : public await_handler_base<Executor, void>
-{
-public:
-  typedef void return_type;
-
-  using await_handler_base<Executor, void>::await_handler_base;
-
-  void operator()(const asio::error_code& ec)
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    if (ec)
-    {
-      this->awaitee_->set_except(
-          std::make_exception_ptr(asio::system_error(ec)));
-    }
-    else
-      this->awaitee_->return_void();
-    this->awaitee_->wake_caller();
-    ptr->rethrow_unhandled_exception();
-  }
-};
-
-template <typename Executor>
-class await_handler<Executor, std::exception_ptr>
-  : public await_handler_base<Executor, void>
-{
-public:
-  using await_handler_base<Executor, void>::await_handler_base;
-
-  void operator()(std::exception_ptr ex)
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    if (ex)
-      this->awaitee_->set_except(ex);
-    else
-      this->awaitee_->return_void();
-    this->awaitee_->wake_caller();
-    ptr->rethrow_unhandled_exception();
-  }
-};
-
-template <typename Executor, typename T>
-class await_handler<Executor, T>
-  : public await_handler_base<Executor, T>
-{
-public:
-  using await_handler_base<Executor, T>::await_handler_base;
-
-  template <typename Arg>
-  void operator()(Arg&& arg)
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    this->awaitee_->return_value(std::forward<Arg>(arg));
-    this->awaitee_->wake_caller();
-    ptr->rethrow_unhandled_exception();
-  }
-};
-
-template <typename Executor, typename T>
-class await_handler<Executor, asio::error_code, T>
-  : public await_handler_base<Executor, T>
-{
-public:
-  using await_handler_base<Executor, T>::await_handler_base;
-
-  template <typename Arg>
-  void operator()(const asio::error_code& ec, Arg&& arg)
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    if (ec)
-    {
-      this->awaitee_->set_except(
-          std::make_exception_ptr(asio::system_error(ec)));
-    }
-    else
-      this->awaitee_->return_value(std::forward<Arg>(arg));
-    this->awaitee_->wake_caller();
-    ptr->rethrow_unhandled_exception();
-  }
-};
-
-template <typename Executor, typename T>
-class await_handler<Executor, std::exception_ptr, T>
-  : public await_handler_base<Executor, T>
-{
-public:
-  using await_handler_base<Executor, T>::await_handler_base;
-
-  template <typename Arg>
-  void operator()(std::exception_ptr ex, Arg&& arg)
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    if (ex)
-      this->awaitee_->set_except(ex);
-    else
-      this->awaitee_->return_value(std::forward<Arg>(arg));
-    this->awaitee_->wake_caller();
-    ptr->rethrow_unhandled_exception();
-  }
-};
-
-template <typename Executor, typename... Ts>
-class await_handler
-  : public await_handler_base<Executor, std::tuple<Ts...>>
-{
-public:
-  using await_handler_base<Executor, std::tuple<Ts...>>::await_handler_base;
-
-  template <typename... Args>
-  void operator()(Args&&... args)
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    this->awaitee_->return_value(
-        std::forward_as_tuple(std::forward<Args>(args)...));
-    this->awaitee_->wake_caller();
-    ptr->rethrow_unhandled_exception();
-  }
-};
-
-template <typename Executor, typename... Ts>
-class await_handler<Executor, asio::error_code, Ts...>
-  : public await_handler_base<Executor, std::tuple<Ts...>>
-{
-public:
-  using await_handler_base<Executor, std::tuple<Ts...>>::await_handler_base;
-
-  template <typename... Args>
-  void operator()(const asio::error_code& ec, Args&&... args)
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    if (ec)
-    {
-      this->awaitee_->set_except(
-          std::make_exception_ptr(asio::system_error(ec)));
-    }
-    else
-    {
-      this->awaitee_->return_value(
-          std::forward_as_tuple(std::forward<Args>(args)...));
-    }
-    this->awaitee_->wake_caller();
-    ptr->rethrow_unhandled_exception();
-  }
-};
-
-template <typename Executor, typename... Ts>
-class await_handler<Executor, std::exception_ptr, Ts...>
-  : public await_handler_base<Executor, std::tuple<Ts...>>
-{
-public:
-  using await_handler_base<Executor, std::tuple<Ts...>>::await_handler_base;
-
-  template <typename... Args>
-  void operator()(std::exception_ptr ex, Args&&... args)
-  {
-    typename awaiter<Executor>::ptr ptr(std::move(this->awaiter_));
-    if (ex)
-      this->awaitee_->set_except(ex);
-    else
-    {
-      this->awaitee_->return_value(
-          std::forward_as_tuple(std::forward<Args>(args)...));
-    }
-    this->awaitee_->wake_caller();
-    ptr->rethrow_unhandled_exception();
-  }
-};
-
-template <typename T>
-struct awaitable_signature;
-
-template <typename T, typename Executor>
-struct awaitable_signature<awaitable<T, Executor>>
-{
-  typedef void type(std::exception_ptr, T);
-};
-
-template <typename Executor>
-struct awaitable_signature<awaitable<void, Executor>>
-{
-  typedef void type(std::exception_ptr);
-};
-
-template <typename T, typename Executor, typename F, typename Handler>
-awaiter<Executor>* co_spawn_entry_point(awaitable<T, Executor>*,
-    executor_work_guard<Executor> work_guard, F f, Handler handler)
-{
-  bool done = false;
-
-  try
-  {
-    T t = co_await f();
-
-    done = true;
-
-    (dispatch)(work_guard.get_executor(),
-        [handler = std::move(handler), t = std::move(t)]() mutable
-        {
-          handler(std::exception_ptr(), std::move(t));
-        });
-  }
-  catch (...)
-  {
-    if (done)
-      throw;
-
-    (dispatch)(work_guard.get_executor(),
-        [handler = std::move(handler), e = std::current_exception()]() mutable
-        {
-          handler(e, T());
-        });
-  }
-}
-
-template <typename Executor, typename F, typename Handler>
-awaiter<Executor>* co_spawn_entry_point(awaitable<void, Executor>*,
-    executor_work_guard<Executor> work_guard, F f, Handler handler)
-{
-  std::exception_ptr e = nullptr;
-
-  try
-  {
-    co_await f();
-  }
-  catch (...)
-  {
-    e = std::current_exception();
-  }
-
-  (dispatch)(work_guard.get_executor(),
-      [handler = std::move(handler), e]() mutable
-      {
-        handler(e);
-      });
-}
-
-template <typename Executor, typename F, typename CompletionToken>
-auto co_spawn(const Executor& ex, F&& f, CompletionToken&& token)
-{
-  typedef typename result_of<F()>::type awaitable_type;
-  typedef typename awaitable_type::executor_type executor_type;
-  typedef typename awaitable_signature<awaitable_type>::type signature_type;
-
-  async_completion<CompletionToken, signature_type> completion(token);
-
-  executor_type ex2(ex);
-  auto work_guard = make_work_guard(completion.completion_handler, ex2);
-
-  auto* a = (co_spawn_entry_point)(
-      static_cast<awaitable_type*>(nullptr), std::move(work_guard),
-      std::forward<F>(f), std::move(completion.completion_handler));
-
-  a->set_executor(ex2);
-  (post)(co_spawn_handler<executor_type>(a));
-
-  return completion.result.get();
-}
-
-#if defined(_MSC_VER)
-# pragma warning(push)
-# pragma warning(disable:4033)
-#endif // defined(_MSC_VER)
-
-#if defined(_MSC_VER)
-template <typename T> T dummy_return()
-{
-  return std::move(*static_cast<T*>(nullptr));
-}
-
-template <>
-inline void dummy_return()
-{
-}
-#endif // defined(_MSC_VER)
-
-template <typename Awaitable>
-inline Awaitable make_dummy_awaitable()
-{
-  for (;;) co_await std::experimental::suspend_always();
-#if defined(_MSC_VER)
-  co_return dummy_return<typename Awaitable::value_type>();
-#endif // defined(_MSC_VER)
-}
-
-#if defined(_MSC_VER)
-# pragma warning(pop)
-#endif // defined(_MSC_VER)
-
-} // namespace detail
-} // namespace experimental
-
-template <typename Executor, typename R, typename... Args>
-class async_result<experimental::await_token<Executor>, R(Args...)>
-{
-public:
-  typedef experimental::detail::await_handler<
-    Executor, typename decay<Args>::type...> completion_handler_type;
-
-  typedef typename experimental::detail::await_handler<
-    Executor, Args...>::awaitable_type return_type;
-
-  async_result(completion_handler_type& h)
-    : awaitable_(experimental::detail::make_dummy_awaitable<return_type>())
-  {
-    h.attach_awaitee(awaitable_);
-  }
-
-  return_type get()
-  {
-    return std::move(awaitable_);
-  }
-
-private:
-  return_type awaitable_;
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-template <typename Executor, typename R, typename... Args>
-struct handler_type<experimental::await_token<Executor>, R(Args...)>
-{
-  typedef experimental::detail::await_handler<
-    Executor, typename decay<Args>::type...> type;
-};
-
-template <typename Executor, typename... Args>
-class async_result<experimental::detail::await_handler<Executor, Args...>>
-{
-public:
-  typedef typename experimental::detail::await_handler<
-    Executor, Args...>::awaitable_type type;
-
-  async_result(experimental::detail::await_handler<Executor, Args...>& h)
-    : awaitable_(experimental::detail::make_dummy_awaitable<type>())
-  {
-    h.attach_awaitee(awaitable_);
-  }
-
-  type get()
-  {
-    return std::move(awaitable_);
-  }
-
-private:
-  type awaitable_;
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-} // namespace asio
-
-namespace std { namespace experimental {
-
-template <typename Executor, typename... Args>
-struct coroutine_traits<
-  asio::experimental::detail::awaiter<Executor>*, Args...>
-{
-  typedef asio::experimental::detail::awaiter<Executor> promise_type;
-};
-
-template <typename T, typename Executor, typename... Args>
-struct coroutine_traits<
-  asio::experimental::awaitable<T, Executor>, Args...>
-{
-  typedef asio::experimental::detail::awaitee<T, Executor> promise_type;
-};
-
-}} // namespace std::experimental
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_EXPERIMENTAL_IMPL_CO_SPAWN_HPP
diff --git a/tools/sdk/include/asio/asio/experimental/impl/detached.hpp b/tools/sdk/include/asio/asio/experimental/impl/detached.hpp
deleted file mode 100644
index 6ce88872e22..00000000000
--- a/tools/sdk/include/asio/asio/experimental/impl/detached.hpp
+++ /dev/null
@@ -1,91 +0,0 @@
-//
-// experimental/impl/detached.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXPERIMENTAL_IMPL_DETACHED_HPP
-#define ASIO_EXPERIMENTAL_IMPL_DETACHED_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/async_result.hpp"
-#include "asio/detail/variadic_templates.hpp"
-#include "asio/handler_type.hpp"
-#include "asio/system_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace experimental {
-namespace detail {
-
-  // Class to adapt a detached_t as a completion handler.
-  class detached_handler
-  {
-  public:
-    detached_handler(detached_t)
-    {
-    }
-
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-    template <typename... Args>
-    void operator()(Args...)
-    {
-    }
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-    void operator()()
-    {
-    }
-
-#define ASIO_PRIVATE_DETACHED_DEF(n) \
-    template <ASIO_VARIADIC_TPARAMS(n)> \
-    void operator()(ASIO_VARIADIC_BYVAL_PARAMS(n)) \
-    { \
-    } \
-    /**/
-    ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_DETACHED_DEF)
-#undef ASIO_PRIVATE_DETACHED_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-  };
-
-} // namespace detail
-} // namespace experimental
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename Signature>
-struct async_result<experimental::detached_t, Signature>
-{
-  typedef asio::experimental::detail::detached_handler
-    completion_handler_type;
-
-  typedef void return_type;
-
-  explicit async_result(completion_handler_type&)
-  {
-  }
-
-  void get()
-  {
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_EXPERIMENTAL_IMPL_DETACHED_HPP
diff --git a/tools/sdk/include/asio/asio/experimental/impl/redirect_error.hpp b/tools/sdk/include/asio/asio/experimental/impl/redirect_error.hpp
deleted file mode 100644
index d3b97facc91..00000000000
--- a/tools/sdk/include/asio/asio/experimental/impl/redirect_error.hpp
+++ /dev/null
@@ -1,294 +0,0 @@
-//
-// experimental/impl/redirect_error.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXPERIMENTAL_IMPL_REDIRECT_ERROR_HPP
-#define ASIO_EXPERIMENTAL_IMPL_REDIRECT_ERROR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/async_result.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/detail/variadic_templates.hpp"
-#include "asio/handler_type.hpp"
-#include "asio/system_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace experimental {
-namespace detail {
-
-// Class to adapt a redirect_error_t as a completion handler.
-template <typename Handler>
-class redirect_error_handler
-{
-public:
-  template <typename CompletionToken>
-  redirect_error_handler(redirect_error_t<CompletionToken> e)
-    : ec_(e.ec_),
-      handler_(ASIO_MOVE_CAST(CompletionToken)(e.token_))
-  {
-  }
-
-  void operator()()
-  {
-    handler_();
-  }
-
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  template <typename Arg, typename... Args>
-  typename enable_if<
-    !is_same<typename decay<Arg>::type, asio::error_code>::value
-  >::type
-  operator()(ASIO_MOVE_ARG(Arg) arg, ASIO_MOVE_ARG(Args)... args)
-  {
-    handler_(ASIO_MOVE_CAST(Arg)(arg),
-        ASIO_MOVE_CAST(Args)(args)...);
-  }
-
-  template <typename... Args>
-  void operator()(const asio::error_code& ec,
-      ASIO_MOVE_ARG(Args)... args)
-  {
-    ec_ = ec;
-    handler_(ASIO_MOVE_CAST(Args)(args)...);
-  }
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  template <typename Arg>
-  typename enable_if<
-    !is_same<typename decay<Arg>::type, asio::error_code>::value
-  >::type
-  operator()(ASIO_MOVE_ARG(Arg) arg)
-  {
-    handler_(ASIO_MOVE_CAST(Arg)(arg));
-  }
-
-  void operator()(const asio::error_code& ec)
-  {
-    ec_ = ec;
-    handler_();
-  }
-
-#define ASIO_PRIVATE_REDIRECT_ERROR_DEF(n) \
-  template <typename Arg, ASIO_VARIADIC_TPARAMS(n)> \
-  typename enable_if< \
-    !is_same<typename decay<Arg>::type, asio::error_code>::value \
-  >::type \
-  operator()(ASIO_MOVE_ARG(Arg) arg, ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  { \
-    handler_(ASIO_MOVE_CAST(Arg)(arg), \
-        ASIO_VARIADIC_MOVE_ARGS(n)); \
-  } \
-  \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  void operator()(const asio::error_code& ec, \
-      ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  { \
-    ec_ = ec; \
-    handler_(ASIO_VARIADIC_MOVE_ARGS(n)); \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_REDIRECT_ERROR_DEF)
-#undef ASIO_PRIVATE_REDIRECT_ERROR_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-//private:
-  asio::error_code& ec_;
-  Handler handler_;
-};
-
-template <typename Handler>
-inline void* asio_handler_allocate(std::size_t size,
-    redirect_error_handler<Handler>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Handler>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    redirect_error_handler<Handler>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Handler>
-inline bool asio_handler_is_continuation(
-    redirect_error_handler<Handler>* this_handler)
-{
-  return asio_handler_cont_helpers::is_continuation(
-        this_handler->handler_);
-}
-
-template <typename Function, typename Handler>
-inline void asio_handler_invoke(Function& function,
-    redirect_error_handler<Handler>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Function, typename Handler>
-inline void asio_handler_invoke(const Function& function,
-    redirect_error_handler<Handler>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Signature>
-struct redirect_error_signature
-{
-  typedef Signature type;
-};
-
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-template <typename R, typename... Args>
-struct redirect_error_signature<R(asio::error_code, Args...)>
-{
-  typedef R type(Args...);
-};
-
-template <typename R, typename... Args>
-struct redirect_error_signature<R(const asio::error_code&, Args...)>
-{
-  typedef R type(Args...);
-};
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-template <typename R>
-struct redirect_error_signature<R(asio::error_code)>
-{
-  typedef R type();
-};
-
-template <typename R>
-struct redirect_error_signature<R(const asio::error_code&)>
-{
-  typedef R type();
-};
-
-#define ASIO_PRIVATE_REDIRECT_ERROR_DEF(n) \
-  template <typename R, ASIO_VARIADIC_TPARAMS(n)> \
-  struct redirect_error_signature< \
-      R(asio::error_code, ASIO_VARIADIC_TARGS(n))> \
-  { \
-    typedef R type(ASIO_VARIADIC_TARGS(n)); \
-  }; \
-  \
-  template <typename R, ASIO_VARIADIC_TPARAMS(n)> \
-  struct redirect_error_signature< \
-      R(const asio::error_code&, ASIO_VARIADIC_TARGS(n))> \
-  { \
-    typedef R type(ASIO_VARIADIC_TARGS(n)); \
-  }; \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_REDIRECT_ERROR_DEF)
-#undef ASIO_PRIVATE_REDIRECT_ERROR_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-} // namespace detail
-} // namespace experimental
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename CompletionToken, typename Signature>
-struct async_result<experimental::redirect_error_t<CompletionToken>, Signature>
-  : async_result<CompletionToken,
-      typename experimental::detail::redirect_error_signature<Signature>::type>
-{
-  typedef experimental::detail::redirect_error_handler<
-    typename async_result<CompletionToken,
-      typename experimental::detail::redirect_error_signature<Signature>::type>
-        ::completion_handler_type> completion_handler_type;
-
-  explicit async_result(completion_handler_type& h)
-    : async_result<CompletionToken,
-        typename experimental::detail::redirect_error_signature<
-          Signature>::type>(h.handler_)
-  {
-  }
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-template <typename CompletionToken, typename Signature>
-struct handler_type<experimental::redirect_error_t<CompletionToken>, Signature>
-{
-  typedef experimental::detail::redirect_error_handler<
-    typename async_result<CompletionToken,
-      typename experimental::detail::redirect_error_signature<Signature>::type>
-        ::completion_handler_type> type;
-};
-
-template <typename Handler>
-struct async_result<experimental::detail::redirect_error_handler<Handler> >
-  : async_result<Handler>
-{
-  explicit async_result(
-      experimental::detail::redirect_error_handler<Handler>& h)
-    : async_result<Handler>(h.handler_)
-  {
-  }
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Handler, typename Executor>
-struct associated_executor<
-    experimental::detail::redirect_error_handler<Handler>, Executor>
-{
-  typedef typename associated_executor<Handler, Executor>::type type;
-
-  static type get(
-      const experimental::detail::redirect_error_handler<Handler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<Handler, Executor>::get(h.handler_, ex);
-  }
-};
-
-template <typename Handler, typename Allocator>
-struct associated_allocator<
-    experimental::detail::redirect_error_handler<Handler>, Allocator>
-{
-  typedef typename associated_allocator<Handler, Allocator>::type type;
-
-  static type get(
-      const experimental::detail::redirect_error_handler<Handler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<Handler, Allocator>::get(h.handler_, a);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_EXPERIMENTAL_IMPL_REDIRECT_ERROR_HPP
diff --git a/tools/sdk/include/asio/asio/experimental/redirect_error.hpp b/tools/sdk/include/asio/asio/experimental/redirect_error.hpp
deleted file mode 100644
index 30e81cf5a28..00000000000
--- a/tools/sdk/include/asio/asio/experimental/redirect_error.hpp
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// experimental/redirect_error.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_EXPERIMENTAL_REDIRECT_ERROR_HPP
-#define ASIO_EXPERIMENTAL_REDIRECT_ERROR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error_code.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace experimental {
-
-/// Completion token type used to specify that an error produced by an
-/// asynchronous operation is captured to an error_code variable.
-/**
- * The redirect_error_t class is used to indicate that any error_code produced
- * by an asynchronous operation is captured to a specified variable.
- */
-template <typename CompletionToken>
-class redirect_error_t
-{
-public:
-  /// Constructor. 
-  template <typename T>
-  redirect_error_t(ASIO_MOVE_ARG(T) completion_token,
-      asio::error_code& ec)
-    : token_(ASIO_MOVE_CAST(T)(completion_token)),
-      ec_(ec)
-  {
-  }
-
-//private:
-  CompletionToken token_;
-  asio::error_code& ec_;
-};
-
-/// Create a completion token to capture error_code values to a variable.
-template <typename CompletionToken>
-inline redirect_error_t<typename decay<CompletionToken>::type> redirect_error(
-    CompletionToken&& completion_token, asio::error_code& ec)
-{
-  return redirect_error_t<typename decay<CompletionToken>::type>(
-      ASIO_MOVE_CAST(CompletionToken)(completion_token), ec);
-}
-
-} // namespace experimental
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/experimental/impl/redirect_error.hpp"
-
-#endif // ASIO_EXPERIMENTAL_REDIRECT_ERROR_HPP
diff --git a/tools/sdk/include/asio/asio/generic/basic_endpoint.hpp b/tools/sdk/include/asio/asio/generic/basic_endpoint.hpp
deleted file mode 100644
index 73aa151d627..00000000000
--- a/tools/sdk/include/asio/asio/generic/basic_endpoint.hpp
+++ /dev/null
@@ -1,193 +0,0 @@
-//
-// generic/basic_endpoint.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_GENERIC_BASIC_ENDPOINT_HPP
-#define ASIO_GENERIC_BASIC_ENDPOINT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/generic/detail/endpoint.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace generic {
-
-/// Describes an endpoint for any socket type.
-/**
- * The asio::generic::basic_endpoint class template describes an endpoint
- * that may be associated with any socket type.
- *
- * @note The socket types sockaddr type must be able to fit into a
- * @c sockaddr_storage structure.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * Endpoint.
- */
-template <typename Protocol>
-class basic_endpoint
-{
-public:
-  /// The protocol type associated with the endpoint.
-  typedef Protocol protocol_type;
-
-  /// The type of the endpoint structure. This type is dependent on the
-  /// underlying implementation of the socket layer.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined data_type;
-#else
-  typedef asio::detail::socket_addr_type data_type;
-#endif
-
-  /// Default constructor.
-  basic_endpoint()
-  {
-  }
-
-  /// Construct an endpoint from the specified socket address.
-  basic_endpoint(const void* socket_address,
-      std::size_t socket_address_size, int socket_protocol = 0)
-    : impl_(socket_address, socket_address_size, socket_protocol)
-  {
-  }
-
-  /// Construct an endpoint from the specific endpoint type.
-  template <typename Endpoint>
-  basic_endpoint(const Endpoint& endpoint)
-    : impl_(endpoint.data(), endpoint.size(), endpoint.protocol().protocol())
-  {
-  }
-
-  /// Copy constructor.
-  basic_endpoint(const basic_endpoint& other)
-    : impl_(other.impl_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  basic_endpoint(basic_endpoint&& other)
-    : impl_(other.impl_)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assign from another endpoint.
-  basic_endpoint& operator=(const basic_endpoint& other)
-  {
-    impl_ = other.impl_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move-assign from another endpoint.
-  basic_endpoint& operator=(basic_endpoint&& other)
-  {
-    impl_ = other.impl_;
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// The protocol associated with the endpoint.
-  protocol_type protocol() const
-  {
-    return protocol_type(impl_.family(), impl_.protocol());
-  }
-
-  /// Get the underlying endpoint in the native type.
-  data_type* data()
-  {
-    return impl_.data();
-  }
-
-  /// Get the underlying endpoint in the native type.
-  const data_type* data() const
-  {
-    return impl_.data();
-  }
-
-  /// Get the underlying size of the endpoint in the native type.
-  std::size_t size() const
-  {
-    return impl_.size();
-  }
-
-  /// Set the underlying size of the endpoint in the native type.
-  void resize(std::size_t new_size)
-  {
-    impl_.resize(new_size);
-  }
-
-  /// Get the capacity of the endpoint in the native type.
-  std::size_t capacity() const
-  {
-    return impl_.capacity();
-  }
-
-  /// Compare two endpoints for equality.
-  friend bool operator==(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return e1.impl_ == e2.impl_;
-  }
-
-  /// Compare two endpoints for inequality.
-  friend bool operator!=(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return !(e1.impl_ == e2.impl_);
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator<(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return e1.impl_ < e2.impl_;
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator>(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return e2.impl_ < e1.impl_;
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator<=(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return !(e2 < e1);
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator>=(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return !(e1 < e2);
-  }
-
-private:
-  // The underlying generic endpoint.
-  asio::generic::detail::endpoint impl_;
-};
-
-} // namespace generic
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_GENERIC_BASIC_ENDPOINT_HPP
diff --git a/tools/sdk/include/asio/asio/generic/datagram_protocol.hpp b/tools/sdk/include/asio/asio/generic/datagram_protocol.hpp
deleted file mode 100644
index 8678ad85bcc..00000000000
--- a/tools/sdk/include/asio/asio/generic/datagram_protocol.hpp
+++ /dev/null
@@ -1,123 +0,0 @@
-//
-// generic/datagram_protocol.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_GENERIC_DATAGRAM_PROTOCOL_HPP
-#define ASIO_GENERIC_DATAGRAM_PROTOCOL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <typeinfo>
-#include "asio/basic_datagram_socket.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/throw_exception.hpp"
-#include "asio/generic/basic_endpoint.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace generic {
-
-/// Encapsulates the flags needed for a generic datagram-oriented socket.
-/**
- * The asio::generic::datagram_protocol class contains flags necessary
- * for datagram-oriented sockets of any address family and protocol.
- *
- * @par Examples
- * Constructing using a native address family and socket protocol:
- * @code datagram_protocol p(AF_INET, IPPROTO_UDP); @endcode
- * Constructing from a specific protocol type:
- * @code datagram_protocol p(asio::ip::udp::v4()); @endcode
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Protocol.
- */
-class datagram_protocol
-{
-public:
-  /// Construct a protocol object for a specific address family and protocol.
-  datagram_protocol(int address_family, int socket_protocol)
-    : family_(address_family),
-      protocol_(socket_protocol)
-  {
-  }
-
-  /// Construct a generic protocol object from a specific protocol.
-  /**
-   * @throws @c bad_cast Thrown if the source protocol is not datagram-oriented.
-   */
-  template <typename Protocol>
-  datagram_protocol(const Protocol& source_protocol)
-    : family_(source_protocol.family()),
-      protocol_(source_protocol.protocol())
-  {
-    if (source_protocol.type() != type())
-    {
-      std::bad_cast ex;
-      asio::detail::throw_exception(ex);
-    }
-  }
-
-  /// Obtain an identifier for the type of the protocol.
-  int type() const
-  {
-    return ASIO_OS_DEF(SOCK_DGRAM);
-  }
-
-  /// Obtain an identifier for the protocol.
-  int protocol() const
-  {
-    return protocol_;
-  }
-
-  /// Obtain an identifier for the protocol family.
-  int family() const
-  {
-    return family_;
-  }
-
-  /// Compare two protocols for equality.
-  friend bool operator==(const datagram_protocol& p1,
-      const datagram_protocol& p2)
-  {
-    return p1.family_ == p2.family_ && p1.protocol_ == p2.protocol_;
-  }
-
-  /// Compare two protocols for inequality.
-  friend bool operator!=(const datagram_protocol& p1,
-      const datagram_protocol& p2)
-  {
-    return !(p1 == p2);
-  }
-
-  /// The type of an endpoint.
-  typedef basic_endpoint<datagram_protocol> endpoint;
-
-  /// The generic socket type.
-  typedef basic_datagram_socket<datagram_protocol> socket;
-
-private:
-  int family_;
-  int protocol_;
-};
-
-} // namespace generic
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_GENERIC_DATAGRAM_PROTOCOL_HPP
diff --git a/tools/sdk/include/asio/asio/generic/detail/endpoint.hpp b/tools/sdk/include/asio/asio/generic/detail/endpoint.hpp
deleted file mode 100644
index 190beb14c64..00000000000
--- a/tools/sdk/include/asio/asio/generic/detail/endpoint.hpp
+++ /dev/null
@@ -1,133 +0,0 @@
-//
-// generic/detail/endpoint.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_GENERIC_DETAIL_ENDPOINT_HPP
-#define ASIO_GENERIC_DETAIL_ENDPOINT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <cstddef>
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace generic {
-namespace detail {
-
-// Helper class for implementing a generic socket endpoint.
-class endpoint
-{
-public:
-  // Default constructor.
-  ASIO_DECL endpoint();
-
-  // Construct an endpoint from the specified raw bytes.
-  ASIO_DECL endpoint(const void* sock_addr,
-      std::size_t sock_addr_size, int sock_protocol);
-
-  // Copy constructor.
-  endpoint(const endpoint& other)
-    : data_(other.data_),
-      size_(other.size_),
-      protocol_(other.protocol_)
-  {
-  }
-
-  // Assign from another endpoint.
-  endpoint& operator=(const endpoint& other)
-  {
-    data_ = other.data_;
-    size_ = other.size_;
-    protocol_ = other.protocol_;
-    return *this;
-  }
-
-  // Get the address family associated with the endpoint.
-  int family() const
-  {
-    return data_.base.sa_family;
-  }
-
-  // Get the socket protocol associated with the endpoint.
-  int protocol() const
-  {
-    return protocol_;
-  }
-
-  // Get the underlying endpoint in the native type.
-  asio::detail::socket_addr_type* data()
-  {
-    return &data_.base;
-  }
-
-  // Get the underlying endpoint in the native type.
-  const asio::detail::socket_addr_type* data() const
-  {
-    return &data_.base;
-  }
-
-  // Get the underlying size of the endpoint in the native type.
-  std::size_t size() const
-  {
-    return size_;
-  }
-
-  // Set the underlying size of the endpoint in the native type.
-  ASIO_DECL void resize(std::size_t size);
-
-  // Get the capacity of the endpoint in the native type.
-  std::size_t capacity() const
-  {
-    return sizeof(asio::detail::sockaddr_storage_type);
-  }
-
-  // Compare two endpoints for equality.
-  ASIO_DECL friend bool operator==(
-      const endpoint& e1, const endpoint& e2);
-
-  // Compare endpoints for ordering.
-  ASIO_DECL friend bool operator<(
-      const endpoint& e1, const endpoint& e2);
-
-private:
-  // The underlying socket address.
-  union data_union
-  {
-    asio::detail::socket_addr_type base;
-    asio::detail::sockaddr_storage_type generic;
-  } data_;
-
-  // The length of the socket address stored in the endpoint.
-  std::size_t size_;
-
-  // The socket protocol associated with the endpoint.
-  int protocol_;
-
-  // Initialise with a specified memory.
-  ASIO_DECL void init(const void* sock_addr,
-      std::size_t sock_addr_size, int sock_protocol);
-};
-
-} // namespace detail
-} // namespace generic
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/generic/detail/impl/endpoint.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_GENERIC_DETAIL_ENDPOINT_HPP
diff --git a/tools/sdk/include/asio/asio/generic/raw_protocol.hpp b/tools/sdk/include/asio/asio/generic/raw_protocol.hpp
deleted file mode 100644
index b83dca6e32c..00000000000
--- a/tools/sdk/include/asio/asio/generic/raw_protocol.hpp
+++ /dev/null
@@ -1,121 +0,0 @@
-//
-// generic/raw_protocol.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_GENERIC_RAW_PROTOCOL_HPP
-#define ASIO_GENERIC_RAW_PROTOCOL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <typeinfo>
-#include "asio/basic_raw_socket.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/throw_exception.hpp"
-#include "asio/generic/basic_endpoint.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace generic {
-
-/// Encapsulates the flags needed for a generic raw socket.
-/**
- * The asio::generic::raw_protocol class contains flags necessary for
- * raw sockets of any address family and protocol.
- *
- * @par Examples
- * Constructing using a native address family and socket protocol:
- * @code raw_protocol p(AF_INET, IPPROTO_ICMP); @endcode
- * Constructing from a specific protocol type:
- * @code raw_protocol p(asio::ip::icmp::v4()); @endcode
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Protocol.
- */
-class raw_protocol
-{
-public:
-  /// Construct a protocol object for a specific address family and protocol.
-  raw_protocol(int address_family, int socket_protocol)
-    : family_(address_family),
-      protocol_(socket_protocol)
-  {
-  }
-
-  /// Construct a generic protocol object from a specific protocol.
-  /**
-   * @throws @c bad_cast Thrown if the source protocol is not raw-oriented.
-   */
-  template <typename Protocol>
-  raw_protocol(const Protocol& source_protocol)
-    : family_(source_protocol.family()),
-      protocol_(source_protocol.protocol())
-  {
-    if (source_protocol.type() != type())
-    {
-      std::bad_cast ex;
-      asio::detail::throw_exception(ex);
-    }
-  }
-
-  /// Obtain an identifier for the type of the protocol.
-  int type() const
-  {
-    return ASIO_OS_DEF(SOCK_RAW);
-  }
-
-  /// Obtain an identifier for the protocol.
-  int protocol() const
-  {
-    return protocol_;
-  }
-
-  /// Obtain an identifier for the protocol family.
-  int family() const
-  {
-    return family_;
-  }
-
-  /// Compare two protocols for equality.
-  friend bool operator==(const raw_protocol& p1, const raw_protocol& p2)
-  {
-    return p1.family_ == p2.family_ && p1.protocol_ == p2.protocol_;
-  }
-
-  /// Compare two protocols for inequality.
-  friend bool operator!=(const raw_protocol& p1, const raw_protocol& p2)
-  {
-    return !(p1 == p2);
-  }
-
-  /// The type of an endpoint.
-  typedef basic_endpoint<raw_protocol> endpoint;
-
-  /// The generic socket type.
-  typedef basic_raw_socket<raw_protocol> socket;
-
-private:
-  int family_;
-  int protocol_;
-};
-
-} // namespace generic
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_GENERIC_RAW_PROTOCOL_HPP
diff --git a/tools/sdk/include/asio/asio/generic/seq_packet_protocol.hpp b/tools/sdk/include/asio/asio/generic/seq_packet_protocol.hpp
deleted file mode 100644
index f92a4c8f89f..00000000000
--- a/tools/sdk/include/asio/asio/generic/seq_packet_protocol.hpp
+++ /dev/null
@@ -1,122 +0,0 @@
-//
-// generic/seq_packet_protocol.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_GENERIC_SEQ_PACKET_PROTOCOL_HPP
-#define ASIO_GENERIC_SEQ_PACKET_PROTOCOL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <typeinfo>
-#include "asio/basic_seq_packet_socket.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/throw_exception.hpp"
-#include "asio/generic/basic_endpoint.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace generic {
-
-/// Encapsulates the flags needed for a generic sequenced packet socket.
-/**
- * The asio::generic::seq_packet_protocol class contains flags necessary
- * for seq_packet-oriented sockets of any address family and protocol.
- *
- * @par Examples
- * Constructing using a native address family and socket protocol:
- * @code seq_packet_protocol p(AF_INET, IPPROTO_SCTP); @endcode
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Protocol.
- */
-class seq_packet_protocol
-{
-public:
-  /// Construct a protocol object for a specific address family and protocol.
-  seq_packet_protocol(int address_family, int socket_protocol)
-    : family_(address_family),
-      protocol_(socket_protocol)
-  {
-  }
-
-  /// Construct a generic protocol object from a specific protocol.
-  /**
-   * @throws @c bad_cast Thrown if the source protocol is not based around
-   * sequenced packets.
-   */
-  template <typename Protocol>
-  seq_packet_protocol(const Protocol& source_protocol)
-    : family_(source_protocol.family()),
-      protocol_(source_protocol.protocol())
-  {
-    if (source_protocol.type() != type())
-    {
-      std::bad_cast ex;
-      asio::detail::throw_exception(ex);
-    }
-  }
-
-  /// Obtain an identifier for the type of the protocol.
-  int type() const
-  {
-    return ASIO_OS_DEF(SOCK_SEQPACKET);
-  }
-
-  /// Obtain an identifier for the protocol.
-  int protocol() const
-  {
-    return protocol_;
-  }
-
-  /// Obtain an identifier for the protocol family.
-  int family() const
-  {
-    return family_;
-  }
-
-  /// Compare two protocols for equality.
-  friend bool operator==(const seq_packet_protocol& p1,
-      const seq_packet_protocol& p2)
-  {
-    return p1.family_ == p2.family_ && p1.protocol_ == p2.protocol_;
-  }
-
-  /// Compare two protocols for inequality.
-  friend bool operator!=(const seq_packet_protocol& p1,
-      const seq_packet_protocol& p2)
-  {
-    return !(p1 == p2);
-  }
-
-  /// The type of an endpoint.
-  typedef basic_endpoint<seq_packet_protocol> endpoint;
-
-  /// The generic socket type.
-  typedef basic_seq_packet_socket<seq_packet_protocol> socket;
-
-private:
-  int family_;
-  int protocol_;
-};
-
-} // namespace generic
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_GENERIC_SEQ_PACKET_PROTOCOL_HPP
diff --git a/tools/sdk/include/asio/asio/generic/stream_protocol.hpp b/tools/sdk/include/asio/asio/generic/stream_protocol.hpp
deleted file mode 100644
index 8349f25bc71..00000000000
--- a/tools/sdk/include/asio/asio/generic/stream_protocol.hpp
+++ /dev/null
@@ -1,127 +0,0 @@
-//
-// generic/stream_protocol.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_GENERIC_STREAM_PROTOCOL_HPP
-#define ASIO_GENERIC_STREAM_PROTOCOL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <typeinfo>
-#include "asio/basic_socket_iostream.hpp"
-#include "asio/basic_stream_socket.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/throw_exception.hpp"
-#include "asio/generic/basic_endpoint.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace generic {
-
-/// Encapsulates the flags needed for a generic stream-oriented socket.
-/**
- * The asio::generic::stream_protocol class contains flags necessary for
- * stream-oriented sockets of any address family and protocol.
- *
- * @par Examples
- * Constructing using a native address family and socket protocol:
- * @code stream_protocol p(AF_INET, IPPROTO_TCP); @endcode
- * Constructing from a specific protocol type:
- * @code stream_protocol p(asio::ip::tcp::v4()); @endcode
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Protocol.
- */
-class stream_protocol
-{
-public:
-  /// Construct a protocol object for a specific address family and protocol.
-  stream_protocol(int address_family, int socket_protocol)
-    : family_(address_family),
-      protocol_(socket_protocol)
-  {
-  }
-
-  /// Construct a generic protocol object from a specific protocol.
-  /**
-   * @throws @c bad_cast Thrown if the source protocol is not stream-oriented.
-   */
-  template <typename Protocol>
-  stream_protocol(const Protocol& source_protocol)
-    : family_(source_protocol.family()),
-      protocol_(source_protocol.protocol())
-  {
-    if (source_protocol.type() != type())
-    {
-      std::bad_cast ex;
-      asio::detail::throw_exception(ex);
-    }
-  }
-
-  /// Obtain an identifier for the type of the protocol.
-  int type() const
-  {
-    return ASIO_OS_DEF(SOCK_STREAM);
-  }
-
-  /// Obtain an identifier for the protocol.
-  int protocol() const
-  {
-    return protocol_;
-  }
-
-  /// Obtain an identifier for the protocol family.
-  int family() const
-  {
-    return family_;
-  }
-
-  /// Compare two protocols for equality.
-  friend bool operator==(const stream_protocol& p1, const stream_protocol& p2)
-  {
-    return p1.family_ == p2.family_ && p1.protocol_ == p2.protocol_;
-  }
-
-  /// Compare two protocols for inequality.
-  friend bool operator!=(const stream_protocol& p1, const stream_protocol& p2)
-  {
-    return !(p1 == p2);
-  }
-
-  /// The type of an endpoint.
-  typedef basic_endpoint<stream_protocol> endpoint;
-
-  /// The generic socket type.
-  typedef basic_stream_socket<stream_protocol> socket;
-
-#if !defined(ASIO_NO_IOSTREAM)
-  /// The generic socket iostream type.
-  typedef basic_socket_iostream<stream_protocol> iostream;
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-private:
-  int family_;
-  int protocol_;
-};
-
-} // namespace generic
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_GENERIC_STREAM_PROTOCOL_HPP
diff --git a/tools/sdk/include/asio/asio/handler_alloc_hook.hpp b/tools/sdk/include/asio/asio/handler_alloc_hook.hpp
deleted file mode 100644
index d7fe2b01fa5..00000000000
--- a/tools/sdk/include/asio/asio/handler_alloc_hook.hpp
+++ /dev/null
@@ -1,81 +0,0 @@
-//
-// handler_alloc_hook.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_HANDLER_ALLOC_HOOK_HPP
-#define ASIO_HANDLER_ALLOC_HOOK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default allocation function for handlers.
-/**
- * Asynchronous operations may need to allocate temporary objects. Since
- * asynchronous operations have a handler function object, these temporary
- * objects can be said to be associated with the handler.
- *
- * Implement asio_handler_allocate and asio_handler_deallocate for your own
- * handlers to provide custom allocation for these temporary objects.
- *
- * The default implementation of these allocation hooks uses <tt>::operator
- * new</tt> and <tt>::operator delete</tt>.
- *
- * @note All temporary objects associated with a handler will be deallocated
- * before the upcall to the handler is performed. This allows the same memory to
- * be reused for a subsequent asynchronous operation initiated by the handler.
- *
- * @par Example
- * @code
- * class my_handler;
- *
- * void* asio_handler_allocate(std::size_t size, my_handler* context)
- * {
- *   return ::operator new(size);
- * }
- *
- * void asio_handler_deallocate(void* pointer, std::size_t size,
- *     my_handler* context)
- * {
- *   ::operator delete(pointer);
- * }
- * @endcode
- */
-ASIO_DECL void* asio_handler_allocate(
-    std::size_t size, ...);
-
-/// Default deallocation function for handlers.
-/**
- * Implement asio_handler_allocate and asio_handler_deallocate for your own
- * handlers to provide custom allocation for the associated temporary objects.
- *
- * The default implementation of these allocation hooks uses <tt>::operator
- * new</tt> and <tt>::operator delete</tt>.
- *
- * @sa asio_handler_allocate.
- */
-ASIO_DECL void asio_handler_deallocate(
-    void* pointer, std::size_t size, ...);
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/impl/handler_alloc_hook.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_HANDLER_ALLOC_HOOK_HPP
diff --git a/tools/sdk/include/asio/asio/handler_continuation_hook.hpp b/tools/sdk/include/asio/asio/handler_continuation_hook.hpp
deleted file mode 100644
index d41d10595f3..00000000000
--- a/tools/sdk/include/asio/asio/handler_continuation_hook.hpp
+++ /dev/null
@@ -1,54 +0,0 @@
-//
-// handler_continuation_hook.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_HANDLER_CONTINUATION_HOOK_HPP
-#define ASIO_HANDLER_CONTINUATION_HOOK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default continuation function for handlers.
-/**
- * Asynchronous operations may represent a continuation of the asynchronous
- * control flow associated with the current handler. The implementation can use
- * this knowledge to optimise scheduling of the handler.
- *
- * Implement asio_handler_is_continuation for your own handlers to indicate
- * when a handler represents a continuation.
- *
- * The default implementation of the continuation hook returns <tt>false</tt>.
- *
- * @par Example
- * @code
- * class my_handler;
- *
- * bool asio_handler_is_continuation(my_handler* context)
- * {
- *   return true;
- * }
- * @endcode
- */
-inline bool asio_handler_is_continuation(...)
-{
-  return false;
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_HANDLER_CONTINUATION_HOOK_HPP
diff --git a/tools/sdk/include/asio/asio/handler_invoke_hook.hpp b/tools/sdk/include/asio/asio/handler_invoke_hook.hpp
deleted file mode 100644
index ee618e5ef63..00000000000
--- a/tools/sdk/include/asio/asio/handler_invoke_hook.hpp
+++ /dev/null
@@ -1,85 +0,0 @@
-//
-// handler_invoke_hook.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_HANDLER_INVOKE_HOOK_HPP
-#define ASIO_HANDLER_INVOKE_HOOK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/** @defgroup asio_handler_invoke asio::asio_handler_invoke
- *
- * @brief Default invoke function for handlers.
- *
- * Completion handlers for asynchronous operations are invoked by the
- * io_context associated with the corresponding object (e.g. a socket or
- * deadline_timer). Certain guarantees are made on when the handler may be
- * invoked, in particular that a handler can only be invoked from a thread that
- * is currently calling @c run() on the corresponding io_context object.
- * Handlers may subsequently be invoked through other objects (such as
- * io_context::strand objects) that provide additional guarantees.
- *
- * When asynchronous operations are composed from other asynchronous
- * operations, all intermediate handlers should be invoked using the same
- * method as the final handler. This is required to ensure that user-defined
- * objects are not accessed in a way that may violate the guarantees. This
- * hooking function ensures that the invoked method used for the final handler
- * is accessible at each intermediate step.
- *
- * Implement asio_handler_invoke for your own handlers to specify a custom
- * invocation strategy.
- *
- * This default implementation invokes the function object like so:
- * @code function(); @endcode
- * If necessary, the default implementation makes a copy of the function object
- * so that the non-const operator() can be used.
- *
- * @par Example
- * @code
- * class my_handler;
- *
- * template <typename Function>
- * void asio_handler_invoke(Function function, my_handler* context)
- * {
- *   context->strand_.dispatch(function);
- * }
- * @endcode
- */
-/*@{*/
-
-/// Default handler invocation hook used for non-const function objects.
-template <typename Function>
-inline void asio_handler_invoke(Function& function, ...)
-{
-  function();
-}
-
-/// Default handler invocation hook used for const function objects.
-template <typename Function>
-inline void asio_handler_invoke(const Function& function, ...)
-{
-  Function tmp(function);
-  tmp();
-}
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_HANDLER_INVOKE_HOOK_HPP
diff --git a/tools/sdk/include/asio/asio/handler_type.hpp b/tools/sdk/include/asio/asio/handler_type.hpp
deleted file mode 100644
index bc0d3051405..00000000000
--- a/tools/sdk/include/asio/asio/handler_type.hpp
+++ /dev/null
@@ -1,50 +0,0 @@
-//
-// handler_type.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_HANDLER_TYPE_HPP
-#define ASIO_HANDLER_TYPE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// (Deprecated: Use two-parameter version of async_result.) Default handler
-/// type traits provided for all completion token types.
-/**
- * The handler_type traits class is used for determining the concrete handler
- * type to be used for an asynchronous operation. It allows the handler type to
- * be determined at the point where the specific completion handler signature
- * is known.
- *
- * This template may be specialised for user-defined completion token types.
- */
-template <typename CompletionToken, typename Signature, typename = void>
-struct handler_type
-{
-  /// The handler type for the specific signature.
-  typedef typename conditional<
-    is_same<CompletionToken, typename decay<CompletionToken>::type>::value,
-    decay<CompletionToken>,
-    handler_type<typename decay<CompletionToken>::type, Signature>
-  >::type::type type;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_HANDLER_TYPE_HPP
diff --git a/tools/sdk/include/asio/asio/high_resolution_timer.hpp b/tools/sdk/include/asio/asio/high_resolution_timer.hpp
deleted file mode 100644
index 0549cc2569c..00000000000
--- a/tools/sdk/include/asio/asio/high_resolution_timer.hpp
+++ /dev/null
@@ -1,44 +0,0 @@
-//
-// high_resolution_timer.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_HIGH_RESOLUTION_TIMER_HPP
-#define ASIO_HIGH_RESOLUTION_TIMER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/basic_waitable_timer.hpp"
-#include "asio/detail/chrono.hpp"
-
-namespace asio {
-
-/// Typedef for a timer based on the high resolution clock.
-/**
- * This typedef uses the C++11 @c &lt;chrono&gt; standard library facility, if
- * available. Otherwise, it may use the Boost.Chrono library. To explicitly
- * utilise Boost.Chrono, use the basic_waitable_timer template directly:
- * @code
- * typedef basic_waitable_timer<boost::chrono::high_resolution_clock> timer;
- * @endcode
- */
-typedef basic_waitable_timer<
-    chrono::high_resolution_clock>
-  high_resolution_timer;
-
-} // namespace asio
-
-#endif // defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_HIGH_RESOLUTION_TIMER_HPP
diff --git a/tools/sdk/include/asio/asio/impl/buffered_read_stream.hpp b/tools/sdk/include/asio/asio/impl/buffered_read_stream.hpp
deleted file mode 100644
index e0ed20e4c20..00000000000
--- a/tools/sdk/include/asio/asio/impl/buffered_read_stream.hpp
+++ /dev/null
@@ -1,429 +0,0 @@
-//
-// impl/buffered_read_stream.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_BUFFERED_READ_STREAM_HPP
-#define ASIO_IMPL_BUFFERED_READ_STREAM_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-template <typename Stream>
-std::size_t buffered_read_stream<Stream>::fill()
-{
-  detail::buffer_resize_guard<detail::buffered_stream_storage>
-    resize_guard(storage_);
-  std::size_t previous_size = storage_.size();
-  storage_.resize(storage_.capacity());
-  storage_.resize(previous_size + next_layer_.read_some(buffer(
-          storage_.data() + previous_size,
-          storage_.size() - previous_size)));
-  resize_guard.commit();
-  return storage_.size() - previous_size;
-}
-
-template <typename Stream>
-std::size_t buffered_read_stream<Stream>::fill(asio::error_code& ec)
-{
-  detail::buffer_resize_guard<detail::buffered_stream_storage>
-    resize_guard(storage_);
-  std::size_t previous_size = storage_.size();
-  storage_.resize(storage_.capacity());
-  storage_.resize(previous_size + next_layer_.read_some(buffer(
-          storage_.data() + previous_size,
-          storage_.size() - previous_size),
-        ec));
-  resize_guard.commit();
-  return storage_.size() - previous_size;
-}
-
-namespace detail
-{
-  template <typename ReadHandler>
-  class buffered_fill_handler
-  {
-  public:
-    buffered_fill_handler(detail::buffered_stream_storage& storage,
-        std::size_t previous_size, ReadHandler& handler)
-      : storage_(storage),
-        previous_size_(previous_size),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    buffered_fill_handler(const buffered_fill_handler& other)
-      : storage_(other.storage_),
-        previous_size_(other.previous_size_),
-        handler_(other.handler_)
-    {
-    }
-
-    buffered_fill_handler(buffered_fill_handler&& other)
-      : storage_(other.storage_),
-        previous_size_(other.previous_size_),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        const std::size_t bytes_transferred)
-    {
-      storage_.resize(previous_size_ + bytes_transferred);
-      handler_(ec, bytes_transferred);
-    }
-
-  //private:
-    detail::buffered_stream_storage& storage_;
-    std::size_t previous_size_;
-    ReadHandler handler_;
-  };
-
-  template <typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      buffered_fill_handler<ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      buffered_fill_handler<ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      buffered_fill_handler<ReadHandler>* this_handler)
-  {
-    return asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      buffered_fill_handler<ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      buffered_fill_handler<ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename ReadHandler, typename Allocator>
-struct associated_allocator<
-    detail::buffered_fill_handler<ReadHandler>, Allocator>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator>::type type;
-
-  static type get(const detail::buffered_fill_handler<ReadHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename ReadHandler, typename Executor>
-struct associated_executor<
-    detail::buffered_fill_handler<ReadHandler>, Executor>
-{
-  typedef typename associated_executor<ReadHandler, Executor>::type type;
-
-  static type get(const detail::buffered_fill_handler<ReadHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename Stream>
-template <typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-buffered_read_stream<Stream>::async_fill(
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  std::size_t previous_size = storage_.size();
-  storage_.resize(storage_.capacity());
-  next_layer_.async_read_some(
-      buffer(
-        storage_.data() + previous_size,
-        storage_.size() - previous_size),
-      detail::buffered_fill_handler<ASIO_HANDLER_TYPE(
-        ReadHandler, void (asio::error_code, std::size_t))>(
-        storage_, previous_size, init.completion_handler));
-
-  return init.result.get();
-}
-
-template <typename Stream>
-template <typename MutableBufferSequence>
-std::size_t buffered_read_stream<Stream>::read_some(
-    const MutableBufferSequence& buffers)
-{
-  using asio::buffer_size;
-  if (buffer_size(buffers) == 0)
-    return 0;
-
-  if (storage_.empty())
-    this->fill();
-
-  return this->copy(buffers);
-}
-
-template <typename Stream>
-template <typename MutableBufferSequence>
-std::size_t buffered_read_stream<Stream>::read_some(
-    const MutableBufferSequence& buffers, asio::error_code& ec)
-{
-  ec = asio::error_code();
-
-  using asio::buffer_size;
-  if (buffer_size(buffers) == 0)
-    return 0;
-
-  if (storage_.empty() && !this->fill(ec))
-    return 0;
-
-  return this->copy(buffers);
-}
-
-namespace detail
-{
-  template <typename MutableBufferSequence, typename ReadHandler>
-  class buffered_read_some_handler
-  {
-  public:
-    buffered_read_some_handler(detail::buffered_stream_storage& storage,
-        const MutableBufferSequence& buffers, ReadHandler& handler)
-      : storage_(storage),
-        buffers_(buffers),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-      buffered_read_some_handler(const buffered_read_some_handler& other)
-        : storage_(other.storage_),
-          buffers_(other.buffers_),
-          handler_(other.handler_)
-      {
-      }
-
-      buffered_read_some_handler(buffered_read_some_handler&& other)
-        : storage_(other.storage_),
-          buffers_(other.buffers_),
-          handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-      {
-      }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec, std::size_t)
-    {
-      if (ec || storage_.empty())
-      {
-        const std::size_t length = 0;
-        handler_(ec, length);
-      }
-      else
-      {
-        const std::size_t bytes_copied = asio::buffer_copy(
-            buffers_, storage_.data(), storage_.size());
-        storage_.consume(bytes_copied);
-        handler_(ec, bytes_copied);
-      }
-    }
-
-  //private:
-    detail::buffered_stream_storage& storage_;
-    MutableBufferSequence buffers_;
-    ReadHandler handler_;
-  };
-
-  template <typename MutableBufferSequence, typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      buffered_read_some_handler<
-        MutableBufferSequence, ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename MutableBufferSequence, typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      buffered_read_some_handler<
-        MutableBufferSequence, ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename MutableBufferSequence, typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      buffered_read_some_handler<
-        MutableBufferSequence, ReadHandler>* this_handler)
-  {
-    return asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename MutableBufferSequence,
-      typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      buffered_read_some_handler<
-        MutableBufferSequence, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename MutableBufferSequence,
-      typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      buffered_read_some_handler<
-        MutableBufferSequence, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename MutableBufferSequence,
-    typename ReadHandler, typename Allocator>
-struct associated_allocator<
-    detail::buffered_read_some_handler<MutableBufferSequence, ReadHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator>::type type;
-
-  static type get(
-      const detail::buffered_read_some_handler<
-        MutableBufferSequence, ReadHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename MutableBufferSequence,
-    typename ReadHandler, typename Executor>
-struct associated_executor<
-    detail::buffered_read_some_handler<MutableBufferSequence, ReadHandler>,
-    Executor>
-{
-  typedef typename associated_executor<ReadHandler, Executor>::type type;
-
-  static type get(
-      const detail::buffered_read_some_handler<
-        MutableBufferSequence, ReadHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename Stream>
-template <typename MutableBufferSequence, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-buffered_read_stream<Stream>::async_read_some(
-    const MutableBufferSequence& buffers,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  using asio::buffer_size;
-  if (buffer_size(buffers) == 0 || !storage_.empty())
-  {
-    next_layer_.async_read_some(ASIO_MUTABLE_BUFFER(0, 0),
-        detail::buffered_read_some_handler<
-          MutableBufferSequence, ASIO_HANDLER_TYPE(
-            ReadHandler, void (asio::error_code, std::size_t))>(
-            storage_, buffers, init.completion_handler));
-  }
-  else
-  {
-    this->async_fill(detail::buffered_read_some_handler<
-          MutableBufferSequence, ASIO_HANDLER_TYPE(
-            ReadHandler, void (asio::error_code, std::size_t))>(
-            storage_, buffers, init.completion_handler));
-  }
-
-  return init.result.get();
-}
-
-template <typename Stream>
-template <typename MutableBufferSequence>
-std::size_t buffered_read_stream<Stream>::peek(
-    const MutableBufferSequence& buffers)
-{
-  if (storage_.empty())
-    this->fill();
-  return this->peek_copy(buffers);
-}
-
-template <typename Stream>
-template <typename MutableBufferSequence>
-std::size_t buffered_read_stream<Stream>::peek(
-    const MutableBufferSequence& buffers, asio::error_code& ec)
-{
-  ec = asio::error_code();
-  if (storage_.empty() && !this->fill(ec))
-    return 0;
-  return this->peek_copy(buffers);
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_BUFFERED_READ_STREAM_HPP
diff --git a/tools/sdk/include/asio/asio/impl/buffered_write_stream.hpp b/tools/sdk/include/asio/asio/impl/buffered_write_stream.hpp
deleted file mode 100644
index bc2d823ab7b..00000000000
--- a/tools/sdk/include/asio/asio/impl/buffered_write_stream.hpp
+++ /dev/null
@@ -1,411 +0,0 @@
-//
-// impl/buffered_write_stream.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_BUFFERED_WRITE_STREAM_HPP
-#define ASIO_IMPL_BUFFERED_WRITE_STREAM_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-template <typename Stream>
-std::size_t buffered_write_stream<Stream>::flush()
-{
-  std::size_t bytes_written = write(next_layer_,
-      buffer(storage_.data(), storage_.size()));
-  storage_.consume(bytes_written);
-  return bytes_written;
-}
-
-template <typename Stream>
-std::size_t buffered_write_stream<Stream>::flush(asio::error_code& ec)
-{
-  std::size_t bytes_written = write(next_layer_,
-      buffer(storage_.data(), storage_.size()),
-      transfer_all(), ec);
-  storage_.consume(bytes_written);
-  return bytes_written;
-}
-
-namespace detail
-{
-  template <typename WriteHandler>
-  class buffered_flush_handler
-  {
-  public:
-    buffered_flush_handler(detail::buffered_stream_storage& storage,
-        WriteHandler& handler)
-      : storage_(storage),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    buffered_flush_handler(const buffered_flush_handler& other)
-      : storage_(other.storage_),
-        handler_(other.handler_)
-    {
-    }
-
-    buffered_flush_handler(buffered_flush_handler&& other)
-      : storage_(other.storage_),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        const std::size_t bytes_written)
-    {
-      storage_.consume(bytes_written);
-      handler_(ec, bytes_written);
-    }
-
-  //private:
-    detail::buffered_stream_storage& storage_;
-    WriteHandler handler_;
-  };
-
-  template <typename WriteHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      buffered_flush_handler<WriteHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename WriteHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      buffered_flush_handler<WriteHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename WriteHandler>
-  inline bool asio_handler_is_continuation(
-      buffered_flush_handler<WriteHandler>* this_handler)
-  {
-    return asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename WriteHandler>
-  inline void asio_handler_invoke(Function& function,
-      buffered_flush_handler<WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename WriteHandler>
-  inline void asio_handler_invoke(const Function& function,
-      buffered_flush_handler<WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename WriteHandler, typename Allocator>
-struct associated_allocator<
-    detail::buffered_flush_handler<WriteHandler>, Allocator>
-{
-  typedef typename associated_allocator<WriteHandler, Allocator>::type type;
-
-  static type get(const detail::buffered_flush_handler<WriteHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<WriteHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename WriteHandler, typename Executor>
-struct associated_executor<
-    detail::buffered_flush_handler<WriteHandler>, Executor>
-{
-  typedef typename associated_executor<WriteHandler, Executor>::type type;
-
-  static type get(const detail::buffered_flush_handler<WriteHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<WriteHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename Stream>
-template <typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-buffered_write_stream<Stream>::async_flush(
-    ASIO_MOVE_ARG(WriteHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a WriteHandler.
-  ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-  async_completion<WriteHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  async_write(next_layer_, buffer(storage_.data(), storage_.size()),
-      detail::buffered_flush_handler<ASIO_HANDLER_TYPE(
-        WriteHandler, void (asio::error_code, std::size_t))>(
-        storage_, init.completion_handler));
-
-  return init.result.get();
-}
-
-template <typename Stream>
-template <typename ConstBufferSequence>
-std::size_t buffered_write_stream<Stream>::write_some(
-    const ConstBufferSequence& buffers)
-{
-  using asio::buffer_size;
-  if (buffer_size(buffers) == 0)
-    return 0;
-
-  if (storage_.size() == storage_.capacity())
-    this->flush();
-
-  return this->copy(buffers);
-}
-
-template <typename Stream>
-template <typename ConstBufferSequence>
-std::size_t buffered_write_stream<Stream>::write_some(
-    const ConstBufferSequence& buffers, asio::error_code& ec)
-{
-  ec = asio::error_code();
-
-  using asio::buffer_size;
-  if (buffer_size(buffers) == 0)
-    return 0;
-
-  if (storage_.size() == storage_.capacity() && !flush(ec))
-    return 0;
-
-  return this->copy(buffers);
-}
-
-namespace detail
-{
-  template <typename ConstBufferSequence, typename WriteHandler>
-  class buffered_write_some_handler
-  {
-  public:
-    buffered_write_some_handler(detail::buffered_stream_storage& storage,
-        const ConstBufferSequence& buffers, WriteHandler& handler)
-      : storage_(storage),
-        buffers_(buffers),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-      buffered_write_some_handler(const buffered_write_some_handler& other)
-        : storage_(other.storage_),
-          buffers_(other.buffers_),
-          handler_(other.handler_)
-      {
-      }
-
-      buffered_write_some_handler(buffered_write_some_handler&& other)
-        : storage_(other.storage_),
-          buffers_(other.buffers_),
-          handler_(ASIO_MOVE_CAST(WriteHandler)(other.handler_))
-      {
-      }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec, std::size_t)
-    {
-      if (ec)
-      {
-        const std::size_t length = 0;
-        handler_(ec, length);
-      }
-      else
-      {
-        using asio::buffer_size;
-        std::size_t orig_size = storage_.size();
-        std::size_t space_avail = storage_.capacity() - orig_size;
-        std::size_t bytes_avail = buffer_size(buffers_);
-        std::size_t length = bytes_avail < space_avail
-          ? bytes_avail : space_avail;
-        storage_.resize(orig_size + length);
-        const std::size_t bytes_copied = asio::buffer_copy(
-            storage_.data() + orig_size, buffers_, length);
-        handler_(ec, bytes_copied);
-      }
-    }
-
-  //private:
-    detail::buffered_stream_storage& storage_;
-    ConstBufferSequence buffers_;
-    WriteHandler handler_;
-  };
-
-  template <typename ConstBufferSequence, typename WriteHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      buffered_write_some_handler<
-        ConstBufferSequence, WriteHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename ConstBufferSequence, typename WriteHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      buffered_write_some_handler<
-        ConstBufferSequence, WriteHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename ConstBufferSequence, typename WriteHandler>
-  inline bool asio_handler_is_continuation(
-      buffered_write_some_handler<
-        ConstBufferSequence, WriteHandler>* this_handler)
-  {
-    return asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename ConstBufferSequence,
-      typename WriteHandler>
-  inline void asio_handler_invoke(Function& function,
-      buffered_write_some_handler<
-        ConstBufferSequence, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename ConstBufferSequence,
-      typename WriteHandler>
-  inline void asio_handler_invoke(const Function& function,
-      buffered_write_some_handler<
-        ConstBufferSequence, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename ConstBufferSequence,
-    typename WriteHandler, typename Allocator>
-struct associated_allocator<
-    detail::buffered_write_some_handler<ConstBufferSequence, WriteHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<WriteHandler, Allocator>::type type;
-
-  static type get(
-      const detail::buffered_write_some_handler<
-        ConstBufferSequence, WriteHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<WriteHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename ConstBufferSequence,
-    typename WriteHandler, typename Executor>
-struct associated_executor<
-    detail::buffered_write_some_handler<ConstBufferSequence, WriteHandler>,
-    Executor>
-{
-  typedef typename associated_executor<WriteHandler, Executor>::type type;
-
-  static type get(
-      const detail::buffered_write_some_handler<
-        ConstBufferSequence, WriteHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<WriteHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename Stream>
-template <typename ConstBufferSequence, typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-buffered_write_stream<Stream>::async_write_some(
-    const ConstBufferSequence& buffers,
-    ASIO_MOVE_ARG(WriteHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a WriteHandler.
-  ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-  async_completion<WriteHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  using asio::buffer_size;
-  if (buffer_size(buffers) == 0
-      || storage_.size() < storage_.capacity())
-  {
-    next_layer_.async_write_some(ASIO_CONST_BUFFER(0, 0),
-        detail::buffered_write_some_handler<
-          ConstBufferSequence, ASIO_HANDLER_TYPE(
-            WriteHandler, void (asio::error_code, std::size_t))>(
-            storage_, buffers, init.completion_handler));
-  }
-  else
-  {
-    this->async_flush(detail::buffered_write_some_handler<
-          ConstBufferSequence, ASIO_HANDLER_TYPE(
-            WriteHandler, void (asio::error_code, std::size_t))>(
-            storage_, buffers, init.completion_handler));
-  }
-
-  return init.result.get();
-}
-
-template <typename Stream>
-template <typename ConstBufferSequence>
-std::size_t buffered_write_stream<Stream>::copy(
-    const ConstBufferSequence& buffers)
-{
-  using asio::buffer_size;
-  std::size_t orig_size = storage_.size();
-  std::size_t space_avail = storage_.capacity() - orig_size;
-  std::size_t bytes_avail = buffer_size(buffers);
-  std::size_t length = bytes_avail < space_avail ? bytes_avail : space_avail;
-  storage_.resize(orig_size + length);
-  return asio::buffer_copy(
-      storage_.data() + orig_size, buffers, length);
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_BUFFERED_WRITE_STREAM_HPP
diff --git a/tools/sdk/include/asio/asio/impl/connect.hpp b/tools/sdk/include/asio/asio/impl/connect.hpp
deleted file mode 100644
index bff1913b1fb..00000000000
--- a/tools/sdk/include/asio/asio/impl/connect.hpp
+++ /dev/null
@@ -1,860 +0,0 @@
-//
-// impl/connect.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_CONNECT_HPP
-#define ASIO_IMPL_CONNECT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include <algorithm>
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/post.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail
-{
-  struct default_connect_condition
-  {
-    template <typename Endpoint>
-    bool operator()(const asio::error_code&, const Endpoint&)
-    {
-      return true;
-    }
-  };
-
-  template <typename Protocol, typename Iterator>
-  inline typename Protocol::endpoint deref_connect_result(
-      Iterator iter, asio::error_code& ec)
-  {
-    return ec ? typename Protocol::endpoint() : *iter;
-  }
-
-  template <typename T, typename Iterator>
-  struct legacy_connect_condition_helper : T
-  {
-    typedef char (*fallback_func_type)(...);
-    operator fallback_func_type() const;
-  };
-
-  template <typename R, typename Arg1, typename Arg2, typename Iterator>
-  struct legacy_connect_condition_helper<R (*)(Arg1, Arg2), Iterator>
-  {
-    R operator()(Arg1, Arg2) const;
-    char operator()(...) const;
-  };
-
-  template <typename T, typename Iterator>
-  struct is_legacy_connect_condition
-  {
-    static char asio_connect_condition_check(char);
-    static char (&asio_connect_condition_check(Iterator))[2];
-
-    static const bool value =
-      sizeof(asio_connect_condition_check(
-        (*static_cast<legacy_connect_condition_helper<T, Iterator>*>(0))(
-          *static_cast<const asio::error_code*>(0),
-          *static_cast<const Iterator*>(0)))) != 1;
-  };
-
-  template <typename ConnectCondition, typename Iterator>
-  inline Iterator call_connect_condition(ConnectCondition& connect_condition,
-      const asio::error_code& ec, Iterator next, Iterator end,
-      typename enable_if<is_legacy_connect_condition<
-        ConnectCondition, Iterator>::value>::type* = 0)
-  {
-    if (next != end)
-      return connect_condition(ec, next);
-    return end;
-  }
-
-  template <typename ConnectCondition, typename Iterator>
-  inline Iterator call_connect_condition(ConnectCondition& connect_condition,
-      const asio::error_code& ec, Iterator next, Iterator end,
-      typename enable_if<!is_legacy_connect_condition<
-        ConnectCondition, Iterator>::value>::type* = 0)
-  {
-    for (;next != end; ++next)
-      if (connect_condition(ec, *next))
-        return next;
-    return end;
-  }
-}
-
-template <typename Protocol ASIO_SVC_TPARAM, typename EndpointSequence>
-typename Protocol::endpoint connect(
-    basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type*)
-{
-  asio::error_code ec;
-  typename Protocol::endpoint result = connect(s, endpoints, ec);
-  asio::detail::throw_error(ec, "connect");
-  return result;
-}
-
-template <typename Protocol ASIO_SVC_TPARAM, typename EndpointSequence>
-typename Protocol::endpoint connect(
-    basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints, asio::error_code& ec,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type*)
-{
-  return detail::deref_connect_result<Protocol>(
-      connect(s, endpoints.begin(), endpoints.end(),
-        detail::default_connect_condition(), ec), ec);
-}
-
-#if !defined(ASIO_NO_DEPRECATED)
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s, Iterator begin,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type*)
-{
-  asio::error_code ec;
-  Iterator result = connect(s, begin, ec);
-  asio::detail::throw_error(ec, "connect");
-  return result;
-}
-
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator>
-inline Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, asio::error_code& ec,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type*)
-{
-  return connect(s, begin, Iterator(), detail::default_connect_condition(), ec);
-}
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end)
-{
-  asio::error_code ec;
-  Iterator result = connect(s, begin, end, ec);
-  asio::detail::throw_error(ec, "connect");
-  return result;
-}
-
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator>
-inline Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end, asio::error_code& ec)
-{
-  return connect(s, begin, end, detail::default_connect_condition(), ec);
-}
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename EndpointSequence, typename ConnectCondition>
-typename Protocol::endpoint connect(
-    basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints, ConnectCondition connect_condition,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type*)
-{
-  asio::error_code ec;
-  typename Protocol::endpoint result = connect(
-      s, endpoints, connect_condition, ec);
-  asio::detail::throw_error(ec, "connect");
-  return result;
-}
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename EndpointSequence, typename ConnectCondition>
-typename Protocol::endpoint connect(
-    basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints, ConnectCondition connect_condition,
-    asio::error_code& ec,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type*)
-{
-  return detail::deref_connect_result<Protocol>(
-      connect(s, endpoints.begin(), endpoints.end(),
-        connect_condition, ec), ec);
-}
-
-#if !defined(ASIO_NO_DEPRECATED)
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, ConnectCondition connect_condition,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type*)
-{
-  asio::error_code ec;
-  Iterator result = connect(s, begin, connect_condition, ec);
-  asio::detail::throw_error(ec, "connect");
-  return result;
-}
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition>
-inline Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, ConnectCondition connect_condition,
-    asio::error_code& ec,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type*)
-{
-  return connect(s, begin, Iterator(), connect_condition, ec);
-}
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end, ConnectCondition connect_condition)
-{
-  asio::error_code ec;
-  Iterator result = connect(s, begin, end, connect_condition, ec);
-  asio::detail::throw_error(ec, "connect");
-  return result;
-}
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition>
-Iterator connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end, ConnectCondition connect_condition,
-    asio::error_code& ec)
-{
-  ec = asio::error_code();
-
-  for (Iterator iter = begin; iter != end; ++iter)
-  {
-    iter = (detail::call_connect_condition(connect_condition, ec, iter, end));
-    if (iter != end)
-    {
-      s.close(ec);
-      s.connect(*iter, ec);
-      if (!ec)
-        return iter;
-    }
-    else
-      break;
-  }
-
-  if (!ec)
-    ec = asio::error::not_found;
-
-  return end;
-}
-
-namespace detail
-{
-  // Enable the empty base class optimisation for the connect condition.
-  template <typename ConnectCondition>
-  class base_from_connect_condition
-  {
-  protected:
-    explicit base_from_connect_condition(
-        const ConnectCondition& connect_condition)
-      : connect_condition_(connect_condition)
-    {
-    }
-
-    template <typename Iterator>
-    void check_condition(const asio::error_code& ec,
-        Iterator& iter, Iterator& end)
-    {
-      iter = detail::call_connect_condition(connect_condition_, ec, iter, end);
-    }
-
-  private:
-    ConnectCondition connect_condition_;
-  };
-
-  // The default_connect_condition implementation is essentially a no-op. This
-  // template specialisation lets us eliminate all costs associated with it.
-  template <>
-  class base_from_connect_condition<default_connect_condition>
-  {
-  protected:
-    explicit base_from_connect_condition(const default_connect_condition&)
-    {
-    }
-
-    template <typename Iterator>
-    void check_condition(const asio::error_code&, Iterator&, Iterator&)
-    {
-    }
-  };
-
-  template <typename Protocol ASIO_SVC_TPARAM,
-      typename EndpointSequence, typename ConnectCondition,
-      typename RangeConnectHandler>
-  class range_connect_op : base_from_connect_condition<ConnectCondition>
-  {
-  public:
-    range_connect_op(basic_socket<Protocol ASIO_SVC_TARG>& sock,
-        const EndpointSequence& endpoints,
-        const ConnectCondition& connect_condition,
-        RangeConnectHandler& handler)
-      : base_from_connect_condition<ConnectCondition>(connect_condition),
-        socket_(sock),
-        endpoints_(endpoints),
-        index_(0),
-        start_(0),
-        handler_(ASIO_MOVE_CAST(RangeConnectHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    range_connect_op(const range_connect_op& other)
-      : base_from_connect_condition<ConnectCondition>(other),
-        socket_(other.socket_),
-        endpoints_(other.endpoints_),
-        index_(other.index_),
-        start_(other.start_),
-        handler_(other.handler_)
-    {
-    }
-
-    range_connect_op(range_connect_op&& other)
-      : base_from_connect_condition<ConnectCondition>(other),
-        socket_(other.socket_),
-        endpoints_(other.endpoints_),
-        index_(other.index_),
-        start_(other.start_),
-        handler_(ASIO_MOVE_CAST(RangeConnectHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(asio::error_code ec, int start = 0)
-    {
-      typename EndpointSequence::const_iterator begin = endpoints_.begin();
-      typename EndpointSequence::const_iterator iter = begin;
-      std::advance(iter, index_);
-      typename EndpointSequence::const_iterator end = endpoints_.end();
-
-      switch (start_ = start)
-      {
-        case 1:
-        for (;;)
-        {
-          this->check_condition(ec, iter, end);
-          index_ = std::distance(begin, iter);
-
-          if (iter != end)
-          {
-            socket_.close(ec);
-            socket_.async_connect(*iter,
-                ASIO_MOVE_CAST(range_connect_op)(*this));
-            return;
-          }
-
-          if (start)
-          {
-            ec = asio::error::not_found;
-            asio::post(socket_.get_executor(),
-                detail::bind_handler(
-                  ASIO_MOVE_CAST(range_connect_op)(*this), ec));
-            return;
-          }
-
-          default:
-
-          if (iter == end)
-            break;
-
-          if (!socket_.is_open())
-          {
-            ec = asio::error::operation_aborted;
-            break;
-          }
-
-          if (!ec)
-            break;
-
-          ++iter;
-          ++index_;
-        }
-
-        handler_(static_cast<const asio::error_code&>(ec),
-            static_cast<const typename Protocol::endpoint&>(
-              ec || iter == end ? typename Protocol::endpoint() : *iter));
-      }
-    }
-
-  //private:
-    basic_socket<Protocol ASIO_SVC_TARG>& socket_;
-    EndpointSequence endpoints_;
-    std::size_t index_;
-    int start_;
-    RangeConnectHandler handler_;
-  };
-
-  template <typename Protocol ASIO_SVC_TPARAM,
-      typename EndpointSequence, typename ConnectCondition,
-      typename RangeConnectHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      range_connect_op<Protocol ASIO_SVC_TARG, EndpointSequence,
-        ConnectCondition, RangeConnectHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename Protocol ASIO_SVC_TPARAM,
-      typename EndpointSequence, typename ConnectCondition,
-      typename RangeConnectHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      range_connect_op<Protocol ASIO_SVC_TARG, EndpointSequence,
-        ConnectCondition, RangeConnectHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename Protocol ASIO_SVC_TPARAM,
-      typename EndpointSequence, typename ConnectCondition,
-      typename RangeConnectHandler>
-  inline bool asio_handler_is_continuation(
-      range_connect_op<Protocol ASIO_SVC_TARG, EndpointSequence,
-        ConnectCondition, RangeConnectHandler>* this_handler)
-  {
-    return asio_handler_cont_helpers::is_continuation(
-        this_handler->handler_);
-  }
-
-  template <typename Function, typename Protocol
-      ASIO_SVC_TPARAM, typename EndpointSequence,
-      typename ConnectCondition, typename RangeConnectHandler>
-  inline void asio_handler_invoke(Function& function,
-      range_connect_op<Protocol ASIO_SVC_TARG, EndpointSequence,
-        ConnectCondition, RangeConnectHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename Protocol
-      ASIO_SVC_TPARAM, typename EndpointSequence,
-      typename ConnectCondition, typename RangeConnectHandler>
-  inline void asio_handler_invoke(const Function& function,
-      range_connect_op<Protocol ASIO_SVC_TARG, EndpointSequence,
-        ConnectCondition, RangeConnectHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Protocol ASIO_SVC_TPARAM, typename Iterator,
-      typename ConnectCondition, typename IteratorConnectHandler>
-  class iterator_connect_op : base_from_connect_condition<ConnectCondition>
-  {
-  public:
-    iterator_connect_op(basic_socket<Protocol ASIO_SVC_TARG>& sock,
-        const Iterator& begin, const Iterator& end,
-        const ConnectCondition& connect_condition,
-        IteratorConnectHandler& handler)
-      : base_from_connect_condition<ConnectCondition>(connect_condition),
-        socket_(sock),
-        iter_(begin),
-        end_(end),
-        start_(0),
-        handler_(ASIO_MOVE_CAST(IteratorConnectHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    iterator_connect_op(const iterator_connect_op& other)
-      : base_from_connect_condition<ConnectCondition>(other),
-        socket_(other.socket_),
-        iter_(other.iter_),
-        end_(other.end_),
-        start_(other.start_),
-        handler_(other.handler_)
-    {
-    }
-
-    iterator_connect_op(iterator_connect_op&& other)
-      : base_from_connect_condition<ConnectCondition>(other),
-        socket_(other.socket_),
-        iter_(other.iter_),
-        end_(other.end_),
-        start_(other.start_),
-        handler_(ASIO_MOVE_CAST(IteratorConnectHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(asio::error_code ec, int start = 0)
-    {
-      switch (start_ = start)
-      {
-        case 1:
-        for (;;)
-        {
-          this->check_condition(ec, iter_, end_);
-
-          if (iter_ != end_)
-          {
-            socket_.close(ec);
-            socket_.async_connect(*iter_,
-                ASIO_MOVE_CAST(iterator_connect_op)(*this));
-            return;
-          }
-
-          if (start)
-          {
-            ec = asio::error::not_found;
-            asio::post(socket_.get_executor(),
-                detail::bind_handler(
-                  ASIO_MOVE_CAST(iterator_connect_op)(*this), ec));
-            return;
-          }
-
-          default:
-
-          if (iter_ == end_)
-            break;
-
-          if (!socket_.is_open())
-          {
-            ec = asio::error::operation_aborted;
-            break;
-          }
-
-          if (!ec)
-            break;
-
-          ++iter_;
-        }
-
-        handler_(static_cast<const asio::error_code&>(ec),
-            static_cast<const Iterator&>(iter_));
-      }
-    }
-
-  //private:
-    basic_socket<Protocol ASIO_SVC_TARG>& socket_;
-    Iterator iter_;
-    Iterator end_;
-    int start_;
-    IteratorConnectHandler handler_;
-  };
-
-  template <typename Protocol ASIO_SVC_TPARAM, typename Iterator,
-      typename ConnectCondition, typename IteratorConnectHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-        ConnectCondition, IteratorConnectHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename Protocol ASIO_SVC_TPARAM, typename Iterator,
-      typename ConnectCondition, typename IteratorConnectHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-        ConnectCondition, IteratorConnectHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename Protocol ASIO_SVC_TPARAM, typename Iterator,
-      typename ConnectCondition, typename IteratorConnectHandler>
-  inline bool asio_handler_is_continuation(
-      iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-        ConnectCondition, IteratorConnectHandler>* this_handler)
-  {
-    return asio_handler_cont_helpers::is_continuation(
-        this_handler->handler_);
-  }
-
-  template <typename Function, typename Protocol
-      ASIO_SVC_TPARAM, typename Iterator,
-      typename ConnectCondition, typename IteratorConnectHandler>
-  inline void asio_handler_invoke(Function& function,
-      iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-        ConnectCondition, IteratorConnectHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename Protocol
-      ASIO_SVC_TPARAM, typename Iterator,
-      typename ConnectCondition, typename IteratorConnectHandler>
-  inline void asio_handler_invoke(const Function& function,
-      iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-        ConnectCondition, IteratorConnectHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename EndpointSequence, typename ConnectCondition,
-    typename RangeConnectHandler, typename Allocator>
-struct associated_allocator<
-    detail::range_connect_op<Protocol ASIO_SVC_TARG,
-      EndpointSequence, ConnectCondition, RangeConnectHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<
-      RangeConnectHandler, Allocator>::type type;
-
-  static type get(
-      const detail::range_connect_op<Protocol ASIO_SVC_TARG,
-        EndpointSequence, ConnectCondition, RangeConnectHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<RangeConnectHandler,
-        Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename EndpointSequence, typename ConnectCondition,
-    typename RangeConnectHandler, typename Executor>
-struct associated_executor<
-    detail::range_connect_op<Protocol ASIO_SVC_TARG,
-      EndpointSequence, ConnectCondition, RangeConnectHandler>,
-    Executor>
-{
-  typedef typename associated_executor<
-      RangeConnectHandler, Executor>::type type;
-
-  static type get(
-      const detail::range_connect_op<Protocol ASIO_SVC_TARG,
-        EndpointSequence, ConnectCondition, RangeConnectHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<RangeConnectHandler,
-        Executor>::get(h.handler_, ex);
-  }
-};
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition,
-    typename IteratorConnectHandler, typename Allocator>
-struct associated_allocator<
-    detail::iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-      ConnectCondition, IteratorConnectHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<
-      IteratorConnectHandler, Allocator>::type type;
-
-  static type get(
-      const detail::iterator_connect_op<Protocol ASIO_SVC_TARG,
-        Iterator, ConnectCondition, IteratorConnectHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<IteratorConnectHandler,
-        Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename ConnectCondition,
-    typename IteratorConnectHandler, typename Executor>
-struct associated_executor<
-    detail::iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-      ConnectCondition, IteratorConnectHandler>,
-    Executor>
-{
-  typedef typename associated_executor<
-      IteratorConnectHandler, Executor>::type type;
-
-  static type get(
-      const detail::iterator_connect_op<Protocol ASIO_SVC_TARG,
-        Iterator, ConnectCondition, IteratorConnectHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<IteratorConnectHandler,
-        Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename EndpointSequence, typename RangeConnectHandler>
-inline ASIO_INITFN_RESULT_TYPE(RangeConnectHandler,
-    void (asio::error_code, typename Protocol::endpoint))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints,
-    ASIO_MOVE_ARG(RangeConnectHandler) handler,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a RangeConnectHandler.
-  ASIO_RANGE_CONNECT_HANDLER_CHECK(
-      RangeConnectHandler, handler, typename Protocol::endpoint) type_check;
-
-  async_completion<RangeConnectHandler,
-    void (asio::error_code, typename Protocol::endpoint)>
-      init(handler);
-
-  detail::range_connect_op<Protocol ASIO_SVC_TARG, EndpointSequence,
-    detail::default_connect_condition,
-      ASIO_HANDLER_TYPE(RangeConnectHandler,
-        void (asio::error_code, typename Protocol::endpoint))>(s,
-          endpoints, detail::default_connect_condition(),
-            init.completion_handler)(asio::error_code(), 1);
-
-  return init.result.get();
-}
-
-#if !defined(ASIO_NO_DEPRECATED)
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename IteratorConnectHandler>
-inline ASIO_INITFN_RESULT_TYPE(IteratorConnectHandler,
-    void (asio::error_code, Iterator))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, ASIO_MOVE_ARG(IteratorConnectHandler) handler,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a IteratorConnectHandler.
-  ASIO_ITERATOR_CONNECT_HANDLER_CHECK(
-      IteratorConnectHandler, handler, Iterator) type_check;
-
-  async_completion<IteratorConnectHandler,
-    void (asio::error_code, Iterator)> init(handler);
-
-  detail::iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-    detail::default_connect_condition, ASIO_HANDLER_TYPE(
-      IteratorConnectHandler, void (asio::error_code, Iterator))>(s,
-        begin, Iterator(), detail::default_connect_condition(),
-          init.completion_handler)(asio::error_code(), 1);
-
-  return init.result.get();
-}
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Protocol ASIO_SVC_TPARAM,
-    typename Iterator, typename IteratorConnectHandler>
-inline ASIO_INITFN_RESULT_TYPE(IteratorConnectHandler,
-    void (asio::error_code, Iterator))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end,
-    ASIO_MOVE_ARG(IteratorConnectHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a IteratorConnectHandler.
-  ASIO_ITERATOR_CONNECT_HANDLER_CHECK(
-      IteratorConnectHandler, handler, Iterator) type_check;
-
-  async_completion<IteratorConnectHandler,
-    void (asio::error_code, Iterator)> init(handler);
-
-  detail::iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-    detail::default_connect_condition, ASIO_HANDLER_TYPE(
-      IteratorConnectHandler, void (asio::error_code, Iterator))>(s,
-        begin, end, detail::default_connect_condition(),
-          init.completion_handler)(asio::error_code(), 1);
-
-  return init.result.get();
-}
-
-template <typename Protocol ASIO_SVC_TPARAM, typename EndpointSequence,
-    typename ConnectCondition, typename RangeConnectHandler>
-inline ASIO_INITFN_RESULT_TYPE(RangeConnectHandler,
-    void (asio::error_code, typename Protocol::endpoint))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    const EndpointSequence& endpoints, ConnectCondition connect_condition,
-    ASIO_MOVE_ARG(RangeConnectHandler) handler,
-    typename enable_if<is_endpoint_sequence<
-        EndpointSequence>::value>::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a RangeConnectHandler.
-  ASIO_RANGE_CONNECT_HANDLER_CHECK(
-      RangeConnectHandler, handler, typename Protocol::endpoint) type_check;
-
-  async_completion<RangeConnectHandler,
-    void (asio::error_code, typename Protocol::endpoint)>
-      init(handler);
-
-  detail::range_connect_op<Protocol ASIO_SVC_TARG, EndpointSequence,
-    ConnectCondition, ASIO_HANDLER_TYPE(RangeConnectHandler,
-      void (asio::error_code, typename Protocol::endpoint))>(s,
-        endpoints, connect_condition, init.completion_handler)(
-          asio::error_code(), 1);
-
-  return init.result.get();
-}
-
-#if !defined(ASIO_NO_DEPRECATED)
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator,
-    typename ConnectCondition, typename IteratorConnectHandler>
-inline ASIO_INITFN_RESULT_TYPE(IteratorConnectHandler,
-    void (asio::error_code, Iterator))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, ConnectCondition connect_condition,
-    ASIO_MOVE_ARG(IteratorConnectHandler) handler,
-    typename enable_if<!is_endpoint_sequence<Iterator>::value>::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a IteratorConnectHandler.
-  ASIO_ITERATOR_CONNECT_HANDLER_CHECK(
-      IteratorConnectHandler, handler, Iterator) type_check;
-
-  async_completion<IteratorConnectHandler,
-    void (asio::error_code, Iterator)> init(handler);
-
-  detail::iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-    ConnectCondition, ASIO_HANDLER_TYPE(
-      IteratorConnectHandler, void (asio::error_code, Iterator))>(s,
-        begin, Iterator(), connect_condition, init.completion_handler)(
-          asio::error_code(), 1);
-
-  return init.result.get();
-}
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Protocol ASIO_SVC_TPARAM, typename Iterator,
-    typename ConnectCondition, typename IteratorConnectHandler>
-inline ASIO_INITFN_RESULT_TYPE(IteratorConnectHandler,
-    void (asio::error_code, Iterator))
-async_connect(basic_socket<Protocol ASIO_SVC_TARG>& s,
-    Iterator begin, Iterator end, ConnectCondition connect_condition,
-    ASIO_MOVE_ARG(IteratorConnectHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a IteratorConnectHandler.
-  ASIO_ITERATOR_CONNECT_HANDLER_CHECK(
-      IteratorConnectHandler, handler, Iterator) type_check;
-
-  async_completion<IteratorConnectHandler,
-    void (asio::error_code, Iterator)> init(handler);
-
-  detail::iterator_connect_op<Protocol ASIO_SVC_TARG, Iterator,
-    ConnectCondition, ASIO_HANDLER_TYPE(
-      IteratorConnectHandler, void (asio::error_code, Iterator))>(s,
-        begin, end, connect_condition, init.completion_handler)(
-          asio::error_code(), 1);
-
-  return init.result.get();
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_CONNECT_HPP
diff --git a/tools/sdk/include/asio/asio/impl/defer.hpp b/tools/sdk/include/asio/asio/impl/defer.hpp
deleted file mode 100644
index a27df0f134b..00000000000
--- a/tools/sdk/include/asio/asio/impl/defer.hpp
+++ /dev/null
@@ -1,77 +0,0 @@
-//
-// impl/defer.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_DEFER_HPP
-#define ASIO_IMPL_DEFER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/detail/work_dispatcher.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-template <typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) defer(
-    ASIO_MOVE_ARG(CompletionToken) token)
-{
-  typedef ASIO_HANDLER_TYPE(CompletionToken, void()) handler;
-
-  async_completion<CompletionToken, void()> init(token);
-
-  typename associated_executor<handler>::type ex(
-      (get_associated_executor)(init.completion_handler));
-
-  typename associated_allocator<handler>::type alloc(
-      (get_associated_allocator)(init.completion_handler));
-
-  ex.defer(ASIO_MOVE_CAST(handler)(init.completion_handler), alloc);
-
-  return init.result.get();
-}
-
-template <typename Executor, typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) defer(
-    const Executor& ex, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_executor<Executor>::value>::type*)
-{
-  typedef ASIO_HANDLER_TYPE(CompletionToken, void()) handler;
-
-  async_completion<CompletionToken, void()> init(token);
-
-  typename associated_allocator<handler>::type alloc(
-      (get_associated_allocator)(init.completion_handler));
-
-  ex.defer(detail::work_dispatcher<handler>(init.completion_handler), alloc);
-
-  return init.result.get();
-}
-
-template <typename ExecutionContext, typename CompletionToken>
-inline ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) defer(
-    ExecutionContext& ctx, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_convertible<
-      ExecutionContext&, execution_context&>::value>::type*)
-{
-  return (defer)(ctx.get_executor(),
-      ASIO_MOVE_CAST(CompletionToken)(token));
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_DEFER_HPP
diff --git a/tools/sdk/include/asio/asio/impl/dispatch.hpp b/tools/sdk/include/asio/asio/impl/dispatch.hpp
deleted file mode 100644
index 4e11c6b2eba..00000000000
--- a/tools/sdk/include/asio/asio/impl/dispatch.hpp
+++ /dev/null
@@ -1,78 +0,0 @@
-//
-// impl/dispatch.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_DISPATCH_HPP
-#define ASIO_IMPL_DISPATCH_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/detail/work_dispatcher.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-template <typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) dispatch(
-    ASIO_MOVE_ARG(CompletionToken) token)
-{
-  typedef ASIO_HANDLER_TYPE(CompletionToken, void()) handler;
-
-  async_completion<CompletionToken, void()> init(token);
-
-  typename associated_executor<handler>::type ex(
-      (get_associated_executor)(init.completion_handler));
-
-  typename associated_allocator<handler>::type alloc(
-      (get_associated_allocator)(init.completion_handler));
-
-  ex.dispatch(ASIO_MOVE_CAST(handler)(init.completion_handler), alloc);
-
-  return init.result.get();
-}
-
-template <typename Executor, typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) dispatch(
-    const Executor& ex, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_executor<Executor>::value>::type*)
-{
-  typedef ASIO_HANDLER_TYPE(CompletionToken, void()) handler;
-
-  async_completion<CompletionToken, void()> init(token);
-
-  typename associated_allocator<handler>::type alloc(
-      (get_associated_allocator)(init.completion_handler));
-
-  ex.dispatch(detail::work_dispatcher<handler>(
-        init.completion_handler), alloc);
-
-  return init.result.get();
-}
-
-template <typename ExecutionContext, typename CompletionToken>
-inline ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) dispatch(
-    ExecutionContext& ctx, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_convertible<
-      ExecutionContext&, execution_context&>::value>::type*)
-{
-  return (dispatch)(ctx.get_executor(),
-      ASIO_MOVE_CAST(CompletionToken)(token));
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_DISPATCH_HPP
diff --git a/tools/sdk/include/asio/asio/impl/execution_context.hpp b/tools/sdk/include/asio/asio/impl/execution_context.hpp
deleted file mode 100644
index 3d1e457e74e..00000000000
--- a/tools/sdk/include/asio/asio/impl/execution_context.hpp
+++ /dev/null
@@ -1,107 +0,0 @@
-//
-// impl/execution_context.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_EXECUTION_CONTEXT_HPP
-#define ASIO_IMPL_EXECUTION_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/scoped_ptr.hpp"
-#include "asio/detail/service_registry.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-template <typename Service>
-inline Service& use_service(execution_context& e)
-{
-  // Check that Service meets the necessary type requirements.
-  (void)static_cast<execution_context::service*>(static_cast<Service*>(0));
-
-  return e.service_registry_->template use_service<Service>();
-}
-
-#if !defined(GENERATING_DOCUMENTATION)
-# if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-template <typename Service, typename... Args>
-Service& make_service(execution_context& e, ASIO_MOVE_ARG(Args)... args)
-{
-  detail::scoped_ptr<Service> svc(
-      new Service(e, ASIO_MOVE_CAST(Args)(args)...));
-  e.service_registry_->template add_service<Service>(svc.get());
-  Service& result = *svc;
-  svc.release();
-  return result;
-}
-
-# else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-template <typename Service>
-Service& make_service(execution_context& e)
-{
-  detail::scoped_ptr<Service> svc(new Service(e));
-  e.service_registry_->template add_service<Service>(svc.get());
-  Service& result = *svc;
-  svc.release();
-  return result;
-}
-
-#define ASIO_PRIVATE_MAKE_SERVICE_DEF(n) \
-  template <typename Service, ASIO_VARIADIC_TPARAMS(n)> \
-  Service& make_service(execution_context& e, \
-      ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  { \
-    detail::scoped_ptr<Service> svc( \
-        new Service(e, ASIO_VARIADIC_MOVE_ARGS(n))); \
-    e.service_registry_->template add_service<Service>(svc.get()); \
-    Service& result = *svc; \
-    svc.release(); \
-    return result; \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_MAKE_SERVICE_DEF)
-#undef ASIO_PRIVATE_MAKE_SERVICE_DEF
-
-# endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename Service>
-inline void add_service(execution_context& e, Service* svc)
-{
-  // Check that Service meets the necessary type requirements.
-  (void)static_cast<execution_context::service*>(static_cast<Service*>(0));
-
-  e.service_registry_->template add_service<Service>(svc);
-}
-
-template <typename Service>
-inline bool has_service(execution_context& e)
-{
-  // Check that Service meets the necessary type requirements.
-  (void)static_cast<execution_context::service*>(static_cast<Service*>(0));
-
-  return e.service_registry_->template has_service<Service>();
-}
-
-inline execution_context& execution_context::service::context()
-{
-  return owner_;
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_EXECUTION_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/impl/executor.hpp b/tools/sdk/include/asio/asio/impl/executor.hpp
deleted file mode 100644
index 0fcf5f54a0e..00000000000
--- a/tools/sdk/include/asio/asio/impl/executor.hpp
+++ /dev/null
@@ -1,386 +0,0 @@
-//
-// impl/executor.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_EXECUTOR_HPP
-#define ASIO_IMPL_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/atomic_count.hpp"
-#include "asio/detail/executor_op.hpp"
-#include "asio/detail/global.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/recycling_allocator.hpp"
-#include "asio/executor.hpp"
-#include "asio/system_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-#if defined(ASIO_HAS_MOVE)
-
-// Lightweight, move-only function object wrapper.
-class executor::function
-{
-public:
-  template <typename F, typename Alloc>
-  explicit function(F f, const Alloc& a)
-  {
-    // Allocate and construct an operation to wrap the function.
-    typedef detail::executor_op<F, Alloc> op;
-    typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-    op_ = new (p.v) op(ASIO_MOVE_CAST(F)(f), a);
-    p.v = 0;
-  }
-
-  function(function&& other)
-    : op_(other.op_)
-  {
-    other.op_ = 0;
-  }
-
-  ~function()
-  {
-    if (op_)
-      op_->destroy();
-  }
-
-  void operator()()
-  {
-    if (op_)
-    {
-      detail::scheduler_operation* op = op_;
-      op_ = 0;
-      op->complete(this, asio::error_code(), 0);
-    }
-  }
-
-private:
-  detail::scheduler_operation* op_;
-};
-
-#else // defined(ASIO_HAS_MOVE)
-
-// Not so lightweight, copyable function object wrapper.
-class executor::function
-{
-public:
-  template <typename F, typename Alloc>
-  explicit function(const F& f, const Alloc&)
-    : impl_(new impl<F>(f))
-  {
-  }
-
-  void operator()()
-  {
-    impl_->invoke_(impl_.get());
-  }
-
-private:
-  // Base class for polymorphic function implementations.
-  struct impl_base
-  {
-    void (*invoke_)(impl_base*);
-  };
-
-  // Polymorphic function implementation.
-  template <typename F>
-  struct impl : impl_base
-  {
-    impl(const F& f)
-      : function_(f)
-    {
-      invoke_ = &function::invoke<F>;
-    }
-
-    F function_;
-  };
-
-  // Helper to invoke a function.
-  template <typename F>
-  static void invoke(impl_base* i)
-  {
-    static_cast<impl<F>*>(i)->function_();
-  }
-
-  detail::shared_ptr<impl_base> impl_;
-};
-
-#endif // defined(ASIO_HAS_MOVE)
-
-// Default polymorphic allocator implementation.
-template <typename Executor, typename Allocator>
-class executor::impl
-  : public executor::impl_base
-{
-public:
-  typedef ASIO_REBIND_ALLOC(Allocator, impl) allocator_type;
-
-  static impl_base* create(const Executor& e, Allocator a = Allocator())
-  {
-    raw_mem mem(a);
-    impl* p = new (mem.ptr_) impl(e, a);
-    mem.ptr_ = 0;
-    return p;
-  }
-
-  impl(const Executor& e, const Allocator& a) ASIO_NOEXCEPT
-    : impl_base(false),
-      ref_count_(1),
-      executor_(e),
-      allocator_(a)
-  {
-  }
-
-  impl_base* clone() const ASIO_NOEXCEPT
-  {
-    ++ref_count_;
-    return const_cast<impl_base*>(static_cast<const impl_base*>(this));
-  }
-
-  void destroy() ASIO_NOEXCEPT
-  {
-    if (--ref_count_ == 0)
-    {
-      allocator_type alloc(allocator_);
-      impl* p = this;
-      p->~impl();
-      alloc.deallocate(p, 1);
-    }
-  }
-
-  void on_work_started() ASIO_NOEXCEPT
-  {
-    executor_.on_work_started();
-  }
-
-  void on_work_finished() ASIO_NOEXCEPT
-  {
-    executor_.on_work_finished();
-  }
-
-  execution_context& context() ASIO_NOEXCEPT
-  {
-    return executor_.context();
-  }
-
-  void dispatch(ASIO_MOVE_ARG(function) f)
-  {
-    executor_.dispatch(ASIO_MOVE_CAST(function)(f), allocator_);
-  }
-
-  void post(ASIO_MOVE_ARG(function) f)
-  {
-    executor_.post(ASIO_MOVE_CAST(function)(f), allocator_);
-  }
-
-  void defer(ASIO_MOVE_ARG(function) f)
-  {
-    executor_.defer(ASIO_MOVE_CAST(function)(f), allocator_);
-  }
-
-  type_id_result_type target_type() const ASIO_NOEXCEPT
-  {
-    return type_id<Executor>();
-  }
-
-  void* target() ASIO_NOEXCEPT
-  {
-    return &executor_;
-  }
-
-  const void* target() const ASIO_NOEXCEPT
-  {
-    return &executor_;
-  }
-
-  bool equals(const impl_base* e) const ASIO_NOEXCEPT
-  {
-    if (this == e)
-      return true;
-    if (target_type() != e->target_type())
-      return false;
-    return executor_ == *static_cast<const Executor*>(e->target());
-  }
-
-private:
-  mutable detail::atomic_count ref_count_;
-  Executor executor_;
-  Allocator allocator_;
-
-  struct raw_mem
-  {
-    allocator_type allocator_;
-    impl* ptr_;
-
-    explicit raw_mem(const Allocator& a)
-      : allocator_(a),
-        ptr_(allocator_.allocate(1))
-    {
-    }
-
-    ~raw_mem()
-    {
-      if (ptr_)
-        allocator_.deallocate(ptr_, 1);
-    }
-
-  private:
-    // Disallow copying and assignment.
-    raw_mem(const raw_mem&);
-    raw_mem operator=(const raw_mem&);
-  };
-};
-
-// Polymorphic allocator specialisation for system_executor.
-template <typename Allocator>
-class executor::impl<system_executor, Allocator>
-  : public executor::impl_base
-{
-public:
-  static impl_base* create(const system_executor&,
-      const Allocator& = Allocator())
-  {
-    return &detail::global<impl<system_executor, std::allocator<void> > >();
-  }
-
-  impl()
-    : impl_base(true)
-  {
-  }
-
-  impl_base* clone() const ASIO_NOEXCEPT
-  {
-    return const_cast<impl_base*>(static_cast<const impl_base*>(this));
-  }
-
-  void destroy() ASIO_NOEXCEPT
-  {
-  }
-
-  void on_work_started() ASIO_NOEXCEPT
-  {
-    executor_.on_work_started();
-  }
-
-  void on_work_finished() ASIO_NOEXCEPT
-  {
-    executor_.on_work_finished();
-  }
-
-  execution_context& context() ASIO_NOEXCEPT
-  {
-    return executor_.context();
-  }
-
-  void dispatch(ASIO_MOVE_ARG(function) f)
-  {
-    executor_.dispatch(ASIO_MOVE_CAST(function)(f), allocator_);
-  }
-
-  void post(ASIO_MOVE_ARG(function) f)
-  {
-    executor_.post(ASIO_MOVE_CAST(function)(f), allocator_);
-  }
-
-  void defer(ASIO_MOVE_ARG(function) f)
-  {
-    executor_.defer(ASIO_MOVE_CAST(function)(f), allocator_);
-  }
-
-  type_id_result_type target_type() const ASIO_NOEXCEPT
-  {
-    return type_id<system_executor>();
-  }
-
-  void* target() ASIO_NOEXCEPT
-  {
-    return &executor_;
-  }
-
-  const void* target() const ASIO_NOEXCEPT
-  {
-    return &executor_;
-  }
-
-  bool equals(const impl_base* e) const ASIO_NOEXCEPT
-  {
-    return this == e;
-  }
-
-private:
-  system_executor executor_;
-  Allocator allocator_;
-};
-
-template <typename Executor>
-executor::executor(Executor e)
-  : impl_(impl<Executor, std::allocator<void> >::create(e))
-{
-}
-
-template <typename Executor, typename Allocator>
-executor::executor(allocator_arg_t, const Allocator& a, Executor e)
-  : impl_(impl<Executor, Allocator>::create(e, a))
-{
-}
-
-template <typename Function, typename Allocator>
-void executor::dispatch(ASIO_MOVE_ARG(Function) f,
-    const Allocator& a) const
-{
-  impl_base* i = get_impl();
-  if (i->fast_dispatch_)
-    system_executor().dispatch(ASIO_MOVE_CAST(Function)(f), a);
-  else
-    i->dispatch(function(ASIO_MOVE_CAST(Function)(f), a));
-}
-
-template <typename Function, typename Allocator>
-void executor::post(ASIO_MOVE_ARG(Function) f,
-    const Allocator& a) const
-{
-  get_impl()->post(function(ASIO_MOVE_CAST(Function)(f), a));
-}
-
-template <typename Function, typename Allocator>
-void executor::defer(ASIO_MOVE_ARG(Function) f,
-    const Allocator& a) const
-{
-  get_impl()->defer(function(ASIO_MOVE_CAST(Function)(f), a));
-}
-
-template <typename Executor>
-Executor* executor::target() ASIO_NOEXCEPT
-{
-  return impl_ && impl_->target_type() == type_id<Executor>()
-    ? static_cast<Executor*>(impl_->target()) : 0;
-}
-
-template <typename Executor>
-const Executor* executor::target() const ASIO_NOEXCEPT
-{
-  return impl_ && impl_->target_type() == type_id<Executor>()
-    ? static_cast<Executor*>(impl_->target()) : 0;
-}
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/impl/io_context.hpp b/tools/sdk/include/asio/asio/impl/io_context.hpp
deleted file mode 100644
index eaf580da7fd..00000000000
--- a/tools/sdk/include/asio/asio/impl/io_context.hpp
+++ /dev/null
@@ -1,343 +0,0 @@
-//
-// impl/io_context.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_IO_CONTEXT_HPP
-#define ASIO_IMPL_IO_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/completion_handler.hpp"
-#include "asio/detail/executor_op.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/recycling_allocator.hpp"
-#include "asio/detail/service_registry.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-template <typename Service>
-inline Service& use_service(io_context& ioc)
-{
-  // Check that Service meets the necessary type requirements.
-  (void)static_cast<execution_context::service*>(static_cast<Service*>(0));
-  (void)static_cast<const execution_context::id*>(&Service::id);
-
-  return ioc.service_registry_->template use_service<Service>(ioc);
-}
-
-template <>
-inline detail::io_context_impl& use_service<detail::io_context_impl>(
-    io_context& ioc)
-{
-  return ioc.impl_;
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HAS_IOCP)
-# include "asio/detail/win_iocp_io_context.hpp"
-#else
-# include "asio/detail/scheduler.hpp"
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-inline io_context::executor_type
-io_context::get_executor() ASIO_NOEXCEPT
-{
-  return executor_type(*this);
-}
-
-#if defined(ASIO_HAS_CHRONO)
-
-template <typename Rep, typename Period>
-std::size_t io_context::run_for(
-    const chrono::duration<Rep, Period>& rel_time)
-{
-  return this->run_until(chrono::steady_clock::now() + rel_time);
-}
-
-template <typename Clock, typename Duration>
-std::size_t io_context::run_until(
-    const chrono::time_point<Clock, Duration>& abs_time)
-{
-  std::size_t n = 0;
-  while (this->run_one_until(abs_time))
-    if (n != (std::numeric_limits<std::size_t>::max)())
-      ++n;
-  return n;
-}
-
-template <typename Rep, typename Period>
-std::size_t io_context::run_one_for(
-    const chrono::duration<Rep, Period>& rel_time)
-{
-  return this->run_one_until(chrono::steady_clock::now() + rel_time);
-}
-
-template <typename Clock, typename Duration>
-std::size_t io_context::run_one_until(
-    const chrono::time_point<Clock, Duration>& abs_time)
-{
-  typename Clock::time_point now = Clock::now();
-  while (now < abs_time)
-  {
-    typename Clock::duration rel_time = abs_time - now;
-    if (rel_time > chrono::seconds(1))
-      rel_time = chrono::seconds(1);
-
-    asio::error_code ec;
-    std::size_t s = impl_.wait_one(
-        static_cast<long>(chrono::duration_cast<
-          chrono::microseconds>(rel_time).count()), ec);
-    asio::detail::throw_error(ec);
-
-    if (s || impl_.stopped())
-      return s;
-
-    now = Clock::now();
-  }
-
-  return 0;
-}
-
-#endif // defined(ASIO_HAS_CHRONO)
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-inline void io_context::reset()
-{
-  restart();
-}
-
-template <typename LegacyCompletionHandler>
-ASIO_INITFN_RESULT_TYPE(LegacyCompletionHandler, void ())
-io_context::dispatch(ASIO_MOVE_ARG(LegacyCompletionHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a LegacyCompletionHandler.
-  ASIO_LEGACY_COMPLETION_HANDLER_CHECK(
-      LegacyCompletionHandler, handler) type_check;
-
-  async_completion<LegacyCompletionHandler, void ()> init(handler);
-
-  if (impl_.can_dispatch())
-  {
-    detail::fenced_block b(detail::fenced_block::full);
-    asio_handler_invoke_helpers::invoke(
-        init.completion_handler, init.completion_handler);
-  }
-  else
-  {
-    // Allocate and construct an operation to wrap the handler.
-    typedef detail::completion_handler<
-      typename handler_type<LegacyCompletionHandler, void ()>::type> op;
-    typename op::ptr p = { detail::addressof(init.completion_handler),
-      op::ptr::allocate(init.completion_handler), 0 };
-    p.p = new (p.v) op(init.completion_handler);
-
-    ASIO_HANDLER_CREATION((*this, *p.p,
-          "io_context", this, 0, "dispatch"));
-
-    impl_.do_dispatch(p.p);
-    p.v = p.p = 0;
-  }
-
-  return init.result.get();
-}
-
-template <typename LegacyCompletionHandler>
-ASIO_INITFN_RESULT_TYPE(LegacyCompletionHandler, void ())
-io_context::post(ASIO_MOVE_ARG(LegacyCompletionHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a LegacyCompletionHandler.
-  ASIO_LEGACY_COMPLETION_HANDLER_CHECK(
-      LegacyCompletionHandler, handler) type_check;
-
-  async_completion<LegacyCompletionHandler, void ()> init(handler);
-
-  bool is_continuation =
-    asio_handler_cont_helpers::is_continuation(init.completion_handler);
-
-  // Allocate and construct an operation to wrap the handler.
-  typedef detail::completion_handler<
-    typename handler_type<LegacyCompletionHandler, void ()>::type> op;
-  typename op::ptr p = { detail::addressof(init.completion_handler),
-      op::ptr::allocate(init.completion_handler), 0 };
-  p.p = new (p.v) op(init.completion_handler);
-
-  ASIO_HANDLER_CREATION((*this, *p.p,
-        "io_context", this, 0, "post"));
-
-  impl_.post_immediate_completion(p.p, is_continuation);
-  p.v = p.p = 0;
-
-  return init.result.get();
-}
-
-template <typename Handler>
-#if defined(GENERATING_DOCUMENTATION)
-unspecified
-#else
-inline detail::wrapped_handler<io_context&, Handler>
-#endif
-io_context::wrap(Handler handler)
-{
-  return detail::wrapped_handler<io_context&, Handler>(*this, handler);
-}
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-inline io_context&
-io_context::executor_type::context() const ASIO_NOEXCEPT
-{
-  return io_context_;
-}
-
-inline void
-io_context::executor_type::on_work_started() const ASIO_NOEXCEPT
-{
-  io_context_.impl_.work_started();
-}
-
-inline void
-io_context::executor_type::on_work_finished() const ASIO_NOEXCEPT
-{
-  io_context_.impl_.work_finished();
-}
-
-template <typename Function, typename Allocator>
-void io_context::executor_type::dispatch(
-    ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-{
-  typedef typename decay<Function>::type function_type;
-
-  // Invoke immediately if we are already inside the thread pool.
-  if (io_context_.impl_.can_dispatch())
-  {
-    // Make a local, non-const copy of the function.
-    function_type tmp(ASIO_MOVE_CAST(Function)(f));
-
-    detail::fenced_block b(detail::fenced_block::full);
-    asio_handler_invoke_helpers::invoke(tmp, tmp);
-    return;
-  }
-
-  // Allocate and construct an operation to wrap the function.
-  typedef detail::executor_op<function_type, Allocator, detail::operation> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(f), a);
-
-  ASIO_HANDLER_CREATION((this->context(), *p.p,
-        "io_context", &this->context(), 0, "post"));
-
-  io_context_.impl_.post_immediate_completion(p.p, false);
-  p.v = p.p = 0;
-}
-
-template <typename Function, typename Allocator>
-void io_context::executor_type::post(
-    ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-{
-  typedef typename decay<Function>::type function_type;
-
-  // Allocate and construct an operation to wrap the function.
-  typedef detail::executor_op<function_type, Allocator, detail::operation> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(f), a);
-
-  ASIO_HANDLER_CREATION((this->context(), *p.p,
-        "io_context", &this->context(), 0, "post"));
-
-  io_context_.impl_.post_immediate_completion(p.p, false);
-  p.v = p.p = 0;
-}
-
-template <typename Function, typename Allocator>
-void io_context::executor_type::defer(
-    ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-{
-  typedef typename decay<Function>::type function_type;
-
-  // Allocate and construct an operation to wrap the function.
-  typedef detail::executor_op<function_type, Allocator, detail::operation> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(f), a);
-
-  ASIO_HANDLER_CREATION((this->context(), *p.p,
-        "io_context", &this->context(), 0, "defer"));
-
-  io_context_.impl_.post_immediate_completion(p.p, true);
-  p.v = p.p = 0;
-}
-
-inline bool
-io_context::executor_type::running_in_this_thread() const ASIO_NOEXCEPT
-{
-  return io_context_.impl_.can_dispatch();
-}
-
-#if !defined(ASIO_NO_DEPRECATED)
-inline io_context::work::work(asio::io_context& io_context)
-  : io_context_impl_(io_context.impl_)
-{
-  io_context_impl_.work_started();
-}
-
-inline io_context::work::work(const work& other)
-  : io_context_impl_(other.io_context_impl_)
-{
-  io_context_impl_.work_started();
-}
-
-inline io_context::work::~work()
-{
-  io_context_impl_.work_finished();
-}
-
-inline asio::io_context& io_context::work::get_io_context()
-{
-  return static_cast<asio::io_context&>(io_context_impl_.context());
-}
-
-inline asio::io_context& io_context::work::get_io_service()
-{
-  return static_cast<asio::io_context&>(io_context_impl_.context());
-}
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-inline asio::io_context& io_context::service::get_io_context()
-{
-  return static_cast<asio::io_context&>(context());
-}
-
-#if !defined(ASIO_NO_DEPRECATED)
-inline asio::io_context& io_context::service::get_io_service()
-{
-  return static_cast<asio::io_context&>(context());
-}
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_IO_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/impl/post.hpp b/tools/sdk/include/asio/asio/impl/post.hpp
deleted file mode 100644
index 55389532b48..00000000000
--- a/tools/sdk/include/asio/asio/impl/post.hpp
+++ /dev/null
@@ -1,77 +0,0 @@
-//
-// impl/post.hpp
-// ~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_POST_HPP
-#define ASIO_IMPL_POST_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/detail/work_dispatcher.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-template <typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) post(
-    ASIO_MOVE_ARG(CompletionToken) token)
-{
-  typedef ASIO_HANDLER_TYPE(CompletionToken, void()) handler;
-
-  async_completion<CompletionToken, void()> init(token);
-
-  typename associated_executor<handler>::type ex(
-      (get_associated_executor)(init.completion_handler));
-
-  typename associated_allocator<handler>::type alloc(
-      (get_associated_allocator)(init.completion_handler));
-
-  ex.post(ASIO_MOVE_CAST(handler)(init.completion_handler), alloc);
-
-  return init.result.get();
-}
-
-template <typename Executor, typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) post(
-    const Executor& ex, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_executor<Executor>::value>::type*)
-{
-  typedef ASIO_HANDLER_TYPE(CompletionToken, void()) handler;
-
-  async_completion<CompletionToken, void()> init(token);
-
-  typename associated_allocator<handler>::type alloc(
-      (get_associated_allocator)(init.completion_handler));
-
-  ex.post(detail::work_dispatcher<handler>(init.completion_handler), alloc);
-
-  return init.result.get();
-}
-
-template <typename ExecutionContext, typename CompletionToken>
-inline ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) post(
-    ExecutionContext& ctx, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_convertible<
-      ExecutionContext&, execution_context&>::value>::type*)
-{
-  return (post)(ctx.get_executor(),
-      ASIO_MOVE_CAST(CompletionToken)(token));
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_POST_HPP
diff --git a/tools/sdk/include/asio/asio/impl/read.hpp b/tools/sdk/include/asio/asio/impl/read.hpp
deleted file mode 100644
index 603a7a9b19a..00000000000
--- a/tools/sdk/include/asio/asio/impl/read.hpp
+++ /dev/null
@@ -1,715 +0,0 @@
-//
-// impl/read.hpp
-// ~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_READ_HPP
-#define ASIO_IMPL_READ_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include <algorithm>
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/buffer.hpp"
-#include "asio/completion_condition.hpp"
-#include "asio/detail/array_fwd.hpp"
-#include "asio/detail/base_from_completion_cond.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/consuming_buffers.hpp"
-#include "asio/detail/dependent_type.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail
-{
-  template <typename SyncReadStream, typename MutableBufferSequence,
-      typename MutableBufferIterator, typename CompletionCondition>
-  std::size_t read_buffer_sequence(SyncReadStream& s,
-      const MutableBufferSequence& buffers, const MutableBufferIterator&,
-      CompletionCondition completion_condition, asio::error_code& ec)
-  {
-    ec = asio::error_code();
-    asio::detail::consuming_buffers<mutable_buffer,
-        MutableBufferSequence, MutableBufferIterator> tmp(buffers);
-    while (!tmp.empty())
-    {
-      if (std::size_t max_size = detail::adapt_completion_condition_result(
-            completion_condition(ec, tmp.total_consumed())))
-        tmp.consume(s.read_some(tmp.prepare(max_size), ec));
-      else
-        break;
-    }
-    return tmp.total_consumed();;
-  }
-} // namespace detail
-
-template <typename SyncReadStream, typename MutableBufferSequence,
-    typename CompletionCondition>
-std::size_t read(SyncReadStream& s, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition, asio::error_code& ec,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type*)
-{
-  return detail::read_buffer_sequence(s, buffers,
-      asio::buffer_sequence_begin(buffers), completion_condition, ec);
-}
-
-template <typename SyncReadStream, typename MutableBufferSequence>
-inline std::size_t read(SyncReadStream& s, const MutableBufferSequence& buffers,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type*)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read(s, buffers, transfer_all(), ec);
-  asio::detail::throw_error(ec, "read");
-  return bytes_transferred;
-}
-
-template <typename SyncReadStream, typename MutableBufferSequence>
-inline std::size_t read(SyncReadStream& s, const MutableBufferSequence& buffers,
-    asio::error_code& ec,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type*)
-{
-  return read(s, buffers, transfer_all(), ec);
-}
-
-template <typename SyncReadStream, typename MutableBufferSequence,
-    typename CompletionCondition>
-inline std::size_t read(SyncReadStream& s, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type*)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read(s, buffers, completion_condition, ec);
-  asio::detail::throw_error(ec, "read");
-  return bytes_transferred;
-}
-
-template <typename SyncReadStream, typename DynamicBuffer,
-    typename CompletionCondition>
-std::size_t read(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition, asio::error_code& ec,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  typename decay<DynamicBuffer>::type b(
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers));
-
-  ec = asio::error_code();
-  std::size_t total_transferred = 0;
-  std::size_t max_size = detail::adapt_completion_condition_result(
-        completion_condition(ec, total_transferred));
-  std::size_t bytes_available = std::min<std::size_t>(
-        std::max<std::size_t>(512, b.capacity() - b.size()),
-        std::min<std::size_t>(max_size, b.max_size() - b.size()));
-  while (bytes_available > 0)
-  {
-    std::size_t bytes_transferred = s.read_some(b.prepare(bytes_available), ec);
-    b.commit(bytes_transferred);
-    total_transferred += bytes_transferred;
-    max_size = detail::adapt_completion_condition_result(
-          completion_condition(ec, total_transferred));
-    bytes_available = std::min<std::size_t>(
-          std::max<std::size_t>(512, b.capacity() - b.size()),
-          std::min<std::size_t>(max_size, b.max_size() - b.size()));
-  }
-  return total_transferred;
-}
-
-template <typename SyncReadStream, typename DynamicBuffer>
-inline std::size_t read(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers), transfer_all(), ec);
-  asio::detail::throw_error(ec, "read");
-  return bytes_transferred;
-}
-
-template <typename SyncReadStream, typename DynamicBuffer>
-inline std::size_t read(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    asio::error_code& ec,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  return read(s, ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-      transfer_all(), ec);
-}
-
-template <typename SyncReadStream, typename DynamicBuffer,
-    typename CompletionCondition>
-inline std::size_t read(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-      completion_condition, ec);
-  asio::detail::throw_error(ec, "read");
-  return bytes_transferred;
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-template <typename SyncReadStream, typename Allocator,
-    typename CompletionCondition>
-inline std::size_t read(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition, asio::error_code& ec)
-{
-  return read(s, basic_streambuf_ref<Allocator>(b), completion_condition, ec);
-}
-
-template <typename SyncReadStream, typename Allocator>
-inline std::size_t read(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b)
-{
-  return read(s, basic_streambuf_ref<Allocator>(b));
-}
-
-template <typename SyncReadStream, typename Allocator>
-inline std::size_t read(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    asio::error_code& ec)
-{
-  return read(s, basic_streambuf_ref<Allocator>(b), ec);
-}
-
-template <typename SyncReadStream, typename Allocator,
-    typename CompletionCondition>
-inline std::size_t read(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition)
-{
-  return read(s, basic_streambuf_ref<Allocator>(b), completion_condition);
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-namespace detail
-{
-  template <typename AsyncReadStream, typename MutableBufferSequence,
-      typename MutableBufferIterator, typename CompletionCondition,
-      typename ReadHandler>
-  class read_op
-    : detail::base_from_completion_cond<CompletionCondition>
-  {
-  public:
-    read_op(AsyncReadStream& stream, const MutableBufferSequence& buffers,
-        CompletionCondition completion_condition, ReadHandler& handler)
-      : detail::base_from_completion_cond<
-          CompletionCondition>(completion_condition),
-        stream_(stream),
-        buffers_(buffers),
-        start_(0),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    read_op(const read_op& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        stream_(other.stream_),
-        buffers_(other.buffers_),
-        start_(other.start_),
-        handler_(other.handler_)
-    {
-    }
-
-    read_op(read_op&& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        stream_(other.stream_),
-        buffers_(other.buffers_),
-        start_(other.start_),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      std::size_t max_size;
-      switch (start_ = start)
-      {
-        case 1:
-        max_size = this->check_for_completion(ec, buffers_.total_consumed());
-        do
-        {
-          stream_.async_read_some(buffers_.prepare(max_size),
-              ASIO_MOVE_CAST(read_op)(*this));
-          return; default:
-          buffers_.consume(bytes_transferred);
-          if ((!ec && bytes_transferred == 0) || buffers_.empty())
-            break;
-          max_size = this->check_for_completion(ec, buffers_.total_consumed());
-        } while (max_size > 0);
-
-        handler_(ec, buffers_.total_consumed());
-      }
-    }
-
-  //private:
-    AsyncReadStream& stream_;
-    asio::detail::consuming_buffers<mutable_buffer,
-        MutableBufferSequence, MutableBufferIterator> buffers_;
-    int start_;
-    ReadHandler handler_;
-  };
-
-  template <typename AsyncReadStream, typename MutableBufferSequence,
-      typename MutableBufferIterator, typename CompletionCondition,
-      typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      read_op<AsyncReadStream, MutableBufferSequence, MutableBufferIterator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream, typename MutableBufferSequence,
-      typename MutableBufferIterator, typename CompletionCondition,
-      typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      read_op<AsyncReadStream, MutableBufferSequence, MutableBufferIterator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream, typename MutableBufferSequence,
-      typename MutableBufferIterator, typename CompletionCondition,
-      typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      read_op<AsyncReadStream, MutableBufferSequence, MutableBufferIterator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename MutableBufferSequence, typename MutableBufferIterator,
-      typename CompletionCondition, typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      read_op<AsyncReadStream, MutableBufferSequence, MutableBufferIterator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename MutableBufferSequence, typename MutableBufferIterator,
-      typename CompletionCondition, typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      read_op<AsyncReadStream, MutableBufferSequence, MutableBufferIterator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream, typename MutableBufferSequence,
-      typename MutableBufferIterator, typename CompletionCondition,
-      typename ReadHandler>
-  inline void start_read_buffer_sequence_op(AsyncReadStream& stream,
-      const MutableBufferSequence& buffers, const MutableBufferIterator&,
-      CompletionCondition completion_condition, ReadHandler& handler)
-  {
-    detail::read_op<AsyncReadStream, MutableBufferSequence,
-      MutableBufferIterator, CompletionCondition, ReadHandler>(
-        stream, buffers, completion_condition, handler)(
-          asio::error_code(), 0, 1);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream, typename MutableBufferSequence,
-    typename MutableBufferIterator, typename CompletionCondition,
-    typename ReadHandler, typename Allocator>
-struct associated_allocator<
-    detail::read_op<AsyncReadStream, MutableBufferSequence,
-      MutableBufferIterator, CompletionCondition, ReadHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator>::type type;
-
-  static type get(
-      const detail::read_op<AsyncReadStream, MutableBufferSequence,
-        MutableBufferIterator, CompletionCondition, ReadHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncReadStream, typename MutableBufferSequence,
-    typename MutableBufferIterator, typename CompletionCondition,
-    typename ReadHandler, typename Executor>
-struct associated_executor<
-    detail::read_op<AsyncReadStream, MutableBufferSequence,
-      MutableBufferIterator, CompletionCondition, ReadHandler>,
-    Executor>
-{
-  typedef typename associated_executor<ReadHandler, Executor>::type type;
-
-  static type get(
-      const detail::read_op<AsyncReadStream, MutableBufferSequence,
-        MutableBufferIterator, CompletionCondition, ReadHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream, typename MutableBufferSequence,
-    typename CompletionCondition, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::start_read_buffer_sequence_op(s, buffers,
-      asio::buffer_sequence_begin(buffers), completion_condition,
-      init.completion_handler);
-
-  return init.result.get();
-}
-
-template <typename AsyncReadStream, typename MutableBufferSequence,
-    typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s, const MutableBufferSequence& buffers,
-    ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::start_read_buffer_sequence_op(s, buffers,
-      asio::buffer_sequence_begin(buffers), transfer_all(),
-      init.completion_handler);
-
-  return init.result.get();
-}
-
-namespace detail
-{
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename CompletionCondition, typename ReadHandler>
-  class read_dynbuf_op
-    : detail::base_from_completion_cond<CompletionCondition>
-  {
-  public:
-    template <typename BufferSequence>
-    read_dynbuf_op(AsyncReadStream& stream,
-        ASIO_MOVE_ARG(BufferSequence) buffers,
-        CompletionCondition completion_condition, ReadHandler& handler)
-      : detail::base_from_completion_cond<
-          CompletionCondition>(completion_condition),
-        stream_(stream),
-        buffers_(ASIO_MOVE_CAST(BufferSequence)(buffers)),
-        start_(0),
-        total_transferred_(0),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    read_dynbuf_op(const read_dynbuf_op& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        stream_(other.stream_),
-        buffers_(other.buffers_),
-        start_(other.start_),
-        total_transferred_(other.total_transferred_),
-        handler_(other.handler_)
-    {
-    }
-
-    read_dynbuf_op(read_dynbuf_op&& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        stream_(other.stream_),
-        buffers_(ASIO_MOVE_CAST(DynamicBuffer)(other.buffers_)),
-        start_(other.start_),
-        total_transferred_(other.total_transferred_),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      std::size_t max_size, bytes_available;
-      switch (start_ = start)
-      {
-        case 1:
-        max_size = this->check_for_completion(ec, total_transferred_);
-        bytes_available = std::min<std::size_t>(
-              std::max<std::size_t>(512,
-                buffers_.capacity() - buffers_.size()),
-              std::min<std::size_t>(max_size,
-                buffers_.max_size() - buffers_.size()));
-        for (;;)
-        {
-          stream_.async_read_some(buffers_.prepare(bytes_available),
-              ASIO_MOVE_CAST(read_dynbuf_op)(*this));
-          return; default:
-          total_transferred_ += bytes_transferred;
-          buffers_.commit(bytes_transferred);
-          max_size = this->check_for_completion(ec, total_transferred_);
-          bytes_available = std::min<std::size_t>(
-                std::max<std::size_t>(512,
-                  buffers_.capacity() - buffers_.size()),
-                std::min<std::size_t>(max_size,
-                  buffers_.max_size() - buffers_.size()));
-          if ((!ec && bytes_transferred == 0) || bytes_available == 0)
-            break;
-        }
-
-        handler_(ec, static_cast<const std::size_t&>(total_transferred_));
-      }
-    }
-
-  //private:
-    AsyncReadStream& stream_;
-    DynamicBuffer buffers_;
-    int start_;
-    std::size_t total_transferred_;
-    ReadHandler handler_;
-  };
-
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename CompletionCondition, typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      read_dynbuf_op<AsyncReadStream, DynamicBuffer,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename CompletionCondition, typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      read_dynbuf_op<AsyncReadStream, DynamicBuffer,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename CompletionCondition, typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      read_dynbuf_op<AsyncReadStream, DynamicBuffer,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename CompletionCondition,
-      typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      read_dynbuf_op<AsyncReadStream, DynamicBuffer,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename CompletionCondition,
-      typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      read_dynbuf_op<AsyncReadStream, DynamicBuffer,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename CompletionCondition, typename ReadHandler, typename Allocator>
-struct associated_allocator<
-    detail::read_dynbuf_op<AsyncReadStream,
-      DynamicBuffer, CompletionCondition, ReadHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator>::type type;
-
-  static type get(
-      const detail::read_dynbuf_op<AsyncReadStream,
-        DynamicBuffer, CompletionCondition, ReadHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename CompletionCondition, typename ReadHandler, typename Executor>
-struct associated_executor<
-    detail::read_dynbuf_op<AsyncReadStream,
-      DynamicBuffer, CompletionCondition, ReadHandler>,
-    Executor>
-{
-  typedef typename associated_executor<ReadHandler, Executor>::type type;
-
-  static type get(
-      const detail::read_dynbuf_op<AsyncReadStream,
-        DynamicBuffer, CompletionCondition, ReadHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream,
-    typename DynamicBuffer, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  return async_read(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-      transfer_all(), ASIO_MOVE_CAST(ReadHandler)(handler));
-}
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename CompletionCondition, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::read_dynbuf_op<AsyncReadStream,
-    typename decay<DynamicBuffer>::type,
-      CompletionCondition, ASIO_HANDLER_TYPE(
-        ReadHandler, void (asio::error_code, std::size_t))>(
-          s, ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-            completion_condition, init.completion_handler)(
-              asio::error_code(), 0, 1);
-
-  return init.result.get();
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-template <typename AsyncReadStream, typename Allocator, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s, basic_streambuf<Allocator>& b,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  return async_read(s, basic_streambuf_ref<Allocator>(b),
-      ASIO_MOVE_CAST(ReadHandler)(handler));
-}
-
-template <typename AsyncReadStream, typename Allocator,
-    typename CompletionCondition, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  return async_read(s, basic_streambuf_ref<Allocator>(b),
-      completion_condition, ASIO_MOVE_CAST(ReadHandler)(handler));
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_READ_HPP
diff --git a/tools/sdk/include/asio/asio/impl/read_at.hpp b/tools/sdk/include/asio/asio/impl/read_at.hpp
deleted file mode 100644
index d736d4d3156..00000000000
--- a/tools/sdk/include/asio/asio/impl/read_at.hpp
+++ /dev/null
@@ -1,640 +0,0 @@
-//
-// impl/read_at.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_READ_AT_HPP
-#define ASIO_IMPL_READ_AT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include <algorithm>
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/buffer.hpp"
-#include "asio/completion_condition.hpp"
-#include "asio/detail/array_fwd.hpp"
-#include "asio/detail/base_from_completion_cond.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/consuming_buffers.hpp"
-#include "asio/detail/dependent_type.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail
-{
-  template <typename SyncRandomAccessReadDevice, typename MutableBufferSequence,
-      typename MutableBufferIterator, typename CompletionCondition>
-  std::size_t read_at_buffer_sequence(SyncRandomAccessReadDevice& d,
-      uint64_t offset, const MutableBufferSequence& buffers,
-      const MutableBufferIterator&, CompletionCondition completion_condition,
-      asio::error_code& ec)
-  {
-    ec = asio::error_code();
-    asio::detail::consuming_buffers<mutable_buffer,
-        MutableBufferSequence, MutableBufferIterator> tmp(buffers);
-    while (!tmp.empty())
-    {
-      if (std::size_t max_size = detail::adapt_completion_condition_result(
-            completion_condition(ec, tmp.total_consumed())))
-      {
-        tmp.consume(d.read_some_at(offset + tmp.total_consumed(),
-              tmp.prepare(max_size), ec));
-      }
-      else
-        break;
-    }
-    return tmp.total_consumed();;
-  }
-} // namespace detail
-
-template <typename SyncRandomAccessReadDevice, typename MutableBufferSequence,
-    typename CompletionCondition>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition, asio::error_code& ec)
-{
-  return detail::read_at_buffer_sequence(d, offset, buffers,
-      asio::buffer_sequence_begin(buffers), completion_condition, ec);
-}
-
-template <typename SyncRandomAccessReadDevice, typename MutableBufferSequence>
-inline std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read_at(
-      d, offset, buffers, transfer_all(), ec);
-  asio::detail::throw_error(ec, "read_at");
-  return bytes_transferred;
-}
-
-template <typename SyncRandomAccessReadDevice, typename MutableBufferSequence>
-inline std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers,
-    asio::error_code& ec)
-{
-  return read_at(d, offset, buffers, transfer_all(), ec);
-}
-
-template <typename SyncRandomAccessReadDevice, typename MutableBufferSequence,
-    typename CompletionCondition>
-inline std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read_at(
-      d, offset, buffers, completion_condition, ec);
-  asio::detail::throw_error(ec, "read_at");
-  return bytes_transferred;
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-template <typename SyncRandomAccessReadDevice, typename Allocator,
-    typename CompletionCondition>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition, asio::error_code& ec)
-{
-  ec = asio::error_code();
-  std::size_t total_transferred = 0;
-  std::size_t max_size = detail::adapt_completion_condition_result(
-        completion_condition(ec, total_transferred));
-  std::size_t bytes_available = read_size_helper(b, max_size);
-  while (bytes_available > 0)
-  {
-    std::size_t bytes_transferred = d.read_some_at(
-        offset + total_transferred, b.prepare(bytes_available), ec);
-    b.commit(bytes_transferred);
-    total_transferred += bytes_transferred;
-    max_size = detail::adapt_completion_condition_result(
-          completion_condition(ec, total_transferred));
-    bytes_available = read_size_helper(b, max_size);
-  }
-  return total_transferred;
-}
-
-template <typename SyncRandomAccessReadDevice, typename Allocator>
-inline std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read_at(
-      d, offset, b, transfer_all(), ec);
-  asio::detail::throw_error(ec, "read_at");
-  return bytes_transferred;
-}
-
-template <typename SyncRandomAccessReadDevice, typename Allocator>
-inline std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    asio::error_code& ec)
-{
-  return read_at(d, offset, b, transfer_all(), ec);
-}
-
-template <typename SyncRandomAccessReadDevice, typename Allocator,
-    typename CompletionCondition>
-inline std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read_at(
-      d, offset, b, completion_condition, ec);
-  asio::detail::throw_error(ec, "read_at");
-  return bytes_transferred;
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-namespace detail
-{
-  template <typename AsyncRandomAccessReadDevice,
-      typename MutableBufferSequence, typename MutableBufferIterator,
-      typename CompletionCondition, typename ReadHandler>
-  class read_at_op
-    : detail::base_from_completion_cond<CompletionCondition>
-  {
-  public:
-    read_at_op(AsyncRandomAccessReadDevice& device,
-        uint64_t offset, const MutableBufferSequence& buffers,
-        CompletionCondition completion_condition, ReadHandler& handler)
-      : detail::base_from_completion_cond<
-          CompletionCondition>(completion_condition),
-        device_(device),
-        offset_(offset),
-        buffers_(buffers),
-        start_(0),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    read_at_op(const read_at_op& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        device_(other.device_),
-        offset_(other.offset_),
-        buffers_(other.buffers_),
-        start_(other.start_),
-        handler_(other.handler_)
-    {
-    }
-
-    read_at_op(read_at_op&& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        device_(other.device_),
-        offset_(other.offset_),
-        buffers_(other.buffers_),
-        start_(other.start_),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      std::size_t max_size;
-      switch (start_ = start)
-      {
-        case 1:
-        max_size = this->check_for_completion(ec, buffers_.total_consumed());
-        do
-        {
-          device_.async_read_some_at(
-              offset_ + buffers_.total_consumed(), buffers_.prepare(max_size),
-              ASIO_MOVE_CAST(read_at_op)(*this));
-          return; default:
-          buffers_.consume(bytes_transferred);
-          if ((!ec && bytes_transferred == 0) || buffers_.empty())
-            break;
-          max_size = this->check_for_completion(ec, buffers_.total_consumed());
-        } while (max_size > 0);
-
-        handler_(ec, buffers_.total_consumed());
-      }
-    }
-
-  //private:
-    AsyncRandomAccessReadDevice& device_;
-    uint64_t offset_;
-    asio::detail::consuming_buffers<mutable_buffer,
-        MutableBufferSequence, MutableBufferIterator> buffers_;
-    int start_;
-    ReadHandler handler_;
-  };
-
-  template <typename AsyncRandomAccessReadDevice,
-      typename MutableBufferSequence, typename MutableBufferIterator,
-      typename CompletionCondition, typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      read_at_op<AsyncRandomAccessReadDevice, MutableBufferSequence,
-        MutableBufferIterator, CompletionCondition, ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncRandomAccessReadDevice,
-      typename MutableBufferSequence, typename MutableBufferIterator,
-      typename CompletionCondition, typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      read_at_op<AsyncRandomAccessReadDevice, MutableBufferSequence,
-        MutableBufferIterator, CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncRandomAccessReadDevice,
-      typename MutableBufferSequence, typename MutableBufferIterator,
-      typename CompletionCondition, typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      read_at_op<AsyncRandomAccessReadDevice, MutableBufferSequence,
-        MutableBufferIterator, CompletionCondition, ReadHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncRandomAccessReadDevice,
-      typename MutableBufferSequence, typename MutableBufferIterator,
-      typename CompletionCondition, typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      read_at_op<AsyncRandomAccessReadDevice, MutableBufferSequence,
-        MutableBufferIterator, CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncRandomAccessReadDevice,
-      typename MutableBufferSequence, typename MutableBufferIterator,
-      typename CompletionCondition, typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      read_at_op<AsyncRandomAccessReadDevice, MutableBufferSequence,
-        MutableBufferIterator, CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename AsyncRandomAccessReadDevice,
-      typename MutableBufferSequence, typename MutableBufferIterator,
-      typename CompletionCondition, typename ReadHandler>
-  inline void start_read_at_buffer_sequence_op(AsyncRandomAccessReadDevice& d,
-      uint64_t offset, const MutableBufferSequence& buffers,
-      const MutableBufferIterator&, CompletionCondition completion_condition,
-      ReadHandler& handler)
-  {
-    detail::read_at_op<AsyncRandomAccessReadDevice, MutableBufferSequence,
-      MutableBufferIterator, CompletionCondition, ReadHandler>(
-        d, offset, buffers, completion_condition, handler)(
-          asio::error_code(), 0, 1);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncRandomAccessReadDevice,
-    typename MutableBufferSequence, typename MutableBufferIterator,
-    typename CompletionCondition, typename ReadHandler, typename Allocator>
-struct associated_allocator<
-    detail::read_at_op<AsyncRandomAccessReadDevice, MutableBufferSequence,
-    MutableBufferIterator, CompletionCondition, ReadHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator>::type type;
-
-  static type get(
-      const detail::read_at_op<AsyncRandomAccessReadDevice,
-      MutableBufferSequence, MutableBufferIterator,
-      CompletionCondition, ReadHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncRandomAccessReadDevice,
-    typename MutableBufferSequence, typename MutableBufferIterator,
-    typename CompletionCondition, typename ReadHandler, typename Executor>
-struct associated_executor<
-    detail::read_at_op<AsyncRandomAccessReadDevice, MutableBufferSequence,
-    MutableBufferIterator, CompletionCondition, ReadHandler>,
-    Executor>
-{
-  typedef typename associated_executor<ReadHandler, Executor>::type type;
-
-  static type get(
-      const detail::read_at_op<AsyncRandomAccessReadDevice,
-      MutableBufferSequence, MutableBufferIterator,
-      CompletionCondition, ReadHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncRandomAccessReadDevice, typename MutableBufferSequence,
-    typename CompletionCondition, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_at(AsyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::start_read_at_buffer_sequence_op(d, offset, buffers,
-      asio::buffer_sequence_begin(buffers), completion_condition,
-      init.completion_handler);
-
-  return init.result.get();
-}
-
-template <typename AsyncRandomAccessReadDevice, typename MutableBufferSequence,
-    typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_at(AsyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::start_read_at_buffer_sequence_op(d, offset, buffers,
-      asio::buffer_sequence_begin(buffers), transfer_all(),
-      init.completion_handler);
-
-  return init.result.get();
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-namespace detail
-{
-  template <typename AsyncRandomAccessReadDevice, typename Allocator,
-      typename CompletionCondition, typename ReadHandler>
-  class read_at_streambuf_op
-    : detail::base_from_completion_cond<CompletionCondition>
-  {
-  public:
-    read_at_streambuf_op(AsyncRandomAccessReadDevice& device,
-        uint64_t offset, basic_streambuf<Allocator>& streambuf,
-        CompletionCondition completion_condition, ReadHandler& handler)
-      : detail::base_from_completion_cond<
-          CompletionCondition>(completion_condition),
-        device_(device),
-        offset_(offset),
-        streambuf_(streambuf),
-        start_(0),
-        total_transferred_(0),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    read_at_streambuf_op(const read_at_streambuf_op& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        device_(other.device_),
-        offset_(other.offset_),
-        streambuf_(other.streambuf_),
-        start_(other.start_),
-        total_transferred_(other.total_transferred_),
-        handler_(other.handler_)
-    {
-    }
-
-    read_at_streambuf_op(read_at_streambuf_op&& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        device_(other.device_),
-        offset_(other.offset_),
-        streambuf_(other.streambuf_),
-        start_(other.start_),
-        total_transferred_(other.total_transferred_),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      std::size_t max_size, bytes_available;
-      switch (start_ = start)
-      {
-        case 1:
-        max_size = this->check_for_completion(ec, total_transferred_);
-        bytes_available = read_size_helper(streambuf_, max_size);
-        for (;;)
-        {
-          device_.async_read_some_at(offset_ + total_transferred_,
-              streambuf_.prepare(bytes_available),
-              ASIO_MOVE_CAST(read_at_streambuf_op)(*this));
-          return; default:
-          total_transferred_ += bytes_transferred;
-          streambuf_.commit(bytes_transferred);
-          max_size = this->check_for_completion(ec, total_transferred_);
-          bytes_available = read_size_helper(streambuf_, max_size);
-          if ((!ec && bytes_transferred == 0) || bytes_available == 0)
-            break;
-        }
-
-        handler_(ec, static_cast<const std::size_t&>(total_transferred_));
-      }
-    }
-
-  //private:
-    AsyncRandomAccessReadDevice& device_;
-    uint64_t offset_;
-    asio::basic_streambuf<Allocator>& streambuf_;
-    int start_;
-    std::size_t total_transferred_;
-    ReadHandler handler_;
-  };
-
-  template <typename AsyncRandomAccessReadDevice, typename Allocator,
-      typename CompletionCondition, typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      read_at_streambuf_op<AsyncRandomAccessReadDevice, Allocator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncRandomAccessReadDevice, typename Allocator,
-      typename CompletionCondition, typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      read_at_streambuf_op<AsyncRandomAccessReadDevice, Allocator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncRandomAccessReadDevice, typename Allocator,
-      typename CompletionCondition, typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      read_at_streambuf_op<AsyncRandomAccessReadDevice, Allocator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncRandomAccessReadDevice,
-      typename Allocator, typename CompletionCondition, typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      read_at_streambuf_op<AsyncRandomAccessReadDevice, Allocator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncRandomAccessReadDevice,
-      typename Allocator, typename CompletionCondition, typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      read_at_streambuf_op<AsyncRandomAccessReadDevice, Allocator,
-        CompletionCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncRandomAccessReadDevice, typename Allocator,
-    typename CompletionCondition, typename ReadHandler, typename Allocator1>
-struct associated_allocator<
-    detail::read_at_streambuf_op<AsyncRandomAccessReadDevice,
-      Allocator, CompletionCondition, ReadHandler>,
-    Allocator1>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator1>::type type;
-
-  static type get(
-      const detail::read_at_streambuf_op<AsyncRandomAccessReadDevice,
-        Allocator, CompletionCondition, ReadHandler>& h,
-      const Allocator1& a = Allocator1()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator1>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncRandomAccessReadDevice, typename Executor,
-    typename CompletionCondition, typename ReadHandler, typename Executor1>
-struct associated_executor<
-    detail::read_at_streambuf_op<AsyncRandomAccessReadDevice,
-      Executor, CompletionCondition, ReadHandler>,
-    Executor1>
-{
-  typedef typename associated_executor<ReadHandler, Executor1>::type type;
-
-  static type get(
-      const detail::read_at_streambuf_op<AsyncRandomAccessReadDevice,
-        Executor, CompletionCondition, ReadHandler>& h,
-      const Executor1& ex = Executor1()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor1>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncRandomAccessReadDevice, typename Allocator,
-    typename CompletionCondition, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_at(AsyncRandomAccessReadDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::read_at_streambuf_op<AsyncRandomAccessReadDevice, Allocator,
-    CompletionCondition, ASIO_HANDLER_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))>(
-        d, offset, b, completion_condition, init.completion_handler)(
-          asio::error_code(), 0, 1);
-
-  return init.result.get();
-}
-
-template <typename AsyncRandomAccessReadDevice, typename Allocator,
-    typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_at(AsyncRandomAccessReadDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::read_at_streambuf_op<AsyncRandomAccessReadDevice, Allocator,
-    detail::transfer_all_t, ASIO_HANDLER_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))>(
-        d, offset, b, transfer_all(), init.completion_handler)(
-          asio::error_code(), 0, 1);
-
-  return init.result.get();
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_READ_AT_HPP
diff --git a/tools/sdk/include/asio/asio/impl/read_until.hpp b/tools/sdk/include/asio/asio/impl/read_until.hpp
deleted file mode 100644
index 1f39e1933b5..00000000000
--- a/tools/sdk/include/asio/asio/impl/read_until.hpp
+++ /dev/null
@@ -1,1500 +0,0 @@
-//
-// impl/read_until.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_READ_UNTIL_HPP
-#define ASIO_IMPL_READ_UNTIL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include <algorithm>
-#include <string>
-#include <vector>
-#include <utility>
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/buffer.hpp"
-#include "asio/buffers_iterator.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/limits.hpp"
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-template <typename SyncReadStream, typename DynamicBuffer>
-inline std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers, char delim)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read_until(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers), delim, ec);
-  asio::detail::throw_error(ec, "read_until");
-  return bytes_transferred;
-}
-
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    char delim, asio::error_code& ec)
-{
-  typename decay<DynamicBuffer>::type b(
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers));
-
-  std::size_t search_position = 0;
-  for (;;)
-  {
-    // Determine the range of the data to be searched.
-    typedef typename DynamicBuffer::const_buffers_type buffers_type;
-    typedef buffers_iterator<buffers_type> iterator;
-    buffers_type data_buffers = b.data();
-    iterator begin = iterator::begin(data_buffers);
-    iterator start_pos = begin + search_position;
-    iterator end = iterator::end(data_buffers);
-
-    // Look for a match.
-    iterator iter = std::find(start_pos, end, delim);
-    if (iter != end)
-    {
-      // Found a match. We're done.
-      ec = asio::error_code();
-      return iter - begin + 1;
-    }
-    else
-    {
-      // No match. Next search can start with the new data.
-      search_position = end - begin;
-    }
-
-    // Check if buffer is full.
-    if (b.size() == b.max_size())
-    {
-      ec = error::not_found;
-      return 0;
-    }
-
-    // Need more data.
-    std::size_t bytes_to_read = std::min<std::size_t>(
-          std::max<std::size_t>(512, b.capacity() - b.size()),
-          std::min<std::size_t>(65536, b.max_size() - b.size()));
-    b.commit(s.read_some(b.prepare(bytes_to_read), ec));
-    if (ec)
-      return 0;
-  }
-}
-
-template <typename SyncReadStream, typename DynamicBuffer>
-inline std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_STRING_VIEW_PARAM delim)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read_until(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers), delim, ec);
-  asio::detail::throw_error(ec, "read_until");
-  return bytes_transferred;
-}
-
-namespace detail
-{
-  // Algorithm that finds a subsequence of equal values in a sequence. Returns
-  // (iterator,true) if a full match was found, in which case the iterator
-  // points to the beginning of the match. Returns (iterator,false) if a
-  // partial match was found at the end of the first sequence, in which case
-  // the iterator points to the beginning of the partial match. Returns
-  // (last1,false) if no full or partial match was found.
-  template <typename Iterator1, typename Iterator2>
-  std::pair<Iterator1, bool> partial_search(
-      Iterator1 first1, Iterator1 last1, Iterator2 first2, Iterator2 last2)
-  {
-    for (Iterator1 iter1 = first1; iter1 != last1; ++iter1)
-    {
-      Iterator1 test_iter1 = iter1;
-      Iterator2 test_iter2 = first2;
-      for (;; ++test_iter1, ++test_iter2)
-      {
-        if (test_iter2 == last2)
-          return std::make_pair(iter1, true);
-        if (test_iter1 == last1)
-        {
-          if (test_iter2 != first2)
-            return std::make_pair(iter1, false);
-          else
-            break;
-        }
-        if (*test_iter1 != *test_iter2)
-          break;
-      }
-    }
-    return std::make_pair(last1, false);
-  }
-} // namespace detail
-
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_STRING_VIEW_PARAM delim, asio::error_code& ec)
-{
-  typename decay<DynamicBuffer>::type b(
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers));
-
-  std::size_t search_position = 0;
-  for (;;)
-  {
-    // Determine the range of the data to be searched.
-    typedef typename DynamicBuffer::const_buffers_type buffers_type;
-    typedef buffers_iterator<buffers_type> iterator;
-    buffers_type data_buffers = b.data();
-    iterator begin = iterator::begin(data_buffers);
-    iterator start_pos = begin + search_position;
-    iterator end = iterator::end(data_buffers);
-
-    // Look for a match.
-    std::pair<iterator, bool> result = detail::partial_search(
-        start_pos, end, delim.begin(), delim.end());
-    if (result.first != end)
-    {
-      if (result.second)
-      {
-        // Full match. We're done.
-        ec = asio::error_code();
-        return result.first - begin + delim.length();
-      }
-      else
-      {
-        // Partial match. Next search needs to start from beginning of match.
-        search_position = result.first - begin;
-      }
-    }
-    else
-    {
-      // No match. Next search can start with the new data.
-      search_position = end - begin;
-    }
-
-    // Check if buffer is full.
-    if (b.size() == b.max_size())
-    {
-      ec = error::not_found;
-      return 0;
-    }
-
-    // Need more data.
-    std::size_t bytes_to_read = std::min<std::size_t>(
-          std::max<std::size_t>(512, b.capacity() - b.size()),
-          std::min<std::size_t>(65536, b.max_size() - b.size()));
-    b.commit(s.read_some(b.prepare(bytes_to_read), ec));
-    if (ec)
-      return 0;
-  }
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if defined(ASIO_HAS_BOOST_REGEX)
-
-template <typename SyncReadStream, typename DynamicBuffer>
-inline std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    const boost::regex& expr)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read_until(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers), expr, ec);
-  asio::detail::throw_error(ec, "read_until");
-  return bytes_transferred;
-}
-
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    const boost::regex& expr, asio::error_code& ec)
-{
-  typename decay<DynamicBuffer>::type b(
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers));
-
-  std::size_t search_position = 0;
-  for (;;)
-  {
-    // Determine the range of the data to be searched.
-    typedef typename DynamicBuffer::const_buffers_type buffers_type;
-    typedef buffers_iterator<buffers_type> iterator;
-    buffers_type data_buffers = b.data();
-    iterator begin = iterator::begin(data_buffers);
-    iterator start_pos = begin + search_position;
-    iterator end = iterator::end(data_buffers);
-
-    // Look for a match.
-    boost::match_results<iterator,
-      typename std::vector<boost::sub_match<iterator> >::allocator_type>
-        match_results;
-    if (regex_search(start_pos, end, match_results, expr,
-          boost::match_default | boost::match_partial))
-    {
-      if (match_results[0].matched)
-      {
-        // Full match. We're done.
-        ec = asio::error_code();
-        return match_results[0].second - begin;
-      }
-      else
-      {
-        // Partial match. Next search needs to start from beginning of match.
-        search_position = match_results[0].first - begin;
-      }
-    }
-    else
-    {
-      // No match. Next search can start with the new data.
-      search_position = end - begin;
-    }
-
-    // Check if buffer is full.
-    if (b.size() == b.max_size())
-    {
-      ec = error::not_found;
-      return 0;
-    }
-
-    // Need more data.
-    std::size_t bytes_to_read = read_size_helper(b, 65536);
-    b.commit(s.read_some(b.prepare(bytes_to_read), ec));
-    if (ec)
-      return 0;
-  }
-}
-
-#endif // defined(ASIO_HAS_BOOST_REGEX)
-
-template <typename SyncReadStream,
-    typename DynamicBuffer, typename MatchCondition>
-inline std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    MatchCondition match_condition,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type*)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = read_until(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-      match_condition, ec);
-  asio::detail::throw_error(ec, "read_until");
-  return bytes_transferred;
-}
-
-template <typename SyncReadStream,
-    typename DynamicBuffer, typename MatchCondition>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    MatchCondition match_condition, asio::error_code& ec,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type*)
-{
-  typename decay<DynamicBuffer>::type b(
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers));
-
-  std::size_t search_position = 0;
-  for (;;)
-  {
-    // Determine the range of the data to be searched.
-    typedef typename DynamicBuffer::const_buffers_type buffers_type;
-    typedef buffers_iterator<buffers_type> iterator;
-    buffers_type data_buffers = b.data();
-    iterator begin = iterator::begin(data_buffers);
-    iterator start_pos = begin + search_position;
-    iterator end = iterator::end(data_buffers);
-
-    // Look for a match.
-    std::pair<iterator, bool> result = match_condition(start_pos, end);
-    if (result.second)
-    {
-      // Full match. We're done.
-      ec = asio::error_code();
-      return result.first - begin;
-    }
-    else if (result.first != end)
-    {
-      // Partial match. Next search needs to start from beginning of match.
-      search_position = result.first - begin;
-    }
-    else
-    {
-      // No match. Next search can start with the new data.
-      search_position = end - begin;
-    }
-
-    // Check if buffer is full.
-    if (b.size() == b.max_size())
-    {
-      ec = error::not_found;
-      return 0;
-    }
-
-    // Need more data.
-    std::size_t bytes_to_read = std::min<std::size_t>(
-          std::max<std::size_t>(512, b.capacity() - b.size()),
-          std::min<std::size_t>(65536, b.max_size() - b.size()));
-    b.commit(s.read_some(b.prepare(bytes_to_read), ec));
-    if (ec)
-      return 0;
-  }
-}
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-template <typename SyncReadStream, typename Allocator>
-inline std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, char delim)
-{
-  return read_until(s, basic_streambuf_ref<Allocator>(b), delim);
-}
-
-template <typename SyncReadStream, typename Allocator>
-inline std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, char delim,
-    asio::error_code& ec)
-{
-  return read_until(s, basic_streambuf_ref<Allocator>(b), delim, ec);
-}
-
-template <typename SyncReadStream, typename Allocator>
-inline std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    ASIO_STRING_VIEW_PARAM delim)
-{
-  return read_until(s, basic_streambuf_ref<Allocator>(b), delim);
-}
-
-template <typename SyncReadStream, typename Allocator>
-inline std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    ASIO_STRING_VIEW_PARAM delim, asio::error_code& ec)
-{
-  return read_until(s, basic_streambuf_ref<Allocator>(b), delim, ec);
-}
-
-#if defined(ASIO_HAS_BOOST_REGEX)
-
-template <typename SyncReadStream, typename Allocator>
-inline std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, const boost::regex& expr)
-{
-  return read_until(s, basic_streambuf_ref<Allocator>(b), expr);
-}
-
-template <typename SyncReadStream, typename Allocator>
-inline std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, const boost::regex& expr,
-    asio::error_code& ec)
-{
-  return read_until(s, basic_streambuf_ref<Allocator>(b), expr, ec);
-}
-
-#endif // defined(ASIO_HAS_BOOST_REGEX)
-
-template <typename SyncReadStream, typename Allocator, typename MatchCondition>
-inline std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, MatchCondition match_condition,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type*)
-{
-  return read_until(s, basic_streambuf_ref<Allocator>(b), match_condition);
-}
-
-template <typename SyncReadStream, typename Allocator, typename MatchCondition>
-inline std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    MatchCondition match_condition, asio::error_code& ec,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type*)
-{
-  return read_until(s, basic_streambuf_ref<Allocator>(b), match_condition, ec);
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-namespace detail
-{
-  template <typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  class read_until_delim_op
-  {
-  public:
-    template <typename BufferSequence>
-    read_until_delim_op(AsyncReadStream& stream,
-        ASIO_MOVE_ARG(BufferSequence) buffers,
-        char delim, ReadHandler& handler)
-      : stream_(stream),
-        buffers_(ASIO_MOVE_CAST(BufferSequence)(buffers)),
-        delim_(delim),
-        start_(0),
-        search_position_(0),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    read_until_delim_op(const read_until_delim_op& other)
-      : stream_(other.stream_),
-        buffers_(other.buffers_),
-        delim_(other.delim_),
-        start_(other.start_),
-        search_position_(other.search_position_),
-        handler_(other.handler_)
-    {
-    }
-
-    read_until_delim_op(read_until_delim_op&& other)
-      : stream_(other.stream_),
-        buffers_(ASIO_MOVE_CAST(DynamicBuffer)(other.buffers_)),
-        delim_(other.delim_),
-        start_(other.start_),
-        search_position_(other.search_position_),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      const std::size_t not_found = (std::numeric_limits<std::size_t>::max)();
-      std::size_t bytes_to_read;
-      switch (start_ = start)
-      {
-      case 1:
-        for (;;)
-        {
-          {
-            // Determine the range of the data to be searched.
-            typedef typename DynamicBuffer::const_buffers_type
-              buffers_type;
-            typedef buffers_iterator<buffers_type> iterator;
-            buffers_type data_buffers = buffers_.data();
-            iterator begin = iterator::begin(data_buffers);
-            iterator start_pos = begin + search_position_;
-            iterator end = iterator::end(data_buffers);
-
-            // Look for a match.
-            iterator iter = std::find(start_pos, end, delim_);
-            if (iter != end)
-            {
-              // Found a match. We're done.
-              search_position_ = iter - begin + 1;
-              bytes_to_read = 0;
-            }
-
-            // No match yet. Check if buffer is full.
-            else if (buffers_.size() == buffers_.max_size())
-            {
-              search_position_ = not_found;
-              bytes_to_read = 0;
-            }
-
-            // Need to read some more data.
-            else
-            {
-              // Next search can start with the new data.
-              search_position_ = end - begin;
-              bytes_to_read = std::min<std::size_t>(
-                    std::max<std::size_t>(512,
-                      buffers_.capacity() - buffers_.size()),
-                    std::min<std::size_t>(65536,
-                      buffers_.max_size() - buffers_.size()));
-            }
-          }
-
-          // Check if we're done.
-          if (!start && bytes_to_read == 0)
-            break;
-
-          // Start a new asynchronous read operation to obtain more data.
-          stream_.async_read_some(buffers_.prepare(bytes_to_read),
-              ASIO_MOVE_CAST(read_until_delim_op)(*this));
-          return; default:
-          buffers_.commit(bytes_transferred);
-          if (ec || bytes_transferred == 0)
-            break;
-        }
-
-        const asio::error_code result_ec =
-          (search_position_ == not_found)
-          ? error::not_found : ec;
-
-        const std::size_t result_n =
-          (ec || search_position_ == not_found)
-          ? 0 : search_position_;
-
-        handler_(result_ec, result_n);
-      }
-    }
-
-  //private:
-    AsyncReadStream& stream_;
-    DynamicBuffer buffers_;
-    char delim_;
-    int start_;
-    std::size_t search_position_;
-    ReadHandler handler_;
-  };
-
-  template <typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      read_until_delim_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      read_until_delim_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      read_until_delim_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      read_until_delim_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      read_until_delim_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename ReadHandler, typename Allocator>
-struct associated_allocator<
-    detail::read_until_delim_op<AsyncReadStream,
-      DynamicBuffer, ReadHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator>::type type;
-
-  static type get(
-      const detail::read_until_delim_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename ReadHandler, typename Executor>
-struct associated_executor<
-    detail::read_until_delim_op<AsyncReadStream,
-      DynamicBuffer, ReadHandler>,
-    Executor>
-{
-  typedef typename associated_executor<ReadHandler, Executor>::type type;
-
-  static type get(
-      const detail::read_until_delim_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream,
-    typename DynamicBuffer, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    char delim, ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::read_until_delim_op<AsyncReadStream,
-    typename decay<DynamicBuffer>::type,
-      ASIO_HANDLER_TYPE(ReadHandler,
-        void (asio::error_code, std::size_t))>(
-          s, ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-            delim, init.completion_handler)(asio::error_code(), 0, 1);
-
-  return init.result.get();
-}
-
-namespace detail
-{
-  template <typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  class read_until_delim_string_op
-  {
-  public:
-    template <typename BufferSequence>
-    read_until_delim_string_op(AsyncReadStream& stream,
-        ASIO_MOVE_ARG(BufferSequence) buffers,
-        const std::string& delim, ReadHandler& handler)
-      : stream_(stream),
-        buffers_(ASIO_MOVE_CAST(BufferSequence)(buffers)),
-        delim_(delim),
-        start_(0),
-        search_position_(0),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    read_until_delim_string_op(const read_until_delim_string_op& other)
-      : stream_(other.stream_),
-        buffers_(other.buffers_),
-        delim_(other.delim_),
-        start_(other.start_),
-        search_position_(other.search_position_),
-        handler_(other.handler_)
-    {
-    }
-
-    read_until_delim_string_op(read_until_delim_string_op&& other)
-      : stream_(other.stream_),
-        buffers_(ASIO_MOVE_CAST(DynamicBuffer)(other.buffers_)),
-        delim_(ASIO_MOVE_CAST(std::string)(other.delim_)),
-        start_(other.start_),
-        search_position_(other.search_position_),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      const std::size_t not_found = (std::numeric_limits<std::size_t>::max)();
-      std::size_t bytes_to_read;
-      switch (start_ = start)
-      {
-      case 1:
-        for (;;)
-        {
-          {
-            // Determine the range of the data to be searched.
-            typedef typename DynamicBuffer::const_buffers_type
-              buffers_type;
-            typedef buffers_iterator<buffers_type> iterator;
-            buffers_type data_buffers = buffers_.data();
-            iterator begin = iterator::begin(data_buffers);
-            iterator start_pos = begin + search_position_;
-            iterator end = iterator::end(data_buffers);
-
-            // Look for a match.
-            std::pair<iterator, bool> result = detail::partial_search(
-                start_pos, end, delim_.begin(), delim_.end());
-            if (result.first != end && result.second)
-            {
-              // Full match. We're done.
-              search_position_ = result.first - begin + delim_.length();
-              bytes_to_read = 0;
-            }
-
-            // No match yet. Check if buffer is full.
-            else if (buffers_.size() == buffers_.max_size())
-            {
-              search_position_ = not_found;
-              bytes_to_read = 0;
-            }
-
-            // Need to read some more data.
-            else
-            {
-              if (result.first != end)
-              {
-                // Partial match. Next search needs to start from beginning of
-                // match.
-                search_position_ = result.first - begin;
-              }
-              else
-              {
-                // Next search can start with the new data.
-                search_position_ = end - begin;
-              }
-
-              bytes_to_read = std::min<std::size_t>(
-                    std::max<std::size_t>(512,
-                      buffers_.capacity() - buffers_.size()),
-                    std::min<std::size_t>(65536,
-                      buffers_.max_size() - buffers_.size()));
-            }
-          }
-
-          // Check if we're done.
-          if (!start && bytes_to_read == 0)
-            break;
-
-          // Start a new asynchronous read operation to obtain more data.
-          stream_.async_read_some(buffers_.prepare(bytes_to_read),
-              ASIO_MOVE_CAST(read_until_delim_string_op)(*this));
-          return; default:
-          buffers_.commit(bytes_transferred);
-          if (ec || bytes_transferred == 0)
-            break;
-        }
-
-        const asio::error_code result_ec =
-          (search_position_ == not_found)
-          ? error::not_found : ec;
-
-        const std::size_t result_n =
-          (ec || search_position_ == not_found)
-          ? 0 : search_position_;
-
-        handler_(result_ec, result_n);
-      }
-    }
-
-  //private:
-    AsyncReadStream& stream_;
-    DynamicBuffer buffers_;
-    std::string delim_;
-    int start_;
-    std::size_t search_position_;
-    ReadHandler handler_;
-  };
-
-  template <typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      read_until_delim_string_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      read_until_delim_string_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      read_until_delim_string_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      read_until_delim_string_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      read_until_delim_string_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename ReadHandler, typename Allocator>
-struct associated_allocator<
-    detail::read_until_delim_string_op<AsyncReadStream,
-      DynamicBuffer, ReadHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator>::type type;
-
-  static type get(
-      const detail::read_until_delim_string_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename ReadHandler, typename Executor>
-struct associated_executor<
-    detail::read_until_delim_string_op<AsyncReadStream,
-      DynamicBuffer, ReadHandler>,
-    Executor>
-{
-  typedef typename associated_executor<ReadHandler, Executor>::type type;
-
-  static type get(
-      const detail::read_until_delim_string_op<AsyncReadStream,
-        DynamicBuffer, ReadHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream,
-    typename DynamicBuffer, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_STRING_VIEW_PARAM delim,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::read_until_delim_string_op<AsyncReadStream,
-    typename decay<DynamicBuffer>::type,
-      ASIO_HANDLER_TYPE(ReadHandler,
-        void (asio::error_code, std::size_t))>(
-          s, ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-            static_cast<std::string>(delim),
-              init.completion_handler)(asio::error_code(), 0, 1);
-
-  return init.result.get();
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if defined(ASIO_HAS_BOOST_REGEX)
-
-namespace detail
-{
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename RegEx, typename ReadHandler>
-  class read_until_expr_op
-  {
-  public:
-    template <typename BufferSequence>
-    read_until_expr_op(AsyncReadStream& stream,
-        ASIO_MOVE_ARG(BufferSequence) buffers,
-        const boost::regex& expr, ReadHandler& handler)
-      : stream_(stream),
-        buffers_(ASIO_MOVE_CAST(BufferSequence)(buffers)),
-        expr_(expr),
-        start_(0),
-        search_position_(0),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    read_until_expr_op(const read_until_expr_op& other)
-      : stream_(other.stream_),
-        buffers_(other.buffers_),
-        expr_(other.expr_),
-        start_(other.start_),
-        search_position_(other.search_position_),
-        handler_(other.handler_)
-    {
-    }
-
-    read_until_expr_op(read_until_expr_op&& other)
-      : stream_(other.stream_),
-        buffers_(ASIO_MOVE_CAST(DynamicBuffer)(other.buffers_)),
-        expr_(other.expr_),
-        start_(other.start_),
-        search_position_(other.search_position_),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      const std::size_t not_found = (std::numeric_limits<std::size_t>::max)();
-      std::size_t bytes_to_read;
-      switch (start_ = start)
-      {
-      case 1:
-        for (;;)
-        {
-          {
-            // Determine the range of the data to be searched.
-            typedef typename DynamicBuffer::const_buffers_type
-              buffers_type;
-            typedef buffers_iterator<buffers_type> iterator;
-            buffers_type data_buffers = buffers_.data();
-            iterator begin = iterator::begin(data_buffers);
-            iterator start_pos = begin + search_position_;
-            iterator end = iterator::end(data_buffers);
-
-            // Look for a match.
-            boost::match_results<iterator,
-              typename std::vector<boost::sub_match<iterator> >::allocator_type>
-                match_results;
-            bool match = regex_search(start_pos, end, match_results, expr_,
-                boost::match_default | boost::match_partial);
-            if (match && match_results[0].matched)
-            {
-              // Full match. We're done.
-              search_position_ = match_results[0].second - begin;
-              bytes_to_read = 0;
-            }
-
-            // No match yet. Check if buffer is full.
-            else if (buffers_.size() == buffers_.max_size())
-            {
-              search_position_ = not_found;
-              bytes_to_read = 0;
-            }
-
-            // Need to read some more data.
-            else
-            {
-              if (match)
-              {
-                // Partial match. Next search needs to start from beginning of
-                // match.
-                search_position_ = match_results[0].first - begin;
-              }
-              else
-              {
-                // Next search can start with the new data.
-                search_position_ = end - begin;
-              }
-
-              bytes_to_read = std::min<std::size_t>(
-                    std::max<std::size_t>(512,
-                      buffers_.capacity() - buffers_.size()),
-                    std::min<std::size_t>(65536,
-                      buffers_.max_size() - buffers_.size()));
-            }
-          }
-
-          // Check if we're done.
-          if (!start && bytes_to_read == 0)
-            break;
-
-          // Start a new asynchronous read operation to obtain more data.
-          stream_.async_read_some(buffers_.prepare(bytes_to_read),
-              ASIO_MOVE_CAST(read_until_expr_op)(*this));
-          return; default:
-          buffers_.commit(bytes_transferred);
-          if (ec || bytes_transferred == 0)
-            break;
-        }
-
-        const asio::error_code result_ec =
-          (search_position_ == not_found)
-          ? error::not_found : ec;
-
-        const std::size_t result_n =
-          (ec || search_position_ == not_found)
-          ? 0 : search_position_;
-
-        handler_(result_ec, result_n);
-      }
-    }
-
-  //private:
-    AsyncReadStream& stream_;
-    DynamicBuffer buffers_;
-    RegEx expr_;
-    int start_;
-    std::size_t search_position_;
-    ReadHandler handler_;
-  };
-
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename RegEx, typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      read_until_expr_op<AsyncReadStream,
-        DynamicBuffer, RegEx, ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename RegEx, typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      read_until_expr_op<AsyncReadStream,
-        DynamicBuffer, RegEx, ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename RegEx, typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      read_until_expr_op<AsyncReadStream,
-        DynamicBuffer, RegEx, ReadHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename RegEx, typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      read_until_expr_op<AsyncReadStream,
-        DynamicBuffer, RegEx, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename RegEx, typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      read_until_expr_op<AsyncReadStream,
-        DynamicBuffer, RegEx, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename RegEx, typename ReadHandler, typename Allocator>
-struct associated_allocator<
-    detail::read_until_expr_op<AsyncReadStream,
-      DynamicBuffer, RegEx, ReadHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator>::type type;
-
-  static type get(
-      const detail::read_until_expr_op<AsyncReadStream,
-        DynamicBuffer, RegEx, ReadHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename RegEx, typename ReadHandler, typename Executor>
-struct associated_executor<
-    detail::read_until_expr_op<AsyncReadStream,
-      DynamicBuffer, RegEx, ReadHandler>,
-    Executor>
-{
-  typedef typename associated_executor<ReadHandler, Executor>::type type;
-
-  static type get(
-      const detail::read_until_expr_op<AsyncReadStream,
-        DynamicBuffer, RegEx, ReadHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream,
-    typename DynamicBuffer, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    const boost::regex& expr,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::read_until_expr_op<AsyncReadStream,
-    typename decay<DynamicBuffer>::type,
-      boost::regex, ASIO_HANDLER_TYPE(ReadHandler,
-        void (asio::error_code, std::size_t))>(
-          s, ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-            expr, init.completion_handler)(asio::error_code(), 0, 1);
-
-  return init.result.get();
-}
-
-#endif // defined(ASIO_HAS_BOOST_REGEX)
-
-namespace detail
-{
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename MatchCondition, typename ReadHandler>
-  class read_until_match_op
-  {
-  public:
-    template <typename BufferSequence>
-    read_until_match_op(AsyncReadStream& stream,
-        ASIO_MOVE_ARG(BufferSequence) buffers,
-        MatchCondition match_condition, ReadHandler& handler)
-      : stream_(stream),
-        buffers_(ASIO_MOVE_CAST(BufferSequence)(buffers)),
-        match_condition_(match_condition),
-        start_(0),
-        search_position_(0),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    read_until_match_op(const read_until_match_op& other)
-      : stream_(other.stream_),
-        buffers_(other.buffers_),
-        match_condition_(other.match_condition_),
-        start_(other.start_),
-        search_position_(other.search_position_),
-        handler_(other.handler_)
-    {
-    }
-
-    read_until_match_op(read_until_match_op&& other)
-      : stream_(other.stream_),
-        buffers_(ASIO_MOVE_CAST(DynamicBuffer)(other.buffers_)),
-        match_condition_(other.match_condition_),
-        start_(other.start_),
-        search_position_(other.search_position_),
-        handler_(ASIO_MOVE_CAST(ReadHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      const std::size_t not_found = (std::numeric_limits<std::size_t>::max)();
-      std::size_t bytes_to_read;
-      switch (start_ = start)
-      {
-      case 1:
-        for (;;)
-        {
-          {
-            // Determine the range of the data to be searched.
-            typedef typename DynamicBuffer::const_buffers_type
-              buffers_type;
-            typedef buffers_iterator<buffers_type> iterator;
-            buffers_type data_buffers = buffers_.data();
-            iterator begin = iterator::begin(data_buffers);
-            iterator start_pos = begin + search_position_;
-            iterator end = iterator::end(data_buffers);
-
-            // Look for a match.
-            std::pair<iterator, bool> result = match_condition_(start_pos, end);
-            if (result.second)
-            {
-              // Full match. We're done.
-              search_position_ = result.first - begin;
-              bytes_to_read = 0;
-            }
-
-            // No match yet. Check if buffer is full.
-            else if (buffers_.size() == buffers_.max_size())
-            {
-              search_position_ = not_found;
-              bytes_to_read = 0;
-            }
-
-            // Need to read some more data.
-            else
-            {
-              if (result.first != end)
-              {
-                // Partial match. Next search needs to start from beginning of
-                // match.
-                search_position_ = result.first - begin;
-              }
-              else
-              {
-                // Next search can start with the new data.
-                search_position_ = end - begin;
-              }
-
-              bytes_to_read = std::min<std::size_t>(
-                    std::max<std::size_t>(512,
-                      buffers_.capacity() - buffers_.size()),
-                    std::min<std::size_t>(65536,
-                      buffers_.max_size() - buffers_.size()));
-            }
-          }
-
-          // Check if we're done.
-          if (!start && bytes_to_read == 0)
-            break;
-
-          // Start a new asynchronous read operation to obtain more data.
-          stream_.async_read_some(buffers_.prepare(bytes_to_read),
-              ASIO_MOVE_CAST(read_until_match_op)(*this));
-          return; default:
-          buffers_.commit(bytes_transferred);
-          if (ec || bytes_transferred == 0)
-            break;
-        }
-
-        const asio::error_code result_ec =
-          (search_position_ == not_found)
-          ? error::not_found : ec;
-
-        const std::size_t result_n =
-          (ec || search_position_ == not_found)
-          ? 0 : search_position_;
-
-        handler_(result_ec, result_n);
-      }
-    }
-
-  //private:
-    AsyncReadStream& stream_;
-    DynamicBuffer buffers_;
-    MatchCondition match_condition_;
-    int start_;
-    std::size_t search_position_;
-    ReadHandler handler_;
-  };
-
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename MatchCondition, typename ReadHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      read_until_match_op<AsyncReadStream, DynamicBuffer,
-        MatchCondition, ReadHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename MatchCondition, typename ReadHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      read_until_match_op<AsyncReadStream, DynamicBuffer,
-        MatchCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncReadStream, typename DynamicBuffer,
-      typename MatchCondition, typename ReadHandler>
-  inline bool asio_handler_is_continuation(
-      read_until_match_op<AsyncReadStream, DynamicBuffer,
-        MatchCondition, ReadHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename MatchCondition,
-      typename ReadHandler>
-  inline void asio_handler_invoke(Function& function,
-      read_until_match_op<AsyncReadStream, DynamicBuffer,
-        MatchCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncReadStream,
-      typename DynamicBuffer, typename MatchCondition,
-      typename ReadHandler>
-  inline void asio_handler_invoke(const Function& function,
-      read_until_match_op<AsyncReadStream, DynamicBuffer,
-      MatchCondition, ReadHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename MatchCondition, typename ReadHandler, typename Allocator>
-struct associated_allocator<
-    detail::read_until_match_op<AsyncReadStream,
-      DynamicBuffer, MatchCondition, ReadHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<ReadHandler, Allocator>::type type;
-
-  static type get(
-      const detail::read_until_match_op<AsyncReadStream,
-        DynamicBuffer, MatchCondition, ReadHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<ReadHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename MatchCondition, typename ReadHandler, typename Executor>
-struct associated_executor<
-    detail::read_until_match_op<AsyncReadStream,
-      DynamicBuffer, MatchCondition, ReadHandler>,
-    Executor>
-{
-  typedef typename associated_executor<ReadHandler, Executor>::type type;
-
-  static type get(
-      const detail::read_until_match_op<AsyncReadStream,
-        DynamicBuffer, MatchCondition, ReadHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<ReadHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename MatchCondition, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    MatchCondition match_condition, ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a ReadHandler.
-  ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-  async_completion<ReadHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::read_until_match_op<AsyncReadStream,
-    typename decay<DynamicBuffer>::type,
-      MatchCondition, ASIO_HANDLER_TYPE(ReadHandler,
-        void (asio::error_code, std::size_t))>(
-          s, ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-            match_condition, init.completion_handler)(
-              asio::error_code(), 0, 1);
-
-  return init.result.get();
-}
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-template <typename AsyncReadStream, typename Allocator, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    char delim, ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  return async_read_until(s, basic_streambuf_ref<Allocator>(b),
-      delim, ASIO_MOVE_CAST(ReadHandler)(handler));
-}
-
-template <typename AsyncReadStream, typename Allocator, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    ASIO_STRING_VIEW_PARAM delim,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  return async_read_until(s, basic_streambuf_ref<Allocator>(b),
-      delim, ASIO_MOVE_CAST(ReadHandler)(handler));
-}
-
-#if defined(ASIO_HAS_BOOST_REGEX)
-
-template <typename AsyncReadStream, typename Allocator, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, const boost::regex& expr,
-    ASIO_MOVE_ARG(ReadHandler) handler)
-{
-  return async_read_until(s, basic_streambuf_ref<Allocator>(b),
-      expr, ASIO_MOVE_CAST(ReadHandler)(handler));
-}
-
-#endif // defined(ASIO_HAS_BOOST_REGEX)
-
-template <typename AsyncReadStream, typename Allocator,
-    typename MatchCondition, typename ReadHandler>
-inline ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    MatchCondition match_condition, ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type*)
-{
-  return async_read_until(s, basic_streambuf_ref<Allocator>(b),
-      match_condition, ASIO_MOVE_CAST(ReadHandler)(handler));
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_READ_UNTIL_HPP
diff --git a/tools/sdk/include/asio/asio/impl/serial_port_base.hpp b/tools/sdk/include/asio/asio/impl/serial_port_base.hpp
deleted file mode 100644
index cdc201d8ab6..00000000000
--- a/tools/sdk/include/asio/asio/impl/serial_port_base.hpp
+++ /dev/null
@@ -1,59 +0,0 @@
-//
-// impl/serial_port_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Rep Invariant Systems, Inc. (info@repinvariant.com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_SERIAL_PORT_BASE_HPP
-#define ASIO_IMPL_SERIAL_PORT_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-inline serial_port_base::baud_rate::baud_rate(unsigned int rate)
-  : value_(rate)
-{
-}
-
-inline unsigned int serial_port_base::baud_rate::value() const
-{
-  return value_;
-}
-
-inline serial_port_base::flow_control::type
-serial_port_base::flow_control::value() const
-{
-  return value_;
-}
-
-inline serial_port_base::parity::type serial_port_base::parity::value() const
-{
-  return value_;
-}
-
-inline serial_port_base::stop_bits::type
-serial_port_base::stop_bits::value() const
-{
-  return value_;
-}
-
-inline unsigned int serial_port_base::character_size::value() const
-{
-  return value_;
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_SERIAL_PORT_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/impl/spawn.hpp b/tools/sdk/include/asio/asio/impl/spawn.hpp
deleted file mode 100644
index 5594ad93d43..00000000000
--- a/tools/sdk/include/asio/asio/impl/spawn.hpp
+++ /dev/null
@@ -1,535 +0,0 @@
-//
-// impl/spawn.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_SPAWN_HPP
-#define ASIO_IMPL_SPAWN_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/async_result.hpp"
-#include "asio/bind_executor.hpp"
-#include "asio/detail/atomic_count.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/system_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-  template <typename Handler, typename T>
-  class coro_handler
-  {
-  public:
-    coro_handler(basic_yield_context<Handler> ctx)
-      : coro_(ctx.coro_.lock()),
-        ca_(ctx.ca_),
-        handler_(ctx.handler_),
-        ready_(0),
-        ec_(ctx.ec_),
-        value_(0)
-    {
-    }
-
-    void operator()(T value)
-    {
-      *ec_ = asio::error_code();
-      *value_ = ASIO_MOVE_CAST(T)(value);
-      if (--*ready_ == 0)
-        (*coro_)();
-    }
-
-    void operator()(asio::error_code ec, T value)
-    {
-      *ec_ = ec;
-      *value_ = ASIO_MOVE_CAST(T)(value);
-      if (--*ready_ == 0)
-        (*coro_)();
-    }
-
-  //private:
-    shared_ptr<typename basic_yield_context<Handler>::callee_type> coro_;
-    typename basic_yield_context<Handler>::caller_type& ca_;
-    Handler handler_;
-    atomic_count* ready_;
-    asio::error_code* ec_;
-    T* value_;
-  };
-
-  template <typename Handler>
-  class coro_handler<Handler, void>
-  {
-  public:
-    coro_handler(basic_yield_context<Handler> ctx)
-      : coro_(ctx.coro_.lock()),
-        ca_(ctx.ca_),
-        handler_(ctx.handler_),
-        ready_(0),
-        ec_(ctx.ec_)
-    {
-    }
-
-    void operator()()
-    {
-      *ec_ = asio::error_code();
-      if (--*ready_ == 0)
-        (*coro_)();
-    }
-
-    void operator()(asio::error_code ec)
-    {
-      *ec_ = ec;
-      if (--*ready_ == 0)
-        (*coro_)();
-    }
-
-  //private:
-    shared_ptr<typename basic_yield_context<Handler>::callee_type> coro_;
-    typename basic_yield_context<Handler>::caller_type& ca_;
-    Handler handler_;
-    atomic_count* ready_;
-    asio::error_code* ec_;
-  };
-
-  template <typename Handler, typename T>
-  inline void* asio_handler_allocate(std::size_t size,
-      coro_handler<Handler, T>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename Handler, typename T>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      coro_handler<Handler, T>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename Handler, typename T>
-  inline bool asio_handler_is_continuation(coro_handler<Handler, T>*)
-  {
-    return true;
-  }
-
-  template <typename Function, typename Handler, typename T>
-  inline void asio_handler_invoke(Function& function,
-      coro_handler<Handler, T>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename Handler, typename T>
-  inline void asio_handler_invoke(const Function& function,
-      coro_handler<Handler, T>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Handler, typename T>
-  class coro_async_result
-  {
-  public:
-    typedef coro_handler<Handler, T> completion_handler_type;
-    typedef T return_type;
-
-    explicit coro_async_result(completion_handler_type& h)
-      : handler_(h),
-        ca_(h.ca_),
-        ready_(2)
-    {
-      h.ready_ = &ready_;
-      out_ec_ = h.ec_;
-      if (!out_ec_) h.ec_ = &ec_;
-      h.value_ = &value_;
-    }
-
-    return_type get()
-    {
-      // Must not hold shared_ptr to coro while suspended.
-      handler_.coro_.reset();
-
-      if (--ready_ != 0)
-        ca_();
-      if (!out_ec_ && ec_) throw asio::system_error(ec_);
-      return ASIO_MOVE_CAST(return_type)(value_);
-    }
-
-  private:
-    completion_handler_type& handler_;
-    typename basic_yield_context<Handler>::caller_type& ca_;
-    atomic_count ready_;
-    asio::error_code* out_ec_;
-    asio::error_code ec_;
-    return_type value_;
-  };
-
-  template <typename Handler>
-  class coro_async_result<Handler, void>
-  {
-  public:
-    typedef coro_handler<Handler, void> completion_handler_type;
-    typedef void return_type;
-
-    explicit coro_async_result(completion_handler_type& h)
-      : handler_(h),
-        ca_(h.ca_),
-        ready_(2)
-    {
-      h.ready_ = &ready_;
-      out_ec_ = h.ec_;
-      if (!out_ec_) h.ec_ = &ec_;
-    }
-
-    void get()
-    {
-      // Must not hold shared_ptr to coro while suspended.
-      handler_.coro_.reset();
-
-      if (--ready_ != 0)
-        ca_();
-      if (!out_ec_ && ec_) throw asio::system_error(ec_);
-    }
-
-  private:
-    completion_handler_type& handler_;
-    typename basic_yield_context<Handler>::caller_type& ca_;
-    atomic_count ready_;
-    asio::error_code* out_ec_;
-    asio::error_code ec_;
-  };
-
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename Handler, typename ReturnType>
-class async_result<basic_yield_context<Handler>, ReturnType()>
-  : public detail::coro_async_result<Handler, void>
-{
-public:
-  explicit async_result(
-    typename detail::coro_async_result<Handler,
-      void>::completion_handler_type& h)
-    : detail::coro_async_result<Handler, void>(h)
-  {
-  }
-};
-
-template <typename Handler, typename ReturnType, typename Arg1>
-class async_result<basic_yield_context<Handler>, ReturnType(Arg1)>
-  : public detail::coro_async_result<Handler, typename decay<Arg1>::type>
-{
-public:
-  explicit async_result(
-    typename detail::coro_async_result<Handler,
-      typename decay<Arg1>::type>::completion_handler_type& h)
-    : detail::coro_async_result<Handler, typename decay<Arg1>::type>(h)
-  {
-  }
-};
-
-template <typename Handler, typename ReturnType>
-class async_result<basic_yield_context<Handler>,
-    ReturnType(asio::error_code)>
-  : public detail::coro_async_result<Handler, void>
-{
-public:
-  explicit async_result(
-    typename detail::coro_async_result<Handler,
-      void>::completion_handler_type& h)
-    : detail::coro_async_result<Handler, void>(h)
-  {
-  }
-};
-
-template <typename Handler, typename ReturnType, typename Arg2>
-class async_result<basic_yield_context<Handler>,
-    ReturnType(asio::error_code, Arg2)>
-  : public detail::coro_async_result<Handler, typename decay<Arg2>::type>
-{
-public:
-  explicit async_result(
-    typename detail::coro_async_result<Handler,
-      typename decay<Arg2>::type>::completion_handler_type& h)
-    : detail::coro_async_result<Handler, typename decay<Arg2>::type>(h)
-  {
-  }
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-template <typename Handler, typename ReturnType>
-struct handler_type<basic_yield_context<Handler>, ReturnType()>
-{
-  typedef detail::coro_handler<Handler, void> type;
-};
-
-template <typename Handler, typename ReturnType, typename Arg1>
-struct handler_type<basic_yield_context<Handler>, ReturnType(Arg1)>
-{
-  typedef detail::coro_handler<Handler, typename decay<Arg1>::type> type;
-};
-
-template <typename Handler, typename ReturnType>
-struct handler_type<basic_yield_context<Handler>,
-    ReturnType(asio::error_code)>
-{
-  typedef detail::coro_handler<Handler, void> type;
-};
-
-template <typename Handler, typename ReturnType, typename Arg2>
-struct handler_type<basic_yield_context<Handler>,
-    ReturnType(asio::error_code, Arg2)>
-{
-  typedef detail::coro_handler<Handler, typename decay<Arg2>::type> type;
-};
-
-template <typename Handler, typename T>
-class async_result<detail::coro_handler<Handler, T> >
-  : public detail::coro_async_result<Handler, T>
-{
-public:
-  typedef typename detail::coro_async_result<Handler, T>::return_type type;
-
-  explicit async_result(
-    typename detail::coro_async_result<Handler,
-      T>::completion_handler_type& h)
-    : detail::coro_async_result<Handler, T>(h)
-  {
-  }
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Handler, typename T, typename Allocator>
-struct associated_allocator<detail::coro_handler<Handler, T>, Allocator>
-{
-  typedef typename associated_allocator<Handler, Allocator>::type type;
-
-  static type get(const detail::coro_handler<Handler, T>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<Handler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename Handler, typename T, typename Executor>
-struct associated_executor<detail::coro_handler<Handler, T>, Executor>
-{
-  typedef typename associated_executor<Handler, Executor>::type type;
-
-  static type get(const detail::coro_handler<Handler, T>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<Handler, Executor>::get(h.handler_, ex);
-  }
-};
-
-namespace detail {
-
-  template <typename Handler, typename Function>
-  struct spawn_data : private noncopyable
-  {
-    template <typename Hand, typename Func>
-    spawn_data(ASIO_MOVE_ARG(Hand) handler,
-        bool call_handler, ASIO_MOVE_ARG(Func) function)
-      : handler_(ASIO_MOVE_CAST(Hand)(handler)),
-        call_handler_(call_handler),
-        function_(ASIO_MOVE_CAST(Func)(function))
-    {
-    }
-
-    weak_ptr<typename basic_yield_context<Handler>::callee_type> coro_;
-    Handler handler_;
-    bool call_handler_;
-    Function function_;
-  };
-
-  template <typename Handler, typename Function>
-  struct coro_entry_point
-  {
-    void operator()(typename basic_yield_context<Handler>::caller_type& ca)
-    {
-      shared_ptr<spawn_data<Handler, Function> > data(data_);
-#if !defined(BOOST_COROUTINES_UNIDIRECT) && !defined(BOOST_COROUTINES_V2)
-      ca(); // Yield until coroutine pointer has been initialised.
-#endif // !defined(BOOST_COROUTINES_UNIDIRECT) && !defined(BOOST_COROUTINES_V2)
-      const basic_yield_context<Handler> yield(
-          data->coro_, ca, data->handler_);
-
-      (data->function_)(yield);
-      if (data->call_handler_)
-        (data->handler_)();
-    }
-
-    shared_ptr<spawn_data<Handler, Function> > data_;
-  };
-
-  template <typename Handler, typename Function>
-  struct spawn_helper
-  {
-    void operator()()
-    {
-      typedef typename basic_yield_context<Handler>::callee_type callee_type;
-      coro_entry_point<Handler, Function> entry_point = { data_ };
-      shared_ptr<callee_type> coro(new callee_type(entry_point, attributes_));
-      data_->coro_ = coro;
-      (*coro)();
-    }
-
-    shared_ptr<spawn_data<Handler, Function> > data_;
-    boost::coroutines::attributes attributes_;
-  };
-
-  template <typename Function, typename Handler, typename Function1>
-  inline void asio_handler_invoke(Function& function,
-      spawn_helper<Handler, Function1>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->data_->handler_);
-  }
-
-  template <typename Function, typename Handler, typename Function1>
-  inline void asio_handler_invoke(const Function& function,
-      spawn_helper<Handler, Function1>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->data_->handler_);
-  }
-
-  inline void default_spawn_handler() {}
-
-} // namespace detail
-
-template <typename Function>
-inline void spawn(ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes)
-{
-  typedef typename decay<Function>::type function_type;
-
-  typename associated_executor<function_type>::type ex(
-      (get_associated_executor)(function));
-
-  asio::spawn(ex, ASIO_MOVE_CAST(Function)(function), attributes);
-}
-
-template <typename Handler, typename Function>
-void spawn(ASIO_MOVE_ARG(Handler) handler,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes,
-    typename enable_if<!is_executor<typename decay<Handler>::type>::value &&
-      !is_convertible<Handler&, execution_context&>::value>::type*)
-{
-  typedef typename decay<Handler>::type handler_type;
-  typedef typename decay<Function>::type function_type;
-
-  typename associated_executor<handler_type>::type ex(
-      (get_associated_executor)(handler));
-
-  typename associated_allocator<handler_type>::type a(
-      (get_associated_allocator)(handler));
-
-  detail::spawn_helper<handler_type, function_type> helper;
-  helper.data_.reset(
-      new detail::spawn_data<handler_type, function_type>(
-        ASIO_MOVE_CAST(Handler)(handler), true,
-        ASIO_MOVE_CAST(Function)(function)));
-  helper.attributes_ = attributes;
-
-  ex.dispatch(helper, a);
-}
-
-template <typename Handler, typename Function>
-void spawn(basic_yield_context<Handler> ctx,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes)
-{
-  typedef typename decay<Function>::type function_type;
-
-  Handler handler(ctx.handler_); // Explicit copy that might be moved from.
-
-  typename associated_executor<Handler>::type ex(
-      (get_associated_executor)(handler));
-
-  typename associated_allocator<Handler>::type a(
-      (get_associated_allocator)(handler));
-
-  detail::spawn_helper<Handler, function_type> helper;
-  helper.data_.reset(
-      new detail::spawn_data<Handler, function_type>(
-        ASIO_MOVE_CAST(Handler)(handler), false,
-        ASIO_MOVE_CAST(Function)(function)));
-  helper.attributes_ = attributes;
-
-  ex.dispatch(helper, a);
-}
-
-template <typename Function, typename Executor>
-inline void spawn(const Executor& ex,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes,
-    typename enable_if<is_executor<Executor>::value>::type*)
-{
-  asio::spawn(asio::strand<Executor>(ex),
-      ASIO_MOVE_CAST(Function)(function), attributes);
-}
-
-template <typename Function, typename Executor>
-inline void spawn(const strand<Executor>& ex,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes)
-{
-  asio::spawn(asio::bind_executor(
-        ex, &detail::default_spawn_handler),
-      ASIO_MOVE_CAST(Function)(function), attributes);
-}
-
-template <typename Function>
-inline void spawn(const asio::io_context::strand& s,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes)
-{
-  asio::spawn(asio::bind_executor(
-        s, &detail::default_spawn_handler),
-      ASIO_MOVE_CAST(Function)(function), attributes);
-}
-
-template <typename Function, typename ExecutionContext>
-inline void spawn(ExecutionContext& ctx,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes,
-    typename enable_if<is_convertible<
-      ExecutionContext&, execution_context&>::value>::type*)
-{
-  asio::spawn(ctx.get_executor(),
-      ASIO_MOVE_CAST(Function)(function), attributes);
-}
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_SPAWN_HPP
diff --git a/tools/sdk/include/asio/asio/impl/src.hpp b/tools/sdk/include/asio/asio/impl/src.hpp
deleted file mode 100644
index a72637b94ed..00000000000
--- a/tools/sdk/include/asio/asio/impl/src.hpp
+++ /dev/null
@@ -1,82 +0,0 @@
-//
-// impl/src.hpp
-// ~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_SRC_HPP
-#define ASIO_IMPL_SRC_HPP
-
-#define ASIO_SOURCE
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# error Do not compile Asio library source with ASIO_HEADER_ONLY defined
-#endif
-
-#include "asio/impl/error.ipp"
-#include "asio/impl/error_code.ipp"
-#include "asio/impl/execution_context.ipp"
-#include "asio/impl/executor.ipp"
-#include "asio/impl/handler_alloc_hook.ipp"
-#include "asio/impl/io_context.ipp"
-#include "asio/impl/serial_port_base.ipp"
-#include "asio/impl/system_context.ipp"
-#include "asio/impl/thread_pool.ipp"
-#include "asio/detail/impl/buffer_sequence_adapter.ipp"
-#include "asio/detail/impl/descriptor_ops.ipp"
-#include "asio/detail/impl/dev_poll_reactor.ipp"
-#include "asio/detail/impl/epoll_reactor.ipp"
-#include "asio/detail/impl/eventfd_select_interrupter.ipp"
-#include "asio/detail/impl/handler_tracking.ipp"
-#include "asio/detail/impl/kqueue_reactor.ipp"
-#include "asio/detail/impl/null_event.ipp"
-#include "asio/detail/impl/pipe_select_interrupter.ipp"
-#include "asio/detail/impl/posix_event.ipp"
-#include "asio/detail/impl/posix_mutex.ipp"
-#include "asio/detail/impl/posix_thread.ipp"
-#include "asio/detail/impl/posix_tss_ptr.ipp"
-#include "asio/detail/impl/reactive_descriptor_service.ipp"
-#include "asio/detail/impl/reactive_serial_port_service.ipp"
-#include "asio/detail/impl/reactive_socket_service_base.ipp"
-#include "asio/detail/impl/resolver_service_base.ipp"
-#include "asio/detail/impl/scheduler.ipp"
-#include "asio/detail/impl/select_reactor.ipp"
-#include "asio/detail/impl/service_registry.ipp"
-#include "asio/detail/impl/signal_set_service.ipp"
-#include "asio/detail/impl/socket_ops.ipp"
-#include "asio/detail/impl/socket_select_interrupter.ipp"
-#include "asio/detail/impl/strand_executor_service.ipp"
-#include "asio/detail/impl/strand_service.ipp"
-#include "asio/detail/impl/throw_error.ipp"
-#include "asio/detail/impl/timer_queue_ptime.ipp"
-#include "asio/detail/impl/timer_queue_set.ipp"
-#include "asio/detail/impl/win_iocp_handle_service.ipp"
-#include "asio/detail/impl/win_iocp_io_context.ipp"
-#include "asio/detail/impl/win_iocp_serial_port_service.ipp"
-#include "asio/detail/impl/win_iocp_socket_service_base.ipp"
-#include "asio/detail/impl/win_event.ipp"
-#include "asio/detail/impl/win_mutex.ipp"
-#include "asio/detail/impl/win_object_handle_service.ipp"
-#include "asio/detail/impl/win_static_mutex.ipp"
-#include "asio/detail/impl/win_thread.ipp"
-#include "asio/detail/impl/win_tss_ptr.ipp"
-#include "asio/detail/impl/winrt_ssocket_service_base.ipp"
-#include "asio/detail/impl/winrt_timer_scheduler.ipp"
-#include "asio/detail/impl/winsock_init.ipp"
-#include "asio/generic/detail/impl/endpoint.ipp"
-#include "asio/ip/impl/address.ipp"
-#include "asio/ip/impl/address_v4.ipp"
-#include "asio/ip/impl/address_v6.ipp"
-#include "asio/ip/impl/host_name.ipp"
-#include "asio/ip/impl/network_v4.ipp"
-#include "asio/ip/impl/network_v6.ipp"
-#include "asio/ip/detail/impl/endpoint.ipp"
-#include "asio/local/detail/impl/endpoint.ipp"
-
-#endif // ASIO_IMPL_SRC_HPP
diff --git a/tools/sdk/include/asio/asio/impl/system_context.hpp b/tools/sdk/include/asio/asio/impl/system_context.hpp
deleted file mode 100644
index 87ffe76a258..00000000000
--- a/tools/sdk/include/asio/asio/impl/system_context.hpp
+++ /dev/null
@@ -1,34 +0,0 @@
-//
-// impl/system_context.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_SYSTEM_CONTEXT_HPP
-#define ASIO_IMPL_SYSTEM_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/system_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-inline system_context::executor_type
-system_context::get_executor() ASIO_NOEXCEPT
-{
-  return system_executor();
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_SYSTEM_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/impl/system_executor.hpp b/tools/sdk/include/asio/asio/impl/system_executor.hpp
deleted file mode 100644
index ac4861f56b8..00000000000
--- a/tools/sdk/include/asio/asio/impl/system_executor.hpp
+++ /dev/null
@@ -1,85 +0,0 @@
-//
-// impl/system_executor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_SYSTEM_EXECUTOR_HPP
-#define ASIO_IMPL_SYSTEM_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/executor_op.hpp"
-#include "asio/detail/global.hpp"
-#include "asio/detail/recycling_allocator.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/system_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-inline system_context& system_executor::context() const ASIO_NOEXCEPT
-{
-  return detail::global<system_context>();
-}
-
-template <typename Function, typename Allocator>
-void system_executor::dispatch(
-    ASIO_MOVE_ARG(Function) f, const Allocator&) const
-{
-  typename decay<Function>::type tmp(ASIO_MOVE_CAST(Function)(f));
-  asio_handler_invoke_helpers::invoke(tmp, tmp);
-}
-
-template <typename Function, typename Allocator>
-void system_executor::post(
-    ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-{
-  typedef typename decay<Function>::type function_type;
-
-  system_context& ctx = detail::global<system_context>();
-
-  // Allocate and construct an operation to wrap the function.
-  typedef detail::executor_op<function_type, Allocator> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(f), a);
-
-  ASIO_HANDLER_CREATION((ctx, *p.p,
-        "system_executor", &this->context(), 0, "post"));
-
-  ctx.scheduler_.post_immediate_completion(p.p, false);
-  p.v = p.p = 0;
-}
-
-template <typename Function, typename Allocator>
-void system_executor::defer(
-    ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-{
-  typedef typename decay<Function>::type function_type;
-
-  system_context& ctx = detail::global<system_context>();
-
-  // Allocate and construct an operation to wrap the function.
-  typedef detail::executor_op<function_type, Allocator> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(f), a);
-
-  ASIO_HANDLER_CREATION((ctx, *p.p,
-        "system_executor", &this->context(), 0, "defer"));
-
-  ctx.scheduler_.post_immediate_completion(p.p, true);
-  p.v = p.p = 0;
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_SYSTEM_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/impl/thread_pool.hpp b/tools/sdk/include/asio/asio/impl/thread_pool.hpp
deleted file mode 100644
index 058e3771bba..00000000000
--- a/tools/sdk/include/asio/asio/impl/thread_pool.hpp
+++ /dev/null
@@ -1,127 +0,0 @@
-//
-// impl/thread_pool.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_THREAD_POOL_HPP
-#define ASIO_IMPL_THREAD_POOL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/executor_op.hpp"
-#include "asio/detail/fenced_block.hpp"
-#include "asio/detail/recycling_allocator.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/execution_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-inline thread_pool::executor_type
-thread_pool::get_executor() ASIO_NOEXCEPT
-{
-  return executor_type(*this);
-}
-
-inline thread_pool&
-thread_pool::executor_type::context() const ASIO_NOEXCEPT
-{
-  return pool_;
-}
-
-inline void
-thread_pool::executor_type::on_work_started() const ASIO_NOEXCEPT
-{
-  pool_.scheduler_.work_started();
-}
-
-inline void thread_pool::executor_type::on_work_finished()
-const ASIO_NOEXCEPT
-{
-  pool_.scheduler_.work_finished();
-}
-
-template <typename Function, typename Allocator>
-void thread_pool::executor_type::dispatch(
-    ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-{
-  typedef typename decay<Function>::type function_type;
-
-  // Invoke immediately if we are already inside the thread pool.
-  if (pool_.scheduler_.can_dispatch())
-  {
-    // Make a local, non-const copy of the function.
-    function_type tmp(ASIO_MOVE_CAST(Function)(f));
-
-    detail::fenced_block b(detail::fenced_block::full);
-    asio_handler_invoke_helpers::invoke(tmp, tmp);
-    return;
-  }
-
-  // Allocate and construct an operation to wrap the function.
-  typedef detail::executor_op<function_type, Allocator> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(f), a);
-
-  ASIO_HANDLER_CREATION((pool_, *p.p,
-        "thread_pool", &this->context(), 0, "dispatch"));
-
-  pool_.scheduler_.post_immediate_completion(p.p, false);
-  p.v = p.p = 0;
-}
-
-template <typename Function, typename Allocator>
-void thread_pool::executor_type::post(
-    ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-{
-  typedef typename decay<Function>::type function_type;
-
-  // Allocate and construct an operation to wrap the function.
-  typedef detail::executor_op<function_type, Allocator> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(f), a);
-
-  ASIO_HANDLER_CREATION((pool_, *p.p,
-        "thread_pool", &this->context(), 0, "post"));
-
-  pool_.scheduler_.post_immediate_completion(p.p, false);
-  p.v = p.p = 0;
-}
-
-template <typename Function, typename Allocator>
-void thread_pool::executor_type::defer(
-    ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-{
-  typedef typename decay<Function>::type function_type;
-
-  // Allocate and construct an operation to wrap the function.
-  typedef detail::executor_op<function_type, Allocator> op;
-  typename op::ptr p = { detail::addressof(a), op::ptr::allocate(a), 0 };
-  p.p = new (p.v) op(ASIO_MOVE_CAST(Function)(f), a);
-
-  ASIO_HANDLER_CREATION((pool_, *p.p,
-        "thread_pool", &this->context(), 0, "defer"));
-
-  pool_.scheduler_.post_immediate_completion(p.p, true);
-  p.v = p.p = 0;
-}
-
-inline bool
-thread_pool::executor_type::running_in_this_thread() const ASIO_NOEXCEPT
-{
-  return pool_.scheduler_.can_dispatch();
-}
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_THREAD_POOL_HPP
diff --git a/tools/sdk/include/asio/asio/impl/use_future.hpp b/tools/sdk/include/asio/asio/impl/use_future.hpp
deleted file mode 100644
index 51eb7e2ca41..00000000000
--- a/tools/sdk/include/asio/asio/impl/use_future.hpp
+++ /dev/null
@@ -1,938 +0,0 @@
-//
-// impl/use_future.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_USE_FUTURE_HPP
-#define ASIO_IMPL_USE_FUTURE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <future>
-#include <tuple>
-#include "asio/async_result.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/error_code.hpp"
-#include "asio/packaged_task.hpp"
-#include "asio/system_error.hpp"
-#include "asio/system_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-template <typename T, typename F, typename... Args>
-inline void promise_invoke_and_set(std::promise<T>& p,
-    F& f, ASIO_MOVE_ARG(Args)... args)
-{
-#if !defined(ASIO_NO_EXCEPTIONS)
-  try
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-  {
-    p.set_value(f(ASIO_MOVE_CAST(Args)(args)...));
-  }
-#if !defined(ASIO_NO_EXCEPTIONS)
-  catch (...)
-  {
-    p.set_exception(std::current_exception());
-  }
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-}
-
-template <typename F, typename... Args>
-inline void promise_invoke_and_set(std::promise<void>& p,
-    F& f, ASIO_MOVE_ARG(Args)... args)
-{
-#if !defined(ASIO_NO_EXCEPTIONS)
-  try
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-  {
-    f(ASIO_MOVE_CAST(Args)(args)...);
-    p.set_value();
-  }
-#if !defined(ASIO_NO_EXCEPTIONS)
-  catch (...)
-  {
-    p.set_exception(std::current_exception());
-  }
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-}
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-template <typename T, typename F>
-inline void promise_invoke_and_set(std::promise<T>& p, F& f)
-{
-#if !defined(ASIO_NO_EXCEPTIONS)
-  try
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-  {
-    p.set_value(f());
-  }
-#if !defined(ASIO_NO_EXCEPTIONS)
-  catch (...)
-  {
-    p.set_exception(std::current_exception());
-  }
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-}
-
-template <typename F, typename Args>
-inline void promise_invoke_and_set(std::promise<void>& p, F& f)
-{
-#if !defined(ASIO_NO_EXCEPTIONS)
-  try
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-  {
-    f();
-    p.set_value();
-#if !defined(ASIO_NO_EXCEPTIONS)
-  }
-  catch (...)
-  {
-    p.set_exception(std::current_exception());
-  }
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-}
-
-#if defined(ASIO_NO_EXCEPTIONS)
-
-#define ASIO_PRIVATE_PROMISE_INVOKE_DEF(n) \
-  template <typename T, typename F, ASIO_VARIADIC_TPARAMS(n)> \
-  inline void promise_invoke_and_set(std::promise<T>& p, \
-      F& f, ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  { \
-    p.set_value(f(ASIO_VARIADIC_MOVE_ARGS(n))); \
-  } \
-  \
-  template <typename F, ASIO_VARIADIC_TPARAMS(n)> \
-  inline void promise_invoke_and_set(std::promise<void>& p, \
-      F& f, ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  { \
-    f(ASIO_VARIADIC_MOVE_ARGS(n)); \
-    p.set_value(); \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_PROMISE_INVOKE_DEF)
-#undef ASIO_PRIVATE_PROMISE_INVOKE_DEF
-
-#else // defined(ASIO_NO_EXCEPTIONS)
-
-#define ASIO_PRIVATE_PROMISE_INVOKE_DEF(n) \
-  template <typename T, typename F, ASIO_VARIADIC_TPARAMS(n)> \
-  inline void promise_invoke_and_set(std::promise<T>& p, \
-      F& f, ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  { \
-    try \
-    { \
-      p.set_value(f(ASIO_VARIADIC_MOVE_ARGS(n))); \
-    } \
-    catch (...) \
-    { \
-      p.set_exception(std::current_exception()); \
-    } \
-  } \
-  \
-  template <typename F, ASIO_VARIADIC_TPARAMS(n)> \
-  inline void promise_invoke_and_set(std::promise<void>& p, \
-      F& f, ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  { \
-    try \
-    { \
-      f(ASIO_VARIADIC_MOVE_ARGS(n)); \
-      p.set_value(); \
-    } \
-    catch (...) \
-    { \
-      p.set_exception(std::current_exception()); \
-    } \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_PROMISE_INVOKE_DEF)
-#undef ASIO_PRIVATE_PROMISE_INVOKE_DEF
-
-#endif // defined(ASIO_NO_EXCEPTIONS)
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-// A function object adapter to invoke a nullary function object and capture
-// any exception thrown into a promise.
-template <typename T, typename F>
-class promise_invoker
-{
-public:
-  promise_invoker(const shared_ptr<std::promise<T> >& p,
-      ASIO_MOVE_ARG(F) f)
-    : p_(p), f_(ASIO_MOVE_CAST(F)(f))
-  {
-  }
-
-  void operator()()
-  {
-#if !defined(ASIO_NO_EXCEPTIONS)
-    try
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-    {
-      f_();
-    }
-#if !defined(ASIO_NO_EXCEPTIONS)
-    catch (...)
-    {
-      p_->set_exception(std::current_exception());
-    }
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-  }
-
-private:
-  shared_ptr<std::promise<T> > p_;
-  typename decay<F>::type f_;
-};
-
-// An executor that adapts the system_executor to capture any exeption thrown
-// by a submitted function object and save it into a promise.
-template <typename T>
-class promise_executor
-{
-public:
-  explicit promise_executor(const shared_ptr<std::promise<T> >& p)
-    : p_(p)
-  {
-  }
-
-  execution_context& context() const ASIO_NOEXCEPT
-  {
-    return system_executor().context();
-  }
-
-  void on_work_started() const ASIO_NOEXCEPT {}
-  void on_work_finished() const ASIO_NOEXCEPT {}
-
-  template <typename F, typename A>
-  void dispatch(ASIO_MOVE_ARG(F) f, const A&) const
-  {
-    promise_invoker<T, F>(p_, ASIO_MOVE_CAST(F)(f))();
-  }
-
-  template <typename F, typename A>
-  void post(ASIO_MOVE_ARG(F) f, const A& a) const
-  {
-    system_executor().post(
-        promise_invoker<T, F>(p_, ASIO_MOVE_CAST(F)(f)), a);
-  }
-
-  template <typename F, typename A>
-  void defer(ASIO_MOVE_ARG(F) f, const A& a) const
-  {
-    system_executor().defer(
-        promise_invoker<T, F>(p_, ASIO_MOVE_CAST(F)(f)), a);
-  }
-
-  friend bool operator==(const promise_executor& a,
-      const promise_executor& b) ASIO_NOEXCEPT
-  {
-    return a.p_ == b.p_;
-  }
-
-  friend bool operator!=(const promise_executor& a,
-      const promise_executor& b) ASIO_NOEXCEPT
-  {
-    return a.p_ != b.p_;
-  }
-
-private:
-  shared_ptr<std::promise<T> > p_;
-};
-
-// The base class for all completion handlers that create promises.
-template <typename T>
-class promise_creator
-{
-public:
-  typedef promise_executor<T> executor_type;
-
-  executor_type get_executor() const ASIO_NOEXCEPT
-  {
-    return executor_type(p_);
-  }
-
-  typedef std::future<T> future_type;
-
-  future_type get_future()
-  {
-    return p_->get_future();
-  }
-
-protected:
-  template <typename Allocator>
-  void create_promise(const Allocator& a)
-  {
-    ASIO_REBIND_ALLOC(Allocator, char) b(a);
-    p_ = std::allocate_shared<std::promise<T>>(b, std::allocator_arg, b);
-  }
-
-  shared_ptr<std::promise<T> > p_;
-};
-
-// For completion signature void().
-class promise_handler_0
-  : public promise_creator<void>
-{
-public:
-  void operator()()
-  {
-    this->p_->set_value();
-  }
-};
-
-// For completion signature void(error_code).
-class promise_handler_ec_0
-  : public promise_creator<void>
-{
-public:
-  void operator()(const asio::error_code& ec)
-  {
-    if (ec)
-    {
-      this->p_->set_exception(
-          std::make_exception_ptr(
-            asio::system_error(ec)));
-    }
-    else
-    {
-      this->p_->set_value();
-    }
-  }
-};
-
-// For completion signature void(exception_ptr).
-class promise_handler_ex_0
-  : public promise_creator<void>
-{
-public:
-  void operator()(const std::exception_ptr& ex)
-  {
-    if (ex)
-    {
-      this->p_->set_exception(ex);
-    }
-    else
-    {
-      this->p_->set_value();
-    }
-  }
-};
-
-// For completion signature void(T).
-template <typename T>
-class promise_handler_1
-  : public promise_creator<T>
-{
-public:
-  template <typename Arg>
-  void operator()(ASIO_MOVE_ARG(Arg) arg)
-  {
-    this->p_->set_value(ASIO_MOVE_CAST(Arg)(arg));
-  }
-};
-
-// For completion signature void(error_code, T).
-template <typename T>
-class promise_handler_ec_1
-  : public promise_creator<T>
-{
-public:
-  template <typename Arg>
-  void operator()(const asio::error_code& ec,
-      ASIO_MOVE_ARG(Arg) arg)
-  {
-    if (ec)
-    {
-      this->p_->set_exception(
-          std::make_exception_ptr(
-            asio::system_error(ec)));
-    }
-    else
-      this->p_->set_value(ASIO_MOVE_CAST(Arg)(arg));
-  }
-};
-
-// For completion signature void(exception_ptr, T).
-template <typename T>
-class promise_handler_ex_1
-  : public promise_creator<T>
-{
-public:
-  template <typename Arg>
-  void operator()(const std::exception_ptr& ex,
-      ASIO_MOVE_ARG(Arg) arg)
-  {
-    if (ex)
-      this->p_->set_exception(ex);
-    else
-      this->p_->set_value(ASIO_MOVE_CAST(Arg)(arg));
-  }
-};
-
-// For completion signature void(T1, ..., Tn);
-template <typename T>
-class promise_handler_n
-  : public promise_creator<T>
-{
-public:
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  template <typename... Args>
-  void operator()(ASIO_MOVE_ARG(Args)... args)
-  {
-    this->p_->set_value(
-        std::forward_as_tuple(
-          ASIO_MOVE_CAST(Args)(args)...));
-  }
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#define ASIO_PRIVATE_CALL_OP_DEF(n) \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  void operator()(ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  {\
-    this->p_->set_value( \
-        std::forward_as_tuple( \
-          ASIO_VARIADIC_MOVE_ARGS(n))); \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_CALL_OP_DEF)
-#undef ASIO_PRIVATE_CALL_OP_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-};
-
-// For completion signature void(error_code, T1, ..., Tn);
-template <typename T>
-class promise_handler_ec_n
-  : public promise_creator<T>
-{
-public:
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  template <typename... Args>
-  void operator()(const asio::error_code& ec,
-      ASIO_MOVE_ARG(Args)... args)
-  {
-    if (ec)
-    {
-      this->p_->set_exception(
-          std::make_exception_ptr(
-            asio::system_error(ec)));
-    }
-    else
-    {
-      this->p_->set_value(
-          std::forward_as_tuple(
-            ASIO_MOVE_CAST(Args)(args)...));
-    }
-  }
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#define ASIO_PRIVATE_CALL_OP_DEF(n) \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  void operator()(const asio::error_code& ec, \
-      ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  {\
-    if (ec) \
-    { \
-      this->p_->set_exception( \
-          std::make_exception_ptr( \
-            asio::system_error(ec))); \
-    } \
-    else \
-    { \
-      this->p_->set_value( \
-          std::forward_as_tuple( \
-            ASIO_VARIADIC_MOVE_ARGS(n))); \
-    } \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_CALL_OP_DEF)
-#undef ASIO_PRIVATE_CALL_OP_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-};
-
-// For completion signature void(exception_ptr, T1, ..., Tn);
-template <typename T>
-class promise_handler_ex_n
-  : public promise_creator<T>
-{
-public:
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  template <typename... Args>
-  void operator()(const std::exception_ptr& ex,
-      ASIO_MOVE_ARG(Args)... args)
-  {
-    if (ex)
-      this->p_->set_exception(ex);
-    else
-    {
-      this->p_->set_value(
-          std::forward_as_tuple(
-            ASIO_MOVE_CAST(Args)(args)...));
-    }
-  }
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#define ASIO_PRIVATE_CALL_OP_DEF(n) \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  void operator()(const std::exception_ptr& ex, \
-      ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  {\
-    if (ex) \
-      this->p_->set_exception(ex); \
-    else \
-    { \
-      this->p_->set_value( \
-          std::forward_as_tuple( \
-            ASIO_VARIADIC_MOVE_ARGS(n))); \
-    } \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_CALL_OP_DEF)
-#undef ASIO_PRIVATE_CALL_OP_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-};
-
-// Helper template to choose the appropriate concrete promise handler
-// implementation based on the supplied completion signature.
-template <typename> class promise_handler_selector;
-
-template <>
-class promise_handler_selector<void()>
-  : public promise_handler_0 {};
-
-template <>
-class promise_handler_selector<void(asio::error_code)>
-  : public promise_handler_ec_0 {};
-
-template <>
-class promise_handler_selector<void(std::exception_ptr)>
-  : public promise_handler_ex_0 {};
-
-template <typename Arg>
-class promise_handler_selector<void(Arg)>
-  : public promise_handler_1<Arg> {};
-
-template <typename Arg>
-class promise_handler_selector<void(asio::error_code, Arg)>
-  : public promise_handler_ec_1<Arg> {};
-
-template <typename Arg>
-class promise_handler_selector<void(std::exception_ptr, Arg)>
-  : public promise_handler_ex_1<Arg> {};
-
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-template <typename... Arg>
-class promise_handler_selector<void(Arg...)>
-  : public promise_handler_n<std::tuple<Arg...> > {};
-
-template <typename... Arg>
-class promise_handler_selector<void(asio::error_code, Arg...)>
-  : public promise_handler_ec_n<std::tuple<Arg...> > {};
-
-template <typename... Arg>
-class promise_handler_selector<void(std::exception_ptr, Arg...)>
-  : public promise_handler_ex_n<std::tuple<Arg...> > {};
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#define ASIO_PRIVATE_PROMISE_SELECTOR_DEF(n) \
-  template <typename Arg, ASIO_VARIADIC_TPARAMS(n)> \
-  class promise_handler_selector< \
-    void(Arg, ASIO_VARIADIC_TARGS(n))> \
-      : public promise_handler_n< \
-        std::tuple<Arg, ASIO_VARIADIC_TARGS(n)> > {}; \
-  \
-  template <typename Arg, ASIO_VARIADIC_TPARAMS(n)> \
-  class promise_handler_selector< \
-    void(asio::error_code, Arg, ASIO_VARIADIC_TARGS(n))> \
-      : public promise_handler_ec_n< \
-        std::tuple<Arg, ASIO_VARIADIC_TARGS(n)> > {}; \
-  \
-  template <typename Arg, ASIO_VARIADIC_TPARAMS(n)> \
-  class promise_handler_selector< \
-    void(std::exception_ptr, Arg, ASIO_VARIADIC_TARGS(n))> \
-      : public promise_handler_ex_n< \
-        std::tuple<Arg, ASIO_VARIADIC_TARGS(n)> > {}; \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_PROMISE_SELECTOR_DEF)
-#undef ASIO_PRIVATE_PROMISE_SELECTOR_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-// Completion handlers produced from the use_future completion token, when not
-// using use_future::operator().
-template <typename Signature, typename Allocator>
-class promise_handler
-  : public promise_handler_selector<Signature>
-{
-public:
-  typedef Allocator allocator_type;
-  typedef void result_type;
-
-  promise_handler(use_future_t<Allocator> u)
-    : allocator_(u.get_allocator())
-  {
-    this->create_promise(allocator_);
-  }
-
-  allocator_type get_allocator() const ASIO_NOEXCEPT
-  {
-    return allocator_;
-  }
-
-private:
-  Allocator allocator_;
-};
-
-template <typename Function, typename Signature, typename Allocator>
-inline void asio_handler_invoke(Function& f,
-    promise_handler<Signature, Allocator>* h)
-{
-  typename promise_handler<Signature, Allocator>::executor_type
-    ex(h->get_executor());
-  ex.dispatch(ASIO_MOVE_CAST(Function)(f), std::allocator<void>());
-}
-
-template <typename Function, typename Signature, typename Allocator>
-inline void asio_handler_invoke(const Function& f,
-    promise_handler<Signature, Allocator>* h)
-{
-  typename promise_handler<Signature, Allocator>::executor_type
-    ex(h->get_executor());
-  ex.dispatch(f, std::allocator<void>());
-}
-
-// Helper base class for async_result specialisation.
-template <typename Signature, typename Allocator>
-class promise_async_result
-{
-public:
-  typedef promise_handler<Signature, Allocator> completion_handler_type;
-  typedef typename completion_handler_type::future_type return_type;
-
-  explicit promise_async_result(completion_handler_type& h)
-    : future_(h.get_future())
-  {
-  }
-
-  return_type get()
-  {
-    return ASIO_MOVE_CAST(return_type)(future_);
-  }
-
-private:
-  return_type future_;
-};
-
-// Return value from use_future::operator().
-template <typename Function, typename Allocator>
-class packaged_token
-{
-public:
-  packaged_token(Function f, const Allocator& a)
-    : function_(ASIO_MOVE_CAST(Function)(f)),
-      allocator_(a)
-  {
-  }
-
-//private:
-  Function function_;
-  Allocator allocator_;
-};
-
-// Completion handlers produced from the use_future completion token, when
-// using use_future::operator().
-template <typename Function, typename Allocator, typename Result>
-class packaged_handler
-  : public promise_creator<Result>
-{
-public:
-  typedef Allocator allocator_type;
-  typedef void result_type;
-
-  packaged_handler(packaged_token<Function, Allocator> t)
-    : function_(ASIO_MOVE_CAST(Function)(t.function_)),
-      allocator_(t.allocator_)
-  {
-    this->create_promise(allocator_);
-  }
-
-  allocator_type get_allocator() const ASIO_NOEXCEPT
-  {
-    return allocator_;
-  }
-
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  template <typename... Args>
-  void operator()(ASIO_MOVE_ARG(Args)... args)
-  {
-    (promise_invoke_and_set)(*this->p_,
-        function_, ASIO_MOVE_CAST(Args)(args)...);
-  }
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-  void operator()()
-  {
-    (promise_invoke_and_set)(*this->p_, function_);
-  }
-
-#define ASIO_PRIVATE_CALL_OP_DEF(n) \
-  template <ASIO_VARIADIC_TPARAMS(n)> \
-  void operator()(ASIO_VARIADIC_MOVE_PARAMS(n)) \
-  {\
-    (promise_invoke_and_set)(*this->p_, \
-        function_, ASIO_VARIADIC_MOVE_ARGS(n)); \
-  } \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_CALL_OP_DEF)
-#undef ASIO_PRIVATE_CALL_OP_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-private:
-  Function function_;
-  Allocator allocator_;
-};
-
-template <typename Function,
-    typename Function1, typename Allocator, typename Result>
-inline void asio_handler_invoke(Function& f,
-    packaged_handler<Function1, Allocator, Result>* h)
-{
-  typename packaged_handler<Function1, Allocator, Result>::executor_type
-    ex(h->get_executor());
-  ex.dispatch(ASIO_MOVE_CAST(Function)(f), std::allocator<void>());
-}
-
-template <typename Function,
-    typename Function1, typename Allocator, typename Result>
-inline void asio_handler_invoke(const Function& f,
-    packaged_handler<Function1, Allocator, Result>* h)
-{
-  typename packaged_handler<Function1, Allocator, Result>::executor_type
-    ex(h->get_executor());
-  ex.dispatch(f, std::allocator<void>());
-}
-
-// Helper base class for async_result specialisation.
-template <typename Function, typename Allocator, typename Result>
-class packaged_async_result
-{
-public:
-  typedef packaged_handler<Function, Allocator, Result> completion_handler_type;
-  typedef typename completion_handler_type::future_type return_type;
-
-  explicit packaged_async_result(completion_handler_type& h)
-    : future_(h.get_future())
-  {
-  }
-
-  return_type get()
-  {
-    return ASIO_MOVE_CAST(return_type)(future_);
-  }
-
-private:
-  return_type future_;
-};
-
-} // namespace detail
-
-template <typename Allocator> template <typename Function>
-inline detail::packaged_token<typename decay<Function>::type, Allocator>
-use_future_t<Allocator>::operator()(ASIO_MOVE_ARG(Function) f) const
-{
-  return detail::packaged_token<typename decay<Function>::type, Allocator>(
-      ASIO_MOVE_CAST(Function)(f), allocator_);
-}
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-template <typename Allocator, typename Result, typename... Args>
-class async_result<use_future_t<Allocator>, Result(Args...)>
-  : public detail::promise_async_result<
-      void(typename decay<Args>::type...), Allocator>
-{
-public:
-  explicit async_result(
-    typename detail::promise_async_result<void(typename decay<Args>::type...),
-      Allocator>::completion_handler_type& h)
-    : detail::promise_async_result<
-        void(typename decay<Args>::type...), Allocator>(h)
-  {
-  }
-};
-
-template <typename Function, typename Allocator,
-    typename Result, typename... Args>
-class async_result<detail::packaged_token<Function, Allocator>, Result(Args...)>
-  : public detail::packaged_async_result<Function, Allocator,
-      typename result_of<Function(Args...)>::type>
-{
-public:
-  explicit async_result(
-    typename detail::packaged_async_result<Function, Allocator,
-      typename result_of<Function(Args...)>::type>::completion_handler_type& h)
-    : detail::packaged_async_result<Function, Allocator,
-        typename result_of<Function(Args...)>::type>(h)
-  {
-  }
-};
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-template <typename Allocator, typename Result>
-class async_result<use_future_t<Allocator>, Result()>
-  : public detail::promise_async_result<void(), Allocator>
-{
-public:
-  explicit async_result(
-    typename detail::promise_async_result<
-      void(), Allocator>::completion_handler_type& h)
-    : detail::promise_async_result<void(), Allocator>(h)
-  {
-  }
-};
-
-template <typename Function, typename Allocator, typename Result>
-class async_result<detail::packaged_token<Function, Allocator>, Result()>
-  : public detail::packaged_async_result<Function, Allocator,
-      typename result_of<Function()>::type>
-{
-public:
-  explicit async_result(
-    typename detail::packaged_async_result<Function, Allocator,
-      typename result_of<Function()>::type>::completion_handler_type& h)
-    : detail::packaged_async_result<Function, Allocator,
-        typename result_of<Function()>::type>(h)
-  {
-  }
-};
-
-#define ASIO_PRIVATE_ASYNC_RESULT_DEF(n) \
-  template <typename Allocator, \
-      typename Result, ASIO_VARIADIC_TPARAMS(n)> \
-  class async_result<use_future_t<Allocator>, \
-      Result(ASIO_VARIADIC_TARGS(n))> \
-    : public detail::promise_async_result< \
-        void(ASIO_VARIADIC_DECAY(n)), Allocator> \
-  { \
-  public: \
-    explicit async_result( \
-      typename detail::promise_async_result< \
-        void(ASIO_VARIADIC_DECAY(n)), \
-        Allocator>::completion_handler_type& h) \
-      : detail::promise_async_result< \
-          void(ASIO_VARIADIC_DECAY(n)), Allocator>(h) \
-    { \
-    } \
-  }; \
-  \
-  template <typename Function, typename Allocator, \
-      typename Result, ASIO_VARIADIC_TPARAMS(n)> \
-  class async_result<detail::packaged_token<Function, Allocator>, \
-      Result(ASIO_VARIADIC_TARGS(n))> \
-    : public detail::packaged_async_result<Function, Allocator, \
-        typename result_of<Function(ASIO_VARIADIC_TARGS(n))>::type> \
-  { \
-  public: \
-    explicit async_result( \
-      typename detail::packaged_async_result<Function, Allocator, \
-        typename result_of<Function(ASIO_VARIADIC_TARGS(n))>::type \
-        >::completion_handler_type& h) \
-      : detail::packaged_async_result<Function, Allocator, \
-          typename result_of<Function(ASIO_VARIADIC_TARGS(n))>::type>(h) \
-    { \
-    } \
-  }; \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_ASYNC_RESULT_DEF)
-#undef ASIO_PRIVATE_ASYNC_RESULT_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-template <typename Allocator, typename Signature>
-struct handler_type<use_future_t<Allocator>, Signature>
-{
-  typedef typename async_result<use_future_t<Allocator>,
-    Signature>::completion_handler_type type;
-};
-
-template <typename Signature, typename Allocator>
-class async_result<detail::promise_handler<Signature, Allocator> >
-  : public detail::promise_async_result<Signature, Allocator>
-{
-public:
-  typedef typename detail::promise_async_result<
-    Signature, Allocator>::return_type type;
-
-  explicit async_result(
-    typename detail::promise_async_result<
-      Signature, Allocator>::completion_handler_type& h)
-    : detail::promise_async_result<Signature, Allocator>(h)
-  {
-  }
-};
-
-template <typename Function, typename Allocator, typename Signature>
-struct handler_type<detail::packaged_token<Function, Allocator>, Signature>
-{
-  typedef typename async_result<detail::packaged_token<Function, Allocator>,
-    Signature>::completion_handler_type type;
-};
-
-template <typename Function, typename Allocator, typename Result>
-class async_result<detail::packaged_handler<Function, Allocator, Result> >
-  : public detail::packaged_async_result<Function, Allocator, Result>
-{
-public:
-  typedef typename detail::packaged_async_result<
-    Function, Allocator, Result>::return_type type;
-
-  explicit async_result(
-    typename detail::packaged_async_result<
-      Function, Allocator, Result>::completion_handler_type& h)
-    : detail::packaged_async_result<Function, Allocator, Result>(h)
-  {
-  }
-};
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_USE_FUTURE_HPP
diff --git a/tools/sdk/include/asio/asio/impl/write.hpp b/tools/sdk/include/asio/asio/impl/write.hpp
deleted file mode 100644
index d07e8d3e077..00000000000
--- a/tools/sdk/include/asio/asio/impl/write.hpp
+++ /dev/null
@@ -1,674 +0,0 @@
-//
-// impl/write.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_WRITE_HPP
-#define ASIO_IMPL_WRITE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/buffer.hpp"
-#include "asio/completion_condition.hpp"
-#include "asio/detail/array_fwd.hpp"
-#include "asio/detail/base_from_completion_cond.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/consuming_buffers.hpp"
-#include "asio/detail/dependent_type.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail
-{
-  template <typename SyncWriteStream, typename ConstBufferSequence,
-      typename ConstBufferIterator, typename CompletionCondition>
-  std::size_t write_buffer_sequence(SyncWriteStream& s,
-      const ConstBufferSequence& buffers, const ConstBufferIterator&,
-      CompletionCondition completion_condition, asio::error_code& ec)
-  {
-    ec = asio::error_code();
-    asio::detail::consuming_buffers<const_buffer,
-        ConstBufferSequence, ConstBufferIterator> tmp(buffers);
-    while (!tmp.empty())
-    {
-      if (std::size_t max_size = detail::adapt_completion_condition_result(
-            completion_condition(ec, tmp.total_consumed())))
-        tmp.consume(s.write_some(tmp.prepare(max_size), ec));
-      else
-        break;
-    }
-    return tmp.total_consumed();;
-  }
-} // namespace detail
-
-template <typename SyncWriteStream, typename ConstBufferSequence,
-    typename CompletionCondition>
-inline std::size_t write(SyncWriteStream& s, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition, asio::error_code& ec,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type*)
-{
-  return detail::write_buffer_sequence(s, buffers,
-      asio::buffer_sequence_begin(buffers), completion_condition, ec);
-}
-
-template <typename SyncWriteStream, typename ConstBufferSequence>
-inline std::size_t write(SyncWriteStream& s, const ConstBufferSequence& buffers,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type*)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = write(s, buffers, transfer_all(), ec);
-  asio::detail::throw_error(ec, "write");
-  return bytes_transferred;
-}
-
-template <typename SyncWriteStream, typename ConstBufferSequence>
-inline std::size_t write(SyncWriteStream& s, const ConstBufferSequence& buffers,
-    asio::error_code& ec,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type*)
-{
-  return write(s, buffers, transfer_all(), ec);
-}
-
-template <typename SyncWriteStream, typename ConstBufferSequence,
-    typename CompletionCondition>
-inline std::size_t write(SyncWriteStream& s, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type*)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = write(s, buffers, completion_condition, ec);
-  asio::detail::throw_error(ec, "write");
-  return bytes_transferred;
-}
-
-template <typename SyncWriteStream, typename DynamicBuffer,
-    typename CompletionCondition>
-std::size_t write(SyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition, asio::error_code& ec,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  typename decay<DynamicBuffer>::type b(
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers));
-
-  std::size_t bytes_transferred = write(s, b.data(), completion_condition, ec);
-  b.consume(bytes_transferred);
-  return bytes_transferred;
-}
-
-template <typename SyncWriteStream, typename DynamicBuffer>
-inline std::size_t write(SyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = write(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-      transfer_all(), ec);
-  asio::detail::throw_error(ec, "write");
-  return bytes_transferred;
-}
-
-template <typename SyncWriteStream, typename DynamicBuffer>
-inline std::size_t write(SyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    asio::error_code& ec,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  return write(s, ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-      transfer_all(), ec);
-}
-
-template <typename SyncWriteStream, typename DynamicBuffer,
-    typename CompletionCondition>
-inline std::size_t write(SyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = write(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-      completion_condition, ec);
-  asio::detail::throw_error(ec, "write");
-  return bytes_transferred;
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-template <typename SyncWriteStream, typename Allocator,
-    typename CompletionCondition>
-inline std::size_t write(SyncWriteStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition, asio::error_code& ec)
-{
-  return write(s, basic_streambuf_ref<Allocator>(b), completion_condition, ec);
-}
-
-template <typename SyncWriteStream, typename Allocator>
-inline std::size_t write(SyncWriteStream& s,
-    asio::basic_streambuf<Allocator>& b)
-{
-  return write(s, basic_streambuf_ref<Allocator>(b));
-}
-
-template <typename SyncWriteStream, typename Allocator>
-inline std::size_t write(SyncWriteStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    asio::error_code& ec)
-{
-  return write(s, basic_streambuf_ref<Allocator>(b), ec);
-}
-
-template <typename SyncWriteStream, typename Allocator,
-    typename CompletionCondition>
-inline std::size_t write(SyncWriteStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition)
-{
-  return write(s, basic_streambuf_ref<Allocator>(b), completion_condition);
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-namespace detail
-{
-  template <typename AsyncWriteStream, typename ConstBufferSequence,
-      typename ConstBufferIterator, typename CompletionCondition,
-      typename WriteHandler>
-  class write_op
-    : detail::base_from_completion_cond<CompletionCondition>
-  {
-  public:
-    write_op(AsyncWriteStream& stream, const ConstBufferSequence& buffers,
-        CompletionCondition completion_condition, WriteHandler& handler)
-      : detail::base_from_completion_cond<
-          CompletionCondition>(completion_condition),
-        stream_(stream),
-        buffers_(buffers),
-        start_(0),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    write_op(const write_op& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        stream_(other.stream_),
-        buffers_(other.buffers_),
-        start_(other.start_),
-        handler_(other.handler_)
-    {
-    }
-
-    write_op(write_op&& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        stream_(other.stream_),
-        buffers_(other.buffers_),
-        start_(other.start_),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      std::size_t max_size;
-      switch (start_ = start)
-      {
-        case 1:
-        max_size = this->check_for_completion(ec, buffers_.total_consumed());
-        do
-        {
-          stream_.async_write_some(buffers_.prepare(max_size),
-              ASIO_MOVE_CAST(write_op)(*this));
-          return; default:
-          buffers_.consume(bytes_transferred);
-          if ((!ec && bytes_transferred == 0) || buffers_.empty())
-            break;
-          max_size = this->check_for_completion(ec, buffers_.total_consumed());
-        } while (max_size > 0);
-
-        handler_(ec, buffers_.total_consumed());
-      }
-    }
-
-  //private:
-    AsyncWriteStream& stream_;
-    asio::detail::consuming_buffers<const_buffer,
-        ConstBufferSequence, ConstBufferIterator> buffers_;
-    int start_;
-    WriteHandler handler_;
-  };
-
-  template <typename AsyncWriteStream, typename ConstBufferSequence,
-      typename ConstBufferIterator, typename CompletionCondition,
-      typename WriteHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      write_op<AsyncWriteStream, ConstBufferSequence, ConstBufferIterator,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncWriteStream, typename ConstBufferSequence,
-      typename ConstBufferIterator, typename CompletionCondition,
-      typename WriteHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      write_op<AsyncWriteStream, ConstBufferSequence, ConstBufferIterator,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncWriteStream, typename ConstBufferSequence,
-      typename ConstBufferIterator, typename CompletionCondition,
-      typename WriteHandler>
-  inline bool asio_handler_is_continuation(
-      write_op<AsyncWriteStream, ConstBufferSequence, ConstBufferIterator,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncWriteStream,
-      typename ConstBufferSequence, typename ConstBufferIterator,
-      typename CompletionCondition, typename WriteHandler>
-  inline void asio_handler_invoke(Function& function,
-      write_op<AsyncWriteStream, ConstBufferSequence, ConstBufferIterator,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncWriteStream,
-      typename ConstBufferSequence, typename ConstBufferIterator,
-      typename CompletionCondition, typename WriteHandler>
-  inline void asio_handler_invoke(const Function& function,
-      write_op<AsyncWriteStream, ConstBufferSequence, ConstBufferIterator,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename AsyncWriteStream, typename ConstBufferSequence,
-      typename ConstBufferIterator, typename CompletionCondition,
-      typename WriteHandler>
-  inline void start_write_buffer_sequence_op(AsyncWriteStream& stream,
-      const ConstBufferSequence& buffers, const ConstBufferIterator&,
-      CompletionCondition completion_condition, WriteHandler& handler)
-  {
-    detail::write_op<AsyncWriteStream, ConstBufferSequence,
-      ConstBufferIterator, CompletionCondition, WriteHandler>(
-        stream, buffers, completion_condition, handler)(
-          asio::error_code(), 0, 1);
-  }
-
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncWriteStream, typename ConstBufferSequence,
-    typename ConstBufferIterator, typename CompletionCondition,
-    typename WriteHandler, typename Allocator>
-struct associated_allocator<
-    detail::write_op<AsyncWriteStream, ConstBufferSequence,
-      ConstBufferIterator, CompletionCondition, WriteHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<WriteHandler, Allocator>::type type;
-
-  static type get(
-      const detail::write_op<AsyncWriteStream, ConstBufferSequence,
-        ConstBufferIterator, CompletionCondition, WriteHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<WriteHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncWriteStream, typename ConstBufferSequence,
-    typename ConstBufferIterator, typename CompletionCondition,
-    typename WriteHandler, typename Executor>
-struct associated_executor<
-    detail::write_op<AsyncWriteStream, ConstBufferSequence,
-      ConstBufferIterator, CompletionCondition, WriteHandler>,
-    Executor>
-{
-  typedef typename associated_executor<WriteHandler, Executor>::type type;
-
-  static type get(
-      const detail::write_op<AsyncWriteStream, ConstBufferSequence,
-        ConstBufferIterator, CompletionCondition, WriteHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<WriteHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncWriteStream, typename ConstBufferSequence,
-  typename CompletionCondition, typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a WriteHandler.
-  ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-  async_completion<WriteHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::start_write_buffer_sequence_op(s, buffers,
-      asio::buffer_sequence_begin(buffers), completion_condition,
-      init.completion_handler);
-
-  return init.result.get();
-}
-
-template <typename AsyncWriteStream, typename ConstBufferSequence,
-    typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s, const ConstBufferSequence& buffers,
-    ASIO_MOVE_ARG(WriteHandler) handler,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a WriteHandler.
-  ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-  async_completion<WriteHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::start_write_buffer_sequence_op(s, buffers,
-      asio::buffer_sequence_begin(buffers), transfer_all(),
-      init.completion_handler);
-
-  return init.result.get();
-}
-
-namespace detail
-{
-  template <typename AsyncWriteStream, typename DynamicBuffer,
-      typename CompletionCondition, typename WriteHandler>
-  class write_dynbuf_op
-  {
-  public:
-    template <typename BufferSequence>
-    write_dynbuf_op(AsyncWriteStream& stream,
-        ASIO_MOVE_ARG(BufferSequence) buffers,
-        CompletionCondition completion_condition, WriteHandler& handler)
-      : stream_(stream),
-        buffers_(ASIO_MOVE_CAST(BufferSequence)(buffers)),
-        completion_condition_(
-          ASIO_MOVE_CAST(CompletionCondition)(completion_condition)),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    write_dynbuf_op(const write_dynbuf_op& other)
-      : stream_(other.stream_),
-        buffers_(other.buffers_),
-        completion_condition_(other.completion_condition_),
-        handler_(other.handler_)
-    {
-    }
-
-    write_dynbuf_op(write_dynbuf_op&& other)
-      : stream_(other.stream_),
-        buffers_(ASIO_MOVE_CAST(DynamicBuffer)(other.buffers_)),
-        completion_condition_(
-          ASIO_MOVE_CAST(CompletionCondition)(
-            other.completion_condition_)),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      switch (start)
-      {
-        case 1:
-        async_write(stream_, buffers_.data(), completion_condition_,
-            ASIO_MOVE_CAST(write_dynbuf_op)(*this));
-        return; default:
-        buffers_.consume(bytes_transferred);
-        handler_(ec, static_cast<const std::size_t&>(bytes_transferred));
-      }
-    }
-
-  //private:
-    AsyncWriteStream& stream_;
-    DynamicBuffer buffers_;
-    CompletionCondition completion_condition_;
-    WriteHandler handler_;
-  };
-
-  template <typename AsyncWriteStream, typename DynamicBuffer,
-      typename CompletionCondition, typename WriteHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      write_dynbuf_op<AsyncWriteStream, DynamicBuffer,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncWriteStream, typename DynamicBuffer,
-      typename CompletionCondition, typename WriteHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      write_dynbuf_op<AsyncWriteStream, DynamicBuffer,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncWriteStream, typename DynamicBuffer,
-      typename CompletionCondition, typename WriteHandler>
-  inline bool asio_handler_is_continuation(
-      write_dynbuf_op<AsyncWriteStream, DynamicBuffer,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    return asio_handler_cont_helpers::is_continuation(
-        this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncWriteStream,
-      typename DynamicBuffer, typename CompletionCondition,
-      typename WriteHandler>
-  inline void asio_handler_invoke(Function& function,
-      write_dynbuf_op<AsyncWriteStream, DynamicBuffer,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncWriteStream,
-      typename DynamicBuffer, typename CompletionCondition,
-      typename WriteHandler>
-  inline void asio_handler_invoke(const Function& function,
-      write_dynbuf_op<AsyncWriteStream, DynamicBuffer,
-        CompletionCondition, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncWriteStream, typename DynamicBuffer,
-    typename CompletionCondition, typename WriteHandler, typename Allocator>
-struct associated_allocator<
-    detail::write_dynbuf_op<AsyncWriteStream,
-      DynamicBuffer, CompletionCondition, WriteHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<WriteHandler, Allocator>::type type;
-
-  static type get(
-      const detail::write_dynbuf_op<AsyncWriteStream,
-        DynamicBuffer, CompletionCondition, WriteHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<WriteHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncWriteStream, typename DynamicBuffer,
-    typename CompletionCondition, typename WriteHandler, typename Executor>
-struct associated_executor<
-    detail::write_dynbuf_op<AsyncWriteStream,
-      DynamicBuffer, CompletionCondition, WriteHandler>,
-    Executor>
-{
-  typedef typename associated_executor<WriteHandler, Executor>::type type;
-
-  static type get(
-      const detail::write_dynbuf_op<AsyncWriteStream,
-        DynamicBuffer, CompletionCondition, WriteHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<WriteHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncWriteStream,
-    typename DynamicBuffer, typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_MOVE_ARG(WriteHandler) handler,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  return async_write(s,
-      ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-      transfer_all(), ASIO_MOVE_CAST(WriteHandler)(handler));
-}
-
-template <typename AsyncWriteStream, typename DynamicBuffer,
-    typename CompletionCondition, typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type*)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a WriteHandler.
-  ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-  async_completion<WriteHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::write_dynbuf_op<AsyncWriteStream,
-    typename decay<DynamicBuffer>::type,
-      CompletionCondition, ASIO_HANDLER_TYPE(
-        WriteHandler, void (asio::error_code, std::size_t))>(
-          s, ASIO_MOVE_CAST(DynamicBuffer)(buffers),
-            completion_condition, init.completion_handler)(
-              asio::error_code(), 0, 1);
-
-  return init.result.get();
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-template <typename AsyncWriteStream, typename Allocator, typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    ASIO_MOVE_ARG(WriteHandler) handler)
-{
-  return async_write(s, basic_streambuf_ref<Allocator>(b),
-      ASIO_MOVE_CAST(WriteHandler)(handler));
-}
-
-template <typename AsyncWriteStream, typename Allocator,
-    typename CompletionCondition, typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler)
-{
-  return async_write(s, basic_streambuf_ref<Allocator>(b),
-      completion_condition, ASIO_MOVE_CAST(WriteHandler)(handler));
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_WRITE_HPP
diff --git a/tools/sdk/include/asio/asio/impl/write_at.hpp b/tools/sdk/include/asio/asio/impl/write_at.hpp
deleted file mode 100644
index cc6f336f1d1..00000000000
--- a/tools/sdk/include/asio/asio/impl/write_at.hpp
+++ /dev/null
@@ -1,572 +0,0 @@
-//
-// impl/write_at.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IMPL_WRITE_AT_HPP
-#define ASIO_IMPL_WRITE_AT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/associated_allocator.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/buffer.hpp"
-#include "asio/completion_condition.hpp"
-#include "asio/detail/array_fwd.hpp"
-#include "asio/detail/base_from_completion_cond.hpp"
-#include "asio/detail/bind_handler.hpp"
-#include "asio/detail/consuming_buffers.hpp"
-#include "asio/detail/dependent_type.hpp"
-#include "asio/detail/handler_alloc_helpers.hpp"
-#include "asio/detail/handler_cont_helpers.hpp"
-#include "asio/detail/handler_invoke_helpers.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail
-{
-  template <typename SyncRandomAccessWriteDevice, typename ConstBufferSequence,
-      typename ConstBufferIterator, typename CompletionCondition>
-  std::size_t write_at_buffer_sequence(SyncRandomAccessWriteDevice& d,
-      uint64_t offset, const ConstBufferSequence& buffers,
-      const ConstBufferIterator&, CompletionCondition completion_condition,
-      asio::error_code& ec)
-  {
-    ec = asio::error_code();
-    asio::detail::consuming_buffers<const_buffer,
-        ConstBufferSequence, ConstBufferIterator> tmp(buffers);
-    while (!tmp.empty())
-    {
-      if (std::size_t max_size = detail::adapt_completion_condition_result(
-            completion_condition(ec, tmp.total_consumed())))
-      {
-        tmp.consume(d.write_some_at(offset + tmp.total_consumed(),
-              tmp.prepare(max_size), ec));
-      }
-      else
-        break;
-    }
-    return tmp.total_consumed();;
-  }
-} // namespace detail
-
-template <typename SyncRandomAccessWriteDevice, typename ConstBufferSequence,
-    typename CompletionCondition>
-std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition, asio::error_code& ec)
-{
-  return detail::write_at_buffer_sequence(d, offset, buffers,
-      asio::buffer_sequence_begin(buffers), completion_condition, ec);
-}
-
-template <typename SyncRandomAccessWriteDevice, typename ConstBufferSequence>
-inline std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = write_at(
-      d, offset, buffers, transfer_all(), ec);
-  asio::detail::throw_error(ec, "write_at");
-  return bytes_transferred;
-}
-
-template <typename SyncRandomAccessWriteDevice, typename ConstBufferSequence>
-inline std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers,
-    asio::error_code& ec)
-{
-  return write_at(d, offset, buffers, transfer_all(), ec);
-}
-
-template <typename SyncRandomAccessWriteDevice, typename ConstBufferSequence,
-    typename CompletionCondition>
-inline std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = write_at(
-      d, offset, buffers, completion_condition, ec);
-  asio::detail::throw_error(ec, "write_at");
-  return bytes_transferred;
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-template <typename SyncRandomAccessWriteDevice, typename Allocator,
-    typename CompletionCondition>
-std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition, asio::error_code& ec)
-{
-  std::size_t bytes_transferred = write_at(
-      d, offset, b.data(), completion_condition, ec);
-  b.consume(bytes_transferred);
-  return bytes_transferred;
-}
-
-template <typename SyncRandomAccessWriteDevice, typename Allocator>
-inline std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = write_at(d, offset, b, transfer_all(), ec);
-  asio::detail::throw_error(ec, "write_at");
-  return bytes_transferred;
-}
-
-template <typename SyncRandomAccessWriteDevice, typename Allocator>
-inline std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    asio::error_code& ec)
-{
-  return write_at(d, offset, b, transfer_all(), ec);
-}
-
-template <typename SyncRandomAccessWriteDevice, typename Allocator,
-    typename CompletionCondition>
-inline std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition)
-{
-  asio::error_code ec;
-  std::size_t bytes_transferred = write_at(
-      d, offset, b, completion_condition, ec);
-  asio::detail::throw_error(ec, "write_at");
-  return bytes_transferred;
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-namespace detail
-{
-  template <typename AsyncRandomAccessWriteDevice,
-      typename ConstBufferSequence, typename ConstBufferIterator,
-      typename CompletionCondition, typename WriteHandler>
-  class write_at_op
-    : detail::base_from_completion_cond<CompletionCondition>
-  {
-  public:
-    write_at_op(AsyncRandomAccessWriteDevice& device,
-        uint64_t offset, const ConstBufferSequence& buffers,
-        CompletionCondition completion_condition, WriteHandler& handler)
-      : detail::base_from_completion_cond<
-          CompletionCondition>(completion_condition),
-        device_(device),
-        offset_(offset),
-        buffers_(buffers),
-        start_(0),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    write_at_op(const write_at_op& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        device_(other.device_),
-        offset_(other.offset_),
-        buffers_(other.buffers_),
-        start_(other.start_),
-        handler_(other.handler_)
-    {
-    }
-
-    write_at_op(write_at_op&& other)
-      : detail::base_from_completion_cond<CompletionCondition>(other),
-        device_(other.device_),
-        offset_(other.offset_),
-        buffers_(other.buffers_),
-        start_(other.start_),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        std::size_t bytes_transferred, int start = 0)
-    {
-      std::size_t max_size;
-      switch (start_ = start)
-      {
-        case 1:
-        max_size = this->check_for_completion(ec, buffers_.total_consumed());
-        do
-        {
-          device_.async_write_some_at(
-              offset_ + buffers_.total_consumed(), buffers_.prepare(max_size),
-              ASIO_MOVE_CAST(write_at_op)(*this));
-          return; default:
-          buffers_.consume(bytes_transferred);
-          if ((!ec && bytes_transferred == 0) || buffers_.empty())
-            break;
-          max_size = this->check_for_completion(ec, buffers_.total_consumed());
-        } while (max_size > 0);
-
-        handler_(ec, buffers_.total_consumed());
-      }
-    }
-
-  //private:
-    AsyncRandomAccessWriteDevice& device_;
-    uint64_t offset_;
-    asio::detail::consuming_buffers<const_buffer,
-        ConstBufferSequence, ConstBufferIterator> buffers_;
-    int start_;
-    WriteHandler handler_;
-  };
-
-  template <typename AsyncRandomAccessWriteDevice,
-      typename ConstBufferSequence, typename ConstBufferIterator,
-      typename CompletionCondition, typename WriteHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      write_at_op<AsyncRandomAccessWriteDevice, ConstBufferSequence,
-        ConstBufferIterator, CompletionCondition, WriteHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename AsyncRandomAccessWriteDevice,
-      typename ConstBufferSequence, typename ConstBufferIterator,
-      typename CompletionCondition, typename WriteHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      write_at_op<AsyncRandomAccessWriteDevice, ConstBufferSequence,
-        ConstBufferIterator, CompletionCondition, WriteHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename AsyncRandomAccessWriteDevice,
-      typename ConstBufferSequence, typename ConstBufferIterator,
-      typename CompletionCondition, typename WriteHandler>
-  inline bool asio_handler_is_continuation(
-      write_at_op<AsyncRandomAccessWriteDevice, ConstBufferSequence,
-        ConstBufferIterator, CompletionCondition, WriteHandler>* this_handler)
-  {
-    return this_handler->start_ == 0 ? true
-      : asio_handler_cont_helpers::is_continuation(
-          this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncRandomAccessWriteDevice,
-      typename ConstBufferSequence, typename ConstBufferIterator,
-      typename CompletionCondition, typename WriteHandler>
-  inline void asio_handler_invoke(Function& function,
-      write_at_op<AsyncRandomAccessWriteDevice, ConstBufferSequence,
-        ConstBufferIterator, CompletionCondition, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename AsyncRandomAccessWriteDevice,
-      typename ConstBufferSequence, typename ConstBufferIterator,
-      typename CompletionCondition, typename WriteHandler>
-  inline void asio_handler_invoke(const Function& function,
-      write_at_op<AsyncRandomAccessWriteDevice, ConstBufferSequence,
-        ConstBufferIterator, CompletionCondition, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename AsyncRandomAccessWriteDevice,
-      typename ConstBufferSequence, typename ConstBufferIterator,
-      typename CompletionCondition, typename WriteHandler>
-  inline void start_write_at_buffer_sequence_op(AsyncRandomAccessWriteDevice& d,
-      uint64_t offset, const ConstBufferSequence& buffers,
-      const ConstBufferIterator&, CompletionCondition completion_condition,
-      WriteHandler& handler)
-  {
-    detail::write_at_op<AsyncRandomAccessWriteDevice, ConstBufferSequence,
-      ConstBufferIterator, CompletionCondition, WriteHandler>(
-        d, offset, buffers, completion_condition, handler)(
-          asio::error_code(), 0, 1);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncRandomAccessWriteDevice,
-    typename ConstBufferSequence, typename ConstBufferIterator,
-    typename CompletionCondition, typename WriteHandler, typename Allocator>
-struct associated_allocator<
-    detail::write_at_op<AsyncRandomAccessWriteDevice, ConstBufferSequence,
-      ConstBufferIterator, CompletionCondition, WriteHandler>,
-    Allocator>
-{
-  typedef typename associated_allocator<WriteHandler, Allocator>::type type;
-
-  static type get(
-      const detail::write_at_op<AsyncRandomAccessWriteDevice,
-        ConstBufferSequence, ConstBufferIterator,
-        CompletionCondition, WriteHandler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<WriteHandler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename AsyncRandomAccessWriteDevice,
-    typename ConstBufferSequence, typename ConstBufferIterator,
-    typename CompletionCondition, typename WriteHandler, typename Executor>
-struct associated_executor<
-    detail::write_at_op<AsyncRandomAccessWriteDevice, ConstBufferSequence,
-      ConstBufferIterator, CompletionCondition, WriteHandler>,
-    Executor>
-{
-  typedef typename associated_executor<WriteHandler, Executor>::type type;
-
-  static type get(
-      const detail::write_at_op<AsyncRandomAccessWriteDevice,
-        ConstBufferSequence, ConstBufferIterator,
-        CompletionCondition, WriteHandler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<WriteHandler, Executor>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncRandomAccessWriteDevice, typename ConstBufferSequence,
-    typename CompletionCondition, typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write_at(AsyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a WriteHandler.
-  ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-  async_completion<WriteHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::start_write_at_buffer_sequence_op(d, offset, buffers,
-      asio::buffer_sequence_begin(buffers), completion_condition,
-      init.completion_handler);
-
-  return init.result.get();
-}
-
-template <typename AsyncRandomAccessWriteDevice, typename ConstBufferSequence,
-    typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write_at(AsyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers,
-    ASIO_MOVE_ARG(WriteHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a WriteHandler.
-  ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-  async_completion<WriteHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  detail::start_write_at_buffer_sequence_op(d, offset, buffers,
-      asio::buffer_sequence_begin(buffers), transfer_all(),
-      init.completion_handler);
-
-  return init.result.get();
-}
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-namespace detail
-{
-  template <typename Allocator, typename WriteHandler>
-  class write_at_streambuf_op
-  {
-  public:
-    write_at_streambuf_op(
-        asio::basic_streambuf<Allocator>& streambuf,
-        WriteHandler& handler)
-      : streambuf_(streambuf),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(handler))
-    {
-    }
-
-#if defined(ASIO_HAS_MOVE)
-    write_at_streambuf_op(const write_at_streambuf_op& other)
-      : streambuf_(other.streambuf_),
-        handler_(other.handler_)
-    {
-    }
-
-    write_at_streambuf_op(write_at_streambuf_op&& other)
-      : streambuf_(other.streambuf_),
-        handler_(ASIO_MOVE_CAST(WriteHandler)(other.handler_))
-    {
-    }
-#endif // defined(ASIO_HAS_MOVE)
-
-    void operator()(const asio::error_code& ec,
-        const std::size_t bytes_transferred)
-    {
-      streambuf_.consume(bytes_transferred);
-      handler_(ec, bytes_transferred);
-    }
-
-  //private:
-    asio::basic_streambuf<Allocator>& streambuf_;
-    WriteHandler handler_;
-  };
-
-  template <typename Allocator, typename WriteHandler>
-  inline void* asio_handler_allocate(std::size_t size,
-      write_at_streambuf_op<Allocator, WriteHandler>* this_handler)
-  {
-    return asio_handler_alloc_helpers::allocate(
-        size, this_handler->handler_);
-  }
-
-  template <typename Allocator, typename WriteHandler>
-  inline void asio_handler_deallocate(void* pointer, std::size_t size,
-      write_at_streambuf_op<Allocator, WriteHandler>* this_handler)
-  {
-    asio_handler_alloc_helpers::deallocate(
-        pointer, size, this_handler->handler_);
-  }
-
-  template <typename Allocator, typename WriteHandler>
-  inline bool asio_handler_is_continuation(
-      write_at_streambuf_op<Allocator, WriteHandler>* this_handler)
-  {
-    return asio_handler_cont_helpers::is_continuation(
-        this_handler->handler_);
-  }
-
-  template <typename Function, typename Allocator, typename WriteHandler>
-  inline void asio_handler_invoke(Function& function,
-      write_at_streambuf_op<Allocator, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Function, typename Allocator, typename WriteHandler>
-  inline void asio_handler_invoke(const Function& function,
-      write_at_streambuf_op<Allocator, WriteHandler>* this_handler)
-  {
-    asio_handler_invoke_helpers::invoke(
-        function, this_handler->handler_);
-  }
-
-  template <typename Allocator, typename WriteHandler>
-  inline write_at_streambuf_op<Allocator, WriteHandler>
-  make_write_at_streambuf_op(
-      asio::basic_streambuf<Allocator>& b, WriteHandler handler)
-  {
-    return write_at_streambuf_op<Allocator, WriteHandler>(b, handler);
-  }
-} // namespace detail
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-template <typename Allocator, typename WriteHandler, typename Allocator1>
-struct associated_allocator<
-    detail::write_at_streambuf_op<Allocator, WriteHandler>,
-    Allocator1>
-{
-  typedef typename associated_allocator<WriteHandler, Allocator1>::type type;
-
-  static type get(
-      const detail::write_at_streambuf_op<Allocator, WriteHandler>& h,
-      const Allocator1& a = Allocator1()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<WriteHandler, Allocator1>::get(h.handler_, a);
-  }
-};
-
-template <typename Executor, typename WriteHandler, typename Executor1>
-struct associated_executor<
-    detail::write_at_streambuf_op<Executor, WriteHandler>,
-    Executor1>
-{
-  typedef typename associated_executor<WriteHandler, Executor1>::type type;
-
-  static type get(
-      const detail::write_at_streambuf_op<Executor, WriteHandler>& h,
-      const Executor1& ex = Executor1()) ASIO_NOEXCEPT
-  {
-    return associated_executor<WriteHandler, Executor1>::get(h.handler_, ex);
-  }
-};
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-template <typename AsyncRandomAccessWriteDevice, typename Allocator,
-    typename CompletionCondition, typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write_at(AsyncRandomAccessWriteDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a WriteHandler.
-  ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-  async_completion<WriteHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  async_write_at(d, offset, b.data(), completion_condition,
-    detail::write_at_streambuf_op<Allocator, ASIO_HANDLER_TYPE(
-      WriteHandler, void (asio::error_code, std::size_t))>(
-        b, init.completion_handler));
-
-  return init.result.get();
-}
-
-template <typename AsyncRandomAccessWriteDevice, typename Allocator,
-    typename WriteHandler>
-inline ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write_at(AsyncRandomAccessWriteDevice& d,
-    uint64_t offset, asio::basic_streambuf<Allocator>& b,
-    ASIO_MOVE_ARG(WriteHandler) handler)
-{
-  // If you get an error on the following line it means that your handler does
-  // not meet the documented type requirements for a WriteHandler.
-  ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-  async_completion<WriteHandler,
-    void (asio::error_code, std::size_t)> init(handler);
-
-  async_write_at(d, offset, b.data(), transfer_all(),
-    detail::write_at_streambuf_op<Allocator, ASIO_HANDLER_TYPE(
-      WriteHandler, void (asio::error_code, std::size_t))>(
-        b, init.completion_handler));
-
-  return init.result.get();
-}
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IMPL_WRITE_AT_HPP
diff --git a/tools/sdk/include/asio/asio/io_context.hpp b/tools/sdk/include/asio/asio/io_context.hpp
deleted file mode 100644
index 4d93be44b2c..00000000000
--- a/tools/sdk/include/asio/asio/io_context.hpp
+++ /dev/null
@@ -1,876 +0,0 @@
-//
-// io_context.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IO_CONTEXT_HPP
-#define ASIO_IO_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <stdexcept>
-#include <typeinfo>
-#include "asio/async_result.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/wrapped_handler.hpp"
-#include "asio/error_code.hpp"
-#include "asio/execution_context.hpp"
-
-#if defined(ASIO_HAS_CHRONO)
-# include "asio/detail/chrono.hpp"
-#endif // defined(ASIO_HAS_CHRONO)
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-# include "asio/detail/winsock_init.hpp"
-#elif defined(__sun) || defined(__QNX__) || defined(__hpux) || defined(_AIX) \
-  || defined(__osf__)
-# include "asio/detail/signal_init.hpp"
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail {
-#if defined(ASIO_HAS_IOCP)
-  typedef class win_iocp_io_context io_context_impl;
-  class win_iocp_overlapped_ptr;
-#else
-  typedef class scheduler io_context_impl;
-#endif
-} // namespace detail
-
-/// Provides core I/O functionality.
-/**
- * The io_context class provides the core I/O functionality for users of the
- * asynchronous I/O objects, including:
- *
- * @li asio::ip::tcp::socket
- * @li asio::ip::tcp::acceptor
- * @li asio::ip::udp::socket
- * @li asio::deadline_timer.
- *
- * The io_context class also includes facilities intended for developers of
- * custom asynchronous services.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe, with the specific exceptions of the restart()
- * and notify_fork() functions. Calling restart() while there are unfinished
- * run(), run_one(), run_for(), run_until(), poll() or poll_one() calls results
- * in undefined behaviour. The notify_fork() function should not be called
- * while any io_context function, or any function on an I/O object that is
- * associated with the io_context, is being called in another thread.
- *
- * @par Concepts:
- * Dispatcher.
- *
- * @par Synchronous and asynchronous operations
- *
- * Synchronous operations on I/O objects implicitly run the io_context object
- * for an individual operation. The io_context functions run(), run_one(),
- * run_for(), run_until(), poll() or poll_one() must be called for the
- * io_context to perform asynchronous operations on behalf of a C++ program.
- * Notification that an asynchronous operation has completed is delivered by
- * invocation of the associated handler. Handlers are invoked only by a thread
- * that is currently calling any overload of run(), run_one(), run_for(),
- * run_until(), poll() or poll_one() for the io_context.
- *
- * @par Effect of exceptions thrown from handlers
- *
- * If an exception is thrown from a handler, the exception is allowed to
- * propagate through the throwing thread's invocation of run(), run_one(),
- * run_for(), run_until(), poll() or poll_one(). No other threads that are
- * calling any of these functions are affected. It is then the responsibility
- * of the application to catch the exception.
- *
- * After the exception has been caught, the run(), run_one(), run_for(),
- * run_until(), poll() or poll_one() call may be restarted @em without the need
- * for an intervening call to restart(). This allows the thread to rejoin the
- * io_context object's thread pool without impacting any other threads in the
- * pool.
- *
- * For example:
- *
- * @code
- * asio::io_context io_context;
- * ...
- * for (;;)
- * {
- *   try
- *   {
- *     io_context.run();
- *     break; // run() exited normally
- *   }
- *   catch (my_exception& e)
- *   {
- *     // Deal with exception as appropriate.
- *   }
- * }
- * @endcode
- *
- * @par Submitting arbitrary tasks to the io_context
- *
- * To submit functions to the io_context, use the @ref asio::dispatch,
- * @ref asio::post or @ref asio::defer free functions.
- *
- * For example:
- *
- * @code void my_task()
- * {
- *   ...
- * }
- *
- * ...
- *
- * asio::io_context io_context;
- *
- * // Submit a function to the io_context.
- * asio::post(io_context, my_task);
- *
- * // Submit a lambda object to the io_context.
- * asio::post(io_context,
- *     []()
- *     {
- *       ...
- *     });
- *
- * // Run the io_context until it runs out of work.
- * io_context.run(); @endcode
- *
- * @par Stopping the io_context from running out of work
- *
- * Some applications may need to prevent an io_context object's run() call from
- * returning when there is no more work to do. For example, the io_context may
- * be being run in a background thread that is launched prior to the
- * application's asynchronous operations. The run() call may be kept running by
- * creating an object of type
- * asio::executor_work_guard<io_context::executor_type>:
- *
- * @code asio::io_context io_context;
- * asio::executor_work_guard<asio::io_context::executor_type>
- *   = asio::make_work_guard(io_context);
- * ... @endcode
- *
- * To effect a shutdown, the application will then need to call the io_context
- * object's stop() member function. This will cause the io_context run() call
- * to return as soon as possible, abandoning unfinished operations and without
- * permitting ready handlers to be dispatched.
- *
- * Alternatively, if the application requires that all operations and handlers
- * be allowed to finish normally, the work object may be explicitly reset.
- *
- * @code asio::io_context io_context;
- * asio::executor_work_guard<asio::io_context::executor_type>
- *   = asio::make_work_guard(io_context);
- * ...
- * work.reset(); // Allow run() to exit. @endcode
- */
-class io_context
-  : public execution_context
-{
-private:
-  typedef detail::io_context_impl impl_type;
-#if defined(ASIO_HAS_IOCP)
-  friend class detail::win_iocp_overlapped_ptr;
-#endif
-
-public:
-  class executor_type;
-  friend class executor_type;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  class work;
-  friend class work;
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  class service;
-
-#if !defined(ASIO_NO_EXTENSIONS)
-  class strand;
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-  /// The type used to count the number of handlers executed by the context.
-  typedef std::size_t count_type;
-
-  /// Constructor.
-  ASIO_DECL io_context();
-
-  /// Constructor.
-  /**
-   * Construct with a hint about the required level of concurrency.
-   *
-   * @param concurrency_hint A suggestion to the implementation on how many
-   * threads it should allow to run simultaneously.
-   */
-  ASIO_DECL explicit io_context(int concurrency_hint);
-
-  /// Destructor.
-  /**
-   * On destruction, the io_context performs the following sequence of
-   * operations:
-   *
-   * @li For each service object @c svc in the io_context set, in reverse order
-   * of the beginning of service object lifetime, performs
-   * @c svc->shutdown().
-   *
-   * @li Uninvoked handler objects that were scheduled for deferred invocation
-   * on the io_context, or any associated strand, are destroyed.
-   *
-   * @li For each service object @c svc in the io_context set, in reverse order
-   * of the beginning of service object lifetime, performs
-   * <tt>delete static_cast<io_context::service*>(svc)</tt>.
-   *
-   * @note The destruction sequence described above permits programs to
-   * simplify their resource management by using @c shared_ptr<>. Where an
-   * object's lifetime is tied to the lifetime of a connection (or some other
-   * sequence of asynchronous operations), a @c shared_ptr to the object would
-   * be bound into the handlers for all asynchronous operations associated with
-   * it. This works as follows:
-   *
-   * @li When a single connection ends, all associated asynchronous operations
-   * complete. The corresponding handler objects are destroyed, and all
-   * @c shared_ptr references to the objects are destroyed.
-   *
-   * @li To shut down the whole program, the io_context function stop() is
-   * called to terminate any run() calls as soon as possible. The io_context
-   * destructor defined above destroys all handlers, causing all @c shared_ptr
-   * references to all connection objects to be destroyed.
-   */
-  ASIO_DECL ~io_context();
-
-  /// Obtains the executor associated with the io_context.
-  executor_type get_executor() ASIO_NOEXCEPT;
-
-  /// Run the io_context object's event processing loop.
-  /**
-   * The run() function blocks until all work has finished and there are no
-   * more handlers to be dispatched, or until the io_context has been stopped.
-   *
-   * Multiple threads may call the run() function to set up a pool of threads
-   * from which the io_context may execute handlers. All threads that are
-   * waiting in the pool are equivalent and the io_context may choose any one
-   * of them to invoke a handler.
-   *
-   * A normal exit from the run() function implies that the io_context object
-   * is stopped (the stopped() function returns @c true). Subsequent calls to
-   * run(), run_one(), poll() or poll_one() will return immediately unless there
-   * is a prior call to restart().
-   *
-   * @return The number of handlers that were executed.
-   *
-   * @note Calling the run() function from a thread that is currently calling
-   * one of run(), run_one(), run_for(), run_until(), poll() or poll_one() on
-   * the same io_context object may introduce the potential for deadlock. It is
-   * the caller's reponsibility to avoid this.
-   *
-   * The poll() function may also be used to dispatch ready handlers, but
-   * without blocking.
-   */
-  ASIO_DECL count_type run();
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use non-error_code overload.) Run the io_context object's
-  /// event processing loop.
-  /**
-   * The run() function blocks until all work has finished and there are no
-   * more handlers to be dispatched, or until the io_context has been stopped.
-   *
-   * Multiple threads may call the run() function to set up a pool of threads
-   * from which the io_context may execute handlers. All threads that are
-   * waiting in the pool are equivalent and the io_context may choose any one
-   * of them to invoke a handler.
-   *
-   * A normal exit from the run() function implies that the io_context object
-   * is stopped (the stopped() function returns @c true). Subsequent calls to
-   * run(), run_one(), poll() or poll_one() will return immediately unless there
-   * is a prior call to restart().
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of handlers that were executed.
-   *
-   * @note Calling the run() function from a thread that is currently calling
-   * one of run(), run_one(), run_for(), run_until(), poll() or poll_one() on
-   * the same io_context object may introduce the potential for deadlock. It is
-   * the caller's reponsibility to avoid this.
-   *
-   * The poll() function may also be used to dispatch ready handlers, but
-   * without blocking.
-   */
-  ASIO_DECL count_type run(asio::error_code& ec);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-#if defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-  /// Run the io_context object's event processing loop for a specified
-  /// duration.
-  /**
-   * The run_for() function blocks until all work has finished and there are no
-   * more handlers to be dispatched, until the io_context has been stopped, or
-   * until the specified duration has elapsed.
-   *
-   * @param rel_time The duration for which the call may block.
-   *
-   * @return The number of handlers that were executed.
-   */
-  template <typename Rep, typename Period>
-  std::size_t run_for(const chrono::duration<Rep, Period>& rel_time);
-
-  /// Run the io_context object's event processing loop until a specified time.
-  /**
-   * The run_until() function blocks until all work has finished and there are
-   * no more handlers to be dispatched, until the io_context has been stopped,
-   * or until the specified time has been reached.
-   *
-   * @param abs_time The time point until which the call may block.
-   *
-   * @return The number of handlers that were executed.
-   */
-  template <typename Clock, typename Duration>
-  std::size_t run_until(const chrono::time_point<Clock, Duration>& abs_time);
-#endif // defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-
-  /// Run the io_context object's event processing loop to execute at most one
-  /// handler.
-  /**
-   * The run_one() function blocks until one handler has been dispatched, or
-   * until the io_context has been stopped.
-   *
-   * @return The number of handlers that were executed. A zero return value
-   * implies that the io_context object is stopped (the stopped() function
-   * returns @c true). Subsequent calls to run(), run_one(), poll() or
-   * poll_one() will return immediately unless there is a prior call to
-   * restart().
-   *
-   * @note Calling the run_one() function from a thread that is currently
-   * calling one of run(), run_one(), run_for(), run_until(), poll() or
-   * poll_one() on the same io_context object may introduce the potential for
-   * deadlock. It is the caller's reponsibility to avoid this.
-   */
-  ASIO_DECL count_type run_one();
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use non-error_code overlaod.) Run the io_context object's
-  /// event processing loop to execute at most one handler.
-  /**
-   * The run_one() function blocks until one handler has been dispatched, or
-   * until the io_context has been stopped.
-   *
-   * @return The number of handlers that were executed. A zero return value
-   * implies that the io_context object is stopped (the stopped() function
-   * returns @c true). Subsequent calls to run(), run_one(), poll() or
-   * poll_one() will return immediately unless there is a prior call to
-   * restart().
-   *
-   * @return The number of handlers that were executed.
-   *
-   * @note Calling the run_one() function from a thread that is currently
-   * calling one of run(), run_one(), run_for(), run_until(), poll() or
-   * poll_one() on the same io_context object may introduce the potential for
-   * deadlock. It is the caller's reponsibility to avoid this.
-   */
-  ASIO_DECL count_type run_one(asio::error_code& ec);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-#if defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-  /// Run the io_context object's event processing loop for a specified duration
-  /// to execute at most one handler.
-  /**
-   * The run_one_for() function blocks until one handler has been dispatched,
-   * until the io_context has been stopped, or until the specified duration has
-   * elapsed.
-   *
-   * @param rel_time The duration for which the call may block.
-   *
-   * @return The number of handlers that were executed.
-   */
-  template <typename Rep, typename Period>
-  std::size_t run_one_for(const chrono::duration<Rep, Period>& rel_time);
-
-  /// Run the io_context object's event processing loop until a specified time
-  /// to execute at most one handler.
-  /**
-   * The run_one_until() function blocks until one handler has been dispatched,
-   * until the io_context has been stopped, or until the specified time has
-   * been reached.
-   *
-   * @param abs_time The time point until which the call may block.
-   *
-   * @return The number of handlers that were executed.
-   */
-  template <typename Clock, typename Duration>
-  std::size_t run_one_until(
-      const chrono::time_point<Clock, Duration>& abs_time);
-#endif // defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-
-  /// Run the io_context object's event processing loop to execute ready
-  /// handlers.
-  /**
-   * The poll() function runs handlers that are ready to run, without blocking,
-   * until the io_context has been stopped or there are no more ready handlers.
-   *
-   * @return The number of handlers that were executed.
-   */
-  ASIO_DECL count_type poll();
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use non-error_code overload.) Run the io_context object's
-  /// event processing loop to execute ready handlers.
-  /**
-   * The poll() function runs handlers that are ready to run, without blocking,
-   * until the io_context has been stopped or there are no more ready handlers.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of handlers that were executed.
-   */
-  ASIO_DECL count_type poll(asio::error_code& ec);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Run the io_context object's event processing loop to execute one ready
-  /// handler.
-  /**
-   * The poll_one() function runs at most one handler that is ready to run,
-   * without blocking.
-   *
-   * @return The number of handlers that were executed.
-   */
-  ASIO_DECL count_type poll_one();
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use non-error_code overload.) Run the io_context object's
-  /// event processing loop to execute one ready handler.
-  /**
-   * The poll_one() function runs at most one handler that is ready to run,
-   * without blocking.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @return The number of handlers that were executed.
-   */
-  ASIO_DECL count_type poll_one(asio::error_code& ec);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Stop the io_context object's event processing loop.
-  /**
-   * This function does not block, but instead simply signals the io_context to
-   * stop. All invocations of its run() or run_one() member functions should
-   * return as soon as possible. Subsequent calls to run(), run_one(), poll()
-   * or poll_one() will return immediately until restart() is called.
-   */
-  ASIO_DECL void stop();
-
-  /// Determine whether the io_context object has been stopped.
-  /**
-   * This function is used to determine whether an io_context object has been
-   * stopped, either through an explicit call to stop(), or due to running out
-   * of work. When an io_context object is stopped, calls to run(), run_one(),
-   * poll() or poll_one() will return immediately without invoking any
-   * handlers.
-   *
-   * @return @c true if the io_context object is stopped, otherwise @c false.
-   */
-  ASIO_DECL bool stopped() const;
-
-  /// Restart the io_context in preparation for a subsequent run() invocation.
-  /**
-   * This function must be called prior to any second or later set of
-   * invocations of the run(), run_one(), poll() or poll_one() functions when a
-   * previous invocation of these functions returned due to the io_context
-   * being stopped or running out of work. After a call to restart(), the
-   * io_context object's stopped() function will return @c false.
-   *
-   * This function must not be called while there are any unfinished calls to
-   * the run(), run_one(), poll() or poll_one() functions.
-   */
-  ASIO_DECL void restart();
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use restart().) Reset the io_context in preparation for a
-  /// subsequent run() invocation.
-  /**
-   * This function must be called prior to any second or later set of
-   * invocations of the run(), run_one(), poll() or poll_one() functions when a
-   * previous invocation of these functions returned due to the io_context
-   * being stopped or running out of work. After a call to restart(), the
-   * io_context object's stopped() function will return @c false.
-   *
-   * This function must not be called while there are any unfinished calls to
-   * the run(), run_one(), poll() or poll_one() functions.
-   */
-  void reset();
-
-  /// (Deprecated: Use asio::dispatch().) Request the io_context to
-  /// invoke the given handler.
-  /**
-   * This function is used to ask the io_context to execute the given handler.
-   *
-   * The io_context guarantees that the handler will only be called in a thread
-   * in which the run(), run_one(), poll() or poll_one() member functions is
-   * currently being invoked. The handler may be executed inside this function
-   * if the guarantee can be met.
-   *
-   * @param handler The handler to be called. The io_context will make
-   * a copy of the handler object as required. The function signature of the
-   * handler must be: @code void handler(); @endcode
-   *
-   * @note This function throws an exception only if:
-   *
-   * @li the handler's @c asio_handler_allocate function; or
-   *
-   * @li the handler's copy constructor
-   *
-   * throws an exception.
-   */
-  template <typename LegacyCompletionHandler>
-  ASIO_INITFN_RESULT_TYPE(LegacyCompletionHandler, void ())
-  dispatch(ASIO_MOVE_ARG(LegacyCompletionHandler) handler);
-
-  /// (Deprecated: Use asio::post().) Request the io_context to invoke
-  /// the given handler and return immediately.
-  /**
-   * This function is used to ask the io_context to execute the given handler,
-   * but without allowing the io_context to call the handler from inside this
-   * function.
-   *
-   * The io_context guarantees that the handler will only be called in a thread
-   * in which the run(), run_one(), poll() or poll_one() member functions is
-   * currently being invoked.
-   *
-   * @param handler The handler to be called. The io_context will make
-   * a copy of the handler object as required. The function signature of the
-   * handler must be: @code void handler(); @endcode
-   *
-   * @note This function throws an exception only if:
-   *
-   * @li the handler's @c asio_handler_allocate function; or
-   *
-   * @li the handler's copy constructor
-   *
-   * throws an exception.
-   */
-  template <typename LegacyCompletionHandler>
-  ASIO_INITFN_RESULT_TYPE(LegacyCompletionHandler, void ())
-  post(ASIO_MOVE_ARG(LegacyCompletionHandler) handler);
-
-  /// (Deprecated: Use asio::bind_executor().) Create a new handler that
-  /// automatically dispatches the wrapped handler on the io_context.
-  /**
-   * This function is used to create a new handler function object that, when
-   * invoked, will automatically pass the wrapped handler to the io_context
-   * object's dispatch function.
-   *
-   * @param handler The handler to be wrapped. The io_context will make a copy
-   * of the handler object as required. The function signature of the handler
-   * must be: @code void handler(A1 a1, ... An an); @endcode
-   *
-   * @return A function object that, when invoked, passes the wrapped handler to
-   * the io_context object's dispatch function. Given a function object with the
-   * signature:
-   * @code R f(A1 a1, ... An an); @endcode
-   * If this function object is passed to the wrap function like so:
-   * @code io_context.wrap(f); @endcode
-   * then the return value is a function object with the signature
-   * @code void g(A1 a1, ... An an); @endcode
-   * that, when invoked, executes code equivalent to:
-   * @code io_context.dispatch(boost::bind(f, a1, ... an)); @endcode
-   */
-  template <typename Handler>
-#if defined(GENERATING_DOCUMENTATION)
-  unspecified
-#else
-  detail::wrapped_handler<io_context&, Handler>
-#endif
-  wrap(Handler handler);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-private:
-  // Helper function to add the implementation.
-  ASIO_DECL impl_type& add_impl(impl_type* impl);
-
-  // Backwards compatible overload for use with services derived from
-  // io_context::service.
-  template <typename Service>
-  friend Service& use_service(io_context& ioc);
-
-#if defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-  detail::winsock_init<> init_;
-#elif defined(__sun) || defined(__QNX__) || defined(__hpux) || defined(_AIX) \
-  || defined(__osf__)
-  detail::signal_init<> init_;
-#endif
-
-  // The implementation.
-  impl_type& impl_;
-};
-
-/// Executor used to submit functions to an io_context.
-class io_context::executor_type
-{
-public:
-  /// Obtain the underlying execution context.
-  io_context& context() const ASIO_NOEXCEPT;
-
-  /// Inform the io_context that it has some outstanding work to do.
-  /**
-   * This function is used to inform the io_context that some work has begun.
-   * This ensures that the io_context's run() and run_one() functions do not
-   * exit while the work is underway.
-   */
-  void on_work_started() const ASIO_NOEXCEPT;
-
-  /// Inform the io_context that some work is no longer outstanding.
-  /**
-   * This function is used to inform the io_context that some work has
-   * finished. Once the count of unfinished work reaches zero, the io_context
-   * is stopped and the run() and run_one() functions may exit.
-   */
-  void on_work_finished() const ASIO_NOEXCEPT;
-
-  /// Request the io_context to invoke the given function object.
-  /**
-   * This function is used to ask the io_context to execute the given function
-   * object. If the current thread is running the io_context, @c dispatch()
-   * executes the function before returning. Otherwise, the function will be
-   * scheduled to run on the io_context.
-   *
-   * @param f The function object to be called. The executor will make a copy
-   * of the handler object as required. The function signature of the function
-   * object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void dispatch(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Request the io_context to invoke the given function object.
-  /**
-   * This function is used to ask the io_context to execute the given function
-   * object. The function object will never be executed inside @c post().
-   * Instead, it will be scheduled to run on the io_context.
-   *
-   * @param f The function object to be called. The executor will make a copy
-   * of the handler object as required. The function signature of the function
-   * object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void post(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Request the io_context to invoke the given function object.
-  /**
-   * This function is used to ask the io_context to execute the given function
-   * object. The function object will never be executed inside @c defer().
-   * Instead, it will be scheduled to run on the io_context.
-   *
-   * If the current thread belongs to the io_context, @c defer() will delay
-   * scheduling the function object until the current thread returns control to
-   * the pool.
-   *
-   * @param f The function object to be called. The executor will make a copy
-   * of the handler object as required. The function signature of the function
-   * object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void defer(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Determine whether the io_context is running in the current thread.
-  /**
-   * @return @c true if the current thread is running the io_context. Otherwise
-   * returns @c false.
-   */
-  bool running_in_this_thread() const ASIO_NOEXCEPT;
-
-  /// Compare two executors for equality.
-  /**
-   * Two executors are equal if they refer to the same underlying io_context.
-   */
-  friend bool operator==(const executor_type& a,
-      const executor_type& b) ASIO_NOEXCEPT
-  {
-    return &a.io_context_ == &b.io_context_;
-  }
-
-  /// Compare two executors for inequality.
-  /**
-   * Two executors are equal if they refer to the same underlying io_context.
-   */
-  friend bool operator!=(const executor_type& a,
-      const executor_type& b) ASIO_NOEXCEPT
-  {
-    return &a.io_context_ != &b.io_context_;
-  }
-
-private:
-  friend class io_context;
-
-  // Constructor.
-  explicit executor_type(io_context& i) : io_context_(i) {}
-
-  // The underlying io_context.
-  io_context& io_context_;
-};
-
-#if !defined(ASIO_NO_DEPRECATED)
-/// (Deprecated: Use executor_work_guard.) Class to inform the io_context when
-/// it has work to do.
-/**
- * The work class is used to inform the io_context when work starts and
- * finishes. This ensures that the io_context object's run() function will not
- * exit while work is underway, and that it does exit when there is no
- * unfinished work remaining.
- *
- * The work class is copy-constructible so that it may be used as a data member
- * in a handler class. It is not assignable.
- */
-class io_context::work
-{
-public:
-  /// Constructor notifies the io_context that work is starting.
-  /**
-   * The constructor is used to inform the io_context that some work has begun.
-   * This ensures that the io_context object's run() function will not exit
-   * while the work is underway.
-   */
-  explicit work(asio::io_context& io_context);
-
-  /// Copy constructor notifies the io_context that work is starting.
-  /**
-   * The constructor is used to inform the io_context that some work has begun.
-   * This ensures that the io_context object's run() function will not exit
-   * while the work is underway.
-   */
-  work(const work& other);
-
-  /// Destructor notifies the io_context that the work is complete.
-  /**
-   * The destructor is used to inform the io_context that some work has
-   * finished. Once the count of unfinished work reaches zero, the io_context
-   * object's run() function is permitted to exit.
-   */
-  ~work();
-
-  /// Get the io_context associated with the work.
-  asio::io_context& get_io_context();
-
-  /// (Deprecated: Use get_io_context().) Get the io_context associated with the
-  /// work.
-  asio::io_context& get_io_service();
-
-private:
-  // Prevent assignment.
-  void operator=(const work& other);
-
-  // The io_context implementation.
-  detail::io_context_impl& io_context_impl_;
-};
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-/// Base class for all io_context services.
-class io_context::service
-  : public execution_context::service
-{
-public:
-  /// Get the io_context object that owns the service.
-  asio::io_context& get_io_context();
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// Get the io_context object that owns the service.
-  asio::io_context& get_io_service();
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-private:
-  /// Destroy all user-defined handler objects owned by the service.
-  ASIO_DECL virtual void shutdown();
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use shutdown().) Destroy all user-defined handler objects
-  /// owned by the service.
-  ASIO_DECL virtual void shutdown_service();
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Handle notification of a fork-related event to perform any necessary
-  /// housekeeping.
-  /**
-   * This function is not a pure virtual so that services only have to
-   * implement it if necessary. The default implementation does nothing.
-   */
-  ASIO_DECL virtual void notify_fork(
-      execution_context::fork_event event);
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use notify_fork().) Handle notification of a fork-related
-  /// event to perform any necessary housekeeping.
-  /**
-   * This function is not a pure virtual so that services only have to
-   * implement it if necessary. The default implementation does nothing.
-   */
-  ASIO_DECL virtual void fork_service(
-      execution_context::fork_event event);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-protected:
-  /// Constructor.
-  /**
-   * @param owner The io_context object that owns the service.
-   */
-  ASIO_DECL service(asio::io_context& owner);
-
-  /// Destructor.
-  ASIO_DECL virtual ~service();
-};
-
-namespace detail {
-
-// Special service base class to keep classes header-file only.
-template <typename Type>
-class service_base
-  : public asio::io_context::service
-{
-public:
-  static asio::detail::service_id<Type> id;
-
-  // Constructor.
-  service_base(asio::io_context& io_context)
-    : asio::io_context::service(io_context)
-  {
-  }
-};
-
-template <typename Type>
-asio::detail::service_id<Type> service_base<Type>::id;
-
-} // namespace detail
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/io_context.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/impl/io_context.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-// If both io_context.hpp and strand.hpp have been included, automatically
-// include the header file needed for the io_context::strand class.
-#if !defined(ASIO_NO_EXTENSIONS)
-# if defined(ASIO_STRAND_HPP)
-#  include "asio/io_context_strand.hpp"
-# endif // defined(ASIO_STRAND_HPP)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-#endif // ASIO_IO_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/io_context_strand.hpp b/tools/sdk/include/asio/asio/io_context_strand.hpp
deleted file mode 100644
index 3c596f125ea..00000000000
--- a/tools/sdk/include/asio/asio/io_context_strand.hpp
+++ /dev/null
@@ -1,384 +0,0 @@
-//
-// io_context_strand.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IO_CONTEXT_STRAND_HPP
-#define ASIO_IO_CONTEXT_STRAND_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_NO_EXTENSIONS)
-
-#include "asio/async_result.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/strand_service.hpp"
-#include "asio/detail/wrapped_handler.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides serialised handler execution.
-/**
- * The io_context::strand class provides the ability to post and dispatch
- * handlers with the guarantee that none of those handlers will execute
- * concurrently.
- *
- * @par Order of handler invocation
- * Given:
- *
- * @li a strand object @c s
- *
- * @li an object @c a meeting completion handler requirements
- *
- * @li an object @c a1 which is an arbitrary copy of @c a made by the
- * implementation
- *
- * @li an object @c b meeting completion handler requirements
- *
- * @li an object @c b1 which is an arbitrary copy of @c b made by the
- * implementation
- *
- * if any of the following conditions are true:
- *
- * @li @c s.post(a) happens-before @c s.post(b)
- * 
- * @li @c s.post(a) happens-before @c s.dispatch(b), where the latter is
- * performed outside the strand
- * 
- * @li @c s.dispatch(a) happens-before @c s.post(b), where the former is
- * performed outside the strand
- * 
- * @li @c s.dispatch(a) happens-before @c s.dispatch(b), where both are
- * performed outside the strand
- *   
- * then @c asio_handler_invoke(a1, &a1) happens-before
- * @c asio_handler_invoke(b1, &b1).
- * 
- * Note that in the following case:
- * @code async_op_1(..., s.wrap(a));
- * async_op_2(..., s.wrap(b)); @endcode
- * the completion of the first async operation will perform @c s.dispatch(a),
- * and the second will perform @c s.dispatch(b), but the order in which those
- * are performed is unspecified. That is, you cannot state whether one
- * happens-before the other. Therefore none of the above conditions are met and
- * no ordering guarantee is made.
- *
- * @note The implementation makes no guarantee that handlers posted or
- * dispatched through different @c strand objects will be invoked concurrently.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Dispatcher.
- */
-class io_context::strand
-{
-public:
-  /// Constructor.
-  /**
-   * Constructs the strand.
-   *
-   * @param io_context The io_context object that the strand will use to
-   * dispatch handlers that are ready to be run.
-   */
-  explicit strand(asio::io_context& io_context)
-    : service_(asio::use_service<
-        asio::detail::strand_service>(io_context))
-  {
-    service_.construct(impl_);
-  }
-
-  /// Destructor.
-  /**
-   * Destroys a strand.
-   *
-   * Handlers posted through the strand that have not yet been invoked will
-   * still be dispatched in a way that meets the guarantee of non-concurrency.
-   */
-  ~strand()
-  {
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use context().) Get the io_context associated with the
-  /// strand.
-  /**
-   * This function may be used to obtain the io_context object that the strand
-   * uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the strand will use to
-   * dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return service_.get_io_context();
-  }
-
-  /// (Deprecated: Use context().) Get the io_context associated with the
-  /// strand.
-  /**
-   * This function may be used to obtain the io_context object that the strand
-   * uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the strand will use to
-   * dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return service_.get_io_context();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Obtain the underlying execution context.
-  asio::io_context& context() const ASIO_NOEXCEPT
-  {
-    return service_.get_io_context();
-  }
-
-  /// Inform the strand that it has some outstanding work to do.
-  /**
-   * The strand delegates this call to its underlying io_context.
-   */
-  void on_work_started() const ASIO_NOEXCEPT
-  {
-    context().get_executor().on_work_started();
-  }
-
-  /// Inform the strand that some work is no longer outstanding.
-  /**
-   * The strand delegates this call to its underlying io_context.
-   */
-  void on_work_finished() const ASIO_NOEXCEPT
-  {
-    context().get_executor().on_work_finished();
-  }
-
-  /// Request the strand to invoke the given function object.
-  /**
-   * This function is used to ask the strand to execute the given function
-   * object on its underlying io_context. The function object will be executed
-   * inside this function if the strand is not otherwise busy and if the
-   * underlying io_context's executor's @c dispatch() function is also able to
-   * execute the function before returning.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void dispatch(ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-  {
-    typename decay<Function>::type tmp(ASIO_MOVE_CAST(Function)(f));
-    service_.dispatch(impl_, tmp);
-    (void)a;
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use asio::dispatch().) Request the strand to invoke
-  /// the given handler.
-  /**
-   * This function is used to ask the strand to execute the given handler.
-   *
-   * The strand object guarantees that handlers posted or dispatched through
-   * the strand will not be executed concurrently. The handler may be executed
-   * inside this function if the guarantee can be met. If this function is
-   * called from within a handler that was posted or dispatched through the same
-   * strand, then the new handler will be executed immediately.
-   *
-   * The strand's guarantee is in addition to the guarantee provided by the
-   * underlying io_context. The io_context guarantees that the handler will only
-   * be called in a thread in which the io_context's run member function is
-   * currently being invoked.
-   *
-   * @param handler The handler to be called. The strand will make a copy of the
-   * handler object as required. The function signature of the handler must be:
-   * @code void handler(); @endcode
-   */
-  template <typename LegacyCompletionHandler>
-  ASIO_INITFN_RESULT_TYPE(LegacyCompletionHandler, void ())
-  dispatch(ASIO_MOVE_ARG(LegacyCompletionHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a LegacyCompletionHandler.
-    ASIO_LEGACY_COMPLETION_HANDLER_CHECK(
-        LegacyCompletionHandler, handler) type_check;
-
-    async_completion<LegacyCompletionHandler, void ()> init(handler);
-
-    service_.dispatch(impl_, init.completion_handler);
-
-    return init.result.get();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Request the strand to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object will never be executed inside this function.
-   * Instead, it will be scheduled to run by the underlying io_context.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void post(ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-  {
-    typename decay<Function>::type tmp(ASIO_MOVE_CAST(Function)(f));
-    service_.post(impl_, tmp);
-    (void)a;
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use asio::post().) Request the strand to invoke the
-  /// given handler and return immediately.
-  /**
-   * This function is used to ask the strand to execute the given handler, but
-   * without allowing the strand to call the handler from inside this function.
-   *
-   * The strand object guarantees that handlers posted or dispatched through
-   * the strand will not be executed concurrently. The strand's guarantee is in
-   * addition to the guarantee provided by the underlying io_context. The
-   * io_context guarantees that the handler will only be called in a thread in
-   * which the io_context's run member function is currently being invoked.
-   *
-   * @param handler The handler to be called. The strand will make a copy of the
-   * handler object as required. The function signature of the handler must be:
-   * @code void handler(); @endcode
-   */
-  template <typename LegacyCompletionHandler>
-  ASIO_INITFN_RESULT_TYPE(LegacyCompletionHandler, void ())
-  post(ASIO_MOVE_ARG(LegacyCompletionHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a LegacyCompletionHandler.
-    ASIO_LEGACY_COMPLETION_HANDLER_CHECK(
-        LegacyCompletionHandler, handler) type_check;
-
-    async_completion<LegacyCompletionHandler, void ()> init(handler);
-
-    service_.post(impl_, init.completion_handler);
-
-    return init.result.get();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Request the strand to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object will never be executed inside this function.
-   * Instead, it will be scheduled to run by the underlying io_context.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void defer(ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-  {
-    typename decay<Function>::type tmp(ASIO_MOVE_CAST(Function)(f));
-    service_.post(impl_, tmp);
-    (void)a;
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use asio::bind_executor().) Create a new handler that
-  /// automatically dispatches the wrapped handler on the strand.
-  /**
-   * This function is used to create a new handler function object that, when
-   * invoked, will automatically pass the wrapped handler to the strand's
-   * dispatch function.
-   *
-   * @param handler The handler to be wrapped. The strand will make a copy of
-   * the handler object as required. The function signature of the handler must
-   * be: @code void handler(A1 a1, ... An an); @endcode
-   *
-   * @return A function object that, when invoked, passes the wrapped handler to
-   * the strand's dispatch function. Given a function object with the signature:
-   * @code R f(A1 a1, ... An an); @endcode
-   * If this function object is passed to the wrap function like so:
-   * @code strand.wrap(f); @endcode
-   * then the return value is a function object with the signature
-   * @code void g(A1 a1, ... An an); @endcode
-   * that, when invoked, executes code equivalent to:
-   * @code strand.dispatch(boost::bind(f, a1, ... an)); @endcode
-   */
-  template <typename Handler>
-#if defined(GENERATING_DOCUMENTATION)
-  unspecified
-#else
-  detail::wrapped_handler<strand, Handler, detail::is_continuation_if_running>
-#endif
-  wrap(Handler handler)
-  {
-    return detail::wrapped_handler<io_context::strand, Handler,
-        detail::is_continuation_if_running>(*this, handler);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Determine whether the strand is running in the current thread.
-  /**
-   * @return @c true if the current thread is executing a handler that was
-   * submitted to the strand using post(), dispatch() or wrap(). Otherwise
-   * returns @c false.
-   */
-  bool running_in_this_thread() const ASIO_NOEXCEPT
-  {
-    return service_.running_in_this_thread(impl_);
-  }
-
-  /// Compare two strands for equality.
-  /**
-   * Two strands are equal if they refer to the same ordered, non-concurrent
-   * state.
-   */
-  friend bool operator==(const strand& a, const strand& b) ASIO_NOEXCEPT
-  {
-    return a.impl_ == b.impl_;
-  }
-
-  /// Compare two strands for inequality.
-  /**
-   * Two strands are equal if they refer to the same ordered, non-concurrent
-   * state.
-   */
-  friend bool operator!=(const strand& a, const strand& b) ASIO_NOEXCEPT
-  {
-    return a.impl_ != b.impl_;
-  }
-
-private:
-  asio::detail::strand_service& service_;
-  mutable asio::detail::strand_service::implementation_type impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-#endif // ASIO_IO_CONTEXT_STRAND_HPP
diff --git a/tools/sdk/include/asio/asio/io_service.hpp b/tools/sdk/include/asio/asio/io_service.hpp
deleted file mode 100644
index ed05c834101..00000000000
--- a/tools/sdk/include/asio/asio/io_service.hpp
+++ /dev/null
@@ -1,33 +0,0 @@
-//
-// io_service.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IO_SERVICE_HPP
-#define ASIO_IO_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-#if !defined(ASIO_NO_DEPRECATED)
-/// Typedef for backwards compatibility.
-typedef io_context io_service;
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IO_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/io_service_strand.hpp b/tools/sdk/include/asio/asio/io_service_strand.hpp
deleted file mode 100644
index 7093f0e9074..00000000000
--- a/tools/sdk/include/asio/asio/io_service_strand.hpp
+++ /dev/null
@@ -1,20 +0,0 @@
-//
-// io_service_strand.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IO_SERVICE_STRAND_HPP
-#define ASIO_IO_SERVICE_STRAND_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/io_context_strand.hpp"
-
-#endif // ASIO_IO_SERVICE_STRAND_HPP
diff --git a/tools/sdk/include/asio/asio/ip/address.hpp b/tools/sdk/include/asio/asio/ip/address.hpp
deleted file mode 100644
index cf852a6d619..00000000000
--- a/tools/sdk/include/asio/asio/ip/address.hpp
+++ /dev/null
@@ -1,260 +0,0 @@
-//
-// ip/address.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_ADDRESS_HPP
-#define ASIO_IP_ADDRESS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/detail/throw_exception.hpp"
-#include "asio/detail/string_view.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error_code.hpp"
-#include "asio/ip/address_v4.hpp"
-#include "asio/ip/address_v6.hpp"
-#include "asio/ip/bad_address_cast.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-# include <iosfwd>
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Implements version-independent IP addresses.
-/**
- * The asio::ip::address class provides the ability to use either IP
- * version 4 or version 6 addresses.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class address
-{
-public:
-  /// Default constructor.
-  ASIO_DECL address();
-
-  /// Construct an address from an IPv4 address.
-  ASIO_DECL address(const asio::ip::address_v4& ipv4_address);
-
-  /// Construct an address from an IPv6 address.
-  ASIO_DECL address(const asio::ip::address_v6& ipv6_address);
-
-  /// Copy constructor.
-  ASIO_DECL address(const address& other);
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  ASIO_DECL address(address&& other);
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assign from another address.
-  ASIO_DECL address& operator=(const address& other);
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move-assign from another address.
-  ASIO_DECL address& operator=(address&& other);
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assign from an IPv4 address.
-  ASIO_DECL address& operator=(
-      const asio::ip::address_v4& ipv4_address);
-
-  /// Assign from an IPv6 address.
-  ASIO_DECL address& operator=(
-      const asio::ip::address_v6& ipv6_address);
-
-  /// Get whether the address is an IP version 4 address.
-  bool is_v4() const
-  {
-    return type_ == ipv4;
-  }
-
-  /// Get whether the address is an IP version 6 address.
-  bool is_v6() const
-  {
-    return type_ == ipv6;
-  }
-
-  /// Get the address as an IP version 4 address.
-  ASIO_DECL asio::ip::address_v4 to_v4() const;
-
-  /// Get the address as an IP version 6 address.
-  ASIO_DECL asio::ip::address_v6 to_v6() const;
-
-  /// Get the address as a string.
-  ASIO_DECL std::string to_string() const;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use other overload.) Get the address as a string.
-  ASIO_DECL std::string to_string(asio::error_code& ec) const;
-
-  /// (Deprecated: Use make_address().) Create an address from an IPv4 address
-  /// string in dotted decimal form, or from an IPv6 address in hexadecimal
-  /// notation.
-  static address from_string(const char* str);
-
-  /// (Deprecated: Use make_address().) Create an address from an IPv4 address
-  /// string in dotted decimal form, or from an IPv6 address in hexadecimal
-  /// notation.
-  static address from_string(const char* str, asio::error_code& ec);
-
-  /// (Deprecated: Use make_address().) Create an address from an IPv4 address
-  /// string in dotted decimal form, or from an IPv6 address in hexadecimal
-  /// notation.
-  static address from_string(const std::string& str);
-
-  /// (Deprecated: Use make_address().) Create an address from an IPv4 address
-  /// string in dotted decimal form, or from an IPv6 address in hexadecimal
-  /// notation.
-  static address from_string(
-      const std::string& str, asio::error_code& ec);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Determine whether the address is a loopback address.
-  ASIO_DECL bool is_loopback() const;
-
-  /// Determine whether the address is unspecified.
-  ASIO_DECL bool is_unspecified() const;
-
-  /// Determine whether the address is a multicast address.
-  ASIO_DECL bool is_multicast() const;
-
-  /// Compare two addresses for equality.
-  ASIO_DECL friend bool operator==(const address& a1, const address& a2);
-
-  /// Compare two addresses for inequality.
-  friend bool operator!=(const address& a1, const address& a2)
-  {
-    return !(a1 == a2);
-  }
-
-  /// Compare addresses for ordering.
-  ASIO_DECL friend bool operator<(const address& a1, const address& a2);
-
-  /// Compare addresses for ordering.
-  friend bool operator>(const address& a1, const address& a2)
-  {
-    return a2 < a1;
-  }
-
-  /// Compare addresses for ordering.
-  friend bool operator<=(const address& a1, const address& a2)
-  {
-    return !(a2 < a1);
-  }
-
-  /// Compare addresses for ordering.
-  friend bool operator>=(const address& a1, const address& a2)
-  {
-    return !(a1 < a2);
-  }
-
-private:
-  // The type of the address.
-  enum { ipv4, ipv6 } type_;
-
-  // The underlying IPv4 address.
-  asio::ip::address_v4 ipv4_address_;
-
-  // The underlying IPv6 address.
-  asio::ip::address_v6 ipv6_address_;
-};
-
-/// Create an address from an IPv4 address string in dotted decimal form,
-/// or from an IPv6 address in hexadecimal notation.
-/**
- * @relates address
- */
-ASIO_DECL address make_address(const char* str);
-
-/// Create an address from an IPv4 address string in dotted decimal form,
-/// or from an IPv6 address in hexadecimal notation.
-/**
- * @relates address
- */
-ASIO_DECL address make_address(
-    const char* str, asio::error_code& ec);
-
-/// Create an address from an IPv4 address string in dotted decimal form,
-/// or from an IPv6 address in hexadecimal notation.
-/**
- * @relates address
- */
-ASIO_DECL address make_address(const std::string& str);
-
-/// Create an address from an IPv4 address string in dotted decimal form,
-/// or from an IPv6 address in hexadecimal notation.
-/**
- * @relates address
- */
-ASIO_DECL address make_address(
-    const std::string& str, asio::error_code& ec);
-
-#if defined(ASIO_HAS_STRING_VIEW) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Create an address from an IPv4 address string in dotted decimal form,
-/// or from an IPv6 address in hexadecimal notation.
-/**
- * @relates address
- */
-ASIO_DECL address make_address(string_view str);
-
-/// Create an address from an IPv4 address string in dotted decimal form,
-/// or from an IPv6 address in hexadecimal notation.
-/**
- * @relates address
- */
-ASIO_DECL address make_address(
-    string_view str, asio::error_code& ec);
-
-#endif // defined(ASIO_HAS_STRING_VIEW)
-       //  || defined(GENERATING_DOCUMENTATION)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Output an address as a string.
-/**
- * Used to output a human-readable string for a specified address.
- *
- * @param os The output stream to which the string will be written.
- *
- * @param addr The address to be written.
- *
- * @return The output stream.
- *
- * @relates asio::ip::address
- */
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const address& addr);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/ip/impl/address.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ip/impl/address.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_IP_ADDRESS_HPP
diff --git a/tools/sdk/include/asio/asio/ip/address_v4.hpp b/tools/sdk/include/asio/asio/ip/address_v4.hpp
deleted file mode 100644
index 4e1cc9a3348..00000000000
--- a/tools/sdk/include/asio/asio/ip/address_v4.hpp
+++ /dev/null
@@ -1,329 +0,0 @@
-//
-// ip/address_v4.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_ADDRESS_V4_HPP
-#define ASIO_IP_ADDRESS_V4_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/detail/array.hpp"
-#include "asio/detail/cstdint.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/string_view.hpp"
-#include "asio/detail/winsock_init.hpp"
-#include "asio/error_code.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-# include <iosfwd>
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Implements IP version 4 style addresses.
-/**
- * The asio::ip::address_v4 class provides the ability to use and
- * manipulate IP version 4 addresses.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class address_v4
-{
-public:
-  /// The type used to represent an address as an unsigned integer.
-  typedef uint_least32_t uint_type;
-
-  /// The type used to represent an address as an array of bytes.
-  /**
-   * @note This type is defined in terms of the C++0x template @c std::array
-   * when it is available. Otherwise, it uses @c boost:array.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef array<unsigned char, 4> bytes_type;
-#else
-  typedef asio::detail::array<unsigned char, 4> bytes_type;
-#endif
-
-  /// Default constructor.
-  address_v4()
-  {
-    addr_.s_addr = 0;
-  }
-
-  /// Construct an address from raw bytes.
-  ASIO_DECL explicit address_v4(const bytes_type& bytes);
-
-  /// Construct an address from an unsigned integer in host byte order.
-  ASIO_DECL explicit address_v4(uint_type addr);
-
-  /// Copy constructor.
-  address_v4(const address_v4& other)
-    : addr_(other.addr_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  address_v4(address_v4&& other)
-    : addr_(other.addr_)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assign from another address.
-  address_v4& operator=(const address_v4& other)
-  {
-    addr_ = other.addr_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move-assign from another address.
-  address_v4& operator=(address_v4&& other)
-  {
-    addr_ = other.addr_;
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Get the address in bytes, in network byte order.
-  ASIO_DECL bytes_type to_bytes() const;
-
-  /// Get the address as an unsigned integer in host byte order
-  ASIO_DECL uint_type to_uint() const;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// Get the address as an unsigned long in host byte order
-  ASIO_DECL unsigned long to_ulong() const;
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the address as a string in dotted decimal format.
-  ASIO_DECL std::string to_string() const;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use other overload.) Get the address as a string in dotted
-  /// decimal format.
-  ASIO_DECL std::string to_string(asio::error_code& ec) const;
-
-  /// (Deprecated: Use make_address_v4().) Create an address from an IP address
-  /// string in dotted decimal form.
-  static address_v4 from_string(const char* str);
-
-  /// (Deprecated: Use make_address_v4().) Create an address from an IP address
-  /// string in dotted decimal form.
-  static address_v4 from_string(
-      const char* str, asio::error_code& ec);
-
-  /// (Deprecated: Use make_address_v4().) Create an address from an IP address
-  /// string in dotted decimal form.
-  static address_v4 from_string(const std::string& str);
-
-  /// (Deprecated: Use make_address_v4().) Create an address from an IP address
-  /// string in dotted decimal form.
-  static address_v4 from_string(
-      const std::string& str, asio::error_code& ec);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Determine whether the address is a loopback address.
-  ASIO_DECL bool is_loopback() const;
-
-  /// Determine whether the address is unspecified.
-  ASIO_DECL bool is_unspecified() const;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use network_v4 class.) Determine whether the address is a
-  /// class A address.
-  ASIO_DECL bool is_class_a() const;
-
-  /// (Deprecated: Use network_v4 class.) Determine whether the address is a
-  /// class B address.
-  ASIO_DECL bool is_class_b() const;
-
-  /// (Deprecated: Use network_v4 class.) Determine whether the address is a
-  /// class C address.
-  ASIO_DECL bool is_class_c() const;
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Determine whether the address is a multicast address.
-  ASIO_DECL bool is_multicast() const;
-
-  /// Compare two addresses for equality.
-  friend bool operator==(const address_v4& a1, const address_v4& a2)
-  {
-    return a1.addr_.s_addr == a2.addr_.s_addr;
-  }
-
-  /// Compare two addresses for inequality.
-  friend bool operator!=(const address_v4& a1, const address_v4& a2)
-  {
-    return a1.addr_.s_addr != a2.addr_.s_addr;
-  }
-
-  /// Compare addresses for ordering.
-  friend bool operator<(const address_v4& a1, const address_v4& a2)
-  {
-    return a1.to_uint() < a2.to_uint();
-  }
-
-  /// Compare addresses for ordering.
-  friend bool operator>(const address_v4& a1, const address_v4& a2)
-  {
-    return a1.to_uint() > a2.to_uint();
-  }
-
-  /// Compare addresses for ordering.
-  friend bool operator<=(const address_v4& a1, const address_v4& a2)
-  {
-    return a1.to_uint() <= a2.to_uint();
-  }
-
-  /// Compare addresses for ordering.
-  friend bool operator>=(const address_v4& a1, const address_v4& a2)
-  {
-    return a1.to_uint() >= a2.to_uint();
-  }
-
-  /// Obtain an address object that represents any address.
-  static address_v4 any()
-  {
-    return address_v4();
-  }
-
-  /// Obtain an address object that represents the loopback address.
-  static address_v4 loopback()
-  {
-    return address_v4(0x7F000001);
-  }
-
-  /// Obtain an address object that represents the broadcast address.
-  static address_v4 broadcast()
-  {
-    return address_v4(0xFFFFFFFF);
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use network_v4 class.) Obtain an address object that
-  /// represents the broadcast address that corresponds to the specified
-  /// address and netmask.
-  ASIO_DECL static address_v4 broadcast(
-      const address_v4& addr, const address_v4& mask);
-
-  /// (Deprecated: Use network_v4 class.) Obtain the netmask that corresponds
-  /// to the address, based on its address class.
-  ASIO_DECL static address_v4 netmask(const address_v4& addr);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-private:
-  // The underlying IPv4 address.
-  asio::detail::in4_addr_type addr_;
-};
-
-/// Create an IPv4 address from raw bytes in network order.
-/**
- * @relates address_v4
- */
-inline address_v4 make_address_v4(const address_v4::bytes_type& bytes)
-{
-  return address_v4(bytes);
-}
-
-/// Create an IPv4 address from an unsigned integer in host byte order.
-/**
- * @relates address_v4
- */
-inline address_v4 make_address_v4(address_v4::uint_type addr)
-{
-  return address_v4(addr);
-}
-
-/// Create an IPv4 address from an IP address string in dotted decimal form.
-/**
- * @relates address_v4
- */
-ASIO_DECL address_v4 make_address_v4(const char* str);
-
-/// Create an IPv4 address from an IP address string in dotted decimal form.
-/**
- * @relates address_v4
- */
-ASIO_DECL address_v4 make_address_v4(
-    const char* str, asio::error_code& ec);
-
-/// Create an IPv4 address from an IP address string in dotted decimal form.
-/**
- * @relates address_v4
- */
-ASIO_DECL address_v4 make_address_v4(const std::string& str);
-
-/// Create an IPv4 address from an IP address string in dotted decimal form.
-/**
- * @relates address_v4
- */
-ASIO_DECL address_v4 make_address_v4(
-    const std::string& str, asio::error_code& ec);
-
-#if defined(ASIO_HAS_STRING_VIEW) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Create an IPv4 address from an IP address string in dotted decimal form.
-/**
- * @relates address_v4
- */
-ASIO_DECL address_v4 make_address_v4(string_view str);
-
-/// Create an IPv4 address from an IP address string in dotted decimal form.
-/**
- * @relates address_v4
- */
-ASIO_DECL address_v4 make_address_v4(
-    string_view str, asio::error_code& ec);
-
-#endif // defined(ASIO_HAS_STRING_VIEW)
-       //  || defined(GENERATING_DOCUMENTATION)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Output an address as a string.
-/**
- * Used to output a human-readable string for a specified address.
- *
- * @param os The output stream to which the string will be written.
- *
- * @param addr The address to be written.
- *
- * @return The output stream.
- *
- * @relates asio::ip::address_v4
- */
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const address_v4& addr);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/ip/impl/address_v4.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ip/impl/address_v4.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_IP_ADDRESS_V4_HPP
diff --git a/tools/sdk/include/asio/asio/ip/address_v4_iterator.hpp b/tools/sdk/include/asio/asio/ip/address_v4_iterator.hpp
deleted file mode 100644
index e2ef3937e82..00000000000
--- a/tools/sdk/include/asio/asio/ip/address_v4_iterator.hpp
+++ /dev/null
@@ -1,162 +0,0 @@
-//
-// ip/address_v4_iterator.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_ADDRESS_V4_ITERATOR_HPP
-#define ASIO_IP_ADDRESS_V4_ITERATOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/ip/address_v4.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-template <typename> class basic_address_iterator;
-
-/// An input iterator that can be used for traversing IPv4 addresses.
-/**
- * In addition to satisfying the input iterator requirements, this iterator
- * also supports decrement.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <> class basic_address_iterator<address_v4>
-{
-public:
-  /// The type of the elements pointed to by the iterator.
-  typedef address_v4 value_type;
-
-  /// Distance between two iterators.
-  typedef std::ptrdiff_t difference_type;
-
-  /// The type of a pointer to an element pointed to by the iterator.
-  typedef const address_v4* pointer;
-
-  /// The type of a reference to an element pointed to by the iterator.
-  typedef const address_v4& reference;
-
-  /// Denotes that the iterator satisfies the input iterator requirements.
-  typedef std::input_iterator_tag iterator_category;
-
-  /// Construct an iterator that points to the specified address.
-  basic_address_iterator(const address_v4& addr) ASIO_NOEXCEPT
-    : address_(addr)
-  {
-  }
-
-  /// Copy constructor.
-  basic_address_iterator(
-      const basic_address_iterator& other) ASIO_NOEXCEPT
-    : address_(other.address_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  basic_address_iterator(basic_address_iterator&& other) ASIO_NOEXCEPT
-    : address_(ASIO_MOVE_CAST(address_v4)(other.address_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assignment operator.
-  basic_address_iterator& operator=(
-      const basic_address_iterator& other) ASIO_NOEXCEPT
-  {
-    address_ = other.address_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move assignment operator.
-  basic_address_iterator& operator=(
-      basic_address_iterator&& other) ASIO_NOEXCEPT
-  {
-    address_ = ASIO_MOVE_CAST(address_v4)(other.address_);
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Dereference the iterator.
-  const address_v4& operator*() const ASIO_NOEXCEPT
-  {
-    return address_;
-  }
-
-  /// Dereference the iterator.
-  const address_v4* operator->() const ASIO_NOEXCEPT
-  {
-    return &address_;
-  }
-
-  /// Pre-increment operator.
-  basic_address_iterator& operator++() ASIO_NOEXCEPT
-  {
-    address_ = address_v4((address_.to_uint() + 1) & 0xFFFFFFFF);
-    return *this;
-  }
-
-  /// Post-increment operator.
-  basic_address_iterator operator++(int) ASIO_NOEXCEPT
-  {
-    basic_address_iterator tmp(*this);
-    ++*this;
-    return tmp;
-  }
-
-  /// Pre-decrement operator.
-  basic_address_iterator& operator--() ASIO_NOEXCEPT
-  {
-    address_ = address_v4((address_.to_uint() - 1) & 0xFFFFFFFF);
-    return *this;
-  }
-
-  /// Post-decrement operator.
-  basic_address_iterator operator--(int)
-  {
-    basic_address_iterator tmp(*this);
-    --*this;
-    return tmp;
-  }
-
-  /// Compare two addresses for equality.
-  friend bool operator==(const basic_address_iterator& a,
-      const basic_address_iterator& b)
-  {
-    return a.address_ == b.address_;
-  }
-
-  /// Compare two addresses for inequality.
-  friend bool operator!=(const basic_address_iterator& a,
-      const basic_address_iterator& b)
-  {
-    return a.address_ != b.address_;
-  }
-
-private:
-  address_v4 address_;
-};
-
-/// An input iterator that can be used for traversing IPv4 addresses.
-typedef basic_address_iterator<address_v4> address_v4_iterator;
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_ADDRESS_V4_ITERATOR_HPP
diff --git a/tools/sdk/include/asio/asio/ip/address_v4_range.hpp b/tools/sdk/include/asio/asio/ip/address_v4_range.hpp
deleted file mode 100644
index a402842080b..00000000000
--- a/tools/sdk/include/asio/asio/ip/address_v4_range.hpp
+++ /dev/null
@@ -1,134 +0,0 @@
-//
-// ip/address_v4_range.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_ADDRESS_V4_RANGE_HPP
-#define ASIO_IP_ADDRESS_V4_RANGE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/ip/address_v4_iterator.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-template <typename> class basic_address_range;
-
-/// Represents a range of IPv4 addresses.
-/**
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <> class basic_address_range<address_v4>
-{
-public:
-  /// The type of an iterator that points into the range.
-  typedef basic_address_iterator<address_v4> iterator;
-
-  /// Construct an empty range.
-  basic_address_range() ASIO_NOEXCEPT
-    : begin_(address_v4()),
-      end_(address_v4())
-  {
-  }
-
-  /// Construct an range that represents the given range of addresses.
-  explicit basic_address_range(const iterator& first,
-      const iterator& last) ASIO_NOEXCEPT
-    : begin_(first),
-      end_(last)
-  {
-  }
-
-  /// Copy constructor.
-  basic_address_range(const basic_address_range& other) ASIO_NOEXCEPT
-    : begin_(other.begin_),
-      end_(other.end_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  basic_address_range(basic_address_range&& other) ASIO_NOEXCEPT
-    : begin_(ASIO_MOVE_CAST(iterator)(other.begin_)),
-      end_(ASIO_MOVE_CAST(iterator)(other.end_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assignment operator.
-  basic_address_range& operator=(
-      const basic_address_range& other) ASIO_NOEXCEPT
-  {
-    begin_ = other.begin_;
-    end_ = other.end_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move assignment operator.
-  basic_address_range& operator=(
-      basic_address_range&& other) ASIO_NOEXCEPT
-  {
-    begin_ = ASIO_MOVE_CAST(iterator)(other.begin_);
-    end_ = ASIO_MOVE_CAST(iterator)(other.end_);
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Obtain an iterator that points to the start of the range.
-  iterator begin() const ASIO_NOEXCEPT
-  {
-    return begin_;
-  }
-
-  /// Obtain an iterator that points to the end of the range.
-  iterator end() const ASIO_NOEXCEPT
-  {
-    return end_;
-  }
-
-  /// Determine whether the range is empty.
-  bool empty() const ASIO_NOEXCEPT
-  {
-    return size() == 0;
-  }
-
-  /// Return the size of the range.
-  std::size_t size() const ASIO_NOEXCEPT
-  {
-    return end_->to_uint() - begin_->to_uint();
-  }
-
-  /// Find an address in the range.
-  iterator find(const address_v4& addr) const ASIO_NOEXCEPT
-  {
-    return addr >= *begin_ && addr < *end_ ? iterator(addr) : end_;
-  }
-
-private:
-  iterator begin_;
-  iterator end_;
-};
-
-/// Represents a range of IPv4 addresses.
-typedef basic_address_range<address_v4> address_v4_range;
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_ADDRESS_V4_RANGE_HPP
diff --git a/tools/sdk/include/asio/asio/ip/address_v6.hpp b/tools/sdk/include/asio/asio/ip/address_v6.hpp
deleted file mode 100644
index fece3329756..00000000000
--- a/tools/sdk/include/asio/asio/ip/address_v6.hpp
+++ /dev/null
@@ -1,336 +0,0 @@
-//
-// ip/address_v6.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_ADDRESS_V6_HPP
-#define ASIO_IP_ADDRESS_V6_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/detail/array.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/string_view.hpp"
-#include "asio/detail/winsock_init.hpp"
-#include "asio/error_code.hpp"
-#include "asio/ip/address_v4.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-# include <iosfwd>
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-template <typename> class basic_address_iterator;
-
-/// Implements IP version 6 style addresses.
-/**
- * The asio::ip::address_v6 class provides the ability to use and
- * manipulate IP version 6 addresses.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class address_v6
-{
-public:
-  /// The type used to represent an address as an array of bytes.
-  /**
-   * @note This type is defined in terms of the C++0x template @c std::array
-   * when it is available. Otherwise, it uses @c boost:array.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef array<unsigned char, 16> bytes_type;
-#else
-  typedef asio::detail::array<unsigned char, 16> bytes_type;
-#endif
-
-  /// Default constructor.
-  ASIO_DECL address_v6();
-
-  /// Construct an address from raw bytes and scope ID.
-  ASIO_DECL explicit address_v6(const bytes_type& bytes,
-      unsigned long scope_id = 0);
-
-  /// Copy constructor.
-  ASIO_DECL address_v6(const address_v6& other);
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  ASIO_DECL address_v6(address_v6&& other);
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assign from another address.
-  ASIO_DECL address_v6& operator=(const address_v6& other);
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move-assign from another address.
-  ASIO_DECL address_v6& operator=(address_v6&& other);
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// The scope ID of the address.
-  /**
-   * Returns the scope ID associated with the IPv6 address.
-   */
-  unsigned long scope_id() const
-  {
-    return scope_id_;
-  }
-
-  /// The scope ID of the address.
-  /**
-   * Modifies the scope ID associated with the IPv6 address.
-   */
-  void scope_id(unsigned long id)
-  {
-    scope_id_ = id;
-  }
-
-  /// Get the address in bytes, in network byte order.
-  ASIO_DECL bytes_type to_bytes() const;
-
-  /// Get the address as a string.
-  ASIO_DECL std::string to_string() const;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use other overload.) Get the address as a string.
-  ASIO_DECL std::string to_string(asio::error_code& ec) const;
-
-  /// (Deprecated: Use make_address_v6().) Create an IPv6 address from an IP
-  /// address string.
-  static address_v6 from_string(const char* str);
-
-  /// (Deprecated: Use make_address_v6().) Create an IPv6 address from an IP
-  /// address string.
-  static address_v6 from_string(
-      const char* str, asio::error_code& ec);
-
-  /// (Deprecated: Use make_address_v6().) Create an IPv6 address from an IP
-  /// address string.
-  static address_v6 from_string(const std::string& str);
-
-  /// (Deprecated: Use make_address_v6().) Create an IPv6 address from an IP
-  /// address string.
-  static address_v6 from_string(
-      const std::string& str, asio::error_code& ec);
-
-  /// (Deprecated: Use make_address_v4().) Converts an IPv4-mapped or
-  /// IPv4-compatible address to an IPv4 address.
-  ASIO_DECL address_v4 to_v4() const;
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Determine whether the address is a loopback address.
-  ASIO_DECL bool is_loopback() const;
-
-  /// Determine whether the address is unspecified.
-  ASIO_DECL bool is_unspecified() const;
-
-  /// Determine whether the address is link local.
-  ASIO_DECL bool is_link_local() const;
-
-  /// Determine whether the address is site local.
-  ASIO_DECL bool is_site_local() const;
-
-  /// Determine whether the address is a mapped IPv4 address.
-  ASIO_DECL bool is_v4_mapped() const;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: No replacement.) Determine whether the address is an
-  /// IPv4-compatible address.
-  ASIO_DECL bool is_v4_compatible() const;
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Determine whether the address is a multicast address.
-  ASIO_DECL bool is_multicast() const;
-
-  /// Determine whether the address is a global multicast address.
-  ASIO_DECL bool is_multicast_global() const;
-
-  /// Determine whether the address is a link-local multicast address.
-  ASIO_DECL bool is_multicast_link_local() const;
-
-  /// Determine whether the address is a node-local multicast address.
-  ASIO_DECL bool is_multicast_node_local() const;
-
-  /// Determine whether the address is a org-local multicast address.
-  ASIO_DECL bool is_multicast_org_local() const;
-
-  /// Determine whether the address is a site-local multicast address.
-  ASIO_DECL bool is_multicast_site_local() const;
-
-  /// Compare two addresses for equality.
-  ASIO_DECL friend bool operator==(
-      const address_v6& a1, const address_v6& a2);
-
-  /// Compare two addresses for inequality.
-  friend bool operator!=(const address_v6& a1, const address_v6& a2)
-  {
-    return !(a1 == a2);
-  }
-
-  /// Compare addresses for ordering.
-  ASIO_DECL friend bool operator<(
-      const address_v6& a1, const address_v6& a2);
-
-  /// Compare addresses for ordering.
-  friend bool operator>(const address_v6& a1, const address_v6& a2)
-  {
-    return a2 < a1;
-  }
-
-  /// Compare addresses for ordering.
-  friend bool operator<=(const address_v6& a1, const address_v6& a2)
-  {
-    return !(a2 < a1);
-  }
-
-  /// Compare addresses for ordering.
-  friend bool operator>=(const address_v6& a1, const address_v6& a2)
-  {
-    return !(a1 < a2);
-  }
-
-  /// Obtain an address object that represents any address.
-  static address_v6 any()
-  {
-    return address_v6();
-  }
-
-  /// Obtain an address object that represents the loopback address.
-  ASIO_DECL static address_v6 loopback();
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use make_address_v6().) Create an IPv4-mapped IPv6 address.
-  ASIO_DECL static address_v6 v4_mapped(const address_v4& addr);
-
-  /// (Deprecated: No replacement.) Create an IPv4-compatible IPv6 address.
-  ASIO_DECL static address_v6 v4_compatible(const address_v4& addr);
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-private:
-  friend class basic_address_iterator<address_v6>;
-
-  // The underlying IPv6 address.
-  asio::detail::in6_addr_type addr_;
-
-  // The scope ID associated with the address.
-  unsigned long scope_id_;
-};
-
-/// Create an IPv6 address from raw bytes and scope ID.
-/**
- * @relates address_v6
- */
-inline address_v6 make_address_v6(const address_v6::bytes_type& bytes,
-    unsigned long scope_id = 0)
-{
-  return address_v6(bytes, scope_id);
-}
-
-/// Create an IPv6 address from an IP address string.
-/**
- * @relates address_v6
- */
-ASIO_DECL address_v6 make_address_v6(const char* str);
-
-/// Create an IPv6 address from an IP address string.
-/**
- * @relates address_v6
- */
-ASIO_DECL address_v6 make_address_v6(
-    const char* str, asio::error_code& ec);
-
-/// Createan IPv6 address from an IP address string.
-/**
- * @relates address_v6
- */
-ASIO_DECL address_v6 make_address_v6(const std::string& str);
-
-/// Create an IPv6 address from an IP address string.
-/**
- * @relates address_v6
- */
-ASIO_DECL address_v6 make_address_v6(
-    const std::string& str, asio::error_code& ec);
-
-#if defined(ASIO_HAS_STRING_VIEW) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Create an IPv6 address from an IP address string.
-/**
- * @relates address_v6
- */
-ASIO_DECL address_v6 make_address_v6(string_view str);
-
-/// Create an IPv6 address from an IP address string.
-/**
- * @relates address_v6
- */
-ASIO_DECL address_v6 make_address_v6(
-    string_view str, asio::error_code& ec);
-
-#endif // defined(ASIO_HAS_STRING_VIEW)
-       //  || defined(GENERATING_DOCUMENTATION)
-
-/// Tag type used for distinguishing overloads that deal in IPv4-mapped IPv6
-/// addresses.
-enum v4_mapped_t { v4_mapped };
-
-/// Create an IPv4 address from a IPv4-mapped IPv6 address.
-/**
- * @relates address_v4
- */
-ASIO_DECL address_v4 make_address_v4(
-    v4_mapped_t, const address_v6& v6_addr);
-
-/// Create an IPv4-mapped IPv6 address from an IPv4 address.
-/**
- * @relates address_v6
- */
-ASIO_DECL address_v6 make_address_v6(
-    v4_mapped_t, const address_v4& v4_addr);
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Output an address as a string.
-/**
- * Used to output a human-readable string for a specified address.
- *
- * @param os The output stream to which the string will be written.
- *
- * @param addr The address to be written.
- *
- * @return The output stream.
- *
- * @relates asio::ip::address_v6
- */
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const address_v6& addr);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/ip/impl/address_v6.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ip/impl/address_v6.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_IP_ADDRESS_V6_HPP
diff --git a/tools/sdk/include/asio/asio/ip/address_v6_iterator.hpp b/tools/sdk/include/asio/asio/ip/address_v6_iterator.hpp
deleted file mode 100644
index 0a1fb3feabd..00000000000
--- a/tools/sdk/include/asio/asio/ip/address_v6_iterator.hpp
+++ /dev/null
@@ -1,183 +0,0 @@
-//
-// ip/address_v6_iterator.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//                         Oliver Kowalke (oliver dot kowalke at gmail dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_ADDRESS_V6_ITERATOR_HPP
-#define ASIO_IP_ADDRESS_V6_ITERATOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/ip/address_v6.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-template <typename> class basic_address_iterator;
-
-/// An input iterator that can be used for traversing IPv6 addresses.
-/**
- * In addition to satisfying the input iterator requirements, this iterator
- * also supports decrement.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <> class basic_address_iterator<address_v6>
-{
-public:
-  /// The type of the elements pointed to by the iterator.
-  typedef address_v6 value_type;
-
-  /// Distance between two iterators.
-  typedef std::ptrdiff_t difference_type;
-
-  /// The type of a pointer to an element pointed to by the iterator.
-  typedef const address_v6* pointer;
-
-  /// The type of a reference to an element pointed to by the iterator.
-  typedef const address_v6& reference;
-
-  /// Denotes that the iterator satisfies the input iterator requirements.
-  typedef std::input_iterator_tag iterator_category;
-
-  /// Construct an iterator that points to the specified address.
-  basic_address_iterator(const address_v6& addr) ASIO_NOEXCEPT
-    : address_(addr)
-  {
-  }
-
-  /// Copy constructor.
-  basic_address_iterator(
-      const basic_address_iterator& other) ASIO_NOEXCEPT
-    : address_(other.address_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  basic_address_iterator(basic_address_iterator&& other) ASIO_NOEXCEPT
-    : address_(ASIO_MOVE_CAST(address_v6)(other.address_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assignment operator.
-  basic_address_iterator& operator=(
-      const basic_address_iterator& other) ASIO_NOEXCEPT
-  {
-    address_ = other.address_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move assignment operator.
-  basic_address_iterator& operator=(
-      basic_address_iterator&& other) ASIO_NOEXCEPT
-  {
-    address_ = ASIO_MOVE_CAST(address_v6)(other.address_);
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Dereference the iterator.
-  const address_v6& operator*() const ASIO_NOEXCEPT
-  {
-    return address_;
-  }
-
-  /// Dereference the iterator.
-  const address_v6* operator->() const ASIO_NOEXCEPT
-  {
-    return &address_;
-  }
-
-  /// Pre-increment operator.
-  basic_address_iterator& operator++() ASIO_NOEXCEPT
-  {
-    for (int i = 15; i >= 0; --i)
-    {
-      if (address_.addr_.s6_addr[i] < 0xFF)
-      {
-        ++address_.addr_.s6_addr[i];
-        break;
-      }
-
-      address_.addr_.s6_addr[i] = 0;
-    }
-
-    return *this;
-  }
-
-  /// Post-increment operator.
-  basic_address_iterator operator++(int) ASIO_NOEXCEPT
-  {
-    basic_address_iterator tmp(*this);
-    ++*this;
-    return tmp;
-  }
-
-  /// Pre-decrement operator.
-  basic_address_iterator& operator--() ASIO_NOEXCEPT
-  {
-    for (int i = 15; i >= 0; --i)
-    {
-      if (address_.addr_.s6_addr[i] > 0)
-      {
-        --address_.addr_.s6_addr[i];
-        break;
-      }
-
-      address_.addr_.s6_addr[i] = 0xFF;
-    }
-
-    return *this;
-  }
-
-  /// Post-decrement operator.
-  basic_address_iterator operator--(int)
-  {
-    basic_address_iterator tmp(*this);
-    --*this;
-    return tmp;
-  }
-
-  /// Compare two addresses for equality.
-  friend bool operator==(const basic_address_iterator& a,
-      const basic_address_iterator& b)
-  {
-    return a.address_ == b.address_;
-  }
-
-  /// Compare two addresses for inequality.
-  friend bool operator!=(const basic_address_iterator& a,
-      const basic_address_iterator& b)
-  {
-    return a.address_ != b.address_;
-  }
-
-private:
-  address_v6 address_;
-};
-
-/// An input iterator that can be used for traversing IPv6 addresses.
-typedef basic_address_iterator<address_v6> address_v6_iterator;
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_ADDRESS_V6_ITERATOR_HPP
diff --git a/tools/sdk/include/asio/asio/ip/address_v6_range.hpp b/tools/sdk/include/asio/asio/ip/address_v6_range.hpp
deleted file mode 100644
index 9d7062ef8eb..00000000000
--- a/tools/sdk/include/asio/asio/ip/address_v6_range.hpp
+++ /dev/null
@@ -1,129 +0,0 @@
-//
-// ip/address_v6_range.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//                         Oliver Kowalke (oliver dot kowalke at gmail dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_ADDRESS_V6_RANGE_HPP
-#define ASIO_IP_ADDRESS_V6_RANGE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/ip/address_v6_iterator.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-template <typename> class basic_address_range;
-
-/// Represents a range of IPv6 addresses.
-/**
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <> class basic_address_range<address_v6>
-{
-public:
-  /// The type of an iterator that points into the range.
-  typedef basic_address_iterator<address_v6> iterator;
-
-  /// Construct an empty range.
-  basic_address_range() ASIO_NOEXCEPT
-    : begin_(address_v6()),
-      end_(address_v6())
-  {
-  }
-
-  /// Construct an range that represents the given range of addresses.
-  explicit basic_address_range(const iterator& first,
-      const iterator& last) ASIO_NOEXCEPT
-    : begin_(first),
-      end_(last)
-  {
-  }
-
-  /// Copy constructor.
-  basic_address_range(const basic_address_range& other) ASIO_NOEXCEPT
-    : begin_(other.begin_),
-      end_(other.end_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  basic_address_range(basic_address_range&& other) ASIO_NOEXCEPT
-    : begin_(ASIO_MOVE_CAST(iterator)(other.begin_)),
-      end_(ASIO_MOVE_CAST(iterator)(other.end_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assignment operator.
-  basic_address_range& operator=(
-      const basic_address_range& other) ASIO_NOEXCEPT
-  {
-    begin_ = other.begin_;
-    end_ = other.end_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move assignment operator.
-  basic_address_range& operator=(
-      basic_address_range&& other) ASIO_NOEXCEPT
-  {
-    begin_ = ASIO_MOVE_CAST(iterator)(other.begin_);
-    end_ = ASIO_MOVE_CAST(iterator)(other.end_);
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Obtain an iterator that points to the start of the range.
-  iterator begin() const ASIO_NOEXCEPT
-  {
-    return begin_;
-  }
-
-  /// Obtain an iterator that points to the end of the range.
-  iterator end() const ASIO_NOEXCEPT
-  {
-    return end_;
-  }
-
-  /// Determine whether the range is empty.
-  bool empty() const ASIO_NOEXCEPT
-  {
-    return begin_ == end_;
-  }
-
-  /// Find an address in the range.
-  iterator find(const address_v6& addr) const ASIO_NOEXCEPT
-  {
-    return addr >= *begin_ && addr < *end_ ? iterator(addr) : end_;
-  }
-
-private:
-  iterator begin_;
-  iterator end_;
-};
-
-/// Represents a range of IPv6 addresses.
-typedef basic_address_range<address_v6> address_v6_range;
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_ADDRESS_V6_RANGE_HPP
diff --git a/tools/sdk/include/asio/asio/ip/bad_address_cast.hpp b/tools/sdk/include/asio/asio/ip/bad_address_cast.hpp
deleted file mode 100644
index 8c71f704f83..00000000000
--- a/tools/sdk/include/asio/asio/ip/bad_address_cast.hpp
+++ /dev/null
@@ -1,48 +0,0 @@
-//
-// ip/bad_address_cast.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_BAD_ADDRESS_CAST_HPP
-#define ASIO_IP_BAD_ADDRESS_CAST_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <typeinfo>
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Thrown to indicate a failed address conversion.
-class bad_address_cast : public std::bad_cast
-{
-public:
-  /// Default constructor.
-  bad_address_cast() {}
-
-  /// Destructor.
-  virtual ~bad_address_cast() ASIO_NOEXCEPT_OR_NOTHROW {}
-
-  /// Get the message associated with the exception.
-  virtual const char* what() const ASIO_NOEXCEPT_OR_NOTHROW
-  {
-    return "bad address cast";
-  }
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_ADDRESS_HPP
diff --git a/tools/sdk/include/asio/asio/ip/basic_endpoint.hpp b/tools/sdk/include/asio/asio/ip/basic_endpoint.hpp
deleted file mode 100644
index 4418ee77636..00000000000
--- a/tools/sdk/include/asio/asio/ip/basic_endpoint.hpp
+++ /dev/null
@@ -1,263 +0,0 @@
-//
-// ip/basic_endpoint.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_BASIC_ENDPOINT_HPP
-#define ASIO_IP_BASIC_ENDPOINT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/ip/address.hpp"
-#include "asio/ip/detail/endpoint.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-# include <iosfwd>
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Describes an endpoint for a version-independent IP socket.
-/**
- * The asio::ip::basic_endpoint class template describes an endpoint that
- * may be associated with a particular socket.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * Endpoint.
- */
-template <typename InternetProtocol>
-class basic_endpoint
-{
-public:
-  /// The protocol type associated with the endpoint.
-  typedef InternetProtocol protocol_type;
-
-  /// The type of the endpoint structure. This type is dependent on the
-  /// underlying implementation of the socket layer.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined data_type;
-#else
-  typedef asio::detail::socket_addr_type data_type;
-#endif
-
-  /// Default constructor.
-  basic_endpoint()
-    : impl_()
-  {
-  }
-
-  /// Construct an endpoint using a port number, specified in the host's byte
-  /// order. The IP address will be the any address (i.e. INADDR_ANY or
-  /// in6addr_any). This constructor would typically be used for accepting new
-  /// connections.
-  /**
-   * @par Examples
-   * To initialise an IPv4 TCP endpoint for port 1234, use:
-   * @code
-   * asio::ip::tcp::endpoint ep(asio::ip::tcp::v4(), 1234);
-   * @endcode
-   *
-   * To specify an IPv6 UDP endpoint for port 9876, use:
-   * @code
-   * asio::ip::udp::endpoint ep(asio::ip::udp::v6(), 9876);
-   * @endcode
-   */
-  basic_endpoint(const InternetProtocol& internet_protocol,
-      unsigned short port_num)
-    : impl_(internet_protocol.family(), port_num)
-  {
-  }
-
-  /// Construct an endpoint using a port number and an IP address. This
-  /// constructor may be used for accepting connections on a specific interface
-  /// or for making a connection to a remote endpoint.
-  basic_endpoint(const asio::ip::address& addr, unsigned short port_num)
-    : impl_(addr, port_num)
-  {
-  }
-
-  /// Copy constructor.
-  basic_endpoint(const basic_endpoint& other)
-    : impl_(other.impl_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move constructor.
-  basic_endpoint(basic_endpoint&& other)
-    : impl_(other.impl_)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Assign from another endpoint.
-  basic_endpoint& operator=(const basic_endpoint& other)
-  {
-    impl_ = other.impl_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-assign from another endpoint.
-  basic_endpoint& operator=(basic_endpoint&& other)
-  {
-    impl_ = other.impl_;
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// The protocol associated with the endpoint.
-  protocol_type protocol() const
-  {
-    if (impl_.is_v4())
-      return InternetProtocol::v4();
-    return InternetProtocol::v6();
-  }
-
-  /// Get the underlying endpoint in the native type.
-  data_type* data()
-  {
-    return impl_.data();
-  }
-
-  /// Get the underlying endpoint in the native type.
-  const data_type* data() const
-  {
-    return impl_.data();
-  }
-
-  /// Get the underlying size of the endpoint in the native type.
-  std::size_t size() const
-  {
-    return impl_.size();
-  }
-
-  /// Set the underlying size of the endpoint in the native type.
-  void resize(std::size_t new_size)
-  {
-    impl_.resize(new_size);
-  }
-
-  /// Get the capacity of the endpoint in the native type.
-  std::size_t capacity() const
-  {
-    return impl_.capacity();
-  }
-
-  /// Get the port associated with the endpoint. The port number is always in
-  /// the host's byte order.
-  unsigned short port() const
-  {
-    return impl_.port();
-  }
-
-  /// Set the port associated with the endpoint. The port number is always in
-  /// the host's byte order.
-  void port(unsigned short port_num)
-  {
-    impl_.port(port_num);
-  }
-
-  /// Get the IP address associated with the endpoint.
-  asio::ip::address address() const
-  {
-    return impl_.address();
-  }
-
-  /// Set the IP address associated with the endpoint.
-  void address(const asio::ip::address& addr)
-  {
-    impl_.address(addr);
-  }
-
-  /// Compare two endpoints for equality.
-  friend bool operator==(const basic_endpoint<InternetProtocol>& e1,
-      const basic_endpoint<InternetProtocol>& e2)
-  {
-    return e1.impl_ == e2.impl_;
-  }
-
-  /// Compare two endpoints for inequality.
-  friend bool operator!=(const basic_endpoint<InternetProtocol>& e1,
-      const basic_endpoint<InternetProtocol>& e2)
-  {
-    return !(e1 == e2);
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator<(const basic_endpoint<InternetProtocol>& e1,
-      const basic_endpoint<InternetProtocol>& e2)
-  {
-    return e1.impl_ < e2.impl_;
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator>(const basic_endpoint<InternetProtocol>& e1,
-      const basic_endpoint<InternetProtocol>& e2)
-  {
-    return e2.impl_ < e1.impl_;
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator<=(const basic_endpoint<InternetProtocol>& e1,
-      const basic_endpoint<InternetProtocol>& e2)
-  {
-    return !(e2 < e1);
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator>=(const basic_endpoint<InternetProtocol>& e1,
-      const basic_endpoint<InternetProtocol>& e2)
-  {
-    return !(e1 < e2);
-  }
-
-private:
-  // The underlying IP endpoint.
-  asio::ip::detail::endpoint impl_;
-};
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Output an endpoint as a string.
-/**
- * Used to output a human-readable string for a specified endpoint.
- *
- * @param os The output stream to which the string will be written.
- *
- * @param endpoint The endpoint to be written.
- *
- * @return The output stream.
- *
- * @relates asio::ip::basic_endpoint
- */
-template <typename Elem, typename Traits, typename InternetProtocol>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os,
-    const basic_endpoint<InternetProtocol>& endpoint);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/ip/impl/basic_endpoint.hpp"
-
-#endif // ASIO_IP_BASIC_ENDPOINT_HPP
diff --git a/tools/sdk/include/asio/asio/ip/basic_resolver.hpp b/tools/sdk/include/asio/asio/ip/basic_resolver.hpp
deleted file mode 100644
index 812dbec541c..00000000000
--- a/tools/sdk/include/asio/asio/ip/basic_resolver.hpp
+++ /dev/null
@@ -1,1018 +0,0 @@
-//
-// ip/basic_resolver.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_BASIC_RESOLVER_HPP
-#define ASIO_IP_BASIC_RESOLVER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/async_result.hpp"
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/string_view.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/ip/basic_resolver_iterator.hpp"
-#include "asio/ip/basic_resolver_query.hpp"
-#include "asio/ip/basic_resolver_results.hpp"
-#include "asio/ip/resolver_base.hpp"
-
-#if defined(ASIO_HAS_MOVE)
-# include <utility>
-#endif // defined(ASIO_HAS_MOVE)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/ip/resolver_service.hpp"
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-# if defined(ASIO_WINDOWS_RUNTIME)
-#  include "asio/detail/winrt_resolver_service.hpp"
-#  define ASIO_SVC_T \
-    asio::detail::winrt_resolver_service<InternetProtocol>
-# else
-#  include "asio/detail/resolver_service.hpp"
-#  define ASIO_SVC_T \
-    asio::detail::resolver_service<InternetProtocol>
-# endif
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Provides endpoint resolution functionality.
-/**
- * The basic_resolver class template provides the ability to resolve a query
- * to a list of endpoints.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename InternetProtocol
-    ASIO_SVC_TPARAM_DEF1(= resolver_service<InternetProtocol>)>
-class basic_resolver
-  : ASIO_SVC_ACCESS basic_io_object<ASIO_SVC_T>,
-    public resolver_base
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// The protocol type.
-  typedef InternetProtocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename InternetProtocol::endpoint endpoint_type;
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated.) The query type.
-  typedef basic_resolver_query<InternetProtocol> query;
-
-  /// (Deprecated.) The iterator type.
-  typedef basic_resolver_iterator<InternetProtocol> iterator;
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// The results type.
-  typedef basic_resolver_results<InternetProtocol> results_type;
-
-  /// Constructor.
-  /**
-   * This constructor creates a basic_resolver.
-   *
-   * @param io_context The io_context object that the resolver will use to
-   * dispatch handlers for any asynchronous operations performed on the
-   * resolver.
-   */
-  explicit basic_resolver(asio::io_context& io_context)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_resolver from another.
-  /**
-   * This constructor moves a resolver from one object to another.
-   *
-   * @param other The other basic_resolver object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_resolver(io_context&) constructor.
-   */
-  basic_resolver(basic_resolver&& other)
-    : basic_io_object<ASIO_SVC_T>(std::move(other))
-  {
-  }
-
-  /// Move-assign a basic_resolver from another.
-  /**
-   * This assignment operator moves a resolver from one object to another.
-   * Cancels any outstanding asynchronous operations associated with the target
-   * object.
-   *
-   * @param other The other basic_resolver object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_resolver(io_context&) constructor.
-   */
-  basic_resolver& operator=(basic_resolver&& other)
-  {
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroys the resolver.
-  /**
-   * This function destroys the resolver, cancelling any outstanding
-   * asynchronous wait operations associated with the resolver as if by calling
-   * @c cancel.
-   */
-  ~basic_resolver()
-  {
-  }
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-  // These functions are provided by basic_io_object<>.
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<ASIO_SVC_T>::get_executor();
-  }
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-  /// Cancel any asynchronous operations that are waiting on the resolver.
-  /**
-   * This function forces the completion of any pending asynchronous
-   * operations on the host resolver. The handler for each cancelled operation
-   * will be invoked with the asio::error::operation_aborted error code.
-   */
-  void cancel()
-  {
-    return this->get_service().cancel(this->get_implementation());
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated.) Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve a query into a list of endpoint entries.
-   *
-   * @param q A query object that determines what endpoints will be returned.
-   *
-   * @returns A range object representing the list of endpoint entries. A
-   * successful call to this function is guaranteed to return a non-empty
-   * range.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  results_type resolve(const query& q)
-  {
-    asio::error_code ec;
-    results_type r = this->get_service().resolve(
-        this->get_implementation(), q, ec);
-    asio::detail::throw_error(ec, "resolve");
-    return r;
-  }
-
-  /// (Deprecated.) Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve a query into a list of endpoint entries.
-   *
-   * @param q A query object that determines what endpoints will be returned.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns A range object representing the list of endpoint entries. An
-   * empty range is returned if an error occurs. A successful call to this
-   * function is guaranteed to return a non-empty range.
-   */
-  results_type resolve(const query& q, asio::error_code& ec)
-  {
-    return this->get_service().resolve(this->get_implementation(), q, ec);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @returns A range object representing the list of endpoint entries. A
-   * successful call to this function is guaranteed to return a non-empty
-   * range.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  results_type resolve(ASIO_STRING_VIEW_PARAM host,
-      ASIO_STRING_VIEW_PARAM service)
-  {
-    return resolve(host, service, resolver_base::flags());
-  }
-
-  /// Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns A range object representing the list of endpoint entries. An
-   * empty range is returned if an error occurs. A successful call to this
-   * function is guaranteed to return a non-empty range.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  results_type resolve(ASIO_STRING_VIEW_PARAM host,
-      ASIO_STRING_VIEW_PARAM service, asio::error_code& ec)
-  {
-    return resolve(host, service, resolver_base::flags(), ec);
-  }
-
-  /// Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for communication with
-   * remote hosts.
-   *
-   * @returns A range object representing the list of endpoint entries. A
-   * successful call to this function is guaranteed to return a non-empty
-   * range.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  results_type resolve(ASIO_STRING_VIEW_PARAM host,
-      ASIO_STRING_VIEW_PARAM service, resolver_base::flags resolve_flags)
-  {
-    asio::error_code ec;
-    basic_resolver_query<protocol_type> q(static_cast<std::string>(host),
-        static_cast<std::string>(service), resolve_flags);
-    results_type r = this->get_service().resolve(
-        this->get_implementation(), q, ec);
-    asio::detail::throw_error(ec, "resolve");
-    return r;
-  }
-
-  /// Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for communication with
-   * remote hosts.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns A range object representing the list of endpoint entries. An
-   * empty range is returned if an error occurs. A successful call to this
-   * function is guaranteed to return a non-empty range.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  results_type resolve(ASIO_STRING_VIEW_PARAM host,
-      ASIO_STRING_VIEW_PARAM service, resolver_base::flags resolve_flags,
-      asio::error_code& ec)
-  {
-    basic_resolver_query<protocol_type> q(static_cast<std::string>(host),
-        static_cast<std::string>(service), resolve_flags);
-    return this->get_service().resolve(this->get_implementation(), q, ec);
-  }
-
-  /// Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param protocol A protocol object, normally representing either the IPv4 or
-   * IPv6 version of an internet protocol.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @returns A range object representing the list of endpoint entries. A
-   * successful call to this function is guaranteed to return a non-empty
-   * range.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  results_type resolve(const protocol_type& protocol,
-      ASIO_STRING_VIEW_PARAM host, ASIO_STRING_VIEW_PARAM service)
-  {
-    return resolve(protocol, host, service, resolver_base::flags());
-  }
-
-  /// Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param protocol A protocol object, normally representing either the IPv4 or
-   * IPv6 version of an internet protocol.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns A range object representing the list of endpoint entries. An
-   * empty range is returned if an error occurs. A successful call to this
-   * function is guaranteed to return a non-empty range.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  results_type resolve(const protocol_type& protocol,
-      ASIO_STRING_VIEW_PARAM host, ASIO_STRING_VIEW_PARAM service,
-      asio::error_code& ec)
-  {
-    return resolve(protocol, host, service, resolver_base::flags(), ec);
-  }
-
-  /// Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param protocol A protocol object, normally representing either the IPv4 or
-   * IPv6 version of an internet protocol.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for communication with
-   * remote hosts.
-   *
-   * @returns A range object representing the list of endpoint entries. A
-   * successful call to this function is guaranteed to return a non-empty
-   * range.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  results_type resolve(const protocol_type& protocol,
-      ASIO_STRING_VIEW_PARAM host, ASIO_STRING_VIEW_PARAM service,
-      resolver_base::flags resolve_flags)
-  {
-    asio::error_code ec;
-    basic_resolver_query<protocol_type> q(
-        protocol, static_cast<std::string>(host),
-        static_cast<std::string>(service), resolve_flags);
-    results_type r = this->get_service().resolve(
-        this->get_implementation(), q, ec);
-    asio::detail::throw_error(ec, "resolve");
-    return r;
-  }
-
-  /// Perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param protocol A protocol object, normally representing either the IPv4 or
-   * IPv6 version of an internet protocol.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for communication with
-   * remote hosts.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns A range object representing the list of endpoint entries. An
-   * empty range is returned if an error occurs. A successful call to this
-   * function is guaranteed to return a non-empty range.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  results_type resolve(const protocol_type& protocol,
-      ASIO_STRING_VIEW_PARAM host, ASIO_STRING_VIEW_PARAM service,
-      resolver_base::flags resolve_flags, asio::error_code& ec)
-  {
-    basic_resolver_query<protocol_type> q(
-        protocol, static_cast<std::string>(host),
-        static_cast<std::string>(service), resolve_flags);
-    return this->get_service().resolve(this->get_implementation(), q, ec);
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated.) Asynchronously perform forward resolution of a query to a
-  /// list of entries.
-  /**
-   * This function is used to asynchronously resolve a query into a list of
-   * endpoint entries.
-   *
-   * @param q A query object that determines what endpoints will be returned.
-   *
-   * @param handler The handler to be called when the resolve operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   resolver::results_type results // Resolved endpoints as a range.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * A successful resolve operation is guaranteed to pass a non-empty range to
-   * the handler.
-   */
-  template <typename ResolveHandler>
-  ASIO_INITFN_RESULT_TYPE(ResolveHandler,
-      void (asio::error_code, results_type))
-  async_resolve(const query& q,
-      ASIO_MOVE_ARG(ResolveHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ResolveHandler.
-    ASIO_RESOLVE_HANDLER_CHECK(
-        ResolveHandler, handler, results_type) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_resolve(this->get_implementation(), q,
-        ASIO_MOVE_CAST(ResolveHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    asio::async_completion<ResolveHandler,
-      void (asio::error_code, results_type)> init(handler);
-
-    this->get_service().async_resolve(
-        this->get_implementation(), q, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Asynchronously perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param handler The handler to be called when the resolve operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   resolver::results_type results // Resolved endpoints as a range.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * A successful resolve operation is guaranteed to pass a non-empty range to
-   * the handler.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  template <typename ResolveHandler>
-  ASIO_INITFN_RESULT_TYPE(ResolveHandler,
-      void (asio::error_code, results_type))
-  async_resolve(ASIO_STRING_VIEW_PARAM host,
-      ASIO_STRING_VIEW_PARAM service,
-      ASIO_MOVE_ARG(ResolveHandler) handler)
-  {
-    return async_resolve(host, service, resolver_base::flags(),
-        ASIO_MOVE_CAST(ResolveHandler)(handler));
-  }
-
-  /// Asynchronously perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for communication with
-   * remote hosts.
-   *
-   * @param handler The handler to be called when the resolve operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   resolver::results_type results // Resolved endpoints as a range.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * A successful resolve operation is guaranteed to pass a non-empty range to
-   * the handler.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  template <typename ResolveHandler>
-  ASIO_INITFN_RESULT_TYPE(ResolveHandler,
-      void (asio::error_code, results_type))
-  async_resolve(ASIO_STRING_VIEW_PARAM host,
-      ASIO_STRING_VIEW_PARAM service,
-      resolver_base::flags resolve_flags,
-      ASIO_MOVE_ARG(ResolveHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ResolveHandler.
-    ASIO_RESOLVE_HANDLER_CHECK(
-        ResolveHandler, handler, results_type) type_check;
-
-    basic_resolver_query<protocol_type> q(static_cast<std::string>(host),
-        static_cast<std::string>(service), resolve_flags);
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_resolve(this->get_implementation(), q,
-        ASIO_MOVE_CAST(ResolveHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    asio::async_completion<ResolveHandler,
-      void (asio::error_code, results_type)> init(handler);
-
-    this->get_service().async_resolve(
-        this->get_implementation(), q, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Asynchronously perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param protocol A protocol object, normally representing either the IPv4 or
-   * IPv6 version of an internet protocol.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param handler The handler to be called when the resolve operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   resolver::results_type results // Resolved endpoints as a range.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * A successful resolve operation is guaranteed to pass a non-empty range to
-   * the handler.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  template <typename ResolveHandler>
-  ASIO_INITFN_RESULT_TYPE(ResolveHandler,
-      void (asio::error_code, results_type))
-  async_resolve(const protocol_type& protocol,
-      ASIO_STRING_VIEW_PARAM host, ASIO_STRING_VIEW_PARAM service,
-      ASIO_MOVE_ARG(ResolveHandler) handler)
-  {
-    return async_resolve(protocol, host, service, resolver_base::flags(),
-        ASIO_MOVE_CAST(ResolveHandler)(handler));
-  }
-
-  /// Asynchronously perform forward resolution of a query to a list of entries.
-  /**
-   * This function is used to resolve host and service names into a list of
-   * endpoint entries.
-   *
-   * @param protocol A protocol object, normally representing either the IPv4 or
-   * IPv6 version of an internet protocol.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for communication with
-   * remote hosts.
-   *
-   * @param handler The handler to be called when the resolve operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   resolver::results_type results // Resolved endpoints as a range.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * A successful resolve operation is guaranteed to pass a non-empty range to
-   * the handler.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  template <typename ResolveHandler>
-  ASIO_INITFN_RESULT_TYPE(ResolveHandler,
-      void (asio::error_code, results_type))
-  async_resolve(const protocol_type& protocol,
-      ASIO_STRING_VIEW_PARAM host, ASIO_STRING_VIEW_PARAM service,
-      resolver_base::flags resolve_flags,
-      ASIO_MOVE_ARG(ResolveHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ResolveHandler.
-    ASIO_RESOLVE_HANDLER_CHECK(
-        ResolveHandler, handler, results_type) type_check;
-
-    basic_resolver_query<protocol_type> q(
-        protocol, static_cast<std::string>(host),
-        static_cast<std::string>(service), resolve_flags);
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_resolve(this->get_implementation(), q,
-        ASIO_MOVE_CAST(ResolveHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    asio::async_completion<ResolveHandler,
-      void (asio::error_code, results_type)> init(handler);
-
-    this->get_service().async_resolve(
-        this->get_implementation(), q, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-
-  /// Perform reverse resolution of an endpoint to a list of entries.
-  /**
-   * This function is used to resolve an endpoint into a list of endpoint
-   * entries.
-   *
-   * @param e An endpoint object that determines what endpoints will be
-   * returned.
-   *
-   * @returns A range object representing the list of endpoint entries. A
-   * successful call to this function is guaranteed to return a non-empty
-   * range.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  results_type resolve(const endpoint_type& e)
-  {
-    asio::error_code ec;
-    results_type i = this->get_service().resolve(
-        this->get_implementation(), e, ec);
-    asio::detail::throw_error(ec, "resolve");
-    return i;
-  }
-
-  /// Perform reverse resolution of an endpoint to a list of entries.
-  /**
-   * This function is used to resolve an endpoint into a list of endpoint
-   * entries.
-   *
-   * @param e An endpoint object that determines what endpoints will be
-   * returned.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns A range object representing the list of endpoint entries. An
-   * empty range is returned if an error occurs. A successful call to this
-   * function is guaranteed to return a non-empty range.
-   */
-  results_type resolve(const endpoint_type& e, asio::error_code& ec)
-  {
-    return this->get_service().resolve(this->get_implementation(), e, ec);
-  }
-
-  /// Asynchronously perform reverse resolution of an endpoint to a list of
-  /// entries.
-  /**
-   * This function is used to asynchronously resolve an endpoint into a list of
-   * endpoint entries.
-   *
-   * @param e An endpoint object that determines what endpoints will be
-   * returned.
-   *
-   * @param handler The handler to be called when the resolve operation
-   * completes. Copies will be made of the handler as required. The function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   resolver::results_type results // Resolved endpoints as a range.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * A successful resolve operation is guaranteed to pass a non-empty range to
-   * the handler.
-   */
-  template <typename ResolveHandler>
-  ASIO_INITFN_RESULT_TYPE(ResolveHandler,
-      void (asio::error_code, results_type))
-  async_resolve(const endpoint_type& e,
-      ASIO_MOVE_ARG(ResolveHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ResolveHandler.
-    ASIO_RESOLVE_HANDLER_CHECK(
-        ResolveHandler, handler, results_type) type_check;
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-    return this->get_service().async_resolve(this->get_implementation(), e,
-        ASIO_MOVE_CAST(ResolveHandler)(handler));
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-    asio::async_completion<ResolveHandler,
-      void (asio::error_code, results_type)> init(handler);
-
-    this->get_service().async_resolve(
-        this->get_implementation(), e, init.completion_handler);
-
-    return init.result.get();
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-  }
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-# undef ASIO_SVC_T
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_IP_BASIC_RESOLVER_HPP
diff --git a/tools/sdk/include/asio/asio/ip/basic_resolver_entry.hpp b/tools/sdk/include/asio/asio/ip/basic_resolver_entry.hpp
deleted file mode 100644
index 99bcbd29e6f..00000000000
--- a/tools/sdk/include/asio/asio/ip/basic_resolver_entry.hpp
+++ /dev/null
@@ -1,113 +0,0 @@
-//
-// ip/basic_resolver_entry.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_BASIC_RESOLVER_ENTRY_HPP
-#define ASIO_IP_BASIC_RESOLVER_ENTRY_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/detail/string_view.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// An entry produced by a resolver.
-/**
- * The asio::ip::basic_resolver_entry class template describes an entry
- * as returned by a resolver.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename InternetProtocol>
-class basic_resolver_entry
-{
-public:
-  /// The protocol type associated with the endpoint entry.
-  typedef InternetProtocol protocol_type;
-
-  /// The endpoint type associated with the endpoint entry.
-  typedef typename InternetProtocol::endpoint endpoint_type;
-
-  /// Default constructor.
-  basic_resolver_entry()
-  {
-  }
-
-  /// Construct with specified endpoint, host name and service name.
-  basic_resolver_entry(const endpoint_type& ep,
-      ASIO_STRING_VIEW_PARAM host, ASIO_STRING_VIEW_PARAM service)
-    : endpoint_(ep),
-      host_name_(static_cast<std::string>(host)),
-      service_name_(static_cast<std::string>(service))
-  {
-  }
-
-  /// Get the endpoint associated with the entry.
-  endpoint_type endpoint() const
-  {
-    return endpoint_;
-  }
-
-  /// Convert to the endpoint associated with the entry.
-  operator endpoint_type() const
-  {
-    return endpoint_;
-  }
-
-  /// Get the host name associated with the entry.
-  std::string host_name() const
-  {
-    return host_name_;
-  }
-
-  /// Get the host name associated with the entry.
-  template <class Allocator>
-  std::basic_string<char, std::char_traits<char>, Allocator> host_name(
-      const Allocator& alloc = Allocator()) const
-  {
-    return std::basic_string<char, std::char_traits<char>, Allocator>(
-        host_name_.c_str(), alloc);
-  }
-
-  /// Get the service name associated with the entry.
-  std::string service_name() const
-  {
-    return service_name_;
-  }
-
-  /// Get the service name associated with the entry.
-  template <class Allocator>
-  std::basic_string<char, std::char_traits<char>, Allocator> service_name(
-      const Allocator& alloc = Allocator()) const
-  {
-    return std::basic_string<char, std::char_traits<char>, Allocator>(
-        service_name_.c_str(), alloc);
-  }
-
-private:
-  endpoint_type endpoint_;
-  std::string host_name_;
-  std::string service_name_;
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_BASIC_RESOLVER_ENTRY_HPP
diff --git a/tools/sdk/include/asio/asio/ip/basic_resolver_iterator.hpp b/tools/sdk/include/asio/asio/ip/basic_resolver_iterator.hpp
deleted file mode 100644
index ec5412cf6f7..00000000000
--- a/tools/sdk/include/asio/asio/ip/basic_resolver_iterator.hpp
+++ /dev/null
@@ -1,192 +0,0 @@
-//
-// ip/basic_resolver_iterator.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_BASIC_RESOLVER_ITERATOR_HPP
-#define ASIO_IP_BASIC_RESOLVER_ITERATOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <cstring>
-#include <iterator>
-#include <string>
-#include <vector>
-#include "asio/detail/memory.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/ip/basic_resolver_entry.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/winrt_utils.hpp"
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// An iterator over the entries produced by a resolver.
-/**
- * The asio::ip::basic_resolver_iterator class template is used to define
- * iterators over the results returned by a resolver.
- *
- * The iterator's value_type, obtained when the iterator is dereferenced, is:
- * @code const basic_resolver_entry<InternetProtocol> @endcode
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename InternetProtocol>
-class basic_resolver_iterator
-{
-public:
-  /// The type used for the distance between two iterators.
-  typedef std::ptrdiff_t difference_type;
-
-  /// The type of the value pointed to by the iterator.
-  typedef basic_resolver_entry<InternetProtocol> value_type;
-
-  /// The type of the result of applying operator->() to the iterator.
-  typedef const basic_resolver_entry<InternetProtocol>* pointer;
-
-  /// The type of the result of applying operator*() to the iterator.
-  typedef const basic_resolver_entry<InternetProtocol>& reference;
-
-  /// The iterator category.
-  typedef std::forward_iterator_tag iterator_category;
-
-  /// Default constructor creates an end iterator.
-  basic_resolver_iterator()
-    : index_(0)
-  {
-  }
-
-  /// Copy constructor.
-  basic_resolver_iterator(const basic_resolver_iterator& other)
-    : values_(other.values_),
-      index_(other.index_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move constructor.
-  basic_resolver_iterator(basic_resolver_iterator&& other)
-    : values_(ASIO_MOVE_CAST(values_ptr_type)(other.values_)),
-      index_(other.index_)
-  {
-    other.index_ = 0;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Assignment operator.
-  basic_resolver_iterator& operator=(const basic_resolver_iterator& other)
-  {
-    values_ = other.values_;
-    index_ = other.index_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-assignment operator.
-  basic_resolver_iterator& operator=(basic_resolver_iterator&& other)
-  {
-    if (this != &other)
-    {
-      values_ = ASIO_MOVE_CAST(values_ptr_type)(other.values_);
-      index_ = other.index_;
-      other.index_ = 0;
-    }
-
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Dereference an iterator.
-  const basic_resolver_entry<InternetProtocol>& operator*() const
-  {
-    return dereference();
-  }
-
-  /// Dereference an iterator.
-  const basic_resolver_entry<InternetProtocol>* operator->() const
-  {
-    return &dereference();
-  }
-
-  /// Increment operator (prefix).
-  basic_resolver_iterator& operator++()
-  {
-    increment();
-    return *this;
-  }
-
-  /// Increment operator (postfix).
-  basic_resolver_iterator operator++(int)
-  {
-    basic_resolver_iterator tmp(*this);
-    ++*this;
-    return tmp;
-  }
-
-  /// Test two iterators for equality.
-  friend bool operator==(const basic_resolver_iterator& a,
-      const basic_resolver_iterator& b)
-  {
-    return a.equal(b);
-  }
-
-  /// Test two iterators for inequality.
-  friend bool operator!=(const basic_resolver_iterator& a,
-      const basic_resolver_iterator& b)
-  {
-    return !a.equal(b);
-  }
-
-protected:
-  void increment()
-  {
-    if (++index_ == values_->size())
-    {
-      // Reset state to match a default constructed end iterator.
-      values_.reset();
-      index_ = 0;
-    }
-  }
-
-  bool equal(const basic_resolver_iterator& other) const
-  {
-    if (!values_ && !other.values_)
-      return true;
-    if (values_ != other.values_)
-      return false;
-    return index_ == other.index_;
-  }
-
-  const basic_resolver_entry<InternetProtocol>& dereference() const
-  {
-    return (*values_)[index_];
-  }
-
-  typedef std::vector<basic_resolver_entry<InternetProtocol> > values_type;
-  typedef asio::detail::shared_ptr<values_type> values_ptr_type;
-  values_ptr_type values_;
-  std::size_t index_;
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_BASIC_RESOLVER_ITERATOR_HPP
diff --git a/tools/sdk/include/asio/asio/ip/basic_resolver_query.hpp b/tools/sdk/include/asio/asio/ip/basic_resolver_query.hpp
deleted file mode 100644
index 84cd98d5582..00000000000
--- a/tools/sdk/include/asio/asio/ip/basic_resolver_query.hpp
+++ /dev/null
@@ -1,244 +0,0 @@
-//
-// ip/basic_resolver_query.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_BASIC_RESOLVER_QUERY_HPP
-#define ASIO_IP_BASIC_RESOLVER_QUERY_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/detail/socket_ops.hpp"
-#include "asio/ip/resolver_query_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// An query to be passed to a resolver.
-/**
- * The asio::ip::basic_resolver_query class template describes a query
- * that can be passed to a resolver.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename InternetProtocol>
-class basic_resolver_query
-  : public resolver_query_base
-{
-public:
-  /// The protocol type associated with the endpoint query.
-  typedef InternetProtocol protocol_type;
-
-  /// Construct with specified service name for any protocol.
-  /**
-   * This constructor is typically used to perform name resolution for local
-   * service binding.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for local service
-   * binding.
-   *
-   * @note On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  basic_resolver_query(const std::string& service,
-      resolver_query_base::flags resolve_flags = passive | address_configured)
-    : hints_(),
-      host_name_(),
-      service_name_(service)
-  {
-    typename InternetProtocol::endpoint endpoint;
-    hints_.ai_flags = static_cast<int>(resolve_flags);
-    hints_.ai_family = PF_UNSPEC;
-    hints_.ai_socktype = endpoint.protocol().type();
-    hints_.ai_protocol = endpoint.protocol().protocol();
-    hints_.ai_addrlen = 0;
-    hints_.ai_canonname = 0;
-    hints_.ai_addr = 0;
-    hints_.ai_next = 0;
-  }
-
-  /// Construct with specified service name for a given protocol.
-  /**
-   * This constructor is typically used to perform name resolution for local
-   * service binding with a specific protocol version.
-   *
-   * @param protocol A protocol object, normally representing either the IPv4 or
-   * IPv6 version of an internet protocol.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for local service
-   * binding.
-   *
-   * @note On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  basic_resolver_query(const protocol_type& protocol,
-      const std::string& service,
-      resolver_query_base::flags resolve_flags = passive | address_configured)
-    : hints_(),
-      host_name_(),
-      service_name_(service)
-  {
-    hints_.ai_flags = static_cast<int>(resolve_flags);
-    hints_.ai_family = protocol.family();
-    hints_.ai_socktype = protocol.type();
-    hints_.ai_protocol = protocol.protocol();
-    hints_.ai_addrlen = 0;
-    hints_.ai_canonname = 0;
-    hints_.ai_addr = 0;
-    hints_.ai_next = 0;
-  }
-
-  /// Construct with specified host name and service name for any protocol.
-  /**
-   * This constructor is typically used to perform name resolution for
-   * communication with remote hosts.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for communication with
-   * remote hosts.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  basic_resolver_query(const std::string& host, const std::string& service,
-      resolver_query_base::flags resolve_flags = address_configured)
-    : hints_(),
-      host_name_(host),
-      service_name_(service)
-  {
-    typename InternetProtocol::endpoint endpoint;
-    hints_.ai_flags = static_cast<int>(resolve_flags);
-    hints_.ai_family = ASIO_OS_DEF(AF_UNSPEC);
-    hints_.ai_socktype = endpoint.protocol().type();
-    hints_.ai_protocol = endpoint.protocol().protocol();
-    hints_.ai_addrlen = 0;
-    hints_.ai_canonname = 0;
-    hints_.ai_addr = 0;
-    hints_.ai_next = 0;
-  }
-
-  /// Construct with specified host name and service name for a given protocol.
-  /**
-   * This constructor is typically used to perform name resolution for
-   * communication with remote hosts.
-   *
-   * @param protocol A protocol object, normally representing either the IPv4 or
-   * IPv6 version of an internet protocol.
-   *
-   * @param host A string identifying a location. May be a descriptive name or
-   * a numeric address string. If an empty string and the passive flag has been
-   * specified, the resolved endpoints are suitable for local service binding.
-   * If an empty string and passive is not specified, the resolved endpoints
-   * will use the loopback address.
-   *
-   * @param service A string identifying the requested service. This may be a
-   * descriptive name or a numeric string corresponding to a port number. May
-   * be an empty string, in which case all resolved endpoints will have a port
-   * number of 0.
-   *
-   * @param resolve_flags A set of flags that determine how name resolution
-   * should be performed. The default flags are suitable for communication with
-   * remote hosts.
-   *
-   * @note On POSIX systems, host names may be locally defined in the file
-   * <tt>/etc/hosts</tt>. On Windows, host names may be defined in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\hosts</tt>. Remote host name
-   * resolution is performed using DNS. Operating systems may use additional
-   * locations when resolving host names (such as NETBIOS names on Windows).
-   *
-   * On POSIX systems, service names are typically defined in the file
-   * <tt>/etc/services</tt>. On Windows, service names may be found in the file
-   * <tt>c:\\windows\\system32\\drivers\\etc\\services</tt>. Operating systems
-   * may use additional locations when resolving service names.
-   */
-  basic_resolver_query(const protocol_type& protocol,
-      const std::string& host, const std::string& service,
-      resolver_query_base::flags resolve_flags = address_configured)
-    : hints_(),
-      host_name_(host),
-      service_name_(service)
-  {
-    hints_.ai_flags = static_cast<int>(resolve_flags);
-    hints_.ai_family = protocol.family();
-    hints_.ai_socktype = protocol.type();
-    hints_.ai_protocol = protocol.protocol();
-    hints_.ai_addrlen = 0;
-    hints_.ai_canonname = 0;
-    hints_.ai_addr = 0;
-    hints_.ai_next = 0;
-  }
-
-  /// Get the hints associated with the query.
-  const asio::detail::addrinfo_type& hints() const
-  {
-    return hints_;
-  }
-
-  /// Get the host name associated with the query.
-  std::string host_name() const
-  {
-    return host_name_;
-  }
-
-  /// Get the service name associated with the query.
-  std::string service_name() const
-  {
-    return service_name_;
-  }
-
-private:
-  asio::detail::addrinfo_type hints_;
-  std::string host_name_;
-  std::string service_name_;
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_BASIC_RESOLVER_QUERY_HPP
diff --git a/tools/sdk/include/asio/asio/ip/basic_resolver_results.hpp b/tools/sdk/include/asio/asio/ip/basic_resolver_results.hpp
deleted file mode 100644
index 185075f0bf9..00000000000
--- a/tools/sdk/include/asio/asio/ip/basic_resolver_results.hpp
+++ /dev/null
@@ -1,311 +0,0 @@
-//
-// ip/basic_resolver_results.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_BASIC_RESOLVER_RESULTS_HPP
-#define ASIO_IP_BASIC_RESOLVER_RESULTS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <cstring>
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/ip/basic_resolver_iterator.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/winrt_utils.hpp"
-#endif // defined(ASIO_WINDOWS_RUNTIME)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// A range of entries produced by a resolver.
-/**
- * The asio::ip::basic_resolver_results class template is used to define
- * a range over the results returned by a resolver.
- *
- * The iterator's value_type, obtained when a results iterator is dereferenced,
- * is: @code const basic_resolver_entry<InternetProtocol> @endcode
- *
- * @note For backward compatibility, basic_resolver_results is derived from
- * basic_resolver_iterator. This derivation is deprecated.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename InternetProtocol>
-class basic_resolver_results
-#if !defined(ASIO_NO_DEPRECATED)
-  : public basic_resolver_iterator<InternetProtocol>
-#else // !defined(ASIO_NO_DEPRECATED)
-  : private basic_resolver_iterator<InternetProtocol>
-#endif // !defined(ASIO_NO_DEPRECATED)
-{
-public:
-  /// The protocol type associated with the results.
-  typedef InternetProtocol protocol_type;
-
-  /// The endpoint type associated with the results.
-  typedef typename protocol_type::endpoint endpoint_type;
-
-  /// The type of a value in the results range.
-  typedef basic_resolver_entry<protocol_type> value_type;
-
-  /// The type of a const reference to a value in the range.
-  typedef const value_type& const_reference;
-
-  /// The type of a non-const reference to a value in the range.
-  typedef value_type& reference;
-
-  /// The type of an iterator into the range.
-  typedef basic_resolver_iterator<protocol_type> const_iterator;
-
-  /// The type of an iterator into the range.
-  typedef const_iterator iterator;
-
-  /// Type used to represent the distance between two iterators in the range.
-  typedef std::ptrdiff_t difference_type;
-
-  /// Type used to represent a count of the elements in the range.
-  typedef std::size_t size_type;
-
-  /// Default constructor creates an empty range.
-  basic_resolver_results()
-  {
-  }
-
-  /// Copy constructor.
-  basic_resolver_results(const basic_resolver_results& other)
-    : basic_resolver_iterator<InternetProtocol>(other)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move constructor.
-  basic_resolver_results(basic_resolver_results&& other)
-    : basic_resolver_iterator<InternetProtocol>(
-        ASIO_MOVE_CAST(basic_resolver_results)(other))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Assignment operator.
-  basic_resolver_results& operator=(const basic_resolver_results& other)
-  {
-    basic_resolver_iterator<InternetProtocol>::operator=(other);
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-assignment operator.
-  basic_resolver_results& operator=(basic_resolver_results&& other)
-  {
-    basic_resolver_iterator<InternetProtocol>::operator=(
-        ASIO_MOVE_CAST(basic_resolver_results)(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-#if !defined(GENERATING_DOCUMENTATION)
-  // Create results from an addrinfo list returned by getaddrinfo.
-  static basic_resolver_results create(
-      asio::detail::addrinfo_type* address_info,
-      const std::string& host_name, const std::string& service_name)
-  {
-    basic_resolver_results results;
-    if (!address_info)
-      return results;
-
-    std::string actual_host_name = host_name;
-    if (address_info->ai_canonname)
-      actual_host_name = address_info->ai_canonname;
-
-    results.values_.reset(new values_type);
-
-    while (address_info)
-    {
-      if (address_info->ai_family == ASIO_OS_DEF(AF_INET)
-          || address_info->ai_family == ASIO_OS_DEF(AF_INET6))
-      {
-        using namespace std; // For memcpy.
-        typename InternetProtocol::endpoint endpoint;
-        endpoint.resize(static_cast<std::size_t>(address_info->ai_addrlen));
-        memcpy(endpoint.data(), address_info->ai_addr,
-            address_info->ai_addrlen);
-        results.values_->push_back(
-            basic_resolver_entry<InternetProtocol>(endpoint,
-              actual_host_name, service_name));
-      }
-      address_info = address_info->ai_next;
-    }
-
-    return results;
-  }
-
-  // Create results from an endpoint, host name and service name.
-  static basic_resolver_results create(const endpoint_type& endpoint,
-      const std::string& host_name, const std::string& service_name)
-  {
-    basic_resolver_results results;
-    results.values_.reset(new values_type);
-    results.values_->push_back(
-        basic_resolver_entry<InternetProtocol>(
-          endpoint, host_name, service_name));
-    return results;
-  }
-
-  // Create results from a sequence of endpoints, host and service name.
-  template <typename EndpointIterator>
-  static basic_resolver_results create(
-      EndpointIterator begin, EndpointIterator end,
-      const std::string& host_name, const std::string& service_name)
-  {
-    basic_resolver_results results;
-    if (begin != end)
-    {
-      results.values_.reset(new values_type);
-      for (EndpointIterator ep_iter = begin; ep_iter != end; ++ep_iter)
-      {
-        results.values_->push_back(
-            basic_resolver_entry<InternetProtocol>(
-              *ep_iter, host_name, service_name));
-      }
-    }
-    return results;
-  }
-
-# if defined(ASIO_WINDOWS_RUNTIME)
-  // Create results from a Windows Runtime list of EndpointPair objects.
-  static basic_resolver_results create(
-      Windows::Foundation::Collections::IVectorView<
-        Windows::Networking::EndpointPair^>^ endpoints,
-      const asio::detail::addrinfo_type& hints,
-      const std::string& host_name, const std::string& service_name)
-  {
-    basic_resolver_results results;
-    if (endpoints->Size)
-    {
-      results.values_.reset(new values_type);
-      for (unsigned int i = 0; i < endpoints->Size; ++i)
-      {
-        auto pair = endpoints->GetAt(i);
-
-        if (hints.ai_family == ASIO_OS_DEF(AF_INET)
-            && pair->RemoteHostName->Type
-              != Windows::Networking::HostNameType::Ipv4)
-          continue;
-
-        if (hints.ai_family == ASIO_OS_DEF(AF_INET6)
-            && pair->RemoteHostName->Type
-              != Windows::Networking::HostNameType::Ipv6)
-          continue;
-
-        results.values_->push_back(
-            basic_resolver_entry<InternetProtocol>(
-              typename InternetProtocol::endpoint(
-                ip::make_address(
-                  asio::detail::winrt_utils::string(
-                    pair->RemoteHostName->CanonicalName)),
-                asio::detail::winrt_utils::integer(
-                  pair->RemoteServiceName)),
-              host_name, service_name));
-      }
-    }
-    return results;
-  }
-# endif // defined(ASIO_WINDOWS_RUNTIME)
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-  /// Get the number of entries in the results range.
-  size_type size() const ASIO_NOEXCEPT
-  {
-    return this->values_->size();
-  }
-
-  /// Get the maximum number of entries permitted in a results range.
-  size_type max_size() const ASIO_NOEXCEPT
-  {
-    return this->values_->max_size();
-  }
-
-  /// Determine whether the results range is empty.
-  bool empty() const ASIO_NOEXCEPT
-  {
-    return this->values_->empty();
-  }
-
-  /// Obtain a begin iterator for the results range.
-  const_iterator begin() const
-  {
-    basic_resolver_results tmp(*this);
-    tmp.index_ = 0;
-    return tmp;
-  }
-
-  /// Obtain an end iterator for the results range.
-  const_iterator end() const
-  {
-    return const_iterator();
-  }
-
-  /// Obtain a begin iterator for the results range.
-  const_iterator cbegin() const
-  {
-    return begin();
-  }
-
-  /// Obtain an end iterator for the results range.
-  const_iterator cend() const
-  {
-    return end();
-  }
-
-  /// Swap the results range with another.
-  void swap(basic_resolver_results& that) ASIO_NOEXCEPT
-  {
-    if (this != &that)
-    {
-      this->values_.swap(that.values_);
-      std::size_t index = this->index_;
-      this->index_ = that.index_;
-      that.index_ = index;
-    }
-  }
-
-  /// Test two iterators for equality.
-  friend bool operator==(const basic_resolver_results& a,
-      const basic_resolver_results& b)
-  {
-    return a.equal(b);
-  }
-
-  /// Test two iterators for inequality.
-  friend bool operator!=(const basic_resolver_results& a,
-      const basic_resolver_results& b)
-  {
-    return !a.equal(b);
-  }
-
-private:
-  typedef std::vector<basic_resolver_entry<InternetProtocol> > values_type;
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_BASIC_RESOLVER_RESULTS_HPP
diff --git a/tools/sdk/include/asio/asio/ip/detail/endpoint.hpp b/tools/sdk/include/asio/asio/ip/detail/endpoint.hpp
deleted file mode 100644
index 9acefe5fe29..00000000000
--- a/tools/sdk/include/asio/asio/ip/detail/endpoint.hpp
+++ /dev/null
@@ -1,139 +0,0 @@
-//
-// ip/detail/endpoint.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_DETAIL_ENDPOINT_HPP
-#define ASIO_IP_DETAIL_ENDPOINT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/winsock_init.hpp"
-#include "asio/error_code.hpp"
-#include "asio/ip/address.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-namespace detail {
-
-// Helper class for implementating an IP endpoint.
-class endpoint
-{
-public:
-  // Default constructor.
-  ASIO_DECL endpoint();
-
-  // Construct an endpoint using a family and port number.
-  ASIO_DECL endpoint(int family, unsigned short port_num);
-
-  // Construct an endpoint using an address and port number.
-  ASIO_DECL endpoint(const asio::ip::address& addr,
-      unsigned short port_num);
-
-  // Copy constructor.
-  endpoint(const endpoint& other)
-    : data_(other.data_)
-  {
-  }
-
-  // Assign from another endpoint.
-  endpoint& operator=(const endpoint& other)
-  {
-    data_ = other.data_;
-    return *this;
-  }
-
-  // Get the underlying endpoint in the native type.
-  asio::detail::socket_addr_type* data()
-  {
-    return &data_.base;
-  }
-
-  // Get the underlying endpoint in the native type.
-  const asio::detail::socket_addr_type* data() const
-  {
-    return &data_.base;
-  }
-
-  // Get the underlying size of the endpoint in the native type.
-  std::size_t size() const
-  {
-    if (is_v4())
-      return sizeof(asio::detail::sockaddr_in4_type);
-    else
-      return sizeof(asio::detail::sockaddr_in6_type);
-  }
-
-  // Set the underlying size of the endpoint in the native type.
-  ASIO_DECL void resize(std::size_t new_size);
-
-  // Get the capacity of the endpoint in the native type.
-  std::size_t capacity() const
-  {
-    return sizeof(data_);
-  }
-
-  // Get the port associated with the endpoint.
-  ASIO_DECL unsigned short port() const;
-
-  // Set the port associated with the endpoint.
-  ASIO_DECL void port(unsigned short port_num);
-
-  // Get the IP address associated with the endpoint.
-  ASIO_DECL asio::ip::address address() const;
-
-  // Set the IP address associated with the endpoint.
-  ASIO_DECL void address(const asio::ip::address& addr);
-
-  // Compare two endpoints for equality.
-  ASIO_DECL friend bool operator==(
-      const endpoint& e1, const endpoint& e2);
-
-  // Compare endpoints for ordering.
-  ASIO_DECL friend bool operator<(
-      const endpoint& e1, const endpoint& e2);
-
-  // Determine whether the endpoint is IPv4.
-  bool is_v4() const
-  {
-    return data_.base.sa_family == ASIO_OS_DEF(AF_INET);
-  }
-
-#if !defined(ASIO_NO_IOSTREAM)
-  // Convert to a string.
-  ASIO_DECL std::string to_string() const;
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-private:
-  // The underlying IP socket address.
-  union data_union
-  {
-    asio::detail::socket_addr_type base;
-    asio::detail::sockaddr_in4_type v4;
-    asio::detail::sockaddr_in6_type v6;
-  } data_;
-};
-
-} // namespace detail
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ip/detail/impl/endpoint.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_IP_DETAIL_ENDPOINT_HPP
diff --git a/tools/sdk/include/asio/asio/ip/detail/socket_option.hpp b/tools/sdk/include/asio/asio/ip/detail/socket_option.hpp
deleted file mode 100644
index 051ef30db95..00000000000
--- a/tools/sdk/include/asio/asio/ip/detail/socket_option.hpp
+++ /dev/null
@@ -1,566 +0,0 @@
-//
-// detail/socket_option.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_DETAIL_SOCKET_OPTION_HPP
-#define ASIO_IP_DETAIL_SOCKET_OPTION_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <cstring>
-#include <stdexcept>
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/detail/throw_exception.hpp"
-#include "asio/ip/address.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-namespace detail {
-namespace socket_option {
-
-// Helper template for implementing multicast enable loopback options.
-template <int IPv4_Level, int IPv4_Name, int IPv6_Level, int IPv6_Name>
-class multicast_enable_loopback
-{
-public:
-#if defined(__sun) || defined(__osf__)
-  typedef unsigned char ipv4_value_type;
-  typedef unsigned char ipv6_value_type;
-#elif defined(_AIX) || defined(__hpux) || defined(__QNXNTO__) 
-  typedef unsigned char ipv4_value_type;
-  typedef unsigned int ipv6_value_type;
-#else
-  typedef int ipv4_value_type;
-  typedef int ipv6_value_type;
-#endif
-
-  // Default constructor.
-  multicast_enable_loopback()
-    : ipv4_value_(0),
-      ipv6_value_(0)
-  {
-  }
-
-  // Construct with a specific option value.
-  explicit multicast_enable_loopback(bool v)
-    : ipv4_value_(v ? 1 : 0),
-      ipv6_value_(v ? 1 : 0)
-  {
-  }
-
-  // Set the value of the boolean.
-  multicast_enable_loopback& operator=(bool v)
-  {
-    ipv4_value_ = v ? 1 : 0;
-    ipv6_value_ = v ? 1 : 0;
-    return *this;
-  }
-
-  // Get the current value of the boolean.
-  bool value() const
-  {
-    return !!ipv4_value_;
-  }
-
-  // Convert to bool.
-  operator bool() const
-  {
-    return !!ipv4_value_;
-  }
-
-  // Test for false.
-  bool operator!() const
-  {
-    return !ipv4_value_;
-  }
-
-  // Get the level of the socket option.
-  template <typename Protocol>
-  int level(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Level;
-    return IPv4_Level;
-  }
-
-  // Get the name of the socket option.
-  template <typename Protocol>
-  int name(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Name;
-    return IPv4_Name;
-  }
-
-  // Get the address of the boolean data.
-  template <typename Protocol>
-  void* data(const Protocol& protocol)
-  {
-    if (protocol.family() == PF_INET6)
-      return &ipv6_value_;
-    return &ipv4_value_;
-  }
-
-  // Get the address of the boolean data.
-  template <typename Protocol>
-  const void* data(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return &ipv6_value_;
-    return &ipv4_value_;
-  }
-
-  // Get the size of the boolean data.
-  template <typename Protocol>
-  std::size_t size(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return sizeof(ipv6_value_);
-    return sizeof(ipv4_value_);
-  }
-
-  // Set the size of the boolean data.
-  template <typename Protocol>
-  void resize(const Protocol& protocol, std::size_t s)
-  {
-    if (protocol.family() == PF_INET6)
-    {
-      if (s != sizeof(ipv6_value_))
-      {
-        std::length_error ex("multicast_enable_loopback socket option resize");
-        asio::detail::throw_exception(ex);
-      }
-      ipv4_value_ = ipv6_value_ ? 1 : 0;
-    }
-    else
-    {
-      if (s != sizeof(ipv4_value_))
-      {
-        std::length_error ex("multicast_enable_loopback socket option resize");
-        asio::detail::throw_exception(ex);
-      }
-      ipv6_value_ = ipv4_value_ ? 1 : 0;
-    }
-  }
-
-private:
-  ipv4_value_type ipv4_value_;
-  ipv6_value_type ipv6_value_;
-};
-
-// Helper template for implementing unicast hops options.
-template <int IPv4_Level, int IPv4_Name, int IPv6_Level, int IPv6_Name>
-class unicast_hops
-{
-public:
-  // Default constructor.
-  unicast_hops()
-    : value_(0)
-  {
-  }
-
-  // Construct with a specific option value.
-  explicit unicast_hops(int v)
-    : value_(v)
-  {
-  }
-
-  // Set the value of the option.
-  unicast_hops& operator=(int v)
-  {
-    value_ = v;
-    return *this;
-  }
-
-  // Get the current value of the option.
-  int value() const
-  {
-    return value_;
-  }
-
-  // Get the level of the socket option.
-  template <typename Protocol>
-  int level(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Level;
-    return IPv4_Level;
-  }
-
-  // Get the name of the socket option.
-  template <typename Protocol>
-  int name(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Name;
-    return IPv4_Name;
-  }
-
-  // Get the address of the data.
-  template <typename Protocol>
-  int* data(const Protocol&)
-  {
-    return &value_;
-  }
-
-  // Get the address of the data.
-  template <typename Protocol>
-  const int* data(const Protocol&) const
-  {
-    return &value_;
-  }
-
-  // Get the size of the data.
-  template <typename Protocol>
-  std::size_t size(const Protocol&) const
-  {
-    return sizeof(value_);
-  }
-
-  // Set the size of the data.
-  template <typename Protocol>
-  void resize(const Protocol&, std::size_t s)
-  {
-    if (s != sizeof(value_))
-    {
-      std::length_error ex("unicast hops socket option resize");
-      asio::detail::throw_exception(ex);
-    }
-#if defined(__hpux)
-    if (value_ < 0)
-      value_ = value_ & 0xFF;
-#endif
-  }
-
-private:
-  int value_;
-};
-
-// Helper template for implementing multicast hops options.
-template <int IPv4_Level, int IPv4_Name, int IPv6_Level, int IPv6_Name>
-class multicast_hops
-{
-public:
-#if defined(ASIO_WINDOWS) && defined(UNDER_CE)
-  typedef int ipv4_value_type;
-#else
-  typedef unsigned char ipv4_value_type;
-#endif
-  typedef int ipv6_value_type;
-
-  // Default constructor.
-  multicast_hops()
-    : ipv4_value_(0),
-      ipv6_value_(0)
-  {
-  }
-
-  // Construct with a specific option value.
-  explicit multicast_hops(int v)
-  {
-    if (v < 0 || v > 255)
-    {
-      std::out_of_range ex("multicast hops value out of range");
-      asio::detail::throw_exception(ex);
-    }
-    ipv4_value_ = (ipv4_value_type)v;
-    ipv6_value_ = v;
-  }
-
-  // Set the value of the option.
-  multicast_hops& operator=(int v)
-  {
-    if (v < 0 || v > 255)
-    {
-      std::out_of_range ex("multicast hops value out of range");
-      asio::detail::throw_exception(ex);
-    }
-    ipv4_value_ = (ipv4_value_type)v;
-    ipv6_value_ = v;
-    return *this;
-  }
-
-  // Get the current value of the option.
-  int value() const
-  {
-    return ipv6_value_;
-  }
-
-  // Get the level of the socket option.
-  template <typename Protocol>
-  int level(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Level;
-    return IPv4_Level;
-  }
-
-  // Get the name of the socket option.
-  template <typename Protocol>
-  int name(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Name;
-    return IPv4_Name;
-  }
-
-  // Get the address of the data.
-  template <typename Protocol>
-  void* data(const Protocol& protocol)
-  {
-    if (protocol.family() == PF_INET6)
-      return &ipv6_value_;
-    return &ipv4_value_;
-  }
-
-  // Get the address of the data.
-  template <typename Protocol>
-  const void* data(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return &ipv6_value_;
-    return &ipv4_value_;
-  }
-
-  // Get the size of the data.
-  template <typename Protocol>
-  std::size_t size(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return sizeof(ipv6_value_);
-    return sizeof(ipv4_value_);
-  }
-
-  // Set the size of the data.
-  template <typename Protocol>
-  void resize(const Protocol& protocol, std::size_t s)
-  {
-    if (protocol.family() == PF_INET6)
-    {
-      if (s != sizeof(ipv6_value_))
-      {
-        std::length_error ex("multicast hops socket option resize");
-        asio::detail::throw_exception(ex);
-      }
-      if (ipv6_value_ < 0)
-        ipv4_value_ = 0;
-      else if (ipv6_value_ > 255)
-        ipv4_value_ = 255;
-      else
-        ipv4_value_ = (ipv4_value_type)ipv6_value_;
-    }
-    else
-    {
-      if (s != sizeof(ipv4_value_))
-      {
-        std::length_error ex("multicast hops socket option resize");
-        asio::detail::throw_exception(ex);
-      }
-      ipv6_value_ = ipv4_value_;
-    }
-  }
-
-private:
-  ipv4_value_type ipv4_value_;
-  ipv6_value_type ipv6_value_;
-};
-
-// Helper template for implementing ip_mreq-based options.
-template <int IPv4_Level, int IPv4_Name, int IPv6_Level, int IPv6_Name>
-class multicast_request
-{
-public:
-  // Default constructor.
-  multicast_request()
-    : ipv4_value_(), // Zero-initialisation gives the "any" address.
-      ipv6_value_() // Zero-initialisation gives the "any" address.
-  {
-  }
-
-  // Construct with multicast address only.
-  explicit multicast_request(const address& multicast_address)
-    : ipv4_value_(), // Zero-initialisation gives the "any" address.
-      ipv6_value_() // Zero-initialisation gives the "any" address.
-  {
-    if (multicast_address.is_v6())
-    {
-      using namespace std; // For memcpy.
-      address_v6 ipv6_address = multicast_address.to_v6();
-      address_v6::bytes_type bytes = ipv6_address.to_bytes();
-      memcpy(ipv6_value_.ipv6mr_multiaddr.s6_addr, bytes.data(), 16);
-      ipv6_value_.ipv6mr_interface = ipv6_address.scope_id();
-    }
-    else
-    {
-      ipv4_value_.imr_multiaddr.s_addr =
-        asio::detail::socket_ops::host_to_network_long(
-            multicast_address.to_v4().to_uint());
-      ipv4_value_.imr_interface.s_addr =
-        asio::detail::socket_ops::host_to_network_long(
-            address_v4::any().to_uint());
-    }
-  }
-
-  // Construct with multicast address and IPv4 address specifying an interface.
-  explicit multicast_request(const address_v4& multicast_address,
-      const address_v4& network_interface = address_v4::any())
-    : ipv6_value_() // Zero-initialisation gives the "any" address.
-  {
-    ipv4_value_.imr_multiaddr.s_addr =
-      asio::detail::socket_ops::host_to_network_long(
-          multicast_address.to_uint());
-    ipv4_value_.imr_interface.s_addr =
-      asio::detail::socket_ops::host_to_network_long(
-          network_interface.to_uint());
-  }
-
-  // Construct with multicast address and IPv6 network interface index.
-  explicit multicast_request(
-      const address_v6& multicast_address,
-      unsigned long network_interface = 0)
-    : ipv4_value_() // Zero-initialisation gives the "any" address.
-  {
-    using namespace std; // For memcpy.
-    address_v6::bytes_type bytes = multicast_address.to_bytes();
-    memcpy(ipv6_value_.ipv6mr_multiaddr.s6_addr, bytes.data(), 16);
-    if (network_interface)
-      ipv6_value_.ipv6mr_interface = network_interface;
-    else
-      ipv6_value_.ipv6mr_interface = multicast_address.scope_id();
-  }
-
-  // Get the level of the socket option.
-  template <typename Protocol>
-  int level(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Level;
-    return IPv4_Level;
-  }
-
-  // Get the name of the socket option.
-  template <typename Protocol>
-  int name(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Name;
-    return IPv4_Name;
-  }
-
-  // Get the address of the option data.
-  template <typename Protocol>
-  const void* data(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return &ipv6_value_;
-    return &ipv4_value_;
-  }
-
-  // Get the size of the option data.
-  template <typename Protocol>
-  std::size_t size(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return sizeof(ipv6_value_);
-    return sizeof(ipv4_value_);
-  }
-
-private:
-  asio::detail::in4_mreq_type ipv4_value_;
-  asio::detail::in6_mreq_type ipv6_value_;
-};
-
-// Helper template for implementing options that specify a network interface.
-template <int IPv4_Level, int IPv4_Name, int IPv6_Level, int IPv6_Name>
-class network_interface
-{
-public:
-  // Default constructor.
-  network_interface()
-  {
-    ipv4_value_.s_addr =
-      asio::detail::socket_ops::host_to_network_long(
-          address_v4::any().to_uint());
-    ipv6_value_ = 0;
-  }
-
-  // Construct with IPv4 interface.
-  explicit network_interface(const address_v4& ipv4_interface)
-  {
-    ipv4_value_.s_addr =
-      asio::detail::socket_ops::host_to_network_long(
-          ipv4_interface.to_uint());
-    ipv6_value_ = 0;
-  }
-
-  // Construct with IPv6 interface.
-  explicit network_interface(unsigned int ipv6_interface)
-  {
-    ipv4_value_.s_addr =
-      asio::detail::socket_ops::host_to_network_long(
-          address_v4::any().to_uint());
-    ipv6_value_ = ipv6_interface;
-  }
-
-  // Get the level of the socket option.
-  template <typename Protocol>
-  int level(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Level;
-    return IPv4_Level;
-  }
-
-  // Get the name of the socket option.
-  template <typename Protocol>
-  int name(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return IPv6_Name;
-    return IPv4_Name;
-  }
-
-  // Get the address of the option data.
-  template <typename Protocol>
-  const void* data(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return &ipv6_value_;
-    return &ipv4_value_;
-  }
-
-  // Get the size of the option data.
-  template <typename Protocol>
-  std::size_t size(const Protocol& protocol) const
-  {
-    if (protocol.family() == PF_INET6)
-      return sizeof(ipv6_value_);
-    return sizeof(ipv4_value_);
-  }
-
-private:
-  asio::detail::in4_addr_type ipv4_value_;
-  unsigned int ipv6_value_;
-};
-
-} // namespace socket_option
-} // namespace detail
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_DETAIL_SOCKET_OPTION_HPP
diff --git a/tools/sdk/include/asio/asio/ip/host_name.hpp b/tools/sdk/include/asio/asio/ip/host_name.hpp
deleted file mode 100644
index d06de5089ab..00000000000
--- a/tools/sdk/include/asio/asio/ip/host_name.hpp
+++ /dev/null
@@ -1,42 +0,0 @@
-//
-// ip/host_name.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_HOST_NAME_HPP
-#define ASIO_IP_HOST_NAME_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/error_code.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Get the current host name.
-ASIO_DECL std::string host_name();
-
-/// Get the current host name.
-ASIO_DECL std::string host_name(asio::error_code& ec);
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ip/impl/host_name.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_IP_HOST_NAME_HPP
diff --git a/tools/sdk/include/asio/asio/ip/icmp.hpp b/tools/sdk/include/asio/asio/ip/icmp.hpp
deleted file mode 100644
index 92e1953f301..00000000000
--- a/tools/sdk/include/asio/asio/ip/icmp.hpp
+++ /dev/null
@@ -1,115 +0,0 @@
-//
-// ip/icmp.hpp
-// ~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_ICMP_HPP
-#define ASIO_IP_ICMP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/basic_raw_socket.hpp"
-#include "asio/ip/basic_endpoint.hpp"
-#include "asio/ip/basic_resolver.hpp"
-#include "asio/ip/basic_resolver_iterator.hpp"
-#include "asio/ip/basic_resolver_query.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Encapsulates the flags needed for ICMP.
-/**
- * The asio::ip::icmp class contains flags necessary for ICMP sockets.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Protocol, InternetProtocol.
- */
-class icmp
-{
-public:
-  /// The type of a ICMP endpoint.
-  typedef basic_endpoint<icmp> endpoint;
-
-  /// Construct to represent the IPv4 ICMP protocol.
-  static icmp v4()
-  {
-    return icmp(ASIO_OS_DEF(IPPROTO_ICMP),
-        ASIO_OS_DEF(AF_INET));
-  }
-
-  /// Construct to represent the IPv6 ICMP protocol.
-  static icmp v6()
-  {
-    return icmp(ASIO_OS_DEF(IPPROTO_ICMPV6),
-        ASIO_OS_DEF(AF_INET6));
-  }
-
-  /// Obtain an identifier for the type of the protocol.
-  int type() const
-  {
-    return ASIO_OS_DEF(SOCK_RAW);
-  }
-
-  /// Obtain an identifier for the protocol.
-  int protocol() const
-  {
-    return protocol_;
-  }
-
-  /// Obtain an identifier for the protocol family.
-  int family() const
-  {
-    return family_;
-  }
-
-  /// The ICMP socket type.
-  typedef basic_raw_socket<icmp> socket;
-
-  /// The ICMP resolver type.
-  typedef basic_resolver<icmp> resolver;
-
-  /// Compare two protocols for equality.
-  friend bool operator==(const icmp& p1, const icmp& p2)
-  {
-    return p1.protocol_ == p2.protocol_ && p1.family_ == p2.family_;
-  }
-
-  /// Compare two protocols for inequality.
-  friend bool operator!=(const icmp& p1, const icmp& p2)
-  {
-    return p1.protocol_ != p2.protocol_ || p1.family_ != p2.family_;
-  }
-
-private:
-  // Construct with a specific family.
-  explicit icmp(int protocol_id, int protocol_family)
-    : protocol_(protocol_id),
-      family_(protocol_family)
-  {
-  }
-
-  int protocol_;
-  int family_;
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_ICMP_HPP
diff --git a/tools/sdk/include/asio/asio/ip/impl/address.hpp b/tools/sdk/include/asio/asio/ip/impl/address.hpp
deleted file mode 100644
index 085b93f7b51..00000000000
--- a/tools/sdk/include/asio/asio/ip/impl/address.hpp
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// ip/impl/address.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_IMPL_ADDRESS_HPP
-#define ASIO_IP_IMPL_ADDRESS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-inline address address::from_string(const char* str)
-{
-  return asio::ip::make_address(str);
-}
-
-inline address address::from_string(
-    const char* str, asio::error_code& ec)
-{
-  return asio::ip::make_address(str, ec);
-}
-
-inline address address::from_string(const std::string& str)
-{
-  return asio::ip::make_address(str);
-}
-
-inline address address::from_string(
-    const std::string& str, asio::error_code& ec)
-{
-  return asio::ip::make_address(str, ec);
-}
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const address& addr)
-{
-  return os << addr.to_string().c_str();
-}
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_IP_IMPL_ADDRESS_HPP
diff --git a/tools/sdk/include/asio/asio/ip/impl/address_v4.hpp b/tools/sdk/include/asio/asio/ip/impl/address_v4.hpp
deleted file mode 100644
index d1cf407c30c..00000000000
--- a/tools/sdk/include/asio/asio/ip/impl/address_v4.hpp
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// ip/impl/address_v4.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_IMPL_ADDRESS_V4_HPP
-#define ASIO_IP_IMPL_ADDRESS_V4_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-inline address_v4 address_v4::from_string(const char* str)
-{
-  return asio::ip::make_address_v4(str);
-}
-
-inline address_v4 address_v4::from_string(
-    const char* str, asio::error_code& ec)
-{
-  return asio::ip::make_address_v4(str, ec);
-}
-
-inline address_v4 address_v4::from_string(const std::string& str)
-{
-  return asio::ip::make_address_v4(str);
-}
-
-inline address_v4 address_v4::from_string(
-    const std::string& str, asio::error_code& ec)
-{
-  return asio::ip::make_address_v4(str, ec);
-}
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const address_v4& addr)
-{
-  return os << addr.to_string().c_str();
-}
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_IP_IMPL_ADDRESS_V4_HPP
diff --git a/tools/sdk/include/asio/asio/ip/impl/address_v6.hpp b/tools/sdk/include/asio/asio/ip/impl/address_v6.hpp
deleted file mode 100644
index 330eafd1fed..00000000000
--- a/tools/sdk/include/asio/asio/ip/impl/address_v6.hpp
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// ip/impl/address_v6.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_IMPL_ADDRESS_V6_HPP
-#define ASIO_IP_IMPL_ADDRESS_V6_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-#if !defined(ASIO_NO_DEPRECATED)
-
-inline address_v6 address_v6::from_string(const char* str)
-{
-  return asio::ip::make_address_v6(str);
-}
-
-inline address_v6 address_v6::from_string(
-    const char* str, asio::error_code& ec)
-{
-  return asio::ip::make_address_v6(str, ec);
-}
-
-inline address_v6 address_v6::from_string(const std::string& str)
-{
-  return asio::ip::make_address_v6(str);
-}
-
-inline address_v6 address_v6::from_string(
-    const std::string& str, asio::error_code& ec)
-{
-  return asio::ip::make_address_v6(str, ec);
-}
-
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const address_v6& addr)
-{
-  return os << addr.to_string().c_str();
-}
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_IP_IMPL_ADDRESS_V6_HPP
diff --git a/tools/sdk/include/asio/asio/ip/impl/basic_endpoint.hpp b/tools/sdk/include/asio/asio/ip/impl/basic_endpoint.hpp
deleted file mode 100644
index 5680a438176..00000000000
--- a/tools/sdk/include/asio/asio/ip/impl/basic_endpoint.hpp
+++ /dev/null
@@ -1,43 +0,0 @@
-//
-// ip/impl/basic_endpoint.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_IMPL_BASIC_ENDPOINT_HPP
-#define ASIO_IP_IMPL_BASIC_ENDPOINT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-template <typename Elem, typename Traits, typename InternetProtocol>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os,
-    const basic_endpoint<InternetProtocol>& endpoint)
-{
-  asio::ip::detail::endpoint tmp_ep(endpoint.address(), endpoint.port());
-  return os << tmp_ep.to_string().c_str();
-}
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_IP_IMPL_BASIC_ENDPOINT_HPP
diff --git a/tools/sdk/include/asio/asio/ip/impl/network_v4.hpp b/tools/sdk/include/asio/asio/ip/impl/network_v4.hpp
deleted file mode 100644
index 911a45c3fbe..00000000000
--- a/tools/sdk/include/asio/asio/ip/impl/network_v4.hpp
+++ /dev/null
@@ -1,54 +0,0 @@
-//
-// ip/impl/network_v4.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2014 Oliver Kowalke (oliver dot kowalke at gmail dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_IMPL_NETWORK_V4_HPP
-#define ASIO_IP_IMPL_NETWORK_V4_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const network_v4& addr)
-{
-  asio::error_code ec;
-  std::string s = addr.to_string(ec);
-  if (ec)
-  {
-    if (os.exceptions() & std::basic_ostream<Elem, Traits>::failbit)
-      asio::detail::throw_error(ec);
-    else
-      os.setstate(std::basic_ostream<Elem, Traits>::failbit);
-  }
-  else
-    for (std::string::iterator i = s.begin(); i != s.end(); ++i)
-      os << os.widen(*i);
-  return os;
-}
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_IP_IMPL_NETWORK_V4_HPP
diff --git a/tools/sdk/include/asio/asio/ip/impl/network_v6.hpp b/tools/sdk/include/asio/asio/ip/impl/network_v6.hpp
deleted file mode 100644
index b0eedaded2e..00000000000
--- a/tools/sdk/include/asio/asio/ip/impl/network_v6.hpp
+++ /dev/null
@@ -1,53 +0,0 @@
-//
-// ip/impl/network_v6.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_IMPL_NETWORK_V6_HPP
-#define ASIO_IP_IMPL_NETWORK_V6_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const network_v6& addr)
-{
-  asio::error_code ec;
-  std::string s = addr.to_string(ec);
-  if (ec)
-  {
-    if (os.exceptions() & std::basic_ostream<Elem, Traits>::failbit)
-      asio::detail::throw_error(ec);
-    else
-      os.setstate(std::basic_ostream<Elem, Traits>::failbit);
-  }
-  else
-    for (std::string::iterator i = s.begin(); i != s.end(); ++i)
-      os << os.widen(*i);
-  return os;
-}
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_IP_IMPL_NETWORK_V6_HPP
diff --git a/tools/sdk/include/asio/asio/ip/multicast.hpp b/tools/sdk/include/asio/asio/ip/multicast.hpp
deleted file mode 100644
index ea624e147b7..00000000000
--- a/tools/sdk/include/asio/asio/ip/multicast.hpp
+++ /dev/null
@@ -1,191 +0,0 @@
-//
-// ip/multicast.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_MULTICAST_HPP
-#define ASIO_IP_MULTICAST_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/ip/detail/socket_option.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-namespace multicast {
-
-/// Socket option to join a multicast group on a specified interface.
-/**
- * Implements the IPPROTO_IP/IP_ADD_MEMBERSHIP socket option.
- *
- * @par Examples
- * Setting the option to join a multicast group:
- * @code
- * asio::ip::udp::socket socket(io_context); 
- * ...
- * asio::ip::address multicast_address =
- *   asio::ip::address::from_string("225.0.0.1");
- * asio::ip::multicast::join_group option(multicast_address);
- * socket.set_option(option);
- * @endcode
- *
- * @par Concepts:
- * SettableSocketOption.
- */
-#if defined(GENERATING_DOCUMENTATION)
-typedef implementation_defined join_group;
-#else
-typedef asio::ip::detail::socket_option::multicast_request<
-  ASIO_OS_DEF(IPPROTO_IP),
-  ASIO_OS_DEF(IP_ADD_MEMBERSHIP),
-  ASIO_OS_DEF(IPPROTO_IPV6),
-  ASIO_OS_DEF(IPV6_JOIN_GROUP)> join_group;
-#endif
-
-/// Socket option to leave a multicast group on a specified interface.
-/**
- * Implements the IPPROTO_IP/IP_DROP_MEMBERSHIP socket option.
- *
- * @par Examples
- * Setting the option to leave a multicast group:
- * @code
- * asio::ip::udp::socket socket(io_context); 
- * ...
- * asio::ip::address multicast_address =
- *   asio::ip::address::from_string("225.0.0.1");
- * asio::ip::multicast::leave_group option(multicast_address);
- * socket.set_option(option);
- * @endcode
- *
- * @par Concepts:
- * SettableSocketOption.
- */
-#if defined(GENERATING_DOCUMENTATION)
-typedef implementation_defined leave_group;
-#else
-typedef asio::ip::detail::socket_option::multicast_request<
-  ASIO_OS_DEF(IPPROTO_IP),
-  ASIO_OS_DEF(IP_DROP_MEMBERSHIP),
-  ASIO_OS_DEF(IPPROTO_IPV6),
-  ASIO_OS_DEF(IPV6_LEAVE_GROUP)> leave_group;
-#endif
-
-/// Socket option for local interface to use for outgoing multicast packets.
-/**
- * Implements the IPPROTO_IP/IP_MULTICAST_IF socket option.
- *
- * @par Examples
- * Setting the option:
- * @code
- * asio::ip::udp::socket socket(io_context); 
- * ...
- * asio::ip::address_v4 local_interface =
- *   asio::ip::address_v4::from_string("1.2.3.4");
- * asio::ip::multicast::outbound_interface option(local_interface);
- * socket.set_option(option);
- * @endcode
- *
- * @par Concepts:
- * SettableSocketOption.
- */
-#if defined(GENERATING_DOCUMENTATION)
-typedef implementation_defined outbound_interface;
-#else
-typedef asio::ip::detail::socket_option::network_interface<
-  ASIO_OS_DEF(IPPROTO_IP),
-  ASIO_OS_DEF(IP_MULTICAST_IF),
-  ASIO_OS_DEF(IPPROTO_IPV6),
-  ASIO_OS_DEF(IPV6_MULTICAST_IF)> outbound_interface;
-#endif
-
-/// Socket option for time-to-live associated with outgoing multicast packets.
-/**
- * Implements the IPPROTO_IP/IP_MULTICAST_TTL socket option.
- *
- * @par Examples
- * Setting the option:
- * @code
- * asio::ip::udp::socket socket(io_context); 
- * ...
- * asio::ip::multicast::hops option(4);
- * socket.set_option(option);
- * @endcode
- *
- * @par
- * Getting the current option value:
- * @code
- * asio::ip::udp::socket socket(io_context); 
- * ...
- * asio::ip::multicast::hops option;
- * socket.get_option(option);
- * int ttl = option.value();
- * @endcode
- *
- * @par Concepts:
- * GettableSocketOption, SettableSocketOption.
- */
-#if defined(GENERATING_DOCUMENTATION)
-typedef implementation_defined hops;
-#else
-typedef asio::ip::detail::socket_option::multicast_hops<
-  ASIO_OS_DEF(IPPROTO_IP),
-  ASIO_OS_DEF(IP_MULTICAST_TTL),
-  ASIO_OS_DEF(IPPROTO_IPV6),
-  ASIO_OS_DEF(IPV6_MULTICAST_HOPS)> hops;
-#endif
-
-/// Socket option determining whether outgoing multicast packets will be
-/// received on the same socket if it is a member of the multicast group.
-/**
- * Implements the IPPROTO_IP/IP_MULTICAST_LOOP socket option.
- *
- * @par Examples
- * Setting the option:
- * @code
- * asio::ip::udp::socket socket(io_context); 
- * ...
- * asio::ip::multicast::enable_loopback option(true);
- * socket.set_option(option);
- * @endcode
- *
- * @par
- * Getting the current option value:
- * @code
- * asio::ip::udp::socket socket(io_context); 
- * ...
- * asio::ip::multicast::enable_loopback option;
- * socket.get_option(option);
- * bool is_set = option.value();
- * @endcode
- *
- * @par Concepts:
- * GettableSocketOption, SettableSocketOption.
- */
-#if defined(GENERATING_DOCUMENTATION)
-typedef implementation_defined enable_loopback;
-#else
-typedef asio::ip::detail::socket_option::multicast_enable_loopback<
-  ASIO_OS_DEF(IPPROTO_IP),
-  ASIO_OS_DEF(IP_MULTICAST_LOOP),
-  ASIO_OS_DEF(IPPROTO_IPV6),
-  ASIO_OS_DEF(IPV6_MULTICAST_LOOP)> enable_loopback;
-#endif
-
-} // namespace multicast
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_MULTICAST_HPP
diff --git a/tools/sdk/include/asio/asio/ip/network_v4.hpp b/tools/sdk/include/asio/asio/ip/network_v4.hpp
deleted file mode 100644
index e38f60fe9ae..00000000000
--- a/tools/sdk/include/asio/asio/ip/network_v4.hpp
+++ /dev/null
@@ -1,261 +0,0 @@
-//
-// ip/network_v4.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2014 Oliver Kowalke (oliver dot kowalke at gmail dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_NETWORK_V4_HPP
-#define ASIO_IP_NETWORK_V4_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/detail/string_view.hpp"
-#include "asio/error_code.hpp"
-#include "asio/ip/address_v4_range.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Represents an IPv4 network.
-/**
- * The asio::ip::network_v4 class provides the ability to use and
- * manipulate IP version 4 networks.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class network_v4
-{
-public:
-  /// Default constructor.
-  network_v4() ASIO_NOEXCEPT
-    : address_(),
-      prefix_length_(0)
-  {
-  }
-
-  /// Construct a network based on the specified address and prefix length.
-  ASIO_DECL network_v4(const address_v4& addr,
-      unsigned short prefix_len);
-
-  /// Construct network based on the specified address and netmask.
-  ASIO_DECL network_v4(const address_v4& addr,
-      const address_v4& mask);
-
-  /// Copy constructor.
-  network_v4(const network_v4& other) ASIO_NOEXCEPT
-    : address_(other.address_),
-      prefix_length_(other.prefix_length_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  network_v4(network_v4&& other) ASIO_NOEXCEPT
-    : address_(ASIO_MOVE_CAST(address_v4)(other.address_)),
-      prefix_length_(other.prefix_length_)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assign from another network.
-  network_v4& operator=(const network_v4& other) ASIO_NOEXCEPT
-  {
-    address_ = other.address_;
-    prefix_length_ = other.prefix_length_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move-assign from another network.
-  network_v4& operator=(network_v4&& other) ASIO_NOEXCEPT
-  {
-    address_ = ASIO_MOVE_CAST(address_v4)(other.address_);
-    prefix_length_ = other.prefix_length_;
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Obtain the address object specified when the network object was created.
-  address_v4 address() const ASIO_NOEXCEPT
-  {
-    return address_;
-  }
-
-  /// Obtain the prefix length that was specified when the network object was
-  /// created.
-  unsigned short prefix_length() const ASIO_NOEXCEPT
-  {
-    return prefix_length_;
-  }
-
-  /// Obtain the netmask that was specified when the network object was created.
-  ASIO_DECL address_v4 netmask() const ASIO_NOEXCEPT;
-
-  /// Obtain an address object that represents the network address.
-  address_v4 network() const ASIO_NOEXCEPT
-  {
-    return address_v4(address_.to_uint() & netmask().to_uint());
-  }
-
-  /// Obtain an address object that represents the network's broadcast address.
-  address_v4 broadcast() const ASIO_NOEXCEPT
-  {
-    return address_v4(network().to_uint() | (netmask().to_uint() ^ 0xFFFFFFFF));
-  }
-
-  /// Obtain an address range corresponding to the hosts in the network.
-  ASIO_DECL address_v4_range hosts() const ASIO_NOEXCEPT;
-
-  /// Obtain the true network address, omitting any host bits.
-  network_v4 canonical() const ASIO_NOEXCEPT
-  {
-    return network_v4(network(), netmask());
-  }
-
-  /// Test if network is a valid host address.
-  bool is_host() const ASIO_NOEXCEPT
-  {
-    return prefix_length_ == 32;
-  }
-
-  /// Test if a network is a real subnet of another network.
-  ASIO_DECL bool is_subnet_of(const network_v4& other) const;
-
-  /// Get the network as an address in dotted decimal format.
-  ASIO_DECL std::string to_string() const;
-
-  /// Get the network as an address in dotted decimal format.
-  ASIO_DECL std::string to_string(asio::error_code& ec) const;
-
-  /// Compare two networks for equality.
-  friend bool operator==(const network_v4& a, const network_v4& b)
-  {
-    return a.address_ == b.address_ && a.prefix_length_ == b.prefix_length_;
-  }
-
-  /// Compare two networks for inequality.
-  friend bool operator!=(const network_v4& a, const network_v4& b)
-  {
-    return !(a == b);
-  }
-
-private:
-  address_v4 address_;
-  unsigned short prefix_length_;
-};
-
-/// Create an IPv4 network from an address and prefix length.
-/**
- * @relates address_v4
- */
-inline network_v4 make_network_v4(
-    const address_v4& addr, unsigned short prefix_len)
-{
-  return network_v4(addr, prefix_len);
-}
-
-/// Create an IPv4 network from an address and netmask.
-/**
- * @relates address_v4
- */
-inline network_v4 make_network_v4(
-    const address_v4& addr, const address_v4& mask)
-{
-  return network_v4(addr, mask);
-}
-
-/// Create an IPv4 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v4
- */
-ASIO_DECL network_v4 make_network_v4(const char* str);
-
-/// Create an IPv4 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v4
- */
-ASIO_DECL network_v4 make_network_v4(
-    const char* str, asio::error_code& ec);
-
-/// Create an IPv4 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v4
- */
-ASIO_DECL network_v4 make_network_v4(const std::string& str);
-
-/// Create an IPv4 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v4
- */
-ASIO_DECL network_v4 make_network_v4(
-    const std::string& str, asio::error_code& ec);
-
-#if defined(ASIO_HAS_STRING_VIEW) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Create an IPv4 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v4
- */
-ASIO_DECL network_v4 make_network_v4(string_view str);
-
-/// Create an IPv4 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v4
- */
-ASIO_DECL network_v4 make_network_v4(
-    string_view str, asio::error_code& ec);
-
-#endif // defined(ASIO_HAS_STRING_VIEW)
-       //  || defined(GENERATING_DOCUMENTATION)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Output a network as a string.
-/**
- * Used to output a human-readable string for a specified network.
- *
- * @param os The output stream to which the string will be written.
- *
- * @param net The network to be written.
- *
- * @return The output stream.
- *
- * @relates asio::ip::address_v4
- */
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const network_v4& net);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/ip/impl/network_v4.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ip/impl/network_v4.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_IP_NETWORK_V4_HPP
diff --git a/tools/sdk/include/asio/asio/ip/network_v6.hpp b/tools/sdk/include/asio/asio/ip/network_v6.hpp
deleted file mode 100644
index 7b6b7e61389..00000000000
--- a/tools/sdk/include/asio/asio/ip/network_v6.hpp
+++ /dev/null
@@ -1,235 +0,0 @@
-//
-// ip/network_v6.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2014 Oliver Kowalke (oliver dot kowalke at gmail dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_NETWORK_V6_HPP
-#define ASIO_IP_NETWORK_V6_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <string>
-#include "asio/detail/string_view.hpp"
-#include "asio/error_code.hpp"
-#include "asio/ip/address_v6_range.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Represents an IPv6 network.
-/**
- * The asio::ip::network_v6 class provides the ability to use and
- * manipulate IP version 6 networks.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class network_v6
-{
-public:
-  /// Default constructor.
-  network_v6() ASIO_NOEXCEPT
-    : address_(),
-      prefix_length_(0)
-  {
-  }
-
-  /// Construct a network based on the specified address and prefix length.
-  ASIO_DECL network_v6(const address_v6& addr,
-      unsigned short prefix_len);
-
-  /// Copy constructor.
-  network_v6(const network_v6& other) ASIO_NOEXCEPT
-    : address_(other.address_),
-      prefix_length_(other.prefix_length_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  network_v6(network_v6&& other) ASIO_NOEXCEPT
-    : address_(ASIO_MOVE_CAST(address_v6)(other.address_)),
-      prefix_length_(other.prefix_length_)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assign from another network.
-  network_v6& operator=(const network_v6& other) ASIO_NOEXCEPT
-  {
-    address_ = other.address_;
-    prefix_length_ = other.prefix_length_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move-assign from another network.
-  network_v6& operator=(network_v6&& other) ASIO_NOEXCEPT
-  {
-    address_ = ASIO_MOVE_CAST(address_v6)(other.address_);
-    prefix_length_ = other.prefix_length_;
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Obtain the address object specified when the network object was created.
-  address_v6 address() const ASIO_NOEXCEPT
-  {
-    return address_;
-  }
-
-  /// Obtain the prefix length that was specified when the network object was
-  /// created.
-  unsigned short prefix_length() const ASIO_NOEXCEPT
-  {
-    return prefix_length_;
-  }
-
-  /// Obtain an address object that represents the network address.
-  ASIO_DECL address_v6 network() const ASIO_NOEXCEPT;
-
-  /// Obtain an address range corresponding to the hosts in the network.
-  ASIO_DECL address_v6_range hosts() const ASIO_NOEXCEPT;
-
-  /// Obtain the true network address, omitting any host bits.
-  network_v6 canonical() const ASIO_NOEXCEPT
-  {
-    return network_v6(network(), prefix_length());
-  }
-
-  /// Test if network is a valid host address.
-  bool is_host() const ASIO_NOEXCEPT
-  {
-    return prefix_length_ == 128;
-  }
-
-  /// Test if a network is a real subnet of another network.
-  ASIO_DECL bool is_subnet_of(const network_v6& other) const;
-
-  /// Get the network as an address in dotted decimal format.
-  ASIO_DECL std::string to_string() const;
-
-  /// Get the network as an address in dotted decimal format.
-  ASIO_DECL std::string to_string(asio::error_code& ec) const;
-
-  /// Compare two networks for equality.
-  friend bool operator==(const network_v6& a, const network_v6& b)
-  {
-    return a.address_ == b.address_ && a.prefix_length_ == b.prefix_length_;
-  }
-
-  /// Compare two networks for inequality.
-  friend bool operator!=(const network_v6& a, const network_v6& b)
-  {
-    return !(a == b);
-  }
-
-private:
-  address_v6 address_;
-  unsigned short prefix_length_;
-};
-
-/// Create an IPv6 network from an address and prefix length.
-/**
- * @relates address_v6
- */
-inline network_v6 make_network_v6(
-    const address_v6& addr, unsigned short prefix_len)
-{
-  return network_v6(addr, prefix_len);
-}
-
-/// Create an IPv6 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v6
- */
-ASIO_DECL network_v6 make_network_v6(const char* str);
-
-/// Create an IPv6 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v6
- */
-ASIO_DECL network_v6 make_network_v6(
-    const char* str, asio::error_code& ec);
-
-/// Create an IPv6 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v6
- */
-ASIO_DECL network_v6 make_network_v6(const std::string& str);
-
-/// Create an IPv6 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v6
- */
-ASIO_DECL network_v6 make_network_v6(
-    const std::string& str, asio::error_code& ec);
-
-#if defined(ASIO_HAS_STRING_VIEW) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Create an IPv6 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v6
- */
-ASIO_DECL network_v6 make_network_v6(string_view str);
-
-/// Create an IPv6 network from a string containing IP address and prefix
-/// length.
-/**
- * @relates network_v6
- */
-ASIO_DECL network_v6 make_network_v6(
-    string_view str, asio::error_code& ec);
-
-#endif // defined(ASIO_HAS_STRING_VIEW)
-       //  || defined(GENERATING_DOCUMENTATION)
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Output a network as a string.
-/**
- * Used to output a human-readable string for a specified network.
- *
- * @param os The output stream to which the string will be written.
- *
- * @param net The network to be written.
- *
- * @return The output stream.
- *
- * @relates asio::ip::address_v6
- */
-template <typename Elem, typename Traits>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os, const network_v6& net);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/ip/impl/network_v6.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ip/impl/network_v6.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_IP_NETWORK_V6_HPP
diff --git a/tools/sdk/include/asio/asio/ip/resolver_base.hpp b/tools/sdk/include/asio/asio/ip/resolver_base.hpp
deleted file mode 100644
index d32c9110d2b..00000000000
--- a/tools/sdk/include/asio/asio/ip/resolver_base.hpp
+++ /dev/null
@@ -1,129 +0,0 @@
-//
-// ip/resolver_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_RESOLVER_BASE_HPP
-#define ASIO_IP_RESOLVER_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// The resolver_base class is used as a base for the basic_resolver class
-/// templates to provide a common place to define the flag constants.
-class resolver_base
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// A bitmask type (C++ Std [lib.bitmask.types]).
-  typedef unspecified flags;
-
-  /// Determine the canonical name of the host specified in the query.
-  static const flags canonical_name = implementation_defined;
-
-  /// Indicate that returned endpoint is intended for use as a locally bound
-  /// socket endpoint.
-  static const flags passive = implementation_defined;
-
-  /// Host name should be treated as a numeric string defining an IPv4 or IPv6
-  /// address and no name resolution should be attempted.
-  static const flags numeric_host = implementation_defined;
-
-  /// Service name should be treated as a numeric string defining a port number
-  /// and no name resolution should be attempted.
-  static const flags numeric_service = implementation_defined;
-
-  /// If the query protocol family is specified as IPv6, return IPv4-mapped
-  /// IPv6 addresses on finding no IPv6 addresses.
-  static const flags v4_mapped = implementation_defined;
-
-  /// If used with v4_mapped, return all matching IPv6 and IPv4 addresses.
-  static const flags all_matching = implementation_defined;
-
-  /// Only return IPv4 addresses if a non-loopback IPv4 address is configured
-  /// for the system. Only return IPv6 addresses if a non-loopback IPv6 address
-  /// is configured for the system.
-  static const flags address_configured = implementation_defined;
-#else
-  enum flags
-  {
-    canonical_name = ASIO_OS_DEF(AI_CANONNAME),
-    passive = ASIO_OS_DEF(AI_PASSIVE),
-    numeric_host = ASIO_OS_DEF(AI_NUMERICHOST),
-    numeric_service = ASIO_OS_DEF(AI_NUMERICSERV),
-    v4_mapped = ASIO_OS_DEF(AI_V4MAPPED),
-    all_matching = ASIO_OS_DEF(AI_ALL),
-    address_configured = ASIO_OS_DEF(AI_ADDRCONFIG)
-  };
-
-  // Implement bitmask operations as shown in C++ Std [lib.bitmask.types].
-
-  friend flags operator&(flags x, flags y)
-  {
-    return static_cast<flags>(
-        static_cast<unsigned int>(x) & static_cast<unsigned int>(y));
-  }
-
-  friend flags operator|(flags x, flags y)
-  {
-    return static_cast<flags>(
-        static_cast<unsigned int>(x) | static_cast<unsigned int>(y));
-  }
-
-  friend flags operator^(flags x, flags y)
-  {
-    return static_cast<flags>(
-        static_cast<unsigned int>(x) ^ static_cast<unsigned int>(y));
-  }
-
-  friend flags operator~(flags x)
-  {
-    return static_cast<flags>(~static_cast<unsigned int>(x));
-  }
-
-  friend flags& operator&=(flags& x, flags y)
-  {
-    x = x & y;
-    return x;
-  }
-
-  friend flags& operator|=(flags& x, flags y)
-  {
-    x = x | y;
-    return x;
-  }
-
-  friend flags& operator^=(flags& x, flags y)
-  {
-    x = x ^ y;
-    return x;
-  }
-#endif
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  ~resolver_base()
-  {
-  }
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_RESOLVER_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/ip/resolver_query_base.hpp b/tools/sdk/include/asio/asio/ip/resolver_query_base.hpp
deleted file mode 100644
index be368589ed7..00000000000
--- a/tools/sdk/include/asio/asio/ip/resolver_query_base.hpp
+++ /dev/null
@@ -1,43 +0,0 @@
-//
-// ip/resolver_query_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_RESOLVER_QUERY_BASE_HPP
-#define ASIO_IP_RESOLVER_QUERY_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/ip/resolver_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// The resolver_query_base class is used as a base for the
-/// basic_resolver_query class templates to provide a common place to define
-/// the flag constants.
-class resolver_query_base : public resolver_base
-{
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  ~resolver_query_base()
-  {
-  }
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_RESOLVER_QUERY_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/ip/resolver_service.hpp b/tools/sdk/include/asio/asio/ip/resolver_service.hpp
deleted file mode 100644
index 519d72dbb11..00000000000
--- a/tools/sdk/include/asio/asio/ip/resolver_service.hpp
+++ /dev/null
@@ -1,200 +0,0 @@
-//
-// ip/resolver_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_RESOLVER_SERVICE_HPP
-#define ASIO_IP_RESOLVER_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/async_result.hpp"
-#include "asio/error_code.hpp"
-#include "asio/io_context.hpp"
-#include "asio/ip/basic_resolver_iterator.hpp"
-#include "asio/ip/basic_resolver_query.hpp"
-#include "asio/ip/basic_resolver_results.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/winrt_resolver_service.hpp"
-#else
-# include "asio/detail/resolver_service.hpp"
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Default service implementation for a resolver.
-template <typename InternetProtocol>
-class resolver_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<
-      resolver_service<InternetProtocol> >
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-  /// The protocol type.
-  typedef InternetProtocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename InternetProtocol::endpoint endpoint_type;
-
-  /// The query type.
-  typedef basic_resolver_query<InternetProtocol> query_type;
-
-  /// The iterator type.
-  typedef basic_resolver_iterator<InternetProtocol> iterator_type;
-
-  /// The results type.
-  typedef basic_resolver_results<InternetProtocol> results_type;
-
-private:
-  // The type of the platform-specific implementation.
-#if defined(ASIO_WINDOWS_RUNTIME)
-  typedef asio::detail::winrt_resolver_service<InternetProtocol>
-    service_impl_type;
-#else
-  typedef asio::detail::resolver_service<InternetProtocol>
-    service_impl_type;
-#endif
-
-public:
-  /// The type of a resolver implementation.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef typename service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// Construct a new resolver service for the specified io_context.
-  explicit resolver_service(asio::io_context& io_context)
-    : asio::detail::service_base<
-        resolver_service<InternetProtocol> >(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new resolver implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new resolver implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another resolver implementation.
-  void move_assign(implementation_type& impl,
-      resolver_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a resolver implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Cancel pending asynchronous operations.
-  void cancel(implementation_type& impl)
-  {
-    service_impl_.cancel(impl);
-  }
-
-  /// Resolve a query to a list of entries.
-  results_type resolve(implementation_type& impl, const query_type& query,
-      asio::error_code& ec)
-  {
-    return service_impl_.resolve(impl, query, ec);
-  }
-
-  /// Asynchronously resolve a query to a list of entries.
-  template <typename ResolveHandler>
-  ASIO_INITFN_RESULT_TYPE(ResolveHandler,
-      void (asio::error_code, results_type))
-  async_resolve(implementation_type& impl, const query_type& query,
-      ASIO_MOVE_ARG(ResolveHandler) handler)
-  {
-    asio::async_completion<ResolveHandler,
-      void (asio::error_code, results_type)> init(handler);
-
-    service_impl_.async_resolve(impl, query, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Resolve an endpoint to a list of entries.
-  results_type resolve(implementation_type& impl,
-      const endpoint_type& endpoint, asio::error_code& ec)
-  {
-    return service_impl_.resolve(impl, endpoint, ec);
-  }
-
-  /// Asynchronously resolve an endpoint to a list of entries.
-  template <typename ResolveHandler>
-  ASIO_INITFN_RESULT_TYPE(ResolveHandler,
-      void (asio::error_code, results_type))
-  async_resolve(implementation_type& impl, const endpoint_type& endpoint,
-      ASIO_MOVE_ARG(ResolveHandler) handler)
-  {
-    asio::async_completion<ResolveHandler,
-      void (asio::error_code, results_type)> init(handler);
-
-    service_impl_.async_resolve(impl, endpoint, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // Perform any fork-related housekeeping.
-  void notify_fork(asio::io_context::fork_event event)
-  {
-    service_impl_.notify_fork(event);
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_IP_RESOLVER_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/ip/tcp.hpp b/tools/sdk/include/asio/asio/ip/tcp.hpp
deleted file mode 100644
index f1adeb02c80..00000000000
--- a/tools/sdk/include/asio/asio/ip/tcp.hpp
+++ /dev/null
@@ -1,155 +0,0 @@
-//
-// ip/tcp.hpp
-// ~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_TCP_HPP
-#define ASIO_IP_TCP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/basic_socket_acceptor.hpp"
-#include "asio/basic_socket_iostream.hpp"
-#include "asio/basic_stream_socket.hpp"
-#include "asio/detail/socket_option.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/ip/basic_endpoint.hpp"
-#include "asio/ip/basic_resolver.hpp"
-#include "asio/ip/basic_resolver_iterator.hpp"
-#include "asio/ip/basic_resolver_query.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Encapsulates the flags needed for TCP.
-/**
- * The asio::ip::tcp class contains flags necessary for TCP sockets.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Protocol, InternetProtocol.
- */
-class tcp
-{
-public:
-  /// The type of a TCP endpoint.
-  typedef basic_endpoint<tcp> endpoint;
-
-  /// Construct to represent the IPv4 TCP protocol.
-  static tcp v4()
-  {
-    return tcp(ASIO_OS_DEF(AF_INET));
-  }
-
-  /// Construct to represent the IPv6 TCP protocol.
-  static tcp v6()
-  {
-    return tcp(ASIO_OS_DEF(AF_INET6));
-  }
-
-  /// Obtain an identifier for the type of the protocol.
-  int type() const
-  {
-    return ASIO_OS_DEF(SOCK_STREAM);
-  }
-
-  /// Obtain an identifier for the protocol.
-  int protocol() const
-  {
-    return ASIO_OS_DEF(IPPROTO_TCP);
-  }
-
-  /// Obtain an identifier for the protocol family.
-  int family() const
-  {
-    return family_;
-  }
-
-  /// The TCP socket type.
-  typedef basic_stream_socket<tcp> socket;
-
-  /// The TCP acceptor type.
-  typedef basic_socket_acceptor<tcp> acceptor;
-
-  /// The TCP resolver type.
-  typedef basic_resolver<tcp> resolver;
-
-#if !defined(ASIO_NO_IOSTREAM)
-  /// The TCP iostream type.
-  typedef basic_socket_iostream<tcp> iostream;
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-  /// Socket option for disabling the Nagle algorithm.
-  /**
-   * Implements the IPPROTO_TCP/TCP_NODELAY socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::ip::tcp::no_delay option(true);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::ip::tcp::no_delay option;
-   * socket.get_option(option);
-   * bool is_set = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Boolean_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined no_delay;
-#else
-  typedef asio::detail::socket_option::boolean<
-    ASIO_OS_DEF(IPPROTO_TCP), ASIO_OS_DEF(TCP_NODELAY)> no_delay;
-#endif
-
-  /// Compare two protocols for equality.
-  friend bool operator==(const tcp& p1, const tcp& p2)
-  {
-    return p1.family_ == p2.family_;
-  }
-
-  /// Compare two protocols for inequality.
-  friend bool operator!=(const tcp& p1, const tcp& p2)
-  {
-    return p1.family_ != p2.family_;
-  }
-
-private:
-  // Construct with a specific family.
-  explicit tcp(int protocol_family)
-    : family_(protocol_family)
-  {
-  }
-
-  int family_;
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_TCP_HPP
diff --git a/tools/sdk/include/asio/asio/ip/udp.hpp b/tools/sdk/include/asio/asio/ip/udp.hpp
deleted file mode 100644
index 1c93f9b0a5a..00000000000
--- a/tools/sdk/include/asio/asio/ip/udp.hpp
+++ /dev/null
@@ -1,111 +0,0 @@
-//
-// ip/udp.hpp
-// ~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_UDP_HPP
-#define ASIO_IP_UDP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/basic_datagram_socket.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/ip/basic_endpoint.hpp"
-#include "asio/ip/basic_resolver.hpp"
-#include "asio/ip/basic_resolver_iterator.hpp"
-#include "asio/ip/basic_resolver_query.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Encapsulates the flags needed for UDP.
-/**
- * The asio::ip::udp class contains flags necessary for UDP sockets.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Protocol, InternetProtocol.
- */
-class udp
-{
-public:
-  /// The type of a UDP endpoint.
-  typedef basic_endpoint<udp> endpoint;
-
-  /// Construct to represent the IPv4 UDP protocol.
-  static udp v4()
-  {
-    return udp(ASIO_OS_DEF(AF_INET));
-  }
-
-  /// Construct to represent the IPv6 UDP protocol.
-  static udp v6()
-  {
-    return udp(ASIO_OS_DEF(AF_INET6));
-  }
-
-  /// Obtain an identifier for the type of the protocol.
-  int type() const
-  {
-    return ASIO_OS_DEF(SOCK_DGRAM);
-  }
-
-  /// Obtain an identifier for the protocol.
-  int protocol() const
-  {
-    return ASIO_OS_DEF(IPPROTO_UDP);
-  }
-
-  /// Obtain an identifier for the protocol family.
-  int family() const
-  {
-    return family_;
-  }
-
-  /// The UDP socket type.
-  typedef basic_datagram_socket<udp> socket;
-
-  /// The UDP resolver type.
-  typedef basic_resolver<udp> resolver;
-
-  /// Compare two protocols for equality.
-  friend bool operator==(const udp& p1, const udp& p2)
-  {
-    return p1.family_ == p2.family_;
-  }
-
-  /// Compare two protocols for inequality.
-  friend bool operator!=(const udp& p1, const udp& p2)
-  {
-    return p1.family_ != p2.family_;
-  }
-
-private:
-  // Construct with a specific family.
-  explicit udp(int protocol_family)
-    : family_(protocol_family)
-  {
-  }
-
-  int family_;
-};
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_UDP_HPP
diff --git a/tools/sdk/include/asio/asio/ip/unicast.hpp b/tools/sdk/include/asio/asio/ip/unicast.hpp
deleted file mode 100644
index 14e3e489fd4..00000000000
--- a/tools/sdk/include/asio/asio/ip/unicast.hpp
+++ /dev/null
@@ -1,70 +0,0 @@
-//
-// ip/unicast.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_UNICAST_HPP
-#define ASIO_IP_UNICAST_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/ip/detail/socket_option.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-namespace unicast {
-
-/// Socket option for time-to-live associated with outgoing unicast packets.
-/**
- * Implements the IPPROTO_IP/IP_UNICAST_TTL socket option.
- *
- * @par Examples
- * Setting the option:
- * @code
- * asio::ip::udp::socket socket(io_context); 
- * ...
- * asio::ip::unicast::hops option(4);
- * socket.set_option(option);
- * @endcode
- *
- * @par
- * Getting the current option value:
- * @code
- * asio::ip::udp::socket socket(io_context); 
- * ...
- * asio::ip::unicast::hops option;
- * socket.get_option(option);
- * int ttl = option.value();
- * @endcode
- *
- * @par Concepts:
- * GettableSocketOption, SettableSocketOption.
- */
-#if defined(GENERATING_DOCUMENTATION)
-typedef implementation_defined hops;
-#else
-typedef asio::ip::detail::socket_option::unicast_hops<
-  ASIO_OS_DEF(IPPROTO_IP),
-  ASIO_OS_DEF(IP_TTL),
-  ASIO_OS_DEF(IPPROTO_IPV6),
-  ASIO_OS_DEF(IPV6_UNICAST_HOPS)> hops;
-#endif
-
-} // namespace unicast
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_UNICAST_HPP
diff --git a/tools/sdk/include/asio/asio/ip/v6_only.hpp b/tools/sdk/include/asio/asio/ip/v6_only.hpp
deleted file mode 100644
index ac7234edcba..00000000000
--- a/tools/sdk/include/asio/asio/ip/v6_only.hpp
+++ /dev/null
@@ -1,69 +0,0 @@
-//
-// ip/v6_only.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IP_V6_ONLY_HPP
-#define ASIO_IP_V6_ONLY_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/socket_option.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ip {
-
-/// Socket option for determining whether an IPv6 socket supports IPv6
-/// communication only.
-/**
- * Implements the IPPROTO_IPV6/IP_V6ONLY socket option.
- *
- * @par Examples
- * Setting the option:
- * @code
- * asio::ip::tcp::socket socket(io_context); 
- * ...
- * asio::ip::v6_only option(true);
- * socket.set_option(option);
- * @endcode
- *
- * @par
- * Getting the current option value:
- * @code
- * asio::ip::tcp::socket socket(io_context); 
- * ...
- * asio::ip::v6_only option;
- * socket.get_option(option);
- * bool v6_only = option.value();
- * @endcode
- *
- * @par Concepts:
- * GettableSocketOption, SettableSocketOption.
- */
-#if defined(GENERATING_DOCUMENTATION)
-typedef implementation_defined v6_only;
-#elif defined(IPV6_V6ONLY)
-typedef asio::detail::socket_option::boolean<
-    IPPROTO_IPV6, IPV6_V6ONLY> v6_only;
-#else
-typedef asio::detail::socket_option::boolean<
-    asio::detail::custom_socket_option_level,
-    asio::detail::always_fail_option> v6_only;
-#endif
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IP_V6_ONLY_HPP
diff --git a/tools/sdk/include/asio/asio/is_executor.hpp b/tools/sdk/include/asio/asio/is_executor.hpp
deleted file mode 100644
index a1661ec46b6..00000000000
--- a/tools/sdk/include/asio/asio/is_executor.hpp
+++ /dev/null
@@ -1,46 +0,0 @@
-//
-// is_executor.hpp
-// ~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IS_EXECUTOR_HPP
-#define ASIO_IS_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/is_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// The is_executor trait detects whether a type T meets the Executor type
-/// requirements.
-/**
- * Class template @c is_executor is a UnaryTypeTrait that is derived from @c
- * true_type if the type @c T meets the syntactic requirements for Executor,
- * otherwise @c false_type.
- */
-template <typename T>
-struct is_executor
-#if defined(GENERATING_DOCUMENTATION)
-  : integral_constant<bool, automatically_determined>
-#else // defined(GENERATING_DOCUMENTATION)
-  : asio::detail::is_executor<T>
-#endif // defined(GENERATING_DOCUMENTATION)
-{
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IS_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/is_read_buffered.hpp b/tools/sdk/include/asio/asio/is_read_buffered.hpp
deleted file mode 100644
index c5a67b2da77..00000000000
--- a/tools/sdk/include/asio/asio/is_read_buffered.hpp
+++ /dev/null
@@ -1,59 +0,0 @@
-//
-// is_read_buffered.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IS_READ_BUFFERED_HPP
-#define ASIO_IS_READ_BUFFERED_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/buffered_read_stream_fwd.hpp"
-#include "asio/buffered_stream_fwd.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail {
-
-template <typename Stream>
-char is_read_buffered_helper(buffered_stream<Stream>* s);
-
-template <typename Stream>
-char is_read_buffered_helper(buffered_read_stream<Stream>* s);
-
-struct is_read_buffered_big_type { char data[10]; };
-is_read_buffered_big_type is_read_buffered_helper(...);
-
-} // namespace detail
-
-/// The is_read_buffered class is a traits class that may be used to determine
-/// whether a stream type supports buffering of read data.
-template <typename Stream>
-class is_read_buffered
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The value member is true only if the Stream type supports buffering of
-  /// read data.
-  static const bool value;
-#else
-  ASIO_STATIC_CONSTANT(bool,
-      value = sizeof(detail::is_read_buffered_helper((Stream*)0)) == 1);
-#endif
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IS_READ_BUFFERED_HPP
diff --git a/tools/sdk/include/asio/asio/is_write_buffered.hpp b/tools/sdk/include/asio/asio/is_write_buffered.hpp
deleted file mode 100644
index e237dd6f461..00000000000
--- a/tools/sdk/include/asio/asio/is_write_buffered.hpp
+++ /dev/null
@@ -1,59 +0,0 @@
-//
-// is_write_buffered.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_IS_WRITE_BUFFERED_HPP
-#define ASIO_IS_WRITE_BUFFERED_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/buffered_stream_fwd.hpp"
-#include "asio/buffered_write_stream_fwd.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail {
-
-template <typename Stream>
-char is_write_buffered_helper(buffered_stream<Stream>* s);
-
-template <typename Stream>
-char is_write_buffered_helper(buffered_write_stream<Stream>* s);
-
-struct is_write_buffered_big_type { char data[10]; };
-is_write_buffered_big_type is_write_buffered_helper(...);
-
-} // namespace detail
-
-/// The is_write_buffered class is a traits class that may be used to determine
-/// whether a stream type supports buffering of written data.
-template <typename Stream>
-class is_write_buffered
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The value member is true only if the Stream type supports buffering of
-  /// written data.
-  static const bool value;
-#else
-  ASIO_STATIC_CONSTANT(bool,
-      value = sizeof(detail::is_write_buffered_helper((Stream*)0)) == 1);
-#endif
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_IS_WRITE_BUFFERED_HPP
diff --git a/tools/sdk/include/asio/asio/local/basic_endpoint.hpp b/tools/sdk/include/asio/asio/local/basic_endpoint.hpp
deleted file mode 100644
index 94e470a4b72..00000000000
--- a/tools/sdk/include/asio/asio/local/basic_endpoint.hpp
+++ /dev/null
@@ -1,239 +0,0 @@
-//
-// local/basic_endpoint.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Derived from a public domain implementation written by Daniel Casimiro.
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_LOCAL_BASIC_ENDPOINT_HPP
-#define ASIO_LOCAL_BASIC_ENDPOINT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_LOCAL_SOCKETS) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/local/detail/endpoint.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-# include <iosfwd>
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace local {
-
-/// Describes an endpoint for a UNIX socket.
-/**
- * The asio::local::basic_endpoint class template describes an endpoint
- * that may be associated with a particular UNIX socket.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * Endpoint.
- */
-template <typename Protocol>
-class basic_endpoint
-{
-public:
-  /// The protocol type associated with the endpoint.
-  typedef Protocol protocol_type;
-
-  /// The type of the endpoint structure. This type is dependent on the
-  /// underlying implementation of the socket layer.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined data_type;
-#else
-  typedef asio::detail::socket_addr_type data_type;
-#endif
-
-  /// Default constructor.
-  basic_endpoint()
-  {
-  }
-
-  /// Construct an endpoint using the specified path name.
-  basic_endpoint(const char* path_name)
-    : impl_(path_name)
-  {
-  }
-
-  /// Construct an endpoint using the specified path name.
-  basic_endpoint(const std::string& path_name)
-    : impl_(path_name)
-  {
-  }
-
-  /// Copy constructor.
-  basic_endpoint(const basic_endpoint& other)
-    : impl_(other.impl_)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move constructor.
-  basic_endpoint(basic_endpoint&& other)
-    : impl_(other.impl_)
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Assign from another endpoint.
-  basic_endpoint& operator=(const basic_endpoint& other)
-  {
-    impl_ = other.impl_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Move-assign from another endpoint.
-  basic_endpoint& operator=(basic_endpoint&& other)
-  {
-    impl_ = other.impl_;
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// The protocol associated with the endpoint.
-  protocol_type protocol() const
-  {
-    return protocol_type();
-  }
-
-  /// Get the underlying endpoint in the native type.
-  data_type* data()
-  {
-    return impl_.data();
-  }
-
-  /// Get the underlying endpoint in the native type.
-  const data_type* data() const
-  {
-    return impl_.data();
-  }
-
-  /// Get the underlying size of the endpoint in the native type.
-  std::size_t size() const
-  {
-    return impl_.size();
-  }
-
-  /// Set the underlying size of the endpoint in the native type.
-  void resize(std::size_t new_size)
-  {
-    impl_.resize(new_size);
-  }
-
-  /// Get the capacity of the endpoint in the native type.
-  std::size_t capacity() const
-  {
-    return impl_.capacity();
-  }
-
-  /// Get the path associated with the endpoint.
-  std::string path() const
-  {
-    return impl_.path();
-  }
-
-  /// Set the path associated with the endpoint.
-  void path(const char* p)
-  {
-    impl_.path(p);
-  }
-
-  /// Set the path associated with the endpoint.
-  void path(const std::string& p)
-  {
-    impl_.path(p);
-  }
-
-  /// Compare two endpoints for equality.
-  friend bool operator==(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return e1.impl_ == e2.impl_;
-  }
-
-  /// Compare two endpoints for inequality.
-  friend bool operator!=(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return !(e1.impl_ == e2.impl_);
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator<(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return e1.impl_ < e2.impl_;
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator>(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return e2.impl_ < e1.impl_;
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator<=(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return !(e2 < e1);
-  }
-
-  /// Compare endpoints for ordering.
-  friend bool operator>=(const basic_endpoint<Protocol>& e1,
-      const basic_endpoint<Protocol>& e2)
-  {
-    return !(e1 < e2);
-  }
-
-private:
-  // The underlying UNIX domain endpoint.
-  asio::local::detail::endpoint impl_;
-};
-
-/// Output an endpoint as a string.
-/**
- * Used to output a human-readable string for a specified endpoint.
- *
- * @param os The output stream to which the string will be written.
- *
- * @param endpoint The endpoint to be written.
- *
- * @return The output stream.
- *
- * @relates asio::local::basic_endpoint
- */
-template <typename Elem, typename Traits, typename Protocol>
-std::basic_ostream<Elem, Traits>& operator<<(
-    std::basic_ostream<Elem, Traits>& os,
-    const basic_endpoint<Protocol>& endpoint)
-{
-  os << endpoint.path();
-  return os;
-}
-
-} // namespace local
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_LOCAL_SOCKETS)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_LOCAL_BASIC_ENDPOINT_HPP
diff --git a/tools/sdk/include/asio/asio/local/connect_pair.hpp b/tools/sdk/include/asio/asio/local/connect_pair.hpp
deleted file mode 100644
index 2f7c090edb1..00000000000
--- a/tools/sdk/include/asio/asio/local/connect_pair.hpp
+++ /dev/null
@@ -1,106 +0,0 @@
-//
-// local/connect_pair.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_LOCAL_CONNECT_PAIR_HPP
-#define ASIO_LOCAL_CONNECT_PAIR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_LOCAL_SOCKETS) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/basic_socket.hpp"
-#include "asio/detail/socket_ops.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/local/basic_endpoint.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace local {
-
-/// Create a pair of connected sockets.
-template <typename Protocol ASIO_SVC_TPARAM ASIO_SVC_TPARAM1>
-void connect_pair(
-    basic_socket<Protocol ASIO_SVC_TARG>& socket1,
-    basic_socket<Protocol ASIO_SVC_TARG1>& socket2);
-
-/// Create a pair of connected sockets.
-template <typename Protocol ASIO_SVC_TPARAM ASIO_SVC_TPARAM1>
-ASIO_SYNC_OP_VOID connect_pair(
-    basic_socket<Protocol ASIO_SVC_TARG>& socket1,
-    basic_socket<Protocol ASIO_SVC_TARG1>& socket2,
-    asio::error_code& ec);
-
-template <typename Protocol ASIO_SVC_TPARAM ASIO_SVC_TPARAM1>
-inline void connect_pair(
-    basic_socket<Protocol ASIO_SVC_TARG>& socket1,
-    basic_socket<Protocol ASIO_SVC_TARG1>& socket2)
-{
-  asio::error_code ec;
-  connect_pair(socket1, socket2, ec);
-  asio::detail::throw_error(ec, "connect_pair");
-}
-
-template <typename Protocol ASIO_SVC_TPARAM ASIO_SVC_TPARAM1>
-inline ASIO_SYNC_OP_VOID connect_pair(
-    basic_socket<Protocol ASIO_SVC_TARG>& socket1,
-    basic_socket<Protocol ASIO_SVC_TARG1>& socket2,
-    asio::error_code& ec)
-{
-  // Check that this function is only being used with a UNIX domain socket.
-  asio::local::basic_endpoint<Protocol>* tmp
-    = static_cast<typename Protocol::endpoint*>(0);
-  (void)tmp;
-
-  Protocol protocol;
-  asio::detail::socket_type sv[2];
-  if (asio::detail::socket_ops::socketpair(protocol.family(),
-        protocol.type(), protocol.protocol(), sv, ec)
-      == asio::detail::socket_error_retval)
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-
-  socket1.assign(protocol, sv[0], ec);
-  if (ec)
-  {
-    asio::error_code temp_ec;
-    asio::detail::socket_ops::state_type state[2] = { 0, 0 };
-    asio::detail::socket_ops::close(sv[0], state[0], true, temp_ec);
-    asio::detail::socket_ops::close(sv[1], state[1], true, temp_ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  socket2.assign(protocol, sv[1], ec);
-  if (ec)
-  {
-    asio::error_code temp_ec;
-    socket1.close(temp_ec);
-    asio::detail::socket_ops::state_type state = 0;
-    asio::detail::socket_ops::close(sv[1], state, true, temp_ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  ASIO_SYNC_OP_VOID_RETURN(ec);
-}
-
-} // namespace local
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_LOCAL_SOCKETS)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_LOCAL_CONNECT_PAIR_HPP
diff --git a/tools/sdk/include/asio/asio/local/datagram_protocol.hpp b/tools/sdk/include/asio/asio/local/datagram_protocol.hpp
deleted file mode 100644
index b87df2e5643..00000000000
--- a/tools/sdk/include/asio/asio/local/datagram_protocol.hpp
+++ /dev/null
@@ -1,80 +0,0 @@
-//
-// local/datagram_protocol.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_LOCAL_DATAGRAM_PROTOCOL_HPP
-#define ASIO_LOCAL_DATAGRAM_PROTOCOL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_LOCAL_SOCKETS) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/basic_datagram_socket.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/local/basic_endpoint.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace local {
-
-/// Encapsulates the flags needed for datagram-oriented UNIX sockets.
-/**
- * The asio::local::datagram_protocol class contains flags necessary for
- * datagram-oriented UNIX domain sockets.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Protocol.
- */
-class datagram_protocol
-{
-public:
-  /// Obtain an identifier for the type of the protocol.
-  int type() const
-  {
-    return SOCK_DGRAM;
-  }
-
-  /// Obtain an identifier for the protocol.
-  int protocol() const
-  {
-    return 0;
-  }
-
-  /// Obtain an identifier for the protocol family.
-  int family() const
-  {
-    return AF_UNIX;
-  }
-
-  /// The type of a UNIX domain endpoint.
-  typedef basic_endpoint<datagram_protocol> endpoint;
-
-  /// The UNIX domain socket type.
-  typedef basic_datagram_socket<datagram_protocol> socket;
-};
-
-} // namespace local
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_LOCAL_SOCKETS)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_LOCAL_DATAGRAM_PROTOCOL_HPP
diff --git a/tools/sdk/include/asio/asio/local/detail/endpoint.hpp b/tools/sdk/include/asio/asio/local/detail/endpoint.hpp
deleted file mode 100644
index 4870f3b9aa7..00000000000
--- a/tools/sdk/include/asio/asio/local/detail/endpoint.hpp
+++ /dev/null
@@ -1,133 +0,0 @@
-//
-// local/detail/endpoint.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Derived from a public domain implementation written by Daniel Casimiro.
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_LOCAL_DETAIL_ENDPOINT_HPP
-#define ASIO_LOCAL_DETAIL_ENDPOINT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_LOCAL_SOCKETS)
-
-#include <cstddef>
-#include <string>
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace local {
-namespace detail {
-
-// Helper class for implementing a UNIX domain endpoint.
-class endpoint
-{
-public:
-  // Default constructor.
-  ASIO_DECL endpoint();
-
-  // Construct an endpoint using the specified path name.
-  ASIO_DECL endpoint(const char* path_name);
-
-  // Construct an endpoint using the specified path name.
-  ASIO_DECL endpoint(const std::string& path_name);
-
-  // Copy constructor.
-  endpoint(const endpoint& other)
-    : data_(other.data_),
-      path_length_(other.path_length_)
-  {
-  }
-
-  // Assign from another endpoint.
-  endpoint& operator=(const endpoint& other)
-  {
-    data_ = other.data_;
-    path_length_ = other.path_length_;
-    return *this;
-  }
-
-  // Get the underlying endpoint in the native type.
-  asio::detail::socket_addr_type* data()
-  {
-    return &data_.base;
-  }
-
-  // Get the underlying endpoint in the native type.
-  const asio::detail::socket_addr_type* data() const
-  {
-    return &data_.base;
-  }
-
-  // Get the underlying size of the endpoint in the native type.
-  std::size_t size() const
-  {
-    return path_length_
-      + offsetof(asio::detail::sockaddr_un_type, sun_path);
-  }
-
-  // Set the underlying size of the endpoint in the native type.
-  ASIO_DECL void resize(std::size_t size);
-
-  // Get the capacity of the endpoint in the native type.
-  std::size_t capacity() const
-  {
-    return sizeof(asio::detail::sockaddr_un_type);
-  }
-
-  // Get the path associated with the endpoint.
-  ASIO_DECL std::string path() const;
-
-  // Set the path associated with the endpoint.
-  ASIO_DECL void path(const char* p);
-
-  // Set the path associated with the endpoint.
-  ASIO_DECL void path(const std::string& p);
-
-  // Compare two endpoints for equality.
-  ASIO_DECL friend bool operator==(
-      const endpoint& e1, const endpoint& e2);
-
-  // Compare endpoints for ordering.
-  ASIO_DECL friend bool operator<(
-      const endpoint& e1, const endpoint& e2);
-
-private:
-  // The underlying UNIX socket address.
-  union data_union
-  {
-    asio::detail::socket_addr_type base;
-    asio::detail::sockaddr_un_type local;
-  } data_;
-
-  // The length of the path associated with the endpoint.
-  std::size_t path_length_;
-
-  // Initialise with a specified path.
-  ASIO_DECL void init(const char* path, std::size_t path_length);
-};
-
-} // namespace detail
-} // namespace local
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/local/detail/impl/endpoint.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_LOCAL_SOCKETS)
-
-#endif // ASIO_LOCAL_DETAIL_ENDPOINT_HPP
diff --git a/tools/sdk/include/asio/asio/local/stream_protocol.hpp b/tools/sdk/include/asio/asio/local/stream_protocol.hpp
deleted file mode 100644
index e2ef5f3b95f..00000000000
--- a/tools/sdk/include/asio/asio/local/stream_protocol.hpp
+++ /dev/null
@@ -1,90 +0,0 @@
-//
-// local/stream_protocol.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_LOCAL_STREAM_PROTOCOL_HPP
-#define ASIO_LOCAL_STREAM_PROTOCOL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_LOCAL_SOCKETS) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/basic_socket_acceptor.hpp"
-#include "asio/basic_socket_iostream.hpp"
-#include "asio/basic_stream_socket.hpp"
-#include "asio/detail/socket_types.hpp"
-#include "asio/local/basic_endpoint.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace local {
-
-/// Encapsulates the flags needed for stream-oriented UNIX sockets.
-/**
- * The asio::local::stream_protocol class contains flags necessary for
- * stream-oriented UNIX domain sockets.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Safe.
- *
- * @par Concepts:
- * Protocol.
- */
-class stream_protocol
-{
-public:
-  /// Obtain an identifier for the type of the protocol.
-  int type() const
-  {
-    return SOCK_STREAM;
-  }
-
-  /// Obtain an identifier for the protocol.
-  int protocol() const
-  {
-    return 0;
-  }
-
-  /// Obtain an identifier for the protocol family.
-  int family() const
-  {
-    return AF_UNIX;
-  }
-
-  /// The type of a UNIX domain endpoint.
-  typedef basic_endpoint<stream_protocol> endpoint;
-
-  /// The UNIX domain socket type.
-  typedef basic_stream_socket<stream_protocol> socket;
-
-  /// The UNIX domain acceptor type.
-  typedef basic_socket_acceptor<stream_protocol> acceptor;
-
-#if !defined(ASIO_NO_IOSTREAM)
-  /// The UNIX domain iostream type.
-  typedef basic_socket_iostream<stream_protocol> iostream;
-#endif // !defined(ASIO_NO_IOSTREAM)
-};
-
-} // namespace local
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_LOCAL_SOCKETS)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_LOCAL_STREAM_PROTOCOL_HPP
diff --git a/tools/sdk/include/asio/asio/packaged_task.hpp b/tools/sdk/include/asio/asio/packaged_task.hpp
deleted file mode 100644
index 1e20b42e4d2..00000000000
--- a/tools/sdk/include/asio/asio/packaged_task.hpp
+++ /dev/null
@@ -1,126 +0,0 @@
-//
-// packaged_task.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_PACKAGED_TASK_HPP
-#define ASIO_PACKAGED_TASK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_FUTURE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <future>
-#include "asio/async_result.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/detail/variadic_templates.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-#if defined(ASIO_HAS_VARIADIC_TEMPLATES) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Partial specialisation of @c async_result for @c std::packaged_task.
-template <typename Result, typename... Args, typename Signature>
-class async_result<std::packaged_task<Result(Args...)>, Signature>
-{
-public:
-  /// The packaged task is the concrete completion handler type.
-  typedef std::packaged_task<Result(Args...)> completion_handler_type;
-
-  /// The return type of the initiating function is the future obtained from
-  /// the packaged task.
-  typedef std::future<Result> return_type;
-
-  /// The constructor extracts the future from the packaged task.
-  explicit async_result(completion_handler_type& h)
-    : future_(h.get_future())
-  {
-  }
-
-  /// Returns the packaged task's future.
-  return_type get()
-  {
-    return std::move(future_);
-  }
-
-private:
-  return_type future_;
-};
-
-#else // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-      //   || defined(GENERATING_DOCUMENTATION)
-
-template <typename Result, typename Signature>
-struct async_result<std::packaged_task<Result()>, Signature>
-{
-  typedef std::packaged_task<Result()> completion_handler_type;
-  typedef std::future<Result> return_type;
-
-  explicit async_result(completion_handler_type& h)
-    : future_(h.get_future())
-  {
-  }
-
-  return_type get()
-  {
-    return std::move(future_);
-  }
-
-private:
-  return_type future_;
-};
-
-#define ASIO_PRIVATE_ASYNC_RESULT_DEF(n) \
-  template <typename Result, \
-    ASIO_VARIADIC_TPARAMS(n), typename Signature> \
-  class async_result< \
-    std::packaged_task<Result(ASIO_VARIADIC_TARGS(n))>, Signature> \
-  { \
-  public: \
-    typedef std::packaged_task< \
-      Result(ASIO_VARIADIC_TARGS(n))> \
-        completion_handler_type; \
-  \
-    typedef std::future<Result> return_type; \
-  \
-    explicit async_result(completion_handler_type& h) \
-      : future_(h.get_future()) \
-    { \
-    } \
-  \
-    return_type get() \
-    { \
-      return std::move(future_); \
-    } \
-  \
-  private: \
-    return_type future_; \
-  }; \
-  /**/
-  ASIO_VARIADIC_GENERATE(ASIO_PRIVATE_ASYNC_RESULT_DEF)
-#undef ASIO_PRIVATE_ASYNC_RESULT_DEF
-
-#endif // defined(ASIO_HAS_VARIADIC_TEMPLATES)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_STD_FUTURE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_PACKAGED_TASK_HPP
diff --git a/tools/sdk/include/asio/asio/placeholders.hpp b/tools/sdk/include/asio/asio/placeholders.hpp
deleted file mode 100644
index e71a21e7f10..00000000000
--- a/tools/sdk/include/asio/asio/placeholders.hpp
+++ /dev/null
@@ -1,151 +0,0 @@
-//
-// placeholders.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_PLACEHOLDERS_HPP
-#define ASIO_PLACEHOLDERS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_BOOST_BIND)
-# include <boost/bind/arg.hpp>
-#endif // defined(ASIO_HAS_BOOST_BIND)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace placeholders {
-
-#if defined(GENERATING_DOCUMENTATION)
-
-/// An argument placeholder, for use with boost::bind(), that corresponds to
-/// the error argument of a handler for any of the asynchronous functions.
-unspecified error;
-
-/// An argument placeholder, for use with boost::bind(), that corresponds to
-/// the bytes_transferred argument of a handler for asynchronous functions such
-/// as asio::basic_stream_socket::async_write_some or
-/// asio::async_write.
-unspecified bytes_transferred;
-
-/// An argument placeholder, for use with boost::bind(), that corresponds to
-/// the iterator argument of a handler for asynchronous functions such as
-/// asio::async_connect.
-unspecified iterator;
-
-/// An argument placeholder, for use with boost::bind(), that corresponds to
-/// the results argument of a handler for asynchronous functions such as
-/// asio::basic_resolver::async_resolve.
-unspecified results;
-
-/// An argument placeholder, for use with boost::bind(), that corresponds to
-/// the results argument of a handler for asynchronous functions such as
-/// asio::async_connect.
-unspecified endpoint;
-
-/// An argument placeholder, for use with boost::bind(), that corresponds to
-/// the signal_number argument of a handler for asynchronous functions such as
-/// asio::signal_set::async_wait.
-unspecified signal_number;
-
-#elif defined(ASIO_HAS_BOOST_BIND)
-# if defined(__BORLANDC__) || defined(__GNUC__)
-
-inline boost::arg<1> error()
-{
-  return boost::arg<1>();
-}
-
-inline boost::arg<2> bytes_transferred()
-{
-  return boost::arg<2>();
-}
-
-inline boost::arg<2> iterator()
-{
-  return boost::arg<2>();
-}
-
-inline boost::arg<2> results()
-{
-  return boost::arg<2>();
-}
-
-inline boost::arg<2> endpoint()
-{
-  return boost::arg<2>();
-}
-
-inline boost::arg<2> signal_number()
-{
-  return boost::arg<2>();
-}
-
-# else
-
-namespace detail
-{
-  template <int Number>
-  struct placeholder
-  {
-    static boost::arg<Number>& get()
-    {
-      static boost::arg<Number> result;
-      return result;
-    }
-  };
-}
-
-#  if defined(ASIO_MSVC) && (ASIO_MSVC < 1400)
-
-static boost::arg<1>& error
-  = asio::placeholders::detail::placeholder<1>::get();
-static boost::arg<2>& bytes_transferred
-  = asio::placeholders::detail::placeholder<2>::get();
-static boost::arg<2>& iterator
-  = asio::placeholders::detail::placeholder<2>::get();
-static boost::arg<2>& results
-  = asio::placeholders::detail::placeholder<2>::get();
-static boost::arg<2>& endpoint
-  = asio::placeholders::detail::placeholder<2>::get();
-static boost::arg<2>& signal_number
-  = asio::placeholders::detail::placeholder<2>::get();
-
-#  else
-
-namespace
-{
-  boost::arg<1>& error
-    = asio::placeholders::detail::placeholder<1>::get();
-  boost::arg<2>& bytes_transferred
-    = asio::placeholders::detail::placeholder<2>::get();
-  boost::arg<2>& iterator
-    = asio::placeholders::detail::placeholder<2>::get();
-  boost::arg<2>& results
-    = asio::placeholders::detail::placeholder<2>::get();
-  boost::arg<2>& endpoint
-    = asio::placeholders::detail::placeholder<2>::get();
-  boost::arg<2>& signal_number
-    = asio::placeholders::detail::placeholder<2>::get();
-} // namespace
-
-#  endif
-# endif
-#endif
-
-} // namespace placeholders
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_PLACEHOLDERS_HPP
diff --git a/tools/sdk/include/asio/asio/posix/basic_descriptor.hpp b/tools/sdk/include/asio/asio/posix/basic_descriptor.hpp
deleted file mode 100644
index c15da632c95..00000000000
--- a/tools/sdk/include/asio/asio/posix/basic_descriptor.hpp
+++ /dev/null
@@ -1,582 +0,0 @@
-//
-// posix/basic_descriptor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_POSIX_BASIC_DESCRIPTOR_HPP
-#define ASIO_POSIX_BASIC_DESCRIPTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/posix/descriptor_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace posix {
-
-/// Provides POSIX descriptor functionality.
-/**
- * The posix::basic_descriptor class template provides the ability to wrap a
- * POSIX descriptor.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename DescriptorService>
-class basic_descriptor
-  : public basic_io_object<DescriptorService>,
-    public descriptor_base
-{
-public:
-  /// The native representation of a descriptor.
-  typedef typename DescriptorService::native_handle_type native_handle_type;
-
-  /// A basic_descriptor is always the lowest layer.
-  typedef basic_descriptor<DescriptorService> lowest_layer_type;
-
-  /// Construct a basic_descriptor without opening it.
-  /**
-   * This constructor creates a descriptor without opening it.
-   *
-   * @param io_context The io_context object that the descriptor will use to
-   * dispatch handlers for any asynchronous operations performed on the
-   * descriptor.
-   */
-  explicit basic_descriptor(asio::io_context& io_context)
-    : basic_io_object<DescriptorService>(io_context)
-  {
-  }
-
-  /// Construct a basic_descriptor on an existing native descriptor.
-  /**
-   * This constructor creates a descriptor object to hold an existing native
-   * descriptor.
-   *
-   * @param io_context The io_context object that the descriptor will use to
-   * dispatch handlers for any asynchronous operations performed on the
-   * descriptor.
-   *
-   * @param native_descriptor A native descriptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_descriptor(asio::io_context& io_context,
-      const native_handle_type& native_descriptor)
-    : basic_io_object<DescriptorService>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        native_descriptor, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_descriptor from another.
-  /**
-   * This constructor moves a descriptor from one object to another.
-   *
-   * @param other The other basic_descriptor object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_descriptor(io_context&) constructor.
-   */
-  basic_descriptor(basic_descriptor&& other)
-    : basic_io_object<DescriptorService>(
-        ASIO_MOVE_CAST(basic_descriptor)(other))
-  {
-  }
-
-  /// Move-assign a basic_descriptor from another.
-  /**
-   * This assignment operator moves a descriptor from one object to another.
-   *
-   * @param other The other basic_descriptor object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_descriptor(io_context&) constructor.
-   */
-  basic_descriptor& operator=(basic_descriptor&& other)
-  {
-    basic_io_object<DescriptorService>::operator=(
-        ASIO_MOVE_CAST(basic_descriptor)(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * layers. Since a basic_descriptor cannot contain any further layers, it
-   * simply returns a reference to itself.
-   *
-   * @return A reference to the lowest layer in the stack of layers. Ownership
-   * is not transferred to the caller.
-   */
-  lowest_layer_type& lowest_layer()
-  {
-    return *this;
-  }
-
-  /// Get a const reference to the lowest layer.
-  /**
-   * This function returns a const reference to the lowest layer in a stack of
-   * layers. Since a basic_descriptor cannot contain any further layers, it
-   * simply returns a reference to itself.
-   *
-   * @return A const reference to the lowest layer in the stack of layers.
-   * Ownership is not transferred to the caller.
-   */
-  const lowest_layer_type& lowest_layer() const
-  {
-    return *this;
-  }
-
-  /// Assign an existing native descriptor to the descriptor.
-  /*
-   * This function opens the descriptor to hold an existing native descriptor.
-   *
-   * @param native_descriptor A native descriptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void assign(const native_handle_type& native_descriptor)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        native_descriptor, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-  /// Assign an existing native descriptor to the descriptor.
-  /*
-   * This function opens the descriptor to hold an existing native descriptor.
-   *
-   * @param native_descriptor A native descriptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID assign(const native_handle_type& native_descriptor,
-      asio::error_code& ec)
-  {
-    this->get_service().assign(
-        this->get_implementation(), native_descriptor, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the descriptor is open.
-  bool is_open() const
-  {
-    return this->get_service().is_open(this->get_implementation());
-  }
-
-  /// Close the descriptor.
-  /**
-   * This function is used to close the descriptor. Any asynchronous read or
-   * write operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure. Note that, even if
-   * the function indicates an error, the underlying descriptor is closed.
-   */
-  void close()
-  {
-    asio::error_code ec;
-    this->get_service().close(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "close");
-  }
-
-  /// Close the descriptor.
-  /**
-   * This function is used to close the descriptor. Any asynchronous read or
-   * write operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any. Note that, even if
-   * the function indicates an error, the underlying descriptor is closed.
-   */
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    this->get_service().close(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native descriptor representation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * descriptor. This is intended to allow access to native descriptor
-   * functionality that is not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return this->get_service().native_handle(this->get_implementation());
-  }
-
-  /// Release ownership of the native descriptor implementation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * descriptor. After calling this function, @c is_open() returns false. The
-   * caller is responsible for closing the descriptor.
-   *
-   * All outstanding asynchronous read or write operations will finish
-   * immediately, and the handlers for cancelled operations will be passed the
-   * asio::error::operation_aborted error.
-   */
-  native_handle_type release()
-  {
-    return this->get_service().release(this->get_implementation());
-  }
-
-  /// Cancel all asynchronous operations associated with the descriptor.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all asynchronous operations associated with the descriptor.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the descriptor.
-  /**
-   * This function is used to execute an IO control command on the descriptor.
-   *
-   * @param command The IO control command to be performed on the descriptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa IoControlCommand @n
-   * asio::posix::descriptor_base::bytes_readable @n
-   * asio::posix::descriptor_base::non_blocking_io
-   *
-   * @par Example
-   * Getting the number of bytes ready to read:
-   * @code
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * asio::posix::stream_descriptor::bytes_readable command;
-   * descriptor.io_control(command);
-   * std::size_t bytes_readable = command.get();
-   * @endcode
-   */
-  template <typename IoControlCommand>
-  void io_control(IoControlCommand& command)
-  {
-    asio::error_code ec;
-    this->get_service().io_control(this->get_implementation(), command, ec);
-    asio::detail::throw_error(ec, "io_control");
-  }
-
-  /// Perform an IO control command on the descriptor.
-  /**
-   * This function is used to execute an IO control command on the descriptor.
-   *
-   * @param command The IO control command to be performed on the descriptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa IoControlCommand @n
-   * asio::posix::descriptor_base::bytes_readable @n
-   * asio::posix::descriptor_base::non_blocking_io
-   *
-   * @par Example
-   * Getting the number of bytes ready to read:
-   * @code
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * asio::posix::stream_descriptor::bytes_readable command;
-   * asio::error_code ec;
-   * descriptor.io_control(command, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * std::size_t bytes_readable = command.get();
-   * @endcode
-   */
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(IoControlCommand& command,
-      asio::error_code& ec)
-  {
-    this->get_service().io_control(this->get_implementation(), command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the descriptor.
-  /**
-   * @returns @c true if the descriptor's synchronous operations will fail with
-   * asio::error::would_block if they are unable to perform the requested
-   * operation immediately. If @c false, synchronous operations will block
-   * until complete.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  bool non_blocking() const
-  {
-    return this->get_service().non_blocking(this->get_implementation());
-  }
-
-  /// Sets the non-blocking mode of the descriptor.
-  /**
-   * @param mode If @c true, the descriptor's synchronous operations will fail
-   * with asio::error::would_block if they are unable to perform the
-   * requested operation immediately. If @c false, synchronous operations will
-   * block until complete.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  void non_blocking(bool mode)
-  {
-    asio::error_code ec;
-    this->get_service().non_blocking(this->get_implementation(), mode, ec);
-    asio::detail::throw_error(ec, "non_blocking");
-  }
-
-  /// Sets the non-blocking mode of the descriptor.
-  /**
-   * @param mode If @c true, the descriptor's synchronous operations will fail
-   * with asio::error::would_block if they are unable to perform the
-   * requested operation immediately. If @c false, synchronous operations will
-   * block until complete.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  ASIO_SYNC_OP_VOID non_blocking(
-      bool mode, asio::error_code& ec)
-  {
-    this->get_service().non_blocking(this->get_implementation(), mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native descriptor implementation.
-  /**
-   * This function is used to retrieve the non-blocking mode of the underlying
-   * native descriptor. This mode has no effect on the behaviour of the
-   * descriptor object's synchronous operations.
-   *
-   * @returns @c true if the underlying descriptor is in non-blocking mode and
-   * direct system calls may fail with asio::error::would_block (or the
-   * equivalent system error).
-   *
-   * @note The current non-blocking mode is cached by the descriptor object.
-   * Consequently, the return value may be incorrect if the non-blocking mode
-   * was set directly on the native descriptor.
-   */
-  bool native_non_blocking() const
-  {
-    return this->get_service().native_non_blocking(
-        this->get_implementation());
-  }
-
-  /// Sets the non-blocking mode of the native descriptor implementation.
-  /**
-   * This function is used to modify the non-blocking mode of the underlying
-   * native descriptor. It has no effect on the behaviour of the descriptor
-   * object's synchronous operations.
-   *
-   * @param mode If @c true, the underlying descriptor is put into non-blocking
-   * mode and direct system calls may fail with asio::error::would_block
-   * (or the equivalent system error).
-   *
-   * @throws asio::system_error Thrown on failure. If the @c mode is
-   * @c false, but the current value of @c non_blocking() is @c true, this
-   * function fails with asio::error::invalid_argument, as the
-   * combination does not make sense.
-   */
-  void native_non_blocking(bool mode)
-  {
-    asio::error_code ec;
-    this->get_service().native_non_blocking(
-        this->get_implementation(), mode, ec);
-    asio::detail::throw_error(ec, "native_non_blocking");
-  }
-
-  /// Sets the non-blocking mode of the native descriptor implementation.
-  /**
-   * This function is used to modify the non-blocking mode of the underlying
-   * native descriptor. It has no effect on the behaviour of the descriptor
-   * object's synchronous operations.
-   *
-   * @param mode If @c true, the underlying descriptor is put into non-blocking
-   * mode and direct system calls may fail with asio::error::would_block
-   * (or the equivalent system error).
-   *
-   * @param ec Set to indicate what error occurred, if any. If the @c mode is
-   * @c false, but the current value of @c non_blocking() is @c true, this
-   * function fails with asio::error::invalid_argument, as the
-   * combination does not make sense.
-   */
-  ASIO_SYNC_OP_VOID native_non_blocking(
-      bool mode, asio::error_code& ec)
-  {
-    this->get_service().native_non_blocking(
-        this->get_implementation(), mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Wait for the descriptor to become ready to read, ready to write, or to
-  /// have pending error conditions.
-  /**
-   * This function is used to perform a blocking wait for a descriptor to enter
-   * a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired descriptor state.
-   *
-   * @par Example
-   * Waiting for a descriptor to become readable.
-   * @code
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * descriptor.wait(asio::posix::stream_descriptor::wait_read);
-   * @endcode
-   */
-  void wait(wait_type w)
-  {
-    asio::error_code ec;
-    this->get_service().wait(this->get_implementation(), w, ec);
-    asio::detail::throw_error(ec, "wait");
-  }
-
-  /// Wait for the descriptor to become ready to read, ready to write, or to
-  /// have pending error conditions.
-  /**
-   * This function is used to perform a blocking wait for a descriptor to enter
-   * a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired descriptor state.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * Waiting for a descriptor to become readable.
-   * @code
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * asio::error_code ec;
-   * descriptor.wait(asio::posix::stream_descriptor::wait_read, ec);
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID wait(wait_type w, asio::error_code& ec)
-  {
-    this->get_service().wait(this->get_implementation(), w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the descriptor to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  /**
-   * This function is used to perform an asynchronous wait for a descriptor to
-   * enter a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired descriptor state.
-   *
-   * @param handler The handler to be called when the wait operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void wait_handler(const asio::error_code& error)
-   * {
-   *   if (!error)
-   *   {
-   *     // Wait succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * descriptor.async_wait(
-   *     asio::posix::stream_descriptor::wait_read,
-   *     wait_handler);
-   * @endcode
-   */
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(wait_type w, ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WaitHandler.
-    ASIO_WAIT_HANDLER_CHECK(WaitHandler, handler) type_check;
-
-    return this->get_service().async_wait(this->get_implementation(),
-        w, ASIO_MOVE_CAST(WaitHandler)(handler));
-  }
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  ~basic_descriptor()
-  {
-  }
-};
-
-} // namespace posix
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_POSIX_BASIC_DESCRIPTOR_HPP
diff --git a/tools/sdk/include/asio/asio/posix/basic_stream_descriptor.hpp b/tools/sdk/include/asio/asio/posix/basic_stream_descriptor.hpp
deleted file mode 100644
index acd5cb6ae18..00000000000
--- a/tools/sdk/include/asio/asio/posix/basic_stream_descriptor.hpp
+++ /dev/null
@@ -1,362 +0,0 @@
-//
-// posix/basic_stream_descriptor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_POSIX_BASIC_STREAM_DESCRIPTOR_HPP
-#define ASIO_POSIX_BASIC_STREAM_DESCRIPTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/posix/basic_descriptor.hpp"
-#include "asio/posix/stream_descriptor_service.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace posix {
-
-/// Provides stream-oriented descriptor functionality.
-/**
- * The posix::basic_stream_descriptor class template provides asynchronous and
- * blocking stream-oriented descriptor functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * AsyncReadStream, AsyncWriteStream, Stream, SyncReadStream, SyncWriteStream.
- */
-template <typename StreamDescriptorService = stream_descriptor_service>
-class basic_stream_descriptor
-  : public basic_descriptor<StreamDescriptorService>
-{
-public:
-  /// The native representation of a descriptor.
-  typedef typename StreamDescriptorService::native_handle_type
-    native_handle_type;
-
-  /// Construct a basic_stream_descriptor without opening it.
-  /**
-   * This constructor creates a stream descriptor without opening it. The
-   * descriptor needs to be opened and then connected or accepted before data
-   * can be sent or received on it.
-   *
-   * @param io_context The io_context object that the stream descriptor will
-   * use to dispatch handlers for any asynchronous operations performed on the
-   * descriptor.
-   */
-  explicit basic_stream_descriptor(asio::io_context& io_context)
-    : basic_descriptor<StreamDescriptorService>(io_context)
-  {
-  }
-
-  /// Construct a basic_stream_descriptor on an existing native descriptor.
-  /**
-   * This constructor creates a stream descriptor object to hold an existing
-   * native descriptor.
-   *
-   * @param io_context The io_context object that the stream descriptor will
-   * use to dispatch handlers for any asynchronous operations performed on the
-   * descriptor.
-   *
-   * @param native_descriptor The new underlying descriptor implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_stream_descriptor(asio::io_context& io_context,
-      const native_handle_type& native_descriptor)
-    : basic_descriptor<StreamDescriptorService>(io_context, native_descriptor)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_stream_descriptor from another.
-  /**
-   * This constructor moves a stream descriptor from one object to another.
-   *
-   * @param other The other basic_stream_descriptor object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_stream_descriptor(io_context&) constructor.
-   */
-  basic_stream_descriptor(basic_stream_descriptor&& other)
-    : basic_descriptor<StreamDescriptorService>(
-        ASIO_MOVE_CAST(basic_stream_descriptor)(other))
-  {
-  }
-
-  /// Move-assign a basic_stream_descriptor from another.
-  /**
-   * This assignment operator moves a stream descriptor from one object to
-   * another.
-   *
-   * @param other The other basic_stream_descriptor object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_stream_descriptor(io_context&) constructor.
-   */
-  basic_stream_descriptor& operator=(basic_stream_descriptor&& other)
-  {
-    basic_descriptor<StreamDescriptorService>::operator=(
-        ASIO_MOVE_CAST(basic_stream_descriptor)(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Write some data to the descriptor.
-  /**
-   * This function is used to write data to the stream descriptor. The function
-   * call will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the descriptor.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * descriptor.write_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "write_some");
-    return s;
-  }
-
-  /// Write some data to the descriptor.
-  /**
-   * This function is used to write data to the stream descriptor. The function
-   * call will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the descriptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous write.
-  /**
-   * This function is used to asynchronously write data to the stream
-   * descriptor. The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be written to the descriptor.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The write operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write function if you need to ensure that all
-   * data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * descriptor.async_write_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-    return this->get_service().async_write_some(this->get_implementation(),
-        buffers, ASIO_MOVE_CAST(WriteHandler)(handler));
-  }
-
-  /// Read some data from the descriptor.
-  /**
-   * This function is used to read data from the stream descriptor. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * descriptor.read_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "read_some");
-    return s;
-  }
-
-  /// Read some data from the descriptor.
-  /**
-   * This function is used to read data from the stream descriptor. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous read.
-  /**
-   * This function is used to asynchronously read data from the stream
-   * descriptor. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The read operation may not read all of the requested number of bytes.
-   * Consider using the @ref async_read function if you need to ensure that the
-   * requested amount of data is read before the asynchronous operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * descriptor.async_read_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-    return this->get_service().async_read_some(this->get_implementation(),
-        buffers, ASIO_MOVE_CAST(ReadHandler)(handler));
-  }
-};
-
-} // namespace posix
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_POSIX_BASIC_STREAM_DESCRIPTOR_HPP
diff --git a/tools/sdk/include/asio/asio/posix/descriptor.hpp b/tools/sdk/include/asio/asio/posix/descriptor.hpp
deleted file mode 100644
index d0cee1a2647..00000000000
--- a/tools/sdk/include/asio/asio/posix/descriptor.hpp
+++ /dev/null
@@ -1,644 +0,0 @@
-//
-// posix/descriptor.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_POSIX_DESCRIPTOR_HPP
-#define ASIO_POSIX_DESCRIPTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/async_result.hpp"
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/reactive_descriptor_service.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/posix/descriptor_base.hpp"
-
-#if defined(ASIO_HAS_MOVE)
-# include <utility>
-#endif // defined(ASIO_HAS_MOVE)
-
-#define ASIO_SVC_T asio::detail::reactive_descriptor_service
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace posix {
-
-/// Provides POSIX descriptor functionality.
-/**
- * The posix::descriptor class template provides the ability to wrap a
- * POSIX descriptor.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class descriptor
-  : ASIO_SVC_ACCESS basic_io_object<ASIO_SVC_T>,
-    public descriptor_base
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// The native representation of a descriptor.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef ASIO_SVC_T::native_handle_type native_handle_type;
-#endif
-
-  /// A descriptor is always the lowest layer.
-  typedef descriptor lowest_layer_type;
-
-  /// Construct a descriptor without opening it.
-  /**
-   * This constructor creates a descriptor without opening it.
-   *
-   * @param io_context The io_context object that the descriptor will use to
-   * dispatch handlers for any asynchronous operations performed on the
-   * descriptor.
-   */
-  explicit descriptor(asio::io_context& io_context)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-  }
-
-  /// Construct a descriptor on an existing native descriptor.
-  /**
-   * This constructor creates a descriptor object to hold an existing native
-   * descriptor.
-   *
-   * @param io_context The io_context object that the descriptor will use to
-   * dispatch handlers for any asynchronous operations performed on the
-   * descriptor.
-   *
-   * @param native_descriptor A native descriptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  descriptor(asio::io_context& io_context,
-      const native_handle_type& native_descriptor)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        native_descriptor, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a descriptor from another.
-  /**
-   * This constructor moves a descriptor from one object to another.
-   *
-   * @param other The other descriptor object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c descriptor(io_context&) constructor.
-   */
-  descriptor(descriptor&& other)
-    : basic_io_object<ASIO_SVC_T>(std::move(other))
-  {
-  }
-
-  /// Move-assign a descriptor from another.
-  /**
-   * This assignment operator moves a descriptor from one object to another.
-   *
-   * @param other The other descriptor object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c descriptor(io_context&) constructor.
-   */
-  descriptor& operator=(descriptor&& other)
-  {
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<ASIO_SVC_T>::get_executor();
-  }
-
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * layers. Since a descriptor cannot contain any further layers, it
-   * simply returns a reference to itself.
-   *
-   * @return A reference to the lowest layer in the stack of layers. Ownership
-   * is not transferred to the caller.
-   */
-  lowest_layer_type& lowest_layer()
-  {
-    return *this;
-  }
-
-  /// Get a const reference to the lowest layer.
-  /**
-   * This function returns a const reference to the lowest layer in a stack of
-   * layers. Since a descriptor cannot contain any further layers, it
-   * simply returns a reference to itself.
-   *
-   * @return A const reference to the lowest layer in the stack of layers.
-   * Ownership is not transferred to the caller.
-   */
-  const lowest_layer_type& lowest_layer() const
-  {
-    return *this;
-  }
-
-  /// Assign an existing native descriptor to the descriptor.
-  /*
-   * This function opens the descriptor to hold an existing native descriptor.
-   *
-   * @param native_descriptor A native descriptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void assign(const native_handle_type& native_descriptor)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        native_descriptor, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-  /// Assign an existing native descriptor to the descriptor.
-  /*
-   * This function opens the descriptor to hold an existing native descriptor.
-   *
-   * @param native_descriptor A native descriptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID assign(const native_handle_type& native_descriptor,
-      asio::error_code& ec)
-  {
-    this->get_service().assign(
-        this->get_implementation(), native_descriptor, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the descriptor is open.
-  bool is_open() const
-  {
-    return this->get_service().is_open(this->get_implementation());
-  }
-
-  /// Close the descriptor.
-  /**
-   * This function is used to close the descriptor. Any asynchronous read or
-   * write operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure. Note that, even if
-   * the function indicates an error, the underlying descriptor is closed.
-   */
-  void close()
-  {
-    asio::error_code ec;
-    this->get_service().close(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "close");
-  }
-
-  /// Close the descriptor.
-  /**
-   * This function is used to close the descriptor. Any asynchronous read or
-   * write operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any. Note that, even if
-   * the function indicates an error, the underlying descriptor is closed.
-   */
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    this->get_service().close(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native descriptor representation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * descriptor. This is intended to allow access to native descriptor
-   * functionality that is not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return this->get_service().native_handle(this->get_implementation());
-  }
-
-  /// Release ownership of the native descriptor implementation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * descriptor. After calling this function, @c is_open() returns false. The
-   * caller is responsible for closing the descriptor.
-   *
-   * All outstanding asynchronous read or write operations will finish
-   * immediately, and the handlers for cancelled operations will be passed the
-   * asio::error::operation_aborted error.
-   */
-  native_handle_type release()
-  {
-    return this->get_service().release(this->get_implementation());
-  }
-
-  /// Cancel all asynchronous operations associated with the descriptor.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all asynchronous operations associated with the descriptor.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the descriptor.
-  /**
-   * This function is used to execute an IO control command on the descriptor.
-   *
-   * @param command The IO control command to be performed on the descriptor.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa IoControlCommand @n
-   * asio::posix::descriptor_base::bytes_readable @n
-   * asio::posix::descriptor_base::non_blocking_io
-   *
-   * @par Example
-   * Getting the number of bytes ready to read:
-   * @code
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * asio::posix::stream_descriptor::bytes_readable command;
-   * descriptor.io_control(command);
-   * std::size_t bytes_readable = command.get();
-   * @endcode
-   */
-  template <typename IoControlCommand>
-  void io_control(IoControlCommand& command)
-  {
-    asio::error_code ec;
-    this->get_service().io_control(this->get_implementation(), command, ec);
-    asio::detail::throw_error(ec, "io_control");
-  }
-
-  /// Perform an IO control command on the descriptor.
-  /**
-   * This function is used to execute an IO control command on the descriptor.
-   *
-   * @param command The IO control command to be performed on the descriptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa IoControlCommand @n
-   * asio::posix::descriptor_base::bytes_readable @n
-   * asio::posix::descriptor_base::non_blocking_io
-   *
-   * @par Example
-   * Getting the number of bytes ready to read:
-   * @code
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * asio::posix::stream_descriptor::bytes_readable command;
-   * asio::error_code ec;
-   * descriptor.io_control(command, ec);
-   * if (ec)
-   * {
-   *   // An error occurred.
-   * }
-   * std::size_t bytes_readable = command.get();
-   * @endcode
-   */
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(IoControlCommand& command,
-      asio::error_code& ec)
-  {
-    this->get_service().io_control(this->get_implementation(), command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the descriptor.
-  /**
-   * @returns @c true if the descriptor's synchronous operations will fail with
-   * asio::error::would_block if they are unable to perform the requested
-   * operation immediately. If @c false, synchronous operations will block
-   * until complete.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  bool non_blocking() const
-  {
-    return this->get_service().non_blocking(this->get_implementation());
-  }
-
-  /// Sets the non-blocking mode of the descriptor.
-  /**
-   * @param mode If @c true, the descriptor's synchronous operations will fail
-   * with asio::error::would_block if they are unable to perform the
-   * requested operation immediately. If @c false, synchronous operations will
-   * block until complete.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  void non_blocking(bool mode)
-  {
-    asio::error_code ec;
-    this->get_service().non_blocking(this->get_implementation(), mode, ec);
-    asio::detail::throw_error(ec, "non_blocking");
-  }
-
-  /// Sets the non-blocking mode of the descriptor.
-  /**
-   * @param mode If @c true, the descriptor's synchronous operations will fail
-   * with asio::error::would_block if they are unable to perform the
-   * requested operation immediately. If @c false, synchronous operations will
-   * block until complete.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note The non-blocking mode has no effect on the behaviour of asynchronous
-   * operations. Asynchronous operations will never fail with the error
-   * asio::error::would_block.
-   */
-  ASIO_SYNC_OP_VOID non_blocking(
-      bool mode, asio::error_code& ec)
-  {
-    this->get_service().non_blocking(this->get_implementation(), mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native descriptor implementation.
-  /**
-   * This function is used to retrieve the non-blocking mode of the underlying
-   * native descriptor. This mode has no effect on the behaviour of the
-   * descriptor object's synchronous operations.
-   *
-   * @returns @c true if the underlying descriptor is in non-blocking mode and
-   * direct system calls may fail with asio::error::would_block (or the
-   * equivalent system error).
-   *
-   * @note The current non-blocking mode is cached by the descriptor object.
-   * Consequently, the return value may be incorrect if the non-blocking mode
-   * was set directly on the native descriptor.
-   */
-  bool native_non_blocking() const
-  {
-    return this->get_service().native_non_blocking(
-        this->get_implementation());
-  }
-
-  /// Sets the non-blocking mode of the native descriptor implementation.
-  /**
-   * This function is used to modify the non-blocking mode of the underlying
-   * native descriptor. It has no effect on the behaviour of the descriptor
-   * object's synchronous operations.
-   *
-   * @param mode If @c true, the underlying descriptor is put into non-blocking
-   * mode and direct system calls may fail with asio::error::would_block
-   * (or the equivalent system error).
-   *
-   * @throws asio::system_error Thrown on failure. If the @c mode is
-   * @c false, but the current value of @c non_blocking() is @c true, this
-   * function fails with asio::error::invalid_argument, as the
-   * combination does not make sense.
-   */
-  void native_non_blocking(bool mode)
-  {
-    asio::error_code ec;
-    this->get_service().native_non_blocking(
-        this->get_implementation(), mode, ec);
-    asio::detail::throw_error(ec, "native_non_blocking");
-  }
-
-  /// Sets the non-blocking mode of the native descriptor implementation.
-  /**
-   * This function is used to modify the non-blocking mode of the underlying
-   * native descriptor. It has no effect on the behaviour of the descriptor
-   * object's synchronous operations.
-   *
-   * @param mode If @c true, the underlying descriptor is put into non-blocking
-   * mode and direct system calls may fail with asio::error::would_block
-   * (or the equivalent system error).
-   *
-   * @param ec Set to indicate what error occurred, if any. If the @c mode is
-   * @c false, but the current value of @c non_blocking() is @c true, this
-   * function fails with asio::error::invalid_argument, as the
-   * combination does not make sense.
-   */
-  ASIO_SYNC_OP_VOID native_non_blocking(
-      bool mode, asio::error_code& ec)
-  {
-    this->get_service().native_non_blocking(
-        this->get_implementation(), mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Wait for the descriptor to become ready to read, ready to write, or to
-  /// have pending error conditions.
-  /**
-   * This function is used to perform a blocking wait for a descriptor to enter
-   * a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired descriptor state.
-   *
-   * @par Example
-   * Waiting for a descriptor to become readable.
-   * @code
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * descriptor.wait(asio::posix::stream_descriptor::wait_read);
-   * @endcode
-   */
-  void wait(wait_type w)
-  {
-    asio::error_code ec;
-    this->get_service().wait(this->get_implementation(), w, ec);
-    asio::detail::throw_error(ec, "wait");
-  }
-
-  /// Wait for the descriptor to become ready to read, ready to write, or to
-  /// have pending error conditions.
-  /**
-   * This function is used to perform a blocking wait for a descriptor to enter
-   * a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired descriptor state.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @par Example
-   * Waiting for a descriptor to become readable.
-   * @code
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * asio::error_code ec;
-   * descriptor.wait(asio::posix::stream_descriptor::wait_read, ec);
-   * @endcode
-   */
-  ASIO_SYNC_OP_VOID wait(wait_type w, asio::error_code& ec)
-  {
-    this->get_service().wait(this->get_implementation(), w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the descriptor to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  /**
-   * This function is used to perform an asynchronous wait for a descriptor to
-   * enter a ready to read, write or error condition state.
-   *
-   * @param w Specifies the desired descriptor state.
-   *
-   * @param handler The handler to be called when the wait operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @par Example
-   * @code
-   * void wait_handler(const asio::error_code& error)
-   * {
-   *   if (!error)
-   *   {
-   *     // Wait succeeded.
-   *   }
-   * }
-   *
-   * ...
-   *
-   * asio::posix::stream_descriptor descriptor(io_context);
-   * ...
-   * descriptor.async_wait(
-   *     asio::posix::stream_descriptor::wait_read,
-   *     wait_handler);
-   * @endcode
-   */
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(wait_type w, ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WaitHandler.
-    ASIO_WAIT_HANDLER_CHECK(WaitHandler, handler) type_check;
-
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    this->get_service().async_wait(
-        this->get_implementation(), w, init.completion_handler);
-
-    return init.result.get();
-  }
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  /**
-   * This function destroys the descriptor, cancelling any outstanding
-   * asynchronous wait operations associated with the descriptor as if by
-   * calling @c cancel.
-   */
-  ~descriptor()
-  {
-  }
-};
-
-} // namespace posix
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#undef ASIO_SVC_T
-
-#endif // defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_POSIX_DESCRIPTOR_HPP
diff --git a/tools/sdk/include/asio/asio/posix/descriptor_base.hpp b/tools/sdk/include/asio/asio/posix/descriptor_base.hpp
deleted file mode 100644
index 4aac04f1088..00000000000
--- a/tools/sdk/include/asio/asio/posix/descriptor_base.hpp
+++ /dev/null
@@ -1,90 +0,0 @@
-//
-// posix/descriptor_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_POSIX_DESCRIPTOR_BASE_HPP
-#define ASIO_POSIX_DESCRIPTOR_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/detail/io_control.hpp"
-#include "asio/detail/socket_option.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace posix {
-
-/// The descriptor_base class is used as a base for the descriptor class as a
-/// place to define the associated IO control commands.
-class descriptor_base
-{
-public:
-  /// Wait types.
-  /**
-   * For use with descriptor::wait() and descriptor::async_wait().
-   */
-  enum wait_type
-  {
-    /// Wait for a descriptor to become ready to read.
-    wait_read,
-
-    /// Wait for a descriptor to become ready to write.
-    wait_write,
-
-    /// Wait for a descriptor to have error conditions pending.
-    wait_error
-  };
-
-  /// IO control command to get the amount of data that can be read without
-  /// blocking.
-  /**
-   * Implements the FIONREAD IO control command.
-   *
-   * @par Example
-   * @code
-   * asio::posix::stream_descriptor descriptor(io_context); 
-   * ...
-   * asio::descriptor_base::bytes_readable command(true);
-   * descriptor.io_control(command);
-   * std::size_t bytes_readable = command.get();
-   * @endcode
-   *
-   * @par Concepts:
-   * IoControlCommand.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined bytes_readable;
-#else
-  typedef asio::detail::io_control::bytes_readable bytes_readable;
-#endif
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  ~descriptor_base()
-  {
-  }
-};
-
-} // namespace posix
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_POSIX_DESCRIPTOR_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/posix/stream_descriptor.hpp b/tools/sdk/include/asio/asio/posix/stream_descriptor.hpp
deleted file mode 100644
index abb426a3904..00000000000
--- a/tools/sdk/include/asio/asio/posix/stream_descriptor.hpp
+++ /dev/null
@@ -1,360 +0,0 @@
-//
-// posix/stream_descriptor.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_POSIX_STREAM_DESCRIPTOR_HPP
-#define ASIO_POSIX_STREAM_DESCRIPTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/posix/descriptor.hpp"
-
-#if defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/posix/basic_stream_descriptor.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-namespace asio {
-namespace posix {
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-// Typedef for the typical usage of a stream-oriented descriptor.
-typedef basic_stream_descriptor<> stream_descriptor;
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-/// Provides stream-oriented descriptor functionality.
-/**
- * The posix::stream_descriptor class template provides asynchronous and
- * blocking stream-oriented descriptor functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * AsyncReadStream, AsyncWriteStream, Stream, SyncReadStream, SyncWriteStream.
- */
-class stream_descriptor
-  : public descriptor
-{
-public:
-  /// Construct a stream_descriptor without opening it.
-  /**
-   * This constructor creates a stream descriptor without opening it. The
-   * descriptor needs to be opened and then connected or accepted before data
-   * can be sent or received on it.
-   *
-   * @param io_context The io_context object that the stream descriptor will
-   * use to dispatch handlers for any asynchronous operations performed on the
-   * descriptor.
-   */
-  explicit stream_descriptor(asio::io_context& io_context)
-    : descriptor(io_context)
-  {
-  }
-
-  /// Construct a stream_descriptor on an existing native descriptor.
-  /**
-   * This constructor creates a stream descriptor object to hold an existing
-   * native descriptor.
-   *
-   * @param io_context The io_context object that the stream descriptor will
-   * use to dispatch handlers for any asynchronous operations performed on the
-   * descriptor.
-   *
-   * @param native_descriptor The new underlying descriptor implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  stream_descriptor(asio::io_context& io_context,
-      const native_handle_type& native_descriptor)
-    : descriptor(io_context, native_descriptor)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a stream_descriptor from another.
-  /**
-   * This constructor moves a stream descriptor from one object to another.
-   *
-   * @param other The other stream_descriptor object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c stream_descriptor(io_context&) constructor.
-   */
-  stream_descriptor(stream_descriptor&& other)
-    : descriptor(std::move(other))
-  {
-  }
-
-  /// Move-assign a stream_descriptor from another.
-  /**
-   * This assignment operator moves a stream descriptor from one object to
-   * another.
-   *
-   * @param other The other stream_descriptor object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c stream_descriptor(io_context&) constructor.
-   */
-  stream_descriptor& operator=(stream_descriptor&& other)
-  {
-    descriptor::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Write some data to the descriptor.
-  /**
-   * This function is used to write data to the stream descriptor. The function
-   * call will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the descriptor.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * descriptor.write_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "write_some");
-    return s;
-  }
-
-  /// Write some data to the descriptor.
-  /**
-   * This function is used to write data to the stream descriptor. The function
-   * call will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the descriptor.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous write.
-  /**
-   * This function is used to asynchronously write data to the stream
-   * descriptor. The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be written to the descriptor.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The write operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write function if you need to ensure that all
-   * data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * descriptor.async_write_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-    asio::async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_write_some(
-        this->get_implementation(), buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Read some data from the descriptor.
-  /**
-   * This function is used to read data from the stream descriptor. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * descriptor.read_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "read_some");
-    return s;
-  }
-
-  /// Read some data from the descriptor.
-  /**
-   * This function is used to read data from the stream descriptor. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous read.
-  /**
-   * This function is used to asynchronously read data from the stream
-   * descriptor. The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The read operation may not read all of the requested number of bytes.
-   * Consider using the @ref async_read function if you need to ensure that the
-   * requested amount of data is read before the asynchronous operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * descriptor.async_read_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-    asio::async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_read_some(
-        this->get_implementation(), buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-};
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-} // namespace posix
-} // namespace asio
-
-#endif // defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_POSIX_STREAM_DESCRIPTOR_HPP
diff --git a/tools/sdk/include/asio/asio/posix/stream_descriptor_service.hpp b/tools/sdk/include/asio/asio/posix/stream_descriptor_service.hpp
deleted file mode 100644
index 4ffbb9602d5..00000000000
--- a/tools/sdk/include/asio/asio/posix/stream_descriptor_service.hpp
+++ /dev/null
@@ -1,279 +0,0 @@
-//
-// posix/stream_descriptor_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_POSIX_STREAM_DESCRIPTOR_SERVICE_HPP
-#define ASIO_POSIX_STREAM_DESCRIPTOR_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/detail/reactive_descriptor_service.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace posix {
-
-/// Default service implementation for a stream descriptor.
-class stream_descriptor_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<stream_descriptor_service>
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-private:
-  // The type of the platform-specific implementation.
-  typedef detail::reactive_descriptor_service service_impl_type;
-
-public:
-  /// The type of a stream descriptor implementation.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native descriptor type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new stream descriptor service for the specified io_context.
-  explicit stream_descriptor_service(asio::io_context& io_context)
-    : asio::detail::service_base<stream_descriptor_service>(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new stream descriptor implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new stream descriptor implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another stream descriptor implementation.
-  void move_assign(implementation_type& impl,
-      stream_descriptor_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a stream descriptor implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Assign an existing native descriptor to a stream descriptor.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const native_handle_type& native_descriptor,
-      asio::error_code& ec)
-  {
-    service_impl_.assign(impl, native_descriptor, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the descriptor is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Close a stream descriptor implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native descriptor implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Release ownership of the native descriptor implementation.
-  native_handle_type release(implementation_type& impl)
-  {
-    return service_impl_.release(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the descriptor.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the descriptor.
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(implementation_type& impl,
-      IoControlCommand& command, asio::error_code& ec)
-  {
-    service_impl_.io_control(impl, command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the descriptor.
-  bool non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the descriptor.
-  ASIO_SYNC_OP_VOID non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native descriptor implementation.
-  bool native_non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.native_non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the native descriptor implementation.
-  ASIO_SYNC_OP_VOID native_non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.native_non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Wait for the descriptor to become ready to read, ready to write, or to
-  /// have pending error conditions.
-  ASIO_SYNC_OP_VOID wait(implementation_type& impl,
-      descriptor_base::wait_type w, asio::error_code& ec)
-  {
-    service_impl_.wait(impl, w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the descriptor to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(implementation_type& impl, descriptor_base::wait_type w,
-      ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_wait(impl, w, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Write the given data to the stream.
-  template <typename ConstBufferSequence>
-  std::size_t write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    return service_impl_.write_some(impl, buffers, ec);
-  }
-
-  /// Start an asynchronous write.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    asio::async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_write_some(impl, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Read some data from the stream.
-  template <typename MutableBufferSequence>
-  std::size_t read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    return service_impl_.read_some(impl, buffers, ec);
-  }
-
-  /// Start an asynchronous read.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    asio::async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_read_some(impl, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace posix
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_POSIX_STREAM_DESCRIPTOR)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_POSIX_STREAM_DESCRIPTOR_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/post.hpp b/tools/sdk/include/asio/asio/post.hpp
deleted file mode 100644
index 87d7b96d6be..00000000000
--- a/tools/sdk/include/asio/asio/post.hpp
+++ /dev/null
@@ -1,107 +0,0 @@
-//
-// post.hpp
-// ~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_POST_HPP
-#define ASIO_POST_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/async_result.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/execution_context.hpp"
-#include "asio/is_executor.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Submits a completion token or function object for execution.
-/**
- * This function submits an object for execution using the object's associated
- * executor. The function object is queued for execution, and is never called
- * from the current thread prior to returning from <tt>post()</tt>.
- *
- * This function has the following effects:
- *
- * @li Constructs a function object handler of type @c Handler, initialized
- * with <tt>handler(forward<CompletionToken>(token))</tt>.
- *
- * @li Constructs an object @c result of type <tt>async_result<Handler></tt>,
- * initializing the object as <tt>result(handler)</tt>.
- *
- * @li Obtains the handler's associated executor object @c ex by performing
- * <tt>get_associated_executor(handler)</tt>.
- *
- * @li Obtains the handler's associated allocator object @c alloc by performing
- * <tt>get_associated_allocator(handler)</tt>.
- *
- * @li Performs <tt>ex.post(std::move(handler), alloc)</tt>.
- *
- * @li Returns <tt>result.get()</tt>.
- */
-template <typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) post(
-    ASIO_MOVE_ARG(CompletionToken) token);
-
-/// Submits a completion token or function object for execution.
-/**
- * This function submits an object for execution using the specified executor.
- * The function object is queued for execution, and is never called from the
- * current thread prior to returning from <tt>post()</tt>.
- *
- * This function has the following effects:
- *
- * @li Constructs a function object handler of type @c Handler, initialized
- * with <tt>handler(forward<CompletionToken>(token))</tt>.
- *
- * @li Constructs an object @c result of type <tt>async_result<Handler></tt>,
- * initializing the object as <tt>result(handler)</tt>.
- *
- * @li Obtains the handler's associated executor object @c ex1 by performing
- * <tt>get_associated_executor(handler)</tt>.
- *
- * @li Creates a work object @c w by performing <tt>make_work(ex1)</tt>.
- *
- * @li Obtains the handler's associated allocator object @c alloc by performing
- * <tt>get_associated_allocator(handler)</tt>.
- *
- * @li Constructs a function object @c f with a function call operator that
- * performs <tt>ex1.dispatch(std::move(handler), alloc)</tt> followed by
- * <tt>w.reset()</tt>.
- *
- * @li Performs <tt>Executor(ex).post(std::move(f), alloc)</tt>.
- *
- * @li Returns <tt>result.get()</tt>.
- */
-template <typename Executor, typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) post(
-    const Executor& ex, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_executor<Executor>::value>::type* = 0);
-
-/// Submits a completion token or function object for execution.
-/**
- * @returns <tt>post(ctx.get_executor(), forward<CompletionToken>(token))</tt>.
- */
-template <typename ExecutionContext, typename CompletionToken>
-ASIO_INITFN_RESULT_TYPE(CompletionToken, void()) post(
-    ExecutionContext& ctx, ASIO_MOVE_ARG(CompletionToken) token,
-    typename enable_if<is_convertible<
-      ExecutionContext&, execution_context&>::value>::type* = 0);
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/post.hpp"
-
-#endif // ASIO_POST_HPP
diff --git a/tools/sdk/include/asio/asio/raw_socket_service.hpp b/tools/sdk/include/asio/asio/raw_socket_service.hpp
deleted file mode 100644
index 2bccf032e3d..00000000000
--- a/tools/sdk/include/asio/asio/raw_socket_service.hpp
+++ /dev/null
@@ -1,466 +0,0 @@
-//
-// raw_socket_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_RAW_SOCKET_SERVICE_HPP
-#define ASIO_RAW_SOCKET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/null_socket_service.hpp"
-#elif defined(ASIO_HAS_IOCP)
-# include "asio/detail/win_iocp_socket_service.hpp"
-#else
-# include "asio/detail/reactive_socket_service.hpp"
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default service implementation for a raw socket.
-template <typename Protocol>
-class raw_socket_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<raw_socket_service<Protocol> >
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-private:
-  // The type of the platform-specific implementation.
-#if defined(ASIO_WINDOWS_RUNTIME)
-  typedef detail::null_socket_service<Protocol> service_impl_type;
-#elif defined(ASIO_HAS_IOCP)
-  typedef detail::win_iocp_socket_service<Protocol> service_impl_type;
-#else
-  typedef detail::reactive_socket_service<Protocol> service_impl_type;
-#endif
-
-public:
-  /// The type of a raw socket.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef typename service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native socket type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new raw socket service for the specified io_context.
-  explicit raw_socket_service(asio::io_context& io_context)
-    : asio::detail::service_base<
-        raw_socket_service<Protocol> >(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new raw socket implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new raw socket implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another raw socket implementation.
-  void move_assign(implementation_type& impl,
-      raw_socket_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-
-  // All socket services have access to each other's implementations.
-  template <typename Protocol1> friend class raw_socket_service;
-
-  /// Move-construct a new raw socket implementation from another protocol
-  /// type.
-  template <typename Protocol1>
-  void converting_move_construct(implementation_type& impl,
-      raw_socket_service<Protocol1>& other_service,
-      typename raw_socket_service<
-        Protocol1>::implementation_type& other_impl,
-      typename enable_if<is_convertible<
-        Protocol1, Protocol>::value>::type* = 0)
-  {
-    service_impl_.template converting_move_construct<Protocol1>(
-        impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a raw socket implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  // Open a new raw socket implementation.
-  ASIO_SYNC_OP_VOID open(implementation_type& impl,
-      const protocol_type& protocol, asio::error_code& ec)
-  {
-    if (protocol.type() == ASIO_OS_DEF(SOCK_RAW))
-      service_impl_.open(impl, protocol, ec);
-    else
-      ec = asio::error::invalid_argument;
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assign an existing native socket to a raw socket.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const protocol_type& protocol, const native_handle_type& native_socket,
-      asio::error_code& ec)
-  {
-    service_impl_.assign(impl, protocol, native_socket, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Close a raw socket implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Release ownership of the underlying socket.
-  native_handle_type release(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return service_impl_.release(impl, ec);
-  }
-
-  /// Get the native socket implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the socket.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is at the out-of-band data mark.
-  bool at_mark(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.at_mark(impl, ec);
-  }
-
-  /// Determine the number of bytes available for reading.
-  std::size_t available(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.available(impl, ec);
-  }
-
-  // Bind the raw socket to the specified local endpoint.
-  ASIO_SYNC_OP_VOID bind(implementation_type& impl,
-      const endpoint_type& endpoint, asio::error_code& ec)
-  {
-    service_impl_.bind(impl, endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Connect the raw socket to the specified endpoint.
-  ASIO_SYNC_OP_VOID connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, asio::error_code& ec)
-  {
-    service_impl_.connect(impl, peer_endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous connect.
-  template <typename ConnectHandler>
-  ASIO_INITFN_RESULT_TYPE(ConnectHandler,
-      void (asio::error_code))
-  async_connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint,
-      ASIO_MOVE_ARG(ConnectHandler) handler)
-  {
-    async_completion<ConnectHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_connect(impl, peer_endpoint, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Set a socket option.
-  template <typename SettableSocketOption>
-  ASIO_SYNC_OP_VOID set_option(implementation_type& impl,
-      const SettableSocketOption& option, asio::error_code& ec)
-  {
-    service_impl_.set_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get a socket option.
-  template <typename GettableSocketOption>
-  ASIO_SYNC_OP_VOID get_option(const implementation_type& impl,
-      GettableSocketOption& option, asio::error_code& ec) const
-  {
-    service_impl_.get_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the socket.
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(implementation_type& impl,
-      IoControlCommand& command, asio::error_code& ec)
-  {
-    service_impl_.io_control(impl, command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the socket.
-  bool non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the socket.
-  ASIO_SYNC_OP_VOID non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native socket implementation.
-  bool native_non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.native_non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the native socket implementation.
-  ASIO_SYNC_OP_VOID native_non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.native_non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the local endpoint.
-  endpoint_type local_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.local_endpoint(impl, ec);
-  }
-
-  /// Get the remote endpoint.
-  endpoint_type remote_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.remote_endpoint(impl, ec);
-  }
-
-  /// Disable sends or receives on the socket.
-  ASIO_SYNC_OP_VOID shutdown(implementation_type& impl,
-      socket_base::shutdown_type what, asio::error_code& ec)
-  {
-    service_impl_.shutdown(impl, what, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Wait for the socket to become ready to read, ready to write, or to have
-  /// pending error conditions.
-  ASIO_SYNC_OP_VOID wait(implementation_type& impl,
-      socket_base::wait_type w, asio::error_code& ec)
-  {
-    service_impl_.wait(impl, w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the socket to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(implementation_type& impl, socket_base::wait_type w,
-      ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_wait(impl, w, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Send the given data to the peer.
-  template <typename ConstBufferSequence>
-  std::size_t send(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.send(impl, buffers, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(implementation_type& impl, const ConstBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_send(impl, buffers, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Send raw data to the specified endpoint.
-  template <typename ConstBufferSequence>
-  std::size_t send_to(implementation_type& impl,
-      const ConstBufferSequence& buffers, const endpoint_type& destination,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.send_to(impl, buffers, destination, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send_to(implementation_type& impl,
-      const ConstBufferSequence& buffers, const endpoint_type& destination,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_send_to(impl, buffers,
-        destination, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Receive some data from the peer.
-  template <typename MutableBufferSequence>
-  std::size_t receive(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.receive(impl, buffers, flags, ec);
-  }
-
-  /// Start an asynchronous receive.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_receive(impl, buffers, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Receive raw data with the endpoint of the sender.
-  template <typename MutableBufferSequence>
-  std::size_t receive_from(implementation_type& impl,
-      const MutableBufferSequence& buffers, endpoint_type& sender_endpoint,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.receive_from(impl, buffers, sender_endpoint, flags,
-        ec);
-  }
-
-  /// Start an asynchronous receive that will get the endpoint of the sender.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive_from(implementation_type& impl,
-      const MutableBufferSequence& buffers, endpoint_type& sender_endpoint,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_receive_from(impl, buffers,
-        sender_endpoint, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_RAW_SOCKET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/read.hpp b/tools/sdk/include/asio/asio/read.hpp
deleted file mode 100644
index e77206a88cf..00000000000
--- a/tools/sdk/include/asio/asio/read.hpp
+++ /dev/null
@@ -1,947 +0,0 @@
-//
-// read.hpp
-// ~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_READ_HPP
-#define ASIO_READ_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/buffer.hpp"
-#include "asio/error.hpp"
-
-#if !defined(ASIO_NO_EXTENSIONS)
-# include "asio/basic_streambuf_fwd.hpp"
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/**
- * @defgroup read asio::read
- *
- * @brief Attempt to read a certain amount of data from a stream before
- * returning.
- */
-/*@{*/
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * stream.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code asio::read(s, asio::buffer(data, size)); @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read(
- *     s, buffers,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncReadStream, typename MutableBufferSequence>
-std::size_t read(SyncReadStream& s, const MutableBufferSequence& buffers,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type* = 0);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * stream.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code asio::read(s, asio::buffer(data, size), ec); @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read(
- *     s, buffers,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncReadStream, typename MutableBufferSequence>
-std::size_t read(SyncReadStream& s, const MutableBufferSequence& buffers,
-    asio::error_code& ec,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type* = 0);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * stream.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the stream's read_some function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code asio::read(s, asio::buffer(data, size),
- *     asio::transfer_at_least(32)); @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename SyncReadStream, typename MutableBufferSequence,
-  typename CompletionCondition>
-std::size_t read(SyncReadStream& s, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type* = 0);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * stream.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the stream's read_some function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes read. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncReadStream, typename MutableBufferSequence,
-    typename CompletionCondition>
-std::size_t read(SyncReadStream& s, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition, asio::error_code& ec,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type* = 0);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The specified dynamic buffer sequence is full (that is, it has reached
- * maximum size).
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read(
- *     s, buffers,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The supplied buffer is full (that is, it has reached maximum size).
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read(
- *     s, buffers,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    asio::error_code& ec,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The specified dynamic buffer sequence is full (that is, it has reached
- * maximum size).
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the stream's read_some function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- */
-template <typename SyncReadStream, typename DynamicBuffer,
-    typename CompletionCondition>
-std::size_t read(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The specified dynamic buffer sequence is full (that is, it has reached
- * maximum size).
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the stream's read_some function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes read. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncReadStream, typename DynamicBuffer,
-    typename CompletionCondition>
-std::size_t read(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition, asio::error_code& ec,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The supplied buffer is full (that is, it has reached maximum size).
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b The basic_streambuf object into which the data will be read.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read(
- *     s, b,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncReadStream, typename Allocator>
-std::size_t read(SyncReadStream& s, basic_streambuf<Allocator>& b);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The supplied buffer is full (that is, it has reached maximum size).
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b The basic_streambuf object into which the data will be read.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read(
- *     s, b,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncReadStream, typename Allocator>
-std::size_t read(SyncReadStream& s, basic_streambuf<Allocator>& b,
-    asio::error_code& ec);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The supplied buffer is full (that is, it has reached maximum size).
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b The basic_streambuf object into which the data will be read.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the stream's read_some function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- */
-template <typename SyncReadStream, typename Allocator,
-    typename CompletionCondition>
-std::size_t read(SyncReadStream& s, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition);
-
-/// Attempt to read a certain amount of data from a stream before returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * stream. The call will block until one of the following conditions is true:
- *
- * @li The supplied buffer is full (that is, it has reached maximum size).
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b The basic_streambuf object into which the data will be read.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the stream's read_some function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes read. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncReadStream, typename Allocator,
-    typename CompletionCondition>
-std::size_t read(SyncReadStream& s, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition, asio::error_code& ec);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-/**
- * @defgroup async_read asio::async_read
- *
- * @brief Start an asynchronous operation to read a certain amount of data from
- * a stream.
- */
-/*@{*/
-
-/// Start an asynchronous operation to read a certain amount of data from a
-/// stream.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions is
- * true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other read operations (such
- * as async_read, the stream's async_read_some function, or any other composed
- * operations that perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * stream. Although the buffers object may be copied as necessary, ownership of
- * the underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes copied into the
- *                                           // buffers. If an error occurred,
- *                                           // this will be the  number of
- *                                           // bytes successfully transferred
- *                                           // prior to the error.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code
- * asio::async_read(s, asio::buffer(data, size), handler);
- * @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::async_read(
- *     s, buffers,
- *     asio::transfer_all(),
- *     handler); @endcode
- */
-template <typename AsyncReadStream, typename MutableBufferSequence,
-    typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s, const MutableBufferSequence& buffers,
-    ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type* = 0);
-
-/// Start an asynchronous operation to read a certain amount of data from a
-/// stream.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions is
- * true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * stream. Although the buffers object may be copied as necessary, ownership of
- * the underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_read_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the stream's async_read_some function.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes copied into the
- *                                           // buffers. If an error occurred,
- *                                           // this will be the  number of
- *                                           // bytes successfully transferred
- *                                           // prior to the error.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code asio::async_read(s,
- *     asio::buffer(data, size),
- *     asio::transfer_at_least(32),
- *     handler); @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename AsyncReadStream, typename MutableBufferSequence,
-    typename CompletionCondition, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<
-      is_mutable_buffer_sequence<MutableBufferSequence>::value
-    >::type* = 0);
-
-/// Start an asynchronous operation to read a certain amount of data from a
-/// stream.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions is
- * true:
- *
- * @li The specified dynamic buffer sequence is full (that is, it has reached
- * maximum size).
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other read operations (such
- * as async_read, the stream's async_read_some function, or any other composed
- * operations that perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes copied into the
- *                                           // buffers. If an error occurred,
- *                                           // this will be the  number of
- *                                           // bytes successfully transferred
- *                                           // prior to the error.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note This overload is equivalent to calling:
- * @code asio::async_read(
- *     s, buffers,
- *     asio::transfer_all(),
- *     handler); @endcode
- */
-template <typename AsyncReadStream,
-    typename DynamicBuffer, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-/// Start an asynchronous operation to read a certain amount of data from a
-/// stream.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions is
- * true:
- *
- * @li The specified dynamic buffer sequence is full (that is, it has reached
- * maximum size).
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other read operations (such
- * as async_read, the stream's async_read_some function, or any other composed
- * operations that perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_read_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the stream's async_read_some function.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes copied into the
- *                                           // buffers. If an error occurred,
- *                                           // this will be the  number of
- *                                           // bytes successfully transferred
- *                                           // prior to the error.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- */
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename CompletionCondition, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Start an asynchronous operation to read a certain amount of data from a
-/// stream.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions is
- * true:
- *
- * @li The supplied buffer is full (that is, it has reached maximum size).
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other read operations (such
- * as async_read, the stream's async_read_some function, or any other composed
- * operations that perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param b A basic_streambuf object into which the data will be read. Ownership
- * of the streambuf is retained by the caller, which must guarantee that it
- * remains valid until the handler is called.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes copied into the
- *                                           // buffers. If an error occurred,
- *                                           // this will be the  number of
- *                                           // bytes successfully transferred
- *                                           // prior to the error.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note This overload is equivalent to calling:
- * @code asio::async_read(
- *     s, b,
- *     asio::transfer_all(),
- *     handler); @endcode
- */
-template <typename AsyncReadStream, typename Allocator, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s, basic_streambuf<Allocator>& b,
-    ASIO_MOVE_ARG(ReadHandler) handler);
-
-/// Start an asynchronous operation to read a certain amount of data from a
-/// stream.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions is
- * true:
- *
- * @li The supplied buffer is full (that is, it has reached maximum size).
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other read operations (such
- * as async_read, the stream's async_read_some function, or any other composed
- * operations that perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param b A basic_streambuf object into which the data will be read. Ownership
- * of the streambuf is retained by the caller, which must guarantee that it
- * remains valid until the handler is called.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_read_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the stream's async_read_some function.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes copied into the
- *                                           // buffers. If an error occurred,
- *                                           // this will be the  number of
- *                                           // bytes successfully transferred
- *                                           // prior to the error.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- */
-template <typename AsyncReadStream, typename Allocator,
-    typename CompletionCondition, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read(AsyncReadStream& s, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/read.hpp"
-
-#endif // ASIO_READ_HPP
diff --git a/tools/sdk/include/asio/asio/read_at.hpp b/tools/sdk/include/asio/asio/read_at.hpp
deleted file mode 100644
index df2c628782c..00000000000
--- a/tools/sdk/include/asio/asio/read_at.hpp
+++ /dev/null
@@ -1,671 +0,0 @@
-//
-// read_at.hpp
-// ~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_READ_AT_HPP
-#define ASIO_READ_AT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/cstdint.hpp"
-#include "asio/error.hpp"
-
-#if !defined(ASIO_NO_EXTENSIONS)
-# include "asio/basic_streambuf_fwd.hpp"
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/**
- * @defgroup read_at asio::read_at
- *
- * @brief Attempt to read a certain amount of data at the specified offset
- * before returning.
- */
-/*@{*/
-
-/// Attempt to read a certain amount of data at the specified offset before
-/// returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * random access device at the specified offset. The call will block until one
- * of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the SyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * device.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code asio::read_at(d, 42, asio::buffer(data, size)); @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read_at(
- *     d, 42, buffers,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncRandomAccessReadDevice, typename MutableBufferSequence>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers);
-
-/// Attempt to read a certain amount of data at the specified offset before
-/// returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * random access device at the specified offset. The call will block until one
- * of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the SyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * device.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code asio::read_at(d, 42,
- *     asio::buffer(data, size), ec); @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read_at(
- *     d, 42, buffers,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncRandomAccessReadDevice, typename MutableBufferSequence>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers,
-    asio::error_code& ec);
-
-/// Attempt to read a certain amount of data at the specified offset before
-/// returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * random access device at the specified offset. The call will block until one
- * of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the SyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * device.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the device's read_some_at function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code asio::read_at(d, 42, asio::buffer(data, size),
- *     asio::transfer_at_least(32)); @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename SyncRandomAccessReadDevice, typename MutableBufferSequence,
-    typename CompletionCondition>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition);
-
-/// Attempt to read a certain amount of data at the specified offset before
-/// returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * random access device at the specified offset. The call will block until one
- * of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the SyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * device.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the device's read_some_at function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes read. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncRandomAccessReadDevice, typename MutableBufferSequence,
-    typename CompletionCondition>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition, asio::error_code& ec);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Attempt to read a certain amount of data at the specified offset before
-/// returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * random access device at the specified offset. The call will block until one
- * of the following conditions is true:
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the SyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param b The basic_streambuf object into which the data will be read.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read_at(
- *     d, 42, b,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncRandomAccessReadDevice, typename Allocator>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, basic_streambuf<Allocator>& b);
-
-/// Attempt to read a certain amount of data at the specified offset before
-/// returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * random access device at the specified offset. The call will block until one
- * of the following conditions is true:
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the SyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param b The basic_streambuf object into which the data will be read.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @note This overload is equivalent to calling:
- * @code asio::read_at(
- *     d, 42, b,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncRandomAccessReadDevice, typename Allocator>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, basic_streambuf<Allocator>& b,
-    asio::error_code& ec);
-
-/// Attempt to read a certain amount of data at the specified offset before
-/// returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * random access device at the specified offset. The call will block until one
- * of the following conditions is true:
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the SyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param b The basic_streambuf object into which the data will be read.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the device's read_some_at function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- */
-template <typename SyncRandomAccessReadDevice, typename Allocator,
-    typename CompletionCondition>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition);
-
-/// Attempt to read a certain amount of data at the specified offset before
-/// returning.
-/**
- * This function is used to read a certain number of bytes of data from a
- * random access device at the specified offset. The call will block until one
- * of the following conditions is true:
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the SyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param b The basic_streambuf object into which the data will be read.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest read_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the device's read_some_at function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes read. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncRandomAccessReadDevice, typename Allocator,
-    typename CompletionCondition>
-std::size_t read_at(SyncRandomAccessReadDevice& d,
-    uint64_t offset, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition, asio::error_code& ec);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-/**
- * @defgroup async_read_at asio::async_read_at
- *
- * @brief Start an asynchronous operation to read a certain amount of data at
- * the specified offset.
- */
-/*@{*/
-
-/// Start an asynchronous operation to read a certain amount of data at the
-/// specified offset.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a random access device at the specified offset. The function call
- * always returns immediately. The asynchronous operation will continue until
- * one of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * async_read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the AsyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * device. Although the buffers object may be copied as necessary, ownership of
- * the underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes copied into the buffers. If an error
- *   // occurred, this will be the number of bytes successfully
- *   // transferred prior to the error.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code
- * asio::async_read_at(d, 42, asio::buffer(data, size), handler);
- * @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::async_read_at(
- *     d, 42, buffers,
- *     asio::transfer_all(),
- *     handler); @endcode
- */
-template <typename AsyncRandomAccessReadDevice, typename MutableBufferSequence,
-    typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_at(AsyncRandomAccessReadDevice& d, uint64_t offset,
-    const MutableBufferSequence& buffers,
-    ASIO_MOVE_ARG(ReadHandler) handler);
-
-/// Start an asynchronous operation to read a certain amount of data at the
-/// specified offset.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a random access device at the specified offset. The function call
- * always returns immediately. The asynchronous operation will continue until
- * one of the following conditions is true:
- *
- * @li The supplied buffers are full. That is, the bytes transferred is equal to
- * the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * @param d The device from which the data is to be read. The type must support
- * the AsyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param buffers One or more buffers into which the data will be read. The sum
- * of the buffer sizes indicates the maximum number of bytes to read from the
- * device. Although the buffers object may be copied as necessary, ownership of
- * the underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_read_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the device's async_read_some_at function.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes copied into the buffers. If an error
- *   // occurred, this will be the number of bytes successfully
- *   // transferred prior to the error.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * To read into a single data buffer use the @ref buffer function as follows:
- * @code asio::async_read_at(d, 42,
- *     asio::buffer(data, size),
- *     asio::transfer_at_least(32),
- *     handler); @endcode
- * See the @ref buffer documentation for information on reading into multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename AsyncRandomAccessReadDevice, typename MutableBufferSequence,
-    typename CompletionCondition, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_at(AsyncRandomAccessReadDevice& d,
-    uint64_t offset, const MutableBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Start an asynchronous operation to read a certain amount of data at the
-/// specified offset.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a random access device at the specified offset. The function call
- * always returns immediately. The asynchronous operation will continue until
- * one of the following conditions is true:
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * async_read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the AsyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param b A basic_streambuf object into which the data will be read. Ownership
- * of the streambuf is retained by the caller, which must guarantee that it
- * remains valid until the handler is called.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes copied into the buffers. If an error
- *   // occurred, this will be the number of bytes successfully
- *   // transferred prior to the error.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note This overload is equivalent to calling:
- * @code asio::async_read_at(
- *     d, 42, b,
- *     asio::transfer_all(),
- *     handler); @endcode
- */
-template <typename AsyncRandomAccessReadDevice, typename Allocator,
-    typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_at(AsyncRandomAccessReadDevice& d, uint64_t offset,
-    basic_streambuf<Allocator>& b, ASIO_MOVE_ARG(ReadHandler) handler);
-
-/// Start an asynchronous operation to read a certain amount of data at the
-/// specified offset.
-/**
- * This function is used to asynchronously read a certain number of bytes of
- * data from a random access device at the specified offset. The function call
- * always returns immediately. The asynchronous operation will continue until
- * one of the following conditions is true:
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * async_read_some_at function.
- *
- * @param d The device from which the data is to be read. The type must support
- * the AsyncRandomAccessReadDevice concept.
- *
- * @param offset The offset at which the data will be read.
- *
- * @param b A basic_streambuf object into which the data will be read. Ownership
- * of the streambuf is retained by the caller, which must guarantee that it
- * remains valid until the handler is called.
- *
- * @param completion_condition The function object to be called to determine
- * whether the read operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_read_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the read operation is complete. A non-zero
- * return value indicates the maximum number of bytes to be read on the next
- * call to the device's async_read_some_at function.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes copied into the buffers. If an error
- *   // occurred, this will be the number of bytes successfully
- *   // transferred prior to the error.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- */
-template <typename AsyncRandomAccessReadDevice, typename Allocator,
-    typename CompletionCondition, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_at(AsyncRandomAccessReadDevice& d,
-    uint64_t offset, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(ReadHandler) handler);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/read_at.hpp"
-
-#endif // ASIO_READ_AT_HPP
diff --git a/tools/sdk/include/asio/asio/read_until.hpp b/tools/sdk/include/asio/asio/read_until.hpp
deleted file mode 100644
index f413d987d0f..00000000000
--- a/tools/sdk/include/asio/asio/read_until.hpp
+++ /dev/null
@@ -1,1824 +0,0 @@
-//
-// read_until.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_READ_UNTIL_HPP
-#define ASIO_READ_UNTIL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include <string>
-#include "asio/async_result.hpp"
-#include "asio/detail/regex_fwd.hpp"
-#include "asio/detail/string_view.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-
-#if !defined(ASIO_NO_EXTENSIONS)
-# include "asio/basic_streambuf_fwd.hpp"
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-namespace detail
-{
-  char (&has_result_type_helper(...))[2];
-
-  template <typename T>
-  char has_result_type_helper(T*, typename T::result_type* = 0);
-
-  template <typename T>
-  struct has_result_type
-  {
-    enum { value = (sizeof((has_result_type_helper)((T*)(0))) == 1) };
-  };
-} // namespace detail
-
-/// Type trait used to determine whether a type can be used as a match condition
-/// function with read_until and async_read_until.
-template <typename T>
-struct is_match_condition
-{
-#if defined(GENERATING_DOCUMENTATION)
-  /// The value member is true if the type may be used as a match condition.
-  static const bool value;
-#else
-  enum
-  {
-    value = asio::is_function<
-        typename asio::remove_pointer<T>::type>::value
-      || detail::has_result_type<T>::value
-  };
-#endif
-};
-
-/**
- * @defgroup read_until asio::read_until
- *
- * @brief Read data into a dynamic buffer sequence, or into a streambuf, until
- * it contains a delimiter, matches a regular expression, or a function object
- * indicates a match.
- */
-/*@{*/
-
-/// Read data into a dynamic buffer sequence until it contains a specified
-/// delimiter.
-/**
- * This function is used to read data into the specified dynamic buffer
- * sequence until the dynamic buffer sequence's get area contains the specified
- * delimiter. The call will block until one of the following conditions is
- * true:
- *
- * @li The get area of the dynamic buffer sequence contains the specified
- * delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the dynamic buffer sequence's get area already
- * contains the delimiter, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- *
- * @param delim The delimiter character.
- *
- * @returns The number of bytes in the dynamic buffer sequence's get area up to
- * and including the delimiter.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note After a successful read_until operation, the dynamic buffer sequence
- * may contain additional data beyond the delimiter. An application will
- * typically leave that data in the dynamic buffer sequence for a subsequent
- * read_until operation to examine.
- *
- * @par Example
- * To read data into a @c std::string until a newline is encountered:
- * @code std::string data;
- * std::string n = asio::read_until(s,
- *     asio::dynamic_buffer(data), '\n');
- * std::string line = data.substr(0, n);
- * data.erase(0, n); @endcode
- * After the @c read_until operation completes successfully, the string @c data
- * contains the delimiter:
- * @code { 'a', 'b', ..., 'c', '\n', 'd', 'e', ... } @endcode
- * The call to @c substr then extracts the data up to and including the
- * delimiter, so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\n' } @endcode
- * After the call to @c erase, the remaining data is left in the buffer @c b as
- * follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c read_until operation.
- */
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers, char delim);
-
-/// Read data into a dynamic buffer sequence until it contains a specified
-/// delimiter.
-/**
- * This function is used to read data into the specified dynamic buffer
- * sequence until the dynamic buffer sequence's get area contains the specified
- * delimiter. The call will block until one of the following conditions is
- * true:
- *
- * @li The get area of the dynamic buffer sequence contains the specified
- * delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the dynamic buffer sequence's get area already
- * contains the delimiter, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- *
- * @param delim The delimiter character.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes in the dynamic buffer sequence's get area up to
- * and including the delimiter. Returns 0 if an error occurred.
- *
- * @note After a successful read_until operation, the dynamic buffer sequence
- * may contain additional data beyond the delimiter. An application will
- * typically leave that data in the dynamic buffer sequence for a subsequent
- * read_until operation to examine.
- */
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    char delim, asio::error_code& ec);
-
-/// Read data into a dynamic buffer sequence until it contains a specified
-/// delimiter.
-/**
- * This function is used to read data into the specified dynamic buffer
- * sequence until the dynamic buffer sequence's get area contains the specified
- * delimiter. The call will block until one of the following conditions is
- * true:
- *
- * @li The get area of the dynamic buffer sequence contains the specified
- * delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the dynamic buffer sequence's get area already
- * contains the delimiter, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- *
- * @param delim The delimiter string.
- *
- * @returns The number of bytes in the dynamic buffer sequence's get area up to
- * and including the delimiter.
- *
- * @note After a successful read_until operation, the dynamic buffer sequence
- * may contain additional data beyond the delimiter. An application will
- * typically leave that data in the dynamic buffer sequence for a subsequent
- * read_until operation to examine.
- *
- * @par Example
- * To read data into a @c std::string until a CR-LF sequence is encountered:
- * @code std::string data;
- * std::string n = asio::read_until(s,
- *     asio::dynamic_buffer(data), "\r\n");
- * std::string line = data.substr(0, n);
- * data.erase(0, n); @endcode
- * After the @c read_until operation completes successfully, the string @c data
- * contains the delimiter:
- * @code { 'a', 'b', ..., 'c', '\r', '\n', 'd', 'e', ... } @endcode
- * The call to @c substr then extracts the data up to and including the
- * delimiter, so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\r', '\n' } @endcode
- * After the call to @c erase, the remaining data is left in the buffer @c b as
- * follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c read_until operation.
- */
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_STRING_VIEW_PARAM delim);
-
-/// Read data into a dynamic buffer sequence until it contains a specified
-/// delimiter.
-/**
- * This function is used to read data into the specified dynamic buffer
- * sequence until the dynamic buffer sequence's get area contains the specified
- * delimiter. The call will block until one of the following conditions is
- * true:
- *
- * @li The get area of the dynamic buffer sequence contains the specified
- * delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the dynamic buffer sequence's get area already
- * contains the delimiter, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- *
- * @param delim The delimiter string.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes in the dynamic buffer sequence's get area up to
- * and including the delimiter. Returns 0 if an error occurred.
- *
- * @note After a successful read_until operation, the dynamic buffer sequence
- * may contain additional data beyond the delimiter. An application will
- * typically leave that data in the dynamic buffer sequence for a subsequent
- * read_until operation to examine.
- */
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_STRING_VIEW_PARAM delim,
-    asio::error_code& ec);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if defined(ASIO_HAS_BOOST_REGEX) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Read data into a dynamic buffer sequence until some part of the data it
-/// contains matches a regular expression.
-/**
- * This function is used to read data into the specified dynamic buffer
- * sequence until the dynamic buffer sequence's get area contains some data
- * that matches a regular expression. The call will block until one of the
- * following conditions is true:
- *
- * @li A substring of the dynamic buffer sequence's get area matches the
- * regular expression.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the dynamic buffer sequence's get area already
- * contains data that matches the regular expression, the function returns
- * immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers A dynamic buffer sequence into which the data will be read.
- *
- * @param expr The regular expression.
- *
- * @returns The number of bytes in the dynamic buffer sequence's get area up to
- * and including the substring that matches the regular expression.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note After a successful read_until operation, the dynamic buffer sequence
- * may contain additional data beyond that which matched the regular
- * expression. An application will typically leave that data in the dynamic
- * buffer sequence for a subsequent read_until operation to examine.
- *
- * @par Example
- * To read data into a @c std::string until a CR-LF sequence is encountered:
- * @code std::string data;
- * std::string n = asio::read_until(s,
- *     asio::dynamic_buffer(data), boost::regex("\r\n"));
- * std::string line = data.substr(0, n);
- * data.erase(0, n); @endcode
- * After the @c read_until operation completes successfully, the string @c data
- * contains the delimiter:
- * @code { 'a', 'b', ..., 'c', '\r', '\n', 'd', 'e', ... } @endcode
- * The call to @c substr then extracts the data up to and including the
- * delimiter, so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\r', '\n' } @endcode
- * After the call to @c erase, the remaining data is left in the buffer @c b as
- * follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c read_until operation.
- */
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    const boost::regex& expr);
-
-/// Read data into a dynamic buffer sequence until some part of the data it
-/// contains matches a regular expression.
-/**
- * This function is used to read data into the specified dynamic buffer
- * sequence until the dynamic buffer sequence's get area contains some data
- * that matches a regular expression. The call will block until one of the
- * following conditions is true:
- *
- * @li A substring of the dynamic buffer sequence's get area matches the
- * regular expression.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the dynamic buffer sequence's get area already
- * contains data that matches the regular expression, the function returns
- * immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers A dynamic buffer sequence into which the data will be read.
- *
- * @param expr The regular expression.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes in the dynamic buffer sequence's get area up to
- * and including the substring that matches the regular expression. Returns 0
- * if an error occurred.
- *
- * @note After a successful read_until operation, the dynamic buffer sequence
- * may contain additional data beyond that which matched the regular
- * expression. An application will typically leave that data in the dynamic
- * buffer sequence for a subsequent read_until operation to examine.
- */
-template <typename SyncReadStream, typename DynamicBuffer>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    const boost::regex& expr, asio::error_code& ec);
-
-#endif // defined(ASIO_HAS_BOOST_REGEX)
-       // || defined(GENERATING_DOCUMENTATION)
-
-/// Read data into a dynamic buffer sequence until a function object indicates a
-/// match.
-
-/**
- * This function is used to read data into the specified dynamic buffer
- * sequence until a user-defined match condition function object, when applied
- * to the data contained in the dynamic buffer sequence, indicates a successful
- * match. The call will block until one of the following conditions is true:
- *
- * @li The match condition function object returns a std::pair where the second
- * element evaluates to true.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the match condition function object already indicates
- * a match, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers A dynamic buffer sequence into which the data will be read.
- *
- * @param match_condition The function object to be called to determine whether
- * a match exists. The signature of the function object must be:
- * @code pair<iterator, bool> match_condition(iterator begin, iterator end);
- * @endcode
- * where @c iterator represents the type:
- * @code buffers_iterator<typename DynamicBuffer::const_buffers_type>
- * @endcode
- * The iterator parameters @c begin and @c end define the range of bytes to be
- * scanned to determine whether there is a match. The @c first member of the
- * return value is an iterator marking one-past-the-end of the bytes that have
- * been consumed by the match function. This iterator is used to calculate the
- * @c begin parameter for any subsequent invocation of the match condition. The
- * @c second member of the return value is true if a match has been found, false
- * otherwise.
- *
- * @returns The number of bytes in the dynamic_buffer's get area that
- * have been fully consumed by the match function.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note After a successful read_until operation, the dynamic buffer sequence
- * may contain additional data beyond that which matched the function object.
- * An application will typically leave that data in the dynamic buffer sequence
- * for a subsequent read_until operation to examine.
-
- * @note The default implementation of the @c is_match_condition type trait
- * evaluates to true for function pointers and function objects with a
- * @c result_type typedef. It must be specialised for other user-defined
- * function objects.
- *
- * @par Examples
- * To read data into a dynamic buffer sequence until whitespace is encountered:
- * @code typedef asio::buffers_iterator<
- *     asio::const_buffers_1> iterator;
- *
- * std::pair<iterator, bool>
- * match_whitespace(iterator begin, iterator end)
- * {
- *   iterator i = begin;
- *   while (i != end)
- *     if (std::isspace(*i++))
- *       return std::make_pair(i, true);
- *   return std::make_pair(i, false);
- * }
- * ...
- * std::string data;
- * asio::read_until(s, data, match_whitespace);
- * @endcode
- *
- * To read data into a @c std::string until a matching character is found:
- * @code class match_char
- * {
- * public:
- *   explicit match_char(char c) : c_(c) {}
- *
- *   template <typename Iterator>
- *   std::pair<Iterator, bool> operator()(
- *       Iterator begin, Iterator end) const
- *   {
- *     Iterator i = begin;
- *     while (i != end)
- *       if (c_ == *i++)
- *         return std::make_pair(i, true);
- *     return std::make_pair(i, false);
- *   }
- *
- * private:
- *   char c_;
- * };
- *
- * namespace asio {
- *   template <> struct is_match_condition<match_char>
- *     : public boost::true_type {};
- * } // namespace asio
- * ...
- * std::string data;
- * asio::read_until(s, data, match_char('a'));
- * @endcode
- */
-template <typename SyncReadStream,
-    typename DynamicBuffer, typename MatchCondition>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    MatchCondition match_condition,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type* = 0);
-
-/// Read data into a dynamic buffer sequence until a function object indicates a
-/// match.
-/**
- * This function is used to read data into the specified dynamic buffer
- * sequence until a user-defined match condition function object, when applied
- * to the data contained in the dynamic buffer sequence, indicates a successful
- * match. The call will block until one of the following conditions is true:
- *
- * @li The match condition function object returns a std::pair where the second
- * element evaluates to true.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the match condition function object already indicates
- * a match, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param buffers A dynamic buffer sequence into which the data will be read.
- *
- * @param match_condition The function object to be called to determine whether
- * a match exists. The signature of the function object must be:
- * @code pair<iterator, bool> match_condition(iterator begin, iterator end);
- * @endcode
- * where @c iterator represents the type:
- * @code buffers_iterator<DynamicBuffer::const_buffers_type>
- * @endcode
- * The iterator parameters @c begin and @c end define the range of bytes to be
- * scanned to determine whether there is a match. The @c first member of the
- * return value is an iterator marking one-past-the-end of the bytes that have
- * been consumed by the match function. This iterator is used to calculate the
- * @c begin parameter for any subsequent invocation of the match condition. The
- * @c second member of the return value is true if a match has been found, false
- * otherwise.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes in the dynamic buffer sequence's get area that
- * have been fully consumed by the match function. Returns 0 if an error
- * occurred.
- *
- * @note After a successful read_until operation, the dynamic buffer sequence
- * may contain additional data beyond that which matched the function object.
- * An application will typically leave that data in the dynamic buffer sequence
- * for a subsequent read_until operation to examine.
- *
- * @note The default implementation of the @c is_match_condition type trait
- * evaluates to true for function pointers and function objects with a
- * @c result_type typedef. It must be specialised for other user-defined
- * function objects.
- */
-template <typename SyncReadStream,
-    typename DynamicBuffer, typename MatchCondition>
-std::size_t read_until(SyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    MatchCondition match_condition, asio::error_code& ec,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type* = 0);
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Read data into a streambuf until it contains a specified delimiter.
-/**
- * This function is used to read data into the specified streambuf until the
- * streambuf's get area contains the specified delimiter. The call will block
- * until one of the following conditions is true:
- *
- * @li The get area of the streambuf contains the specified delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the streambuf's get area already contains the
- * delimiter, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read.
- *
- * @param delim The delimiter character.
- *
- * @returns The number of bytes in the streambuf's get area up to and including
- * the delimiter.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note After a successful read_until operation, the streambuf may contain
- * additional data beyond the delimiter. An application will typically leave
- * that data in the streambuf for a subsequent read_until operation to examine.
- *
- * @par Example
- * To read data into a streambuf until a newline is encountered:
- * @code asio::streambuf b;
- * asio::read_until(s, b, '\n');
- * std::istream is(&b);
- * std::string line;
- * std::getline(is, line); @endcode
- * After the @c read_until operation completes successfully, the buffer @c b
- * contains the delimiter:
- * @code { 'a', 'b', ..., 'c', '\n', 'd', 'e', ... } @endcode
- * The call to @c std::getline then extracts the data up to and including the
- * newline (which is discarded), so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c' } @endcode
- * The remaining data is left in the buffer @c b as follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c read_until operation.
- */
-template <typename SyncReadStream, typename Allocator>
-std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, char delim);
-
-/// Read data into a streambuf until it contains a specified delimiter.
-/**
- * This function is used to read data into the specified streambuf until the
- * streambuf's get area contains the specified delimiter. The call will block
- * until one of the following conditions is true:
- *
- * @li The get area of the streambuf contains the specified delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the streambuf's get area already contains the
- * delimiter, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read.
- *
- * @param delim The delimiter character.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes in the streambuf's get area up to and including
- * the delimiter. Returns 0 if an error occurred.
- *
- * @note After a successful read_until operation, the streambuf may contain
- * additional data beyond the delimiter. An application will typically leave
- * that data in the streambuf for a subsequent read_until operation to examine.
- */
-template <typename SyncReadStream, typename Allocator>
-std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, char delim,
-    asio::error_code& ec);
-
-/// Read data into a streambuf until it contains a specified delimiter.
-/**
- * This function is used to read data into the specified streambuf until the
- * streambuf's get area contains the specified delimiter. The call will block
- * until one of the following conditions is true:
- *
- * @li The get area of the streambuf contains the specified delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the streambuf's get area already contains the
- * delimiter, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read.
- *
- * @param delim The delimiter string.
- *
- * @returns The number of bytes in the streambuf's get area up to and including
- * the delimiter.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note After a successful read_until operation, the streambuf may contain
- * additional data beyond the delimiter. An application will typically leave
- * that data in the streambuf for a subsequent read_until operation to examine.
- *
- * @par Example
- * To read data into a streambuf until a newline is encountered:
- * @code asio::streambuf b;
- * asio::read_until(s, b, "\r\n");
- * std::istream is(&b);
- * std::string line;
- * std::getline(is, line); @endcode
- * After the @c read_until operation completes successfully, the buffer @c b
- * contains the delimiter:
- * @code { 'a', 'b', ..., 'c', '\r', '\n', 'd', 'e', ... } @endcode
- * The call to @c std::getline then extracts the data up to and including the
- * newline (which is discarded), so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\r' } @endcode
- * The remaining data is left in the buffer @c b as follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c read_until operation.
- */
-template <typename SyncReadStream, typename Allocator>
-std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    ASIO_STRING_VIEW_PARAM delim);
-
-/// Read data into a streambuf until it contains a specified delimiter.
-/**
- * This function is used to read data into the specified streambuf until the
- * streambuf's get area contains the specified delimiter. The call will block
- * until one of the following conditions is true:
- *
- * @li The get area of the streambuf contains the specified delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the streambuf's get area already contains the
- * delimiter, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read.
- *
- * @param delim The delimiter string.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes in the streambuf's get area up to and including
- * the delimiter. Returns 0 if an error occurred.
- *
- * @note After a successful read_until operation, the streambuf may contain
- * additional data beyond the delimiter. An application will typically leave
- * that data in the streambuf for a subsequent read_until operation to examine.
- */
-template <typename SyncReadStream, typename Allocator>
-std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    ASIO_STRING_VIEW_PARAM delim, asio::error_code& ec);
-
-#if defined(ASIO_HAS_BOOST_REGEX) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Read data into a streambuf until some part of the data it contains matches
-/// a regular expression.
-/**
- * This function is used to read data into the specified streambuf until the
- * streambuf's get area contains some data that matches a regular expression.
- * The call will block until one of the following conditions is true:
- *
- * @li A substring of the streambuf's get area matches the regular expression.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the streambuf's get area already contains data that
- * matches the regular expression, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read.
- *
- * @param expr The regular expression.
- *
- * @returns The number of bytes in the streambuf's get area up to and including
- * the substring that matches the regular expression.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note After a successful read_until operation, the streambuf may contain
- * additional data beyond that which matched the regular expression. An
- * application will typically leave that data in the streambuf for a subsequent
- * read_until operation to examine.
- *
- * @par Example
- * To read data into a streambuf until a CR-LF sequence is encountered:
- * @code asio::streambuf b;
- * asio::read_until(s, b, boost::regex("\r\n"));
- * std::istream is(&b);
- * std::string line;
- * std::getline(is, line); @endcode
- * After the @c read_until operation completes successfully, the buffer @c b
- * contains the data which matched the regular expression:
- * @code { 'a', 'b', ..., 'c', '\r', '\n', 'd', 'e', ... } @endcode
- * The call to @c std::getline then extracts the data up to and including the
- * newline (which is discarded), so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\r' } @endcode
- * The remaining data is left in the buffer @c b as follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c read_until operation.
- */
-template <typename SyncReadStream, typename Allocator>
-std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, const boost::regex& expr);
-
-/// Read data into a streambuf until some part of the data it contains matches
-/// a regular expression.
-/**
- * This function is used to read data into the specified streambuf until the
- * streambuf's get area contains some data that matches a regular expression.
- * The call will block until one of the following conditions is true:
- *
- * @li A substring of the streambuf's get area matches the regular expression.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the streambuf's get area already contains data that
- * matches the regular expression, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read.
- *
- * @param expr The regular expression.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes in the streambuf's get area up to and including
- * the substring that matches the regular expression. Returns 0 if an error
- * occurred.
- *
- * @note After a successful read_until operation, the streambuf may contain
- * additional data beyond that which matched the regular expression. An
- * application will typically leave that data in the streambuf for a subsequent
- * read_until operation to examine.
- */
-template <typename SyncReadStream, typename Allocator>
-std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, const boost::regex& expr,
-    asio::error_code& ec);
-
-#endif // defined(ASIO_HAS_BOOST_REGEX)
-       // || defined(GENERATING_DOCUMENTATION)
-
-/// Read data into a streambuf until a function object indicates a match.
-/**
- * This function is used to read data into the specified streambuf until a
- * user-defined match condition function object, when applied to the data
- * contained in the streambuf, indicates a successful match. The call will
- * block until one of the following conditions is true:
- *
- * @li The match condition function object returns a std::pair where the second
- * element evaluates to true.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the match condition function object already indicates
- * a match, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read.
- *
- * @param match_condition The function object to be called to determine whether
- * a match exists. The signature of the function object must be:
- * @code pair<iterator, bool> match_condition(iterator begin, iterator end);
- * @endcode
- * where @c iterator represents the type:
- * @code buffers_iterator<basic_streambuf<Allocator>::const_buffers_type>
- * @endcode
- * The iterator parameters @c begin and @c end define the range of bytes to be
- * scanned to determine whether there is a match. The @c first member of the
- * return value is an iterator marking one-past-the-end of the bytes that have
- * been consumed by the match function. This iterator is used to calculate the
- * @c begin parameter for any subsequent invocation of the match condition. The
- * @c second member of the return value is true if a match has been found, false
- * otherwise.
- *
- * @returns The number of bytes in the streambuf's get area that have been fully
- * consumed by the match function.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note After a successful read_until operation, the streambuf may contain
- * additional data beyond that which matched the function object. An application
- * will typically leave that data in the streambuf for a subsequent read_until
- * operation to examine.
- *
- * @note The default implementation of the @c is_match_condition type trait
- * evaluates to true for function pointers and function objects with a
- * @c result_type typedef. It must be specialised for other user-defined
- * function objects.
- *
- * @par Examples
- * To read data into a streambuf until whitespace is encountered:
- * @code typedef asio::buffers_iterator<
- *     asio::streambuf::const_buffers_type> iterator;
- *
- * std::pair<iterator, bool>
- * match_whitespace(iterator begin, iterator end)
- * {
- *   iterator i = begin;
- *   while (i != end)
- *     if (std::isspace(*i++))
- *       return std::make_pair(i, true);
- *   return std::make_pair(i, false);
- * }
- * ...
- * asio::streambuf b;
- * asio::read_until(s, b, match_whitespace);
- * @endcode
- *
- * To read data into a streambuf until a matching character is found:
- * @code class match_char
- * {
- * public:
- *   explicit match_char(char c) : c_(c) {}
- *
- *   template <typename Iterator>
- *   std::pair<Iterator, bool> operator()(
- *       Iterator begin, Iterator end) const
- *   {
- *     Iterator i = begin;
- *     while (i != end)
- *       if (c_ == *i++)
- *         return std::make_pair(i, true);
- *     return std::make_pair(i, false);
- *   }
- *
- * private:
- *   char c_;
- * };
- *
- * namespace asio {
- *   template <> struct is_match_condition<match_char>
- *     : public boost::true_type {};
- * } // namespace asio
- * ...
- * asio::streambuf b;
- * asio::read_until(s, b, match_char('a'));
- * @endcode
- */
-template <typename SyncReadStream, typename Allocator, typename MatchCondition>
-std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, MatchCondition match_condition,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type* = 0);
-
-/// Read data into a streambuf until a function object indicates a match.
-/**
- * This function is used to read data into the specified streambuf until a
- * user-defined match condition function object, when applied to the data
- * contained in the streambuf, indicates a successful match. The call will
- * block until one of the following conditions is true:
- *
- * @li The match condition function object returns a std::pair where the second
- * element evaluates to true.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * read_some function. If the match condition function object already indicates
- * a match, the function returns immediately.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the SyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read.
- *
- * @param match_condition The function object to be called to determine whether
- * a match exists. The signature of the function object must be:
- * @code pair<iterator, bool> match_condition(iterator begin, iterator end);
- * @endcode
- * where @c iterator represents the type:
- * @code buffers_iterator<basic_streambuf<Allocator>::const_buffers_type>
- * @endcode
- * The iterator parameters @c begin and @c end define the range of bytes to be
- * scanned to determine whether there is a match. The @c first member of the
- * return value is an iterator marking one-past-the-end of the bytes that have
- * been consumed by the match function. This iterator is used to calculate the
- * @c begin parameter for any subsequent invocation of the match condition. The
- * @c second member of the return value is true if a match has been found, false
- * otherwise.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes in the streambuf's get area that have been fully
- * consumed by the match function. Returns 0 if an error occurred.
- *
- * @note After a successful read_until operation, the streambuf may contain
- * additional data beyond that which matched the function object. An application
- * will typically leave that data in the streambuf for a subsequent read_until
- * operation to examine.
- *
- * @note The default implementation of the @c is_match_condition type trait
- * evaluates to true for function pointers and function objects with a
- * @c result_type typedef. It must be specialised for other user-defined
- * function objects.
- */
-template <typename SyncReadStream, typename Allocator, typename MatchCondition>
-std::size_t read_until(SyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    MatchCondition match_condition, asio::error_code& ec,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type* = 0);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-/**
- * @defgroup async_read_until asio::async_read_until
- *
- * @brief Start an asynchronous operation to read data into a dynamic buffer
- * sequence, or into a streambuf, until it contains a delimiter, matches a
- * regular expression, or a function object indicates a match.
- */
-/*@{*/
-
-/// Start an asynchronous operation to read data into a dynamic buffer sequence
-/// until it contains a specified delimiter.
-/**
- * This function is used to asynchronously read data into the specified dynamic
- * buffer sequence until the dynamic buffer sequence's get area contains the
- * specified delimiter. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li The get area of the dynamic buffer sequence contains the specified
- * delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. If
- * the dynamic buffer sequence's get area already contains the delimiter, this
- * asynchronous operation completes immediately. The program must ensure that
- * the stream performs no other read operations (such as async_read,
- * async_read_until, the stream's async_read_some function, or any other
- * composed operations that perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param delim The delimiter character.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // The number of bytes in the dynamic buffer sequence's
- *   // get area up to and including the delimiter.
- *   // 0 if an error occurred.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note After a successful async_read_until operation, the dynamic buffer
- * sequence may contain additional data beyond the delimiter. An application
- * will typically leave that data in the dynamic buffer sequence for a
- * subsequent async_read_until operation to examine.
- *
- * @par Example
- * To asynchronously read data into a @c std::string until a newline is
- * encountered:
- * @code std::string data;
- * ...
- * void handler(const asio::error_code& e, std::size_t size)
- * {
- *   if (!e)
- *   {
- *     std::string line = data.substr(0, n);
- *     data.erase(0, n);
- *     ...
- *   }
- * }
- * ...
- * asio::async_read_until(s, data, '\n', handler); @endcode
- * After the @c async_read_until operation completes successfully, the buffer
- * @c data contains the delimiter:
- * @code { 'a', 'b', ..., 'c', '\n', 'd', 'e', ... } @endcode
- * The call to @c substr then extracts the data up to and including the
- * delimiter, so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\n' } @endcode
- * After the call to @c erase, the remaining data is left in the buffer @c data
- * as follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c async_read_until operation.
- */
-template <typename AsyncReadStream,
-    typename DynamicBuffer, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    char delim, ASIO_MOVE_ARG(ReadHandler) handler);
-
-/// Start an asynchronous operation to read data into a dynamic buffer sequence
-/// until it contains a specified delimiter.
-/**
- * This function is used to asynchronously read data into the specified dynamic
- * buffer sequence until the dynamic buffer sequence's get area contains the
- * specified delimiter. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li The get area of the dynamic buffer sequence contains the specified
- * delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. If
- * the dynamic buffer sequence's get area already contains the delimiter, this
- * asynchronous operation completes immediately. The program must ensure that
- * the stream performs no other read operations (such as async_read,
- * async_read_until, the stream's async_read_some function, or any other
- * composed operations that perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param delim The delimiter string.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // The number of bytes in the dynamic buffer sequence's
- *   // get area up to and including the delimiter.
- *   // 0 if an error occurred.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note After a successful async_read_until operation, the dynamic buffer
- * sequence may contain additional data beyond the delimiter. An application
- * will typically leave that data in the dynamic buffer sequence for a
- * subsequent async_read_until operation to examine.
- *
- * @par Example
- * To asynchronously read data into a @c std::string until a CR-LF sequence is
- * encountered:
- * @code std::string data;
- * ...
- * void handler(const asio::error_code& e, std::size_t size)
- * {
- *   if (!e)
- *   {
- *     std::string line = data.substr(0, n);
- *     data.erase(0, n);
- *     ...
- *   }
- * }
- * ...
- * asio::async_read_until(s, data, "\r\n", handler); @endcode
- * After the @c async_read_until operation completes successfully, the string
- * @c data contains the delimiter:
- * @code { 'a', 'b', ..., 'c', '\r', '\n', 'd', 'e', ... } @endcode
- * The call to @c substr then extracts the data up to and including the
- * delimiter, so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\r', '\n' } @endcode
- * After the call to @c erase, the remaining data is left in the string @c data
- * as follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c async_read_until operation.
- */
-template <typename AsyncReadStream,
-    typename DynamicBuffer, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_STRING_VIEW_PARAM delim,
-    ASIO_MOVE_ARG(ReadHandler) handler);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if defined(ASIO_HAS_BOOST_REGEX) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Start an asynchronous operation to read data into a dynamic buffer sequence
-/// until some part of its data matches a regular expression.
-/**
- * This function is used to asynchronously read data into the specified dynamic
- * buffer sequence until the dynamic buffer sequence's get area contains some
- * data that matches a regular expression. The function call always returns
- * immediately. The asynchronous operation will continue until one of the
- * following conditions is true:
- *
- * @li A substring of the dynamic buffer sequence's get area matches the regular
- * expression.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. If
- * the dynamic buffer sequence's get area already contains data that matches
- * the regular expression, this asynchronous operation completes immediately.
- * The program must ensure that the stream performs no other read operations
- * (such as async_read, async_read_until, the stream's async_read_some
- * function, or any other composed operations that perform reads) until this
- * operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param expr The regular expression.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // The number of bytes in the dynamic buffer
- *   // sequence's get area up to and including the
- *   // substring that matches the regular expression.
- *   // 0 if an error occurred.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note After a successful async_read_until operation, the dynamic buffer
- * sequence may contain additional data beyond that which matched the regular
- * expression. An application will typically leave that data in the dynamic
- * buffer sequence for a subsequent async_read_until operation to examine.
- *
- * @par Example
- * To asynchronously read data into a @c std::string until a CR-LF sequence is
- * encountered:
- * @code std::string data;
- * ...
- * void handler(const asio::error_code& e, std::size_t size)
- * {
- *   if (!e)
- *   {
- *     std::string line = data.substr(0, n);
- *     data.erase(0, n);
- *     ...
- *   }
- * }
- * ...
- * asio::async_read_until(s, data,
- *     boost::regex("\r\n"), handler); @endcode
- * After the @c async_read_until operation completes successfully, the string
- * @c data contains the data which matched the regular expression:
- * @code { 'a', 'b', ..., 'c', '\r', '\n', 'd', 'e', ... } @endcode
- * The call to @c substr then extracts the data up to and including the match,
- * so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\r', '\n' } @endcode
- * After the call to @c erase, the remaining data is left in the string @c data
- * as follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c async_read_until operation.
- */
-template <typename AsyncReadStream,
-    typename DynamicBuffer, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    const boost::regex& expr,
-    ASIO_MOVE_ARG(ReadHandler) handler);
-
-#endif // defined(ASIO_HAS_BOOST_REGEX)
-       // || defined(GENERATING_DOCUMENTATION)
-
-/// Start an asynchronous operation to read data into a dynamic buffer sequence
-/// until a function object indicates a match.
-/**
- * This function is used to asynchronously read data into the specified dynamic
- * buffer sequence until a user-defined match condition function object, when
- * applied to the data contained in the dynamic buffer sequence, indicates a
- * successful match. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li The match condition function object returns a std::pair where the second
- * element evaluates to true.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. If
- * the match condition function object already indicates a match, this
- * asynchronous operation completes immediately. The program must ensure that
- * the stream performs no other read operations (such as async_read,
- * async_read_until, the stream's async_read_some function, or any other
- * composed operations that perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param buffers The dynamic buffer sequence into which the data will be read.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param match_condition The function object to be called to determine whether
- * a match exists. The signature of the function object must be:
- * @code pair<iterator, bool> match_condition(iterator begin, iterator end);
- * @endcode
- * where @c iterator represents the type:
- * @code buffers_iterator<typename DynamicBuffer::const_buffers_type>
- * @endcode
- * The iterator parameters @c begin and @c end define the range of bytes to be
- * scanned to determine whether there is a match. The @c first member of the
- * return value is an iterator marking one-past-the-end of the bytes that have
- * been consumed by the match function. This iterator is used to calculate the
- * @c begin parameter for any subsequent invocation of the match condition. The
- * @c second member of the return value is true if a match has been found, false
- * otherwise.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // The number of bytes in the dynamic buffer sequence's
- *   // get area that have been fully consumed by the match
- *   // function. O if an error occurred.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note After a successful async_read_until operation, the dynamic buffer
- * sequence may contain additional data beyond that which matched the function
- * object. An application will typically leave that data in the dynamic buffer
- * sequence for a subsequent async_read_until operation to examine.
- *
- * @note The default implementation of the @c is_match_condition type trait
- * evaluates to true for function pointers and function objects with a
- * @c result_type typedef. It must be specialised for other user-defined
- * function objects.
- *
- * @par Examples
- * To asynchronously read data into a @c std::string until whitespace is
- * encountered:
- * @code typedef asio::buffers_iterator<
- *     asio::const_buffers_1> iterator;
- *
- * std::pair<iterator, bool>
- * match_whitespace(iterator begin, iterator end)
- * {
- *   iterator i = begin;
- *   while (i != end)
- *     if (std::isspace(*i++))
- *       return std::make_pair(i, true);
- *   return std::make_pair(i, false);
- * }
- * ...
- * void handler(const asio::error_code& e, std::size_t size);
- * ...
- * std::string data;
- * asio::async_read_until(s, data, match_whitespace, handler);
- * @endcode
- *
- * To asynchronously read data into a @c std::string until a matching character
- * is found:
- * @code class match_char
- * {
- * public:
- *   explicit match_char(char c) : c_(c) {}
- *
- *   template <typename Iterator>
- *   std::pair<Iterator, bool> operator()(
- *       Iterator begin, Iterator end) const
- *   {
- *     Iterator i = begin;
- *     while (i != end)
- *       if (c_ == *i++)
- *         return std::make_pair(i, true);
- *     return std::make_pair(i, false);
- *   }
- *
- * private:
- *   char c_;
- * };
- *
- * namespace asio {
- *   template <> struct is_match_condition<match_char>
- *     : public boost::true_type {};
- * } // namespace asio
- * ...
- * void handler(const asio::error_code& e, std::size_t size);
- * ...
- * std::string data;
- * asio::async_read_until(s, data, match_char('a'), handler);
- * @endcode
- */
-template <typename AsyncReadStream, typename DynamicBuffer,
-    typename MatchCondition, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    MatchCondition match_condition, ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type* = 0);
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Start an asynchronous operation to read data into a streambuf until it
-/// contains a specified delimiter.
-/**
- * This function is used to asynchronously read data into the specified
- * streambuf until the streambuf's get area contains the specified delimiter.
- * The function call always returns immediately. The asynchronous operation
- * will continue until one of the following conditions is true:
- *
- * @li The get area of the streambuf contains the specified delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. If
- * the streambuf's get area already contains the delimiter, this asynchronous
- * operation completes immediately. The program must ensure that the stream
- * performs no other read operations (such as async_read, async_read_until, the
- * stream's async_read_some function, or any other composed operations that
- * perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read. Ownership of
- * the streambuf is retained by the caller, which must guarantee that it remains
- * valid until the handler is called.
- *
- * @param delim The delimiter character.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // The number of bytes in the streambuf's get
- *   // area up to and including the delimiter.
- *   // 0 if an error occurred.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note After a successful async_read_until operation, the streambuf may
- * contain additional data beyond the delimiter. An application will typically
- * leave that data in the streambuf for a subsequent async_read_until operation
- * to examine.
- *
- * @par Example
- * To asynchronously read data into a streambuf until a newline is encountered:
- * @code asio::streambuf b;
- * ...
- * void handler(const asio::error_code& e, std::size_t size)
- * {
- *   if (!e)
- *   {
- *     std::istream is(&b);
- *     std::string line;
- *     std::getline(is, line);
- *     ...
- *   }
- * }
- * ...
- * asio::async_read_until(s, b, '\n', handler); @endcode
- * After the @c async_read_until operation completes successfully, the buffer
- * @c b contains the delimiter:
- * @code { 'a', 'b', ..., 'c', '\n', 'd', 'e', ... } @endcode
- * The call to @c std::getline then extracts the data up to and including the
- * newline (which is discarded), so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c' } @endcode
- * The remaining data is left in the buffer @c b as follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c async_read_until operation.
- */
-template <typename AsyncReadStream, typename Allocator, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    char delim, ASIO_MOVE_ARG(ReadHandler) handler);
-
-/// Start an asynchronous operation to read data into a streambuf until it
-/// contains a specified delimiter.
-/**
- * This function is used to asynchronously read data into the specified
- * streambuf until the streambuf's get area contains the specified delimiter.
- * The function call always returns immediately. The asynchronous operation
- * will continue until one of the following conditions is true:
- *
- * @li The get area of the streambuf contains the specified delimiter.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. If
- * the streambuf's get area already contains the delimiter, this asynchronous
- * operation completes immediately. The program must ensure that the stream
- * performs no other read operations (such as async_read, async_read_until, the
- * stream's async_read_some function, or any other composed operations that
- * perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read. Ownership of
- * the streambuf is retained by the caller, which must guarantee that it remains
- * valid until the handler is called.
- *
- * @param delim The delimiter string.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // The number of bytes in the streambuf's get
- *   // area up to and including the delimiter.
- *   // 0 if an error occurred.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note After a successful async_read_until operation, the streambuf may
- * contain additional data beyond the delimiter. An application will typically
- * leave that data in the streambuf for a subsequent async_read_until operation
- * to examine.
- *
- * @par Example
- * To asynchronously read data into a streambuf until a newline is encountered:
- * @code asio::streambuf b;
- * ...
- * void handler(const asio::error_code& e, std::size_t size)
- * {
- *   if (!e)
- *   {
- *     std::istream is(&b);
- *     std::string line;
- *     std::getline(is, line);
- *     ...
- *   }
- * }
- * ...
- * asio::async_read_until(s, b, "\r\n", handler); @endcode
- * After the @c async_read_until operation completes successfully, the buffer
- * @c b contains the delimiter:
- * @code { 'a', 'b', ..., 'c', '\r', '\n', 'd', 'e', ... } @endcode
- * The call to @c std::getline then extracts the data up to and including the
- * newline (which is discarded), so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\r' } @endcode
- * The remaining data is left in the buffer @c b as follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c async_read_until operation.
- */
-template <typename AsyncReadStream, typename Allocator, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    ASIO_STRING_VIEW_PARAM delim,
-    ASIO_MOVE_ARG(ReadHandler) handler);
-
-#if defined(ASIO_HAS_BOOST_REGEX) \
-  || defined(GENERATING_DOCUMENTATION)
-
-/// Start an asynchronous operation to read data into a streambuf until some
-/// part of its data matches a regular expression.
-/**
- * This function is used to asynchronously read data into the specified
- * streambuf until the streambuf's get area contains some data that matches a
- * regular expression. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li A substring of the streambuf's get area matches the regular expression.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. If
- * the streambuf's get area already contains data that matches the regular
- * expression, this asynchronous operation completes immediately. The program
- * must ensure that the stream performs no other read operations (such as
- * async_read, async_read_until, the stream's async_read_some function, or any
- * other composed operations that perform reads) until this operation
- * completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read. Ownership of
- * the streambuf is retained by the caller, which must guarantee that it remains
- * valid until the handler is called.
- *
- * @param expr The regular expression.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // The number of bytes in the streambuf's get
- *   // area up to and including the substring
- *   // that matches the regular. expression.
- *   // 0 if an error occurred.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note After a successful async_read_until operation, the streambuf may
- * contain additional data beyond that which matched the regular expression. An
- * application will typically leave that data in the streambuf for a subsequent
- * async_read_until operation to examine.
- *
- * @par Example
- * To asynchronously read data into a streambuf until a CR-LF sequence is
- * encountered:
- * @code asio::streambuf b;
- * ...
- * void handler(const asio::error_code& e, std::size_t size)
- * {
- *   if (!e)
- *   {
- *     std::istream is(&b);
- *     std::string line;
- *     std::getline(is, line);
- *     ...
- *   }
- * }
- * ...
- * asio::async_read_until(s, b, boost::regex("\r\n"), handler); @endcode
- * After the @c async_read_until operation completes successfully, the buffer
- * @c b contains the data which matched the regular expression:
- * @code { 'a', 'b', ..., 'c', '\r', '\n', 'd', 'e', ... } @endcode
- * The call to @c std::getline then extracts the data up to and including the
- * newline (which is discarded), so that the string @c line contains:
- * @code { 'a', 'b', ..., 'c', '\r' } @endcode
- * The remaining data is left in the buffer @c b as follows:
- * @code { 'd', 'e', ... } @endcode
- * This data may be the start of a new line, to be extracted by a subsequent
- * @c async_read_until operation.
- */
-template <typename AsyncReadStream, typename Allocator, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b, const boost::regex& expr,
-    ASIO_MOVE_ARG(ReadHandler) handler);
-
-#endif // defined(ASIO_HAS_BOOST_REGEX)
-       // || defined(GENERATING_DOCUMENTATION)
-
-/// Start an asynchronous operation to read data into a streambuf until a
-/// function object indicates a match.
-/**
- * This function is used to asynchronously read data into the specified
- * streambuf until a user-defined match condition function object, when applied
- * to the data contained in the streambuf, indicates a successful match. The
- * function call always returns immediately. The asynchronous operation will
- * continue until one of the following conditions is true:
- *
- * @li The match condition function object returns a std::pair where the second
- * element evaluates to true.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_read_some function, and is known as a <em>composed operation</em>. If
- * the match condition function object already indicates a match, this
- * asynchronous operation completes immediately. The program must ensure that
- * the stream performs no other read operations (such as async_read,
- * async_read_until, the stream's async_read_some function, or any other
- * composed operations that perform reads) until this operation completes.
- *
- * @param s The stream from which the data is to be read. The type must support
- * the AsyncReadStream concept.
- *
- * @param b A streambuf object into which the data will be read.
- *
- * @param match_condition The function object to be called to determine whether
- * a match exists. The signature of the function object must be:
- * @code pair<iterator, bool> match_condition(iterator begin, iterator end);
- * @endcode
- * where @c iterator represents the type:
- * @code buffers_iterator<basic_streambuf<Allocator>::const_buffers_type>
- * @endcode
- * The iterator parameters @c begin and @c end define the range of bytes to be
- * scanned to determine whether there is a match. The @c first member of the
- * return value is an iterator marking one-past-the-end of the bytes that have
- * been consumed by the match function. This iterator is used to calculate the
- * @c begin parameter for any subsequent invocation of the match condition. The
- * @c second member of the return value is true if a match has been found, false
- * otherwise.
- *
- * @param handler The handler to be called when the read operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // The number of bytes in the streambuf's get
- *   // area that have been fully consumed by the
- *   // match function. O if an error occurred.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @note After a successful async_read_until operation, the streambuf may
- * contain additional data beyond that which matched the function object. An
- * application will typically leave that data in the streambuf for a subsequent
- * async_read_until operation to examine.
- *
- * @note The default implementation of the @c is_match_condition type trait
- * evaluates to true for function pointers and function objects with a
- * @c result_type typedef. It must be specialised for other user-defined
- * function objects.
- *
- * @par Examples
- * To asynchronously read data into a streambuf until whitespace is encountered:
- * @code typedef asio::buffers_iterator<
- *     asio::streambuf::const_buffers_type> iterator;
- *
- * std::pair<iterator, bool>
- * match_whitespace(iterator begin, iterator end)
- * {
- *   iterator i = begin;
- *   while (i != end)
- *     if (std::isspace(*i++))
- *       return std::make_pair(i, true);
- *   return std::make_pair(i, false);
- * }
- * ...
- * void handler(const asio::error_code& e, std::size_t size);
- * ...
- * asio::streambuf b;
- * asio::async_read_until(s, b, match_whitespace, handler);
- * @endcode
- *
- * To asynchronously read data into a streambuf until a matching character is
- * found:
- * @code class match_char
- * {
- * public:
- *   explicit match_char(char c) : c_(c) {}
- *
- *   template <typename Iterator>
- *   std::pair<Iterator, bool> operator()(
- *       Iterator begin, Iterator end) const
- *   {
- *     Iterator i = begin;
- *     while (i != end)
- *       if (c_ == *i++)
- *         return std::make_pair(i, true);
- *     return std::make_pair(i, false);
- *   }
- *
- * private:
- *   char c_;
- * };
- *
- * namespace asio {
- *   template <> struct is_match_condition<match_char>
- *     : public boost::true_type {};
- * } // namespace asio
- * ...
- * void handler(const asio::error_code& e, std::size_t size);
- * ...
- * asio::streambuf b;
- * asio::async_read_until(s, b, match_char('a'), handler);
- * @endcode
- */
-template <typename AsyncReadStream, typename Allocator,
-    typename MatchCondition, typename ReadHandler>
-ASIO_INITFN_RESULT_TYPE(ReadHandler,
-    void (asio::error_code, std::size_t))
-async_read_until(AsyncReadStream& s,
-    asio::basic_streambuf<Allocator>& b,
-    MatchCondition match_condition, ASIO_MOVE_ARG(ReadHandler) handler,
-    typename enable_if<is_match_condition<MatchCondition>::value>::type* = 0);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/read_until.hpp"
-
-#endif // ASIO_READ_UNTIL_HPP
diff --git a/tools/sdk/include/asio/asio/seq_packet_socket_service.hpp b/tools/sdk/include/asio/asio/seq_packet_socket_service.hpp
deleted file mode 100644
index 7e6824d41e0..00000000000
--- a/tools/sdk/include/asio/asio/seq_packet_socket_service.hpp
+++ /dev/null
@@ -1,416 +0,0 @@
-//
-// seq_packet_socket_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SEQ_PACKET_SOCKET_SERVICE_HPP
-#define ASIO_SEQ_PACKET_SOCKET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/null_socket_service.hpp"
-#elif defined(ASIO_HAS_IOCP)
-# include "asio/detail/win_iocp_socket_service.hpp"
-#else
-# include "asio/detail/reactive_socket_service.hpp"
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default service implementation for a sequenced packet socket.
-template <typename Protocol>
-class seq_packet_socket_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<
-      seq_packet_socket_service<Protocol> >
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-private:
-  // The type of the platform-specific implementation.
-#if defined(ASIO_WINDOWS_RUNTIME)
-  typedef detail::null_socket_service<Protocol> service_impl_type;
-#elif defined(ASIO_HAS_IOCP)
-  typedef detail::win_iocp_socket_service<Protocol> service_impl_type;
-#else
-  typedef detail::reactive_socket_service<Protocol> service_impl_type;
-#endif
-
-public:
-  /// The type of a sequenced packet socket implementation.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef typename service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native socket type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new sequenced packet socket service for the specified
-  /// io_context.
-  explicit seq_packet_socket_service(asio::io_context& io_context)
-    : asio::detail::service_base<
-        seq_packet_socket_service<Protocol> >(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new sequenced packet socket implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new sequenced packet socket implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another sequenced packet socket implementation.
-  void move_assign(implementation_type& impl,
-      seq_packet_socket_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-
-  // All socket services have access to each other's implementations.
-  template <typename Protocol1> friend class seq_packet_socket_service;
-
-  /// Move-construct a new sequenced packet socket implementation from another
-  /// protocol type.
-  template <typename Protocol1>
-  void converting_move_construct(implementation_type& impl,
-      seq_packet_socket_service<Protocol1>& other_service,
-      typename seq_packet_socket_service<
-        Protocol1>::implementation_type& other_impl,
-      typename enable_if<is_convertible<
-        Protocol1, Protocol>::value>::type* = 0)
-  {
-    service_impl_.template converting_move_construct<Protocol1>(
-        impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a sequenced packet socket implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Open a sequenced packet socket.
-  ASIO_SYNC_OP_VOID open(implementation_type& impl,
-      const protocol_type& protocol, asio::error_code& ec)
-  {
-    if (protocol.type() == ASIO_OS_DEF(SOCK_SEQPACKET))
-      service_impl_.open(impl, protocol, ec);
-    else
-      ec = asio::error::invalid_argument;
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assign an existing native socket to a sequenced packet socket.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const protocol_type& protocol, const native_handle_type& native_socket,
-      asio::error_code& ec)
-  {
-    service_impl_.assign(impl, protocol, native_socket, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Close a sequenced packet socket implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Release ownership of the underlying socket.
-  native_handle_type release(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return service_impl_.release(impl, ec);
-  }
-
-  /// Get the native socket implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the socket.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is at the out-of-band data mark.
-  bool at_mark(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.at_mark(impl, ec);
-  }
-
-  /// Determine the number of bytes available for reading.
-  std::size_t available(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.available(impl, ec);
-  }
-
-  /// Bind the sequenced packet socket to the specified local endpoint.
-  ASIO_SYNC_OP_VOID bind(implementation_type& impl,
-      const endpoint_type& endpoint, asio::error_code& ec)
-  {
-    service_impl_.bind(impl, endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Connect the sequenced packet socket to the specified endpoint.
-  ASIO_SYNC_OP_VOID connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, asio::error_code& ec)
-  {
-    service_impl_.connect(impl, peer_endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous connect.
-  template <typename ConnectHandler>
-  ASIO_INITFN_RESULT_TYPE(ConnectHandler,
-      void (asio::error_code))
-  async_connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint,
-      ASIO_MOVE_ARG(ConnectHandler) handler)
-  {
-    async_completion<ConnectHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_connect(impl, peer_endpoint, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Set a socket option.
-  template <typename SettableSocketOption>
-  ASIO_SYNC_OP_VOID set_option(implementation_type& impl,
-      const SettableSocketOption& option, asio::error_code& ec)
-  {
-    service_impl_.set_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get a socket option.
-  template <typename GettableSocketOption>
-  ASIO_SYNC_OP_VOID get_option(const implementation_type& impl,
-      GettableSocketOption& option, asio::error_code& ec) const
-  {
-    service_impl_.get_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the socket.
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(implementation_type& impl,
-      IoControlCommand& command, asio::error_code& ec)
-  {
-    service_impl_.io_control(impl, command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the socket.
-  bool non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the socket.
-  ASIO_SYNC_OP_VOID non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native socket implementation.
-  bool native_non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.native_non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the native socket implementation.
-  ASIO_SYNC_OP_VOID native_non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.native_non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the local endpoint.
-  endpoint_type local_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.local_endpoint(impl, ec);
-  }
-
-  /// Get the remote endpoint.
-  endpoint_type remote_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.remote_endpoint(impl, ec);
-  }
-
-  /// Disable sends or receives on the socket.
-  ASIO_SYNC_OP_VOID shutdown(implementation_type& impl,
-      socket_base::shutdown_type what, asio::error_code& ec)
-  {
-    service_impl_.shutdown(impl, what, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Wait for the socket to become ready to read, ready to write, or to have
-  /// pending error conditions.
-  ASIO_SYNC_OP_VOID wait(implementation_type& impl,
-      socket_base::wait_type w, asio::error_code& ec)
-  {
-    service_impl_.wait(impl, w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the socket to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(implementation_type& impl, socket_base::wait_type w,
-      ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_wait(impl, w, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Send the given data to the peer.
-  template <typename ConstBufferSequence>
-  std::size_t send(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.send(impl, buffers, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_send(impl, buffers, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Receive some data from the peer.
-  template <typename MutableBufferSequence>
-  std::size_t receive(implementation_type& impl,
-      const MutableBufferSequence& buffers, socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags, asio::error_code& ec)
-  {
-    return service_impl_.receive_with_flags(impl,
-        buffers, in_flags, out_flags, ec);
-  }
-
-  /// Start an asynchronous receive.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(implementation_type& impl,
-      const MutableBufferSequence& buffers, socket_base::message_flags in_flags,
-      socket_base::message_flags& out_flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_receive_with_flags(impl,
-        buffers, in_flags, out_flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_SEQ_PACKET_SOCKET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/serial_port.hpp b/tools/sdk/include/asio/asio/serial_port.hpp
deleted file mode 100644
index 27bb63ef739..00000000000
--- a/tools/sdk/include/asio/asio/serial_port.hpp
+++ /dev/null
@@ -1,769 +0,0 @@
-//
-// serial_port.hpp
-// ~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Rep Invariant Systems, Inc. (info@repinvariant.com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SERIAL_PORT_HPP
-#define ASIO_SERIAL_PORT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_SERIAL_PORT) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <string>
-#include "asio/async_result.hpp"
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/serial_port_base.hpp"
-
-#if defined(ASIO_HAS_MOVE)
-# include <utility>
-#endif // defined(ASIO_HAS_MOVE)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/basic_serial_port.hpp"
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-# if defined(ASIO_HAS_IOCP)
-#  include "asio/detail/win_iocp_serial_port_service.hpp"
-#  define ASIO_SVC_T detail::win_iocp_serial_port_service
-# else
-#  include "asio/detail/reactive_serial_port_service.hpp"
-#  define ASIO_SVC_T detail::reactive_serial_port_service
-# endif
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-// Typedef for the typical usage of a serial port.
-typedef basic_serial_port<> serial_port;
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-/// Provides serial port functionality.
-/**
- * The serial_port class provides a wrapper over serial port functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class serial_port
-  : ASIO_SVC_ACCESS basic_io_object<ASIO_SVC_T>,
-    public serial_port_base
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// The native representation of a serial port.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef ASIO_SVC_T::native_handle_type native_handle_type;
-#endif
-
-  /// A basic_serial_port is always the lowest layer.
-  typedef serial_port lowest_layer_type;
-
-  /// Construct a serial_port without opening it.
-  /**
-   * This constructor creates a serial port without opening it.
-   *
-   * @param io_context The io_context object that the serial port will use to
-   * dispatch handlers for any asynchronous operations performed on the port.
-   */
-  explicit serial_port(asio::io_context& io_context)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-  }
-
-  /// Construct and open a serial_port.
-  /**
-   * This constructor creates and opens a serial port for the specified device
-   * name.
-   *
-   * @param io_context The io_context object that the serial port will use to
-   * dispatch handlers for any asynchronous operations performed on the port.
-   *
-   * @param device The platform-specific device name for this serial
-   * port.
-   */
-  explicit serial_port(asio::io_context& io_context,
-      const char* device)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), device, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Construct and open a serial_port.
-  /**
-   * This constructor creates and opens a serial port for the specified device
-   * name.
-   *
-   * @param io_context The io_context object that the serial port will use to
-   * dispatch handlers for any asynchronous operations performed on the port.
-   *
-   * @param device The platform-specific device name for this serial
-   * port.
-   */
-  explicit serial_port(asio::io_context& io_context,
-      const std::string& device)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), device, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Construct a serial_port on an existing native serial port.
-  /**
-   * This constructor creates a serial port object to hold an existing native
-   * serial port.
-   *
-   * @param io_context The io_context object that the serial port will use to
-   * dispatch handlers for any asynchronous operations performed on the port.
-   *
-   * @param native_serial_port A native serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  serial_port(asio::io_context& io_context,
-      const native_handle_type& native_serial_port)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        native_serial_port, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a serial_port from another.
-  /**
-   * This constructor moves a serial port from one object to another.
-   *
-   * @param other The other serial_port object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c serial_port(io_context&) constructor.
-   */
-  serial_port(serial_port&& other)
-    : basic_io_object<ASIO_SVC_T>(std::move(other))
-  {
-  }
-
-  /// Move-assign a serial_port from another.
-  /**
-   * This assignment operator moves a serial port from one object to another.
-   *
-   * @param other The other serial_port object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c serial_port(io_context&) constructor.
-   */
-  serial_port& operator=(serial_port&& other)
-  {
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroys the serial port.
-  /**
-   * This function destroys the serial port, cancelling any outstanding
-   * asynchronous wait operations associated with the serial port as if by
-   * calling @c cancel.
-   */
-  ~serial_port()
-  {
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<ASIO_SVC_T>::get_executor();
-  }
-
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * layers. Since a serial_port cannot contain any further layers, it simply
-   * returns a reference to itself.
-   *
-   * @return A reference to the lowest layer in the stack of layers. Ownership
-   * is not transferred to the caller.
-   */
-  lowest_layer_type& lowest_layer()
-  {
-    return *this;
-  }
-
-  /// Get a const reference to the lowest layer.
-  /**
-   * This function returns a const reference to the lowest layer in a stack of
-   * layers. Since a serial_port cannot contain any further layers, it simply
-   * returns a reference to itself.
-   *
-   * @return A const reference to the lowest layer in the stack of layers.
-   * Ownership is not transferred to the caller.
-   */
-  const lowest_layer_type& lowest_layer() const
-  {
-    return *this;
-  }
-
-  /// Open the serial port using the specified device name.
-  /**
-   * This function opens the serial port for the specified device name.
-   *
-   * @param device The platform-specific device name.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void open(const std::string& device)
-  {
-    asio::error_code ec;
-    this->get_service().open(this->get_implementation(), device, ec);
-    asio::detail::throw_error(ec, "open");
-  }
-
-  /// Open the serial port using the specified device name.
-  /**
-   * This function opens the serial port using the given platform-specific
-   * device name.
-   *
-   * @param device The platform-specific device name.
-   *
-   * @param ec Set the indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID open(const std::string& device,
-      asio::error_code& ec)
-  {
-    this->get_service().open(this->get_implementation(), device, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assign an existing native serial port to the serial port.
-  /*
-   * This function opens the serial port to hold an existing native serial port.
-   *
-   * @param native_serial_port A native serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void assign(const native_handle_type& native_serial_port)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(),
-        native_serial_port, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-  /// Assign an existing native serial port to the serial port.
-  /*
-   * This function opens the serial port to hold an existing native serial port.
-   *
-   * @param native_serial_port A native serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID assign(const native_handle_type& native_serial_port,
-      asio::error_code& ec)
-  {
-    this->get_service().assign(this->get_implementation(),
-        native_serial_port, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the serial port is open.
-  bool is_open() const
-  {
-    return this->get_service().is_open(this->get_implementation());
-  }
-
-  /// Close the serial port.
-  /**
-   * This function is used to close the serial port. Any asynchronous read or
-   * write operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void close()
-  {
-    asio::error_code ec;
-    this->get_service().close(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "close");
-  }
-
-  /// Close the serial port.
-  /**
-   * This function is used to close the serial port. Any asynchronous read or
-   * write operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    this->get_service().close(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native serial port representation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * serial port. This is intended to allow access to native serial port
-   * functionality that is not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return this->get_service().native_handle(this->get_implementation());
-  }
-
-  /// Cancel all asynchronous operations associated with the serial port.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all asynchronous operations associated with the serial port.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Send a break sequence to the serial port.
-  /**
-   * This function causes a break sequence of platform-specific duration to be
-   * sent out the serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void send_break()
-  {
-    asio::error_code ec;
-    this->get_service().send_break(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "send_break");
-  }
-
-  /// Send a break sequence to the serial port.
-  /**
-   * This function causes a break sequence of platform-specific duration to be
-   * sent out the serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID send_break(asio::error_code& ec)
-  {
-    this->get_service().send_break(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Set an option on the serial port.
-  /**
-   * This function is used to set an option on the serial port.
-   *
-   * @param option The option value to be set on the serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa SettableSerialPortOption @n
-   * asio::serial_port_base::baud_rate @n
-   * asio::serial_port_base::flow_control @n
-   * asio::serial_port_base::parity @n
-   * asio::serial_port_base::stop_bits @n
-   * asio::serial_port_base::character_size
-   */
-  template <typename SettableSerialPortOption>
-  void set_option(const SettableSerialPortOption& option)
-  {
-    asio::error_code ec;
-    this->get_service().set_option(this->get_implementation(), option, ec);
-    asio::detail::throw_error(ec, "set_option");
-  }
-
-  /// Set an option on the serial port.
-  /**
-   * This function is used to set an option on the serial port.
-   *
-   * @param option The option value to be set on the serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa SettableSerialPortOption @n
-   * asio::serial_port_base::baud_rate @n
-   * asio::serial_port_base::flow_control @n
-   * asio::serial_port_base::parity @n
-   * asio::serial_port_base::stop_bits @n
-   * asio::serial_port_base::character_size
-   */
-  template <typename SettableSerialPortOption>
-  ASIO_SYNC_OP_VOID set_option(const SettableSerialPortOption& option,
-      asio::error_code& ec)
-  {
-    this->get_service().set_option(this->get_implementation(), option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get an option from the serial port.
-  /**
-   * This function is used to get the current value of an option on the serial
-   * port.
-   *
-   * @param option The option value to be obtained from the serial port.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @sa GettableSerialPortOption @n
-   * asio::serial_port_base::baud_rate @n
-   * asio::serial_port_base::flow_control @n
-   * asio::serial_port_base::parity @n
-   * asio::serial_port_base::stop_bits @n
-   * asio::serial_port_base::character_size
-   */
-  template <typename GettableSerialPortOption>
-  void get_option(GettableSerialPortOption& option)
-  {
-    asio::error_code ec;
-    this->get_service().get_option(this->get_implementation(), option, ec);
-    asio::detail::throw_error(ec, "get_option");
-  }
-
-  /// Get an option from the serial port.
-  /**
-   * This function is used to get the current value of an option on the serial
-   * port.
-   *
-   * @param option The option value to be obtained from the serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @sa GettableSerialPortOption @n
-   * asio::serial_port_base::baud_rate @n
-   * asio::serial_port_base::flow_control @n
-   * asio::serial_port_base::parity @n
-   * asio::serial_port_base::stop_bits @n
-   * asio::serial_port_base::character_size
-   */
-  template <typename GettableSerialPortOption>
-  ASIO_SYNC_OP_VOID get_option(GettableSerialPortOption& option,
-      asio::error_code& ec)
-  {
-    this->get_service().get_option(this->get_implementation(), option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Write some data to the serial port.
-  /**
-   * This function is used to write data to the serial port. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the serial port.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * serial_port.write_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "write_some");
-    return s;
-  }
-
-  /// Write some data to the serial port.
-  /**
-   * This function is used to write data to the serial port. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the serial port.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous write.
-  /**
-   * This function is used to asynchronously write data to the serial port.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be written to the serial port.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The write operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write function if you need to ensure that all
-   * data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * serial_port.async_write_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_write_some(
-        this->get_implementation(), buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Read some data from the serial port.
-  /**
-   * This function is used to read data from the serial port. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * serial_port.read_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "read_some");
-    return s;
-  }
-
-  /// Read some data from the serial port.
-  /**
-   * This function is used to read data from the serial port. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous read.
-  /**
-   * This function is used to asynchronously read data from the serial port.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The read operation may not read all of the requested number of bytes.
-   * Consider using the @ref async_read function if you need to ensure that the
-   * requested amount of data is read before the asynchronous operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * serial_port.async_read_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_read_some(
-        this->get_implementation(), buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-};
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-# undef ASIO_SVC_T
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // defined(ASIO_HAS_SERIAL_PORT)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_SERIAL_PORT_HPP
diff --git a/tools/sdk/include/asio/asio/serial_port_base.hpp b/tools/sdk/include/asio/asio/serial_port_base.hpp
deleted file mode 100644
index feb5b9df871..00000000000
--- a/tools/sdk/include/asio/asio/serial_port_base.hpp
+++ /dev/null
@@ -1,167 +0,0 @@
-//
-// serial_port_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2008 Rep Invariant Systems, Inc. (info@repinvariant.com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SERIAL_PORT_BASE_HPP
-#define ASIO_SERIAL_PORT_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_SERIAL_PORT) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#if !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-# include <termios.h>
-#endif // !defined(ASIO_WINDOWS) && !defined(__CYGWIN__)
-
-#include "asio/detail/socket_types.hpp"
-#include "asio/error_code.hpp"
-
-#if defined(GENERATING_DOCUMENTATION)
-# define ASIO_OPTION_STORAGE implementation_defined
-#elif defined(ASIO_WINDOWS) || defined(__CYGWIN__)
-# define ASIO_OPTION_STORAGE DCB
-#else
-# define ASIO_OPTION_STORAGE termios
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// The serial_port_base class is used as a base for the basic_serial_port class
-/// template so that we have a common place to define the serial port options.
-class serial_port_base
-{
-public:
-  /// Serial port option to permit changing the baud rate.
-  /**
-   * Implements changing the baud rate for a given serial port.
-   */
-  class baud_rate
-  {
-  public:
-    explicit baud_rate(unsigned int rate = 0);
-    unsigned int value() const;
-    ASIO_DECL ASIO_SYNC_OP_VOID store(
-        ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec) const;
-    ASIO_DECL ASIO_SYNC_OP_VOID load(
-        const ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec);
-  private:
-    unsigned int value_;
-  };
-
-  /// Serial port option to permit changing the flow control.
-  /**
-   * Implements changing the flow control for a given serial port.
-   */
-  class flow_control
-  {
-  public:
-    enum type { none, software, hardware };
-    ASIO_DECL explicit flow_control(type t = none);
-    type value() const;
-    ASIO_DECL ASIO_SYNC_OP_VOID store(
-        ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec) const;
-    ASIO_DECL ASIO_SYNC_OP_VOID load(
-        const ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec);
-  private:
-    type value_;
-  };
-
-  /// Serial port option to permit changing the parity.
-  /**
-   * Implements changing the parity for a given serial port.
-   */
-  class parity
-  {
-  public:
-    enum type { none, odd, even };
-    ASIO_DECL explicit parity(type t = none);
-    type value() const;
-    ASIO_DECL ASIO_SYNC_OP_VOID store(
-        ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec) const;
-    ASIO_DECL ASIO_SYNC_OP_VOID load(
-        const ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec);
-  private:
-    type value_;
-  };
-
-  /// Serial port option to permit changing the number of stop bits.
-  /**
-   * Implements changing the number of stop bits for a given serial port.
-   */
-  class stop_bits
-  {
-  public:
-    enum type { one, onepointfive, two };
-    ASIO_DECL explicit stop_bits(type t = one);
-    type value() const;
-    ASIO_DECL ASIO_SYNC_OP_VOID store(
-        ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec) const;
-    ASIO_DECL ASIO_SYNC_OP_VOID load(
-        const ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec);
-  private:
-    type value_;
-  };
-
-  /// Serial port option to permit changing the character size.
-  /**
-   * Implements changing the character size for a given serial port.
-   */
-  class character_size
-  {
-  public:
-    ASIO_DECL explicit character_size(unsigned int t = 8);
-    unsigned int value() const;
-    ASIO_DECL ASIO_SYNC_OP_VOID store(
-        ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec) const;
-    ASIO_DECL ASIO_SYNC_OP_VOID load(
-        const ASIO_OPTION_STORAGE& storage,
-        asio::error_code& ec);
-  private:
-    unsigned int value_;
-  };
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  ~serial_port_base()
-  {
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#undef ASIO_OPTION_STORAGE
-
-#include "asio/impl/serial_port_base.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/impl/serial_port_base.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // defined(ASIO_HAS_SERIAL_PORT)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_SERIAL_PORT_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/serial_port_service.hpp b/tools/sdk/include/asio/asio/serial_port_service.hpp
deleted file mode 100644
index 0e20d96e3f2..00000000000
--- a/tools/sdk/include/asio/asio/serial_port_service.hpp
+++ /dev/null
@@ -1,249 +0,0 @@
-//
-// serial_port_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SERIAL_PORT_SERVICE_HPP
-#define ASIO_SERIAL_PORT_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_SERIAL_PORT) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include <string>
-#include "asio/async_result.hpp"
-#include "asio/detail/reactive_serial_port_service.hpp"
-#include "asio/detail/win_iocp_serial_port_service.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-#include "asio/serial_port_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default service implementation for a serial port.
-class serial_port_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<serial_port_service>
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-private:
-  // The type of the platform-specific implementation.
-#if defined(ASIO_HAS_IOCP)
-  typedef detail::win_iocp_serial_port_service service_impl_type;
-#else
-  typedef detail::reactive_serial_port_service service_impl_type;
-#endif
-
-public:
-  /// The type of a serial port implementation.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native handle type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new serial port service for the specified io_context.
-  explicit serial_port_service(asio::io_context& io_context)
-    : asio::detail::service_base<serial_port_service>(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new serial port implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new serial port implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another serial port implementation.
-  void move_assign(implementation_type& impl,
-      serial_port_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a serial port implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Open a serial port.
-  ASIO_SYNC_OP_VOID open(implementation_type& impl,
-      const std::string& device, asio::error_code& ec)
-  {
-    service_impl_.open(impl, device, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assign an existing native handle to a serial port.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const native_handle_type& handle, asio::error_code& ec)
-  {
-    service_impl_.assign(impl, handle, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the handle is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Close a serial port implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native handle implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Set a serial port option.
-  template <typename SettableSerialPortOption>
-  ASIO_SYNC_OP_VOID set_option(implementation_type& impl,
-      const SettableSerialPortOption& option, asio::error_code& ec)
-  {
-    service_impl_.set_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get a serial port option.
-  template <typename GettableSerialPortOption>
-  ASIO_SYNC_OP_VOID get_option(const implementation_type& impl,
-      GettableSerialPortOption& option, asio::error_code& ec) const
-  {
-    service_impl_.get_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Send a break sequence to the serial port.
-  ASIO_SYNC_OP_VOID send_break(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.send_break(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Write the given data to the stream.
-  template <typename ConstBufferSequence>
-  std::size_t write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    return service_impl_.write_some(impl, buffers, ec);
-  }
-
-  /// Start an asynchronous write.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_write_some(impl, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Read some data from the stream.
-  template <typename MutableBufferSequence>
-  std::size_t read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    return service_impl_.read_some(impl, buffers, ec);
-  }
-
-  /// Start an asynchronous read.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_read_some(impl, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_SERIAL_PORT)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_SERIAL_PORT_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/signal_set.hpp b/tools/sdk/include/asio/asio/signal_set.hpp
deleted file mode 100644
index 30e5c4e39b7..00000000000
--- a/tools/sdk/include/asio/asio/signal_set.hpp
+++ /dev/null
@@ -1,447 +0,0 @@
-//
-// signal_set.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SIGNAL_SET_HPP
-#define ASIO_SIGNAL_SET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/async_result.hpp"
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/basic_signal_set.hpp"
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/detail/signal_set_service.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-namespace asio {
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-// Typedef for the typical usage of a signal set.
-typedef basic_signal_set<> signal_set;
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-/// Provides signal functionality.
-/**
- * The signal_set class provides the ability to perform an asynchronous wait
- * for one or more signals to occur.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Example
- * Performing an asynchronous wait:
- * @code
- * void handler(
- *     const asio::error_code& error,
- *     int signal_number)
- * {
- *   if (!error)
- *   {
- *     // A signal occurred.
- *   }
- * }
- *
- * ...
- *
- * // Construct a signal set registered for process termination.
- * asio::signal_set signals(io_context, SIGINT, SIGTERM);
- *
- * // Start an asynchronous wait for one of the signals to occur.
- * signals.async_wait(handler);
- * @endcode
- *
- * @par Queueing of signal notifications
- *
- * If a signal is registered with a signal_set, and the signal occurs when
- * there are no waiting handlers, then the signal notification is queued. The
- * next async_wait operation on that signal_set will dequeue the notification.
- * If multiple notifications are queued, subsequent async_wait operations
- * dequeue them one at a time. Signal notifications are dequeued in order of
- * ascending signal number.
- *
- * If a signal number is removed from a signal_set (using the @c remove or @c
- * erase member functions) then any queued notifications for that signal are
- * discarded.
- *
- * @par Multiple registration of signals
- *
- * The same signal number may be registered with different signal_set objects.
- * When the signal occurs, one handler is called for each signal_set object.
- *
- * Note that multiple registration only works for signals that are registered
- * using Asio. The application must not also register a signal handler using
- * functions such as @c signal() or @c sigaction().
- *
- * @par Signal masking on POSIX platforms
- *
- * POSIX allows signals to be blocked using functions such as @c sigprocmask()
- * and @c pthread_sigmask(). For signals to be delivered, programs must ensure
- * that any signals registered using signal_set objects are unblocked in at
- * least one thread.
- */
-class signal_set
-  : ASIO_SVC_ACCESS basic_io_object<detail::signal_set_service>
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// Construct a signal set without adding any signals.
-  /**
-   * This constructor creates a signal set without registering for any signals.
-   *
-   * @param io_context The io_context object that the signal set will use to
-   * dispatch handlers for any asynchronous operations performed on the set.
-   */
-  explicit signal_set(asio::io_context& io_context)
-    : basic_io_object<detail::signal_set_service>(io_context)
-  {
-  }
-
-  /// Construct a signal set and add one signal.
-  /**
-   * This constructor creates a signal set and registers for one signal.
-   *
-   * @param io_context The io_context object that the signal set will use to
-   * dispatch handlers for any asynchronous operations performed on the set.
-   *
-   * @param signal_number_1 The signal number to be added.
-   *
-   * @note This constructor is equivalent to performing:
-   * @code asio::signal_set signals(io_context);
-   * signals.add(signal_number_1); @endcode
-   */
-  signal_set(asio::io_context& io_context, int signal_number_1)
-    : basic_io_object<detail::signal_set_service>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().add(this->get_implementation(), signal_number_1, ec);
-    asio::detail::throw_error(ec, "add");
-  }
-
-  /// Construct a signal set and add two signals.
-  /**
-   * This constructor creates a signal set and registers for two signals.
-   *
-   * @param io_context The io_context object that the signal set will use to
-   * dispatch handlers for any asynchronous operations performed on the set.
-   *
-   * @param signal_number_1 The first signal number to be added.
-   *
-   * @param signal_number_2 The second signal number to be added.
-   *
-   * @note This constructor is equivalent to performing:
-   * @code asio::signal_set signals(io_context);
-   * signals.add(signal_number_1);
-   * signals.add(signal_number_2); @endcode
-   */
-  signal_set(asio::io_context& io_context, int signal_number_1,
-      int signal_number_2)
-    : basic_io_object<detail::signal_set_service>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().add(this->get_implementation(), signal_number_1, ec);
-    asio::detail::throw_error(ec, "add");
-    this->get_service().add(this->get_implementation(), signal_number_2, ec);
-    asio::detail::throw_error(ec, "add");
-  }
-
-  /// Construct a signal set and add three signals.
-  /**
-   * This constructor creates a signal set and registers for three signals.
-   *
-   * @param io_context The io_context object that the signal set will use to
-   * dispatch handlers for any asynchronous operations performed on the set.
-   *
-   * @param signal_number_1 The first signal number to be added.
-   *
-   * @param signal_number_2 The second signal number to be added.
-   *
-   * @param signal_number_3 The third signal number to be added.
-   *
-   * @note This constructor is equivalent to performing:
-   * @code asio::signal_set signals(io_context);
-   * signals.add(signal_number_1);
-   * signals.add(signal_number_2);
-   * signals.add(signal_number_3); @endcode
-   */
-  signal_set(asio::io_context& io_context, int signal_number_1,
-      int signal_number_2, int signal_number_3)
-    : basic_io_object<detail::signal_set_service>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().add(this->get_implementation(), signal_number_1, ec);
-    asio::detail::throw_error(ec, "add");
-    this->get_service().add(this->get_implementation(), signal_number_2, ec);
-    asio::detail::throw_error(ec, "add");
-    this->get_service().add(this->get_implementation(), signal_number_3, ec);
-    asio::detail::throw_error(ec, "add");
-  }
-
-  /// Destroys the signal set.
-  /**
-   * This function destroys the signal set, cancelling any outstanding
-   * asynchronous wait operations associated with the signal set as if by
-   * calling @c cancel.
-   */
-  ~signal_set()
-  {
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<detail::signal_set_service>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<detail::signal_set_service>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<detail::signal_set_service>::get_executor();
-  }
-
-  /// Add a signal to a signal_set.
-  /**
-   * This function adds the specified signal to the set. It has no effect if the
-   * signal is already in the set.
-   *
-   * @param signal_number The signal to be added to the set.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void add(int signal_number)
-  {
-    asio::error_code ec;
-    this->get_service().add(this->get_implementation(), signal_number, ec);
-    asio::detail::throw_error(ec, "add");
-  }
-
-  /// Add a signal to a signal_set.
-  /**
-   * This function adds the specified signal to the set. It has no effect if the
-   * signal is already in the set.
-   *
-   * @param signal_number The signal to be added to the set.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID add(int signal_number,
-      asio::error_code& ec)
-  {
-    this->get_service().add(this->get_implementation(), signal_number, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Remove a signal from a signal_set.
-  /**
-   * This function removes the specified signal from the set. It has no effect
-   * if the signal is not in the set.
-   *
-   * @param signal_number The signal to be removed from the set.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Removes any notifications that have been queued for the specified
-   * signal number.
-   */
-  void remove(int signal_number)
-  {
-    asio::error_code ec;
-    this->get_service().remove(this->get_implementation(), signal_number, ec);
-    asio::detail::throw_error(ec, "remove");
-  }
-
-  /// Remove a signal from a signal_set.
-  /**
-   * This function removes the specified signal from the set. It has no effect
-   * if the signal is not in the set.
-   *
-   * @param signal_number The signal to be removed from the set.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Removes any notifications that have been queued for the specified
-   * signal number.
-   */
-  ASIO_SYNC_OP_VOID remove(int signal_number,
-      asio::error_code& ec)
-  {
-    this->get_service().remove(this->get_implementation(), signal_number, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Remove all signals from a signal_set.
-  /**
-   * This function removes all signals from the set. It has no effect if the set
-   * is already empty.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Removes all queued notifications.
-   */
-  void clear()
-  {
-    asio::error_code ec;
-    this->get_service().clear(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "clear");
-  }
-
-  /// Remove all signals from a signal_set.
-  /**
-   * This function removes all signals from the set. It has no effect if the set
-   * is already empty.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Removes all queued notifications.
-   */
-  ASIO_SYNC_OP_VOID clear(asio::error_code& ec)
-  {
-    this->get_service().clear(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Cancel all operations associated with the signal set.
-  /**
-   * This function forces the completion of any pending asynchronous wait
-   * operations against the signal set. The handler for each cancelled
-   * operation will be invoked with the asio::error::operation_aborted
-   * error code.
-   *
-   * Cancellation does not alter the set of registered signals.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note If a registered signal occurred before cancel() is called, then the
-   * handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all operations associated with the signal set.
-  /**
-   * This function forces the completion of any pending asynchronous wait
-   * operations against the signal set. The handler for each cancelled
-   * operation will be invoked with the asio::error::operation_aborted
-   * error code.
-   *
-   * Cancellation does not alter the set of registered signals.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note If a registered signal occurred before cancel() is called, then the
-   * handlers for asynchronous wait operations will:
-   *
-   * @li have already been invoked; or
-   *
-   * @li have been queued for invocation in the near future.
-   *
-   * These handlers can no longer be cancelled, and therefore are passed an
-   * error code that indicates the successful completion of the wait operation.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous operation to wait for a signal to be delivered.
-  /**
-   * This function may be used to initiate an asynchronous wait against the
-   * signal set. It always returns immediately.
-   *
-   * For each call to async_wait(), the supplied handler will be called exactly
-   * once. The handler will be called when:
-   *
-   * @li One of the registered signals in the signal set occurs; or
-   *
-   * @li The signal set was cancelled, in which case the handler is passed the
-   * error code asio::error::operation_aborted.
-   *
-   * @param handler The handler to be called when the signal occurs. Copies
-   * will be made of the handler as required. The function signature of the
-   * handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   int signal_number // Indicates which signal occurred.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename SignalHandler>
-  ASIO_INITFN_RESULT_TYPE(SignalHandler,
-      void (asio::error_code, int))
-  async_wait(ASIO_MOVE_ARG(SignalHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a SignalHandler.
-    ASIO_SIGNAL_HANDLER_CHECK(SignalHandler, handler) type_check;
-
-    async_completion<SignalHandler,
-      void (asio::error_code, int)> init(handler);
-
-    this->get_service().async_wait(this->get_implementation(),
-        init.completion_handler);
-
-    return init.result.get();
-  }
-};
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-} // namespace asio
-
-#endif // ASIO_SIGNAL_SET_HPP
diff --git a/tools/sdk/include/asio/asio/signal_set_service.hpp b/tools/sdk/include/asio/asio/signal_set_service.hpp
deleted file mode 100644
index 3285beb0035..00000000000
--- a/tools/sdk/include/asio/asio/signal_set_service.hpp
+++ /dev/null
@@ -1,142 +0,0 @@
-//
-// signal_set_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SIGNAL_SET_SERVICE_HPP
-#define ASIO_SIGNAL_SET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/async_result.hpp"
-#include "asio/detail/signal_set_service.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default service implementation for a signal set.
-class signal_set_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<signal_set_service>
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-public:
-  /// The type of a signal set implementation.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef detail::signal_set_service::implementation_type implementation_type;
-#endif
-
-  /// Construct a new signal set service for the specified io_context.
-  explicit signal_set_service(asio::io_context& io_context)
-    : asio::detail::service_base<signal_set_service>(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new signal set implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-  /// Destroy a signal set implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Add a signal to a signal_set.
-  ASIO_SYNC_OP_VOID add(implementation_type& impl,
-      int signal_number, asio::error_code& ec)
-  {
-    service_impl_.add(impl, signal_number, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Remove a signal to a signal_set.
-  ASIO_SYNC_OP_VOID remove(implementation_type& impl,
-      int signal_number, asio::error_code& ec)
-  {
-    service_impl_.remove(impl, signal_number, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Remove all signals from a signal_set.
-  ASIO_SYNC_OP_VOID clear(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.clear(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Cancel all operations associated with the signal set.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  // Start an asynchronous operation to wait for a signal to be delivered.
-  template <typename SignalHandler>
-  ASIO_INITFN_RESULT_TYPE(SignalHandler,
-      void (asio::error_code, int))
-  async_wait(implementation_type& impl,
-      ASIO_MOVE_ARG(SignalHandler) handler)
-  {
-    async_completion<SignalHandler,
-      void (asio::error_code, int)> init(handler);
-
-    service_impl_.async_wait(impl, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // Perform any fork-related housekeeping.
-  void notify_fork(asio::io_context::fork_event event)
-  {
-    service_impl_.notify_fork(event);
-  }
-
-  // The platform-specific implementation.
-  detail::signal_set_service service_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_SIGNAL_SET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/socket_acceptor_service.hpp b/tools/sdk/include/asio/asio/socket_acceptor_service.hpp
deleted file mode 100644
index cd40fe14201..00000000000
--- a/tools/sdk/include/asio/asio/socket_acceptor_service.hpp
+++ /dev/null
@@ -1,372 +0,0 @@
-//
-// socket_acceptor_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SOCKET_ACCEPTOR_SERVICE_HPP
-#define ASIO_SOCKET_ACCEPTOR_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/basic_socket.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/null_socket_service.hpp"
-#elif defined(ASIO_HAS_IOCP)
-# include "asio/detail/win_iocp_socket_service.hpp"
-#else
-# include "asio/detail/reactive_socket_service.hpp"
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default service implementation for a socket acceptor.
-template <typename Protocol>
-class socket_acceptor_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<socket_acceptor_service<Protocol> >
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename protocol_type::endpoint endpoint_type;
-
-private:
-  // The type of the platform-specific implementation.
-#if defined(ASIO_WINDOWS_RUNTIME)
-  typedef detail::null_socket_service<Protocol> service_impl_type;
-#elif defined(ASIO_HAS_IOCP)
-  typedef detail::win_iocp_socket_service<Protocol> service_impl_type;
-#else
-  typedef detail::reactive_socket_service<Protocol> service_impl_type;
-#endif
-
-public:
-  /// The native type of the socket acceptor.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef typename service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native acceptor type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new socket acceptor service for the specified io_context.
-  explicit socket_acceptor_service(asio::io_context& io_context)
-    : asio::detail::service_base<
-        socket_acceptor_service<Protocol> >(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new socket acceptor implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new socket acceptor implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another socket acceptor implementation.
-  void move_assign(implementation_type& impl,
-      socket_acceptor_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-
-  // All acceptor services have access to each other's implementations.
-  template <typename Protocol1> friend class socket_acceptor_service;
-
-  /// Move-construct a new socket acceptor implementation from another protocol
-  /// type.
-  template <typename Protocol1>
-  void converting_move_construct(implementation_type& impl,
-      socket_acceptor_service<Protocol1>& other_service,
-      typename socket_acceptor_service<
-        Protocol1>::implementation_type& other_impl,
-      typename enable_if<is_convertible<
-        Protocol1, Protocol>::value>::type* = 0)
-  {
-    service_impl_.template converting_move_construct<Protocol1>(
-        impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a socket acceptor implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Open a new socket acceptor implementation.
-  ASIO_SYNC_OP_VOID open(implementation_type& impl,
-      const protocol_type& protocol, asio::error_code& ec)
-  {
-    service_impl_.open(impl, protocol, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assign an existing native acceptor to a socket acceptor.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const protocol_type& protocol, const native_handle_type& native_acceptor,
-      asio::error_code& ec)
-  {
-    service_impl_.assign(impl, protocol, native_acceptor, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the acceptor is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the acceptor.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Bind the socket acceptor to the specified local endpoint.
-  ASIO_SYNC_OP_VOID bind(implementation_type& impl,
-      const endpoint_type& endpoint, asio::error_code& ec)
-  {
-    service_impl_.bind(impl, endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Place the socket acceptor into the state where it will listen for new
-  /// connections.
-  ASIO_SYNC_OP_VOID listen(implementation_type& impl, int backlog,
-      asio::error_code& ec)
-  {
-    service_impl_.listen(impl, backlog, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Close a socket acceptor implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Release ownership of the underlying acceptor.
-  native_handle_type release(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return service_impl_.release(impl, ec);
-  }
-
-  /// Get the native acceptor implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Set a socket option.
-  template <typename SettableSocketOption>
-  ASIO_SYNC_OP_VOID set_option(implementation_type& impl,
-      const SettableSocketOption& option, asio::error_code& ec)
-  {
-    service_impl_.set_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get a socket option.
-  template <typename GettableSocketOption>
-  ASIO_SYNC_OP_VOID get_option(const implementation_type& impl,
-      GettableSocketOption& option, asio::error_code& ec) const
-  {
-    service_impl_.get_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the socket.
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(implementation_type& impl,
-      IoControlCommand& command, asio::error_code& ec)
-  {
-    service_impl_.io_control(impl, command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the acceptor.
-  bool non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the acceptor.
-  ASIO_SYNC_OP_VOID non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native acceptor implementation.
-  bool native_non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.native_non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the native acceptor implementation.
-  ASIO_SYNC_OP_VOID native_non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.native_non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the local endpoint.
-  endpoint_type local_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.local_endpoint(impl, ec);
-  }
-
-  /// Wait for the acceptor to become ready to read, ready to write, or to have
-  /// pending error conditions.
-  ASIO_SYNC_OP_VOID wait(implementation_type& impl,
-      socket_base::wait_type w, asio::error_code& ec)
-  {
-    service_impl_.wait(impl, w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the acceptor to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(implementation_type& impl, socket_base::wait_type w,
-      ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_wait(impl, w, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Accept a new connection.
-  template <typename Protocol1, typename SocketService>
-  ASIO_SYNC_OP_VOID accept(implementation_type& impl,
-      basic_socket<Protocol1, SocketService>& peer,
-      endpoint_type* peer_endpoint, asio::error_code& ec,
-      typename enable_if<is_convertible<Protocol, Protocol1>::value>::type* = 0)
-  {
-    service_impl_.accept(impl, peer, peer_endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Accept a new connection.
-  typename Protocol::socket accept(implementation_type& impl,
-      io_context* peer_io_context, endpoint_type* peer_endpoint,
-      asio::error_code& ec)
-  {
-    return service_impl_.accept(impl, peer_io_context, peer_endpoint, ec);
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  /// Start an asynchronous accept.
-  template <typename Protocol1, typename SocketService, typename AcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(AcceptHandler,
-      void (asio::error_code))
-  async_accept(implementation_type& impl,
-      basic_socket<Protocol1, SocketService>& peer,
-      endpoint_type* peer_endpoint,
-      ASIO_MOVE_ARG(AcceptHandler) handler,
-      typename enable_if<is_convertible<Protocol, Protocol1>::value>::type* = 0)
-  {
-    async_completion<AcceptHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_accept(impl,
-        peer, peer_endpoint, init.completion_handler);
-
-    return init.result.get();
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  /// Start an asynchronous accept.
-  template <typename MoveAcceptHandler>
-  ASIO_INITFN_RESULT_TYPE(MoveAcceptHandler,
-      void (asio::error_code, typename Protocol::socket))
-  async_accept(implementation_type& impl,
-      asio::io_context* peer_io_context, endpoint_type* peer_endpoint,
-      ASIO_MOVE_ARG(MoveAcceptHandler) handler)
-  {
-    async_completion<MoveAcceptHandler,
-      void (asio::error_code,
-        typename Protocol::socket)> init(handler);
-
-    service_impl_.async_accept(impl,
-        peer_io_context, peer_endpoint, init.completion_handler);
-
-    return init.result.get();
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_SOCKET_ACCEPTOR_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/socket_base.hpp b/tools/sdk/include/asio/asio/socket_base.hpp
deleted file mode 100644
index 87ed8408bd0..00000000000
--- a/tools/sdk/include/asio/asio/socket_base.hpp
+++ /dev/null
@@ -1,559 +0,0 @@
-//
-// socket_base.hpp
-// ~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SOCKET_BASE_HPP
-#define ASIO_SOCKET_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/io_control.hpp"
-#include "asio/detail/socket_option.hpp"
-#include "asio/detail/socket_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// The socket_base class is used as a base for the basic_stream_socket and
-/// basic_datagram_socket class templates so that we have a common place to
-/// define the shutdown_type and enum.
-class socket_base
-{
-public:
-  /// Different ways a socket may be shutdown.
-  enum shutdown_type
-  {
-#if defined(GENERATING_DOCUMENTATION)
-    /// Shutdown the receive side of the socket.
-    shutdown_receive = implementation_defined,
-
-    /// Shutdown the send side of the socket.
-    shutdown_send = implementation_defined,
-
-    /// Shutdown both send and receive on the socket.
-    shutdown_both = implementation_defined
-#else
-    shutdown_receive = ASIO_OS_DEF(SHUT_RD),
-    shutdown_send = ASIO_OS_DEF(SHUT_WR),
-    shutdown_both = ASIO_OS_DEF(SHUT_RDWR)
-#endif
-  };
-
-  /// Bitmask type for flags that can be passed to send and receive operations.
-  typedef int message_flags;
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// Peek at incoming data without removing it from the input queue.
-  static const int message_peek = implementation_defined;
-
-  /// Process out-of-band data.
-  static const int message_out_of_band = implementation_defined;
-
-  /// Specify that the data should not be subject to routing.
-  static const int message_do_not_route = implementation_defined;
-
-  /// Specifies that the data marks the end of a record.
-  static const int message_end_of_record = implementation_defined;
-#else
-  ASIO_STATIC_CONSTANT(int,
-      message_peek = ASIO_OS_DEF(MSG_PEEK));
-  ASIO_STATIC_CONSTANT(int,
-      message_out_of_band = ASIO_OS_DEF(MSG_OOB));
-  ASIO_STATIC_CONSTANT(int,
-      message_do_not_route = ASIO_OS_DEF(MSG_DONTROUTE));
-  ASIO_STATIC_CONSTANT(int,
-      message_end_of_record = ASIO_OS_DEF(MSG_EOR));
-#endif
-
-  /// Wait types.
-  /**
-   * For use with basic_socket::wait() and basic_socket::async_wait().
-   */
-  enum wait_type
-  {
-    /// Wait for a socket to become ready to read.
-    wait_read,
-
-    /// Wait for a socket to become ready to write.
-    wait_write,
-
-    /// Wait for a socket to have error conditions pending.
-    wait_error
-  };
-
-  /// Socket option to permit sending of broadcast messages.
-  /**
-   * Implements the SOL_SOCKET/SO_BROADCAST socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::udp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::broadcast option(true);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::udp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::broadcast option;
-   * socket.get_option(option);
-   * bool is_set = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Boolean_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined broadcast;
-#else
-  typedef asio::detail::socket_option::boolean<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_BROADCAST)>
-      broadcast;
-#endif
-
-  /// Socket option to enable socket-level debugging.
-  /**
-   * Implements the SOL_SOCKET/SO_DEBUG socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::debug option(true);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::debug option;
-   * socket.get_option(option);
-   * bool is_set = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Boolean_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined debug;
-#else
-  typedef asio::detail::socket_option::boolean<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_DEBUG)> debug;
-#endif
-
-  /// Socket option to prevent routing, use local interfaces only.
-  /**
-   * Implements the SOL_SOCKET/SO_DONTROUTE socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::udp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::do_not_route option(true);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::udp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::do_not_route option;
-   * socket.get_option(option);
-   * bool is_set = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Boolean_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined do_not_route;
-#else
-  typedef asio::detail::socket_option::boolean<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_DONTROUTE)>
-      do_not_route;
-#endif
-
-  /// Socket option to send keep-alives.
-  /**
-   * Implements the SOL_SOCKET/SO_KEEPALIVE socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::keep_alive option(true);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::keep_alive option;
-   * socket.get_option(option);
-   * bool is_set = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Boolean_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined keep_alive;
-#else
-  typedef asio::detail::socket_option::boolean<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_KEEPALIVE)> keep_alive;
-#endif
-
-  /// Socket option for the send buffer size of a socket.
-  /**
-   * Implements the SOL_SOCKET/SO_SNDBUF socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::send_buffer_size option(8192);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::send_buffer_size option;
-   * socket.get_option(option);
-   * int size = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Integer_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined send_buffer_size;
-#else
-  typedef asio::detail::socket_option::integer<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_SNDBUF)>
-      send_buffer_size;
-#endif
-
-  /// Socket option for the send low watermark.
-  /**
-   * Implements the SOL_SOCKET/SO_SNDLOWAT socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::send_low_watermark option(1024);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::send_low_watermark option;
-   * socket.get_option(option);
-   * int size = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Integer_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined send_low_watermark;
-#else
-  typedef asio::detail::socket_option::integer<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_SNDLOWAT)>
-      send_low_watermark;
-#endif
-
-  /// Socket option for the receive buffer size of a socket.
-  /**
-   * Implements the SOL_SOCKET/SO_RCVBUF socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::receive_buffer_size option(8192);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::receive_buffer_size option;
-   * socket.get_option(option);
-   * int size = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Integer_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined receive_buffer_size;
-#else
-  typedef asio::detail::socket_option::integer<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_RCVBUF)>
-      receive_buffer_size;
-#endif
-
-  /// Socket option for the receive low watermark.
-  /**
-   * Implements the SOL_SOCKET/SO_RCVLOWAT socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::receive_low_watermark option(1024);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::receive_low_watermark option;
-   * socket.get_option(option);
-   * int size = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Integer_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined receive_low_watermark;
-#else
-  typedef asio::detail::socket_option::integer<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_RCVLOWAT)>
-      receive_low_watermark;
-#endif
-
-  /// Socket option to allow the socket to be bound to an address that is
-  /// already in use.
-  /**
-   * Implements the SOL_SOCKET/SO_REUSEADDR socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context); 
-   * ...
-   * asio::socket_base::reuse_address option(true);
-   * acceptor.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context); 
-   * ...
-   * asio::socket_base::reuse_address option;
-   * acceptor.get_option(option);
-   * bool is_set = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Boolean_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined reuse_address;
-#else
-  typedef asio::detail::socket_option::boolean<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_REUSEADDR)>
-      reuse_address;
-#endif
-
-  /// Socket option to specify whether the socket lingers on close if unsent
-  /// data is present.
-  /**
-   * Implements the SOL_SOCKET/SO_LINGER socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::linger option(true, 30);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::linger option;
-   * socket.get_option(option);
-   * bool is_set = option.enabled();
-   * unsigned short timeout = option.timeout();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Linger_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined linger;
-#else
-  typedef asio::detail::socket_option::linger<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_LINGER)>
-      linger;
-#endif
-
-  /// Socket option for putting received out-of-band data inline.
-  /**
-   * Implements the SOL_SOCKET/SO_OOBINLINE socket option.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::socket_base::out_of_band_inline option(true);
-   * socket.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::socket socket(io_context);
-   * ...
-   * asio::socket_base::out_of_band_inline option;
-   * socket.get_option(option);
-   * bool value = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Boolean_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined out_of_band_inline;
-#else
-  typedef asio::detail::socket_option::boolean<
-    ASIO_OS_DEF(SOL_SOCKET), ASIO_OS_DEF(SO_OOBINLINE)>
-      out_of_band_inline;
-#endif
-
-  /// Socket option to report aborted connections on accept.
-  /**
-   * Implements a custom socket option that determines whether or not an accept
-   * operation is permitted to fail with asio::error::connection_aborted.
-   * By default the option is false.
-   *
-   * @par Examples
-   * Setting the option:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context); 
-   * ...
-   * asio::socket_base::enable_connection_aborted option(true);
-   * acceptor.set_option(option);
-   * @endcode
-   *
-   * @par
-   * Getting the current option value:
-   * @code
-   * asio::ip::tcp::acceptor acceptor(io_context); 
-   * ...
-   * asio::socket_base::enable_connection_aborted option;
-   * acceptor.get_option(option);
-   * bool is_set = option.value();
-   * @endcode
-   *
-   * @par Concepts:
-   * Socket_Option, Boolean_Socket_Option.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined enable_connection_aborted;
-#else
-  typedef asio::detail::socket_option::boolean<
-    asio::detail::custom_socket_option_level,
-    asio::detail::enable_connection_aborted_option>
-    enable_connection_aborted;
-#endif
-
-  /// IO control command to get the amount of data that can be read without
-  /// blocking.
-  /**
-   * Implements the FIONREAD IO control command.
-   *
-   * @par Example
-   * @code
-   * asio::ip::tcp::socket socket(io_context); 
-   * ...
-   * asio::socket_base::bytes_readable command(true);
-   * socket.io_control(command);
-   * std::size_t bytes_readable = command.get();
-   * @endcode
-   *
-   * @par Concepts:
-   * IO_Control_Command, Size_IO_Control_Command.
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined bytes_readable;
-#else
-  typedef asio::detail::io_control::bytes_readable bytes_readable;
-#endif
-
-  /// The maximum length of the queue of pending incoming connections.
-#if defined(GENERATING_DOCUMENTATION)
-  static const int max_listen_connections = implementation_defined;
-#else
-  ASIO_STATIC_CONSTANT(int, max_listen_connections
-      = ASIO_OS_DEF(SOMAXCONN));
-#endif
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use max_listen_connections.) The maximum length of the queue
-  /// of pending incoming connections.
-#if defined(GENERATING_DOCUMENTATION)
-  static const int max_connections = implementation_defined;
-#else
-  ASIO_STATIC_CONSTANT(int, max_connections
-      = ASIO_OS_DEF(SOMAXCONN));
-#endif
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  ~socket_base()
-  {
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SOCKET_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/spawn.hpp b/tools/sdk/include/asio/asio/spawn.hpp
deleted file mode 100644
index a91c5815fbd..00000000000
--- a/tools/sdk/include/asio/asio/spawn.hpp
+++ /dev/null
@@ -1,336 +0,0 @@
-//
-// spawn.hpp
-// ~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SPAWN_HPP
-#define ASIO_SPAWN_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <boost/coroutine/all.hpp>
-#include "asio/bind_executor.hpp"
-#include "asio/detail/memory.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/detail/wrapped_handler.hpp"
-#include "asio/executor.hpp"
-#include "asio/io_context.hpp"
-#include "asio/is_executor.hpp"
-#include "asio/strand.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Context object the represents the currently executing coroutine.
-/**
- * The basic_yield_context class is used to represent the currently executing
- * stackful coroutine. A basic_yield_context may be passed as a handler to an
- * asynchronous operation. For example:
- *
- * @code template <typename Handler>
- * void my_coroutine(basic_yield_context<Handler> yield)
- * {
- *   ...
- *   std::size_t n = my_socket.async_read_some(buffer, yield);
- *   ...
- * } @endcode
- *
- * The initiating function (async_read_some in the above example) suspends the
- * current coroutine. The coroutine is resumed when the asynchronous operation
- * completes, and the result of the operation is returned.
- */
-template <typename Handler>
-class basic_yield_context
-{
-public:
-  /// The coroutine callee type, used by the implementation.
-  /**
-   * When using Boost.Coroutine v1, this type is:
-   * @code typename coroutine<void()> @endcode
-   * When using Boost.Coroutine v2 (unidirectional coroutines), this type is:
-   * @code push_coroutine<void> @endcode
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined callee_type;
-#elif defined(BOOST_COROUTINES_UNIDIRECT) || defined(BOOST_COROUTINES_V2)
-  typedef boost::coroutines::push_coroutine<void> callee_type;
-#else
-  typedef boost::coroutines::coroutine<void()> callee_type;
-#endif
-  
-  /// The coroutine caller type, used by the implementation.
-  /**
-   * When using Boost.Coroutine v1, this type is:
-   * @code typename coroutine<void()>::caller_type @endcode
-   * When using Boost.Coroutine v2 (unidirectional coroutines), this type is:
-   * @code pull_coroutine<void> @endcode
-   */
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined caller_type;
-#elif defined(BOOST_COROUTINES_UNIDIRECT) || defined(BOOST_COROUTINES_V2)
-  typedef boost::coroutines::pull_coroutine<void> caller_type;
-#else
-  typedef boost::coroutines::coroutine<void()>::caller_type caller_type;
-#endif
-
-  /// Construct a yield context to represent the specified coroutine.
-  /**
-   * Most applications do not need to use this constructor. Instead, the
-   * spawn() function passes a yield context as an argument to the coroutine
-   * function.
-   */
-  basic_yield_context(
-      const detail::weak_ptr<callee_type>& coro,
-      caller_type& ca, Handler& handler)
-    : coro_(coro),
-      ca_(ca),
-      handler_(handler),
-      ec_(0)
-  {
-  }
-
-  /// Construct a yield context from another yield context type.
-  /**
-   * Requires that OtherHandler be convertible to Handler.
-   */
-  template <typename OtherHandler>
-  basic_yield_context(const basic_yield_context<OtherHandler>& other)
-    : coro_(other.coro_),
-      ca_(other.ca_),
-      handler_(other.handler_),
-      ec_(other.ec_)
-  {
-  }
-
-  /// Return a yield context that sets the specified error_code.
-  /**
-   * By default, when a yield context is used with an asynchronous operation, a
-   * non-success error_code is converted to system_error and thrown. This
-   * operator may be used to specify an error_code object that should instead be
-   * set with the asynchronous operation's result. For example:
-   *
-   * @code template <typename Handler>
-   * void my_coroutine(basic_yield_context<Handler> yield)
-   * {
-   *   ...
-   *   std::size_t n = my_socket.async_read_some(buffer, yield[ec]);
-   *   if (ec)
-   *   {
-   *     // An error occurred.
-   *   }
-   *   ...
-   * } @endcode
-   */
-  basic_yield_context operator[](asio::error_code& ec) const
-  {
-    basic_yield_context tmp(*this);
-    tmp.ec_ = &ec;
-    return tmp;
-  }
-
-#if defined(GENERATING_DOCUMENTATION)
-private:
-#endif // defined(GENERATING_DOCUMENTATION)
-  detail::weak_ptr<callee_type> coro_;
-  caller_type& ca_;
-  Handler handler_;
-  asio::error_code* ec_;
-};
-
-#if defined(GENERATING_DOCUMENTATION)
-/// Context object that represents the currently executing coroutine.
-typedef basic_yield_context<unspecified> yield_context;
-#else // defined(GENERATING_DOCUMENTATION)
-typedef basic_yield_context<
-  executor_binder<void(*)(), executor> > yield_context;
-#endif // defined(GENERATING_DOCUMENTATION)
-
-/**
- * @defgroup spawn asio::spawn
- *
- * @brief Start a new stackful coroutine.
- *
- * The spawn() function is a high-level wrapper over the Boost.Coroutine
- * library. This function enables programs to implement asynchronous logic in a
- * synchronous manner, as illustrated by the following example:
- *
- * @code asio::spawn(my_strand, do_echo);
- *
- * // ...
- *
- * void do_echo(asio::yield_context yield)
- * {
- *   try
- *   {
- *     char data[128];
- *     for (;;)
- *     {
- *       std::size_t length =
- *         my_socket.async_read_some(
- *           asio::buffer(data), yield);
- *
- *       asio::async_write(my_socket,
- *           asio::buffer(data, length), yield);
- *     }
- *   }
- *   catch (std::exception& e)
- *   {
- *     // ...
- *   }
- * } @endcode
- */
-/*@{*/
-
-/// Start a new stackful coroutine, calling the specified handler when it
-/// completes.
-/**
- * This function is used to launch a new coroutine.
- *
- * @param function The coroutine function. The function must have the signature:
- * @code void function(basic_yield_context<Handler> yield); @endcode
- *
- * @param attributes Boost.Coroutine attributes used to customise the coroutine.
- */
-template <typename Function>
-void spawn(ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes
-      = boost::coroutines::attributes());
-
-/// Start a new stackful coroutine, calling the specified handler when it
-/// completes.
-/**
- * This function is used to launch a new coroutine.
- *
- * @param handler A handler to be called when the coroutine exits. More
- * importantly, the handler provides an execution context (via the the handler
- * invocation hook) for the coroutine. The handler must have the signature:
- * @code void handler(); @endcode
- *
- * @param function The coroutine function. The function must have the signature:
- * @code void function(basic_yield_context<Handler> yield); @endcode
- *
- * @param attributes Boost.Coroutine attributes used to customise the coroutine.
- */
-template <typename Handler, typename Function>
-void spawn(ASIO_MOVE_ARG(Handler) handler,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes
-      = boost::coroutines::attributes(),
-    typename enable_if<!is_executor<typename decay<Handler>::type>::value &&
-      !is_convertible<Handler&, execution_context&>::value>::type* = 0);
-
-/// Start a new stackful coroutine, inheriting the execution context of another.
-/**
- * This function is used to launch a new coroutine.
- *
- * @param ctx Identifies the current coroutine as a parent of the new
- * coroutine. This specifies that the new coroutine should inherit the
- * execution context of the parent. For example, if the parent coroutine is
- * executing in a particular strand, then the new coroutine will execute in the
- * same strand.
- *
- * @param function The coroutine function. The function must have the signature:
- * @code void function(basic_yield_context<Handler> yield); @endcode
- *
- * @param attributes Boost.Coroutine attributes used to customise the coroutine.
- */
-template <typename Handler, typename Function>
-void spawn(basic_yield_context<Handler> ctx,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes
-      = boost::coroutines::attributes());
-
-/// Start a new stackful coroutine that executes on a given executor.
-/**
- * This function is used to launch a new coroutine.
- *
- * @param ex Identifies the executor that will run the coroutine. The new
- * coroutine is implicitly given its own strand within this executor.
- *
- * @param function The coroutine function. The function must have the signature:
- * @code void function(yield_context yield); @endcode
- *
- * @param attributes Boost.Coroutine attributes used to customise the coroutine.
- */
-template <typename Function, typename Executor>
-void spawn(const Executor& ex,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes
-      = boost::coroutines::attributes(),
-    typename enable_if<is_executor<Executor>::value>::type* = 0);
-
-/// Start a new stackful coroutine that executes on a given strand.
-/**
- * This function is used to launch a new coroutine.
- *
- * @param ex Identifies the strand that will run the coroutine.
- *
- * @param function The coroutine function. The function must have the signature:
- * @code void function(yield_context yield); @endcode
- *
- * @param attributes Boost.Coroutine attributes used to customise the coroutine.
- */
-template <typename Function, typename Executor>
-void spawn(const strand<Executor>& ex,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes
-      = boost::coroutines::attributes());
-
-/// Start a new stackful coroutine that executes in the context of a strand.
-/**
- * This function is used to launch a new coroutine.
- *
- * @param s Identifies a strand. By starting multiple coroutines on the same
- * strand, the implementation ensures that none of those coroutines can execute
- * simultaneously.
- *
- * @param function The coroutine function. The function must have the signature:
- * @code void function(yield_context yield); @endcode
- *
- * @param attributes Boost.Coroutine attributes used to customise the coroutine.
- */
-template <typename Function>
-void spawn(const asio::io_context::strand& s,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes
-      = boost::coroutines::attributes());
-
-/// Start a new stackful coroutine that executes on a given execution context.
-/**
- * This function is used to launch a new coroutine.
- *
- * @param ctx Identifies the execution context that will run the coroutine. The
- * new coroutine is implicitly given its own strand within this execution
- * context.
- *
- * @param function The coroutine function. The function must have the signature:
- * @code void function(yield_context yield); @endcode
- *
- * @param attributes Boost.Coroutine attributes used to customise the coroutine.
- */
-template <typename Function, typename ExecutionContext>
-void spawn(ExecutionContext& ctx,
-    ASIO_MOVE_ARG(Function) function,
-    const boost::coroutines::attributes& attributes
-      = boost::coroutines::attributes(),
-    typename enable_if<is_convertible<
-      ExecutionContext&, execution_context&>::value>::type* = 0);
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/spawn.hpp"
-
-#endif // ASIO_SPAWN_HPP
diff --git a/tools/sdk/include/asio/asio/ssl.hpp b/tools/sdk/include/asio/asio/ssl.hpp
deleted file mode 100644
index cbad19d81cc..00000000000
--- a/tools/sdk/include/asio/asio/ssl.hpp
+++ /dev/null
@@ -1,27 +0,0 @@
-//
-// ssl.hpp
-// ~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_HPP
-#define ASIO_SSL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/ssl/context.hpp"
-#include "asio/ssl/context_base.hpp"
-#include "asio/ssl/error.hpp"
-#include "asio/ssl/rfc2818_verification.hpp"
-#include "asio/ssl/stream.hpp"
-#include "asio/ssl/stream_base.hpp"
-#include "asio/ssl/verify_context.hpp"
-#include "asio/ssl/verify_mode.hpp"
-
-#endif // ASIO_SSL_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/context.hpp b/tools/sdk/include/asio/asio/ssl/context.hpp
deleted file mode 100644
index 9543aab68e5..00000000000
--- a/tools/sdk/include/asio/asio/ssl/context.hpp
+++ /dev/null
@@ -1,758 +0,0 @@
-//
-// ssl/context.hpp
-// ~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_CONTEXT_HPP
-#define ASIO_SSL_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <string>
-#include "asio/buffer.hpp"
-#include "asio/io_context.hpp"
-#include "asio/ssl/context_base.hpp"
-#include "asio/ssl/detail/openssl_types.hpp"
-#include "asio/ssl/detail/openssl_init.hpp"
-#include "asio/ssl/detail/password_callback.hpp"
-#include "asio/ssl/detail/verify_callback.hpp"
-#include "asio/ssl/verify_mode.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-
-class context
-  : public context_base,
-    private noncopyable
-{
-public:
-  /// The native handle type of the SSL context.
-  typedef SSL_CTX* native_handle_type;
-
-  /// Constructor.
-  ASIO_DECL explicit context(method m);
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a context from another.
-  /**
-   * This constructor moves an SSL context from one object to another.
-   *
-   * @param other The other context object from which the move will occur.
-   *
-   * @note Following the move, the following operations only are valid for the
-   * moved-from object:
-   * @li Destruction.
-   * @li As a target for move-assignment.
-   */
-  ASIO_DECL context(context&& other);
-
-  /// Move-assign a context from another.
-  /**
-   * This assignment operator moves an SSL context from one object to another.
-   *
-   * @param other The other context object from which the move will occur.
-   *
-   * @note Following the move, the following operations only are valid for the
-   * moved-from object:
-   * @li Destruction.
-   * @li As a target for move-assignment.
-   */
-  ASIO_DECL context& operator=(context&& other);
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destructor.
-  ASIO_DECL ~context();
-
-  /// Get the underlying implementation in the native type.
-  /**
-   * This function may be used to obtain the underlying implementation of the
-   * context. This is intended to allow access to context functionality that is
-   * not otherwise provided.
-   */
-  ASIO_DECL native_handle_type native_handle();
-
-  /// Clear options on the context.
-  /**
-   * This function may be used to configure the SSL options used by the context.
-   *
-   * @param o A bitmask of options. The available option values are defined in
-   * the context_base class. The specified options, if currently enabled on the
-   * context, are cleared.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_clear_options.
-   */
-  ASIO_DECL void clear_options(options o);
-
-  /// Clear options on the context.
-  /**
-   * This function may be used to configure the SSL options used by the context.
-   *
-   * @param o A bitmask of options. The available option values are defined in
-   * the context_base class. The specified options, if currently enabled on the
-   * context, are cleared.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_clear_options.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID clear_options(options o,
-      asio::error_code& ec);
-
-  /// Set options on the context.
-  /**
-   * This function may be used to configure the SSL options used by the context.
-   *
-   * @param o A bitmask of options. The available option values are defined in
-   * the context_base class. The options are bitwise-ored with any existing
-   * value for the options.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_set_options.
-   */
-  ASIO_DECL void set_options(options o);
-
-  /// Set options on the context.
-  /**
-   * This function may be used to configure the SSL options used by the context.
-   *
-   * @param o A bitmask of options. The available option values are defined in
-   * the context_base class. The options are bitwise-ored with any existing
-   * value for the options.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_set_options.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID set_options(options o,
-      asio::error_code& ec);
-
-  /// Set the peer verification mode.
-  /**
-   * This function may be used to configure the peer verification mode used by
-   * the context.
-   *
-   * @param v A bitmask of peer verification modes. See @ref verify_mode for
-   * available values.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_set_verify.
-   */
-  ASIO_DECL void set_verify_mode(verify_mode v);
-
-  /// Set the peer verification mode.
-  /**
-   * This function may be used to configure the peer verification mode used by
-   * the context.
-   *
-   * @param v A bitmask of peer verification modes. See @ref verify_mode for
-   * available values.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_set_verify.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID set_verify_mode(
-      verify_mode v, asio::error_code& ec);
-
-  /// Set the peer verification depth.
-  /**
-   * This function may be used to configure the maximum verification depth
-   * allowed by the context.
-   *
-   * @param depth Maximum depth for the certificate chain verification that
-   * shall be allowed.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_set_verify_depth.
-   */
-  ASIO_DECL void set_verify_depth(int depth);
-
-  /// Set the peer verification depth.
-  /**
-   * This function may be used to configure the maximum verification depth
-   * allowed by the context.
-   *
-   * @param depth Maximum depth for the certificate chain verification that
-   * shall be allowed.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_set_verify_depth.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID set_verify_depth(
-      int depth, asio::error_code& ec);
-
-  /// Set the callback used to verify peer certificates.
-  /**
-   * This function is used to specify a callback function that will be called
-   * by the implementation when it needs to verify a peer certificate.
-   *
-   * @param callback The function object to be used for verifying a certificate.
-   * The function signature of the handler must be:
-   * @code bool verify_callback(
-   *   bool preverified, // True if the certificate passed pre-verification.
-   *   verify_context& ctx // The peer certificate and other context.
-   * ); @endcode
-   * The return value of the callback is true if the certificate has passed
-   * verification, false otherwise.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_set_verify.
-   */
-  template <typename VerifyCallback>
-  void set_verify_callback(VerifyCallback callback);
-
-  /// Set the callback used to verify peer certificates.
-  /**
-   * This function is used to specify a callback function that will be called
-   * by the implementation when it needs to verify a peer certificate.
-   *
-   * @param callback The function object to be used for verifying a certificate.
-   * The function signature of the handler must be:
-   * @code bool verify_callback(
-   *   bool preverified, // True if the certificate passed pre-verification.
-   *   verify_context& ctx // The peer certificate and other context.
-   * ); @endcode
-   * The return value of the callback is true if the certificate has passed
-   * verification, false otherwise.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_set_verify.
-   */
-  template <typename VerifyCallback>
-  ASIO_SYNC_OP_VOID set_verify_callback(VerifyCallback callback,
-      asio::error_code& ec);
-
-  /// Load a certification authority file for performing verification.
-  /**
-   * This function is used to load one or more trusted certification authorities
-   * from a file.
-   *
-   * @param filename The name of a file containing certification authority
-   * certificates in PEM format.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_load_verify_locations.
-   */
-  ASIO_DECL void load_verify_file(const std::string& filename);
-
-  /// Load a certification authority file for performing verification.
-  /**
-   * This function is used to load the certificates for one or more trusted
-   * certification authorities from a file.
-   *
-   * @param filename The name of a file containing certification authority
-   * certificates in PEM format.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_load_verify_locations.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID load_verify_file(
-      const std::string& filename, asio::error_code& ec);
-
-  /// Add certification authority for performing verification.
-  /**
-   * This function is used to add one trusted certification authority
-   * from a memory buffer.
-   *
-   * @param ca The buffer containing the certification authority certificate.
-   * The certificate must use the PEM format.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_get_cert_store and @c X509_STORE_add_cert.
-   */
-  ASIO_DECL void add_certificate_authority(const const_buffer& ca);
-
-  /// Add certification authority for performing verification.
-  /**
-   * This function is used to add one trusted certification authority
-   * from a memory buffer.
-   *
-   * @param ca The buffer containing the certification authority certificate.
-   * The certificate must use the PEM format.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_get_cert_store and @c X509_STORE_add_cert.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID add_certificate_authority(
-      const const_buffer& ca, asio::error_code& ec);
-
-  /// Configures the context to use the default directories for finding
-  /// certification authority certificates.
-  /**
-   * This function specifies that the context should use the default,
-   * system-dependent directories for locating certification authority
-   * certificates.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_set_default_verify_paths.
-   */
-  ASIO_DECL void set_default_verify_paths();
-
-  /// Configures the context to use the default directories for finding
-  /// certification authority certificates.
-  /**
-   * This function specifies that the context should use the default,
-   * system-dependent directories for locating certification authority
-   * certificates.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_set_default_verify_paths.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID set_default_verify_paths(
-      asio::error_code& ec);
-
-  /// Add a directory containing certificate authority files to be used for
-  /// performing verification.
-  /**
-   * This function is used to specify the name of a directory containing
-   * certification authority certificates. Each file in the directory must
-   * contain a single certificate. The files must be named using the subject
-   * name's hash and an extension of ".0".
-   *
-   * @param path The name of a directory containing the certificates.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_load_verify_locations.
-   */
-  ASIO_DECL void add_verify_path(const std::string& path);
-
-  /// Add a directory containing certificate authority files to be used for
-  /// performing verification.
-  /**
-   * This function is used to specify the name of a directory containing
-   * certification authority certificates. Each file in the directory must
-   * contain a single certificate. The files must be named using the subject
-   * name's hash and an extension of ".0".
-   *
-   * @param path The name of a directory containing the certificates.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_load_verify_locations.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID add_verify_path(
-      const std::string& path, asio::error_code& ec);
-
-  /// Use a certificate from a memory buffer.
-  /**
-   * This function is used to load a certificate into the context from a buffer.
-   *
-   * @param certificate The buffer containing the certificate.
-   *
-   * @param format The certificate format (ASN.1 or PEM).
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_use_certificate or SSL_CTX_use_certificate_ASN1.
-   */
-  ASIO_DECL void use_certificate(
-      const const_buffer& certificate, file_format format);
-
-  /// Use a certificate from a memory buffer.
-  /**
-   * This function is used to load a certificate into the context from a buffer.
-   *
-   * @param certificate The buffer containing the certificate.
-   *
-   * @param format The certificate format (ASN.1 or PEM).
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_use_certificate or SSL_CTX_use_certificate_ASN1.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_certificate(
-      const const_buffer& certificate, file_format format,
-      asio::error_code& ec);
-
-  /// Use a certificate from a file.
-  /**
-   * This function is used to load a certificate into the context from a file.
-   *
-   * @param filename The name of the file containing the certificate.
-   *
-   * @param format The file format (ASN.1 or PEM).
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_use_certificate_file.
-   */
-  ASIO_DECL void use_certificate_file(
-      const std::string& filename, file_format format);
-
-  /// Use a certificate from a file.
-  /**
-   * This function is used to load a certificate into the context from a file.
-   *
-   * @param filename The name of the file containing the certificate.
-   *
-   * @param format The file format (ASN.1 or PEM).
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_use_certificate_file.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_certificate_file(
-      const std::string& filename, file_format format,
-      asio::error_code& ec);
-
-  /// Use a certificate chain from a memory buffer.
-  /**
-   * This function is used to load a certificate chain into the context from a
-   * buffer.
-   *
-   * @param chain The buffer containing the certificate chain. The certificate
-   * chain must use the PEM format.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_use_certificate and SSL_CTX_add_extra_chain_cert.
-   */
-  ASIO_DECL void use_certificate_chain(const const_buffer& chain);
-
-  /// Use a certificate chain from a memory buffer.
-  /**
-   * This function is used to load a certificate chain into the context from a
-   * buffer.
-   *
-   * @param chain The buffer containing the certificate chain. The certificate
-   * chain must use the PEM format.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_use_certificate and SSL_CTX_add_extra_chain_cert.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_certificate_chain(
-      const const_buffer& chain, asio::error_code& ec);
-
-  /// Use a certificate chain from a file.
-  /**
-   * This function is used to load a certificate chain into the context from a
-   * file.
-   *
-   * @param filename The name of the file containing the certificate. The file
-   * must use the PEM format.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_use_certificate_chain_file.
-   */
-  ASIO_DECL void use_certificate_chain_file(const std::string& filename);
-
-  /// Use a certificate chain from a file.
-  /**
-   * This function is used to load a certificate chain into the context from a
-   * file.
-   *
-   * @param filename The name of the file containing the certificate. The file
-   * must use the PEM format.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_use_certificate_chain_file.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_certificate_chain_file(
-      const std::string& filename, asio::error_code& ec);
-
-  /// Use a private key from a memory buffer.
-  /**
-   * This function is used to load a private key into the context from a buffer.
-   *
-   * @param private_key The buffer containing the private key.
-   *
-   * @param format The private key format (ASN.1 or PEM).
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_use_PrivateKey or SSL_CTX_use_PrivateKey_ASN1.
-   */
-  ASIO_DECL void use_private_key(
-      const const_buffer& private_key, file_format format);
-
-  /// Use a private key from a memory buffer.
-  /**
-   * This function is used to load a private key into the context from a buffer.
-   *
-   * @param private_key The buffer containing the private key.
-   *
-   * @param format The private key format (ASN.1 or PEM).
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_use_PrivateKey or SSL_CTX_use_PrivateKey_ASN1.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_private_key(
-      const const_buffer& private_key, file_format format,
-      asio::error_code& ec);
-
-  /// Use a private key from a file.
-  /**
-   * This function is used to load a private key into the context from a file.
-   *
-   * @param filename The name of the file containing the private key.
-   *
-   * @param format The file format (ASN.1 or PEM).
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_use_PrivateKey_file.
-   */
-  ASIO_DECL void use_private_key_file(
-      const std::string& filename, file_format format);
-
-  /// Use a private key from a file.
-  /**
-   * This function is used to load a private key into the context from a file.
-   *
-   * @param filename The name of the file containing the private key.
-   *
-   * @param format The file format (ASN.1 or PEM).
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_use_PrivateKey_file.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_private_key_file(
-      const std::string& filename, file_format format,
-      asio::error_code& ec);
-
-  /// Use an RSA private key from a memory buffer.
-  /**
-   * This function is used to load an RSA private key into the context from a
-   * buffer.
-   *
-   * @param private_key The buffer containing the RSA private key.
-   *
-   * @param format The private key format (ASN.1 or PEM).
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_use_RSAPrivateKey or SSL_CTX_use_RSAPrivateKey_ASN1.
-   */
-  ASIO_DECL void use_rsa_private_key(
-      const const_buffer& private_key, file_format format);
-
-  /// Use an RSA private key from a memory buffer.
-  /**
-   * This function is used to load an RSA private key into the context from a
-   * buffer.
-   *
-   * @param private_key The buffer containing the RSA private key.
-   *
-   * @param format The private key format (ASN.1 or PEM).
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_use_RSAPrivateKey or SSL_CTX_use_RSAPrivateKey_ASN1.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_rsa_private_key(
-      const const_buffer& private_key, file_format format,
-      asio::error_code& ec);
-
-  /// Use an RSA private key from a file.
-  /**
-   * This function is used to load an RSA private key into the context from a
-   * file.
-   *
-   * @param filename The name of the file containing the RSA private key.
-   *
-   * @param format The file format (ASN.1 or PEM).
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_use_RSAPrivateKey_file.
-   */
-  ASIO_DECL void use_rsa_private_key_file(
-      const std::string& filename, file_format format);
-
-  /// Use an RSA private key from a file.
-  /**
-   * This function is used to load an RSA private key into the context from a
-   * file.
-   *
-   * @param filename The name of the file containing the RSA private key.
-   *
-   * @param format The file format (ASN.1 or PEM).
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_use_RSAPrivateKey_file.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_rsa_private_key_file(
-      const std::string& filename, file_format format,
-      asio::error_code& ec);
-
-  /// Use the specified memory buffer to obtain the temporary Diffie-Hellman
-  /// parameters.
-  /**
-   * This function is used to load Diffie-Hellman parameters into the context
-   * from a buffer.
-   *
-   * @param dh The memory buffer containing the Diffie-Hellman parameters. The
-   * buffer must use the PEM format.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_set_tmp_dh.
-   */
-  ASIO_DECL void use_tmp_dh(const const_buffer& dh);
-
-  /// Use the specified memory buffer to obtain the temporary Diffie-Hellman
-  /// parameters.
-  /**
-   * This function is used to load Diffie-Hellman parameters into the context
-   * from a buffer.
-   *
-   * @param dh The memory buffer containing the Diffie-Hellman parameters. The
-   * buffer must use the PEM format.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_set_tmp_dh.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_tmp_dh(
-      const const_buffer& dh, asio::error_code& ec);
-
-  /// Use the specified file to obtain the temporary Diffie-Hellman parameters.
-  /**
-   * This function is used to load Diffie-Hellman parameters into the context
-   * from a file.
-   *
-   * @param filename The name of the file containing the Diffie-Hellman
-   * parameters. The file must use the PEM format.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_set_tmp_dh.
-   */
-  ASIO_DECL void use_tmp_dh_file(const std::string& filename);
-
-  /// Use the specified file to obtain the temporary Diffie-Hellman parameters.
-  /**
-   * This function is used to load Diffie-Hellman parameters into the context
-   * from a file.
-   *
-   * @param filename The name of the file containing the Diffie-Hellman
-   * parameters. The file must use the PEM format.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_set_tmp_dh.
-   */
-  ASIO_DECL ASIO_SYNC_OP_VOID use_tmp_dh_file(
-      const std::string& filename, asio::error_code& ec);
-
-  /// Set the password callback.
-  /**
-   * This function is used to specify a callback function to obtain password
-   * information about an encrypted key in PEM format.
-   *
-   * @param callback The function object to be used for obtaining the password.
-   * The function signature of the handler must be:
-   * @code std::string password_callback(
-   *   std::size_t max_length,  // The maximum size for a password.
-   *   password_purpose purpose // Whether password is for reading or writing.
-   * ); @endcode
-   * The return value of the callback is a string containing the password.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_CTX_set_default_passwd_cb.
-   */
-  template <typename PasswordCallback>
-  void set_password_callback(PasswordCallback callback);
-
-  /// Set the password callback.
-  /**
-   * This function is used to specify a callback function to obtain password
-   * information about an encrypted key in PEM format.
-   *
-   * @param callback The function object to be used for obtaining the password.
-   * The function signature of the handler must be:
-   * @code std::string password_callback(
-   *   std::size_t max_length,  // The maximum size for a password.
-   *   password_purpose purpose // Whether password is for reading or writing.
-   * ); @endcode
-   * The return value of the callback is a string containing the password.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_CTX_set_default_passwd_cb.
-   */
-  template <typename PasswordCallback>
-  ASIO_SYNC_OP_VOID set_password_callback(PasswordCallback callback,
-      asio::error_code& ec);
-
-private:
-  struct bio_cleanup;
-  struct x509_cleanup;
-  struct evp_pkey_cleanup;
-  struct rsa_cleanup;
-  struct dh_cleanup;
-
-  // Helper function used to set a peer certificate verification callback.
-  ASIO_DECL ASIO_SYNC_OP_VOID do_set_verify_callback(
-      detail::verify_callback_base* callback, asio::error_code& ec);
-
-  // Callback used when the SSL implementation wants to verify a certificate.
-  ASIO_DECL static int verify_callback_function(
-      int preverified, X509_STORE_CTX* ctx);
-
-  // Helper function used to set a password callback.
-  ASIO_DECL ASIO_SYNC_OP_VOID do_set_password_callback(
-      detail::password_callback_base* callback, asio::error_code& ec);
-
-  // Callback used when the SSL implementation wants a password.
-  ASIO_DECL static int password_callback_function(
-      char* buf, int size, int purpose, void* data);
-
-  // Helper function to set the temporary Diffie-Hellman parameters from a BIO.
-  ASIO_DECL ASIO_SYNC_OP_VOID do_use_tmp_dh(
-      BIO* bio, asio::error_code& ec);
-
-  // Helper function to make a BIO from a memory buffer.
-  ASIO_DECL BIO* make_buffer_bio(const const_buffer& b);
-
-  // The underlying native implementation.
-  native_handle_type handle_;
-
-  // Ensure openssl is initialised.
-  asio::ssl::detail::openssl_init<> init_;
-};
-
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/ssl/impl/context.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ssl/impl/context.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_SSL_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/context_base.hpp b/tools/sdk/include/asio/asio/ssl/context_base.hpp
deleted file mode 100644
index 56c76936e0c..00000000000
--- a/tools/sdk/include/asio/asio/ssl/context_base.hpp
+++ /dev/null
@@ -1,192 +0,0 @@
-//
-// ssl/context_base.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_CONTEXT_BASE_HPP
-#define ASIO_SSL_CONTEXT_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/ssl/detail/openssl_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-
-/// The context_base class is used as a base for the basic_context class
-/// template so that we have a common place to define various enums.
-class context_base
-{
-public:
-  /// Different methods supported by a context.
-  enum method
-  {
-    /// Generic SSL version 2.
-    sslv2,
-
-    /// SSL version 2 client.
-    sslv2_client,
-
-    /// SSL version 2 server.
-    sslv2_server,
-
-    /// Generic SSL version 3.
-    sslv3,
-
-    /// SSL version 3 client.
-    sslv3_client,
-
-    /// SSL version 3 server.
-    sslv3_server,
-
-    /// Generic TLS version 1.
-    tlsv1,
-
-    /// TLS version 1 client.
-    tlsv1_client,
-
-    /// TLS version 1 server.
-    tlsv1_server,
-
-    /// Generic SSL/TLS.
-    sslv23,
-
-    /// SSL/TLS client.
-    sslv23_client,
-
-    /// SSL/TLS server.
-    sslv23_server,
-
-    /// Generic TLS version 1.1.
-    tlsv11,
-
-    /// TLS version 1.1 client.
-    tlsv11_client,
-
-    /// TLS version 1.1 server.
-    tlsv11_server,
-
-    /// Generic TLS version 1.2.
-    tlsv12,
-
-    /// TLS version 1.2 client.
-    tlsv12_client,
-
-    /// TLS version 1.2 server.
-    tlsv12_server,
-
-    /// Generic TLS.
-    tls,
-
-    /// TLS client.
-    tls_client,
-
-    /// TLS server.
-    tls_server
-  };
-
-  /// Bitmask type for SSL options.
-  typedef long options;
-
-#if defined(GENERATING_DOCUMENTATION)
-  /// Implement various bug workarounds.
-  static const long default_workarounds = implementation_defined;
-
-  /// Always create a new key when using tmp_dh parameters.
-  static const long single_dh_use = implementation_defined;
-
-  /// Disable SSL v2.
-  static const long no_sslv2 = implementation_defined;
-
-  /// Disable SSL v3.
-  static const long no_sslv3 = implementation_defined;
-
-  /// Disable TLS v1.
-  static const long no_tlsv1 = implementation_defined;
-
-  /// Disable TLS v1.1.
-  static const long no_tlsv1_1 = implementation_defined;
-
-  /// Disable TLS v1.2.
-  static const long no_tlsv1_2 = implementation_defined;
-
-  /// Disable compression. Compression is disabled by default.
-  static const long no_compression = implementation_defined;
-#else
-  ASIO_STATIC_CONSTANT(long, default_workarounds = SSL_OP_ALL);
-  ASIO_STATIC_CONSTANT(long, single_dh_use = SSL_OP_SINGLE_DH_USE);
-  ASIO_STATIC_CONSTANT(long, no_sslv2 = SSL_OP_NO_SSLv2);
-  ASIO_STATIC_CONSTANT(long, no_sslv3 = SSL_OP_NO_SSLv3);
-  ASIO_STATIC_CONSTANT(long, no_tlsv1 = SSL_OP_NO_TLSv1);
-# if defined(SSL_OP_NO_TLSv1_1)
-  ASIO_STATIC_CONSTANT(long, no_tlsv1_1 = SSL_OP_NO_TLSv1_1);
-# else // defined(SSL_OP_NO_TLSv1_1)
-  ASIO_STATIC_CONSTANT(long, no_tlsv1_1 = 0x10000000L);
-# endif // defined(SSL_OP_NO_TLSv1_1)
-# if defined(SSL_OP_NO_TLSv1_2)
-  ASIO_STATIC_CONSTANT(long, no_tlsv1_2 = SSL_OP_NO_TLSv1_2);
-# else // defined(SSL_OP_NO_TLSv1_2)
-  ASIO_STATIC_CONSTANT(long, no_tlsv1_2 = 0x08000000L);
-# endif // defined(SSL_OP_NO_TLSv1_2)
-# if defined(SSL_OP_NO_COMPRESSION)
-  ASIO_STATIC_CONSTANT(long, no_compression = SSL_OP_NO_COMPRESSION);
-# else // defined(SSL_OP_NO_COMPRESSION)
-  ASIO_STATIC_CONSTANT(long, no_compression = 0x20000L);
-# endif // defined(SSL_OP_NO_COMPRESSION)
-#endif
-
-  /// File format types.
-  enum file_format
-  {
-    /// ASN.1 file.
-    asn1,
-
-    /// PEM file.
-    pem
-  };
-
-#if !defined(GENERATING_DOCUMENTATION)
-  // The following types and constants are preserved for backward compatibility.
-  // New programs should use the equivalents of the same names that are defined
-  // in the asio::ssl namespace.
-  typedef int verify_mode;
-  ASIO_STATIC_CONSTANT(int, verify_none = SSL_VERIFY_NONE);
-  ASIO_STATIC_CONSTANT(int, verify_peer = SSL_VERIFY_PEER);
-  ASIO_STATIC_CONSTANT(int,
-      verify_fail_if_no_peer_cert = SSL_VERIFY_FAIL_IF_NO_PEER_CERT);
-  ASIO_STATIC_CONSTANT(int, verify_client_once = SSL_VERIFY_CLIENT_ONCE);
-#endif
-
-  /// Purpose of PEM password.
-  enum password_purpose
-  {
-    /// The password is needed for reading/decryption.
-    for_reading,
-
-    /// The password is needed for writing/encryption.
-    for_writing
-  };
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  ~context_base()
-  {
-  }
-};
-
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_CONTEXT_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/buffered_handshake_op.hpp b/tools/sdk/include/asio/asio/ssl/detail/buffered_handshake_op.hpp
deleted file mode 100644
index 38a03fcce97..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/buffered_handshake_op.hpp
+++ /dev/null
@@ -1,114 +0,0 @@
-//
-// ssl/detail/buffered_handshake_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_BUFFERED_HANDSHAKE_OP_HPP
-#define ASIO_SSL_DETAIL_BUFFERED_HANDSHAKE_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/ssl/detail/engine.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-template <typename ConstBufferSequence>
-class buffered_handshake_op
-{
-public:
-  buffered_handshake_op(stream_base::handshake_type type,
-      const ConstBufferSequence& buffers)
-    : type_(type),
-      buffers_(buffers),
-      total_buffer_size_(asio::buffer_size(buffers_))
-  {
-  }
-
-  engine::want operator()(engine& eng,
-      asio::error_code& ec,
-      std::size_t& bytes_transferred) const
-  {
-    return this->process(eng, ec, bytes_transferred,
-        asio::buffer_sequence_begin(buffers_),
-        asio::buffer_sequence_end(buffers_));
-  }
-
-  template <typename Handler>
-  void call_handler(Handler& handler,
-      const asio::error_code& ec,
-      const std::size_t& bytes_transferred) const
-  {
-    handler(ec, bytes_transferred);
-  }
-
-private:
-  template <typename Iterator>
-  engine::want process(engine& eng,
-      asio::error_code& ec,
-      std::size_t& bytes_transferred,
-      Iterator begin, Iterator end) const
-  {
-    Iterator iter = begin;
-    std::size_t accumulated_size = 0;
-
-    for (;;)
-    {
-      engine::want want = eng.handshake(type_, ec);
-      if (want != engine::want_input_and_retry
-          || bytes_transferred == total_buffer_size_)
-        return want;
-
-      // Find the next buffer piece to be fed to the engine.
-      while (iter != end)
-      {
-        const_buffer buffer(*iter);
-
-        // Skip over any buffers which have already been consumed by the engine.
-        if (bytes_transferred >= accumulated_size + buffer.size())
-        {
-          accumulated_size += buffer.size();
-          ++iter;
-          continue;
-        }
-
-        // The current buffer may have been partially consumed by the engine on
-        // a previous iteration. If so, adjust the buffer to point to the
-        // unused portion.
-        if (bytes_transferred > accumulated_size)
-          buffer = buffer + (bytes_transferred - accumulated_size);
-
-        // Pass the buffer to the engine, and update the bytes transferred to
-        // reflect the total number of bytes consumed so far.
-        bytes_transferred += buffer.size();
-        buffer = eng.put_input(buffer);
-        bytes_transferred -= buffer.size();
-        break;
-      }
-    }
-  }
-
-  stream_base::handshake_type type_;
-  ConstBufferSequence buffers_;
-  std::size_t total_buffer_size_;
-};
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_DETAIL_BUFFERED_HANDSHAKE_OP_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/engine.hpp b/tools/sdk/include/asio/asio/ssl/detail/engine.hpp
deleted file mode 100644
index 2f033d66cf1..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/engine.hpp
+++ /dev/null
@@ -1,160 +0,0 @@
-//
-// ssl/detail/engine.hpp
-// ~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_ENGINE_HPP
-#define ASIO_SSL_DETAIL_ENGINE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/buffer.hpp"
-#include "asio/detail/static_mutex.hpp"
-#include "asio/ssl/detail/openssl_types.hpp"
-#include "asio/ssl/detail/verify_callback.hpp"
-#include "asio/ssl/stream_base.hpp"
-#include "asio/ssl/verify_mode.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-class engine
-{
-public:
-  enum want
-  {
-    // Returned by functions to indicate that the engine wants input. The input
-    // buffer should be updated to point to the data. The engine then needs to
-    // be called again to retry the operation.
-    want_input_and_retry = -2,
-
-    // Returned by functions to indicate that the engine wants to write output.
-    // The output buffer points to the data to be written. The engine then
-    // needs to be called again to retry the operation.
-    want_output_and_retry = -1,
-
-    // Returned by functions to indicate that the engine doesn't need input or
-    // output.
-    want_nothing = 0,
-
-    // Returned by functions to indicate that the engine wants to write output.
-    // The output buffer points to the data to be written. After that the
-    // operation is complete, and the engine does not need to be called again.
-    want_output = 1
-  };
-
-  // Construct a new engine for the specified context.
-  ASIO_DECL explicit engine(SSL_CTX* context);
-
-  // Destructor.
-  ASIO_DECL ~engine();
-
-  // Get the underlying implementation in the native type.
-  ASIO_DECL SSL* native_handle();
-
-  // Set the peer verification mode.
-  ASIO_DECL asio::error_code set_verify_mode(
-      verify_mode v, asio::error_code& ec);
-
-  // Set the peer verification depth.
-  ASIO_DECL asio::error_code set_verify_depth(
-      int depth, asio::error_code& ec);
-
-  // Set a peer certificate verification callback.
-  ASIO_DECL asio::error_code set_verify_callback(
-      verify_callback_base* callback, asio::error_code& ec);
-
-  // Perform an SSL handshake using either SSL_connect (client-side) or
-  // SSL_accept (server-side).
-  ASIO_DECL want handshake(
-      stream_base::handshake_type type, asio::error_code& ec);
-
-  // Perform a graceful shutdown of the SSL session.
-  ASIO_DECL want shutdown(asio::error_code& ec);
-
-  // Write bytes to the SSL session.
-  ASIO_DECL want write(const asio::const_buffer& data,
-      asio::error_code& ec, std::size_t& bytes_transferred);
-
-  // Read bytes from the SSL session.
-  ASIO_DECL want read(const asio::mutable_buffer& data,
-      asio::error_code& ec, std::size_t& bytes_transferred);
-
-  // Get output data to be written to the transport.
-  ASIO_DECL asio::mutable_buffer get_output(
-      const asio::mutable_buffer& data);
-
-  // Put input data that was read from the transport.
-  ASIO_DECL asio::const_buffer put_input(
-      const asio::const_buffer& data);
-
-  // Map an error::eof code returned by the underlying transport according to
-  // the type and state of the SSL session. Returns a const reference to the
-  // error code object, suitable for passing to a completion handler.
-  ASIO_DECL const asio::error_code& map_error_code(
-      asio::error_code& ec) const;
-
-private:
-  // Disallow copying and assignment.
-  engine(const engine&);
-  engine& operator=(const engine&);
-
-  // Callback used when the SSL implementation wants to verify a certificate.
-  ASIO_DECL static int verify_callback_function(
-      int preverified, X509_STORE_CTX* ctx);
-
-#if (OPENSSL_VERSION_NUMBER < 0x10000000L)
-  // The SSL_accept function may not be thread safe. This mutex is used to
-  // protect all calls to the SSL_accept function.
-  ASIO_DECL static asio::detail::static_mutex& accept_mutex();
-#endif // (OPENSSL_VERSION_NUMBER < 0x10000000L)
-
-  // Perform one operation. Returns >= 0 on success or error, want_read if the
-  // operation needs more input, or want_write if it needs to write some output
-  // before the operation can complete.
-  ASIO_DECL want perform(int (engine::* op)(void*, std::size_t),
-      void* data, std::size_t length, asio::error_code& ec,
-      std::size_t* bytes_transferred);
-
-  // Adapt the SSL_accept function to the signature needed for perform().
-  ASIO_DECL int do_accept(void*, std::size_t);
-
-  // Adapt the SSL_connect function to the signature needed for perform().
-  ASIO_DECL int do_connect(void*, std::size_t);
-
-  // Adapt the SSL_shutdown function to the signature needed for perform().
-  ASIO_DECL int do_shutdown(void*, std::size_t);
-
-  // Adapt the SSL_read function to the signature needed for perform().
-  ASIO_DECL int do_read(void* data, std::size_t length);
-
-  // Adapt the SSL_write function to the signature needed for perform().
-  ASIO_DECL int do_write(void* data, std::size_t length);
-
-  SSL* ssl_;
-  BIO* ext_bio_;
-};
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ssl/detail/impl/engine.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_SSL_DETAIL_ENGINE_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/handshake_op.hpp b/tools/sdk/include/asio/asio/ssl/detail/handshake_op.hpp
deleted file mode 100644
index f782023a1b0..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/handshake_op.hpp
+++ /dev/null
@@ -1,62 +0,0 @@
-//
-// ssl/detail/handshake_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_HANDSHAKE_OP_HPP
-#define ASIO_SSL_DETAIL_HANDSHAKE_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/ssl/detail/engine.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-class handshake_op
-{
-public:
-  handshake_op(stream_base::handshake_type type)
-    : type_(type)
-  {
-  }
-
-  engine::want operator()(engine& eng,
-      asio::error_code& ec,
-      std::size_t& bytes_transferred) const
-  {
-    bytes_transferred = 0;
-    return eng.handshake(type_, ec);
-  }
-
-  template <typename Handler>
-  void call_handler(Handler& handler,
-      const asio::error_code& ec,
-      const std::size_t&) const
-  {
-    handler(ec);
-  }
-
-private:
-  stream_base::handshake_type type_;
-};
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_DETAIL_HANDSHAKE_OP_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/io.hpp b/tools/sdk/include/asio/asio/ssl/detail/io.hpp
deleted file mode 100644
index 0b0e51a2044..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/io.hpp
+++ /dev/null
@@ -1,372 +0,0 @@
-//
-// ssl/detail/io.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_IO_HPP
-#define ASIO_SSL_DETAIL_IO_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/ssl/detail/engine.hpp"
-#include "asio/ssl/detail/stream_core.hpp"
-#include "asio/write.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-template <typename Stream, typename Operation>
-std::size_t io(Stream& next_layer, stream_core& core,
-    const Operation& op, asio::error_code& ec)
-{
-  std::size_t bytes_transferred = 0;
-  do switch (op(core.engine_, ec, bytes_transferred))
-  {
-  case engine::want_input_and_retry:
-
-    // If the input buffer is empty then we need to read some more data from
-    // the underlying transport.
-    if (core.input_.size() == 0)
-      core.input_ = asio::buffer(core.input_buffer_,
-          next_layer.read_some(core.input_buffer_, ec));
-
-    // Pass the new input data to the engine.
-    core.input_ = core.engine_.put_input(core.input_);
-
-    // Try the operation again.
-    continue;
-
-  case engine::want_output_and_retry:
-
-    // Get output data from the engine and write it to the underlying
-    // transport.
-    asio::write(next_layer,
-        core.engine_.get_output(core.output_buffer_), ec);
-
-    // Try the operation again.
-    continue;
-
-  case engine::want_output:
-
-    // Get output data from the engine and write it to the underlying
-    // transport.
-    asio::write(next_layer,
-        core.engine_.get_output(core.output_buffer_), ec);
-
-    // Operation is complete. Return result to caller.
-    core.engine_.map_error_code(ec);
-    return bytes_transferred;
-
-  default:
-
-    // Operation is complete. Return result to caller.
-    core.engine_.map_error_code(ec);
-    return bytes_transferred;
-
-  } while (!ec);
-
-  // Operation failed. Return result to caller.
-  core.engine_.map_error_code(ec);
-  return 0;
-}
-
-template <typename Stream, typename Operation, typename Handler>
-class io_op
-{
-public:
-  io_op(Stream& next_layer, stream_core& core,
-      const Operation& op, Handler& handler)
-    : next_layer_(next_layer),
-      core_(core),
-      op_(op),
-      start_(0),
-      want_(engine::want_nothing),
-      bytes_transferred_(0),
-      handler_(ASIO_MOVE_CAST(Handler)(handler))
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE)
-  io_op(const io_op& other)
-    : next_layer_(other.next_layer_),
-      core_(other.core_),
-      op_(other.op_),
-      start_(other.start_),
-      want_(other.want_),
-      ec_(other.ec_),
-      bytes_transferred_(other.bytes_transferred_),
-      handler_(other.handler_)
-  {
-  }
-
-  io_op(io_op&& other)
-    : next_layer_(other.next_layer_),
-      core_(other.core_),
-      op_(ASIO_MOVE_CAST(Operation)(other.op_)),
-      start_(other.start_),
-      want_(other.want_),
-      ec_(other.ec_),
-      bytes_transferred_(other.bytes_transferred_),
-      handler_(ASIO_MOVE_CAST(Handler)(other.handler_))
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE)
-
-  void operator()(asio::error_code ec,
-      std::size_t bytes_transferred = ~std::size_t(0), int start = 0)
-  {
-    switch (start_ = start)
-    {
-    case 1: // Called after at least one async operation.
-      do
-      {
-        switch (want_ = op_(core_.engine_, ec_, bytes_transferred_))
-        {
-        case engine::want_input_and_retry:
-
-          // If the input buffer already has data in it we can pass it to the
-          // engine and then retry the operation immediately.
-          if (core_.input_.size() != 0)
-          {
-            core_.input_ = core_.engine_.put_input(core_.input_);
-            continue;
-          }
-
-          // The engine wants more data to be read from input. However, we
-          // cannot allow more than one read operation at a time on the
-          // underlying transport. The pending_read_ timer's expiry is set to
-          // pos_infin if a read is in progress, and neg_infin otherwise.
-          if (core_.expiry(core_.pending_read_) == core_.neg_infin())
-          {
-            // Prevent other read operations from being started.
-            core_.pending_read_.expires_at(core_.pos_infin());
-
-            // Start reading some data from the underlying transport.
-            next_layer_.async_read_some(
-                asio::buffer(core_.input_buffer_),
-                ASIO_MOVE_CAST(io_op)(*this));
-          }
-          else
-          {
-            // Wait until the current read operation completes.
-            core_.pending_read_.async_wait(ASIO_MOVE_CAST(io_op)(*this));
-          }
-
-          // Yield control until asynchronous operation completes. Control
-          // resumes at the "default:" label below.
-          return;
-
-        case engine::want_output_and_retry:
-        case engine::want_output:
-
-          // The engine wants some data to be written to the output. However, we
-          // cannot allow more than one write operation at a time on the
-          // underlying transport. The pending_write_ timer's expiry is set to
-          // pos_infin if a write is in progress, and neg_infin otherwise.
-          if (core_.expiry(core_.pending_write_) == core_.neg_infin())
-          {
-            // Prevent other write operations from being started.
-            core_.pending_write_.expires_at(core_.pos_infin());
-
-            // Start writing all the data to the underlying transport.
-            asio::async_write(next_layer_,
-                core_.engine_.get_output(core_.output_buffer_),
-                ASIO_MOVE_CAST(io_op)(*this));
-          }
-          else
-          {
-            // Wait until the current write operation completes.
-            core_.pending_write_.async_wait(ASIO_MOVE_CAST(io_op)(*this));
-          }
-
-          // Yield control until asynchronous operation completes. Control
-          // resumes at the "default:" label below.
-          return;
-
-        default:
-
-          // The SSL operation is done and we can invoke the handler, but we
-          // have to keep in mind that this function might be being called from
-          // the async operation's initiating function. In this case we're not
-          // allowed to call the handler directly. Instead, issue a zero-sized
-          // read so the handler runs "as-if" posted using io_context::post().
-          if (start)
-          {
-            next_layer_.async_read_some(
-                asio::buffer(core_.input_buffer_, 0),
-                ASIO_MOVE_CAST(io_op)(*this));
-
-            // Yield control until asynchronous operation completes. Control
-            // resumes at the "default:" label below.
-            return;
-          }
-          else
-          {
-            // Continue on to run handler directly.
-            break;
-          }
-        }
-
-        default:
-        if (bytes_transferred == ~std::size_t(0))
-          bytes_transferred = 0; // Timer cancellation, no data transferred.
-        else if (!ec_)
-          ec_ = ec;
-
-        switch (want_)
-        {
-        case engine::want_input_and_retry:
-
-          // Add received data to the engine's input.
-          core_.input_ = asio::buffer(
-              core_.input_buffer_, bytes_transferred);
-          core_.input_ = core_.engine_.put_input(core_.input_);
-
-          // Release any waiting read operations.
-          core_.pending_read_.expires_at(core_.neg_infin());
-
-          // Try the operation again.
-          continue;
-
-        case engine::want_output_and_retry:
-
-          // Release any waiting write operations.
-          core_.pending_write_.expires_at(core_.neg_infin());
-
-          // Try the operation again.
-          continue;
-
-        case engine::want_output:
-
-          // Release any waiting write operations.
-          core_.pending_write_.expires_at(core_.neg_infin());
-
-          // Fall through to call handler.
-
-        default:
-
-          // Pass the result to the handler.
-          op_.call_handler(handler_,
-              core_.engine_.map_error_code(ec_),
-              ec_ ? 0 : bytes_transferred_);
-
-          // Our work here is done.
-          return;
-        }
-      } while (!ec_);
-
-      // Operation failed. Pass the result to the handler.
-      op_.call_handler(handler_, core_.engine_.map_error_code(ec_), 0);
-    }
-  }
-
-//private:
-  Stream& next_layer_;
-  stream_core& core_;
-  Operation op_;
-  int start_;
-  engine::want want_;
-  asio::error_code ec_;
-  std::size_t bytes_transferred_;
-  Handler handler_;
-};
-
-template <typename Stream, typename Operation, typename Handler>
-inline void* asio_handler_allocate(std::size_t size,
-    io_op<Stream, Operation, Handler>* this_handler)
-{
-  return asio_handler_alloc_helpers::allocate(
-      size, this_handler->handler_);
-}
-
-template <typename Stream, typename Operation, typename Handler>
-inline void asio_handler_deallocate(void* pointer, std::size_t size,
-    io_op<Stream, Operation, Handler>* this_handler)
-{
-  asio_handler_alloc_helpers::deallocate(
-      pointer, size, this_handler->handler_);
-}
-
-template <typename Stream, typename Operation, typename Handler>
-inline bool asio_handler_is_continuation(
-    io_op<Stream, Operation, Handler>* this_handler)
-{
-  return this_handler->start_ == 0 ? true
-    : asio_handler_cont_helpers::is_continuation(this_handler->handler_);
-}
-
-template <typename Function, typename Stream,
-    typename Operation, typename Handler>
-inline void asio_handler_invoke(Function& function,
-    io_op<Stream, Operation, Handler>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Function, typename Stream,
-    typename Operation, typename Handler>
-inline void asio_handler_invoke(const Function& function,
-    io_op<Stream, Operation, Handler>* this_handler)
-{
-  asio_handler_invoke_helpers::invoke(
-      function, this_handler->handler_);
-}
-
-template <typename Stream, typename Operation, typename Handler>
-inline void async_io(Stream& next_layer, stream_core& core,
-    const Operation& op, Handler& handler)
-{
-  io_op<Stream, Operation, Handler>(
-    next_layer, core, op, handler)(
-      asio::error_code(), 0, 1);
-}
-
-} // namespace detail
-} // namespace ssl
-
-template <typename Stream, typename Operation,
-    typename Handler, typename Allocator>
-struct associated_allocator<
-    ssl::detail::io_op<Stream, Operation, Handler>, Allocator>
-{
-  typedef typename associated_allocator<Handler, Allocator>::type type;
-
-  static type get(const ssl::detail::io_op<Stream, Operation, Handler>& h,
-      const Allocator& a = Allocator()) ASIO_NOEXCEPT
-  {
-    return associated_allocator<Handler, Allocator>::get(h.handler_, a);
-  }
-};
-
-template <typename Stream, typename Operation,
-    typename Handler, typename Executor>
-struct associated_executor<
-    ssl::detail::io_op<Stream, Operation, Handler>, Executor>
-{
-  typedef typename associated_executor<Handler, Executor>::type type;
-
-  static type get(const ssl::detail::io_op<Stream, Operation, Handler>& h,
-      const Executor& ex = Executor()) ASIO_NOEXCEPT
-  {
-    return associated_executor<Handler, Executor>::get(h.handler_, ex);
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_DETAIL_IO_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/openssl_init.hpp b/tools/sdk/include/asio/asio/ssl/detail/openssl_init.hpp
deleted file mode 100644
index c3e47278fe7..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/openssl_init.hpp
+++ /dev/null
@@ -1,101 +0,0 @@
-//
-// ssl/detail/openssl_init.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_OPENSSL_INIT_HPP
-#define ASIO_SSL_DETAIL_OPENSSL_INIT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstring>
-#include "asio/detail/memory.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/ssl/detail/openssl_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-class openssl_init_base
-  : private noncopyable
-{
-protected:
-  // Class that performs the actual initialisation.
-  class do_init;
-
-  // Helper function to manage a do_init singleton. The static instance of the
-  // openssl_init object ensures that this function is always called before
-  // main, and therefore before any other threads can get started. The do_init
-  // instance must be static in this function to ensure that it gets
-  // initialised before any other global objects try to use it.
-  ASIO_DECL static asio::detail::shared_ptr<do_init> instance();
-
-#if !defined(SSL_OP_NO_COMPRESSION) \
-  && (OPENSSL_VERSION_NUMBER >= 0x00908000L)
-  // Get an empty stack of compression methods, to be used when disabling
-  // compression.
-  ASIO_DECL static STACK_OF(SSL_COMP)* get_null_compression_methods();
-#endif // !defined(SSL_OP_NO_COMPRESSION)
-       // && (OPENSSL_VERSION_NUMBER >= 0x00908000L)
-};
-
-template <bool Do_Init = true>
-class openssl_init : private openssl_init_base
-{
-public:
-  // Constructor.
-  openssl_init()
-    : ref_(instance())
-  {
-    using namespace std; // For memmove.
-
-    // Ensure openssl_init::instance_ is linked in.
-    openssl_init* tmp = &instance_;
-    memmove(&tmp, &tmp, sizeof(openssl_init*));
-  }
-
-  // Destructor.
-  ~openssl_init()
-  {
-  }
-
-#if !defined(SSL_OP_NO_COMPRESSION) \
-  && (OPENSSL_VERSION_NUMBER >= 0x00908000L)
-  using openssl_init_base::get_null_compression_methods;
-#endif // !defined(SSL_OP_NO_COMPRESSION)
-       // && (OPENSSL_VERSION_NUMBER >= 0x00908000L)
-
-private:
-  // Instance to force initialisation of openssl at global scope.
-  static openssl_init instance_;
-
-  // Reference to singleton do_init object to ensure that openssl does not get
-  // cleaned up until the last user has finished with it.
-  asio::detail::shared_ptr<do_init> ref_;
-};
-
-template <bool Do_Init>
-openssl_init<Do_Init> openssl_init<Do_Init>::instance_;
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ssl/detail/impl/openssl_init.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_SSL_DETAIL_OPENSSL_INIT_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/openssl_types.hpp b/tools/sdk/include/asio/asio/ssl/detail/openssl_types.hpp
deleted file mode 100644
index a044af30d40..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/openssl_types.hpp
+++ /dev/null
@@ -1,30 +0,0 @@
-//
-// ssl/detail/openssl_types.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_OPENSSL_TYPES_HPP
-#define ASIO_SSL_DETAIL_OPENSSL_TYPES_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/socket_types.hpp"
-#include <openssl/conf.h>
-#include <openssl/ssl.h>
-#if !defined(OPENSSL_NO_ENGINE)
-# include <openssl/engine.h>
-#endif // !defined(OPENSSL_NO_ENGINE)
-#include <openssl/dh.h>
-#include <openssl/err.h>
-#include <openssl/rsa.h>
-#include <openssl/x509v3.h>
-
-#endif // ASIO_SSL_DETAIL_OPENSSL_TYPES_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/password_callback.hpp b/tools/sdk/include/asio/asio/ssl/detail/password_callback.hpp
deleted file mode 100644
index 9b1dbeeb884..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/password_callback.hpp
+++ /dev/null
@@ -1,66 +0,0 @@
-//
-// ssl/detail/password_callback.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_PASSWORD_CALLBACK_HPP
-#define ASIO_SSL_DETAIL_PASSWORD_CALLBACK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <cstddef>
-#include <string>
-#include "asio/ssl/context_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-class password_callback_base
-{
-public:
-  virtual ~password_callback_base()
-  {
-  }
-
-  virtual std::string call(std::size_t size,
-      context_base::password_purpose purpose) = 0;
-};
-
-template <typename PasswordCallback>
-class password_callback : public password_callback_base
-{
-public:
-  explicit password_callback(PasswordCallback callback)
-    : callback_(callback)
-  {
-  }
-
-  virtual std::string call(std::size_t size,
-      context_base::password_purpose purpose)
-  {
-    return callback_(size, purpose);
-  }
-
-private:
-  PasswordCallback callback_;
-};
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_DETAIL_PASSWORD_CALLBACK_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/read_op.hpp b/tools/sdk/include/asio/asio/ssl/detail/read_op.hpp
deleted file mode 100644
index b0d6de26657..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/read_op.hpp
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// ssl/detail/read_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_READ_OP_HPP
-#define ASIO_SSL_DETAIL_READ_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/ssl/detail/engine.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-template <typename MutableBufferSequence>
-class read_op
-{
-public:
-  read_op(const MutableBufferSequence& buffers)
-    : buffers_(buffers)
-  {
-  }
-
-  engine::want operator()(engine& eng,
-      asio::error_code& ec,
-      std::size_t& bytes_transferred) const
-  {
-    asio::mutable_buffer buffer =
-      asio::detail::buffer_sequence_adapter<asio::mutable_buffer,
-        MutableBufferSequence>::first(buffers_);
-
-    return eng.read(buffer, ec, bytes_transferred);
-  }
-
-  template <typename Handler>
-  void call_handler(Handler& handler,
-      const asio::error_code& ec,
-      const std::size_t& bytes_transferred) const
-  {
-    handler(ec, bytes_transferred);
-  }
-
-private:
-  MutableBufferSequence buffers_;
-};
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_DETAIL_READ_OP_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/shutdown_op.hpp b/tools/sdk/include/asio/asio/ssl/detail/shutdown_op.hpp
deleted file mode 100644
index d20b4309ea0..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/shutdown_op.hpp
+++ /dev/null
@@ -1,54 +0,0 @@
-//
-// ssl/detail/shutdown_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_SHUTDOWN_OP_HPP
-#define ASIO_SSL_DETAIL_SHUTDOWN_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/ssl/detail/engine.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-class shutdown_op
-{
-public:
-  engine::want operator()(engine& eng,
-      asio::error_code& ec,
-      std::size_t& bytes_transferred) const
-  {
-    bytes_transferred = 0;
-    return eng.shutdown(ec);
-  }
-
-  template <typename Handler>
-  void call_handler(Handler& handler,
-      const asio::error_code& ec,
-      const std::size_t&) const
-  {
-    handler(ec);
-  }
-};
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_DETAIL_SHUTDOWN_OP_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/stream_core.hpp b/tools/sdk/include/asio/asio/ssl/detail/stream_core.hpp
deleted file mode 100644
index 13fde74bf98..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/stream_core.hpp
+++ /dev/null
@@ -1,134 +0,0 @@
-//
-// ssl/detail/stream_core.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_STREAM_CORE_HPP
-#define ASIO_SSL_DETAIL_STREAM_CORE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME)
-# include "asio/deadline_timer.hpp"
-#else // defined(ASIO_HAS_BOOST_DATE_TIME)
-# include "asio/steady_timer.hpp"
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-#include "asio/ssl/detail/engine.hpp"
-#include "asio/buffer.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-struct stream_core
-{
-  // According to the OpenSSL documentation, this is the buffer size that is
-  // sufficient to hold the largest possible TLS record.
-  enum { max_tls_record_size = 17 * 1024 };
-
-  stream_core(SSL_CTX* context, asio::io_context& io_context)
-    : engine_(context),
-      pending_read_(io_context),
-      pending_write_(io_context),
-      output_buffer_space_(max_tls_record_size),
-      output_buffer_(asio::buffer(output_buffer_space_)),
-      input_buffer_space_(max_tls_record_size),
-      input_buffer_(asio::buffer(input_buffer_space_))
-  {
-    pending_read_.expires_at(neg_infin());
-    pending_write_.expires_at(neg_infin());
-  }
-
-  ~stream_core()
-  {
-  }
-
-  // The SSL engine.
-  engine engine_;
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME)
-  // Timer used for storing queued read operations.
-  asio::deadline_timer pending_read_;
-
-  // Timer used for storing queued write operations.
-  asio::deadline_timer pending_write_;
-
-  // Helper function for obtaining a time value that always fires.
-  static asio::deadline_timer::time_type neg_infin()
-  {
-    return boost::posix_time::neg_infin;
-  }
-
-  // Helper function for obtaining a time value that never fires.
-  static asio::deadline_timer::time_type pos_infin()
-  {
-    return boost::posix_time::pos_infin;
-  }
-
-  // Helper function to get a timer's expiry time.
-  static asio::deadline_timer::time_type expiry(
-      const asio::deadline_timer& timer)
-  {
-    return timer.expires_at();
-  }
-#else // defined(ASIO_HAS_BOOST_DATE_TIME)
-  // Timer used for storing queued read operations.
-  asio::steady_timer pending_read_;
-
-  // Timer used for storing queued write operations.
-  asio::steady_timer pending_write_;
-
-  // Helper function for obtaining a time value that always fires.
-  static asio::steady_timer::time_point neg_infin()
-  {
-    return (asio::steady_timer::time_point::min)();
-  }
-
-  // Helper function for obtaining a time value that never fires.
-  static asio::steady_timer::time_point pos_infin()
-  {
-    return (asio::steady_timer::time_point::max)();
-  }
-
-  // Helper function to get a timer's expiry time.
-  static asio::steady_timer::time_point expiry(
-      const asio::steady_timer& timer)
-  {
-    return timer.expiry();
-  }
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-
-  // Buffer space used to prepare output intended for the transport.
-  std::vector<unsigned char> output_buffer_space_;
-
-  // A buffer that may be used to prepare output intended for the transport.
-  const asio::mutable_buffer output_buffer_;
-
-  // Buffer space used to read input intended for the engine.
-  std::vector<unsigned char> input_buffer_space_;
-
-  // A buffer that may be used to read input intended for the engine.
-  const asio::mutable_buffer input_buffer_;
-
-  // The buffer pointing to the engine's unconsumed input.
-  asio::const_buffer input_;
-};
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_DETAIL_STREAM_CORE_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/verify_callback.hpp b/tools/sdk/include/asio/asio/ssl/detail/verify_callback.hpp
deleted file mode 100644
index 1c56a27d824..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/verify_callback.hpp
+++ /dev/null
@@ -1,62 +0,0 @@
-//
-// ssl/detail/verify_callback.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_VERIFY_CALLBACK_HPP
-#define ASIO_SSL_DETAIL_VERIFY_CALLBACK_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/ssl/verify_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-class verify_callback_base
-{
-public:
-  virtual ~verify_callback_base()
-  {
-  }
-
-  virtual bool call(bool preverified, verify_context& ctx) = 0;
-};
-
-template <typename VerifyCallback>
-class verify_callback : public verify_callback_base
-{
-public:
-  explicit verify_callback(VerifyCallback callback)
-    : callback_(callback)
-  {
-  }
-
-  virtual bool call(bool preverified, verify_context& ctx)
-  {
-    return callback_(preverified, ctx);
-  }
-
-private:
-  VerifyCallback callback_;
-};
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_DETAIL_VERIFY_CALLBACK_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/detail/write_op.hpp b/tools/sdk/include/asio/asio/ssl/detail/write_op.hpp
deleted file mode 100644
index 1d341c09d21..00000000000
--- a/tools/sdk/include/asio/asio/ssl/detail/write_op.hpp
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// ssl/detail/write_op.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_DETAIL_WRITE_OP_HPP
-#define ASIO_SSL_DETAIL_WRITE_OP_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/ssl/detail/engine.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-namespace detail {
-
-template <typename ConstBufferSequence>
-class write_op
-{
-public:
-  write_op(const ConstBufferSequence& buffers)
-    : buffers_(buffers)
-  {
-  }
-
-  engine::want operator()(engine& eng,
-      asio::error_code& ec,
-      std::size_t& bytes_transferred) const
-  {
-    asio::const_buffer buffer =
-      asio::detail::buffer_sequence_adapter<asio::const_buffer,
-        ConstBufferSequence>::first(buffers_);
-
-    return eng.write(buffer, ec, bytes_transferred);
-  }
-
-  template <typename Handler>
-  void call_handler(Handler& handler,
-      const asio::error_code& ec,
-      const std::size_t& bytes_transferred) const
-  {
-    handler(ec, bytes_transferred);
-  }
-
-private:
-  ConstBufferSequence buffers_;
-};
-
-} // namespace detail
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_DETAIL_WRITE_OP_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/error.hpp b/tools/sdk/include/asio/asio/ssl/error.hpp
deleted file mode 100644
index 6165c5cf764..00000000000
--- a/tools/sdk/include/asio/asio/ssl/error.hpp
+++ /dev/null
@@ -1,111 +0,0 @@
-//
-// ssl/error.hpp
-// ~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_ERROR_HPP
-#define ASIO_SSL_ERROR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/error_code.hpp"
-#include "asio/ssl/detail/openssl_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace error {
-
-enum ssl_errors
-{
-  // Error numbers are those produced by openssl.
-};
-
-extern ASIO_DECL
-const asio::error_category& get_ssl_category();
-
-static const asio::error_category&
-  ssl_category ASIO_UNUSED_VARIABLE
-  = asio::error::get_ssl_category();
-
-} // namespace error
-namespace ssl {
-namespace error {
-
-enum stream_errors
-{
-#if defined(GENERATING_DOCUMENTATION)
-  /// The underlying stream closed before the ssl stream gracefully shut down.
-  stream_truncated
-#elif (OPENSSL_VERSION_NUMBER < 0x10100000L) && !defined(OPENSSL_IS_BORINGSSL)
-  stream_truncated = ERR_PACK(ERR_LIB_SSL, 0, SSL_R_SHORT_READ)
-#else
-  stream_truncated = 1
-#endif
-};
-
-extern ASIO_DECL
-const asio::error_category& get_stream_category();
-
-static const asio::error_category&
-  stream_category ASIO_UNUSED_VARIABLE
-  = asio::ssl::error::get_stream_category();
-
-} // namespace error
-} // namespace ssl
-} // namespace asio
-
-#if defined(ASIO_HAS_STD_SYSTEM_ERROR)
-namespace std {
-
-template<> struct is_error_code_enum<asio::error::ssl_errors>
-{
-  static const bool value = true;
-};
-
-template<> struct is_error_code_enum<asio::ssl::error::stream_errors>
-{
-  static const bool value = true;
-};
-
-} // namespace std
-#endif // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-namespace asio {
-namespace error {
-
-inline asio::error_code make_error_code(ssl_errors e)
-{
-  return asio::error_code(
-      static_cast<int>(e), get_ssl_category());
-}
-
-} // namespace error
-namespace ssl {
-namespace error {
-
-inline asio::error_code make_error_code(stream_errors e)
-{
-  return asio::error_code(
-      static_cast<int>(e), get_stream_category());
-}
-
-} // namespace error
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ssl/impl/error.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_SSL_ERROR_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/impl/context.hpp b/tools/sdk/include/asio/asio/ssl/impl/context.hpp
deleted file mode 100644
index 40199c143cf..00000000000
--- a/tools/sdk/include/asio/asio/ssl/impl/context.hpp
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// ssl/impl/context.hpp
-// ~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2005 Voipster / Indrek dot Juhani at voipster dot com
-// Copyright (c) 2005-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_IMPL_CONTEXT_HPP
-#define ASIO_SSL_IMPL_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/throw_error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-
-template <typename VerifyCallback>
-void context::set_verify_callback(VerifyCallback callback)
-{
-  asio::error_code ec;
-  this->set_verify_callback(callback, ec);
-  asio::detail::throw_error(ec, "set_verify_callback");
-}
-
-template <typename VerifyCallback>
-ASIO_SYNC_OP_VOID context::set_verify_callback(
-    VerifyCallback callback, asio::error_code& ec)
-{
-  do_set_verify_callback(
-      new detail::verify_callback<VerifyCallback>(callback), ec);
-  ASIO_SYNC_OP_VOID_RETURN(ec);
-}
-
-template <typename PasswordCallback>
-void context::set_password_callback(PasswordCallback callback)
-{
-  asio::error_code ec;
-  this->set_password_callback(callback, ec);
-  asio::detail::throw_error(ec, "set_password_callback");
-}
-
-template <typename PasswordCallback>
-ASIO_SYNC_OP_VOID context::set_password_callback(
-    PasswordCallback callback, asio::error_code& ec)
-{
-  do_set_password_callback(
-      new detail::password_callback<PasswordCallback>(callback), ec);
-  ASIO_SYNC_OP_VOID_RETURN(ec);
-}
-
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_IMPL_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/impl/src.hpp b/tools/sdk/include/asio/asio/ssl/impl/src.hpp
deleted file mode 100644
index 9a1b038a4c3..00000000000
--- a/tools/sdk/include/asio/asio/ssl/impl/src.hpp
+++ /dev/null
@@ -1,28 +0,0 @@
-//
-// impl/ssl/src.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_IMPL_SRC_HPP
-#define ASIO_SSL_IMPL_SRC_HPP
-
-#define ASIO_SOURCE
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# error Do not compile Asio library source with ASIO_HEADER_ONLY defined
-#endif
-
-#include "asio/ssl/impl/context.ipp"
-#include "asio/ssl/impl/error.ipp"
-#include "asio/ssl/detail/impl/engine.ipp"
-#include "asio/ssl/detail/impl/openssl_init.ipp"
-#include "asio/ssl/impl/rfc2818_verification.ipp"
-
-#endif // ASIO_SSL_IMPL_SRC_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/rfc2818_verification.hpp b/tools/sdk/include/asio/asio/ssl/rfc2818_verification.hpp
deleted file mode 100644
index 3589f5383eb..00000000000
--- a/tools/sdk/include/asio/asio/ssl/rfc2818_verification.hpp
+++ /dev/null
@@ -1,94 +0,0 @@
-//
-// ssl/rfc2818_verification.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_RFC2818_VERIFICATION_HPP
-#define ASIO_SSL_RFC2818_VERIFICATION_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include <string>
-#include "asio/ssl/detail/openssl_types.hpp"
-#include "asio/ssl/verify_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-
-/// Verifies a certificate against a hostname according to the rules described
-/// in RFC 2818.
-/**
- * @par Example
- * The following example shows how to synchronously open a secure connection to
- * a given host name:
- * @code
- * using asio::ip::tcp;
- * namespace ssl = asio::ssl;
- * typedef ssl::stream<tcp::socket> ssl_socket;
- *
- * // Create a context that uses the default paths for finding CA certificates.
- * ssl::context ctx(ssl::context::sslv23);
- * ctx.set_default_verify_paths();
- *
- * // Open a socket and connect it to the remote host.
- * asio::io_context io_context;
- * ssl_socket sock(io_context, ctx);
- * tcp::resolver resolver(io_context);
- * tcp::resolver::query query("host.name", "https");
- * asio::connect(sock.lowest_layer(), resolver.resolve(query));
- * sock.lowest_layer().set_option(tcp::no_delay(true));
- *
- * // Perform SSL handshake and verify the remote host's certificate.
- * sock.set_verify_mode(ssl::verify_peer);
- * sock.set_verify_callback(ssl::rfc2818_verification("host.name"));
- * sock.handshake(ssl_socket::client);
- *
- * // ... read and write as normal ...
- * @endcode
- */
-class rfc2818_verification
-{
-public:
-  /// The type of the function object's result.
-  typedef bool result_type;
-
-  /// Constructor.
-  explicit rfc2818_verification(const std::string& host)
-    : host_(host)
-  {
-  }
-
-  /// Perform certificate verification.
-  ASIO_DECL bool operator()(bool preverified, verify_context& ctx) const;
-
-private:
-  // Helper function to check a host name against a pattern.
-  ASIO_DECL static bool match_pattern(const char* pattern,
-      std::size_t pattern_length, const char* host);
-
-  // Helper function to check a host name against an IPv4 address
-  // The host name to be checked.
-  std::string host_;
-};
-
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/ssl/impl/rfc2818_verification.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_SSL_RFC2818_VERIFICATION_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/stream.hpp b/tools/sdk/include/asio/asio/ssl/stream.hpp
deleted file mode 100644
index 2b221ed514f..00000000000
--- a/tools/sdk/include/asio/asio/ssl/stream.hpp
+++ /dev/null
@@ -1,761 +0,0 @@
-//
-// ssl/stream.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_STREAM_HPP
-#define ASIO_SSL_STREAM_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/async_result.hpp"
-#include "asio/detail/buffer_sequence_adapter.hpp"
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/ssl/context.hpp"
-#include "asio/ssl/detail/buffered_handshake_op.hpp"
-#include "asio/ssl/detail/handshake_op.hpp"
-#include "asio/ssl/detail/io.hpp"
-#include "asio/ssl/detail/read_op.hpp"
-#include "asio/ssl/detail/shutdown_op.hpp"
-#include "asio/ssl/detail/stream_core.hpp"
-#include "asio/ssl/detail/write_op.hpp"
-#include "asio/ssl/stream_base.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-
-/// Provides stream-oriented functionality using SSL.
-/**
- * The stream class template provides asynchronous and blocking stream-oriented
- * functionality using SSL.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe. The application must also ensure that all
- * asynchronous operations are performed within the same implicit or explicit
- * strand.
- *
- * @par Example
- * To use the SSL stream template with an ip::tcp::socket, you would write:
- * @code
- * asio::io_context io_context;
- * asio::ssl::context ctx(asio::ssl::context::sslv23);
- * asio::ssl::stream<asio:ip::tcp::socket> sock(io_context, ctx);
- * @endcode
- *
- * @par Concepts:
- * AsyncReadStream, AsyncWriteStream, Stream, SyncReadStream, SyncWriteStream.
- */
-template <typename Stream>
-class stream :
-  public stream_base,
-  private noncopyable
-{
-public:
-  /// The native handle type of the SSL stream.
-  typedef SSL* native_handle_type;
-
-  /// Structure for use with deprecated impl_type.
-  struct impl_struct
-  {
-    SSL* ssl;
-  };
-
-  /// The type of the next layer.
-  typedef typename remove_reference<Stream>::type next_layer_type;
-
-  /// The type of the lowest layer.
-  typedef typename next_layer_type::lowest_layer_type lowest_layer_type;
-
-  /// The type of the executor associated with the object.
-  typedef typename lowest_layer_type::executor_type executor_type;
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Construct a stream.
-  /**
-   * This constructor creates a stream and initialises the underlying stream
-   * object.
-   *
-   * @param arg The argument to be passed to initialise the underlying stream.
-   *
-   * @param ctx The SSL context to be used for the stream.
-   */
-  template <typename Arg>
-  stream(Arg&& arg, context& ctx)
-    : next_layer_(ASIO_MOVE_CAST(Arg)(arg)),
-      core_(ctx.native_handle(),
-          next_layer_.lowest_layer().get_executor().context())
-  {
-  }
-#else // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  template <typename Arg>
-  stream(Arg& arg, context& ctx)
-    : next_layer_(arg),
-      core_(ctx.native_handle(),
-          next_layer_.lowest_layer().get_executor().context())
-  {
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destructor.
-  /**
-   * @note A @c stream object must not be destroyed while there are pending
-   * asynchronous operations associated with it.
-   */
-  ~stream()
-  {
-  }
-
-  /// Get the executor associated with the object.
-  /**
-   * This function may be used to obtain the executor object that the stream
-   * uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A copy of the executor that stream will use to dispatch handlers.
-   */
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return next_layer_.lowest_layer().get_executor();
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  asio::io_context& get_io_context()
-  {
-    return next_layer_.lowest_layer().get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  asio::io_context& get_io_service()
-  {
-    return next_layer_.lowest_layer().get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the underlying implementation in the native type.
-  /**
-   * This function may be used to obtain the underlying implementation of the
-   * context. This is intended to allow access to context functionality that is
-   * not otherwise provided.
-   *
-   * @par Example
-   * The native_handle() function returns a pointer of type @c SSL* that is
-   * suitable for passing to functions such as @c SSL_get_verify_result and
-   * @c SSL_get_peer_certificate:
-   * @code
-   * asio::ssl::stream<asio:ip::tcp::socket> sock(io_context, ctx);
-   *
-   * // ... establish connection and perform handshake ...
-   *
-   * if (X509* cert = SSL_get_peer_certificate(sock.native_handle()))
-   * {
-   *   if (SSL_get_verify_result(sock.native_handle()) == X509_V_OK)
-   *   {
-   *     // ...
-   *   }
-   * }
-   * @endcode
-   */
-  native_handle_type native_handle()
-  {
-    return core_.engine_.native_handle();
-  }
-
-  /// Get a reference to the next layer.
-  /**
-   * This function returns a reference to the next layer in a stack of stream
-   * layers.
-   *
-   * @return A reference to the next layer in the stack of stream layers.
-   * Ownership is not transferred to the caller.
-   */
-  const next_layer_type& next_layer() const
-  {
-    return next_layer_;
-  }
-
-  /// Get a reference to the next layer.
-  /**
-   * This function returns a reference to the next layer in a stack of stream
-   * layers.
-   *
-   * @return A reference to the next layer in the stack of stream layers.
-   * Ownership is not transferred to the caller.
-   */
-  next_layer_type& next_layer()
-  {
-    return next_layer_;
-  }
-
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * stream layers.
-   *
-   * @return A reference to the lowest layer in the stack of stream layers.
-   * Ownership is not transferred to the caller.
-   */
-  lowest_layer_type& lowest_layer()
-  {
-    return next_layer_.lowest_layer();
-  }
-
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * stream layers.
-   *
-   * @return A reference to the lowest layer in the stack of stream layers.
-   * Ownership is not transferred to the caller.
-   */
-  const lowest_layer_type& lowest_layer() const
-  {
-    return next_layer_.lowest_layer();
-  }
-
-  /// Set the peer verification mode.
-  /**
-   * This function may be used to configure the peer verification mode used by
-   * the stream. The new mode will override the mode inherited from the context.
-   *
-   * @param v A bitmask of peer verification modes. See @ref verify_mode for
-   * available values.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_set_verify.
-   */
-  void set_verify_mode(verify_mode v)
-  {
-    asio::error_code ec;
-    set_verify_mode(v, ec);
-    asio::detail::throw_error(ec, "set_verify_mode");
-  }
-
-  /// Set the peer verification mode.
-  /**
-   * This function may be used to configure the peer verification mode used by
-   * the stream. The new mode will override the mode inherited from the context.
-   *
-   * @param v A bitmask of peer verification modes. See @ref verify_mode for
-   * available values.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_set_verify.
-   */
-  ASIO_SYNC_OP_VOID set_verify_mode(
-      verify_mode v, asio::error_code& ec)
-  {
-    core_.engine_.set_verify_mode(v, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Set the peer verification depth.
-  /**
-   * This function may be used to configure the maximum verification depth
-   * allowed by the stream.
-   *
-   * @param depth Maximum depth for the certificate chain verification that
-   * shall be allowed.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_set_verify_depth.
-   */
-  void set_verify_depth(int depth)
-  {
-    asio::error_code ec;
-    set_verify_depth(depth, ec);
-    asio::detail::throw_error(ec, "set_verify_depth");
-  }
-
-  /// Set the peer verification depth.
-  /**
-   * This function may be used to configure the maximum verification depth
-   * allowed by the stream.
-   *
-   * @param depth Maximum depth for the certificate chain verification that
-   * shall be allowed.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_set_verify_depth.
-   */
-  ASIO_SYNC_OP_VOID set_verify_depth(
-      int depth, asio::error_code& ec)
-  {
-    core_.engine_.set_verify_depth(depth, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Set the callback used to verify peer certificates.
-  /**
-   * This function is used to specify a callback function that will be called
-   * by the implementation when it needs to verify a peer certificate.
-   *
-   * @param callback The function object to be used for verifying a certificate.
-   * The function signature of the handler must be:
-   * @code bool verify_callback(
-   *   bool preverified, // True if the certificate passed pre-verification.
-   *   verify_context& ctx // The peer certificate and other context.
-   * ); @endcode
-   * The return value of the callback is true if the certificate has passed
-   * verification, false otherwise.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note Calls @c SSL_set_verify.
-   */
-  template <typename VerifyCallback>
-  void set_verify_callback(VerifyCallback callback)
-  {
-    asio::error_code ec;
-    this->set_verify_callback(callback, ec);
-    asio::detail::throw_error(ec, "set_verify_callback");
-  }
-
-  /// Set the callback used to verify peer certificates.
-  /**
-   * This function is used to specify a callback function that will be called
-   * by the implementation when it needs to verify a peer certificate.
-   *
-   * @param callback The function object to be used for verifying a certificate.
-   * The function signature of the handler must be:
-   * @code bool verify_callback(
-   *   bool preverified, // True if the certificate passed pre-verification.
-   *   verify_context& ctx // The peer certificate and other context.
-   * ); @endcode
-   * The return value of the callback is true if the certificate has passed
-   * verification, false otherwise.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @note Calls @c SSL_set_verify.
-   */
-  template <typename VerifyCallback>
-  ASIO_SYNC_OP_VOID set_verify_callback(VerifyCallback callback,
-      asio::error_code& ec)
-  {
-    core_.engine_.set_verify_callback(
-        new detail::verify_callback<VerifyCallback>(callback), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform SSL handshaking.
-  /**
-   * This function is used to perform SSL handshaking on the stream. The
-   * function call will block until handshaking is complete or an error occurs.
-   *
-   * @param type The type of handshaking to be performed, i.e. as a client or as
-   * a server.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void handshake(handshake_type type)
-  {
-    asio::error_code ec;
-    handshake(type, ec);
-    asio::detail::throw_error(ec, "handshake");
-  }
-
-  /// Perform SSL handshaking.
-  /**
-   * This function is used to perform SSL handshaking on the stream. The
-   * function call will block until handshaking is complete or an error occurs.
-   *
-   * @param type The type of handshaking to be performed, i.e. as a client or as
-   * a server.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID handshake(handshake_type type,
-      asio::error_code& ec)
-  {
-    detail::io(next_layer_, core_, detail::handshake_op(type), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform SSL handshaking.
-  /**
-   * This function is used to perform SSL handshaking on the stream. The
-   * function call will block until handshaking is complete or an error occurs.
-   *
-   * @param type The type of handshaking to be performed, i.e. as a client or as
-   * a server.
-   *
-   * @param buffers The buffered data to be reused for the handshake.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  template <typename ConstBufferSequence>
-  void handshake(handshake_type type, const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    handshake(type, buffers, ec);
-    asio::detail::throw_error(ec, "handshake");
-  }
-
-  /// Perform SSL handshaking.
-  /**
-   * This function is used to perform SSL handshaking on the stream. The
-   * function call will block until handshaking is complete or an error occurs.
-   *
-   * @param type The type of handshaking to be performed, i.e. as a client or as
-   * a server.
-   *
-   * @param buffers The buffered data to be reused for the handshake.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  template <typename ConstBufferSequence>
-  ASIO_SYNC_OP_VOID handshake(handshake_type type,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    detail::io(next_layer_, core_,
-        detail::buffered_handshake_op<ConstBufferSequence>(type, buffers), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous SSL handshake.
-  /**
-   * This function is used to asynchronously perform an SSL handshake on the
-   * stream. This function call always returns immediately.
-   *
-   * @param type The type of handshaking to be performed, i.e. as a client or as
-   * a server.
-   *
-   * @param handler The handler to be called when the handshake operation
-   * completes. Copies will be made of the handler as required. The equivalent
-   * function signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation.
-   * ); @endcode
-   */
-  template <typename HandshakeHandler>
-  ASIO_INITFN_RESULT_TYPE(HandshakeHandler,
-      void (asio::error_code))
-  async_handshake(handshake_type type,
-      ASIO_MOVE_ARG(HandshakeHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a HandshakeHandler.
-    ASIO_HANDSHAKE_HANDLER_CHECK(HandshakeHandler, handler) type_check;
-
-    asio::async_completion<HandshakeHandler,
-      void (asio::error_code)> init(handler);
-
-    detail::async_io(next_layer_, core_,
-        detail::handshake_op(type), init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Start an asynchronous SSL handshake.
-  /**
-   * This function is used to asynchronously perform an SSL handshake on the
-   * stream. This function call always returns immediately.
-   *
-   * @param type The type of handshaking to be performed, i.e. as a client or as
-   * a server.
-   *
-   * @param buffers The buffered data to be reused for the handshake. Although
-   * the buffers object may be copied as necessary, ownership of the underlying
-   * buffers is retained by the caller, which must guarantee that they remain
-   * valid until the handler is called.
-   *
-   * @param handler The handler to be called when the handshake operation
-   * completes. Copies will be made of the handler as required. The equivalent
-   * function signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred // Amount of buffers used in handshake.
-   * ); @endcode
-   */
-  template <typename ConstBufferSequence, typename BufferedHandshakeHandler>
-  ASIO_INITFN_RESULT_TYPE(BufferedHandshakeHandler,
-      void (asio::error_code, std::size_t))
-  async_handshake(handshake_type type, const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(BufferedHandshakeHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a BufferedHandshakeHandler.
-    ASIO_BUFFERED_HANDSHAKE_HANDLER_CHECK(
-        BufferedHandshakeHandler, handler) type_check;
-
-    asio::async_completion<BufferedHandshakeHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    detail::async_io(next_layer_, core_,
-        detail::buffered_handshake_op<ConstBufferSequence>(type, buffers),
-        init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Shut down SSL on the stream.
-  /**
-   * This function is used to shut down SSL on the stream. The function call
-   * will block until SSL has been shut down or an error occurs.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void shutdown()
-  {
-    asio::error_code ec;
-    shutdown(ec);
-    asio::detail::throw_error(ec, "shutdown");
-  }
-
-  /// Shut down SSL on the stream.
-  /**
-   * This function is used to shut down SSL on the stream. The function call
-   * will block until SSL has been shut down or an error occurs.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID shutdown(asio::error_code& ec)
-  {
-    detail::io(next_layer_, core_, detail::shutdown_op(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously shut down SSL on the stream.
-  /**
-   * This function is used to asynchronously shut down SSL on the stream. This
-   * function call always returns immediately.
-   *
-   * @param handler The handler to be called when the handshake operation
-   * completes. Copies will be made of the handler as required. The equivalent
-   * function signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation.
-   * ); @endcode
-   */
-  template <typename ShutdownHandler>
-  ASIO_INITFN_RESULT_TYPE(ShutdownHandler,
-      void (asio::error_code))
-  async_shutdown(ASIO_MOVE_ARG(ShutdownHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ShutdownHandler.
-    ASIO_SHUTDOWN_HANDLER_CHECK(ShutdownHandler, handler) type_check;
-
-    asio::async_completion<ShutdownHandler,
-      void (asio::error_code)> init(handler);
-
-    detail::async_io(next_layer_, core_, detail::shutdown_op(),
-        init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Write some data to the stream.
-  /**
-   * This function is used to write data on the stream. The function call will
-   * block until one or more bytes of data has been written successfully, or
-   * until an error occurs.
-   *
-   * @param buffers The data to be written.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that all
-   * data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t n = write_some(buffers, ec);
-    asio::detail::throw_error(ec, "write_some");
-    return n;
-  }
-
-  /// Write some data to the stream.
-  /**
-   * This function is used to write data on the stream. The function call will
-   * block until one or more bytes of data has been written successfully, or
-   * until an error occurs.
-   *
-   * @param buffers The data to be written to the stream.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that all
-   * data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return detail::io(next_layer_, core_,
-        detail::write_op<ConstBufferSequence>(buffers), ec);
-  }
-
-  /// Start an asynchronous write.
-  /**
-   * This function is used to asynchronously write one or more bytes of data to
-   * the stream. The function call always returns immediately.
-   *
-   * @param buffers The data to be written to the stream. Although the buffers
-   * object may be copied as necessary, ownership of the underlying buffers is
-   * retained by the caller, which must guarantee that they remain valid until
-   * the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The equivalent function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   *
-   * @note The async_write_some operation may not transmit all of the data to
-   * the peer. Consider using the @ref async_write function if you need to
-   * ensure that all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-    asio::async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    detail::async_io(next_layer_, core_,
-        detail::write_op<ConstBufferSequence>(buffers),
-        init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Read some data from the stream.
-  /**
-   * This function is used to read data from the stream. The function call will
-   * block until one or more bytes of data has been read successfully, or until
-   * an error occurs.
-   *
-   * @param buffers The buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that the
-   * requested amount of data is read before the blocking operation completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t n = read_some(buffers, ec);
-    asio::detail::throw_error(ec, "read_some");
-    return n;
-  }
-
-  /// Read some data from the stream.
-  /**
-   * This function is used to read data from the stream. The function call will
-   * block until one or more bytes of data has been read successfully, or until
-   * an error occurs.
-   *
-   * @param buffers The buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that the
-   * requested amount of data is read before the blocking operation completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return detail::io(next_layer_, core_,
-        detail::read_op<MutableBufferSequence>(buffers), ec);
-  }
-
-  /// Start an asynchronous read.
-  /**
-   * This function is used to asynchronously read one or more bytes of data from
-   * the stream. The function call always returns immediately.
-   *
-   * @param buffers The buffers into which the data will be read. Although the
-   * buffers object may be copied as necessary, ownership of the underlying
-   * buffers is retained by the caller, which must guarantee that they remain
-   * valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The equivalent function
-   * signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   *
-   * @note The async_read_some operation may not read all of the requested
-   * number of bytes. Consider using the @ref async_read function if you need to
-   * ensure that the requested amount of data is read before the asynchronous
-   * operation completes.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-    asio::async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    detail::async_io(next_layer_, core_,
-        detail::read_op<MutableBufferSequence>(buffers),
-        init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  Stream next_layer_;
-  detail::stream_core core_;
-};
-
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_STREAM_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/stream_base.hpp b/tools/sdk/include/asio/asio/ssl/stream_base.hpp
deleted file mode 100644
index 56873e4a5c2..00000000000
--- a/tools/sdk/include/asio/asio/ssl/stream_base.hpp
+++ /dev/null
@@ -1,52 +0,0 @@
-//
-// ssl/stream_base.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_STREAM_BASE_HPP
-#define ASIO_SSL_STREAM_BASE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-
-/// The stream_base class is used as a base for the asio::ssl::stream
-/// class template so that we have a common place to define various enums.
-class stream_base
-{
-public:
-  /// Different handshake types.
-  enum handshake_type
-  {
-    /// Perform handshaking as a client.
-    client,
-
-    /// Perform handshaking as a server.
-    server
-  };
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  ~stream_base()
-  {
-  }
-};
-
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_STREAM_BASE_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/verify_context.hpp b/tools/sdk/include/asio/asio/ssl/verify_context.hpp
deleted file mode 100644
index e17269715af..00000000000
--- a/tools/sdk/include/asio/asio/ssl/verify_context.hpp
+++ /dev/null
@@ -1,67 +0,0 @@
-//
-// ssl/verify_context.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_VERIFY_CONTEXT_HPP
-#define ASIO_SSL_VERIFY_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/ssl/detail/openssl_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-
-/// A simple wrapper around the X509_STORE_CTX type, used during verification of
-/// a peer certificate.
-/**
- * @note The verify_context does not own the underlying X509_STORE_CTX object.
- */
-class verify_context
-  : private noncopyable
-{
-public:
-  /// The native handle type of the verification context.
-  typedef X509_STORE_CTX* native_handle_type;
-
-  /// Constructor.
-  explicit verify_context(native_handle_type handle)
-    : handle_(handle)
-  {
-  }
-
-  /// Get the underlying implementation in the native type.
-  /**
-   * This function may be used to obtain the underlying implementation of the
-   * context. This is intended to allow access to context functionality that is
-   * not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return handle_;
-  }
-
-private:
-  // The underlying native implementation.
-  native_handle_type handle_;
-};
-
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_VERIFY_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/ssl/verify_mode.hpp b/tools/sdk/include/asio/asio/ssl/verify_mode.hpp
deleted file mode 100644
index 8c4b3942628..00000000000
--- a/tools/sdk/include/asio/asio/ssl/verify_mode.hpp
+++ /dev/null
@@ -1,63 +0,0 @@
-//
-// ssl/verify_mode.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SSL_VERIFY_MODE_HPP
-#define ASIO_SSL_VERIFY_MODE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/ssl/detail/openssl_types.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace ssl {
-
-/// Bitmask type for peer verification.
-/**
- * Possible values are:
- *
- * @li @ref verify_none
- * @li @ref verify_peer
- * @li @ref verify_fail_if_no_peer_cert
- * @li @ref verify_client_once
- */
-typedef int verify_mode;
-
-#if defined(GENERATING_DOCUMENTATION)
-/// No verification.
-const int verify_none = implementation_defined;
-
-/// Verify the peer.
-const int verify_peer = implementation_defined;
-
-/// Fail verification if the peer has no certificate. Ignored unless
-/// @ref verify_peer is set.
-const int verify_fail_if_no_peer_cert = implementation_defined;
-
-/// Do not request client certificate on renegotiation. Ignored unless
-/// @ref verify_peer is set.
-const int verify_client_once = implementation_defined;
-#else
-const int verify_none = SSL_VERIFY_NONE;
-const int verify_peer = SSL_VERIFY_PEER;
-const int verify_fail_if_no_peer_cert = SSL_VERIFY_FAIL_IF_NO_PEER_CERT;
-const int verify_client_once = SSL_VERIFY_CLIENT_ONCE;
-#endif
-
-} // namespace ssl
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SSL_VERIFY_MODE_HPP
diff --git a/tools/sdk/include/asio/asio/steady_timer.hpp b/tools/sdk/include/asio/asio/steady_timer.hpp
deleted file mode 100644
index 3ede2084706..00000000000
--- a/tools/sdk/include/asio/asio/steady_timer.hpp
+++ /dev/null
@@ -1,42 +0,0 @@
-//
-// steady_timer.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_STEADY_TIMER_HPP
-#define ASIO_STEADY_TIMER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/basic_waitable_timer.hpp"
-#include "asio/detail/chrono.hpp"
-
-namespace asio {
-
-/// Typedef for a timer based on the steady clock.
-/**
- * This typedef uses the C++11 @c &lt;chrono&gt; standard library facility, if
- * available. Otherwise, it may use the Boost.Chrono library. To explicitly
- * utilise Boost.Chrono, use the basic_waitable_timer template directly:
- * @code
- * typedef basic_waitable_timer<boost::chrono::steady_clock> timer;
- * @endcode
- */
-typedef basic_waitable_timer<chrono::steady_clock> steady_timer;
-
-} // namespace asio
-
-#endif // defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_STEADY_TIMER_HPP
diff --git a/tools/sdk/include/asio/asio/strand.hpp b/tools/sdk/include/asio/asio/strand.hpp
deleted file mode 100644
index ea78ef02feb..00000000000
--- a/tools/sdk/include/asio/asio/strand.hpp
+++ /dev/null
@@ -1,286 +0,0 @@
-//
-// strand.hpp
-// ~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_STRAND_HPP
-#define ASIO_STRAND_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/strand_executor_service.hpp"
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Provides serialised function invocation for any executor type.
-template <typename Executor>
-class strand
-{
-public:
-  /// The type of the underlying executor.
-  typedef Executor inner_executor_type;
-
-  /// Default constructor.
-  /**
-   * This constructor is only valid if the underlying executor type is default
-   * constructible.
-   */
-  strand()
-    : executor_(),
-      impl_(use_service<detail::strand_executor_service>(
-            executor_.context()).create_implementation())
-  {
-  }
-
-  /// Construct a strand for the specified executor.
-  explicit strand(const Executor& e)
-    : executor_(e),
-      impl_(use_service<detail::strand_executor_service>(
-            executor_.context()).create_implementation())
-  {
-  }
-
-  /// Copy constructor.
-  strand(const strand& other) ASIO_NOEXCEPT
-    : executor_(other.executor_),
-      impl_(other.impl_)
-  {
-  }
-
-  /// Converting constructor.
-  /**
-   * This constructor is only valid if the @c OtherExecutor type is convertible
-   * to @c Executor.
-   */
-  template <class OtherExecutor>
-  strand(
-      const strand<OtherExecutor>& other) ASIO_NOEXCEPT
-    : executor_(other.executor_),
-      impl_(other.impl_)
-  {
-  }
-
-  /// Assignment operator.
-  strand& operator=(const strand& other) ASIO_NOEXCEPT
-  {
-    executor_ = other.executor_;
-    impl_ = other.impl_;
-    return *this;
-  }
-
-  /// Converting assignment operator.
-  /**
-   * This assignment operator is only valid if the @c OtherExecutor type is
-   * convertible to @c Executor.
-   */
-  template <class OtherExecutor>
-  strand& operator=(
-      const strand<OtherExecutor>& other) ASIO_NOEXCEPT
-  {
-    executor_ = other.executor_;
-    impl_ = other.impl_;
-    return *this;
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move constructor.
-  strand(strand&& other) ASIO_NOEXCEPT
-    : executor_(ASIO_MOVE_CAST(Executor)(other.executor_)),
-      impl_(ASIO_MOVE_CAST(implementation_type)(other.impl_))
-  {
-  }
-
-  /// Converting move constructor.
-  /**
-   * This constructor is only valid if the @c OtherExecutor type is convertible
-   * to @c Executor.
-   */
-  template <class OtherExecutor>
-  strand(strand<OtherExecutor>&& other) ASIO_NOEXCEPT
-    : executor_(ASIO_MOVE_CAST(OtherExecutor)(other)),
-      impl_(ASIO_MOVE_CAST(implementation_type)(other.impl_))
-  {
-  }
-
-  /// Move assignment operator.
-  strand& operator=(strand&& other) ASIO_NOEXCEPT
-  {
-    executor_ = ASIO_MOVE_CAST(Executor)(other);
-    impl_ = ASIO_MOVE_CAST(implementation_type)(other.impl_);
-    return *this;
-  }
-
-  /// Converting move assignment operator.
-  /**
-   * This assignment operator is only valid if the @c OtherExecutor type is
-   * convertible to @c Executor.
-   */
-  template <class OtherExecutor>
-  strand& operator=(
-      const strand<OtherExecutor>&& other) ASIO_NOEXCEPT
-  {
-    executor_ = ASIO_MOVE_CAST(OtherExecutor)(other);
-    impl_ = ASIO_MOVE_CAST(implementation_type)(other.impl_);
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destructor.
-  ~strand()
-  {
-  }
-
-  /// Obtain the underlying executor.
-  inner_executor_type get_inner_executor() const ASIO_NOEXCEPT
-  {
-    return executor_;
-  }
-
-  /// Obtain the underlying execution context.
-  execution_context& context() const ASIO_NOEXCEPT
-  {
-    return executor_.context();
-  }
-
-  /// Inform the strand that it has some outstanding work to do.
-  /**
-   * The strand delegates this call to its underlying executor.
-   */
-  void on_work_started() const ASIO_NOEXCEPT
-  {
-    executor_.on_work_started();
-  }
-
-  /// Inform the strand that some work is no longer outstanding.
-  /**
-   * The strand delegates this call to its underlying executor.
-   */
-  void on_work_finished() const ASIO_NOEXCEPT
-  {
-    executor_.on_work_finished();
-  }
-
-  /// Request the strand to invoke the given function object.
-  /**
-   * This function is used to ask the strand to execute the given function
-   * object on its underlying executor. The function object will be executed
-   * inside this function if the strand is not otherwise busy and if the
-   * underlying executor's @c dispatch() function is also able to execute the
-   * function before returning.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void dispatch(ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-  {
-    detail::strand_executor_service::dispatch(impl_,
-        executor_, ASIO_MOVE_CAST(Function)(f), a);
-  }
-
-  /// Request the strand to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object will never be executed inside this function.
-   * Instead, it will be scheduled by the underlying executor's defer function.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void post(ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-  {
-    detail::strand_executor_service::post(impl_,
-        executor_, ASIO_MOVE_CAST(Function)(f), a);
-  }
-
-  /// Request the strand to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object will never be executed inside this function.
-   * Instead, it will be scheduled by the underlying executor's defer function.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void defer(ASIO_MOVE_ARG(Function) f, const Allocator& a) const
-  {
-    detail::strand_executor_service::defer(impl_,
-        executor_, ASIO_MOVE_CAST(Function)(f), a);
-  }
-
-  /// Determine whether the strand is running in the current thread.
-  /**
-   * @return @c true if the current thread is executing a function that was
-   * submitted to the strand using post(), dispatch() or defer(). Otherwise
-   * returns @c false.
-   */
-  bool running_in_this_thread() const ASIO_NOEXCEPT
-  {
-    return detail::strand_executor_service::running_in_this_thread(impl_);
-  }
-
-  /// Compare two strands for equality.
-  /**
-   * Two strands are equal if they refer to the same ordered, non-concurrent
-   * state.
-   */
-  friend bool operator==(const strand& a, const strand& b) ASIO_NOEXCEPT
-  {
-    return a.impl_ == b.impl_;
-  }
-
-  /// Compare two strands for inequality.
-  /**
-   * Two strands are equal if they refer to the same ordered, non-concurrent
-   * state.
-   */
-  friend bool operator!=(const strand& a, const strand& b) ASIO_NOEXCEPT
-  {
-    return a.impl_ != b.impl_;
-  }
-
-private:
-  Executor executor_;
-  typedef detail::strand_executor_service::implementation_type
-    implementation_type;
-  implementation_type impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-// If both io_context.hpp and strand.hpp have been included, automatically
-// include the header file needed for the io_context::strand class.
-#if !defined(ASIO_NO_EXTENSIONS)
-# if defined(ASIO_IO_CONTEXT_HPP)
-#  include "asio/io_context_strand.hpp"
-# endif // defined(ASIO_IO_CONTEXT_HPP)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-#endif // ASIO_STRAND_HPP
diff --git a/tools/sdk/include/asio/asio/stream_socket_service.hpp b/tools/sdk/include/asio/asio/stream_socket_service.hpp
deleted file mode 100644
index 91b0a711f2a..00000000000
--- a/tools/sdk/include/asio/asio/stream_socket_service.hpp
+++ /dev/null
@@ -1,412 +0,0 @@
-//
-// stream_socket_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_STREAM_SOCKET_SERVICE_HPP
-#define ASIO_STREAM_SOCKET_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/type_traits.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_WINDOWS_RUNTIME)
-# include "asio/detail/winrt_ssocket_service.hpp"
-#elif defined(ASIO_HAS_IOCP)
-# include "asio/detail/win_iocp_socket_service.hpp"
-#else
-# include "asio/detail/reactive_socket_service.hpp"
-#endif
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default service implementation for a stream socket.
-template <typename Protocol>
-class stream_socket_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<stream_socket_service<Protocol> >
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-  /// The protocol type.
-  typedef Protocol protocol_type;
-
-  /// The endpoint type.
-  typedef typename Protocol::endpoint endpoint_type;
-
-private:
-  // The type of the platform-specific implementation.
-#if defined(ASIO_WINDOWS_RUNTIME)
-  typedef detail::winrt_ssocket_service<Protocol> service_impl_type;
-#elif defined(ASIO_HAS_IOCP)
-  typedef detail::win_iocp_socket_service<Protocol> service_impl_type;
-#else
-  typedef detail::reactive_socket_service<Protocol> service_impl_type;
-#endif
-
-public:
-  /// The type of a stream socket implementation.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef typename service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native socket type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef typename service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new stream socket service for the specified io_context.
-  explicit stream_socket_service(asio::io_context& io_context)
-    : asio::detail::service_base<
-        stream_socket_service<Protocol> >(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new stream socket implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new stream socket implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another stream socket implementation.
-  void move_assign(implementation_type& impl,
-      stream_socket_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-
-  // All socket services have access to each other's implementations.
-  template <typename Protocol1> friend class stream_socket_service;
-
-  /// Move-construct a new stream socket implementation from another protocol
-  /// type.
-  template <typename Protocol1>
-  void converting_move_construct(implementation_type& impl,
-      stream_socket_service<Protocol1>& other_service,
-      typename stream_socket_service<
-        Protocol1>::implementation_type& other_impl,
-      typename enable_if<is_convertible<
-        Protocol1, Protocol>::value>::type* = 0)
-  {
-    service_impl_.template converting_move_construct<Protocol1>(
-        impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a stream socket implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Open a stream socket.
-  ASIO_SYNC_OP_VOID open(implementation_type& impl,
-      const protocol_type& protocol, asio::error_code& ec)
-  {
-    if (protocol.type() == ASIO_OS_DEF(SOCK_STREAM))
-      service_impl_.open(impl, protocol, ec);
-    else
-      ec = asio::error::invalid_argument;
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Assign an existing native socket to a stream socket.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const protocol_type& protocol, const native_handle_type& native_socket,
-      asio::error_code& ec)
-  {
-    service_impl_.assign(impl, protocol, native_socket, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Close a stream socket implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Release ownership of the underlying socket.
-  native_handle_type release(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return service_impl_.release(impl, ec);
-  }
-
-  /// Get the native socket implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the socket.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the socket is at the out-of-band data mark.
-  bool at_mark(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.at_mark(impl, ec);
-  }
-
-  /// Determine the number of bytes available for reading.
-  std::size_t available(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.available(impl, ec);
-  }
-
-  /// Bind the stream socket to the specified local endpoint.
-  ASIO_SYNC_OP_VOID bind(implementation_type& impl,
-      const endpoint_type& endpoint, asio::error_code& ec)
-  {
-    service_impl_.bind(impl, endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Connect the stream socket to the specified endpoint.
-  ASIO_SYNC_OP_VOID connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint, asio::error_code& ec)
-  {
-    service_impl_.connect(impl, peer_endpoint, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Start an asynchronous connect.
-  template <typename ConnectHandler>
-  ASIO_INITFN_RESULT_TYPE(ConnectHandler,
-      void (asio::error_code))
-  async_connect(implementation_type& impl,
-      const endpoint_type& peer_endpoint,
-      ASIO_MOVE_ARG(ConnectHandler) handler)
-  {
-    async_completion<ConnectHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_connect(impl, peer_endpoint, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Set a socket option.
-  template <typename SettableSocketOption>
-  ASIO_SYNC_OP_VOID set_option(implementation_type& impl,
-      const SettableSocketOption& option, asio::error_code& ec)
-  {
-    service_impl_.set_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get a socket option.
-  template <typename GettableSocketOption>
-  ASIO_SYNC_OP_VOID get_option(const implementation_type& impl,
-      GettableSocketOption& option, asio::error_code& ec) const
-  {
-    service_impl_.get_option(impl, option, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform an IO control command on the socket.
-  template <typename IoControlCommand>
-  ASIO_SYNC_OP_VOID io_control(implementation_type& impl,
-      IoControlCommand& command, asio::error_code& ec)
-  {
-    service_impl_.io_control(impl, command, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the socket.
-  bool non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the socket.
-  ASIO_SYNC_OP_VOID non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Gets the non-blocking mode of the native socket implementation.
-  bool native_non_blocking(const implementation_type& impl) const
-  {
-    return service_impl_.native_non_blocking(impl);
-  }
-
-  /// Sets the non-blocking mode of the native socket implementation.
-  ASIO_SYNC_OP_VOID native_non_blocking(implementation_type& impl,
-      bool mode, asio::error_code& ec)
-  {
-    service_impl_.native_non_blocking(impl, mode, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the local endpoint.
-  endpoint_type local_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.local_endpoint(impl, ec);
-  }
-
-  /// Get the remote endpoint.
-  endpoint_type remote_endpoint(const implementation_type& impl,
-      asio::error_code& ec) const
-  {
-    return service_impl_.remote_endpoint(impl, ec);
-  }
-
-  /// Disable sends or receives on the socket.
-  ASIO_SYNC_OP_VOID shutdown(implementation_type& impl,
-      socket_base::shutdown_type what, asio::error_code& ec)
-  {
-    service_impl_.shutdown(impl, what, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Wait for the socket to become ready to read, ready to write, or to have
-  /// pending error conditions.
-  ASIO_SYNC_OP_VOID wait(implementation_type& impl,
-      socket_base::wait_type w, asio::error_code& ec)
-  {
-    service_impl_.wait(impl, w, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Asynchronously wait for the socket to become ready to read, ready to
-  /// write, or to have pending error conditions.
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(implementation_type& impl, socket_base::wait_type w,
-      ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_wait(impl, w, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Send the given data to the peer.
-  template <typename ConstBufferSequence>
-  std::size_t send(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.send(impl, buffers, flags, ec);
-  }
-
-  /// Start an asynchronous send.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_send(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_send(impl, buffers, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Receive some data from the peer.
-  template <typename MutableBufferSequence>
-  std::size_t receive(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags, asio::error_code& ec)
-  {
-    return service_impl_.receive(impl, buffers, flags, ec);
-  }
-
-  /// Start an asynchronous receive.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_receive(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      socket_base::message_flags flags,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_receive(impl, buffers, flags, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_STREAM_SOCKET_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/streambuf.hpp b/tools/sdk/include/asio/asio/streambuf.hpp
deleted file mode 100644
index cb3f35f7d67..00000000000
--- a/tools/sdk/include/asio/asio/streambuf.hpp
+++ /dev/null
@@ -1,33 +0,0 @@
-//
-// streambuf.hpp
-// ~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_STREAMBUF_HPP
-#define ASIO_STREAMBUF_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_NO_IOSTREAM)
-
-#include "asio/basic_streambuf.hpp"
-
-namespace asio {
-
-/// Typedef for the typical usage of basic_streambuf.
-typedef basic_streambuf<> streambuf;
-
-} // namespace asio
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-
-#endif // ASIO_STREAMBUF_HPP
diff --git a/tools/sdk/include/asio/asio/system_context.hpp b/tools/sdk/include/asio/asio/system_context.hpp
deleted file mode 100644
index ccd11134305..00000000000
--- a/tools/sdk/include/asio/asio/system_context.hpp
+++ /dev/null
@@ -1,78 +0,0 @@
-//
-// system_context.hpp
-// ~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SYSTEM_CONTEXT_HPP
-#define ASIO_SYSTEM_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/scheduler.hpp"
-#include "asio/detail/thread_group.hpp"
-#include "asio/execution_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-class system_executor;
-
-/// The executor context for the system executor.
-class system_context : public execution_context
-{
-public:
-  /// The executor type associated with the context.
-  typedef system_executor executor_type;
-
-  /// Destructor shuts down all threads in the system thread pool.
-  ASIO_DECL ~system_context();
-
-  /// Obtain an executor for the context.
-  executor_type get_executor() ASIO_NOEXCEPT;
-
-  /// Signal all threads in the system thread pool to stop.
-  ASIO_DECL void stop();
-
-  /// Determine whether the system thread pool has been stopped.
-  ASIO_DECL bool stopped() const ASIO_NOEXCEPT;
-
-  /// Join all threads in the system thread pool.
-  ASIO_DECL void join();
-
-#if defined(GENERATING_DOCUMENTATION)
-private:
-#endif // defined(GENERATING_DOCUMENTATION)
-  // Constructor creates all threads in the system thread pool.
-  ASIO_DECL system_context();
-
-private:
-  friend class system_executor;
-
-  struct thread_function;
-
-  // The underlying scheduler.
-  detail::scheduler& scheduler_;
-
-  // The threads in the system thread pool.
-  detail::thread_group threads_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/system_context.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/impl/system_context.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_SYSTEM_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/system_error.hpp b/tools/sdk/include/asio/asio/system_error.hpp
deleted file mode 100644
index 63908941627..00000000000
--- a/tools/sdk/include/asio/asio/system_error.hpp
+++ /dev/null
@@ -1,131 +0,0 @@
-//
-// system_error.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SYSTEM_ERROR_HPP
-#define ASIO_SYSTEM_ERROR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_SYSTEM_ERROR)
-# include <system_error>
-#else // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-# include <cerrno>
-# include <exception>
-# include <string>
-# include "asio/error_code.hpp"
-# include "asio/detail/scoped_ptr.hpp"
-#endif // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-#if defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-typedef std::system_error system_error;
-
-#else // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-/// The system_error class is used to represent system conditions that
-/// prevent the library from operating correctly.
-class system_error
-  : public std::exception
-{
-public:
-  /// Construct with an error code.
-  system_error(const error_code& ec)
-    : code_(ec),
-      context_()
-  {
-  }
-
-  /// Construct with an error code and context.
-  system_error(const error_code& ec, const std::string& context)
-    : code_(ec),
-      context_(context)
-  {
-  }
-
-  /// Copy constructor.
-  system_error(const system_error& other)
-    : std::exception(other),
-      code_(other.code_),
-      context_(other.context_),
-      what_()
-  {
-  }
-
-  /// Destructor.
-  virtual ~system_error() throw ()
-  {
-  }
-
-  /// Assignment operator.
-  system_error& operator=(const system_error& e)
-  {
-    context_ = e.context_;
-    code_ = e.code_;
-    what_.reset();
-    return *this;
-  }
-
-  /// Get a string representation of the exception.
-  virtual const char* what() const throw ()
-  {
-#if !defined(ASIO_NO_EXCEPTIONS)
-    try
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-    {
-      if (!what_.get())
-      {
-        std::string tmp(context_);
-        if (tmp.length())
-          tmp += ": ";
-        tmp += code_.message();
-        what_.reset(new std::string(tmp));
-      }
-      return what_->c_str();
-    }
-#if !defined(ASIO_NO_EXCEPTIONS)
-    catch (std::exception&)
-    {
-      return "system_error";
-    }
-#endif // !defined(ASIO_NO_EXCEPTIONS)
-  }
-
-  /// Get the error code associated with the exception.
-  error_code code() const
-  {
-    return code_;
-  }
-
-private:
-  // The code associated with the error.
-  error_code code_;
-
-  // The context associated with the error.
-  std::string context_;
-
-  // The string representation of the error.
-  mutable asio::detail::scoped_ptr<std::string> what_;
-};
-
-#endif // defined(ASIO_HAS_STD_SYSTEM_ERROR)
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_SYSTEM_ERROR_HPP
diff --git a/tools/sdk/include/asio/asio/system_executor.hpp b/tools/sdk/include/asio/asio/system_executor.hpp
deleted file mode 100644
index b588a21b410..00000000000
--- a/tools/sdk/include/asio/asio/system_executor.hpp
+++ /dev/null
@@ -1,129 +0,0 @@
-//
-// system_executor.hpp
-// ~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SYSTEM_EXECUTOR_HPP
-#define ASIO_SYSTEM_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-class system_context;
-
-/// An executor that uses arbitrary threads.
-/**
- * The system executor represents an execution context where functions are
- * permitted to run on arbitrary threads. The post() and defer() functions
- * schedule the function to run on an unspecified system thread pool, and
- * dispatch() invokes the function immediately.
- */
-class system_executor
-{
-public:
-  /// Obtain the underlying execution context.
-  system_context& context() const ASIO_NOEXCEPT;
-
-  /// Inform the executor that it has some outstanding work to do.
-  /**
-   * For the system executor, this is a no-op.
-   */
-  void on_work_started() const ASIO_NOEXCEPT
-  {
-  }
-
-  /// Inform the executor that some work is no longer outstanding.
-  /**
-   * For the system executor, this is a no-op.
-   */
-  void on_work_finished() const ASIO_NOEXCEPT
-  {
-  }
-
-  /// Request the system executor to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object will always be executed inside this function.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void dispatch(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Request the system executor to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object will never be executed inside this function.
-   * Instead, it will be scheduled to run on an unspecified system thread pool.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void post(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Request the system executor to invoke the given function object.
-  /**
-   * This function is used to ask the executor to execute the given function
-   * object. The function object will never be executed inside this function.
-   * Instead, it will be scheduled to run on an unspecified system thread pool.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void defer(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Compare two executors for equality.
-  /**
-   * System executors always compare equal.
-   */
-  friend bool operator==(const system_executor&,
-      const system_executor&) ASIO_NOEXCEPT
-  {
-    return true;
-  }
-
-  /// Compare two executors for inequality.
-  /**
-   * System executors always compare equal.
-   */
-  friend bool operator!=(const system_executor&,
-      const system_executor&) ASIO_NOEXCEPT
-  {
-    return false;
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/system_executor.hpp"
-
-#endif // ASIO_SYSTEM_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/system_timer.hpp b/tools/sdk/include/asio/asio/system_timer.hpp
deleted file mode 100644
index e75e7d4c12b..00000000000
--- a/tools/sdk/include/asio/asio/system_timer.hpp
+++ /dev/null
@@ -1,42 +0,0 @@
-//
-// system_timer.hpp
-// ~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_SYSTEM_TIMER_HPP
-#define ASIO_SYSTEM_TIMER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/basic_waitable_timer.hpp"
-#include "asio/detail/chrono.hpp"
-
-namespace asio {
-
-/// Typedef for a timer based on the system clock.
-/**
- * This typedef uses the C++11 @c &lt;chrono&gt; standard library facility, if
- * available. Otherwise, it may use the Boost.Chrono library. To explicitly
- * utilise Boost.Chrono, use the basic_waitable_timer template directly:
- * @code
- * typedef basic_waitable_timer<boost::chrono::system_clock> timer;
- * @endcode
- */
-typedef basic_waitable_timer<chrono::system_clock> system_timer;
-
-} // namespace asio
-
-#endif // defined(ASIO_HAS_CHRONO) || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_SYSTEM_TIMER_HPP
diff --git a/tools/sdk/include/asio/asio/thread.hpp b/tools/sdk/include/asio/asio/thread.hpp
deleted file mode 100644
index eeeef7bb5cf..00000000000
--- a/tools/sdk/include/asio/asio/thread.hpp
+++ /dev/null
@@ -1,92 +0,0 @@
-//
-// thread.hpp
-// ~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_THREAD_HPP
-#define ASIO_THREAD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/thread.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// A simple abstraction for starting threads.
-/**
- * The asio::thread class implements the smallest possible subset of the
- * functionality of boost::thread. It is intended to be used only for starting
- * a thread and waiting for it to exit. If more extensive threading
- * capabilities are required, you are strongly advised to use something else.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Example
- * A typical use of asio::thread would be to launch a thread to run an
- * io_context's event processing loop:
- *
- * @par
- * @code asio::io_context io_context;
- * // ...
- * asio::thread t(boost::bind(&asio::io_context::run, &io_context));
- * // ...
- * t.join(); @endcode
- */
-class thread
-  : private noncopyable
-{
-public:
-  /// Start a new thread that executes the supplied function.
-  /**
-   * This constructor creates a new thread that will execute the given function
-   * or function object.
-   *
-   * @param f The function or function object to be run in the thread. The
-   * function signature must be: @code void f(); @endcode
-   */
-  template <typename Function>
-  explicit thread(Function f)
-    : impl_(f)
-  {
-  }
-
-  /// Destructor.
-  ~thread()
-  {
-  }
-
-  /// Wait for the thread to exit.
-  /**
-   * This function will block until the thread has exited.
-   *
-   * If this function is not called before the thread object is destroyed, the
-   * thread itself will continue to run until completion. You will, however,
-   * no longer have the ability to wait for it to exit.
-   */
-  void join()
-  {
-    impl_.join();
-  }
-
-private:
-  detail::thread impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_THREAD_HPP
diff --git a/tools/sdk/include/asio/asio/thread_pool.hpp b/tools/sdk/include/asio/asio/thread_pool.hpp
deleted file mode 100644
index f22f18d1177..00000000000
--- a/tools/sdk/include/asio/asio/thread_pool.hpp
+++ /dev/null
@@ -1,232 +0,0 @@
-//
-// thread_pool.hpp
-// ~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_THREAD_POOL_HPP
-#define ASIO_THREAD_POOL_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/scheduler.hpp"
-#include "asio/detail/thread_group.hpp"
-#include "asio/execution_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// A simple fixed-size thread pool.
-/**
- * The thread pool class is an execution context where functions are permitted
- * to run on one of a fixed number of threads.
- *
- * @par Submitting tasks to the pool
- *
- * To submit functions to the io_context, use the @ref asio::dispatch,
- * @ref asio::post or @ref asio::defer free functions.
- *
- * For example:
- *
- * @code void my_task()
- * {
- *   ...
- * }
- *
- * ...
- *
- * // Launch the pool with four threads.
- * asio::thread_pool pool(4);
- *
- * // Submit a function to the pool.
- * asio::post(pool, my_task);
- *
- * // Submit a lambda object to the pool.
- * asio::post(pool,
- *     []()
- *     {
- *       ...
- *     });
- *
- * // Wait for all tasks in the pool to complete.
- * pool.join(); @endcode
- */
-class thread_pool
-  : public execution_context
-{
-public:
-  class executor_type;
-
-  /// Constructs a pool with an automatically determined number of threads.
-  ASIO_DECL thread_pool();
-
-  /// Constructs a pool with a specified number of threads.
-  ASIO_DECL thread_pool(std::size_t num_threads);
-
-  /// Destructor.
-  /**
-   * Automatically stops and joins the pool, if not explicitly done beforehand.
-   */
-  ASIO_DECL ~thread_pool();
-
-  /// Obtains the executor associated with the pool.
-  executor_type get_executor() ASIO_NOEXCEPT;
-
-  /// Stops the threads.
-  /**
-   * This function stops the threads as soon as possible. As a result of calling
-   * @c stop(), pending function objects may be never be invoked.
-   */
-  ASIO_DECL void stop();
-
-  /// Joins the threads.
-  /**
-   * This function blocks until the threads in the pool have completed. If @c
-   * stop() is not called prior to @c join(), the @c join() call will wait
-   * until the pool has no more outstanding work.
-   */
-  ASIO_DECL void join();
-
-private:
-  friend class executor_type;
-  struct thread_function;
-
-  // The underlying scheduler.
-  detail::scheduler& scheduler_;
-
-  // The threads in the pool.
-  detail::thread_group threads_;
-};
-
-/// Executor used to submit functions to a thread pool.
-class thread_pool::executor_type
-{
-public:
-  /// Obtain the underlying execution context.
-  thread_pool& context() const ASIO_NOEXCEPT;
-
-  /// Inform the thread pool that it has some outstanding work to do.
-  /**
-   * This function is used to inform the thread pool that some work has begun.
-   * This ensures that the thread pool's join() function will not return while
-   * the work is underway.
-   */
-  void on_work_started() const ASIO_NOEXCEPT;
-
-  /// Inform the thread pool that some work is no longer outstanding.
-  /**
-   * This function is used to inform the thread pool that some work has
-   * finished. Once the count of unfinished work reaches zero, the thread
-   * pool's join() function is permitted to exit.
-   */
-  void on_work_finished() const ASIO_NOEXCEPT;
-
-  /// Request the thread pool to invoke the given function object.
-  /**
-   * This function is used to ask the thread pool to execute the given function
-   * object. If the current thread belongs to the pool, @c dispatch() executes
-   * the function before returning. Otherwise, the function will be scheduled
-   * to run on the thread pool.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void dispatch(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Request the thread pool to invoke the given function object.
-  /**
-   * This function is used to ask the thread pool to execute the given function
-   * object. The function object will never be executed inside @c post().
-   * Instead, it will be scheduled to run on the thread pool.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void post(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Request the thread pool to invoke the given function object.
-  /**
-   * This function is used to ask the thread pool to execute the given function
-   * object. The function object will never be executed inside @c defer().
-   * Instead, it will be scheduled to run on the thread pool.
-   *
-   * If the current thread belongs to the thread pool, @c defer() will delay
-   * scheduling the function object until the current thread returns control to
-   * the pool.
-   *
-   * @param f The function object to be called. The executor will make
-   * a copy of the handler object as required. The function signature of the
-   * function object must be: @code void function(); @endcode
-   *
-   * @param a An allocator that may be used by the executor to allocate the
-   * internal storage needed for function invocation.
-   */
-  template <typename Function, typename Allocator>
-  void defer(ASIO_MOVE_ARG(Function) f, const Allocator& a) const;
-
-  /// Determine whether the thread pool is running in the current thread.
-  /**
-   * @return @c true if the current thread belongs to the pool. Otherwise
-   * returns @c false.
-   */
-  bool running_in_this_thread() const ASIO_NOEXCEPT;
-
-  /// Compare two executors for equality.
-  /**
-   * Two executors are equal if they refer to the same underlying thread pool.
-   */
-  friend bool operator==(const executor_type& a,
-      const executor_type& b) ASIO_NOEXCEPT
-  {
-    return &a.pool_ == &b.pool_;
-  }
-
-  /// Compare two executors for inequality.
-  /**
-   * Two executors are equal if they refer to the same underlying thread pool.
-   */
-  friend bool operator!=(const executor_type& a,
-      const executor_type& b) ASIO_NOEXCEPT
-  {
-    return &a.pool_ != &b.pool_;
-  }
-
-private:
-  friend class thread_pool;
-
-  // Constructor.
-  explicit executor_type(thread_pool& p) : pool_(p) {}
-
-  // The underlying thread pool.
-  thread_pool& pool_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/thread_pool.hpp"
-#if defined(ASIO_HEADER_ONLY)
-# include "asio/impl/thread_pool.ipp"
-#endif // defined(ASIO_HEADER_ONLY)
-
-#endif // ASIO_THREAD_POOL_HPP
diff --git a/tools/sdk/include/asio/asio/time_traits.hpp b/tools/sdk/include/asio/asio/time_traits.hpp
deleted file mode 100644
index 72f4aabe782..00000000000
--- a/tools/sdk/include/asio/asio/time_traits.hpp
+++ /dev/null
@@ -1,86 +0,0 @@
-//
-// time_traits.hpp
-// ~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_TIME_TRAITS_HPP
-#define ASIO_TIME_TRAITS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/socket_types.hpp" // Must come before posix_time.
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <boost/date_time/posix_time/posix_time_types.hpp>
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Time traits suitable for use with the deadline timer.
-template <typename Time>
-struct time_traits;
-
-/// Time traits specialised for posix_time.
-template <>
-struct time_traits<boost::posix_time::ptime>
-{
-  /// The time type.
-  typedef boost::posix_time::ptime time_type;
-
-  /// The duration type.
-  typedef boost::posix_time::time_duration duration_type;
-
-  /// Get the current time.
-  static time_type now()
-  {
-#if defined(BOOST_DATE_TIME_HAS_HIGH_PRECISION_CLOCK)
-    return boost::posix_time::microsec_clock::universal_time();
-#else // defined(BOOST_DATE_TIME_HAS_HIGH_PRECISION_CLOCK)
-    return boost::posix_time::second_clock::universal_time();
-#endif // defined(BOOST_DATE_TIME_HAS_HIGH_PRECISION_CLOCK)
-  }
-
-  /// Add a duration to a time.
-  static time_type add(const time_type& t, const duration_type& d)
-  {
-    return t + d;
-  }
-
-  /// Subtract one time from another.
-  static duration_type subtract(const time_type& t1, const time_type& t2)
-  {
-    return t1 - t2;
-  }
-
-  /// Test whether one time is less than another.
-  static bool less_than(const time_type& t1, const time_type& t2)
-  {
-    return t1 < t2;
-  }
-
-  /// Convert to POSIX duration type.
-  static boost::posix_time::time_duration to_posix_duration(
-      const duration_type& d)
-  {
-    return d;
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-       // || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_TIME_TRAITS_HPP
diff --git a/tools/sdk/include/asio/asio/ts/buffer.hpp b/tools/sdk/include/asio/asio/ts/buffer.hpp
deleted file mode 100644
index faf08a474b0..00000000000
--- a/tools/sdk/include/asio/asio/ts/buffer.hpp
+++ /dev/null
@@ -1,24 +0,0 @@
-//
-// ts/buffer.hpp
-// ~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_TS_BUFFER_HPP
-#define ASIO_TS_BUFFER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/buffer.hpp"
-#include "asio/completion_condition.hpp"
-#include "asio/read.hpp"
-#include "asio/write.hpp"
-#include "asio/read_until.hpp"
-
-#endif // ASIO_TS_BUFFER_HPP
diff --git a/tools/sdk/include/asio/asio/ts/executor.hpp b/tools/sdk/include/asio/asio/ts/executor.hpp
deleted file mode 100644
index 8669cb6c577..00000000000
--- a/tools/sdk/include/asio/asio/ts/executor.hpp
+++ /dev/null
@@ -1,35 +0,0 @@
-//
-// ts/executor.hpp
-// ~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_TS_EXECUTOR_HPP
-#define ASIO_TS_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/handler_type.hpp"
-#include "asio/async_result.hpp"
-#include "asio/associated_allocator.hpp"
-#include "asio/execution_context.hpp"
-#include "asio/is_executor.hpp"
-#include "asio/associated_executor.hpp"
-#include "asio/bind_executor.hpp"
-#include "asio/executor_work_guard.hpp"
-#include "asio/system_executor.hpp"
-#include "asio/executor.hpp"
-#include "asio/dispatch.hpp"
-#include "asio/post.hpp"
-#include "asio/defer.hpp"
-#include "asio/strand.hpp"
-#include "asio/packaged_task.hpp"
-#include "asio/use_future.hpp"
-
-#endif // ASIO_TS_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/ts/internet.hpp b/tools/sdk/include/asio/asio/ts/internet.hpp
deleted file mode 100644
index 6282e905a02..00000000000
--- a/tools/sdk/include/asio/asio/ts/internet.hpp
+++ /dev/null
@@ -1,40 +0,0 @@
-//
-// ts/internet.hpp
-// ~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_TS_INTERNET_HPP
-#define ASIO_TS_INTERNET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/ip/address.hpp"
-#include "asio/ip/address_v4.hpp"
-#include "asio/ip/address_v4_iterator.hpp"
-#include "asio/ip/address_v4_range.hpp"
-#include "asio/ip/address_v6.hpp"
-#include "asio/ip/address_v6_iterator.hpp"
-#include "asio/ip/address_v6_range.hpp"
-#include "asio/ip/bad_address_cast.hpp"
-#include "asio/ip/basic_endpoint.hpp"
-#include "asio/ip/basic_resolver_query.hpp"
-#include "asio/ip/basic_resolver_entry.hpp"
-#include "asio/ip/basic_resolver_iterator.hpp"
-#include "asio/ip/basic_resolver.hpp"
-#include "asio/ip/host_name.hpp"
-#include "asio/ip/network_v4.hpp"
-#include "asio/ip/network_v6.hpp"
-#include "asio/ip/tcp.hpp"
-#include "asio/ip/udp.hpp"
-#include "asio/ip/v6_only.hpp"
-#include "asio/ip/unicast.hpp"
-#include "asio/ip/multicast.hpp"
-
-#endif // ASIO_TS_INTERNET_HPP
diff --git a/tools/sdk/include/asio/asio/ts/io_context.hpp b/tools/sdk/include/asio/asio/ts/io_context.hpp
deleted file mode 100644
index b967cd63edf..00000000000
--- a/tools/sdk/include/asio/asio/ts/io_context.hpp
+++ /dev/null
@@ -1,20 +0,0 @@
-//
-// ts/io_context.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_TS_IO_CONTEXT_HPP
-#define ASIO_TS_IO_CONTEXT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/io_context.hpp"
-
-#endif // ASIO_TS_IO_CONTEXT_HPP
diff --git a/tools/sdk/include/asio/asio/ts/net.hpp b/tools/sdk/include/asio/asio/ts/net.hpp
deleted file mode 100644
index f96075d9fe6..00000000000
--- a/tools/sdk/include/asio/asio/ts/net.hpp
+++ /dev/null
@@ -1,26 +0,0 @@
-//
-// ts/net.hpp
-// ~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_TS_NET_HPP
-#define ASIO_TS_NET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/ts/netfwd.hpp"
-#include "asio/ts/executor.hpp"
-#include "asio/ts/io_context.hpp"
-#include "asio/ts/timer.hpp"
-#include "asio/ts/buffer.hpp"
-#include "asio/ts/socket.hpp"
-#include "asio/ts/internet.hpp"
-
-#endif // ASIO_TS_NET_HPP
diff --git a/tools/sdk/include/asio/asio/ts/netfwd.hpp b/tools/sdk/include/asio/asio/ts/netfwd.hpp
deleted file mode 100644
index 657a21d3727..00000000000
--- a/tools/sdk/include/asio/asio/ts/netfwd.hpp
+++ /dev/null
@@ -1,197 +0,0 @@
-//
-// ts/netfwd.hpp
-// ~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_TS_NETFWD_HPP
-#define ASIO_TS_NETFWD_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_CHRONO)
-# include "asio/detail/chrono.hpp"
-#endif // defined(ASIO_HAS_CHRONO)
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME)
-# include "asio/detail/date_time_fwd.hpp"
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-
-#if !defined(GENERATING_DOCUMENTATION)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-class execution_context;
-
-template <typename T, typename Executor>
-class executor_binder;
-
-template <typename Executor>
-class executor_work_guard;
-
-class system_executor;
-
-class executor;
-
-template <typename Executor>
-class strand;
-
-class io_context;
-
-template <typename Clock>
-struct wait_traits;
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME)
-
-template <typename Time>
-struct time_traits;
-
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-template <typename Clock, typename WaitTraits>
-class waitable_timer_service;
-
-#if defined(ASIO_HAS_BOOST_DATE_TIME)
-
-template <typename TimeType, typename TimeTraits>
-class deadline_timer_service;
-
-#endif // defined(ASIO_HAS_BOOST_DATE_TIME)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if !defined(ASIO_BASIC_WAITABLE_TIMER_FWD_DECL)
-#define ASIO_BASIC_WAITABLE_TIMER_FWD_DECL
-
-template <typename Clock,
-    typename WaitTraits = asio::wait_traits<Clock>
-    ASIO_SVC_TPARAM_DEF2(= waitable_timer_service<Clock, WaitTraits>)>
-class basic_waitable_timer;
-
-#endif // !defined(ASIO_BASIC_WAITABLE_TIMER_FWD_DECL)
-
-#if defined(ASIO_HAS_CHRONO)
-
-typedef basic_waitable_timer<chrono::system_clock> system_timer;
-
-typedef basic_waitable_timer<chrono::steady_clock> steady_timer;
-
-typedef basic_waitable_timer<chrono::high_resolution_clock>
-  high_resolution_timer;
-
-#endif // defined(ASIO_HAS_CHRONO)
-
-template <class Protocol ASIO_SVC_TPARAM>
-class basic_socket;
-
-template <typename Protocol ASIO_SVC_TPARAM>
-class basic_datagram_socket;
-
-template <typename Protocol ASIO_SVC_TPARAM>
-class basic_stream_socket;
-
-template <typename Protocol ASIO_SVC_TPARAM>
-class basic_socket_acceptor;
-
-#if !defined(ASIO_BASIC_SOCKET_STREAMBUF_FWD_DECL)
-#define ASIO_BASIC_SOCKET_STREAMBUF_FWD_DECL
-
-// Forward declaration with defaulted arguments.
-template <typename Protocol
-    ASIO_SVC_TPARAM_DEF1(= stream_socket_service<Protocol>),
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  || defined(GENERATING_DOCUMENTATION)
-    typename Clock = boost::posix_time::ptime,
-    typename WaitTraits = time_traits<Clock>
-    ASIO_SVC_TPARAM1_DEF2(= deadline_timer_service<Clock, WaitTraits>)>
-#else
-    typename Clock = chrono::steady_clock,
-    typename WaitTraits = wait_traits<Clock>
-    ASIO_SVC_TPARAM1_DEF1(= steady_timer::service_type)>
-#endif
-class basic_socket_streambuf;
-
-#endif // !defined(ASIO_BASIC_SOCKET_STREAMBUF_FWD_DECL)
-
-#if !defined(ASIO_BASIC_SOCKET_IOSTREAM_FWD_DECL)
-#define ASIO_BASIC_SOCKET_IOSTREAM_FWD_DECL
-
-// Forward declaration with defaulted arguments.
-template <typename Protocol
-    ASIO_SVC_TPARAM_DEF1(= stream_socket_service<Protocol>),
-#if defined(ASIO_HAS_BOOST_DATE_TIME) \
-  || defined(GENERATING_DOCUMENTATION)
-    typename Clock = boost::posix_time::ptime,
-    typename WaitTraits = time_traits<Clock>
-    ASIO_SVC_TPARAM1_DEF2(= deadline_timer_service<Clock, WaitTraits>)>
-#else
-    typename Clock = chrono::steady_clock,
-    typename WaitTraits = wait_traits<Clock>
-    ASIO_SVC_TPARAM1_DEF1(= steady_timer::service_type)>
-#endif
-class basic_socket_iostream;
-
-#endif // !defined(ASIO_BASIC_SOCKET_IOSTREAM_FWD_DECL)
-
-namespace ip {
-
-class address;
-
-class address_v4;
-
-class address_v6;
-
-template <typename Address>
-class basic_address_iterator;
-
-typedef basic_address_iterator<address_v4> address_v4_iterator;
-
-typedef basic_address_iterator<address_v6> address_v6_iterator;
-
-template <typename Address>
-class basic_address_range;
-
-typedef basic_address_range<address_v4> address_v4_range;
-
-typedef basic_address_range<address_v6> address_v6_range;
-
-class network_v4;
-
-class network_v6;
-
-template <typename InternetProtocol>
-class basic_endpoint;
-
-template <typename InternetProtocol>
-class basic_resolver_entry;
-
-template <typename InternetProtocol>
-class basic_resolver_results;
-
-template <typename InternetProtocol ASIO_SVC_TPARAM>
-class basic_resolver;
-
-class tcp;
-
-class udp;
-
-} // namespace ip
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // !defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_TS_NETFWD_HPP
diff --git a/tools/sdk/include/asio/asio/ts/socket.hpp b/tools/sdk/include/asio/asio/ts/socket.hpp
deleted file mode 100644
index a542734856e..00000000000
--- a/tools/sdk/include/asio/asio/ts/socket.hpp
+++ /dev/null
@@ -1,27 +0,0 @@
-//
-// ts/socket.hpp
-// ~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_TS_SOCKET_HPP
-#define ASIO_TS_SOCKET_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/socket_base.hpp"
-#include "asio/basic_socket.hpp"
-#include "asio/basic_datagram_socket.hpp"
-#include "asio/basic_stream_socket.hpp"
-#include "asio/basic_socket_acceptor.hpp"
-#include "asio/basic_socket_streambuf.hpp"
-#include "asio/basic_socket_iostream.hpp"
-#include "asio/connect.hpp"
-
-#endif // ASIO_TS_SOCKET_HPP
diff --git a/tools/sdk/include/asio/asio/ts/timer.hpp b/tools/sdk/include/asio/asio/ts/timer.hpp
deleted file mode 100644
index 872be8bfd70..00000000000
--- a/tools/sdk/include/asio/asio/ts/timer.hpp
+++ /dev/null
@@ -1,26 +0,0 @@
-//
-// ts/timer.hpp
-// ~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_TS_TIMER_HPP
-#define ASIO_TS_TIMER_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/chrono.hpp"
-
-#include "asio/wait_traits.hpp"
-#include "asio/basic_waitable_timer.hpp"
-#include "asio/system_timer.hpp"
-#include "asio/steady_timer.hpp"
-#include "asio/high_resolution_timer.hpp"
-
-#endif // ASIO_TS_TIMER_HPP
diff --git a/tools/sdk/include/asio/asio/unyield.hpp b/tools/sdk/include/asio/asio/unyield.hpp
deleted file mode 100644
index de3ed0275e4..00000000000
--- a/tools/sdk/include/asio/asio/unyield.hpp
+++ /dev/null
@@ -1,21 +0,0 @@
-//
-// unyield.hpp
-// ~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifdef reenter
-# undef reenter
-#endif
-
-#ifdef yield
-# undef yield
-#endif
-
-#ifdef fork
-# undef fork
-#endif
diff --git a/tools/sdk/include/asio/asio/use_future.hpp b/tools/sdk/include/asio/asio/use_future.hpp
deleted file mode 100644
index 3f9c6968790..00000000000
--- a/tools/sdk/include/asio/asio/use_future.hpp
+++ /dev/null
@@ -1,159 +0,0 @@
-//
-// use_future.hpp
-// ~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_USE_FUTURE_HPP
-#define ASIO_USE_FUTURE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_STD_FUTURE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <memory>
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace detail {
-
-template <typename Function, typename Allocator>
-class packaged_token;
-
-template <typename Function, typename Allocator, typename Result>
-class packaged_handler;
-
-} // namespace detail
-
-/// Class used to specify that an asynchronous operation should return a future.
-/**
- * The use_future_t class is used to indicate that an asynchronous operation
- * should return a std::future object. A use_future_t object may be passed as a
- * handler to an asynchronous operation, typically using the special value @c
- * asio::use_future. For example:
- *
- * @code std::future<std::size_t> my_future
- *   = my_socket.async_read_some(my_buffer, asio::use_future); @endcode
- *
- * The initiating function (async_read_some in the above example) returns a
- * future that will receive the result of the operation. If the operation
- * completes with an error_code indicating failure, it is converted into a
- * system_error and passed back to the caller via the future.
- */
-template <typename Allocator = std::allocator<void> >
-class use_future_t
-{
-public:
-  /// The allocator type. The allocator is used when constructing the
-  /// @c std::promise object for a given asynchronous operation.
-  typedef Allocator allocator_type;
-
-  /// Construct using default-constructed allocator.
-  ASIO_CONSTEXPR use_future_t()
-  {
-  }
-
-  /// Construct using specified allocator.
-  explicit use_future_t(const Allocator& allocator)
-    : allocator_(allocator)
-  {
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use rebind().) Specify an alternate allocator.
-  template <typename OtherAllocator>
-  use_future_t<OtherAllocator> operator[](const OtherAllocator& allocator) const
-  {
-    return use_future_t<OtherAllocator>(allocator);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Specify an alternate allocator.
-  template <typename OtherAllocator>
-  use_future_t<OtherAllocator> rebind(const OtherAllocator& allocator) const
-  {
-    return use_future_t<OtherAllocator>(allocator);
-  }
-
-  /// Obtain allocator.
-  allocator_type get_allocator() const
-  {
-    return allocator_;
-  }
-
-  /// Wrap a function object in a packaged task.
-  /**
-   * The @c package function is used to adapt a function object as a packaged
-   * task. When this adapter is passed as a completion token to an asynchronous
-   * operation, the result of the function object is retuned via a std::future.
-   *
-   * @par Example
-   *
-   * @code std::future<std::size_t> fut =
-   *   my_socket.async_read_some(buffer,
-   *     use_future([](asio::error_code ec, std::size_t n)
-   *       {
-   *         return ec ? 0 : n;
-   *       }));
-   * ...
-   * std::size_t n = fut.get(); @endcode
-   */
-  template <typename Function>
-#if defined(GENERATING_DOCUMENTATION)
-  unspecified
-#else // defined(GENERATING_DOCUMENTATION)
-  detail::packaged_token<typename decay<Function>::type, Allocator>
-#endif // defined(GENERATING_DOCUMENTATION)
-  operator()(ASIO_MOVE_ARG(Function) f) const;
-
-private:
-  // Helper type to ensure that use_future can be constexpr default-constructed
-  // even when std::allocator<void> can't be.
-  struct std_allocator_void
-  {
-    ASIO_CONSTEXPR std_allocator_void()
-    {
-    }
-
-    operator std::allocator<void>() const
-    {
-      return std::allocator<void>();
-    }
-  };
-
-  typename conditional<
-    is_same<std::allocator<void>, Allocator>::value,
-    std_allocator_void, Allocator>::type allocator_;
-};
-
-/// A special value, similar to std::nothrow.
-/**
- * See the documentation for asio::use_future_t for a usage example.
- */
-#if defined(ASIO_HAS_CONSTEXPR) || defined(GENERATING_DOCUMENTATION)
-constexpr use_future_t<> use_future;
-#elif defined(ASIO_MSVC)
-__declspec(selectany) use_future_t<> use_future;
-#endif
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/use_future.hpp"
-
-#endif // defined(ASIO_HAS_STD_FUTURE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_USE_FUTURE_HPP
diff --git a/tools/sdk/include/asio/asio/uses_executor.hpp b/tools/sdk/include/asio/asio/uses_executor.hpp
deleted file mode 100644
index e985c28245f..00000000000
--- a/tools/sdk/include/asio/asio/uses_executor.hpp
+++ /dev/null
@@ -1,71 +0,0 @@
-//
-// uses_executor.hpp
-// ~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_USES_EXECUTOR_HPP
-#define ASIO_USES_EXECUTOR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/detail/type_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// A special type, similar to std::nothrow_t, used to disambiguate
-/// constructors that accept executor arguments.
-/**
- * The executor_arg_t struct is an empty structure type used as a unique type
- * to disambiguate constructor and function overloading. Specifically, some
- * types have constructors with executor_arg_t as the first argument,
- * immediately followed by an argument of a type that satisfies the Executor
- * type requirements.
- */
-struct executor_arg_t
-{
-  /// Constructor.
-  ASIO_CONSTEXPR executor_arg_t() ASIO_NOEXCEPT
-  {
-  }
-};
-
-/// A special value, similar to std::nothrow, used to disambiguate constructors
-/// that accept executor arguments.
-/**
- * See asio::executor_arg_t and asio::uses_executor
- * for more information.
- */
-#if defined(ASIO_HAS_CONSTEXPR) || defined(GENERATING_DOCUMENTATION)
-constexpr executor_arg_t executor_arg;
-#elif defined(ASIO_MSVC)
-__declspec(selectany) executor_arg_t executor_arg;
-#endif
-
-/// The uses_executor trait detects whether a type T has an associated executor
-/// that is convertible from type Executor.
-/**
- * Meets the BinaryTypeTrait requirements. The Asio library provides a
- * definition that is derived from false_type. A program may specialize this
- * template to derive from true_type for a user-defined type T that can be
- * constructed with an executor, where the first argument of a constructor has
- * type executor_arg_t and the second argument is convertible from type
- * Executor.
- */
-template <typename T, typename Executor>
-struct uses_executor : false_type {};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_USES_EXECUTOR_HPP
diff --git a/tools/sdk/include/asio/asio/version.hpp b/tools/sdk/include/asio/asio/version.hpp
deleted file mode 100644
index ee0313f7366..00000000000
--- a/tools/sdk/include/asio/asio/version.hpp
+++ /dev/null
@@ -1,23 +0,0 @@
-//
-// version.hpp
-// ~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_VERSION_HPP
-#define ASIO_VERSION_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-// ASIO_VERSION % 100 is the sub-minor version
-// ASIO_VERSION / 100 % 1000 is the minor version
-// ASIO_VERSION / 100000 is the major version
-#define ASIO_VERSION 101200 // 1.12.0
-
-#endif // ASIO_VERSION_HPP
diff --git a/tools/sdk/include/asio/asio/wait_traits.hpp b/tools/sdk/include/asio/asio/wait_traits.hpp
deleted file mode 100644
index a6016f7c037..00000000000
--- a/tools/sdk/include/asio/asio/wait_traits.hpp
+++ /dev/null
@@ -1,56 +0,0 @@
-//
-// wait_traits.hpp
-// ~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WAIT_TRAITS_HPP
-#define ASIO_WAIT_TRAITS_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Wait traits suitable for use with the basic_waitable_timer class template.
-template <typename Clock>
-struct wait_traits
-{
-  /// Convert a clock duration into a duration used for waiting.
-  /**
-   * @returns @c d.
-   */
-  static typename Clock::duration to_wait_duration(
-      const typename Clock::duration& d)
-  {
-    return d;
-  }
-
-  /// Convert a clock duration into a duration used for waiting.
-  /**
-   * @returns @c d.
-   */
-  static typename Clock::duration to_wait_duration(
-      const typename Clock::time_point& t)
-  {
-    typename Clock::time_point now = Clock::now();
-    if (now + (Clock::duration::max)() < t)
-      return (Clock::duration::max)();
-    if (now + (Clock::duration::min)() > t)
-      return (Clock::duration::min)();
-    return t - now;
-  }
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // ASIO_WAIT_TRAITS_HPP
diff --git a/tools/sdk/include/asio/asio/waitable_timer_service.hpp b/tools/sdk/include/asio/asio/waitable_timer_service.hpp
deleted file mode 100644
index 75e496f8d28..00000000000
--- a/tools/sdk/include/asio/asio/waitable_timer_service.hpp
+++ /dev/null
@@ -1,210 +0,0 @@
-//
-// waitable_timer_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WAITABLE_TIMER_SERVICE_HPP
-#define ASIO_WAITABLE_TIMER_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/chrono_time_traits.hpp"
-#include "asio/detail/deadline_timer_service.hpp"
-#include "asio/io_context.hpp"
-#include "asio/wait_traits.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/// Default service implementation for a timer.
-template <typename Clock,
-    typename WaitTraits = asio::wait_traits<Clock> >
-class waitable_timer_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<
-      waitable_timer_service<Clock, WaitTraits> >
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-  /// The clock type.
-  typedef Clock clock_type;
-
-  /// The duration type of the clock.
-  typedef typename clock_type::duration duration;
-
-  /// The time point type of the clock.
-  typedef typename clock_type::time_point time_point;
-
-  /// The wait traits type.
-  typedef WaitTraits traits_type;
-
-private:
-  // The type of the platform-specific implementation.
-  typedef detail::deadline_timer_service<
-    detail::chrono_time_traits<Clock, WaitTraits> > service_impl_type;
-
-public:
-  /// The implementation type of the waitable timer.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef typename service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// Construct a new timer service for the specified io_context.
-  explicit waitable_timer_service(asio::io_context& io_context)
-    : asio::detail::service_base<
-        waitable_timer_service<Clock, WaitTraits> >(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new timer implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-  /// Destroy a timer implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new timer implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another timer implementation.
-  void move_assign(implementation_type& impl,
-      waitable_timer_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Cancel any asynchronous wait operations associated with the timer.
-  std::size_t cancel(implementation_type& impl, asio::error_code& ec)
-  {
-    return service_impl_.cancel(impl, ec);
-  }
-
-  /// Cancels one asynchronous wait operation associated with the timer.
-  std::size_t cancel_one(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    return service_impl_.cancel_one(impl, ec);
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use expiry().) Get the expiry time for the timer as an
-  /// absolute time.
-  time_point expires_at(const implementation_type& impl) const
-  {
-    return service_impl_.expiry(impl);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the expiry time for the timer as an absolute time.
-  time_point expiry(const implementation_type& impl) const
-  {
-    return service_impl_.expiry(impl);
-  }
-
-  /// Set the expiry time for the timer as an absolute time.
-  std::size_t expires_at(implementation_type& impl,
-      const time_point& expiry_time, asio::error_code& ec)
-  {
-    return service_impl_.expires_at(impl, expiry_time, ec);
-  }
-
-  /// Set the expiry time for the timer relative to now.
-  std::size_t expires_after(implementation_type& impl,
-      const duration& expiry_time, asio::error_code& ec)
-  {
-    return service_impl_.expires_after(impl, expiry_time, ec);
-  }
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use expiry().) Get the expiry time for the timer relative to
-  /// now.
-  duration expires_from_now(const implementation_type& impl) const
-  {
-    typedef detail::chrono_time_traits<Clock, WaitTraits> traits;
-    return traits::subtract(service_impl_.expiry(impl), traits::now());
-  }
-
-  /// (Deprecated: Use expires_after().) Set the expiry time for the timer
-  /// relative to now.
-  std::size_t expires_from_now(implementation_type& impl,
-      const duration& expiry_time, asio::error_code& ec)
-  {
-    return service_impl_.expires_after(impl, expiry_time, ec);
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  // Perform a blocking wait on the timer.
-  void wait(implementation_type& impl, asio::error_code& ec)
-  {
-    service_impl_.wait(impl, ec);
-  }
-
-  // Start an asynchronous wait on the timer.
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(implementation_type& impl,
-      ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_wait(impl, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_WAITABLE_TIMER_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/basic_handle.hpp b/tools/sdk/include/asio/asio/windows/basic_handle.hpp
deleted file mode 100644
index f7c9d0d0368..00000000000
--- a/tools/sdk/include/asio/asio/windows/basic_handle.hpp
+++ /dev/null
@@ -1,273 +0,0 @@
-//
-// windows/basic_handle.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_BASIC_HANDLE_HPP
-#define ASIO_WINDOWS_BASIC_HANDLE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE) \
-  || defined(ASIO_HAS_WINDOWS_STREAM_HANDLE) \
-  || defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-/// Provides Windows handle functionality.
-/**
- * The windows::basic_handle class template provides the ability to wrap a
- * Windows handle.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename HandleService>
-class basic_handle
-  : public basic_io_object<HandleService>
-{
-public:
-  /// The native representation of a handle.
-  typedef typename HandleService::native_handle_type native_handle_type;
-
-  /// A basic_handle is always the lowest layer.
-  typedef basic_handle<HandleService> lowest_layer_type;
-
-  /// Construct a basic_handle without opening it.
-  /**
-   * This constructor creates a handle without opening it.
-   *
-   * @param io_context The io_context object that the handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   */
-  explicit basic_handle(asio::io_context& io_context)
-    : basic_io_object<HandleService>(io_context)
-  {
-  }
-
-  /// Construct a basic_handle on an existing native handle.
-  /**
-   * This constructor creates a handle object to hold an existing native handle.
-   *
-   * @param io_context The io_context object that the handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   *
-   * @param handle A native handle.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_handle(asio::io_context& io_context,
-      const native_handle_type& handle)
-    : basic_io_object<HandleService>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(), handle, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_handle from another.
-  /**
-   * This constructor moves a handle from one object to another.
-   *
-   * @param other The other basic_handle object from which the move will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_handle(io_context&) constructor.
-   */
-  basic_handle(basic_handle&& other)
-    : basic_io_object<HandleService>(
-        ASIO_MOVE_CAST(basic_handle)(other))
-  {
-  }
-
-  /// Move-assign a basic_handle from another.
-  /**
-   * This assignment operator moves a handle from one object to another.
-   *
-   * @param other The other basic_handle object from which the move will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_handle(io_context&) constructor.
-   */
-  basic_handle& operator=(basic_handle&& other)
-  {
-    basic_io_object<HandleService>::operator=(
-        ASIO_MOVE_CAST(basic_handle)(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * layers. Since a basic_handle cannot contain any further layers, it simply
-   * returns a reference to itself.
-   *
-   * @return A reference to the lowest layer in the stack of layers. Ownership
-   * is not transferred to the caller.
-   */
-  lowest_layer_type& lowest_layer()
-  {
-    return *this;
-  }
-
-  /// Get a const reference to the lowest layer.
-  /**
-   * This function returns a const reference to the lowest layer in a stack of
-   * layers. Since a basic_handle cannot contain any further layers, it simply
-   * returns a reference to itself.
-   *
-   * @return A const reference to the lowest layer in the stack of layers.
-   * Ownership is not transferred to the caller.
-   */
-  const lowest_layer_type& lowest_layer() const
-  {
-    return *this;
-  }
-
-  /// Assign an existing native handle to the handle.
-  /*
-   * This function opens the handle to hold an existing native handle.
-   *
-   * @param handle A native handle.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void assign(const native_handle_type& handle)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(), handle, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-  /// Assign an existing native handle to the handle.
-  /*
-   * This function opens the handle to hold an existing native handle.
-   *
-   * @param handle A native handle.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID assign(const native_handle_type& handle,
-      asio::error_code& ec)
-  {
-    this->get_service().assign(this->get_implementation(), handle, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the handle is open.
-  bool is_open() const
-  {
-    return this->get_service().is_open(this->get_implementation());
-  }
-
-  /// Close the handle.
-  /**
-   * This function is used to close the handle. Any asynchronous read or write
-   * operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void close()
-  {
-    asio::error_code ec;
-    this->get_service().close(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "close");
-  }
-
-  /// Close the handle.
-  /**
-   * This function is used to close the handle. Any asynchronous read or write
-   * operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    this->get_service().close(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native handle representation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * handle. This is intended to allow access to native handle functionality
-   * that is not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return this->get_service().native_handle(this->get_implementation());
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  ~basic_handle()
-  {
-  }
-};
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE)
-       //   || defined(ASIO_HAS_WINDOWS_STREAM_HANDLE)
-       //   || defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_WINDOWS_BASIC_HANDLE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/basic_object_handle.hpp b/tools/sdk/include/asio/asio/windows/basic_object_handle.hpp
deleted file mode 100644
index 4b2968460b7..00000000000
--- a/tools/sdk/include/asio/asio/windows/basic_object_handle.hpp
+++ /dev/null
@@ -1,182 +0,0 @@
-//
-// windows/basic_object_handle.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2011 Boris Schaeling (boris@highscore.de)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_BASIC_OBJECT_HANDLE_HPP
-#define ASIO_WINDOWS_BASIC_OBJECT_HANDLE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/windows/basic_handle.hpp"
-#include "asio/windows/object_handle_service.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-/// Provides object-oriented handle functionality.
-/**
- * The windows::basic_object_handle class template provides asynchronous and
- * blocking object-oriented handle functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename ObjectHandleService = object_handle_service>
-class basic_object_handle
-  : public basic_handle<ObjectHandleService>
-{
-public:
-  /// The native representation of a handle.
-  typedef typename ObjectHandleService::native_handle_type native_handle_type;
-
-  /// Construct a basic_object_handle without opening it.
-  /**
-   * This constructor creates an object handle without opening it.
-   *
-   * @param io_context The io_context object that the object handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   */
-  explicit basic_object_handle(asio::io_context& io_context)
-    : basic_handle<ObjectHandleService>(io_context)
-  {
-  }
-
-  /// Construct a basic_object_handle on an existing native handle.
-  /**
-   * This constructor creates an object handle object to hold an existing native
-   * handle.
-   *
-   * @param io_context The io_context object that the object handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   *
-   * @param native_handle The new underlying handle implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_object_handle(asio::io_context& io_context,
-      const native_handle_type& native_handle)
-    : basic_handle<ObjectHandleService>(io_context, native_handle)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_object_handle from another.
-  /**
-   * This constructor moves an object handle from one object to another.
-   *
-   * @param other The other basic_object_handle object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_object_handle(io_context&) constructor.
-   */
-  basic_object_handle(basic_object_handle&& other)
-    : basic_handle<ObjectHandleService>(
-        ASIO_MOVE_CAST(basic_object_handle)(other))
-  {
-  }
-
-  /// Move-assign a basic_object_handle from another.
-  /**
-   * This assignment operator moves an object handle from one object to another.
-   *
-   * @param other The other basic_object_handle object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_object_handle(io_context&) constructor.
-   */
-  basic_object_handle& operator=(basic_object_handle&& other)
-  {
-    basic_handle<ObjectHandleService>::operator=(
-        ASIO_MOVE_CAST(basic_object_handle)(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Perform a blocking wait on the object handle.
-  /**
-   * This function is used to wait for the object handle to be set to the
-   * signalled state. This function blocks and does not return until the object
-   * handle has been set to the signalled state.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void wait()
-  {
-    asio::error_code ec;
-    this->get_service().wait(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "wait");
-  }
-
-  /// Perform a blocking wait on the object handle.
-  /**
-   * This function is used to wait for the object handle to be set to the
-   * signalled state. This function blocks and does not return until the object
-   * handle has been set to the signalled state.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  void wait(asio::error_code& ec)
-  {
-    this->get_service().wait(this->get_implementation(), ec);
-  }
-
-  /// Start an asynchronous wait on the object handle.
-  /**
-   * This function is be used to initiate an asynchronous wait against the
-   * object handle. It always returns immediately.
-   *
-   * @param handler The handler to be called when the object handle is set to
-   * the signalled state. Copies will be made of the handler as required. The
-   * function signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    return this->get_service().async_wait(this->get_implementation(),
-        ASIO_MOVE_CAST(WaitHandler)(handler));
-  }
-};
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_WINDOWS_BASIC_OBJECT_HANDLE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/basic_random_access_handle.hpp b/tools/sdk/include/asio/asio/windows/basic_random_access_handle.hpp
deleted file mode 100644
index 4226977315e..00000000000
--- a/tools/sdk/include/asio/asio/windows/basic_random_access_handle.hpp
+++ /dev/null
@@ -1,376 +0,0 @@
-//
-// windows/basic_random_access_handle.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_BASIC_RANDOM_ACCESS_HANDLE_HPP
-#define ASIO_WINDOWS_BASIC_RANDOM_ACCESS_HANDLE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/windows/basic_handle.hpp"
-#include "asio/windows/random_access_handle_service.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-/// Provides random-access handle functionality.
-/**
- * The windows::basic_random_access_handle class template provides asynchronous
- * and blocking random-access handle functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-template <typename RandomAccessHandleService = random_access_handle_service>
-class basic_random_access_handle
-  : public basic_handle<RandomAccessHandleService>
-{
-public:
-  /// The native representation of a handle.
-  typedef typename RandomAccessHandleService::native_handle_type
-    native_handle_type;
-
-  /// Construct a basic_random_access_handle without opening it.
-  /**
-   * This constructor creates a random-access handle without opening it. The
-   * handle needs to be opened before data can be written to or read from it.
-   *
-   * @param io_context The io_context object that the random-access handle will
-   * use to dispatch handlers for any asynchronous operations performed on the
-   * handle.
-   */
-  explicit basic_random_access_handle(asio::io_context& io_context)
-    : basic_handle<RandomAccessHandleService>(io_context)
-  {
-  }
-
-  /// Construct a basic_random_access_handle on an existing native handle.
-  /**
-   * This constructor creates a random-access handle object to hold an existing
-   * native handle.
-   *
-   * @param io_context The io_context object that the random-access handle will
-   * use to dispatch handlers for any asynchronous operations performed on the
-   * handle.
-   *
-   * @param handle The new underlying handle implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_random_access_handle(asio::io_context& io_context,
-      const native_handle_type& handle)
-    : basic_handle<RandomAccessHandleService>(io_context, handle)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_random_access_handle from another.
-  /**
-   * This constructor moves a random-access handle from one object to another.
-   *
-   * @param other The other basic_random_access_handle object from which the
-   * move will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_random_access_handle(io_context&)
-   * constructor.
-   */
-  basic_random_access_handle(basic_random_access_handle&& other)
-    : basic_handle<RandomAccessHandleService>(
-        ASIO_MOVE_CAST(basic_random_access_handle)(other))
-  {
-  }
-
-  /// Move-assign a basic_random_access_handle from another.
-  /**
-   * This assignment operator moves a random-access handle from one object to
-   * another.
-   *
-   * @param other The other basic_random_access_handle object from which the
-   * move will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_random_access_handle(io_context&)
-   * constructor.
-   */
-  basic_random_access_handle& operator=(basic_random_access_handle&& other)
-  {
-    basic_handle<RandomAccessHandleService>::operator=(
-        ASIO_MOVE_CAST(basic_random_access_handle)(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Write some data to the handle at the specified offset.
-  /**
-   * This function is used to write data to the random-access handle. The
-   * function call will block until one or more bytes of the data has been
-   * written successfully, or until an error occurs.
-   *
-   * @param offset The offset at which the data will be written.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The write_some_at operation may not write all of the data. Consider
-   * using the @ref write_at function if you need to ensure that all data is
-   * written before the blocking operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.write_some_at(42, asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some_at(uint64_t offset,
-      const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().write_some_at(
-        this->get_implementation(), offset, buffers, ec);
-    asio::detail::throw_error(ec, "write_some_at");
-    return s;
-  }
-
-  /// Write some data to the handle at the specified offset.
-  /**
-   * This function is used to write data to the random-access handle. The
-   * function call will block until one or more bytes of the data has been
-   * written successfully, or until an error occurs.
-   *
-   * @param offset The offset at which the data will be written.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write_at function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some_at(uint64_t offset,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    return this->get_service().write_some_at(
-        this->get_implementation(), offset, buffers, ec);
-  }
-
-  /// Start an asynchronous write at the specified offset.
-  /**
-   * This function is used to asynchronously write data to the random-access
-   * handle. The function call always returns immediately.
-   *
-   * @param offset The offset at which the data will be written.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The write operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write_at function if you need to ensure that
-   * all data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.async_write_some_at(42, asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some_at(uint64_t offset,
-      const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-    return this->get_service().async_write_some_at(this->get_implementation(),
-        offset, buffers, ASIO_MOVE_CAST(WriteHandler)(handler));
-  }
-
-  /// Read some data from the handle at the specified offset.
-  /**
-   * This function is used to read data from the random-access handle. The
-   * function call will block until one or more bytes of data has been read
-   * successfully, or until an error occurs.
-   *
-   * @param offset The offset at which the data will be read.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read_at function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.read_some_at(42, asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some_at(uint64_t offset,
-      const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().read_some_at(
-        this->get_implementation(), offset, buffers, ec);
-    asio::detail::throw_error(ec, "read_some_at");
-    return s;
-  }
-
-  /// Read some data from the handle at the specified offset.
-  /**
-   * This function is used to read data from the random-access handle. The
-   * function call will block until one or more bytes of data has been read
-   * successfully, or until an error occurs.
-   *
-   * @param offset The offset at which the data will be read.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read_at function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some_at(uint64_t offset,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    return this->get_service().read_some_at(
-        this->get_implementation(), offset, buffers, ec);
-  }
-
-  /// Start an asynchronous read at the specified offset.
-  /**
-   * This function is used to asynchronously read data from the random-access
-   * handle. The function call always returns immediately.
-   *
-   * @param offset The offset at which the data will be read.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The read operation may not read all of the requested number of bytes.
-   * Consider using the @ref async_read_at function if you need to ensure that
-   * the requested amount of data is read before the asynchronous operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.async_read_some_at(42, asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some_at(uint64_t offset,
-      const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-    return this->get_service().async_read_some_at(this->get_implementation(),
-        offset, buffers, ASIO_MOVE_CAST(ReadHandler)(handler));
-  }
-};
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_WINDOWS_BASIC_RANDOM_ACCESS_HANDLE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/basic_stream_handle.hpp b/tools/sdk/include/asio/asio/windows/basic_stream_handle.hpp
deleted file mode 100644
index 3bfce6884f0..00000000000
--- a/tools/sdk/include/asio/asio/windows/basic_stream_handle.hpp
+++ /dev/null
@@ -1,359 +0,0 @@
-//
-// windows/basic_stream_handle.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_BASIC_STREAM_HANDLE_HPP
-#define ASIO_WINDOWS_BASIC_STREAM_HANDLE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_WINDOWS_STREAM_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include "asio/detail/handler_type_requirements.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/error.hpp"
-#include "asio/windows/basic_handle.hpp"
-#include "asio/windows/stream_handle_service.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-/// Provides stream-oriented handle functionality.
-/**
- * The windows::basic_stream_handle class template provides asynchronous and
- * blocking stream-oriented handle functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * AsyncReadStream, AsyncWriteStream, Stream, SyncReadStream, SyncWriteStream.
- */
-template <typename StreamHandleService = stream_handle_service>
-class basic_stream_handle
-  : public basic_handle<StreamHandleService>
-{
-public:
-  /// The native representation of a handle.
-  typedef typename StreamHandleService::native_handle_type native_handle_type;
-
-  /// Construct a basic_stream_handle without opening it.
-  /**
-   * This constructor creates a stream handle without opening it. The handle
-   * needs to be opened and then connected or accepted before data can be sent
-   * or received on it.
-   *
-   * @param io_context The io_context object that the stream handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   */
-  explicit basic_stream_handle(asio::io_context& io_context)
-    : basic_handle<StreamHandleService>(io_context)
-  {
-  }
-
-  /// Construct a basic_stream_handle on an existing native handle.
-  /**
-   * This constructor creates a stream handle object to hold an existing native
-   * handle.
-   *
-   * @param io_context The io_context object that the stream handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   *
-   * @param handle The new underlying handle implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  basic_stream_handle(asio::io_context& io_context,
-      const native_handle_type& handle)
-    : basic_handle<StreamHandleService>(io_context, handle)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a basic_stream_handle from another.
-  /**
-   * This constructor moves a stream handle from one object to another.
-   *
-   * @param other The other basic_stream_handle object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_stream_handle(io_context&) constructor.
-   */
-  basic_stream_handle(basic_stream_handle&& other)
-    : basic_handle<StreamHandleService>(
-        ASIO_MOVE_CAST(basic_stream_handle)(other))
-  {
-  }
-
-  /// Move-assign a basic_stream_handle from another.
-  /**
-   * This assignment operator moves a stream handle from one object to
-   * another.
-   *
-   * @param other The other basic_stream_handle object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c basic_stream_handle(io_context&) constructor.
-   */
-  basic_stream_handle& operator=(basic_stream_handle&& other)
-  {
-    basic_handle<StreamHandleService>::operator=(
-        ASIO_MOVE_CAST(basic_stream_handle)(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Write some data to the handle.
-  /**
-   * This function is used to write data to the stream handle. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.write_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "write_some");
-    return s;
-  }
-
-  /// Write some data to the handle.
-  /**
-   * This function is used to write data to the stream handle. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous write.
-  /**
-   * This function is used to asynchronously write data to the stream handle.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The write operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write function if you need to ensure that all
-   * data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.async_write_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-    return this->get_service().async_write_some(this->get_implementation(),
-        buffers, ASIO_MOVE_CAST(WriteHandler)(handler));
-  }
-
-  /// Read some data from the handle.
-  /**
-   * This function is used to read data from the stream handle. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.read_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "read_some");
-    return s;
-  }
-
-  /// Read some data from the handle.
-  /**
-   * This function is used to read data from the stream handle. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous read.
-  /**
-   * This function is used to asynchronously read data from the stream handle.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The read operation may not read all of the requested number of bytes.
-   * Consider using the @ref async_read function if you need to ensure that the
-   * requested amount of data is read before the asynchronous operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.async_read_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-    return this->get_service().async_read_some(this->get_implementation(),
-        buffers, ASIO_MOVE_CAST(ReadHandler)(handler));
-  }
-};
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_STREAM_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_WINDOWS_BASIC_STREAM_HANDLE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/object_handle.hpp b/tools/sdk/include/asio/asio/windows/object_handle.hpp
deleted file mode 100644
index 581b5680011..00000000000
--- a/tools/sdk/include/asio/asio/windows/object_handle.hpp
+++ /dev/null
@@ -1,381 +0,0 @@
-//
-// windows/object_handle.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2011 Boris Schaeling (boris@highscore.de)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_OBJECT_HANDLE_HPP
-#define ASIO_WINDOWS_OBJECT_HANDLE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/async_result.hpp"
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/detail/win_object_handle_service.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_HAS_MOVE)
-# include <utility>
-#endif // defined(ASIO_HAS_MOVE)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/windows/basic_object_handle.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#define ASIO_SVC_T asio::detail::win_object_handle_service
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-// Typedef for the typical usage of an object handle.
-typedef basic_object_handle<> object_handle;
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-/// Provides object-oriented handle functionality.
-/**
- * The windows::object_handle class provides asynchronous and blocking
- * object-oriented handle functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class object_handle
-  : ASIO_SVC_ACCESS basic_io_object<ASIO_SVC_T>
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// The native representation of a handle.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef ASIO_SVC_T::native_handle_type native_handle_type;
-#endif
-
-  /// An object_handle is always the lowest layer.
-  typedef object_handle lowest_layer_type;
-
-  /// Construct an object_handle without opening it.
-  /**
-   * This constructor creates an object handle without opening it.
-   *
-   * @param io_context The io_context object that the object handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   */
-  explicit object_handle(asio::io_context& io_context)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-  }
-
-  /// Construct an object_handle on an existing native handle.
-  /**
-   * This constructor creates an object handle object to hold an existing native
-   * handle.
-   *
-   * @param io_context The io_context object that the object handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   *
-   * @param native_handle The new underlying handle implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  object_handle(asio::io_context& io_context,
-      const native_handle_type& native_handle)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(), native_handle, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct an object_handle from another.
-  /**
-   * This constructor moves an object handle from one object to another.
-   *
-   * @param other The other object_handle object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c object_handle(io_context&) constructor.
-   */
-  object_handle(object_handle&& other)
-    : basic_io_object<ASIO_SVC_T>(std::move(other))
-  {
-  }
-
-  /// Move-assign an object_handle from another.
-  /**
-   * This assignment operator moves an object handle from one object to another.
-   *
-   * @param other The other object_handle object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c object_handle(io_context&) constructor.
-   */
-  object_handle& operator=(object_handle&& other)
-  {
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<ASIO_SVC_T>::get_executor();
-  }
-
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * layers. Since an object_handle cannot contain any further layers, it simply
-   * returns a reference to itself.
-   *
-   * @return A reference to the lowest layer in the stack of layers. Ownership
-   * is not transferred to the caller.
-   */
-  lowest_layer_type& lowest_layer()
-  {
-    return *this;
-  }
-
-  /// Get a const reference to the lowest layer.
-  /**
-   * This function returns a const reference to the lowest layer in a stack of
-   * layers. Since an object_handle cannot contain any further layers, it simply
-   * returns a reference to itself.
-   *
-   * @return A const reference to the lowest layer in the stack of layers.
-   * Ownership is not transferred to the caller.
-   */
-  const lowest_layer_type& lowest_layer() const
-  {
-    return *this;
-  }
-
-  /// Assign an existing native handle to the handle.
-  /*
-   * This function opens the handle to hold an existing native handle.
-   *
-   * @param handle A native handle.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void assign(const native_handle_type& handle)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(), handle, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-  /// Assign an existing native handle to the handle.
-  /*
-   * This function opens the handle to hold an existing native handle.
-   *
-   * @param handle A native handle.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID assign(const native_handle_type& handle,
-      asio::error_code& ec)
-  {
-    this->get_service().assign(this->get_implementation(), handle, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the handle is open.
-  bool is_open() const
-  {
-    return this->get_service().is_open(this->get_implementation());
-  }
-
-  /// Close the handle.
-  /**
-   * This function is used to close the handle. Any asynchronous read or write
-   * operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void close()
-  {
-    asio::error_code ec;
-    this->get_service().close(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "close");
-  }
-
-  /// Close the handle.
-  /**
-   * This function is used to close the handle. Any asynchronous read or write
-   * operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    this->get_service().close(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native handle representation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * handle. This is intended to allow access to native handle functionality
-   * that is not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return this->get_service().native_handle(this->get_implementation());
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Perform a blocking wait on the object handle.
-  /**
-   * This function is used to wait for the object handle to be set to the
-   * signalled state. This function blocks and does not return until the object
-   * handle has been set to the signalled state.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void wait()
-  {
-    asio::error_code ec;
-    this->get_service().wait(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "wait");
-  }
-
-  /// Perform a blocking wait on the object handle.
-  /**
-   * This function is used to wait for the object handle to be set to the
-   * signalled state. This function blocks and does not return until the object
-   * handle has been set to the signalled state.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  void wait(asio::error_code& ec)
-  {
-    this->get_service().wait(this->get_implementation(), ec);
-  }
-
-  /// Start an asynchronous wait on the object handle.
-  /**
-   * This function is be used to initiate an asynchronous wait against the
-   * object handle. It always returns immediately.
-   *
-   * @param handler The handler to be called when the object handle is set to
-   * the signalled state. Copies will be made of the handler as required. The
-   * function signature of the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error // Result of operation.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   */
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    asio::async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    this->get_service().async_wait(this->get_implementation(),
-        init.completion_handler);
-
-    return init.result.get();
-  }
-};
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#undef ASIO_SVC_T
-
-#endif // defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_WINDOWS_OBJECT_HANDLE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/object_handle_service.hpp b/tools/sdk/include/asio/asio/windows/object_handle_service.hpp
deleted file mode 100644
index 95436d790e0..00000000000
--- a/tools/sdk/include/asio/asio/windows/object_handle_service.hpp
+++ /dev/null
@@ -1,183 +0,0 @@
-//
-// windows/object_handle_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-// Copyright (c) 2011 Boris Schaeling (boris@highscore.de)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_OBJECT_HANDLE_SERVICE_HPP
-#define ASIO_WINDOWS_OBJECT_HANDLE_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/async_result.hpp"
-#include "asio/detail/win_object_handle_service.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-/// Default service implementation for an object handle.
-class object_handle_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<object_handle_service>
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-private:
-  // The type of the platform-specific implementation.
-  typedef detail::win_object_handle_service service_impl_type;
-
-public:
-  /// The type of an object handle implementation.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native handle type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new object handle service for the specified io_context.
-  explicit object_handle_service(asio::io_context& io_context)
-    : asio::detail::service_base<object_handle_service>(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new object handle implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new object handle implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another object handle implementation.
-  void move_assign(implementation_type& impl,
-      object_handle_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy an object handle implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Assign an existing native handle to an object handle.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const native_handle_type& handle, asio::error_code& ec)
-  {
-    service_impl_.assign(impl, handle, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the handle is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Close an object handle implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native handle implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  // Wait for a signaled state.
-  void wait(implementation_type& impl, asio::error_code& ec)
-  {
-    service_impl_.wait(impl, ec);
-  }
-
-  /// Start an asynchronous wait.
-  template <typename WaitHandler>
-  ASIO_INITFN_RESULT_TYPE(WaitHandler,
-      void (asio::error_code))
-  async_wait(implementation_type& impl,
-      ASIO_MOVE_ARG(WaitHandler) handler)
-  {
-    asio::async_completion<WaitHandler,
-      void (asio::error_code)> init(handler);
-
-    service_impl_.async_wait(impl, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_OBJECT_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_WINDOWS_OBJECT_HANDLE_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/overlapped_handle.hpp b/tools/sdk/include/asio/asio/windows/overlapped_handle.hpp
deleted file mode 100644
index 3d479ba6c82..00000000000
--- a/tools/sdk/include/asio/asio/windows/overlapped_handle.hpp
+++ /dev/null
@@ -1,331 +0,0 @@
-//
-// windows/overlapped_handle.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_OVERLAPPED_HANDLE_HPP
-#define ASIO_WINDOWS_OVERLAPPED_HANDLE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE) \
-  || defined(ASIO_HAS_WINDOWS_STREAM_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/basic_io_object.hpp"
-#include "asio/detail/throw_error.hpp"
-#include "asio/detail/win_iocp_handle_service.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#if defined(ASIO_HAS_MOVE)
-# include <utility>
-#endif // defined(ASIO_HAS_MOVE)
-
-#define ASIO_SVC_T asio::detail::win_iocp_handle_service
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-/// Provides Windows handle functionality for objects that support
-/// overlapped I/O.
-/**
- * The windows::overlapped_handle class provides the ability to wrap a Windows
- * handle. The underlying object referred to by the handle must support
- * overlapped I/O.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class overlapped_handle
-  : ASIO_SVC_ACCESS basic_io_object<ASIO_SVC_T>
-{
-public:
-  /// The type of the executor associated with the object.
-  typedef io_context::executor_type executor_type;
-
-  /// The native representation of a handle.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef ASIO_SVC_T::native_handle_type native_handle_type;
-#endif
-
-  /// An overlapped_handle is always the lowest layer.
-  typedef overlapped_handle lowest_layer_type;
-
-  /// Construct an overlapped_handle without opening it.
-  /**
-   * This constructor creates a handle without opening it.
-   *
-   * @param io_context The io_context object that the handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   */
-  explicit overlapped_handle(asio::io_context& io_context)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-  }
-
-  /// Construct an overlapped_handle on an existing native handle.
-  /**
-   * This constructor creates a handle object to hold an existing native handle.
-   *
-   * @param io_context The io_context object that the handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   *
-   * @param handle A native handle.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  overlapped_handle(asio::io_context& io_context,
-      const native_handle_type& handle)
-    : basic_io_object<ASIO_SVC_T>(io_context)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(), handle, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct an overlapped_handle from another.
-  /**
-   * This constructor moves a handle from one object to another.
-   *
-   * @param other The other overlapped_handle object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c overlapped_handle(io_context&) constructor.
-   */
-  overlapped_handle(overlapped_handle&& other)
-    : basic_io_object<ASIO_SVC_T>(std::move(other))
-  {
-  }
-
-  /// Move-assign an overlapped_handle from another.
-  /**
-   * This assignment operator moves a handle from one object to another.
-   *
-   * @param other The other overlapped_handle object from which the move will
-   * occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c overlapped_handle(io_context&) constructor.
-   */
-  overlapped_handle& operator=(overlapped_handle&& other)
-  {
-    basic_io_object<ASIO_SVC_T>::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-#if !defined(ASIO_NO_DEPRECATED)
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_context()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_context();
-  }
-
-  /// (Deprecated: Use get_executor().) Get the io_context associated with the
-  /// object.
-  /**
-   * This function may be used to obtain the io_context object that the I/O
-   * object uses to dispatch handlers for asynchronous operations.
-   *
-   * @return A reference to the io_context object that the I/O object will use
-   * to dispatch handlers. Ownership is not transferred to the caller.
-   */
-  asio::io_context& get_io_service()
-  {
-    return basic_io_object<ASIO_SVC_T>::get_io_service();
-  }
-#endif // !defined(ASIO_NO_DEPRECATED)
-
-  /// Get the executor associated with the object.
-  executor_type get_executor() ASIO_NOEXCEPT
-  {
-    return basic_io_object<ASIO_SVC_T>::get_executor();
-  }
-
-  /// Get a reference to the lowest layer.
-  /**
-   * This function returns a reference to the lowest layer in a stack of
-   * layers. Since an overlapped_handle cannot contain any further layers, it
-   * simply returns a reference to itself.
-   *
-   * @return A reference to the lowest layer in the stack of layers. Ownership
-   * is not transferred to the caller.
-   */
-  lowest_layer_type& lowest_layer()
-  {
-    return *this;
-  }
-
-  /// Get a const reference to the lowest layer.
-  /**
-   * This function returns a const reference to the lowest layer in a stack of
-   * layers. Since an overlapped_handle cannot contain any further layers, it
-   * simply returns a reference to itself.
-   *
-   * @return A const reference to the lowest layer in the stack of layers.
-   * Ownership is not transferred to the caller.
-   */
-  const lowest_layer_type& lowest_layer() const
-  {
-    return *this;
-  }
-
-  /// Assign an existing native handle to the handle.
-  /*
-   * This function opens the handle to hold an existing native handle.
-   *
-   * @param handle A native handle.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void assign(const native_handle_type& handle)
-  {
-    asio::error_code ec;
-    this->get_service().assign(this->get_implementation(), handle, ec);
-    asio::detail::throw_error(ec, "assign");
-  }
-
-  /// Assign an existing native handle to the handle.
-  /*
-   * This function opens the handle to hold an existing native handle.
-   *
-   * @param handle A native handle.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID assign(const native_handle_type& handle,
-      asio::error_code& ec)
-  {
-    this->get_service().assign(this->get_implementation(), handle, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the handle is open.
-  bool is_open() const
-  {
-    return this->get_service().is_open(this->get_implementation());
-  }
-
-  /// Close the handle.
-  /**
-   * This function is used to close the handle. Any asynchronous read or write
-   * operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void close()
-  {
-    asio::error_code ec;
-    this->get_service().close(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "close");
-  }
-
-  /// Close the handle.
-  /**
-   * This function is used to close the handle. Any asynchronous read or write
-   * operations will be cancelled immediately, and will complete with the
-   * asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID close(asio::error_code& ec)
-  {
-    this->get_service().close(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native handle representation.
-  /**
-   * This function may be used to obtain the underlying representation of the
-   * handle. This is intended to allow access to native handle functionality
-   * that is not otherwise provided.
-   */
-  native_handle_type native_handle()
-  {
-    return this->get_service().native_handle(this->get_implementation());
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  void cancel()
-  {
-    asio::error_code ec;
-    this->get_service().cancel(this->get_implementation(), ec);
-    asio::detail::throw_error(ec, "cancel");
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  /**
-   * This function causes all outstanding asynchronous read or write operations
-   * to finish immediately, and the handlers for cancelled operations will be
-   * passed the asio::error::operation_aborted error.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   */
-  ASIO_SYNC_OP_VOID cancel(asio::error_code& ec)
-  {
-    this->get_service().cancel(this->get_implementation(), ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-protected:
-  /// Protected destructor to prevent deletion through this type.
-  /**
-   * This function destroys the handle, cancelling any outstanding asynchronous
-   * wait operations associated with the handle as if by calling @c cancel.
-   */
-  ~overlapped_handle()
-  {
-  }
-};
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#undef ASIO_SVC_T
-
-#endif // defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE)
-       //   || defined(ASIO_HAS_WINDOWS_STREAM_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // !defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_WINDOWS_OVERLAPPED_HANDLE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/overlapped_ptr.hpp b/tools/sdk/include/asio/asio/windows/overlapped_ptr.hpp
deleted file mode 100644
index ce0b2a42d22..00000000000
--- a/tools/sdk/include/asio/asio/windows/overlapped_ptr.hpp
+++ /dev/null
@@ -1,116 +0,0 @@
-//
-// windows/overlapped_ptr.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_OVERLAPPED_PTR_HPP
-#define ASIO_WINDOWS_OVERLAPPED_PTR_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_HAS_WINDOWS_OVERLAPPED_PTR) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include "asio/detail/noncopyable.hpp"
-#include "asio/detail/win_iocp_overlapped_ptr.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-/// Wraps a handler to create an OVERLAPPED object for use with overlapped I/O.
-/**
- * A special-purpose smart pointer used to wrap an application handler so that
- * it can be passed as the LPOVERLAPPED argument to overlapped I/O functions.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class overlapped_ptr
-  : private noncopyable
-{
-public:
-  /// Construct an empty overlapped_ptr.
-  overlapped_ptr()
-    : impl_()
-  {
-  }
-
-  /// Construct an overlapped_ptr to contain the specified handler.
-  template <typename Handler>
-  explicit overlapped_ptr(asio::io_context& io_context,
-      ASIO_MOVE_ARG(Handler) handler)
-    : impl_(io_context, ASIO_MOVE_CAST(Handler)(handler))
-  {
-  }
-
-  /// Destructor automatically frees the OVERLAPPED object unless released.
-  ~overlapped_ptr()
-  {
-  }
-
-  /// Reset to empty.
-  void reset()
-  {
-    impl_.reset();
-  }
-
-  /// Reset to contain the specified handler, freeing any current OVERLAPPED
-  /// object.
-  template <typename Handler>
-  void reset(asio::io_context& io_context,
-      ASIO_MOVE_ARG(Handler) handler)
-  {
-    impl_.reset(io_context, ASIO_MOVE_CAST(Handler)(handler));
-  }
-
-  /// Get the contained OVERLAPPED object.
-  OVERLAPPED* get()
-  {
-    return impl_.get();
-  }
-
-  /// Get the contained OVERLAPPED object.
-  const OVERLAPPED* get() const
-  {
-    return impl_.get();
-  }
-
-  /// Release ownership of the OVERLAPPED object.
-  OVERLAPPED* release()
-  {
-    return impl_.release();
-  }
-
-  /// Post completion notification for overlapped operation. Releases ownership.
-  void complete(const asio::error_code& ec,
-      std::size_t bytes_transferred)
-  {
-    impl_.complete(ec, bytes_transferred);
-  }
-
-private:
-  detail::win_iocp_overlapped_ptr impl_;
-};
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_OVERLAPPED_PTR)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_WINDOWS_OVERLAPPED_PTR_HPP
diff --git a/tools/sdk/include/asio/asio/windows/random_access_handle.hpp b/tools/sdk/include/asio/asio/windows/random_access_handle.hpp
deleted file mode 100644
index 301d5f8dd35..00000000000
--- a/tools/sdk/include/asio/asio/windows/random_access_handle.hpp
+++ /dev/null
@@ -1,378 +0,0 @@
-//
-// windows/random_access_handle.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_RANDOM_ACCESS_HANDLE_HPP
-#define ASIO_WINDOWS_RANDOM_ACCESS_HANDLE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/windows/overlapped_handle.hpp"
-
-#if defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/windows/basic_random_access_handle.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-// Typedef for the typical usage of a random-access handle.
-typedef basic_random_access_handle<> random_access_handle;
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-/// Provides random-access handle functionality.
-/**
- * The windows::random_access_handle class provides asynchronous and
- * blocking random-access handle functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- */
-class random_access_handle
-  : public overlapped_handle
-{
-public:
-  /// Construct a random_access_handle without opening it.
-  /**
-   * This constructor creates a random-access handle without opening it. The
-   * handle needs to be opened before data can be written to or read from it.
-   *
-   * @param io_context The io_context object that the random-access handle will
-   * use to dispatch handlers for any asynchronous operations performed on the
-   * handle.
-   */
-  explicit random_access_handle(asio::io_context& io_context)
-    : overlapped_handle(io_context)
-  {
-  }
-
-  /// Construct a random_access_handle on an existing native handle.
-  /**
-   * This constructor creates a random-access handle object to hold an existing
-   * native handle.
-   *
-   * @param io_context The io_context object that the random-access handle will
-   * use to dispatch handlers for any asynchronous operations performed on the
-   * handle.
-   *
-   * @param handle The new underlying handle implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  random_access_handle(asio::io_context& io_context,
-      const native_handle_type& handle)
-    : overlapped_handle(io_context, handle)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a random_access_handle from another.
-  /**
-   * This constructor moves a random-access handle from one object to another.
-   *
-   * @param other The other random_access_handle object from which the
-   * move will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c random_access_handle(io_context&)
-   * constructor.
-   */
-  random_access_handle(random_access_handle&& other)
-    : overlapped_handle(std::move(other))
-  {
-  }
-
-  /// Move-assign a random_access_handle from another.
-  /**
-   * This assignment operator moves a random-access handle from one object to
-   * another.
-   *
-   * @param other The other random_access_handle object from which the
-   * move will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c random_access_handle(io_context&)
-   * constructor.
-   */
-  random_access_handle& operator=(random_access_handle&& other)
-  {
-    overlapped_handle::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Write some data to the handle at the specified offset.
-  /**
-   * This function is used to write data to the random-access handle. The
-   * function call will block until one or more bytes of the data has been
-   * written successfully, or until an error occurs.
-   *
-   * @param offset The offset at which the data will be written.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The write_some_at operation may not write all of the data. Consider
-   * using the @ref write_at function if you need to ensure that all data is
-   * written before the blocking operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.write_some_at(42, asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some_at(uint64_t offset,
-      const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().write_some_at(
-        this->get_implementation(), offset, buffers, ec);
-    asio::detail::throw_error(ec, "write_some_at");
-    return s;
-  }
-
-  /// Write some data to the handle at the specified offset.
-  /**
-   * This function is used to write data to the random-access handle. The
-   * function call will block until one or more bytes of the data has been
-   * written successfully, or until an error occurs.
-   *
-   * @param offset The offset at which the data will be written.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write_at function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some_at(uint64_t offset,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    return this->get_service().write_some_at(
-        this->get_implementation(), offset, buffers, ec);
-  }
-
-  /// Start an asynchronous write at the specified offset.
-  /**
-   * This function is used to asynchronously write data to the random-access
-   * handle. The function call always returns immediately.
-   *
-   * @param offset The offset at which the data will be written.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The write operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write_at function if you need to ensure that
-   * all data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.async_write_some_at(42, asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some_at(uint64_t offset,
-      const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-    asio::async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_write_some_at(this->get_implementation(),
-        offset, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Read some data from the handle at the specified offset.
-  /**
-   * This function is used to read data from the random-access handle. The
-   * function call will block until one or more bytes of data has been read
-   * successfully, or until an error occurs.
-   *
-   * @param offset The offset at which the data will be read.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read_at function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.read_some_at(42, asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some_at(uint64_t offset,
-      const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().read_some_at(
-        this->get_implementation(), offset, buffers, ec);
-    asio::detail::throw_error(ec, "read_some_at");
-    return s;
-  }
-
-  /// Read some data from the handle at the specified offset.
-  /**
-   * This function is used to read data from the random-access handle. The
-   * function call will block until one or more bytes of data has been read
-   * successfully, or until an error occurs.
-   *
-   * @param offset The offset at which the data will be read.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read_at function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some_at(uint64_t offset,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    return this->get_service().read_some_at(
-        this->get_implementation(), offset, buffers, ec);
-  }
-
-  /// Start an asynchronous read at the specified offset.
-  /**
-   * This function is used to asynchronously read data from the random-access
-   * handle. The function call always returns immediately.
-   *
-   * @param offset The offset at which the data will be read.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The read operation may not read all of the requested number of bytes.
-   * Consider using the @ref async_read_at function if you need to ensure that
-   * the requested amount of data is read before the asynchronous operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.async_read_some_at(42, asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some_at(uint64_t offset,
-      const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-    asio::async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_read_some_at(this->get_implementation(),
-        offset, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-};
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_WINDOWS_RANDOM_ACCESS_HANDLE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/random_access_handle_service.hpp b/tools/sdk/include/asio/asio/windows/random_access_handle_service.hpp
deleted file mode 100644
index ebccf3e3944..00000000000
--- a/tools/sdk/include/asio/asio/windows/random_access_handle_service.hpp
+++ /dev/null
@@ -1,214 +0,0 @@
-//
-// windows/random_access_handle_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_RANDOM_ACCESS_HANDLE_SERVICE_HPP
-#define ASIO_WINDOWS_RANDOM_ACCESS_HANDLE_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/cstdint.hpp"
-#include "asio/detail/win_iocp_handle_service.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-/// Default service implementation for a random-access handle.
-class random_access_handle_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<random_access_handle_service>
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-private:
-  // The type of the platform-specific implementation.
-  typedef detail::win_iocp_handle_service service_impl_type;
-
-public:
-  /// The type of a random-access handle implementation.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native handle type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new random-access handle service for the specified io_context.
-  explicit random_access_handle_service(asio::io_context& io_context)
-    : asio::detail::service_base<
-        random_access_handle_service>(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new random-access handle implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new random-access handle implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another random-access handle implementation.
-  void move_assign(implementation_type& impl,
-      random_access_handle_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a random-access handle implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Assign an existing native handle to a random-access handle.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const native_handle_type& handle, asio::error_code& ec)
-  {
-    service_impl_.assign(impl, handle, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the handle is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Close a random-access handle implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native handle implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Write the given data at the specified offset.
-  template <typename ConstBufferSequence>
-  std::size_t write_some_at(implementation_type& impl, uint64_t offset,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    return service_impl_.write_some_at(impl, offset, buffers, ec);
-  }
-
-  /// Start an asynchronous write at the specified offset.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some_at(implementation_type& impl,
-      uint64_t offset, const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    asio::async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_write_some_at(impl,
-        offset, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Read some data from the specified offset.
-  template <typename MutableBufferSequence>
-  std::size_t read_some_at(implementation_type& impl, uint64_t offset,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    return service_impl_.read_some_at(impl, offset, buffers, ec);
-  }
-
-  /// Start an asynchronous read at the specified offset.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some_at(implementation_type& impl,
-      uint64_t offset, const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    asio::async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_read_some_at(impl,
-        offset, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_RANDOM_ACCESS_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_WINDOWS_RANDOM_ACCESS_HANDLE_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/stream_handle.hpp b/tools/sdk/include/asio/asio/windows/stream_handle.hpp
deleted file mode 100644
index 8f0a21b1fe9..00000000000
--- a/tools/sdk/include/asio/asio/windows/stream_handle.hpp
+++ /dev/null
@@ -1,362 +0,0 @@
-//
-// windows/stream_handle.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_STREAM_HANDLE_HPP
-#define ASIO_WINDOWS_STREAM_HANDLE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include "asio/windows/overlapped_handle.hpp"
-
-#if defined(ASIO_HAS_WINDOWS_STREAM_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-# include "asio/windows/basic_stream_handle.hpp"
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-// Typedef for the typical usage of a stream-oriented handle.
-typedef basic_stream_handle<> stream_handle;
-#else // defined(ASIO_ENABLE_OLD_SERVICES)
-/// Provides stream-oriented handle functionality.
-/**
- * The windows::stream_handle class provides asynchronous and blocking
- * stream-oriented handle functionality.
- *
- * @par Thread Safety
- * @e Distinct @e objects: Safe.@n
- * @e Shared @e objects: Unsafe.
- *
- * @par Concepts:
- * AsyncReadStream, AsyncWriteStream, Stream, SyncReadStream, SyncWriteStream.
- */
-class stream_handle
-  : public overlapped_handle
-{
-public:
-  /// Construct a stream_handle without opening it.
-  /**
-   * This constructor creates a stream handle without opening it. The handle
-   * needs to be opened and then connected or accepted before data can be sent
-   * or received on it.
-   *
-   * @param io_context The io_context object that the stream handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   */
-  explicit stream_handle(asio::io_context& io_context)
-    : overlapped_handle(io_context)
-  {
-  }
-
-  /// Construct a stream_handle on an existing native handle.
-  /**
-   * This constructor creates a stream handle object to hold an existing native
-   * handle.
-   *
-   * @param io_context The io_context object that the stream handle will use to
-   * dispatch handlers for any asynchronous operations performed on the handle.
-   *
-   * @param handle The new underlying handle implementation.
-   *
-   * @throws asio::system_error Thrown on failure.
-   */
-  stream_handle(asio::io_context& io_context,
-      const native_handle_type& handle)
-    : overlapped_handle(io_context, handle)
-  {
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a stream_handle from another.
-  /**
-   * This constructor moves a stream handle from one object to another.
-   *
-   * @param other The other stream_handle object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c stream_handle(io_context&) constructor.
-   */
-  stream_handle(stream_handle&& other)
-    : overlapped_handle(std::move(other))
-  {
-  }
-
-  /// Move-assign a stream_handle from another.
-  /**
-   * This assignment operator moves a stream handle from one object to
-   * another.
-   *
-   * @param other The other stream_handle object from which the move
-   * will occur.
-   *
-   * @note Following the move, the moved-from object is in the same state as if
-   * constructed using the @c stream_handle(io_context&) constructor.
-   */
-  stream_handle& operator=(stream_handle&& other)
-  {
-    overlapped_handle::operator=(std::move(other));
-    return *this;
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Write some data to the handle.
-  /**
-   * This function is used to write data to the stream handle. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   *
-   * @returns The number of bytes written.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.write_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "write_some");
-    return s;
-  }
-
-  /// Write some data to the handle.
-  /**
-   * This function is used to write data to the stream handle. The function call
-   * will block until one or more bytes of the data has been written
-   * successfully, or until an error occurs.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes written. Returns 0 if an error occurred.
-   *
-   * @note The write_some operation may not transmit all of the data to the
-   * peer. Consider using the @ref write function if you need to ensure that
-   * all data is written before the blocking operation completes.
-   */
-  template <typename ConstBufferSequence>
-  std::size_t write_some(const ConstBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().write_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous write.
-  /**
-   * This function is used to asynchronously write data to the stream handle.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more data buffers to be written to the handle.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the write operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes written.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The write operation may not transmit all of the data to the peer.
-   * Consider using the @ref async_write function if you need to ensure that all
-   * data is written before the asynchronous operation completes.
-   *
-   * @par Example
-   * To write a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.async_write_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on writing multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a WriteHandler.
-    ASIO_WRITE_HANDLER_CHECK(WriteHandler, handler) type_check;
-
-    asio::async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_write_some(
-        this->get_implementation(), buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Read some data from the handle.
-  /**
-   * This function is used to read data from the stream handle. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @returns The number of bytes read.
-   *
-   * @throws asio::system_error Thrown on failure. An error code of
-   * asio::error::eof indicates that the connection was closed by the
-   * peer.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.read_some(asio::buffer(data, size));
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers)
-  {
-    asio::error_code ec;
-    std::size_t s = this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-    asio::detail::throw_error(ec, "read_some");
-    return s;
-  }
-
-  /// Read some data from the handle.
-  /**
-   * This function is used to read data from the stream handle. The function
-   * call will block until one or more bytes of data has been read successfully,
-   * or until an error occurs.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   *
-   * @param ec Set to indicate what error occurred, if any.
-   *
-   * @returns The number of bytes read. Returns 0 if an error occurred.
-   *
-   * @note The read_some operation may not read all of the requested number of
-   * bytes. Consider using the @ref read function if you need to ensure that
-   * the requested amount of data is read before the blocking operation
-   * completes.
-   */
-  template <typename MutableBufferSequence>
-  std::size_t read_some(const MutableBufferSequence& buffers,
-      asio::error_code& ec)
-  {
-    return this->get_service().read_some(
-        this->get_implementation(), buffers, ec);
-  }
-
-  /// Start an asynchronous read.
-  /**
-   * This function is used to asynchronously read data from the stream handle.
-   * The function call always returns immediately.
-   *
-   * @param buffers One or more buffers into which the data will be read.
-   * Although the buffers object may be copied as necessary, ownership of the
-   * underlying memory blocks is retained by the caller, which must guarantee
-   * that they remain valid until the handler is called.
-   *
-   * @param handler The handler to be called when the read operation completes.
-   * Copies will be made of the handler as required. The function signature of
-   * the handler must be:
-   * @code void handler(
-   *   const asio::error_code& error, // Result of operation.
-   *   std::size_t bytes_transferred           // Number of bytes read.
-   * ); @endcode
-   * Regardless of whether the asynchronous operation completes immediately or
-   * not, the handler will not be invoked from within this function. Invocation
-   * of the handler will be performed in a manner equivalent to using
-   * asio::io_context::post().
-   *
-   * @note The read operation may not read all of the requested number of bytes.
-   * Consider using the @ref async_read function if you need to ensure that the
-   * requested amount of data is read before the asynchronous operation
-   * completes.
-   *
-   * @par Example
-   * To read into a single data buffer use the @ref buffer function as follows:
-   * @code
-   * handle.async_read_some(asio::buffer(data, size), handler);
-   * @endcode
-   * See the @ref buffer documentation for information on reading into multiple
-   * buffers in one go, and how to use it with arrays, boost::array or
-   * std::vector.
-   */
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    // If you get an error on the following line it means that your handler does
-    // not meet the documented type requirements for a ReadHandler.
-    ASIO_READ_HANDLER_CHECK(ReadHandler, handler) type_check;
-
-    asio::async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    this->get_service().async_read_some(
-        this->get_implementation(), buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-};
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_STREAM_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // ASIO_WINDOWS_STREAM_HANDLE_HPP
diff --git a/tools/sdk/include/asio/asio/windows/stream_handle_service.hpp b/tools/sdk/include/asio/asio/windows/stream_handle_service.hpp
deleted file mode 100644
index 1c665d5e1e0..00000000000
--- a/tools/sdk/include/asio/asio/windows/stream_handle_service.hpp
+++ /dev/null
@@ -1,210 +0,0 @@
-//
-// windows/stream_handle_service.hpp
-// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WINDOWS_STREAM_HANDLE_SERVICE_HPP
-#define ASIO_WINDOWS_STREAM_HANDLE_SERVICE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-
-#if defined(ASIO_ENABLE_OLD_SERVICES)
-
-#if defined(ASIO_HAS_WINDOWS_STREAM_HANDLE) \
-  || defined(GENERATING_DOCUMENTATION)
-
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/win_iocp_handle_service.hpp"
-#include "asio/error.hpp"
-#include "asio/io_context.hpp"
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-namespace windows {
-
-/// Default service implementation for a stream handle.
-class stream_handle_service
-#if defined(GENERATING_DOCUMENTATION)
-  : public asio::io_context::service
-#else
-  : public asio::detail::service_base<stream_handle_service>
-#endif
-{
-public:
-#if defined(GENERATING_DOCUMENTATION)
-  /// The unique service identifier.
-  static asio::io_context::id id;
-#endif
-
-private:
-  // The type of the platform-specific implementation.
-  typedef detail::win_iocp_handle_service service_impl_type;
-
-public:
-  /// The type of a stream handle implementation.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined implementation_type;
-#else
-  typedef service_impl_type::implementation_type implementation_type;
-#endif
-
-  /// The native handle type.
-#if defined(GENERATING_DOCUMENTATION)
-  typedef implementation_defined native_handle_type;
-#else
-  typedef service_impl_type::native_handle_type native_handle_type;
-#endif
-
-  /// Construct a new stream handle service for the specified io_context.
-  explicit stream_handle_service(asio::io_context& io_context)
-    : asio::detail::service_base<stream_handle_service>(io_context),
-      service_impl_(io_context)
-  {
-  }
-
-  /// Construct a new stream handle implementation.
-  void construct(implementation_type& impl)
-  {
-    service_impl_.construct(impl);
-  }
-
-#if defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-  /// Move-construct a new stream handle implementation.
-  void move_construct(implementation_type& impl,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_construct(impl, other_impl);
-  }
-
-  /// Move-assign from another stream handle implementation.
-  void move_assign(implementation_type& impl,
-      stream_handle_service& other_service,
-      implementation_type& other_impl)
-  {
-    service_impl_.move_assign(impl, other_service.service_impl_, other_impl);
-  }
-#endif // defined(ASIO_HAS_MOVE) || defined(GENERATING_DOCUMENTATION)
-
-  /// Destroy a stream handle implementation.
-  void destroy(implementation_type& impl)
-  {
-    service_impl_.destroy(impl);
-  }
-
-  /// Assign an existing native handle to a stream handle.
-  ASIO_SYNC_OP_VOID assign(implementation_type& impl,
-      const native_handle_type& handle, asio::error_code& ec)
-  {
-    service_impl_.assign(impl, handle, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Determine whether the handle is open.
-  bool is_open(const implementation_type& impl) const
-  {
-    return service_impl_.is_open(impl);
-  }
-
-  /// Close a stream handle implementation.
-  ASIO_SYNC_OP_VOID close(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.close(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Get the native handle implementation.
-  native_handle_type native_handle(implementation_type& impl)
-  {
-    return service_impl_.native_handle(impl);
-  }
-
-  /// Cancel all asynchronous operations associated with the handle.
-  ASIO_SYNC_OP_VOID cancel(implementation_type& impl,
-      asio::error_code& ec)
-  {
-    service_impl_.cancel(impl, ec);
-    ASIO_SYNC_OP_VOID_RETURN(ec);
-  }
-
-  /// Write the given data to the stream.
-  template <typename ConstBufferSequence>
-  std::size_t write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers, asio::error_code& ec)
-  {
-    return service_impl_.write_some(impl, buffers, ec);
-  }
-
-  /// Start an asynchronous write.
-  template <typename ConstBufferSequence, typename WriteHandler>
-  ASIO_INITFN_RESULT_TYPE(WriteHandler,
-      void (asio::error_code, std::size_t))
-  async_write_some(implementation_type& impl,
-      const ConstBufferSequence& buffers,
-      ASIO_MOVE_ARG(WriteHandler) handler)
-  {
-    asio::async_completion<WriteHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_write_some(impl, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-  /// Read some data from the stream.
-  template <typename MutableBufferSequence>
-  std::size_t read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers, asio::error_code& ec)
-  {
-    return service_impl_.read_some(impl, buffers, ec);
-  }
-
-  /// Start an asynchronous read.
-  template <typename MutableBufferSequence, typename ReadHandler>
-  ASIO_INITFN_RESULT_TYPE(ReadHandler,
-      void (asio::error_code, std::size_t))
-  async_read_some(implementation_type& impl,
-      const MutableBufferSequence& buffers,
-      ASIO_MOVE_ARG(ReadHandler) handler)
-  {
-    asio::async_completion<ReadHandler,
-      void (asio::error_code, std::size_t)> init(handler);
-
-    service_impl_.async_read_some(impl, buffers, init.completion_handler);
-
-    return init.result.get();
-  }
-
-private:
-  // Destroy all user-defined handler objects owned by the service.
-  void shutdown()
-  {
-    service_impl_.shutdown();
-  }
-
-  // The platform-specific implementation.
-  service_impl_type service_impl_;
-};
-
-} // namespace windows
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#endif // defined(ASIO_HAS_WINDOWS_STREAM_HANDLE)
-       //   || defined(GENERATING_DOCUMENTATION)
-
-#endif // defined(ASIO_ENABLE_OLD_SERVICES)
-
-#endif // ASIO_WINDOWS_STREAM_HANDLE_SERVICE_HPP
diff --git a/tools/sdk/include/asio/asio/write.hpp b/tools/sdk/include/asio/asio/write.hpp
deleted file mode 100644
index 517a8420537..00000000000
--- a/tools/sdk/include/asio/asio/write.hpp
+++ /dev/null
@@ -1,927 +0,0 @@
-//
-// write.hpp
-// ~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WRITE_HPP
-#define ASIO_WRITE_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/buffer.hpp"
-#include "asio/error.hpp"
-
-#if !defined(ASIO_NO_EXTENSIONS)
-# include "asio/basic_streambuf_fwd.hpp"
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/**
- * @defgroup write asio::write
- *
- * @brief Write a certain amount of data to a stream before returning.
- */
-/*@{*/
-
-/// Write all of the supplied data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param buffers One or more buffers containing the data to be written. The sum
- * of the buffer sizes indicates the maximum number of bytes to write to the
- * stream.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code asio::write(s, asio::buffer(data, size)); @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write(
- *     s, buffers,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncWriteStream, typename ConstBufferSequence>
-std::size_t write(SyncWriteStream& s, const ConstBufferSequence& buffers,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type* = 0);
-
-/// Write all of the supplied data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param buffers One or more buffers containing the data to be written. The sum
- * of the buffer sizes indicates the maximum number of bytes to write to the
- * stream.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code asio::write(s, asio::buffer(data, size), ec); @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write(
- *     s, buffers,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncWriteStream, typename ConstBufferSequence>
-std::size_t write(SyncWriteStream& s, const ConstBufferSequence& buffers,
-    asio::error_code& ec,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type* = 0);
-
-/// Write a certain amount of data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param buffers One or more buffers containing the data to be written. The sum
- * of the buffer sizes indicates the maximum number of bytes to write to the
- * stream.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the stream's write_some function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code asio::write(s, asio::buffer(data, size),
- *     asio::transfer_at_least(32)); @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename SyncWriteStream, typename ConstBufferSequence,
-    typename CompletionCondition>
-std::size_t write(SyncWriteStream& s, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type* = 0);
-
-/// Write a certain amount of data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param buffers One or more buffers containing the data to be written. The sum
- * of the buffer sizes indicates the maximum number of bytes to write to the
- * stream.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the stream's write_some function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes written. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncWriteStream, typename ConstBufferSequence,
-    typename CompletionCondition>
-std::size_t write(SyncWriteStream& s, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition, asio::error_code& ec,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type* = 0);
-
-/// Write all of the supplied data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied dynamic buffer sequence has been written.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param buffers The dynamic buffer sequence from which data will be written.
- * Successfully written data is automatically consumed from the buffers.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write(
- *     s, buffers,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncWriteStream, typename DynamicBuffer>
-std::size_t write(SyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-/// Write all of the supplied data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied dynamic buffer sequence has been written.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param buffers The dynamic buffer sequence from which data will be written.
- * Successfully written data is automatically consumed from the buffers.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write(
- *     s, buffers,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncWriteStream, typename DynamicBuffer>
-std::size_t write(SyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    asio::error_code& ec,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-/// Write a certain amount of data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied dynamic buffer sequence has been written.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param buffers The dynamic buffer sequence from which data will be written.
- * Successfully written data is automatically consumed from the buffers.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the stream's write_some function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- */
-template <typename SyncWriteStream, typename DynamicBuffer,
-    typename CompletionCondition>
-std::size_t write(SyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-/// Write a certain amount of data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied dynamic buffer sequence has been written.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param buffers The dynamic buffer sequence from which data will be written.
- * Successfully written data is automatically consumed from the buffers.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the stream's write_some function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes written. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncWriteStream, typename DynamicBuffer,
-    typename CompletionCondition>
-std::size_t write(SyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition, asio::error_code& ec,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Write all of the supplied data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param b The basic_streambuf object from which data will be written.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write(
- *     s, b,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncWriteStream, typename Allocator>
-std::size_t write(SyncWriteStream& s, basic_streambuf<Allocator>& b);
-
-/// Write all of the supplied data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param b The basic_streambuf object from which data will be written.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write(
- *     s, b,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncWriteStream, typename Allocator>
-std::size_t write(SyncWriteStream& s, basic_streambuf<Allocator>& b,
-    asio::error_code& ec);
-
-/// Write a certain amount of data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param b The basic_streambuf object from which data will be written.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the stream's write_some function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- */
-template <typename SyncWriteStream, typename Allocator,
-    typename CompletionCondition>
-std::size_t write(SyncWriteStream& s, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition);
-
-/// Write a certain amount of data to a stream before returning.
-/**
- * This function is used to write a certain number of bytes of data to a stream.
- * The call will block until one of the following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * write_some function.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the SyncWriteStream concept.
- *
- * @param b The basic_streambuf object from which data will be written.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the stream's write_some function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes written. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncWriteStream, typename Allocator,
-    typename CompletionCondition>
-std::size_t write(SyncWriteStream& s, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition, asio::error_code& ec);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-/**
- * @defgroup async_write asio::async_write
- *
- * @brief Start an asynchronous operation to write a certain amount of data to a
- * stream.
- */
-/*@{*/
-
-/// Start an asynchronous operation to write all of the supplied data to a
-/// stream.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_write_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other write operations (such
- * as async_write, the stream's async_write_some function, or any other composed
- * operations that perform writes) until this operation completes.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the AsyncWriteStream concept.
- *
- * @param buffers One or more buffers containing the data to be written.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of
- * the handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes written from the
- *                                           // buffers. If an error occurred,
- *                                           // this will be less than the sum
- *                                           // of the buffer sizes.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code
- * asio::async_write(s, asio::buffer(data, size), handler);
- * @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename AsyncWriteStream, typename ConstBufferSequence,
-    typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s, const ConstBufferSequence& buffers,
-    ASIO_MOVE_ARG(WriteHandler) handler,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type* = 0);
-
-/// Start an asynchronous operation to write a certain amount of data to a
-/// stream.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_write_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other write operations (such
- * as async_write, the stream's async_write_some function, or any other composed
- * operations that perform writes) until this operation completes.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the AsyncWriteStream concept.
- *
- * @param buffers One or more buffers containing the data to be written.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_write_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the stream's async_write_some function.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes written from the
- *                                           // buffers. If an error occurred,
- *                                           // this will be less than the sum
- *                                           // of the buffer sizes.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code asio::async_write(s,
- *     asio::buffer(data, size),
- *     asio::transfer_at_least(32),
- *     handler); @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename AsyncWriteStream, typename ConstBufferSequence,
-    typename CompletionCondition, typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler,
-    typename enable_if<
-      is_const_buffer_sequence<ConstBufferSequence>::value
-    >::type* = 0);
-
-/// Start an asynchronous operation to write all of the supplied data to a
-/// stream.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li All of the data in the supplied dynamic buffer sequence has been written.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_write_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other write operations (such
- * as async_write, the stream's async_write_some function, or any other composed
- * operations that perform writes) until this operation completes.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the AsyncWriteStream concept.
- *
- * @param buffers The dynamic buffer sequence from which data will be written.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called. Successfully written
- * data is automatically consumed from the buffers.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes written from the
- *                                           // buffers. If an error occurred,
- *                                           // this will be less than the sum
- *                                           // of the buffer sizes.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- */
-template <typename AsyncWriteStream,
-    typename DynamicBuffer, typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    ASIO_MOVE_ARG(WriteHandler) handler,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-/// Start an asynchronous operation to write a certain amount of data to a
-/// stream.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li All of the data in the supplied dynamic buffer sequence has been written.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_write_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other write operations (such
- * as async_write, the stream's async_write_some function, or any other composed
- * operations that perform writes) until this operation completes.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the AsyncWriteStream concept.
- *
- * @param buffers The dynamic buffer sequence from which data will be written.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called. Successfully written
- * data is automatically consumed from the buffers.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_write_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the stream's async_write_some function.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes written from the
- *                                           // buffers. If an error occurred,
- *                                           // this will be less than the sum
- *                                           // of the buffer sizes.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- */
-template <typename AsyncWriteStream, typename DynamicBuffer,
-    typename CompletionCondition, typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s,
-    ASIO_MOVE_ARG(DynamicBuffer) buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler,
-    typename enable_if<
-      is_dynamic_buffer<typename decay<DynamicBuffer>::type>::value
-    >::type* = 0);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Start an asynchronous operation to write all of the supplied data to a
-/// stream.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_write_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other write operations (such
- * as async_write, the stream's async_write_some function, or any other composed
- * operations that perform writes) until this operation completes.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the AsyncWriteStream concept.
- *
- * @param b A basic_streambuf object from which data will be written. Ownership
- * of the streambuf is retained by the caller, which must guarantee that it
- * remains valid until the handler is called.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes written from the
- *                                           // buffers. If an error occurred,
- *                                           // this will be less than the sum
- *                                           // of the buffer sizes.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- */
-template <typename AsyncWriteStream, typename Allocator, typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s, basic_streambuf<Allocator>& b,
-    ASIO_MOVE_ARG(WriteHandler) handler);
-
-/// Start an asynchronous operation to write a certain amount of data to a
-/// stream.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a stream. The function call always returns immediately. The
- * asynchronous operation will continue until one of the following conditions
- * is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the stream's
- * async_write_some function, and is known as a <em>composed operation</em>. The
- * program must ensure that the stream performs no other write operations (such
- * as async_write, the stream's async_write_some function, or any other composed
- * operations that perform writes) until this operation completes.
- *
- * @param s The stream to which the data is to be written. The type must support
- * the AsyncWriteStream concept.
- *
- * @param b A basic_streambuf object from which data will be written. Ownership
- * of the streambuf is retained by the caller, which must guarantee that it
- * remains valid until the handler is called.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_write_some operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the stream's async_write_some function.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   const asio::error_code& error, // Result of operation.
- *
- *   std::size_t bytes_transferred           // Number of bytes written from the
- *                                           // buffers. If an error occurred,
- *                                           // this will be less than the sum
- *                                           // of the buffer sizes.
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- */
-template <typename AsyncWriteStream, typename Allocator,
-    typename CompletionCondition, typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write(AsyncWriteStream& s, basic_streambuf<Allocator>& b,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/write.hpp"
-
-#endif // ASIO_WRITE_HPP
diff --git a/tools/sdk/include/asio/asio/write_at.hpp b/tools/sdk/include/asio/asio/write_at.hpp
deleted file mode 100644
index 5018d210605..00000000000
--- a/tools/sdk/include/asio/asio/write_at.hpp
+++ /dev/null
@@ -1,677 +0,0 @@
-//
-// write_at.hpp
-// ~~~~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#ifndef ASIO_WRITE_AT_HPP
-#define ASIO_WRITE_AT_HPP
-
-#if defined(_MSC_VER) && (_MSC_VER >= 1200)
-# pragma once
-#endif // defined(_MSC_VER) && (_MSC_VER >= 1200)
-
-#include "asio/detail/config.hpp"
-#include <cstddef>
-#include "asio/async_result.hpp"
-#include "asio/detail/cstdint.hpp"
-#include "asio/error.hpp"
-
-#if !defined(ASIO_NO_EXTENSIONS)
-# include "asio/basic_streambuf_fwd.hpp"
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-#include "asio/detail/push_options.hpp"
-
-namespace asio {
-
-/**
- * @defgroup write_at asio::write_at
- *
- * @brief Write a certain amount of data at a specified offset before returning.
- */
-/*@{*/
-
-/// Write all of the supplied data at the specified offset before returning.
-/**
- * This function is used to write a certain number of bytes of data to a random
- * access device at a specified offset. The call will block until one of the
- * following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * write_some_at function.
- *
- * @param d The device to which the data is to be written. The type must support
- * the SyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param buffers One or more buffers containing the data to be written. The sum
- * of the buffer sizes indicates the maximum number of bytes to write to the
- * device.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code asio::write_at(d, 42, asio::buffer(data, size)); @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write_at(
- *     d, offset, buffers,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncRandomAccessWriteDevice, typename ConstBufferSequence>
-std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers);
-
-/// Write all of the supplied data at the specified offset before returning.
-/**
- * This function is used to write a certain number of bytes of data to a random
- * access device at a specified offset. The call will block until one of the
- * following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * write_some_at function.
- *
- * @param d The device to which the data is to be written. The type must support
- * the SyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param buffers One or more buffers containing the data to be written. The sum
- * of the buffer sizes indicates the maximum number of bytes to write to the
- * device.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code asio::write_at(d, 42,
- *     asio::buffer(data, size), ec); @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write_at(
- *     d, offset, buffers,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncRandomAccessWriteDevice, typename ConstBufferSequence>
-std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers,
-    asio::error_code& ec);
-
-/// Write a certain amount of data at a specified offset before returning.
-/**
- * This function is used to write a certain number of bytes of data to a random
- * access device at a specified offset. The call will block until one of the
- * following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * write_some_at function.
- *
- * @param d The device to which the data is to be written. The type must support
- * the SyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param buffers One or more buffers containing the data to be written. The sum
- * of the buffer sizes indicates the maximum number of bytes to write to the
- * device.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the device's write_some_at function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code asio::write_at(d, 42, asio::buffer(data, size),
- *     asio::transfer_at_least(32)); @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename SyncRandomAccessWriteDevice, typename ConstBufferSequence,
-    typename CompletionCondition>
-std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition);
-
-/// Write a certain amount of data at a specified offset before returning.
-/**
- * This function is used to write a certain number of bytes of data to a random
- * access device at a specified offset. The call will block until one of the
- * following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * write_some_at function.
- *
- * @param d The device to which the data is to be written. The type must support
- * the SyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param buffers One or more buffers containing the data to be written. The sum
- * of the buffer sizes indicates the maximum number of bytes to write to the
- * device.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the device's write_some_at function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes written. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncRandomAccessWriteDevice, typename ConstBufferSequence,
-    typename CompletionCondition>
-std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition, asio::error_code& ec);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Write all of the supplied data at the specified offset before returning.
-/**
- * This function is used to write a certain number of bytes of data to a random
- * access device at a specified offset. The call will block until one of the
- * following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * write_some_at function.
- *
- * @param d The device to which the data is to be written. The type must support
- * the SyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param b The basic_streambuf object from which data will be written.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write_at(
- *     d, 42, b,
- *     asio::transfer_all()); @endcode
- */
-template <typename SyncRandomAccessWriteDevice, typename Allocator>
-std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, basic_streambuf<Allocator>& b);
-
-/// Write all of the supplied data at the specified offset before returning.
-/**
- * This function is used to write a certain number of bytes of data to a random
- * access device at a specified offset. The call will block until one of the
- * following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * write_some_at function.
- *
- * @param d The device to which the data is to be written. The type must support
- * the SyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param b The basic_streambuf object from which data will be written.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes transferred.
- *
- * @note This overload is equivalent to calling:
- * @code asio::write_at(
- *     d, 42, b,
- *     asio::transfer_all(), ec); @endcode
- */
-template <typename SyncRandomAccessWriteDevice, typename Allocator>
-std::size_t write_at(SyncRandomAccessWriteDevice& d,
-    uint64_t offset, basic_streambuf<Allocator>& b,
-    asio::error_code& ec);
-
-/// Write a certain amount of data at a specified offset before returning.
-/**
- * This function is used to write a certain number of bytes of data to a random
- * access device at a specified offset. The call will block until one of the
- * following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * write_some_at function.
- *
- * @param d The device to which the data is to be written. The type must support
- * the SyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param b The basic_streambuf object from which data will be written.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the device's write_some_at function.
- *
- * @returns The number of bytes transferred.
- *
- * @throws asio::system_error Thrown on failure.
- */
-template <typename SyncRandomAccessWriteDevice, typename Allocator,
-    typename CompletionCondition>
-std::size_t write_at(SyncRandomAccessWriteDevice& d, uint64_t offset,
-    basic_streambuf<Allocator>& b, CompletionCondition completion_condition);
-
-/// Write a certain amount of data at a specified offset before returning.
-/**
- * This function is used to write a certain number of bytes of data to a random
- * access device at a specified offset. The call will block until one of the
- * following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * write_some_at function.
- *
- * @param d The device to which the data is to be written. The type must support
- * the SyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param b The basic_streambuf object from which data will be written.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest write_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the device's write_some_at function.
- *
- * @param ec Set to indicate what error occurred, if any.
- *
- * @returns The number of bytes written. If an error occurs, returns the total
- * number of bytes successfully transferred prior to the error.
- */
-template <typename SyncRandomAccessWriteDevice, typename Allocator,
-    typename CompletionCondition>
-std::size_t write_at(SyncRandomAccessWriteDevice& d, uint64_t offset,
-    basic_streambuf<Allocator>& b, CompletionCondition completion_condition,
-    asio::error_code& ec);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-/**
- * @defgroup async_write_at asio::async_write_at
- *
- * @brief Start an asynchronous operation to write a certain amount of data at
- * the specified offset.
- */
-/*@{*/
-
-/// Start an asynchronous operation to write all of the supplied data at the
-/// specified offset.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a random access device at a specified offset. The function call
- * always returns immediately. The asynchronous operation will continue until
- * one of the following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * async_write_some_at function, and is known as a <em>composed operation</em>.
- * The program must ensure that the device performs no <em>overlapping</em>
- * write operations (such as async_write_at, the device's async_write_some_at
- * function, or any other composed operations that perform writes) until this
- * operation completes. Operations are overlapping if the regions defined by
- * their offsets, and the numbers of bytes to write, intersect.
- *
- * @param d The device to which the data is to be written. The type must support
- * the AsyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param buffers One or more buffers containing the data to be written.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of
- * the handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes written from the buffers. If an error
- *   // occurred, this will be less than the sum of the buffer sizes.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code
- * asio::async_write_at(d, 42, asio::buffer(data, size), handler);
- * @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename AsyncRandomAccessWriteDevice, typename ConstBufferSequence,
-    typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write_at(AsyncRandomAccessWriteDevice& d, uint64_t offset,
-    const ConstBufferSequence& buffers,
-    ASIO_MOVE_ARG(WriteHandler) handler);
-
-/// Start an asynchronous operation to write a certain amount of data at the
-/// specified offset.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a random access device at a specified offset. The function call
- * always returns immediately. The asynchronous operation will continue until
- * one of the following conditions is true:
- *
- * @li All of the data in the supplied buffers has been written. That is, the
- * bytes transferred is equal to the sum of the buffer sizes.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * async_write_some_at function, and is known as a <em>composed operation</em>.
- * The program must ensure that the device performs no <em>overlapping</em>
- * write operations (such as async_write_at, the device's async_write_some_at
- * function, or any other composed operations that perform writes) until this
- * operation completes. Operations are overlapping if the regions defined by
- * their offsets, and the numbers of bytes to write, intersect.
- *
- * @param d The device to which the data is to be written. The type must support
- * the AsyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param buffers One or more buffers containing the data to be written.
- * Although the buffers object may be copied as necessary, ownership of the
- * underlying memory blocks is retained by the caller, which must guarantee
- * that they remain valid until the handler is called.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_write_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the device's async_write_some_at function.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes written from the buffers. If an error
- *   // occurred, this will be less than the sum of the buffer sizes.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- *
- * @par Example
- * To write a single data buffer use the @ref buffer function as follows:
- * @code asio::async_write_at(d, 42,
- *     asio::buffer(data, size),
- *     asio::transfer_at_least(32),
- *     handler); @endcode
- * See the @ref buffer documentation for information on writing multiple
- * buffers in one go, and how to use it with arrays, boost::array or
- * std::vector.
- */
-template <typename AsyncRandomAccessWriteDevice, typename ConstBufferSequence,
-    typename CompletionCondition, typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write_at(AsyncRandomAccessWriteDevice& d,
-    uint64_t offset, const ConstBufferSequence& buffers,
-    CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler);
-
-#if !defined(ASIO_NO_EXTENSIONS)
-#if !defined(ASIO_NO_IOSTREAM)
-
-/// Start an asynchronous operation to write all of the supplied data at the
-/// specified offset.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a random access device at a specified offset. The function call
- * always returns immediately. The asynchronous operation will continue until
- * one of the following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li An error occurred.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * async_write_some_at function, and is known as a <em>composed operation</em>.
- * The program must ensure that the device performs no <em>overlapping</em>
- * write operations (such as async_write_at, the device's async_write_some_at
- * function, or any other composed operations that perform writes) until this
- * operation completes. Operations are overlapping if the regions defined by
- * their offsets, and the numbers of bytes to write, intersect.
- *
- * @param d The device to which the data is to be written. The type must support
- * the AsyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param b A basic_streambuf object from which data will be written. Ownership
- * of the streambuf is retained by the caller, which must guarantee that it
- * remains valid until the handler is called.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes written from the buffers. If an error
- *   // occurred, this will be less than the sum of the buffer sizes.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- */
-template <typename AsyncRandomAccessWriteDevice, typename Allocator,
-    typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write_at(AsyncRandomAccessWriteDevice& d, uint64_t offset,
-    basic_streambuf<Allocator>& b, ASIO_MOVE_ARG(WriteHandler) handler);
-
-/// Start an asynchronous operation to write a certain amount of data at the
-/// specified offset.
-/**
- * This function is used to asynchronously write a certain number of bytes of
- * data to a random access device at a specified offset. The function call
- * always returns immediately. The asynchronous operation will continue until
- * one of the following conditions is true:
- *
- * @li All of the data in the supplied basic_streambuf has been written.
- *
- * @li The completion_condition function object returns 0.
- *
- * This operation is implemented in terms of zero or more calls to the device's
- * async_write_some_at function, and is known as a <em>composed operation</em>.
- * The program must ensure that the device performs no <em>overlapping</em>
- * write operations (such as async_write_at, the device's async_write_some_at
- * function, or any other composed operations that perform writes) until this
- * operation completes. Operations are overlapping if the regions defined by
- * their offsets, and the numbers of bytes to write, intersect.
- *
- * @param d The device to which the data is to be written. The type must support
- * the AsyncRandomAccessWriteDevice concept.
- *
- * @param offset The offset at which the data will be written.
- *
- * @param b A basic_streambuf object from which data will be written. Ownership
- * of the streambuf is retained by the caller, which must guarantee that it
- * remains valid until the handler is called.
- *
- * @param completion_condition The function object to be called to determine
- * whether the write operation is complete. The signature of the function object
- * must be:
- * @code std::size_t completion_condition(
- *   // Result of latest async_write_some_at operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes transferred so far.
- *   std::size_t bytes_transferred
- * ); @endcode
- * A return value of 0 indicates that the write operation is complete. A
- * non-zero return value indicates the maximum number of bytes to be written on
- * the next call to the device's async_write_some_at function.
- *
- * @param handler The handler to be called when the write operation completes.
- * Copies will be made of the handler as required. The function signature of the
- * handler must be:
- * @code void handler(
- *   // Result of operation.
- *   const asio::error_code& error,
- *
- *   // Number of bytes written from the buffers. If an error
- *   // occurred, this will be less than the sum of the buffer sizes.
- *   std::size_t bytes_transferred
- * ); @endcode
- * Regardless of whether the asynchronous operation completes immediately or
- * not, the handler will not be invoked from within this function. Invocation of
- * the handler will be performed in a manner equivalent to using
- * asio::io_context::post().
- */
-template <typename AsyncRandomAccessWriteDevice, typename Allocator,
-    typename CompletionCondition, typename WriteHandler>
-ASIO_INITFN_RESULT_TYPE(WriteHandler,
-    void (asio::error_code, std::size_t))
-async_write_at(AsyncRandomAccessWriteDevice& d, uint64_t offset,
-    basic_streambuf<Allocator>& b, CompletionCondition completion_condition,
-    ASIO_MOVE_ARG(WriteHandler) handler);
-
-#endif // !defined(ASIO_NO_IOSTREAM)
-#endif // !defined(ASIO_NO_EXTENSIONS)
-
-/*@}*/
-
-} // namespace asio
-
-#include "asio/detail/pop_options.hpp"
-
-#include "asio/impl/write_at.hpp"
-
-#endif // ASIO_WRITE_AT_HPP
diff --git a/tools/sdk/include/asio/asio/yield.hpp b/tools/sdk/include/asio/asio/yield.hpp
deleted file mode 100644
index b527ac9b4b2..00000000000
--- a/tools/sdk/include/asio/asio/yield.hpp
+++ /dev/null
@@ -1,23 +0,0 @@
-//
-// yield.hpp
-// ~~~~~~~~~
-//
-// Copyright (c) 2003-2018 Christopher M. Kohlhoff (chris at kohlhoff dot com)
-//
-// Distributed under the Boost Software License, Version 1.0. (See accompanying
-// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
-//
-
-#include "coroutine.hpp"
-
-#ifndef reenter
-# define reenter(c) ASIO_CORO_REENTER(c)
-#endif
-
-#ifndef yield
-# define yield ASIO_CORO_YIELD
-#endif
-
-#ifndef fork
-# define fork ASIO_CORO_FORK
-#endif
diff --git a/tools/sdk/include/asio/esp_asio_config.h b/tools/sdk/include/asio/esp_asio_config.h
deleted file mode 100644
index accccad0da7..00000000000
--- a/tools/sdk/include/asio/esp_asio_config.h
+++ /dev/null
@@ -1,45 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_ASIO_CONFIG_H_
-#define _ESP_ASIO_CONFIG_H_
-
-//
-// Enabling exceptions only when they are enabled in menuconfig
-//
-# include <sdkconfig.h>
-# ifndef CONFIG_CXX_EXCEPTIONS
-#  define ASIO_NO_EXCEPTIONS
-# endif   // CONFIG_CXX_EXCEPTIONS
-
-//
-// LWIP compatifility inet and address macros/functions
-//
-# define LWIP_COMPAT_SOCKET_INET 1
-# define LWIP_COMPAT_SOCKET_ADDR 1
-
-//
-// Specific ASIO feature flags
-//
-# define ASIO_DISABLE_SERIAL_PORT
-# define ASIO_SEPARATE_COMPILATION
-# define ASIO_STANDALONE
-# define ASIO_NO_TYPEID
-# define ASIO_DISABLE_SIGNAL
-# define ASIO_HAS_PTHREADS
-# define ASIO_DISABLE_EPOLL
-# define ASIO_DISABLE_EVENTFD
-# define ASIO_DISABLE_SIGNAL
-# define ASIO_DISABLE_SIGACTION
-
-#endif // _ESP_ASIO_CONFIG_H_
diff --git a/tools/sdk/include/asio/esp_exception.h b/tools/sdk/include/asio/esp_exception.h
deleted file mode 100644
index 3c5c043755f..00000000000
--- a/tools/sdk/include/asio/esp_exception.h
+++ /dev/null
@@ -1,39 +0,0 @@
-
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_EXCEPTION_H_
-#define _ESP_EXCEPTION_H_
-
-//
-// This exception stub is enabled only if exceptions are disabled in menuconfig
-//
-#if !defined(CONFIG_CXX_EXCEPTIONS) && defined (ASIO_NO_EXCEPTIONS)
-
-#include "esp_log.h"
-
-//
-// asio exception stub
-//
-namespace asio {
-namespace detail {
-template <typename Exception>
-void throw_exception(const Exception& e)
-{
-  ESP_LOGE("esp32_asio_exception", "Caught exception: %s!", e.what());   
-  abort();
-}
-}}
-#endif // CONFIG_CXX_EXCEPTIONS==1 && defined (ASIO_NO_EXCEPTIONS)
-
-#endif // _ESP_EXCEPTION_H_
diff --git a/tools/sdk/include/bootloader_support/bootloader_clock.h b/tools/sdk/include/bootloader_support/bootloader_clock.h
deleted file mode 100644
index 9eaba46a8cd..00000000000
--- a/tools/sdk/include/bootloader_support/bootloader_clock.h
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/** @brief Configure clocks for early boot
- *
- * Called by bootloader, or by the app if the bootloader version is old (pre v2.1).
- */
-void bootloader_clock_configure(void);
diff --git a/tools/sdk/include/bootloader_support/bootloader_common.h b/tools/sdk/include/bootloader_support/bootloader_common.h
deleted file mode 100644
index a948adbe6fa..00000000000
--- a/tools/sdk/include/bootloader_support/bootloader_common.h
+++ /dev/null
@@ -1,167 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-#include "esp_flash_data_types.h"
-#include "esp_image_format.h"
-#include "esp_image_format.h"
-
-/// Type of hold a GPIO in low state
-typedef enum {
-    GPIO_LONG_HOLD  = 1,    /*!< The long hold GPIO */
-    GPIO_SHORT_HOLD = -1,   /*!< The short hold GPIO */
-    GPIO_NOT_HOLD   = 0     /*!< If the GPIO input is not low */
-} esp_comm_gpio_hold_t;
-
-typedef enum {
-    ESP_IMAGE_BOOTLOADER,
-    ESP_IMAGE_APPLICATION
-} esp_image_type;
-
-/**
- * @brief Calculate crc for the OTA data select.
- *
- * @param[in] s The OTA data select.
- * @return    Returns crc value.
- */
-uint32_t bootloader_common_ota_select_crc(const esp_ota_select_entry_t *s);
-
-/**
- * @brief Verifies the validity of the OTA data select
- *
- * @param[in] s The OTA data select.
- * @return    Returns true on valid, false otherwise.
- */
-bool bootloader_common_ota_select_valid(const esp_ota_select_entry_t *s);
-
-/**
- * @brief Returns true if OTADATA is not marked as bootable partition.
- *
- * @param[in] s The OTA data select.
- * @return    Returns true if OTADATA invalid, false otherwise.
- */
-bool bootloader_common_ota_select_invalid(const esp_ota_select_entry_t *s);
-
-/**
- * @brief Check if the GPIO input is a long hold or a short hold.
- *
- * Number of the GPIO input will be configured as an input with internal pull-up enabled.
- * If the GPIO input is held low continuously for delay_sec period then it is a long hold.
- * If the GPIO input is held low for less period then it is a short hold.
- *
- * @param[in] num_pin Number of the GPIO input.
- * @param[in] delay_sec Input must be driven low for at least this long, continuously.
- * @return esp_comm_gpio_hold_t Defines type of hold a GPIO in low state.
- */
-esp_comm_gpio_hold_t bootloader_common_check_long_hold_gpio(uint32_t num_pin, uint32_t delay_sec);
-
-/**
- * @brief Erase the partition data that is specified in the transferred list.
- *
- * @param[in] list_erase String containing a list of cleared partitions. Like this "nvs, phy". The string must be null-terminal.
- * @param[in] ota_data_erase If true then the OTA data partition will be cleared (if there is it in partition table).
- * @return    Returns true on success, false otherwise.
- */
-bool bootloader_common_erase_part_type_data(const char *list_erase, bool ota_data_erase);
-
-/**
- * @brief Determines if the list contains the label
- *
- * @param[in] list  A string of names delimited by commas or spaces. Like this "nvs, phy, data". The string must be null-terminated.
- * @param[in] label The substring that will be searched in the list.
- * @return    Returns true if the list contains the label, false otherwise.
- */
-bool bootloader_common_label_search(const char *list, char *label);
-
-/**
- * @brief Calculates a sha-256 for a given partition or returns a appended digest.
- *
- * This function can be used to return the SHA-256 digest of application, bootloader and data partitions.
- * For apps with SHA-256 appended to the app image, the result is the appended SHA-256 value for the app image content.
- * The hash is verified before returning, if app content is invalid then the function returns ESP_ERR_IMAGE_INVALID.
- * For apps without SHA-256 appended to the image, the result is the SHA-256 of all bytes in the app image.
- * For other partition types, the result is the SHA-256 of the entire partition.
- *
- * @param[in]  address      Address of partition.
- * @param[in]  size         Size of partition.
- * @param[in]  type         Type of partition. For applications the type is 0, otherwise type is data.
- * @param[out] out_sha_256  Returned SHA-256 digest for a given partition.
- *
- * @return
- *          - ESP_OK: In case of successful operation.
- *          - ESP_ERR_INVALID_ARG: The size was 0 or the sha_256 was NULL.
- *          - ESP_ERR_NO_MEM: Cannot allocate memory for sha256 operation.
- *          - ESP_ERR_IMAGE_INVALID: App partition doesn't contain a valid app image.
- *          - ESP_FAIL: An allocation error occurred.
- */
-esp_err_t bootloader_common_get_sha256_of_partition(uint32_t address, uint32_t size, int type, uint8_t *out_sha_256);
-
-/**
- * @brief Returns the number of active otadata.
- *
- * @param[in] two_otadata Pointer on array from two otadata structures.
- *
- * @return The number of active otadata (0 or 1).
- *        - -1: If it does not have active otadata.
- */
-int bootloader_common_get_active_otadata(esp_ota_select_entry_t *two_otadata);
-
-/**
- * @brief Returns the number of active otadata.
- *
- * @param[in] two_otadata       Pointer on array from two otadata structures.
- * @param[in] valid_two_otadata Pointer on array from two bools. True means select.
- * @param[in] max               True - will select the maximum ota_seq number, otherwise the minimum.
- *
- * @return The number of active otadata (0 or 1).
- *        - -1: If it does not have active otadata.
- */
-int bootloader_common_select_otadata(const esp_ota_select_entry_t *two_otadata, bool *valid_two_otadata, bool max);
-
-/**
- * @brief Returns esp_app_desc structure for app partition. This structure includes app version.
- *
- * Returns a description for the requested app partition.
- * @param[in] partition      App partition description.
- * @param[out] app_desc      Structure of info about app.
- * @return
- *  - ESP_OK:                Successful.
- *  - ESP_ERR_INVALID_ARG:   The arguments passed are not valid.
- *  - ESP_ERR_NOT_FOUND:     app_desc structure is not found. Magic word is incorrect.
- *  - ESP_FAIL:              mapping is fail.
- */
-esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t *partition, esp_app_desc_t *app_desc);
-
-/**
- * @brief Get chip revision
- *
- * @return Chip revision number
- */
-uint8_t bootloader_common_get_chip_revision(void);
-
-/**
- * @brief Check if the image (bootloader and application) has valid chip ID and revision
- *
- * @param[in] img_hdr: image header
- * @param[in] type: image type, bootloader or application
- * @return
- *      - ESP_OK: image and chip are matched well
- *      - ESP_FAIL: image doesn't match to the chip
- */
-esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type);
-
-/**
- * @brief Configure VDDSDIO, call this API to rise VDDSDIO to 1.9V when VDDSDIO regulator is enabled as 1.8V mode.
- */
-void bootloader_common_vddsdio_configure();
diff --git a/tools/sdk/include/bootloader_support/bootloader_flash_config.h b/tools/sdk/include/bootloader_support/bootloader_flash_config.h
deleted file mode 100644
index 2f716cce2a4..00000000000
--- a/tools/sdk/include/bootloader_support/bootloader_flash_config.h
+++ /dev/null
@@ -1,71 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "esp_image_format.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Update the flash id in g_rom_flashchip(global esp_rom_spiflash_chip_t structure).
- *
- * @return None
- */
-void bootloader_flash_update_id();
-
-/**
- * @brief Set the flash CS setup and hold time.
- *
- * @note CS setup time is recomemded to be 1.5T, and CS hold time is recommended to be 2.5T.
- *       cs_setup = 1, cs_setup_time = 0; cs_hold = 1, cs_hold_time = 1.
- *
- * @return None
- */
-void bootloader_flash_cs_timing_config();
-
-/**
- * @brief Configure SPI flash clock.
- *
- * @note This function only set clock frequency for SPI0.
- *
- * @param pfhdr Pointer to App image header, from where to fetch flash settings.
- *
- * @return None
- */
-void bootloader_flash_clock_config(const esp_image_header_t* pfhdr);
-
-/**
- * @brief Configure SPI flash gpio, include the IO matrix and drive strength configuration.
- *
- * @param pfhdr Pointer to App image header, from where to fetch flash settings.
- *
- * @return None
- */
-void bootloader_flash_gpio_config(const esp_image_header_t* pfhdr);
-
-/**
- * @brief Configure SPI flash read dummy based on different mode and frequency.
- *
- * @param pfhdr Pointer to App image header, from where to fetch flash settings.
- *
- * @return None
- */
-void bootloader_flash_dummy_config(const esp_image_header_t* pfhdr);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/bootloader_support/bootloader_random.h b/tools/sdk/include/bootloader_support/bootloader_random.h
deleted file mode 100644
index bb3b2a81dde..00000000000
--- a/tools/sdk/include/bootloader_support/bootloader_random.h
+++ /dev/null
@@ -1,49 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <stddef.h>
-
-/**
- * @brief Enable early entropy source for RNG
- *
- * Uses the SAR ADC to feed entropy into the HWRNG. The ADC is put
- * into a test mode that reads the 1.1V internal reference source and
- * feeds the LSB of data into the HWRNG.
- *
- * Can also be used from app code early during operation, if entropy
- * is required before WiFi stack is initialised. Call this function
- * from app code only if WiFi/BT are not yet enabled and I2S and SAR
- * ADC are not in use.
- *
- * Call bootloader_random_disable() when done.
- */
-void bootloader_random_enable(void);
-
-/**
- * @brief Disable early entropy source for RNG
- *
- * Disables SAR ADC source and resets the I2S hardware.
- *
- */
-void bootloader_random_disable(void);
-
-/**
- * @brief Fill buffer with 'length' random bytes
- *
- * @param buffer Pointer to buffer
- * @param length This many bytes of random data will be copied to buffer
- */
-void bootloader_fill_random(void *buffer, size_t length);
diff --git a/tools/sdk/include/bootloader_support/bootloader_util.h b/tools/sdk/include/bootloader_support/bootloader_util.h
deleted file mode 100644
index 30f8bd8d2c0..00000000000
--- a/tools/sdk/include/bootloader_support/bootloader_util.h
+++ /dev/null
@@ -1,34 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <stddef.h>
-
-/**
- * @brief Check if half-open intervals overlap
- *
- * @param start1  interval 1 start
- * @param end1    interval 1 end
- * @param start2  interval 2 start
- * @param end2    interval 2 end
- * @return true iff [start1; end1) overlaps [start2; end2)
- */
-static inline bool bootloader_util_regions_overlap(
-        const intptr_t start1, const intptr_t end1,
-        const intptr_t start2, const intptr_t end2)
-{
-    return (end1 > start2 && end2 > start1) ||
-           !(end1 <= start2 || end2 <= start1);
-}
diff --git a/tools/sdk/include/bootloader_support/esp_flash_encrypt.h b/tools/sdk/include/bootloader_support/esp_flash_encrypt.h
deleted file mode 100644
index 59eca33b246..00000000000
--- a/tools/sdk/include/bootloader_support/esp_flash_encrypt.h
+++ /dev/null
@@ -1,117 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __ESP32_FLASH_ENCRYPT_H
-#define __ESP32_FLASH_ENCRYPT_H
-
-#include <stdbool.h>
-#include "esp_attr.h"
-#include "esp_err.h"
-#ifndef BOOTLOADER_BUILD
-#include "esp_spi_flash.h"
-#endif
-#include "soc/efuse_reg.h"
-
-/**
- * @file esp_partition.h
- * @brief Support functions for flash encryption features
- *
- * Can be compiled as part of app or bootloader code.
- */
-
-/** @brief Is flash encryption currently enabled in hardware?
- *
- * Flash encryption is enabled if the FLASH_CRYPT_CNT efuse has an odd number of bits set.
- *
- * @return true if flash encryption is enabled.
- */
-static inline /** @cond */ IRAM_ATTR /** @endcond */ bool esp_flash_encryption_enabled(void) {
-    uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT);
-    /* __builtin_parity is in flash, so we calculate parity inline */
-    bool enabled = false;
-    while(flash_crypt_cnt) {
-        if (flash_crypt_cnt & 1) {
-            enabled = !enabled;
-        }
-        flash_crypt_cnt >>= 1;
-    }
-    return enabled;
-}
-
-/* @brief Update on-device flash encryption
- *
- * Intended to be called as part of the bootloader process if flash
- * encryption is enabled in device menuconfig.
- *
- * If FLASH_CRYPT_CNT efuse parity is 1 (ie odd number of bits set),
- * then return ESP_OK immediately (indicating flash encryption is enabled
- * and functional).
- *
- * If FLASH_CRYPT_CNT efuse parity is 0 (ie even number of bits set),
- * assume the flash has just been written with plaintext that needs encrypting.
- *
- * The following regions of flash are encrypted in place:
- *
- * - The bootloader image, if a valid plaintext image is found.[*]
- * - The partition table, if a valid plaintext table is found.
- * - Any app partition that contains a valid plaintext app image.
- * - Any other partitions with the "encrypt" flag set. [**]
- *
- * After the re-encryption process completes, a '1' bit is added to the
- * FLASH_CRYPT_CNT value (setting the parity to 1) and the EFUSE is re-burned.
- *
- * [*] If reflashing bootloader with secure boot enabled, pre-encrypt
- * the bootloader before writing it to flash or secure boot will fail.
- *
- * [**] For this reason, if serial re-flashing a previous flashed
- * device with secure boot enabled and using FLASH_CRYPT_CNT to
- * trigger re-encryption, you must simultaneously re-flash plaintext
- * content to all partitions with the "encrypt" flag set or this
- * data will be corrupted (encrypted twice).
- *
- * @note The post-condition of this function is that all
- * partitions that should be encrypted are encrypted.
- *
- * @note Take care not to power off the device while this function
- * is running, or the partition currently being encrypted will be lost.
- *
- * @note RTC_WDT will reset while encryption operations will be performed (if RTC_WDT is configured).
- *
- * @return ESP_OK if all operations succeeded, ESP_ERR_INVALID_STATE
- * if a fatal error occured during encryption of all partitions.
- */
-esp_err_t esp_flash_encrypt_check_and_update(void);
-
-
-/** @brief Encrypt-in-place a block of flash sectors
- *
- * @note This function resets RTC_WDT between operations with sectors.
- * @param src_addr Source offset in flash. Should be multiple of 4096 bytes.
- * @param data_length Length of data to encrypt in bytes. Will be rounded up to next multiple of 4096 bytes.
- *
- * @return ESP_OK if all operations succeeded, ESP_ERR_FLASH_OP_FAIL
- * if SPI flash fails, ESP_ERR_FLASH_OP_TIMEOUT if flash times out.
- */
-esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length);
-
-/** @brief Write protect FLASH_CRYPT_CNT
- *
- * Intended to be called as a part of boot process if flash encryption
- * is enabled but secure boot is not used. This should protect against
- * serial re-flashing of an unauthorised code in absence of secure boot.
- *
- * @return 
- */
-void esp_flash_write_protect_crypt_cnt();
-
-#endif
diff --git a/tools/sdk/include/bootloader_support/esp_flash_partitions.h b/tools/sdk/include/bootloader_support/esp_flash_partitions.h
deleted file mode 100644
index b5f37aa5fc6..00000000000
--- a/tools/sdk/include/bootloader_support/esp_flash_partitions.h
+++ /dev/null
@@ -1,47 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __ESP_FLASH_PARTITIONS_H
-#define __ESP_FLASH_PARTITIONS_H
-
-#include "esp_err.h"
-#include "esp_flash_data_types.h"
-#include <stdbool.h>
-#include "sdkconfig.h"
-
-/* Pre-partition table fixed flash offsets */
-#define ESP_BOOTLOADER_DIGEST_OFFSET 0x0
-#define ESP_BOOTLOADER_OFFSET 0x1000 /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */
-#define ESP_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. Backwards-compatible name.*/
-
-#define ESP_PARTITION_TABLE_MAX_LEN 0xC00 /* Maximum length of partition table data */
-#define ESP_PARTITION_TABLE_MAX_ENTRIES (ESP_PARTITION_TABLE_MAX_LEN / sizeof(esp_partition_info_t)) /* Maximum length of partition table data, including terminating entry */
-
-/* @brief Verify the partition table
- *
- * @param partition_table Pointer to at least ESP_PARTITION_TABLE_MAX_ENTRIES of potential partition table data. (ESP_PARTITION_TABLE_MAX_LEN bytes.)
- * @param log_errors Log errors if the partition table is invalid.
- * @param num_partitions If result is ESP_OK, num_partitions is updated with total number of partitions (not including terminating entry).
- *
- * @return ESP_OK on success, ESP_ERR_INVALID_STATE if partition table is not valid.
- */
-esp_err_t esp_partition_table_verify(const esp_partition_info_t *partition_table, bool log_errors, int *num_partitions);
-
-
-/* This function is included for compatibility with the ESP-IDF v3.x API */
-inline static __attribute__((deprecated)) esp_err_t esp_partition_table_basic_verify(const esp_partition_info_t *partition_table, bool log_errors, int *num_partitions)
-{
-    return esp_partition_table_verify(partition_table, log_errors, num_partitions);
-}
-
-#endif
diff --git a/tools/sdk/include/bootloader_support/esp_image_format.h b/tools/sdk/include/bootloader_support/esp_image_format.h
deleted file mode 100644
index fe6cf89bd2f..00000000000
--- a/tools/sdk/include/bootloader_support/esp_image_format.h
+++ /dev/null
@@ -1,256 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include <stdbool.h>
-#include <esp_err.h>
-#include "esp_flash_partitions.h"
-
-#define ESP_ERR_IMAGE_BASE       0x2000
-#define ESP_ERR_IMAGE_FLASH_FAIL (ESP_ERR_IMAGE_BASE + 1)
-#define ESP_ERR_IMAGE_INVALID    (ESP_ERR_IMAGE_BASE + 2)
-
-/* Support for app/bootloader image parsing
-   Can be compiled as part of app or bootloader code.
-*/
-
-/* SPI flash mode, used in esp_image_header_t */
-typedef enum {
-    ESP_IMAGE_SPI_MODE_QIO,
-    ESP_IMAGE_SPI_MODE_QOUT,
-    ESP_IMAGE_SPI_MODE_DIO,
-    ESP_IMAGE_SPI_MODE_DOUT,
-    ESP_IMAGE_SPI_MODE_FAST_READ,
-    ESP_IMAGE_SPI_MODE_SLOW_READ
-} esp_image_spi_mode_t;
-
-/* SPI flash clock frequency */
-typedef enum {
-    ESP_IMAGE_SPI_SPEED_40M,
-    ESP_IMAGE_SPI_SPEED_26M,
-    ESP_IMAGE_SPI_SPEED_20M,
-    ESP_IMAGE_SPI_SPEED_80M = 0xF
-} esp_image_spi_freq_t;
-
-/* Supported SPI flash sizes */
-typedef enum {
-    ESP_IMAGE_FLASH_SIZE_1MB = 0,
-    ESP_IMAGE_FLASH_SIZE_2MB,
-    ESP_IMAGE_FLASH_SIZE_4MB,
-    ESP_IMAGE_FLASH_SIZE_8MB,
-    ESP_IMAGE_FLASH_SIZE_16MB,
-    ESP_IMAGE_FLASH_SIZE_MAX
-} esp_image_flash_size_t;
-
-#define ESP_IMAGE_HEADER_MAGIC 0xE9
-
-/**
- * @brief ESP chip ID
- *
- */
-typedef enum {
-    ESP_CHIP_ID_ESP32 = 0x0000,  /*!< chip ID: ESP32 */
-    ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
-} __attribute__((packed)) esp_chip_id_t;
-
-/** @cond */
-_Static_assert(sizeof(esp_chip_id_t) == 2, "esp_chip_id_t should be 16 bit");
-/** @endcond */
-
-/* Main header of binary image */
-typedef struct {
-    uint8_t magic;
-    uint8_t segment_count;
-    /* flash read mode (esp_image_spi_mode_t as uint8_t) */
-    uint8_t spi_mode;
-    /* flash frequency (esp_image_spi_freq_t as uint8_t) */
-    uint8_t spi_speed: 4;
-    /* flash chip size (esp_image_flash_size_t as uint8_t) */
-    uint8_t spi_size: 4;
-    uint32_t entry_addr;
-    /* WP pin when SPI pins set via efuse (read by ROM bootloader, the IDF bootloader uses software to configure the WP
-     * pin and sets this field to 0xEE=disabled) */
-    uint8_t wp_pin;
-    /* Drive settings for the SPI flash pins (read by ROM bootloader) */
-    uint8_t spi_pin_drv[3];
-    esp_chip_id_t chip_id; /*!< Chip identification number */
-    uint8_t min_chip_rev;  /*!< Minimum chip revision supported by image */
-    uint8_t reserved[8];   /*!< Reserved bytes in additional header space, currently unused */
-    /* If 1, a SHA256 digest "simple hash" (of the entire image) is appended after the checksum. Included in image length. This digest
-     * is separate to secure boot and only used for detecting corruption. For secure boot signed images, the signature
-     * is appended after this (and the simple hash is included in the signed data). */
-    uint8_t hash_appended;
-} __attribute__((packed))  esp_image_header_t;
-
-_Static_assert(sizeof(esp_image_header_t) == 24, "binary image header should be 24 bytes");
-
-#define ESP_IMAGE_HASH_LEN 32 /* Length of the appended SHA-256 digest */
-
-/* Header of binary image segment */
-typedef struct {
-    uint32_t load_addr;
-    uint32_t data_len;
-} esp_image_segment_header_t;
-
-#define ESP_APP_DESC_MAGIC_WORD 0xABCD5432 /*!< The magic word for the esp_app_desc structure that is in DROM. */
-
-/**
- * @brief Description about application.
- */
-typedef struct {
-    uint32_t magic_word;        /*!< Magic word ESP_APP_DESC_MAGIC_WORD */
-    uint32_t secure_version;    /*!< Secure version */
-    uint32_t reserv1[2];        /*!< --- */
-    char version[32];           /*!< Application version */
-    char project_name[32];      /*!< Project name */
-    char time[16];              /*!< Compile time */
-    char date[16];              /*!< Compile date*/
-    char idf_ver[32];           /*!< Version IDF */
-    uint8_t app_elf_sha256[32]; /*!< sha256 of elf file */
-    uint32_t reserv2[20];       /*!< --- */
-} esp_app_desc_t;
-_Static_assert(sizeof(esp_app_desc_t) == 256, "esp_app_desc_t should be 256 bytes");
-
-#define ESP_IMAGE_MAX_SEGMENTS 16
-
-/* Structure to hold on-flash image metadata */
-typedef struct {
-  uint32_t start_addr;   /* Start address of image */
-  esp_image_header_t image; /* Header for entire image */
-  esp_image_segment_header_t segments[ESP_IMAGE_MAX_SEGMENTS]; /* Per-segment header data */
-  uint32_t segment_data[ESP_IMAGE_MAX_SEGMENTS]; /* Data offsets for each segment */
-  uint32_t image_len; /* Length of image on flash, in bytes */
-  uint8_t image_digest[32]; /* appended SHA-256 digest */
-} esp_image_metadata_t;
-
-/* Mode selection for esp_image_load() */
-typedef enum {
-    ESP_IMAGE_VERIFY,        /* Verify image contents, load metadata. Print errors. */
-    ESP_IMAGE_VERIFY_SILENT, /* Verify image contents, load metadata. Don't print errors. */
-#ifdef BOOTLOADER_BUILD
-    ESP_IMAGE_LOAD,          /* Verify image contents, load to memory. Print errors. */
-#endif
-} esp_image_load_mode_t;
-
-/**
- * @brief Verify and (optionally, in bootloader mode) load an app image.
- *
- * This name is deprecated and is included for compatibility with the ESP-IDF v3.x API.
- * It will be removed in V4.0 version.
- * Function has been renamed to esp_image_verify().
- * Use function esp_image_verify() to verify a image. And use function bootloader_load_image() to load image from a bootloader space.
- *
- * If encryption is enabled, data will be transparently decrypted.
- *
- * @param mode Mode of operation (verify, silent verify, or load).
- * @param part Partition to load the app from.
- * @param[inout] data Pointer to the image metadata structure which is be filled in by this function. 'start_addr' member should be set (to the start address of the image.) Other fields will all be initialised by this function.
- *
- * Image validation checks:
- * - Magic byte.
- * - Partition smaller than 16MB.
- * - All segments & image fit in partition.
- * - 8 bit image checksum is valid.
- * - SHA-256 of image is valid (if image has this appended).
- * - (Signature) if signature verification is enabled.
- *
- * @return
- * - ESP_OK if verify or load was successful
- * - ESP_ERR_IMAGE_FLASH_FAIL if a SPI flash error occurs
- * - ESP_ERR_IMAGE_INVALID if the image appears invalid.
- * - ESP_ERR_INVALID_ARG if the partition or data pointers are invalid.
- */
-esp_err_t esp_image_load(esp_image_load_mode_t mode, const esp_partition_pos_t *part, esp_image_metadata_t *data) __attribute__((deprecated));
-
-/**
- * @brief Verify an app image.
- *
- * If encryption is enabled, data will be transparently decrypted.
- *
- * @param mode Mode of operation (verify, silent verify, or load).
- * @param part Partition to load the app from.
- * @param[inout] data Pointer to the image metadata structure which is be filled in by this function.
- *                    'start_addr' member should be set (to the start address of the image.)
- *                    Other fields will all be initialised by this function.
- *
- * Image validation checks:
- * - Magic byte.
- * - Partition smaller than 16MB.
- * - All segments & image fit in partition.
- * - 8 bit image checksum is valid.
- * - SHA-256 of image is valid (if image has this appended).
- * - (Signature) if signature verification is enabled.
- *
- * @return
- * - ESP_OK if verify or load was successful
- * - ESP_ERR_IMAGE_FLASH_FAIL if a SPI flash error occurs
- * - ESP_ERR_IMAGE_INVALID if the image appears invalid.
- * - ESP_ERR_INVALID_ARG if the partition or data pointers are invalid.
- */
-esp_err_t esp_image_verify(esp_image_load_mode_t mode, const esp_partition_pos_t *part, esp_image_metadata_t *data);
-
-/**
- * @brief Verify and load an app image (available only in space of bootloader).
- *
- * If encryption is enabled, data will be transparently decrypted.
- *
- * @param part Partition to load the app from.
- * @param[inout] data Pointer to the image metadata structure which is be filled in by this function.
- *                    'start_addr' member should be set (to the start address of the image.)
- *                    Other fields will all be initialised by this function.
- *
- * Image validation checks:
- * - Magic byte.
- * - Partition smaller than 16MB.
- * - All segments & image fit in partition.
- * - 8 bit image checksum is valid.
- * - SHA-256 of image is valid (if image has this appended).
- * - (Signature) if signature verification is enabled.
- *
- * @return
- * - ESP_OK if verify or load was successful
- * - ESP_ERR_IMAGE_FLASH_FAIL if a SPI flash error occurs
- * - ESP_ERR_IMAGE_INVALID if the image appears invalid.
- * - ESP_ERR_INVALID_ARG if the partition or data pointers are invalid.
- */
-esp_err_t bootloader_load_image(const esp_partition_pos_t *part, esp_image_metadata_t *data);
-
-/**
- * @brief Verify the bootloader image.
- *
- * @param[out] If result is ESP_OK and this pointer is non-NULL, it
- * will be set to the length of the bootloader image.
- *
- * @return As per esp_image_load_metadata().
- */
-esp_err_t esp_image_verify_bootloader(uint32_t *length);
-
-/**
- * @brief Verify the bootloader image.
- *
- * @param[out] Metadata for the image. Only valid if result is ESP_OK.
- *
- * @return As per esp_image_load_metadata().
- */
-esp_err_t esp_image_verify_bootloader_data(esp_image_metadata_t *data);
-
-
-typedef struct {
-    uint32_t drom_addr;
-    uint32_t drom_load_addr;
-    uint32_t drom_size;
-    uint32_t irom_addr;
-    uint32_t irom_load_addr;
-    uint32_t irom_size;
-} esp_image_flash_mapping_t;
diff --git a/tools/sdk/include/bootloader_support/esp_secure_boot.h b/tools/sdk/include/bootloader_support/esp_secure_boot.h
deleted file mode 100644
index 17b405e4fab..00000000000
--- a/tools/sdk/include/bootloader_support/esp_secure_boot.h
+++ /dev/null
@@ -1,137 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include <stdbool.h>
-#include <esp_err.h>
-#include "soc/efuse_reg.h"
-
-#include "sdkconfig.h"
-
-#ifdef CONFIG_SECURE_BOOT_ENABLED
-#if !defined(CONFIG_SECURE_SIGNED_ON_BOOT) || !defined(CONFIG_SECURE_SIGNED_ON_UPDATE) || !defined(CONFIG_SECURE_SIGNED_APPS)
-#error "internal sdkconfig error, secure boot should always enable all signature options"
-#endif
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Support functions for secure boot features.
-
-   Can be compiled as part of app or bootloader code.
-*/
-
-/** @brief Is secure boot currently enabled in hardware?
- *
- * Secure boot is enabled if the ABS_DONE_0 efuse is blown. This means
- * that the ROM bootloader code will only boot a verified secure
- * bootloader digest from now on.
- *
- * @return true if secure boot is enabled.
- */
-static inline bool esp_secure_boot_enabled(void) {
-    return REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_RD_ABS_DONE_0;
-}
-
-/** @brief Generate secure digest from bootloader image
- *
- * @important This function is intended to be called from bootloader code only.
- *
- * If secure boot is not yet enabled for bootloader, this will:
- *     1) generate the secure boot key and burn it on EFUSE
- *        (without enabling R/W protection)
- *     2) generate the digest from bootloader and save it
- *        to flash address 0x0
- *
- * If first boot gets interrupted after calling this function
- * but before esp_secure_boot_permanently_enable() is called, then
- * the key burned on EFUSE will not be regenerated, unless manually
- * done using espefuse.py tool
- *
- * @return ESP_OK if secure boot digest is generated
- * successfully or found to be already present
- */
-esp_err_t esp_secure_boot_generate_digest(void);
-
-/** @brief Enable secure boot if it is not already enabled.
- *
- * @important If this function succeeds, secure boot is permanently
- * enabled on the chip via efuse.
- *
- * @important This function is intended to be called from bootloader code only.
- *
- * @important This will enable r/w protection of secure boot key on EFUSE,
- * therefore it is to be ensured that esp_secure_boot_generate_digest()
- * is called before this
- *
- * If secure boot is not yet enabled for bootloader, this will
- *     1) enable R/W protection of secure boot key on EFUSE
- *     2) enable secure boot by blowing the EFUSE_RD_ABS_DONE_0 efuse.
- *
- * This function does not verify secure boot of the bootloader (the
- * ROM bootloader does this.)
- *
- * Will fail if efuses have been part-burned in a way that indicates
- * secure boot should not or could not be correctly enabled.
- *
- * @return ESP_ERR_INVALID_STATE if efuse state doesn't allow
- * secure boot to be enabled cleanly. ESP_OK if secure boot
- * is enabled on this chip from now on.
- */
-esp_err_t esp_secure_boot_permanently_enable(void);
-
-/** @brief Verify the secure boot signature (determinstic ECDSA w/ SHA256) appended to some binary data in flash.
- *
- * Public key is compiled into the calling program. See docs/security/secure-boot.rst for details.
- *
- * @param src_addr Starting offset of the data in flash.
- * @param length Length of data in bytes. Signature is appended -after- length bytes.
- *
- * If flash encryption is enabled, the image will be transparently decrypted while being verified.
- *
- * @return ESP_OK if signature is valid, ESP_ERR_INVALID_STATE if
- * signature fails, ESP_FAIL for other failures (ie can't read flash).
- */
-esp_err_t esp_secure_boot_verify_signature(uint32_t src_addr, uint32_t length);
-
-/** @brief Verify the secure boot signature block (deterministic ECDSA w/ SHA256) based on the SHA256 hash of some data.
- *
- * Similar to esp_secure_boot_verify_signature(), but can be used when the digest is precalculated.
- * @param sig_block Pointer to signature block data
- * @param image_digest Pointer to 32 byte buffer holding SHA-256 hash.
- *
- */
-
-/** @brief Secure boot verification block, on-flash data format. */
-typedef struct {
-    uint32_t version;
-    uint8_t signature[64];
-} esp_secure_boot_sig_block_t;
-
-esp_err_t esp_secure_boot_verify_signature_block(const esp_secure_boot_sig_block_t *sig_block, const uint8_t *image_digest);
-
-#define FLASH_OFFS_SECURE_BOOT_IV_DIGEST 0
-
-/** @brief Secure boot IV+digest header */
-typedef struct {
-    uint8_t iv[128];
-    uint8_t digest[64];
-} esp_secure_boot_iv_digest_t;
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/bt/bt.h b/tools/sdk/include/bt/bt.h
deleted file mode 100644
index a957698fb0c..00000000000
--- a/tools/sdk/include/bt/bt.h
+++ /dev/null
@@ -1,3 +0,0 @@
-#pragma once
-#warning "This header is deprecated, please use functions defined in esp_bt.h instead."
-#include "esp_bt.h"
diff --git a/tools/sdk/include/bt/esp_a2dp_api.h b/tools/sdk/include/bt/esp_a2dp_api.h
deleted file mode 100644
index 96aad492b59..00000000000
--- a/tools/sdk/include/bt/esp_a2dp_api.h
+++ /dev/null
@@ -1,342 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_A2DP_API_H__
-#define __ESP_A2DP_API_H__
-
-#include "esp_err.h"
-#include "esp_bt_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/// Media codec types supported by A2DP
-#define ESP_A2D_MCT_SBC         (0)             /*!< SBC */
-#define ESP_A2D_MCT_M12         (0x01)          /*!< MPEG-1, 2 Audio */
-#define ESP_A2D_MCT_M24         (0x02)          /*!< MPEG-2, 4 AAC */
-#define ESP_A2D_MCT_ATRAC       (0x04)          /*!< ATRAC family */
-#define ESP_A2D_MCT_NON_A2DP    (0xff)
-
-typedef uint8_t esp_a2d_mct_t;
-
-/// A2DP media codec capabilities union
-typedef struct {
-    esp_a2d_mct_t type;                        /*!< A2DP media codec type */
-#define ESP_A2D_CIE_LEN_SBC          (4)
-#define ESP_A2D_CIE_LEN_M12          (4)
-#define ESP_A2D_CIE_LEN_M24          (6)
-#define ESP_A2D_CIE_LEN_ATRAC        (7)
-    union {
-        uint8_t sbc[ESP_A2D_CIE_LEN_SBC];
-        uint8_t m12[ESP_A2D_CIE_LEN_M12];
-        uint8_t m24[ESP_A2D_CIE_LEN_M24];
-        uint8_t atrac[ESP_A2D_CIE_LEN_ATRAC];
-    } cie;                                     /*!< A2DP codec information element */
-} __attribute__((packed)) esp_a2d_mcc_t;
-
-/// Bluetooth A2DP connection states
-typedef enum {
-    ESP_A2D_CONNECTION_STATE_DISCONNECTED = 0, /*!< connection released  */
-    ESP_A2D_CONNECTION_STATE_CONNECTING,       /*!< connecting remote device */
-    ESP_A2D_CONNECTION_STATE_CONNECTED,        /*!< connection established */
-    ESP_A2D_CONNECTION_STATE_DISCONNECTING     /*!< disconnecting remote device */
-} esp_a2d_connection_state_t;
-
-/// Bluetooth A2DP disconnection reason
-typedef enum {
-    ESP_A2D_DISC_RSN_NORMAL = 0,               /*!< Finished disconnection that is initiated by local or remote device */
-    ESP_A2D_DISC_RSN_ABNORMAL                  /*!< Abnormal disconnection caused by signal loss */
-} esp_a2d_disc_rsn_t;
-
-/// Bluetooth A2DP datapath states
-typedef enum {
-    ESP_A2D_AUDIO_STATE_REMOTE_SUSPEND = 0,    /*!< audio stream datapath suspended by remote device */
-    ESP_A2D_AUDIO_STATE_STOPPED,               /*!< audio stream datapath stopped */
-    ESP_A2D_AUDIO_STATE_STARTED,               /*!< audio stream datapath started */
-} esp_a2d_audio_state_t;
-
-/// A2DP media control command acknowledgement code
-typedef enum {
-    ESP_A2D_MEDIA_CTRL_ACK_SUCCESS = 0,        /*!< media control command is acknowledged with success */
-    ESP_A2D_MEDIA_CTRL_ACK_FAILURE,            /*!< media control command is acknowledged with failure */
-    ESP_A2D_MEDIA_CTRL_ACK_BUSY,               /*!< media control command is rejected, as previous command is not yet acknowledged */
-} esp_a2d_media_ctrl_ack_t;
-
-/// A2DP media control commands
-typedef enum {
-    ESP_A2D_MEDIA_CTRL_NONE = 0,               /*!< Not for application use, use inside stack only. */
-    ESP_A2D_MEDIA_CTRL_CHECK_SRC_RDY,          /*!< check whether AVDTP is connected, only used in A2DP source */
-    ESP_A2D_MEDIA_CTRL_START,                  /*!< command to set up media transmission channel */
-    ESP_A2D_MEDIA_CTRL_STOP,                   /*!< command to stop media transmission */
-    ESP_A2D_MEDIA_CTRL_SUSPEND,                /*!< command to suspend media transmission  */
-} esp_a2d_media_ctrl_t;
-
-/// A2DP callback events
-typedef enum {
-    ESP_A2D_CONNECTION_STATE_EVT = 0,          /*!< connection state changed event */
-    ESP_A2D_AUDIO_STATE_EVT,                   /*!< audio stream transmission state changed event */
-    ESP_A2D_AUDIO_CFG_EVT,                     /*!< audio codec is configured, only used for A2DP SINK */
-    ESP_A2D_MEDIA_CTRL_ACK_EVT,                /*!< acknowledge event in response to media control commands */
-} esp_a2d_cb_event_t;
-
-/// A2DP state callback parameters
-typedef union {
-    /**
-     * @brief  ESP_A2D_CONNECTION_STATE_EVT
-     */
-    struct a2d_conn_stat_param {
-        esp_a2d_connection_state_t state;      /*!< one of values from esp_a2d_connection_state_t */
-        esp_bd_addr_t remote_bda;              /*!< remote bluetooth device address */
-        esp_a2d_disc_rsn_t disc_rsn;           /*!< reason of disconnection for "DISCONNECTED" */
-    } conn_stat;                               /*!< A2DP connection status */
-
-    /**
-     * @brief ESP_A2D_AUDIO_STATE_EVT
-     */
-    struct a2d_audio_stat_param {
-        esp_a2d_audio_state_t state;           /*!< one of the values from esp_a2d_audio_state_t */
-        esp_bd_addr_t remote_bda;              /*!< remote bluetooth device address */
-    } audio_stat;                              /*!< audio stream playing state */
-
-    /**
-     * @brief ESP_A2D_AUDIO_CFG_EVT
-     */
-    struct a2d_audio_cfg_param {
-        esp_bd_addr_t remote_bda;              /*!< remote bluetooth device address */
-        esp_a2d_mcc_t mcc;                     /*!< A2DP media codec capability information */
-    } audio_cfg;                               /*!< media codec configuration information */
-
-    /**
-     * @brief ESP_A2D_MEDIA_CTRL_ACK_EVT
-     */
-    struct media_ctrl_stat_param {
-        esp_a2d_media_ctrl_t cmd;              /*!< media control commands to acknowledge */
-        esp_a2d_media_ctrl_ack_t status;       /*!< acknowledgement to media control commands */
-    } media_ctrl_stat;                         /*!< status in acknowledgement to media control commands */
-} esp_a2d_cb_param_t;
-
-/**
- * @brief           A2DP profile callback function type
- *
- * @param           event : Event type
- *
- * @param           param : Pointer to callback parameter
- */
-typedef void (* esp_a2d_cb_t)(esp_a2d_cb_event_t event, esp_a2d_cb_param_t *param);
-
-/**
- * @brief           A2DP profile data callback function
- * @param[in]       buf : data received from A2DP source device and is PCM format decoder from SBC decoder;
- *                  buf references to a static memory block and can be overwritten by upcoming data
- * @param[in]       len : size(in bytes) in buf
- */
-typedef void (* esp_a2d_sink_data_cb_t)(const uint8_t *buf, uint32_t len);
-
-/**
- * @brief           A2DP source data read callback function
- *
- * @param[in]       buf : buffer to be filled with PCM data stream from higher layer
- *
- * @param[in]       len : size(in bytes) of data block to be copied to buf. -1 is an indication to user
- *                  that data buffer shall be flushed
- *
- * @return          size of bytes read successfully, if the argument len is -1, this value is ignored.
- *
- */
-typedef int32_t (* esp_a2d_source_data_cb_t)(uint8_t *buf, int32_t len);
-
-/**
- * @brief           Register application callback function to A2DP module. This function should be called
- *                  only after esp_bluedroid_enable() completes successfully, used by both A2DP source
- *                  and sink.
- *
- * @param[in]       callback: A2DP event callback function
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: if callback is a NULL function pointer
- *
- */
-esp_err_t esp_a2d_register_callback(esp_a2d_cb_t callback);
-
-
-/**
- * @brief           Register A2DP sink data output function; For now the output is PCM data stream decoded
- *                  from SBC format. This function should be called only after esp_bluedroid_enable()
- *                  completes successfully, used only by A2DP sink. The callback is invoked in the context
- *                  of A2DP sink task whose stack size is configurable through menuconfig
- *
- * @param[in]       callback: A2DP sink data callback function
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: if callback is a NULL function pointer
- *
- */
-esp_err_t esp_a2d_sink_register_data_callback(esp_a2d_sink_data_cb_t callback);
-
-
-/**
- *
- * @brief           Initialize the bluetooth A2DP sink module. This function should be called
- *                  after esp_bluedroid_enable() completes successfully
- *
- * @return
- *                  - ESP_OK: if the initialization request is sent successfully
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_a2d_sink_init(void);
-
-
-/**
- *
- * @brief           De-initialize for A2DP sink module. This function
- *                  should be called only after esp_bluedroid_enable() completes successfully
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_a2d_sink_deinit(void);
-
-
-/**
- *
- * @brief           Connect to remote bluetooth A2DP source device, must after esp_a2d_sink_init()
- *
- * @param[in]       remote_bda: remote bluetooth device address
- *
- * @return
- *                  - ESP_OK: connect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_a2d_sink_connect(esp_bd_addr_t remote_bda);
-
-
-/**
- *
- * @brief           Disconnect from the remote A2DP source device
- *
- * @param[in]       remote_bda: remote bluetooth device address
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_a2d_sink_disconnect(esp_bd_addr_t remote_bda);
-
-
-/**
- *
- * @brief           media control commands; this API can be used for both A2DP sink and source
- *
- * @param[in]       ctrl: control commands for A2DP data channel
- * @return
- *                  - ESP_OK: control command is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_a2d_media_ctrl(esp_a2d_media_ctrl_t ctrl);
-
-
-/**
- *
- * @brief           Initialize the bluetooth A2DP source module. This function should be called
- *                  after esp_bluedroid_enable() completes successfully
- *
- * @return
- *                  - ESP_OK: if the initialization request is sent successfully
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_a2d_source_init(void);
-
-
-/**
- *
- * @brief           De-initialize for A2DP source module. This function
- *                  should be called only after esp_bluedroid_enable() completes successfully
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_a2d_source_deinit(void);
-
-
-/**
- * @brief           Register A2DP source data input function; For now the input is PCM data stream.
- *                  This function should be called only after esp_bluedroid_enable() completes
- *                  successfully. The callback is invoked in the context of A2DP source task whose
- *                  stack size is configurable through menuconfig
- *
- * @param[in]       callback: A2DP source data callback function
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: if callback is a NULL function pointer
- *
- */
-esp_err_t esp_a2d_source_register_data_callback(esp_a2d_source_data_cb_t callback);
-
-
-/**
- *
- * @brief           Connect to remote A2DP sink device, must after esp_a2d_source_init()
- *
- * @param[in]       remote_bda: remote bluetooth device address
- *
- * @return
- *                  - ESP_OK: connect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_a2d_source_connect(esp_bd_addr_t remote_bda);
-
-
-/**
- *
- * @brief           Disconnect from the remote A2DP sink device
- *
- * @param[in]       remote_bda: remote bluetooth device address
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_a2d_source_disconnect(esp_bd_addr_t remote_bda);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __ESP_A2DP_API_H__ */
diff --git a/tools/sdk/include/bt/esp_avrc_api.h b/tools/sdk/include/bt/esp_avrc_api.h
deleted file mode 100644
index e1f68392c86..00000000000
--- a/tools/sdk/include/bt/esp_avrc_api.h
+++ /dev/null
@@ -1,288 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_AVRC_API_H__
-#define __ESP_AVRC_API_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-#include "esp_bt_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/// AVRC feature bit mask
-typedef enum {
-    ESP_AVRC_FEAT_RCTG = 0x0001,                 /*!< remote control target */
-    ESP_AVRC_FEAT_RCCT = 0x0002,                 /*!< remote control controller */
-    ESP_AVRC_FEAT_VENDOR = 0x0008,               /*!< remote control vendor dependent commands */
-    ESP_AVRC_FEAT_BROWSE = 0x0010,               /*!< use browsing channel */
-    ESP_AVRC_FEAT_META_DATA = 0x0040,            /*!< remote control metadata transfer command/response */
-    ESP_AVRC_FEAT_ADV_CTRL = 0x0200,             /*!< remote control advanced control commmand/response */
-} esp_avrc_features_t;
-
-/// AVRC passthrough command code
-typedef enum {
-    ESP_AVRC_PT_CMD_PLAY = 0x44,                 /*!< play */
-    ESP_AVRC_PT_CMD_STOP = 0x45,                 /*!< stop */
-    ESP_AVRC_PT_CMD_PAUSE = 0x46,                /*!< pause */
-    ESP_AVRC_PT_CMD_FORWARD = 0x4B,              /*!< forward */
-    ESP_AVRC_PT_CMD_BACKWARD = 0x4C,             /*!< backward */
-    ESP_AVRC_PT_CMD_REWIND = 0x48,               /*!< rewind */
-    ESP_AVRC_PT_CMD_FAST_FORWARD = 0x49          /*!< fast forward */
-} esp_avrc_pt_cmd_t;
-
-/// AVRC passthrough command state
-typedef enum {
-    ESP_AVRC_PT_CMD_STATE_PRESSED = 0,           /*!< key pressed */
-    ESP_AVRC_PT_CMD_STATE_RELEASED = 1           /*!< key released */
-} esp_avrc_pt_cmd_state_t;
-
-/// AVRC Controller callback events
-typedef enum {
-    ESP_AVRC_CT_CONNECTION_STATE_EVT = 0,        /*!< connection state changed event */
-    ESP_AVRC_CT_PASSTHROUGH_RSP_EVT = 1,         /*!< passthrough response event */
-    ESP_AVRC_CT_METADATA_RSP_EVT = 2,            /*!< metadata response event */
-    ESP_AVRC_CT_PLAY_STATUS_RSP_EVT = 3,         /*!< play status response event */
-    ESP_AVRC_CT_CHANGE_NOTIFY_EVT = 4,           /*!< notification event */
-    ESP_AVRC_CT_REMOTE_FEATURES_EVT = 5,         /*!< feature of remote device indication event */
-} esp_avrc_ct_cb_event_t;
-
-/// AVRC metadata attribute mask
-typedef enum {
-    ESP_AVRC_MD_ATTR_TITLE = 0x1,                 /*!< title of the playing track */
-    ESP_AVRC_MD_ATTR_ARTIST = 0x2,                /*!< track artist */
-    ESP_AVRC_MD_ATTR_ALBUM = 0x4,                 /*!< album name */
-    ESP_AVRC_MD_ATTR_TRACK_NUM = 0x8,             /*!< track position on the album */
-    ESP_AVRC_MD_ATTR_NUM_TRACKS = 0x10,           /*!< number of tracks on the album */
-    ESP_AVRC_MD_ATTR_GENRE = 0x20,                /*!< track genre */
-    ESP_AVRC_MD_ATTR_PLAYING_TIME = 0x40          /*!< total album playing time in miliseconds */
-} esp_avrc_md_attr_mask_t;
-
-/// AVRC event notification ids
-typedef enum {
-    ESP_AVRC_RN_PLAY_STATUS_CHANGE = 0x01,        /*!< track status change, eg. from playing to paused */
-    ESP_AVRC_RN_TRACK_CHANGE = 0x02,              /*!< new track is loaded */
-    ESP_AVRC_RN_TRACK_REACHED_END = 0x03,         /*!< current track reached end */
-    ESP_AVRC_RN_TRACK_REACHED_START = 0x04,       /*!< current track reached start position */
-    ESP_AVRC_RN_PLAY_POS_CHANGED = 0x05,          /*!< track playing position changed */
-    ESP_AVRC_RN_BATTERY_STATUS_CHANGE = 0x06,     /*!< battery status changed */
-    ESP_AVRC_RN_SYSTEM_STATUS_CHANGE = 0x07,      /*!< system status changed */
-    ESP_AVRC_RN_APP_SETTING_CHANGE = 0x08,        /*!< application settings changed */
-    ESP_AVRC_RN_MAX_EVT
-} esp_avrc_rn_event_ids_t;
-
-/// AVRC player setting ids
-typedef enum {
-    ESP_AVRC_PS_EQUALIZER = 0x01,                 /*!< equalizer, on or off */
-    ESP_AVRC_PS_REPEAT_MODE = 0x02,               /*!< repeat mode */
-    ESP_AVRC_PS_SHUFFLE_MODE = 0x03,              /*!< shuffle mode */
-    ESP_AVRC_PS_SCAN_MODE = 0x04,                 /*!< scan mode on or off */
-    ESP_AVRC_PS_MAX_ATTR
-} esp_avrc_ps_attr_ids_t;
-
-/// AVRC equalizer modes
-typedef enum {
-    ESP_AVRC_PS_EQUALIZER_OFF = 0x1,              /*!< equalizer OFF */
-    ESP_AVRC_PS_EQUALIZER_ON = 0x2                /*!< equalizer ON */
-} esp_avrc_ps_eq_value_ids_t;
-
-/// AVRC repeat modes
-typedef enum {
-    ESP_AVRC_PS_REPEAT_OFF = 0x1,                 /*!< repeat mode off */
-    ESP_AVRC_PS_REPEAT_SINGLE = 0x2,              /*!< single track repeat */
-    ESP_AVRC_PS_REPEAT_GROUP = 0x3                /*!< group repeat */
-} esp_avrc_ps_rpt_value_ids_t;
-
-
-/// AVRC shuffle modes
-typedef enum {
-    ESP_AVRC_PS_SHUFFLE_OFF = 0x1,                /*<! shuffle off */
-    ESP_AVRC_PS_SHUFFLE_ALL = 0x2,                /*<! shuffle all tracks */
-    ESP_AVRC_PS_SHUFFLE_GROUP = 0x3               /*<! group shuffle */
-} esp_avrc_ps_shf_value_ids_t;
-
-/// AVRC scan modes
-typedef enum {
-    ESP_AVRC_PS_SCAN_OFF = 0x1,                   /*!< scan off */
-    ESP_AVRC_PS_SCAN_ALL = 0x2,                   /*!< all tracks scan */
-    ESP_AVRC_PS_SCAN_GROUP = 0x3                  /*!< group scan */
-} esp_avrc_ps_scn_value_ids_t;
-
-/// AVRC controller callback parameters
-typedef union {
-    /**
-     * @brief ESP_AVRC_CT_CONNECTION_STATE_EVT
-     */
-    struct avrc_ct_conn_stat_param {
-        bool connected;                          /*!< whether AVRC connection is set up */
-        esp_bd_addr_t remote_bda;                /*!< remote bluetooth device address */
-    } conn_stat;                                 /*!< AVRC connection status */
-
-    /**
-     * @brief ESP_AVRC_CT_PASSTHROUGH_RSP_EVT
-     */
-    struct avrc_ct_psth_rsp_param {
-        uint8_t tl;                              /*!< transaction label, 0 to 15 */
-        uint8_t key_code;                        /*!< passthrough command code */
-        uint8_t key_state;                       /*!< 0 for PRESSED, 1 for RELEASED */
-    } psth_rsp;                                  /*!< passthrough command response */
-
-    /**
-     * @brief ESP_AVRC_CT_METADATA_RSP_EVT
-     */
-    struct avrc_ct_meta_rsp_param {
-        uint8_t attr_id;                         /*!< id of metadata attribute */
-        uint8_t *attr_text;                      /*!< attribute itself */
-        int attr_length;                         /*!< attribute character length */
-    } meta_rsp;                                  /*!< metadata attributes response */
-
-    /**
-     * @brief ESP_AVRC_CT_CHANGE_NOTIFY_EVT
-     */
-    struct avrc_ct_change_notify_param {
-        uint8_t event_id;                        /*!< id of AVRC event notification */
-        uint32_t event_parameter;                /*!< event notification parameter */
-    } change_ntf;                                /*!< notifications */
-
-    /**
-     * @brief ESP_AVRC_CT_REMOTE_FEATURES_EVT
-     */
-    struct avrc_ct_rmt_feats_param {
-        uint32_t feat_mask;                      /*!< AVRC feature mask of remote device */
-        esp_bd_addr_t remote_bda;                /*!< remote bluetooth device address */
-    } rmt_feats;                                 /*!< AVRC features discovered from remote SDP server */
-    
-} esp_avrc_ct_cb_param_t;
-
-
-/**
- * @brief           AVRCP controller callback function type
- * @param           event : Event type
- * @param           param : Pointer to callback parameter union
- */
-typedef void (* esp_avrc_ct_cb_t)(esp_avrc_ct_cb_event_t event, esp_avrc_ct_cb_param_t *param);
-
-
-/**
- * @brief           Register application callbacks to AVRCP module; for now only AVRCP Controller
- *                  role is supported. This function should be called after esp_bluedroid_enable()
- *                  completes successfully
- *
- * @param[in]       callback: AVRCP controller callback function
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_avrc_ct_register_callback(esp_avrc_ct_cb_t callback);
-
-
-/**
- *
- * @brief           Initialize the bluetooth AVRCP controller module, This function should be called
- *                  after esp_bluedroid_enable() completes successfully
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_avrc_ct_init(void);
-
-
-/**
- *
- * @brief           De-initialize AVRCP controller module. This function should be called after
- *                  after esp_bluedroid_enable() completes successfully
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_avrc_ct_deinit(void);
-
-/**
- *
- * @brief           Send player application settings command to AVRCP target. This function should be called
- *                  after ESP_AVRC_CT_CONNECTION_STATE_EVT is received and AVRCP connection is established.
- *
- * @param[in]       tl : transaction label, 0 to 15, consecutive commands should use different values.
- * @param[in]       attr_id : player application setting attribute IDs from one of esp_avrc_ps_attr_ids_t
- * @param[in]       value_id : attribute value defined for the specific player application setting attribute
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_avrc_ct_send_set_player_value_cmd(uint8_t tl, uint8_t attr_id, uint8_t value_id);
-
-/**
- * @brief           Send register notification command to AVRCP target, This function should be called after
- *                  ESP_AVRC_CT_CONNECTION_STATE_EVT is received and AVRCP connection is established
- *
- * @param[in]       tl : transaction label, 0 to 15, consecutive commands should use different values.
- * @param[in]       event_id : id of events, e.g. ESP_AVRC_RN_PLAY_STATUS_CHANGE, ESP_AVRC_RN_TRACK_CHANGE, etc.
- * @param[in]       event_parameter : special parameters, eg. playback interval for ESP_AVRC_RN_PLAY_POS_CHANGED
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_avrc_ct_send_register_notification_cmd(uint8_t tl, uint8_t event_id, uint32_t event_parameter);
-
-
-/**
- * @brief           Send metadata command to AVRCP target, This function should be called after
- *                  ESP_AVRC_CT_CONNECTION_STATE_EVT is received and AVRCP connection is established
- *
- * @param[in]       tl : transaction label, 0 to 15, consecutive commands should use different values.
- * @param[in]       attr_mask : mask of attributes, e.g. ESP_AVRC_MD_ATTR_ID_TITLE | ESP_AVRC_MD_ATTR_ID_ARTIST.
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_avrc_ct_send_metadata_cmd(uint8_t tl, uint8_t attr_mask);
-
-
-/**
- * @brief           Send passthrough command to AVRCP target, This function should be called after
- *                  ESP_AVRC_CT_CONNECTION_STATE_EVT is received and AVRCP connection is established
- *
- * @param[in]       tl : transaction label, 0 to 15, consecutive commands should use different values.
- * @param[in]       key_code : passthrough command code, e.g. ESP_AVRC_PT_CMD_PLAY, ESP_AVRC_PT_CMD_STOP, etc.
- * @param[in]       key_state : passthrough command key state, ESP_AVRC_PT_CMD_STATE_PRESSED or
- *                  ESP_AVRC_PT_CMD_STATE_RELEASED
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_avrc_ct_send_passthrough_cmd(uint8_t tl, uint8_t key_code, uint8_t key_state);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_AVRC_API_H__ */
diff --git a/tools/sdk/include/bt/esp_blufi_api.h b/tools/sdk/include/bt/esp_blufi_api.h
deleted file mode 100644
index f17fcbc2282..00000000000
--- a/tools/sdk/include/bt/esp_blufi_api.h
+++ /dev/null
@@ -1,442 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_BLUFI_API_H__
-#define __ESP_BLUFI_API_H__
-
-#include "esp_bt_defs.h"
-#include "esp_gatt_defs.h"
-#include "esp_err.h"
-#include "esp_wifi_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ESP_BLUFI_EVENT_INIT_FINISH = 0,                     /*<! When BLUFI init complete, this event happen */
-    ESP_BLUFI_EVENT_DEINIT_FINISH,                       /*<! When BLUFI deinit complete, this event happen */
-    ESP_BLUFI_EVENT_SET_WIFI_OPMODE,                     /*<! When Phone set ESP32 wifi operation mode(AP/STA/AP_STA), this event happen */
-    ESP_BLUFI_EVENT_BLE_CONNECT,                         /*<! When Phone connect to ESP32 with BLE, this event happen */
-    ESP_BLUFI_EVENT_BLE_DISCONNECT,                      /*<! When Phone disconnect with BLE, this event happen */
-    ESP_BLUFI_EVENT_REQ_CONNECT_TO_AP,                   /*<! When Phone request ESP32's STA connect to AP, this event happen */
-    ESP_BLUFI_EVENT_REQ_DISCONNECT_FROM_AP,              /*<! When Phone request ESP32's STA disconnect from AP, this event happen */
-    ESP_BLUFI_EVENT_GET_WIFI_STATUS,                     /*<! When Phone get ESP32 wifi status, this event happen */
-    ESP_BLUFI_EVENT_DEAUTHENTICATE_STA,                  /*<! When Phone deauthenticate sta from SOFTAP, this event happen */
-    /* recv data */
-    ESP_BLUFI_EVENT_RECV_STA_BSSID,                      /*<! When Phone send STA BSSID to ESP32 to connect, this event happen */
-    ESP_BLUFI_EVENT_RECV_STA_SSID,                       /*<! When Phone send STA SSID to ESP32 to connect, this event happen */
-    ESP_BLUFI_EVENT_RECV_STA_PASSWD,                     /*<! When Phone send STA PASSWORD to ESP32 to connect, this event happen */
-    ESP_BLUFI_EVENT_RECV_SOFTAP_SSID,                    /*<! When Phone send SOFTAP SSID to ESP32 to start SOFTAP, this event happen */
-    ESP_BLUFI_EVENT_RECV_SOFTAP_PASSWD,                  /*<! When Phone send SOFTAP PASSWORD to ESP32 to start SOFTAP, this event happen */
-    ESP_BLUFI_EVENT_RECV_SOFTAP_MAX_CONN_NUM,            /*<! When Phone send SOFTAP max connection number to ESP32 to start SOFTAP, this event happen */
-    ESP_BLUFI_EVENT_RECV_SOFTAP_AUTH_MODE,               /*<! When Phone send SOFTAP authentication mode to ESP32 to start SOFTAP, this event happen */
-    ESP_BLUFI_EVENT_RECV_SOFTAP_CHANNEL,                 /*<! When Phone send SOFTAP channel to ESP32 to start SOFTAP, this event happen */
-    ESP_BLUFI_EVENT_RECV_USERNAME,                       /*<! When Phone send username to ESP32, this event happen */
-    ESP_BLUFI_EVENT_RECV_CA_CERT,                        /*<! When Phone send CA certificate to ESP32, this event happen */
-    ESP_BLUFI_EVENT_RECV_CLIENT_CERT,                    /*<! When Phone send Client certificate to ESP32, this event happen */
-    ESP_BLUFI_EVENT_RECV_SERVER_CERT,                    /*<! When Phone send Server certificate to ESP32, this event happen */
-    ESP_BLUFI_EVENT_RECV_CLIENT_PRIV_KEY,                /*<! When Phone send Client Private key to ESP32, this event happen */
-    ESP_BLUFI_EVENT_RECV_SERVER_PRIV_KEY,                /*<! When Phone send Server Private key to ESP32, this event happen */
-    ESP_BLUFI_EVENT_RECV_SLAVE_DISCONNECT_BLE,           /*<! When Phone send Disconnect key to ESP32, this event happen */
-    ESP_BLUFI_EVENT_GET_WIFI_LIST,                       /*<! When Phone send get wifi list command to ESP32, this event happen */
-    ESP_BLUFI_EVENT_REPORT_ERROR,                        /*<! When Blufi report error, this event happen */
-    ESP_BLUFI_EVENT_RECV_CUSTOM_DATA,                    /*<! When Phone send custom data to ESP32, this event happen */
-} esp_blufi_cb_event_t;
-
-/// BLUFI config status
-typedef enum {
-    ESP_BLUFI_STA_CONN_SUCCESS = 0x00,
-    ESP_BLUFI_STA_CONN_FAIL    = 0x01,
-} esp_blufi_sta_conn_state_t;
-
-/// BLUFI init status
-typedef enum {
-    ESP_BLUFI_INIT_OK = 0,
-    ESP_BLUFI_INIT_FAILED,
-} esp_blufi_init_state_t;
-
-/// BLUFI deinit status
-typedef enum {
-    ESP_BLUFI_DEINIT_OK = 0,
-    ESP_BLUFI_DEINIT_FAILED,
-} esp_blufi_deinit_state_t;
-
-typedef enum {
-    ESP_BLUFI_SEQUENCE_ERROR = 0,
-    ESP_BLUFI_CHECKSUM_ERROR,
-    ESP_BLUFI_DECRYPT_ERROR,
-    ESP_BLUFI_ENCRYPT_ERROR,
-    ESP_BLUFI_INIT_SECURITY_ERROR,
-    ESP_BLUFI_DH_MALLOC_ERROR,
-    ESP_BLUFI_DH_PARAM_ERROR,
-    ESP_BLUFI_READ_PARAM_ERROR,
-    ESP_BLUFI_MAKE_PUBLIC_ERROR,
-    ESP_BLUFI_DATA_FORMAT_ERROR,
-} esp_blufi_error_state_t;
-
-/**
- * @brief BLUFI  extra information structure
- */
-typedef struct {
-    //station
-    uint8_t sta_bssid[6];           /*!< BSSID of station interface */
-    bool sta_bssid_set;             /*!< is BSSID of station interface set */
-    uint8_t *sta_ssid;              /*!< SSID of station interface */
-    int sta_ssid_len;               /*!< length of SSID of station interface */
-    uint8_t *sta_passwd;            /*!< password of station interface */
-    int sta_passwd_len;             /*!< length of password of station interface */
-    uint8_t *softap_ssid;           /*!< SSID of softap interface */
-    int softap_ssid_len;            /*!< length of SSID of softap interface */
-    uint8_t *softap_passwd;         /*!< password of station interface */
-    int softap_passwd_len;          /*!< length of password of station interface */
-    uint8_t softap_authmode;        /*!< authentication mode of softap interface */
-    bool softap_authmode_set;       /*!< is authentication mode of softap interface set */
-    uint8_t softap_max_conn_num;    /*!< max connection number of softap interface */
-    bool softap_max_conn_num_set;   /*!< is max connection number of softap interface set */
-    uint8_t softap_channel;         /*!< channel of softap interface */
-    bool softap_channel_set;        /*!< is channel of softap interface set */
-} esp_blufi_extra_info_t;
-
-/** @brief Description of an WiFi AP */
-typedef struct {
-    uint8_t ssid[33];                     /**< SSID of AP */
-    int8_t  rssi;                         /**< signal strength of AP */
-} esp_blufi_ap_record_t;
-
-/**
- * @brief BLUFI callback parameters union 
- */
-typedef union {
-    /**
-	 * @brief ESP_BLUFI_EVENT_INIT_FINISH
-	 */
-    struct blufi_init_finish_evt_param {
-        esp_blufi_init_state_t state;				/*!< Initial status */
-    } init_finish;									/*!< Blufi callback param of ESP_BLUFI_EVENT_INIT_FINISH */
-
-    /**
-	 * @brief ESP_BLUFI_EVENT_DEINIT_FINISH
-	 */
-    struct blufi_deinit_finish_evt_param {
-        esp_blufi_deinit_state_t state;				/*!< De-initial status */
-    } deinit_finish;								/*!< Blufi callback param of ESP_BLUFI_EVENT_DEINIT_FINISH */
-
-    /**
-     * @brief ESP_BLUFI_EVENT_SET_WIFI_MODE
-     */
-    struct blufi_set_wifi_mode_evt_param {
-        wifi_mode_t op_mode;                        /*!< Wifi operation mode */
-    } wifi_mode;									/*!< Blufi callback param of ESP_BLUFI_EVENT_INIT_FINISH */
-
-    /**
-     * @brief ESP_BLUFI_EVENT_CONNECT
-	 */
-    struct blufi_connect_evt_param {
-        esp_bd_addr_t remote_bda;                   /*!< Blufi Remote bluetooth device address */
-        uint8_t    server_if;                       /*!< server interface */
-        uint16_t   conn_id;                         /*!< Connection id */
-    } connect;									    /*!< Blufi callback param of ESP_BLUFI_EVENT_CONNECT */
-
-    /**
-     * @brief ESP_BLUFI_EVENT_DISCONNECT
-	 */
-    struct blufi_disconnect_evt_param {
-        esp_bd_addr_t remote_bda;                   /*!< Blufi Remote bluetooth device address */
-    } disconnect;									/*!< Blufi callback param of ESP_BLUFI_EVENT_DISCONNECT */
-
-    /* ESP_BLUFI_EVENT_REQ_WIFI_CONNECT */          /* No callback param */
-    /* ESP_BLUFI_EVENT_REQ_WIFI_DISCONNECT */       /* No callback param */
-
-    /**
-     * @brief ESP_BLUFI_EVENT_RECV_STA_BSSID
-     */
-    struct blufi_recv_sta_bssid_evt_param {
-        uint8_t bssid[6];                           /*!< BSSID */
-    } sta_bssid;                                    /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_STA_BSSID */
-
-    /**
-     * @brief ESP_BLUFI_EVENT_RECV_STA_SSID
-     */
-    struct blufi_recv_sta_ssid_evt_param {
-        uint8_t *ssid;                              /*!< SSID */
-        int ssid_len;                               /*!< SSID length */
-    } sta_ssid;                                     /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_STA_SSID */
-
-    /**
-     * @brief 
-     * ESP_BLUFI_EVENT_RECV_STA_PASSWD
-     */
-    struct blufi_recv_sta_passwd_evt_param {
-        uint8_t *passwd;                            /*!< Password */
-        int passwd_len;                             /*!< Password Length */
-    } sta_passwd;                                   /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_STA_PASSWD */
-
-    /**
-     * @brief ESP_BLUFI_EVENT_RECV_SOFTAP_SSID
-     */
-    struct blufi_recv_softap_ssid_evt_param {
-        uint8_t *ssid;                              /*!< SSID */
-        int ssid_len;                               /*!< SSID length */
-    } softap_ssid;                                  /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_SOFTAP_SSID */
-
-    /**
-     * @brief 
-     * ESP_BLUFI_EVENT_RECV_SOFTAP_PASSWD
-     */
-    struct blufi_recv_softap_passwd_evt_param {
-        uint8_t *passwd;                            /*!< Password */
-        int passwd_len;                             /*!< Password Length */
-    } softap_passwd;                                /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_SOFTAP_PASSWD */
-
-    /**
-     * @brief ESP_BLUFI_EVENT_RECV_SOFTAP_MAX_CONN_NUM
-     */
-    struct blufi_recv_softap_max_conn_num_evt_param {
-        int max_conn_num;                           /*!< SSID */
-    } softap_max_conn_num;                          /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_SOFTAP_MAX_CONN_NUM */
-
-    /**
-     * @brief 
-     * ESP_BLUFI_EVENT_RECV_SOFTAP_AUTH_MODE
-     */
-    struct blufi_recv_softap_auth_mode_evt_param {
-        wifi_auth_mode_t auth_mode;                 /*!< Authentication mode */
-    } softap_auth_mode;                             /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_SOFTAP_AUTH_MODE */
-
-    /**
-     * @brief 
-     * ESP_BLUFI_EVENT_RECV_SOFTAP_CHANNEL
-     */
-    struct blufi_recv_softap_channel_evt_param {
-        uint8_t channel;                            /*!< Authentication mode */
-    } softap_channel;                             /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_SOFTAP_CHANNEL */
-
-    /**
-     * @brief ESP_BLUFI_EVENT_RECV_USERNAME
-     */
-    struct blufi_recv_username_evt_param {
-        uint8_t *name;                              /*!< Username point */
-        int name_len;                               /*!< Username length */
-    } username;                                     /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_USERNAME*/ 
-
-    /**
-     * @brief ESP_BLUFI_EVENT_RECV_CA_CERT
-     */
-    struct blufi_recv_ca_evt_param {
-        uint8_t *cert;                              /*!< CA certificate point */
-        int cert_len;                               /*!< CA certificate length */
-    } ca;                                           /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_CA_CERT */
-
-    /**
-     * ESP_BLUFI_EVENT_RECV_CLIENT_CERT
-     */
-    struct blufi_recv_client_cert_evt_param {
-        uint8_t *cert;                              /*!< Client certificate point */
-        int cert_len;                               /*!< Client certificate length */
-    } client_cert;                                  /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_CLIENT_CERT */
-
-    /**
-     * ESP_BLUFI_EVENT_RECV_SERVER_CERT
-     */
-    struct blufi_recv_server_cert_evt_param {
-        uint8_t *cert;                              /*!< Client certificate point */
-        int cert_len;                               /*!< Client certificate length */
-    } server_cert;                                  /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_SERVER_CERT */
-
-    /**
-     * ESP_BLUFI_EVENT_RECV_CLIENT_PRIV_KEY
-     */
-    struct blufi_recv_client_pkey_evt_param {
-        uint8_t *pkey;                              /*!< Client Private Key point, if Client certificate not contain Key */
-        int pkey_len;                               /*!< Client Private key length */
-    } client_pkey;                                  /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_CLIENT_PRIV_KEY */
-    /**
-     * ESP_BLUFI_EVENT_RECV_SERVER_PRIV_KEY
-     */
-    struct blufi_recv_server_pkey_evt_param {
-        uint8_t *pkey;                              /*!< Client Private Key point, if Client certificate not contain Key */
-        int pkey_len;                               /*!< Client Private key length */
-    } server_pkey;                                  /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_SERVER_PRIV_KEY */
-    /**
-     * @brief
-     * ESP_BLUFI_EVENT_REPORT_ERROR
-     */
-    struct blufi_get_error_evt_param {
-        esp_blufi_error_state_t state;              /*!< Blufi error state */
-    } report_error;                                 /*!< Blufi callback param of ESP_BLUFI_EVENT_REPORT_ERROR */
-    /**
-     * @brief 
-     * ESP_BLUFI_EVENT_RECV_CUSTOM_DATA
-     */
-    struct blufi_recv_custom_data_evt_param {
-        uint8_t *data;                              /*!< Custom data */
-        uint32_t data_len;                          /*!< Custom data Length */
-    } custom_data;                                  /*!< Blufi callback param of ESP_BLUFI_EVENT_RECV_CUSTOM_DATA */
-} esp_blufi_cb_param_t;
-
-/**
- * @brief BLUFI event callback function type
- * @param event : Event type
- * @param param : Point to callback parameter, currently is union type
- */
-typedef void (* esp_blufi_event_cb_t)(esp_blufi_cb_event_t event, esp_blufi_cb_param_t *param);
-
-/* security function declare */
-
-/**
- * @brief BLUFI negotiate data handler 
- * @param data : data from phone
- * @param len  : length of data from phone
- * @param output_data : data want to send to phone
- * @param output_len : length of data want to send to phone
- */
-typedef void (*esp_blufi_negotiate_data_handler_t)(uint8_t *data, int len, uint8_t **output_data, int *output_len, bool *need_free);
-
-/**
- * @brief BLUFI  encrypt the data after negotiate a share key
- * @param iv8  : initial vector(8bit), normally, blufi core will input packet sequence number
- * @param crypt_data : plain text and encrypted data, the encrypt function must support autochthonous encrypt 
- * @param crypt_len  : length of plain text
- * @return  Nonnegative number is encrypted length, if error, return negative number;
- */
-typedef int (* esp_blufi_encrypt_func_t)(uint8_t iv8, uint8_t *crypt_data, int cyprt_len);
-
-/**
- * @brief BLUFI  decrypt the data after negotiate a share key
- * @param iv8  : initial vector(8bit), normally, blufi core will input packet sequence number
- * @param crypt_data : encrypted data and plain text, the encrypt function must support autochthonous decrypt 
- * @param crypt_len  : length of encrypted text
- * @return  Nonnegative number is decrypted length, if error, return negative number;
- */
-typedef int (* esp_blufi_decrypt_func_t)(uint8_t iv8, uint8_t *crypt_data, int crypt_len);
-
-/**
- * @brief BLUFI  checksum
- * @param iv8  : initial vector(8bit), normally, blufi core will input packet sequence number
- * @param data : data need to checksum
- * @param len  : length of data
- */
-typedef uint16_t (*esp_blufi_checksum_func_t)(uint8_t iv8, uint8_t *data, int len);
-
-/**
- * @brief BLUFI  callback functions type
- */
-typedef struct {
-    esp_blufi_event_cb_t                event_cb;                   /*!< BLUFI event callback */
-    esp_blufi_negotiate_data_handler_t  negotiate_data_handler;     /*!< BLUFI negotiate data function for negotiate share key */
-    esp_blufi_encrypt_func_t            encrypt_func;               /*!< BLUFI encrypt data function with share key generated by negotiate_data_handler */
-    esp_blufi_decrypt_func_t            decrypt_func;               /*!< BLUFI decrypt data function with share key generated by negotiate_data_handler */
-    esp_blufi_checksum_func_t           checksum_func;              /*!< BLUFI check sum function (FCS) */
-} esp_blufi_callbacks_t;
-
-/**
- *
- * @brief           This function is called to receive blufi callback event
- *
- * @param[in]       callbacks: callback functions
- *
- * @return          ESP_OK - success, other - failed
- *
- */
-esp_err_t esp_blufi_register_callbacks(esp_blufi_callbacks_t *callbacks);
-
-/**
- *
- * @brief           This function is called to initialize blufi_profile
- *
- * @return          ESP_OK - success, other - failed
- *
- */
-esp_err_t esp_blufi_profile_init(void);
-
-/**
- *
- * @brief           This function is called to de-initialize blufi_profile
- *
- * @return          ESP_OK - success, other - failed
- *
- */
-esp_err_t esp_blufi_profile_deinit(void);
-
-/**
- *
- * @brief           This function is called to send wifi connection report
- * @param opmode :  wifi opmode
- * @param sta_conn_state   : station is already in connection or not
- * @param softap_conn_num  : softap connection number
- * @param extra_info       : extra information, such as sta_ssid, softap_ssid and etc. 
- *
- * @return          ESP_OK - success, other - failed
- *
- */
-esp_err_t esp_blufi_send_wifi_conn_report(wifi_mode_t opmode, esp_blufi_sta_conn_state_t sta_conn_state, uint8_t softap_conn_num, esp_blufi_extra_info_t *extra_info);
-
-/**
- *
- * @brief           This function is called to send wifi list
- * @param apCount :  wifi list count
- * @param list   : wifi list
- *
- * @return          ESP_OK - success, other - failed
- *
- */
-esp_err_t esp_blufi_send_wifi_list(uint16_t apCount, esp_blufi_ap_record_t *list);
-
-/**
- *
- * @brief           Get BLUFI profile version
- * 
- * @return          Most 8bit significant is Great version, Least 8bit is Sub version
- *
- */
-uint16_t esp_blufi_get_version(void);
-
-/**
- * @brief           Close a connection  a remote device.
- *
- * @param[in]       gatts_if: GATT server access interface
- * @param[in]       conn_id: connection ID to be closed.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_blufi_close(esp_gatt_if_t gatts_if, uint16_t conn_id);
-
-/**
- *
- * @brief           This function is called to send blufi error information
- * @param state :  error state
- *
- * @return          ESP_OK - success, other - failed
- *
- */
-esp_err_t esp_blufi_send_error_info(esp_blufi_error_state_t state);
-/**
- *
- * @brief           This function is called to custom data
- * @param data :  custom data value
- * @param data_len :  the length of custom data
- *
- * @return          ESP_OK - success, other - failed
- *
- */
-esp_err_t esp_blufi_send_custom_data(uint8_t *data, uint32_t data_len);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ESP_BLUFI_API_ */
diff --git a/tools/sdk/include/bt/esp_bt.h b/tools/sdk/include/bt/esp_bt.h
deleted file mode 100644
index fb38fe68df0..00000000000
--- a/tools/sdk/include/bt/esp_bt.h
+++ /dev/null
@@ -1,496 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_BT_H__
-#define __ESP_BT_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-#include "sdkconfig.h"
-#include "esp_task.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL  0x20200611
-
-/**
- * @brief Bluetooth mode for controller enable/disable
- */
-typedef enum {
-    ESP_BT_MODE_IDLE       = 0x00,   /*!< Bluetooth is not running */
-    ESP_BT_MODE_BLE        = 0x01,   /*!< Run BLE mode */
-    ESP_BT_MODE_CLASSIC_BT = 0x02,   /*!< Run Classic BT mode */
-    ESP_BT_MODE_BTDM       = 0x03,   /*!< Run dual mode */
-} esp_bt_mode_t;
-
-#ifdef CONFIG_BT_ENABLED
-/* While scanning, if the free memory value in controller is less than SCAN_SEND_ADV_RESERVED_SIZE,
-the adv packet will be discarded until the memory is restored. */
-#define SCAN_SEND_ADV_RESERVED_SIZE        1000
-/* enable controller log debug when adv lost */
-#define CONTROLLER_ADV_LOST_DEBUG_BIT      (0<<0)
-
-#ifdef CONFIG_BT_HCI_UART_NO
-#define BT_HCI_UART_NO_DEFAULT                      CONFIG_BT_HCI_UART_NO
-#else
-#define BT_HCI_UART_NO_DEFAULT                      1
-#endif /* BT_HCI_UART_NO_DEFAULT */
-
-#ifdef CONFIG_BT_HCI_UART_BAUDRATE
-#define BT_HCI_UART_BAUDRATE_DEFAULT                CONFIG_BT_HCI_UART_BAUDRATE
-#else
-#define BT_HCI_UART_BAUDRATE_DEFAULT                921600
-#endif /* BT_HCI_UART_BAUDRATE_DEFAULT */
-
-#ifdef CONFIG_SCAN_DUPLICATE_TYPE
-#define SCAN_DUPLICATE_TYPE_VALUE  CONFIG_SCAN_DUPLICATE_TYPE
-#else
-#define SCAN_DUPLICATE_TYPE_VALUE  0
-#endif
-
-/* normal adv cache size */
-#ifdef CONFIG_DUPLICATE_SCAN_CACHE_SIZE
-#define NORMAL_SCAN_DUPLICATE_CACHE_SIZE            CONFIG_DUPLICATE_SCAN_CACHE_SIZE
-#else
-#define NORMAL_SCAN_DUPLICATE_CACHE_SIZE            20
-#endif
-
-#ifndef CONFIG_BLE_MESH_SCAN_DUPLICATE_EN
-#define CONFIG_BLE_MESH_SCAN_DUPLICATE_EN FALSE
-#endif
-
-#define SCAN_DUPLICATE_MODE_NORMAL_ADV_ONLY         0
-#define SCAN_DUPLICATE_MODE_NORMAL_ADV_MESH_ADV     1
-
-#if CONFIG_BLE_MESH_SCAN_DUPLICATE_EN
-    #define SCAN_DUPLICATE_MODE                     SCAN_DUPLICATE_MODE_NORMAL_ADV_MESH_ADV
-    #ifdef CONFIG_MESH_DUPLICATE_SCAN_CACHE_SIZE
-    #define MESH_DUPLICATE_SCAN_CACHE_SIZE          CONFIG_MESH_DUPLICATE_SCAN_CACHE_SIZE
-    #else
-    #define MESH_DUPLICATE_SCAN_CACHE_SIZE          50
-    #endif
-#else
-    #define SCAN_DUPLICATE_MODE SCAN_DUPLICATE_MODE_NORMAL_ADV_ONLY
-    #define MESH_DUPLICATE_SCAN_CACHE_SIZE          0
-#endif
-
-#if defined(CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY)
-#define BTDM_CONTROLLER_MODE_EFF                    ESP_BT_MODE_BLE
-#elif defined(CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY)
-#define BTDM_CONTROLLER_MODE_EFF                    ESP_BT_MODE_CLASSIC_BT
-#else
-#define BTDM_CONTROLLER_MODE_EFF                    ESP_BT_MODE_BTDM
-#endif
-
-#ifdef CONFIG_BTDM_CTRL_AUTO_LATENCY_EFF
-#define BTDM_CTRL_AUTO_LATENCY_EFF CONFIG_BTDM_CTRL_AUTO_LATENCY_EFF
-#else
-#define BTDM_CTRL_AUTO_LATENCY_EFF false
-#endif
-
-#ifdef CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF
-#define BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF
-#else
-#define BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF false
-#endif
-
-#define BTDM_CONTROLLER_BLE_MAX_CONN_LIMIT          9   //Maximum BLE connection limitation
-#define BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_LIMIT   7   //Maximum ACL connection limitation
-#define BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_LIMIT  3   //Maximum SCO/eSCO connection limitation
-
-#define BTDM_CONTROLLER_SCO_DATA_PATH_HCI           0   // SCO data is routed to HCI
-#define BTDM_CONTROLLER_SCO_DATA_PATH_PCM           1   // SCO data path is PCM
-
-#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {                              \
-    .controller_task_stack_size = ESP_TASK_BT_CONTROLLER_STACK,            \
-    .controller_task_prio = ESP_TASK_BT_CONTROLLER_PRIO,                   \
-    .hci_uart_no = BT_HCI_UART_NO_DEFAULT,                                 \
-    .hci_uart_baudrate = BT_HCI_UART_BAUDRATE_DEFAULT,                     \
-    .scan_duplicate_mode = SCAN_DUPLICATE_MODE,                            \
-    .scan_duplicate_type = SCAN_DUPLICATE_TYPE_VALUE,                      \
-    .normal_adv_size = NORMAL_SCAN_DUPLICATE_CACHE_SIZE,                   \
-    .mesh_adv_size = MESH_DUPLICATE_SCAN_CACHE_SIZE,                       \
-    .send_adv_reserved_size = SCAN_SEND_ADV_RESERVED_SIZE,                 \
-    .controller_debug_flag = CONTROLLER_ADV_LOST_DEBUG_BIT,                \
-    .mode = BTDM_CONTROLLER_MODE_EFF,                                      \
-    .ble_max_conn = CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF,               \
-    .bt_max_acl_conn = CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF,     \
-    .bt_sco_datapath = CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF,          \
-    .auto_latency = BTDM_CTRL_AUTO_LATENCY_EFF,                            \
-    .bt_legacy_auth_vs_evt = BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF,         \
-    .bt_max_sync_conn = CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF,   \
-    .magic = ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL,                           \
-};
-
-#else
-#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use bt.h");
-#endif
-
-/**
- * @brief Controller config options, depend on config mask.
- *        Config mask indicate which functions enabled, this means
- *        some options or parameters of some functions enabled by config mask.
- */
-typedef struct {
-    /*
-     * Following parameters can be configured runtime, when call esp_bt_controller_init()
-     */
-    uint16_t controller_task_stack_size;    /*!< Bluetooth controller task stack size */
-    uint8_t controller_task_prio;           /*!< Bluetooth controller task priority */
-    uint8_t hci_uart_no;                    /*!< If use UART1/2 as HCI IO interface, indicate UART number */
-    uint32_t hci_uart_baudrate;             /*!< If use UART1/2 as HCI IO interface, indicate UART baudrate */
-    uint8_t scan_duplicate_mode;            /*!< scan duplicate mode */
-    uint8_t scan_duplicate_type;            /*!< scan duplicate type */
-    uint16_t normal_adv_size;               /*!< Normal adv size for scan duplicate */
-    uint16_t mesh_adv_size;                 /*!< Mesh adv size for scan duplicate */
-    uint16_t send_adv_reserved_size;        /*!< Controller minimum memory value */
-    uint32_t  controller_debug_flag;        /*!< Controller debug log flag */
-    uint8_t mode;                           /*!< Controller mode: BR/EDR, BLE or Dual Mode */
-    uint8_t ble_max_conn;                   /*!< BLE maximum connection numbers */
-    uint8_t bt_max_acl_conn;                /*!< BR/EDR maximum ACL connection numbers */
-    uint8_t bt_sco_datapath;                /*!< SCO data path, i.e. HCI or PCM module */
-    bool auto_latency;                      /*!< BLE auto latency, used to enhance classic BT performance */
-    bool bt_legacy_auth_vs_evt;             /*!< BR/EDR Legacy auth complete event required to  protect from BIAS attack */
-    /*
-     * Following parameters can not be configured runtime when call esp_bt_controller_init()
-     * It will be overwrite with a constant value which in menuconfig or from a macro.
-     * So, do not modify the value when esp_bt_controller_init()
-     */
-    uint8_t bt_max_sync_conn;               /*!< BR/EDR maximum ACL connection numbers. Effective in menuconfig */
-    uint32_t magic;                         /*!< Magic number */
-} esp_bt_controller_config_t;
-
-/**
- * @brief Bluetooth controller enable/disable/initialised/de-initialised status
- */
-typedef enum {
-    ESP_BT_CONTROLLER_STATUS_IDLE = 0,
-    ESP_BT_CONTROLLER_STATUS_INITED,
-    ESP_BT_CONTROLLER_STATUS_ENABLED,
-    ESP_BT_CONTROLLER_STATUS_NUM,
-} esp_bt_controller_status_t;
-
-/**
- * @brief BLE tx power type
- *        ESP_BLE_PWR_TYPE_CONN_HDL0-8: for each connection, and only be set after connection completed.
- *                                      when disconnect, the correspond TX power is not effected.
- *        ESP_BLE_PWR_TYPE_ADV : for advertising/scan response.
- *        ESP_BLE_PWR_TYPE_SCAN : for scan.
- *        ESP_BLE_PWR_TYPE_DEFAULT : if each connection's TX power is not set, it will use this default value.
- *                                   if neither in scan mode nor in adv mode, it will use this default value.
- *        If none of power type is set, system will use ESP_PWR_LVL_P3 as default for ADV/SCAN/CONN0-9.
- */
-typedef enum {
-    ESP_BLE_PWR_TYPE_CONN_HDL0  = 0,            /*!< For connection handle 0 */
-    ESP_BLE_PWR_TYPE_CONN_HDL1  = 1,            /*!< For connection handle 1 */
-    ESP_BLE_PWR_TYPE_CONN_HDL2  = 2,            /*!< For connection handle 2 */
-    ESP_BLE_PWR_TYPE_CONN_HDL3  = 3,            /*!< For connection handle 3 */
-    ESP_BLE_PWR_TYPE_CONN_HDL4  = 4,            /*!< For connection handle 4 */
-    ESP_BLE_PWR_TYPE_CONN_HDL5  = 5,            /*!< For connection handle 5 */
-    ESP_BLE_PWR_TYPE_CONN_HDL6  = 6,            /*!< For connection handle 6 */
-    ESP_BLE_PWR_TYPE_CONN_HDL7  = 7,            /*!< For connection handle 7 */
-    ESP_BLE_PWR_TYPE_CONN_HDL8  = 8,            /*!< For connection handle 8 */
-    ESP_BLE_PWR_TYPE_ADV        = 9,            /*!< For advertising */
-    ESP_BLE_PWR_TYPE_SCAN       = 10,           /*!< For scan */
-    ESP_BLE_PWR_TYPE_DEFAULT    = 11,           /*!< For default, if not set other, it will use default value */
-    ESP_BLE_PWR_TYPE_NUM        = 12,           /*!< TYPE numbers */
-} esp_ble_power_type_t;
-
-/**
- * @brief Bluetooth TX power level(index), it's just a index corresponding to power(dbm).
- */
-typedef enum {
-    ESP_PWR_LVL_N12 = 0,                /*!< Corresponding to -12dbm */
-    ESP_PWR_LVL_N9  = 1,                /*!< Corresponding to  -9dbm */
-    ESP_PWR_LVL_N6  = 2,                /*!< Corresponding to  -6dbm */
-    ESP_PWR_LVL_N3  = 3,                /*!< Corresponding to  -3dbm */
-    ESP_PWR_LVL_N0  = 4,                /*!< Corresponding to   0dbm */
-    ESP_PWR_LVL_P3  = 5,                /*!< Corresponding to  +3dbm */
-    ESP_PWR_LVL_P6  = 6,                /*!< Corresponding to  +6dbm */
-    ESP_PWR_LVL_P9  = 7,                /*!< Corresponding to  +9dbm */
-    ESP_PWR_LVL_N14 = ESP_PWR_LVL_N12,  /*!< Backward compatibility! Setting to -14dbm will actually result to -12dbm */
-    ESP_PWR_LVL_N11 = ESP_PWR_LVL_N9,   /*!< Backward compatibility! Setting to -11dbm will actually result to  -9dbm */
-    ESP_PWR_LVL_N8  = ESP_PWR_LVL_N6,   /*!< Backward compatibility! Setting to  -8dbm will actually result to  -6dbm */
-    ESP_PWR_LVL_N5  = ESP_PWR_LVL_N3,   /*!< Backward compatibility! Setting to  -5dbm will actually result to  -3dbm */
-    ESP_PWR_LVL_N2  = ESP_PWR_LVL_N0,   /*!< Backward compatibility! Setting to  -2dbm will actually result to   0dbm */
-    ESP_PWR_LVL_P1  = ESP_PWR_LVL_P3,   /*!< Backward compatibility! Setting to  +1dbm will actually result to  +3dbm */
-    ESP_PWR_LVL_P4  = ESP_PWR_LVL_P6,   /*!< Backward compatibility! Setting to  +4dbm will actually result to  +6dbm */
-    ESP_PWR_LVL_P7  = ESP_PWR_LVL_P9,   /*!< Backward compatibility! Setting to  +7dbm will actually result to  +9dbm */
-} esp_power_level_t;
-
-/**
- * @brief Bluetooth audio data transport path
- */
-typedef enum {
-    ESP_SCO_DATA_PATH_HCI = 0,            /*!< data over HCI transport */
-    ESP_SCO_DATA_PATH_PCM = 1,            /*!< data over PCM interface */
-} esp_sco_data_path_t;
-
-/**
- * @brief  Set BLE TX power
- *         Connection Tx power should only be set after connection created.
- * @param  power_type : The type of which tx power, could set Advertising/Connection/Default and etc
- * @param  power_level: Power level(index) corresponding to absolute value(dbm)
- * @return              ESP_OK - success, other - failed
- */
-esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level);
-
-/**
- * @brief  Get BLE TX power
- *         Connection Tx power should only be get after connection created.
- * @param  power_type : The type of which tx power, could set Advertising/Connection/Default and etc
- * @return             >= 0 - Power level, < 0 - Invalid
- */
-esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type);
-
-/**
- * @brief  Set BR/EDR TX power
- *         BR/EDR power control will use the power in range of minimum value and maximum value.
- *         The power level will effect the global BR/EDR TX power, such inquire, page, connection and so on.
- *         Please call the function after esp_bt_controller_enable and before any function which cause RF do TX.
- *         So you can call the function before doing discovery, profile init and so on.
- *         For example, if you want BR/EDR use the new TX power to do inquire, you should call
- *         this function before inquire. Another word, If call this function when BR/EDR is in inquire(ING),
- *         please do inquire again after call this function.
- *         Default minimum power level is ESP_PWR_LVL_N0, and maximum power level is ESP_PWR_LVL_P3.
- * @param  min_power_level: The minimum power level
- * @param  max_power_level: The maximum power level
- * @return              ESP_OK - success, other - failed
- */
-esp_err_t esp_bredr_tx_power_set(esp_power_level_t min_power_level, esp_power_level_t max_power_level);
-
-/**
- * @brief  Get BR/EDR TX power
- *         If the argument is not NULL, then store the corresponding value.
- * @param  min_power_level: The minimum power level
- * @param  max_power_level: The maximum power level
- * @return              ESP_OK - success, other - failed
- */
-esp_err_t esp_bredr_tx_power_get(esp_power_level_t *min_power_level, esp_power_level_t *max_power_level);
-
-/**
- * @brief  set default SCO data path
- *         Should be called after controller is enabled, and before (e)SCO link is established
- * @param  data_path: SCO data path
- * @return              ESP_OK - success, other - failed
- */
-esp_err_t esp_bredr_sco_datapath_set(esp_sco_data_path_t data_path);
-
-/**
- * @brief       Initialize BT controller to allocate task and other resource.
- *              This function should be called only once, before any other BT functions are called.
- * @param  cfg: Initial configuration of BT controller. Different from previous version, there's a mode and some
- *              connection configuration in "cfg" to configure controller work mode and allocate the resource which is needed.
- * @return      ESP_OK - success, other - failed
- */
-esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg);
-
-/**
- * @brief  De-initialize BT controller to free resource and delete task.
- *
- * This function should be called only once, after any other BT functions are called.
- * This function is not whole completed, esp_bt_controller_init cannot called after this function.
- * @return  ESP_OK - success, other - failed
- */
-esp_err_t esp_bt_controller_deinit(void);
-
-/**
- * @brief Enable BT controller.
- *               Due to a known issue, you cannot call esp_bt_controller_enable() a second time
- *               to change the controller mode dynamically. To change controller mode, call
- *               esp_bt_controller_disable() and then call esp_bt_controller_enable() with the new mode.
- * @param mode : the mode(BLE/BT/BTDM) to enable. For compatible of API, retain this argument. This mode must be
- *               equal as the mode in "cfg" of esp_bt_controller_init().
- * @return       ESP_OK - success, other - failed
- */
-esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode);
-
-/**
- * @brief  Disable BT controller
- * @return       ESP_OK - success, other - failed
- */
-esp_err_t esp_bt_controller_disable(void);
-
-/**
- * @brief  Get BT controller is initialised/de-initialised/enabled/disabled
- * @return status value
- */
-esp_bt_controller_status_t esp_bt_controller_get_status(void);
-
-/** @brief esp_vhci_host_callback
- *  used for vhci call host function to notify what host need to do
- */
-typedef struct esp_vhci_host_callback {
-    void (*notify_host_send_available)(void);               /*!< callback used to notify that the host can send packet to controller */
-    int (*notify_host_recv)(uint8_t *data, uint16_t len);   /*!< callback used to notify that the controller has a packet to send to the host*/
-} esp_vhci_host_callback_t;
-
-/** @brief esp_vhci_host_check_send_available
- *  used for check actively if the host can send packet to controller or not.
- *  @return true for ready to send, false means cannot send packet
- */
-bool esp_vhci_host_check_send_available(void);
-
-/** @brief esp_vhci_host_send_packet
- * host send packet to controller
- *
- * Should not call this function from within a critical section
- * or when the scheduler is suspended.
- *
- * @param data the packet point
- * @param len the packet length
- */
-void esp_vhci_host_send_packet(uint8_t *data, uint16_t len);
-
-/** @brief esp_vhci_host_register_callback
- * register the vhci reference callback
- * struct defined by vhci_host_callback structure.
- * @param callback esp_vhci_host_callback type variable
- * @return ESP_OK - success, ESP_FAIL - failed
- */
-esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback);
-
-/** @brief esp_bt_controller_mem_release
- * release the controller memory as per the mode
- *
- * This function releases the BSS, data and other sections of the controller to heap. The total size is about 70k bytes.
- *
- * esp_bt_controller_mem_release(mode) should be called only before esp_bt_controller_init()
- * or after esp_bt_controller_deinit().
- *
- * Note that once BT controller memory is released, the process cannot be reversed. It means you cannot use the bluetooth
- * mode which you have released by this function.
- *
- * If your firmware will later upgrade the Bluetooth controller mode (BLE -> BT Classic or disabled -> enabled)
- * then do not call this function.
- *
- * If the app calls esp_bt_controller_enable(ESP_BT_MODE_BLE) to use BLE only then it is safe to call
- * esp_bt_controller_mem_release(ESP_BT_MODE_CLASSIC_BT) at initialization time to free unused BT Classic memory.
- *
- * If the mode is ESP_BT_MODE_BTDM, then it may be useful to call API esp_bt_mem_release(ESP_BT_MODE_BTDM) instead,
- * which internally calls esp_bt_controller_mem_release(ESP_BT_MODE_BTDM) and additionally releases the BSS and data
- * consumed by the BT/BLE host stack to heap. For more details about usage please refer to the documentation of
- * esp_bt_mem_release() function
- *
- * @param mode : the mode want to release memory
- * @return ESP_OK - success, other - failed
- */
-esp_err_t esp_bt_controller_mem_release(esp_bt_mode_t mode);
-
-/** @brief esp_bt_mem_release
- * release controller memory and BSS and data section of the BT/BLE host stack as per the mode
- *
- * This function first releases controller memory by internally calling esp_bt_controller_mem_release().
- * Additionally, if the mode is set to ESP_BT_MODE_BTDM, it also releases the BSS and data consumed by the BT/BLE host stack to heap
- *
- * Note that once BT memory is released, the process cannot be reversed. It means you cannot use the bluetooth
- * mode which you have released by this function.
- *
- * If your firmware will later upgrade the Bluetooth controller mode (BLE -> BT Classic or disabled -> enabled)
- * then do not call this function.
- *
- * If you never intend to use bluetooth in a current boot-up cycle, you can call esp_bt_mem_release(ESP_BT_MODE_BTDM)
- * before esp_bt_controller_init or after esp_bt_controller_deinit.
- *
- * For example, if a user only uses bluetooth for setting the WiFi configuration, and does not use bluetooth in the rest of the product operation".
- * In such cases, after receiving the WiFi configuration, you can disable/deinit bluetooth and release its memory.
- * Below is the sequence of APIs to be called for such scenarios:
- *
- *      esp_bluedroid_disable();
- *      esp_bluedroid_deinit();
- *      esp_bt_controller_disable();
- *      esp_bt_controller_deinit();
- *      esp_bt_mem_release(ESP_BT_MODE_BTDM);
- *
- * @param mode : the mode whose memory is to be released
- * @return ESP_OK - success, other - failed
- */
-esp_err_t esp_bt_mem_release(esp_bt_mode_t mode);
-
-/**
- * @brief enable bluetooth to enter modem sleep
- *
- * Note that this function shall not be invoked before esp_bt_controller_enable()
- *
- * There are currently two options for bluetooth modem sleep, one is ORIG mode, and another is EVED Mode. EVED Mode is intended for BLE only.
- *
- * For ORIG mode:
- * Bluetooth modem sleep is enabled in controller start up by default if CONFIG_BTDM_CONTROLLER_MODEM_SLEEP is set and "ORIG mode" is selected. In ORIG modem sleep mode, bluetooth controller will switch off some components and pause to work every now and then, if there is no event to process; and wakeup according to the scheduled interval and resume the work. It can also wakeup earlier upon external request using function "esp_bt_controller_wakeup_request".
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- */
-esp_err_t esp_bt_sleep_enable(void);
-
-
-/**
- * @brief disable bluetooth modem sleep
- *
- * Note that this function shall not be invoked before esp_bt_controller_enable()
- *
- * If esp_bt_sleep_disable() is called, bluetooth controller will not be allowed to enter modem sleep;
- *
- * If ORIG modem sleep mode is in use, if this function is called, bluetooth controller may not immediately wake up if it is dormant then.
- * In this case, esp_bt_controller_wakeup_request() can be used to shorten the time for wakeup.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- */
-esp_err_t esp_bt_sleep_disable(void);
-
-/**
- * @brief to check whether bluetooth controller is sleeping at the instant, if modem sleep is enabled
- *
- * Note that this function shall not be invoked before esp_bt_controller_enable()
- * This function is supposed to be used ORIG mode of modem sleep
- *
- * @return  true if in modem sleep state, false otherwise
- */
-bool esp_bt_controller_is_sleeping(void);
-
-/**
- * @brief request controller to wakeup from sleeping state during sleep mode
- *
- * Note that this function shall not be invoked before esp_bt_controller_enable()
- * Note that this function is supposed to be used ORIG mode of modem sleep
- * Note that after this request, bluetooth controller may again enter sleep as long as the modem sleep is enabled
- *
- * Profiling shows that it takes several milliseconds to wakeup from modem sleep after this request.
- * Generally it takes longer if 32kHz XTAL is used than the main XTAL, due to the lower frequency of the former as the bluetooth low power clock source.
- */
-void esp_bt_controller_wakeup_request(void);
-
-/**
- * @brief Manually clear scan duplicate list
- *
- * Note that scan duplicate list will be automatically cleared when the maximum amount of device in the filter is reached
- * the amount of device in the filter can be configured in menuconfig.
- *
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- */
-esp_err_t esp_ble_scan_dupilcate_list_flush(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_BT_H__ */
diff --git a/tools/sdk/include/bt/esp_bt_defs.h b/tools/sdk/include/bt/esp_bt_defs.h
deleted file mode 100644
index da93b87bcad..00000000000
--- a/tools/sdk/include/bt/esp_bt_defs.h
+++ /dev/null
@@ -1,137 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_BT_DEFS_H__
-#define __ESP_BT_DEFS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ESP_BLUEDROID_STATUS_CHECK(status)           \
-    if (esp_bluedroid_get_status() != (status)) {    \
-        return ESP_ERR_INVALID_STATE;                \
-    }
-
-
-/* relate to BT_STATUS_xxx in bt_def.h */
-/// Status Return Value
-typedef enum {
-    ESP_BT_STATUS_SUCCESS       = 0,            /* relate to BT_STATUS_SUCCESS in bt_def.h */
-    ESP_BT_STATUS_FAIL,                         /* relate to BT_STATUS_FAIL in bt_def.h */
-    ESP_BT_STATUS_NOT_READY,                    /* relate to BT_STATUS_NOT_READY in bt_def.h */
-    ESP_BT_STATUS_NOMEM,                        /* relate to BT_STATUS_NOMEM in bt_def.h */
-    ESP_BT_STATUS_BUSY,                         /* relate to BT_STATUS_BUSY in bt_def.h */
-    ESP_BT_STATUS_DONE          = 5,            /* relate to BT_STATUS_DONE in bt_def.h */
-    ESP_BT_STATUS_UNSUPPORTED,                  /* relate to BT_STATUS_UNSUPPORTED in bt_def.h */
-    ESP_BT_STATUS_PARM_INVALID,                 /* relate to BT_STATUS_PARM_INVALID in bt_def.h */
-    ESP_BT_STATUS_UNHANDLED,                    /* relate to BT_STATUS_UNHANDLED in bt_def.h */
-    ESP_BT_STATUS_AUTH_FAILURE,                 /* relate to BT_STATUS_AUTH_FAILURE in bt_def.h */
-    ESP_BT_STATUS_RMT_DEV_DOWN  = 10,           /* relate to BT_STATUS_RMT_DEV_DOWN in bt_def.h */
-    ESP_BT_STATUS_AUTH_REJECTED,                /* relate to BT_STATUS_AUTH_REJECTED in bt_def.h */
-    ESP_BT_STATUS_INVALID_STATIC_RAND_ADDR,     /* relate to BT_STATUS_INVALID_STATIC_RAND_ADDR in bt_def.h */
-    ESP_BT_STATUS_PENDING,                      /* relate to BT_STATUS_PENDING in bt_def.h */
-    ESP_BT_STATUS_UNACCEPT_CONN_INTERVAL,       /* relate to BT_UNACCEPT_CONN_INTERVAL in bt_def.h */
-    ESP_BT_STATUS_PARAM_OUT_OF_RANGE,           /* relate to BT_PARAM_OUT_OF_RANGE in bt_def.h */
-    ESP_BT_STATUS_TIMEOUT,                      /* relate to BT_STATUS_TIMEOUT in bt_def.h */
-    ESP_BT_STATUS_PEER_LE_DATA_LEN_UNSUPPORTED, /* relate to BTM_PEER_LE_DATA_LEN_UNSUPPORTED in stack/btm_api.h */
-    ESP_BT_STATUS_CONTROL_LE_DATA_LEN_UNSUPPORTED,/* relate to BTM_CONTROL_LE_DATA_LEN_UNSUPPORTED in stack/btm_api.h */
-    ESP_BT_STATUS_ERR_ILLEGAL_PARAMETER_FMT,    /* relate to HCI_ERR_ILLEGAL_PARAMETER_FMT in stack/hcidefs.h */
-    ESP_BT_STATUS_MEMORY_FULL,                  /* relate to BT_STATUS_MEMORY_FULL in bt_def.h */
-} esp_bt_status_t;
-
-
-/*Define the bt octet 16 bit size*/
-#define ESP_BT_OCTET16_LEN    16
-typedef uint8_t esp_bt_octet16_t[ESP_BT_OCTET16_LEN];   /* octet array: size 16 */
-
-#define ESP_BT_OCTET8_LEN    8
-typedef uint8_t esp_bt_octet8_t[ESP_BT_OCTET8_LEN];   /* octet array: size 8 */
-
-typedef uint8_t esp_link_key[ESP_BT_OCTET16_LEN];      /* Link Key */
-
-/// Default GATT interface id
-#define ESP_DEFAULT_GATT_IF             0xff
-
-#define ESP_BLE_CONN_INT_MIN                0x0006       /*!< relate to BTM_BLE_CONN_INT_MIN in stack/btm_ble_api.h */
-#define ESP_BLE_CONN_INT_MAX                0x0C80       /*!< relate to BTM_BLE_CONN_INT_MAX in stack/btm_ble_api.h */
-#define ESP_BLE_CONN_LATENCY_MAX            500          /*!< relate to ESP_BLE_CONN_LATENCY_MAX in stack/btm_ble_api.h */
-#define ESP_BLE_CONN_SUP_TOUT_MIN           0x000A       /*!< relate to BTM_BLE_CONN_SUP_TOUT_MIN in stack/btm_ble_api.h */
-#define ESP_BLE_CONN_SUP_TOUT_MAX           0x0C80       /*!< relate to ESP_BLE_CONN_SUP_TOUT_MAX in stack/btm_ble_api.h */
-#define ESP_BLE_CONN_PARAM_UNDEF            0xffff       /* use this value when a specific value not to be overwritten */ /* relate to ESP_BLE_CONN_PARAM_UNDEF in stack/btm_ble_api.h */
-#define ESP_BLE_SCAN_PARAM_UNDEF            0xffffffff   /* relate to ESP_BLE_SCAN_PARAM_UNDEF in stack/btm_ble_api.h */
-
-/// Check the param is valid or not
-#define ESP_BLE_IS_VALID_PARAM(x, min, max)  (((x) >= (min) && (x) <= (max)) || ((x) == ESP_BLE_CONN_PARAM_UNDEF))
-
-/// UUID type
-typedef struct {
-#define ESP_UUID_LEN_16     2
-#define ESP_UUID_LEN_32     4
-#define ESP_UUID_LEN_128    16
-    uint16_t len;							/*!< UUID length, 16bit, 32bit or 128bit */
-    union {
-        uint16_t    uuid16;
-        uint32_t    uuid32;
-        uint8_t     uuid128[ESP_UUID_LEN_128];
-    } uuid;									/*!< UUID */
-} __attribute__((packed)) esp_bt_uuid_t;
-
-/// Bluetooth device type
-typedef enum {
-    ESP_BT_DEVICE_TYPE_BREDR   = 0x01,
-    ESP_BT_DEVICE_TYPE_BLE     = 0x02,
-    ESP_BT_DEVICE_TYPE_DUMO    = 0x03,
-} esp_bt_dev_type_t;
-
-/// Bluetooth address length
-#define ESP_BD_ADDR_LEN     6
-
-/// Bluetooth device address
-typedef uint8_t esp_bd_addr_t[ESP_BD_ADDR_LEN];
-
-/// BLE device address type
-typedef enum {
-    BLE_ADDR_TYPE_PUBLIC        = 0x00,
-    BLE_ADDR_TYPE_RANDOM        = 0x01,
-    BLE_ADDR_TYPE_RPA_PUBLIC    = 0x02,
-    BLE_ADDR_TYPE_RPA_RANDOM    = 0x03,
-} esp_ble_addr_type_t;
-
-/// Used to exchange the encryption key in the init key & response key
-#define ESP_BLE_ENC_KEY_MASK    (1 << 0)            /* relate to BTM_BLE_ENC_KEY_MASK in stack/btm_api.h */
-/// Used to exchange the IRK key in the init key & response key
-#define ESP_BLE_ID_KEY_MASK     (1 << 1)            /* relate to BTM_BLE_ID_KEY_MASK in stack/btm_api.h */
-/// Used to exchange the CSRK key in the init key & response key
-#define ESP_BLE_CSR_KEY_MASK    (1 << 2)            /* relate to BTM_BLE_CSR_KEY_MASK in stack/btm_api.h */
-/// Used to exchange the link key(this key just used in the BLE & BR/EDR coexist mode) in the init key & response key
-#define ESP_BLE_LINK_KEY_MASK   (1 << 3)            /* relate to BTM_BLE_LINK_KEY_MASK in stack/btm_api.h */
-typedef uint8_t esp_ble_key_mask_t;            /* the key mask type */
-
-/// Minimum of the application id
-#define ESP_APP_ID_MIN  0x0000
-/// Maximum of the application id
-#define ESP_APP_ID_MAX  0x7fff
-
-#define ESP_BD_ADDR_STR         "%02x:%02x:%02x:%02x:%02x:%02x"
-#define ESP_BD_ADDR_HEX(addr)   addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif     /* __ESP_BT_DEFS_H__ */
diff --git a/tools/sdk/include/bt/esp_bt_device.h b/tools/sdk/include/bt/esp_bt_device.h
deleted file mode 100644
index 76fb1b9d34f..00000000000
--- a/tools/sdk/include/bt/esp_bt_device.h
+++ /dev/null
@@ -1,57 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_BT_DEVICE_H__
-#define __ESP_BT_DEVICE_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-#include "esp_bt_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *
- * @brief      Get bluetooth device address.  Must use after "esp_bluedroid_enable".
- *
- * @return     bluetooth device address (six bytes), or NULL if bluetooth stack is not enabled
- */
-const uint8_t *esp_bt_dev_get_address(void);
-
-
-/**
- * @brief           Set bluetooth device name. This function should be called after esp_bluedroid_enable()
- *                  completes successfully.
- *                  A BR/EDR/LE device type shall have a single Bluetooth device name which shall be
- *                  identical irrespective of the physical channel used to perform the name discovery procedure.
- *
- * @param[in]       name : device name to be set
- *
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_ERR_INVALID_ARG : if name is NULL pointer or empty, or string length out of limit
- *                  - ESP_ERR_INVALID_STATE : if bluetooth stack is not yet enabled
- *                  - ESP_FAIL : others
- */
-esp_err_t esp_bt_dev_set_device_name(const char *name);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __ESP_BT_DEVICE_H__ */
diff --git a/tools/sdk/include/bt/esp_bt_main.h b/tools/sdk/include/bt/esp_bt_main.h
deleted file mode 100644
index fad010d2c2b..00000000000
--- a/tools/sdk/include/bt/esp_bt_main.h
+++ /dev/null
@@ -1,81 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_BT_MAIN_H__
-#define __ESP_BT_MAIN_H__
-
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Bluetooth stack status type, to indicate whether the bluetooth stack is ready
- */
-typedef enum {
-    ESP_BLUEDROID_STATUS_UNINITIALIZED   = 0,        /*!< Bluetooth not initialized */
-    ESP_BLUEDROID_STATUS_INITIALIZED,                /*!< Bluetooth initialized but not enabled */
-    ESP_BLUEDROID_STATUS_ENABLED                     /*!< Bluetooth initialized and enabled */
-} esp_bluedroid_status_t;
-
-/**
- * @brief     Get bluetooth stack status
- *
- * @return    Bluetooth stack status
- *
- */
-esp_bluedroid_status_t esp_bluedroid_get_status(void);
-    
-/**
- * @brief     Enable bluetooth, must after esp_bluedroid_init()
- *
- * @return
- *            - ESP_OK : Succeed
- *            - Other  : Failed
- */
-esp_err_t esp_bluedroid_enable(void);
-
-/**
- * @brief     Disable bluetooth, must prior to esp_bluedroid_deinit()
- *
- * @return
- *            - ESP_OK : Succeed
- *            - Other  : Failed
- */
-esp_err_t esp_bluedroid_disable(void);
-
-/**
- * @brief     Init and alloc the resource for bluetooth, must be prior to every bluetooth stuff
- *
- * @return
- *            - ESP_OK : Succeed
- *            - Other  : Failed
- */
-esp_err_t esp_bluedroid_init(void);
-
-/**
- * @brief     Deinit and free the resource for bluetooth, must be after every bluetooth stuff
- *
- * @return
- *            - ESP_OK : Succeed
- *            - Other  : Failed
- */
-esp_err_t esp_bluedroid_deinit(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_BT_MAIN_H__ */
diff --git a/tools/sdk/include/bt/esp_gap_ble_api.h b/tools/sdk/include/bt/esp_gap_ble_api.h
deleted file mode 100644
index 12bc48f1b10..00000000000
--- a/tools/sdk/include/bt/esp_gap_ble_api.h
+++ /dev/null
@@ -1,1250 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_GAP_BLE_API_H__
-#define __ESP_GAP_BLE_API_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "esp_err.h"
-#include "esp_bt_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**@{
- * BLE_ADV_DATA_FLAG data flag bit definition used for advertising data flag
- */
-#define ESP_BLE_ADV_FLAG_LIMIT_DISC         (0x01 << 0)
-#define ESP_BLE_ADV_FLAG_GEN_DISC           (0x01 << 1)
-#define ESP_BLE_ADV_FLAG_BREDR_NOT_SPT      (0x01 << 2)
-#define ESP_BLE_ADV_FLAG_DMT_CONTROLLER_SPT (0x01 << 3)
-#define ESP_BLE_ADV_FLAG_DMT_HOST_SPT       (0x01 << 4)
-#define ESP_BLE_ADV_FLAG_NON_LIMIT_DISC     (0x00 )
-/**
- * @}
- */
-
-/* relate to BTM_LE_KEY_xxx in stack/btm_api.h */
-#define ESP_LE_KEY_NONE                    0                                                                         /* relate to BTM_LE_KEY_NONE in stack/btm_api.h */
-#define ESP_LE_KEY_PENC                    (1 << 0)   /*!< encryption key, encryption information of peer device */  /* relate to BTM_LE_KEY_PENC in stack/btm_api.h */
-#define ESP_LE_KEY_PID                     (1 << 1)   /*!< identity key of the peer device */                        /* relate to BTM_LE_KEY_PID in stack/btm_api.h */
-#define ESP_LE_KEY_PCSRK                   (1 << 2)   /*!< peer SRK */                                               /* relate to BTM_LE_KEY_PCSRK in stack/btm_api.h */
-#define ESP_LE_KEY_PLK                     (1 << 3)   /*!< Link key*/                                                /* relate to BTM_LE_KEY_PLK in stack/btm_api.h */
-#define ESP_LE_KEY_LLK                     (ESP_LE_KEY_PLK << 4)                                                     /* relate to BTM_LE_KEY_LLK in stack/btm_api.h */
-#define ESP_LE_KEY_LENC                    (ESP_LE_KEY_PENC << 4)   /*!< master role security information:div */     /* relate to BTM_LE_KEY_LENC in stack/btm_api.h */
-#define ESP_LE_KEY_LID                     (ESP_LE_KEY_PID << 4)    /*!< master device ID key */                     /* relate to BTM_LE_KEY_LID in stack/btm_api.h */
-#define ESP_LE_KEY_LCSRK                   (ESP_LE_KEY_PCSRK << 4)  /*!< local CSRK has been deliver to peer */      /* relate to BTM_LE_KEY_LCSRK in stack/btm_api.h */
-typedef uint8_t esp_ble_key_type_t;
-
-/* relate to BTM_LE_AUTH_xxx in stack/btm_api.h */
-#define ESP_LE_AUTH_NO_BOND                 0x00                                     /*!< 0*/                     /* relate to BTM_LE_AUTH_NO_BOND in stack/btm_api.h */
-#define ESP_LE_AUTH_BOND                    0x01                                     /*!< 1 << 0 */               /* relate to BTM_LE_AUTH_BOND in stack/btm_api.h */
-#define ESP_LE_AUTH_REQ_MITM                (1 << 2)                                 /*!< 1 << 2 */               /* relate to BTM_LE_AUTH_REQ_MITM in stack/btm_api.h */
-#define ESP_LE_AUTH_REQ_BOND_MITM           (ESP_LE_AUTH_BOND | ESP_LE_AUTH_REQ_MITM)/*!< 0101*/
-#define ESP_LE_AUTH_REQ_SC_ONLY             (1 << 3)                                 /*!< 1 << 3 */               /* relate to BTM_LE_AUTH_REQ_SC_ONLY in stack/btm_api.h */
-#define ESP_LE_AUTH_REQ_SC_BOND             (ESP_LE_AUTH_BOND | ESP_LE_AUTH_REQ_SC_ONLY)            /*!< 1001 */  /* relate to BTM_LE_AUTH_REQ_SC_BOND in stack/btm_api.h */
-#define ESP_LE_AUTH_REQ_SC_MITM             (ESP_LE_AUTH_REQ_MITM | ESP_LE_AUTH_REQ_SC_ONLY)        /*!< 1100 */  /* relate to BTM_LE_AUTH_REQ_SC_MITM in stack/btm_api.h */
-#define ESP_LE_AUTH_REQ_SC_MITM_BOND        (ESP_LE_AUTH_REQ_MITM | ESP_LE_AUTH_REQ_SC_ONLY | ESP_LE_AUTH_BOND)   /*!< 1101 */  /* relate to BTM_LE_AUTH_REQ_SC_MITM_BOND in stack/btm_api.h */
-typedef uint8_t   esp_ble_auth_req_t;         /*!< combination of the above bit pattern */
-
-#define ESP_BLE_ONLY_ACCEPT_SPECIFIED_AUTH_DISABLE 0
-#define ESP_BLE_ONLY_ACCEPT_SPECIFIED_AUTH_ENABLE  1
-
-#define ESP_BLE_OOB_DISABLE 0
-#define ESP_BLE_OOB_ENABLE  1
-
-/* relate to BTM_IO_CAP_xxx in stack/btm_api.h */
-#define ESP_IO_CAP_OUT                      0   /*!< DisplayOnly */         /* relate to BTM_IO_CAP_OUT in stack/btm_api.h */
-#define ESP_IO_CAP_IO                       1   /*!< DisplayYesNo */        /* relate to BTM_IO_CAP_IO in stack/btm_api.h */
-#define ESP_IO_CAP_IN                       2   /*!< KeyboardOnly */        /* relate to BTM_IO_CAP_IN in stack/btm_api.h */
-#define ESP_IO_CAP_NONE                     3   /*!< NoInputNoOutput */     /* relate to BTM_IO_CAP_NONE in stack/btm_api.h */
-#define ESP_IO_CAP_KBDISP                   4   /*!< Keyboard display */    /* relate to BTM_IO_CAP_KBDISP in stack/btm_api.h */
-
-#define ESP_BLE_APPEARANCE_UNKNOWN                 0x0000 /* relate to BTM_BLE_APPEARANCE_UNKNOWN in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_PHONE           0x0040 /* relate to BTM_BLE_APPEARANCE_GENERIC_PHONE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_COMPUTER        0x0080 /* relate to BTM_BLE_APPEARANCE_GENERIC_COMPUTER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_WATCH           0x00C0 /* relate to BTM_BLE_APPEARANCE_GENERIC_WATCH in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_SPORTS_WATCH            0x00C1 /* relate to BTM_BLE_APPEARANCE_SPORTS_WATCH in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_CLOCK           0x0100 /* relate to BTM_BLE_APPEARANCE_GENERIC_CLOCK in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_DISPLAY         0x0140 /* relate to BTM_BLE_APPEARANCE_GENERIC_DISPLAY in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_REMOTE          0x0180 /* relate to BTM_BLE_APPEARANCE_GENERIC_REMOTE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_EYEGLASSES      0x01C0 /* relate to BTM_BLE_APPEARANCE_GENERIC_EYEGLASSES in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_TAG             0x0200 /* relate to BTM_BLE_APPEARANCE_GENERIC_TAG in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_KEYRING         0x0240 /* relate to BTM_BLE_APPEARANCE_GENERIC_KEYRING in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_MEDIA_PLAYER    0x0280 /* relate to BTM_BLE_APPEARANCE_GENERIC_MEDIA_PLAYER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_BARCODE_SCANNER 0x02C0 /* relate to BTM_BLE_APPEARANCE_GENERIC_BARCODE_SCANNER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_THERMOMETER     0x0300 /* relate to BTM_BLE_APPEARANCE_GENERIC_THERMOMETER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_THERMOMETER_EAR         0x0301 /* relate to BTM_BLE_APPEARANCE_THERMOMETER_EAR in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_HEART_RATE      0x0340 /* relate to BTM_BLE_APPEARANCE_GENERIC_HEART_RATE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_HEART_RATE_BELT         0x0341 /* relate to BTM_BLE_APPEARANCE_HEART_RATE_BELT in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE  0x0380 /* relate to BTM_BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_BLOOD_PRESSURE_ARM      0x0381 /* relate to BTM_BLE_APPEARANCE_BLOOD_PRESSURE_ARM in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_BLOOD_PRESSURE_WRIST    0x0382 /* relate to BTM_BLE_APPEARANCE_BLOOD_PRESSURE_WRIST in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_HID             0x03C0 /* relate to BTM_BLE_APPEARANCE_GENERIC_HID in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_HID_KEYBOARD            0x03C1 /* relate to BTM_BLE_APPEARANCE_HID_KEYBOARD in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_HID_MOUSE               0x03C2 /* relate to BTM_BLE_APPEARANCE_HID_MOUSE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_HID_JOYSTICK            0x03C3 /* relate to BTM_BLE_APPEARANCE_HID_JOYSTICK in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_HID_GAMEPAD             0x03C4 /* relate to BTM_BLE_APPEARANCE_HID_GAMEPAD in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_HID_DIGITIZER_TABLET    0x03C5 /* relate to BTM_BLE_APPEARANCE_HID_DIGITIZER_TABLET in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_HID_CARD_READER         0x03C6 /* relate to BTM_BLE_APPEARANCE_HID_CARD_READER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_HID_DIGITAL_PEN         0x03C7 /* relate to BTM_BLE_APPEARANCE_HID_DIGITAL_PEN in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_HID_BARCODE_SCANNER     0x03C8 /* relate to BTM_BLE_APPEARANCE_HID_BARCODE_SCANNER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_GLUCOSE         0x0400 /* relate to BTM_BLE_APPEARANCE_GENERIC_GLUCOSE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_WALKING         0x0440 /* relate to BTM_BLE_APPEARANCE_GENERIC_WALKING in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_WALKING_IN_SHOE         0x0441 /* relate to BTM_BLE_APPEARANCE_WALKING_IN_SHOE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_WALKING_ON_SHOE         0x0442 /* relate to BTM_BLE_APPEARANCE_WALKING_ON_SHOE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_WALKING_ON_HIP          0x0443 /* relate to BTM_BLE_APPEARANCE_WALKING_ON_HIP in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_CYCLING         0x0480 /* relate to BTM_BLE_APPEARANCE_GENERIC_CYCLING in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_CYCLING_COMPUTER        0x0481 /* relate to BTM_BLE_APPEARANCE_CYCLING_COMPUTER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_CYCLING_SPEED           0x0482 /* relate to BTM_BLE_APPEARANCE_CYCLING_SPEED in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_CYCLING_CADENCE         0x0483 /* relate to BTM_BLE_APPEARANCE_CYCLING_CADENCE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_CYCLING_POWER           0x0484 /* relate to BTM_BLE_APPEARANCE_CYCLING_POWER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_CYCLING_SPEED_CADENCE   0x0485 /* relate to BTM_BLE_APPEARANCE_CYCLING_SPEED_CADENCE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_PULSE_OXIMETER  0x0C40 /* relate to BTM_BLE_APPEARANCE_GENERIC_PULSE_OXIMETER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP 0x0C41 /* relate to BTM_BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_PULSE_OXIMETER_WRIST    0x0C42 /* relate to BTM_BLE_APPEARANCE_PULSE_OXIMETER_WRIST in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_WEIGHT          0x0C80 /* relate to BTM_BLE_APPEARANCE_GENERIC_WEIGHT in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_PERSONAL_MOBILITY_DEVICE    0x0CC0 /* relate to BTM_BLE_APPEARANCE_GENERIC_PERSONAL_MOBILITY_DEVICE in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_POWERED_WHEELCHAIR                  0x0CC1 /* relate to BTM_BLE_APPEARANCE_POWERED_WHEELCHAIR in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_MOBILITY_SCOOTER                    0x0CC2 /* relate to BTM_BLE_APPEARANCE_MOBILITY_SCOOTER in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_CONTINUOUS_GLUCOSE_MONITOR  0x0D00 /* relate to BTM_BLE_APPEARANCE_GENERIC_CONTINUOUS_GLUCOSE_MONITOR in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_INSULIN_PUMP                0x0D40 /* relate to BTM_BLE_APPEARANCE_GENERIC_INSULIN_PUMP in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_INSULIN_PUMP_DURABLE_PUMP           0x0D41 /* relate to BTM_BLE_APPEARANCE_INSULIN_PUMP_DURABLE_PUMP in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_INSULIN_PUMP_PATCH_PUMP             0x0D44 /* relate to BTM_BLE_APPEARANCE_INSULIN_PUMP_PATCH_PUMP in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_INSULIN_PEN                         0x0D48 /* relate to BTM_BLE_APPEARANCE_INSULIN_PEN in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_MEDICATION_DELIVERY         0x0D80 /* relate to BTM_BLE_APPEARANCE_GENERIC_MEDICATION_DELIVERY in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS  0x1440             /* relate to BTM_BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION 0x1441             /* relate to BTM_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION_AND_NAV     0x1442 /* relate to BTM_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION_AND_NAV in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION_POD         0x1443 /* relate to BTM_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION_POD in stack/btm_ble_api.h */
-#define ESP_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION_POD_AND_NAV 0x1444 /* relate to BTM_BLE_APPEARANCE_OUTDOOR_SPORTS_LOCATION_POD_AND_NAV in stack/btm_ble_api.h */
-
-typedef uint8_t esp_ble_io_cap_t;               /*!< combination of the io capability */
-
-/// GAP BLE callback event type
-typedef enum {
-    ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT        = 0,       /*!< When advertising data set complete, the event comes */
-    ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT,             /*!< When scan response data set complete, the event comes */
-    ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT,                /*!< When scan parameters set complete, the event comes */
-    ESP_GAP_BLE_SCAN_RESULT_EVT,                            /*!< When one scan result ready, the event comes each time */
-    ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT,              /*!< When raw advertising data set complete, the event comes */
-    ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT,         /*!< When raw advertising data set complete, the event comes */
-    ESP_GAP_BLE_ADV_START_COMPLETE_EVT,                     /*!< When start advertising complete, the event comes */
-    ESP_GAP_BLE_SCAN_START_COMPLETE_EVT,                    /*!< When start scan complete, the event comes */
-    ESP_GAP_BLE_AUTH_CMPL_EVT,                              /* Authentication complete indication. */
-    ESP_GAP_BLE_KEY_EVT,                                    /* BLE  key event for peer device keys */
-    ESP_GAP_BLE_SEC_REQ_EVT,                                /* BLE  security request */
-    ESP_GAP_BLE_PASSKEY_NOTIF_EVT,                          /* passkey notification event */
-    ESP_GAP_BLE_PASSKEY_REQ_EVT,                            /* passkey request event */
-    ESP_GAP_BLE_OOB_REQ_EVT,                                /* OOB request event */
-    ESP_GAP_BLE_LOCAL_IR_EVT,                               /* BLE local IR event */
-    ESP_GAP_BLE_LOCAL_ER_EVT,                               /* BLE local ER event */
-    ESP_GAP_BLE_NC_REQ_EVT,                                 /* Numeric Comparison request event */
-    ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT,                      /*!< When stop adv complete, the event comes */
-    ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT,                     /*!< When stop scan complete, the event comes */
-    ESP_GAP_BLE_SET_STATIC_RAND_ADDR_EVT,                   /*!< When set the static rand address complete, the event comes */
-    ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT,                     /*!< When update connection parameters complete, the event comes */
-    ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT,                /*!< When set pkt length complete, the event comes */
-    ESP_GAP_BLE_SET_LOCAL_PRIVACY_COMPLETE_EVT,             /*!< When  Enable/disable privacy on the local device complete, the event comes */
-    ESP_GAP_BLE_REMOVE_BOND_DEV_COMPLETE_EVT,               /*!< When remove the bond device complete, the event comes */
-    ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT,                /*!< When clear the bond device clear complete, the event comes */
-    ESP_GAP_BLE_GET_BOND_DEV_COMPLETE_EVT,                  /*!< When get the bond device list complete, the event comes */
-    ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT,                     /*!< When read the rssi complete, the event comes */
-    ESP_GAP_BLE_UPDATE_WHITELIST_COMPLETE_EVT,              /*!< When add or remove whitelist complete, the event comes */
-    ESP_GAP_BLE_UPDATE_DUPLICATE_EXCEPTIONAL_LIST_COMPLETE_EVT,  /*!< When update duplicate exceptional list complete, the event comes */
-    ESP_GAP_BLE_EVT_MAX,
-} esp_gap_ble_cb_event_t;
-/// This is the old name, just for backwards compatibility
-#define ESP_GAP_BLE_ADD_WHITELIST_COMPLETE_EVT ESP_GAP_BLE_UPDATE_WHITELIST_COMPLETE_EVT
-
-/// Advertising data maximum length
-#define ESP_BLE_ADV_DATA_LEN_MAX               31
-/// Scan response data maximum length
-#define ESP_BLE_SCAN_RSP_DATA_LEN_MAX          31
-
-/* relate to BTM_BLE_AD_TYPE_xxx in stack/btm_ble_api.h */
-/// The type of advertising data(not adv_type)
-typedef enum {
-    ESP_BLE_AD_TYPE_FLAG                     = 0x01,    /* relate to BTM_BLE_AD_TYPE_FLAG in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_16SRV_PART               = 0x02,    /* relate to BTM_BLE_AD_TYPE_16SRV_PART in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_16SRV_CMPL               = 0x03,    /* relate to BTM_BLE_AD_TYPE_16SRV_CMPL in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_32SRV_PART               = 0x04,    /* relate to BTM_BLE_AD_TYPE_32SRV_PART in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_32SRV_CMPL               = 0x05,    /* relate to BTM_BLE_AD_TYPE_32SRV_CMPL in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_128SRV_PART              = 0x06,    /* relate to BTM_BLE_AD_TYPE_128SRV_PART in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_128SRV_CMPL              = 0x07,    /* relate to BTM_BLE_AD_TYPE_128SRV_CMPL in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_NAME_SHORT               = 0x08,    /* relate to BTM_BLE_AD_TYPE_NAME_SHORT in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_NAME_CMPL                = 0x09,    /* relate to BTM_BLE_AD_TYPE_NAME_CMPL in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_TX_PWR                   = 0x0A,    /* relate to BTM_BLE_AD_TYPE_TX_PWR in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_DEV_CLASS                = 0x0D,    /* relate to BTM_BLE_AD_TYPE_DEV_CLASS in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_SM_TK                    = 0x10,    /* relate to BTM_BLE_AD_TYPE_SM_TK in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_SM_OOB_FLAG              = 0x11,    /* relate to BTM_BLE_AD_TYPE_SM_OOB_FLAG in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_INT_RANGE                = 0x12,    /* relate to BTM_BLE_AD_TYPE_INT_RANGE in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_SOL_SRV_UUID             = 0x14,    /* relate to BTM_BLE_AD_TYPE_SOL_SRV_UUID in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_128SOL_SRV_UUID          = 0x15,    /* relate to BTM_BLE_AD_TYPE_128SOL_SRV_UUID in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_SERVICE_DATA             = 0x16,    /* relate to BTM_BLE_AD_TYPE_SERVICE_DATA in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_PUBLIC_TARGET            = 0x17,    /* relate to BTM_BLE_AD_TYPE_PUBLIC_TARGET in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_RANDOM_TARGET            = 0x18,    /* relate to BTM_BLE_AD_TYPE_RANDOM_TARGET in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_APPEARANCE               = 0x19,    /* relate to BTM_BLE_AD_TYPE_APPEARANCE in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_ADV_INT                  = 0x1A,    /* relate to BTM_BLE_AD_TYPE_ADV_INT in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_LE_DEV_ADDR              = 0x1b,    /* relate to BTM_BLE_AD_TYPE_LE_DEV_ADDR in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_LE_ROLE                  = 0x1c,    /* relate to BTM_BLE_AD_TYPE_LE_ROLE in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_SPAIR_C256               = 0x1d,    /* relate to BTM_BLE_AD_TYPE_SPAIR_C256 in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_SPAIR_R256               = 0x1e,    /* relate to BTM_BLE_AD_TYPE_SPAIR_R256 in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_32SOL_SRV_UUID           = 0x1f,    /* relate to BTM_BLE_AD_TYPE_32SOL_SRV_UUID in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_32SERVICE_DATA           = 0x20,    /* relate to BTM_BLE_AD_TYPE_32SERVICE_DATA in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_128SERVICE_DATA          = 0x21,    /* relate to BTM_BLE_AD_TYPE_128SERVICE_DATA in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_LE_SECURE_CONFIRM        = 0x22,    /* relate to BTM_BLE_AD_TYPE_LE_SECURE_CONFIRM in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_LE_SECURE_RANDOM         = 0x23,    /* relate to BTM_BLE_AD_TYPE_LE_SECURE_RANDOM in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_URI                      = 0x24,    /* relate to BTM_BLE_AD_TYPE_URI in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_INDOOR_POSITION          = 0x25,    /* relate to BTM_BLE_AD_TYPE_INDOOR_POSITION in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_TRANS_DISC_DATA          = 0x26,    /* relate to BTM_BLE_AD_TYPE_TRANS_DISC_DATA in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_LE_SUPPORT_FEATURE       = 0x27,    /* relate to BTM_BLE_AD_TYPE_LE_SUPPORT_FEATURE in stack/btm_ble_api.h */
-    ESP_BLE_AD_TYPE_CHAN_MAP_UPDATE          = 0x28,    /* relate to BTM_BLE_AD_TYPE_CHAN_MAP_UPDATE in stack/btm_ble_api.h */
-    ESP_BLE_AD_MANUFACTURER_SPECIFIC_TYPE    = 0xFF,    /* relate to BTM_BLE_AD_MANUFACTURER_SPECIFIC_TYPE in stack/btm_ble_api.h */
-} esp_ble_adv_data_type;
-
-/// Advertising mode
-typedef enum {
-    ADV_TYPE_IND                = 0x00,
-    ADV_TYPE_DIRECT_IND_HIGH    = 0x01,
-    ADV_TYPE_SCAN_IND           = 0x02,
-    ADV_TYPE_NONCONN_IND        = 0x03,
-    ADV_TYPE_DIRECT_IND_LOW     = 0x04,
-} esp_ble_adv_type_t;
-
-/// Advertising channel mask
-typedef enum {
-    ADV_CHNL_37     = 0x01,
-    ADV_CHNL_38     = 0x02,
-    ADV_CHNL_39     = 0x04,
-    ADV_CHNL_ALL    = 0x07,
-} esp_ble_adv_channel_t;
-
-typedef enum {
-    ///Allow both scan and connection requests from anyone
-    ADV_FILTER_ALLOW_SCAN_ANY_CON_ANY  = 0x00,
-    ///Allow both scan req from White List devices only and connection req from anyone
-    ADV_FILTER_ALLOW_SCAN_WLST_CON_ANY,
-    ///Allow both scan req from anyone and connection req from White List devices only
-    ADV_FILTER_ALLOW_SCAN_ANY_CON_WLST,
-    ///Allow scan and connection requests from White List devices only
-    ADV_FILTER_ALLOW_SCAN_WLST_CON_WLST,
-    ///Enumeration end value for advertising filter policy value check
-} esp_ble_adv_filter_t;
-
-
-/* relate to BTA_DM_BLE_SEC_xxx in bta/bta_api.h */
-typedef enum {
-    ESP_BLE_SEC_ENCRYPT = 1,            /* relate to BTA_DM_BLE_SEC_ENCRYPT in bta/bta_api.h. If the device has already
-                                           bonded, the stack will used LTK to encrypt with the remote device directly.
-                                           Else if the device hasn't bonded, the stack will used the default authentication request
-                                           used the esp_ble_gap_set_security_param function set by the user. */
-    ESP_BLE_SEC_ENCRYPT_NO_MITM,        /* relate to BTA_DM_BLE_SEC_ENCRYPT_NO_MITM in bta/bta_api.h. If the device has already
-                                           bonded, the stack will check the LTK Whether the authentication request has been met, if met, used the LTK
-                                           to encrypt with the remote device directly, else Re-pair with the remote device.
-                                           Else if the device hasn't bonded, the stack will used NO MITM authentication request in the current link instead of
-                                           used the authreq in the esp_ble_gap_set_security_param function set by the user. */
-    ESP_BLE_SEC_ENCRYPT_MITM,           /* relate to BTA_DM_BLE_SEC_ENCRYPT_MITM in bta/bta_api.h. If the device has already
-                                           bonded, the stack will check the LTK Whether the authentication request has been met, if met, used the LTK
-                                           to encrypt with the remote device directly, else Re-pair with the remote device.
-                                           Else if the device hasn't bonded, the stack will used MITM authentication request in the current link instead of
-                                           used the authreq in the esp_ble_gap_set_security_param function set by the user. */
-}esp_ble_sec_act_t;
-
-typedef enum {
-    ESP_BLE_SM_PASSKEY = 0,
-    /* Authentication requirements of local device */
-    ESP_BLE_SM_AUTHEN_REQ_MODE,
-    /* The IO capability of local device */
-    ESP_BLE_SM_IOCAP_MODE,
-    /* Initiator Key Distribution/Generation */
-    ESP_BLE_SM_SET_INIT_KEY,
-    /* Responder Key Distribution/Generation */
-    ESP_BLE_SM_SET_RSP_KEY,
-    /* Maximum Encryption key size to support */
-    ESP_BLE_SM_MAX_KEY_SIZE,
-    /* Minimum Encryption key size requirement from Peer */
-    ESP_BLE_SM_MIN_KEY_SIZE,
-    /* Set static Passkey */
-    ESP_BLE_SM_SET_STATIC_PASSKEY,
-    /* Reset static Passkey */
-    ESP_BLE_SM_CLEAR_STATIC_PASSKEY,
-    /* Accept only specified SMP Authentication requirement */
-    ESP_BLE_SM_ONLY_ACCEPT_SPECIFIED_SEC_AUTH,
-    /* Enable/Disable OOB support */
-    ESP_BLE_SM_OOB_SUPPORT,
-    ESP_BLE_SM_MAX_PARAM,
-} esp_ble_sm_param_t;
-
-/// Advertising parameters
-typedef struct {
-    uint16_t                adv_int_min;        /*!< Minimum advertising interval for
-                                                  undirected and low duty cycle directed advertising.
-                                                  Range: 0x0020 to 0x4000 Default: N = 0x0800 (1.28 second)
-                                                  Time = N * 0.625 msec Time Range: 20 ms to 10.24 sec */
-    uint16_t                adv_int_max;        /*!< Maximum advertising interval for
-                                                  undirected and low duty cycle directed advertising.
-                                                  Range: 0x0020 to 0x4000 Default: N = 0x0800 (1.28 second)
-                                                  Time = N * 0.625 msec Time Range: 20 ms to 10.24 sec Advertising max interval */
-    esp_ble_adv_type_t      adv_type;           /*!< Advertising type */
-    esp_ble_addr_type_t     own_addr_type;      /*!< Owner bluetooth device address type */
-    esp_bd_addr_t           peer_addr;          /*!< Peer device bluetooth device address */
-    esp_ble_addr_type_t     peer_addr_type;     /*!< Peer device bluetooth device address type, only support public address type and random address type */
-    esp_ble_adv_channel_t   channel_map;        /*!< Advertising channel map */
-    esp_ble_adv_filter_t    adv_filter_policy;  /*!< Advertising filter policy */
-} esp_ble_adv_params_t;
-
-/// Advertising data content, according to "Supplement to the Bluetooth Core Specification"
-typedef struct {
-    bool                    set_scan_rsp;           /*!< Set this advertising data as scan response or not*/
-    bool                    include_name;           /*!< Advertising data include device name or not */
-    bool                    include_txpower;        /*!< Advertising data include TX power */
-    int                     min_interval;           /*!< Advertising data show slave preferred connection min interval.
-                                                    The connection interval in the following manner:
-                                                    connIntervalmin = Conn_Interval_Min * 1.25 ms
-                                                    Conn_Interval_Min range: 0x0006 to 0x0C80
-                                                    Value of 0xFFFF indicates no specific minimum.
-                                                    Values not defined above are reserved for future use.*/
-
-    int                     max_interval;           /*!< Advertising data show slave preferred connection max interval.
-                                                    The connection interval in the following manner:
-                                                    connIntervalmax = Conn_Interval_Max * 1.25 ms
-                                                    Conn_Interval_Max range: 0x0006 to 0x0C80
-                                                    Conn_Interval_Max shall be equal to or greater than the Conn_Interval_Min.
-                                                    Value of 0xFFFF indicates no specific maximum.
-                                                    Values not defined above are reserved for future use.*/
-
-    int                     appearance;             /*!< External appearance of device */
-    uint16_t                manufacturer_len;       /*!< Manufacturer data length */
-    uint8_t                 *p_manufacturer_data;   /*!< Manufacturer data point */
-    uint16_t                service_data_len;       /*!< Service data length */
-    uint8_t                 *p_service_data;        /*!< Service data point */
-    uint16_t                service_uuid_len;       /*!< Service uuid length */
-    uint8_t                 *p_service_uuid;        /*!< Service uuid array point */
-    uint8_t                 flag;                   /*!< Advertising flag of discovery mode, see BLE_ADV_DATA_FLAG detail */
-} esp_ble_adv_data_t;
-
-/// Ble scan type
-typedef enum {
-    BLE_SCAN_TYPE_PASSIVE   =   0x0,            /*!< Passive scan */
-    BLE_SCAN_TYPE_ACTIVE    =   0x1,            /*!< Active scan */
-} esp_ble_scan_type_t;
-
-/// Ble scan filter type
-typedef enum {
-    BLE_SCAN_FILTER_ALLOW_ALL           = 0x0,  /*!< Accept all :
-                                                  1. advertisement packets except directed advertising packets not addressed to this device (default). */
-    BLE_SCAN_FILTER_ALLOW_ONLY_WLST     = 0x1,  /*!< Accept only :
-                                                  1. advertisement packets from devices where the advertiser’s address is in the White list.
-                                                  2. Directed advertising packets which are not addressed for this device shall be ignored. */
-    BLE_SCAN_FILTER_ALLOW_UND_RPA_DIR   = 0x2,  /*!< Accept all :
-                                                  1. undirected advertisement packets, and
-                                                  2. directed advertising packets where the initiator address is a resolvable private address, and
-                                                  3. directed advertising packets addressed to this device. */
-    BLE_SCAN_FILTER_ALLOW_WLIST_PRA_DIR = 0x3,  /*!< Accept all :
-                                                  1. advertisement packets from devices where the advertiser’s address is in the White list, and
-                                                  2. directed advertising packets where the initiator address is a resolvable private address, and
-                                                  3. directed advertising packets addressed to this device.*/
-} esp_ble_scan_filter_t;
-
-/// Ble scan duplicate type
-typedef enum {
-    BLE_SCAN_DUPLICATE_DISABLE           = 0x0,  /*!< the Link Layer should generate advertising reports to the host for each packet received */
-    BLE_SCAN_DUPLICATE_ENABLE            = 0x1,  /*!< the Link Layer should filter out duplicate advertising reports to the Host */
-    BLE_SCAN_DUPLICATE_MAX               = 0x2,  /*!< 0x02 – 0xFF, Reserved for future use */
-} esp_ble_scan_duplicate_t;
-
-/// Ble scan parameters
-typedef struct {
-    esp_ble_scan_type_t     scan_type;              /*!< Scan type */
-    esp_ble_addr_type_t     own_addr_type;          /*!< Owner address type */
-    esp_ble_scan_filter_t   scan_filter_policy;     /*!< Scan filter policy */
-    uint16_t                scan_interval;          /*!< Scan interval. This is defined as the time interval from
-                                                      when the Controller started its last LE scan until it begins the subsequent LE scan.
-                                                      Range: 0x0004 to 0x4000 Default: 0x0010 (10 ms)
-                                                      Time = N * 0.625 msec
-                                                      Time Range: 2.5 msec to 10.24 seconds*/
-    uint16_t                scan_window;            /*!< Scan window. The duration of the LE scan. LE_Scan_Window
-                                                      shall be less than or equal to LE_Scan_Interval
-                                                      Range: 0x0004 to 0x4000 Default: 0x0010 (10 ms)
-                                                      Time = N * 0.625 msec
-                                                      Time Range: 2.5 msec to 10240 msec */
-    esp_ble_scan_duplicate_t  scan_duplicate;       /*!< The Scan_Duplicates parameter controls whether the Link Layer should filter out
-                                                        duplicate advertising reports (BLE_SCAN_DUPLICATE_ENABLE) to the Host, or if the Link Layer should generate
-                                                        advertising reports for each packet received */
-} esp_ble_scan_params_t;
-
-/// Connection update parameters
-typedef struct {
-    esp_bd_addr_t bda;                              /*!< Bluetooth device address */
-    uint16_t min_int;                               /*!< Min connection interval */
-    uint16_t max_int;                               /*!< Max connection interval */
-    uint16_t latency;                               /*!< Slave latency for the connection in number of connection events. Range: 0x0000 to 0x01F3 */
-    uint16_t timeout;                               /*!< Supervision timeout for the LE Link. Range: 0x000A to 0x0C80.
-                                                      Mandatory Range: 0x000A to 0x0C80 Time = N * 10 msec
-                                                      Time Range: 100 msec to 32 seconds */
-} esp_ble_conn_update_params_t;
-
-/**
-* @brief BLE pkt date length keys
-*/
-typedef struct
-{
-    uint16_t rx_len;                   /*!< pkt rx data length value */
-    uint16_t tx_len;                   /*!< pkt tx data length value */
-}esp_ble_pkt_data_length_params_t;
-
-/**
-* @brief BLE encryption keys
-*/
-typedef struct
-{
-    esp_bt_octet16_t     ltk;          /*!< The long term key*/
-    esp_bt_octet8_t      rand;         /*!< The random number*/
-    uint16_t             ediv;         /*!< The ediv value*/
-    uint8_t              sec_level;    /*!< The security level of the security link*/
-    uint8_t              key_size;     /*!< The key size(7~16) of the security link*/
-} esp_ble_penc_keys_t;                 /*!< The key type*/
-
-/**
-* @brief  BLE CSRK keys
-*/
-typedef struct
-{
-    uint32_t            counter;      /*!< The counter */
-    esp_bt_octet16_t    csrk;         /*!< The csrk key */
-    uint8_t             sec_level;    /*!< The security level */
-} esp_ble_pcsrk_keys_t;               /*!< The pcsrk key type */
-
-/**
-* @brief  BLE pid keys
-*/
-typedef struct
-{
-    esp_bt_octet16_t          irk;           /*!< The irk value */
-    esp_ble_addr_type_t       addr_type;     /*!< The address type */
-    esp_bd_addr_t             static_addr;   /*!< The static address */
-} esp_ble_pid_keys_t;                        /*!< The pid key type */
-
-/**
-* @brief  BLE Encryption reproduction keys
-*/
-typedef struct
-{
-    esp_bt_octet16_t  ltk;                  /*!< The long term key */
-    uint16_t          div;                  /*!< The div value */
-    uint8_t           key_size;             /*!< The key size of the security link */
-    uint8_t           sec_level;            /*!< The security level of the security link */
-} esp_ble_lenc_keys_t;                      /*!< The  key type */
-
-/**
-* @brief  BLE SRK keys
-*/
-typedef struct
-{
-    uint32_t          counter;              /*!< The counter value */
-    uint16_t          div;                  /*!< The div value */
-    uint8_t           sec_level;            /*!< The security level of the security link */
-    esp_bt_octet16_t  csrk;                 /*!< The csrk key value */
-} esp_ble_lcsrk_keys;                       /*!< The csrk key type */
-
-/**
-* @brief  Structure associated with ESP_KEY_NOTIF_EVT
-*/
-typedef struct
-{
-    esp_bd_addr_t  bd_addr;        /*!< peer address */
-    uint32_t       passkey;        /*!< the numeric value for comparison. If just_works, do not show this number to UI */
-} esp_ble_sec_key_notif_t;         /*!< BLE key notify type*/
-
-/**
-* @brief  Structure of the security request
-*/
-typedef struct
-{
-    esp_bd_addr_t  bd_addr;        /*!< peer address */
-} esp_ble_sec_req_t;               /*!< BLE security request type*/
-
-/**
-* @brief  union type of the security key value
-*/
-typedef union
-{
-    esp_ble_penc_keys_t   penc_key;       /*!< received peer encryption key */
-    esp_ble_pcsrk_keys_t  pcsrk_key;      /*!< received peer device SRK */
-    esp_ble_pid_keys_t    pid_key;        /*!< peer device ID key */
-    esp_ble_lenc_keys_t   lenc_key;       /*!< local encryption reproduction keys LTK = = d1(ER,DIV,0)*/
-    esp_ble_lcsrk_keys    lcsrk_key;      /*!< local device CSRK = d1(ER,DIV,1)*/
-} esp_ble_key_value_t;                    /*!< ble key value type*/
-
-/**
-* @brief  struct type of the bond key information value
-*/
-typedef struct
-{
-    esp_ble_key_mask_t    key_mask;       /*!< the key mask to indicate witch key is present */
-    esp_ble_penc_keys_t   penc_key;       /*!< received peer encryption key */
-    esp_ble_pcsrk_keys_t  pcsrk_key;      /*!< received peer device SRK */
-    esp_ble_pid_keys_t    pid_key;        /*!< peer device ID key */
-} esp_ble_bond_key_info_t;                /*!< ble bond key information value type */
-
-/**
-* @brief  struct type of the bond device value
-*/
-typedef struct
-{
-    esp_bd_addr_t  bd_addr;               /*!< peer address */
-    esp_ble_bond_key_info_t bond_key;     /*!< the bond key information */
-} esp_ble_bond_dev_t;                     /*!< the ble bond device type */
-
-
-/**
-* @brief  union type of the security key value
-*/
-typedef struct
-{
-    esp_bd_addr_t               bd_addr;        /*!< peer address */
-    esp_ble_key_type_t          key_type;       /*!< key type of the security link */
-    esp_ble_key_value_t         p_key_value;    /*!< the pointer to the key value */
-} esp_ble_key_t;                                /*!< the union to the ble key value type*/
-
-/**
-* @brief  structure type of the ble local id keys value
-*/
-typedef struct {
-    esp_bt_octet16_t       ir;                  /*!< the 16 bits of the ir value */
-    esp_bt_octet16_t       irk;                 /*!< the 16 bits of the ir key value */
-    esp_bt_octet16_t       dhk;                 /*!< the 16 bits of the dh key value */
-} esp_ble_local_id_keys_t;                      /*!< the structure of the ble local id keys value type*/
-
-
-/**
-  * @brief Structure associated with ESP_AUTH_CMPL_EVT
-  */
-typedef struct
-{
-    esp_bd_addr_t         bd_addr;               /*!< BD address peer device. */
-    bool                  key_present;           /*!< Valid link key value in key element */
-    esp_link_key          key;                   /*!< Link key associated with peer device. */
-    uint8_t               key_type;              /*!< The type of Link Key */
-    bool                  success;               /*!< TRUE of authentication succeeded, FALSE if failed. */
-    uint8_t               fail_reason;           /*!< The HCI reason/error code for when success=FALSE */
-    esp_ble_addr_type_t   addr_type;             /*!< Peer device address type */
-    esp_bt_dev_type_t     dev_type;              /*!< Device type */
-    esp_ble_auth_req_t    auth_mode;             /*!< authentication mode */
-} esp_ble_auth_cmpl_t;                           /*!< The ble authentication complete cb type */
-
-/**
-  * @brief union associated with ble security
-  */
-typedef union
-{
-    esp_ble_sec_key_notif_t    key_notif;      /*!< passkey notification */
-    esp_ble_sec_req_t          ble_req;        /*!< BLE SMP related request */
-    esp_ble_key_t              ble_key;        /*!< BLE SMP keys used when pairing */
-    esp_ble_local_id_keys_t    ble_id_keys;    /*!< BLE IR event */
-    esp_ble_auth_cmpl_t        auth_cmpl;      /*!< Authentication complete indication. */
-} esp_ble_sec_t;                               /*!< BLE security type */
-
-/// Sub Event of ESP_GAP_BLE_SCAN_RESULT_EVT
-typedef enum {
-    ESP_GAP_SEARCH_INQ_RES_EVT             = 0,      /*!< Inquiry result for a peer device. */
-    ESP_GAP_SEARCH_INQ_CMPL_EVT            = 1,      /*!< Inquiry complete. */
-    ESP_GAP_SEARCH_DISC_RES_EVT            = 2,      /*!< Discovery result for a peer device. */
-    ESP_GAP_SEARCH_DISC_BLE_RES_EVT        = 3,      /*!< Discovery result for BLE GATT based service on a peer device. */
-    ESP_GAP_SEARCH_DISC_CMPL_EVT           = 4,      /*!< Discovery complete. */
-    ESP_GAP_SEARCH_DI_DISC_CMPL_EVT        = 5,      /*!< Discovery complete. */
-    ESP_GAP_SEARCH_SEARCH_CANCEL_CMPL_EVT  = 6,      /*!< Search cancelled */
-    ESP_GAP_SEARCH_INQ_DISCARD_NUM_EVT     = 7,      /*!< The number of pkt discarded by flow control */
-} esp_gap_search_evt_t;
-
-/**
- * @brief Ble scan result event type, to indicate the
- *        result is scan response or advertising data or other
- */
-typedef enum {
-    ESP_BLE_EVT_CONN_ADV         = 0x00,        /*!< Connectable undirected advertising (ADV_IND) */
-    ESP_BLE_EVT_CONN_DIR_ADV     = 0x01,        /*!< Connectable directed advertising (ADV_DIRECT_IND) */
-    ESP_BLE_EVT_DISC_ADV         = 0x02,        /*!< Scannable undirected advertising (ADV_SCAN_IND) */
-    ESP_BLE_EVT_NON_CONN_ADV     = 0x03,        /*!< Non connectable undirected advertising (ADV_NONCONN_IND) */
-    ESP_BLE_EVT_SCAN_RSP         = 0x04,        /*!< Scan Response (SCAN_RSP) */
-} esp_ble_evt_type_t;
-
-typedef enum{
-    ESP_BLE_WHITELIST_REMOVE     = 0X00,    /*!< remove mac from whitelist */
-    ESP_BLE_WHITELIST_ADD        = 0X01,    /*!< add address to whitelist */
-}esp_ble_wl_opration_t;
-
-typedef enum {
-    ESP_BLE_DUPLICATE_EXCEPTIONAL_LIST_ADD      = 0,  /*!< Add device info into duplicate scan exceptional list */
-    ESP_BLE_DUPLICATE_EXCEPTIONAL_LIST_REMOVE,        /*!< Remove device info from duplicate scan exceptional list */
-    ESP_BLE_DUPLICATE_EXCEPTIONAL_LIST_CLEAN,         /*!< Clean duplicate scan exceptional list */
-} esp_bt_duplicate_exceptional_subcode_type_t;
-
-#define BLE_BIT(n) (1UL<<(n))
-
-typedef enum {
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_INFO_ADV_ADDR       = 0,  /*!< BLE advertising address , device info will be added into ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_ADDR_LIST */
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_INFO_MESH_LINK_ID,        /*!< BLE mesh link ID, it is for BLE mesh, device info will be added into ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_MESH_LINK_ID_LIST */
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_INFO_MESH_BEACON_TYPE,    /*!< BLE mesh beacon AD type, the format is | Len | 0x2B | Beacon Type | Beacon Data | */
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_INFO_MESH_PROV_SRV_ADV,   /*!< BLE mesh provisioning service uuid, the format is | 0x02 | 0x01 | flags | 0x03 | 0x03 | 0x1827 | .... |` */
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_INFO_MESH_PROXY_SRV_ADV,  /*!< BLE mesh adv with proxy service uuid, the format is | 0x02 | 0x01 | flags | 0x03 | 0x03 | 0x1828 | .... |` */
-} esp_ble_duplicate_exceptional_info_type_t;
-
-typedef enum {
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_ADDR_LIST                  = BLE_BIT(0),             /*!< duplicate scan exceptional addr list */
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_MESH_LINK_ID_LIST          = BLE_BIT(1),             /*!< duplicate scan exceptional mesh link ID list */
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_MESH_BEACON_TYPE_LIST      = BLE_BIT(2),             /*!< duplicate scan exceptional mesh beacon type list */
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_MESH_PROV_SRV_ADV_LIST     = BLE_BIT(3),             /*!< duplicate scan exceptional mesh adv with provisioning service uuid */
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_MESH_PROXY_SRV_ADV_LIST    = BLE_BIT(4),             /*!< duplicate scan exceptional mesh adv with provisioning service uuid */
-    ESP_BLE_DUPLICATE_SCAN_EXCEPTIONAL_ALL_LIST                   = 0xFFFF,                 /*!< duplicate scan exceptional all list */
-} esp_duplicate_scan_exceptional_list_type_t;
-
-typedef uint8_t esp_duplicate_info_t[ESP_BD_ADDR_LEN];
-
-/**
- * @brief Gap callback parameters union
- */
-typedef union {
-    /**
-     * @brief ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT
-     */
-    struct ble_adv_data_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the set advertising data operation success status */
-    } adv_data_cmpl;                                /*!< Event parameter of ESP_GAP_BLE_ADV_DATA_SET_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT
-     */
-    struct ble_scan_rsp_data_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the set scan response data operation success status */
-    } scan_rsp_data_cmpl;                           /*!< Event parameter of ESP_GAP_BLE_SCAN_RSP_DATA_SET_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT
-     */
-    struct ble_scan_param_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the set scan param operation success status */
-    } scan_param_cmpl;                              /*!< Event parameter of ESP_GAP_BLE_SCAN_PARAM_SET_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_SCAN_RESULT_EVT
-     */
-    struct ble_scan_result_evt_param {
-        esp_gap_search_evt_t search_evt;            /*!< Search event type */
-        esp_bd_addr_t bda;                          /*!< Bluetooth device address which has been searched */
-        esp_bt_dev_type_t dev_type;                 /*!< Device type */
-        esp_ble_addr_type_t ble_addr_type;          /*!< Ble device address type */
-        esp_ble_evt_type_t ble_evt_type;            /*!< Ble scan result event type */
-        int rssi;                                   /*!< Searched device's RSSI */
-        uint8_t  ble_adv[ESP_BLE_ADV_DATA_LEN_MAX + ESP_BLE_SCAN_RSP_DATA_LEN_MAX];     /*!< Received EIR */
-        int flag;                                   /*!< Advertising data flag bit */
-        int num_resps;                              /*!< Scan result number */
-        uint8_t adv_data_len;                       /*!< Adv data length */
-        uint8_t scan_rsp_len;                       /*!< Scan response length */
-        uint32_t num_dis;                          /*!< The number of discard packets */
-    } scan_rst;                                     /*!< Event parameter of ESP_GAP_BLE_SCAN_RESULT_EVT */
-    /**
-     * @brief ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT
-     */
-    struct ble_adv_data_raw_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the set raw advertising data operation success status */
-    } adv_data_raw_cmpl;                            /*!< Event parameter of ESP_GAP_BLE_ADV_DATA_RAW_SET_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT
-     */
-    struct ble_scan_rsp_data_raw_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the set raw advertising data operation success status */
-    } scan_rsp_data_raw_cmpl;                       /*!< Event parameter of ESP_GAP_BLE_SCAN_RSP_DATA_RAW_SET_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_ADV_START_COMPLETE_EVT
-     */
-    struct ble_adv_start_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate advertising start operation success status */
-    } adv_start_cmpl;                               /*!< Event parameter of ESP_GAP_BLE_ADV_START_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_SCAN_START_COMPLETE_EVT
-     */
-    struct ble_scan_start_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate scan start operation success status */
-    } scan_start_cmpl;                              /*!< Event parameter of ESP_GAP_BLE_SCAN_START_COMPLETE_EVT */
-
-    esp_ble_sec_t ble_security;                     /*!< ble gap security union type */
-    /**
-     * @brief ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT
-     */
-    struct ble_scan_stop_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate scan stop operation success status */
-    } scan_stop_cmpl;                               /*!< Event parameter of ESP_GAP_BLE_SCAN_STOP_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT
-     */
-    struct ble_adv_stop_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate adv stop operation success status */
-    } adv_stop_cmpl;                                /*!< Event parameter of ESP_GAP_BLE_ADV_STOP_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_SET_STATIC_RAND_ADDR_EVT
-     */
-    struct ble_set_rand_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate set static rand address operation success status */
-    } set_rand_addr_cmpl;                           /*!< Event parameter of ESP_GAP_BLE_SET_STATIC_RAND_ADDR_EVT */
-    /**
-     * @brief ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT
-     */
-    struct ble_update_conn_params_evt_param {
-        esp_bt_status_t status;                    /*!< Indicate update connection parameters success status */
-        esp_bd_addr_t bda;                         /*!< Bluetooth device address */
-        uint16_t min_int;                          /*!< Min connection interval */
-        uint16_t max_int;                          /*!< Max connection interval */
-        uint16_t latency;                          /*!< Slave latency for the connection in number of connection events. Range: 0x0000 to 0x01F3 */
-        uint16_t conn_int;                         /*!< Current connection interval */
-        uint16_t timeout;                          /*!< Supervision timeout for the LE Link. Range: 0x000A to 0x0C80.
-                                                     Mandatory Range: 0x000A to 0x0C80 Time = N * 10 msec */
-    }update_conn_params;                           /*!< Event parameter of ESP_GAP_BLE_UPDATE_CONN_PARAMS_EVT */
-    /**
-     * @brief ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT
-     */
-    struct ble_pkt_data_length_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the set pkt data length operation success status */
-        esp_ble_pkt_data_length_params_t params;    /*!<  pkt data length value */
-    } pkt_data_lenth_cmpl;                          /*!< Event parameter of ESP_GAP_BLE_SET_PKT_LENGTH_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_SET_LOCAL_PRIVACY_COMPLETE_EVT
-     */
-    struct ble_local_privacy_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the set local privacy operation success status */
-    } local_privacy_cmpl;                           /*!< Event parameter of ESP_GAP_BLE_SET_LOCAL_PRIVACY_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_REMOVE_BOND_DEV_COMPLETE_EVT
-     */
-    struct ble_remove_bond_dev_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the remove bond device operation success status */
-        esp_bd_addr_t bd_addr;                      /*!< The device address which has been remove from the bond list */
-    }remove_bond_dev_cmpl;                          /*!< Event parameter of ESP_GAP_BLE_REMOVE_BOND_DEV_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT
-     */
-    struct ble_clear_bond_dev_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the clear bond device operation success status */
-    }clear_bond_dev_cmpl;                           /*!< Event parameter of ESP_GAP_BLE_CLEAR_BOND_DEV_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_GET_BOND_DEV_COMPLETE_EVT
-     */
-    struct ble_get_bond_dev_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the get bond device operation success status */
-        uint8_t dev_num;                            /*!< Indicate the get number device in the bond list */
-        esp_ble_bond_dev_t *bond_dev;               /*!< the pointer to the bond device Structure */
-    }get_bond_dev_cmpl;                             /*!< Event parameter of ESP_GAP_BLE_GET_BOND_DEV_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT
-     */
-    struct ble_read_rssi_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the read adv tx power operation success status */
-        int8_t rssi;                                /*!< The ble remote device rssi value, the range is from -127 to 20, the unit is dbm,
-                                                         if the RSSI cannot be read, the RSSI metric shall be set to 127. */
-        esp_bd_addr_t remote_addr;                  /*!< The remote device address */
-    } read_rssi_cmpl;                               /*!< Event parameter of ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_UPDATE_WHITELIST_COMPLETE_EVT
-     */
-    struct ble_update_whitelist_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate the add or remove whitelist operation success status */
-        esp_ble_wl_opration_t wl_opration;          /*!< The value is ESP_BLE_WHITELIST_ADD if add address to whitelist operation success, ESP_BLE_WHITELIST_REMOVE if remove address from the whitelist operation success */
-    } update_whitelist_cmpl;                        /*!< Event parameter of ESP_GAP_BLE_UPDATE_WHITELIST_COMPLETE_EVT */
-    /**
-     * @brief ESP_GAP_BLE_UPDATE_DUPLICATE_EXCEPTIONAL_LIST_COMPLETE_EVT
-     */
-    struct ble_update_duplicate_exceptional_list_cmpl_evt_param {
-        esp_bt_status_t status;                     /*!< Indicate update duplicate scan exceptional list operation success status */
-        uint8_t         subcode;                    /*!< Define in esp_bt_duplicate_exceptional_subcode_type_t */
-        uint16_t         length;                     /*!< The length of device_info */
-        esp_duplicate_info_t device_info;           /*!< device information, when subcode is ESP_BLE_DUPLICATE_EXCEPTIONAL_LIST_CLEAN, the value is invalid */
-    } update_duplicate_exceptional_list_cmpl;       /*!< Event parameter of ESP_GAP_BLE_UPDATE_DUPLICATE_EXCEPTIONAL_LIST_COMPLETE_EVT */
-} esp_ble_gap_cb_param_t;
-
-/**
- * @brief GAP callback function type
- * @param event : Event type
- * @param param : Point to callback parameter, currently is union type
- */
-typedef void (* esp_gap_ble_cb_t)(esp_gap_ble_cb_event_t event, esp_ble_gap_cb_param_t *param);
-
-/**
- * @brief           This function is called to occur gap event, such as scan result
- *
- * @param[in]       callback: callback function
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_register_callback(esp_gap_ble_cb_t callback);
-
-
-/**
- * @brief           This function is called to override the BTA default ADV parameters.
- *
- * @param[in]       adv_data: Pointer to User defined ADV data structure. This
- *                  memory space can not be freed until callback of config_adv_data
- *                  is received.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_config_adv_data (esp_ble_adv_data_t *adv_data);
-
-
-
-/**
- * @brief           This function is called to set scan parameters
- *
- * @param[in]       scan_params: Pointer to User defined scan_params data structure. This
- *                  memory space can not be freed until callback of set_scan_params
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_set_scan_params(esp_ble_scan_params_t *scan_params);
-
-
-/**
- * @brief           This procedure keep the device scanning the peer device which advertising on the air
- *
- * @param[in]       duration: Keeping the scanning time, the unit is second.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_start_scanning(uint32_t duration);
-
-
-/**
- * @brief          This function call to stop the device scanning the peer device which advertising on the air
- * @return
- *                 - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_stop_scanning(void);
-
-/**
- * @brief           This function is called to start advertising.
- *
- * @param[in]       adv_params: pointer to User defined adv_params data structure.
-
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_start_advertising (esp_ble_adv_params_t *adv_params);
-
-
-
-/**
- * @brief           This function is called to stop advertising.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_stop_advertising(void);
-
-
-
-/**
- * @brief           Update connection parameters, can only be used when connection is up.
- *
- * @param[in]       params   -  connection update parameters
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_update_conn_params(esp_ble_conn_update_params_t *params);
-
-
-/**
- * @brief           This function is to set maximum LE data packet size
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_set_pkt_data_len(esp_bd_addr_t remote_device, uint16_t tx_data_length);
-
-/**
- * @brief           This function sets the random address for the application
- *
- * @param[in]       rand_addr: the random address which should be setting
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_set_rand_addr(esp_bd_addr_t rand_addr);
-
-/**
- * @brief           This function clears the random address for the application
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_clear_rand_addr(void);
-
-
-
-/**
- * @brief           Enable/disable privacy on the local device
- *
- * @param[in]       privacy_enable   - enable/disable privacy on remote device.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_config_local_privacy (bool privacy_enable);
-
-/**
- * @brief           set local gap appearance icon
- *
- *
- * @param[in]       icon   - External appearance value, these values are defined by the Bluetooth SIG, please refer to
- *                  https://www.bluetooth.com/specifications/gatt/viewer?attributeXmlFile=org.bluetooth.characteristic.gap.appearance.xml
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_config_local_icon (uint16_t icon);
-
-/**
-* @brief            Add or remove device from white list
-*
-* @param[in]        add_remove: the value is true if added the ble device to the white list, and false remove to the white list.
-* @param[in]        remote_bda: the remote device address add/remove from the white list.
-* @return
-*                     - ESP_OK : success
-*                     - other  : failed
-*
-*/
-esp_err_t esp_ble_gap_update_whitelist(bool add_remove, esp_bd_addr_t remote_bda);
-
-/**
-* @brief            Get the whitelist size in the controller
-*
-* @param[out]       length: the white list length.
-* @return
-*                     - ESP_OK : success
-*                     - other  : failed
-*
-*/
-esp_err_t esp_ble_gap_get_whitelist_size(uint16_t *length);
-
-/**
-* @brief            This function is called to set the preferred connection
-*                   parameters when default connection parameter is not desired before connecting.
-*                   This API can only be used in the master role.
-*
-* @param[in]        bd_addr: BD address of the peripheral
-* @param[in]        min_conn_int: minimum preferred connection interval
-* @param[in]        max_conn_int: maximum preferred connection interval
-* @param[in]        slave_latency: preferred slave latency
-* @param[in]        supervision_tout: preferred supervision timeout
-*
-* @return
-*                   - ESP_OK : success
-*                   - other  : failed
-*
-*/
-esp_err_t esp_ble_gap_set_prefer_conn_params(esp_bd_addr_t bd_addr,
-                                                                 uint16_t min_conn_int, uint16_t max_conn_int,
-                                                                 uint16_t slave_latency, uint16_t supervision_tout);
-
-/**
- * @brief           Set device name to the local device
- *
- * @param[in]       name   -  device name.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_set_device_name(const char *name);
-
-/**
- * @brief          This function is called to get local used address and adress type.
- *                 uint8_t *esp_bt_dev_get_address(void) get the public address
- *
- * @param[in]       local_used_addr - current local used ble address (six bytes)
- * @param[in]       addr_type   - ble address type
- *
- * @return          - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_get_local_used_addr(esp_bd_addr_t local_used_addr, uint8_t * addr_type);
-/**
- * @brief          This function is called to get ADV data for a specific type.
- *
- * @param[in]       adv_data - pointer of ADV data which to be resolved
- * @param[in]       type   - finding ADV data type
- * @param[out]      length - return the length of ADV data not including type
- *
- * @return          pointer of ADV data
- *
- */
-uint8_t *esp_ble_resolve_adv_data(uint8_t *adv_data, uint8_t type, uint8_t *length);
-
-/**
- * @brief           This function is called to set raw advertising data. User need to fill
- *                  ADV data by self.
- *
- * @param[in]       raw_data : raw advertising data
- * @param[in]       raw_data_len : raw advertising data length , less than 31 bytes
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gap_config_adv_data_raw(uint8_t *raw_data, uint32_t raw_data_len);
-
-/**
- * @brief           This function is called to set raw scan response data. User need to fill
- *                  scan response data by self.
- *
- * @param[in]       raw_data : raw scan response data
- * @param[in]       raw_data_len : raw scan response data length , less than 31 bytes
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- */
-esp_err_t esp_ble_gap_config_scan_rsp_data_raw(uint8_t *raw_data, uint32_t raw_data_len);
-
-/**
- * @brief           This function is called to read the RSSI of remote device.
- *                  The address of link policy results are returned in the gap callback function with
- *                  ESP_GAP_BLE_READ_RSSI_COMPLETE_EVT event.
- *
- * @param[in]       remote_addr : The remote connection device address.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- */
-esp_err_t esp_ble_gap_read_rssi(esp_bd_addr_t remote_addr);
-
-/**
- * @brief           This function is called to add a device info into the duplicate scan exceptional list.
- *
- *
- * @param[in]       type: device info type, it is defined in esp_ble_duplicate_exceptional_info_type_t
- *                  when type is MESH_BEACON_TYPE, MESH_PROV_SRV_ADV or MESH_PROXY_SRV_ADV , device_info is invalid.
- * @param[in]       device_info: the device information.
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- */
-esp_err_t esp_ble_gap_add_duplicate_scan_exceptional_device(esp_ble_duplicate_exceptional_info_type_t type, esp_duplicate_info_t device_info);
-
-/**
- * @brief           This function is called to remove a device info from the duplicate scan exceptional list.
- *
- *
- * @param[in]       type: device info type, it is defined in esp_ble_duplicate_exceptional_info_type_t
- *                  when type is MESH_BEACON_TYPE, MESH_PROV_SRV_ADV or MESH_PROXY_SRV_ADV , device_info is invalid.
- * @param[in]       device_info: the device information.
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- */
-esp_err_t esp_ble_gap_remove_duplicate_scan_exceptional_device(esp_ble_duplicate_exceptional_info_type_t type, esp_duplicate_info_t device_info);
-
-/**
- * @brief           This function is called to clean the duplicate scan exceptional list.
- *                  This API will delete all device information in the duplicate scan exceptional list.
- *
- *
- * @param[in]       list_type: duplicate scan exceptional list type, the value can be one or more of esp_duplicate_scan_exceptional_list_type_t.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- */
-esp_err_t esp_ble_gap_clean_duplicate_scan_exceptional_list(esp_duplicate_scan_exceptional_list_type_t list_type);
-
-#if (SMP_INCLUDED == TRUE)
-/**
-* @brief             Set a GAP security parameter value. Overrides the default value.
-*
-* @param[in]       param_type : the type of the param which to be set
-* @param[in]       value  : the param value
-* @param[in]       len : the length of the param value
-*
-* @return            - ESP_OK : success
-*                       - other  : failed
-*
-*/
-esp_err_t esp_ble_gap_set_security_param(esp_ble_sm_param_t param_type,
-                                         void *value, uint8_t len);
-
-/**
-* @brief             Grant security request access.
-*
-* @param[in]       bd_addr : BD address of the peer
-* @param[in]       accept  :  accept the security request or not
-*
-* @return            - ESP_OK : success
-*                    - other  : failed
-*
-*/
-esp_err_t esp_ble_gap_security_rsp(esp_bd_addr_t bd_addr,  bool accept);
-
-
-/**
-* @brief             Set a gap parameter value. Use this function to change
-*                    the default GAP parameter values.
-*
-* @param[in]       bd_addr : the address of the peer device need to encryption
-* @param[in]       sec_act  : This is the security action to indicate
-*                                   what kind of BLE security level is required for
-*                                   the BLE link if the BLE is supported
-*
-* @return            - ESP_OK : success
-*                       - other  : failed
-*
-*/
-esp_err_t esp_ble_set_encryption(esp_bd_addr_t bd_addr, esp_ble_sec_act_t sec_act);
-
-/**
-* @brief          Reply the key value to the peer device in the legacy connection stage.
-*
-* @param[in]      bd_addr : BD address of the peer
-* @param[in]      accept : passkey entry successful or declined.
-* @param[in]      passkey : passkey value, must be a 6 digit number,
-*                                     can be lead by 0.
-*
-* @return            - ESP_OK : success
-*                  - other  : failed
-*
-*/
-esp_err_t esp_ble_passkey_reply(esp_bd_addr_t bd_addr, bool accept, uint32_t passkey);
-
-
-/**
-* @brief           Reply the confirm value to the peer device in the secure connection stage.
-*
-* @param[in]       bd_addr : BD address of the peer device
-* @param[in]       accept : numbers to compare are the same or different.
-*
-* @return            - ESP_OK : success
-*                       - other  : failed
-*
-*/
-esp_err_t esp_ble_confirm_reply(esp_bd_addr_t bd_addr, bool accept);
-
-/**
-* @brief           Removes a device from the security database list of
-*                  peer device. It manages unpairing event while connected.
-*
-* @param[in]       bd_addr : BD address of the peer device
-*
-* @return            - ESP_OK : success
-*                       - other  : failed
-*
-*/
-esp_err_t esp_ble_remove_bond_device(esp_bd_addr_t bd_addr);
-
-/**
-* @brief           Get the device number from the security database list of peer device.
-*                  It will return the device bonded number immediately.
-*
-* @return          - >= 0 : bonded devices number.
-*                  - ESP_FAIL  : failed
-*
-*/
-int esp_ble_get_bond_device_num(void);
-
-
-/**
-* @brief           Get the device from the security database list of peer device.
-*                  It will return the device bonded information immediately.
-* @param[inout]    dev_num: Indicate the dev_list array(buffer) size as input.
-*                           If dev_num is large enough, it means the actual number as output.
-*                           Suggest that dev_num value equal to esp_ble_get_bond_device_num().
-*
-* @param[out]      dev_list: an array(buffer) of `esp_ble_bond_dev_t` type. Use for storing the bonded devices address.
-*                            The dev_list should be allocated by who call this API.
-* @return          - ESP_OK : success
-*                  - other  : failed
-*
-*/
-esp_err_t esp_ble_get_bond_device_list(int *dev_num, esp_ble_bond_dev_t *dev_list);
-
-/**
-* @brief           This function is called to provide the OOB data for
-*                  SMP in response to ESP_GAP_BLE_OOB_REQ_EVT
-*
-* @param[in]       bd_addr: BD address of the peer device.
-* @param[in]       TK: TK value, the TK value shall be a 128-bit random number
-* @param[in]       len: length of tk, should always be 128-bit
-*
-* @return          - ESP_OK : success
-*                  - other  : failed
-*
-*/
-esp_err_t esp_ble_oob_req_reply(esp_bd_addr_t bd_addr, uint8_t *TK, uint8_t len);
-
-#endif /* #if (SMP_INCLUDED == TRUE) */
-
-/**
-* @brief           This function is to disconnect the physical connection of the peer device
-*                  gattc may have multiple virtual GATT server connections when multiple app_id registered.
-*                  esp_ble_gattc_close (esp_gatt_if_t gattc_if, uint16_t conn_id) only close one virtual GATT server connection.
-*                  if there exist other virtual GATT server connections, it does not disconnect the physical connection.
-*                  esp_ble_gap_disconnect(esp_bd_addr_t remote_device) disconnect the physical connection directly.
-*
-*
-*
-* @param[in]       remote_device : BD address of the peer device
-*
-* @return            - ESP_OK : success
-*                    - other  : failed
-*
-*/
-esp_err_t esp_ble_gap_disconnect(esp_bd_addr_t remote_device);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_GAP_BLE_API_H__ */
diff --git a/tools/sdk/include/bt/esp_gap_bt_api.h b/tools/sdk/include/bt/esp_gap_bt_api.h
deleted file mode 100644
index 627cb041802..00000000000
--- a/tools/sdk/include/bt/esp_gap_bt_api.h
+++ /dev/null
@@ -1,600 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_GAP_BT_API_H__
-#define __ESP_GAP_BT_API_H__
-
-#include <stdint.h>
-#include "esp_err.h"
-#include "esp_bt_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/// RSSI threshold
-#define ESP_BT_GAP_RSSI_HIGH_THRLD  -20             /*!< High RSSI threshold */
-#define ESP_BT_GAP_RSSI_LOW_THRLD   -45             /*!< Low RSSI threshold */
-
-/// Class of device
-typedef struct {
-    uint32_t      reserved_2: 2;                    /*!< undefined */
-    uint32_t      minor: 6;                         /*!< minor class */
-    uint32_t      major: 5;                         /*!< major class */
-    uint32_t      service: 11;                      /*!< service class */
-    uint32_t      reserved_8: 8;                    /*!< undefined */
-} esp_bt_cod_t;
-
-/// class of device settings
-typedef enum {
-    ESP_BT_SET_COD_MAJOR_MINOR     = 0x01,          /*!< overwrite major, minor class */
-    ESP_BT_SET_COD_SERVICE_CLASS   = 0x02,          /*!< set the bits in the input, the current bit will remain */
-    ESP_BT_CLR_COD_SERVICE_CLASS   = 0x04,          /*!< clear the bits in the input, others will remain */
-    ESP_BT_SET_COD_ALL             = 0x08,          /*!< overwrite major, minor, set the bits in service class */
-    ESP_BT_INIT_COD                = 0x0a,          /*!< overwrite major, minor, and service class */
-} esp_bt_cod_mode_t;
-
-/// Discoverability and Connectability mode
-typedef enum {
-    ESP_BT_SCAN_MODE_NONE = 0,                      /*!< Neither discoverable nor connectable */
-    ESP_BT_SCAN_MODE_CONNECTABLE,                   /*!< Connectable but not discoverable */
-    ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE       /*!< both discoverable and connectable */
-} esp_bt_scan_mode_t;
-
-/// Bluetooth Device Property type
-typedef enum {
-    ESP_BT_GAP_DEV_PROP_BDNAME = 1,                 /*!< Bluetooth device name, value type is int8_t [] */
-    ESP_BT_GAP_DEV_PROP_COD,                        /*!< Class of Device, value type is uint32_t */
-    ESP_BT_GAP_DEV_PROP_RSSI,                       /*!< Received Signal strength Indication, value type is int8_t, ranging from -128 to 127 */
-    ESP_BT_GAP_DEV_PROP_EIR,                        /*!< Extended Inquiry Response, value type is uint8_t [] */
-} esp_bt_gap_dev_prop_type_t;
-
-/// Maximum bytes of Bluetooth device name
-#define ESP_BT_GAP_MAX_BDNAME_LEN             (248)
-
-/// Maximum size of EIR Significant part
-#define ESP_BT_GAP_EIR_DATA_LEN               (240)
-
-/// Bluetooth Device Property Descriptor
-typedef struct {
-    esp_bt_gap_dev_prop_type_t type;                /*!< device property type */
-    int len;                                        /*!< device property value length */
-    void *val;                                      /*!< device property value */
-} esp_bt_gap_dev_prop_t;
-
-/// Extended Inquiry Response data type
-typedef enum {
-    ESP_BT_EIR_TYPE_FLAGS                    = 0x01,     /*!< Flag with information such as BR/EDR and LE support */
-    ESP_BT_EIR_TYPE_INCMPL_16BITS_UUID       = 0x02,     /*!< Incomplete list of 16-bit service UUIDs */
-    ESP_BT_EIR_TYPE_CMPL_16BITS_UUID         = 0x03,     /*!< Complete list of 16-bit service UUIDs */
-    ESP_BT_EIR_TYPE_INCMPL_32BITS_UUID       = 0x04,     /*!< Incomplete list of 32-bit service UUIDs */
-    ESP_BT_EIR_TYPE_CMPL_32BITS_UUID         = 0x05,     /*!< Complete list of 32-bit service UUIDs */
-    ESP_BT_EIR_TYPE_INCMPL_128BITS_UUID      = 0x06,     /*!< Incomplete list of 128-bit service UUIDs */
-    ESP_BT_EIR_TYPE_CMPL_128BITS_UUID        = 0x07,     /*!< Complete list of 128-bit service UUIDs */
-    ESP_BT_EIR_TYPE_SHORT_LOCAL_NAME         = 0x08,     /*!< Shortened Local Name */
-    ESP_BT_EIR_TYPE_CMPL_LOCAL_NAME          = 0x09,     /*!< Complete Local Name */
-    ESP_BT_EIR_TYPE_TX_POWER_LEVEL           = 0x0a,     /*!< Tx power level, value is 1 octet ranging from  -127 to 127, unit is dBm*/
-    ESP_BT_EIR_TYPE_MANU_SPECIFIC            = 0xff,     /*!< Manufacturer specific data */
-} esp_bt_eir_type_t;
-
-/// Major service class field of Class of Device, mutiple bits can be set
-typedef enum {
-    ESP_BT_COD_SRVC_NONE                     =     0,    /*!< None indicates an invalid value */
-    ESP_BT_COD_SRVC_LMTD_DISCOVER            =   0x1,    /*!< Limited Discoverable Mode */
-    ESP_BT_COD_SRVC_POSITIONING              =   0x8,    /*!< Positioning (Location identification) */
-    ESP_BT_COD_SRVC_NETWORKING               =  0x10,    /*!< Networking, e.g. LAN, Ad hoc */
-    ESP_BT_COD_SRVC_RENDERING                =  0x20,    /*!< Rendering, e.g. Printing, Speakers */
-    ESP_BT_COD_SRVC_CAPTURING                =  0x40,    /*!< Capturing, e.g. Scanner, Microphone */
-    ESP_BT_COD_SRVC_OBJ_TRANSFER             =  0x80,    /*!< Object Transfer, e.g. v-Inbox, v-Folder */
-    ESP_BT_COD_SRVC_AUDIO                    = 0x100,    /*!< Audio, e.g. Speaker, Microphone, Headset service */
-    ESP_BT_COD_SRVC_TELEPHONY                = 0x200,    /*!< Telephony, e.g. Cordless telephony, Modem, Headset service */
-    ESP_BT_COD_SRVC_INFORMATION              = 0x400,    /*!< Information, e.g., WEB-server, WAP-server */
-} esp_bt_cod_srvc_t;
-
-typedef enum{
-    ESP_BT_PIN_TYPE_VARIABLE = 0,                       /*!< Refer to BTM_PIN_TYPE_VARIABLE */
-    ESP_BT_PIN_TYPE_FIXED    = 1,                       /*!< Refer to BTM_PIN_TYPE_FIXED */
-} esp_bt_pin_type_t;
-
-#define ESP_BT_PIN_CODE_LEN        16                   /*!< Max pin code length */
-typedef uint8_t esp_bt_pin_code_t[ESP_BT_PIN_CODE_LEN]; /*!< Pin Code (upto 128 bits) MSB is 0 */
-
-typedef enum {
-    ESP_BT_SP_IOCAP_MODE = 0,                            /*!< Set IO mode */
-    //ESP_BT_SP_OOB_DATA, //TODO                         /*!< Set OOB data */
-} esp_bt_sp_param_t;
-
-/* relate to BTM_IO_CAP_xxx in stack/btm_api.h */
-#define ESP_BT_IO_CAP_OUT                      0        /*!< DisplayOnly */         /* relate to BTM_IO_CAP_OUT in stack/btm_api.h */
-#define ESP_BT_IO_CAP_IO                       1        /*!< DisplayYesNo */        /* relate to BTM_IO_CAP_IO in stack/btm_api.h */
-#define ESP_BT_IO_CAP_IN                       2        /*!< KeyboardOnly */        /* relate to BTM_IO_CAP_IN in stack/btm_api.h */
-#define ESP_BT_IO_CAP_NONE                     3        /*!< NoInputNoOutput */     /* relate to BTM_IO_CAP_NONE in stack/btm_api.h */
-typedef uint8_t esp_bt_io_cap_t;                        /*!< combination of the io capability */
-
-/// Bits of major service class field
-#define ESP_BT_COD_SRVC_BIT_MASK              (0xffe000) /*!< Major service bit mask */
-#define ESP_BT_COD_SRVC_BIT_OFFSET            (13)       /*!< Major service bit offset */
-
-/// Major device class field of Class of Device
-typedef enum {
-    ESP_BT_COD_MAJOR_DEV_MISC                = 0,    /*!< Miscellaneous */
-    ESP_BT_COD_MAJOR_DEV_COMPUTER            = 1,    /*!< Computer */
-    ESP_BT_COD_MAJOR_DEV_PHONE               = 2,    /*!< Phone(cellular, cordless, pay phone, modem */
-    ESP_BT_COD_MAJOR_DEV_LAN_NAP             = 3,    /*!< LAN, Network Access Point */
-    ESP_BT_COD_MAJOR_DEV_AV                  = 4,    /*!< Audio/Video(headset, speaker, stereo, video display, VCR */
-    ESP_BT_COD_MAJOR_DEV_PERIPHERAL          = 5,    /*!< Peripheral(mouse, joystick, keyboard) */
-    ESP_BT_COD_MAJOR_DEV_IMAGING             = 6,    /*!< Imaging(printer, scanner, camera, display */
-    ESP_BT_COD_MAJOR_DEV_WEARABLE            = 7,    /*!< Wearable */
-    ESP_BT_COD_MAJOR_DEV_TOY                 = 8,    /*!< Toy */
-    ESP_BT_COD_MAJOR_DEV_HEALTH              = 9,    /*!< Health */
-    ESP_BT_COD_MAJOR_DEV_UNCATEGORIZED       = 31,   /*!< Uncategorized: device not specified */
-} esp_bt_cod_major_dev_t;
-
-/// Bits of major device class field
-#define ESP_BT_COD_MAJOR_DEV_BIT_MASK         (0x1f00) /*!< Major device bit mask */
-#define ESP_BT_COD_MAJOR_DEV_BIT_OFFSET       (8)      /*!< Major device bit offset */
-
-/// Bits of minor device class field
-#define ESP_BT_COD_MINOR_DEV_BIT_MASK         (0xfc)   /*!< Minor device bit mask */
-#define ESP_BT_COD_MINOR_DEV_BIT_OFFSET       (2)      /*!< Minor device bit offset */
-
-/// Bits of format type
-#define ESP_BT_COD_FORMAT_TYPE_BIT_MASK       (0x03)   /*!< Format type bit mask */
-#define ESP_BT_COD_FORMAT_TYPE_BIT_OFFSET     (0)      /*!< Format type bit offset */
-
-/// Class of device format type 1
-#define ESP_BT_COD_FORMAT_TYPE_1              (0x00)
-
-/** Bluetooth Device Discovery state */
-typedef enum {
-    ESP_BT_GAP_DISCOVERY_STOPPED,                   /*!< device discovery stopped */
-    ESP_BT_GAP_DISCOVERY_STARTED,                   /*!< device discovery started */
-} esp_bt_gap_discovery_state_t;
-
-/// BT GAP callback events
-typedef enum {
-    ESP_BT_GAP_DISC_RES_EVT = 0,                    /*!< device discovery result event */
-    ESP_BT_GAP_DISC_STATE_CHANGED_EVT,              /*!< discovery state changed event */
-    ESP_BT_GAP_RMT_SRVCS_EVT,                       /*!< get remote services event */
-    ESP_BT_GAP_RMT_SRVC_REC_EVT,                    /*!< get remote service record event */
-    ESP_BT_GAP_AUTH_CMPL_EVT,                       /*!< AUTH complete event */
-    ESP_BT_GAP_PIN_REQ_EVT,                         /*!< Legacy Pairing Pin code request */
-    ESP_BT_GAP_CFM_REQ_EVT,                         /*!< Simple Pairing User Confirmation request. */
-    ESP_BT_GAP_KEY_NOTIF_EVT,                       /*!< Simple Pairing Passkey Notification */
-    ESP_BT_GAP_KEY_REQ_EVT,                         /*!< Simple Pairing Passkey request */
-    ESP_BT_GAP_READ_RSSI_DELTA_EVT,                 /*!< read rssi event */
-    ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT,        /*!< remove bond device complete event */
-    ESP_BT_GAP_EVT_MAX,
-} esp_bt_gap_cb_event_t;
-
-/** Inquiry Mode */
-typedef enum {
-    ESP_BT_INQ_MODE_GENERAL_INQUIRY,                /*!< General inquiry mode */
-    ESP_BT_INQ_MODE_LIMITED_INQUIRY,                /*!< Limited inquiry mode */
-} esp_bt_inq_mode_t;
-
-/** Minimum and Maximum inquiry length*/
-#define ESP_BT_GAP_MIN_INQ_LEN                (0x01)  /*!< Minimum inquiry duration, unit is 1.28s */
-#define ESP_BT_GAP_MAX_INQ_LEN                (0x30)  /*!< Maximum inquiry duration, unit is 1.28s */
-
-/// A2DP state callback parameters
-typedef union {
-    /**
-     * @brief ESP_BT_GAP_DISC_RES_EVT
-     */
-    struct disc_res_param {
-        esp_bd_addr_t bda;                     /*!< remote bluetooth device address*/
-        int num_prop;                          /*!< number of properties got */
-        esp_bt_gap_dev_prop_t *prop;           /*!< properties discovered from the new device */
-    } disc_res;                                /*!< discovery result parameter struct */
-
-    /**
-     * @brief  ESP_BT_GAP_DISC_STATE_CHANGED_EVT
-     */
-    struct disc_state_changed_param {
-        esp_bt_gap_discovery_state_t state;    /*!< discovery state */
-    } disc_st_chg;                             /*!< discovery state changed parameter struct */
-
-    /**
-     * @brief ESP_BT_GAP_RMT_SRVCS_EVT
-     */
-    struct rmt_srvcs_param {
-        esp_bd_addr_t bda;                     /*!< remote bluetooth device address*/
-        esp_bt_status_t stat;                  /*!< service search status */
-        int num_uuids;                         /*!< number of UUID in uuid_list */
-        esp_bt_uuid_t *uuid_list;              /*!< list of service UUIDs of remote device */
-    } rmt_srvcs;                               /*!< services of remote device parameter struct */
-
-    /**
-     * @brief ESP_BT_GAP_RMT_SRVC_REC_EVT
-     */
-    struct rmt_srvc_rec_param {
-        esp_bd_addr_t bda;                     /*!< remote bluetooth device address*/
-        esp_bt_status_t stat;                  /*!< service search status */
-    } rmt_srvc_rec;                            /*!< specific service record from remote device parameter struct */
-
-    /**
-     * @brief ESP_BT_GAP_READ_RSSI_DELTA_EVT *
-     */
-    struct read_rssi_delta_param {
-        esp_bd_addr_t bda;                     /*!< remote bluetooth device address*/
-        esp_bt_status_t stat;                  /*!< read rssi status */
-        int8_t rssi_delta;                     /*!< rssi delta value range -128 ~127, The value zero indicates that the RSSI is inside the Golden Receive Power Range, the Golden Receive Power Range is from ESP_BT_GAP_RSSI_LOW_THRLD to ESP_BT_GAP_RSSI_HIGH_THRLD */
-    } read_rssi_delta;                         /*!< read rssi parameter struct */
-
-    /**
-     * @brief ESP_BT_GAP_AUTH_CMPL_EVT
-     */
-    struct auth_cmpl_param {
-        esp_bd_addr_t bda;                     /*!< remote bluetooth device address*/
-        esp_bt_status_t stat;                  /*!< authentication complete status */
-        uint8_t device_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1]; /*!< device name */
-    } auth_cmpl;                               /*!< authentication complete parameter struct */
-
-    /**
-     * @brief ESP_BT_GAP_PIN_REQ_EVT
-     */
-    struct pin_req_param {
-        esp_bd_addr_t bda;                     /*!< remote bluetooth device address*/
-        bool min_16_digit;                     /*!< TRUE if the pin returned must be at least 16 digits */
-    } pin_req;                                 /*!< pin request parameter struct */
-
-    /**
-     * @brief ESP_BT_GAP_CFM_REQ_EVT
-     */
-    struct cfm_req_param {
-        esp_bd_addr_t bda;                     /*!< remote bluetooth device address*/
-        uint32_t num_val;                      /*!< the numeric value for comparison. */
-    } cfm_req;                                 /*!< confirm request parameter struct */
-
-    /**
-     * @brief ESP_BT_GAP_KEY_NOTIF_EVT
-     */
-    struct key_notif_param {
-        esp_bd_addr_t bda;                     /*!< remote bluetooth device address*/
-        uint32_t passkey;                      /*!< the numeric value for passkey entry. */
-    } key_notif;                               /*!< passkey notif parameter struct */
-
-    /**
-     * @brief ESP_BT_GAP_KEY_REQ_EVT
-     */
-    struct key_req_param {
-        esp_bd_addr_t bda;                     /*!< remote bluetooth device address*/
-    } key_req;                                 /*!< passkey request parameter struct */
-
-    /**
-     * @brief ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT
-     */
-    struct bt_remove_bond_dev_cmpl_evt_param {
-        esp_bd_addr_t bda;                          /*!< remote bluetooth device address*/
-        esp_bt_status_t status;                     /*!< Indicate the remove bond device operation success status */
-    }remove_bond_dev_cmpl;                           /*!< Event parameter of ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT */
-} esp_bt_gap_cb_param_t;
-
-/**
- * @brief           bluetooth GAP callback function type
- * @param           event : Event type
- * @param           param : Pointer to callback parameter
- */
-typedef void (* esp_bt_gap_cb_t)(esp_bt_gap_cb_event_t event, esp_bt_gap_cb_param_t *param);
-
-/**
- * @brief           get major service field of COD
- * @param[in]       cod: Class of Device
- * @return          major service bits
- */
-inline uint32_t esp_bt_gap_get_cod_srvc(uint32_t cod)
-{
-    return (cod & ESP_BT_COD_SRVC_BIT_MASK) >> ESP_BT_COD_SRVC_BIT_OFFSET;
-}
-
-/**
- * @brief           get major device field of COD
- * @param[in]       cod: Class of Device
- * @return          major device bits
- */
-inline uint32_t esp_bt_gap_get_cod_major_dev(uint32_t cod)
-{
-    return (cod & ESP_BT_COD_MAJOR_DEV_BIT_MASK) >> ESP_BT_COD_MAJOR_DEV_BIT_OFFSET;
-}
-
-/**
- * @brief           get minor service field of COD
- * @param[in]       cod: Class of Device
- * @return          minor service bits
- */
-inline uint32_t esp_bt_gap_get_cod_minor_dev(uint32_t cod)
-{
-    return (cod & ESP_BT_COD_MINOR_DEV_BIT_MASK) >> ESP_BT_COD_MINOR_DEV_BIT_OFFSET;
-}
-
-/**
- * @brief           get format type of COD
- * @param[in]       cod: Class of Device
- * @return          format type
- */
-inline uint32_t esp_bt_gap_get_cod_format_type(uint32_t cod)
-{
-    return (cod & ESP_BT_COD_FORMAT_TYPE_BIT_MASK);
-}
-
-/**
- * @brief           decide the integrity of COD
- * @param[in]       cod: Class of Device
- * @return
- *                  - true if cod is valid
- *                  - false otherise
- */
-inline bool esp_bt_gap_is_valid_cod(uint32_t cod)
-{
-    if (esp_bt_gap_get_cod_format_type(cod) == ESP_BT_COD_FORMAT_TYPE_1 &&
-            esp_bt_gap_get_cod_srvc(cod) != ESP_BT_COD_SRVC_NONE) {
-        return true;
-    }
-
-    return false;
-}
-
-/**
- * @brief           register callback function. This function should be called after esp_bluedroid_enable() completes successfully
- *
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_bt_gap_register_callback(esp_bt_gap_cb_t callback);
-
-/**
- * @brief           Set discoverability and connectability mode for legacy bluetooth. This function should
- *                  be called after esp_bluedroid_enable() completes successfully
- *
- * @param[in]       mode : one of the enums of bt_scan_mode_t
- *
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_ERR_INVALID_ARG: if argument invalid
- *                  - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_bt_gap_set_scan_mode(esp_bt_scan_mode_t mode);
-
-/**
- * @brief           This function starts Inquiry and Name Discovery. It should be called after esp_bluedroid_enable() completes successfully.
- *                  When Inquiry is halted and cached results do not contain device name, then Name Discovery will connect to the peer target to get the device name.
- *                  esp_bt_gap_cb_t will be called with ESP_BT_GAP_DISC_STATE_CHANGED_EVT when Inquriry is started or Name Discovery is completed.
- *                  esp_bt_gap_cb_t will be called with ESP_BT_GAP_DISC_RES_EVT each time the two types of discovery results are got.
- *
- * @param[in]       mode - Inquiry mode
- * @param[in]       inq_len - Inquiry duration in 1.28 sec units, ranging from 0x01 to 0x30. This parameter only specifies the total duration of the Inquiry process,
- *                          - when this time expires, Inquiry will be halted.
- * @param[in]       num_rsps - Number of responses that can be received before the Inquiry is halted, value 0 indicates an unlimited number of responses.
- *
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_ERR_INVALID_ARG: if invalid parameters are provided
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_bt_gap_start_discovery(esp_bt_inq_mode_t mode, uint8_t inq_len, uint8_t num_rsps);
-
-/**
- * @brief           Cancel Inquiry and Name Discovery. This function should be called after esp_bluedroid_enable() completes successfully.
- *                  esp_bt_gap_cb_t will be called with ESP_BT_GAP_DISC_STATE_CHANGED_EVT if Inquiry or Name Discovery is cancelled by
- *                  calling this function.
- *
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_bt_gap_cancel_discovery(void);
-
-/**
- * @brief           Start SDP to get remote services. This function should be called after esp_bluedroid_enable() completes successfully.
- *                  esp_bt_gap_cb_t will is called with ESP_BT_GAP_RMT_SRVCS_EVT after service discovery ends
- *
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_bt_gap_get_remote_services(esp_bd_addr_t remote_bda);
-
-/**
- * @brief           Start SDP to look up the service matching uuid on the remote device. This function should be called after
- *                  esp_bluedroid_enable() completes successfully
- *
- *                  esp_bt_gap_cb_t will is called with ESP_BT_GAP_RMT_SRVC_REC_EVT after service discovery ends
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_bt_gap_get_remote_service_record(esp_bd_addr_t remote_bda, esp_bt_uuid_t *uuid);
-
-/**
- * @brief           This function is called to get EIR data for a specific type.
- *
- * @param[in]       eir - pointer of raw eir data to be resolved
- * @param[in]       type   - specific EIR data type
- * @param[out]      length - return the length of EIR data excluding fields of length and data type
- *
- * @return          pointer of starting position of eir data excluding eir data type, NULL if not found
- *
- */
-uint8_t *esp_bt_gap_resolve_eir_data(uint8_t *eir, esp_bt_eir_type_t type, uint8_t *length);
-
-/**
- * @brief           This function is called to set class of device.
- *                  esp_bt_gap_cb_t will is called with ESP_BT_GAP_SET_COD_EVT after set COD ends
- *                  Some profile have special restrictions on class of device,
- *                  changes may cause these profile do not work
- *
- * @param[in]       cod - class of device
- * @param[in]       mode   - setting mode
- *
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_ERR_INVALID_ARG: if param is invalid
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_bt_gap_set_cod(esp_bt_cod_t cod, esp_bt_cod_mode_t mode);
-
-/**
- * @brief           This function is called to get class of device.
- *
- * @param[out]      cod - class of device
- *
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_FAIL: others
- */
-esp_err_t esp_bt_gap_get_cod(esp_bt_cod_t *cod);
-
-/**
- * @brief           This function is called to read RSSI delta by address after connected. The RSSI value returned by ESP_BT_GAP_READ_RSSI_DELTA_EVT.
- *
- *
- * @param[in]       remote_addr - remote device address, corresponding to a certain connection handle.
- * @return
- *                  - ESP_OK : Succeed
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_bt_gap_read_rssi_delta(esp_bd_addr_t remote_addr);
-
-/**
-* @brief           Removes a device from the security database list of
-*                  peer device.
-*
-* @param[in]       bd_addr : BD address of the peer device
-*
-* @return          - ESP_OK : success
-*                  - ESP_FAIL  : failed
-*
-*/
-esp_err_t esp_bt_gap_remove_bond_device(esp_bd_addr_t bd_addr);
-
-/**
-* @brief           Get the device number from the security database list of peer device.
-*                  It will return the device bonded number immediately.
-*
-* @return          - >= 0 : bonded devices number.
-*                  - ESP_FAIL  : failed
-*
-*/
-int esp_bt_gap_get_bond_device_num(void);
-
-/**
-* @brief           Get the device from the security database list of peer device.
-*                  It will return the device bonded information immediately.
-* @param[inout]    dev_num: Indicate the dev_list array(buffer) size as input.
-*                           If dev_num is large enough, it means the actual number as output.
-*                           Suggest that dev_num value equal to esp_ble_get_bond_device_num().
-*
-* @param[out]      dev_list: an array(buffer) of `esp_bd_addr_t` type. Use for storing the bonded devices address.
-*                            The dev_list should be allocated by who call this API.
-*
-* @return
-*                  - ESP_OK : Succeed
-*                  - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
-*                  - ESP_FAIL: others
-*/
-esp_err_t esp_bt_gap_get_bond_device_list(int *dev_num, esp_bd_addr_t *dev_list);
-
-/**
-* @brief            Set pin type and default pin code for legacy pairing.
-*
-* @param[in]        pin_type:       Use variable or fixed pin.
-*                                   If pin_type is ESP_BT_PIN_TYPE_VARIABLE, pin_code and pin_code_len
-*                                   will be ignored, and ESP_BT_GAP_PIN_REQ_EVT will come when control
-*                                   requests for pin code.
-*                                   Else, will use fixed pin code and not callback to users.
-* @param[in]        pin_code_len:   Length of pin_code
-* @param[in]        pin_code:       Pin_code
-*
-* @return           - ESP_OK : success
-*                   - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
-*                   - other  : failed
-*/
-esp_err_t esp_bt_gap_set_pin(esp_bt_pin_type_t pin_type, uint8_t pin_code_len, esp_bt_pin_code_t pin_code);
-
-/**
-* @brief            Reply the pin_code to the peer device for legacy pairing
-*                   when ESP_BT_GAP_PIN_REQ_EVT is coming.
-*
-* @param[in]        bd_addr:        BD address of the peer
-* @param[in]        accept:         Pin_code reply successful or declined.
-* @param[in]        pin_code_len:   Length of pin_code
-* @param[in]        pin_code:       Pin_code
-*
-* @return           - ESP_OK : success
-*                   - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
-*                   - other  : failed
-*/
-esp_err_t esp_bt_gap_pin_reply(esp_bd_addr_t bd_addr, bool accept, uint8_t pin_code_len, esp_bt_pin_code_t pin_code);
-
-#if (BT_SSP_INCLUDED == TRUE)
-/**
-* @brief            Set a GAP security parameter value. Overrides the default value.
-*
-* @param[in]        param_type : the type of the param which is to be set
-* @param[in]        value  : the param value
-* @param[in]        len : the length of the param value
-*
-* @return           - ESP_OK : success
-*                   - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
-*                   - other  : failed
-*
-*/
-esp_err_t esp_bt_gap_set_security_param(esp_bt_sp_param_t param_type,
-                                        void *value, uint8_t len);
-
-/**
-* @brief            Reply the key value to the peer device in the legacy connection stage.
-*
-* @param[in]        bd_addr : BD address of the peer
-* @param[in]        accept : passkey entry successful or declined.
-* @param[in]        passkey : passkey value, must be a 6 digit number,
-*                                     can be lead by 0.
-*
-* @return           - ESP_OK : success
-*                   - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
-*                   - other  : failed
-*
-*/
-esp_err_t esp_bt_gap_ssp_passkey_reply(esp_bd_addr_t bd_addr, bool accept, uint32_t passkey);
-
-
-/**
-* @brief            Reply the confirm value to the peer device in the legacy connection stage.
-*
-* @param[in]        bd_addr : BD address of the peer device
-* @param[in]        accept : numbers to compare are the same or different.
-*
-* @return           - ESP_OK : success
-*                   - ESP_ERR_INVALID_STATE: if bluetooth stack is not yet enabled
-*                   - other  : failed
-*
-*/
-esp_err_t esp_bt_gap_ssp_confirm_reply(esp_bd_addr_t bd_addr, bool accept);
-
-#endif /*(BT_SSP_INCLUDED == TRUE)*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_GAP_BT_API_H__ */
diff --git a/tools/sdk/include/bt/esp_gatt_common_api.h b/tools/sdk/include/bt/esp_gatt_common_api.h
deleted file mode 100644
index 447a26bd957..00000000000
--- a/tools/sdk/include/bt/esp_gatt_common_api.h
+++ /dev/null
@@ -1,56 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_GATT_COMMON_API_H__
-#define __ESP_GATT_COMMON_API_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "esp_err.h"
-#include "esp_bt_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Maximum Transmission Unit used in GATT
-#define ESP_GATT_DEF_BLE_MTU_SIZE   23   /* relate to GATT_DEF_BLE_MTU_SIZE in stack/gatt_api.h */
-
-// Maximum Transmission Unit allowed in GATT
-#define ESP_GATT_MAX_MTU_SIZE       517  /* relate to GATT_MAX_MTU_SIZE in stack/gatt_api.h */
-
-/**
- * @brief           This function is called to set local MTU,
- *                  the function is called before BLE connection.
- *
- * @param[in]       mtu: the size of MTU.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-extern esp_err_t esp_ble_gatt_set_local_mtu (uint16_t mtu);
-
-#if (BLE_INCLUDED == TRUE)
-extern uint16_t esp_ble_get_sendable_packets_num (void);
-extern uint16_t esp_ble_get_cur_sendable_packets_num (uint16_t connid);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_GATT_COMMON_API_H__ */
diff --git a/tools/sdk/include/bt/esp_gatt_defs.h b/tools/sdk/include/bt/esp_gatt_defs.h
deleted file mode 100644
index 615ea418bb3..00000000000
--- a/tools/sdk/include/bt/esp_gatt_defs.h
+++ /dev/null
@@ -1,474 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_GATT_DEFS_H__
-#define __ESP_GATT_DEFS_H__
-
-#include "esp_bt_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/// GATT INVALID UUID
-#define ESP_GATT_ILLEGAL_UUID               0
-/// GATT INVALID HANDLE
-#define ESP_GATT_ILLEGAL_HANDLE             0
-/// GATT attribute max handle
-#define ESP_GATT_ATTR_HANDLE_MAX            100
-#define ESP_GATT_MAX_READ_MULTI_HANDLES     10           /* Max attributes to read in one request */
-
-
-/**@{
- * All "ESP_GATT_UUID_xxx" is attribute types
- */
-#define ESP_GATT_UUID_IMMEDIATE_ALERT_SVC           0x1802          /*  Immediate alert Service*/
-#define ESP_GATT_UUID_LINK_LOSS_SVC                 0x1803          /*  Link Loss Service*/
-#define ESP_GATT_UUID_TX_POWER_SVC                  0x1804          /*  TX Power Service*/
-#define ESP_GATT_UUID_CURRENT_TIME_SVC              0x1805          /*  Current Time Service Service*/
-#define ESP_GATT_UUID_REF_TIME_UPDATE_SVC           0x1806          /*  Reference Time Update Service*/
-#define ESP_GATT_UUID_NEXT_DST_CHANGE_SVC           0x1807          /*  Next DST Change Service*/
-#define ESP_GATT_UUID_GLUCOSE_SVC                   0x1808          /*  Glucose Service*/
-#define ESP_GATT_UUID_HEALTH_THERMOM_SVC            0x1809          /*  Health Thermometer Service*/
-#define ESP_GATT_UUID_DEVICE_INFO_SVC               0x180A          /*  Device Information Service*/
-#define ESP_GATT_UUID_HEART_RATE_SVC                0x180D          /*  Heart Rate Service*/
-#define ESP_GATT_UUID_PHONE_ALERT_STATUS_SVC        0x180E          /* Phone Alert Status Service*/
-#define ESP_GATT_UUID_BATTERY_SERVICE_SVC           0x180F          /* Battery Service*/
-#define ESP_GATT_UUID_BLOOD_PRESSURE_SVC            0x1810          /* Blood Pressure Service*/
-#define ESP_GATT_UUID_ALERT_NTF_SVC                 0x1811          /* Alert Notification Service*/
-#define ESP_GATT_UUID_HID_SVC                       0x1812          /* HID Service*/
-#define ESP_GATT_UUID_SCAN_PARAMETERS_SVC           0x1813          /* Scan Parameters Service*/
-#define ESP_GATT_UUID_RUNNING_SPEED_CADENCE_SVC     0x1814          /* Running Speed and Cadence Service*/
-#define ESP_GATT_UUID_CYCLING_SPEED_CADENCE_SVC     0x1816          /* Cycling Speed and Cadence Service*/
-#define ESP_GATT_UUID_CYCLING_POWER_SVC             0x1818          /* Cycling Power Service*/
-#define ESP_GATT_UUID_LOCATION_AND_NAVIGATION_SVC   0x1819          /* Location and Navigation Service*/
-#define ESP_GATT_UUID_USER_DATA_SVC                 0x181C          /* User Data Service*/
-#define ESP_GATT_UUID_WEIGHT_SCALE_SVC              0x181D          /* Weight Scale Service*/
-
-#define ESP_GATT_UUID_PRI_SERVICE                   0x2800
-#define ESP_GATT_UUID_SEC_SERVICE                   0x2801
-#define ESP_GATT_UUID_INCLUDE_SERVICE               0x2802
-#define ESP_GATT_UUID_CHAR_DECLARE                  0x2803          /*  Characteristic Declaration*/
-
-#define ESP_GATT_UUID_CHAR_EXT_PROP                 0x2900          /*  Characteristic Extended Properties */
-#define ESP_GATT_UUID_CHAR_DESCRIPTION              0x2901          /*  Characteristic User Description*/
-#define ESP_GATT_UUID_CHAR_CLIENT_CONFIG            0x2902          /*  Client Characteristic Configuration */
-#define ESP_GATT_UUID_CHAR_SRVR_CONFIG              0x2903          /*  Server Characteristic Configuration */
-#define ESP_GATT_UUID_CHAR_PRESENT_FORMAT           0x2904          /*  Characteristic Presentation Format*/
-#define ESP_GATT_UUID_CHAR_AGG_FORMAT               0x2905          /*  Characteristic Aggregate Format*/
-#define ESP_GATT_UUID_CHAR_VALID_RANGE              0x2906          /*  Characteristic Valid Range */
-#define ESP_GATT_UUID_EXT_RPT_REF_DESCR             0x2907          /*  External Report Reference */
-#define ESP_GATT_UUID_RPT_REF_DESCR                 0x2908          /*  Report Reference */
-#define ESP_GATT_UUID_NUM_DIGITALS_DESCR            0x2909          /*  Number of Digitals */
-#define ESP_GATT_UUID_VALUE_TRIGGER_DESCR           0x290A          /*  Value Trigger Setting */
-#define ESP_GATT_UUID_ENV_SENSING_CONFIG_DESCR      0x290B          /*  Environmental Sensing Configuration */
-#define ESP_GATT_UUID_ENV_SENSING_MEASUREMENT_DESCR 0x290C          /*  Environmental Sensing Measurement */
-#define ESP_GATT_UUID_ENV_SENSING_TRIGGER_DESCR     0x290D          /*  Environmental Sensing Trigger Setting */
-#define ESP_GATT_UUID_TIME_TRIGGER_DESCR            0x290E          /*  Time Trigger Setting */
-
-/* GAP Profile Attributes */
-#define ESP_GATT_UUID_GAP_DEVICE_NAME               0x2A00
-#define ESP_GATT_UUID_GAP_ICON                      0x2A01
-#define ESP_GATT_UUID_GAP_PREF_CONN_PARAM           0x2A04
-#define ESP_GATT_UUID_GAP_CENTRAL_ADDR_RESOL        0x2AA6
-
-/* Attribute Profile Attribute UUID */
-#define ESP_GATT_UUID_GATT_SRV_CHGD                 0x2A05
-
-/* Link ESP_Loss Service */
-#define ESP_GATT_UUID_ALERT_LEVEL                   0x2A06          /* Alert Level */
-#define ESP_GATT_UUID_TX_POWER_LEVEL                0x2A07          /* TX power level */
-
-/* Current Time Service */
-#define ESP_GATT_UUID_CURRENT_TIME                  0x2A2B          /* Current Time */
-#define ESP_GATT_UUID_LOCAL_TIME_INFO               0x2A0F          /* Local time info */
-#define ESP_GATT_UUID_REF_TIME_INFO                 0x2A14          /* reference time information */
-
-/* Network availability Profile */
-#define ESP_GATT_UUID_NW_STATUS                     0x2A18          /* network availability status */
-#define ESP_GATT_UUID_NW_TRIGGER                    0x2A1A          /* Network availability trigger */
-
-/* Phone alert */
-#define ESP_GATT_UUID_ALERT_STATUS                  0x2A3F          /* alert status */
-#define ESP_GATT_UUID_RINGER_CP                     0x2A40          /* ringer control point */
-#define ESP_GATT_UUID_RINGER_SETTING                0x2A41          /* ringer setting */
-
-/* Glucose Service */
-#define ESP_GATT_UUID_GM_MEASUREMENT                0x2A18
-#define ESP_GATT_UUID_GM_CONTEXT                    0x2A34
-#define ESP_GATT_UUID_GM_CONTROL_POINT              0x2A52
-#define ESP_GATT_UUID_GM_FEATURE                    0x2A51
-
-/* device information characteristic */
-#define ESP_GATT_UUID_SYSTEM_ID                     0x2A23
-#define ESP_GATT_UUID_MODEL_NUMBER_STR              0x2A24
-#define ESP_GATT_UUID_SERIAL_NUMBER_STR             0x2A25
-#define ESP_GATT_UUID_FW_VERSION_STR                0x2A26
-#define ESP_GATT_UUID_HW_VERSION_STR                0x2A27
-#define ESP_GATT_UUID_SW_VERSION_STR                0x2A28
-#define ESP_GATT_UUID_MANU_NAME                     0x2A29
-#define ESP_GATT_UUID_IEEE_DATA                     0x2A2A
-#define ESP_GATT_UUID_PNP_ID                        0x2A50
-
-/* HID characteristics */
-#define ESP_GATT_UUID_HID_INFORMATION               0x2A4A
-#define ESP_GATT_UUID_HID_REPORT_MAP                0x2A4B
-#define ESP_GATT_UUID_HID_CONTROL_POINT             0x2A4C
-#define ESP_GATT_UUID_HID_REPORT                    0x2A4D
-#define ESP_GATT_UUID_HID_PROTO_MODE                0x2A4E
-#define ESP_GATT_UUID_HID_BT_KB_INPUT               0x2A22
-#define ESP_GATT_UUID_HID_BT_KB_OUTPUT              0x2A32
-#define ESP_GATT_UUID_HID_BT_MOUSE_INPUT            0x2A33
-
- /// Heart Rate Measurement
-#define    ESP_GATT_HEART_RATE_MEAS                 0x2A37
-/// Body Sensor Location
-#define    ESP_GATT_BODY_SENSOR_LOCATION            0x2A38
-/// Heart Rate Control Point
-#define    ESP_GATT_HEART_RATE_CNTL_POINT           0x2A39
-
-/* Battery Service characteristics */
-#define ESP_GATT_UUID_BATTERY_LEVEL                 0x2A19
-
-/* Sensor Service */
-#define ESP_GATT_UUID_SC_CONTROL_POINT              0x2A55
-#define ESP_GATT_UUID_SENSOR_LOCATION               0x2A5D
-
-/* Runners speed and cadence service */
-#define ESP_GATT_UUID_RSC_MEASUREMENT               0x2A53
-#define ESP_GATT_UUID_RSC_FEATURE                   0x2A54
-
-/* Cycling speed and cadence service */
-#define ESP_GATT_UUID_CSC_MEASUREMENT               0x2A5B
-#define ESP_GATT_UUID_CSC_FEATURE                   0x2A5C
-
-/* Scan ESP_Parameter characteristics */
-#define ESP_GATT_UUID_SCAN_INT_WINDOW               0x2A4F
-#define ESP_GATT_UUID_SCAN_REFRESH                  0x2A31
-/**
- * @}
- */
-
-/* relate to BTA_GATT_PREP_WRITE_xxx in bta/bta_gatt_api.h */
-/// Attribute write data type from the client
-typedef enum {
-    ESP_GATT_PREP_WRITE_CANCEL    = 0x00,       /*!< Prepare write cancel */  /* relate to BTA_GATT_PREP_WRITE_CANCEL in bta/bta_gatt_api.h */
-    ESP_GATT_PREP_WRITE_EXEC      = 0x01,       /*!< Prepare write execute */ /* relate to BTA_GATT_PREP_WRITE_EXEC in bta/bta_gatt_api.h */
-} esp_gatt_prep_write_type;
-
-/* relate to BTA_GATT_xxx in bta/bta_gatt_api.h */
-/**
- * @brief GATT success code and error codes
- */
-typedef enum {
-    ESP_GATT_OK                     =   0x0,                    /* relate to BTA_GATT_OK in bta/bta_gatt_api.h */
-    ESP_GATT_INVALID_HANDLE         =   0x01,   /* 0x0001 */    /* relate to BTA_GATT_INVALID_HANDLE in bta/bta_gatt_api.h */
-    ESP_GATT_READ_NOT_PERMIT        =   0x02,   /* 0x0002 */    /* relate to BTA_GATT_READ_NOT_PERMIT in bta/bta_gatt_api.h */
-    ESP_GATT_WRITE_NOT_PERMIT       =   0x03,   /* 0x0003 */    /* relate to BTA_GATT_WRITE_NOT_PERMIT in bta/bta_gatt_api.h */
-    ESP_GATT_INVALID_PDU            =   0x04,   /* 0x0004 */    /* relate to BTA_GATT_INVALID_PDU in bta/bta_gatt_api.h */
-    ESP_GATT_INSUF_AUTHENTICATION   =   0x05,   /* 0x0005 */    /* relate to BTA_GATT_INSUF_AUTHENTICATION in bta/bta_gatt_api.h */
-    ESP_GATT_REQ_NOT_SUPPORTED      =   0x06,   /* 0x0006 */    /* relate to BTA_GATT_REQ_NOT_SUPPORTED in bta/bta_gatt_api.h */
-    ESP_GATT_INVALID_OFFSET         =   0x07,   /* 0x0007 */    /* relate to BTA_GATT_INVALID_OFFSET in bta/bta_gatt_api.h */
-    ESP_GATT_INSUF_AUTHORIZATION    =   0x08,   /* 0x0008 */    /* relate to BTA_GATT_INSUF_AUTHORIZATION in bta/bta_gatt_api.h */
-    ESP_GATT_PREPARE_Q_FULL         =   0x09,   /* 0x0009 */    /* relate to BTA_GATT_PREPARE_Q_FULL in bta/bta_gatt_api.h */
-    ESP_GATT_NOT_FOUND              =   0x0a,   /* 0x000a */    /* relate to BTA_GATT_NOT_FOUND in bta/bta_gatt_api.h */
-    ESP_GATT_NOT_LONG               =   0x0b,   /* 0x000b */    /* relate to BTA_GATT_NOT_LONG in bta/bta_gatt_api.h */
-    ESP_GATT_INSUF_KEY_SIZE         =   0x0c,   /* 0x000c */    /* relate to BTA_GATT_INSUF_KEY_SIZE in bta/bta_gatt_api.h */
-    ESP_GATT_INVALID_ATTR_LEN       =   0x0d,   /* 0x000d */    /* relate to BTA_GATT_INVALID_ATTR_LEN in bta/bta_gatt_api.h */
-    ESP_GATT_ERR_UNLIKELY           =   0x0e,   /* 0x000e */    /* relate to BTA_GATT_ERR_UNLIKELY in bta/bta_gatt_api.h */
-    ESP_GATT_INSUF_ENCRYPTION       =   0x0f,   /* 0x000f */    /* relate to BTA_GATT_INSUF_ENCRYPTION in bta/bta_gatt_api.h */
-    ESP_GATT_UNSUPPORT_GRP_TYPE     =   0x10,   /* 0x0010 */    /* relate to BTA_GATT_UNSUPPORT_GRP_TYPE in bta/bta_gatt_api.h */
-    ESP_GATT_INSUF_RESOURCE         =   0x11,   /* 0x0011 */    /* relate to BTA_GATT_INSUF_RESOURCE in bta/bta_gatt_api.h */
-
-    ESP_GATT_NO_RESOURCES           =   0x80,   /* 0x80 */    /* relate to BTA_GATT_NO_RESOURCES in bta/bta_gatt_api.h */
-    ESP_GATT_INTERNAL_ERROR         =   0x81,   /* 0x81 */    /* relate to BTA_GATT_INTERNAL_ERROR in bta/bta_gatt_api.h */
-    ESP_GATT_WRONG_STATE            =   0x82,   /* 0x82 */    /* relate to BTA_GATT_WRONG_STATE in bta/bta_gatt_api.h */
-    ESP_GATT_DB_FULL                =   0x83,   /* 0x83 */    /* relate to BTA_GATT_DB_FULL in bta/bta_gatt_api.h */
-    ESP_GATT_BUSY                   =   0x84,   /* 0x84 */    /* relate to BTA_GATT_BUSY in bta/bta_gatt_api.h */
-    ESP_GATT_ERROR                  =   0x85,   /* 0x85 */    /* relate to BTA_GATT_ERROR in bta/bta_gatt_api.h */
-    ESP_GATT_CMD_STARTED            =   0x86,   /* 0x86 */    /* relate to BTA_GATT_CMD_STARTED in bta/bta_gatt_api.h */
-    ESP_GATT_ILLEGAL_PARAMETER      =   0x87,   /* 0x87 */    /* relate to BTA_GATT_ILLEGAL_PARAMETER in bta/bta_gatt_api.h */
-    ESP_GATT_PENDING                =   0x88,   /* 0x88 */    /* relate to BTA_GATT_PENDING in bta/bta_gatt_api.h */
-    ESP_GATT_AUTH_FAIL              =   0x89,   /* 0x89 */    /* relate to BTA_GATT_AUTH_FAIL in bta/bta_gatt_api.h */
-    ESP_GATT_MORE                   =   0x8a,   /* 0x8a */    /* relate to BTA_GATT_MORE in bta/bta_gatt_api.h */
-    ESP_GATT_INVALID_CFG            =   0x8b,   /* 0x8b */    /* relate to BTA_GATT_INVALID_CFG in bta/bta_gatt_api.h */
-    ESP_GATT_SERVICE_STARTED        =   0x8c,   /* 0x8c */    /* relate to BTA_GATT_SERVICE_STARTED in bta/bta_gatt_api.h */
-    ESP_GATT_ENCRYPED_MITM          =   ESP_GATT_OK,    /* relate to BTA_GATT_ENCRYPED_MITM in bta/bta_gatt_api.h */
-    ESP_GATT_ENCRYPED_NO_MITM       =   0x8d,   /* 0x8d */    /* relate to BTA_GATT_ENCRYPED_NO_MITM in bta/bta_gatt_api.h */
-    ESP_GATT_NOT_ENCRYPTED          =   0x8e,   /* 0x8e */    /* relate to BTA_GATT_NOT_ENCRYPTED in bta/bta_gatt_api.h */
-    ESP_GATT_CONGESTED              =   0x8f,   /* 0x8f */    /* relate to BTA_GATT_CONGESTED in bta/bta_gatt_api.h */
-    ESP_GATT_DUP_REG                =   0x90,   /* 0x90 */    /* relate to BTA_GATT_DUP_REG in bta/bta_gatt_api.h */
-    ESP_GATT_ALREADY_OPEN           =   0x91,   /* 0x91 */    /* relate to BTA_GATT_ALREADY_OPEN in bta/bta_gatt_api.h */
-    ESP_GATT_CANCEL                 =   0x92,   /* 0x92 */    /* relate to BTA_GATT_CANCEL in bta/bta_gatt_api.h */
-    /* 0xE0 ~ 0xFC reserved for future use */
-    ESP_GATT_STACK_RSP              =   0xe0,   /* 0xe0 */    /* relate to BTA_GATT_STACK_RSP in bta/bta_gatt_api.h */
-    ESP_GATT_APP_RSP                =   0xe1,   /* 0xe1 */    /* relate to BTA_GATT_APP_RSP in bta/bta_gatt_api.h */
-    //Error caused by customer application or stack bug
-    ESP_GATT_UNKNOWN_ERROR          =   0xef,   /* 0xef */    /* relate to BTA_GATT_UNKNOWN_ERROR in bta/bta_gatt_api.h */
-    ESP_GATT_CCC_CFG_ERR            =   0xfd,   /* 0xFD Client Characteristic Configuration Descriptor Improperly Configured */    /* relate to BTA_GATT_CCC_CFG_ERR in bta/bta_gatt_api.h */
-    ESP_GATT_PRC_IN_PROGRESS        =   0xfe,   /* 0xFE Procedure Already in progress */  /* relate to BTA_GATT_PRC_IN_PROGRESS in bta/bta_gatt_api.h */
-    ESP_GATT_OUT_OF_RANGE           =   0xff,   /* 0xFFAttribute value out of range */    /* relate to BTA_GATT_OUT_OF_RANGE in bta/bta_gatt_api.h */
-} esp_gatt_status_t;
-
-/* relate to BTA_GATT_CONN_xxx in bta/bta_gatt_api.h */
-/**
- * @brief Gatt Connection reason enum
- */
-typedef enum {
-    ESP_GATT_CONN_UNKNOWN = 0,                      /*!< Gatt connection unknown */               /* relate to BTA_GATT_CONN_UNKNOWN in bta/bta_gatt_api.h */
-    ESP_GATT_CONN_L2C_FAILURE = 1,                  /*!< General L2cap failure  */                /* relate to BTA_GATT_CONN_L2C_FAILURE in bta/bta_gatt_api.h */
-    ESP_GATT_CONN_TIMEOUT = 0x08,                   /*!< Connection timeout  */                   /* relate to BTA_GATT_CONN_TIMEOUT in bta/bta_gatt_api.h */
-    ESP_GATT_CONN_TERMINATE_PEER_USER = 0x13,       /*!< Connection terminate by peer user  */    /* relate to BTA_GATT_CONN_TERMINATE_PEER_USER in bta/bta_gatt_api.h */
-    ESP_GATT_CONN_TERMINATE_LOCAL_HOST = 0x16,      /*!< Connection terminated by local host */    /* relate to BTA_GATT_CONN_TERMINATE_LOCAL_HOST in bta/bta_gatt_api.h */
-    ESP_GATT_CONN_FAIL_ESTABLISH = 0x3e,            /*!< Connection fail to establish  */         /* relate to BTA_GATT_CONN_FAIL_ESTABLISH in bta/bta_gatt_api.h */
-    ESP_GATT_CONN_LMP_TIMEOUT = 0x22,               /*!< Connection fail for LMP response tout */ /* relate to BTA_GATT_CONN_LMP_TIMEOUT in bta/bta_gatt_api.h */
-    ESP_GATT_CONN_CONN_CANCEL = 0x0100,             /*!< L2CAP connection cancelled  */           /* relate to BTA_GATT_CONN_CONN_CANCEL in bta/bta_gatt_api.h */
-    ESP_GATT_CONN_NONE = 0x0101                     /*!< No connection to cancel  */              /* relate to BTA_GATT_CONN_NONE in bta/bta_gatt_api.h */
-} esp_gatt_conn_reason_t;
-
-/**
- * @brief Gatt id, include uuid and instance id
- */
-typedef struct {
-    esp_bt_uuid_t   uuid;                   /*!< UUID */
-    uint8_t         inst_id;                /*!< Instance id */
-} __attribute__((packed)) esp_gatt_id_t;
-
-/**
- * @brief Gatt service id, include id
- *        (uuid and instance id) and primary flag
- */
-typedef struct {
-    esp_gatt_id_t   id;                     /*!< Gatt id, include uuid and instance */
-    bool            is_primary;             /*!< This service is primary or not */
-} __attribute__((packed)) esp_gatt_srvc_id_t;
-
-/* relate to BTA_GATT_AUTH_REQ_xxx in bta/bta_gatt_api.h */
-/**
- * @brief Gatt authentication request type
- */
-typedef enum {
-    ESP_GATT_AUTH_REQ_NONE                  = 0,                                       /* relate to BTA_GATT_AUTH_REQ_NONE in bta/bta_gatt_api.h */
-    ESP_GATT_AUTH_REQ_NO_MITM               = 1,   /* unauthenticated encryption */    /* relate to BTA_GATT_AUTH_REQ_NO_MITM in bta/bta_gatt_api.h */
-    ESP_GATT_AUTH_REQ_MITM                  = 2,   /* authenticated encryption */      /* relate to BTA_GATT_AUTH_REQ_MITM in bta/bta_gatt_api.h */
-    ESP_GATT_AUTH_REQ_SIGNED_NO_MITM        = 3,                                       /* relate to BTA_GATT_AUTH_REQ_SIGNED_NO_MITM in bta/bta_gatt_api.h */
-    ESP_GATT_AUTH_REQ_SIGNED_MITM           = 4,                                       /* relate to BTA_GATT_AUTH_REQ_SIGNED_MITM in bta/bta_gatt_api.h */
-} esp_gatt_auth_req_t;
-
-/* relate to BTA_GATT_PERM_xxx in bta/bta_gatt_api.h */
-/**
- * @brief Attribute permissions
- */
-#define    ESP_GATT_PERM_READ                  (1 << 0)   /* bit 0 -  0x0001 */    /* relate to BTA_GATT_PERM_READ in bta/bta_gatt_api.h */
-#define    ESP_GATT_PERM_READ_ENCRYPTED        (1 << 1)   /* bit 1 -  0x0002 */    /* relate to BTA_GATT_PERM_READ_ENCRYPTED in bta/bta_gatt_api.h */
-#define    ESP_GATT_PERM_READ_ENC_MITM         (1 << 2)   /* bit 2 -  0x0004 */    /* relate to BTA_GATT_PERM_READ_ENC_MITM in bta/bta_gatt_api.h */
-#define    ESP_GATT_PERM_WRITE                 (1 << 4)   /* bit 4 -  0x0010 */    /* relate to BTA_GATT_PERM_WRITE in bta/bta_gatt_api.h */
-#define    ESP_GATT_PERM_WRITE_ENCRYPTED       (1 << 5)   /* bit 5 -  0x0020 */    /* relate to BTA_GATT_PERM_WRITE_ENCRYPTED in bta/bta_gatt_api.h */
-#define    ESP_GATT_PERM_WRITE_ENC_MITM        (1 << 6)   /* bit 6 -  0x0040 */    /* relate to BTA_GATT_PERM_WRITE_ENC_MITM in bta/bta_gatt_api.h */
-#define    ESP_GATT_PERM_WRITE_SIGNED          (1 << 7)   /* bit 7 -  0x0080 */    /* relate to BTA_GATT_PERM_WRITE_SIGNED in bta/bta_gatt_api.h */
-#define    ESP_GATT_PERM_WRITE_SIGNED_MITM     (1 << 8)   /* bit 8 -  0x0100 */    /* relate to BTA_GATT_PERM_WRITE_SIGNED_MITM in bta/bta_gatt_api.h */
-typedef uint16_t esp_gatt_perm_t;
-
-/* relate to BTA_GATT_CHAR_PROP_BIT_xxx in bta/bta_gatt_api.h */
-/* definition of characteristic properties */
-#define    ESP_GATT_CHAR_PROP_BIT_BROADCAST    (1 << 0)       /* 0x01 */    /* relate to BTA_GATT_CHAR_PROP_BIT_BROADCAST in bta/bta_gatt_api.h */
-#define    ESP_GATT_CHAR_PROP_BIT_READ         (1 << 1)       /* 0x02 */    /* relate to BTA_GATT_CHAR_PROP_BIT_READ in bta/bta_gatt_api.h */
-#define    ESP_GATT_CHAR_PROP_BIT_WRITE_NR     (1 << 2)       /* 0x04 */    /* relate to BTA_GATT_CHAR_PROP_BIT_WRITE_NR in bta/bta_gatt_api.h */
-#define    ESP_GATT_CHAR_PROP_BIT_WRITE        (1 << 3)       /* 0x08 */    /* relate to BTA_GATT_CHAR_PROP_BIT_WRITE in bta/bta_gatt_api.h */
-#define    ESP_GATT_CHAR_PROP_BIT_NOTIFY       (1 << 4)       /* 0x10 */    /* relate to BTA_GATT_CHAR_PROP_BIT_NOTIFY in bta/bta_gatt_api.h */
-#define    ESP_GATT_CHAR_PROP_BIT_INDICATE     (1 << 5)       /* 0x20 */    /* relate to BTA_GATT_CHAR_PROP_BIT_INDICATE in bta/bta_gatt_api.h */
-#define    ESP_GATT_CHAR_PROP_BIT_AUTH         (1 << 6)       /* 0x40 */    /* relate to BTA_GATT_CHAR_PROP_BIT_AUTH in bta/bta_gatt_api.h */
-#define    ESP_GATT_CHAR_PROP_BIT_EXT_PROP     (1 << 7)       /* 0x80 */    /* relate to BTA_GATT_CHAR_PROP_BIT_EXT_PROP in bta/bta_gatt_api.h */
-typedef uint8_t esp_gatt_char_prop_t;
-
-/// GATT maximum attribute length
-#define ESP_GATT_MAX_ATTR_LEN   600 //as same as GATT_MAX_ATTR_LEN
-
-typedef enum {
-    ESP_GATT_SERVICE_FROM_REMOTE_DEVICE         = 0,                                       /* relate to BTA_GATTC_SERVICE_INFO_FROM_REMOTE_DEVICE in bta_gattc_int.h */
-    ESP_GATT_SERVICE_FROM_NVS_FLASH             = 1,                                       /* relate to BTA_GATTC_SERVICE_INFO_FROM_NVS_FLASH in bta_gattc_int.h */
-    ESP_GATT_SERVICE_FROM_UNKNOWN               = 2,                                       /* relate to BTA_GATTC_SERVICE_INFO_FROM_UNKNOWN in bta_gattc_int.h */
-} esp_service_source_t;
-
-/**
- * @brief Attribute description (used to create database)
- */
- typedef struct
- {
-     uint16_t uuid_length;              /*!< UUID length */
-     uint8_t  *uuid_p;                  /*!< UUID value */
-     uint16_t perm;                     /*!< Attribute permission */
-     uint16_t max_length;               /*!< Maximum length of the element*/
-     uint16_t length;                   /*!< Current length of the element*/
-     uint8_t  *value;                   /*!< Element value array*/
- } esp_attr_desc_t;
-
-
-/**
- * @brief attribute auto response flag
- */
-typedef struct
-{
-#define ESP_GATT_RSP_BY_APP             0
-#define ESP_GATT_AUTO_RSP               1
-    /**
-     * @brief if auto_rsp set to ESP_GATT_RSP_BY_APP, means the response of Write/Read operation will by replied by application.
-              if auto_rsp set to ESP_GATT_AUTO_RSP, means the response of Write/Read operation will be replied by GATT stack automatically.
-     */
-    uint8_t auto_rsp;
-} esp_attr_control_t;
-
-
-/**
- * @brief attribute type added to the gatt server database
- */
-typedef struct
-{
-    esp_attr_control_t      attr_control;                   /*!< The attribute control type */
-    esp_attr_desc_t         att_desc;                       /*!< The attribute type */
-} esp_gatts_attr_db_t;
-
-
-/**
-  * @brief set the attribute value type
-  */
-typedef struct
-{
-    uint16_t attr_max_len;                                  /*!<  attribute max value length */
-    uint16_t attr_len;                                      /*!<  attribute current value length */
-    uint8_t  *attr_value;                                   /*!<  the pointer to attribute value */
-} esp_attr_value_t;
-
-
-/**
-  * @brief Gatt  include service entry element
-  */
-typedef struct
-{
-    uint16_t start_hdl;                                     /*!< Gatt start handle value of included service */
-    uint16_t end_hdl;                                       /*!< Gatt end handle value of included service */
-    uint16_t uuid;                                          /*!< Gatt attribute value UUID of included service */
-} esp_gatts_incl_svc_desc_t;                                /*!< Gatt include service entry element */
-
-/**
-  * @brief Gatt  include 128 bit service entry element
-  */
-typedef struct
-{
-    uint16_t start_hdl;                                     /*!< Gatt start handle value of included 128 bit service */
-    uint16_t end_hdl;                                       /*!< Gatt end handle value of included 128 bit service */
-} esp_gatts_incl128_svc_desc_t;                             /*!< Gatt include 128 bit service entry element */
-
-/// Gatt attribute value
-typedef struct {
-    uint8_t           value[ESP_GATT_MAX_ATTR_LEN];         /*!< Gatt attribute value */
-    uint16_t          handle;                               /*!< Gatt attribute handle */
-    uint16_t          offset;                               /*!< Gatt attribute value offset */
-    uint16_t          len;                                  /*!< Gatt attribute value length */
-    uint8_t           auth_req;                             /*!< Gatt authentication request */
-} esp_gatt_value_t;
-
-/// GATT remote read request response type
-typedef union {
-    esp_gatt_value_t attr_value;                            /*!< Gatt attribute structure */
-    uint16_t            handle;                             /*!< Gatt attribute handle */
-} esp_gatt_rsp_t;
-
-/**
-  * @brief Gatt write type
-  */
-typedef enum {
-    ESP_GATT_WRITE_TYPE_NO_RSP  =   1,                      /*!< Gatt write attribute need no response */
-    ESP_GATT_WRITE_TYPE_RSP,                                /*!< Gatt write attribute need remote response */
-} esp_gatt_write_type_t;
-
-#define ESP_GATT_IF_NONE    0xff                            /*!< If callback report gattc_if/gatts_if as this macro, means this event is not correspond to any app */
-
-typedef uint8_t    esp_gatt_if_t;                           /*!< Gatt interface type, different application on GATT client use different gatt_if */
-
-/**
-  * @brief the type of attribute element
-  */
-typedef enum {
-    ESP_GATT_DB_PRIMARY_SERVICE,                            /*!< Gattc primary service attribute type in the cache */
-    ESP_GATT_DB_SECONDARY_SERVICE,                          /*!< Gattc secondary service attribute type in the cache */
-    ESP_GATT_DB_CHARACTERISTIC,                             /*!< Gattc characteristic attribute type in the cache */
-    ESP_GATT_DB_DESCRIPTOR,                                 /*!< Gattc characteristic descriptor attribute type in the cache */
-    ESP_GATT_DB_INCLUDED_SERVICE,                           /*!< Gattc include service attribute type in the cache */
-    ESP_GATT_DB_ALL,                                        /*!< Gattc all the attribute (primary service & secondary service & include service & char & descriptor) type in the cache */
-} esp_gatt_db_attr_type_t;                                  /*!< Gattc attribute type element */
-
-/**
-  * @brief read multiple attribute
-  */
-typedef struct {
-    uint8_t  num_attr;                                      /*!< The number of the attribute */
-    uint16_t handles[ESP_GATT_MAX_READ_MULTI_HANDLES];      /*!< The handles list */
-} esp_gattc_multi_t;                                        /*!< The gattc multiple read element */
-
-/**
-  * @brief data base attribute element
-  */
-typedef struct {
-    esp_gatt_db_attr_type_t     type;                       /*!< The attribute type */
-    uint16_t                    attribute_handle;           /*!< The attribute handle, it's valid for all of the type */
-    uint16_t                    start_handle;               /*!< The service start handle, it's valid only when the type = ESP_GATT_DB_PRIMARY_SERVICE or ESP_GATT_DB_SECONDARY_SERVICE */
-    uint16_t                    end_handle;                 /*!< The service end handle, it's valid only when the type = ESP_GATT_DB_PRIMARY_SERVICE or ESP_GATT_DB_SECONDARY_SERVICE */
-    esp_gatt_char_prop_t        properties;                 /*!< The characteristic properties, it's valid only when the type = ESP_GATT_DB_CHARACTERISTIC */
-    esp_bt_uuid_t               uuid;                       /*!< The attribute uuid, it's valid for all of the type */
-} esp_gattc_db_elem_t;                                      /*!< The gattc service data base element in the cache */
-
-/**
-  * @brief service element
-  */
-typedef struct {
-    bool                        is_primary;                 /*!< The service flag, true if the service is primary service, else is secondary service */
-    uint16_t                    start_handle;               /*!< The start handle of the service */
-    uint16_t                    end_handle;                 /*!< The end handle of the service */
-    esp_bt_uuid_t               uuid;                       /*!< The uuid of the service */
-} esp_gattc_service_elem_t;                                 /*!< The gattc service element */
-
-/**
-  * @brief characteristic element
-  */
-typedef struct {
-    uint16_t                    char_handle;                /*!< The characteristic handle */
-    esp_gatt_char_prop_t        properties;                 /*!< The characteristic properties */
-    esp_bt_uuid_t               uuid;                       /*!< The characteristic uuid */
-} esp_gattc_char_elem_t;                                    /*!< The gattc characteristic element */
-
-/**
-  * @brief descriptor element
-  */
-typedef struct {
-    uint16_t                   handle;                      /*!< The characteristic descriptor handle */
-    esp_bt_uuid_t              uuid;                        /*!< The characteristic descriptor uuid */
-} esp_gattc_descr_elem_t;                                   /*!< The gattc descriptor type element */
-
-/**
-  * @brief include service element
-  */
-typedef struct {
-    uint16_t                   handle;                      /*!< The include service current attribute handle */
-    uint16_t                   incl_srvc_s_handle;          /*!< The start handle of the service which has been included */
-    uint16_t                   incl_srvc_e_handle;          /*!< The end handle of the service which has been included */
-    esp_bt_uuid_t              uuid;                        /*!< The include service uuid */
-} esp_gattc_incl_svc_elem_t;                                /*!< The gattc include service element */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_GATT_DEFS_H__ */
diff --git a/tools/sdk/include/bt/esp_gattc_api.h b/tools/sdk/include/bt/esp_gattc_api.h
deleted file mode 100644
index b494bcfd398..00000000000
--- a/tools/sdk/include/bt/esp_gattc_api.h
+++ /dev/null
@@ -1,845 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_GATTC_API_H__
-#define __ESP_GATTC_API_H__
-
-#include "esp_bt_defs.h"
-#include "esp_gatt_defs.h"
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/// GATT Client callback function events
-typedef enum {
-    ESP_GATTC_REG_EVT                 = 0,        /*!< When GATT client is registered, the event comes */
-    ESP_GATTC_UNREG_EVT               = 1,        /*!< When GATT client is unregistered, the event comes */
-    ESP_GATTC_OPEN_EVT                = 2,        /*!< When GATT virtual connection is set up, the event comes */
-    ESP_GATTC_READ_CHAR_EVT           = 3,        /*!< When GATT characteristic is read, the event comes */
-    ESP_GATTC_WRITE_CHAR_EVT          = 4,        /*!< When GATT characteristic write operation completes, the event comes */
-    ESP_GATTC_CLOSE_EVT               = 5,        /*!< When GATT virtual connection is closed, the event comes */
-    ESP_GATTC_SEARCH_CMPL_EVT         = 6,        /*!< When GATT service discovery is completed, the event comes */
-    ESP_GATTC_SEARCH_RES_EVT          = 7,        /*!< When GATT service discovery result is got, the event comes */
-    ESP_GATTC_READ_DESCR_EVT          = 8,        /*!< When GATT characteristic descriptor read completes, the event comes */
-    ESP_GATTC_WRITE_DESCR_EVT         = 9,        /*!< When GATT characteristic descriptor write completes, the event comes */
-    ESP_GATTC_NOTIFY_EVT              = 10,       /*!< When GATT notification or indication arrives, the event comes */
-    ESP_GATTC_PREP_WRITE_EVT          = 11,       /*!< When GATT prepare-write operation completes, the event comes */
-    ESP_GATTC_EXEC_EVT                = 12,       /*!< When write execution completes, the event comes */
-    ESP_GATTC_ACL_EVT                 = 13,       /*!< When ACL connection is up, the event comes */
-    ESP_GATTC_CANCEL_OPEN_EVT         = 14,       /*!< When GATT client ongoing connection is cancelled, the event comes */
-    ESP_GATTC_SRVC_CHG_EVT            = 15,       /*!< When "service changed" occurs, the event comes */
-    ESP_GATTC_ENC_CMPL_CB_EVT         = 17,       /*!< When encryption procedure completes, the event comes */
-    ESP_GATTC_CFG_MTU_EVT             = 18,       /*!< When configuration of MTU completes, the event comes */
-    ESP_GATTC_ADV_DATA_EVT            = 19,       /*!< When advertising of data, the event comes */
-    ESP_GATTC_MULT_ADV_ENB_EVT        = 20,       /*!< When multi-advertising is enabled, the event comes */
-    ESP_GATTC_MULT_ADV_UPD_EVT        = 21,       /*!< When multi-advertising parameters are updated, the event comes */
-    ESP_GATTC_MULT_ADV_DATA_EVT       = 22,       /*!< When multi-advertising data arrives, the event comes */
-    ESP_GATTC_MULT_ADV_DIS_EVT        = 23,       /*!< When multi-advertising is disabled, the event comes */
-    ESP_GATTC_CONGEST_EVT             = 24,       /*!< When GATT connection congestion comes, the event comes */
-    ESP_GATTC_BTH_SCAN_ENB_EVT        = 25,       /*!< When batch scan is enabled, the event comes */
-    ESP_GATTC_BTH_SCAN_CFG_EVT        = 26,       /*!< When batch scan storage is configured, the event comes */
-    ESP_GATTC_BTH_SCAN_RD_EVT         = 27,       /*!< When Batch scan read event is reported, the event comes */
-    ESP_GATTC_BTH_SCAN_THR_EVT        = 28,       /*!< When Batch scan threshold is set, the event comes */
-    ESP_GATTC_BTH_SCAN_PARAM_EVT      = 29,       /*!< When Batch scan parameters are set, the event comes */
-    ESP_GATTC_BTH_SCAN_DIS_EVT        = 30,       /*!< When Batch scan is disabled, the event comes */
-    ESP_GATTC_SCAN_FLT_CFG_EVT        = 31,       /*!< When Scan filter configuration completes, the event comes */
-    ESP_GATTC_SCAN_FLT_PARAM_EVT      = 32,       /*!< When Scan filter parameters are set, the event comes */
-    ESP_GATTC_SCAN_FLT_STATUS_EVT     = 33,       /*!< When Scan filter status is reported, the event comes */
-    ESP_GATTC_ADV_VSC_EVT             = 34,       /*!< When advertising vendor spec content event is reported, the event comes */
-    ESP_GATTC_REG_FOR_NOTIFY_EVT      = 38,       /*!< When register for notification of a service completes, the event comes */
-    ESP_GATTC_UNREG_FOR_NOTIFY_EVT    = 39,       /*!< When unregister for notification of a service completes, the event comes */
-    ESP_GATTC_CONNECT_EVT             = 40,       /*!< When the ble physical connection is set up, the event comes */
-    ESP_GATTC_DISCONNECT_EVT          = 41,       /*!< When the ble physical connection disconnected, the event comes */
-    ESP_GATTC_READ_MULTIPLE_EVT       = 42,       /*!< When the ble characteristic or descriptor multiple complete, the event comes */
-    ESP_GATTC_QUEUE_FULL_EVT          = 43,       /*!< When the gattc command queue full, the event comes */
-    ESP_GATTC_SET_ASSOC_EVT           = 44,       /*!< When the ble gattc set the associated address complete, the event comes */
-    ESP_GATTC_GET_ADDR_LIST_EVT       = 45,       /*!< When the ble get gattc address list in cache finish, the event comes */
-} esp_gattc_cb_event_t;
-
-
-/**
- * @brief Gatt client callback parameters union
- */
-typedef union {
-    /**
-     * @brief ESP_GATTC_REG_EVT
-     */
-    struct gattc_reg_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t app_id;                /*!< Application id which input in register API */
-    } reg;                              /*!< Gatt client callback param of ESP_GATTC_REG_EVT */
-
-    /**
-     * @brief ESP_GATTC_OPEN_EVT
-     */
-    struct gattc_open_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t conn_id;               /*!< Connection id */
-        esp_bd_addr_t remote_bda;       /*!< Remote bluetooth device address */
-        uint16_t mtu;                   /*!< MTU size */
-    } open;                             /*!< Gatt client callback param of ESP_GATTC_OPEN_EVT */
-
-    /**
-     * @brief ESP_GATTC_CLOSE_EVT
-     */
-    struct gattc_close_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t conn_id;               /*!< Connection id */
-        esp_bd_addr_t remote_bda;       /*!< Remote bluetooth device address */
-        esp_gatt_conn_reason_t reason;  /*!< The reason of gatt connection close */
-    } close;                            /*!< Gatt client callback param of ESP_GATTC_CLOSE_EVT */
-
-    /**
-     * @brief ESP_GATTC_CFG_MTU_EVT
-     */
-    struct gattc_cfg_mtu_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t conn_id;               /*!< Connection id */
-        uint16_t mtu;                   /*!< MTU size */
-    } cfg_mtu;                          /*!< Gatt client callback param of ESP_GATTC_CFG_MTU_EVT */
-
-    /**
-     * @brief ESP_GATTC_SEARCH_CMPL_EVT
-     */
-    struct gattc_search_cmpl_evt_param {
-        esp_gatt_status_t status;                     /*!< Operation status */
-        uint16_t conn_id;                             /*!< Connection id */
-        esp_service_source_t searched_service_source; /*!< The source of the service information */
-    } search_cmpl;                                    /*!< Gatt client callback param of ESP_GATTC_SEARCH_CMPL_EVT */
-
-    /**
-     * @brief ESP_GATTC_SEARCH_RES_EVT
-     */
-    struct gattc_search_res_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        uint16_t start_handle;          /*!< Service start handle */
-        uint16_t end_handle;            /*!< Service end handle */
-        esp_gatt_id_t srvc_id;          /*!< Service id, include service uuid and other information */
-        bool      is_primary;           /*!< True if this is the primary service */
-    } search_res;                       /*!< Gatt client callback param of ESP_GATTC_SEARCH_RES_EVT */
-
-    /**
-     * @brief ESP_GATTC_READ_CHAR_EVT,  ESP_GATTC_READ_DESCR_EVT
-     */
-    struct gattc_read_char_evt_param {
-
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t conn_id;               /*!< Connection id */
-        uint16_t handle;                /*!< Characteristic handle */
-        uint8_t *value;                 /*!< Characteristic value */
-        uint16_t value_len;             /*!< Characteristic value length */
-    } read;                             /*!< Gatt client callback param of ESP_GATTC_READ_CHAR_EVT */
-
-    /**
-     * @brief ESP_GATTC_WRITE_CHAR_EVT, ESP_GATTC_PREP_WRITE_EVT, ESP_GATTC_WRITE_DESCR_EVT
-     */
-    struct gattc_write_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t conn_id;               /*!< Connection id */
-        uint16_t handle;                /*!< The Characteristic or descriptor handle */
-        uint16_t offset;                /*!< The prepare write offset, this value is valid only when prepare write */
-    } write;                            /*!< Gatt client callback param of ESP_GATTC_WRITE_DESCR_EVT */
-
-    /**
-     * @brief ESP_GATTC_EXEC_EVT
-     */
-    struct gattc_exec_cmpl_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t conn_id;               /*!< Connection id */
-    } exec_cmpl;                        /*!< Gatt client callback param of ESP_GATTC_EXEC_EVT */
-
-    /**
-     * @brief ESP_GATTC_NOTIFY_EVT
-     */
-    struct gattc_notify_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        esp_bd_addr_t remote_bda;       /*!< Remote bluetooth device address */
-        uint16_t handle;                /*!< The Characteristic or descriptor handle */
-        uint16_t value_len;             /*!< Notify attribute value */
-        uint8_t *value;                 /*!< Notify attribute value */
-        bool is_notify;                 /*!< True means notify, false means indicate */
-    } notify;                           /*!< Gatt client callback param of ESP_GATTC_NOTIFY_EVT */
-
-    /**
-     * @brief ESP_GATTC_SRVC_CHG_EVT
-	 */
-    struct gattc_srvc_chg_evt_param {
-        esp_bd_addr_t remote_bda;       /*!< Remote bluetooth device address */
-    } srvc_chg;                         /*!< Gatt client callback param of ESP_GATTC_SRVC_CHG_EVT */
-
-    /**
-     * @brief ESP_GATTC_CONGEST_EVT
-     */
-    struct gattc_congest_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        bool congested;                 /*!< Congested or not */
-    } congest;                          /*!< Gatt client callback param of ESP_GATTC_CONGEST_EVT */
-    /**
-     * @brief ESP_GATTC_REG_FOR_NOTIFY_EVT
-     */
-    struct gattc_reg_for_notify_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t handle;                /*!< The characteristic or descriptor handle */
-    } reg_for_notify;                   /*!< Gatt client callback param of ESP_GATTC_REG_FOR_NOTIFY_EVT */
-
-    /**
-     * @brief ESP_GATTC_UNREG_FOR_NOTIFY_EVT
-     */
-    struct gattc_unreg_for_notify_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t handle;                /*!< The characteristic or descriptor handle */
-    } unreg_for_notify;                 /*!< Gatt client callback param of ESP_GATTC_UNREG_FOR_NOTIFY_EVT */
-
-    /**
-     * @brief ESP_GATTC_CONNECT_EVT
-     */
-    struct gattc_connect_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        esp_bd_addr_t remote_bda;       /*!< Remote bluetooth device address */
-    } connect;                          /*!< Gatt client callback param of ESP_GATTC_CONNECT_EVT */
-
-    /**
-     * @brief ESP_GATTC_DISCONNECT_EVT
-     */
-    struct gattc_disconnect_evt_param {
-        esp_gatt_conn_reason_t reason;  /*!< disconnection reason */
-        uint16_t conn_id;               /*!< Connection id */
-        esp_bd_addr_t remote_bda;       /*!< Remote bluetooth device address */
-    } disconnect;                       /*!< Gatt client callback param of ESP_GATTC_DISCONNECT_EVT */
-    /**
-     * @brief ESP_GATTC_SET_ASSOC_EVT
-     */
-    struct gattc_set_assoc_addr_cmp_evt_param {
-        esp_gatt_status_t status;      /*!< Operation status */
-    } set_assoc_cmp;                     /*!< Gatt client callback param of ESP_GATTC_SET_ASSOC_EVT */
-    /**
-     * @brief ESP_GATTC_GET_ADDR_LIST_EVT
-     */
-    struct gattc_get_addr_list_evt_param {
-        esp_gatt_status_t status;      /*!< Operation status */
-        uint8_t num_addr;              /*!< The number of address in the gattc cache address list */
-        esp_bd_addr_t *addr_list;      /*!< The pointer to the address list which has been get from the gattc cache */
-    } get_addr_list;                   /*!< Gatt client callback param of ESP_GATTC_GET_ADDR_LIST_EVT */
-
-    /**
-     * @brief ESP_GATTC_QUEUE_FULL_EVT
-     */
-    struct gattc_queue_full_evt_param {
-        esp_gatt_status_t status;      /*!< Operation status */
-        uint16_t conn_id;              /*!< Connection id */
-        bool     is_full;              /*!< The gattc command queue is full or not */
-    } queue_full;                      /*!< Gatt client callback param of ESP_GATTC_QUEUE_FULL_EVT */
-
-} esp_ble_gattc_cb_param_t;             /*!< GATT client callback parameter union type */
-
-/**
- * @brief GATT Client callback function type
- * @param event : Event type
- * @param gatts_if : GATT client access interface, normally
- *                   different gattc_if correspond to different profile
- * @param param : Point to callback parameter, currently is union type
- */
-typedef void (* esp_gattc_cb_t)(esp_gattc_cb_event_t event, esp_gatt_if_t gattc_if, esp_ble_gattc_cb_param_t *param);
-
-/**
- * @brief           This function is called to register application callbacks
- *                  with GATTC module.
- *
- * @param[in]       callback : pointer to the application callback function.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_register_callback(esp_gattc_cb_t callback);
-
-
-/**
- * @brief           This function is called to register application callbacks
- *                  with GATTC module.
- *
- * @param[in]       app_id : Application Identify (UUID), for different application
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_app_register(uint16_t app_id);
-
-
-/**
- * @brief           This function is called to unregister an application
- *                  from GATTC module.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_app_unregister(esp_gatt_if_t gattc_if);
-
-
-/**
- * @brief           Open a direct connection or add a background auto connection
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       remote_bda: remote device bluetooth device address.
- * @param[in]       remote_addr_type: remote device bluetooth device the address type.
- * @param[in]       is_direct: direct connection or background auto connection
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_open(esp_gatt_if_t gattc_if, esp_bd_addr_t remote_bda, esp_ble_addr_type_t remote_addr_type, bool is_direct);
-
-
-/**
- * @brief           Close the virtual connection to the GATT server. gattc may have multiple virtual GATT server connections when multiple app_id registered,
- *                  this API only close one virtual GATT server connection. if there exist other virtual GATT server connections,
- *                  it does not disconnect the physical connection.
- *                  if you want to disconnect the physical connection directly, you can use esp_ble_gap_disconnect(esp_bd_addr_t remote_device).
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID to be closed.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_close (esp_gatt_if_t gattc_if, uint16_t conn_id);
-
-
-/**
- * @brief           Configure the MTU size in the GATT channel. This can be done
- *                  only once per connection. Before using, use esp_ble_gatt_set_local_mtu()
- *                  to configure the local MTU size.
- *
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_send_mtu_req (esp_gatt_if_t gattc_if, uint16_t conn_id);
-
-
-/**
- * @brief           This function is called to get service from local cache. 
- *                  If it does not exist, request a GATT service discovery
- *                  on a GATT server. This function report service search result
- *                  by a callback event, and followed by a service search complete
- *                  event.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID.
- * @param[in]       filter_uuid: a UUID of the service application is interested in.
- *                  If Null, discover for all services.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_search_service(esp_gatt_if_t gattc_if, uint16_t conn_id, esp_bt_uuid_t *filter_uuid);
-
-/**
- * @brief           Find all the service with the given service uuid in the gattc cache, if the svc_uuid is NULL, find all the service.
- *                  Note: It just get service from local cache, won't get from remote devices. If want to get it from remote device, need
- *                  to used the esp_ble_gattc_search_service.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID which identify the server.
- * @param[in]       svc_uuid: the pointer to the service uuid.
- * @param[out]      result: The pointer to the service which has been found in the gattc cache.
- * @param[inout]   count: input the number of service want to find,
- *                         it will output the number of service has been found in the gattc cache with the given service uuid.
- * @param[in]       offset: Offset of the service position to get.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_gatt_status_t esp_ble_gattc_get_service(esp_gatt_if_t gattc_if, uint16_t conn_id, esp_bt_uuid_t *svc_uuid,
-                                            esp_gattc_service_elem_t *result, uint16_t *count, uint16_t offset);
-
-/**
- * @brief           Find all the characteristic with the given service in the gattc cache
- *                  Note: It just get characteristic from local cache, won't get from remote devices.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID which identify the server.
- * @param[in]       start_handle: the attribute start handle.
- * @param[in]       end_handle: the attribute end handle
- * @param[out]      result: The pointer to the characteristic in the service.
- * @param[inout]   count: input the number of characteristic want to find,
- *                         it will output the number of characteristic has been found in the gattc cache with the given service.
- * @param[in]       offset: Offset of the characteristic position to get.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_gatt_status_t esp_ble_gattc_get_all_char(esp_gatt_if_t gattc_if,
-                                             uint16_t conn_id,
-                                             uint16_t start_handle,
-                                             uint16_t end_handle,
-                                             esp_gattc_char_elem_t *result,
-                                             uint16_t *count, uint16_t offset);
-
-/**
- * @brief           Find all the descriptor with the given characteristic in the gattc cache
- *                  Note: It just get descriptor from local cache, won't get from remote devices.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID which identify the server.
- * @param[in]       char_handle: the given characteristic handle
- * @param[out]      result: The pointer to the descriptor in the characteristic.
- * @param[inout]    count: input the number of descriptor want to find,
- *                         it will output the number of descriptor has been found in the gattc cache with the given characteristic.
- * @param[in]       offset: Offset of the descriptor position to get.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_gatt_status_t esp_ble_gattc_get_all_descr(esp_gatt_if_t gattc_if,
-                                              uint16_t conn_id,
-                                              uint16_t char_handle,
-                                              esp_gattc_descr_elem_t *result,
-                                              uint16_t *count, uint16_t offset);
-
-
-/**
- * @brief           Find the characteristic with the given characteristic uuid in the gattc cache
- *                  Note: It just get characteristic from local cache, won't get from remote devices.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID which identify the server.
- * @param[in]       start_handle: the attribute start handle
- * @param[in]       end_handle: the attribute end handle
- * @param[in]       char_uuid: the characteristic uuid
- * @param[out]      result: The pointer to the characteristic in the service.
- * @param[inout]   count: input the number of characteristic want to find,
- *                         it will output the number of characteristic has been found in the gattc cache with the given service.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_gatt_status_t esp_ble_gattc_get_char_by_uuid(esp_gatt_if_t gattc_if,
-                                                 uint16_t conn_id,
-                                                 uint16_t start_handle,
-                                                 uint16_t end_handle,
-                                                 esp_bt_uuid_t char_uuid,
-                                                 esp_gattc_char_elem_t *result,
-                                                 uint16_t *count);
-
-/**
- * @brief           Find the descriptor with the given characteristic uuid in the gattc cache
- *                  Note: It just get descriptor from local cache, won't get from remote devices.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID which identify the server.
- * @param[in]       start_handle: the attribute start handle
- * @param[in]       end_handle: the attribute end handle
- * @param[in]       char_uuid: the characteristic uuid.
- * @param[in]       descr_uuid: the descriptor uuid.
- * @param[out]      result: The pointer to the descriptor in the given characteristic.
- * @param[inout]   count: input the number of descriptor want to find,
- *                         it will output the number of descriptor has been found in the gattc cache with the given characteristic.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_gatt_status_t esp_ble_gattc_get_descr_by_uuid(esp_gatt_if_t gattc_if,
-                                                  uint16_t conn_id,
-                                                  uint16_t start_handle,
-                                                  uint16_t end_handle,
-                                                  esp_bt_uuid_t char_uuid,
-                                                  esp_bt_uuid_t descr_uuid,
-                                                  esp_gattc_descr_elem_t *result,
-                                                  uint16_t *count);
-
-/**
- * @brief           Find the descriptor with the given characteristic handle in the gattc cache
- *                  Note: It just get descriptor from local cache, won't get from remote devices.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID which identify the server.
- * @param[in]       char_handle: the characteristic handle.
- * @param[in]       descr_uuid: the descriptor uuid.
- * @param[out]      result: The pointer to the descriptor in the given characteristic.
- * @param[inout]   count: input the number of descriptor want to find,
- *                         it will output the number of descriptor has been found in the gattc cache with the given characteristic.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_gatt_status_t esp_ble_gattc_get_descr_by_char_handle(esp_gatt_if_t gattc_if,
-                                                         uint16_t conn_id,
-                                                         uint16_t char_handle,
-                                                         esp_bt_uuid_t descr_uuid,
-                                                         esp_gattc_descr_elem_t *result,
-                                                         uint16_t *count);
-
-/**
- * @brief           Find the include service with the given service handle in the gattc cache
- *                  Note: It just get include service from local cache, won't get from remote devices.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID which identify the server.
- * @param[in]       start_handle: the attribute start handle
- * @param[in]       end_handle: the attribute end handle
- * @param[in]       incl_uuid: the include service uuid
- * @param[out]      result: The pointer to the include service in the given service.
- * @param[inout]   count: input the number of include service want to find,
- *                         it will output the number of include service has been found in the gattc cache with the given service.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_gatt_status_t esp_ble_gattc_get_include_service(esp_gatt_if_t gattc_if,
-                                                    uint16_t conn_id,
-                                                    uint16_t start_handle,
-                                                    uint16_t end_handle,
-                                                    esp_bt_uuid_t *incl_uuid,
-                                                    esp_gattc_incl_svc_elem_t *result,
-                                                    uint16_t *count);
-
-
-/**
- * @brief           Find the attribute count with the given service or characteristic in the gattc cache
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id: connection ID which identify the server.
- * @param[in]       type: the attribute type.
- * @param[in]       start_handle: the attribute start handle, if the type is ESP_GATT_DB_DESCRIPTOR, this parameter should be ignore
- * @param[in]       end_handle: the attribute end handle, if the type is ESP_GATT_DB_DESCRIPTOR, this parameter should be ignore
- * @param[in]       char_handle: the characteristic handle, this parameter valid when the type is ESP_GATT_DB_DESCRIPTOR. If the type
- *                               isn't ESP_GATT_DB_DESCRIPTOR, this parameter should be ignore.
- * @param[out]      count: output the number of attribute has been found in the gattc cache with the given attribute type.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_gatt_status_t esp_ble_gattc_get_attr_count(esp_gatt_if_t gattc_if,
-                                               uint16_t conn_id,
-                                               esp_gatt_db_attr_type_t type,
-                                               uint16_t start_handle,
-                                               uint16_t end_handle,
-                                               uint16_t char_handle,
-                                               uint16_t *count);
-
-/**
- * @brief           This function is called to get the GATT database.
- *                  Note: It just get attribute data base from local cache, won't get from remote devices.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       start_handle: the attribute start handle
- * @param[in]       end_handle: the attribute end handle
- * @param[in]       conn_id: connection ID which identify the server.
- * @param[in]       db: output parameter which will contain the GATT database copy.
- *                      Caller is responsible for freeing it.
- * @param[in]       count: number of elements in database.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_gatt_status_t esp_ble_gattc_get_db(esp_gatt_if_t gattc_if, uint16_t conn_id, uint16_t start_handle, uint16_t end_handle,
-                                        esp_gattc_db_elem_t *db, uint16_t *count);
-
-/**
- * @brief           This function is called to read a service's characteristics of
- *                  the given characteristic handle
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id : connection ID.
- * @param[in]       handle : characteritic handle to read.
- * @param[in]       auth_req : authenticate request type
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_read_char (esp_gatt_if_t gattc_if,
-                                   uint16_t conn_id,
-                                   uint16_t handle,
-                                   esp_gatt_auth_req_t auth_req);
-
-/**
- * @brief           This function is called to read multiple characteristic or
- *                  characteristic descriptors.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id : connection ID.
- * @param[in]       read_multi : pointer to the read multiple parameter.
- * @param[in]       auth_req : authenticate request type
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_read_multiple(esp_gatt_if_t gattc_if,
-                                      uint16_t conn_id, esp_gattc_multi_t *read_multi,
-                                      esp_gatt_auth_req_t auth_req);
-
-
-/**
- * @brief           This function is called to read a characteristics descriptor.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id : connection ID.
- * @param[in]       handle : descriptor handle to read.
- * @param[in]       auth_req : authenticate request type
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_read_char_descr (esp_gatt_if_t gattc_if,
-                                         uint16_t conn_id,
-                                         uint16_t handle,
-                                         esp_gatt_auth_req_t auth_req);
-
-
-/**
- * @brief           This function is called to write characteristic value.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id : connection ID.
- * @param[in]       handle : characteristic handle to write.
- * @param[in]       value_len: length of the value to be written.
- * @param[in]       value : the value to be written.
- * @param[in]       write_type : the type of attribute write operation.
- * @param[in]       auth_req : authentication request.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_write_char( esp_gatt_if_t gattc_if,
-                                    uint16_t conn_id,
-                                    uint16_t handle,
-                                    uint16_t value_len,
-                                    uint8_t *value,
-                                    esp_gatt_write_type_t write_type,
-                                    esp_gatt_auth_req_t auth_req);
-
-
-/**
- * @brief           This function is called to write characteristic descriptor value.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id : connection ID
- * @param[in]       handle : descriptor hadle to write.
- * @param[in]       value_len: length of the value to be written.
- * @param[in]       value : the value to be written.
- * @param[in]       write_type : the type of attribute write operation.
- * @param[in]       auth_req : authentication request.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_write_char_descr (esp_gatt_if_t gattc_if,
-                                         uint16_t conn_id,
-                                         uint16_t handle,
-                                         uint16_t value_len,
-                                         uint8_t *value,
-                                         esp_gatt_write_type_t write_type,
-                                         esp_gatt_auth_req_t auth_req);
-
-
-/**
- * @brief           This function is called to prepare write a characteristic value.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id : connection ID.
- * @param[in]       handle : characteristic handle to prepare write.
- * @param[in]       offset : offset of the write value.
- * @param[in]       value_len: length of the value to be written.
- * @param[in]       value : the value to be written.
- * @param[in]       auth_req : authentication request.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_prepare_write(esp_gatt_if_t gattc_if,
-                                      uint16_t conn_id,
-                                      uint16_t handle,
-                                      uint16_t offset,
-                                      uint16_t value_len,
-                                      uint8_t *value,
-                                      esp_gatt_auth_req_t auth_req);
-
-
-/**
- * @brief           This function is called to prepare write a characteristic descriptor value.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id : connection ID.
- * @param[in]       handle : characteristic descriptor handle to prepare write.
- * @param[in]       offset : offset of the write value.
- * @param[in]       value_len: length of the value to be written.
- * @param[in]       value : the value to be written.
- * @param[in]       auth_req : authentication request.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_prepare_write_char_descr(esp_gatt_if_t gattc_if,
-                                                 uint16_t conn_id,
-                                                 uint16_t handle,
-                                                 uint16_t offset,
-                                                 uint16_t value_len,
-                                                 uint8_t *value,
-                                                 esp_gatt_auth_req_t auth_req);
-
-
-/**
- * @brief           This function is called to execute write a prepare write sequence.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       conn_id : connection ID.
- * @param[in]       is_execute : execute or cancel.
- *
- * @return
- *                  - ESP_OK: success
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_execute_write (esp_gatt_if_t gattc_if, uint16_t conn_id, bool is_execute);
-
-
-/**
- * @brief           This function is called to register for notification of a service.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       server_bda : target GATT server.
- * @param[in]       handle : GATT characteristic handle.
- *
- * @return
- *                  - ESP_OK: registration succeeds
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_register_for_notify (esp_gatt_if_t gattc_if,
-                                             esp_bd_addr_t server_bda,
-                                             uint16_t handle);
-
-
-/**
- * @brief           This function is called to de-register for notification of a service.
- *
- * @param[in]       gattc_if: Gatt client access interface.
- * @param[in]       server_bda : target GATT server.
- * @param[in]       handle : GATT characteristic handle.
- *
- * @return
- *                  - ESP_OK: unregister succeeds
- *                  - other: failed
- *
- */
-esp_err_t esp_ble_gattc_unregister_for_notify (esp_gatt_if_t gattc_if,
-                                               esp_bd_addr_t server_bda,
-                                               uint16_t handle);
-
-
-/**
-* @brief           Refresh the server cache store in the gattc stack of the remote device
-*
-* @param[in]       remote_bda: remote device BD address.
-*
-* @return
-*                  - ESP_OK: success
-*                  - other: failed
-*
-*/
-esp_err_t esp_ble_gattc_cache_refresh(esp_bd_addr_t remote_bda);
-
-/**
-* @brief           Add or delete the associated address with the source address.
-*                  Note: The role of this API is mainly when the client side has stored a server-side database, 
-*                        when it needs to connect another device, but the device's attribute database is the same 
-*                        as the server database stored on the client-side, calling this API can use the database 
-*                        that the device has stored used as the peer server database to reduce the attribute 
-*                        database search and discovery process and speed up the connection time.
-*                        The associated address mains that device want to used the database has stored in the local cache.
-*                        The source address mains that device want to share the database to the associated address device.
-*
-* @param[in]       gattc_if: Gatt client access interface.
-* @param[in]       src_addr: the source address which provide the attribute table.
-* @param[in]       assoc_addr: the associated device address which went to share the attribute table with the source address.
-* @param[in]       is_assoc: true add the associated device address, false remove the associated device address.
-* @return
-*                  - ESP_OK: success
-*                  - other: failed
-*
-*/
-esp_err_t esp_ble_gattc_cache_assoc(esp_gatt_if_t gattc_if, esp_bd_addr_t src_addr, 
-                                      esp_bd_addr_t assoc_addr, bool is_assoc);
-/**
-* @brief           Get the address list which has store the attribute table in the gattc cache. There will
-*                  callback ESP_GATTC_GET_ADDR_LIST_EVT event when get address list complete.
-*
-* @param[in]       gattc_if: Gatt client access interface.
-* @return
-*                  - ESP_OK: success
-*                  - other: failed
-*
-*/
-esp_err_t esp_ble_gattc_cache_get_addr_list(esp_gatt_if_t gattc_if);
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_GATTC_API_H__ */
diff --git a/tools/sdk/include/bt/esp_gatts_api.h b/tools/sdk/include/bt/esp_gatts_api.h
deleted file mode 100644
index 97296b1c7a8..00000000000
--- a/tools/sdk/include/bt/esp_gatts_api.h
+++ /dev/null
@@ -1,582 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_GATTS_API_H__
-#define __ESP_GATTS_API_H__
-
-#include "esp_bt_defs.h"
-#include "esp_gatt_defs.h"
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/// GATT Server callback function events
-typedef enum {
-    ESP_GATTS_REG_EVT                 = 0,       /*!< When register application id, the event comes */
-    ESP_GATTS_READ_EVT                = 1,       /*!< When gatt client request read operation, the event comes */
-    ESP_GATTS_WRITE_EVT               = 2,       /*!< When gatt client request write operation, the event comes */
-    ESP_GATTS_EXEC_WRITE_EVT          = 3,       /*!< When gatt client request execute write, the event comes */
-    ESP_GATTS_MTU_EVT                 = 4,       /*!< When set mtu complete, the event comes */
-    ESP_GATTS_CONF_EVT                = 5,       /*!< When receive confirm, the event comes */
-    ESP_GATTS_UNREG_EVT               = 6,       /*!< When unregister application id, the event comes */
-    ESP_GATTS_CREATE_EVT              = 7,       /*!< When create service complete, the event comes */
-    ESP_GATTS_ADD_INCL_SRVC_EVT       = 8,       /*!< When add included service complete, the event comes */
-    ESP_GATTS_ADD_CHAR_EVT            = 9,       /*!< When add characteristic complete, the event comes */
-    ESP_GATTS_ADD_CHAR_DESCR_EVT      = 10,      /*!< When add descriptor complete, the event comes */
-    ESP_GATTS_DELETE_EVT              = 11,      /*!< When delete service complete, the event comes */
-    ESP_GATTS_START_EVT               = 12,      /*!< When start service complete, the event comes */
-    ESP_GATTS_STOP_EVT                = 13,      /*!< When stop service complete, the event comes */
-    ESP_GATTS_CONNECT_EVT             = 14,      /*!< When gatt client connect, the event comes */
-    ESP_GATTS_DISCONNECT_EVT          = 15,      /*!< When gatt client disconnect, the event comes */
-    ESP_GATTS_OPEN_EVT                = 16,      /*!< When connect to peer, the event comes */
-    ESP_GATTS_CANCEL_OPEN_EVT         = 17,      /*!< When disconnect from peer, the event comes */
-    ESP_GATTS_CLOSE_EVT               = 18,      /*!< When gatt server close, the event comes */
-    ESP_GATTS_LISTEN_EVT              = 19,      /*!< When gatt listen to be connected the event comes */
-    ESP_GATTS_CONGEST_EVT             = 20,      /*!< When congest happen, the event comes */
-    /* following is extra event */
-    ESP_GATTS_RESPONSE_EVT            = 21,      /*!< When gatt send response complete, the event comes */
-    ESP_GATTS_CREAT_ATTR_TAB_EVT      = 22,      /*!< When gatt create table complete, the event comes */
-    ESP_GATTS_SET_ATTR_VAL_EVT        = 23,      /*!< When gatt set attr value complete, the event comes */
-    ESP_GATTS_SEND_SERVICE_CHANGE_EVT = 24,      /*!< When gatt send service change indication complete, the event comes */
-} esp_gatts_cb_event_t;
-
-/**
- * @brief Gatt server callback parameters union
- */
-typedef union {
-    /**
-     * @brief ESP_GATTS_REG_EVT
-     */
-    struct gatts_reg_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t app_id;                /*!< Application id which input in register API */
-    } reg;                              /*!< Gatt server callback param of ESP_GATTS_REG_EVT */
-
-    /**
-     * @brief ESP_GATTS_READ_EVT
-     */
-    struct gatts_read_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        uint32_t trans_id;              /*!< Transfer id */
-        esp_bd_addr_t bda;              /*!< The bluetooth device address which been read */
-        uint16_t handle;                /*!< The attribute handle */
-        uint16_t offset;                /*!< Offset of the value, if the value is too long */
-        bool is_long;                   /*!< The value is too long or not */
-        bool need_rsp;                  /*!< The read operation need to do response */
-    } read;                             /*!< Gatt server callback param of ESP_GATTS_READ_EVT */
-
-
-    /**
-     * @brief ESP_GATTS_WRITE_EVT
-     */
-    struct gatts_write_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        uint32_t trans_id;              /*!< Transfer id */
-        esp_bd_addr_t bda;              /*!< The bluetooth device address which been written */
-        uint16_t handle;                /*!< The attribute handle */
-        uint16_t offset;                /*!< Offset of the value, if the value is too long */
-        bool need_rsp;                  /*!< The write operation need to do response */
-        bool is_prep;                   /*!< This write operation is prepare write */
-        uint16_t len;                   /*!< The write attribute value length */
-        uint8_t *value;                 /*!< The write attribute value */
-    } write;                            /*!< Gatt server callback param of ESP_GATTS_WRITE_EVT */
-
-    /**
-     * @brief ESP_GATTS_EXEC_WRITE_EVT
-     */
-    struct gatts_exec_write_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        uint32_t trans_id;              /*!< Transfer id */
-        esp_bd_addr_t bda;              /*!< The bluetooth device address which been written */
-#define ESP_GATT_PREP_WRITE_CANCEL 0x00 /*!< Prepare write flag to indicate cancel prepare write */
-#define ESP_GATT_PREP_WRITE_EXEC   0x01 /*!< Prepare write flag to indicate execute prepare write */
-        uint8_t exec_write_flag;        /*!< Execute write flag */
-    } exec_write;                       /*!< Gatt server callback param of ESP_GATTS_EXEC_WRITE_EVT */
-
-    /**
-     * @brief ESP_GATTS_MTU_EVT
-     */
-    struct gatts_mtu_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        uint16_t mtu;                   /*!< MTU size */
-    } mtu;                              /*!< Gatt server callback param of ESP_GATTS_MTU_EVT */
-
-    /**
-     * @brief ESP_GATTS_CONF_EVT
-     */
-    struct gatts_conf_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t conn_id;               /*!< Connection id */
-        uint16_t handle;                /*!< attribute handle */
-        uint16_t len;                   /*!< The indication or notification value length, len is valid when send notification or indication failed */
-        uint8_t *value;                 /*!< The indication or notification value , value is valid when send notification or indication failed */
-    } conf;                             /*!< Gatt server callback param of ESP_GATTS_CONF_EVT (confirm) */
-
-    /**
-     * @brief ESP_GATTS_UNREG_EVT
-     */
-
-    /**
-     * @brief ESP_GATTS_CREATE_EVT
-     */
-    struct gatts_create_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t service_handle;        /*!< Service attribute handle */
-        esp_gatt_srvc_id_t service_id;  /*!< Service id, include service uuid and other information */
-    } create;                           /*!< Gatt server callback param of ESP_GATTS_CREATE_EVT */
-
-    /**
-     * @brief ESP_GATTS_ADD_INCL_SRVC_EVT
-     */
-    struct gatts_add_incl_srvc_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t attr_handle;           /*!< Included service attribute handle */
-        uint16_t service_handle;        /*!< Service attribute handle */
-    } add_incl_srvc;                    /*!< Gatt server callback param of ESP_GATTS_ADD_INCL_SRVC_EVT */
-
-    /**
-     * @brief ESP_GATTS_ADD_CHAR_EVT
-     */
-    struct gatts_add_char_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t attr_handle;           /*!< Characteristic attribute handle */
-        uint16_t service_handle;        /*!< Service attribute handle */
-        esp_bt_uuid_t char_uuid;        /*!< Characteristic uuid */
-    } add_char;                         /*!< Gatt server callback param of ESP_GATTS_ADD_CHAR_EVT */
-
-    /**
-     * @brief ESP_GATTS_ADD_CHAR_DESCR_EVT
-     */
-    struct gatts_add_char_descr_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t attr_handle;           /*!< Descriptor attribute handle */
-        uint16_t service_handle;        /*!< Service attribute handle */
-        esp_bt_uuid_t descr_uuid;       /*!< Characteristic descriptor uuid */
-    } add_char_descr;                   /*!< Gatt server callback param of ESP_GATTS_ADD_CHAR_DESCR_EVT */
-
-    /**
-     * @brief ESP_GATTS_DELETE_EVT
-     */
-    struct gatts_delete_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t service_handle;        /*!< Service attribute handle */
-    } del;                              /*!< Gatt server callback param of ESP_GATTS_DELETE_EVT */
-
-    /**
-     * @brief ESP_GATTS_START_EVT
-     */
-    struct gatts_start_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t service_handle;        /*!< Service attribute handle */
-    } start;                            /*!< Gatt server callback param of ESP_GATTS_START_EVT */
-
-    /**
-     * @brief ESP_GATTS_STOP_EVT
-     */
-    struct gatts_stop_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t service_handle;        /*!< Service attribute handle */
-    } stop;                             /*!< Gatt server callback param of ESP_GATTS_STOP_EVT */
-
-    /**
-     * @brief ESP_GATTS_CONNECT_EVT
-     */
-    struct gatts_connect_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        esp_bd_addr_t remote_bda;       /*!< Remote bluetooth device address */
-    } connect;                          /*!< Gatt server callback param of ESP_GATTS_CONNECT_EVT */
-
-    /**
-     * @brief ESP_GATTS_DISCONNECT_EVT
-     */
-    struct gatts_disconnect_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        esp_bd_addr_t remote_bda;       /*!< Remote bluetooth device address */
-        esp_gatt_conn_reason_t reason;  /*!< Indicate the reason of disconnection */
-    } disconnect;                       /*!< Gatt server callback param of ESP_GATTS_DISCONNECT_EVT */
-
-    /**
-     * @brief ESP_GATTS_OPEN_EVT
-     */
-    struct gatts_open_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-    } open;                             /*!< Gatt server callback param of ESP_GATTS_OPEN_EVT */
-
-    /**
-     * @brief ESP_GATTS_CANCEL_OPEN_EVT
-     */
-    struct gatts_cancel_open_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-    } cancel_open;                      /*!< Gatt server callback param of ESP_GATTS_CANCEL_OPEN_EVT */
-
-    /**
-     * @brief ESP_GATTS_CLOSE_EVT
-     */
-    struct gatts_close_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t conn_id;               /*!< Connection id */
-    } close;                            /*!< Gatt server callback param of ESP_GATTS_CLOSE_EVT */
-
-    /**
-     * @brief ESP_GATTS_LISTEN_EVT
-     */
-    /**
-     * @brief ESP_GATTS_CONGEST_EVT
-     */
-    struct gatts_congest_evt_param {
-        uint16_t conn_id;               /*!< Connection id */
-        bool congested;                 /*!< Congested or not */
-    } congest;                          /*!< Gatt server callback param of ESP_GATTS_CONGEST_EVT */
-
-    /**
-     * @brief ESP_GATTS_RESPONSE_EVT
-     */
-    struct gatts_rsp_evt_param {
-        esp_gatt_status_t status;       /*!< Operation status */
-        uint16_t handle;                /*!< Attribute handle which send response */
-    } rsp;                              /*!< Gatt server callback param of ESP_GATTS_RESPONSE_EVT */
-
-    /**
-     * @brief ESP_GATTS_CREAT_ATTR_TAB_EVT
-     */
-    struct gatts_add_attr_tab_evt_param{
-        esp_gatt_status_t status;       /*!< Operation status */
-        esp_bt_uuid_t svc_uuid;         /*!< Service uuid type */
-        uint16_t num_handle;            /*!< The number of the attribute handle to be added to the gatts database */
-        uint16_t *handles;              /*!< The number to the handles */
-    } add_attr_tab;                     /*!< Gatt server callback param of ESP_GATTS_CREAT_ATTR_TAB_EVT */
-
-
-   /**
-    * @brief ESP_GATTS_SET_ATTR_VAL_EVT
-    */
-    struct gatts_set_attr_val_evt_param{
-        uint16_t srvc_handle;           /*!< The service handle */
-        uint16_t attr_handle;           /*!< The attribute  handle */
-        esp_gatt_status_t status;       /*!< Operation status*/
-    } set_attr_val;                     /*!< Gatt server callback param of ESP_GATTS_SET_ATTR_VAL_EVT */
-
-    /**
-    * @brief ESP_GATTS_SEND_SERVICE_CHANGE_EVT
-    */
-    struct gatts_send_service_change_evt_param{
-        esp_gatt_status_t status;       /*!< Operation status*/
-    } service_change;                    /*!< Gatt server callback param of ESP_GATTS_SEND_SERVICE_CHANGE_EVT */
-
-} esp_ble_gatts_cb_param_t;
-
-/**
- * @brief GATT Server callback function type
- * @param event : Event type
- * @param gatts_if : GATT server access interface, normally
- *                   different gatts_if correspond to different profile
- * @param param : Point to callback parameter, currently is union type
- */
-typedef void (* esp_gatts_cb_t)(esp_gatts_cb_event_t event, esp_gatt_if_t gatts_if, esp_ble_gatts_cb_param_t *param);
-
-/**
- * @brief           This function is called to register application callbacks
- *                  with BTA GATTS module.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_register_callback(esp_gatts_cb_t callback);
-
-/**
- * @brief           This function is called to register application identifier
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_app_register(uint16_t app_id);
-
-
-
-/**
- * @brief           unregister with GATT Server.
- *
- * @param[in]       gatts_if: GATT server access interface
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_app_unregister(esp_gatt_if_t gatts_if);
-
-
-/**
- * @brief           Create a service. When service creation is done, a callback
- *                  event BTA_GATTS_CREATE_SRVC_EVT is called to report status
- *                  and service ID to the profile. The service ID obtained in
- *                  the callback function needs to be used when adding included
- *                  service and characteristics/descriptors into the service.
- *
- * @param[in]       gatts_if: GATT server access interface
- * @param[in]       service_id: service ID.
- * @param[in]       num_handle: number of handle requested for this service.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_create_service(esp_gatt_if_t gatts_if,
-                                       esp_gatt_srvc_id_t *service_id, uint16_t num_handle);
-
-
-/**
- * @brief               Create a service attribute tab. 
- * @param[in]       gatts_attr_db: the pointer to the service attr tab
- * @param[in]       gatts_if: GATT server access interface
- * @param[in]       max_nb_attr: the number of attribute to be added to the service database.
- * @param[in]       srvc_inst_id: the instance id of the service
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_create_attr_tab(const esp_gatts_attr_db_t *gatts_attr_db, 
-                                            esp_gatt_if_t gatts_if,
-                                            uint8_t max_nb_attr,
-                                            uint8_t srvc_inst_id);
-/**
- * @brief           This function is called to add an included service. This function have to be called between 
- *                  'esp_ble_gatts_create_service' and 'esp_ble_gatts_add_char'.  After included
- *                  service is included, a callback event BTA_GATTS_ADD_INCL_SRVC_EVT
- *                  is reported the included service ID.
- *
- * @param[in]       service_handle: service handle to which this included service is to
- *                  be added.
- * @param[in]       included_service_handle: the service ID to be included.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_add_included_service(uint16_t service_handle, uint16_t included_service_handle);
-
-
-
-/**
- * @brief           This function is called to add a characteristic into a service.
- *
- * @param[in]       service_handle: service handle to which this included service is to
- *                  be added.
- * @param[in]       char_uuid : Characteristic UUID.
- * @param[in]       perm      : Characteristic value declaration attribute permission.
- * @param[in]       property  : Characteristic Properties
- * @param[in]       char_val    : Characteristic value 
- * @param[in]       control : attribute response control byte
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_add_char(uint16_t service_handle,  esp_bt_uuid_t  *char_uuid,
-                                 esp_gatt_perm_t perm, esp_gatt_char_prop_t property, esp_attr_value_t *char_val,
-                                 esp_attr_control_t *control);
-
-
-/**
- * @brief           This function is called to add characteristic descriptor. When
- *                  it's done, a callback event BTA_GATTS_ADD_DESCR_EVT is called
- *                  to report the status and an ID number for this descriptor.
- *
- * @param[in]       service_handle: service handle to which this characteristic descriptor is to
- *                              be added.
- * @param[in]       perm: descriptor access permission.
- * @param[in]       descr_uuid: descriptor UUID.
- * @param[in]       char_descr_val  : Characteristic descriptor value 
- * @param[in]       control : attribute response control byte
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_add_char_descr (uint16_t service_handle,
-                                        esp_bt_uuid_t   *descr_uuid,
-                                        esp_gatt_perm_t perm, esp_attr_value_t *char_descr_val,
-                                        esp_attr_control_t *control);
-
-
-
-/**
- * @brief           This function is called to delete a service. When this is done,
- *                  a callback event BTA_GATTS_DELETE_EVT is report with the status.
- *
- * @param[in]       service_handle: service_handle to be deleted.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_delete_service(uint16_t service_handle);
-
-
-
-/**
- * @brief           This function is called to start a service.
- *
- * @param[in]       service_handle: the service handle to be started.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_start_service(uint16_t service_handle);
-
-
-
-/**
- * @brief           This function is called to stop a service.
- *
- * @param[in]       service_handle - service to be topped.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_stop_service(uint16_t service_handle);
-
-
-
-/**
- * @brief           Send indicate or notify to GATT client.
- *                  Set param need_confirm as false will send notification, otherwise indication.
- *
- * @param[in]       gatts_if: GATT server access interface
- * @param[in]       conn_id - connection id to indicate.
- * @param[in]       attr_handle - attribute handle to indicate.
- * @param[in]       value_len - indicate value length.
- * @param[in]       value: value to indicate.
- * @param[in]       need_confirm - Whether a confirmation is required.
- *                  false sends a GATT notification, true sends a GATT indication.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_send_indicate(esp_gatt_if_t gatts_if, uint16_t conn_id, uint16_t attr_handle,
-                                      uint16_t value_len, uint8_t *value, bool need_confirm);
-
-
-/**
- * @brief           This function is called to send a response to a request.
- *
- * @param[in]       gatts_if: GATT server access interface
- * @param[in]       conn_id - connection identifier.
- * @param[in]       trans_id - transfer id
- * @param[in]       status - response status
- * @param[in]       rsp - response data.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_send_response(esp_gatt_if_t gatts_if, uint16_t conn_id, uint32_t trans_id,
-                                      esp_gatt_status_t status, esp_gatt_rsp_t *rsp);
-
-
-/**
- * @brief           This function is called to set the attribute value by the application
- *
- * @param[in]       attr_handle: the attribute handle which to be set
- * @param[in]       length: the value length
- * @param[in]       value: the pointer to the attribute value
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_set_attr_value(uint16_t attr_handle, uint16_t length, const uint8_t *value);
-
-/**
- * @brief       Retrieve attribute value
- *
- * @param[in]   attr_handle: Attribute handle.
- * @param[out]  length: pointer to the attribute value length
- * @param[out]  value:  Pointer to attribute value payload, the value cannot be modified by user
- *
- * @return
- *                  - ESP_GATT_OK : success
- *                  - other  : failed
- *
- */
-esp_gatt_status_t esp_ble_gatts_get_attr_value(uint16_t attr_handle, uint16_t *length, const uint8_t **value);
-
-
-/**
- * @brief           Open a direct open connection or add a background auto connection
- *
- * @param[in]       gatts_if: GATT server access interface
- * @param[in]       remote_bda: remote device bluetooth device address.
- * @param[in]       is_direct: direct connection or background auto connection
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_open(esp_gatt_if_t gatts_if, esp_bd_addr_t remote_bda, bool is_direct);
-
-/**
- * @brief           Close a connection  a remote device.
- *
- * @param[in]       gatts_if: GATT server access interface
- * @param[in]       conn_id: connection ID to be closed.
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_close(esp_gatt_if_t gatts_if, uint16_t conn_id);
-
-/**
- * @brief           Send service change indication
- *
- * @param[in]       gatts_if: GATT server access interface
- * @param[in]       remote_bda: remote device bluetooth device address.
- *                  If remote_bda is NULL then it will send service change
- *                  indication to all the connected devices and if not then
- *                  to a specific device
- *
- * @return
- *                  - ESP_OK : success
- *                  - other  : failed
- *
- */
-esp_err_t esp_ble_gatts_send_service_change_indication(esp_gatt_if_t gatts_if, esp_bd_addr_t remote_bda);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_GATTS_API_H__ */
diff --git a/tools/sdk/include/bt/esp_hf_client_api.h b/tools/sdk/include/bt/esp_hf_client_api.h
deleted file mode 100644
index dfc06ed5d1c..00000000000
--- a/tools/sdk/include/bt/esp_hf_client_api.h
+++ /dev/null
@@ -1,635 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_HF_CLIENT_API_H__
-#define __ESP_HF_CLIENT_API_H__
-
-#include "esp_err.h"
-#include "esp_bt_defs.h"
-#include "esp_hf_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ESP_BT_HF_CLIENT_NUMBER_LEN           (32)
-#define ESP_BT_HF_CLIENT_OPERATOR_NAME_LEN    (16)
-
-/// Bluetooth HFP RFCOMM connection and service level connection status
-typedef enum {
-    ESP_HF_CLIENT_CONNECTION_STATE_DISCONNECTED = 0,     /*!< RFCOMM data link channel released */
-    ESP_HF_CLIENT_CONNECTION_STATE_CONNECTING,           /*!< connecting remote device on the RFCOMM data link*/
-    ESP_HF_CLIENT_CONNECTION_STATE_CONNECTED,            /*!< RFCOMM connection established */
-    ESP_HF_CLIENT_CONNECTION_STATE_SLC_CONNECTED,        /*!< service level connection established */
-    ESP_HF_CLIENT_CONNECTION_STATE_DISCONNECTING,        /*!< disconnecting with remote device on the RFCOMM dat link*/
-} esp_hf_client_connection_state_t;
-
-/// Bluetooth HFP audio connection status
-typedef enum {
-    ESP_HF_CLIENT_AUDIO_STATE_DISCONNECTED = 0,          /*!< audio connection released */
-    ESP_HF_CLIENT_AUDIO_STATE_CONNECTING,                /*!< audio connection has been initiated */
-    ESP_HF_CLIENT_AUDIO_STATE_CONNECTED,                 /*!< audio connection is established */
-    ESP_HF_CLIENT_AUDIO_STATE_CONNECTED_MSBC,            /*!< mSBC audio connection is established */
-} esp_hf_client_audio_state_t;
-
-/// in-band ring tone state
-typedef enum {
-    ESP_HF_CLIENT_IN_BAND_RINGTONE_NOT_PROVIDED = 0,
-    ESP_HF_CLIENT_IN_BAND_RINGTONE_PROVIDED,
-} esp_hf_client_in_band_ring_state_t;
-
-/* features masks of AG */
-#define ESP_HF_CLIENT_PEER_FEAT_3WAY       0x01        /* Three-way calling */
-#define ESP_HF_CLIENT_PEER_FEAT_ECNR       0x02        /* Echo cancellation and/or noise reduction */
-#define ESP_HF_CLIENT_PEER_FEAT_VREC       0x04        /* Voice recognition */
-#define ESP_HF_CLIENT_PEER_FEAT_INBAND     0x08        /* In-band ring tone */
-#define ESP_HF_CLIENT_PEER_FEAT_VTAG       0x10        /* Attach a phone number to a voice tag */
-#define ESP_HF_CLIENT_PEER_FEAT_REJECT     0x20        /* Ability to reject incoming call */
-#define ESP_HF_CLIENT_PEER_FEAT_ECS        0x40        /* Enhanced Call Status */
-#define ESP_HF_CLIENT_PEER_FEAT_ECC        0x80        /* Enhanced Call Control */
-#define ESP_HF_CLIENT_PEER_FEAT_EXTERR    0x100        /* Extended error codes */
-#define ESP_HF_CLIENT_PEER_FEAT_CODEC     0x200        /* Codec Negotiation */
-
-/* CHLD feature masks of AG */
-#define ESP_HF_CLIENT_CHLD_FEAT_REL           0x01       /* 0  Release waiting call or held calls */
-#define ESP_HF_CLIENT_CHLD_FEAT_REL_ACC       0x02       /* 1  Release active calls and accept other waiting or held call */
-#define ESP_HF_CLIENT_CHLD_FEAT_REL_X         0x04       /* 1x Release specified active call only */
-#define ESP_HF_CLIENT_CHLD_FEAT_HOLD_ACC      0x08       /* 2  Active calls on hold and accept other waiting or held call */
-#define ESP_HF_CLIENT_CHLD_FEAT_PRIV_X        0x10       /* 2x Request private mode with specified call(put the rest on hold) */
-#define ESP_HF_CLIENT_CHLD_FEAT_MERGE         0x20       /* 3  Add held call to multiparty */
-#define ESP_HF_CLIENT_CHLD_FEAT_MERGE_DETACH  0x40       /* 4  Connect two calls and leave(disconnect from multiparty) */
-
-/// HF CLIENT callback events
-typedef enum {
-    ESP_HF_CLIENT_CONNECTION_STATE_EVT = 0,          /*!< connection state changed event */
-    ESP_HF_CLIENT_AUDIO_STATE_EVT,                   /*!< audio connection state change event */
-    ESP_HF_CLIENT_BVRA_EVT,                          /*!< voice recognition state change event */
-    ESP_HF_CLIENT_CIND_CALL_EVT,                     /*!< call indication */
-    ESP_HF_CLIENT_CIND_CALL_SETUP_EVT,               /*!< call setup indication */
-    ESP_HF_CLIENT_CIND_CALL_HELD_EVT,                /*!< call held indication */
-    ESP_HF_CLIENT_CIND_SERVICE_AVAILABILITY_EVT,     /*!< network service availability indication */
-    ESP_HF_CLIENT_CIND_SIGNAL_STRENGTH_EVT,          /*!< signal strength indication */
-    ESP_HF_CLIENT_CIND_ROAMING_STATUS_EVT,           /*!< roaming status indication */
-    ESP_HF_CLIENT_CIND_BATTERY_LEVEL_EVT,            /*!< battery level indication */
-    ESP_HF_CLIENT_COPS_CURRENT_OPERATOR_EVT,         /*!< current operator information */
-    ESP_HF_CLIENT_BTRH_EVT,                          /*!< call response and hold event */
-    ESP_HF_CLIENT_CLIP_EVT,                          /*!< Calling Line Identification notification */
-    ESP_HF_CLIENT_CCWA_EVT,                          /*!< call waiting notification */
-    ESP_HF_CLIENT_CLCC_EVT,                          /*!< list of current calls notification */
-    ESP_HF_CLIENT_VOLUME_CONTROL_EVT,                /*!< audio volume control command from AG, provided by +VGM or +VGS message */
-    ESP_HF_CLIENT_AT_RESPONSE_EVT,                   /*!< AT command response event */
-    ESP_HF_CLIENT_CNUM_EVT,                          /*!< subscriber information response from AG */
-    ESP_HF_CLIENT_BSIR_EVT,                          /*!< setting of in-band ring tone */
-    ESP_HF_CLIENT_BINP_EVT,                          /*!< requested number of last voice tag from AG */
-    ESP_HF_CLIENT_RING_IND_EVT,                      /*!< ring indication event */
-} esp_hf_client_cb_event_t;
-
-/// HFP client callback parameters
-typedef union {
-    /**
-     * @brief  ESP_HF_CLIENT_CONNECTION_STATE_EVT
-     */
-    struct hf_client_conn_stat_param {
-        esp_hf_client_connection_state_t state;   /*!< HF connection state */
-        uint32_t peer_feat;                       /*!< AG supported features */
-        uint32_t chld_feat;                       /*!< AG supported features on call hold and multiparty services */
-        esp_bd_addr_t remote_bda;                 /*!< remote bluetooth device address */
-    } conn_stat;                                  /*!< HF callback param of ESP_HF_CLIENT_CONNECTION_STATE_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_AUDIO_STATE_EVT
-     */
-    struct hf_client_audio_stat_param {
-        esp_hf_client_audio_state_t state;        /*!< audio connection state */
-        esp_bd_addr_t remote_bda;                 /*!< remote bluetooth device address */
-    } audio_stat;                                 /*!< HF callback param of ESP_HF_CLIENT_AUDIO_STATE_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_BVRA_EVT
-     */
-    struct hf_client_bvra_param {
-        esp_hf_vr_state_t value;                  /*!< voice recognition state */
-    } bvra;                                       /*!< HF callback param of ESP_HF_CLIENT_BVRA_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CIND_SERVICE_AVAILABILITY_EVT
-     */
-    struct hf_client_service_availability_param {
-        esp_hf_service_availability_status_t status;     /*!< service availability status */
-    } service_availability;                              /*!< HF callback param of ESP_HF_CLIENT_CIND_SERVICE_AVAILABILITY_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CIND_ROAMING_STATUS_EVT
-     */
-    struct hf_client_network_roaming_param {
-        esp_hf_roaming_status_t status;          /*!< roaming status */
-    } roaming;                                   /*!< HF callback param of ESP_HF_CLIENT_CIND_ROAMING_STATUS_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CIND_SIGNAL_STRENGTH_EVT
-     */
-    struct hf_client_signal_strength_ind_param {
-        int value;                               /*!< signal strength value, ranges from 0 to 5 */
-    } signal_strength;                           /*!< HF callback param of ESP_HF_CLIENT_CIND_SIGNAL_STRENGTH_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CIND_BATTERY_LEVEL_EVT
-     */
-    struct hf_client_battery_level_ind_param {
-        int value;                               /*!< battery charge value, ranges from 0 to 5 */
-    } battery_level;                             /*!< HF callback param of ESP_HF_CLIENT_CIND_BATTERY_LEVEL_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_COPS_CURRENT_OPERATOR_EVT
-     */
-    struct hf_client_current_operator_param {
-        const char *name;                        /*!< name of the network operator */
-    } cops;                                      /*!< HF callback param of ESP_HF_CLIENT_COPS_CURRENT_OPERATOR_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CIND_CALL_EVT
-     */
-    struct hf_client_call_ind_param {
-        esp_hf_call_status_t status;             /*!< call status indicator */
-    } call;                                      /*!< HF callback param of ESP_HF_CLIENT_CIND_CALL_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CIND_CALL_SETUP_EVT
-     */
-    struct hf_client_call_setup_ind_param {
-        esp_hf_call_setup_status_t status;       /*!< call setup status indicator */
-    } call_setup;                                /*!< HF callback param of ESP_HF_CLIENT_BVRA_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CIND_CALL_HELD_EVT
-     */
-    struct hf_client_call_held_ind_param {
-        esp_hf_call_held_status_t status;        /*!< bluetooth proprietary call hold status indicator */
-    } call_held;                                 /*!< HF callback param of ESP_HF_CLIENT_CIND_CALL_HELD_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_BTRH_EVT
-     */
-    struct hf_client_btrh_param {
-        esp_hf_btrh_status_t status;             /*!< call hold and response status result code */
-    } btrh;                                      /*!< HF callback param of ESP_HF_CLIENT_BRTH_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CLIP_EVT
-     */
-    struct hf_client_clip_param {
-        const char *number;                      /*!< phone number string of call */
-    } clip;                                      /*!< HF callback param of ESP_HF_CLIENT_CLIP_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CCWA_EVT
-     */
-    struct hf_client_ccwa_param {
-        const char *number;                      /*!< phone number string of waiting call */
-    } ccwa;                                      /*!< HF callback param of ESP_HF_CLIENT_BVRA_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CLCC_EVT
-     */
-    struct hf_client_clcc_param {
-        int idx;                                 /*!< numbering(starting with 1) of the call */
-        esp_hf_current_call_direction_t dir;     /*!< direction of the call */
-        esp_hf_current_call_status_t status;     /*!< status of the call */
-        esp_hf_current_call_mpty_type_t mpty;    /*!< multi-party flag */
-        char *number;                            /*!< phone number(optional) */
-    } clcc;                                      /*!< HF callback param of ESP_HF_CLIENT_CLCC_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_VOLUME_CONTROL_EVT
-     */
-    struct hf_client_volume_control_param {
-        esp_hf_volume_control_target_t type;     /*!< volume control target, speaker or microphone */
-        int volume;                              /*!< gain, ranges from 0 to 15 */
-    } volume_control;                            /*!< HF callback param of ESP_HF_CLIENT_VOLUME_CONTROL_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_AT_RESPONSE_EVT
-     */
-    struct hf_client_at_response_param {
-        esp_hf_at_response_code_t code;          /*!< AT response code */
-        esp_hf_cme_err_t cme;                    /*!< Extended Audio Gateway Error Result Code */
-    } at_response;                               /*!< HF callback param of ESP_HF_CLIENT_AT_RESPONSE_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_CNUM_EVT
-     */
-    struct hf_client_cnum_param {
-        const char *number;                      /*!< phone number string */
-        esp_hf_subscriber_service_type_t type;   /*!< service type that the phone number relates to */
-    } cnum;                                      /*!< HF callback param of ESP_HF_CLIENT_CNUM_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_BSIR_EVT
-     */
-    struct hf_client_bsirparam {
-        esp_hf_client_in_band_ring_state_t state;  /*!< setting state of in-band ring tone */
-    } bsir;                                        /*!< HF callback param of ESP_HF_CLIENT_BSIR_EVT */
-
-    /**
-     * @brief ESP_HF_CLIENT_BINP_EVT
-     */
-    struct hf_client_binp_param {
-        const char *number;                      /*!< phone number corresponding to the last voice tag in the HF */
-    } binp;                                      /*!< HF callback param of ESP_HF_CLIENT_BINP_EVT */
-
-} esp_hf_client_cb_param_t;
-
-/**
- * @brief           HFP client incoming data callback function, the callback is useful in case of
- *                  Voice Over HCI.
- * @param[in]       buf : pointer to incoming data(payload of HCI synchronous data packet), the
- *                  buffer is allocated inside bluetooth protocol stack and will be released after
- *                  invoke of the callback is finished.
- * @param[in]       len : size(in bytes) in buf
- */
-typedef void (* esp_hf_client_incoming_data_cb_t)(const uint8_t *buf, uint32_t len);
-
-/**
- * @brief           HFP client outgoing data callback function, the callback is useful in case of
- *                  Voice Over HCI. Once audio connection is set up and the application layer has
- *                  prepared data to send, the lower layer will call this function to read data
- *                  and then send. This callback is supposed to be implemented as non-blocking,
- *                  and if data is not enough, return value 0 is supposed.
- *
- * @param[in]       buf : pointer to incoming data(payload of HCI synchronous data packet), the
- *                  buffer is allocated inside bluetooth protocol stack and will be released after
- *                  invoke of the callback is finished.
- * @param[in]       len : size(in bytes) in buf
- * @param[out]      length of data successfully read
- */
-typedef uint32_t (* esp_hf_client_outgoing_data_cb_t)(uint8_t *buf, uint32_t len);
-
-/**
- * @brief           HFP client callback function type
- *
- * @param           event : Event type
- *
- * @param           param : Pointer to callback parameter
- */
-typedef void (* esp_hf_client_cb_t)(esp_hf_client_cb_event_t event, esp_hf_client_cb_param_t *param);
-
-/**
- * @brief           Register application callback function to HFP client module. This function should be called
- *                  only after esp_bluedroid_enable() completes successfully, used by HFP client
- *
- * @param[in]       callback: HFP client event callback function
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: if callback is a NULL function pointer
- *
- */
-esp_err_t esp_hf_client_register_callback(esp_hf_client_cb_t callback);
-
-/**
- *
- * @brief           Initialize the bluetooth HFP client module. This function should be called
- *                  after esp_bluedroid_enable() completes successfully
- *
- * @return
- *                  - ESP_OK: if the initialization request is sent successfully
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_init(void);
-
-/**
- *
- * @brief           De-initialize for HFP client module. This function
- *                  should be called only after esp_bluedroid_enable() completes successfully
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_deinit(void);
-
-/**
- *
- * @brief           Connect to remote bluetooth HFP audio gateway(AG) device, must after esp_hf_client_init()
- *
- * @param[in]       remote_bda: remote bluetooth device address
- *
- * @return
- *                  - ESP_OK: connect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_connect(esp_bd_addr_t remote_bda);
-
-/**
- *
- * @brief           Disconnect from the remote HFP audio gateway
- *
- * @param[in]       remote_bda: remote bluetooth device address
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_disconnect(esp_bd_addr_t remote_bda);
-
-/**
- *
- * @brief           Create audio connection with remote HFP AG. As a precondition to use this API,
- *                  Service Level Connection shall exist with AG
- *
- * @param[in]       remote_bda: remote bluetooth device address
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_connect_audio(esp_bd_addr_t remote_bda);
-
-/**
- *
- * @brief           Release the established audio connection with remote HFP AG.
- *
- * @param[in]       remote_bda: remote bluetooth device address
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_disconnect_audio(esp_bd_addr_t remote_bda);
-
-/**
- *
- * @brief           Enable voice recognition in the AG. As a precondition to use this API,
- *                  Service Level Connection shall exist with AG
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_start_voice_recognition(void);
-
-/**
- *
- * @brief           Disable voice recognition in the AG. As a precondition to use this API,
- *                  Service Level Connection shall exist with AG
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_stop_voice_recognition(void);
-
-/**
- *
- * @brief           Volume synchronization with AG. As a precondition to use this API,
- *                  Service Level Connection shall exist with AG
- *
- * @param[in]       type: volume control target, speaker or microphone
- * @param[in]       volume: gain of the speaker of microphone, ranges 0 to 15
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_volume_update(esp_hf_volume_control_target_t type, int volume);
-
-/**
- *
- * @brief           Place a call with a specified number, if number is NULL, last called number is
- *                  called.  As a precondition to use this API, Service Level Connection shall
- *                  exist with AG
- *
- * @param[in]       number: number string of the call. If NULL, the last number is called(aka re-dial)
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_dial(const char *number);
-
-/**
- *
- * @brief           Place a call with number specified by location(speed dial). As a precondition,
- *                  to use this API, Service Level Connection shall exist with AG
- *
- * @param[in]       location: location of the number in the memory
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-
-esp_err_t esp_hf_client_dial_memory(int location);
-
-/**
- *
- * @brief           Send call hold and multiparty commands, or enhanced call control commands(Use AT+CHLD).
- *                  As a precondition to use this API, Service Level Connection shall exist with AG
- *
- * @param[in]       chld: AT+CHLD call hold and multiparty handling AT command.
- * @param[in]       idx: used in Enhanced Call Control Mechanisms, used if chld is
- *                       ESP_HF_CHLD_TYPE_REL_X or ESP_HF_CHLD_TYPE_PRIV_X
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_send_chld_cmd(esp_hf_chld_type_t chld, int idx);
-
-/**
- *
- * @brief           Send response and hold action command(Send AT+BTRH command)
- *                  As a precondition to use this API, Service Level Connection shall exist with AG
- *
- * @param[in]       btrh: response and hold action to send
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_send_btrh_cmd(esp_hf_btrh_cmd_t btrh);
-
-/**
- *
- * @brief           Answer an incoming call(send ATA command). As a precondition to use this API,
- *                  Service Level Connection shall exist with AG
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_answer_call(void);
-
-/**
- *
- * @brief           Reject an incoming call(send AT+CHUP command), As a precondition to use this API,
- *                  Service Level Connection shall exist with AG
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_reject_call(void);
-
-/**
- *
- * @brief           Query list of current calls in AG(send AT+CLCC command), As a precondition to use this API,
- *                  Service Level Connection shall exist with AG
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_query_current_calls(void);
-
-/**
- *
- * @brief           Query the name of currently selected network operator in AG(use AT+COPS commands)
- *                  As a precondition to use this API, Service Level Connection shall exist with AG
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_query_current_operator_name(void);
-
-/**
- *
- * @brief           Get subscriber information number from AG(send AT+CNUM command)
- *                  As a precondition to use this API, Service Level Connection shall exist with AG
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_retrieve_subscriber_info(void);
-
-/**
- *
- * @brief           Transmit DTMF codes during an ongoing call(use AT+VTS commands)
- *                  As a precondition to use this API, Service Level Connection shall exist with AG
- *
- * @param[in]       code: dtmf code, single ascii character in the set 0-9, #, *, A-D
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_send_dtmf(char code);
-
-/**
- *
- * @brief           Request a phone number from AG corresponding to last voice tag recorded
- *                  (send AT+BINP command). As a precondition to use this API, Service Level
- *                  Connection shall exist with AG
- *
- * @return
- *                  - ESP_OK: disconnect request is sent to lower layer
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: others
- *
- */
-esp_err_t esp_hf_client_request_last_voice_tag_number(void);
-
-/**
- * @brief           Register HFP client data output function; the callback is only used in
- *                  the case that Voice Over HCI is enabled.
- *
- * @param[in]       recv: HFP client incoming data callback function
- * @param[in]       send: HFP client outgoing data callback function
- *
- * @return
- *                  - ESP_OK: success
- *                  - ESP_INVALID_STATE: if bluetooth stack is not yet enabled
- *                  - ESP_FAIL: if callback is a NULL function pointer
- *
- */
-esp_err_t esp_hf_client_register_data_callback(esp_hf_client_incoming_data_cb_t recv,
-                                               esp_hf_client_outgoing_data_cb_t send);
-
-/**
- * @brief           Trigger the lower-layer to fetch and send audio data. This function is only
- *                  only used in the case that Voice Over HCI is enabled. Precondition is that
- *                  the HFP audio connection is connected. After this function is called, lower
- *                  layer will invoke esp_hf_client_outgoing_data_cb_t to fetch data
- *
- */
-void esp_hf_client_outgoing_data_ready(void);
-
-
-/**
- * @brief           Initialize the down sampling converter. This is a utility function that can
- *                  only be used in the case that Voice Over HCI is enabled.
- *
- * @param[in]       src_sps: original samples per second(source audio data, i.e. 48000, 32000,
- *                  16000, 44100, 22050, 11025)
- * @param[in]       bits: number of bits per pcm sample (16)
- * @param[in]       channels: number of channels (i.e. mono(1), stereo(2)...)
- */
-void esp_hf_client_pcm_resample_init(uint32_t src_sps, uint32_t bits, uint32_t channels);
-
-/**
- * @brief           Down sampling utility to convert high sampling rate into 8K/16bits 1-channel mode PCM
- *                  samples. This can only be used in the case that Voice Over HCI is enabled.
- *
- * @param[in]       src: pointer to the buffer where the original sampling PCM are stored
- * @param[in]       in_bytes: length of the input PCM sample buffer in byte
- * @param[in]       dst: pointer to the buffer which is to be used to store the converted PCM samples
- *
- * @return          number of samples converted
- */
-int32_t esp_hf_client_pcm_resample(void *src, uint32_t in_bytes, void *dst);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __ESP_HF_CLIENT_API_H__ */
diff --git a/tools/sdk/include/bt/esp_hf_defs.h b/tools/sdk/include/bt/esp_hf_defs.h
deleted file mode 100644
index 1ff9f14f6e7..00000000000
--- a/tools/sdk/include/bt/esp_hf_defs.h
+++ /dev/null
@@ -1,181 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_HF_DEFS_H__
-#define __ESP_HF_DEFS_H__
-
-#include "esp_bt_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/// Bluetooth HFP audio volume control target
-typedef enum {
-    ESP_HF_VOLUME_CONTROL_TARGET_SPK = 0,             /*!< speaker */
-    ESP_HF_VOLUME_CONTROL_TARGET_MIC,                 /*!< microphone */
-} esp_hf_volume_control_target_t;
-
-/// +CIND roaming status indicator values
-typedef enum {
-    ESP_HF_ROAMING_STATUS_INACTIVE = 0,               /*!< roaming is not active */
-    ESP_HF_ROAMING_STATUS_ACTIVE,                     /*!< a roaming is active */
-} esp_hf_roaming_status_t;
-
-/// +CIND call status indicator values
-typedef enum {
-    ESP_HF_CALL_STATUS_NO_CALLS = 0,                  /*!< no call in progress  */
-    ESP_HF_CALL_STATUS_CALL_IN_PROGRESS = 1,          /*!< call is present(active or held) */
-} esp_hf_call_status_t;
-
-/// +CIND call setup status indicator values
-typedef enum {
-    ESP_HF_CALL_SETUP_STATUS_NONE = 0,                /*!< no call setup in progress */
-    ESP_HF_CALL_SETUP_STATUS_INCOMING = 1,            /*!< incoming call setup in progress */
-    ESP_HF_CALL_SETUP_STATUS_OUTGOING_DIALING = 2,    /*!< outgoing call setup in dialing state */
-    ESP_HF_CALL_SETUP_STATUS_OUTGOING_ALERTING = 3,   /*!< outgoing call setup in alerting state */
-} esp_hf_call_setup_status_t;
-
-/// +CIND call held indicator values
-typedef enum {
-    ESP_HF_CALL_HELD_STATUS_NONE = 0,                 /*!< no calls held */
-    ESP_HF_CALL_HELD_STATUS_HELD_AND_ACTIVE = 1,      /*!< both active and held call */
-    ESP_HF_CALL_HELD_STATUS_HELD = 2,                 /*!< call on hold, no active call*/
-} esp_hf_call_held_status_t;
-
-/// +CIND network service availability status
-typedef enum {
-    ESP_HF_SERVICE_AVAILABILITY_STATUS_UNAVAILABLE = 0, /*!< service not available */
-    ESP_HF_SERVICE_AVAILABILITY_STATUS_AVAILABLE,       /*!< service available */
-} esp_hf_service_availability_status_t;
-
-/// +CLCC status of the call
-typedef enum {
-    ESP_HF_CURRENT_CALL_STATUS_ACTIVE = 0,            /*!< active */
-    ESP_HF_CURRENT_CALL_STATUS_HELD = 1,              /*!< held */
-    ESP_HF_CURRENT_CALL_STATUS_DIALING = 2,           /*!< dialing (outgoing calls only) */
-    ESP_HF_CURRENT_CALL_STATUS_ALERTING = 3,          /*!< alerting (outgoing calls only) */
-    ESP_HF_CURRENT_CALL_STATUS_INCOMING = 4,          /*!< incoming (incoming calls only) */
-    ESP_HF_CURRENT_CALL_STATUS_WAITING = 5,           /*!< waiting (incoming calls only) */
-    ESP_HF_CURRENT_CALL_STATUS_HELD_BY_RESP_HOLD = 6, /*!< call held by response and hold */
-} esp_hf_current_call_status_t;
-
-/// +CLCC direction of the call
-typedef enum {
-    ESP_HF_CURRENT_CALL_DIRECTION_OUTGOING = 0,       /*!< outgoing */
-    ESP_HF_CURRENT_CALL_DIRECTION_INCOMING = 1,       /*!< incoming */
-} esp_hf_current_call_direction_t;
-
-/// +CLCC multi-party call flag
-typedef enum {
-    ESP_HF_CURRENT_CALL_MPTY_TYPE_SINGLE = 0,         /*!< not a member of a multi-party call */
-    ESP_HF_CURRENT_CALL_MPTY_TYPE_MULTI = 1,          /*!< member of a multi-party call */
-} esp_hf_current_call_mpty_type_t;
-
-/// +CLCC call mode
-typedef enum {
-    ESP_HF_CURRENT_CALL_MODE_VOICE = 0,
-    ESP_HF_CURRENT_CALL_MODE_DATA = 1,
-    ESP_HF_CURRENT_CALL_MODE_FAX = 2,
-} esp_hf_current_call_mode_t;
-
-/// +CLCC address type
-typedef enum {
-    ESP_HF_CALL_ADDR_TYPE_UNKNOWN = 0x81,            /*!< unkown address type */
-    ESP_HF_CALL_ADDR_TYPE_INTERNATIONAL = 0x91,      /*!< international address */
-} esp_hf_call_addr_type_t;
-
-/// +CNUM service type of the phone number
-typedef enum {
-    ESP_HF_SUBSCRIBER_SERVICE_TYPE_UNKNOWN = 0,      /*!< unknown */
-    ESP_HF_SUBSCRIBER_SERVICE_TYPE_VOICE,            /*!< voice service */
-    ESP_HF_SUBSCRIBER_SERVICE_TYPE_FAX,              /*!< fax service */
-} esp_hf_subscriber_service_type_t;
-
-/// +BTRH response and hold result code
-typedef enum {
-    ESP_HF_BTRH_STATUS_HELD = 0,       /*!< incoming call is put on held in AG */
-    ESP_HF_BTRH_STATUS_ACCEPTED,       /*!< held incoming call is accepted in AG */
-    ESP_HF_BTRH_STATUS_REJECTED,       /*!< held incoming call is rejected in AG */
-} esp_hf_btrh_status_t;
-
-/// AT+BTRH response and hold action code
-typedef enum {
-    ESP_HF_BTRH_CMD_HOLD = 0,          /*!< put the incoming call on hold */
-    ESP_HF_BTRH_CMD_ACCEPT = 1,        /*!< accept a held incoming call */
-    ESP_HF_BTRH_CMD_REJECT = 2,        /*!< reject a held incoming call */
-} esp_hf_btrh_cmd_t;
-
-/// response indication codes for AT commands
-typedef enum {
-    ESP_HF_AT_RESPONSE_CODE_OK = 0,         /*!< acknowledges execution of a command line */
-    ESP_HF_AT_RESPONSE_CODE_ERR,            /*!< command not accepted */
-    ESP_HF_AT_RESPONSE_CODE_NO_CARRIER,     /*!< connection terminated */
-    ESP_HF_AT_RESPONSE_CODE_BUSY,           /*!< busy signal detected */
-    ESP_HF_AT_RESPONSE_CODE_NO_ANSWER,      /*!< connection completion timeout */
-    ESP_HF_AT_RESPONSE_CODE_DELAYED,        /*!< delayed */
-    ESP_HF_AT_RESPONSE_CODE_BLACKLISTED,    /*!< blacklisted */
-    ESP_HF_AT_RESPONSE_CODE_CME,            /*!< CME error */
-} esp_hf_at_response_code_t;
-
-/// voice recognition state
-typedef enum {
-    ESP_HF_VR_STATE_DISABLED = 0,           /*!< voice recognition disabled */
-    ESP_HF_VR_STATE_ENABLED,                /*!< voice recognition enabled */
-} esp_hf_vr_state_t;
-
-/// AT+CHLD command values
-typedef enum {
-    ESP_HF_CHLD_TYPE_REL = 0,               /*!< <0>, Terminate all held or set UDUB("busy") to a waiting call */
-    ESP_HF_CHLD_TYPE_REL_ACC,               /*!< <1>, Terminate all active calls and accepts a waiting/held call */
-    ESP_HF_CHLD_TYPE_HOLD_ACC,              /*!< <2>, Hold all active calls and accepts a waiting/held call */
-    ESP_HF_CHLD_TYPE_MERGE,                 /*!< <3>, Add all held calls to a conference */
-    ESP_HF_CHLD_TYPE_MERGE_DETACH,          /*!< <4>, connect the two calls and disconnects the subscriber from both calls */
-    ESP_HF_CHLD_TYPE_REL_X,                 /*!< <1x>, releases specified calls only */
-    ESP_HF_CHLD_TYPE_PRIV_X,                /*!< <2x>, request private consultation mode with specified call */
-} esp_hf_chld_type_t;
-
-/// Extended Audio Gateway Error Result Code Response
-typedef enum {
-    ESP_HF_CME_AG_FAILURE = 0,                    /*!< ag failure */
-    ESP_HF_CME_NO_CONNECTION_TO_PHONE = 1,        /*!< no connection to phone */
-    ESP_HF_CME_OPERATION_NOT_ALLOWED = 3,         /*!< operation not allowed */
-    ESP_HF_CME_OPERATION_NOT_SUPPORTED = 4,       /*!< operation not supported */
-    ESP_HF_CME_PH_SIM_PIN_REQUIRED = 5,           /*!< PH-SIM PIN Required */
-    ESP_HF_CME_SIM_NOT_INSERTED = 10,             /*!< SIM not inserted */
-    ESP_HF_CME_SIM_PIN_REQUIRED = 11,             /*!< SIM PIN required */
-    ESP_HF_CME_SIM_PUK_REQUIRED = 12,             /*!< SIM PUK required */
-    ESP_HF_CME_SIM_FAILURE = 13,                  /*!< SIM failure */
-    ESP_HF_CME_SIM_BUSY = 14,                     /*!< SIM busy */
-    ESP_HF_CME_INCORRECT_PASSWORD = 16,           /*!< incorrect password */
-    ESP_HF_CME_SIM_PIN2_REQUIRED = 17,            /*!< SIM PIN2 required */
-    ESP_HF_CME_SIM_PUK2_REQUIRED = 18,            /*!< SIM PUK2 required */
-    ESP_HF_CME_MEMEORY_FULL = 20,                 /*!< memory full */
-    ESP_HF_CME_INVALID_INDEX = 21,                /*!< invalid index */
-    ESP_HF_CME_MEMEORY_FAILURE = 23,              /*!< memory failure */
-    ESP_HF_CME_TEXT_STRING_TOO_LONG = 24,         /*!< test string too long */
-    ESP_HF_CME_INVALID_CHARACTERS_IN_TEXT_STRING = 25,  /*!< invalid characters in text string */
-    ESP_HF_CME_DIAL_STRING_TOO_LONG = 26,         /*!< dial string too long*/
-    ESP_HF_CME_INVALID_CHARACTERS_IN_DIAL_STRING = 27,  /*!< invalid characters in dial string */
-    ESP_HF_CME_NO_NETWORK_SERVICE = 30,           /*!< no network service */
-    ESP_HF_CME_NETWORK_TIMEOUT = 31,              /*!< network timeout */
-    ESP_HF_CME_NETWORK_NOT_ALLOWED = 32,          /*!< network not allowed --emergency calls only */
-} esp_hf_cme_err_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_HF_DEFS_H__ */
diff --git a/tools/sdk/include/bt/esp_spp_api.h b/tools/sdk/include/bt/esp_spp_api.h
deleted file mode 100644
index 9e657642499..00000000000
--- a/tools/sdk/include/bt/esp_spp_api.h
+++ /dev/null
@@ -1,331 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_SPP_API_H__
-#define __ESP_SPP_API_H__
-
-#include "esp_err.h"
-#include "esp_bt_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ESP_SPP_SUCCESS   = 0,          /*!< Successful operation. */
-    ESP_SPP_FAILURE,                /*!< Generic failure. */
-    ESP_SPP_BUSY,                   /*!< Temporarily can not handle this request. */
-    ESP_SPP_NO_DATA,                /*!< no data. */
-    ESP_SPP_NO_RESOURCE             /*!< No more set pm control block */
-} esp_spp_status_t;
-
-/* Security Setting Mask, Suggest to use ESP_SPP_SEC_NONE, ESP_SPP_SEC_AUTHORIZE or ESP_SPP_SEC_AUTHENTICATE only.*/
-#define ESP_SPP_SEC_NONE            0x0000    /*!< No security. relate to BTA_SEC_NONE in bta/bta_api.h */
-#define ESP_SPP_SEC_AUTHORIZE       0x0001    /*!< Authorization required (only needed for out going connection ) relate to BTA_SEC_AUTHORIZE in bta/bta_api.h*/
-#define ESP_SPP_SEC_AUTHENTICATE    0x0012    /*!< Authentication required.  relate to BTA_SEC_AUTHENTICATE in bta/bta_api.h*/
-#define ESP_SPP_SEC_ENCRYPT         0x0024    /*!< Encryption required.  relate to BTA_SEC_ENCRYPT in bta/bta_api.h*/
-#define ESP_SPP_SEC_MODE4_LEVEL4    0x0040    /*!< Mode 4 level 4 service, i.e. incoming/outgoing MITM and P-256 encryption  relate to BTA_SEC_MODE4_LEVEL4 in bta/bta_api.h*/
-#define ESP_SPP_SEC_MITM            0x3000    /*!< Man-In-The_Middle protection  relate to BTA_SEC_MITM in bta/bta_api.h*/
-#define ESP_SPP_SEC_IN_16_DIGITS    0x4000    /*!< Min 16 digit for pin code  relate to BTA_SEC_IN_16_DIGITS in bta/bta_api.h*/
-typedef uint16_t esp_spp_sec_t;
-
-typedef enum {
-    ESP_SPP_ROLE_MASTER     = 0,          /*!< Role: master */
-    ESP_SPP_ROLE_SLAVE      = 1,          /*!< Role: slave */
-} esp_spp_role_t;
-
-typedef enum {
-    ESP_SPP_MODE_CB         = 0,          /*!< When data is coming, a callback will come with data */
-    ESP_SPP_MODE_VFS        = 1,          /*!< Use VFS to write/read data */
-} esp_spp_mode_t;
-
-#define ESP_SPP_MAX_MTU                 (3*330)     /*!< SPP max MTU */
-#define ESP_SPP_MAX_SCN                 31          /*!< SPP max SCN */
-/**
- * @brief SPP callback function events
- */
-typedef enum {
-    ESP_SPP_INIT_EVT                    = 0,                /*!< When SPP is inited, the event comes */
-    ESP_SPP_UNINIT_EVT                  = 1,                /*!< When SPP is uninited, the event comes */
-    ESP_SPP_DISCOVERY_COMP_EVT          = 8,                /*!< When SDP discovery complete, the event comes */
-    ESP_SPP_OPEN_EVT                    = 26,               /*!< When SPP Client connection open, the event comes */
-    ESP_SPP_CLOSE_EVT                   = 27,               /*!< When SPP connection closed, the event comes */
-    ESP_SPP_START_EVT                   = 28,               /*!< When SPP server started, the event comes */
-    ESP_SPP_CL_INIT_EVT                 = 29,               /*!< When SPP client initiated a connection, the event comes */
-    ESP_SPP_DATA_IND_EVT                = 30,               /*!< When SPP connection received data, the event comes, only for ESP_SPP_MODE_CB */
-    ESP_SPP_CONG_EVT                    = 31,               /*!< When SPP connection congestion status changed, the event comes, only for ESP_SPP_MODE_CB */
-    ESP_SPP_WRITE_EVT                   = 33,               /*!< When SPP write operation completes, the event comes, only for ESP_SPP_MODE_CB */
-    ESP_SPP_SRV_OPEN_EVT                = 34,               /*!< When SPP Server connection open, the event comes */
-    ESP_SPP_SRV_STOP_EVT                = 35,               /*!< When SPP server stopped, the event comes */
-} esp_spp_cb_event_t;
-
-
-/**
- * @brief SPP callback parameters union
- */
-typedef union {
-    /**
-     * @brief SPP_INIT_EVT
-     */
-    struct spp_init_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-    } init;                                 /*!< SPP callback param of SPP_INIT_EVT */
-
-    /**
-     * @brief SPP_UNINIT_EVT
-     */
-    struct spp_uninit_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-    } uninit;                                 /*!< SPP callback param of SPP_UNINIT_EVT */
-
-    /**
-     * @brief SPP_DISCOVERY_COMP_EVT
-     */
-    struct spp_discovery_comp_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-        uint8_t             scn_num;        /*!< The num of scn_num */
-        uint8_t             scn[ESP_SPP_MAX_SCN];    /*!< channel # */
-    } disc_comp;                            /*!< SPP callback param of SPP_DISCOVERY_COMP_EVT */
-
-    /**
-     * @brief ESP_SPP_OPEN_EVT
-     */
-    struct spp_open_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-        uint32_t            handle;         /*!< The connection handle */
-        int                 fd;             /*!< The file descriptor only for ESP_SPP_MODE_VFS */
-        esp_bd_addr_t       rem_bda;        /*!< The peer address */
-    } open;                                 /*!< SPP callback param of ESP_SPP_OPEN_EVT */
-
-    /**
-     * @brief ESP_SPP_SRV_OPEN_EVT
-     */
-    struct spp_srv_open_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-        uint32_t            handle;         /*!< The connection handle */
-        uint32_t            new_listen_handle;  /*!< The new listen handle */
-        int                 fd;             /*!< The file descriptor only for ESP_SPP_MODE_VFS */
-        esp_bd_addr_t       rem_bda;        /*!< The peer address */
-    } srv_open;                             /*!< SPP callback param of ESP_SPP_SRV_OPEN_EVT */
-    /**
-     * @brief ESP_SPP_CLOSE_EVT
-     */
-    struct spp_close_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-        uint32_t            port_status;    /*!< PORT status */
-        uint32_t            handle;         /*!< The connection handle */
-        bool                async;          /*!< FALSE, if local initiates disconnect */
-    } close;                                /*!< SPP callback param of ESP_SPP_CLOSE_EVT */
-
-    /**
-     * @brief ESP_SPP_START_EVT
-     */
-    struct spp_start_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-        uint32_t            handle;         /*!< The connection handle */
-        uint8_t             sec_id;         /*!< security ID used by this server */
-        bool                use_co;         /*!< TRUE to use co_rfc_data */
-    } start;                                /*!< SPP callback param of ESP_SPP_START_EVT */
-
-    /**
-     * @brief ESP_SPP_SRV_STOP_EVT
-     */
-    struct spp_srv_stop_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-    } srv_stop;                                 /*!< SPP callback param of ESP_SPP_SRV_STOP_EVT */
-
-    /**
-     * @brief ESP_SPP_CL_INIT_EVT
-     */
-    struct spp_cl_init_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-        uint32_t            handle;         /*!< The connection handle */
-        uint8_t             sec_id;         /*!< security ID used by this server */
-        bool                use_co;         /*!< TRUE to use co_rfc_data */
-    } cl_init;                              /*!< SPP callback param of ESP_SPP_CL_INIT_EVT */
-
-    /**
-     * @brief ESP_SPP_WRITE_EVT
-     */
-    struct spp_write_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-        uint32_t            handle;         /*!< The connection handle */
-        int                 len;            /*!< The length of the data written. */
-        bool                cong;           /*!< congestion status */
-    } write;                                /*!< SPP callback param of ESP_SPP_WRITE_EVT */
-
-    /**
-     * @brief ESP_SPP_DATA_IND_EVT
-     */
-    struct spp_data_ind_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-        uint32_t            handle;         /*!< The connection handle */
-        uint16_t            len;            /*!< The length of data */
-        uint8_t             *data;          /*!< The data received */
-    } data_ind;                             /*!< SPP callback param of ESP_SPP_DATA_IND_EVT */
-
-    /**
-     * @brief ESP_SPP_CONG_EVT
-     */
-    struct spp_cong_evt_param {
-        esp_spp_status_t    status;         /*!< status */
-        uint32_t            handle;         /*!< The connection handle */
-        bool                cong;           /*!< TRUE, congested. FALSE, uncongested */
-    } cong;                                 /*!< SPP callback param of ESP_SPP_CONG_EVT */
-} esp_spp_cb_param_t;                       /*!< SPP callback parameter union type */
-
-/**
- * @brief       SPP callback function type
- * @param       event:      Event type
- * @param       param:      Point to callback parameter, currently is union type
- */
-typedef void (esp_spp_cb_t)(esp_spp_cb_event_t event, esp_spp_cb_param_t *param);
-
-/**
- * @brief       This function is called to init callbacks
- *              with SPP module.
- *
- * @param[in]   callback:   pointer to the init callback function.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_register_callback(esp_spp_cb_t callback);
-
-/**
- * @brief       This function is called to init SPP.
- *
- * @param[in]   mode: Choose the mode of SPP, ESP_SPP_MODE_CB or ESP_SPP_MODE_VFS.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_init(esp_spp_mode_t mode);
-
-/**
- * @brief       This function is called to uninit SPP.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_deinit();
-
-
-/**
- * @brief       This function is called to performs service discovery for
- *              the services provided by the given peer device. When the
- *              operation is complete the callback function will be called
- *              with a ESP_SPP_DISCOVERY_COMP_EVT.
- *
- * @param[in]   bd_addr:   Remote device bluetooth device address.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_start_discovery(esp_bd_addr_t bd_addr);
-
-/**
- * @brief       This function makes an SPP connection to a remote BD Address.
- *              When the connection is initiated or failed to initiate,
- *              the callback is called with ESP_SPP_CL_INIT_EVT.
- *              When the connection is established or failed,
- *              the callback is called with ESP_SPP_OPEN_EVT.
- *
- * @param[in]   sec_mask:     Security Setting Mask. Suggest to use ESP_SPP_SEC_NONE, ESP_SPP_SEC_AUTHORIZE or ESP_SPP_SEC_AUTHENTICATE only.
- * @param[in]   role:         Master or slave.
- * @param[in]   remote_scn:   Remote device bluetooth device SCN.
- * @param[in]   peer_bd_addr: Remote device bluetooth device address.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_connect(esp_spp_sec_t sec_mask,
-                          esp_spp_role_t role, uint8_t remote_scn, esp_bd_addr_t peer_bd_addr);
-
-/**
- * @brief       This function closes an SPP connection.
- *
- * @param[in]   handle:    The connection handle.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_disconnect(uint32_t handle);
-
-/**
- * @brief       This function create a SPP server and starts listening for an
- *              SPP connection request from a remote Bluetooth device.
- *              When the server is started successfully, the callback is called
- *              with ESP_SPP_START_EVT.
- *              When the connection is established, the callback is called
- *              with ESP_SPP_SRV_OPEN_EVT.
- *
- * @param[in]   sec_mask:     Security Setting Mask. Security Setting Mask. Suggest to use ESP_SPP_SEC_NONE, ESP_SPP_SEC_AUTHORIZE or ESP_SPP_SEC_AUTHENTICATE only.
- * @param[in]   role:         Master or slave.
- * @param[in]   local_scn:    The specific channel you want to get.
- *                            If channel is 0, means get any channel.
- * @param[in]   name:         Server's name.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_start_srv(esp_spp_sec_t sec_mask,
-                            esp_spp_role_t role, uint8_t local_scn, const char *name);
-
-/**
- * @brief       This function stops a SPP server
- *              When the server is stopped successfully, the callback is called
- *              with ESP_SPP_SRV_STOP_EVT.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_stop_srv(void);
-
-/**
- * @brief       This function is used to write data, only for ESP_SPP_MODE_CB.
- *
- * @param[in]   handle: The connection handle.
- * @param[in]   len:    The length of the data written.
- * @param[in]   p_data: The data written.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_write(uint32_t handle, int len, uint8_t *p_data);
-
-
-/**
- * @brief       This function is used to register VFS.
- *
- * @return
- *              - ESP_OK: success
- *              - other: failed
- */
-esp_err_t esp_spp_vfs_register(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif ///__ESP_SPP_API_H__
diff --git a/tools/sdk/include/coap/address.h b/tools/sdk/include/coap/address.h
deleted file mode 100644
index 85db2046e36..00000000000
--- a/tools/sdk/include/coap/address.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * address.h -- representation of network addresses
- *
- * Copyright (C) 2010-2011,2015-2016 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file address.h
- * @brief Representation of network addresses
- */
-
-#ifndef _COAP_ADDRESS_H_
-#define _COAP_ADDRESS_H_
-
-#include <assert.h>
-#include <stdint.h>
-#include <string.h>
-#include <sys/types.h>
-#include "libcoap.h"
-
-#ifdef WITH_LWIP
-#include <lwip/ip_addr.h>
-
-typedef struct coap_address_t {
-  uint16_t port;
-  ip_addr_t addr;
-} coap_address_t;
-
-#define _coap_address_equals_impl(A, B)   (!!ip_addr_cmp(&(A)->addr,&(B)->addr))
-
-#define _coap_address_isany_impl(A)  ip_addr_isany(&(A)->addr)
-
-#define _coap_is_mcast_impl(Address) ip_addr_ismulticast(&(Address)->addr)
-#endif /* WITH_LWIP */
-
-#ifdef WITH_CONTIKI
-#include "uip.h"
-
-typedef struct coap_address_t {
-  uip_ipaddr_t addr;
-  unsigned short port;
-} coap_address_t;
-
-#define _coap_address_equals_impl(A,B) \
-        ((A)->port == (B)->port        \
-        && uip_ipaddr_cmp(&((A)->addr),&((B)->addr)))
-
-/** @todo implementation of _coap_address_isany_impl() for Contiki */
-#define _coap_address_isany_impl(A)  0
-
-#define _coap_is_mcast_impl(Address) uip_is_addr_mcast(&((Address)->addr))
-#endif /* WITH_CONTIKI */
-
-#ifdef WITH_POSIX
-/** multi-purpose address abstraction */
-typedef struct coap_address_t {
-  socklen_t size;           /**< size of addr */
-  union {
-    struct sockaddr         sa;
-    struct sockaddr_storage st;
-    struct sockaddr_in      sin;
-    struct sockaddr_in6     sin6;
-  } addr;
-} coap_address_t;
-
-/**
- * Compares given address objects @p a and @p b. This function returns @c 1 if
- * addresses are equal, @c 0 otherwise. The parameters @p a and @p b must not be
- * @c NULL;
- */
-int coap_address_equals(const coap_address_t *a, const coap_address_t *b);
-
-static inline int
-_coap_address_isany_impl(const coap_address_t *a) {
-  /* need to compare only relevant parts of sockaddr_in6 */
-  switch (a->addr.sa.sa_family) {
-  case AF_INET:
-    return a->addr.sin.sin_addr.s_addr == INADDR_ANY;
-  case AF_INET6:
-    return memcmp(&in6addr_any,
-                  &a->addr.sin6.sin6_addr,
-                  sizeof(in6addr_any)) == 0;
-  default:
-    ;
-  }
-
-  return 0;
-}
-#endif /* WITH_POSIX */
-
-/**
- * Resets the given coap_address_t object @p addr to its default values. In
- * particular, the member size must be initialized to the available size for
- * storing addresses.
- *
- * @param addr The coap_address_t object to initialize.
- */
-static inline void
-coap_address_init(coap_address_t *addr) {
-  assert(addr);
-  memset(addr, 0, sizeof(coap_address_t));
-#ifdef WITH_POSIX
-  /* lwip and Contiki have constant address sizes and doesn't need the .size part */
-  addr->size = sizeof(addr->addr);
-#endif
-}
-
-#ifndef WITH_POSIX
-/**
- * Compares given address objects @p a and @p b. This function returns @c 1 if
- * addresses are equal, @c 0 otherwise. The parameters @p a and @p b must not be
- * @c NULL;
- */
-static inline int
-coap_address_equals(const coap_address_t *a, const coap_address_t *b) {
-  assert(a); assert(b);
-  return _coap_address_equals_impl(a, b);
-}
-#endif
-
-/**
- * Checks if given address object @p a denotes the wildcard address. This
- * function returns @c 1 if this is the case, @c 0 otherwise. The parameters @p
- * a must not be @c NULL;
- */
-static inline int
-coap_address_isany(const coap_address_t *a) {
-  assert(a);
-  return _coap_address_isany_impl(a);
-}
-
-#ifdef WITH_POSIX
-/**
- * Checks if given address @p a denotes a multicast address. This function
- * returns @c 1 if @p a is multicast, @c 0 otherwise.
- */
-int coap_is_mcast(const coap_address_t *a);
-#else /* WITH_POSIX */
-/**
- * Checks if given address @p a denotes a multicast address. This function
- * returns @c 1 if @p a is multicast, @c 0 otherwise.
- */
-static inline int
-coap_is_mcast(const coap_address_t *a) {
-  return a && _coap_is_mcast_impl(a);
-}
-#endif /* WITH_POSIX */
-
-#endif /* _COAP_ADDRESS_H_ */
diff --git a/tools/sdk/include/coap/async.h b/tools/sdk/include/coap/async.h
deleted file mode 100644
index 0c36defacdb..00000000000
--- a/tools/sdk/include/coap/async.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * async.h -- state management for asynchronous messages
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file async.h
- * @brief State management for asynchronous messages
- */
-
-#ifndef _COAP_ASYNC_H_
-#define _COAP_ASYNC_H_
-
-#include "net.h"
-
-#ifndef WITHOUT_ASYNC
-
-/**
- * @defgroup coap_async Asynchronous Messaging
- * @{
- * Structure for managing asynchronous state of CoAP resources. A
- * coap_resource_t object holds a list of coap_async_state_t objects that can be
- * used to generate a separate response in case a result of an operation cannot
- * be delivered in time, or the resource has been explicitly subscribed to with
- * the option @c observe.
- */
-typedef struct coap_async_state_t {
-  unsigned char flags;  /**< holds the flags to control behaviour */
-
-  /**
-   * Holds the internal time when the object was registered with a
-   * resource. This field will be updated whenever
-   * coap_register_async() is called for a specific resource.
-   */
-  coap_tick_t created;
-
-  /**
-   * This field can be used to register opaque application data with the
-   * asynchronous state object.
-   */
-  void *appdata;
-  unsigned short message_id;       /**< id of last message seen */
-  coap_tid_t id;                   /**< transaction id */
-  struct coap_async_state_t *next; /**< internally used for linking */
-  coap_address_t peer;             /**< the peer to notify */
-  size_t tokenlen;                 /**< length of the token */
-  unsigned char token[];           /**< the token to use in a response */
-} coap_async_state_t;
-
-/* Definitions for Async Status Flags These flags can be used to control the
- * behaviour of asynchronous response generation.
- */
-#define COAP_ASYNC_CONFIRM   0x01  /**< send confirmable response */
-#define COAP_ASYNC_SEPARATE  0x02  /**< send separate response */
-#define COAP_ASYNC_OBSERVED  0x04  /**< the resource is being observed */
-
-/** release application data on destruction */
-#define COAP_ASYNC_RELEASE_DATA  0x08
-
-/**
- * Allocates a new coap_async_state_t object and fills its fields according to
- * the given @p request. The @p flags are used to control generation of empty
- * ACK responses to stop retransmissions and to release registered @p data when
- * the resource is deleted by coap_free_async(). This function returns a pointer
- * to the registered coap_async_t object or @c NULL on error. Note that this
- * function will return @c NULL in case that an object with the same identifier
- * is already registered.
- *
- * @param context  The context to use.
- * @param peer     The remote peer that is to be asynchronously notified.
- * @param request  The request that is handled asynchronously.
- * @param flags    Flags to control state management.
- * @param data     Opaque application data to register. Note that the
- *                 storage occupied by @p data is released on destruction
- *                 only if flag COAP_ASYNC_RELEASE_DATA is set.
- *
- * @return         A pointer to the registered coap_async_state_t object or @c
- *                 NULL in case of an error.
- */
-coap_async_state_t *
-coap_register_async(coap_context_t *context,
-                    coap_address_t *peer,
-                    coap_pdu_t *request,
-                    unsigned char flags,
-                    void *data);
-
-/**
- * Removes the state object identified by @p id from @p context. The removed
- * object is returned in @p s, if found. Otherwise, @p s is undefined. This
- * function returns @c 1 if the object was removed, @c 0 otherwise. Note that
- * the storage allocated for the stored object is not released by this
- * functions. You will have to call coap_free_async() to do so.
- *
- * @param context The context where the async object is registered.
- * @param id      The identifier of the asynchronous transaction.
- * @param s       Will be set to the object identified by @p id after removal.
- *
- * @return        @c 1 if object was removed and @p s updated, or @c 0 if no
- *                object was found with the given id. @p s is valid only if the
- *                return value is @c 1.
- */
-int coap_remove_async(coap_context_t *context,
-                      coap_tid_t id,
-                      coap_async_state_t **s);
-
-/**
- * Releases the memory that was allocated by coap_async_state_init() for the
- * object @p s. The registered application data will be released automatically
- * if COAP_ASYNC_RELEASE_DATA is set.
- *
- * @param state The object to delete.
- */
-void
-coap_free_async(coap_async_state_t *state);
-
-/**
- * Retrieves the object identified by @p id from the list of asynchronous
- * transactions that are registered with @p context. This function returns a
- * pointer to that object or @c NULL if not found.
- *
- * @param context The context where the asynchronous objects are registered
- *                with.
- * @param id      The id of the object to retrieve.
- *
- * @return        A pointer to the object identified by @p id or @c NULL if
- *                not found.
- */
-coap_async_state_t *coap_find_async(coap_context_t *context, coap_tid_t id);
-
-/**
- * Updates the time stamp of @p s.
- *
- * @param s The state object to update.
- */
-static inline void
-coap_touch_async(coap_async_state_t *s) { coap_ticks(&s->created); }
-
-/** @} */
-
-#endif /*  WITHOUT_ASYNC */
-
-#endif /* _COAP_ASYNC_H_ */
diff --git a/tools/sdk/include/coap/bits.h b/tools/sdk/include/coap/bits.h
deleted file mode 100644
index 0b269166d57..00000000000
--- a/tools/sdk/include/coap/bits.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * bits.h -- bit vector manipulation
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file bits.h
- * @brief Bit vector manipulation
- */
-
-#ifndef _COAP_BITS_H_
-#define _COAP_BITS_H_
-
-#include <stdint.h>
-
-/**
- * Sets the bit @p bit in bit-vector @p vec. This function returns @c 1 if bit
- * was set or @c -1 on error (i.e. when the given bit does not fit in the
- * vector).
- *
- * @param vec  The bit-vector to change.
- * @param size The size of @p vec in bytes.
- * @param bit  The bit to set in @p vec.
- *
- * @return     @c -1 if @p bit does not fit into @p vec, @c 1 otherwise.
- */
-inline static int
-bits_setb(uint8_t *vec, size_t size, uint8_t bit) {
-  if (size <= (bit >> 3))
-    return -1;
-
-  *(vec + (bit >> 3)) |= (uint8_t)(1 << (bit & 0x07));
-  return 1;
-}
-
-/**
- * Clears the bit @p bit from bit-vector @p vec. This function returns @c 1 if
- * bit was cleared or @c -1 on error (i.e. when the given bit does not fit in
- * the vector).
- *
- * @param vec  The bit-vector to change.
- * @param size The size of @p vec in bytes.
- * @param bit  The bit to clear from @p vec.
- *
- * @return     @c -1 if @p bit does not fit into @p vec, @c 1 otherwise.
- */
-inline static int
-bits_clrb(uint8_t *vec, size_t size, uint8_t bit) {
-  if (size <= (bit >> 3))
-    return -1;
-
-  *(vec + (bit >> 3)) &= (uint8_t)(~(1 << (bit & 0x07)));
-  return 1;
-}
-
-/**
- * Gets the status of bit @p bit from bit-vector @p vec. This function returns
- * @c 1 if the bit is set, @c 0 otherwise (even in case of an error).
- *
- * @param vec  The bit-vector to read from.
- * @param size The size of @p vec in bytes.
- * @param bit  The bit to get from @p vec.
- *
- * @return     @c 1 if the bit is set, @c 0 otherwise.
- */
-inline static int
-bits_getb(const uint8_t *vec, size_t size, uint8_t bit) {
-  if (size <= (bit >> 3))
-    return -1;
-
-  return (*(vec + (bit >> 3)) & (1 << (bit & 0x07))) != 0;
-}
-
-#endif /* _COAP_BITS_H_ */
diff --git a/tools/sdk/include/coap/block.h b/tools/sdk/include/coap/block.h
deleted file mode 100644
index 9ce00311cc4..00000000000
--- a/tools/sdk/include/coap/block.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * block.h -- block transfer
- *
- * Copyright (C) 2010-2012,2014-2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_BLOCK_H_
-#define _COAP_BLOCK_H_
-
-#include "encode.h"
-#include "option.h"
-#include "pdu.h"
-
-/**
- * @defgroup block Block Transfer
- * @{
- */
-
-#ifndef COAP_MAX_BLOCK_SZX
-/**
- * The largest value for the SZX component in a Block option. Note that
- * 1 << (COAP_MAX_BLOCK_SZX + 4) should not exceed COAP_MAX_PDU_SIZE.
- */
-#define COAP_MAX_BLOCK_SZX      4
-#endif /* COAP_MAX_BLOCK_SZX */
-
-/**
- * Structure of Block options.
- */
-typedef struct {
-  unsigned int num;       /**< block number */
-  unsigned int m:1;       /**< 1 if more blocks follow, 0 otherwise */
-  unsigned int szx:3;     /**< block size */
-} coap_block_t;
-
-/**
- * Returns the value of the least significant byte of a Block option @p opt.
- * For zero-length options (i.e. num == m == szx == 0), COAP_OPT_BLOCK_LAST
- * returns @c NULL.
- */
-#define COAP_OPT_BLOCK_LAST(opt) \
-  (COAP_OPT_LENGTH(opt) ? (COAP_OPT_VALUE(opt) + (COAP_OPT_LENGTH(opt)-1)) : 0)
-
-/** Returns the value of the More-bit of a Block option @p opt. */
-#define COAP_OPT_BLOCK_MORE(opt) \
-  (COAP_OPT_LENGTH(opt) ? (*COAP_OPT_BLOCK_LAST(opt) & 0x08) : 0)
-
-/** Returns the value of the SZX-field of a Block option @p opt. */
-#define COAP_OPT_BLOCK_SZX(opt)  \
-  (COAP_OPT_LENGTH(opt) ? (*COAP_OPT_BLOCK_LAST(opt) & 0x07) : 0)
-
-/**
- * Returns the value of field @c num in the given block option @p block_opt.
- */
-unsigned int coap_opt_block_num(const coap_opt_t *block_opt);
-
-/**
- * Checks if more than @p num blocks are required to deliver @p data_len
- * bytes of data for a block size of 1 << (@p szx + 4).
- */
-static inline int
-coap_more_blocks(size_t data_len, unsigned int num, unsigned short szx) {
-  return ((num+1) << (szx + 4)) < data_len;
-}
-
-/** Sets the More-bit in @p block_opt */
-static inline void
-coap_opt_block_set_m(coap_opt_t *block_opt, int m) {
-  if (m)
-    *(COAP_OPT_VALUE(block_opt) + (COAP_OPT_LENGTH(block_opt) - 1)) |= 0x08;
-  else
-    *(COAP_OPT_VALUE(block_opt) + (COAP_OPT_LENGTH(block_opt) - 1)) &= ~0x08;
-}
-
-/**
- * Initializes @p block from @p pdu. @p type must be either COAP_OPTION_BLOCK1
- * or COAP_OPTION_BLOCK2. When option @p type was found in @p pdu, @p block is
- * initialized with values from this option and the function returns the value
- * @c 1. Otherwise, @c 0 is returned.
- *
- * @param pdu   The pdu to search for option @p type.
- * @param type  The option to search for (must be COAP_OPTION_BLOCK1 or
- *              COAP_OPTION_BLOCK2).
- * @param block The block structure to initilize.
- *
- * @return      @c 1 on success, @c 0 otherwise.
- */
-int coap_get_block(coap_pdu_t *pdu, unsigned short type, coap_block_t *block);
-
-/**
- * Writes a block option of type @p type to message @p pdu. If the requested
- * block size is too large to fit in @p pdu, it is reduced accordingly. An
- * exception is made for the final block when less space is required. The actual
- * length of the resource is specified in @p data_length.
- *
- * This function may change *block to reflect the values written to @p pdu. As
- * the function takes into consideration the remaining space @p pdu, no more
- * options should be added after coap_write_block_opt() has returned.
- *
- * @param block       The block structure to use. On return, this object is
- *                    updated according to the values that have been written to
- *                    @p pdu.
- * @param type        COAP_OPTION_BLOCK1 or COAP_OPTION_BLOCK2.
- * @param pdu         The message where the block option should be written.
- * @param data_length The length of the actual data that will be added the @p
- *                    pdu by calling coap_add_block().
- *
- * @return            @c 1 on success, or a negative value on error.
- */
-int coap_write_block_opt(coap_block_t *block,
-                         unsigned short type,
-                         coap_pdu_t *pdu,
-                         size_t data_length);
-
-/**
- * Adds the @p block_num block of size 1 << (@p block_szx + 4) from source @p
- * data to @p pdu.
- *
- * @param pdu       The message to add the block.
- * @param len       The length of @p data.
- * @param data      The source data to fill the block with.
- * @param block_num The actual block number.
- * @param block_szx Encoded size of block @p block_number.
- *
- * @return          @c 1 on success, @c 0 otherwise.
- */
-int coap_add_block(coap_pdu_t *pdu,
-                   unsigned int len,
-                   const unsigned char *data,
-                   unsigned int block_num,
-                   unsigned char block_szx);
-/**@}*/
-
-#endif /* _COAP_BLOCK_H_ */
diff --git a/tools/sdk/include/coap/coap.h b/tools/sdk/include/coap/coap.h
deleted file mode 100644
index cbdc9dfc81b..00000000000
--- a/tools/sdk/include/coap/coap.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Modify head file implementation for ESP32 platform.
- *
- * Uses libcoap software implementation for failover when concurrent
- * define operations are in use.
- *
- * coap.h -- main header file for CoAP stack of libcoap
- *
- * Copyright (C) 2010-2012,2015-2016 Olaf Bergmann <bergmann@tzi.org>
- *               2015 Carsten Schoenert <c.schoenert@t-online.de>
- *
- * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_H_
-#define _COAP_H_
-
-#include "libcoap.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "address.h"
-#include "async.h"
-#include "bits.h"
-#include "block.h"
-#include "coap_io.h"
-#include "coap_time.h"
-#include "debug.h"
-#include "encode.h"
-#include "mem.h"
-#include "net.h"
-#include "option.h"
-#include "pdu.h"
-#include "prng.h"
-#include "resource.h"
-#include "str.h"
-#include "subscribe.h"
-#include "uri.h"
-#include "uthash.h"
-#include "utlist.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _COAP_H_ */
diff --git a/tools/sdk/include/coap/coap/address.h b/tools/sdk/include/coap/coap/address.h
deleted file mode 100644
index 85db2046e36..00000000000
--- a/tools/sdk/include/coap/coap/address.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * address.h -- representation of network addresses
- *
- * Copyright (C) 2010-2011,2015-2016 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file address.h
- * @brief Representation of network addresses
- */
-
-#ifndef _COAP_ADDRESS_H_
-#define _COAP_ADDRESS_H_
-
-#include <assert.h>
-#include <stdint.h>
-#include <string.h>
-#include <sys/types.h>
-#include "libcoap.h"
-
-#ifdef WITH_LWIP
-#include <lwip/ip_addr.h>
-
-typedef struct coap_address_t {
-  uint16_t port;
-  ip_addr_t addr;
-} coap_address_t;
-
-#define _coap_address_equals_impl(A, B)   (!!ip_addr_cmp(&(A)->addr,&(B)->addr))
-
-#define _coap_address_isany_impl(A)  ip_addr_isany(&(A)->addr)
-
-#define _coap_is_mcast_impl(Address) ip_addr_ismulticast(&(Address)->addr)
-#endif /* WITH_LWIP */
-
-#ifdef WITH_CONTIKI
-#include "uip.h"
-
-typedef struct coap_address_t {
-  uip_ipaddr_t addr;
-  unsigned short port;
-} coap_address_t;
-
-#define _coap_address_equals_impl(A,B) \
-        ((A)->port == (B)->port        \
-        && uip_ipaddr_cmp(&((A)->addr),&((B)->addr)))
-
-/** @todo implementation of _coap_address_isany_impl() for Contiki */
-#define _coap_address_isany_impl(A)  0
-
-#define _coap_is_mcast_impl(Address) uip_is_addr_mcast(&((Address)->addr))
-#endif /* WITH_CONTIKI */
-
-#ifdef WITH_POSIX
-/** multi-purpose address abstraction */
-typedef struct coap_address_t {
-  socklen_t size;           /**< size of addr */
-  union {
-    struct sockaddr         sa;
-    struct sockaddr_storage st;
-    struct sockaddr_in      sin;
-    struct sockaddr_in6     sin6;
-  } addr;
-} coap_address_t;
-
-/**
- * Compares given address objects @p a and @p b. This function returns @c 1 if
- * addresses are equal, @c 0 otherwise. The parameters @p a and @p b must not be
- * @c NULL;
- */
-int coap_address_equals(const coap_address_t *a, const coap_address_t *b);
-
-static inline int
-_coap_address_isany_impl(const coap_address_t *a) {
-  /* need to compare only relevant parts of sockaddr_in6 */
-  switch (a->addr.sa.sa_family) {
-  case AF_INET:
-    return a->addr.sin.sin_addr.s_addr == INADDR_ANY;
-  case AF_INET6:
-    return memcmp(&in6addr_any,
-                  &a->addr.sin6.sin6_addr,
-                  sizeof(in6addr_any)) == 0;
-  default:
-    ;
-  }
-
-  return 0;
-}
-#endif /* WITH_POSIX */
-
-/**
- * Resets the given coap_address_t object @p addr to its default values. In
- * particular, the member size must be initialized to the available size for
- * storing addresses.
- *
- * @param addr The coap_address_t object to initialize.
- */
-static inline void
-coap_address_init(coap_address_t *addr) {
-  assert(addr);
-  memset(addr, 0, sizeof(coap_address_t));
-#ifdef WITH_POSIX
-  /* lwip and Contiki have constant address sizes and doesn't need the .size part */
-  addr->size = sizeof(addr->addr);
-#endif
-}
-
-#ifndef WITH_POSIX
-/**
- * Compares given address objects @p a and @p b. This function returns @c 1 if
- * addresses are equal, @c 0 otherwise. The parameters @p a and @p b must not be
- * @c NULL;
- */
-static inline int
-coap_address_equals(const coap_address_t *a, const coap_address_t *b) {
-  assert(a); assert(b);
-  return _coap_address_equals_impl(a, b);
-}
-#endif
-
-/**
- * Checks if given address object @p a denotes the wildcard address. This
- * function returns @c 1 if this is the case, @c 0 otherwise. The parameters @p
- * a must not be @c NULL;
- */
-static inline int
-coap_address_isany(const coap_address_t *a) {
-  assert(a);
-  return _coap_address_isany_impl(a);
-}
-
-#ifdef WITH_POSIX
-/**
- * Checks if given address @p a denotes a multicast address. This function
- * returns @c 1 if @p a is multicast, @c 0 otherwise.
- */
-int coap_is_mcast(const coap_address_t *a);
-#else /* WITH_POSIX */
-/**
- * Checks if given address @p a denotes a multicast address. This function
- * returns @c 1 if @p a is multicast, @c 0 otherwise.
- */
-static inline int
-coap_is_mcast(const coap_address_t *a) {
-  return a && _coap_is_mcast_impl(a);
-}
-#endif /* WITH_POSIX */
-
-#endif /* _COAP_ADDRESS_H_ */
diff --git a/tools/sdk/include/coap/coap/async.h b/tools/sdk/include/coap/coap/async.h
deleted file mode 100644
index 0c36defacdb..00000000000
--- a/tools/sdk/include/coap/coap/async.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * async.h -- state management for asynchronous messages
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file async.h
- * @brief State management for asynchronous messages
- */
-
-#ifndef _COAP_ASYNC_H_
-#define _COAP_ASYNC_H_
-
-#include "net.h"
-
-#ifndef WITHOUT_ASYNC
-
-/**
- * @defgroup coap_async Asynchronous Messaging
- * @{
- * Structure for managing asynchronous state of CoAP resources. A
- * coap_resource_t object holds a list of coap_async_state_t objects that can be
- * used to generate a separate response in case a result of an operation cannot
- * be delivered in time, or the resource has been explicitly subscribed to with
- * the option @c observe.
- */
-typedef struct coap_async_state_t {
-  unsigned char flags;  /**< holds the flags to control behaviour */
-
-  /**
-   * Holds the internal time when the object was registered with a
-   * resource. This field will be updated whenever
-   * coap_register_async() is called for a specific resource.
-   */
-  coap_tick_t created;
-
-  /**
-   * This field can be used to register opaque application data with the
-   * asynchronous state object.
-   */
-  void *appdata;
-  unsigned short message_id;       /**< id of last message seen */
-  coap_tid_t id;                   /**< transaction id */
-  struct coap_async_state_t *next; /**< internally used for linking */
-  coap_address_t peer;             /**< the peer to notify */
-  size_t tokenlen;                 /**< length of the token */
-  unsigned char token[];           /**< the token to use in a response */
-} coap_async_state_t;
-
-/* Definitions for Async Status Flags These flags can be used to control the
- * behaviour of asynchronous response generation.
- */
-#define COAP_ASYNC_CONFIRM   0x01  /**< send confirmable response */
-#define COAP_ASYNC_SEPARATE  0x02  /**< send separate response */
-#define COAP_ASYNC_OBSERVED  0x04  /**< the resource is being observed */
-
-/** release application data on destruction */
-#define COAP_ASYNC_RELEASE_DATA  0x08
-
-/**
- * Allocates a new coap_async_state_t object and fills its fields according to
- * the given @p request. The @p flags are used to control generation of empty
- * ACK responses to stop retransmissions and to release registered @p data when
- * the resource is deleted by coap_free_async(). This function returns a pointer
- * to the registered coap_async_t object or @c NULL on error. Note that this
- * function will return @c NULL in case that an object with the same identifier
- * is already registered.
- *
- * @param context  The context to use.
- * @param peer     The remote peer that is to be asynchronously notified.
- * @param request  The request that is handled asynchronously.
- * @param flags    Flags to control state management.
- * @param data     Opaque application data to register. Note that the
- *                 storage occupied by @p data is released on destruction
- *                 only if flag COAP_ASYNC_RELEASE_DATA is set.
- *
- * @return         A pointer to the registered coap_async_state_t object or @c
- *                 NULL in case of an error.
- */
-coap_async_state_t *
-coap_register_async(coap_context_t *context,
-                    coap_address_t *peer,
-                    coap_pdu_t *request,
-                    unsigned char flags,
-                    void *data);
-
-/**
- * Removes the state object identified by @p id from @p context. The removed
- * object is returned in @p s, if found. Otherwise, @p s is undefined. This
- * function returns @c 1 if the object was removed, @c 0 otherwise. Note that
- * the storage allocated for the stored object is not released by this
- * functions. You will have to call coap_free_async() to do so.
- *
- * @param context The context where the async object is registered.
- * @param id      The identifier of the asynchronous transaction.
- * @param s       Will be set to the object identified by @p id after removal.
- *
- * @return        @c 1 if object was removed and @p s updated, or @c 0 if no
- *                object was found with the given id. @p s is valid only if the
- *                return value is @c 1.
- */
-int coap_remove_async(coap_context_t *context,
-                      coap_tid_t id,
-                      coap_async_state_t **s);
-
-/**
- * Releases the memory that was allocated by coap_async_state_init() for the
- * object @p s. The registered application data will be released automatically
- * if COAP_ASYNC_RELEASE_DATA is set.
- *
- * @param state The object to delete.
- */
-void
-coap_free_async(coap_async_state_t *state);
-
-/**
- * Retrieves the object identified by @p id from the list of asynchronous
- * transactions that are registered with @p context. This function returns a
- * pointer to that object or @c NULL if not found.
- *
- * @param context The context where the asynchronous objects are registered
- *                with.
- * @param id      The id of the object to retrieve.
- *
- * @return        A pointer to the object identified by @p id or @c NULL if
- *                not found.
- */
-coap_async_state_t *coap_find_async(coap_context_t *context, coap_tid_t id);
-
-/**
- * Updates the time stamp of @p s.
- *
- * @param s The state object to update.
- */
-static inline void
-coap_touch_async(coap_async_state_t *s) { coap_ticks(&s->created); }
-
-/** @} */
-
-#endif /*  WITHOUT_ASYNC */
-
-#endif /* _COAP_ASYNC_H_ */
diff --git a/tools/sdk/include/coap/coap/bits.h b/tools/sdk/include/coap/coap/bits.h
deleted file mode 100644
index 0b269166d57..00000000000
--- a/tools/sdk/include/coap/coap/bits.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * bits.h -- bit vector manipulation
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file bits.h
- * @brief Bit vector manipulation
- */
-
-#ifndef _COAP_BITS_H_
-#define _COAP_BITS_H_
-
-#include <stdint.h>
-
-/**
- * Sets the bit @p bit in bit-vector @p vec. This function returns @c 1 if bit
- * was set or @c -1 on error (i.e. when the given bit does not fit in the
- * vector).
- *
- * @param vec  The bit-vector to change.
- * @param size The size of @p vec in bytes.
- * @param bit  The bit to set in @p vec.
- *
- * @return     @c -1 if @p bit does not fit into @p vec, @c 1 otherwise.
- */
-inline static int
-bits_setb(uint8_t *vec, size_t size, uint8_t bit) {
-  if (size <= (bit >> 3))
-    return -1;
-
-  *(vec + (bit >> 3)) |= (uint8_t)(1 << (bit & 0x07));
-  return 1;
-}
-
-/**
- * Clears the bit @p bit from bit-vector @p vec. This function returns @c 1 if
- * bit was cleared or @c -1 on error (i.e. when the given bit does not fit in
- * the vector).
- *
- * @param vec  The bit-vector to change.
- * @param size The size of @p vec in bytes.
- * @param bit  The bit to clear from @p vec.
- *
- * @return     @c -1 if @p bit does not fit into @p vec, @c 1 otherwise.
- */
-inline static int
-bits_clrb(uint8_t *vec, size_t size, uint8_t bit) {
-  if (size <= (bit >> 3))
-    return -1;
-
-  *(vec + (bit >> 3)) &= (uint8_t)(~(1 << (bit & 0x07)));
-  return 1;
-}
-
-/**
- * Gets the status of bit @p bit from bit-vector @p vec. This function returns
- * @c 1 if the bit is set, @c 0 otherwise (even in case of an error).
- *
- * @param vec  The bit-vector to read from.
- * @param size The size of @p vec in bytes.
- * @param bit  The bit to get from @p vec.
- *
- * @return     @c 1 if the bit is set, @c 0 otherwise.
- */
-inline static int
-bits_getb(const uint8_t *vec, size_t size, uint8_t bit) {
-  if (size <= (bit >> 3))
-    return -1;
-
-  return (*(vec + (bit >> 3)) & (1 << (bit & 0x07))) != 0;
-}
-
-#endif /* _COAP_BITS_H_ */
diff --git a/tools/sdk/include/coap/coap/block.h b/tools/sdk/include/coap/coap/block.h
deleted file mode 100644
index 9ce00311cc4..00000000000
--- a/tools/sdk/include/coap/coap/block.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * block.h -- block transfer
- *
- * Copyright (C) 2010-2012,2014-2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_BLOCK_H_
-#define _COAP_BLOCK_H_
-
-#include "encode.h"
-#include "option.h"
-#include "pdu.h"
-
-/**
- * @defgroup block Block Transfer
- * @{
- */
-
-#ifndef COAP_MAX_BLOCK_SZX
-/**
- * The largest value for the SZX component in a Block option. Note that
- * 1 << (COAP_MAX_BLOCK_SZX + 4) should not exceed COAP_MAX_PDU_SIZE.
- */
-#define COAP_MAX_BLOCK_SZX      4
-#endif /* COAP_MAX_BLOCK_SZX */
-
-/**
- * Structure of Block options.
- */
-typedef struct {
-  unsigned int num;       /**< block number */
-  unsigned int m:1;       /**< 1 if more blocks follow, 0 otherwise */
-  unsigned int szx:3;     /**< block size */
-} coap_block_t;
-
-/**
- * Returns the value of the least significant byte of a Block option @p opt.
- * For zero-length options (i.e. num == m == szx == 0), COAP_OPT_BLOCK_LAST
- * returns @c NULL.
- */
-#define COAP_OPT_BLOCK_LAST(opt) \
-  (COAP_OPT_LENGTH(opt) ? (COAP_OPT_VALUE(opt) + (COAP_OPT_LENGTH(opt)-1)) : 0)
-
-/** Returns the value of the More-bit of a Block option @p opt. */
-#define COAP_OPT_BLOCK_MORE(opt) \
-  (COAP_OPT_LENGTH(opt) ? (*COAP_OPT_BLOCK_LAST(opt) & 0x08) : 0)
-
-/** Returns the value of the SZX-field of a Block option @p opt. */
-#define COAP_OPT_BLOCK_SZX(opt)  \
-  (COAP_OPT_LENGTH(opt) ? (*COAP_OPT_BLOCK_LAST(opt) & 0x07) : 0)
-
-/**
- * Returns the value of field @c num in the given block option @p block_opt.
- */
-unsigned int coap_opt_block_num(const coap_opt_t *block_opt);
-
-/**
- * Checks if more than @p num blocks are required to deliver @p data_len
- * bytes of data for a block size of 1 << (@p szx + 4).
- */
-static inline int
-coap_more_blocks(size_t data_len, unsigned int num, unsigned short szx) {
-  return ((num+1) << (szx + 4)) < data_len;
-}
-
-/** Sets the More-bit in @p block_opt */
-static inline void
-coap_opt_block_set_m(coap_opt_t *block_opt, int m) {
-  if (m)
-    *(COAP_OPT_VALUE(block_opt) + (COAP_OPT_LENGTH(block_opt) - 1)) |= 0x08;
-  else
-    *(COAP_OPT_VALUE(block_opt) + (COAP_OPT_LENGTH(block_opt) - 1)) &= ~0x08;
-}
-
-/**
- * Initializes @p block from @p pdu. @p type must be either COAP_OPTION_BLOCK1
- * or COAP_OPTION_BLOCK2. When option @p type was found in @p pdu, @p block is
- * initialized with values from this option and the function returns the value
- * @c 1. Otherwise, @c 0 is returned.
- *
- * @param pdu   The pdu to search for option @p type.
- * @param type  The option to search for (must be COAP_OPTION_BLOCK1 or
- *              COAP_OPTION_BLOCK2).
- * @param block The block structure to initilize.
- *
- * @return      @c 1 on success, @c 0 otherwise.
- */
-int coap_get_block(coap_pdu_t *pdu, unsigned short type, coap_block_t *block);
-
-/**
- * Writes a block option of type @p type to message @p pdu. If the requested
- * block size is too large to fit in @p pdu, it is reduced accordingly. An
- * exception is made for the final block when less space is required. The actual
- * length of the resource is specified in @p data_length.
- *
- * This function may change *block to reflect the values written to @p pdu. As
- * the function takes into consideration the remaining space @p pdu, no more
- * options should be added after coap_write_block_opt() has returned.
- *
- * @param block       The block structure to use. On return, this object is
- *                    updated according to the values that have been written to
- *                    @p pdu.
- * @param type        COAP_OPTION_BLOCK1 or COAP_OPTION_BLOCK2.
- * @param pdu         The message where the block option should be written.
- * @param data_length The length of the actual data that will be added the @p
- *                    pdu by calling coap_add_block().
- *
- * @return            @c 1 on success, or a negative value on error.
- */
-int coap_write_block_opt(coap_block_t *block,
-                         unsigned short type,
-                         coap_pdu_t *pdu,
-                         size_t data_length);
-
-/**
- * Adds the @p block_num block of size 1 << (@p block_szx + 4) from source @p
- * data to @p pdu.
- *
- * @param pdu       The message to add the block.
- * @param len       The length of @p data.
- * @param data      The source data to fill the block with.
- * @param block_num The actual block number.
- * @param block_szx Encoded size of block @p block_number.
- *
- * @return          @c 1 on success, @c 0 otherwise.
- */
-int coap_add_block(coap_pdu_t *pdu,
-                   unsigned int len,
-                   const unsigned char *data,
-                   unsigned int block_num,
-                   unsigned char block_szx);
-/**@}*/
-
-#endif /* _COAP_BLOCK_H_ */
diff --git a/tools/sdk/include/coap/coap/coap.h b/tools/sdk/include/coap/coap/coap.h
deleted file mode 100644
index cbdc9dfc81b..00000000000
--- a/tools/sdk/include/coap/coap/coap.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Modify head file implementation for ESP32 platform.
- *
- * Uses libcoap software implementation for failover when concurrent
- * define operations are in use.
- *
- * coap.h -- main header file for CoAP stack of libcoap
- *
- * Copyright (C) 2010-2012,2015-2016 Olaf Bergmann <bergmann@tzi.org>
- *               2015 Carsten Schoenert <c.schoenert@t-online.de>
- *
- * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_H_
-#define _COAP_H_
-
-#include "libcoap.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "address.h"
-#include "async.h"
-#include "bits.h"
-#include "block.h"
-#include "coap_io.h"
-#include "coap_time.h"
-#include "debug.h"
-#include "encode.h"
-#include "mem.h"
-#include "net.h"
-#include "option.h"
-#include "pdu.h"
-#include "prng.h"
-#include "resource.h"
-#include "str.h"
-#include "subscribe.h"
-#include "uri.h"
-#include "uthash.h"
-#include "utlist.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _COAP_H_ */
diff --git a/tools/sdk/include/coap/coap/coap_io.h b/tools/sdk/include/coap/coap/coap_io.h
deleted file mode 100644
index 7a48b319a1d..00000000000
--- a/tools/sdk/include/coap/coap/coap_io.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * coap_io.h -- Default network I/O functions for libcoap
- *
- * Copyright (C) 2012-2013 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_IO_H_
-#define _COAP_IO_H_
-
-#include <assert.h>
-#include <sys/types.h>
-
-#include "address.h"
-
-/**
- * Abstract handle that is used to identify a local network interface.
- */
-typedef int coap_if_handle_t;
-
-/** Invalid interface handle */
-#define COAP_IF_INVALID -1
-
-struct coap_packet_t;
-typedef struct coap_packet_t coap_packet_t;
-
-struct coap_context_t;
-
-/**
- * Abstraction of virtual endpoint that can be attached to coap_context_t. The
- * tuple (handle, addr) must uniquely identify this endpoint.
- */
-typedef struct coap_endpoint_t {
-#if defined(WITH_POSIX) || defined(WITH_CONTIKI)
-  union {
-    int fd;       /**< on POSIX systems */
-    void *conn;   /**< opaque connection (e.g. uip_conn in Contiki) */
-  } handle;       /**< opaque handle to identify this endpoint */
-#endif /* WITH_POSIX or WITH_CONTIKI */
-
-#ifdef WITH_LWIP
-  struct udp_pcb *pcb;
- /**< @FIXME --chrysn
-  * this was added in a hurry, not sure it confirms to the overall model */
-  struct coap_context_t *context;
-#endif /* WITH_LWIP */
-
-  coap_address_t addr; /**< local interface address */
-  int ifindex;
-  int flags;
-} coap_endpoint_t;
-
-#define COAP_ENDPOINT_NOSEC 0x00
-#define COAP_ENDPOINT_DTLS  0x01
-
-coap_endpoint_t *coap_new_endpoint(const coap_address_t *addr, int flags);
-
-void coap_free_endpoint(coap_endpoint_t *ep);
-
-/**
- * Function interface for data transmission. This function returns the number of
- * bytes that have been transmitted, or a value less than zero on error.
- *
- * @param context          The calling CoAP context.
- * @param local_interface  The local interface to send the data.
- * @param dst              The address of the receiver.
- * @param data             The data to send.
- * @param datalen          The actual length of @p data.
- *
- * @return                 The number of bytes written on success, or a value
- *                         less than zero on error.
- */
-ssize_t coap_network_send(struct coap_context_t *context,
-                          const coap_endpoint_t *local_interface,
-                          const coap_address_t *dst,
-                          unsigned char *data, size_t datalen);
-
-/**
- * Function interface for reading data. This function returns the number of
- * bytes that have been read, or a value less than zero on error. In case of an
- * error, @p *packet is set to NULL.
- *
- * @param ep     The endpoint that is used for reading data from the network.
- * @param packet A result parameter where a pointer to the received packet
- *               structure is stored. The caller must call coap_free_packet to
- *               release the storage used by this packet.
- *
- * @return       The number of bytes received on success, or a value less than
- *               zero on error.
- */
-ssize_t coap_network_read(coap_endpoint_t *ep, coap_packet_t **packet);
-
-#ifndef coap_mcast_interface
-# define coap_mcast_interface(Local) 0
-#endif
-
-/**
- * Releases the storage allocated for @p packet.
- */
-void coap_free_packet(coap_packet_t *packet);
-
-/**
- * Populate the coap_endpoint_t *target from the incoming packet's destination
- * data.
- *
- * This is usually used to copy a packet's data into a node's local_if member.
- */
-void coap_packet_populate_endpoint(coap_packet_t *packet,
-                                   coap_endpoint_t *target);
-
-/**
- * Given an incoming packet, copy its source address into an address struct.
- */
-void coap_packet_copy_source(coap_packet_t *packet, coap_address_t *target);
-
-/**
- * Given a packet, set msg and msg_len to an address and length of the packet's
- * data in memory.
- * */
-void coap_packet_get_memmapped(coap_packet_t *packet,
-                               unsigned char **address,
-                               size_t *length);
-
-#ifdef WITH_LWIP
-/**
- * Get the pbuf of a packet. The caller takes over responsibility for freeing
- * the pbuf.
- */
-struct pbuf *coap_packet_extract_pbuf(coap_packet_t *packet);
-#endif
-
-#ifdef WITH_CONTIKI
-/*
- * This is only included in coap_io.h instead of .c in order to be available for
- * sizeof in mem.c.
- */
-struct coap_packet_t {
-  coap_if_handle_t hnd;         /**< the interface handle */
-  coap_address_t src;           /**< the packet's source address */
-  coap_address_t dst;           /**< the packet's destination address */
-  const coap_endpoint_t *interface;
-  int ifindex;
-  void *session;                /**< opaque session data */
-  size_t length;                /**< length of payload */
-  unsigned char payload[];      /**< payload */
-};
-#endif
-
-#ifdef WITH_LWIP
-/*
- * This is only included in coap_io.h instead of .c in order to be available for
- * sizeof in lwippools.h.
- * Simple carry-over of the incoming pbuf that is later turned into a node.
- *
- * Source address data is currently side-banded via ip_current_dest_addr & co
- * as the packets have limited lifetime anyway.
- */
-struct coap_packet_t {
-  struct pbuf *pbuf;
-  const coap_endpoint_t *local_interface;
-  uint16_t srcport;
-};
-#endif
-
-#endif /* _COAP_IO_H_ */
diff --git a/tools/sdk/include/coap/coap/coap_time.h b/tools/sdk/include/coap/coap/coap_time.h
deleted file mode 100644
index 9357e5ff7d0..00000000000
--- a/tools/sdk/include/coap/coap/coap_time.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * coap_time.h -- Clock Handling
- *
- * Copyright (C) 2010-2013 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file coap_time.h
- * @brief Clock Handling
- */
-
-#ifndef _COAP_TIME_H_
-#define _COAP_TIME_H_
-
-/**
- * @defgroup clock Clock Handling
- * Default implementation of internal clock.
- * @{
- */
-
-#ifdef WITH_LWIP
-
-#include <stdint.h>
-#include <lwip/sys.h>
-
-/* lwIP provides ms in sys_now */
-#define COAP_TICKS_PER_SECOND 1000
-
-typedef uint32_t coap_tick_t;
-typedef uint32_t coap_time_t;
-typedef int32_t coap_tick_diff_t;
-
-static inline void coap_ticks_impl(coap_tick_t *t) {
-  *t = sys_now();
-}
-
-static inline void coap_clock_init_impl(void) {
-}
-
-#define coap_clock_init coap_clock_init_impl
-#define coap_ticks coap_ticks_impl
-
-static inline coap_time_t coap_ticks_to_rt(coap_tick_t t) {
-  return t / COAP_TICKS_PER_SECOND;
-}
-#endif
-
-#ifdef WITH_CONTIKI
-#include "clock.h"
-
-typedef clock_time_t coap_tick_t;
-typedef clock_time_t coap_time_t;
-
-/**
- * This data type is used to represent the difference between two clock_tick_t
- * values. This data type must have the same size in memory as coap_tick_t to
- * allow wrapping.
- */
-typedef int coap_tick_diff_t;
-
-#define COAP_TICKS_PER_SECOND CLOCK_SECOND
-
-static inline void coap_clock_init(void) {
-  clock_init();
-}
-
-static inline void coap_ticks(coap_tick_t *t) {
-  *t = clock_time();
-}
-
-static inline coap_time_t coap_ticks_to_rt(coap_tick_t t) {
-  return t / COAP_TICKS_PER_SECOND;
-}
-#endif /* WITH_CONTIKI */
-
-#ifdef WITH_POSIX
-/**
- * This data type represents internal timer ticks with COAP_TICKS_PER_SECOND
- * resolution.
- */
-typedef unsigned long coap_tick_t;
-
-/**
- * CoAP time in seconds since epoch.
- */
-typedef time_t coap_time_t;
-
-/**
- * This data type is used to represent the difference between two clock_tick_t
- * values. This data type must have the same size in memory as coap_tick_t to
- * allow wrapping.
- */
-typedef long coap_tick_diff_t;
-
-/** Use ms resolution on POSIX systems */
-#define COAP_TICKS_PER_SECOND 1000
-
-/**
- * Initializes the internal clock.
- */
-void coap_clock_init(void);
-
-/**
- * Sets @p t to the internal time with COAP_TICKS_PER_SECOND resolution.
- */
-void coap_ticks(coap_tick_t *t);
-
-/**
- * Helper function that converts coap ticks to wallclock time. On POSIX, this
- * function returns the number of seconds since the epoch. On other systems, it
- * may be the calculated number of seconds since last reboot or so.
- *
- * @param t Internal system ticks.
- *
- * @return  The number of seconds that has passed since a specific reference
- *          point (seconds since epoch on POSIX).
- */
-coap_time_t coap_ticks_to_rt(coap_tick_t t);
-#endif /* WITH_POSIX */
-
-/**
- * Returns @c 1 if and only if @p a is less than @p b where less is defined on a
- * signed data type.
- */
-static inline int coap_time_lt(coap_tick_t a, coap_tick_t b) {
-  return ((coap_tick_diff_t)(a - b)) < 0;
-}
-
-/**
- * Returns @c 1 if and only if @p a is less than or equal @p b where less is
- * defined on a signed data type.
- */
-static inline int coap_time_le(coap_tick_t a, coap_tick_t b) {
-  return a == b || coap_time_lt(a,b);
-}
-
-/** @} */
-
-#endif /* _COAP_TIME_H_ */
diff --git a/tools/sdk/include/coap/coap/debug.h b/tools/sdk/include/coap/coap/debug.h
deleted file mode 100644
index e7c86aff517..00000000000
--- a/tools/sdk/include/coap/coap/debug.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * debug.h -- debug utilities
- *
- * Copyright (C) 2010-2011,2014 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_DEBUG_H_
-#define _COAP_DEBUG_H_
-
-#ifndef COAP_DEBUG_FD
-#define COAP_DEBUG_FD stdout
-#endif
-
-#ifndef COAP_ERR_FD
-#define COAP_ERR_FD stderr
-#endif
-
-#ifdef HAVE_SYSLOG_H
-#include <syslog.h>
-typedef short coap_log_t;
-#else
-/** Pre-defined log levels akin to what is used in \b syslog. */
-typedef enum {
-  LOG_EMERG=0,
-  LOG_ALERT,
-  LOG_CRIT,
-  LOG_ERR,
-  LOG_WARNING,
-  LOG_NOTICE,
-  LOG_INFO,
-  LOG_DEBUG
-} coap_log_t;
-#endif
-
-/** Returns the current log level. */
-coap_log_t coap_get_log_level(void);
-
-/** Sets the log level to the specified value. */
-void coap_set_log_level(coap_log_t level);
-
-/** Returns a zero-terminated string with the name of this library. */
-const char *coap_package_name(void);
-
-/** Returns a zero-terminated string with the library version. */
-const char *coap_package_version(void);
-
-/**
- * Writes the given text to @c COAP_ERR_FD (for @p level <= @c LOG_CRIT) or @c
- * COAP_DEBUG_FD (for @p level >= @c LOG_WARNING). The text is output only when
- * @p level is below or equal to the log level that set by coap_set_log_level().
- */
-void coap_log_impl(coap_log_t level, const char *format, ...);
-
-#ifndef coap_log
-#define coap_log(...) coap_log_impl(__VA_ARGS__)
-#endif
-
-#ifndef NDEBUG
-
-/* A set of convenience macros for common log levels. */
-#define info(...) coap_log(LOG_INFO, __VA_ARGS__)
-#define warn(...) coap_log(LOG_WARNING, __VA_ARGS__)
-#define debug(...) coap_log(LOG_DEBUG, __VA_ARGS__)
-
-#include "pdu.h"
-void coap_show_pdu(const coap_pdu_t *);
-
-struct coap_address_t;
-size_t coap_print_addr(const struct coap_address_t *, unsigned char *, size_t);
-
-#else
-
-#define debug(...)
-#define info(...)
-#define warn(...)
-
-#define coap_show_pdu(x)
-#define coap_print_addr(...)
-
-#endif /* NDEBUG */
-
-#endif /* _COAP_DEBUG_H_ */
diff --git a/tools/sdk/include/coap/coap/encode.h b/tools/sdk/include/coap/coap/encode.h
deleted file mode 100644
index a5d290c4ecf..00000000000
--- a/tools/sdk/include/coap/coap/encode.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * encode.h -- encoding and decoding of CoAP data types
- *
- * Copyright (C) 2010-2012 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_ENCODE_H_
-#define _COAP_ENCODE_H_
-
-#if (BSD >= 199103) || defined(WITH_CONTIKI)
-# include <string.h>
-#else
-# include <strings.h>
-#endif
-
-#define Nn 8  /* duplicate definition of N if built on sky motes */
-#define ENCODE_HEADER_SIZE 4
-#define HIBIT (1 << (Nn - 1))
-#define EMASK ((1 << ENCODE_HEADER_SIZE) - 1)
-#define MMASK ((1 << Nn) - 1 - EMASK)
-#define MAX_VALUE ( (1 << Nn) - (1 << ENCODE_HEADER_SIZE) ) * (1 << ((1 << ENCODE_HEADER_SIZE) - 1))
-
-#define COAP_PSEUDOFP_DECODE_8_4(r) (r < HIBIT ? r : (r & MMASK) << (r & EMASK))
-
-#ifndef HAVE_FLS
-/* include this only if fls() is not available */
-extern int coap_fls(unsigned int i);
-#else
-#define coap_fls(i) fls(i)
-#endif
-
-/* ls and s must be integer variables */
-#define COAP_PSEUDOFP_ENCODE_8_4_DOWN(v,ls) (v < HIBIT ? v : (ls = coap_fls(v) - Nn, (v >> ls) & MMASK) + ls)
-#define COAP_PSEUDOFP_ENCODE_8_4_UP(v,ls,s) (v < HIBIT ? v : (ls = coap_fls(v) - Nn, (s = (((v + ((1<<ENCODE_HEADER_SIZE<<ls)-1)) >> ls) & MMASK)), s == 0 ? HIBIT + ls + 1 : s + ls))
-
-/**
- * Decodes multiple-length byte sequences. buf points to an input byte sequence
- * of length len. Returns the decoded value.
- */
-unsigned int coap_decode_var_bytes(unsigned char *buf,unsigned int len);
-
-/**
- * Encodes multiple-length byte sequences. buf points to an output buffer of
- * sufficient length to store the encoded bytes. val is the value to encode.
- * Returns the number of bytes used to encode val or 0 on error.
- */
-unsigned int coap_encode_var_bytes(unsigned char *buf, unsigned int val);
-
-#endif /* _COAP_ENCODE_H_ */
diff --git a/tools/sdk/include/coap/coap/hashkey.h b/tools/sdk/include/coap/coap/hashkey.h
deleted file mode 100644
index 5cff67d2d8a..00000000000
--- a/tools/sdk/include/coap/coap/hashkey.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * hashkey.h -- definition of hash key type and helper functions
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file hashkey.h
- * @brief definition of hash key type and helper functions
- */
-
-#ifndef _COAP_HASHKEY_H_
-#define _COAP_HASHKEY_H_
-
-#include "str.h"
-
-typedef unsigned char coap_key_t[4];
-
-#ifndef coap_hash
-/**
- * Calculates a fast hash over the given string @p s of length @p len and stores
- * the result into @p h. Depending on the exact implementation, this function
- * cannot be used as one-way function to check message integrity or simlar.
- *
- * @param s   The string used for hash calculation.
- * @param len The length of @p s.
- * @param h   The result buffer to store the calculated hash key.
- */
-void coap_hash_impl(const unsigned char *s, unsigned int len, coap_key_t h);
-
-#define coap_hash(String,Length,Result) \
-  coap_hash_impl((String),(Length),(Result))
-
-/* This is used to control the pre-set hash-keys for resources. */
-#define __COAP_DEFAULT_HASH
-#else
-#undef __COAP_DEFAULT_HASH
-#endif /* coap_hash */
-
-/**
- * Calls coap_hash() with given @c str object as parameter.
- *
- * @param Str Must contain a pointer to a coap string object.
- * @param H   A coap_key_t object to store the result.
- *
- * @hideinitializer
- */
-#define coap_str_hash(Str,H) {               \
-    assert(Str);                             \
-    memset((H), 0, sizeof(coap_key_t));      \
-    coap_hash((Str)->s, (Str)->length, (H)); \
-  }
-
-#endif /* _COAP_HASHKEY_H_ */
diff --git a/tools/sdk/include/coap/coap/libcoap.h b/tools/sdk/include/coap/coap/libcoap.h
deleted file mode 100644
index 214b9e235e8..00000000000
--- a/tools/sdk/include/coap/coap/libcoap.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * libcoap.h -- platform specific header file for CoAP stack
- *
- * Copyright (C) 2015 Carsten Schoenert <c.schoenert@t-online.de>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _LIBCOAP_H_
-#define _LIBCOAP_H_
-
-/* The non posix embedded platforms like Contiki, TinyOS, RIOT, ... doesn't have
- * a POSIX compatible header structure so we have to slightly do some platform
- * related things. Currently there is only Contiki available so we check for a
- * CONTIKI environment and do *not* include the POSIX related network stuff. If
- * there are other platforms in future there need to be analogous environments.
- *
- * The CONTIKI variable is within the Contiki build environment! */
-
-#if !defined (CONTIKI) 
-#include <netinet/in.h>
-#include <sys/socket.h>
-#endif /* CONTIKI */
-
-#endif /* _LIBCOAP_H_ */
diff --git a/tools/sdk/include/coap/coap/lwippools.h b/tools/sdk/include/coap/coap/lwippools.h
deleted file mode 100644
index 0bfb3f527a7..00000000000
--- a/tools/sdk/include/coap/coap/lwippools.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/** Memory pool definitions for the libcoap when used with lwIP (which has its
- * own mechanism for quickly allocating chunks of data with known sizes). Has
- * to be findable by lwIP (ie. an #include <lwippools.h> must either directly
- * include this or include something more generic which includes this), and
- * MEMP_USE_CUSTOM_POOLS has to be set in lwipopts.h. */
-
-#include "coap_config.h"
-#include <net.h>
-#include <resource.h>
-#include <subscribe.h>
-
-#ifndef MEMP_NUM_COAPCONTEXT
-#define MEMP_NUM_COAPCONTEXT 1
-#endif
-
-#ifndef MEMP_NUM_COAPENDPOINT
-#define MEMP_NUM_COAPENDPOINT 1
-#endif
-
-/* 1 is sufficient as this is very short-lived */
-#ifndef MEMP_NUM_COAPPACKET
-#define MEMP_NUM_COAPPACKET 1
-#endif
-
-#ifndef MEMP_NUM_COAPNODE
-#define MEMP_NUM_COAPNODE 4
-#endif
-
-#ifndef MEMP_NUM_COAPPDU
-#define MEMP_NUM_COAPPDU MEMP_NUM_COAPNODE
-#endif
-
-#ifndef MEMP_NUM_COAP_SUBSCRIPTION
-#define MEMP_NUM_COAP_SUBSCRIPTION 4
-#endif
-
-#ifndef MEMP_NUM_COAPRESOURCE
-#define MEMP_NUM_COAPRESOURCE 10
-#endif
-
-#ifndef MEMP_NUM_COAPRESOURCEATTR
-#define MEMP_NUM_COAPRESOURCEATTR 20
-#endif
-
-LWIP_MEMPOOL(COAP_CONTEXT, MEMP_NUM_COAPCONTEXT, sizeof(coap_context_t), "COAP_CONTEXT")
-LWIP_MEMPOOL(COAP_ENDPOINT, MEMP_NUM_COAPENDPOINT, sizeof(coap_endpoint_t), "COAP_ENDPOINT")
-LWIP_MEMPOOL(COAP_PACKET, MEMP_NUM_COAPPACKET, sizeof(coap_packet_t), "COAP_PACKET")
-LWIP_MEMPOOL(COAP_NODE, MEMP_NUM_COAPNODE, sizeof(coap_queue_t), "COAP_NODE")
-LWIP_MEMPOOL(COAP_PDU, MEMP_NUM_COAPPDU, sizeof(coap_pdu_t), "COAP_PDU")
-LWIP_MEMPOOL(COAP_subscription, MEMP_NUM_COAP_SUBSCRIPTION, sizeof(coap_subscription_t), "COAP_subscription")
-LWIP_MEMPOOL(COAP_RESOURCE, MEMP_NUM_COAPRESOURCE, sizeof(coap_resource_t), "COAP_RESOURCE")
-LWIP_MEMPOOL(COAP_RESOURCEATTR, MEMP_NUM_COAPRESOURCEATTR, sizeof(coap_attr_t), "COAP_RESOURCEATTR")
diff --git a/tools/sdk/include/coap/coap/mem.h b/tools/sdk/include/coap/coap/mem.h
deleted file mode 100644
index fd3c69aafde..00000000000
--- a/tools/sdk/include/coap/coap/mem.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * mem.h -- CoAP memory handling
- *
- * Copyright (C) 2010-2011,2014-2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_MEM_H_
-#define _COAP_MEM_H_
-
-#include <stdlib.h>
-
-#ifndef WITH_LWIP
-/**
- * Initializes libcoap's memory management.
- * This function must be called once before coap_malloc() can be used on
- * constrained devices.
- */
-void coap_memory_init(void);
-#endif /* WITH_LWIP */
-
-/**
- * Type specifiers for coap_malloc_type(). Memory objects can be typed to
- * facilitate arrays of type objects to be used instead of dynamic memory
- * management on constrained devices.
- */
-typedef enum {
-  COAP_STRING,
-  COAP_ATTRIBUTE_NAME,
-  COAP_ATTRIBUTE_VALUE,
-  COAP_PACKET,
-  COAP_NODE,
-  COAP_CONTEXT,
-  COAP_ENDPOINT,
-  COAP_PDU,
-  COAP_PDU_BUF,
-  COAP_RESOURCE,
-  COAP_RESOURCEATTR
-} coap_memory_tag_t;
-
-#ifndef WITH_LWIP
-
-/**
- * Allocates a chunk of @p size bytes and returns a pointer to the newly
- * allocated memory. The @p type is used to select the appropriate storage
- * container on constrained devices. The storage allocated by coap_malloc_type()
- * must be released with coap_free_type().
- *
- * @param type The type of object to be stored.
- * @param size The number of bytes requested.
- * @return     A pointer to the allocated storage or @c NULL on error.
- */
-void *coap_malloc_type(coap_memory_tag_t type, size_t size);
-
-/**
- * Releases the memory that was allocated by coap_malloc_type(). The type tag @p
- * type must be the same that was used for allocating the object pointed to by
- * @p .
- *
- * @param type The type of the object to release.
- * @param p    A pointer to memory that was allocated by coap_malloc_type().
- */
-void coap_free_type(coap_memory_tag_t type, void *p);
-
-/**
- * Wrapper function to coap_malloc_type() for backwards compatibility.
- */
-static inline void *coap_malloc(size_t size) {
-  return coap_malloc_type(COAP_STRING, size);
-}
-
-/**
- * Wrapper function to coap_free_type() for backwards compatibility.
- */
-static inline void coap_free(void *object) {
-  coap_free_type(COAP_STRING, object);
-}
-
-#endif /* not WITH_LWIP */
-
-#ifdef WITH_LWIP
-
-#include <lwip/memp.h>
-
-/* no initialization needed with lwip (or, more precisely: lwip must be
- * completely initialized anyway by the time coap gets active)  */
-static inline void coap_memory_init(void) {}
-
-/* It would be nice to check that size equals the size given at the memp
- * declaration, but i currently don't see a standard way to check that without
- * sourcing the custom memp pools and becoming dependent of its syntax
- */
-#define coap_malloc_type(type, size) memp_malloc(MEMP_ ## type)
-#define coap_free_type(type, p) memp_free(MEMP_ ## type, p)
-
-/* Those are just here to make uri.c happy where string allocation has not been
- * made conditional.
- */
-static inline void *coap_malloc(size_t size) {
-  LWIP_ASSERT("coap_malloc must not be used in lwIP", 0);
-}
-
-static inline void coap_free(void *pointer) {
-  LWIP_ASSERT("coap_free must not be used in lwIP", 0);
-}
-
-#endif /* WITH_LWIP */
-
-#endif /* _COAP_MEM_H_ */
diff --git a/tools/sdk/include/coap/coap/net.h b/tools/sdk/include/coap/coap/net.h
deleted file mode 100644
index 014b4903ab4..00000000000
--- a/tools/sdk/include/coap/coap/net.h
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * net.h -- CoAP network interface
- *
- * Copyright (C) 2010-2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_NET_H_
-#define _COAP_NET_H_
-
-#include <assert.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/time.h>
-#include <time.h>
-
-#ifdef WITH_LWIP
-#include <lwip/ip_addr.h>
-#endif
-
-#include "coap_io.h"
-#include "coap_time.h"
-#include "option.h"
-#include "pdu.h"
-#include "prng.h"
-
-struct coap_queue_t;
-
-typedef struct coap_queue_t {
-  struct coap_queue_t *next;
-  coap_tick_t t;                /**< when to send PDU for the next time */
-  unsigned char retransmit_cnt; /**< retransmission counter, will be removed
-                                 *    when zero */
-  unsigned int timeout;         /**< the randomized timeout value */
-  coap_endpoint_t local_if;     /**< the local address interface */
-  coap_address_t remote;        /**< remote address */
-  coap_tid_t id;                /**< unique transaction id */
-  coap_pdu_t *pdu;              /**< the CoAP PDU to send */
-} coap_queue_t;
-
-/** Adds node to given queue, ordered by node->t. */
-int coap_insert_node(coap_queue_t **queue, coap_queue_t *node);
-
-/** Destroys specified node. */
-int coap_delete_node(coap_queue_t *node);
-
-/** Removes all items from given queue and frees the allocated storage. */
-void coap_delete_all(coap_queue_t *queue);
-
-/** Creates a new node suitable for adding to the CoAP sendqueue. */
-coap_queue_t *coap_new_node(void);
-
-struct coap_resource_t;
-struct coap_context_t;
-#ifndef WITHOUT_ASYNC
-struct coap_async_state_t;
-#endif
-
-/** Message handler that is used as call-back in coap_context_t */
-typedef void (*coap_response_handler_t)(struct coap_context_t  *,
-                                        const coap_endpoint_t *local_interface,
-                                        const coap_address_t *remote,
-                                        coap_pdu_t *sent,
-                                        coap_pdu_t *received,
-                                        const coap_tid_t id);
-
-#define COAP_MID_CACHE_SIZE 3
-typedef struct {
-  unsigned char flags[COAP_MID_CACHE_SIZE];
-  coap_key_t item[COAP_MID_CACHE_SIZE];
-} coap_mid_cache_t;
-
-/** The CoAP stack's global state is stored in a coap_context_t object */
-typedef struct coap_context_t {
-  coap_opt_filter_t known_options;
-  struct coap_resource_t *resources; /**< hash table or list of known resources */
-
-#ifndef WITHOUT_ASYNC
-  /**
-   * list of asynchronous transactions */
-  struct coap_async_state_t *async_state;
-#endif /* WITHOUT_ASYNC */
-
-  /**
-   * The time stamp in the first element of the sendqeue is relative
-   * to sendqueue_basetime. */
-  coap_tick_t sendqueue_basetime;
-  coap_queue_t *sendqueue;
-  coap_endpoint_t *endpoint;      /**< the endpoint used for listening  */
-
-#ifdef WITH_POSIX
-  int sockfd;                     /**< send/receive socket */
-#endif /* WITH_POSIX */
-
-#ifdef WITH_CONTIKI
-  struct uip_udp_conn *conn;      /**< uIP connection object */
-  struct etimer retransmit_timer; /**< fires when the next packet must be sent */
-  struct etimer notify_timer;     /**< used to check resources periodically */
-#endif /* WITH_CONTIKI */
-
-#ifdef WITH_LWIP
-  uint8_t timer_configured;       /**< Set to 1 when a retransmission is
-                                   *   scheduled using lwIP timers for this
-                                   *   context, otherwise 0. */
-#endif /* WITH_LWIP */
-
-  /**
-   * The last message id that was used is stored in this field. The initial
-   * value is set by coap_new_context() and is usually a random value. A new
-   * message id can be created with coap_new_message_id().
-   */
-  unsigned short message_id;
-
-  /**
-   * The next value to be used for Observe. This field is global for all
-   * resources and will be updated when notifications are created.
-   */
-  unsigned int observe;
-
-  coap_response_handler_t response_handler;
-
-  ssize_t (*network_send)(struct coap_context_t *context,
-                          const coap_endpoint_t *local_interface,
-                          const coap_address_t *dst,
-                          unsigned char *data, size_t datalen);
-
-  ssize_t (*network_read)(coap_endpoint_t *ep, coap_packet_t **packet);
-
-} coap_context_t;
-
-/**
- * Registers a new message handler that is called whenever a response was
- * received that matches an ongoing transaction.
- *
- * @param context The context to register the handler for.
- * @param handler The response handler to register.
- */
-static inline void
-coap_register_response_handler(coap_context_t *context,
-                               coap_response_handler_t handler) {
-  context->response_handler = handler;
-}
-
-/**
- * Registers the option type @p type with the given context object @p ctx.
- *
- * @param ctx  The context to use.
- * @param type The option type to register.
- */
-inline static void
-coap_register_option(coap_context_t *ctx, unsigned char type) {
-  coap_option_setb(ctx->known_options, type);
-}
-
-/**
- * Set sendqueue_basetime in the given context object @p ctx to @p now. This
- * function returns the number of elements in the queue head that have timed
- * out.
- */
-unsigned int coap_adjust_basetime(coap_context_t *ctx, coap_tick_t now);
-
-/**
- * Returns the next pdu to send without removing from sendqeue.
- */
-coap_queue_t *coap_peek_next( coap_context_t *context );
-
-/**
- * Returns the next pdu to send and removes it from the sendqeue.
- */
-coap_queue_t *coap_pop_next( coap_context_t *context );
-
-/**
- * Creates a new coap_context_t object that will hold the CoAP stack status.
- */
-coap_context_t *coap_new_context(const coap_address_t *listen_addr);
-
-/**
- * Returns a new message id and updates @p context->message_id accordingly. The
- * message id is returned in network byte order to make it easier to read in
- * tracing tools.
- *
- * @param context The current coap_context_t object.
- *
- * @return        Incremented message id in network byte order.
- */
-static inline unsigned short
-coap_new_message_id(coap_context_t *context) {
-  context->message_id++;
-#ifndef WITH_CONTIKI
-  return htons(context->message_id);
-#else /* WITH_CONTIKI */
-  return uip_htons(context->message_id);
-#endif
-}
-
-/**
- * CoAP stack context must be released with coap_free_context(). This function
- * clears all entries from the receive queue and send queue and deletes the
- * resources that have been registered with @p context, and frees the attached
- * endpoints.
- */
-void coap_free_context(coap_context_t *context);
-
-
-/**
- * Sends a confirmed CoAP message to given destination. The memory that is
- * allocated by pdu will not be released by coap_send_confirmed(). The caller
- * must release the memory.
- *
- * @param context         The CoAP context to use.
- * @param local_interface The local network interface where the outbound
- *                        packet is sent.
- * @param dst             The address to send to.
- * @param pdu             The CoAP PDU to send.
- *
- * @return                The message id of the sent message or @c
- *                        COAP_INVALID_TID on error.
- */
-coap_tid_t coap_send_confirmed(coap_context_t *context,
-                               const coap_endpoint_t *local_interface,
-                               const coap_address_t *dst,
-                               coap_pdu_t *pdu);
-
-/**
- * Creates a new ACK PDU with specified error @p code. The options specified by
- * the filter expression @p opts will be copied from the original request
- * contained in @p request. Unless @c SHORT_ERROR_RESPONSE was defined at build
- * time, the textual reason phrase for @p code will be added as payload, with
- * Content-Type @c 0.
- * This function returns a pointer to the new response message, or @c NULL on
- * error. The storage allocated for the new message must be relased with
- * coap_free().
- *
- * @param request Specification of the received (confirmable) request.
- * @param code    The error code to set.
- * @param opts    An option filter that specifies which options to copy from
- *                the original request in @p node.
- *
- * @return        A pointer to the new message or @c NULL on error.
- */
-coap_pdu_t *coap_new_error_response(coap_pdu_t *request,
-                                    unsigned char code,
-                                    coap_opt_filter_t opts);
-
-/**
- * Sends a non-confirmed CoAP message to given destination. The memory that is
- * allocated by pdu will not be released by coap_send().
- * The caller must release the memory.
- *
- * @param context         The CoAP context to use.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             The address to send to.
- * @param pdu             The CoAP PDU to send.
- *
- * @return                The message id of the sent message or @c
- *                        COAP_INVALID_TID on error.
- */
-coap_tid_t coap_send(coap_context_t *context,
-                     const coap_endpoint_t *local_interface,
-                     const coap_address_t *dst,
-                     coap_pdu_t *pdu);
-
-/**
- * Sends an error response with code @p code for request @p request to @p dst.
- * @p opts will be passed to coap_new_error_response() to copy marked options
- * from the request. This function returns the transaction id if the message was
- * sent, or @c COAP_INVALID_TID otherwise.
- *
- * @param context         The context to use.
- * @param request         The original request to respond to.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             The remote peer that sent the request.
- * @param code            The response code.
- * @param opts            A filter that specifies the options to copy from the
- *                        @p request.
- *
- * @return                The transaction id if the message was sent, or @c
- *                        COAP_INVALID_TID otherwise.
- */
-coap_tid_t coap_send_error(coap_context_t *context,
-                           coap_pdu_t *request,
-                           const coap_endpoint_t *local_interface,
-                           const coap_address_t *dst,
-                           unsigned char code,
-                           coap_opt_filter_t opts);
-
-/**
- * Helper funktion to create and send a message with @p type (usually ACK or
- * RST). This function returns @c COAP_INVALID_TID when the message was not
- * sent, a valid transaction id otherwise.
- *
- * @param  context        The CoAP context.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             Where to send the context.
- * @param request         The request that should be responded to.
- * @param type            Which type to set.
- * @return                transaction id on success or @c COAP_INVALID_TID
- *                        otherwise.
- */
-coap_tid_t
-coap_send_message_type(coap_context_t *context,
-                       const coap_endpoint_t *local_interface,
-                       const coap_address_t *dst,
-                       coap_pdu_t *request,
-                       unsigned char type);
-
-/**
- * Sends an ACK message with code @c 0 for the specified @p request to @p dst.
- * This function returns the corresponding transaction id if the message was
- * sent or @c COAP_INVALID_TID on error.
- *
- * @param context         The context to use.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             The destination address.
- * @param request         The request to be acknowledged.
- *
- * @return                The transaction id if ACK was sent or @c
- *                        COAP_INVALID_TID on error.
- */
-coap_tid_t coap_send_ack(coap_context_t *context,
-                         const coap_endpoint_t *local_interface,
-                         const coap_address_t *dst,
-                         coap_pdu_t *request);
-
-/**
- * Sends an RST message with code @c 0 for the specified @p request to @p dst.
- * This function returns the corresponding transaction id if the message was
- * sent or @c COAP_INVALID_TID on error.
- *
- * @param context         The context to use.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             The destination address.
- * @param request         The request to be reset.
- *
- * @return                The transaction id if RST was sent or @c
- *                        COAP_INVALID_TID on error.
- */
-static inline coap_tid_t
-coap_send_rst(coap_context_t *context,
-              const coap_endpoint_t *local_interface,
-              const coap_address_t *dst,
-              coap_pdu_t *request) {
-  return coap_send_message_type(context,
-                                local_interface,
-                                dst, request,
-                                COAP_MESSAGE_RST);
-}
-
-/**
- * Handles retransmissions of confirmable messages
- */
-coap_tid_t coap_retransmit(coap_context_t *context, coap_queue_t *node);
-
-/**
- * Reads data from the network and tries to parse as CoAP PDU. On success, 0 is
- * returned and a new node with the parsed PDU is added to the receive queue in
- * the specified context object.
- */
-int coap_read(coap_context_t *context);
-
-/**
- * Parses and interprets a CoAP message with context @p ctx. This function
- * returns @c 0 if the message was handled, or a value less than zero on
- * error.
- *
- * @param ctx    The current CoAP context.
- * @param packet The received packet.
- *
- * @return       @c 0 if message was handled successfully, or less than zero on
- *               error.
- */
-int coap_handle_message(coap_context_t *ctx,
-                        coap_packet_t *packet);
-
-/**
- * Calculates a unique transaction id from given arguments @p peer and @p pdu.
- * The id is returned in @p id.
- *
- * @param peer The remote party who sent @p pdu.
- * @param pdu  The message that initiated the transaction.
- * @param id   Set to the new id.
- */
-void coap_transaction_id(const coap_address_t *peer,
-                         const coap_pdu_t *pdu,
-                         coap_tid_t *id);
-
-/**
- * This function removes the element with given @p id from the list given list.
- * If @p id was found, @p node is updated to point to the removed element. Note
- * that the storage allocated by @p node is @b not released. The caller must do
- * this manually using coap_delete_node(). This function returns @c 1 if the
- * element with id @p id was found, @c 0 otherwise. For a return value of @c 0,
- * the contents of @p node is undefined.
- *
- * @param queue The queue to search for @p id.
- * @param id    The node id to look for.
- * @param node  If found, @p node is updated to point to the removed node. You
- *              must release the storage pointed to by @p node manually.
- *
- * @return      @c 1 if @p id was found, @c 0 otherwise.
- */
-int coap_remove_from_queue(coap_queue_t **queue,
-                           coap_tid_t id,
-                           coap_queue_t **node);
-
-/**
- * Removes the transaction identified by @p id from given @p queue. This is a
- * convenience function for coap_remove_from_queue() with automatic deletion of
- * the removed node.
- *
- * @param queue The queue to search for @p id.
- * @param id    The transaction id.
- *
- * @return      @c 1 if node was found, removed and destroyed, @c 0 otherwise.
- */
-inline static int
-coap_remove_transaction(coap_queue_t **queue, coap_tid_t id) {
-  coap_queue_t *node;
-  if (!coap_remove_from_queue(queue, id, &node))
-    return 0;
-
-  coap_delete_node(node);
-  return 1;
-}
-
-/**
- * Retrieves transaction from the queue.
- *
- * @param queue The transaction queue to be searched.
- * @param id    Unique key of the transaction to find.
- *
- * @return      A pointer to the transaction object or NULL if not found.
- */
-coap_queue_t *coap_find_transaction(coap_queue_t *queue, coap_tid_t id);
-
-/**
- * Cancels all outstanding messages for peer @p dst that have the specified
- * token.
- *
- * @param context      The context in use.
- * @param dst          Destination address of the messages to remove.
- * @param token        Message token.
- * @param token_length Actual length of @p token.
- */
-void coap_cancel_all_messages(coap_context_t *context,
-                              const coap_address_t *dst,
-                              const unsigned char *token,
-                              size_t token_length);
-
-/**
- * Dispatches the PDUs from the receive queue in given context.
- */
-void coap_dispatch(coap_context_t *context, coap_queue_t *rcvd);
-
-/**
- * Returns 1 if there are no messages to send or to dispatch in the context's
- * queues. */
-int coap_can_exit(coap_context_t *context);
-
-/**
- * Returns the current value of an internal tick counter. The counter counts \c
- * COAP_TICKS_PER_SECOND ticks every second.
- */
-void coap_ticks(coap_tick_t *);
-
-/**
- * Verifies that @p pdu contains no unknown critical options. Options must be
- * registered at @p ctx, using the function coap_register_option(). A basic set
- * of options is registered automatically by coap_new_context(). This function
- * returns @c 1 if @p pdu is ok, @c 0 otherwise. The given filter object @p
- * unknown will be updated with the unknown options. As only @c COAP_MAX_OPT
- * options can be signalled this way, remaining options must be examined
- * manually.
- *
- * @code
-  coap_opt_filter_t f = COAP_OPT_NONE;
-  coap_opt_iterator_t opt_iter;
-
-  if (coap_option_check_critical(ctx, pdu, f) == 0) {
-    coap_option_iterator_init(pdu, &opt_iter, f);
-
-    while (coap_option_next(&opt_iter)) {
-      if (opt_iter.type & 0x01) {
-        ... handle unknown critical option in opt_iter ...
-      }
-    }
-  }
- * @endcode
- *
- * @param ctx      The context where all known options are registered.
- * @param pdu      The PDU to check.
- * @param unknown  The output filter that will be updated to indicate the
- *                 unknown critical options found in @p pdu.
- *
- * @return         @c 1 if everything was ok, @c 0 otherwise.
- */
-int coap_option_check_critical(coap_context_t *ctx,
-                               coap_pdu_t *pdu,
-                               coap_opt_filter_t unknown);
-
-/**
- * Creates a new response for given @p request with the contents of @c
- * .well-known/core. The result is NULL on error or a newly allocated PDU that
- * must be released by coap_delete_pdu().
- *
- * @param context The current coap context to use.
- * @param request The request for @c .well-known/core .
- *
- * @return        A new 2.05 response for @c .well-known/core or NULL on error.
- */
-coap_pdu_t *coap_wellknown_response(coap_context_t *context,
-                                    coap_pdu_t *request);
-
-#endif /* _COAP_NET_H_ */
diff --git a/tools/sdk/include/coap/coap/option.h b/tools/sdk/include/coap/coap/option.h
deleted file mode 100644
index ace2b81c713..00000000000
--- a/tools/sdk/include/coap/coap/option.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * option.h -- helpers for handling options in CoAP PDUs
- *
- * Copyright (C) 2010-2013 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file option.h
- * @brief Helpers for handling options in CoAP PDUs
- */
-
-#ifndef _COAP_OPTION_H_
-#define _COAP_OPTION_H_
-
-#include "bits.h"
-#include "pdu.h"
-
-/**
- * Use byte-oriented access methods here because sliding a complex struct
- * coap_opt_t over the data buffer may cause bus error on certain platforms.
- */
-typedef unsigned char coap_opt_t;
-#define PCHAR(p) ((coap_opt_t *)(p))
-
-/** Representation of CoAP options. */
-typedef struct {
-  unsigned short delta;
-  size_t length;
-  unsigned char *value;
-} coap_option_t;
-
-/**
- * Parses the option pointed to by @p opt into @p result. This function returns
- * the number of bytes that have been parsed, or @c 0 on error. An error is
- * signaled when illegal delta or length values are encountered or when option
- * parsing would result in reading past the option (i.e. beyond opt + length).
- *
- * @param opt    The beginning of the option to parse.
- * @param length The maximum length of @p opt.
- * @param result A pointer to the coap_option_t structure that is filled with
- *               actual values iff coap_opt_parse() > 0.
- * @return       The number of bytes parsed or @c 0 on error.
- */
-size_t coap_opt_parse(const coap_opt_t *opt,
-                      size_t length,
-                      coap_option_t *result);
-
-/**
- * Returns the size of the given option, taking into account a possible option
- * jump.
- *
- * @param opt An option jump or the beginning of the option.
- * @return    The number of bytes between @p opt and the end of the option
- *            starting at @p opt. In case of an error, this function returns
- *            @c 0 as options need at least one byte storage space.
- */
-size_t coap_opt_size(const coap_opt_t *opt);
-
-/** @deprecated { Use coap_opt_size() instead. } */
-#define COAP_OPT_SIZE(opt) coap_opt_size(opt)
-
-/**
- * Calculates the beginning of the PDU's option section.
- *
- * @param pdu The PDU containing the options.
- * @return    A pointer to the first option if available, or @c NULL otherwise.
- */
-coap_opt_t *options_start(coap_pdu_t *pdu);
-
-/**
- * Interprets @p opt as pointer to a CoAP option and advances to
- * the next byte past this option.
- * @hideinitializer
- */
-#define options_next(opt) \
-  ((coap_opt_t *)((unsigned char *)(opt) + COAP_OPT_SIZE(opt)))
-
-/**
- * @defgroup opt_filter Option Filters
- * @{
- */
-
-/**
- * The number of option types below 256 that can be stored in an
- * option filter. COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG must be
- * at most 16. Each coap_option_filter_t object reserves
- * ((COAP_OPT_FILTER_SHORT + 1) / 2) * 2 bytes for short options.
- */
-#define COAP_OPT_FILTER_SHORT 6
-
-/**
- * The number of option types above 255 that can be stored in an
- * option filter. COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG must be
- * at most 16. Each coap_option_filter_t object reserves
- * COAP_OPT_FILTER_LONG * 2 bytes for short options.
- */
-#define COAP_OPT_FILTER_LONG  2
-
-/* Ensure that COAP_OPT_FILTER_SHORT and COAP_OPT_FILTER_LONG are set
- * correctly. */
-#if (COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG > 16)
-#error COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG must be less or equal 16
-#endif /* (COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG > 16) */
-
-/** The number of elements in coap_opt_filter_t. */
-#define COAP_OPT_FILTER_SIZE					\
-  (((COAP_OPT_FILTER_SHORT + 1) >> 1) + COAP_OPT_FILTER_LONG) +1
-
-/**
- * Fixed-size vector we use for option filtering. It is large enough
- * to hold COAP_OPT_FILTER_SHORT entries with an option number between
- * 0 and 255, and COAP_OPT_FILTER_LONG entries with an option number
- * between 256 and 65535. Its internal structure is
- *
- * @code
-struct {
-  uint16_t mask;
-  uint16_t long_opts[COAP_OPT_FILTER_LONG];
-  uint8_t short_opts[COAP_OPT_FILTER_SHORT];
-}
- * @endcode
- *
- * The first element contains a bit vector that indicates which fields
- * in the remaining array are used. The first COAP_OPT_FILTER_LONG
- * bits correspond to the long option types that are stored in the
- * elements from index 1 to COAP_OPT_FILTER_LONG. The next
- * COAP_OPT_FILTER_SHORT bits correspond to the short option types
- * that are stored in the elements from index COAP_OPT_FILTER_LONG + 1
- * to COAP_OPT_FILTER_LONG + COAP_OPT_FILTER_SHORT. The latter
- * elements are treated as bytes.
- */
-typedef uint16_t coap_opt_filter_t[COAP_OPT_FILTER_SIZE];
-
-/** Pre-defined filter that includes all options. */
-#define COAP_OPT_ALL NULL
-
-/**
- * Clears filter @p f.
- *
- * @param f The filter to clear.
- */
-static inline void
-coap_option_filter_clear(coap_opt_filter_t f) {
-  memset(f, 0, sizeof(coap_opt_filter_t));
-}
-
-/**
- * Sets the corresponding entry for @p type in @p filter. This
- * function returns @c 1 if bit was set or @c 0 on error (i.e. when
- * the given type does not fit in the filter).
- *
- * @param filter The filter object to change.
- * @param type   The type for which the bit should be set.
- *
- * @return       @c 1 if bit was set, @c 0 otherwise.
- */
-int coap_option_filter_set(coap_opt_filter_t filter, unsigned short type);
-
-/**
- * Clears the corresponding entry for @p type in @p filter. This
- * function returns @c 1 if bit was set or @c 0 on error (i.e. when
- * the given type does not fit in the filter).
- *
- * @param filter The filter object to change.
- * @param type   The type that should be cleared from the filter.
- *
- * @return       @c 1 if bit was set, @c 0 otherwise.
- */
-int coap_option_filter_unset(coap_opt_filter_t filter, unsigned short type);
-
-/**
- * Checks if @p type is contained in @p filter. This function returns
- * @c 1 if found, @c 0 if not, or @c -1 on error (i.e. when the given
- * type does not fit in the filter).
- *
- * @param filter The filter object to search.
- * @param type   The type to search for.
- *
- * @return       @c 1 if @p type was found, @c 0 otherwise, or @c -1 on error.
- */
-int coap_option_filter_get(const coap_opt_filter_t filter, unsigned short type);
-
-/**
- * Sets the corresponding bit for @p type in @p filter. This function returns @c
- * 1 if bit was set or @c -1 on error (i.e. when the given type does not fit in
- * the filter).
- *
- * @deprecated Use coap_option_filter_set() instead.
- *
- * @param filter The filter object to change.
- * @param type   The type for which the bit should be set.
- *
- * @return       @c 1 if bit was set, @c -1 otherwise.
- */
-inline static int
-coap_option_setb(coap_opt_filter_t filter, unsigned short type) {
-  return coap_option_filter_set(filter, type) ? 1 : -1;
-}
-
-/**
- * Clears the corresponding bit for @p type in @p filter. This function returns
- * @c 1 if bit was cleared or @c -1 on error (i.e. when the given type does not
- * fit in the filter).
- *
- * @deprecated Use coap_option_filter_unset() instead.
- *
- * @param filter The filter object to change.
- * @param type   The type for which the bit should be cleared.
- *
- * @return       @c 1 if bit was set, @c -1 otherwise.
- */
-inline static int
-coap_option_clrb(coap_opt_filter_t filter, unsigned short type) {
-  return coap_option_filter_unset(filter, type) ? 1 : -1;
-}
-
-/**
- * Gets the corresponding bit for @p type in @p filter. This function returns @c
- * 1 if the bit is set @c 0 if not, or @c -1 on error (i.e. when the given type
- * does not fit in the filter).
- *
- * @deprecated Use coap_option_filter_get() instead.
- *
- * @param filter The filter object to read bit from.
- * @param type   The type for which the bit should be read.
- *
- * @return       @c 1 if bit was set, @c 0 if not, @c -1 on error.
- */
-inline static int
-coap_option_getb(const coap_opt_filter_t filter, unsigned short type) {
-  return coap_option_filter_get(filter, type);
-}
-
-/**
- * Iterator to run through PDU options. This object must be
- * initialized with coap_option_iterator_init(). Call
- * coap_option_next() to walk through the list of options until
- * coap_option_next() returns @c NULL.
- *
- * @code
- * coap_opt_t *option;
- * coap_opt_iterator_t opt_iter;
- * coap_option_iterator_init(pdu, &opt_iter, COAP_OPT_ALL);
- *
- * while ((option = coap_option_next(&opt_iter))) {
- *   ... do something with option ...
- * }
- * @endcode
- */
-typedef struct {
-  size_t length;                /**< remaining length of PDU */
-  unsigned short type;          /**< decoded option type */
-  unsigned int bad:1;           /**< iterator object is ok if not set */
-  unsigned int filtered:1;      /**< denotes whether or not filter is used */
-  coap_opt_t *next_option;      /**< pointer to the unparsed next option */
-  coap_opt_filter_t filter;     /**< option filter */
-} coap_opt_iterator_t;
-
-/**
- * Initializes the given option iterator @p oi to point to the beginning of the
- * @p pdu's option list. This function returns @p oi on success, @c NULL
- * otherwise (i.e. when no options exist). Note that a length check on the
- * option list must be performed before coap_option_iterator_init() is called.
- *
- * @param pdu    The PDU the options of which should be walked through.
- * @param oi     An iterator object that will be initilized.
- * @param filter An optional option type filter.
- *               With @p type != @c COAP_OPT_ALL, coap_option_next()
- *               will return only options matching this bitmask.
- *               Fence-post options @c 14, @c 28, @c 42, ... are always
- *               skipped.
- *
- * @return       The iterator object @p oi on success, @c NULL otherwise.
- */
-coap_opt_iterator_t *coap_option_iterator_init(coap_pdu_t *pdu,
-                                               coap_opt_iterator_t *oi,
-                                               const coap_opt_filter_t filter);
-
-/**
- * Updates the iterator @p oi to point to the next option. This function returns
- * a pointer to that option or @c NULL if no more options exist. The contents of
- * @p oi will be updated. In particular, @c oi->n specifies the current option's
- * ordinal number (counted from @c 1), @c oi->type is the option's type code,
- * and @c oi->option points to the beginning of the current option itself. When
- * advanced past the last option, @c oi->option will be @c NULL.
- *
- * Note that options are skipped whose corresponding bits in the filter
- * specified with coap_option_iterator_init() are @c 0. Options with type codes
- * that do not fit in this filter hence will always be returned.
- *
- * @param oi The option iterator to update.
- *
- * @return   The next option or @c NULL if no more options exist.
- */
-coap_opt_t *coap_option_next(coap_opt_iterator_t *oi);
-
-/**
- * Retrieves the first option of type @p type from @p pdu. @p oi must point to a
- * coap_opt_iterator_t object that will be initialized by this function to
- * filter only options with code @p type. This function returns the first option
- * with this type, or @c NULL if not found.
- *
- * @param pdu  The PDU to parse for options.
- * @param type The option type code to search for.
- * @param oi   An iterator object to use.
- *
- * @return     A pointer to the first option of type @p type, or @c NULL if
- *             not found.
- */
-coap_opt_t *coap_check_option(coap_pdu_t *pdu,
-                              unsigned short type,
-                              coap_opt_iterator_t *oi);
-
-/**
- * Encodes the given delta and length values into @p opt. This function returns
- * the number of bytes that were required to encode @p delta and @p length or @c
- * 0 on error. Note that the result indicates by how many bytes @p opt must be
- * advanced to encode the option value.
- *
- * @param opt    The option buffer space where @p delta and @p length are
- *               written.
- * @param maxlen The maximum length of @p opt.
- * @param delta  The actual delta value to encode.
- * @param length The actual length value to encode.
- *
- * @return       The number of bytes used or @c 0 on error.
- */
-size_t coap_opt_setheader(coap_opt_t *opt,
-                          size_t maxlen,
-                          unsigned short delta,
-                          size_t length);
-
-/**
- * Encodes option with given @p delta into @p opt. This function returns the
- * number of bytes written to @p opt or @c 0 on error. This happens especially
- * when @p opt does not provide sufficient space to store the option value,
- * delta, and option jumps when required.
- *
- * @param opt    The option buffer space where @p val is written.
- * @param n      Maximum length of @p opt.
- * @param delta  The option delta.
- * @param val    The option value to copy into @p opt.
- * @param length The actual length of @p val.
- *
- * @return       The number of bytes that have been written to @p opt or @c 0 on
- *               error. The return value will always be less than @p n.
- */
-size_t coap_opt_encode(coap_opt_t *opt,
-                       size_t n,
-                       unsigned short delta,
-                       const unsigned char *val,
-                       size_t length);
-
-/**
- * Decodes the delta value of the next option. This function returns the number
- * of bytes read or @c 0 on error. The caller of this function must ensure that
- * it does not read over the boundaries of @p opt (e.g. by calling
- * coap_opt_check_delta().
- *
- * @param opt The option to examine.
- *
- * @return    The number of bytes read or @c 0 on error.
- */
-unsigned short coap_opt_delta(const coap_opt_t *opt);
-
-/** @deprecated { Use coap_opt_delta() instead. } */
-#define COAP_OPT_DELTA(opt) coap_opt_delta(opt)
-
-/** @deprecated { Use coap_opt_encode() instead. } */
-#define COAP_OPT_SETDELTA(opt,val) \
-  coap_opt_encode((opt), COAP_MAX_PDU_SIZE, (val), NULL, 0)
-
-/**
- * Returns the length of the given option. @p opt must point to an option jump
- * or the beginning of the option. This function returns @c 0 when @p opt is not
- * an option or the actual length of @p opt (which can be @c 0 as well).
- *
- * @note {The rationale for using @c 0 in case of an error is that in most
- * contexts, the result of this function is used to skip the next
- * coap_opt_length() bytes.}
- *
- * @param opt  The option whose length should be returned.
- *
- * @return     The option's length or @c 0 when undefined.
- */
-unsigned short coap_opt_length(const coap_opt_t *opt);
-
-/** @deprecated { Use coap_opt_length() instead. } */
-#define COAP_OPT_LENGTH(opt) coap_opt_length(opt)
-
-/**
- * Returns a pointer to the value of the given option. @p opt must point to an
- * option jump or the beginning of the option. This function returns @c NULL if
- * @p opt is not a valid option.
- *
- * @param opt The option whose value should be returned.
- *
- * @return    A pointer to the option value or @c NULL on error.
- */
-unsigned char *coap_opt_value(coap_opt_t *opt);
-
-/** @deprecated { Use coap_opt_value() instead. } */
-#define COAP_OPT_VALUE(opt) coap_opt_value((coap_opt_t *)opt)
-
-/** @} */
-
-#endif /* _OPTION_H_ */
diff --git a/tools/sdk/include/coap/coap/pdu.h b/tools/sdk/include/coap/coap/pdu.h
deleted file mode 100644
index 7ed482deee0..00000000000
--- a/tools/sdk/include/coap/coap/pdu.h
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * pdu.h -- CoAP message structure
- *
- * Copyright (C) 2010-2014 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file pdu.h
- * @brief Pre-defined constants that reflect defaults for CoAP
- */
-
-#ifndef _COAP_PDU_H_
-#define _COAP_PDU_H_
-
-#include "uri.h"
-
-#ifdef WITH_LWIP
-#include <lwip/pbuf.h>
-#endif
-
-#define COAP_DEFAULT_PORT      5683 /* CoAP default UDP port */
-#define COAP_DEFAULT_MAX_AGE     60 /* default maximum object lifetime in seconds */
-#ifndef COAP_MAX_PDU_SIZE
-#define COAP_MAX_PDU_SIZE      1400 /* maximum size of a CoAP PDU */
-#endif /* COAP_MAX_PDU_SIZE */
-
-#define COAP_DEFAULT_VERSION      1 /* version of CoAP supported */
-#define COAP_DEFAULT_SCHEME  "coap" /* the default scheme for CoAP URIs */
-
-/** well-known resources URI */
-#define COAP_DEFAULT_URI_WELLKNOWN ".well-known/core"
-
-#ifdef __COAP_DEFAULT_HASH
-/* pre-calculated hash key for the default well-known URI */
-#define COAP_DEFAULT_WKC_HASHKEY   "\345\130\144\245"
-#endif
-
-/* CoAP message types */
-
-#define COAP_MESSAGE_CON       0 /* confirmable message (requires ACK/RST) */
-#define COAP_MESSAGE_NON       1 /* non-confirmable message (one-shot message) */
-#define COAP_MESSAGE_ACK       2 /* used to acknowledge confirmable messages */
-#define COAP_MESSAGE_RST       3 /* indicates error in received messages */
-
-/* CoAP request methods */
-
-#define COAP_REQUEST_GET       1
-#define COAP_REQUEST_POST      2
-#define COAP_REQUEST_PUT       3
-#define COAP_REQUEST_DELETE    4
-
-/* CoAP option types (be sure to update check_critical when adding options */
-
-#define COAP_OPTION_IF_MATCH        1 /* C, opaque, 0-8 B, (none) */
-#define COAP_OPTION_URI_HOST        3 /* C, String, 1-255 B, destination address */
-#define COAP_OPTION_ETAG            4 /* E, opaque, 1-8 B, (none) */
-#define COAP_OPTION_IF_NONE_MATCH   5 /* empty, 0 B, (none) */
-#define COAP_OPTION_URI_PORT        7 /* C, uint, 0-2 B, destination port */
-#define COAP_OPTION_LOCATION_PATH   8 /* E, String, 0-255 B, - */
-#define COAP_OPTION_URI_PATH       11 /* C, String, 0-255 B, (none) */
-#define COAP_OPTION_CONTENT_FORMAT 12 /* E, uint, 0-2 B, (none) */
-#define COAP_OPTION_CONTENT_TYPE COAP_OPTION_CONTENT_FORMAT
-#define COAP_OPTION_MAXAGE         14 /* E, uint, 0--4 B, 60 Seconds */
-#define COAP_OPTION_URI_QUERY      15 /* C, String, 1-255 B, (none) */
-#define COAP_OPTION_ACCEPT         17 /* C, uint,   0-2 B, (none) */
-#define COAP_OPTION_LOCATION_QUERY 20 /* E, String,   0-255 B, (none) */
-#define COAP_OPTION_PROXY_URI      35 /* C, String, 1-1034 B, (none) */
-#define COAP_OPTION_PROXY_SCHEME   39 /* C, String, 1-255 B, (none) */
-#define COAP_OPTION_SIZE1          60 /* E, uint, 0-4 B, (none) */
-
-/* option types from RFC 7641 */
-
-#define COAP_OPTION_OBSERVE         6 /* E, empty/uint, 0 B/0-3 B, (none) */
-#define COAP_OPTION_SUBSCRIPTION  COAP_OPTION_OBSERVE
-
-/* selected option types from RFC 7959 */
-
-#define COAP_OPTION_BLOCK2         23 /* C, uint, 0--3 B, (none) */
-#define COAP_OPTION_BLOCK1         27 /* C, uint, 0--3 B, (none) */
-
-/* selected option types from RFC 7967 */
-
-#define COAP_OPTION_NORESPONSE    258 /* N, uint, 0--1 B, 0 */
-
-#define COAP_MAX_OPT            65535 /**< the highest option number we know */
-
-/* CoAP result codes (HTTP-Code / 100 * 40 + HTTP-Code % 100) */
-
-/* As of draft-ietf-core-coap-04, response codes are encoded to base
- * 32, i.e.  the three upper bits determine the response class while
- * the remaining five fine-grained information specific to that class.
- */
-#define COAP_RESPONSE_CODE(N) (((N)/100 << 5) | (N)%100)
-
-/* Determines the class of response code C */
-#define COAP_RESPONSE_CLASS(C) (((C) >> 5) & 0xFF)
-
-#ifndef SHORT_ERROR_RESPONSE
-/**
- * Returns a human-readable response phrase for the specified CoAP response @p
- * code. This function returns @c NULL if not found.
- *
- * @param code The response code for which the literal phrase should be
- *             retrieved.
- *
- * @return     A zero-terminated string describing the error, or @c NULL if not
- *             found.
- */
-char *coap_response_phrase(unsigned char code);
-
-#define COAP_ERROR_PHRASE_LENGTH   32 /**< maximum length of error phrase */
-
-#else
-#define coap_response_phrase(x) ((char *)NULL)
-
-#define COAP_ERROR_PHRASE_LENGTH    0 /**< maximum length of error phrase */
-#endif /* SHORT_ERROR_RESPONSE */
-
-/* The following definitions exist for backwards compatibility */
-#if 0 /* this does not exist any more */
-#define COAP_RESPONSE_100      40 /* 100 Continue */
-#endif
-#define COAP_RESPONSE_200      COAP_RESPONSE_CODE(200)  /* 2.00 OK */
-#define COAP_RESPONSE_201      COAP_RESPONSE_CODE(201)  /* 2.01 Created */
-#define COAP_RESPONSE_304      COAP_RESPONSE_CODE(203)  /* 2.03 Valid */
-#define COAP_RESPONSE_400      COAP_RESPONSE_CODE(400)  /* 4.00 Bad Request */
-#define COAP_RESPONSE_404      COAP_RESPONSE_CODE(404)  /* 4.04 Not Found */
-#define COAP_RESPONSE_405      COAP_RESPONSE_CODE(405)  /* 4.05 Method Not Allowed */
-#define COAP_RESPONSE_415      COAP_RESPONSE_CODE(415)  /* 4.15 Unsupported Media Type */
-#define COAP_RESPONSE_500      COAP_RESPONSE_CODE(500)  /* 5.00 Internal Server Error */
-#define COAP_RESPONSE_501      COAP_RESPONSE_CODE(501)  /* 5.01 Not Implemented */
-#define COAP_RESPONSE_503      COAP_RESPONSE_CODE(503)  /* 5.03 Service Unavailable */
-#define COAP_RESPONSE_504      COAP_RESPONSE_CODE(504)  /* 5.04 Gateway Timeout */
-#if 0  /* these response codes do not have a valid code any more */
-#  define COAP_RESPONSE_X_240    240   /* Token Option required by server */
-#  define COAP_RESPONSE_X_241    241   /* Uri-Authority Option required by server */
-#endif
-#define COAP_RESPONSE_X_242    COAP_RESPONSE_CODE(402)  /* Critical Option not supported */
-
-/* CoAP media type encoding */
-
-#define COAP_MEDIATYPE_TEXT_PLAIN                 0 /* text/plain (UTF-8) */
-#define COAP_MEDIATYPE_APPLICATION_LINK_FORMAT   40 /* application/link-format */
-#define COAP_MEDIATYPE_APPLICATION_XML           41 /* application/xml */
-#define COAP_MEDIATYPE_APPLICATION_OCTET_STREAM  42 /* application/octet-stream */
-#define COAP_MEDIATYPE_APPLICATION_RDF_XML       43 /* application/rdf+xml */
-#define COAP_MEDIATYPE_APPLICATION_EXI           47 /* application/exi  */
-#define COAP_MEDIATYPE_APPLICATION_JSON          50 /* application/json  */
-#define COAP_MEDIATYPE_APPLICATION_CBOR          60 /* application/cbor  */
-
-/* Note that identifiers for registered media types are in the range 0-65535. We
- * use an unallocated type here and hope for the best. */
-#define COAP_MEDIATYPE_ANY                         0xff /* any media type */
-
-/**
- * coap_tid_t is used to store CoAP transaction id, i.e. a hash value
- * built from the remote transport address and the message id of a
- * CoAP PDU.  Valid transaction ids are greater or equal zero.
- */
-typedef int coap_tid_t;
-
-/** Indicates an invalid transaction id. */
-#define COAP_INVALID_TID -1
-
-/**
- * Indicates that a response is suppressed. This will occur for error
- * responses if the request was received via IP multicast.
- */
-#define COAP_DROPPED_RESPONSE -2
-
-#ifdef WORDS_BIGENDIAN
-typedef struct {
-  unsigned int version:2;      /* protocol version */
-  unsigned int type:2;         /* type flag */
-  unsigned int token_length:4; /* length of Token */
-  unsigned int code:8;         /* request method (value 1--10) or response
-                                  code (value 40-255) */
-  unsigned short id;           /* message id */
-  unsigned char token[];       /* the actual token, if any */
-} coap_hdr_t;
-#else
-typedef struct {
-  unsigned int token_length:4; /* length of Token */
-  unsigned int type:2;         /* type flag */
-  unsigned int version:2;      /* protocol version */
-  unsigned int code:8;         /* request method (value 1--10) or response
-                                  code (value 40-255) */
-  unsigned short id;           /* transaction id (network byte order!) */
-  unsigned char token[];       /* the actual token, if any */
-} coap_hdr_t;
-#endif
-
-#define COAP_MESSAGE_IS_EMPTY(MSG)    ((MSG)->code == 0)
-#define COAP_MESSAGE_IS_REQUEST(MSG)  (!COAP_MESSAGE_IS_EMPTY(MSG) \
-                                       && ((MSG)->code < 32))
-#define COAP_MESSAGE_IS_RESPONSE(MSG) ((MSG)->code >= 64)
-
-#define COAP_OPT_LONG 0x0F      /* OC == 0b1111 indicates that the option list
-                                 * in a CoAP message is limited by 0b11110000
-                                 * marker */
-
-#define COAP_OPT_END 0xF0       /* end marker */
-
-#define COAP_PAYLOAD_START 0xFF /* payload marker */
-
-/**
- * Structures for more convenient handling of options. (To be used with ordered
- * coap_list_t.) The option's data will be added to the end of the coap_option
- * structure (see macro COAP_OPTION_DATA).
- */
-typedef struct {
-  unsigned short key;           /* the option key (no delta coding) */
-  unsigned int length;
-} coap_option;
-
-#define COAP_OPTION_KEY(option) (option).key
-#define COAP_OPTION_LENGTH(option) (option).length
-#define COAP_OPTION_DATA(option) ((unsigned char *)&(option) + sizeof(coap_option))
-
-/**
- * Header structure for CoAP PDUs
- */
-
-typedef struct {
-  size_t max_size;          /**< allocated storage for options and data */
-  coap_hdr_t *hdr;          /**< Address of the first byte of the CoAP message.
-                             *   This may or may not equal (coap_hdr_t*)(pdu+1)
-                             *   depending on the memory management
-                             *   implementation. */
-  unsigned short max_delta; /**< highest option number */
-  unsigned short length;    /**< PDU length (including header, options, data) */
-  unsigned char *data;      /**< payload */
-
-#ifdef WITH_LWIP
-  struct pbuf *pbuf;        /**< lwIP PBUF. The package data will always reside
-                             *    inside the pbuf's payload, but this pointer
-                             *    has to be kept because no exact offset can be
-                             *    given. This field must not be accessed from
-                             *    outside, because the pbuf's reference count
-                             *    is checked to be 1 when the pbuf is assigned
-                             *    to the pdu, and the pbuf stays exclusive to
-                             *    this pdu. */
-#endif
-} coap_pdu_t;
-
-/**
- * Options in coap_pdu_t are accessed with the macro COAP_OPTION.
- */
-#define COAP_OPTION(node) ((coap_option *)(node)->options)
-
-#ifdef WITH_LWIP
-/**
- * Creates a CoAP PDU from an lwIP @p pbuf, whose reference is passed on to this
- * function.
- *
- * The pbuf is checked for being contiguous, and for having only one reference.
- * The reference is stored in the PDU and will be freed when the PDU is freed.
- *
- * (For now, these are fatal errors; in future, a new pbuf might be allocated,
- * the data copied and the passed pbuf freed).
- *
- * This behaves like coap_pdu_init(0, 0, 0, pbuf->tot_len), and afterwards
- * copying the contents of the pbuf to the pdu.
- *
- * @return A pointer to the new PDU object or @c NULL on error.
- */
-coap_pdu_t * coap_pdu_from_pbuf(struct pbuf *pbuf);
-#endif
-
-/**
- * Creates a new CoAP PDU of given @p size (must be large enough to hold the
- * basic CoAP message header (coap_hdr_t). The function returns a pointer to the
- * node coap_pdu_t object on success, or @c NULL on error. The storage allocated
- * for the result must be released with coap_delete_pdu().
- *
- * @param type The type of the PDU (one of COAP_MESSAGE_CON, COAP_MESSAGE_NON,
- *             COAP_MESSAGE_ACK, COAP_MESSAGE_RST).
- * @param code The message code.
- * @param id   The message id to set or COAP_INVALID_TID if unknown.
- * @param size The number of bytes to allocate for the actual message.
- *
- * @return     A pointer to the new PDU object or @c NULL on error.
- */
-coap_pdu_t *
-coap_pdu_init(unsigned char type,
-              unsigned char code,
-              unsigned short id,
-              size_t size);
-
-/**
- * Clears any contents from @p pdu and resets @c version field, @c
- * length and @c data pointers. @c max_size is set to @p size, any
- * other field is set to @c 0. Note that @p pdu must be a valid
- * pointer to a coap_pdu_t object created e.g. by coap_pdu_init().
- */
-void coap_pdu_clear(coap_pdu_t *pdu, size_t size);
-
-/**
- * Creates a new CoAP PDU.
- * The object is created on the heap and must be released using
- * coap_delete_pdu();
- *
- * @deprecated This function allocates the maximum storage for each
- * PDU. Use coap_pdu_init() instead.
- */
-coap_pdu_t *coap_new_pdu(void);
-
-void coap_delete_pdu(coap_pdu_t *);
-
-/**
- * Parses @p data into the CoAP PDU structure given in @p result.
- * This function returns @c 0 on error or a number greater than zero on success.
- *
- * @param data   The raw data to parse as CoAP PDU.
- * @param length The actual size of @p data.
- * @param result The PDU structure to fill. Note that the structure must
- *               provide space for at least @p length bytes to hold the
- *               entire CoAP PDU.
- *
- * @return       A value greater than zero on success or @c 0 on error.
- */
-int coap_pdu_parse(unsigned char *data,
-                   size_t length,
-                   coap_pdu_t *result);
-
-/**
- * Adds token of length @p len to @p pdu.
- * Adding the token destroys any following contents of the pdu. Hence options
- * and data must be added after coap_add_token() has been called. In @p pdu,
- * length is set to @p len + @c 4, and max_delta is set to @c 0. This funtion
- * returns @c 0 on error or a value greater than zero on success.
- *
- * @param pdu  The PDU where the token is to be added.
- * @param len  The length of the new token.
- * @param data The token to add.
- *
- * @return     A value greater than zero on success, or @c 0 on error.
- */
-int coap_add_token(coap_pdu_t *pdu,
-                  size_t len,
-                  const unsigned char *data);
-
-/**
- * Adds option of given type to pdu that is passed as first
- * parameter.
- * coap_add_option() destroys the PDU's data, so coap_add_data() must be called
- * after all options have been added. As coap_add_token() destroys the options
- * following the token, the token must be added before coap_add_option() is
- * called. This function returns the number of bytes written or @c 0 on error.
- */
-size_t coap_add_option(coap_pdu_t *pdu,
-                       unsigned short type,
-                       unsigned int len,
-                       const unsigned char *data);
-
-/**
- * Adds option of given type to pdu that is passed as first parameter, but does
- * not write a value. It works like coap_add_option with respect to calling
- * sequence (i.e. after token and before data). This function returns a memory
- * address to which the option data has to be written before the PDU can be
- * sent, or @c NULL on error.
- */
-unsigned char *coap_add_option_later(coap_pdu_t *pdu,
-                                     unsigned short type,
-                                     unsigned int len);
-
-/**
- * Adds given data to the pdu that is passed as first parameter. Note that the
- * PDU's data is destroyed by coap_add_option(). coap_add_data() must be called
- * only once per PDU, otherwise the result is undefined.
- */
-int coap_add_data(coap_pdu_t *pdu,
-                  unsigned int len,
-                  const unsigned char *data);
-
-/**
- * Retrieves the length and data pointer of specified PDU. Returns 0 on error or
- * 1 if *len and *data have correct values. Note that these values are destroyed
- * with the pdu.
- */
-int coap_get_data(coap_pdu_t *pdu,
-                  size_t *len,
-                  unsigned char **data);
-
-#endif /* _COAP_PDU_H_ */
diff --git a/tools/sdk/include/coap/coap/prng.h b/tools/sdk/include/coap/coap/prng.h
deleted file mode 100644
index da6d9534404..00000000000
--- a/tools/sdk/include/coap/coap/prng.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * prng.h -- Pseudo Random Numbers
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file prng.h
- * @brief Pseudo Random Numbers
- */
-
-#ifndef _COAP_PRNG_H_
-#define _COAP_PRNG_H_
-
-/**
- * @defgroup prng Pseudo Random Numbers
- * @{
- */
-
-#if defined(WITH_POSIX) || (defined(WITH_LWIP) && !defined(LWIP_RAND))
-#include <stdlib.h>
-
-/**
- * Fills \p buf with \p len random bytes. This is the default implementation for
- * prng(). You might want to change prng() to use a better PRNG on your specific
- * platform.
- */
-static inline int
-coap_prng_impl(unsigned char *buf, size_t len) {
-  while (len--)
-    *buf++ = rand() & 0xFF;
-  return 1;
-}
-#endif /* WITH_POSIX */
-
-#ifdef WITH_CONTIKI
-#include <string.h>
-
-/**
- * Fills \p buf with \p len random bytes. This is the default implementation for
- * prng(). You might want to change prng() to use a better PRNG on your specific
- * platform.
- */
-static inline int
-contiki_prng_impl(unsigned char *buf, size_t len) {
-  unsigned short v = random_rand();
-  while (len > sizeof(v)) {
-    memcpy(buf, &v, sizeof(v));
-    len -= sizeof(v);
-    buf += sizeof(v);
-    v = random_rand();
-  }
-
-  memcpy(buf, &v, len);
-  return 1;
-}
-
-#define prng(Buf,Length) contiki_prng_impl((Buf), (Length))
-#define prng_init(Value) random_init((unsigned short)(Value))
-#endif /* WITH_CONTIKI */
-
-#if defined(WITH_LWIP) && defined(LWIP_RAND)
-static inline int
-lwip_prng_impl(unsigned char *buf, size_t len) {
-  u32_t v = LWIP_RAND();
-  while (len > sizeof(v)) {
-    memcpy(buf, &v, sizeof(v));
-    len -= sizeof(v);
-    buf += sizeof(v);
-    v = LWIP_RAND();
-  }
-
-  memcpy(buf, &v, len);
-  return 1;
-}
-
-#define prng(Buf,Length) lwip_prng_impl((Buf), (Length))
-#define prng_init(Value)
-
-#endif /* WITH_LWIP */
-
-#ifndef prng
-/**
- * Fills \p Buf with \p Length bytes of random data.
- *
- * @hideinitializer
- */
-#define prng(Buf,Length) coap_prng_impl((Buf), (Length))
-#endif
-
-#ifndef prng_init
-/**
- * Called to set the PRNG seed. You may want to re-define this to allow for a
- * better PRNG.
- *
- * @hideinitializer
- */
-#define prng_init(Value) srand((unsigned long)(Value))
-#endif
-
-/** @} */
-
-#endif /* _COAP_PRNG_H_ */
diff --git a/tools/sdk/include/coap/coap/resource.h b/tools/sdk/include/coap/coap/resource.h
deleted file mode 100644
index dbb19a8d1f6..00000000000
--- a/tools/sdk/include/coap/coap/resource.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * resource.h -- generic resource handling
- *
- * Copyright (C) 2010,2011,2014,2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file resource.h
- * @brief Generic resource handling
- */
-
-#ifndef _COAP_RESOURCE_H_
-#define _COAP_RESOURCE_H_
-
-# include <assert.h>
-
-#ifndef COAP_RESOURCE_CHECK_TIME
-/** The interval in seconds to check if resources have changed. */
-#define COAP_RESOURCE_CHECK_TIME 2
-#endif /* COAP_RESOURCE_CHECK_TIME */
-
-#ifdef COAP_RESOURCES_NOHASH
-#  include "utlist.h"
-#else
-#  include "uthash.h"
-#endif
-
-#include "hashkey.h"
-#include "async.h"
-#include "str.h"
-#include "pdu.h"
-#include "net.h"
-#include "subscribe.h"
-
-/**
- * Definition of message handler function (@sa coap_resource_t).
- */
-typedef void (*coap_method_handler_t)
-  (coap_context_t  *,
-   struct coap_resource_t *,
-   const coap_endpoint_t *,
-   coap_address_t *,
-   coap_pdu_t *,
-   str * /* token */,
-   coap_pdu_t * /* response */);
-
-#define COAP_ATTR_FLAGS_RELEASE_NAME  0x1
-#define COAP_ATTR_FLAGS_RELEASE_VALUE 0x2
-
-typedef struct coap_attr_t {
-  struct coap_attr_t *next;
-  str name;
-  str value;
-  int flags;
-} coap_attr_t;
-
-/** The URI passed to coap_resource_init() is free'd by coap_delete_resource(). */
-#define COAP_RESOURCE_FLAGS_RELEASE_URI 0x1
-
-/**
- * Notifications will be sent non-confirmable by default. RFC 7641 Section 4.5
- * https://tools.ietf.org/html/rfc7641#section-4.5
- */
-#define COAP_RESOURCE_FLAGS_NOTIFY_NON  0x0
-
-/**
- * Notifications will be sent confirmable by default. RFC 7641 Section 4.5
- * https://tools.ietf.org/html/rfc7641#section-4.5
- */
-#define COAP_RESOURCE_FLAGS_NOTIFY_CON  0x2
-
-typedef struct coap_resource_t {
-  unsigned int dirty:1;          /**< set to 1 if resource has changed */
-  unsigned int partiallydirty:1; /**< set to 1 if some subscribers have not yet
-                                  *   been notified of the last change */
-  unsigned int observable:1;     /**< can be observed */
-  unsigned int cacheable:1;      /**< can be cached */
-
-  /**
-   * Used to store handlers for the four coap methods @c GET, @c POST, @c PUT,
-   * and @c DELETE. coap_dispatch() will pass incoming requests to the handler
-   * that corresponds to its request method or generate a 4.05 response if no
-   * handler is available.
-   */
-  coap_method_handler_t handler[4];
-
-  coap_key_t key;                /**< the actual key bytes for this resource */
-
-#ifdef COAP_RESOURCES_NOHASH
-  struct coap_resource_t *next;
-#else
-  UT_hash_handle hh;
-#endif
-
-  coap_attr_t *link_attr; /**< attributes to be included with the link format */
-  coap_subscription_t *subscribers;  /**< list of observers for this resource */
-
-  /**
-   * Request URI for this resource. This field will point into the static
-   * memory.
-   */
-  str uri;
-  int flags;
-
-} coap_resource_t;
-
-/**
- * Creates a new resource object and initializes the link field to the string
- * of length @p len. This function returns the new coap_resource_t object.
- *
- * @param uri    The URI path of the new resource.
- * @param len    The length of @p uri.
- * @param flags  Flags for memory management (in particular release of memory).
- *
- * @return       A pointer to the new object or @c NULL on error.
- */
-coap_resource_t *coap_resource_init(const unsigned char *uri,
-                                    size_t len, int flags);
-
-
-/**
- * Sets the notification message type of resource @p r to given
- * @p mode which must be one of @c COAP_RESOURCE_FLAGS_NOTIFY_NON
- * or @c COAP_RESOURCE_FLAGS_NOTIFY_CON.
- */
-static inline void
-coap_resource_set_mode(coap_resource_t *r, int mode) {
-  r->flags = (r->flags & !COAP_RESOURCE_FLAGS_NOTIFY_CON) | mode;
-}
-
-/**
- * Registers the given @p resource for @p context. The resource must have been
- * created by coap_resource_init(), the storage allocated for the resource will
- * be released by coap_delete_resource().
- *
- * @param context  The context to use.
- * @param resource The resource to store.
- */
-void coap_add_resource(coap_context_t *context, coap_resource_t *resource);
-
-/**
- * Deletes a resource identified by @p key. The storage allocated for that
- * resource is freed.
- *
- * @param context  The context where the resources are stored.
- * @param key      The unique key for the resource to delete.
- *
- * @return         @c 1 if the resource was found (and destroyed),
- *                 @c 0 otherwise.
- */
-int coap_delete_resource(coap_context_t *context, coap_key_t key);
-
-/**
- * Deletes all resources from given @p context and frees their storage.
- *
- * @param context The CoAP context with the resources to be deleted.
- */
-void coap_delete_all_resources(coap_context_t *context);
-
-/**
- * Registers a new attribute with the given @p resource. As the
- * attributes str fields will point to @p name and @p val the
- * caller must ensure that these pointers are valid during the
- * attribute's lifetime.
- *
- * @param resource The resource to register the attribute with.
- * @param name     The attribute's name.
- * @param nlen     Length of @p name.
- * @param val      The attribute's value or @c NULL if none.
- * @param vlen     Length of @p val if specified.
- * @param flags    Flags for memory management (in particular release of
- *                 memory).
- *
- * @return         A pointer to the new attribute or @c NULL on error.
- */
-coap_attr_t *coap_add_attr(coap_resource_t *resource,
-                           const unsigned char *name,
-                           size_t nlen,
-                           const unsigned char *val,
-                           size_t vlen,
-                           int flags);
-
-/**
- * Returns @p resource's coap_attr_t object with given @p name if found, @c NULL
- * otherwise.
- *
- * @param resource The resource to search for attribute @p name.
- * @param name     Name of the requested attribute.
- * @param nlen     Actual length of @p name.
- * @return         The first attribute with specified @p name or @c NULL if none
- *                 was found.
- */
-coap_attr_t *coap_find_attr(coap_resource_t *resource,
-                            const unsigned char *name,
-                            size_t nlen);
-
-/**
- * Deletes an attribute.
- *
- * @param attr Pointer to a previously created attribute.
- *
- */
-void coap_delete_attr(coap_attr_t *attr);
-
-/**
- * Status word to encode the result of conditional print or copy operations such
- * as coap_print_link(). The lower 28 bits of coap_print_status_t are used to
- * encode the number of characters that has actually been printed, bits 28 to 31
- * encode the status.  When COAP_PRINT_STATUS_ERROR is set, an error occurred
- * during output. In this case, the other bits are undefined.
- * COAP_PRINT_STATUS_TRUNC indicates that the output is truncated, i.e. the
- * printing would have exceeded the current buffer.
- */
-typedef unsigned int coap_print_status_t;
-
-#define COAP_PRINT_STATUS_MASK  0xF0000000u
-#define COAP_PRINT_OUTPUT_LENGTH(v) ((v) & ~COAP_PRINT_STATUS_MASK)
-#define COAP_PRINT_STATUS_ERROR 0x80000000u
-#define COAP_PRINT_STATUS_TRUNC 0x40000000u
-
-/**
- * Writes a description of this resource in link-format to given text buffer. @p
- * len must be initialized to the maximum length of @p buf and will be set to
- * the number of characters actually written if successful. This function
- * returns @c 1 on success or @c 0 on error.
- *
- * @param resource The resource to describe.
- * @param buf      The output buffer to write the description to.
- * @param len      Must be initialized to the length of @p buf and
- *                 will be set to the length of the printed link description.
- * @param offset   The offset within the resource description where to
- *                 start writing into @p buf. This is useful for dealing
- *                 with the Block2 option. @p offset is updated during
- *                 output as it is consumed.
- *
- * @return If COAP_PRINT_STATUS_ERROR is set, an error occured. Otherwise,
- *         the lower 28 bits will indicate the number of characters that
- *         have actually been output into @p buffer. The flag
- *         COAP_PRINT_STATUS_TRUNC indicates that the output has been
- *         truncated.
- */
-coap_print_status_t coap_print_link(const coap_resource_t *resource,
-                                    unsigned char *buf,
-                                    size_t *len,
-                                    size_t *offset);
-
-/**
- * Registers the specified @p handler as message handler for the request type @p
- * method
- *
- * @param resource The resource for which the handler shall be registered.
- * @param method   The CoAP request method to handle.
- * @param handler  The handler to register with @p resource.
- */
-static inline void
-coap_register_handler(coap_resource_t *resource,
-                      unsigned char method,
-                      coap_method_handler_t handler) {
-  assert(resource);
-  assert(method > 0 && (size_t)(method-1) < sizeof(resource->handler)/sizeof(coap_method_handler_t));
-  resource->handler[method-1] = handler;
-}
-
-/**
- * Returns the resource identified by the unique string @p key. If no resource
- * was found, this function returns @c NULL.
- *
- * @param context  The context to look for this resource.
- * @param key      The unique key of the resource.
- *
- * @return         A pointer to the resource or @c NULL if not found.
- */
-coap_resource_t *coap_get_resource_from_key(coap_context_t *context,
-                                            coap_key_t key);
-
-/**
- * Calculates the hash key for the resource requested by the Uri-Options of @p
- * request. This function calls coap_hash() for every path segment.
- *
- * @param request The requesting pdu.
- * @param key     The resulting hash is stored in @p key.
- */
-void coap_hash_request_uri(const coap_pdu_t *request, coap_key_t key);
-
-/**
- * @addtogroup observe
- */
-
-/**
- * Adds the specified peer as observer for @p resource. The subscription is
- * identified by the given @p token. This function returns the registered
- * subscription information if the @p observer has been added, or @c NULL on
- * error.
- *
- * @param resource        The observed resource.
- * @param local_interface The local network interface where the observer is
- *                        attached to.
- * @param observer        The remote peer that wants to received status updates.
- * @param token           The token that identifies this subscription.
- * @return                A pointer to the added/updated subscription
- *                        information or @c NULL on error.
- */
-coap_subscription_t *coap_add_observer(coap_resource_t *resource,
-                                       const coap_endpoint_t *local_interface,
-                                       const coap_address_t *observer,
-                                       const str *token);
-
-/**
- * Returns a subscription object for given @p peer.
- *
- * @param resource The observed resource.
- * @param peer     The address to search for.
- * @param token    The token that identifies this subscription or @c NULL for
- *                 any token.
- * @return         A valid subscription if exists or @c NULL otherwise.
- */
-coap_subscription_t *coap_find_observer(coap_resource_t *resource,
-                                        const coap_address_t *peer,
-                                        const str *token);
-
-/**
- * Marks an observer as alive.
- *
- * @param context  The CoAP context to use.
- * @param observer The transport address of the observer.
- * @param token    The corresponding token that has been used for the
- *                 subscription.
- */
-void coap_touch_observer(coap_context_t *context,
-                         const coap_address_t *observer,
-                         const str *token);
-
-/**
- * Removes any subscription for @p observer from @p resource and releases the
- * allocated storage. The result is @c 1 if an observation relationship with @p
- * observer and @p token existed, @c 0 otherwise.
- *
- * @param resource The observed resource.
- * @param observer The observer's address.
- * @param token    The token that identifies this subscription or @c NULL for
- *                 any token.
- * @return         @c 1 if the observer has been deleted, @c 0 otherwise.
- */
-int coap_delete_observer(coap_resource_t *resource,
-                         const coap_address_t *observer,
-                         const str *token);
-
-/**
- * Checks for all known resources, if they are dirty and notifies subscribed
- * observers.
- */
-void coap_check_notify(coap_context_t *context);
-
-#ifdef COAP_RESOURCES_NOHASH
-
-#define RESOURCES_ADD(r, obj) \
-  LL_PREPEND((r), (obj))
-
-#define RESOURCES_DELETE(r, obj) \
-  LL_DELETE((r), (obj))
-
-#define RESOURCES_ITER(r,tmp) \
-  coap_resource_t *tmp;       \
-  LL_FOREACH((r), tmp)
-
-#define RESOURCES_FIND(r, k, res) {                         \
-    coap_resource_t *tmp;                                   \
-    (res) = tmp = NULL;                                     \
-    LL_FOREACH((r), tmp) {                                  \
-      if (memcmp((k), tmp->key, sizeof(coap_key_t)) == 0) { \
-        (res) = tmp;                                        \
-        break;                                              \
-      }                                                     \
-    }                                                       \
-  }
-#else /* COAP_RESOURCES_NOHASH */
-
-#define RESOURCES_ADD(r, obj) \
-  HASH_ADD(hh, (r), key, sizeof(coap_key_t), (obj))
-
-#define RESOURCES_DELETE(r, obj) \
-  HASH_DELETE(hh, (r), (obj))
-
-#define RESOURCES_ITER(r,tmp)  \
-  coap_resource_t *tmp, *rtmp; \
-  HASH_ITER(hh, (r), tmp, rtmp)
-
-#define RESOURCES_FIND(r, k, res) {                     \
-    HASH_FIND(hh, (r), (k), sizeof(coap_key_t), (res)); \
-  }
-
-#endif /* COAP_RESOURCES_NOHASH */
-
-/** @} */
-
-coap_print_status_t coap_print_wellknown(coap_context_t *,
-                                         unsigned char *,
-                                         size_t *, size_t,
-                                         coap_opt_t *);
-
-void coap_handle_failed_notify(coap_context_t *,
-                               const coap_address_t *,
-                               const str *);
-
-#endif /* _COAP_RESOURCE_H_ */
diff --git a/tools/sdk/include/coap/coap/str.h b/tools/sdk/include/coap/coap/str.h
deleted file mode 100644
index 3dfa6731550..00000000000
--- a/tools/sdk/include/coap/coap/str.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * str.h -- strings to be used in the CoAP library
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_STR_H_
-#define _COAP_STR_H_
-
-#include <string.h>
-
-typedef struct {
-  size_t length;    /* length of string */
-  unsigned char *s; /* string data */
-} str;
-
-#define COAP_SET_STR(st,l,v) { (st)->length = (l), (st)->s = (v); }
-
-/**
- * Returns a new string object with at least size bytes storage allocated. The
- * string must be released using coap_delete_string();
- */
-str *coap_new_string(size_t size);
-
-/**
- * Deletes the given string and releases any memory allocated.
- */
-void coap_delete_string(str *);
-
-#endif /* _COAP_STR_H_ */
diff --git a/tools/sdk/include/coap/coap/subscribe.h b/tools/sdk/include/coap/coap/subscribe.h
deleted file mode 100644
index 52068642dd7..00000000000
--- a/tools/sdk/include/coap/coap/subscribe.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * subscribe.h -- subscription handling for CoAP
- *                see draft-ietf-core-observe-16
- *
- * Copyright (C) 2010-2012,2014-2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-
-#ifndef _COAP_SUBSCRIBE_H_
-#define _COAP_SUBSCRIBE_H_
-
-#include "address.h"
-#include "coap_io.h"
-
-/**
- * @defgroup observe Resource observation
- * @{
- */
-
-/**
- * The value COAP_OBSERVE_ESTABLISH in a GET request indicates a new observe
- * relationship for (sender address, token) is requested.
- */
-#define COAP_OBSERVE_ESTABLISH 0
-
-/**
- * The value COAP_OBSERVE_CANCEL in a GET request indicates that the observe
- * relationship for (sender address, token) must be cancelled.
- */
-#define COAP_OBSERVE_CANCEL 1
-
-#ifndef COAP_OBS_MAX_NON
-/**
- * Number of notifications that may be sent non-confirmable before a confirmable
- * message is sent to detect if observers are alive. The maximum allowed value
- * here is @c 15.
- */
-#define COAP_OBS_MAX_NON   5
-#endif /* COAP_OBS_MAX_NON */
-
-#ifndef COAP_OBS_MAX_FAIL
-/**
- * Number of confirmable notifications that may fail (i.e. time out without
- * being ACKed) before an observer is removed. The maximum value for
- * COAP_OBS_MAX_FAIL is @c 3.
- */
-#define COAP_OBS_MAX_FAIL  3
-#endif /* COAP_OBS_MAX_FAIL */
-
-/** Subscriber information */
-typedef struct coap_subscription_t {
-  struct coap_subscription_t *next; /**< next element in linked list */
-  coap_endpoint_t local_if;         /**< local communication interface */
-  coap_address_t subscriber;        /**< address and port of subscriber */
-
-  unsigned int non_cnt:4;  /**< up to 15 non-confirmable notifies allowed */
-  unsigned int fail_cnt:2; /**< up to 3 confirmable notifies can fail */
-  unsigned int dirty:1;    /**< set if the notification temporarily could not be
-                            *   sent (in that case, the resource's partially
-                            *   dirty flag is set too) */
-  size_t token_length;     /**< actual length of token */
-  unsigned char token[8];  /**< token used for subscription */
-} coap_subscription_t;
-
-void coap_subscription_init(coap_subscription_t *);
-
-/** @} */
-
-#endif /* _COAP_SUBSCRIBE_H_ */
diff --git a/tools/sdk/include/coap/coap/uri.h b/tools/sdk/include/coap/coap/uri.h
deleted file mode 100644
index 2340a7a6c88..00000000000
--- a/tools/sdk/include/coap/coap/uri.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * uri.h -- helper functions for URI treatment
- *
- * Copyright (C) 2010-2011,2016 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_URI_H_
-#define _COAP_URI_H_
-
-#include "hashkey.h"
-#include "str.h"
-
-/**
- * Representation of parsed URI. Components may be filled from a string with
- * coap_split_uri() and can be used as input for option-creation functions.
- */
-typedef struct {
-  str host;             /**< host part of the URI */
-  unsigned short port;  /**< The port in host byte order */
-  str path;             /**< Beginning of the first path segment. 
-                             Use coap_split_path() to create Uri-Path options */
-  str query;            /**<  The query part if present */
-} coap_uri_t;
-
-/**
- * Creates a new coap_uri_t object from the specified URI. Returns the new
- * object or NULL on error. The memory allocated by the new coap_uri_t
- * must be released using coap_free().
- *
- * @param uri The URI path to copy.
- * @param length The length of uri.
- *
- * @return New URI object or NULL on error.
- */
-coap_uri_t *coap_new_uri(const unsigned char *uri, unsigned int length);
-
-/**
- * Clones the specified coap_uri_t object. Thie function allocates sufficient
- * memory to hold the coap_uri_t structure and its contents. The object must
- * be released with coap_free(). */
-coap_uri_t *coap_clone_uri(const coap_uri_t *uri);
-
-/**
- * Calculates a hash over the given path and stores the result in 
- * @p key. This function returns @c 0 on error or @c 1 on success.
- * 
- * @param path The URI path to generate hash for.
- * @param len  The length of @p path.
- * @param key  The output buffer.
- * 
- * @return @c 1 if @p key was set, @c 0 otherwise.
- */
-int coap_hash_path(const unsigned char *path, size_t len, coap_key_t key);
-
-/**
- * @defgroup uri_parse URI Parsing Functions
- *
- * CoAP PDUs contain normalized URIs with their path and query split into
- * multiple segments. The functions in this module help splitting strings.
- * @{
- */
-
-/**
- * Parses a given string into URI components. The identified syntactic
- * components are stored in the result parameter @p uri. Optional URI
- * components that are not specified will be set to { 0, 0 }, except for the
- * port which is set to @c COAP_DEFAULT_PORT. This function returns @p 0 if
- * parsing succeeded, a value less than zero otherwise.
- * 
- * @param str_var The string to split up.
- * @param len     The actual length of @p str_var
- * @param uri     The coap_uri_t object to store the result.
- * @return        @c 0 on success, or < 0 on error.
- *
- */
-int coap_split_uri(const unsigned char *str_var, size_t len, coap_uri_t *uri);
-
-/**
- * Splits the given URI path into segments. Each segment is preceded
- * by an option pseudo-header with delta-value 0 and the actual length
- * of the respective segment after percent-decoding.
- * 
- * @param s      The path string to split. 
- * @param length The actual length of @p s.
- * @param buf    Result buffer for parsed segments. 
- * @param buflen Maximum length of @p buf. Will be set to the actual number
- *               of bytes written into buf on success.
- * 
- * @return       The number of segments created or @c -1 on error.
- */
-int coap_split_path(const unsigned char *s,
-                    size_t length,
-                    unsigned char *buf,
-                    size_t *buflen);
-
-/** 
- * Splits the given URI query into segments. Each segment is preceded
- * by an option pseudo-header with delta-value 0 and the actual length
- * of the respective query term.
- * 
- * @param s      The query string to split. 
- * @param length The actual length of @p s.
- * @param buf    Result buffer for parsed segments. 
- * @param buflen Maximum length of @p buf. Will be set to the actual number
- *               of bytes written into buf on success.
- * 
- * @return       The number of segments created or @c -1 on error.
- *
- * @bug This function does not reserve additional space for delta > 12.
- */
-int coap_split_query(const unsigned char *s,
-                     size_t length,
-                     unsigned char *buf,
-                     size_t *buflen);
-
-/** @} */
-
-#endif /* _COAP_URI_H_ */
diff --git a/tools/sdk/include/coap/coap/uthash.h b/tools/sdk/include/coap/coap/uthash.h
deleted file mode 100644
index 32b7a81cfbb..00000000000
--- a/tools/sdk/include/coap/coap/uthash.h
+++ /dev/null
@@ -1,963 +0,0 @@
-/*
-Copyright (c) 2003-2014, Troy D. Hanson     http://troydhanson.github.com/uthash/
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
-OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#ifndef UTHASH_H
-#define UTHASH_H
-
-#include <string.h>   /* memcmp,strlen */
-#include <stddef.h>   /* ptrdiff_t */
-#include <stdlib.h>   /* exit() */
-
-/* These macros use decltype or the earlier __typeof GNU extension.
-   As decltype is only available in newer compilers (VS2010 or gcc 4.3+
-   when compiling c++ source) this code uses whatever method is needed
-   or, for VS2008 where neither is available, uses casting workarounds. */
-#if defined(_MSC_VER)   /* MS compiler */
-#if _MSC_VER >= 1600 && defined(__cplusplus)  /* VS2010 or newer in C++ mode */
-#define DECLTYPE(x) (decltype(x))
-#else                   /* VS2008 or older (or VS2010 in C mode) */
-#define NO_DECLTYPE
-#define DECLTYPE(x)
-#endif
-#elif defined(__BORLANDC__) || defined(__LCC__) || defined(__WATCOMC__)
-#define NO_DECLTYPE
-#define DECLTYPE(x)
-#else                   /* GNU, Sun and other compilers */
-#define DECLTYPE(x) (__typeof(x))
-#endif
-
-#ifdef NO_DECLTYPE
-#define DECLTYPE_ASSIGN(dst,src)                                                 \
-do {                                                                             \
-  char **_da_dst = (char**)(&(dst));                                             \
-  *_da_dst = (char*)(src);                                                       \
-} while(0)
-#else
-#define DECLTYPE_ASSIGN(dst,src)                                                 \
-do {                                                                             \
-  (dst) = DECLTYPE(dst)(src);                                                    \
-} while(0)
-#endif
-
-/* a number of the hash function use uint32_t which isn't defined on Pre VS2010 */
-#if defined (_WIN32)
-#if defined(_MSC_VER) && _MSC_VER >= 1600
-#include <stdint.h>
-#elif defined(__WATCOMC__)
-#include <stdint.h>
-#else
-typedef unsigned int uint32_t;
-typedef unsigned char uint8_t;
-#endif
-#else
-#include <stdint.h>
-#endif
-
-#define UTHASH_VERSION 1.9.9
-
-#ifndef uthash_fatal
-#define uthash_fatal(msg) exit(-1)        /* fatal error (out of memory,etc) */
-#endif
-#ifndef uthash_malloc
-#define uthash_malloc(sz) malloc(sz)      /* malloc fcn                      */
-#endif
-#ifndef uthash_free
-#define uthash_free(ptr,sz) free(ptr)     /* free fcn                        */
-#endif
-
-#ifndef uthash_noexpand_fyi
-#define uthash_noexpand_fyi(tbl)          /* can be defined to log noexpand  */
-#endif
-#ifndef uthash_expand_fyi
-#define uthash_expand_fyi(tbl)            /* can be defined to log expands   */
-#endif
-
-/* initial number of buckets */
-#define HASH_INITIAL_NUM_BUCKETS 32      /* initial number of buckets        */
-#define HASH_INITIAL_NUM_BUCKETS_LOG2 5  /* lg2 of initial number of buckets */
-#define HASH_BKT_CAPACITY_THRESH 10      /* expand when bucket count reaches */
-
-/* calculate the element whose hash handle address is hhe */
-#define ELMT_FROM_HH(tbl,hhp) ((void*)(((char*)(hhp)) - ((tbl)->hho)))
-
-#define HASH_FIND(hh,head,keyptr,keylen,out)                                     \
-do {                                                                             \
-  out=NULL;                                                                      \
-  if (head) {                                                                    \
-     unsigned _hf_bkt,_hf_hashv;                                                 \
-     HASH_FCN(keyptr,keylen, (head)->hh.tbl->num_buckets, _hf_hashv, _hf_bkt);   \
-     if (HASH_BLOOM_TEST((head)->hh.tbl, _hf_hashv)) {                           \
-       HASH_FIND_IN_BKT((head)->hh.tbl, hh, (head)->hh.tbl->buckets[ _hf_bkt ],  \
-                        keyptr,keylen,out);                                      \
-     }                                                                           \
-  }                                                                              \
-} while (0)
-
-#ifdef HASH_BLOOM
-#define HASH_BLOOM_BITLEN (1ULL << HASH_BLOOM)
-#define HASH_BLOOM_BYTELEN (HASH_BLOOM_BITLEN/8) + ((HASH_BLOOM_BITLEN%8) ? 1:0)
-#define HASH_BLOOM_MAKE(tbl)                                                     \
-do {                                                                             \
-  (tbl)->bloom_nbits = HASH_BLOOM;                                               \
-  (tbl)->bloom_bv = (uint8_t*)uthash_malloc(HASH_BLOOM_BYTELEN);                 \
-  if (!((tbl)->bloom_bv))  { uthash_fatal( "out of memory"); }                   \
-  memset((tbl)->bloom_bv, 0, HASH_BLOOM_BYTELEN);                                \
-  (tbl)->bloom_sig = HASH_BLOOM_SIGNATURE;                                       \
-} while (0)
-
-#define HASH_BLOOM_FREE(tbl)                                                     \
-do {                                                                             \
-  uthash_free((tbl)->bloom_bv, HASH_BLOOM_BYTELEN);                              \
-} while (0)
-
-#define HASH_BLOOM_BITSET(bv,idx) (bv[(idx)/8] |= (1U << ((idx)%8)))
-#define HASH_BLOOM_BITTEST(bv,idx) (bv[(idx)/8] & (1U << ((idx)%8)))
-
-#define HASH_BLOOM_ADD(tbl,hashv)                                                \
-  HASH_BLOOM_BITSET((tbl)->bloom_bv, (hashv & (uint32_t)((1ULL << (tbl)->bloom_nbits) - 1)))
-
-#define HASH_BLOOM_TEST(tbl,hashv)                                               \
-  HASH_BLOOM_BITTEST((tbl)->bloom_bv, (hashv & (uint32_t)((1ULL << (tbl)->bloom_nbits) - 1)))
-
-#else
-#define HASH_BLOOM_MAKE(tbl)
-#define HASH_BLOOM_FREE(tbl)
-#define HASH_BLOOM_ADD(tbl,hashv)
-#define HASH_BLOOM_TEST(tbl,hashv) (1)
-#define HASH_BLOOM_BYTELEN 0
-#endif
-
-#define HASH_MAKE_TABLE(hh,head)                                                 \
-do {                                                                             \
-  (head)->hh.tbl = (UT_hash_table*)uthash_malloc(                                \
-                  sizeof(UT_hash_table));                                        \
-  if (!((head)->hh.tbl))  { uthash_fatal( "out of memory"); }                    \
-  memset((head)->hh.tbl, 0, sizeof(UT_hash_table));                              \
-  (head)->hh.tbl->tail = &((head)->hh);                                          \
-  (head)->hh.tbl->num_buckets = HASH_INITIAL_NUM_BUCKETS;                        \
-  (head)->hh.tbl->log2_num_buckets = HASH_INITIAL_NUM_BUCKETS_LOG2;              \
-  (head)->hh.tbl->hho = (char*)(&(head)->hh) - (char*)(head);                    \
-  (head)->hh.tbl->buckets = (UT_hash_bucket*)uthash_malloc(                      \
-          HASH_INITIAL_NUM_BUCKETS*sizeof(struct UT_hash_bucket));               \
-  if (! (head)->hh.tbl->buckets) { uthash_fatal( "out of memory"); }             \
-  memset((head)->hh.tbl->buckets, 0,                                             \
-          HASH_INITIAL_NUM_BUCKETS*sizeof(struct UT_hash_bucket));               \
-  HASH_BLOOM_MAKE((head)->hh.tbl);                                               \
-  (head)->hh.tbl->signature = HASH_SIGNATURE;                                    \
-} while(0)
-
-#define HASH_ADD(hh,head,fieldname,keylen_in,add)                                \
-        HASH_ADD_KEYPTR(hh,head,&((add)->fieldname),keylen_in,add)
-
-#define HASH_REPLACE(hh,head,fieldname,keylen_in,add,replaced)                   \
-do {                                                                             \
-  replaced=NULL;                                                                 \
-  HASH_FIND(hh,head,&((add)->fieldname),keylen_in,replaced);                     \
-  if (replaced!=NULL) {                                                          \
-     HASH_DELETE(hh,head,replaced);                                              \
-  };                                                                             \
-  HASH_ADD(hh,head,fieldname,keylen_in,add);                                     \
-} while(0)
-
-#define HASH_ADD_KEYPTR(hh,head,keyptr,keylen_in,add)                            \
-do {                                                                             \
- unsigned _ha_bkt;                                                               \
- (add)->hh.next = NULL;                                                          \
- (add)->hh.key = (char*)(keyptr);                                                \
- (add)->hh.keylen = (unsigned)(keylen_in);                                       \
- if (!(head)) {                                                                  \
-    head = (add);                                                                \
-    (head)->hh.prev = NULL;                                                      \
-    HASH_MAKE_TABLE(hh,head);                                                    \
- } else {                                                                        \
-    (head)->hh.tbl->tail->next = (add);                                          \
-    (add)->hh.prev = ELMT_FROM_HH((head)->hh.tbl, (head)->hh.tbl->tail);         \
-    (head)->hh.tbl->tail = &((add)->hh);                                         \
- }                                                                               \
- (head)->hh.tbl->num_items++;                                                    \
- (add)->hh.tbl = (head)->hh.tbl;                                                 \
- HASH_FCN(keyptr,keylen_in, (head)->hh.tbl->num_buckets,                         \
-         (add)->hh.hashv, _ha_bkt);                                              \
- HASH_ADD_TO_BKT((head)->hh.tbl->buckets[_ha_bkt],&(add)->hh);                   \
- HASH_BLOOM_ADD((head)->hh.tbl,(add)->hh.hashv);                                 \
- HASH_EMIT_KEY(hh,head,keyptr,keylen_in);                                        \
- HASH_FSCK(hh,head);                                                             \
-} while(0)
-
-#define HASH_TO_BKT( hashv, num_bkts, bkt )                                      \
-do {                                                                             \
-  bkt = ((hashv) & ((num_bkts) - 1));                                            \
-} while(0)
-
-/* delete "delptr" from the hash table.
- * "the usual" patch-up process for the app-order doubly-linked-list.
- * The use of _hd_hh_del below deserves special explanation.
- * These used to be expressed using (delptr) but that led to a bug
- * if someone used the same symbol for the head and deletee, like
- *  HASH_DELETE(hh,users,users);
- * We want that to work, but by changing the head (users) below
- * we were forfeiting our ability to further refer to the deletee (users)
- * in the patch-up process. Solution: use scratch space to
- * copy the deletee pointer, then the latter references are via that
- * scratch pointer rather than through the repointed (users) symbol.
- */
-#define HASH_DELETE(hh,head,delptr)                                              \
-do {                                                                             \
-    struct UT_hash_handle *_hd_hh_del;                                           \
-    if ( ((delptr)->hh.prev == NULL) && ((delptr)->hh.next == NULL) )  {         \
-        uthash_free((head)->hh.tbl->buckets,                                     \
-                    (head)->hh.tbl->num_buckets*sizeof(struct UT_hash_bucket) ); \
-        HASH_BLOOM_FREE((head)->hh.tbl);                                         \
-        uthash_free((head)->hh.tbl, sizeof(UT_hash_table));                      \
-        head = NULL;                                                             \
-    } else {                                                                     \
-        unsigned _hd_bkt;                                                        \
-        _hd_hh_del = &((delptr)->hh);                                            \
-        if ((delptr) == ELMT_FROM_HH((head)->hh.tbl,(head)->hh.tbl->tail)) {     \
-            (head)->hh.tbl->tail =                                               \
-                (UT_hash_handle*)((ptrdiff_t)((delptr)->hh.prev) +               \
-                (head)->hh.tbl->hho);                                            \
-        }                                                                        \
-        if ((delptr)->hh.prev) {                                                 \
-            ((UT_hash_handle*)((ptrdiff_t)((delptr)->hh.prev) +                  \
-                    (head)->hh.tbl->hho))->next = (delptr)->hh.next;             \
-        } else {                                                                 \
-            DECLTYPE_ASSIGN(head,(delptr)->hh.next);                             \
-        }                                                                        \
-        if (_hd_hh_del->next) {                                                  \
-            ((UT_hash_handle*)((ptrdiff_t)_hd_hh_del->next +                     \
-                    (head)->hh.tbl->hho))->prev =                                \
-                    _hd_hh_del->prev;                                            \
-        }                                                                        \
-        HASH_TO_BKT( _hd_hh_del->hashv, (head)->hh.tbl->num_buckets, _hd_bkt);   \
-        HASH_DEL_IN_BKT(hh,(head)->hh.tbl->buckets[_hd_bkt], _hd_hh_del);        \
-        (head)->hh.tbl->num_items--;                                             \
-    }                                                                            \
-    HASH_FSCK(hh,head);                                                          \
-} while (0)
-
-
-/* convenience forms of HASH_FIND/HASH_ADD/HASH_DEL */
-#define HASH_FIND_STR(head,findstr,out)                                          \
-    HASH_FIND(hh,head,findstr,(unsigned)strlen(findstr),out)
-#define HASH_ADD_STR(head,strfield,add)                                          \
-    HASH_ADD(hh,head,strfield[0],strlen(add->strfield),add)
-#define HASH_REPLACE_STR(head,strfield,add,replaced)                             \
-    HASH_REPLACE(hh,head,strfield[0],(unsigned)strlen(add->strfield),add,replaced)
-#define HASH_FIND_INT(head,findint,out)                                          \
-    HASH_FIND(hh,head,findint,sizeof(int),out)
-#define HASH_ADD_INT(head,intfield,add)                                          \
-    HASH_ADD(hh,head,intfield,sizeof(int),add)
-#define HASH_REPLACE_INT(head,intfield,add,replaced)                             \
-    HASH_REPLACE(hh,head,intfield,sizeof(int),add,replaced)
-#define HASH_FIND_PTR(head,findptr,out)                                          \
-    HASH_FIND(hh,head,findptr,sizeof(void *),out)
-#define HASH_ADD_PTR(head,ptrfield,add)                                          \
-    HASH_ADD(hh,head,ptrfield,sizeof(void *),add)
-#define HASH_REPLACE_PTR(head,ptrfield,add,replaced)                             \
-    HASH_REPLACE(hh,head,ptrfield,sizeof(void *),add,replaced)
-#define HASH_DEL(head,delptr)                                                    \
-    HASH_DELETE(hh,head,delptr)
-
-/* HASH_FSCK checks hash integrity on every add/delete when HASH_DEBUG is defined.
- * This is for uthash developer only; it compiles away if HASH_DEBUG isn't defined.
- */
-#ifdef HASH_DEBUG
-#define HASH_OOPS(...) do { fprintf(stderr,__VA_ARGS__); exit(-1); } while (0)
-#define HASH_FSCK(hh,head)                                                       \
-do {                                                                             \
-    struct UT_hash_handle *_thh;                                                 \
-    if (head) {                                                                  \
-        unsigned _bkt_i;                                                         \
-        unsigned _count;                                                         \
-        char *_prev;                                                             \
-        _count = 0;                                                              \
-        for( _bkt_i = 0; _bkt_i < (head)->hh.tbl->num_buckets; _bkt_i++) {       \
-            unsigned _bkt_count = 0;                                             \
-            _thh = (head)->hh.tbl->buckets[_bkt_i].hh_head;                      \
-            _prev = NULL;                                                        \
-            while (_thh) {                                                       \
-               if (_prev != (char*)(_thh->hh_prev)) {                            \
-                   HASH_OOPS("invalid hh_prev %p, actual %p\n",                  \
-                    _thh->hh_prev, _prev );                                      \
-               }                                                                 \
-               _bkt_count++;                                                     \
-               _prev = (char*)(_thh);                                            \
-               _thh = _thh->hh_next;                                             \
-            }                                                                    \
-            _count += _bkt_count;                                                \
-            if ((head)->hh.tbl->buckets[_bkt_i].count !=  _bkt_count) {          \
-               HASH_OOPS("invalid bucket count %u, actual %u\n",                 \
-                (head)->hh.tbl->buckets[_bkt_i].count, _bkt_count);              \
-            }                                                                    \
-        }                                                                        \
-        if (_count != (head)->hh.tbl->num_items) {                               \
-            HASH_OOPS("invalid hh item count %u, actual %u\n",                   \
-                (head)->hh.tbl->num_items, _count );                             \
-        }                                                                        \
-        /* traverse hh in app order; check next/prev integrity, count */         \
-        _count = 0;                                                              \
-        _prev = NULL;                                                            \
-        _thh =  &(head)->hh;                                                     \
-        while (_thh) {                                                           \
-           _count++;                                                             \
-           if (_prev !=(char*)(_thh->prev)) {                                    \
-              HASH_OOPS("invalid prev %p, actual %p\n",                          \
-                    _thh->prev, _prev );                                         \
-           }                                                                     \
-           _prev = (char*)ELMT_FROM_HH((head)->hh.tbl, _thh);                    \
-           _thh = ( _thh->next ?  (UT_hash_handle*)((char*)(_thh->next) +        \
-                                  (head)->hh.tbl->hho) : NULL );                 \
-        }                                                                        \
-        if (_count != (head)->hh.tbl->num_items) {                               \
-            HASH_OOPS("invalid app item count %u, actual %u\n",                  \
-                (head)->hh.tbl->num_items, _count );                             \
-        }                                                                        \
-    }                                                                            \
-} while (0)
-#else
-#define HASH_FSCK(hh,head)
-#endif
-
-/* When compiled with -DHASH_EMIT_KEYS, length-prefixed keys are emitted to
- * the descriptor to which this macro is defined for tuning the hash function.
- * The app can #include <unistd.h> to get the prototype for write(2). */
-#ifdef HASH_EMIT_KEYS
-#define HASH_EMIT_KEY(hh,head,keyptr,fieldlen)                                   \
-do {                                                                             \
-    unsigned _klen = fieldlen;                                                   \
-    write(HASH_EMIT_KEYS, &_klen, sizeof(_klen));                                \
-    write(HASH_EMIT_KEYS, keyptr, fieldlen);                                     \
-} while (0)
-#else
-#define HASH_EMIT_KEY(hh,head,keyptr,fieldlen)
-#endif
-
-/* default to Jenkin's hash unless overridden e.g. DHASH_FUNCTION=HASH_SAX */
-#ifdef HASH_FUNCTION
-#define HASH_FCN HASH_FUNCTION
-#else
-#define HASH_FCN HASH_JEN
-#endif
-
-/* The Bernstein hash function, used in Perl prior to v5.6. Note (x<<5+x)=x*33. */
-#define HASH_BER(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _hb_keylen=keylen;                                                    \
-  char *_hb_key=(char*)(key);                                                    \
-  (hashv) = 0;                                                                   \
-  while (_hb_keylen--)  { (hashv) = (((hashv) << 5) + (hashv)) + *_hb_key++; }   \
-  bkt = (hashv) & (num_bkts-1);                                                  \
-} while (0)
-
-
-/* SAX/FNV/OAT/JEN hash functions are macro variants of those listed at
- * http://eternallyconfuzzled.com/tuts/algorithms/jsw_tut_hashing.aspx */
-#define HASH_SAX(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _sx_i;                                                                \
-  char *_hs_key=(char*)(key);                                                    \
-  hashv = 0;                                                                     \
-  for(_sx_i=0; _sx_i < keylen; _sx_i++)                                          \
-      hashv ^= (hashv << 5) + (hashv >> 2) + _hs_key[_sx_i];                     \
-  bkt = hashv & (num_bkts-1);                                                    \
-} while (0)
-/* FNV-1a variation */
-#define HASH_FNV(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _fn_i;                                                                \
-  char *_hf_key=(char*)(key);                                                    \
-  hashv = 2166136261UL;                                                          \
-  for(_fn_i=0; _fn_i < keylen; _fn_i++) {                                        \
-      hashv = hashv ^ _hf_key[_fn_i];                                            \
-      hashv = hashv * 16777619;                                                  \
-  }                                                                              \
-  bkt = hashv & (num_bkts-1);                                                    \
-} while(0)
-
-#define HASH_OAT(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _ho_i;                                                                \
-  char *_ho_key=(char*)(key);                                                    \
-  hashv = 0;                                                                     \
-  for(_ho_i=0; _ho_i < keylen; _ho_i++) {                                        \
-      hashv += _ho_key[_ho_i];                                                   \
-      hashv += (hashv << 10);                                                    \
-      hashv ^= (hashv >> 6);                                                     \
-  }                                                                              \
-  hashv += (hashv << 3);                                                         \
-  hashv ^= (hashv >> 11);                                                        \
-  hashv += (hashv << 15);                                                        \
-  bkt = hashv & (num_bkts-1);                                                    \
-} while(0)
-
-#define HASH_JEN_MIX(a,b,c)                                                      \
-do {                                                                             \
-  a -= b; a -= c; a ^= ( c >> 13 );                                              \
-  b -= c; b -= a; b ^= ( a << 8 );                                               \
-  c -= a; c -= b; c ^= ( b >> 13 );                                              \
-  a -= b; a -= c; a ^= ( c >> 12 );                                              \
-  b -= c; b -= a; b ^= ( a << 16 );                                              \
-  c -= a; c -= b; c ^= ( b >> 5 );                                               \
-  a -= b; a -= c; a ^= ( c >> 3 );                                               \
-  b -= c; b -= a; b ^= ( a << 10 );                                              \
-  c -= a; c -= b; c ^= ( b >> 15 );                                              \
-} while (0)
-
-#define HASH_JEN(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _hj_i,_hj_j,_hj_k;                                                    \
-  unsigned char *_hj_key=(unsigned char*)(key);                                  \
-  hashv = 0xfeedbeef;                                                            \
-  _hj_i = _hj_j = 0x9e3779b9;                                                    \
-  _hj_k = (unsigned)(keylen);                                                    \
-  while (_hj_k >= 12) {                                                          \
-    _hj_i +=    (_hj_key[0] + ( (unsigned)_hj_key[1] << 8 )                      \
-        + ( (unsigned)_hj_key[2] << 16 )                                         \
-        + ( (unsigned)_hj_key[3] << 24 ) );                                      \
-    _hj_j +=    (_hj_key[4] + ( (unsigned)_hj_key[5] << 8 )                      \
-        + ( (unsigned)_hj_key[6] << 16 )                                         \
-        + ( (unsigned)_hj_key[7] << 24 ) );                                      \
-    hashv += (_hj_key[8] + ( (unsigned)_hj_key[9] << 8 )                         \
-        + ( (unsigned)_hj_key[10] << 16 )                                        \
-        + ( (unsigned)_hj_key[11] << 24 ) );                                     \
-                                                                                 \
-     HASH_JEN_MIX(_hj_i, _hj_j, hashv);                                          \
-                                                                                 \
-     _hj_key += 12;                                                              \
-     _hj_k -= 12;                                                                \
-  }                                                                              \
-  hashv += keylen;                                                               \
-  switch ( _hj_k ) {                                                             \
-     case 11: hashv += ( (unsigned)_hj_key[10] << 24 );                          \
-     case 10: hashv += ( (unsigned)_hj_key[9] << 16 );                           \
-     case 9:  hashv += ( (unsigned)_hj_key[8] << 8 );                            \
-     case 8:  _hj_j += ( (unsigned)_hj_key[7] << 24 );                           \
-     case 7:  _hj_j += ( (unsigned)_hj_key[6] << 16 );                           \
-     case 6:  _hj_j += ( (unsigned)_hj_key[5] << 8 );                            \
-     case 5:  _hj_j += _hj_key[4];                                               \
-     case 4:  _hj_i += ( (unsigned)_hj_key[3] << 24 );                           \
-     case 3:  _hj_i += ( (unsigned)_hj_key[2] << 16 );                           \
-     case 2:  _hj_i += ( (unsigned)_hj_key[1] << 8 );                            \
-     case 1:  _hj_i += _hj_key[0];                                               \
-     /* case 0: nothing left to add */                                           \
-     default: /* make gcc -Wswitch-default happy */                              \
-       ;                                                                         \
-  }                                                                              \
-  HASH_JEN_MIX(_hj_i, _hj_j, hashv);                                             \
-  bkt = hashv & (num_bkts-1);                                                    \
-} while(0)
-
-/* The Paul Hsieh hash function */
-#undef get16bits
-#if (defined(__GNUC__) && defined(__i386__)) || defined(__WATCOMC__)             \
-  || defined(_MSC_VER) || defined (__BORLANDC__) || defined (__TURBOC__)
-#define get16bits(d) (*((const uint16_t *) (d)))
-#endif
-
-#if !defined (get16bits)
-#define get16bits(d) ((((uint32_t)(((const uint8_t *)(d))[1])) << 8)             \
-                       +(uint32_t)(((const uint8_t *)(d))[0]) )
-#endif
-#define HASH_SFH(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned char *_sfh_key=(unsigned char*)(key);                                 \
-  uint32_t _sfh_tmp, _sfh_len = keylen;                                          \
-                                                                                 \
-  int _sfh_rem = _sfh_len & 3;                                                   \
-  _sfh_len >>= 2;                                                                \
-  hashv = 0xcafebabe;                                                            \
-                                                                                 \
-  /* Main loop */                                                                \
-  for (;_sfh_len > 0; _sfh_len--) {                                              \
-    hashv    += get16bits (_sfh_key);                                            \
-    _sfh_tmp       = (uint32_t)(get16bits (_sfh_key+2)) << 11  ^ hashv;          \
-    hashv     = (hashv << 16) ^ _sfh_tmp;                                        \
-    _sfh_key += 2*sizeof (uint16_t);                                             \
-    hashv    += hashv >> 11;                                                     \
-  }                                                                              \
-                                                                                 \
-  /* Handle end cases */                                                         \
-  switch (_sfh_rem) {                                                            \
-    case 3: hashv += get16bits (_sfh_key);                                       \
-            hashv ^= hashv << 16;                                                \
-            hashv ^= (uint32_t)(_sfh_key[sizeof (uint16_t)] << 18);              \
-            hashv += hashv >> 11;                                                \
-            break;                                                               \
-    case 2: hashv += get16bits (_sfh_key);                                       \
-            hashv ^= hashv << 11;                                                \
-            hashv += hashv >> 17;                                                \
-            break;                                                               \
-    case 1: hashv += *_sfh_key;                                                  \
-            hashv ^= hashv << 10;                                                \
-            hashv += hashv >> 1;                                                 \
-  }                                                                              \
-                                                                                 \
-    /* Force "avalanching" of final 127 bits */                                  \
-    hashv ^= hashv << 3;                                                         \
-    hashv += hashv >> 5;                                                         \
-    hashv ^= hashv << 4;                                                         \
-    hashv += hashv >> 17;                                                        \
-    hashv ^= hashv << 25;                                                        \
-    hashv += hashv >> 6;                                                         \
-    bkt = hashv & (num_bkts-1);                                                  \
-} while(0)
-
-#ifdef HASH_USING_NO_STRICT_ALIASING
-/* The MurmurHash exploits some CPU's (x86,x86_64) tolerance for unaligned reads.
- * For other types of CPU's (e.g. Sparc) an unaligned read causes a bus error.
- * MurmurHash uses the faster approach only on CPU's where we know it's safe.
- *
- * Note the preprocessor built-in defines can be emitted using:
- *
- *   gcc -m64 -dM -E - < /dev/null                  (on gcc)
- *   cc -## a.c (where a.c is a simple test file)   (Sun Studio)
- */
-#if (defined(__i386__) || defined(__x86_64__)  || defined(_M_IX86))
-#define MUR_GETBLOCK(p,i) p[i]
-#else /* non intel */
-#define MUR_PLUS0_ALIGNED(p) (((unsigned long)p & 0x3) == 0)
-#define MUR_PLUS1_ALIGNED(p) (((unsigned long)p & 0x3) == 1)
-#define MUR_PLUS2_ALIGNED(p) (((unsigned long)p & 0x3) == 2)
-#define MUR_PLUS3_ALIGNED(p) (((unsigned long)p & 0x3) == 3)
-#define WP(p) ((uint32_t*)((unsigned long)(p) & ~3UL))
-#if (defined(__BIG_ENDIAN__) || defined(SPARC) || defined(__ppc__) || defined(__ppc64__))
-#define MUR_THREE_ONE(p) ((((*WP(p))&0x00ffffff) << 8) | (((*(WP(p)+1))&0xff000000) >> 24))
-#define MUR_TWO_TWO(p)   ((((*WP(p))&0x0000ffff) <<16) | (((*(WP(p)+1))&0xffff0000) >> 16))
-#define MUR_ONE_THREE(p) ((((*WP(p))&0x000000ff) <<24) | (((*(WP(p)+1))&0xffffff00) >>  8))
-#else /* assume little endian non-intel */
-#define MUR_THREE_ONE(p) ((((*WP(p))&0xffffff00) >> 8) | (((*(WP(p)+1))&0x000000ff) << 24))
-#define MUR_TWO_TWO(p)   ((((*WP(p))&0xffff0000) >>16) | (((*(WP(p)+1))&0x0000ffff) << 16))
-#define MUR_ONE_THREE(p) ((((*WP(p))&0xff000000) >>24) | (((*(WP(p)+1))&0x00ffffff) <<  8))
-#endif
-#define MUR_GETBLOCK(p,i) (MUR_PLUS0_ALIGNED(p) ? ((p)[i]) :           \
-                            (MUR_PLUS1_ALIGNED(p) ? MUR_THREE_ONE(p) : \
-                             (MUR_PLUS2_ALIGNED(p) ? MUR_TWO_TWO(p) :  \
-                                                      MUR_ONE_THREE(p))))
-#endif
-#define MUR_ROTL32(x,r) (((x) << (r)) | ((x) >> (32 - (r))))
-#define MUR_FMIX(_h) \
-do {                 \
-  _h ^= _h >> 16;    \
-  _h *= 0x85ebca6b;  \
-  _h ^= _h >> 13;    \
-  _h *= 0xc2b2ae35l; \
-  _h ^= _h >> 16;    \
-} while(0)
-
-#define HASH_MUR(key,keylen,num_bkts,hashv,bkt)                        \
-do {                                                                   \
-  const uint8_t *_mur_data = (const uint8_t*)(key);                    \
-  const int _mur_nblocks = (keylen) / 4;                               \
-  uint32_t _mur_h1 = 0xf88D5353;                                       \
-  uint32_t _mur_c1 = 0xcc9e2d51;                                       \
-  uint32_t _mur_c2 = 0x1b873593;                                       \
-  uint32_t _mur_k1 = 0;                                                \
-  const uint8_t *_mur_tail;                                            \
-  const uint32_t *_mur_blocks = (const uint32_t*)(_mur_data+_mur_nblocks*4); \
-  int _mur_i;                                                          \
-  for(_mur_i = -_mur_nblocks; _mur_i; _mur_i++) {                      \
-    _mur_k1 = MUR_GETBLOCK(_mur_blocks,_mur_i);                        \
-    _mur_k1 *= _mur_c1;                                                \
-    _mur_k1 = MUR_ROTL32(_mur_k1,15);                                  \
-    _mur_k1 *= _mur_c2;                                                \
-                                                                       \
-    _mur_h1 ^= _mur_k1;                                                \
-    _mur_h1 = MUR_ROTL32(_mur_h1,13);                                  \
-    _mur_h1 = _mur_h1*5+0xe6546b64;                                    \
-  }                                                                    \
-  _mur_tail = (const uint8_t*)(_mur_data + _mur_nblocks*4);            \
-  _mur_k1=0;                                                           \
-  switch((keylen) & 3) {                                               \
-    case 3: _mur_k1 ^= _mur_tail[2] << 16;                             \
-    case 2: _mur_k1 ^= _mur_tail[1] << 8;                              \
-    case 1: _mur_k1 ^= _mur_tail[0];                                   \
-    _mur_k1 *= _mur_c1;                                                \
-    _mur_k1 = MUR_ROTL32(_mur_k1,15);                                  \
-    _mur_k1 *= _mur_c2;                                                \
-    _mur_h1 ^= _mur_k1;                                                \
-  }                                                                    \
-  _mur_h1 ^= (keylen);                                                 \
-  MUR_FMIX(_mur_h1);                                                   \
-  hashv = _mur_h1;                                                     \
-  bkt = hashv & (num_bkts-1);                                          \
-} while(0)
-#endif  /* HASH_USING_NO_STRICT_ALIASING */
-
-/* key comparison function; return 0 if keys equal */
-#define HASH_KEYCMP(a,b,len) memcmp(a,b,len)
-
-/* iterate over items in a known bucket to find desired item */
-#define HASH_FIND_IN_BKT(tbl,hh,head,keyptr,keylen_in,out)                       \
-do {                                                                             \
- if (head.hh_head) DECLTYPE_ASSIGN(out,ELMT_FROM_HH(tbl,head.hh_head));          \
- else out=NULL;                                                                  \
- while (out) {                                                                   \
-    if ((out)->hh.keylen == keylen_in) {                                           \
-        if ((HASH_KEYCMP((out)->hh.key,keyptr,keylen_in)) == 0) break;             \
-    }                                                                            \
-    if ((out)->hh.hh_next) DECLTYPE_ASSIGN(out,ELMT_FROM_HH(tbl,(out)->hh.hh_next)); \
-    else out = NULL;                                                             \
- }                                                                               \
-} while(0)
-
-/* add an item to a bucket  */
-#define HASH_ADD_TO_BKT(head,addhh)                                              \
-do {                                                                             \
- head.count++;                                                                   \
- (addhh)->hh_next = head.hh_head;                                                \
- (addhh)->hh_prev = NULL;                                                        \
- if (head.hh_head) { (head).hh_head->hh_prev = (addhh); }                        \
- (head).hh_head=addhh;                                                           \
- if (head.count >= ((head.expand_mult+1) * HASH_BKT_CAPACITY_THRESH)             \
-     && (addhh)->tbl->noexpand != 1) {                                           \
-       HASH_EXPAND_BUCKETS((addhh)->tbl);                                        \
- }                                                                               \
-} while(0)
-
-/* remove an item from a given bucket */
-#define HASH_DEL_IN_BKT(hh,head,hh_del)                                          \
-    (head).count--;                                                              \
-    if ((head).hh_head == hh_del) {                                              \
-      (head).hh_head = hh_del->hh_next;                                          \
-    }                                                                            \
-    if (hh_del->hh_prev) {                                                       \
-        hh_del->hh_prev->hh_next = hh_del->hh_next;                              \
-    }                                                                            \
-    if (hh_del->hh_next) {                                                       \
-        hh_del->hh_next->hh_prev = hh_del->hh_prev;                              \
-    }
-
-/* Bucket expansion has the effect of doubling the number of buckets
- * and redistributing the items into the new buckets. Ideally the
- * items will distribute more or less evenly into the new buckets
- * (the extent to which this is true is a measure of the quality of
- * the hash function as it applies to the key domain).
- *
- * With the items distributed into more buckets, the chain length
- * (item count) in each bucket is reduced. Thus by expanding buckets
- * the hash keeps a bound on the chain length. This bounded chain
- * length is the essence of how a hash provides constant time lookup.
- *
- * The calculation of tbl->ideal_chain_maxlen below deserves some
- * explanation. First, keep in mind that we're calculating the ideal
- * maximum chain length based on the *new* (doubled) bucket count.
- * In fractions this is just n/b (n=number of items,b=new num buckets).
- * Since the ideal chain length is an integer, we want to calculate
- * ceil(n/b). We don't depend on floating point arithmetic in this
- * hash, so to calculate ceil(n/b) with integers we could write
- *
- *      ceil(n/b) = (n/b) + ((n%b)?1:0)
- *
- * and in fact a previous version of this hash did just that.
- * But now we have improved things a bit by recognizing that b is
- * always a power of two. We keep its base 2 log handy (call it lb),
- * so now we can write this with a bit shift and logical AND:
- *
- *      ceil(n/b) = (n>>lb) + ( (n & (b-1)) ? 1:0)
- *
- */
-#define HASH_EXPAND_BUCKETS(tbl)                                                 \
-do {                                                                             \
-    unsigned _he_bkt;                                                            \
-    unsigned _he_bkt_i;                                                          \
-    struct UT_hash_handle *_he_thh, *_he_hh_nxt;                                 \
-    UT_hash_bucket *_he_new_buckets, *_he_newbkt;                                \
-    _he_new_buckets = (UT_hash_bucket*)uthash_malloc(                            \
-             2 * tbl->num_buckets * sizeof(struct UT_hash_bucket));              \
-    if (!_he_new_buckets) { uthash_fatal( "out of memory"); }                    \
-    memset(_he_new_buckets, 0,                                                   \
-            2 * tbl->num_buckets * sizeof(struct UT_hash_bucket));               \
-    tbl->ideal_chain_maxlen =                                                    \
-       (tbl->num_items >> (tbl->log2_num_buckets+1)) +                           \
-       ((tbl->num_items & ((tbl->num_buckets*2)-1)) ? 1 : 0);                    \
-    tbl->nonideal_items = 0;                                                     \
-    for(_he_bkt_i = 0; _he_bkt_i < tbl->num_buckets; _he_bkt_i++)                \
-    {                                                                            \
-        _he_thh = tbl->buckets[ _he_bkt_i ].hh_head;                             \
-        while (_he_thh) {                                                        \
-           _he_hh_nxt = _he_thh->hh_next;                                        \
-           HASH_TO_BKT( _he_thh->hashv, tbl->num_buckets*2, _he_bkt);            \
-           _he_newbkt = &(_he_new_buckets[ _he_bkt ]);                           \
-           if (++(_he_newbkt->count) > tbl->ideal_chain_maxlen) {                \
-             tbl->nonideal_items++;                                              \
-             _he_newbkt->expand_mult = _he_newbkt->count /                       \
-                                        tbl->ideal_chain_maxlen;                 \
-           }                                                                     \
-           _he_thh->hh_prev = NULL;                                              \
-           _he_thh->hh_next = _he_newbkt->hh_head;                               \
-           if (_he_newbkt->hh_head) _he_newbkt->hh_head->hh_prev =               \
-                _he_thh;                                                         \
-           _he_newbkt->hh_head = _he_thh;                                        \
-           _he_thh = _he_hh_nxt;                                                 \
-        }                                                                        \
-    }                                                                            \
-    uthash_free( tbl->buckets, tbl->num_buckets*sizeof(struct UT_hash_bucket) ); \
-    tbl->num_buckets *= 2;                                                       \
-    tbl->log2_num_buckets++;                                                     \
-    tbl->buckets = _he_new_buckets;                                              \
-    tbl->ineff_expands = (tbl->nonideal_items > (tbl->num_items >> 1)) ?         \
-        (tbl->ineff_expands+1) : 0;                                              \
-    if (tbl->ineff_expands > 1) {                                                \
-        tbl->noexpand=1;                                                         \
-        uthash_noexpand_fyi(tbl);                                                \
-    }                                                                            \
-    uthash_expand_fyi(tbl);                                                      \
-} while(0)
-
-
-/* This is an adaptation of Simon Tatham's O(n log(n)) mergesort */
-/* Note that HASH_SORT assumes the hash handle name to be hh.
- * HASH_SRT was added to allow the hash handle name to be passed in. */
-#define HASH_SORT(head,cmpfcn) HASH_SRT(hh,head,cmpfcn)
-#define HASH_SRT(hh,head,cmpfcn)                                                 \
-do {                                                                             \
-  unsigned _hs_i;                                                                \
-  unsigned _hs_looping,_hs_nmerges,_hs_insize,_hs_psize,_hs_qsize;               \
-  struct UT_hash_handle *_hs_p, *_hs_q, *_hs_e, *_hs_list, *_hs_tail;            \
-  if (head) {                                                                    \
-      _hs_insize = 1;                                                            \
-      _hs_looping = 1;                                                           \
-      _hs_list = &((head)->hh);                                                  \
-      while (_hs_looping) {                                                      \
-          _hs_p = _hs_list;                                                      \
-          _hs_list = NULL;                                                       \
-          _hs_tail = NULL;                                                       \
-          _hs_nmerges = 0;                                                       \
-          while (_hs_p) {                                                        \
-              _hs_nmerges++;                                                     \
-              _hs_q = _hs_p;                                                     \
-              _hs_psize = 0;                                                     \
-              for ( _hs_i = 0; _hs_i  < _hs_insize; _hs_i++ ) {                  \
-                  _hs_psize++;                                                   \
-                  _hs_q = (UT_hash_handle*)((_hs_q->next) ?                      \
-                          ((void*)((char*)(_hs_q->next) +                        \
-                          (head)->hh.tbl->hho)) : NULL);                         \
-                  if (! (_hs_q) ) break;                                         \
-              }                                                                  \
-              _hs_qsize = _hs_insize;                                            \
-              while ((_hs_psize > 0) || ((_hs_qsize > 0) && _hs_q )) {           \
-                  if (_hs_psize == 0) {                                          \
-                      _hs_e = _hs_q;                                             \
-                      _hs_q = (UT_hash_handle*)((_hs_q->next) ?                  \
-                              ((void*)((char*)(_hs_q->next) +                    \
-                              (head)->hh.tbl->hho)) : NULL);                     \
-                      _hs_qsize--;                                               \
-                  } else if ( (_hs_qsize == 0) || !(_hs_q) ) {                   \
-                      _hs_e = _hs_p;                                             \
-                      if (_hs_p){                                                \
-                        _hs_p = (UT_hash_handle*)((_hs_p->next) ?                \
-                                ((void*)((char*)(_hs_p->next) +                  \
-                                (head)->hh.tbl->hho)) : NULL);                   \
-                       }                                                         \
-                      _hs_psize--;                                               \
-                  } else if ((                                                   \
-                      cmpfcn(DECLTYPE(head)(ELMT_FROM_HH((head)->hh.tbl,_hs_p)), \
-                             DECLTYPE(head)(ELMT_FROM_HH((head)->hh.tbl,_hs_q))) \
-                             ) <= 0) {                                           \
-                      _hs_e = _hs_p;                                             \
-                      if (_hs_p){                                                \
-                        _hs_p = (UT_hash_handle*)((_hs_p->next) ?                \
-                               ((void*)((char*)(_hs_p->next) +                   \
-                               (head)->hh.tbl->hho)) : NULL);                    \
-                       }                                                         \
-                      _hs_psize--;                                               \
-                  } else {                                                       \
-                      _hs_e = _hs_q;                                             \
-                      _hs_q = (UT_hash_handle*)((_hs_q->next) ?                  \
-                              ((void*)((char*)(_hs_q->next) +                    \
-                              (head)->hh.tbl->hho)) : NULL);                     \
-                      _hs_qsize--;                                               \
-                  }                                                              \
-                  if ( _hs_tail ) {                                              \
-                      _hs_tail->next = ((_hs_e) ?                                \
-                            ELMT_FROM_HH((head)->hh.tbl,_hs_e) : NULL);          \
-                  } else {                                                       \
-                      _hs_list = _hs_e;                                          \
-                  }                                                              \
-                  if (_hs_e) {                                                   \
-                  _hs_e->prev = ((_hs_tail) ?                                    \
-                     ELMT_FROM_HH((head)->hh.tbl,_hs_tail) : NULL);              \
-                  }                                                              \
-                  _hs_tail = _hs_e;                                              \
-              }                                                                  \
-              _hs_p = _hs_q;                                                     \
-          }                                                                      \
-          if (_hs_tail){                                                         \
-            _hs_tail->next = NULL;                                               \
-          }                                                                      \
-          if ( _hs_nmerges <= 1 ) {                                              \
-              _hs_looping=0;                                                     \
-              (head)->hh.tbl->tail = _hs_tail;                                   \
-              DECLTYPE_ASSIGN(head,ELMT_FROM_HH((head)->hh.tbl, _hs_list));      \
-          }                                                                      \
-          _hs_insize *= 2;                                                       \
-      }                                                                          \
-      HASH_FSCK(hh,head);                                                        \
- }                                                                               \
-} while (0)
-
-/* This function selects items from one hash into another hash.
- * The end result is that the selected items have dual presence
- * in both hashes. There is no copy of the items made; rather
- * they are added into the new hash through a secondary hash
- * hash handle that must be present in the structure. */
-#define HASH_SELECT(hh_dst, dst, hh_src, src, cond)                              \
-do {                                                                             \
-  unsigned _src_bkt, _dst_bkt;                                                   \
-  void *_last_elt=NULL, *_elt;                                                   \
-  UT_hash_handle *_src_hh, *_dst_hh, *_last_elt_hh=NULL;                         \
-  ptrdiff_t _dst_hho = ((char*)(&(dst)->hh_dst) - (char*)(dst));                 \
-  if (src) {                                                                     \
-    for(_src_bkt=0; _src_bkt < (src)->hh_src.tbl->num_buckets; _src_bkt++) {     \
-      for(_src_hh = (src)->hh_src.tbl->buckets[_src_bkt].hh_head;                \
-          _src_hh;                                                               \
-          _src_hh = _src_hh->hh_next) {                                          \
-          _elt = ELMT_FROM_HH((src)->hh_src.tbl, _src_hh);                       \
-          if (cond(_elt)) {                                                      \
-            _dst_hh = (UT_hash_handle*)(((char*)_elt) + _dst_hho);               \
-            _dst_hh->key = _src_hh->key;                                         \
-            _dst_hh->keylen = _src_hh->keylen;                                   \
-            _dst_hh->hashv = _src_hh->hashv;                                     \
-            _dst_hh->prev = _last_elt;                                           \
-            _dst_hh->next = NULL;                                                \
-            if (_last_elt_hh) { _last_elt_hh->next = _elt; }                     \
-            if (!dst) {                                                          \
-              DECLTYPE_ASSIGN(dst,_elt);                                         \
-              HASH_MAKE_TABLE(hh_dst,dst);                                       \
-            } else {                                                             \
-              _dst_hh->tbl = (dst)->hh_dst.tbl;                                  \
-            }                                                                    \
-            HASH_TO_BKT(_dst_hh->hashv, _dst_hh->tbl->num_buckets, _dst_bkt);    \
-            HASH_ADD_TO_BKT(_dst_hh->tbl->buckets[_dst_bkt],_dst_hh);            \
-            (dst)->hh_dst.tbl->num_items++;                                      \
-            _last_elt = _elt;                                                    \
-            _last_elt_hh = _dst_hh;                                              \
-          }                                                                      \
-      }                                                                          \
-    }                                                                            \
-  }                                                                              \
-  HASH_FSCK(hh_dst,dst);                                                         \
-} while (0)
-
-#define HASH_CLEAR(hh,head)                                                      \
-do {                                                                             \
-  if (head) {                                                                    \
-    uthash_free((head)->hh.tbl->buckets,                                         \
-                (head)->hh.tbl->num_buckets*sizeof(struct UT_hash_bucket));      \
-    HASH_BLOOM_FREE((head)->hh.tbl);                                             \
-    uthash_free((head)->hh.tbl, sizeof(UT_hash_table));                          \
-    (head)=NULL;                                                                 \
-  }                                                                              \
-} while(0)
-
-#define HASH_OVERHEAD(hh,head)                                                   \
- ((head) ? (                                                                     \
- (size_t)((((head)->hh.tbl->num_items   * sizeof(UT_hash_handle))   +            \
-           ((head)->hh.tbl->num_buckets * sizeof(UT_hash_bucket))   +            \
-            (sizeof(UT_hash_table))                                 +            \
-            (HASH_BLOOM_BYTELEN)))) : 0)
-
-#ifdef NO_DECLTYPE
-#define HASH_ITER(hh,head,el,tmp)                                                \
-for((el)=(head), (*(char**)(&(tmp)))=(char*)((head)?(head)->hh.next:NULL);       \
-  el; (el)=(tmp),(*(char**)(&(tmp)))=(char*)((tmp)?(tmp)->hh.next:NULL))
-#else
-#define HASH_ITER(hh,head,el,tmp)                                                \
-for((el)=(head),(tmp)=DECLTYPE(el)((head)?(head)->hh.next:NULL);                 \
-  el; (el)=(tmp),(tmp)=DECLTYPE(el)((tmp)?(tmp)->hh.next:NULL))
-#endif
-
-/* obtain a count of items in the hash */
-#define HASH_COUNT(head) HASH_CNT(hh,head)
-#define HASH_CNT(hh,head) ((head)?((head)->hh.tbl->num_items):0)
-
-typedef struct UT_hash_bucket {
-   struct UT_hash_handle *hh_head;
-   unsigned count;
-
-   /* expand_mult is normally set to 0. In this situation, the max chain length
-    * threshold is enforced at its default value, HASH_BKT_CAPACITY_THRESH. (If
-    * the bucket's chain exceeds this length, bucket expansion is triggered).
-    * However, setting expand_mult to a non-zero value delays bucket expansion
-    * (that would be triggered by additions to this particular bucket)
-    * until its chain length reaches a *multiple* of HASH_BKT_CAPACITY_THRESH.
-    * (The multiplier is simply expand_mult+1). The whole idea of this
-    * multiplier is to reduce bucket expansions, since they are expensive, in
-    * situations where we know that a particular bucket tends to be overused.
-    * It is better to let its chain length grow to a longer yet-still-bounded
-    * value, than to do an O(n) bucket expansion too often.
-    */
-   unsigned expand_mult;
-
-} UT_hash_bucket;
-
-/* random signature used only to find hash tables in external analysis */
-#define HASH_SIGNATURE 0xa0111fe1
-#define HASH_BLOOM_SIGNATURE 0xb12220f2
-
-typedef struct UT_hash_table {
-   UT_hash_bucket *buckets;
-   unsigned num_buckets, log2_num_buckets;
-   unsigned num_items;
-   struct UT_hash_handle *tail; /* tail hh in app order, for fast append    */
-   ptrdiff_t hho; /* hash handle offset (byte pos of hash handle in element */
-
-   /* in an ideal situation (all buckets used equally), no bucket would have
-    * more than ceil(#items/#buckets) items. that's the ideal chain length. */
-   unsigned ideal_chain_maxlen;
-
-   /* nonideal_items is the number of items in the hash whose chain position
-    * exceeds the ideal chain maxlen. these items pay the penalty for an uneven
-    * hash distribution; reaching them in a chain traversal takes >ideal steps */
-   unsigned nonideal_items;
-
-   /* ineffective expands occur when a bucket doubling was performed, but
-    * afterward, more than half the items in the hash had nonideal chain
-    * positions. If this happens on two consecutive expansions we inhibit any
-    * further expansion, as it's not helping; this happens when the hash
-    * function isn't a good fit for the key domain. When expansion is inhibited
-    * the hash will still work, albeit no longer in constant time. */
-   unsigned ineff_expands, noexpand;
-
-   uint32_t signature; /* used only to find hash tables in external analysis */
-#ifdef HASH_BLOOM
-   uint32_t bloom_sig; /* used only to test bloom exists in external analysis */
-   uint8_t *bloom_bv;
-   char bloom_nbits;
-#endif
-
-} UT_hash_table;
-
-typedef struct UT_hash_handle {
-   struct UT_hash_table *tbl;
-   void *prev;                       /* prev element in app order      */
-   void *next;                       /* next element in app order      */
-   struct UT_hash_handle *hh_prev;   /* previous hh in bucket order    */
-   struct UT_hash_handle *hh_next;   /* next hh in bucket order        */
-   void *key;                        /* ptr to enclosing struct's key  */
-   unsigned keylen;                  /* enclosing struct's key len     */
-   unsigned hashv;                   /* result of hash-fcn(key)        */
-} UT_hash_handle;
-
-#endif /* UTHASH_H */
diff --git a/tools/sdk/include/coap/coap/utlist.h b/tools/sdk/include/coap/coap/utlist.h
deleted file mode 100644
index b5f3f04c104..00000000000
--- a/tools/sdk/include/coap/coap/utlist.h
+++ /dev/null
@@ -1,757 +0,0 @@
-/*
-Copyright (c) 2007-2014, Troy D. Hanson   http://troydhanson.github.com/uthash/
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
-OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#ifndef UTLIST_H
-#define UTLIST_H
-
-#define UTLIST_VERSION 1.9.9
-
-#include <assert.h>
-
-/*
- * This file contains macros to manipulate singly and doubly-linked lists.
- *
- * 1. LL_ macros:  singly-linked lists.
- * 2. DL_ macros:  doubly-linked lists.
- * 3. CDL_ macros: circular doubly-linked lists.
- *
- * To use singly-linked lists, your structure must have a "next" pointer.
- * To use doubly-linked lists, your structure must "prev" and "next" pointers.
- * Either way, the pointer to the head of the list must be initialized to NULL.
- *
- * ----------------.EXAMPLE -------------------------
- * struct item {
- *      int id;
- *      struct item *prev, *next;
- * }
- *
- * struct item *list = NULL:
- *
- * int main() {
- *      struct item *item;
- *      ... allocate and populate item ...
- *      DL_APPEND(list, item);
- * }
- * --------------------------------------------------
- *
- * For doubly-linked lists, the append and delete macros are O(1)
- * For singly-linked lists, append and delete are O(n) but prepend is O(1)
- * The sort macro is O(n log(n)) for all types of single/double/circular lists.
- */
-
-/* These macros use decltype or the earlier __typeof GNU extension.
-   As decltype is only available in newer compilers (VS2010 or gcc 4.3+
-   when compiling c++ code), this code uses whatever method is needed
-   or, for VS2008 where neither is available, uses casting workarounds. */
-#ifdef _MSC_VER            /* MS compiler */
-#if _MSC_VER >= 1600 && defined(__cplusplus)  /* VS2010 or newer in C++ mode */
-#define LDECLTYPE(x) decltype(x)
-#else                     /* VS2008 or older (or VS2010 in C mode) */
-#define NO_DECLTYPE
-#define LDECLTYPE(x) char*
-#endif
-#elif defined(__ICCARM__)
-#define NO_DECLTYPE
-#define LDECLTYPE(x) char*
-#else                      /* GNU, Sun and other compilers */
-#define LDECLTYPE(x) __typeof(x)
-#endif
-
-/* for VS2008 we use some workarounds to get around the lack of decltype,
- * namely, we always reassign our tmp variable to the list head if we need
- * to dereference its prev/next pointers, and save/restore the real head.*/
-#ifdef NO_DECLTYPE
-#define _SV(elt,list) _tmp = (char*)(list); {char **_alias = (char**)&(list); *_alias = (elt); }
-#define _NEXT(elt,list,next) ((char*)((list)->next))
-#define _NEXTASGN(elt,list,to,next) { char **_alias = (char**)&((list)->next); *_alias=(char*)(to); }
-/* #define _PREV(elt,list,prev) ((char*)((list)->prev)) */
-#define _PREVASGN(elt,list,to,prev) { char **_alias = (char**)&((list)->prev); *_alias=(char*)(to); }
-#define _RS(list) { char **_alias = (char**)&(list); *_alias=_tmp; }
-#define _CASTASGN(a,b) { char **_alias = (char**)&(a); *_alias=(char*)(b); }
-#else
-#define _SV(elt,list)
-#define _NEXT(elt,list,next) ((elt)->next)
-#define _NEXTASGN(elt,list,to,next) ((elt)->next)=(to)
-/* #define _PREV(elt,list,prev) ((elt)->prev) */
-#define _PREVASGN(elt,list,to,prev) ((elt)->prev)=(to)
-#define _RS(list)
-#define _CASTASGN(a,b) (a)=(b)
-#endif
-
-/******************************************************************************
- * The sort macro is an adaptation of Simon Tatham's O(n log(n)) mergesort    *
- * Unwieldy variable names used here to avoid shadowing passed-in variables.  *
- *****************************************************************************/
-#define LL_SORT(list, cmp)                                                                     \
-    LL_SORT2(list, cmp, next)
-
-#define LL_SORT2(list, cmp, next)                                                              \
-do {                                                                                           \
-  LDECLTYPE(list) _ls_p;                                                                       \
-  LDECLTYPE(list) _ls_q;                                                                       \
-  LDECLTYPE(list) _ls_e;                                                                       \
-  LDECLTYPE(list) _ls_tail;                                                                    \
-  int _ls_insize, _ls_nmerges, _ls_psize, _ls_qsize, _ls_i, _ls_looping;                       \
-  if (list) {                                                                                  \
-    _ls_insize = 1;                                                                            \
-    _ls_looping = 1;                                                                           \
-    while (_ls_looping) {                                                                      \
-      _CASTASGN(_ls_p,list);                                                                   \
-      list = NULL;                                                                             \
-      _ls_tail = NULL;                                                                         \
-      _ls_nmerges = 0;                                                                         \
-      while (_ls_p) {                                                                          \
-        _ls_nmerges++;                                                                         \
-        _ls_q = _ls_p;                                                                         \
-        _ls_psize = 0;                                                                         \
-        for (_ls_i = 0; _ls_i < _ls_insize; _ls_i++) {                                         \
-          _ls_psize++;                                                                         \
-          _SV(_ls_q,list); _ls_q = _NEXT(_ls_q,list,next); _RS(list);                          \
-          if (!_ls_q) break;                                                                   \
-        }                                                                                      \
-        _ls_qsize = _ls_insize;                                                                \
-        while (_ls_psize > 0 || (_ls_qsize > 0 && _ls_q)) {                                    \
-          if (_ls_psize == 0) {                                                                \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-          } else if (_ls_qsize == 0 || !_ls_q) {                                               \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-          } else if (cmp(_ls_p,_ls_q) <= 0) {                                                  \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-          } else {                                                                             \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-          }                                                                                    \
-          if (_ls_tail) {                                                                      \
-            _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,_ls_e,next); _RS(list);                \
-          } else {                                                                             \
-            _CASTASGN(list,_ls_e);                                                             \
-          }                                                                                    \
-          _ls_tail = _ls_e;                                                                    \
-        }                                                                                      \
-        _ls_p = _ls_q;                                                                         \
-      }                                                                                        \
-      if (_ls_tail) {                                                                          \
-        _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,NULL,next); _RS(list);                     \
-      }                                                                                        \
-      if (_ls_nmerges <= 1) {                                                                  \
-        _ls_looping=0;                                                                         \
-      }                                                                                        \
-      _ls_insize *= 2;                                                                         \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-
-#define DL_SORT(list, cmp)                                                                     \
-    DL_SORT2(list, cmp, prev, next)
-
-#define DL_SORT2(list, cmp, prev, next)                                                        \
-do {                                                                                           \
-  LDECLTYPE(list) _ls_p;                                                                       \
-  LDECLTYPE(list) _ls_q;                                                                       \
-  LDECLTYPE(list) _ls_e;                                                                       \
-  LDECLTYPE(list) _ls_tail;                                                                    \
-  int _ls_insize, _ls_nmerges, _ls_psize, _ls_qsize, _ls_i, _ls_looping;                       \
-  if (list) {                                                                                  \
-    _ls_insize = 1;                                                                            \
-    _ls_looping = 1;                                                                           \
-    while (_ls_looping) {                                                                      \
-      _CASTASGN(_ls_p,list);                                                                   \
-      list = NULL;                                                                             \
-      _ls_tail = NULL;                                                                         \
-      _ls_nmerges = 0;                                                                         \
-      while (_ls_p) {                                                                          \
-        _ls_nmerges++;                                                                         \
-        _ls_q = _ls_p;                                                                         \
-        _ls_psize = 0;                                                                         \
-        for (_ls_i = 0; _ls_i < _ls_insize; _ls_i++) {                                         \
-          _ls_psize++;                                                                         \
-          _SV(_ls_q,list); _ls_q = _NEXT(_ls_q,list,next); _RS(list);                          \
-          if (!_ls_q) break;                                                                   \
-        }                                                                                      \
-        _ls_qsize = _ls_insize;                                                                \
-        while (_ls_psize > 0 || (_ls_qsize > 0 && _ls_q)) {                                    \
-          if (_ls_psize == 0) {                                                                \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-          } else if (_ls_qsize == 0 || !_ls_q) {                                               \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-          } else if (cmp(_ls_p,_ls_q) <= 0) {                                                  \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-          } else {                                                                             \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-          }                                                                                    \
-          if (_ls_tail) {                                                                      \
-            _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,_ls_e,next); _RS(list);                \
-          } else {                                                                             \
-            _CASTASGN(list,_ls_e);                                                             \
-          }                                                                                    \
-          _SV(_ls_e,list); _PREVASGN(_ls_e,list,_ls_tail,prev); _RS(list);                     \
-          _ls_tail = _ls_e;                                                                    \
-        }                                                                                      \
-        _ls_p = _ls_q;                                                                         \
-      }                                                                                        \
-      _CASTASGN(list->prev, _ls_tail);                                                         \
-      _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,NULL,next); _RS(list);                       \
-      if (_ls_nmerges <= 1) {                                                                  \
-        _ls_looping=0;                                                                         \
-      }                                                                                        \
-      _ls_insize *= 2;                                                                         \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-#define CDL_SORT(list, cmp)                                                                    \
-    CDL_SORT2(list, cmp, prev, next)
-
-#define CDL_SORT2(list, cmp, prev, next)                                                       \
-do {                                                                                           \
-  LDECLTYPE(list) _ls_p;                                                                       \
-  LDECLTYPE(list) _ls_q;                                                                       \
-  LDECLTYPE(list) _ls_e;                                                                       \
-  LDECLTYPE(list) _ls_tail;                                                                    \
-  LDECLTYPE(list) _ls_oldhead;                                                                 \
-  LDECLTYPE(list) _tmp;                                                                        \
-  int _ls_insize, _ls_nmerges, _ls_psize, _ls_qsize, _ls_i, _ls_looping;                       \
-  if (list) {                                                                                  \
-    _ls_insize = 1;                                                                            \
-    _ls_looping = 1;                                                                           \
-    while (_ls_looping) {                                                                      \
-      _CASTASGN(_ls_p,list);                                                                   \
-      _CASTASGN(_ls_oldhead,list);                                                             \
-      list = NULL;                                                                             \
-      _ls_tail = NULL;                                                                         \
-      _ls_nmerges = 0;                                                                         \
-      while (_ls_p) {                                                                          \
-        _ls_nmerges++;                                                                         \
-        _ls_q = _ls_p;                                                                         \
-        _ls_psize = 0;                                                                         \
-        for (_ls_i = 0; _ls_i < _ls_insize; _ls_i++) {                                         \
-          _ls_psize++;                                                                         \
-          _SV(_ls_q,list);                                                                     \
-          if (_NEXT(_ls_q,list,next) == _ls_oldhead) {                                         \
-            _ls_q = NULL;                                                                      \
-          } else {                                                                             \
-            _ls_q = _NEXT(_ls_q,list,next);                                                    \
-          }                                                                                    \
-          _RS(list);                                                                           \
-          if (!_ls_q) break;                                                                   \
-        }                                                                                      \
-        _ls_qsize = _ls_insize;                                                                \
-        while (_ls_psize > 0 || (_ls_qsize > 0 && _ls_q)) {                                    \
-          if (_ls_psize == 0) {                                                                \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-            if (_ls_q == _ls_oldhead) { _ls_q = NULL; }                                        \
-          } else if (_ls_qsize == 0 || !_ls_q) {                                               \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-            if (_ls_p == _ls_oldhead) { _ls_p = NULL; }                                        \
-          } else if (cmp(_ls_p,_ls_q) <= 0) {                                                  \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-            if (_ls_p == _ls_oldhead) { _ls_p = NULL; }                                        \
-          } else {                                                                             \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-            if (_ls_q == _ls_oldhead) { _ls_q = NULL; }                                        \
-          }                                                                                    \
-          if (_ls_tail) {                                                                      \
-            _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,_ls_e,next); _RS(list);                \
-          } else {                                                                             \
-            _CASTASGN(list,_ls_e);                                                             \
-          }                                                                                    \
-          _SV(_ls_e,list); _PREVASGN(_ls_e,list,_ls_tail,prev); _RS(list);                     \
-          _ls_tail = _ls_e;                                                                    \
-        }                                                                                      \
-        _ls_p = _ls_q;                                                                         \
-      }                                                                                        \
-      _CASTASGN(list->prev,_ls_tail);                                                          \
-      _CASTASGN(_tmp,list);                                                                    \
-      _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,_tmp,next); _RS(list);                       \
-      if (_ls_nmerges <= 1) {                                                                  \
-        _ls_looping=0;                                                                         \
-      }                                                                                        \
-      _ls_insize *= 2;                                                                         \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-/******************************************************************************
- * singly linked list macros (non-circular)                                   *
- *****************************************************************************/
-#define LL_PREPEND(head,add)                                                                   \
-    LL_PREPEND2(head,add,next)
-
-#define LL_PREPEND2(head,add,next)                                                             \
-do {                                                                                           \
-  (add)->next = head;                                                                          \
-  head = add;                                                                                  \
-} while (0)
-
-#define LL_CONCAT(head1,head2)                                                                 \
-    LL_CONCAT2(head1,head2,next)
-
-#define LL_CONCAT2(head1,head2,next)                                                           \
-do {                                                                                           \
-  LDECLTYPE(head1) _tmp;                                                                       \
-  if (head1) {                                                                                 \
-    _tmp = head1;                                                                              \
-    while (_tmp->next) { _tmp = _tmp->next; }                                                  \
-    _tmp->next=(head2);                                                                        \
-  } else {                                                                                     \
-    (head1)=(head2);                                                                           \
-  }                                                                                            \
-} while (0)
-
-#define LL_APPEND(head,add)                                                                    \
-    LL_APPEND2(head,add,next)
-
-#define LL_APPEND2(head,add,next)                                                              \
-do {                                                                                           \
-  LDECLTYPE(head) _tmp;                                                                        \
-  (add)->next=NULL;                                                                            \
-  if (head) {                                                                                  \
-    _tmp = head;                                                                               \
-    while (_tmp->next) { _tmp = _tmp->next; }                                                  \
-    _tmp->next=(add);                                                                          \
-  } else {                                                                                     \
-    (head)=(add);                                                                              \
-  }                                                                                            \
-} while (0)
-
-#define LL_DELETE(head,del)                                                                    \
-    LL_DELETE2(head,del,next)
-
-#define LL_DELETE2(head,del,next)                                                              \
-do {                                                                                           \
-  LDECLTYPE(head) _tmp;                                                                        \
-  if ((head) == (del)) {                                                                       \
-    (head)=(head)->next;                                                                       \
-  } else {                                                                                     \
-    _tmp = head;                                                                               \
-    while (_tmp->next && (_tmp->next != (del))) {                                              \
-      _tmp = _tmp->next;                                                                       \
-    }                                                                                          \
-    if (_tmp->next) {                                                                          \
-      _tmp->next = ((del)->next);                                                              \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-/* Here are VS2008 replacements for LL_APPEND and LL_DELETE */
-#define LL_APPEND_VS2008(head,add)                                                             \
-    LL_APPEND2_VS2008(head,add,next)
-
-#define LL_APPEND2_VS2008(head,add,next)                                                       \
-do {                                                                                           \
-  if (head) {                                                                                  \
-    (add)->next = head;     /* use add->next as a temp variable */                             \
-    while ((add)->next->next) { (add)->next = (add)->next->next; }                             \
-    (add)->next->next=(add);                                                                   \
-  } else {                                                                                     \
-    (head)=(add);                                                                              \
-  }                                                                                            \
-  (add)->next=NULL;                                                                            \
-} while (0)
-
-#define LL_DELETE_VS2008(head,del)                                                             \
-    LL_DELETE2_VS2008(head,del,next)
-
-#define LL_DELETE2_VS2008(head,del,next)                                                       \
-do {                                                                                           \
-  if ((head) == (del)) {                                                                       \
-    (head)=(head)->next;                                                                       \
-  } else {                                                                                     \
-    char *_tmp = (char*)(head);                                                                \
-    while ((head)->next && ((head)->next != (del))) {                                          \
-      head = (head)->next;                                                                     \
-    }                                                                                          \
-    if ((head)->next) {                                                                        \
-      (head)->next = ((del)->next);                                                            \
-    }                                                                                          \
-    {                                                                                          \
-      char **_head_alias = (char**)&(head);                                                    \
-      *_head_alias = _tmp;                                                                     \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-#ifdef NO_DECLTYPE
-#undef LL_APPEND
-#define LL_APPEND LL_APPEND_VS2008
-#undef LL_DELETE
-#define LL_DELETE LL_DELETE_VS2008
-#undef LL_DELETE2
-#define LL_DELETE2 LL_DELETE2_VS2008
-#undef LL_APPEND2
-#define LL_APPEND2 LL_APPEND2_VS2008
-#undef LL_CONCAT /* no LL_CONCAT_VS2008 */
-#undef DL_CONCAT /* no DL_CONCAT_VS2008 */
-#endif
-/* end VS2008 replacements */
-
-#define LL_COUNT(head,el,counter)                                                              \
-    LL_COUNT2(head,el,counter,next)                                                            \
-
-#define LL_COUNT2(head,el,counter,next)                                                        \
-{                                                                                              \
-    counter = 0;                                                                               \
-    LL_FOREACH2(head,el,next){ ++counter; }                                                    \
-}
-
-#define LL_FOREACH(head,el)                                                                    \
-    LL_FOREACH2(head,el,next)
-
-#define LL_FOREACH2(head,el,next)                                                              \
-    for(el=head;el;el=(el)->next)
-
-#define LL_FOREACH_SAFE(head,el,tmp)                                                           \
-    LL_FOREACH_SAFE2(head,el,tmp,next)
-
-#define LL_FOREACH_SAFE2(head,el,tmp,next)                                                     \
-  for((el)=(head);(el) && (tmp = (el)->next, 1); (el) = tmp)
-
-#define LL_SEARCH_SCALAR(head,out,field,val)                                                   \
-    LL_SEARCH_SCALAR2(head,out,field,val,next)
-
-#define LL_SEARCH_SCALAR2(head,out,field,val,next)                                             \
-do {                                                                                           \
-    LL_FOREACH2(head,out,next) {                                                               \
-      if ((out)->field == (val)) break;                                                        \
-    }                                                                                          \
-} while(0)
-
-#define LL_SEARCH(head,out,elt,cmp)                                                            \
-    LL_SEARCH2(head,out,elt,cmp,next)
-
-#define LL_SEARCH2(head,out,elt,cmp,next)                                                      \
-do {                                                                                           \
-    LL_FOREACH2(head,out,next) {                                                               \
-      if ((cmp(out,elt))==0) break;                                                            \
-    }                                                                                          \
-} while(0)
-
-#define LL_REPLACE_ELEM(head, el, add)                                                         \
-do {                                                                                           \
- LDECLTYPE(head) _tmp;                                                                         \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- (add)->next = (el)->next;                                                                     \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
- } else {                                                                                      \
-  _tmp = head;                                                                                 \
-  while (_tmp->next && (_tmp->next != (el))) {                                                 \
-   _tmp = _tmp->next;                                                                          \
-  }                                                                                            \
-  if (_tmp->next) {                                                                            \
-    _tmp->next = (add);                                                                        \
-  }                                                                                            \
- }                                                                                             \
-} while (0)
-
-#define LL_PREPEND_ELEM(head, el, add)                                                         \
-do {                                                                                           \
- LDECLTYPE(head) _tmp;                                                                         \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- (add)->next = (el);                                                                           \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
- } else {                                                                                      \
-  _tmp = head;                                                                                 \
-  while (_tmp->next && (_tmp->next != (el))) {                                                 \
-   _tmp = _tmp->next;                                                                          \
-  }                                                                                            \
-  if (_tmp->next) {                                                                            \
-    _tmp->next = (add);                                                                        \
-  }                                                                                            \
- }                                                                                             \
-} while (0)                                                                                    \
-
-
-/******************************************************************************
- * doubly linked list macros (non-circular)                                   *
- *****************************************************************************/
-#define DL_PREPEND(head,add)                                                                   \
-    DL_PREPEND2(head,add,prev,next)
-
-#define DL_PREPEND2(head,add,prev,next)                                                        \
-do {                                                                                           \
- (add)->next = head;                                                                           \
- if (head) {                                                                                   \
-   (add)->prev = (head)->prev;                                                                 \
-   (head)->prev = (add);                                                                       \
- } else {                                                                                      \
-   (add)->prev = (add);                                                                        \
- }                                                                                             \
- (head) = (add);                                                                               \
-} while (0)
-
-#define DL_APPEND(head,add)                                                                    \
-    DL_APPEND2(head,add,prev,next)
-
-#define DL_APPEND2(head,add,prev,next)                                                         \
-do {                                                                                           \
-  if (head) {                                                                                  \
-      (add)->prev = (head)->prev;                                                              \
-      (head)->prev->next = (add);                                                              \
-      (head)->prev = (add);                                                                    \
-      (add)->next = NULL;                                                                      \
-  } else {                                                                                     \
-      (head)=(add);                                                                            \
-      (head)->prev = (head);                                                                   \
-      (head)->next = NULL;                                                                     \
-  }                                                                                            \
-} while (0)
-
-#define DL_CONCAT(head1,head2)                                                                 \
-    DL_CONCAT2(head1,head2,prev,next)
-
-#define DL_CONCAT2(head1,head2,prev,next)                                                      \
-do {                                                                                           \
-  LDECLTYPE(head1) _tmp;                                                                       \
-  if (head2) {                                                                                 \
-    if (head1) {                                                                               \
-        _tmp = (head2)->prev;                                                                  \
-        (head2)->prev = (head1)->prev;                                                         \
-        (head1)->prev->next = (head2);                                                         \
-        (head1)->prev = _tmp;                                                                  \
-    } else {                                                                                   \
-        (head1)=(head2);                                                                       \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-#define DL_DELETE(head,del)                                                                    \
-    DL_DELETE2(head,del,prev,next)
-
-#define DL_DELETE2(head,del,prev,next)                                                         \
-do {                                                                                           \
-  assert((del)->prev != NULL);                                                                 \
-  if ((del)->prev == (del)) {                                                                  \
-      (head)=NULL;                                                                             \
-  } else if ((del)==(head)) {                                                                  \
-      (del)->next->prev = (del)->prev;                                                         \
-      (head) = (del)->next;                                                                    \
-  } else {                                                                                     \
-      (del)->prev->next = (del)->next;                                                         \
-      if ((del)->next) {                                                                       \
-          (del)->next->prev = (del)->prev;                                                     \
-      } else {                                                                                 \
-          (head)->prev = (del)->prev;                                                          \
-      }                                                                                        \
-  }                                                                                            \
-} while (0)
-
-#define DL_COUNT(head,el,counter)                                                              \
-    DL_COUNT2(head,el,counter,next)                                                            \
-
-#define DL_COUNT2(head,el,counter,next)                                                        \
-{                                                                                              \
-    counter = 0;                                                                               \
-    DL_FOREACH2(head,el,next){ ++counter; }                                                    \
-}
-
-#define DL_FOREACH(head,el)                                                                    \
-    DL_FOREACH2(head,el,next)
-
-#define DL_FOREACH2(head,el,next)                                                              \
-    for(el=head;el;el=(el)->next)
-
-/* this version is safe for deleting the elements during iteration */
-#define DL_FOREACH_SAFE(head,el,tmp)                                                           \
-    DL_FOREACH_SAFE2(head,el,tmp,next)
-
-#define DL_FOREACH_SAFE2(head,el,tmp,next)                                                     \
-  for((el)=(head);(el) && (tmp = (el)->next, 1); (el) = tmp)
-
-/* these are identical to their singly-linked list counterparts */
-#define DL_SEARCH_SCALAR LL_SEARCH_SCALAR
-#define DL_SEARCH LL_SEARCH
-#define DL_SEARCH_SCALAR2 LL_SEARCH_SCALAR2
-#define DL_SEARCH2 LL_SEARCH2
-
-#define DL_REPLACE_ELEM(head, el, add)                                                         \
-do {                                                                                           \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
-  (add)->next = (el)->next;                                                                    \
-  if ((el)->next == NULL) {                                                                    \
-   (add)->prev = (add);                                                                        \
-  } else {                                                                                     \
-   (add)->prev = (el)->prev;                                                                   \
-   (add)->next->prev = (add);                                                                  \
-  }                                                                                            \
- } else {                                                                                      \
-  (add)->next = (el)->next;                                                                    \
-  (add)->prev = (el)->prev;                                                                    \
-  (add)->prev->next = (add);                                                                   \
-  if ((el)->next == NULL) {                                                                    \
-   (head)->prev = (add);                                                                       \
-  } else {                                                                                     \
-   (add)->next->prev = (add);                                                                  \
-  }                                                                                            \
- }                                                                                             \
-} while (0)
-
-#define DL_PREPEND_ELEM(head, el, add)                                                         \
-do {                                                                                           \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- (add)->next = (el);                                                                           \
- (add)->prev = (el)->prev;                                                                     \
- (el)->prev = (add);                                                                           \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
- } else {                                                                                      \
-  (add)->prev->next = (add);                                                                   \
- }                                                                                             \
-} while (0)                                                                                    \
-
-
-/******************************************************************************
- * circular doubly linked list macros                                         *
- *****************************************************************************/
-#define CDL_PREPEND(head,add)                                                                  \
-    CDL_PREPEND2(head,add,prev,next)
-
-#define CDL_PREPEND2(head,add,prev,next)                                                       \
-do {                                                                                           \
- if (head) {                                                                                   \
-   (add)->prev = (head)->prev;                                                                 \
-   (add)->next = (head);                                                                       \
-   (head)->prev = (add);                                                                       \
-   (add)->prev->next = (add);                                                                  \
- } else {                                                                                      \
-   (add)->prev = (add);                                                                        \
-   (add)->next = (add);                                                                        \
- }                                                                                             \
-(head)=(add);                                                                                  \
-} while (0)
-
-#define CDL_DELETE(head,del)                                                                   \
-    CDL_DELETE2(head,del,prev,next)
-
-#define CDL_DELETE2(head,del,prev,next)                                                        \
-do {                                                                                           \
-  if ( ((head)==(del)) && ((head)->next == (head))) {                                          \
-      (head) = 0L;                                                                             \
-  } else {                                                                                     \
-     (del)->next->prev = (del)->prev;                                                          \
-     (del)->prev->next = (del)->next;                                                          \
-     if ((del) == (head)) (head)=(del)->next;                                                  \
-  }                                                                                            \
-} while (0)
-
-#define CDL_COUNT(head,el,counter)                                                             \
-    CDL_COUNT2(head,el,counter,next)                                                           \
-
-#define CDL_COUNT2(head, el, counter,next)                                                     \
-{                                                                                              \
-    counter = 0;                                                                               \
-    CDL_FOREACH2(head,el,next){ ++counter; }                                                   \
-}
-
-#define CDL_FOREACH(head,el)                                                                   \
-    CDL_FOREACH2(head,el,next)
-
-#define CDL_FOREACH2(head,el,next)                                                             \
-    for(el=head;el;el=((el)->next==head ? 0L : (el)->next))
-
-#define CDL_FOREACH_SAFE(head,el,tmp1,tmp2)                                                    \
-    CDL_FOREACH_SAFE2(head,el,tmp1,tmp2,prev,next)
-
-#define CDL_FOREACH_SAFE2(head,el,tmp1,tmp2,prev,next)                                         \
-  for((el)=(head), ((tmp1)=(head)?((head)->prev):NULL);                                        \
-      (el) && ((tmp2)=(el)->next, 1);                                                          \
-      ((el) = (((el)==(tmp1)) ? 0L : (tmp2))))
-
-#define CDL_SEARCH_SCALAR(head,out,field,val)                                                  \
-    CDL_SEARCH_SCALAR2(head,out,field,val,next)
-
-#define CDL_SEARCH_SCALAR2(head,out,field,val,next)                                            \
-do {                                                                                           \
-    CDL_FOREACH2(head,out,next) {                                                              \
-      if ((out)->field == (val)) break;                                                        \
-    }                                                                                          \
-} while(0)
-
-#define CDL_SEARCH(head,out,elt,cmp)                                                           \
-    CDL_SEARCH2(head,out,elt,cmp,next)
-
-#define CDL_SEARCH2(head,out,elt,cmp,next)                                                     \
-do {                                                                                           \
-    CDL_FOREACH2(head,out,next) {                                                              \
-      if ((cmp(out,elt))==0) break;                                                            \
-    }                                                                                          \
-} while(0)
-
-#define CDL_REPLACE_ELEM(head, el, add)                                                        \
-do {                                                                                           \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- if ((el)->next == (el)) {                                                                     \
-  (add)->next = (add);                                                                         \
-  (add)->prev = (add);                                                                         \
-  (head) = (add);                                                                              \
- } else {                                                                                      \
-  (add)->next = (el)->next;                                                                    \
-  (add)->prev = (el)->prev;                                                                    \
-  (add)->next->prev = (add);                                                                   \
-  (add)->prev->next = (add);                                                                   \
-  if ((head) == (el)) {                                                                        \
-   (head) = (add);                                                                             \
-  }                                                                                            \
- }                                                                                             \
-} while (0)
-
-#define CDL_PREPEND_ELEM(head, el, add)                                                        \
-do {                                                                                           \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- (add)->next = (el);                                                                           \
- (add)->prev = (el)->prev;                                                                     \
- (el)->prev = (add);                                                                           \
- (add)->prev->next = (add);                                                                    \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
- }                                                                                             \
-} while (0)                                                                                    \
-
-#endif /* UTLIST_H */
-
diff --git a/tools/sdk/include/coap/coap_config.h b/tools/sdk/include/coap/coap_config.h
deleted file mode 100644
index db314f2de90..00000000000
--- a/tools/sdk/include/coap/coap_config.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * libcoap configure implementation for ESP32 platform.
- *
- * Uses libcoap software implementation for failover when concurrent
- * configure operations are in use.
- *
- * coap.h -- main header file for CoAP stack of libcoap
- *
- * Copyright (C) 2010-2012,2015-2016 Olaf Bergmann <bergmann@tzi.org>
- *               2015 Carsten Schoenert <c.schoenert@t-online.de>
- *
- * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _CONFIG_H_
-#define _CONFIG_H_
-
-#ifdef WITH_POSIX
-#include "coap_config_posix.h"
-#endif
-
-#define HAVE_STDIO_H
-#define HAVE_ASSERT_H
-
-#define PACKAGE_STRING PACKAGE_NAME PACKAGE_VERSION
-
-/* it's just provided by libc. i hope we don't get too many of those, as
- * actually we'd need autotools again to find out what environment we're
- * building in */
-#define HAVE_STRNLEN 1
-
-#define HAVE_LIMITS_H
-
-#define COAP_RESOURCES_NOHASH
-
-#endif /* _CONFIG_H_ */
diff --git a/tools/sdk/include/coap/coap_config_posix.h b/tools/sdk/include/coap/coap_config_posix.h
deleted file mode 100644
index a77e97f074e..00000000000
--- a/tools/sdk/include/coap/coap_config_posix.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * libcoap configure implementation for ESP32 platform.
- *
- * Uses libcoap software implementation for failover when concurrent
- * configure operations are in use.
- *
- * coap.h -- main header file for CoAP stack of libcoap
- *
- * Copyright (C) 2010-2012,2015-2016 Olaf Bergmann <bergmann@tzi.org>
- *               2015 Carsten Schoenert <c.schoenert@t-online.de>
- *
- * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef COAP_CONFIG_POSIX_H_
-#define COAP_CONFIG_POSIX_H_
-
-#ifdef WITH_POSIX
-
-#include <sys/socket.h>
-
-#define HAVE_SYS_SOCKET_H
-#define HAVE_MALLOC
-#define HAVE_ARPA_INET_H
-
-#define IP_PKTINFO   IP_MULTICAST_IF
-#define IPV6_PKTINFO IPV6_V6ONLY
-
-#define PACKAGE_NAME "libcoap-posix"
-#define PACKAGE_VERSION "?"
-
-#define CUSTOM_COAP_NETWORK_ENDPOINT
-#define CUSTOM_COAP_NETWORK_SEND
-#define CUSTOM_COAP_NETWORK_READ
-
-#endif
-
-#endif /* COAP_CONFIG_POSIX_H_ */
diff --git a/tools/sdk/include/coap/coap_io.h b/tools/sdk/include/coap/coap_io.h
deleted file mode 100644
index 7a48b319a1d..00000000000
--- a/tools/sdk/include/coap/coap_io.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * coap_io.h -- Default network I/O functions for libcoap
- *
- * Copyright (C) 2012-2013 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_IO_H_
-#define _COAP_IO_H_
-
-#include <assert.h>
-#include <sys/types.h>
-
-#include "address.h"
-
-/**
- * Abstract handle that is used to identify a local network interface.
- */
-typedef int coap_if_handle_t;
-
-/** Invalid interface handle */
-#define COAP_IF_INVALID -1
-
-struct coap_packet_t;
-typedef struct coap_packet_t coap_packet_t;
-
-struct coap_context_t;
-
-/**
- * Abstraction of virtual endpoint that can be attached to coap_context_t. The
- * tuple (handle, addr) must uniquely identify this endpoint.
- */
-typedef struct coap_endpoint_t {
-#if defined(WITH_POSIX) || defined(WITH_CONTIKI)
-  union {
-    int fd;       /**< on POSIX systems */
-    void *conn;   /**< opaque connection (e.g. uip_conn in Contiki) */
-  } handle;       /**< opaque handle to identify this endpoint */
-#endif /* WITH_POSIX or WITH_CONTIKI */
-
-#ifdef WITH_LWIP
-  struct udp_pcb *pcb;
- /**< @FIXME --chrysn
-  * this was added in a hurry, not sure it confirms to the overall model */
-  struct coap_context_t *context;
-#endif /* WITH_LWIP */
-
-  coap_address_t addr; /**< local interface address */
-  int ifindex;
-  int flags;
-} coap_endpoint_t;
-
-#define COAP_ENDPOINT_NOSEC 0x00
-#define COAP_ENDPOINT_DTLS  0x01
-
-coap_endpoint_t *coap_new_endpoint(const coap_address_t *addr, int flags);
-
-void coap_free_endpoint(coap_endpoint_t *ep);
-
-/**
- * Function interface for data transmission. This function returns the number of
- * bytes that have been transmitted, or a value less than zero on error.
- *
- * @param context          The calling CoAP context.
- * @param local_interface  The local interface to send the data.
- * @param dst              The address of the receiver.
- * @param data             The data to send.
- * @param datalen          The actual length of @p data.
- *
- * @return                 The number of bytes written on success, or a value
- *                         less than zero on error.
- */
-ssize_t coap_network_send(struct coap_context_t *context,
-                          const coap_endpoint_t *local_interface,
-                          const coap_address_t *dst,
-                          unsigned char *data, size_t datalen);
-
-/**
- * Function interface for reading data. This function returns the number of
- * bytes that have been read, or a value less than zero on error. In case of an
- * error, @p *packet is set to NULL.
- *
- * @param ep     The endpoint that is used for reading data from the network.
- * @param packet A result parameter where a pointer to the received packet
- *               structure is stored. The caller must call coap_free_packet to
- *               release the storage used by this packet.
- *
- * @return       The number of bytes received on success, or a value less than
- *               zero on error.
- */
-ssize_t coap_network_read(coap_endpoint_t *ep, coap_packet_t **packet);
-
-#ifndef coap_mcast_interface
-# define coap_mcast_interface(Local) 0
-#endif
-
-/**
- * Releases the storage allocated for @p packet.
- */
-void coap_free_packet(coap_packet_t *packet);
-
-/**
- * Populate the coap_endpoint_t *target from the incoming packet's destination
- * data.
- *
- * This is usually used to copy a packet's data into a node's local_if member.
- */
-void coap_packet_populate_endpoint(coap_packet_t *packet,
-                                   coap_endpoint_t *target);
-
-/**
- * Given an incoming packet, copy its source address into an address struct.
- */
-void coap_packet_copy_source(coap_packet_t *packet, coap_address_t *target);
-
-/**
- * Given a packet, set msg and msg_len to an address and length of the packet's
- * data in memory.
- * */
-void coap_packet_get_memmapped(coap_packet_t *packet,
-                               unsigned char **address,
-                               size_t *length);
-
-#ifdef WITH_LWIP
-/**
- * Get the pbuf of a packet. The caller takes over responsibility for freeing
- * the pbuf.
- */
-struct pbuf *coap_packet_extract_pbuf(coap_packet_t *packet);
-#endif
-
-#ifdef WITH_CONTIKI
-/*
- * This is only included in coap_io.h instead of .c in order to be available for
- * sizeof in mem.c.
- */
-struct coap_packet_t {
-  coap_if_handle_t hnd;         /**< the interface handle */
-  coap_address_t src;           /**< the packet's source address */
-  coap_address_t dst;           /**< the packet's destination address */
-  const coap_endpoint_t *interface;
-  int ifindex;
-  void *session;                /**< opaque session data */
-  size_t length;                /**< length of payload */
-  unsigned char payload[];      /**< payload */
-};
-#endif
-
-#ifdef WITH_LWIP
-/*
- * This is only included in coap_io.h instead of .c in order to be available for
- * sizeof in lwippools.h.
- * Simple carry-over of the incoming pbuf that is later turned into a node.
- *
- * Source address data is currently side-banded via ip_current_dest_addr & co
- * as the packets have limited lifetime anyway.
- */
-struct coap_packet_t {
-  struct pbuf *pbuf;
-  const coap_endpoint_t *local_interface;
-  uint16_t srcport;
-};
-#endif
-
-#endif /* _COAP_IO_H_ */
diff --git a/tools/sdk/include/coap/coap_time.h b/tools/sdk/include/coap/coap_time.h
deleted file mode 100644
index 9357e5ff7d0..00000000000
--- a/tools/sdk/include/coap/coap_time.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * coap_time.h -- Clock Handling
- *
- * Copyright (C) 2010-2013 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file coap_time.h
- * @brief Clock Handling
- */
-
-#ifndef _COAP_TIME_H_
-#define _COAP_TIME_H_
-
-/**
- * @defgroup clock Clock Handling
- * Default implementation of internal clock.
- * @{
- */
-
-#ifdef WITH_LWIP
-
-#include <stdint.h>
-#include <lwip/sys.h>
-
-/* lwIP provides ms in sys_now */
-#define COAP_TICKS_PER_SECOND 1000
-
-typedef uint32_t coap_tick_t;
-typedef uint32_t coap_time_t;
-typedef int32_t coap_tick_diff_t;
-
-static inline void coap_ticks_impl(coap_tick_t *t) {
-  *t = sys_now();
-}
-
-static inline void coap_clock_init_impl(void) {
-}
-
-#define coap_clock_init coap_clock_init_impl
-#define coap_ticks coap_ticks_impl
-
-static inline coap_time_t coap_ticks_to_rt(coap_tick_t t) {
-  return t / COAP_TICKS_PER_SECOND;
-}
-#endif
-
-#ifdef WITH_CONTIKI
-#include "clock.h"
-
-typedef clock_time_t coap_tick_t;
-typedef clock_time_t coap_time_t;
-
-/**
- * This data type is used to represent the difference between two clock_tick_t
- * values. This data type must have the same size in memory as coap_tick_t to
- * allow wrapping.
- */
-typedef int coap_tick_diff_t;
-
-#define COAP_TICKS_PER_SECOND CLOCK_SECOND
-
-static inline void coap_clock_init(void) {
-  clock_init();
-}
-
-static inline void coap_ticks(coap_tick_t *t) {
-  *t = clock_time();
-}
-
-static inline coap_time_t coap_ticks_to_rt(coap_tick_t t) {
-  return t / COAP_TICKS_PER_SECOND;
-}
-#endif /* WITH_CONTIKI */
-
-#ifdef WITH_POSIX
-/**
- * This data type represents internal timer ticks with COAP_TICKS_PER_SECOND
- * resolution.
- */
-typedef unsigned long coap_tick_t;
-
-/**
- * CoAP time in seconds since epoch.
- */
-typedef time_t coap_time_t;
-
-/**
- * This data type is used to represent the difference between two clock_tick_t
- * values. This data type must have the same size in memory as coap_tick_t to
- * allow wrapping.
- */
-typedef long coap_tick_diff_t;
-
-/** Use ms resolution on POSIX systems */
-#define COAP_TICKS_PER_SECOND 1000
-
-/**
- * Initializes the internal clock.
- */
-void coap_clock_init(void);
-
-/**
- * Sets @p t to the internal time with COAP_TICKS_PER_SECOND resolution.
- */
-void coap_ticks(coap_tick_t *t);
-
-/**
- * Helper function that converts coap ticks to wallclock time. On POSIX, this
- * function returns the number of seconds since the epoch. On other systems, it
- * may be the calculated number of seconds since last reboot or so.
- *
- * @param t Internal system ticks.
- *
- * @return  The number of seconds that has passed since a specific reference
- *          point (seconds since epoch on POSIX).
- */
-coap_time_t coap_ticks_to_rt(coap_tick_t t);
-#endif /* WITH_POSIX */
-
-/**
- * Returns @c 1 if and only if @p a is less than @p b where less is defined on a
- * signed data type.
- */
-static inline int coap_time_lt(coap_tick_t a, coap_tick_t b) {
-  return ((coap_tick_diff_t)(a - b)) < 0;
-}
-
-/**
- * Returns @c 1 if and only if @p a is less than or equal @p b where less is
- * defined on a signed data type.
- */
-static inline int coap_time_le(coap_tick_t a, coap_tick_t b) {
-  return a == b || coap_time_lt(a,b);
-}
-
-/** @} */
-
-#endif /* _COAP_TIME_H_ */
diff --git a/tools/sdk/include/coap/debug.h b/tools/sdk/include/coap/debug.h
deleted file mode 100644
index e7c86aff517..00000000000
--- a/tools/sdk/include/coap/debug.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * debug.h -- debug utilities
- *
- * Copyright (C) 2010-2011,2014 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_DEBUG_H_
-#define _COAP_DEBUG_H_
-
-#ifndef COAP_DEBUG_FD
-#define COAP_DEBUG_FD stdout
-#endif
-
-#ifndef COAP_ERR_FD
-#define COAP_ERR_FD stderr
-#endif
-
-#ifdef HAVE_SYSLOG_H
-#include <syslog.h>
-typedef short coap_log_t;
-#else
-/** Pre-defined log levels akin to what is used in \b syslog. */
-typedef enum {
-  LOG_EMERG=0,
-  LOG_ALERT,
-  LOG_CRIT,
-  LOG_ERR,
-  LOG_WARNING,
-  LOG_NOTICE,
-  LOG_INFO,
-  LOG_DEBUG
-} coap_log_t;
-#endif
-
-/** Returns the current log level. */
-coap_log_t coap_get_log_level(void);
-
-/** Sets the log level to the specified value. */
-void coap_set_log_level(coap_log_t level);
-
-/** Returns a zero-terminated string with the name of this library. */
-const char *coap_package_name(void);
-
-/** Returns a zero-terminated string with the library version. */
-const char *coap_package_version(void);
-
-/**
- * Writes the given text to @c COAP_ERR_FD (for @p level <= @c LOG_CRIT) or @c
- * COAP_DEBUG_FD (for @p level >= @c LOG_WARNING). The text is output only when
- * @p level is below or equal to the log level that set by coap_set_log_level().
- */
-void coap_log_impl(coap_log_t level, const char *format, ...);
-
-#ifndef coap_log
-#define coap_log(...) coap_log_impl(__VA_ARGS__)
-#endif
-
-#ifndef NDEBUG
-
-/* A set of convenience macros for common log levels. */
-#define info(...) coap_log(LOG_INFO, __VA_ARGS__)
-#define warn(...) coap_log(LOG_WARNING, __VA_ARGS__)
-#define debug(...) coap_log(LOG_DEBUG, __VA_ARGS__)
-
-#include "pdu.h"
-void coap_show_pdu(const coap_pdu_t *);
-
-struct coap_address_t;
-size_t coap_print_addr(const struct coap_address_t *, unsigned char *, size_t);
-
-#else
-
-#define debug(...)
-#define info(...)
-#define warn(...)
-
-#define coap_show_pdu(x)
-#define coap_print_addr(...)
-
-#endif /* NDEBUG */
-
-#endif /* _COAP_DEBUG_H_ */
diff --git a/tools/sdk/include/coap/encode.h b/tools/sdk/include/coap/encode.h
deleted file mode 100644
index a5d290c4ecf..00000000000
--- a/tools/sdk/include/coap/encode.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * encode.h -- encoding and decoding of CoAP data types
- *
- * Copyright (C) 2010-2012 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_ENCODE_H_
-#define _COAP_ENCODE_H_
-
-#if (BSD >= 199103) || defined(WITH_CONTIKI)
-# include <string.h>
-#else
-# include <strings.h>
-#endif
-
-#define Nn 8  /* duplicate definition of N if built on sky motes */
-#define ENCODE_HEADER_SIZE 4
-#define HIBIT (1 << (Nn - 1))
-#define EMASK ((1 << ENCODE_HEADER_SIZE) - 1)
-#define MMASK ((1 << Nn) - 1 - EMASK)
-#define MAX_VALUE ( (1 << Nn) - (1 << ENCODE_HEADER_SIZE) ) * (1 << ((1 << ENCODE_HEADER_SIZE) - 1))
-
-#define COAP_PSEUDOFP_DECODE_8_4(r) (r < HIBIT ? r : (r & MMASK) << (r & EMASK))
-
-#ifndef HAVE_FLS
-/* include this only if fls() is not available */
-extern int coap_fls(unsigned int i);
-#else
-#define coap_fls(i) fls(i)
-#endif
-
-/* ls and s must be integer variables */
-#define COAP_PSEUDOFP_ENCODE_8_4_DOWN(v,ls) (v < HIBIT ? v : (ls = coap_fls(v) - Nn, (v >> ls) & MMASK) + ls)
-#define COAP_PSEUDOFP_ENCODE_8_4_UP(v,ls,s) (v < HIBIT ? v : (ls = coap_fls(v) - Nn, (s = (((v + ((1<<ENCODE_HEADER_SIZE<<ls)-1)) >> ls) & MMASK)), s == 0 ? HIBIT + ls + 1 : s + ls))
-
-/**
- * Decodes multiple-length byte sequences. buf points to an input byte sequence
- * of length len. Returns the decoded value.
- */
-unsigned int coap_decode_var_bytes(unsigned char *buf,unsigned int len);
-
-/**
- * Encodes multiple-length byte sequences. buf points to an output buffer of
- * sufficient length to store the encoded bytes. val is the value to encode.
- * Returns the number of bytes used to encode val or 0 on error.
- */
-unsigned int coap_encode_var_bytes(unsigned char *buf, unsigned int val);
-
-#endif /* _COAP_ENCODE_H_ */
diff --git a/tools/sdk/include/coap/hashkey.h b/tools/sdk/include/coap/hashkey.h
deleted file mode 100644
index 5cff67d2d8a..00000000000
--- a/tools/sdk/include/coap/hashkey.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * hashkey.h -- definition of hash key type and helper functions
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file hashkey.h
- * @brief definition of hash key type and helper functions
- */
-
-#ifndef _COAP_HASHKEY_H_
-#define _COAP_HASHKEY_H_
-
-#include "str.h"
-
-typedef unsigned char coap_key_t[4];
-
-#ifndef coap_hash
-/**
- * Calculates a fast hash over the given string @p s of length @p len and stores
- * the result into @p h. Depending on the exact implementation, this function
- * cannot be used as one-way function to check message integrity or simlar.
- *
- * @param s   The string used for hash calculation.
- * @param len The length of @p s.
- * @param h   The result buffer to store the calculated hash key.
- */
-void coap_hash_impl(const unsigned char *s, unsigned int len, coap_key_t h);
-
-#define coap_hash(String,Length,Result) \
-  coap_hash_impl((String),(Length),(Result))
-
-/* This is used to control the pre-set hash-keys for resources. */
-#define __COAP_DEFAULT_HASH
-#else
-#undef __COAP_DEFAULT_HASH
-#endif /* coap_hash */
-
-/**
- * Calls coap_hash() with given @c str object as parameter.
- *
- * @param Str Must contain a pointer to a coap string object.
- * @param H   A coap_key_t object to store the result.
- *
- * @hideinitializer
- */
-#define coap_str_hash(Str,H) {               \
-    assert(Str);                             \
-    memset((H), 0, sizeof(coap_key_t));      \
-    coap_hash((Str)->s, (Str)->length, (H)); \
-  }
-
-#endif /* _COAP_HASHKEY_H_ */
diff --git a/tools/sdk/include/coap/libcoap.h b/tools/sdk/include/coap/libcoap.h
deleted file mode 100644
index 214b9e235e8..00000000000
--- a/tools/sdk/include/coap/libcoap.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * libcoap.h -- platform specific header file for CoAP stack
- *
- * Copyright (C) 2015 Carsten Schoenert <c.schoenert@t-online.de>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _LIBCOAP_H_
-#define _LIBCOAP_H_
-
-/* The non posix embedded platforms like Contiki, TinyOS, RIOT, ... doesn't have
- * a POSIX compatible header structure so we have to slightly do some platform
- * related things. Currently there is only Contiki available so we check for a
- * CONTIKI environment and do *not* include the POSIX related network stuff. If
- * there are other platforms in future there need to be analogous environments.
- *
- * The CONTIKI variable is within the Contiki build environment! */
-
-#if !defined (CONTIKI) 
-#include <netinet/in.h>
-#include <sys/socket.h>
-#endif /* CONTIKI */
-
-#endif /* _LIBCOAP_H_ */
diff --git a/tools/sdk/include/coap/lwippools.h b/tools/sdk/include/coap/lwippools.h
deleted file mode 100644
index 0bfb3f527a7..00000000000
--- a/tools/sdk/include/coap/lwippools.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/** Memory pool definitions for the libcoap when used with lwIP (which has its
- * own mechanism for quickly allocating chunks of data with known sizes). Has
- * to be findable by lwIP (ie. an #include <lwippools.h> must either directly
- * include this or include something more generic which includes this), and
- * MEMP_USE_CUSTOM_POOLS has to be set in lwipopts.h. */
-
-#include "coap_config.h"
-#include <net.h>
-#include <resource.h>
-#include <subscribe.h>
-
-#ifndef MEMP_NUM_COAPCONTEXT
-#define MEMP_NUM_COAPCONTEXT 1
-#endif
-
-#ifndef MEMP_NUM_COAPENDPOINT
-#define MEMP_NUM_COAPENDPOINT 1
-#endif
-
-/* 1 is sufficient as this is very short-lived */
-#ifndef MEMP_NUM_COAPPACKET
-#define MEMP_NUM_COAPPACKET 1
-#endif
-
-#ifndef MEMP_NUM_COAPNODE
-#define MEMP_NUM_COAPNODE 4
-#endif
-
-#ifndef MEMP_NUM_COAPPDU
-#define MEMP_NUM_COAPPDU MEMP_NUM_COAPNODE
-#endif
-
-#ifndef MEMP_NUM_COAP_SUBSCRIPTION
-#define MEMP_NUM_COAP_SUBSCRIPTION 4
-#endif
-
-#ifndef MEMP_NUM_COAPRESOURCE
-#define MEMP_NUM_COAPRESOURCE 10
-#endif
-
-#ifndef MEMP_NUM_COAPRESOURCEATTR
-#define MEMP_NUM_COAPRESOURCEATTR 20
-#endif
-
-LWIP_MEMPOOL(COAP_CONTEXT, MEMP_NUM_COAPCONTEXT, sizeof(coap_context_t), "COAP_CONTEXT")
-LWIP_MEMPOOL(COAP_ENDPOINT, MEMP_NUM_COAPENDPOINT, sizeof(coap_endpoint_t), "COAP_ENDPOINT")
-LWIP_MEMPOOL(COAP_PACKET, MEMP_NUM_COAPPACKET, sizeof(coap_packet_t), "COAP_PACKET")
-LWIP_MEMPOOL(COAP_NODE, MEMP_NUM_COAPNODE, sizeof(coap_queue_t), "COAP_NODE")
-LWIP_MEMPOOL(COAP_PDU, MEMP_NUM_COAPPDU, sizeof(coap_pdu_t), "COAP_PDU")
-LWIP_MEMPOOL(COAP_subscription, MEMP_NUM_COAP_SUBSCRIPTION, sizeof(coap_subscription_t), "COAP_subscription")
-LWIP_MEMPOOL(COAP_RESOURCE, MEMP_NUM_COAPRESOURCE, sizeof(coap_resource_t), "COAP_RESOURCE")
-LWIP_MEMPOOL(COAP_RESOURCEATTR, MEMP_NUM_COAPRESOURCEATTR, sizeof(coap_attr_t), "COAP_RESOURCEATTR")
diff --git a/tools/sdk/include/coap/mem.h b/tools/sdk/include/coap/mem.h
deleted file mode 100644
index fd3c69aafde..00000000000
--- a/tools/sdk/include/coap/mem.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * mem.h -- CoAP memory handling
- *
- * Copyright (C) 2010-2011,2014-2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_MEM_H_
-#define _COAP_MEM_H_
-
-#include <stdlib.h>
-
-#ifndef WITH_LWIP
-/**
- * Initializes libcoap's memory management.
- * This function must be called once before coap_malloc() can be used on
- * constrained devices.
- */
-void coap_memory_init(void);
-#endif /* WITH_LWIP */
-
-/**
- * Type specifiers for coap_malloc_type(). Memory objects can be typed to
- * facilitate arrays of type objects to be used instead of dynamic memory
- * management on constrained devices.
- */
-typedef enum {
-  COAP_STRING,
-  COAP_ATTRIBUTE_NAME,
-  COAP_ATTRIBUTE_VALUE,
-  COAP_PACKET,
-  COAP_NODE,
-  COAP_CONTEXT,
-  COAP_ENDPOINT,
-  COAP_PDU,
-  COAP_PDU_BUF,
-  COAP_RESOURCE,
-  COAP_RESOURCEATTR
-} coap_memory_tag_t;
-
-#ifndef WITH_LWIP
-
-/**
- * Allocates a chunk of @p size bytes and returns a pointer to the newly
- * allocated memory. The @p type is used to select the appropriate storage
- * container on constrained devices. The storage allocated by coap_malloc_type()
- * must be released with coap_free_type().
- *
- * @param type The type of object to be stored.
- * @param size The number of bytes requested.
- * @return     A pointer to the allocated storage or @c NULL on error.
- */
-void *coap_malloc_type(coap_memory_tag_t type, size_t size);
-
-/**
- * Releases the memory that was allocated by coap_malloc_type(). The type tag @p
- * type must be the same that was used for allocating the object pointed to by
- * @p .
- *
- * @param type The type of the object to release.
- * @param p    A pointer to memory that was allocated by coap_malloc_type().
- */
-void coap_free_type(coap_memory_tag_t type, void *p);
-
-/**
- * Wrapper function to coap_malloc_type() for backwards compatibility.
- */
-static inline void *coap_malloc(size_t size) {
-  return coap_malloc_type(COAP_STRING, size);
-}
-
-/**
- * Wrapper function to coap_free_type() for backwards compatibility.
- */
-static inline void coap_free(void *object) {
-  coap_free_type(COAP_STRING, object);
-}
-
-#endif /* not WITH_LWIP */
-
-#ifdef WITH_LWIP
-
-#include <lwip/memp.h>
-
-/* no initialization needed with lwip (or, more precisely: lwip must be
- * completely initialized anyway by the time coap gets active)  */
-static inline void coap_memory_init(void) {}
-
-/* It would be nice to check that size equals the size given at the memp
- * declaration, but i currently don't see a standard way to check that without
- * sourcing the custom memp pools and becoming dependent of its syntax
- */
-#define coap_malloc_type(type, size) memp_malloc(MEMP_ ## type)
-#define coap_free_type(type, p) memp_free(MEMP_ ## type, p)
-
-/* Those are just here to make uri.c happy where string allocation has not been
- * made conditional.
- */
-static inline void *coap_malloc(size_t size) {
-  LWIP_ASSERT("coap_malloc must not be used in lwIP", 0);
-}
-
-static inline void coap_free(void *pointer) {
-  LWIP_ASSERT("coap_free must not be used in lwIP", 0);
-}
-
-#endif /* WITH_LWIP */
-
-#endif /* _COAP_MEM_H_ */
diff --git a/tools/sdk/include/coap/net.h b/tools/sdk/include/coap/net.h
deleted file mode 100644
index 014b4903ab4..00000000000
--- a/tools/sdk/include/coap/net.h
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * net.h -- CoAP network interface
- *
- * Copyright (C) 2010-2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_NET_H_
-#define _COAP_NET_H_
-
-#include <assert.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/time.h>
-#include <time.h>
-
-#ifdef WITH_LWIP
-#include <lwip/ip_addr.h>
-#endif
-
-#include "coap_io.h"
-#include "coap_time.h"
-#include "option.h"
-#include "pdu.h"
-#include "prng.h"
-
-struct coap_queue_t;
-
-typedef struct coap_queue_t {
-  struct coap_queue_t *next;
-  coap_tick_t t;                /**< when to send PDU for the next time */
-  unsigned char retransmit_cnt; /**< retransmission counter, will be removed
-                                 *    when zero */
-  unsigned int timeout;         /**< the randomized timeout value */
-  coap_endpoint_t local_if;     /**< the local address interface */
-  coap_address_t remote;        /**< remote address */
-  coap_tid_t id;                /**< unique transaction id */
-  coap_pdu_t *pdu;              /**< the CoAP PDU to send */
-} coap_queue_t;
-
-/** Adds node to given queue, ordered by node->t. */
-int coap_insert_node(coap_queue_t **queue, coap_queue_t *node);
-
-/** Destroys specified node. */
-int coap_delete_node(coap_queue_t *node);
-
-/** Removes all items from given queue and frees the allocated storage. */
-void coap_delete_all(coap_queue_t *queue);
-
-/** Creates a new node suitable for adding to the CoAP sendqueue. */
-coap_queue_t *coap_new_node(void);
-
-struct coap_resource_t;
-struct coap_context_t;
-#ifndef WITHOUT_ASYNC
-struct coap_async_state_t;
-#endif
-
-/** Message handler that is used as call-back in coap_context_t */
-typedef void (*coap_response_handler_t)(struct coap_context_t  *,
-                                        const coap_endpoint_t *local_interface,
-                                        const coap_address_t *remote,
-                                        coap_pdu_t *sent,
-                                        coap_pdu_t *received,
-                                        const coap_tid_t id);
-
-#define COAP_MID_CACHE_SIZE 3
-typedef struct {
-  unsigned char flags[COAP_MID_CACHE_SIZE];
-  coap_key_t item[COAP_MID_CACHE_SIZE];
-} coap_mid_cache_t;
-
-/** The CoAP stack's global state is stored in a coap_context_t object */
-typedef struct coap_context_t {
-  coap_opt_filter_t known_options;
-  struct coap_resource_t *resources; /**< hash table or list of known resources */
-
-#ifndef WITHOUT_ASYNC
-  /**
-   * list of asynchronous transactions */
-  struct coap_async_state_t *async_state;
-#endif /* WITHOUT_ASYNC */
-
-  /**
-   * The time stamp in the first element of the sendqeue is relative
-   * to sendqueue_basetime. */
-  coap_tick_t sendqueue_basetime;
-  coap_queue_t *sendqueue;
-  coap_endpoint_t *endpoint;      /**< the endpoint used for listening  */
-
-#ifdef WITH_POSIX
-  int sockfd;                     /**< send/receive socket */
-#endif /* WITH_POSIX */
-
-#ifdef WITH_CONTIKI
-  struct uip_udp_conn *conn;      /**< uIP connection object */
-  struct etimer retransmit_timer; /**< fires when the next packet must be sent */
-  struct etimer notify_timer;     /**< used to check resources periodically */
-#endif /* WITH_CONTIKI */
-
-#ifdef WITH_LWIP
-  uint8_t timer_configured;       /**< Set to 1 when a retransmission is
-                                   *   scheduled using lwIP timers for this
-                                   *   context, otherwise 0. */
-#endif /* WITH_LWIP */
-
-  /**
-   * The last message id that was used is stored in this field. The initial
-   * value is set by coap_new_context() and is usually a random value. A new
-   * message id can be created with coap_new_message_id().
-   */
-  unsigned short message_id;
-
-  /**
-   * The next value to be used for Observe. This field is global for all
-   * resources and will be updated when notifications are created.
-   */
-  unsigned int observe;
-
-  coap_response_handler_t response_handler;
-
-  ssize_t (*network_send)(struct coap_context_t *context,
-                          const coap_endpoint_t *local_interface,
-                          const coap_address_t *dst,
-                          unsigned char *data, size_t datalen);
-
-  ssize_t (*network_read)(coap_endpoint_t *ep, coap_packet_t **packet);
-
-} coap_context_t;
-
-/**
- * Registers a new message handler that is called whenever a response was
- * received that matches an ongoing transaction.
- *
- * @param context The context to register the handler for.
- * @param handler The response handler to register.
- */
-static inline void
-coap_register_response_handler(coap_context_t *context,
-                               coap_response_handler_t handler) {
-  context->response_handler = handler;
-}
-
-/**
- * Registers the option type @p type with the given context object @p ctx.
- *
- * @param ctx  The context to use.
- * @param type The option type to register.
- */
-inline static void
-coap_register_option(coap_context_t *ctx, unsigned char type) {
-  coap_option_setb(ctx->known_options, type);
-}
-
-/**
- * Set sendqueue_basetime in the given context object @p ctx to @p now. This
- * function returns the number of elements in the queue head that have timed
- * out.
- */
-unsigned int coap_adjust_basetime(coap_context_t *ctx, coap_tick_t now);
-
-/**
- * Returns the next pdu to send without removing from sendqeue.
- */
-coap_queue_t *coap_peek_next( coap_context_t *context );
-
-/**
- * Returns the next pdu to send and removes it from the sendqeue.
- */
-coap_queue_t *coap_pop_next( coap_context_t *context );
-
-/**
- * Creates a new coap_context_t object that will hold the CoAP stack status.
- */
-coap_context_t *coap_new_context(const coap_address_t *listen_addr);
-
-/**
- * Returns a new message id and updates @p context->message_id accordingly. The
- * message id is returned in network byte order to make it easier to read in
- * tracing tools.
- *
- * @param context The current coap_context_t object.
- *
- * @return        Incremented message id in network byte order.
- */
-static inline unsigned short
-coap_new_message_id(coap_context_t *context) {
-  context->message_id++;
-#ifndef WITH_CONTIKI
-  return htons(context->message_id);
-#else /* WITH_CONTIKI */
-  return uip_htons(context->message_id);
-#endif
-}
-
-/**
- * CoAP stack context must be released with coap_free_context(). This function
- * clears all entries from the receive queue and send queue and deletes the
- * resources that have been registered with @p context, and frees the attached
- * endpoints.
- */
-void coap_free_context(coap_context_t *context);
-
-
-/**
- * Sends a confirmed CoAP message to given destination. The memory that is
- * allocated by pdu will not be released by coap_send_confirmed(). The caller
- * must release the memory.
- *
- * @param context         The CoAP context to use.
- * @param local_interface The local network interface where the outbound
- *                        packet is sent.
- * @param dst             The address to send to.
- * @param pdu             The CoAP PDU to send.
- *
- * @return                The message id of the sent message or @c
- *                        COAP_INVALID_TID on error.
- */
-coap_tid_t coap_send_confirmed(coap_context_t *context,
-                               const coap_endpoint_t *local_interface,
-                               const coap_address_t *dst,
-                               coap_pdu_t *pdu);
-
-/**
- * Creates a new ACK PDU with specified error @p code. The options specified by
- * the filter expression @p opts will be copied from the original request
- * contained in @p request. Unless @c SHORT_ERROR_RESPONSE was defined at build
- * time, the textual reason phrase for @p code will be added as payload, with
- * Content-Type @c 0.
- * This function returns a pointer to the new response message, or @c NULL on
- * error. The storage allocated for the new message must be relased with
- * coap_free().
- *
- * @param request Specification of the received (confirmable) request.
- * @param code    The error code to set.
- * @param opts    An option filter that specifies which options to copy from
- *                the original request in @p node.
- *
- * @return        A pointer to the new message or @c NULL on error.
- */
-coap_pdu_t *coap_new_error_response(coap_pdu_t *request,
-                                    unsigned char code,
-                                    coap_opt_filter_t opts);
-
-/**
- * Sends a non-confirmed CoAP message to given destination. The memory that is
- * allocated by pdu will not be released by coap_send().
- * The caller must release the memory.
- *
- * @param context         The CoAP context to use.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             The address to send to.
- * @param pdu             The CoAP PDU to send.
- *
- * @return                The message id of the sent message or @c
- *                        COAP_INVALID_TID on error.
- */
-coap_tid_t coap_send(coap_context_t *context,
-                     const coap_endpoint_t *local_interface,
-                     const coap_address_t *dst,
-                     coap_pdu_t *pdu);
-
-/**
- * Sends an error response with code @p code for request @p request to @p dst.
- * @p opts will be passed to coap_new_error_response() to copy marked options
- * from the request. This function returns the transaction id if the message was
- * sent, or @c COAP_INVALID_TID otherwise.
- *
- * @param context         The context to use.
- * @param request         The original request to respond to.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             The remote peer that sent the request.
- * @param code            The response code.
- * @param opts            A filter that specifies the options to copy from the
- *                        @p request.
- *
- * @return                The transaction id if the message was sent, or @c
- *                        COAP_INVALID_TID otherwise.
- */
-coap_tid_t coap_send_error(coap_context_t *context,
-                           coap_pdu_t *request,
-                           const coap_endpoint_t *local_interface,
-                           const coap_address_t *dst,
-                           unsigned char code,
-                           coap_opt_filter_t opts);
-
-/**
- * Helper funktion to create and send a message with @p type (usually ACK or
- * RST). This function returns @c COAP_INVALID_TID when the message was not
- * sent, a valid transaction id otherwise.
- *
- * @param  context        The CoAP context.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             Where to send the context.
- * @param request         The request that should be responded to.
- * @param type            Which type to set.
- * @return                transaction id on success or @c COAP_INVALID_TID
- *                        otherwise.
- */
-coap_tid_t
-coap_send_message_type(coap_context_t *context,
-                       const coap_endpoint_t *local_interface,
-                       const coap_address_t *dst,
-                       coap_pdu_t *request,
-                       unsigned char type);
-
-/**
- * Sends an ACK message with code @c 0 for the specified @p request to @p dst.
- * This function returns the corresponding transaction id if the message was
- * sent or @c COAP_INVALID_TID on error.
- *
- * @param context         The context to use.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             The destination address.
- * @param request         The request to be acknowledged.
- *
- * @return                The transaction id if ACK was sent or @c
- *                        COAP_INVALID_TID on error.
- */
-coap_tid_t coap_send_ack(coap_context_t *context,
-                         const coap_endpoint_t *local_interface,
-                         const coap_address_t *dst,
-                         coap_pdu_t *request);
-
-/**
- * Sends an RST message with code @c 0 for the specified @p request to @p dst.
- * This function returns the corresponding transaction id if the message was
- * sent or @c COAP_INVALID_TID on error.
- *
- * @param context         The context to use.
- * @param local_interface The local network interface where the outbound packet
- *                        is sent.
- * @param dst             The destination address.
- * @param request         The request to be reset.
- *
- * @return                The transaction id if RST was sent or @c
- *                        COAP_INVALID_TID on error.
- */
-static inline coap_tid_t
-coap_send_rst(coap_context_t *context,
-              const coap_endpoint_t *local_interface,
-              const coap_address_t *dst,
-              coap_pdu_t *request) {
-  return coap_send_message_type(context,
-                                local_interface,
-                                dst, request,
-                                COAP_MESSAGE_RST);
-}
-
-/**
- * Handles retransmissions of confirmable messages
- */
-coap_tid_t coap_retransmit(coap_context_t *context, coap_queue_t *node);
-
-/**
- * Reads data from the network and tries to parse as CoAP PDU. On success, 0 is
- * returned and a new node with the parsed PDU is added to the receive queue in
- * the specified context object.
- */
-int coap_read(coap_context_t *context);
-
-/**
- * Parses and interprets a CoAP message with context @p ctx. This function
- * returns @c 0 if the message was handled, or a value less than zero on
- * error.
- *
- * @param ctx    The current CoAP context.
- * @param packet The received packet.
- *
- * @return       @c 0 if message was handled successfully, or less than zero on
- *               error.
- */
-int coap_handle_message(coap_context_t *ctx,
-                        coap_packet_t *packet);
-
-/**
- * Calculates a unique transaction id from given arguments @p peer and @p pdu.
- * The id is returned in @p id.
- *
- * @param peer The remote party who sent @p pdu.
- * @param pdu  The message that initiated the transaction.
- * @param id   Set to the new id.
- */
-void coap_transaction_id(const coap_address_t *peer,
-                         const coap_pdu_t *pdu,
-                         coap_tid_t *id);
-
-/**
- * This function removes the element with given @p id from the list given list.
- * If @p id was found, @p node is updated to point to the removed element. Note
- * that the storage allocated by @p node is @b not released. The caller must do
- * this manually using coap_delete_node(). This function returns @c 1 if the
- * element with id @p id was found, @c 0 otherwise. For a return value of @c 0,
- * the contents of @p node is undefined.
- *
- * @param queue The queue to search for @p id.
- * @param id    The node id to look for.
- * @param node  If found, @p node is updated to point to the removed node. You
- *              must release the storage pointed to by @p node manually.
- *
- * @return      @c 1 if @p id was found, @c 0 otherwise.
- */
-int coap_remove_from_queue(coap_queue_t **queue,
-                           coap_tid_t id,
-                           coap_queue_t **node);
-
-/**
- * Removes the transaction identified by @p id from given @p queue. This is a
- * convenience function for coap_remove_from_queue() with automatic deletion of
- * the removed node.
- *
- * @param queue The queue to search for @p id.
- * @param id    The transaction id.
- *
- * @return      @c 1 if node was found, removed and destroyed, @c 0 otherwise.
- */
-inline static int
-coap_remove_transaction(coap_queue_t **queue, coap_tid_t id) {
-  coap_queue_t *node;
-  if (!coap_remove_from_queue(queue, id, &node))
-    return 0;
-
-  coap_delete_node(node);
-  return 1;
-}
-
-/**
- * Retrieves transaction from the queue.
- *
- * @param queue The transaction queue to be searched.
- * @param id    Unique key of the transaction to find.
- *
- * @return      A pointer to the transaction object or NULL if not found.
- */
-coap_queue_t *coap_find_transaction(coap_queue_t *queue, coap_tid_t id);
-
-/**
- * Cancels all outstanding messages for peer @p dst that have the specified
- * token.
- *
- * @param context      The context in use.
- * @param dst          Destination address of the messages to remove.
- * @param token        Message token.
- * @param token_length Actual length of @p token.
- */
-void coap_cancel_all_messages(coap_context_t *context,
-                              const coap_address_t *dst,
-                              const unsigned char *token,
-                              size_t token_length);
-
-/**
- * Dispatches the PDUs from the receive queue in given context.
- */
-void coap_dispatch(coap_context_t *context, coap_queue_t *rcvd);
-
-/**
- * Returns 1 if there are no messages to send or to dispatch in the context's
- * queues. */
-int coap_can_exit(coap_context_t *context);
-
-/**
- * Returns the current value of an internal tick counter. The counter counts \c
- * COAP_TICKS_PER_SECOND ticks every second.
- */
-void coap_ticks(coap_tick_t *);
-
-/**
- * Verifies that @p pdu contains no unknown critical options. Options must be
- * registered at @p ctx, using the function coap_register_option(). A basic set
- * of options is registered automatically by coap_new_context(). This function
- * returns @c 1 if @p pdu is ok, @c 0 otherwise. The given filter object @p
- * unknown will be updated with the unknown options. As only @c COAP_MAX_OPT
- * options can be signalled this way, remaining options must be examined
- * manually.
- *
- * @code
-  coap_opt_filter_t f = COAP_OPT_NONE;
-  coap_opt_iterator_t opt_iter;
-
-  if (coap_option_check_critical(ctx, pdu, f) == 0) {
-    coap_option_iterator_init(pdu, &opt_iter, f);
-
-    while (coap_option_next(&opt_iter)) {
-      if (opt_iter.type & 0x01) {
-        ... handle unknown critical option in opt_iter ...
-      }
-    }
-  }
- * @endcode
- *
- * @param ctx      The context where all known options are registered.
- * @param pdu      The PDU to check.
- * @param unknown  The output filter that will be updated to indicate the
- *                 unknown critical options found in @p pdu.
- *
- * @return         @c 1 if everything was ok, @c 0 otherwise.
- */
-int coap_option_check_critical(coap_context_t *ctx,
-                               coap_pdu_t *pdu,
-                               coap_opt_filter_t unknown);
-
-/**
- * Creates a new response for given @p request with the contents of @c
- * .well-known/core. The result is NULL on error or a newly allocated PDU that
- * must be released by coap_delete_pdu().
- *
- * @param context The current coap context to use.
- * @param request The request for @c .well-known/core .
- *
- * @return        A new 2.05 response for @c .well-known/core or NULL on error.
- */
-coap_pdu_t *coap_wellknown_response(coap_context_t *context,
-                                    coap_pdu_t *request);
-
-#endif /* _COAP_NET_H_ */
diff --git a/tools/sdk/include/coap/option.h b/tools/sdk/include/coap/option.h
deleted file mode 100644
index ace2b81c713..00000000000
--- a/tools/sdk/include/coap/option.h
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * option.h -- helpers for handling options in CoAP PDUs
- *
- * Copyright (C) 2010-2013 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file option.h
- * @brief Helpers for handling options in CoAP PDUs
- */
-
-#ifndef _COAP_OPTION_H_
-#define _COAP_OPTION_H_
-
-#include "bits.h"
-#include "pdu.h"
-
-/**
- * Use byte-oriented access methods here because sliding a complex struct
- * coap_opt_t over the data buffer may cause bus error on certain platforms.
- */
-typedef unsigned char coap_opt_t;
-#define PCHAR(p) ((coap_opt_t *)(p))
-
-/** Representation of CoAP options. */
-typedef struct {
-  unsigned short delta;
-  size_t length;
-  unsigned char *value;
-} coap_option_t;
-
-/**
- * Parses the option pointed to by @p opt into @p result. This function returns
- * the number of bytes that have been parsed, or @c 0 on error. An error is
- * signaled when illegal delta or length values are encountered or when option
- * parsing would result in reading past the option (i.e. beyond opt + length).
- *
- * @param opt    The beginning of the option to parse.
- * @param length The maximum length of @p opt.
- * @param result A pointer to the coap_option_t structure that is filled with
- *               actual values iff coap_opt_parse() > 0.
- * @return       The number of bytes parsed or @c 0 on error.
- */
-size_t coap_opt_parse(const coap_opt_t *opt,
-                      size_t length,
-                      coap_option_t *result);
-
-/**
- * Returns the size of the given option, taking into account a possible option
- * jump.
- *
- * @param opt An option jump or the beginning of the option.
- * @return    The number of bytes between @p opt and the end of the option
- *            starting at @p opt. In case of an error, this function returns
- *            @c 0 as options need at least one byte storage space.
- */
-size_t coap_opt_size(const coap_opt_t *opt);
-
-/** @deprecated { Use coap_opt_size() instead. } */
-#define COAP_OPT_SIZE(opt) coap_opt_size(opt)
-
-/**
- * Calculates the beginning of the PDU's option section.
- *
- * @param pdu The PDU containing the options.
- * @return    A pointer to the first option if available, or @c NULL otherwise.
- */
-coap_opt_t *options_start(coap_pdu_t *pdu);
-
-/**
- * Interprets @p opt as pointer to a CoAP option and advances to
- * the next byte past this option.
- * @hideinitializer
- */
-#define options_next(opt) \
-  ((coap_opt_t *)((unsigned char *)(opt) + COAP_OPT_SIZE(opt)))
-
-/**
- * @defgroup opt_filter Option Filters
- * @{
- */
-
-/**
- * The number of option types below 256 that can be stored in an
- * option filter. COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG must be
- * at most 16. Each coap_option_filter_t object reserves
- * ((COAP_OPT_FILTER_SHORT + 1) / 2) * 2 bytes for short options.
- */
-#define COAP_OPT_FILTER_SHORT 6
-
-/**
- * The number of option types above 255 that can be stored in an
- * option filter. COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG must be
- * at most 16. Each coap_option_filter_t object reserves
- * COAP_OPT_FILTER_LONG * 2 bytes for short options.
- */
-#define COAP_OPT_FILTER_LONG  2
-
-/* Ensure that COAP_OPT_FILTER_SHORT and COAP_OPT_FILTER_LONG are set
- * correctly. */
-#if (COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG > 16)
-#error COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG must be less or equal 16
-#endif /* (COAP_OPT_FILTER_SHORT + COAP_OPT_FILTER_LONG > 16) */
-
-/** The number of elements in coap_opt_filter_t. */
-#define COAP_OPT_FILTER_SIZE					\
-  (((COAP_OPT_FILTER_SHORT + 1) >> 1) + COAP_OPT_FILTER_LONG) +1
-
-/**
- * Fixed-size vector we use for option filtering. It is large enough
- * to hold COAP_OPT_FILTER_SHORT entries with an option number between
- * 0 and 255, and COAP_OPT_FILTER_LONG entries with an option number
- * between 256 and 65535. Its internal structure is
- *
- * @code
-struct {
-  uint16_t mask;
-  uint16_t long_opts[COAP_OPT_FILTER_LONG];
-  uint8_t short_opts[COAP_OPT_FILTER_SHORT];
-}
- * @endcode
- *
- * The first element contains a bit vector that indicates which fields
- * in the remaining array are used. The first COAP_OPT_FILTER_LONG
- * bits correspond to the long option types that are stored in the
- * elements from index 1 to COAP_OPT_FILTER_LONG. The next
- * COAP_OPT_FILTER_SHORT bits correspond to the short option types
- * that are stored in the elements from index COAP_OPT_FILTER_LONG + 1
- * to COAP_OPT_FILTER_LONG + COAP_OPT_FILTER_SHORT. The latter
- * elements are treated as bytes.
- */
-typedef uint16_t coap_opt_filter_t[COAP_OPT_FILTER_SIZE];
-
-/** Pre-defined filter that includes all options. */
-#define COAP_OPT_ALL NULL
-
-/**
- * Clears filter @p f.
- *
- * @param f The filter to clear.
- */
-static inline void
-coap_option_filter_clear(coap_opt_filter_t f) {
-  memset(f, 0, sizeof(coap_opt_filter_t));
-}
-
-/**
- * Sets the corresponding entry for @p type in @p filter. This
- * function returns @c 1 if bit was set or @c 0 on error (i.e. when
- * the given type does not fit in the filter).
- *
- * @param filter The filter object to change.
- * @param type   The type for which the bit should be set.
- *
- * @return       @c 1 if bit was set, @c 0 otherwise.
- */
-int coap_option_filter_set(coap_opt_filter_t filter, unsigned short type);
-
-/**
- * Clears the corresponding entry for @p type in @p filter. This
- * function returns @c 1 if bit was set or @c 0 on error (i.e. when
- * the given type does not fit in the filter).
- *
- * @param filter The filter object to change.
- * @param type   The type that should be cleared from the filter.
- *
- * @return       @c 1 if bit was set, @c 0 otherwise.
- */
-int coap_option_filter_unset(coap_opt_filter_t filter, unsigned short type);
-
-/**
- * Checks if @p type is contained in @p filter. This function returns
- * @c 1 if found, @c 0 if not, or @c -1 on error (i.e. when the given
- * type does not fit in the filter).
- *
- * @param filter The filter object to search.
- * @param type   The type to search for.
- *
- * @return       @c 1 if @p type was found, @c 0 otherwise, or @c -1 on error.
- */
-int coap_option_filter_get(const coap_opt_filter_t filter, unsigned short type);
-
-/**
- * Sets the corresponding bit for @p type in @p filter. This function returns @c
- * 1 if bit was set or @c -1 on error (i.e. when the given type does not fit in
- * the filter).
- *
- * @deprecated Use coap_option_filter_set() instead.
- *
- * @param filter The filter object to change.
- * @param type   The type for which the bit should be set.
- *
- * @return       @c 1 if bit was set, @c -1 otherwise.
- */
-inline static int
-coap_option_setb(coap_opt_filter_t filter, unsigned short type) {
-  return coap_option_filter_set(filter, type) ? 1 : -1;
-}
-
-/**
- * Clears the corresponding bit for @p type in @p filter. This function returns
- * @c 1 if bit was cleared or @c -1 on error (i.e. when the given type does not
- * fit in the filter).
- *
- * @deprecated Use coap_option_filter_unset() instead.
- *
- * @param filter The filter object to change.
- * @param type   The type for which the bit should be cleared.
- *
- * @return       @c 1 if bit was set, @c -1 otherwise.
- */
-inline static int
-coap_option_clrb(coap_opt_filter_t filter, unsigned short type) {
-  return coap_option_filter_unset(filter, type) ? 1 : -1;
-}
-
-/**
- * Gets the corresponding bit for @p type in @p filter. This function returns @c
- * 1 if the bit is set @c 0 if not, or @c -1 on error (i.e. when the given type
- * does not fit in the filter).
- *
- * @deprecated Use coap_option_filter_get() instead.
- *
- * @param filter The filter object to read bit from.
- * @param type   The type for which the bit should be read.
- *
- * @return       @c 1 if bit was set, @c 0 if not, @c -1 on error.
- */
-inline static int
-coap_option_getb(const coap_opt_filter_t filter, unsigned short type) {
-  return coap_option_filter_get(filter, type);
-}
-
-/**
- * Iterator to run through PDU options. This object must be
- * initialized with coap_option_iterator_init(). Call
- * coap_option_next() to walk through the list of options until
- * coap_option_next() returns @c NULL.
- *
- * @code
- * coap_opt_t *option;
- * coap_opt_iterator_t opt_iter;
- * coap_option_iterator_init(pdu, &opt_iter, COAP_OPT_ALL);
- *
- * while ((option = coap_option_next(&opt_iter))) {
- *   ... do something with option ...
- * }
- * @endcode
- */
-typedef struct {
-  size_t length;                /**< remaining length of PDU */
-  unsigned short type;          /**< decoded option type */
-  unsigned int bad:1;           /**< iterator object is ok if not set */
-  unsigned int filtered:1;      /**< denotes whether or not filter is used */
-  coap_opt_t *next_option;      /**< pointer to the unparsed next option */
-  coap_opt_filter_t filter;     /**< option filter */
-} coap_opt_iterator_t;
-
-/**
- * Initializes the given option iterator @p oi to point to the beginning of the
- * @p pdu's option list. This function returns @p oi on success, @c NULL
- * otherwise (i.e. when no options exist). Note that a length check on the
- * option list must be performed before coap_option_iterator_init() is called.
- *
- * @param pdu    The PDU the options of which should be walked through.
- * @param oi     An iterator object that will be initilized.
- * @param filter An optional option type filter.
- *               With @p type != @c COAP_OPT_ALL, coap_option_next()
- *               will return only options matching this bitmask.
- *               Fence-post options @c 14, @c 28, @c 42, ... are always
- *               skipped.
- *
- * @return       The iterator object @p oi on success, @c NULL otherwise.
- */
-coap_opt_iterator_t *coap_option_iterator_init(coap_pdu_t *pdu,
-                                               coap_opt_iterator_t *oi,
-                                               const coap_opt_filter_t filter);
-
-/**
- * Updates the iterator @p oi to point to the next option. This function returns
- * a pointer to that option or @c NULL if no more options exist. The contents of
- * @p oi will be updated. In particular, @c oi->n specifies the current option's
- * ordinal number (counted from @c 1), @c oi->type is the option's type code,
- * and @c oi->option points to the beginning of the current option itself. When
- * advanced past the last option, @c oi->option will be @c NULL.
- *
- * Note that options are skipped whose corresponding bits in the filter
- * specified with coap_option_iterator_init() are @c 0. Options with type codes
- * that do not fit in this filter hence will always be returned.
- *
- * @param oi The option iterator to update.
- *
- * @return   The next option or @c NULL if no more options exist.
- */
-coap_opt_t *coap_option_next(coap_opt_iterator_t *oi);
-
-/**
- * Retrieves the first option of type @p type from @p pdu. @p oi must point to a
- * coap_opt_iterator_t object that will be initialized by this function to
- * filter only options with code @p type. This function returns the first option
- * with this type, or @c NULL if not found.
- *
- * @param pdu  The PDU to parse for options.
- * @param type The option type code to search for.
- * @param oi   An iterator object to use.
- *
- * @return     A pointer to the first option of type @p type, or @c NULL if
- *             not found.
- */
-coap_opt_t *coap_check_option(coap_pdu_t *pdu,
-                              unsigned short type,
-                              coap_opt_iterator_t *oi);
-
-/**
- * Encodes the given delta and length values into @p opt. This function returns
- * the number of bytes that were required to encode @p delta and @p length or @c
- * 0 on error. Note that the result indicates by how many bytes @p opt must be
- * advanced to encode the option value.
- *
- * @param opt    The option buffer space where @p delta and @p length are
- *               written.
- * @param maxlen The maximum length of @p opt.
- * @param delta  The actual delta value to encode.
- * @param length The actual length value to encode.
- *
- * @return       The number of bytes used or @c 0 on error.
- */
-size_t coap_opt_setheader(coap_opt_t *opt,
-                          size_t maxlen,
-                          unsigned short delta,
-                          size_t length);
-
-/**
- * Encodes option with given @p delta into @p opt. This function returns the
- * number of bytes written to @p opt or @c 0 on error. This happens especially
- * when @p opt does not provide sufficient space to store the option value,
- * delta, and option jumps when required.
- *
- * @param opt    The option buffer space where @p val is written.
- * @param n      Maximum length of @p opt.
- * @param delta  The option delta.
- * @param val    The option value to copy into @p opt.
- * @param length The actual length of @p val.
- *
- * @return       The number of bytes that have been written to @p opt or @c 0 on
- *               error. The return value will always be less than @p n.
- */
-size_t coap_opt_encode(coap_opt_t *opt,
-                       size_t n,
-                       unsigned short delta,
-                       const unsigned char *val,
-                       size_t length);
-
-/**
- * Decodes the delta value of the next option. This function returns the number
- * of bytes read or @c 0 on error. The caller of this function must ensure that
- * it does not read over the boundaries of @p opt (e.g. by calling
- * coap_opt_check_delta().
- *
- * @param opt The option to examine.
- *
- * @return    The number of bytes read or @c 0 on error.
- */
-unsigned short coap_opt_delta(const coap_opt_t *opt);
-
-/** @deprecated { Use coap_opt_delta() instead. } */
-#define COAP_OPT_DELTA(opt) coap_opt_delta(opt)
-
-/** @deprecated { Use coap_opt_encode() instead. } */
-#define COAP_OPT_SETDELTA(opt,val) \
-  coap_opt_encode((opt), COAP_MAX_PDU_SIZE, (val), NULL, 0)
-
-/**
- * Returns the length of the given option. @p opt must point to an option jump
- * or the beginning of the option. This function returns @c 0 when @p opt is not
- * an option or the actual length of @p opt (which can be @c 0 as well).
- *
- * @note {The rationale for using @c 0 in case of an error is that in most
- * contexts, the result of this function is used to skip the next
- * coap_opt_length() bytes.}
- *
- * @param opt  The option whose length should be returned.
- *
- * @return     The option's length or @c 0 when undefined.
- */
-unsigned short coap_opt_length(const coap_opt_t *opt);
-
-/** @deprecated { Use coap_opt_length() instead. } */
-#define COAP_OPT_LENGTH(opt) coap_opt_length(opt)
-
-/**
- * Returns a pointer to the value of the given option. @p opt must point to an
- * option jump or the beginning of the option. This function returns @c NULL if
- * @p opt is not a valid option.
- *
- * @param opt The option whose value should be returned.
- *
- * @return    A pointer to the option value or @c NULL on error.
- */
-unsigned char *coap_opt_value(coap_opt_t *opt);
-
-/** @deprecated { Use coap_opt_value() instead. } */
-#define COAP_OPT_VALUE(opt) coap_opt_value((coap_opt_t *)opt)
-
-/** @} */
-
-#endif /* _OPTION_H_ */
diff --git a/tools/sdk/include/coap/pdu.h b/tools/sdk/include/coap/pdu.h
deleted file mode 100644
index 7ed482deee0..00000000000
--- a/tools/sdk/include/coap/pdu.h
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * pdu.h -- CoAP message structure
- *
- * Copyright (C) 2010-2014 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file pdu.h
- * @brief Pre-defined constants that reflect defaults for CoAP
- */
-
-#ifndef _COAP_PDU_H_
-#define _COAP_PDU_H_
-
-#include "uri.h"
-
-#ifdef WITH_LWIP
-#include <lwip/pbuf.h>
-#endif
-
-#define COAP_DEFAULT_PORT      5683 /* CoAP default UDP port */
-#define COAP_DEFAULT_MAX_AGE     60 /* default maximum object lifetime in seconds */
-#ifndef COAP_MAX_PDU_SIZE
-#define COAP_MAX_PDU_SIZE      1400 /* maximum size of a CoAP PDU */
-#endif /* COAP_MAX_PDU_SIZE */
-
-#define COAP_DEFAULT_VERSION      1 /* version of CoAP supported */
-#define COAP_DEFAULT_SCHEME  "coap" /* the default scheme for CoAP URIs */
-
-/** well-known resources URI */
-#define COAP_DEFAULT_URI_WELLKNOWN ".well-known/core"
-
-#ifdef __COAP_DEFAULT_HASH
-/* pre-calculated hash key for the default well-known URI */
-#define COAP_DEFAULT_WKC_HASHKEY   "\345\130\144\245"
-#endif
-
-/* CoAP message types */
-
-#define COAP_MESSAGE_CON       0 /* confirmable message (requires ACK/RST) */
-#define COAP_MESSAGE_NON       1 /* non-confirmable message (one-shot message) */
-#define COAP_MESSAGE_ACK       2 /* used to acknowledge confirmable messages */
-#define COAP_MESSAGE_RST       3 /* indicates error in received messages */
-
-/* CoAP request methods */
-
-#define COAP_REQUEST_GET       1
-#define COAP_REQUEST_POST      2
-#define COAP_REQUEST_PUT       3
-#define COAP_REQUEST_DELETE    4
-
-/* CoAP option types (be sure to update check_critical when adding options */
-
-#define COAP_OPTION_IF_MATCH        1 /* C, opaque, 0-8 B, (none) */
-#define COAP_OPTION_URI_HOST        3 /* C, String, 1-255 B, destination address */
-#define COAP_OPTION_ETAG            4 /* E, opaque, 1-8 B, (none) */
-#define COAP_OPTION_IF_NONE_MATCH   5 /* empty, 0 B, (none) */
-#define COAP_OPTION_URI_PORT        7 /* C, uint, 0-2 B, destination port */
-#define COAP_OPTION_LOCATION_PATH   8 /* E, String, 0-255 B, - */
-#define COAP_OPTION_URI_PATH       11 /* C, String, 0-255 B, (none) */
-#define COAP_OPTION_CONTENT_FORMAT 12 /* E, uint, 0-2 B, (none) */
-#define COAP_OPTION_CONTENT_TYPE COAP_OPTION_CONTENT_FORMAT
-#define COAP_OPTION_MAXAGE         14 /* E, uint, 0--4 B, 60 Seconds */
-#define COAP_OPTION_URI_QUERY      15 /* C, String, 1-255 B, (none) */
-#define COAP_OPTION_ACCEPT         17 /* C, uint,   0-2 B, (none) */
-#define COAP_OPTION_LOCATION_QUERY 20 /* E, String,   0-255 B, (none) */
-#define COAP_OPTION_PROXY_URI      35 /* C, String, 1-1034 B, (none) */
-#define COAP_OPTION_PROXY_SCHEME   39 /* C, String, 1-255 B, (none) */
-#define COAP_OPTION_SIZE1          60 /* E, uint, 0-4 B, (none) */
-
-/* option types from RFC 7641 */
-
-#define COAP_OPTION_OBSERVE         6 /* E, empty/uint, 0 B/0-3 B, (none) */
-#define COAP_OPTION_SUBSCRIPTION  COAP_OPTION_OBSERVE
-
-/* selected option types from RFC 7959 */
-
-#define COAP_OPTION_BLOCK2         23 /* C, uint, 0--3 B, (none) */
-#define COAP_OPTION_BLOCK1         27 /* C, uint, 0--3 B, (none) */
-
-/* selected option types from RFC 7967 */
-
-#define COAP_OPTION_NORESPONSE    258 /* N, uint, 0--1 B, 0 */
-
-#define COAP_MAX_OPT            65535 /**< the highest option number we know */
-
-/* CoAP result codes (HTTP-Code / 100 * 40 + HTTP-Code % 100) */
-
-/* As of draft-ietf-core-coap-04, response codes are encoded to base
- * 32, i.e.  the three upper bits determine the response class while
- * the remaining five fine-grained information specific to that class.
- */
-#define COAP_RESPONSE_CODE(N) (((N)/100 << 5) | (N)%100)
-
-/* Determines the class of response code C */
-#define COAP_RESPONSE_CLASS(C) (((C) >> 5) & 0xFF)
-
-#ifndef SHORT_ERROR_RESPONSE
-/**
- * Returns a human-readable response phrase for the specified CoAP response @p
- * code. This function returns @c NULL if not found.
- *
- * @param code The response code for which the literal phrase should be
- *             retrieved.
- *
- * @return     A zero-terminated string describing the error, or @c NULL if not
- *             found.
- */
-char *coap_response_phrase(unsigned char code);
-
-#define COAP_ERROR_PHRASE_LENGTH   32 /**< maximum length of error phrase */
-
-#else
-#define coap_response_phrase(x) ((char *)NULL)
-
-#define COAP_ERROR_PHRASE_LENGTH    0 /**< maximum length of error phrase */
-#endif /* SHORT_ERROR_RESPONSE */
-
-/* The following definitions exist for backwards compatibility */
-#if 0 /* this does not exist any more */
-#define COAP_RESPONSE_100      40 /* 100 Continue */
-#endif
-#define COAP_RESPONSE_200      COAP_RESPONSE_CODE(200)  /* 2.00 OK */
-#define COAP_RESPONSE_201      COAP_RESPONSE_CODE(201)  /* 2.01 Created */
-#define COAP_RESPONSE_304      COAP_RESPONSE_CODE(203)  /* 2.03 Valid */
-#define COAP_RESPONSE_400      COAP_RESPONSE_CODE(400)  /* 4.00 Bad Request */
-#define COAP_RESPONSE_404      COAP_RESPONSE_CODE(404)  /* 4.04 Not Found */
-#define COAP_RESPONSE_405      COAP_RESPONSE_CODE(405)  /* 4.05 Method Not Allowed */
-#define COAP_RESPONSE_415      COAP_RESPONSE_CODE(415)  /* 4.15 Unsupported Media Type */
-#define COAP_RESPONSE_500      COAP_RESPONSE_CODE(500)  /* 5.00 Internal Server Error */
-#define COAP_RESPONSE_501      COAP_RESPONSE_CODE(501)  /* 5.01 Not Implemented */
-#define COAP_RESPONSE_503      COAP_RESPONSE_CODE(503)  /* 5.03 Service Unavailable */
-#define COAP_RESPONSE_504      COAP_RESPONSE_CODE(504)  /* 5.04 Gateway Timeout */
-#if 0  /* these response codes do not have a valid code any more */
-#  define COAP_RESPONSE_X_240    240   /* Token Option required by server */
-#  define COAP_RESPONSE_X_241    241   /* Uri-Authority Option required by server */
-#endif
-#define COAP_RESPONSE_X_242    COAP_RESPONSE_CODE(402)  /* Critical Option not supported */
-
-/* CoAP media type encoding */
-
-#define COAP_MEDIATYPE_TEXT_PLAIN                 0 /* text/plain (UTF-8) */
-#define COAP_MEDIATYPE_APPLICATION_LINK_FORMAT   40 /* application/link-format */
-#define COAP_MEDIATYPE_APPLICATION_XML           41 /* application/xml */
-#define COAP_MEDIATYPE_APPLICATION_OCTET_STREAM  42 /* application/octet-stream */
-#define COAP_MEDIATYPE_APPLICATION_RDF_XML       43 /* application/rdf+xml */
-#define COAP_MEDIATYPE_APPLICATION_EXI           47 /* application/exi  */
-#define COAP_MEDIATYPE_APPLICATION_JSON          50 /* application/json  */
-#define COAP_MEDIATYPE_APPLICATION_CBOR          60 /* application/cbor  */
-
-/* Note that identifiers for registered media types are in the range 0-65535. We
- * use an unallocated type here and hope for the best. */
-#define COAP_MEDIATYPE_ANY                         0xff /* any media type */
-
-/**
- * coap_tid_t is used to store CoAP transaction id, i.e. a hash value
- * built from the remote transport address and the message id of a
- * CoAP PDU.  Valid transaction ids are greater or equal zero.
- */
-typedef int coap_tid_t;
-
-/** Indicates an invalid transaction id. */
-#define COAP_INVALID_TID -1
-
-/**
- * Indicates that a response is suppressed. This will occur for error
- * responses if the request was received via IP multicast.
- */
-#define COAP_DROPPED_RESPONSE -2
-
-#ifdef WORDS_BIGENDIAN
-typedef struct {
-  unsigned int version:2;      /* protocol version */
-  unsigned int type:2;         /* type flag */
-  unsigned int token_length:4; /* length of Token */
-  unsigned int code:8;         /* request method (value 1--10) or response
-                                  code (value 40-255) */
-  unsigned short id;           /* message id */
-  unsigned char token[];       /* the actual token, if any */
-} coap_hdr_t;
-#else
-typedef struct {
-  unsigned int token_length:4; /* length of Token */
-  unsigned int type:2;         /* type flag */
-  unsigned int version:2;      /* protocol version */
-  unsigned int code:8;         /* request method (value 1--10) or response
-                                  code (value 40-255) */
-  unsigned short id;           /* transaction id (network byte order!) */
-  unsigned char token[];       /* the actual token, if any */
-} coap_hdr_t;
-#endif
-
-#define COAP_MESSAGE_IS_EMPTY(MSG)    ((MSG)->code == 0)
-#define COAP_MESSAGE_IS_REQUEST(MSG)  (!COAP_MESSAGE_IS_EMPTY(MSG) \
-                                       && ((MSG)->code < 32))
-#define COAP_MESSAGE_IS_RESPONSE(MSG) ((MSG)->code >= 64)
-
-#define COAP_OPT_LONG 0x0F      /* OC == 0b1111 indicates that the option list
-                                 * in a CoAP message is limited by 0b11110000
-                                 * marker */
-
-#define COAP_OPT_END 0xF0       /* end marker */
-
-#define COAP_PAYLOAD_START 0xFF /* payload marker */
-
-/**
- * Structures for more convenient handling of options. (To be used with ordered
- * coap_list_t.) The option's data will be added to the end of the coap_option
- * structure (see macro COAP_OPTION_DATA).
- */
-typedef struct {
-  unsigned short key;           /* the option key (no delta coding) */
-  unsigned int length;
-} coap_option;
-
-#define COAP_OPTION_KEY(option) (option).key
-#define COAP_OPTION_LENGTH(option) (option).length
-#define COAP_OPTION_DATA(option) ((unsigned char *)&(option) + sizeof(coap_option))
-
-/**
- * Header structure for CoAP PDUs
- */
-
-typedef struct {
-  size_t max_size;          /**< allocated storage for options and data */
-  coap_hdr_t *hdr;          /**< Address of the first byte of the CoAP message.
-                             *   This may or may not equal (coap_hdr_t*)(pdu+1)
-                             *   depending on the memory management
-                             *   implementation. */
-  unsigned short max_delta; /**< highest option number */
-  unsigned short length;    /**< PDU length (including header, options, data) */
-  unsigned char *data;      /**< payload */
-
-#ifdef WITH_LWIP
-  struct pbuf *pbuf;        /**< lwIP PBUF. The package data will always reside
-                             *    inside the pbuf's payload, but this pointer
-                             *    has to be kept because no exact offset can be
-                             *    given. This field must not be accessed from
-                             *    outside, because the pbuf's reference count
-                             *    is checked to be 1 when the pbuf is assigned
-                             *    to the pdu, and the pbuf stays exclusive to
-                             *    this pdu. */
-#endif
-} coap_pdu_t;
-
-/**
- * Options in coap_pdu_t are accessed with the macro COAP_OPTION.
- */
-#define COAP_OPTION(node) ((coap_option *)(node)->options)
-
-#ifdef WITH_LWIP
-/**
- * Creates a CoAP PDU from an lwIP @p pbuf, whose reference is passed on to this
- * function.
- *
- * The pbuf is checked for being contiguous, and for having only one reference.
- * The reference is stored in the PDU and will be freed when the PDU is freed.
- *
- * (For now, these are fatal errors; in future, a new pbuf might be allocated,
- * the data copied and the passed pbuf freed).
- *
- * This behaves like coap_pdu_init(0, 0, 0, pbuf->tot_len), and afterwards
- * copying the contents of the pbuf to the pdu.
- *
- * @return A pointer to the new PDU object or @c NULL on error.
- */
-coap_pdu_t * coap_pdu_from_pbuf(struct pbuf *pbuf);
-#endif
-
-/**
- * Creates a new CoAP PDU of given @p size (must be large enough to hold the
- * basic CoAP message header (coap_hdr_t). The function returns a pointer to the
- * node coap_pdu_t object on success, or @c NULL on error. The storage allocated
- * for the result must be released with coap_delete_pdu().
- *
- * @param type The type of the PDU (one of COAP_MESSAGE_CON, COAP_MESSAGE_NON,
- *             COAP_MESSAGE_ACK, COAP_MESSAGE_RST).
- * @param code The message code.
- * @param id   The message id to set or COAP_INVALID_TID if unknown.
- * @param size The number of bytes to allocate for the actual message.
- *
- * @return     A pointer to the new PDU object or @c NULL on error.
- */
-coap_pdu_t *
-coap_pdu_init(unsigned char type,
-              unsigned char code,
-              unsigned short id,
-              size_t size);
-
-/**
- * Clears any contents from @p pdu and resets @c version field, @c
- * length and @c data pointers. @c max_size is set to @p size, any
- * other field is set to @c 0. Note that @p pdu must be a valid
- * pointer to a coap_pdu_t object created e.g. by coap_pdu_init().
- */
-void coap_pdu_clear(coap_pdu_t *pdu, size_t size);
-
-/**
- * Creates a new CoAP PDU.
- * The object is created on the heap and must be released using
- * coap_delete_pdu();
- *
- * @deprecated This function allocates the maximum storage for each
- * PDU. Use coap_pdu_init() instead.
- */
-coap_pdu_t *coap_new_pdu(void);
-
-void coap_delete_pdu(coap_pdu_t *);
-
-/**
- * Parses @p data into the CoAP PDU structure given in @p result.
- * This function returns @c 0 on error or a number greater than zero on success.
- *
- * @param data   The raw data to parse as CoAP PDU.
- * @param length The actual size of @p data.
- * @param result The PDU structure to fill. Note that the structure must
- *               provide space for at least @p length bytes to hold the
- *               entire CoAP PDU.
- *
- * @return       A value greater than zero on success or @c 0 on error.
- */
-int coap_pdu_parse(unsigned char *data,
-                   size_t length,
-                   coap_pdu_t *result);
-
-/**
- * Adds token of length @p len to @p pdu.
- * Adding the token destroys any following contents of the pdu. Hence options
- * and data must be added after coap_add_token() has been called. In @p pdu,
- * length is set to @p len + @c 4, and max_delta is set to @c 0. This funtion
- * returns @c 0 on error or a value greater than zero on success.
- *
- * @param pdu  The PDU where the token is to be added.
- * @param len  The length of the new token.
- * @param data The token to add.
- *
- * @return     A value greater than zero on success, or @c 0 on error.
- */
-int coap_add_token(coap_pdu_t *pdu,
-                  size_t len,
-                  const unsigned char *data);
-
-/**
- * Adds option of given type to pdu that is passed as first
- * parameter.
- * coap_add_option() destroys the PDU's data, so coap_add_data() must be called
- * after all options have been added. As coap_add_token() destroys the options
- * following the token, the token must be added before coap_add_option() is
- * called. This function returns the number of bytes written or @c 0 on error.
- */
-size_t coap_add_option(coap_pdu_t *pdu,
-                       unsigned short type,
-                       unsigned int len,
-                       const unsigned char *data);
-
-/**
- * Adds option of given type to pdu that is passed as first parameter, but does
- * not write a value. It works like coap_add_option with respect to calling
- * sequence (i.e. after token and before data). This function returns a memory
- * address to which the option data has to be written before the PDU can be
- * sent, or @c NULL on error.
- */
-unsigned char *coap_add_option_later(coap_pdu_t *pdu,
-                                     unsigned short type,
-                                     unsigned int len);
-
-/**
- * Adds given data to the pdu that is passed as first parameter. Note that the
- * PDU's data is destroyed by coap_add_option(). coap_add_data() must be called
- * only once per PDU, otherwise the result is undefined.
- */
-int coap_add_data(coap_pdu_t *pdu,
-                  unsigned int len,
-                  const unsigned char *data);
-
-/**
- * Retrieves the length and data pointer of specified PDU. Returns 0 on error or
- * 1 if *len and *data have correct values. Note that these values are destroyed
- * with the pdu.
- */
-int coap_get_data(coap_pdu_t *pdu,
-                  size_t *len,
-                  unsigned char **data);
-
-#endif /* _COAP_PDU_H_ */
diff --git a/tools/sdk/include/coap/prng.h b/tools/sdk/include/coap/prng.h
deleted file mode 100644
index da6d9534404..00000000000
--- a/tools/sdk/include/coap/prng.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * prng.h -- Pseudo Random Numbers
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file prng.h
- * @brief Pseudo Random Numbers
- */
-
-#ifndef _COAP_PRNG_H_
-#define _COAP_PRNG_H_
-
-/**
- * @defgroup prng Pseudo Random Numbers
- * @{
- */
-
-#if defined(WITH_POSIX) || (defined(WITH_LWIP) && !defined(LWIP_RAND))
-#include <stdlib.h>
-
-/**
- * Fills \p buf with \p len random bytes. This is the default implementation for
- * prng(). You might want to change prng() to use a better PRNG on your specific
- * platform.
- */
-static inline int
-coap_prng_impl(unsigned char *buf, size_t len) {
-  while (len--)
-    *buf++ = rand() & 0xFF;
-  return 1;
-}
-#endif /* WITH_POSIX */
-
-#ifdef WITH_CONTIKI
-#include <string.h>
-
-/**
- * Fills \p buf with \p len random bytes. This is the default implementation for
- * prng(). You might want to change prng() to use a better PRNG on your specific
- * platform.
- */
-static inline int
-contiki_prng_impl(unsigned char *buf, size_t len) {
-  unsigned short v = random_rand();
-  while (len > sizeof(v)) {
-    memcpy(buf, &v, sizeof(v));
-    len -= sizeof(v);
-    buf += sizeof(v);
-    v = random_rand();
-  }
-
-  memcpy(buf, &v, len);
-  return 1;
-}
-
-#define prng(Buf,Length) contiki_prng_impl((Buf), (Length))
-#define prng_init(Value) random_init((unsigned short)(Value))
-#endif /* WITH_CONTIKI */
-
-#if defined(WITH_LWIP) && defined(LWIP_RAND)
-static inline int
-lwip_prng_impl(unsigned char *buf, size_t len) {
-  u32_t v = LWIP_RAND();
-  while (len > sizeof(v)) {
-    memcpy(buf, &v, sizeof(v));
-    len -= sizeof(v);
-    buf += sizeof(v);
-    v = LWIP_RAND();
-  }
-
-  memcpy(buf, &v, len);
-  return 1;
-}
-
-#define prng(Buf,Length) lwip_prng_impl((Buf), (Length))
-#define prng_init(Value)
-
-#endif /* WITH_LWIP */
-
-#ifndef prng
-/**
- * Fills \p Buf with \p Length bytes of random data.
- *
- * @hideinitializer
- */
-#define prng(Buf,Length) coap_prng_impl((Buf), (Length))
-#endif
-
-#ifndef prng_init
-/**
- * Called to set the PRNG seed. You may want to re-define this to allow for a
- * better PRNG.
- *
- * @hideinitializer
- */
-#define prng_init(Value) srand((unsigned long)(Value))
-#endif
-
-/** @} */
-
-#endif /* _COAP_PRNG_H_ */
diff --git a/tools/sdk/include/coap/resource.h b/tools/sdk/include/coap/resource.h
deleted file mode 100644
index dbb19a8d1f6..00000000000
--- a/tools/sdk/include/coap/resource.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * resource.h -- generic resource handling
- *
- * Copyright (C) 2010,2011,2014,2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-/**
- * @file resource.h
- * @brief Generic resource handling
- */
-
-#ifndef _COAP_RESOURCE_H_
-#define _COAP_RESOURCE_H_
-
-# include <assert.h>
-
-#ifndef COAP_RESOURCE_CHECK_TIME
-/** The interval in seconds to check if resources have changed. */
-#define COAP_RESOURCE_CHECK_TIME 2
-#endif /* COAP_RESOURCE_CHECK_TIME */
-
-#ifdef COAP_RESOURCES_NOHASH
-#  include "utlist.h"
-#else
-#  include "uthash.h"
-#endif
-
-#include "hashkey.h"
-#include "async.h"
-#include "str.h"
-#include "pdu.h"
-#include "net.h"
-#include "subscribe.h"
-
-/**
- * Definition of message handler function (@sa coap_resource_t).
- */
-typedef void (*coap_method_handler_t)
-  (coap_context_t  *,
-   struct coap_resource_t *,
-   const coap_endpoint_t *,
-   coap_address_t *,
-   coap_pdu_t *,
-   str * /* token */,
-   coap_pdu_t * /* response */);
-
-#define COAP_ATTR_FLAGS_RELEASE_NAME  0x1
-#define COAP_ATTR_FLAGS_RELEASE_VALUE 0x2
-
-typedef struct coap_attr_t {
-  struct coap_attr_t *next;
-  str name;
-  str value;
-  int flags;
-} coap_attr_t;
-
-/** The URI passed to coap_resource_init() is free'd by coap_delete_resource(). */
-#define COAP_RESOURCE_FLAGS_RELEASE_URI 0x1
-
-/**
- * Notifications will be sent non-confirmable by default. RFC 7641 Section 4.5
- * https://tools.ietf.org/html/rfc7641#section-4.5
- */
-#define COAP_RESOURCE_FLAGS_NOTIFY_NON  0x0
-
-/**
- * Notifications will be sent confirmable by default. RFC 7641 Section 4.5
- * https://tools.ietf.org/html/rfc7641#section-4.5
- */
-#define COAP_RESOURCE_FLAGS_NOTIFY_CON  0x2
-
-typedef struct coap_resource_t {
-  unsigned int dirty:1;          /**< set to 1 if resource has changed */
-  unsigned int partiallydirty:1; /**< set to 1 if some subscribers have not yet
-                                  *   been notified of the last change */
-  unsigned int observable:1;     /**< can be observed */
-  unsigned int cacheable:1;      /**< can be cached */
-
-  /**
-   * Used to store handlers for the four coap methods @c GET, @c POST, @c PUT,
-   * and @c DELETE. coap_dispatch() will pass incoming requests to the handler
-   * that corresponds to its request method or generate a 4.05 response if no
-   * handler is available.
-   */
-  coap_method_handler_t handler[4];
-
-  coap_key_t key;                /**< the actual key bytes for this resource */
-
-#ifdef COAP_RESOURCES_NOHASH
-  struct coap_resource_t *next;
-#else
-  UT_hash_handle hh;
-#endif
-
-  coap_attr_t *link_attr; /**< attributes to be included with the link format */
-  coap_subscription_t *subscribers;  /**< list of observers for this resource */
-
-  /**
-   * Request URI for this resource. This field will point into the static
-   * memory.
-   */
-  str uri;
-  int flags;
-
-} coap_resource_t;
-
-/**
- * Creates a new resource object and initializes the link field to the string
- * of length @p len. This function returns the new coap_resource_t object.
- *
- * @param uri    The URI path of the new resource.
- * @param len    The length of @p uri.
- * @param flags  Flags for memory management (in particular release of memory).
- *
- * @return       A pointer to the new object or @c NULL on error.
- */
-coap_resource_t *coap_resource_init(const unsigned char *uri,
-                                    size_t len, int flags);
-
-
-/**
- * Sets the notification message type of resource @p r to given
- * @p mode which must be one of @c COAP_RESOURCE_FLAGS_NOTIFY_NON
- * or @c COAP_RESOURCE_FLAGS_NOTIFY_CON.
- */
-static inline void
-coap_resource_set_mode(coap_resource_t *r, int mode) {
-  r->flags = (r->flags & !COAP_RESOURCE_FLAGS_NOTIFY_CON) | mode;
-}
-
-/**
- * Registers the given @p resource for @p context. The resource must have been
- * created by coap_resource_init(), the storage allocated for the resource will
- * be released by coap_delete_resource().
- *
- * @param context  The context to use.
- * @param resource The resource to store.
- */
-void coap_add_resource(coap_context_t *context, coap_resource_t *resource);
-
-/**
- * Deletes a resource identified by @p key. The storage allocated for that
- * resource is freed.
- *
- * @param context  The context where the resources are stored.
- * @param key      The unique key for the resource to delete.
- *
- * @return         @c 1 if the resource was found (and destroyed),
- *                 @c 0 otherwise.
- */
-int coap_delete_resource(coap_context_t *context, coap_key_t key);
-
-/**
- * Deletes all resources from given @p context and frees their storage.
- *
- * @param context The CoAP context with the resources to be deleted.
- */
-void coap_delete_all_resources(coap_context_t *context);
-
-/**
- * Registers a new attribute with the given @p resource. As the
- * attributes str fields will point to @p name and @p val the
- * caller must ensure that these pointers are valid during the
- * attribute's lifetime.
- *
- * @param resource The resource to register the attribute with.
- * @param name     The attribute's name.
- * @param nlen     Length of @p name.
- * @param val      The attribute's value or @c NULL if none.
- * @param vlen     Length of @p val if specified.
- * @param flags    Flags for memory management (in particular release of
- *                 memory).
- *
- * @return         A pointer to the new attribute or @c NULL on error.
- */
-coap_attr_t *coap_add_attr(coap_resource_t *resource,
-                           const unsigned char *name,
-                           size_t nlen,
-                           const unsigned char *val,
-                           size_t vlen,
-                           int flags);
-
-/**
- * Returns @p resource's coap_attr_t object with given @p name if found, @c NULL
- * otherwise.
- *
- * @param resource The resource to search for attribute @p name.
- * @param name     Name of the requested attribute.
- * @param nlen     Actual length of @p name.
- * @return         The first attribute with specified @p name or @c NULL if none
- *                 was found.
- */
-coap_attr_t *coap_find_attr(coap_resource_t *resource,
-                            const unsigned char *name,
-                            size_t nlen);
-
-/**
- * Deletes an attribute.
- *
- * @param attr Pointer to a previously created attribute.
- *
- */
-void coap_delete_attr(coap_attr_t *attr);
-
-/**
- * Status word to encode the result of conditional print or copy operations such
- * as coap_print_link(). The lower 28 bits of coap_print_status_t are used to
- * encode the number of characters that has actually been printed, bits 28 to 31
- * encode the status.  When COAP_PRINT_STATUS_ERROR is set, an error occurred
- * during output. In this case, the other bits are undefined.
- * COAP_PRINT_STATUS_TRUNC indicates that the output is truncated, i.e. the
- * printing would have exceeded the current buffer.
- */
-typedef unsigned int coap_print_status_t;
-
-#define COAP_PRINT_STATUS_MASK  0xF0000000u
-#define COAP_PRINT_OUTPUT_LENGTH(v) ((v) & ~COAP_PRINT_STATUS_MASK)
-#define COAP_PRINT_STATUS_ERROR 0x80000000u
-#define COAP_PRINT_STATUS_TRUNC 0x40000000u
-
-/**
- * Writes a description of this resource in link-format to given text buffer. @p
- * len must be initialized to the maximum length of @p buf and will be set to
- * the number of characters actually written if successful. This function
- * returns @c 1 on success or @c 0 on error.
- *
- * @param resource The resource to describe.
- * @param buf      The output buffer to write the description to.
- * @param len      Must be initialized to the length of @p buf and
- *                 will be set to the length of the printed link description.
- * @param offset   The offset within the resource description where to
- *                 start writing into @p buf. This is useful for dealing
- *                 with the Block2 option. @p offset is updated during
- *                 output as it is consumed.
- *
- * @return If COAP_PRINT_STATUS_ERROR is set, an error occured. Otherwise,
- *         the lower 28 bits will indicate the number of characters that
- *         have actually been output into @p buffer. The flag
- *         COAP_PRINT_STATUS_TRUNC indicates that the output has been
- *         truncated.
- */
-coap_print_status_t coap_print_link(const coap_resource_t *resource,
-                                    unsigned char *buf,
-                                    size_t *len,
-                                    size_t *offset);
-
-/**
- * Registers the specified @p handler as message handler for the request type @p
- * method
- *
- * @param resource The resource for which the handler shall be registered.
- * @param method   The CoAP request method to handle.
- * @param handler  The handler to register with @p resource.
- */
-static inline void
-coap_register_handler(coap_resource_t *resource,
-                      unsigned char method,
-                      coap_method_handler_t handler) {
-  assert(resource);
-  assert(method > 0 && (size_t)(method-1) < sizeof(resource->handler)/sizeof(coap_method_handler_t));
-  resource->handler[method-1] = handler;
-}
-
-/**
- * Returns the resource identified by the unique string @p key. If no resource
- * was found, this function returns @c NULL.
- *
- * @param context  The context to look for this resource.
- * @param key      The unique key of the resource.
- *
- * @return         A pointer to the resource or @c NULL if not found.
- */
-coap_resource_t *coap_get_resource_from_key(coap_context_t *context,
-                                            coap_key_t key);
-
-/**
- * Calculates the hash key for the resource requested by the Uri-Options of @p
- * request. This function calls coap_hash() for every path segment.
- *
- * @param request The requesting pdu.
- * @param key     The resulting hash is stored in @p key.
- */
-void coap_hash_request_uri(const coap_pdu_t *request, coap_key_t key);
-
-/**
- * @addtogroup observe
- */
-
-/**
- * Adds the specified peer as observer for @p resource. The subscription is
- * identified by the given @p token. This function returns the registered
- * subscription information if the @p observer has been added, or @c NULL on
- * error.
- *
- * @param resource        The observed resource.
- * @param local_interface The local network interface where the observer is
- *                        attached to.
- * @param observer        The remote peer that wants to received status updates.
- * @param token           The token that identifies this subscription.
- * @return                A pointer to the added/updated subscription
- *                        information or @c NULL on error.
- */
-coap_subscription_t *coap_add_observer(coap_resource_t *resource,
-                                       const coap_endpoint_t *local_interface,
-                                       const coap_address_t *observer,
-                                       const str *token);
-
-/**
- * Returns a subscription object for given @p peer.
- *
- * @param resource The observed resource.
- * @param peer     The address to search for.
- * @param token    The token that identifies this subscription or @c NULL for
- *                 any token.
- * @return         A valid subscription if exists or @c NULL otherwise.
- */
-coap_subscription_t *coap_find_observer(coap_resource_t *resource,
-                                        const coap_address_t *peer,
-                                        const str *token);
-
-/**
- * Marks an observer as alive.
- *
- * @param context  The CoAP context to use.
- * @param observer The transport address of the observer.
- * @param token    The corresponding token that has been used for the
- *                 subscription.
- */
-void coap_touch_observer(coap_context_t *context,
-                         const coap_address_t *observer,
-                         const str *token);
-
-/**
- * Removes any subscription for @p observer from @p resource and releases the
- * allocated storage. The result is @c 1 if an observation relationship with @p
- * observer and @p token existed, @c 0 otherwise.
- *
- * @param resource The observed resource.
- * @param observer The observer's address.
- * @param token    The token that identifies this subscription or @c NULL for
- *                 any token.
- * @return         @c 1 if the observer has been deleted, @c 0 otherwise.
- */
-int coap_delete_observer(coap_resource_t *resource,
-                         const coap_address_t *observer,
-                         const str *token);
-
-/**
- * Checks for all known resources, if they are dirty and notifies subscribed
- * observers.
- */
-void coap_check_notify(coap_context_t *context);
-
-#ifdef COAP_RESOURCES_NOHASH
-
-#define RESOURCES_ADD(r, obj) \
-  LL_PREPEND((r), (obj))
-
-#define RESOURCES_DELETE(r, obj) \
-  LL_DELETE((r), (obj))
-
-#define RESOURCES_ITER(r,tmp) \
-  coap_resource_t *tmp;       \
-  LL_FOREACH((r), tmp)
-
-#define RESOURCES_FIND(r, k, res) {                         \
-    coap_resource_t *tmp;                                   \
-    (res) = tmp = NULL;                                     \
-    LL_FOREACH((r), tmp) {                                  \
-      if (memcmp((k), tmp->key, sizeof(coap_key_t)) == 0) { \
-        (res) = tmp;                                        \
-        break;                                              \
-      }                                                     \
-    }                                                       \
-  }
-#else /* COAP_RESOURCES_NOHASH */
-
-#define RESOURCES_ADD(r, obj) \
-  HASH_ADD(hh, (r), key, sizeof(coap_key_t), (obj))
-
-#define RESOURCES_DELETE(r, obj) \
-  HASH_DELETE(hh, (r), (obj))
-
-#define RESOURCES_ITER(r,tmp)  \
-  coap_resource_t *tmp, *rtmp; \
-  HASH_ITER(hh, (r), tmp, rtmp)
-
-#define RESOURCES_FIND(r, k, res) {                     \
-    HASH_FIND(hh, (r), (k), sizeof(coap_key_t), (res)); \
-  }
-
-#endif /* COAP_RESOURCES_NOHASH */
-
-/** @} */
-
-coap_print_status_t coap_print_wellknown(coap_context_t *,
-                                         unsigned char *,
-                                         size_t *, size_t,
-                                         coap_opt_t *);
-
-void coap_handle_failed_notify(coap_context_t *,
-                               const coap_address_t *,
-                               const str *);
-
-#endif /* _COAP_RESOURCE_H_ */
diff --git a/tools/sdk/include/coap/str.h b/tools/sdk/include/coap/str.h
deleted file mode 100644
index 3dfa6731550..00000000000
--- a/tools/sdk/include/coap/str.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * str.h -- strings to be used in the CoAP library
- *
- * Copyright (C) 2010-2011 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_STR_H_
-#define _COAP_STR_H_
-
-#include <string.h>
-
-typedef struct {
-  size_t length;    /* length of string */
-  unsigned char *s; /* string data */
-} str;
-
-#define COAP_SET_STR(st,l,v) { (st)->length = (l), (st)->s = (v); }
-
-/**
- * Returns a new string object with at least size bytes storage allocated. The
- * string must be released using coap_delete_string();
- */
-str *coap_new_string(size_t size);
-
-/**
- * Deletes the given string and releases any memory allocated.
- */
-void coap_delete_string(str *);
-
-#endif /* _COAP_STR_H_ */
diff --git a/tools/sdk/include/coap/subscribe.h b/tools/sdk/include/coap/subscribe.h
deleted file mode 100644
index 52068642dd7..00000000000
--- a/tools/sdk/include/coap/subscribe.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * subscribe.h -- subscription handling for CoAP
- *                see draft-ietf-core-observe-16
- *
- * Copyright (C) 2010-2012,2014-2015 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-
-#ifndef _COAP_SUBSCRIBE_H_
-#define _COAP_SUBSCRIBE_H_
-
-#include "address.h"
-#include "coap_io.h"
-
-/**
- * @defgroup observe Resource observation
- * @{
- */
-
-/**
- * The value COAP_OBSERVE_ESTABLISH in a GET request indicates a new observe
- * relationship for (sender address, token) is requested.
- */
-#define COAP_OBSERVE_ESTABLISH 0
-
-/**
- * The value COAP_OBSERVE_CANCEL in a GET request indicates that the observe
- * relationship for (sender address, token) must be cancelled.
- */
-#define COAP_OBSERVE_CANCEL 1
-
-#ifndef COAP_OBS_MAX_NON
-/**
- * Number of notifications that may be sent non-confirmable before a confirmable
- * message is sent to detect if observers are alive. The maximum allowed value
- * here is @c 15.
- */
-#define COAP_OBS_MAX_NON   5
-#endif /* COAP_OBS_MAX_NON */
-
-#ifndef COAP_OBS_MAX_FAIL
-/**
- * Number of confirmable notifications that may fail (i.e. time out without
- * being ACKed) before an observer is removed. The maximum value for
- * COAP_OBS_MAX_FAIL is @c 3.
- */
-#define COAP_OBS_MAX_FAIL  3
-#endif /* COAP_OBS_MAX_FAIL */
-
-/** Subscriber information */
-typedef struct coap_subscription_t {
-  struct coap_subscription_t *next; /**< next element in linked list */
-  coap_endpoint_t local_if;         /**< local communication interface */
-  coap_address_t subscriber;        /**< address and port of subscriber */
-
-  unsigned int non_cnt:4;  /**< up to 15 non-confirmable notifies allowed */
-  unsigned int fail_cnt:2; /**< up to 3 confirmable notifies can fail */
-  unsigned int dirty:1;    /**< set if the notification temporarily could not be
-                            *   sent (in that case, the resource's partially
-                            *   dirty flag is set too) */
-  size_t token_length;     /**< actual length of token */
-  unsigned char token[8];  /**< token used for subscription */
-} coap_subscription_t;
-
-void coap_subscription_init(coap_subscription_t *);
-
-/** @} */
-
-#endif /* _COAP_SUBSCRIBE_H_ */
diff --git a/tools/sdk/include/coap/uri.h b/tools/sdk/include/coap/uri.h
deleted file mode 100644
index 2340a7a6c88..00000000000
--- a/tools/sdk/include/coap/uri.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * uri.h -- helper functions for URI treatment
- *
- * Copyright (C) 2010-2011,2016 Olaf Bergmann <bergmann@tzi.org>
- *
- * This file is part of the CoAP library libcoap. Please see README for terms
- * of use.
- */
-
-#ifndef _COAP_URI_H_
-#define _COAP_URI_H_
-
-#include "hashkey.h"
-#include "str.h"
-
-/**
- * Representation of parsed URI. Components may be filled from a string with
- * coap_split_uri() and can be used as input for option-creation functions.
- */
-typedef struct {
-  str host;             /**< host part of the URI */
-  unsigned short port;  /**< The port in host byte order */
-  str path;             /**< Beginning of the first path segment. 
-                             Use coap_split_path() to create Uri-Path options */
-  str query;            /**<  The query part if present */
-} coap_uri_t;
-
-/**
- * Creates a new coap_uri_t object from the specified URI. Returns the new
- * object or NULL on error. The memory allocated by the new coap_uri_t
- * must be released using coap_free().
- *
- * @param uri The URI path to copy.
- * @param length The length of uri.
- *
- * @return New URI object or NULL on error.
- */
-coap_uri_t *coap_new_uri(const unsigned char *uri, unsigned int length);
-
-/**
- * Clones the specified coap_uri_t object. Thie function allocates sufficient
- * memory to hold the coap_uri_t structure and its contents. The object must
- * be released with coap_free(). */
-coap_uri_t *coap_clone_uri(const coap_uri_t *uri);
-
-/**
- * Calculates a hash over the given path and stores the result in 
- * @p key. This function returns @c 0 on error or @c 1 on success.
- * 
- * @param path The URI path to generate hash for.
- * @param len  The length of @p path.
- * @param key  The output buffer.
- * 
- * @return @c 1 if @p key was set, @c 0 otherwise.
- */
-int coap_hash_path(const unsigned char *path, size_t len, coap_key_t key);
-
-/**
- * @defgroup uri_parse URI Parsing Functions
- *
- * CoAP PDUs contain normalized URIs with their path and query split into
- * multiple segments. The functions in this module help splitting strings.
- * @{
- */
-
-/**
- * Parses a given string into URI components. The identified syntactic
- * components are stored in the result parameter @p uri. Optional URI
- * components that are not specified will be set to { 0, 0 }, except for the
- * port which is set to @c COAP_DEFAULT_PORT. This function returns @p 0 if
- * parsing succeeded, a value less than zero otherwise.
- * 
- * @param str_var The string to split up.
- * @param len     The actual length of @p str_var
- * @param uri     The coap_uri_t object to store the result.
- * @return        @c 0 on success, or < 0 on error.
- *
- */
-int coap_split_uri(const unsigned char *str_var, size_t len, coap_uri_t *uri);
-
-/**
- * Splits the given URI path into segments. Each segment is preceded
- * by an option pseudo-header with delta-value 0 and the actual length
- * of the respective segment after percent-decoding.
- * 
- * @param s      The path string to split. 
- * @param length The actual length of @p s.
- * @param buf    Result buffer for parsed segments. 
- * @param buflen Maximum length of @p buf. Will be set to the actual number
- *               of bytes written into buf on success.
- * 
- * @return       The number of segments created or @c -1 on error.
- */
-int coap_split_path(const unsigned char *s,
-                    size_t length,
-                    unsigned char *buf,
-                    size_t *buflen);
-
-/** 
- * Splits the given URI query into segments. Each segment is preceded
- * by an option pseudo-header with delta-value 0 and the actual length
- * of the respective query term.
- * 
- * @param s      The query string to split. 
- * @param length The actual length of @p s.
- * @param buf    Result buffer for parsed segments. 
- * @param buflen Maximum length of @p buf. Will be set to the actual number
- *               of bytes written into buf on success.
- * 
- * @return       The number of segments created or @c -1 on error.
- *
- * @bug This function does not reserve additional space for delta > 12.
- */
-int coap_split_query(const unsigned char *s,
-                     size_t length,
-                     unsigned char *buf,
-                     size_t *buflen);
-
-/** @} */
-
-#endif /* _COAP_URI_H_ */
diff --git a/tools/sdk/include/coap/uthash.h b/tools/sdk/include/coap/uthash.h
deleted file mode 100644
index 32b7a81cfbb..00000000000
--- a/tools/sdk/include/coap/uthash.h
+++ /dev/null
@@ -1,963 +0,0 @@
-/*
-Copyright (c) 2003-2014, Troy D. Hanson     http://troydhanson.github.com/uthash/
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
-OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#ifndef UTHASH_H
-#define UTHASH_H
-
-#include <string.h>   /* memcmp,strlen */
-#include <stddef.h>   /* ptrdiff_t */
-#include <stdlib.h>   /* exit() */
-
-/* These macros use decltype or the earlier __typeof GNU extension.
-   As decltype is only available in newer compilers (VS2010 or gcc 4.3+
-   when compiling c++ source) this code uses whatever method is needed
-   or, for VS2008 where neither is available, uses casting workarounds. */
-#if defined(_MSC_VER)   /* MS compiler */
-#if _MSC_VER >= 1600 && defined(__cplusplus)  /* VS2010 or newer in C++ mode */
-#define DECLTYPE(x) (decltype(x))
-#else                   /* VS2008 or older (or VS2010 in C mode) */
-#define NO_DECLTYPE
-#define DECLTYPE(x)
-#endif
-#elif defined(__BORLANDC__) || defined(__LCC__) || defined(__WATCOMC__)
-#define NO_DECLTYPE
-#define DECLTYPE(x)
-#else                   /* GNU, Sun and other compilers */
-#define DECLTYPE(x) (__typeof(x))
-#endif
-
-#ifdef NO_DECLTYPE
-#define DECLTYPE_ASSIGN(dst,src)                                                 \
-do {                                                                             \
-  char **_da_dst = (char**)(&(dst));                                             \
-  *_da_dst = (char*)(src);                                                       \
-} while(0)
-#else
-#define DECLTYPE_ASSIGN(dst,src)                                                 \
-do {                                                                             \
-  (dst) = DECLTYPE(dst)(src);                                                    \
-} while(0)
-#endif
-
-/* a number of the hash function use uint32_t which isn't defined on Pre VS2010 */
-#if defined (_WIN32)
-#if defined(_MSC_VER) && _MSC_VER >= 1600
-#include <stdint.h>
-#elif defined(__WATCOMC__)
-#include <stdint.h>
-#else
-typedef unsigned int uint32_t;
-typedef unsigned char uint8_t;
-#endif
-#else
-#include <stdint.h>
-#endif
-
-#define UTHASH_VERSION 1.9.9
-
-#ifndef uthash_fatal
-#define uthash_fatal(msg) exit(-1)        /* fatal error (out of memory,etc) */
-#endif
-#ifndef uthash_malloc
-#define uthash_malloc(sz) malloc(sz)      /* malloc fcn                      */
-#endif
-#ifndef uthash_free
-#define uthash_free(ptr,sz) free(ptr)     /* free fcn                        */
-#endif
-
-#ifndef uthash_noexpand_fyi
-#define uthash_noexpand_fyi(tbl)          /* can be defined to log noexpand  */
-#endif
-#ifndef uthash_expand_fyi
-#define uthash_expand_fyi(tbl)            /* can be defined to log expands   */
-#endif
-
-/* initial number of buckets */
-#define HASH_INITIAL_NUM_BUCKETS 32      /* initial number of buckets        */
-#define HASH_INITIAL_NUM_BUCKETS_LOG2 5  /* lg2 of initial number of buckets */
-#define HASH_BKT_CAPACITY_THRESH 10      /* expand when bucket count reaches */
-
-/* calculate the element whose hash handle address is hhe */
-#define ELMT_FROM_HH(tbl,hhp) ((void*)(((char*)(hhp)) - ((tbl)->hho)))
-
-#define HASH_FIND(hh,head,keyptr,keylen,out)                                     \
-do {                                                                             \
-  out=NULL;                                                                      \
-  if (head) {                                                                    \
-     unsigned _hf_bkt,_hf_hashv;                                                 \
-     HASH_FCN(keyptr,keylen, (head)->hh.tbl->num_buckets, _hf_hashv, _hf_bkt);   \
-     if (HASH_BLOOM_TEST((head)->hh.tbl, _hf_hashv)) {                           \
-       HASH_FIND_IN_BKT((head)->hh.tbl, hh, (head)->hh.tbl->buckets[ _hf_bkt ],  \
-                        keyptr,keylen,out);                                      \
-     }                                                                           \
-  }                                                                              \
-} while (0)
-
-#ifdef HASH_BLOOM
-#define HASH_BLOOM_BITLEN (1ULL << HASH_BLOOM)
-#define HASH_BLOOM_BYTELEN (HASH_BLOOM_BITLEN/8) + ((HASH_BLOOM_BITLEN%8) ? 1:0)
-#define HASH_BLOOM_MAKE(tbl)                                                     \
-do {                                                                             \
-  (tbl)->bloom_nbits = HASH_BLOOM;                                               \
-  (tbl)->bloom_bv = (uint8_t*)uthash_malloc(HASH_BLOOM_BYTELEN);                 \
-  if (!((tbl)->bloom_bv))  { uthash_fatal( "out of memory"); }                   \
-  memset((tbl)->bloom_bv, 0, HASH_BLOOM_BYTELEN);                                \
-  (tbl)->bloom_sig = HASH_BLOOM_SIGNATURE;                                       \
-} while (0)
-
-#define HASH_BLOOM_FREE(tbl)                                                     \
-do {                                                                             \
-  uthash_free((tbl)->bloom_bv, HASH_BLOOM_BYTELEN);                              \
-} while (0)
-
-#define HASH_BLOOM_BITSET(bv,idx) (bv[(idx)/8] |= (1U << ((idx)%8)))
-#define HASH_BLOOM_BITTEST(bv,idx) (bv[(idx)/8] & (1U << ((idx)%8)))
-
-#define HASH_BLOOM_ADD(tbl,hashv)                                                \
-  HASH_BLOOM_BITSET((tbl)->bloom_bv, (hashv & (uint32_t)((1ULL << (tbl)->bloom_nbits) - 1)))
-
-#define HASH_BLOOM_TEST(tbl,hashv)                                               \
-  HASH_BLOOM_BITTEST((tbl)->bloom_bv, (hashv & (uint32_t)((1ULL << (tbl)->bloom_nbits) - 1)))
-
-#else
-#define HASH_BLOOM_MAKE(tbl)
-#define HASH_BLOOM_FREE(tbl)
-#define HASH_BLOOM_ADD(tbl,hashv)
-#define HASH_BLOOM_TEST(tbl,hashv) (1)
-#define HASH_BLOOM_BYTELEN 0
-#endif
-
-#define HASH_MAKE_TABLE(hh,head)                                                 \
-do {                                                                             \
-  (head)->hh.tbl = (UT_hash_table*)uthash_malloc(                                \
-                  sizeof(UT_hash_table));                                        \
-  if (!((head)->hh.tbl))  { uthash_fatal( "out of memory"); }                    \
-  memset((head)->hh.tbl, 0, sizeof(UT_hash_table));                              \
-  (head)->hh.tbl->tail = &((head)->hh);                                          \
-  (head)->hh.tbl->num_buckets = HASH_INITIAL_NUM_BUCKETS;                        \
-  (head)->hh.tbl->log2_num_buckets = HASH_INITIAL_NUM_BUCKETS_LOG2;              \
-  (head)->hh.tbl->hho = (char*)(&(head)->hh) - (char*)(head);                    \
-  (head)->hh.tbl->buckets = (UT_hash_bucket*)uthash_malloc(                      \
-          HASH_INITIAL_NUM_BUCKETS*sizeof(struct UT_hash_bucket));               \
-  if (! (head)->hh.tbl->buckets) { uthash_fatal( "out of memory"); }             \
-  memset((head)->hh.tbl->buckets, 0,                                             \
-          HASH_INITIAL_NUM_BUCKETS*sizeof(struct UT_hash_bucket));               \
-  HASH_BLOOM_MAKE((head)->hh.tbl);                                               \
-  (head)->hh.tbl->signature = HASH_SIGNATURE;                                    \
-} while(0)
-
-#define HASH_ADD(hh,head,fieldname,keylen_in,add)                                \
-        HASH_ADD_KEYPTR(hh,head,&((add)->fieldname),keylen_in,add)
-
-#define HASH_REPLACE(hh,head,fieldname,keylen_in,add,replaced)                   \
-do {                                                                             \
-  replaced=NULL;                                                                 \
-  HASH_FIND(hh,head,&((add)->fieldname),keylen_in,replaced);                     \
-  if (replaced!=NULL) {                                                          \
-     HASH_DELETE(hh,head,replaced);                                              \
-  };                                                                             \
-  HASH_ADD(hh,head,fieldname,keylen_in,add);                                     \
-} while(0)
-
-#define HASH_ADD_KEYPTR(hh,head,keyptr,keylen_in,add)                            \
-do {                                                                             \
- unsigned _ha_bkt;                                                               \
- (add)->hh.next = NULL;                                                          \
- (add)->hh.key = (char*)(keyptr);                                                \
- (add)->hh.keylen = (unsigned)(keylen_in);                                       \
- if (!(head)) {                                                                  \
-    head = (add);                                                                \
-    (head)->hh.prev = NULL;                                                      \
-    HASH_MAKE_TABLE(hh,head);                                                    \
- } else {                                                                        \
-    (head)->hh.tbl->tail->next = (add);                                          \
-    (add)->hh.prev = ELMT_FROM_HH((head)->hh.tbl, (head)->hh.tbl->tail);         \
-    (head)->hh.tbl->tail = &((add)->hh);                                         \
- }                                                                               \
- (head)->hh.tbl->num_items++;                                                    \
- (add)->hh.tbl = (head)->hh.tbl;                                                 \
- HASH_FCN(keyptr,keylen_in, (head)->hh.tbl->num_buckets,                         \
-         (add)->hh.hashv, _ha_bkt);                                              \
- HASH_ADD_TO_BKT((head)->hh.tbl->buckets[_ha_bkt],&(add)->hh);                   \
- HASH_BLOOM_ADD((head)->hh.tbl,(add)->hh.hashv);                                 \
- HASH_EMIT_KEY(hh,head,keyptr,keylen_in);                                        \
- HASH_FSCK(hh,head);                                                             \
-} while(0)
-
-#define HASH_TO_BKT( hashv, num_bkts, bkt )                                      \
-do {                                                                             \
-  bkt = ((hashv) & ((num_bkts) - 1));                                            \
-} while(0)
-
-/* delete "delptr" from the hash table.
- * "the usual" patch-up process for the app-order doubly-linked-list.
- * The use of _hd_hh_del below deserves special explanation.
- * These used to be expressed using (delptr) but that led to a bug
- * if someone used the same symbol for the head and deletee, like
- *  HASH_DELETE(hh,users,users);
- * We want that to work, but by changing the head (users) below
- * we were forfeiting our ability to further refer to the deletee (users)
- * in the patch-up process. Solution: use scratch space to
- * copy the deletee pointer, then the latter references are via that
- * scratch pointer rather than through the repointed (users) symbol.
- */
-#define HASH_DELETE(hh,head,delptr)                                              \
-do {                                                                             \
-    struct UT_hash_handle *_hd_hh_del;                                           \
-    if ( ((delptr)->hh.prev == NULL) && ((delptr)->hh.next == NULL) )  {         \
-        uthash_free((head)->hh.tbl->buckets,                                     \
-                    (head)->hh.tbl->num_buckets*sizeof(struct UT_hash_bucket) ); \
-        HASH_BLOOM_FREE((head)->hh.tbl);                                         \
-        uthash_free((head)->hh.tbl, sizeof(UT_hash_table));                      \
-        head = NULL;                                                             \
-    } else {                                                                     \
-        unsigned _hd_bkt;                                                        \
-        _hd_hh_del = &((delptr)->hh);                                            \
-        if ((delptr) == ELMT_FROM_HH((head)->hh.tbl,(head)->hh.tbl->tail)) {     \
-            (head)->hh.tbl->tail =                                               \
-                (UT_hash_handle*)((ptrdiff_t)((delptr)->hh.prev) +               \
-                (head)->hh.tbl->hho);                                            \
-        }                                                                        \
-        if ((delptr)->hh.prev) {                                                 \
-            ((UT_hash_handle*)((ptrdiff_t)((delptr)->hh.prev) +                  \
-                    (head)->hh.tbl->hho))->next = (delptr)->hh.next;             \
-        } else {                                                                 \
-            DECLTYPE_ASSIGN(head,(delptr)->hh.next);                             \
-        }                                                                        \
-        if (_hd_hh_del->next) {                                                  \
-            ((UT_hash_handle*)((ptrdiff_t)_hd_hh_del->next +                     \
-                    (head)->hh.tbl->hho))->prev =                                \
-                    _hd_hh_del->prev;                                            \
-        }                                                                        \
-        HASH_TO_BKT( _hd_hh_del->hashv, (head)->hh.tbl->num_buckets, _hd_bkt);   \
-        HASH_DEL_IN_BKT(hh,(head)->hh.tbl->buckets[_hd_bkt], _hd_hh_del);        \
-        (head)->hh.tbl->num_items--;                                             \
-    }                                                                            \
-    HASH_FSCK(hh,head);                                                          \
-} while (0)
-
-
-/* convenience forms of HASH_FIND/HASH_ADD/HASH_DEL */
-#define HASH_FIND_STR(head,findstr,out)                                          \
-    HASH_FIND(hh,head,findstr,(unsigned)strlen(findstr),out)
-#define HASH_ADD_STR(head,strfield,add)                                          \
-    HASH_ADD(hh,head,strfield[0],strlen(add->strfield),add)
-#define HASH_REPLACE_STR(head,strfield,add,replaced)                             \
-    HASH_REPLACE(hh,head,strfield[0],(unsigned)strlen(add->strfield),add,replaced)
-#define HASH_FIND_INT(head,findint,out)                                          \
-    HASH_FIND(hh,head,findint,sizeof(int),out)
-#define HASH_ADD_INT(head,intfield,add)                                          \
-    HASH_ADD(hh,head,intfield,sizeof(int),add)
-#define HASH_REPLACE_INT(head,intfield,add,replaced)                             \
-    HASH_REPLACE(hh,head,intfield,sizeof(int),add,replaced)
-#define HASH_FIND_PTR(head,findptr,out)                                          \
-    HASH_FIND(hh,head,findptr,sizeof(void *),out)
-#define HASH_ADD_PTR(head,ptrfield,add)                                          \
-    HASH_ADD(hh,head,ptrfield,sizeof(void *),add)
-#define HASH_REPLACE_PTR(head,ptrfield,add,replaced)                             \
-    HASH_REPLACE(hh,head,ptrfield,sizeof(void *),add,replaced)
-#define HASH_DEL(head,delptr)                                                    \
-    HASH_DELETE(hh,head,delptr)
-
-/* HASH_FSCK checks hash integrity on every add/delete when HASH_DEBUG is defined.
- * This is for uthash developer only; it compiles away if HASH_DEBUG isn't defined.
- */
-#ifdef HASH_DEBUG
-#define HASH_OOPS(...) do { fprintf(stderr,__VA_ARGS__); exit(-1); } while (0)
-#define HASH_FSCK(hh,head)                                                       \
-do {                                                                             \
-    struct UT_hash_handle *_thh;                                                 \
-    if (head) {                                                                  \
-        unsigned _bkt_i;                                                         \
-        unsigned _count;                                                         \
-        char *_prev;                                                             \
-        _count = 0;                                                              \
-        for( _bkt_i = 0; _bkt_i < (head)->hh.tbl->num_buckets; _bkt_i++) {       \
-            unsigned _bkt_count = 0;                                             \
-            _thh = (head)->hh.tbl->buckets[_bkt_i].hh_head;                      \
-            _prev = NULL;                                                        \
-            while (_thh) {                                                       \
-               if (_prev != (char*)(_thh->hh_prev)) {                            \
-                   HASH_OOPS("invalid hh_prev %p, actual %p\n",                  \
-                    _thh->hh_prev, _prev );                                      \
-               }                                                                 \
-               _bkt_count++;                                                     \
-               _prev = (char*)(_thh);                                            \
-               _thh = _thh->hh_next;                                             \
-            }                                                                    \
-            _count += _bkt_count;                                                \
-            if ((head)->hh.tbl->buckets[_bkt_i].count !=  _bkt_count) {          \
-               HASH_OOPS("invalid bucket count %u, actual %u\n",                 \
-                (head)->hh.tbl->buckets[_bkt_i].count, _bkt_count);              \
-            }                                                                    \
-        }                                                                        \
-        if (_count != (head)->hh.tbl->num_items) {                               \
-            HASH_OOPS("invalid hh item count %u, actual %u\n",                   \
-                (head)->hh.tbl->num_items, _count );                             \
-        }                                                                        \
-        /* traverse hh in app order; check next/prev integrity, count */         \
-        _count = 0;                                                              \
-        _prev = NULL;                                                            \
-        _thh =  &(head)->hh;                                                     \
-        while (_thh) {                                                           \
-           _count++;                                                             \
-           if (_prev !=(char*)(_thh->prev)) {                                    \
-              HASH_OOPS("invalid prev %p, actual %p\n",                          \
-                    _thh->prev, _prev );                                         \
-           }                                                                     \
-           _prev = (char*)ELMT_FROM_HH((head)->hh.tbl, _thh);                    \
-           _thh = ( _thh->next ?  (UT_hash_handle*)((char*)(_thh->next) +        \
-                                  (head)->hh.tbl->hho) : NULL );                 \
-        }                                                                        \
-        if (_count != (head)->hh.tbl->num_items) {                               \
-            HASH_OOPS("invalid app item count %u, actual %u\n",                  \
-                (head)->hh.tbl->num_items, _count );                             \
-        }                                                                        \
-    }                                                                            \
-} while (0)
-#else
-#define HASH_FSCK(hh,head)
-#endif
-
-/* When compiled with -DHASH_EMIT_KEYS, length-prefixed keys are emitted to
- * the descriptor to which this macro is defined for tuning the hash function.
- * The app can #include <unistd.h> to get the prototype for write(2). */
-#ifdef HASH_EMIT_KEYS
-#define HASH_EMIT_KEY(hh,head,keyptr,fieldlen)                                   \
-do {                                                                             \
-    unsigned _klen = fieldlen;                                                   \
-    write(HASH_EMIT_KEYS, &_klen, sizeof(_klen));                                \
-    write(HASH_EMIT_KEYS, keyptr, fieldlen);                                     \
-} while (0)
-#else
-#define HASH_EMIT_KEY(hh,head,keyptr,fieldlen)
-#endif
-
-/* default to Jenkin's hash unless overridden e.g. DHASH_FUNCTION=HASH_SAX */
-#ifdef HASH_FUNCTION
-#define HASH_FCN HASH_FUNCTION
-#else
-#define HASH_FCN HASH_JEN
-#endif
-
-/* The Bernstein hash function, used in Perl prior to v5.6. Note (x<<5+x)=x*33. */
-#define HASH_BER(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _hb_keylen=keylen;                                                    \
-  char *_hb_key=(char*)(key);                                                    \
-  (hashv) = 0;                                                                   \
-  while (_hb_keylen--)  { (hashv) = (((hashv) << 5) + (hashv)) + *_hb_key++; }   \
-  bkt = (hashv) & (num_bkts-1);                                                  \
-} while (0)
-
-
-/* SAX/FNV/OAT/JEN hash functions are macro variants of those listed at
- * http://eternallyconfuzzled.com/tuts/algorithms/jsw_tut_hashing.aspx */
-#define HASH_SAX(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _sx_i;                                                                \
-  char *_hs_key=(char*)(key);                                                    \
-  hashv = 0;                                                                     \
-  for(_sx_i=0; _sx_i < keylen; _sx_i++)                                          \
-      hashv ^= (hashv << 5) + (hashv >> 2) + _hs_key[_sx_i];                     \
-  bkt = hashv & (num_bkts-1);                                                    \
-} while (0)
-/* FNV-1a variation */
-#define HASH_FNV(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _fn_i;                                                                \
-  char *_hf_key=(char*)(key);                                                    \
-  hashv = 2166136261UL;                                                          \
-  for(_fn_i=0; _fn_i < keylen; _fn_i++) {                                        \
-      hashv = hashv ^ _hf_key[_fn_i];                                            \
-      hashv = hashv * 16777619;                                                  \
-  }                                                                              \
-  bkt = hashv & (num_bkts-1);                                                    \
-} while(0)
-
-#define HASH_OAT(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _ho_i;                                                                \
-  char *_ho_key=(char*)(key);                                                    \
-  hashv = 0;                                                                     \
-  for(_ho_i=0; _ho_i < keylen; _ho_i++) {                                        \
-      hashv += _ho_key[_ho_i];                                                   \
-      hashv += (hashv << 10);                                                    \
-      hashv ^= (hashv >> 6);                                                     \
-  }                                                                              \
-  hashv += (hashv << 3);                                                         \
-  hashv ^= (hashv >> 11);                                                        \
-  hashv += (hashv << 15);                                                        \
-  bkt = hashv & (num_bkts-1);                                                    \
-} while(0)
-
-#define HASH_JEN_MIX(a,b,c)                                                      \
-do {                                                                             \
-  a -= b; a -= c; a ^= ( c >> 13 );                                              \
-  b -= c; b -= a; b ^= ( a << 8 );                                               \
-  c -= a; c -= b; c ^= ( b >> 13 );                                              \
-  a -= b; a -= c; a ^= ( c >> 12 );                                              \
-  b -= c; b -= a; b ^= ( a << 16 );                                              \
-  c -= a; c -= b; c ^= ( b >> 5 );                                               \
-  a -= b; a -= c; a ^= ( c >> 3 );                                               \
-  b -= c; b -= a; b ^= ( a << 10 );                                              \
-  c -= a; c -= b; c ^= ( b >> 15 );                                              \
-} while (0)
-
-#define HASH_JEN(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned _hj_i,_hj_j,_hj_k;                                                    \
-  unsigned char *_hj_key=(unsigned char*)(key);                                  \
-  hashv = 0xfeedbeef;                                                            \
-  _hj_i = _hj_j = 0x9e3779b9;                                                    \
-  _hj_k = (unsigned)(keylen);                                                    \
-  while (_hj_k >= 12) {                                                          \
-    _hj_i +=    (_hj_key[0] + ( (unsigned)_hj_key[1] << 8 )                      \
-        + ( (unsigned)_hj_key[2] << 16 )                                         \
-        + ( (unsigned)_hj_key[3] << 24 ) );                                      \
-    _hj_j +=    (_hj_key[4] + ( (unsigned)_hj_key[5] << 8 )                      \
-        + ( (unsigned)_hj_key[6] << 16 )                                         \
-        + ( (unsigned)_hj_key[7] << 24 ) );                                      \
-    hashv += (_hj_key[8] + ( (unsigned)_hj_key[9] << 8 )                         \
-        + ( (unsigned)_hj_key[10] << 16 )                                        \
-        + ( (unsigned)_hj_key[11] << 24 ) );                                     \
-                                                                                 \
-     HASH_JEN_MIX(_hj_i, _hj_j, hashv);                                          \
-                                                                                 \
-     _hj_key += 12;                                                              \
-     _hj_k -= 12;                                                                \
-  }                                                                              \
-  hashv += keylen;                                                               \
-  switch ( _hj_k ) {                                                             \
-     case 11: hashv += ( (unsigned)_hj_key[10] << 24 );                          \
-     case 10: hashv += ( (unsigned)_hj_key[9] << 16 );                           \
-     case 9:  hashv += ( (unsigned)_hj_key[8] << 8 );                            \
-     case 8:  _hj_j += ( (unsigned)_hj_key[7] << 24 );                           \
-     case 7:  _hj_j += ( (unsigned)_hj_key[6] << 16 );                           \
-     case 6:  _hj_j += ( (unsigned)_hj_key[5] << 8 );                            \
-     case 5:  _hj_j += _hj_key[4];                                               \
-     case 4:  _hj_i += ( (unsigned)_hj_key[3] << 24 );                           \
-     case 3:  _hj_i += ( (unsigned)_hj_key[2] << 16 );                           \
-     case 2:  _hj_i += ( (unsigned)_hj_key[1] << 8 );                            \
-     case 1:  _hj_i += _hj_key[0];                                               \
-     /* case 0: nothing left to add */                                           \
-     default: /* make gcc -Wswitch-default happy */                              \
-       ;                                                                         \
-  }                                                                              \
-  HASH_JEN_MIX(_hj_i, _hj_j, hashv);                                             \
-  bkt = hashv & (num_bkts-1);                                                    \
-} while(0)
-
-/* The Paul Hsieh hash function */
-#undef get16bits
-#if (defined(__GNUC__) && defined(__i386__)) || defined(__WATCOMC__)             \
-  || defined(_MSC_VER) || defined (__BORLANDC__) || defined (__TURBOC__)
-#define get16bits(d) (*((const uint16_t *) (d)))
-#endif
-
-#if !defined (get16bits)
-#define get16bits(d) ((((uint32_t)(((const uint8_t *)(d))[1])) << 8)             \
-                       +(uint32_t)(((const uint8_t *)(d))[0]) )
-#endif
-#define HASH_SFH(key,keylen,num_bkts,hashv,bkt)                                  \
-do {                                                                             \
-  unsigned char *_sfh_key=(unsigned char*)(key);                                 \
-  uint32_t _sfh_tmp, _sfh_len = keylen;                                          \
-                                                                                 \
-  int _sfh_rem = _sfh_len & 3;                                                   \
-  _sfh_len >>= 2;                                                                \
-  hashv = 0xcafebabe;                                                            \
-                                                                                 \
-  /* Main loop */                                                                \
-  for (;_sfh_len > 0; _sfh_len--) {                                              \
-    hashv    += get16bits (_sfh_key);                                            \
-    _sfh_tmp       = (uint32_t)(get16bits (_sfh_key+2)) << 11  ^ hashv;          \
-    hashv     = (hashv << 16) ^ _sfh_tmp;                                        \
-    _sfh_key += 2*sizeof (uint16_t);                                             \
-    hashv    += hashv >> 11;                                                     \
-  }                                                                              \
-                                                                                 \
-  /* Handle end cases */                                                         \
-  switch (_sfh_rem) {                                                            \
-    case 3: hashv += get16bits (_sfh_key);                                       \
-            hashv ^= hashv << 16;                                                \
-            hashv ^= (uint32_t)(_sfh_key[sizeof (uint16_t)] << 18);              \
-            hashv += hashv >> 11;                                                \
-            break;                                                               \
-    case 2: hashv += get16bits (_sfh_key);                                       \
-            hashv ^= hashv << 11;                                                \
-            hashv += hashv >> 17;                                                \
-            break;                                                               \
-    case 1: hashv += *_sfh_key;                                                  \
-            hashv ^= hashv << 10;                                                \
-            hashv += hashv >> 1;                                                 \
-  }                                                                              \
-                                                                                 \
-    /* Force "avalanching" of final 127 bits */                                  \
-    hashv ^= hashv << 3;                                                         \
-    hashv += hashv >> 5;                                                         \
-    hashv ^= hashv << 4;                                                         \
-    hashv += hashv >> 17;                                                        \
-    hashv ^= hashv << 25;                                                        \
-    hashv += hashv >> 6;                                                         \
-    bkt = hashv & (num_bkts-1);                                                  \
-} while(0)
-
-#ifdef HASH_USING_NO_STRICT_ALIASING
-/* The MurmurHash exploits some CPU's (x86,x86_64) tolerance for unaligned reads.
- * For other types of CPU's (e.g. Sparc) an unaligned read causes a bus error.
- * MurmurHash uses the faster approach only on CPU's where we know it's safe.
- *
- * Note the preprocessor built-in defines can be emitted using:
- *
- *   gcc -m64 -dM -E - < /dev/null                  (on gcc)
- *   cc -## a.c (where a.c is a simple test file)   (Sun Studio)
- */
-#if (defined(__i386__) || defined(__x86_64__)  || defined(_M_IX86))
-#define MUR_GETBLOCK(p,i) p[i]
-#else /* non intel */
-#define MUR_PLUS0_ALIGNED(p) (((unsigned long)p & 0x3) == 0)
-#define MUR_PLUS1_ALIGNED(p) (((unsigned long)p & 0x3) == 1)
-#define MUR_PLUS2_ALIGNED(p) (((unsigned long)p & 0x3) == 2)
-#define MUR_PLUS3_ALIGNED(p) (((unsigned long)p & 0x3) == 3)
-#define WP(p) ((uint32_t*)((unsigned long)(p) & ~3UL))
-#if (defined(__BIG_ENDIAN__) || defined(SPARC) || defined(__ppc__) || defined(__ppc64__))
-#define MUR_THREE_ONE(p) ((((*WP(p))&0x00ffffff) << 8) | (((*(WP(p)+1))&0xff000000) >> 24))
-#define MUR_TWO_TWO(p)   ((((*WP(p))&0x0000ffff) <<16) | (((*(WP(p)+1))&0xffff0000) >> 16))
-#define MUR_ONE_THREE(p) ((((*WP(p))&0x000000ff) <<24) | (((*(WP(p)+1))&0xffffff00) >>  8))
-#else /* assume little endian non-intel */
-#define MUR_THREE_ONE(p) ((((*WP(p))&0xffffff00) >> 8) | (((*(WP(p)+1))&0x000000ff) << 24))
-#define MUR_TWO_TWO(p)   ((((*WP(p))&0xffff0000) >>16) | (((*(WP(p)+1))&0x0000ffff) << 16))
-#define MUR_ONE_THREE(p) ((((*WP(p))&0xff000000) >>24) | (((*(WP(p)+1))&0x00ffffff) <<  8))
-#endif
-#define MUR_GETBLOCK(p,i) (MUR_PLUS0_ALIGNED(p) ? ((p)[i]) :           \
-                            (MUR_PLUS1_ALIGNED(p) ? MUR_THREE_ONE(p) : \
-                             (MUR_PLUS2_ALIGNED(p) ? MUR_TWO_TWO(p) :  \
-                                                      MUR_ONE_THREE(p))))
-#endif
-#define MUR_ROTL32(x,r) (((x) << (r)) | ((x) >> (32 - (r))))
-#define MUR_FMIX(_h) \
-do {                 \
-  _h ^= _h >> 16;    \
-  _h *= 0x85ebca6b;  \
-  _h ^= _h >> 13;    \
-  _h *= 0xc2b2ae35l; \
-  _h ^= _h >> 16;    \
-} while(0)
-
-#define HASH_MUR(key,keylen,num_bkts,hashv,bkt)                        \
-do {                                                                   \
-  const uint8_t *_mur_data = (const uint8_t*)(key);                    \
-  const int _mur_nblocks = (keylen) / 4;                               \
-  uint32_t _mur_h1 = 0xf88D5353;                                       \
-  uint32_t _mur_c1 = 0xcc9e2d51;                                       \
-  uint32_t _mur_c2 = 0x1b873593;                                       \
-  uint32_t _mur_k1 = 0;                                                \
-  const uint8_t *_mur_tail;                                            \
-  const uint32_t *_mur_blocks = (const uint32_t*)(_mur_data+_mur_nblocks*4); \
-  int _mur_i;                                                          \
-  for(_mur_i = -_mur_nblocks; _mur_i; _mur_i++) {                      \
-    _mur_k1 = MUR_GETBLOCK(_mur_blocks,_mur_i);                        \
-    _mur_k1 *= _mur_c1;                                                \
-    _mur_k1 = MUR_ROTL32(_mur_k1,15);                                  \
-    _mur_k1 *= _mur_c2;                                                \
-                                                                       \
-    _mur_h1 ^= _mur_k1;                                                \
-    _mur_h1 = MUR_ROTL32(_mur_h1,13);                                  \
-    _mur_h1 = _mur_h1*5+0xe6546b64;                                    \
-  }                                                                    \
-  _mur_tail = (const uint8_t*)(_mur_data + _mur_nblocks*4);            \
-  _mur_k1=0;                                                           \
-  switch((keylen) & 3) {                                               \
-    case 3: _mur_k1 ^= _mur_tail[2] << 16;                             \
-    case 2: _mur_k1 ^= _mur_tail[1] << 8;                              \
-    case 1: _mur_k1 ^= _mur_tail[0];                                   \
-    _mur_k1 *= _mur_c1;                                                \
-    _mur_k1 = MUR_ROTL32(_mur_k1,15);                                  \
-    _mur_k1 *= _mur_c2;                                                \
-    _mur_h1 ^= _mur_k1;                                                \
-  }                                                                    \
-  _mur_h1 ^= (keylen);                                                 \
-  MUR_FMIX(_mur_h1);                                                   \
-  hashv = _mur_h1;                                                     \
-  bkt = hashv & (num_bkts-1);                                          \
-} while(0)
-#endif  /* HASH_USING_NO_STRICT_ALIASING */
-
-/* key comparison function; return 0 if keys equal */
-#define HASH_KEYCMP(a,b,len) memcmp(a,b,len)
-
-/* iterate over items in a known bucket to find desired item */
-#define HASH_FIND_IN_BKT(tbl,hh,head,keyptr,keylen_in,out)                       \
-do {                                                                             \
- if (head.hh_head) DECLTYPE_ASSIGN(out,ELMT_FROM_HH(tbl,head.hh_head));          \
- else out=NULL;                                                                  \
- while (out) {                                                                   \
-    if ((out)->hh.keylen == keylen_in) {                                           \
-        if ((HASH_KEYCMP((out)->hh.key,keyptr,keylen_in)) == 0) break;             \
-    }                                                                            \
-    if ((out)->hh.hh_next) DECLTYPE_ASSIGN(out,ELMT_FROM_HH(tbl,(out)->hh.hh_next)); \
-    else out = NULL;                                                             \
- }                                                                               \
-} while(0)
-
-/* add an item to a bucket  */
-#define HASH_ADD_TO_BKT(head,addhh)                                              \
-do {                                                                             \
- head.count++;                                                                   \
- (addhh)->hh_next = head.hh_head;                                                \
- (addhh)->hh_prev = NULL;                                                        \
- if (head.hh_head) { (head).hh_head->hh_prev = (addhh); }                        \
- (head).hh_head=addhh;                                                           \
- if (head.count >= ((head.expand_mult+1) * HASH_BKT_CAPACITY_THRESH)             \
-     && (addhh)->tbl->noexpand != 1) {                                           \
-       HASH_EXPAND_BUCKETS((addhh)->tbl);                                        \
- }                                                                               \
-} while(0)
-
-/* remove an item from a given bucket */
-#define HASH_DEL_IN_BKT(hh,head,hh_del)                                          \
-    (head).count--;                                                              \
-    if ((head).hh_head == hh_del) {                                              \
-      (head).hh_head = hh_del->hh_next;                                          \
-    }                                                                            \
-    if (hh_del->hh_prev) {                                                       \
-        hh_del->hh_prev->hh_next = hh_del->hh_next;                              \
-    }                                                                            \
-    if (hh_del->hh_next) {                                                       \
-        hh_del->hh_next->hh_prev = hh_del->hh_prev;                              \
-    }
-
-/* Bucket expansion has the effect of doubling the number of buckets
- * and redistributing the items into the new buckets. Ideally the
- * items will distribute more or less evenly into the new buckets
- * (the extent to which this is true is a measure of the quality of
- * the hash function as it applies to the key domain).
- *
- * With the items distributed into more buckets, the chain length
- * (item count) in each bucket is reduced. Thus by expanding buckets
- * the hash keeps a bound on the chain length. This bounded chain
- * length is the essence of how a hash provides constant time lookup.
- *
- * The calculation of tbl->ideal_chain_maxlen below deserves some
- * explanation. First, keep in mind that we're calculating the ideal
- * maximum chain length based on the *new* (doubled) bucket count.
- * In fractions this is just n/b (n=number of items,b=new num buckets).
- * Since the ideal chain length is an integer, we want to calculate
- * ceil(n/b). We don't depend on floating point arithmetic in this
- * hash, so to calculate ceil(n/b) with integers we could write
- *
- *      ceil(n/b) = (n/b) + ((n%b)?1:0)
- *
- * and in fact a previous version of this hash did just that.
- * But now we have improved things a bit by recognizing that b is
- * always a power of two. We keep its base 2 log handy (call it lb),
- * so now we can write this with a bit shift and logical AND:
- *
- *      ceil(n/b) = (n>>lb) + ( (n & (b-1)) ? 1:0)
- *
- */
-#define HASH_EXPAND_BUCKETS(tbl)                                                 \
-do {                                                                             \
-    unsigned _he_bkt;                                                            \
-    unsigned _he_bkt_i;                                                          \
-    struct UT_hash_handle *_he_thh, *_he_hh_nxt;                                 \
-    UT_hash_bucket *_he_new_buckets, *_he_newbkt;                                \
-    _he_new_buckets = (UT_hash_bucket*)uthash_malloc(                            \
-             2 * tbl->num_buckets * sizeof(struct UT_hash_bucket));              \
-    if (!_he_new_buckets) { uthash_fatal( "out of memory"); }                    \
-    memset(_he_new_buckets, 0,                                                   \
-            2 * tbl->num_buckets * sizeof(struct UT_hash_bucket));               \
-    tbl->ideal_chain_maxlen =                                                    \
-       (tbl->num_items >> (tbl->log2_num_buckets+1)) +                           \
-       ((tbl->num_items & ((tbl->num_buckets*2)-1)) ? 1 : 0);                    \
-    tbl->nonideal_items = 0;                                                     \
-    for(_he_bkt_i = 0; _he_bkt_i < tbl->num_buckets; _he_bkt_i++)                \
-    {                                                                            \
-        _he_thh = tbl->buckets[ _he_bkt_i ].hh_head;                             \
-        while (_he_thh) {                                                        \
-           _he_hh_nxt = _he_thh->hh_next;                                        \
-           HASH_TO_BKT( _he_thh->hashv, tbl->num_buckets*2, _he_bkt);            \
-           _he_newbkt = &(_he_new_buckets[ _he_bkt ]);                           \
-           if (++(_he_newbkt->count) > tbl->ideal_chain_maxlen) {                \
-             tbl->nonideal_items++;                                              \
-             _he_newbkt->expand_mult = _he_newbkt->count /                       \
-                                        tbl->ideal_chain_maxlen;                 \
-           }                                                                     \
-           _he_thh->hh_prev = NULL;                                              \
-           _he_thh->hh_next = _he_newbkt->hh_head;                               \
-           if (_he_newbkt->hh_head) _he_newbkt->hh_head->hh_prev =               \
-                _he_thh;                                                         \
-           _he_newbkt->hh_head = _he_thh;                                        \
-           _he_thh = _he_hh_nxt;                                                 \
-        }                                                                        \
-    }                                                                            \
-    uthash_free( tbl->buckets, tbl->num_buckets*sizeof(struct UT_hash_bucket) ); \
-    tbl->num_buckets *= 2;                                                       \
-    tbl->log2_num_buckets++;                                                     \
-    tbl->buckets = _he_new_buckets;                                              \
-    tbl->ineff_expands = (tbl->nonideal_items > (tbl->num_items >> 1)) ?         \
-        (tbl->ineff_expands+1) : 0;                                              \
-    if (tbl->ineff_expands > 1) {                                                \
-        tbl->noexpand=1;                                                         \
-        uthash_noexpand_fyi(tbl);                                                \
-    }                                                                            \
-    uthash_expand_fyi(tbl);                                                      \
-} while(0)
-
-
-/* This is an adaptation of Simon Tatham's O(n log(n)) mergesort */
-/* Note that HASH_SORT assumes the hash handle name to be hh.
- * HASH_SRT was added to allow the hash handle name to be passed in. */
-#define HASH_SORT(head,cmpfcn) HASH_SRT(hh,head,cmpfcn)
-#define HASH_SRT(hh,head,cmpfcn)                                                 \
-do {                                                                             \
-  unsigned _hs_i;                                                                \
-  unsigned _hs_looping,_hs_nmerges,_hs_insize,_hs_psize,_hs_qsize;               \
-  struct UT_hash_handle *_hs_p, *_hs_q, *_hs_e, *_hs_list, *_hs_tail;            \
-  if (head) {                                                                    \
-      _hs_insize = 1;                                                            \
-      _hs_looping = 1;                                                           \
-      _hs_list = &((head)->hh);                                                  \
-      while (_hs_looping) {                                                      \
-          _hs_p = _hs_list;                                                      \
-          _hs_list = NULL;                                                       \
-          _hs_tail = NULL;                                                       \
-          _hs_nmerges = 0;                                                       \
-          while (_hs_p) {                                                        \
-              _hs_nmerges++;                                                     \
-              _hs_q = _hs_p;                                                     \
-              _hs_psize = 0;                                                     \
-              for ( _hs_i = 0; _hs_i  < _hs_insize; _hs_i++ ) {                  \
-                  _hs_psize++;                                                   \
-                  _hs_q = (UT_hash_handle*)((_hs_q->next) ?                      \
-                          ((void*)((char*)(_hs_q->next) +                        \
-                          (head)->hh.tbl->hho)) : NULL);                         \
-                  if (! (_hs_q) ) break;                                         \
-              }                                                                  \
-              _hs_qsize = _hs_insize;                                            \
-              while ((_hs_psize > 0) || ((_hs_qsize > 0) && _hs_q )) {           \
-                  if (_hs_psize == 0) {                                          \
-                      _hs_e = _hs_q;                                             \
-                      _hs_q = (UT_hash_handle*)((_hs_q->next) ?                  \
-                              ((void*)((char*)(_hs_q->next) +                    \
-                              (head)->hh.tbl->hho)) : NULL);                     \
-                      _hs_qsize--;                                               \
-                  } else if ( (_hs_qsize == 0) || !(_hs_q) ) {                   \
-                      _hs_e = _hs_p;                                             \
-                      if (_hs_p){                                                \
-                        _hs_p = (UT_hash_handle*)((_hs_p->next) ?                \
-                                ((void*)((char*)(_hs_p->next) +                  \
-                                (head)->hh.tbl->hho)) : NULL);                   \
-                       }                                                         \
-                      _hs_psize--;                                               \
-                  } else if ((                                                   \
-                      cmpfcn(DECLTYPE(head)(ELMT_FROM_HH((head)->hh.tbl,_hs_p)), \
-                             DECLTYPE(head)(ELMT_FROM_HH((head)->hh.tbl,_hs_q))) \
-                             ) <= 0) {                                           \
-                      _hs_e = _hs_p;                                             \
-                      if (_hs_p){                                                \
-                        _hs_p = (UT_hash_handle*)((_hs_p->next) ?                \
-                               ((void*)((char*)(_hs_p->next) +                   \
-                               (head)->hh.tbl->hho)) : NULL);                    \
-                       }                                                         \
-                      _hs_psize--;                                               \
-                  } else {                                                       \
-                      _hs_e = _hs_q;                                             \
-                      _hs_q = (UT_hash_handle*)((_hs_q->next) ?                  \
-                              ((void*)((char*)(_hs_q->next) +                    \
-                              (head)->hh.tbl->hho)) : NULL);                     \
-                      _hs_qsize--;                                               \
-                  }                                                              \
-                  if ( _hs_tail ) {                                              \
-                      _hs_tail->next = ((_hs_e) ?                                \
-                            ELMT_FROM_HH((head)->hh.tbl,_hs_e) : NULL);          \
-                  } else {                                                       \
-                      _hs_list = _hs_e;                                          \
-                  }                                                              \
-                  if (_hs_e) {                                                   \
-                  _hs_e->prev = ((_hs_tail) ?                                    \
-                     ELMT_FROM_HH((head)->hh.tbl,_hs_tail) : NULL);              \
-                  }                                                              \
-                  _hs_tail = _hs_e;                                              \
-              }                                                                  \
-              _hs_p = _hs_q;                                                     \
-          }                                                                      \
-          if (_hs_tail){                                                         \
-            _hs_tail->next = NULL;                                               \
-          }                                                                      \
-          if ( _hs_nmerges <= 1 ) {                                              \
-              _hs_looping=0;                                                     \
-              (head)->hh.tbl->tail = _hs_tail;                                   \
-              DECLTYPE_ASSIGN(head,ELMT_FROM_HH((head)->hh.tbl, _hs_list));      \
-          }                                                                      \
-          _hs_insize *= 2;                                                       \
-      }                                                                          \
-      HASH_FSCK(hh,head);                                                        \
- }                                                                               \
-} while (0)
-
-/* This function selects items from one hash into another hash.
- * The end result is that the selected items have dual presence
- * in both hashes. There is no copy of the items made; rather
- * they are added into the new hash through a secondary hash
- * hash handle that must be present in the structure. */
-#define HASH_SELECT(hh_dst, dst, hh_src, src, cond)                              \
-do {                                                                             \
-  unsigned _src_bkt, _dst_bkt;                                                   \
-  void *_last_elt=NULL, *_elt;                                                   \
-  UT_hash_handle *_src_hh, *_dst_hh, *_last_elt_hh=NULL;                         \
-  ptrdiff_t _dst_hho = ((char*)(&(dst)->hh_dst) - (char*)(dst));                 \
-  if (src) {                                                                     \
-    for(_src_bkt=0; _src_bkt < (src)->hh_src.tbl->num_buckets; _src_bkt++) {     \
-      for(_src_hh = (src)->hh_src.tbl->buckets[_src_bkt].hh_head;                \
-          _src_hh;                                                               \
-          _src_hh = _src_hh->hh_next) {                                          \
-          _elt = ELMT_FROM_HH((src)->hh_src.tbl, _src_hh);                       \
-          if (cond(_elt)) {                                                      \
-            _dst_hh = (UT_hash_handle*)(((char*)_elt) + _dst_hho);               \
-            _dst_hh->key = _src_hh->key;                                         \
-            _dst_hh->keylen = _src_hh->keylen;                                   \
-            _dst_hh->hashv = _src_hh->hashv;                                     \
-            _dst_hh->prev = _last_elt;                                           \
-            _dst_hh->next = NULL;                                                \
-            if (_last_elt_hh) { _last_elt_hh->next = _elt; }                     \
-            if (!dst) {                                                          \
-              DECLTYPE_ASSIGN(dst,_elt);                                         \
-              HASH_MAKE_TABLE(hh_dst,dst);                                       \
-            } else {                                                             \
-              _dst_hh->tbl = (dst)->hh_dst.tbl;                                  \
-            }                                                                    \
-            HASH_TO_BKT(_dst_hh->hashv, _dst_hh->tbl->num_buckets, _dst_bkt);    \
-            HASH_ADD_TO_BKT(_dst_hh->tbl->buckets[_dst_bkt],_dst_hh);            \
-            (dst)->hh_dst.tbl->num_items++;                                      \
-            _last_elt = _elt;                                                    \
-            _last_elt_hh = _dst_hh;                                              \
-          }                                                                      \
-      }                                                                          \
-    }                                                                            \
-  }                                                                              \
-  HASH_FSCK(hh_dst,dst);                                                         \
-} while (0)
-
-#define HASH_CLEAR(hh,head)                                                      \
-do {                                                                             \
-  if (head) {                                                                    \
-    uthash_free((head)->hh.tbl->buckets,                                         \
-                (head)->hh.tbl->num_buckets*sizeof(struct UT_hash_bucket));      \
-    HASH_BLOOM_FREE((head)->hh.tbl);                                             \
-    uthash_free((head)->hh.tbl, sizeof(UT_hash_table));                          \
-    (head)=NULL;                                                                 \
-  }                                                                              \
-} while(0)
-
-#define HASH_OVERHEAD(hh,head)                                                   \
- ((head) ? (                                                                     \
- (size_t)((((head)->hh.tbl->num_items   * sizeof(UT_hash_handle))   +            \
-           ((head)->hh.tbl->num_buckets * sizeof(UT_hash_bucket))   +            \
-            (sizeof(UT_hash_table))                                 +            \
-            (HASH_BLOOM_BYTELEN)))) : 0)
-
-#ifdef NO_DECLTYPE
-#define HASH_ITER(hh,head,el,tmp)                                                \
-for((el)=(head), (*(char**)(&(tmp)))=(char*)((head)?(head)->hh.next:NULL);       \
-  el; (el)=(tmp),(*(char**)(&(tmp)))=(char*)((tmp)?(tmp)->hh.next:NULL))
-#else
-#define HASH_ITER(hh,head,el,tmp)                                                \
-for((el)=(head),(tmp)=DECLTYPE(el)((head)?(head)->hh.next:NULL);                 \
-  el; (el)=(tmp),(tmp)=DECLTYPE(el)((tmp)?(tmp)->hh.next:NULL))
-#endif
-
-/* obtain a count of items in the hash */
-#define HASH_COUNT(head) HASH_CNT(hh,head)
-#define HASH_CNT(hh,head) ((head)?((head)->hh.tbl->num_items):0)
-
-typedef struct UT_hash_bucket {
-   struct UT_hash_handle *hh_head;
-   unsigned count;
-
-   /* expand_mult is normally set to 0. In this situation, the max chain length
-    * threshold is enforced at its default value, HASH_BKT_CAPACITY_THRESH. (If
-    * the bucket's chain exceeds this length, bucket expansion is triggered).
-    * However, setting expand_mult to a non-zero value delays bucket expansion
-    * (that would be triggered by additions to this particular bucket)
-    * until its chain length reaches a *multiple* of HASH_BKT_CAPACITY_THRESH.
-    * (The multiplier is simply expand_mult+1). The whole idea of this
-    * multiplier is to reduce bucket expansions, since they are expensive, in
-    * situations where we know that a particular bucket tends to be overused.
-    * It is better to let its chain length grow to a longer yet-still-bounded
-    * value, than to do an O(n) bucket expansion too often.
-    */
-   unsigned expand_mult;
-
-} UT_hash_bucket;
-
-/* random signature used only to find hash tables in external analysis */
-#define HASH_SIGNATURE 0xa0111fe1
-#define HASH_BLOOM_SIGNATURE 0xb12220f2
-
-typedef struct UT_hash_table {
-   UT_hash_bucket *buckets;
-   unsigned num_buckets, log2_num_buckets;
-   unsigned num_items;
-   struct UT_hash_handle *tail; /* tail hh in app order, for fast append    */
-   ptrdiff_t hho; /* hash handle offset (byte pos of hash handle in element */
-
-   /* in an ideal situation (all buckets used equally), no bucket would have
-    * more than ceil(#items/#buckets) items. that's the ideal chain length. */
-   unsigned ideal_chain_maxlen;
-
-   /* nonideal_items is the number of items in the hash whose chain position
-    * exceeds the ideal chain maxlen. these items pay the penalty for an uneven
-    * hash distribution; reaching them in a chain traversal takes >ideal steps */
-   unsigned nonideal_items;
-
-   /* ineffective expands occur when a bucket doubling was performed, but
-    * afterward, more than half the items in the hash had nonideal chain
-    * positions. If this happens on two consecutive expansions we inhibit any
-    * further expansion, as it's not helping; this happens when the hash
-    * function isn't a good fit for the key domain. When expansion is inhibited
-    * the hash will still work, albeit no longer in constant time. */
-   unsigned ineff_expands, noexpand;
-
-   uint32_t signature; /* used only to find hash tables in external analysis */
-#ifdef HASH_BLOOM
-   uint32_t bloom_sig; /* used only to test bloom exists in external analysis */
-   uint8_t *bloom_bv;
-   char bloom_nbits;
-#endif
-
-} UT_hash_table;
-
-typedef struct UT_hash_handle {
-   struct UT_hash_table *tbl;
-   void *prev;                       /* prev element in app order      */
-   void *next;                       /* next element in app order      */
-   struct UT_hash_handle *hh_prev;   /* previous hh in bucket order    */
-   struct UT_hash_handle *hh_next;   /* next hh in bucket order        */
-   void *key;                        /* ptr to enclosing struct's key  */
-   unsigned keylen;                  /* enclosing struct's key len     */
-   unsigned hashv;                   /* result of hash-fcn(key)        */
-} UT_hash_handle;
-
-#endif /* UTHASH_H */
diff --git a/tools/sdk/include/coap/utlist.h b/tools/sdk/include/coap/utlist.h
deleted file mode 100644
index b5f3f04c104..00000000000
--- a/tools/sdk/include/coap/utlist.h
+++ /dev/null
@@ -1,757 +0,0 @@
-/*
-Copyright (c) 2007-2014, Troy D. Hanson   http://troydhanson.github.com/uthash/
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-    * Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
-OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#ifndef UTLIST_H
-#define UTLIST_H
-
-#define UTLIST_VERSION 1.9.9
-
-#include <assert.h>
-
-/*
- * This file contains macros to manipulate singly and doubly-linked lists.
- *
- * 1. LL_ macros:  singly-linked lists.
- * 2. DL_ macros:  doubly-linked lists.
- * 3. CDL_ macros: circular doubly-linked lists.
- *
- * To use singly-linked lists, your structure must have a "next" pointer.
- * To use doubly-linked lists, your structure must "prev" and "next" pointers.
- * Either way, the pointer to the head of the list must be initialized to NULL.
- *
- * ----------------.EXAMPLE -------------------------
- * struct item {
- *      int id;
- *      struct item *prev, *next;
- * }
- *
- * struct item *list = NULL:
- *
- * int main() {
- *      struct item *item;
- *      ... allocate and populate item ...
- *      DL_APPEND(list, item);
- * }
- * --------------------------------------------------
- *
- * For doubly-linked lists, the append and delete macros are O(1)
- * For singly-linked lists, append and delete are O(n) but prepend is O(1)
- * The sort macro is O(n log(n)) for all types of single/double/circular lists.
- */
-
-/* These macros use decltype or the earlier __typeof GNU extension.
-   As decltype is only available in newer compilers (VS2010 or gcc 4.3+
-   when compiling c++ code), this code uses whatever method is needed
-   or, for VS2008 where neither is available, uses casting workarounds. */
-#ifdef _MSC_VER            /* MS compiler */
-#if _MSC_VER >= 1600 && defined(__cplusplus)  /* VS2010 or newer in C++ mode */
-#define LDECLTYPE(x) decltype(x)
-#else                     /* VS2008 or older (or VS2010 in C mode) */
-#define NO_DECLTYPE
-#define LDECLTYPE(x) char*
-#endif
-#elif defined(__ICCARM__)
-#define NO_DECLTYPE
-#define LDECLTYPE(x) char*
-#else                      /* GNU, Sun and other compilers */
-#define LDECLTYPE(x) __typeof(x)
-#endif
-
-/* for VS2008 we use some workarounds to get around the lack of decltype,
- * namely, we always reassign our tmp variable to the list head if we need
- * to dereference its prev/next pointers, and save/restore the real head.*/
-#ifdef NO_DECLTYPE
-#define _SV(elt,list) _tmp = (char*)(list); {char **_alias = (char**)&(list); *_alias = (elt); }
-#define _NEXT(elt,list,next) ((char*)((list)->next))
-#define _NEXTASGN(elt,list,to,next) { char **_alias = (char**)&((list)->next); *_alias=(char*)(to); }
-/* #define _PREV(elt,list,prev) ((char*)((list)->prev)) */
-#define _PREVASGN(elt,list,to,prev) { char **_alias = (char**)&((list)->prev); *_alias=(char*)(to); }
-#define _RS(list) { char **_alias = (char**)&(list); *_alias=_tmp; }
-#define _CASTASGN(a,b) { char **_alias = (char**)&(a); *_alias=(char*)(b); }
-#else
-#define _SV(elt,list)
-#define _NEXT(elt,list,next) ((elt)->next)
-#define _NEXTASGN(elt,list,to,next) ((elt)->next)=(to)
-/* #define _PREV(elt,list,prev) ((elt)->prev) */
-#define _PREVASGN(elt,list,to,prev) ((elt)->prev)=(to)
-#define _RS(list)
-#define _CASTASGN(a,b) (a)=(b)
-#endif
-
-/******************************************************************************
- * The sort macro is an adaptation of Simon Tatham's O(n log(n)) mergesort    *
- * Unwieldy variable names used here to avoid shadowing passed-in variables.  *
- *****************************************************************************/
-#define LL_SORT(list, cmp)                                                                     \
-    LL_SORT2(list, cmp, next)
-
-#define LL_SORT2(list, cmp, next)                                                              \
-do {                                                                                           \
-  LDECLTYPE(list) _ls_p;                                                                       \
-  LDECLTYPE(list) _ls_q;                                                                       \
-  LDECLTYPE(list) _ls_e;                                                                       \
-  LDECLTYPE(list) _ls_tail;                                                                    \
-  int _ls_insize, _ls_nmerges, _ls_psize, _ls_qsize, _ls_i, _ls_looping;                       \
-  if (list) {                                                                                  \
-    _ls_insize = 1;                                                                            \
-    _ls_looping = 1;                                                                           \
-    while (_ls_looping) {                                                                      \
-      _CASTASGN(_ls_p,list);                                                                   \
-      list = NULL;                                                                             \
-      _ls_tail = NULL;                                                                         \
-      _ls_nmerges = 0;                                                                         \
-      while (_ls_p) {                                                                          \
-        _ls_nmerges++;                                                                         \
-        _ls_q = _ls_p;                                                                         \
-        _ls_psize = 0;                                                                         \
-        for (_ls_i = 0; _ls_i < _ls_insize; _ls_i++) {                                         \
-          _ls_psize++;                                                                         \
-          _SV(_ls_q,list); _ls_q = _NEXT(_ls_q,list,next); _RS(list);                          \
-          if (!_ls_q) break;                                                                   \
-        }                                                                                      \
-        _ls_qsize = _ls_insize;                                                                \
-        while (_ls_psize > 0 || (_ls_qsize > 0 && _ls_q)) {                                    \
-          if (_ls_psize == 0) {                                                                \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-          } else if (_ls_qsize == 0 || !_ls_q) {                                               \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-          } else if (cmp(_ls_p,_ls_q) <= 0) {                                                  \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-          } else {                                                                             \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-          }                                                                                    \
-          if (_ls_tail) {                                                                      \
-            _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,_ls_e,next); _RS(list);                \
-          } else {                                                                             \
-            _CASTASGN(list,_ls_e);                                                             \
-          }                                                                                    \
-          _ls_tail = _ls_e;                                                                    \
-        }                                                                                      \
-        _ls_p = _ls_q;                                                                         \
-      }                                                                                        \
-      if (_ls_tail) {                                                                          \
-        _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,NULL,next); _RS(list);                     \
-      }                                                                                        \
-      if (_ls_nmerges <= 1) {                                                                  \
-        _ls_looping=0;                                                                         \
-      }                                                                                        \
-      _ls_insize *= 2;                                                                         \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-
-#define DL_SORT(list, cmp)                                                                     \
-    DL_SORT2(list, cmp, prev, next)
-
-#define DL_SORT2(list, cmp, prev, next)                                                        \
-do {                                                                                           \
-  LDECLTYPE(list) _ls_p;                                                                       \
-  LDECLTYPE(list) _ls_q;                                                                       \
-  LDECLTYPE(list) _ls_e;                                                                       \
-  LDECLTYPE(list) _ls_tail;                                                                    \
-  int _ls_insize, _ls_nmerges, _ls_psize, _ls_qsize, _ls_i, _ls_looping;                       \
-  if (list) {                                                                                  \
-    _ls_insize = 1;                                                                            \
-    _ls_looping = 1;                                                                           \
-    while (_ls_looping) {                                                                      \
-      _CASTASGN(_ls_p,list);                                                                   \
-      list = NULL;                                                                             \
-      _ls_tail = NULL;                                                                         \
-      _ls_nmerges = 0;                                                                         \
-      while (_ls_p) {                                                                          \
-        _ls_nmerges++;                                                                         \
-        _ls_q = _ls_p;                                                                         \
-        _ls_psize = 0;                                                                         \
-        for (_ls_i = 0; _ls_i < _ls_insize; _ls_i++) {                                         \
-          _ls_psize++;                                                                         \
-          _SV(_ls_q,list); _ls_q = _NEXT(_ls_q,list,next); _RS(list);                          \
-          if (!_ls_q) break;                                                                   \
-        }                                                                                      \
-        _ls_qsize = _ls_insize;                                                                \
-        while (_ls_psize > 0 || (_ls_qsize > 0 && _ls_q)) {                                    \
-          if (_ls_psize == 0) {                                                                \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-          } else if (_ls_qsize == 0 || !_ls_q) {                                               \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-          } else if (cmp(_ls_p,_ls_q) <= 0) {                                                  \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-          } else {                                                                             \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-          }                                                                                    \
-          if (_ls_tail) {                                                                      \
-            _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,_ls_e,next); _RS(list);                \
-          } else {                                                                             \
-            _CASTASGN(list,_ls_e);                                                             \
-          }                                                                                    \
-          _SV(_ls_e,list); _PREVASGN(_ls_e,list,_ls_tail,prev); _RS(list);                     \
-          _ls_tail = _ls_e;                                                                    \
-        }                                                                                      \
-        _ls_p = _ls_q;                                                                         \
-      }                                                                                        \
-      _CASTASGN(list->prev, _ls_tail);                                                         \
-      _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,NULL,next); _RS(list);                       \
-      if (_ls_nmerges <= 1) {                                                                  \
-        _ls_looping=0;                                                                         \
-      }                                                                                        \
-      _ls_insize *= 2;                                                                         \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-#define CDL_SORT(list, cmp)                                                                    \
-    CDL_SORT2(list, cmp, prev, next)
-
-#define CDL_SORT2(list, cmp, prev, next)                                                       \
-do {                                                                                           \
-  LDECLTYPE(list) _ls_p;                                                                       \
-  LDECLTYPE(list) _ls_q;                                                                       \
-  LDECLTYPE(list) _ls_e;                                                                       \
-  LDECLTYPE(list) _ls_tail;                                                                    \
-  LDECLTYPE(list) _ls_oldhead;                                                                 \
-  LDECLTYPE(list) _tmp;                                                                        \
-  int _ls_insize, _ls_nmerges, _ls_psize, _ls_qsize, _ls_i, _ls_looping;                       \
-  if (list) {                                                                                  \
-    _ls_insize = 1;                                                                            \
-    _ls_looping = 1;                                                                           \
-    while (_ls_looping) {                                                                      \
-      _CASTASGN(_ls_p,list);                                                                   \
-      _CASTASGN(_ls_oldhead,list);                                                             \
-      list = NULL;                                                                             \
-      _ls_tail = NULL;                                                                         \
-      _ls_nmerges = 0;                                                                         \
-      while (_ls_p) {                                                                          \
-        _ls_nmerges++;                                                                         \
-        _ls_q = _ls_p;                                                                         \
-        _ls_psize = 0;                                                                         \
-        for (_ls_i = 0; _ls_i < _ls_insize; _ls_i++) {                                         \
-          _ls_psize++;                                                                         \
-          _SV(_ls_q,list);                                                                     \
-          if (_NEXT(_ls_q,list,next) == _ls_oldhead) {                                         \
-            _ls_q = NULL;                                                                      \
-          } else {                                                                             \
-            _ls_q = _NEXT(_ls_q,list,next);                                                    \
-          }                                                                                    \
-          _RS(list);                                                                           \
-          if (!_ls_q) break;                                                                   \
-        }                                                                                      \
-        _ls_qsize = _ls_insize;                                                                \
-        while (_ls_psize > 0 || (_ls_qsize > 0 && _ls_q)) {                                    \
-          if (_ls_psize == 0) {                                                                \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-            if (_ls_q == _ls_oldhead) { _ls_q = NULL; }                                        \
-          } else if (_ls_qsize == 0 || !_ls_q) {                                               \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-            if (_ls_p == _ls_oldhead) { _ls_p = NULL; }                                        \
-          } else if (cmp(_ls_p,_ls_q) <= 0) {                                                  \
-            _ls_e = _ls_p; _SV(_ls_p,list); _ls_p =                                            \
-              _NEXT(_ls_p,list,next); _RS(list); _ls_psize--;                                  \
-            if (_ls_p == _ls_oldhead) { _ls_p = NULL; }                                        \
-          } else {                                                                             \
-            _ls_e = _ls_q; _SV(_ls_q,list); _ls_q =                                            \
-              _NEXT(_ls_q,list,next); _RS(list); _ls_qsize--;                                  \
-            if (_ls_q == _ls_oldhead) { _ls_q = NULL; }                                        \
-          }                                                                                    \
-          if (_ls_tail) {                                                                      \
-            _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,_ls_e,next); _RS(list);                \
-          } else {                                                                             \
-            _CASTASGN(list,_ls_e);                                                             \
-          }                                                                                    \
-          _SV(_ls_e,list); _PREVASGN(_ls_e,list,_ls_tail,prev); _RS(list);                     \
-          _ls_tail = _ls_e;                                                                    \
-        }                                                                                      \
-        _ls_p = _ls_q;                                                                         \
-      }                                                                                        \
-      _CASTASGN(list->prev,_ls_tail);                                                          \
-      _CASTASGN(_tmp,list);                                                                    \
-      _SV(_ls_tail,list); _NEXTASGN(_ls_tail,list,_tmp,next); _RS(list);                       \
-      if (_ls_nmerges <= 1) {                                                                  \
-        _ls_looping=0;                                                                         \
-      }                                                                                        \
-      _ls_insize *= 2;                                                                         \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-/******************************************************************************
- * singly linked list macros (non-circular)                                   *
- *****************************************************************************/
-#define LL_PREPEND(head,add)                                                                   \
-    LL_PREPEND2(head,add,next)
-
-#define LL_PREPEND2(head,add,next)                                                             \
-do {                                                                                           \
-  (add)->next = head;                                                                          \
-  head = add;                                                                                  \
-} while (0)
-
-#define LL_CONCAT(head1,head2)                                                                 \
-    LL_CONCAT2(head1,head2,next)
-
-#define LL_CONCAT2(head1,head2,next)                                                           \
-do {                                                                                           \
-  LDECLTYPE(head1) _tmp;                                                                       \
-  if (head1) {                                                                                 \
-    _tmp = head1;                                                                              \
-    while (_tmp->next) { _tmp = _tmp->next; }                                                  \
-    _tmp->next=(head2);                                                                        \
-  } else {                                                                                     \
-    (head1)=(head2);                                                                           \
-  }                                                                                            \
-} while (0)
-
-#define LL_APPEND(head,add)                                                                    \
-    LL_APPEND2(head,add,next)
-
-#define LL_APPEND2(head,add,next)                                                              \
-do {                                                                                           \
-  LDECLTYPE(head) _tmp;                                                                        \
-  (add)->next=NULL;                                                                            \
-  if (head) {                                                                                  \
-    _tmp = head;                                                                               \
-    while (_tmp->next) { _tmp = _tmp->next; }                                                  \
-    _tmp->next=(add);                                                                          \
-  } else {                                                                                     \
-    (head)=(add);                                                                              \
-  }                                                                                            \
-} while (0)
-
-#define LL_DELETE(head,del)                                                                    \
-    LL_DELETE2(head,del,next)
-
-#define LL_DELETE2(head,del,next)                                                              \
-do {                                                                                           \
-  LDECLTYPE(head) _tmp;                                                                        \
-  if ((head) == (del)) {                                                                       \
-    (head)=(head)->next;                                                                       \
-  } else {                                                                                     \
-    _tmp = head;                                                                               \
-    while (_tmp->next && (_tmp->next != (del))) {                                              \
-      _tmp = _tmp->next;                                                                       \
-    }                                                                                          \
-    if (_tmp->next) {                                                                          \
-      _tmp->next = ((del)->next);                                                              \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-/* Here are VS2008 replacements for LL_APPEND and LL_DELETE */
-#define LL_APPEND_VS2008(head,add)                                                             \
-    LL_APPEND2_VS2008(head,add,next)
-
-#define LL_APPEND2_VS2008(head,add,next)                                                       \
-do {                                                                                           \
-  if (head) {                                                                                  \
-    (add)->next = head;     /* use add->next as a temp variable */                             \
-    while ((add)->next->next) { (add)->next = (add)->next->next; }                             \
-    (add)->next->next=(add);                                                                   \
-  } else {                                                                                     \
-    (head)=(add);                                                                              \
-  }                                                                                            \
-  (add)->next=NULL;                                                                            \
-} while (0)
-
-#define LL_DELETE_VS2008(head,del)                                                             \
-    LL_DELETE2_VS2008(head,del,next)
-
-#define LL_DELETE2_VS2008(head,del,next)                                                       \
-do {                                                                                           \
-  if ((head) == (del)) {                                                                       \
-    (head)=(head)->next;                                                                       \
-  } else {                                                                                     \
-    char *_tmp = (char*)(head);                                                                \
-    while ((head)->next && ((head)->next != (del))) {                                          \
-      head = (head)->next;                                                                     \
-    }                                                                                          \
-    if ((head)->next) {                                                                        \
-      (head)->next = ((del)->next);                                                            \
-    }                                                                                          \
-    {                                                                                          \
-      char **_head_alias = (char**)&(head);                                                    \
-      *_head_alias = _tmp;                                                                     \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-#ifdef NO_DECLTYPE
-#undef LL_APPEND
-#define LL_APPEND LL_APPEND_VS2008
-#undef LL_DELETE
-#define LL_DELETE LL_DELETE_VS2008
-#undef LL_DELETE2
-#define LL_DELETE2 LL_DELETE2_VS2008
-#undef LL_APPEND2
-#define LL_APPEND2 LL_APPEND2_VS2008
-#undef LL_CONCAT /* no LL_CONCAT_VS2008 */
-#undef DL_CONCAT /* no DL_CONCAT_VS2008 */
-#endif
-/* end VS2008 replacements */
-
-#define LL_COUNT(head,el,counter)                                                              \
-    LL_COUNT2(head,el,counter,next)                                                            \
-
-#define LL_COUNT2(head,el,counter,next)                                                        \
-{                                                                                              \
-    counter = 0;                                                                               \
-    LL_FOREACH2(head,el,next){ ++counter; }                                                    \
-}
-
-#define LL_FOREACH(head,el)                                                                    \
-    LL_FOREACH2(head,el,next)
-
-#define LL_FOREACH2(head,el,next)                                                              \
-    for(el=head;el;el=(el)->next)
-
-#define LL_FOREACH_SAFE(head,el,tmp)                                                           \
-    LL_FOREACH_SAFE2(head,el,tmp,next)
-
-#define LL_FOREACH_SAFE2(head,el,tmp,next)                                                     \
-  for((el)=(head);(el) && (tmp = (el)->next, 1); (el) = tmp)
-
-#define LL_SEARCH_SCALAR(head,out,field,val)                                                   \
-    LL_SEARCH_SCALAR2(head,out,field,val,next)
-
-#define LL_SEARCH_SCALAR2(head,out,field,val,next)                                             \
-do {                                                                                           \
-    LL_FOREACH2(head,out,next) {                                                               \
-      if ((out)->field == (val)) break;                                                        \
-    }                                                                                          \
-} while(0)
-
-#define LL_SEARCH(head,out,elt,cmp)                                                            \
-    LL_SEARCH2(head,out,elt,cmp,next)
-
-#define LL_SEARCH2(head,out,elt,cmp,next)                                                      \
-do {                                                                                           \
-    LL_FOREACH2(head,out,next) {                                                               \
-      if ((cmp(out,elt))==0) break;                                                            \
-    }                                                                                          \
-} while(0)
-
-#define LL_REPLACE_ELEM(head, el, add)                                                         \
-do {                                                                                           \
- LDECLTYPE(head) _tmp;                                                                         \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- (add)->next = (el)->next;                                                                     \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
- } else {                                                                                      \
-  _tmp = head;                                                                                 \
-  while (_tmp->next && (_tmp->next != (el))) {                                                 \
-   _tmp = _tmp->next;                                                                          \
-  }                                                                                            \
-  if (_tmp->next) {                                                                            \
-    _tmp->next = (add);                                                                        \
-  }                                                                                            \
- }                                                                                             \
-} while (0)
-
-#define LL_PREPEND_ELEM(head, el, add)                                                         \
-do {                                                                                           \
- LDECLTYPE(head) _tmp;                                                                         \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- (add)->next = (el);                                                                           \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
- } else {                                                                                      \
-  _tmp = head;                                                                                 \
-  while (_tmp->next && (_tmp->next != (el))) {                                                 \
-   _tmp = _tmp->next;                                                                          \
-  }                                                                                            \
-  if (_tmp->next) {                                                                            \
-    _tmp->next = (add);                                                                        \
-  }                                                                                            \
- }                                                                                             \
-} while (0)                                                                                    \
-
-
-/******************************************************************************
- * doubly linked list macros (non-circular)                                   *
- *****************************************************************************/
-#define DL_PREPEND(head,add)                                                                   \
-    DL_PREPEND2(head,add,prev,next)
-
-#define DL_PREPEND2(head,add,prev,next)                                                        \
-do {                                                                                           \
- (add)->next = head;                                                                           \
- if (head) {                                                                                   \
-   (add)->prev = (head)->prev;                                                                 \
-   (head)->prev = (add);                                                                       \
- } else {                                                                                      \
-   (add)->prev = (add);                                                                        \
- }                                                                                             \
- (head) = (add);                                                                               \
-} while (0)
-
-#define DL_APPEND(head,add)                                                                    \
-    DL_APPEND2(head,add,prev,next)
-
-#define DL_APPEND2(head,add,prev,next)                                                         \
-do {                                                                                           \
-  if (head) {                                                                                  \
-      (add)->prev = (head)->prev;                                                              \
-      (head)->prev->next = (add);                                                              \
-      (head)->prev = (add);                                                                    \
-      (add)->next = NULL;                                                                      \
-  } else {                                                                                     \
-      (head)=(add);                                                                            \
-      (head)->prev = (head);                                                                   \
-      (head)->next = NULL;                                                                     \
-  }                                                                                            \
-} while (0)
-
-#define DL_CONCAT(head1,head2)                                                                 \
-    DL_CONCAT2(head1,head2,prev,next)
-
-#define DL_CONCAT2(head1,head2,prev,next)                                                      \
-do {                                                                                           \
-  LDECLTYPE(head1) _tmp;                                                                       \
-  if (head2) {                                                                                 \
-    if (head1) {                                                                               \
-        _tmp = (head2)->prev;                                                                  \
-        (head2)->prev = (head1)->prev;                                                         \
-        (head1)->prev->next = (head2);                                                         \
-        (head1)->prev = _tmp;                                                                  \
-    } else {                                                                                   \
-        (head1)=(head2);                                                                       \
-    }                                                                                          \
-  }                                                                                            \
-} while (0)
-
-#define DL_DELETE(head,del)                                                                    \
-    DL_DELETE2(head,del,prev,next)
-
-#define DL_DELETE2(head,del,prev,next)                                                         \
-do {                                                                                           \
-  assert((del)->prev != NULL);                                                                 \
-  if ((del)->prev == (del)) {                                                                  \
-      (head)=NULL;                                                                             \
-  } else if ((del)==(head)) {                                                                  \
-      (del)->next->prev = (del)->prev;                                                         \
-      (head) = (del)->next;                                                                    \
-  } else {                                                                                     \
-      (del)->prev->next = (del)->next;                                                         \
-      if ((del)->next) {                                                                       \
-          (del)->next->prev = (del)->prev;                                                     \
-      } else {                                                                                 \
-          (head)->prev = (del)->prev;                                                          \
-      }                                                                                        \
-  }                                                                                            \
-} while (0)
-
-#define DL_COUNT(head,el,counter)                                                              \
-    DL_COUNT2(head,el,counter,next)                                                            \
-
-#define DL_COUNT2(head,el,counter,next)                                                        \
-{                                                                                              \
-    counter = 0;                                                                               \
-    DL_FOREACH2(head,el,next){ ++counter; }                                                    \
-}
-
-#define DL_FOREACH(head,el)                                                                    \
-    DL_FOREACH2(head,el,next)
-
-#define DL_FOREACH2(head,el,next)                                                              \
-    for(el=head;el;el=(el)->next)
-
-/* this version is safe for deleting the elements during iteration */
-#define DL_FOREACH_SAFE(head,el,tmp)                                                           \
-    DL_FOREACH_SAFE2(head,el,tmp,next)
-
-#define DL_FOREACH_SAFE2(head,el,tmp,next)                                                     \
-  for((el)=(head);(el) && (tmp = (el)->next, 1); (el) = tmp)
-
-/* these are identical to their singly-linked list counterparts */
-#define DL_SEARCH_SCALAR LL_SEARCH_SCALAR
-#define DL_SEARCH LL_SEARCH
-#define DL_SEARCH_SCALAR2 LL_SEARCH_SCALAR2
-#define DL_SEARCH2 LL_SEARCH2
-
-#define DL_REPLACE_ELEM(head, el, add)                                                         \
-do {                                                                                           \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
-  (add)->next = (el)->next;                                                                    \
-  if ((el)->next == NULL) {                                                                    \
-   (add)->prev = (add);                                                                        \
-  } else {                                                                                     \
-   (add)->prev = (el)->prev;                                                                   \
-   (add)->next->prev = (add);                                                                  \
-  }                                                                                            \
- } else {                                                                                      \
-  (add)->next = (el)->next;                                                                    \
-  (add)->prev = (el)->prev;                                                                    \
-  (add)->prev->next = (add);                                                                   \
-  if ((el)->next == NULL) {                                                                    \
-   (head)->prev = (add);                                                                       \
-  } else {                                                                                     \
-   (add)->next->prev = (add);                                                                  \
-  }                                                                                            \
- }                                                                                             \
-} while (0)
-
-#define DL_PREPEND_ELEM(head, el, add)                                                         \
-do {                                                                                           \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- (add)->next = (el);                                                                           \
- (add)->prev = (el)->prev;                                                                     \
- (el)->prev = (add);                                                                           \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
- } else {                                                                                      \
-  (add)->prev->next = (add);                                                                   \
- }                                                                                             \
-} while (0)                                                                                    \
-
-
-/******************************************************************************
- * circular doubly linked list macros                                         *
- *****************************************************************************/
-#define CDL_PREPEND(head,add)                                                                  \
-    CDL_PREPEND2(head,add,prev,next)
-
-#define CDL_PREPEND2(head,add,prev,next)                                                       \
-do {                                                                                           \
- if (head) {                                                                                   \
-   (add)->prev = (head)->prev;                                                                 \
-   (add)->next = (head);                                                                       \
-   (head)->prev = (add);                                                                       \
-   (add)->prev->next = (add);                                                                  \
- } else {                                                                                      \
-   (add)->prev = (add);                                                                        \
-   (add)->next = (add);                                                                        \
- }                                                                                             \
-(head)=(add);                                                                                  \
-} while (0)
-
-#define CDL_DELETE(head,del)                                                                   \
-    CDL_DELETE2(head,del,prev,next)
-
-#define CDL_DELETE2(head,del,prev,next)                                                        \
-do {                                                                                           \
-  if ( ((head)==(del)) && ((head)->next == (head))) {                                          \
-      (head) = 0L;                                                                             \
-  } else {                                                                                     \
-     (del)->next->prev = (del)->prev;                                                          \
-     (del)->prev->next = (del)->next;                                                          \
-     if ((del) == (head)) (head)=(del)->next;                                                  \
-  }                                                                                            \
-} while (0)
-
-#define CDL_COUNT(head,el,counter)                                                             \
-    CDL_COUNT2(head,el,counter,next)                                                           \
-
-#define CDL_COUNT2(head, el, counter,next)                                                     \
-{                                                                                              \
-    counter = 0;                                                                               \
-    CDL_FOREACH2(head,el,next){ ++counter; }                                                   \
-}
-
-#define CDL_FOREACH(head,el)                                                                   \
-    CDL_FOREACH2(head,el,next)
-
-#define CDL_FOREACH2(head,el,next)                                                             \
-    for(el=head;el;el=((el)->next==head ? 0L : (el)->next))
-
-#define CDL_FOREACH_SAFE(head,el,tmp1,tmp2)                                                    \
-    CDL_FOREACH_SAFE2(head,el,tmp1,tmp2,prev,next)
-
-#define CDL_FOREACH_SAFE2(head,el,tmp1,tmp2,prev,next)                                         \
-  for((el)=(head), ((tmp1)=(head)?((head)->prev):NULL);                                        \
-      (el) && ((tmp2)=(el)->next, 1);                                                          \
-      ((el) = (((el)==(tmp1)) ? 0L : (tmp2))))
-
-#define CDL_SEARCH_SCALAR(head,out,field,val)                                                  \
-    CDL_SEARCH_SCALAR2(head,out,field,val,next)
-
-#define CDL_SEARCH_SCALAR2(head,out,field,val,next)                                            \
-do {                                                                                           \
-    CDL_FOREACH2(head,out,next) {                                                              \
-      if ((out)->field == (val)) break;                                                        \
-    }                                                                                          \
-} while(0)
-
-#define CDL_SEARCH(head,out,elt,cmp)                                                           \
-    CDL_SEARCH2(head,out,elt,cmp,next)
-
-#define CDL_SEARCH2(head,out,elt,cmp,next)                                                     \
-do {                                                                                           \
-    CDL_FOREACH2(head,out,next) {                                                              \
-      if ((cmp(out,elt))==0) break;                                                            \
-    }                                                                                          \
-} while(0)
-
-#define CDL_REPLACE_ELEM(head, el, add)                                                        \
-do {                                                                                           \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- if ((el)->next == (el)) {                                                                     \
-  (add)->next = (add);                                                                         \
-  (add)->prev = (add);                                                                         \
-  (head) = (add);                                                                              \
- } else {                                                                                      \
-  (add)->next = (el)->next;                                                                    \
-  (add)->prev = (el)->prev;                                                                    \
-  (add)->next->prev = (add);                                                                   \
-  (add)->prev->next = (add);                                                                   \
-  if ((head) == (el)) {                                                                        \
-   (head) = (add);                                                                             \
-  }                                                                                            \
- }                                                                                             \
-} while (0)
-
-#define CDL_PREPEND_ELEM(head, el, add)                                                        \
-do {                                                                                           \
- assert(head != NULL);                                                                         \
- assert(el != NULL);                                                                           \
- assert(add != NULL);                                                                          \
- (add)->next = (el);                                                                           \
- (add)->prev = (el)->prev;                                                                     \
- (el)->prev = (add);                                                                           \
- (add)->prev->next = (add);                                                                    \
- if ((head) == (el)) {                                                                         \
-  (head) = (add);                                                                              \
- }                                                                                             \
-} while (0)                                                                                    \
-
-#endif /* UTLIST_H */
-
diff --git a/tools/sdk/include/config/sdkconfig.h b/tools/sdk/include/config/sdkconfig.h
deleted file mode 100644
index b49c866cab8..00000000000
--- a/tools/sdk/include/config/sdkconfig.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/*
- *
- * Automatically generated file; DO NOT EDIT.
- * Espressif IoT Development Framework Configuration
- *
- */
-#define CONFIG_GATTC_ENABLE 1
-#define CONFIG_ESP32_PHY_MAX_TX_POWER 20
-#define CONFIG_TRACEMEM_RESERVE_DRAM 0x0
-#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
-#define CONFIG_MQTT_TRANSPORT_SSL 1
-#define CONFIG_BLE_SMP_ENABLE 1
-#define CONFIG_SPIRAM_TYPE_AUTO 1
-#define CONFIG_STACK_CHECK 1
-#define CONFIG_MB_SERIAL_TASK_PRIO 10
-#define CONFIG_MQTT_PROTOCOL_311 1
-#define CONFIG_TCP_RECVMBOX_SIZE 6
-#define CONFIG_LWIP_ETHARP_TRUST_IP_MAC 1
-#define CONFIG_BLE_SCAN_DUPLICATE 1
-#define CONFIG_STACK_CHECK_NORM 1
-#define CONFIG_TCP_WND_DEFAULT 5744
-#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
-#define CONFIG_SW_COEXIST_ENABLE 1
-#define CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE 3
-#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1
-#define CONFIG_ESPTOOLPY_FLASHSIZE_4MB 1
-#define CONFIG_IPC_TASK_STACK_SIZE 1024
-#define CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES 16
-#define CONFIG_FATFS_PER_FILE_CACHE 1
-#define CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY 1
-#define CONFIG_ESPTOOLPY_FLASHFREQ "40m"
-#define CONFIG_LWIP_TCP_RTO_TIME 3000
-#define CONFIG_SCCB_HARDWARE_I2C_PORT1 1
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1
-#define CONFIG_UDP_RECVMBOX_SIZE 6
-#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 16
-#define CONFIG_ARDUHAL_PARTITION_SCHEME_DEFAULT 1
-#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0
-#define CONFIG_MBEDTLS_AES_C 1
-#define CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED 1
-#define CONFIG_A2DP_SINK_TASK_STACK_SIZE 2048
-#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752
-#define CONFIG_MBEDTLS_GCM_C 1
-#define CONFIG_ESPTOOLPY_FLASHSIZE "4MB"
-#define CONFIG_SPIFFS_CACHE_WR 1
-#define CONFIG_SPIRAM_CACHE_WORKAROUND 1
-#define CONFIG_BROWNOUT_DET_LVL_SEL_0 1
-#define CONFIG_D0WD_PSRAM_CS_IO 16
-#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
-#define CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE 1
-#define CONFIG_BTDM_CONTROLLER_MODEM_SLEEP 1
-#define CONFIG_SPIFFS_CACHE 1
-#define CONFIG_INT_WDT 1
-#define CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL 1
-#define CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN 3
-#define CONFIG_MBEDTLS_SSL_PROTO_TLS1 1
-#define CONFIG_BT_STACK_NO_LOG 1
-#define CONFIG_ESP_GRATUITOUS_ARP 1
-#define CONFIG_MBEDTLS_ECDSA_C 1
-#define CONFIG_ESPTOOLPY_FLASHFREQ_40M 1
-#define CONFIG_HTTPD_MAX_REQ_HDR_LEN 512
-#define CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE 0
-#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
-#define CONFIG_MBEDTLS_ECDH_C 1
-#define CONFIG_SPIRAM_USE_CAPS_ALLOC 1
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE 1
-#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 16
-#define CONFIG_MBEDTLS_SSL_ALPN 1
-#define CONFIG_MBEDTLS_PEM_WRITE_C 1
-#define CONFIG_BT_SPP_ENABLED 1
-#define CONFIG_BT_RESERVE_DRAM 0xdb5c
-#define CONFIG_APP_COMPILE_TIME_DATE 1
-#define CONFIG_CXX_EXCEPTIONS 1
-#define CONFIG_D2WD_PSRAM_CLK_IO 9
-#define CONFIG_FATFS_FS_LOCK 0
-#define CONFIG_IP_LOST_TIMER_INTERVAL 120
-#define CONFIG_SPIFFS_META_LENGTH 4
-#define CONFIG_ESP32_PANIC_PRINT_REBOOT 1
-#define CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE 20
-#define CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED 1
-#define CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED 1
-#define CONFIG_CAMERA_CORE1 1
-#define CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL 5
-#define CONFIG_MB_SERIAL_BUF_SIZE 256
-#define CONFIG_CONSOLE_UART_BAUDRATE 115200
-#define CONFIG_SPIRAM_SUPPORT 1
-#define CONFIG_MFN56_1X 1
-#define CONFIG_LWIP_MAX_SOCKETS 10
-#define CONFIG_LWIP_NETIF_LOOPBACK 1
-#define CONFIG_LWIP_TCP_ISN_HOOK 1
-#define CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT "pthread"
-#define CONFIG_EMAC_TASK_PRIORITY 20
-#define CONFIG_TIMER_TASK_STACK_DEPTH 2048
-#define CONFIG_TCP_MSS 1436
-#define CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED 1
-#define CONFIG_BTDM_CONTROLLER_MODE_BTDM 1
-#define CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF 3
-#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1
-#define CONFIG_TCPIP_TASK_AFFINITY_CPU0 1
-#define CONFIG_FATFS_CODEPAGE 850
-#define CONFIG_SPIRAM_SPIWP_SD3_PIN 7
-#define CONFIG_ULP_COPROC_RESERVE_MEM 512
-#define CONFIG_LWIP_MAX_UDP_PCBS 16
-#define CONFIG_ESPTOOLPY_BAUD 921600
-#define CONFIG_INT_WDT_CHECK_CPU1 1
-#define CONFIG_ADC_CAL_LUT_ENABLE 1
-#define CONFIG_FLASHMODE_DIO 1
-#define CONFIG_LWIP_ESP_LWIP_ASSERT 1
-#define CONFIG_ESPTOOLPY_AFTER_RESET 1
-#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED 1
-#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8
-#define CONFIG_TOOLPREFIX "xtensa-esp32-elf-"
-#define CONFIG_MBEDTLS_ECP_C 1
-#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1024
-#define CONFIG_MBEDTLS_RC4_DISABLED 1
-#define CONFIG_FATFS_LFN_STACK 1
-#define CONFIG_BTDM_CONTROLLER_FULL_SCAN_SUPPORTED 1
-#define CONFIG_CONSOLE_UART_NUM 0
-#define CONFIG_ARDUINO_EVENT_RUNNING_CORE 1
-#define CONFIG_ESP32_APPTRACE_LOCK_ENABLE 1
-#define CONFIG_PTHREAD_STACK_MIN 768
-#define CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC 1
-#define CONFIG_TCP_OVERSIZE_MSS 1
-#define CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS 1
-#define CONFIG_CONSOLE_UART_DEFAULT 1
-#define CONFIG_A2DP_SOURCE_TASK_STACK_SIZE 2048
-#define CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN 16384
-#define CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS 4
-#define CONFIG_ESPTOOLPY_FLASHSIZE_DETECT 1
-#define CONFIG_AUTOSTART_ARDUINO 1
-#define CONFIG_ARDUINO_RUNNING_CORE 1
-#define CONFIG_ESP32_ECO3_CACHE_LOCK_FIX 1
-#define CONFIG_PPP_CHAP_SUPPORT 1
-#define CONFIG_LOG_DEFAULT_LEVEL_ERROR 1
-#define CONFIG_TIMER_TASK_STACK_SIZE 4096
-#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE 1
-#define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1
-#define CONFIG_MBEDTLS_X509_CRL_PARSE_C 1
-#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1
-#define CONFIG_HTTPD_PURGE_BUF_LEN 32
-#define CONFIG_SCAN_DUPLICATE_BY_DEVICE_ADDR 1
-#define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1
-#define CONFIG_MB_SERIAL_TASK_STACK_SIZE 2048
-#define CONFIG_MBEDTLS_PSK_MODES 1
-#define CONFIG_GATTS_SEND_SERVICE_CHANGE_AUTO 1
-#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60
-#define CONFIG_EFUSE_MAX_BLK_LEN 192
-#define CONFIG_SPIFFS_USE_MAGIC 1
-#define CONFIG_OV7725_SUPPORT 1
-#define CONFIG_TCPIP_TASK_STACK_SIZE 2560
-#define CONFIG_BLUEDROID_PINNED_TO_CORE_0 1
-#define CONFIG_FATFS_CODEPAGE_850 1
-#define CONFIG_TASK_WDT 1
-#define CONFIG_MTMN_LITE_QUANT 1
-#define CONFIG_MAIN_TASK_STACK_SIZE 4096
-#define CONFIG_SPIFFS_PAGE_CHECK 1
-#define CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0 1
-#define CONFIG_LWIP_MAX_ACTIVE_TCP 16
-#define CONFIG_TASK_WDT_TIMEOUT_S 5
-#define CONFIG_INT_WDT_TIMEOUT_MS 300
-#define CONFIG_ARDUINO_EVENT_RUN_CORE1 1
-#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
-#define CONFIG_BTC_TASK_STACK_SIZE 8192
-#define CONFIG_BLUEDROID_ENABLED 1
-#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA 1
-#define CONFIG_ESPTOOLPY_BEFORE "default_reset"
-#define CONFIG_ADC2_DISABLE_DAC 1
-#define CONFIG_HFP_ENABLE 1
-#define CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM 100
-#define CONFIG_ESP32_REV_MIN_0 1
-#define CONFIG_LOG_DEFAULT_LEVEL 1
-#define CONFIG_TIMER_QUEUE_LENGTH 10
-#define CONFIG_ESP32_REV_MIN 0
-#define CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT 1
-#define CONFIG_GATTS_SEND_SERVICE_CHANGE_MODE 0
-#define CONFIG_OV5640_SUPPORT 1
-#define CONFIG_MAKE_WARN_UNDEFINED_VARIABLES 1
-#define CONFIG_FATFS_TIMEOUT_MS 10000
-#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
-#define CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS 1
-#define CONFIG_MBEDTLS_CCM_C 1
-#define CONFIG_SPI_MASTER_ISR_IN_IRAM 1
-#define CONFIG_ARDUHAL_PARTITION_SCHEME "default"
-#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER 20
-#define CONFIG_ESP32_RTC_CLK_CAL_CYCLES 1024
-#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
-#define CONFIG_ESP32_WIFI_NVS_ENABLED 1
-#define CONFIG_MDNS_MAX_SERVICES 10
-#define CONFIG_ULP_COPROC_ENABLED 1
-#define CONFIG_HFP_AUDIO_DATA_PATH_PCM 1
-#define CONFIG_IDF_TARGET_ESP32 1
-#define CONFIG_EMAC_CHECK_LINK_PERIOD_MS 2000
-#define CONFIG_BTDM_LPCLK_SEL_MAIN_XTAL 1
-#define CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED 1
-#define CONFIG_LWIP_SNTP_UPDATE_DELAY 3600000
-#define CONFIG_LIBSODIUM_USE_MBEDTLS_SHA 1
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK 1
-#define CONFIG_DMA_RX_BUF_NUM 10
-#define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_PSK 1
-#define CONFIG_TCP_SYNMAXRTX 6
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1
-#define CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF 0
-#define CONFIG_HEAP_POISONING_LIGHT 1
-#define CONFIG_PYTHON "python"
-#define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8
-#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1
-#define CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 1
-#define CONFIG_ESPTOOLPY_COMPRESSED 1
-#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
-#define CONFIG_MB_CONTROLLER_STACK_SIZE 4096
-#define CONFIG_TCP_SND_BUF_DEFAULT 5744
-#define CONFIG_GARP_TMR_INTERVAL 60
-#define CONFIG_LWIP_DHCP_MAX_NTP_SERVERS 1
-#define CONFIG_TCP_MSL 60000
-#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_1 1
-#define CONFIG_LWIP_SO_REUSE_RXTOALL 1
-#define CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT 20
-#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32
-#define CONFIG_PARTITION_TABLE_SINGLE_APP 1
-#define CONFIG_XTENSA_IMPL 1
-#define CONFIG_UNITY_ENABLE_FLOAT 1
-#define CONFIG_ESP32_WIFI_RX_BA_WIN 16
-#define CONFIG_MBEDTLS_X509_CSR_PARSE_C 1
-#define CONFIG_SPIFFS_USE_MTIME 1
-#define CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN 0
-#define CONFIG_LWIP_DHCP_RESTORE_LAST_IP 1
-#define CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN 2
-#define CONFIG_PICO_PSRAM_CS_IO 10
-#define CONFIG_EMAC_TASK_STACK_SIZE 3072
-#define CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT 1
-#define CONFIG_MB_QUEUE_LENGTH 20
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1
-#define CONFIG_OV2640_SUPPORT 1
-#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK 1
-#define CONFIG_PPP_SUPPORT 1
-#define CONFIG_SPIRAM_SPEED_40M 1
-#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2048
-#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
-#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
-#define CONFIG_BROWNOUT_DET_LVL 0
-#define CONFIG_MBEDTLS_PEM_PARSE_C 1
-#define CONFIG_SPIFFS_GC_MAX_RUNS 10
-#define CONFIG_ARDUINO_RUN_CORE1 1
-#define CONFIG_ESP32_APPTRACE_DEST_NONE 1
-#define CONFIG_HP_NANO1 1
-#define CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC 1
-#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 1
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA 1
-#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
-#define CONFIG_HTTPD_MAX_URI_LEN 512
-#define CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED 1
-#define CONFIG_OV7670_SUPPORT 1
-#define CONFIG_ARDUHAL_ESP_LOG 1
-#define CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED 1
-#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 240
-#define CONFIG_MBEDTLS_HARDWARE_AES 1
-#define CONFIG_FREERTOS_HZ 1000
-#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE 1
-#define CONFIG_ADC_CAL_EFUSE_TP_ENABLE 1
-#define CONFIG_FREERTOS_ASSERT_FAIL_ABORT 1
-#define CONFIG_BROWNOUT_DET 1
-#define CONFIG_ESP32_XTAL_FREQ 0
-#define CONFIG_MONITOR_BAUD_115200B 1
-#define CONFIG_LOG_BOOTLOADER_LEVEL 0
-#define CONFIG_D2WD_PSRAM_CS_IO 10
-#define CONFIG_MBEDTLS_TLS_ENABLED 1
-#define CONFIG_LWIP_MAX_RAW_PCBS 16
-#define CONFIG_BTU_TASK_STACK_SIZE 4096
-#define CONFIG_SMP_ENABLE 1
-#define CONFIG_SPIRAM_SIZE -1
-#define CONFIG_ARDUINO_UDP_TASK_PRIORITY 3
-#define CONFIG_MBEDTLS_SSL_SESSION_TICKETS 1
-#define CONFIG_SPIFFS_MAX_PARTITIONS 3
-#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1
-#define CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_0 1
-#define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1
-#define CONFIG_ESPTOOLPY_BEFORE_RESET 1
-#define CONFIG_MB_EVENT_QUEUE_TIMEOUT 20
-#define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200
-#define CONFIG_PPP_MPPE_SUPPORT 1
-#define CONFIG_ENABLE_ARDUINO_DEPENDS 1
-#define CONFIG_WARN_WRITE_STRINGS 1
-#define CONFIG_SPIFFS_OBJ_NAME_LEN 32
-#define CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT 5
-#define CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF 2
-#define CONFIG_LOG_BOOTLOADER_LEVEL_NONE 1
-#define CONFIG_PARTITION_TABLE_MD5 1
-#define CONFIG_TCPIP_RECVMBOX_SIZE 32
-#define CONFIG_ESP32_DEFAULT_CPU_FREQ_240 1
-#define CONFIG_ESP32_XTAL_FREQ_AUTO 1
-#define CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST 1
-#define CONFIG_TCP_MAXRTX 12
-#define CONFIG_ESPTOOLPY_AFTER "hard_reset"
-#define CONFIG_LWIP_IP4_FRAG 1
-#define CONFIG_TCPIP_TASK_AFFINITY 0x0
-#define CONFIG_LWIP_SO_REUSE 1
-#define CONFIG_ARDUINO_UDP_RUN_CORE1 1
-#define CONFIG_DMA_TX_BUF_NUM 10
-#define CONFIG_LWIP_MAX_LISTENING_TCP 16
-#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1
-#define CONFIG_WL_SECTOR_SIZE 4096
-#define CONFIG_ESP32_DEBUG_OCDAWARE 1
-#define CONFIG_MQTT_TRANSPORT_WEBSOCKET 1
-#define CONFIG_TIMER_TASK_PRIORITY 1
-#define CONFIG_PPP_PAP_SUPPORT 1
-#define CONFIG_MBEDTLS_TLS_CLIENT 1
-#define CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI 1
-#define CONFIG_BT_ENABLED 1
-#define CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY 1
-#define CONFIG_D0WD_PSRAM_CLK_IO 17
-#define CONFIG_BT_SSP_ENABLED 1
-#define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1
-#define CONFIG_MONITOR_BAUD 115200
-#define CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT -1
-#define CONFIG_ESP32_DEBUG_STUBS_ENABLE 1
-#define CONFIG_BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT 30
-#define CONFIG_TCPIP_LWIP 1
-#define CONFIG_REDUCE_PHY_TX_POWER 1
-#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
-#define CONFIG_FREERTOS_CORETIMER_0 1
-#define CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF 1
-#define CONFIG_LWIP_IP6_FRAG 1
-#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0000
-#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
-#define CONFIG_MBEDTLS_HAVE_TIME 1
-#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1
-#define CONFIG_TCP_QUEUE_OOSEQ 1
-#define CONFIG_FATFS_ALLOC_PREFER_EXTRAM 1
-#define CONFIG_GATTS_ENABLE 1
-#define CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE 0
-#define CONFIG_ADC_CAL_EFUSE_VREF_ENABLE 1
-#define CONFIG_MBEDTLS_TLS_SERVER 1
-#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1
-#define CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED 1
-#define CONFIG_FREERTOS_ISR_STACKSIZE 1536
-#define CONFIG_SUPPORT_TERMIOS 1
-#define CONFIG_CLASSIC_BT_ENABLED 1
-#define CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK 1
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK 1
-#define CONFIG_OPENSSL_ASSERT_DO_NOTHING 1
-#define CONFIG_IDF_TARGET "esp32"
-#define CONFIG_WL_SECTOR_SIZE_4096 1
-#define CONFIG_OPTIMIZATION_LEVEL_DEBUG 1
-#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF
-#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
-#define CONFIG_HTTPD_ERR_RESP_NO_DELAY 1
-#define CONFIG_MB_TIMER_INDEX 0
-#define CONFIG_SCAN_DUPLICATE_TYPE 0
-#define CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED 1
-#define CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED 1
-#define CONFIG_HFP_CLIENT_ENABLE 1
-#define CONFIG_NT99141_SUPPORT 1
-#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA 1
-#define CONFIG_SPI_SLAVE_ISR_IN_IRAM 1
-#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE 32
-#define CONFIG_BT_ACL_CONNECTIONS 4
-#define CONFIG_FATFS_MAX_LFN 255
-#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
-#define CONFIG_ESPTOOLPY_BAUD_921600B 1
-#define CONFIG_BOOTLOADER_WDT_ENABLE 1
-#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
-#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8
-#define CONFIG_A2DP_ENABLE 1
-#define CONFIG_MB_TIMER_GROUP 0
-#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
-#define CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS 5
-#define CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE 1
-#define CONFIG_SPIFFS_PAGE_SIZE 256
-#define CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED 1
-#define CONFIG_ESP32_DPORT_WORKAROUND 1
-#define CONFIG_PPP_MSCHAP_SUPPORT 1
-#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 1
-#define CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT 2048
-#define CONFIG_LWIP_SO_RCVBUF 1
-#define CONFIG_MB_TIMER_PORT_ENABLED 1
-#define CONFIG_DUPLICATE_SCAN_CACHE_SIZE 20
-#define CONFIG_ARDUINO_UDP_RUNNING_CORE 1
-#define CONFIG_MONITOR_BAUD_OTHER_VAL 115200
-#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1
-#define CONFIG_ESPTOOLPY_PORT "/dev/cu.usbserial-DO00EAB0"
-#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS 1
-#define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 0
-#define CONFIG_LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1
-#define CONFIG_TASK_WDT_PANIC 1
-#define CONFIG_OV3660_SUPPORT 1
-#define CONFIG_UNITY_ENABLE_DOUBLE 1
-#define CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD 20
-#define CONFIG_BLUEDROID_PINNED_TO_CORE 0
-#define CONFIG_HD_NANO1 1
-#define CONFIG_BTDM_MODEM_SLEEP_MODE_ORIG 1
-#define CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_ERROR 1
-#define CONFIG_FATFS_API_ENCODING_ANSI_OEM 1
-#define CONFIG_ARDUINO_IDF_COMMIT "68b237fe5"
-#define CONFIG_ARDUINO_IDF_BRANCH "release/v3.3"
diff --git a/tools/sdk/include/console/argtable3/argtable3.h b/tools/sdk/include/console/argtable3/argtable3.h
deleted file mode 100644
index 37a321fb53a..00000000000
--- a/tools/sdk/include/console/argtable3/argtable3.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/*******************************************************************************
- * This file is part of the argtable3 library.
- *
- * Copyright (C) 1998-2001,2003-2011,2013 Stewart Heitmann
- * <sheitmann@users.sourceforge.net>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of STEWART HEITMANN nor the  names of its contributors
- *       may be used to endorse or promote products derived from this software
- *       without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL STEWART HEITMANN BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************/
-
-#ifndef ARGTABLE3
-#define ARGTABLE3
-
-#include <stdio.h>      /* FILE */
-#include <time.h>       /* struct tm */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ARG_REX_ICASE 1
-    
-/* bit masks for arg_hdr.flag */
-enum
-{
-    ARG_TERMINATOR=0x1,
-    ARG_HASVALUE=0x2,
-    ARG_HASOPTVALUE=0x4
-};
-
-typedef void (arg_resetfn)(void *parent);
-typedef int  (arg_scanfn)(void *parent, const char *argval);
-typedef int  (arg_checkfn)(void *parent);
-typedef void (arg_errorfn)(void *parent, FILE *fp, int error, const char *argval, const char *progname);
-
-
-/*
-* The arg_hdr struct defines properties that are common to all arg_xxx structs.
-* The argtable library requires each arg_xxx struct to have an arg_hdr
-* struct as its first data member.
-* The argtable library functions then use this data to identify the
-* properties of the command line option, such as its option tags,
-* datatype string, and glossary strings, and so on.
-* Moreover, the arg_hdr struct contains pointers to custom functions that
-* are provided by each arg_xxx struct which perform the tasks of parsing
-* that particular arg_xxx arguments, performing post-parse checks, and
-* reporting errors.
-* These functions are private to the individual arg_xxx source code
-* and are the pointer to them are initiliased by that arg_xxx struct's
-* constructor function. The user could alter them after construction
-* if desired, but the original intention is for them to be set by the
-* constructor and left unaltered.
-*/
-struct arg_hdr
-{
-    char         flag;        /* Modifier flags: ARG_TERMINATOR, ARG_HASVALUE. */
-    const char  *shortopts;   /* String defining the short options */
-    const char  *longopts;    /* String defiing the long options */
-    const char  *datatype;    /* Description of the argument data type */
-    const char  *glossary;    /* Description of the option as shown by arg_print_glossary function */
-    int          mincount;    /* Minimum number of occurences of this option accepted */
-    int          maxcount;    /* Maximum number of occurences if this option accepted */
-    void        *parent;      /* Pointer to parent arg_xxx struct */
-    arg_resetfn *resetfn;     /* Pointer to parent arg_xxx reset function */
-    arg_scanfn  *scanfn;      /* Pointer to parent arg_xxx scan function */
-    arg_checkfn *checkfn;     /* Pointer to parent arg_xxx check function */
-    arg_errorfn *errorfn;     /* Pointer to parent arg_xxx error function */
-    void        *priv;        /* Pointer to private header data for use by arg_xxx functions */
-};
-
-struct arg_rem
-{
-    struct arg_hdr hdr;      /* The mandatory argtable header struct */
-};
-
-struct arg_lit
-{
-    struct arg_hdr hdr;      /* The mandatory argtable header struct */
-    int count;               /* Number of matching command line args */
-};
-
-struct arg_int
-{
-    struct arg_hdr hdr;      /* The mandatory argtable header struct */
-    int count;               /* Number of matching command line args */
-    int *ival;               /* Array of parsed argument values */
-};
-
-struct arg_dbl
-{
-    struct arg_hdr hdr;      /* The mandatory argtable header struct */
-    int count;               /* Number of matching command line args */
-    double *dval;            /* Array of parsed argument values */
-};
-
-struct arg_str
-{
-    struct arg_hdr hdr;      /* The mandatory argtable header struct */
-    int count;               /* Number of matching command line args */
-    const char **sval;       /* Array of parsed argument values */
-};
-
-struct arg_rex
-{
-    struct arg_hdr hdr;      /* The mandatory argtable header struct */
-    int count;               /* Number of matching command line args */
-    const char **sval;       /* Array of parsed argument values */
-};
-
-struct arg_file
-{
-    struct arg_hdr hdr;      /* The mandatory argtable header struct */
-    int count;               /* Number of matching command line args*/
-    const char **filename;   /* Array of parsed filenames  (eg: /home/foo.bar) */
-    const char **basename;   /* Array of parsed basenames  (eg: foo.bar) */
-    const char **extension;  /* Array of parsed extensions (eg: .bar) */
-};
-
-struct arg_date
-{
-    struct arg_hdr hdr;      /* The mandatory argtable header struct */
-    const char *format;      /* strptime format string used to parse the date */
-    int count;               /* Number of matching command line args */
-    struct tm *tmval;        /* Array of parsed time values */
-};
-
-enum {ARG_ELIMIT=1, ARG_EMALLOC, ARG_ENOMATCH, ARG_ELONGOPT, ARG_EMISSARG};
-struct arg_end
-{
-    struct arg_hdr hdr;      /* The mandatory argtable header struct */
-    int count;               /* Number of errors encountered */
-    int *error;              /* Array of error codes */
-    void **parent;           /* Array of pointers to offending arg_xxx struct */
-    const char **argval;     /* Array of pointers to offending argv[] string */
-};
-
-
-/**** arg_xxx constructor functions *********************************/
-
-struct arg_rem* arg_rem(const char* datatype, const char* glossary);
-
-struct arg_lit* arg_lit0(const char* shortopts,
-    const char* longopts,
-    const char* glossary);
-struct arg_lit* arg_lit1(const char* shortopts,
-    const char* longopts,
-    const char *glossary);
-struct arg_lit* arg_litn(const char* shortopts,
-    const char* longopts,
-    int mincount,
-    int maxcount,
-    const char *glossary);
-
-struct arg_key* arg_key0(const char* keyword,
-    int flags,
-    const char* glossary);
-struct arg_key* arg_key1(const char* keyword,
-    int flags,
-    const char* glossary);
-struct arg_key* arg_keyn(const char* keyword,
-    int flags,
-    int mincount,
-    int maxcount,
-    const char* glossary);
-
-struct arg_int* arg_int0(const char* shortopts,
-    const char* longopts,
-    const char* datatype,
-    const char* glossary);
-struct arg_int* arg_int1(const char* shortopts,
-    const char* longopts,
-    const char* datatype,
-    const char *glossary);
-struct arg_int* arg_intn(const char* shortopts,
-    const char* longopts,
-    const char *datatype,
-    int mincount,
-    int maxcount,
-    const char *glossary);
-
-struct arg_dbl* arg_dbl0(const char* shortopts,
-    const char* longopts,
-    const char* datatype,
-    const char* glossary);
-struct arg_dbl* arg_dbl1(const char* shortopts,
-    const char* longopts,
-    const char* datatype,
-    const char *glossary);
-struct arg_dbl* arg_dbln(const char* shortopts,
-    const char* longopts,
-    const char *datatype,
-    int mincount,
-    int maxcount,
-    const char *glossary);
-
-struct arg_str* arg_str0(const char* shortopts,
-    const char* longopts,
-    const char* datatype,
-    const char* glossary);
-struct arg_str* arg_str1(const char* shortopts,
-    const char* longopts,                    
-    const char* datatype,
-    const char *glossary);
-struct arg_str* arg_strn(const char* shortopts,
-    const char* longopts,
-    const char* datatype,
-    int mincount,
-    int maxcount,
-    const char *glossary);
-
-struct arg_rex* arg_rex0(const char* shortopts,
-    const char* longopts,
-    const char* pattern,
-    const char* datatype,
-    int flags,
-    const char* glossary);
-struct arg_rex* arg_rex1(const char* shortopts,
-    const char* longopts,
-    const char* pattern,
-    const char* datatype,
-    int flags,
-    const char *glossary);
-struct arg_rex* arg_rexn(const char* shortopts,
-    const char* longopts,
-    const char* pattern,
-    const char* datatype,
-    int mincount,
-    int maxcount,
-    int flags,
-    const char *glossary);
-
-struct arg_file* arg_file0(const char* shortopts,
-    const char* longopts,
-    const char* datatype,
-    const char* glossary);
-struct arg_file* arg_file1(const char* shortopts,
-    const char* longopts,
-    const char* datatype,
-    const char *glossary);
-struct arg_file* arg_filen(const char* shortopts,
-    const char* longopts,
-    const char* datatype,
-    int mincount,
-    int maxcount,
-    const char *glossary);
-
-struct arg_date* arg_date0(const char* shortopts,
-    const char* longopts,
-    const char* format,
-    const char* datatype,
-    const char* glossary);
-struct arg_date* arg_date1(const char* shortopts,
-    const char* longopts,
-    const char* format,
-    const char* datatype,
-    const char *glossary);
-struct arg_date* arg_daten(const char* shortopts,
-    const char* longopts,
-    const char* format,
-    const char* datatype,
-    int mincount,
-    int maxcount,
-    const char *glossary);
-
-struct arg_end* arg_end(int maxerrors);
-
-
-/**** other functions *******************************************/
-int arg_nullcheck(void **argtable);
-int arg_parse(int argc, char **argv, void **argtable);
-void arg_print_option(FILE *fp, const char *shortopts, const char *longopts, const char *datatype, const char *suffix);
-void arg_print_syntax(FILE *fp, void **argtable, const char *suffix);
-void arg_print_syntaxv(FILE *fp, void **argtable, const char *suffix);
-void arg_print_glossary(FILE *fp, void **argtable, const char *format);
-void arg_print_glossary_gnu(FILE *fp, void **argtable);
-void arg_print_errors(FILE* fp, struct arg_end* end, const char* progname);
-void arg_freetable(void **argtable, size_t n);
-void arg_print_formatted(FILE *fp, const unsigned lmargin, const unsigned rmargin, const char *text);
-
-/**** deprecated functions, for back-compatibility only ********/
-void arg_free(void **argtable);
-
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/tools/sdk/include/console/esp_console.h b/tools/sdk/include/console/esp_console.h
deleted file mode 100644
index 45a10b7a2ed..00000000000
--- a/tools/sdk/include/console/esp_console.h
+++ /dev/null
@@ -1,192 +0,0 @@
-// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include <stddef.h>
-#include "esp_err.h"
-
-// Forward declaration. Definition in linenoise/linenoise.h.
-typedef struct linenoiseCompletions linenoiseCompletions;
-
-/**
- * @brief Parameters for console initialization
- */
-typedef struct {
-    size_t max_cmdline_length;  //!< length of command line buffer, in bytes
-    size_t max_cmdline_args;    //!< maximum number of command line arguments to parse
-    int hint_color;     //!< ASCII color code of hint text
-    int hint_bold;      //!< Set to 1 to print hint text in bold
-} esp_console_config_t;
-
-/**
- * @brief initialize console module
- * Call this once before using other console module features
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NO_MEM if out of memory
- *      - ESP_ERR_INVALID_STATE if already initialized
- */
-esp_err_t esp_console_init(const esp_console_config_t* config);
-
-
-/**
- * @brief de-initialize console module
- * Call this once when done using console module functions
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if not initialized yet
- */
-esp_err_t esp_console_deinit();
-
-
-/**
- * @brief Console command main function
- * @param argc number of arguments
- * @param argv array with argc entries, each pointing to a zero-terminated string argument
- * @return console command return code, 0 indicates "success"
- */
-typedef int (*esp_console_cmd_func_t)(int argc, char** argv);
-
-/**
- * @brief Console command description
- */
-typedef struct {
-    /**
-     * Command name. Must not be NULL, must not contain spaces.
-     * The pointer must be valid until the call to esp_console_deinit.
-     */
-    const char* command;    //!< command name
-    /**
-     * Help text for the command, shown by help command.
-     * If set, the pointer must be valid until the call to esp_console_deinit.
-     * If not set, the command will not be listed in 'help' output.
-     */
-    const char* help;
-    /**
-     * Hint text, usually lists possible arguments.
-     * If set to NULL, and 'argtable' field is non-NULL, hint will be generated
-     * automatically
-     */
-    const char* hint;
-    /**
-     * Pointer to a function which implements the command.
-     */
-    esp_console_cmd_func_t func;
-    /**
-     * Array or structure of pointers to arg_xxx structures, may be NULL.
-     * Used to generate hint text if 'hint' is set to NULL.
-     * Array/structure which this field points to must end with an arg_end.
-     * Only used for the duration of esp_console_cmd_register call.
-     */
-    void* argtable;
-} esp_console_cmd_t;
-
-/**
- * @brief Register console command
- * @param cmd pointer to the command description; can point to a temporary value
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NO_MEM if out of memory
- */
-esp_err_t esp_console_cmd_register(const esp_console_cmd_t *cmd);
-
-/**
- * @brief Run command line
- * @param cmdline command line (command name followed by a number of arguments)
- * @param[out] cmd_ret return code from the command (set if command was run)
- * @return
- *      - ESP_OK, if command was run
- *      - ESP_ERR_INVALID_ARG, if the command line is empty, or only contained
- *        whitespace
- *      - ESP_ERR_NOT_FOUND, if command with given name wasn't registered
- *      - ESP_ERR_INVALID_STATE, if esp_console_init wasn't called
- */
-esp_err_t esp_console_run(const char* cmdline, int* cmd_ret);
-
-/**
- * @brief Split command line into arguments in place
- *
- * - This function finds whitespace-separated arguments in the given input line.
- *
- *     'abc def 1 20 .3' -> [ 'abc', 'def', '1', '20', '.3' ]
- *
- * - Argument which include spaces may be surrounded with quotes. In this case
- *   spaces are preserved and quotes are stripped.
- *
- *     'abc "123 456" def' -> [ 'abc', '123 456', 'def' ]
- *
- * - Escape sequences may be used to produce backslash, double quote, and space:
- *
- *     'a\ b\\c\"' -> [ 'a b\c"' ]
- *
- * Pointers to at most argv_size - 1 arguments are returned in argv array.
- * The pointer after the last one (i.e. argv[argc]) is set to NULL.
- *
- * @param line pointer to buffer to parse; it is modified in place
- * @param argv array where the pointers to arguments are written
- * @param argv_size number of elements in argv_array (max. number of arguments)
- * @return number of arguments found (argc)
- */
-size_t esp_console_split_argv(char *line, char **argv, size_t argv_size);
-
-/**
- * @brief Callback which provides command completion for linenoise library
- *
- * When using linenoise for line editing, command completion support
- * can be enabled like this:
- *
- *   linenoiseSetCompletionCallback(&esp_console_get_completion);
- *
- * @param buf the string typed by the user
- * @param lc linenoiseCompletions to be filled in
- */
-void esp_console_get_completion(const char *buf, linenoiseCompletions *lc);
-
-/**
- * @brief Callback which provides command hints for linenoise library
- *
- * When using linenoise for line editing, hints support can be enabled as
- * follows:
- *
- *   linenoiseSetHintsCallback((linenoiseHintsCallback*) &esp_console_get_hint);
- *
- * The extra cast is needed because linenoiseHintsCallback is defined as
- * returning a char* instead of const char*.
- *
- * @param buf line typed by the user
- * @param[out] color ANSI color code to be used when displaying the hint
- * @param[out] bold set to 1 if hint has to be displayed in bold
- * @return string containing the hint text. This string is persistent and should
- *         not be freed (i.e. linenoiseSetFreeHintsCallback should not be used).
- */
-const char *esp_console_get_hint(const char *buf, int *color, int *bold);
-
-/**
- * @brief Register a 'help' command
- * Default 'help' command prints the list of registered commands along with
- * hints and help strings.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE, if esp_console_init wasn't called
- */
-esp_err_t esp_console_register_help_command();
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/console/linenoise/linenoise.h b/tools/sdk/include/console/linenoise/linenoise.h
deleted file mode 100644
index a82701f835b..00000000000
--- a/tools/sdk/include/console/linenoise/linenoise.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* linenoise.h -- VERSION 1.0
- *
- * Guerrilla line editing library against the idea that a line editing lib
- * needs to be 20,000 lines of C code.
- *
- * See linenoise.c for more information.
- *
- * ------------------------------------------------------------------------
- *
- * Copyright (c) 2010-2014, Salvatore Sanfilippo <antirez at gmail dot com>
- * Copyright (c) 2010-2013, Pieter Noordhuis <pcnoordhuis at gmail dot com>
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *  *  Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *  *  Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in the
- *     documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __LINENOISE_H
-#define __LINENOISE_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct linenoiseCompletions {
-  size_t len;
-  char **cvec;
-} linenoiseCompletions;
-
-typedef void(linenoiseCompletionCallback)(const char *, linenoiseCompletions *);
-typedef char*(linenoiseHintsCallback)(const char *, int *color, int *bold);
-typedef void(linenoiseFreeHintsCallback)(void *);
-void linenoiseSetCompletionCallback(linenoiseCompletionCallback *);
-void linenoiseSetHintsCallback(linenoiseHintsCallback *);
-void linenoiseSetFreeHintsCallback(linenoiseFreeHintsCallback *);
-void linenoiseAddCompletion(linenoiseCompletions *, const char *);
-
-int linenoiseProbe(void);
-char *linenoise(const char *prompt);
-void linenoiseFree(void *ptr);
-int linenoiseHistoryAdd(const char *line);
-int linenoiseHistorySetMaxLen(int len);
-int linenoiseHistorySave(const char *filename);
-int linenoiseHistoryLoad(const char *filename);
-void linenoiseHistoryFree();
-void linenoiseClearScreen(void);
-void linenoiseSetMultiLine(int ml);
-void linenoiseSetDumbMode(int set);
-void linenoisePrintKeyCodes(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LINENOISE_H */
diff --git a/tools/sdk/include/driver/driver/adc.h b/tools/sdk/include/driver/driver/adc.h
deleted file mode 100644
index b5a9a9848e3..00000000000
--- a/tools/sdk/include/driver/driver/adc.h
+++ /dev/null
@@ -1,408 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_ADC_H_
-#define _DRIVER_ADC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-#include "driver/gpio.h"
-#include "soc/adc_channel.h"
-
-typedef enum {
-    ADC_ATTEN_DB_0   = 0,  /*!<The input voltage of ADC will be reduced to about 1/1 */
-    ADC_ATTEN_DB_2_5 = 1,  /*!<The input voltage of ADC will be reduced to about 1/1.34 */
-    ADC_ATTEN_DB_6   = 2,  /*!<The input voltage of ADC will be reduced to about 1/2 */
-    ADC_ATTEN_DB_11  = 3,  /*!<The input voltage of ADC will be reduced to about 1/3.6*/
-    ADC_ATTEN_MAX,
-} adc_atten_t;
-
-typedef enum {
-    ADC_WIDTH_BIT_9  = 0, /*!< ADC capture width is 9Bit*/
-    ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit*/
-    ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit*/
-    ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit*/
-    ADC_WIDTH_MAX,
-} adc_bits_width_t;
-
-//this definitions are only for being back-compatible
-#define ADC_ATTEN_0db   ADC_ATTEN_DB_0
-#define ADC_ATTEN_2_5db ADC_ATTEN_DB_2_5
-#define ADC_ATTEN_6db   ADC_ATTEN_DB_6
-#define ADC_ATTEN_11db  ADC_ATTEN_DB_11
-//this definitions are only for being back-compatible
-#define ADC_WIDTH_9Bit  ADC_WIDTH_BIT_9
-#define ADC_WIDTH_10Bit ADC_WIDTH_BIT_10
-#define ADC_WIDTH_11Bit ADC_WIDTH_BIT_11
-#define ADC_WIDTH_12Bit ADC_WIDTH_BIT_12
-
-typedef enum {
-    ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO36 */
-    ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO37 */
-    ADC1_CHANNEL_2,     /*!< ADC1 channel 2 is GPIO38 */
-    ADC1_CHANNEL_3,     /*!< ADC1 channel 3 is GPIO39 */
-    ADC1_CHANNEL_4,     /*!< ADC1 channel 4 is GPIO32 */
-    ADC1_CHANNEL_5,     /*!< ADC1 channel 5 is GPIO33 */
-    ADC1_CHANNEL_6,     /*!< ADC1 channel 6 is GPIO34 */
-    ADC1_CHANNEL_7,     /*!< ADC1 channel 7 is GPIO35 */
-    ADC1_CHANNEL_MAX,
-} adc1_channel_t;
-
-typedef enum {
-    ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO4 */
-    ADC2_CHANNEL_1,     /*!< ADC2 channel 1 is GPIO0 */
-    ADC2_CHANNEL_2,     /*!< ADC2 channel 2 is GPIO2 */
-    ADC2_CHANNEL_3,     /*!< ADC2 channel 3 is GPIO15 */
-    ADC2_CHANNEL_4,     /*!< ADC2 channel 4 is GPIO13 */
-    ADC2_CHANNEL_5,     /*!< ADC2 channel 5 is GPIO12 */
-    ADC2_CHANNEL_6,     /*!< ADC2 channel 6 is GPIO14 */
-    ADC2_CHANNEL_7,     /*!< ADC2 channel 7 is GPIO27 */
-    ADC2_CHANNEL_8,     /*!< ADC2 channel 8 is GPIO25 */
-    ADC2_CHANNEL_9,     /*!< ADC2 channel 9 is GPIO26 */
-    ADC2_CHANNEL_MAX,
-} adc2_channel_t;
-
-typedef enum {
-    ADC_CHANNEL_0 = 0, /*!< ADC channel */
-    ADC_CHANNEL_1,     /*!< ADC channel */
-    ADC_CHANNEL_2,     /*!< ADC channel */
-    ADC_CHANNEL_3,     /*!< ADC channel */
-    ADC_CHANNEL_4,     /*!< ADC channel */
-    ADC_CHANNEL_5,     /*!< ADC channel */
-    ADC_CHANNEL_6,     /*!< ADC channel */
-    ADC_CHANNEL_7,     /*!< ADC channel */
-    ADC_CHANNEL_8,     /*!< ADC channel */
-    ADC_CHANNEL_9,     /*!< ADC channel */
-    ADC_CHANNEL_MAX,
-} adc_channel_t;
-
-typedef enum {
-    ADC_UNIT_1 = 1,          /*!< SAR ADC 1*/
-    ADC_UNIT_2 = 2,          /*!< SAR ADC 2, not supported yet*/
-    ADC_UNIT_BOTH = 3,       /*!< SAR ADC 1 and 2, not supported yet */
-    ADC_UNIT_ALTER = 7,      /*!< SAR ADC 1 and 2 alternative mode, not supported yet */
-    ADC_UNIT_MAX,
-} adc_unit_t;
-
-typedef enum {
-    ADC_ENCODE_12BIT,        /*!< ADC to I2S data format, [15:12]-channel [11:0]-12 bits ADC data */
-    ADC_ENCODE_11BIT,        /*!< ADC to I2S data format, [15]-1 [14:11]-channel [10:0]-11 bits ADC data */
-    ADC_ENCODE_MAX,
-} adc_i2s_encode_t;
-
-typedef enum {
-    ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal  */
-    ADC_I2S_DATA_SRC_ADC = 1,    /*!< I2S data from ADC */
-    ADC_I2S_DATA_SRC_MAX,
-} adc_i2s_source_t;
-
-/**
- * @brief Get the gpio number of a specific ADC1 channel.
- * 
- * @param channel Channel to get the gpio number
- * 
- * @param gpio_num output buffer to hold the gpio number
- * 
- * @return 
- *   - ESP_OK if success
- *   - ESP_ERR_INVALID_ARG if channal not valid 
- */
-esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num);
-
-/**
- * @brief Configure ADC1 capture width, meanwhile enable output invert for ADC1.
- * The configuration is for all channels of ADC1
- * @param width_bit Bit capture width for ADC1
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t adc1_config_width(adc_bits_width_t width_bit);
-
-/**
- * @brief Configure ADC capture width.
- * @param adc_unit ADC unit index
- * @param width_bit Bit capture width for ADC unit.
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit);
-
-/**
- * @brief Set the attenuation of a particular channel on ADC1, and configure its
- * associated GPIO pin mux.
- *
- * @note For any given channel, this function must be called before the first time
- * adc1_get_raw() is called for that channel.
- *
- * @note This function can be called multiple times to configure multiple
- * ADC channels simultaneously. adc1_get_raw() can then be called for any configured
- * channel.
- *
- * The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage,
- * usually 3.3V) requires setting >0dB signal attenuation for that ADC channel.
- *
- * When VDD_A is 3.3V:
- *
- * - 0dB attenuaton (ADC_ATTEN_DB_0) gives full-scale voltage 1.1V
- * - 2.5dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5V
- * - 6dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2V
- * - 11dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9V (see note below)
- *
- * @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured
- * bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.)
- *
- * @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage.
- *
- * Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges:
- *
- * - 0dB attenuaton (ADC_ATTEN_DB_0) between 100 and 950mV
- * - 2.5dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250mV
- * - 6dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750mV
- * - 11dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450mV
- *
- * For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges.
- *
- * @param channel ADC1 channel to configure
- * @param atten  Attenuation level
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten);
-
-/**
- * @brief Take an ADC1 reading from a single channel.
- * @note When the power switch of SARADC1, SARADC2, HALL sensor and AMP sensor is turned on,
- *       the input of GPIO36 and GPIO39 will be pulled down for about 80ns.
- *       When enabling power for any of these peripherals, ignore input from GPIO36 and GPIO39.
- *       Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue.
- *
- * @note Call adc1_config_width() before the first time this
- * function is called.
- *
- * @note For any given channel, adc1_config_channel_atten(channel)
- * must be called before the first time this function is called. Configuring
- * a new channel does not prevent a previously configured channel from being read.
- *
- * @param  channel ADC1 channel to read
- *
- * @return
- *     - -1: Parameter error
- *     -  Other: ADC1 channel reading.
- */
-int adc1_get_raw(adc1_channel_t channel);
-
-/** @cond */    //Doxygen command to hide deprecated function from API Reference
-/*
- * @note When the power switch of SARADC1, SARADC2, HALL sensor and AMP sensor is turned on,
- *       the input of GPIO36 and GPIO39 will be pulled down for about 80ns.
- *       When enabling power for any of these peripherals, ignore input from GPIO36 and GPIO39.
- *       Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue.
- *       
- * @deprecated This function returns an ADC1 reading but is deprecated due to
- * a misleading name and has been changed to directly call the new function.
- * Use the new function adc1_get_raw() instead
- */
-int adc1_get_voltage(adc1_channel_t channel) __attribute__((deprecated));
-/** @endcond */
-
-/**
- * @brief Enable ADC power
- */
-void adc_power_on();
-
-/**
- * @brief Power off SAR ADC
- * This function will force power down for ADC
- */
-void adc_power_off();
-
-/**
- * @brief Initialize ADC pad
- * @param adc_unit ADC unit index
- * @param channel ADC channel index
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel);
-
-/**
- * @brief Set ADC data invert
- * @param adc_unit ADC unit index
- * @param inv_en whether enable data invert
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en);
-
-/**
- * @brief Set ADC source clock
- * @param clk_div ADC clock divider, ADC clock is divided from APB clock
- * @return
- *     - ESP_OK success
- */
-esp_err_t adc_set_clk_div(uint8_t clk_div);
-
-/**
- * @brief Set I2S data source
- * @param src I2S DMA data source, I2S DMA can get data from digital signals or from ADC.
- * @return
- *     - ESP_OK success
- */
-esp_err_t adc_set_i2s_data_source(adc_i2s_source_t src);
-
-/**
- * @brief Initialize I2S ADC mode
- * @param adc_unit ADC unit index
- * @param channel ADC channel index
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel);
-
-/**
- * @brief Configure ADC1 to be usable by the ULP
- *
- * This function reconfigures ADC1 to be controlled by the ULP.
- * Effect of this function can be reverted using adc1_get_raw function.
- *
- * Note that adc1_config_channel_atten, adc1_config_width functions need
- * to be called to configure ADC1 channels, before ADC1 is used by the ULP.
- */
-void adc1_ulp_enable();
-
-/**
- * @brief Read Hall Sensor
- *
- * @note When the power switch of SARADC1, SARADC2, HALL sensor and AMP sensor is turned on,
- *       the input of GPIO36 and GPIO39 will be pulled down for about 80ns.
- *       When enabling power for any of these peripherals, ignore input from GPIO36 and GPIO39.
- *       Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue.
- *
- * @note The Hall Sensor uses channels 0 and 3 of ADC1. Do not configure
- * these channels for use as ADC channels.
- *
- * @note The ADC1 module must be enabled by calling
- *       adc1_config_width() before calling hall_sensor_read(). ADC1
- *       should be configured for 12 bit readings, as the hall sensor
- *       readings are low values and do not cover the full range of the
- *       ADC.
- *
- * @return The hall sensor reading.
- */
-int hall_sensor_read();
-
-/**
- * @brief Get the gpio number of a specific ADC2 channel.
- * 
- * @param channel Channel to get the gpio number
- * 
- * @param gpio_num output buffer to hold the gpio number
- * 
- * @return 
- *   - ESP_OK if success
- *   - ESP_ERR_INVALID_ARG if channal not valid 
- */
-esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num);
-
-/**
- * @brief Configure the ADC2 channel, including setting attenuation.
- *
- * @note This function also configures the input GPIO pin mux to
- * connect it to the ADC2 channel. It must be called before calling
- * ``adc2_get_raw()`` for this channel.
- *
- * The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage,
- * usually 3.3V) requires setting >0dB signal attenuation for that ADC channel.
- *
- * When VDD_A is 3.3V:
- *
- * - 0dB attenuaton (ADC_ATTEN_0db) gives full-scale voltage 1.1V
- * - 2.5dB attenuation (ADC_ATTEN_2_5db) gives full-scale voltage 1.5V
- * - 6dB attenuation (ADC_ATTEN_6db) gives full-scale voltage 2.2V
- * - 11dB attenuation (ADC_ATTEN_11db) gives full-scale voltage 3.9V (see note below)
- *
- * @note The full-scale voltage is the voltage corresponding to a maximum reading 
- * (depending on ADC2 configured bit width, this value is: 4095 for 12-bits, 2047 
- * for 11-bits, 1023 for 10-bits, 511 for 9 bits.)
- *
- * @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage.
- *
- * @param channel ADC2 channel to configure
- * @param atten  Attenuation level
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
-
-/**
- * @brief Take an ADC2 reading on a single channel
- *
- * @note When the power switch of SARADC1, SARADC2, HALL sensor and AMP sensor is turned on,
- *       the input of GPIO36 and GPIO39 will be pulled down for about 80ns.
- *       When enabling power for any of these peripherals, ignore input from GPIO36 and GPIO39.
- *       Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue.
- *
- * @note For a given channel, ``adc2_config_channel_atten()``
- * must be called before the first time this function is called. If Wi-Fi is started via ``esp_wifi_start()``, this
- * function will always fail with ``ESP_ERR_TIMEOUT``.
- *
- * @param  channel ADC2 channel to read
- * 
- * @param width_bit Bit capture width for ADC2
- * 
- * @param raw_out the variable to hold the output data.
- *
- * @return
- *     - ESP_OK if success
- *     - ESP_ERR_TIMEOUT the WIFI is started, using the ADC2
- */
-esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int* raw_out);
-
-/**
- *  @brief Output ADC2 reference voltage to gpio 25 or 26 or 27
- *
- *  This function utilizes the testing mux exclusive to ADC 2 to route the
- *  reference voltage one of ADC2's channels. Supported gpios are gpios
- *  25, 26, and 27. This refernce voltage can be manually read from the pin
- *  and used in the esp_adc_cal component.
- *
- *  @param[in]  gpio    GPIO number (gpios 25,26,27 supported)
- *
- *  @return
- *                  - ESP_OK: v_ref successfully routed to selected gpio
- *                  - ESP_ERR_INVALID_ARG: Unsupported gpio
- */
-esp_err_t adc2_vref_to_gpio(gpio_num_t gpio);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /*_DRIVER_ADC_H_*/
-
diff --git a/tools/sdk/include/driver/driver/adc2_wifi_internal.h b/tools/sdk/include/driver/driver/adc2_wifi_internal.h
deleted file mode 100644
index ba5c32ead94..00000000000
--- a/tools/sdk/include/driver/driver/adc2_wifi_internal.h
+++ /dev/null
@@ -1,52 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_ADC2_INTERNAL_H_
-#define _DRIVER_ADC2_INTERNAL_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "esp_err.h"
-
-/**
- * @brief For WIFI module to claim the usage of ADC2.
- *
- * Other tasks will be forbidden to use ADC2 between ``adc2_wifi_acquire`` and ``adc2_wifi_release``.
- * The WIFI module may have to wait for a short time for the current conversion (if exist) to finish.
- *
- * @return
- *      - ESP_OK success
- *      - ESP_ERR_TIMEOUT reserved for future use. Currently the function will wait until success.
- */
-esp_err_t adc2_wifi_acquire();
-
-
-/**
- * @brief For WIFI module to let other tasks use the ADC2 when WIFI is not work.
- *
- * Other tasks will be forbidden to use ADC2 between ``adc2_wifi_acquire`` and ``adc2_wifi_release``.
- * Call this function to release the occupation of ADC2 by WIFI.
- *
- * @return always return ESP_OK.
- */
-esp_err_t adc2_wifi_release();
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /*_DRIVER_ADC2_INTERNAL_H_*/
-
diff --git a/tools/sdk/include/driver/driver/can.h b/tools/sdk/include/driver/driver/can.h
deleted file mode 100644
index 28d42077fb4..00000000000
--- a/tools/sdk/include/driver/driver/can.h
+++ /dev/null
@@ -1,436 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_CAN_H_
-#define _DRIVER_CAN_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "freertos/FreeRTOS.h"
-#include "esp_types.h"
-#include "esp_intr.h"
-#include "esp_err.h"
-#include "gpio.h"
-
-/* -------------------- Default initializers and flags ---------------------- */
-/** @cond */    //Doxy command to hide preprocessor definitions from docs
-/**
- * @brief Initializer macro for general configuration structure.
- *
- * This initializer macros allows the TX GPIO, RX GPIO, and operating mode to be
- * configured. The other members of the general configuration structure are
- * assigned default values.
- */
-#define CAN_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) {.mode = op_mode, .tx_io = tx_io_num, .rx_io = rx_io_num,       \
-                                                                   .clkout_io = CAN_IO_UNUSED, .bus_off_io = CAN_IO_UNUSED,       \
-                                                                   .tx_queue_len = 5, .rx_queue_len = 5,                          \
-                                                                   .alerts_enabled = CAN_ALERT_NONE,  .clkout_divider = 0,        }
-
-/**
- * @brief Initializer macros for timing configuration structure
- *
- * The following initializer macros offer commonly found bit rates.
- *
- * @note These timing values are based on the assumption APB clock is at 80MHz
- * @note The 20K, 16K and 12.5K bit rates are only available from ESP32 Revision 2 onwards
- */
-#if (CONFIG_ESP32_REV_MIN >= 2)
-#define CAN_TIMING_CONFIG_12_5KBITS()   {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
-#define CAN_TIMING_CONFIG_16KBITS()     {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
-#define CAN_TIMING_CONFIG_20KBITS()     {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
-#endif
-#define CAN_TIMING_CONFIG_25KBITS()     {.brp = 128, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
-#define CAN_TIMING_CONFIG_50KBITS()     {.brp = 80, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
-#define CAN_TIMING_CONFIG_100KBITS()    {.brp = 40, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
-#define CAN_TIMING_CONFIG_125KBITS()    {.brp = 32, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
-#define CAN_TIMING_CONFIG_250KBITS()    {.brp = 16, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
-#define CAN_TIMING_CONFIG_500KBITS()    {.brp = 8, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
-#define CAN_TIMING_CONFIG_800KBITS()    {.brp = 4, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
-#define CAN_TIMING_CONFIG_1MBITS()      {.brp = 4, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
-
-/**
- * @brief   Initializer macro for filter configuration to accept all IDs
- */
-#define CAN_FILTER_CONFIG_ACCEPT_ALL()  {.acceptance_code = 0, .acceptance_mask = 0xFFFFFFFF, .single_filter = true}
-
-/**
- * @brief   Alert flags
- *
- * The following flags represents the various kind of alerts available in
- * the CAN driver. These flags can be used when configuring/reconfiguring
- * alerts, or when calling can_read_alerts().
- *
- * @note    The CAN_ALERT_AND_LOG flag is not an actual alert, but will configure
- *          the CAN driver to log to UART when an enabled alert occurs.
- */
-#define CAN_ALERT_TX_IDLE               0x0001      /**< Alert(1): No more messages to transmit */
-#define CAN_ALERT_TX_SUCCESS            0x0002      /**< Alert(2): The previous transmission was successful */
-#define CAN_ALERT_BELOW_ERR_WARN        0x0004      /**< Alert(4): Both error counters have dropped below error warning limit */
-#define CAN_ALERT_ERR_ACTIVE            0x0008      /**< Alert(8): CAN controller has become error active */
-#define CAN_ALERT_RECOVERY_IN_PROGRESS  0x0010      /**< Alert(16): CAN controller is undergoing bus recovery */
-#define CAN_ALERT_BUS_RECOVERED         0x0020      /**< Alert(32): CAN controller has successfully completed bus recovery */
-#define CAN_ALERT_ARB_LOST              0x0040      /**< Alert(64): The previous transmission lost arbitration */
-#define CAN_ALERT_ABOVE_ERR_WARN        0x0080      /**< Alert(128): One of the error counters have exceeded the error warning limit */
-#define CAN_ALERT_BUS_ERROR             0x0100      /**< Alert(256): A (Bit, Stuff, CRC, Form, ACK) error has occurred on the bus */
-#define CAN_ALERT_TX_FAILED             0x0200      /**< Alert(512): The previous transmission has failed (for single shot transmission) */
-#define CAN_ALERT_RX_QUEUE_FULL         0x0400      /**< Alert(1024): The RX queue is full causing a frame to be lost */
-#define CAN_ALERT_ERR_PASS              0x0800      /**< Alert(2048): CAN controller has become error passive */
-#define CAN_ALERT_BUS_OFF               0x1000      /**< Alert(4096): Bus-off condition occurred. CAN controller can no longer influence bus */
-#define CAN_ALERT_ALL                   0x1FFF      /**< Bit mask to enable all alerts during configuration */
-#define CAN_ALERT_NONE                  0x0000      /**< Bit mask to disable all alerts during configuration */
-#define CAN_ALERT_AND_LOG               0x2000      /**< Bit mask to enable alerts to also be logged when they occur */
-
-/**
- * @brief   Message flags
- *
- * The message flags are used to indicate the type of message transmitted/received.
- * Some flags also specify the type of transmission.
- */
-#define CAN_MSG_FLAG_NONE               0x00        /**< No message flags (Standard Frame Format) */
-#define CAN_MSG_FLAG_EXTD               0x01        /**< Extended Frame Format (29bit ID)  */
-#define CAN_MSG_FLAG_RTR                0x02        /**< Message is a Remote Transmit Request */
-#define CAN_MSG_FLAG_SS                 0x04        /**< Transmit as a Single Shot Transmission */
-#define CAN_MSG_FLAG_SELF               0x08        /**< Transmit as a Self Reception Request */
-#define CAN_MSG_FLAG_DLC_NON_COMP       0x10        /**< Message's Data length code is larger than 8. This will break compliance with CAN2.0B */
-
-/**
- * @brief Miscellaneous macros
- */
-#define CAN_EXTD_ID_MASK                0x1FFFFFFF  /**< Bit mask for 29 bit Extended Frame Format ID */
-#define CAN_STD_ID_MASK                 0x7FF       /**< Bit mask for 11 bit Standard Frame Format ID */
-#define CAN_MAX_DATA_LEN                8           /**< Maximum number of data bytes in a CAN2.0B frame */
-#define CAN_IO_UNUSED                   ((gpio_num_t) -1)   /**< Marks GPIO as unused in CAN configuration */
-/** @endcond */
-
-/* ----------------------- Enum and Struct Definitions ---------------------- */
-
-/**
- * @brief   CAN driver operating modes
- */
-typedef enum {
-    CAN_MODE_NORMAL,                /**< Normal operating mode where CAN controller can send/receive/acknowledge messages */
-    CAN_MODE_NO_ACK,                /**< Transmission does not require acknowledgment. Use this mode for self testing */
-    CAN_MODE_LISTEN_ONLY,           /**< The CAN controller will not influence the bus (No transmissions or acknowledgments) but can receive messages */
-} can_mode_t;
-
-/**
- * @brief   CAN driver states
- */
-typedef enum {
-    CAN_STATE_STOPPED,              /**< Stopped state. The CAN controller will not participate in any CAN bus activities */
-    CAN_STATE_RUNNING,              /**< Running state. The CAN controller can transmit and receive messages */
-    CAN_STATE_BUS_OFF,              /**< Bus-off state. The CAN controller cannot participate in bus activities until it has recovered */
-    CAN_STATE_RECOVERING,           /**< Recovering state. The CAN controller is undergoing bus recovery */
-} can_state_t;
-
-/**
- * @brief   Structure for general configuration of the CAN driver
- *
- * @note    Macro initializers are available for this structure
- */
-typedef struct {
-    can_mode_t mode;                /**< Mode of CAN controller */
-    gpio_num_t tx_io;               /**< Transmit GPIO number */
-    gpio_num_t rx_io;               /**< Receive GPIO number */
-    gpio_num_t clkout_io;           /**< CLKOUT GPIO number (optional, set to -1 if unused) */
-    gpio_num_t bus_off_io;          /**< Bus off indicator GPIO number (optional, set to -1 if unused) */
-    uint32_t tx_queue_len;          /**< Number of messages TX queue can hold (set to 0 to disable TX Queue) */
-    uint32_t rx_queue_len;          /**< Number of messages RX queue can hold */
-    uint32_t alerts_enabled;        /**< Bit field of alerts to enable (see documentation) */
-    uint32_t clkout_divider;        /**< CLKOUT divider. Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused) */
-} can_general_config_t;
-
-/**
- * @brief   Structure for bit timing configuration of the CAN driver
- *
- * @note    Macro initializers are available for this structure
- */
-typedef struct {
-    uint32_t brp;                   /**< Baudrate prescaler (i.e., APB clock divider) can be any even number from 2 to 128.
-                                         For ESP32 Rev 2 or later, multiples of 4 from 132 to 256 are also supported */
-    uint8_t tseg_1;                 /**< Timing segment 1 (Number of time quanta, between 1 to 16) */
-    uint8_t tseg_2;                 /**< Timing segment 2 (Number of time quanta, 1 to 8) */
-    uint8_t sjw;                    /**< Synchronization Jump Width (Max time quanta jump for synchronize from 1 to 4) */
-    bool triple_sampling;           /**< Enables triple sampling when the CAN controller samples a bit */
-} can_timing_config_t;
-
-/**
- * @brief   Structure for acceptance filter configuration of the CAN driver (see documentation)
- *
- * @note    Macro initializers are available for this structure
- */
-typedef struct {
-    uint32_t acceptance_code;       /**< 32-bit acceptance code */
-    uint32_t acceptance_mask;       /**< 32-bit acceptance mask */
-    bool single_filter;             /**< Use Single Filter Mode (see documentation) */
-} can_filter_config_t;
-
-/**
- * @brief   Structure to store status information of CAN driver
- */
-typedef struct {
-    can_state_t state;              /**< Current state of CAN controller (Stopped/Running/Bus-Off/Recovery) */
-    uint32_t msgs_to_tx;            /**< Number of messages queued for transmission or awaiting transmission completion */
-    uint32_t msgs_to_rx;            /**< Number of messages in RX queue waiting to be read */
-    uint32_t tx_error_counter;      /**< Current value of Transmit Error Counter */
-    uint32_t rx_error_counter;      /**< Current value of Receive Error Counter */
-    uint32_t tx_failed_count;       /**< Number of messages that failed transmissions */
-    uint32_t rx_missed_count;       /**< Number of messages that were lost due to a full RX queue */
-    uint32_t arb_lost_count;        /**< Number of instances arbitration was lost */
-    uint32_t bus_error_count;       /**< Number of instances a bus error has occurred */
-} can_status_info_t;
-
-/**
- * @brief   Structure to store a CAN message
- *
- * @note    The flags member is used to control the message type, and transmission
- *          type (see documentation for message flags)
- */
-typedef struct {
-    uint32_t flags;                 /**< Bit field of message flags indicates frame/transmission type (see documentation) */
-    uint32_t identifier;            /**< 11 or 29 bit identifier */
-    uint8_t data_length_code;       /**< Data length code */
-    uint8_t data[CAN_MAX_DATA_LEN]; /**< Data bytes (not relevant in RTR frame) */
-} can_message_t;
-
-/* ----------------------------- Public API -------------------------------- */
-
-/**
- * @brief   Install CAN driver
- *
- * This function installs the CAN driver using three configuration structures.
- * The required memory is allocated and the CAN driver is placed in the stopped
- * state after running this function.
- *
- * @param[in]   g_config    General configuration structure
- * @param[in]   t_config    Timing configuration structure
- * @param[in]   f_config    Filter configuration structure
- *
- * @note    Macro initializers are available for the configuration structures (see documentation)
- *
- * @note    To reinstall the CAN driver, call can_driver_uninstall() first
- *
- * @return
- *      - ESP_OK: Successfully installed CAN driver
- *      - ESP_ERR_INVALID_ARG: Arguments are invalid
- *      - ESP_ERR_NO_MEM: Insufficient memory
- *      - ESP_ERR_INVALID_STATE: Driver is already installed
- */
-esp_err_t can_driver_install(const can_general_config_t *g_config, const can_timing_config_t *t_config, const can_filter_config_t *f_config);
-
-/**
- * @brief   Uninstall the CAN driver
- *
- * This function uninstalls the CAN driver, freeing the memory utilized by the
- * driver. This function can only be called when the driver is in the stopped
- * state or the bus-off state.
- *
- * @warning The application must ensure that no tasks are blocked on TX/RX
- *          queues or alerts when this function is called.
- *
- * @return
- *      - ESP_OK: Successfully uninstalled CAN driver
- *      - ESP_ERR_INVALID_STATE: Driver is not in stopped/bus-off state, or is not installed
- */
-esp_err_t can_driver_uninstall();
-
-/**
- * @brief   Start the CAN driver
- *
- * This function starts the CAN driver, putting the CAN driver into the running
- * state. This allows the CAN driver to participate in CAN bus activities such
- * as transmitting/receiving messages. The RX queue is reset in this function,
- * clearing any unread messages. This function can only be called when the CAN
- * driver is in the stopped state.
- *
- * @return
- *      - ESP_OK: CAN driver is now running
- *      - ESP_ERR_INVALID_STATE: Driver is not in stopped state, or is not installed
- */
-esp_err_t can_start();
-
-/**
- * @brief   Stop the CAN driver
- *
- * This function stops the CAN driver, preventing any further message from being
- * transmitted or received until can_start() is called. Any messages in the TX
- * queue are cleared. Any messages in the RX queue should be read by the
- * application after this function is called. This function can only be called
- * when the CAN driver is in the running state.
- *
- * @warning A message currently being transmitted/received on the CAN bus will
- *          be ceased immediately. This may lead to other CAN nodes interpreting
- *          the unfinished message as an error.
- *
- * @return
- *      - ESP_OK: CAN driver is now Stopped
- *      - ESP_ERR_INVALID_STATE: Driver is not in running state, or is not installed
- */
-esp_err_t can_stop();
-
-/**
- * @brief   Transmit a CAN message
- *
- * This function queues a CAN message for transmission. Transmission will start
- * immediately if no other messages are queued for transmission. If the TX queue
- * is full, this function will block until more space becomes available or until
- * it timesout. If the TX queue is disabled (TX queue length = 0 in configuration),
- * this function will return immediately if another message is undergoing
- * transmission. This function can only be called when the CAN driver is in the
- * running state and cannot be called under Listen Only Mode.
- *
- * @param[in]   message         Message to transmit
- * @param[in]   ticks_to_wait   Number of FreeRTOS ticks to block on the TX queue
- *
- * @note    This function does not guarantee that the transmission is successful.
- *          The TX_SUCCESS/TX_FAILED alert can be enabled to alert the application
- *          upon the success/failure of a transmission.
- *
- * @note    The TX_IDLE alert can be used to alert the application when no other
- *          messages are awaiting transmission.
- *
- * @return
- *      - ESP_OK: Transmission successfully queued/initiated
- *      - ESP_ERR_INVALID_ARG: Arguments are invalid
- *      - ESP_ERR_TIMEOUT: Timed out waiting for space on TX queue
- *      - ESP_FAIL: TX queue is disabled and another message is currently transmitting
- *      - ESP_ERR_INVALID_STATE: CAN driver is not in running state, or is not installed
- *      - ESP_ERR_NOT_SUPPORTED: Listen Only Mode does not support transmissions
- */
-esp_err_t can_transmit(const can_message_t *message, TickType_t ticks_to_wait);
-
-/**
- * @brief   Receive a CAN message
- *
- * This function receives a message from the RX queue. The flags field of the
- * message structure will indicate the type of message received. This function
- * will block if there are no messages in the RX queue
- *
- * @param[out]  message         Received message
- * @param[in]   ticks_to_wait   Number of FreeRTOS ticks to block on RX queue
- *
- * @warning The flags field of the received message should be checked to determine
- *          if the received message contains any data bytes.
- *
- * @return
- *      - ESP_OK: Message successfully received from RX queue
- *      - ESP_ERR_TIMEOUT: Timed out waiting for message
- *      - ESP_ERR_INVALID_ARG: Arguments are invalid
- *      - ESP_ERR_INVALID_STATE: CAN driver is not installed
- */
-esp_err_t can_receive(can_message_t *message, TickType_t ticks_to_wait);
-
-/**
- * @brief   Read CAN driver alerts
- *
- * This function will read the alerts raised by the CAN driver. If no alert has
- * been when this function is called, this function will block until an alert
- * occurs or until it timeouts.
- *
- * @param[out]  alerts          Bit field of raised alerts (see documentation for alert flags)
- * @param[in]   ticks_to_wait   Number of FreeRTOS ticks to block for alert
- *
- * @note    Multiple alerts can be raised simultaneously. The application should
- *          check for all alerts that have been enabled.
- *
- * @return
- *      - ESP_OK: Alerts read
- *      - ESP_ERR_TIMEOUT: Timed out waiting for alerts
- *      - ESP_ERR_INVALID_ARG: Arguments are invalid
- *      - ESP_ERR_INVALID_STATE: CAN driver is not installed
- */
-esp_err_t can_read_alerts(uint32_t *alerts, TickType_t ticks_to_wait);
-
-/**
- * @brief   Reconfigure which alerts are enabled
- *
- * This function reconfigures which alerts are enabled. If there are alerts
- * which have not been read whilst reconfiguring, this function can read those
- * alerts.
- *
- * @param[in]   alerts_enabled  Bit field of alerts to enable (see documentation for alert flags)
- * @param[out]  current_alerts  Bit field of currently raised alerts. Set to NULL if unused
- *
- * @return
- *      - ESP_OK: Alerts reconfigured
- *      - ESP_ERR_INVALID_STATE: CAN driver is not installed
- */
-esp_err_t can_reconfigure_alerts(uint32_t alerts_enabled, uint32_t *current_alerts);
-
-/**
- * @brief   Start the bus recovery process
- *
- * This function initiates the bus recovery process when the CAN driver is in
- * the bus-off state. Once initiated, the CAN driver will enter the recovering
- * state and wait for 128 occurrences of the bus-free signal on the CAN bus
- * before returning to the stopped state. This function will reset the TX queue,
- * clearing any messages pending transmission.
- *
- * @note    The BUS_RECOVERED alert can be enabled to alert the application when
- *          the bus recovery process completes.
- *
- * @return
- *      - ESP_OK: Bus recovery started
- *      - ESP_ERR_INVALID_STATE: CAN driver is not in the bus-off state, or is not installed
- */
-esp_err_t can_initiate_recovery();
-
-/**
- * @brief   Get current status information of the CAN driver
- *
- * @param[out]  status_info     Status information
- *
- * @return
- *      - ESP_OK: Status information retrieved
- *      - ESP_ERR_INVALID_ARG: Arguments are invalid
- *      - ESP_ERR_INVALID_STATE: CAN driver is not installed
- */
-esp_err_t can_get_status_info(can_status_info_t *status_info);
-
-/**
- * @brief   Clear the transmit queue
- *
- * This function will clear the transmit queue of all messages.
- *
- * @note    The transmit queue is automatically cleared when can_stop() or
- *          can_initiate_recovery() is called.
- *
- * @return
- *      - ESP_OK: Transmit queue cleared
- *      - ESP_ERR_INVALID_STATE: CAN driver is not installed or TX queue is disabled
- */
-esp_err_t can_clear_transmit_queue();
-
-/**
- * @brief   Clear the receive queue
- *
- * This function will clear the receive queue of all messages.
- *
- * @note    The receive queue is automatically cleared when can_start() is
- *          called.
- *
- * @return
- *      - ESP_OK: Transmit queue cleared
- *      - ESP_ERR_INVALID_STATE: CAN driver is not installed
- */
-esp_err_t can_clear_receive_queue();
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*_DRIVER_CAN_H_*/
-
diff --git a/tools/sdk/include/driver/driver/dac.h b/tools/sdk/include/driver/driver/dac.h
deleted file mode 100644
index f921d98f146..00000000000
--- a/tools/sdk/include/driver/driver/dac.h
+++ /dev/null
@@ -1,113 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_DAC_H_
-#define _DRIVER_DAC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include "esp_err.h"
-#include "soc/dac_channel.h"
-
-typedef enum {
-    DAC_CHANNEL_1 = 1,  /*!< DAC channel 1 is GPIO25 */
-    DAC_CHANNEL_2,      /*!< DAC channel 2 is GPIO26 */
-    DAC_CHANNEL_MAX,
-} dac_channel_t;
-
-/**
- * @brief Get the gpio number of a specific DAC channel.
- * 
- * @param channel Channel to get the gpio number
- * 
- * @param gpio_num output buffer to hold the gpio number
- * 
- * @return 
- *   - ESP_OK if success
- *   - ESP_ERR_INVALID_ARG if channal not valid 
- */
-esp_err_t dac_pad_get_io_num(dac_channel_t channel, gpio_num_t *gpio_num);
-
-/** @cond */
-/**
-  * @brief  Set DAC output voltage.
-  *
-  * @note Function has been deprecated, please use dac_output_voltage instead.
-  *       This name will be removed in a future release.
-  *       The difference is that before calling dac_output_voltage, we need to initialize the dac pad by dac_output_enable
-  *
-  *
-  * @param channel DAC channel
-  * @param dac_value DAC output value
-  *
-  * @return
-  *     - ESP_OK success
-  *     - ESP_ERR_INVALID_ARG Parameter error
-  */
-esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value) __attribute__ ((deprecated));
-/** @endcond */
-
-/**
- * @brief Set DAC output voltage.
- *
- * DAC output is 8-bit. Maximum (255) corresponds to VDD.
- *
- * @note Need to configure DAC pad before calling this function.
- *       DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
- *
- * @param channel DAC channel
- * @param dac_value DAC output value
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t dac_output_voltage(dac_channel_t channel, uint8_t dac_value);
-
-/**
- * @brief DAC pad output enable
- *
- * @param channel DAC channel
- * @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
- *       I2S left channel will be mapped to DAC channel 2
- *       I2S right channel will be mapped to DAC channel 1
- */
-esp_err_t dac_output_enable(dac_channel_t channel);
-
-/**
- * @brief DAC pad output disable
- *
- * @param channel DAC channel
- * @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
- */
-esp_err_t dac_output_disable(dac_channel_t channel);
-
-/**
- * @brief Enable DAC output data from I2S
- */
-esp_err_t dac_i2s_enable();
-
-/**
- * @brief Disable DAC output data from I2S
- */
-esp_err_t dac_i2s_disable();
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /*_DRIVER_DAC_H_*/
-
diff --git a/tools/sdk/include/driver/driver/gpio.h b/tools/sdk/include/driver/driver/gpio.h
deleted file mode 100644
index c2231a625b1..00000000000
--- a/tools/sdk/include/driver/driver/gpio.h
+++ /dev/null
@@ -1,617 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_GPIO_H_
-#define _DRIVER_GPIO_H_
-#include "esp_err.h"
-#include <esp_types.h>
-#include "soc/gpio_reg.h"
-#include "soc/gpio_struct.h"
-#include "soc/rtc_io_reg.h"
-#include "soc/io_mux_reg.h"
-#include "soc/gpio_sig_map.h"
-#include "rom/gpio.h"
-#include "esp_attr.h"
-#include "esp_intr_alloc.h"
-#include "soc/gpio_periph.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define GPIO_SEL_0              (BIT(0))                         /*!< Pin 0 selected */
-#define GPIO_SEL_1              (BIT(1))                         /*!< Pin 1 selected */
-#define GPIO_SEL_2              (BIT(2))                         /*!< Pin 2 selected
-                                                                      @note There are more macros
-                                                                      like that up to pin 39,
-                                                                      excluding pins 20, 24 and 28..31.
-                                                                      They are not shown here
-                                                                      to reduce redundant information. */
-/** @cond */
-#define GPIO_SEL_3              (BIT(3))                         /*!< Pin 3 selected */
-#define GPIO_SEL_4              (BIT(4))                         /*!< Pin 4 selected */
-#define GPIO_SEL_5              (BIT(5))                         /*!< Pin 5 selected */
-#define GPIO_SEL_6              (BIT(6))                         /*!< Pin 6 selected */
-#define GPIO_SEL_7              (BIT(7))                         /*!< Pin 7 selected */
-#define GPIO_SEL_8              (BIT(8))                         /*!< Pin 8 selected */
-#define GPIO_SEL_9              (BIT(9))                         /*!< Pin 9 selected */
-#define GPIO_SEL_10             (BIT(10))                        /*!< Pin 10 selected */
-#define GPIO_SEL_11             (BIT(11))                        /*!< Pin 11 selected */
-#define GPIO_SEL_12             (BIT(12))                        /*!< Pin 12 selected */
-#define GPIO_SEL_13             (BIT(13))                        /*!< Pin 13 selected */
-#define GPIO_SEL_14             (BIT(14))                        /*!< Pin 14 selected */
-#define GPIO_SEL_15             (BIT(15))                        /*!< Pin 15 selected */
-#define GPIO_SEL_16             (BIT(16))                        /*!< Pin 16 selected */
-#define GPIO_SEL_17             (BIT(17))                        /*!< Pin 17 selected */
-#define GPIO_SEL_18             (BIT(18))                        /*!< Pin 18 selected */
-#define GPIO_SEL_19             (BIT(19))                        /*!< Pin 19 selected */
-
-#define GPIO_SEL_21             (BIT(21))                        /*!< Pin 21 selected */
-#define GPIO_SEL_22             (BIT(22))                        /*!< Pin 22 selected */
-#define GPIO_SEL_23             (BIT(23))                        /*!< Pin 23 selected */
-
-#define GPIO_SEL_25             (BIT(25))                        /*!< Pin 25 selected */
-#define GPIO_SEL_26             (BIT(26))                        /*!< Pin 26 selected */
-#define GPIO_SEL_27             (BIT(27))                        /*!< Pin 27 selected */
-
-#define GPIO_SEL_32             ((uint64_t)(((uint64_t)1)<<32))  /*!< Pin 32 selected */
-#define GPIO_SEL_33             ((uint64_t)(((uint64_t)1)<<33))  /*!< Pin 33 selected */
-#define GPIO_SEL_34             ((uint64_t)(((uint64_t)1)<<34))  /*!< Pin 34 selected */
-#define GPIO_SEL_35             ((uint64_t)(((uint64_t)1)<<35))  /*!< Pin 35 selected */
-#define GPIO_SEL_36             ((uint64_t)(((uint64_t)1)<<36))  /*!< Pin 36 selected */
-#define GPIO_SEL_37             ((uint64_t)(((uint64_t)1)<<37))  /*!< Pin 37 selected */
-#define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
-#define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
-
-#define GPIO_PIN_REG_0          IO_MUX_GPIO0_REG
-#define GPIO_PIN_REG_1          IO_MUX_GPIO1_REG
-#define GPIO_PIN_REG_2          IO_MUX_GPIO2_REG
-#define GPIO_PIN_REG_3          IO_MUX_GPIO3_REG
-#define GPIO_PIN_REG_4          IO_MUX_GPIO4_REG
-#define GPIO_PIN_REG_5          IO_MUX_GPIO5_REG
-#define GPIO_PIN_REG_6          IO_MUX_GPIO6_REG
-#define GPIO_PIN_REG_7          IO_MUX_GPIO7_REG
-#define GPIO_PIN_REG_8          IO_MUX_GPIO8_REG
-#define GPIO_PIN_REG_9          IO_MUX_GPIO9_REG
-#define GPIO_PIN_REG_10         IO_MUX_GPIO10_REG
-#define GPIO_PIN_REG_11         IO_MUX_GPIO11_REG
-#define GPIO_PIN_REG_12         IO_MUX_GPIO12_REG
-#define GPIO_PIN_REG_13         IO_MUX_GPIO13_REG
-#define GPIO_PIN_REG_14         IO_MUX_GPIO14_REG
-#define GPIO_PIN_REG_15         IO_MUX_GPIO15_REG
-#define GPIO_PIN_REG_16         IO_MUX_GPIO16_REG
-#define GPIO_PIN_REG_17         IO_MUX_GPIO17_REG
-#define GPIO_PIN_REG_18         IO_MUX_GPIO18_REG
-#define GPIO_PIN_REG_19         IO_MUX_GPIO19_REG
-#define GPIO_PIN_REG_20         IO_MUX_GPIO20_REG
-#define GPIO_PIN_REG_21         IO_MUX_GPIO21_REG
-#define GPIO_PIN_REG_22         IO_MUX_GPIO22_REG
-#define GPIO_PIN_REG_23         IO_MUX_GPIO23_REG
-#define GPIO_PIN_REG_25         IO_MUX_GPIO25_REG
-#define GPIO_PIN_REG_26         IO_MUX_GPIO26_REG
-#define GPIO_PIN_REG_27         IO_MUX_GPIO27_REG
-#define GPIO_PIN_REG_32         IO_MUX_GPIO32_REG
-#define GPIO_PIN_REG_33         IO_MUX_GPIO33_REG
-#define GPIO_PIN_REG_34         IO_MUX_GPIO34_REG
-#define GPIO_PIN_REG_35         IO_MUX_GPIO35_REG
-#define GPIO_PIN_REG_36         IO_MUX_GPIO36_REG
-#define GPIO_PIN_REG_37         IO_MUX_GPIO37_REG
-#define GPIO_PIN_REG_38         IO_MUX_GPIO38_REG
-#define GPIO_PIN_REG_39         IO_MUX_GPIO39_REG
-
-#define GPIO_APP_CPU_INTR_ENA      (BIT(0))
-#define GPIO_APP_CPU_NMI_INTR_ENA  (BIT(1))
-#define GPIO_PRO_CPU_INTR_ENA      (BIT(2))
-#define GPIO_PRO_CPU_NMI_INTR_ENA  (BIT(3))
-#define GPIO_SDIO_EXT_INTR_ENA     (BIT(4))
-
-#define GPIO_MODE_DEF_DISABLE         (0)
-#define GPIO_MODE_DEF_INPUT           (BIT0)
-#define GPIO_MODE_DEF_OUTPUT          (BIT1)
-#define GPIO_MODE_DEF_OD              (BIT2)
-
-
-/** @endcond */
-
-#define GPIO_IS_VALID_GPIO(gpio_num)      ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0))   /*!< Check whether it is a valid GPIO number */
-#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)      ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34))         /*!< Check whether it can be a valid GPIO number of output mode */
-
-typedef enum {
-    GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
-    GPIO_NUM_1 = 1,     /*!< GPIO1, input and output */
-    GPIO_NUM_2 = 2,     /*!< GPIO2, input and output
-                             @note There are more enumerations like that
-                             up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31.
-                             They are not shown here to reduce redundant information.
-                             @note GPIO34..39 are input mode only. */
-/** @cond */
-    GPIO_NUM_3 = 3,     /*!< GPIO3, input and output */
-    GPIO_NUM_4 = 4,     /*!< GPIO4, input and output */
-    GPIO_NUM_5 = 5,     /*!< GPIO5, input and output */
-    GPIO_NUM_6 = 6,     /*!< GPIO6, input and output */
-    GPIO_NUM_7 = 7,     /*!< GPIO7, input and output */
-    GPIO_NUM_8 = 8,     /*!< GPIO8, input and output */
-    GPIO_NUM_9 = 9,     /*!< GPIO9, input and output */
-    GPIO_NUM_10 = 10,   /*!< GPIO10, input and output */
-    GPIO_NUM_11 = 11,   /*!< GPIO11, input and output */
-    GPIO_NUM_12 = 12,   /*!< GPIO12, input and output */
-    GPIO_NUM_13 = 13,   /*!< GPIO13, input and output */
-    GPIO_NUM_14 = 14,   /*!< GPIO14, input and output */
-    GPIO_NUM_15 = 15,   /*!< GPIO15, input and output */
-    GPIO_NUM_16 = 16,   /*!< GPIO16, input and output */
-    GPIO_NUM_17 = 17,   /*!< GPIO17, input and output */
-    GPIO_NUM_18 = 18,   /*!< GPIO18, input and output */
-    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
-
-    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
-    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
-    GPIO_NUM_23 = 23,   /*!< GPIO23, input and output */
-
-    GPIO_NUM_25 = 25,   /*!< GPIO25, input and output */
-    GPIO_NUM_26 = 26,   /*!< GPIO26, input and output */
-    GPIO_NUM_27 = 27,   /*!< GPIO27, input and output */
-
-    GPIO_NUM_32 = 32,   /*!< GPIO32, input and output */
-    GPIO_NUM_33 = 33,   /*!< GPIO33, input and output */
-    GPIO_NUM_34 = 34,   /*!< GPIO34, input mode only */
-    GPIO_NUM_35 = 35,   /*!< GPIO35, input mode only */
-    GPIO_NUM_36 = 36,   /*!< GPIO36, input mode only */
-    GPIO_NUM_37 = 37,   /*!< GPIO37, input mode only */
-    GPIO_NUM_38 = 38,   /*!< GPIO38, input mode only */
-    GPIO_NUM_39 = 39,   /*!< GPIO39, input mode only */
-    GPIO_NUM_MAX = 40,
-/** @endcond */
-} gpio_num_t;
-
-typedef enum {
-    GPIO_INTR_DISABLE = 0,     /*!< Disable GPIO interrupt                             */
-    GPIO_INTR_POSEDGE = 1,     /*!< GPIO interrupt type : rising edge                  */
-    GPIO_INTR_NEGEDGE = 2,     /*!< GPIO interrupt type : falling edge                 */
-    GPIO_INTR_ANYEDGE = 3,     /*!< GPIO interrupt type : both rising and falling edge */
-    GPIO_INTR_LOW_LEVEL = 4,   /*!< GPIO interrupt type : input low level trigger      */
-    GPIO_INTR_HIGH_LEVEL = 5,  /*!< GPIO interrupt type : input high level trigger     */
-    GPIO_INTR_MAX,
-} gpio_int_type_t;
-
-typedef enum {
-    GPIO_MODE_DISABLE = GPIO_MODE_DEF_DISABLE,                                        /*!< GPIO mode : disable input and output             */
-    GPIO_MODE_INPUT = GPIO_MODE_DEF_INPUT,                                                         /*!< GPIO mode : input only                           */
-    GPIO_MODE_OUTPUT = GPIO_MODE_DEF_OUTPUT,                                                       /*!< GPIO mode : output only mode                     */
-    GPIO_MODE_OUTPUT_OD = ((GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)),                             /*!< GPIO mode : output only with open-drain mode     */
-    GPIO_MODE_INPUT_OUTPUT_OD = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)), /*!< GPIO mode : output and input with open-drain mode*/
-    GPIO_MODE_INPUT_OUTPUT = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)),                       /*!< GPIO mode : output and input mode                */
-} gpio_mode_t;
-
-typedef enum {
-    GPIO_PULLUP_DISABLE = 0x0,     /*!< Disable GPIO pull-up resistor */
-    GPIO_PULLUP_ENABLE = 0x1,      /*!< Enable GPIO pull-up resistor */
-} gpio_pullup_t;
-
-typedef enum {
-    GPIO_PULLDOWN_DISABLE = 0x0,   /*!< Disable GPIO pull-down resistor */
-    GPIO_PULLDOWN_ENABLE = 0x1,    /*!< Enable GPIO pull-down resistor  */
-} gpio_pulldown_t;
-
-/**
- * @brief Configuration parameters of GPIO pad for gpio_config function
- */
-typedef struct {
-    uint64_t pin_bit_mask;          /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */
-    gpio_mode_t mode;               /*!< GPIO mode: set input/output mode                     */
-    gpio_pullup_t pull_up_en;       /*!< GPIO pull-up                                         */
-    gpio_pulldown_t pull_down_en;   /*!< GPIO pull-down                                       */
-    gpio_int_type_t intr_type;      /*!< GPIO interrupt type                                  */
-} gpio_config_t;
-
-typedef enum {
-    GPIO_PULLUP_ONLY,               /*!< Pad pull up            */
-    GPIO_PULLDOWN_ONLY,             /*!< Pad pull down          */
-    GPIO_PULLUP_PULLDOWN,           /*!< Pad pull up + pull down*/
-    GPIO_FLOATING,                  /*!< Pad floating           */
-} gpio_pull_mode_t;
-
-typedef enum {
-    GPIO_DRIVE_CAP_0       = 0,    /*!< Pad drive capability: weak          */
-    GPIO_DRIVE_CAP_1       = 1,    /*!< Pad drive capability: stronger      */
-    GPIO_DRIVE_CAP_2       = 2,    /*!< Pad drive capability: default value */
-    GPIO_DRIVE_CAP_DEFAULT = 2,    /*!< Pad drive capability: default value */
-    GPIO_DRIVE_CAP_3       = 3,    /*!< Pad drive capability: strongest     */
-    GPIO_DRIVE_CAP_MAX,
-} gpio_drive_cap_t;
-
-typedef void (*gpio_isr_t)(void*);
-typedef intr_handle_t gpio_isr_handle_t;
-
-/**
- * @brief GPIO common configuration
- *
- *        Configure GPIO's Mode,pull-up,PullDown,IntrType
- *
- * @param  pGPIOConfig Pointer to GPIO configure struct
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *
- */
-esp_err_t gpio_config(const gpio_config_t *pGPIOConfig);
-
-/**
- * @brief Reset an gpio to default state (select gpio function, enable pullup and disable input and output).
- *
- * @param gpio_num GPIO number.
- *
- * @note This function also configures the IOMUX for this pin to the GPIO
- *       function, and disconnects any other peripheral output configured via GPIO
- *       Matrix.
- *
- * @return Always return ESP_OK.
- */
-esp_err_t gpio_reset_pin(gpio_num_t gpio_num);
-
-/**
- * @brief  GPIO set interrupt trigger type
- *
- * @param  gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);
- * @param  intr_type Interrupt type, select from gpio_int_type_t
- *
- * @return
- *     - ESP_OK  Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *
- */
-esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type);
-
-/**
- * @brief  Enable GPIO module interrupt signal
- *
- * @note Please do not use the interrupt of GPIO36 and GPIO39 when using ADC.
- *       Please refer to the comments of `adc1_get_raw`.
- *       Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue.
- *
- * @param  gpio_num GPIO number. If you want to enable an interrupt on e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *
- */
-esp_err_t gpio_intr_enable(gpio_num_t gpio_num);
-
-/**
- * @brief  Disable GPIO module interrupt signal
- *
- * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *
- */
-esp_err_t gpio_intr_disable(gpio_num_t gpio_num);
-
-/**
- * @brief  GPIO set output level
- *
- * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
- * @param  level Output level. 0: low ; 1: high
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO number error
- *
- */
-esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level);
-
-/**
- * @brief  GPIO get input level
- *
- * @warning If the pad is not configured for input (or input and output) the returned value is always 0.
- *
- * @param  gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
- *
- * @return
- *     - 0 the GPIO input level is 0
- *     - 1 the GPIO input level is 1
- *
- */
-int gpio_get_level(gpio_num_t gpio_num);
-
-/**
- * @brief	 GPIO set direction
- *
- * Configure GPIO direction,such as output_only,input_only,output_and_input
- *
- * @param  gpio_num  Configure GPIO pins number, it should be GPIO number. If you want to set direction of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
- * @param  mode GPIO direction
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO error
- *
- */
-esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode);
-
-/**
- * @brief  Configure GPIO pull-up/pull-down resistors
- *
- * Only pins that support both input & output have integrated pull-up and pull-down resistors. Input-only GPIOs 34-39 do not.
- *
- * @param  gpio_num GPIO number. If you want to set pull up or down mode for e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
- * @param  pull GPIO pull up/down mode.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG : Parameter error
- *
- */
-esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull);
-
-/**
- * @brief Enable GPIO wake-up function.
- *
- * @param gpio_num GPIO number.
- *
- * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type);
-
-/**
- * @brief Disable GPIO wake-up function.
- *
- * @param gpio_num GPIO number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num);
-
-/**
- * @brief   Register GPIO interrupt handler, the handler is an ISR.
- *          The handler will be attached to the same CPU core that this function is running on.
- *
- * This ISR function is called whenever any GPIO interrupt occurs. See
- * the alternative gpio_install_isr_service() and
- * gpio_isr_handler_add() API in order to have the driver support
- * per-GPIO ISRs.
- *
- * @param  fn  Interrupt handler function.
- * @param  intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
- * @param  arg  Parameter for handler function
- * @param  handle Pointer to return handle. If non-NULL, a handle for the interrupt will be returned here.
- *
- * \verbatim embed:rst:leading-asterisk
- * To disable or remove the ISR, pass the returned handle to the :doc:`interrupt allocation functions </api-reference/system/intr_alloc>`.
- * \endverbatim
- *
- * @return
- *     - ESP_OK Success ;
- *     - ESP_ERR_INVALID_ARG GPIO error
- *     - ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
- */
-esp_err_t gpio_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, gpio_isr_handle_t *handle);
-
-/**
-  * @brief Enable pull-up on GPIO.
-  *
-  * @param gpio_num GPIO number
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_INVALID_ARG Parameter error
-  */
-esp_err_t gpio_pullup_en(gpio_num_t gpio_num);
-
-/**
-  * @brief Disable pull-up on GPIO.
-  *
-  * @param gpio_num GPIO number
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_INVALID_ARG Parameter error
-  */
-esp_err_t gpio_pullup_dis(gpio_num_t gpio_num);
-
-/**
-  * @brief Enable pull-down on GPIO.
-  *
-  * @param gpio_num GPIO number
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_INVALID_ARG Parameter error
-  */
-esp_err_t gpio_pulldown_en(gpio_num_t gpio_num);
-
-/**
-  * @brief Disable pull-down on GPIO.
-  *
-  * @param gpio_num GPIO number
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_INVALID_ARG Parameter error
-  */
-esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num);
-
-/**
-  * @brief Install the driver's GPIO ISR handler service, which allows per-pin GPIO interrupt handlers.
-  *
-  * This function is incompatible with gpio_isr_register() - if that function is used, a single global ISR is registered for all GPIO interrupts. If this function is used, the ISR service provides a global GPIO ISR and individual pin handlers are registered via the gpio_isr_handler_add() function.
-  *
-  * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
-  *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_NO_MEM No memory to install this service
-  *     - ESP_ERR_INVALID_STATE ISR service already installed.
-  *     - ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
-  *     - ESP_ERR_INVALID_ARG GPIO error
-  */
-esp_err_t gpio_install_isr_service(int intr_alloc_flags);
-
-/**
-  * @brief Uninstall the driver's GPIO ISR service, freeing related resources.
-  */
-void gpio_uninstall_isr_service();
-
-/**
-  * @brief Add ISR handler for the corresponding GPIO pin.
-  *
-  * Call this function after using gpio_install_isr_service() to
-  * install the driver's GPIO ISR handler service.
-  *
-  * The pin ISR handlers no longer need to be declared with IRAM_ATTR,
-  * unless you pass the ESP_INTR_FLAG_IRAM flag when allocating the
-  * ISR in gpio_install_isr_service().
-  *
-  * This ISR handler will be called from an ISR. So there is a stack
-  * size limit (configurable as "ISR stack size" in menuconfig). This
-  * limit is smaller compared to a global GPIO interrupt handler due
-  * to the additional level of indirection.
-  *
-  * @param gpio_num GPIO number
-  * @param isr_handler ISR handler function for the corresponding GPIO number.
-  * @param args parameter for ISR handler.
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_INVALID_STATE Wrong state, the ISR service has not been initialized.
-  *     - ESP_ERR_INVALID_ARG Parameter error
-  */
-esp_err_t gpio_isr_handler_add(gpio_num_t gpio_num, gpio_isr_t isr_handler, void* args);
-
-/**
-  * @brief Remove ISR handler for the corresponding GPIO pin.
-  *
-  * @param gpio_num GPIO number
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_INVALID_STATE Wrong state, the ISR service has not been initialized.
-  *     - ESP_ERR_INVALID_ARG Parameter error
-  */
-esp_err_t gpio_isr_handler_remove(gpio_num_t gpio_num);
-
-/**
-  * @brief Set GPIO pad drive capability
-  *
-  * @param gpio_num GPIO number, only support output GPIOs
-  * @param strength Drive capability of the pad
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_INVALID_ARG Parameter error
-  */
-esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength);
-
-/**
-  * @brief Get GPIO pad drive capability
-  *
-  * @param gpio_num GPIO number, only support output GPIOs
-  * @param strength Pointer to accept drive capability of the pad
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_INVALID_ARG Parameter error
-  */
-esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength);
-
-/**
-  * @brief Enable gpio pad hold function.
-  *
-  * The gpio pad hold function works in both input and output modes, but must be output-capable gpios.
-  * If pad hold enabled:
-  *   in output mode: the output level of the pad will be force locked and can not be changed.
-  *   in input mode: the input value read will not change, regardless the changes of input signal.
-  *
-  * The state of digital gpio cannot be held during Deep-sleep, and it will resume the hold function
-  * when the chip wakes up from Deep-sleep. If the digital gpio also needs to be held during Deep-sleep,
-  * `gpio_deep_sleep_hold_en` should also be called.
-  *
-  * Power down or call gpio_hold_dis will disable this function.
-  *
-  * @param gpio_num GPIO number, only support output-capable GPIOs
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_NOT_SUPPORTED Not support pad hold function
-  */
-esp_err_t gpio_hold_en(gpio_num_t gpio_num);
-
-/**
-  * @brief Disable gpio pad hold function.
-  *
-  * When the chip is woken up from Deep-sleep, the gpio will be set to the default mode, so, the gpio will output
-  * the default level if this function is called. If you dont't want the level changes, the gpio should be configured to
-  * a known state before this function is called.
-  *  e.g.
-  *     If you hold gpio18 high during Deep-sleep, after the chip is woken up and `gpio_hold_dis` is called, 
-  *     gpio18 will output low level(because gpio18 is input mode by default). If you don't want this behavior,
-  *     you should configure gpio18 as output mode and set it to hight level before calling `gpio_hold_dis`.
-  *
-  * @param gpio_num GPIO number, only support output-capable GPIOs
-  *
-  * @return
-  *     - ESP_OK Success
-  *     - ESP_ERR_NOT_SUPPORTED Not support pad hold function
-  */
-esp_err_t gpio_hold_dis(gpio_num_t gpio_num);
-
-/**
-  * @brief Enable all digital gpio pad hold function during Deep-sleep.
-  *
-  * When the chip is in Deep-sleep mode, all digital gpio will hold the state before sleep, and when the chip is woken up,
-  * the status of digital gpio will not be held. Note that the pad hold feature only works when the chip is in Deep-sleep mode,
-  * when not in sleep mode, the digital gpio state can be changed even you have called this function.
-  *
-  * Power down or call gpio_hold_dis will disable this function, otherwise, the digital gpio hold feature works as long as the chip enter Deep-sleep.
-  */
-void gpio_deep_sleep_hold_en(void);
-
-/**
-  * @brief Disable all digital gpio pad hold function during Deep-sleep.
-  *
-  */
-void gpio_deep_sleep_hold_dis(void);
-
-/**
-  * @brief Set pad input to a peripheral signal through the IOMUX.
-  * @param gpio_num GPIO number of the pad.
-  * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
-  */
-void gpio_iomux_in(uint32_t gpio_num, uint32_t signal_idx);
-
-/**
-  * @brief Set peripheral output to an GPIO pad through the IOMUX.
-  * @param gpio_num gpio_num GPIO number of the pad.
-  * @param func The function number of the peripheral pin to output pin.
-  *        One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``.
-  * @param oen_inv True if the output enable needs to be inversed, otherwise False.
-  */
-void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DRIVER_GPIO_H_ */
diff --git a/tools/sdk/include/driver/driver/i2c.h b/tools/sdk/include/driver/driver/i2c.h
deleted file mode 100644
index feb1d78bd63..00000000000
--- a/tools/sdk/include/driver/driver/i2c.h
+++ /dev/null
@@ -1,579 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_I2C_H_
-#define _DRIVER_I2C_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include <esp_types.h>
-#include "esp_err.h"
-#include "esp_intr_alloc.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
-#include "freertos/task.h"
-#include "freertos/queue.h"
-#include "freertos/ringbuf.h"
-#include "driver/gpio.h"
-
-#define I2C_APB_CLK_FREQ  APB_CLK_FREQ /*!< I2C source clock is APB clock, 80MHz */
-#define I2C_FIFO_LEN   (32)  /*!< I2C hardware fifo length */
-typedef enum{
-    I2C_MODE_SLAVE = 0,   /*!< I2C slave mode */
-    I2C_MODE_MASTER,      /*!< I2C master mode */
-    I2C_MODE_MAX,
-}i2c_mode_t;
-
-typedef enum {
-    I2C_MASTER_WRITE = 0,   /*!< I2C write data */
-    I2C_MASTER_READ,        /*!< I2C read data */
-} i2c_rw_t;
-
-typedef enum {
-    I2C_DATA_MODE_MSB_FIRST = 0,  /*!< I2C data msb first */
-    I2C_DATA_MODE_LSB_FIRST = 1,  /*!< I2C data lsb first */
-    I2C_DATA_MODE_MAX
-} i2c_trans_mode_t;
-
-typedef enum{
-    I2C_CMD_RESTART = 0,   /*!<I2C restart command */
-    I2C_CMD_WRITE,         /*!<I2C write command */
-    I2C_CMD_READ,          /*!<I2C read command */
-    I2C_CMD_STOP,          /*!<I2C stop command */
-    I2C_CMD_END            /*!<I2C end command */
-}i2c_opmode_t;
-
-typedef enum{
-    I2C_NUM_0 = 0,  /*!< I2C port 0 */
-    I2C_NUM_1 ,     /*!< I2C port 1 */
-    I2C_NUM_MAX
-} i2c_port_t;
-
-typedef enum {
-    I2C_ADDR_BIT_7 = 0,    /*!< I2C 7bit address for slave mode */
-    I2C_ADDR_BIT_10,       /*!< I2C 10bit address for slave mode */
-    I2C_ADDR_BIT_MAX,
-} i2c_addr_mode_t;
-
-typedef enum {
-    I2C_MASTER_ACK = 0x0,        /*!< I2C ack for each byte read */
-    I2C_MASTER_NACK = 0x1,       /*!< I2C nack for each byte read */
-    I2C_MASTER_LAST_NACK = 0x2,   /*!< I2C nack for the last byte*/
-    I2C_MASTER_ACK_MAX,
-} i2c_ack_type_t;
-
-/**
- * @brief I2C initialization parameters
- */
-typedef struct{
-    i2c_mode_t mode;       /*!< I2C mode */
-    gpio_num_t sda_io_num;        /*!< GPIO number for I2C sda signal */
-    gpio_pullup_t sda_pullup_en;  /*!< Internal GPIO pull mode for I2C sda signal*/
-    gpio_num_t scl_io_num;        /*!< GPIO number for I2C scl signal */
-    gpio_pullup_t scl_pullup_en;  /*!< Internal GPIO pull mode for I2C scl signal*/
-
-    union {
-        struct {
-            uint32_t clk_speed;     /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */
-        } master;
-        struct {
-            uint8_t addr_10bit_en;  /*!< I2C 10bit address mode enable for slave mode */
-            uint16_t slave_addr;    /*!< I2C address for slave mode */
-        } slave;
-
-    };
-}i2c_config_t;
-
-typedef void* i2c_cmd_handle_t;    /*!< I2C command handle  */
-
-/**
- * @brief I2C driver install
- *
- * @param i2c_num I2C port number
- * @param mode I2C mode( master or slave )
- * @param slv_rx_buf_len receiving buffer size for slave mode
- *        @note
- *        Only slave mode will use this value, driver will ignore this value in master mode.
- * @param slv_tx_buf_len sending buffer size for slave mode
- *        @note
- *        Only slave mode will use this value, driver will ignore this value in master mode.
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
- *        @note
- *        In master mode, if the cache is likely to be disabled(such as write flash) and the slave is time-sensitive,
- *        `ESP_INTR_FLAG_IRAM` is suggested to be used. In this case, please use the memory allocated from internal RAM in i2c read and write function,
- *        because we can not access the psram(if psram is enabled) in interrupt handle function when cache is disabled.
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_FAIL Driver install error
- */
-esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_buf_len, size_t slv_tx_buf_len, int intr_alloc_flags);
-
-/**
- * @brief I2C driver delete
- *
- * @param i2c_num I2C port number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_driver_delete(i2c_port_t i2c_num);
-
-/**
- * @brief I2C parameter initialization
- *
- * @param i2c_num I2C port number
- * @param i2c_conf pointer to I2C parameter settings
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t* i2c_conf);
-
-/**
- * @brief reset I2C tx hardware fifo
- *
- * @param i2c_num I2C port number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_reset_tx_fifo(i2c_port_t i2c_num);
-
-/**
- * @brief reset I2C rx fifo
- *
- * @param i2c_num I2C port number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_reset_rx_fifo(i2c_port_t i2c_num);
-
-/**
- * @brief I2C isr handler register
- *
- * @param i2c_num I2C port number
- * @param fn isr handler function
- * @param arg parameter for isr handler function
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
- * @param handle handle return from esp_intr_alloc.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_isr_register(i2c_port_t i2c_num, void (*fn)(void*), void * arg, int intr_alloc_flags, intr_handle_t *handle);
-
-/**
- * @brief to delete and free I2C isr.
- *
- * @param handle handle of isr.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_isr_free(intr_handle_t handle);
-
-/**
- * @brief Configure GPIO signal for I2C sck and sda
- *
- * @param i2c_num I2C port number
- * @param sda_io_num GPIO number for I2C sda signal
- * @param scl_io_num GPIO number for I2C scl signal
- * @param sda_pullup_en Whether to enable the internal pullup for sda pin
- * @param scl_pullup_en Whether to enable the internal pullup for scl pin
- * @param mode I2C mode
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_set_pin(i2c_port_t i2c_num, int sda_io_num, int scl_io_num,
-                      gpio_pullup_t sda_pullup_en, gpio_pullup_t scl_pullup_en, i2c_mode_t mode);
-
-/**
- * @brief Create and init I2C command link
- *        @note
- *        Before we build I2C command link, we need to call i2c_cmd_link_create() to create
- *        a command link.
- *        After we finish sending the commands, we need to call i2c_cmd_link_delete() to
- *        release and return the resources.
- *
- * @return i2c command link handler
- */
-i2c_cmd_handle_t i2c_cmd_link_create();
-
-/**
- * @brief Free I2C command link
- *        @note
- *        Before we build I2C command link, we need to call i2c_cmd_link_create() to create
- *        a command link.
- *        After we finish sending the commands, we need to call i2c_cmd_link_delete() to
- *        release and return the resources.
- *
- * @param cmd_handle I2C command handle
- */
-void i2c_cmd_link_delete(i2c_cmd_handle_t cmd_handle);
-
-/**
- * @brief Queue command for I2C master to generate a start signal
- *        @note
- *        Only call this function in I2C master mode
- *        Call i2c_master_cmd_begin() to send all queued commands
- *
- * @param cmd_handle I2C cmd link
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_master_start(i2c_cmd_handle_t cmd_handle);
-
-/**
- * @brief Queue command for I2C master to write one byte to I2C bus
- *        @note
- *        Only call this function in I2C master mode
- *        Call i2c_master_cmd_begin() to send all queued commands
- *
- * @param cmd_handle I2C cmd link
- * @param data I2C one byte command to write to bus
- * @param ack_en enable ack check for master
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_master_write_byte(i2c_cmd_handle_t cmd_handle, uint8_t data, bool ack_en);
-
-/**
- * @brief Queue command for I2C master to write buffer to I2C bus
- *        @note
- *        Only call this function in I2C master mode
- *        Call i2c_master_cmd_begin() to send all queued commands
- *
- * @param cmd_handle I2C cmd link
- * @param data data to send
- *        @note
- *        If the psram is enabled and intr_flag is `ESP_INTR_FLAG_IRAM`, please use the memory allocated from internal RAM.
- * @param data_len data length
- * @param ack_en enable ack check for master
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_master_write(i2c_cmd_handle_t cmd_handle, uint8_t* data, size_t data_len, bool ack_en);
-
-/**
- * @brief Queue command for I2C master to read one byte from I2C bus
- *        @note
- *        Only call this function in I2C master mode
- *        Call i2c_master_cmd_begin() to send all queued commands
- *
- * @param cmd_handle I2C cmd link
- * @param data pointer accept the data byte
- *        @note
- *        If the psram is enabled and intr_flag is `ESP_INTR_FLAG_IRAM`, please use the memory allocated from internal RAM.
- * @param ack ack value for read command
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_master_read_byte(i2c_cmd_handle_t cmd_handle, uint8_t* data, i2c_ack_type_t ack);
-
-/**
- * @brief Queue command for I2C master to read data from I2C bus
- *        @note
- *        Only call this function in I2C master mode
- *        Call i2c_master_cmd_begin() to send all queued commands
- *
- * @param cmd_handle I2C cmd link
- * @param data data buffer to accept the data from bus
- *        @note
- *        If the psram is enabled and intr_flag is `ESP_INTR_FLAG_IRAM`, please use the memory allocated from internal RAM.
- * @param data_len read data length
- * @param ack ack value for read command
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_master_read(i2c_cmd_handle_t cmd_handle, uint8_t* data, size_t data_len, i2c_ack_type_t ack);
-
-/**
- * @brief Queue command for I2C master to generate a stop signal
- *        @note
- *        Only call this function in I2C master mode
- *        Call i2c_master_cmd_begin() to send all queued commands
- *
- * @param cmd_handle I2C cmd link
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_master_stop(i2c_cmd_handle_t cmd_handle);
-
-/**
- * @brief I2C master send queued commands.
- *        This function will trigger sending all queued commands.
- *        The task will be blocked until all the commands have been sent out.
- *        The I2C APIs are not thread-safe, if you want to use one I2C port in different tasks,
- *        you need to take care of the multi-thread issue.
- *        @note
- *        Only call this function in I2C master mode
- *
- * @param i2c_num I2C port number
- * @param cmd_handle I2C command handler
- * @param ticks_to_wait maximum wait ticks.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_FAIL Sending command error, slave doesn't ACK the transfer.
- *     - ESP_ERR_INVALID_STATE I2C driver not installed or not in master mode.
- *     - ESP_ERR_TIMEOUT Operation timeout because the bus is busy.
- */
-esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle, TickType_t ticks_to_wait);
-
-/**
- * @brief I2C slave write data to internal ringbuffer, when tx fifo empty, isr will fill the hardware
- *        fifo from the internal ringbuffer
- *        @note
- *        Only call this function in I2C slave mode
- *
- * @param i2c_num I2C port number
- * @param data data pointer to write into internal buffer
- * @param size data size
- * @param ticks_to_wait Maximum waiting ticks
- *
- * @return
- *     - ESP_FAIL(-1) Parameter error
- *     - Others(>=0) The number of data bytes that pushed to the I2C slave buffer.
- */
-int i2c_slave_write_buffer(i2c_port_t i2c_num, uint8_t* data, int size, TickType_t ticks_to_wait);
-
-/**
- * @brief I2C slave read data from internal buffer. When I2C slave receive data, isr will copy received data
- *        from hardware rx fifo to internal ringbuffer. Then users can read from internal ringbuffer.
- *        @note
- *        Only call this function in I2C slave mode
- *
- * @param i2c_num I2C port number
- * @param data data pointer to write into internal buffer
- * @param max_size Maximum data size to read
- * @param ticks_to_wait Maximum waiting ticks
- *
- * @return
- *     - ESP_FAIL(-1) Parameter error
- *     - Others(>=0) The number of data bytes that read from I2C slave buffer.
- */
-int i2c_slave_read_buffer(i2c_port_t i2c_num, uint8_t* data, size_t max_size, TickType_t ticks_to_wait);
-
-/**
- * @brief set I2C master clock period
- *
- * @param i2c_num I2C port number
- * @param high_period clock cycle number during SCL is high level, high_period is a 14 bit value
- * @param low_period clock cycle number during SCL is low level, low_period is a 14 bit value
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_set_period(i2c_port_t i2c_num, int high_period, int low_period);
-
-/**
- * @brief get I2C master clock period
- *
- * @param i2c_num I2C port number
- * @param high_period pointer to get clock cycle number during SCL is high level, will get a 14 bit value
- * @param low_period pointer to get clock cycle number during SCL is low level, will get a 14 bit value
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_get_period(i2c_port_t i2c_num, int* high_period, int* low_period);
-
-/**
- * @brief enable hardware filter on I2C bus
- *        Sometimes the I2C bus is disturbed by high frequency noise(about 20ns), or the rising edge of
- *        the SCL clock is very slow, these may cause the master state machine broken. enable hardware
- *        filter can filter out high frequency interference and make the master more stable.
- *        @note
- *        Enable filter will slow the SCL clock.
- *
- * @param i2c_num I2C port number
- * @param cyc_num the APB cycles need to be filtered(0<= cyc_num <=7).
- *        When the period of a pulse is less than cyc_num * APB_cycle, the I2C controller will ignore this pulse.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_filter_enable(i2c_port_t i2c_num, uint8_t cyc_num);
-
-/**
- * @brief disable filter on I2C bus
- *
- * @param i2c_num I2C port number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_filter_disable(i2c_port_t i2c_num);
-
-/**
- * @brief set I2C master start signal timing
- *
- * @param i2c_num I2C port number
- * @param setup_time clock number between the falling-edge of SDA and rising-edge of SCL for start mark, it's a 10-bit value.
- * @param hold_time clock num between the falling-edge of SDA and falling-edge of SCL for start mark, it's a 10-bit value.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_set_start_timing(i2c_port_t i2c_num, int setup_time, int hold_time);
-
-/**
- * @brief get I2C master start signal timing
- *
- * @param i2c_num I2C port number
- * @param setup_time pointer to get setup time
- * @param hold_time pointer to get hold time
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_get_start_timing(i2c_port_t i2c_num, int* setup_time, int* hold_time);
-
-/**
- * @brief set I2C master stop signal timing
- *
- * @param i2c_num I2C port number
- * @param setup_time clock num between the rising-edge of SCL and the rising-edge of SDA, it's a 10-bit value.
- * @param hold_time clock number after the STOP bit's rising-edge, it's a 14-bit value.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_set_stop_timing(i2c_port_t i2c_num, int setup_time, int hold_time);
-
-/**
- * @brief get I2C master stop signal timing
- *
- * @param i2c_num I2C port number
- * @param setup_time pointer to get setup time.
- * @param hold_time pointer to get hold time.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_get_stop_timing(i2c_port_t i2c_num, int* setup_time, int* hold_time);
-
-/**
- * @brief set I2C data signal timing
- *
- * @param i2c_num I2C port number
- * @param sample_time clock number I2C used to sample data on SDA after the rising-edge of SCL, it's a 10-bit value
- * @param hold_time clock number I2C used to hold the data after the falling-edge of SCL, it's a 10-bit value
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_set_data_timing(i2c_port_t i2c_num, int sample_time, int hold_time);
-
-/**
- * @brief get I2C data signal timing
- *
- * @param i2c_num I2C port number
- * @param sample_time pointer to get sample time
- * @param hold_time pointer to get hold time
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_get_data_timing(i2c_port_t i2c_num, int* sample_time, int* hold_time);
-
-/**
- * @brief set I2C timeout value
- * @param i2c_num I2C port number
- * @param timeout timeout value for I2C bus (unit: APB 80Mhz clock cycle)
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_set_timeout(i2c_port_t i2c_num, int timeout);
-
-/**
- * @brief get I2C timeout value
- * @param i2c_num I2C port number
- * @param timeout pointer to get timeout value
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_get_timeout(i2c_port_t i2c_num, int* timeout);
-/**
- * @brief set I2C data transfer mode
- *
- * @param i2c_num I2C port number
- * @param tx_trans_mode I2C sending data mode
- * @param rx_trans_mode I2C receving data mode
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_set_data_mode(i2c_port_t i2c_num, i2c_trans_mode_t tx_trans_mode, i2c_trans_mode_t rx_trans_mode);
-
-/**
- * @brief get I2C data transfer mode
- *
- * @param i2c_num I2C port number
- * @param tx_trans_mode pointer to get I2C sending data mode
- * @param rx_trans_mode pointer to get I2C receiving data mode
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2c_get_data_mode(i2c_port_t i2c_num, i2c_trans_mode_t *tx_trans_mode, i2c_trans_mode_t *rx_trans_mode);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*_DRIVER_I2C_H_*/
diff --git a/tools/sdk/include/driver/driver/i2s.h b/tools/sdk/include/driver/driver/i2s.h
deleted file mode 100644
index 6179ec3c15f..00000000000
--- a/tools/sdk/include/driver/driver/i2s.h
+++ /dev/null
@@ -1,555 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_I2S_H_
-#define _DRIVER_I2S_H_
-#include "esp_err.h"
-#include <esp_types.h>
-#include "soc/gpio_reg.h"
-#include "soc/soc.h"
-#include "soc/i2s_struct.h"
-#include "soc/i2s_reg.h"
-#include "soc/rtc_io_reg.h"
-#include "soc/io_mux_reg.h"
-#include "rom/gpio.h"
-#include "esp_attr.h"
-#include "esp_intr_alloc.h"
-#include "driver/periph_ctrl.h"
-#include "driver/adc.h"
-#include "freertos/semphr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief I2S bit width per sample.
- *
- */
-typedef enum {
-    I2S_BITS_PER_SAMPLE_8BIT    = 8,        /*!< I2S bits per sample: 8-bits*/
-    I2S_BITS_PER_SAMPLE_16BIT   = 16,       /*!< I2S bits per sample: 16-bits*/
-    I2S_BITS_PER_SAMPLE_24BIT   = 24,       /*!< I2S bits per sample: 24-bits*/
-    I2S_BITS_PER_SAMPLE_32BIT   = 32,       /*!< I2S bits per sample: 32-bits*/
-} i2s_bits_per_sample_t;
-
-/**
- * @brief I2S channel.
- *
- */
-typedef enum {
-    I2S_CHANNEL_MONO        = 1,            /*!< I2S 1 channel (mono)*/
-    I2S_CHANNEL_STEREO      = 2             /*!< I2S 2 channel (stereo)*/
-} i2s_channel_t;
-
-/**
- * @brief I2S communication standard format
- *
- */
-typedef enum {
-    I2S_COMM_FORMAT_I2S         = 0x01, /*!< I2S communication format I2S*/
-    I2S_COMM_FORMAT_I2S_MSB     = 0x02, /*!< I2S format MSB*/
-    I2S_COMM_FORMAT_I2S_LSB     = 0x04, /*!< I2S format LSB*/
-    I2S_COMM_FORMAT_PCM         = 0x08, /*!< I2S communication format PCM*/
-    I2S_COMM_FORMAT_PCM_SHORT   = 0x10, /*!< PCM Short*/
-    I2S_COMM_FORMAT_PCM_LONG    = 0x20, /*!< PCM Long*/
-} i2s_comm_format_t;
-
-
-/**
- * @brief I2S channel format type
- */
-typedef enum {
-    I2S_CHANNEL_FMT_RIGHT_LEFT = 0x00,
-    I2S_CHANNEL_FMT_ALL_RIGHT,
-    I2S_CHANNEL_FMT_ALL_LEFT,
-    I2S_CHANNEL_FMT_ONLY_RIGHT,
-    I2S_CHANNEL_FMT_ONLY_LEFT,
-} i2s_channel_fmt_t;
-
-/**
- * @brief PDM sample rate ratio, measured in Hz.
- *
- */
-typedef enum {
-    PDM_SAMPLE_RATE_RATIO_64,
-    PDM_SAMPLE_RATE_RATIO_128,
-} pdm_sample_rate_ratio_t;
-
-/**
- * @brief PDM PCM convter enable/disable.
- *
- */
-typedef enum {
-    PDM_PCM_CONV_ENABLE,
-    PDM_PCM_CONV_DISABLE,
-} pdm_pcm_conv_t;
-
-
-/**
- * @brief I2S Peripheral, 0 & 1.
- *
- */
-typedef enum {
-    I2S_NUM_0 = 0x0,  /*!< I2S 0*/
-    I2S_NUM_1 = 0x1,  /*!< I2S 1*/
-    I2S_NUM_MAX,
-} i2s_port_t;
-
-/**
- * @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX
- *
- * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
- *
- */
-typedef enum {
-    I2S_MODE_MASTER = 1,
-    I2S_MODE_SLAVE = 2,
-    I2S_MODE_TX = 4,
-    I2S_MODE_RX = 8,
-    I2S_MODE_DAC_BUILT_IN = 16,       /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
-    I2S_MODE_ADC_BUILT_IN = 32,       /*!< Input I2S data from built-in ADC, each data can be 12-bit width at most*/
-    I2S_MODE_PDM = 64,
-} i2s_mode_t;
-
-
-
-/**
- * @brief I2S configuration parameters for i2s_param_config function
- *
- */
-typedef struct {
-    i2s_mode_t              mode;                   /*!< I2S work mode*/
-    int                     sample_rate;            /*!< I2S sample rate*/
-    i2s_bits_per_sample_t   bits_per_sample;        /*!< I2S bits per sample*/
-    i2s_channel_fmt_t       channel_format;         /*!< I2S channel format */
-    i2s_comm_format_t       communication_format;   /*!< I2S communication format */
-    int                     intr_alloc_flags;       /*!< Flags used to allocate the interrupt. One or multiple (ORred) ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info */
-    int                     dma_buf_count;          /*!< I2S DMA Buffer Count */
-    int                     dma_buf_len;            /*!< I2S DMA Buffer Length */
-    bool                    use_apll;              /*!< I2S using APLL as main I2S clock, enable it to get accurate clock */
-    bool                    tx_desc_auto_clear;     /*!< I2S auto clear tx descriptor if there is underflow condition (helps in avoiding noise in case of data unavailability) */
-    int                     fixed_mclk;             /*!< I2S using fixed MCLK output. If use_apll = true and fixed_mclk > 0, then the clock output for i2s is fixed and equal to the fixed_mclk value.*/
-} i2s_config_t;
-
-/**
- * @brief I2S event types
- *
- */
-typedef enum {
-    I2S_EVENT_DMA_ERROR,
-    I2S_EVENT_TX_DONE,     /*!< I2S DMA finish sent 1 buffer*/
-    I2S_EVENT_RX_DONE,     /*!< I2S DMA finish received 1 buffer*/
-    I2S_EVENT_MAX,         /*!< I2S event max index*/
-} i2s_event_type_t;
-
-/**
- * @brief I2S DAC mode for i2s_set_dac_mode.
- *
- * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
- */
-typedef enum {
-    I2S_DAC_CHANNEL_DISABLE  = 0,    /*!< Disable I2S built-in DAC signals*/
-    I2S_DAC_CHANNEL_RIGHT_EN = 1,    /*!< Enable I2S built-in DAC right channel, maps to DAC channel 1 on GPIO25*/
-    I2S_DAC_CHANNEL_LEFT_EN  = 2,    /*!< Enable I2S built-in DAC left  channel, maps to DAC channel 2 on GPIO26*/
-    I2S_DAC_CHANNEL_BOTH_EN  = 0x3,  /*!< Enable both of the I2S built-in DAC channels.*/
-    I2S_DAC_CHANNEL_MAX      = 0x4,  /*!< I2S built-in DAC mode max index*/
-} i2s_dac_mode_t;
-
-/**
- * @brief Event structure used in I2S event queue
- *
- */
-typedef struct {
-    i2s_event_type_t    type;   /*!< I2S event type */
-    size_t              size;   /*!< I2S data size for I2S_DATA event*/
-} i2s_event_t;
-
-#define I2S_PIN_NO_CHANGE (-1) /*!< Use in i2s_pin_config_t for pins which should not be changed */
-
-/**
- * @brief I2S pin number for i2s_set_pin
- *
- */
-typedef struct {
-    int bck_io_num;     /*!< BCK in out pin*/
-    int ws_io_num;      /*!< WS in out pin*/
-    int data_out_num;   /*!< DATA out pin*/
-    int data_in_num;    /*!< DATA in pin*/
-} i2s_pin_config_t;
-
-/**
- * @brief I2S PDM RX downsample mode
- */
-typedef enum {
-    I2S_PDM_DSR_8S = 0,  /*!< downsampling number is 8 for PDM RX mode*/
-    I2S_PDM_DSR_16S,     /*!< downsampling number is 16 for PDM RX mode*/
-    I2S_PDM_DSR_MAX,
-} i2s_pdm_dsr_t;
-
-typedef intr_handle_t i2s_isr_handle_t;
-/**
- * @brief Set I2S pin number
- *
- * @note
- * The I2S peripheral output signals can be connected to multiple GPIO pads.
- * However, the I2S peripheral input signal can only be connected to one GPIO pad.
- *
- * @param   i2s_num     I2S_NUM_0 or I2S_NUM_1
- *
- * @param   pin         I2S Pin structure, or NULL to set 2-channel 8-bit internal DAC pin configuration (GPIO25 & GPIO26)
- *
- * Inside the pin configuration structure, set I2S_PIN_NO_CHANGE for any pin where
- * the current configuration should not be changed.
- *
- * @note if *pin is set as NULL, this function will initialize both of the built-in DAC channels by default.
- *       if you don't want this to happen and you want to initialize only one of the DAC channels, you can call i2s_set_dac_mode instead.
- *
- * @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_FAIL            IO error
- */
-esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin);
-
-/**
- * @brief Set PDM mode down-sample rate
- *        In PDM RX mode, there would be 2 rounds of downsample process in hardware.
- *        In the first downsample process, the sampling number can be 16 or 8.
- *        In the second downsample process, the sampling number is fixed as 8.
- *        So the clock frequency in PDM RX mode would be (fpcm * 64) or (fpcm * 128) accordingly.
- * @param i2s_num I2S_NUM_0, I2S_NUM_1
- * @param dsr i2s RX down sample rate for PDM mode.
- *
- * @note After calling this function, it would call i2s_set_clk inside to update the clock frequency.
- *       Please call this function after I2S driver has been initialized.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NO_MEM      Out of memory
- */
-esp_err_t i2s_set_pdm_rx_down_sample(i2s_port_t i2s_num, i2s_pdm_dsr_t dsr);
-
-/**
- * @brief Set I2S dac mode, I2S built-in DAC is disabled by default
- *
- * @param dac_mode DAC mode configurations - see i2s_dac_mode_t
- *
- * @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip.
- *       If either of the built-in DAC channel are enabled, the other one can not
- *       be used as RTC DAC function at the same time.
- *
- * @return
- *     - ESP_OK               Success
- *     - ESP_ERR_INVALID_ARG  Parameter error
- */
-esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
-
-/**
- * @brief Install and start I2S driver.
- *
- * @param i2s_num         I2S_NUM_0, I2S_NUM_1
- *
- * @param i2s_config      I2S configurations - see i2s_config_t struct
- *
- * @param queue_size      I2S event queue size/depth.
- *
- * @param i2s_queue       I2S event queue handle, if set NULL, driver will not use an event queue.
- *
- * This function must be called before any I2S driver read/write operations.
- *
- * @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NO_MEM      Out of memory
- */
-esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, int queue_size, void* i2s_queue);
-
-/**
- * @brief Uninstall I2S driver.
- *
- * @param i2s_num  I2S_NUM_0, I2S_NUM_1
- *
- * @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2s_driver_uninstall(i2s_port_t i2s_num);
-
-/**
- * @brief Write data to I2S DMA transmit buffer.
- *
- * This function is deprecated. Use 'i2s_write' instead.
- * This definition will be removed in a future release.
- *
- * @return
- *     - The amount of bytes written, if timeout, the result will be less than the size passed in.
- *     - ESP_FAIL  Parameter error
- */
-int i2s_write_bytes(i2s_port_t i2s_num, const void *src, size_t size, TickType_t ticks_to_wait) __attribute__ ((deprecated));
-
-/**
- * @brief Write data to I2S DMA transmit buffer.
- *
- * @param i2s_num             I2S_NUM_0, I2S_NUM_1
- *
- * @param src                 Source address to write from
- *
- * @param size                Size of data in bytes
- *
- * @param[out] bytes_written  Number of bytes written, if timeout, the result will be less than the size passed in.
- *
- * @param ticks_to_wait       TX buffer wait timeout in RTOS ticks. If this
- * many ticks pass without space becoming available in the DMA
- * transmit buffer, then the function will return (note that if the
- * data is written to the DMA buffer in pieces, the overall operation
- * may still take longer than this timeout.) Pass portMAX_DELAY for no
- * timeout.
- *
- * @return
- *     - ESP_OK               Success
- *     - ESP_ERR_INVALID_ARG  Parameter error
- */
-esp_err_t i2s_write(i2s_port_t i2s_num, const void *src, size_t size, size_t *bytes_written, TickType_t ticks_to_wait);
-
-/**
- * @brief Write data to I2S DMA transmit buffer while expanding the number of bits per sample. For example, expanding 16-bit PCM to 32-bit PCM.
- *
- * @param i2s_num             I2S_NUM_0, I2S_NUM_1
- *
- * @param src                 Source address to write from
- *
- * @param size                Size of data in bytes
- *
- * @param src_bits            Source audio bit
- *
- * @param aim_bits            Bit wanted, no more than 32, and must be greater than src_bits
- *
- * @param[out] bytes_written  Number of bytes written, if timeout, the result will be less than the size passed in.
- *
- * @param ticks_to_wait       TX buffer wait timeout in RTOS ticks. If this
- * many ticks pass without space becoming available in the DMA
- * transmit buffer, then the function will return (note that if the
- * data is written to the DMA buffer in pieces, the overall operation
- * may still take longer than this timeout.) Pass portMAX_DELAY for no
- * timeout.
- *
- * Format of the data in source buffer is determined by the I2S
- * configuration (see i2s_config_t).
- *
- * @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2s_write_expand(i2s_port_t i2s_num, const void *src, size_t size, size_t src_bits, size_t aim_bits, size_t *bytes_written, TickType_t ticks_to_wait);
-
-/**
- * @brief Read data from I2S DMA receive buffer
- *
- * This function is deprecated. Use 'i2s_read' instead.
- * This definition will be removed in a future release.
- *
- * @return
- *     - The amount of bytes read, if timeout, bytes read will be less than the size passed in
- *     - ESP_FAIL  Parameter error
- */
-int i2s_read_bytes(i2s_port_t i2s_num, void *dest, size_t size, TickType_t ticks_to_wait) __attribute__ ((deprecated));
-
-/**
- * @brief Read data from I2S DMA receive buffer
- *
- * @param i2s_num         I2S_NUM_0, I2S_NUM_1
- *
- * @param dest            Destination address to read into
- *
- * @param size            Size of data in bytes
- *
- * @param[out] bytes_read Number of bytes read, if timeout, bytes read will be less than the size passed in.
- *
- * @param ticks_to_wait   RX buffer wait timeout in RTOS ticks. If this many ticks pass without bytes becoming available in the DMA receive buffer, then the function will return (note that if data is read from the DMA buffer in pieces, the overall operation may still take longer than this timeout.) Pass portMAX_DELAY for no timeout.
- *
- * @note If the built-in ADC mode is enabled, we should call i2s_adc_start and i2s_adc_stop around the whole reading process,
- *       to prevent the data getting corrupted.
- *
- * @return
- *     - ESP_OK               Success
- *     - ESP_ERR_INVALID_ARG  Parameter error
- */
-esp_err_t i2s_read(i2s_port_t i2s_num, void *dest, size_t size, size_t *bytes_read, TickType_t ticks_to_wait);
-
-/**
- * @brief Write a single sample to the I2S DMA TX buffer.
- *
- * This function is deprecated. Use 'i2s_write' instead.
- * This definition will be removed in a future release.
- *
- * @param i2s_num         I2S_NUM_0, I2S_NUM_1
- *
- * @param sample          Buffer to read data. Size of buffer (in bytes) = bits_per_sample / 8.
- *
- * @param ticks_to_wait   Timeout in RTOS ticks. If a sample is not available in the DMA buffer within this period, no data is read and function returns zero.
- *
- * @return
- *     - Number of bytes successfully pushed to DMA buffer, will be either zero or the size of configured sample buffer (in bytes).
- *     - ESP_FAIL Parameter error
- */
-int i2s_push_sample(i2s_port_t i2s_num, const void *sample, TickType_t ticks_to_wait) __attribute__ ((deprecated));
-
-/**
- * @brief Read a single sample from the I2S DMA RX buffer.
- *
- * This function is deprecated. Use 'i2s_read' instead.
- * This definition will be removed in a future release.
- *
- * @param i2s_num         I2S_NUM_0, I2S_NUM_1
- *
- * @param sample          Buffer to write data. Size of buffer (in bytes) = bits_per_sample / 8.
- *
- * @param ticks_to_wait   Timeout in RTOS ticks. If a sample is not available in the DMA buffer within this period, no data is read and function returns zero.
- *
- * @return
- *     - Number of bytes successfully read from DMA buffer, will be either zero or the size of configured sample buffer (in bytes).
- *     - ESP_FAIL Parameter error
- */
-int i2s_pop_sample(i2s_port_t i2s_num, void *sample, TickType_t ticks_to_wait) __attribute__ ((deprecated));
-
-/**
- * @brief Set sample rate used for I2S RX and TX.
- *
- * The bit clock rate is determined by the sample rate and i2s_config_t configuration parameters (number of channels, bits_per_sample).
- *
- * `bit_clock = rate * (number of channels) * bits_per_sample`
- *
- * @param i2s_num  I2S_NUM_0, I2S_NUM_1
- *
- * @param rate I2S sample rate (ex: 8000, 44100...)
- *
- * @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NO_MEM      Out of memory
- */
-esp_err_t i2s_set_sample_rates(i2s_port_t i2s_num, uint32_t rate);
-
-/**
- * @brief Stop I2S driver
- *
- * Disables I2S TX/RX, until i2s_start() is called.
- *
- * @param i2s_num  I2S_NUM_0, I2S_NUM_1
- *
- * @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2s_stop(i2s_port_t i2s_num);
-
-/**
- * @brief Start I2S driver
- *
- * It is not necessary to call this function after i2s_driver_install() (it is started automatically), however it is necessary to call it after i2s_stop().
- *
- *
- * @param i2s_num  I2S_NUM_0, I2S_NUM_1
- *
-* @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2s_start(i2s_port_t i2s_num);
-
-/**
- * @brief Zero the contents of the TX DMA buffer.
- *
- * Pushes zero-byte samples into the TX DMA buffer, until it is full.
- *
- * @param i2s_num  I2S_NUM_0, I2S_NUM_1
- *
- * @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num);
-
-/**
- * @brief Set clock & bit width used for I2S RX and TX.
- *
- * Similar to i2s_set_sample_rates(), but also sets bit width.
- *
- * @param i2s_num  I2S_NUM_0, I2S_NUM_1
- *
- * @param rate I2S sample rate (ex: 8000, 44100...)
- *
- * @param bits I2S bit width (I2S_BITS_PER_SAMPLE_16BIT, I2S_BITS_PER_SAMPLE_24BIT, I2S_BITS_PER_SAMPLE_32BIT)
- *
- * @param ch I2S channel, (I2S_CHANNEL_MONO, I2S_CHANNEL_STEREO)
- *
- * @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NO_MEM      Out of memory
- */
-esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t bits, i2s_channel_t ch);
-
-/**
- * @brief get clock set on particular port number.
- *
- * @param i2s_num  I2S_NUM_0, I2S_NUM_1
- *
- * @return
- *     - actual clock set by i2s driver
- */
-float i2s_get_clk(i2s_port_t i2s_num);
-
-/**
- * @brief Set built-in ADC mode for I2S DMA, this function will initialize ADC pad,
- *        and set ADC parameters.
- * @param adc_unit    SAR ADC unit index
- * @param adc_channel ADC channel index
- * @return
- *     - ESP_OK              Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
-
-/**
- * @brief Start to use I2S built-in ADC mode
- * @note This function would acquire the lock of ADC to prevent the data getting corrupted
- *       during the I2S peripheral is being used to do fully continuous ADC sampling.
- *
- * @param i2s_num i2s port index
- * @return
- *     - ESP_OK                Success
- *     - ESP_ERR_INVALID_ARG   Parameter error
- *     - ESP_ERR_INVALID_STATE Driver state error
- */
-esp_err_t i2s_adc_enable(i2s_port_t i2s_num);
-
-/**
- * @brief Stop to use I2S built-in ADC mode
- * @param i2s_num i2s port index
- * @note This function would release the lock of ADC so that other tasks can use ADC.
- * @return
- *     - ESP_OK                 Success
- *     - ESP_ERR_INVALID_ARG    Parameter error
- *     - ESP_ERR_INVALID_STATE  Driver state error
- */
-esp_err_t i2s_adc_disable(i2s_port_t i2s_num);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DRIVER_I2S_H_ */
diff --git a/tools/sdk/include/driver/driver/ledc.h b/tools/sdk/include/driver/driver/ledc.h
deleted file mode 100644
index f54f5acd19d..00000000000
--- a/tools/sdk/include/driver/driver/ledc.h
+++ /dev/null
@@ -1,523 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_LEDC_H_
-#define _DRIVER_LEDC_H_
-#include "esp_err.h"
-#include "soc/soc.h"
-#include "driver/gpio.h"
-#include "driver/periph_ctrl.h"
-#include "esp_intr_alloc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define LEDC_APB_CLK_HZ (APB_CLK_FREQ)
-#define LEDC_REF_CLK_HZ (1*1000000)
-#define LEDC_ERR_DUTY   (0xFFFFFFFF)
-#define LEDC_ERR_VAL    (-1)
-
-typedef enum {
-    LEDC_HIGH_SPEED_MODE = 0, /*!< LEDC high speed speed_mode */
-    LEDC_LOW_SPEED_MODE,      /*!< LEDC low speed speed_mode */
-    LEDC_SPEED_MODE_MAX,      /*!< LEDC speed limit */
-} ledc_mode_t;
-
-typedef enum {
-    LEDC_INTR_DISABLE = 0,    /*!< Disable LEDC interrupt */
-    LEDC_INTR_FADE_END,       /*!< Enable LEDC interrupt */
-} ledc_intr_type_t;
-
-typedef enum {
-    LEDC_DUTY_DIR_DECREASE = 0,    /*!< LEDC duty decrease direction */
-    LEDC_DUTY_DIR_INCREASE = 1,    /*!< LEDC duty increase direction */
-    LEDC_DUTY_DIR_MAX,
-} ledc_duty_direction_t;
-
-typedef enum  {
-    LEDC_REF_TICK = 0, /*!< LEDC timer clock divided from reference tick (1Mhz) */
-    LEDC_APB_CLK,      /*!< LEDC timer clock divided from APB clock (80Mhz) */
-} ledc_clk_src_t;
-
-typedef enum {
-    LEDC_TIMER_0 = 0, /*!< LEDC timer 0 */
-    LEDC_TIMER_1,     /*!< LEDC timer 1 */
-    LEDC_TIMER_2,     /*!< LEDC timer 2 */
-    LEDC_TIMER_3,     /*!< LEDC timer 3 */
-    LEDC_TIMER_MAX,
-} ledc_timer_t;
-
-typedef enum {
-    LEDC_CHANNEL_0 = 0, /*!< LEDC channel 0 */
-    LEDC_CHANNEL_1,     /*!< LEDC channel 1 */
-    LEDC_CHANNEL_2,     /*!< LEDC channel 2 */
-    LEDC_CHANNEL_3,     /*!< LEDC channel 3 */
-    LEDC_CHANNEL_4,     /*!< LEDC channel 4 */
-    LEDC_CHANNEL_5,     /*!< LEDC channel 5 */
-    LEDC_CHANNEL_6,     /*!< LEDC channel 6 */
-    LEDC_CHANNEL_7,     /*!< LEDC channel 7 */
-    LEDC_CHANNEL_MAX,
-} ledc_channel_t;
-
-typedef enum {
-    LEDC_TIMER_1_BIT = 1,   /*!< LEDC PWM duty resolution of  1 bits */
-    LEDC_TIMER_2_BIT,       /*!< LEDC PWM duty resolution of  2 bits */
-    LEDC_TIMER_3_BIT,       /*!< LEDC PWM duty resolution of  3 bits */
-    LEDC_TIMER_4_BIT,       /*!< LEDC PWM duty resolution of  4 bits */
-    LEDC_TIMER_5_BIT,       /*!< LEDC PWM duty resolution of  5 bits */
-    LEDC_TIMER_6_BIT,       /*!< LEDC PWM duty resolution of  6 bits */
-    LEDC_TIMER_7_BIT,       /*!< LEDC PWM duty resolution of  7 bits */
-    LEDC_TIMER_8_BIT,       /*!< LEDC PWM duty resolution of  8 bits */
-    LEDC_TIMER_9_BIT,       /*!< LEDC PWM duty resolution of  9 bits */
-    LEDC_TIMER_10_BIT,      /*!< LEDC PWM duty resolution of 10 bits */
-    LEDC_TIMER_11_BIT,      /*!< LEDC PWM duty resolution of 11 bits */
-    LEDC_TIMER_12_BIT,      /*!< LEDC PWM duty resolution of 12 bits */
-    LEDC_TIMER_13_BIT,      /*!< LEDC PWM duty resolution of 13 bits */
-    LEDC_TIMER_14_BIT,      /*!< LEDC PWM duty resolution of 14 bits */
-    LEDC_TIMER_15_BIT,      /*!< LEDC PWM duty resolution of 15 bits */
-    LEDC_TIMER_16_BIT,      /*!< LEDC PWM duty resolution of 16 bits */
-    LEDC_TIMER_17_BIT,      /*!< LEDC PWM duty resolution of 17 bits */
-    LEDC_TIMER_18_BIT,      /*!< LEDC PWM duty resolution of 18 bits */
-    LEDC_TIMER_19_BIT,      /*!< LEDC PWM duty resolution of 19 bits */
-    LEDC_TIMER_20_BIT,      /*!< LEDC PWM duty resolution of 20 bits */
-    LEDC_TIMER_BIT_MAX,
-} ledc_timer_bit_t;
-
-typedef enum {
-    LEDC_FADE_NO_WAIT = 0,  /*!< LEDC fade function will return immediately */
-    LEDC_FADE_WAIT_DONE,    /*!< LEDC fade function will block until fading to the target duty */
-    LEDC_FADE_MAX,
-} ledc_fade_mode_t;
-
-/**
- * @brief Configuration parameters of LEDC channel for ledc_channel_config function
- */
-typedef struct {
-    int gpio_num;                   /*!< the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16 */
-    ledc_mode_t speed_mode;         /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
-    ledc_channel_t channel;         /*!< LEDC channel (0 - 7) */
-    ledc_intr_type_t intr_type;     /*!< configure interrupt, Fade interrupt enable  or Fade interrupt disable */
-    ledc_timer_t timer_sel;         /*!< Select the timer source of channel (0 - 3) */
-    uint32_t duty;                  /*!< LEDC channel duty, the range of duty setting is [0, (2**duty_resolution)] */
-    int hpoint;                     /*!< LEDC channel hpoint value, the max value is 0xfffff */
-} ledc_channel_config_t;
-
-/**
- * @brief Configuration parameters of LEDC Timer timer for ledc_timer_config function
- */
-typedef struct {
-    ledc_mode_t speed_mode;                /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
-    union {
-        ledc_timer_bit_t duty_resolution;  /*!< LEDC channel duty resolution */
-        ledc_timer_bit_t bit_num __attribute__((deprecated)); /*!< Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1 */
-    };
-    ledc_timer_t  timer_num;               /*!< The timer source of channel (0 - 3) */
-    uint32_t freq_hz;                      /*!< LEDC timer frequency (Hz) */
-} ledc_timer_config_t;
-
-typedef intr_handle_t ledc_isr_handle_t;
-
-/**
- * @brief LEDC channel configuration
- *        Configure LEDC channel with the given channel/output gpio_num/interrupt/source timer/frequency(Hz)/LEDC duty resolution
- *
- * @param ledc_conf Pointer of LEDC channel configure struct
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t ledc_channel_config(const ledc_channel_config_t* ledc_conf);
-
-/**
- * @brief LEDC timer configuration
- *        Configure LEDC timer with the given source timer/frequency(Hz)/duty_resolution
- *
- * @param  timer_conf Pointer of LEDC timer configure struct
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_FAIL Can not find a proper pre-divider number base on the given frequency and the current duty_resolution.
- */
-esp_err_t ledc_timer_config(const ledc_timer_config_t* timer_conf);
-
-/**
- * @brief LEDC update channel parameters
- * @note  Call this function to activate the LEDC updated parameters.
- *        After ledc_set_duty, we need to call this function to update the settings.
- * @note  ledc_set_duty, ledc_set_duty_with_hpoint and ledc_update_duty are not thread-safe, do not call these functions to
- *        control one LEDC channel in different tasks at the same time.
- *        A thread-safe version of API is ledc_set_duty_and_update
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,
- * @param channel LEDC channel (0-7), select from ledc_channel_t
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *
- */
-esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel);
-
-/**
- * @brief Set LEDC output gpio.
- *
- * @param  gpio_num The LEDC output gpio
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param  ledc_channel LEDC channel (0-7), select from ledc_channel_t
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc_channel);
-
-/**
- * @brief LEDC stop.
- *        Disable LEDC output, and set idle level
- *
- * @param  speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param  channel LEDC channel (0-7), select from ledc_channel_t
- * @param  idle_level Set output idle level after LEDC stops.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idle_level);
-
-/**
- * @brief LEDC set channel frequency (Hz)
- *
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param  timer_num LEDC timer index (0-3), select from ledc_timer_t
- * @param  freq_hz Set the LEDC frequency
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_FAIL Can not find a proper pre-divider number base on the given frequency and the current duty_resolution.
- */
-esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t freq_hz);
-
-/**
- * @brief      LEDC get channel frequency (Hz)
- *
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param timer_num LEDC timer index (0-3), select from ledc_timer_t
- *
- * @return
- *     - 0  error
- *     - Others Current LEDC frequency
- */
-uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num);
-
-/**
- * @brief LEDC set duty and hpoint value
- *        Only after calling ledc_update_duty will the duty update.
- * @note  ledc_set_duty, ledc_set_duty_with_hpoint and ledc_update_duty are not thread-safe, do not call these functions to
- *        control one LEDC channel in different tasks at the same time.
- *        A thread-safe version of API is ledc_set_duty_and_update
- * @note  If a fade operation is running in progress on that channel, the driver would not allow it to be stopped.
- *        Other duty operations will have to wait until the fade operation has finished.
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param channel LEDC channel (0-7), select from ledc_channel_t
- * @param duty Set the LEDC duty, the range of duty setting is [0, (2**duty_resolution)]
- * @param hpoint Set the LEDC hpoint value(max: 0xfffff)
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t ledc_set_duty_with_hpoint(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty, uint32_t hpoint);
-
-/**
- * @brief LEDC get hpoint value, the counter value when the output is set high level.
- *
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param channel LEDC channel (0-7), select from ledc_channel_t
- * @return
- *     - LEDC_ERR_VAL if parameter error
- *     - Others Current hpoint value of LEDC channel
- */
-int ledc_get_hpoint(ledc_mode_t speed_mode, ledc_channel_t channel);
-
-/**
- * @brief LEDC set duty
- *        This function do not change the hpoint value of this channel. if needed, please call ledc_set_duty_with_hpoint.
- *        only after calling ledc_update_duty will the duty update.
- * @note  ledc_set_duty, ledc_set_duty_with_hpoint and ledc_update_duty are not thread-safe, do not call these functions to
- *        control one LEDC channel in different tasks at the same time.
- *        A thread-safe version of API is ledc_set_duty_and_update.
- * @note  If a fade operation is running in progress on that channel, the driver would not allow it to be stopped.
- *        Other duty operations will have to wait until the fade operation has finished.
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param channel LEDC channel (0-7), select from ledc_channel_t
- * @param duty Set the LEDC duty, the range of duty setting is [0, (2**duty_resolution)]
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty);
-
-/**
- * @brief LEDC get duty
- *
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param channel LEDC channel (0-7), select from ledc_channel_t
- *
- * @return
- *     - LEDC_ERR_DUTY if parameter error
- *     - Others Current LEDC duty
- */
-uint32_t ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel);
-
-/**
- * @brief LEDC set gradient
- *        Set LEDC gradient, After the function calls the ledc_update_duty function, the function can take effect.
- * @note  If a fade operation is running in progress on that channel, the driver would not allow it to be stopped.
- *        Other duty operations will have to wait until the fade operation has finished.
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param channel LEDC channel (0-7), select from ledc_channel_t
- * @param duty Set the start of the gradient duty, the range of duty setting is [0, (2**duty_resolution)]
- * @param fade_direction Set the direction of the gradient
- * @param step_num Set the number of the gradient
- * @param duty_cyle_num Set how many LEDC tick each time the gradient lasts
- * @param duty_scale Set gradient change amplitude
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t ledc_set_fade(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty, ledc_duty_direction_t fade_direction,
-                        uint32_t step_num, uint32_t duty_cyle_num, uint32_t duty_scale);
-
-/**
- * @brief Register LEDC interrupt handler, the handler is an ISR.
- *        The handler will be attached to the same CPU core that this function is running on.
- *
- * @param fn Interrupt handler function.
- * @param arg User-supplied argument passed to the handler function.
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
- * @param arg Parameter for handler function
- * @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will
- *        be returned here.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Function pointer error.
- */
-esp_err_t ledc_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, ledc_isr_handle_t *handle);
-
-/**
- * @brief Configure LEDC settings
- *
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param timer_sel  Timer index (0-3), there are 4 timers in LEDC module
- * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source
- * @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)]
- * @param clk_src Select LEDC source clock.
- *
- * @return
- *     - (-1) Parameter error
- *     - Other Current LEDC duty
- */
-esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider, uint32_t duty_resolution, ledc_clk_src_t clk_src);
-
-/**
- * @brief Reset LEDC timer
- *
- * @param  speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param  timer_sel LEDC timer index (0-3), select from ledc_timer_t
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, uint32_t timer_sel);
-
-/**
- * @brief Pause LEDC timer counter
- *
- * @param  speed_mode  Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param  timer_sel LEDC timer index (0-3), select from ledc_timer_t
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- *
- */
-esp_err_t ledc_timer_pause(ledc_mode_t speed_mode, uint32_t timer_sel);
-
-/**
- * @brief Resume LEDC timer
- *
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t ledc_timer_resume(ledc_mode_t speed_mode, uint32_t timer_sel);
-
-/**
- * @brief Bind LEDC channel with the selected timer
- *
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param channel LEDC channel index (0-7), select from ledc_channel_t
- * @param timer_idx LEDC timer index (0-3), select from ledc_timer_t
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t ledc_bind_channel_timer(ledc_mode_t speed_mode, uint32_t channel, uint32_t timer_idx);
-
-/**
- * @brief Set LEDC fade function.
- * @note  Call ledc_fade_func_install() once before calling this function.
- *        Call ledc_fade_start() after this to start fading.
- * @note  ledc_set_fade_with_step, ledc_set_fade_with_time and ledc_fade_start are not thread-safe, do not call these functions to
- *        control one LEDC channel in different tasks at the same time.
- *        A thread-safe version of API is ledc_set_fade_step_and_start
- * @note  If a fade operation is running in progress on that channel, the driver would not allow it to be stopped.
- *        Other duty operations will have to wait until the fade operation has finished.
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,
- * @param channel LEDC channel index (0-7), select from ledc_channel_t
- * @param target_duty Target duty of fading [0, (2**duty_resolution) - 1]
- * @param scale Controls the increase or decrease step scale.
- * @param cycle_num increase or decrease the duty every cycle_num cycles
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_STATE Fade function not installed.
- *     - ESP_FAIL Fade function init error
- */
-esp_err_t ledc_set_fade_with_step(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t target_duty, uint32_t scale, uint32_t cycle_num);
-
-/**
- * @brief Set LEDC fade function, with a limited time.
- * @note  Call ledc_fade_func_install() once before calling this function.
- *        Call ledc_fade_start() after this to start fading.
- * @note  ledc_set_fade_with_step, ledc_set_fade_with_time and ledc_fade_start are not thread-safe, do not call these functions to
- *        control one LEDC channel in different tasks at the same time.
- *        A thread-safe version of API is ledc_set_fade_step_and_start
- * @note  If a fade operation is running in progress on that channel, the driver would not allow it to be stopped.
- *        Other duty operations will have to wait until the fade operation has finished.
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,
- * @param channel LEDC channel index (0-7), select from ledc_channel_t
- * @param target_duty Target duty of fading.( 0 - (2 ** duty_resolution - 1)))
- * @param max_fade_time_ms The maximum time of the fading ( ms ).
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_STATE Fade function not installed.
- *     - ESP_FAIL Fade function init error
- */
-esp_err_t ledc_set_fade_with_time(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t target_duty, int max_fade_time_ms);
-
-/**
- * @brief Install LEDC fade function. This function will occupy interrupt of LEDC module.
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_STATE Fade function already installed.
- */
-esp_err_t ledc_fade_func_install(int intr_alloc_flags);
-
-/**
- * @brief Uninstall LEDC fade function.
- *
- */
-void ledc_fade_func_uninstall();
-
-/**
- * @brief Start LEDC fading.
- * @note  Call ledc_fade_func_install() once before calling this function.
- *        Call this API right after ledc_set_fade_with_time or ledc_set_fade_with_step before to start fading.
- * @note  If a fade operation is running in progress on that channel, the driver would not allow it to be stopped.
- *        Other duty operations will have to wait until the fade operation has finished.
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param channel LEDC channel number
- * @param fade_mode Whether to block until fading done.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_STATE Fade function not installed.
- *     - ESP_ERR_INVALID_ARG Parameter error.
- */
-esp_err_t ledc_fade_start(ledc_mode_t speed_mode, ledc_channel_t channel, ledc_fade_mode_t fade_mode);
-
-/**
- * @brief A thread-safe API to set duty for LEDC channel and return when duty updated.
- * @note  If a fade operation is running in progress on that channel, the driver would not allow it to be stopped.
- *        Other duty operations will have to wait until the fade operation has finished.
- *
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
- * @param channel LEDC channel (0-7), select from ledc_channel_t
- * @param duty Set the LEDC duty, the range of duty setting is [0, (2**duty_resolution)]
- * @param hpoint Set the LEDC hpoint value(max: 0xfffff)
- *
- */
-esp_err_t ledc_set_duty_and_update(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty, uint32_t hpoint);
-
-/**
- * @brief A thread-safe API to set and start LEDC fade function, with a limited time.
- * @note  Call ledc_fade_func_install() once, before calling this function.
- * @note  If a fade operation is running in progress on that channel, the driver would not allow it to be stopped.
- *        Other duty operations will have to wait until the fade operation has finished.
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,
- * @param channel LEDC channel index (0-7), select from ledc_channel_t
- * @param target_duty Target duty of fading.( 0 - (2 ** duty_resolution - 1)))
- * @param max_fade_time_ms The maximum time of the fading ( ms ).
- * @param fade_mode choose blocking or non-blocking mode
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_STATE Fade function not installed.
- *     - ESP_FAIL Fade function init error
- */
-esp_err_t ledc_set_fade_time_and_start(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t target_duty, uint32_t max_fade_time_ms, ledc_fade_mode_t fade_mode);
-
-/**
- * @brief A thread-safe API to set and start LEDC fade function.
- * @note  Call ledc_fade_func_install() once before calling this function.
- * @note  If a fade operation is running in progress on that channel, the driver would not allow it to be stopped.
- *        Other duty operations will have to wait until the fade operation has finished.
- * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,
- * @param channel LEDC channel index (0-7), select from ledc_channel_t
- * @param target_duty Target duty of fading [0, (2**duty_resolution) - 1]
- * @param scale Controls the increase or decrease step scale.
- * @param cycle_num increase or decrease the duty every cycle_num cycles
- * @param fade_mode choose blocking or non-blocking mode
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_STATE Fade function not installed.
- *     - ESP_FAIL Fade function init error
- */
-esp_err_t ledc_set_fade_step_and_start(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t target_duty, uint32_t scale, uint32_t cycle_num, ledc_fade_mode_t fade_mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DRIVER_LEDC_H_ */
diff --git a/tools/sdk/include/driver/driver/mcpwm.h b/tools/sdk/include/driver/driver/mcpwm.h
deleted file mode 100644
index 301ca41926b..00000000000
--- a/tools/sdk/include/driver/driver/mcpwm.h
+++ /dev/null
@@ -1,710 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_MCPWM_H_
-#define _DRIVER_MCPWM_H_
-
-#include "esp_err.h"
-#include "soc/soc.h"
-#include "driver/gpio.h"
-#include "driver/periph_ctrl.h"
-#include "esp_intr.h"
-#include "esp_intr_alloc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief IO signals for the MCPWM
- *
- *        - 6 MCPWM output pins that generate PWM signals
- *        - 3 MCPWM fault input pins to detect faults like overcurrent, overvoltage, etc.
- *        - 3 MCPWM sync input pins to synchronize MCPWM outputs signals
- *        - 3 MCPWM capture input pins to gather feedback from controlled motors, using e.g. hall sensors
- */
-typedef enum {
-    MCPWM0A = 0,        /*!<PWM0A output pin*/
-    MCPWM0B,            /*!<PWM0B output pin*/
-    MCPWM1A,            /*!<PWM1A output pin*/
-    MCPWM1B,            /*!<PWM1B output pin*/
-    MCPWM2A,            /*!<PWM2A output pin*/
-    MCPWM2B,            /*!<PWM2B output pin*/
-    MCPWM_SYNC_0,       /*!<SYNC0  input pin*/
-    MCPWM_SYNC_1,       /*!<SYNC1  input pin*/
-    MCPWM_SYNC_2,       /*!<SYNC2  input pin*/
-    MCPWM_FAULT_0,      /*!<FAULT0 input pin*/
-    MCPWM_FAULT_1,      /*!<FAULT1 input pin*/
-    MCPWM_FAULT_2,      /*!<FAULT2 input pin*/
-    MCPWM_CAP_0 = 84,   /*!<CAP0   input pin*/
-    MCPWM_CAP_1,        /*!<CAP1   input pin*/
-    MCPWM_CAP_2,        /*!<CAP2   input pin*/
-} mcpwm_io_signals_t;
-
-/**
- * @brief MCPWM pin number for
- *
- */
-typedef struct {
-    int mcpwm0a_out_num;       /*!<MCPWM0A out pin*/
-    int mcpwm0b_out_num;       /*!<MCPWM0A out pin*/
-    int mcpwm1a_out_num;       /*!<MCPWM0A out pin*/
-    int mcpwm1b_out_num;       /*!<MCPWM0A out pin*/
-    int mcpwm2a_out_num;       /*!<MCPWM0A out pin*/
-    int mcpwm2b_out_num;       /*!<MCPWM0A out pin*/
-    int mcpwm_sync0_in_num;    /*!<SYNC0  in pin*/
-    int mcpwm_sync1_in_num;    /*!<SYNC1  in pin*/
-    int mcpwm_sync2_in_num;    /*!<SYNC2  in pin*/
-    int mcpwm_fault0_in_num;   /*!<FAULT0 in pin*/
-    int mcpwm_fault1_in_num;   /*!<FAULT1 in pin*/
-    int mcpwm_fault2_in_num;   /*!<FAULT2 in pin*/
-    int mcpwm_cap0_in_num;     /*!<CAP0   in pin*/
-    int mcpwm_cap1_in_num;     /*!<CAP1   in pin*/
-    int mcpwm_cap2_in_num;     /*!<CAP2   in pin*/
-} mcpwm_pin_config_t;
-
-/**
- * @brief Select MCPWM unit
- */
-typedef enum {
-    MCPWM_UNIT_0 = 0,  /*!<MCPWM unit0 selected*/
-    MCPWM_UNIT_1,      /*!<MCPWM unit1 selected*/
-    MCPWM_UNIT_MAX,    /*!<Num of MCPWM units on ESP32*/
-} mcpwm_unit_t;
-
-/**
- * @brief Select MCPWM timer
- */
-typedef enum {
-    MCPWM_TIMER_0 = 0,  /*!<Select MCPWM timer0*/
-    MCPWM_TIMER_1,      /*!<Select MCPWM timer1*/
-    MCPWM_TIMER_2,      /*!<Select MCPWM timer2*/
-    MCPWM_TIMER_MAX,    /*!<Num of MCPWM timers on ESP32*/
-} mcpwm_timer_t;
-
-/**
- * @brief Select MCPWM operator
- */
-typedef enum {
-    MCPWM_OPR_A = 0,  /*!<Select MCPWMXA, where 'X' is timer number*/
-    MCPWM_OPR_B,      /*!<Select MCPWMXB, where 'X' is timer number*/
-    MCPWM_OPR_MAX,    /*!<Num of operators to each timer of MCPWM*/
-} mcpwm_operator_t;
-
-/**
- * @brief Select type of MCPWM counter
- */
-typedef enum {
-    MCPWM_UP_COUNTER = 1,   /*!<For asymmetric MCPWM*/
-    MCPWM_DOWN_COUNTER,     /*!<For asymmetric MCPWM*/
-    MCPWM_UP_DOWN_COUNTER,  /*!<For symmetric MCPWM, frequency is half of MCPWM frequency set*/
-    MCPWM_COUNTER_MAX,      /*!<Maximum counter mode*/
-} mcpwm_counter_type_t;
-
-/**
- * @brief Select type of MCPWM duty cycle mode
- */
-typedef enum {
-    MCPWM_DUTY_MODE_0 = 0, /*!<Active high duty, i.e. duty cycle proportional to high time for asymmetric MCPWM*/
-    MCPWM_DUTY_MODE_1,     /*!<Active low duty,  i.e. duty cycle proportional to low  time for asymmetric MCPWM, out of phase(inverted) MCPWM*/
-    MCPWM_DUTY_MODE_MAX,   /*!<Num of duty cycle modes*/
-} mcpwm_duty_type_t;
-
-/**
- * @brief MCPWM carrier oneshot mode, in this mode the width of the first pulse of carrier can be programmed
- */
-typedef enum {
-    MCPWM_ONESHOT_MODE_DIS = 0,  /*!<Enable oneshot mode*/
-    MCPWM_ONESHOT_MODE_EN,       /*!<Disable oneshot mode*/
-} mcpwm_carrier_os_t;
-
-/**
- * @brief MCPWM carrier output inversion, high frequency carrier signal active with MCPWM signal is high
- */
-typedef enum {
-    MCPWM_CARRIER_OUT_IVT_DIS = 0,  /*!<Enable  carrier output inversion*/
-    MCPWM_CARRIER_OUT_IVT_EN,       /*!<Disable carrier output inversion*/
-} mcpwm_carrier_out_ivt_t;
-
-/**
- * @brief MCPWM select sync signal input
- */
-typedef enum {
-    MCPWM_SELECT_SYNC0 = 4,  /*!<Select SYNC0 as input*/
-    MCPWM_SELECT_SYNC1,      /*!<Select SYNC1 as input*/
-    MCPWM_SELECT_SYNC2,      /*!<Select SYNC2 as input*/
-} mcpwm_sync_signal_t;
-
-/**
- * @brief MCPWM select fault signal input
- */
-typedef enum {
-    MCPWM_SELECT_F0 = 0,  /*!<Select F0 as input*/
-    MCPWM_SELECT_F1,      /*!<Select F1 as input*/
-    MCPWM_SELECT_F2,      /*!<Select F2 as input*/
-} mcpwm_fault_signal_t;
-
-/**
- * @brief MCPWM select triggering level of fault signal
- */
-typedef enum {
-    MCPWM_LOW_LEVEL_TGR = 0,  /*!<Fault condition occurs when fault input signal goes from high to low, currently not supported*/
-    MCPWM_HIGH_LEVEL_TGR,     /*!<Fault condition occurs when fault input signal goes low to high*/
-} mcpwm_fault_input_level_t;
-
-/**
- * @brief MCPWM select action to be taken on MCPWMXA when fault occurs
- */
-typedef enum {
-    MCPWM_NO_CHANGE_IN_MCPWMXA = 0,  /*!<No change in MCPWMXA output*/
-    MCPWM_FORCE_MCPWMXA_LOW,         /*!<Make MCPWMXA output low*/
-    MCPWM_FORCE_MCPWMXA_HIGH,        /*!<Make MCPWMXA output high*/
-    MCPWM_TOG_MCPWMXA,               /*!<Make MCPWMXA output toggle*/
-} mcpwm_action_on_pwmxa_t;
-
-/**
- * @brief MCPWM select action to be taken on MCPWMxB when fault occurs
- */
-typedef enum {
-    MCPWM_NO_CHANGE_IN_MCPWMXB = 0,  /*!<No change in MCPWMXB output*/
-    MCPWM_FORCE_MCPWMXB_LOW,         /*!<Make MCPWMXB output low*/
-    MCPWM_FORCE_MCPWMXB_HIGH,        /*!<Make MCPWMXB output high*/
-    MCPWM_TOG_MCPWMXB,               /*!<Make MCPWMXB output toggle*/
-} mcpwm_action_on_pwmxb_t;
-
-/**
- * @brief MCPWM select capture signal input
- */
-typedef enum {
-    MCPWM_SELECT_CAP0 = 0, /*!<Select CAP0 as input*/
-    MCPWM_SELECT_CAP1,     /*!<Select CAP1 as input*/
-    MCPWM_SELECT_CAP2,     /*!<Select CAP2 as input*/
-} mcpwm_capture_signal_t;
-
-/**
- * @brief MCPWM select capture starts from which edge
- */
-typedef enum {
-    MCPWM_NEG_EDGE = 0,  /*!<Capture starts from negative edge*/
-    MCPWM_POS_EDGE,      /*!<Capture starts from positive edge*/
-} mcpwm_capture_on_edge_t;
-
-/**
- * @brief MCPWM deadtime types, used to generate deadtime, RED refers to rising edge delay and FED refers to falling edge delay
- */
-typedef enum {
-    MCPWM_BYPASS_RED = 0,               /*!<MCPWMXA = no change, MCPWMXB = falling edge delay*/
-    MCPWM_BYPASS_FED,                   /*!<MCPWMXA = rising edge delay, MCPWMXB = no change*/
-    MCPWM_ACTIVE_HIGH_MODE,             /*!<MCPWMXA = rising edge delay,  MCPWMXB = falling edge delay*/
-    MCPWM_ACTIVE_LOW_MODE,              /*!<MCPWMXA = compliment of rising edge delay,  MCPWMXB = compliment of falling edge delay*/
-    MCPWM_ACTIVE_HIGH_COMPLIMENT_MODE,  /*!<MCPWMXA = rising edge delay,  MCPWMXB = compliment of falling edge delay*/
-    MCPWM_ACTIVE_LOW_COMPLIMENT_MODE,   /*!<MCPWMXA = compliment of rising edge delay,  MCPWMXB = falling edge delay*/
-    MCPWM_ACTIVE_RED_FED_FROM_PWMXA,    /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXA*/
-    MCPWM_ACTIVE_RED_FED_FROM_PWMXB,    /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXB*/
-    MCPWM_DEADTIME_TYPE_MAX,
-} mcpwm_deadtime_type_t;
-
-/**
- * @brief MCPWM config structure
- */
-typedef struct {
-    uint32_t frequency;              /*!<Set frequency of MCPWM in Hz*/
-    float cmpr_a;                    /*!<Set % duty cycle for operator a(MCPWMXA), i.e for 62.3% duty cycle, duty_a = 62.3*/
-    float cmpr_b;                    /*!<Set % duty cycle for operator b(MCPWMXB), i.e for 48% duty cycle, duty_b = 48.0*/
-    mcpwm_duty_type_t duty_mode;     /*!<Set type of duty cycle*/
-    mcpwm_counter_type_t counter_mode;  /*!<Set  type of MCPWM counter*/
-} mcpwm_config_t;
-
-/**
- * @brief MCPWM config carrier structure
- */
-typedef struct {
-    uint8_t carrier_period;                    /*!<Set carrier period = (carrier_period + 1)*800ns, carrier_period should be < 16*/
-    uint8_t carrier_duty;                      /*!<Set carrier duty cycle, carrier_duty should be less than 8 (increment every 12.5%)*/
-    uint8_t pulse_width_in_os;                 /*!<Set pulse width of first pulse in one shot mode = (carrier period)*(pulse_width_in_os + 1), should be less then 16*/
-    mcpwm_carrier_os_t carrier_os_mode;        /*!<Enable or disable carrier oneshot mode*/
-    mcpwm_carrier_out_ivt_t carrier_ivt_mode;  /*!<Invert output of carrier*/
-} mcpwm_carrier_config_t;
-
-
-/**
- * @brief This function initializes each gpio signal for MCPWM
- *        @note
- *        This function initializes one gpio at a time.
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param io_signal set MCPWM signals, each MCPWM unit has 6 output(MCPWMXA, MCPWMXB) and 9 input(SYNC_X, FAULT_X, CAP_X)
- *                  'X' is timer_num(0-2)
- * @param gpio_num set this to configure gpio for MCPWM, if you want to use gpio16, gpio_num = 16
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, int gpio_num);
-
-/**
- * @brief Initialize MCPWM gpio structure
- *        @note
- *        This function can be used to initialize more then one gpio at a time.
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param mcpwm_pin MCPWM pin structure
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_pin);
-
-/**
- * @brief Initialize MCPWM parameters
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param mcpwm_conf configure structure mcpwm_config_t
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_init( mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_config_t  *mcpwm_conf);
-
-/**
- * @brief Set frequency(in Hz) of MCPWM timer
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param frequency set the frequency in Hz of each timer
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_set_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint32_t frequency);
-
-/**
- * @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB)
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param op_num set the operator(MCPWMXA/MCPWMXB), 'X' is timer number selected
- * @param duty set duty cycle in %(i.e for 62.3% duty cycle, duty = 62.3) of each operator
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_set_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, float duty);
-
-/**
- * @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB) in us
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
- * @param duty set duty value in microseconds of each operator
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_set_duty_in_us(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, uint32_t duty);
-
-/**
- * @brief Set duty either active high or active low(out of phase/inverted)
- *        @note
- *        Call this function every time after mcpwm_set_signal_high or mcpwm_set_signal_low to resume with previously set duty cycle
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
- * @param duty_num set active low or active high duty type
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_set_duty_type(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, mcpwm_duty_type_t duty_num);
-
-/**
-* @brief Get frequency of timer
-*
-* @param mcpwm_num set MCPWM unit(0-1)
-* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
-*
-* @return
-*     - frequency of timer
-*/
-uint32_t mcpwm_get_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
-
-/**
- * @brief Get duty cycle of each operator
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
- *
- * @return
- *     - duty cycle in % of each operator(56.7 means duty is 56.7%)
- */
-float mcpwm_get_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
-
-/**
- * @brief Use this function to set MCPWM signal high
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
-
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_set_signal_high(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
-
-/**
- * @brief Use this function to set MCPWM signal low
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
-
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_set_signal_low(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
-/**
- * @brief Start MCPWM signal on timer 'x'
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_start(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
-
-/**
- * @brief Start MCPWM signal on timer 'x'
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_stop(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
-
-/**
- * @brief  Initialize carrier configuration
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param carrier_conf configure structure mcpwm_carrier_config_t
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_carrier_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_carrier_config_t *carrier_conf);
-
-/**
-* @brief Enable MCPWM carrier submodule, for respective timer
-*
-* @param mcpwm_num set MCPWM unit(0-1)
-* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
-*
-* @return
-*     - ESP_OK Success
-*     - ESP_ERR_INVALID_ARG Parameter error
-*/
-esp_err_t mcpwm_carrier_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
-
-/**
- * @brief Disable MCPWM carrier submodule, for respective timer
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_carrier_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
-
-/**
- * @brief Set period of carrier
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param carrier_period set the carrier period of each timer, carrier period = (carrier_period + 1)*800ns
- *                    (carrier_period <= 15)
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_carrier_set_period(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_period);
-
-/**
- * @brief Set duty_cycle of carrier
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param carrier_duty set duty_cycle of carrier , carrier duty cycle = carrier_duty*12.5%
- *                  (chop_duty <= 7)
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_carrier_set_duty_cycle(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_duty);
-
-/**
- * @brief Enable and set width of first pulse in carrier oneshot mode
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param pulse_width set pulse width of first pulse in oneshot mode, width = (carrier period)*(pulse_width +1)
- *                    (pulse_width <= 15)
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_carrier_oneshot_mode_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t pulse_width);
-
-/**
- * @brief Disable oneshot mode, width of first pulse = carrier period
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_carrier_oneshot_mode_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
-
-/**
- * @brief Enable or disable carrier output inversion
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param carrier_ivt_mode enable or disable carrier output inversion
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_carrier_output_invert(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
-                                      mcpwm_carrier_out_ivt_t carrier_ivt_mode);
-
-/**
- * @brief Enable and initialize deadtime for each MCPWM timer
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param dt_mode set deadtime mode
- * @param red set rising edge delay = red*100ns
- * @param fed set rising edge delay = fed*100ns
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_deadtime_type_t dt_mode,
-                                uint32_t red, uint32_t fed);
-
-/**
- * @brief Disable deadtime on MCPWM timer
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_deadtime_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
-
-/**
- * @brief Initialize fault submodule, currently low level triggering is not supported
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param intput_level set fault signal level, which will cause fault to occur
- * @param fault_sig set the fault pin, which needs to be enabled
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t intput_level, mcpwm_fault_signal_t fault_sig);
-
-/**
- * @brief Set oneshot mode on fault detection, once fault occur in oneshot mode reset is required to resume MCPWM signals
- *        @note
- *        currently low level triggering is not supported
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param fault_sig set the fault pin, which needs to be enabled for oneshot mode
- * @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
- * @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
-                                       mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb);
-
-/**
- * @brief Set cycle-by-cycle mode on fault detection, once fault occur in cyc mode MCPWM signal resumes as soon as fault signal becomes inactive
- *        @note
- *        currently low level triggering is not supported
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param fault_sig set the fault pin, which needs to be enabled for cyc mode
- * @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
- * @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_fault_set_cyc_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
-                                   mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb);
-
-/**
- * @brief Disable fault signal
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param fault_sig fault pin, which needs to be disabled
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_sig);
-
-/**
- * @brief Initialize capture submodule
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param cap_edge set capture edge, BIT(0) - negative edge, BIT(1) - positive edge
- * @param cap_sig capture pin, which needs to be enabled
- * @param num_of_pulse count time between rising/falling edge between 2 *(pulses mentioned), counter uses APB_CLK
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-
-esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig, mcpwm_capture_on_edge_t cap_edge,
-                               uint32_t num_of_pulse);
-
-/**
- * @brief Disable capture signal
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param cap_sig capture pin, which needs to be disabled
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
-
-/**
- * @brief Get capture value
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param cap_sig capture pin on which value is to be measured
- *
- * @return
- *     Captured value
- */
-uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
-
-/**
- * @brief Get edge of capture signal
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param cap_sig capture pin of whose edge is to be determined
- *
- * @return
- *     Capture signal edge: 1 - positive edge, 2 - negtive edge
- */
-uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
-
-/**
- * @brief Initialize sync submodule
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- * @param sync_sig set the synchronization pin, which needs to be enabled
- * @param phase_val phase value in 1/1000 (for 86.7%, phase_val = 867) which timer moves to on sync signal
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_sync_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_sync_signal_t sync_sig,
-                            uint32_t phase_val);
-
-/**
- * @brief Disable sync submodule on given timer
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mcpwm_sync_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
-
-/**
- * @brief Register MCPWM interrupt handler, the handler is an ISR.
- *        the handler will be attached to the same CPU core that this function is running on.
- *
- * @param mcpwm_num set MCPWM unit(0-1)
- * @param fn interrupt handler function.
- * @param arg user-supplied argument passed to the handler function.
- * @param intr_alloc_flags flags used to allocate the interrupt. One or multiple (ORred)
- *        ESP_INTR_FLAG_* values. see esp_intr_alloc.h for more info.
- * @param arg parameter for handler function
- * @param handle pointer to return handle. If non-NULL, a handle for the interrupt will
- *        be returned here.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Function pointer error.
- */
-esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *arg, int intr_alloc_flags, intr_handle_t *handle);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /*_DRIVER_MCPWM_H_*/
diff --git a/tools/sdk/include/driver/driver/pcnt.h b/tools/sdk/include/driver/driver/pcnt.h
deleted file mode 100644
index e96450d0b97..00000000000
--- a/tools/sdk/include/driver/driver/pcnt.h
+++ /dev/null
@@ -1,436 +0,0 @@
-#ifndef __PCNT_H__
-#define __PCNT_H__
-
-#include <esp_types.h>
-#include "esp_intr.h"
-#include "esp_err.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
-#include "soc/soc.h"
-#include "soc/pcnt_reg.h"
-#include "soc/pcnt_struct.h"
-#include "soc/gpio_sig_map.h"
-#include "driver/gpio.h"
-#include "esp_intr_alloc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define PCNT_PIN_NOT_USED     (-1)  /*!< When selected for a pin, this pin will not be used */
-
-/**
- * @brief Selection of available modes that determine the counter's action depending on the state of the control signal's input GPIO
- * @note  Configuration covers two actions, one for high, and one for low level on the control input
- */
-typedef enum {
-    PCNT_MODE_KEEP = 0,             /*!< Control mode: won't change counter mode*/
-    PCNT_MODE_REVERSE = 1,          /*!< Control mode: invert counter mode(increase -> decrease, decrease -> increase) */
-    PCNT_MODE_DISABLE = 2,          /*!< Control mode: Inhibit counter(counter value will not change in this condition) */
-    PCNT_MODE_MAX
-} pcnt_ctrl_mode_t;
-
-/**
- * @brief Selection of available modes that determine the counter's action on the edge of the pulse signal's input GPIO
- * @note  Configuration covers two actions, one for positive, and one for negative edge on the pulse input
- */
-typedef enum {
-    PCNT_COUNT_DIS = 0,            /*!< Counter mode: Inhibit counter(counter value will not change in this condition) */
-    PCNT_COUNT_INC = 1,            /*!< Counter mode: Increase counter value */
-    PCNT_COUNT_DEC = 2,            /*!< Counter mode: Decrease counter value */
-    PCNT_COUNT_MAX
-} pcnt_count_mode_t;
-
-/**
- * @brief Selection of all available PCNT units
- */
-typedef enum {
-    PCNT_UNIT_0 = 0,                 /*!< PCNT unit 0 */
-    PCNT_UNIT_1 = 1,                 /*!< PCNT unit 1 */
-    PCNT_UNIT_2 = 2,                 /*!< PCNT unit 2 */
-    PCNT_UNIT_3 = 3,                 /*!< PCNT unit 3 */
-    PCNT_UNIT_4 = 4,                 /*!< PCNT unit 4 */
-    PCNT_UNIT_5 = 5,                 /*!< PCNT unit 5 */
-    PCNT_UNIT_6 = 6,                 /*!< PCNT unit 6 */
-    PCNT_UNIT_7 = 7,                 /*!< PCNT unit 7 */
-    PCNT_UNIT_MAX,
-} pcnt_unit_t; 
-
-/**
- * @brief Selection of channels available for a single PCNT unit
- */
-typedef enum {
-    PCNT_CHANNEL_0 = 0x00,           /*!< PCNT channel 0 */
-    PCNT_CHANNEL_1 = 0x01,           /*!< PCNT channel 1 */
-    PCNT_CHANNEL_MAX,
-} pcnt_channel_t;
-
-/**
- * @brief Selection of counter's events the may trigger an interrupt
- */
-typedef enum {
-    PCNT_EVT_L_LIM = 0,             /*!< PCNT watch point event: Minimum counter value */
-    PCNT_EVT_H_LIM = 1,             /*!< PCNT watch point event: Maximum counter value */
-    PCNT_EVT_THRES_0 = 2,           /*!< PCNT watch point event: threshold0 value event */
-    PCNT_EVT_THRES_1 = 3,           /*!< PCNT watch point event: threshold1 value event */
-    PCNT_EVT_ZERO = 4,              /*!< PCNT watch point event: counter value zero event */
-    PCNT_EVT_MAX
-} pcnt_evt_type_t;
-
-/**
- * @brief Pulse Counter configuration for a single channel
- */
-typedef struct {
-    int pulse_gpio_num;             /*!< Pulse input GPIO number, if you want to use GPIO16, enter pulse_gpio_num = 16, a negative value will be ignored */
-    int ctrl_gpio_num;              /*!< Control signal input GPIO number, a negative value will be ignored */
-    pcnt_ctrl_mode_t lctrl_mode;    /*!< PCNT low control mode */
-    pcnt_ctrl_mode_t hctrl_mode;    /*!< PCNT high control mode */
-    pcnt_count_mode_t pos_mode;     /*!< PCNT positive edge count mode */
-    pcnt_count_mode_t neg_mode;     /*!< PCNT negative edge count mode */
-    int16_t counter_h_lim;          /*!< Maximum counter value */
-    int16_t counter_l_lim;          /*!< Minimum counter value */
-    pcnt_unit_t unit;               /*!< PCNT unit number */
-    pcnt_channel_t channel;         /*!< the PCNT channel */
-} pcnt_config_t;
-
-typedef intr_handle_t pcnt_isr_handle_t;
-
-/**
- * @brief Configure Pulse Counter unit
- *        @note
- *        This function will disable three events: PCNT_EVT_L_LIM, PCNT_EVT_H_LIM, PCNT_EVT_ZERO.
- *
- * @param pcnt_config Pointer of Pulse Counter unit configure parameter
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_unit_config(const pcnt_config_t *pcnt_config);
-
-/**
- * @brief Get pulse counter value
- *
- * @param pcnt_unit  Pulse Counter unit number
- * @param count Pointer to accept counter value
- *
- * @return  
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_get_counter_value(pcnt_unit_t pcnt_unit, int16_t* count);
-
-/**
- * @brief Pause PCNT counter of PCNT unit
- *
- * @param pcnt_unit PCNT unit number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_counter_pause(pcnt_unit_t pcnt_unit);
-
-/**
- * @brief Resume counting for PCNT counter
- *
- * @param pcnt_unit PCNT unit number, select from pcnt_unit_t
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_counter_resume(pcnt_unit_t pcnt_unit);
-
-/**
- * @brief Clear and reset PCNT counter value to zero
- *
- * @param  pcnt_unit PCNT unit number, select from pcnt_unit_t
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_counter_clear(pcnt_unit_t pcnt_unit);
-
-/**
- * @brief Enable PCNT interrupt for PCNT unit
- *        @note
- *        Each Pulse counter unit has five watch point events that share the same interrupt.
- *        Configure events with pcnt_event_enable() and pcnt_event_disable()
- *
- * @param pcnt_unit PCNT unit number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_intr_enable(pcnt_unit_t pcnt_unit);
-
-/**
- * @brief Disable PCNT interrupt for PCNT unit
- *
- * @param pcnt_unit PCNT unit number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_intr_disable(pcnt_unit_t pcnt_unit);
-
-/**
- * @brief Enable PCNT event of PCNT unit
- *
- * @param unit PCNT unit number
- * @param evt_type Watch point event type.
- *                 All enabled events share the same interrupt (one interrupt per pulse counter unit).
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_event_enable(pcnt_unit_t unit, pcnt_evt_type_t evt_type);
-
-/**
- * @brief Disable PCNT event of PCNT unit
- *
- * @param unit PCNT unit number
- * @param evt_type Watch point event type.
- *                 All enabled events share the same interrupt (one interrupt per pulse counter unit).
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_event_disable(pcnt_unit_t unit, pcnt_evt_type_t evt_type);
-
-/**
- * @brief Set PCNT event value of PCNT unit
- *
- * @param unit PCNT unit number
- * @param evt_type Watch point event type.
- *                 All enabled events share the same interrupt (one interrupt per pulse counter unit).
- *
- * @param value Counter value for PCNT event
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_set_event_value(pcnt_unit_t unit, pcnt_evt_type_t evt_type, int16_t value);
-
-/**
- * @brief Get PCNT event value of PCNT unit
- *
- * @param unit PCNT unit number
- * @param evt_type Watch point event type.
- *                 All enabled events share the same interrupt (one interrupt per pulse counter unit).
- * @param value Pointer to accept counter value for PCNT event
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_get_event_value(pcnt_unit_t unit, pcnt_evt_type_t evt_type, int16_t *value);
-
-/**
- * @brief Register PCNT interrupt handler, the handler is an ISR.
- *        The handler will be attached to the same CPU core that this function is running on.
- *        Please do not use pcnt_isr_service_install if this function was called.
- *
- * @param fn Interrupt handler function.
- * @param arg Parameter for handler function
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
- * @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will
- *        be returned here. Calling esp_intr_free to unregister this ISR service if needed,
- *        but only if the handle is not NULL.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_NOT_FOUND Can not find the interrupt that matches the flags.
- *     - ESP_ERR_INVALID_ARG Function pointer error.
- */
-esp_err_t pcnt_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, pcnt_isr_handle_t *handle);
-
-/**
- * @brief Configure PCNT pulse signal input pin and control input pin
- *
- * @param unit PCNT unit number
- * @param channel PCNT channel number
- * @param pulse_io Pulse signal input GPIO
- * @param ctrl_io Control signal input GPIO
- *
- * @note  Set the signal input to PCNT_PIN_NOT_USED if unused.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_set_pin(pcnt_unit_t unit, pcnt_channel_t channel, int pulse_io, int ctrl_io);
-
-/**
- * @brief Enable PCNT input filter
- *
- * @param unit PCNT unit number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_filter_enable(pcnt_unit_t unit);
-
-/**
- * @brief Disable PCNT input filter
- *
- * @param unit PCNT unit number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_filter_disable(pcnt_unit_t unit);
-
-/**
- * @brief Set PCNT filter value
- *
- * @param unit PCNT unit number
- * @param filter_val PCNT signal filter value, counter in APB_CLK cycles.
- *        Any pulses lasting shorter than this will be ignored when the filter is enabled.
- *        @note
- *        filter_val is a 10-bit value, so the maximum filter_val should be limited to 1023.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_set_filter_value(pcnt_unit_t unit, uint16_t filter_val);
-
-/**
- * @brief Get PCNT filter value
- *
- * @param unit PCNT unit number
- * @param filter_val Pointer to accept PCNT filter value.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_get_filter_value(pcnt_unit_t unit, uint16_t *filter_val);
-
-/**
- * @brief Set PCNT counter mode
- *
- * @param unit PCNT unit number
- * @param channel PCNT channel number
- * @param pos_mode Counter mode when detecting positive edge
- * @param neg_mode Counter mode when detecting negative edge
- * @param hctrl_mode Counter mode when control signal is high level
- * @param lctrl_mode Counter mode when control signal is low level
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_set_mode(pcnt_unit_t unit, pcnt_channel_t channel,
-                        pcnt_count_mode_t pos_mode, pcnt_count_mode_t neg_mode,
-                        pcnt_ctrl_mode_t hctrl_mode, pcnt_ctrl_mode_t lctrl_mode);
-
-/**
- * @brief Add ISR handler for specified unit.
- *
- * Call this function after using pcnt_isr_service_install() to
- * install the PCNT driver's ISR handler service.
- *
- * The ISR handlers do not need to be declared with IRAM_ATTR,
- * unless you pass the ESP_INTR_FLAG_IRAM flag when allocating the
- * ISR in pcnt_isr_service_install().
- *
- * This ISR handler will be called from an ISR. So there is a stack
- * size limit (configurable as "ISR stack size" in menuconfig). This
- * limit is smaller compared to a global PCNT interrupt handler due
- * to the additional level of indirection.
- *
- * @param unit PCNT unit number
- * @param isr_handler Interrupt handler function.
- * @param args Parameter for handler function
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_isr_handler_add(pcnt_unit_t unit, void(*isr_handler)(void *), void *args);
-
-/**
- * @brief Install PCNT ISR service.
- * @note We can manage different interrupt service for each unit.
- *       This function will use the default ISR handle service, Calling pcnt_isr_service_uninstall to
- *       uninstall the default service if needed. Please do not use pcnt_isr_register if this function was called. 
- *
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_NO_MEM No memory to install this service
- *     - ESP_ERR_INVALID_STATE ISR service already installed
- */
-esp_err_t pcnt_isr_service_install(int intr_alloc_flags);
-
-/**
- * @brief Uninstall PCNT ISR service, freeing related resources.
- */
-void pcnt_isr_service_uninstall(void);
-
-/**
- * @brief Delete ISR handler for specified unit.
- *
- * @param unit PCNT unit number
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t pcnt_isr_handler_remove(pcnt_unit_t unit);
-
-/**
- * @addtogroup pcnt-examples
- *
- * @{
- *
- * EXAMPLE OF PCNT CONFIGURATION
- * ==============================
- * @code{c}
- * //1. Config PCNT unit
- * pcnt_config_t pcnt_config = {
- *     .pulse_gpio_num = 4,         //set gpio4 as pulse input gpio
- *     .ctrl_gpio_num = 5,          //set gpio5 as control gpio
- *     .channel = PCNT_CHANNEL_0,         //use unit 0 channel 0
- *     .lctrl_mode = PCNT_MODE_REVERSE,   //when control signal is low, reverse the primary counter mode(inc->dec/dec->inc)
- *     .hctrl_mode = PCNT_MODE_KEEP,      //when control signal is high, keep the primary counter mode
- *     .pos_mode = PCNT_COUNT_INC,        //increment the counter
- *     .neg_mode = PCNT_COUNT_DIS,        //keep the counter value
- *     .counter_h_lim = 10,
- *     .counter_l_lim = -10,
- * };
- * pcnt_unit_config(&pcnt_config);        //init unit
- * @endcode
- *
- * EXAMPLE OF PCNT EVENT SETTING
- * ==============================
- * @code{c}
- * //2. Configure PCNT watchpoint event.
- * pcnt_set_event_value(PCNT_UNIT_0, PCNT_EVT_THRES_1, 5);   //set thres1 value
- * pcnt_event_enable(PCNT_UNIT_0, PCNT_EVT_THRES_1);         //enable thres1 event
- * @endcode
- *
- * For more examples please refer to PCNT example code in IDF_PATH/examples
- *
- * @}
- */
-
-#ifdef __cplusplus 
-}
-#endif
-
-
-#endif
diff --git a/tools/sdk/include/driver/driver/periph_ctrl.h b/tools/sdk/include/driver/driver/periph_ctrl.h
deleted file mode 100644
index 1d010c0c2ca..00000000000
--- a/tools/sdk/include/driver/driver/periph_ctrl.h
+++ /dev/null
@@ -1,93 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_PERIPH_CTRL_H_
-#define _DRIVER_PERIPH_CTRL_H_
-
-#include "esp_err.h"
-#include "soc/soc.h"
-#include "soc/dport_reg.h"
-#include "soc/periph_defs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief      enable peripheral module
- *
- * @param[in]  periph    :  Peripheral module name
- *
- * Clock for the module will be ungated, and reset de-asserted.
- *
- * @return     NULL
- *
- */
-void periph_module_enable(periph_module_t periph);
-
-/**
- * @brief      disable peripheral module
- *
- * @param[in]  periph    :  Peripheral module name
- *
- * Clock for the module will be gated, reset asserted.
- *
- * @return     NULL
- *
- */
-void periph_module_disable(periph_module_t periph);
-
-/**
- * @brief      reset peripheral module
- *
- * @param[in]  periph    :  Peripheral module name
- *
- * Reset will asserted then de-assrted for the peripheral.
- *
- * Calling this function does not enable or disable the clock for the module.
- *
- * @return     NULL
- *
- */
-void periph_module_reset(periph_module_t periph);
-
-/**
- * @brief      enable wifi bt common module
- *
- * @note If wifi_bt_common_module_enable is called a number of times,
- *       wifi_bt_common_module_disable has to be called the same number of times
- *       in order to put the peripheral into disabled state.
- *
- * @return     NULL 
- * 
- */
-void wifi_bt_common_module_enable(void);
-
-/**
- * @brief      disable wifi bt common module
- *
- * @note If wifi_bt_common_module_enable is called a number of times,
- *       wifi_bt_common_module_disable has to be called the same number of times
- *       in order to put the peripheral into disabled state.
- *
- * @return     NULL 
- * 
- */
-void wifi_bt_common_module_disable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DRIVER_PERIPH_CTRL_H_ */
diff --git a/tools/sdk/include/driver/driver/rmt.h b/tools/sdk/include/driver/driver/rmt.h
deleted file mode 100644
index 87916b3756b..00000000000
--- a/tools/sdk/include/driver/driver/rmt.h
+++ /dev/null
@@ -1,815 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_RMT_CTRL_H_
-#define _DRIVER_RMT_CTRL_H_
-#include "esp_err.h"
-#include "soc/rmt_reg.h"
-#include "soc/dport_reg.h"
-#include "soc/rmt_struct.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
-#include "freertos/ringbuf.h"
-#include "driver/gpio.h"
-#include "driver/periph_ctrl.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define RMT_MEM_BLOCK_BYTE_NUM (256)
-#define RMT_MEM_ITEM_NUM  (RMT_MEM_BLOCK_BYTE_NUM/4)
-
-typedef enum {
-    RMT_CHANNEL_0 = 0, /*!< RMT Channel 0 */
-    RMT_CHANNEL_1,     /*!< RMT Channel 1 */
-    RMT_CHANNEL_2,     /*!< RMT Channel 2 */
-    RMT_CHANNEL_3,     /*!< RMT Channel 3 */
-    RMT_CHANNEL_4,     /*!< RMT Channel 4 */
-    RMT_CHANNEL_5,     /*!< RMT Channel 5 */
-    RMT_CHANNEL_6,     /*!< RMT Channel 6 */
-    RMT_CHANNEL_7,     /*!< RMT Channel 7 */
-    RMT_CHANNEL_MAX
-} rmt_channel_t;
-
-typedef enum {
-    RMT_MEM_OWNER_TX = 0,  /*!< RMT RX mode, RMT transmitter owns the memory block*/
-    RMT_MEM_OWNER_RX = 1,  /*!< RMT RX mode, RMT receiver owns the memory block*/
-    RMT_MEM_OWNER_MAX,
-}rmt_mem_owner_t;
-
-typedef enum {
-    RMT_BASECLK_REF = 0,   /*!< RMT source clock system reference tick, 1MHz by default (not supported in this version) */
-    RMT_BASECLK_APB,       /*!< RMT source clock is APB CLK, 80Mhz by default */
-    RMT_BASECLK_MAX,
-} rmt_source_clk_t;
-
-typedef enum {
-    RMT_DATA_MODE_FIFO = 0,  /*<! RMT memory access in FIFO mode */
-    RMT_DATA_MODE_MEM = 1,   /*<! RMT memory access in memory mode */
-    RMT_DATA_MODE_MAX,
-} rmt_data_mode_t;
-
-typedef enum {
-    RMT_MODE_TX = 0,   /*!< RMT TX mode */
-    RMT_MODE_RX,       /*!< RMT RX mode */
-    RMT_MODE_MAX
-} rmt_mode_t;
-
-typedef enum {
-    RMT_IDLE_LEVEL_LOW = 0,   /*!< RMT TX idle level: low Level */
-    RMT_IDLE_LEVEL_HIGH,      /*!< RMT TX idle level: high Level */
-    RMT_IDLE_LEVEL_MAX,
-} rmt_idle_level_t;
-
-typedef enum {
-    RMT_CARRIER_LEVEL_LOW = 0,  /*!< RMT carrier wave is modulated for low Level output */
-    RMT_CARRIER_LEVEL_HIGH,     /*!< RMT carrier wave is modulated for high Level output */
-    RMT_CARRIER_LEVEL_MAX
-} rmt_carrier_level_t;
-
-typedef enum {
-    RMT_CHANNEL_UNINIT = 0, /*!< RMT channel uninitialized */
-    RMT_CHANNEL_IDLE = 1,   /*!< RMT channel status idle */
-    RMT_CHANNEL_BUSY = 2,   /*!< RMT channel status busy */
-} rmt_channel_status_t;
-
-/**
- * @brief Data struct of RMT channel status
- */
-typedef struct {
-  rmt_channel_status_t status[RMT_CHANNEL_MAX]; /*!< Store the current status of each channel */
-} rmt_channel_status_result_t;
-
-/**
- * @brief Data struct of RMT TX configure parameters
- */
-typedef struct {
-    bool loop_en;                         /*!< Enable sending RMT items in a loop */
-    uint32_t carrier_freq_hz;             /*!< RMT carrier frequency */
-    uint8_t carrier_duty_percent;         /*!< RMT carrier duty (%) */
-    rmt_carrier_level_t carrier_level;    /*!< Level of the RMT output, when the carrier is applied */
-    bool carrier_en;                      /*!< RMT carrier enable */
-    rmt_idle_level_t idle_level;          /*!< RMT idle level */
-    bool idle_output_en;                  /*!< RMT idle level output enable */
-}rmt_tx_config_t;
-
-/**
- * @brief Data struct of RMT RX configure parameters
- */
-typedef struct {
-    bool filter_en;                    /*!< RMT receiver filter enable */
-    uint8_t filter_ticks_thresh;       /*!< RMT filter tick number */
-    uint16_t idle_threshold;           /*!< RMT RX idle threshold */
-}rmt_rx_config_t;
-
-/**
- * @brief Data struct of RMT configure parameters
- */
-typedef struct {
-    rmt_mode_t rmt_mode;               /*!< RMT mode: transmitter or receiver */
-    rmt_channel_t channel;             /*!< RMT channel */
-    uint8_t clk_div;                   /*!< RMT channel counter divider */
-    gpio_num_t gpio_num;               /*!< RMT GPIO number */
-    uint8_t mem_block_num;             /*!< RMT memory block number */
-    union{
-        rmt_tx_config_t tx_config;     /*!< RMT TX parameter */
-        rmt_rx_config_t rx_config;     /*!< RMT RX parameter */
-    };
-} rmt_config_t;
-
-typedef intr_handle_t rmt_isr_handle_t;
-
-typedef void (*rmt_tx_end_fn_t)(rmt_channel_t channel, void *arg);
-
-/**
- * @brief Structure encapsulating a RMT TX end callback
- */
-typedef struct {
-    rmt_tx_end_fn_t function; /*!< Function which is called on RMT TX end */
-    void *arg;                /*!< Optional argument passed to function */
-} rmt_tx_end_callback_t;
-
-/**
- * @brief User callback function to convert uint8_t type data to rmt format(rmt_item32_t).
- *
- *        This function may be called from an ISR, so, the code should be short and efficient.
- *
- * @param  src Pointer to the buffer storing the raw data that needs to be converted to rmt format.
- * @param[out] dest Pointer to the buffer storing the rmt format data.
- * @param  src_size The raw data size.
- * @param  wanted_num The number of rmt format data that wanted to get.
- * @param[out] translated_size The size of the raw data that has been converted to rmt format,
- *             it should return 0 if no data is converted in user callback.
- * @param[out] item_num The number of the rmt format data that actually converted to, it can be less than wanted_num if there is not enough raw data,
- *             but cannot exceed wanted_num. it should return 0 if no data was converted.
- *
- *       @note
- *       In fact, item_num should be a multiple of translated_size, e.g. :
- *       When we convert each byte of uint8_t type data to rmt format data,
- *       the relation between item_num and translated_size should be `item_num = translated_size*8`.
- */
-typedef void (*sample_to_rmt_t)(const void* src, rmt_item32_t* dest, size_t src_size, size_t wanted_num, size_t* translated_size, size_t* item_num);
-
-/**
- * @brief Set RMT clock divider, channel clock is divided from source clock.
- *
- * @param channel RMT channel (0-7)
- * @param div_cnt RMT counter clock divider
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt);
-
-/**
- * @brief Get RMT clock divider, channel clock is divided from source clock.
- *
- * @param channel RMT channel (0-7)
- * @param div_cnt pointer to accept RMT counter divider
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t* div_cnt);
-
-/**
- * @brief Set RMT RX idle threshold value
- *
- *        In receive mode, when no edge is detected on the input signal
- *        for longer than idle_thres channel clock cycles,
- *        the receive process is finished.
- *
- * @param channel RMT channel (0-7)
- * @param thresh RMT RX idle threshold
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh);
-
-/**
- * @brief Get RMT idle threshold value.
- *
- *        In receive mode, when no edge is detected on the input signal
- *        for longer than idle_thres channel clock cycles,
- *        the receive process is finished.
- *
- * @param channel RMT channel (0-7)
- * @param thresh pointer to accept RMT RX idle threshold value
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh);
-
-/**
- * @brief Set RMT memory block number for RMT channel
- *
- *        This function is used to configure the amount of memory blocks allocated to channel n
- *        The 8 channels share a 512x32-bit RAM block which can be read and written
- *        by the processor cores over the APB bus, as well as read by the transmitters
- *        and written by the receivers.
- *
- *        The RAM address range for channel n is start_addr_CHn to end_addr_CHn, which are defined by:
- *        Memory block start address is RMT_CHANNEL_MEM(n) (in soc/rmt_reg.h),
- *        that is, start_addr_chn = RMT base address + 0x800 + 64 ∗ 4 ∗ n, and
- *        end_addr_chn = RMT base address + 0x800 +  64 ∗ 4 ∗ n + 64 ∗ 4 ∗ RMT_MEM_SIZE_CHn mod 512 ∗ 4
- *
- *        @note
- *        If memory block number of one channel is set to a value greater than 1, this channel will occupy the memory
- *        block of the next channel.
- *        Channel 0 can use at most 8 blocks of memory, accordingly channel 7 can only use one memory block.
- *
- * @param channel RMT channel (0-7)
- * @param rmt_mem_num RMT RX memory block number, one block has 64 * 32 bits.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num);
-
-/**
- * @brief Get RMT memory block number
- *
- * @param channel RMT channel (0-7)
- * @param rmt_mem_num Pointer to accept RMT RX memory block number
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t* rmt_mem_num);
-
-/**
- * @brief Configure RMT carrier for TX signal.
- *
- *        Set different values for carrier_high and carrier_low to set different frequency of carrier.
- *        The unit of carrier_high/low is the source clock tick, not the divided channel counter clock.
- *
- * @param channel RMT channel (0-7)
- * @param carrier_en Whether to enable output carrier.
- * @param high_level High level duration of carrier
- * @param low_level Low level duration of carrier.
- * @param carrier_level Configure the way carrier wave is modulated for channel 0-7.
- *     - 1'b1:transmit on low output level
- *     - 1'b0:transmit on high output level
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t low_level, rmt_carrier_level_t carrier_level);
-
-/**
- * @brief Set RMT memory in low power mode.
- *
- *        Reduce power consumed by memory. 1:memory is in low power state.
- *
- * @param channel RMT channel (0-7)
- * @param pd_en RMT memory low power enable.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en);
-
-/**
- * @brief Get RMT memory low power mode.
- *
- * @param channel RMT channel (0-7)
- * @param pd_en Pointer to accept RMT memory low power mode.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool* pd_en);
-
-/**
- * @brief Set RMT start sending data from memory.
- *
- * @param channel RMT channel (0-7)
- * @param tx_idx_rst Set true to reset memory index for TX.
- *                   Otherwise, transmitter will continue sending from the last index in memory.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst);
-
-/**
- * @brief Set RMT stop sending.
- *
- * @param channel RMT channel (0-7)
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_tx_stop(rmt_channel_t channel);
-
-/**
- * @brief Set RMT start receiving data.
- *
- * @param channel RMT channel (0-7)
- * @param rx_idx_rst Set true to reset memory index for receiver.
- *                   Otherwise, receiver will continue receiving data to the last index in memory.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst);
-
-/**
- * @brief Set RMT stop receiving data.
- *
- * @param channel RMT channel (0-7)
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_rx_stop(rmt_channel_t channel);
-
-/**
- * @brief Reset RMT TX/RX memory index.
- *
- * @param channel RMT channel (0-7)
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_memory_rw_rst(rmt_channel_t channel);
-
-/**
- * @brief Set RMT memory owner.
- *
- * @param channel RMT channel (0-7)
- * @param owner To set when the transmitter or receiver can process the memory of channel.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner);
-
-/**
- * @brief Get RMT memory owner.
- *
- * @param channel RMT channel (0-7)
- * @param owner Pointer to get memory owner.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t* owner);
-
-/**
- * @brief Set RMT tx loop mode.
- *
- * @param channel RMT channel (0-7)
- * @param loop_en Enable RMT transmitter loop sending mode.
- *                If set true, transmitter will continue sending from the first data
- *                to the last data in channel 0-7 over and over again in a loop.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en);
-
-/**
- * @brief Get RMT tx loop mode.
- *
- * @param channel RMT channel (0-7)
- * @param loop_en Pointer to accept RMT transmitter loop sending mode.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool* loop_en);
-
-/**
- * @brief Set RMT RX filter.
- *
- *        In receive mode, channel 0-7 will ignore input pulse when the pulse width is smaller than threshold.
- *        Counted in source clock, not divided counter clock.
- *
- * @param channel RMT channel (0-7)
- * @param rx_filter_en To enable RMT receiver filter.
- * @param thresh Threshold of pulse width for receiver.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh);
-
-/**
- * @brief Set RMT source clock
- *
- *        RMT module has two clock sources:
- *        1. APB clock which is 80Mhz
- *        2. REF tick clock, which would be 1Mhz (not supported in this version).
- *
- * @param channel RMT channel (0-7)
- * @param base_clk To choose source clock for RMT module.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk);
-
-/**
- * @brief Get RMT source clock
- *
- *        RMT module has two clock sources:
- *        1. APB clock which is 80Mhz
- *        2. REF tick clock, which would be 1Mhz (not supported in this version).
- *
- * @param channel RMT channel (0-7)
- * @param src_clk Pointer to accept source clock for RMT module.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t* src_clk);
-
-/**
- * @brief Set RMT idle output level for transmitter
- *
- * @param channel RMT channel (0-7)
- * @param idle_out_en To enable idle level output.
- * @param level To set the output signal's level for channel 0-7 in idle state.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_level_t level);
-
-/**
- * @brief Get RMT idle output level for transmitter
- *
- * @param channel RMT channel (0-7)
- * @param idle_out_en Pointer to accept value of enable idle.
- * @param level Pointer to accept value of output signal's level in idle state for specified channel.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool* idle_out_en, rmt_idle_level_t* level);
-
-/**
- * @brief Get RMT status
- *
- * @param channel RMT channel (0-7)
- * @param status Pointer to accept channel status.
- *        Please refer to RMT_CHnSTATUS_REG(n=0~7) in `rmt_reg.h` for more details of each field.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t* status);
-
-/**
- * @brief Set mask value to RMT interrupt enable register.
- *
- * @param mask Bit mask to set to the register
- *
- */
-void rmt_set_intr_enable_mask(uint32_t mask);
-
-/**
- * @brief Clear mask value to RMT interrupt enable register.
- *
- * @param mask Bit mask to clear the register
- *
- */
-void rmt_clr_intr_enable_mask(uint32_t mask);
-
-/**
- * @brief Set RMT RX interrupt enable
- *
- * @param channel RMT channel (0 - 7)
- * @param en enable or disable RX interrupt.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en);
-
-/**
- * @brief Set RMT RX error interrupt enable
- *
- * @param channel RMT channel (0 - 7)
- * @param en enable or disable RX err interrupt.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en);
-
-/**
- * @brief Set RMT TX interrupt enable
- *
- * @param channel RMT channel (0 - 7)
- * @param en enable or disable TX interrupt.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en);
-
-/**
- * @brief Set RMT TX threshold event interrupt enable
- *
- * An interrupt will be triggered when the number of transmitted items reaches the threshold value
- *
- * @param channel RMT channel (0 - 7)
- * @param en enable or disable TX event interrupt.
- * @param evt_thresh RMT event interrupt threshold value
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh);
-
-/**
- * @brief Set RMT pin
- *
- * @param channel RMT channel (0 - 7)
- * @param mode TX or RX mode for RMT
- * @param gpio_num GPIO number to transmit or receive the signal.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num);
-
-/**
- * @brief Configure RMT parameters
- *
- * @param rmt_param RMT parameter struct
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_config(const rmt_config_t* rmt_param);
-
-/**
- * @brief Register RMT interrupt handler, the handler is an ISR.
- *
- *        The handler will be attached to the same CPU core that this function is running on.
- *
- * @note  If you already called rmt_driver_install to use system RMT driver,
- *        please do not register ISR handler again.
- *
- * @param fn Interrupt handler function.
- * @param arg Parameter for the handler function
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
- * @param handle If non-zero, a handle to later clean up the ISR gets stored here.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Function pointer error.
- *     - ESP_FAIL System driver installed, can not register ISR handler for RMT
- */
-esp_err_t rmt_isr_register(void (* fn)(void* ), void * arg, int intr_alloc_flags, rmt_isr_handle_t *handle);
-
-/**
- * @brief   Deregister previously registered RMT interrupt handler
- *
- * @param handle Handle obtained from rmt_isr_register
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Handle invalid
- */
-esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle);
-
-/**
- * @brief Fill memory data of channel with given RMT items.
- *
- * @param channel RMT channel (0 - 7)
- * @param item Pointer of items.
- * @param item_num RMT sending items number.
- * @param mem_offset Index offset of memory.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t* item, uint16_t item_num, uint16_t mem_offset);
-
-/**
- * @brief Initialize RMT driver
- *
- * @param channel RMT channel (0 - 7)
- * @param rx_buf_size Size of RMT RX ringbuffer. Can be 0 if the RX ringbuffer is not used.
- * @param intr_alloc_flags Flags for the RMT driver interrupt handler. Pass 0 for default flags. See esp_intr_alloc.h for details.
- *        If ESP_INTR_FLAG_IRAM is used, please do not use the memory allocated from psram when calling rmt_write_items.
- *
- * @return
- *     - ESP_ERR_INVALID_STATE Driver is already installed, call rmt_driver_uninstall first.
- *     - ESP_ERR_NO_MEM Memory allocation failure
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags);
-
-/**
- * @brief Uninstall RMT driver.
- *
- * @param channel RMT channel (0 - 7)
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_driver_uninstall(rmt_channel_t channel);
-
-/**
- * @brief Get the current status of eight channels.
- *
- * @note Do not call this function if it is possible that `rmt_driver_uninstall` will be called at the same time.
- *
- * @param[out] channel_status store the current status of each channel
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter is NULL
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status);
-
-/**
- * @brief RMT send waveform from rmt_item array.
- *
- *        This API allows user to send waveform with any length.
- *
- * @param channel RMT channel (0 - 7)
- * @param rmt_item head point of RMT items array.
- *        If ESP_INTR_FLAG_IRAM is used, please do not use the memory allocated from psram when calling rmt_write_items.
- * @param item_num RMT data item number.
- * @param wait_tx_done
- *        - If set 1, it will block the task and wait for sending done.
- *        - If set 0, it will not wait and return immediately.
- *
- *         @note
- *         This function will not copy data, instead, it will point to the original items,
- *         and send the waveform items.
- *         If wait_tx_done is set to true, this function will block and will not return until
- *         all items have been sent out.
- *         If wait_tx_done is set to false, this function will return immediately, and the driver
- *         interrupt will continue sending the items. We must make sure the item data will not be
- *         damaged when the driver is still sending items in driver interrupt.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t* rmt_item, int item_num, bool wait_tx_done);
-
-/**
- * @brief Wait RMT TX finished.
- *
- * @param channel RMT channel (0 - 7)
- * @param wait_time Maximum time in ticks to wait for transmission to be complete.  If set 0, return immediately with ESP_ERR_TIMEOUT if TX is busy (polling).
- *
- * @return
- *     - ESP_OK RMT Tx done successfully
- *     - ESP_ERR_TIMEOUT Exceeded the 'wait_time' given
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_FAIL Driver not installed
- */
-esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time);
-
-/**
- * @brief Get ringbuffer from RMT.
- *
- *        Users can get the RMT RX ringbuffer handle, and process the RX data.
- *
- * @param channel RMT channel (0 - 7)
- * @param buf_handle Pointer to buffer handle to accept RX ringbuffer handle.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_OK Success
- */
-esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t* buf_handle);
-
-/**
- * @brief Init rmt translator and register user callback.
- *        The callback will convert the raw data that needs to be sent to rmt format.
- *        If a channel is initialized more than once, tha user callback will be replaced by the later.
- *
- * @param channel RMT channel (0 - 7).
- * @param fn Point to the data conversion function.
- *
- * @return
- *     - ESP_FAIL Init fail.
- *     - ESP_OK Init success.
- */
-esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn);
-
-/**
- * @brief Translate uint8_t type of data into rmt format and send it out.
- *        Requires rmt_translator_init to init the translator first.
- *
- * @param channel RMT channel (0 - 7).
- * @param src Pointer to the raw data.
- * @param src_size The size of the raw data.
- * @param wait_tx_done Set true to wait all data send done.
- *
- * @return
- *     - ESP_FAIL Send fail
- *     - ESP_OK Send success
- */
-esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src_size, bool wait_tx_done);
-
-/**
- * @brief Registers a callback that will be called when transmission ends.
- *
- *        Called by rmt_driver_isr_default in interrupt context.
- *
- * @note Requires rmt_driver_install to install the default ISR handler.
- *
- * @param function Function to be called from the default interrupt handler or NULL.
- * @param arg Argument which will be provided to the callback when it is called.
- *
- * @return the previous callback settings (members will be set to NULL if there was none)
- */
-rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, void *arg);
-
-
-/*
- * ----------------EXAMPLE OF RMT INTERRUPT ------------------
- * @code{c}
- *
- * rmt_isr_register(rmt_isr, NULL, 0);           //hook the ISR handler for RMT interrupt
- * @endcode
- * @note
- *     0. If you have called rmt_driver_install, you don't need to set ISR handler any more.
- *
- * ----------------EXAMPLE OF INTERRUPT HANDLER ---------------
- * @code{c}
- * #include "esp_attr.h"
- * void IRAM_ATTR rmt_isr_handler(void* arg)
- * {
- *    //read RMT interrupt status.
- *    uint32_t intr_st = RMT.int_st.val;
- *
- *    //you will find which channels have triggered an interrupt here,
- *    //then, you can post some event to RTOS queue to process the event.
- *    //later we will add a queue in the driver code.
- *
- *   //clear RMT interrupt status.
- *    RMT.int_clr.val = intr_st;
- * }
- * @endcode
- *
- *--------------------------END OF EXAMPLE --------------------------
- */
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DRIVER_RMT_CTRL_H_ */
diff --git a/tools/sdk/include/driver/driver/rtc_cntl.h b/tools/sdk/include/driver/driver/rtc_cntl.h
deleted file mode 100644
index a79745713e4..00000000000
--- a/tools/sdk/include/driver/driver/rtc_cntl.h
+++ /dev/null
@@ -1,48 +0,0 @@
-// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <stdint.h>
-#include "esp_err.h"
-#include "esp_intr_alloc.h"
-
-/**
- * @brief Register a handler for specific RTC_CNTL interrupts
- *
- * Multiple handlers can be registered using this function. Whenever an
- * RTC interrupt happens, all handlers with matching rtc_intr_mask values
- * will be called.
- *
- * @param handler  handler function to call
- * @param handler_arg  argument to be passed to the handler
- * @param rtc_intr_mask  combination of RTC_CNTL_*_INT_ENA bits indicating the
- *                       sources to call the handler for
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NO_MEM not enough memory to allocate handler structure
- *      - other errors returned by esp_intr_alloc
- */
-esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg,
-                            uint32_t rtc_intr_mask);
-/**
- * @brief Deregister the handler previously registered using rtc_isr_register
- * @param handler  handler function to call (as passed to rtc_isr_register)
- * @param handler_arg  argument of the handler (as passed to rtc_isr_register)
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if a handler matching both handler and
- *        handler_arg isn't registered
- */
-esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg);
diff --git a/tools/sdk/include/driver/driver/rtc_io.h b/tools/sdk/include/driver/driver/rtc_io.h
deleted file mode 100644
index 4e84ea1da27..00000000000
--- a/tools/sdk/include/driver/driver/rtc_io.h
+++ /dev/null
@@ -1,276 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_RTC_GPIO_H_
-#define _DRIVER_RTC_GPIO_H_
-
-#include <stdint.h>
-#include "esp_err.h"
-#include "driver/gpio.h"
-#include "soc/rtc_gpio_channel.h"
-#include "soc/rtc_periph.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad input */
-    RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad output */
-    RTC_GPIO_MODE_INPUT_OUTPUT, /*!< Pad pull input + output */
-    RTC_GPIO_MODE_DISABLED,    /*!< Pad (output + input) disable */
-} rtc_gpio_mode_t;
-
-/**
- * @brief Determine if the specified GPIO is a valid RTC GPIO.
- *
- * @param gpio_num GPIO number
- * @return true if GPIO is valid for RTC GPIO use. false otherwise.
- */
-inline static bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num)
-{
-    return gpio_num < GPIO_PIN_COUNT
-        && rtc_gpio_desc[gpio_num].reg != 0;
-}
-
-#define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num) // Deprecated, use rtc_gpio_is_valid_gpio()
-
-/**
- * @brief Init a GPIO as RTC GPIO
- *
- * This function must be called when initializing a pad for an analog function.
- *
- * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_init(gpio_num_t gpio_num);
-
-/**
- * @brief Init a GPIO as digital GPIO
- *
- * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num);
-
-/**
- * @brief Get the RTC IO input level
- *
- * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
- *
- * @return
- *     - 1 High level
- *     - 0 Low level
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-uint32_t rtc_gpio_get_level(gpio_num_t gpio_num);
-
-/**
- * @brief Set the RTC IO output level
- *
- * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
- * @param  level output level
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level);
-
-/**
- * @brief    RTC GPIO set direction
- *
- * Configure RTC GPIO direction, such as output only, input only,
- * output and input.
- *
- * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
- * @param  mode GPIO direction
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode);
-
-/**
- * @brief  RTC GPIO pullup enable
- *
- * This function only works for RTC IOs. In general, call gpio_pullup_en,
- * which will work both for normal GPIOs and RTC IOs.
- *
- * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num);
-
-/**
- * @brief  RTC GPIO pulldown enable
- *
- * This function only works for RTC IOs. In general, call gpio_pulldown_en,
- * which will work both for normal GPIOs and RTC IOs.
- *
- * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num);
-
-/**
- * @brief  RTC GPIO pullup disable
- *
- * This function only works for RTC IOs. In general, call gpio_pullup_dis,
- * which will work both for normal GPIOs and RTC IOs.
- *
- * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num);
-
-/**
- * @brief  RTC GPIO pulldown disable
- *
- * This function only works for RTC IOs. In general, call gpio_pulldown_dis,
- * which will work both for normal GPIOs and RTC IOs.
- *
- * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num);
-
-/**
- * @brief Enable hold function on an RTC IO pad
- *
- * Enabling HOLD function will cause the pad to latch current values of
- * input enable, output enable, output value, function, drive strength values.
- * This function is useful when going into light or deep sleep mode to prevent
- * the pin configuration from changing.
- *
- * @param gpio_num GPIO number (e.g. GPIO_NUM_12)
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num);
-
-/**
- * @brief Disable hold function on an RTC IO pad
- *
- * Disabling hold function will allow the pad receive the values of
- * input enable, output enable, output value, function, drive strength from
- * RTC_IO peripheral.
- *
- * @param gpio_num GPIO number (e.g. GPIO_NUM_12)
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num);
-
-/**
- * @brief Helper function to disconnect internal circuits from an RTC IO
- * This function disables input, output, pullup, pulldown, and enables
- * hold feature for an RTC IO.
- * Use this function if an RTC IO needs to be disconnected from internal
- * circuits in deep sleep, to minimize leakage current.
- *
- * In particular, for ESP32-WROVER module, call
- * rtc_gpio_isolate(GPIO_NUM_12) before entering deep sleep, to reduce
- * deep sleep current.
- *
- * @param gpio_num GPIO number (e.g. GPIO_NUM_12).
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if GPIO is not an RTC IO
- */
-esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num);
-
-/**
- * @brief Disable force hold signal for all RTC IOs
- *
- * Each RTC pad has a "force hold" input signal from the RTC controller.
- * If this signal is set, pad latches current values of input enable,
- * function, output enable, and other signals which come from the RTC mux.
- * Force hold signal is enabled before going into deep sleep for pins which
- * are used for EXT1 wakeup.
- */
-void rtc_gpio_force_hold_dis_all();
-
-/**
- * @brief Set RTC GPIO pad drive capability
- *
- * @param gpio_num GPIO number, only support output GPIOs
- * @param strength Drive capability of the pad
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength);
-
-/**
- * @brief Get RTC GPIO pad drive capability
- *
- * @param gpio_num GPIO number, only support output GPIOs
- * @param strength Pointer to accept drive capability of the pad
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength);
-
-/**
- * @brief Enable wakeup from sleep mode using specific GPIO
- * @param gpio_num  GPIO number
- * @param intr_type  Wakeup on high level (GPIO_INTR_HIGH_LEVEL) or low level
- *                   (GPIO_INTR_LOW_LEVEL)
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if gpio_num is not an RTC IO, or intr_type is not
- *        one of GPIO_INTR_HIGH_LEVEL, GPIO_INTR_LOW_LEVEL.
- */
-esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type);
-
-/**
- * @brief Disable wakeup from sleep mode using specific GPIO
- * @param gpio_num  GPIO number
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if gpio_num is not an RTC IO
- */
-esp_err_t rtc_gpio_wakeup_disable(gpio_num_t gpio_num);
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/driver/driver/sdio_slave.h b/tools/sdk/include/driver/driver/sdio_slave.h
deleted file mode 100644
index fba650d1dca..00000000000
--- a/tools/sdk/include/driver/driver/sdio_slave.h
+++ /dev/null
@@ -1,309 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_SDIO_SLAVE_H_
-#define _DRIVER_SDIO_SLAVE_H_
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/portmacro.h"
-#include "esp_err.h"
-#include "rom/queue.h"
-
-#include "soc/sdio_slave_periph.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SDIO_SLAVE_RECV_MAX_BUFFER  (4096-4)
-
-typedef void(*sdio_event_cb_t)(uint8_t event);
-
-/// Mask of interrupts sending to the host.
-typedef enum {
-    SDIO_SLAVE_HOSTINT_SEND_NEW_PACKET =  HOST_SLC0_RX_NEW_PACKET_INT_ENA,  ///< New packet available
-    SDIO_SLAVE_HOSTINT_RECV_OVF        =  HOST_SLC0_TX_OVF_INT_ENA,         ///< Slave receive buffer overflow
-    SDIO_SLAVE_HOSTINT_SEND_UDF        =  HOST_SLC0_RX_UDF_INT_ENA,         ///< Slave sending buffer underflow (this case only happen when the host do not request for packet according to the packet len).
-    SDIO_SLAVE_HOSTINT_BIT7            =  HOST_SLC0_TOHOST_BIT7_INT_ENA,    ///< General purpose interrupt bits that can be used by the user.
-    SDIO_SLAVE_HOSTINT_BIT6            =  HOST_SLC0_TOHOST_BIT6_INT_ENA,
-    SDIO_SLAVE_HOSTINT_BIT5            =  HOST_SLC0_TOHOST_BIT5_INT_ENA,
-    SDIO_SLAVE_HOSTINT_BIT4            =  HOST_SLC0_TOHOST_BIT4_INT_ENA,
-    SDIO_SLAVE_HOSTINT_BIT3            =  HOST_SLC0_TOHOST_BIT3_INT_ENA,
-    SDIO_SLAVE_HOSTINT_BIT2            =  HOST_SLC0_TOHOST_BIT2_INT_ENA,
-    SDIO_SLAVE_HOSTINT_BIT1            =  HOST_SLC0_TOHOST_BIT1_INT_ENA,
-    SDIO_SLAVE_HOSTINT_BIT0            =  HOST_SLC0_TOHOST_BIT0_INT_ENA,
-} sdio_slave_hostint_t;
-
-/// Timing of SDIO slave
-typedef enum {
-    SDIO_SLAVE_TIMING_PSEND_PSAMPLE = 0,/**< Send at posedge, and sample at posedge. Default value for HS mode.
-                                         *   Normally there's no problem using this to work in DS mode.
-                                         */
-    SDIO_SLAVE_TIMING_NSEND_PSAMPLE    ,///< Send at negedge, and sample at posedge. Default value for DS mode and below.
-    SDIO_SLAVE_TIMING_PSEND_NSAMPLE,    ///< Send at posedge, and sample at negedge
-    SDIO_SLAVE_TIMING_NSEND_NSAMPLE,    ///< Send at negedge, and sample at negedge
-} sdio_slave_timing_t;
-
-/// Configuration of SDIO slave mode
-typedef enum {
-    SDIO_SLAVE_SEND_STREAM = 0, ///< Stream mode, all packets to send will be combined as one if possible
-    SDIO_SLAVE_SEND_PACKET = 1, ///< Packet mode, one packets will be sent one after another (only increase packet_len if last packet sent).
-} sdio_slave_sending_mode_t;
-
-/// Configuration of SDIO slave
-typedef struct {
-    sdio_slave_timing_t timing;             ///< timing of sdio_slave. see `sdio_slave_timing_t`.
-    sdio_slave_sending_mode_t sending_mode; ///< mode of sdio_slave. `SDIO_SLAVE_MODE_STREAM` if the data needs to be sent as much as possible; `SDIO_SLAVE_MODE_PACKET` if the data should be sent in packets.
-    int                 send_queue_size;    ///< max buffers that can be queued before sending.
-    size_t              recv_buffer_size;
-                            ///< If buffer_size is too small, it costs more CPU time to handle larger number of buffers.
-                            ///< If buffer_size is too large, the space larger than the transaction length is left blank but still counts a buffer, and the buffers are easily run out.
-                            ///< Should be set according to length of data really transferred.
-                            ///< All data that do not fully fill a buffer is still counted as one buffer. E.g. 10 bytes data costs 2 buffers if the size is 8 bytes per buffer.
-                            ///< Buffer size of the slave pre-defined between host and slave before communication. All receive buffer given to the driver should be larger than this.
-    sdio_event_cb_t     event_cb;           ///< when the host interrupts slave, this callback will be called with interrupt number (0-7).
-    uint32_t            flags; ///< Features to be enabled for the slave, combinations of ``SDIO_SLAVE_FLAG_*``.
-#define SDIO_SLAVE_FLAG_DAT2_DISABLED       BIT(0)      /**< It is required by the SD specification that all 4 data
-        lines should be used and pulled up even in 1-bit mode or SPI mode. However, as a feature, the user can specify
-        this flag to make use of DAT2 pin in 1-bit mode. Note that the host cannot read CCCR registers to know we don't
-        support 4-bit mode anymore, please do this at your own risk.
-        */
-#define SDIO_SLAVE_FLAG_HOST_INTR_DISABLED  BIT(1)      /**< The DAT1 line is used as the interrupt line in SDIO
-        protocol. However, as a feature, the user can specify this flag to make use of DAT1 pin of the slave in 1-bit
-        mode. Note that the host has to do polling to the interrupt registers to know whether there are interrupts from
-        the slave. And it cannot read CCCR registers to know we don't support 4-bit mode anymore, please do this at
-        your own risk.
-        */
-#define SDIO_SLAVE_FLAG_INTERNAL_PULLUP     BIT(2)      /**< Enable internal pullups for enabled pins. It is required
-        by the SD specification that all the 4 data lines should be pulled up even in 1-bit mode or SPI mode. Note that
-        the internal pull-ups are not sufficient for stable communication, please do connect external pull-ups on the
-        bus. This is only for example and debug use.
-        */
-} sdio_slave_config_t;
-
-/** Handle of a receive buffer, register a handle by calling ``sdio_slave_recv_register_buf``. Use the handle to load the buffer to the
- *  driver, or call ``sdio_slave_recv_unregister_buf`` if it is no longer used.
- */
-typedef void *sdio_slave_buf_handle_t;
-
-/** Initialize the sdio slave driver
- *
- * @param config Configuration of the sdio slave driver.
- *
- * @return
- *     - ESP_ERR_NOT_FOUND if no free interrupt found.
- *     - ESP_ERR_INVALID_STATE if already initialized.
- *     - ESP_ERR_NO_MEM if fail due to memory allocation failed.
- *     - ESP_OK if success
- */
-esp_err_t sdio_slave_initialize(sdio_slave_config_t *config);
-
-/** De-initialize the sdio slave driver to release the resources.
- */
-void sdio_slave_deinit();
-
-/** Start hardware for sending and receiving, as well as set the IOREADY1 to 1.
- *
- * @note The driver will continue sending from previous data and PKT_LEN counting, keep data received as well as start receiving from current TOKEN1 counting.
- * See ``sdio_slave_reset``.
- *
- * @return
- *  - ESP_ERR_INVALID_STATE if already started.
- *  - ESP_OK otherwise.
- */
-esp_err_t sdio_slave_start();
-
-/** Stop hardware from sending and receiving, also set IOREADY1 to 0.
- *
- * @note this will not clear the data already in the driver, and also not reset the PKT_LEN and TOKEN1 counting. Call ``sdio_slave_reset`` to do that.
- */
-void sdio_slave_stop();
-
-/** Clear the data still in the driver, as well as reset the PKT_LEN and TOKEN1 counting.
- *
- * @return always return ESP_OK.
- */
-esp_err_t sdio_slave_reset();
-
-/*---------------------------------------------------------------------------
- *                  Receive
- *--------------------------------------------------------------------------*/
-/** Register buffer used for receiving. All buffers should be registered before used, and then can be used (again) in the driver by the handle returned.
- *
- * @param start The start address of the buffer.
- *
- * @note The driver will use and only use the amount of space specified in the `recv_buffer_size` member set in the `sdio_slave_config_t`.
- *       All buffers should be larger than that. The buffer is used by the DMA, so it should be DMA capable and 32-bit aligned.
- *
- * @return The buffer handle if success, otherwise NULL.
- */
-sdio_slave_buf_handle_t sdio_slave_recv_register_buf(uint8_t *start);
-
-/** Unregister buffer from driver, and free the space used by the descriptor pointing to the buffer.
- *
- * @param handle Handle to the buffer to release.
- *
- * @return ESP_OK if success, ESP_ERR_INVALID_ARG if the handle is NULL or the buffer is being used.
- */
-esp_err_t sdio_slave_recv_unregister_buf(sdio_slave_buf_handle_t handle);
-
-/** Load buffer to the queue waiting to receive data. The driver takes ownership of the buffer until the buffer is returned by
- *  ``sdio_slave_send_get_finished`` after the transaction is finished.
- *
- * @param handle Handle to the buffer ready to receive data.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG    if invalid handle or the buffer is already in the queue. Only after the buffer is returened by
- *                              ``sdio_slave_recv`` can you load it again.
- *     - ESP_OK if success
- */
-esp_err_t sdio_slave_recv_load_buf(sdio_slave_buf_handle_t handle);
-
-/** Get received data if exist. The driver returns the ownership of the buffer to the app.
- *
- * @param handle_ret Handle to the buffer holding received data. Use this handle in ``sdio_slave_recv_load_buf`` to receive in the same buffer again.
- * @param[out] out_addr Output of the start address, set to NULL if not needed.
- * @param[out] out_len Actual length of the data in the buffer, set to NULL if not needed.
- * @param wait Time to wait before data received.
- *
- * @note Call ``sdio_slave_load_buf`` with the handle to re-load the buffer onto the link list, and receive with the same buffer again.
- *       The address and length of the buffer got here is the same as got from `sdio_slave_get_buffer`.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG    if handle_ret is NULL
- *     - ESP_ERR_TIMEOUT        if timeout before receiving new data
- *     - ESP_OK if success
- */
-esp_err_t sdio_slave_recv(sdio_slave_buf_handle_t* handle_ret, uint8_t **out_addr, size_t *out_len, TickType_t wait);
-
-/** Retrieve the buffer corresponding to a handle.
- *
- * @param handle Handle to get the buffer.
- * @param len_o Output of buffer length
- *
- * @return buffer address if success, otherwise NULL.
- */
-uint8_t* sdio_slave_recv_get_buf(sdio_slave_buf_handle_t handle, size_t *len_o);
-
-/*---------------------------------------------------------------------------
- *                  Send
- *--------------------------------------------------------------------------*/
-/** Put a new sending transfer into the send queue. The driver takes ownership of the buffer until the buffer is returned by
- *  ``sdio_slave_send_get_finished`` after the transaction is finished.
- *
- * @param addr Address for data to be sent. The buffer should be DMA capable and 32-bit aligned.
- * @param len Length of the data, should not be longer than 4092 bytes (may support longer in the future).
- * @param arg Argument to returned in ``sdio_slave_send_get_finished``. The argument can be used to indicate which transaction is done,
- *            or as a parameter for a callback. Set to NULL if not needed.
- * @param wait Time to wait if the buffer is full.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG if the length is not greater than 0.
- *     - ESP_ERR_TIMEOUT if the queue is still full until timeout.
- *     - ESP_OK if success.
- */
-esp_err_t sdio_slave_send_queue(uint8_t* addr, size_t len, void* arg, TickType_t wait);
-
-/** Return the ownership of a finished transaction.
- * @param out_arg Argument of the finished transaction. Set to NULL if unused.
- * @param wait Time to wait if there's no finished sending transaction.
- *
- * @return ESP_ERR_TIMEOUT if no transaction finished, or ESP_OK if succeed.
- */
-esp_err_t sdio_slave_send_get_finished(void** out_arg, TickType_t wait);
-
-/** Start a new sending transfer, and wait for it (blocked) to be finished.
- *
- * @param addr Start address of the buffer to send
- * @param len Length of buffer to send.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG if the length of descriptor is not greater than 0.
- *     - ESP_ERR_TIMEOUT if the queue is full or host do not start a transfer before timeout.
- *     - ESP_OK if success.
- */
-esp_err_t sdio_slave_transmit(uint8_t* addr, size_t len);
-
-/*---------------------------------------------------------------------------
- *                  Host
- *--------------------------------------------------------------------------*/
-/** Read the spi slave register shared with host.
- *
- * @param pos register address, 0-27 or 32-63.
- *
- * @note register 28 to 31 are reserved for interrupt vector.
- *
- * @return value of the register.
- */
-uint8_t sdio_slave_read_reg(int pos);
-
-/** Write the spi slave register shared with host.
- *
- * @param pos register address, 0-11, 14-15, 18-19, 24-27 and 32-63, other address are reserved.
- * @param reg the value to write.
- *
- * @note register 29 and 31 are used for interrupt vector.
- *
- * @return ESP_ERR_INVALID_ARG if address wrong, otherwise ESP_OK.
- */
-esp_err_t sdio_slave_write_reg(int pos, uint8_t reg);
-
-/** Get the interrupt enable for host.
- *
- * @return the interrupt mask.
- */
-sdio_slave_hostint_t sdio_slave_get_host_intena();
-
-/** Set the interrupt enable for host.
- *
- * @param ena Enable mask for host interrupt.
- */
-void sdio_slave_set_host_intena(sdio_slave_hostint_t ena);
-
-/** Interrupt the host by general purpose interrupt.
- *
- * @param pos Interrupt num, 0-7.
- *
- * @return
- *     - ESP_ERR_INVALID_ARG if interrupt num error
- *     - ESP_OK otherwise
- */
-esp_err_t sdio_slave_send_host_int(uint8_t pos);
-
-/** Clear general purpose interrupt to host.
- *
- * @param mask Interrupt bits to clear, by bit mask.
- */
-void sdio_slave_clear_host_int(uint8_t mask);
-
-/** Wait for general purpose interrupt from host.
- *
- * @param pos Interrupt source number to wait for.
- * is set.
- * @param wait Time to wait before interrupt triggered.
- *
- * @note this clears the interrupt at the same time.
- *
- * @return ESP_OK if success, ESP_ERR_TIMEOUT if timeout.
- */
-esp_err_t sdio_slave_wait_int(int pos, TickType_t wait);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*_DRIVER_SDIO_SLAVE_H */
-
-
diff --git a/tools/sdk/include/driver/driver/sdmmc_defs.h b/tools/sdk/include/driver/driver/sdmmc_defs.h
deleted file mode 100644
index 6ea567b8f56..00000000000
--- a/tools/sdk/include/driver/driver/sdmmc_defs.h
+++ /dev/null
@@ -1,466 +0,0 @@
-/*
- * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
- * Adaptations to ESP-IDF Copyright (c) 2016 Espressif Systems (Shanghai) PTE LTD
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _SDMMC_DEFS_H_
-#define _SDMMC_DEFS_H_
-
-#include <stdint.h>
-#include <limits.h>
-
-/* MMC commands */                              /* response type */
-#define MMC_GO_IDLE_STATE               0       /* R0 */
-#define MMC_SEND_OP_COND                1       /* R3 */
-#define MMC_ALL_SEND_CID                2       /* R2 */
-#define MMC_SET_RELATIVE_ADDR           3       /* R1 */
-#define MMC_SWITCH                      6       /* R1B */
-#define MMC_SELECT_CARD                 7       /* R1 */
-#define MMC_SEND_EXT_CSD                8       /* R1 */
-#define MMC_SEND_CSD                    9       /* R2 */
-#define MMC_SEND_CID                    10      /* R1 */
-#define MMC_READ_DAT_UNTIL_STOP         11      /* R1 */
-#define MMC_STOP_TRANSMISSION           12      /* R1B */
-#define MMC_SEND_STATUS                 13      /* R1 */
-#define MMC_SET_BLOCKLEN                16      /* R1 */
-#define MMC_READ_BLOCK_SINGLE           17      /* R1 */
-#define MMC_READ_BLOCK_MULTIPLE         18      /* R1 */
-#define MMC_WRITE_DAT_UNTIL_STOP        20      /* R1 */
-#define MMC_SET_BLOCK_COUNT             23      /* R1 */
-#define MMC_WRITE_BLOCK_SINGLE          24      /* R1 */
-#define MMC_WRITE_BLOCK_MULTIPLE        25      /* R1 */
-#define MMC_APP_CMD                     55      /* R1 */
-
-/* SD commands */                               /* response type */
-#define SD_SEND_RELATIVE_ADDR           3       /* R6 */
-#define SD_SEND_SWITCH_FUNC             6       /* R1 */
-#define SD_SEND_IF_COND                 8       /* R7 */
-#define SD_READ_OCR                     58      /* R3 */
-#define SD_CRC_ON_OFF                   59      /* R1 */
-
-/* SD application commands */                   /* response type */
-#define SD_APP_SET_BUS_WIDTH            6       /* R1 */
-#define SD_APP_SD_STATUS                13      /* R2 */
-#define SD_APP_OP_COND                  41      /* R3 */
-#define SD_APP_SEND_SCR                 51      /* R1 */
-
-/* SD IO commands */
-#define SD_IO_SEND_OP_COND              5       /* R4 */
-#define SD_IO_RW_DIRECT                 52      /* R5 */
-#define SD_IO_RW_EXTENDED               53      /* R5 */
-
-
-/* OCR bits */
-#define MMC_OCR_MEM_READY               (1<<31) /* memory power-up status bit */
-#define MMC_OCR_ACCESS_MODE_MASK        0x60000000 /* bits 30:29 */
-#define MMC_OCR_SECTOR_MODE             (1<<30)
-#define MMC_OCR_BYTE_MODE               (1<<29)
-#define MMC_OCR_3_5V_3_6V               (1<<23)
-#define MMC_OCR_3_4V_3_5V               (1<<22)
-#define MMC_OCR_3_3V_3_4V               (1<<21)
-#define MMC_OCR_3_2V_3_3V               (1<<20)
-#define MMC_OCR_3_1V_3_2V               (1<<19)
-#define MMC_OCR_3_0V_3_1V               (1<<18)
-#define MMC_OCR_2_9V_3_0V               (1<<17)
-#define MMC_OCR_2_8V_2_9V               (1<<16)
-#define MMC_OCR_2_7V_2_8V               (1<<15)
-#define MMC_OCR_2_6V_2_7V               (1<<14)
-#define MMC_OCR_2_5V_2_6V               (1<<13)
-#define MMC_OCR_2_4V_2_5V               (1<<12)
-#define MMC_OCR_2_3V_2_4V               (1<<11)
-#define MMC_OCR_2_2V_2_3V               (1<<10)
-#define MMC_OCR_2_1V_2_2V               (1<<9)
-#define MMC_OCR_2_0V_2_1V               (1<<8)
-#define MMC_OCR_1_65V_1_95V             (1<<7)
-
-#define SD_OCR_SDHC_CAP                 (1<<30)
-#define SD_OCR_VOL_MASK                 0xFF8000 /* bits 23:15 */
-
-/* SD mode R1 response type bits */
-#define MMC_R1_READY_FOR_DATA           (1<<8)  /* ready for next transfer */
-#define MMC_R1_APP_CMD                  (1<<5)  /* app. commands supported */
-#define MMC_R1_SWITCH_ERROR             (1<<7)  /* switch command did not succeed */
-
-/* SPI mode R1 response type bits */
-#define SD_SPI_R1_IDLE_STATE            (1<<0)
-#define SD_SPI_R1_ERASE_RST             (1<<1)
-#define SD_SPI_R1_ILLEGAL_CMD           (1<<2)
-#define SD_SPI_R1_CMD_CRC_ERR           (1<<3)
-#define SD_SPI_R1_ERASE_SEQ_ERR         (1<<4)
-#define SD_SPI_R1_ADDR_ERR              (1<<5)
-#define SD_SPI_R1_PARAM_ERR             (1<<6)
-#define SD_SPI_R1_NO_RESPONSE           (1<<7)
-
-/* 48-bit response decoding (32 bits w/o CRC) */
-#define MMC_R1(resp)                    ((resp)[0])
-#define MMC_R3(resp)                    ((resp)[0])
-#define MMC_R4(resp)                    ((resp)[0])
-#define MMC_R5(resp)                    ((resp)[0])
-#define SD_R6(resp)                     ((resp)[0])
-#define MMC_R1_CURRENT_STATE(resp)      (((resp)[0] >> 9) & 0xf)
-
-/* SPI mode response decoding */
-#define SD_SPI_R1(resp)                 ((resp)[0] & 0xff)
-#define SD_SPI_R2(resp)                 ((resp)[0] & 0xffff)
-#define SD_SPI_R3(resp)                 ((resp)[0])
-#define SD_SPI_R7(resp)                 ((resp)[0])
-
-/* RCA argument and response */
-#define MMC_ARG_RCA(rca)                ((rca) << 16)
-#define SD_R6_RCA(resp)                 (SD_R6((resp)) >> 16)
-
-/* bus width argument */
-#define SD_ARG_BUS_WIDTH_1              0
-#define SD_ARG_BUS_WIDTH_4              2
-
-/* EXT_CSD fields */
-#define EXT_CSD_BUS_WIDTH               183     /* WO */
-#define EXT_CSD_HS_TIMING               185     /* R/W */
-#define EXT_CSD_REV                     192     /* RO */
-#define EXT_CSD_STRUCTURE               194     /* RO */
-#define EXT_CSD_CARD_TYPE               196     /* RO */
-#define EXT_CSD_SEC_COUNT               212     /* RO */
-#define EXT_CSD_PWR_CL_26_360           203     /* RO */
-#define EXT_CSD_PWR_CL_52_360           202     /* RO */
-#define EXT_CSD_PWR_CL_26_195           201     /* RO */
-#define EXT_CSD_PWR_CL_52_195           200     /* RO */
-#define EXT_CSD_POWER_CLASS             187     /* R/W */
-#define EXT_CSD_CMD_SET                 191     /* R/W */
-#define EXT_CSD_S_CMD_SET               504     /* RO */
-
-/* EXT_CSD field definitions */
-#define EXT_CSD_CMD_SET_NORMAL          (1U << 0)
-#define EXT_CSD_CMD_SET_SECURE          (1U << 1)
-#define EXT_CSD_CMD_SET_CPSECURE        (1U << 2)
-
-/* EXT_CSD_HS_TIMING */
-#define EXT_CSD_HS_TIMING_BC            0
-#define EXT_CSD_HS_TIMING_HS            1
-#define EXT_CSD_HS_TIMING_HS200         2
-#define EXT_CSD_HS_TIMING_HS400         3
-
-/* EXT_CSD_BUS_WIDTH  */
-#define EXT_CSD_BUS_WIDTH_1             0
-#define EXT_CSD_BUS_WIDTH_4             1
-#define EXT_CSD_BUS_WIDTH_8             2
-#define EXT_CSD_BUS_WIDTH_4_DDR         5
-#define EXT_CSD_BUS_WIDTH_8_DDR         6
-
-/* EXT_CSD_CARD_TYPE */
-/* The only currently valid values for this field are 0x01, 0x03, 0x07,
- * 0x0B and 0x0F. */
-#define EXT_CSD_CARD_TYPE_F_26M         (1 << 0)        /* SDR at "rated voltages */
-#define EXT_CSD_CARD_TYPE_F_52M         (1 << 1)        /* SDR at "rated voltages */
-#define EXT_CSD_CARD_TYPE_F_52M_1_8V    (1 << 2)        /* DDR, 1.8V or 3.3V I/O */
-#define EXT_CSD_CARD_TYPE_F_52M_1_2V    (1 << 3)        /* DDR, 1.2V I/O */
-#define EXT_CSD_CARD_TYPE_26M           0x01
-#define EXT_CSD_CARD_TYPE_52M           0x03
-#define EXT_CSD_CARD_TYPE_52M_V18       0x07
-#define EXT_CSD_CARD_TYPE_52M_V12       0x0b
-#define EXT_CSD_CARD_TYPE_52M_V12_18    0x0f
-
-/* EXT_CSD MMC */
-#define EXT_CSD_MMC_SIZE 512
-
-/* MMC_SWITCH access mode */
-#define MMC_SWITCH_MODE_CMD_SET         0x00    /* Change the command set */
-#define MMC_SWITCH_MODE_SET_BITS        0x01    /* Set bits in value */
-#define MMC_SWITCH_MODE_CLEAR_BITS      0x02    /* Clear bits in value */
-#define MMC_SWITCH_MODE_WRITE_BYTE      0x03    /* Set target to value */
-
-/* MMC R2 response (CSD) */
-#define MMC_CSD_CSDVER(resp)            MMC_RSP_BITS((resp), 126, 2)
-#define  MMC_CSD_CSDVER_1_0             1
-#define  MMC_CSD_CSDVER_2_0             2
-#define  MMC_CSD_CSDVER_EXT_CSD         3
-#define MMC_CSD_MMCVER(resp)            MMC_RSP_BITS((resp), 122, 4)
-#define  MMC_CSD_MMCVER_1_0             0 /* MMC 1.0 - 1.2 */
-#define  MMC_CSD_MMCVER_1_4             1 /* MMC 1.4 */
-#define  MMC_CSD_MMCVER_2_0             2 /* MMC 2.0 - 2.2 */
-#define  MMC_CSD_MMCVER_3_1             3 /* MMC 3.1 - 3.3 */
-#define  MMC_CSD_MMCVER_4_0             4 /* MMC 4 */
-#define MMC_CSD_READ_BL_LEN(resp)       MMC_RSP_BITS((resp), 80, 4)
-#define MMC_CSD_C_SIZE(resp)            MMC_RSP_BITS((resp), 62, 12)
-#define MMC_CSD_CAPACITY(resp)          ((MMC_CSD_C_SIZE((resp))+1) << \
-                                         (MMC_CSD_C_SIZE_MULT((resp))+2))
-#define MMC_CSD_C_SIZE_MULT(resp)       MMC_RSP_BITS((resp), 47, 3)
-
-/* MMC v1 R2 response (CID) */
-#define MMC_CID_MID_V1(resp)            MMC_RSP_BITS((resp), 104, 24)
-#define MMC_CID_PNM_V1_CPY(resp, pnm)                                   \
-        do {                                                            \
-                (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
-                (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
-                (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
-                (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
-                (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
-                (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
-                (pnm)[6] = MMC_RSP_BITS((resp), 48, 8);                 \
-                (pnm)[7] = '\0';                                        \
-        } while (0)
-#define MMC_CID_REV_V1(resp)            MMC_RSP_BITS((resp), 40, 8)
-#define MMC_CID_PSN_V1(resp)            MMC_RSP_BITS((resp), 16, 24)
-#define MMC_CID_MDT_V1(resp)            MMC_RSP_BITS((resp), 8, 8)
-
-/* MMC v2 R2 response (CID) */
-#define MMC_CID_MID_V2(resp)            MMC_RSP_BITS((resp), 120, 8)
-#define MMC_CID_OID_V2(resp)            MMC_RSP_BITS((resp), 104, 16)
-#define MMC_CID_PNM_V2_CPY(resp, pnm)                                   \
-        do {                                                            \
-                (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
-                (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
-                (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
-                (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
-                (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
-                (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
-                (pnm)[6] = '\0';                                        \
-        } while (0)
-#define MMC_CID_PSN_V2(resp)            MMC_RSP_BITS((resp), 16, 32)
-
-/* SD R2 response (CSD) */
-#define SD_CSD_CSDVER(resp)             MMC_RSP_BITS((resp), 126, 2)
-#define  SD_CSD_CSDVER_1_0              0
-#define  SD_CSD_CSDVER_2_0              1
-#define SD_CSD_TAAC(resp)               MMC_RSP_BITS((resp), 112, 8)
-#define  SD_CSD_TAAC_1_5_MSEC           0x26
-#define SD_CSD_NSAC(resp)               MMC_RSP_BITS((resp), 104, 8)
-#define SD_CSD_SPEED(resp)              MMC_RSP_BITS((resp), 96, 8)
-#define  SD_CSD_SPEED_25_MHZ            0x32
-#define  SD_CSD_SPEED_50_MHZ            0x5a
-#define SD_CSD_CCC(resp)                MMC_RSP_BITS((resp), 84, 12)
-#define  SD_CSD_CCC_BASIC               (1 << 0)        /* basic */
-#define  SD_CSD_CCC_BR                  (1 << 2)        /* block read */
-#define  SD_CSD_CCC_BW                  (1 << 4)        /* block write */
-#define  SD_CSD_CCC_ERASE               (1 << 5)        /* erase */
-#define  SD_CSD_CCC_WP                  (1 << 6)        /* write protection */
-#define  SD_CSD_CCC_LC                  (1 << 7)        /* lock card */
-#define  SD_CSD_CCC_AS                  (1 << 8)        /*application specific*/
-#define  SD_CSD_CCC_IOM                 (1 << 9)        /* I/O mode */
-#define  SD_CSD_CCC_SWITCH              (1 << 10)       /* switch */
-#define SD_CSD_READ_BL_LEN(resp)        MMC_RSP_BITS((resp), 80, 4)
-#define SD_CSD_READ_BL_PARTIAL(resp)    MMC_RSP_BITS((resp), 79, 1)
-#define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
-#define SD_CSD_READ_BLK_MISALIGN(resp)  MMC_RSP_BITS((resp), 77, 1)
-#define SD_CSD_DSR_IMP(resp)            MMC_RSP_BITS((resp), 76, 1)
-#define SD_CSD_C_SIZE(resp)             MMC_RSP_BITS((resp), 62, 12)
-#define SD_CSD_CAPACITY(resp)           ((SD_CSD_C_SIZE((resp))+1) << \
-                                         (SD_CSD_C_SIZE_MULT((resp))+2))
-#define SD_CSD_V2_C_SIZE(resp)          MMC_RSP_BITS((resp), 48, 22)
-#define SD_CSD_V2_CAPACITY(resp)        ((SD_CSD_V2_C_SIZE((resp))+1) << 10) 
-#define SD_CSD_V2_BL_LEN                0x9     /* 512 */
-#define SD_CSD_VDD_R_CURR_MIN(resp)     MMC_RSP_BITS((resp), 59, 3)
-#define SD_CSD_VDD_R_CURR_MAX(resp)     MMC_RSP_BITS((resp), 56, 3)
-#define SD_CSD_VDD_W_CURR_MIN(resp)     MMC_RSP_BITS((resp), 53, 3)
-#define SD_CSD_VDD_W_CURR_MAX(resp)     MMC_RSP_BITS((resp), 50, 3)
-#define  SD_CSD_VDD_RW_CURR_100mA       0x7
-#define  SD_CSD_VDD_RW_CURR_80mA        0x6
-#define SD_CSD_C_SIZE_MULT(resp)        MMC_RSP_BITS((resp), 47, 3)
-#define SD_CSD_ERASE_BLK_EN(resp)       MMC_RSP_BITS((resp), 46, 1)
-#define SD_CSD_SECTOR_SIZE(resp)        MMC_RSP_BITS((resp), 39, 7) /* +1 */
-#define SD_CSD_WP_GRP_SIZE(resp)        MMC_RSP_BITS((resp), 32, 7) /* +1 */
-#define SD_CSD_WP_GRP_ENABLE(resp)      MMC_RSP_BITS((resp), 31, 1)
-#define SD_CSD_R2W_FACTOR(resp)         MMC_RSP_BITS((resp), 26, 3)
-#define SD_CSD_WRITE_BL_LEN(resp)       MMC_RSP_BITS((resp), 22, 4)
-#define  SD_CSD_RW_BL_LEN_2G            0xa
-#define  SD_CSD_RW_BL_LEN_1G            0x9
-#define SD_CSD_WRITE_BL_PARTIAL(resp)   MMC_RSP_BITS((resp), 21, 1)
-#define SD_CSD_FILE_FORMAT_GRP(resp)    MMC_RSP_BITS((resp), 15, 1)
-#define SD_CSD_COPY(resp)               MMC_RSP_BITS((resp), 14, 1)
-#define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
-#define SD_CSD_TMP_WRITE_PROTECT(resp)  MMC_RSP_BITS((resp), 12, 1)
-#define SD_CSD_FILE_FORMAT(resp)        MMC_RSP_BITS((resp), 10, 2)
-
-/* SD R2 response (CID) */
-#define SD_CID_MID(resp)                MMC_RSP_BITS((resp), 120, 8)
-#define SD_CID_OID(resp)                MMC_RSP_BITS((resp), 104, 16)
-#define SD_CID_PNM_CPY(resp, pnm)                                       \
-        do {                                                            \
-                (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
-                (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
-                (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
-                (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
-                (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
-                (pnm)[5] = '\0';                                        \
-        } while (0)
-#define SD_CID_REV(resp)                MMC_RSP_BITS((resp), 56, 8)
-#define SD_CID_PSN(resp)                MMC_RSP_BITS((resp), 24, 32)
-#define SD_CID_MDT(resp)                MMC_RSP_BITS((resp), 8, 12)
-
-/* SCR (SD Configuration Register) */
-#define SCR_STRUCTURE(scr)              MMC_RSP_BITS((scr), 60, 4)
-#define  SCR_STRUCTURE_VER_1_0          0 /* Version 1.0 */
-#define SCR_SD_SPEC(scr)                MMC_RSP_BITS((scr), 56, 4)
-#define  SCR_SD_SPEC_VER_1_0            0 /* Version 1.0 and 1.01 */
-#define  SCR_SD_SPEC_VER_1_10           1 /* Version 1.10 */
-#define  SCR_SD_SPEC_VER_2              2 /* Version 2.00 or Version 3.0X */
-#define SCR_DATA_STAT_AFTER_ERASE(scr)  MMC_RSP_BITS((scr), 55, 1)
-#define SCR_SD_SECURITY(scr)            MMC_RSP_BITS((scr), 52, 3)
-#define  SCR_SD_SECURITY_NONE           0 /* no security */
-#define  SCR_SD_SECURITY_1_0            1 /* security protocol 1.0 */
-#define  SCR_SD_SECURITY_1_0_2          2 /* security protocol 1.0 */
-#define SCR_SD_BUS_WIDTHS(scr)          MMC_RSP_BITS((scr), 48, 4)
-#define  SCR_SD_BUS_WIDTHS_1BIT         (1 << 0) /* 1bit (DAT0) */
-#define  SCR_SD_BUS_WIDTHS_4BIT         (1 << 2) /* 4bit (DAT0-3) */
-#define SCR_SD_SPEC3(scr)               MMC_RSP_BITS((scr), 47, 1)
-#define SCR_EX_SECURITY(scr)            MMC_RSP_BITS((scr), 43, 4)
-#define SCR_SD_SPEC4(scr)               MMC_RSP_BITS((scr), 42, 1)
-#define SCR_RESERVED(scr)               MMC_RSP_BITS((scr), 34, 8)
-#define SCR_CMD_SUPPORT_CMD23(scr)      MMC_RSP_BITS((scr), 33, 1)
-#define SCR_CMD_SUPPORT_CMD20(scr)      MMC_RSP_BITS((scr), 32, 1)
-#define SCR_RESERVED2(scr)              MMC_RSP_BITS((scr), 0, 32)
-
-/* Max supply current in SWITCH_FUNC response (in mA) */
-#define SD_SFUNC_I_MAX(status) (MMC_RSP_BITS((uint32_t *)(status), 496, 16))
-
-/* Supported flags in SWITCH_FUNC response */
-#define SD_SFUNC_SUPPORTED(status, group) \
-        (MMC_RSP_BITS((uint32_t *)(status), 400 + (group - 1) * 16, 16))
-
-/* Selected function in SWITCH_FUNC response */
-#define SD_SFUNC_SELECTED(status, group) \
-        (MMC_RSP_BITS((uint32_t *)(status), 376 + (group - 1) * 4, 4))
-
-/* Busy flags in SWITCH_FUNC response */
-#define SD_SFUNC_BUSY(status, group) \
-        (MMC_RSP_BITS((uint32_t *)(status), 272 + (group - 1) * 16, 16))
-
-/* Version of SWITCH_FUNC response */
-#define SD_SFUNC_VER(status)    (MMC_RSP_BITS((uint32_t *)(status), 368, 8))
-
-#define SD_SFUNC_GROUP_MAX      6
-#define SD_SFUNC_FUNC_MAX       15
-
-#define SD_ACCESS_MODE          1       /* Function group 1, Access Mode */
-
-#define SD_ACCESS_MODE_SDR12    0       /* 25 MHz clock */
-#define SD_ACCESS_MODE_SDR25    1       /* 50 MHz clock */
-#define SD_ACCESS_MODE_SDR50    2       /* UHS-I, 100 MHz clock */
-#define SD_ACCESS_MODE_SDR104   3       /* UHS-I, 208 MHz clock */
-#define SD_ACCESS_MODE_DDR50    4       /* UHS-I, 50 MHz clock, DDR */
-
-/**
- * @brief Extract up to 32 sequential bits from an array of 32-bit words
- *
- * Bits within the word are numbered in the increasing order from LSB to MSB.
- *
- * As an example, consider 2 32-bit words:
- *
- * 0x01234567 0x89abcdef
- *
- * On a little-endian system, the bytes are stored in memory as follows:
- *
- * 67 45 23 01 ef cd ab 89
- *
- * MMC_RSP_BITS will extact bits as follows:
- *
- * start=0  len=4   -> result=0x00000007
- * start=0  len=12  -> result=0x00000567
- * start=28 len=8   -> result=0x000000f0
- * start=59 len=5   -> result=0x00000011
- *
- * @param src array of words to extract bits from
- * @param start index of the first bit to extract
- * @param len number of bits to extract, 1 to 32
- * @return 32-bit word where requested bits start from LSB
- */
-static inline uint32_t MMC_RSP_BITS(uint32_t *src, int start, int len)
-{
-    uint32_t mask = (len % 32 == 0) ? UINT_MAX : UINT_MAX >> (32 - (len % 32));
-    size_t word = start / 32;
-    size_t shift = start % 32;
-    uint32_t right = src[word] >> shift;
-    uint32_t left = (len + shift <= 32) ? 0 : src[word + 1] << ((32 - shift) % 32);
-    return (left | right) & mask;
-}
-
-/* SD R4 response (IO OCR) */
-#define SD_IO_OCR_MEM_READY             (1<<31)
-#define SD_IO_OCR_NUM_FUNCTIONS(ocr)    (((ocr) >> 28) & 0x7)
-#define SD_IO_OCR_MEM_PRESENT       (1<<27)
-#define SD_IO_OCR_MASK              0x00fffff0
-
-/* CMD52 arguments */
-#define SD_ARG_CMD52_READ           (0<<31)
-#define SD_ARG_CMD52_WRITE          (1<<31)
-#define SD_ARG_CMD52_FUNC_SHIFT     28
-#define SD_ARG_CMD52_FUNC_MASK      0x7
-#define SD_ARG_CMD52_EXCHANGE       (1<<27)
-#define SD_ARG_CMD52_REG_SHIFT      9
-#define SD_ARG_CMD52_REG_MASK       0x1ffff
-#define SD_ARG_CMD52_DATA_SHIFT     0
-#define SD_ARG_CMD52_DATA_MASK      0xff
-#define SD_R5_DATA(resp)            ((resp)[0] & 0xff)
-
-/* CMD53 arguments */
-#define SD_ARG_CMD53_READ           (0<<31)
-#define SD_ARG_CMD53_WRITE          (1<<31)
-#define SD_ARG_CMD53_FUNC_SHIFT     28
-#define SD_ARG_CMD53_FUNC_MASK      0x7
-#define SD_ARG_CMD53_BLOCK_MODE     (1<<27)
-#define SD_ARG_CMD53_INCREMENT      (1<<26)
-#define SD_ARG_CMD53_REG_SHIFT      9
-#define SD_ARG_CMD53_REG_MASK       0x1ffff
-#define SD_ARG_CMD53_LENGTH_SHIFT   0
-#define SD_ARG_CMD53_LENGTH_MASK    0x1ff
-#define SD_ARG_CMD53_LENGTH_MAX     512
-
-/* Card Common Control Registers (CCCR) */
-#define SD_IO_CCCR_START            0x00000
-#define SD_IO_CCCR_SIZE             0x100
-#define SD_IO_CCCR_FN_ENABLE        0x02
-#define SD_IO_CCCR_FN_READY         0x03
-#define SD_IO_CCCR_INT_ENABLE       0x04
-#define SD_IO_CCCR_INT_PENDING      0x05
-#define SD_IO_CCCR_CTL              0x06
-#define  CCCR_CTL_RES               (1<<3)
-#define SD_IO_CCCR_BUS_WIDTH        0x07
-#define  CCCR_BUS_WIDTH_1           (0<<0)
-#define  CCCR_BUS_WIDTH_4           (2<<0)
-#define  CCCR_BUS_WIDTH_8           (3<<0)
-#define SD_IO_CCCR_CARD_CAP         0x08
-#define  CCCR_CARD_CAP_LSC          BIT(6)
-#define  CCCR_CARD_CAP_4BLS         BIT(7)
-#define SD_IO_CCCR_CISPTR           0x09
-#define SD_IO_CCCR_BLKSIZEL         0x10
-#define SD_IO_CCCR_BLKSIZEH         0x11
-#define SD_IO_CCCR_HIGHSPEED        0x13
-#define  CCCR_HIGHSPEED_SUPPORT     BIT(0)
-#define  CCCR_HIGHSPEED_ENABLE      BIT(1)
-
-/* Function Basic Registers (FBR) */
-#define SD_IO_FBR_START         0x00100
-#define SD_IO_FBR_SIZE          0x00700
-
-/* Card Information Structure (CIS) */
-#define SD_IO_CIS_START         0x01000
-#define SD_IO_CIS_SIZE          0x17000
-
-/* CIS tuple codes (based on PC Card 16) */
-#define SD_IO_CISTPL_NULL       0x00
-#define SD_IO_CISTPL_VERS_1     0x15
-#define SD_IO_CISTPL_MANFID     0x20
-#define SD_IO_CISTPL_FUNCID     0x21
-#define SD_IO_CISTPL_FUNCE      0x22
-#define SD_IO_CISTPL_END        0xff
-
-/* CISTPL_FUNCID codes */
-#define TPLFID_FUNCTION_SDIO        0x0c
-
-/* Timing */
-#define SDMMC_TIMING_LEGACY 0
-#define SDMMC_TIMING_HIGHSPEED 1
-#define SDMMC_TIMING_MMC_DDR52 2
-
-#endif //_SDMMC_DEFS_H_
diff --git a/tools/sdk/include/driver/driver/sdmmc_host.h b/tools/sdk/include/driver/driver/sdmmc_host.h
deleted file mode 100644
index 4d94d03c7cd..00000000000
--- a/tools/sdk/include/driver/driver/sdmmc_host.h
+++ /dev/null
@@ -1,242 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <stdint.h>
-#include <stddef.h>
-#include "esp_err.h"
-#include "sdmmc_types.h"
-#include "driver/gpio.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SDMMC_HOST_SLOT_0     0     ///< SDMMC slot 0
-#define SDMMC_HOST_SLOT_1     1     ///< SDMMC slot 1
-
-/**
- * @brief Default sdmmc_host_t structure initializer for SDMMC peripheral
- *
- * Uses SDMMC peripheral, with 4-bit mode enabled, and max frequency set to 20MHz
- */
-#define SDMMC_HOST_DEFAULT() {\
-    .flags = SDMMC_HOST_FLAG_8BIT | \
-             SDMMC_HOST_FLAG_4BIT | \
-             SDMMC_HOST_FLAG_1BIT | \
-             SDMMC_HOST_FLAG_DDR, \
-    .slot = SDMMC_HOST_SLOT_1, \
-    .max_freq_khz = SDMMC_FREQ_DEFAULT, \
-    .io_voltage = 3.3f, \
-    .init = &sdmmc_host_init, \
-    .set_bus_width = &sdmmc_host_set_bus_width, \
-    .get_bus_width = &sdmmc_host_get_slot_width, \
-    .set_bus_ddr_mode = &sdmmc_host_set_bus_ddr_mode, \
-    .set_card_clk = &sdmmc_host_set_card_clk, \
-    .do_transaction = &sdmmc_host_do_transaction, \
-    .deinit = &sdmmc_host_deinit, \
-    .io_int_enable = sdmmc_host_io_int_enable, \
-    .io_int_wait = sdmmc_host_io_int_wait, \
-    .command_timeout_ms = 0, \
-}
-
-/**
- * Extra configuration for SDMMC peripheral slot
- */
-typedef struct {
-    gpio_num_t gpio_cd;     ///< GPIO number of card detect signal
-    gpio_num_t gpio_wp;     ///< GPIO number of write protect signal
-    uint8_t width;          ///< Bus width used by the slot (might be less than the max width supported)
-    uint32_t flags;         ///< Features used by this slot
-#define SDMMC_SLOT_FLAG_INTERNAL_PULLUP  BIT(0) 
-        /**< Enable internal pullups on enabled pins. The internal pullups
-         are insufficient however, please make sure external pullups are
-         connected on the bus. This is for debug / example purpose only.
-         */
-} sdmmc_slot_config_t;
-
-#define SDMMC_SLOT_NO_CD      ((gpio_num_t) -1)     ///< indicates that card detect line is not used
-#define SDMMC_SLOT_NO_WP      ((gpio_num_t) -1)     ///< indicates that write protect line is not used
-#define SDMMC_SLOT_WIDTH_DEFAULT 0 ///< use the default width for the slot (8 for slot 0, 4 for slot 1)
-
-/**
- * Macro defining default configuration of SDMMC host slot
- */
-#define SDMMC_SLOT_CONFIG_DEFAULT() {\
-    .gpio_cd = SDMMC_SLOT_NO_CD, \
-    .gpio_wp = SDMMC_SLOT_NO_WP, \
-    .width   = SDMMC_SLOT_WIDTH_DEFAULT, \
-    .flags = 0, \
-}
-
-/**
- * @brief Initialize SDMMC host peripheral
- *
- * @note This function is not thread safe
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if sdmmc_host_init was already called
- *      - ESP_ERR_NO_MEM if memory can not be allocated
- */
-esp_err_t sdmmc_host_init();
-
-/**
- * @brief Initialize given slot of SDMMC peripheral
- *
- * On the ESP32, SDMMC peripheral has two slots:
- *  - Slot 0: 8-bit wide, maps to HS1_* signals in PIN MUX
- *  - Slot 1: 4-bit wide, maps to HS2_* signals in PIN MUX
- *
- * Card detect and write protect signals can be routed to
- * arbitrary GPIOs using GPIO matrix.
- *
- * @note This function is not thread safe
- *
- * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
- * @param slot_config  additional configuration for the slot
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if host has not been initialized using sdmmc_host_init
- */
-esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t* slot_config);
-
-/**
- * @brief Select bus width to be used for data transfer
- *
- * SD/MMC card must be initialized prior to this command, and a command to set
- * bus width has to be sent to the card (e.g. SD_APP_SET_BUS_WIDTH)
- *
- * @note This function is not thread safe
- *
- * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
- * @param width  bus width (1, 4, or 8 for slot 0; 1 or 4 for slot 1)
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if slot number or width is not valid
- */
-esp_err_t sdmmc_host_set_bus_width(int slot, size_t width);
-
-/**
- * @brief Get bus width configured in ``sdmmc_host_init_slot`` to be used for data transfer
- *
- * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
- * @return configured bus width of the specified slot.
- */
-size_t sdmmc_host_get_slot_width(int slot);
-
-/**
- * @brief Set card clock frequency
- *
- * Currently only integer fractions of 40MHz clock can be used.
- * For High Speed cards, 40MHz can be used.
- * For Default Speed cards, 20MHz can be used.
- *
- * @note This function is not thread safe
- *
- * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
- * @param freq_khz  card clock frequency, in kHz
- * @return
- *      - ESP_OK on success
- *      - other error codes may be returned in the future
- */
-esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz);
-
-/**
- * @brief Enable or disable DDR mode of SD interface
- * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
- * @param ddr_enabled  enable or disable DDR mode
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NOT_SUPPORTED if DDR mode is not supported on this slot
- */
-esp_err_t sdmmc_host_set_bus_ddr_mode(int slot, bool ddr_enabled);
-
-/**
- * @brief Send command to the card and get response
- *
- * This function returns when command is sent and response is received,
- * or data is transferred, or timeout occurs.
- *
- * @note This function is not thread safe w.r.t. init/deinit functions,
- *       and bus width/clock speed configuration functions. Multiple tasks
- *       can call sdmmc_host_do_transaction as long as other sdmmc_host_*
- *       functions are not called.
- *
- * @attention Data buffer passed in cmdinfo->data must be in DMA capable memory
- *
- * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
- * @param cmdinfo   pointer to structure describing command and data to transfer
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_TIMEOUT if response or data transfer has timed out
- *      - ESP_ERR_INVALID_CRC if response or data transfer CRC check has failed
- *      - ESP_ERR_INVALID_RESPONSE if the card has sent an invalid response
- *      - ESP_ERR_INVALID_SIZE if the size of data transfer is not valid in SD protocol
- *      - ESP_ERR_INVALID_ARG if the data buffer is not in DMA capable memory
- */
-esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo);
-
-/**
- * @brief Enable IO interrupts
- *
- * This function configures the host to accept SDIO interrupts.
- *
- * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
- * @return returns ESP_OK, other errors possible in the future
- */
-esp_err_t sdmmc_host_io_int_enable(int slot);
-
-/**
- * @brief Block until an SDIO interrupt is received, or timeout occurs
- * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
- * @param timeout_ticks  number of RTOS ticks to wait for the interrupt
- * @return
- *  - ESP_OK on success (interrupt received)
- *  - ESP_ERR_TIMEOUT if the interrupt did not occur within timeout_ticks
- */
-esp_err_t sdmmc_host_io_int_wait(int slot, TickType_t timeout_ticks);
-
-/**
- * @brief Disable SDMMC host and release allocated resources
- *
- * @note This function is not thread safe
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if sdmmc_host_init function has not been called
- */
-esp_err_t sdmmc_host_deinit();
-
-/**
- * @brief Enable the pull-ups of sd pins.
- * 
- * @note You should always place actual pullups on the lines instead of using
- * this function. Internal pullup resistance are high and not sufficient, may
- * cause instability in products. This is for debug or examples only.
- * 
- * @param slot Slot to use, normally set it to 1.
- * @param width Bit width of your configuration, 1 or 4.
- * 
- * @return
- *      - ESP_OK: if success
- *      - ESP_ERR_INVALID_ARG: if configured width larger than maximum the slot can
- *              support
- */
-esp_err_t sdmmc_host_pullup_en(int slot, int width);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/driver/driver/sdmmc_types.h b/tools/sdk/include/driver/driver/sdmmc_types.h
deleted file mode 100644
index 369a9210f8b..00000000000
--- a/tools/sdk/include/driver/driver/sdmmc_types.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
- * Adaptations to ESP-IDF Copyright (c) 2016 Espressif Systems (Shanghai) PTE LTD
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _SDMMC_TYPES_H_
-#define _SDMMC_TYPES_H_
-
-#include <stdint.h>
-#include <stddef.h>
-#include "esp_err.h"
-#include "freertos/FreeRTOS.h"
-
-/**
- * Decoded values from SD card Card Specific Data register
- */
-typedef struct {
-    int csd_ver;                /*!< CSD structure format */
-    int mmc_ver;                /*!< MMC version (for CID format) */
-    int capacity;               /*!< total number of sectors */
-    int sector_size;            /*!< sector size in bytes */
-    int read_block_len;         /*!< block length for reads */
-    int card_command_class;     /*!< Card Command Class for SD */
-    int tr_speed;               /*!< Max transfer speed */
-} sdmmc_csd_t;
-
-/**
- * Decoded values from SD card Card IDentification register
- */
-typedef struct {
-    int mfg_id;     /*!< manufacturer identification number */
-    int oem_id;     /*!< OEM/product identification number */
-    char name[8];   /*!< product name (MMC v1 has the longest) */
-    int revision;   /*!< product revision */
-    int serial;     /*!< product serial number */
-    int date;       /*!< manufacturing date */
-} sdmmc_cid_t;
-
-/**
- * Decoded values from SD Configuration Register
- */
-typedef struct {
-    int sd_spec;    /*!< SD Physical layer specification version, reported by card */
-    int bus_width;  /*!< bus widths supported by card: BIT(0) — 1-bit bus, BIT(2) — 4-bit bus */
-} sdmmc_scr_t;
-
-/**
- * Decoded values of Extended Card Specific Data
- */
-typedef struct {
-    uint8_t power_class;    /*!< Power class used by the card */
-} sdmmc_ext_csd_t;
-
-/**
- * SD/MMC command response buffer
- */
-typedef uint32_t sdmmc_response_t[4];
-
-/**
- * SD SWITCH_FUNC response buffer
- */
-typedef struct {
-    uint32_t data[512 / 8 / sizeof(uint32_t)];  /*!< response data */
-} sdmmc_switch_func_rsp_t;
-
-/**
- * SD/MMC command information
- */
-typedef struct {
-        uint32_t opcode;            /*!< SD or MMC command index */
-        uint32_t arg;               /*!< SD/MMC command argument */
-        sdmmc_response_t response;  /*!< response buffer */
-        void* data;                 /*!< buffer to send or read into */
-        size_t datalen;             /*!< length of data buffer */
-        size_t blklen;              /*!< block length */
-        int flags;                  /*!< see below */
-/** @cond */
-#define SCF_ITSDONE      0x0001     /*!< command is complete */
-#define SCF_CMD(flags)   ((flags) & 0x00f0)
-#define SCF_CMD_AC       0x0000
-#define SCF_CMD_ADTC     0x0010
-#define SCF_CMD_BC       0x0020
-#define SCF_CMD_BCR      0x0030
-#define SCF_CMD_READ     0x0040     /*!< read command (data expected) */
-#define SCF_RSP_BSY      0x0100
-#define SCF_RSP_136      0x0200
-#define SCF_RSP_CRC      0x0400
-#define SCF_RSP_IDX      0x0800
-#define SCF_RSP_PRESENT  0x1000
-/* response types */
-#define SCF_RSP_R0       0 /*!< none */
-#define SCF_RSP_R1       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
-#define SCF_RSP_R1B      (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
-#define SCF_RSP_R2       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136)
-#define SCF_RSP_R3       (SCF_RSP_PRESENT)
-#define SCF_RSP_R4       (SCF_RSP_PRESENT)
-#define SCF_RSP_R5       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
-#define SCF_RSP_R5B      (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
-#define SCF_RSP_R6       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
-#define SCF_RSP_R7       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
-/* special flags */
-#define SCF_WAIT_BUSY    0x2000     /*!< Wait for completion of card busy signal before returning */
-/** @endcond */
-        esp_err_t error;            /*!< error returned from transfer */
-        int timeout_ms;             /*!< response timeout, in milliseconds */
-} sdmmc_command_t;
-
-/**
- * SD/MMC Host description
- *
- * This structure defines properties of SD/MMC host and functions
- * of SD/MMC host which can be used by upper layers.
- */
-typedef struct {
-    uint32_t flags;             /*!< flags defining host properties */
-#define SDMMC_HOST_FLAG_1BIT    BIT(0)      /*!< host supports 1-line SD and MMC protocol */
-#define SDMMC_HOST_FLAG_4BIT    BIT(1)      /*!< host supports 4-line SD and MMC protocol */
-#define SDMMC_HOST_FLAG_8BIT    BIT(2)      /*!< host supports 8-line MMC protocol */
-#define SDMMC_HOST_FLAG_SPI     BIT(3)      /*!< host supports SPI protocol */
-#define SDMMC_HOST_FLAG_DDR     BIT(4)      /*!< host supports DDR mode for SD/MMC */
-    int slot;                   /*!< slot number, to be passed to host functions */
-    int max_freq_khz;           /*!< max frequency supported by the host */
-#define SDMMC_FREQ_DEFAULT      20000       /*!< SD/MMC Default speed (limited by clock divider) */
-#define SDMMC_FREQ_HIGHSPEED    40000       /*!< SD High speed (limited by clock divider) */
-#define SDMMC_FREQ_PROBING      400         /*!< SD/MMC probing speed */
-#define SDMMC_FREQ_52M          52000       /*!< MMC 52MHz speed */
-#define SDMMC_FREQ_26M          26000       /*!< MMC 26MHz speed */
-    float io_voltage;           /*!< I/O voltage used by the controller (voltage switching is not supported) */
-    esp_err_t (*init)(void);    /*!< Host function to initialize the driver */
-    esp_err_t (*set_bus_width)(int slot, size_t width);    /*!< host function to set bus width */
-    size_t (*get_bus_width)(int slot); /*!< host function to get bus width */
-    esp_err_t (*set_bus_ddr_mode)(int slot, bool ddr_enable); /*!< host function to set DDR mode */
-    esp_err_t (*set_card_clk)(int slot, uint32_t freq_khz); /*!< host function to set card clock frequency */
-    esp_err_t (*do_transaction)(int slot, sdmmc_command_t* cmdinfo);    /*!< host function to do a transaction */
-    esp_err_t (*deinit)(void);  /*!< host function to deinitialize the driver */
-    esp_err_t (*io_int_enable)(int slot); /*!< Host function to enable SDIO interrupt line */
-    esp_err_t (*io_int_wait)(int slot, TickType_t timeout_ticks); /*!< Host function to wait for SDIO interrupt line to be active */
-    int command_timeout_ms;     /*!< timeout, in milliseconds, of a single command. Set to 0 to use the default value. */
-} sdmmc_host_t;
-
-/**
- * SD/MMC card information structure
- */
-typedef struct {
-    sdmmc_host_t host;          /*!< Host with which the card is associated */
-    uint32_t ocr;               /*!< OCR (Operation Conditions Register) value */
-    sdmmc_cid_t cid;            /*!< decoded CID (Card IDentification) register value */
-    sdmmc_csd_t csd;            /*!< decoded CSD (Card-Specific Data) register value */
-    sdmmc_scr_t scr;            /*!< decoded SCR (SD card Configuration Register) value */
-    sdmmc_ext_csd_t ext_csd;    /*!< decoded EXT_CSD (Extended Card Specific Data) register value */
-    uint16_t rca;               /*!< RCA (Relative Card Address) */
-    uint16_t max_freq_khz;      /*!< Maximum frequency, in kHz, supported by the card */
-    uint32_t is_mem : 1;        /*!< Bit indicates if the card is a memory card */
-    uint32_t is_sdio : 1;       /*!< Bit indicates if the card is an IO card */
-    uint32_t is_mmc : 1;        /*!< Bit indicates if the card is MMC */
-    uint32_t num_io_functions : 3;  /*!< If is_sdio is 1, contains the number of IO functions on the card */
-    uint32_t log_bus_width : 2; /*!< log2(bus width supported by card) */
-    uint32_t is_ddr : 1;        /*!< Card supports DDR mode */
-    uint32_t reserved : 23;     /*!< Reserved for future expansion */
-} sdmmc_card_t;
-
-
-#endif // _SDMMC_TYPES_H_
diff --git a/tools/sdk/include/driver/driver/sdspi_host.h b/tools/sdk/include/driver/driver/sdspi_host.h
deleted file mode 100644
index 1b3b67017e1..00000000000
--- a/tools/sdk/include/driver/driver/sdspi_host.h
+++ /dev/null
@@ -1,161 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <stdint.h>
-#include <stddef.h>
-#include "esp_err.h"
-#include "sdmmc_types.h"
-#include "driver/gpio.h"
-#include "driver/spi_master.h"
-#include "driver/sdmmc_host.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Default sdmmc_host_t structure initializer for SD over SPI driver
- *
- * Uses SPI mode and max frequency set to 20MHz
- *
- * 'slot' can be set to one of HSPI_HOST, VSPI_HOST.
- */
-#define SDSPI_HOST_DEFAULT() {\
-    .flags = SDMMC_HOST_FLAG_SPI, \
-    .slot = HSPI_HOST, \
-    .max_freq_khz = SDMMC_FREQ_DEFAULT, \
-    .io_voltage = 3.3f, \
-    .init = &sdspi_host_init, \
-    .set_bus_width = NULL, \
-    .get_bus_width = NULL, \
-    .set_bus_ddr_mode = NULL, \
-    .set_card_clk = &sdspi_host_set_card_clk, \
-    .do_transaction = &sdspi_host_do_transaction, \
-    .deinit = &sdspi_host_deinit, \
-    .io_int_enable = NULL, \
-    .io_int_wait = NULL, \
-    .command_timeout_ms = 0, \
-}
-
-/**
- * Extra configuration for SPI host
- */
-typedef struct {
-    gpio_num_t gpio_miso;   ///< GPIO number of MISO signal
-    gpio_num_t gpio_mosi;   ///< GPIO number of MOSI signal
-    gpio_num_t gpio_sck;    ///< GPIO number of SCK signal
-    gpio_num_t gpio_cs;     ///< GPIO number of CS signal
-    gpio_num_t gpio_cd;     ///< GPIO number of card detect signal
-    gpio_num_t gpio_wp;     ///< GPIO number of write protect signal
-    int dma_channel;        ///< DMA channel to be used by SPI driver (1 or 2)
-} sdspi_slot_config_t;
-
-#define SDSPI_SLOT_NO_CD    ((gpio_num_t) -1)   ///< indicates that card detect line is not used
-#define SDSPI_SLOT_NO_WP    ((gpio_num_t) -1)   ///< indicates that write protect line is not used
-
-/**
- * Macro defining default configuration of SPI host
- */
-#define SDSPI_SLOT_CONFIG_DEFAULT() {\
-    .gpio_miso = GPIO_NUM_2, \
-    .gpio_mosi = GPIO_NUM_15, \
-    .gpio_sck  = GPIO_NUM_14, \
-    .gpio_cs   = GPIO_NUM_13, \
-    .gpio_cd   = SDSPI_SLOT_NO_CD, \
-    .gpio_wp   = SDSPI_SLOT_NO_WP, \
-    .dma_channel = 1 \
-}
-
-/**
- * @brief Initialize SD SPI driver
- *
- * @note This function is not thread safe
- *
- * @return
- *      - ESP_OK on success
- *      - other error codes may be returned in future versions
- */
-esp_err_t sdspi_host_init();
-
-/**
-* @brief Initialize SD SPI driver for the specific SPI controller
-*
-* @note This function is not thread safe
-*
-* @param slot         SPI controller to use (HSPI_HOST or VSPI_HOST)
-* @param slot_config  pointer to slot configuration structure
-*
-* @return
-*      - ESP_OK on success
-*      - ESP_ERR_INVALID_ARG if sdspi_init_slot has invalid arguments
-*      - ESP_ERR_NO_MEM if memory can not be allocated
-*      - other errors from the underlying spi_master and gpio drivers
-*/
-esp_err_t sdspi_host_init_slot(int slot, const sdspi_slot_config_t* slot_config);
-
-/**
- * @brief Send command to the card and get response
- *
- * This function returns when command is sent and response is received,
- * or data is transferred, or timeout occurs.
- *
- * @note This function is not thread safe w.r.t. init/deinit functions,
- *       and bus width/clock speed configuration functions. Multiple tasks
- *       can call sdspi_host_do_transaction as long as other sdspi_host_*
- *       functions are not called.
- *
- * @param slot      SPI controller (HSPI_HOST or VSPI_HOST)
- * @param cmdinfo   pointer to structure describing command and data to transfer
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_TIMEOUT if response or data transfer has timed out
- *      - ESP_ERR_INVALID_CRC if response or data transfer CRC check has failed
- *      - ESP_ERR_INVALID_RESPONSE if the card has sent an invalid response
- */
-esp_err_t sdspi_host_do_transaction(int slot, sdmmc_command_t *cmdinfo);
-
-/**
- * @brief Set card clock frequency
- *
- * Currently only integer fractions of 40MHz clock can be used.
- * For High Speed cards, 40MHz can be used.
- * For Default Speed cards, 20MHz can be used.
- *
- * @note This function is not thread safe
- *
- * @param slot      SPI controller (HSPI_HOST or VSPI_HOST)
- * @param freq_khz  card clock frequency, in kHz
- * @return
- *      - ESP_OK on success
- *      - other error codes may be returned in the future
- */
-esp_err_t sdspi_host_set_card_clk(int slot, uint32_t freq_khz);
-
-
-/**
- * @brief Release resources allocated using sdspi_host_init
- *
- * @note This function is not thread safe
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if sdspi_host_init function has not been called
- */
-esp_err_t sdspi_host_deinit();
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/driver/driver/sigmadelta.h b/tools/sdk/include/driver/driver/sigmadelta.h
deleted file mode 100644
index b62d937a533..00000000000
--- a/tools/sdk/include/driver/driver/sigmadelta.h
+++ /dev/null
@@ -1,109 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __DRIVER_SIGMADELTA_H__
-#define __DRIVER_SIGMADELTA_H__
-#include <esp_types.h>
-#include "soc/gpio_sd_struct.h"
-#include "soc/gpio_sd_reg.h"
-#include "driver/gpio.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Sigma-delta channel list
- */
-typedef enum{
-    SIGMADELTA_CHANNEL_0 = 0,         /*!< Sigma-delta channel 0 */
-    SIGMADELTA_CHANNEL_1 = 1,         /*!< Sigma-delta channel 1 */
-    SIGMADELTA_CHANNEL_2 = 2,         /*!< Sigma-delta channel 2 */
-    SIGMADELTA_CHANNEL_3 = 3,         /*!< Sigma-delta channel 3 */
-    SIGMADELTA_CHANNEL_4 = 4,         /*!< Sigma-delta channel 4 */
-    SIGMADELTA_CHANNEL_5 = 5,         /*!< Sigma-delta channel 5 */
-    SIGMADELTA_CHANNEL_6 = 6,         /*!< Sigma-delta channel 6 */
-    SIGMADELTA_CHANNEL_7 = 7,         /*!< Sigma-delta channel 7 */
-    SIGMADELTA_CHANNEL_MAX,
-} sigmadelta_channel_t;
-
-/**
- * @brief Sigma-delta configure struct
- */
-typedef struct {
-    sigmadelta_channel_t channel;    /*!< Sigma-delta channel number */
-    int8_t sigmadelta_duty;          /*!< Sigma-delta duty, duty ranges from -128 to 127. */
-    uint8_t sigmadelta_prescale;     /*!< Sigma-delta prescale, prescale ranges from 0 to 255. */
-    uint8_t  sigmadelta_gpio;        /*!< Sigma-delta output io number, refer to gpio.h for more details. */
-} sigmadelta_config_t;
-
-/**
- * @brief Configure Sigma-delta channel
- *
- * @param  config Pointer of Sigma-delta channel configuration struct
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t sigmadelta_config(const sigmadelta_config_t *config);
-
-/**
- * @brief Set Sigma-delta channel duty.
- *
- *        This function is used to set Sigma-delta channel duty,
- *        If you add a capacitor between the output pin and ground,
- *        the average output voltage will be Vdc = VDDIO / 256 * duty + VDDIO/2,
- *        where VDDIO is the power supply voltage.
- *
- * @param channel Sigma-delta channel number
- * @param duty Sigma-delta duty of one channel, the value ranges from -128 to 127, recommended range is -90 ~ 90.
- *             The waveform is more like a random one in this range.
- *                                
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t sigmadelta_set_duty(sigmadelta_channel_t channel, int8_t duty);
-
-/**
- * @brief Set Sigma-delta channel's clock pre-scale value.
- *        The source clock is APP_CLK, 80MHz. The clock frequency of the sigma-delta channel is APP_CLK / pre_scale
- *
- * @param channel Sigma-delta channel number
- * @param prescale The divider of source clock, ranges from 0 to 255
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t sigmadelta_set_prescale(sigmadelta_channel_t channel, uint8_t prescale);
-
-/**
- * @brief Set Sigma-delta signal output pin
- *
- * @param channel Sigma-delta channel number
- * @param gpio_num GPIO number of output pin.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t sigmadelta_set_pin(sigmadelta_channel_t channel, gpio_num_t gpio_num);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/driver/driver/spi_common.h b/tools/sdk/include/driver/driver/spi_common.h
deleted file mode 100644
index c2d645566e9..00000000000
--- a/tools/sdk/include/driver/driver/spi_common.h
+++ /dev/null
@@ -1,356 +0,0 @@
-// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef _DRIVER_SPI_COMMON_H_
-#define _DRIVER_SPI_COMMON_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-#include "rom/lldesc.h"
-#include "soc/spi_periph.h"
-#include "sdkconfig.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-//Maximum amount of bytes that can be put in one DMA descriptor
-#define SPI_MAX_DMA_LEN (4096-4)
-
-/**
- * Transform unsigned integer of length <= 32 bits to the format which can be
- * sent by the SPI driver directly.
- *
- * E.g. to send 9 bits of data, you can:
- *
- *      uint16_t data = SPI_SWAP_DATA_TX(0x145, 9);
- *
- * Then points tx_buffer to ``&data``.
- *
- * @param DATA Data to be sent, can be uint8_t, uint16_t or uint32_t.
- * @param LEN Length of data to be sent, since the SPI peripheral sends from
- *      the MSB, this helps to shift the data to the MSB.
- */
-#define SPI_SWAP_DATA_TX(DATA, LEN) __builtin_bswap32((uint32_t)(DATA)<<(32-(LEN)))
-
-/**
- * Transform received data of length <= 32 bits to the format of an unsigned integer.
- *
- * E.g. to transform the data of 15 bits placed in a 4-byte array to integer:
- *
- *      uint16_t data = SPI_SWAP_DATA_RX(*(uint32_t*)t->rx_data, 15);
- *
- * @param DATA Data to be rearranged, can be uint8_t, uint16_t or uint32_t.
- * @param LEN Length of data received, since the SPI peripheral writes from
- *      the MSB, this helps to shift the data to the LSB.
- */
-#define SPI_SWAP_DATA_RX(DATA, LEN) (__builtin_bswap32(DATA)>>(32-(LEN)))
-
-/**
- * @brief Enum with the three SPI peripherals that are software-accessible in it
- */
-typedef enum {
-    SPI_HOST=0,                     ///< SPI1, SPI
-    HSPI_HOST=1,                    ///< SPI2, HSPI
-    VSPI_HOST=2                     ///< SPI3, VSPI
-} spi_host_device_t;
-
-/**
- * @brief This is a configuration structure for a SPI bus.
- *
- * You can use this structure to specify the GPIO pins of the bus. Normally, the driver will use the
- * GPIO matrix to route the signals. An exception is made when all signals either can be routed through
- * the IO_MUX or are -1. In that case, the IO_MUX is used, allowing for >40MHz speeds.
- *
- * @note Be advised that the slave driver does not use the quadwp/quadhd lines and fields in spi_bus_config_t refering to these lines will be ignored and can thus safely be left uninitialized.
- */
-typedef struct {
-    int mosi_io_num;                ///< GPIO pin for Master Out Slave In (=spi_d) signal, or -1 if not used.
-    int miso_io_num;                ///< GPIO pin for Master In Slave Out (=spi_q) signal, or -1 if not used.
-    int sclk_io_num;                ///< GPIO pin for Spi CLocK signal, or -1 if not used.
-    int quadwp_io_num;              ///< GPIO pin for WP (Write Protect) signal which is used as D2 in 4-bit communication modes, or -1 if not used.
-    int quadhd_io_num;              ///< GPIO pin for HD (HolD) signal which is used as D3 in 4-bit communication modes, or -1 if not used.
-    int max_transfer_sz;            ///< Maximum transfer size, in bytes. Defaults to 4094 if 0.
-    uint32_t flags;                 ///< Abilities of bus to be checked by the driver. Or-ed value of ``SPICOMMON_BUSFLAG_*`` flags.
-    int intr_flags;    /**< Interrupt flag for the bus to set the priority, and IRAM attribute, see
-                         *  ``esp_intr_alloc.h``. Note that the EDGE, INTRDISABLED attribute are ignored
-                         *  by the driver. Note that if ESP_INTR_FLAG_IRAM is set, ALL the callbacks of
-                         *  the driver, and their callee functions, should be put in the IRAM.
-                         */
-} spi_bus_config_t;
-
-
-/**
- * @brief Try to claim a SPI peripheral
- *
- * Call this if your driver wants to manage a SPI peripheral.
- *
- * @param host Peripheral to claim
- * @param source The caller indentification string.
- *
- * @return True if peripheral is claimed successfully; false if peripheral already is claimed.
- */
-bool spicommon_periph_claim(spi_host_device_t host, const char* source);
-
-// The macro is to keep the back-compatibility of IDF v3.2 and before
-// In this way we can call spicommon_periph_claim with two arguments, or the host with the source set to the calling function name
-// When two arguments (host, func) are given, __spicommon_periph_claim2 is called
-// or if only one arguments (host) is given, __spicommon_periph_claim1 is called
-#define spicommon_periph_claim(host...) __spicommon_periph_claim(host, 2, 1)
-#define __spicommon_periph_claim(host, source, n, ...) __spicommon_periph_claim ## n(host, source)
-#define __spicommon_periph_claim1(host, _)    ({ \
-    char* warning_str = "calling spicommon_periph_claim without source string is deprecated.";\
-    spicommon_periph_claim(host, __FUNCTION__); })
-
-#define __spicommon_periph_claim2(host, func) spicommon_periph_claim(host, func)
-
-/**
- * @brief Check whether the spi periph is in use.
- *
- * @param host Peripheral to check.
- *
- * @return True if in use, otherwise false.
- */
-bool spicommon_periph_in_use(spi_host_device_t host);
-
-/**
- * @brief Return the SPI peripheral so another driver can claim it.
- *
- * @param host Peripheral to return
- * @return True if peripheral is returned successfully; false if peripheral was free to claim already.
- */
-bool spicommon_periph_free(spi_host_device_t host);
-
-/**
- * @brief Try to claim a SPI DMA channel
- *
- *  Call this if your driver wants to use SPI with a DMA channnel.
- *
- * @param dma_chan channel to claim
- *
- * @return True if success; false otherwise.
- */
-bool spicommon_dma_chan_claim(int dma_chan);
-
-/**
- * @brief Check whether the spi DMA channel is in use.
- *
- * @param dma_chan DMA channel to check.
- *
- * @return True if in use, otherwise false.
- */
-bool spicommon_dma_chan_in_use(int dma_chan);
-
-/**
- * @brief Return the SPI DMA channel so other driver can claim it, or just to power down DMA.
- *
- * @param dma_chan channel to return
- *
- * @return True if success; false otherwise.
- */
-bool spicommon_dma_chan_free(int dma_chan);
-
-#define SPICOMMON_BUSFLAG_SLAVE         0          ///< Initialize I/O in slave mode
-#define SPICOMMON_BUSFLAG_MASTER        (1<<0)     ///< Initialize I/O in master mode
-#define SPICOMMON_BUSFLAG_NATIVE_PINS   (1<<1)     ///< Check using iomux pins. Or indicates the pins are configured through the IO mux rather than GPIO matrix.
-#define SPICOMMON_BUSFLAG_SCLK          (1<<2)     ///< Check existing of SCLK pin. Or indicates CLK line initialized.
-#define SPICOMMON_BUSFLAG_MISO          (1<<3)     ///< Check existing of MISO pin. Or indicates MISO line initialized.
-#define SPICOMMON_BUSFLAG_MOSI          (1<<4)     ///< Check existing of MOSI pin. Or indicates CLK line initialized.
-#define SPICOMMON_BUSFLAG_DUAL          (1<<5)     ///< Check MOSI and MISO pins can output. Or indicates bus able to work under DIO mode.
-#define SPICOMMON_BUSFLAG_WPHD          (1<<6)     ///< Check existing of WP and HD pins. Or indicates WP & HD pins initialized.
-#define SPICOMMON_BUSFLAG_QUAD          (SPICOMMON_BUSFLAG_DUAL|SPICOMMON_BUSFLAG_WPHD)     ///< Check existing of MOSI/MISO/WP/HD pins as output. Or indicates bus able to work under QIO mode.
-
-/**
- * @brief Connect a SPI peripheral to GPIO pins
- *
- * This routine is used to connect a SPI peripheral to the IO-pads and DMA channel given in
- * the arguments. Depending on the IO-pads requested, the routing is done either using the
- * IO_mux or using the GPIO matrix.
- *
- * @param host SPI peripheral to be routed
- * @param bus_config Pointer to a spi_bus_config struct detailing the GPIO pins
- * @param dma_chan DMA-channel (1 or 2) to use, or 0 for no DMA.
- * @param flags Combination of SPICOMMON_BUSFLAG_* flags, set to ensure the pins set are capable with some functions:
- *              - ``SPICOMMON_BUSFLAG_MASTER``: Initialize I/O in master mode
- *              - ``SPICOMMON_BUSFLAG_SLAVE``: Initialize I/O in slave mode
- *              - ``SPICOMMON_BUSFLAG_NATIVE_PINS``: Pins set should match the iomux pins of the controller.
- *              - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``:
- *                  Make sure SCLK/MISO/MOSI is/are set to a valid GPIO. Also check output capability according to the mode.
- *              - ``SPICOMMON_BUSFLAG_DUAL``: Make sure both MISO and MOSI are output capable so that DIO mode is capable.
- *              - ``SPICOMMON_BUSFLAG_WPHD`` Make sure WP and HD are set to valid output GPIOs.
- *              - ``SPICOMMON_BUSFLAG_QUAD``: Combination of ``SPICOMMON_BUSFLAG_DUAL`` and ``SPICOMMON_BUSFLAG_WPHD``.
- * @param[out] flags_o A SPICOMMON_BUSFLAG_* flag combination of bus abilities will be written to this address.
- *              Leave to NULL if not needed.
- *              - ``SPICOMMON_BUSFLAG_NATIVE_PINS``: The bus is connected to iomux pins.
- *              - ``SPICOMMON_BUSFLAG_SCLK``, ``SPICOMMON_BUSFLAG_MISO``, ``SPICOMMON_BUSFLAG_MOSI``: The bus has
- *                  CLK/MISO/MOSI connected.
- *              - ``SPICOMMON_BUSFLAG_DUAL``: The bus is capable with DIO mode.
- *              - ``SPICOMMON_BUSFLAG_WPHD`` The bus has WP and HD connected.
- *              - ``SPICOMMON_BUSFLAG_QUAD``: Combination of ``SPICOMMON_BUSFLAG_DUAL`` and ``SPICOMMON_BUSFLAG_WPHD``.
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_OK                on success
- */
-esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan, uint32_t flags, uint32_t *flags_o);
-
-/**
- * @brief Free the IO used by a SPI peripheral
- * @deprecated Use spicommon_bus_free_io_cfg instead.
- *
- * @param host SPI peripheral to be freed
- *
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_OK                on success
- */
-esp_err_t spicommon_bus_free_io(spi_host_device_t host) __attribute__((deprecated));
-
-/**
- * @brief Free the IO used by a SPI peripheral
- *
- * @param bus_cfg Bus config struct which defines which pins to be used.
- *
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_OK                on success
- */
-esp_err_t spicommon_bus_free_io_cfg(const spi_bus_config_t *bus_cfg);
-
-/**
- * @brief Initialize a Chip Select pin for a specific SPI peripheral
- *
- *
- * @param host SPI peripheral
- * @param cs_io_num GPIO pin to route
- * @param cs_num CS id to route
- * @param force_gpio_matrix If true, CS will always be routed through the GPIO matrix. If false,
- *                          if the GPIO number allows it, the routing will happen through the IO_mux.
- */
-
-void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, int force_gpio_matrix);
-
-/**
- * @brief Free a chip select line
- * @deprecated Use spicommon_cs_io, which inputs the gpio num rather than the cs id instead.
- *
- * @param host SPI peripheral
- * @param cs_num CS id to free
- */
-void spicommon_cs_free(spi_host_device_t host, int cs_num) __attribute__((deprecated));
-
-/**
- * @brief Free a chip select line
- *
- * @param cs_gpio_num CS gpio num to free
- */
-void spicommon_cs_free_io(int cs_gpio_num);
-
-/**
- * @brief Setup a DMA link chain
- *
- * This routine will set up a chain of linked DMA descriptors in the array pointed to by
- * ``dmadesc``. Enough DMA descriptors will be used to fit the buffer of ``len`` bytes in, and the
- * descriptors will point to the corresponding positions in ``buffer`` and linked together. The
- * end result is that feeding ``dmadesc[0]`` into DMA hardware results in the entirety ``len`` bytes
- * of ``data`` being read or written.
- *
- * @param dmadesc Pointer to array of DMA descriptors big enough to be able to convey ``len`` bytes
- * @param len Length of buffer
- * @param data Data buffer to use for DMA transfer
- * @param isrx True if data is to be written into ``data``, false if it's to be read from ``data``.
- */
-void spicommon_setup_dma_desc_links(lldesc_t *dmadesc, int len, const uint8_t *data, bool isrx);
-
-/**
- * @brief Get the position of the hardware registers for a specific SPI host
- *
- * @param host The SPI host
- *
- * @return A register descriptor stuct pointer, pointed at the hardware registers
- */
-spi_dev_t *spicommon_hw_for_host(spi_host_device_t host);
-
-/**
- * @brief Get the IRQ source for a specific SPI host
- *
- * @param host The SPI host
- *
- * @return The hosts IRQ source
- */
-int spicommon_irqsource_for_host(spi_host_device_t host);
-
-/**
- * Callback, to be called when a DMA engine reset is completed
-*/
-typedef void(*dmaworkaround_cb_t)(void *arg);
-
-
-/**
- * @brief Request a reset for a certain DMA channel
- *
- * @note In some (well-defined) cases in the ESP32 (at least rev v.0 and v.1), a SPI DMA channel will get confused. This can be remedied
- * by resetting the SPI DMA hardware in case this happens. Unfortunately, the reset knob used for thsi will reset _both_ DMA channels, and
- * as such can only done safely when both DMA channels are idle. These functions coordinate this.
- *
- * Essentially, when a reset is needed, a driver can request this using spicommon_dmaworkaround_req_reset. This is supposed to be called
- * with an user-supplied function as an argument. If both DMA channels are idle, this call will reset the DMA subsystem and return true.
- * If the other DMA channel is still busy, it will return false; as soon as the other DMA channel is done, however, it will reset the
- * DMA subsystem and call the callback. The callback is then supposed to be used to continue the SPI drivers activity.
- *
- * @param dmachan DMA channel associated with the SPI host that needs a reset
- * @param cb Callback to call in case DMA channel cannot be reset immediately
- * @param arg Argument to the callback
- *
- * @return True when a DMA reset could be executed immediately. False when it could not; in this
- *         case the callback will be called with the specified argument when the logic can execute
- *         a reset, after that reset.
- */
-bool spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t cb, void *arg);
-
-
-/**
- * @brief Check if a DMA reset is requested but has not completed yet
- *
- * @return True when a DMA reset is requested but hasn't completed yet. False otherwise.
- */
-bool spicommon_dmaworkaround_reset_in_progress();
-
-
-/**
- * @brief Mark a DMA channel as idle.
- *
- * A call to this function tells the workaround logic that this channel will
- * not be affected by a global SPI DMA reset.
- */
-void spicommon_dmaworkaround_idle(int dmachan);
-
-/**
- * @brief Mark a DMA channel as active.
- *
- * A call to this function tells the workaround logic that this channel will
- * be affected by a global SPI DMA reset, and a reset like that should not be attempted.
- */
-void spicommon_dmaworkaround_transfer_active(int dmachan);
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/driver/driver/spi_master.h b/tools/sdk/include/driver/driver/spi_master.h
deleted file mode 100644
index b2acee0d0ec..00000000000
--- a/tools/sdk/include/driver/driver/spi_master.h
+++ /dev/null
@@ -1,416 +0,0 @@
-// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef _DRIVER_SPI_MASTER_H_
-#define _DRIVER_SPI_MASTER_H_
-
-#include "esp_err.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-
-#include "driver/spi_common.h"
-
-/** SPI master clock is divided by 80MHz apb clock. Below defines are example frequencies, and are accurate. Be free to specify a random frequency, it will be rounded to closest frequency (to macros below if above 8MHz).
-  * 8MHz
-  */
-#define SPI_MASTER_FREQ_8M      (APB_CLK_FREQ/10)
-#define SPI_MASTER_FREQ_9M      (APB_CLK_FREQ/9)    ///< 8.89MHz
-#define SPI_MASTER_FREQ_10M     (APB_CLK_FREQ/8)    ///< 10MHz
-#define SPI_MASTER_FREQ_11M     (APB_CLK_FREQ/7)    ///< 11.43MHz
-#define SPI_MASTER_FREQ_13M     (APB_CLK_FREQ/6)    ///< 13.33MHz
-#define SPI_MASTER_FREQ_16M     (APB_CLK_FREQ/5)    ///< 16MHz
-#define SPI_MASTER_FREQ_20M     (APB_CLK_FREQ/4)    ///< 20MHz
-#define SPI_MASTER_FREQ_26M     (APB_CLK_FREQ/3)    ///< 26.67MHz
-#define SPI_MASTER_FREQ_40M     (APB_CLK_FREQ/2)    ///< 40MHz
-#define SPI_MASTER_FREQ_80M     (APB_CLK_FREQ/1)    ///< 80MHz
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#define SPI_DEVICE_TXBIT_LSBFIRST          (1<<0)  ///< Transmit command/address/data LSB first instead of the default MSB first
-#define SPI_DEVICE_RXBIT_LSBFIRST          (1<<1)  ///< Receive data LSB first instead of the default MSB first
-#define SPI_DEVICE_BIT_LSBFIRST            (SPI_DEVICE_TXBIT_LSBFIRST|SPI_DEVICE_RXBIT_LSBFIRST) ///< Transmit and receive LSB first
-#define SPI_DEVICE_3WIRE                   (1<<2)  ///< Use MOSI (=spid) for both sending and receiving data
-#define SPI_DEVICE_POSITIVE_CS             (1<<3)  ///< Make CS positive during a transaction instead of negative
-#define SPI_DEVICE_HALFDUPLEX              (1<<4)  ///< Transmit data before receiving it, instead of simultaneously
-#define SPI_DEVICE_CLK_AS_CS               (1<<5)  ///< Output clock on CS line if CS is active
-/** There are timing issue when reading at high frequency (the frequency is related to whether iomux pins are used, valid time after slave sees the clock).
-  *     - In half-duplex mode, the driver automatically inserts dummy bits before reading phase to fix the timing issue. Set this flag to disable this feature.
-  *     - In full-duplex mode, however, the hardware cannot use dummy bits, so there is no way to prevent data being read from getting corrupted.
-  *       Set this flag to confirm that you're going to work with output only, or read without dummy bits at your own risk.
-  */
-#define SPI_DEVICE_NO_DUMMY                (1<<6)
-
-
-typedef struct spi_transaction_t spi_transaction_t;
-typedef void(*transaction_cb_t)(spi_transaction_t *trans);
-
-/**
- * @brief This is a configuration for a SPI slave device that is connected to one of the SPI buses.
- */
-typedef struct {
-    uint8_t command_bits;           ///< Default amount of bits in command phase (0-16), used when ``SPI_TRANS_VARIABLE_CMD`` is not used, otherwise ignored.
-    uint8_t address_bits;           ///< Default amount of bits in address phase (0-64), used when ``SPI_TRANS_VARIABLE_ADDR`` is not used, otherwise ignored.
-    uint8_t dummy_bits;             ///< Amount of dummy bits to insert between address and data phase
-    uint8_t mode;                   ///< SPI mode (0-3)
-    uint8_t duty_cycle_pos;         ///< Duty cycle of positive clock, in 1/256th increments (128 = 50%/50% duty). Setting this to 0 (=not setting it) is equivalent to setting this to 128.
-    uint8_t cs_ena_pretrans;        ///< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions.
-    uint8_t cs_ena_posttrans;       ///< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16)
-    int clock_speed_hz;             ///< Clock speed, divisors of 80MHz, in Hz. See ``SPI_MASTER_FREQ_*``.
-    int input_delay_ns;             /**< Maximum data valid time of slave. The time required between SCLK and MISO
-        valid, including the possible clock delay from slave to master. The driver uses this value to give an extra
-        delay before the MISO is ready on the line. Leave at 0 unless you know you need a delay. For better timing
-        performance at high frequency (over 8MHz), it's suggest to have the right value.
-        */
-    int spics_io_num;               ///< CS GPIO pin for this device, or -1 if not used
-    uint32_t flags;                 ///< Bitwise OR of SPI_DEVICE_* flags
-    int queue_size;                 ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_device_queue_trans but not yet finished using spi_device_get_trans_result) at the same time
-    transaction_cb_t pre_cb;   /**< Callback to be called before a transmission is started.
-                                 *
-                                 *  This callback is called within interrupt
-                                 *  context should be in IRAM for best
-                                 *  performance, see "Transferring Speed"
-                                 *  section in the SPI Master documentation for
-                                 *  full details. If not, the callback may crash
-                                 *  during flash operation when the driver is
-                                 *  initialized with ESP_INTR_FLAG_IRAM.
-                                 */
-    transaction_cb_t post_cb;  /**< Callback to be called after a transmission has completed.
-                                 *
-                                 *  This callback is called within interrupt
-                                 *  context should be in IRAM for best
-                                 *  performance, see "Transferring Speed"
-                                 *  section in the SPI Master documentation for
-                                 *  full details. If not, the callback may crash
-                                 *  during flash operation when the driver is
-                                 *  initialized with ESP_INTR_FLAG_IRAM.
-                                 */
-} spi_device_interface_config_t;
-
-
-#define SPI_TRANS_MODE_DIO            (1<<0)  ///< Transmit/receive data in 2-bit mode
-#define SPI_TRANS_MODE_QIO            (1<<1)  ///< Transmit/receive data in 4-bit mode
-#define SPI_TRANS_USE_RXDATA          (1<<2)  ///< Receive into rx_data member of spi_transaction_t instead into memory at rx_buffer.
-#define SPI_TRANS_USE_TXDATA          (1<<3)  ///< Transmit tx_data member of spi_transaction_t instead of data at tx_buffer. Do not set tx_buffer when using this.
-#define SPI_TRANS_MODE_DIOQIO_ADDR    (1<<4)  ///< Also transmit address in mode selected by SPI_MODE_DIO/SPI_MODE_QIO
-#define SPI_TRANS_VARIABLE_CMD        (1<<5)  ///< Use the ``command_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
-#define SPI_TRANS_VARIABLE_ADDR       (1<<6)  ///< Use the ``address_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
-
-/**
- * This structure describes one SPI transaction. The descriptor should not be modified until the transaction finishes.
- */
-struct spi_transaction_t {
-    uint32_t flags;                 ///< Bitwise OR of SPI_TRANS_* flags
-    uint16_t cmd;                   /**< Command data, of which the length is set in the ``command_bits`` of spi_device_interface_config_t.
-                                      *
-                                      *  <b>NOTE: this field, used to be "command" in ESP-IDF 2.1 and before, is re-written to be used in a new way in ESP-IDF 3.0.</b>
-                                      *
-                                      *  Example: write 0x0123 and command_bits=12 to send command 0x12, 0x3_ (in previous version, you may have to write 0x3_12).
-                                      */
-    uint64_t addr;                  /**< Address data, of which the length is set in the ``address_bits`` of spi_device_interface_config_t.
-                                      *
-                                      *  <b>NOTE: this field, used to be "address" in ESP-IDF 2.1 and before, is re-written to be used in a new way in ESP-IDF3.0.</b>
-                                      *
-                                      *  Example: write 0x123400 and address_bits=24 to send address of 0x12, 0x34, 0x00 (in previous version, you may have to write 0x12340000).
-                                      */
-    size_t length;                  ///< Total data length, in bits
-    size_t rxlength;                ///< Total data length received, should be not greater than ``length`` in full-duplex mode (0 defaults this to the value of ``length``).
-    void *user;                     ///< User-defined variable. Can be used to store eg transaction ID.
-    union {
-        const void *tx_buffer;      ///< Pointer to transmit buffer, or NULL for no MOSI phase
-        uint8_t tx_data[4];         ///< If SPI_USE_TXDATA is set, data set here is sent directly from this variable.
-    };
-    union {
-        void *rx_buffer;            ///< Pointer to receive buffer, or NULL for no MISO phase. Written by 4 bytes-unit if DMA is used.
-        uint8_t rx_data[4];         ///< If SPI_USE_RXDATA is set, data is received directly to this variable
-    };
-} ;        //the rx data should start from a 32-bit aligned address to get around dma issue.
-
-/**
- * This struct is for SPI transactions which may change their address and command length.
- * Please do set the flags in base to ``SPI_TRANS_VARIABLE_CMD_ADR`` to use the bit length here.
- */
-typedef struct {
-    struct spi_transaction_t base;  ///< Transaction data, so that pointer to spi_transaction_t can be converted into spi_transaction_ext_t
-    uint8_t command_bits;           ///< The command length in this transaction, in bits.
-    uint8_t address_bits;           ///< The address length in this transaction, in bits.
-} spi_transaction_ext_t ;
-
-
-typedef struct spi_device_t* spi_device_handle_t;  ///< Handle for a device on a SPI bus
-
-/**
- * @brief Initialize a SPI bus
- *
- * @warning For now, only supports HSPI and VSPI.
- *
- * @param host SPI peripheral that controls this bus
- * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized
- * @param dma_chan Either channel 1 or 2, or 0 in the case when no DMA is required. Selecting a DMA channel
- *                 for a SPI bus allows transfers on the bus to have sizes only limited by the amount of
- *                 internal memory. Selecting no DMA channel (by passing the value 0) limits the amount of
- *                 bytes transfered to a maximum of 32.
- *
- * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in
- *          DMA-capable memory.
- *
- * @warning The ISR of SPI is always executed on the core which calls this
- *          function. Never starve the ISR on this core or the SPI transactions will not
- *          be handled.
- *
- * @return
- *         - ESP_ERR_INVALID_ARG   if configuration is invalid
- *         - ESP_ERR_INVALID_STATE if host already is in use
- *         - ESP_ERR_NO_MEM        if out of memory
- *         - ESP_OK                on success
- */
-esp_err_t spi_bus_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan);
-
-/**
- * @brief Free a SPI bus
- *
- * @warning In order for this to succeed, all devices have to be removed first.
- *
- * @param host SPI peripheral to free
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_ERR_INVALID_STATE if not all devices on the bus are freed
- *         - ESP_OK                on success
- */
-esp_err_t spi_bus_free(spi_host_device_t host);
-
-/**
- * @brief Allocate a device on a SPI bus
- *
- * This initializes the internal structures for a device, plus allocates a CS pin on the indicated SPI master
- * peripheral and routes it to the indicated GPIO. All SPI master devices have three CS pins and can thus control
- * up to three devices.
- *
- * @note While in general, speeds up to 80MHz on the dedicated SPI pins and 40MHz on GPIO-matrix-routed pins are
- *       supported, full-duplex transfers routed over the GPIO matrix only support speeds up to 26MHz.
- *
- * @param host SPI peripheral to allocate device on
- * @param dev_config SPI interface protocol config for the device
- * @param handle Pointer to variable to hold the device handle
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_ERR_NOT_FOUND     if host doesn't have any free CS slots
- *         - ESP_ERR_NO_MEM        if out of memory
- *         - ESP_OK                on success
- */
-esp_err_t spi_bus_add_device(spi_host_device_t host, const spi_device_interface_config_t *dev_config, spi_device_handle_t *handle);
-
-
-/**
- * @brief Remove a device from the SPI bus
- *
- * @param handle Device handle to free
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_ERR_INVALID_STATE if device already is freed
- *         - ESP_OK                on success
- */
-esp_err_t spi_bus_remove_device(spi_device_handle_t handle);
-
-
-/**
- * @brief Queue a SPI transaction for interrupt transaction execution. Get the result by ``spi_device_get_trans_result``.
- *
- * @note Normally a device cannot start (queue) polling and interrupt
- *      transactions simultaneously.
- *
- * @param handle Device handle obtained using spi_host_add_dev
- * @param trans_desc Description of transaction to execute
- * @param ticks_to_wait Ticks to wait until there's room in the queue; use portMAX_DELAY to
- *                      never time out.
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_ERR_TIMEOUT       if there was no room in the queue before ticks_to_wait expired
- *         - ESP_ERR_NO_MEM        if allocating DMA-capable temporary buffer failed
- *         - ESP_ERR_INVALID_STATE if previous transactions are not finished
- *         - ESP_OK                on success
- */
-esp_err_t spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait);
-
-
-/**
- * @brief Get the result of a SPI transaction queued earlier by ``spi_device_queue_trans``.
- *
- * This routine will wait until a transaction to the given device
- * succesfully completed. It will then return the description of the
- * completed transaction so software can inspect the result and e.g. free the memory or
- * re-use the buffers.
- *
- * @param handle Device handle obtained using spi_host_add_dev
- * @param trans_desc Pointer to variable able to contain a pointer to the description of the transaction
-        that is executed. The descriptor should not be modified until the descriptor is returned by
-        spi_device_get_trans_result.
- * @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time
-                        out.
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_ERR_TIMEOUT       if there was no completed transaction before ticks_to_wait expired
- *         - ESP_OK                on success
- */
-esp_err_t spi_device_get_trans_result(spi_device_handle_t handle, spi_transaction_t **trans_desc, TickType_t ticks_to_wait);
-
-
-/**
- * @brief Send a SPI transaction, wait for it to complete, and return the result
- *
- * This function is the equivalent of calling spi_device_queue_trans() followed by spi_device_get_trans_result().
- * Do not use this when there is still a transaction separately queued (started) from spi_device_queue_trans() or polling_start/transmit that hasn't been finalized.
- *
- * @note This function is not thread safe when multiple tasks access the same SPI device.
- *      Normally a device cannot start (queue) polling and interrupt
- *      transactions simutanuously.
- *
- * @param handle Device handle obtained using spi_host_add_dev
- * @param trans_desc Description of transaction to execute
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_OK                on success
- */
-esp_err_t spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc);
-
-
-/**
- * @brief Immediately start a polling transaction.
- *
- * @note Normally a device cannot start (queue) polling and interrupt
- *      transactions simutanuously. Moreover, a device cannot start a new polling
- *      transaction if another polling transaction is not finished.
- *
- * @param handle Device handle obtained using spi_host_add_dev
- * @param trans_desc Description of transaction to execute
- * @param ticks_to_wait Ticks to wait until there's room in the queue;
- *              currently only portMAX_DELAY is supported.
- *
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_ERR_TIMEOUT       if the device cannot get control of the bus before ``ticks_to_wait`` expired
- *         - ESP_ERR_NO_MEM        if allocating DMA-capable temporary buffer failed
- *         - ESP_ERR_INVALID_STATE if previous transactions are not finished
- *         - ESP_OK                on success
- */
-esp_err_t spi_device_polling_start(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait);
-
-
-/**
- * @brief Poll until the polling transaction ends.
- *
- * This routine will not return until the transaction to the given device has
- * succesfully completed. The task is not blocked, but actively busy-spins for
- * the transaction to be completed.
- *
- * @param handle Device handle obtained using spi_host_add_dev
- * @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time
-                        out.
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_ERR_TIMEOUT       if the transaction cannot finish before ticks_to_wait expired
- *         - ESP_OK                on success
- */
-esp_err_t spi_device_polling_end(spi_device_handle_t handle, TickType_t ticks_to_wait);
-
-
-/**
- * @brief Send a polling transaction, wait for it to complete, and return the result
- *
- * This function is the equivalent of calling spi_device_polling_start() followed by spi_device_polling_end().
- * Do not use this when there is still a transaction that hasn't been finalized.
- *
- * @note This function is not thread safe when multiple tasks access the same SPI device.
- *      Normally a device cannot start (queue) polling and interrupt
- *      transactions simutanuously.
- *
- * @param handle Device handle obtained using spi_host_add_dev
- * @param trans_desc Description of transaction to execute
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_OK                on success
- */
-esp_err_t spi_device_polling_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc);
-
-
-/**
- * @brief Occupy the SPI bus for a device to do continuous transactions.
- *
- * Transactions to all other devices will be put off until ``spi_device_release_bus`` is called.
- *
- * @note The function will wait until all the existing transactions have been sent.
- *
- * @param device The device to occupy the bus.
- * @param wait Time to wait before the the bus is occupied by the device. Currently MUST set to portMAX_DELAY.
- *
- * @return
- *      - ESP_ERR_INVALID_ARG : ``wait`` is not set to portMAX_DELAY.
- *      - ESP_OK : Success.
- */
-esp_err_t spi_device_acquire_bus(spi_device_handle_t device, TickType_t wait);
-
-/**
- * @brief Release the SPI bus occupied by the device. All other devices can start sending transactions.
- *
- * @param dev The device to release the bus.
- */
-void spi_device_release_bus(spi_device_handle_t dev);
-
-
-/**
- * @brief Calculate the working frequency that is most close to desired frequency, and also the register value.
- *
- * @param fapb The frequency of apb clock, should be ``APB_CLK_FREQ``.
- * @param hz Desired working frequency
- * @param duty_cycle Duty cycle of the spi clock
- * @param reg_o Output of value to be set in clock register, or NULL if not needed.
- * @return Actual working frequency that most fit.
- */
-int spi_cal_clock(int fapb, int hz, int duty_cycle, uint32_t* reg_o);
-
-/**
-  * @brief Calculate the timing settings of specified frequency and settings.
-  *
-  * @param gpio_is_used True if using GPIO matrix, or False if iomux pins are used.
-  * @param input_delay_ns Input delay from SCLK launch edge to MISO data valid.
-  * @param eff_clk Effective clock frequency (in Hz) from spi_cal_clock.
-  * @param dummy_o Address of dummy bits used output. Set to NULL if not needed.
-  * @param cycles_remain_o Address of cycles remaining (after dummy bits are used) output.
-  *         - -1 If too many cycles remaining, suggest to compensate half a clock.
-  *         - 0 If no remaining cycles or dummy bits are not used.
-  *         - positive value: cycles suggest to compensate.
-  *
-  * @note If **dummy_o* is not zero, it means dummy bits should be applied in half duplex mode, and full duplex mode may not work.
-  */
-void spi_get_timing(bool gpio_is_used, int input_delay_ns, int eff_clk, int* dummy_o, int* cycles_remain_o);
-
-/**
-  * @brief Get the frequency limit of current configurations.
-  *         SPI master working at this limit is OK, while above the limit, full duplex mode and DMA will not work,
-  *         and dummy bits will be aplied in the half duplex mode.
-  *
-  * @param gpio_is_used True if using GPIO matrix, or False if native pins are used.
-  * @param input_delay_ns Input delay from SCLK launch edge to MISO data valid.
-  * @return Frequency limit of current configurations.
-  */
-int spi_get_freq_limit(bool gpio_is_used, int input_delay_ns);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/driver/driver/spi_slave.h b/tools/sdk/include/driver/driver/spi_slave.h
deleted file mode 100644
index 522c9fb8ab0..00000000000
--- a/tools/sdk/include/driver/driver/spi_slave.h
+++ /dev/null
@@ -1,191 +0,0 @@
-// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef _DRIVER_SPI_SLAVE_H_
-#define _DRIVER_SPI_SLAVE_H_
-
-#include "esp_err.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-#include "driver/spi_common.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-#define SPI_SLAVE_TXBIT_LSBFIRST          (1<<0)  ///< Transmit command/address/data LSB first instead of the default MSB first
-#define SPI_SLAVE_RXBIT_LSBFIRST          (1<<1)  ///< Receive data LSB first instead of the default MSB first
-#define SPI_SLAVE_BIT_LSBFIRST            (SPI_SLAVE_TXBIT_LSBFIRST|SPI_SLAVE_RXBIT_LSBFIRST) ///< Transmit and receive LSB first
-
-
-typedef struct spi_slave_transaction_t spi_slave_transaction_t;
-typedef void(*slave_transaction_cb_t)(spi_slave_transaction_t *trans);
-
-/**
- * @brief This is a configuration for a SPI host acting as a slave device.
- */
-typedef struct {
-    int spics_io_num;               ///< CS GPIO pin for this device
-    uint32_t flags;                 ///< Bitwise OR of SPI_SLAVE_* flags
-    int queue_size;                 ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_slave_queue_trans but not yet finished using spi_slave_get_trans_result) at the same time
-    uint8_t mode;                   ///< SPI mode (0-3)
-    slave_transaction_cb_t post_setup_cb;  /**< Callback called after the SPI registers are loaded with new data.
-                                             *
-                                             *  This callback is called within interrupt
-                                             *  context should be in IRAM for best
-                                             *  performance, see "Transferring Speed"
-                                             *  section in the SPI Master documentation for
-                                             *  full details. If not, the callback may crash
-                                             *  during flash operation when the driver is
-                                             *  initialized with ESP_INTR_FLAG_IRAM.
-                                             */
-    slave_transaction_cb_t post_trans_cb;  /**< Callback called after a transaction is done.
-                                             *
-                                             *  This callback is called within interrupt
-                                             *  context should be in IRAM for best
-                                             *  performance, see "Transferring Speed"
-                                             *  section in the SPI Master documentation for
-                                             *  full details. If not, the callback may crash
-                                             *  during flash operation when the driver is
-                                             *  initialized with ESP_INTR_FLAG_IRAM.
-                                             */
-} spi_slave_interface_config_t;
-
-/**
- * This structure describes one SPI transaction
- */
-struct spi_slave_transaction_t {
-    size_t length;                  ///< Total data length, in bits
-    size_t trans_len;               ///< Transaction data length, in bits
-    const void *tx_buffer;          ///< Pointer to transmit buffer, or NULL for no MOSI phase
-    void *rx_buffer;                /**< Pointer to receive buffer, or NULL for no MISO phase.
-                                     * When the DMA is anabled, must start at WORD boundary (``rx_buffer%4==0``),
-                                     * and has length of a multiple of 4 bytes.
-                                     */
-    void *user;                     ///< User-defined variable. Can be used to store eg transaction ID.
-};
-
-/**
- * @brief Initialize a SPI bus as a slave interface
- *
- * @warning For now, only supports HSPI and VSPI.
- *
- * @param host SPI peripheral to use as a SPI slave interface
- * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized
- * @param slave_config Pointer to a spi_slave_interface_config_t struct specifying the details for the slave interface
- * @param dma_chan Either 1 or 2. A SPI bus used by this driver must have a DMA channel associated with
- *                 it. The SPI hardware has two DMA channels to share. This parameter indicates which
- *                 one to use.
- *
- * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in
- *          DMA-capable memory.
- *
- * @warning The ISR of SPI is always executed on the core which calls this
- *          function. Never starve the ISR on this core or the SPI transactions will not
- *          be handled.
- *
- * @return
- *         - ESP_ERR_INVALID_ARG   if configuration is invalid
- *         - ESP_ERR_INVALID_STATE if host already is in use
- *         - ESP_ERR_NO_MEM        if out of memory
- *         - ESP_OK                on success
- */
-esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, int dma_chan);
-
-/**
- * @brief Free a SPI bus claimed as a SPI slave interface
- *
- * @param host SPI peripheral to free
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_ERR_INVALID_STATE if not all devices on the bus are freed
- *         - ESP_OK                on success
- */
-esp_err_t spi_slave_free(spi_host_device_t host);
-
-
-/**
- * @brief Queue a SPI transaction for execution
- *
- * Queues a SPI transaction to be executed by this slave device. (The transaction queue size was specified when the slave
- * device was initialised via spi_slave_initialize.) This function may block if the queue is full (depending on the
- * ticks_to_wait parameter). No SPI operation is directly initiated by this function, the next queued transaction
- * will happen when the master initiates a SPI transaction by pulling down CS and sending out clock signals.
- *
- * This function hands over ownership of the buffers in ``trans_desc`` to the SPI slave driver; the application is
- * not to access this memory until ``spi_slave_queue_trans`` is called to hand ownership back to the application.
- *
- * @param host SPI peripheral that is acting as a slave
- * @param trans_desc Description of transaction to execute. Not const because we may want to write status back
- *                   into the transaction description.
- * @param ticks_to_wait Ticks to wait until there's room in the queue; use portMAX_DELAY to
- *                      never time out.
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_OK                on success
- */
-esp_err_t spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait);
-
-
-/**
- * @brief Get the result of a SPI transaction queued earlier
- *
- * This routine will wait until a transaction to the given device (queued earlier with
- * spi_slave_queue_trans) has succesfully completed. It will then return the description of the
- * completed transaction so software can inspect the result and e.g. free the memory or
- * re-use the buffers.
- *
- * It is mandatory to eventually use this function for any transaction queued by ``spi_slave_queue_trans``.
- *
- * @param host SPI peripheral to that is acting as a slave
- * @param[out] trans_desc Pointer to variable able to contain a pointer to the description of the
- *                   transaction that is executed
- * @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time
- *                      out.
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_OK                on success
- */
-esp_err_t spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transaction_t **trans_desc, TickType_t ticks_to_wait);
-
-
-/**
- * @brief Do a SPI transaction
- *
- * Essentially does the same as spi_slave_queue_trans followed by spi_slave_get_trans_result. Do
- * not use this when there is still a transaction queued that hasn't been finalized
- * using spi_slave_get_trans_result.
- *
- * @param host SPI peripheral to that is acting as a slave
- * @param trans_desc Pointer to variable able to contain a pointer to the description of the
- *                   transaction that is executed. Not const because we may want to write status back
- *                   into the transaction description.
- * @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time
- *                      out.
- * @return
- *         - ESP_ERR_INVALID_ARG   if parameter is invalid
- *         - ESP_OK                on success
- */
-esp_err_t spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/driver/driver/timer.h b/tools/sdk/include/driver/driver/timer.h
deleted file mode 100644
index 48e2b98908d..00000000000
--- a/tools/sdk/include/driver/driver/timer.h
+++ /dev/null
@@ -1,353 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_TIMER_H_
-#define _DRIVER_TIMER_H_
-#include "esp_err.h"
-#include "esp_attr.h"
-#include "soc/soc.h"
-#include "soc/timer_group_reg.h"
-#include "soc/timer_group_struct.h"
-#include "esp_intr_alloc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#define TIMER_BASE_CLK   (APB_CLK_FREQ)  /*!< Frequency of the clock on the input of the timer groups */
-
-/**
- * @brief Selects a Timer-Group out of 2 available groups
- */
-typedef enum {
-    TIMER_GROUP_0 = 0, /*!<Hw timer group 0*/
-    TIMER_GROUP_1 = 1, /*!<Hw timer group 1*/
-    TIMER_GROUP_MAX,
-} timer_group_t;
-
-/**
- * @brief Select a hardware timer from timer groups
- */
-typedef enum {
-    TIMER_0 = 0, /*!<Select timer0 of GROUPx*/
-    TIMER_1 = 1, /*!<Select timer1 of GROUPx*/
-    TIMER_MAX,
-} timer_idx_t;
-
-/**
- * @brief Decides the direction of counter
- */
-typedef enum {
-    TIMER_COUNT_DOWN = 0, /*!< Descending Count from cnt.high|cnt.low*/
-    TIMER_COUNT_UP = 1,   /*!< Ascending Count from Zero*/
-    TIMER_COUNT_MAX
-} timer_count_dir_t;
-
-/**
- * @brief Decides whether timer is on or paused
- */
-typedef enum {
-    TIMER_PAUSE = 0, /*!<Pause timer counter*/
-    TIMER_START = 1, /*!<Start timer counter*/
-} timer_start_t;
-
-/**
- * @brief Decides whether to enable alarm mode
- */
-typedef enum {
-    TIMER_ALARM_DIS = 0,  /*!< Disable timer alarm*/
-    TIMER_ALARM_EN = 1,   /*!< Enable timer alarm*/
-    TIMER_ALARM_MAX
-} timer_alarm_t;
-
-/**
- * @brief Select interrupt type if running in alarm mode.
- */
-typedef enum {
-    TIMER_INTR_LEVEL = 0,  /*!< Interrupt mode: level mode*/
-    //TIMER_INTR_EDGE = 1, /*!< Interrupt mode: edge mode, Not supported Now*/
-    TIMER_INTR_MAX
-} timer_intr_mode_t;
-
-/**
- * @brief Select if Alarm needs to be loaded by software or automatically reload by hardware.
- */
-typedef enum {
-    TIMER_AUTORELOAD_DIS = 0,  /*!< Disable auto-reload: hardware will not load counter value after an alarm event*/
-    TIMER_AUTORELOAD_EN = 1,   /*!< Enable auto-reload: hardware will load counter value after an alarm event*/
-    TIMER_AUTORELOAD_MAX,
-} timer_autoreload_t;
-
-/**
- * @brief Data structure with timer's configuration settings
- */
-typedef struct {
-    bool alarm_en;      /*!< Timer alarm enable */
-    bool counter_en;    /*!< Counter enable */
-    timer_intr_mode_t intr_type; /*!< Interrupt mode */
-    timer_count_dir_t counter_dir; /*!< Counter direction  */
-    bool auto_reload;   /*!< Timer auto-reload */
-    uint32_t divider;   /*!< Counter clock divider. The divider's range is from from 2 to 65536. */
-} timer_config_t;
-
-
-/**
- * @brief Interrupt handle, used in order to free the isr after use.
- * Aliases to an int handle for now.
- */
-typedef intr_handle_t timer_isr_handle_t;
-
-/**
- * @brief Read the counter value of hardware timer.
- *
- * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param timer_val Pointer to accept timer counter value.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t* timer_val);
-
-/**
- * @brief Read the counter value of hardware timer, in unit of a given scale.
- *
- * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param time Pointer, type of double*, to accept timer counter value, in seconds.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_num, double* time);
-
-/**
- * @brief Set counter value to hardware timer.
- *
- * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param load_val Counter value to write to the hardware timer.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_set_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t load_val);
-
-/**
- * @brief Start the counter of hardware timer.
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_start(timer_group_t group_num, timer_idx_t timer_num);
-
-/**
- * @brief Pause the counter of hardware timer.
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_pause(timer_group_t group_num, timer_idx_t timer_num);
-
-/**
- * @brief Set counting mode for hardware timer.
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param counter_dir Counting direction of timer, count-up or count-down
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_set_counter_mode(timer_group_t group_num, timer_idx_t timer_num, timer_count_dir_t counter_dir);
-
-/**
- * @brief Enable or disable counter reload function when alarm event occurs.
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param reload Counter reload mode.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_set_auto_reload(timer_group_t group_num, timer_idx_t timer_num, timer_autoreload_t reload);
-
-/**
- * @brief Set hardware timer source clock divider. Timer groups clock are divider from APB clock.
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param divider Timer clock divider value. The divider's range is from from 2 to 65536.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_set_divider(timer_group_t group_num, timer_idx_t timer_num, uint32_t divider);
-
-/**
- * @brief Set timer alarm value.
- *
- * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param alarm_value A 64-bit value to set the alarm value.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_set_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_value);
-
-/**
- * @brief Get timer alarm value.
- *
- * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param alarm_value Pointer of A 64-bit value to accept the alarm value.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_get_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t* alarm_value);
-
-/**
- * @brief Enable or disable generation of timer alarm events.
- *
- * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param alarm_en To enable or disable timer alarm function.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_alarm_t alarm_en);
-
-/**
- * @brief Register Timer interrupt handler, the handler is an ISR.
- *        The handler will be attached to the same CPU core that this function is running on.
- *
- * @param group_num Timer group number
- * @param timer_num Timer index of timer group
- * @param fn Interrupt handler function.
- * @param arg Parameter for handler function
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
- * @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will
- *        be returned here.
- *
- * @note If the intr_alloc_flags value ESP_INTR_FLAG_IRAM is set, 
- *       the handler function must be declared with IRAM_ATTR attribute 
- *       and can only call functions in IRAM or ROM. It cannot call other timer APIs. 
- *       Use direct register access to configure timers from inside the ISR in this case.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num, void (*fn)(void*), void * arg, int intr_alloc_flags, timer_isr_handle_t *handle);
-
-/** @brief Initializes and configure the timer.
- * 
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param config Pointer to timer initialization parameters.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer_config_t* config);
-
-/** @brief Get timer configure value.
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
- * @param config Pointer of struct to accept timer parameters.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_get_config(timer_group_t group_num, timer_idx_t timer_num, timer_config_t *config);
-
-/** @brief Enable timer group interrupt, by enable mask
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param en_mask Timer interrupt enable mask.
- *        Use TIMG_T0_INT_ENA_M to enable t0 interrupt
- *        Use TIMG_T1_INT_ENA_M to enable t1 interrupt
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_group_intr_enable(timer_group_t group_num, uint32_t en_mask);
-
-/** @brief Disable timer group interrupt, by disable mask
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param disable_mask Timer interrupt disable mask.
- *        Use TIMG_T0_INT_ENA_M to disable t0 interrupt
- *        Use TIMG_T1_INT_ENA_M to disable t1 interrupt
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_group_intr_disable(timer_group_t group_num, uint32_t disable_mask);
-
-/** @brief Enable timer interrupt
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_enable_intr(timer_group_t group_num, timer_idx_t timer_num);
-
-/** @brief Disable timer interrupt
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param timer_num Timer index.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _TIMER_H_ */
diff --git a/tools/sdk/include/driver/driver/touch_pad.h b/tools/sdk/include/driver/driver/touch_pad.h
deleted file mode 100644
index 21e2e2ec7c4..00000000000
--- a/tools/sdk/include/driver/driver/touch_pad.h
+++ /dev/null
@@ -1,568 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_TOUCH_PAD_H_
-#define _DRIVER_TOUCH_PAD_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "esp_intr.h"
-#include "esp_err.h"
-#include "esp_intr_alloc.h"
-#include "soc/touch_channel.h"
-
-typedef enum {
-    TOUCH_PAD_NUM0 = 0, /*!< Touch pad channel 0 is GPIO4 */
-    TOUCH_PAD_NUM1,     /*!< Touch pad channel 1 is GPIO0 */
-    TOUCH_PAD_NUM2,     /*!< Touch pad channel 2 is GPIO2 */
-    TOUCH_PAD_NUM3,     /*!< Touch pad channel 3 is GPIO15*/
-    TOUCH_PAD_NUM4,     /*!< Touch pad channel 4 is GPIO13*/
-    TOUCH_PAD_NUM5,     /*!< Touch pad channel 5 is GPIO12*/
-    TOUCH_PAD_NUM6,     /*!< Touch pad channel 6 is GPIO14*/
-    TOUCH_PAD_NUM7,     /*!< Touch pad channel 7 is GPIO27*/
-    TOUCH_PAD_NUM8,     /*!< Touch pad channel 8 is GPIO33*/
-    TOUCH_PAD_NUM9,     /*!< Touch pad channel 9 is GPIO32*/
-    TOUCH_PAD_MAX,
-} touch_pad_t;
-
-typedef enum {
-    TOUCH_HVOLT_KEEP = -1, /*!<Touch sensor high reference voltage, no change  */
-    TOUCH_HVOLT_2V4 = 0,   /*!<Touch sensor high reference voltage, 2.4V  */
-    TOUCH_HVOLT_2V5,       /*!<Touch sensor high reference voltage, 2.5V  */
-    TOUCH_HVOLT_2V6,       /*!<Touch sensor high reference voltage, 2.6V  */
-    TOUCH_HVOLT_2V7,       /*!<Touch sensor high reference voltage, 2.7V  */
-    TOUCH_HVOLT_MAX,
-} touch_high_volt_t;
-
-typedef enum {
-    TOUCH_LVOLT_KEEP = -1, /*!<Touch sensor low reference voltage, no change  */
-    TOUCH_LVOLT_0V5 = 0,   /*!<Touch sensor low reference voltage, 0.5V  */
-    TOUCH_LVOLT_0V6,       /*!<Touch sensor low reference voltage, 0.6V  */
-    TOUCH_LVOLT_0V7,       /*!<Touch sensor low reference voltage, 0.7V  */
-    TOUCH_LVOLT_0V8,       /*!<Touch sensor low reference voltage, 0.8V  */
-    TOUCH_LVOLT_MAX,
-} touch_low_volt_t;
-
-typedef enum {
-    TOUCH_HVOLT_ATTEN_KEEP = -1,  /*!<Touch sensor high reference voltage attenuation, no change  */
-    TOUCH_HVOLT_ATTEN_1V5 = 0,    /*!<Touch sensor high reference voltage attenuation, 1.5V attenuation  */
-    TOUCH_HVOLT_ATTEN_1V,         /*!<Touch sensor high reference voltage attenuation, 1.0V attenuation  */
-    TOUCH_HVOLT_ATTEN_0V5,        /*!<Touch sensor high reference voltage attenuation, 0.5V attenuation  */
-    TOUCH_HVOLT_ATTEN_0V,         /*!<Touch sensor high reference voltage attenuation,   0V attenuation  */
-    TOUCH_HVOLT_ATTEN_MAX,
-} touch_volt_atten_t;
-
-typedef enum {
-    TOUCH_PAD_SLOPE_0 = 0,       /*!<Touch sensor charge / discharge speed, always zero  */
-    TOUCH_PAD_SLOPE_1 = 1,       /*!<Touch sensor charge / discharge speed, slowest  */
-    TOUCH_PAD_SLOPE_2 = 2,       /*!<Touch sensor charge / discharge speed */
-    TOUCH_PAD_SLOPE_3 = 3,       /*!<Touch sensor charge / discharge speed  */
-    TOUCH_PAD_SLOPE_4 = 4,       /*!<Touch sensor charge / discharge speed  */
-    TOUCH_PAD_SLOPE_5 = 5,       /*!<Touch sensor charge / discharge speed  */
-    TOUCH_PAD_SLOPE_6 = 6,       /*!<Touch sensor charge / discharge speed  */
-    TOUCH_PAD_SLOPE_7 = 7,       /*!<Touch sensor charge / discharge speed, fast  */
-    TOUCH_PAD_SLOPE_MAX,
-} touch_cnt_slope_t;
-
-typedef enum {
-    TOUCH_TRIGGER_BELOW = 0,   /*!<Touch interrupt will happen if counter value is less than threshold.*/
-    TOUCH_TRIGGER_ABOVE = 1,   /*!<Touch interrupt will happen if counter value is larger than threshold.*/
-    TOUCH_TRIGGER_MAX,
-} touch_trigger_mode_t;
-
-typedef enum {
-    TOUCH_TRIGGER_SOURCE_BOTH = 0,  /*!< wakeup interrupt is generated if both SET1 and SET2 are "touched"*/
-    TOUCH_TRIGGER_SOURCE_SET1 = 1,  /*!< wakeup interrupt is generated if SET1 is "touched"*/
-    TOUCH_TRIGGER_SOURCE_MAX,
-} touch_trigger_src_t;
-
-typedef enum {
-    TOUCH_PAD_TIE_OPT_LOW = 0,    /*!<Initial level of charging voltage, low level */
-    TOUCH_PAD_TIE_OPT_HIGH = 1,   /*!<Initial level of charging voltage, high level */
-    TOUCH_PAD_TIE_OPT_MAX,
-} touch_tie_opt_t;
-
-typedef enum {
-    TOUCH_FSM_MODE_TIMER = 0,   /*!<To start touch FSM by timer */
-    TOUCH_FSM_MODE_SW,          /*!<To start touch FSM by software trigger */
-    TOUCH_FSM_MODE_MAX,
-} touch_fsm_mode_t;
-
-
-typedef intr_handle_t touch_isr_handle_t;
-
-#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT   (0x1000)  /*!<The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options), max value is 0xffff */
-#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (0x7fff)  /*!<The timer frequency is 8Mhz, the max value is 0x7fff */
-#define TOUCH_PAD_MEASURE_WAIT_DEFAULT  (0xFF)    /*!<The timer frequency is 8Mhz, the max value is 0xff */
-#define TOUCH_FSM_MODE_DEFAULT          (TOUCH_FSM_MODE_SW)  /*!<The touch FSM my be started by the software or timer */
-#define TOUCH_TRIGGER_MODE_DEFAULT      (TOUCH_TRIGGER_BELOW)   /*!<Interrupts can be triggered if sensor value gets below or above threshold */
-#define TOUCH_TRIGGER_SOURCE_DEFAULT    (TOUCH_TRIGGER_SOURCE_SET1)  /*!<The wakeup trigger source can be SET1 or both SET1 and SET2 */
-#define TOUCH_PAD_BIT_MASK_MAX          (0x3ff)
-
-/**
- * @brief Initialize touch module.
- * @note  The default FSM mode is 'TOUCH_FSM_MODE_SW'. If you want to use interrupt trigger mode,
- *        then set it using function 'touch_pad_set_fsm_mode' to 'TOUCH_FSM_MODE_TIMER' after calling 'touch_pad_init'.
- * @return
- *     - ESP_OK Success
- *     - ESP_FAIL Touch pad init error
- */
-esp_err_t touch_pad_init();
-
-/**
- * @brief Un-install touch pad driver.
- * @note  After this function is called, other touch functions are prohibited from being called.
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Touch pad driver not initialized
- */
-esp_err_t touch_pad_deinit();
-
-/**
- * @brief Configure touch pad interrupt threshold.
- *
- * @note  If FSM mode is set to TOUCH_FSM_MODE_TIMER, this function will be blocked for one measurement cycle and wait for data to be valid.
- *
- * @param touch_num touch pad index
- * @param threshold interrupt threshold,
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG if argument wrong
- *     - ESP_FAIL if touch pad not initialized
- */
-esp_err_t touch_pad_config(touch_pad_t touch_num, uint16_t threshold);
-
-/**
- * @brief get touch sensor counter value.
- *        Each touch sensor has a counter to count the number of charge/discharge cycles.
- *        When the pad is not 'touched', we can get a number of the counter.
- *        When the pad is 'touched', the value in counter will get smaller because of the larger equivalent capacitance.
- *
- * @note This API requests hardware measurement once. If IIR filter mode is enabled,
- *       please use 'touch_pad_read_raw_data' interface instead.
- *
- * @param touch_num touch pad index
- * @param touch_value pointer to accept touch sensor value
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Touch pad parameter error
- *     - ESP_ERR_INVALID_STATE This touch pad hardware connection is error, the value of "touch_value" is 0.
- *     - ESP_FAIL Touch pad not initialized
- */
-esp_err_t touch_pad_read(touch_pad_t touch_num, uint16_t * touch_value);
-
-/**
- * @brief get filtered touch sensor counter value by IIR filter.
- *
- * @note touch_pad_filter_start has to be called before calling touch_pad_read_filtered.
- *       This function can be called from ISR
- *
- * @param touch_num touch pad index
- * @param touch_value pointer to accept touch sensor value
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Touch pad parameter error
- *     - ESP_ERR_INVALID_STATE This touch pad hardware connection is error, the value of "touch_value" is 0.
- *     - ESP_FAIL Touch pad not initialized
- */
-esp_err_t touch_pad_read_filtered(touch_pad_t touch_num, uint16_t *touch_value);
-
-/**
- * @brief get raw data (touch sensor counter value) from IIR filter process.
- *        Need not request hardware measurements.
- *
- * @note touch_pad_filter_start has to be called before calling touch_pad_read_raw_data.
- *       This function can be called from ISR
- *
- * @param touch_num touch pad index
- * @param touch_value pointer to accept touch sensor value
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Touch pad parameter error
- *     - ESP_ERR_INVALID_STATE This touch pad hardware connection is error, the value of "touch_value" is 0.
- *     - ESP_FAIL Touch pad not initialized
- */
-esp_err_t touch_pad_read_raw_data(touch_pad_t touch_num, uint16_t *touch_value);
-
-/**
-  * @brief Callback function that is called after each IIR filter calculation.
-  * @note This callback is called in timer task in each filtering cycle.
-  * @note This callback should not be blocked.
-  * @param raw_value  The latest raw data(touch sensor counter value) that
-  *        points to all channels(raw_value[0..TOUCH_PAD_MAX-1]).
-  * @param filtered_value  The latest IIR filtered data(calculated from raw data) that
-  *        points to all channels(filtered_value[0..TOUCH_PAD_MAX-1]).
-  *
-  */
-typedef void (* filter_cb_t)(uint16_t *raw_value, uint16_t *filtered_value);
-
-/**
- * @brief Register the callback function that is called after each IIR filter calculation.
- * @note The 'read_cb' callback is called in timer task in each filtering cycle.
- * @param read_cb  Pointer to filtered callback function.
- *                 If the argument passed in is NULL, the callback will stop.
- * @return
- *      - ESP_OK Success
- *      - ESP_ERR_INVALID_ARG set error
- */
-esp_err_t touch_pad_set_filter_read_cb(filter_cb_t read_cb);
-
-/**
- * @brief   Register touch-pad ISR,
- * @note Deprecated function, users should replace this with touch_pad_isr_register,
- *       because RTC modules share a same interrupt index.
- * @param fn  Pointer to ISR handler
- * @param arg  Parameter for ISR
- * @param unused Reserved, not used
- * @param handle_unused Reserved, not used
- * @return
- *     - ESP_OK Success ;
- *     - ESP_ERR_INVALID_ARG GPIO error
- *     - ESP_ERR_NO_MEM No memory
- */
-esp_err_t touch_pad_isr_handler_register(void(*fn)(void *), void *arg, int unused, intr_handle_t *handle_unused) __attribute__ ((deprecated));
-
-/**
- * @brief   Register touch-pad ISR.
- *          The handler will be attached to the same CPU core that this function is running on.
- * @param fn  Pointer to ISR handler
- * @param arg  Parameter for ISR
- * @return
- *     - ESP_OK Success ;
- *     - ESP_ERR_INVALID_ARG GPIO error
- *     - ESP_ERR_NO_MEM No memory
- */
-esp_err_t touch_pad_isr_register(intr_handler_t fn, void* arg);
-
-/**
- * @brief Deregister the handler previously registered using touch_pad_isr_handler_register
- * @param fn  handler function to call (as passed to touch_pad_isr_handler_register)
- * @param arg  argument of the handler (as passed to touch_pad_isr_handler_register)
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if a handler matching both fn and
- *        arg isn't registered
- */
-esp_err_t touch_pad_isr_deregister(void(*fn)(void *), void *arg);
-
-/**
- * @brief Set touch sensor measurement and sleep time
- * @param sleep_cycle  The touch sensor will sleep after each measurement.
- *                     sleep_cycle decide the interval between each measurement.
- *                     t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency).
- *                     The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
- * @param meas_cycle The duration of the touch sensor measurement.
- *                   t_meas = meas_cycle / 8M, the maximum measure time is 0xffff / 8M = 8.19 ms
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_cycle);
-
-/**
- * @brief Get touch sensor measurement and sleep time
- * @param sleep_cycle  Pointer to accept sleep cycle number
- * @param meas_cycle Pointer to accept measurement cycle count.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_cycle);
-
-/**
- * @brief Set touch sensor reference voltage, if the voltage gap between high and low reference voltage get less,
- *        the charging and discharging time would be faster, accordingly, the counter value would be larger.
- *        In the case of detecting very slight change of capacitance, we can narrow down the gap so as to increase
- *        the sensitivity. On the other hand, narrow voltage gap would also introduce more noise, but we can use a
- *        software filter to pre-process the counter value.
- * @param refh the value of DREFH
- * @param refl the value of DREFL
- * @param atten the attenuation on DREFH
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_set_voltage(touch_high_volt_t refh, touch_low_volt_t refl, touch_volt_atten_t atten);
-
-/**
- * @brief Get touch sensor reference voltage,
- * @param refh pointer to accept DREFH value
- * @param refl pointer to accept DREFL value
- * @param atten pointer to accept the attenuation on DREFH
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_voltage(touch_high_volt_t *refh, touch_low_volt_t *refl, touch_volt_atten_t *atten);
-
-/**
- * @brief Set touch sensor charge/discharge speed for each pad.
- *        If the slope is 0, the counter would always be zero.
- *        If the slope is 1, the charging and discharging would be slow, accordingly, the counter value would be small.
- *        If the slope is set 7, which is the maximum value, the charging and discharging would be fast, accordingly, the
- *        counter value would be larger.
- * @param touch_num touch pad index
- * @param slope touch pad charge/discharge speed
- * @param opt the initial voltage
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_set_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t slope, touch_tie_opt_t opt);
-
-/**
- * @brief Get touch sensor charge/discharge speed for each pad
- * @param touch_num touch pad index
- * @param slope pointer to accept touch pad charge/discharge slope
- * @param opt pointer to accept the initial voltage
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_get_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t *slope, touch_tie_opt_t *opt);
-
-/**
- * @brief Initialize touch pad GPIO
- * @param touch_num touch pad index
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_io_init(touch_pad_t touch_num);
-
-/**
- * @brief Set touch sensor FSM mode, the test action can be triggered by the timer,
- *        as well as by the software.
- * @param mode FSM mode
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_set_fsm_mode(touch_fsm_mode_t mode);
-
-/**
- * @brief Get touch sensor FSM mode
- * @param mode pointer to accept FSM mode
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_fsm_mode(touch_fsm_mode_t *mode);
-
-/**
- * @brief Trigger a touch sensor measurement, only support in SW mode of FSM
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_sw_start();
-
-/**
- * @brief Set touch sensor interrupt threshold
- * @param touch_num touch pad index
- * @param threshold threshold of touchpad count, refer to touch_pad_set_trigger_mode to see how to set trigger mode.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint16_t threshold);
-
-/**
- * @brief Get touch sensor interrupt threshold
- * @param touch_num touch pad index
- * @param threshold pointer to accept threshold
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint16_t *threshold);
-
-/**
- * @brief Set touch sensor interrupt trigger mode.
- *        Interrupt can be triggered either when counter result is less than
- *        threshold or when counter result is more than threshold.
- * @param mode touch sensor interrupt trigger mode
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_set_trigger_mode(touch_trigger_mode_t mode);
-
-/**
- * @brief Get touch sensor interrupt trigger mode
- * @param mode pointer to accept touch sensor interrupt trigger mode
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_trigger_mode(touch_trigger_mode_t *mode);
-
-/**
- * @brief Set touch sensor interrupt trigger source. There are two sets of touch signals.
- *        Set1 and set2 can be mapped to several touch signals. Either set will be triggered
- *        if at least one of its touch signal is 'touched'. The interrupt can be configured to be generated
- *        if set1 is triggered, or only if both sets are triggered.
- * @param src touch sensor interrupt trigger source
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_set_trigger_source(touch_trigger_src_t src);
-
-/**
- * @brief Get touch sensor interrupt trigger source
- * @param src pointer to accept touch sensor interrupt trigger source
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_trigger_source(touch_trigger_src_t *src);
-
-/**
- * @brief Set touch sensor group mask.
- *        Touch pad module has two sets of signals, 'Touched' signal is triggered only if
- *        at least one of touch pad in this group is "touched".
- *        This function will set the register bits according to the given bitmask.
- * @param set1_mask bitmask of touch sensor signal group1, it's a 10-bit value
- * @param set2_mask bitmask of touch sensor signal group2, it's a 10-bit value
- * @param en_mask bitmask of touch sensor work enable, it's a 10-bit value
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_set_group_mask(uint16_t set1_mask, uint16_t set2_mask, uint16_t en_mask);
-
-/**
- * @brief Get touch sensor group mask.
- * @param set1_mask pointer to accept bitmask of touch sensor signal group1, it's a 10-bit value
- * @param set2_mask pointer to accept bitmask of touch sensor signal group2, it's a 10-bit value
- * @param en_mask pointer to accept bitmask of touch sensor work enable, it's a 10-bit value
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_group_mask(uint16_t *set1_mask, uint16_t *set2_mask, uint16_t *en_mask);
-
-/**
- * @brief Clear touch sensor group mask.
- *        Touch pad module has two sets of signals, Interrupt is triggered only if
- *        at least one of touch pad in this group is "touched".
- *        This function will clear the register bits according to the given bitmask.
- * @param set1_mask bitmask touch sensor signal group1, it's a 10-bit value
- * @param set2_mask bitmask touch sensor signal group2, it's a 10-bit value
- * @param en_mask bitmask of touch sensor work enable, it's a 10-bit value
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_clear_group_mask(uint16_t set1_mask, uint16_t set2_mask, uint16_t en_mask);
-
-/**
- * @brief To clear the touch status register, usually use this function in touch ISR to clear status.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_clear_status();
-
-/**
- * @brief Get the touch sensor status, usually used in ISR to decide which pads are 'touched'.
- * @return
- *      - touch status
- */
-uint32_t touch_pad_get_status();
-
-/**
- * @brief To enable touch pad interrupt
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_intr_enable();
-
-/**
- * @brief To disable touch pad interrupt
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_intr_disable();
-
-/**
- * @brief set touch pad filter calibration period, in ms.
- *        Need to call touch_pad_filter_start before all touch filter APIs
- * @param new_period_ms filter period, in ms
- * @return
- *      - ESP_OK Success
- *      - ESP_ERR_INVALID_STATE driver state error
- *      - ESP_ERR_INVALID_ARG parameter error
- */
-esp_err_t touch_pad_set_filter_period(uint32_t new_period_ms);
-
-/**
- * @brief get touch pad filter calibration period, in ms
- *        Need to call touch_pad_filter_start before all touch filter APIs
- * @param p_period_ms pointer to accept period
- * @return
- *      - ESP_OK Success
- *      - ESP_ERR_INVALID_STATE driver state error
- *      - ESP_ERR_INVALID_ARG parameter error
- */
-esp_err_t touch_pad_get_filter_period(uint32_t* p_period_ms);
-
-/**
- * @brief start touch pad filter function
- *      This API will start a filter to process the noise in order to prevent false triggering
- *      when detecting slight change of capacitance.
- *      Need to call touch_pad_filter_start before all touch filter APIs
- *
- * @note This filter uses FreeRTOS timer, which is dispatched from a task with
- *       priority 1 by default on CPU 0. So if some application task with higher priority
- *       takes a lot of CPU0 time, then the quality of data obtained from this filter will be affected.
- *       You can adjust FreeRTOS timer task priority in menuconfig.
- * @param filter_period_ms filter calibration period, in ms
- * @return
- *      - ESP_OK Success
- *      - ESP_ERR_INVALID_ARG parameter error
- *      - ESP_ERR_NO_MEM No memory for driver
- *      - ESP_ERR_INVALID_STATE driver state error
- */
-esp_err_t touch_pad_filter_start(uint32_t filter_period_ms);
-
-/**
- * @brief stop touch pad filter function
- *        Need to call touch_pad_filter_start before all touch filter APIs
- * @return
- *      - ESP_OK Success
- *      - ESP_ERR_INVALID_STATE driver state error
- */
-esp_err_t touch_pad_filter_stop();
-
-/**
- * @brief delete touch pad filter driver and release the memory
- *        Need to call touch_pad_filter_start before all touch filter APIs
- * @return
- *      - ESP_OK Success
- *      - ESP_ERR_INVALID_STATE driver state error
- */
-esp_err_t touch_pad_filter_delete();
-
-/**
- * @brief Get the touch pad which caused wakeup from sleep
- * @param pad_num pointer to touch pad which caused wakeup
- * @return
- *      - ESP_OK Success
- *      - ESP_FAIL get status err
- */
-esp_err_t touch_pad_get_wakeup_status(touch_pad_t *pad_num);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif/*_DRIVER_TOUCH_PAD_H_*/
-
diff --git a/tools/sdk/include/driver/driver/uart.h b/tools/sdk/include/driver/driver/uart.h
deleted file mode 100644
index e716e542458..00000000000
--- a/tools/sdk/include/driver/driver/uart.h
+++ /dev/null
@@ -1,849 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DRIVER_UART_H_
-#define _DRIVER_UART_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "soc/uart_reg.h"
-#include "soc/uart_struct.h"
-#include "esp_err.h"
-#include "esp_intr_alloc.h"
-#include "driver/periph_ctrl.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-#include "freertos/xtensa_api.h"
-#include "freertos/task.h"
-#include "freertos/queue.h"
-#include "freertos/ringbuf.h"
-#include <esp_types.h>
-#include "soc/uart_channel.h"
-
-#define UART_FIFO_LEN           (128)        /*!< Length of the hardware FIFO buffers */
-#define UART_INTR_MASK          0x1ff        /*!< Mask of all UART interrupts */
-#define UART_LINE_INV_MASK      (0x3f << 19) /*!< TBD */
-#define UART_BITRATE_MAX        5000000      /*!< Max bit rate supported by UART */
-#define UART_PIN_NO_CHANGE      (-1)         /*!< Constant for uart_set_pin function which indicates that UART pin should not be changed */
-
-#define UART_INVERSE_DISABLE  (0x0)            /*!< Disable UART signal inverse*/
-#define UART_INVERSE_RXD   (UART_RXD_INV_M)    /*!< UART RXD input inverse*/
-#define UART_INVERSE_CTS   (UART_CTS_INV_M)    /*!< UART CTS input inverse*/
-#define UART_INVERSE_TXD   (UART_TXD_INV_M)    /*!< UART TXD output inverse*/
-#define UART_INVERSE_RTS   (UART_RTS_INV_M)    /*!< UART RTS output inverse*/
-
-/**
- * @brief UART mode selection
- */
-typedef enum {
-    UART_MODE_UART = 0x00,                      /*!< mode: regular UART mode*/
-    UART_MODE_RS485_HALF_DUPLEX = 0x01,         /*!< mode: half duplex RS485 UART mode control by RTS pin */
-    UART_MODE_IRDA = 0x02,                      /*!< mode: IRDA  UART mode*/
-    UART_MODE_RS485_COLLISION_DETECT = 0x03,    /*!< mode: RS485 collision detection UART mode (used for test purposes)*/
-    UART_MODE_RS485_APP_CTRL = 0x04,            /*!< mode: application control RS485 UART mode (used for test purposes)*/
-} uart_mode_t;
-
-/**
- * @brief UART word length constants
- */
-typedef enum {
-    UART_DATA_5_BITS = 0x0,    /*!< word length: 5bits*/
-    UART_DATA_6_BITS = 0x1,    /*!< word length: 6bits*/
-    UART_DATA_7_BITS = 0x2,    /*!< word length: 7bits*/
-    UART_DATA_8_BITS = 0x3,    /*!< word length: 8bits*/
-    UART_DATA_BITS_MAX = 0x4,
-} uart_word_length_t;
-
-/**
- * @brief UART stop bits number
- */
-typedef enum {
-    UART_STOP_BITS_1   = 0x1,  /*!< stop bit: 1bit*/
-    UART_STOP_BITS_1_5 = 0x2,  /*!< stop bit: 1.5bits*/
-    UART_STOP_BITS_2   = 0x3,  /*!< stop bit: 2bits*/
-    UART_STOP_BITS_MAX = 0x4,
-} uart_stop_bits_t;
-
-/**
- * @brief UART peripheral number
- */
-typedef enum {
-    UART_NUM_0 = 0x0,  /*!< UART base address 0x3ff40000*/
-    UART_NUM_1 = 0x1,  /*!< UART base address 0x3ff50000*/
-    UART_NUM_2 = 0x2,  /*!< UART base address 0x3ff6e000*/
-    UART_NUM_MAX,
-} uart_port_t;
-
-/**
- * @brief UART parity constants
- */
-typedef enum {
-    UART_PARITY_DISABLE = 0x0,  /*!< Disable UART parity*/
-    UART_PARITY_EVEN = 0x2,     /*!< Enable UART even parity*/
-    UART_PARITY_ODD  = 0x3      /*!< Enable UART odd parity*/
-} uart_parity_t;
-
-/**
- * @brief UART hardware flow control modes
- */
-typedef enum {
-    UART_HW_FLOWCTRL_DISABLE = 0x0,   /*!< disable hardware flow control*/
-    UART_HW_FLOWCTRL_RTS     = 0x1,   /*!< enable RX hardware flow control (rts)*/
-    UART_HW_FLOWCTRL_CTS     = 0x2,   /*!< enable TX hardware flow control (cts)*/
-    UART_HW_FLOWCTRL_CTS_RTS = 0x3,   /*!< enable hardware flow control*/
-    UART_HW_FLOWCTRL_MAX     = 0x4,
-} uart_hw_flowcontrol_t;
-
-/**
- * @brief UART configuration parameters for uart_param_config function
- */
-typedef struct {
-    int baud_rate;                      /*!< UART baud rate*/
-    uart_word_length_t data_bits;       /*!< UART byte size*/
-    uart_parity_t parity;               /*!< UART parity mode*/
-    uart_stop_bits_t stop_bits;         /*!< UART stop bits*/
-    uart_hw_flowcontrol_t flow_ctrl;    /*!< UART HW flow control mode (cts/rts)*/
-    uint8_t rx_flow_ctrl_thresh;        /*!< UART HW RTS threshold*/
-    bool use_ref_tick;                  /*!< Set to true if UART should be clocked from REF_TICK */
-} uart_config_t;
-
-/**
- * @brief UART interrupt configuration parameters for uart_intr_config function
- */
-typedef struct {
-    uint32_t intr_enable_mask;          /*!< UART interrupt enable mask, choose from UART_XXXX_INT_ENA_M under UART_INT_ENA_REG(i), connect with bit-or operator*/
-    uint8_t  rx_timeout_thresh;         /*!< UART timeout interrupt threshold (unit: time of sending one byte)*/
-    uint8_t  txfifo_empty_intr_thresh;  /*!< UART TX empty interrupt threshold.*/
-    uint8_t  rxfifo_full_thresh;        /*!< UART RX full interrupt threshold.*/
-} uart_intr_config_t;
-
-/**
- * @brief UART event types used in the ring buffer
- */
-typedef enum {
-    UART_DATA,              /*!< UART data event*/
-    UART_BREAK,             /*!< UART break event*/
-    UART_BUFFER_FULL,       /*!< UART RX buffer full event*/
-    UART_FIFO_OVF,          /*!< UART FIFO overflow event*/
-    UART_FRAME_ERR,         /*!< UART RX frame error event*/
-    UART_PARITY_ERR,        /*!< UART RX parity event*/
-    UART_DATA_BREAK,        /*!< UART TX data and break event*/
-    UART_PATTERN_DET,       /*!< UART pattern detected */
-    UART_EVENT_MAX,         /*!< UART event max index*/
-} uart_event_type_t;
-
-/**
- * @brief Event structure used in UART event queue
- */
-typedef struct {
-    uart_event_type_t type; /*!< UART event type */
-    size_t size;            /*!< UART data size for UART_DATA event*/
-} uart_event_t;
-
-typedef intr_handle_t uart_isr_handle_t;
-
-/**
- * @brief Set UART data bits.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param data_bit UART data bits
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit);
-
-/**
- * @brief Get UART data bits.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param data_bit Pointer to accept value of UART data bits.
- *
- * @return
- *     - ESP_FAIL  Parameter error
- *     - ESP_OK    Success, result will be put in (*data_bit)
- */
-esp_err_t uart_get_word_length(uart_port_t uart_num, uart_word_length_t* data_bit);
-
-/**
- * @brief Set UART stop bits.
- *
- * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param stop_bits  UART stop bits
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Fail
- */
-esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bits);
-
-/**
- * @brief Get UART stop bits.
- *
- * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param stop_bits  Pointer to accept value of UART stop bits.
- *
- * @return
- *     - ESP_FAIL Parameter error
- *     - ESP_OK   Success, result will be put in (*stop_bit)
- */
-esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t* stop_bits);
-
-/**
- * @brief Set UART parity mode.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param parity_mode the enum of uart parity configuration
- *
- * @return
- *     - ESP_FAIL  Parameter error
- *     - ESP_OK    Success
- */
-esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode);
-
-/**
- * @brief Get UART parity mode.
- *
- * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param parity_mode Pointer to accept value of UART parity mode.
- *
- * @return
- *     - ESP_FAIL  Parameter error
- *     - ESP_OK    Success, result will be put in (*parity_mode)
- *
- */
-esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t* parity_mode);
-
-/**
- * @brief Set UART baud rate.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param baudrate UART baud rate.
- *
- * @return
- *     - ESP_FAIL Parameter error
- *     - ESP_OK   Success
- */
-esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baudrate);
-
-/**
- * @brief Get UART baud rate.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param baudrate Pointer to accept value of UART baud rate
- *
- * @return
- *     - ESP_FAIL Parameter error
- *     - ESP_OK   Success, result will be put in (*baudrate)
- *
- */
-esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t* baudrate);
-
-/**
- * @brief Set UART line inverse mode
- *
- * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param inverse_mask Choose the wires that need to be inverted.
- *        Inverse_mask should be chosen from 
- *        UART_INVERSE_RXD / UART_INVERSE_TXD / UART_INVERSE_RTS / UART_INVERSE_CTS,
- *        combined with OR operation.
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask);
-
-/**
- * @brief Set hardware flow control.
- *
- * @param uart_num   UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param flow_ctrl Hardware flow control mode
- * @param rx_thresh Threshold of Hardware RX flow control (0 ~ UART_FIFO_LEN).
- *        Only when UART_HW_FLOWCTRL_RTS is set, will the rx_thresh value be set.
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh);
-
-/**
- * @brief Set software flow control.
- *
- * @param uart_num   UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param enable     switch on or off
- * @param rx_thresh_xon  low water mark
- * @param rx_thresh_xoff high water mark
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
- esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable, uint8_t rx_thresh_xon,  uint8_t rx_thresh_xoff);
-
-/**
- * @brief Get hardware flow control mode
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param flow_ctrl Option for different flow control mode.
- *
- * @return
- *     - ESP_FAIL Parameter error
- *     - ESP_OK   Success, result will be put in (*flow_ctrl)
- */
-esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flow_ctrl);
-
-/**
- * @brief Clear UART interrupt status
- *
- * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param clr_mask  Bit mask of the interrupt status to be cleared.
- *                  The bit mask should be composed from the fields of register UART_INT_CLR_REG.
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_clear_intr_status(uart_port_t uart_num, uint32_t clr_mask);
-
-/**
- * @brief Set UART interrupt enable
- *
- * @param uart_num     UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param enable_mask  Bit mask of the enable bits.
- *                     The bit mask should be composed from the fields of register UART_INT_ENA_REG.
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_enable_intr_mask(uart_port_t uart_num, uint32_t enable_mask);
-
-/**
- * @brief Clear UART interrupt enable bits
- *
- * @param uart_num      UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param disable_mask  Bit mask of the disable bits.
- *                      The bit mask should be composed from the fields of register UART_INT_ENA_REG.
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask);
-
-/**
- * @brief Enable UART RX interrupt (RX_FULL & RX_TIMEOUT INTERRUPT)
- *
- * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_enable_rx_intr(uart_port_t uart_num);
-
-/**
- * @brief Disable UART RX interrupt (RX_FULL & RX_TIMEOUT INTERRUPT)
- *
- * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_disable_rx_intr(uart_port_t uart_num);
-
-/**
- * @brief Disable UART TX interrupt (TX_FULL & TX_TIMEOUT INTERRUPT)
- *
- * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_disable_tx_intr(uart_port_t uart_num);
-
-/**
- * @brief Enable UART TX interrupt (TX_FULL & TX_TIMEOUT INTERRUPT)
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param enable  1: enable; 0: disable
- * @param thresh  Threshold of TX interrupt, 0 ~ UART_FIFO_LEN
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh);
-
-/**
- * @brief Register UART interrupt handler (ISR).
- *
- * @note UART ISR handler will be attached to the same CPU core that this function is running on.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param fn  Interrupt handler function.
- * @param arg parameter for handler function
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info. 
- * @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will
- *        be returned here.
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void*), void * arg, int intr_alloc_flags,  uart_isr_handle_t *handle);
-
-/**
- * @brief Free UART interrupt handler registered by uart_isr_register. Must be called on the same core as
- * uart_isr_register was called.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_isr_free(uart_port_t uart_num);
-
-/**
- * @brief Set UART pin number
- *
- * @note Internal signal can be output to multiple GPIO pads.
- *       Only one GPIO pad can connect with input signal.
- *
- * @note Instead of GPIO number a macro 'UART_PIN_NO_CHANGE' may be provided 
-         to keep the currently allocated pin.
- *
- * @param uart_num   UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param tx_io_num  UART TX pin GPIO number.
- * @param rx_io_num  UART RX pin GPIO number.
- * @param rts_io_num UART RTS pin GPIO number.
- * @param cts_io_num UART CTS pin GPIO number.
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num);
-
-/**
- * @brief Manually set the UART RTS pin level.
- * @note  UART must be configured with hardware flow control disabled.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param level    1: RTS output low (active); 0: RTS output high (block)
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_set_rts(uart_port_t uart_num, int level);
-
-/**
- * @brief Manually set the UART DTR pin level.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param level    1: DTR output low; 0: DTR output high
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_set_dtr(uart_port_t uart_num, int level);
-
-/**
- * @brief Set UART idle interval after tx FIFO is empty
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param idle_num idle interval after tx FIFO is empty(unit: the time it takes to send one bit
- *        under current baudrate)
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_set_tx_idle_num(uart_port_t uart_num, uint16_t idle_num);
-
-/**
- * @brief Set UART configuration parameters.
- *
- * @param uart_num    UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param uart_config UART parameter settings
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_config);
-
-/**
- * @brief Configure UART interrupts.
- *
- * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param intr_conf UART interrupt settings
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_conf);
-
-/**
- * @brief Install UART driver.
- *
- * UART ISR handler will be attached to the same CPU core that this function is running on.
- *
- * @note  Rx_buffer_size should be greater than UART_FIFO_LEN. Tx_buffer_size should be either zero or greater than UART_FIFO_LEN.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param rx_buffer_size UART RX ring buffer size.
- * @param tx_buffer_size UART TX ring buffer size.
- *        If set to zero, driver will not use TX buffer, TX function will block task until all data have been sent out.
- * @param queue_size UART event queue size/depth.
- * @param uart_queue UART event queue handle (out param). On success, a new queue handle is written here to provide
- *        access to UART events. If set to NULL, driver will not use an event queue.
- * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
- *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info. Do not set ESP_INTR_FLAG_IRAM here
- *        (the driver's ISR handler is not located in IRAM)
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_buffer_size, int queue_size, QueueHandle_t* uart_queue, int intr_alloc_flags);
-
-/**
- * @brief Uninstall UART driver.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_driver_delete(uart_port_t uart_num);
-
-/**
- * @brief Wait until UART TX FIFO is empty.
- *
- * @param uart_num      UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param ticks_to_wait Timeout, count in RTOS ticks
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- *     - ESP_ERR_TIMEOUT  Timeout
- */
-esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait);
-
-/**
- * @brief Send data to the UART port from a given buffer and length.
- * 
- * This function will not wait for enough space in TX FIFO. It will just fill the available TX FIFO and return when the FIFO is full.
- * @note This function should only be used when UART TX buffer is not enabled.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param buffer data buffer address
- * @param len    data length to send
- *
- * @return
- *     - (-1)  Parameter error
- *     - OTHERS (>=0) The number of bytes pushed to the TX FIFO
- */
-int uart_tx_chars(uart_port_t uart_num, const char* buffer, uint32_t len);
-
-/**
- * @brief Send data to the UART port from a given buffer and length,
- *
- * If the UART driver's parameter 'tx_buffer_size' is set to zero:
- * This function will not return until all the data have been sent out, or at least pushed into TX FIFO.
- *
- * Otherwise, if the 'tx_buffer_size' > 0, this function will return after copying all the data to tx ring buffer,
- * UART ISR will then move data from the ring buffer to TX FIFO gradually.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param src   data buffer address
- * @param size  data length to send
- *
- * @return
- *     - (-1) Parameter error
- *     - OTHERS (>=0) The number of bytes pushed to the TX FIFO
- */
-int uart_write_bytes(uart_port_t uart_num, const char* src, size_t size);
-
-/**
- * @brief Send data to the UART port from a given buffer and length,
- *
- * If the UART driver's parameter 'tx_buffer_size' is set to zero:
- * This function will not return until all the data and the break signal have been sent out.
- * After all data is sent out, send a break signal.
- *
- * Otherwise, if the 'tx_buffer_size' > 0, this function will return after copying all the data to tx ring buffer,
- * UART ISR will then move data from the ring buffer to TX FIFO gradually.
- * After all data sent out, send a break signal.
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param src   data buffer address
- * @param size  data length to send
- * @param brk_len break signal duration(unit: the time it takes to send one bit at current baudrate)
- *
- * @return
- *     - (-1) Parameter error
- *     - OTHERS (>=0) The number of bytes pushed to the TX FIFO
- */
-int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t size, int brk_len);
-
-/**
- * @brief UART read bytes from UART buffer
- *
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- * @param buf     pointer to the buffer.
- * @param length  data length
- * @param ticks_to_wait sTimeout, count in RTOS ticks
- *
- * @return
- *     - (-1) Error
- *     - OTHERS (>=0) The number of bytes read from UART FIFO
- */
-int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickType_t ticks_to_wait);
-
-/**
- * @brief Alias of uart_flush_input.
- *        UART ring buffer flush. This will discard all data in the UART RX buffer.
- * @note  Instead of waiting the data sent out, this function will clear UART rx buffer.
- *        In order to send all the data in tx FIFO, we can use uart_wait_tx_done function.
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_flush(uart_port_t uart_num);
-
-/**
- * @brief Clear input buffer, discard all the data is in the ring-buffer.
- * @note  In order to send all the data in tx FIFO, we can use uart_wait_tx_done function.
- * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_flush_input(uart_port_t uart_num);
-
-/**
- * @brief   UART get RX ring buffer cached data length
- *
- * @param   uart_num UART port number.
- * @param   size Pointer of size_t to accept cached data length
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size);
-
-/**
- * @brief   UART disable pattern detect function.
- *          Designed for applications like 'AT commands'.
- *          When the hardware detects a series of one same character, the interrupt will be triggered.
- *
- * @param uart_num UART port number.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num);
-
-/**
- * @brief UART enable pattern detect function.
- *        Designed for applications like 'AT commands'.
- *        When the hardware detect a series of one same character, the interrupt will be triggered.
- *
- * @param uart_num UART port number.
- * @param pattern_chr character of the pattern
- * @param chr_num number of the character, 8bit value.
- * @param chr_tout timeout of the interval between each pattern characters, 24bit value, unit is APB (80Mhz) clock cycle.
- *        When the duration is less than this value, it will not take this data as at_cmd char
- * @param post_idle idle time after the last pattern character, 24bit value, unit is APB (80Mhz) clock cycle.
- *        When the duration is less than this value, it will not take the previous data as the last at_cmd char
- * @param pre_idle idle time before the first pattern character, 24bit value, unit is APB (80Mhz) clock cycle.
- *        When the duration is less than this value, it will not take this data as the first at_cmd char
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle);
-
-/**
- * @brief Return the nearest detected pattern position in buffer.
- *        The positions of the detected pattern are saved in a queue,
- *        this function will dequeue the first pattern position and move the pointer to next pattern position.
- * @note  If the RX buffer is full and flow control is not enabled,
- *        the detected pattern may not be found in the rx buffer due to overflow.
- *
- *        The following APIs will modify the pattern position info:
- *        uart_flush_input, uart_read_bytes, uart_driver_delete, uart_pop_pattern_pos
- *        It is the application's responsibility to ensure atomic access to the pattern queue and the rx data buffer
- *        when using pattern detect feature.
- *
- * @param uart_num UART port number
- * @return
- *     - (-1) No pattern found for current index or parameter error
- *     - others the pattern position in rx buffer.
- */
-int uart_pattern_pop_pos(uart_port_t uart_num);
-
-/**
- * @brief Return the nearest detected pattern position in buffer.
- *        The positions of the detected pattern are saved in a queue,
- *        This function do nothing to the queue.
- * @note  If the RX buffer is full and flow control is not enabled,
- *        the detected pattern may not be found in the rx buffer due to overflow.
- *
- *        The following APIs will modify the pattern position info:
- *        uart_flush_input, uart_read_bytes, uart_driver_delete, uart_pop_pattern_pos
- *        It is the application's responsibility to ensure atomic access to the pattern queue and the rx data buffer
- *        when using pattern detect feature.
- *
- * @param uart_num UART port number
- * @return
- *     - (-1) No pattern found for current index or parameter error
- *     - others the pattern position in rx buffer.
- */
-int uart_pattern_get_pos(uart_port_t uart_num);
-
-/**
- * @brief Allocate a new memory with the given length to save record the detected pattern position in rx buffer.
- * @param uart_num UART port number
- * @param queue_length Max queue length for the detected pattern.
- *        If the queue length is not large enough, some pattern positions might be lost.
- *        Set this value to the maximum number of patterns that could be saved in data buffer at the same time.
- * @return
- *     - ESP_ERR_NO_MEM No enough memory
- *     - ESP_ERR_INVALID_STATE Driver not installed
- *     - ESP_FAIL Parameter error
- *     - ESP_OK Success
- */
-esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length);
-
-/**
- * @brief UART set communication mode 
- * @note  This function must be executed after uart_driver_install(), when the driver object is initialized.
- * @param uart_num     Uart number to configure
- * @param mode UART    UART mode to set 
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode);
-
-/**
- * @brief UART set threshold timeout for TOUT feature
- *
- * @param uart_num     Uart number to configure
- * @param tout_thresh  This parameter defines timeout threshold in uart symbol periods. The maximum value of threshold is 126. 
- *        tout_thresh = 1, defines TOUT interrupt timeout equal to transmission time of one symbol (~11 bit) on current baudrate. 
- *        If the time is expired the UART_RXFIFO_TOUT_INT interrupt is triggered. If tout_thresh == 0,
- *        the TOUT feature is disabled.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_INVALID_STATE Driver is not installed
- */
-esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh);
-
-/**
- * @brief Returns collision detection flag for RS485 mode
- *        Function returns the collision detection flag into variable pointed by collision_flag.
- *        *collision_flag = true, if collision detected else it is equal to false.
- *        This function should be executed when actual transmission is completed (after uart_write_bytes()).
- *
- * @param uart_num       Uart number to configure
- * @param collision_flag Pointer to variable of type bool to return collision flag.
- *
- * @return
- *     - ESP_OK Success 
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag);
-
-/**
- * @brief Set the number of RX pin signal edges for light sleep wakeup
- *
- * UART can be used to wake up the system from light sleep. This feature works
- * by counting the number of positive edges on RX pin and comparing the count to
- * the threshold. When the count exceeds the threshold, system is woken up from
- * light sleep. This function allows setting the threshold value.
- *
- * Stop bit and parity bits (if enabled) also contribute to the number of edges.
- * For example, letter 'a' with ASCII code 97 is encoded as 0100001101 on the wire
- * (with 8n1 configuration), start and stop bits included. This sequence has 3
- * positive edges (transitions from 0 to 1). Therefore, to wake up the system
- * when 'a' is sent, set wakeup_threshold=3.
- *
- * The character that triggers wakeup is not received by UART (i.e. it can not
- * be obtained from UART FIFO). Depending on the baud rate, a few characters
- * after that will also not be received. Note that when the chip enters and exits
- * light sleep mode, APB frequency will be changing. To make sure that UART has
- * correct baud rate all the time, select REF_TICK as UART clock source,
- * by setting use_ref_tick field in uart_config_t to true.
- *
- * @note in ESP32, the wakeup signal can only be input via IO_MUX (i.e.
- *       GPIO3 should be configured as function_1 to wake up UART0,
- *       GPIO9 should be configured as function_5 to wake up UART1), UART2
- *       does not support light sleep wakeup feature.
- *
- * @param uart_num  UART number
- * @param wakeup_threshold  number of RX edges for light sleep wakeup, value is 3 .. 0x3ff.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if uart_num is incorrect or wakeup_threshold is
- *        outside of [3, 0x3ff] range.
- */
-esp_err_t uart_set_wakeup_threshold(uart_port_t uart_num, int wakeup_threshold);
-
-/**
- * @brief Get the number of RX pin signal edges for light sleep wakeup.
- *
- * See description of uart_set_wakeup_threshold for the explanation of UART
- * wakeup feature.
- *
- * @param uart_num  UART number
- * @param[out] out_wakeup_threshold  output, set to the current value of wakeup
- *                                   threshold for the given UART.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if out_wakeup_threshold is NULL
- */
-esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int* out_wakeup_threshold);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*_DRIVER_UART_H_*/
diff --git a/tools/sdk/include/driver/driver/uart_select.h b/tools/sdk/include/driver/driver/uart_select.h
deleted file mode 100644
index 24f06c1de61..00000000000
--- a/tools/sdk/include/driver/driver/uart_select.h
+++ /dev/null
@@ -1,49 +0,0 @@
-
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _UART_SELECT_H_
-#define _UART_SELECT_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "driver/uart.h"
-
-typedef enum {
-    UART_SELECT_READ_NOTIF,
-    UART_SELECT_WRITE_NOTIF,
-    UART_SELECT_ERROR_NOTIF,
-} uart_select_notif_t;
-
-typedef void (*uart_select_notif_callback_t)(uart_port_t uart_num, uart_select_notif_t uart_select_notif, BaseType_t *task_woken);
-
-/**
- * @brief Set notification callback function for select() events
- * @param uart_num UART port number
- * @param uart_select_notif_callback callback function
- */
-void uart_set_select_notif_callback(uart_port_t uart_num, uart_select_notif_callback_t uart_select_notif_callback);
-
-/**
- * @brief Get mutex guarding select() notifications
- */
-portMUX_TYPE *uart_get_selectlock();
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //_UART_SELECT_H_
diff --git a/tools/sdk/include/efuse/esp_efuse.h b/tools/sdk/include/efuse/esp_efuse.h
deleted file mode 100644
index 68f8491e49e..00000000000
--- a/tools/sdk/include/efuse/esp_efuse.h
+++ /dev/null
@@ -1,362 +0,0 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_EFUSE_MANAGER_H_
-#define _ESP_EFUSE_MANAGER_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include "esp_err.h"
-#include "esp_log.h"
-
-#define ESP_ERR_EFUSE                              0x1600                     /*!< Base error code for efuse api. */
-#define ESP_OK_EFUSE_CNT                          (ESP_ERR_EFUSE + 0x01)      /*!< OK the required number of bits is set. */
-#define ESP_ERR_EFUSE_CNT_IS_FULL                 (ESP_ERR_EFUSE + 0x02)      /*!< Error field is full. */
-#define ESP_ERR_EFUSE_REPEATED_PROG               (ESP_ERR_EFUSE + 0x03)      /*!< Error repeated programming of programmed bits is strictly forbidden. */
-#define ESP_ERR_CODING                            (ESP_ERR_EFUSE + 0x04)      /*!< Error while a encoding operation. */
-
-/**
- * @brief Type of eFuse blocks
- */
-typedef enum {
-    EFUSE_BLK0 = 0,     /**< Number of eFuse block. Reserved. */
-    EFUSE_BLK1 = 1,     /**< Number of eFuse block. Used for Flash Encryption. If not using that Flash Encryption feature, they can be used for another purpose. */
-    EFUSE_BLK2 = 2,     /**< Number of eFuse block. Used for Secure Boot. If not using that Secure Boot feature, they can be used for another purpose. */
-    EFUSE_BLK3 = 3      /**< Number of eFuse block. Uses for the purpose of the user. */
-} esp_efuse_block_t;
-
-/**
- * @brief Type of coding scheme
- */
-typedef enum {
-    EFUSE_CODING_SCHEME_NONE    = 0,    /**< None */
-    EFUSE_CODING_SCHEME_3_4     = 1,    /**< 3/4 coding */
-    EFUSE_CODING_SCHEME_REPEAT  = 2,    /**< Repeat coding */
-} esp_efuse_coding_scheme_t;
-
-/**
-* @brief Structure eFuse field
- */
-typedef struct {
-    esp_efuse_block_t   efuse_block: 8; /**< Block of eFuse */
-    uint8_t             bit_start;      /**< Start bit [0..255] */
-    uint16_t            bit_count;      /**< Length of bit field [1..-]*/
-} esp_efuse_desc_t;
-
-/**
- * @brief   Reads bits from EFUSE field and writes it into an array.
- *
- * The number of read bits will be limited to the minimum value
- * from the description of the bits in "field" structure or "dst_size_bits" required size.
- * Use "esp_efuse_get_field_size()" function to determine the length of the field.
- * @param[in]  field          A pointer to the structure describing the fields of efuse.
- * @param[out] dst            A pointer to array that will contain the result of reading.
- * @param[in]  dst_size_bits  The number of bits required to read.
- *                            If the requested number of bits is greater than the field,
- *                            the number will be limited to the field size.
- *
- * @return
- *    - ESP_OK: The operation was successfully completed.
- *    - ESP_ERR_INVALID_ARG: Error in the passed arguments.
- */
-esp_err_t esp_efuse_read_field_blob(const esp_efuse_desc_t* field[], void* dst, size_t dst_size_bits);
-
-/**
- * @brief   Reads bits from EFUSE field and returns number of bits programmed as "1".
- *
- * If the bits are set not sequentially, they will still be counted.
- * @param[in]  field          A pointer to the structure describing the fields of efuse.
- * @param[out] out_cnt        A pointer that will contain the number of programmed as "1" bits.
- *
- * @return
- *    - ESP_OK: The operation was successfully completed.
- *    - ESP_ERR_INVALID_ARG: Error in the passed arguments.
- */
-esp_err_t esp_efuse_read_field_cnt(const esp_efuse_desc_t* field[], size_t* out_cnt);
-
-/**
- * @brief   Writes array to EFUSE field.
- *
- * The number of write bits will be limited to the minimum value
- * from the description of the bits in "field" structure or "src_size_bits" required size.
- * Use "esp_efuse_get_field_size()" function to determine the length of the field.
- * After the function is completed, the writing registers are cleared.
- * @param[in]  field          A pointer to the structure describing the fields of efuse.
- * @param[in]  src            A pointer to array that contains the data for writing.
- * @param[in]  src_size_bits  The number of bits required to write.
- *
- * @return
- *    - ESP_OK: The operation was successfully completed.
- *    - ESP_ERR_INVALID_ARG: Error in the passed arguments.
- *    - ESP_ERR_EFUSE_REPEATED_PROG: Error repeated programming of programmed bits is strictly forbidden.
- *    - ESP_ERR_CODING: Error range of data does not match the coding scheme.
- */
-esp_err_t esp_efuse_write_field_blob(const esp_efuse_desc_t* field[], const void* src, size_t src_size_bits);
-
-/**
- * @brief   Writes a required count of bits as "1" to EFUSE field.
- *
- * If there are no free bits in the field to set the required number of bits to "1",
- * ESP_ERR_EFUSE_CNT_IS_FULL error is returned, the field will not be partially recorded.
- * After the function is completed, the writing registers are cleared.
- * @param[in]  field          A pointer to the structure describing the fields of efuse.
- * @param[in]  cnt            Required number of programmed as "1" bits.
- *
- * @return
- *    - ESP_OK: The operation was successfully completed.
- *    - ESP_ERR_INVALID_ARG: Error in the passed arguments.
- *    - ESP_ERR_EFUSE_CNT_IS_FULL: Not all requested cnt bits is set.
- */
-esp_err_t esp_efuse_write_field_cnt(const esp_efuse_desc_t* field[], size_t cnt);
-
-/**
- * @brief   Sets a write protection for the whole block.
- *
- * After that, it is impossible to write to this block.
- * The write protection does not apply to block 0.
- * @param[in]  blk          Block number of eFuse. (EFUSE_BLK1, EFUSE_BLK2 and EFUSE_BLK3)
- *
- * @return
- *    - ESP_OK: The operation was successfully completed.
- *    - ESP_ERR_INVALID_ARG: Error in the passed arguments.
- *    - ESP_ERR_EFUSE_CNT_IS_FULL: Not all requested cnt bits is set.
- *    - ESP_ERR_NOT_SUPPORTED: The block does not support this command.
- */
-esp_err_t esp_efuse_set_write_protect(esp_efuse_block_t blk);
-
-/**
- * @brief   Sets a read protection for the whole block.
- *
- * After that, it is impossible to read from this block.
- * The read protection does not apply to block 0.
- * @param[in]  blk          Block number of eFuse. (EFUSE_BLK1, EFUSE_BLK2 and EFUSE_BLK3)
- *
- * @return
- *    - ESP_OK: The operation was successfully completed.
- *    - ESP_ERR_INVALID_ARG: Error in the passed arguments.
- *    - ESP_ERR_EFUSE_CNT_IS_FULL: Not all requested cnt bits is set.
- *    - ESP_ERR_NOT_SUPPORTED: The block does not support this command.
- */
-esp_err_t esp_efuse_set_read_protect(esp_efuse_block_t blk);
-
-/**
- * @brief   Returns the number of bits used by field.
- *
- * @param[in]  field          A pointer to the structure describing the fields of efuse.
- *
- * @return Returns the number of bits used by field.
- */
-int esp_efuse_get_field_size(const esp_efuse_desc_t* field[]);
-
-/**
- * @brief   Returns value of efuse register.
- *
- * This is a thread-safe implementation.
- * Example: EFUSE_BLK2_RDATA3_REG where (blk=2, num_reg=3)
- * @param[in]  blk     Block number of eFuse.
- * @param[in]  num_reg The register number in the block.
- *
- * @return Value of register
- */
-uint32_t esp_efuse_read_reg(esp_efuse_block_t blk, unsigned int num_reg);
-
-/**
- * @brief   Write value to efuse register.
- *
- * Apply a coding scheme if necessary.
- * This is a thread-safe implementation.
- * Example: EFUSE_BLK3_WDATA0_REG where (blk=3, num_reg=0)
- * @param[in]  blk     Block number of eFuse.
- * @param[in]  num_reg The register number in the block.
- * @param[in]  val     Value to write.
- *
- * @return
- *      - ESP_OK: The operation was successfully completed.
- *      - ESP_ERR_EFUSE_REPEATED_PROG: Error repeated programming of programmed bits is strictly forbidden.
- */
-esp_err_t esp_efuse_write_reg(esp_efuse_block_t blk, unsigned int num_reg, uint32_t val);
-
-/**
- * @brief   Return efuse coding scheme for blocks.
- *
- * Note: The coding scheme is applicable only to 1, 2 and 3 blocks. For 0 block, the coding scheme is always ``NONE``.
- *
- * @param[in]  blk     Block number of eFuse.
- * @return Return efuse coding scheme for blocks
- */
-esp_efuse_coding_scheme_t esp_efuse_get_coding_scheme(esp_efuse_block_t blk);
-
-/**
- * @brief   Read key to efuse block starting at the offset and the required size.
- *
- * @param[in]  blk             Block number of eFuse.
- * @param[in]  dst_key         A pointer to array that will contain the result of reading.
- * @param[in]  offset_in_bits  Start bit in block.
- * @param[in]  size_bits       The number of bits required to read.
- *
- * @return
- *    - ESP_OK: The operation was successfully completed.
- *    - ESP_ERR_INVALID_ARG: Error in the passed arguments.
- *    - ESP_ERR_CODING: Error range of data does not match the coding scheme.
- */
-esp_err_t esp_efuse_read_block(esp_efuse_block_t blk, void* dst_key, size_t offset_in_bits, size_t size_bits);
-
-/**
- * @brief   Write key to efuse block starting at the offset and the required size.
- *
- * @param[in]  blk             Block number of eFuse.
- * @param[in]  src_key         A pointer to array that contains the key for writing.
- * @param[in]  offset_in_bits  Start bit in block.
- * @param[in]  size_bits       The number of bits required to write.
- *
- * @return
- *    - ESP_OK: The operation was successfully completed.
- *    - ESP_ERR_INVALID_ARG: Error in the passed arguments.
- *    - ESP_ERR_CODING: Error range of data does not match the coding scheme.
- *    - ESP_ERR_EFUSE_REPEATED_PROG: Error repeated programming of programmed bits
- */
-esp_err_t esp_efuse_write_block(esp_efuse_block_t blk, const void* src_key, size_t offset_in_bits, size_t size_bits);
-
-/**
- * @brief   Returns chip version from efuse
- *
- * @return chip version
- */
-uint8_t esp_efuse_get_chip_ver(void);
-
-/**
- * @brief   Returns chip package from efuse
- *
- * @return chip package
- */
-uint32_t esp_efuse_get_pkg_ver(void);
-
-/* @brief Permanently update values written to the efuse write registers
- *
- * After updating EFUSE_BLKx_WDATAx_REG registers with new values to
- * write, call this function to permanently write them to efuse.
- *
- * @note Setting bits in efuse is permanent, they cannot be unset.
- *
- * @note Due to this restriction you don't need to copy values to
- * Efuse write registers from the matching read registers, bits which
- * are set in the read register but unset in the matching write
- * register will be unchanged when new values are burned.
- *
- * @note This function is not threadsafe, if calling code updates
- * efuse values from multiple tasks then this is caller's
- * responsibility to serialise.
- *
- * After burning new efuses, the read registers are updated to match
- * the new efuse values.
- */
-void esp_efuse_burn_new_values(void);
-
-/* @brief Reset efuse write registers
- *
- * Efuse write registers are written to zero, to negate
- * any changes that have been staged here.
- *
- * @note This function is not threadsafe, if calling code updates
- * efuse values from multiple tasks then this is caller's
- * responsibility to serialise.
- */
-void esp_efuse_reset(void);
-
-/* @brief Disable BASIC ROM Console via efuse
- *
- * By default, if booting from flash fails the ESP32 will boot a
- * BASIC console in ROM.
- *
- * Call this function (from bootloader or app) to permanently
- * disable the console on this chip.
- */
-void esp_efuse_disable_basic_rom_console(void);
-
-/* @brief Encode one or more sets of 6 byte sequences into
- * 8 bytes suitable for 3/4 Coding Scheme.
- *
- * This function is only useful if the CODING_SCHEME efuse
- * is set to value 1 for 3/4 Coding Scheme.
- *
- * @param[in] in_bytes Pointer to a sequence of bytes to encode for 3/4 Coding Scheme. Must have length in_bytes_len. After being written to hardware, these bytes will read back as little-endian words.
- * @param[out] out_words Pointer to array of words suitable for writing to efuse write registers. Array must contain 2 words (8 bytes) for every 6 bytes in in_bytes_len. Can be a pointer to efuse write registers.
- * @param in_bytes_len. Length of array pointed to by in_bytes, in bytes. Must be a multiple of 6.
- *
- * @return ESP_ERR_INVALID_ARG if either pointer is null or in_bytes_len is not a multiple of 6. ESP_OK otherwise.
- */
-esp_err_t esp_efuse_apply_34_encoding(const uint8_t *in_bytes, uint32_t *out_words, size_t in_bytes_len);
-
-/* @brief Write random data to efuse key block write registers
- *
- * @note Caller is responsible for ensuring efuse
- * block is empty and not write protected, before calling.
- *
- * @note Behaviour depends on coding scheme: a 256-bit key is
- * generated and written for Coding Scheme "None", a 192-bit key
- * is generated, extended to 256-bits by the Coding Scheme,
- * and then writtten for 3/4 Coding Scheme.
- *
- * @note This function does not burn the new values, caller should
- * call esp_efuse_burn_new_values() when ready to do this.
- *
- * @param blk_wdata0_reg Address of the first data write register
- * in the block
- */
-void esp_efuse_write_random_key(uint32_t blk_wdata0_reg);
-
-/* @brief Return secure_version from efuse field.
- * @return Secure version from efuse field
- */
-uint32_t esp_efuse_read_secure_version();
-
-/* @brief Check secure_version from app and secure_version and from efuse field.
- *
- * @param secure_version Secure version from app.
- * @return
- *          - True: If version of app is equal or more then secure_version from efuse.
- */
-bool esp_efuse_check_secure_version(uint32_t secure_version);
-
-/* @brief Write efuse field by secure_version value.
- *
- * Update the secure_version value is available if the coding scheme is None.
- * Note: Do not use this function in your applications. This function is called as part of the other API.
- *
- * @param[in] secure_version Secure version from app.
- * @return
- *          - ESP_OK: Successful.
- *          - ESP_FAIL: secure version of app cannot be set to efuse field.
- *          - ESP_ERR_NOT_SUPPORTED: Anti rollback is not supported with the 3/4 and Repeat coding scheme.
- */
-esp_err_t esp_efuse_update_secure_version(uint32_t secure_version);
-
-/* @brief Initializes variables: offset and size to simulate the work of an eFuse.
- *
- * Note: To simulate the work of an eFuse need to set CONFIG_EFUSE_SECURE_VERSION_EMULATE option
- * and to add in the partition.csv file a line `efuse_em, data, efuse,   ,   0x2000,`.
- *
- * @param[in] offset The starting address of the partition where the eFuse data will be located.
- * @param[in] size The size of the partition.
- */
-void esp_efuse_init(uint32_t offset, uint32_t size);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _ESP_EFUSE_MANAGER_H_
diff --git a/tools/sdk/include/efuse/esp_efuse_table.h b/tools/sdk/include/efuse/esp_efuse_table.h
deleted file mode 100644
index a0137c012f3..00000000000
--- a/tools/sdk/include/efuse/esp_efuse_table.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at",
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-// md5_digest_table 2e23344575b3d07f01ecb695294e9770
-// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
-// If you want to change some fields, you need to change esp_efuse_table.csv file
-// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
-// To show efuse_table run the command 'show_efuse_table'.
-
-
-extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY_CRC[];
-extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_CRC[];
-extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[];
-extern const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_VER[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_FLASH_KEY[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_CONFIG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_JTAG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_APP_CPU[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_BT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_LOW[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_HIGH[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_HIGH[];
-extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/tools/sdk/include/esp-face/cat_face_3.h b/tools/sdk/include/esp-face/cat_face_3.h
deleted file mode 100644
index 42d6fa85821..00000000000
--- a/tools/sdk/include/esp-face/cat_face_3.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * ESPRESSIF MIT License
- *
- * Copyright (c) 2018 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
- *
- * Permission is hereby granted for use on ESPRESSIF SYSTEMS products only, in which case,
- * it is free of charge, to any person_body obtaining a copy of this software and associated
- * documentation files (the "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
- * to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all copies or
- * substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-#include "dl_lib_matrix3d.h"
-#include "dl_lib_matrix3dq.h"
-#include "freertos/FreeRTOS.h"
-#include "detection.h"
-
-    extern detection_model_t cat_face_3_model;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-face/detection.h b/tools/sdk/include/esp-face/detection.h
deleted file mode 100644
index 0bba4f49b6f..00000000000
--- a/tools/sdk/include/esp-face/detection.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
-  * ESPRESSIF MIT License
-  *
-  * Copyright (c) 2018 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
-  *
-  * Permission is hereby granted for use on ESPRESSIF SYSTEMS products only, in which case,
-  * it is free of charge, to any person obtaining a copy of this software and associated
-  * documentation files (the "Software"), to deal in the Software without restriction, including
-  * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
-  * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
-  * to do so, subject to the following conditions:
-  *
-  * The above copyright notice and this permission notice shall be included in all copies or
-  * substantial portions of the Software.
-  *
-  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
-#pragma once
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-#include "dl_lib_matrix3d.h"
-#include "dl_lib_matrix3dq.h"
-#include "freertos/FreeRTOS.h"
-
-    typedef enum
-    {
-        Anchor_Point, /*<! Anchor point detection model*/
-        Anchor_Box    /*<! Anchor box detection model */
-    } detection_model_type_t;
-
-    typedef struct
-    {
-        int **anchors_shape; /*<! Anchor shape of this stage */
-        int stride;          /*<! Zoom in stride of this stage */
-        int boundary;        /*<! Detection image low-limit of this stage */
-        int project_offset;  /*<! Project offset of this stage */
-    } detection_stage_config_t;
-
-    typedef struct
-    {
-        dl_matrix3dq_t *score;           /*<! score feature map of this stage*/
-        dl_matrix3dq_t *box_offset;      /*<! box_offset feature map of this stage*/
-        dl_matrix3dq_t *landmark_offset; /*<! landmark_offset feature map of this stage */
-    } detection_stage_result_t;
-
-    typedef struct
-    {
-        int resized_height;    /*<! The height after resized */
-        int resized_width;     /*<! The width after resized */
-        fptp_t y_resize_scale; /*<! resized_height / input_height */
-        fptp_t x_resize_scale; /*<! resized_width / input_width */
-        qtp_t score_threshold; /*<! Score threshold of detection model */
-        fptp_t nms_threshold;  /*<! NMS threshold of detection model */
-        bool with_landmark;    /*<! Whether detection with landmark, true: with, false: without */
-        bool free_image;       /*<! Whether free the resized image */
-        int enabled_top_k;     /*<! The number of enabled stages */
-    } detection_model_config_t;
-
-    typedef struct
-    {
-        detection_stage_config_t *stage_config;                                                                      /*<! Configuration of each stage */
-        int stage_number;                                                                                            /*<! The number of stages */
-        detection_model_type_t model_type;                                                                           /*<! The type of detection model */
-        detection_model_config_t model_config;                                                                       /*<! Configuration of detection model */
-        detection_stage_result_t *(*op)(dl_matrix3dq_t *, detection_model_config_t *);                               /*<! The function of detection inference */
-        void *(*get_boxes)(detection_stage_result_t *, detection_model_config_t *, detection_stage_config_t *, int); /*<! The function of how to get real boxes */
-    } detection_model_t;
-
-    /**
-     * @brief free 'detection_stage_result_t' type value
-     * 
-     * @param value A 'detection_stage_result_t' type value
-     */
-    void free_detection_stage_result(detection_stage_result_t value);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-face/dl_lib_matrix3d.h b/tools/sdk/include/esp-face/dl_lib_matrix3d.h
deleted file mode 100644
index fa53bcac172..00000000000
--- a/tools/sdk/include/esp-face/dl_lib_matrix3d.h
+++ /dev/null
@@ -1,819 +0,0 @@
-#pragma once
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-#include <assert.h>
-
-#if CONFIG_SPIRAM_SUPPORT || CONFIG_ESP32_SPIRAM_SUPPORT
-#include "freertos/FreeRTOS.h"
-#define DL_SPIRAM_SUPPORT 1
-#else
-#define DL_SPIRAM_SUPPORT 0
-#endif
-
-
-#ifndef max
-#define max(x, y) (((x) < (y)) ? (y) : (x))
-#endif
-
-#ifndef min
-#define min(x, y) (((x) < (y)) ? (x) : (y))
-#endif
-
-typedef float fptp_t;
-typedef uint8_t uc_t;
-
-typedef enum
-{
-    DL_SUCCESS = 0,
-    DL_FAIL = 1,
-} dl_error_type;
-
-typedef enum
-{
-    PADDING_VALID = 0,                   /*!< Valid padding */
-    PADDING_SAME = 1,                    /*!< Same padding, from right to left, free input */
-    PADDING_SAME_DONT_FREE_INPUT = 2,    /*!< Same padding, from right to left, do not free input */
-    PADDING_SAME_MXNET = 3,              /*!< Same padding, from left to right */
-} dl_padding_type;
-
-typedef enum
-{
-    DL_POOLING_MAX = 0,        /*!< Max pooling */
-    DL_POOLING_AVG = 1,        /*!< Average pooling */
-} dl_pooling_type; 
-/*
- * Matrix for 3d
- * @Warning: the sequence of variables is fixed, cannot be modified, otherwise there will be errors in esp_dsp_dot_float
- */
-typedef struct
-{
-    int w;        /*!< Width */
-    int h;        /*!< Height */
-    int c;        /*!< Channel */
-    int n;        /*!< Number of filter, input and output must be 1 */
-    int stride;   /*!< Step between lines */
-    fptp_t *item; /*!< Data */
-} dl_matrix3d_t;
-
-typedef struct
-{
-    int w;      /*!< Width */
-    int h;      /*!< Height */
-    int c;      /*!< Channel */
-    int n;      /*!< Number of filter, input and output must be 1 */
-    int stride; /*!< Step between lines */
-    uc_t *item; /*!< Data */
-} dl_matrix3du_t;
-
-typedef enum
-{
-    UPSAMPLE_NEAREST_NEIGHBOR = 0, /*!< Use nearest neighbor interpolation as the upsample method*/
-    UPSAMPLE_BILINEAR = 1,        /*!< Use nearest bilinear interpolation as the upsample method*/
-} dl_upsample_type;
-
-typedef struct
-{
-    int stride_x;                    /*!< Strides of width */
-    int stride_y;                    /*!< Strides of height */
-    dl_padding_type padding;         /*!< Padding type */
-} dl_matrix3d_mobilenet_config_t;
-
-/*
- * @brief Allocate a zero-initialized space. Must use 'dl_lib_free' to free the memory.
- *
- * @param cnt  Count of units.
- * @param size Size of unit.
- * @param align Align of memory. If not required, set 0.
- * @return Pointer of allocated memory. Null for failed.
- */
-static void *dl_lib_calloc(int cnt, int size, int align)
-{
-    int total_size = cnt * size + align + sizeof(void *);
-    void *res = malloc(total_size);
-    if (NULL == res)
-    {
-#if DL_SPIRAM_SUPPORT
-        res = heap_caps_malloc(total_size, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM);
-    }
-    if (NULL == res)
-    {
-        printf("Item psram alloc failed. Size: %d x %d\n", cnt, size);
-#else
-        printf("Item alloc failed. Size: %d x %d, SPIRAM_FLAG: %d\n", cnt, size, DL_SPIRAM_SUPPORT);
-#endif
-        return NULL;
-    }
-    bzero(res, total_size);
-    void **data = (void **)res + 1;
-    void **aligned;
-    if (align)
-        aligned = (void **)(((size_t)data + (align - 1)) & -align);
-    else
-        aligned = data;
-
-    aligned[-1] = res;
-    return (void *)aligned;
-}
-
-/**
- * @brief Free the memory space allocated by 'dl_lib_calloc'
- * 
- */
-static inline void dl_lib_free(void *d)
-{
-    if (NULL == d)
-        return;
-
-    free(((void **)d)[-1]);
-}
-
-/*
- * @brief Allocate a 3D matrix with float items, the access sequence is NHWC
- *
- * @param n     Number of matrix3d, for filters it is out channels, for others it is 1
- * @param w     Width of matrix3d
- * @param h     Height of matrix3d
- * @param c     Channel of matrix3d
- * @return      3d matrix
- */
-static inline dl_matrix3d_t *dl_matrix3d_alloc(int n, int w, int h, int c)
-{
-    dl_matrix3d_t *r = (dl_matrix3d_t *)dl_lib_calloc(1, sizeof(dl_matrix3d_t), 0);
-    if (NULL == r)
-    {
-        printf("internal r failed.\n");
-        return NULL;
-    }
-    fptp_t *items = (fptp_t *)dl_lib_calloc(n * w * h * c, sizeof(fptp_t), 0);
-    if (NULL == items)
-    {
-        printf("matrix3d item alloc failed.\n");
-        dl_lib_free(r);
-        return NULL;
-    }
-
-    r->w = w;
-    r->h = h;
-    r->c = c;
-    r->n = n;
-    r->stride = w * c;
-    r->item = items;
-
-    return r;
-}
-
-/*
- * @brief Allocate a 3D matrix with 8-bits items, the access sequence is NHWC
- *
- * @param n     Number of matrix3d, for filters it is out channels, for others it is 1
- * @param w     Width of matrix3d
- * @param h     Height of matrix3d
- * @param c     Channel of matrix3d
- * @return      3d matrix
- */
-static inline dl_matrix3du_t *dl_matrix3du_alloc(int n, int w, int h, int c)
-{
-    dl_matrix3du_t *r = (dl_matrix3du_t *)dl_lib_calloc(1, sizeof(dl_matrix3du_t), 0);
-    if (NULL == r)
-    {
-        printf("internal r failed.\n");
-        return NULL;
-    }
-    uc_t *items = (uc_t *)dl_lib_calloc(n * w * h * c, sizeof(uc_t), 0);
-    if (NULL == items)
-    {
-        printf("matrix3du item alloc failed.\n");
-        dl_lib_free(r);
-        return NULL;
-    }
-
-    r->w = w;
-    r->h = h;
-    r->c = c;
-    r->n = n;
-    r->stride = w * c;
-    r->item = items;
-
-    return r;
-}
-
-/*
- * @brief Free a matrix3d
- *
- * @param m matrix3d with float items
- */
-static inline void dl_matrix3d_free(dl_matrix3d_t *m)
-{
-    if (NULL == m)
-        return;
-    if (NULL == m->item)
-    {
-        dl_lib_free(m);
-        return;
-    }
-    dl_lib_free(m->item);
-    dl_lib_free(m);
-}
-
-/*
- * @brief Free a matrix3d
- *
- * @param m matrix3d with 8-bits items
- */
-static inline void dl_matrix3du_free(dl_matrix3du_t *m)
-{
-    if (NULL == m)
-        return;
-    if (NULL == m->item)
-    {
-        dl_lib_free(m);
-        return;
-    }
-    dl_lib_free(m->item);
-    dl_lib_free(m);
-}
-
-
-/*
- * @brief Dot product with a vector and matrix
- *
- * @param out   Space to put the result
- * @param in    input vector
- * @param f     filter matrix
- */
-void dl_matrix3dff_dot_product(dl_matrix3d_t *out, dl_matrix3d_t *in, dl_matrix3d_t *f);
-
-/**
- * @brief Do a softmax operation on a matrix3d
- *
- * @param in        Input matrix3d
- */
-void dl_matrix3d_softmax(dl_matrix3d_t *m);
-
-/**
- * @brief Copy a range of float items from an existing matrix to a preallocated matrix
- *
- * @param dst   The destination slice matrix
- * @param src   The source matrix to slice
- * @param x     X-offset of the origin of the returned matrix within the sliced matrix
- * @param y     Y-offset of the origin of the returned matrix within the sliced matrix
- * @param w     Width of the resulting matrix
- * @param h     Height of the resulting matrix
- */
-void dl_matrix3d_slice_copy(dl_matrix3d_t *dst,
-                            dl_matrix3d_t *src,
-                            int x,
-                            int y,
-                            int w,
-                            int h);
-
-/**
- * @brief Copy a range of 8-bits items from an existing matrix to a preallocated matrix
- *
- * @param dst   The destination slice matrix
- * @param src   The source matrix to slice
- * @param x     X-offset of the origin of the returned matrix within the sliced matrix
- * @param y     Y-offset of the origin of the returned matrix within the sliced matrix
- * @param w     Width of the resulting matrix
- * @param h     Height of the resulting matrix
- */
-void dl_matrix3du_slice_copy(dl_matrix3du_t *dst,
-                             dl_matrix3du_t *src,
-                             int x,
-                             int y,
-                             int w,
-                             int h);
-
-/**
- * @brief Transform a sliced matrix block from nhwc to nchw, the block needs to be memory continous.
- *
- * @param out  The destination sliced matrix in nchw
- * @param in   The source sliced matrix in nhwc
- */
-void dl_matrix3d_sliced_transform_nchw(dl_matrix3d_t *out,
-                                       dl_matrix3d_t *in);
-
-/**
- * @brief Do a general CNN layer pass, dimension is (number, width, height, channel)
- *
- * @param in               Input matrix3d
- * @param filter           Weights of the neurons
- * @param bias             Bias for the CNN layer
- * @param stride_x         The step length of the convolution window in x(width) direction
- * @param stride_y         The step length of the convolution window in y(height) direction
- * @param padding          One of VALID or SAME
- * @param mode             Do convolution using C implement or xtensa implement, 0 or 1, with respect
- *                         If ESP_PLATFORM is not defined, this value is not used. Default is 0
- * @return dl_matrix3d_t*  The result of CNN layer
- */
-dl_matrix3d_t *dl_matrix3d_conv(dl_matrix3d_t *in,
-                                dl_matrix3d_t *filter,
-                                dl_matrix3d_t *bias,
-                                int stride_x,
-                                int stride_y,
-                                int padding,
-                                int mode);
-
-/**
- * @brief Do a global average pooling layer pass, dimension is (number, width, height, channel)
- *
- * @param in             Input matrix3d
- *
- * @return               The result of global average pooling layer
- */
-dl_matrix3d_t *dl_matrix3d_global_pool(dl_matrix3d_t *in);
-
-/**
- * @brief Calculate pooling layer of a feature map
- *
- * @param in               Input matrix, size (1, w, h, c)
- * @param f_w              Window width
- * @param f_h              Window height 
- * @param stride_x         Stride in horizontal direction
- * @param stride_y         Stride in vertical direction
- * @param padding          Padding type: PADDING_VALID and PADDING_SAME
- * @param pooling_type     Pooling type: DL_POOLING_MAX and POOLING_AVG
- * @return dl_matrix3d_t*  Resulting matrix, size (1, w', h', c)
- */
-dl_matrix3d_t *dl_matrix3d_pooling(dl_matrix3d_t *in,
-                                   int f_w,
-                                   int f_h,
-                                   int stride_x,
-                                   int stride_y,
-                                   dl_padding_type padding,
-                                   dl_pooling_type pooling_type);
-/**
- * @brief Do a batch normalization operation, update the input matrix3d: input = input * scale + offset
- *
- * @param m              Input matrix3d
- * @param scale          scale matrix3d,  scale = gamma/((moving_variance+sigma)^(1/2))
- * @param Offset         Offset matrix3d, offset = beta-(moving_mean*gamma/((moving_variance+sigma)^(1/2)))
- */
-void dl_matrix3d_batch_normalize(dl_matrix3d_t *m,
-                                 dl_matrix3d_t *scale,
-                                 dl_matrix3d_t *offset);
-
-/**
- * @brief Add a pair of matrix3d item-by-item: res=in_1+in_2
- *
- * @param in_1             First Floating point input matrix3d
- * @param in_2             Second Floating point input matrix3d
- *
- * @return dl_matrix3d_t*  Added data
- */
-dl_matrix3d_t *dl_matrix3d_add(dl_matrix3d_t *in_1, dl_matrix3d_t *in_2);
-
-/**
- * @brief Concatenate the channels of two matrix3ds into a new matrix3d
- *
- * @param in_1             First Floating point input matrix3d
- * @param in_2             Second Floating point input matrix3d
- *
- * @return dl_matrix3d_t*  A newly allocated matrix3d with as avlues in_1|in_2
- */
-dl_matrix3d_t *dl_matrix3d_concat(dl_matrix3d_t *in_1, dl_matrix3d_t *in_2);
-
-/**
- * @brief Concatenate the channels of four matrix3ds into a new matrix3d
- *
- * @param in_1           First Floating point input matrix3d
- * @param in_2           Second Floating point input matrix3d
- * @param in_3           Third Floating point input matrix3d
- * @param in_4           Fourth Floating point input matrix3d
- *
- * @return               A newly allocated matrix3d with as avlues in_1|in_2|in_3|in_4
- */
-dl_matrix3d_t *dl_matrix3d_concat_4(dl_matrix3d_t *in_1,
-                                    dl_matrix3d_t *in_2,
-                                    dl_matrix3d_t *in_3,
-                                    dl_matrix3d_t *in_4);
-
-/**
- * @brief Concatenate the channels of eight matrix3ds into a new matrix3d
- *
- * @param in_1           First Floating point input matrix3d
- * @param in_2           Second Floating point input matrix3d
- * @param in_3           Third Floating point input matrix3d
- * @param in_4           Fourth Floating point input matrix3d
- * @param in_5           Fifth Floating point input matrix3d
- * @param in_6           Sixth Floating point input matrix3d
- * @param in_7           Seventh Floating point input matrix3d
- * @param in_8           eighth Floating point input matrix3d
- *
- * @return               A newly allocated matrix3d with as avlues in_1|in_2|in_3|in_4|in_5|in_6|in_7|in_8
- */
-dl_matrix3d_t *dl_matrix3d_concat_8(dl_matrix3d_t *in_1,
-                                    dl_matrix3d_t *in_2,
-                                    dl_matrix3d_t *in_3,
-                                    dl_matrix3d_t *in_4,
-                                    dl_matrix3d_t *in_5,
-                                    dl_matrix3d_t *in_6,
-                                    dl_matrix3d_t *in_7,
-                                    dl_matrix3d_t *in_8);
-
-/**
- * @brief Do a mobilefacenet block forward, dimension is (number, width, height, channel)
- *
- * @param in                    Input matrix3d
- * @param pw                    Weights of the pointwise conv layer
- * @param pw_bn_scale           The scale params of the batch_normalize layer after the pointwise conv layer
- * @param pw_bn_offset          The offset params of the batch_normalize layer after the pointwise conv layer
- * @param dw                    Weights of the depthwise conv layer
- * @param dw_bn_scale           The scale params of the batch_normalize layer after the depthwise conv layer
- * @param dw_bn_offset          The offset params of the batch_normalize layer after the depthwise conv layer
- * @param pw_linear             Weights of the pointwise linear conv layer
- * @param pw_linear_bn_scale    The scale params of the batch_normalize layer after the pointwise linear conv layer
- * @param pw_linear_bn_offset   The offset params of the batch_normalize layer after the pointwise linear conv layer
- * @param stride_x              The step length of the convolution window in x(width) direction
- * @param stride_y              The step length of the convolution window in y(height) direction
- * @param padding               One of VALID or SAME
- * @param mode                  Do convolution using C implement or xtensa implement, 0 or 1, with respect
- *                              If ESP_PLATFORM is not defined, this value is not used. Default is 0
- * @return                      The result of a mobilefacenet block
- */
-dl_matrix3d_t *dl_matrix3d_mobilefaceblock(dl_matrix3d_t *in,
-                                           dl_matrix3d_t *pw,
-                                           dl_matrix3d_t *pw_bn_scale,
-                                           dl_matrix3d_t *pw_bn_offset,
-                                           dl_matrix3d_t *dw,
-                                           dl_matrix3d_t *dw_bn_scale,
-                                           dl_matrix3d_t *dw_bn_offset,
-                                           dl_matrix3d_t *pw_linear,
-                                           dl_matrix3d_t *pw_linear_bn_scale,
-                                           dl_matrix3d_t *pw_linear_bn_offset,
-                                           int stride_x,
-                                           int stride_y,
-                                           int padding,
-                                           int mode,
-                                           int shortcut);
-
-/**
- * @brief Do a mobilefacenet block forward with 1x1 split conv, dimension is (number, width, height, channel)
- *
- * @param in                    Input matrix3d
- * @param pw_1                  Weights of the pointwise conv layer 1
- * @param pw_2                  Weights of the pointwise conv layer 2
- * @param pw_bn_scale           The scale params of the batch_normalize layer after the pointwise conv layer
- * @param pw_bn_offset          The offset params of the batch_normalize layer after the pointwise conv layer
- * @param dw                    Weights of the depthwise conv layer
- * @param dw_bn_scale           The scale params of the batch_normalize layer after the depthwise conv layer
- * @param dw_bn_offset          The offset params of the batch_normalize layer after the depthwise conv layer
- * @param pw_linear_1           Weights of the pointwise linear conv layer 1
- * @param pw_linear_2           Weights of the pointwise linear conv layer 2
- * @param pw_linear_bn_scale    The scale params of the batch_normalize layer after the pointwise linear conv layer
- * @param pw_linear_bn_offset   The offset params of the batch_normalize layer after the pointwise linear conv layer
- * @param stride_x              The step length of the convolution window in x(width) direction
- * @param stride_y              The step length of the convolution window in y(height) direction
- * @param padding               One of VALID or SAME
- * @param mode                  Do convolution using C implement or xtensa implement, 0 or 1, with respect
- *                              If ESP_PLATFORM is not defined, this value is not used. Default is 0
- * @return                      The result of a mobilefacenet block
- */
-dl_matrix3d_t *dl_matrix3d_mobilefaceblock_split(dl_matrix3d_t *in,
-                                                 dl_matrix3d_t *pw_1,
-                                                 dl_matrix3d_t *pw_2,
-                                                 dl_matrix3d_t *pw_bn_scale,
-                                                 dl_matrix3d_t *pw_bn_offset,
-                                                 dl_matrix3d_t *dw,
-                                                 dl_matrix3d_t *dw_bn_scale,
-                                                 dl_matrix3d_t *dw_bn_offset,
-                                                 dl_matrix3d_t *pw_linear_1,
-                                                 dl_matrix3d_t *pw_linear_2,
-                                                 dl_matrix3d_t *pw_linear_bn_scale,
-                                                 dl_matrix3d_t *pw_linear_bn_offset,
-                                                 int stride_x,
-                                                 int stride_y,
-                                                 int padding,
-                                                 int mode,
-                                                 int shortcut);
-
-/**
- * @brief           Initialize the matrix3d feature map to bias
- * 
- * @param out       The matrix3d feature map needs to be initialized
- * @param bias      The bias of a convlotion operation
- */
-void dl_matrix3d_init_bias(dl_matrix3d_t *out, dl_matrix3d_t *bias);
-
-/**
- * @brief  Do a elementwise multiplication of two matrix3ds
- * 
- * @param out  Preallocated matrix3d, size (n, w, h, c)
- * @param in1  Input matrix 1, size (n, w, h, c)
- * @param in2  Input matrix 2, size (n, w, h, c)
- */
-void dl_matrix3d_multiply(dl_matrix3d_t *out, dl_matrix3d_t *in1, dl_matrix3d_t *in2);
-
-//
-// Activation
-//
-
-/**
- * @brief Do a standard relu operation, update the input matrix3d
- *
- * @param m        Floating point input matrix3d
- */
-void dl_matrix3d_relu(dl_matrix3d_t *m);
-
-/**
- * @brief Do a relu (Rectifier Linear Unit) operation, update the input matrix3d
- *
- * @param in        Floating point input matrix3d
- * @param clip      If value is higher than this, it will be clipped to this value
- */
-void dl_matrix3d_relu_clip(dl_matrix3d_t *m, fptp_t clip);
-
-/**
- * @brief Do a Prelu (Rectifier Linear Unit) operation, update the input matrix3d
- *
- * @param in        Floating point input matrix3d
- * @param alpha     If value is less than zero, it will be updated by multiplying this factor
- */
-void dl_matrix3d_p_relu(dl_matrix3d_t *in, dl_matrix3d_t *alpha);
-
-/**
- * @brief Do a leaky relu (Rectifier Linear Unit) operation, update the input matrix3d
- *
- * @param in        Floating point input matrix3d
- * @param alpha     If value is less than zero, it will be updated by multiplying this factor
- */
-void dl_matrix3d_leaky_relu(dl_matrix3d_t *m, fptp_t alpha);
-
-//
-// Conv 1x1
-//
-/**
- * @brief Do 1x1 convolution with a matrix3d
- * 
- * @param out        Preallocated matrix3d, size (1, w, h, n)
- * @param in         Input matrix, size (1, w, h, c)
- * @param filter     1x1 filter, size (n, 1, 1, c)
- */
-void dl_matrix3dff_conv_1x1(dl_matrix3d_t *out,
-                            dl_matrix3d_t *in,
-                            dl_matrix3d_t *filter);
-
-/**
- * @brief Do 1x1 convolution with a matrix3d, with bias adding
- * 
- * @param out        Preallocated matrix3d, size (1, w, h, n)
- * @param in         Input matrix, size (1, w, h, c)
- * @param filter     1x1 filter, size (n, 1, 1, c)
- * @param bias       Bias, size (1, 1, 1, n)
- */
-void dl_matrix3dff_conv_1x1_with_bias(dl_matrix3d_t *out,
-                                      dl_matrix3d_t *in,
-                                      dl_matrix3d_t *filter,
-                                      dl_matrix3d_t *bias);
-
-/**
- * @brief Do 1x1 convolution with an 8-bit fixed point matrix
- * 
- * @param out        Preallocated matrix3d, size (1, w, h, n)
- * @param in         Input matrix, size (1, w, h, c)
- * @param filter     1x1 filter, size (n, 1, 1, c)
- */
-void dl_matrix3duf_conv_1x1(dl_matrix3d_t *out,
-                            dl_matrix3du_t *in,
-                            dl_matrix3d_t *filter);
-
-/**
- * @brief Do 1x1 convolution with an 8-bit fixed point matrix, with bias adding
- * 
- * @param out        Preallocated matrix3d, size (1, w, h, n)  
- * @param in         Input matrix, size (1, w, h, c)
- * @param filter     1x1 filter, size (n, 1, 1, c)
- * @param bias       Bias, size (1, 1, 1, n)
- */
-void dl_matrix3duf_conv_1x1_with_bias(dl_matrix3d_t *out,
-                                      dl_matrix3du_t *in,
-                                      dl_matrix3d_t *filter,
-                                      dl_matrix3d_t *bias);
-
-//
-// Conv 3x3
-//
-
-/**
- * @brief Do 3x3 convolution with a matrix3d, without padding
- * 
- * @param out        Preallocated matrix3d, size (1, w, h, n)
- * @param in         Input matrix, size (1, w, h, c)
- * @param f          3x3 filter, size (n, 3, 3, c)
- * @param step_x     Stride of width
- * @param step_y     Stride of height
- */
-void dl_matrix3dff_conv_3x3_op(dl_matrix3d_t *out,
-                               dl_matrix3d_t *in,
-                               dl_matrix3d_t *f,
-                               int step_x,
-                               int step_y);
-
-/**
- * @brief Do 3x3 convolution with a matrix3d, with bias adding
- * 
- * @param input             Input matrix, size (1, w, h, c)
- * @param filter            3x3 filter, size (n, 3, 3, c)
- * @param bias              Bias, size (1, 1, 1, n)
- * @param stride_x          Stride of width
- * @param stride_y          Stride of height
- * @param padding           Padding type
- * @return dl_matrix3d_t*   Resulting matrix3d
- */
-dl_matrix3d_t *dl_matrix3dff_conv_3x3(dl_matrix3d_t *in,
-                                      dl_matrix3d_t *filter,
-                                      dl_matrix3d_t *bias,
-                                      int stride_x,
-                                      int stride_y,
-                                      dl_padding_type padding);
-
-//
-// Conv Common
-//
-
-/**
- * @brief Do a general convolution layer pass with an 8-bit fixed point matrix, size is (number, width, height, channel)
- * 
- * @param in                Input image
- * @param filter            Weights of the neurons
- * @param bias              Bias for the CNN layer
- * @param stride_x          The step length of the convolution window in x(width) direction
- * @param stride_y          The step length of the convolution window in y(height) direction
- * @param padding           Padding type
- * @return dl_matrix3d_t*   Resulting matrix3d
- */
-dl_matrix3d_t *dl_matrix3duf_conv_common(dl_matrix3du_t *in,
-                                         dl_matrix3d_t *filter,
-                                         dl_matrix3d_t *bias,
-                                         int stride_x,
-                                         int stride_y,
-                                         dl_padding_type padding);
-
-/**
- * @brief Do a general convolution layer pass, size is (number, width, height, channel)
- * 
- * @param in                Input image
- * @param filter            Weights of the neurons
- * @param bias              Bias for the CNN layer
- * @param stride_x          The step length of the convolution window in x(width) direction
- * @param stride_y          The step length of the convolution window in y(height) direction
- * @param padding           Padding type
- * @return dl_matrix3d_t*   Resulting matrix3d
- */
-dl_matrix3d_t *dl_matrix3dff_conv_common(dl_matrix3d_t *in,
-                                         dl_matrix3d_t *filter,
-                                         dl_matrix3d_t *bias,
-                                         int stride_x,
-                                         int stride_y,
-                                         dl_padding_type padding);
-
-//
-// Depthwise 3x3
-//
-
-/**
- * @brief Do 3x3 depthwise convolution with a float matrix3d
- * 
- * @param in                  Input matrix, size (1, w, h, c)
- * @param filter              3x3 filter, size (1, 3, 3, c)
- * @param stride_x            Stride of width
- * @param stride_y            Stride of height
- * @param padding             Padding type, 0: valid, 1: same
- * @return dl_matrix3d_t*     Resulting float matrix3d
- */
-dl_matrix3d_t *dl_matrix3dff_depthwise_conv_3x3(dl_matrix3d_t *in,
-                                                dl_matrix3d_t *filter,
-                                                int stride_x,
-                                                int stride_y,
-                                                int padding);
-
-/**
- * @brief Do 3x3 depthwise convolution with a 8-bit fixed point matrix
- * 
- * @param in                  Input matrix, size (1, w, h, c)
- * @param filter              3x3 filter, size (1, 3, 3, c)
- * @param stride_x            Stride of width
- * @param stride_y            Stride of height
- * @param padding             Padding type, 0: valid, 1: same
- * @return dl_matrix3d_t*     Resulting float matrix3d
- */
-dl_matrix3d_t *dl_matrix3duf_depthwise_conv_3x3(dl_matrix3du_t *in,
-                                                dl_matrix3d_t *filter,
-                                                int stride_x,
-                                                int stride_y,
-                                                int padding);
-
-/**
- * @brief Do 3x3 depthwise convolution with a float matrix3d, without padding
- * 
- * @param out                 Preallocated matrix3d, size (1, w, h, n)
- * @param in                  Input matrix, size (1, w, h, c)
- * @param f                   3x3 filter, size (1, 3, 3, c)
- * @param step_x              Stride of width
- * @param step_y              Stride of height
- */
-void dl_matrix3dff_depthwise_conv_3x3_op(dl_matrix3d_t *out,
-                                         dl_matrix3d_t *in,
-                                         dl_matrix3d_t *f,
-                                         int step_x,
-                                         int step_y);
-
-//
-// Depthwise Common
-//
-
-/**
- * @brief Do a depthwise CNN layer pass, dimension is (number, width, height, channel)
- *
- * @param in             Input matrix3d
- * @param filter         Weights of the neurons
- * @param stride_x       The step length of the convolution window in x(width) direction
- * @param stride_y       The step length of the convolution window in y(height) direction
- * @param padding        One of VALID or SAME
- * @param mode           Do convolution using C implement or xtensa implement, 0 or 1, with respect
- *                       If ESP_PLATFORM is not defined, this value is not used. Default is 0
- * @return               The result of depthwise CNN layer
- */
-dl_matrix3d_t *dl_matrix3dff_depthwise_conv_common(dl_matrix3d_t *in,
-                                                   dl_matrix3d_t *filter,
-                                                   int stride_x,
-                                                   int stride_y,
-                                                   dl_padding_type padding);
-
-//
-// FC
-//
-/**
- * @brief Do a general fully connected layer pass, dimension is (number, width, height, channel)
- *
- * @param in             Input matrix3d, size is (1, w, 1, 1)
- * @param filter         Weights of the neurons, size is (1, w, h, 1)
- * @param bias           Bias for the fc layer, size is (1, 1, 1, h)
- * @return               The result of fc layer, size is (1, 1, 1, h)
- */
-void dl_matrix3dff_fc(dl_matrix3d_t *out,
-                      dl_matrix3d_t *in,
-                      dl_matrix3d_t *filter);
-
-/**
- * @brief Do fully connected layer forward, with bias adding
- *
- * @param out       Preallocated resulting matrix, size (1, 1, 1, h)
- * @param in        Input matrix, size (1, 1, 1, w)
- * @param filter    Filter matrix, size (1, w, h, 1)
- * @param bias      Bias matrix, size (1, 1, 1, h)
- */
-void dl_matrix3dff_fc_with_bias(dl_matrix3d_t *out,
-                                dl_matrix3d_t *in,
-                                dl_matrix3d_t *filter,
-                                dl_matrix3d_t *bias);
-
-//
-// Mobilenet
-//
-
-/**
- * @brief Do a mobilenet block forward, dimension is (number, width, height, channel)
- *
- * @param in             Input matrix3d
- * @param filter         Weights of the neurons
- * @param stride_x       The step length of the convolution window in x(width) direction
- * @param stride_y       The step length of the convolution window in y(height) direction
- * @param padding        One of VALID or SAME
- * @param mode           Do convolution using C implement or xtensa implement, 0 or 1, with respect
- *                       If ESP_PLATFORM is not defined, this value is not used. Default is 0
- * @return               The result of depthwise CNN layer
- */
-dl_matrix3d_t *dl_matrix3dff_mobilenet(dl_matrix3d_t *in,
-                                       dl_matrix3d_t *dilate_filter,
-                                       dl_matrix3d_t *dilate_prelu,
-                                       dl_matrix3d_t *depthwise_filter,
-                                       dl_matrix3d_t *depthwise_prelu,
-                                       dl_matrix3d_t *compress_filter,
-                                       dl_matrix3d_t *bias,
-                                       dl_matrix3d_mobilenet_config_t config);
-
-/**
- * @brief Do a mobilenet block forward, dimension is (number, width, height, channel)
- *
- * @param in             Input matrix3du
- * @param filter         Weights of the neurons
- * @param stride_x       The step length of the convolution window in x(width) direction
- * @param stride_y       The step length of the convolution window in y(height) direction
- * @param padding        One of VALID or SAME
- * @param mode           Do convolution using C implement or xtensa implement, 0 or 1, with respect
- *                       If ESP_PLATFORM is not defined, this value is not used. Default is 0
- * @return               The result of depthwise CNN layer
- */
-dl_matrix3d_t *dl_matrix3duf_mobilenet(dl_matrix3du_t *in,
-                                       dl_matrix3d_t *dilate_filter,
-                                       dl_matrix3d_t *dilate_prelu,
-                                       dl_matrix3d_t *depthwise_filter,
-                                       dl_matrix3d_t *depthwise_prelu,
-                                       dl_matrix3d_t *compress_filter,
-                                       dl_matrix3d_t *bias,
-                                       dl_matrix3d_mobilenet_config_t config);
diff --git a/tools/sdk/include/esp-face/dl_lib_matrix3dq.h b/tools/sdk/include/esp-face/dl_lib_matrix3dq.h
deleted file mode 100644
index 0d982b4a0e0..00000000000
--- a/tools/sdk/include/esp-face/dl_lib_matrix3dq.h
+++ /dev/null
@@ -1,1441 +0,0 @@
-#pragma once
-#include "dl_lib_matrix3d.h"
-
-typedef int16_t qtp_t;
-
-/**
- * Matrix for input, filter, and output
- * @Warning: the sequence of variables is fixed, cannot be modified, otherwise there will be errors in 
- * some handwrite xtensa instruction functions
- */
-typedef struct
-{
-    /******* fix start *******/
-    int w;        /*!< Width */
-    int h;        /*!< Height */
-    int c;        /*!< Channel */
-    int n;        /*!< Number of filter, input and output must be 1 */
-    int stride;   /*!< Step between lines */
-    int exponent; /*!< Exponent for quantization */
-    qtp_t *item;  /*!< Data */
-    /******* fix end *******/
-} dl_matrix3dq_t;
-
-#ifndef DL_QTP_SHIFT
-#define DL_QTP_SHIFT 15
-#define DL_ITMQ(m, x, y) m->itemq[(y) + (x)*m->stride]
-#define DL_QTP_RANGE ((1 << DL_QTP_SHIFT) - 1)
-#define DL_QTP_MAX 32767
-#define DL_QTP_MIN -32768
-
-#define DL_QTP_EXP_NA 255 //non-applicable exponent because matrix is null
-
-#define DL_SHIFT_AUTO 32
-#endif
-
-/**
- * Implementation of matrix relative operations
- */
-typedef enum
-{
-    DL_C_IMPL = 0,     /*!< ANSI C */
-    DL_XTENSA_IMPL = 1 /*!< Handwrite xtensa instruction */
-} dl_conv_mode;
-
-/**
- * Configuration of mobilenet operation
- */
-typedef struct
-{
-    int stride_x;            /*!< Strides of width */
-    int stride_y;            /*!< Strides of height */
-    dl_padding_type padding; /*!< Padding type */
-    dl_conv_mode mode;       /*!< Implementation mode */
-    int dilate_exponent;     /*!< Exponent of dilation filter */
-    int depthwise_exponent;  /*!< Exponent of depthwise filter */
-    int compress_exponent;   /*!< Exponent of compress filter */
-} dl_matrix3dq_mobilenet_config_t;
-
-typedef struct
-{
-    int stride_x;            /*!< Strides of width */
-    int stride_y;            /*!< Strides of height */
-    dl_padding_type padding; /*!< Padding type */
-    dl_conv_mode mode;       /*!< Implementation mode */
-    int dw1_exponent;        /*!< Exponent of dw1 filter */
-    int pw1_exponent;        /*!< Exponent of pw1 filter */
-    int dw2_exponent;        /*!< Exponent of dw2 filter */
-    int pw2_exponent;        /*!< Exponent of pw2 filter */
-    int shortcut;           /*!< Shortcut connection flag */
-    int save_input;         /*!< Input save flag */
-} dl_matrix3dq_blazeblock_config_t;
-
-//
-// Utility
-//
-
-/*
- * @brief Allocate a 3d quantised matrix
- *
- * @param n Number of filters, for input and output, should be 1
- * @param w Width of matrix
- * @param h Height of matrix
- * @param c Channel of matrix
- * @param e Exponent of matrix data
- * @return 3d quantized matrix
- */
-static inline dl_matrix3dq_t *dl_matrix3dq_alloc(int n, int w, int h, int c, int e)
-{
-    dl_matrix3dq_t *r = (dl_matrix3dq_t *)dl_lib_calloc(1, sizeof(dl_matrix3dq_t), 0);
-    if (NULL == r)
-    {
-        printf("dl_matrix3dq alloc failed.\n");
-        return NULL;
-    }
-
-    qtp_t *items = (qtp_t *)dl_lib_calloc(n * w * h * c, sizeof(qtp_t), 16);
-    if (NULL == items)
-    {
-        printf("matrix3dq item alloc failed.\n");
-        dl_lib_free(r);
-        return NULL;
-    }
-
-    r->w = w;
-    r->h = h;
-    r->c = c;
-    r->n = n;
-    r->exponent = e;
-    r->stride = w * c;
-    r->item = items;
-
-    return r;
-}
-
-/*
- * @brief Free a 3d quantized matrix
- *
- * @param m 3d quantised matrix
- */
-static inline void dl_matrix3dq_free(dl_matrix3dq_t *m)
-{
-    if (NULL == m)
-        return;
-    if (NULL == m->item)
-    {
-        dl_lib_free(m);
-        return;
-    }
-    dl_lib_free(m->item);
-    dl_lib_free(m);
-}
-
-
-/**
- * @brief Copy a range of items from an existing matrix to a preallocated matrix
- *
- * @param dst   The resulting slice matrix
- * @param src   Old matrix to slice.
- * @param x     X-offset of the origin of the returned matrix within the sliced matrix
- * @param y     Y-offset of the origin of the returned matrix within the sliced matrix
- * @param w     Width of the resulting matrix
- * @param h     Height of the resulting matrix
- */
-void dl_matrix3dq_slice_copy(dl_matrix3dq_t *dst, dl_matrix3dq_t *src, int x, int y, int w, int h);
-
-/**
- * @brief Transform a sliced matrix block from nhwc to nchw, the block needs to be memory continous.
- *
- * @param out  The destination sliced matrix in nchw
- * @param in   The source sliced matrix in nhwc
- */
-void dl_matrix3dq_sliced_transform_nchw(dl_matrix3dq_t *out,
-                                        dl_matrix3dq_t *in);
-
-/**
- * @brief Transform a fixed point matrix to a float point matrix
- *
- * @param m     Quantized matrix
- * @return      Float point matrix
- */
-dl_matrix3d_t *dl_matrix3d_from_matrixq(dl_matrix3dq_t *m);
-
-/**
- * @brief Transform a float point matrix to a fixed point matrix with pre-defined exponent
- *
- * @param m         Float point matrix
- * @param exponent  Exponent for resulting matrix
- * @return          Fixed point matrix
- */
-dl_matrix3dq_t *dl_matrixq_from_matrix3d_qmf(dl_matrix3d_t *m, int exponent);
-
-/**
- * @brief Transform a float point matrix to a fixed point matrix. The exponent is defined by the distribution of the input matrix.
- *
- * @param m         Float point matrix
- * @return          Fixed point matrix
- */
-dl_matrix3dq_t *dl_matrixq_from_matrix3d(dl_matrix3d_t *m);
-
-/**
- * @brief Truncate the overflowed 16bit number
- * 
- * @param value               Input value
- * @param location            Location tag
- * @return qtp_t              Truncated value
- */
-qtp_t dl_matrix3dq_quant_range_exceeded_checking(int64_t value, char *location);
-
-/**
- * @brief Reform a quantized matrix with exponent
- *
- * @param out       Preallocated resulting matrix
- * @param in        Input matrix
- * @param exponent  Exponent for resulting matrix
- */
-void dl_matrix3dq_shift_exponent(dl_matrix3dq_t *out, dl_matrix3dq_t *in, int exponent);
-
-/**
- * @brief Do batch normalization for a quantized matrix
- *
- * @param m         Input and output quantized matrix, data will be updated
- * @param scale     Scale of batch-norm
- * @param offset    Offset of batch-norm
- */
-void dl_matrix3dq_batch_normalize(dl_matrix3dq_t *m, dl_matrix3dq_t *scale, dl_matrix3dq_t *offset);
-
-/**
- * @brief Add two quantized matrix with a pre-defined exponent
- *
- * @param in_1                     Adder 1
- * @param in_2                     Adder 2
- * @param exponent                 Exponent for resulting matrix
- * @return dl_matrix3dq_t*         Result of accumulation of two matrix
- */
-dl_matrix3dq_t *dl_matrix3dq_add(dl_matrix3dq_t *in_1, dl_matrix3dq_t *in_2, int exponent);
-
-/**
- * @brief Add two quantized matrix with different channels 
- * 
- * @param in_1               Adder 1
- * @param in_2               Adder 2
- * @param exponent           Exponent for resulting matrix
- * @return dl_matrix3dq_t*   Result of accumulation of two matrix
- */
-dl_matrix3dq_t *dl_matrix3dq_add_channel_diff(dl_matrix3dq_t *in_1, dl_matrix3dq_t *in_2, int exponent);
-
-//
-// Activation
-//
-/**
- * @brief Do relu for a quantized matrix
- *
- * @param in        Input and output quantized matrix, data will be updated
- */
-void dl_matrix3dq_relu(dl_matrix3dq_t *in);
-
-/**
- * @brief Do relu with clips for a quantized matrix
- *
- * @param in        Input and output quantized matrix, data will be updated
- * @param clip      Float point value to limit the maximum data
- */
-void dl_matrix3dq_relu_clip(dl_matrix3dq_t *in, fptp_t clip);
-
-/**
- * @brief Do leaky relu for a quantized matrix
- *
- * @param in        Input and output quantized matrix, data will be updated
- * @param alpha     Float point value to multiply for those less than zero
- * @param clip      Float point value to limit the maximum data
- */
-void dl_matrix3dq_leaky_relu(dl_matrix3dq_t *in, fptp_t alpha, fptp_t clip);
-
-/**
- * @brief Do prelu for a quantized matrix
- *
- * @param in        Input and output quantized matrix, data will be updated
- * @param alpha     Quantized matrix to multiply for those less than zero
- */
-void dl_matrix3dq_p_relu(dl_matrix3dq_t *in, dl_matrix3dq_t *alpha);
-
-//
-// Concat
-//
-/**
- * @brief Concatenate two quantized matrix in channel
- *
- * @param in_1      Quantized matrix to be concatenated
- * @param in_2      Quantized matrix to be concatenated
- * @return          Quantized matrix with the same width and height of in_1 and in_2, and with the sum of channel number of in_1 and in_2
- */
-dl_matrix3dq_t *dl_matrix3dq_concat(dl_matrix3dq_t *in_1,
-                                    dl_matrix3dq_t *in_2);
-
-/**
- * @brief Concatenate four quantized matrix in channel
- *
- * @param in_1      Quantized matrix to be concatenated
- * @param in_2      Quantized matrix to be concatenated
- * @param in_3      Quantized matrix to be concatenated
- * @param in_4      Quantized matrix to be concatenated
- * @return          Quantized matrix with the same width and height of all inputs, and with the sum of channel number of all inputs
- */
-dl_matrix3dq_t *dl_matrix3dq_concat_4(dl_matrix3dq_t *in_1,
-                                      dl_matrix3dq_t *in_2,
-                                      dl_matrix3dq_t *in_3,
-                                      dl_matrix3dq_t *in_4);
-
-/**
- * @brief Concatenate four quantized matrix in channel
- *
- * @param in_1      Quantized matrix to be concatenated
- * @param in_2      Quantized matrix to be concatenated
- * @param in_3      Quantized matrix to be concatenated
- * @param in_4      Quantized matrix to be concatenated
- * @param in_5      Quantized matrix to be concatenated
- * @param in_6      Quantized matrix to be concatenated
- * @param in_7      Quantized matrix to be concatenated
- * @param in_8      Quantized matrix to be concatenated
- * @return          Quantized matrix with the same width and height of all inputs, and with the sum of channel number of all inputs
- */
-dl_matrix3dq_t *dl_matrix3dq_concat_8(dl_matrix3dq_t *in_1,
-                                      dl_matrix3dq_t *in_2,
-                                      dl_matrix3dq_t *in_3,
-                                      dl_matrix3dq_t *in_4,
-                                      dl_matrix3dq_t *in_5,
-                                      dl_matrix3dq_t *in_6,
-                                      dl_matrix3dq_t *in_7,
-                                      dl_matrix3dq_t *in_8);
-
-//
-// Conv 1x1
-//
-/**
- * @brief Do 1x1 convolution with a quantized matrix
- *
- * @param out       Preallocated quantized matrix, size (1, w, h, n)
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    1x1 filter, size (n, 1, 1, c)
- * @param mode      Implementation mode
- * @param name      Layer name to debug
- */
-void dl_matrix3dqq_conv_1x1(dl_matrix3dq_t *out,
-                            dl_matrix3dq_t *in,
-                            dl_matrix3dq_t *filter,
-                            dl_conv_mode mode,
-                            char *name);
-
-/**
- * @brief Do 1x1 convolution with a quantized matrix, with relu activation
- *
- * @param out       Preallocated quantized matrix, size (1, w, h, n)
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    1x1 filter, size (n, 1, 1, c)
- * @param mode      Implementation mode
- * @param name      Layer name to debug
- */
-void dl_matrix3dqq_conv_1x1_with_relu(dl_matrix3dq_t *out,
-                                      dl_matrix3dq_t *in,
-                                      dl_matrix3dq_t *filter,
-                                      dl_conv_mode mode,
-                                      char *name);
-
-/**
- * @brief Do 1x1 convolution with a quantized matrix, with bias adding
- *
- * @param out       Preallocated quantized matrix, size (1, w, h, n)
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    1x1 filter, size (n, 1, 1, c)
- * @param bias      Bias, size (1, 1, 1, n)
- * @param mode      Implementation mode
- * @param name      Layer name to debug
- */
-void dl_matrix3dqq_conv_1x1_with_bias(dl_matrix3dq_t *out,
-                                      dl_matrix3dq_t *in,
-                                      dl_matrix3dq_t *filter,
-                                      dl_matrix3dq_t *bias,
-                                      dl_conv_mode mode,
-                                      char *name);
-
-/**
- * @brief Do 1x1 convolution with a quantized matrix, with bias adding
- *
- * @param out       Preallocated quantized matrix, size (1, w, h, n)
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    1x1 filter, size (n, 1, 1, c)
- * @param bias      Bias, size (1, 1, 1, n)
- * @param mode      Implementation mode
- * @param name      Layer name to debug
- */
-void dl_matrix3dqq_conv_1x1_with_bias_relu(dl_matrix3dq_t *out,
-                                           dl_matrix3dq_t *in,
-                                           dl_matrix3dq_t *filter,
-                                           dl_matrix3dq_t *bias,
-                                           dl_conv_mode mode,
-                                           char *name);
-
-/**
- * @brief Do 1x1 convolution with a quantized matrix, with prelu activation         
- * 
- * @param out       Preallocated quantized matrix, size (1, w, h, n)
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    1x1 filter, size (n, 1, 1, c)
- * @param prelu     prelu params, size (1, 1, 1, n)
- * @param mode      Implementation mode
- * @param name      Layer name to debug
- */
-void dl_matrix3dqq_conv_1x1_with_prelu(dl_matrix3dq_t *out,
-                                       dl_matrix3dq_t *in,
-                                       dl_matrix3dq_t *filter,
-                                       dl_matrix3dq_t *prelu,
-                                       dl_conv_mode mode,
-                                       char *name);
-
-/**
- * @brief Do 1x1 convolution with an 8-bit fixed point matrix
- *
- * @param out       Preallocated quantized matrix, size (1, w, h, n)
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    1x1 filter, size (n, 1, 1, c)
- * @param mode      Implementation mode
- * @param name      Layer name to debug
- */
-void dl_matrix3duq_conv_1x1(dl_matrix3dq_t *out,
-                            dl_matrix3du_t *in,
-                            dl_matrix3dq_t *filter,
-                            dl_conv_mode mode,
-                            char *name);
-
-/**
- * @brief Do 1x1 convolution with an 8-bit fixed point matrix, with bias adding
- *
- * @param out       Preallocated quantized matrix, size (1, w, h, n)
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    1x1 filter, size (n, 1, 1, c)
- * @param bias      Bias, size (1, 1, 1, n)
- * @param mode      Implementation mode
- * @param name      Layer name to debug
- */
-void dl_matrix3duq_conv_1x1_with_bias(dl_matrix3dq_t *out,
-                                      dl_matrix3du_t *in,
-                                      dl_matrix3dq_t *filter,
-                                      dl_matrix3dq_t *bias,
-                                      dl_conv_mode mode,
-                                      char *name);
-
-//
-// Conv 3x3
-//
-
-/**
- * @brief Do 3x3 convolution with a quantized matrix
- * 
- * @param input             Input matrix, size (1, w, h, c)
- * @param filter            3x3 filter, size (n, 3, 3, c)
- * @param stride_x          Stride of width
- * @param stride_y          Stride of height
- * @param padding           Padding type, 0: valid, 1: same
- * @param exponent          Exponent for resulting matrix
- * @param name              Layer name to debug 
- * @return dl_matrix3dq_t*  Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_conv_3x3(dl_matrix3dq_t *input,
-                                       dl_matrix3dq_t *filter,
-                                       int stride_x,
-                                       int stride_y,
-                                       dl_padding_type padding,
-                                       int exponent,
-                                       char *name);
-
-/**
- * @brief Do 3x3 convolution with a quantized matrix, with bias adding
- * 
- * @param input             Input matrix, size (1, w, h, c)
- * @param filter            3x3 filter, size (n, 3, 3, c)
- * @param bias              Bias, size (1, 1, 1, n)
- * @param stride_x          Stride of width
- * @param stride_y          Stride of height
- * @param padding           Padding type
- * @param exponent          Exponent for resulting matrix
- * @param name              Layer name to debug 
- * @return dl_matrix3dq_t*  Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_conv_3x3_with_bias(dl_matrix3dq_t *input,
-                                                 dl_matrix3dq_t *filter,
-                                                 dl_matrix3dq_t *bias,
-                                                 int stride_x,
-                                                 int stride_y,
-                                                 dl_padding_type padding,
-                                                 int exponent,
-                                                 char *name);
-
-/**
- * @brief Do 3x3 convolution with a quantized matrix, with bias adding, relu activation
- * 
- * @param input             Input matrix, size (1, w, h, c)
- * @param filter            3x3 filter, size (n, 3, 3, c)
- * @param bias              Bias, size (1, 1, 1, n)
- * @param stride_x          Stride of width
- * @param stride_y          Stride of height
- * @param padding           Padding type
- * @param exponent          Exponent for resulting matrix
- * @param name              Layer name to debug 
- * @return dl_matrix3dq_t*  Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_conv_3x3_with_bias_relu(dl_matrix3dq_t *input,
-                                                      dl_matrix3dq_t *filter,
-                                                      dl_matrix3dq_t *bias,
-                                                      int stride_x,
-                                                      int stride_y,
-                                                      dl_padding_type padding,
-                                                      int exponent,
-                                                      char *name);
-
-/**
- * @brief  Do 3x3 convolution with an 8-bit fixed point matrix, with bias adding
- * 
- * @param input             Input matrix, size (1, w, h, c)
- * @param filter            3x3 filter, size (n, 3, 3, c)
- * @param bias              Bias, size (1, 1, 1, n)
- * @param stride_x          Stride of width
- * @param stride_y          Stride of height
- * @param padding           Padding type
- * @param exponent          Exponent for resulting matrix
- * @param name              Layer name to debug 
- * @return dl_matrix3dq_t*  Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3duq_conv_3x3_with_bias(dl_matrix3du_t *input,
-                                                 dl_matrix3dq_t *filter,
-                                                 dl_matrix3dq_t *bias,
-                                                 int stride_x,
-                                                 int stride_y,
-                                                 dl_padding_type padding,
-                                                 int exponent,
-                                                 char *name);
-
-/**
- * @brief   Do 3x3 convolution with an 8-bit fixed point matrix, with bias adding, prelu activation
- * 
- * @param input             Input matrix, size (1, w, h, c)
- * @param filter            3x3 filter, size (n, 3, 3, c)
- * @param bias              Bias, size (1, 1, 1, n)
- * @param prelu             prelu params, size (1, 1, 1, n)
- * @param stride_x          Stride of width
- * @param stride_y          Stride of height
- * @param padding           Padding type
- * @param exponent          Exponent for resulting matrix
- * @param name              Layer name to debug
- * @return dl_matrix3dq_t*  Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3duq_conv_3x3_with_bias_prelu(dl_matrix3du_t *input,
-                                                       dl_matrix3dq_t *filter,
-                                                       dl_matrix3dq_t *bias,
-                                                       dl_matrix3dq_t *prelu,
-                                                       int stride_x,
-                                                       int stride_y,
-                                                       dl_padding_type padding,
-                                                       int exponent,
-                                                       char *name);
-
-
-/**
- * @brief   Do 3x3 convolution with a quantized matrix, with bias adding, prelu activation
- * 
- * @param input             Input matrix, size (1, w, h, c)
- * @param filter            3x3 filter, size (n, 3, 3, c)
- * @param bias              Bias, size (1, 1, 1, n)
- * @param prelu             prelu params, size (1, 1, 1, n)
- * @param stride_x          Stride of width
- * @param stride_y          Stride of height
- * @param padding           Padding type
- * @param exponent          Exponent for resulting matrix
- * @param name              Layer name to debug
- * @return dl_matrix3dq_t*  Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_conv_3x3_with_bias_prelu(dl_matrix3dq_t *input,
-                                                       dl_matrix3dq_t *filter,
-                                                       dl_matrix3dq_t *bias,
-                                                       dl_matrix3dq_t *prelu,
-                                                       int stride_x,
-                                                       int stride_y,
-                                                       dl_padding_type padding,
-                                                       int exponent,
-                                                       char *name);
-//
-// Conv common
-//
-
-/**
- * @brief Do a general convolution layer pass, size is (number, width, height, channel)
- *
- * @param in             Input image
- * @param filter         Weights of the neurons
- * @param bias           Bias for the CNN layer.
- * @param stride_x       The step length of the convolution window in x(width) direction
- * @param stride_y       The step length of the convolution window in y(height) direction
- * @param padding        One of VALID or SAME
- * @param mode           Do convolution using C implement or xtensa implement, 0 or 1, with respect.
- *                       If ESP_PLATFORM is not defined, this value is not used.
- * @return               The result of CNN layer.
- */
-dl_matrix3dq_t *dl_matrix3dqq_conv_common(dl_matrix3dq_t *in,
-                                          dl_matrix3dq_t *filter,
-                                          dl_matrix3dq_t *bias,
-                                          int stride_x,
-                                          int stride_y,
-                                          dl_padding_type padding,
-                                          int exponent,
-                                          dl_conv_mode mode);
-
-/**
- * @brief Do a general convolution layer pass for an 8-bit fixed point matrix, size is (number, width, height, channel)
- *
- * @param in             Input image
- * @param filter         Weights of the neurons
- * @param bias           Bias for the CNN layer.
- * @param stride_x       The step length of the convolution window in x(width) direction
- * @param stride_y       The step length of the convolution window in y(height) direction
- * @param padding        One of VALID or SAME
- * @param mode           Do convolution using C implement or xtensa implement, 0 or 1, with respect.
- *                       If ESP_PLATFORM is not defined, this value is not used.
- * @return               The result of CNN layer.
- */
-dl_matrix3dq_t *dl_matrix3duq_conv_common(dl_matrix3du_t *in,
-                                          dl_matrix3dq_t *filter,
-                                          dl_matrix3dq_t *bias,
-                                          int stride_x,
-                                          int stride_y,
-                                          dl_padding_type padding,
-                                          int exponent,
-                                          dl_conv_mode mode);
-
-//
-// Depthwise 3x3
-//
-/**
- * @brief Do 3x3 depthwise convolution with an 8-bit fixed point matrix
- *
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    3x3 filter, size (1, 3, 3, c)
- * @param stride_x  Stride of width
- * @param stride_y  Stride of height
- * @param padding   Padding type, 0: valid, 1: same
- * @param exponent  Exponent for resulting matrix
- * @param name      Layer name to debug
- * @return          Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3duq_depthwise_conv_3x3(dl_matrix3du_t *in,
-                                                 dl_matrix3dq_t *filter,
-                                                 int stride_x,
-                                                 int stride_y,
-                                                 dl_padding_type padding,
-                                                 int exponent,
-                                                 char *name);
-
-/**
- * @brief Do 3x3 depthwise convolution with a quantized matrix
- *
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    3x3 filter, size (1, 3, 3, c)
- * @param stride_x  Stride of width
- * @param stride_y  Stride of height
- * @param padding   Padding type, 0: valid, 1: same
- * @param relu      ReLU, 0: don't, 1: do
- * @param exponent  Exponent for resulting matrix
- * @param name      Layer name to debug
- * @return          Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_3x3(dl_matrix3dq_t *in,
-                                                 dl_matrix3dq_t *filter,
-                                                 int stride_x,
-                                                 int stride_y,
-                                                 dl_padding_type padding,
-                                                 int relu,
-                                                 int exponent,
-                                                 char *name);
-
-#if CONFIG_DEVELOPING_CODE
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_3x3_2(dl_matrix3dq_t *in,
-                                                   dl_matrix3dq_t *filter,
-                                                   int stride_x,
-                                                   int stride_y,
-                                                   dl_padding_type padding,
-                                                   int exponent,
-                                                   char *name);
-
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_3x3_3(dl_matrix3dq_t *in,
-                                                   dl_matrix3dq_t *filter,
-                                                   int stride_x,
-                                                   int stride_y,
-                                                   dl_padding_type padding,
-                                                   int exponent,
-                                                   char *name);
-#endif
-
-/**
- * @brief Do 3x3 depthwise convolution with a quantized matrix, with bias adding
- *
- * @param in        Input matrix, size (1, w, h, c)
- * @param f         3x3 filter, size (1, 3, 3, c)
- * @param bias      Bias, size (1, 1, 1, c)
- * @param stride_x  Stride of width
- * @param stride_y  Stride of height
- * @param padding   Padding type, 0: valid, 1: same
- * @param exponent  Exponent for resulting matrix
- * @param relu      Whether to use relu activation
- * @param name      Layer name to debug
- * @return          Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_3x3_with_bias(dl_matrix3dq_t *in,
-                                                           dl_matrix3dq_t *f,
-                                                           dl_matrix3dq_t *bias,
-                                                           int stride_x,
-                                                           int stride_y,
-                                                           dl_padding_type padding,
-                                                           int exponent,
-                                                           int relu,
-                                                           char *name);
-
-/**
- * @brief Do 3x3 depthwise convolution with a quantized matrix, with bias adding and stride 1
- *
- * @param in        Input matrix, size (1, w, h, c)
- * @param f         3x3 filter, size (1, 3, 3, c)
- * @param bias      Bias, size (1, 1, 1, c)
- * @param padding   Padding type, 0: valid, 1: same
- * @param exponent  Exponent for resulting matrix
- * @param relu      Whether to use relu activation
- * @param name      Layer name to debug
- * @return          Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_3x3s1_with_bias(dl_matrix3dq_t *in,
-                                                             dl_matrix3dq_t *f,
-                                                             dl_matrix3dq_t *bias,
-                                                             dl_padding_type padding,
-                                                             int exponent,
-                                                             int relu,
-                                                             char *name);
-
-/**
- * @brief Do 3x3 depthwise convolution with a quantized matrix, with prelu activation
- * 
- * @param in               Input matrix, size (1, w, h, c) 
- * @param filter           3x3 filter, size (1, 3, 3, c)
- * @param prelu            prelu params, size (1, 1, 1, c)
- * @param stride_x         Stride of width
- * @param stride_y         Stride of height
- * @param padding          Padding type
- * @param exponent         Exponent for resulting matrix
- * @param name             Layer name to debug
- * @return dl_matrix3dq_t* Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_3x3_with_prelu(dl_matrix3dq_t *in,
-                                                            dl_matrix3dq_t *filter,
-                                                            dl_matrix3dq_t *prelu,
-                                                            int stride_x,
-                                                            int stride_y,
-                                                            dl_padding_type padding,
-                                                            int exponent,
-                                                            char *name);
-
-/**
- * @brief Do 3x3 depthwise convolution with a quantized matrix, with bias adding and prelu activation
- * 
- * @param in               Input matrix, size (1, w, h, c) 
- * @param f                3x3 filter, size (1, 3, 3, c)
- * @param bias             Bias, size (1, 1, 1, c)
- * @param prelu            prelu params, size (1, 1, 1, c)
- * @param stride_x         Stride of width
- * @param stride_y         Stride of height
- * @param padding          Padding type
- * @param exponent         Exponent for resulting matrix
- * @param name             Layer name to debug
- * @return dl_matrix3dq_t* Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_3x3_with_bias_prelu(dl_matrix3dq_t *in,
-                                                           dl_matrix3dq_t *f,
-                                                           dl_matrix3dq_t *bias,
-                                                           dl_matrix3dq_t *prelu,
-                                                           int stride_x,
-                                                           int stride_y,
-                                                           dl_padding_type padding,
-                                                           int exponent,
-                                                           char *name);
-
-/**
- * @brief Do global depthwise convolution with a quantized matrix, with bias adding
- * 
- * @param in                 Input matrix, size (1, w, h, c)    
- * @param filter             filter, size (1, w, h, c)
- * @param bias               Bias, size (1, 1, 1, c)
- * @param exponent           Exponent for resulting matrix
- * @param name               Layer name to debug
- * @return dl_matrix3dq_t*   Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_global_depthwise_conv_with_bias(dl_matrix3dq_t *in,
-                                                    dl_matrix3dq_t *filter,
-                                                    dl_matrix3dq_t *bias,
-                                                    int exponent,
-                                                    char *name);
-
-
-
-//
-// Depthwise 2x2
-//
-/**
- * @brief Do 2x2 depthwise convolution with a quantized matrix
- *
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    2x2 filter, size (1, 2, 2, c)
- * @param stride_x  Stride of width
- * @param stride_y  Stride of height
- * @param padding   Padding type, 0: valid, 1: same
- * @param exponent  Exponent for resulting matrix
- * @param name      Layer name to debug
- * @return          Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_2x2(dl_matrix3dq_t *in,
-                                                 dl_matrix3dq_t *filter,
-                                                 int stride_x,
-                                                 int stride_y,
-                                                 dl_padding_type padding,
-                                                 int exponent,
-                                                 char *name);
-
-/**
- * @brief Do 2x2 depthwise convolution with a quantized matrix, with bias adding
- *
- * @param in        Input matrix, size (1, w, h, c)
- * @param f         2x2 filter, size (1, 2, 2, c)
- * @param bias      Bias, size (1, 1, 1, c)
- * @param stride_x  Stride of width
- * @param stride_y  Stride of height
- * @param padding   Padding type, 0: valid, 1: same
- * @param exponent  Exponent for resulting matrix
- * @param relu      Whether to use relu activation
- * @param name      Layer name to debug
- * @return          Resulting quantized matrix
- */                                        
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_2x2_with_bias(dl_matrix3dq_t *in,
-                                                           dl_matrix3dq_t *f,
-                                                           dl_matrix3dq_t *bias,
-                                                           int stride_x,
-                                                           int stride_y,
-                                                           dl_padding_type padding,
-                                                           int exponent,
-                                                           int relu,
-                                                           char *name);
-
-/**
- * @brief Do 2x2 depthwise convolution with a quantized matrix, with prelu activation
- * 
- * @param in               Input matrix, size (1, w, h, c) 
- * @param filter           2x2 filter, size (1, 2, 2, c)
- * @param prelu            prelu params, size (1, 1, 1, c)
- * @param stride_x         Stride of width
- * @param stride_y         Stride of height
- * @param padding          Padding type
- * @param exponent         Exponent for resulting matrix
- * @param name             Layer name to debug
- * @return dl_matrix3dq_t* Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_2x2_with_prelu(dl_matrix3dq_t *in,
-                                                            dl_matrix3dq_t *filter,
-                                                            dl_matrix3dq_t *prelu,
-                                                            int stride_x,
-                                                            int stride_y,
-                                                            dl_padding_type padding,
-                                                            int exponent,
-                                                            char *name);
-
-/**
- * @brief Do 2x2 depthwise convolution with a quantized matrix, with bias adding and prelu activation
- * 
- * @param in               Input matrix, size (1, w, h, c) 
- * @param f                2x2 filter, size (1, 2, 2, c)
- * @param bias             Bias, size (1, 1, 1, c)
- * @param prelu            prelu params, size (1, 1, 1, c)
- * @param stride_x         Stride of width
- * @param stride_y         Stride of height
- * @param padding          Padding type
- * @param exponent         Exponent for resulting matrix
- * @param name             Layer name to debug
- * @return dl_matrix3dq_t* Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_2x2_with_bias_prelu(dl_matrix3dq_t *in,
-                                                                 dl_matrix3dq_t *f,
-                                                                 dl_matrix3dq_t *bias,
-                                                                 dl_matrix3dq_t *prelu,
-                                                                 int stride_x,
-                                                                 int stride_y,
-                                                                 dl_padding_type padding,
-                                                                 int exponent,
-                                                                 char *name);
-
-//
-// Depthwise 5x5
-//
-/**
- * @brief Do 5x5 depthwise convolution with a quantized matrix
- *
- * @param in        Input matrix, size (1, w, h, c)
- * @param filter    5x5 filter, size (1, 5, 5, c)
- * @param stride_x  Stride of width
- * @param stride_y  Stride of height
- * @param padding   Padding type, 0: valid, 1: same
- * @param exponent  Exponent for resulting matrix
- * @param name      Layer name to debug
- * @return          Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_5x5(dl_matrix3dq_t *in,
-                                                 dl_matrix3dq_t *filter,
-                                                 int stride_x,
-                                                 int stride_y,
-                                                 dl_padding_type padding,
-                                                 int exponent,
-                                                 char *name);
-
-/**
- * @brief Do 5x5 depthwise convolution with a quantized matrix, with bias adding
- *
- * @param in        Input matrix, size (1, w, h, c)
- * @param f         5x5 filter, size (1, 5, 5, c)
- * @param bias      Bias, size (1, 1, 1, c)
- * @param stride_x  Stride of width
- * @param stride_y  Stride of height
- * @param padding   Padding type, 0: valid, 1: same
- * @param exponent  Exponent for resulting matrix
- * @param relu      Whether to use relu activation
- * @param name      Layer name to debug
- * @return          Resulting quantized matrix
- */                                         
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_5x5_with_bias(dl_matrix3dq_t *in,
-                                                           dl_matrix3dq_t *f,
-                                                           dl_matrix3dq_t *bias,
-                                                           int stride_x,
-                                                           int stride_y,
-                                                           dl_padding_type padding,
-                                                           int exponent,
-                                                           int relu,
-                                                           char *name);
-
-/**
- * @brief Do 5x5 depthwise convolution with a quantized matrix, with prelu activation
- * 
- * @param in               Input matrix, size (1, w, h, c) 
- * @param filter           5x5 filter, size (1, 5, 5, c)
- * @param prelu            prelu params, size (1, 1, 1, c)
- * @param stride_x         Stride of width
- * @param stride_y         Stride of height
- * @param padding          Padding type
- * @param exponent         Exponent for resulting matrix
- * @param name             Layer name to debug
- * @return dl_matrix3dq_t* Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_5x5_with_prelu(dl_matrix3dq_t *in,
-                                                            dl_matrix3dq_t *filter,
-                                                            dl_matrix3dq_t *prelu,
-                                                            int stride_x,
-                                                            int stride_y,
-                                                            dl_padding_type padding,
-                                                            int exponent,
-                                                            char *name);
-
-/**
- * @brief Do 5x5 depthwise convolution with a quantized matrix, with bias adding and prelu activation
- * 
- * @param in               Input matrix, size (1, w, h, c) 
- * @param f                5x5 filter, size (1, 5, 5, c)
- * @param bias             Bias, size (1, 1, 1, c)
- * @param prelu            prelu params, size (1, 1, 1, c)
- * @param stride_x         Stride of width
- * @param stride_y         Stride of height
- * @param padding          Padding type
- * @param exponent         Exponent for resulting matrix
- * @param name             Layer name to debug
- * @return dl_matrix3dq_t* Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_5x5_with_bias_prelu(dl_matrix3dq_t *in,
-                                                                 dl_matrix3dq_t *f,
-                                                                 dl_matrix3dq_t *bias,
-                                                                 dl_matrix3dq_t *prelu,
-                                                                 int stride_x,
-                                                                 int stride_y,
-                                                                 dl_padding_type padding,
-                                                                 int exponent,
-                                                                 char *name);
-                                                    
-//
-// Depthwise Common
-//
-#if CONFIG_DEVELOPING_CODE
-/**
- * @brief Do a general depthwise convolution layer pass with a quantized matrix
- * 
- * @param in                    Input matrix, size (1, w, h, c) 
- * @param filter                Weights of the neurons, size (1, k_w, k_h, c)
- * @param stride_x              Stride of width
- * @param stride_y              Stride of height
- * @param padding               Padding type
- * @param exponent              Exponent for resulting matrix
- * @param mode                  Implementation mode
- * @return dl_matrix3dq_t*      Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_depthwise_conv_common(dl_matrix3dq_t *in,
-                                                    dl_matrix3dq_t *filter,
-                                                    int stride_x,
-                                                    int stride_y,
-                                                    dl_padding_type padding,
-                                                    int exponent,
-                                                    dl_conv_mode mode);
-
-/**
- * @brief Do a general depthwise convolution layer pass with an 8-bit fixed point matrix
- * 
- * @param in                    Input matrix, size (1, w, h, c) 
- * @param filter                Weights of the neurons, size (1, k_w, k_h, c)
- * @param stride_x              Stride of width
- * @param stride_y              Stride of height
- * @param padding               Padding type
- * @param exponent              Exponent for resulting matrix
- * @param mode                  Implementation mode
- * @return dl_matrix3dq_t*      Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3duq_depthwise_conv_common(dl_matrix3du_t *in,
-                                                    dl_matrix3dq_t *filter,
-                                                    int stride_x,
-                                                    int stride_y,
-                                                    dl_padding_type padding,
-                                                    int exponent,
-                                                    dl_conv_mode mode);
-#endif
-
-//
-// Dot Product
-//
-
-/**
- * @brief Do dot product operation with a quantized matrix
- * 
- * @param out     Preallocated resulting matrix, size (1, 1, 1, h)
- * @param in      Input matrix, size (1, 1, 1, w)
- * @param filter  Filter matrix, size (1, w, h, 1)
- * @param mode    Implementation mode
- */
-void dl_matrix3dqq_dot_product(dl_matrix3dq_t *out,
-                               dl_matrix3dq_t *in,
-                               dl_matrix3dq_t *filter,
-                               dl_conv_mode mode);
-
-//
-// FC
-//
-/**
- * @brief Do fully connected layer forward.
- *
- * @param out       Preallocated resulting matrix, size (1, 1, 1, h)
- * @param in        Input matrix, size (1, 1, 1, w)
- * @param filter    Filter matrix, size (1, w, h, 1)
- * @param mode      Implementation mode
- * @param name      Layer name to debug
- */
-void dl_matrix3dqq_fc(dl_matrix3dq_t *out,
-                      dl_matrix3dq_t *in,
-                      dl_matrix3dq_t *filter,
-                      dl_conv_mode mode,
-                      char *name);
-
-/**
- * @brief Do fully connected layer forward, with bias adding
- *
- * @param out       Preallocated resulting matrix, size (1, 1, 1, h)
- * @param in        Input matrix, size (1, 1, 1, w)
- * @param filter    Filter matrix, size (1, w, h, 1)
- * @param bias      Bias matrix, size (1, 1, 1, h)
- * @param mode      Implementation mode
- * @param name      Layer name to debug
- */
-void dl_matrix3dqq_fc_with_bias(dl_matrix3dq_t *out,
-                                dl_matrix3dq_t *in,
-                                dl_matrix3dq_t *filter,
-                                dl_matrix3dq_t *bias,
-                                dl_conv_mode mode,
-                                char *name);
-
-//
-// Mobilefaceblock
-//
-/**
- * @brief Do mobilefacenet process with splited pointwise 1x1 convolution, the process sequence is 1x1 pointwise->bn->relu->3x3 depthwise->bn->relu->1x1 pointwise->bn
- *
- * @param in                    Input matrix, size (1, w, h, c)
- * @param pw_1                  Pointwise 1x1 filter, size (n1/2, 1, 1, c)
- * @param pw_2                  Pointwise 1x1 filter, size (n1/2, 1, 1, c)
- * @param pw_bias               Pointwise bias, size (1, 1, 1, n1)
- * @param dw                    Depthwise 3x3 filter, size (1, 3, 3, n1)
- * @param dw_bias               Depthwise bias, size (1, 1, 1, n1)
- * @param pw_linear_1           Pointwise 1x1 filter, size (n2/2, 1, 1, n1)
- * @param pw_linear_2           Pointwise 1x1 filter, size (n2/2, 1, 1, n1)
- * @param pw_linear_bias        Pointwise bias, size (1, 1, 1, n2)
- * @param pw_exponent           Exponent for pointwise resulting matrix
- * @param dw_exponent           Exponent for depthwise resulting matrix
- * @param pw_linear_exponent    Exponent for pointwise resulting matrix
- * @param stride_x              Stride of width
- * @param stride_y              Stride of height
- * @param padding               Padding type, 0: valid, 1: same
- * @param mode                  Implementation mode
- * @param shortcut              Whether has a shortcut at pointwise linear
- * @return                      Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_mobilefaceblock_split(dl_matrix3dq_t *in,
-                                                    dl_matrix3dq_t *pw_1,
-                                                    dl_matrix3dq_t *pw_2,
-                                                    dl_matrix3dq_t *pw_bias,
-                                                    dl_matrix3dq_t *dw,
-                                                    dl_matrix3dq_t *dw_bias,
-                                                    dl_matrix3dq_t *pw_linear_1,
-                                                    dl_matrix3dq_t *pw_linear_2,
-                                                    dl_matrix3dq_t *pw_linear_bias,
-                                                    int pw_exponent,
-                                                    int dw_exponent,
-                                                    int pw_linear_exponent,
-                                                    int stride_x,
-                                                    int stride_y,
-                                                    dl_padding_type padding,
-                                                    dl_conv_mode mode,
-                                                    int shortcut);
-
-/**
- * @brief Do mobilefacenet process, the process sequence is 1x1 pointwise->bn->relu->3x3 depthwise->bn->relu->1x1 pointwise->bn
- *
- * @param in                    Input matrix, size (1, w, h, c)
- * @param pw                    Pointwise 1x1 filter, size (n1, 1, 1, c)
- * @param pw_bias               Pointwise bias, size (1, 1, 1, n1)
- * @param dw                    Depthwise 3x3 filter, size (1, 3, 3, n1)
- * @param dw_bias               Depthwise bias, size (1, 1, 1, n1)
- * @param pw_linear             Pointwise 1x1 filter, size (n2, 1, 1, n1)
- * @param pw_linear_bias        Pointwise bias, size (1, 1, 1, n2)
- * @param pw_exponent           Exponent for pointwise resulting matrix
- * @param dw_exponent           Exponent for depthwise resulting matrix
- * @param pw_linear_exponent    Exponent for pointwise resulting matrix
- * @param stride_x              Stride of width
- * @param stride_y              Stride of height
- * @param padding               Padding type, 0: valid, 1: same
- * @param mode                  Implementation mode
- * @param shortcut              Whether has a shortcut at pointwise linear
- * @return                      Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_mobilefaceblock(dl_matrix3dq_t *in,
-                                              dl_matrix3dq_t *pw,
-                                              dl_matrix3dq_t *pw_bias,
-                                              dl_matrix3dq_t *dw,
-                                              dl_matrix3dq_t *dw_bias,
-                                              dl_matrix3dq_t *pw_linear,
-                                              dl_matrix3dq_t *pw_linear_bias,
-                                              int pw_exponent,
-                                              int dw_exponent,
-                                              int pw_linear_exponent,
-                                              int stride_x,
-                                              int stride_y,
-                                              dl_padding_type padding,
-                                              dl_conv_mode mode,
-                                              int shortcut);
-
-/**
- * @brief Do mobilefacenet process, the process sequence is 1x1 pointwise->bn->prelu->3x3 depthwise->bn->prelu->1x1 pointwise->bn
- * 
- * @param in                     Input matrix, size (1, w, h, c)
- * @param pw                     Pointwise 1x1 filter, size (n1, 1, 1, c)
- * @param pw_bias                Pointwise bias, size (1, 1, 1, n1)
- * @param pw_prelu               Pointwise prelu, size (1, 1, 1, n1)
- * @param dw                     Depthwise 3x3 filter, size (1, 3, 3, n1)
- * @param dw_bias                Depthwise bias, size (1, 1, 1, n1)
- * @param dw_prelu               Depthwise prelu, size(1, 1, 1, n1)
- * @param pw_linear              Pointwise 1x1 filter, size (n2, 1, 1, n1)
- * @param pw_linear_bias         Pointwise bias, size (1, 1, 1, n2)
- * @param pw_exponent            Exponent for pointwise resulting matrix
- * @param dw_exponent            Exponent for depthwise resulting matrix
- * @param pw_linear_exponent     Exponent for pointwise resulting matrix
- * @param stride_x               Stride of width
- * @param stride_y               Stride of height
- * @param padding                Depthwise Convlution Padding type
- * @param mode                   Implementation mode
- * @param shortcut               Whether has a shortcut at pointwise linear
- * @return dl_matrix3dq_t*       Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_mobilefaceblock_prelu(dl_matrix3dq_t *in,
-                                                dl_matrix3dq_t *pw,
-                                                dl_matrix3dq_t *pw_bias,
-                                                dl_matrix3dq_t *pw_prelu,
-                                                dl_matrix3dq_t *dw,
-                                                dl_matrix3dq_t *dw_bias,
-                                                dl_matrix3dq_t *dw_prelu,
-                                                dl_matrix3dq_t *pw_linear,
-                                                dl_matrix3dq_t *pw_linear_bias,
-                                                int pw_exponent,
-                                                int dw_exponent,
-                                                int pw_linear_exponent,
-                                                int stride_x,
-                                                int stride_y,
-                                                dl_padding_type padding,
-                                                dl_conv_mode mode,
-                                                int shortcut);
-
-/**@{*/
-/**
- * @brief Do mobilefacenet process, the process sequence is 1x1 pointwise->bn->prelu->3x3 depthwise->bn->prelu->1x1 pointwise->bn
- * 
- * Compared to ‘dl_matrix3dqq_mobilefaceblock_prelu’， this family of functions 'dl_matrix3dqq_mobilefaceblock_prelu_split_x1_x2' 
- * split the first pointwise convlution into x1 pointwise convlutions, and split the second pointwise convlution into x2 pointwise convlutions.
- * 
- * 
- */
-dl_matrix3dq_t *dl_matrix3dqq_mobilefaceblock_prelu_split_2_2(dl_matrix3dq_t *in,
-                                                    dl_matrix3dq_t *pw_1,
-                                                    dl_matrix3dq_t *pw_2,
-                                                    dl_matrix3dq_t *pw_bias,
-                                                    dl_matrix3dq_t *pw_prelu,
-                                                    dl_matrix3dq_t *dw,
-                                                    dl_matrix3dq_t *dw_bias,
-                                                    dl_matrix3dq_t *dw_prelu,
-                                                    dl_matrix3dq_t *pw_linear_1,
-                                                    dl_matrix3dq_t *pw_linear_2,
-                                                    dl_matrix3dq_t *pw_linear_bias,
-                                                    int pw_exponent,
-                                                    int dw_exponent,
-                                                    int pw_linear_exponent,
-                                                    int stride_x,
-                                                    int stride_y,
-                                                    dl_padding_type padding,
-                                                    dl_conv_mode mode,
-                                                    int shortcut);
-
-dl_matrix3dq_t *dl_matrix3dqq_mobilefaceblock_prelu_split_4_4(dl_matrix3dq_t *in,
-                                                    dl_matrix3dq_t *pw_1,
-                                                    dl_matrix3dq_t *pw_2,
-                                                    dl_matrix3dq_t *pw_3,
-                                                    dl_matrix3dq_t *pw_4,
-                                                    dl_matrix3dq_t *pw_bias,
-                                                    dl_matrix3dq_t *pw_prelu,
-                                                    dl_matrix3dq_t *dw,
-                                                    dl_matrix3dq_t *dw_bias,
-                                                    dl_matrix3dq_t *dw_prelu,
-                                                    dl_matrix3dq_t *pw_linear_1,
-                                                    dl_matrix3dq_t *pw_linear_2,
-                                                    dl_matrix3dq_t *pw_linear_3,
-                                                    dl_matrix3dq_t *pw_linear_4,
-                                                    dl_matrix3dq_t *pw_linear_bias,
-                                                    int pw_exponent,
-                                                    int dw_exponent,
-                                                    int pw_linear_exponent,
-                                                    int stride_x,
-                                                    int stride_y,
-                                                    dl_padding_type padding,
-                                                    dl_conv_mode mode,
-                                                    int shortcut);
-
-dl_matrix3dq_t *dl_matrix3dqq_mobilefaceblock_prelu_split_1_2(dl_matrix3dq_t *in,
-                                                    dl_matrix3dq_t *pw,
-                                                    dl_matrix3dq_t *pw_bias,
-                                                    dl_matrix3dq_t *pw_prelu,
-                                                    dl_matrix3dq_t *dw,
-                                                    dl_matrix3dq_t *dw_bias,
-                                                    dl_matrix3dq_t *dw_prelu,
-                                                    dl_matrix3dq_t *pw_linear_1,
-                                                    dl_matrix3dq_t *pw_linear_2,
-                                                    dl_matrix3dq_t *pw_linear_bias,
-                                                    int pw_exponent,
-                                                    int dw_exponent,
-                                                    int pw_linear_exponent,
-                                                    int stride_x,
-                                                    int stride_y,
-                                                    dl_padding_type padding,
-                                                    dl_conv_mode mode,
-                                                    int shortcut);
-/**@}*/
-
-//
-//  blazeblock
-//
-
-/**
- * @brief Do blazeblock process, the process sequence is depthwise->bn->1x1 pointwise->bn->shortcut->relu
- * 
- * @param in                 Input matrix, size (1, w, h, c)
- * @param dw1_kernel         Depthwise filter, size (1, k, k, c)
- * @param dw1_bias           Depthwise bias, size (1, 1, 1, c)
- * @param pw1_kernel         Pointwise 1x1 filter, size (n, 1, 1, c)
- * @param pw1_bias           Pointwise bias, size (1, 1, 1, n)
- * @param config             blazeblock configuration
- * @param name               Layer name to debug
- * @return dl_matrix3dq_t*   Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_blazeblock(dl_matrix3dq_t *in,
-                                        dl_matrix3dq_t *dw1_kernel,
-                                        dl_matrix3dq_t *dw1_bias,
-                                        dl_matrix3dq_t *pw1_kernel,
-                                        dl_matrix3dq_t *pw1_bias,
-                                        dl_matrix3dq_blazeblock_config_t config,
-                                        char *name);
-
-/**
- * @brief Do double blazeblock process, the process sequence is depthwise->bn->1x1 pointwise->bn->relu->depthwise->bn->1x1 pointwise->bn->shortcut->relu 
- * 
- * @param in                 Input matrix, size (1, w, h, c)
- * @param dw1_kernel         Depthwise filter, size (1, k, k, c)
- * @param dw1_bias           Depthwise bias, size (1, 1, 1, c)
- * @param pw1_kernel         Pointwise 1x1 filter, size (n1, 1, 1, c)
- * @param pw1_bias           Pointwise bias, size (1, 1, 1, n1)
- * @param dw2_kernel         Depthwise filter, size (1, k, k, n1)
- * @param dw2_bias           Depthwise bias, size (1, 1, 1, n1)
- * @param pw2_kernel         Pointwise 1x1 filter, size (n2, 1, 1, n1)
- * @param pw2_bias           Pointwise bias, size (1, 1, 1, n2)
- * @param config             blazeblock configuration
- * @param name               Layer name to debug
- * @return dl_matrix3dq_t*   Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_double_blazeblock(dl_matrix3dq_t *in,
-                                        dl_matrix3dq_t *dw1_kernel,
-                                        dl_matrix3dq_t *dw1_bias,
-                                        dl_matrix3dq_t *pw1_kernel,
-                                        dl_matrix3dq_t *pw1_bias,
-                                        dl_matrix3dq_t *dw2_kernel,
-                                        dl_matrix3dq_t *dw2_bias,
-                                        dl_matrix3dq_t *pw2_kernel,
-                                        dl_matrix3dq_t *pw2_bias,
-                                        dl_matrix3dq_blazeblock_config_t config,
-                                        char *name);
-//
-// Mobilenet
-//
-
-/**
- * @brief Do mobilenet process, the process sequence is 1x1 dilated->prelu->3x3 depthwise->prelu->1x1 compress->bias
- *
- * @param in                    Input matrix, size (1, w, h, c)
- * @param dilate                Pointwise 1x1 filter, size (n1, 1, 1, c)
- * @param dilate_prelu          Pointwise prelu, size (1, 1, 1, n1)
- * @param depthwise             Depthwise 3x3 filter, size (1, 3, 3, n1)
- * @param depthwise_prelu       Depthwise prelu, size (1, 1, 1, n1)
- * @param compress              Pointwise 1x1 filter, size (n2, 1, 1, n1)
- * @param bias                  Pointwise bias, size (1, 1, 1, n2)
- * @param config                Mobilenet configuration
- * @param name                  Block name to debug
- * @return dl_matrix3dq_t*      Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3dqq_mobilenet(dl_matrix3dq_t *in,
-                                        dl_matrix3dq_t *dilate,
-                                        dl_matrix3dq_t *dilate_prelu,
-                                        dl_matrix3dq_t *depthwise,
-                                        dl_matrix3dq_t *depth_prelu,
-                                        dl_matrix3dq_t *compress,
-                                        dl_matrix3dq_t *bias,
-                                        dl_matrix3dq_mobilenet_config_t config,
-                                        char *name);
-
-/**
- * @brief Do mobilenet process, the process sequence is 1x1 dilated->prelu->3x3 depthwise->prelu->1x1 compress->bias
- *
- * @param in                    Input matrix, 8-bit fixed point, size (1, w, h, c)
- * @param dilate                Pointwise 1x1 filter, size (n1, 1, 1, c)
- * @param dilate_prelu          Pointwise prelu, size (1, 1, 1, n1)
- * @param depthwise             Depthwise 3x3 filter, size (1, 3, 3, n1)
- * @param depthwise_prelu       Depthwise prelu, size (1, 1, 1, n1)
- * @param compress              Pointwise 1x1 filter, size (n2, 1, 1, n1)
- * @param bias                  Pointwise bias, size (1, 1, 1, n2)
- * @param config                Mobilenet configuration
- * @param name                  Block name to debug
- * @return dl_matrix3dq_t*      Resulting quantized matrix
- */
-dl_matrix3dq_t *dl_matrix3duq_mobilenet(dl_matrix3du_t *in,
-                                        dl_matrix3dq_t *dilate,
-                                        dl_matrix3dq_t *dilate_prelu,
-                                        dl_matrix3dq_t *depthwise,
-                                        dl_matrix3dq_t *depth_prelu,
-                                        dl_matrix3dq_t *compress,
-                                        dl_matrix3dq_t *bias,
-                                        dl_matrix3dq_mobilenet_config_t config,
-                                        char *name);
-
-//
-// Padding
-//
-
-/**@{*/
-/**
- * @brief This family of functions do a padding operation before a convlution
- * 
- * @param padded_input      the padded result pointer
- * @param output_height     the output height pointer
- * @param output_width      the output width pointer
- * @param input             Input matrix, size (1, w, h, c)
- * @param stride_x          Stride of width
- * @param stride_y          Stride of height
- * @param kernel_size       Kernel size of the next convlution
- * @param padding_type      Padding type
- * @return dl_error_type    Return DL_SUCCESS if padding successfully, else return DL_FAIL
- */
-dl_error_type dl_matrix3dqq_padding(dl_matrix3dq_t **padded_input,
-                                    int *output_height,
-                                    int *output_width,
-                                    dl_matrix3dq_t *input,
-                                    int stride_x,
-                                    int stride_y,
-                                    int kernel_size,
-                                    dl_padding_type padding_type);
-
-dl_error_type dl_matrix3duq_padding(dl_matrix3du_t **padded_input,
-                                    int *output_height,
-                                    int *output_width,
-                                    dl_matrix3du_t *input,
-                                    int stride_x,
-                                    int stride_y,
-                                    int kernel_size,
-                                    dl_padding_type padding_type);
-/**@}*/
-
-//
-// Upsample
-//
-/**
- * @brief Upsample a feature map to twice the size 
- * 
- * @param in                  Input matrix, size (1, w, h, c)
- * @param upsample            upsample type
- * @return dl_matrix3dq_t*    Resulting matrix, size (1, 2*w, 2*h, c)
- */
-dl_matrix3dq_t *dl_matrix3dqq_upsample_2x(dl_matrix3dq_t *in, 
-                                        dl_upsample_type upsample);
-
-//
-// Pooling
-//
-/**
- * @brief Calculate average value of a feature map
- *
- * @param in                 Input matrix, size (1, w, h, c)
- * @return dl_matrix3dq_t*   Resulting matrix, size (1, 1, 1, c)
- */
-dl_matrix3dq_t *dl_matrix3dq_global_pool(dl_matrix3dq_t *in);
-
-/**
- * @brief Calculate pooling layer of a feature map
- *
- * @param in                Input matrix, size (1, w, h, c)
- * @param f_w               Window width
- * @param f_h               Window height 
- * @param stride_x          Stride in horizontal direction
- * @param stride_y          Stride in vertical direction
- * @param padding           Padding type: PADDING_VALID and PADDING_SAME
- * @param pooling_type      Pooling type: DL_POOLING_MAX and POOLING_AVG
- * @return dl_matrix3dq_t*  Resulting matrix, size (1, w', h', c)
- */
-dl_matrix3dq_t *dl_matrix3dq_pooling(dl_matrix3dq_t *in,
-                                     int f_w,
-                                     int f_h,
-                                     int stride_x,
-                                     int stride_y,
-                                     dl_padding_type padding,
-                                     dl_pooling_type pooling_type);
diff --git a/tools/sdk/include/esp-face/esp_image.hpp b/tools/sdk/include/esp-face/esp_image.hpp
deleted file mode 100644
index f5f924d6b6a..00000000000
--- a/tools/sdk/include/esp-face/esp_image.hpp
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
-  * ESPRESSIF MIT License
-  *
-  * Copyright (c) 2018 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
-  *
-  * Permission is hereby granted for use on ESPRESSIF SYSTEMS products only, in which case,
-  * it is free of charge, to any person obtaining a copy of this software and associated
-  * documentation files (the "Software"), to deal in the Software without restriction, including
-  * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
-  * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
-  * to do so, subject to the following conditions:
-  *
-  * The above copyright notice and this permission notice shall be included in all copies or
-  * substantial portions of the Software.
-  *
-  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
-#pragma once
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include <stdint.h>
-#include <math.h>
-#include <assert.h>
-
-#ifdef __cplusplus
-}
-#endif
-
-typedef enum
-{
-    IMAGE_RESIZE_BILINEAR = 0, /*<! Resize image by taking bilinear of four pixels */
-    IMAGE_RESIZE_MEAN = 1,     /*<! Resize image by taking mean of four pixels */
-    IMAGE_RESIZE_NEAREST = 2   /*<! Resize image by taking the nearest pixel */
-} image_resize_t;
-
-template <class T>
-class Image
-{
-public:
-    /**
-     * @brief Convert a RGB565 pixel to RGB888
-     * 
-     * @param input     Pixel value in RGB565
-     * @param output    Pixel value in RGB888
-     */
-    static inline void pixel_rgb565_to_rgb888(uint16_t input, T *output)
-    {
-        output[2] = (input & 0x1F00) >> 5;                           //blue
-        output[1] = ((input & 0x7) << 5) | ((input & 0xE000) >> 11); //green
-        output[0] = input & 0xF8;                                    //red
-    };
-
-    /**
-     * @brief Resize a RGB565 image to a RGB88 image
-     * 
-     * @param dst_image     The destination image
-     * @param y_start       The start y index of where resized image located
-     * @param y_end         The end y index of where resized image located
-     * @param x_start       The start x index of where resized image located
-     * @param x_end         The end x index of where resized image located
-     * @param channel       The channel number of image
-     * @param src_image     The source image
-     * @param src_h         The height of source image
-     * @param src_w         The width of source image
-     * @param dst_w         The width of destination image
-     * @param shift_left    The bit number of left shifting
-     * @param type          The resize type
-     */
-    static void resize_to_rgb888(T *dst_image, int y_start, int y_end, int x_start, int x_end, int channel, uint16_t *src_image, int src_h, int src_w, int dst_w, int shift_left, image_resize_t type);
-
-    /**
-     * @brief Resize a RGB888 image to a RGB88 image
-     * 
-     * @param dst_image     The destination image
-     * @param y_start       The start y index of where resized image located
-     * @param y_end         The end y index of where resized image located
-     * @param x_start       The start x index of where resized image located
-     * @param x_end         The end x index of where resized image located
-     * @param channel       The channel number of image
-     * @param src_image     The source image
-     * @param src_h         The height of source image
-     * @param src_w         The width of source image
-     * @param dst_w         The width of destination image
-     * @param shift_left    The bit number of left shifting
-     * @param type          The resize type
-     */
-    static void resize_to_rgb888(T *dst_image, int y_start, int y_end, int x_start, int x_end, int channel, uint8_t *src_image, int src_h, int src_w, int dst_w, int shift_left, image_resize_t type);
-    // static void resize_to_rgb565(uint16_t *dst_image, int y_start, int y_end, int x_start, int x_end, int channel, uint16_t *src_image, int src_h, int src_w, int dst_w, int shift_left, image_resize_t type);
-    // static void resize_to_rgb565(uint16_t *dst_image, int y_start, int y_end, int x_start, int x_end, int channel, uint8_t *src_image, int src_h, int src_w, int dst_w, int shift_left, image_resize_t type);
-};
-
-template <class T>
-void Image<T>::resize_to_rgb888(T *dst_image, int y_start, int y_end, int x_start, int x_end, int channel, uint16_t *src_image, int src_h, int src_w, int dst_w, int shift_left, image_resize_t type)
-{
-    assert(channel == 3);
-    float scale_y = (float)src_h / (y_end - y_start);
-    float scale_x = (float)src_w / (x_end - x_start);
-    int temp[13];
-
-    switch (type)
-    {
-    case IMAGE_RESIZE_BILINEAR:
-        for (size_t y = y_start; y < y_end; y++)
-        {
-            float ratio_y[2];
-            ratio_y[0] = (float)((y + 0.5) * scale_y - 0.5); // y
-            int src_y = (int)ratio_y[0];                     // y1
-            ratio_y[0] -= src_y;                             // y - y1
-
-            if (src_y < 0)
-            {
-                ratio_y[0] = 0;
-                src_y = 0;
-            }
-            if (src_y > src_h - 2)
-            {
-                ratio_y[0] = 0;
-                src_y = src_h - 2;
-            }
-            ratio_y[1] = 1 - ratio_y[0]; // y2 - y
-
-            int _dst_i = y * dst_w;
-
-            int _src_row_0 = src_y * src_w;
-            int _src_row_1 = _src_row_0 + src_w;
-
-            for (size_t x = x_start; x < x_end; x++)
-            {
-                float ratio_x[2];
-                ratio_x[0] = (float)((x + 0.5) * scale_x - 0.5); // x
-                int src_x = (int)ratio_x[0];                     // x1
-                ratio_x[0] -= src_x;                             // x - x1
-
-                if (src_x < 0)
-                {
-                    ratio_x[0] = 0;
-                    src_x = 0;
-                }
-                if (src_x > src_w - 2)
-                {
-                    ratio_x[0] = 0;
-                    src_x = src_w - 2;
-                }
-                ratio_x[1] = 1 - ratio_x[0]; // x2 - x
-
-                int dst_i = (_dst_i + x) * channel;
-
-                int src_row_0 = _src_row_0 + src_x;
-                int src_row_1 = _src_row_1 + src_x;
-
-                Image<int>::pixel_rgb565_to_rgb888(src_image[src_row_0], temp);
-                Image<int>::pixel_rgb565_to_rgb888(src_image[src_row_0 + 1], temp + 3);
-                Image<int>::pixel_rgb565_to_rgb888(src_image[src_row_1], temp + 6);
-                Image<int>::pixel_rgb565_to_rgb888(src_image[src_row_1 + 1], temp + 9);
-
-                for (int c = 0; c < channel; c++)
-                {
-                    temp[12] = round(temp[c] * ratio_x[1] * ratio_y[1] + temp[channel + c] * ratio_x[0] * ratio_y[1] + temp[channel + channel + c] * ratio_x[1] * ratio_y[0] + src_image[channel + channel + channel + c] * ratio_x[0] * ratio_y[0]);
-                    dst_image[dst_i + c] = (shift_left > 0) ? (temp[12] << shift_left) : (temp[12] >> -shift_left);
-                }
-            }
-        }
-        break;
-
-    case IMAGE_RESIZE_MEAN:
-        shift_left -= 2;
-        for (int y = y_start; y < y_end; y++)
-        {
-            int _dst_i = y * dst_w;
-
-            float _src_row_0 = rintf(y * scale_y) * src_w;
-            float _src_row_1 = _src_row_0 + src_w;
-
-            for (int x = x_start; x < x_end; x++)
-            {
-                int dst_i = (_dst_i + x) * channel;
-
-                int src_row_0 = (_src_row_0 + rintf(x * scale_x));
-                int src_row_1 = (_src_row_1 + rintf(x * scale_x));
-
-                Image<int>::pixel_rgb565_to_rgb888(src_image[src_row_0], temp);
-                Image<int>::pixel_rgb565_to_rgb888(src_image[src_row_0 + 1], temp + 3);
-                Image<int>::pixel_rgb565_to_rgb888(src_image[src_row_1], temp + 6);
-                Image<int>::pixel_rgb565_to_rgb888(src_image[src_row_1 + 1], temp + 9);
-
-                dst_image[dst_i] = (shift_left > 0) ? ((temp[0] + temp[3] + temp[6] + temp[9]) << shift_left) : ((temp[0] + temp[3] + temp[6] + temp[9]) >> -shift_left);
-                dst_image[dst_i + 1] = (shift_left > 0) ? ((temp[1] + temp[4] + temp[7] + temp[10]) << shift_left) : ((temp[1] + temp[4] + temp[7] + temp[10]) >> -shift_left);
-                dst_image[dst_i + 2] = (shift_left > 0) ? ((temp[2] + temp[5] + temp[8] + temp[11]) << shift_left) : ((temp[1] + temp[4] + temp[7] + temp[10]) >> -shift_left);
-            }
-        }
-
-        break;
-
-    case IMAGE_RESIZE_NEAREST:
-        for (size_t y = y_start; y < y_end; y++)
-        {
-            int _dst_i = y * dst_w;
-            float _src_i = rintf(y * scale_y) * src_w;
-
-            for (size_t x = x_start; x < x_end; x++)
-            {
-                int dst_i = (_dst_i + x) * channel;
-                int src_i = _src_i + rintf(x * scale_x);
-
-                Image<int>::pixel_rgb565_to_rgb888(src_image[src_i], temp);
-
-                dst_image[dst_i] = (shift_left > 0) ? (temp[0] << shift_left) : (temp[0] >> -shift_left);
-                dst_image[dst_i + 1] = (shift_left > 0) ? (temp[1] << shift_left) : (temp[1] >> -shift_left);
-                dst_image[dst_i + 2] = (shift_left > 0) ? (temp[2] << shift_left) : (temp[2] >> -shift_left);
-            }
-        }
-        break;
-
-    default:
-        break;
-    }
-}
-
-template <class T>
-void Image<T>::resize_to_rgb888(T *dst_image, int y_start, int y_end, int x_start, int x_end, int channel, uint8_t *src_image, int src_h, int src_w, int dst_w, int shift_left, image_resize_t type)
-{
-    float scale_y = (float)src_h / (y_end - y_start);
-    float scale_x = (float)src_w / (x_end - x_start);
-    int temp;
-
-    switch (type)
-    {
-    case IMAGE_RESIZE_BILINEAR:
-        for (size_t y = y_start; y < y_end; y++)
-        {
-            float ratio_y[2];
-            ratio_y[0] = (float)((y + 0.5) * scale_y - 0.5); // y
-            int src_y = (int)ratio_y[0];                     // y1
-            ratio_y[0] -= src_y;                             // y - y1
-
-            if (src_y < 0)
-            {
-                ratio_y[0] = 0;
-                src_y = 0;
-            }
-            if (src_y > src_h - 2)
-            {
-                ratio_y[0] = 0;
-                src_y = src_h - 2;
-            }
-            ratio_y[1] = 1 - ratio_y[0]; // y2 - y
-
-            int _dst_i = y * dst_w;
-
-            int _src_row_0 = src_y * src_w;
-            int _src_row_1 = _src_row_0 + src_w;
-
-            for (size_t x = x_start; x < x_end; x++)
-            {
-                float ratio_x[2];
-                ratio_x[0] = (float)((x + 0.5) * scale_x - 0.5); // x
-                int src_x = (int)ratio_x[0];                     // x1
-                ratio_x[0] -= src_x;                             // x - x1
-
-                if (src_x < 0)
-                {
-                    ratio_x[0] = 0;
-                    src_x = 0;
-                }
-                if (src_x > src_w - 2)
-                {
-                    ratio_x[0] = 0;
-                    src_x = src_w - 2;
-                }
-                ratio_x[1] = 1 - ratio_x[0]; // x2 - x
-
-                int dst_i = (_dst_i + x) * channel;
-
-                int src_row_0 = (_src_row_0 + src_x) * channel;
-                int src_row_1 = (_src_row_1 + src_x) * channel;
-
-                for (int c = 0; c < channel; c++)
-                {
-                    temp = round(src_image[src_row_0 + c] * ratio_x[1] * ratio_y[1] + src_image[src_row_0 + channel + c] * ratio_x[0] * ratio_y[1] + src_image[src_row_1 + c] * ratio_x[1] * ratio_y[0] + src_image[src_row_1 + channel + c] * ratio_x[0] * ratio_y[0]);
-                    dst_image[dst_i + c] = (shift_left > 0) ? (temp << shift_left) : (temp >> -shift_left);
-                }
-            }
-        }
-        break;
-
-    case IMAGE_RESIZE_MEAN:
-        shift_left -= 2;
-
-        for (size_t y = y_start; y < y_end; y++)
-        {
-            int _dst_i = y * dst_w;
-
-            float _src_row_0 = rintf(y * scale_y) * src_w;
-            float _src_row_1 = _src_row_0 + src_w;
-
-            for (size_t x = x_start; x < x_end; x++)
-            {
-                int dst_i = (_dst_i + x) * channel;
-
-                int src_row_0 = (_src_row_0 + rintf(x * scale_x)) * channel;
-                int src_row_1 = (_src_row_1 + rintf(x * scale_x)) * channel;
-
-                for (size_t c = 0; c < channel; c++)
-                {
-                    temp = (int)src_image[src_row_0 + c] + (int)src_image[src_row_0 + channel + c] + (int)src_image[src_row_1 + c] + (int)src_image[src_row_1 + channel + c];
-                    dst_image[dst_i + c] = (shift_left > 0) ? (temp << shift_left) : (temp >> -shift_left);
-                }
-            }
-        }
-        break;
-
-    case IMAGE_RESIZE_NEAREST:
-        for (size_t y = y_start; y < y_end; y++)
-        {
-            int _dst_i = y * dst_w;
-            float _src_i = rintf(y * scale_y) * src_w;
-
-            for (size_t x = x_start; x < x_end; x++)
-            {
-                int dst_i = (_dst_i + x) * channel;
-                int src_i = (_src_i + rintf(x * scale_x)) * channel;
-
-                for (size_t c = 0; c < channel; c++)
-                {
-                    dst_image[dst_i + c] = (shift_left > 0) ? ((T)src_image[src_i + c] << shift_left) : ((T)src_image[src_i + c] >> -shift_left);
-                }
-            }
-        }
-        break;
-
-    default:
-        break;
-    }
-}
\ No newline at end of file
diff --git a/tools/sdk/include/esp-face/fd_forward.h b/tools/sdk/include/esp-face/fd_forward.h
deleted file mode 100644
index 878c8c481c8..00000000000
--- a/tools/sdk/include/esp-face/fd_forward.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
-  * ESPRESSIF MIT License
-  *
-  * Copyright (c) 2018 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
-  *
-  * Permission is hereby granted for use on ESPRESSIF SYSTEMS products only, in which case,
-  * it is free of charge, to any person obtaining a copy of this software and associated
-  * documentation files (the "Software"), to deal in the Software without restriction, including
-  * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
-  * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
-  * to do so, subject to the following conditions:
-  *
-  * The above copyright notice and this permission notice shall be included in all copies or
-  * substantial portions of the Software.
-  *
-  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
-#pragma once
-
-#if __cplusplus
-extern "C"
-{
-#endif
-
-#include "image_util.h"
-#include "dl_lib_matrix3d.h"
-#include "mtmn.h"
-
-    typedef enum
-    {
-        FAST = 0,            /*!< fast resize type */         
-        NORMAL = 1,          /*!< normal resize type */ 
-    } mtmn_resize_type;
-
-    typedef struct
-    {
-        float score;          /*!< score threshold for filter candidates by score */
-        float nms;            /*!< nms threshold for nms process */
-        int candidate_number; /*!< candidate number limitation for each net */
-    } threshold_config_t;
-
-    typedef struct
-    {
-        int w;                        /*!< net width */
-        int h;                        /*!< net height */
-        threshold_config_t threshold; /*!< threshold of net */
-    } net_config_t;
-
-    typedef struct
-    {
-        float min_face;                 /*!< The minimum size of a detectable face */
-        float pyramid;                  /*!< The scale of the gradient scaling for the input images */
-        int pyramid_times;              /*!< The pyramid resizing times */
-        threshold_config_t p_threshold; /*!< The thresholds for P-Net. For details, see the definition of threshold_config_t */
-        threshold_config_t r_threshold; /*!< The thresholds for R-Net. For details, see the definition of threshold_config_t */
-        threshold_config_t o_threshold; /*!< The thresholds for O-Net. For details, see the definition of threshold_config_t */
-        mtmn_resize_type type;          /*!< The image resize type. 'pyramid' will lose efficacy, when 'type'==FAST. */
-    } mtmn_config_t;
-
-    /**
-     * @brief Get the initial MTMN model configuration
-     * 
-     * @return mtmn_config_t      MTMN configuration
-     */
-    static inline mtmn_config_t mtmn_init_config()
-    {
-        mtmn_config_t mtmn_config;
-        mtmn_config.type = FAST;
-        mtmn_config.min_face = 80;
-        mtmn_config.pyramid = 0.707;
-        mtmn_config.pyramid_times = 4;
-        mtmn_config.p_threshold.score = 0.6;
-        mtmn_config.p_threshold.nms = 0.7;
-        mtmn_config.p_threshold.candidate_number = 20;
-        mtmn_config.r_threshold.score = 0.7;
-        mtmn_config.r_threshold.nms = 0.7;
-        mtmn_config.r_threshold.candidate_number = 10;
-        mtmn_config.o_threshold.score = 0.7;
-        mtmn_config.o_threshold.nms = 0.7;
-        mtmn_config.o_threshold.candidate_number = 1;
-
-        return mtmn_config;
-    }
-
-    /**
-     * @brief Do MTMN face detection, return box and landmark infomation.
-     * 
-     * @param image_matrix      Image matrix, rgb888 format
-     * @param config            Configuration of MTMN i.e. score threshold, nms threshold, candidate number threshold, pyramid, min face size
-     * @return box_array_t*     A list of boxes and score.
-     */
-    box_array_t *face_detect(dl_matrix3du_t *image_matrix,
-                             mtmn_config_t *config);
-
-#if __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-face/fr_flash.h b/tools/sdk/include/esp-face/fr_flash.h
deleted file mode 100644
index 5da0ddcc182..00000000000
--- a/tools/sdk/include/esp-face/fr_flash.h
+++ /dev/null
@@ -1,82 +0,0 @@
-#pragma once
-
-#if __cplusplus
-extern "C"
-{
-#endif
-
-#include "fr_forward.h"
-
-#define FR_FLASH_TYPE   32
-#define FR_FLASH_SUBTYPE   32
-#define FR_FLASH_PARTITION_NAME "fr"
-#define FR_FLASH_INFO_FLAG 12138
-        
-     /**
-     * @brief Produce face id according to the input aligned face, and save it to dest_id and flash.
-     * 
-     * @param l                     Face id list
-     * @param aligned_face          An aligned face
-     * @return -2                   Flash partition not found
-     * @return 0                    Enrollment finish
-     * @return >=1                  The left piece of aligned faces should be input
-     */
-    int8_t enroll_face_id_to_flash(face_id_list *l,
-            dl_matrix3du_t *aligned_face);
-
-    /**
-     * @brief Produce face id according to the input aligned face, and save the id-name pairs to dest_id and flash.
-     * 
-     * @param l                     Face id list
-     * @param new_id                An aligned face
-     * @param name                  name corresponding to face id
-     * @return -2                   Flash partition not found
-     * @return 0                    Enrollment finish
-     * @return >=1                  The left piece of aligned faces should be input
-     */
-    int8_t enroll_face_id_to_flash_with_name(face_id_name_list *l,
-            dl_matrix3d_t *new_id,
-            char *name);
-    /**
-     * @brief Read the enrolled face IDs from the flash.
-     * 
-     * @param l                     Face id list
-     * @return int8_t               The number of IDs remaining in flash
-     */
-    int8_t read_face_id_from_flash(face_id_list *l);
-    
-    /**
-     * @brief Read the enrolled face IDs and their corresponding names from the flash.
-     * 
-     * @param l                     Face id list
-     * @return int8_t               The number of IDs remaining in flash
-     */
-    int8_t read_face_id_from_flash_with_name(face_id_name_list *l);
-
-    /**
-     * @brief Delete the enrolled face IDs in the flash.
-     * 
-     * @param l                     Face id list
-     * @return int8_t               The number of IDs remaining in flash
-     */
-    int8_t delete_face_id_in_flash(face_id_list *l);
-
-    /**
-     * @brief Delete the enrolled face ID corresponding to the name in the flash.
-     * 
-     * @param l                     Face id list
-     * @param name                  The name that needs to be deleted
-     * @return int8_t               The number of IDs remaining in flash
-     */
-    int8_t delete_face_id_in_flash_with_name(face_id_name_list *l, char *name);
-
-    /**
-     * @brief Delete all the enrolled face IDs and names paris in the flash.
-     * 
-     * @param l                     Face id list
-     */
-    void delete_face_all_in_flash_with_name(face_id_name_list *l);
-
-#if __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-face/fr_forward.h b/tools/sdk/include/esp-face/fr_forward.h
deleted file mode 100644
index 32c55168eb6..00000000000
--- a/tools/sdk/include/esp-face/fr_forward.h
+++ /dev/null
@@ -1,194 +0,0 @@
-#pragma once
-
-#if __cplusplus
-extern "C"
-{
-#endif
-
-#include "image_util.h"
-#include "dl_lib_matrix3d.h"
-#include "frmn.h"
-
-#define FACE_WIDTH 56
-#define FACE_HEIGHT 56
-#define FACE_ID_SIZE 512
-#define FACE_REC_THRESHOLD 0.55
-
-#define LEFT_EYE_X 0
-#define LEFT_EYE_Y 1
-#define RIGHT_EYE_X 6
-#define RIGHT_EYE_Y 7
-#define NOSE_X 4
-#define NOSE_Y 5
-#define LEFT_MOUTH_X 2
-#define LEFT_MOUTH_Y 3
-#define RIGHT_MOUTH_X 8
-#define RIGHT_MOUTH_Y 9
-
-#define EYE_DIST_SET 16.5f
-#define NOSE_EYE_RATIO_THRES_MIN 0.49f
-#define NOSE_EYE_RATIO_THRES_MAX 2.04f
-
-
-#define ENROLL_NAME_LEN 16
-    typedef struct tag_face_id_node
-    {
-        struct tag_face_id_node *next;           /*!< next face id node */
-        char id_name[ENROLL_NAME_LEN];           /*!< name corresponding to the face id  */
-        dl_matrix3d_t *id_vec;                   /*!< face id */
-    } face_id_node;
-
-    typedef struct
-    {
-        face_id_node *head;    /*!< head pointer of the id list */
-        face_id_node *tail;    /*!< tail pointer of the id list */
-        uint8_t count;         /*!< number of enrolled ids */
-        uint8_t confirm_times; /*!< images needed for one enrolling */
-    } face_id_name_list;
-
-    typedef struct
-    {
-        uint8_t head;            /*!< head index of the id list */
-        uint8_t tail;            /*!< tail index of the id list */
-        uint8_t count;           /*!< number of enrolled ids */
-        uint8_t size;            /*!< max len of id list */
-        uint8_t confirm_times;   /*!< images needed for one enrolling */
-        dl_matrix3d_t **id_list; /*!< stores face id vectors */
-    } face_id_list;
-
-    /**
-     * @brief Initialize face id list.
-     * 
-     * @param l                    Face id list
-     * @param size                 Size of list, one list contains one vector
-     * @param confirm_times        Enroll times for one id
-     */
-    void face_id_init(face_id_list *l, uint8_t size, uint8_t confirm_times);
-
-    /**
-     * @brief Initialize face id list with name.
-     * 
-     * @param l                    Face id list
-     * @param size                 Size of list, one list contains one vector
-     * @param confirm_times        Enroll times for one id
-     */
-    void face_id_name_init(face_id_name_list *l, uint8_t size, uint8_t confirm_times);
-
-    /**
-     * @brief Alloc memory for aligned face.
-     * 
-     * @return dl_matrix3du_t*          Size: 1xFACE_WIDTHxFACE_HEIGHTx3
-     */
-    dl_matrix3du_t *aligned_face_alloc();
-
-    /**@{*/
-    /**
-     * @brief Align detected face to average face according to landmark.
-     * 
-     * @param onet_boxes        Output of MTMN with box and landmark
-     * @param src               Image matrix, rgb888 format
-     * @param dest              Output image
-     * @return ESP_OK           Input face is good for recognition
-     * @return ESP_FAIL         Input face is not good for recognition
-     */
-    int8_t align_face_rot(box_array_t *onet_boxes,
-                      dl_matrix3du_t *src,
-                      dl_matrix3du_t *dest);
-    
-    int8_t align_face_sim(box_array_t *onet_boxes,
-                   dl_matrix3du_t *src,
-                   dl_matrix3du_t *dest);
-    
-    inline int8_t align_face(box_array_t *onet_boxes,
-                       dl_matrix3du_t *src,
-                       dl_matrix3du_t *dest)
-    {
-        return align_face_sim(onet_boxes, src, dest);              
-    }
-    /**@}*/
-
-    /**
-     * @brief Run the face recognition model to get the face feature
-     * 
-     * @param aligned_face      A 56x56x3 image, the variable need to do align_face first
-     * @return face_id          A 512 vector, size (1, 1, 1, 512)
-     */
-    dl_matrix3d_t *get_face_id(dl_matrix3du_t *aligned_face);
-
-    /**
-     * @brief Add src_id to dest_id
-     * 
-     * @param dest_id       Face id after accumulation
-     * @param src_id        Face id to be added
-     */
-    void add_face_id(dl_matrix3d_t *dest_id,
-                     dl_matrix3d_t *src_id);
-
-    /**
-     * @brief Match face with the id_list, and return matched_id.
-     *
-     * @param l                     An ID list 
-     * @param algined_face          An aligned face
-     * @return int8_t               Matched face id
-     */
-    int8_t recognize_face(face_id_list *l, dl_matrix3du_t *algined_face);
-
-    /**
-     * @brief Match face id with the id_list, and return matched face id node.
-     * 
-     * @param l 
-     * @param face_id 
-     * @return face_id_node* 
-     */
-    face_id_node *recognize_face_with_name(face_id_name_list *l, dl_matrix3d_t *face_id);
-    
-    /**
-     * @brief Produce face id according to the input aligned face, and save it to dest_id.
-     * 
-     * @param l                     Face id list
-     * @param aligned_face          An aligned face
-     * @param enroll_confirm_times  Confirm times for each face id enrollment
-     * @return -1                   Wrong input enroll_confirm_times
-     * @return 0                    Enrollment finish
-     * @return >=1                  The left piece of aligned faces should be input
-     */
-    int8_t enroll_face(face_id_list *l, dl_matrix3du_t *aligned_face);
-
-    /**
-     * @brief Produce face id according to the input aligned face, and save the id-name pairs to dest_id
-     * 
-     * @param l                      Face id list with name 
-     * @param new_id                 A face id that need to be enrolled
-     * @param name                   name corresponding to the face id  
-     * @return int8_t                The left piece of aligned faces should be input
-     */
-    int8_t enroll_face_with_name(face_id_name_list *l,
-                                 dl_matrix3d_t *new_id,
-                                 char *name);
-
-    /**
-     * @brief Delete the enrolled face IDs
-     * 
-     * @param l            Face id list
-     * @return uint8_t     The number of IDs remaining in face id list
-     */
-    uint8_t delete_face(face_id_list *l);
-
-    /**
-     * @brief Delete the enrolled face IDs and associated names
-     * 
-     * @param l             Face id list
-     * @param name          The name that needs to be deleted
-     * @return int8_t       The number of IDs remaining in face id list
-     */
-    int8_t delete_face_with_name(face_id_name_list *l, char *name);
-    
-    /**
-     * @brief               Delete all the enrolled face IDs and names paris
-     * 
-     * @param l             Face id list with names
-     */
-    void delete_face_all_with_name(face_id_name_list *l);
-#if __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-face/frmn.h b/tools/sdk/include/esp-face/frmn.h
deleted file mode 100644
index c1f08a0fadc..00000000000
--- a/tools/sdk/include/esp-face/frmn.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#pragma once
-
-#if __cplusplus
-extern "C"
-{
-#endif
-
-#include "dl_lib_matrix3d.h"
-#include "dl_lib_matrix3dq.h"
-
-    /**
-     * @brief Forward the face recognition process with frmn model. Calculate in float.
-     *
-     * @param in    Image matrix, rgb888 format, size is 56x56, normalized
-     * @return dl_matrix3d_t* Face ID feature vector, size is 512
-     */
-    dl_matrix3d_t *frmn(dl_matrix3d_t *in);
-    
-    /**@{*/
-    /**
-     * @brief Forward the face recognition process with specified model. Calculate in quantization.
-     *
-     * @param in    Image matrix, rgb888 format, size is 56x56, normalized
-     * @param mode  0: C implement; 1: handwrite xtensa instruction implement
-     * @return      Face ID feature vector, size is 512
-     */
-    dl_matrix3dq_t *frmn_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    dl_matrix3dq_t *frmn2p_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    dl_matrix3dq_t *mfn56_42m_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    dl_matrix3dq_t *mfn56_72m_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    dl_matrix3dq_t *mfn56_112m_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    dl_matrix3dq_t *mfn56_156m_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    /**@}*/
-
-#if __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-face/hd_model.h b/tools/sdk/include/esp-face/hd_model.h
deleted file mode 100644
index 0bc28d70ddc..00000000000
--- a/tools/sdk/include/esp-face/hd_model.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#pragma once
-
-#if __cplusplus
-extern "C"
-{
-#endif
-
-#include "dl_lib_matrix3d.h"
-#include "dl_lib_matrix3dq.h"
-
-    typedef struct
-    {
-        int num;              /*!< The total number of the boxes */
-        dl_matrix3d_t *cls;   /*!< The class feature map corresponding to the box. size: (height, width, anchor_num, 1) */
-        dl_matrix3d_t *score; /*!< The confidence score feature map of the class corresponding to the box. size: (height, width, anchor_num, 1) */
-        dl_matrix3d_t *boxes; /*!< (x, y, w, h) of the boxes. x and y are the center coordinates. size:(height, width, anchor_num, 4) */
-    } detection_result_t;
-
-    /**
-     * @brief Forward the hand detection process with hd_nano1 model. Calculate in quantization.
-     * 
-     * @param in                      A normalized image matrix in rgb888 format, its width and height must be integer multiples of 16.
-     * @param mode                    0: C implement; 1: handwrite xtensa instruction implement
-     * @return detection_result_t**   Detection results
-     */
-    detection_result_t **hd_nano1_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    /**
-     * @brief Forward the hand detection process with hd_lite1 model. Calculate in quantization.
-     * 
-     * @param in                      A normalized image matrix in rgb888 format, its width and height must be integer multiples of 32.
-     * @param mode                    0: C implement; 1: handwrite xtensa instruction implement.
-     * @return detection_result_t**   Detection results.
-     */
-    detection_result_t **hd_lite1_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    /**
-     * @brief Free the single detection result.
-     * 
-     * @param m     The single detection result.
-     */
-    void detection_result_free(detection_result_t *m);
-
-    /**
-     * @brief Free the detection result group from different feature map.
-     * 
-     * @param m       The detection result group
-     * @param length  The number of the detection results
-     */
-    void detection_results_free(detection_result_t **m, int length);
-
-    /**
-     * @brief Test the result of hand detection model.
-     * 
-     */
-    void hd_test();
-
-    /**
-     * @brief Test the forward time of hand detection model.
-     * 
-     */
-    void hd_time_test();
-
-#if __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-face/hp_model.h b/tools/sdk/include/esp-face/hp_model.h
deleted file mode 100644
index ad9080c5473..00000000000
--- a/tools/sdk/include/esp-face/hp_model.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#pragma once
-
-#if __cplusplus
-extern "C"
-{
-#endif
-
-#include "dl_lib_matrix3d.h"
-#include "dl_lib_matrix3dq.h"
-
-    /**
-     * @brief Forward the hand pose estimation process with hp_nano1_ls16 model. Calculate in quantization.
-     * 
-     * @param in                 A normalized image matrix in rgb888 format, its size is (1, 128, 128, 3).
-     * @param mode               0: C implement; 1: handwrite xtensa instruction implement
-     * @return dl_matrix3d_t*    The resulting hand joint point coordinates, the size is (1, 1, 21, 2)
-     */
-    dl_matrix3d_t *hp_nano1_ls16_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    /**
-     * @brief Forward the hand pose estimation process with hp_lite1 model. Calculate in quantization.
-     * 
-     * @param in                 A normalized image matrix in rgb888 format, its size is (1, 128, 128, 3).
-     * @param mode               0: C implement; 1: handwrite xtensa instruction implement
-     * @return dl_matrix3d_t*    The resulting hand joint point coordinates, the size is (1, 1, 21, 2)
-     */
-    dl_matrix3d_t *hp_lite1_q(dl_matrix3dq_t *in, dl_conv_mode mode);
-
-    /**
-     * @brief Test the result of hand pose estimation model.
-     * 
-     */
-    void hp_test();
-
-    /**
-     * @brief Test the forward time of hand pose estimation model.
-     * 
-     */
-    void hp_time_test();
-
-#if __cplusplus
-}
-#endif
\ No newline at end of file
diff --git a/tools/sdk/include/esp-face/image_util.h b/tools/sdk/include/esp-face/image_util.h
deleted file mode 100644
index f997b34154b..00000000000
--- a/tools/sdk/include/esp-face/image_util.h
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
-  * ESPRESSIF MIT License
-  *
-  * Copyright (c) 2018 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
-  *
-  * Permission is hereby granted for use on ESPRESSIF SYSTEMS products only, in which case,
-  * it is free of charge, to any person obtaining a copy of this software and associated
-  * documentation files (the "Software"), to deal in the Software without restriction, including
-  * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
-  * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
-  * to do so, subject to the following conditions:
-  *
-  * The above copyright notice and this permission notice shall be included in all copies or
-  * substantial portions of the Software.
-  *
-  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
-#pragma once
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-#include <stdint.h>
-#include <math.h>
-#include "mtmn.h"
-
-#define LANDMARKS_NUM (10)
-
-#define MAX_VALID_COUNT_PER_IMAGE (30)
-
-#define DL_IMAGE_MIN(A, B) ((A) < (B) ? (A) : (B))
-#define DL_IMAGE_MAX(A, B) ((A) < (B) ? (B) : (A))
-
-#define RGB565_MASK_RED 0xF800
-#define RGB565_MASK_GREEN 0x07E0
-#define RGB565_MASK_BLUE 0x001F
-
-    typedef enum
-    {
-        BINARY, /*!< binary */
-    } en_threshold_mode;
-
-    typedef struct
-    {
-        fptp_t landmark_p[LANDMARKS_NUM]; /*!< landmark struct */
-    } landmark_t;
-
-    typedef struct
-    {
-        fptp_t box_p[4]; /*!< box struct */
-    } box_t;
-
-    typedef struct tag_box_list
-    {
-        uint8_t *category;    /*!< The category of the corresponding box */
-        fptp_t *score;        /*!< The confidence score of the class corresponding to the box */
-        box_t *box;           /*!< Anchor boxes or predicted boxes*/
-        landmark_t *landmark; /*!< The landmarks corresponding to the box */
-        int len;              /*!< The num of the boxes */
-    } box_array_t;
-
-    typedef struct tag_image_box
-    {
-        struct tag_image_box *next; /*!< Next image_box_t */
-        uint8_t category;
-        fptp_t score;        /*!< The confidence score of the class corresponding to the box */
-        box_t box;           /*!< Anchor boxes or predicted boxes */
-        box_t offset;        /*!< The predicted anchor-based offset */
-        landmark_t landmark; /*!< The landmarks corresponding to the box */
-    } image_box_t;
-
-    typedef struct tag_image_list
-    {
-        image_box_t *head;        /*!< The current head of the image_list */
-        image_box_t *origin_head; /*!< The original head of the image_list */
-        int len;                  /*!< Length of the image_list */
-    } image_list_t;
-
-    /**
-     * @brief Get the width and height of the box.
-     * 
-     * @param box         Input box
-     * @param w           Resulting width of the box
-     * @param h           Resulting height of the box
-     */
-    static inline void image_get_width_and_height(box_t *box, float *w, float *h)
-    {
-        *w = box->box_p[2] - box->box_p[0] + 1;
-        *h = box->box_p[3] - box->box_p[1] + 1;
-    }
-
-    /**
-     * @brief Get the area of the box.
-     * 
-     * @param box         Input box
-     * @param area        Resulting area of the box 
-     */
-    static inline void image_get_area(box_t *box, float *area)
-    {
-        float w, h;
-        image_get_width_and_height(box, &w, &h);
-        *area = w * h;
-    }
-
-    /**
-     * @brief calibrate the boxes by offset
-     * 
-     * @param image_list         Input boxes
-     * @param image_height       Height of the original image
-     * @param image_width        Width of the original image
-     */
-    static inline void image_calibrate_by_offset(image_list_t *image_list, int image_height, int image_width)
-    {
-        for (image_box_t *head = image_list->head; head; head = head->next)
-        {
-            float w, h;
-            image_get_width_and_height(&(head->box), &w, &h);
-            head->box.box_p[0] = DL_IMAGE_MAX(0, head->box.box_p[0] + head->offset.box_p[0] * w);
-            head->box.box_p[1] = DL_IMAGE_MAX(0, head->box.box_p[1] + head->offset.box_p[1] * w);
-            head->box.box_p[2] += head->offset.box_p[2] * w;
-            if (head->box.box_p[2] > image_width)
-            {
-                head->box.box_p[2] = image_width - 1;
-                head->box.box_p[0] = image_width - w;
-            }
-            head->box.box_p[3] += head->offset.box_p[3] * h;
-            if (head->box.box_p[3] > image_height)
-            {
-                head->box.box_p[3] = image_height - 1;
-                head->box.box_p[1] = image_height - h;
-            }
-        }
-    }
-
-    /**
-     * @brief calibrate the landmarks
-     * 
-     * @param image_list     Input landmarks
-     */
-    static inline void image_landmark_calibrate(image_list_t *image_list)
-    {
-        for (image_box_t *head = image_list->head; head; head = head->next)
-        {
-            float w, h;
-            image_get_width_and_height(&(head->box), &w, &h);
-            head->landmark.landmark_p[0] = head->box.box_p[0] + head->landmark.landmark_p[0] * w;
-            head->landmark.landmark_p[1] = head->box.box_p[1] + head->landmark.landmark_p[1] * h;
-
-            head->landmark.landmark_p[2] = head->box.box_p[0] + head->landmark.landmark_p[2] * w;
-            head->landmark.landmark_p[3] = head->box.box_p[1] + head->landmark.landmark_p[3] * h;
-
-            head->landmark.landmark_p[4] = head->box.box_p[0] + head->landmark.landmark_p[4] * w;
-            head->landmark.landmark_p[5] = head->box.box_p[1] + head->landmark.landmark_p[5] * h;
-
-            head->landmark.landmark_p[6] = head->box.box_p[0] + head->landmark.landmark_p[6] * w;
-            head->landmark.landmark_p[7] = head->box.box_p[1] + head->landmark.landmark_p[7] * h;
-
-            head->landmark.landmark_p[8] = head->box.box_p[0] + head->landmark.landmark_p[8] * w;
-            head->landmark.landmark_p[9] = head->box.box_p[1] + head->landmark.landmark_p[9] * h;
-        }
-    }
-
-    /**
-     * @brief Convert a rectangular box into a square box
-     * 
-     * @param boxes    Input box 
-     * @param width    Width of the orignal image
-     * @param height   height of the orignal image
-     */
-    static inline void image_rect2sqr(box_array_t *boxes, int width, int height)
-    {
-        for (int i = 0; i < boxes->len; i++)
-        {
-            box_t *box = &(boxes->box[i]);
-
-            int x1 = round(box->box_p[0]);
-            int y1 = round(box->box_p[1]);
-            int x2 = round(box->box_p[2]);
-            int y2 = round(box->box_p[3]);
-
-            int w = x2 - x1 + 1;
-            int h = y2 - y1 + 1;
-            int l = DL_IMAGE_MAX(w, h);
-
-            box->box_p[0] = DL_IMAGE_MAX(round(DL_IMAGE_MAX(0, x1) + 0.5 * (w - l)), 0);
-            box->box_p[1] = DL_IMAGE_MAX(round(DL_IMAGE_MAX(0, y1) + 0.5 * (h - l)), 0);
-
-            box->box_p[2] = box->box_p[0] + l - 1;
-            if (box->box_p[2] > width)
-            {
-                box->box_p[2] = width - 1;
-                box->box_p[0] = width - l;
-            }
-            box->box_p[3] = box->box_p[1] + l - 1;
-            if (box->box_p[3] > height)
-            {
-                box->box_p[3] = height - 1;
-                box->box_p[1] = height - l;
-            }
-        }
-    }
-
-    /**@{*/
-    /**
-     * @brief Convert RGB565 image to RGB888 image
-     * 
-     * @param in    Input RGB565 image
-     * @param dst   Resulting RGB888 image
-     */
-    static inline void rgb565_to_888(uint16_t in, uint8_t *dst)
-    { /*{{{*/
-        in = (in & 0xFF) << 8 | (in & 0xFF00) >> 8;
-        dst[2] = (in & RGB565_MASK_BLUE) << 3;  // blue
-        dst[1] = (in & RGB565_MASK_GREEN) >> 3; // green
-        dst[0] = (in & RGB565_MASK_RED) >> 8;   // red
-
-        // dst[0] = (in & 0x1F00) >> 5;
-        // dst[1] = ((in & 0x7) << 5) | ((in & 0xE000) >> 11);
-        // dst[2] = in & 0xF8;
-    } /*}}}*/
-
-    static inline void rgb565_to_888_q16(uint16_t in, int16_t *dst)
-    { /*{{{*/
-        in = (in & 0xFF) << 8 | (in & 0xFF00) >> 8;
-        dst[2] = (in & RGB565_MASK_BLUE) << 3;  // blue
-        dst[1] = (in & RGB565_MASK_GREEN) >> 3; // green
-        dst[0] = (in & RGB565_MASK_RED) >> 8;   // red
-
-        // dst[0] = (in & 0x1F00) >> 5;
-        // dst[1] = ((in & 0x7) << 5) | ((in & 0xE000) >> 11);
-        // dst[2] = in & 0xF8;
-    } /*}}}*/
-    /**@}*/
-
-    /**
-     * @brief Convert RGB888 image to RGB565 image
-     * 
-     * @param in      Resulting RGB565 image
-     * @param r       The red channel of the Input RGB888 image 
-     * @param g       The green channel of the Input RGB888 image 
-     * @param b       The blue channel of the Input RGB888 image
-     */
-    static inline void rgb888_to_565(uint16_t *in, uint8_t r, uint8_t g, uint8_t b)
-    { /*{{{*/
-        uint16_t rgb565 = 0;
-        rgb565 = ((r >> 3) << 11);
-        rgb565 |= ((g >> 2) << 5);
-        rgb565 |= (b >> 3);
-        rgb565 = (rgb565 & 0xFF) << 8 | (rgb565 & 0xFF00) >> 8;
-        *in = rgb565;
-    } /*}}}*/
-
-    /**
-     * @brief Filter out the resulting boxes whose confidence score is lower than the threshold and convert the boxes to the actual boxes on the original image.((x, y, w, h) -> (x1, y1, x2, y2))
-     * 
-     * @param score                    Confidence score of the boxes
-     * @param offset                   The predicted anchor-based offset
-     * @param landmark                 The landmarks corresponding to the box
-     * @param width                    Height of the original image
-     * @param height                   Width of the original image
-     * @param anchor_number            Anchor number of the detection output feature map 
-     * @param anchors_size             The anchor size
-     * @param score_threshold          Threshold of the confidence score
-     * @param stride 
-     * @param resized_height_scale 
-     * @param resized_width_scale 
-     * @param do_regression 
-     * @return image_list_t* 
-     */
-    image_list_t *image_get_valid_boxes(fptp_t *score,
-                                        fptp_t *offset,
-                                        fptp_t *landmark,
-                                        int width,
-                                        int height,
-                                        int anchor_number,
-                                        int *anchors_size,
-                                        fptp_t score_threshold,
-                                        int stride,
-                                        fptp_t resized_height_scale,
-                                        fptp_t resized_width_scale,
-                                        bool do_regression);
-    /**
-     * @brief Sort the resulting box lists by their confidence score.
-     * 
-     * @param image_sorted_list     The sorted box list.
-     * @param insert_list           The box list that have not been sorted.
-     */
-    void image_sort_insert_by_score(image_list_t *image_sorted_list, const image_list_t *insert_list);
-
-    /**
-     * @brief Run NMS algorithm 
-     * 
-     * @param image_list         The input boxes list
-     * @param nms_threshold      NMS threshold
-     * @param same_area          The flag of boxes with same area
-     */
-    void image_nms_process(image_list_t *image_list, fptp_t nms_threshold, int same_area);
-
-    /**
-     * @brief Resize an image to half size 
-     * 
-     * @param dimage      The output image
-     * @param dw          Width of the output image
-     * @param dh          Height of the output image
-     * @param dc          Channel of the output image
-     * @param simage      Source image
-     * @param sw          Width of the source image
-     * @param sc          Channel of the source image
-     */
-    void image_zoom_in_twice(uint8_t *dimage,
-                             int dw,
-                             int dh,
-                             int dc,
-                             uint8_t *simage,
-                             int sw,
-                             int sc);
-
-    /**
-     * @brief Resize the image in RGB888 format via bilinear interpolation
-     * 
-     * @param dst_image    The output image
-     * @param src_image    Source image
-     * @param dst_w        Width of the output image
-     * @param dst_h        Height of the output image
-     * @param dst_c        Channel of the output image
-     * @param src_w        Width of the source image
-     * @param src_h        Height of the source image
-     */
-    void image_resize_linear(uint8_t *dst_image, uint8_t *src_image, int dst_w, int dst_h, int dst_c, int src_w, int src_h);
-
-    /**
-     * @brief Crop， rotate and zoom the image in RGB888 format, 
-     * 
-     * @param corp_image       The output image
-     * @param src_image        Source image
-     * @param rotate_angle     Rotate angle
-     * @param ratio            scaling ratio
-     * @param center           Center of rotation
-     */
-    void image_cropper(uint8_t *corp_image, uint8_t *src_image, int dst_w, int dst_h, int dst_c, int src_w, int src_h, float rotate_angle, float ratio, float *center);
-
-    /**
-     * @brief Convert the rgb565 image to the rgb888 image   
-     * 
-     * @param m       The output rgb888 image
-     * @param bmp     The input rgb565 image
-     * @param count   Total pixels of the rgb565 image
-     */
-    void image_rgb565_to_888(uint8_t *m, uint16_t *bmp, int count);
-
-    /**
-     * @brief Convert the rgb888 image to the rgb565 image
-     * 
-     * @param bmp     The output rgb565 image
-     * @param m       The input rgb888 image
-     * @param count   Total pixels of the rgb565 image
-     */
-    void image_rgb888_to_565(uint16_t *bmp, uint8_t *m, int count);
-
-    /**
-     * @brief draw rectangle on the rgb565 image
-     * 
-     * @param buf     Input image
-     * @param boxes   Rectangle Boxes
-     * @param width   Width of the input image
-     */
-    void draw_rectangle_rgb565(uint16_t *buf, box_array_t *boxes, int width);
-
-    /**
-     * @brief draw rectangle on the rgb888 image
-     * 
-     * @param buf     Input image
-     * @param boxes   Rectangle Boxes
-     * @param width   Width of the input image
-     */
-    void draw_rectangle_rgb888(uint8_t *buf, box_array_t *boxes, int width);
-
-    /**
-     * @brief Get the pixel difference of two images
-     * 
-     * @param dst       The output pixel difference
-     * @param src1      Input image 1
-     * @param src2      Input image 2
-     * @param count     Total pixels of the input image
-     */
-    void image_abs_diff(uint8_t *dst, uint8_t *src1, uint8_t *src2, int count);
-
-    /**
-     * @brief Binarize an image to 0 and value. 
-     * 
-     * @param dst           The output image
-     * @param src           Source image
-     * @param threshold     Threshold of binarization
-     * @param value         The value of binarization
-     * @param count         Total pixels of the input image
-     * @param mode          Threshold mode
-     */
-    void image_threshold(uint8_t *dst, uint8_t *src, int threshold, int value, int count, en_threshold_mode mode);
-
-    /**
-     * @brief Erode the image
-     * 
-     * @param dst          The output image
-     * @param src          Source image
-     * @param src_w        Width of the source image
-     * @param src_h        Height of the source image
-     * @param src_c        Channel of the source image
-     */
-    void image_erode(uint8_t *dst, uint8_t *src, int src_w, int src_h, int src_c);
-
-    typedef float matrixType;
-    typedef struct
-    {
-        int w;              /*!< width */
-        int h;              /*!< height */
-        matrixType **array; /*!< array */
-    } Matrix;
-
-    /**
-     * @brief Allocate a 2d matrix
-     * 
-     * @param h                Height of matrix
-     * @param w                Width of matrix
-     * @return Matrix*         2d matrix
-     */
-    Matrix *matrix_alloc(int h, int w);
-
-    /**
-     * @brief Free a 2d matrix
-     * 
-     * @param m    2d matrix 
-     */
-    void matrix_free(Matrix *m);
-
-    /**
-     * @brief Get the similarity matrix of similarity transformation
-     * 
-     * @param srcx          Source x coordinates
-     * @param srcy          Source y coordinates
-     * @param dstx          Destination x coordinates
-     * @param dsty          Destination y coordinates
-     * @param num           The number of the coordinates
-     * @return Matrix*      The resulting transformation matrix
-     */
-    Matrix *get_similarity_matrix(float *srcx, float *srcy, float *dstx, float *dsty, int num);
-
-    /**
-     * @brief Get the affine transformation matrix
-     * 
-     * @param srcx          Source x coordinates
-     * @param srcy          Source y coordinates
-     * @param dstx          Destination x coordinates
-     * @param dsty          Destination y coordinates
-     * @return Matrix*      The resulting transformation matrix
-     */
-    Matrix *get_affine_transform(float *srcx, float *srcy, float *dstx, float *dsty);
-
-    /**
-     * @brief Applies an affine transformation to an image
-     * 
-     * @param img           Input image
-     * @param crop          Dst output image that has the size dsize and the same type as src
-     * @param M             Affine transformation matrix
-     */
-    void warp_affine(dl_matrix3du_t *img, dl_matrix3du_t *crop, Matrix *M);
-
-    /**
-     * @brief Resize the image in RGB888 format via bilinear interpolation, and quantify the output image
-     * 
-     * @param dst_image            Quantized output image
-     * @param src_image            Input image 
-     * @param dst_w                Width of the output image 
-     * @param dst_h                Height of the output image 
-     * @param dst_c                Channel of the output image
-     * @param src_w                Width of the input image 
-     * @param src_h                Height of the input image
-     * @param shift                Shift parameter of quantization.
-     */
-    void image_resize_linear_q(qtp_t *dst_image, uint8_t *src_image, int dst_w, int dst_h, int dst_c, int src_w, int src_h, int shift);
-
-    /**
-     * @brief Preprocess the input image of object detection model. The process is like this: resize -> normalize -> quantify
-     * 
-     * @param image                 Input image, RGB888 format.
-     * @param input_w               Width of the input image.
-     * @param input_h               Height of the input image.
-     * @param target_size           Target size of the model input image.
-     * @param exponent              Exponent of the quantized model input image.
-     * @param process_mode          Process mode. 0: resize with padding to keep height == width. 1: resize without padding, height != width.  
-     * @return dl_matrix3dq_t*      The resulting preprocessed image.
-     */
-    dl_matrix3dq_t *image_resize_normalize_quantize(uint8_t *image, int input_w, int input_h, int target_size, int exponent, int process_mode);
-
-    /**
-     * @brief Resize the image in RGB565 format via mean neighbour interpolation, and quantify the output image
-     * 
-     * @param dimage            Quantized output image. 
-     * @param simage            Input image.  
-     * @param dw                Width of the allocated output image memory.
-     * @param dc                Channel of the allocated output image memory.
-     * @param sw                Width of the input image. 
-     * @param sh                Height of the input image. 
-     * @param tw                Target width of the output image.
-     * @param th                Target height of the output image.
-     * @param shift             Shift parameter of quantization.
-     */
-    void image_resize_shift_fast(qtp_t *dimage, uint16_t *simage, int dw, int dc, int sw, int sh, int tw, int th, int shift);
-
-    /**
-     * @brief Resize the image in RGB565 format via nearest neighbour interpolation, and quantify the output image
-     * 
-     * @param dimage            Quantized output image. 
-     * @param simage            Input image.  
-     * @param dw                Width of the allocated output image memory.
-     * @param dc                Channel of the allocated output image memory.
-     * @param sw                Width of the input image. 
-     * @param sh                Height of the input image. 
-     * @param tw                Target width of the output image.
-     * @param th                Target height of the output image.
-     * @param shift             Shift parameter of quantization.
-     */
-    void image_resize_nearest_shift(qtp_t *dimage, uint16_t *simage, int dw, int dc, int sw, int sh, int tw, int th, int shift);
-
-    /**
-     * @brief Crop the image in RGB565 format and resize it to target size, then quantify the output image 
-     * 
-     * @param dimage            Quantized output image. 
-     * @param simage            Input image.
-     * @param dw                Target size of the output image.
-     * @param sw                Width of the input image. 
-     * @param sh                Height of the input image. 
-     * @param x1                The x coordinate of the upper left corner of the cropped area
-     * @param y1                The y coordinate of the upper left corner of the cropped area
-     * @param x2                The x coordinate of the lower right corner of the cropped area
-     * @param y2                The y coordinate of the lower right corner of the cropped area
-     * @param shift             Shift parameter of quantization.
-     */
-    void image_crop_shift_fast(qtp_t *dimage, uint16_t *simage, int dw, int sw, int sh, int x1, int y1, int x2, int y2, int shift);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-face/lssh.h b/tools/sdk/include/esp-face/lssh.h
deleted file mode 100644
index 69c661c58e5..00000000000
--- a/tools/sdk/include/esp-face/lssh.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
-  * ESPRESSIF MIT License
-  *
-  * Copyright (c) 2018 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
-  *
-  * Permission is hereby granted for use on ESPRESSIF SYSTEMS products only, in which case,
-  * it is free of charge, to any person obtaining a copy of this software and associated
-  * documentation files (the "Software"), to deal in the Software without restriction, including
-  * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
-  * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
-  * to do so, subject to the following conditions:
-  *
-  * The above copyright notice and this permission notice shall be included in all copies or
-  * substantial portions of the Software.
-  *
-  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
-#pragma once
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-#include "dl_lib_matrix3d.h"
-#include "dl_lib_matrix3dq.h"
-#include "freertos/FreeRTOS.h"
-
-    typedef struct
-    {
-        int resized_height;
-        int resized_width;
-        fptp_t y_resize_scale;
-        fptp_t x_resize_scale;
-        int enabled_top_k;
-        fptp_t score_threshold;
-        fptp_t nms_threshold;
-
-        dl_conv_mode mode;
-    } lssh_config_t;
-
-    typedef struct
-    {
-        int *anchor_size;
-        int stride;
-        int boundary;
-    } lssh_module_config_t;
-
-    typedef struct
-    {
-        lssh_module_config_t *module_config;
-        int number;
-    } lssh_modules_config_t;
-
-    typedef struct
-    {
-        dl_matrix3d_t *category;
-        dl_matrix3d_t *box_offset;
-        dl_matrix3d_t *landmark_offset;
-    } lssh_module_result_t;
-
-    /**
-     * @brief 
-     * 
-     * @param value 
-     */
-    void lssh_module_result_free(lssh_module_result_t value);
-
-    /**
-     * @brief 
-     * 
-     * @param values 
-     * @param length 
-     */
-    void lssh_module_results_free(lssh_module_result_t *values, int length);
-
-    /////////////////////////
-    //////sparse_mn_5_q//////
-    /////////////////////////
-    extern lssh_modules_config_t sparse_mn_5_modules_config;
-    lssh_module_result_t *sparse_mn_5_q_without_landmark(dl_matrix3du_t *image, bool free_image, int enabled_top_k, dl_conv_mode mode);
-    lssh_module_result_t *sparse_mn_5_q_with_landmark(dl_matrix3du_t *image, bool free_image, int enabled_top_k, dl_conv_mode mode);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-face/mtmn.h b/tools/sdk/include/esp-face/mtmn.h
deleted file mode 100644
index 609a82ea488..00000000000
--- a/tools/sdk/include/esp-face/mtmn.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
-  * ESPRESSIF MIT License
-  *
-  * Copyright (c) 2018 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
-  *
-  * Permission is hereby granted for use on ESPRESSIF SYSTEMS products only, in which case,
-  * it is free of charge, to any person obtaining a copy of this software and associated
-  * documentation files (the "Software"), to deal in the Software without restriction, including
-  * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
-  * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
-  * to do so, subject to the following conditions:
-  *
-  * The above copyright notice and this permission notice shall be included in all copies or
-  * substantial portions of the Software.
-  *
-  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-  *
-  */
-#pragma once
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-#include "dl_lib_matrix3d.h"
-#include "dl_lib_matrix3dq.h"
-
-    /**
-     * Detection results with MTMN.
-     *
-     */
-    typedef struct
-    {
-        dl_matrix3d_t *category;    /*!< Classification result after softmax, channel is 2 */
-        dl_matrix3d_t *offset;      /*!< Bounding box offset of 2 points: top-left and bottom-right, channel is 4 */
-        dl_matrix3d_t *landmark;    /*!< Offsets of 5 landmarks:
-                                     * - Left eye
-                                     * - Mouth leftside
-                                     * - Nose
-                                     * - Right eye
-                                     * - Mouth rightside
-                                     *
-                                     * channel is 10
-                                     * */
-    } mtmn_net_t;
-
-
-    /**
-     * @brief Free a mtmn_net_t
-     *
-     * @param p         A mtmn_net_t pointer
-     *
-     */
-
-    void mtmn_net_t_free(mtmn_net_t *p);
-
-    /**
-     * @brief Forward the pnet process, coarse detection. Calculate in float.
-     *
-     * @param in        Image matrix, rgb888 format, size is 320x240
-     * @return          Scores for every pixel, and box offset with respect.
-     */
-    mtmn_net_t *pnet_lite_f(dl_matrix3du_t *in);
-
-    /**
-     * @brief Forward the rnet process, fine determine the boxes from pnet. Calculate in float.
-     *
-     * @param in        Image matrix, rgb888 format
-     * @param threshold Score threshold to detect human face
-     * @return          Scores for every box, and box offset with respect.
-     */
-    mtmn_net_t *rnet_lite_f_with_score_verify(dl_matrix3du_t *in, float threshold);
-
-    /**
-     * @brief Forward the onet process, fine determine the boxes from rnet. Calculate in float.
-     *
-     * @param in        Image matrix, rgb888 format
-     * @param threshold Score threshold to detect human face
-     * @return          Scores for every box, box offset, and landmark with respect.
-     */
-    mtmn_net_t *onet_lite_f_with_score_verify(dl_matrix3du_t *in, float threshold);
-
-    /**
-     * @brief Forward the pnet process, coarse detection. Calculate in quantization.
-     *
-     * @param in        Image matrix, rgb888 format, size is 320x240
-     * @return          Scores for every pixel, and box offset with respect.
-     */
-    mtmn_net_t *pnet_lite_q(dl_matrix3du_t *in, dl_conv_mode mode);
-
-    /**
-     * @brief Forward the rnet process, fine determine the boxes from pnet. Calculate in quantization.
-     *
-     * @param in        Image matrix, rgb888 format
-     * @param threshold Score threshold to detect human face
-     * @return          Scores for every box, and box offset with respect.
-     */
-    mtmn_net_t *rnet_lite_q_with_score_verify(dl_matrix3du_t *in, float threshold, dl_conv_mode mode);
-
-    /**
-     * @brief Forward the onet process, fine determine the boxes from rnet. Calculate in quantization.
-     *
-     * @param in        Image matrix, rgb888 format
-     * @param threshold Score threshold to detect human face
-     * @return          Scores for every box, box offset, and landmark with respect.
-     */
-    mtmn_net_t *onet_lite_q_with_score_verify(dl_matrix3du_t *in, float threshold, dl_conv_mode mode);
-
-    /**
-     * @brief Forward the pnet process, coarse detection. Calculate in quantization.
-     *
-     * @param in        Image matrix, rgb888 format, size is 320x240
-     * @return          Scores for every pixel, and box offset with respect.
-     */
-    mtmn_net_t *pnet_heavy_q(dl_matrix3du_t *in, dl_conv_mode mode);
-
-    /**
-     * @brief Forward the rnet process, fine determine the boxes from pnet. Calculate in quantization.
-     *
-     * @param in        Image matrix, rgb888 format
-     * @param threshold Score threshold to detect human face
-     * @return          Scores for every box, and box offset with respect.
-     */
-    mtmn_net_t *rnet_heavy_q_with_score_verify(dl_matrix3du_t *in, float threshold, dl_conv_mode mode);
-
-    /**
-     * @brief Forward the onet process, fine determine the boxes from rnet. Calculate in quantization.
-     *
-     * @param in        Image matrix, rgb888 format
-     * @param threshold Score threshold to detect human face
-     * @return          Scores for every box, box offset, and landmark with respect.
-     */
-    mtmn_net_t *onet_heavy_q_with_score_verify(dl_matrix3du_t *in, float threshold, dl_conv_mode mode);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp-tls/esp_tls.h b/tools/sdk/include/esp-tls/esp_tls.h
deleted file mode 100644
index a1cceabe88e..00000000000
--- a/tools/sdk/include/esp-tls/esp_tls.h
+++ /dev/null
@@ -1,330 +0,0 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_TLS_H_
-#define _ESP_TLS_H_
-
-#include <stdbool.h>
-#include <sys/socket.h>
-#include <fcntl.h>
-#include "esp_err.h"
-
-#include "mbedtls/platform.h"
-#include "mbedtls/net_sockets.h"
-#include "mbedtls/esp_debug.h"
-#include "mbedtls/ssl.h"
-#include "mbedtls/entropy.h"
-#include "mbedtls/ctr_drbg.h"
-#include "mbedtls/error.h"
-#include "mbedtls/certs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *  @brief ESP-TLS Connection State
- */
-typedef enum esp_tls_conn_state {
-    ESP_TLS_INIT = 0,
-    ESP_TLS_CONNECTING,
-    ESP_TLS_HANDSHAKE,
-    ESP_TLS_FAIL,
-    ESP_TLS_DONE,
-} esp_tls_conn_state_t;
-
-/**
- * @brief      ESP-TLS configuration parameters 
- */ 
-typedef struct esp_tls_cfg {
-    const char **alpn_protos;               /*!< Application protocols required for HTTP2.
-                                                 If HTTP2/ALPN support is required, a list
-                                                 of protocols that should be negotiated. 
-                                                 The format is length followed by protocol
-                                                 name. 
-                                                 For the most common cases the following is ok:
-                                                 "\x02h2"
-                                                 - where the first '2' is the length of the protocol and
-                                                 - the subsequent 'h2' is the protocol name */
- 
-    const unsigned char *cacert_pem_buf;    /*!< Certificate Authority's certificate in a buffer.
-                                                 This buffer should be NULL terminated */
- 
-    unsigned int cacert_pem_bytes;          /*!< Size of Certificate Authority certificate
-                                                 pointed to by cacert_pem_buf */
-
-    const unsigned char *clientcert_pem_buf;/*!< Client certificate in a buffer
-                                                 This buffer should be NULL terminated */
- 
-    unsigned int clientcert_pem_bytes;      /*!< Size of client certificate pointed to by
-                                                 clientcert_pem_buf */
-
-    const unsigned char *clientkey_pem_buf; /*!< Client key in a buffer
-                                                 This buffer should be NULL terminated */
-
-    unsigned int clientkey_pem_bytes;       /*!< Size of client key pointed to by
-                                                 clientkey_pem_buf */
-
-    const unsigned char *clientkey_password;/*!< Client key decryption password string */
-
-    unsigned int clientkey_password_len;    /*!< String length of the password pointed to by
-                                                 clientkey_password */
-
-    bool non_block;                         /*!< Configure non-blocking mode. If set to true the 
-                                                 underneath socket will be configured in non 
-                                                 blocking mode after tls session is established */
-
-    int timeout_ms;                         /*!< Network timeout in milliseconds */
-
-    bool use_global_ca_store;               /*!< Use a global ca_store for all the connections in which
-                                                 this bool is set. */
-
-    const char *common_name;                /*!< If non-NULL, server certificate CN must match this name.
-                                                 If NULL, server certificate CN must match hostname. */
-
-    bool skip_common_name;                  /*!< Skip any validation of server certificate CN field */
-} esp_tls_cfg_t;
-
-/**
- * @brief      ESP-TLS Connection Handle 
- */
-typedef struct esp_tls {
-    mbedtls_ssl_context ssl;                                                    /*!< TLS/SSL context */
- 
-    mbedtls_entropy_context entropy;                                            /*!< mbedTLS entropy context structure */
- 
-    mbedtls_ctr_drbg_context ctr_drbg;                                          /*!< mbedTLS ctr drbg context structure.
-                                                                                     CTR_DRBG is deterministic random 
-                                                                                     bit generation based on AES-256 */
- 
-    mbedtls_ssl_config conf;                                                    /*!< TLS/SSL configuration to be shared 
-                                                                                     between mbedtls_ssl_context 
-                                                                                     structures */
- 
-    mbedtls_net_context server_fd;                                              /*!< mbedTLS wrapper type for sockets */
- 
-    mbedtls_x509_crt cacert;                                                    /*!< Container for the X.509 CA certificate */
-
-    mbedtls_x509_crt *cacert_ptr;                                               /*!< Pointer to the cacert being used. */
-
-    mbedtls_x509_crt clientcert;                                                /*!< Container for the X.509 client certificate */
-
-    mbedtls_pk_context clientkey;                                               /*!< Container for the private key of the client
-                                                                                     certificate */
-
-    int sockfd;                                                                 /*!< Underlying socket file descriptor. */
- 
-    ssize_t (*read)(struct esp_tls  *tls, char *data, size_t datalen);          /*!< Callback function for reading data from TLS/SSL
-                                                                                     connection. */
- 
-    ssize_t (*write)(struct esp_tls *tls, const char *data, size_t datalen);    /*!< Callback function for writing data to TLS/SSL
-                                                                                     connection. */
-
-    esp_tls_conn_state_t  conn_state;                                           /*!< ESP-TLS Connection state */
-
-    fd_set rset;                                                                /*!< read file descriptors */
-
-    fd_set wset;                                                                /*!< write file descriptors */
-} esp_tls_t;
-
-/**
- * @brief      Create a new blocking TLS/SSL connection
- *
- * This function establishes a TLS/SSL connection with the specified host in blocking manner.
- * 
- * @param[in]  hostname  Hostname of the host.
- * @param[in]  hostlen   Length of hostname.
- * @param[in]  port      Port number of the host.
- * @param[in]  cfg       TLS configuration as esp_tls_cfg_t. If you wish to open 
- *                       non-TLS connection, keep this NULL. For TLS connection,
- *                       a pass pointer to esp_tls_cfg_t. At a minimum, this
- *                       structure should be zero-initialized.
- * @return pointer to esp_tls_t, or NULL if connection couldn't be opened.
- */
-esp_tls_t *esp_tls_conn_new(const char *hostname, int hostlen, int port, const esp_tls_cfg_t *cfg);
-
-/**
- * @brief      Create a new blocking TLS/SSL connection with a given "HTTP" url
- *
- * The behaviour is same as esp_tls_conn_new() API. However this API accepts host's url.
- * 
- * @param[in]  url  url of host.
- * @param[in]  cfg  TLS configuration as esp_tls_cfg_t. If you wish to open
- *                  non-TLS connection, keep this NULL. For TLS connection,
- *                  a pass pointer to 'esp_tls_cfg_t'. At a minimum, this
- *                  structure should be zero-initialized.
- * @return pointer to esp_tls_t, or NULL if connection couldn't be opened.
- */
-esp_tls_t *esp_tls_conn_http_new(const char *url, const esp_tls_cfg_t *cfg);
-   
-/**
- * @brief      Create a new non-blocking TLS/SSL connection
- *
- * This function initiates a non-blocking TLS/SSL connection with the specified host, but due to
- * its non-blocking nature, it doesn't wait for the connection to get established.
- *
- * @param[in]  hostname  Hostname of the host.
- * @param[in]  hostlen   Length of hostname.
- * @param[in]  port      Port number of the host.
- * @param[in]  cfg       TLS configuration as esp_tls_cfg_t. `non_block` member of
- *                       this structure should be set to be true.
- * @param[in]  tls       pointer to esp-tls as esp-tls handle.
- *
- * @return
- *             - -1      If connection establishment fails.
- *             -  0      If connection establishment is in progress.
- *             -  1      If connection establishment is successful.
- */
-int esp_tls_conn_new_async(const char *hostname, int hostlen, int port, const esp_tls_cfg_t *cfg, esp_tls_t *tls);
-
-/**
- * @brief      Create a new non-blocking TLS/SSL connection with a given "HTTP" url
- *
- * The behaviour is same as esp_tls_conn_new() API. However this API accepts host's url.
- *
- * @param[in]  url     url of host.
- * @param[in]  cfg     TLS configuration as esp_tls_cfg_t.
- * @param[in]  tls     pointer to esp-tls as esp-tls handle.
- *
- * @return
- *             - -1     If connection establishment fails.
- *             -  0     If connection establishment is in progress.
- *             -  1     If connection establishment is successful.
- */
-int esp_tls_conn_http_new_async(const char *url, const esp_tls_cfg_t *cfg, esp_tls_t *tls);
-
-/**
- * @brief      Write from buffer 'data' into specified tls connection.
- * 
- * @param[in]  tls      pointer to esp-tls as esp-tls handle.
- * @param[in]  data     Buffer from which data will be written.
- * @param[in]  datalen  Length of data buffer.
- * 
- * @return 
- *             - >0  if write operation was successful, the return value is the number 
- *                   of bytes actually written to the TLS/SSL connection.  
- *             -  0  if write operation was not successful. The underlying
- *                   connection was closed.
- *             - <0  if write operation was not successful, because either an 
- *                   error occured or an action must be taken by the calling process.   
- */
-static inline ssize_t esp_tls_conn_write(esp_tls_t *tls, const void *data, size_t datalen)
-{
-    return tls->write(tls, (char *)data, datalen);
-}
-
-/**
- * @brief      Read from specified tls connection into the buffer 'data'.
- * 
- * @param[in]  tls      pointer to esp-tls as esp-tls handle.
- * @param[in]  data     Buffer to hold read data.
- * @param[in]  datalen  Length of data buffer. 
- *
- * @return
- *             - >0  if read operation was successful, the return value is the number
- *                   of bytes actually read from the TLS/SSL connection.
- *             -  0  if read operation was not successful. The underlying
- *                   connection was closed.
- *             - <0  if read operation was not successful, because either an
- *                   error occured or an action must be taken by the calling process.
- */
-static inline ssize_t esp_tls_conn_read(esp_tls_t *tls, void  *data, size_t datalen)
-{
-    return tls->read(tls, (char *)data, datalen);
-}
-
-/**
- * @brief      Close the TLS/SSL connection and free any allocated resources.
- * 
- * This function should be called to close each tls connection opened with esp_tls_conn_new() or
- * esp_tls_conn_http_new() APIs. 
- *
- * @param[in]  tls  pointer to esp-tls as esp-tls handle.    
- */
-void esp_tls_conn_delete(esp_tls_t *tls);
-
-/**
- * @brief      Return the number of application data bytes remaining to be
- *             read from the current record
- *
- * This API is a wrapper over mbedtls's mbedtls_ssl_get_bytes_avail() API.
- *
- * @param[in]  tls  pointer to esp-tls as esp-tls handle.
- *
- * @return
- *            - -1  in case of invalid arg
- *            - bytes available in the application data
- *              record read buffer
- */
-size_t esp_tls_get_bytes_avail(esp_tls_t *tls);
-
-/**
- * @brief      Create a global CA store, initially empty.
- *
- * This function should be called if the application wants to use the same CA store for multiple connections.
- * This function initialises the global CA store which can be then set by calling esp_tls_set_global_ca_store().
- * To be effective, this function must be called before any call to esp_tls_set_global_ca_store().
- *
- * @return
- *             - ESP_OK             if creating global CA store was successful.
- *             - ESP_ERR_NO_MEM     if an error occured when allocating the mbedTLS resources.
- */
-esp_err_t esp_tls_init_global_ca_store();
-
-/**
- * @brief      Set the global CA store with the buffer provided in pem format.
- *
- * This function should be called if the application wants to set the global CA store for
- * multiple connections i.e. to add the certificates in the provided buffer to the certificate chain.
- * This function implicitly calls esp_tls_init_global_ca_store() if it has not already been called.
- * The application must call this function before calling esp_tls_conn_new().
- *
- * @param[in]  cacert_pem_buf    Buffer which has certificates in pem format. This buffer
- *                               is used for creating a global CA store, which can be used
- *                               by other tls connections.
- * @param[in]  cacert_pem_bytes  Length of the buffer.
- *
- * @return
- *             - ESP_OK  if adding certificates was successful.
- *             - Other   if an error occured or an action must be taken by the calling process.
- */
-esp_err_t esp_tls_set_global_ca_store(const unsigned char *cacert_pem_buf, const unsigned int cacert_pem_bytes);
-
-/**
- * @brief      Get the pointer to the global CA store currently being used.
- *
- * The application must first call esp_tls_set_global_ca_store(). Then the same
- * CA store could be used by the application for APIs other than esp_tls.
- *
- * @note       Modifying the pointer might cause a failure in verifying the certificates.
- *
- * @return
- *             - Pointer to the global CA store currently being used    if successful.
- *             - NULL                                                   if there is no global CA store set.
- */
-mbedtls_x509_crt *esp_tls_get_global_ca_store();
-
-/**
- * @brief      Free the global CA store currently being used.
- *
- * The memory being used by the global CA store to store all the parsed certificates is
- * freed up. The application can call this API if it no longer needs the global CA store.
- */
-void esp_tls_free_global_ca_store();
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! _ESP_TLS_H_ */
diff --git a/tools/sdk/include/esp32-camera/esp_camera.h b/tools/sdk/include/esp32-camera/esp_camera.h
deleted file mode 100755
index dadd0c0983f..00000000000
--- a/tools/sdk/include/esp32-camera/esp_camera.h
+++ /dev/null
@@ -1,195 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-/*
- * Example Use
- *
-    static camera_config_t camera_example_config = {
-        .pin_pwdn       = PIN_PWDN,
-        .pin_reset      = PIN_RESET,
-        .pin_xclk       = PIN_XCLK,
-        .pin_sscb_sda   = PIN_SIOD,
-        .pin_sscb_scl   = PIN_SIOC,
-        .pin_d7         = PIN_D7,
-        .pin_d6         = PIN_D6,
-        .pin_d5         = PIN_D5,
-        .pin_d4         = PIN_D4,
-        .pin_d3         = PIN_D3,
-        .pin_d2         = PIN_D2,
-        .pin_d1         = PIN_D1,
-        .pin_d0         = PIN_D0,
-        .pin_vsync      = PIN_VSYNC,
-        .pin_href       = PIN_HREF,
-        .pin_pclk       = PIN_PCLK,
-
-        .xclk_freq_hz   = 20000000,
-        .ledc_timer     = LEDC_TIMER_0,
-        .ledc_channel   = LEDC_CHANNEL_0,
-        .pixel_format   = PIXFORMAT_JPEG,
-        .frame_size     = FRAMESIZE_SVGA,
-        .jpeg_quality   = 10,
-        .fb_count       = 2
-    };
-
-    esp_err_t camera_example_init(){
-        return esp_camera_init(&camera_example_config);
-    }
-
-    esp_err_t camera_example_capture(){
-        //capture a frame
-        camera_fb_t * fb = esp_camera_fb_get();
-        if (!fb) {
-            ESP_LOGE(TAG, "Frame buffer could not be acquired");
-            return ESP_FAIL;
-        }
-
-        //replace this with your own function
-        display_image(fb->width, fb->height, fb->pixformat, fb->buf, fb->len);
-
-        //return the frame buffer back to be reused
-        esp_camera_fb_return(fb);
-
-        return ESP_OK;
-    }
-*/
-
-#pragma once
-
-#include "esp_err.h"
-#include "driver/ledc.h"
-#include "sensor.h"
-#include "sys/time.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Configuration structure for camera initialization
- */
-typedef struct {
-    int pin_pwdn;                   /*!< GPIO pin for camera power down line */
-    int pin_reset;                  /*!< GPIO pin for camera reset line */
-    int pin_xclk;                   /*!< GPIO pin for camera XCLK line */
-    int pin_sscb_sda;               /*!< GPIO pin for camera SDA line */
-    int pin_sscb_scl;               /*!< GPIO pin for camera SCL line */
-    int pin_d7;                     /*!< GPIO pin for camera D7 line */
-    int pin_d6;                     /*!< GPIO pin for camera D6 line */
-    int pin_d5;                     /*!< GPIO pin for camera D5 line */
-    int pin_d4;                     /*!< GPIO pin for camera D4 line */
-    int pin_d3;                     /*!< GPIO pin for camera D3 line */
-    int pin_d2;                     /*!< GPIO pin for camera D2 line */
-    int pin_d1;                     /*!< GPIO pin for camera D1 line */
-    int pin_d0;                     /*!< GPIO pin for camera D0 line */
-    int pin_vsync;                  /*!< GPIO pin for camera VSYNC line */
-    int pin_href;                   /*!< GPIO pin for camera HREF line */
-    int pin_pclk;                   /*!< GPIO pin for camera PCLK line */
-
-    int xclk_freq_hz;               /*!< Frequency of XCLK signal, in Hz. Either 20KHz or 10KHz for OV2640 double FPS (Experimental) */
-
-    ledc_timer_t ledc_timer;        /*!< LEDC timer to be used for generating XCLK  */
-    ledc_channel_t ledc_channel;    /*!< LEDC channel to be used for generating XCLK  */
-
-    pixformat_t pixel_format;       /*!< Format of the pixel data: PIXFORMAT_ + YUV422|GRAYSCALE|RGB565|JPEG  */
-    framesize_t frame_size;         /*!< Size of the output image: FRAMESIZE_ + QVGA|CIF|VGA|SVGA|XGA|SXGA|UXGA  */
-
-    int jpeg_quality;               /*!< Quality of JPEG output. 0-63 lower means higher quality  */
-    size_t fb_count;                /*!< Number of frame buffers to be allocated. If more than one, then each frame will be acquired (double speed)  */
-} camera_config_t;
-
-/**
- * @brief Data structure of camera frame buffer
- */
-typedef struct {
-    uint8_t * buf;              /*!< Pointer to the pixel data */
-    size_t len;                 /*!< Length of the buffer in bytes */
-    size_t width;               /*!< Width of the buffer in pixels */
-    size_t height;              /*!< Height of the buffer in pixels */
-    pixformat_t format;         /*!< Format of the pixel data */
-    struct timeval timestamp;   /*!< Timestamp since boot of the first DMA buffer of the frame */
-} camera_fb_t;
-
-#define ESP_ERR_CAMERA_BASE 0x20000
-#define ESP_ERR_CAMERA_NOT_DETECTED             (ESP_ERR_CAMERA_BASE + 1)
-#define ESP_ERR_CAMERA_FAILED_TO_SET_FRAME_SIZE (ESP_ERR_CAMERA_BASE + 2)
-#define ESP_ERR_CAMERA_FAILED_TO_SET_OUT_FORMAT (ESP_ERR_CAMERA_BASE + 3)
-#define ESP_ERR_CAMERA_NOT_SUPPORTED            (ESP_ERR_CAMERA_BASE + 4)
-
-/**
- * @brief Initialize the camera driver
- *
- * @note call camera_probe before calling this function
- *
- * This function detects and configures camera over I2C interface,
- * allocates framebuffer and DMA buffers,
- * initializes parallel I2S input, and sets up DMA descriptors.
- *
- * Currently this function can only be called once and there is
- * no way to de-initialize this module.
- *
- * @param config  Camera configuration parameters
- *
- * @return ESP_OK on success
- */
-esp_err_t esp_camera_init(const camera_config_t* config);
-
-/**
- * @brief Deinitialize the camera driver
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if the driver hasn't been initialized yet
- */
-esp_err_t esp_camera_deinit();
-
-/**
- * @brief Obtain pointer to a frame buffer.
- *
- * @return pointer to the frame buffer
- */
-camera_fb_t* esp_camera_fb_get();
-
-/**
- * @brief Return the frame buffer to be reused again.
- *
- * @param fb    Pointer to the frame buffer
- */
-void esp_camera_fb_return(camera_fb_t * fb);
-
-/**
- * @brief Get a pointer to the image sensor control structure
- *
- * @return pointer to the sensor
- */
-sensor_t * esp_camera_sensor_get();
-
-/**
- * @brief Save camera settings to non-volatile-storage (NVS)
- * 
- * @param key   A unique nvs key name for the camera settings 
- */
-esp_err_t esp_camera_save_to_nvs(const char *key);
-
-/**
- * @brief Load camera settings from non-volatile-storage (NVS)
- * 
- * @param key   A unique nvs key name for the camera settings 
- */
-esp_err_t esp_camera_load_from_nvs(const char *key);
-
-#ifdef __cplusplus
-}
-#endif
-
-#include "img_converters.h"
-
diff --git a/tools/sdk/include/esp32-camera/esp_jpg_decode.h b/tools/sdk/include/esp32-camera/esp_jpg_decode.h
deleted file mode 100644
index f13536edf4d..00000000000
--- a/tools/sdk/include/esp32-camera/esp_jpg_decode.h
+++ /dev/null
@@ -1,43 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_JPG_DECODE_H_
-#define _ESP_JPG_DECODE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-
-typedef enum {
-    JPG_SCALE_NONE,
-    JPG_SCALE_2X,
-    JPG_SCALE_4X,
-    JPG_SCALE_8X,
-    JPG_SCALE_MAX = JPG_SCALE_8X
-} jpg_scale_t;
-
-typedef size_t (* jpg_reader_cb)(void * arg, size_t index, uint8_t *buf, size_t len);
-typedef bool (* jpg_writer_cb)(void * arg, uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint8_t *data);
-
-esp_err_t esp_jpg_decode(size_t len, jpg_scale_t scale, jpg_reader_cb reader, jpg_writer_cb writer, void * arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ESP_JPG_DECODE_H_ */
diff --git a/tools/sdk/include/esp32-camera/img_converters.h b/tools/sdk/include/esp32-camera/img_converters.h
deleted file mode 100644
index 2b83c4d6f42..00000000000
--- a/tools/sdk/include/esp32-camera/img_converters.h
+++ /dev/null
@@ -1,126 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _IMG_CONVERTERS_H_
-#define _IMG_CONVERTERS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_camera.h"
-
-typedef size_t (* jpg_out_cb)(void * arg, size_t index, const void* data, size_t len);
-
-/**
- * @brief Convert image buffer to JPEG
- *
- * @param src       Source buffer in RGB565, RGB888, YUYV or GRAYSCALE format
- * @param src_len   Length in bytes of the source buffer
- * @param width     Width in pixels of the source image
- * @param height    Height in pixels of the source image
- * @param format    Format of the source image
- * @param quality   JPEG quality of the resulting image
- * @param cp        Callback to be called to write the bytes of the output JPEG
- * @param arg       Pointer to be passed to the callback
- *
- * @return true on success
- */
-bool fmt2jpg_cb(uint8_t *src, size_t src_len, uint16_t width, uint16_t height, pixformat_t format, uint8_t quality, jpg_out_cb cb, void * arg);
-
-/**
- * @brief Convert camera frame buffer to JPEG
- *
- * @param fb        Source camera frame buffer
- * @param quality   JPEG quality of the resulting image
- * @param cp        Callback to be called to write the bytes of the output JPEG
- * @param arg       Pointer to be passed to the callback
- *
- * @return true on success
- */
-bool frame2jpg_cb(camera_fb_t * fb, uint8_t quality, jpg_out_cb cb, void * arg);
-
-/**
- * @brief Convert image buffer to JPEG buffer
- *
- * @param src       Source buffer in RGB565, RGB888, YUYV or GRAYSCALE format
- * @param src_len   Length in bytes of the source buffer
- * @param width     Width in pixels of the source image
- * @param height    Height in pixels of the source image
- * @param format    Format of the source image
- * @param quality   JPEG quality of the resulting image
- * @param out       Pointer to be populated with the address of the resulting buffer
- * @param out_len   Pointer to be populated with the length of the output buffer
- *
- * @return true on success
- */
-bool fmt2jpg(uint8_t *src, size_t src_len, uint16_t width, uint16_t height, pixformat_t format, uint8_t quality, uint8_t ** out, size_t * out_len);
-
-/**
- * @brief Convert camera frame buffer to JPEG buffer
- *
- * @param fb        Source camera frame buffer
- * @param quality   JPEG quality of the resulting image
- * @param out       Pointer to be populated with the address of the resulting buffer
- * @param out_len   Pointer to be populated with the length of the output buffer
- *
- * @return true on success
- */
-bool frame2jpg(camera_fb_t * fb, uint8_t quality, uint8_t ** out, size_t * out_len);
-
-/**
- * @brief Convert image buffer to BMP buffer
- *
- * @param src       Source buffer in JPEG, RGB565, RGB888, YUYV or GRAYSCALE format
- * @param src_len   Length in bytes of the source buffer
- * @param width     Width in pixels of the source image
- * @param height    Height in pixels of the source image
- * @param format    Format of the source image
- * @param out       Pointer to be populated with the address of the resulting buffer
- * @param out_len   Pointer to be populated with the length of the output buffer
- *
- * @return true on success
- */
-bool fmt2bmp(uint8_t *src, size_t src_len, uint16_t width, uint16_t height, pixformat_t format, uint8_t ** out, size_t * out_len);
-
-/**
- * @brief Convert camera frame buffer to BMP buffer
- *
- * @param fb        Source camera frame buffer
- * @param out       Pointer to be populated with the address of the resulting buffer
- * @param out_len   Pointer to be populated with the length of the output buffer
- *
- * @return true on success
- */
-bool frame2bmp(camera_fb_t * fb, uint8_t ** out, size_t * out_len);
-
-/**
- * @brief Convert image buffer to RGB888 buffer (used for face detection)
- *
- * @param src       Source buffer in JPEG, RGB565, RGB888, YUYV or GRAYSCALE format
- * @param src_len   Length in bytes of the source buffer
- * @param format    Format of the source image
- * @param rgb_buf   Pointer to the output buffer (width * height * 3)
- *
- * @return true on success
- */
-bool fmt2rgb888(const uint8_t *src_buf, size_t src_len, pixformat_t format, uint8_t * rgb_buf);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _IMG_CONVERTERS_H_ */
diff --git a/tools/sdk/include/esp32-camera/sensor.h b/tools/sdk/include/esp32-camera/sensor.h
deleted file mode 100755
index ad6cd890d19..00000000000
--- a/tools/sdk/include/esp32-camera/sensor.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * This file is part of the OpenMV project.
- * Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
- * This work is licensed under the MIT license, see the file LICENSE for details.
- *
- * Sensor abstraction layer.
- *
- */
-#ifndef __SENSOR_H__
-#define __SENSOR_H__
-#include <stdint.h>
-#include <stdbool.h>
-
-#define NT99141_PID     (0x14)
-#define OV9650_PID     (0x96)
-#define OV7725_PID     (0x77)
-#define OV2640_PID     (0x26)
-#define OV3660_PID     (0x36)
-#define OV5640_PID     (0x56)
-#define OV7670_PID     (0x76)
-
-typedef enum {
-    PIXFORMAT_RGB565,    // 2BPP/RGB565
-    PIXFORMAT_YUV422,    // 2BPP/YUV422
-    PIXFORMAT_GRAYSCALE, // 1BPP/GRAYSCALE
-    PIXFORMAT_JPEG,      // JPEG/COMPRESSED
-    PIXFORMAT_RGB888,    // 3BPP/RGB888
-    PIXFORMAT_RAW,       // RAW
-    PIXFORMAT_RGB444,    // 3BP2P/RGB444
-    PIXFORMAT_RGB555,    // 3BP2P/RGB555
-} pixformat_t;
-
-typedef enum {
-    FRAMESIZE_96X96,    // 96x96
-    FRAMESIZE_QQVGA,    // 160x120
-    FRAMESIZE_QCIF,     // 176x144
-    FRAMESIZE_HQVGA,    // 240x176
-    FRAMESIZE_240X240,  // 240x240
-    FRAMESIZE_QVGA,     // 320x240
-    FRAMESIZE_CIF,      // 400x296
-    FRAMESIZE_HVGA,     // 480x320
-    FRAMESIZE_VGA,      // 640x480
-    FRAMESIZE_SVGA,     // 800x600
-    FRAMESIZE_XGA,      // 1024x768
-    FRAMESIZE_HD,       // 1280x720
-    FRAMESIZE_SXGA,     // 1280x1024
-    FRAMESIZE_UXGA,     // 1600x1200
-    // 3MP Sensors
-    FRAMESIZE_FHD,      // 1920x1080
-    FRAMESIZE_P_HD,     //  720x1280
-    FRAMESIZE_P_3MP,    //  864x1536
-    FRAMESIZE_QXGA,     // 2048x1536
-    // 5MP Sensors
-    FRAMESIZE_QHD,      // 2560x1440
-    FRAMESIZE_WQXGA,    // 2560x1600
-    FRAMESIZE_P_FHD,    // 1080x1920
-    FRAMESIZE_QSXGA,    // 2560x1920
-    FRAMESIZE_INVALID
-} framesize_t;
-
-typedef enum {
-    ASPECT_RATIO_4X3,
-    ASPECT_RATIO_3X2,
-    ASPECT_RATIO_16X10,
-    ASPECT_RATIO_5X3,
-    ASPECT_RATIO_16X9,
-    ASPECT_RATIO_21X9,
-    ASPECT_RATIO_5X4,
-    ASPECT_RATIO_1X1,
-    ASPECT_RATIO_9X16
-} aspect_ratio_t;
-
-typedef enum {
-    GAINCEILING_2X,
-    GAINCEILING_4X,
-    GAINCEILING_8X,
-    GAINCEILING_16X,
-    GAINCEILING_32X,
-    GAINCEILING_64X,
-    GAINCEILING_128X,
-} gainceiling_t;
-
-typedef struct {
-        uint16_t max_width;
-        uint16_t max_height;
-        uint16_t start_x;
-        uint16_t start_y;
-        uint16_t end_x;
-        uint16_t end_y;
-        uint16_t offset_x;
-        uint16_t offset_y;
-        uint16_t total_x;
-        uint16_t total_y;
-} ratio_settings_t;
-
-typedef struct {
-        const uint16_t width;
-        const uint16_t height;
-        const aspect_ratio_t aspect_ratio;
-} resolution_info_t;
-
-// Resolution table (in sensor.c)
-extern const resolution_info_t resolution[];
-
-typedef struct {
-    uint8_t MIDH;
-    uint8_t MIDL;
-    uint8_t PID;
-    uint8_t VER;
-} sensor_id_t;
-
-typedef struct {
-    framesize_t framesize;//0 - 10
-    bool scale;
-    bool binning;
-    uint8_t quality;//0 - 63
-    int8_t brightness;//-2 - 2
-    int8_t contrast;//-2 - 2
-    int8_t saturation;//-2 - 2
-    int8_t sharpness;//-2 - 2
-    uint8_t denoise;
-    uint8_t special_effect;//0 - 6
-    uint8_t wb_mode;//0 - 4
-    uint8_t awb;
-    uint8_t awb_gain;
-    uint8_t aec;
-    uint8_t aec2;
-    int8_t ae_level;//-2 - 2
-    uint16_t aec_value;//0 - 1200
-    uint8_t agc;
-    uint8_t agc_gain;//0 - 30
-    uint8_t gainceiling;//0 - 6
-    uint8_t bpc;
-    uint8_t wpc;
-    uint8_t raw_gma;
-    uint8_t lenc;
-    uint8_t hmirror;
-    uint8_t vflip;
-    uint8_t dcw;
-    uint8_t colorbar;
-} camera_status_t;
-
-typedef struct _sensor sensor_t;
-typedef struct _sensor {
-    sensor_id_t id;             // Sensor ID.
-    uint8_t  slv_addr;          // Sensor I2C slave address.
-    pixformat_t pixformat;
-    camera_status_t status;
-    int xclk_freq_hz;
-
-    // Sensor function pointers
-    int  (*init_status)         (sensor_t *sensor);
-    int  (*reset)               (sensor_t *sensor);
-    int  (*set_pixformat)       (sensor_t *sensor, pixformat_t pixformat);
-    int  (*set_framesize)       (sensor_t *sensor, framesize_t framesize);
-    int  (*set_contrast)        (sensor_t *sensor, int level);
-    int  (*set_brightness)      (sensor_t *sensor, int level);
-    int  (*set_saturation)      (sensor_t *sensor, int level);
-    int  (*set_sharpness)       (sensor_t *sensor, int level);
-    int  (*set_denoise)         (sensor_t *sensor, int level);
-    int  (*set_gainceiling)     (sensor_t *sensor, gainceiling_t gainceiling);
-    int  (*set_quality)         (sensor_t *sensor, int quality);
-    int  (*set_colorbar)        (sensor_t *sensor, int enable);
-    int  (*set_whitebal)        (sensor_t *sensor, int enable);
-    int  (*set_gain_ctrl)       (sensor_t *sensor, int enable);
-    int  (*set_exposure_ctrl)   (sensor_t *sensor, int enable);
-    int  (*set_hmirror)         (sensor_t *sensor, int enable);
-    int  (*set_vflip)           (sensor_t *sensor, int enable);
-
-    int  (*set_aec2)            (sensor_t *sensor, int enable);
-    int  (*set_awb_gain)        (sensor_t *sensor, int enable);
-    int  (*set_agc_gain)        (sensor_t *sensor, int gain);
-    int  (*set_aec_value)       (sensor_t *sensor, int gain);
-
-    int  (*set_special_effect)  (sensor_t *sensor, int effect);
-    int  (*set_wb_mode)         (sensor_t *sensor, int mode);
-    int  (*set_ae_level)        (sensor_t *sensor, int level);
-
-    int  (*set_dcw)             (sensor_t *sensor, int enable);
-    int  (*set_bpc)             (sensor_t *sensor, int enable);
-    int  (*set_wpc)             (sensor_t *sensor, int enable);
-
-    int  (*set_raw_gma)         (sensor_t *sensor, int enable);
-    int  (*set_lenc)            (sensor_t *sensor, int enable);
-
-    int  (*get_reg)             (sensor_t *sensor, int reg, int mask);
-    int  (*set_reg)             (sensor_t *sensor, int reg, int mask, int value);
-    int  (*set_res_raw)         (sensor_t *sensor, int startX, int startY, int endX, int endY, int offsetX, int offsetY, int totalX, int totalY, int outputX, int outputY, bool scale, bool binning);
-    int  (*set_pll)             (sensor_t *sensor, int bypass, int mul, int sys, int root, int pre, int seld5, int pclken, int pclk);
-    int  (*set_xclk)            (sensor_t *sensor, int timer, int xclk);
-} sensor_t;
-
-#endif /* __SENSOR_H__ */
diff --git a/tools/sdk/include/esp32/esp32/pm.h b/tools/sdk/include/esp32/esp32/pm.h
deleted file mode 100644
index f64045fb31b..00000000000
--- a/tools/sdk/include/esp32/esp32/pm.h
+++ /dev/null
@@ -1,44 +0,0 @@
-// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#pragma once
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-
-#include "soc/rtc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**
- * @brief Power management config for ESP32
- *
- * Pass a pointer to this structure as an argument to esp_pm_configure function.
- */
-typedef struct {
-    rtc_cpu_freq_t max_cpu_freq __attribute__((deprecated));    /*!< Maximum CPU frequency to use. Deprecated, use max_freq_mhz instead. */
-    int max_freq_mhz;   /*!< Maximum CPU frequency, in MHz */
-    rtc_cpu_freq_t min_cpu_freq __attribute__((deprecated));    /*!< Minimum CPU frequency to use when no frequency locks are taken.  Deprecated, use min_freq_mhz instead. */
-    int min_freq_mhz;   /*!< Minimum CPU frequency to use when no locks are taken, in MHz */
-    bool light_sleep_enable;        /*!< Enter light sleep when no locks are taken */
-} esp_pm_config_esp32_t;
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp32/esp_assert.h b/tools/sdk/include/esp32/esp_assert.h
deleted file mode 100644
index 39d6a32843f..00000000000
--- a/tools/sdk/include/esp32/esp_assert.h
+++ /dev/null
@@ -1,37 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __ESP_ASSERT_H__
-#define __ESP_ASSERT_H__
-
-#include "assert.h"
-
-/* Assert at compile time if possible, runtime otherwise */
-#ifndef __cplusplus
-/* __builtin_choose_expr() is only in C, makes this a lot cleaner */
-#define TRY_STATIC_ASSERT(CONDITION, MSG) do {                                                              \
-            _Static_assert(__builtin_choose_expr(__builtin_constant_p(CONDITION), (CONDITION), 1), #MSG);   \
-            assert(#MSG && (CONDITION));                                                                    \
-        } while(0)
-#else
-/* for C++, use __attribute__((error)) - works almost as well as _Static_assert */
-#define TRY_STATIC_ASSERT(CONDITION, MSG) do {                                                              \
-            if (__builtin_constant_p(CONDITION) && !(CONDITION)) {          \
-                extern __attribute__((error(#MSG))) void failed_compile_time_assert(void);      \
-                failed_compile_time_assert();                                                   \
-            }                                                                                   \
-            assert(#MSG && (CONDITION));                                                                    \
-        } while(0)
-#endif /* __cplusplus */
-
-#endif /* __ESP_ASSERT_H__ */
diff --git a/tools/sdk/include/esp32/esp_attr.h b/tools/sdk/include/esp32/esp_attr.h
deleted file mode 100644
index c9e3879eea3..00000000000
--- a/tools/sdk/include/esp32/esp_attr.h
+++ /dev/null
@@ -1,87 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __ESP_ATTR_H__
-#define __ESP_ATTR_H__
-
-#include "sdkconfig.h"
-
-#define ROMFN_ATTR
-
-//Normally, the linker script will put all code and rodata in flash,
-//and all variables in shared RAM. These macros can be used to redirect
-//particular functions/variables to other memory regions.
-
-// Forces code into IRAM instead of flash
-#define IRAM_ATTR _SECTION_ATTR_IMPL(".iram1", __COUNTER__)
-
-// Forces data into DRAM instead of flash
-#define DRAM_ATTR _SECTION_ATTR_IMPL(".dram1", __COUNTER__)
-
-// Forces data to be 4 bytes aligned
-#define WORD_ALIGNED_ATTR __attribute__((aligned(4)))
-
-// Forces data to be placed to DMA-capable places
-#define DMA_ATTR WORD_ALIGNED_ATTR DRAM_ATTR
-
-// Forces a string into DRAM instead of flash
-// Use as ets_printf(DRAM_STR("Hello world!\n"));
-#define DRAM_STR(str) (__extension__({static const DRAM_ATTR char __c[] = (str); (const char *)&__c;}))
-
-// Forces code into RTC fast memory. See "docs/deep-sleep-stub.rst"
-#define RTC_IRAM_ATTR _SECTION_ATTR_IMPL(".rtc.text", __COUNTER__)
-
-#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
-// Forces bss variable into external memory. "
-#define EXT_RAM_ATTR _SECTION_ATTR_IMPL(".ext_ram.bss", __COUNTER__)
-#else
-#define EXT_RAM_ATTR 
-#endif
-
-// Forces data into RTC slow memory. See "docs/deep-sleep-stub.rst"
-// Any variable marked with this attribute will keep its value
-// during a deep sleep / wake cycle.
-#define RTC_DATA_ATTR _SECTION_ATTR_IMPL(".rtc.data", __COUNTER__)
-
-// Forces read-only data into RTC memory. See "docs/deep-sleep-stub.rst"
-#define RTC_RODATA_ATTR _SECTION_ATTR_IMPL(".rtc.rodata", __COUNTER__)
-
-// Allows to place data into RTC_SLOW memory.
-#define RTC_SLOW_ATTR _SECTION_ATTR_IMPL(".rtc.force_slow", __COUNTER__)
-
-// Allows to place data into RTC_FAST memory.
-#define RTC_FAST_ATTR _SECTION_ATTR_IMPL(".rtc.force_fast", __COUNTER__)
-
-// Forces data into noinit section to avoid initialization after restart.
-#define __NOINIT_ATTR _SECTION_ATTR_IMPL(".noinit", __COUNTER__)
-
-// Forces data into RTC slow memory of .noinit section.
-// Any variable marked with this attribute will keep its value
-// after restart or during a deep sleep / wake cycle.
-#define RTC_NOINIT_ATTR  _SECTION_ATTR_IMPL(".rtc_noinit", __COUNTER__)
-
-// Forces to not inline function
-#define NOINLINE_ATTR __attribute__((noinline))
-
-// Implementation for a unique custom section
-//
-// This prevents gcc producing "x causes a section type conflict with y"
-// errors if two variables in the same source file have different linkage (maybe const & non-const) but are placed in the same custom section
-//
-// Using unique sections also means --gc-sections can remove unused
-// data with a custom section type set
-#define _SECTION_ATTR_IMPL(SECTION, COUNTER) __attribute__((section(SECTION "." _COUNTER_STRINGIFY(COUNTER))))
-
-#define _COUNTER_STRINGIFY(COUNTER) #COUNTER
-
-#endif /* __ESP_ATTR_H__ */
diff --git a/tools/sdk/include/esp32/esp_brownout.h b/tools/sdk/include/esp32/esp_brownout.h
deleted file mode 100644
index 5a0b1aec001..00000000000
--- a/tools/sdk/include/esp32/esp_brownout.h
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_BROWNOUT_H
-#define __ESP_BROWNOUT_H
-
-void esp_brownout_init();
-
-#endif
\ No newline at end of file
diff --git a/tools/sdk/include/esp32/esp_cache_err_int.h b/tools/sdk/include/esp32/esp_cache_err_int.h
deleted file mode 100644
index bcbd63e7998..00000000000
--- a/tools/sdk/include/esp32/esp_cache_err_int.h
+++ /dev/null
@@ -1,33 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-/**
- * @brief initialize cache invalid access interrupt
- *
- * This function enables cache invalid access interrupt source and connects it
- * to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
- * from the startup code.
- */
-void esp_cache_err_int_init();
-
-
-/**
- * @brief get the CPU which caused cache invalid access interrupt
- * @return
- *  - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
- *  - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
- *  - (-1) otherwise
- */
-int esp_cache_err_get_cpuid();
diff --git a/tools/sdk/include/esp32/esp_clk.h b/tools/sdk/include/esp32/esp_clk.h
deleted file mode 100644
index 99e4f3078c6..00000000000
--- a/tools/sdk/include/esp32/esp_clk.h
+++ /dev/null
@@ -1,87 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-#include <stdint.h>
-
-/**
- * @file esp_clk.h
- *
- * This file contains declarations of clock related functions.
- */
-
-/**
- * @brief Get the calibration value of RTC slow clock
- *
- * The value is in the same format as returned by rtc_clk_cal (microseconds,
- * in Q13.19 fixed-point format).
- *
- * @return the calibration value obtained using rtc_clk_cal, at startup time
- */
-uint32_t esp_clk_slowclk_cal_get();
-
-/**
- * @brief Update the calibration value of RTC slow clock
- *
- * The value has to be in the same format as returned by rtc_clk_cal (microseconds,
- * in Q13.19 fixed-point format).
- * This value is used by timekeeping functions (such as gettimeofday) to
- * calculate current time based on RTC counter value.
- * @param value calibration value obtained using rtc_clk_cal
- */
-void esp_clk_slowclk_cal_set(uint32_t value);
-
-/**
- * @brief Return current CPU clock frequency
- * When frequency switching is performed, this frequency may change.
- * However it is guaranteed that the frequency never changes with a critical
- * section.
- *
- * @return CPU clock frequency, in Hz
- */
-int esp_clk_cpu_freq(void);
-
-/**
- * @brief Return current APB clock frequency
- *
- * When frequency switching is performed, this frequency may change.
- * However it is guaranteed that the frequency never changes with a critical
- * section.
- *
- * @return APB clock frequency, in Hz
- */
-int esp_clk_apb_freq(void);
-
-/**
- * @brief Return frequency of the main XTAL
- *
- * Frequency of the main XTAL can be either auto-detected or set at compile
- * time (see CONFIG_ESP32_XTAL_FREQ_SEL sdkconfig option). In both cases, this
- * function returns the actual value at run time.
- *
- * @return XTAL frequency, in Hz
- */
-int esp_clk_xtal_freq(void);
-
-
-/**
- * @brief Read value of RTC counter, converting it to microseconds
- * @attention The value returned by this function may change abruptly when
- * calibration value of RTC counter is updated via esp_clk_slowclk_cal_set
- * function. This should not happen unless application calls esp_clk_slowclk_cal_set.
- * In ESP-IDF, esp_clk_slowclk_cal_set is only called in startup code.
- *
- * @return Value or RTC counter, expressed in microseconds
- */
-uint64_t esp_clk_rtc_time();
diff --git a/tools/sdk/include/esp32/esp_coexist.h b/tools/sdk/include/esp32/esp_coexist.h
deleted file mode 100644
index 6def75c571f..00000000000
--- a/tools/sdk/include/esp32/esp_coexist.h
+++ /dev/null
@@ -1,107 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_COEXIST_H__
-#define __ESP_COEXIST_H__
-
-#include <stdbool.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief coex prefer value
- */
-typedef enum {
-    ESP_COEX_PREFER_WIFI = 0,       /*!< Prefer to WiFi, WiFi will have more opportunity to use RF */
-    ESP_COEX_PREFER_BT,             /*!< Prefer to bluetooth, bluetooth will have more opportunity to use RF */
-    ESP_COEX_PREFER_BALANCE,        /*!< Do balance of WiFi and bluetooth */
-    ESP_COEX_PREFER_NUM,            /*!< Prefer value numbers */
-} esp_coex_prefer_t;
-
- /**
- * @brief coex status type
- */
-typedef enum {
-    ESP_COEX_ST_TYPE_WIFI = 0,
-    ESP_COEX_ST_TYPE_BLE,
-    ESP_COEX_ST_TYPE_BT,
-} esp_coex_status_type_t;
-
-#define ESP_COEX_BLE_ST_MESH_CONFIG        0x08
-#define ESP_COEX_BLE_ST_MESH_TRAFFIC       0x10
-#define ESP_COEX_BLE_ST_MESH_STANDBY       0x20
-
-#define ESP_COEX_BT_ST_A2DP_STREAMING      0x10
-#define ESP_COEX_BT_ST_A2DP_PAUSED         0x20
-
-/**
- * @brief Get software coexist version string
- *
- * @return : version string
- */
-const char *esp_coex_version_get(void);
-
-/**
- * @deprecated Use esp_coex_status_bit_set() and esp_coex_status_bit_clear() instead.
- *  Set coexist preference of performance
- *  For example, if prefer to bluetooth, then it will make A2DP(play audio via classic bt)
- *  more smooth while wifi is runnning something.
- *  If prefer to wifi, it will do similar things as prefer to bluetooth.
- *  Default, it prefer to balance.
- *
- *  @param prefer : the prefer enumeration value
- *  @return : ESP_OK - success, other - failed
- */
-esp_err_t esp_coex_preference_set(esp_coex_prefer_t prefer);
-
-/**
- * @brief Set coex schm status
- * @param type : WIFI/BLE/BT
- * @param status : WIFI/BLE/BT STATUS
- * @return : ESP_OK - success, other - failed
- */
-esp_err_t esp_coex_status_bit_set(esp_coex_status_type_t type, uint32_t status);
-
-/**
- * @brief Clear coex schm status
- * @param type : WIFI/BLE/BT
- * @param status : WIFI/BLE/BT STATUS
- * @return : ESP_OK - success, other - failed
- */
-esp_err_t esp_coex_status_bit_clear(esp_coex_status_type_t type, uint32_t status);
-
-/**
- * @brief Enable BLE connection dynamic priority
- * @attention If the parameter is true, BLE connection performance will be better but WiFi performance
- *            will be poorer. And vice versa.
- * @param low_interval : true - Increase BLE connection priority to be higher than WiFi's when BLE
- *                              connection interval is less or equal than 50 ms. The default value
- *                              is false.
- *                       false - not increace
- * @param high_interval : true - Increase BLE connection priority to be higher than WiFi's when BLE
- *                               connection interval is more than 50 ms. The default value is true.
- *                        false - not increace
- * @return : ESP_OK - success, other - failed
- */
-esp_err_t esp_coex_ble_conn_dynamic_prio_enable(bool low_interval, bool high_interval);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __ESP_COEXIST_H__ */
diff --git a/tools/sdk/include/esp32/esp_coexist_adapter.h b/tools/sdk/include/esp32/esp_coexist_adapter.h
deleted file mode 100644
index f2a38c31e63..00000000000
--- a/tools/sdk/include/esp32/esp_coexist_adapter.h
+++ /dev/null
@@ -1,59 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_COEXIST_ADAPTER_H__
-#define __ESP_COEXIST_ADAPTER_H__
-
-#include <stdarg.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define COEX_ADAPTER_VERSION  0x00000001
-#define COEX_ADAPTER_MAGIC    0xDEADBEAF
-
-#define COEX_ADAPTER_FUNCS_TIME_BLOCKING      0xffffffff
-
-typedef struct {
-    int32_t _version;
-    void *(* _spin_lock_create)(void);
-    void (* _spin_lock_delete)(void *lock);
-    uint32_t (*_int_disable)(void *mux);
-    void (*_int_enable)(void *mux, uint32_t tmp);
-    void (*_task_yield_from_isr)(void);
-    void *(*_semphr_create)(uint32_t max, uint32_t init);
-    void (*_semphr_delete)(void *semphr);
-    int32_t (*_semphr_take_from_isr)(void *semphr, void *hptw);
-    int32_t (*_semphr_give_from_isr)(void *semphr, void *hptw);
-    int32_t (*_semphr_take)(void *semphr, uint32_t block_time_tick);
-    int32_t (*_semphr_give)(void *semphr);
-    int32_t (* _is_in_isr)(void);
-    void * (* _malloc_internal)(size_t size);
-    void (* _free)(void *p);
-    void (* _timer_disarm)(void *timer);
-    void (* _timer_done)(void *ptimer);
-    void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg);
-    void (* _timer_arm_us)(void *ptimer, uint32_t us, bool repeat);
-    int64_t (* _esp_timer_get_time)(void);
-    int32_t _magic;
-} coex_adapter_funcs_t;
-
-extern coex_adapter_funcs_t g_coex_adapter_funcs;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_COEXIST_ADAPTER_H__ */
diff --git a/tools/sdk/include/esp32/esp_coexist_internal.h b/tools/sdk/include/esp32/esp_coexist_internal.h
deleted file mode 100644
index bdd023a93d9..00000000000
--- a/tools/sdk/include/esp32/esp_coexist_internal.h
+++ /dev/null
@@ -1,177 +0,0 @@
-// Copyright 2018-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_COEXIST_INTERNAL_H__
-#define __ESP_COEXIST_INTERNAL_H__
-
-#include <stdbool.h>
-#include "esp_coexist_adapter.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    COEX_PREFER_WIFI = 0,
-    COEX_PREFER_BT,
-    COEX_PREFER_BALANCE,
-    COEX_PREFER_NUM,
-} coex_prefer_t;
-
-typedef void (* coex_func_cb_t)(uint32_t event, int sched_cnt);
-
-/**
- * @brief Pre-Init software coexist
- *        extern function for internal use.
- *
- * @return Init ok or failed.
- */
-esp_err_t coex_pre_init(void);
-
-/**
- * @brief Init software coexist
- *        extern function for internal use.
- *
- * @return Init ok or failed.
- */
-esp_err_t coex_init(void);
-
-/**
- * @brief De-init software coexist
- *        extern function for internal use.
- */
-void coex_deinit(void);
-
-/**
- * @brief Pause software coexist
- *        extern function for internal use.
- */
-void coex_pause(void);
-
-/**
- * @brief Resume software coexist
- *        extern function for internal use.
- */
-void coex_resume(void);
-
-/**
- * @brief Get software coexist version string
- *        extern function for internal use.
- * @return : version string
- */
-const char *coex_version_get(void);
-
-/**
- * @brief Coexist performance preference set from libbt.a
- *        extern function for internal use.
- *
- *  @param prefer : the prefer enumeration value
- *  @return : ESP_OK - success, other - failed
- */
-esp_err_t coex_preference_set(coex_prefer_t prefer);
-
-/**
- * @brief Get software coexist status.
- * @return : software coexist status
- */
-uint32_t coex_status_get(void);
-
-/**
- * @brief Set software coexist condition.
- * @return : software coexist condition
- */
-void coex_condition_set(uint32_t type, bool dissatisfy);
-
-/**
- * @brief WiFi requests coexistence.
- *
- *  @param event : WiFi event
- *  @param latency : WiFi will request coexistence after latency
- *  @param duration : duration for WiFi to request coexistence
- *  @return : 0 - success, other - failed
- */
-int coex_wifi_request(uint32_t event, uint32_t latency, uint32_t duration);
-
-/**
- * @brief WiFi release coexistence.
- *
- *  @param event : WiFi event
- *  @return : 0 - success, other - failed
- */
-int coex_wifi_release(uint32_t event);
-
-/**
- * @brief Blue tooth requests coexistence.
- *
- *  @param event : blue tooth event
- *  @param latency : blue tooth will request coexistence after latency
- *  @param duration : duration for blue tooth to request coexistence
- *  @return : 0 - success, other - failed
- */
-int coex_bt_request(uint32_t event, uint32_t latency, uint32_t duration);
-
-/**
- * @brief Blue tooth release coexistence.
- *
- *  @param event : blue tooth event
- *  @return : 0 - success, other - failed
- */
-int coex_bt_release(uint32_t event);
-
-/**
- * @brief Register callback function for blue tooth.
- *
- *  @param cb : callback function
- *  @return : 0 - success, other - failed
- */
-int coex_register_bt_cb(coex_func_cb_t cb);
-
-/**
- * @brief Lock before reset base band.
- *
- *  @return : lock value
- */
-uint32_t coex_bb_reset_lock(void);
-
-/**
- * @brief Unlock after reset base band.
- *
- *  @param restore : lock value
- */
-void coex_bb_reset_unlock(uint32_t restore);
-
-/**
- * @brief Register coexistence adapter functions.
- *
- *  @param funcs : coexistence adapter functions
- *  @return : ESP_OK - success, other - failed
- */
-esp_err_t esp_coex_adapter_register(coex_adapter_funcs_t *funcs);
-
-/**
-  * @brief     Check the MD5 values of the coexistence adapter header files in IDF and WiFi library
-  *
-  * @attention 1. It is used for internal CI version check
-  *
-  * @return
-  *     - ESP_OK : succeed
-  *     - ESP_WIFI_INVALID_ARG : MD5 check fail
-  */
-esp_err_t esp_coex_adapter_funcs_md5_check(const char *md5);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_COEXIST_INTERNAL_H__ */
diff --git a/tools/sdk/include/esp32/esp_crosscore_int.h b/tools/sdk/include/esp32/esp_crosscore_int.h
deleted file mode 100644
index 2f1c5b3becf..00000000000
--- a/tools/sdk/include/esp32/esp_crosscore_int.h
+++ /dev/null
@@ -1,54 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __ESP_CROSSCORE_INT_H
-#define __ESP_CROSSCORE_INT_H
-
-
-/**
- * Initialize the crosscore interrupt system for this CPU.
- * This needs to be called once on every CPU that is used
- * by FreeRTOS.
- *
- * If multicore FreeRTOS support is enabled, this will be
- * called automatically by the startup code and should not
- * be called manually.
- */
-void esp_crosscore_int_init();
-
-
-/**
- * Send an interrupt to a CPU indicating it should yield its
- * currently running task in favour of a higher-priority task
- * that presumably just woke up.
- *
- * This is used internally by FreeRTOS in multicore mode
- * and should not be called by the user.
- *
- * @param core_id Core that should do the yielding
- */
-void esp_crosscore_int_send_yield(int core_id);
-
-
-/**
- * Send an interrupt to a CPU indicating it should update its
- * CCOMPARE1 value due to a frequency switch.
- *
- * This is used internally when dynamic frequency switching is
- * enabled, and should not be called from application code.
- *
- * @param core_id Core that should update its CCOMPARE1 value
- */
-void esp_crosscore_int_send_freq_switch(int core_id);
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_dbg_stubs.h b/tools/sdk/include/esp32/esp_dbg_stubs.h
deleted file mode 100644
index 899dfa56ed8..00000000000
--- a/tools/sdk/include/esp32/esp_dbg_stubs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef ESP_DBG_STUBS_H_
-#define ESP_DBG_STUBS_H_
-
-#include "esp_err.h"
-
-/**
- * Debug stubs entries IDs
- */
-typedef enum {
-    ESP_DBG_STUB_CONTROL_DATA,	///< stubs descriptor entry
-    ESP_DBG_STUB_ENTRY_FIRST,
-    ESP_DBG_STUB_ENTRY_GCOV		///< GCOV entry
-    						= ESP_DBG_STUB_ENTRY_FIRST,
-    ESP_DBG_STUB_ENTRY_MAX
-} esp_dbg_stub_id_t;
-
-/**
- * @brief  Initializes debug stubs.
- *
- * @note   Must be called after esp_apptrace_init() if app tracing is enabled.
- */
-void esp_dbg_stubs_init(void);
-
-/**
- * @brief  Initializes application tracing module.
- *
- * @note   Should be called before any esp_apptrace_xxx call.
- *
- * @param id 	Stub ID.
- * @param entry Stub entry. Usually it is stub entry function address,
- *              but can be any value meaningfull for OpenOCD command/code.
- *
- * @return ESP_OK on success, otherwise see esp_err_t
- */
-esp_err_t esp_dbg_stub_entry_set(esp_dbg_stub_id_t id, uint32_t entry);
-
-#endif //ESP_DBG_STUBS_H_
\ No newline at end of file
diff --git a/tools/sdk/include/esp32/esp_deep_sleep.h b/tools/sdk/include/esp32/esp_deep_sleep.h
deleted file mode 100644
index ea4601818a5..00000000000
--- a/tools/sdk/include/esp32/esp_deep_sleep.h
+++ /dev/null
@@ -1,94 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/**
- * @file esp_deep_sleep.h
- * @brief legacy definitions of esp_deep_sleep APIs
- *
- * This file provides compatibility for applications using esp_deep_sleep_* APIs.
- * New applications should use functions defined in "esp_sleep.h" instead.
- * These functions and types will be deprecated at some point.
- */
-
-#warning esp_deep_sleep.h will be deprecated in the next release. Use esp_sleep.h instead.
-
-#include "esp_sleep.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-typedef esp_sleep_pd_domain_t esp_deep_sleep_pd_domain_t;
-typedef esp_sleep_pd_option_t esp_deep_sleep_pd_option_t;
-typedef esp_sleep_ext1_wakeup_mode_t esp_ext1_wakeup_mode_t;
-typedef esp_sleep_wakeup_cause_t esp_deep_sleep_wakeup_cause_t;
-
-inline static esp_err_t esp_deep_sleep_enable_ulp_wakeup(void)
-{
-    return esp_sleep_enable_ulp_wakeup();
-}
-
-inline static esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us)
-{
-    return esp_sleep_enable_timer_wakeup(time_in_us);
-}
-
-inline static esp_err_t esp_deep_sleep_enable_touchpad_wakeup(void)
-{
-    return esp_sleep_enable_touchpad_wakeup();
-}
-
-inline static touch_pad_t esp_deep_sleep_get_touchpad_wakeup_status()
-{
-    return esp_sleep_get_touchpad_wakeup_status();
-}
-
-inline static esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
-{
-    return esp_sleep_enable_ext0_wakeup(gpio_num, level);
-}
-
-inline static esp_err_t esp_deep_sleep_enable_ext1_wakeup(uint64_t mask, esp_ext1_wakeup_mode_t mode)
-{
-    return esp_sleep_enable_ext1_wakeup(mask, mode);
-}
-
-inline static esp_err_t esp_deep_sleep_pd_config(
-        esp_deep_sleep_pd_domain_t domain,
-        esp_deep_sleep_pd_option_t option)
-{
-    return esp_sleep_pd_config(domain, option);
-}
-
-inline static esp_deep_sleep_wakeup_cause_t esp_deep_sleep_get_wakeup_cause()
-{
-    return esp_sleep_get_wakeup_cause();
-}
-
-#define ESP_DEEP_SLEEP_WAKEUP_UNDEFINED     ESP_SLEEP_WAKEUP_UNDEFINED
-#define ESP_DEEP_SLEEP_WAKEUP_EXT0          ESP_SLEEP_WAKEUP_EXT0
-#define ESP_DEEP_SLEEP_WAKEUP_EXT1          ESP_SLEEP_WAKEUP_EXT1
-#define ESP_DEEP_SLEEP_WAKEUP_TIMER         ESP_SLEEP_WAKEUP_TIMER
-#define ESP_DEEP_SLEEP_WAKEUP_TOUCHPAD      ESP_SLEEP_WAKEUP_TOUCHPAD
-#define ESP_DEEP_SLEEP_WAKEUP_ULP           ESP_SLEEP_WAKEUP_ULP
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/tools/sdk/include/esp32/esp_deepsleep.h b/tools/sdk/include/esp32/esp_deepsleep.h
deleted file mode 100644
index 3f0151b6a81..00000000000
--- a/tools/sdk/include/esp32/esp_deepsleep.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#warning esp_deepsleep.h has been renamed to esp_sleep.h, please update include directives
-#include "esp_sleep.h"
diff --git a/tools/sdk/include/esp32/esp_dport_access.h b/tools/sdk/include/esp32/esp_dport_access.h
deleted file mode 100644
index 8ea60c4cdb0..00000000000
--- a/tools/sdk/include/esp32/esp_dport_access.h
+++ /dev/null
@@ -1,52 +0,0 @@
-// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#include <sdkconfig.h>
-
-#ifndef _ESP_DPORT_ACCESS_H_
-#define _ESP_DPORT_ACCESS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void esp_dport_access_stall_other_cpu_start(void);
-void esp_dport_access_stall_other_cpu_end(void);
-void esp_dport_access_int_init(void);
-void esp_dport_access_int_pause(void);
-void esp_dport_access_int_resume(void);
-void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
-uint32_t esp_dport_access_reg_read(uint32_t reg);
-uint32_t esp_dport_access_sequence_reg_read(uint32_t reg);
-//This routine does not stop the dport routines in any way that is recoverable. Please
-//only call in case of panic().
-void esp_dport_access_int_abort(void);
-
-#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
-#define DPORT_STALL_OTHER_CPU_START()
-#define DPORT_STALL_OTHER_CPU_END()
-#define DPORT_INTERRUPT_DISABLE()
-#define DPORT_INTERRUPT_RESTORE()
-#else
-#define DPORT_STALL_OTHER_CPU_START()   esp_dport_access_stall_other_cpu_start()
-#define DPORT_STALL_OTHER_CPU_END()     esp_dport_access_stall_other_cpu_end()
-#define DPORT_INTERRUPT_DISABLE()       unsigned int intLvl = XTOS_SET_INTLEVEL(CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL)
-#define DPORT_INTERRUPT_RESTORE()       XTOS_RESTORE_JUST_INTLEVEL(intLvl)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ESP_DPORT_ACCESS_H_ */
diff --git a/tools/sdk/include/esp32/esp_err.h b/tools/sdk/include/esp32/esp_err.h
deleted file mode 100644
index 6672f233a19..00000000000
--- a/tools/sdk/include/esp32/esp_err.h
+++ /dev/null
@@ -1,148 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include <stdint.h>
-#include <stdio.h>
-#include <assert.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef int32_t esp_err_t;
-
-/* Definitions for error constants. */
-#define ESP_OK          0       /*!< esp_err_t value indicating success (no error) */
-#define ESP_FAIL        -1      /*!< Generic esp_err_t code indicating failure */
-
-#define ESP_ERR_NO_MEM              0x101   /*!< Out of memory */
-#define ESP_ERR_INVALID_ARG         0x102   /*!< Invalid argument */
-#define ESP_ERR_INVALID_STATE       0x103   /*!< Invalid state */
-#define ESP_ERR_INVALID_SIZE        0x104   /*!< Invalid size */
-#define ESP_ERR_NOT_FOUND           0x105   /*!< Requested resource not found */
-#define ESP_ERR_NOT_SUPPORTED       0x106   /*!< Operation or feature not supported */
-#define ESP_ERR_TIMEOUT             0x107   /*!< Operation timed out */
-#define ESP_ERR_INVALID_RESPONSE    0x108   /*!< Received response was invalid */
-#define ESP_ERR_INVALID_CRC         0x109   /*!< CRC or checksum was invalid */
-#define ESP_ERR_INVALID_VERSION     0x10A   /*!< Version was invalid */
-#define ESP_ERR_INVALID_MAC         0x10B   /*!< MAC address was invalid */
-
-#define ESP_ERR_WIFI_BASE           0x3000  /*!< Starting number of WiFi error codes */
-#define ESP_ERR_MESH_BASE           0x4000  /*!< Starting number of MESH error codes */
-
-/**
-  * @brief Returns string for esp_err_t error codes
-  *
-  * This function finds the error code in a pre-generated lookup-table and
-  * returns its string representation.
-  *
-  * The function is generated by the Python script
-  * tools/gen_esp_err_to_name.py which should be run each time an esp_err_t
-  * error is modified, created or removed from the IDF project.
-  *
-  * @param code esp_err_t error code
-  * @return string error message
-  */
-const char *esp_err_to_name(esp_err_t code);
-
-/**
-  * @brief Returns string for esp_err_t and system error codes
-  *
-  * This function finds the error code in a pre-generated lookup-table of
-  * esp_err_t errors and returns its string representation. If the error code
-  * is not found then it is attempted to be found among system errors.
-  *
-  * The function is generated by the Python script
-  * tools/gen_esp_err_to_name.py which should be run each time an esp_err_t
-  * error is modified, created or removed from the IDF project.
-  *
-  * @param code esp_err_t error code
-  * @param[out] buf buffer where the error message should be written
-  * @param buflen Size of buffer buf. At most buflen bytes are written into the buf buffer (including the terminating null byte).
-  * @return buf containing the string error message
-  */
-const char *esp_err_to_name_r(esp_err_t code, char *buf, size_t buflen);
-
-/** @cond */
-void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const char *function, const char *expression) __attribute__((noreturn));
-
-/** @cond */
-void _esp_error_check_failed_without_abort(esp_err_t rc, const char *file, int line, const char *function, const char *expression);
-
-#ifndef __ASSERT_FUNC
-/* This won't happen on IDF, which defines __ASSERT_FUNC in assert.h, but it does happen when building on the host which
-   uses /usr/include/assert.h or equivalent.
-*/
-#ifdef __ASSERT_FUNCTION
-#define __ASSERT_FUNC __ASSERT_FUNCTION /* used in glibc assert.h */
-#else
-#define __ASSERT_FUNC "??"
-#endif
-#endif
-/** @endcond */
-
-/**
- * Macro which can be used to check the error code,
- * and terminate the program in case the code is not ESP_OK.
- * Prints the error code, error location, and the failed statement to serial output.
- *
- * Disabled if assertions are disabled.
- */
-#ifdef NDEBUG
-#define ESP_ERROR_CHECK(x) do {                                         \
-        esp_err_t __err_rc = (x);                                       \
-        (void) sizeof(__err_rc);                                        \
-    } while(0);
-#elif defined(CONFIG_OPTIMIZATION_ASSERTIONS_SILENT)
-#define ESP_ERROR_CHECK(x) do {                                         \
-        esp_err_t __err_rc = (x);                                       \
-        if (__err_rc != ESP_OK) {                                       \
-            abort();                                                    \
-        }                                                               \
-    } while(0);
-#else
-#define ESP_ERROR_CHECK(x) do {                                         \
-        esp_err_t __err_rc = (x);                                       \
-        if (__err_rc != ESP_OK) {                                       \
-            _esp_error_check_failed(__err_rc, __FILE__, __LINE__,       \
-                                    __ASSERT_FUNC, #x);                 \
-        }                                                               \
-    } while(0);
-#endif
-
-/**
- * Macro which can be used to check the error code. Prints the error code, error location, and the failed statement to
- * serial output.
- * In comparison with ESP_ERROR_CHECK(), this prints the same error message but isn't terminating the program.
- */
-#ifdef NDEBUG
-#define ESP_ERROR_CHECK_WITHOUT_ABORT(x) ({                                         \
-        esp_err_t __err_rc = (x);                                                   \
-        __err_rc;                                                                   \
-    })
-#else
-#define ESP_ERROR_CHECK_WITHOUT_ABORT(x) ({                                         \
-        esp_err_t __err_rc = (x);                                                   \
-        if (__err_rc != ESP_OK) {                                                   \
-            _esp_error_check_failed_without_abort(__err_rc, __FILE__, __LINE__,     \
-                                    __ASSERT_FUNC, #x);                             \
-        }                                                                           \
-        __err_rc;                                                                   \
-    })
-#endif //NDEBUG
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp32/esp_event_legacy.h b/tools/sdk/include/esp32/esp_event_legacy.h
deleted file mode 100644
index 0ee6046c7ed..00000000000
--- a/tools/sdk/include/esp32/esp_event_legacy.h
+++ /dev/null
@@ -1,193 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_EVENT_H__
-#define __ESP_EVENT_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "esp_err.h"
-#include "esp_wifi_types.h"
-#include "tcpip_adapter.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    SYSTEM_EVENT_WIFI_READY = 0,           /**< ESP32 WiFi ready */
-    SYSTEM_EVENT_SCAN_DONE,                /**< ESP32 finish scanning AP */
-    SYSTEM_EVENT_STA_START,                /**< ESP32 station start */
-    SYSTEM_EVENT_STA_STOP,                 /**< ESP32 station stop */
-    SYSTEM_EVENT_STA_CONNECTED,            /**< ESP32 station connected to AP */
-    SYSTEM_EVENT_STA_DISCONNECTED,         /**< ESP32 station disconnected from AP */
-    SYSTEM_EVENT_STA_AUTHMODE_CHANGE,      /**< the auth mode of AP connected by ESP32 station changed */
-    SYSTEM_EVENT_STA_GOT_IP,               /**< ESP32 station got IP from connected AP */
-    SYSTEM_EVENT_STA_LOST_IP,              /**< ESP32 station lost IP and the IP is reset to 0 */
-    SYSTEM_EVENT_STA_WPS_ER_SUCCESS,       /**< ESP32 station wps succeeds in enrollee mode */
-    SYSTEM_EVENT_STA_WPS_ER_FAILED,        /**< ESP32 station wps fails in enrollee mode */
-    SYSTEM_EVENT_STA_WPS_ER_TIMEOUT,       /**< ESP32 station wps timeout in enrollee mode */
-    SYSTEM_EVENT_STA_WPS_ER_PIN,           /**< ESP32 station wps pin code in enrollee mode */
-    SYSTEM_EVENT_STA_WPS_ER_PBC_OVERLAP,   /*!< ESP32 station wps overlap in enrollee mode */
-    SYSTEM_EVENT_AP_START,                 /**< ESP32 soft-AP start */
-    SYSTEM_EVENT_AP_STOP,                  /**< ESP32 soft-AP stop */
-    SYSTEM_EVENT_AP_STACONNECTED,          /**< a station connected to ESP32 soft-AP */
-    SYSTEM_EVENT_AP_STADISCONNECTED,       /**< a station disconnected from ESP32 soft-AP */
-    SYSTEM_EVENT_AP_STAIPASSIGNED,         /**< ESP32 soft-AP assign an IP to a connected station */
-    SYSTEM_EVENT_AP_PROBEREQRECVED,        /**< Receive probe request packet in soft-AP interface */
-    SYSTEM_EVENT_GOT_IP6,                  /**< ESP32 station or ap or ethernet interface v6IP addr is preferred */
-    SYSTEM_EVENT_ETH_START,                /**< ESP32 ethernet start */
-    SYSTEM_EVENT_ETH_STOP,                 /**< ESP32 ethernet stop */
-    SYSTEM_EVENT_ETH_CONNECTED,            /**< ESP32 ethernet phy link up */
-    SYSTEM_EVENT_ETH_DISCONNECTED,         /**< ESP32 ethernet phy link down */
-    SYSTEM_EVENT_ETH_GOT_IP,               /**< ESP32 ethernet got IP from connected AP */
-    SYSTEM_EVENT_MAX
-} system_event_id_t;
-
-/* add this macro define for compatible with old IDF version */
-#ifndef SYSTEM_EVENT_AP_STA_GOT_IP6
-#define SYSTEM_EVENT_AP_STA_GOT_IP6 SYSTEM_EVENT_GOT_IP6
-#endif
-
-typedef enum {
-    WPS_FAIL_REASON_NORMAL = 0,                   /**< ESP32 WPS normal fail reason */
-    WPS_FAIL_REASON_RECV_M2D,                       /**< ESP32 WPS receive M2D frame */
-    WPS_FAIL_REASON_MAX
-}system_event_sta_wps_fail_reason_t;
-typedef struct {
-    uint32_t status;          /**< status of scanning APs */
-    uint8_t  number;
-    uint8_t  scan_id;
-} system_event_sta_scan_done_t;
-
-typedef struct {
-    uint8_t ssid[32];         /**< SSID of connected AP */
-    uint8_t ssid_len;         /**< SSID length of connected AP */
-    uint8_t bssid[6];         /**< BSSID of connected AP*/
-    uint8_t channel;          /**< channel of connected AP*/
-    wifi_auth_mode_t authmode;
-} system_event_sta_connected_t;
-
-typedef struct {
-    uint8_t ssid[32];         /**< SSID of disconnected AP */
-    uint8_t ssid_len;         /**< SSID length of disconnected AP */
-    uint8_t bssid[6];         /**< BSSID of disconnected AP */
-    uint8_t reason;           /**< reason of disconnection */
-} system_event_sta_disconnected_t;
-
-typedef struct {
-    wifi_auth_mode_t old_mode;         /**< the old auth mode of AP */
-    wifi_auth_mode_t new_mode;         /**< the new auth mode of AP */
-} system_event_sta_authmode_change_t;
-
-typedef struct {
-    tcpip_adapter_ip_info_t ip_info;
-    bool ip_changed;
-} system_event_sta_got_ip_t;
-
-typedef struct {
-    uint8_t pin_code[8];         /**< PIN code of station in enrollee mode */
-} system_event_sta_wps_er_pin_t;
-
-typedef struct {
-    tcpip_adapter_if_t if_index;
-    tcpip_adapter_ip6_info_t ip6_info;
-} system_event_got_ip6_t;
-
-typedef struct {
-    uint8_t mac[6];           /**< MAC address of the station connected to ESP32 soft-AP */
-    uint8_t aid;              /**< the aid that ESP32 soft-AP gives to the station connected to  */
-} system_event_ap_staconnected_t;
-
-typedef struct {
-    uint8_t mac[6];           /**< MAC address of the station disconnects to ESP32 soft-AP */
-    uint8_t aid;              /**< the aid that ESP32 soft-AP gave to the station disconnects to  */
-} system_event_ap_stadisconnected_t;
-
-typedef struct {
-    int rssi;                 /**< Received probe request signal strength */
-    uint8_t mac[6];           /**< MAC address of the station which send probe request */
-} system_event_ap_probe_req_rx_t;
-
-typedef struct {
-    ip4_addr_t ip; 
-} system_event_ap_staipassigned_t;
-
-typedef union {
-    system_event_sta_connected_t               connected;          /**< ESP32 station connected to AP */
-    system_event_sta_disconnected_t            disconnected;       /**< ESP32 station disconnected to AP */
-    system_event_sta_scan_done_t               scan_done;          /**< ESP32 station scan (APs) done */
-    system_event_sta_authmode_change_t         auth_change;        /**< the auth mode of AP ESP32 station connected to changed */
-    system_event_sta_got_ip_t                  got_ip;             /**< ESP32 station got IP, first time got IP or when IP is changed */
-    system_event_sta_wps_er_pin_t              sta_er_pin;         /**< ESP32 station WPS enrollee mode PIN code received */
-    system_event_sta_wps_fail_reason_t         sta_er_fail_reason;/**< ESP32 station WPS enrollee mode failed reason code received */
-    system_event_ap_staconnected_t             sta_connected;      /**< a station connected to ESP32 soft-AP */
-    system_event_ap_stadisconnected_t          sta_disconnected;   /**< a station disconnected to ESP32 soft-AP */
-    system_event_ap_probe_req_rx_t             ap_probereqrecved;  /**< ESP32 soft-AP receive probe request packet */
-    system_event_ap_staipassigned_t            ap_staipassigned;   /**< ESP32 soft-AP assign an IP to the station*/
-    system_event_got_ip6_t                     got_ip6;            /**< ESP32 station　or ap or ethernet ipv6 addr state change to preferred */
-} system_event_info_t;
-
-typedef struct {
-    system_event_id_t     event_id;      /**< event ID */
-    system_event_info_t   event_info;    /**< event information */
-} system_event_t;
-
-typedef esp_err_t (*system_event_handler_t)(system_event_t *event);
-
-/**
-  * @brief  Send a event to event task
-  *
-  * @attention 1. Other task/modules, such as the TCPIP module, can call this API to send an event to event task
-  *
-  * @param  system_event_t * event : event
-  *
-  * @return ESP_OK : succeed
-  * @return others : fail
-  */
-esp_err_t esp_event_send(system_event_t *event);
-
-/**
-  * @brief  Default event handler for system events
-  *
-  * This function performs default handling of system events.
-  * When using esp_event_loop APIs, it is called automatically before invoking the user-provided
-  * callback function.
-  *
-  * Applications which implement a custom event loop must call this function
-  * as part of event processing.
-  *
-  * @param  event pointer to event to be handled
-  * @return ESP_OK if an event was handled successfully
-  */
-esp_err_t esp_event_process_default(system_event_t *event);
-
-/**
-  * @brief  Install default event handlers for Ethernet interface
-  *
-  */
-void esp_event_set_default_eth_handlers();
-
-/**
-  * @brief  Install default event handlers for Wi-Fi interfaces (station and AP)
-  *
-  */
-void esp_event_set_default_wifi_handlers();
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_EVENT_H__ */
diff --git a/tools/sdk/include/esp32/esp_event_loop.h b/tools/sdk/include/esp32/esp_event_loop.h
deleted file mode 100644
index 97672aedf2d..00000000000
--- a/tools/sdk/include/esp32/esp_event_loop.h
+++ /dev/null
@@ -1,81 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_EVENT_LOOP_H__
-#define __ESP_EVENT_LOOP_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "esp_err.h"
-#include "esp_event.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/queue.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  * @brief  Application specified event callback function
-  *
-  * @param  void *ctx : reserved for user
-  * @param  system_event_t *event : event type defined in this file
-  *
-  * @return ESP_OK : succeed
-  * @return others : fail
-  */
-typedef esp_err_t (*system_event_cb_t)(void *ctx, system_event_t *event);
-
-/**
-  * @brief  Initialize event loop
-  *         Create the event handler and task
-  *
-  * @param  system_event_cb_t cb : application specified event callback, it can be modified by call esp_event_set_cb
-  * @param  void *ctx : reserved for user
-  *
-  * @return ESP_OK : succeed
-  * @return others : fail
-  */
-esp_err_t esp_event_loop_init(system_event_cb_t cb, void *ctx);
-
-/**
-  * @brief  Set application specified event callback function
-  *
-  * @attention 1. If cb is NULL, means application don't need to handle
-  *               If cb is not NULL, it will be call when an event is received, after the default event callback is completed
-  *
-  * @param  system_event_cb_t cb : callback
-  * @param  void *ctx : reserved for user
-  *
-  * @return system_event_cb_t : old callback
-  */
-system_event_cb_t esp_event_loop_set_cb(system_event_cb_t cb, void *ctx);
-
-/**
-  * @brief  Get the queue used by event loop
-  *
-  * @attention : currently this API is used to initialize "q" parameter
-  * of wifi_init structure.
-  *
-  * @return QueueHandle_t : event queue handle
-  */
-QueueHandle_t esp_event_loop_get_queue(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_EVENT_LOOP_H__ */
diff --git a/tools/sdk/include/esp32/esp_flash_data_types.h b/tools/sdk/include/esp32/esp_flash_data_types.h
deleted file mode 100644
index 998e522f068..00000000000
--- a/tools/sdk/include/esp32/esp_flash_data_types.h
+++ /dev/null
@@ -1,86 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __ESP_BIN_TYPES_H__
-#define __ESP_BIN_TYPES_H__
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#define ESP_PARTITION_MAGIC 0x50AA
-#define ESP_PARTITION_MAGIC_MD5 0xEBEB
-
-/// OTA_DATA states for checking operability of the app.
-typedef enum {
-    ESP_OTA_IMG_NEW             = 0x0U,         /*!< Monitor the first boot. In bootloader this state is changed to ESP_OTA_IMG_PENDING_VERIFY. */
-    ESP_OTA_IMG_PENDING_VERIFY  = 0x1U,         /*!< First boot for this app was. If while the second boot this state is then it will be changed to ABORTED. */
-    ESP_OTA_IMG_VALID           = 0x2U,         /*!< App was confirmed as workable. App can boot and work without limits. */
-    ESP_OTA_IMG_INVALID         = 0x3U,         /*!< App was confirmed as non-workable. This app will not selected to boot at all. */
-    ESP_OTA_IMG_ABORTED         = 0x4U,         /*!< App could not confirm the workable or non-workable. In bootloader IMG_PENDING_VERIFY state will be changed to IMG_ABORTED. This app will not selected to boot at all. */
-    ESP_OTA_IMG_UNDEFINED       = 0xFFFFFFFFU,  /*!< Undefined. App can boot and work without limits. */
-} esp_ota_img_states_t;
-
-/* OTA selection structure (two copies in the OTA data partition.)
-   Size of 32 bytes is friendly to flash encryption */
-typedef struct {
-    uint32_t ota_seq;
-    uint8_t  seq_label[20];
-    uint32_t ota_state;
-    uint32_t crc; /* CRC32 of ota_seq field only */
-} esp_ota_select_entry_t;
-
-
-typedef struct {
-    uint32_t offset;
-    uint32_t size;
-} esp_partition_pos_t;
-
-/* Structure which describes the layout of partition table entry.
- * See docs/partition_tables.rst for more information about individual fields.
- */
-typedef struct {
-	uint16_t magic;
-	uint8_t  type;
-    uint8_t  subtype;
-    esp_partition_pos_t pos;
-	uint8_t  label[16];
-    uint32_t flags;
-} esp_partition_info_t;
-
-#define PART_TYPE_APP 0x00
-#define PART_SUBTYPE_FACTORY  0x00
-#define PART_SUBTYPE_OTA_FLAG 0x10
-#define PART_SUBTYPE_OTA_MASK 0x0f
-#define PART_SUBTYPE_TEST     0x20
-
-#define PART_TYPE_DATA 0x01
-#define PART_SUBTYPE_DATA_OTA 0x00
-#define PART_SUBTYPE_DATA_RF  0x01
-#define PART_SUBTYPE_DATA_WIFI 0x02
-#define PART_SUBTYPE_DATA_NVS_KEYS 0x04
-#define PART_SUBTYPE_DATA_EFUSE_EM 0x05
-
-#define PART_TYPE_END 0xff
-#define PART_SUBTYPE_END 0xff
-
-#define PART_FLAG_ENCRYPTED (1<<0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__ESP_BIN_TYPES_H__
diff --git a/tools/sdk/include/esp32/esp_freertos_hooks.h b/tools/sdk/include/esp32/esp_freertos_hooks.h
deleted file mode 100644
index 5f24bc35a6c..00000000000
--- a/tools/sdk/include/esp32/esp_freertos_hooks.h
+++ /dev/null
@@ -1,131 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_FREERTOS_HOOKS_H__
-#define __ESP_FREERTOS_HOOKS_H__
-
-#include <stdbool.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*
- Definitions for the tickhook and idlehook callbacks
-*/
-typedef bool (*esp_freertos_idle_cb_t)();
-typedef void (*esp_freertos_tick_cb_t)();
-
-/**
-  * @brief  Register a callback to be called from the specified core's idle hook.
-  *         The callback should return true if it should be called by the idle hook
-  *         once per interrupt (or FreeRTOS tick), and return false if it should
-  *         be called repeatedly as fast as possible by the idle hook.
-  *
-  * @warning Idle callbacks MUST NOT, UNDER ANY CIRCUMSTANCES, CALL
-  *          A FUNCTION THAT MIGHT BLOCK.
-  *
-  * @param[in]  new_idle_cb     Callback to be called
-  * @param[in]  cpuid           id of the core
-  *
-  * @return
-  *     - ESP_OK:              Callback registered to the specified core's idle hook
-  *     - ESP_ERR_NO_MEM:      No more space on the specified core's idle hook to register callback
-  *     - ESP_ERR_INVALID_ARG: cpuid is invalid
-  */
-esp_err_t esp_register_freertos_idle_hook_for_cpu(esp_freertos_idle_cb_t new_idle_cb, UBaseType_t cpuid);
-
-/**
-  * @brief  Register a callback to the idle hook of the core that calls this function.
-  *         The callback should return true if it should be called by the idle hook
-  *         once per interrupt (or FreeRTOS tick), and return false if it should
-  *         be called repeatedly as fast as possible by the idle hook.
-  *
-  * @warning Idle callbacks MUST NOT, UNDER ANY CIRCUMSTANCES, CALL
-  *          A FUNCTION THAT MIGHT BLOCK.
-  *
-  * @param[in]  new_idle_cb     Callback to be called
-  *
-  * @return
-  *     - ESP_OK:         Callback registered to the calling core's idle hook
-  *     - ESP_ERR_NO_MEM: No more space on the calling core's idle hook to register callback
-  */
-esp_err_t esp_register_freertos_idle_hook(esp_freertos_idle_cb_t new_idle_cb);
-
-/**
-  * @brief  Register a callback to be called from the specified core's tick hook.
-  *
-  * @param[in]  new_tick_cb     Callback to be called
-  * @param[in]  cpuid           id of the core
-  *
-  * @return
-  *     - ESP_OK:              Callback registered to specified core's tick hook
-  *     - ESP_ERR_NO_MEM:      No more space on the specified core's tick hook to register the callback
-  *     - ESP_ERR_INVALID_ARG: cpuid is invalid
-  */
-esp_err_t esp_register_freertos_tick_hook_for_cpu(esp_freertos_tick_cb_t new_tick_cb, UBaseType_t cpuid);
-
-/**
-  * @brief  Register a callback to be called from the calling core's tick hook.
-  *
-  * @param[in]  new_tick_cb     Callback to be called
-  *
-  * @return
-  *     - ESP_OK:         Callback registered to the calling core's tick hook
-  *     - ESP_ERR_NO_MEM: No more space on the calling core's tick hook to register the callback
-  */
-esp_err_t esp_register_freertos_tick_hook(esp_freertos_tick_cb_t new_tick_cb);
-
-/**
-  * @brief  Unregister an idle callback from the idle hook of the specified core
-  *
-  * @param[in]  old_idle_cb     Callback to be unregistered
-  * @param[in]  cpuid           id of the core
-  */
-void esp_deregister_freertos_idle_hook_for_cpu(esp_freertos_idle_cb_t old_idle_cb, UBaseType_t cpuid);
-
-/**
-  * @brief  Unregister an idle callback. If the idle callback is registered to
-  *         the idle hooks of both cores, the idle hook will be unregistered from
-  *         both cores
-  *
-  * @param[in]  old_idle_cb     Callback to be unregistered
-  */
-void esp_deregister_freertos_idle_hook(esp_freertos_idle_cb_t old_idle_cb);
-
-/**
-  * @brief  Unregister a tick callback from the tick hook of the specified core
-  *
-  * @param[in]  old_tick_cb     Callback to be unregistered
-  * @param[in]  cpuid           id of the core
-  */
-void esp_deregister_freertos_tick_hook_for_cpu(esp_freertos_tick_cb_t old_tick_cb, UBaseType_t cpuid);
-
-/**
-  * @brief  Unregister a tick callback. If the tick callback is registered to the
-  *         tick hooks of both cores, the tick hook will be unregistered from
-  *         both cores
-  *
-  * @param[in]  old_tick_cb     Callback to be unregistered
-  */
-void esp_deregister_freertos_tick_hook(esp_freertos_tick_cb_t old_tick_cb);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_gdbstub.h b/tools/sdk/include/esp32/esp_gdbstub.h
deleted file mode 100644
index 9e7243aad07..00000000000
--- a/tools/sdk/include/esp32/esp_gdbstub.h
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef GDBSTUB_H
-#define GDBSTUB_H
-
-#include <xtensa/config/core.h>
-#include "freertos/xtensa_api.h"
-
-void esp_gdbstub_panic_handler(XtExcFrame *frame) __attribute__((noreturn));
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_himem.h b/tools/sdk/include/esp32/esp_himem.h
deleted file mode 100644
index 099d9260153..00000000000
--- a/tools/sdk/include/esp32/esp_himem.h
+++ /dev/null
@@ -1,152 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include <stddef.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//Opaque pointers as handles for ram/range data
-typedef struct esp_himem_ramdata_t *esp_himem_handle_t;
-typedef struct esp_himem_rangedata_t *esp_himem_rangehandle_t;
-
-//ESP32 MMU block size
-#define ESP_HIMEM_BLKSZ (0x8000)
-
-#define ESP_HIMEM_MAPFLAG_RO 1 /*!< Indicates that a mapping will only be read from. Note that this is unused for now. */
-
-/**
- * @brief Allocate a block in high memory
- *
- * @param size Size of the to-be-allocated block, in bytes. Note that this needs to be
- *             a multiple of the external RAM mmu block size (32K).
- * @param[out] handle_out Handle to be returned
- * @returns - ESP_OK if succesful
- *          - ESP_ERR_NO_MEM if out of memory
- *          - ESP_ERR_INVALID_SIZE if size is not a multiple of 32K
- */
-esp_err_t esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out);
-
-
-/**
- * @brief Allocate a memory region to map blocks into
- * 
- * This allocates a contiguous CPU memory region that can be used to map blocks
- * of physical memory into.
- *
- * @param size Size of the range to be allocated. Note this needs to be a multiple of
- *             the external RAM mmu block size (32K).
- * @param[out] handle_out Handle to be returned
- * @returns - ESP_OK if succesful
- *          - ESP_ERR_NO_MEM if out of memory or address space
- *          - ESP_ERR_INVALID_SIZE if size is not a multiple of 32K
- */
-esp_err_t esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t *handle_out);
-
-/**
- * @brief Map a block of high memory into the CPUs address space
- *
- * This effectively makes the block available for read/write operations.
- * 
- * @note The region to be mapped needs to have offsets and sizes that are aligned to the
- *       SPI RAM MMU block size (32K)
- *
- * @param handle Handle to the block of memory, as given by esp_himem_alloc
- * @param range Range handle to map the memory in
- * @param ram_offset Offset into the block of physical memory of the block to map
- * @param range_offset Offset into the address range where the block will be mapped
- * @param len Length of region to map
- * @param flags One of ESP_HIMEM_MAPFLAG_*
- * @param[out] out_ptr Pointer to variable to store resulting memory pointer in
- * @returns - ESP_OK if the memory could be mapped
- *          - ESP_ERR_INVALID_ARG if offset, range or len aren't MMU-block-aligned (32K)
- *          - ESP_ERR_INVALID_SIZE if the offsets/lengths don't fit in the allocated memory or range
- *          - ESP_ERR_INVALID_STATE if a block in the selected ram offset/length is already mapped, or
- *                                  if a block in the selected range offset/length already has a mapping.
- */
-esp_err_t esp_himem_map(esp_himem_handle_t handle, esp_himem_rangehandle_t range, size_t ram_offset, size_t range_offset, size_t len, int flags, void **out_ptr);
-
-
-/**
- * @brief Free a block of physical memory
- *
- * This clears out the associated handle making the memory available for re-allocation again.
- * This will only succeed if none of the memory blocks currently have a mapping.
- *
- * @param handle Handle to the block of memory, as given by esp_himem_alloc
- * @returns - ESP_OK if the memory is succesfully freed
- *          - ESP_ERR_INVALID_ARG if the handle still is (partially) mapped
- */
-esp_err_t esp_himem_free(esp_himem_handle_t handle);
-
-
-
-/**
- * @brief Free a mapping range
- *
- * This clears out the associated handle making the range available for re-allocation again.
- * This will only succeed if none of the range blocks currently are used for a mapping.
- *
- * @param handle Handle to the range block, as given by esp_himem_alloc_map_range
- * @returns - ESP_OK if the memory is succesfully freed
- *          - ESP_ERR_INVALID_ARG if the handle still is (partially) mapped to
- */
-esp_err_t esp_himem_free_map_range(esp_himem_rangehandle_t handle);
-
-
-/**
- * @brief Unmap a region
- *
- * @param range Range handle
- * @param ptr Pointer returned by esp_himem_map
- * @param len Length of the block to be unmapped. Must be aligned to the SPI RAM MMU blocksize (32K)
- * @returns - ESP_OK if the memory is succesfully unmapped,
- *          - ESP_ERR_INVALID_ARG if ptr or len are invalid.
- */
-esp_err_t esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len);
-
-
-/**
- * @brief Get total amount of memory under control of himem API
- *
- * @returns Amount of memory, in bytes
- */
-size_t esp_himem_get_phys_size();
-
-/**
- * @brief Get free amount of memory under control of himem API
- *
- * @returns Amount of free memory, in bytes
- */
-size_t esp_himem_get_free_size();
-
-
-/**
- * @brief Get amount of SPI memory address space needed for bankswitching
- *
- * @note This is also weakly defined in esp32/spiram.c and returns 0 there, so
- *       if no other function in this file is used, no memory is reserved.
- *
- * @returns Amount of reserved area, in bytes
- */
-size_t esp_himem_reserved_area_size();
-
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/tools/sdk/include/esp32/esp_idf_version.h b/tools/sdk/include/esp32/esp_idf_version.h
deleted file mode 100644
index 6b59e6b2789..00000000000
--- a/tools/sdk/include/esp32/esp_idf_version.h
+++ /dev/null
@@ -1,62 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Major version number (X.x.x) */
-#define ESP_IDF_VERSION_MAJOR   3
-/** Minor version number (x.X.x) */
-#define ESP_IDF_VERSION_MINOR   3
-/** Patch version number (x.x.X) */
-#define ESP_IDF_VERSION_PATCH   4
-
-/**
- * Macro to convert IDF version number into an integer
- *
- * To be used in comparisons, such as ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 0, 0)
- */
-#define ESP_IDF_VERSION_VAL(major, minor, patch) ((major << 16) | (minor << 8) | (patch))
-
-/**
- * Current IDF version, as an integer
- *
- * To be used in comparisons, such as ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 0, 0)
- */
-#define ESP_IDF_VERSION  ESP_IDF_VERSION_VAL(ESP_IDF_VERSION_MAJOR, \
-                                             ESP_IDF_VERSION_MINOR, \
-                                             ESP_IDF_VERSION_PATCH)
-
-#ifndef __ASSEMBLER__
-
-/**
- * Return full IDF version string, same as 'git describe' output.
- *
- * @note If you are printing the ESP-IDF version in a log file or other information,
- * this function provides more information than using the numerical version macros.
- * For example, numerical version macros don't differentiate between development,
- * pre-release and release versions, but the output of this function does.
- *
- * @return constant string from IDF_VER
- */
-const char* esp_get_idf_version(void);
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp32/esp_int_wdt.h b/tools/sdk/include/esp32/esp_int_wdt.h
deleted file mode 100644
index f581d939ad8..00000000000
--- a/tools/sdk/include/esp32/esp_int_wdt.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_INT_WDT_H
-#define __ESP_INT_WDT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup Watchdog_APIs
-  * @{
-  */
-
-/*
-This routine enables a watchdog to catch instances of processes disabling
-interrupts for too long, or code within interrupt handlers taking too long. 
-It does this by setting up a watchdog which gets fed from the FreeRTOS
-task switch interrupt. When this watchdog times out, initially it will call
-a high-level interrupt routine that will panic FreeRTOS in order to allow
-for forensic examination of the state of the both CPUs. When this interrupt
-handler is not called and the watchdog times out a second time, it will 
-reset the SoC.
-
-This uses the TIMERG1 WDT.
-*/
-
-
-/**
-  * @brief  Initialize the non-CPU-specific parts of interrupt watchdog.
-  *         This is called in the init code if the interrupt watchdog
-  *         is enabled in menuconfig.
-  *
-  */
-void esp_int_wdt_init();
-
-/**
-  * @brief  Enable the interrupt watchdog on the current CPU. This is called
-  *         in the init code by both CPUs if the interrupt watchdog is enabled
-  *         in menuconfig.
-  *
-  */
-void esp_int_wdt_cpu_init();
-
-
-
-/**
-  * @}
-  */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_interface.h b/tools/sdk/include/esp32/esp_interface.h
deleted file mode 100644
index 950c05bb22c..00000000000
--- a/tools/sdk/include/esp32/esp_interface.h
+++ /dev/null
@@ -1,37 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_INTERFACE_H__
-#define __ESP_INTERFACE_H__
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ESP_IF_WIFI_STA = 0,     /**< ESP32 station interface */
-    ESP_IF_WIFI_AP,          /**< ESP32 soft-AP interface */
-    ESP_IF_ETH,              /**< ESP32 ethernet interface */
-    ESP_IF_MAX
-} esp_interface_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __ESP_INTERFACE_TYPES_H__ */
diff --git a/tools/sdk/include/esp32/esp_intr.h b/tools/sdk/include/esp32/esp_intr.h
deleted file mode 100644
index 579eb6353d8..00000000000
--- a/tools/sdk/include/esp32/esp_intr.h
+++ /dev/null
@@ -1,89 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_INTR_H__
-#define __ESP_INTR_H__
-
-#include "rom/ets_sys.h"
-#include "freertos/xtensa_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ESP_CCOMPARE_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_CCOMPARE_INUM, (func), (void *)(arg))
-
-#define ESP_EPWM_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_EPWM_INUM, (func), (void *)(arg))
-
-#define ESP_MPWM_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_MPWM_INUM, (func), (void *)(arg))
-
-#define ESP_SPI1_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_SPI1_INUM, (func), (void *)(arg))
-
-#define ESP_SPI2_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_SPI2_INUM, (func), (void *)(arg))
-
-#define ESP_SPI3_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_SPI3_INUM, (func), (void *)(arg))
-
-#define ESP_I2S0_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_I2S0_INUM, (func), (void *)(arg))
-
-#define ESP_PCNT_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_PCNT_INUM, (func), (void *)(arg))
-
-#define ESP_LEDC_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_LEDC_INUM, (func), (void *)(arg))
-
-#define ESP_WMAC_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_WMAC_INUM, (func), (void *)(arg))
-
-#define ESP_FRC_TIMER1_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))
-
-#define ESP_FRC_TIMER2_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_FRC_TIMER2_INUM, (func), (void *)(arg))
-
-#define ESP_GPIO_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg))
-
-#define ESP_UART0_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg))
-
-#define ESP_WDT_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg))
-
-#define ESP_RTC_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_RTC_INUM, (func), (void *)(arg))
-
-#define ESP_SLC_INTR_ATTACH(func, arg) \
-    xt_set_interrupt_handler(ETS_SLC_INUM, (func), (void *)(arg))
-
-#define ESP_RMT_CTRL_INTRL(func,arg)\
-    xt_set_interrupt_handler(ETS_RMT_CTRL_INUM, (func), (void *)(arg))
-
-#define ESP_INTR_ENABLE(inum) \
-    xt_ints_on((1<<inum))
-
-#define ESP_INTR_DISABLE(inum) \
-    xt_ints_off((1<<inum))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_INTR_H__ */
diff --git a/tools/sdk/include/esp32/esp_intr_alloc.h b/tools/sdk/include/esp32/esp_intr_alloc.h
deleted file mode 100644
index edc4b9f2df3..00000000000
--- a/tools/sdk/include/esp32/esp_intr_alloc.h
+++ /dev/null
@@ -1,296 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_INTR_ALLOC_H__
-#define __ESP_INTR_ALLOC_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/** @addtogroup Intr_Alloc
-  * @{
-  */
-
-
-/** @brief Interrupt allocation flags
- *
- * These flags can be used to specify which interrupt qualities the
- * code calling esp_intr_alloc* needs.
- *
- */
-
-//Keep the LEVELx values as they are here; they match up with (1<<level)
-#define ESP_INTR_FLAG_LEVEL1		(1<<1)	///< Accept a Level 1 interrupt vector (lowest priority)
-#define ESP_INTR_FLAG_LEVEL2		(1<<2)	///< Accept a Level 2 interrupt vector
-#define ESP_INTR_FLAG_LEVEL3		(1<<3)	///< Accept a Level 3 interrupt vector
-#define ESP_INTR_FLAG_LEVEL4		(1<<4)	///< Accept a Level 4 interrupt vector
-#define ESP_INTR_FLAG_LEVEL5		(1<<5)	///< Accept a Level 5 interrupt vector
-#define ESP_INTR_FLAG_LEVEL6		(1<<6)	///< Accept a Level 6 interrupt vector
-#define ESP_INTR_FLAG_NMI			(1<<7)	///< Accept a Level 7 interrupt vector (highest priority)
-#define ESP_INTR_FLAG_SHARED		(1<<8)	///< Interrupt can be shared between ISRs
-#define ESP_INTR_FLAG_EDGE			(1<<9)	///< Edge-triggered interrupt
-#define ESP_INTR_FLAG_IRAM			(1<<10)	///< ISR can be called if cache is disabled
-#define ESP_INTR_FLAG_INTRDISABLED	(1<<11)	///< Return with this interrupt disabled
-
-#define ESP_INTR_FLAG_LOWMED	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) ///< Low and medium prio interrupts. These can be handled in C.
-#define ESP_INTR_FLAG_HIGH		(ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6|ESP_INTR_FLAG_NMI) ///< High level interrupts. Need to be handled in assembly.
-
-#define ESP_INTR_FLAG_LEVELMASK	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
-								 ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
-								 ESP_INTR_FLAG_NMI) ///< Mask for all level flags
-/**@}*/
-
-
-/** @addtogroup Intr_Alloc_Pseudo_Src
-  * @{
-  */
-
-/**
- * The esp_intr_alloc* functions can allocate an int for all ETS_*_INTR_SOURCE interrupt sources that
- * are routed through the interrupt mux. Apart from these sources, each core also has some internal
- * sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
- * pass these pseudo-sources to the functions.
- */
-#define ETS_INTERNAL_TIMER0_INTR_SOURCE		-1 ///< Xtensa timer 0 interrupt source
-#define ETS_INTERNAL_TIMER1_INTR_SOURCE		-2 ///< Xtensa timer 1 interrupt source
-#define ETS_INTERNAL_TIMER2_INTR_SOURCE		-3 ///< Xtensa timer 2 interrupt source
-#define ETS_INTERNAL_SW0_INTR_SOURCE		-4 ///< Software int source 1
-#define ETS_INTERNAL_SW1_INTR_SOURCE		-5 ///< Software int source 2
-#define ETS_INTERNAL_PROFILING_INTR_SOURCE	-6 ///< Int source for profiling
-
-/**@}*/
-
-// This is used to provide SystemView with positive IRQ IDs, otherwise sheduler events are not shown properly
-#define ETS_INTERNAL_INTR_SOURCE_OFF		(-ETS_INTERNAL_PROFILING_INTR_SOURCE)
-
-typedef void (*intr_handler_t)(void *arg); 
-
-
-typedef struct intr_handle_data_t intr_handle_data_t;
-typedef intr_handle_data_t* intr_handle_t ;
-
-/**
- * @brief Mark an interrupt as a shared interrupt
- * 
- * This will mark a certain interrupt on the specified CPU as
- * an interrupt that can be used to hook shared interrupt handlers
- * to.
- *
- * @param intno The number of the interrupt (0-31)
- * @param cpu CPU on which the interrupt should be marked as shared (0 or 1)
- * @param is_in_iram Shared interrupt is for handlers that reside in IRAM and
- *                   the int can be left enabled while the flash cache is disabled.
- *
- * @return ESP_ERR_INVALID_ARG if cpu or intno is invalid
- *         ESP_OK otherwise
- */
-esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_in_iram);
-
-/**
- * @brief Reserve an interrupt to be used outside of this framework
- * 
- * This will mark a certain interrupt on the specified CPU as
- * reserved, not to be allocated for any reason.
- *
- * @param intno The number of the interrupt (0-31)
- * @param cpu CPU on which the interrupt should be marked as shared (0 or 1)
- *
- * @return ESP_ERR_INVALID_ARG if cpu or intno is invalid
- *         ESP_OK otherwise
- */
-esp_err_t esp_intr_reserve(int intno, int cpu);
-
-/**
- * @brief Allocate an interrupt with the given parameters.
- *
- * This finds an interrupt that matches the restrictions as given in the flags
- * parameter, maps the given interrupt source to it and hooks up the given
- * interrupt handler (with optional argument) as well. If needed, it can return
- * a handle for the interrupt as well.
- *
- * The interrupt will always be allocated on the core that runs this function.
- *
- * If ESP_INTR_FLAG_IRAM flag is used, and handler address is not in IRAM or
- * RTC_FAST_MEM, then ESP_ERR_INVALID_ARG is returned.
- *
- * @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux
- *               sources, as defined in soc/soc.h, or one of the internal
- *               ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header.
- * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the
- *               choice of interrupts that this routine can choose from. If this value
- *               is 0, it will default to allocating a non-shared interrupt of level
- *               1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
- *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 
- *               from this function with the interrupt disabled.
- * @param handler The interrupt handler. Must be NULL when an interrupt of level >3
- *               is requested, because these types of interrupts aren't C-callable.
- * @param arg    Optional argument for passed to the interrupt handler
- * @param ret_handle Pointer to an intr_handle_t to store a handle that can later be
- *               used to request details or free the interrupt. Can be NULL if no handle
- *               is required.
- *
- * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
- *         ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
- *         ESP_OK otherwise
- */
-esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *arg, intr_handle_t *ret_handle);
-
-
-/**
- * @brief Allocate an interrupt with the given parameters.
- *
- *
- * This essentially does the same as esp_intr_alloc, but allows specifying a register and mask
- * combo. For shared interrupts, the handler is only called if a read from the specified 
- * register, ANDed with the mask, returns non-zero. By passing an interrupt status register
- * address and a fitting mask, this can be used to accelerate interrupt handling in the case
- * a shared interrupt is triggered; by checking the interrupt statuses first, the code can
- * decide which ISRs can be skipped
- *
- * @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux
- *               sources, as defined in soc/soc.h, or one of the internal
- *               ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header.
- * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the
- *               choice of interrupts that this routine can choose from. If this value
- *               is 0, it will default to allocating a non-shared interrupt of level
- *               1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
- *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 
- *               from this function with the interrupt disabled.
- * @param intrstatusreg The address of an interrupt status register
- * @param intrstatusmask A mask. If a read of address intrstatusreg has any of the bits
- *               that are 1 in the mask set, the ISR will be called. If not, it will be
- *               skipped.
- * @param handler The interrupt handler. Must be NULL when an interrupt of level >3
- *               is requested, because these types of interrupts aren't C-callable.
- * @param arg    Optional argument for passed to the interrupt handler
- * @param ret_handle Pointer to an intr_handle_t to store a handle that can later be
- *               used to request details or free the interrupt. Can be NULL if no handle
- *               is required.
- *
- * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
- *         ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
- *         ESP_OK otherwise
- */
-esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusreg, uint32_t intrstatusmask, intr_handler_t handler, void *arg, intr_handle_t *ret_handle);
-
-
-/**
- * @brief Disable and free an interrupt.
- *
- * Use an interrupt handle to disable the interrupt and release the resources associated with it.
- * If the current core is not the core that registered this interrupt, this routine will be assigned to
- * the core that allocated this interrupt, blocking and waiting until the resource is successfully released.
- *
- * @note 
- * When the handler shares its source with other handlers, the interrupt status 
- * bits it's responsible for should be managed properly before freeing it. see 
- * ``esp_intr_disable`` for more details. Please do not call this function in ``esp_ipc_call_blocking``.
- *
- * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
- *
- * @return ESP_ERR_INVALID_ARG the handle is NULL
- *         ESP_FAIL failed to release this handle
- *         ESP_OK otherwise
- */
-esp_err_t esp_intr_free(intr_handle_t handle);
-
-
-/**
- * @brief Get CPU number an interrupt is tied to
- * 
- * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
- *
- * @return The core number where the interrupt is allocated
- */
-int esp_intr_get_cpu(intr_handle_t handle);
-
-/**
- * @brief Get the allocated interrupt for a certain handle
- * 
- * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
- *
- * @return The interrupt number
- */
-int esp_intr_get_intno(intr_handle_t handle);
-
-/**
- * @brief Disable the interrupt associated with the handle
- * 
- * @note 
- * 1. For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
- * CPU the interrupt is allocated on. Other interrupts have no such restriction.
- * 2. When several handlers sharing a same interrupt source, interrupt status bits, which are 
- * handled in the handler to be disabled, should be masked before the disabling, or handled
- * in other enabled interrupts properly. Miss of interrupt status handling will cause infinite 
- * interrupt calls and finally system crash.
- *
- * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
- *
- * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
- *         ESP_OK otherwise
- */
-esp_err_t esp_intr_disable(intr_handle_t handle);
-
-/**
- * @brief Enable the interrupt associated with the handle
- *
- * @note For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
- *       CPU the interrupt is allocated on. Other interrupts have no such restriction.
- *
- * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
- *
- * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
- *         ESP_OK otherwise
- */
-esp_err_t esp_intr_enable(intr_handle_t handle);
-
-/**
- * @brief Set the "in IRAM" status of the handler.
- *
- * @note Does not work on shared interrupts.
- *
- * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
- * @param is_in_iram Whether the handler associated with this handle resides in IRAM.
- *                   Handlers residing in IRAM can be called when cache is disabled.
- *
- * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
- *         ESP_OK otherwise
- */
-esp_err_t esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram);
-
-/**
- * @brief Disable interrupts that aren't specifically marked as running from IRAM
- */
-void esp_intr_noniram_disable();
-
-
-/**
- * @brief Re-enable interrupts disabled by esp_intr_noniram_disable
- */
-void esp_intr_noniram_enable();
-
-/**@}*/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_ipc.h b/tools/sdk/include/esp32/esp_ipc.h
deleted file mode 100644
index 477b3d0af4e..00000000000
--- a/tools/sdk/include/esp32/esp_ipc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_IPC_H__
-#define __ESP_IPC_H__
-
-#include <esp_err.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/** @cond */
-typedef void (*esp_ipc_func_t)(void* arg);
-/** @endcond */
-/*
- * Inter-processor call APIs
- *
- * FreeRTOS provides several APIs which can be used to communicate between
- * different tasks, including tasks running on different CPUs.
- * This module provides additional APIs to run some code on the other CPU.
- *
- * These APIs can only be used when FreeRTOS scheduler is running.
- */
-
-/**
- * @brief Execute a function on the given CPU
- *
- * Run a given function on a particular CPU. The given function must accept a
- * void* argument and return void. The given function is run in the context of
- * the IPC task of the CPU specified by the cpu_id parameter. The calling task
- * will be blocked until the IPC task begins executing the given function. If
- * another IPC call is ongoing, the calling task will block until the other IPC
- * call completes. The stack size allocated for the IPC task can be configured
- * in the "Inter-Processor Call (IPC) task stack size" setting in menuconfig.
- * Increase this setting if the given function requires more stack than default.
- *
- * @note In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1.
- *
- * @param[in]   cpu_id  CPU where the given function should be executed (0 or 1)
- * @param[in]   func    Pointer to a function of type void func(void* arg) to be executed
- * @param[in]   arg     Arbitrary argument of type void* to be passed into the function
- *
- * @return
- *      - ESP_ERR_INVALID_ARG if cpu_id is invalid
- *      - ESP_ERR_INVALID_STATE if the FreeRTOS scheduler is not running
- *      - ESP_OK otherwise
- */
-esp_err_t esp_ipc_call(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
-
-
-/**
- * @brief Execute a function on the given CPU and blocks until it completes
- *
- * Run a given function on a particular CPU. The given function must accept a
- * void* argument and return void. The given function is run in the context of
- * the IPC task of the CPU specified by the cpu_id parameter. The calling task
- * will be blocked until the IPC task completes execution of the given function.
- * If another IPC call is ongoing, the calling task will block until the other
- * IPC call completes. The stack size allocated for the IPC task can be
- * configured in the "Inter-Processor Call (IPC) task stack size" setting in
- * menuconfig. Increase this setting if the given function requires more stack
- * than default.
- *
- * @note    In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1.
- *
- * @param[in]   cpu_id  CPU where the given function should be executed (0 or 1)
- * @param[in]   func    Pointer to a function of type void func(void* arg) to be executed
- * @param[in]   arg     Arbitrary argument of type void* to be passed into the function
- *
- * @return
- *      - ESP_ERR_INVALID_ARG if cpu_id is invalid
- *      - ESP_ERR_INVALID_STATE if the FreeRTOS scheduler is not running
- *      - ESP_OK otherwise
- */
-esp_err_t esp_ipc_call_blocking(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_IPC_H__ */
diff --git a/tools/sdk/include/esp32/esp_mesh.h b/tools/sdk/include/esp32/esp_mesh.h
deleted file mode 100644
index e703ec8280a..00000000000
--- a/tools/sdk/include/esp32/esp_mesh.h
+++ /dev/null
@@ -1,1499 +0,0 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-/*
- *   Software Stack demonstrated:
- *  |------------------------------------------------------------------------------|
- *  |            |                                                                 |
- *  |            |                          Application                            |
- *  |            |-----------------------------------------------------------------|
- *  |            |               | Protocols: |      |      |               |      |
- *  |            |   Mesh Stack  | HTTP, DNS, |      |      |     Other     |      |
- *  |   RTOS:    | (Networking,  | DHCP, ...  |      |      |   Components  |      |
- *  | (freeRTOS) | self-healing, |------------|      |      |               |      |
- *  |            | flow control, |  Network Stack:   |      |               |      |
- *  |            | ...)          |      (LwIP)       |      |               |      |
- *  |            |-----------------------------------|      |---------------|      |
- *  |            |                                                  |              |
- *  |            |                       Wi-Fi Driver               |              |
- *  |            |--------------------------------------------------|              |
- *  |            |                                                                 |
- *  |            |                       Platform HAL                              |
- *  |------------------------------------------------------------------------------|
- *
- *   System Events delivery:
- *
- *  |---------------|
- *  |               |                    default handler
- *  |  Wi-Fi stack  |     events     |---------------------|
- *  |               | -------------> |                     |
- *  |---------------|                |                     |
- *                                   |      event task     |
- *  |---------------|     events     |                     |
- *  |               | -------------> |                     |
- *  |  LwIP stack   |                |---------------------|
- *  |               |--------|
- *  |---------------|        |
- *                           |         mesh event callback handler
- *                           |       |----------------------------|
- *                           |-----> |                            |
- *  |---------------|                |        application         |
- *  |               |     events     |            task            |
- *  |  mesh stack   | -------------> |                            |
- *  |               |                |----------------------------|
- *  |---------------|
- *
- *
- *  Mesh Stack
- *
- *  Mesh event defines almost all system events applications tasks need.
- *  Mesh event contains Wi-Fi connection states on station interface, children connection states on softAP interface and etc..
- *  Applications need to register a mesh event callback handler by API esp_mesh_set_config() firstly.
- *  This handler is to receive events posted from mesh stack and LwIP stack.
- *  Applications could add relative handler for each event.
- *  Examples:
- *  (1) Applications could use Wi-Fi station connect states to decide when to send data to its parent, to the root or to external IP network;
- *  (2) Applications could use Wi-Fi softAP states to decide when to send data to its children.
- *
- *  In present implementation, applications are able to access mesh stack directly without having to go through LwIP stack.
- *  Applications use esp_mesh_send() and esp_mesh_recv() to send and receive messages over the mesh network.
- *  In mesh stack design, normal devices don't require LwIP stack. But since IDF hasn't supported system without initializing LwIP stack yet,
- *  applications still need to do LwIP initialization and two more things are required to be done
- *  (1) stop DHCP server on softAP interface by default
- *  (2) stop DHCP client on station interface by default.
- *  Examples:
- *  tcpip_adapter_init();
- *  tcpip_adapter_dhcps_stop(TCPIP_ADAPTER_IF_AP)；
- *  tcpip_adapter_dhcpc_stop(TCPIP_ADAPTER_IF_STA)；
- *
- *  Over the mesh network, only the root is able to access external IP network.
- *  In application mesh event handler, once a device becomes a root, start DHCP client immediately whether DHCP is chosen.
- */
-
-#ifndef __ESP_MESH_H__
-#define __ESP_MESH_H__
-
-#include "esp_err.h"
-#include "esp_wifi.h"
-#include "esp_wifi_types.h"
-#include "esp_mesh_internal.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*******************************************************
- *                Constants
- *******************************************************/
-#define MESH_ROOT_LAYER                   (1)       /**< root layer value */
-#define MESH_MTU                          (1500)    /**< max transmit unit(in bytes) */
-#define MESH_MPS                          (1472)    /**< max payload size(in bytes) */
-/**
- * @brief Mesh error code definition
- */
-#define ESP_ERR_MESH_WIFI_NOT_START       (ESP_ERR_MESH_BASE + 1)    /**< Wi-Fi isn't started */
-#define ESP_ERR_MESH_NOT_INIT             (ESP_ERR_MESH_BASE + 2)    /**< mesh isn't initialized */
-#define ESP_ERR_MESH_NOT_CONFIG           (ESP_ERR_MESH_BASE + 3)    /**< mesh isn't configured */
-#define ESP_ERR_MESH_NOT_START            (ESP_ERR_MESH_BASE + 4)    /**< mesh isn't started */
-#define ESP_ERR_MESH_NOT_SUPPORT          (ESP_ERR_MESH_BASE + 5)    /**< not supported yet */
-#define ESP_ERR_MESH_NOT_ALLOWED          (ESP_ERR_MESH_BASE + 6)    /**< operation is not allowed */
-#define ESP_ERR_MESH_NO_MEMORY            (ESP_ERR_MESH_BASE + 7)    /**< out of memory */
-#define ESP_ERR_MESH_ARGUMENT             (ESP_ERR_MESH_BASE + 8)    /**< illegal argument */
-#define ESP_ERR_MESH_EXCEED_MTU           (ESP_ERR_MESH_BASE + 9)    /**< packet size exceeds MTU */
-#define ESP_ERR_MESH_TIMEOUT              (ESP_ERR_MESH_BASE + 10)   /**< timeout */
-#define ESP_ERR_MESH_DISCONNECTED         (ESP_ERR_MESH_BASE + 11)   /**< disconnected with parent on station interface */
-#define ESP_ERR_MESH_QUEUE_FAIL           (ESP_ERR_MESH_BASE + 12)   /**< queue fail */
-#define ESP_ERR_MESH_QUEUE_FULL           (ESP_ERR_MESH_BASE + 13)   /**< queue full */
-#define ESP_ERR_MESH_NO_PARENT_FOUND      (ESP_ERR_MESH_BASE + 14)   /**< no parent found to join the mesh network */
-#define ESP_ERR_MESH_NO_ROUTE_FOUND       (ESP_ERR_MESH_BASE + 15)   /**< no route found to forward the packet */
-#define ESP_ERR_MESH_OPTION_NULL          (ESP_ERR_MESH_BASE + 16)   /**< no option found */
-#define ESP_ERR_MESH_OPTION_UNKNOWN       (ESP_ERR_MESH_BASE + 17)   /**< unknown option */
-#define ESP_ERR_MESH_XON_NO_WINDOW        (ESP_ERR_MESH_BASE + 18)   /**< no window for software flow control on upstream */
-#define ESP_ERR_MESH_INTERFACE            (ESP_ERR_MESH_BASE + 19)   /**< low-level Wi-Fi interface error */
-#define ESP_ERR_MESH_DISCARD_DUPLICATE    (ESP_ERR_MESH_BASE + 20)   /**< discard the packet due to the duplicate sequence number */
-#define ESP_ERR_MESH_DISCARD              (ESP_ERR_MESH_BASE + 21)   /**< discard the packet */
-#define ESP_ERR_MESH_VOTING               (ESP_ERR_MESH_BASE + 22)   /**< vote in progress */
-#define ESP_ERR_MESH_XMIT                 (ESP_ERR_MESH_BASE + 23)   /**< XMIT */
-#define ESP_ERR_MESH_QUEUE_READ           (ESP_ERR_MESH_BASE + 24)   /**< error in reading queue */
-#define ESP_ERR_MESH_RECV_RELEASE         (ESP_ERR_MESH_BASE + 26)   /**< release esp_mesh_recv_toDS */
-
-/**
- * @brief Flags bitmap for esp_mesh_send() and esp_mesh_recv()
- */
-#define MESH_DATA_ENC           (0x01)  /**< data encrypted (Unimplemented) */
-#define MESH_DATA_P2P           (0x02)  /**< point-to-point delivery over the mesh network */
-#define MESH_DATA_FROMDS        (0x04)  /**< receive from external IP network */
-#define MESH_DATA_TODS          (0x08)  /**< identify this packet is target to external IP network */
-#define MESH_DATA_NONBLOCK      (0x10)  /**< esp_mesh_send() non-block */
-#define MESH_DATA_DROP          (0x20)  /**< in the situation of the root having been changed, identify this packet can be dropped by new root */
-#define MESH_DATA_GROUP         (0x40)  /**< identify this packet is target to a group address */
-
-/**
- * @brief Option definitions for esp_mesh_send() and esp_mesh_recv()
- */
-#define MESH_OPT_SEND_GROUP     (7)     /**< data transmission by group; used with esp_mesh_send() and shall have payload */
-#define MESH_OPT_RECV_DS_ADDR   (8)     /**< return a remote IP address; used with esp_mesh_send() and esp_mesh_recv() */
-
-/**
- * @brief Flag of mesh networking IE
- */
-#define MESH_ASSOC_FLAG_VOTE_IN_PROGRESS    (0x02)     /**< vote in progress */
-#define MESH_ASSOC_FLAG_NETWORK_FREE        (0x08)     /**< no root in current network */
-#define MESH_ASSOC_FLAG_ROOTS_FOUND         (0x20)     /**< root conflict is found */
-#define MESH_ASSOC_FLAG_ROOT_FIXED          (0x40)     /**< fixed root */
-
-/*******************************************************
- *                Enumerations
- *******************************************************/
-/**
- * @brief Enumerated list of mesh event id
- */
-typedef enum {
-    MESH_EVENT_STARTED,                 /**< mesh is started */
-    MESH_EVENT_STOPPED,                 /**< mesh is stopped */
-    MESH_EVENT_CHANNEL_SWITCH,          /**< channel switch */
-    MESH_EVENT_CHILD_CONNECTED,         /**< a child is connected on softAP interface */
-    MESH_EVENT_CHILD_DISCONNECTED,      /**< a child is disconnected on softAP interface */
-    MESH_EVENT_ROUTING_TABLE_ADD,       /**< routing table is changed by adding newly joined children */
-    MESH_EVENT_ROUTING_TABLE_REMOVE,    /**< routing table is changed by removing leave children */
-    MESH_EVENT_PARENT_CONNECTED,        /**< parent is connected on station interface */
-    MESH_EVENT_PARENT_DISCONNECTED,     /**< parent is disconnected on station interface */
-    MESH_EVENT_NO_PARENT_FOUND,         /**< no parent found */
-    MESH_EVENT_LAYER_CHANGE,            /**< layer changes over the mesh network */
-    MESH_EVENT_TODS_STATE,              /**< state represents whether the root is able to access external IP network */
-    MESH_EVENT_VOTE_STARTED,            /**< the process of voting a new root is started either by children or by the root */
-    MESH_EVENT_VOTE_STOPPED,            /**< the process of voting a new root is stopped */
-    MESH_EVENT_ROOT_ADDRESS,            /**< the root address is obtained. It is posted by mesh stack automatically. */
-    MESH_EVENT_ROOT_SWITCH_REQ,         /**< root switch request sent from a new voted root candidate */
-    MESH_EVENT_ROOT_SWITCH_ACK,         /**< root switch acknowledgment responds the above request sent from current root */
-    MESH_EVENT_ROOT_GOT_IP,             /**< the root obtains the IP address. It is posted by LwIP stack automatically */
-    MESH_EVENT_ROOT_LOST_IP,            /**< the root loses the IP address. It is posted by LwIP stack automatically */
-    MESH_EVENT_ROOT_ASKED_YIELD,        /**< the root is asked yield by a more powerful existing root. If self organized is disabled
-                                             and this device is specified to be a root by users, users should set a new parent
-                                             for this device. if self organized is enabled, this device will find a new parent
-                                             by itself, users could ignore this event. */
-    MESH_EVENT_ROOT_FIXED,              /**< when devices join a network, if the setting of Fixed Root for one device is different
-                                             from that of its parent, the device will update the setting the same as its parent's.
-                                             Fixed Root Setting of each device is variable as that setting changes of the root. */
-    MESH_EVENT_SCAN_DONE,               /**< if self-organized networking is disabled, user can call esp_wifi_scan_start() to trigger
-                                             this event, and add the corresponding scan done handler in this event. */
-    MESH_EVENT_NETWORK_STATE,           /**< network state, such as whether current mesh network has a root. */
-    MESH_EVENT_STOP_RECONNECTION,       /**< the root stops reconnecting to the router and non-root devices stop reconnecting to their parents. */
-    MESH_EVENT_FIND_NETWORK,            /**< when the channel field in mesh configuration is set to zero, mesh stack will perform a
-                                             full channel scan to find a mesh network that can join, and return the channel value
-                                             after finding it. */
-    MESH_EVENT_ROUTER_SWITCH,           /**< if users specify BSSID of the router in mesh configuration, when the root connects to another
-                                             router with the same SSID, this event will be posted and the new router information is attached. */
-    MESH_EVENT_MAX,
-} mesh_event_id_t;
-
-/**
- * @brief Device type
- */
-typedef enum {
-    MESH_IDLE,    /**< hasn't joined the mesh network yet */
-    MESH_ROOT,    /**< the only sink of the mesh network. Has the ability to access external IP network */
-    MESH_NODE,    /**< intermediate device. Has the ability to forward packets over the mesh network */
-    MESH_LEAF,    /**< has no forwarding ability */
-    MESH_STA,     /**< connect to router with a standlone Wi-Fi station mode, no network expansion capability */
-} mesh_type_t;
-
-/**
- * @brief Protocol of transmitted application data
- */
-typedef enum {
-    MESH_PROTO_BIN,     /**< binary */
-    MESH_PROTO_HTTP,    /**< HTTP protocol */
-    MESH_PROTO_JSON,    /**< JSON format */
-    MESH_PROTO_MQTT,    /**< MQTT protocol */
-} mesh_proto_t;
-
-/**
- * @brief For reliable transmission, mesh stack provides three type of services
- */
-typedef enum {
-    MESH_TOS_P2P,    /**< provide P2P (point-to-point) retransmission on mesh stack by default */
-    MESH_TOS_E2E,    /**< provide E2E (end-to-end) retransmission on mesh stack (Unimplemented) */
-    MESH_TOS_DEF,    /**< no retransmission on mesh stack */
-} mesh_tos_t;
-
-/**
- * @brief Vote reason
- */
-typedef enum {
-    MESH_VOTE_REASON_ROOT_INITIATED = 1,    /**< vote is initiated by the root */
-    MESH_VOTE_REASON_CHILD_INITIATED,       /**< vote is initiated by children */
-} mesh_vote_reason_t;
-
-/**
- * @brief Mesh disconnect reason code
- */
-typedef enum {
-    MESH_REASON_CYCLIC = 100,               /**< cyclic is detected */
-    MESH_REASON_PARENT_IDLE,                /**< parent is idle */
-    MESH_REASON_LEAF,                       /**< the connected device is changed to a leaf */
-    MESH_REASON_DIFF_ID,                    /**< in different mesh ID */
-    MESH_REASON_ROOTS,                      /**< root conflict is detected */
-    MESH_REASON_PARENT_STOPPED,             /**< parent has stopped the mesh */
-    MESH_REASON_SCAN_FAIL,                  /**< scan fail */
-    MESH_REASON_IE_UNKNOWN,                 /**< unknown IE */
-    MESH_REASON_WAIVE_ROOT,                 /**< waive root */
-    MESH_REASON_PARENT_WORSE,               /**< parent with very poor RSSI */
-    MESH_REASON_EMPTY_PASSWORD,             /**< use an empty password to connect to an encrypted parent */
-    MESH_REASON_PARENT_UNENCRYPTED,         /**< connect to an unencrypted parent/router */
-} mesh_disconnect_reason_t;
-
-/*******************************************************
- *                Structures
- *******************************************************/
-/**
- * @brief IP address and port
- */
-typedef struct {
-    ip4_addr_t ip4;    /**< IP address */
-    uint16_t port;     /**< port */
-} __attribute__((packed)) mip_t;
-
-/**
- * @brief Mesh address
- */
-typedef union {
-    uint8_t addr[6];    /**< mac address */
-    mip_t mip;          /**< mip address */
-} mesh_addr_t;
-
-/**
- * @brief Channel switch information
- */
-typedef struct {
-    uint8_t channel;    /**< new channel */
-} mesh_event_channel_switch_t;
-
-/**
- * @brief Parent connected information
- */
-typedef struct {
-    system_event_sta_connected_t connected; /**< parent information, same as Wi-Fi event SYSTEM_EVENT_STA_CONNECTED does */
-    uint8_t self_layer;                     /**< layer */
-} mesh_event_connected_t;
-
-/**
- * @brief No parent found information
- */
-typedef struct {
-    int scan_times;    /**< scan times being through */
-} mesh_event_no_parent_found_t;
-
-/**
- * @brief Layer change information
- */
-typedef struct {
-    uint8_t new_layer; /**< new layer */
-} mesh_event_layer_change_t;
-
-/**
- * @brief The reachability of the root to a DS (distribute system)
- */
-typedef enum {
-    MESH_TODS_UNREACHABLE,    /**< the root isn't able to access external IP network */
-    MESH_TODS_REACHABLE,      /**< the root is able to access external IP network */
-} mesh_event_toDS_state_t;
-
-/**
- * @brief vote started information
- */
-typedef struct {
-    int reason;             /**< vote reason, vote could be initiated by children or by the root itself */
-    int attempts;           /**< max vote attempts before stopped */
-    mesh_addr_t rc_addr;    /**< root address specified by users via API esp_mesh_waive_root() */
-} mesh_event_vote_started_t;
-
-/**
- * @brief find a mesh network that this device can join
- */
-typedef struct {
-    uint8_t channel;            /**< channel number of the new found network */
-    uint8_t router_bssid[6];    /**< router BSSID */
-} mesh_event_find_network_t;
-
-/**
- * @brief IP settings from LwIP stack
- */
-typedef system_event_sta_got_ip_t mesh_event_root_got_ip_t;
-
-/**
- * @brief Root address
- */
-typedef mesh_addr_t mesh_event_root_address_t;
-
-/**
- * @brief Parent disconnected information
- */
-typedef system_event_sta_disconnected_t mesh_event_disconnected_t;
-
-/**
- * @brief Child connected information
- */
-typedef system_event_ap_staconnected_t mesh_event_child_connected_t;
-
-/**
- * @brief Child disconnected information
- */
-typedef system_event_ap_stadisconnected_t mesh_event_child_disconnected_t;
-
-/**
- * @brief Root switch request information
- */
-typedef struct {
-    int reason;             /**< root switch reason, generally root switch is initialized by users via API esp_mesh_waive_root() */
-    mesh_addr_t rc_addr;    /**< the address of root switch requester */
-} mesh_event_root_switch_req_t;
-
-/**
- * @brief Other powerful root address
- */
-typedef struct {
-    int8_t rssi;           /**< rssi with router */
-    uint16_t capacity;     /**< the number of devices in current network */
-    uint8_t addr[6];       /**< other powerful root address */
-} mesh_event_root_conflict_t;
-
-/**
- * @brief Routing table change
- */
-typedef struct {
-    uint16_t rt_size_new;      /**< the new value */
-    uint16_t rt_size_change;   /**< the changed value */
-} mesh_event_routing_table_change_t;
-
-/**
- * @brief Root fixed
- */
-typedef struct {
-    bool is_fixed;     /**< status */
-} mesh_event_root_fixed_t;
-
-/**
- * @brief Scan done　event information
- */
-typedef struct {
-    uint8_t  number;     /**< the number of APs scanned */
-} mesh_event_scan_done_t;
-
-/**
- * @brief Network state information
- */
-typedef struct {
-    bool is_rootless;     /**< whether current mesh network has a root */
-} mesh_event_network_state_t;
-
-/**
- * @brief New router information
- */
-typedef system_event_sta_connected_t mesh_event_router_switch_t;
-
-/**
- * @brief Mesh event information
- */
-typedef union {
-    mesh_event_channel_switch_t channel_switch;            /**< channel switch */
-    mesh_event_child_connected_t child_connected;          /**< child connected */
-    mesh_event_child_disconnected_t child_disconnected;    /**< child disconnected */
-    mesh_event_routing_table_change_t routing_table;       /**< routing table change */
-    mesh_event_connected_t connected;                      /**< parent connected */
-    mesh_event_disconnected_t disconnected;                /**< parent disconnected */
-    mesh_event_no_parent_found_t no_parent;                /**< no parent found */
-    mesh_event_layer_change_t layer_change;                /**< layer change */
-    mesh_event_toDS_state_t toDS_state;                    /**< toDS state, devices shall check this state firstly before trying to send packets to
-                                                                external IP network. This state indicates right now whether the root is capable of sending
-                                                                packets out. If not, devices had better to wait until this state changes to be
-                                                                MESH_TODS_REACHABLE. */
-    mesh_event_vote_started_t vote_started;                /**< vote started */
-    mesh_event_root_got_ip_t got_ip;                       /**< root obtains IP address */
-    mesh_event_root_address_t root_addr;                   /**< root address */
-    mesh_event_root_switch_req_t switch_req;               /**< root switch request */
-    mesh_event_root_conflict_t root_conflict;              /**< other powerful root */
-    mesh_event_root_fixed_t root_fixed;                    /**< fixed root */
-    mesh_event_scan_done_t scan_done;                      /**< scan done */
-    mesh_event_network_state_t network_state;              /**< network state, such as whether current mesh network has a root. */
-    mesh_event_find_network_t find_network;                /**< network found that can join */
-    mesh_event_router_switch_t router_switch;              /**< new router information */
-} mesh_event_info_t;
-
-/**
- * @brief Mesh event
- */
-typedef struct {
-    mesh_event_id_t id;        /**< mesh event id */
-    mesh_event_info_t info;    /**< mesh event info */
-} mesh_event_t;
-
-/**
- * @brief  Mesh event callback handler prototype definition
- *
- * @param  event  mesh_event_t
- */
-typedef void (*mesh_event_cb_t)(mesh_event_t event);
-
-/**
- * @brief Mesh option
- */
-typedef struct {
-    uint8_t type;    /**< option type */
-    uint16_t len;    /**< option length */
-    uint8_t *val;    /**< option value */
-} __attribute__((packed)) mesh_opt_t;
-
-/**
- * @brief Mesh data for esp_mesh_send() and esp_mesh_recv()
- */
-typedef struct {
-    uint8_t *data;         /**< data */
-    uint16_t size;         /**< data size */
-    mesh_proto_t proto;    /**< data protocol */
-    mesh_tos_t tos;        /**< data type of service */
-} mesh_data_t;
-
-/**
- * @brief Router configuration
- */
-typedef struct {
-    uint8_t ssid[32];             /**< SSID */
-    uint8_t ssid_len;             /**< length of SSID */
-    uint8_t bssid[6];             /**< BSSID, if this value is specified, users should also specify "allow_router_switch". */
-    uint8_t password[64];         /**< password */
-    bool allow_router_switch;     /**< if the BSSID is specified and this value is also set, when the router of this specified BSSID
-                                       fails to be found after "fail" (mesh_attempts_t) times, the whole network is allowed to switch
-                                       to another router with the same SSID. The new router might also be on a different channel.
-                                       The default value is false.
-                                       There is a risk that if the password is different between the new switched router and the previous
-                                       one, the mesh network could be established but the root will never connect to the new switched router. */
-} mesh_router_t;
-
-/**
- * @brief Mesh softAP configuration
- */
-typedef struct {
-    uint8_t password[64];      /**< mesh softAP password */
-    uint8_t max_connection;    /**< max number of stations allowed to connect in, max 10 */
-} mesh_ap_cfg_t;
-
-/**
- * @brief Mesh initialization configuration
- */
-typedef struct {
-    uint8_t channel;                            /**< channel, the mesh network on */
-    bool allow_channel_switch;                  /**< if this value is set, when "fail" (mesh_attempts_t) times is reached, device will change to
-                                                     a full channel scan for a network that could join. The default value is false. */
-    mesh_event_cb_t event_cb;                   /**< mesh event callback */
-    mesh_addr_t mesh_id;                        /**< mesh network identification */
-    mesh_router_t router;                       /**< router configuration */
-    mesh_ap_cfg_t mesh_ap;                      /**< mesh softAP configuration */
-    const mesh_crypto_funcs_t *crypto_funcs;    /**< crypto functions */
-} mesh_cfg_t;
-
-/**
- * @brief Vote address configuration
- */
-typedef union {
-    int attempts;           /**< max vote attempts before a new root is elected automatically by mesh network. (min:15, 15 by default) */
-    mesh_addr_t rc_addr;    /**< a new root address specified by users for API esp_mesh_waive_root() */
-} mesh_rc_config_t;
-
-/**
- * @brief Vote
- */
-typedef struct {
-    float percentage;           /**< vote percentage threshold for approval of being a root */
-    bool is_rc_specified;       /**< if true, rc_addr shall be specified (Unimplemented).
-                                     if false, attempts value shall be specified to make network start root election. */
-    mesh_rc_config_t config;    /**< vote address configuration */
-} mesh_vote_t;
-
-/**
- * @brief The number of packets pending in the queue waiting to be sent by the mesh stack
- */
-typedef struct {
-    int to_parent;        /**< to parent queue */
-    int to_parent_p2p;    /**< to parent (P2P) queue */
-    int to_child;         /**< to child queue */
-    int to_child_p2p;     /**< to child (P2P) queue */
-    int mgmt;             /**< management queue */
-    int broadcast;        /**< broadcast and multicast queue */
-} mesh_tx_pending_t;
-
-/**
- * @brief The number of packets available in the queue waiting to be received by applications
- */
-typedef struct {
-    int toDS;      /**< to external DS */
-    int toSelf;    /**< to self */
-} mesh_rx_pending_t;
-
-/*******************************************************
- *                Variable Declaration
- *******************************************************/
-/* mesh IE crypto callback function */
-extern const mesh_crypto_funcs_t g_wifi_default_mesh_crypto_funcs;
-
-/* mesh event callback handler */
-extern mesh_event_cb_t g_mesh_event_cb;
-
-#define MESH_INIT_CONFIG_DEFAULT() { \
-    .crypto_funcs = &g_wifi_default_mesh_crypto_funcs, \
-}
-
-/*******************************************************
- *                Function Definitions
- *******************************************************/
-/**
- * @brief      Mesh initialization
- *             - Check whether Wi-Fi is started.
- *             - Initialize mesh global variables with default values.
- *
- * @attention  This API shall be called after Wi-Fi is started.
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_init(void);
-
-/**
- * @brief      Mesh de-initialization
- *
- *             - Release resources and stop the mesh
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_deinit(void);
-
-/**
- * @brief      Start mesh
- *             - Initialize mesh IE.
- *             - Start mesh network management service.
- *             - Create TX and RX queues according to the configuration.
- *             - Register mesh packets receive callback.
- *
- * @attention　　This API shall be called after mesh initialization and configuration.
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- *    - ESP_ERR_MESH_NOT_INIT
- *    - ESP_ERR_MESH_NOT_CONFIG
- *    - ESP_ERR_MESH_NO_MEMORY
- */
-esp_err_t esp_mesh_start(void);
-
-/**
- * @brief      Stop mesh
- *             - Deinitialize mesh IE.
- *             - Disconnect with current parent.
- *             - Disassociate all currently associated children.
- *             - Stop mesh network management service.
- *             - Unregister mesh packets receive callback.
- *             - Delete TX and RX queues.
- *             - Release resources.
- *             - Restore Wi-Fi softAP to default settings if Wi-Fi dual mode is enabled.
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_stop(void);
-
-/**
- * @brief      Send a packet over the mesh network
- *             - Send a packet to any device in the mesh network.
- *             - Send a packet to external IP network.
- *
- * @attention  This API is not reentrant.
- *
- * @param[in]  to  the address of the final destination of the packet
- *             - If the packet is to the root, set this parameter to NULL.
- *             - If the packet is to an external IP network, set this parameter to the IPv4:PORT combination.
- *               This packet will be delivered to the root firstly, then the root will forward this packet to the final IP server address.
- * @param[in]  data  pointer to a sending mesh packet
- *             - Field size should not exceed MESH_MPS. Note that the size of one mesh packet should not exceed MESH_MTU.
- *             - Field proto should be set to data protocol in use (default is MESH_PROTO_BIN for binary).
- *             - Field tos should be set to transmission tos (type of service) in use (default is MESH_TOS_P2P for point-to-point reliable).
- * @param[in]  flag  bitmap for data sent
- *             -  Speed up the route search
- *               - If the packet is to the root and "to" parameter is NULL, set this parameter to 0.
- *               - If the packet is to an internal device, MESH_DATA_P2P should be set.
- *               - If the packet is to the root ("to" parameter isn't NULL) or to external IP network, MESH_DATA_TODS should be set.
- *               - If the packet is from the root to an internal device, MESH_DATA_FROMDS should be set.
- *             - Specify whether this API is block or non-block, block by default
- *               - If needs non-block, MESH_DATA_NONBLOCK should be set.
- *             - In the situation of the root change, MESH_DATA_DROP identifies this packet can be dropped by the new root
- *               for upstream data to external IP network, we try our best to avoid data loss caused by the root change, but
- *               there is a risk that the new root is running out of memory because most of memory is occupied by the pending data which
- *               isn't read out in time by esp_mesh_recv_toDS().
- *
- *               Generally, we suggest esp_mesh_recv_toDS() is called after a connection with IP network is created. Thus data outgoing
- *               to external IP network via socket is just from reading esp_mesh_recv_toDS() which avoids unnecessary memory copy.
- *
- * @param[in]  opt  options
- *             - In case of sending a packet to a certain group, MESH_OPT_SEND_GROUP is a good choice.
- *               In this option, the value field should be set to the target receiver addresses in this group.
- *             - Root sends a packet to an internal device, this packet is from external IP network in case the receiver device responds
- *             this packet, MESH_OPT_RECV_DS_ADDR is required to attach the target DS address.
- * @param[in]  opt_count  option count
- *             - Currently, this API only takes one option, so opt_count is only supported to be 1.
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- *    - ESP_ERR_MESH_ARGUMENT
- *    - ESP_ERR_MESH_NOT_START
- *    - ESP_ERR_MESH_DISCONNECTED
- *    - ESP_ERR_MESH_OPT_UNKNOWN
- *    - ESP_ERR_MESH_EXCEED_MTU
- *    - ESP_ERR_MESH_NO_MEMORY
- *    - ESP_ERR_MESH_TIMEOUT
- *    - ESP_ERR_MESH_QUEUE_FULL
- *    - ESP_ERR_MESH_NO_ROUTE_FOUND
- *    - ESP_ERR_MESH_DISCARD
- */
-esp_err_t esp_mesh_send(const mesh_addr_t *to, const mesh_data_t *data,
-                        int flag, const mesh_opt_t opt[],  int opt_count);
-
-/**
- * @brief      Receive a packet targeted to self over the mesh network
- *
- * @attention  Mesh RX queue should be checked regularly to avoid running out of memory.
- *             - Use esp_mesh_get_rx_pending() to check the number of packets available in the queue waiting
- *             to be received by applications.
- *
- * @param[out] from  the address of the original source of the packet
- * @param[out] data  pointer to the received mesh packet
- *             - Field proto is the data protocol in use. Should follow it to parse the received data.
- *             - Field tos is the transmission tos (type of service) in use.
- * @param[in]  timeout_ms  wait time if a packet isn't immediately available (0:no wait, portMAX_DELAY:wait forever)
- * @param[out] flag  bitmap for data received
- *             - MESH_DATA_FROMDS represents data from external IP network
- *             - MESH_DATA_TODS represents data directed upward within the mesh network
- *
- *             flag could be MESH_DATA_FROMDS or MESH_DATA_TODS.
- * @param[out] opt  options desired to receive
- *             - MESH_OPT_RECV_DS_ADDR attaches the DS address
- * @param[in]  opt_count  option count desired to receive
- *             - Currently, this API only takes one option, so opt_count is only supported to be 1.
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- *    - ESP_ERR_MESH_NOT_START
- *    - ESP_ERR_MESH_TIMEOUT
- *    - ESP_ERR_MESH_DISCARD
- */
-esp_err_t esp_mesh_recv(mesh_addr_t *from, mesh_data_t *data, int timeout_ms,
-                        int *flag, mesh_opt_t opt[], int opt_count);
-
-/**
- * @brief      Receive a packet targeted to external IP network
- *             - Root uses this API to receive packets destined to external IP network
- *             - Root forwards the received packets to the final destination via socket.
- *             - If no socket connection is ready to send out the received packets and this esp_mesh_recv_toDS()
- *             hasn't been called by applications, packets from the whole mesh network will be pending in toDS queue.
- *
- *             Use esp_mesh_get_rx_pending() to check the number of packets available in the queue waiting
- *             to be received by applications in case of running out of memory in the root.
- *
- *             Using esp_mesh_set_xon_qsize() users may configure the RX queue size, default:32. If this size is too large,
- *             and esp_mesh_recv_toDS() isn't called in time, there is a risk that a great deal of memory is occupied
- *             by the pending packets. If this size is too small, it will impact the efficiency on upstream. How to
- *             decide this value depends on the specific application scenarios.
- *
- * @attention  This API is only called by the root.
- *
- * @param[out] from  the address of the original source of the packet
- * @param[out] to  the address contains remote IP address and port (IPv4:PORT)
- * @param[out] data  pointer to the received packet
- *             - Contain the protocol and applications should follow it to parse the data.
- * @param[in]  timeout_ms  wait time if a packet isn't immediately available (0:no wait, portMAX_DELAY:wait forever)
- * @param[out] flag  bitmap for data received
- *             - MESH_DATA_TODS represents the received data target to external IP network. Root shall forward this data to external IP network via the association with router.
- *
- *             flag could be MESH_DATA_TODS.
- * @param[out] opt  options desired to receive
- * @param[in]  opt_count  option count desired to receive
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- *    - ESP_ERR_MESH_NOT_START
- *    - ESP_ERR_MESH_TIMEOUT
- *    - ESP_ERR_MESH_DISCARD
- *    - ESP_ERR_MESH_RECV_RELEASE
- */
-esp_err_t esp_mesh_recv_toDS(mesh_addr_t *from, mesh_addr_t *to,
-                             mesh_data_t *data, int timeout_ms, int *flag, mesh_opt_t opt[],
-                             int opt_count);
-
-/**
- * @brief      Set mesh stack configuration
- *             - Use MESH_INIT_CONFIG_DEFAULT() to initialize the default values, mesh IE is encrypted by default.
- *             - Mesh network is established on a fixed channel (1-14).
- *             - Mesh event callback is mandatory.
- *             - Mesh ID is an identifier of an MBSS. Nodes with the same mesh ID can communicate with each other.
- *             - Regarding to the router configuration, if the router is hidden, BSSID field is mandatory.
- *
- *             If BSSID field isn't set and there exists more than one router with same SSID, there is a risk that more
- *             roots than one connected with different BSSID will appear. It means more than one mesh network is established
- *             with the same mesh ID.
- *
- *             Root conflict function could eliminate redundant roots connected with the same BSSID, but couldn't handle roots
- *             connected with different BSSID. Because users might have such requirements of setting up routers with same SSID
- *             for the future replacement. But in that case, if the above situations happen, please make sure applications
- *             implement forward functions on the root to guarantee devices in different mesh networks can communicate with each other.
- *             max_connection of mesh softAP is limited by the max number of Wi-Fi softAP supported (max:10).
- *
- * @attention  This API shall be called before mesh is started after mesh is initialized.
- *
- * @param[in]  config  pointer to mesh stack configuration
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- *    - ESP_ERR_MESH_NOT_ALLOWED
- */
-esp_err_t esp_mesh_set_config(const mesh_cfg_t *config);
-
-/**
- * @brief      Get mesh stack configuration
- *
- * @param[out] config  pointer to mesh stack configuration
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_get_config(mesh_cfg_t *config);
-
-/**
- * @brief      Get router configuration
- *
- * @attention  This API is used to dynamically modify the router configuration after mesh is configured.
- *
- * @param[in]  router  pointer to router configuration
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_set_router(const mesh_router_t *router);
-
-/**
- * @brief      Get router configuration
- *
- * @param[out] router  pointer to router configuration
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_get_router(mesh_router_t *router);
-
-/**
- * @brief      Set mesh network ID
- *
- * @attention  This API is used to dynamically modify the mesh network ID.
- *
- * @param[in]  id  pointer to mesh network ID
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT: invalid argument
- */
-esp_err_t esp_mesh_set_id(const mesh_addr_t *id);
-
-/**
- * @brief      Get mesh network ID
- *
- * @param[out] id  pointer to mesh network ID
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_get_id(mesh_addr_t *id);
-
-/**
- * @brief      Designate device type over the mesh network
- *            - MESH_IDLE: designates a device as a self-organized node for a mesh network
- *            - MESH_ROOT: designates the root node for a mesh network
- *            - MESH_LEAF: designates a device as a standalone Wi-Fi station that connects to a parent
- *            - MESH_STA: designates a device as a standalone Wi-Fi station that connects to a router
- *
- * @param[in]  type  device type
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_NOT_ALLOWED
- */
-esp_err_t esp_mesh_set_type(mesh_type_t type);
-
-/**
- * @brief      Get device type over mesh network
- *
- * @attention  This API shall be called after having received the event MESH_EVENT_PARENT_CONNECTED.
- *
- * @return     mesh type
- *
- */
-mesh_type_t esp_mesh_get_type(void);
-
-/**
- * @brief      Set network max layer value (max:25, default:25)
- *             - Network max layer limits the max hop count.
- *
- * @attention  This API shall be called before mesh is started.
- *
- * @param[in]  max_layer  max layer value
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- *    - ESP_ERR_MESH_NOT_ALLOWED
- */
-esp_err_t esp_mesh_set_max_layer(int max_layer);
-
-/**
- * @brief      Get max layer value
- *
- * @return     max layer value
- */
-int esp_mesh_get_max_layer(void);
-
-/**
- * @brief      Set mesh softAP password
- *
- * @attention  This API shall be called before mesh is started.
- *
- * @param[in]  pwd  pointer to the password
- * @param[in]  len  password length
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- *    - ESP_ERR_MESH_NOT_ALLOWED
- */
-esp_err_t esp_mesh_set_ap_password(const uint8_t *pwd, int len);
-
-/**
- * @brief      Set mesh softAP authentication mode
- *
- * @attention  This API shall be called before mesh is started.
- *
- * @param[in]  authmode  authentication mode
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- *    - ESP_ERR_MESH_NOT_ALLOWED
- */
-esp_err_t esp_mesh_set_ap_authmode(wifi_auth_mode_t authmode);
-
-/**
- * @brief      Get mesh softAP authentication mode
- *
- * @return     authentication mode
- */
-wifi_auth_mode_t esp_mesh_get_ap_authmode(void);
-
-/**
- * @brief      Set mesh softAP max connection value
- *
- * @attention  This API shall be called before mesh is started.
- *
- * @param[in]  connections  the number of max connections
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_set_ap_connections(int connections);
-
-/**
- * @brief      Get mesh softAP max connection configuration
- *
- * @return     the number of max connections
- */
-int esp_mesh_get_ap_connections(void);
-
-/**
- * @brief      Get current layer value over the mesh network
- *
- * @attention  This API shall be called after having received the event MESH_EVENT_PARENT_CONNECTED.
- *
- * @return     layer value
- *
- */
-int esp_mesh_get_layer(void);
-
-/**
- * @brief      Get the parent BSSID
- *
- * @attention  This API shall be called after having received the event MESH_EVENT_PARENT_CONNECTED.
- *
- * @param[out] bssid  pointer to parent BSSID
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_get_parent_bssid(mesh_addr_t *bssid);
-
-/**
- * @brief      Return whether the device is the root node of the network
- *
- * @return     true/false
- */
-bool esp_mesh_is_root(void);
-
-/**
- * @brief      Enable/disable self-organized networking
- *             - Self-organized networking has three main functions:
- *             select the root node;
- *             find a preferred parent;
- *             initiate reconnection if a disconnection is detected.
- *             - Self-organized networking is enabled by default.
- *             - If self-organized is disabled, users should set a parent for the device via esp_mesh_set_parent().
- *
- * @attention  This API is used to dynamically modify whether to enable the self organizing.
- *
- * @param[in]  enable  enable or disable self-organized networking
- * @param[in]  select_parent  Only valid when self-organized networking is enabled.
- *             - if select_parent is set to true, the root will give up its mesh root status and search for a new parent
- *             like other non-root devices.
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_set_self_organized(bool enable, bool select_parent);
-
-/**
- * @brief      Return whether enable self-organized networking or not
- *
- * @return     true/false
- */
-bool esp_mesh_get_self_organized(void);
-
-/**
- * @brief      Cause the root device to give up (waive) its mesh root status
- *             - A device is elected root primarily based on RSSI from the external router.
- *             - If external router conditions change, users can call this API to perform a root switch.
- *             - In this API, users could specify a desired root address to replace itself or specify an attempts value
- *             to ask current root to initiate a new round of voting. During the voting, a better root candidate would
- *             be expected to find to replace the current one.
- *             - If no desired root candidate, the vote will try a specified number of attempts (at least 15). If no better
- *             root candidate is found, keep the current one. If a better candidate is found, the new better one will
- *             send a root switch request to the current root, current root will respond with a root switch acknowledgment.
- *             - After that, the new candidate will connect to the router to be a new root, the previous root will disconnect
- *             with the router and choose another parent instead.
- *
- *             Root switch is completed with minimal disruption to the whole mesh network.
- *
- * @attention  This API is only called by the root.
- *
- * @param[in]  vote  vote configuration
- *             - If this parameter is set NULL, the vote will perform the default 15 times.
- *
- *             - Field percentage threshold is 0.9 by default.
- *             - Field is_rc_specified shall be false.
- *             - Field attempts shall be at least 15 times.
- * @param[in]  reason  only accept MESH_VOTE_REASON_ROOT_INITIATED for now
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_QUEUE_FULL
- *    - ESP_ERR_MESH_DISCARD
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_waive_root(const mesh_vote_t *vote, int reason);
-
-/**
- * @brief      Set vote percentage threshold for approval of being a root
- *             - During the networking, only obtaining vote percentage reaches this threshold,
- *             the device could be a root.
- *
- * @attention  This API shall be called before mesh is started.
- *
- * @param[in]  percentage  vote percentage threshold
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_set_vote_percentage(float percentage);
-
-/**
- * @brief      Get vote percentage threshold for approval of being a root
- *
- * @return     percentage threshold
- */
-float esp_mesh_get_vote_percentage(void);
-
-/**
- * @brief      Set mesh softAP associate expired time (default:10 seconds)
- *             - If mesh softAP hasn't received any data from an associated child within this time,
- *             mesh softAP will take this child inactive and disassociate it.
- *             - If mesh softAP is encrypted, this value should be set a greater value, such as 30 seconds.
- *
- * @param[in]  seconds  the expired time
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_set_ap_assoc_expire(int seconds);
-
-/**
- * @brief      Get mesh softAP associate expired time
- *
- * @return     seconds
- */
-int esp_mesh_get_ap_assoc_expire(void);
-
-/**
- * @brief      Get total number of devices in current network (including the root)
- *
- * @attention  The returned value might be incorrect when the network is changing.
- **
- * @return     total number of devices (including the root)
- */
-int esp_mesh_get_total_node_num(void);
-
-/**
- * @brief      Get the number of devices in this device's sub-network (including self)
- *
- * @return     the number of devices over this device's sub-network (including self)
- */
-int esp_mesh_get_routing_table_size(void);
-
-/**
- * @brief      Get routing table of this device's sub-network (including itself)
- *
- * @param[out] mac  pointer to routing table
- * @param[in]  len  routing table size(in bytes)
- * @param[out] size  pointer to the number of devices in routing table (including itself)
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_get_routing_table(mesh_addr_t *mac, int len, int *size);
-
-/**
- * @brief      Post the toDS state to the mesh stack
- *
- * @attention  This API is only for the root.
- *
- * @param[in]  reachable  this state represents whether the root is able to access external IP network
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_post_toDS_state(bool reachable);
-
-/**
- * @brief      Return the number of packets pending in the queue waiting to be sent by the mesh stack
- *
- * @param[out] pending  pointer to the TX pending
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_get_tx_pending(mesh_tx_pending_t *pending);
-
-/**
- * @brief      Return the number of packets available in the queue waiting to be received by applications
- *
- * @param[out] pending  pointer to the RX pending
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_get_rx_pending(mesh_rx_pending_t *pending);
-
-/**
- * @brief      Return the number of packets could be accepted from the specified address
- *
- * @param[in]  addr  self address or an associate children address
- * @param[out] xseqno_in  sequence number of the last received packet from the specified address
- *
- * @return    the number of upQ for a certain address
- */
-int esp_mesh_available_txupQ_num(const mesh_addr_t *addr, uint32_t *xseqno_in);
-
-/**
- * @brief      Set the number of queue
- *
- * @attention  This API shall be called before mesh is started.
- *
- * @param[in]  qsize  default:32 (min:16)
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_set_xon_qsize(int qsize);
-
-/**
- * @brief      Get queue size
- *
- * @return     the number of queue
- */
-int esp_mesh_get_xon_qsize(void);
-
-/**
- * @brief      Set whether allow more than one root existing in one network
- *
- * @param[in]  allowed  allow or not
- *
- * @return
- *    - ESP_OK
- *    - ESP_WIFI_ERR_NOT_INIT
- *    - ESP_WIFI_ERR_NOT_START
- */
-esp_err_t esp_mesh_allow_root_conflicts(bool allowed);
-
-/**
- * @brief      Check whether allow more than one root to exist in one network
- *
- * @return     true/false
- */
-bool esp_mesh_is_root_conflicts_allowed(void);
-
-/**
- * @brief      Set group ID addresses
- *
- * @param[in]  addr  pointer to new group ID addresses
- * @param[in]  num  the number of group ID addresses
- *
- * @return
- *    - ESP_OK
- *    - ESP_MESH_ERR_ARGUMENT
- */
-esp_err_t esp_mesh_set_group_id(const mesh_addr_t *addr, int num);
-
-/**
- * @brief      Delete group ID addresses
- *
- * @param[in]  addr  pointer to deleted group ID address
- * @param[in]  num  the number of group ID addresses
- *
- * @return
- *    - ESP_OK
- *    - ESP_MESH_ERR_ARGUMENT
- */
-esp_err_t esp_mesh_delete_group_id(const mesh_addr_t *addr, int num);
-
-/**
- * @brief      Get the number of group ID addresses
- *
- * @return     the number of group ID addresses
- */
-int esp_mesh_get_group_num(void);
-
-/**
- * @brief      Get group ID addresses
- *
- * @param[out] addr  pointer to group ID addresses
- * @param[in]  num  the number of group ID addresses
- *
- * @return
- *    - ESP_OK
- *    - ESP_MESH_ERR_ARGUMENT
- */
-esp_err_t esp_mesh_get_group_list(mesh_addr_t *addr, int num);
-
-/**
- * @brief      Check whether the specified group address is my group
- *
- * @return     true/false
- */
-bool esp_mesh_is_my_group(const mesh_addr_t *addr);
-
-/**
- * @brief      Set mesh network capacity (max:1000, default:300)
- *
- * @attention  This API shall be called before mesh is started.
- *
- * @param[in]  num  mesh network capacity
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_NOT_ALLOWED
- *    - ESP_MESH_ERR_ARGUMENT
- */
-esp_err_t esp_mesh_set_capacity_num(int num);
-
-/**
- * @brief      Get mesh network capacity
- *
- * @return     mesh network capacity
- */
-int esp_mesh_get_capacity_num(void);
-
-/**
- * @brief      Set mesh IE crypto functions
- *
- * @attention  This API can be called at any time after mesh is initialized.
- *
- * @param[in]  crypto_funcs  crypto functions for mesh IE
- *           - If crypto_funcs is set to NULL, mesh IE is no longer encrypted.
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_set_ie_crypto_funcs(const mesh_crypto_funcs_t *crypto_funcs);
-
-/**
- * @brief      Set mesh IE crypto key
- *
- * @attention  This API can be called at any time after mesh is initialized.
- *
- * @param[in]  key  ASCII crypto key
- * @param[in]  len  length in bytes, range:8~64
- *
- * @return
- *    - ESP_OK
- *    - ESP_MESH_ERR_ARGUMENT
- */
-esp_err_t esp_mesh_set_ie_crypto_key(const char *key, int len);
-
-/**
- * @brief      Get mesh IE crypto key
- *
- * @param[out] key  ASCII crypto key
- * @param[in]  len  length in bytes, range:8~64
- *
- * @return
- *    - ESP_OK
- *    - ESP_MESH_ERR_ARGUMENT
- */
-esp_err_t esp_mesh_get_ie_crypto_key(char *key, int len);
-
-/**
- * @brief      Set delay time before starting root healing
- *
- * @param[in]  delay_ms  delay time in milliseconds
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_set_root_healing_delay(int delay_ms);
-
-/**
- * @brief      Get delay time before network starts root healing
- *
- * @return     delay time in milliseconds
- */
-int esp_mesh_get_root_healing_delay(void);
-
-/**
- * @brief      Set mesh event callback
- *
- * @param[in]  event_cb  mesh event call back
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_set_event_cb(const mesh_event_cb_t event_cb);
-
-/**
- * @brief      Enable network Fixed Root Setting
- *             - Enabling fixed root disables automatic election of the root node via voting.
- *             - All devices in the network shall use the same Fixed Root Setting (enabled or disabled).
- *             - If Fixed Root is enabled, users should make sure a root node is designated for the network.
- *
- * @param[in]  enable  enable or not
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_fix_root(bool enable);
-
-/**
- * @brief      Check whether network Fixed Root Setting is enabled
- *             - Enable/disable network Fixed Root Setting by API esp_mesh_fix_root().
- *             - Network Fixed Root Setting also changes with the "flag" value in parent networking IE.
- *
- * @return     true/false
- */
-bool esp_mesh_is_root_fixed(void);
-
-/**
- * @brief      Set a specified parent for the device
- *
- * @attention  This API can be called at any time after mesh is configured.
- *
- * @param[in]  parent  parent configuration, the SSID and the channel of the parent are mandatory.
- *             - If the BSSID is set, make sure that the SSID and BSSID represent the same parent,
- *             otherwise the device will never find this specified parent.
- * @param[in]  parent_mesh_id  parent mesh ID,
- *             - If this value is not set, the original mesh ID is used.
- * @param[in]  my_type  mesh type
- *             - If the parent set for the device is the same as the router in the network configuration,
- *            then my_type shall set MESH_ROOT and my_layer shall set MESH_ROOT_LAYER.
- * @param[in]  my_layer  mesh layer
- *             - my_layer of the device may change after joining the network.
- *             - If my_type is set MESH_NODE, my_layer shall be greater than MESH_ROOT_LAYER.
- *             - If my_type is set MESH_LEAF, the device becomes a standalone Wi-Fi station and no longer
- *             has the ability to extend the network.
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_ARGUMENT
- *    - ESP_ERR_MESH_NOT_CONFIG
- */
-esp_err_t esp_mesh_set_parent(const wifi_config_t *parent, const mesh_addr_t *parent_mesh_id, mesh_type_t my_type, int my_layer);
-
-/**
- * @brief      Get mesh networking IE length of one AP
- *
- * @param[out] len  mesh networking IE length
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_WIFI_NOT_INIT
- *    - ESP_ERR_WIFI_ARG
- *    - ESP_ERR_WIFI_FAIL
- */
-esp_err_t esp_mesh_scan_get_ap_ie_len(int *len);
-
-/**
- * @brief      Get AP record
- *
- * @attention  Different from esp_wifi_scan_get_ap_records(), this API only gets one of APs scanned each time.
- *             See "manual_networking" example.
- *
- * @param[out] ap_record  pointer to one AP record
- * @param[out] buffer  pointer to the mesh networking IE of this AP
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_WIFI_NOT_INIT
- *    - ESP_ERR_WIFI_ARG
- *    - ESP_ERR_WIFI_FAIL
- */
-esp_err_t esp_mesh_scan_get_ap_record(wifi_ap_record_t *ap_record, void *buffer);
-
-/**
- * @brief      Flush upstream packets pending in to_parent queue and to_parent_p2p queue
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_flush_upstream_packets(void);
-
-/**
- * @brief      Get the number of nodes in the subnet of a specific child
- *
- * @param[in]  child_mac  an associated child address of this device
- * @param[out] nodes_num  pointer to the number of nodes in the subnet of a specific child
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_NOT_START
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_get_subnet_nodes_num(const mesh_addr_t *child_mac, int *nodes_num);
-
-/**
- * @brief      Get nodes in the subnet of a specific child
- *
- * @param[in]  child_mac  an associated child address of this device
- * @param[out] nodes  pointer to nodes in the subnet of a specific child
- * @param[in]  nodes_num  the number of nodes in the subnet of a specific child
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_NOT_START
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_get_subnet_nodes_list(const mesh_addr_t *child_mac, mesh_addr_t *nodes, int nodes_num);
-
-/**
- * @brief      Disconnect from current parent
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_disconnect(void);
-
-/**
- * @brief      Connect to current parent
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_connect(void);
-
-/**
- * @brief      Flush scan result
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_flush_scan_result(void);
-
-/**
- * @brief      Cause the root device to add Channel Switch Announcement Element (CSA IE) to beacon
- *             - Set the new channel
- *             - Set how many beacons with CSA IE will be sent before changing a new channel
- *             - Enable the channel switch function
- *
- * @attention  This API is only called by the root.
- *
- * @param[in]  new_bssid  the new router BSSID if the router changes
- * @param[in]  csa_newchan  the new channel number to which the whole network is moving
- * @param[in]  csa_count  channel switch period(beacon count), unit is based on beacon interval of its softAP, the default value is 15.
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_switch_channel(const uint8_t *new_bssid, int csa_newchan, int csa_count);
-
-/**
- * @brief      Get the router BSSID
- *
- * @param[out] router_bssid  pointer to the router BSSID
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_WIFI_NOT_INIT
- *    - ESP_ERR_WIFI_ARG
- */
-esp_err_t esp_mesh_get_router_bssid(uint8_t *router_bssid);
-
-/**
- * @brief      Get the TSF time
- *
- * @return     the TSF time
- */
-int64_t esp_mesh_get_tsf_time(void);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __ESP_MESH_H__ */
diff --git a/tools/sdk/include/esp32/esp_mesh_internal.h b/tools/sdk/include/esp32/esp_mesh_internal.h
deleted file mode 100644
index 020354ab136..00000000000
--- a/tools/sdk/include/esp32/esp_mesh_internal.h
+++ /dev/null
@@ -1,279 +0,0 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_MESH_INTERNAL_H__
-#define __ESP_MESH_INTERNAL_H__
-
-#include "esp_err.h"
-#include "esp_wifi.h"
-#include "esp_wifi_types.h"
-#include "esp_wifi_internal.h"
-#include "esp_wifi_crypto_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*******************************************************
- *                Constants
- *******************************************************/
-
-/*******************************************************
- *                Structures
- *******************************************************/
-typedef struct {
-    int scan;          /**< minimum scan times before being a root, default:10 */
-    int vote;          /**< max vote times in self-healing, default:1000 */
-    int fail;          /**< parent selection fail times, if the scan times reach this value,
-                            device will disconnect with associated children and join self-healing. default:60 */
-    int monitor_ie;    /**< acceptable times of parent networking IE change before update its own networking IE. default:3 */
-} mesh_attempts_t;
-
-typedef struct {
-    int duration_ms;   /* parent weak RSSI monitor duration, if the RSSI continues to be weak during this duration_ms,
-                          device will search for a new parent. */
-    int cnx_rssi;      /* RSSI threshold for keeping a good connection with parent.
-                          If set a value greater than -120 dBm, a timer will be armed to monitor parent RSSI at a period time of duration_ms. */
-    int select_rssi;   /* RSSI threshold for parent selection. It should be a value greater than switch_rssi. */
-    int switch_rssi;   /* Disassociate with current parent and switch to a new parent when the RSSI is greater than this set threshold. */
-    int backoff_rssi;  /* RSSI threshold for connecting to the root */
-} mesh_switch_parent_t;
-
-typedef struct {
-    int high;
-    int medium;
-    int low;
-} mesh_rssi_threshold_t;
-
-/**
- * @brief Mesh networking IE
- */
-typedef struct {
-    /**< mesh networking IE head */
-    uint8_t eid;             /**< element ID */
-    uint8_t len;             /**< element length */
-    uint8_t oui[3];          /**< organization identifier */
-    /**< mesh networking IE content */
-    uint8_t type;            /** ESP defined IE type */
-    uint8_t encrypted : 1;   /**< whether mesh networking IE is encrypted */
-    uint8_t version : 7;     /**< mesh networking IE version */
-    /**< content */
-    uint8_t mesh_type;       /**< mesh device type */
-    uint8_t mesh_id[6];      /**< mesh ID */
-    uint8_t layer_cap;       /**< max layer */
-    uint8_t layer;           /**< current layer */
-    uint8_t assoc_cap;       /**< max connections of mesh AP */
-    uint8_t assoc;           /**< current connections */
-    uint8_t leaf_cap;        /**< leaf capacity */
-    uint8_t leaf_assoc;      /**< the number of current connected leaf */
-    uint16_t root_cap;       /**< root capacity */
-    uint16_t self_cap;       /**< self capacity */
-    uint16_t layer2_cap;     /**< layer2 capacity */
-    uint16_t scan_ap_num;    /**< the number of scanning APs */
-    int8_t rssi;             /**< RSSI of the parent */
-    int8_t router_rssi;      /**< RSSI of the router */
-    uint8_t flag;            /**< flag of networking */
-    uint8_t rc_addr[6];      /**< root address */
-    int8_t rc_rssi;          /**< root RSSI */
-    uint8_t vote_addr[6];    /**< voter address */
-    int8_t vote_rssi;        /**< vote RSSI of the router */
-    uint8_t vote_ttl;        /**< vote ttl */
-    uint16_t votes;          /**< votes */
-    uint16_t my_votes;       /**< my votes */
-    uint8_t reason;          /**< reason */
-    uint8_t child[6];        /**< child address */
-    uint8_t toDS;            /**< toDS state */
-} __attribute__((packed)) mesh_assoc_t;
-
-/*******************************************************
- *                Function Definitions
- *******************************************************/
-/**
- * @brief      Set mesh softAP beacon interval
- *
- * @param[in]  interval  beacon interval (msecs) (100 msecs ~ 60000 msecs)
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- *    - ESP_ERR_WIFI_ARG
- */
-esp_err_t esp_mesh_set_beacon_interval(int interval_ms);
-
-/**
- * @brief      Get mesh softAP beacon interval
- *
- * @param[out] interval  beacon interval (msecs)
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_get_beacon_interval(int *interval_ms);
-
-/**
- * @brief     Set attempts for mesh self-organized networking
- *
- * @param[in] attempts
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_set_attempts(mesh_attempts_t *attempts);
-
-/**
- * @brief      Get attempts for mesh self-organized networking
- *
- * @param[out] attempts
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_get_attempts(mesh_attempts_t *attempts);
-
-/**
- * @brief      Set parameters for parent switch
- *
- * @param[in]  paras  parameters for parent switch
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_set_switch_parent_paras(mesh_switch_parent_t *paras);
-
-/**
- * @brief      Get parameters for parent switch
- *
- * @param[out] paras  parameters for parent switch
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_get_switch_parent_paras(mesh_switch_parent_t *paras);
-
-/**
- * @brief      Set RSSI threshold
- *             - The default high RSSI threshold value is -78 dBm.
- *             - The default medium RSSI threshold value is -82 dBm.
- *             - The default low RSSI threshold value is -85 dBm.
- *
- * @param[in]  threshold  RSSI threshold
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_set_rssi_threshold(const mesh_rssi_threshold_t *threshold);
-
-/**
- * @brief      Get RSSI threshold
- *
- * @param[out] threshold  RSSI threshold
- *
- * @return
- *    - ESP_OK
- *    - ESP_ERR_MESH_ARGUMENT
- */
-esp_err_t esp_mesh_get_rssi_threshold(mesh_rssi_threshold_t *threshold);
-
-/**
- * @brief      Enable the minimum rate to 6 Mbps
- *
- * @attention  This API shall be called before Wi-Fi is started.
- *
- * @param[in]  is_6m  enable or not
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_set_6m_rate(bool is_6m);
-
-/**
- * @brief      Print the number of txQ waiting
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_print_txQ_waiting(void);
-
-/**
- * @brief      Print the number of rxQ waiting
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- */
-esp_err_t esp_mesh_print_rxQ_waiting(void);
-
-/**
- * @brief      Set passive scan time
- *
- * @param[in]  interval_ms  passive scan time (msecs)
- *
- * @return
- *    - ESP_OK
- *    - ESP_FAIL
- *    - ESP_ERR_ARGUMENT
- */
-esp_err_t esp_mesh_set_passive_scan_time(int time_ms);
-
-/**
- * @brief      Get passive scan time
- *
- * @return     interval_ms  passive scan time (msecs)
- */
-int esp_mesh_get_passive_scan_time(void);
-
-/**
- * @brief      Set announce interval
- *             - The default short interval is 500 milliseconds.
- *             - The default long interval is 3000 milliseconds.
- *
- * @param[in]  short_ms  shall be greater than the default value
- * @param[in]  long_ms  shall be greater than the default value
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_set_announce_interval(int short_ms, int long_ms);
-
-/**
- * @brief      Get announce interval
- *
- * @param[out] short_ms  short interval
- * @param[out] long_ms  long interval
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_get_announce_interval(int *short_ms, int *long_ms);
-
-/**
- * @brief      Enable mesh print scan result
- *
- * @param[in]  enable  enable or not
- *
- * @return
- *    - ESP_OK
- */
-esp_err_t esp_mesh_print_scan_result(bool enable);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __ESP_MESH_INTERNAL_H__ */
diff --git a/tools/sdk/include/esp32/esp_now.h b/tools/sdk/include/esp32/esp_now.h
deleted file mode 100644
index 981c9001e49..00000000000
--- a/tools/sdk/include/esp32/esp_now.h
+++ /dev/null
@@ -1,317 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_NOW_H__
-#define __ESP_NOW_H__
-
-#include <stdbool.h>
-#include "esp_err.h"
-#include "esp_wifi_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup WiFi_APIs WiFi Related APIs
-  * @brief WiFi APIs
-  */
-
-/** @addtogroup WiFi_APIs
-  * @{
-  */
-
-/** \defgroup ESPNOW_APIs  ESPNOW APIs
-  * @brief ESP32 ESPNOW APIs
-  *
-  */
-
-/** @addtogroup ESPNOW_APIs
-  * @{
-  */
-
-#define ESP_ERR_ESPNOW_BASE         (ESP_ERR_WIFI_BASE + 100) /*!< ESPNOW error number base. */
-#define ESP_ERR_ESPNOW_NOT_INIT     (ESP_ERR_ESPNOW_BASE + 1) /*!< ESPNOW is not initialized. */
-#define ESP_ERR_ESPNOW_ARG          (ESP_ERR_ESPNOW_BASE + 2) /*!< Invalid argument */
-#define ESP_ERR_ESPNOW_NO_MEM       (ESP_ERR_ESPNOW_BASE + 3) /*!< Out of memory */
-#define ESP_ERR_ESPNOW_FULL         (ESP_ERR_ESPNOW_BASE + 4) /*!< ESPNOW peer list is full */
-#define ESP_ERR_ESPNOW_NOT_FOUND    (ESP_ERR_ESPNOW_BASE + 5) /*!< ESPNOW peer is not found */
-#define ESP_ERR_ESPNOW_INTERNAL     (ESP_ERR_ESPNOW_BASE + 6) /*!< Internal error */
-#define ESP_ERR_ESPNOW_EXIST        (ESP_ERR_ESPNOW_BASE + 7) /*!< ESPNOW peer has existed */
-#define ESP_ERR_ESPNOW_IF           (ESP_ERR_ESPNOW_BASE + 8) /*!< Interface error */
-
-#define ESP_NOW_ETH_ALEN             6         /*!< Length of ESPNOW peer MAC address */
-#define ESP_NOW_KEY_LEN              16        /*!< Length of ESPNOW peer local master key */
-
-#define ESP_NOW_MAX_TOTAL_PEER_NUM   20        /*!< Maximum number of ESPNOW total peers */
-#define ESP_NOW_MAX_ENCRYPT_PEER_NUM 6         /*!< Maximum number of ESPNOW encrypted peers */
-
-#define ESP_NOW_MAX_DATA_LEN         250       /*!< Maximum length of ESPNOW data which is sent very time */
-
-/**
- * @brief Status of sending ESPNOW data .
- */
-typedef enum {
-    ESP_NOW_SEND_SUCCESS = 0,       /**< Send ESPNOW data successfully */
-    ESP_NOW_SEND_FAIL,              /**< Send ESPNOW data fail */
-} esp_now_send_status_t;
-
-/**
- * @brief ESPNOW peer information parameters.
- */
-typedef struct esp_now_peer_info {
-    uint8_t peer_addr[ESP_NOW_ETH_ALEN];    /**< ESPNOW peer MAC address that is also the MAC address of station or softap */
-    uint8_t lmk[ESP_NOW_KEY_LEN];           /**< ESPNOW peer local master key that is used to encrypt data */
-    uint8_t channel;                        /**< Wi-Fi channel that peer uses to send/receive ESPNOW data. If the value is 0,
-                                                 use the current channel which station or softap is on. Otherwise, it must be
-                                                 set as the channel that station or softap is on. */
-    wifi_interface_t ifidx;                 /**< Wi-Fi interface that peer uses to send/receive ESPNOW data */
-    bool encrypt;                           /**< ESPNOW data that this peer sends/receives is encrypted or not */
-    void *priv;                             /**< ESPNOW peer private data */
-} esp_now_peer_info_t;
-
-/**
- * @brief Number of ESPNOW peers which exist currently.
- */
-typedef struct esp_now_peer_num {
-    int total_num;                           /**< Total number of ESPNOW peers, maximum value is ESP_NOW_MAX_TOTAL_PEER_NUM */
-    int encrypt_num;                         /**< Number of encrypted ESPNOW peers, maximum value is ESP_NOW_MAX_ENCRYPT_PEER_NUM */
-} esp_now_peer_num_t;
-
-/**
-  * @brief     Callback function of receiving ESPNOW data
-  * @param     mac_addr peer MAC address
-  * @param     data received data
-  * @param     data_len length of received data
-  */
-typedef void (*esp_now_recv_cb_t)(const uint8_t *mac_addr, const uint8_t *data, int data_len);
-
-/**
-  * @brief     Callback function of sending ESPNOW data
-  * @param     mac_addr peer MAC address
-  * @param     status status of sending ESPNOW data (succeed or fail)
-  */
-typedef void (*esp_now_send_cb_t)(const uint8_t *mac_addr, esp_now_send_status_t status);
-
-/**
-  * @brief     Initialize ESPNOW function
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_INTERNAL : Internal error
-  */
-esp_err_t esp_now_init(void);
-
-/**
-  * @brief     De-initialize ESPNOW function
-  *
-  * @return
-  *          - ESP_OK : succeed
-  */
-esp_err_t esp_now_deinit(void);
-
-/**
-  * @brief     Get the version of ESPNOW
-  *
-  * @param     version  ESPNOW version
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_ARG : invalid argument
-  */
-esp_err_t esp_now_get_version(uint32_t *version);
-
-/**
-  * @brief     Register callback function of receiving ESPNOW data
-  *
-  * @param     cb  callback function of receiving ESPNOW data
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_INTERNAL : internal error
-  */
-esp_err_t esp_now_register_recv_cb(esp_now_recv_cb_t cb);
-
-/**
-  * @brief     Unregister callback function of receiving ESPNOW data
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  */
-esp_err_t esp_now_unregister_recv_cb(void);
-
-/**
-  * @brief     Register callback function of sending ESPNOW data
-  *
-  * @param     cb  callback function of sending ESPNOW data
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_INTERNAL : internal error
-  */
-esp_err_t esp_now_register_send_cb(esp_now_send_cb_t cb);
-
-/**
-  * @brief     Unregister callback function of sending ESPNOW data
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  */
-esp_err_t esp_now_unregister_send_cb(void);
-
-/**
-  * @brief     Send ESPNOW data
-  *
-  * @attention 1. If peer_addr is not NULL, send data to the peer whose MAC address matches peer_addr
-  * @attention 2. If peer_addr is NULL, send data to all of the peers that are added to the peer list
-  * @attention 3. The maximum length of data must be less than ESP_NOW_MAX_DATA_LEN
-  * @attention 4. The buffer pointed to by data argument does not need to be valid after esp_now_send returns
-  *
-  * @param     peer_addr  peer MAC address
-  * @param     data  data to send
-  * @param     len  length of data
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_ARG : invalid argument
-  *          - ESP_ERR_ESPNOW_INTERNAL : internal error
-  *          - ESP_ERR_ESPNOW_NO_MEM : out of memory
-  *          - ESP_ERR_ESPNOW_NOT_FOUND : peer is not found
-  *          - ESP_ERR_ESPNOW_IF : current WiFi interface doesn't match that of peer
-  */
-esp_err_t esp_now_send(const uint8_t *peer_addr, const uint8_t *data, size_t len);
-
-/**
-  * @brief     Add a peer to peer list
-  *
-  * @param     peer  peer information
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_ARG : invalid argument
-  *          - ESP_ERR_ESPNOW_FULL : peer list is full
-  *          - ESP_ERR_ESPNOW_NO_MEM : out of memory
-  *          - ESP_ERR_ESPNOW_EXIST : peer has existed
-  */
-esp_err_t esp_now_add_peer(const esp_now_peer_info_t *peer);
-
-/**
-  * @brief     Delete a peer from peer list
-  *
-  * @param     peer_addr  peer MAC address
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_ARG : invalid argument
-  *          - ESP_ERR_ESPNOW_NOT_FOUND : peer is not found
-  */
-esp_err_t esp_now_del_peer(const uint8_t *peer_addr);
-
-/**
-  * @brief     Modify a peer
-  *
-  * @param     peer  peer information
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_ARG : invalid argument
-  *          - ESP_ERR_ESPNOW_FULL : peer list is full
-  */
-esp_err_t esp_now_mod_peer(const esp_now_peer_info_t *peer);
-
-/**
-  * @brief     Get a peer whose MAC address matches peer_addr from peer list
-  *
-  * @param     peer_addr  peer MAC address
-  * @param     peer  peer information
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_ARG : invalid argument
-  *          - ESP_ERR_ESPNOW_NOT_FOUND : peer is not found
-  */
-esp_err_t esp_now_get_peer(const uint8_t *peer_addr, esp_now_peer_info_t *peer);
-
-/**
-  * @brief     Fetch a peer from peer list
-  *
-  * @param     from_head  fetch from head of list or not
-  * @param     peer  peer information
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_ARG : invalid argument
-  *          - ESP_ERR_ESPNOW_NOT_FOUND : peer is not found
-  */
-esp_err_t esp_now_fetch_peer(bool from_head, esp_now_peer_info_t *peer);
-
-/**
-  * @brief     Peer exists or not
-  *
-  * @param     peer_addr  peer MAC address
-  *
-  * @return
-  *          - true : peer exists
-  *          - false : peer not exists
-  */
-bool esp_now_is_peer_exist(const uint8_t *peer_addr);
-
-/**
-  * @brief     Get the number of peers
-  *
-  * @param     num  number of peers
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_ARG : invalid argument
-  */
-esp_err_t esp_now_get_peer_num(esp_now_peer_num_t *num);
-
-/**
-  * @brief     Set the primary master key
-  *
-  * @param     pmk  primary master key
-  *
-  * @attention 1. primary master key is used to encrypt local master key
-  *
-  * @return
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_ESPNOW_NOT_INIT : ESPNOW is not initialized
-  *          - ESP_ERR_ESPNOW_ARG : invalid argument
-  */
-esp_err_t esp_now_set_pmk(const uint8_t *pmk);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_NOW_H__ */
diff --git a/tools/sdk/include/esp32/esp_panic.h b/tools/sdk/include/esp32/esp_panic.h
deleted file mode 100644
index 8db2836ee37..00000000000
--- a/tools/sdk/include/esp32/esp_panic.h
+++ /dev/null
@@ -1,102 +0,0 @@
-#ifndef PANIC_H
-#define PANIC_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#define PANIC_RSN_NONE 0
-#define PANIC_RSN_DEBUGEXCEPTION 1
-#define PANIC_RSN_DOUBLEEXCEPTION 2
-#define PANIC_RSN_KERNELEXCEPTION 3
-#define PANIC_RSN_COPROCEXCEPTION 4
-#define PANIC_RSN_INTWDT_CPU0 5
-#define PANIC_RSN_INTWDT_CPU1 6
-#define PANIC_RSN_CACHEERR 7
-#define PANIC_RSN_MAX 7
-
-
-#ifndef __ASSEMBLER__
-
-#include "esp_err.h"
-#include "soc/soc.h"
-
-
-/**
- * @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function 
- *        address. Do nothing otherwise.
- * @param data  Pointer to the target breakpoint position
- */
-
-void esp_set_breakpoint_if_jtag(void *fn);
-
-#define ESP_WATCHPOINT_LOAD 0x40000000
-#define ESP_WATCHPOINT_STORE 0x80000000
-#define ESP_WATCHPOINT_ACCESS 0xC0000000
-
-/**
- * @brief Set a watchpoint to break/panic when a certain memory range is accessed.
- *
- * @param no Watchpoint number. On the ESP32, this can be 0 or 1.
- * @param adr Base address to watch
- * @param size Size of the region, starting at the base address, to watch. Must
- *             be one of 2^n, with n in [0..6].
- * @param flags One of ESP_WATCHPOINT_* flags
- *
- * @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
- *
- * @warning The ESP32 watchpoint hardware watches a region of bytes by effectively 
- *          masking away the lower n bits for a region with size 2^n. If adr does
- *          not have zero for these lower n bits, you may not be watching the
- *          region you intended.
- */
-esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags);
-
-
-/**
- * @brief Clear a watchpoint
- *
- * @param no Watchpoint to clear
- *
- */
-void esp_clear_watchpoint(int no);
-
-/**
- * @brief Checks stack pointer in dram
- */
-inline static bool esp_stack_ptr_in_dram(uint32_t sp)
-{
-    //Check if stack ptr is in between SOC_DRAM_LOW and SOC_DRAM_HIGH, and 16 byte aligned.
-    return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0));
-}
-
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-/**
- * @brief Checks stack pointer in external ram
- */
-inline static bool esp_stack_ptr_in_extram(uint32_t sp)
-{
-    //Check if stack ptr is in between SOC_EXTRAM_DATA_LOW and SOC_EXTRAM_DATA_HIGH, and 16 byte aligned.
-    return !(sp < SOC_EXTRAM_DATA_LOW + 0x10 || sp > SOC_EXTRAM_DATA_HIGH - 0x10 || ((sp & 0xF) != 0));
-}
-#endif
-
-/**
- * @brief Checks stack pointer
- */
-static inline bool esp_stack_ptr_is_sane(uint32_t sp)
-{
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-    return (esp_stack_ptr_in_dram(sp) || esp_stack_ptr_in_extram(sp));
-#else
-    return esp_stack_ptr_in_dram(sp);
-#endif
-}
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_phy_init.h b/tools/sdk/include/esp32/esp_phy_init.h
deleted file mode 100644
index 3402f197b0b..00000000000
--- a/tools/sdk/include/esp32/esp_phy_init.h
+++ /dev/null
@@ -1,250 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @file PHY init parameters and API
- */
-
-
-/**
- * @brief Structure holding PHY init parameters
- */
-typedef struct {
-	uint8_t params[128];                    /*!< opaque PHY initialization parameters */
-} esp_phy_init_data_t;
-
-/**
- * @brief Opaque PHY calibration data
- */
-typedef struct {
-    uint8_t version[4];                     /*!< PHY version */
-    uint8_t mac[6];                         /*!< The MAC address of the station */
-    uint8_t opaque[1894];                   /*!< calibration data */
-} esp_phy_calibration_data_t;
-
-typedef enum {
-    PHY_RF_CAL_PARTIAL = 0x00000000,        /*!< Do part of RF calibration. This should be used after power-on reset. */
-    PHY_RF_CAL_NONE    = 0x00000001,        /*!< Don't do any RF calibration. This mode is only suggested to be used after deep sleep reset. */
-    PHY_RF_CAL_FULL    = 0x00000002         /*!< Do full RF calibration. Produces best results, but also consumes a lot of time and current. Suggested to be used once. */
-} esp_phy_calibration_mode_t;
-
-
-/**
- * @brief Modules for modem sleep 
- */
-typedef enum{
-    MODEM_BLE_MODULE,              //!< BLE controller used
-    MODEM_CLASSIC_BT_MODULE,       //!< Classic BT controller used
-    MODEM_WIFI_STATION_MODULE,     //!< Wi-Fi Station used
-    MODEM_WIFI_SOFTAP_MODULE,      //!< Wi-Fi SoftAP used
-    MODEM_WIFI_SNIFFER_MODULE,     //!< Wi-Fi Sniffer used
-    MODEM_WIFI_NULL_MODULE,        //!< Wi-Fi Null mode used
-    MODEM_USER_MODULE,             //!< User used
-    MODEM_MODULE_COUNT             //!< Number of items
-}modem_sleep_module_t;
-
-/**
- * @brief Module WIFI mask for medem sleep
- */
-#define MODEM_BT_MASK   ((1<<MODEM_BLE_MODULE)          |   \
-                         (1<<MODEM_CLASSIC_BT_MODULE))
-
-/**
- * @brief Module WIFI mask for medem sleep
- */
-#define MODEM_WIFI_MASK ((1<<MODEM_WIFI_STATION_MODULE) |   \
-                         (1<<MODEM_WIFI_SOFTAP_MODULE)  |   \
-                         (1<<MODEM_WIFI_SNIFFER_MODULE) |   \
-                         (1<<MODEM_WIFI_NULL_MODULE))
-
-/**
- * @brief Modules needing to call phy_rf_init
- */
-typedef enum{
-    PHY_BT_MODULE,          //!< Bluetooth used
-    PHY_WIFI_MODULE,        //!< Wi-Fi used
-    PHY_MODEM_MODULE,       //!< Modem sleep used
-    PHY_MODULE_COUNT        //!< Number of items
-}phy_rf_module_t;
-
-/**
- * @brief Get PHY init data
- *
- * If "Use a partition to store PHY init data" option is set in menuconfig,
- * This function will load PHY init data from a partition. Otherwise,
- * PHY init data will be compiled into the application itself, and this function
- * will return a pointer to PHY init data located in read-only memory (DROM).
- *
- * If "Use a partition to store PHY init data" option is enabled, this function
- * may return NULL if the data loaded from flash is not valid.
- *
- * @note Call esp_phy_release_init_data to release the pointer obtained using
- * this function after the call to esp_wifi_init.
- *
- * @return pointer to PHY init data structure
- */
-const esp_phy_init_data_t* esp_phy_get_init_data();
-
-/**
- * @brief Release PHY init data
- * @param data  pointer to PHY init data structure obtained from
- *              esp_phy_get_init_data function
- */
-void esp_phy_release_init_data(const esp_phy_init_data_t* data);
-
-/**
- * @brief Function called by esp_phy_init to load PHY calibration data
- *
- * This is a convenience function which can be used to load PHY calibration
- * data from NVS. Data can be stored to NVS using esp_phy_store_cal_data_to_nvs
- * function.
- *
- * If calibration data is not present in the NVS, or
- * data is not valid (was obtained for a chip with a different MAC address,
- * or obtained for a different version of software), this function will
- * return an error.
- *
- * If "Initialize PHY in startup code" option is set in menuconfig, this
- * function will be used to load calibration data. To provide a different
- * mechanism for loading calibration data, disable
- * "Initialize PHY in startup code" option in menuconfig and call esp_phy_init
- * function from the application. For an example usage of esp_phy_init and
- * this function, see esp_phy_store_cal_data_to_nvs function in cpu_start.c
- *
- * @param out_cal_data pointer to calibration data structure to be filled with
- *                     loaded data.
- * @return ESP_OK on success
- */
-esp_err_t esp_phy_load_cal_data_from_nvs(esp_phy_calibration_data_t* out_cal_data);
-
-/**
- * @brief Function called by esp_phy_init to store PHY calibration data
- *
- * This is a convenience function which can be used to store PHY calibration
- * data to the NVS. Calibration data is returned by esp_phy_init function.
- * Data saved using this function to the NVS can later be loaded using
- * esp_phy_store_cal_data_to_nvs function.
- *
- * If "Initialize PHY in startup code" option is set in menuconfig, this
- * function will be used to store calibration data. To provide a different
- * mechanism for storing calibration data, disable
- * "Initialize PHY in startup code" option in menuconfig and call esp_phy_init
- * function from the application.
- *
- * @param cal_data pointer to calibration data which has to be saved.
- * @return ESP_OK on success
- */
-esp_err_t esp_phy_store_cal_data_to_nvs(const esp_phy_calibration_data_t* cal_data);
-
-/**
- * @brief Erase PHY calibration data which is stored in the NVS
- *
- * This is a function which can be used to trigger full calibration as a last-resort remedy 
- * if partial calibration is used. It can be called in the application based on some conditions 
- * (e.g. an option provided in some diagnostic mode).
- *
- * @return ESP_OK on success
- * @return others on fail. Please refer to NVS API return value error number.
- */
-esp_err_t esp_phy_erase_cal_data_in_nvs(void);
-
-/**
- * @brief Initialize PHY and RF module
- *
- * PHY and RF module should be initialized in order to use WiFi or BT.
- * Now PHY and RF initializing job is done automatically when start WiFi or BT. Users should not
- * call this API in their application.
- *
- * @param init_data  PHY parameters. Default set of parameters can
- *                   be obtained by calling esp_phy_get_default_init_data
- *                   function.
- * @param mode  Calibration mode (Full, partial, or no calibration)
- * @param[inout] calibration_data
- * @return ESP_OK on success.
- * @return ESP_FAIL on fail.
- */
-esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data,esp_phy_calibration_mode_t mode, 
-        esp_phy_calibration_data_t* calibration_data, phy_rf_module_t module);
-
-/**
- * @brief De-initialize PHY and RF module
- *
- * PHY module should be de-initialized in order to shutdown WiFi or BT.
- * Now PHY and RF de-initializing job is done automatically when stop WiFi or BT. Users should not
- * call this API in their application.
- *
- * @return ESP_OK on success.
- */
-esp_err_t esp_phy_rf_deinit(phy_rf_module_t module);
-
-/**
- * @brief Load calibration data from NVS and initialize PHY and RF module
- */
-void esp_phy_load_cal_and_init(phy_rf_module_t module);
-
-/**
-* @brief Enable WiFi/BT common clock
-*
-*/
-void esp_phy_common_clock_enable(void);
-
-/**
-* @brief Disable WiFi/BT common clock
-*
-*/
-void esp_phy_common_clock_disable(void);
-
-/**
- * @brief Module requires to enter modem sleep
- */
-esp_err_t esp_modem_sleep_enter(modem_sleep_module_t module);
-
-/**
- * @brief Module requires to exit modem sleep
- */
-esp_err_t esp_modem_sleep_exit(modem_sleep_module_t module);
-
-/**
- * @brief Register module to make it be able to require to enter/exit modem sleep
- *        Although the module has no sleep function, as long as the module use RF,
- *        it must call esp_modem_sleep_regsiter. Otherwise, other modules with sleep
- *        function will disable RF without checking the module which doesn't call
- *        esp_modem_sleep_regsiter.
- */
-esp_err_t esp_modem_sleep_register(modem_sleep_module_t module);
-
-/**
- * @brief De-register module from modem sleep list 
- */
-esp_err_t esp_modem_sleep_deregister(modem_sleep_module_t module);
-
-/**
- * @brief            Get the time stamp when PHY/RF was switched on
- * @return           return 0 if PHY/RF is never switched on. Otherwise return time in
- *                   microsecond since boot when phy/rf was last switched on
-*/
-int64_t esp_phy_rf_get_on_ts(void);
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/tools/sdk/include/esp32/esp_pm.h b/tools/sdk/include/esp32/esp_pm.h
deleted file mode 100644
index 3887e77a921..00000000000
--- a/tools/sdk/include/esp32/esp_pm.h
+++ /dev/null
@@ -1,179 +0,0 @@
-// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-
-// Include SoC-specific definitions. Only ESP32 supported for now.
-#include "esp32/pm.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Power management constraints
- */
-typedef enum {
-    /**
-     * Require CPU frequency to be at the maximum value set via esp_pm_configure.
-     * Argument is unused and should be set to 0.
-     */
-    ESP_PM_CPU_FREQ_MAX,
-    /**
-     * Require APB frequency to be at the maximum value supported by the chip.
-     * Argument is unused and should be set to 0.
-     */
-    ESP_PM_APB_FREQ_MAX,
-    /**
-     * Prevent the system from going into light sleep.
-     * Argument is unused and should be set to 0.
-     */
-    ESP_PM_NO_LIGHT_SLEEP,
-} esp_pm_lock_type_t;
-
-/**
- * @brief Set implementation-specific power management configuration
- * @param config pointer to implementation-specific configuration structure (e.g. esp_pm_config_esp32)
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if the configuration values are not correct
- *      - ESP_ERR_NOT_SUPPORTED if certain combination of values is not supported,
- *        or if CONFIG_PM_ENABLE is not enabled in sdkconfig
- */
-esp_err_t esp_pm_configure(const void* config);
-
-
-/**
- * @brief Opaque handle to the power management lock
- */
-typedef struct esp_pm_lock* esp_pm_lock_handle_t;
-
-
-/**
- * @brief Initialize a lock handle for certain power management parameter
- *
- * When lock is created, initially it is not taken.
- * Call esp_pm_lock_acquire to take the lock.
- *
- * This function must not be called from an ISR.
- *
- * @param lock_type Power management constraint which the lock should control
- * @param arg argument, value depends on lock_type, see esp_pm_lock_type_t
- * @param name arbitrary string identifying the lock (e.g. "wifi" or "spi").
- *             Used by the esp_pm_dump_locks function to list existing locks.
- *             May be set to NULL. If not set to NULL, must point to a string which is valid
- *             for the lifetime of the lock.
- * @param[out] out_handle  handle returned from this function. Use this handle when calling
- *                         esp_pm_lock_delete, esp_pm_lock_acquire, esp_pm_lock_release.
- *                         Must not be NULL.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NO_MEM if the lock structure can not be allocated
- *      - ESP_ERR_INVALID_ARG if out_handle is NULL or type argument is not valid
- *      - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
- */
-esp_err_t esp_pm_lock_create(esp_pm_lock_type_t lock_type, int arg,
-        const char* name, esp_pm_lock_handle_t* out_handle);
-
-/**
- * @brief Take a power management lock
- *
- * Once the lock is taken, power management algorithm will not switch to the
- * mode specified in a call to esp_pm_lock_create, or any of the lower power
- * modes (higher numeric values of 'mode').
- *
- * The lock is recursive, in the sense that if esp_pm_lock_acquire is called
- * a number of times, esp_pm_lock_release has to be called the same number of
- * times in order to release the lock.
- *
- * This function may be called from an ISR.
- *
- * This function is not thread-safe w.r.t. calls to other esp_pm_lock_*
- * functions for the same handle.
- *
- * @param handle handle obtained from esp_pm_lock_create function
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if the handle is invalid
- *      - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
- */
-esp_err_t esp_pm_lock_acquire(esp_pm_lock_handle_t handle);
-
-/**
- * @brief Release the lock taken using esp_pm_lock_acquire.
- *
- * Call to this functions removes power management restrictions placed when
- * taking the lock.
- *
- * Locks are recursive, so if esp_pm_lock_acquire is called a number of times,
- * esp_pm_lock_release has to be called the same number of times in order to
- * actually release the lock.
- *
- * This function may be called from an ISR.
- *
- * This function is not thread-safe w.r.t. calls to other esp_pm_lock_*
- * functions for the same handle.
- *
- * @param handle handle obtained from esp_pm_lock_create function
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if the handle is invalid
- *      - ESP_ERR_INVALID_STATE if lock is not acquired
- *      - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
- */
-esp_err_t esp_pm_lock_release(esp_pm_lock_handle_t handle);
-
-/**
- * @brief Delete a lock created using esp_pm_lock
- *
- * The lock must be released before calling this function.
- *
- * This function must not be called from an ISR.
- *
- * @param handle handle obtained from esp_pm_lock_create function
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if the handle argument is NULL
- *      - ESP_ERR_INVALID_STATE if the lock is still acquired
- *      - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
- */
-esp_err_t esp_pm_lock_delete(esp_pm_lock_handle_t handle);
-
-/**
- * Dump the list of all locks to stderr
- *
- * This function dumps debugging information about locks created using
- * esp_pm_lock_create to an output stream.
- *
- * This function must not be called from an ISR. If esp_pm_lock_acquire/release
- * are called while this function is running, inconsistent results may be
- * reported.
- *
- * @param stream stream to print information to; use stdout or stderr to print
- *               to the console; use fmemopen/open_memstream to print to a
- *               string buffer.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NOT_SUPPORTED if CONFIG_PM_ENABLE is not enabled in sdkconfig
- */
-esp_err_t esp_pm_dump_locks(FILE* stream);
-
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp32/esp_private/esp_wifi_private.h b/tools/sdk/include/esp32/esp_private/esp_wifi_private.h
deleted file mode 100644
index fcdebb6ba59..00000000000
--- a/tools/sdk/include/esp32/esp_private/esp_wifi_private.h
+++ /dev/null
@@ -1,24 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_WIFI_PRIVATE_H
-#define _ESP_WIFI_PRIVATE_H
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/queue.h"
-#include "rom/queue.h"
-#include "sdkconfig.h"
-#include "esp_wifi_crypto_types.h"
-#include "esp_wifi_os_adapter.h"
-
-#endif /* _ESP_WIFI_PRIVATE_H */
diff --git a/tools/sdk/include/esp32/esp_private/esp_wifi_types_private.h b/tools/sdk/include/esp32/esp_private/esp_wifi_types_private.h
deleted file mode 100644
index dd56e0fdecf..00000000000
--- a/tools/sdk/include/esp32/esp_private/esp_wifi_types_private.h
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_WIFI_TYPES_PRIVATE_H
-#define _ESP_WIFI_TYPES_PRIVATE_H
-
-#include "rom/queue.h"
-#include "esp_interface.h"
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_sleep.h b/tools/sdk/include/esp32/esp_sleep.h
deleted file mode 100644
index c21f26add51..00000000000
--- a/tools/sdk/include/esp32/esp_sleep.h
+++ /dev/null
@@ -1,373 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <stdint.h>
-#include "esp_err.h"
-#include "driver/gpio.h"
-#include "driver/touch_pad.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Logic function used for EXT1 wakeup mode.
- */
-typedef enum {
-    ESP_EXT1_WAKEUP_ALL_LOW = 0,    //!< Wake the chip when all selected GPIOs go low
-    ESP_EXT1_WAKEUP_ANY_HIGH = 1    //!< Wake the chip when any of the selected GPIOs go high
-} esp_sleep_ext1_wakeup_mode_t;
-
-/**
- * @brief Power domains which can be powered down in sleep mode
- */
-typedef enum {
-    ESP_PD_DOMAIN_RTC_PERIPH,      //!< RTC IO, sensors and ULP co-processor
-    ESP_PD_DOMAIN_RTC_SLOW_MEM,    //!< RTC slow memory
-    ESP_PD_DOMAIN_RTC_FAST_MEM,    //!< RTC fast memory
-    ESP_PD_DOMAIN_XTAL,            //!< XTAL oscillator
-    ESP_PD_DOMAIN_MAX              //!< Number of domains
-} esp_sleep_pd_domain_t;
-
-/**
- * @brief Power down options
- */
-typedef enum {
-    ESP_PD_OPTION_OFF,      //!< Power down the power domain in sleep mode
-    ESP_PD_OPTION_ON,       //!< Keep power domain enabled during sleep mode
-    ESP_PD_OPTION_AUTO      //!< Keep power domain enabled in sleep mode, if it is needed by one of the wakeup options. Otherwise power it down.
-} esp_sleep_pd_option_t;
-
-/**
- * @brief Sleep wakeup cause
- */
-typedef enum {
-    ESP_SLEEP_WAKEUP_UNDEFINED,    //!< In case of deep sleep, reset was not caused by exit from deep sleep
-    ESP_SLEEP_WAKEUP_ALL,          //!< Not a wakeup cause, used to disable all wakeup sources with esp_sleep_disable_wakeup_source
-    ESP_SLEEP_WAKEUP_EXT0,         //!< Wakeup caused by external signal using RTC_IO
-    ESP_SLEEP_WAKEUP_EXT1,         //!< Wakeup caused by external signal using RTC_CNTL
-    ESP_SLEEP_WAKEUP_TIMER,        //!< Wakeup caused by timer
-    ESP_SLEEP_WAKEUP_TOUCHPAD,     //!< Wakeup caused by touchpad
-    ESP_SLEEP_WAKEUP_ULP,          //!< Wakeup caused by ULP program
-    ESP_SLEEP_WAKEUP_GPIO,         //!< Wakeup caused by GPIO (light sleep only)
-    ESP_SLEEP_WAKEUP_UART,         //!< Wakeup caused by UART (light sleep only)
-} esp_sleep_source_t;
-
-/* Leave this type define for compatibility */
-typedef esp_sleep_source_t esp_sleep_wakeup_cause_t;
-
-/**
- * @brief Disable wakeup source
- *
- * This function is used to deactivate wake up trigger for source
- * defined as parameter of the function.
- *
- * @note This function does not modify wake up configuration in RTC.
- *       It will be performed in esp_sleep_start function.
- *
- * See docs/sleep-modes.rst for details.
- *
- * @param source - number of source to disable of type esp_sleep_source_t
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if trigger was not active
- */
-esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source);
-
-/**
- * @brief Enable wakeup by ULP coprocessor
- * @note In revisions 0 and 1 of the ESP32, ULP wakeup source
- *       can not be used when RTC_PERIPH power domain is forced
- *       to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup
- *       source is used.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
- *      - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
- */
-esp_err_t esp_sleep_enable_ulp_wakeup();
-
-/**
- * @brief Enable wakeup by timer
- * @param time_in_us  time before wakeup, in microseconds
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if value is out of range (TBD)
- */
-esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
-
-/**
- * @brief Enable wakeup by touch sensor
- *
- * @note In revisions 0 and 1 of the ESP32, touch wakeup source
- *       can not be used when RTC_PERIPH power domain is forced
- *       to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup
- *       source is used.
- *
- * @note The FSM mode of the touch button should be configured
- *       as the timer trigger mode.
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT) is enabled.
- *      - ESP_ERR_INVALID_STATE if wakeup triggers conflict
- */
-esp_err_t esp_sleep_enable_touchpad_wakeup();
-
-/**
- * @brief Get the touch pad which caused wakeup
- *
- * If wakeup was caused by another source, this function will return TOUCH_PAD_MAX;
- *
- * @return touch pad which caused wakeup
- */
-touch_pad_t esp_sleep_get_touchpad_wakeup_status();
-
-/**
- * @brief Enable wakeup using a pin
- *
- * This function uses external wakeup feature of RTC_IO peripheral.
- * It will work only if RTC peripherals are kept on during sleep.
- *
- * This feature can monitor any pin which is an RTC IO. Once the pin transitions
- * into the state given by level argument, the chip will be woken up.
- *
- * @note This function does not modify pin configuration. The pin is
- *       configured in esp_sleep_start, immediately before entering sleep mode.
- *
- * @note In revisions 0 and 1 of the ESP32, ext0 wakeup source
- *       can not be used together with touch or ULP wakeup sources.
- *
- * @param gpio_num  GPIO number used as wakeup source. Only GPIOs which are have RTC
- *             functionality can be used: 0,2,4,12-15,25-27,32-39.
- * @param level  input level which will trigger wakeup (0=low, 1=high)
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if the selected GPIO is not an RTC GPIO,
- *        or the mode is invalid
- *      - ESP_ERR_INVALID_STATE if wakeup triggers conflict
- */
-esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level);
-
-/**
- * @brief Enable wakeup using multiple pins
- *
- * This function uses external wakeup feature of RTC controller.
- * It will work even if RTC peripherals are shut down during sleep.
- *
- * This feature can monitor any number of pins which are in RTC IOs.
- * Once any of the selected pins goes into the state given by mode argument,
- * the chip will be woken up.
- *
- * @note This function does not modify pin configuration. The pins are
- *       configured in esp_sleep_start, immediately before
- *       entering sleep mode.
- *
- * @note internal pullups and pulldowns don't work when RTC peripherals are
- *       shut down. In this case, external resistors need to be added.
- *       Alternatively, RTC peripherals (and pullups/pulldowns) may be
- *       kept enabled using esp_sleep_pd_config function.
- *
- * @param mask  bit mask of GPIO numbers which will cause wakeup. Only GPIOs
- *              which are have RTC functionality can be used in this bit map:
- *              0,2,4,12-15,25-27,32-39.
- * @param mode select logic function used to determine wakeup condition:
- *            - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low
- *            - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO,
- *        or mode is invalid
- */
-esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode);
-
-/**
- * @brief Enable wakeup from light sleep using GPIOs
- *
- * Each GPIO supports wakeup function, which can be triggered on either low level
- * or high level. Unlike EXT0 and EXT1 wakeup sources, this method can be used
- * both for all IOs: RTC IOs and digital IOs. It can only be used to wakeup from
- * light sleep though.
- *
- * To enable wakeup, first call gpio_wakeup_enable, specifying gpio number and
- * wakeup level, for each GPIO which is used for wakeup.
- * Then call this function to enable wakeup feature.
- *
- * @note In revisions 0 and 1 of the ESP32, GPIO wakeup source
- *       can not be used together with touch or ULP wakeup sources.
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if wakeup triggers conflict
- */
-esp_err_t esp_sleep_enable_gpio_wakeup();
-
-/**
- * @brief Enable wakeup from light sleep using UART
- *
- * Use uart_set_wakeup_threshold function to configure UART wakeup threshold.
- *
- * Wakeup from light sleep takes some time, so not every character sent
- * to the UART can be received by the application.
- *
- * @note ESP32 does not support wakeup from UART2.
- *
- * @param uart_num  UART port to wake up from
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if wakeup from given UART is not supported
- */
-esp_err_t esp_sleep_enable_uart_wakeup(int uart_num);
-
-/**
- * @brief Get the bit mask of GPIOs which caused wakeup (ext1)
- *
- * If wakeup was caused by another source, this function will return 0.
- *
- * @return bit mask, if GPIOn caused wakeup, BIT(n) will be set
- */
-uint64_t esp_sleep_get_ext1_wakeup_status();
-
-/**
- * @brief Set power down mode for an RTC power domain in sleep mode
- *
- * If not set set using this API, all power domains default to ESP_PD_OPTION_AUTO.
- *
- * @param domain  power domain to configure
- * @param option  power down option (ESP_PD_OPTION_OFF, ESP_PD_OPTION_ON, or ESP_PD_OPTION_AUTO)
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if either of the arguments is out of range
- */
-esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
-                                   esp_sleep_pd_option_t option);
-
-/**
- * @brief Enter deep sleep with the configured wakeup options
- *
- * This function does not return.
- */
-void esp_deep_sleep_start() __attribute__((noreturn));
-
-/**
- * @brief Enter light sleep with the configured wakeup options
- *
- * @return
- *  - ESP_OK on success (returned after wakeup)
- *  - ESP_ERR_INVALID_STATE if WiFi or BT is not stopped
- */
-esp_err_t esp_light_sleep_start();
-
-/**
- * @brief Enter deep-sleep mode
- *
- * The device will automatically wake up after the deep-sleep time
- * Upon waking up, the device calls deep sleep wake stub, and then proceeds
- * to load application.
- *
- * Call to this function is equivalent to a call to esp_deep_sleep_enable_timer_wakeup
- * followed by a call to esp_deep_sleep_start.
- *
- * esp_deep_sleep does not shut down WiFi, BT, and higher level protocol
- * connections gracefully.
- * Make sure relevant WiFi and BT stack functions are called to close any
- * connections and deinitialize the peripherals. These include:
- *     - esp_bluedroid_disable
- *     - esp_bt_controller_disable
- *     - esp_wifi_stop
- *
- * This function does not return.
- *
- * @param time_in_us  deep-sleep time, unit: microsecond
- */
-void esp_deep_sleep(uint64_t time_in_us) __attribute__((noreturn));
-
-/**
- * @brief Enter deep-sleep mode
- *
- * Function has been renamed to esp_deep_sleep.
- * This name is deprecated and will be removed in a future version.
- *
- * @param time_in_us  deep-sleep time, unit: microsecond
- */
-void system_deep_sleep(uint64_t time_in_us) __attribute__((noreturn, deprecated));
-
-
-/**
- * @brief Get the wakeup source which caused wakeup from sleep
- *
- * @return cause of wake up from last sleep (deep sleep or light sleep)
- */
-esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause();
-
-
-/**
- * @brief Default stub to run on wake from deep sleep.
- *
- * Allows for executing code immediately on wake from sleep, before
- * the software bootloader or ESP-IDF app has started up.
- *
- * This function is weak-linked, so you can implement your own version
- * to run code immediately when the chip wakes from
- * sleep.
- *
- * See docs/deep-sleep-stub.rst for details.
- */
-void esp_wake_deep_sleep(void);
-
-/**
- * @brief Function type for stub to run on wake from sleep.
- *
- */
-typedef void (*esp_deep_sleep_wake_stub_fn_t)(void);
-
-/**
- * @brief Install a new stub at runtime to run on wake from deep sleep
- *
- * If implementing esp_wake_deep_sleep() then it is not necessary to
- * call this function.
- *
- * However, it is possible to call this function to substitute a
- * different deep sleep stub. Any function used as a deep sleep stub
- * must be marked RTC_IRAM_ATTR, and must obey the same rules given
- * for esp_wake_deep_sleep().
- */
-void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub);
-
-/**
- * @brief Get current wake from deep sleep stub
- * @return Return current wake from deep sleep stub, or NULL if
- *         no stub is installed.
- */
-esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void);
-
-/**
- *  @brief The default esp-idf-provided esp_wake_deep_sleep() stub.
- *
- *  See docs/deep-sleep-stub.rst for details.
- */
-void esp_default_wake_deep_sleep(void);
-
-/**
- *  @brief Disable logging from the ROM code after deep sleep.
- *
- *  Using LSB of RTC_STORE4.
- */
-void esp_deep_sleep_disable_rom_logging(void);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp32/esp_smartconfig.h b/tools/sdk/include/esp32/esp_smartconfig.h
deleted file mode 100644
index 34cf8667ab9..00000000000
--- a/tools/sdk/include/esp32/esp_smartconfig.h
+++ /dev/null
@@ -1,136 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_SMARTCONFIG_H__
-#define __ESP_SMARTCONFIG_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    SC_STATUS_WAIT = 0,             /**< Waiting to start connect */
-    SC_STATUS_FIND_CHANNEL,         /**< Finding target channel */
-    SC_STATUS_GETTING_SSID_PSWD,    /**< Getting SSID and password of target AP */
-    SC_STATUS_LINK,                 /**< Connecting to target AP */
-    SC_STATUS_LINK_OVER,            /**< Connected to AP successfully */
-} smartconfig_status_t;
-
-typedef enum {
-    SC_TYPE_ESPTOUCH = 0,       /**< protocol: ESPTouch */
-    SC_TYPE_AIRKISS,            /**< protocol: AirKiss */
-    SC_TYPE_ESPTOUCH_AIRKISS,   /**< protocol: ESPTouch and AirKiss */
-} smartconfig_type_t;
-
-/**
-  * @brief  The callback of SmartConfig, executed when smart-config status changed.
-  *
-  * @param  status  Status of SmartConfig:
-  *    - SC_STATUS_GETTING_SSID_PSWD : pdata is a pointer of smartconfig_type_t, means config type.
-  *    - SC_STATUS_LINK : pdata is a pointer to wifi_config_t.
-  *    - SC_STATUS_LINK_OVER : pdata is a pointer of phone's IP address(4 bytes) if pdata unequal NULL.
-  *    - otherwise : parameter void *pdata is NULL.
-  * @param  pdata  According to the different status have different values.
-  *
-  */
-typedef void (*sc_callback_t)(smartconfig_status_t status, void *pdata);
-
-/**
-  * @brief  Get the version of SmartConfig.
-  *
-  * @return
-  *     - SmartConfig version const char.
-  */
-const char *esp_smartconfig_get_version(void);
-
-/**
-  * @brief     Start SmartConfig, config ESP device to connect AP. You need to broadcast information by phone APP.
-  *            Device sniffer special packets from the air that containing SSID and password of target AP.
-  *
-  * @attention 1. This API can be called in station or softAP-station mode.
-  * @attention 2. Can not call esp_smartconfig_start twice before it finish, please call
-  *               esp_smartconfig_stop first.
-  *
-  * @param     cb  SmartConfig callback function.
-  * @param     ... log  1: UART output logs; 0: UART only outputs the result.
-  *
-  * @return
-  *     - ESP_OK: succeed
-  *     - others: fail
-  */
-esp_err_t esp_smartconfig_start(sc_callback_t cb, ...);
-
-/**
-  * @brief     Stop SmartConfig, free the buffer taken by esp_smartconfig_start.
-  *
-  * @attention Whether connect to AP succeed or not, this API should be called to free
-  *            memory taken by smartconfig_start.
-  *
-  * @return
-  *     - ESP_OK: succeed
-  *     - others: fail
-  */
-esp_err_t esp_smartconfig_stop(void);
-
-/**
-  * @brief     Set timeout of SmartConfig process.
-  *
-  * @attention Timing starts from SC_STATUS_FIND_CHANNEL status. SmartConfig will restart if timeout.
-  *
-  * @param     time_s  range 15s~255s, offset:45s.
-  *
-  * @return
-  *     - ESP_OK: succeed
-  *     - others: fail
-  */
-esp_err_t esp_esptouch_set_timeout(uint8_t time_s);
-
-/**
-  * @brief     Set protocol type of SmartConfig.
-  *
-  * @attention If users need to set the SmartConfig type, please set it before calling
-  *            esp_smartconfig_start.
-  *
-  * @param     type  Choose from the smartconfig_type_t.
-  *
-  * @return
-  *     - ESP_OK: succeed
-  *     - others: fail
-  */
-esp_err_t esp_smartconfig_set_type(smartconfig_type_t type);
-
-/**
-  * @brief     Set mode of SmartConfig. default normal mode.
-  *
-  * @attention 1. Please call it before API esp_smartconfig_start.
-  * @attention 2. Fast mode have corresponding APP(phone).
-  * @attention 3. Two mode is compatible.
-  *
-  * @param     enable  false-disable(default); true-enable;
-  *
-  * @return
-  *     - ESP_OK: succeed
-  *     - others: fail
-  */
-esp_err_t esp_smartconfig_fast_mode(bool enable);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_spiram.h b/tools/sdk/include/esp32/esp_spiram.h
deleted file mode 100644
index a55872cd4de..00000000000
--- a/tools/sdk/include/esp32/esp_spiram.h
+++ /dev/null
@@ -1,116 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_SPIRAM_H
-#define __ESP_SPIRAM_H
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-
-typedef enum {
-    ESP_SPIRAM_SIZE_16MBITS = 0,   /*!< SPI RAM size is 16 MBits */
-    ESP_SPIRAM_SIZE_32MBITS = 1,   /*!< SPI RAM size is 32 MBits */
-    ESP_SPIRAM_SIZE_64MBITS = 2,   /*!< SPI RAM size is 64 MBits */
-    ESP_SPIRAM_SIZE_INVALID,       /*!< SPI RAM size is invalid */
-} esp_spiram_size_t;
-
-/**
- * @brief get SPI RAM size
- * @return
- *     - ESP_SPIRAM_SIZE_INVALID if SPI RAM not enabled or not valid
- *     - SPI RAM size
- */
-esp_spiram_size_t esp_spiram_get_chip_size();
-
-/**
- * @brief Initialize spiram interface/hardware. Normally called from cpu_start.c.
- *
- * @return ESP_OK on success
- */
-esp_err_t esp_spiram_init();
-
-/**
- * @brief Configure Cache/MMU for access to external SPI RAM.
- *
- * Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
- * option is enabled. Applications which need to enable SPI RAM at run time
- * can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
- *
- * @attention this function must be called with flash cache disabled.
- */
-void esp_spiram_init_cache();
-
-
-/**
- * @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
- * (in case of a dual-core system) the app CPU is online. This test overwrites the
- * memory with crap, so do not call after e.g. the heap allocator has stored important
- * stuff in SPI RAM.
- *
- * @return true on success, false on failed memory test
- */
-bool esp_spiram_test();
-
-
-/**
- * @brief Add the initialized SPI RAM to the heap allocator.
- */
-esp_err_t esp_spiram_add_to_heapalloc();
-
-
-/**
- * @brief Get the size of the attached SPI RAM chip selected in menuconfig
- *
- * @return Size in bytes, or 0 if no external RAM chip support compiled in.
- */
-size_t esp_spiram_get_size();
-
-
-/**
- * @brief Force a writeback of the data in the SPI RAM cache. This is to be called whenever
- * cache is disabled, because disabling cache on the ESP32 discards the data in the SPI
- * RAM cache.
- *
- * This is meant for use from within the SPI flash code.
- */
-void esp_spiram_writeback_cache();
-
-
-
-/**
- * @brief Reserve a pool of internal memory for specific DMA/internal allocations
- *
- * @param size Size of reserved pool in bytes
- *
- * @return
- *          - ESP_OK on success
- *          - ESP_ERR_NO_MEM when no memory available for pool
- */
-esp_err_t esp_spiram_reserve_dma_pool(size_t size);
-
-
-/**
- * @brief If SPI RAM(PSRAM) has been initialized
- *
- * @return
- *          - true SPI RAM has been initialized successfully
- *          - false SPI RAM hasn't been initialized or initialized failed
- */
-bool esp_spiram_is_initialized(void);
-
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_ssc.h b/tools/sdk/include/esp32/esp_ssc.h
deleted file mode 100644
index 02893ff4106..00000000000
--- a/tools/sdk/include/esp32/esp_ssc.h
+++ /dev/null
@@ -1,119 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_SSC_H__
-#define __ESP_SSC_H__
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define CMD_T_ASYNC   0x01
-#define CMD_T_SYNC    0x02
-
-typedef struct cmd_s {
-    char *cmd_str;
-    uint8_t flag;
-    uint8_t id;
-    void (* cmd_func)(void);
-    void (* cmd_callback)(void *arg);
-} ssc_cmd_t;
-
-#define MAX_LINE_N  127
-
-typedef enum {
-    SSC_BR_9600   = 9600,
-    SSC_BR_19200  = 19200,
-    SSC_BR_38400  = 38400,
-    SSC_BR_57600  = 57600,
-    SSC_BR_74880  = 74880,
-    SSC_BR_115200 = 115200,
-    SSC_BR_230400 = 230400,
-    SSC_BR_460800 = 460800,
-    SSC_BR_921600 = 921600
-} SscBaudRate;
-
-/** \defgroup SSC_APIs SSC APIs
-  * @brief SSC APIs
-  *
-  * SSC means simple serial command.
-  * SSC APIs allows users to define their own command, users can refer to spiffs_test/test_main.c.
-  *
-  */
-
-/** @addtogroup SSC_APIs
-  * @{
-  */
-
-/**
-  * @brief  Initial the ssc function.
-  *
-  * @attention param is no use, just compatible with ESP8266, default bandrate is 115200
-  *
-  * @param  SscBaudRate bandrate : baud rate
-  *
-  * @return null
-  */
-void ssc_attach(SscBaudRate bandrate);
-
-/**
-  * @brief   Get the length of the simple serial command.
-  *
-  * @param   null
-  *
-  * @return  length of the command.
-  */
-int ssc_param_len(void);
-
-/**
-  * @brief   Get the simple serial command string.
-  *
-  * @param   null
-  *
-  * @return  the command.
-  */
-char *ssc_param_str(void);
-
-/**
-  * @brief   Parse the simple serial command (ssc).
-  *
-  * @param   char *pLine  : [input] the ssc string
-  * @param   char *argv[] : [output] parameters of the ssc
-  *
-  * @return  the number of parameters.
-  */
-int ssc_parse_param(char *pLine, char *argv[]);
-
-/**
-  * @brief  Register the user-defined simple serial command (ssc) set.
-  *
-  * @param  ssc_cmd_t *cmdset   : the ssc set
-  * @param  uint8 cmdnum        : number of commands
-  * @param  void (* help)(void) : callback of user-guide
-  *
-  * @return  null
-  */
-void ssc_register(ssc_cmd_t *cmdset, uint8_t cmdnum, void (* help)(void));
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_SSC_H__ */
diff --git a/tools/sdk/include/esp32/esp_system.h b/tools/sdk/include/esp32/esp_system.h
deleted file mode 100644
index 1afbe1fdc56..00000000000
--- a/tools/sdk/include/esp32/esp_system.h
+++ /dev/null
@@ -1,348 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_SYSTEM_H__
-#define __ESP_SYSTEM_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-#include "esp_sleep.h"
-#include "esp_idf_version.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ESP_MAC_WIFI_STA,
-    ESP_MAC_WIFI_SOFTAP,
-    ESP_MAC_BT,
-    ESP_MAC_ETH,
-} esp_mac_type_t;
-
-/** @cond */
-#define TWO_UNIVERSAL_MAC_ADDR 2
-#define FOUR_UNIVERSAL_MAC_ADDR 4
-#define UNIVERSAL_MAC_ADDR_NUM CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS
-/** @endcond */
-
-/**
- * @brief Reset reasons
- */
-typedef enum {
-    ESP_RST_UNKNOWN,    //!< Reset reason can not be determined
-    ESP_RST_POWERON,    //!< Reset due to power-on event
-    ESP_RST_EXT,        //!< Reset by external pin (not applicable for ESP32)
-    ESP_RST_SW,         //!< Software reset via esp_restart
-    ESP_RST_PANIC,      //!< Software reset due to exception/panic
-    ESP_RST_INT_WDT,    //!< Reset (software or hardware) due to interrupt watchdog
-    ESP_RST_TASK_WDT,   //!< Reset due to task watchdog
-    ESP_RST_WDT,        //!< Reset due to other watchdogs
-    ESP_RST_DEEPSLEEP,  //!< Reset after exiting deep sleep mode
-    ESP_RST_BROWNOUT,   //!< Brownout reset (software or hardware)
-    ESP_RST_SDIO,       //!< Reset over SDIO
-} esp_reset_reason_t;
-
-/** @cond */
-/**
-  * @attention  Applications don't need to call this function anymore. It does nothing and will
-  *             be removed in future version.
-  */
-void system_init(void) __attribute__ ((deprecated));
-
-/**
-  * @brief  Reset to default settings.
-  *
-  * Function has been deprecated, please use esp_wifi_restore instead.
-  * This name will be removed in a future release.
-  */
-void system_restore(void) __attribute__ ((deprecated));
-/** @endcond */
-
-/**
- * Shutdown handler type
- */
-typedef void (*shutdown_handler_t)(void);
-
-/**
-  * @brief  Register shutdown handler
-  *
-  * This function allows you to register a handler that gets invoked before
-  * the application is restarted using esp_restart function.
-  */
-esp_err_t esp_register_shutdown_handler(shutdown_handler_t handle);
-
-/**
-  * @brief  Restart PRO and APP CPUs.
-  *
-  * This function can be called both from PRO and APP CPUs.
-  * After successful restart, CPU reset reason will be SW_CPU_RESET.
-  * Peripherals (except for WiFi, BT, UART0, SPI1, and legacy timers) are not reset.
-  * This function does not return.
-  */
-void esp_restart(void) __attribute__ ((noreturn));
-
-/** @cond */
-/**
-  * @brief  Restart system.
-  *
-  * Function has been renamed to esp_restart.
-  * This name will be removed in a future release.
-  */
-void system_restart(void) __attribute__ ((deprecated, noreturn));
-/** @endcond */
-
-/**
- * @brief  Get reason of last reset
- * @return See description of esp_reset_reason_t for explanation of each value.
- */
-esp_reset_reason_t esp_reset_reason(void);
-
-/** @cond */
-/**
-  * @brief  Get system time, unit: microsecond.
-  *
-  * This function is deprecated. Use 'gettimeofday' function for 64-bit precision.
-  * This definition will be removed in a future release.
-  */
-uint32_t system_get_time(void)  __attribute__ ((deprecated));
-/** @endcond */
-
-/**
-  * @brief  Get the size of available heap.
-  *
-  * Note that the returned value may be larger than the maximum contiguous block
-  * which can be allocated.
-  *
-  * @return Available heap size, in bytes.
-  */
-uint32_t esp_get_free_heap_size(void);
-
-/**
- * @brief  Get the size of available internal heap.
- *
- * Note that the returned value may be larger than the maximum contiguous block
- * which can be allocated.
- *
- * @return Available internal heap size, in bytes.
- */
-uint32_t esp_get_free_internal_heap_size(void);
-
-/** @cond */
-/**
-  * @brief  Get the size of available heap.
-  *
-  * Function has been renamed to esp_get_free_heap_size.
-  * This name will be removed in a future release.
-  *
-  * @return Available heap size, in bytes.
-  */
-uint32_t system_get_free_heap_size(void)  __attribute__ ((deprecated));
-/** @endcond */
-
-/**
-  * @brief Get the minimum heap that has ever been available
-  *
-  * @return Minimum free heap ever available
-  */
-uint32_t esp_get_minimum_free_heap_size( void );
-
-/**
- * @brief  Get one random 32-bit word from hardware RNG
- *
- * The hardware RNG is fully functional whenever an RF subsystem is running (ie Bluetooth or WiFi is enabled). For
- * random values, call this function after WiFi or Bluetooth are started.
- *
- * If the RF subsystem is not used by the program, the function bootloader_random_enable() can be called to enable an
- * entropy source. bootloader_random_disable() must be called before RF subsystem or I2S peripheral are used. See these functions'
- * documentation for more details.
- *
- * Any time the app is running without an RF subsystem (or bootloader_random) enabled, RNG hardware should be
- * considered a PRNG. A very small amount of entropy is available due to pre-seeding while the IDF
- * bootloader is running, but this should not be relied upon for any use.
- *
- * @return Random value between 0 and UINT32_MAX
- */
-uint32_t esp_random(void);
-
-/**
- * @brief Fill a buffer with random bytes from hardware RNG
- *
- * @note This function has the same restrictions regarding available entropy as esp_random()
- *
- * @param buf Pointer to buffer to fill with random numbers.
- * @param len Length of buffer in bytes
- */
-void esp_fill_random(void *buf, size_t len);
-
-/**
-  * @brief  Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or
-  *         external storage e.g. flash and EEPROM.
-  *
-  * Base MAC address is used to generate the MAC addresses used by the networking interfaces.
-  * If using base MAC address stored in BLK3 of EFUSE or external storage, call this API to set base MAC
-  * address with the MAC address which is stored in BLK3 of EFUSE or external storage before initializing
-  * WiFi/BT/Ethernet.
-  *
-  * @param  mac  base MAC address, length: 6 bytes.
-  *
-  * @return ESP_OK on success
-  */
-esp_err_t esp_base_mac_addr_set(uint8_t *mac);
-
-/**
-  * @brief  Return base MAC address which is set using esp_base_mac_addr_set.
-  *
-  * @param  mac  base MAC address, length: 6 bytes.
-  *
-  * @return ESP_OK on success
-  *         ESP_ERR_INVALID_MAC base MAC address has not been set
-  */
-esp_err_t esp_base_mac_addr_get(uint8_t *mac);
-
-/**
-  * @brief  Return base MAC address which was previously written to BLK3 of EFUSE.
-  *
-  * Base MAC address is used to generate the MAC addresses used by the networking interfaces.
-  * This API returns the custom base MAC address which was previously written to BLK3 of EFUSE.
-  * Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also
-  * possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details.
-  *
-  * @param  mac  base MAC address, length: 6 bytes.
-  *
-  * @return ESP_OK on success
-  *         ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE
-  *         ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE
-  */
-esp_err_t esp_efuse_mac_get_custom(uint8_t *mac);
-
-/**
-  * @brief  Return base MAC address which is factory-programmed by Espressif in BLK0 of EFUSE.
-  *
-  * @param  mac  base MAC address, length: 6 bytes.
-  *
-  * @return ESP_OK on success
-  */
-esp_err_t esp_efuse_mac_get_default(uint8_t *mac);
-
-/** @cond */
-/**
-  * @brief  Read hardware MAC address from efuse.
-  *
-  * Function has been renamed to esp_efuse_mac_get_default.
-  * This name will be removed in a future release.
-  *
-  * @param  mac  hardware MAC address, length: 6 bytes.
-  *
-  * @return ESP_OK on success
-  */
-esp_err_t esp_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
-
-/**
-  * @brief  Read hardware MAC address.
-  *
-  * Function has been renamed to esp_efuse_mac_get_default.
-  * This name will be removed in a future release.
-  *
-  * @param  mac  hardware MAC address, length: 6 bytes.
-  * @return ESP_OK on success
-  */
-esp_err_t system_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
-/** @endcond */
-
-/**
-  * @brief  Read base MAC address and set MAC address of the interface.
-  *
-  * This function first get base MAC address using esp_base_mac_addr_get or reads base MAC address
-  * from BLK0 of EFUSE. Then set the MAC address of the interface including wifi station, wifi softap,
-  * bluetooth and ethernet.
-  *
-  * @param  mac  MAC address of the interface, length: 6 bytes.
-  * @param  type  type of MAC address, 0:wifi station, 1:wifi softap, 2:bluetooth, 3:ethernet.
-  *
-  * @return ESP_OK on success
-  */
-esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type);
-
-/**
-  * @brief  Derive local MAC address from universal MAC address.
-  *
-  * This function derives a local MAC address from an universal MAC address.
-  * A `definition of local vs universal MAC address can be found on Wikipedia
-  * <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`.
-  * In ESP32, universal MAC address is generated from base MAC address in EFUSE or other external storage.
-  * Local MAC address is derived from the universal MAC address.
-  *
-  * @param  local_mac  Derived local MAC address, length: 6 bytes.
-  * @param  universal_mac  Source universal MAC address, length: 6 bytes.
-  *
-  * @return ESP_OK on success
-  */
-esp_err_t esp_derive_local_mac(uint8_t* local_mac, const uint8_t* universal_mac);
-
-/** @cond */
-/**
- * Get SDK version
- *
- * This function is deprecated and will be removed in a future release.
- *
- * @return constant string "master"
- */
-const char* system_get_sdk_version(void)  __attribute__ ((deprecated));
-/** @endcond */
-
-/**
- * @brief Chip models
- */
-typedef enum {
-    CHIP_ESP32 = 1, //!< ESP32
-} esp_chip_model_t;
-
-/* Chip feature flags, used in esp_chip_info_t */
-#define CHIP_FEATURE_EMB_FLASH      BIT(0)      //!< Chip has embedded flash memory
-#define CHIP_FEATURE_WIFI_BGN       BIT(1)      //!< Chip has 2.4GHz WiFi
-#define CHIP_FEATURE_BLE            BIT(4)      //!< Chip has Bluetooth LE
-#define CHIP_FEATURE_BT             BIT(5)      //!< Chip has Bluetooth Classic
-
-/**
- * @brief The structure represents information about the chip
- */
-typedef struct {
-    esp_chip_model_t model;  //!< chip model, one of esp_chip_model_t
-    uint32_t features;       //!< bit mask of CHIP_FEATURE_x feature flags
-    uint8_t cores;           //!< number of CPU cores
-    uint8_t revision;        //!< chip revision number
-} esp_chip_info_t;
-
-/**
- * @brief Fill an esp_chip_info_t structure with information about the chip
- * @param[out] out_info structure to be filled
- */
-void esp_chip_info(esp_chip_info_t* out_info);
-
-/**
- * @brief Cache lock bug exists or not
- *
- * @return
- *          - true : bug exists
- *          - false : bug not exists
- */
-bool soc_has_cache_lock_bug(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_SYSTEM_H__ */
diff --git a/tools/sdk/include/esp32/esp_task.h b/tools/sdk/include/esp32/esp_task.h
deleted file mode 100644
index 754014b5511..00000000000
--- a/tools/sdk/include/esp32/esp_task.h
+++ /dev/null
@@ -1,58 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-/* Notes:
- * 1. Put all task priority and stack size definition in this file
- * 2. If the task priority is less than 10, use ESP_TASK_PRIO_MIN + X style,
- *    otherwise use ESP_TASK_PRIO_MAX - X style
- * 3. If this is a daemon task, the macro prefix is ESP_TASKD_, otherwise
- *    it's ESP_TASK_
- * 4. If the configMAX_PRIORITIES is modified, please make all priority are
- *    greater than 0
- * 5. Make sure esp_task.h is consistent between wifi lib and idf
- */
-
-#ifndef _ESP_TASK_H_
-#define _ESP_TASK_H_
-
-#include "sdkconfig.h"
-#include "freertos/FreeRTOSConfig.h"
-
-#define ESP_TASK_PRIO_MAX (configMAX_PRIORITIES)
-#define ESP_TASK_PRIO_MIN (0)
-
-/* Bt contoller Task */
-/* controller */
-#define ESP_TASK_BT_CONTROLLER_PRIO   (ESP_TASK_PRIO_MAX - 2)
-#ifdef CONFIG_NEWLIB_NANO_FORMAT
-#define TASK_EXTRA_STACK_SIZE      (0)
-#else
-#define TASK_EXTRA_STACK_SIZE      (512)
-#endif
-
-#define BT_TASK_EXTRA_STACK_SIZE      TASK_EXTRA_STACK_SIZE
-#define ESP_TASK_BT_CONTROLLER_STACK  (3584 + TASK_EXTRA_STACK_SIZE)
-
-
-/* idf task */
-#define ESP_TASK_TIMER_PRIO           (ESP_TASK_PRIO_MAX - 3)
-#define ESP_TASK_TIMER_STACK          (CONFIG_TIMER_TASK_STACK_SIZE +  TASK_EXTRA_STACK_SIZE)
-#define ESP_TASKD_EVENT_PRIO          (ESP_TASK_PRIO_MAX - 5)
-#define ESP_TASKD_EVENT_STACK         (CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
-#define ESP_TASK_TCPIP_PRIO           (ESP_TASK_PRIO_MAX - 7)
-#define ESP_TASK_TCPIP_STACK          (CONFIG_TCPIP_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
-#define ESP_TASK_MAIN_PRIO            (ESP_TASK_PRIO_MIN + 1)
-#define ESP_TASK_MAIN_STACK           (CONFIG_MAIN_TASK_STACK_SIZE + TASK_EXTRA_STACK_SIZE)
-
-#endif
diff --git a/tools/sdk/include/esp32/esp_task_wdt.h b/tools/sdk/include/esp32/esp_task_wdt.h
deleted file mode 100644
index 60b0e5e5c9a..00000000000
--- a/tools/sdk/include/esp32/esp_task_wdt.h
+++ /dev/null
@@ -1,163 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  * @brief  Initialize the Task Watchdog Timer (TWDT)
-  *
-  * This function configures and initializes the TWDT. If the TWDT is already
-  * initialized when this function is called, this function will update the
-  * TWDT's timeout period and panic configurations instead. After initializing
-  * the TWDT, any task can elect to be watched by the TWDT by subscribing to it
-  * using esp_task_wdt_add().
-  *
-  * @param[in]  timeout     Timeout period of TWDT in seconds
-  * @param[in]  panic       Flag that controls whether the panic handler will be
-  *                         executed when the TWDT times out
-  *
-  * @return
-  *     - ESP_OK: Initialization was successful
-  *     - ESP_ERR_NO_MEM: Initialization failed due to lack of memory
-  *
-  * @note   esp_task_wdt_init() must only be called after the scheduler
-  *         started
-  */
-esp_err_t esp_task_wdt_init(uint32_t timeout, bool panic);
-
-/**
- * @brief   Deinitialize the Task Watchdog Timer (TWDT)
- *
- * This function will deinitialize the TWDT. Calling this function whilst tasks
- * are still subscribed to the TWDT, or when the TWDT is already deinitialized,
- * will result in an error code being returned.
- *
- * @return
- *      - ESP_OK: TWDT successfully deinitialized
- *      - ESP_ERR_INVALID_STATE: Error, tasks are still subscribed to the TWDT
- *      - ESP_ERR_NOT_FOUND: Error, TWDT has already been deinitialized
- */
-esp_err_t esp_task_wdt_deinit();
-
-/**
-  * @brief  Subscribe a task to the Task Watchdog Timer (TWDT)
-  *
-  * This function subscribes a task to the TWDT. Each subscribed task must
-  * periodically call esp_task_wdt_reset() to prevent the TWDT from elapsing its
-  * timeout period. Failure to do so will result in a TWDT timeout. If the task
-  * being subscribed is one of the Idle Tasks, this function will automatically
-  * enable esp_task_wdt_reset() to called from the Idle Hook of the Idle Task.
-  * Calling this function whilst the TWDT is uninitialized or attempting to
-  * subscribe an already subscribed task will result in an error code being
-  * returned.
-  *
-  * @param[in]  handle  Handle of the task. Input NULL to subscribe the current
-  *                     running task to the TWDT
-  *
-  * @return
-  *     - ESP_OK: Successfully subscribed the task to the TWDT
-  *     - ESP_ERR_INVALID_ARG: Error, the task is already subscribed
-  *     - ESP_ERR_NO_MEM: Error, could not subscribe the task due to lack of
-  *                       memory
-  *     - ESP_ERR_INVALID_STATE: Error, the TWDT has not been initialized yet
-  */
-esp_err_t esp_task_wdt_add(TaskHandle_t handle);
-
-/**
-  * @brief  Reset the Task Watchdog Timer (TWDT) on behalf of the currently
-  *         running task
-  *
-  * This function will reset the TWDT on behalf of the currently running task.
-  * Each subscribed task must periodically call this function to prevent the
-  * TWDT from timing out. If one or more subscribed tasks fail to reset the
-  * TWDT on their own behalf, a TWDT timeout will occur. If the IDLE tasks have
-  * been subscribed to the TWDT, they will automatically call this function from
-  * their idle hooks. Calling this function from a task that has not subscribed
-  * to the TWDT, or when the TWDT is uninitialized will result in an error code
-  * being returned.
-  *
-  * @return
-  *     - ESP_OK: Successfully reset the TWDT on behalf of the currently
-  *               running task
-  *     - ESP_ERR_NOT_FOUND: Error, the current running task has not subscribed
-  *                          to the TWDT
-  *     - ESP_ERR_INVALID_STATE: Error, the TWDT has not been initialized yet
-  */
-esp_err_t esp_task_wdt_reset();
-
-/**
-  * @brief  Unsubscribes a task from the Task Watchdog Timer (TWDT)
-  *
-  * This function will unsubscribe a task from the TWDT. After being
-  * unsubscribed, the task should no longer call esp_task_wdt_reset(). If the
-  * task is an IDLE task, this function will automatically disable the calling
-  * of esp_task_wdt_reset() from the Idle Hook. Calling this function whilst the
-  * TWDT is uninitialized or attempting to unsubscribe an already unsubscribed
-  * task from the TWDT will result in an error code being returned.
-  *
-  * @param[in]  handle  Handle of the task. Input NULL to unsubscribe the
-  *                     current running task.
-  *
-  * @return
-  *     - ESP_OK: Successfully unsubscribed the task from the TWDT
-  *     - ESP_ERR_INVALID_ARG: Error, the task is already unsubscribed
-  *     - ESP_ERR_INVALID_STATE: Error, the TWDT has not been initialized yet
-  */
-esp_err_t esp_task_wdt_delete(TaskHandle_t handle);
-
-/**
-  * @brief   Query whether a task is subscribed to the Task Watchdog Timer (TWDT)
-  *
-  * This function will query whether a task is currently subscribed to the TWDT,
-  * or whether the TWDT is initialized.
-  *
-  * @param[in]  handle  Handle of the task. Input NULL to query the current
-  *                     running task.
-  *
-  * @return:
-  *     - ESP_OK: The task is currently subscribed to the TWDT
-  *     - ESP_ERR_NOT_FOUND: The task is currently not subscribed to the TWDT
-  *     - ESP_ERR_INVALID_STATE: The TWDT is not initialized, therefore no tasks
-  *                              can be subscribed
-  */
-esp_err_t esp_task_wdt_status(TaskHandle_t handle);
-
-/**
-  * @brief      Reset the TWDT on behalf of the current running task, or
-  *             subscribe the TWDT to if it has not done so already
-  *
-  * @warning    This function is deprecated, use esp_task_wdt_add() and
-  *             esp_task_wdt_reset() instead
-  *
-  * This function is similar to esp_task_wdt_reset() and will reset the TWDT on
-  * behalf of the current running task. However if this task has not subscribed
-  * to the TWDT, this function will automatically subscribe the task. Therefore,
-  * an unsubscribed task will subscribe to the TWDT on its first call to this
-  * function, then proceed to reset the TWDT on subsequent calls of this
-  * function.
-  */
-void esp_task_wdt_feed() __attribute__ ((deprecated));
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp32/esp_timer.h b/tools/sdk/include/esp32/esp_timer.h
deleted file mode 100644
index ff5c13ab4c1..00000000000
--- a/tools/sdk/include/esp32/esp_timer.h
+++ /dev/null
@@ -1,233 +0,0 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/**
- * @file esp_timer.h
- * @brief microsecond-precision 64-bit timer API, replacement for ets_timer
- *
- * esp_timer APIs allow components to receive callbacks when a hardware timer
- * reaches certain value. The timer provides microsecond accuracy and
- * up to 64 bit range. Note that while the timer itself provides microsecond
- * accuracy, callbacks are dispatched from an auxiliary task. Some time is
- * needed to notify this task from timer ISR, and then to invoke the callback.
- * If more than one callback needs to be dispatched at any particular time,
- * each subsequent callback will be dispatched only when the previous callback
- * returns. Therefore, callbacks should not do much work; instead, they should
- * use RTOS notification mechanisms (queues, semaphores, event groups, etc.) to
- * pass information to other tasks.
- *
- * To be implemented: it should be possible to request the callback to be called
- * directly from the ISR. This reduces the latency, but has potential impact on
- * all other callbacks which need to be dispatched. This option should only be
- * used for simple callback functions, which do not take longer than a few
- * microseconds to run.
- *
- * Implementation note: on the ESP32, esp_timer APIs use the "legacy" FRC2
- * timer. Timer callbacks are called from a task running on the PRO CPU.
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Opaque type representing a single esp_timer
- */
-typedef struct esp_timer* esp_timer_handle_t;
-
-/**
- * @brief Timer callback function type
- * @param arg pointer to opaque user-specific data
- */
-typedef void (*esp_timer_cb_t)(void* arg);
-
-
-/**
- * @brief Method for dispatching timer callback
- */
-typedef enum {
-    ESP_TIMER_TASK,     //!< Callback is called from timer task
-
-    /* Not supported for now, provision to allow callbacks to run directly
-     * from an ISR:
-
-        ESP_TIMER_ISR,      //!< Callback is called from timer ISR
-
-     */
-} esp_timer_dispatch_t;
-
-/**
- * @brief Timer configuration passed to esp_timer_create
- */
-typedef struct {
-    esp_timer_cb_t callback;        //!< Function to call when timer expires
-    void* arg;                      //!< Argument to pass to the callback
-    esp_timer_dispatch_t dispatch_method;   //!< Call the callback from task or from ISR
-    const char* name;               //!< Timer name, used in esp_timer_dump function
-} esp_timer_create_args_t;
-
-/**
- * @brief Initialize esp_timer library
- *
- * @note This function is called from startup code. Applications do not need
- * to call this function before using other esp_timer APIs.
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NO_MEM if allocation has failed
- *      - ESP_ERR_INVALID_STATE if already initialized
- *      - other errors from interrupt allocator
- */
-esp_err_t esp_timer_init();
-
-/**
- * @brief De-initialize esp_timer library
- *
- * @note Normally this function should not be called from applications
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if not yet initialized
- */
-esp_err_t esp_timer_deinit();
-
-/**
- * @brief Create an esp_timer instance
- *
- * @note When done using the timer, delete it with esp_timer_delete function.
- *
- * @param create_args   Pointer to a structure with timer creation arguments.
- *                      Not saved by the library, can be allocated on the stack.
- * @param[out] out_handle  Output, pointer to esp_timer_handle_t variable which
- *                         will hold the created timer handle.
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if some of the create_args are not valid
- *      - ESP_ERR_INVALID_STATE if esp_timer library is not initialized yet
- *      - ESP_ERR_NO_MEM if memory allocation fails
- */
-esp_err_t esp_timer_create(const esp_timer_create_args_t* create_args,
-                           esp_timer_handle_t* out_handle);
-
-/**
- * @brief Start one-shot timer
- *
- * Timer should not be running when this function is called.
- *
- * @param timer timer handle created using esp_timer_create
- * @param timeout_us timer timeout, in microseconds relative to the current moment
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if the handle is invalid
- *      - ESP_ERR_INVALID_STATE if the timer is already running
- */
-esp_err_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us);
-
-/**
- * @brief Start a periodic timer
- *
- * Timer should not be running when this function is called. This function will
- * start the timer which will trigger every 'period' microseconds.
- *
- * @param timer timer handle created using esp_timer_create
- * @param period timer period, in microseconds
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if the handle is invalid
- *      - ESP_ERR_INVALID_STATE if the timer is already running
- */
-esp_err_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period);
-
-/**
- * @brief Stop the timer
- *
- * This function stops the timer previously started using esp_timer_start_once
- * or esp_timer_start_periodic.
- *
- * @param timer timer handle created using esp_timer_create
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if the timer is not running
- */
-esp_err_t esp_timer_stop(esp_timer_handle_t timer);
-
-/**
- * @brief Delete an esp_timer instance
- *
- * The timer must be stopped before deleting. A one-shot timer which has expired
- * does not need to be stopped.
- *
- * @param timer timer handle allocated using esp_timer_create
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if the timer is not running
- */
-esp_err_t esp_timer_delete(esp_timer_handle_t timer);
-
-/**
- * @brief Get time in microseconds since boot
- * @return number of microseconds since esp_timer_init was called (this normally
- *          happens early during application startup).
- */
-int64_t esp_timer_get_time();
-
-/**
- * @brief Get the timestamp when the next timeout is expected to occur
- * @return Timestamp of the nearest timer event, in microseconds.
- *         The timebase is the same as for the values returned by esp_timer_get_time.
- */
-int64_t esp_timer_get_next_alarm();
-
-/**
- * @brief Dump the list of timers to a stream
- *
- * If CONFIG_ESP_TIMER_PROFILING option is enabled, this prints the list of all
- * the existing timers. Otherwise, only the list active timers is printed.
- *
- * The format is:
- *
- *   name  period  alarm  times_armed  times_triggered  total_callback_run_time
- *
- * where:
- *
- * name — timer name (if CONFIG_ESP_TIMER_PROFILING is defined), or timer pointer
- * period — period of timer, in microseconds, or 0 for one-shot timer
- * alarm - time of the next alarm, in microseconds since boot, or 0 if the timer
- *         is not started
- *
- * The following fields are printed if CONFIG_ESP_TIMER_PROFILING is defined:
- *
- * times_armed — number of times the timer was armed via esp_timer_start_X
- * times_triggered - number of times the callback was called
- * total_callback_run_time - total time taken by callback to execute, across all calls
- *
- * @param stream stream (such as stdout) to dump the information to
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NO_MEM if can not allocate temporary buffer for the output
- */
-esp_err_t esp_timer_dump(FILE* stream);
-
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/tools/sdk/include/esp32/esp_types.h b/tools/sdk/include/esp32/esp_types.h
deleted file mode 100644
index 547024e3f75..00000000000
--- a/tools/sdk/include/esp32/esp_types.h
+++ /dev/null
@@ -1,25 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_TYPES_H__
-#define __ESP_TYPES_H__
-
-#ifdef __GNUC__
-#include <sys/cdefs.h>
-#endif /*__GNUC__*/
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-
-#endif /* __ESP_TYPES_H__ */
diff --git a/tools/sdk/include/esp32/esp_wifi.h b/tools/sdk/include/esp32/esp_wifi.h
deleted file mode 100644
index f920c57bce9..00000000000
--- a/tools/sdk/include/esp32/esp_wifi.h
+++ /dev/null
@@ -1,1151 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-/*               Notes about WiFi Programming
- *
- *  The esp32 WiFi programming model can be depicted as following picture:
- *
- *
- *                            default handler              user handler
- *  -------------             ---------------             ---------------
- *  |           |   event     |             | callback or |             |
- *  |   tcpip   | --------->  |    event    | ----------> | application |
- *  |   stack   |             |     task    |  event      |    task     |
- *  |-----------|             |-------------|             |-------------|
- *                                  /|\                          |
- *                                   |                           |
- *                            event  |                           |
- *                                   |                           |
- *                                   |                           |
- *                             ---------------                   |
- *                             |             |                   |
- *                             | WiFi Driver |/__________________|
- *                             |             |\     API call
- *                             |             |
- *                             |-------------|
- *
- * The WiFi driver can be consider as black box, it knows nothing about the high layer code, such as
- * TCPIP stack, application task, event task etc, all it can do is to receive API call from high layer
- * or post event queue to a specified Queue, which is initialized by API esp_wifi_init().
- *
- * The event task is a daemon task, which receives events from WiFi driver or from other subsystem, such
- * as TCPIP stack, event task will call the default callback function on receiving the event. For example,
- * on receiving event SYSTEM_EVENT_STA_CONNECTED, it will call tcpip_adapter_start() to start the DHCP
- * client in it's default handler.
- *
- * Application can register it's own event callback function by API esp_event_init, then the application callback
- * function will be called after the default callback. Also, if application doesn't want to execute the callback
- * in the event task, what it needs to do is to post the related event to application task in the application callback function.
- *
- * The application task (code) generally mixes all these thing together, it calls APIs to init the system/WiFi and
- * handle the events when necessary.
- *
- */
-
-#ifndef __ESP_WIFI_H__
-#define __ESP_WIFI_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-#include "esp_wifi_types.h"
-#include "esp_event.h"
-#include "esp_private/esp_wifi_private.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ESP_ERR_WIFI_NOT_INIT    (ESP_ERR_WIFI_BASE + 1)   /*!< WiFi driver was not installed by esp_wifi_init */
-#define ESP_ERR_WIFI_NOT_STARTED (ESP_ERR_WIFI_BASE + 2)   /*!< WiFi driver was not started by esp_wifi_start */
-#define ESP_ERR_WIFI_NOT_STOPPED (ESP_ERR_WIFI_BASE + 3)   /*!< WiFi driver was not stopped by esp_wifi_stop */
-#define ESP_ERR_WIFI_IF          (ESP_ERR_WIFI_BASE + 4)   /*!< WiFi interface error */
-#define ESP_ERR_WIFI_MODE        (ESP_ERR_WIFI_BASE + 5)   /*!< WiFi mode error */
-#define ESP_ERR_WIFI_STATE       (ESP_ERR_WIFI_BASE + 6)   /*!< WiFi internal state error */
-#define ESP_ERR_WIFI_CONN        (ESP_ERR_WIFI_BASE + 7)   /*!< WiFi internal control block of station or soft-AP error */
-#define ESP_ERR_WIFI_NVS         (ESP_ERR_WIFI_BASE + 8)   /*!< WiFi internal NVS module error */
-#define ESP_ERR_WIFI_MAC         (ESP_ERR_WIFI_BASE + 9)   /*!< MAC address is invalid */
-#define ESP_ERR_WIFI_SSID        (ESP_ERR_WIFI_BASE + 10)   /*!< SSID is invalid */
-#define ESP_ERR_WIFI_PASSWORD    (ESP_ERR_WIFI_BASE + 11)  /*!< Password is invalid */
-#define ESP_ERR_WIFI_TIMEOUT     (ESP_ERR_WIFI_BASE + 12)  /*!< Timeout error */
-#define ESP_ERR_WIFI_WAKE_FAIL   (ESP_ERR_WIFI_BASE + 13)  /*!< WiFi is in sleep state(RF closed) and wakeup fail */
-#define ESP_ERR_WIFI_WOULD_BLOCK (ESP_ERR_WIFI_BASE + 14)  /*!< The caller would block */
-#define ESP_ERR_WIFI_NOT_CONNECT (ESP_ERR_WIFI_BASE + 15)  /*!< Station still in disconnect status */
-
-#define ESP_ERR_WIFI_POST        (ESP_ERR_WIFI_BASE + 18)  /*!< Failed to post the event to WiFi task */
-#define ESP_ERR_WIFI_INIT_STATE  (ESP_ERR_WIFI_BASE + 19)  /*!< Invalod WiFi state when init/deinit is called */
-#define ESP_ERR_WIFI_STOP_STATE  (ESP_ERR_WIFI_BASE + 20)  /*!< Returned when WiFi is stopping */
-
-/**
- * @brief WiFi stack configuration parameters passed to esp_wifi_init call.
- */
-typedef struct {
-    system_event_handler_t event_handler;          /**< WiFi event handler */
-    wifi_osi_funcs_t*      osi_funcs;              /**< WiFi OS functions */
-    wpa_crypto_funcs_t     wpa_crypto_funcs;       /**< WiFi station crypto functions when connect */
-    int                    static_rx_buf_num;      /**< WiFi static RX buffer number */
-    int                    dynamic_rx_buf_num;     /**< WiFi dynamic RX buffer number */
-    int                    tx_buf_type;            /**< WiFi TX buffer type */
-    int                    static_tx_buf_num;      /**< WiFi static TX buffer number */
-    int                    dynamic_tx_buf_num;     /**< WiFi dynamic TX buffer number */
-    int                    csi_enable;             /**< WiFi channel state information enable flag */
-    int                    ampdu_rx_enable;        /**< WiFi AMPDU RX feature enable flag */
-    int                    ampdu_tx_enable;        /**< WiFi AMPDU TX feature enable flag */
-    int                    nvs_enable;             /**< WiFi NVS flash enable flag */
-    int                    nano_enable;            /**< Nano option for printf/scan family enable flag */
-    int                    tx_ba_win;              /**< WiFi Block Ack TX window size */
-    int                    rx_ba_win;              /**< WiFi Block Ack RX window size */
-    int                    wifi_task_core_id;      /**< WiFi Task Core ID */
-    int                    beacon_max_len;         /**< WiFi softAP maximum length of the beacon */
-    int                    mgmt_sbuf_num;          /**< WiFi management short buffer number, the minimum value is 6, the maximum value is 32 */
-    int                    magic;                  /**< WiFi init magic number, it should be the last field */
-} wifi_init_config_t;
-
-#ifdef CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM
-#define WIFI_STATIC_TX_BUFFER_NUM CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM
-#else
-#define WIFI_STATIC_TX_BUFFER_NUM 0
-#endif
-
-#ifdef CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM
-#define WIFI_DYNAMIC_TX_BUFFER_NUM CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM
-#else
-#define WIFI_DYNAMIC_TX_BUFFER_NUM 0
-#endif
-
-#if CONFIG_ESP32_WIFI_CSI_ENABLED
-#define WIFI_CSI_ENABLED         1
-#else
-#define WIFI_CSI_ENABLED         0
-#endif
-
-#if CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED
-#define WIFI_AMPDU_RX_ENABLED        1
-#else
-#define WIFI_AMPDU_RX_ENABLED        0
-#endif
-
-#if CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED
-#define WIFI_AMPDU_TX_ENABLED        1
-#else
-#define WIFI_AMPDU_TX_ENABLED        0
-#endif
-
-#if CONFIG_ESP32_WIFI_NVS_ENABLED
-#define WIFI_NVS_ENABLED          1
-#else
-#define WIFI_NVS_ENABLED          0
-#endif
-
-#if CONFIG_NEWLIB_NANO_FORMAT
-#define WIFI_NANO_FORMAT_ENABLED  1
-#else
-#define WIFI_NANO_FORMAT_ENABLED  0
-#endif
-
-extern const wpa_crypto_funcs_t g_wifi_default_wpa_crypto_funcs;
-
-#define WIFI_INIT_CONFIG_MAGIC    0x1F2F3F4F
-
-#ifdef CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED
-#define WIFI_DEFAULT_TX_BA_WIN CONFIG_ESP32_WIFI_TX_BA_WIN
-#else
-#define WIFI_DEFAULT_TX_BA_WIN 0 /* unused if ampdu_tx_enable == false */
-#endif
-
-#ifdef CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED
-#define WIFI_DEFAULT_RX_BA_WIN CONFIG_ESP32_WIFI_RX_BA_WIN
-#else
-#define WIFI_DEFAULT_RX_BA_WIN 0 /* unused if ampdu_rx_enable == false */
-#endif
-
-#if CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1
-#define WIFI_TASK_CORE_ID 1
-#else
-#define WIFI_TASK_CORE_ID 0
-#endif
-
-#ifdef CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN
-#define WIFI_SOFTAP_BEACON_MAX_LEN CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN
-#else
-#define WIFI_SOFTAP_BEACON_MAX_LEN 752
-#endif
-
-#ifdef CONFIG_ESP32_WIFI_MGMT_SBUF_NUM
-#define WIFI_MGMT_SBUF_NUM CONFIG_ESP32_WIFI_MGMT_SBUF_NUM
-#else
-#define WIFI_MGMT_SBUF_NUM 32
-#endif
-
-#define WIFI_INIT_CONFIG_DEFAULT() { \
-    .event_handler = &esp_event_send, \
-    .osi_funcs = &g_wifi_osi_funcs, \
-    .wpa_crypto_funcs = g_wifi_default_wpa_crypto_funcs, \
-    .static_rx_buf_num = CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM,\
-    .dynamic_rx_buf_num = CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM,\
-    .tx_buf_type = CONFIG_ESP32_WIFI_TX_BUFFER_TYPE,\
-    .static_tx_buf_num = WIFI_STATIC_TX_BUFFER_NUM,\
-    .dynamic_tx_buf_num = WIFI_DYNAMIC_TX_BUFFER_NUM,\
-    .csi_enable = WIFI_CSI_ENABLED,\
-    .ampdu_rx_enable = WIFI_AMPDU_RX_ENABLED,\
-    .ampdu_tx_enable = WIFI_AMPDU_TX_ENABLED,\
-    .nvs_enable = WIFI_NVS_ENABLED,\
-    .nano_enable = WIFI_NANO_FORMAT_ENABLED,\
-    .tx_ba_win = WIFI_DEFAULT_TX_BA_WIN,\
-    .rx_ba_win = WIFI_DEFAULT_RX_BA_WIN,\
-    .wifi_task_core_id = WIFI_TASK_CORE_ID,\
-    .beacon_max_len = WIFI_SOFTAP_BEACON_MAX_LEN, \
-    .mgmt_sbuf_num = WIFI_MGMT_SBUF_NUM, \
-    .magic = WIFI_INIT_CONFIG_MAGIC\
-};
-
-/**
-  * @brief  Init WiFi
-  *         Alloc resource for WiFi driver, such as WiFi control structure, RX/TX buffer,
-  *         WiFi NVS structure etc, this WiFi also start WiFi task
-  *
-  * @attention 1. This API must be called before all other WiFi API can be called
-  * @attention 2. Always use WIFI_INIT_CONFIG_DEFAULT macro to init the config to default values, this can
-  *               guarantee all the fields got correct value when more fields are added into wifi_init_config_t
-  *               in future release. If you want to set your owner initial values, overwrite the default values
-  *               which are set by WIFI_INIT_CONFIG_DEFAULT, please be notified that the field 'magic' of 
-  *               wifi_init_config_t should always be WIFI_INIT_CONFIG_MAGIC!
-  *
-  * @param  config pointer to WiFi init configuration structure; can point to a temporary variable.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_NO_MEM: out of memory
-  *    - others: refer to error code esp_err.h
-  */
-esp_err_t esp_wifi_init(const wifi_init_config_t *config);
-
-/**
-  * @brief  Deinit WiFi
-  *         Free all resource allocated in esp_wifi_init and stop WiFi task
-  *
-  * @attention 1. This API should be called if you want to remove WiFi driver from the system
-  *
-  * @return 
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  */
-esp_err_t esp_wifi_deinit(void);
-
-/**
-  * @brief     Set the WiFi operating mode
-  *
-  *            Set the WiFi operating mode as station, soft-AP or station+soft-AP,
-  *            The default mode is soft-AP mode.
-  *
-  * @param     mode  WiFi operating mode
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - others: refer to error code in esp_err.h
-  */
-esp_err_t esp_wifi_set_mode(wifi_mode_t mode);
-
-/**
-  * @brief  Get current operating mode of WiFi
-  *
-  * @param[out]  mode  store current WiFi mode
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_mode(wifi_mode_t *mode);
-
-/**
-  * @brief  Start WiFi according to current configuration
-  *         If mode is WIFI_MODE_STA, it create station control block and start station
-  *         If mode is WIFI_MODE_AP, it create soft-AP control block and start soft-AP
-  *         If mode is WIFI_MODE_APSTA, it create soft-AP and station control block and start soft-AP and station
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - ESP_ERR_NO_MEM: out of memory
-  *    - ESP_ERR_WIFI_CONN: WiFi internal error, station or soft-AP control block wrong
-  *    - ESP_FAIL: other WiFi internal errors
-  */
-esp_err_t esp_wifi_start(void);
-
-/**
-  * @brief  Stop WiFi
-  *         If mode is WIFI_MODE_STA, it stop station and free station control block
-  *         If mode is WIFI_MODE_AP, it stop soft-AP and free soft-AP control block
-  *         If mode is WIFI_MODE_APSTA, it stop station/soft-AP and free station/soft-AP control block
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  */
-esp_err_t esp_wifi_stop(void);
-
-/**
- * @brief  Restore WiFi stack persistent settings to default values
- *
- * This function will reset settings made using the following APIs:
- * - esp_wifi_get_auto_connect,
- * - esp_wifi_set_protocol,
- * - esp_wifi_set_config related
- * - esp_wifi_set_mode
- *
- * @return
- *    - ESP_OK: succeed
- *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
- */
-esp_err_t esp_wifi_restore(void);
-
-/**
-  * @brief     Connect the ESP32 WiFi station to the AP.
-  *
-  * @attention 1. This API only impact WIFI_MODE_STA or WIFI_MODE_APSTA mode
-  * @attention 2. If the ESP32 is connected to an AP, call esp_wifi_disconnect to disconnect.
-  * @attention 3. The scanning triggered by esp_wifi_start_scan() will not be effective until connection between ESP32 and the AP is established.
-  *               If ESP32 is scanning and connecting at the same time, ESP32 will abort scanning and return a warning message and error
-  *               number ESP_ERR_WIFI_STATE.
-  *               If you want to do reconnection after ESP32 received disconnect event, remember to add the maximum retry time, otherwise the called	
-  *               scan will not work. This is especially true when the AP doesn't exist, and you still try reconnection after ESP32 received disconnect
-  *               event with the reason code WIFI_REASON_NO_AP_FOUND.
-  *   
-  * @return 
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
-  *    - ESP_ERR_WIFI_CONN: WiFi internal error, station or soft-AP control block wrong
-  *    - ESP_ERR_WIFI_SSID: SSID of AP which station connects is invalid
-  */
-esp_err_t esp_wifi_connect(void);
-
-/**
-  * @brief     Disconnect the ESP32 WiFi station from the AP.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi was not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
-  *    - ESP_FAIL: other WiFi internal errors
-  */
-esp_err_t esp_wifi_disconnect(void);
-
-/**
-  * @brief     Currently this API is just an stub API
-  *
-
-  * @return
-  *    - ESP_OK: succeed
-  *    - others: fail
-  */
-esp_err_t esp_wifi_clear_fast_connect(void);
-
-/**
-  * @brief     deauthenticate all stations or associated id equals to aid
-  *
-  * @param     aid  when aid is 0, deauthenticate all stations, otherwise deauthenticate station whose associated id is aid
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - ESP_ERR_WIFI_MODE: WiFi mode is wrong
-  */
-esp_err_t esp_wifi_deauth_sta(uint16_t aid);
-
-/**
-  * @brief     Scan all available APs.
-  *
-  * @attention If this API is called, the found APs are stored in WiFi driver dynamic allocated memory and the
-  *            will be freed in esp_wifi_scan_get_ap_records, so generally, call esp_wifi_scan_get_ap_records to cause
-  *            the memory to be freed once the scan is done
-  * @attention The values of maximum active scan time and passive scan time per channel are limited to 1500 milliseconds.
-  *            Values above 1500ms may cause station to disconnect from AP and are not recommended.
-  *
-  * @param     config  configuration of scanning
-  * @param     block if block is true, this API will block the caller until the scan is done, otherwise
-  *                         it will return immediately
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
-  *    - ESP_ERR_WIFI_TIMEOUT: blocking scan is timeout
-  *    - ESP_ERR_WIFI_STATE: wifi still connecting when invoke esp_wifi_scan_start
-  *    - others: refer to error code in esp_err.h
-  */
-esp_err_t esp_wifi_scan_start(const wifi_scan_config_t *config, bool block);
-
-/**
-  * @brief     Stop the scan in process
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
-  */
-esp_err_t esp_wifi_scan_stop(void);
-
-/**
-  * @brief     Get number of APs found in last scan
-  *
-  * @param[out] number  store number of APIs found in last scan
-  *
-  * @attention This API can only be called when the scan is completed, otherwise it may get wrong value.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_scan_get_ap_num(uint16_t *number);
-
-/**
-  * @brief     Get AP list found in last scan
-  *
-  * @param[inout]  number As input param, it stores max AP number ap_records can hold. 
-  *                As output param, it receives the actual AP number this API returns.
-  * @param         ap_records  wifi_ap_record_t array to hold the found APs
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - ESP_ERR_NO_MEM: out of memory
-  */
-esp_err_t esp_wifi_scan_get_ap_records(uint16_t *number, wifi_ap_record_t *ap_records);
-
-
-/**
-  * @brief     Get information of AP which the ESP32 station is associated with
-  *
-  * @param     ap_info  the wifi_ap_record_t to hold AP information
-  *            sta can get the connected ap's phy mode info through the struct member
-  *            phy_11b，phy_11g，phy_11n，phy_lr in the wifi_ap_record_t struct.
-  *            For example, phy_11b = 1 imply that ap support 802.11b mode
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_CONN: The station interface don't initialized
-  *    - ESP_ERR_WIFI_NOT_CONNECT: The station is in disconnect status 
-  */
-esp_err_t esp_wifi_sta_get_ap_info(wifi_ap_record_t *ap_info);
-
-/**
-  * @brief     Set current WiFi power save type
-  *
-  * @attention Default power save type is WIFI_PS_MIN_MODEM.
-  *
-  * @param     type  power save type
-  *
-  * @return    ESP_OK: succeed
-  */
-esp_err_t esp_wifi_set_ps(wifi_ps_type_t type);
-
-/**
-  * @brief     Get current WiFi power save type
-  *
-  * @attention Default power save type is WIFI_PS_MIN_MODEM.
-  *
-  * @param[out]  type: store current power save type
-  *
-  * @return    ESP_OK: succeed
-  */
-esp_err_t esp_wifi_get_ps(wifi_ps_type_t *type);
-
-/**
-  * @brief     Set protocol type of specified interface
-  *            The default protocol is (WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N)
-  *
-  * @attention Currently we only support 802.11b or 802.11bg or 802.11bgn mode
-  *
-  * @param     ifx  interfaces
-  * @param     protocol_bitmap  WiFi protocol bitmap
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_IF: invalid interface
-  *    - others: refer to error codes in esp_err.h
-  */
-esp_err_t esp_wifi_set_protocol(wifi_interface_t ifx, uint8_t protocol_bitmap);
-
-/**
-  * @brief     Get the current protocol bitmap of the specified interface
-  *
-  * @param     ifx  interface
-  * @param[out] protocol_bitmap  store current WiFi protocol bitmap of interface ifx
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_IF: invalid interface
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - others: refer to error codes in esp_err.h
-  */
-esp_err_t esp_wifi_get_protocol(wifi_interface_t ifx, uint8_t *protocol_bitmap);
-
-/**
-  * @brief     Set the bandwidth of ESP32 specified interface
-  *
-  * @attention 1. API return false if try to configure an interface that is not enabled
-  * @attention 2. WIFI_BW_HT40 is supported only when the interface support 11N
-  *
-  * @param     ifx  interface to be configured
-  * @param     bw  bandwidth
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_IF: invalid interface
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - others: refer to error codes in esp_err.h
-  */
-esp_err_t esp_wifi_set_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t bw);
-
-/**
-  * @brief     Get the bandwidth of ESP32 specified interface
-  *
-  * @attention 1. API return false if try to get a interface that is not enable
-  *
-  * @param     ifx interface to be configured
-  * @param[out] bw  store bandwidth of interface ifx
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_IF: invalid interface
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t *bw);
-
-/**
-  * @brief     Set primary/secondary channel of ESP32
-  *
-  * @attention 1. This API should be called after esp_wifi_start()
-  * @attention 2. When ESP32 is in STA mode, this API should not be called when STA is scanning or connecting to an external AP
-  * @attention 3. When ESP32 is in softAP mode, this API should not be called when softAP has connected to external STAs
-  * @attention 4. When ESP32 is in STA+softAP mode, this API should not be called when in the scenarios described above  
-  *
-  * @param     primary  for HT20, primary is the channel number, for HT40, primary is the primary channel
-  * @param     second   for HT20, second is ignored, for HT40, second is the second channel
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_IF: invalid interface
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_set_channel(uint8_t primary, wifi_second_chan_t second);
-
-/**
-  * @brief     Get the primary/secondary channel of ESP32
-  *
-  * @attention 1. API return false if try to get a interface that is not enable
-  *
-  * @param     primary   store current primary channel
-  * @param[out]  second  store current second channel
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_channel(uint8_t *primary, wifi_second_chan_t *second);
-
-/**
-  * @brief     configure country info
-  *
-  * @attention 1. The default country is {.cc="CN", .schan=1, .nchan=13, policy=WIFI_COUNTRY_POLICY_AUTO}
-  * @attention 2. When the country policy is WIFI_COUNTRY_POLICY_AUTO, the country info of the AP to which
-  *               the station is connected is used. E.g. if the configured country info is {.cc="USA", .schan=1, .nchan=11}
-  *               and the country info of the AP to which the station is connected is {.cc="JP", .schan=1, .nchan=14}
-  *               then the country info that will be used is {.cc="JP", .schan=1, .nchan=14}. If the station disconnected
-  *               from the AP the country info is set back back to the country info of the station automatically,
-  *               {.cc="US", .schan=1, .nchan=11} in the example.
-  * @attention 3. When the country policy is WIFI_COUNTRY_POLICY_MANUAL, always use the configured country info.
-  * @attention 4. When the country info is changed because of configuration or because the station connects to a different
-  *               external AP, the country IE in probe response/beacon of the soft-AP is changed also.
-  * @attention 5. The country configuration is not stored into flash
-  * @attention 6. This API doesn't validate the per-country rules, it's up to the user to fill in all fields according to 
-  *               local regulations.
-  *
-  * @param     country   the configured country info
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_set_country(const wifi_country_t *country);
-
-/**
-  * @brief     get the current country info
-  *
-  * @param     country  country info
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_country(wifi_country_t *country);
-
-
-/**
-  * @brief     Set MAC address of the ESP32 WiFi station or the soft-AP interface.
-  *
-  * @attention 1. This API can only be called when the interface is disabled
-  * @attention 2. ESP32 soft-AP and station have different MAC addresses, do not set them to be the same.
-  * @attention 3. The bit 0 of the first byte of ESP32 MAC address can not be 1. For example, the MAC address
-  *      can set to be "1a:XX:XX:XX:XX:XX", but can not be "15:XX:XX:XX:XX:XX".
-  *
-  * @param     ifx  interface
-  * @param     mac  the MAC address
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - ESP_ERR_WIFI_IF: invalid interface
-  *    - ESP_ERR_WIFI_MAC: invalid mac address
-  *    - ESP_ERR_WIFI_MODE: WiFi mode is wrong
-  *    - others: refer to error codes in esp_err.h
-  */
-esp_err_t esp_wifi_set_mac(wifi_interface_t ifx, const uint8_t mac[6]);
-
-/**
-  * @brief     Get mac of specified interface
-  *
-  * @param      ifx  interface
-  * @param[out] mac  store mac of the interface ifx
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - ESP_ERR_WIFI_IF: invalid interface
-  */
-esp_err_t esp_wifi_get_mac(wifi_interface_t ifx, uint8_t mac[6]);
-
-/**
-  * @brief The RX callback function in the promiscuous mode. 
-  *        Each time a packet is received, the callback function will be called.
-  *
-  * @param buf  Data received. Type of data in buffer (wifi_promiscuous_pkt_t or wifi_pkt_rx_ctrl_t) indicated by 'type' parameter.
-  * @param type  promiscuous packet type.
-  *
-  */
-typedef void (* wifi_promiscuous_cb_t)(void *buf, wifi_promiscuous_pkt_type_t type);
-
-/**
-  * @brief Register the RX callback function in the promiscuous mode.
-  *
-  * Each time a packet is received, the registered callback function will be called.
-  *
-  * @param cb  callback
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  */
-esp_err_t esp_wifi_set_promiscuous_rx_cb(wifi_promiscuous_cb_t cb);
-
-/**
-  * @brief     Enable the promiscuous mode.
-  *
-  * @param     en  false - disable, true - enable
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  */
-esp_err_t esp_wifi_set_promiscuous(bool en);
-
-/**
-  * @brief     Get the promiscuous mode.
-  *
-  * @param[out] en  store the current status of promiscuous mode
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_promiscuous(bool *en);
-
-/**
-  * @brief Enable the promiscuous mode packet type filter.
-  *
-  * @note The default filter is to filter all packets except WIFI_PKT_MISC
-  *
-  * @param filter the packet type filtered in promiscuous mode.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  */
-esp_err_t esp_wifi_set_promiscuous_filter(const wifi_promiscuous_filter_t *filter);
-
-/**
-  * @brief     Get the promiscuous filter.
-  *
-  * @param[out] filter  store the current status of promiscuous filter
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_promiscuous_filter(wifi_promiscuous_filter_t *filter);
-
-/**
-  * @brief Enable subtype filter of the control packet in promiscuous mode.
-  *
-  * @note The default filter is to filter none control packet.
-  *
-  * @param filter the subtype of the control packet filtered in promiscuous mode.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  */
-esp_err_t esp_wifi_set_promiscuous_ctrl_filter(const wifi_promiscuous_filter_t *filter);
-
-/**
-  * @brief     Get the subtype filter of the control packet in promiscuous mode.
-  *
-  * @param[out] filter  store the current status of subtype filter of the control packet in promiscuous mode
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_promiscuous_ctrl_filter(wifi_promiscuous_filter_t *filter);
-
-/**
-  * @brief     Set the configuration of the ESP32 STA or AP
-  *
-  * @attention 1. This API can be called only when specified interface is enabled, otherwise, API fail
-  * @attention 2. For station configuration, bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.
-  * @attention 3. ESP32 is limited to only one channel, so when in the soft-AP+station mode, the soft-AP will adjust its channel automatically to be the same as
-  *               the channel of the ESP32 station.
-  *
-  * @param     interface  interface
-  * @param     conf  station or soft-AP configuration
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - ESP_ERR_WIFI_IF: invalid interface
-  *    - ESP_ERR_WIFI_MODE: invalid mode
-  *    - ESP_ERR_WIFI_PASSWORD: invalid password
-  *    - ESP_ERR_WIFI_NVS: WiFi internal NVS error
-  *    - others: refer to the erro code in esp_err.h
-  */
-esp_err_t esp_wifi_set_config(wifi_interface_t interface, wifi_config_t *conf);
-
-/**
-  * @brief     Get configuration of specified interface
-  *
-  * @param     interface  interface
-  * @param[out]  conf  station or soft-AP configuration
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - ESP_ERR_WIFI_IF: invalid interface
-  */
-esp_err_t esp_wifi_get_config(wifi_interface_t interface, wifi_config_t *conf);
-
-/**
-  * @brief     Get STAs associated with soft-AP
-  *
-  * @attention SSC only API
-  *
-  * @param[out] sta  station list
-  *             ap can get the connected sta's phy mode info through the struct member
-  *             phy_11b，phy_11g，phy_11n，phy_lr in the wifi_sta_info_t struct.
-  *             For example, phy_11b = 1 imply that sta support 802.11b mode
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - ESP_ERR_WIFI_MODE: WiFi mode is wrong
-  *    - ESP_ERR_WIFI_CONN: WiFi internal error, the station/soft-AP control block is invalid
-  */
-esp_err_t esp_wifi_ap_get_sta_list(wifi_sta_list_t *sta);
-
-/**
-  * @brief     Get AID of STA connected with soft-AP
-  *
-  * @param     mac  STA's mac address
-  * @param[out]  aid  Store the AID corresponding to STA mac
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  *    - ESP_ERR_NOT_FOUND: Requested resource not found
-  *    - ESP_ERR_WIFI_MODE: WiFi mode is wrong
-  *    - ESP_ERR_WIFI_CONN: WiFi internal error, the station/soft-AP control block is invalid
-  */
-esp_err_t esp_wifi_ap_get_sta_aid(const uint8_t mac[6], uint16_t *aid);
-
-/**
-  * @brief     Set the WiFi API configuration storage type
-  *
-  * @attention 1. The default value is WIFI_STORAGE_FLASH
-  *
-  * @param     storage : storage type
-  *
-  * @return
-  *   - ESP_OK: succeed
-  *   - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *   - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_set_storage(wifi_storage_t storage);
-
-/**
-  * @brief     Set auto connect
-  *            The default value is true
-  *
-  * @param     en : true - enable auto connect / false - disable auto connect
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_MODE: WiFi internal error, the station/soft-AP control block is invalid
-  *    - others: refer to error code in esp_err.h
-  */
-esp_err_t esp_wifi_set_auto_connect(bool en) __attribute__ ((deprecated));
-
-/**
-  * @brief     Get the auto connect flag
-  *
-  * @param[out] en  store current auto connect configuration
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_auto_connect(bool *en) __attribute__ ((deprecated));
-
-/**
-  * @brief     Function signature for received Vendor-Specific Information Element callback.
-  * @param     ctx Context argument, as passed to esp_wifi_set_vendor_ie_cb() when registering callback.
-  * @param     type Information element type, based on frame type received.
-  * @param     sa Source 802.11 address.
-  * @param     vnd_ie Pointer to the vendor specific element data received.
-  * @param     rssi Received signal strength indication.
-  */
-typedef void (*esp_vendor_ie_cb_t) (void *ctx, wifi_vendor_ie_type_t type, const uint8_t sa[6], const vendor_ie_data_t *vnd_ie, int rssi);
-
-/**
-  * @brief     Set 802.11 Vendor-Specific Information Element
-  *
-  * @param     enable If true, specified IE is enabled. If false, specified IE is removed.
-  * @param     type Information Element type. Determines the frame type to associate with the IE.
-  * @param     idx  Index to set or clear. Each IE type can be associated with up to two elements (indices 0 & 1).
-  * @param     vnd_ie Pointer to vendor specific element data. First 6 bytes should be a header with fields matching vendor_ie_data_t.
-  *            If enable is false, this argument is ignored and can be NULL. Data does not need to remain valid after the function returns.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init()
-  *    - ESP_ERR_INVALID_ARG: Invalid argument, including if first byte of vnd_ie is not WIFI_VENDOR_IE_ELEMENT_ID (0xDD)
-  *      or second byte is an invalid length.
-  *    - ESP_ERR_NO_MEM: Out of memory
-  */
-esp_err_t esp_wifi_set_vendor_ie(bool enable, wifi_vendor_ie_type_t type, wifi_vendor_ie_id_t idx, const void *vnd_ie);
-
-/**
-  * @brief     Register Vendor-Specific Information Element monitoring callback.
-  *
-  * @param     cb   Callback function
-  * @param     ctx  Context argument, passed to callback function.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  */
-esp_err_t esp_wifi_set_vendor_ie_cb(esp_vendor_ie_cb_t cb, void *ctx);
-
-/**
-  * @brief     Set maximum transmitting power after WiFi start.
-  *
-  * @attention 1. Maximum power before wifi startup is limited by PHY init data bin.
-  * @attention 2. The value set by this API will be mapped to the max_tx_power of the structure wifi_country_t variable.
-  * @attention 3. Mapping Table {Power, max_tx_power} = {{8,   2}, {20,  5}, {28,  7}, {34,  8}, {44, 11},
-  *                                                      {52, 13}, {56, 14}, {60, 15}, {66, 16}, {72, 18}, {78, 20}}.
-  * @attention 4. Param power unit is 0.25dBm, range is [8, 78] corresponding to 2dBm - 20dBm.
-  * @attention 5. Relationship between set value and actual value. As follows:
-  *              +------------+--------------+
-  *              | set value  | actual value |
-  *              +============+==============+
-  *              |  [8,  19]  |      8       |
-  *              +------------+--------------+
-  *              |  [20, 27]  |      20      |
-  *              +------------+--------------+
-  *              |  [28, 33]  |      28      |
-  *              +------------+--------------+
-  *              |  [34, 43]  |      34      |
-  *              +------------+--------------+
-  *              |  [44, 51]  |      44      |
-  *              +------------+--------------+
-  *              |  [52, 55]  |      52      |
-  *              +------------+--------------+
-  *              |  [56, 59]  |      56      |
-  *              +------------+--------------+
-  *              |  [60, 65]  |      60      |
-  *              +------------+--------------+
-  *              |  [66, 71]  |      66      |
-  *              +------------+--------------+
-  *              |  [72, 77]  |      72      |
-  *              +------------+--------------+
-  *              |     78     |      78      |
-  *              +------------+--------------+
-  * @param     power  Maximum WiFi transmitting power.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
-  *    - ESP_ERR_WIFI_ARG: invalid argument, e.g. parameter is out of range
-  */
-esp_err_t esp_wifi_set_max_tx_power(int8_t power);
-
-/**
-  * @brief     Get maximum transmiting power after WiFi start
-  *
-  * @param     power Maximum WiFi transmitting power, unit is 0.25dBm.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
-  *    - ESP_ERR_WIFI_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_max_tx_power(int8_t *power);
-
-/**
-  * @brief     Set mask to enable or disable some WiFi events
-  *
-  * @attention 1. Mask can be created by logical OR of various WIFI_EVENT_MASK_ constants.
-  *               Events which have corresponding bit set in the mask will not be delivered to the system event handler.
-  * @attention 2. Default WiFi event mask is WIFI_EVENT_MASK_AP_PROBEREQRECVED.
-  * @attention 3. There may be lots of stations sending probe request data around.
-  *               Don't unmask this event unless you need to receive probe request data.
-  *
-  * @param     mask  WiFi event mask.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  */
-esp_err_t esp_wifi_set_event_mask(uint32_t mask);
-
-/**
-  * @brief     Get mask of WiFi events
-  *
-  * @param     mask  WiFi event mask.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_event_mask(uint32_t *mask);
-
-/**
-  * @brief     Send raw ieee80211 data
-  *
-  * @attention Currently only support for sending beacon/probe request/probe response/action and non-QoS
-  *            data frame
-  * 
-  * @param     ifx interface if the Wi-Fi mode is Station, the ifx should be WIFI_IF_STA. If the Wi-Fi
-  *            mode is SoftAP, the ifx should be WIFI_IF_AP. If the Wi-Fi mode is Station+SoftAP, the 
-  *            ifx should be WIFI_IF_STA or WIFI_IF_AP. If the ifx is wrong, the API returns ESP_ERR_WIFI_IF.
-  * @param     buffer raw ieee80211 buffer
-  * @param     len the length of raw buffer, the len must be <= 1500 Bytes and >= 24 Bytes
-  * @param     en_sys_seq indicate whether use the internal sequence number. If en_sys_seq is false, the 
-  *            sequence in raw buffer is unchanged, otherwise it will be overwritten by WiFi driver with 
-  *            the system sequence number.
-  *            Generally, if esp_wifi_80211_tx is called before the Wi-Fi connection has been set up, both
-  *            en_sys_seq==true and en_sys_seq==false are fine. However, if the API is called after the Wi-Fi
-  *            connection has been set up, en_sys_seq must be true, otherwise ESP_ERR_WIFI_ARG is returned.
-  *
-  * @return
-  *    - ESP_OK: success
-  *    - ESP_ERR_WIFI_IF: Invalid interface
-  *    - ESP_ERR_INVALID_ARG: Invalid parameter
-  *    - ESP_ERR_WIFI_NO_MEM: out of memory
-  */
-
-esp_err_t esp_wifi_80211_tx(wifi_interface_t ifx, const void *buffer, int len, bool en_sys_seq);
-
-/**
-  * @brief The RX callback function of Channel State Information(CSI)  data. 
-  *
-  *        Each time a CSI data is received, the callback function will be called.
-  *
-  * @param ctx context argument, passed to esp_wifi_set_csi_rx_cb() when registering callback function. 
-  * @param data CSI data received. The memory that it points to will be deallocated after callback function returns. 
-  *
-  */
-typedef void (* wifi_csi_cb_t)(void *ctx, wifi_csi_info_t *data);
-
-
-/**
-  * @brief Register the RX callback function of CSI data.
-  *
-  *        Each time a CSI data is received, the callback function will be called.
-  *
-  * @param cb  callback
-  * @param ctx context argument, passed to callback function
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  */
-
-esp_err_t esp_wifi_set_csi_rx_cb(wifi_csi_cb_t cb, void *ctx);
-
-/**
-  * @brief Set CSI data configuration
-  *
-  * @param config configuration
-  * 
-  * return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start or promiscuous mode is not enabled
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_set_csi_config(const wifi_csi_config_t *config);
-
-/**
-  * @brief Enable or disable CSI
-  *
-  * @param en true - enable, false - disable
-  *
-  * return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start or promiscuous mode is not enabled
-  *    - ESP_ERR_INVALID_ARG: invalid argument
-  */
-esp_err_t esp_wifi_set_csi(bool en);
-
-/**
-  * @brief     Set antenna GPIO configuration
-  *
-  * @param     config  Antenna GPIO configuration.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_ARG: Invalid argument, e.g. parameter is NULL, invalid GPIO number etc
-  */
-esp_err_t esp_wifi_set_ant_gpio(const wifi_ant_gpio_config_t *config);
-
-/**
-  * @brief     Get current antenna GPIO configuration
-  *
-  * @param     config  Antenna GPIO configuration.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_ARG: invalid argument, e.g. parameter is NULL
-  */
-esp_err_t esp_wifi_get_ant_gpio(wifi_ant_gpio_config_t *config);
-
-
-/**
-  * @brief     Set antenna configuration
-  *
-  * @param     config  Antenna configuration.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_ARG: Invalid argument, e.g. parameter is NULL, invalid antenna mode or invalid GPIO number
-  */
-esp_err_t esp_wifi_set_ant(const wifi_ant_config_t *config);
-
-/**
-  * @brief     Get current antenna configuration
-  *
-  * @param     config  Antenna configuration.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_ARG: invalid argument, e.g. parameter is NULL
-  */
-esp_err_t esp_wifi_get_ant(wifi_ant_config_t *config);
-
-/**
-  * @brief     Set the inactive time of the ESP32 STA or AP
-  *
-  * @attention 1. For Station, If the station does not receive a beacon frame from the connected SoftAP during the inactive time,
-  *               disconnect from SoftAP. Default 6s.
-  * @attention 2. For SoftAP, If the softAP doesn't receive any data from the connected STA during inactive time,
-  *               the softAP will force deauth the STA. Default is 300s.
-  * @attention 3. The inactive time configuration is not stored into flash
-  *
-  * @param     ifx  interface to be configured.
-  * @param     sec  Inactive time. Unit seconds.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
-  *    - ESP_ERR_WIFI_ARG: invalid argument, For Station, if sec is less than 3. For SoftAP, if sec is less than 10.
-  */
-esp_err_t esp_wifi_set_inactive_time(wifi_interface_t ifx, uint16_t sec);
-
-/**
-  * @brief     Get inactive time of specified interface
-  *
-  * @param     ifx  Interface to be configured.
-  * @param     sec  Inactive time. Unit seconds.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_ARG: invalid argument
-  */
-esp_err_t esp_wifi_get_inactive_time(wifi_interface_t ifx, uint16_t *sec);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_WIFI_H__ */
diff --git a/tools/sdk/include/esp32/esp_wifi_crypto_types.h b/tools/sdk/include/esp32/esp_wifi_crypto_types.h
deleted file mode 100644
index e1e2a51a131..00000000000
--- a/tools/sdk/include/esp32/esp_wifi_crypto_types.h
+++ /dev/null
@@ -1,799 +0,0 @@
-// Hardware crypto support Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_WIFI_CRYPTO_TYPES_H__
-#define __ESP_WIFI_CRYPTO_TYPES_H__
-
-/* This is an internal API header for configuring the implementation used for WiFi cryptographic
-   operations.
-
-   During normal operation, you don't need to use any of these types or functions in this header.
-   See esp_wifi.h & esp_wifi_types.h instead.
-*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ESP_WIFI_CRYPTO_VERSION 0x00000001
-
-/*
- * Enumeration for hash operations.
- * When WPA2 is connecting, this enum is used to
- * request a hash algorithm via crypto_hash_xxx functions.
- */
-typedef enum {
-    ESP_CRYPTO_HASH_ALG_MD5, ESP_CRYPTO_HASH_ALG_SHA1,
-    ESP_CRYPTO_HASH_ALG_HMAC_MD5, ESP_CRYPTO_HASH_ALG_HMAC_SHA1,
-    ESP_CRYPTO_HASH_ALG_SHA256, ESP_CRYPTO_HASH_ALG_HMAC_SHA256
-}esp_crypto_hash_alg_t;
-
-/*
- * Enumeration for block cipher operations.
- * When WPA2 is connecting, this enum is used to request a block
- * cipher algorithm via crypto_cipher_xxx functions.
- */
-typedef enum {
-    ESP_CRYPTO_CIPHER_NULL, ESP_CRYPTO_CIPHER_ALG_AES, ESP_CRYPTO_CIPHER_ALG_3DES,
-    ESP_CRYPTO_CIPHER_ALG_DES, ESP_CRYPTO_CIPHER_ALG_RC2, ESP_CRYPTO_CIPHER_ALG_RC4
-} esp_crypto_cipher_alg_t;
-
-/*
- * This structure is about the algorithm when do crypto_hash operation, for detail, 
- * please reference to the structure crypto_hash.
- */
-typedef struct crypto_hash esp_crypto_hash_t;
-
-/*
- * This structure is about the algorithm when do crypto_cipher operation, for detail, 
- * please reference to the structure crypto_cipher.
- */
-typedef struct crypto_cipher esp_crypto_cipher_t;
-
-/**
-  * @brief The crypto callback function used in wpa enterprise hash operation when connect.
-  *        Initialize a esp_crypto_hash_t structure.
-  *
-  * @param alg  Hash algorithm.
-  * @param key  Key for keyed hash (e.g., HMAC) or %NULL if not needed.
-  * @param key_len  Length of the key in bytes
-  *
-  */
-typedef esp_crypto_hash_t * (*esp_crypto_hash_init_t)(esp_crypto_hash_alg_t alg, const unsigned char *key, int key_len);
-
-/**
-  * @brief The crypto callback function used in wpa enterprise hash operation when connect. 
-  *        Add data to hash calculation.
-  *
-  * @param ctz  Context pointer from esp_crypto_hash_init_t function.
-  * @param data  Data buffer to add.
-  * @param len  Length of the buffer.
-  *
-  */
-typedef void (*esp_crypto_hash_update_t)(esp_crypto_hash_t *ctx, const unsigned char *data, int len);
-
-/**
-  * @brief The crypto callback function used in wpa enterprise hash operation when connect. 
-  *        Complete hash calculation.
-  *
-  * @param ctz  Context pointer from esp_crypto_hash_init_t function.
-  * @param hash   Buffer for hash value or %NULL if caller is just freeing the hash
-  *               context.
-  * @param len  Pointer to length of the buffer or %NULL if caller is just freeing the
-  *             hash context; on return, this is set to the actual length of the hash value
-  *             Returns: 0 on success, -1 if buffer is too small (len set to needed length),
-  *             or -2 on other failures (including failed crypto_hash_update() operations)
-  *
-  */
-typedef int (*esp_crypto_hash_finish_t)(esp_crypto_hash_t *ctx, unsigned char *hash, int *len);
-
-/**
-  * @brief The AES callback function when do WPS connect. 
-  *
-  * @param key  Encryption key.
-  * @param iv  Encryption IV for CBC mode (16 bytes).
-  * @param data  Data to encrypt in-place.
-  * @param data_len  Length of data in bytes (must be divisible by 16)
-  */
-typedef int (*esp_aes_128_encrypt_t)(const unsigned char *key, const unsigned char *iv, unsigned char *data, int data_len);
-
-/**
-  * @brief The AES callback function when do WPS connect. 
-  *
-  * @param key  Decryption key.
-  * @param iv  Decryption IV for CBC mode (16 bytes).
-  * @param data  Data to decrypt in-place.
-  * @param data_len  Length of data in bytes (must be divisible by 16)
-  *
-  */
-typedef int (*esp_aes_128_decrypt_t)(const unsigned char *key, const unsigned char *iv, unsigned char *data, int data_len);
-
-/**
-  * @brief The AES callback function when do STA connect.
-  *
-  * @param kek  16-octet Key encryption key (KEK).
-  * @param n  Length of the plaintext key in 64-bit units;
-  * @param plain  Plaintext key to be wrapped, n * 64 bits
-  * @param cipher  Wrapped key, (n + 1) * 64 bits
-  *
-  */
-typedef int (*esp_aes_wrap_t)(const unsigned char *kek, int n, const unsigned char *plain, unsigned char *cipher);
-
-/**
-  * @brief The AES callback function when do STA connect.
-  *
-  * @param kek  16-octet Key decryption key (KEK).
-  * @param n  Length of the plaintext key in 64-bit units;
-  * @param cipher  Wrapped key to be unwrapped, (n + 1) * 64 bits
-  * @param plain  Plaintext key, n * 64 bits
-  *
-  */
-typedef int (*esp_aes_unwrap_t)(const unsigned char *kek, int n, const unsigned char *cipher, unsigned char *plain);
-
-/**
-  * @brief The crypto callback function used in wpa enterprise cipher operation when connect.
-  *        Initialize a esp_crypto_cipher_t structure.
-  *
-  * @param alg  cipher algorithm.
-  * @param iv  Initialization vector for block ciphers or %NULL for stream ciphers.
-  * @param key  Cipher key
-  * @param key_len  Length of key in bytes
-  *
-  */
-typedef esp_crypto_cipher_t * (*esp_crypto_cipher_init_t)(esp_crypto_cipher_alg_t alg, const unsigned char *iv, const unsigned char *key, int key_len);
-
-/**
-  * @brief The crypto callback function used in wpa enterprise cipher operation when connect.
-  *        Cipher encrypt.
-  *
-  * @param ctx  Context pointer from esp_crypto_cipher_init_t callback function.
-  * @param plain  Plaintext to cipher.
-  * @param crypt  Resulting ciphertext.
-  * @param len  Length of the plaintext.
-  *
-  */
-typedef int (*esp_crypto_cipher_encrypt_t)(esp_crypto_cipher_t *ctx,
-				             const unsigned char *plain, unsigned char *crypt, int len);
-/**
-  * @brief The crypto callback function used in wpa enterprise cipher operation when connect.
-  *        Cipher decrypt.
-  *
-  * @param ctx  Context pointer from esp_crypto_cipher_init_t callback function.
-  * @param crypt  Ciphertext to decrypt.
-  * @param plain  Resulting plaintext.
-  * @param len  Length of the cipher text.
-  *
-  */
-typedef int (*esp_crypto_cipher_decrypt_t)(esp_crypto_cipher_t *ctx,
-				             const unsigned char *crypt, unsigned char *plain, int len);
-/**
-  * @brief The crypto callback function used in wpa enterprise cipher operation when connect.
-  *        Free cipher context.
-  *
-  * @param ctx  Context pointer from esp_crypto_cipher_init_t callback function.
-  *
-  */
-typedef void (*esp_crypto_cipher_deinit_t)(esp_crypto_cipher_t *ctx);
-
-/**
-  * @brief The SHA256 callback function when do WPS connect. 
-  *
-  * @param key  Key for HMAC operations.
-  * @param key_len  Length of the key in bytes.
-  * @param data  Pointers to the data area.
-  * @param data_len  Length of the data area.
-  * @param mac  Buffer for the hash (20 bytes).
-  *
-  */
-typedef void (*esp_hmac_sha256_t)(const unsigned char *key, int key_len, const unsigned char *data,
-		                    int data_len, unsigned char *mac);
-
-/**
-  * @brief The SHA256 callback function when do WPS connect. 
-  *
-  * @param key  Key for HMAC operations.
-  * @param key_len  Length of the key in bytes.
-  * @param num_elem  Number of elements in the data vector.
-  * @param addr  Pointers to the data areas.
-  * @param len  Lengths of the data blocks.
-  * @param mac  Buffer for the hash (32 bytes).
-  *
-  */
-typedef void (*esp_hmac_sha256_vector_t)(const unsigned char *key, int key_len, int num_elem,
-			                   const unsigned char *addr[], const int *len, unsigned char *mac);
-
-/**
-  * @brief The AES callback function when do STA connect.
-  *
-  * @param key  Key for PRF.
-  * @param key_len  Length of the key in bytes.
-  * @param label  A unique label for each purpose of the PRF.
-  * @param data  Extra data to bind into the key.
-  * @param data_len  Length of the data.
-  * @param buf  Buffer for the generated pseudo-random key.  
-  * @param buf_len  Number of bytes of key to generate.
-  *
-  */
-typedef void (*esp_sha256_prf_t)(const unsigned char *key, int key_len, const char *label,
-	                           const unsigned char *data, int data_len, unsigned char *buf, int buf_len);
-
-/**
-  * @brief The SHA256 callback function when do WPS connect. 
-  *
-  * @param num_elem  Number of elements in the data vector.
-  * @param addr  Pointers to the data areas.
-  * @param len  Lengths of the data blocks.
-  * @paramac  Buffer for the hash.
-  *
-  */
-typedef int (*esp_sha256_vector_t)(int num_elem, const unsigned char *addr[], const int *len,
-		                     unsigned char *mac);
-
-/**
-  * @brief The bignum calculate callback function used when do connect. 
-  *        In WPS process, it used to calculate public key and private key.
-  *
-  * @param base  Base integer (big endian byte array).
-  * @param base_len  Length of base integer in bytes.
-  * @param power  Power integer (big endian byte array).
-  * @param power_len  Length of power integer in bytes.
-  * @param modulus  Modulus integer (big endian byte array).
-  * @param modulus_len  Length of modulus integer in bytes.
-  * @param result  Buffer for the result.
-  * @param result_len  Result length (max buffer size on input, real len on output).
-  *
-  */
-typedef int (*esp_crypto_mod_exp_t)(const unsigned char *base, int base_len,
-		                      const unsigned char *power, int power_len,
-		                      const unsigned char *modulus, int modulus_len,
-		                      unsigned char *result, unsigned int *result_len);
-
-/**
- * @brief HMAC-MD5 over data buffer (RFC 2104)'
- * 
- * @key: Key for HMAC operations
- * @key_len: Length of the key in bytes
- * @data: Pointers to the data area
- * @data_len: Length of the data area
- * @mac: Buffer for the hash (16 bytes)
- * Returns: 0 on success, -1 on failure
- */
-typedef int (*esp_hmac_md5_t)(const unsigned char *key, unsigned int key_len, const unsigned char *data, 
-                              unsigned int data_len, unsigned char *mac);
-
-/**
- * @brief HMAC-MD5 over data vector (RFC 2104)
- * 
- * @key: Key for HMAC operations
- * @key_len: Length of the key in bytes
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash (16 bytes)
- * Returns: 0 on success, -1 on failure
- */
-typedef int (*esp_hmac_md5_vector_t)(const unsigned char *key, unsigned int key_len, unsigned int num_elem,
-                              const unsigned char *addr[], const unsigned int *len, unsigned char *mac);
-
-/**
- * @brief HMAC-SHA1 over data buffer (RFC 2104)
- * 
- * @key: Key for HMAC operations
- * @key_len: Length of the key in bytes
- * @data: Pointers to the data area
- * @data_len: Length of the data area
- * @mac: Buffer for the hash (20 bytes)
- * Returns: 0 on success, -1 of failure
- */
-typedef int (*esp_hmac_sha1_t)(const unsigned char *key, unsigned int key_len, const unsigned char *data, 
-                              unsigned int data_len, unsigned char *mac);
-
-/**
- * @brief HMAC-SHA1 over data vector (RFC 2104)
- * 
- * @key: Key for HMAC operations
- * @key_len: Length of the key in bytes
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash (20 bytes)
- * Returns: 0 on success, -1 on failure
- */
-typedef int (*esp_hmac_sha1_vector_t)(const unsigned char *key, unsigned int key_len, unsigned int num_elem,
-                              const unsigned char *addr[], const unsigned int *len, unsigned char *mac);
-
-/**
- * @brief SHA1-based Pseudo-Random Function (PRF) (IEEE 802.11i, 8.5.1.1)
- * 
- * @key: Key for PRF
- * @key_len: Length of the key in bytes
- * @label: A unique label for each purpose of the PRF
- * @data: Extra data to bind into the key
- * @data_len: Length of the data
- * @buf: Buffer for the generated pseudo-random key
- * @buf_len: Number of bytes of key to generate
- * Returns: 0 on success, -1 of failure
- *
- * This function is used to derive new, cryptographically separate keys from a
- * given key (e.g., PMK in IEEE 802.11i).
- */
-typedef int (*esp_sha1_prf_t)(const unsigned char *key, unsigned int key_len, const char *label,
-                              const unsigned char *data, unsigned int data_len, unsigned char *buf, unsigned int buf_len);
-
-/**
- * @brief SHA-1 hash for data vector
- * 
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash
- * Returns: 0 on success, -1 on failure
- */
-typedef int (*esp_sha1_vector_t)(unsigned int num_elem, const unsigned char *addr[], const unsigned int *len, 
-                              unsigned char *mac);
-
-/**
- * @brief SHA1-based key derivation function (PBKDF2) for IEEE 802.11i
- * 
- * @passphrase: ASCII passphrase
- * @ssid: SSID
- * @ssid_len: SSID length in bytes
- * @iterations: Number of iterations to run
- * @buf: Buffer for the generated key
- * @buflen: Length of the buffer in bytes
- * Returns: 0 on success, -1 of failure
- *
- * This function is used to derive PSK for WPA-PSK. For this protocol,
- * iterations is set to 4096 and buflen to 32. This function is described in
- * IEEE Std 802.11-2004, Clause H.4. The main construction is from PKCS#5 v2.0.
- */
-typedef int (*esp_pbkdf2_sha1_t)(const char *passphrase, const char *ssid, unsigned int ssid_len,
-                              int iterations, unsigned char *buf, unsigned int buflen);
-
-/**
- * @brief XOR RC4 stream to given data with skip-stream-start
- * 
- * @key: RC4 key
- * @keylen: RC4 key length
- * @skip: number of bytes to skip from the beginning of the RC4 stream
- * @data: data to be XOR'ed with RC4 stream
- * @data_len: buf length
- * Returns: 0 on success, -1 on failure
- *
- * Generate RC4 pseudo random stream for the given key, skip beginning of the
- * stream, and XOR the end result with the data buffer to perform RC4
- * encryption/decryption.
- */
-typedef int (*esp_rc4_skip_t)(const unsigned char *key, unsigned int keylen, unsigned int skip,
-                              unsigned char *data, unsigned int data_len);
-
-/**
- * @brief MD5 hash for data vector
- * 
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash
- * Returns: 0 on success, -1 on failure
- */
-typedef int (*esp_md5_vector_t)(unsigned int num_elem, const unsigned char *addr[], const unsigned int *len,
-                              unsigned char *mac);
-
-/**
- * @brief Encrypt one AES block
- * 
- * @ctx: Context pointer from aes_encrypt_init()
- * @plain: Plaintext data to be encrypted (16 bytes)
- * @crypt: Buffer for the encrypted data (16 bytes)
- */
-typedef void (*esp_aes_encrypt_t)(void *ctx, const unsigned char *plain, unsigned char *crypt);
-
-/**
- * @brief Initialize AES for encryption
- * 
- * @key: Encryption key
- * @len: Key length in bytes (usually 16, i.e., 128 bits)
- * Returns: Pointer to context data or %NULL on failure
- */
-typedef void * (*esp_aes_encrypt_init_t)(const unsigned char *key,  unsigned int len);
-
-/**
- * @brief Deinitialize AES encryption
- * 
- * @ctx: Context pointer from aes_encrypt_init()
- */
-typedef void (*esp_aes_encrypt_deinit_t)(void *ctx);
-
-/**
- * @brief Decrypt one AES block
- * 
- * @ctx: Context pointer from aes_encrypt_init()
- * @crypt: Encrypted data (16 bytes)
- * @plain: Buffer for the decrypted data (16 bytes)
- */
-typedef void (*esp_aes_decrypt_t)(void *ctx, const unsigned char *crypt, unsigned char *plain);
-
-/**
- * @brief Initialize AES for decryption
- * 
- * @key: Decryption key
- * @len: Key length in bytes (usually 16, i.e., 128 bits)
- * Returns: Pointer to context data or %NULL on failure
- */
-typedef void * (*esp_aes_decrypt_init_t)(const unsigned char *key, unsigned int len);
-
-/**
- * @brief Deinitialize AES decryption
- * 
- * @ctx: Context pointer from aes_encrypt_init()
- */
-typedef void (*esp_aes_decrypt_deinit_t)(void *ctx);
-
-/**
- * @brief Initialize TLS library
- * 
- * @conf: Configuration data for TLS library
- * Returns: Context data to be used as tls_ctx in calls to other functions,
- * or %NULL on failure.
- *
- * Called once during program startup and once for each RSN pre-authentication
- * session. In other words, there can be two concurrent TLS contexts. If global
- * library initialization is needed (i.e., one that is shared between both
- * authentication types), the TLS library wrapper should maintain a reference
- * counter and do global initialization only when moving from 0 to 1 reference.
- */
-typedef void * (*esp_tls_init_t)(void);
-
-/**
- * @brief Deinitialize TLS library
- * 
- * @tls_ctx: TLS context data from tls_init()
- *
- * Called once during program shutdown and once for each RSN pre-authentication
- * session. If global library deinitialization is needed (i.e., one that is
- * shared between both authentication types), the TLS library wrapper should
- * maintain a reference counter and do global deinitialization only when moving
- * from 1 to 0 references.
- */
-typedef void (*esp_tls_deinit_t)(void *tls_ctx);
-
-/**
- * @brief Add certificate and private key for connect
- 
- * @sm: eap state machine
- * 
- * Returns: 0 for success, -1 state machine didn't exist, -2 short of certificate or key
- */
-typedef int (*esp_eap_peer_blob_init_t)(void *sm);
-
-/**
- * @brief delete the certificate and private
- * 
- * @sm: eap state machine
- * 
- */
-typedef void (*esp_eap_peer_blob_deinit_t)(void *sm);
-
-/**
- * @brief Initialize the eap state machine
- * 
- * @sm: eap state machine
- * @private_key_passwd: the start address of private_key_passwd
- * @private_key_passwd_len: length of private_key_password
- * 
- * Returns: 0 is success, -1 state machine didn't exist, -2 short of parameters
- * 
- */
-typedef int (*esp_eap_peer_config_init_t)(void *sm, unsigned char *private_key_passwd,int private_key_passwd_len);
-
-/**
- * @brief Deinit the eap state machine
- * 
- * @sm: eap state machine
- * 
- */
-typedef void (*esp_eap_peer_config_deinit_t)(void *sm);
-
-/**
- * @brief Register the eap method 
- * 
- * Note: ESP32 only support PEAP/TTLS/TLS three eap methods now.
- * 
- */
-typedef int (*esp_eap_peer_register_methods_t)(void);
-
-/**
- * @brief remove the eap method 
- * 
- * Note: ESP32 only support PEAP/TTLS/TLS three eap methods now.
- * 
- */
-typedef void (*esp_eap_peer_unregister_methods_t)(void);
-
-/**
- * @brief remove the eap method before build new connect
- * 
- * @sm: eap state machine
- * @txt: not used now
- */
-typedef void (*esp_eap_deinit_prev_method_t)(void *sm, const char *txt);
-
-/**
- * @brief Get EAP method based on type number
- * 
- * @vendor: EAP Vendor-Id (0 = IETF)
- * @method: EAP type number
- * Returns: Pointer to EAP method or %NULL if not found
- */
-typedef const void * (*esp_eap_peer_get_eap_method_t)(int vendor, int method);
-
-/**
- * @brief Abort EAP authentication
- * 
- * @sm: Pointer to EAP state machine allocated with eap_peer_sm_init()
- *
- * Release system resources that have been allocated for the authentication
- * session without fully deinitializing the EAP state machine.
- */
-typedef void (*esp_eap_sm_abort_t)(void *sm);
-
-/**
- * @brief Build EAP-NAK for the current network
- * 
- * @sm: Pointer to EAP state machine allocated with eap_peer_sm_init()
- * @type: EAP type of the fail reason
- * @id: EAP identifier for the packet
- *
- * This function allocates and builds a nak packet for the
- * current network. The caller is responsible for freeing the returned data.
- */
-typedef void * (*esp_eap_sm_build_nak_t)(void *sm, int type, unsigned char id);
-
-/**
- * @brief Build EAP-Identity/Response for the current network
- * 
- * @sm: Pointer to EAP state machine allocated with eap_peer_sm_init()
- * @id: EAP identifier for the packet
- * @encrypted: Whether the packet is for encrypted tunnel (EAP phase 2)
- * Returns: Pointer to the allocated EAP-Identity/Response packet or %NULL on
- * failure
- *
- * This function allocates and builds an EAP-Identity/Response packet for the
- * current network. The caller is responsible for freeing the returned data.
- */
-typedef void * (*esp_eap_sm_build_identity_resp_t)(void *sm, unsigned char id, int encrypted);
-
-/**
- * @brief Allocate a buffer for an EAP message
- * 
- * @vendor: Vendor-Id (0 = IETF)
- * @type: EAP type
- * @payload_len: Payload length in bytes (data after Type)
- * @code: Message Code (EAP_CODE_*)
- * @identifier: Identifier
- * Returns: Pointer to the allocated message buffer or %NULL on error
- *
- * This function can be used to allocate a buffer for an EAP message and fill
- * in the EAP header. This function is automatically using expanded EAP header
- * if the selected Vendor-Id is not IETF. In other words, most EAP methods do
- * not need to separately select which header type to use when using this
- * function to allocate the message buffers. The returned buffer has room for
- * payload_len bytes and has the EAP header and Type field already filled in.
- */
-typedef void * (*esp_eap_msg_alloc_t)(int vendor, int type, unsigned int payload_len,
-                             unsigned char code, unsigned char identifier);
-
-/**
- * @brief get the enrollee mac address
- * @mac_addr: instore the mac address of enrollee
- * @uuid: Universally Unique Identifer of the enrollee
- * 
- */                        
-typedef void (*esp_uuid_gen_mac_addr_t)(const unsigned char *mac_addr, unsigned char *uuid);
-
-/**
- * @brief free the message after finish DH
- * 
- */
-typedef void (*esp_dh5_free_t)(void *ctx);
-
-/**
- * @brief Build WPS IE for (Re)Association Request
- * 
- * @req_type: Value for Request Type attribute
- * Returns: WPS IE or %NULL on failure
- *
- * The caller is responsible for freeing the buffer.
- */
-typedef void * (*esp_wps_build_assoc_req_ie_t)(int req_type);
-
-/**
- * @brief Build WPS IE for (Re)Association Response
- * 
- * Returns: WPS IE or %NULL on failure
- *
- * The caller is responsible for freeing the buffer.
- */
-typedef void * (*esp_wps_build_assoc_resp_ie_t)(void);
-
-/**
- * @brief Build WPS IE for Probe Request
- * 
- * @pw_id: Password ID (DEV_PW_PUSHBUTTON for active PBC and DEV_PW_DEFAULT for
- * most other use cases)
- * @dev: Device attributes
- * @uuid: Own UUID
- * @req_type: Value for Request Type attribute
- * @num_req_dev_types: Number of requested device types
- * @req_dev_types: Requested device types (8 * num_req_dev_types octets) or
- *	%NULL if none
- * Returns: WPS IE or %NULL on failure
- *
- * The caller is responsible for freeing the buffer.
- */
-typedef void * (*esp_wps_build_probe_req_ie_t)(uint16_t pw_id, void *dev, const unsigned char *uuid,
-                             int req_type, unsigned int num_req_dev_types, const unsigned char *req_dev_types);
-
-/**
- * @brief build public key for exchange in M1
- * 
- * 
- */
-typedef int (*esp_wps_build_public_key_t)(void *wps, void *msg, int mode);
-
-
-/**
- * @brief get the wps information in exchange password
- * 
- * 
- */
-typedef void * (*esp_wps_enrollee_get_msg_t)(void *wps, void *op_code);
-
-/**
- * @brief deal with the wps information in exchange password
- * 
- * 
- */
-typedef int (*esp_wps_enrollee_process_msg_t)(void *wps, int op_code, const void *msg);
-
-/**
- * @brief Generate a random PIN
- * 
- * Returns: Eight digit PIN (i.e., including the checksum digit)
- */
-typedef unsigned int (*esp_wps_generate_pin_t)(void);
-
-/**
- * @brief Check whether WPS IE indicates active PIN
- * 
- * @msg: WPS IE contents from Beacon or Probe Response frame
- * Returns: 1 if PIN Registrar is active, 0 if not
- */
-typedef int (*esp_wps_is_selected_pin_registrar_t)(const void *msg, unsigned char *bssid);
-
-/**
- * @brief Check whether WPS IE indicates active PBC
- * 
- * @msg: WPS IE contents from Beacon or Probe Response frame
- * Returns: 1 if PBC Registrar is active, 0 if not
- */
-typedef int (*esp_wps_is_selected_pbc_registrar_t)(const void *msg, unsigned char *bssid);
-
-
-
-/**
-  * @brief The crypto callback function structure used when do station security connect.
-  *        The structure can be set as software crypto or the crypto optimized by ESP32
-  *        hardware.
-  */
-typedef struct {
-    uint32_t size;
-    uint32_t version;
-    esp_aes_wrap_t aes_wrap;                         /**< station connect function used when send EAPOL frame */
-    esp_aes_unwrap_t aes_unwrap;                     /**< station connect function used when decrypt key data */
-    esp_hmac_sha256_vector_t hmac_sha256_vector;     /**< station connect function used when check MIC */
-    esp_sha256_prf_t sha256_prf;                     /**< station connect function used when check MIC */
-    esp_hmac_md5_t hmac_md5;
-    esp_hmac_md5_vector_t hamc_md5_vector;
-    esp_hmac_sha1_t hmac_sha1;
-    esp_hmac_sha1_vector_t hmac_sha1_vector;
-    esp_sha1_prf_t sha1_prf;
-    esp_sha1_vector_t sha1_vector;
-    esp_pbkdf2_sha1_t pbkdf2_sha1;
-    esp_rc4_skip_t rc4_skip;
-    esp_md5_vector_t md5_vector;
-    esp_aes_encrypt_t aes_encrypt;
-    esp_aes_encrypt_init_t aes_encrypt_init;
-    esp_aes_encrypt_deinit_t aes_encrypt_deinit;
-    esp_aes_decrypt_t aes_decrypt;
-    esp_aes_decrypt_init_t aes_decrypt_init;
-    esp_aes_decrypt_deinit_t aes_decrypt_deinit;
-}wpa_crypto_funcs_t;
-
-/**
-  * @brief The crypto callback function structure used when do WPS process. The 
-  *        structure can be set as software crypto or the crypto optimized by ESP32
-  *        hardware.
-  */
-typedef struct{
-    uint32_t size;
-    uint32_t version;
-    esp_aes_128_encrypt_t aes_128_encrypt;          /**< function used to process message when do WPS */
-    esp_aes_128_decrypt_t aes_128_decrypt;          /**< function used to process message when do WPS */
-    esp_crypto_mod_exp_t crypto_mod_exp;            /**< function used to calculate public key and private key */
-    esp_hmac_sha256_t hmac_sha256;                  /**< function used to get attribute */
-    esp_hmac_sha256_vector_t hmac_sha256_vector;    /**< function used to process message when do WPS */
-    esp_sha256_vector_t sha256_vector;              /**< function used to process message when do WPS */
-    esp_uuid_gen_mac_addr_t uuid_gen_mac_addr;
-    esp_dh5_free_t dh5_free;
-    esp_wps_build_assoc_req_ie_t wps_build_assoc_req_ie;
-    esp_wps_build_assoc_resp_ie_t wps_build_assoc_resp_ie;
-    esp_wps_build_probe_req_ie_t wps_build_probe_req_ie;
-    esp_wps_build_public_key_t wps_build_public_key;
-    esp_wps_enrollee_get_msg_t wps_enrollee_get_msg;
-    esp_wps_enrollee_process_msg_t wps_enrollee_process_msg;
-    esp_wps_generate_pin_t wps_generate_pin;
-    esp_wps_is_selected_pin_registrar_t wps_is_selected_pin_registrar;
-    esp_wps_is_selected_pbc_registrar_t wps_is_selected_pbc_registrar;
-    esp_eap_msg_alloc_t eap_msg_alloc;
-}wps_crypto_funcs_t;
-
-/**
-  * @brief The crypto callback function structure used when do WPA enterprise connect.
-  *        The structure can be set as software crypto or the crypto optimized by ESP32
-  *        hardware.
-  */
-typedef struct {
-    uint32_t size;
-    uint32_t version;
-    esp_crypto_hash_init_t crypto_hash_init;                  /**< function used to initialize a crypto_hash structure when use TLSV1 */
-    esp_crypto_hash_update_t crypto_hash_update;              /**< function used to calculate hash data when use TLSV1 */
-    esp_crypto_hash_finish_t crypto_hash_finish;              /**< function used to finish the hash calculate when use TLSV1 */
-    esp_crypto_cipher_init_t crypto_cipher_init;              /**< function used to initialize a crypt_cipher structure when use TLSV1 */
-    esp_crypto_cipher_encrypt_t crypto_cipher_encrypt;        /**< function used to encrypt cipher when use TLSV1 */
-    esp_crypto_cipher_decrypt_t crypto_cipher_decrypt;        /**< function used to decrypt cipher when use TLSV1 */
-    esp_crypto_cipher_deinit_t crypto_cipher_deinit;          /**< function used to free context when use TLSV1 */
-    esp_crypto_mod_exp_t crypto_mod_exp;                      /**< function used to do key exchange when use TLSV1 */
-    esp_sha256_vector_t sha256_vector;                        /**< function used to do X.509v3 certificate parsing and processing */
-    esp_tls_init_t tls_init;
-    esp_tls_deinit_t tls_deinit;
-    esp_eap_peer_blob_init_t eap_peer_blob_init;
-    esp_eap_peer_blob_deinit_t eap_peer_blob_deinit;
-    esp_eap_peer_config_init_t eap_peer_config_init;
-    esp_eap_peer_config_deinit_t eap_peer_config_deinit;
-    esp_eap_peer_register_methods_t eap_peer_register_methods;
-    esp_eap_peer_unregister_methods_t eap_peer_unregister_methods;
-    esp_eap_deinit_prev_method_t eap_deinit_prev_method;
-    esp_eap_peer_get_eap_method_t eap_peer_get_eap_method;
-    esp_eap_sm_abort_t eap_sm_abort;
-    esp_eap_sm_build_nak_t eap_sm_build_nak;
-    esp_eap_sm_build_identity_resp_t eap_sm_build_identity_resp;
-    esp_eap_msg_alloc_t eap_msg_alloc;
-} wpa2_crypto_funcs_t;
-
-/**
-  * @brief The crypto callback function structure used in mesh vendor IE encryption. The
-  *        structure can be set as software crypto or the crypto optimized by ESP32
-  *        hardware.
-  */
-typedef struct{
-    esp_aes_128_encrypt_t aes_128_encrypt;          /**< function used in mesh vendor IE encryption */
-    esp_aes_128_decrypt_t aes_128_decrypt;          /**< function used in mesh vendor IE decryption */
-} mesh_crypto_funcs_t;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/tools/sdk/include/esp32/esp_wifi_internal.h b/tools/sdk/include/esp32/esp_wifi_internal.h
deleted file mode 100644
index 71d0a9c24ff..00000000000
--- a/tools/sdk/include/esp32/esp_wifi_internal.h
+++ /dev/null
@@ -1,362 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-/*
- * All the APIs declared here are internal only APIs, it can only be used by 
- * espressif internal modules, such as SSC, LWIP, TCPIP adapter etc, espressif 
- * customers are not recommended to use them.
- *
- * If someone really want to use specified APIs declared in here, please contact
- * espressif AE/developer to make sure you know the limitations or risk of 
- * the API, otherwise you may get unexpected behavior!!!
- *
- */
-
-
-#ifndef __ESP_WIFI_INTERNAL_H__
-#define __ESP_WIFI_INTERNAL_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "freertos/FreeRTOS.h"
-#include "freertos/queue.h"
-#include "rom/queue.h"
-#include "esp_err.h"
-#include "esp_wifi_types.h"
-#include "esp_event.h"
-#include "esp_wifi.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    QueueHandle_t handle; /**< FreeRTOS queue handler */
-    void *storage;        /**< storage for FreeRTOS queue */
-} wifi_static_queue_t;
-
-/**
-  * @brief WiFi log level
-  *
-  */
-typedef enum {
-    WIFI_LOG_ERROR = 0,   /*enabled by default*/
-    WIFI_LOG_WARNING,     /*enabled by default*/
-    WIFI_LOG_INFO,        /*enabled by default*/
-    WIFI_LOG_DEBUG,       /*can be set in menuconfig*/
-    WIFI_LOG_VERBOSE,     /*can be set in menuconfig*/
-} wifi_log_level_t;
-  
-/**
-  * @brief WiFi log module definition
-  *
-  */
-typedef enum {
-    WIFI_LOG_MODULE_ALL  = 0, /*all log modules */
-    WIFI_LOG_MODULE_WIFI, /*logs related to WiFi*/
-    WIFI_LOG_MODULE_COEX, /*logs related to WiFi and BT(or BLE) coexist*/
-    WIFI_LOG_MODULE_MESH, /*logs related to Mesh*/
-} wifi_log_module_t;
-
-/**
-  * @brief WiFi log submodule definition
-  *
-  */
-#define WIFI_LOG_SUBMODULE_ALL   (0)    /*all log submodules*/
-#define WIFI_LOG_SUBMODULE_INIT  (1)    /*logs related to initialization*/
-#define WIFI_LOG_SUBMODULE_IOCTL (1<<1) /*logs related to API calling*/
-#define WIFI_LOG_SUBMODULE_CONN  (1<<2) /*logs related to connecting*/
-#define WIFI_LOG_SUBMODULE_SCAN  (1<<3) /*logs related to scaning*/
-
-
-/**
- * @brief Initialize Wi-Fi Driver
- *     Alloc resource for WiFi driver, such as WiFi control structure, RX/TX buffer,
- *     WiFi NVS structure among others.
- *
- * For the most part, you need not call this function directly. It gets called
- * from esp_wifi_init().
- *
- * This function may be called, if you only need to initialize the Wi-Fi driver
- * without having to use the network stack on top.
- *
- * @param  config provide WiFi init configuration
- *
- * @return
- *    - ESP_OK: succeed
- *    - ESP_ERR_NO_MEM: out of memory
- *    - others: refer to error code esp_err.h
- */
-esp_err_t esp_wifi_init_internal(const wifi_init_config_t *config);
-
-/**
-  * @brief  get whether the wifi driver is allowed to transmit data or not
-  *
-  * @return
-  *     - true  : upper layer should stop to transmit data to wifi driver
-  *     - false : upper layer can transmit data to wifi driver
-  */
-bool esp_wifi_internal_tx_is_stop(void);
-
-/**
-  * @brief  free the rx buffer which allocated by wifi driver
-  *
-  * @param  void* buffer: rx buffer pointer
-  */
-void esp_wifi_internal_free_rx_buffer(void* buffer);
-
-/**
-  * @brief  transmit the buffer via wifi driver
-  *
-  * @param  wifi_interface_t wifi_if : wifi interface id
-  * @param  void *buffer : the buffer to be tansmit
-  * @param  uint16_t len : the length of buffer
-  *
-  * @return
-  *    - ERR_OK  : Successfully transmit the buffer to wifi driver
-  *    - ERR_MEM : Out of memory
-  *    - ERR_IF : WiFi driver error
-  *    - ERR_ARG : Invalid argument
-  */
-int esp_wifi_internal_tx(wifi_interface_t wifi_if, void *buffer, uint16_t len);
-
-/**
-  * @brief     The WiFi RX callback function
-  *
-  *            Each time the WiFi need to forward the packets to high layer, the callback function will be called
-  */
-typedef esp_err_t (*wifi_rxcb_t)(void *buffer, uint16_t len, void *eb);
-
-/**
-  * @brief     Set the WiFi RX callback
-  *
-  * @attention 1. Currently we support only one RX callback for each interface
-  *
-  * @param     wifi_interface_t ifx : interface
-  * @param     wifi_rxcb_t fn : WiFi RX callback
-  *
-  * @return
-  *     - ESP_OK : succeed
-  *     - others : fail
-  */
-esp_err_t esp_wifi_internal_reg_rxcb(wifi_interface_t ifx, wifi_rxcb_t fn);
-
-/**
-  * @brief     Notify WIFI driver that the station got ip successfully
-  *
-  * @return
-  *     - ESP_OK : succeed
-  *     - others : fail
-  */
-esp_err_t esp_wifi_internal_set_sta_ip(void);
-
-/**
-  * @brief  enable or disable transmitting WiFi MAC frame with fixed rate
-  *
-  * @attention 1. If fixed rate is enabled, both management and data frame are transmitted with fixed rate
-  * @attention 2. Make sure that the receiver is able to receive the frame with the fixed rate if you want the frame to be received
-  *
-  * @param  ifx : wifi interface
-  * @param  en : false - disable, true - enable
-  * @param  rate : PHY rate
-  *
-  * @return
-  *    - ERR_OK  : succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
-  *    - ESP_ERR_WIFI_IF : invalid WiFi interface
-  *    - ESP_ERR_INVALID_ARG : invalid rate
-  *    - ESP_ERR_NOT_SUPPORTED : do not support to set fixed rate if TX AMPDU is enabled
-  */
-esp_err_t esp_wifi_internal_set_fix_rate(wifi_interface_t ifx, bool en, wifi_phy_rate_t rate);
-
-/**
-  * @brief     Check the MD5 values of the OS adapter header files in IDF and WiFi library
-  *
-  * @attention 1. It is used for internal CI version check
-  *
-  * @return
-  *     - ESP_OK : succeed
-  *     - ESP_WIFI_INVALID_ARG : MD5 check fail
-  */
-esp_err_t esp_wifi_internal_osi_funcs_md5_check(const char *md5);
-
-/**
-  * @brief     Check the MD5 values of the crypto types header files in IDF and WiFi library
-  *
-  * @attention 1. It is used for internal CI version check
-  *
-  * @return
-  *     - ESP_OK : succeed
-  *     - ESP_WIFI_INVALID_ARG : MD5 check fail
-  */
-esp_err_t esp_wifi_internal_crypto_funcs_md5_check(const char *md5);
-
-/**
-  * @brief     Check the MD5 values of the esp_wifi_types.h in IDF and WiFi library
-  *
-  * @attention 1. It is used for internal CI version check
-  *
-  * @return
-  *     - ESP_OK : succeed
-  *     - ESP_WIFI_INVALID_ARG : MD5 check fail
-  */
-esp_err_t esp_wifi_internal_wifi_type_md5_check(const char *md5);
-
-/**
-  * @brief     Check the MD5 values of the esp_wifi.h in IDF and WiFi library
-  *
-  * @attention 1. It is used for internal CI version check
-  *
-  * @return
-  *     - ESP_OK : succeed
-  *     - ESP_WIFI_INVALID_ARG : MD5 check fail
-  */
-esp_err_t esp_wifi_internal_esp_wifi_md5_check(const char *md5);
-
-/**
-  * @brief     Allocate a chunk of memory for WiFi driver
-  *
-  * @attention This API is not used for DMA memory allocation.
-  *
-  * @param     size_t size : Size, in bytes, of the amount of memory to allocate
-  *
-  * @return    A pointer to the memory allocated on success, NULL on failure
-  */
-void *wifi_malloc( size_t size );
-
-/**
-  * @brief     Reallocate a chunk of memory for WiFi driver
-  *
-  * @attention This API is not used for DMA memory allocation.
-  *
-  * @param     void * ptr  : Pointer to previously allocated memory, or NULL for a new allocation.
-  * @param     size_t size : Size, in bytes, of the amount of memory to allocate
-  *
-  * @return    A pointer to the memory allocated on success, NULL on failure
-  */
-void *wifi_realloc( void *ptr, size_t size );
-
-/**
-  * @brief     Callocate memory for WiFi driver
-  *
-  * @attention This API is not used for DMA memory allocation.
-  *
-  * @param     size_t n    : Number of continuing chunks of memory to allocate
-  * @param     size_t size : Size, in bytes, of the amount of memory to allocate
-  *
-  * @return    A pointer to the memory allocated on success, NULL on failure
-  */
-void *wifi_calloc( size_t n, size_t size );
-
-/**
-  * @brief     Update WiFi MAC time
-  *
-  * @param     uint32_t time_delta : time duration since the WiFi/BT common clock is disabled
-  *
-  * @return    Always returns ESP_OK
-  */
-typedef esp_err_t (* wifi_mac_time_update_cb_t)( uint32_t time_delta );
-
-/**
-  * @brief     Update WiFi MAC time
-  *
-  * @param     uint32_t time_delta : time duration since the WiFi/BT common clock is disabled
-  *
-  * @return    Always returns ESP_OK
-  */
-esp_err_t esp_wifi_internal_update_mac_time( uint32_t time_delta );
-
-/**
-  * @brief     Set current WiFi log level     
-  *
-  * @param     level   Log level.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_FAIL: level is invalid
-  */
-esp_err_t esp_wifi_internal_set_log_level(wifi_log_level_t level);
-
-/**
-  * @brief     Set current log module and submodule
-  *
-  * @param     module      Log module
-  * @param     submodule   Log submodule
-  * @param     enable      enable or disable
-  *            If module == 0 && enable == 0, all log modules are disabled.
-  *            If module == 0 && enable == 1, all log modules are enabled.
-  *            If submodule == 0 && enable == 0, all log submodules are disabled.
-  *            If submodule == 0 && enable == 1, all log submodules are enabled.
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
-  *    - ESP_ERR_WIFI_ARG: invalid argument
-  */
-esp_err_t esp_wifi_internal_set_log_mod(wifi_log_module_t module, uint32_t submodule, bool enable);
-
-/**
-  * @brief     Get current WiFi log info     
-  *
-  * @param     log_level  the return log level.
-  * @param     log_mod    the return log module and submodule
-  *
-  * @return
-  *    - ESP_OK: succeed
-  */
-esp_err_t esp_wifi_internal_get_log(wifi_log_level_t *log_level, uint32_t *log_mod);
-
-/**
-  * @brief     Get the user-configured channel info 
-  *
-  * @param     ifx : WiFi interface 
-  * @param     primary : store the configured primary channel 
-  * @param     second : store the configured second channel
-  *
-  * @return    
-  *    - ESP_OK: succeed
-  */
-esp_err_t esp_wifi_internal_get_config_channel(wifi_interface_t ifx, uint8_t *primary, uint8_t *second);
-
-/**
-  * @brief     Get the negotiated channel info after WiFi connection established 
-  *
-  * @param     ifx : WiFi interface 
-  * @param     aid : the connection number when a STA connects to the softAP    
-  * @param     primary : store the negotiated primary channel 
-  * @param     second : store the negotiated second channel
-  * @attention the aid param is only works when the ESP32 in softAP/softAP+STA mode 
-  *
-  * @return    
-  *    - ESP_OK: succeed
-  */
-esp_err_t esp_wifi_internal_get_negotiated_channel(wifi_interface_t ifx, uint8_t aid, uint8_t *primary, uint8_t *second);
-
-/**
-  * @brief     Get the negotiated bandwidth info after WiFi connection established 
-  *
-  * @param     ifx : WiFi interface 
-  * @param     bw : store the negotiated bandwidth 
-  *
-  * @return    
-  *    - ESP_OK: succeed
-  */
-esp_err_t esp_wifi_internal_get_negotiated_bandwidth(wifi_interface_t ifx, uint8_t aid, uint8_t *bw);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_WIFI_H__ */
diff --git a/tools/sdk/include/esp32/esp_wifi_os_adapter.h b/tools/sdk/include/esp32/esp_wifi_os_adapter.h
deleted file mode 100644
index 666c44d9263..00000000000
--- a/tools/sdk/include/esp32/esp_wifi_os_adapter.h
+++ /dev/null
@@ -1,139 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef ESP_WIFI_OS_ADAPTER_H_
-#define ESP_WIFI_OS_ADAPTER_H_
-
-#include <stdarg.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ESP_WIFI_OS_ADAPTER_VERSION  0x00000004
-#define ESP_WIFI_OS_ADAPTER_MAGIC    0xDEADBEAF
-
-#define OSI_FUNCS_TIME_BLOCKING      0xffffffff
-
-#define OSI_QUEUE_SEND_FRONT         0
-#define OSI_QUEUE_SEND_BACK          1
-#define OSI_QUEUE_SEND_OVERWRITE     2
-
-typedef struct {
-    int32_t _version;
-    void (*_set_isr)(int32_t n, void *f, void *arg);
-    void (*_ints_on)(uint32_t mask);
-    void (*_ints_off)(uint32_t mask);
-    void *(* _spin_lock_create)(void);
-    void (* _spin_lock_delete)(void *lock);
-    uint32_t (*_wifi_int_disable)(void *wifi_int_mux);
-    void (*_wifi_int_restore)(void *wifi_int_mux, uint32_t tmp);
-    void (*_task_yield_from_isr)(void);
-    void *(*_semphr_create)(uint32_t max, uint32_t init);
-    void (*_semphr_delete)(void *semphr);
-    int32_t (*_semphr_take)(void *semphr, uint32_t block_time_tick);
-    int32_t (*_semphr_give)(void *semphr);
-    void *(*_wifi_thread_semphr_get)(void);
-    void *(*_mutex_create)(void);
-    void *(*_recursive_mutex_create)(void);
-    void (*_mutex_delete)(void *mutex);
-    int32_t (*_mutex_lock)(void *mutex);
-    int32_t (*_mutex_unlock)(void *mutex);
-    void *(* _queue_create)(uint32_t queue_len, uint32_t item_size);
-    void (* _queue_delete)(void *queue);
-    int32_t (* _queue_send)(void *queue, void *item, uint32_t block_time_tick);
-    int32_t (* _queue_send_from_isr)(void *queue, void *item, void *hptw);
-    int32_t (* _queue_send_to_back)(void *queue, void *item, uint32_t block_time_tick);
-    int32_t (* _queue_send_to_front)(void *queue, void *item, uint32_t block_time_tick);
-    int32_t (* _queue_recv)(void *queue, void *item, uint32_t block_time_tick);
-    uint32_t (* _queue_msg_waiting)(void *queue);
-    void *(* _event_group_create)(void);
-    void (* _event_group_delete)(void *event);
-    uint32_t (* _event_group_set_bits)(void *event, uint32_t bits);
-    uint32_t (* _event_group_clear_bits)(void *event, uint32_t bits);
-    uint32_t (* _event_group_wait_bits)(void *event, uint32_t bits_to_wait_for, int32_t clear_on_exit, int32_t wait_for_all_bits, uint32_t block_time_tick);
-    int32_t (* _task_create_pinned_to_core)(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id);
-    int32_t (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle);
-    void (* _task_delete)(void *task_handle);
-    void (* _task_delay)(uint32_t tick);
-    int32_t (* _task_ms_to_tick)(uint32_t ms);
-    void *(* _task_get_current_task)(void);
-    int32_t (* _task_get_max_priority)(void);
-    void *(* _malloc)(uint32_t size);
-    void (* _free)(void *p);
-    uint32_t (* _get_free_heap_size)(void);
-    uint32_t (* _rand)(void);
-    void (* _dport_access_stall_other_cpu_start_wrap)(void);
-    void (* _dport_access_stall_other_cpu_end_wrap)(void);
-    int32_t (* _phy_rf_deinit)(uint32_t module);
-    void (* _phy_load_cal_and_init)(uint32_t module);
-    void (* _phy_common_clock_enable)(void);
-    void (* _phy_common_clock_disable)(void);
-    int32_t (* _read_mac)(uint8_t* mac, uint32_t type);
-    void (* _timer_arm)(void *timer, uint32_t tmout, bool repeat);
-    void (* _timer_disarm)(void *timer);
-    void (* _timer_done)(void *ptimer);
-    void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg);
-    void (* _timer_arm_us)(void *ptimer, uint32_t us, bool repeat);
-    void (* _periph_module_enable)(uint32_t periph);
-    void (* _periph_module_disable)(uint32_t periph);
-    int64_t (* _esp_timer_get_time)(void);
-    int32_t (* _nvs_set_i8)(uint32_t handle, const char* key, int8_t value);
-    int32_t (* _nvs_get_i8)(uint32_t handle, const char* key, int8_t* out_value);
-    int32_t (* _nvs_set_u8)(uint32_t handle, const char* key, uint8_t value);
-    int32_t (* _nvs_get_u8)(uint32_t handle, const char* key, uint8_t* out_value);
-    int32_t (* _nvs_set_u16)(uint32_t handle, const char* key, uint16_t value);
-    int32_t (* _nvs_get_u16)(uint32_t handle, const char* key, uint16_t* out_value);
-    int32_t (* _nvs_open)(const char* name, uint32_t open_mode, uint32_t *out_handle);
-    void (* _nvs_close)(uint32_t handle); 
-    int32_t (* _nvs_commit)(uint32_t handle);
-    int32_t (* _nvs_set_blob)(uint32_t handle, const char* key, const void* value, size_t length);
-    int32_t (* _nvs_get_blob)(uint32_t handle, const char* key, void* out_value, size_t* length);
-    int32_t (* _nvs_erase_key)(uint32_t handle, const char* key);
-    int32_t (* _get_random)(uint8_t *buf, size_t len);
-    int32_t (* _get_time)(void *t);
-    unsigned long (* _random)(void);
-    void (* _log_write)(uint32_t level, const char* tag, const char* format, ...);
-    void (* _log_writev)(uint32_t level, const char* tag, const char* format, va_list args);
-    uint32_t (* _log_timestamp)(void);
-    void * (* _malloc_internal)(size_t size);
-    void * (* _realloc_internal)(void *ptr, size_t size);
-    void * (* _calloc_internal)(size_t n, size_t size);
-    void * (* _zalloc_internal)(size_t size);
-    void * (* _wifi_malloc)(size_t size);
-    void * (* _wifi_realloc)(void *ptr, size_t size);
-    void * (* _wifi_calloc)(size_t n, size_t size);
-    void * (* _wifi_zalloc)(size_t size);
-    void * (* _wifi_create_queue)(int32_t queue_len, int32_t item_size);
-    void (* _wifi_delete_queue)(void * queue);
-    int32_t (* _modem_sleep_enter)(uint32_t module);
-    int32_t (* _modem_sleep_exit)(uint32_t module);
-    int32_t (* _modem_sleep_register)(uint32_t module);
-    int32_t (* _modem_sleep_deregister)(uint32_t module);
-    void (* _sc_ack_send)(void *param);
-    void (* _sc_ack_send_stop)(void);
-    uint32_t (* _coex_status_get)(void);
-    void (* _coex_condition_set)(uint32_t type, bool dissatisfy);
-    int32_t (* _coex_wifi_request)(uint32_t event, uint32_t latency, uint32_t duration);
-    int32_t (* _coex_wifi_release)(uint32_t event);
-    int32_t _magic;
-} wifi_osi_funcs_t;
-
-extern wifi_osi_funcs_t g_wifi_osi_funcs;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ESP_WIFI_OS_ADAPTER_H_ */
diff --git a/tools/sdk/include/esp32/esp_wifi_types.h b/tools/sdk/include/esp32/esp_wifi_types.h
deleted file mode 100644
index f7786f5a02c..00000000000
--- a/tools/sdk/include/esp32/esp_wifi_types.h
+++ /dev/null
@@ -1,527 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_WIFI_TYPES_H__
-#define __ESP_WIFI_TYPES_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-#include "esp_private/esp_wifi_types_private.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    WIFI_MODE_NULL = 0,  /**< null mode */
-    WIFI_MODE_STA,       /**< WiFi station mode */
-    WIFI_MODE_AP,        /**< WiFi soft-AP mode */
-    WIFI_MODE_APSTA,     /**< WiFi station + soft-AP mode */
-    WIFI_MODE_MAX
-} wifi_mode_t;
-
-typedef esp_interface_t wifi_interface_t;
-
-#define WIFI_IF_STA ESP_IF_WIFI_STA
-#define WIFI_IF_AP  ESP_IF_WIFI_AP
-
-typedef enum {
-    WIFI_COUNTRY_POLICY_AUTO,   /**< Country policy is auto, use the country info of AP to which the station is connected */
-    WIFI_COUNTRY_POLICY_MANUAL, /**< Country policy is manual, always use the configured country info */
-} wifi_country_policy_t;
-
-/** @brief Structure describing WiFi country-based regional restrictions. */
-typedef struct {
-    char                  cc[3];   /**< country code string */
-    uint8_t               schan;   /**< start channel */
-    uint8_t               nchan;   /**< total channel number */
-    int8_t                max_tx_power;   /**< This field is used for getting WiFi maximum transmitting power, call esp_wifi_set_max_tx_power to set the maximum transmitting power. */
-    wifi_country_policy_t policy;  /**< country policy */
-} wifi_country_t;
-
-typedef enum {
-    WIFI_AUTH_OPEN = 0,         /**< authenticate mode : open */
-    WIFI_AUTH_WEP,              /**< authenticate mode : WEP */
-    WIFI_AUTH_WPA_PSK,          /**< authenticate mode : WPA_PSK */
-    WIFI_AUTH_WPA2_PSK,         /**< authenticate mode : WPA2_PSK */
-    WIFI_AUTH_WPA_WPA2_PSK,     /**< authenticate mode : WPA_WPA2_PSK */
-    WIFI_AUTH_WPA2_ENTERPRISE,  /**< authenticate mode : WPA2_ENTERPRISE */
-    WIFI_AUTH_MAX
-} wifi_auth_mode_t;
-
-typedef enum {
-    WIFI_REASON_UNSPECIFIED              = 1,
-    WIFI_REASON_AUTH_EXPIRE              = 2,
-    WIFI_REASON_AUTH_LEAVE               = 3,
-    WIFI_REASON_ASSOC_EXPIRE             = 4,
-    WIFI_REASON_ASSOC_TOOMANY            = 5,
-    WIFI_REASON_NOT_AUTHED               = 6,
-    WIFI_REASON_NOT_ASSOCED              = 7,
-    WIFI_REASON_ASSOC_LEAVE              = 8,
-    WIFI_REASON_ASSOC_NOT_AUTHED         = 9,
-    WIFI_REASON_DISASSOC_PWRCAP_BAD      = 10,
-    WIFI_REASON_DISASSOC_SUPCHAN_BAD     = 11,
-    WIFI_REASON_IE_INVALID               = 13,
-    WIFI_REASON_MIC_FAILURE              = 14,
-    WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT   = 15,
-    WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT = 16,
-    WIFI_REASON_IE_IN_4WAY_DIFFERS       = 17,
-    WIFI_REASON_GROUP_CIPHER_INVALID     = 18,
-    WIFI_REASON_PAIRWISE_CIPHER_INVALID  = 19,
-    WIFI_REASON_AKMP_INVALID             = 20,
-    WIFI_REASON_UNSUPP_RSN_IE_VERSION    = 21,
-    WIFI_REASON_INVALID_RSN_IE_CAP       = 22,
-    WIFI_REASON_802_1X_AUTH_FAILED       = 23,
-    WIFI_REASON_CIPHER_SUITE_REJECTED    = 24,
-
-    WIFI_REASON_BEACON_TIMEOUT           = 200,
-    WIFI_REASON_NO_AP_FOUND              = 201,
-    WIFI_REASON_AUTH_FAIL                = 202,
-    WIFI_REASON_ASSOC_FAIL               = 203,
-    WIFI_REASON_HANDSHAKE_TIMEOUT        = 204,
-    WIFI_REASON_CONNECTION_FAIL          = 205,
-    WIFI_REASON_AP_TSF_RESET             = 206,
-} wifi_err_reason_t;
-
-typedef enum {
-    WIFI_SECOND_CHAN_NONE = 0,  /**< the channel width is HT20 */
-    WIFI_SECOND_CHAN_ABOVE,     /**< the channel width is HT40 and the secondary channel is above the primary channel */
-    WIFI_SECOND_CHAN_BELOW,     /**< the channel width is HT40 and the secondary channel is below the primary channel */
-} wifi_second_chan_t;
-
-typedef enum {
-    WIFI_SCAN_TYPE_ACTIVE = 0,  /**< active scan */
-    WIFI_SCAN_TYPE_PASSIVE,     /**< passive scan */
-} wifi_scan_type_t;
-
-/** @brief Range of active scan times per channel */
-typedef struct {
-    uint32_t min;  /**< minimum active scan time per channel, units: millisecond */
-    uint32_t max;  /**< maximum active scan time per channel, units: millisecond, values above 1500ms may
-                                          cause station to disconnect from AP and are not recommended.  */
-} wifi_active_scan_time_t;
-
-/** @brief Aggregate of active & passive scan time per channel */
-typedef struct {
-    wifi_active_scan_time_t active;  /**< active scan time per channel, units: millisecond. */
-    uint32_t passive;                /**< passive scan time per channel, units: millisecond, values above 1500ms may
-                                          cause station to disconnect from AP and are not recommended. */
-} wifi_scan_time_t;
-
-/** @brief Parameters for an SSID scan. */
-typedef struct {
-    uint8_t *ssid;               /**< SSID of AP */
-    uint8_t *bssid;              /**< MAC address of AP */
-    uint8_t channel;             /**< channel, scan the specific channel */
-    bool show_hidden;            /**< enable to scan AP whose SSID is hidden */
-    wifi_scan_type_t scan_type;  /**< scan type, active or passive */
-    wifi_scan_time_t scan_time;  /**< scan time per channel */
-} wifi_scan_config_t;
-
-typedef enum {
-    WIFI_CIPHER_TYPE_NONE = 0,   /**< the cipher type is none */
-    WIFI_CIPHER_TYPE_WEP40,      /**< the cipher type is WEP40 */
-    WIFI_CIPHER_TYPE_WEP104,     /**< the cipher type is WEP104 */
-    WIFI_CIPHER_TYPE_TKIP,       /**< the cipher type is TKIP */
-    WIFI_CIPHER_TYPE_CCMP,       /**< the cipher type is CCMP */
-    WIFI_CIPHER_TYPE_TKIP_CCMP,  /**< the cipher type is TKIP and CCMP */
-    WIFI_CIPHER_TYPE_UNKNOWN,    /**< the cipher type is unknown */
-} wifi_cipher_type_t;
-
-/**
-  * @brief WiFi antenna
-  *
-  */
-typedef enum {
-    WIFI_ANT_ANT0,          /**< WiFi antenna 0 */
-    WIFI_ANT_ANT1,          /**< WiFi antenna 1 */
-    WIFI_ANT_MAX,           /**< Invalid WiFi antenna */
-} wifi_ant_t;
-
-/** @brief Description of a WiFi AP */
-typedef struct {
-    uint8_t bssid[6];                     /**< MAC address of AP */
-    uint8_t ssid[33];                     /**< SSID of AP */
-    uint8_t primary;                      /**< channel of AP */
-    wifi_second_chan_t second;            /**< secondary channel of AP */
-    int8_t  rssi;                         /**< signal strength of AP */
-    wifi_auth_mode_t authmode;            /**< authmode of AP */
-    wifi_cipher_type_t pairwise_cipher;   /**< pairwise cipher of AP */
-    wifi_cipher_type_t group_cipher;      /**< group cipher of AP */
-    wifi_ant_t ant;                       /**< antenna used to receive beacon from AP */
-    uint32_t phy_11b:1;                   /**< bit: 0 flag to identify if 11b mode is enabled or not */
-    uint32_t phy_11g:1;                   /**< bit: 1 flag to identify if 11g mode is enabled or not */
-    uint32_t phy_11n:1;                   /**< bit: 2 flag to identify if 11n mode is enabled or not */
-    uint32_t phy_lr:1;                    /**< bit: 3 flag to identify if low rate is enabled or not */
-    uint32_t wps:1;                       /**< bit: 4 flag to identify if WPS is supported or not */
-    uint32_t reserved:27;                 /**< bit: 5..31 reserved */
-    wifi_country_t country;               /**< country information of AP */
-} wifi_ap_record_t;
-
-typedef enum {
-    WIFI_FAST_SCAN = 0,                   /**< Do fast scan, scan will end after find SSID match AP */
-    WIFI_ALL_CHANNEL_SCAN,                /**< All channel scan, scan will end after scan all the channel */
-}wifi_scan_method_t;
-
-typedef enum {
-    WIFI_CONNECT_AP_BY_SIGNAL = 0,        /**< Sort match AP in scan list by RSSI */
-    WIFI_CONNECT_AP_BY_SECURITY,          /**< Sort match AP in scan list by security mode */
-}wifi_sort_method_t;
-
-/** @brief Structure describing parameters for a WiFi fast scan */
-typedef struct {
-    int8_t              rssi;             /**< The minimum rssi to accept in the fast scan mode */
-    wifi_auth_mode_t    authmode;         /**< The weakest authmode to accept in the fast scan mode */
-}wifi_fast_scan_threshold_t;
-
-typedef wifi_fast_scan_threshold_t wifi_scan_threshold_t;    /**< wifi_fast_scan_threshold_t only used in fast scan mode once, now it enabled in all channel scan, the wifi_fast_scan_threshold_t will be remove in version 4.0 */
-
-typedef enum {
-    WIFI_PS_NONE,        /**< No power save */
-    WIFI_PS_MIN_MODEM,   /**< Minimum modem power saving. In this mode, station wakes up to receive beacon every DTIM period */
-    WIFI_PS_MAX_MODEM,   /**< Maximum modem power saving. In this mode, interval to receive beacons is determined by the listen_interval parameter in wifi_sta_config_t */
-} wifi_ps_type_t;
-
-#define WIFI_PS_MODEM WIFI_PS_MIN_MODEM /**< @deprecated Use WIFI_PS_MIN_MODEM or WIFI_PS_MAX_MODEM instead */
-
-#define WIFI_PROTOCOL_11B         1
-#define WIFI_PROTOCOL_11G         2
-#define WIFI_PROTOCOL_11N         4
-#define WIFI_PROTOCOL_LR          8
-
-typedef enum {
-    WIFI_BW_HT20 = 1, /* Bandwidth is HT20 */
-    WIFI_BW_HT40,     /* Bandwidth is HT40 */
-} wifi_bandwidth_t;
-
-/** @brief Soft-AP configuration settings for the ESP32 */
-typedef struct {
-    uint8_t ssid[32];           /**< SSID of ESP32 soft-AP */
-    uint8_t password[64];       /**< Password of ESP32 soft-AP */
-    uint8_t ssid_len;           /**< Length of SSID. If softap_config.ssid_len==0, check the SSID until there is a termination character; otherwise, set the SSID length according to softap_config.ssid_len. */
-    uint8_t channel;            /**< Channel of ESP32 soft-AP */
-    wifi_auth_mode_t authmode;  /**< Auth mode of ESP32 soft-AP. Do not support AUTH_WEP in soft-AP mode */
-    uint8_t ssid_hidden;        /**< Broadcast SSID or not, default 0, broadcast the SSID */
-    uint8_t max_connection;     /**< Max number of stations allowed to connect in, default 4, max 10 */
-    uint16_t beacon_interval;   /**< Beacon interval, 100 ~ 60000 ms, default 100 ms */
-} wifi_ap_config_t;
-
-/** @brief STA configuration settings for the ESP32 */
-typedef struct {
-    uint8_t ssid[32];      /**< SSID of target AP*/
-    uint8_t password[64];  /**< password of target AP*/
-    wifi_scan_method_t scan_method;    /**< do all channel scan or fast scan */
-    bool bssid_set;        /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
-    uint8_t bssid[6];     /**< MAC address of target AP*/
-    uint8_t channel;       /**< channel of target AP. Set to 1~13 to scan starting from the specified channel before connecting to AP. If the channel of AP is unknown, set it to 0.*/
-    uint16_t listen_interval;   /**< Listen interval for ESP32 station to receive beacon when WIFI_PS_MAX_MODEM is set. Units: AP beacon intervals. Defaults to 3 if set to 0. */
-    wifi_sort_method_t sort_method;    /**< sort the connect AP in the list by rssi or security mode */
-    wifi_scan_threshold_t  threshold;     /**< When scan_method is set, only APs which have an auth mode that is more secure than the selected auth mode and a signal stronger than the minimum RSSI will be used. */
-} wifi_sta_config_t;
-
-/** @brief Configuration data for ESP32 AP or STA.
- *
- * The usage of this union (for ap or sta configuration) is determined by the accompanying
- * interface argument passed to esp_wifi_set_config() or esp_wifi_get_config()
- *
- */
-typedef union {
-    wifi_ap_config_t  ap;  /**< configuration of AP */
-    wifi_sta_config_t sta; /**< configuration of STA */
-} wifi_config_t;
-
-/** @brief Description of STA associated with AP */
-typedef struct {
-    uint8_t mac[6];  /**< mac address */
-    int8_t  rssi;    /**< current average rssi of sta connected */
-    uint32_t phy_11b:1;      /**< bit: 0 flag to identify if 11b mode is enabled or not */
-    uint32_t phy_11g:1;      /**< bit: 1 flag to identify if 11g mode is enabled or not */
-    uint32_t phy_11n:1;      /**< bit: 2 flag to identify if 11n mode is enabled or not */
-    uint32_t phy_lr:1;       /**< bit: 3 flag to identify if low rate is enabled or not */
-    uint32_t reserved:28;    /**< bit: 4..31 reserved */
-} wifi_sta_info_t;
-
-#define ESP_WIFI_MAX_CONN_NUM  (10)       /**< max number of stations which can connect to ESP32 soft-AP */
-
-/** @brief List of stations associated with the ESP32 Soft-AP */
-typedef struct {
-    wifi_sta_info_t sta[ESP_WIFI_MAX_CONN_NUM]; /**< station list */
-    int       num; /**< number of stations in the list (other entries are invalid) */
-} wifi_sta_list_t;
-
-typedef enum {
-    WIFI_STORAGE_FLASH,  /**< all configuration will strore in both memory and flash */
-    WIFI_STORAGE_RAM,    /**< all configuration will only store in the memory */
-} wifi_storage_t;
-
-/**
-  * @brief     Vendor Information Element type
-  *
-  * Determines the frame type that the IE will be associated with.
-  */
-typedef enum {
-    WIFI_VND_IE_TYPE_BEACON,
-    WIFI_VND_IE_TYPE_PROBE_REQ,
-    WIFI_VND_IE_TYPE_PROBE_RESP,
-    WIFI_VND_IE_TYPE_ASSOC_REQ,
-    WIFI_VND_IE_TYPE_ASSOC_RESP,
-} wifi_vendor_ie_type_t;
-
-/**
-  * @brief     Vendor Information Element index
-  *
-  * Each IE type can have up to two associated vendor ID elements.
-  */
-typedef enum {
-    WIFI_VND_IE_ID_0,
-    WIFI_VND_IE_ID_1,
-} wifi_vendor_ie_id_t;
-
-#define WIFI_VENDOR_IE_ELEMENT_ID 0xDD
-
-/**
- * @brief Vendor Information Element header
- *
- * The first bytes of the Information Element will match this header. Payload follows.
- */
-typedef struct {
-    uint8_t element_id;      /**< Should be set to WIFI_VENDOR_IE_ELEMENT_ID (0xDD) */
-    uint8_t length;          /**< Length of all bytes in the element data following this field. Minimum 4. */
-    uint8_t vendor_oui[3];   /**< Vendor identifier (OUI). */
-    uint8_t vendor_oui_type; /**< Vendor-specific OUI type. */
-    uint8_t payload[0];      /**< Payload. Length is equal to value in 'length' field, minus 4. */
-} vendor_ie_data_t;
-
-/** @brief Received packet radio metadata header, this is the common header at the beginning of all promiscuous mode RX callback buffers */
-typedef struct {
-    signed rssi:8;                /**< Received Signal Strength Indicator(RSSI) of packet. unit: dBm */
-    unsigned rate:5;              /**< PHY rate encoding of the packet. Only valid for non HT(11bg) packet */
-    unsigned :1;                  /**< reserve */
-    unsigned sig_mode:2;          /**< 0: non HT(11bg) packet; 1: HT(11n) packet; 3: VHT(11ac) packet */
-    unsigned :16;                 /**< reserve */
-    unsigned mcs:7;               /**< Modulation Coding Scheme. If is HT(11n) packet, shows the modulation, range from 0 to 76(MSC0 ~ MCS76) */
-    unsigned cwb:1;               /**< Channel Bandwidth of the packet. 0: 20MHz; 1: 40MHz */
-    unsigned :16;                 /**< reserve */
-    unsigned smoothing:1;         /**< reserve */
-    unsigned not_sounding:1;      /**< reserve */
-    unsigned :1;                  /**< reserve */
-    unsigned aggregation:1;       /**< Aggregation. 0: MPDU packet; 1: AMPDU packet */
-    unsigned stbc:2;              /**< Space Time Block Code(STBC). 0: non STBC packet; 1: STBC packet */
-    unsigned fec_coding:1;        /**< Flag is set for 11n packets which are LDPC */
-    unsigned sgi:1;               /**< Short Guide Interval(SGI). 0: Long GI; 1: Short GI */
-    signed noise_floor:8;         /**< noise floor of Radio Frequency Module(RF). unit: 0.25dBm*/
-    unsigned ampdu_cnt:8;         /**< ampdu cnt */
-    unsigned channel:4;           /**< primary channel on which this packet is received */
-    unsigned secondary_channel:4; /**< secondary channel on which this packet is received. 0: none; 1: above; 2: below */
-    unsigned :8;                  /**< reserve */
-    unsigned timestamp:32;        /**< timestamp. The local time when this packet is received. It is precise only if modem sleep or light sleep is not enabled. unit: microsecond */
-    unsigned :32;                 /**< reserve */
-    unsigned :31;                 /**< reserve */
-    unsigned ant:1;               /**< antenna number from which this packet is received. 0: WiFi antenna 0; 1: WiFi antenna 1 */
-    unsigned sig_len:12;          /**< length of packet including Frame Check Sequence(FCS) */
-    unsigned :12;                 /**< reserve */
-    unsigned rx_state:8;          /**< state of the packet. 0: no error; others: error numbers which are not public */
-} wifi_pkt_rx_ctrl_t;
-
-/** @brief Payload passed to 'buf' parameter of promiscuous mode RX callback.
- */
-typedef struct {
-    wifi_pkt_rx_ctrl_t rx_ctrl; /**< metadata header */
-    uint8_t payload[0];       /**< Data or management payload. Length of payload is described by rx_ctrl.sig_len. Type of content determined by packet type argument of callback. */
-} wifi_promiscuous_pkt_t;
-
-/**
-  * @brief Promiscuous frame type
-  *
-  * Passed to promiscuous mode RX callback to indicate the type of parameter in the buffer.
-  *
-  */
-typedef enum {
-    WIFI_PKT_MGMT,  /**< Management frame, indicates 'buf' argument is wifi_promiscuous_pkt_t */
-    WIFI_PKT_CTRL,  /**< Control frame, indicates 'buf' argument is wifi_promiscuous_pkt_t */
-    WIFI_PKT_DATA,  /**< Data frame, indiciates 'buf' argument is wifi_promiscuous_pkt_t */
-    WIFI_PKT_MISC,  /**< Other type, such as MIMO etc. 'buf' argument is wifi_promiscuous_pkt_t but the payload is zero length. */
-} wifi_promiscuous_pkt_type_t;
-
-
-#define WIFI_PROMIS_FILTER_MASK_ALL         (0xFFFFFFFF)  /**< filter all packets */
-#define WIFI_PROMIS_FILTER_MASK_MGMT        (1)           /**< filter the packets with type of WIFI_PKT_MGMT */
-#define WIFI_PROMIS_FILTER_MASK_CTRL        (1<<1)        /**< filter the packets with type of WIFI_PKT_CTRL */
-#define WIFI_PROMIS_FILTER_MASK_DATA        (1<<2)        /**< filter the packets with type of WIFI_PKT_DATA */
-#define WIFI_PROMIS_FILTER_MASK_MISC        (1<<3)        /**< filter the packets with type of WIFI_PKT_MISC */
-#define WIFI_PROMIS_FILTER_MASK_DATA_MPDU   (1<<4)        /**< filter the MPDU which is a kind of WIFI_PKT_DATA */
-#define WIFI_PROMIS_FILTER_MASK_DATA_AMPDU  (1<<5)        /**< filter the AMPDU which is a kind of WIFI_PKT_DATA */
-
-#define WIFI_PROMIS_CTRL_FILTER_MASK_ALL         (0xFF800000)  /**< filter all control packets */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_WRAPPER     (1<<23)       /**< filter the control packets with subtype of Control Wrapper */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_BAR         (1<<24)       /**< filter the control packets with subtype of Block Ack Request */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_BA          (1<<25)       /**< filter the control packets with subtype of Block Ack */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_PSPOLL      (1<<26)       /**< filter the control packets with subtype of PS-Poll */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_RTS         (1<<27)       /**< filter the control packets with subtype of RTS */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_CTS         (1<<28)       /**< filter the control packets with subtype of CTS */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_ACK         (1<<29)       /**< filter the control packets with subtype of ACK */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_CFEND       (1<<30)       /**< filter the control packets with subtype of CF-END */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_CFENDACK    (1<<31)       /**< filter the control packets with subtype of CF-END+CF-ACK */
-
-/** @brief Mask for filtering different packet types in promiscuous mode. */
-typedef struct {
-    uint32_t filter_mask; /**< OR of one or more filter values WIFI_PROMIS_FILTER_* */
-} wifi_promiscuous_filter_t;
-
-#define WIFI_EVENT_MASK_ALL                 (0xFFFFFFFF)  /**< mask all WiFi events */
-#define WIFI_EVENT_MASK_NONE                (0)           /**< mask none of the WiFi events */
-#define WIFI_EVENT_MASK_AP_PROBEREQRECVED   (BIT(0))      /**< mask SYSTEM_EVENT_AP_PROBEREQRECVED event */
-
-/**
-  * @brief Channel state information(CSI) configuration type
-  *
-  */
-typedef struct {
-    bool lltf_en;           /**< enable to receive legacy long training field(lltf) data. Default enabled */
-    bool htltf_en;          /**< enable to receive HT long training field(htltf) data. Default enabled */
-    bool stbc_htltf2_en;    /**< enable to receive space time block code HT long training field(stbc-htltf2) data. Default enabled */
-    bool ltf_merge_en;      /**< enable to generate htlft data by averaging lltf and ht_ltf data when receiving HT packet. Otherwise, use ht_ltf data directly. Default enabled */
-    bool channel_filter_en; /**< enable to turn on channel filter to smooth adjacent sub-carrier. Disable it to keep independence of adjacent sub-carrier. Default enabled */
-    bool manu_scale;        /**< manually scale the CSI data by left shifting or automatically scale the CSI data. If set true, please set the shift bits. false: automatically. true: manually. Default false */ 
-    uint8_t shift;          /**< manually left shift bits of the scale of the CSI data. The range of the left shift bits is 0~15 */
-} wifi_csi_config_t;
-
-/**
-  * @brief CSI data type
-  *
-  */
-typedef struct {
-    wifi_pkt_rx_ctrl_t rx_ctrl;/**< received packet radio metadata header of the CSI data */
-    uint8_t mac[6];            /**< source MAC address of the CSI data */
-    bool first_word_invalid;   /**< first four bytes of the CSI data is invalid or not */
-    int8_t *buf;               /**< buffer of CSI data */
-    uint16_t len;              /**< length of CSI data */
-} wifi_csi_info_t;
-
-/**
-  * @brief WiFi GPIO configuration for antenna selection
-  *
-  */
-typedef struct {
-    uint8_t gpio_select: 1,           /**< Whether this GPIO is connected to external antenna switch */
-            gpio_num: 7;              /**< The GPIO number that connects to external antenna switch */
-} wifi_ant_gpio_t;
-
-/**
-  * @brief WiFi GPIOs configuration for antenna selection
-  *
-  */
-typedef struct {
-    wifi_ant_gpio_t  gpio_cfg[4];  /**< The configurations of GPIOs that connect to external antenna switch */
-} wifi_ant_gpio_config_t;
-
-/**
-  * @brief WiFi antenna mode
-  *
-  */
-typedef enum {
-    WIFI_ANT_MODE_ANT0,          /**< Enable WiFi antenna 0 only */
-    WIFI_ANT_MODE_ANT1,          /**< Enable WiFi antenna 1 only */
-    WIFI_ANT_MODE_AUTO,          /**< Enable WiFi antenna 0 and 1, automatically select an antenna */
-    WIFI_ANT_MODE_MAX,           /**< Invalid WiFi enabled antenna */
-} wifi_ant_mode_t;
-
-/**
-  * @brief WiFi antenna configuration
-  *
-  */
-typedef struct {
-    wifi_ant_mode_t rx_ant_mode;          /**< WiFi antenna mode for receiving */
-    wifi_ant_t      rx_ant_default;       /**< Default antenna mode for receiving, it's ignored if rx_ant_mode is not WIFI_ANT_MODE_AUTO */
-    wifi_ant_mode_t tx_ant_mode;          /**< WiFi antenna mode for transmission, it can be set to WIFI_ANT_MODE_AUTO only if rx_ant_mode is set to WIFI_ANT_MODE_AUTO */
-    uint8_t         enabled_ant0: 4,      /**< Index (in antenna GPIO configuration) of enabled WIFI_ANT_MODE_ANT0 */
-                    enabled_ant1: 4;      /**< Index (in antenna GPIO configuration) of enabled WIFI_ANT_MODE_ANT1 */
-} wifi_ant_config_t;
-
-/**
-  * @brief WiFi PHY rate encodings
-  *
-  */
-typedef enum {
-    WIFI_PHY_RATE_1M_L      = 0x00, /**< 1 Mbps with long preamble */
-    WIFI_PHY_RATE_2M_L      = 0x01, /**< 2 Mbps with long preamble */
-    WIFI_PHY_RATE_5M_L      = 0x02, /**< 5.5 Mbps with long preamble */
-    WIFI_PHY_RATE_11M_L     = 0x03, /**< 11 Mbps with long preamble */
-    WIFI_PHY_RATE_2M_S      = 0x05, /**< 2 Mbps with short preamble */
-    WIFI_PHY_RATE_5M_S      = 0x06, /**< 5.5 Mbps with short preamble */
-    WIFI_PHY_RATE_11M_S     = 0x07, /**< 11 Mbps with short preamble */
-    WIFI_PHY_RATE_48M       = 0x08, /**< 48 Mbps */
-    WIFI_PHY_RATE_24M       = 0x09, /**< 24 Mbps */
-    WIFI_PHY_RATE_12M       = 0x0A, /**< 12 Mbps */
-    WIFI_PHY_RATE_6M        = 0x0B, /**< 6 Mbps */
-    WIFI_PHY_RATE_54M       = 0x0C, /**< 54 Mbps */
-    WIFI_PHY_RATE_36M       = 0x0D, /**< 36 Mbps */
-    WIFI_PHY_RATE_18M       = 0x0E, /**< 18 Mbps */
-    WIFI_PHY_RATE_9M        = 0x0F, /**< 9 Mbps */
-    WIFI_PHY_RATE_MCS0_LGI  = 0x10, /**< MCS0 with long GI, 6.5 Mbps for 20MHz, 13.5 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS1_LGI  = 0x11, /**< MCS1 with long GI, 13 Mbps for 20MHz, 27 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS2_LGI  = 0x12, /**< MCS2 with long GI, 19.5 Mbps for 20MHz, 40.5 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS3_LGI  = 0x13, /**< MCS3 with long GI, 26 Mbps for 20MHz, 54 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS4_LGI  = 0x14, /**< MCS4 with long GI, 39 Mbps for 20MHz, 81 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS5_LGI  = 0x15, /**< MCS5 with long GI, 52 Mbps for 20MHz, 108 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS6_LGI  = 0x16, /**< MCS6 with long GI, 58.5 Mbps for 20MHz, 121.5 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS7_LGI  = 0x17, /**< MCS7 with long GI, 65 Mbps for 20MHz, 135 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS0_SGI  = 0x18, /**< MCS0 with short GI, 7.2 Mbps for 20MHz, 15 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS1_SGI  = 0x19, /**< MCS1 with short GI, 14.4 Mbps for 20MHz, 30 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS2_SGI  = 0x1A, /**< MCS2 with short GI, 21.7 Mbps for 20MHz, 45 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS3_SGI  = 0x1B, /**< MCS3 with short GI, 28.9 Mbps for 20MHz, 60 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS4_SGI  = 0x1C, /**< MCS4 with short GI, 43.3 Mbps for 20MHz, 90 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS5_SGI  = 0x1D, /**< MCS5 with short GI, 57.8 Mbps for 20MHz, 120 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS6_SGI  = 0x1E, /**< MCS6 with short GI, 65 Mbps for 20MHz, 135 Mbps for 40MHz */
-    WIFI_PHY_RATE_MCS7_SGI  = 0x1F, /**< MCS7 with short GI, 72.2 Mbps for 20MHz, 150 Mbps for 40MHz */
-    WIFI_PHY_RATE_LORA_250K = 0x29, /**< 250 Kbps */
-    WIFI_PHY_RATE_LORA_500K = 0x2A, /**< 500 Kbps */
-    WIFI_PHY_RATE_MAX,
-} wifi_phy_rate_t;
-
-/** 
-  * @brief WiFi ioctl command type
-  *
-  */
-typedef enum {
-    WIFI_IOCTL_SET_STA_HT2040_COEX = 1, /**< Set the configuration of STA's HT2040 coexist management */
-    WIFI_IOCTL_GET_STA_HT2040_COEX,     /**< Get the configuration of STA's HT2040 coexist management */
-    WIFI_IOCTL_MAX,
-} wifi_ioctl_cmd_t;
-
-/** 
- * @brief Configuration for STA's HT2040 coexist management
- *
- */
-typedef struct {
-    int enable;                         /**< Indicate whether STA's HT2040 coexist management is enabled or not */
-} wifi_ht2040_coex_t;
-
-/** 
-  * @brief Configuration for WiFi ioctl
-  *
-  */
-typedef struct {
-    union {
-        wifi_ht2040_coex_t ht2040_coex; /**< Configuration of STA's HT2040 coexist management */
-    } data;                             /**< Configuration of ioctl command */
-} wifi_ioctl_config_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_WIFI_TYPES_H__ */
diff --git a/tools/sdk/include/esp32/esp_wpa2.h b/tools/sdk/include/esp32/esp_wpa2.h
deleted file mode 100644
index 1b2dfa51038..00000000000
--- a/tools/sdk/include/esp32/esp_wpa2.h
+++ /dev/null
@@ -1,208 +0,0 @@
-// Hardware crypto support Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef ESP_WPA2_H
-#define ESP_WPA2_H
-
-#include <stdbool.h>
-
-#include "esp_err.h"
-#include "esp_wifi_crypto_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern const wpa2_crypto_funcs_t g_wifi_default_wpa2_crypto_funcs;
-
-typedef struct {
-    const wpa2_crypto_funcs_t *crypto_funcs;
-}esp_wpa2_config_t;
-
-#define WPA2_CONFIG_INIT_DEFAULT() { \
-    .crypto_funcs = &g_wifi_default_wpa2_crypto_funcs \
-}
-
-/**
-  * @brief  Enable wpa2 enterprise authentication.
-  *
-  * @attention 1. wpa2 enterprise authentication can only be used when ESP32 station is enabled.
-  * @attention 2. wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
-  *
-  * @return
-  *    - ESP_OK: succeed.
-  *    - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
-  */
-esp_err_t esp_wifi_sta_wpa2_ent_enable(const esp_wpa2_config_t *config);
-
-/**
-  * @brief  Disable wpa2 enterprise authentication.
-  *
-  * @attention 1. wpa2 enterprise authentication can only be used when ESP32 station is enabled.
-  * @attention 2. wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
-  *
-  * @return
-  *    - ESP_OK: succeed.
-  */
-esp_err_t esp_wifi_sta_wpa2_ent_disable(void);
-
-/**
-  * @brief  Set identity for PEAP/TTLS method.
-  *
-  * @attention The API only passes the parameter identity to the global pointer variable in wpa2 enterprise module.
-  *
-  * @param  identity: point to address where stores the identity;
-  * @param  len: length of identity, limited to 1~127
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_INVALID_ARG: fail(len <= 0 or len >= 128)
-  *    - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
-  */
-esp_err_t esp_wifi_sta_wpa2_ent_set_identity(const unsigned char *identity, int len);
-
-/**
-  * @brief  Clear identity for PEAP/TTLS method.
-  */
-void esp_wifi_sta_wpa2_ent_clear_identity(void);
-
-/**
-  * @brief  Set username for PEAP/TTLS method.
-  *
-  * @attention The API only passes the parameter username to the global pointer variable in wpa2 enterprise module.
-  *
-  * @param  username: point to address where stores the username;
-  * @param  len: length of username, limited to 1~127
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_INVALID_ARG: fail(len <= 0 or len >= 128)
-  *    - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
-  */
-esp_err_t esp_wifi_sta_wpa2_ent_set_username(const unsigned char *username, int len);
-
-/**
-  * @brief  Clear username for PEAP/TTLS method.
-  */
-void esp_wifi_sta_wpa2_ent_clear_username(void);
-
-/**
-  * @brief  Set password for PEAP/TTLS method..
-  *
-  * @attention The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
-  *
-  * @param  password: point to address where stores the password;
-  * @param  len: length of password(len > 0)
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_INVALID_ARG: fail(len <= 0)
-  *    - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
-  */
-esp_err_t esp_wifi_sta_wpa2_ent_set_password(const unsigned char *password, int len);
-
-/**
-  * @brief  Clear password for PEAP/TTLS method..
-  */
-void esp_wifi_sta_wpa2_ent_clear_password(void);
-
-/**
-  * @brief  Set new password for MSCHAPv2 method..
-  *
-  * @attention 1. The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
-  * @attention 2. The new password is used to substitute the old password when eap-mschapv2 failure request message with error code ERROR_PASSWD_EXPIRED is received.
-  *
-  * @param  new_password: point to address where stores the password;
-  * @param  len: length of password
-  *
-  * @return
-  *    - ESP_OK: succeed
-  *    - ESP_ERR_INVALID_ARG: fail(len <= 0)
-  *    - ESP_ERR_NO_MEM: fail(internal memory malloc fail)
-  */
-
-esp_err_t esp_wifi_sta_wpa2_ent_set_new_password(const unsigned char *new_password, int len);
-
-/**
-  * @brief  Clear new password for MSCHAPv2 method..
-  */
-void esp_wifi_sta_wpa2_ent_clear_new_password(void);
-
-/**
-  * @brief  Set CA certificate for PEAP/TTLS method.
-  *
-  * @attention 1. The API only passes the parameter ca_cert to the global pointer variable in wpa2 enterprise module.
-  * @attention 2. The ca_cert should be zero terminated.
-  *
-  * @param  ca_cert: point to address where stores the CA certificate;
-  * @param  ca_cert_len: length of ca_cert
-  *
-  * @return
-  *    - ESP_OK: succeed
-  */
-esp_err_t esp_wifi_sta_wpa2_ent_set_ca_cert(const unsigned char *ca_cert, int ca_cert_len);
-
-/**
-  * @brief  Clear CA certificate for PEAP/TTLS method.
-  */
-void esp_wifi_sta_wpa2_ent_clear_ca_cert(void);
-
-/**
-  * @brief  Set client certificate and key.
-  *
-  * @attention 1. The API only passes the parameter client_cert, private_key and private_key_passwd to the global pointer variable in wpa2 enterprise module.
-  * @attention 2. The client_cert, private_key and private_key_passwd should be zero terminated.
-  *
-  * @param  client_cert: point to address where stores the client certificate;
-  * @param  client_cert_len: length of client certificate;
-  * @param  private_key: point to address where stores the private key;
-  * @param  private_key_len: length of private key, limited to 1~2048;
-  * @param  private_key_password: point to address where stores the private key password;
-  * @param  private_key_password_len: length of private key password;
-  *
-  * @return
-  *    - ESP_OK: succeed
-  */
-esp_err_t esp_wifi_sta_wpa2_ent_set_cert_key(const unsigned char *client_cert, int client_cert_len, const unsigned char *private_key, int private_key_len, const unsigned char *private_key_passwd, int private_key_passwd_len);
-
-/**
-  * @brief  Clear client certificate and key.
-  */
-void esp_wifi_sta_wpa2_ent_clear_cert_key(void);
-
-/**
-  * @brief  Set wpa2 enterprise certs time check(disable or not).
-  *
-  * @param  true: disable wpa2 enterprise certs time check
-  * @param  false: enable wpa2 enterprise certs time check
-  *
-  * @return
-  *    - ESP_OK: succeed
-  */
-esp_err_t esp_wifi_sta_wpa2_ent_set_disable_time_check(bool disable);
-
-/**
-  * @brief  Get wpa2 enterprise certs time check(disable or not).
-  *
-  * @param  disable: store disable value
-  *
-  * @return
-  *    - ESP_OK: succeed
-  */
-esp_err_t esp_wifi_sta_wpa2_ent_get_disable_time_check(bool *disable);
-
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/tools/sdk/include/esp32/esp_wps.h b/tools/sdk/include/esp32/esp_wps.h
deleted file mode 100644
index cb5e9327921..00000000000
--- a/tools/sdk/include/esp32/esp_wps.h
+++ /dev/null
@@ -1,151 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_WPS_H__
-#define __ESP_WPS_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "esp_err.h"
-#include "esp_wifi_crypto_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup WiFi_APIs WiFi Related APIs
-  * @brief WiFi APIs
-  */
-
-/** @addtogroup WiFi_APIs
-  * @{
-  */
-
-/** \defgroup WPS_APIs  WPS APIs
-  * @brief ESP32 WPS APIs
-  *
-  * WPS can only be used when ESP32 station is enabled.
-  *
-  */
-
-/** @addtogroup WPS_APIs
-  * @{
-  */
-
-#define ESP_ERR_WIFI_REGISTRAR   (ESP_ERR_WIFI_BASE + 51)  /*!< WPS registrar is not supported */
-#define ESP_ERR_WIFI_WPS_TYPE    (ESP_ERR_WIFI_BASE + 52)  /*!< WPS type error */
-#define ESP_ERR_WIFI_WPS_SM      (ESP_ERR_WIFI_BASE + 53)  /*!< WPS state machine is not initialized */
-
-typedef enum wps_type {
-    WPS_TYPE_DISABLE = 0,
-    WPS_TYPE_PBC,
-    WPS_TYPE_PIN,
-    WPS_TYPE_MAX,
-} wps_type_t;
-
-extern const wps_crypto_funcs_t g_wifi_default_wps_crypto_funcs;
-
-#define WPS_MAX_MANUFACTURER_LEN 65
-#define WPS_MAX_MODEL_NUMBER_LEN 33
-#define WPS_MAX_MODEL_NAME_LEN   33
-#define WPS_MAX_DEVICE_NAME_LEN  33
-
-typedef struct {
-    char manufacturer[WPS_MAX_MANUFACTURER_LEN]; /*!< Manufacturer, null-terminated string. The default manufcturer is used if the string is empty */
-    char model_number[WPS_MAX_MODEL_NUMBER_LEN]; /*!< Model number, null-terminated string. The default model number is used if the string is empty */
-    char model_name[WPS_MAX_MODEL_NAME_LEN];     /*!< Model name, null-terminated string. The default model name is used if the string is empty */
-    char device_name[WPS_MAX_DEVICE_NAME_LEN];   /*!< Device name, null-terminated string. The default device name is used if the string is empty */
-} wps_factory_information_t;
-
-typedef struct {
-    wps_type_t wps_type;
-    const wps_crypto_funcs_t *crypto_funcs;
-    wps_factory_information_t factory_info;
-} esp_wps_config_t;
-
-/* C & C++ compilers have different rules about C99-style named initializers */
-#ifdef __cplusplus
-#define WPS_AGG(X) { X }
-#else
-#define WPS_AGG(X) X
-#endif
-
-#define WPS_CONFIG_INIT_DEFAULT(type) { \
-    .wps_type = type, \
-    .crypto_funcs = &g_wifi_default_wps_crypto_funcs, \
-    .factory_info = {   \
-        WPS_AGG( .manufacturer = "ESPRESSIF" ),  \
-        WPS_AGG( .model_number = "ESP32" ),  \
-        WPS_AGG( .model_name = "ESPRESSIF IOT" ),  \
-        WPS_AGG( .device_name = "ESP STATION" ),  \
-    }  \
-}
-
-/**
-  * @brief     Enable Wi-Fi WPS function.
-  *
-  * @attention WPS can only be used when ESP32 station is enabled.
-  *
-  * @param     wps_type_t wps_type : WPS type, so far only WPS_TYPE_PBC and WPS_TYPE_PIN is supported
-  *
-  * @return    
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_WIFI_WPS_TYPE : wps type is invalid
-  *          - ESP_ERR_WIFI_WPS_MODE : wifi is not in station mode or sniffer mode is on
-  *          - ESP_FAIL : wps initialization fails
-  */
-esp_err_t esp_wifi_wps_enable(const esp_wps_config_t *config);
-
-/**
-  * @brief  Disable Wi-Fi WPS function and release resource it taken.
-  *
-  * @param  null
-  *
-  * @return    
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_WIFI_WPS_MODE : wifi is not in station mode or sniffer mode is on
-  */
-esp_err_t esp_wifi_wps_disable(void);
-
-/**
-  * @brief     WPS starts to work.
-  *
-  * @attention WPS can only be used when ESP32 station is enabled.
-  *
-  * @param     timeout_ms : maximum blocking time before API return.
-  *          - 0 : non-blocking
-  *          - 1~120000 : blocking time (not supported in IDF v1.0)
-  *
-  * @return    
-  *          - ESP_OK : succeed
-  *          - ESP_ERR_WIFI_WPS_TYPE : wps type is invalid
-  *          - ESP_ERR_WIFI_WPS_MODE : wifi is not in station mode or sniffer mode is on
-  *          - ESP_ERR_WIFI_WPS_SM : wps state machine is not initialized
-  *          - ESP_FAIL : wps initialization fails
-  */
-esp_err_t esp_wifi_wps_start(int timeout_ms);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_WPS_H__ */
diff --git a/tools/sdk/include/esp32/hwcrypto/aes.h b/tools/sdk/include/esp32/hwcrypto/aes.h
deleted file mode 100644
index 5a3fd24fe03..00000000000
--- a/tools/sdk/include/esp32/hwcrypto/aes.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/**
- * \brief AES block cipher, ESP32 hardware accelerated version
- * Based on mbedTLS FIPS-197 compliant version.
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *
- */
-
-#ifndef ESP_AES_H
-#define ESP_AES_H
-
-#include "esp_types.h"
-#include "rom/aes.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* padlock.c and aesni.c rely on these values! */
-#define ESP_AES_ENCRYPT     1
-#define ESP_AES_DECRYPT     0
-
-#define ERR_ESP_AES_INVALID_KEY_LENGTH                -0x0020  /**< Invalid key length. */
-#define ERR_ESP_AES_INVALID_INPUT_LENGTH              -0x0022  /**< Invalid data input length. */
-
-/**
- * \brief          AES context structure
- *
- */
-typedef struct {
-    uint8_t key_bytes;
-    volatile uint8_t key_in_hardware; /* This variable is used for fault injection checks, so marked volatile to avoid optimisation */
-    uint8_t key[32];
-} esp_aes_context;
-
-/**
- * \brief The AES XTS context-type definition.
- */
-typedef struct
-{
-    esp_aes_context crypt; /*!< The AES context to use for AES block
-                                        encryption or decryption. */
-    esp_aes_context tweak; /*!< The AES context used for tweak
-                                        computation. */
-} esp_aes_xts_context;
-
-
-/**
- * \brief Lock access to AES hardware unit
- *
- * AES hardware unit can only be used by one
- * consumer at a time.
- *
- * esp_aes_xxx API calls automatically manage locking & unlocking of
- * hardware, this function is only needed if you want to call
- * ets_aes_xxx functions directly.
- */
-void esp_aes_acquire_hardware( void );
-
-/**
- * \brief Unlock access to AES hardware unit
- *
- * esp_aes_xxx API calls automatically manage locking & unlocking of
- * hardware, this function is only needed if you want to call
- * ets_aes_xxx functions directly.
- */
-void esp_aes_release_hardware( void );
-
-/**
- * \brief          Initialize AES context
- *
- * \param ctx      AES context to be initialized
- */
-void esp_aes_init( esp_aes_context *ctx );
-
-/**
- * \brief          Clear AES context
- *
- * \param ctx      AES context to be cleared
- */
-void esp_aes_free( esp_aes_context *ctx );
-
-/**
- * \brief          This function initializes the specified AES XTS context.
- *
- *                 It must be the first API called before using
- *                 the context.
- *
- * \param ctx      The AES XTS context to initialize.
- */
-void esp_aes_xts_init( esp_aes_xts_context *ctx );
-
-/**
- * \brief          This function releases and clears the specified AES XTS context.
- *
- * \param ctx      The AES XTS context to clear.
- */
-void esp_aes_xts_free( esp_aes_xts_context *ctx );
-
-/**
- * \brief          AES set key schedule (encryption or decryption)
- *
- * \param ctx      AES context to be initialized
- * \param key      encryption key
- * \param keybits  must be 128, 192 or 256
- *
- * \return         0 if successful, or ERR_AES_INVALID_KEY_LENGTH
- */
-int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits );
-
-/**
- * \brief          AES-ECB block encryption/decryption
- *
- * \param ctx      AES context
- * \param mode     AES_ENCRYPT or AES_DECRYPT
- * \param input    16-byte input block
- * \param output   16-byte output block
- *
- * \return         0 if successful
- */
-int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] );
-
-/**
- * \brief          AES-CBC buffer encryption/decryption
- *                 Length should be a multiple of the block
- *                 size (16 bytes)
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      AES context
- * \param mode     AES_ENCRYPT or AES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if successful, or ERR_AES_INVALID_INPUT_LENGTH
- */
-int esp_aes_crypt_cbc( esp_aes_context *ctx,
-                       int mode,
-                       size_t length,
-                       unsigned char iv[16],
-                       const unsigned char *input,
-                       unsigned char *output );
-
-
-/**
- * \brief          AES-CFB128 buffer encryption/decryption.
- *
- * Note: Due to the nature of CFB you should use the same key schedule for
- * both encryption and decryption. So a context initialized with
- * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      AES context
- * \param mode     AES_ENCRYPT or AES_DECRYPT
- * \param length   length of the input data
- * \param iv_off   offset in IV (updated after use)
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if successful
- */
-int esp_aes_crypt_cfb128( esp_aes_context *ctx,
-                          int mode,
-                          size_t length,
-                          size_t *iv_off,
-                          unsigned char iv[16],
-                          const unsigned char *input,
-                          unsigned char *output );
-
-/**
- * \brief          AES-CFB8 buffer encryption/decryption.
- *
- * Note: Due to the nature of CFB you should use the same key schedule for
- * both encryption and decryption. So a context initialized with
- * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      AES context
- * \param mode     AES_ENCRYPT or AES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if successful
- */
-int esp_aes_crypt_cfb8( esp_aes_context *ctx,
-                        int mode,
-                        size_t length,
-                        unsigned char iv[16],
-                        const unsigned char *input,
-                        unsigned char *output );
-
-/**
- * \brief               AES-CTR buffer encryption/decryption
- *
- * Warning: You have to keep the maximum use of your counter in mind!
- *
- * Note: Due to the nature of CTR you should use the same key schedule for
- * both encryption and decryption. So a context initialized with
- * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
- *
- * \param ctx           AES context
- * \param length        The length of the data
- * \param nc_off        The offset in the current stream_block (for resuming
- *                      within current cipher stream). The offset pointer to
- *                      should be 0 at the start of a stream.
- * \param nonce_counter The 128-bit nonce and counter.
- * \param stream_block  The saved stream-block for resuming. Is overwritten
- *                      by the function.
- * \param input         The input data stream
- * \param output        The output data stream
- *
- * \return         0 if successful
- */
-int esp_aes_crypt_ctr( esp_aes_context *ctx,
-                       size_t length,
-                       size_t *nc_off,
-                       unsigned char nonce_counter[16],
-                       unsigned char stream_block[16],
-                       const unsigned char *input,
-                       unsigned char *output );
-
-/**
- * \brief          This function prepares an XTS context for encryption and
- *                 sets the encryption key.
- *
- * \param ctx      The AES XTS context to which the key should be bound.
- * \param key      The encryption key. This is comprised of the XTS key1
- *                 concatenated with the XTS key2.
- * \param keybits  The size of \p key passed in bits. Valid options are:
- *                 <ul><li>256 bits (each of key1 and key2 is a 128-bit key)</li>
- *                 <li>512 bits (each of key1 and key2 is a 256-bit key)</li></ul>
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
- */
-int esp_aes_xts_setkey_enc( esp_aes_xts_context *ctx,
-                                const unsigned char *key,
-                                unsigned int keybits );
-
-/**
- * \brief          This function prepares an XTS context for decryption and
- *                 sets the decryption key.
- *
- * \param ctx      The AES XTS context to which the key should be bound.
- * \param key      The decryption key. This is comprised of the XTS key1
- *                 concatenated with the XTS key2.
- * \param keybits  The size of \p key passed in bits. Valid options are:
- *                 <ul><li>256 bits (each of key1 and key2 is a 128-bit key)</li>
- *                 <li>512 bits (each of key1 and key2 is a 256-bit key)</li></ul>
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
- */
-int esp_aes_xts_setkey_dec( esp_aes_xts_context *ctx,
-                                const unsigned char *key,
-                                unsigned int keybits );
-
-
-/**
- * \brief           Internal AES block encryption function
- *                  (Only exposed to allow overriding it,
- *                  see AES_ENCRYPT_ALT)
- *
- * \param ctx       AES context
- * \param input     Plaintext block
- * \param output    Output (ciphertext) block
- */
-int esp_internal_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
-
-/** Deprecated, see esp_aes_internal_encrypt */
-void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated));
-
-/**
- * \brief           Internal AES block decryption function
- *                  (Only exposed to allow overriding it,
- *                  see AES_DECRYPT_ALT)
- *
- * \param ctx       AES context
- * \param input     Ciphertext block
- * \param output    Output (plaintext) block
- */
-int esp_internal_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
-
-/** Deprecated, see esp_aes_internal_decrypt */
-void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* aes.h */
diff --git a/tools/sdk/include/esp32/hwcrypto/sha.h b/tools/sdk/include/esp32/hwcrypto/sha.h
deleted file mode 100644
index 516de6c1272..00000000000
--- a/tools/sdk/include/esp32/hwcrypto/sha.h
+++ /dev/null
@@ -1,211 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_SHA_H_
-#define _ESP_SHA_H_
-
-#include "rom/sha.h"
-#include "esp_types.h"
-
-/** @brief Low-level support functions for the hardware SHA engine
- *
- * @note If you're looking for a SHA API to use, try mbedtls component
- * mbedtls/shaXX.h. That API supports hardware acceleration.
- *
- * The API in this header provides some building blocks for implementing a
- * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha().
- *
- * Some technical details about the hardware SHA engine:
- *
- * - SHA accelerator engine calculates one digest at a time, per SHA
- *   algorithm type. It initialises and maintains the digest state
- *   internally. It is possible to read out an in-progress SHA digest
- *   state, but it is not possible to restore a SHA digest state
- *   into the engine.
- *
- * - The memory block SHA_TEXT_BASE is shared between all SHA digest
- *   engines, so all engines must be idle before this memory block is
- *   modified.
- *
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Defined in rom/sha.h */
-typedef enum SHA_TYPE esp_sha_type;
-
-/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine
- *
- * @note For more versatile SHA calculations, where data doesn't need
- * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. The
- * hardware-accelerated mbedTLS implementation is also faster when
- * hashing large amounts of data.
- *
- * @note It is not necessary to lock any SHA hardware before calling
- * this function, thread safety is managed internally.
- *
- * @note If a TLS connection is open then this function may block
- * indefinitely waiting for a SHA engine to become available. Use the
- * mbedTLS SHA API to avoid this problem.
- *
- * @param sha_type SHA algorithm to use.
- *
- * @param input Input data buffer.
- *
- * @param ilen Length of input data in bytes.
- *
- * @param output Buffer for output SHA digest. Output is 20 bytes for
- * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for
- * sha_type SHA2_384, 64 bytes for sha_type SHA2_512.
- */
-void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output);
-
-/* @brief Begin to execute a single SHA block operation
- *
- * @note This is a piece of a SHA algorithm, rather than an entire SHA
- * algorithm.
- *
- * @note Call esp_sha_try_lock_engine() before calling this
- * function. Do not call esp_sha_lock_memory_block() beforehand, this
- * is done inside the function.
- *
- * @param sha_type SHA algorithm to use.
- *
- * @param data_block Pointer to block of data. Block size is
- * determined by algorithm (SHA1/SHA2_256 = 64 bytes,
- * SHA2_384/SHA2_512 = 128 bytes)
- *
- * @param is_first_block If this parameter is true, the SHA state will
- * be initialised (with the initial state of the given SHA algorithm)
- * before the block is calculated. If false, the existing state of the
- * SHA engine will be used.
- *
- * @return As a performance optimisation, this function returns before
- * the SHA block operation is complete. Both this function and
- * esp_sha_read_state() will automatically wait for any previous
- * operation to complete before they begin. If using the SHA registers
- * directly in another way, call esp_sha_wait_idle() after calling this
- * function but before accessing the SHA registers.
- */
-void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block);
-
-/** @brief Read out the current state of the SHA digest loaded in the engine.
- *
- * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm.
- *
- * @note Call esp_sha_try_lock_engine() before calling this
- * function. Do not call esp_sha_lock_memory_block() beforehand, this
- * is done inside the function.
- *
- * If the SHA suffix padding block has been executed already, the
- * value that is read is the SHA digest (in big endian
- * format). Otherwise, the value that is read is an interim SHA state.
- *
- * @note If sha_type is SHA2_384, only 48 bytes of state will be read.
- * This is enough for the final SHA2_384 digest, but if you want the
- * interim SHA-384 state (to continue digesting) then pass SHA2_512 instead.
- *
- * @param sha_type SHA algorithm in use.
- *
- * @param state Pointer to a memory buffer to hold the SHA state. Size
- * is 20 bytes (SHA1), 32 bytes (SHA2_256), 48 bytes (SHA2_384) or 64 bytes (SHA2_512).
- *
- */
-void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state);
-
-/**
- * @brief Obtain exclusive access to a particular SHA engine
- *
- * @param sha_type Type of SHA engine to use.
- *
- * Blocks until engine is available. Note: Can block indefinitely
- * while a TLS connection is open, suggest using
- * esp_sha_try_lock_engine() and failing over to software SHA.
- */
-void esp_sha_lock_engine(esp_sha_type sha_type);
-
-/**
- * @brief Try and obtain exclusive access to a particular SHA engine
- *
- * @param sha_type Type of SHA engine to use.
- *
- * @return Returns true if the SHA engine is locked for exclusive
- * use. Call esp_sha_unlock_sha_engine() when done.  Returns false if
- * the SHA engine is already in use, caller should use software SHA
- * algorithm for this digest.
- */
-bool esp_sha_try_lock_engine(esp_sha_type sha_type);
-
-/**
- * @brief Unlock an engine previously locked with esp_sha_lock_engine() or esp_sha_try_lock_engine()
- *
- * @param sha_type Type of engine to release.
- */
-void esp_sha_unlock_engine(esp_sha_type sha_type);
-
-/**
- * @brief Acquire exclusive access to the SHA shared memory block at SHA_TEXT_BASE
- *
- * This memory block is shared across all the SHA algorithm types.
- *
- * Caller should have already locked a SHA engine before calling this function.
- *
- * Note that it is possible to obtain exclusive access to the memory block even
- * while it is in use by the SHA engine. Caller should use esp_sha_wait_idle()
- * to ensure the SHA engine is not reading from the memory block in hardware.
- *
- * @note This function enters a critical section. Do not block while holding this lock.
- *
- * @note You do not need to lock the memory block before calling esp_sha_block() or esp_sha_read_digest_state(), these functions handle memory block locking internally.
- *
- * Call esp_sha_unlock_memory_block() when done.
- */
-void esp_sha_lock_memory_block(void);
-
-/**
- * @brief Release exclusive access to the SHA register memory block at SHA_TEXT_BASE
- *
- * Caller should have already locked a SHA engine before calling this function.
- *
- * This function releases the critical section entered by esp_sha_lock_memory_block().
- *
- * Call following esp_sha_lock_memory_block().
- */
-void esp_sha_unlock_memory_block(void);
-
-/** @brief Wait for the SHA engine to finish any current operation
- *
- * @note This function does not ensure exclusive access to any SHA
- * engine. Caller should use esp_sha_try_lock_engine() and
- * esp_sha_lock_memory_block() as required.
- *
- * @note Functions declared in this header file wait for SHA engine
- * completion automatically, so you don't need to use this API for
- * these. However if accessing SHA registers directly, you will need
- * to call this before accessing SHA registers if using the
- * esp_sha_block() function.
- *
- * @note This function busy-waits, so wastes CPU resources.
- * Best to delay calling until you are about to need it.
- *
- */
-void esp_sha_wait_idle(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/tools/sdk/include/esp32/rom/aes.h b/tools/sdk/include/esp32/rom/aes.h
deleted file mode 100644
index 80eca973fc9..00000000000
--- a/tools/sdk/include/esp32/rom/aes.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
-  ROM functions for hardware AES support.
-
-  It is not recommended to use these functions directly,
-  use the wrapper functions in hwcrypto/aes.h instead.
-
- */
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_AES_H_
-#define _ROM_AES_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//TODO, add comment for aes apis
-enum AES_BITS {
-    AES128,
-    AES192,
-    AES256
-};
-
-void ets_aes_enable(void);
-
-void ets_aes_disable(void);
-
-void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap,
-                        bool in_word_swap, bool in_byte_swap,
-                        bool out_word_swap, bool out_byte_swap);
-
-bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits);
-
-bool ets_aes_setkey_dec(const uint8_t *key, enum AES_BITS bits);
-
-void ets_aes_crypt(const uint8_t input[16], uint8_t output[16]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_AES_H_ */
diff --git a/tools/sdk/include/esp32/rom/bigint.h b/tools/sdk/include/esp32/rom/bigint.h
deleted file mode 100644
index 97ad72202a3..00000000000
--- a/tools/sdk/include/esp32/rom/bigint.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
-  ROM functions for hardware bigint support.
-
-  It is not recommended to use these functions directly,
-  use the wrapper functions in hwcrypto/mpi.h instead.
-
- */
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_BIGINT_H_
-#define _ROM_BIGINT_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//TODO: add comment here
-void ets_bigint_enable(void);
-
-void ets_bigint_disable(void);
-
-void ets_bigint_wait_finish(void);
-
-bool ets_bigint_mod_power_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
-                                  uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
-
-bool ets_bigint_mod_power_getz(uint32_t *z, uint32_t len);
-
-bool ets_bigint_mult_prepare(uint32_t *x, uint32_t *y, uint32_t len);
-
-bool ets_bigint_mult_getz(uint32_t *z, uint32_t len);
-
-bool ets_bigint_montgomery_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
-                                        uint32_t m_dash, uint32_t len, bool again);
-
-bool ets_bigint_montgomery_mult_getz(uint32_t *z, uint32_t len);
-
-bool ets_bigint_mod_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
-                                 uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
-
-bool ets_bigint_mod_mult_getz(uint32_t *m, uint32_t *z, uint32_t len);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_BIGINT_H_ */
diff --git a/tools/sdk/include/esp32/rom/cache.h b/tools/sdk/include/esp32/rom/cache.h
deleted file mode 100644
index 4b923e669d7..00000000000
--- a/tools/sdk/include/esp32/rom/cache.h
+++ /dev/null
@@ -1,186 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_CACHE_H_
-#define _ROM_CACHE_H_
-
-#include "soc/dport_access.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup uart_apis, uart configuration and communication related apis
-  * @brief uart apis
-  */
-
-/** @addtogroup uart_apis
-  * @{
-  */
-
-/**
-  * @brief Initialise cache mmu, mark all entries as invalid.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
-  *
-  * @return None
-  */
-void mmu_init(int cpu_no);
-
-/**
-  * @brief Set Flash-Cache mmu mapping.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
-  *
-  * @param  int pod : process identifier. Range 0~7.
-  *
-  * @param  unsigned int vaddr : virtual address in CPU address space.
-  *                              Can be IRam0, IRam1, IRom0 and DRom0 memory address.
-  *                              Should be aligned by psize.
-  *
-  * @param  unsigned int paddr : physical address in Flash.
-  *                              Should be aligned by psize.
-  *
-  * @param  int psize : page size of flash, in kilobytes. Should be 64 here.
-  *
-  * @param  int num : pages to be set.
-  *
-  * @return unsigned int: error status
-  *                   0 : mmu set success
-  *                   1 : vaddr or paddr is not aligned
-  *                   2 : pid error
-  *                   3 : psize error
-  *                   4 : mmu table to be written is out of range
-  *                   5 : vaddr is out of range
-  */
-static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num)
-{
-    extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num);
-
-    unsigned int ret;
-
-    DPORT_STALL_OTHER_CPU_START();
-    ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
-    DPORT_STALL_OTHER_CPU_END();
-
-    return ret;
-}
-
-/**
-  * @brief Set Ext-SRAM-Cache mmu mapping.
-  *        Please do not call this function in your SDK application.
-  *
-  * Note that this code lives in IRAM and has a bugfix in respect to the ROM version
-  * of this function (which erroneously refused a vaddr > 2MiB
-  *
-  * @param  int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
-  *
-  * @param  int pod : process identifier. Range 0~7.
-  *
-  * @param  unsigned int vaddr : virtual address in CPU address space.
-  *                              Can be IRam0, IRam1, IRom0 and DRom0 memory address.
-  *                              Should be aligned by psize.
-  *
-  * @param  unsigned int paddr : physical address in Ext-SRAM.
-  *                              Should be aligned by psize.
-  *
-  * @param  int psize : page size of flash, in kilobytes. Should be 32 here.
-  *
-  * @param  int num : pages to be set.
-  *
-  * @return unsigned int: error status
-  *                   0 : mmu set success
-  *                   1 : vaddr or paddr is not aligned
-  *                   2 : pid error
-  *                   3 : psize error
-  *                   4 : mmu table to be written is out of range
-  *                   5 : vaddr is out of range
-  */
-unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
-
-/**
-  * @brief Initialise cache access for the cpu.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
-  *
-  * @return None
-  */
-static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
-{
-    extern void Cache_Read_Init_rom(int cpu_no);
-    DPORT_STALL_OTHER_CPU_START();
-    Cache_Read_Init_rom(cpu_no);
-    DPORT_STALL_OTHER_CPU_END();
-}
-
-/**
-  * @brief Flush the cache value for the cpu.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
-  *
-  * @return None
-  */
-static inline void IRAM_ATTR Cache_Flush(int cpu_no)
-{
-    extern void Cache_Flush_rom(int cpu_no);
-    DPORT_STALL_OTHER_CPU_START();
-    Cache_Flush_rom(cpu_no);
-    DPORT_STALL_OTHER_CPU_END();
-}
-
-/**
-  * @brief Disable Cache access for the cpu.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
-  *
-  * @return None
-  */
-static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
-{
-    extern void Cache_Read_Disable_rom(int cpu_no);
-    DPORT_STALL_OTHER_CPU_START();
-    Cache_Read_Disable_rom(cpu_no);
-    DPORT_STALL_OTHER_CPU_END();
-}
-
-/**
-  * @brief Enable Cache access for the cpu.
-  *        Please do not call this function in your SDK application.
-  *
-  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
-  *
-  * @return None
-  */
-static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no)
-{
-    extern void Cache_Read_Enable_rom(int cpu_no);
-    DPORT_STALL_OTHER_CPU_START();
-    Cache_Read_Enable_rom(cpu_no);
-    DPORT_STALL_OTHER_CPU_END();
-}
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_CACHE_H_ */
diff --git a/tools/sdk/include/esp32/rom/crc.h b/tools/sdk/include/esp32/rom/crc.h
deleted file mode 100644
index faa1e8c351b..00000000000
--- a/tools/sdk/include/esp32/rom/crc.h
+++ /dev/null
@@ -1,160 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef ROM_CRC_H
-#define ROM_CRC_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup uart_apis, uart configuration and communication related apis
-  * @brief uart apis
-  */
-
-/** @addtogroup uart_apis
-  * @{
-  */
-
-
-/*           Notes about CRC APIs usage
- * The ESP32 ROM include some CRC tables and CRC APIs to speed up CRC calculation.
- * The CRC APIs include CRC8, CRC16, CRC32 algorithms for both little endian and big endian modes.
- * Here are the polynomials for the algorithms:
- * CRC-8        x8+x2+x1+1                                              0x07
- * CRC16-CCITT  x16+x12+x5+1                                            0x1021
- * CRC32        x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1     0x04c11db7
- * 
- * These group of CRC APIs are designed to calculate the data in buffers either continuous or not.
- * To make it easy, we had added a `~` at the beginning and the end of the functions.
- * To calculate non-continuous buffers, we can write the code like this:
- *     init = ~init;
- *     crc = crc32_le(init, buf0, length0);
- *     crc = crc32_le(crc, buf1, length1);
- *     crc = ~crc;
- *
- * However, it is not easy to select which API to use and give the correct parameters.
- * A specific CRC algorithm will include this parameters: width, polynomials, init, refin, refout, xorout
- *     refin and refout show the endian of the algorithm:
- *         if both of them are true, please use the little endian API.
- *         if both of them are false, please use the big endian API.
- *     xorout is the value which you need to be xored to the raw result.
- * However, these group of APIs need one '~' before and after the APIs.
- *
- * Here are some examples for CRC16:
- * CRC-16/CCITT, poly = 0x1021, init = 0x0000, refin = true, refout = true, xorout = 0x0000
- *     crc = ~crc16_le((uint16_t)~0x0000, buf, length);
- * 
- * CRC-16/CCITT-FALSE, poly = 0x1021, init = 0xffff, refin = false, refout = false, xorout = 0x0000
- *     crc = ~crc16_be((uint16_t)~0xffff, buf, length);
- *
- * CRC-16/X25, poly = 0x1021, init = 0xffff, refin = true, refout = true, xorout = 0xffff
- *     crc = (~crc16_le((uint16_t)~(0xffff), buf, length))^0xffff;
- *
- * CRC-16/XMODEM, poly= 0x1021, init = 0x0000, refin = false, refout = false, xorout = 0x0000
- *     crc = ~crc16_be((uint16_t)~0x0000, buf, length);
- *
- *     
- */
-
-/**
-  * @brief CRC32 value that is in little endian.
-  *
-  * @param  uint32_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief CRC32 value that is in big endian.
-  *
-  * @param  uint32_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief CRC16 value that is in little endian.
-  *
-  * @param  uint16_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief CRC16 value that is in big endian.
-  *
-  * @param  uint16_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief CRC8 value that is in little endian.
-  *
-  * @param  uint8_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @brief CRC8 value that is in big endian.
-  *
-  * @param  uint32_t crc : init crc value, use 0 at the first use.
-  *
-  * @param  uint8_t const *buf : buffer to start calculate crc.
-  *
-  * @param  uint32_t len : buffer length in byte.
-  *
-  * @return None
-  */
-uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif
diff --git a/tools/sdk/include/esp32/rom/efuse.h b/tools/sdk/include/esp32/rom/efuse.h
deleted file mode 100644
index 337227ab0d4..00000000000
--- a/tools/sdk/include/esp32/rom/efuse.h
+++ /dev/null
@@ -1,117 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_EFUSE_H_
-#define _ROM_EFUSE_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup efuse_APIs efuse APIs
-  * @brief     ESP32 efuse read/write APIs
-  * @attention
-  *
-  */
-
-/** @addtogroup efuse_APIs
-  * @{
-  */
-
-/**
-  * @brief  Do a efuse read operation, to update the efuse value to efuse read registers.
-  *
-  * @param  null
-  *
-  * @return null
-  */
-void ets_efuse_read_op(void);
-
-/**
-  * @brief  Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
-  *
-  * @param  null
-  *
-  * @return null
-  */
-void ets_efuse_program_op(void);
-
-/**
-  * @brief  Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature.
-  *         It can be used to test the external xtal frequency, do not touch this efuse field.
-  *
-  * @param  null
-  *
-  * @return u32: 1 for 100KHZ, range is 0 to 255.
-  */
-uint32_t ets_efuse_get_8M_clock(void);
-
-/**
-  * @brief  Read spi flash pin configuration from Efuse
-  *
-  * @return
-  * - 0 for default SPI pins.
-  * - 1 for default HSPI pins.
-  * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
-  *   EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
-  *   WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
-  */
-uint32_t ets_efuse_get_spiconfig(void);
-
-#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
-#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
-
-#define EFUSE_SPICONFIG_RET_SPICLK_MASK         0x3f
-#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT        0
-#define EFUSE_SPICONFIG_RET_SPICLK(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
-
-#define EFUSE_SPICONFIG_RET_SPIQ_MASK           0x3f
-#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT          6
-#define EFUSE_SPICONFIG_RET_SPIQ(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
-
-#define EFUSE_SPICONFIG_RET_SPID_MASK           0x3f
-#define EFUSE_SPICONFIG_RET_SPID_SHIFT          12
-#define EFUSE_SPICONFIG_RET_SPID(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
-
-#define EFUSE_SPICONFIG_RET_SPICS0_MASK         0x3f
-#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT        18
-#define EFUSE_SPICONFIG_RET_SPICS0(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
-
-
-#define EFUSE_SPICONFIG_RET_SPIHD_MASK          0x3f
-#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT         24
-#define EFUSE_SPICONFIG_RET_SPIHD(ret)          (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
-
-/**
-  * @brief  A crc8 algorithm used in efuse check.
-  *
-  * @param  unsigned char const *p : Pointer to original data.
-  *
-  * @param  unsigned int len : Data length in byte.
-  *
-  * @return unsigned char: Crc value.
-  */
-unsigned char esp_crc8(unsigned char const *p, unsigned int len);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_EFUSE_H_ */
diff --git a/tools/sdk/include/esp32/rom/ets_sys.h b/tools/sdk/include/esp32/rom/ets_sys.h
deleted file mode 100644
index 6e27b38beb3..00000000000
--- a/tools/sdk/include/esp32/rom/ets_sys.h
+++ /dev/null
@@ -1,645 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_ETS_SYS_H_
-#define _ROM_ETS_SYS_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup ets_sys_apis, ets system related apis
-  * @brief ets system apis
-  */
-
-/** @addtogroup ets_sys_apis
-  * @{
-  */
-
-/************************************************************************
-  *                                NOTE
-  *   Many functions in this header files can't be run in FreeRTOS.
-  *   Please see the comment of the Functions.
-  *   There are also some functions that doesn't work on FreeRTOS
-  *   without listed in the header, such as:
-  *   xtos functions start with "_xtos_" in ld file.
-  *
-  ***********************************************************************
-  */
-
-/** \defgroup ets_apis, Espressif Task Scheduler related apis
-  * @brief ets apis
-  */
-
-/** @addtogroup ets_apis
-  * @{
-  */
-
-typedef enum {
-    ETS_OK     = 0, /**< return successful in ets*/
-    ETS_FAILED = 1  /**< return failed in ets*/
-} ETS_STATUS;
-
-typedef uint32_t ETSSignal;
-typedef uint32_t ETSParam;
-
-typedef struct ETSEventTag ETSEvent;    /**< Event transmit/receive in ets*/
-
-struct ETSEventTag {
-    ETSSignal sig;  /**< Event signal, in same task, different Event with different signal*/
-    ETSParam  par;  /**< Event parameter, sometimes without usage, then will be set as 0*/
-};
-
-typedef void (*ETSTask)(ETSEvent *e);       /**< Type of the Task processer*/
-typedef void (* ets_idle_cb_t)(void *arg);  /**< Type of the system idle callback*/
-
-/**
-  * @brief  Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it.
-  *
-  * @param  none
-  *
-  * @return none
-  */
-void ets_run(void);
-
-/**
-  * @brief  Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep.
-  *
-  * @param  ets_idle_cb_t func : The callback function.
-  *
-  * @param  void *arg : Argument of the callback.
-  *
-  * @return None
-  */
-void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
-
-/**
-  * @brief  Init a task with processer, priority, queue to receive Event, queue length.
-  *
-  * @param  ETSTask task : The task processer.
-  *
-  * @param  uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task.
-  *
-  * @param  ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used.
-  *
-  * @param  uint8_t qlen : Queue length.
-  *
-  * @return None
-  */
-void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
-
-/**
-  * @brief  Post an event to an Task.
-  *
-  * @param  uint8_t prio : Priority of the Task.
-  *
-  * @param  ETSSignal sig : Event signal.
-  *
-  * @param  ETSParam  par : Event parameter
-  *
-  * @return ETS_OK     : post successful
-  * @return ETS_FAILED : post failed
-  */
-ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
-
-/**
-  * @}
-  */
-
-/** \defgroup ets_boot_apis, Boot routing related apis
-  * @brief ets boot apis
-  */
-
-/** @addtogroup ets_apis
-  * @{
-  */
-
-extern const char *const exc_cause_table[40];   ///**< excption cause that defined by the core.*/
-
-/**
-  * @brief  Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
-  *         When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
-  *
-  * @param  uint32_t start : the PRO Entry code address value in uint32_t
-  *
-  * @return None
-  */
-void ets_set_user_start(uint32_t start);
-
-/**
-  * @brief  Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code.
-  *         When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run.
-  *
-  * @param  uint32_t callback : the Startup code address value in uint32_t
-  *
-  * @return None     : post successful
-  */
-void ets_set_startup_callback(uint32_t callback);
-
-/**
-  * @brief  Set App cpu Entry code, code can be called in PRO CPU.
-  *         When APP booting is completed, APP CPU will call the Entry code if not NULL.
-  *
-  * @param  uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D.
-  *
-  * @return None
-  */
-void ets_set_appcpu_boot_addr(uint32_t start);
-
-/**
-  * @brief  unpack the image in flash to iram and dram, no using cache.
-  *
-  * @param  uint32_t pos : Flash physical address.
-  *
-  * @param  uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
-  *
-  * @param  bool jump : Jump into the code in the function or not.
-  *
-  * @param  bool config : Config the flash when unpacking the image, config should be done only once.
-  *
-  * @return ETS_OK     : unpack successful
-  * @return ETS_FAILED : unpack failed
-  */
-ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config);
-
-/**
-  * @brief  unpack the image in flash to iram and dram, using cache, maybe decrypting.
-  *
-  * @param  uint32_t pos : Flash physical address.
-  *
-  * @param  uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
-  *
-  * @param  bool jump : Jump into the code in the function or not.
-  *
-  * @param  bool sb_need_check : Do security boot check or not.
-  *
-  * @param  bool config : Config the flash when unpacking the image, config should be done only once.
-  *
-  * @return ETS_OK     : unpack successful
-  * @return ETS_FAILED : unpack failed
-  */
-ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config);
-
-/**
-  * @}
-  */
-
-/** \defgroup ets_printf_apis, ets_printf related apis used in ets
-  * @brief ets printf apis
-  */
-
-/** @addtogroup ets_printf_apis
-  * @{
-  */
-
-/**
-  * @brief  Printf the strings to uart or other devices, similar with printf, simple than printf.
-  *         Can not print float point data format, or longlong data format.
-  *         So we maybe only use this in ROM.
-  *
-  * @param  const char *fmt : See printf.
-  *
-  * @param  ... : See printf.
-  *
-  * @return int : the length printed to the output device.
-  */
-int ets_printf(const char *fmt, ...);
-
-/**
-  * @brief  Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
-  *         Can not print float point data format, or longlong data format
-  *
-  * @param  char c : char to output.
-  *
-  * @return None
-  */
-void ets_write_char_uart(char c);
-
-/**
-  * @brief  Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
-  *         To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
-  *
-  * @param  void (*)(char) p: Output function to install.
-  *
-  * @return None
-  */
-void ets_install_putc1(void (*p)(char c));
-
-/**
-  * @brief  Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
-  *         To install putc2, which is defaulted installed as NULL.
-  *
-  * @param  void (*)(char) p: Output function to install.
-  *
-  * @return None
-  */
-void ets_install_putc2(void (*p)(char c));
-
-/**
-  * @brief  Install putc1 as ets_write_char_uart.
-  *         In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_install_uart_printf(void);
-
-#define ETS_PRINTF(...) ets_printf(...)
-
-#define ETS_ASSERT(v) do { \
-    if (!(v)) {             \
-        ets_printf("%s %u \n", __FILE__, __LINE__); \
-        while (1) {};   \
-    }                   \
-} while (0);
-
-/**
-  * @}
-  */
-
-/** \defgroup ets_timer_apis, ets_timer related apis used in ets
-  * @brief ets timer apis
-  */
-
-/** @addtogroup ets_timer_apis
-  * @{
-  */
-typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
-
-typedef struct _ETSTIMER_ {
-    struct _ETSTIMER_    *timer_next;   /**< timer linker*/
-    uint32_t              timer_expire; /**< abstruct time when timer expire*/
-    uint32_t              timer_period; /**< timer period, 0 means timer is not periodic repeated*/
-    ETSTimerFunc         *timer_func;   /**< timer handler*/
-    void                 *timer_arg;    /**< timer handler argument*/
-} ETSTimer;
-
-/**
-  * @brief  Init ets timer, this timer range is 640 us to 429496 ms
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_timer_init(void);
-
-/**
-  * @brief  In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_timer_deinit(void);
-
-/**
-  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @param  uint32_t tmout : Timer value in ms, range is 1 to 429496.
-  *
-  * @param  bool repeat : Timer is periodic repeated.
-  *
-  * @return None
-  */
-void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
-
-/**
-  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @param  uint32_t tmout : Timer value in us, range is 1 to 429496729.
-  *
-  * @param  bool repeat : Timer is periodic repeated.
-  *
-  * @return None
-  */
-void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
-
-/**
-  * @brief  Disarm an ets timer.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @return None
-  */
-void ets_timer_disarm(ETSTimer *timer);
-
-/**
-  * @brief  Set timer callback and argument.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @param  ETSTimerFunc *pfunction : Timer callback.
-  *
-  * @param  void *parg : Timer callback argument.
-  *
-  * @return None
-  */
-void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
-
-/**
-  * @brief  Unset timer callback and argument to NULL.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  ETSTimer *timer : Timer struct pointer.
-  *
-  * @return None
-  */
-void ets_timer_done(ETSTimer *ptimer);
-
-/**
-  * @brief  CPU do while loop for some time.
-  *         In FreeRTOS task, please call FreeRTOS apis.
-  *
-  * @param  uint32_t us : Delay time in us.
-  *
-  * @return None
-  */
-void ets_delay_us(uint32_t us);
-
-/**
-  * @brief  Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
-  *         Call this function when CPU frequency is changed.
-  *
-  * @param  uint32_t ticks_per_us : CPU ticks per us.
-  *
-  * @return None
-  */
-void ets_update_cpu_frequency(uint32_t ticks_per_us);
-
-/**
-  * @brief  Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
-  *
-  * @note This function only sets the tick rate for the current CPU. It is located in ROM,
-  *       so the deep sleep stub can use it even if IRAM is not initialized yet.
-  *
-  * @param  uint32_t ticks_per_us : CPU ticks per us.
-  *
-  * @return None
-  */
-void ets_update_cpu_frequency_rom(uint32_t ticks_per_us);
-
-/**
-  * @brief  Get the real CPU ticks per us to the ets.
-  *         This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
-  *
-  * @param  None
-  *
-  * @return uint32_t : CPU ticks per us record in ets.
-  */
-uint32_t ets_get_cpu_frequency(void);
-
-/**
-  * @brief  Get xtal_freq/analog_8M*256 value calibrated in rtc module.
-  *
-  * @param  None
-  *
-  * @return uint32_t : xtal_freq/analog_8M*256.
-  */
-uint32_t ets_get_xtal_scale(void);
-
-/**
-  * @brief  Get xtal_freq value, If value not stored in RTC_STORE5, than store.
-  *
-  * @param  None
-  *
-  * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
-  *                         clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
-  *            else if analog_8M in efuse
-  *                         clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40;
-  *                    else clock = 26M.
-  */
-uint32_t ets_get_detected_xtal_freq(void);
-
-/**
-  * @}
-  */
-
-/** \defgroup ets_intr_apis, ets interrupt configure related apis
-  * @brief ets intr apis
-  */
-
-/** @addtogroup ets_intr_apis
-  * @{
-  */
-
-typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
-
-/**
-  * @brief  Attach a interrupt handler to a CPU interrupt number.
-  *         This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  int i : CPU interrupt number.
-  *
-  * @param  ets_isr_t func : Interrupt handler.
-  *
-  * @param  void *arg : argument of the handler.
-  *
-  * @return None
-  */
-void ets_isr_attach(int i, ets_isr_t func, void *arg);
-
-/**
-  * @brief  Mask the interrupts which show in mask bits.
-  *         This function equals to _xtos_ints_off(mask).
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
-  *
-  * @return None
-  */
-void ets_isr_mask(uint32_t mask);
-
-/**
-  * @brief  Unmask the interrupts which show in mask bits.
-  *         This function equals to _xtos_ints_on(mask).
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
-  *
-  * @return None
-  */
-void ets_isr_unmask(uint32_t unmask);
-
-/**
-  * @brief  Lock the interrupt to level 2.
-  *         This function direct set the CPU registers.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_intr_lock(void);
-
-/**
-  * @brief  Unlock the interrupt to level 0.
-  *         This function direct set the CPU registers.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_intr_unlock(void);
-
-/**
-  * @brief  Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt).
-  *         This function direct set the CPU registers.
-  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void ets_waiti0(void);
-
-/**
-  * @brief  Attach an CPU interrupt to a hardware source.
-  *         We have 4 steps to use an interrupt:
-  *         1.Attach hardware interrupt source to CPU.  intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
-  *         2.Set interrupt handler.                    xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
-  *         3.Enable interrupt for CPU.                 xt_ints_on(1 << ETS_WMAC_INUM);
-  *         4.Enable interrupt in the module.
-  *
-  * @param  int cpu_no : The CPU which the interrupt number belongs.
-  *
-  * @param  uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
-  *
-  * @param  uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
-  *
-  * @return None
-  */
-void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
-
-#define _ETSTR(v) # v
-#define _ETS_SET_INTLEVEL(intlevel)        ({ unsigned __tmp; \
-            __asm__ __volatile__(   "rsil   %0, " _ETSTR(intlevel) "\n" \
-                        : "=a" (__tmp) : : "memory" ); \
-            })
-
-#ifdef CONFIG_NONE_OS
-#define ETS_INTR_LOCK() \
-        ets_intr_lock()
-
-#define ETS_INTR_UNLOCK() \
-        ets_intr_unlock()
-
-#define ETS_ISR_ATTACH \
-        ets_isr_attach
-
-#define ETS_INTR_ENABLE(inum) \
-        ets_isr_unmask((1<<inum))
-
-#define ETS_INTR_DISABLE(inum) \
-        ets_isr_mask((1<<inum))
-
-#define ETS_WMAC_INTR_ATTACH(func, arg) \
-        ETS_ISR_ATTACH(ETS_WMAC_INUM, (func), (void *)(arg))
-
-#define ETS_TG0_T0_INTR_ATTACH(func, arg) \
-        ETS_ISR_ATTACH(ETS_TG0_T0_INUM, (func), (void *)(arg))
-
-#define ETS_GPIO_INTR_ATTACH(func, arg) \
-        ETS_ISR_ATTACH(ETS_GPIO_INUM, (func), (void *)(arg))
-
-#define ETS_UART0_INTR_ATTACH(func, arg) \
-        ETS_ISR_ATTACH(ETS_UART0_INUM, (func), (void *)(arg))
-
-#define ETS_WDT_INTR_ATTACH(func, arg) \
-        ETS_ISR_ATTACH(ETS_WDT_INUM, (func), (void *)(arg))
-
-#define ETS_SLC_INTR_ATTACH(func, arg) \
-        ETS_ISR_ATTACH(ETS_SLC_INUM, (func), (void *)(arg))
-
-#define ETS_BB_INTR_ENABLE() \
-        ETS_INTR_ENABLE(ETS_BB_INUM)
-
-#define ETS_BB_INTR_DISABLE() \
-        ETS_INTR_DISABLE(ETS_BB_INUM)
-
-#define ETS_UART0_INTR_ENABLE() \
-        ETS_INTR_ENABLE(ETS_UART0_INUM)
-
-#define ETS_UART0_INTR_DISABLE() \
-        ETS_INTR_DISABLE(ETS_UART0_INUM)
-
-#define ETS_GPIO_INTR_ENABLE() \
-        ETS_INTR_ENABLE(ETS_GPIO_INUM)
-
-#define ETS_GPIO_INTR_DISABLE() \
-        ETS_INTR_DISABLE(ETS_GPIO_INUM)
-
-#define ETS_WDT_INTR_ENABLE() \
-        ETS_INTR_ENABLE(ETS_WDT_INUM)
-
-#define ETS_WDT_INTR_DISABLE() \
-        ETS_INTR_DISABLE(ETS_WDT_INUM)
-
-#define ETS_TG0_T0_INTR_ENABLE() \
-        ETS_INTR_ENABLE(ETS_TG0_T0_INUM)
-
-#define ETS_TG0_T0_INTR_DISABLE() \
-        ETS_INTR_DISABLE(ETS_TG0_T0_INUM)
-
-#define ETS_SLC_INTR_ENABLE() \
-        ETS_INTR_ENABLE(ETS_SLC_INUM)
-
-#define ETS_SLC_INTR_DISABLE() \
-        ETS_INTR_DISABLE(ETS_SLC_INUM)
-#endif
-
-/**
-  * @}
-  */
-
-#ifndef MAC2STR
-#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
-#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
-#endif
-
-#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
-
-typedef enum {
-    OK = 0,
-    FAIL,
-    PENDING,
-    BUSY,
-    CANCEL,
-} STATUS;
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_ETS_SYS_H_ */
diff --git a/tools/sdk/include/esp32/rom/gpio.h b/tools/sdk/include/esp32/rom/gpio.h
deleted file mode 100644
index f98d6cf2dd0..00000000000
--- a/tools/sdk/include/esp32/rom/gpio.h
+++ /dev/null
@@ -1,303 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_GPIO_H_
-#define _ROM_GPIO_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "esp_attr.h"
-#include "soc/gpio_reg.h"
-#include "soc/gpio_pins.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup gpio_apis, uart configuration and communication related apis
-  * @brief gpio apis
-  */
-
-/** @addtogroup gpio_apis
-  * @{
-  */
-
-#define GPIO_REG_READ(reg)              READ_PERI_REG(reg)
-#define GPIO_REG_WRITE(reg, val)        WRITE_PERI_REG(reg, val)
-#define GPIO_ID_PIN0                    0
-#define GPIO_ID_PIN(n)                  (GPIO_ID_PIN0+(n))
-#define GPIO_PIN_ADDR(i)                (GPIO_PIN0_REG + i*4)
-
-#define GPIO_FUNC_IN_HIGH               0x38
-#define GPIO_FUNC_IN_LOW                0x30
-
-#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
-    ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
-
-#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
-
-typedef enum {
-    GPIO_PIN_INTR_DISABLE = 0,
-    GPIO_PIN_INTR_POSEDGE = 1,
-    GPIO_PIN_INTR_NEGEDGE = 2,
-    GPIO_PIN_INTR_ANYEDGE = 3,
-    GPIO_PIN_INTR_LOLEVEL = 4,
-    GPIO_PIN_INTR_HILEVEL = 5
-} GPIO_INT_TYPE;
-
-#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
-        ((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
-                         gpio_output_set_high(bit_value<<(gpio_no - 32), (bit_value ? 0 : 1)<<(gpio_no - 32), 1<<(gpio_no -32),0))
-#define GPIO_DIS_OUTPUT(gpio_no)    ((gpio_no < 32) ? gpio_output_set(0,0,0, 1<<gpio_no) : gpio_output_set_high(0,0,0, 1<<(gpio_no - 32)))
-#define GPIO_INPUT_GET(gpio_no)     ((gpio_no < 32) ? ((gpio_input_get()>>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0))
-
-/* GPIO interrupt handler, registered through gpio_intr_handler_register */
-typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg);
-
-/**
-  * @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet
-  *        to initialize "output enables" and pin configurations for each gpio pin.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void gpio_init(void);
-
-/**
-  * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
-  *         There is no particular ordering guaranteed; so if the order of writes is significant,
-  *         calling code should divide a single call into multiple calls.
-  *
-  * @param  uint32_t set_mask : the gpios that need high level.
-  *
-  * @param  uint32_t clear_mask : the gpios that need low level.
-  *
-  * @param  uint32_t enable_mask : the gpios that need be changed.
-  *
-  * @param  uint32_t disable_mask : the gpios that need diable output.
-  *
-  * @return None
-  */
-void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
-
-/**
-  * @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
-  *         There is no particular ordering guaranteed; so if the order of writes is significant,
-  *         calling code should divide a single call into multiple calls.
-  *
-  * @param  uint32_t set_mask : the gpios that need high level.
-  *
-  * @param  uint32_t clear_mask : the gpios that need low level.
-  *
-  * @param  uint32_t enable_mask : the gpios that need be changed.
-  *
-  * @param  uint32_t disable_mask : the gpios that need diable output.
-  *
-  * @return None
-  */
-void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
-
-/**
-  * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
-  *
-  * @param None
-  *
-  * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
-  */
-uint32_t gpio_input_get(void);
-
-/**
-  * @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
-  *
-  * @param None
-  *
-  * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32.
-  */
-uint32_t gpio_input_get_high(void);
-
-/**
-  * @brief Register an application-specific interrupt handler for GPIO pin interrupts.
-  *        Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack.
-  *        Please do not call this function in SDK.
-  *
-  * @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler
-  *
-  * @param void *arg : gpio application-specific interrupt handler argument.
-  *
-  * @return None
-  */
-void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg);
-
-/**
-  * @brief Get gpio interrupts which happens but not processed.
-  *        Please do not call this function in SDK.
-  *
-  * @param None
-  *
-  * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0.
-  */
-uint32_t gpio_intr_pending(void);
-
-/**
-  * @brief Get gpio interrupts which happens but not processed.
-  *        Please do not call this function in SDK.
-  *
-  * @param None
-  *
-  * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32.
-  */
-uint32_t gpio_intr_pending_high(void);
-
-/**
-  * @brief Ack gpio interrupts to process pending interrupts.
-  *        Please do not call this function in SDK.
-  *
-  * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0.
-  *
-  * @return None
-  */
-void gpio_intr_ack(uint32_t ack_mask);
-
-/**
-  * @brief Ack gpio interrupts to process pending interrupts.
-  *        Please do not call this function in SDK.
-  *
-  * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32.
-  *
-  * @return None
-  */
-void gpio_intr_ack_high(uint32_t ack_mask);
-
-/**
-  * @brief Set GPIO to wakeup the ESP32.
-  *        Please do not call this function in SDK.
-  *
-  * @param uint32_t i: gpio number.
-  *
-  * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
-  *
-  * @return None
-  */
-void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
-
-/**
-  * @brief disable GPIOs to wakeup the ESP32.
-  *        Please do not call this function in SDK.
-  *
-  * @param None
-  *
-  * @return None
-  */
-void gpio_pin_wakeup_disable(void);
-
-/**
-  * @brief set gpio input to a signal, one gpio can input to several signals.
-  *
-  * @param uint32_t gpio : gpio number, 0~0x27
-  *                        gpio == 0x30, input 0 to signal
-  *                        gpio == 0x34, ???
-  *                        gpio == 0x38, input 1 to signal
-  *
-  * @param uint32_t signal_idx : signal index.
-  *
-  * @param bool inv : the signal is inv or not
-  *
-  * @return None
-  */
-void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
-
-/**
-  * @brief set signal output to gpio, one signal can output to several gpios.
-  *
-  * @param uint32_t gpio : gpio number, 0~0x27
-  *
-  * @param uint32_t signal_idx : signal index.
-  *                        signal_idx == 0x100, cancel output put to the gpio
-  *
-  * @param bool out_inv : the signal output is inv or not
-  *
-  * @param bool oen_inv : the signal output enable is inv or not
-  *
-  * @return None
-  */
-void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
-
-/**
-  * @brief Select pad as a gpio function from IOMUX.
-  *
-  * @param uint32_t gpio_num : gpio number, 0~0x27
-  *
-  * @return None
-  */
-void gpio_pad_select_gpio(uint8_t gpio_num);
-
-/**
-  * @brief Set pad driver capability.
-  *
-  * @param uint32_t gpio_num : gpio number, 0~0x27
-  *
-  * @param uint8_t drv : 0-3
-  *
-  * @return None
-  */
-void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv);
-
-/**
-  * @brief Pull up the pad from gpio number.
-  *
-  * @param uint32_t gpio_num : gpio number, 0~0x27
-  *
-  * @return None
-  */
-void gpio_pad_pullup(uint8_t gpio_num);
-
-/**
-  * @brief Pull down the pad from gpio number.
-  *
-  * @param uint32_t gpio_num : gpio number, 0~0x27
-  *
-  * @return None
-  */
-void gpio_pad_pulldown(uint8_t gpio_num);
-
-/**
-  * @brief Unhold the pad from gpio number.
-  *
-  * @param uint32_t gpio_num : gpio number, 0~0x27
-  *
-  * @return None
-  */
-void gpio_pad_unhold(uint8_t gpio_num);
-
-/**
-  * @brief Hold the pad from gpio number.
-  *
-  * @param uint32_t gpio_num : gpio number, 0~0x27
-  *
-  * @return None
-  */
-void gpio_pad_hold(uint8_t gpio_num);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_GPIO_H_ */
diff --git a/tools/sdk/include/esp32/rom/libc_stubs.h b/tools/sdk/include/esp32/rom/libc_stubs.h
deleted file mode 100644
index 90c0b446886..00000000000
--- a/tools/sdk/include/esp32/rom/libc_stubs.h
+++ /dev/null
@@ -1,89 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ROM_LIBC_STUBS_H_
-#define _ROM_LIBC_STUBS_H_
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdarg.h>
-#include <reent.h>
-#include <errno.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* 
-ESP32 ROM code contains implementations of some of C library functions.
-Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
-implementation defined in the following struct.
-
-The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and
-`syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU)
-and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script.
-
-So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
-application must allocate syscall table structure for each CPU being used, and populate it with pointers
-to actual implementations of corresponding syscalls.
-*/
-
-struct syscall_stub_table 
-{
-    struct _reent* (*__getreent)(void);
-    void* (*_malloc_r)(struct _reent *r, size_t);
-    void (*_free_r)(struct _reent *r, void*);
-    void* (*_realloc_r)(struct _reent *r, void*, size_t);
-    void* (*_calloc_r)(struct _reent *r, size_t, size_t);
-    void (*_abort)(void);
-    int (*_system_r)(struct _reent *r, const char*);
-    int (*_rename_r)(struct _reent *r, const char*, const char*);
-    clock_t (*_times_r)(struct _reent *r, struct tms *);
-    int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
-    void (*_raise_r)(struct _reent *r); /* function signature is incorrect in ROM */
-    int (*_unlink_r)(struct _reent *r, const char*);
-    int (*_link_r)(struct _reent *r, const char*, const char*);
-    int (*_stat_r)(struct _reent *r, const char*, struct stat *);
-    int (*_fstat_r)(struct _reent *r, int, struct stat *);
-    void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
-    int (*_getpid_r)(struct _reent *r);
-    int (*_kill_r)(struct _reent *r, int, int);
-    void (*_exit_r)(struct _reent *r, int);
-    int (*_close_r)(struct _reent *r, int);
-    int (*_open_r)(struct _reent *r, const char *, int, int);
-    int (*_write_r)(struct _reent *r, int, const void *, int);
-    int (*_lseek_r)(struct _reent *r, int, int, int);
-    int (*_read_r)(struct _reent *r, int, void *, int);
-    void (*_lock_init)(_lock_t *lock);
-    void (*_lock_init_recursive)(_lock_t *lock);
-    void (*_lock_close)(_lock_t *lock);
-    void (*_lock_close_recursive)(_lock_t *lock);
-    void (*_lock_acquire)(_lock_t *lock);
-    void (*_lock_acquire_recursive)(_lock_t *lock);
-    int (*_lock_try_acquire)(_lock_t *lock);
-    int (*_lock_try_acquire_recursive)(_lock_t *lock);
-    void (*_lock_release)(_lock_t *lock);
-    void (*_lock_release_recursive)(_lock_t *lock);
-    int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, _CONST char *, size_t len), va_list * ap);
-    int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
-};
-
-extern struct syscall_stub_table* syscall_table_ptr_pro;
-extern struct syscall_stub_table* syscall_table_ptr_app;
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif /* _ROM_LIBC_STUBS_H_ */
diff --git a/tools/sdk/include/esp32/rom/lldesc.h b/tools/sdk/include/esp32/rom/lldesc.h
deleted file mode 100644
index d027362a51f..00000000000
--- a/tools/sdk/include/esp32/rom/lldesc.h
+++ /dev/null
@@ -1,176 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_LLDESC_H_
-#define _ROM_LLDESC_H_
-
-#include <stdint.h>
-
-#include "queue.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define LLDESC_TX_MBLK_SIZE                 268 /* */
-#define LLDESC_RX_SMBLK_SIZE                64  /* small block size, for small mgmt frame */
-#define LLDESC_RX_MBLK_SIZE                 524 /* rx is large sinec we want to contain mgmt frame in one block*/
-#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE    64  /* it is a small buffer which is a cycle link*/
-#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE      256 /*for ampdu entry*/
-#ifdef ESP_MAC_5
-#define LLDESC_TX_MBLK_NUM                  116  /* 64K / 256 */
-#define LLDESC_RX_MBLK_NUM                  82 /* 64K / 512 MAX 172*/
-#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM     4
-#define LLDESC_RX_AMPDU_LEN_MLBK_NUM       12
-#else
-#ifdef SBUF_RXTX
-#define LLDESC_TX_MBLK_NUM_MAX    (2 * 48) /* 23K / 260 - 8 */
-#define LLDESC_RX_MBLK_NUM_MAX    (2 * 48) /* 23K / 524 */
-#define LLDESC_TX_MBLK_NUM_MIN    (2 * 16) /* 23K / 260 - 8 */
-#define LLDESC_RX_MBLK_NUM_MIN    (2 * 16) /* 23K / 524 */
-#endif
-#define LLDESC_TX_MBLK_NUM      10      //(2 * 32) /* 23K / 260 - 8 */
-
-#ifdef IEEE80211_RX_AMPDU
-#define LLDESC_RX_MBLK_NUM      30
-#else
-#define LLDESC_RX_MBLK_NUM      10
-#endif /*IEEE80211_RX_AMPDU*/
-
-#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM  4
-#define LLDESC_RX_AMPDU_LEN_MLBK_NUM    8
-#endif /* !ESP_MAC_5 */
-/*
- *  SLC2 DMA Desc struct, aka lldesc_t
- * 
- * -------------------------------------------------------------- 
- * | own | EoF | sub_sof | 5'b0   | length [11:0] | size [11:0] |
- * --------------------------------------------------------------
- * |            buf_ptr [31:0]                                  |
- * --------------------------------------------------------------
- * |            next_desc_ptr [31:0]                            |
- * --------------------------------------------------------------
- */
-
-/* this bitfield is start from the LSB!!! */
-typedef struct lldesc_s {
-    volatile uint32_t size  :12,
-                        length:12,
-                        offset: 5, /* h/w reserved 5bit, s/w use it as offset in buffer */
-                        sosf  : 1, /* start of sub-frame */
-                        eof   : 1, /* end of frame */
-                        owner : 1; /* hw or sw */
-    volatile uint8_t *buf;       /* point to buffer data */
-    union{
-        volatile uint32_t empty;
-        STAILQ_ENTRY(lldesc_s) qe;  /* pointing to the next desc */
-    };
-} lldesc_t;
-
-typedef struct tx_ampdu_entry_s{
-    uint32_t sub_len  :12,
-              dili_num : 7,
-                       : 1,
-              null_byte: 2,
-              data     : 1,
-              enc      : 1,
-              seq      : 8;
-} tx_ampdu_entry_t;
-
-typedef struct lldesc_chain_s {
-    lldesc_t *head;
-    lldesc_t *tail;
-} lldesc_chain_t;
-
-#ifdef SBUF_RXTX
-enum sbuf_mask_s  {
-    SBUF_MOVE_NO = 0,
-    SBUF_MOVE_TX2RX,
-    SBUF_MOVE_RX2TX,
-} ;
-
-#define SBUF_MOVE_STEP 8
-#endif
-#define LLDESC_SIZE  sizeof(struct lldesc_s)
-
-/* SLC Descriptor  */
-#define LLDESC_OWNER_MASK                  0x80000000
-#define LLDESC_OWNER_SHIFT                         31
-#define LLDESC_SW_OWNED                             0
-#define LLDESC_HW_OWNED                             1
-
-#define LLDESC_EOF_MASK                    0x40000000
-#define LLDESC_EOF_SHIFT                           30
-
-#define LLDESC_SOSF_MASK                   0x20000000
-#define LLDESC_SOSF_SHIFT                          29
-
-#define LLDESC_LENGTH_MASK                 0x00fff000
-#define LLDESC_LENGTH_SHIFT                        12
-
-#define LLDESC_SIZE_MASK                   0x00000fff
-#define LLDESC_SIZE_SHIFT                           0
-
-#define LLDESC_ADDR_MASK                    0x000fffff
-
-void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t * mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner,
-                          lldesc_t **head,
-#ifdef TO_HOST_RESTART
-                          lldesc_t ** one_before_tail,
-#endif
-                          lldesc_t **tail);
-
-lldesc_t *lldesc_num2link(lldesc_t * head, uint16_t nblks);
-
-lldesc_t *lldesc_set_owner(lldesc_t * head, uint16_t nblks, uint8_t owner);
-
-static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
-{
-    lldesc_t *ds = head;
-    uint32_t len = 0;
-    
-    while (ds) {
-        len += ds->length;
-        ds = STAILQ_NEXT(ds, qe);
-    }
-    
-    return len;
-}
-
-static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
-{
-    ds->owner  = owner;
-    ds->eof    = eof;
-    ds->sosf   = sosf;
-    ds->length = len;
-}
-
-#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len)        do { \
-        (_desc)->owner  = (_owner); \
-        (_desc)->eof    = (_eof);   \
-        (_desc)->sosf   = (_sosf);  \
-        (_desc)->length = (_len);   \
-} while(0)
-
-#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
-
-#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
-
-#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_LLDESC_H_ */
diff --git a/tools/sdk/include/esp32/rom/md5_hash.h b/tools/sdk/include/esp32/rom/md5_hash.h
deleted file mode 100644
index f116f1e670f..00000000000
--- a/tools/sdk/include/esp32/rom/md5_hash.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * MD5 internal definitions
- * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef _ROM_MD5_HASH_H_
-#define _ROM_MD5_HASH_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct MD5Context {
-	uint32_t buf[4];
-	uint32_t bits[2];
-	uint8_t in[64];
-};
-
-void MD5Init(struct MD5Context *context);
-void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
-void MD5Final(unsigned char digest[16], struct MD5Context *context);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_MD5_HASH_H_ */
diff --git a/tools/sdk/include/esp32/rom/miniz.h b/tools/sdk/include/esp32/rom/miniz.h
deleted file mode 100644
index ed79beb2cbd..00000000000
--- a/tools/sdk/include/esp32/rom/miniz.h
+++ /dev/null
@@ -1,777 +0,0 @@
-#ifndef MINIZ_HEADER_INCLUDED
-#define MINIZ_HEADER_INCLUDED
-
-#include <stdlib.h>
-
-// Defines to completely disable specific portions of miniz.c:
-// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl.
-
-// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O.
-#define MINIZ_NO_STDIO
-
-// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or
-// get/set file times, and the C run-time funcs that get/set times won't be called.
-// The current downside is the times written to your archives will be from 1979.
-#define MINIZ_NO_TIME
-
-// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's.
-#define MINIZ_NO_ARCHIVE_APIS
-
-// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's.
-#define MINIZ_NO_ARCHIVE_WRITING_APIS
-
-// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's.
-#define MINIZ_NO_ZLIB_APIS
-
-// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib.
-#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES
-
-// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc.
-// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc
-// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user
-// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work.
-#define MINIZ_NO_MALLOC
-
-#if defined(__TINYC__) && (defined(__linux) || defined(__linux__))
-  // TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux
-  #define MINIZ_NO_TIME
-#endif
-
-#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS)
-  #include <time.h>
-#endif
-
-//Hardcoded options for Xtensa - JD
-#define MINIZ_X86_OR_X64_CPU 0
-#define MINIZ_LITTLE_ENDIAN 1
-#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0
-#define MINIZ_HAS_64BIT_REGISTERS 0
-#define TINFL_USE_64BIT_BITBUF 0
-
-
-#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__)
-// MINIZ_X86_OR_X64_CPU is only used to help set the below macros.
-#define MINIZ_X86_OR_X64_CPU 1
-#endif
-
-#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU
-// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian.
-#define MINIZ_LITTLE_ENDIAN 1
-#endif
-
-#if MINIZ_X86_OR_X64_CPU
-// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses.
-#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1
-#endif
-
-#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__)
-// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions).
-#define MINIZ_HAS_64BIT_REGISTERS 1
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ------------------- zlib-style API Definitions.
-
-// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits!
-typedef unsigned long mz_ulong;
-
-// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap.
-void mz_free(void *p);
-
-#define MZ_ADLER32_INIT (1)
-// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL.
-mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len);
-
-#define MZ_CRC32_INIT (0)
-// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL.
-mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len);
-
-// Compression strategies.
-enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 };
-
-// Method
-#define MZ_DEFLATED 8
-
-#ifndef MINIZ_NO_ZLIB_APIS
-
-// Heap allocation callbacks.
-// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long.
-typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size);
-typedef void (*mz_free_func)(void *opaque, void *address);
-typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size);
-
-#define MZ_VERSION          "9.1.15"
-#define MZ_VERNUM           0x91F0
-#define MZ_VER_MAJOR        9
-#define MZ_VER_MINOR        1
-#define MZ_VER_REVISION     15
-#define MZ_VER_SUBREVISION  0
-
-// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs).
-enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 };
-
-// Return status codes. MZ_PARAM_ERROR is non-standard.
-enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 };
-
-// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL.
-enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 };
-
-// Window bits
-#define MZ_DEFAULT_WINDOW_BITS 15
-
-struct mz_internal_state;
-
-// Compression/decompression stream struct.
-typedef struct mz_stream_s
-{
-  const unsigned char *next_in;     // pointer to next byte to read
-  unsigned int avail_in;            // number of bytes available at next_in
-  mz_ulong total_in;                // total number of bytes consumed so far
-
-  unsigned char *next_out;          // pointer to next byte to write
-  unsigned int avail_out;           // number of bytes that can be written to next_out
-  mz_ulong total_out;               // total number of bytes produced so far
-
-  char *msg;                        // error msg (unused)
-  struct mz_internal_state *state;  // internal state, allocated by zalloc/zfree
-
-  mz_alloc_func zalloc;             // optional heap allocation function (defaults to malloc)
-  mz_free_func zfree;               // optional heap free function (defaults to free)
-  void *opaque;                     // heap alloc function user pointer
-
-  int data_type;                    // data_type (unused)
-  mz_ulong adler;                   // adler32 of the source or uncompressed data
-  mz_ulong reserved;                // not used
-} mz_stream;
-
-typedef mz_stream *mz_streamp;
-
-// Returns the version string of miniz.c.
-const char *mz_version(void);
-
-// mz_deflateInit() initializes a compressor with default options:
-// Parameters:
-//  pStream must point to an initialized mz_stream struct.
-//  level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION].
-//  level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio.
-//  (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.)
-// Return values:
-//  MZ_OK on success.
-//  MZ_STREAM_ERROR if the stream is bogus.
-//  MZ_PARAM_ERROR if the input parameters are bogus.
-//  MZ_MEM_ERROR on out of memory.
-int mz_deflateInit(mz_streamp pStream, int level);
-
-// mz_deflateInit2() is like mz_deflate(), except with more control:
-// Additional parameters:
-//   method must be MZ_DEFLATED
-//   window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer)
-//   mem_level must be between [1, 9] (it's checked but ignored by miniz.c)
-int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy);
-
-// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2().
-int mz_deflateReset(mz_streamp pStream);
-
-// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible.
-// Parameters:
-//   pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
-//   flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH.
-// Return values:
-//   MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full).
-//   MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore.
-//   MZ_STREAM_ERROR if the stream is bogus.
-//   MZ_PARAM_ERROR if one of the parameters is invalid.
-//   MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.)
-int mz_deflate(mz_streamp pStream, int flush);
-
-// mz_deflateEnd() deinitializes a compressor:
-// Return values:
-//  MZ_OK on success.
-//  MZ_STREAM_ERROR if the stream is bogus.
-int mz_deflateEnd(mz_streamp pStream);
-
-// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH.
-mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len);
-
-// Single-call compression functions mz_compress() and mz_compress2():
-// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure.
-int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
-int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level);
-
-// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress().
-mz_ulong mz_compressBound(mz_ulong source_len);
-
-// Initializes a decompressor.
-int mz_inflateInit(mz_streamp pStream);
-
-// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer:
-// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate).
-int mz_inflateInit2(mz_streamp pStream, int window_bits);
-
-// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible.
-// Parameters:
-//   pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
-//   flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH.
-//   On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster).
-//   MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data.
-// Return values:
-//   MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full.
-//   MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified.
-//   MZ_STREAM_ERROR if the stream is bogus.
-//   MZ_DATA_ERROR if the deflate stream is invalid.
-//   MZ_PARAM_ERROR if one of the parameters is invalid.
-//   MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again
-//   with more input data, or with more room in the output buffer (except when using single call decompression, described above).
-int mz_inflate(mz_streamp pStream, int flush);
-
-// Deinitializes a decompressor.
-int mz_inflateEnd(mz_streamp pStream);
-
-// Single-call decompression.
-// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure.
-int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
-
-// Returns a string description of the specified error code, or NULL if the error code is invalid.
-const char *mz_error(int err);
-
-// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports.
-// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project.
-#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
-  typedef unsigned char Byte;
-  typedef unsigned int uInt;
-  typedef mz_ulong uLong;
-  typedef Byte Bytef;
-  typedef uInt uIntf;
-  typedef char charf;
-  typedef int intf;
-  typedef void *voidpf;
-  typedef uLong uLongf;
-  typedef void *voidp;
-  typedef void *const voidpc;
-  #define Z_NULL                0
-  #define Z_NO_FLUSH            MZ_NO_FLUSH
-  #define Z_PARTIAL_FLUSH       MZ_PARTIAL_FLUSH
-  #define Z_SYNC_FLUSH          MZ_SYNC_FLUSH
-  #define Z_FULL_FLUSH          MZ_FULL_FLUSH
-  #define Z_FINISH              MZ_FINISH
-  #define Z_BLOCK               MZ_BLOCK
-  #define Z_OK                  MZ_OK
-  #define Z_STREAM_END          MZ_STREAM_END
-  #define Z_NEED_DICT           MZ_NEED_DICT
-  #define Z_ERRNO               MZ_ERRNO
-  #define Z_STREAM_ERROR        MZ_STREAM_ERROR
-  #define Z_DATA_ERROR          MZ_DATA_ERROR
-  #define Z_MEM_ERROR           MZ_MEM_ERROR
-  #define Z_BUF_ERROR           MZ_BUF_ERROR
-  #define Z_VERSION_ERROR       MZ_VERSION_ERROR
-  #define Z_PARAM_ERROR         MZ_PARAM_ERROR
-  #define Z_NO_COMPRESSION      MZ_NO_COMPRESSION
-  #define Z_BEST_SPEED          MZ_BEST_SPEED
-  #define Z_BEST_COMPRESSION    MZ_BEST_COMPRESSION
-  #define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION
-  #define Z_DEFAULT_STRATEGY    MZ_DEFAULT_STRATEGY
-  #define Z_FILTERED            MZ_FILTERED
-  #define Z_HUFFMAN_ONLY        MZ_HUFFMAN_ONLY
-  #define Z_RLE                 MZ_RLE
-  #define Z_FIXED               MZ_FIXED
-  #define Z_DEFLATED            MZ_DEFLATED
-  #define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS
-  #define alloc_func            mz_alloc_func
-  #define free_func             mz_free_func
-  #define internal_state        mz_internal_state
-  #define z_stream              mz_stream
-  #define deflateInit           mz_deflateInit
-  #define deflateInit2          mz_deflateInit2
-  #define deflateReset          mz_deflateReset
-  #define deflate               mz_deflate
-  #define deflateEnd            mz_deflateEnd
-  #define deflateBound          mz_deflateBound
-  #define compress              mz_compress
-  #define compress2             mz_compress2
-  #define compressBound         mz_compressBound
-  #define inflateInit           mz_inflateInit
-  #define inflateInit2          mz_inflateInit2
-  #define inflate               mz_inflate
-  #define inflateEnd            mz_inflateEnd
-  #define uncompress            mz_uncompress
-  #define crc32                 mz_crc32
-  #define adler32               mz_adler32
-  #define MAX_WBITS             15
-  #define MAX_MEM_LEVEL         9
-  #define zError                mz_error
-  #define ZLIB_VERSION          MZ_VERSION
-  #define ZLIB_VERNUM           MZ_VERNUM
-  #define ZLIB_VER_MAJOR        MZ_VER_MAJOR
-  #define ZLIB_VER_MINOR        MZ_VER_MINOR
-  #define ZLIB_VER_REVISION     MZ_VER_REVISION
-  #define ZLIB_VER_SUBREVISION  MZ_VER_SUBREVISION
-  #define zlibVersion           mz_version
-  #define zlib_version          mz_version()
-#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
-
-#endif // MINIZ_NO_ZLIB_APIS
-
-// ------------------- Types and macros
-
-typedef unsigned char mz_uint8;
-typedef signed short mz_int16;
-typedef unsigned short mz_uint16;
-typedef unsigned int mz_uint32;
-typedef unsigned int mz_uint;
-typedef long long mz_int64;
-typedef unsigned long long mz_uint64;
-typedef int mz_bool;
-
-#define MZ_FALSE (0)
-#define MZ_TRUE (1)
-
-// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message.
-#ifdef _MSC_VER
-   #define MZ_MACRO_END while (0, 0)
-#else
-   #define MZ_MACRO_END while (0)
-#endif
-
-// ------------------- ZIP archive reading/writing
-
-#ifndef MINIZ_NO_ARCHIVE_APIS
-
-enum
-{
-  MZ_ZIP_MAX_IO_BUF_SIZE = 64*1024,
-  MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260,
-  MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256
-};
-
-typedef struct
-{
-  mz_uint32 m_file_index;
-  mz_uint32 m_central_dir_ofs;
-  mz_uint16 m_version_made_by;
-  mz_uint16 m_version_needed;
-  mz_uint16 m_bit_flag;
-  mz_uint16 m_method;
-#ifndef MINIZ_NO_TIME
-  time_t m_time;
-#endif
-  mz_uint32 m_crc32;
-  mz_uint64 m_comp_size;
-  mz_uint64 m_uncomp_size;
-  mz_uint16 m_internal_attr;
-  mz_uint32 m_external_attr;
-  mz_uint64 m_local_header_ofs;
-  mz_uint32 m_comment_size;
-  char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE];
-  char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE];
-} mz_zip_archive_file_stat;
-
-typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n);
-typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n);
-
-struct mz_zip_internal_state_tag;
-typedef struct mz_zip_internal_state_tag mz_zip_internal_state;
-
-typedef enum
-{
-  MZ_ZIP_MODE_INVALID = 0,
-  MZ_ZIP_MODE_READING = 1,
-  MZ_ZIP_MODE_WRITING = 2,
-  MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3
-} mz_zip_mode;
-
-typedef struct mz_zip_archive_tag
-{
-  mz_uint64 m_archive_size;
-  mz_uint64 m_central_directory_file_ofs;
-  mz_uint m_total_files;
-  mz_zip_mode m_zip_mode;
-
-  mz_uint m_file_offset_alignment;
-
-  mz_alloc_func m_pAlloc;
-  mz_free_func m_pFree;
-  mz_realloc_func m_pRealloc;
-  void *m_pAlloc_opaque;
-
-  mz_file_read_func m_pRead;
-  mz_file_write_func m_pWrite;
-  void *m_pIO_opaque;
-
-  mz_zip_internal_state *m_pState;
-
-} mz_zip_archive;
-
-typedef enum
-{
-  MZ_ZIP_FLAG_CASE_SENSITIVE                = 0x0100,
-  MZ_ZIP_FLAG_IGNORE_PATH                   = 0x0200,
-  MZ_ZIP_FLAG_COMPRESSED_DATA               = 0x0400,
-  MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800
-} mz_zip_flags;
-
-// ZIP archive reading
-
-// Inits a ZIP archive reader.
-// These functions read and validate the archive's central directory.
-mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags);
-mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags);
-
-#ifndef MINIZ_NO_STDIO
-mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags);
-#endif
-
-// Returns the total number of files in the archive.
-mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip);
-
-// Returns detailed information about an archive file entry.
-mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat);
-
-// Determines if an archive file entry is a directory entry.
-mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index);
-mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index);
-
-// Retrieves the filename of an archive file entry.
-// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename.
-mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size);
-
-// Attempts to locates a file in the archive's central directory.
-// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH
-// Returns -1 if the file cannot be found.
-int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags);
-
-// Extracts a archive file to a memory buffer using no memory allocation.
-mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
-mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
-
-// Extracts a archive file to a memory buffer.
-mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags);
-mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags);
-
-// Extracts a archive file to a dynamically allocated heap buffer.
-void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags);
-void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags);
-
-// Extracts a archive file using a callback function to output the file's data.
-mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
-mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
-
-#ifndef MINIZ_NO_STDIO
-// Extracts a archive file to a disk file and sets its last accessed and modified times.
-// This function only extracts files, not archive directory records.
-mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags);
-mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags);
-#endif
-
-// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used.
-mz_bool mz_zip_reader_end(mz_zip_archive *pZip);
-
-// ZIP archive writing
-
-#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
-
-// Inits a ZIP archive writer.
-mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size);
-mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size);
-
-#ifndef MINIZ_NO_STDIO
-mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning);
-#endif
-
-// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive.
-// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called.
-// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it).
-// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL.
-// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before
-// the archive is finalized the file's central directory will be hosed.
-mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename);
-
-// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive.
-// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer.
-// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
-mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags);
-mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32);
-
-#ifndef MINIZ_NO_STDIO
-// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive.
-// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
-mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
-#endif
-
-// Adds a file to an archive by fully cloning the data from another archive.
-// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields.
-mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index);
-
-// Finalizes the archive by writing the central directory records followed by the end of central directory record.
-// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end().
-// An archive must be manually finalized by calling this function for it to be valid.
-mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip);
-mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize);
-
-// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used.
-// Note for the archive to be valid, it must have been finalized before ending.
-mz_bool mz_zip_writer_end(mz_zip_archive *pZip);
-
-// Misc. high-level helper functions:
-
-// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive.
-// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
-mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
-
-// Reads a single file from an archive into a heap block.
-// Returns NULL on failure.
-void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags);
-
-#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
-
-#endif // #ifndef MINIZ_NO_ARCHIVE_APIS
-
-// ------------------- Low-level Decompression API Definitions
-
-// Decompression flags used by tinfl_decompress().
-// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream.
-// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input.
-// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB).
-// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes.
-enum
-{
-  TINFL_FLAG_PARSE_ZLIB_HEADER = 1,
-  TINFL_FLAG_HAS_MORE_INPUT = 2,
-  TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4,
-  TINFL_FLAG_COMPUTE_ADLER32 = 8
-};
-
-// High level decompression functions:
-// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc().
-// On entry:
-//  pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress.
-// On return:
-//  Function returns a pointer to the decompressed data, or NULL on failure.
-//  *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data.
-//  The caller must call mz_free() on the returned block when it's no longer needed.
-void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
-
-// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory.
-// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success.
-#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1))
-size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
-
-// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer.
-// Returns 1 on success or 0 on failure.
-typedef int (*tinfl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
-int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
-
-struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor;
-
-// Max size of LZ dictionary.
-#define TINFL_LZ_DICT_SIZE 32768
-
-// Return status.
-typedef enum
-{
-  TINFL_STATUS_BAD_PARAM = -3,
-  TINFL_STATUS_ADLER32_MISMATCH = -2,
-  TINFL_STATUS_FAILED = -1,
-  TINFL_STATUS_DONE = 0,
-  TINFL_STATUS_NEEDS_MORE_INPUT = 1,
-  TINFL_STATUS_HAS_MORE_OUTPUT = 2
-} tinfl_status;
-
-// Initializes the decompressor to its initial state.
-#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END
-#define tinfl_get_adler32(r) (r)->m_check_adler32
-
-// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability.
-// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output.
-tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags);
-
-// Internal/private bits follow.
-enum
-{
-  TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19,
-  TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS
-};
-
-typedef struct
-{
-  mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0];
-  mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2];
-} tinfl_huff_table;
-
-#if MINIZ_HAS_64BIT_REGISTERS
-  #define TINFL_USE_64BIT_BITBUF 1
-#endif
-
-#if TINFL_USE_64BIT_BITBUF
-  typedef mz_uint64 tinfl_bit_buf_t;
-  #define TINFL_BITBUF_SIZE (64)
-#else
-  typedef mz_uint32 tinfl_bit_buf_t;
-  #define TINFL_BITBUF_SIZE (32)
-#endif
-
-struct tinfl_decompressor_tag
-{
-  mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES];
-  tinfl_bit_buf_t m_bit_buf;
-  size_t m_dist_from_out_buf_start;
-  tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES];
-  mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137];
-};
-
-// ------------------- Low-level Compression API Definitions
-
-// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently).
-#define TDEFL_LESS_MEMORY 1
-
-// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search):
-// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression).
-enum
-{
-  TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF
-};
-
-// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data.
-// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers).
-// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing.
-// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory).
-// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1)
-// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled.
-// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables.
-// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks.
-// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK).
-enum
-{
-  TDEFL_WRITE_ZLIB_HEADER             = 0x01000,
-  TDEFL_COMPUTE_ADLER32               = 0x02000,
-  TDEFL_GREEDY_PARSING_FLAG           = 0x04000,
-  TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000,
-  TDEFL_RLE_MATCHES                   = 0x10000,
-  TDEFL_FILTER_MATCHES                = 0x20000,
-  TDEFL_FORCE_ALL_STATIC_BLOCKS       = 0x40000,
-  TDEFL_FORCE_ALL_RAW_BLOCKS          = 0x80000
-};
-
-// High level compression functions:
-// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc().
-// On entry:
-//  pSrc_buf, src_buf_len: Pointer and size of source block to compress.
-//  flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression.
-// On return:
-//  Function returns a pointer to the compressed data, or NULL on failure.
-//  *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data.
-//  The caller must free() the returned block when it's no longer needed.
-void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
-
-// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory.
-// Returns 0 on failure.
-size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
-
-// Compresses an image to a compressed PNG file in memory.
-// On entry:
-//  pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4. 
-//  The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory.
-//  level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL
-//  If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps).
-// On return:
-//  Function returns a pointer to the compressed data, or NULL on failure.
-//  *pLen_out will be set to the size of the PNG image file.
-//  The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed.
-void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip);
-void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out);
-
-// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time.
-typedef mz_bool (*tdefl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
-
-// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally.
-mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
-
-enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 };
-
-// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes).
-#if TDEFL_LESS_MEMORY
-enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
-#else
-enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
-#endif
-
-// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions.
-typedef enum
-{
-  TDEFL_STATUS_BAD_PARAM = -2,
-  TDEFL_STATUS_PUT_BUF_FAILED = -1,
-  TDEFL_STATUS_OKAY = 0,
-  TDEFL_STATUS_DONE = 1,
-} tdefl_status;
-
-// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums
-typedef enum
-{
-  TDEFL_NO_FLUSH = 0,
-  TDEFL_SYNC_FLUSH = 2,
-  TDEFL_FULL_FLUSH = 3,
-  TDEFL_FINISH = 4
-} tdefl_flush;
-
-// tdefl's compression state structure.
-typedef struct
-{
-  tdefl_put_buf_func_ptr m_pPut_buf_func;
-  void *m_pPut_buf_user;
-  mz_uint m_flags, m_max_probes[2];
-  int m_greedy_parsing;
-  mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size;
-  mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end;
-  mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer;
-  mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish;
-  tdefl_status m_prev_return_status;
-  const void *m_pIn_buf;
-  void *m_pOut_buf;
-  size_t *m_pIn_buf_size, *m_pOut_buf_size;
-  tdefl_flush m_flush;
-  const mz_uint8 *m_pSrc;
-  size_t m_src_buf_left, m_out_buf_ofs;
-  mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1];
-  mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
-  mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
-  mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
-  mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE];
-  mz_uint16 m_next[TDEFL_LZ_DICT_SIZE];
-  mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE];
-  mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE];
-} tdefl_compressor;
-
-// Initializes the compressor.
-// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory.
-// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression.
-// If pBut_buf_func is NULL the user should always call the tdefl_compress() API.
-// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.)
-tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
-
-// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible.
-tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush);
-
-// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr.
-// tdefl_compress_buffer() always consumes the entire input buffer.
-tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush);
-
-tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d);
-mz_uint32 tdefl_get_adler32(tdefl_compressor *d);
-
-// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros.
-#ifndef MINIZ_NO_ZLIB_APIS
-// Create tdefl_compress() flags given zlib-style compression parameters.
-// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files)
-// window_bits may be -15 (raw deflate) or 15 (zlib)
-// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED
-mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy);
-#endif // #ifndef MINIZ_NO_ZLIB_APIS
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // MINIZ_HEADER_INCLUDED
-
diff --git a/tools/sdk/include/esp32/rom/queue.h b/tools/sdk/include/esp32/rom/queue.h
deleted file mode 100644
index 29ee6706009..00000000000
--- a/tools/sdk/include/esp32/rom/queue.h
+++ /dev/null
@@ -1,645 +0,0 @@
-/*-
- * Copyright (c) 1991, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)queue.h	8.5 (Berkeley) 8/20/94
- * $FreeBSD$
- */
-
-#ifndef _SYS_QUEUE_H_
-#define _SYS_QUEUE_H_
-
-#include <sys/cdefs.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * This file defines four types of data structures: singly-linked lists,
- * singly-linked tail queues, lists and tail queues.
- *
- * A singly-linked list is headed by a single forward pointer. The elements
- * are singly linked for minimum space and pointer manipulation overhead at
- * the expense of O(n) removal for arbitrary elements. New elements can be
- * added to the list after an existing element or at the head of the list.
- * Elements being removed from the head of the list should use the explicit
- * macro for this purpose for optimum efficiency. A singly-linked list may
- * only be traversed in the forward direction.  Singly-linked lists are ideal
- * for applications with large datasets and few or no removals or for
- * implementing a LIFO queue.
- *
- * A singly-linked tail queue is headed by a pair of pointers, one to the
- * head of the list and the other to the tail of the list. The elements are
- * singly linked for minimum space and pointer manipulation overhead at the
- * expense of O(n) removal for arbitrary elements. New elements can be added
- * to the list after an existing element, at the head of the list, or at the
- * end of the list. Elements being removed from the head of the tail queue
- * should use the explicit macro for this purpose for optimum efficiency.
- * A singly-linked tail queue may only be traversed in the forward direction.
- * Singly-linked tail queues are ideal for applications with large datasets
- * and few or no removals or for implementing a FIFO queue.
- *
- * A list is headed by a single forward pointer (or an array of forward
- * pointers for a hash table header). The elements are doubly linked
- * so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before
- * or after an existing element or at the head of the list. A list
- * may only be traversed in the forward direction.
- *
- * A tail queue is headed by a pair of pointers, one to the head of the
- * list and the other to the tail of the list. The elements are doubly
- * linked so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before or
- * after an existing element, at the head of the list, or at the end of
- * the list. A tail queue may be traversed in either direction.
- *
- * For details on the use of these macros, see the queue(3) manual page.
- *
- *
- *				SLIST	LIST	STAILQ	TAILQ
- * _HEAD			+	+	+	+
- * _HEAD_INITIALIZER		+	+	+	+
- * _ENTRY			+	+	+	+
- * _INIT			+	+	+	+
- * _EMPTY			+	+	+	+
- * _FIRST			+	+	+	+
- * _NEXT			+	+	+	+
- * _PREV			-	-	-	+
- * _LAST			-	-	+	+
- * _FOREACH			+	+	+	+
- * _FOREACH_SAFE		+	+	+	+
- * _FOREACH_REVERSE		-	-	-	+
- * _FOREACH_REVERSE_SAFE	-	-	-	+
- * _INSERT_HEAD			+	+	+	+
- * _INSERT_BEFORE		-	+	-	+
- * _INSERT_AFTER		+	+	+	+
- * _INSERT_TAIL			-	-	+	+
- * _CONCAT			-	-	+	+
- * _REMOVE_AFTER		+	-	+	-
- * _REMOVE_HEAD			+	-	+	-
- * _REMOVE			+	+	+	+
- *
- */
-#ifdef QUEUE_MACRO_DEBUG
-/* Store the last 2 places the queue element or head was altered */
-struct qm_trace {
-	char * lastfile;
-	int lastline;
-	char * prevfile;
-	int prevline;
-};
-
-#define	TRACEBUF	struct qm_trace trace;
-#define	TRASHIT(x)	do {(x) = (void *)-1;} while (0)
-#define	QMD_SAVELINK(name, link)	void **name = (void *)&(link)
-
-#define	QMD_TRACE_HEAD(head) do {					\
-	(head)->trace.prevline = (head)->trace.lastline;		\
-	(head)->trace.prevfile = (head)->trace.lastfile;		\
-	(head)->trace.lastline = __LINE__;				\
-	(head)->trace.lastfile = __FILE__;				\
-} while (0)
-
-#define	QMD_TRACE_ELEM(elem) do {					\
-	(elem)->trace.prevline = (elem)->trace.lastline;		\
-	(elem)->trace.prevfile = (elem)->trace.lastfile;		\
-	(elem)->trace.lastline = __LINE__;				\
-	(elem)->trace.lastfile = __FILE__;				\
-} while (0)
-
-#else
-#define	QMD_TRACE_ELEM(elem)
-#define	QMD_TRACE_HEAD(head)
-#define	QMD_SAVELINK(name, link)
-#define	TRACEBUF
-#define	TRASHIT(x)
-#endif	/* QUEUE_MACRO_DEBUG */
-
-/*
- * Singly-linked List declarations.
- */
-#define	SLIST_HEAD(name, type)						\
-struct name {								\
-	struct type *slh_first;	/* first element */			\
-}
-
-#define	SLIST_HEAD_INITIALIZER(head)					\
-	{ NULL }
-
-#define	SLIST_ENTRY(type)						\
-struct {								\
-	struct type *sle_next;	/* next element */			\
-}
-
-/*
- * Singly-linked List functions.
- */
-#define	SLIST_EMPTY(head)	((head)->slh_first == NULL)
-
-#define	SLIST_FIRST(head)	((head)->slh_first)
-
-#define	SLIST_FOREACH(var, head, field)					\
-	for ((var) = SLIST_FIRST((head));				\
-	    (var);							\
-	    (var) = SLIST_NEXT((var), field))
-
-#define	SLIST_FOREACH_SAFE(var, head, field, tvar)			\
-	for ((var) = SLIST_FIRST((head));				\
-	    (var) && ((tvar) = SLIST_NEXT((var), field), 1);		\
-	    (var) = (tvar))
-
-#define	SLIST_FOREACH_PREVPTR(var, varp, head, field)			\
-	for ((varp) = &SLIST_FIRST((head));				\
-	    ((var) = *(varp)) != NULL;					\
-	    (varp) = &SLIST_NEXT((var), field))
-
-#define	SLIST_INIT(head) do {						\
-	SLIST_FIRST((head)) = NULL;					\
-} while (0)
-
-#define	SLIST_INSERT_AFTER(slistelm, elm, field) do {			\
-	SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field);	\
-	SLIST_NEXT((slistelm), field) = (elm);				\
-} while (0)
-
-#define	SLIST_INSERT_HEAD(head, elm, field) do {			\
-	SLIST_NEXT((elm), field) = SLIST_FIRST((head));			\
-	SLIST_FIRST((head)) = (elm);					\
-} while (0)
-
-#define	SLIST_NEXT(elm, field)	((elm)->field.sle_next)
-
-#define	SLIST_REMOVE(head, elm, type, field) do {			\
-	QMD_SAVELINK(oldnext, (elm)->field.sle_next);			\
-	if (SLIST_FIRST((head)) == (elm)) {				\
-		SLIST_REMOVE_HEAD((head), field);			\
-	}								\
-	else {								\
-		struct type *curelm = SLIST_FIRST((head));		\
-		while (SLIST_NEXT(curelm, field) != (elm))		\
-			curelm = SLIST_NEXT(curelm, field);		\
-		SLIST_REMOVE_AFTER(curelm, field);			\
-	}								\
-	TRASHIT(*oldnext);						\
-} while (0)
-
-#define SLIST_REMOVE_AFTER(elm, field) do {				\
-	SLIST_NEXT(elm, field) =					\
-	    SLIST_NEXT(SLIST_NEXT(elm, field), field);			\
-} while (0)
-
-#define	SLIST_REMOVE_HEAD(head, field) do {				\
-	SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field);	\
-} while (0)
-
-/*
- * Singly-linked Tail queue declarations.
- */
-#define	STAILQ_HEAD(name, type)						\
-struct name {								\
-	struct type *stqh_first;/* first element */			\
-	struct type **stqh_last;/* addr of last next element */		\
-}
-
-#define	STAILQ_HEAD_INITIALIZER(head)					\
-	{ NULL, &(head).stqh_first }
-
-#define	STAILQ_ENTRY(type)						\
-struct {								\
-	struct type *stqe_next;	/* next element */			\
-}
-
-/*
- * Singly-linked Tail queue functions.
- */
-#define	STAILQ_CONCAT(head1, head2) do {				\
-	if (!STAILQ_EMPTY((head2))) {					\
-		*(head1)->stqh_last = (head2)->stqh_first;		\
-		(head1)->stqh_last = (head2)->stqh_last;		\
-		STAILQ_INIT((head2));					\
-	}								\
-} while (0)
-
-#define	STAILQ_EMPTY(head)	((head)->stqh_first == NULL)
-
-#define	STAILQ_FIRST(head)	((head)->stqh_first)
-
-#define	STAILQ_FOREACH(var, head, field)				\
-	for((var) = STAILQ_FIRST((head));				\
-	   (var);							\
-	   (var) = STAILQ_NEXT((var), field))
-
-
-#define	STAILQ_FOREACH_SAFE(var, head, field, tvar)			\
-	for ((var) = STAILQ_FIRST((head));				\
-	    (var) && ((tvar) = STAILQ_NEXT((var), field), 1);		\
-	    (var) = (tvar))
-
-#define	STAILQ_INIT(head) do {						\
-	STAILQ_FIRST((head)) = NULL;					\
-	(head)->stqh_last = &STAILQ_FIRST((head));			\
-} while (0)
-
-#define	STAILQ_INSERT_AFTER(head, tqelm, elm, field) do {		\
-	if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
-		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
-	STAILQ_NEXT((tqelm), field) = (elm);				\
-} while (0)
-
-#define	STAILQ_INSERT_HEAD(head, elm, field) do {			\
-	if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL)	\
-		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
-	STAILQ_FIRST((head)) = (elm);					\
-} while (0)
-
-#define	STAILQ_INSERT_TAIL(head, elm, field) do {			\
-	STAILQ_NEXT((elm), field) = NULL;				\
-	*(head)->stqh_last = (elm);					\
-	(head)->stqh_last = &STAILQ_NEXT((elm), field);			\
-} while (0)
-
-#define	STAILQ_LAST(head, type, field)					\
-	(STAILQ_EMPTY((head)) ?						\
-		NULL :							\
-	        ((struct type *)(void *)				\
-		((char *)((head)->stqh_last) - __offsetof(struct type, field))))
-
-#define	STAILQ_NEXT(elm, field)	((elm)->field.stqe_next)
-
-#define	STAILQ_REMOVE(head, elm, type, field) do {			\
-	QMD_SAVELINK(oldnext, (elm)->field.stqe_next);			\
-	if (STAILQ_FIRST((head)) == (elm)) {				\
-		STAILQ_REMOVE_HEAD((head), field);			\
-	}								\
-	else {								\
-		struct type *curelm = STAILQ_FIRST((head));		\
-		while (STAILQ_NEXT(curelm, field) != (elm))		\
-			curelm = STAILQ_NEXT(curelm, field);		\
-		STAILQ_REMOVE_AFTER(head, curelm, field);		\
-	}								\
-	TRASHIT(*oldnext);						\
-} while (0)
-
-#define	STAILQ_REMOVE_HEAD(head, field) do {				\
-	if ((STAILQ_FIRST((head)) =					\
-	     STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL)		\
-		(head)->stqh_last = &STAILQ_FIRST((head));		\
-} while (0)
-
-#define STAILQ_REMOVE_AFTER(head, elm, field) do {			\
-	if ((STAILQ_NEXT(elm, field) =					\
-	     STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL)	\
-		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
-} while (0)
-
-#define STAILQ_SWAP(head1, head2, type) do {				\
-	struct type *swap_first = STAILQ_FIRST(head1);			\
-	struct type **swap_last = (head1)->stqh_last;			\
-	STAILQ_FIRST(head1) = STAILQ_FIRST(head2);			\
-	(head1)->stqh_last = (head2)->stqh_last;			\
-	STAILQ_FIRST(head2) = swap_first;				\
-	(head2)->stqh_last = swap_last;					\
-	if (STAILQ_EMPTY(head1))					\
-		(head1)->stqh_last = &STAILQ_FIRST(head1);		\
-	if (STAILQ_EMPTY(head2))					\
-		(head2)->stqh_last = &STAILQ_FIRST(head2);		\
-} while (0)
-
-#define STAILQ_INSERT_CHAIN_HEAD(head, elm_chead, elm_ctail, field) do {   \
-    if ((STAILQ_NEXT(elm_ctail, field) = STAILQ_FIRST(head)) == NULL ) { \
-        (head)->stqh_last = &STAILQ_NEXT(elm_ctail, field);            \
-    }                                                                      \
-    STAILQ_FIRST(head) = (elm_chead);                                    \
-} while (0)
-
-
-/*
- * List declarations.
- */
-#define	LIST_HEAD(name, type)						\
-struct name {								\
-	struct type *lh_first;	/* first element */			\
-}
-
-#define	LIST_HEAD_INITIALIZER(head)					\
-	{ NULL }
-
-#define	LIST_ENTRY(type)						\
-struct {								\
-	struct type *le_next;	/* next element */			\
-	struct type **le_prev;	/* address of previous next element */	\
-}
-
-/*
- * List functions.
- */
-
-#if (defined(_KERNEL) && defined(INVARIANTS))
-#define	QMD_LIST_CHECK_HEAD(head, field) do {				\
-	if (LIST_FIRST((head)) != NULL &&				\
-	    LIST_FIRST((head))->field.le_prev !=			\
-	     &LIST_FIRST((head)))					\
-		panic("Bad list head %p first->prev != head", (head));	\
-} while (0)
-
-#define	QMD_LIST_CHECK_NEXT(elm, field) do {				\
-	if (LIST_NEXT((elm), field) != NULL &&				\
-	    LIST_NEXT((elm), field)->field.le_prev !=			\
-	     &((elm)->field.le_next))					\
-	     	panic("Bad link elm %p next->prev != elm", (elm));	\
-} while (0)
-
-#define	QMD_LIST_CHECK_PREV(elm, field) do {				\
-	if (*(elm)->field.le_prev != (elm))				\
-		panic("Bad link elm %p prev->next != elm", (elm));	\
-} while (0)
-#else
-#define	QMD_LIST_CHECK_HEAD(head, field)
-#define	QMD_LIST_CHECK_NEXT(elm, field)
-#define	QMD_LIST_CHECK_PREV(elm, field)
-#endif /* (_KERNEL && INVARIANTS) */
-
-#define	LIST_EMPTY(head)	((head)->lh_first == NULL)
-
-#define	LIST_FIRST(head)	((head)->lh_first)
-
-#define	LIST_FOREACH(var, head, field)					\
-	for ((var) = LIST_FIRST((head));				\
-	    (var);							\
-	    (var) = LIST_NEXT((var), field))
-
-#define	LIST_FOREACH_SAFE(var, head, field, tvar)			\
-	for ((var) = LIST_FIRST((head));				\
-	    (var) && ((tvar) = LIST_NEXT((var), field), 1);		\
-	    (var) = (tvar))
-
-#define	LIST_INIT(head) do {						\
-	LIST_FIRST((head)) = NULL;					\
-} while (0)
-
-#define	LIST_INSERT_AFTER(listelm, elm, field) do {			\
-	QMD_LIST_CHECK_NEXT(listelm, field);				\
-	if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
-		LIST_NEXT((listelm), field)->field.le_prev =		\
-		    &LIST_NEXT((elm), field);				\
-	LIST_NEXT((listelm), field) = (elm);				\
-	(elm)->field.le_prev = &LIST_NEXT((listelm), field);		\
-} while (0)
-
-#define	LIST_INSERT_BEFORE(listelm, elm, field) do {			\
-	QMD_LIST_CHECK_PREV(listelm, field);				\
-	(elm)->field.le_prev = (listelm)->field.le_prev;		\
-	LIST_NEXT((elm), field) = (listelm);				\
-	*(listelm)->field.le_prev = (elm);				\
-	(listelm)->field.le_prev = &LIST_NEXT((elm), field);		\
-} while (0)
-
-#define	LIST_INSERT_HEAD(head, elm, field) do {				\
-	QMD_LIST_CHECK_HEAD((head), field);				\
-	if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL)	\
-		LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
-	LIST_FIRST((head)) = (elm);					\
-	(elm)->field.le_prev = &LIST_FIRST((head));			\
-} while (0)
-
-#define	LIST_NEXT(elm, field)	((elm)->field.le_next)
-
-#define	LIST_REMOVE(elm, field) do {					\
-	QMD_SAVELINK(oldnext, (elm)->field.le_next);			\
-	QMD_SAVELINK(oldprev, (elm)->field.le_prev);			\
-	QMD_LIST_CHECK_NEXT(elm, field);				\
-	QMD_LIST_CHECK_PREV(elm, field);				\
-	if (LIST_NEXT((elm), field) != NULL)				\
-		LIST_NEXT((elm), field)->field.le_prev = 		\
-		    (elm)->field.le_prev;				\
-	*(elm)->field.le_prev = LIST_NEXT((elm), field);		\
-	TRASHIT(*oldnext);						\
-	TRASHIT(*oldprev);						\
-} while (0)
-
-#define LIST_SWAP(head1, head2, type, field) do {			\
-	struct type *swap_tmp = LIST_FIRST((head1));			\
-	LIST_FIRST((head1)) = LIST_FIRST((head2));			\
-	LIST_FIRST((head2)) = swap_tmp;					\
-	if ((swap_tmp = LIST_FIRST((head1))) != NULL)			\
-		swap_tmp->field.le_prev = &LIST_FIRST((head1));		\
-	if ((swap_tmp = LIST_FIRST((head2))) != NULL)			\
-		swap_tmp->field.le_prev = &LIST_FIRST((head2));		\
-} while (0)
-
-/*
- * Tail queue declarations.
- */
-#define	TAILQ_HEAD(name, type)						\
-struct name {								\
-	struct type *tqh_first;	/* first element */			\
-	struct type **tqh_last;	/* addr of last next element */		\
-	TRACEBUF							\
-}
-
-#define	TAILQ_HEAD_INITIALIZER(head)					\
-	{ NULL, &(head).tqh_first }
-
-#define	TAILQ_ENTRY(type)						\
-struct {								\
-	struct type *tqe_next;	/* next element */			\
-	struct type **tqe_prev;	/* address of previous next element */	\
-	TRACEBUF							\
-}
-
-/*
- * Tail queue functions.
- */
-#if (defined(_KERNEL) && defined(INVARIANTS))
-#define	QMD_TAILQ_CHECK_HEAD(head, field) do {				\
-	if (!TAILQ_EMPTY(head) &&					\
-	    TAILQ_FIRST((head))->field.tqe_prev !=			\
-	     &TAILQ_FIRST((head)))					\
-		panic("Bad tailq head %p first->prev != head", (head));	\
-} while (0)
-
-#define	QMD_TAILQ_CHECK_TAIL(head, field) do {				\
-	if (*(head)->tqh_last != NULL)					\
-	    	panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); 	\
-} while (0)
-
-#define	QMD_TAILQ_CHECK_NEXT(elm, field) do {				\
-	if (TAILQ_NEXT((elm), field) != NULL &&				\
-	    TAILQ_NEXT((elm), field)->field.tqe_prev !=			\
-	     &((elm)->field.tqe_next))					\
-		panic("Bad link elm %p next->prev != elm", (elm));	\
-} while (0)
-
-#define	QMD_TAILQ_CHECK_PREV(elm, field) do {				\
-	if (*(elm)->field.tqe_prev != (elm))				\
-		panic("Bad link elm %p prev->next != elm", (elm));	\
-} while (0)
-#else
-#define	QMD_TAILQ_CHECK_HEAD(head, field)
-#define	QMD_TAILQ_CHECK_TAIL(head, headname)
-#define	QMD_TAILQ_CHECK_NEXT(elm, field)
-#define	QMD_TAILQ_CHECK_PREV(elm, field)
-#endif /* (_KERNEL && INVARIANTS) */
-
-#define	TAILQ_CONCAT(head1, head2, field) do {				\
-	if (!TAILQ_EMPTY(head2)) {					\
-		*(head1)->tqh_last = (head2)->tqh_first;		\
-		(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last;	\
-		(head1)->tqh_last = (head2)->tqh_last;			\
-		TAILQ_INIT((head2));					\
-		QMD_TRACE_HEAD(head1);					\
-		QMD_TRACE_HEAD(head2);					\
-	}								\
-} while (0)
-
-#define	TAILQ_EMPTY(head)	((head)->tqh_first == NULL)
-
-#define	TAILQ_FIRST(head)	((head)->tqh_first)
-
-#define	TAILQ_FOREACH(var, head, field)					\
-	for ((var) = TAILQ_FIRST((head));				\
-	    (var);							\
-	    (var) = TAILQ_NEXT((var), field))
-
-#define	TAILQ_FOREACH_SAFE(var, head, field, tvar)			\
-	for ((var) = TAILQ_FIRST((head));				\
-	    (var) && ((tvar) = TAILQ_NEXT((var), field), 1);		\
-	    (var) = (tvar))
-
-#define	TAILQ_FOREACH_REVERSE(var, head, headname, field)		\
-	for ((var) = TAILQ_LAST((head), headname);			\
-	    (var);							\
-	    (var) = TAILQ_PREV((var), headname, field))
-
-#define	TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar)	\
-	for ((var) = TAILQ_LAST((head), headname);			\
-	    (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1);	\
-	    (var) = (tvar))
-
-#define	TAILQ_INIT(head) do {						\
-	TAILQ_FIRST((head)) = NULL;					\
-	(head)->tqh_last = &TAILQ_FIRST((head));			\
-	QMD_TRACE_HEAD(head);						\
-} while (0)
-
-#define	TAILQ_INSERT_AFTER(head, listelm, elm, field) do {		\
-	QMD_TAILQ_CHECK_NEXT(listelm, field);				\
-	if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
-		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
-		    &TAILQ_NEXT((elm), field);				\
-	else {								\
-		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
-		QMD_TRACE_HEAD(head);					\
-	}								\
-	TAILQ_NEXT((listelm), field) = (elm);				\
-	(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field);		\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-	QMD_TRACE_ELEM(&listelm->field);				\
-} while (0)
-
-#define	TAILQ_INSERT_BEFORE(listelm, elm, field) do {			\
-	QMD_TAILQ_CHECK_PREV(listelm, field);				\
-	(elm)->field.tqe_prev = (listelm)->field.tqe_prev;		\
-	TAILQ_NEXT((elm), field) = (listelm);				\
-	*(listelm)->field.tqe_prev = (elm);				\
-	(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field);		\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-	QMD_TRACE_ELEM(&listelm->field);				\
-} while (0)
-
-#define	TAILQ_INSERT_HEAD(head, elm, field) do {			\
-	QMD_TAILQ_CHECK_HEAD(head, field);				\
-	if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL)	\
-		TAILQ_FIRST((head))->field.tqe_prev =			\
-		    &TAILQ_NEXT((elm), field);				\
-	else								\
-		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
-	TAILQ_FIRST((head)) = (elm);					\
-	(elm)->field.tqe_prev = &TAILQ_FIRST((head));			\
-	QMD_TRACE_HEAD(head);						\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-} while (0)
-
-#define	TAILQ_INSERT_TAIL(head, elm, field) do {			\
-	QMD_TAILQ_CHECK_TAIL(head, field);				\
-	TAILQ_NEXT((elm), field) = NULL;				\
-	(elm)->field.tqe_prev = (head)->tqh_last;			\
-	*(head)->tqh_last = (elm);					\
-	(head)->tqh_last = &TAILQ_NEXT((elm), field);			\
-	QMD_TRACE_HEAD(head);						\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-} while (0)
-
-#define	TAILQ_LAST(head, headname)					\
-	(*(((struct headname *)((head)->tqh_last))->tqh_last))
-
-#define	TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
-
-#define	TAILQ_PREV(elm, headname, field)				\
-	(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
-
-#define	TAILQ_REMOVE(head, elm, field) do {				\
-	QMD_SAVELINK(oldnext, (elm)->field.tqe_next);			\
-	QMD_SAVELINK(oldprev, (elm)->field.tqe_prev);			\
-	QMD_TAILQ_CHECK_NEXT(elm, field);				\
-	QMD_TAILQ_CHECK_PREV(elm, field);				\
-	if ((TAILQ_NEXT((elm), field)) != NULL)				\
-		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
-		    (elm)->field.tqe_prev;				\
-	else {								\
-		(head)->tqh_last = (elm)->field.tqe_prev;		\
-		QMD_TRACE_HEAD(head);					\
-	}								\
-	*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field);		\
-	TRASHIT(*oldnext);						\
-	TRASHIT(*oldprev);						\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-} while (0)
-
-#define TAILQ_SWAP(head1, head2, type, field) do {			\
-	struct type *swap_first = (head1)->tqh_first;			\
-	struct type **swap_last = (head1)->tqh_last;			\
-	(head1)->tqh_first = (head2)->tqh_first;			\
-	(head1)->tqh_last = (head2)->tqh_last;				\
-	(head2)->tqh_first = swap_first;				\
-	(head2)->tqh_last = swap_last;					\
-	if ((swap_first = (head1)->tqh_first) != NULL)			\
-		swap_first->field.tqe_prev = &(head1)->tqh_first;	\
-	else								\
-		(head1)->tqh_last = &(head1)->tqh_first;		\
-	if ((swap_first = (head2)->tqh_first) != NULL)			\
-		swap_first->field.tqe_prev = &(head2)->tqh_first;	\
-	else								\
-		(head2)->tqh_last = &(head2)->tqh_first;		\
-} while (0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !_SYS_QUEUE_H_ */
diff --git a/tools/sdk/include/esp32/rom/rtc.h b/tools/sdk/include/esp32/rom/rtc.h
deleted file mode 100644
index 6d9d297746a..00000000000
--- a/tools/sdk/include/esp32/rom/rtc.h
+++ /dev/null
@@ -1,220 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_RTC_H_
-#define _ROM_RTC_H_
-
-#include "ets_sys.h"
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup rtc_apis, rtc registers and memory related apis
-  * @brief rtc apis
-  */
-
-/** @addtogroup rtc_apis
-  * @{
-  */
-
-/**************************************************************************************
-  *                                       Note:                                       *
-  *       Some Rtc memory and registers are used, in ROM or in internal library.      *
-  *          Please do not use reserved or used rtc memory or registers.              *
-  *                                                                                   *
-  *************************************************************************************
-  *                          RTC  Memory & Store Register usage
-  *************************************************************************************
-  *     rtc memory addr         type    size            usage
-  *     0x3ff61000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
-  *     0x3ff61000+SIZE_CP      Slow    4096-SIZE_CP
-  *     0x3ff62800              Slow    4096            Reserved
-  *
-  *     0x3ff80000(0x400c0000)  Fast    8192            deep sleep entry code
-  *
-  *************************************************************************************
-  *     RTC store registers     usage
-  *     RTC_CNTL_STORE0_REG     Reserved
-  *     RTC_CNTL_STORE1_REG     RTC_SLOW_CLK calibration value
-  *     RTC_CNTL_STORE2_REG     Boot time, low word
-  *     RTC_CNTL_STORE3_REG     Boot time, high word
-  *     RTC_CNTL_STORE4_REG     External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
-  *     RTC_CNTL_STORE5_REG     APB bus frequency
-  *     RTC_CNTL_STORE6_REG     FAST_RTC_MEMORY_ENTRY
-  *     RTC_CNTL_STORE7_REG     FAST_RTC_MEMORY_CRC
-  *************************************************************************************
-  */
-
-#define RTC_SLOW_CLK_CAL_REG    RTC_CNTL_STORE1_REG
-#define RTC_BOOT_TIME_LOW_REG   RTC_CNTL_STORE2_REG
-#define RTC_BOOT_TIME_HIGH_REG  RTC_CNTL_STORE3_REG
-#define RTC_XTAL_FREQ_REG       RTC_CNTL_STORE4_REG
-#define RTC_APB_FREQ_REG        RTC_CNTL_STORE5_REG
-#define RTC_ENTRY_ADDR_REG      RTC_CNTL_STORE6_REG
-#define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
-#define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
-
-#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
-
-typedef enum {
-    AWAKE = 0,             //<CPU ON
-    LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
-    DEEP_SLEEP  = BIT1     //CPU OFF, PLL OFF, only specific timer could wake up
-} SLEEP_MODE;
-
-typedef enum {
-    NO_MEAN                =  0,
-    POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
-    SW_RESET               =  3,    /**<3, Software reset digital core*/
-    OWDT_RESET             =  4,    /**<4, Legacy watch dog reset digital core*/
-    DEEPSLEEP_RESET        =  5,    /**<3, Deep Sleep reset digital core*/
-    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core*/
-    TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core*/
-    TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core*/
-    RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core*/
-    INTRUSION_RESET        = 10,    /**<10, Instrusion tested to reset CPU*/
-    TGWDT_CPU_RESET        = 11,    /**<11, Time Group reset CPU*/
-    SW_CPU_RESET           = 12,    /**<12, Software reset CPU*/
-    RTCWDT_CPU_RESET       = 13,    /**<13, RTC Watch dog Reset CPU*/
-    EXT_CPU_RESET          = 14,    /**<14, for APP CPU, reseted by PRO CPU*/
-    RTCWDT_BROWN_OUT_RESET = 15,    /**<15, Reset when the vdd voltage is not stable*/
-    RTCWDT_RTC_RESET       = 16     /**<16, RTC Watch dog reset digital core and rtc module*/
-} RESET_REASON;
-
-typedef enum {
-    NO_SLEEP        = 0,
-    EXT_EVENT0_TRIG = BIT0,
-    EXT_EVENT1_TRIG = BIT1,
-    GPIO_TRIG       = BIT2,
-    TIMER_EXPIRE    = BIT3,
-    SDIO_TRIG       = BIT4,
-    MAC_TRIG        = BIT5,
-    UART0_TRIG      = BIT6,
-    UART1_TRIG      = BIT7,
-    TOUCH_TRIG      = BIT8,
-    SAR_TRIG        = BIT9,
-    BT_TRIG         = BIT10
-} WAKEUP_REASON;
-
-typedef enum {
-    DISEN_WAKEUP       = NO_SLEEP,
-    EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
-    EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
-    GPIO_TRIG_EN       = GPIO_TRIG,
-    TIMER_EXPIRE_EN    = TIMER_EXPIRE,
-    SDIO_TRIG_EN       = SDIO_TRIG,
-    MAC_TRIG_EN        = MAC_TRIG,
-    UART0_TRIG_EN      = UART0_TRIG,
-    UART1_TRIG_EN      = UART1_TRIG,
-    TOUCH_TRIG_EN      = TOUCH_TRIG,
-    SAR_TRIG_EN        = SAR_TRIG,
-    BT_TRIG_EN         = BT_TRIG
-} WAKEUP_ENABLE;
-
-typedef enum {
-    NO_INT             = 0,
-    WAKEUP_INT         = BIT0,
-    REJECT_INT         = BIT1,
-    SDIO_IDLE_INT      = BIT2,
-    RTC_WDT_INT        = BIT3,
-    RTC_TIME_VALID_INT = BIT4
-} RTC_INT_REASON;
-
-typedef enum {
-    DISEN_INT             = 0,
-    WAKEUP_INT_EN         = WAKEUP_INT,
-    REJECT_INT_EN         = REJECT_INT,
-    SDIO_IDLE_INT_EN      = SDIO_IDLE_INT,
-    RTC_WDT_INT_EN        = RTC_WDT_INT,
-    RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
-} RTC_INT_EN;
-
-/**
-  * @brief  Get the reset reason for CPU.
-  *
-  * @param  int cpu_no : CPU no.
-  *
-  * @return RESET_REASON
-  */
-RESET_REASON rtc_get_reset_reason(int cpu_no);
-
-/**
-  * @brief  Get the wakeup cause for CPU.
-  *
-  * @param  int cpu_no : CPU no.
-  *
-  * @return WAKEUP_REASON
-  */
-WAKEUP_REASON rtc_get_wakeup_cause(void);
-
-/**
-  * @brief Get CRC for Fast RTC Memory.
-  *
-  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
-  *
-  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
-  *
-  * @return uint32_t : CRC32 result
-  */
-uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
-
-/**
-  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void set_rtc_memory_crc(void);
-
-/**
-  * @brief Software Reset digital core.
-  *
-  * It is not recommended to use this function in esp-idf, use
-  * esp_restart() instead.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void __attribute__((noreturn)) software_reset(void);
-
-/**
-  * @brief Software Reset digital core.
-  *
-  * It is not recommended to use this function in esp-idf, use
-  * esp_restart() instead.
-  *
-  * @param  int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
-  *
-  * @return None
-  */
-void software_reset_cpu(int cpu_no);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_RTC_H_ */
-
diff --git a/tools/sdk/include/esp32/rom/secure_boot.h b/tools/sdk/include/esp32/rom/secure_boot.h
deleted file mode 100644
index bd4f32ed95e..00000000000
--- a/tools/sdk/include/esp32/rom/secure_boot.h
+++ /dev/null
@@ -1,46 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_SECURE_BOOT_H_
-#define _ROM_SECURE_BOOT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void ets_secure_boot_start(void);
-
-void ets_secure_boot_finish(void);
-
-void ets_secure_boot_hash(const uint32_t *buf);
-
-void ets_secure_boot_obtain(void);
-
-int ets_secure_boot_check(uint32_t *buf);
-
-void ets_secure_boot_rd_iv(uint32_t *buf);
-
-void ets_secure_boot_rd_abstract(uint32_t *buf);
-
-bool ets_secure_boot_check_start(uint8_t abs_index, uint32_t iv_addr);
-
-int ets_secure_boot_check_finish(uint32_t *abstract);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_SECURE_BOOT_H_ */
diff --git a/tools/sdk/include/esp32/rom/sha.h b/tools/sdk/include/esp32/rom/sha.h
deleted file mode 100644
index 5dd9c9981fb..00000000000
--- a/tools/sdk/include/esp32/rom/sha.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
-  ROM functions for hardware SHA support.
-
-  It is not recommended to use these functions directly.  If using
-  them from esp-idf then use the esp_sha_lock_engine() and
-  esp_sha_lock_memory_block() functions in hwcrypto/sha.h to ensure
-  exclusive access.
- */
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ROM_SHA_H_
-#define _ROM_SHA_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct SHAContext {
-    bool start;
-    uint32_t total_input_bits[4];
-} SHA_CTX;
-
-enum SHA_TYPE {
-    SHA1 = 0,
-    SHA2_256,
-    SHA2_384,
-    SHA2_512,
-
-
-    SHA_INVALID = -1,
-};
-
-void ets_sha_init(SHA_CTX *ctx);
-
-void ets_sha_enable(void);
-
-void ets_sha_disable(void);
-
-void ets_sha_update(SHA_CTX *ctx, enum SHA_TYPE type, const uint8_t *input, size_t input_bits);
-
-void ets_sha_finish(SHA_CTX *ctx, enum SHA_TYPE type, uint8_t *output);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_SHA_H_ */
diff --git a/tools/sdk/include/esp32/rom/spi_flash.h b/tools/sdk/include/esp32/rom/spi_flash.h
deleted file mode 100644
index a6ed793d6c6..00000000000
--- a/tools/sdk/include/esp32/rom/spi_flash.h
+++ /dev/null
@@ -1,554 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_SPI_FLASH_H_
-#define _ROM_SPI_FLASH_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "esp_attr.h"
-
-#include "soc/spi_reg.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup spi_flash_apis, spi flash operation related apis
-  * @brief spi_flash apis
-  */
-
-/** @addtogroup spi_flash_apis
-  * @{
-  */
-
-/*************************************************************
- *                            Note
- *************************************************************
- * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
- *    used as an SPI master to access Flash and ext-SRAM by
- *    Cache module. It will support Decryto read for Flash,
- *    read/write for ext-SRAM. And SPI1 is also used as an
- *    SPI master for Flash read/write and ext-SRAM read/write.
- *    It will support Encrypto write for Flash.
- * 2. As an SPI master, SPI support Highest clock to 80M,
- *    however, Flash with 80M Clock should be configured
- *    for different Flash chips. If you want to use 80M
- *    clock We should use the SPI that is certified by
- *    Espressif. However, the certification is not started
- *    at the time, so please use 40M clock at the moment.
- * 3. SPI Flash can use 2 lines or 4 lines mode. If you
- *    use 2 lines mode, you can save two pad SPIHD and
- *    SPIWP for gpio. ESP32 support configured SPI pad for
- *    Flash, the configuration is stored in efuse and flash.
- *    However, the configurations of pads should be certified
- *    by Espressif. If you use this function, please use 40M
- *    clock at the moment.
- * 4. ESP32 support to use Common SPI command to configure
- *    Flash to QIO mode, if you failed to configure with fix
- *    command. With Common SPI Command, ESP32 can also provide
- *    a way to use same Common SPI command groups on different
- *    Flash chips.
- * 5. This functions are not protected by packeting, Please use the
- *************************************************************
- */
-
-#define PERIPHS_SPI_FLASH_CMD                 SPI_CMD_REG(1)
-#define PERIPHS_SPI_FLASH_ADDR                SPI_ADDR_REG(1)
-#define PERIPHS_SPI_FLASH_CTRL                SPI_CTRL_REG(1)
-#define PERIPHS_SPI_FLASH_CTRL1               SPI_CTRL1_REG(1)
-#define PERIPHS_SPI_FLASH_STATUS              SPI_RD_STATUS_REG(1)
-#define PERIPHS_SPI_FLASH_USRREG              SPI_USER_REG(1)
-#define PERIPHS_SPI_FLASH_USRREG1             SPI_USER1_REG(1)
-#define PERIPHS_SPI_FLASH_USRREG2             SPI_USER2_REG(1)
-#define PERIPHS_SPI_FLASH_C0                  SPI_W0_REG(1)
-#define PERIPHS_SPI_FLASH_C1                  SPI_W1_REG(1)
-#define PERIPHS_SPI_FLASH_C2                  SPI_W2_REG(1)
-#define PERIPHS_SPI_FLASH_C3                  SPI_W3_REG(1)
-#define PERIPHS_SPI_FLASH_C4                  SPI_W4_REG(1)
-#define PERIPHS_SPI_FLASH_C5                  SPI_W5_REG(1)
-#define PERIPHS_SPI_FLASH_C6                  SPI_W6_REG(1)
-#define PERIPHS_SPI_FLASH_C7                  SPI_W7_REG(1)
-#define PERIPHS_SPI_FLASH_TX_CRC              SPI_TX_CRC_REG(1)
-
-#define SPI0_R_QIO_DUMMY_CYCLELEN             3
-#define SPI0_R_QIO_ADDR_BITSLEN               31
-#define SPI0_R_FAST_DUMMY_CYCLELEN            7
-#define SPI0_R_DIO_DUMMY_CYCLELEN             1
-#define SPI0_R_DIO_ADDR_BITSLEN               27
-#define SPI0_R_FAST_ADDR_BITSLEN              23
-#define SPI0_R_SIO_ADDR_BITSLEN               23
-
-#define SPI1_R_QIO_DUMMY_CYCLELEN             3
-#define SPI1_R_QIO_ADDR_BITSLEN               31
-#define SPI1_R_FAST_DUMMY_CYCLELEN            7
-#define SPI1_R_DIO_DUMMY_CYCLELEN             3
-#define SPI1_R_DIO_ADDR_BITSLEN               31
-#define SPI1_R_FAST_ADDR_BITSLEN              23
-#define SPI1_R_SIO_ADDR_BITSLEN               23
-
-#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN   23
-
-#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN   SPI_WRSR_2B
-
-//SPI address register
-#define ESP_ROM_SPIFLASH_BYTES_LEN            24
-#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM  32
-#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM   64
-#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS  0x3f
-
-//SPI status register
-#define  ESP_ROM_SPIFLASH_BUSY_FLAG           BIT0
-#define  ESP_ROM_SPIFLASH_WRENABLE_FLAG       BIT1
-#define  ESP_ROM_SPIFLASH_BP0                 BIT2
-#define  ESP_ROM_SPIFLASH_BP1                 BIT3
-#define  ESP_ROM_SPIFLASH_BP2                 BIT4
-#define  ESP_ROM_SPIFLASH_WR_PROTECT          (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
-#define  ESP_ROM_SPIFLASH_QE                  BIT9
-
-//Extra dummy for flash read
-#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M   0
-#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M   1
-#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M   2
-
-#define FLASH_ID_GD25LQ32C  0xC86016
-
-typedef enum {
-    ESP_ROM_SPIFLASH_QIO_MODE = 0,
-    ESP_ROM_SPIFLASH_QOUT_MODE,
-    ESP_ROM_SPIFLASH_DIO_MODE,
-    ESP_ROM_SPIFLASH_DOUT_MODE,
-    ESP_ROM_SPIFLASH_FASTRD_MODE,
-    ESP_ROM_SPIFLASH_SLOWRD_MODE
-} esp_rom_spiflash_read_mode_t;
-
-typedef enum {
-    ESP_ROM_SPIFLASH_RESULT_OK,
-    ESP_ROM_SPIFLASH_RESULT_ERR,
-    ESP_ROM_SPIFLASH_RESULT_TIMEOUT
-} esp_rom_spiflash_result_t;
-
-typedef struct {
-    uint32_t device_id;
-    uint32_t chip_size;    // chip size in bytes
-    uint32_t block_size;
-    uint32_t sector_size;
-    uint32_t page_size;
-    uint32_t status_mask;
-} esp_rom_spiflash_chip_t;
-
-typedef struct {
-    uint8_t  data_length;
-    uint8_t  read_cmd0;
-    uint8_t  read_cmd1;
-    uint8_t  write_cmd;
-    uint16_t data_mask;
-    uint16_t data;
-} esp_rom_spiflash_common_cmd_t;
-
-/**
-  * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
-  *    Please do not call this function in SDK.
-  *
-  * @param  uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
-  *
-  * @param  uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
-  *
-  * @return None
-  */
-void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
-
-/**
-  * @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
-  *    Please do not call this function in SDK.
-  *
-  * @param  uint8_t wp_gpio_num: WP gpio number.
-  *
-  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
-  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
-  *
-  * @return None
-  */
-void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
-
-/**
-  * @brief Set SPI Flash pad drivers.
-  *    Please do not call this function in SDK.
-  *
-  * @param  uint8_t wp_gpio_num: WP gpio number.
-  *
-  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
-  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
-  *
-  * @param  uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
-  *            drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
-  *                        Values usually read from falsh by rom code, function usually callde by rom code.
-  *                        if value with bit(3) set, the value is valid, bit[2:0] is the real value.
-  *
-  * @return None
-  */
-void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
-
-/**
-  * @brief Select SPI Flash function for pads.
-  *    Please do not call this function in SDK.
-  *
-  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
-  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
-  *
-  * @return None
-  */
-void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
-
-/**
-  * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
-  *    Please do not call this function in SDK.
-  *
-  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
-  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
-  *
-  * @param  uint8_t legacy: In legacy mode, more SPI command is used in line.
-  *
-  * @return None
-  */
-void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
-
-/**
-  * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
-  *    Please do not call this function in SDK.
-  *
-  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
-  *
-  * @param  uint32_t *status : The pointer to which to return the Flash status value.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
-
-/**
-  * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
-  *        Please do not call this function in SDK.
-  *
-  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
-  *
-  * @param  uint32_t *status : The pointer to which to return the Flash status value.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
-
-/**
-  * @brief Write status to Falsh status register.
-  *        Please do not call this function in SDK.
-  *
-  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
-  *
-  * @param  uint32_t status_value : Value to .
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : write error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
-
-/**
-  * @brief Use a command to Read Flash status register.
-  *        Please do not call this function in SDK.
-  *
-  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
-  *
-  * @param  uint32_t*status : The pointer to which to return the Flash status value.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
-
-/**
-  * @brief Config SPI Flash read mode when init.
-  *        Please do not call this function in SDK.
-  *
-  * @param  esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
-  *
-  * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
-
-/**
-  * @brief Config SPI Flash clock divisor.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t freqdiv: clock divisor.
-  *
-  * @param  uint8_t spi: 0 for SPI0, 1 for SPI1.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
-
-/**
-  * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
-  *        Please do not call this function in SDK.
-  *
-  * @param  esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
-  *
-  * @return uint16_t  0 : do not send command any more.
-  *                   1 : go to the next command.
-  *                   n > 1 : skip (n - 1) commands.
-  */
-uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
-
-/**
-  * @brief Unlock SPI write protect.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
-
-/**
-  * @brief SPI write protect.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
-
-/**
-  * @brief Update SPI Flash parameter.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint32_t deviceId : Device ID read from SPI, the low 32 bit.
-  *
-  * @param  uint32_t chip_size : The Flash size.
-  *
-  * @param  uint32_t block_size : The Flash block size.
-  *
-  * @param  uint32_t sector_size : The Flash sector size.
-  *
-  * @param  uint32_t page_size : The Flash page size.
-  *
-  * @param  uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, 
-                                                        uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
-
-/**
-  * @brief Erase whole flash chip.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
-
-/**
-  * @brief Erase a 64KB block of flash
-  *        Uses SPI flash command D8H.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint32_t block_num : Which block to erase.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
-
-/**
-  * @brief Erase a sector of flash.
-  *        Uses SPI flash command 20H.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint32_t sector_num : Which sector to erase.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
-
-/**
-  * @brief Erase some sectors.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint32_t start_addr : Start addr to erase, should be sector aligned.
-  *
-  * @param  uint32_t area_len : Length to erase, should be sector aligned.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
-
-/**
-  * @brief Write Data to Flash, you should Erase it yourself if need.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint32_t dest_addr : Address to write, should be 4 bytes aligned.
-  *
-  * @param  const uint32_t *src : The pointer to data which is to write.
-  *
-  * @param  uint32_t len : Length to write, should be 4 bytes aligned.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
-
-/**
-  * @brief Read Data from Flash, you should Erase it yourself if need.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint32_t src_addr : Address to read, should be 4 bytes aligned.
-  *
-  * @param  uint32_t *dest : The buf to read the data.
-  *
-  * @param  uint32_t len : Length to read, should be 4 bytes aligned.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
-
-/**
-  * @brief SPI1 go into encrypto mode.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void esp_rom_spiflash_write_encrypted_enable(void);
-
-/**
-  * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint32_t flash_addr : Address to write, should be 32 bytes aligned.
-  *
-  * @param  uint32_t *data : The pointer to data which is to write.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data);
-
-/**
-  * @brief SPI1 go out of encrypto mode.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void esp_rom_spiflash_write_encrypted_disable(void);
-
-/**
-  * @brief Write data to flash with transparent encryption.
-  * @note Sectors to be written should already be erased.
-  *
-  * @note Please do not call this function in SDK.
-  *
-  * @param  uint32_t flash_addr : Address to write, should be 32 byte aligned.
-  *
-  * @param  uint32_t *data : The pointer to data to write. Note, this pointer must
-  *                          be 32 bit aligned and the content of the data will be
-  *                          modified by the encryption function.
-  *
-  * @param  uint32_t len : Length to write, should be 32 bytes aligned.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
-
-
-/** @brief Wait until SPI flash write operation is complete
- *
- * @note Please do not call this function in SDK.
- *
- * Reads the Write In Progress bit of the SPI flash status register,
- * repeats until this bit is zero (indicating write complete).
- *
- * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
- *         ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
- */
-esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
-
-
-/** @brief Enable Quad I/O pin functions
- *
- * @note Please do not call this function in SDK.
- *
- * Sets the HD & WP pin functions for Quad I/O modes, based on the
- * efuse SPI pin configuration.
- *
- * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
- *
- * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
- * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
- * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
- * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
- *   to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
- *   Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
- */
-void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
-
-/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions
- *
- */
-extern esp_rom_spiflash_chip_t g_rom_flashchip;
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_SPI_FLASH_H_ */
diff --git a/tools/sdk/include/esp32/rom/tbconsole.h b/tools/sdk/include/esp32/rom/tbconsole.h
deleted file mode 100644
index 891c2732a53..00000000000
--- a/tools/sdk/include/esp32/rom/tbconsole.h
+++ /dev/null
@@ -1,27 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ROM_TBCONSOLE_H_
-#define _ROM_TBCONSOLE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void start_tb_console();
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_TBCONSOLE_H_ */
diff --git a/tools/sdk/include/esp32/rom/tjpgd.h b/tools/sdk/include/esp32/rom/tjpgd.h
deleted file mode 100644
index 31fbc97cce9..00000000000
--- a/tools/sdk/include/esp32/rom/tjpgd.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*----------------------------------------------------------------------------/
-/ TJpgDec - Tiny JPEG Decompressor include file               (C)ChaN, 2012
-/----------------------------------------------------------------------------*/
-#ifndef _TJPGDEC
-#define _TJPGDEC
-/*---------------------------------------------------------------------------*/
-/* System Configurations */
-
-#define	JD_SZBUF		512	/* Size of stream input buffer */
-#define JD_FORMAT		0	/* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
-#define	JD_USE_SCALE	1	/* Use descaling feature for output */
-#define JD_TBLCLIP		1	/* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
-
-/*---------------------------------------------------------------------------*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* These types must be 16-bit, 32-bit or larger integer */
-typedef int				INT;
-typedef unsigned int	UINT;
-
-/* These types must be 8-bit integer */
-typedef char			CHAR;
-typedef unsigned char	UCHAR;
-typedef unsigned char	BYTE;
-
-/* These types must be 16-bit integer */
-typedef short			SHORT;
-typedef unsigned short	USHORT;
-typedef unsigned short	WORD;
-typedef unsigned short	WCHAR;
-
-/* These types must be 32-bit integer */
-typedef long			LONG;
-typedef unsigned long	ULONG;
-typedef unsigned long	DWORD;
-
-
-/* Error code */
-typedef enum {
-	JDR_OK = 0,	/* 0: Succeeded */
-	JDR_INTR,	/* 1: Interrupted by output function */	
-	JDR_INP,	/* 2: Device error or wrong termination of input stream */
-	JDR_MEM1,	/* 3: Insufficient memory pool for the image */
-	JDR_MEM2,	/* 4: Insufficient stream input buffer */
-	JDR_PAR,	/* 5: Parameter error */
-	JDR_FMT1,	/* 6: Data format error (may be damaged data) */
-	JDR_FMT2,	/* 7: Right format but not supported */
-	JDR_FMT3	/* 8: Not supported JPEG standard */
-} JRESULT;
-
-
-
-/* Rectangular structure */
-typedef struct {
-	WORD left, right, top, bottom;
-} JRECT;
-
-
-
-/* Decompressor object structure */
-typedef struct JDEC JDEC;
-struct JDEC {
-	UINT dctr;				/* Number of bytes available in the input buffer */
-	BYTE* dptr;				/* Current data read ptr */
-	BYTE* inbuf;			/* Bit stream input buffer */
-	BYTE dmsk;				/* Current bit in the current read byte */
-	BYTE scale;				/* Output scaling ratio */
-	BYTE msx, msy;			/* MCU size in unit of block (width, height) */
-	BYTE qtid[3];			/* Quantization table ID of each component */
-	SHORT dcv[3];			/* Previous DC element of each component */
-	WORD nrst;				/* Restart inverval */
-	UINT width, height;		/* Size of the input image (pixel) */
-	BYTE* huffbits[2][2];	/* Huffman bit distribution tables [id][dcac] */
-	WORD* huffcode[2][2];	/* Huffman code word tables [id][dcac] */
-	BYTE* huffdata[2][2];	/* Huffman decoded data tables [id][dcac] */
-	LONG* qttbl[4];			/* Dequaitizer tables [id] */
-	void* workbuf;			/* Working buffer for IDCT and RGB output */
-	BYTE* mcubuf;			/* Working buffer for the MCU */
-	void* pool;				/* Pointer to available memory pool */
-	UINT sz_pool;			/* Size of momory pool (bytes available) */
-	UINT (*infunc)(JDEC*, BYTE*, UINT);/* Pointer to jpeg stream input function */
-	void* device;			/* Pointer to I/O device identifiler for the session */
-};
-
-
-
-/* TJpgDec API functions */
-JRESULT jd_prepare (JDEC*, UINT(*)(JDEC*,BYTE*,UINT), void*, UINT, void*);
-JRESULT jd_decomp (JDEC*, UINT(*)(JDEC*,void*,JRECT*), BYTE);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _TJPGDEC */
diff --git a/tools/sdk/include/esp32/rom/uart.h b/tools/sdk/include/esp32/rom/uart.h
deleted file mode 100644
index a010bfbca47..00000000000
--- a/tools/sdk/include/esp32/rom/uart.h
+++ /dev/null
@@ -1,420 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ROM_UART_H_
-#define _ROM_UART_H_
-
-#include "esp_types.h"
-#include "esp_attr.h"
-#include "ets_sys.h"
-#include "soc/soc.h"
-#include "soc/uart_reg.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \defgroup uart_apis, uart configuration and communication related apis
-  * @brief uart apis
-  */
-
-/** @addtogroup uart_apis
-  * @{
-  */
-
-#define RX_BUFF_SIZE                     0x100
-#define TX_BUFF_SIZE                     100
-
-//uart int enable register ctrl bits
-#define UART_RCV_INTEN                   BIT0
-#define UART_TRX_INTEN                   BIT1
-#define UART_LINE_STATUS_INTEN           BIT2
-
-//uart int identification ctrl bits
-#define UART_INT_FLAG_MASK               0x0E
-
-//uart fifo ctrl bits
-#define UART_CLR_RCV_FIFO                BIT1
-#define UART_CLR_TRX_FIFO                BIT2
-#define UART_RCVFIFO_TRG_LVL_BITS        BIT6
-
-//uart line control bits
-#define  UART_DIV_LATCH_ACCESS_BIT       BIT7
-
-//uart line status bits
-#define  UART_RCV_DATA_RDY_FLAG          BIT0
-#define  UART_RCV_OVER_FLOW_FLAG         BIT1
-#define  UART_RCV_PARITY_ERR_FLAG        BIT2
-#define  UART_RCV_FRAME_ERR_FLAG         BIT3
-#define  UART_BRK_INT_FLAG               BIT4
-#define  UART_TRX_FIFO_EMPTY_FLAG        BIT5
-#define  UART_TRX_ALL_EMPTY_FLAG         BIT6   // include fifo and shift reg
-#define  UART_RCV_ERR_FLAG               BIT7
-
-//send and receive message frame head
-#define FRAME_FLAG                       0x7E
-
-typedef enum {
-    UART_LINE_STATUS_INT_FLAG  = 0x06,
-    UART_RCV_FIFO_INT_FLAG     = 0x04,
-    UART_RCV_TMOUT_INT_FLAG    = 0x0C,
-    UART_TXBUFF_EMPTY_INT_FLAG = 0x02
-} UartIntType;   //consider bit0 for int_flag
-
-typedef enum {
-    RCV_ONE_BYTE      = 0x0,
-    RCV_FOUR_BYTE     = 0x1,
-    RCV_EIGHT_BYTE    = 0x2,
-    RCV_FOURTEEN_BYTE = 0x3
-} UartRcvFifoTrgLvl;
-
-typedef enum {
-    FIVE_BITS  = 0x0,
-    SIX_BITS   = 0x1,
-    SEVEN_BITS = 0x2,
-    EIGHT_BITS = 0x3
-} UartBitsNum4Char;
-
-typedef enum {
-    ONE_STOP_BIT      = 1,
-    ONE_HALF_STOP_BIT = 2,
-    TWO_STOP_BIT      = 3
-} UartStopBitsNum;
-
-typedef enum {
-    NONE_BITS = 0,
-    ODD_BITS  = 2,
-    EVEN_BITS = 3
-
-} UartParityMode;
-
-typedef enum {
-    STICK_PARITY_DIS = 0,
-    STICK_PARITY_EN  = 2
-} UartExistParity;
-
-typedef enum {
-    BIT_RATE_9600   = 9600,
-    BIT_RATE_19200  = 19200,
-    BIT_RATE_38400  = 38400,
-    BIT_RATE_57600  = 57600,
-    BIT_RATE_115200 = 115200,
-    BIT_RATE_230400 = 230400,
-    BIT_RATE_460800 = 460800,
-    BIT_RATE_921600 = 921600
-} UartBautRate;
-
-typedef enum {
-    NONE_CTRL,
-    HARDWARE_CTRL,
-    XON_XOFF_CTRL
-} UartFlowCtrl;
-
-typedef enum {
-    EMPTY,
-    UNDER_WRITE,
-    WRITE_OVER
-} RcvMsgBuffState;
-
-typedef struct {
-    uint8_t *pRcvMsgBuff;
-    uint8_t *pWritePos;
-    uint8_t *pReadPos;
-    uint8_t  TrigLvl;
-    RcvMsgBuffState BuffState;
-} RcvMsgBuff;
-
-typedef struct {
-    uint32_t  TrxBuffSize;
-    uint8_t  *pTrxBuff;
-} TrxMsgBuff;
-
-typedef enum {
-    BAUD_RATE_DET,
-    WAIT_SYNC_FRM,
-    SRCH_MSG_HEAD,
-    RCV_MSG_BODY,
-    RCV_ESC_CHAR,
-} RcvMsgState;
-
-typedef struct {
-    UartBautRate     baut_rate;
-    UartBitsNum4Char data_bits;
-    UartExistParity  exist_parity;
-    UartParityMode   parity;    // chip size in byte
-    UartStopBitsNum  stop_bits;
-    UartFlowCtrl     flow_ctrl;
-    uint8_t          buff_uart_no;  //indicate which uart use tx/rx buffer
-    uint8_t          tx_uart_no;
-    RcvMsgBuff       rcv_buff;
-//    TrxMsgBuff       trx_buff;
-    RcvMsgState      rcv_state;
-    int              received;
-} UartDevice;
-
-/**
-  * @brief Init uart device struct value and reset uart0/uart1 rx.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void uartAttach(void);
-
-/**
-  * @brief Init uart0 or uart1 for UART download booting mode.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t uart_no : 0 for UART0, else for UART1.
-  *
-  * @param  uint32_t clock : clock used by uart module, to adjust baudrate.
-  *
-  * @return None
-  */
-void Uart_Init(uint8_t uart_no, uint32_t clock);
-
-/**
-  * @brief Modify uart baudrate.
-  *        This function will reset RX/TX fifo for uart.
-  *
-  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
-  *
-  * @param  uint32_t DivLatchValue : (clock << 4)/baudrate.
-  *
-  * @return None
-  */
-void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
-
-/**
-  * @brief Init uart0 or uart1 for UART download booting mode.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
-  *
-  * @param  uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected;
-  *                           1, two UART modules, hard to detect, detect and return.
-  *
-  * @return None
-  */
-int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync);
-
-/**
-  * @brief Switch printf channel of uart_tx_one_char.
-  *        Please do not call this function when printf.
-  *
-  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
-  *
-  * @return None
-  */
-void uart_tx_switch(uint8_t uart_no);
-
-/**
-  * @brief Switch message exchange channel for UART download booting.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
-  *
-  * @return None
-  */
-void uart_buff_switch(uint8_t uart_no);
-
-/**
-  * @brief Output a char to printf channel, wait until fifo not full.
-  *
-  * @param  None
-  *
-  * @return OK.
-  */
-STATUS uart_tx_one_char(uint8_t TxChar);
-
-/**
-  * @brief Output a char to message exchange channel, wait until fifo not full.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None
-  *
-  * @return OK.
-  */
-STATUS uart_tx_one_char2(uint8_t TxChar);
-
-/**
-  * @brief Wait until uart tx full empty.
-  *
-  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
-  *
-  * @return None.
-  */
-void uart_tx_flush(uint8_t uart_no);
-
-/**
-  * @brief Wait until uart tx full empty and the last char send ok.
-  *
-  * @param  uart_no : 0 for UART0, 1 for UART1, 2 for UART2
-  *
-  * The function defined in ROM code has a bug, so we define the correct version
-  * here for compatibility.
-  */
-static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) {
-    uint32_t status;
-    do {
-        status = READ_PERI_REG(UART_STATUS_REG(uart_no));
-        /* either tx count or state is non-zero */
-    } while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0);
-}
-
-/**
-  * @brief Get an input char from message channel.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t *pRxChar : the pointer to store the char.
-  *
-  * @return OK for successful.
-  *         FAIL for failed.
-  */
-STATUS uart_rx_one_char(uint8_t *pRxChar);
-
-/**
-  * @brief Get an input char from message channel, wait until successful.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None
-  *
-  * @return char : input char value.
-  */
-char uart_rx_one_char_block(void);
-
-/**
-  * @brief Get an input string line from message channel.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t *pString : the pointer to store the string.
-  *
-  * @param  uint8_t MaxStrlen : the max string length, include '\0'.
-  *
-  * @return OK.
-  */
-STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
-
-/**
-  * @brief Process uart received information in the interrupt handler.
-  *        Please do not call this function in SDK.
-  *
-  * @param  void *para : the message receive buffer.
-  *
-  * @return None
-  */
-void uart_rx_intr_handler(void *para);
-
-/**
-  * @brief Get an char from receive buffer.
-  *        Please do not call this function in SDK.
-  *
-  * @param  RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
-  *
-  * @param  uint8_t *pRxByte : the pointer to store the char.
-  *
-  * @return OK for successful.
-  *         FAIL for failed.
-  */
-STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
-
-/**
-  * @brief Get all chars from receive buffer.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t *pCmdLn : the pointer to store the string.
-  *
-  * @return OK for successful.
-  *         FAIL for failed.
-  */
-STATUS UartGetCmdLn(uint8_t *pCmdLn);
-
-/**
-  * @brief Get uart configuration struct.
-  *        Please do not call this function in SDK.
-  *
-  * @param  None
-  *
-  * @return UartDevice * : uart configuration struct pointer.
-  */
-UartDevice *GetUartDevice(void);
-
-/**
-  * @brief Send an packet to download tool, with SLIP escaping.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t *p : the pointer to output string.
-  *
-  * @param  int len : the string length.
-  *
-  * @return None.
-  */
-void send_packet(uint8_t *p, int len);
-
-/**
-  * @brief Receive an packet from download tool, with SLIP escaping.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t *p : the pointer to input string.
-  *
-  * @param  int len : If string length > len, the string will be truncated.
-  *
-  * @param  uint8_t is_sync : 0, only one UART module;
-  *                           1, two UART modules.
-  *
-  * @return int : the length of the string.
-  */
-int recv_packet(uint8_t *p, int len, uint8_t is_sync);
-
-/**
-  * @brief Send an packet to download tool, with SLIP escaping.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t *pData : the pointer to input string.
-  *
-  * @param  uint16_t DataLen : the string length.
-  *
-  * @return OK for successful.
-  *         FAIL for failed.
-  */
-STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
-
-/**
-  * @brief Receive an packet from download tool, with SLIP escaping.
-  *        Please do not call this function in SDK.
-  *
-  * @param  uint8_t *pData : the pointer to input string.
-  *
-  * @param  uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated.
-  *
-  * @param  uint8_t is_sync : 0, only one UART module;
-  *                           1, two UART modules.
-  *
-  * @return OK for successful.
-  *         FAIL for failed.
-  */
-STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync);
-
-extern UartDevice UartDev;
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ROM_UART_H_ */
diff --git a/tools/sdk/include/esp32/xtensa/cacheasm.h b/tools/sdk/include/esp32/xtensa/cacheasm.h
deleted file mode 100644
index 225e01b320e..00000000000
--- a/tools/sdk/include/esp32/xtensa/cacheasm.h
+++ /dev/null
@@ -1,962 +0,0 @@
-/*
- * xtensa/cacheasm.h -- assembler-specific cache related definitions
- *			that depend on CORE configuration
- *
- *  This file is logically part of xtensa/coreasm.h ,
- *  but is kept separate for modularity / compilation-performance.
- */
-
-/*
- * Copyright (c) 2001-2014 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CACHEASM_H
-#define XTENSA_CACHEASM_H
-
-#include <xtensa/coreasm.h>
-#include <xtensa/corebits.h>
-#include <xtensa/xtensa-xer.h>
-#include <xtensa/xtensa-versions.h>
-
-/*
- *  This header file defines assembler macros of the form:
- *	<x>cache_<func>
- *  where <x> is 'i' or 'd' for instruction and data caches,
- *  and <func> indicates the function of the macro.
- *
- *  The following functions <func> are defined,
- *  and apply only to the specified cache (I or D):
- *
- *  reset
- *	Resets the cache.
- *
- *  sync
- *	Makes sure any previous cache instructions have been completed;
- *	ie. makes sure any previous cache control operations
- *	have had full effect and been synchronized to memory.
- *	Eg. any invalidate completed [so as not to generate a hit],
- *	any writebacks or other pipelined writes written to memory, etc.
- *
- *  invalidate_line		(single cache line)
- *  invalidate_region		(specified memory range)
- *  invalidate_all		(entire cache)
- *	Invalidates all cache entries that cache
- *	data from the specified memory range.
- *	NOTE: locked entries are not invalidated.
- *
- *  writeback_line		(single cache line)
- *  writeback_region		(specified memory range)
- *  writeback_all		(entire cache)
- *	Writes back to memory all dirty cache entries
- *	that cache data from the specified memory range,
- *	and marks these entries as clean.
- *	NOTE: on some future implementations, this might
- *		also invalidate.
- *	NOTE: locked entries are written back, but never invalidated.
- *	NOTE: instruction caches never implement writeback.
- *
- *  writeback_inv_line		(single cache line)
- *  writeback_inv_region	(specified memory range)
- *  writeback_inv_all		(entire cache)
- *	Writes back to memory all dirty cache entries
- *	that cache data from the specified memory range,
- *	and invalidates these entries (including all clean
- *	cache entries that cache data from that range).
- *	NOTE: locked entries are written back but not invalidated.
- *	NOTE: instruction caches never implement writeback.
- *
- *  lock_line			(single cache line)
- *  lock_region			(specified memory range)
- *	Prefetch and lock the specified memory range into cache.
- *	NOTE:  if any part of the specified memory range cannot
- *	be locked, a Load/Store Error (for dcache) or Instruction
- *	Fetch Error (for icache) exception occurs.  These macros don't
- *	do anything special (yet anyway) to handle this situation.
- *
- *  unlock_line			(single cache line)
- *  unlock_region		(specified memory range)
- *  unlock_all			(entire cache)
- *	Unlock cache entries that cache the specified memory range.
- *	Entries not already locked are unaffected.
- *
- *  coherence_on
- *  coherence_off
- *      Turn off and on cache coherence
- *
- */
-
-
-
-/***************************   GENERIC -- ALL CACHES   ***************************/
-
-
-/*
- *  The following macros assume the following cache size/parameter limits
- *  in the current Xtensa core implementation:
- *	cache size:	1024 bytes minimum
- *	line size:	16 - 64 bytes
- *	way count:	1 - 4
- *
- *  Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
- *  Hence the assumption that each loop can execute four cache instructions.
- *
- *  Correspondingly, the offset range of instructions is assumed able to cover
- *  four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
- *  both hit and indexed cache instructions.  Ie. these offsets are all
- *  valid:  0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
- *  This is true of all original cache instructions
- *  (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
- *  of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
- *  This is also true of subsequent cache instructions
- *  (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
- *  of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
- *
- *  (Maximum cache size, currently 32k, doesn't affect the following macros.
- *  Cache ways > MMU min page size cause aliasing but that's another matter.)
- */
-
-
-
-/*
- *  Macro to apply an 'indexed' cache instruction to the entire cache.
- *
- *  Parameters:
- *	cainst      instruction/ that takes an address register parameter
- *              and an offset parameter (in range 0 .. 3*linesize).
- *	size        size of cache in bytes
- *	linesize    size of cache line in bytes (always power-of-2)
- *	assoc_or1   number of associativities (ways/sets) in cache
- *                  if all sets affected by cainst,
- *                  or 1 if only one set (or not all sets) of the cache
- *                  is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
- *	aa, ab      unique address registers (temporaries). 
- *	awb         set to other than a0 if wb type of instruction
- *	loopokay    1 allows use of zero-overhead loops, 0 does not
- *	immrange    range (max value) of cainst's immediate offset parameter, in bytes
- *              (NOTE: macro assumes immrange allows power-of-2 number of lines)
- */
-
-	.macro	cache_index_all		cainst, size, linesize, assoc_or1, aa, ab, loopokay, maxofs, awb=a0
-
-	//  Number of indices in cache (lines per way):
-	.set	.Lindices, (\size / (\linesize * \assoc_or1))
-	//  Number of indices processed per loop iteration (max 4):
-	.set	.Lperloop, .Lindices
-	.ifgt	.Lperloop - 4
-	 .set	.Lperloop, 4
-	.endif
-	//  Also limit instructions per loop if cache line size exceeds immediate range:
-	.set	.Lmaxperloop, (\maxofs / \linesize) + 1
-	.ifgt	.Lperloop - .Lmaxperloop
-	 .set	.Lperloop, .Lmaxperloop
-	.endif
-	//  Avoid addi of 128 which takes two instructions (addmi,addi):
-	.ifeq	.Lperloop*\linesize - 128
-	 .ifgt	.Lperloop - 1
-	  .set	.Lperloop, .Lperloop / 2
-	 .endif
-	.endif
-
-	//  \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
-	// XCHAL_ERRATUM_497 - don't execute using loop, to reduce the amount of added code
-	.ifne	(\loopokay & XCHAL_HAVE_LOOPS && !XCHAL_ERRATUM_497)
-
-	movi	\aa, .Lindices / .Lperloop		// number of loop iterations
-	// Possible improvement: need only loop if \aa > 1 ;
-	// however \aa == 1 is highly unlikely.
-	movi	\ab, 0		// to iterate over cache
-	loop		\aa, .Lend_cachex\@
-	.set	.Li, 0 ;     .rept .Lperloop
-	  \cainst	\ab, .Li*\linesize
-	.set	.Li, .Li+1 ; .endr
-	addi		\ab, \ab, .Lperloop*\linesize	// move to next line
-.Lend_cachex\@:
-
-	.else
-
-	movi	\aa, (\size / \assoc_or1)
-	// Possible improvement: need only loop if \aa > 1 ;
-	// however \aa == 1 is highly unlikely.
-	movi	\ab, 0		// to iterate over cache
-	.ifne	((\awb !=a0) & XCHAL_ERRATUM_497)		// don't use awb if set to a0
-	movi \awb, 0
-	.endif
-.Lstart_cachex\@:
-	.set	.Li, 0 ;     .rept .Lperloop
-	  \cainst	\ab, .Li*\linesize
-	.set	.Li, .Li+1 ; .endr
-	.ifne	((\awb !=a0) & XCHAL_ERRATUM_497)		// do memw after 8 cainst wb instructions
-	addi \awb, \awb, .Lperloop
-	blti \awb, 8, .Lstart_memw\@
-	memw
-	movi \awb, 0
-.Lstart_memw\@:
-	.endif
-	addi		\ab, \ab, .Lperloop*\linesize	// move to next line
-	bltu		\ab, \aa, .Lstart_cachex\@
-	.endif
-
-	.endm
-
-
-/*
- *  Macro to apply a 'hit' cache instruction to a memory region,
- *  ie. to any cache entries that cache a specified portion (region) of memory.
- *  Takes care of the unaligned cases, ie. may apply to one
- *  more cache line than $asize / lineSize if $aaddr is not aligned.
- *
- *
- *  Parameters are:
- *	cainst	instruction/macro that takes an address register parameter
- *		and an offset parameter (currently always zero)
- *		and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
- *	linesize_log2	log2(size of cache line in bytes)
- *	addr	register containing start address of region (clobbered)
- *	asize	register containing size of the region in bytes (clobbered)
- *	askew	unique register used as temporary
- *	awb		unique register used as temporary for erratum 497.
- *
- *  Note: A possible optimization to this macro is to apply the operation
- *  to the entire cache if the region exceeds the size of the cache
- *  by some empirically determined amount or factor.  Some experimentation
- *  is required to determine the appropriate factors, which also need
- *  to be tunable if required.
- */
-
-	.macro	cache_hit_region	cainst, linesize_log2, addr, asize, askew, awb=a0
-
-	//  Make \asize the number of iterations:
-	extui	\askew, \addr, 0, \linesize_log2	// get unalignment amount of \addr
-	add	\asize, \asize, \askew			// ... and add it to \asize
-	addi	\asize, \asize, (1 << \linesize_log2) - 1	// round up!
-	srli	\asize, \asize, \linesize_log2
-
-	//  Iterate over region:
-	.ifne	((\awb !=a0) & XCHAL_ERRATUM_497)		// don't use awb if set to a0
-	movi \awb, 0
-	.endif
-	floopnez	\asize, cacheh\@
-	\cainst		\addr, 0
-	.ifne	((\awb !=a0) & XCHAL_ERRATUM_497)		// do memw after 8 cainst wb instructions
-	addi \awb, \awb, 1
-	blti \awb, 8, .Lstart_memw\@
-	memw
-	movi \awb, 0
-.Lstart_memw\@:
-	.endif
-	addi		\addr, \addr, (1 << \linesize_log2)	// move to next line
-	floopend	\asize, cacheh\@
-	.endm
-
-
-
-
-
-/***************************   INSTRUCTION CACHE   ***************************/
-
-
-/*
- *  Reset/initialize the instruction cache by simply invalidating it:
- *  (need to unlock first also, if cache locking implemented):
- *
- *  Parameters:
- *	aa, ab		unique address registers (temporaries)
- */
-	.macro	icache_reset	aa, ab, loopokay=0
-	icache_unlock_all	\aa, \ab, \loopokay
-	icache_invalidate_all	\aa, \ab, \loopokay
-	.endm
-
-
-/*
- * Synchronize after an instruction cache operation,
- * to be sure everything is in sync with memory as to be
- * expected following any previous instruction cache control operations.
- *
- * Even if a config doesn't have caches, an isync is still needed
- * when instructions in any memory are modified, whether by a loader
- * or self-modifying code.  Therefore, this macro always produces
- * an isync, whether or not an icache is present.
- *
- * Parameters are:
- *	ar	an address register (temporary) (currently unused, but may be used in future)
- */
-	.macro	icache_sync	ar
-	isync
-	.endm
-
-
-
-/*
- *  Invalidate a single line of the instruction cache.
- *  Parameters are:
- *	ar	address register that contains (virtual) address to invalidate
- *		(may get clobbered in a future implementation, but not currently)
- *	offset	(optional) offset to add to \ar to compute effective address to invalidate
- *		(note: some number of lsbits are ignored)
- */
-	.macro	icache_invalidate_line	ar, offset
-#if XCHAL_ICACHE_SIZE > 0
-	ihi	\ar, \offset		// invalidate icache line
-	icache_sync	\ar
-#endif
-	.endm
-
-
-
-
-/*
- *  Invalidate instruction  cache entries that cache a specified portion of memory.
- *  Parameters are:
- *	astart	start address (register gets clobbered)
- *	asize	size of the region in bytes (register gets clobbered)
- *	ac	unique register used as temporary
- */
-	.macro	icache_invalidate_region	astart, asize, ac
-#if XCHAL_ICACHE_SIZE > 0
-	//  Instruction cache region invalidation:
-	cache_hit_region	ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
-	icache_sync	\ac
-	//  End of instruction cache region invalidation
-#endif
-	.endm
-
-
-
-/*
- *  Invalidate entire instruction cache.
- *
- *  Parameters:
- *	aa, ab		unique address registers (temporaries)
- */
-	.macro	icache_invalidate_all	aa, ab, loopokay=1
-#if XCHAL_ICACHE_SIZE > 0
-	//  Instruction cache invalidation:
-	cache_index_all		iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loopokay, 1020
-	icache_sync	\aa
-	//  End of instruction cache invalidation
-#endif
-	.endm
-
-
-
-/*
- *  Lock (prefetch & lock) a single line of the instruction cache.
- *
- *  Parameters are:
- *	ar	address register that contains (virtual) address to lock
- *		(may get clobbered in a future implementation, but not currently)
- *	offset	offset to add to \ar to compute effective address to lock
- *		(note: some number of lsbits are ignored)
- */
-	.macro	icache_lock_line	ar, offset
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-	ipfl	\ar, \offset	/* prefetch and lock icache line */
-	icache_sync	\ar
-#endif
-	.endm
-
-
-
-/*
- *  Lock (prefetch & lock) a specified portion of memory into the instruction cache.
- *  Parameters are:
- *	astart	start address (register gets clobbered)
- *	asize	size of the region in bytes (register gets clobbered)
- *	ac	unique register used as temporary
- */
-	.macro	icache_lock_region	astart, asize, ac
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-	//  Instruction cache region lock:
-	cache_hit_region	ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
-	icache_sync	\ac
-	//  End of instruction cache region lock
-#endif
-	.endm
-
-
-
-/*
- *  Unlock a single line of the instruction cache.
- *
- *  Parameters are:
- *	ar	address register that contains (virtual) address to unlock
- *		(may get clobbered in a future implementation, but not currently)
- *	offset	offset to add to \ar to compute effective address to unlock
- *		(note: some number of lsbits are ignored)
- */
-	.macro	icache_unlock_line	ar, offset
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-	ihu	\ar, \offset	/* unlock icache line */
-	icache_sync	\ar
-#endif
-	.endm
-
-
-
-/*
- *  Unlock a specified portion of memory from the instruction cache.
- *  Parameters are:
- *	astart	start address (register gets clobbered)
- *	asize	size of the region in bytes (register gets clobbered)
- *	ac	unique register used as temporary
- */
-	.macro	icache_unlock_region	astart, asize, ac
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-	//  Instruction cache region unlock:
-	cache_hit_region	ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
-	icache_sync	\ac
-	//  End of instruction cache region unlock
-#endif
-	.endm
-
-
-
-/*
- *  Unlock entire instruction cache.
- *
- *  Parameters:
- *	aa, ab		unique address registers (temporaries)
- */
-	.macro	icache_unlock_all	aa, ab, loopokay=1
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-	//  Instruction cache unlock:
-	cache_index_all		iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
-	icache_sync	\aa
-	//  End of instruction cache unlock
-#endif
-	.endm
-
-
-
-
-
-/***************************   DATA CACHE   ***************************/
-
-
-
-/*
- *  Reset/initialize the data cache by simply invalidating it
- *  (need to unlock first also, if cache locking implemented):
- *
- *  Parameters:
- *	aa, ab		unique address registers (temporaries)
- */
-	.macro	dcache_reset	aa, ab, loopokay=0
-	dcache_unlock_all	\aa, \ab, \loopokay
-	dcache_invalidate_all	\aa, \ab, \loopokay
-	.endm
-
-
-
-
-/*
- * Synchronize after a data cache operation,
- * to be sure everything is in sync with memory as to be
- * expected following any previous data cache control operations.
- *
- * Parameters are:
- *	ar	an address register (temporary) (currently unused, but may be used in future)
- */
-	.macro	dcache_sync	ar, wbtype=0
-#if XCHAL_DCACHE_SIZE > 0
-	//  No synchronization is needed.
-	//  (memw may be desired e.g. after writeback operation to help ensure subsequent
-	//   external accesses are seen to follow that writeback, however that's outside
-	//   the scope of this macro)
-
-	//dsync
-	.ifne	(\wbtype & XCHAL_ERRATUM_497)
-	memw
-	.endif
-#endif
-	.endm
-
-
-
-/*
- * Turn on cache coherence.
- *
- * WARNING:  for RE-201x.x and later hardware, any interrupt that tries
- * to change MEMCTL will see its changes dropped if the interrupt comes
- * in the middle of this routine.  If this might be an issue, call this
- * routine with interrupts disabled.
- *
- * Parameters are:
- *	ar,at	two scratch address registers (both clobbered)
- */
-	.macro	cache_coherence_on	ar at
-#if XCHAL_DCACHE_IS_COHERENT
-# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
-	/*  Have MEMCTL.  Enable snoop responses.  */
-	rsr.memctl	\ar
-	movi		\at, MEMCTL_SNOOP_EN
-	or		\ar, \ar, \at
-	wsr.memctl	\ar
-# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
-	/* Opt into coherence for MX (for backward compatibility / testing).  */
-	movi	\ar, 1
-	movi	\at, XER_CCON
-	wer	\ar, \at
-	extw
-# endif
-#endif
-	.endm
-
-
-
-/*
- * Turn off cache coherence.
- *
- * NOTE:  this is generally preceded by emptying the cache;
- * see xthal_cache_coherence_optout() in hal/coherence.c for details.
- *
- * WARNING:  for RE-201x.x and later hardware, any interrupt that tries
- * to change MEMCTL will see its changes dropped if the interrupt comes
- * in the middle of this routine.  If this might be an issue, call this
- * routine with interrupts disabled.
- *
- * Parameters are:
- *	ar,at	two scratch address registers (both clobbered)
- */
-	.macro	cache_coherence_off	ar at
-#if XCHAL_DCACHE_IS_COHERENT
-# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
-	/*  Have MEMCTL.  Disable snoop responses.  */
-	rsr.memctl	\ar
-	movi		\at, ~MEMCTL_SNOOP_EN
-	and		\ar, \ar, \at
-	wsr.memctl	\ar
-# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
-	/* Opt out of coherence, for MX (for backward compatibility / testing).  */
-	extw
-	movi	\at, 0
-	movi	\ar, XER_CCON
-	wer	\at, \ar
-	extw
-# endif
-#endif
-	.endm
-
-
-
-/*
- * Synchronize after a data store operation,
- * to be sure the stored data is completely off the processor
- * (and assuming there is no buffering outside the processor,
- *  that the data is in memory).  This may be required to
- * ensure that the processor's write buffers are emptied.
- * A MEMW followed by a read guarantees this, by definition.
- * We also try to make sure the read itself completes.
- *
- * Parameters are:
- *	ar	an address register (temporary)
- */
-	.macro	write_sync	ar
-	memw			// ensure previous memory accesses are complete prior to subsequent memory accesses
-	l32i	\ar, sp, 0	// completing this read ensures any previous write has completed, because of MEMW
-	//slot
-	add	\ar, \ar, \ar	// use the result of the read to help ensure the read completes (in future architectures)
-	.endm
-
-
-/*
- *  Invalidate a single line of the data cache.
- *  Parameters are:
- *	ar	address register that contains (virtual) address to invalidate
- *		(may get clobbered in a future implementation, but not currently)
- *	offset	(optional) offset to add to \ar to compute effective address to invalidate
- *		(note: some number of lsbits are ignored)
- */
-	.macro	dcache_invalidate_line	ar, offset
-#if XCHAL_DCACHE_SIZE > 0
-	dhi	\ar, \offset
-	dcache_sync	\ar
-#endif
-	.endm
-
-
-
-
-
-/*
- *  Invalidate data cache entries that cache a specified portion of memory.
- *  Parameters are:
- *	astart	start address (register gets clobbered)
- *	asize	size of the region in bytes (register gets clobbered)
- *	ac	unique register used as temporary
- */
-	.macro	dcache_invalidate_region	astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0
-	//  Data cache region invalidation:
-	cache_hit_region	dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
-	dcache_sync	\ac
-	//  End of data cache region invalidation
-#endif
-	.endm
-
-
-
-/*
- *  Invalidate entire data cache.
- *
- *  Parameters:
- *	aa, ab		unique address registers (temporaries)
- */
-	.macro	dcache_invalidate_all	aa, ab, loopokay=1
-#if XCHAL_DCACHE_SIZE > 0
-	//  Data cache invalidation:
-	cache_index_all		dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020
-	dcache_sync	\aa
-	//  End of data cache invalidation
-#endif
-	.endm
-
-
-
-/*
- *  Writeback a single line of the data cache.
- *  Parameters are:
- *	ar	address register that contains (virtual) address to writeback
- *		(may get clobbered in a future implementation, but not currently)
- *	offset	offset to add to \ar to compute effective address to writeback
- *		(note: some number of lsbits are ignored)
- */
-	.macro	dcache_writeback_line	ar, offset
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
-	dhwb	\ar, \offset
-	dcache_sync	\ar, wbtype=1
-#endif
-	.endm
-
-
-
-/*
- *  Writeback dirty data cache entries that cache a specified portion of memory.
- *  Parameters are:
- *	astart	start address (register gets clobbered)
- *	asize	size of the region in bytes (register gets clobbered)
- *	ac	unique register used as temporary
- */
-	.macro	dcache_writeback_region		astart, asize, ac, awb
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
-	//  Data cache region writeback:
-	cache_hit_region	dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
-	dcache_sync	\ac, wbtype=1
-	//  End of data cache region writeback
-#endif
-	.endm
-
-
-
-/*
- *  Writeback entire data cache.
- *  Parameters:
- *	aa, ab		unique address registers (temporaries)
- */
-	.macro	dcache_writeback_all	aa, ab, awb, loopokay=1
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
-	//  Data cache writeback:
-	cache_index_all		diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb,
-	dcache_sync	\aa, wbtype=1
-	//  End of data cache writeback
-#endif
-	.endm
-
-
-
-/*
- *  Writeback and invalidate a single line of the data cache.
- *  Parameters are:
- *	ar	address register that contains (virtual) address to writeback and invalidate
- *		(may get clobbered in a future implementation, but not currently)
- *	offset	offset to add to \ar to compute effective address to writeback and invalidate
- *		(note: some number of lsbits are ignored)
- */
-	.macro	dcache_writeback_inv_line	ar, offset
-#if XCHAL_DCACHE_SIZE > 0
-	dhwbi	\ar, \offset	/* writeback and invalidate dcache line */
-	dcache_sync	\ar, wbtype=1
-#endif
-	.endm
-
-
-
-/*
- *  Writeback and invalidate data cache entries that cache a specified portion of memory.
- *  Parameters are:
- *	astart	start address (register gets clobbered)
- *	asize	size of the region in bytes (register gets clobbered)
- *	ac	unique register used as temporary
- */
-	.macro	dcache_writeback_inv_region	astart, asize, ac, awb
-#if XCHAL_DCACHE_SIZE > 0
-	//  Data cache region writeback and invalidate:
-	cache_hit_region	dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
-	dcache_sync	\ac, wbtype=1
-	//  End of data cache region writeback and invalidate
-#endif
-	.endm
-
-
-
-/*
- *  Writeback and invalidate entire data cache.
- *  Parameters:
- *	aa, ab		unique address registers (temporaries)
- */
-	.macro	dcache_writeback_inv_all	aa, ab, awb, loopokay=1
-#if XCHAL_DCACHE_SIZE > 0
-	//  Data cache writeback and invalidate:
-#if XCHAL_DCACHE_IS_WRITEBACK
-	cache_index_all		diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb
-	dcache_sync	\aa, wbtype=1
-#else /*writeback*/
-	//  Data cache does not support writeback, so just invalidate: */
-	dcache_invalidate_all	\aa, \ab, \loopokay
-#endif /*writeback*/
-	//  End of data cache writeback and invalidate
-#endif
-	.endm
-
-
-
-
-/*
- *  Lock (prefetch & lock) a single line of the data cache.
- *
- *  Parameters are:
- *	ar	address register that contains (virtual) address to lock
- *		(may get clobbered in a future implementation, but not currently)
- *	offset	offset to add to \ar to compute effective address to lock
- *		(note: some number of lsbits are ignored)
- */
-	.macro	dcache_lock_line	ar, offset
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-	dpfl	\ar, \offset	/* prefetch and lock dcache line */
-	dcache_sync	\ar
-#endif
-	.endm
-
-
-
-/*
- *  Lock (prefetch & lock) a specified portion of memory into the data cache.
- *  Parameters are:
- *	astart	start address (register gets clobbered)
- *	asize	size of the region in bytes (register gets clobbered)
- *	ac	unique register used as temporary
- */
-	.macro	dcache_lock_region	astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-	//  Data cache region lock:
-	cache_hit_region	dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
-	dcache_sync	\ac
-	//  End of data cache region lock
-#endif
-	.endm
-
-
-
-/*
- *  Unlock a single line of the data cache.
- *
- *  Parameters are:
- *	ar	address register that contains (virtual) address to unlock
- *		(may get clobbered in a future implementation, but not currently)
- *	offset	offset to add to \ar to compute effective address to unlock
- *		(note: some number of lsbits are ignored)
- */
-	.macro	dcache_unlock_line	ar, offset
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-	dhu	\ar, \offset	/* unlock dcache line */
-	dcache_sync	\ar
-#endif
-	.endm
-
-
-
-/*
- *  Unlock a specified portion of memory from the data cache.
- *  Parameters are:
- *	astart	start address (register gets clobbered)
- *	asize	size of the region in bytes (register gets clobbered)
- *	ac	unique register used as temporary
- */
-	.macro	dcache_unlock_region	astart, asize, ac
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-	//  Data cache region unlock:
-	cache_hit_region	dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
-	dcache_sync	\ac
-	//  End of data cache region unlock
-#endif
-	.endm
-
-
-
-/*
- *  Unlock entire data cache.
- *
- *  Parameters:
- *	aa, ab		unique address registers (temporaries)
- */
-	.macro	dcache_unlock_all	aa, ab, loopokay=1
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-	//  Data cache unlock:
-	cache_index_all		diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab,  \loopokay, 240
-	dcache_sync	\aa
-	//  End of data cache unlock
-#endif
-	.endm
-
-
-
-/*
- * Get the number of enabled icache ways. Note that this may
- * be different from the value read from the MEMCTL register.
- *
- * Parameters:
- *	aa	address register where value is returned
- */
-	.macro	icache_get_ways		aa
-#if XCHAL_ICACHE_SIZE > 0
-#if XCHAL_HAVE_ICACHE_DYN_WAYS
-	// Read from MEMCTL and shift/mask
-	rsr	\aa, MEMCTL
-	extui	\aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS
-	blti	\aa, XCHAL_ICACHE_WAYS, .Licgw
-	movi	\aa, XCHAL_ICACHE_WAYS
-.Licgw:
-#else
-	// All ways are always enabled
-	movi	\aa, XCHAL_ICACHE_WAYS
-#endif
-#else
-	// No icache
-	movi	\aa, 0
-#endif
-	.endm
-
-
-
-/*
- * Set the number of enabled icache ways.
- *
- * Parameters:
- *	aa      address register specifying number of ways (trashed)
- *	ab,ac	address register for scratch use (trashed)
- */
-	.macro  icache_set_ways		aa, ab, ac
-#if XCHAL_ICACHE_SIZE > 0
-#if XCHAL_HAVE_ICACHE_DYN_WAYS
-	movi	\ac, MEMCTL_ICWU_CLR_MASK	// set up to clear bits 18-22
-	rsr	\ab, MEMCTL
-	and	\ab, \ab, \ac
-	movi	\ac, MEMCTL_INV_EN		// set bit 23
-	slli	\aa, \aa, MEMCTL_ICWU_SHIFT	// move to right spot
-	or	\ab, \ab, \aa
-	or	\ab, \ab, \ac
-	wsr	\ab, MEMCTL
-	isync
-#else
-	// All ways are always enabled
-#endif
-#else
-	// No icache
-#endif
-	.endm
-
-
-
-/*
- * Get the number of enabled dcache ways. Note that this may
- * be different from the value read from the MEMCTL register.
- *
- * Parameters:
- *	aa	address register where value is returned
- */
-	.macro	dcache_get_ways		aa
-#if XCHAL_DCACHE_SIZE > 0
-#if XCHAL_HAVE_DCACHE_DYN_WAYS
-	// Read from MEMCTL and shift/mask
-	rsr	\aa, MEMCTL
-	extui	\aa, \aa, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS
-	blti	\aa, XCHAL_DCACHE_WAYS, .Ldcgw
-	movi	\aa, XCHAL_DCACHE_WAYS
-.Ldcgw:
-#else
-	// All ways are always enabled  
-	movi	\aa, XCHAL_DCACHE_WAYS
-#endif
-#else
-	// No dcache
-	movi	\aa, 0
-#endif
-	.endm
-
-
-
-/*
- * Set the number of enabled dcache ways.
- *
- * Parameters:
- *	aa	address register specifying number of ways (trashed)
- *	ab,ac	address register for scratch use (trashed)
- */
-	.macro	dcache_set_ways		aa, ab, ac
-#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS
-	movi	\ac, MEMCTL_DCWA_CLR_MASK	// set up to clear bits 13-17
-	rsr	\ab, MEMCTL
-	and	\ab, \ab, \ac			// clear ways allocatable
-	slli	\ac, \aa, MEMCTL_DCWA_SHIFT
-	or	\ab, \ab, \ac			// set ways allocatable
-	wsr	\ab, MEMCTL
-#if XCHAL_DCACHE_IS_WRITEBACK
-	// Check if the way count is increasing or decreasing
-	extui	\ac, \ab, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS			// bits 8-12 - ways in use
-	bge	\aa, \ac, .Ldsw3						// equal or increasing
-	slli	\ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH	// start way number
-	slli	\ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH	// end way number
-.Ldsw1:
-	diwbui.p	\ab		// auto-increments ab
-	bge	\ab, \ac, .Ldsw2
-	beqz	\ab, .Ldsw2
-	j	.Ldsw1
-.Ldsw2:
-	rsr	\ab, MEMCTL
-#endif
-.Ldsw3:
-	// No dirty data to write back, just set the new number of ways
-	movi	\ac, MEMCTL_DCWU_CLR_MASK		// set up to clear bits 8-12
-	and	\ab, \ab, \ac				// clear ways in use
-	movi	\ac, MEMCTL_INV_EN
-	or	\ab, \ab, \ac				// set bit 23
-	slli	\aa, \aa, MEMCTL_DCWU_SHIFT
-	or	\ab, \ab, \aa				// set ways in use
-	wsr	\ab, MEMCTL
-#else
-	// No dcache or no way disable support
-#endif
-	.endm
-
-#endif /*XTENSA_CACHEASM_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/cacheattrasm.h b/tools/sdk/include/esp32/xtensa/cacheattrasm.h
deleted file mode 100644
index 20c4cfd558b..00000000000
--- a/tools/sdk/include/esp32/xtensa/cacheattrasm.h
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions
- *			that depend on CORE configuration
- *
- *  This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h),
- *  but is kept separate for modularity / compilation-performance.
- */
-
-/*
- * Copyright (c) 2001-2009 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CACHEATTRASM_H
-#define XTENSA_CACHEATTRASM_H
-
-#include <xtensa/coreasm.h>
-
-/*  Determine whether cache attributes are controlled using eight 512MB entries:  */
-#define XCHAL_CA_8X512	(XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
-	|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY))
-
-
-/*
- *  This header file defines assembler macros of the form:
- *	<x>cacheattr_<func>
- *  where:
- *	<x> is 'i', 'd' or absent for instruction, data
- *		or both caches; and
- *	<func> indicates the function of the macro.
- *
- *  The following functions are defined:
- *
- *  icacheattr_get
- *	Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
- *
- *  dcacheattr_get
- *	Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
- *	(Note:  for configs with a real CACHEATTR register, the
- *	 above two macros are identical.)
- *
- *  cacheattr_set
- *	Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
- *	Works even when changing one's own code's attributes.
- *
- *  icacheattr_is_enabled  label
- *	Branches to \label if I-cache appears to have been enabled
- *	(eg. if CACHEATTR contains a cache-enabled attribute).
- *	(clobbers a2-a5,SAR)
- *
- *  dcacheattr_is_enabled  label
- *	Branches to \label if D-cache appears to have been enabled
- *	(eg. if CACHEATTR contains a cache-enabled attribute).
- *	(clobbers a2-a5,SAR)
- *
- *  cacheattr_is_enabled  label
- *	Branches to \label if either I-cache or D-cache appears to have been enabled
- *	(eg. if CACHEATTR contains a cache-enabled attribute).
- *	(clobbers a2-a5,SAR)
- *
- *  The following macros are only defined under certain conditions:
- *
- *  icacheattr_set	(if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
- *	Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
- *
- *  dcacheattr_set	(if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
- *	Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
- */
-
-
-
-/***************************   GENERIC -- ALL CACHES   ***************************/
-
-/*
- *  _cacheattr_get
- *
- *  (Internal macro.)
- *  Returns value of CACHEATTR register (or closest equivalent) in a2.
- *  
- *  Entry:
- *	(none)
- *  Exit:
- *	a2	value read from CACHEATTR
- *	a3-a5	clobbered (temporaries)
- */
-	.macro	_cacheattr_get	tlb
-#if XCHAL_HAVE_CACHEATTR
-	rsr	a2, CACHEATTR
-#elif XCHAL_CA_8X512
-	//  We have a config that "mimics" CACHEATTR using a simplified
-	//  "MMU" composed of a single statically-mapped way.
-	//  DTLB and ITLB are independent, so there's no single
-	//  cache attribute that can describe both.  So for now
-	//  just return the DTLB state.
-	movi	a5, 0xE0000000
-	movi	a2, 0
-	movi	a3, XCHAL_SPANNING_WAY
-1:	add	a3, a3, a5	// next segment
-	r&tlb&1	a4, a3		// get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
-	dsync	// interlock???
-	slli	a2, a2, 4
-	extui	a4, a4, 0, 4	// extract CA
-	or	a2, a2, a4
-	bgeui	a3, 16, 1b
-#else
-	//  This macro isn't applicable to arbitrary MMU configurations.
-	//  Just return zero.
-	movi	a2, 0
-#endif
-	.endm
-
-	.macro	icacheattr_get
-	_cacheattr_get	itlb
-	.endm
-
-	.macro	dcacheattr_get
-	_cacheattr_get	dtlb
-	.endm
-
-
-/* Default (powerup/reset) value of CACHEATTR,
-   all BYPASS mode (ie. disabled/bypassed caches): */
-#if XCHAL_HAVE_PTP_MMU
-# define XCHAL_CACHEATTR_ALL_BYPASS	0x33333333
-#else
-# define XCHAL_CACHEATTR_ALL_BYPASS	0x22222222
-#endif
-
-#if XCHAL_CA_8X512
-
-#if XCHAL_HAVE_PTP_MMU
-# define XCHAL_FCA_ENAMASK	0x0AA0	/* bitmap of fetch attributes that require enabled icache */
-# define XCHAL_LCA_ENAMASK	0x0FF0	/* bitmap of load  attributes that require enabled dcache */
-# define XCHAL_SCA_ENAMASK	0x0CC0	/* bitmap of store attributes that require enabled dcache */
-#else
-# define XCHAL_FCA_ENAMASK	0x003A	/* bitmap of fetch attributes that require enabled icache */
-# define XCHAL_LCA_ENAMASK	0x0033	/* bitmap of load  attributes that require enabled dcache */
-# define XCHAL_SCA_ENAMASK	0x0033	/* bitmap of store attributes that require enabled dcache */
-#endif
-#define XCHAL_LSCA_ENAMASK	(XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK)	/* l/s attrs requiring enabled dcache */
-#define XCHAL_ALLCA_ENAMASK	(XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK)	/* all attrs requiring enabled caches */
-
-/*
- *  _cacheattr_is_enabled
- *
- *  (Internal macro.)
- *  Branches to \label if CACHEATTR in a2 indicates an enabled
- *  cache, using mask in a3.
- *
- *  Parameters:
- *	label	where to branch to if cache is enabled
- *  Entry:
- *	a2	contains CACHEATTR value used to determine whether
- *		caches are enabled
- *	a3	16-bit constant where each bit correspond to
- *		one of the 16 possible CA values (in a CACHEATTR mask);
- *		CA values that indicate the cache is enabled
- *		have their corresponding bit set in this mask
- *		(eg. use XCHAL_xCA_ENAMASK , above)
- *  Exit:
- *	a2,a4,a5	clobbered
- *	SAR		clobbered
- */
-	.macro	_cacheattr_is_enabled	label
-	movi	a4, 8		// loop 8 times
-.Lcaife\@:
-	extui	a5, a2, 0, 4	// get CA nibble
-	ssr	a5		// index into mask according to CA...
-	srl	a5, a3		// ...and get CA's mask bit in a5 bit 0
-	bbsi.l	a5, 0, \label	// if CA indicates cache enabled, jump to label
-	srli	a2, a2, 4	// next nibble
-	addi	a4, a4, -1
-	bnez	a4, .Lcaife\@	// loop for each nibble
-	.endm
-
-#else /* XCHAL_CA_8X512 */
-	.macro	_cacheattr_is_enabled	label
-	j	\label		// macro not applicable, assume caches always enabled
-	.endm
-#endif /* XCHAL_CA_8X512 */
-
-
-
-/*
- *  icacheattr_is_enabled
- *
- *  Branches to \label if I-cache is enabled.
- *
- *  Parameters:
- *	label	where to branch to if icache is enabled
- *  Entry:
- *	(none)
- *  Exit:
- *	a2-a5, SAR	clobbered (temporaries)
- */
-	.macro	icacheattr_is_enabled	label
-#if XCHAL_CA_8X512
-	icacheattr_get
-	movi	a3, XCHAL_FCA_ENAMASK
-#endif
-	_cacheattr_is_enabled	\label
-	.endm
-
-/*
- *  dcacheattr_is_enabled
- *
- *  Branches to \label if D-cache is enabled.
- *
- *  Parameters:
- *	label	where to branch to if dcache is enabled
- *  Entry:
- *	(none)
- *  Exit:
- *	a2-a5, SAR	clobbered (temporaries)
- */
-	.macro	dcacheattr_is_enabled	label
-#if XCHAL_CA_8X512
-	dcacheattr_get
-	movi	a3, XCHAL_LSCA_ENAMASK
-#endif
-	_cacheattr_is_enabled	\label
-	.endm
-
-/*
- *  cacheattr_is_enabled
- *
- *  Branches to \label if either I-cache or D-cache is enabled.
- *
- *  Parameters:
- *	label	where to branch to if a cache is enabled
- *  Entry:
- *	(none)
- *  Exit:
- *	a2-a5, SAR	clobbered (temporaries)
- */
-	.macro	cacheattr_is_enabled	label
-#if XCHAL_HAVE_CACHEATTR
-	rsr	a2, CACHEATTR
-	movi	a3, XCHAL_ALLCA_ENAMASK
-#elif XCHAL_CA_8X512
-	icacheattr_get
-	movi	a3, XCHAL_FCA_ENAMASK
-	_cacheattr_is_enabled	\label
-	dcacheattr_get
-	movi	a3, XCHAL_LSCA_ENAMASK
-#endif
-	_cacheattr_is_enabled	\label
-	.endm
-
-
-
-/*
- *  The ISA does not have a defined way to change the
- *  instruction cache attributes of the running code,
- *  ie. of the memory area that encloses the current PC.
- *  However, each micro-architecture (or class of
- *  configurations within a micro-architecture)
- *  provides a way to deal with this issue.
- *
- *  Here are a few macros used to implement the relevant
- *  approach taken.
- */
-
-#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
-	//  We have a config that "mimics" CACHEATTR using a simplified
-	//  "MMU" composed of a single statically-mapped way.
-
-/*
- *  icacheattr_set
- *
- *  Entry:
- *	a2		cacheattr value to set
- *  Exit:
- *	a2		unchanged
- *	a3-a8		clobbered (temporaries)
- */
-	.macro	icacheattr_set
-
-	movi	a5, 0xE0000000	// mask of upper 3 bits
-	movi	a6, 3f		// PC where ITLB is set
-	movi	a3, XCHAL_SPANNING_WAY	// start at region 0 (0 .. 7)
-	mov	a7, a2		// copy a2 so it doesn't get clobbered
-	and	a6, a6, a5	// upper 3 bits of local PC area
-	j	3f
-
-	//  Use micro-architecture specific method.
-	//  The following 4-instruction sequence is aligned such that
-	//  it all fits within a single I-cache line.  Sixteen byte
-	//  alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
-	//  actually causes problems because that can be greater than
-	//  the alignment of the reset vector, where this macro is often
-	//  invoked, which would cause the linker to align the reset
-	//  vector code away from the reset vector!!).
-	.begin	no-transform
-	.align	16 /*XCHAL_ICACHE_LINESIZE*/
-1:	witlb	a4, a3		// write wired PTE (CA, no PPN) of 512MB segment to ITLB
-	isync
-	.end	no-transform
-	nop
-	nop
-
-	sub	a3, a3, a5	// next segment (add 0x20000000)
-	bltui	a3, 16, 4f	// done?
-
-	//  Note that in the WITLB loop, we don't do any load/stores
-	//  (may not be an issue here, but it is important in the DTLB case).
-2:	srli	a7, a7, 4	// next CA
-3:
-# if XCHAL_HAVE_MIMIC_CACHEATTR
-	extui	a4, a7, 0, 4	// extract CA to set
-# else	/* have translation, preserve it: */
-	ritlb1	a8, a3		// get current PPN+CA of segment
-	//dsync	// interlock???
-	extui	a4, a7, 0, 4	// extract CA to set
-	srli	a8, a8, 4	// clear CA but keep PPN ...
-	slli	a8, a8, 4	// ...
-	add	a4, a4, a8	// combine new CA with PPN to preserve
-# endif
-	beq	a3, a6, 1b	// current PC's region? if so, do it in a safe way
-	witlb	a4, a3		// write wired PTE (CA [+PPN]) of 512MB segment to ITLB
-	sub	a3, a3, a5	// next segment (add 0x20000000)
-	bgeui	a3, 16, 2b
-	isync			// make sure all ifetch changes take effect
-4:
-	.endm	// icacheattr_set
-
-
-/*
- *  dcacheattr_set
- *
- *  Entry:
- *	a2		cacheattr value to set
- *  Exit:
- *	a2		unchanged
- *	a3-a8		clobbered (temporaries)
- */
-
-	.macro	dcacheattr_set
-
-	movi	a5, 0xE0000000	// mask of upper 3 bits
-	movi	a3, XCHAL_SPANNING_WAY	// start at region 0 (0 .. 7)
-	mov	a7, a2		// copy a2 so it doesn't get clobbered
-	//  Note that in the WDTLB loop, we don't do any load/stores
-2:	//  (including implicit l32r via movi) because it isn't safe.
-# if XCHAL_HAVE_MIMIC_CACHEATTR
-	extui	a4, a7, 0, 4	// extract CA to set
-# else	/* have translation, preserve it: */
-	rdtlb1	a8, a3		// get current PPN+CA of segment
-	//dsync	// interlock???
-	extui	a4, a7, 0, 4	// extract CA to set
-	srli	a8, a8, 4	// clear CA but keep PPN ...
-	slli	a8, a8, 4	// ...
-	add	a4, a4, a8	// combine new CA with PPN to preserve
-# endif
-	wdtlb	a4, a3		// write wired PTE (CA [+PPN]) of 512MB segment to DTLB
-	sub	a3, a3, a5	// next segment (add 0x20000000)
-	srli	a7, a7, 4	// next CA
-	bgeui	a3, 16, 2b
-	dsync			// make sure all data path changes take effect
-	.endm	// dcacheattr_set
-
-#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */
-
-
-
-/*
- *  cacheattr_set
- *
- *  Macro that sets the current CACHEATTR safely
- *  (both i and d) according to the current contents of a2.
- *  It works even when changing the cache attributes of
- *  the currently running code.
- *
- *  Entry:
- *	a2		cacheattr value to set
- *  Exit:
- *	a2		unchanged
- *	a3-a8		clobbered (temporaries)
- */
-	.macro	cacheattr_set
-
-#if XCHAL_HAVE_CACHEATTR
-# if XCHAL_ICACHE_LINESIZE < 4
-	//  No i-cache, so can always safely write to CACHEATTR:
-	wsr	a2, CACHEATTR
-# else
-	//  The Athens micro-architecture, when using the old
-	//  exception architecture option (ie. with the CACHEATTR register)
-	//  allows changing the cache attributes of the running code
-	//  using the following exact sequence aligned to be within
-	//  an instruction cache line.  (NOTE: using XCHAL_ICACHE_LINESIZE
-	//  alignment actually causes problems because that can be greater
-	//  than the alignment of the reset vector, where this macro is often
-	//  invoked, which would cause the linker to align the reset
-	//  vector code away from the reset vector!!).
-	j	1f
-	.begin	no-transform
-	.align	16 /*XCHAL_ICACHE_LINESIZE*/	// align to within an I-cache line
-1:	wsr	a2, CACHEATTR
-	isync
-	.end	no-transform
-	nop
-	nop
-# endif
-#elif XCHAL_CA_8X512
-	//  DTLB and ITLB are independent, but to keep semantics
-	//  of this macro we simply write to both.
-	icacheattr_set
-	dcacheattr_set
-#else
-	//  This macro isn't applicable to arbitrary MMU configurations.
-	//  Do nothing in this case.
-#endif
-	.endm
-
-
-#endif /*XTENSA_CACHEATTRASM_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/config/core-isa.h b/tools/sdk/include/esp32/xtensa/config/core-isa.h
deleted file mode 100644
index 1845647264f..00000000000
--- a/tools/sdk/include/esp32/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,655 +0,0 @@
-/* 
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- *				processor CORE configuration
- *
- *  See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
-   Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
-	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		1	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
-/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			1	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		1	/* MAC16 package */
-
-#define XCHAL_HAVE_FUSION		 0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP	 0	        /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES	 0	        /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	 0       /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	 0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	 0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS	 0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND	 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI        0     /* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP      0   /* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		0	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0	
-
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU         0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU         0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP                 1      /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV             1  /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP           1        /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT            1 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT           1        /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP                        0     /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV            0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP          0       /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT           0        /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT          0       /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		1	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL				/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY    1                 	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  0               	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4		        0	/* PDX4 */
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */
-
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	4	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
-						   (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	0	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	0	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		1	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	1	/* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION		1100003	/* sw version of this header */
-
-#define XCHAL_CORE_ID			"esp32_v3_49_prod"	/* alphanum core name
-						   (CoreID) set in the Xtensa
-						   Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID		0x0005FE96	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC2BCFFFE	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x1CC5FE96	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX6.0.3"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2600	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		3	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION		260003	/* major*100+minor */
-#define XCHAL_HW_REL_LX6		1
-#define XCHAL_HW_REL_LX6_0		1
-#define XCHAL_HW_REL_LX6_0_3		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2600	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	3	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		260003	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2600	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	3	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		260003	/* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE		4	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		4	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		2	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		2	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		0	/* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE		0	/* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK	0	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	0	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		0	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST		0	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		0	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	0	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	0	/* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
-    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
-#define XCHAL_HAVE_AXI			0	/* AXI bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			0	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			0	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		0
-#define XCHAL_DCACHE_SETWIDTH		0
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		1
-#define XCHAL_DCACHE_WAYS		1
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	0
-#define XCHAL_DCACHE_LINE_LOCKABLE	0
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	1
-#define XCHAL_DCACHE_ACCESS_SIZE	1
-
-#define XCHAL_DCACHE_BANKS		0	/* number of banks */
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-#define XCHAL_CA_BITS			4
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM		1	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		1	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			1	/* number of core XLMI ports */
-
-/*  Instruction ROM 0:  */
-#define XCHAL_INSTROM0_VADDR		0x40800000	/* virtual address */
-#define XCHAL_INSTROM0_PADDR		0x40800000	/* physical address */
-#define XCHAL_INSTROM0_SIZE		4194304	/* size in bytes */
-#define XCHAL_INSTROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-/*  Instruction RAM 0:  */
-#define XCHAL_INSTRAM0_VADDR		0x40000000	/* virtual address */
-#define XCHAL_INSTRAM0_PADDR		0x40000000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		4194304	/* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-/*  Instruction RAM 1:  */
-#define XCHAL_INSTRAM1_VADDR		0x40400000	/* virtual address */
-#define XCHAL_INSTRAM1_PADDR		0x40400000	/* physical address */
-#define XCHAL_INSTRAM1_SIZE		4194304	/* size in bytes */
-#define XCHAL_INSTRAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-/*  Data ROM 0:  */
-#define XCHAL_DATAROM0_VADDR		0x3F400000	/* virtual address */
-#define XCHAL_DATAROM0_PADDR		0x3F400000	/* physical address */
-#define XCHAL_DATAROM0_SIZE		4194304	/* size in bytes */
-#define XCHAL_DATAROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATAROM0_BANKS		1	/* number of banks */
-
-/*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0x3FF80000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0x3FF80000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		524288	/* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS		1	/* number of banks */
-
-/*  Data RAM 1:  */
-#define XCHAL_DATARAM1_VADDR		0x3F800000	/* virtual address */
-#define XCHAL_DATARAM1_PADDR		0x3F800000	/* physical address */
-#define XCHAL_DATARAM1_SIZE		4194304	/* size in bytes */
-#define XCHAL_DATARAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM1_BANKS		1	/* number of banks */
-
-/*  XLMI Port 0:  */
-#define XCHAL_XLMI0_VADDR		0x3FF00000	/* virtual address */
-#define XCHAL_XLMI0_PADDR		0x3FF00000	/* physical address */
-#define XCHAL_XLMI0_SIZE		524288	/* size in bytes */
-#define XCHAL_XLMI0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
-			INTERRUPTS and TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		32	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		26	/* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
-						   (not including level zero) */
-#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x000637FF
-#define XCHAL_INTLEVEL2_MASK		0x00380000
-#define XCHAL_INTLEVEL3_MASK		0x28C08800
-#define XCHAL_INTLEVEL4_MASK		0x53000000
-#define XCHAL_INTLEVEL5_MASK		0x84010000
-#define XCHAL_INTLEVEL6_MASK		0x00000000
-#define XCHAL_INTLEVEL7_MASK		0x00004000
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x000637FF
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x003E37FF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x28FEBFFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x7BFEBFFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0xFFFFBFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0xFFFFBFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0xFFFFFFFF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		1
-#define XCHAL_INT3_LEVEL		1
-#define XCHAL_INT4_LEVEL		1
-#define XCHAL_INT5_LEVEL		1
-#define XCHAL_INT6_LEVEL		1
-#define XCHAL_INT7_LEVEL		1
-#define XCHAL_INT8_LEVEL		1
-#define XCHAL_INT9_LEVEL		1
-#define XCHAL_INT10_LEVEL		1
-#define XCHAL_INT11_LEVEL		3
-#define XCHAL_INT12_LEVEL		1
-#define XCHAL_INT13_LEVEL		1
-#define XCHAL_INT14_LEVEL		7
-#define XCHAL_INT15_LEVEL		3
-#define XCHAL_INT16_LEVEL		5
-#define XCHAL_INT17_LEVEL		1
-#define XCHAL_INT18_LEVEL		1
-#define XCHAL_INT19_LEVEL		2
-#define XCHAL_INT20_LEVEL		2
-#define XCHAL_INT21_LEVEL		2
-#define XCHAL_INT22_LEVEL		3
-#define XCHAL_INT23_LEVEL		3
-#define XCHAL_INT24_LEVEL		4
-#define XCHAL_INT25_LEVEL		4
-#define XCHAL_INT26_LEVEL		5
-#define XCHAL_INT27_LEVEL		3
-#define XCHAL_INT28_LEVEL		4
-#define XCHAL_INT29_LEVEL		3
-#define XCHAL_INT30_LEVEL		4
-#define XCHAL_INT31_LEVEL		5
-#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
-						   EXCSAVE/EPS/EPC_n, RFI n) */
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_PROFILING
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT25_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT26_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT27_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT28_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT29_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT30_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT31_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0x00000000
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x20000080
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x50400400
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x8FBE333F
-#define XCHAL_INTTYPE_MASK_TIMER	0x00018040
-#define XCHAL_INTTYPE_MASK_NMI		0x00004000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING	0x00000800
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		15	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		16	/* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
-#define XCHAL_PROFILING_INTERRUPT	11	/* profiling interrupt */
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL7_NUM		14
-/*  (There are many interrupts each at level(s) 1, 2, 3, 4, 5.)  */
-
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM		8	/* (intlevel 1) */
-#define XCHAL_EXTINT7_NUM		9	/* (intlevel 1) */
-#define XCHAL_EXTINT8_NUM		10	/* (intlevel 1) */
-#define XCHAL_EXTINT9_NUM		12	/* (intlevel 1) */
-#define XCHAL_EXTINT10_NUM		13	/* (intlevel 1) */
-#define XCHAL_EXTINT11_NUM		14	/* (intlevel 7) */
-#define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
-#define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
-#define XCHAL_EXTINT14_NUM		19	/* (intlevel 2) */
-#define XCHAL_EXTINT15_NUM		20	/* (intlevel 2) */
-#define XCHAL_EXTINT16_NUM		21	/* (intlevel 2) */
-#define XCHAL_EXTINT17_NUM		22	/* (intlevel 3) */
-#define XCHAL_EXTINT18_NUM		23	/* (intlevel 3) */
-#define XCHAL_EXTINT19_NUM		24	/* (intlevel 4) */
-#define XCHAL_EXTINT20_NUM		25	/* (intlevel 4) */
-#define XCHAL_EXTINT21_NUM		26	/* (intlevel 5) */
-#define XCHAL_EXTINT22_NUM		27	/* (intlevel 3) */
-#define XCHAL_EXTINT23_NUM		28	/* (intlevel 4) */
-#define XCHAL_EXTINT24_NUM		30	/* (intlevel 4) */
-#define XCHAL_EXTINT25_NUM		31	/* (intlevel 5) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM		6	/* (intlevel 1) */
-#define XCHAL_INT9_EXTNUM		7	/* (intlevel 1) */
-#define XCHAL_INT10_EXTNUM		8	/* (intlevel 1) */
-#define XCHAL_INT12_EXTNUM		9	/* (intlevel 1) */
-#define XCHAL_INT13_EXTNUM		10	/* (intlevel 1) */
-#define XCHAL_INT14_EXTNUM		11	/* (intlevel 7) */
-#define XCHAL_INT17_EXTNUM		12	/* (intlevel 1) */
-#define XCHAL_INT18_EXTNUM		13	/* (intlevel 1) */
-#define XCHAL_INT19_EXTNUM		14	/* (intlevel 2) */
-#define XCHAL_INT20_EXTNUM		15	/* (intlevel 2) */
-#define XCHAL_INT21_EXTNUM		16	/* (intlevel 2) */
-#define XCHAL_INT22_EXTNUM		17	/* (intlevel 3) */
-#define XCHAL_INT23_EXTNUM		18	/* (intlevel 3) */
-#define XCHAL_INT24_EXTNUM		19	/* (intlevel 4) */
-#define XCHAL_INT25_EXTNUM		20	/* (intlevel 4) */
-#define XCHAL_INT26_EXTNUM		21	/* (intlevel 5) */
-#define XCHAL_INT27_EXTNUM		22	/* (intlevel 3) */
-#define XCHAL_INT28_EXTNUM		23	/* (intlevel 4) */
-#define XCHAL_INT30_EXTNUM		24	/* (intlevel 4) */
-#define XCHAL_INT31_EXTNUM		25	/* (intlevel 5) */
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
-						   number: 1 == XEA1 (old)
-							   2 == XEA2 (new)
-							   0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR	0x40000000  /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR	0x40000000
-#define XCHAL_RESET_VECBASE_OVERLAP	0
-
-#define XCHAL_RESET_VECTOR0_VADDR	0x50000000
-#define XCHAL_RESET_VECTOR0_PADDR	0x50000000
-#define XCHAL_RESET_VECTOR1_VADDR	0x40000400
-#define XCHAL_RESET_VECTOR1_PADDR	0x40000400
-#define XCHAL_RESET_VECTOR_VADDR	0x40000400
-#define XCHAL_RESET_VECTOR_PADDR	0x40000400
-#define XCHAL_USER_VECOFS		0x00000340
-#define XCHAL_USER_VECTOR_VADDR		0x40000340
-#define XCHAL_USER_VECTOR_PADDR		0x40000340
-#define XCHAL_KERNEL_VECOFS		0x00000300
-#define XCHAL_KERNEL_VECTOR_VADDR	0x40000300
-#define XCHAL_KERNEL_VECTOR_PADDR	0x40000300
-#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x400003C0
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x400003C0
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x40000000
-#define XCHAL_WINDOW_VECTORS_PADDR	0x40000000
-#define XCHAL_INTLEVEL2_VECOFS		0x00000180
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x40000180
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x40000180
-#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x400001C0
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x400001C0
-#define XCHAL_INTLEVEL4_VECOFS		0x00000200
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x40000200
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x40000200
-#define XCHAL_INTLEVEL5_VECOFS		0x00000240
-#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x40000240
-#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x40000240
-#define XCHAL_INTLEVEL6_VECOFS		0x00000280
-#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x40000280
-#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x40000280
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS		0x000002C0
-#define XCHAL_NMI_VECTOR_VADDR		0x400002C0
-#define XCHAL_NMI_VECTOR_PADDR		0x400002C0
-#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
-				DEBUG MODULE
-  ----------------------------------------------------------------------*/
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		16384	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		2	/* performance counters */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See core-matmap.h header file for more details.  */
-
-#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
-						   [autorefill] and protection)
-						   usable for an MMU-based OS */
-/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/tools/sdk/include/esp32/xtensa/config/core-matmap.h b/tools/sdk/include/esp32/xtensa/config/core-matmap.h
deleted file mode 100644
index b101f1e6aa8..00000000000
--- a/tools/sdk/include/esp32/xtensa/config/core-matmap.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/* 
- * xtensa/config/core-matmap.h -- Memory access and translation mapping
- *	parameters (CHAL) of the Xtensa processor core configuration.
- *
- *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
- *  this file) for more details.
- *
- *  In the Xtensa processor products released to date, all parameters
- *  defined in this file are derivable (at least in theory) from
- *  information contained in the core-isa.h header file.
- *  In particular, the following core configuration parameters are relevant:
- *	XCHAL_HAVE_CACHEATTR
- *	XCHAL_HAVE_MIMIC_CACHEATTR
- *	XCHAL_HAVE_XLT_CACHEATTR
- *	XCHAL_HAVE_PTP_MMU
- *	XCHAL_ITLB_ARF_ENTRIES_LOG2
- *	XCHAL_DTLB_ARF_ENTRIES_LOG2
- *	XCHAL_DCACHE_IS_WRITEBACK
- *	XCHAL_ICACHE_SIZE		(presence of I-cache)
- *	XCHAL_DCACHE_SIZE		(presence of D-cache)
- *	XCHAL_HW_VERSION_MAJOR
- *	XCHAL_HW_VERSION_MINOR
- */
-
-/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_CORE_MATMAP_H
-#define XTENSA_CONFIG_CORE_MATMAP_H
-
-
-/*----------------------------------------------------------------------
-			CACHE (MEMORY ACCESS) ATTRIBUTES
-  ----------------------------------------------------------------------*/
-
-
-/*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
-#define XCHAL_FCA_LIST		XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_BYPASS	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_FAM_EXCEPTION
-#define XCHAL_LCA_LIST		XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_LAM_BYPASSG	XCHAL_SEP \
-				XTHAL_LAM_EXCEPTION
-#define XCHAL_SCA_LIST		XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
-				XTHAL_SAM_BYPASS	XCHAL_SEP \
-				XTHAL_SAM_EXCEPTION
-
-
-/*
- *  Specific encoded cache attribute values of general interest.
- *  If a specific cache mode is not available, the closest available
- *  one is returned instead (eg. writethru instead of writeback,
- *  bypass instead of writethru).
- */
-#define XCHAL_CA_BYPASS  		2	/* cache disabled (bypassed) mode */
-#define XCHAL_CA_BYPASSBUF  		6	/* cache disabled (bypassed) bufferable mode */
-#define XCHAL_CA_WRITETHRU		2	/* cache enabled (write-through) mode */
-#define XCHAL_CA_WRITEBACK		2	/* cache enabled (write-back) mode */
-#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC	0	/* write-back no-allocate availability */
-#define XCHAL_CA_WRITEBACK_NOALLOC	2	/* cache enabled (write-back no-allocate) mode */
-#define XCHAL_CA_BYPASS_RW  		0	/* cache disabled (bypassed) mode (no exec) */
-#define XCHAL_CA_WRITETHRU_RW		0	/* cache enabled (write-through) mode (no exec) */
-#define XCHAL_CA_WRITEBACK_RW		0	/* cache enabled (write-back) mode (no exec) */
-#define XCHAL_CA_WRITEBACK_NOALLOC_RW	0	/* cache enabled (write-back no-allocate) mode (no exec) */
-#define XCHAL_CA_ILLEGAL		15	/* no access allowed (all cause exceptions) mode */
-#define XCHAL_CA_ISOLATE		0	/* cache isolate (accesses go to cache not memory) mode */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*
- *  General notes on MMU parameters.
- *
- *  Terminology:
- *	ASID = address-space ID (acts as an "extension" of virtual addresses)
- *	VPN  = virtual page number
- *	PPN  = physical page number
- *	CA   = encoded cache attribute (access modes)
- *	TLB  = translation look-aside buffer (term is stretched somewhat here)
- *	I    = instruction (fetch accesses)
- *	D    = data (load and store accesses)
- *	way  = each TLB (ITLB and DTLB) consists of a number of "ways"
- *		that simultaneously match the virtual address of an access;
- *		a TLB successfully translates a virtual address if exactly
- *		one way matches the vaddr; if none match, it is a miss;
- *		if multiple match, one gets a "multihit" exception;
- *		each way can be independently configured in terms of number of
- *		entries, page sizes, which fields are writable or constant, etc.
- *	set  = group of contiguous ways with exactly identical parameters
- *	ARF  = auto-refill; hardware services a 1st-level miss by loading a PTE
- *		from the page table and storing it in one of the auto-refill ways;
- *		if this PTE load also misses, a miss exception is posted for s/w.
- *	min-wired = a "min-wired" way can be used to map a single (minimum-sized)
- * 		page arbitrarily under program control; it has a single entry,
- *		is non-auto-refill (some other way(s) must be auto-refill),
- *		all its fields (VPN, PPN, ASID, CA) are all writable, and it
- *		supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
- *		restriction is that this be the only page size it supports).
- *
- *  TLB way entries are virtually indexed.
- *  TLB ways that support multiple page sizes:
- *	- must have all writable VPN and PPN fields;
- *	- can only use one page size at any given time (eg. setup at startup),
- *	  selected by the respective ITLBCFG or DTLBCFG special register,
- *	  whose bits n*4+3 .. n*4 index the list of page sizes for way n
- *	  (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
- *	  this list may be sparse for auto-refill ways because auto-refill
- *	  ways have independent lists of supported page sizes sharing a
- *	  common encoding with PTE entries; the encoding is the index into
- *	  this list; unsupported sizes for a given way are zero in the list;
- *	  selecting unsupported sizes results in undefined hardware behaviour;
- *	- is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
- */
-
-#define XCHAL_MMU_ASID_INVALID		0	/* ASID value indicating invalid address space */
-#define XCHAL_MMU_ASID_KERNEL		0	/* ASID value indicating kernel (ring 0) address space */
-#define XCHAL_MMU_SR_BITS		0	/* number of size-restriction bits supported */
-#define XCHAL_MMU_CA_BITS		4	/* number of bits needed to hold cache attribute encoding */
-#define XCHAL_MMU_MAX_PTE_PAGE_SIZE	29	/* max page size in a PTE structure (log2) */
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE	29	/* min page size in a PTE structure (log2) */
-
-
-/***  Instruction TLB:  ***/
-
-#define XCHAL_ITLB_WAY_BITS		0	/* number of bits holding the ways */
-#define XCHAL_ITLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
-#define XCHAL_ITLB_ARF_WAYS		0	/* number of auto-refill ways */
-#define XCHAL_ITLB_SETS			1	/* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_ITLB_WAY0_SET		0
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_ITLB_ARF_SETS		0	/* number of auto-refill sets */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_ITLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
-
-
-/*  ITLB way set 0 (group of ways 0 thru 0):  */
-#define XCHAL_ITLB_SET0_WAY			0	/* index of first way in this way set */
-#define XCHAL_ITLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
-#define XCHAL_ITLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
-#define XCHAL_ITLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
-#define XCHAL_ITLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_ITLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
-#define XCHAL_ITLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
-#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
-							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_ITLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
-#define XCHAL_ITLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_ITLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_VPN_CONST		0x00000000
-#define XCHAL_ITLB_SET0_E1_VPN_CONST		0x20000000
-#define XCHAL_ITLB_SET0_E2_VPN_CONST		0x40000000
-#define XCHAL_ITLB_SET0_E3_VPN_CONST		0x60000000
-#define XCHAL_ITLB_SET0_E4_VPN_CONST		0x80000000
-#define XCHAL_ITLB_SET0_E5_VPN_CONST		0xA0000000
-#define XCHAL_ITLB_SET0_E6_VPN_CONST		0xC0000000
-#define XCHAL_ITLB_SET0_E7_VPN_CONST		0xE0000000
-/*  Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_PPN_CONST		0x00000000
-#define XCHAL_ITLB_SET0_E1_PPN_CONST		0x20000000
-#define XCHAL_ITLB_SET0_E2_PPN_CONST		0x40000000
-#define XCHAL_ITLB_SET0_E3_PPN_CONST		0x60000000
-#define XCHAL_ITLB_SET0_E4_PPN_CONST		0x80000000
-#define XCHAL_ITLB_SET0_E5_PPN_CONST		0xA0000000
-#define XCHAL_ITLB_SET0_E6_PPN_CONST		0xC0000000
-#define XCHAL_ITLB_SET0_E7_PPN_CONST		0xE0000000
-/*  Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero):  */
-#define XCHAL_ITLB_SET0_E0_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E1_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E2_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E3_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E4_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E5_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E6_CA_RESET		0x02
-#define XCHAL_ITLB_SET0_E7_CA_RESET		0x02
-
-
-/***  Data TLB:  ***/
-
-#define XCHAL_DTLB_WAY_BITS		0	/* number of bits holding the ways */
-#define XCHAL_DTLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
-#define XCHAL_DTLB_ARF_WAYS		0	/* number of auto-refill ways */
-#define XCHAL_DTLB_SETS			1	/* number of sets (groups of ways with identical settings) */
-
-/*  Way set to which each way belongs:  */
-#define XCHAL_DTLB_WAY0_SET		0
-
-/*  Ways sets that are used by hardware auto-refill (ARF):  */
-#define XCHAL_DTLB_ARF_SETS		0	/* number of auto-refill sets */
-
-/*  Way sets that are "min-wired" (see terminology comment above):  */
-#define XCHAL_DTLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
-
-
-/*  DTLB way set 0 (group of ways 0 thru 0):  */
-#define XCHAL_DTLB_SET0_WAY			0	/* index of first way in this way set */
-#define XCHAL_DTLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
-#define XCHAL_DTLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
-#define XCHAL_DTLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
-#define XCHAL_DTLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
-#define XCHAL_DTLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
-#define XCHAL_DTLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
-#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
-							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
-#define XCHAL_DTLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
-#define XCHAL_DTLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
-#define XCHAL_DTLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
-/*  Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_VPN_CONST		0x00000000
-#define XCHAL_DTLB_SET0_E1_VPN_CONST		0x20000000
-#define XCHAL_DTLB_SET0_E2_VPN_CONST		0x40000000
-#define XCHAL_DTLB_SET0_E3_VPN_CONST		0x60000000
-#define XCHAL_DTLB_SET0_E4_VPN_CONST		0x80000000
-#define XCHAL_DTLB_SET0_E5_VPN_CONST		0xA0000000
-#define XCHAL_DTLB_SET0_E6_VPN_CONST		0xC0000000
-#define XCHAL_DTLB_SET0_E7_VPN_CONST		0xE0000000
-/*  Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_PPN_CONST		0x00000000
-#define XCHAL_DTLB_SET0_E1_PPN_CONST		0x20000000
-#define XCHAL_DTLB_SET0_E2_PPN_CONST		0x40000000
-#define XCHAL_DTLB_SET0_E3_PPN_CONST		0x60000000
-#define XCHAL_DTLB_SET0_E4_PPN_CONST		0x80000000
-#define XCHAL_DTLB_SET0_E5_PPN_CONST		0xA0000000
-#define XCHAL_DTLB_SET0_E6_PPN_CONST		0xC0000000
-#define XCHAL_DTLB_SET0_E7_PPN_CONST		0xE0000000
-/*  Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero):  */
-#define XCHAL_DTLB_SET0_E0_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E1_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E2_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E3_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E4_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E5_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E6_CA_RESET		0x02
-#define XCHAL_DTLB_SET0_E7_CA_RESET		0x02
-
-
-
-
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/config/core.h b/tools/sdk/include/esp32/xtensa/config/core.h
deleted file mode 100644
index 0204757b055..00000000000
--- a/tools/sdk/include/esp32/xtensa/config/core.h
+++ /dev/null
@@ -1,1416 +0,0 @@
-/* 
- * xtensa/config/core.h -- HAL definitions dependent on CORE configuration
- *
- *  This header file is sometimes referred to as the "compile-time HAL" or CHAL.
- *  It pulls definitions tailored for a specific Xtensa processor configuration.
- *
- *  Sources for binaries meant to be configuration-independent generally avoid
- *  including this file (they may use the configuration-specific HAL library).
- *  It is normal for the HAL library source itself to include this file.
- */
-
-/*
- * Copyright (c) 2005-2014 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef XTENSA_CONFIG_CORE_H
-#define XTENSA_CONFIG_CORE_H
-
-/*  CONFIGURATION INDEPENDENT DEFINITIONS:  */
-#ifdef __XTENSA__
-#include <xtensa/hal.h>
-#include <xtensa/xtensa-versions.h>
-#else
-#include "../hal.h"
-#include "../xtensa-versions.h"
-#endif
-
-/*  CONFIGURATION SPECIFIC DEFINITIONS:  */
-#ifdef __XTENSA__
-#include <xtensa/config/core-isa.h>
-#include <xtensa/config/core-matmap.h>
-#include <xtensa/config/tie.h>
-#else
-#include "core-isa.h"
-#include "core-matmap.h"
-#include "tie.h"
-#endif
-
-#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
-#ifdef __XTENSA__
-#include <xtensa/config/tie-asm.h>
-#else
-#include "tie-asm.h"
-#endif
-#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
-
-
-/*----------------------------------------------------------------------
-				GENERAL
-  ----------------------------------------------------------------------*/
-
-/*
- *  Separators for macros that expand into arrays.
- *  These can be predefined by files that #include this one,
- *  when different separators are required.
- */
-/*  Element separator for macros that expand into 1-dimensional arrays:  */
-#ifndef XCHAL_SEP
-#define XCHAL_SEP			,
-#endif
-/*  Array separator for macros that expand into 2-dimensional arrays:  */
-#ifndef XCHAL_SEP2
-#define XCHAL_SEP2			},{
-#endif
-
-
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------*/
-
-#if XCHAL_HAVE_BE
-# define XCHAL_HAVE_LE			0
-# define XCHAL_MEMORY_ORDER		XTHAL_BIGENDIAN
-#else
-# define XCHAL_HAVE_LE			1
-# define XCHAL_MEMORY_ORDER		XTHAL_LITTLEENDIAN
-#endif
-
-
-
-/*----------------------------------------------------------------------
-				INTERRUPTS
-  ----------------------------------------------------------------------*/
-
-/*  Indexing macros:  */
-#define _XCHAL_INTLEVEL_MASK(n)		XCHAL_INTLEVEL ## n ## _MASK
-#define XCHAL_INTLEVEL_MASK(n)		_XCHAL_INTLEVEL_MASK(n)		/* n = 0 .. 15 */
-#define _XCHAL_INTLEVEL_ANDBELOWMASK(n)	XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
-#define XCHAL_INTLEVEL_ANDBELOW_MASK(n)	_XCHAL_INTLEVEL_ANDBELOWMASK(n)	/* n = 0 .. 15 */
-#define _XCHAL_INTLEVEL_NUM(n)		XCHAL_INTLEVEL ## n ## _NUM
-#define XCHAL_INTLEVEL_NUM(n)		_XCHAL_INTLEVEL_NUM(n)		/* n = 0 .. 15 */
-#define _XCHAL_INT_LEVEL(n)		XCHAL_INT ## n ## _LEVEL
-#define XCHAL_INT_LEVEL(n)		_XCHAL_INT_LEVEL(n)		/* n = 0 .. 31 */
-#define _XCHAL_INT_TYPE(n)		XCHAL_INT ## n ## _TYPE
-#define XCHAL_INT_TYPE(n)		_XCHAL_INT_TYPE(n)		/* n = 0 .. 31 */
-#define _XCHAL_TIMER_INTERRUPT(n)	XCHAL_TIMER ## n ## _INTERRUPT
-#define XCHAL_TIMER_INTERRUPT(n)	_XCHAL_TIMER_INTERRUPT(n)	/* n = 0 .. 3 */
-
-
-#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS	XCHAL_HAVE_HIGHPRI_INTERRUPTS
-#define XCHAL_NUM_LOWPRI_LEVELS		1			/* number of low-priority interrupt levels (always 1) */
-#define XCHAL_FIRST_HIGHPRI_LEVEL	(XCHAL_NUM_LOWPRI_LEVELS+1)	/* level of first high-priority interrupt (always 2) */
-/*  Note:  1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15  */
-
-/*  These values are constant for existing Xtensa processor implementations:  */
-#define XCHAL_INTLEVEL0_MASK		0x00000000
-#define XCHAL_INTLEVEL8_MASK		0x00000000
-#define XCHAL_INTLEVEL9_MASK		0x00000000
-#define XCHAL_INTLEVEL10_MASK		0x00000000
-#define XCHAL_INTLEVEL11_MASK		0x00000000
-#define XCHAL_INTLEVEL12_MASK		0x00000000
-#define XCHAL_INTLEVEL13_MASK		0x00000000
-#define XCHAL_INTLEVEL14_MASK		0x00000000
-#define XCHAL_INTLEVEL15_MASK		0x00000000
-
-/*  Array of masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL_MASKS		XCHAL_INTLEVEL0_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL1_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL2_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL3_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL4_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL5_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL6_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL7_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL8_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL9_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL10_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL11_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL12_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL13_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL14_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL15_MASK
-
-/*  These values are constant for existing Xtensa processor implementations:  */
-#define XCHAL_INTLEVEL0_ANDBELOW_MASK	0x00000000
-#define XCHAL_INTLEVEL8_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL9_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL10_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL11_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL12_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL13_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL14_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
-#define XCHAL_INTLEVEL15_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
-
-/*  Mask of all low-priority interrupts:  */
-#define XCHAL_LOWPRI_MASK		XCHAL_INTLEVEL1_ANDBELOW_MASK
-
-/*  Mask of all interrupts masked by PS.EXCM (or CEXCM):  */
-#define XCHAL_EXCM_MASK			XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL)
-
-/*  Array of masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL_ANDBELOW_MASKS	XCHAL_INTLEVEL0_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL1_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL2_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL3_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL4_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL5_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL6_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL7_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL8_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL9_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL10_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL11_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL12_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL13_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL14_ANDBELOW_MASK \
-			XCHAL_SEP	XCHAL_INTLEVEL15_ANDBELOW_MASK
-
-#if 0 /*XCHAL_HAVE_NMI*/
-/*  NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n):  */
-# define XCHAL_NMILEVEL		(XCHAL_NUM_INTLEVELS+1)
-#endif
-
-/*  Array of levels of each possible interrupt:  */
-#define XCHAL_INT_LEVELS		XCHAL_INT0_LEVEL \
-			XCHAL_SEP	XCHAL_INT1_LEVEL \
-			XCHAL_SEP	XCHAL_INT2_LEVEL \
-			XCHAL_SEP	XCHAL_INT3_LEVEL \
-			XCHAL_SEP	XCHAL_INT4_LEVEL \
-			XCHAL_SEP	XCHAL_INT5_LEVEL \
-			XCHAL_SEP	XCHAL_INT6_LEVEL \
-			XCHAL_SEP	XCHAL_INT7_LEVEL \
-			XCHAL_SEP	XCHAL_INT8_LEVEL \
-			XCHAL_SEP	XCHAL_INT9_LEVEL \
-			XCHAL_SEP	XCHAL_INT10_LEVEL \
-			XCHAL_SEP	XCHAL_INT11_LEVEL \
-			XCHAL_SEP	XCHAL_INT12_LEVEL \
-			XCHAL_SEP	XCHAL_INT13_LEVEL \
-			XCHAL_SEP	XCHAL_INT14_LEVEL \
-			XCHAL_SEP	XCHAL_INT15_LEVEL \
-			XCHAL_SEP	XCHAL_INT16_LEVEL \
-			XCHAL_SEP	XCHAL_INT17_LEVEL \
-			XCHAL_SEP	XCHAL_INT18_LEVEL \
-			XCHAL_SEP	XCHAL_INT19_LEVEL \
-			XCHAL_SEP	XCHAL_INT20_LEVEL \
-			XCHAL_SEP	XCHAL_INT21_LEVEL \
-			XCHAL_SEP	XCHAL_INT22_LEVEL \
-			XCHAL_SEP	XCHAL_INT23_LEVEL \
-			XCHAL_SEP	XCHAL_INT24_LEVEL \
-			XCHAL_SEP	XCHAL_INT25_LEVEL \
-			XCHAL_SEP	XCHAL_INT26_LEVEL \
-			XCHAL_SEP	XCHAL_INT27_LEVEL \
-			XCHAL_SEP	XCHAL_INT28_LEVEL \
-			XCHAL_SEP	XCHAL_INT29_LEVEL \
-			XCHAL_SEP	XCHAL_INT30_LEVEL \
-			XCHAL_SEP	XCHAL_INT31_LEVEL
-
-/*  Array of types of each possible interrupt:  */
-#define XCHAL_INT_TYPES			XCHAL_INT0_TYPE \
-			XCHAL_SEP	XCHAL_INT1_TYPE \
-			XCHAL_SEP	XCHAL_INT2_TYPE \
-			XCHAL_SEP	XCHAL_INT3_TYPE \
-			XCHAL_SEP	XCHAL_INT4_TYPE \
-			XCHAL_SEP	XCHAL_INT5_TYPE \
-			XCHAL_SEP	XCHAL_INT6_TYPE \
-			XCHAL_SEP	XCHAL_INT7_TYPE \
-			XCHAL_SEP	XCHAL_INT8_TYPE \
-			XCHAL_SEP	XCHAL_INT9_TYPE \
-			XCHAL_SEP	XCHAL_INT10_TYPE \
-			XCHAL_SEP	XCHAL_INT11_TYPE \
-			XCHAL_SEP	XCHAL_INT12_TYPE \
-			XCHAL_SEP	XCHAL_INT13_TYPE \
-			XCHAL_SEP	XCHAL_INT14_TYPE \
-			XCHAL_SEP	XCHAL_INT15_TYPE \
-			XCHAL_SEP	XCHAL_INT16_TYPE \
-			XCHAL_SEP	XCHAL_INT17_TYPE \
-			XCHAL_SEP	XCHAL_INT18_TYPE \
-			XCHAL_SEP	XCHAL_INT19_TYPE \
-			XCHAL_SEP	XCHAL_INT20_TYPE \
-			XCHAL_SEP	XCHAL_INT21_TYPE \
-			XCHAL_SEP	XCHAL_INT22_TYPE \
-			XCHAL_SEP	XCHAL_INT23_TYPE \
-			XCHAL_SEP	XCHAL_INT24_TYPE \
-			XCHAL_SEP	XCHAL_INT25_TYPE \
-			XCHAL_SEP	XCHAL_INT26_TYPE \
-			XCHAL_SEP	XCHAL_INT27_TYPE \
-			XCHAL_SEP	XCHAL_INT28_TYPE \
-			XCHAL_SEP	XCHAL_INT29_TYPE \
-			XCHAL_SEP	XCHAL_INT30_TYPE \
-			XCHAL_SEP	XCHAL_INT31_TYPE
-
-/*  Array of masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASKS		XCHAL_INTTYPE_MASK_UNCONFIGURED	\
-			XCHAL_SEP	XCHAL_INTTYPE_MASK_SOFTWARE	\
-			XCHAL_SEP	XCHAL_INTTYPE_MASK_EXTERN_EDGE	\
-			XCHAL_SEP	XCHAL_INTTYPE_MASK_EXTERN_LEVEL	\
-			XCHAL_SEP	XCHAL_INTTYPE_MASK_TIMER	\
-			XCHAL_SEP	XCHAL_INTTYPE_MASK_NMI		\
-			XCHAL_SEP	XCHAL_INTTYPE_MASK_WRITE_ERROR
-
-/*  Interrupts that can be cleared using the INTCLEAR special register:  */
-#define XCHAL_INTCLEARABLE_MASK	(XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR)
-/*  Interrupts that can be triggered using the INTSET special register:  */
-#define XCHAL_INTSETTABLE_MASK	XCHAL_INTTYPE_MASK_SOFTWARE
-
-/*  Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3):  */
-#define XCHAL_TIMER_INTERRUPTS		XCHAL_TIMER0_INTERRUPT \
-			XCHAL_SEP	XCHAL_TIMER1_INTERRUPT \
-			XCHAL_SEP	XCHAL_TIMER2_INTERRUPT \
-			XCHAL_SEP	XCHAL_TIMER3_INTERRUPT
-
-
-
-/*  For backward compatibility and for the array macros, define macros for
- *  each unconfigured interrupt number (unfortunately, the value of
- *  XTHAL_INTTYPE_UNCONFIGURED is not zero):  */
-#if XCHAL_NUM_INTERRUPTS == 0
-# define XCHAL_INT0_LEVEL		0
-# define XCHAL_INT0_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 1
-# define XCHAL_INT1_LEVEL		0
-# define XCHAL_INT1_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 2
-# define XCHAL_INT2_LEVEL		0
-# define XCHAL_INT2_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 3
-# define XCHAL_INT3_LEVEL		0
-# define XCHAL_INT3_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 4
-# define XCHAL_INT4_LEVEL		0
-# define XCHAL_INT4_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 5
-# define XCHAL_INT5_LEVEL		0
-# define XCHAL_INT5_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 6
-# define XCHAL_INT6_LEVEL		0
-# define XCHAL_INT6_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 7
-# define XCHAL_INT7_LEVEL		0
-# define XCHAL_INT7_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 8
-# define XCHAL_INT8_LEVEL		0
-# define XCHAL_INT8_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 9
-# define XCHAL_INT9_LEVEL		0
-# define XCHAL_INT9_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 10
-# define XCHAL_INT10_LEVEL		0
-# define XCHAL_INT10_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 11
-# define XCHAL_INT11_LEVEL		0
-# define XCHAL_INT11_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 12
-# define XCHAL_INT12_LEVEL		0
-# define XCHAL_INT12_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 13
-# define XCHAL_INT13_LEVEL		0
-# define XCHAL_INT13_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 14
-# define XCHAL_INT14_LEVEL		0
-# define XCHAL_INT14_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 15
-# define XCHAL_INT15_LEVEL		0
-# define XCHAL_INT15_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 16
-# define XCHAL_INT16_LEVEL		0
-# define XCHAL_INT16_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 17
-# define XCHAL_INT17_LEVEL		0
-# define XCHAL_INT17_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 18
-# define XCHAL_INT18_LEVEL		0
-# define XCHAL_INT18_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 19
-# define XCHAL_INT19_LEVEL		0
-# define XCHAL_INT19_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 20
-# define XCHAL_INT20_LEVEL		0
-# define XCHAL_INT20_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 21
-# define XCHAL_INT21_LEVEL		0
-# define XCHAL_INT21_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 22
-# define XCHAL_INT22_LEVEL		0
-# define XCHAL_INT22_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 23
-# define XCHAL_INT23_LEVEL		0
-# define XCHAL_INT23_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 24
-# define XCHAL_INT24_LEVEL		0
-# define XCHAL_INT24_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 25
-# define XCHAL_INT25_LEVEL		0
-# define XCHAL_INT25_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 26
-# define XCHAL_INT26_LEVEL		0
-# define XCHAL_INT26_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 27
-# define XCHAL_INT27_LEVEL		0
-# define XCHAL_INT27_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 28
-# define XCHAL_INT28_LEVEL		0
-# define XCHAL_INT28_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 29
-# define XCHAL_INT29_LEVEL		0
-# define XCHAL_INT29_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 30
-# define XCHAL_INT30_LEVEL		0
-# define XCHAL_INT30_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-#if XCHAL_NUM_INTERRUPTS <= 31
-# define XCHAL_INT31_LEVEL		0
-# define XCHAL_INT31_TYPE		XTHAL_INTTYPE_UNCONFIGURED
-#endif
-
-
-/*
- *  Masks and levels corresponding to each *external* interrupt.
- */
-
-#define XCHAL_EXTINT0_MASK		(1 << XCHAL_EXTINT0_NUM)
-#define XCHAL_EXTINT0_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM)
-#define XCHAL_EXTINT1_MASK		(1 << XCHAL_EXTINT1_NUM)
-#define XCHAL_EXTINT1_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM)
-#define XCHAL_EXTINT2_MASK		(1 << XCHAL_EXTINT2_NUM)
-#define XCHAL_EXTINT2_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM)
-#define XCHAL_EXTINT3_MASK		(1 << XCHAL_EXTINT3_NUM)
-#define XCHAL_EXTINT3_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM)
-#define XCHAL_EXTINT4_MASK		(1 << XCHAL_EXTINT4_NUM)
-#define XCHAL_EXTINT4_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM)
-#define XCHAL_EXTINT5_MASK		(1 << XCHAL_EXTINT5_NUM)
-#define XCHAL_EXTINT5_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM)
-#define XCHAL_EXTINT6_MASK		(1 << XCHAL_EXTINT6_NUM)
-#define XCHAL_EXTINT6_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM)
-#define XCHAL_EXTINT7_MASK		(1 << XCHAL_EXTINT7_NUM)
-#define XCHAL_EXTINT7_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM)
-#define XCHAL_EXTINT8_MASK		(1 << XCHAL_EXTINT8_NUM)
-#define XCHAL_EXTINT8_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM)
-#define XCHAL_EXTINT9_MASK		(1 << XCHAL_EXTINT9_NUM)
-#define XCHAL_EXTINT9_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM)
-#define XCHAL_EXTINT10_MASK		(1 << XCHAL_EXTINT10_NUM)
-#define XCHAL_EXTINT10_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM)
-#define XCHAL_EXTINT11_MASK		(1 << XCHAL_EXTINT11_NUM)
-#define XCHAL_EXTINT11_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM)
-#define XCHAL_EXTINT12_MASK		(1 << XCHAL_EXTINT12_NUM)
-#define XCHAL_EXTINT12_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM)
-#define XCHAL_EXTINT13_MASK		(1 << XCHAL_EXTINT13_NUM)
-#define XCHAL_EXTINT13_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM)
-#define XCHAL_EXTINT14_MASK		(1 << XCHAL_EXTINT14_NUM)
-#define XCHAL_EXTINT14_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM)
-#define XCHAL_EXTINT15_MASK		(1 << XCHAL_EXTINT15_NUM)
-#define XCHAL_EXTINT15_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM)
-#define XCHAL_EXTINT16_MASK		(1 << XCHAL_EXTINT16_NUM)
-#define XCHAL_EXTINT16_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM)
-#define XCHAL_EXTINT17_MASK		(1 << XCHAL_EXTINT17_NUM)
-#define XCHAL_EXTINT17_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM)
-#define XCHAL_EXTINT18_MASK		(1 << XCHAL_EXTINT18_NUM)
-#define XCHAL_EXTINT18_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM)
-#define XCHAL_EXTINT19_MASK		(1 << XCHAL_EXTINT19_NUM)
-#define XCHAL_EXTINT19_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM)
-#define XCHAL_EXTINT20_MASK		(1 << XCHAL_EXTINT20_NUM)
-#define XCHAL_EXTINT20_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM)
-#define XCHAL_EXTINT21_MASK		(1 << XCHAL_EXTINT21_NUM)
-#define XCHAL_EXTINT21_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM)
-#define XCHAL_EXTINT22_MASK		(1 << XCHAL_EXTINT22_NUM)
-#define XCHAL_EXTINT22_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM)
-#define XCHAL_EXTINT23_MASK		(1 << XCHAL_EXTINT23_NUM)
-#define XCHAL_EXTINT23_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM)
-#define XCHAL_EXTINT24_MASK		(1 << XCHAL_EXTINT24_NUM)
-#define XCHAL_EXTINT24_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM)
-#define XCHAL_EXTINT25_MASK		(1 << XCHAL_EXTINT25_NUM)
-#define XCHAL_EXTINT25_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM)
-#define XCHAL_EXTINT26_MASK		(1 << XCHAL_EXTINT26_NUM)
-#define XCHAL_EXTINT26_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM)
-#define XCHAL_EXTINT27_MASK		(1 << XCHAL_EXTINT27_NUM)
-#define XCHAL_EXTINT27_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM)
-#define XCHAL_EXTINT28_MASK		(1 << XCHAL_EXTINT28_NUM)
-#define XCHAL_EXTINT28_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM)
-#define XCHAL_EXTINT29_MASK		(1 << XCHAL_EXTINT29_NUM)
-#define XCHAL_EXTINT29_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM)
-#define XCHAL_EXTINT30_MASK		(1 << XCHAL_EXTINT30_NUM)
-#define XCHAL_EXTINT30_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM)
-#define XCHAL_EXTINT31_MASK		(1 << XCHAL_EXTINT31_NUM)
-#define XCHAL_EXTINT31_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM)
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-/*  For backward compatibility ONLY -- DO NOT USE (will be removed in future release):  */
-#define XCHAL_HAVE_OLD_EXC_ARCH		XCHAL_HAVE_XEA1	/* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
-#define XCHAL_HAVE_EXCM			XCHAL_HAVE_XEA2	/* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
-#ifdef XCHAL_USER_VECTOR_VADDR
-#define XCHAL_PROGRAMEXC_VECTOR_VADDR	XCHAL_USER_VECTOR_VADDR
-#define XCHAL_USEREXC_VECTOR_VADDR	XCHAL_USER_VECTOR_VADDR
-#endif
-#ifdef XCHAL_USER_VECTOR_PADDR
-# define XCHAL_PROGRAMEXC_VECTOR_PADDR	XCHAL_USER_VECTOR_PADDR
-# define XCHAL_USEREXC_VECTOR_PADDR	XCHAL_USER_VECTOR_PADDR
-#endif
-#ifdef XCHAL_KERNEL_VECTOR_VADDR
-# define XCHAL_STACKEDEXC_VECTOR_VADDR	XCHAL_KERNEL_VECTOR_VADDR
-# define XCHAL_KERNELEXC_VECTOR_VADDR	XCHAL_KERNEL_VECTOR_VADDR
-#endif
-#ifdef XCHAL_KERNEL_VECTOR_PADDR
-# define XCHAL_STACKEDEXC_VECTOR_PADDR	XCHAL_KERNEL_VECTOR_PADDR
-# define XCHAL_KERNELEXC_VECTOR_PADDR	XCHAL_KERNEL_VECTOR_PADDR
-#endif
-
-#if 0
-#if XCHAL_HAVE_DEBUG
-# define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL)
-/*  This one should only get defined if the corresponding intlevel paddr macro exists:  */
-# define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL)
-#endif
-#endif
-
-/*  Indexing macros:  */
-#define _XCHAL_INTLEVEL_VECTOR_VADDR(n)		XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
-#define XCHAL_INTLEVEL_VECTOR_VADDR(n)		_XCHAL_INTLEVEL_VECTOR_VADDR(n)		/* n = 0 .. 15 */
-
-/*
- *  General Exception Causes
- *  (values of EXCCAUSE special register set by general exceptions,
- *   which vector to the user, kernel, or double-exception vectors).
- *
- *  DEPRECATED.  Please use the equivalent EXCCAUSE_xxx macros
- *  defined in <xtensa/corebits.h>.  (Note that these have slightly
- *  different names, they don't just have the XCHAL_ prefix removed.)
- */
-#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION		0	/* Illegal Instruction */
-#define XCHAL_EXCCAUSE_SYSTEM_CALL			1	/* System Call */
-#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR		2	/* Instruction Fetch Error */
-#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR			3	/* Load Store Error */
-#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT			4	/* Level 1 Interrupt */
-#define XCHAL_EXCCAUSE_ALLOCA				5	/* Stack Extension Assist */
-#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO		6	/* Integer Divide by Zero */
-#define XCHAL_EXCCAUSE_SPECULATION			7	/* Speculation */
-#define XCHAL_EXCCAUSE_PRIVILEGED			8	/* Privileged Instruction */
-#define XCHAL_EXCCAUSE_UNALIGNED			9	/* Unaligned Load Store */
-/*10..15 reserved*/
-#define XCHAL_EXCCAUSE_ITLB_MISS			16	/* ITlb Miss Exception */
-#define XCHAL_EXCCAUSE_ITLB_MULTIHIT			17	/* ITlb Mutltihit Exception */
-#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE			18	/* ITlb Privilege Exception */
-#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION		19	/* ITlb Size Restriction Exception */
-#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE		20	/* Fetch Cache Attribute Exception */
-/*21..23 reserved*/
-#define XCHAL_EXCCAUSE_DTLB_MISS			24	/* DTlb Miss Exception */
-#define XCHAL_EXCCAUSE_DTLB_MULTIHIT			25	/* DTlb Multihit Exception */
-#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE			26	/* DTlb Privilege Exception */
-#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION		27	/* DTlb Size Restriction Exception */
-#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE		28	/* Load Cache Attribute Exception */
-#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE		29	/* Store Cache Attribute Exception */
-/*30..31 reserved*/
-#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED		32	/* Coprocessor 0 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED		33	/* Coprocessor 1 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED		34	/* Coprocessor 2 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED		35	/* Coprocessor 3 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED		36	/* Coprocessor 4 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED		37	/* Coprocessor 5 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED		38	/* Coprocessor 6 disabled */
-#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED		39	/* Coprocessor 7 disabled */
-/*40..63 reserved*/
-
-
-/*
- *  Miscellaneous special register fields.
- *
- *  For each special register, and each field within each register:
- *	XCHAL_<regname>_VALIDMASK is the set of bits defined in the register.
- *	XCHAL_<regname>_<field>_BITS is the number of bits in the field.
- *	XCHAL_<regname>_<field>_NUM is 2^bits, the number of possible values
- *			of the field.
- *	XCHAL_<regname>_<field>_SHIFT is the position of the field within
- *			the register, starting from the least significant bit.
- *
- *  DEPRECATED.  Please use the equivalent macros defined in
- *  <xtensa/corebits.h>.  (Note that these have different names.)
- */
-
-/*  DBREAKC (special register number 160):  */
-#define XCHAL_DBREAKC_VALIDMASK		0xC000003F
-#define XCHAL_DBREAKC_MASK_BITS 	6
-#define XCHAL_DBREAKC_MASK_NUM  	64
-#define XCHAL_DBREAKC_MASK_SHIFT	0
-#define XCHAL_DBREAKC_MASK_MASK 	0x0000003F
-#define XCHAL_DBREAKC_LOADBREAK_BITS 	1
-#define XCHAL_DBREAKC_LOADBREAK_NUM  	2
-#define XCHAL_DBREAKC_LOADBREAK_SHIFT	30
-#define XCHAL_DBREAKC_LOADBREAK_MASK 	0x40000000
-#define XCHAL_DBREAKC_STOREBREAK_BITS 	1
-#define XCHAL_DBREAKC_STOREBREAK_NUM  	2
-#define XCHAL_DBREAKC_STOREBREAK_SHIFT	31
-#define XCHAL_DBREAKC_STOREBREAK_MASK 	0x80000000
-/*  PS (special register number 230):  */
-#define XCHAL_PS_VALIDMASK		0x00070F3F
-#define XCHAL_PS_INTLEVEL_BITS 		4
-#define XCHAL_PS_INTLEVEL_NUM  		16
-#define XCHAL_PS_INTLEVEL_SHIFT		0
-#define XCHAL_PS_INTLEVEL_MASK 		0x0000000F
-#define XCHAL_PS_EXCM_BITS 		1
-#define XCHAL_PS_EXCM_NUM  		2
-#define XCHAL_PS_EXCM_SHIFT		4
-#define XCHAL_PS_EXCM_MASK 		0x00000010
-#define XCHAL_PS_UM_BITS 		1
-#define XCHAL_PS_UM_NUM  		2
-#define XCHAL_PS_UM_SHIFT		5
-#define XCHAL_PS_UM_MASK 		0x00000020
-#define XCHAL_PS_RING_BITS 		2
-#define XCHAL_PS_RING_NUM  		4
-#define XCHAL_PS_RING_SHIFT		6
-#define XCHAL_PS_RING_MASK 		0x000000C0
-#define XCHAL_PS_OWB_BITS 		4
-#define XCHAL_PS_OWB_NUM  		16
-#define XCHAL_PS_OWB_SHIFT		8
-#define XCHAL_PS_OWB_MASK 		0x00000F00
-#define XCHAL_PS_CALLINC_BITS 		2
-#define XCHAL_PS_CALLINC_NUM  		4
-#define XCHAL_PS_CALLINC_SHIFT		16
-#define XCHAL_PS_CALLINC_MASK 		0x00030000
-#define XCHAL_PS_WOE_BITS 		1
-#define XCHAL_PS_WOE_NUM  		2
-#define XCHAL_PS_WOE_SHIFT		18
-#define XCHAL_PS_WOE_MASK 		0x00040000
-/*  EXCCAUSE (special register number 232):  */
-#define XCHAL_EXCCAUSE_VALIDMASK	0x0000003F
-#define XCHAL_EXCCAUSE_BITS 		6
-#define XCHAL_EXCCAUSE_NUM  		64
-#define XCHAL_EXCCAUSE_SHIFT		0
-#define XCHAL_EXCCAUSE_MASK 		0x0000003F
-/*  DEBUGCAUSE (special register number 233):  */
-#define XCHAL_DEBUGCAUSE_VALIDMASK	0x0000003F
-#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 	1
-#define XCHAL_DEBUGCAUSE_ICOUNT_NUM  	2
-#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT	0
-#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 	0x00000001
-#define XCHAL_DEBUGCAUSE_IBREAK_BITS 	1
-#define XCHAL_DEBUGCAUSE_IBREAK_NUM  	2
-#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT	1
-#define XCHAL_DEBUGCAUSE_IBREAK_MASK 	0x00000002
-#define XCHAL_DEBUGCAUSE_DBREAK_BITS 	1
-#define XCHAL_DEBUGCAUSE_DBREAK_NUM  	2
-#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT	2
-#define XCHAL_DEBUGCAUSE_DBREAK_MASK 	0x00000004
-#define XCHAL_DEBUGCAUSE_BREAK_BITS 	1
-#define XCHAL_DEBUGCAUSE_BREAK_NUM  	2
-#define XCHAL_DEBUGCAUSE_BREAK_SHIFT	3
-#define XCHAL_DEBUGCAUSE_BREAK_MASK 	0x00000008
-#define XCHAL_DEBUGCAUSE_BREAKN_BITS 	1
-#define XCHAL_DEBUGCAUSE_BREAKN_NUM  	2
-#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT	4
-#define XCHAL_DEBUGCAUSE_BREAKN_MASK 	0x00000010
-#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 	1
-#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM  	2
-#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT	5
-#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 	0x00000020
-
-
-
-
-/*----------------------------------------------------------------------
-				TIMERS
-  ----------------------------------------------------------------------*/
-
-/*#define XCHAL_HAVE_TIMERS		XCHAL_HAVE_CCOUNT*/
-
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-
-#define  XCHAL_NUM_IROM		XCHAL_NUM_INSTROM	/* (DEPRECATED) */
-#define  XCHAL_NUM_IRAM		XCHAL_NUM_INSTRAM	/* (DEPRECATED) */
-#define  XCHAL_NUM_DROM		XCHAL_NUM_DATAROM	/* (DEPRECATED) */
-#define  XCHAL_NUM_DRAM		XCHAL_NUM_DATARAM	/* (DEPRECATED) */
-
-#define XCHAL_IROM0_VADDR	XCHAL_INSTROM0_VADDR	/* (DEPRECATED) */
-#define XCHAL_IROM0_PADDR	XCHAL_INSTROM0_PADDR	/* (DEPRECATED) */
-#define XCHAL_IROM0_SIZE	XCHAL_INSTROM0_SIZE	/* (DEPRECATED) */
-#define XCHAL_IROM1_VADDR	XCHAL_INSTROM1_VADDR	/* (DEPRECATED) */
-#define XCHAL_IROM1_PADDR	XCHAL_INSTROM1_PADDR	/* (DEPRECATED) */
-#define XCHAL_IROM1_SIZE	XCHAL_INSTROM1_SIZE	/* (DEPRECATED) */
-#define XCHAL_IRAM0_VADDR	XCHAL_INSTRAM0_VADDR	/* (DEPRECATED) */
-#define XCHAL_IRAM0_PADDR	XCHAL_INSTRAM0_PADDR	/* (DEPRECATED) */
-#define XCHAL_IRAM0_SIZE	XCHAL_INSTRAM0_SIZE	/* (DEPRECATED) */
-#define XCHAL_IRAM1_VADDR	XCHAL_INSTRAM1_VADDR	/* (DEPRECATED) */
-#define XCHAL_IRAM1_PADDR	XCHAL_INSTRAM1_PADDR	/* (DEPRECATED) */
-#define XCHAL_IRAM1_SIZE	XCHAL_INSTRAM1_SIZE	/* (DEPRECATED) */
-#define XCHAL_DROM0_VADDR	XCHAL_DATAROM0_VADDR	/* (DEPRECATED) */
-#define XCHAL_DROM0_PADDR	XCHAL_DATAROM0_PADDR	/* (DEPRECATED) */
-#define XCHAL_DROM0_SIZE	XCHAL_DATAROM0_SIZE	/* (DEPRECATED) */
-#define XCHAL_DROM1_VADDR	XCHAL_DATAROM1_VADDR	/* (DEPRECATED) */
-#define XCHAL_DROM1_PADDR	XCHAL_DATAROM1_PADDR	/* (DEPRECATED) */
-#define XCHAL_DROM1_SIZE	XCHAL_DATAROM1_SIZE	/* (DEPRECATED) */
-#define XCHAL_DRAM0_VADDR	XCHAL_DATARAM0_VADDR	/* (DEPRECATED) */
-#define XCHAL_DRAM0_PADDR	XCHAL_DATARAM0_PADDR	/* (DEPRECATED) */
-#define XCHAL_DRAM0_SIZE	XCHAL_DATARAM0_SIZE	/* (DEPRECATED) */
-#define XCHAL_DRAM1_VADDR	XCHAL_DATARAM1_VADDR	/* (DEPRECATED) */
-#define XCHAL_DRAM1_PADDR	XCHAL_DATARAM1_PADDR	/* (DEPRECATED) */
-#define XCHAL_DRAM1_SIZE	XCHAL_DATARAM1_SIZE	/* (DEPRECATED) */
-
-
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-
-/*  Default PREFCTL value to enable prefetch.  */
-#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0
-#define XCHAL_CACHE_PREFCTL_DEFAULT	0x00044	/* enabled, not aggressive */
-#elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0
-#define XCHAL_CACHE_PREFCTL_DEFAULT	0x01044	/* + enable prefetch to L1 */
-#elif XCHAL_PREFETCH_ENTRIES >= 16
-#define XCHAL_CACHE_PREFCTL_DEFAULT	0x81044	/* 12 entries for block ops */
-#elif XCHAL_PREFETCH_ENTRIES >= 8
-#define XCHAL_CACHE_PREFCTL_DEFAULT	0x51044	/* 5 entries for block ops */
-#else
-#define XCHAL_CACHE_PREFCTL_DEFAULT	0x01044	/* 0 entries for block ops */
-#endif
-
-
-/*  Max for both I-cache and D-cache (used for general alignment):  */
-#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
-# define XCHAL_CACHE_LINEWIDTH_MAX	XCHAL_ICACHE_LINEWIDTH
-# define XCHAL_CACHE_LINESIZE_MAX	XCHAL_ICACHE_LINESIZE
-#else
-# define XCHAL_CACHE_LINEWIDTH_MAX	XCHAL_DCACHE_LINEWIDTH
-# define XCHAL_CACHE_LINESIZE_MAX	XCHAL_DCACHE_LINESIZE
-#endif
-
-#define XCHAL_ICACHE_SETSIZE		(1<<XCHAL_ICACHE_SETWIDTH)
-#define XCHAL_DCACHE_SETSIZE		(1<<XCHAL_DCACHE_SETWIDTH)
-/*  Max for both I and D caches (used for cache-coherency page alignment):  */
-#if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH
-# define XCHAL_CACHE_SETWIDTH_MAX	XCHAL_ICACHE_SETWIDTH
-# define XCHAL_CACHE_SETSIZE_MAX	XCHAL_ICACHE_SETSIZE
-#else
-# define XCHAL_CACHE_SETWIDTH_MAX	XCHAL_DCACHE_SETWIDTH
-# define XCHAL_CACHE_SETSIZE_MAX	XCHAL_DCACHE_SETSIZE
-#endif
-
-/*  Instruction cache tag bits:  */
-#define XCHAL_ICACHE_TAG_V_SHIFT	0
-#define XCHAL_ICACHE_TAG_V		0x1	/* valid bit */
-#if XCHAL_ICACHE_WAYS > 1
-# define XCHAL_ICACHE_TAG_F_SHIFT	1
-# define XCHAL_ICACHE_TAG_F		0x2	/* fill (LRU) bit */
-#else
-# define XCHAL_ICACHE_TAG_F_SHIFT	0
-# define XCHAL_ICACHE_TAG_F		0	/* no fill (LRU) bit */
-#endif
-#if XCHAL_ICACHE_LINE_LOCKABLE
-# define XCHAL_ICACHE_TAG_L_SHIFT	(XCHAL_ICACHE_TAG_F_SHIFT+1)
-# define XCHAL_ICACHE_TAG_L		(1 << XCHAL_ICACHE_TAG_L_SHIFT)	/* lock bit */
-#else
-# define XCHAL_ICACHE_TAG_L_SHIFT	XCHAL_ICACHE_TAG_F_SHIFT
-# define XCHAL_ICACHE_TAG_L		0	/* no lock bit */
-#endif
-/*  Data cache tag bits:  */
-#define XCHAL_DCACHE_TAG_V_SHIFT	0
-#define XCHAL_DCACHE_TAG_V		0x1	/* valid bit */
-#if XCHAL_DCACHE_WAYS > 1
-# define XCHAL_DCACHE_TAG_F_SHIFT	1
-# define XCHAL_DCACHE_TAG_F		0x2	/* fill (LRU) bit */
-#else
-# define XCHAL_DCACHE_TAG_F_SHIFT	0
-# define XCHAL_DCACHE_TAG_F		0	/* no fill (LRU) bit */
-#endif
-#if XCHAL_DCACHE_IS_WRITEBACK
-# define XCHAL_DCACHE_TAG_D_SHIFT	(XCHAL_DCACHE_TAG_F_SHIFT+1)
-# define XCHAL_DCACHE_TAG_D		(1 << XCHAL_DCACHE_TAG_D_SHIFT)	/* dirty bit */
-#else
-# define XCHAL_DCACHE_TAG_D_SHIFT	XCHAL_DCACHE_TAG_F_SHIFT
-# define XCHAL_DCACHE_TAG_D		0	/* no dirty bit */
-#endif
-#if XCHAL_DCACHE_LINE_LOCKABLE
-# define XCHAL_DCACHE_TAG_L_SHIFT	(XCHAL_DCACHE_TAG_D_SHIFT+1)
-# define XCHAL_DCACHE_TAG_L		(1 << XCHAL_DCACHE_TAG_L_SHIFT)	/* lock bit */
-#else
-# define XCHAL_DCACHE_TAG_L_SHIFT	XCHAL_DCACHE_TAG_D_SHIFT
-# define XCHAL_DCACHE_TAG_L		0	/* no lock bit */
-#endif
-
-/*  Whether MEMCTL register has anything useful  */
-#define XCHAL_USE_MEMCTL		(((XCHAL_LOOP_BUFFER_SIZE > 0)	||      \
-					XCHAL_DCACHE_IS_COHERENT	||      \
-					XCHAL_HAVE_ICACHE_DYN_WAYS	||      \
-					XCHAL_HAVE_DCACHE_DYN_WAYS)	&&      \
-					(XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
-
-/*  Default MEMCTL values:  */
-#if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS
-/* NOTE: constant defined this way to allow movi instead of l32r in reset code. */
-#define XCHAL_CACHE_MEMCTL_DEFAULT	0xFFFFFF00	/* Init all possible ways */
-#else
-#define XCHAL_CACHE_MEMCTL_DEFAULT	0x00000000	/* Nothing to do */
-#endif
-
-#if XCHAL_DCACHE_IS_COHERENT
-#define _MEMCTL_SNOOP_EN		0x02		/* Enable snoop */
-#else
-#define _MEMCTL_SNOOP_EN		0x00		/* Don't enable snoop */
-#endif
-
-#if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453
-#define _MEMCTL_L0IBUF_EN		0x00		/* No loop buffer or don't enable */
-#else
-#define _MEMCTL_L0IBUF_EN		0x01		/* Enable loop buffer */
-#endif
-
-#define XCHAL_SNOOP_LB_MEMCTL_DEFAULT	(_MEMCTL_SNOOP_EN | _MEMCTL_L0IBUF_EN)
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See <xtensa/config/core-matmap.h> for more details.  */
-
-/*  Has different semantic in open source headers (where it means HAVE_PTP_MMU),
-    so comment out starting with RB-2008.3 release; later, might get
-    get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead:  */
-/*#define XCHAL_HAVE_MMU		XCHAL_HAVE_TLBS*/	/* (DEPRECATED; use XCHAL_HAVE_TLBS instead) */
-
-/*  Indexing macros:  */
-#define _XCHAL_ITLB_SET(n,_what)	XCHAL_ITLB_SET ## n ## _what
-#define XCHAL_ITLB_SET(n,what)		_XCHAL_ITLB_SET(n, _ ## what )
-#define _XCHAL_ITLB_SET_E(n,i,_what)	XCHAL_ITLB_SET ## n ## _E ## i ## _what
-#define XCHAL_ITLB_SET_E(n,i,what)	_XCHAL_ITLB_SET_E(n,i, _ ## what )
-#define _XCHAL_DTLB_SET(n,_what)	XCHAL_DTLB_SET ## n ## _what
-#define XCHAL_DTLB_SET(n,what)		_XCHAL_DTLB_SET(n, _ ## what )
-#define _XCHAL_DTLB_SET_E(n,i,_what)	XCHAL_DTLB_SET ## n ## _E ## i ## _what
-#define XCHAL_DTLB_SET_E(n,i,what)	_XCHAL_DTLB_SET_E(n,i, _ ## what )
-/*
- *  Example use:  XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
- *	to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
- */
-
-/*  Number of entries per autorefill way:  */
-#define XCHAL_ITLB_ARF_ENTRIES		(1<<XCHAL_ITLB_ARF_ENTRIES_LOG2)
-#define XCHAL_DTLB_ARF_ENTRIES		(1<<XCHAL_DTLB_ARF_ENTRIES_LOG2)
-
-/*
- *  Determine whether we have a full MMU (with Page Table and Protection)
- *  usable for an MMU-based OS:
- */
-#if 0
-#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
-# define XCHAL_HAVE_PTP_MMU		1	/* have full MMU (with page table [autorefill] and protection) */
-#else
-# define XCHAL_HAVE_PTP_MMU		0	/* don't have full MMU */
-#endif
-#endif
-
-/*
- *  For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
- */
-#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
-#define XCHAL_KSEG_CACHED_VADDR		0xD0000000	/* virt.addr of kernel RAM cached static map */
-#define XCHAL_KSEG_CACHED_PADDR		0x00000000	/* phys.addr of kseg_cached */
-#define XCHAL_KSEG_CACHED_SIZE		0x08000000	/* size in bytes of kseg_cached (assumed power of 2!!!) */
-#define XCHAL_KSEG_BYPASS_VADDR		0xD8000000	/* virt.addr of kernel RAM bypass (uncached) static map */
-#define XCHAL_KSEG_BYPASS_PADDR		0x00000000	/* phys.addr of kseg_bypass */
-#define XCHAL_KSEG_BYPASS_SIZE		0x08000000	/* size in bytes of kseg_bypass (assumed power of 2!!!) */
-
-#define XCHAL_KIO_CACHED_VADDR		0xE0000000	/* virt.addr of kernel I/O cached static map */
-#define XCHAL_KIO_CACHED_PADDR		0xF0000000	/* phys.addr of kio_cached */
-#define XCHAL_KIO_CACHED_SIZE		0x10000000	/* size in bytes of kio_cached (assumed power of 2!!!) */
-#define XCHAL_KIO_BYPASS_VADDR		0xF0000000	/* virt.addr of kernel I/O bypass (uncached) static map */
-#define XCHAL_KIO_BYPASS_PADDR		0xF0000000	/* phys.addr of kio_bypass */
-#define XCHAL_KIO_BYPASS_SIZE		0x10000000	/* size in bytes of kio_bypass (assumed power of 2!!!) */
-
-#define XCHAL_SEG_MAPPABLE_VADDR	0x00000000	/* start of largest non-static-mapped virtual addr area */
-#define XCHAL_SEG_MAPPABLE_SIZE		0xD0000000	/* size in bytes of  "  */
-/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size.  */
-#endif
-
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-/*  Data alignment required if used for instructions:  */
-#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH
-# define XCHAL_ALIGN_MAX		XCHAL_INST_FETCH_WIDTH
-#else
-# define XCHAL_ALIGN_MAX		XCHAL_DATA_WIDTH
-#endif
-
-/*
- *  Names kept for backward compatibility.
- *  (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
- *   under which they are released.  In the T10##.# era there was no distinction.)
- */
-#define XCHAL_HW_RELEASE_MAJOR		XCHAL_HW_VERSION_MAJOR
-#define XCHAL_HW_RELEASE_MINOR		XCHAL_HW_VERSION_MINOR
-#define XCHAL_HW_RELEASE_NAME		XCHAL_HW_VERSION_NAME
-
-
-
-
-/*----------------------------------------------------------------------
-			COPROCESSORS and EXTRA STATE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_EXTRA_SA_SIZE		XCHAL_NCP_SA_SIZE
-#define XCHAL_EXTRA_SA_ALIGN		XCHAL_NCP_SA_ALIGN
-#define XCHAL_CPEXTRA_SA_SIZE		XCHAL_TOTAL_SA_SIZE
-#define XCHAL_CPEXTRA_SA_ALIGN		XCHAL_TOTAL_SA_ALIGN
-
-#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
-
-	/*  Invoked at start of save area load/store sequence macro to setup macro
-	 *  internal offsets.  Not usually invoked directly.
-	 *	continue	0 for 1st sequence, 1 for subsequent consecutive ones.
-	 *	totofs		offset from original ptr to next load/store location.
-	 */
-	.macro	xchal_sa_start	continue totofs
-	.ifeq \continue
-	 .set	.Lxchal_pofs_, 0	/* offset from original ptr to current \ptr */
-	 .set	.Lxchal_ofs_, 0		/* offset from current \ptr to next load/store location */
-	.endif
-	.if \totofs + 1			/* if totofs specified (not -1) */
-	 .set	.Lxchal_ofs_, \totofs - .Lxchal_pofs_	/* specific offset from original ptr */
-	.endif
-	.endm
-
-	/*  Align portion of save area and bring ptr in range if necessary.
-	 *  Used by save area load/store sequences.  Not usually invoked directly.
-	 *  Allows combining multiple (sub-)sequences arbitrarily.
-	 *	ptr		pointer to save area (may be off, see .Lxchal_pofs_)
-	 *	minofs,maxofs	range of offset from cur ptr to next load/store loc;
-	 *			minofs <= 0 <= maxofs  (0 must always be valid offset)
-	 *			range must be within +/- 30kB or so.
-	 *	ofsalign	alignment granularity of minofs .. maxofs (pow of 2)
-	 *			(restriction on offset from ptr to next load/store loc)
-	 *	totalign	align from orig ptr to next load/store loc (pow of 2)
-	 */
-	.macro	xchal_sa_align	ptr minofs maxofs ofsalign totalign
-	/*  First align where we start accessing the next register
-	 *  per \totalign relative to original ptr (i.e. start of the save area):
-	 */
-	.set	.Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_
-	/*  If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range:  */
-	.if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1))
-	 .set	.Ligmask, 0xFFFFFFFF	/* TODO: optimize to addmi, per aligns and .Lxchal_ofs_ */
-	 addi	\ptr, \ptr, (.Lxchal_ofs_ & .Ligmask)
-	 .set	.Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask)
-	 .set	.Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask)
-	.endif
-	.endm
-	/*
-	 *  We could optimize for addi to expand to only addmi instead of
-	 *  "addmi;addi", where possible.  Here's a partial example how:
-	 * .set	.Lmaxmask, -(\ofsalign) & -(\totalign)
-	 * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0)
-	 *  .set	.Ligmask, 0xFFFFFF00
-	 * .elif ... ditto for negative ofs range ...
-	 *  .set .Ligmask, 0xFFFFFF00
-	 *  .set ... adjust per offset ...
-	 * .else
-	 *  .set .Ligmask, 0xFFFFFFFF
-	 * .endif
-	 */
-
-	/*  Invoke this after xchal_XXX_{load,store} macros to restore \ptr.  */
-	.macro	xchal_sa_ptr_restore	ptr
-	.if .Lxchal_pofs_
-	 addi	\ptr, \ptr, - .Lxchal_pofs_
-	 .set	.Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_
-	 .set	.Lxchal_pofs_, 0
-	.endif
-	.endm
-
-	/*
-	 *  Use as eg:
-	 *	xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5
-	 *	xchal_ncp_load a2, a0,a3,a4,a5
-	 *	xchal_atmps_load  a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5
-	 *
-	 *  Specify only the ARs you *haven't* saved/restored already, up to 4.
-	 *  They *must* be the *last* ARs (in same order) specified to save area
-	 *  load/store sequences.  In the example above, a0 and a3 were already
-	 *  saved/restored and unused (thus available) but a4 and a5 were not.
-	 */
-#define xchal_atmps_store	xchal_atmps_loadstore s32i,
-#define xchal_atmps_load	xchal_atmps_loadstore l32i,
-	.macro	xchal_atmps_loadstore	inst ptr offset nreq aa=0 ab=0 ac=0 ad=0
-	.set	.Lnsaved_, 0
-	.irp	reg,\aa,\ab,\ac,\ad
-	 .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif
-	.endr
-	.set	.Laofs_, 0
-	.irp	reg,\aa,\ab,\ac,\ad
-	 .ifgt (\nreq)-.Lnsaved_
-	  \inst	\reg, \ptr, .Laofs_+\offset
-	  .set	.Laofs_,.Laofs_+4
-	  .set	.Lnsaved_,.Lnsaved_+1
-	 .endif
-	.endr
-	.endm
-
-/*#define xchal_ncp_load_a2	xchal_ncp_load	a2,a3,a4,a5,a6*/
-/*#define xchal_ncp_store_a2	xchal_ncp_store	a2,a3,a4,a5,a6*/
-#define xchal_extratie_load		xchal_ncptie_load
-#define xchal_extratie_store		xchal_ncptie_store
-#define xchal_extratie_load_a2		xchal_ncptie_load  a2,a3,a4,a5,a6
-#define xchal_extratie_store_a2		xchal_ncptie_store a2,a3,a4,a5,a6
-#define xchal_extra_load		xchal_ncp_load
-#define xchal_extra_store		xchal_ncp_store
-#define xchal_extra_load_a2		xchal_ncp_load  a2,a3,a4,a5,a6
-#define xchal_extra_store_a2		xchal_ncp_store a2,a3,a4,a5,a6
-#define xchal_extra_load_funcbody	xchal_ncp_load  a2,a3,a4,a5,a6
-#define xchal_extra_store_funcbody	xchal_ncp_store a2,a3,a4,a5,a6
-#define xchal_cp0_store_a2		xchal_cp0_store  a2,a3,a4,a5,a6
-#define xchal_cp0_load_a2		xchal_cp0_load   a2,a3,a4,a5,a6
-#define xchal_cp1_store_a2		xchal_cp1_store  a2,a3,a4,a5,a6
-#define xchal_cp1_load_a2		xchal_cp1_load   a2,a3,a4,a5,a6
-#define xchal_cp2_store_a2		xchal_cp2_store  a2,a3,a4,a5,a6
-#define xchal_cp2_load_a2		xchal_cp2_load   a2,a3,a4,a5,a6
-#define xchal_cp3_store_a2		xchal_cp3_store  a2,a3,a4,a5,a6
-#define xchal_cp3_load_a2		xchal_cp3_load   a2,a3,a4,a5,a6
-#define xchal_cp4_store_a2		xchal_cp4_store  a2,a3,a4,a5,a6
-#define xchal_cp4_load_a2		xchal_cp4_load   a2,a3,a4,a5,a6
-#define xchal_cp5_store_a2		xchal_cp5_store  a2,a3,a4,a5,a6
-#define xchal_cp5_load_a2		xchal_cp5_load   a2,a3,a4,a5,a6
-#define xchal_cp6_store_a2		xchal_cp6_store  a2,a3,a4,a5,a6
-#define xchal_cp6_load_a2		xchal_cp6_load   a2,a3,a4,a5,a6
-#define xchal_cp7_store_a2		xchal_cp7_store  a2,a3,a4,a5,a6
-#define xchal_cp7_load_a2		xchal_cp7_load   a2,a3,a4,a5,a6
-
-/*  Empty placeholder macros for undefined coprocessors:  */
-#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0
-# if XCHAL_CP0_SA_SIZE == 0
-	.macro xchal_cp0_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp0_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP1_SA_SIZE == 0
-	.macro xchal_cp1_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp1_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP2_SA_SIZE == 0
-	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP3_SA_SIZE == 0
-	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP4_SA_SIZE == 0
-	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP5_SA_SIZE == 0
-	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP6_SA_SIZE == 0
-	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-# if XCHAL_CP7_SA_SIZE == 0
-	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-# endif
-#endif
-
-	/********************
-	 *  Macros to create functions that save and restore the state of *any* TIE
-	 *  coprocessor (by dynamic index).
-	 */
-
-	/*
-	 *  Macro that expands to the body of a function
-	 *  that stores the selected coprocessor's state (registers etc).
-	 *	Entry:	a2 = ptr to save area in which to save cp state
-	 *		a3 = coprocessor number
-	 *	Exit:	any register a2-a15 (?) may have been clobbered.
-	 */
-	.macro	xchal_cpi_store_funcbody
-#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
-# if XCHAL_CP0_SA_SIZE
-	bnez	a3, 99f
-	xchal_cp0_store_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP1_SA_SIZE
-	bnei	a3, 1, 99f
-	xchal_cp1_store_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP2_SA_SIZE
-	bnei	a3, 2, 99f
-	xchal_cp2_store_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP3_SA_SIZE
-	bnei	a3, 3, 99f
-	xchal_cp3_store_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP4_SA_SIZE
-	bnei	a3, 4, 99f
-	xchal_cp4_store_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP5_SA_SIZE
-	bnei	a3, 5, 99f
-	xchal_cp5_store_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP6_SA_SIZE
-	bnei	a3, 6, 99f
-	xchal_cp6_store_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP7_SA_SIZE
-	bnei	a3, 7, 99f
-	xchal_cp7_store_a2
-	j	90f
-99:
-# endif
-90:
-#endif
-	.endm
-
-	/*
-	 *  Macro that expands to the body of a function
-	 *  that loads the selected coprocessor's state (registers etc).
-	 *	Entry:	a2 = ptr to save area from which to restore cp state
-	 *		a3 = coprocessor number
-	 *	Exit:	any register a2-a15 (?) may have been clobbered.
-	 */
-	.macro	xchal_cpi_load_funcbody
-#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
-# if XCHAL_CP0_SA_SIZE
-	bnez	a3, 99f
-	xchal_cp0_load_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP1_SA_SIZE
-	bnei	a3, 1, 99f
-	xchal_cp1_load_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP2_SA_SIZE
-	bnei	a3, 2, 99f
-	xchal_cp2_load_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP3_SA_SIZE
-	bnei	a3, 3, 99f
-	xchal_cp3_load_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP4_SA_SIZE
-	bnei	a3, 4, 99f
-	xchal_cp4_load_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP5_SA_SIZE
-	bnei	a3, 5, 99f
-	xchal_cp5_load_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP6_SA_SIZE
-	bnei	a3, 6, 99f
-	xchal_cp6_load_a2
-	j	90f
-99:
-# endif
-# if XCHAL_CP7_SA_SIZE
-	bnei	a3, 7, 99f
-	xchal_cp7_load_a2
-	j	90f
-99:
-# endif
-90:
-#endif
-	.endm
-
-#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
-
-
-/*  Other default macros for undefined coprocessors:  */
-#ifndef XCHAL_CP0_NAME
-# define XCHAL_CP0_NAME				0
-# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM	0
-# define XCHAL_CP0_SA_CONTENTS_LIBDB		/* empty */
-#endif
-#ifndef XCHAL_CP1_NAME
-# define XCHAL_CP1_NAME				0
-# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM	0
-# define XCHAL_CP1_SA_CONTENTS_LIBDB		/* empty */
-#endif
-#ifndef XCHAL_CP2_NAME
-# define XCHAL_CP2_NAME				0
-# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM	0
-# define XCHAL_CP2_SA_CONTENTS_LIBDB		/* empty */
-#endif
-#ifndef XCHAL_CP3_NAME
-# define XCHAL_CP3_NAME				0
-# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM	0
-# define XCHAL_CP3_SA_CONTENTS_LIBDB		/* empty */
-#endif
-#ifndef XCHAL_CP4_NAME
-# define XCHAL_CP4_NAME				0
-# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM	0
-# define XCHAL_CP4_SA_CONTENTS_LIBDB		/* empty */
-#endif
-#ifndef XCHAL_CP5_NAME
-# define XCHAL_CP5_NAME				0
-# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM	0
-# define XCHAL_CP5_SA_CONTENTS_LIBDB		/* empty */
-#endif
-#ifndef XCHAL_CP6_NAME
-# define XCHAL_CP6_NAME				0
-# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM	0
-# define XCHAL_CP6_SA_CONTENTS_LIBDB		/* empty */
-#endif
-#ifndef XCHAL_CP7_NAME
-# define XCHAL_CP7_NAME				0
-# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM	0
-# define XCHAL_CP7_SA_CONTENTS_LIBDB		/* empty */
-#endif
-
-#if XCHAL_CP_MASK == 0
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP0_SA_SIZE               0
-#define XCHAL_CP0_SA_ALIGN              1
-#define XCHAL_CP1_SA_SIZE               0
-#define XCHAL_CP1_SA_ALIGN              1
-#define XCHAL_CP2_SA_SIZE               0
-#define XCHAL_CP2_SA_ALIGN              1
-#define XCHAL_CP3_SA_SIZE               0
-#define XCHAL_CP3_SA_ALIGN              1
-#define XCHAL_CP4_SA_SIZE               0
-#define XCHAL_CP4_SA_ALIGN              1
-#define XCHAL_CP5_SA_SIZE               0
-#define XCHAL_CP5_SA_ALIGN              1
-#define XCHAL_CP6_SA_SIZE               0
-#define XCHAL_CP6_SA_ALIGN              1
-#define XCHAL_CP7_SA_SIZE               0
-#define XCHAL_CP7_SA_ALIGN              1
-#endif
-
-
-/*  Indexing macros:  */
-#define _XCHAL_CP_SA_SIZE(n)		XCHAL_CP ## n ## _SA_SIZE
-#define XCHAL_CP_SA_SIZE(n)		_XCHAL_CP_SA_SIZE(n)	/* n = 0 .. 7 */
-#define _XCHAL_CP_SA_ALIGN(n)		XCHAL_CP ## n ## _SA_ALIGN
-#define XCHAL_CP_SA_ALIGN(n)		_XCHAL_CP_SA_ALIGN(n)	/* n = 0 .. 7 */
-
-#define XCHAL_CPEXTRA_SA_SIZE_TOR2      XCHAL_CPEXTRA_SA_SIZE	/* Tor2Beta only - do not use */
-
-/*  Link-time HAL global variables that report coprocessor numbers by name
-    (names are case-preserved from the original TIE):  */
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-# define _XCJOIN(a,b)	a ## b
-# define XCJOIN(a,b)	_XCJOIN(a,b)
-# ifdef XCHAL_CP0_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT);
-extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT);
-# endif
-# ifdef XCHAL_CP1_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT);
-extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT);
-# endif
-# ifdef XCHAL_CP2_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT);
-extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT);
-# endif
-# ifdef XCHAL_CP3_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT);
-extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT);
-# endif
-# ifdef XCHAL_CP4_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT);
-extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT);
-# endif
-# ifdef XCHAL_CP5_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT);
-extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT);
-# endif
-# ifdef XCHAL_CP6_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT);
-extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT);
-# endif
-# ifdef XCHAL_CP7_NAME
-extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT);
-extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
-# endif
-#endif
-
-
-
-
-/*----------------------------------------------------------------------
-				DERIVED
-  ----------------------------------------------------------------------*/
-
-#if XCHAL_HAVE_BE
-#define XCHAL_INST_ILLN			0xD60F		/* 2-byte illegal instruction, msb-first */
-#define XCHAL_INST_ILLN_BYTE0		0xD6		/* 2-byte illegal instruction, 1st byte */
-#define XCHAL_INST_ILLN_BYTE1		0x0F		/* 2-byte illegal instruction, 2nd byte */
-#else
-#define XCHAL_INST_ILLN			0xF06D		/* 2-byte illegal instruction, lsb-first */
-#define XCHAL_INST_ILLN_BYTE0		0x6D		/* 2-byte illegal instruction, 1st byte */
-#define XCHAL_INST_ILLN_BYTE1		0xF0		/* 2-byte illegal instruction, 2nd byte */
-#endif
-/*  Belongs in xtensa/hal.h:  */
-#define XTHAL_INST_ILL			0x000000	/* 3-byte illegal instruction */
-
-
-/*
- *  Because information as to exactly which hardware version is targeted
- *  by a given software build is not always available, compile-time HAL
- *  Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
- *  (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
- *   under which they are released.  In the T10##.# era there was no distinction.)
- */
-#if XCHAL_HW_CONFIGID_RELIABLE
-# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)	(XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)	(XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_AT(major,minor)		(XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
-# define XCHAL_HW_RELEASE_MAJOR_AT(major)		((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0)
-#else
-# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)	( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
-							: ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
-							: XTHAL_MAYBE )
-# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)	( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
-							: (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
-							: XTHAL_MAYBE )
-# define XCHAL_HW_RELEASE_AT(major,minor)		( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
-							   ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
-# define XCHAL_HW_RELEASE_MAJOR_AT(major)		XCHAL_HW_RELEASE_AT(major,0)
-#endif
-
-/*
- *  Specific errata:
- */
-
-/*
- *  Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
- *  relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
- */
-#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN	(XCHAL_HAVE_XEA1 && \
-					 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
-					  || XCHAL_HW_RELEASE_AT(1050,0)))
-/*
- *  Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1.
- *  Applies to specific set of configuration options.
- *  Part of the workaround is to add ISYNC at certain points in the code.
- *  The workaround gated by this macro can be disabled if not needed, e.g. if
- *  zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453.
- */
-#if (	XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \
-	XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \
-	XCHAL_ICACHE_SIZE != 0    && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \
-	XCHAL_HAVE_LOOPS          && XCHAL_LOOP_BUFFER_SIZE != 0 && \
-	XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453) )
-#define XCHAL_ERRATUM_453	1
-#else
-#define XCHAL_ERRATUM_453	0
-#endif
-
-/*
- *  Erratum 497 present in RE-2012.2 up to RG/RF-2015.2
- *  Applies to specific set of configuration options.
- *  Workaround is to add MEMWs after at most 8 cache WB instructions
- */
-#if ( ((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 &&    \
-        XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) ||   \
-       (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 &&    \
-        XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2)     \
-      ) && \
-      XCHAL_DCACHE_IS_WRITEBACK && \
-      XCHAL_HAVE_AXI && \
-      XCHAL_HAVE_PIF_WR_RESP && \
-      XCHAL_HAVE_PIF_REQ_ATTR &&  !defined(_NO_ERRATUM_497) \
-    )
-#define XCHAL_ERRATUM_497	1
-#else
-#define XCHAL_ERRATUM_497	0
-#endif
-
-/*
- * Erratum 572 (releases TBD, but present in ESP32)
- * Disable zero-overhead loop buffer to prevent rare illegal instruction
- * exceptions while executing zero-overhead loops.
- */
-#if ( XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 )
-#define XCHAL_ERRATUM_572   1
-#else
-#define XCHAL_ERRATUM_572   0
-#endif
-
-#endif /*XTENSA_CONFIG_CORE_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/config/defs.h b/tools/sdk/include/esp32/xtensa/config/defs.h
deleted file mode 100644
index d7c48ea84ab..00000000000
--- a/tools/sdk/include/esp32/xtensa/config/defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Definitions for Xtensa instructions, types, and protos. */
-
-/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2003-2004 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-/* NOTE: This file exists only for backward compatibility with T1050
-   and earlier Xtensa releases.  It includes only a subset of the
-   available header files.  */
-
-#ifndef _XTENSA_BASE_HEADER
-#define _XTENSA_BASE_HEADER
-
-#ifdef __XTENSA__
-
-#include <xtensa/tie/xt_core.h>
-#include <xtensa/tie/xt_misc.h>
-#include <xtensa/tie/xt_booleans.h>
-
-#endif /* __XTENSA__ */
-#endif /* !_XTENSA_BASE_HEADER */
diff --git a/tools/sdk/include/esp32/xtensa/config/specreg.h b/tools/sdk/include/esp32/xtensa/config/specreg.h
deleted file mode 100644
index 0135d4c7f5a..00000000000
--- a/tools/sdk/include/esp32/xtensa/config/specreg.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
-
-/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Include these special register bitfield definitions, for historical reasons:  */
-#include <xtensa/corebits.h>
-
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define SCOMPARE1	12
-#define ACCLO		16
-#define ACCHI		17
-#define MR_0		32
-#define MR_1		33
-#define MR_2		34
-#define MR_3		35
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define IBREAKENABLE	96
-#define MEMCTL		97
-#define ATOMCTL		99
-#define DDR		104
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define EPC_5		181
-#define EPC_6		182
-#define EPC_7		183
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EPS_5		197
-#define EPS_6		198
-#define EPS_7		199
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define EXCSAVE_5	213
-#define EXCSAVE_6	214
-#define EXCSAVE_7	215
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTENABLE	228
-#define PS		230
-#define VECBASE		231
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define CCOMPARE_2	242
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-#define MISC_REG_2	246
-#define MISC_REG_3	247
-
-/*  Special cases (bases of special register series):  */
-#define MR		32
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-
-/*  Special names for read-only and write-only interrupt registers:  */
-#define INTREAD		226
-#define INTSET		226
-#define INTCLEAR	227
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/tools/sdk/include/esp32/xtensa/config/system.h b/tools/sdk/include/esp32/xtensa/config/system.h
deleted file mode 100644
index 0d56eef74fc..00000000000
--- a/tools/sdk/include/esp32/xtensa/config/system.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/* 
- * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
- *
- *  NOTE: The location and contents of this file are highly subject to change.
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  The HAL itself has historically included this file in some instances,
- *  but this is not appropriate either, because the HAL is meant to be
- *  core-specific but system independent.
- */
-
-/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2000-2010 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef XTENSA_CONFIG_SYSTEM_H
-#define XTENSA_CONFIG_SYSTEM_H
-
-/*#include <xtensa/hal.h>*/
-
-
-
-/*----------------------------------------------------------------------
-				CONFIGURED SOFTWARE OPTIONS
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
-
-#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_ABI_WINDOWED		0
-#define XTHAL_ABI_CALL0			1
-/*  Alternatives:  */
-/*#define XSHAL_WINDOWED_ABI		1*/	/* set if windowed ABI selected */
-/*#define XSHAL_CALL0_ABI		0*/	/* set if call0 ABI selected */
-
-#define XSHAL_CLIB			XTHAL_CLIB_NEWLIB	/* (sw-only option, selected C library) */
-/*  The above maps to one of the following constants:  */
-#define XTHAL_CLIB_NEWLIB		0
-#define XTHAL_CLIB_UCLIBC		1
-#define XTHAL_CLIB_XCLIB		2
-/*  Alternatives:  */
-/*#define XSHAL_NEWLIB			1*/	/* set if newlib C library selected */
-/*#define XSHAL_UCLIBC			0*/	/* set if uCLibC C library selected */
-/*#define XSHAL_XCLIB			0*/	/* set if Xtensa C library selected */
-
-#define XSHAL_USE_FLOATING_POINT	1
-
-#define XSHAL_FLOATING_POINT_ABI	0
-
-/*  SW workarounds enabled for HW errata:  */
-
-/*----------------------------------------------------------------------
-				DEVICE ADDRESSES
-  ----------------------------------------------------------------------*/
-
-/*
- *  Strange place to find these, but the configuration GUI
- *  allows moving these around to account for various core
- *  configurations.  Specific boards (and their BSP software)
- *  will have specific meanings for these components.
- */
-
-/*  I/O Block areas:  */
-#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
-#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
-
-#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
-#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
-
-/*  System ROM:  */
-#define XSHAL_ROM_VADDR		0x50000000
-#define XSHAL_ROM_PADDR		0x50000000
-#define XSHAL_ROM_SIZE		0x01000000
-/*  Largest available area (free of vectors):  */
-#define XSHAL_ROM_AVAIL_VADDR	0x50000000
-#define XSHAL_ROM_AVAIL_VSIZE	0x01000000
-
-/*  System RAM:  */
-#define XSHAL_RAM_VADDR		0x60000000
-#define XSHAL_RAM_PADDR		0x60000000
-#define XSHAL_RAM_VSIZE		0x20000000
-#define XSHAL_RAM_PSIZE		0x20000000
-#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
-/*  Largest available area (free of vectors):  */
-#define XSHAL_RAM_AVAIL_VADDR	0x60000000
-#define XSHAL_RAM_AVAIL_VSIZE	0x20000000
-
-/*
- *  Shadow system RAM (same device as system RAM, at different address).
- *  (Emulation boards need this for the SONIC Ethernet driver
- *   when data caches are configured for writeback mode.)
- *  NOTE: on full MMU configs, this points to the BYPASS virtual address
- *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
- *  addresses are viewed through the BYPASS static map rather than
- *  the CACHED static map.
- */
-#define XSHAL_RAM_BYPASS_VADDR		0xA0000000
-#define XSHAL_RAM_BYPASS_PADDR		0xA0000000
-#define XSHAL_RAM_BYPASS_PSIZE		0x20000000
-
-/*  Alternate system RAM (different device than system RAM):  */
-/*#define XSHAL_ALTRAM_[VP]ADDR		...not configured...*/
-/*#define XSHAL_ALTRAM_SIZE		...not configured...*/
-
-/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
-#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
-#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
-#define XSHAL_SIMIO_PADDR		0xC0000000
-#define XSHAL_SIMIO_SIZE		0x20000000
-
-
-/*----------------------------------------------------------------------
- *  For use by reference testbench exit and diagnostic routines.
- */
-#define XSHAL_MAGIC_EXIT		0x0
-
-/*----------------------------------------------------------------------
- *			DEVICE-ADDRESS DEPENDENT...
- *
- *  Values written to CACHEATTR special register (or its equivalent)
- *  to enable and disable caches in various modes.
- *----------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------
-			BACKWARD COMPATIBILITY ...
-  ----------------------------------------------------------------------*/
-
-/*
- *  NOTE:  the following two macros are DEPRECATED.  Use the latter
- *  board-specific macros instead, which are specially tuned for the
- *  particular target environments' memory maps.
- */
-#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
-#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
-
-/*----------------------------------------------------------------------
-				GENERIC
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
- *  system (PIF) ROM, local memory, or XLMI.  */
-
-/*  These set any unused 512MB region to cache-BYPASS attribute:  */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x22221112	/* enable caches in write-back mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x22221112	/* enable caches in write-allocate mode */
-#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x22221112	/* enable caches in write-through mode */
-#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
-#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set any unused 512MB region to ILLEGAL attribute:  */
-#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xFFFF111F	/* enable caches in write-back mode */
-#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xFFFF111F	/* enable caches in write-allocate mode */
-#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xFFFF111F	/* enable caches in write-through mode */
-#define XSHAL_STRICT_CACHEATTR_BYPASS		0xFFFF222F	/* disable caches in bypass mode */
-#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
- *  NULL-pointer dereference bugs; all other unused 512MB regions are set
- *  to cache-BYPASS attribute:  */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x2222111F	/* enable caches in write-back mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x2222111F	/* enable caches in write-allocate mode */
-#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x2222111F	/* enable caches in write-through mode */
-#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
-#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-/*----------------------------------------------------------------------
-			ISS (Instruction Set Simulator) SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For now, ISS defaults to the TRAPNULL settings:  */
-#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
-#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
-#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
-#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
-
-#define XSHAL_ISS_PIPE_REGIONS	0
-#define XSHAL_ISS_SDRAM_REGIONS	0
-
-
-/*----------------------------------------------------------------------
-			XT2000 BOARD SPECIFIC ...
-  ----------------------------------------------------------------------*/
-
-/*  For the following, a 512MB region is used if it contains any system RAM,
- *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
- *  Regions containing devices are forced to cache-BYPASS mode regardless
- *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
-
-/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
-#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xFF22111F	/* enable caches in write-back mode */
-#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xFF22111F	/* enable caches in write-allocate mode */
-#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xFF22111F	/* enable caches in write-through mode */
-#define XSHAL_XT2000_CACHEATTR_BYPASS		0xFF22222F	/* disable caches in bypass mode */
-#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
-
-#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
-#define XSHAL_XT2000_SDRAM_REGIONS	0x00000440	/* BusInt SDRAM regions */
-
-
-/*----------------------------------------------------------------------
-				VECTOR INFO AND SIZES
-  ----------------------------------------------------------------------*/
-
-#define XSHAL_VECTORS_PACKED		0
-#define XSHAL_STATIC_VECTOR_SELECT	1
-#define XSHAL_RESET_VECTOR_VADDR	0x40000400
-#define XSHAL_RESET_VECTOR_PADDR	0x40000400
-
-/*
- *  Sizes allocated to vectors by the system (memory map) configuration.
- *  These sizes are constrained by core configuration (eg. one vector's
- *  code cannot overflow into another vector) but are dependent on the
- *  system or board (or LSP) memory map configuration.
- *
- *  Whether or not each vector happens to be in a system ROM is also
- *  a system configuration matter, sometimes useful, included here also:
- */
-#define XSHAL_RESET_VECTOR_SIZE	0x00000300
-#define XSHAL_RESET_VECTOR_ISROM	0
-#define XSHAL_USER_VECTOR_SIZE	0x00000038
-#define XSHAL_USER_VECTOR_ISROM	0
-#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNEL_VECTOR_SIZE	0x00000038
-#define XSHAL_KERNEL_VECTOR_ISROM	0
-#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
-#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x00000040
-#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
-#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
-#define XSHAL_WINDOW_VECTORS_ISROM	0
-#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL5_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL5_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL6_VECTOR_SIZE	0x00000038
-#define XSHAL_INTLEVEL6_VECTOR_ISROM	0
-#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL6_VECTOR_SIZE
-#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL6_VECTOR_ISROM
-#define XSHAL_NMI_VECTOR_SIZE	0x00000038
-#define XSHAL_NMI_VECTOR_ISROM	0
-#define XSHAL_INTLEVEL7_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
-
-
-#endif /*XTENSA_CONFIG_SYSTEM_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/config/tie-asm.h b/tools/sdk/include/esp32/xtensa/config/tie-asm.h
deleted file mode 100644
index 831d8676ae2..00000000000
--- a/tools/sdk/include/esp32/xtensa/config/tie-asm.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/* 
- * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file contains assembly-language definitions (assembly
-   macros, etc.) for this specific Xtensa processor's TIE extensions
-   and options.  It is customized to this Xtensa processor configuration.
-
-   Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_ASM_H
-#define _XTENSA_CORE_TIE_ASM_H
-
-/*  Selection parameter values for save-area save/restore macros:  */
-/*  Option vs. TIE:  */
-#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
-#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
-#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
-/*  Whether used automatically by compiler:  */
-#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
-#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
-#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
-/*  ABI handling across function calls:  */
-#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
-#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
-#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
-#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
-/*  Misc  */
-#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
-#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
-					| ((ccuse) & XTHAL_SAS_ANYCC)  \
-					| ((abi)   & XTHAL_SAS_ANYABI) )
-
-
-    /*
-      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger store sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to store.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to store, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any store.
-      */
-    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	rur.THREADPTR	\at1		// threadptr option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	rsr.ACCLO	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rsr.ACCHI	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 996, 4, 4
-	rsr.BR	\at1		// boolean option
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rsr.SCOMPARE1	\at1		// conditional store option
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	rsr.M0	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+8
-	rsr.M1	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+12
-	rsr.M2	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+16
-	rsr.M3	\at1		// MAC16 option
-	s32i	\at1, \ptr, .Lxchal_ofs_+20
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 996, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
-	.endif
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1008, 4, 4
-	rur.F64R_LO	\at1		// ureg 234
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rur.F64R_HI	\at1		// ureg 235
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	rur.F64S	\at1		// ureg 236
-	s32i	\at1, \ptr, .Lxchal_ofs_+8
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 12
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1008, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 12
-	.endif
-    .endm	// xchal_ncp_store
-
-    /*
-      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
-      *  (not including zero-overhead loop registers).
-      *  Required parameters:
-      *      ptr         Save area pointer address register (clobbered)
-      *                  (register must contain a 4 byte aligned address).
-      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
-      *                  registers are clobbered, the remaining are unused).
-      *  Optional parameters:
-      *      continue    If macro invoked as part of a larger load sequence, set to 1
-      *                  if this is not the first in the sequence.  Defaults to 0.
-      *      ofs         Offset from start of larger sequence (from value of first ptr
-      *                  in sequence) at which to load.  Defaults to next available space
-      *                  (or 0 if <continue> is 0).
-      *      select      Select what category(ies) of registers to load, as a bitmask
-      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
-      *      alloc       Select what category(ies) of registers to allocate; if any
-      *                  category is selected here that is not in <select>, space for
-      *                  the corresponding registers is skipped without doing any load.
-      */
-    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start	\continue, \ofs
-	// Optional global registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.THREADPTR	\at1		// threadptr option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1016, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
-	.endif
-	// Optional caller-saved registers used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.ACCLO	\at1		// MAC16 option
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wsr.ACCHI	\at1		// MAC16 option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1012, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
-	.endif
-	// Optional caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 996, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wsr.BR	\at1		// boolean option
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wsr.SCOMPARE1	\at1		// conditional store option
-	l32i	\at1, \ptr, .Lxchal_ofs_+8
-	wsr.M0	\at1		// MAC16 option
-	l32i	\at1, \ptr, .Lxchal_ofs_+12
-	wsr.M1	\at1		// MAC16 option
-	l32i	\at1, \ptr, .Lxchal_ofs_+16
-	wsr.M2	\at1		// MAC16 option
-	l32i	\at1, \ptr, .Lxchal_ofs_+20
-	wsr.M3	\at1		// MAC16 option
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
-	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 996, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
-	.endif
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 1008, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.F64R_LO	\at1		// ureg 234
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wur.F64R_HI	\at1		// ureg 235
-	l32i	\at1, \ptr, .Lxchal_ofs_+8
-	wur.F64S	\at1		// ureg 236
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 12
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 1008, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 12
-	.endif
-    .endm	// xchal_ncp_load
-
-
-#define XCHAL_NCP_NUM_ATMPS	1
-
-    /* 
-     *  Macro to store the state of TIE coprocessor FPU.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 4 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_store.
-     */
-#define xchal_cp_FPU_store	xchal_cp0_store
-    .macro	xchal_cp0_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 948, 4, 4
-	rur.FCR	\at1		// ureg 232
-	s32i	\at1, \ptr, .Lxchal_ofs_+0
-	rur.FSR	\at1		// ureg 233
-	s32i	\at1, \ptr, .Lxchal_ofs_+4
-	ssi	f0, \ptr, .Lxchal_ofs_+8
-	ssi	f1, \ptr, .Lxchal_ofs_+12
-	ssi	f2, \ptr, .Lxchal_ofs_+16
-	ssi	f3, \ptr, .Lxchal_ofs_+20
-	ssi	f4, \ptr, .Lxchal_ofs_+24
-	ssi	f5, \ptr, .Lxchal_ofs_+28
-	ssi	f6, \ptr, .Lxchal_ofs_+32
-	ssi	f7, \ptr, .Lxchal_ofs_+36
-	ssi	f8, \ptr, .Lxchal_ofs_+40
-	ssi	f9, \ptr, .Lxchal_ofs_+44
-	ssi	f10, \ptr, .Lxchal_ofs_+48
-	ssi	f11, \ptr, .Lxchal_ofs_+52
-	ssi	f12, \ptr, .Lxchal_ofs_+56
-	ssi	f13, \ptr, .Lxchal_ofs_+60
-	ssi	f14, \ptr, .Lxchal_ofs_+64
-	ssi	f15, \ptr, .Lxchal_ofs_+68
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 948, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
-	.endif
-    .endm	// xchal_cp0_store
-
-    /* 
-     *  Macro to load the state of TIE coprocessor FPU.
-     *  Required parameters:
-     *      ptr         Save area pointer address register (clobbered)
-     *                  (register must contain a 4 byte aligned address).
-     *      at1..at4    Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
-     *                  registers are clobbered, the remaining are unused).
-     *  Optional parameters are the same as for xchal_ncp_load.
-     */
-#define xchal_cp_FPU_load	xchal_cp0_load
-    .macro	xchal_cp0_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
-	xchal_sa_start \continue, \ofs
-	// Custom caller-saved registers not used by default by the compiler:
-	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
-	xchal_sa_align	\ptr, 0, 948, 4, 4
-	l32i	\at1, \ptr, .Lxchal_ofs_+0
-	wur.FCR	\at1		// ureg 232
-	l32i	\at1, \ptr, .Lxchal_ofs_+4
-	wur.FSR	\at1		// ureg 233
-	lsi	f0, \ptr, .Lxchal_ofs_+8
-	lsi	f1, \ptr, .Lxchal_ofs_+12
-	lsi	f2, \ptr, .Lxchal_ofs_+16
-	lsi	f3, \ptr, .Lxchal_ofs_+20
-	lsi	f4, \ptr, .Lxchal_ofs_+24
-	lsi	f5, \ptr, .Lxchal_ofs_+28
-	lsi	f6, \ptr, .Lxchal_ofs_+32
-	lsi	f7, \ptr, .Lxchal_ofs_+36
-	lsi	f8, \ptr, .Lxchal_ofs_+40
-	lsi	f9, \ptr, .Lxchal_ofs_+44
-	lsi	f10, \ptr, .Lxchal_ofs_+48
-	lsi	f11, \ptr, .Lxchal_ofs_+52
-	lsi	f12, \ptr, .Lxchal_ofs_+56
-	lsi	f13, \ptr, .Lxchal_ofs_+60
-	lsi	f14, \ptr, .Lxchal_ofs_+64
-	lsi	f15, \ptr, .Lxchal_ofs_+68
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
-	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
-	xchal_sa_align	\ptr, 0, 948, 4, 4
-	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
-	.endif
-    .endm	// xchal_cp0_load
-
-#define XCHAL_CP0_NUM_ATMPS	1
-#define XCHAL_SA_NUM_ATMPS	1
-
-	/*  Empty macros for unconfigured coprocessors:  */
-	.macro xchal_cp1_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp1_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
-
-#endif /*_XTENSA_CORE_TIE_ASM_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/config/tie.h b/tools/sdk/include/esp32/xtensa/config/tie.h
deleted file mode 100644
index e178799708e..00000000000
--- a/tools/sdk/include/esp32/xtensa/config/tie.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* 
- * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
- *
- *  NOTE:  This header file is not meant to be included directly.
- */
-
-/* This header file describes this specific Xtensa processor's TIE extensions
-   that extend basic Xtensa core functionality.  It is customized to this
-   Xtensa processor configuration.
-
-   Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_TIE_H
-#define _XTENSA_CORE_TIE_H
-
-#define XCHAL_CP_NUM			1	/* number of coprocessors */
-#define XCHAL_CP_MAX			1	/* max CP ID + 1 (0 if none) */
-#define XCHAL_CP_MASK			0x01	/* bitmask of all CPs by ID */
-#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
-
-/*  Basic parameters of each coprocessor:  */
-#define XCHAL_CP0_NAME			"FPU"
-#define XCHAL_CP0_IDENT			FPU
-#define XCHAL_CP0_SA_SIZE		72	/* size of state save area */
-#define XCHAL_CP0_SA_ALIGN		4	/* min alignment of save area */
-#define XCHAL_CP_ID_FPU             	0	/* coprocessor ID (0..7) */
-
-/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
-#define XCHAL_CP1_SA_SIZE		0
-#define XCHAL_CP1_SA_ALIGN		1
-#define XCHAL_CP2_SA_SIZE		0
-#define XCHAL_CP2_SA_ALIGN		1
-#define XCHAL_CP3_SA_SIZE		0
-#define XCHAL_CP3_SA_ALIGN		1
-#define XCHAL_CP4_SA_SIZE		0
-#define XCHAL_CP4_SA_ALIGN		1
-#define XCHAL_CP5_SA_SIZE		0
-#define XCHAL_CP5_SA_ALIGN		1
-#define XCHAL_CP6_SA_SIZE		0
-#define XCHAL_CP6_SA_ALIGN		1
-#define XCHAL_CP7_SA_SIZE		0
-#define XCHAL_CP7_SA_ALIGN		1
-
-/*  Save area for non-coprocessor optional and custom (TIE) state:  */
-#define XCHAL_NCP_SA_SIZE		48
-#define XCHAL_NCP_SA_ALIGN		4
-
-/*  Total save area for optional and custom state (NCP + CPn):  */
-#define XCHAL_TOTAL_SA_SIZE		128	/* with 16-byte align padding */
-#define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
-
-/*
- * Detailed contents of save areas.
- * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
- * before expanding the XCHAL_xxx_SA_LIST() macros.
- *
- * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
- *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
- *
- *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
- *	ccused = set if used by compiler without special options or code
- *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
- *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
- *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
- *	name = lowercase reg name (no quotes)
- *	galign = group byte alignment (power of 2) (galign >= align)
- *	align = register byte alignment (power of 2)
- *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
- *	  (not including any pad bytes required to galign this or next reg)
- *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
- *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
- *	regnum = reg index in regfile, or special/TIE-user reg number
- *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
- *	gapsz = intervening bits, if bitsz bits not stored contiguously
- *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
- *	reset = register reset value (or 0 if undefined at reset)
- *	x = reserved for future use (0 until then)
- *
- *  To filter out certain registers, e.g. to expand only the non-global
- *  registers used by the compiler, you can do something like this:
- *
- *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
- *  #define SELCC0(p...)
- *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
- *  #define SELAK0(p...)		REG(p)
- *  #define SELAK1(p...)		REG(p)
- *  #define SELAK2(p...)
- *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
- *		...what you want to expand...
- */
-
-#define XCHAL_NCP_SA_NUM	12
-#define XCHAL_NCP_SA_LIST(s)	\
- XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
- XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
- XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             br, 4, 4, 4,0x0204,  sr,4  , 16,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,        f64r_lo, 4, 4, 4,0x03EA,  ur,234, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,        f64r_hi, 4, 4, 4,0x03EB,  ur,235, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,           f64s, 4, 4, 4,0x03EC,  ur,236, 32,0,0,0)
-
-#define XCHAL_CP0_SA_NUM	18
-#define XCHAL_CP0_SA_LIST(s)	\
- XCHAL_SA_REG(s,0,0,1,0,            fcr, 4, 4, 4,0x03E8,  ur,232, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,1,0,            fsr, 4, 4, 4,0x03E9,  ur,233, 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f0, 4, 4, 4,0x0030,   f,0  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f1, 4, 4, 4,0x0031,   f,1  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f2, 4, 4, 4,0x0032,   f,2  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f3, 4, 4, 4,0x0033,   f,3  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f4, 4, 4, 4,0x0034,   f,4  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f5, 4, 4, 4,0x0035,   f,5  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f6, 4, 4, 4,0x0036,   f,6  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f7, 4, 4, 4,0x0037,   f,7  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f8, 4, 4, 4,0x0038,   f,8  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,             f9, 4, 4, 4,0x0039,   f,9  , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f10, 4, 4, 4,0x003A,   f,10 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f11, 4, 4, 4,0x003B,   f,11 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f12, 4, 4, 4,0x003C,   f,12 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f13, 4, 4, 4,0x003D,   f,13 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f14, 4, 4, 4,0x003E,   f,14 , 32,0,0,0) \
- XCHAL_SA_REG(s,0,0,2,0,            f15, 4, 4, 4,0x003F,   f,15 , 32,0,0,0)
-
-#define XCHAL_CP1_SA_NUM	0
-#define XCHAL_CP1_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP2_SA_NUM	0
-#define XCHAL_CP2_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP3_SA_NUM	0
-#define XCHAL_CP3_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP4_SA_NUM	0
-#define XCHAL_CP4_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP5_SA_NUM	0
-#define XCHAL_CP5_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP6_SA_NUM	0
-#define XCHAL_CP6_SA_LIST(s)	/* empty */
-
-#define XCHAL_CP7_SA_NUM	0
-#define XCHAL_CP7_SA_LIST(s)	/* empty */
-
-/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
-#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
-/* Byte length of instruction from its first byte, per FLIX.  */
-#define XCHAL_BYTE0_FORMAT_LENGTHS	\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
-	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
-
-#endif /*_XTENSA_CORE_TIE_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/core-macros.h b/tools/sdk/include/esp32/xtensa/core-macros.h
deleted file mode 100644
index 37c48921a4f..00000000000
--- a/tools/sdk/include/esp32/xtensa/core-macros.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * xtensa/core-macros.h -- C specific definitions
- *                         that depend on CORE configuration
- */
-
-/*
- * Copyright (c) 2012 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_CACHE_H
-#define XTENSA_CACHE_H
-
-#include <xtensa/config/core.h>
-
-/*  Only define things for C code.  */
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-
-
-
-/***************************   CACHE   ***************************/
-
-/* All the macros are in the lower case now and some of them 
- * share the name with the existing functions from hal.h.
- * Including this header file will define XTHAL_USE_CACHE_MACROS 
- * which directs hal.h not to use the functions.
- */
-
-/*
- *  Single-cache-line operations in C-callable inline assembly.
- *  Essentially macro versions (uppercase) of:
- *
- *	xthal_icache_line_invalidate(void *addr);
- *	xthal_icache_line_lock(void *addr);
- *	xthal_icache_line_unlock(void *addr);
- *	xthal_icache_sync(void);
- *
- *  NOTE:  unlike the above functions, the following macros do NOT
- *  execute the xthal_icache_sync() as part of each line operation.
- *  This sync must be called explicitly by the caller.  This is to
- *  allow better optimization when operating on more than one line.
- *
- *	xthal_dcache_line_invalidate(void *addr);
- *	xthal_dcache_line_writeback(void *addr);
- *	xthal_dcache_line_writeback_inv(void *addr);
- *	xthal_dcache_line_lock(void *addr);
- *	xthal_dcache_line_unlock(void *addr);
- *	xthal_dcache_sync(void);
- *	xthal_dcache_line_prefetch_for_write(void *addr);
- *	xthal_dcache_line_prefetch_for_read(void *addr);
- *
- *  All are made memory-barriers, given that's how they're typically used
- *  (ops operate on a whole line, so clobbers all memory not just *addr).
- *
- *  NOTE:  All the block block cache ops and line prefetches are implemented
- *  using intrinsics so they are better optimized regarding memory barriers etc.
- *  
- * All block downgrade functions exist in two forms: with and without
- * the 'max' parameter: This parameter allows compiler to optimize
- * the functions whenever the parameter is smaller than the cache size.
- *
- *	xthal_dcache_block_invalidate(void *addr, unsigned size);
- *	xthal_dcache_block_writeback(void *addr, unsigned size);
- *	xthal_dcache_block_writeback_inv(void *addr, unsigned size);
- *	xthal_dcache_block_invalidate_max(void *addr, unsigned size, unsigned max);
- *	xthal_dcache_block_writeback_max(void *addr, unsigned size, unsigned max);
- *	xthal_dcache_block_writeback_inv_max(void *addr, unsigned size, unsigned max);
- *
- *      xthal_dcache_block_prefetch_for_read(void *addr, unsigned size);
- *      xthal_dcache_block_prefetch_for_write(void *addr, unsigned size);
- *      xthal_dcache_block_prefetch_modify(void *addr, unsigned size);
- *      xthal_dcache_block_prefetch_read_write(void *addr, unsigned size);
- *      xthal_dcache_block_prefetch_for_read_grp(void *addr, unsigned size);
- *      xthal_dcache_block_prefetch_for_write_grp(void *addr, unsigned size);
- *      xthal_dcache_block_prefetch_modify_grp(void *addr, unsigned size);
- *      xthal_dcache_block_prefetch_read_write_grp(void *addr, unsigned size)
- *
- *	xthal_dcache_block_wait();
- *	xthal_dcache_block_required_wait();
- *	xthal_dcache_block_abort();
- *	xthal_dcache_block_prefetch_end();
- *	xthal_dcache_block_newgrp();
- */
-
-/***   INSTRUCTION CACHE   ***/
-
-#define XTHAL_USE_CACHE_MACROS
-
-#if XCHAL_ICACHE_SIZE > 0
-# define xthal_icache_line_invalidate(addr)	do { void *__a = (void*)(addr); \
-		__asm__ __volatile__("ihi %0, 0" :: "a"(__a) : "memory"); 	\
-		} while(0)
-#else
-# define xthal_icache_line_invalidate(addr)	do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
-# define xthal_icache_line_lock(addr)	do { void *__a = (void*)(addr);	 	\
-		__asm__ __volatile__("ipfl %0, 0" :: "a"(__a) : "memory"); 	\
-		} while(0)
-# define xthal_icache_line_unlock(addr)	do { void *__a = (void*)(addr); 	\
-		__asm__ __volatile__("ihu %0, 0" :: "a"(__a) : "memory");	\
-		} while(0)
-#else
-# define xthal_icache_line_lock(addr)		do {/*nothing*/} while(0)
-# define xthal_icache_line_unlock(addr)		do {/*nothing*/} while(0)
-#endif
-
-/*
- * Even if a config doesn't have caches, an isync is still needed
- * when instructions in any memory are modified, whether by a loader
- * or self-modifying code.  Therefore, this macro always produces
- * an isync, whether or not an icache is present.
- */
-#define xthal_icache_sync()							\
-		__asm__ __volatile__("isync":::"memory")
-
-
-/***   DATA CACHE   ***/
-
-#if XCHAL_DCACHE_SIZE > 0
-
-# include <xtensa/tie/xt_datacache.h>
-
-# define xthal_dcache_line_invalidate(addr)	do { void *__a = (void*)(addr); \
-		__asm__ __volatile__("dhi %0, 0" :: "a"(__a) : "memory"); 	\
-		} while(0)
-# define xthal_dcache_line_writeback(addr)	do { void *__a = (void*)(addr); \
-		__asm__ __volatile__("dhwb %0, 0" :: "a"(__a) : "memory"); 	\
-		} while(0)
-# define xthal_dcache_line_writeback_inv(addr)	do { void *__a = (void*)(addr); \
-		__asm__ __volatile__("dhwbi %0, 0" :: "a"(__a) : "memory"); 	\
-		} while(0)
-# define xthal_dcache_sync()							\
-		__asm__ __volatile__("" /*"dsync"?*/:::"memory")
-# define xthal_dcache_line_prefetch_for_read(addr) do {				\
-		XT_DPFR((const int*)addr, 0);					\
-		} while(0)
-#else
-# define xthal_dcache_line_invalidate(addr)		do {/*nothing*/} while(0)
-# define xthal_dcache_line_writeback(addr)		do {/*nothing*/} while(0)
-# define xthal_dcache_line_writeback_inv(addr)		do {/*nothing*/} while(0)
-# define xthal_dcache_sync()				__asm__ __volatile__("":::"memory")
-# define xthal_dcache_line_prefetch_for_read(addr)	do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
-# define xthal_dcache_line_lock(addr)	do { void *__a = (void*)(addr); 	\
-		__asm__ __volatile__("dpfl %0, 0" :: "a"(__a) : "memory"); 	\
-		} while(0)
-# define xthal_dcache_line_unlock(addr)	do { void *__a = (void*)(addr); 	\
-		__asm__ __volatile__("dhu %0, 0" :: "a"(__a) : "memory"); 	\
-		} while(0)
-#else
-# define xthal_dcache_line_lock(addr)		do {/*nothing*/} while(0)
-# define xthal_dcache_line_unlock(addr)		do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
-
-# define xthal_dcache_line_prefetch_for_write(addr) do {			\
-		XT_DPFW((const int*)addr, 0);					\
-		} while(0)
-#else
-# define xthal_dcache_line_prefetch_for_write(addr)	do {/*nothing*/} while(0)
-#endif
-
-
-/*****   Block Operations   *****/
-
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS
-
-/* upgrades */
-
-# define _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, type)		\
-		{						\
-		type((const int*)addr, size);			\
-		}
-
-/*downgrades */
-
-# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type)	\
-	unsigned _s = size;					\
-	unsigned _a = addr;					\
-	do {							\
-		unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? 	\
-				XCHAL_DCACHE_SIZE : _s; 	\
-		type((const int*)_a, __s);			\
-		_s -= __s; 					\
-		_a += __s;					\
-	} while(_s > 0);
-
-# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max)	\
-	if (max <= XCHAL_DCACHE_SIZE) {					\
-		unsigned _s = size;					\
-		unsigned _a = addr;					\
-		type((const int*)_a, _s);				\
-	}								\
-	else {								\
-		_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type);	\
-	}
-
-# define xthal_dcache_block_invalidate(addr, size)	do { 		\
-		_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHI_B);	\
-		} while(0)
-# define xthal_dcache_block_writeback(addr, size)	do {		\
-		_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWB_B);	\
-		} while(0)
-# define xthal_dcache_block_writeback_inv(addr, size)	do {		\
-		_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWBI_B);	\
-		} while(0)
-
-# define xthal_dcache_block_invalidate_max(addr, size, max)	do {		\
-		_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHI_B, max);	\
-		} while(0)
-# define xthal_dcache_block_writeback_max(addr, size, max)	do { 		\
-		_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWB_B, max);	\
-		} while(0)
-# define xthal_dcache_block_writeback_inv_max(addr, size, max)	do {		\
-		_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWBI_B, max);	\
-		} while(0)
-
-/* upgrades that are performed even with write-thru caches  */
-
-# define xthal_dcache_block_prefetch_read_write(addr, size) do {	\
-		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B);	\
-		} while(0)
-# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do {	\
-		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF);	\
-		} while(0)
-# define xthal_dcache_block_prefetch_for_read(addr, size) do {		\
-		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_B);	\
-		} while(0)
-# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do {	\
-		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_BF);	\
-		} while(0)
-
-/* abort all or end optional block cache operations */
-# define xthal_dcache_block_abort()	do { 		\
-		XT_PFEND_A();				\
-		} while(0)
-# define xthal_dcache_block_end()	do { 		\
-		XT_PFEND_O();				\
-		} while(0)
-
-/* wait for all/required block cache operations to finish */
-# define xthal_dcache_block_wait()	do { 		\
-		XT_PFWAIT_A();				\
-		} while(0)
-# define xthal_dcache_block_required_wait()	do { 	\
-		XT_PFWAIT_R();				\
-		} while(0)
-/* Start a new group */
-# define xthal_dcache_block_newgrp()	do { 		\
-		XT_PFNXT_F();				\
-		} while(0)
-#else
-# define xthal_dcache_block_invalidate(addr, size)		do {/*nothing*/} while(0)
-# define xthal_dcache_block_writeback(addr, size)		do {/*nothing*/} while(0)
-# define xthal_dcache_block_writeback_inv(addr, size)		do {/*nothing*/} while(0)
-# define xthal_dcache_block_invalidate_max(addr, size, max)	do {/*nothing*/} while(0)
-# define xthal_dcache_block_writeback_max(addr, size, max)	do {/*nothing*/} while(0)
-# define xthal_dcache_block_writeback_inv_max(addr, size, max) 	do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_read_write(addr, size)	do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_read_write_grp(addr, size)	do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_for_read(addr, size)	do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_for_read_grp(addr, size)	do {/*nothing*/} while(0)
-# define xthal_dcache_block_end()   				do {/*nothing*/} while(0)
-# define xthal_dcache_block_abort()  				do {/*nothing*/} while(0)
-# define xthal_dcache_block_wait()  				do {/*nothing*/} while(0)
-# define xthal_dcache_block_required_wait()   			do {/*nothing*/} while(0)
-# define xthal_dcache_block_newgrp()				do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
-
-# define xthal_dcache_block_prefetch_for_write(addr, size) do {	\
-		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B);	\
-		} while(0)
-# define xthal_dcache_block_prefetch_modify(addr, size) do {		\
-		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_B);	\
-		} while(0)
-# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do {	\
-		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF);	\
-		} while(0)
-# define xthal_dcache_block_prefetch_modify_grp(addr, size) do {	\
-		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_BF);	\
-		} while(0)
-#else
-# define xthal_dcache_block_prefetch_for_write(addr, size)	do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_modify(addr, size) 	do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_for_write_grp(addr, size)	do {/*nothing*/} while(0)
-# define xthal_dcache_block_prefetch_modify_grp(addr, size)  	do {/*nothing*/} while(0)
-#endif
-
-/***************************   INTERRUPTS   ***************************/
-
-/*
- *  Macro versions of:
- *	unsigned  xthal_get_intenable( void );
- *	void      xthal_set_intenable( unsigned );
- *	unsigned  xthal_get_interrupt( void );
- *	void      xthal_set_intset( unsigned );
- *	void      xthal_set_intclear( unsigned );
- *	unsigned  xthal_get_ccount(void);
- *	void      xthal_set_ccompare(int, unsigned);
- *	unsigned  xthal_get_ccompare(int);
- *
- *  NOTE: for {set,get}_ccompare, the first argument MUST be a decimal constant.
- */
-
-#if XCHAL_HAVE_INTERRUPTS
-# define XTHAL_GET_INTENABLE()	({ int __intenable; \
-				__asm__("rsr.intenable %0" : "=a"(__intenable)); \
-				__intenable; })
-# define XTHAL_SET_INTENABLE(v)	do { int __intenable = (int)(v); \
-			__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
-				} while(0)
-# define XTHAL_GET_INTERRUPT()	({ int __interrupt; \
-				__asm__ __volatile__("rsr.interrupt %0" : "=a"(__interrupt)); \
-				__interrupt; })
-# define XTHAL_SET_INTSET(v)	do { int __interrupt = (int)(v); \
-			__asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
-				} while(0)
-# define XTHAL_SET_INTCLEAR(v)	do { int __interrupt = (int)(v); \
-			__asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
-				} while(0)
-# define XTHAL_GET_CCOUNT()	({ int __ccount; \
-				__asm__ __volatile__("rsr.ccount %0" : "=a"(__ccount)); \
-				__ccount; })
-# define XTHAL_SET_CCOUNT(v)	do { int __ccount = (int)(v); \
-			__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \
-				} while(0)
-# define _XTHAL_GET_CCOMPARE(n)	({ int __ccompare; \
-				__asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \
-				__ccompare; })
-# define XTHAL_GET_CCOMPARE(n)	_XTHAL_GET_CCOMPARE(n)
-# define _XTHAL_SET_CCOMPARE(n,v) do { int __ccompare = (int)(v); \
-			__asm__ __volatile__("wsr.ccompare" #n " %0 ; esync" :: "a"(__ccompare):"memory"); \
-				} while(0)
-# define XTHAL_SET_CCOMPARE(n,v) _XTHAL_SET_CCOMPARE(n,v)
-#else
-# define XTHAL_GET_INTENABLE()		0
-# define XTHAL_SET_INTENABLE(v)		do {/*nothing*/} while(0)
-# define XTHAL_GET_INTERRUPT()		0
-# define XTHAL_SET_INTSET(v)		do {/*nothing*/} while(0)
-# define XTHAL_SET_INTCLEAR(v)		do {/*nothing*/} while(0)
-# define XTHAL_GET_CCOUNT()		0
-# define XTHAL_SET_CCOUNT(v)		do {/*nothing*/} while(0)
-# define XTHAL_GET_CCOMPARE(n)		0
-# define XTHAL_SET_CCOMPARE(n,v)	do {/*nothing*/} while(0)
-#endif
-
-
-/***************************   MISC   ***************************/
-
-/*
- *  Macro or inline versions of:
- *	void	  xthal_clear_regcached_code( void );
- *	unsigned  xthal_get_prid( void );
- *	unsigned  xthal_compare_and_set( int *addr, int testval, int setval );
- */
-
-#if XCHAL_HAVE_LOOPS
-# define XTHAL_CLEAR_REGCACHED_CODE()		\
-		__asm__ __volatile__("wsr.lcount %0" :: "a"(0) : "memory")
-#else
-# define XTHAL_CLEAR_REGCACHED_CODE()		do {/*nothing*/} while(0)
-#endif
-
-#if XCHAL_HAVE_PRID
-# define XTHAL_GET_PRID()	({ int __prid; \
-				__asm__("rsr.prid %0" : "=a"(__prid)); \
-				__prid; })
-#else
-# define XTHAL_GET_PRID()	0
-#endif
-
-
-static inline unsigned  XTHAL_COMPARE_AND_SET( int *addr, int testval, int setval )
-{
-    int result;
-
-#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
-    __asm__ __volatile__ (
-	"   wsr.scompare1 %2 \n"
-	"   s32c1i %0, %3, 0 \n"
-	    : "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
-	    : "memory");
-#elif XCHAL_HAVE_INTERRUPTS
-    int tmp;
-    __asm__ __volatile__ (
-        "   rsil   %4, 15 \n"		// %4 == saved ps
-        "   l32i   %0, %3, 0 \n"	// %0 == value to test, return val
-        "   bne    %2, %0, 9f \n"	// test
-        "   s32i   %1, %3, 0 \n"	// write the new value
-	"9: wsr.ps %4 ; rsync \n"	// restore the PS
-	: "=a"(result) 
-	: "0" (setval), "a" (testval), "a" (addr), "a" (tmp)
-	: "memory");
-#else
-    __asm__ __volatile__ (
-        "   l32i  %0, %3, 0 \n"		// %0 == value to test, return val
-        "   bne   %2, %0, 9f \n"	// test
-        "   s32i  %1, %3, 0 \n"		// write the new value
-	"9: \n"
-	    : "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
-	    : "memory");
-#endif
-    return result;
-}
-
-#if XCHAL_HAVE_EXTERN_REGS
-
-static inline unsigned XTHAL_RER (unsigned int reg)
-{
-  unsigned result;
-
-  __asm__ __volatile__ (
-	"   rer     %0, %1"
-	: "=a" (result) : "a" (reg) : "memory");
-
-  return result;
-}
-
-static inline void XTHAL_WER (unsigned reg, unsigned value)
-{
-  __asm__ __volatile__ (
-	"   wer     %0, %1"
-	: : "a" (value), "a" (reg) : "memory");
-}
-
-#endif /* XCHAL_HAVE_EXTERN_REGS */
-
-#endif /* C code */
-
-#endif /*XTENSA_CACHE_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/coreasm.h b/tools/sdk/include/esp32/xtensa/coreasm.h
deleted file mode 100644
index e41e04d1bda..00000000000
--- a/tools/sdk/include/esp32/xtensa/coreasm.h
+++ /dev/null
@@ -1,939 +0,0 @@
-/*
- * xtensa/coreasm.h -- assembler-specific definitions that depend on CORE configuration
- *
- *  Source for configuration-independent binaries (which link in a
- *  configuration-specific HAL library) must NEVER include this file.
- *  It is perfectly normal, however, for the HAL itself to include this file.
- *
- *  This file must NOT include xtensa/config/system.h.  Any assembler
- *  header file that depends on system information should likely go
- *  in a new systemasm.h (or sysasm.h) header file.
- *
- *  NOTE: macro beqi32 is NOT configuration-dependent, and is placed
- *        here until we have a proper configuration-independent header file.
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/coreasm.h#3 $ */
-
-/*
- * Copyright (c) 2000-2014 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_COREASM_H
-#define XTENSA_COREASM_H
-
-/*
- *  Tell header files this is assembly source, so they can avoid non-assembler
- *  definitions (eg. C types etc):
- */
-#ifndef _ASMLANGUAGE	/* conditionalize to avoid cpp warnings (3rd parties might use same macro) */
-#define _ASMLANGUAGE
-#endif
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/config/system.h>
-
-/*
- *  Assembly-language specific definitions (assembly macros, etc.).
- */
-
-/*----------------------------------------------------------------------
- *  find_ms_setbit
- *
- *  This macro finds the most significant bit that is set in <as>
- *  and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
- *  The index counts starting at zero for the lsbit, so the return
- *  value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
- *
- *  Parameters:
- *	<ad>	destination address register (any register)
- *	<as>	source address register
- *	<at>	temporary address register (must be different than <as>)
- *	<base>	constant value added to result (usually 0 or 1)
- *  On entry:
- *	<ad> = undefined if different than <as>
- *	<as> = value whose most significant set bit is to be found
- *	<at> = undefined
- *	no other registers are used by this macro.
- *  On exit:
- *	<ad> = <base> + index of msbit set in original <as>,
- *	     = <base> - 1 if original <as> was zero.
- *	<as> clobbered (if not <ad>)
- *	<at> clobbered (if not <ad>)
- *  Example:
- *	find_ms_setbit a0, a4, a0, 0		-- return in a0 index of msbit set in a4
- */
-
-	.macro	find_ms_setbit ad, as, at, base
-#if XCHAL_HAVE_NSA
-	movi	\at, 31+\base
-	nsau	\as, \as	// get index of \as, numbered from msbit (32 if absent)
-	sub	\ad, \at, \as	// get numbering from lsbit (0..31, -1 if absent)
-#else /* XCHAL_HAVE_NSA */
-	movi	\at, \base	// start with result of 0 (point to lsbit of 32)
-
-	beqz	\as, 2f		// special case for zero argument: return -1
-	bltui	\as, 0x10000, 1f	// is it one of the 16 lsbits? (if so, check lower 16 bits)
-	addi	\at, \at, 16	// no, increment result to upper 16 bits (of 32)
-	//srli	\as, \as, 16	// check upper half (shift right 16 bits)
-	extui	\as, \as, 16, 16	// check upper half (shift right 16 bits)
-1:	bltui	\as, 0x100, 1f	// is it one of the 8 lsbits? (if so, check lower 8 bits)
-	addi	\at, \at, 8	// no, increment result to upper 8 bits (of 16)
-	srli	\as, \as, 8	// shift right to check upper 8 bits
-1:	bltui	\as, 0x10, 1f	// is it one of the 4 lsbits? (if so, check lower 4 bits)
-	addi	\at, \at, 4	// no, increment result to upper 4 bits (of 8)
-	srli	\as, \as, 4	// shift right 4 bits to check upper half
-1:	bltui	\as, 0x4, 1f	// is it one of the 2 lsbits? (if so, check lower 2 bits)
-	addi	\at, \at, 2	// no, increment result to upper 2 bits (of 4)
-	srli	\as, \as, 2	// shift right 2 bits to check upper half
-1:	bltui	\as, 0x2, 1f	// is it the lsbit?
-	addi	\at, \at, 2	// no, increment result to upper bit (of 2)
-2:	addi	\at, \at, -1	// (from just above: add 1;  from beqz: return -1)
-	//srli	\as, \as, 1
-1:				// done! \at contains index of msbit set (or -1 if none set)
-	.if	0x\ad - 0x\at	// destination different than \at ? (works because regs are a0-a15)
-	mov	\ad, \at	// then move result to \ad
-	.endif
-#endif /* XCHAL_HAVE_NSA */
-	.endm	// find_ms_setbit
-
-/*----------------------------------------------------------------------
- *  find_ls_setbit
- *
- *  This macro finds the least significant bit that is set in <as>,
- *  and return its index in <ad>.
- *  Usage is the same as for the find_ms_setbit macro.
- *  Example:
- *	find_ls_setbit a0, a4, a0, 0	-- return in a0 index of lsbit set in a4
- */
-
-	.macro	find_ls_setbit ad, as, at, base
-	neg	\at, \as	// keep only the least-significant bit that is set...
-	and	\as, \at, \as	// ... in \as
-	find_ms_setbit	\ad, \as, \at, \base
-	.endm	// find_ls_setbit
-
-/*----------------------------------------------------------------------
- *  find_ls_one
- *
- *  Same as find_ls_setbit with base zero.
- *  Source (as) and destination (ad) registers must be different.
- *  Provided for backward compatibility.
- */
-
-	.macro	find_ls_one ad, as
-	find_ls_setbit	\ad, \as, \ad, 0
-	.endm	// find_ls_one
-
-/*----------------------------------------------------------------------
- *  floop, floopnez, floopgtz, floopend
- *
- *  These macros are used for fast inner loops that
- *  work whether or not the Loops options is configured.
- *  If the Loops option is configured, they simply use
- *  the zero-overhead LOOP instructions; otherwise
- *  they use explicit decrement and branch instructions.
- *
- *  They are used in pairs, with floop, floopnez or floopgtz
- *  at the beginning of the loop, and floopend at the end.
- *
- *  Each pair of loop macro calls must be given the loop count
- *  address register and a unique label for that loop.
- *
- *  Example:
- *
- *	movi	 a3, 16     // loop 16 times
- *	floop    a3, myloop1
- *	:
- *	bnez     a7, end1	// exit loop if a7 != 0
- *	:
- *	floopend a3, myloop1
- *  end1:
- *
- *  Like the LOOP instructions, these macros cannot be
- *  nested, must include at least one instruction,
- *  cannot call functions inside the loop, etc.
- *  The loop can be exited by jumping to the instruction
- *  following floopend (or elsewhere outside the loop),
- *  or continued by jumping to a NOP instruction placed
- *  immediately before floopend.
- *
- *  Unlike LOOP instructions, the register passed to floop*
- *  cannot be used inside the loop, because it is used as
- *  the loop counter if the Loops option is not configured.
- *  And its value is undefined after exiting the loop.
- *  And because the loop counter register is active inside
- *  the loop, you can't easily use this construct to loop
- *  across a register file using ROTW as you might with LOOP
- *  instructions, unless you copy the loop register along.
- */
-
-	/*  Named label version of the macros:  */
-
-	.macro	floop		ar, endlabel
-	floop_		\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
-	.endm
-
-	.macro	floopnez	ar, endlabel
-	floopnez_	\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
-	.endm
-
-	.macro	floopgtz	ar, endlabel
-	floopgtz_	\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
-	.endm
-
-	.macro	floopend	ar, endlabel
-	floopend_	\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
-	.endm
-
-	/*  Numbered local label version of the macros:  */
-#if 0 /*UNTESTED*/
-	.macro	floop89		ar
-	floop_		\ar, 8, 9f
-	.endm
-
-	.macro	floopnez89	ar
-	floopnez_	\ar, 8, 9f
-	.endm
-
-	.macro	floopgtz89	ar
-	floopgtz_	\ar, 8, 9f
-	.endm
-
-	.macro	floopend89	ar
-	floopend_	\ar, 8b, 9
-	.endm
-#endif /*0*/
-
-	/*  Underlying version of the macros:  */
-
-	.macro	floop_	ar, startlabel, endlabelref
-	.ifdef	_infloop_
-	.if	_infloop_
-	.err	// Error: floop cannot be nested
-	.endif
-	.endif
-	.set	_infloop_, 1
-#if XCHAL_HAVE_LOOPS
-	loop	\ar, \endlabelref
-#else /* XCHAL_HAVE_LOOPS */
-\startlabel:
-	addi	\ar, \ar, -1
-#endif /* XCHAL_HAVE_LOOPS */
-	.endm	// floop_
-
-	.macro	floopnez_	ar, startlabel, endlabelref
-	.ifdef	_infloop_
-	.if	_infloop_
-	.err	// Error: floopnez cannot be nested
-	.endif
-	.endif
-	.set	_infloop_, 1
-#if XCHAL_HAVE_LOOPS
-	loopnez	\ar, \endlabelref
-#else /* XCHAL_HAVE_LOOPS */
-	beqz	\ar, \endlabelref
-\startlabel:
-	addi	\ar, \ar, -1
-#endif /* XCHAL_HAVE_LOOPS */
-	.endm	// floopnez_
-
-	.macro	floopgtz_	ar, startlabel, endlabelref
-	.ifdef	_infloop_
-	.if	_infloop_
-	.err	// Error: floopgtz cannot be nested
-	.endif
-	.endif
-	.set	_infloop_, 1
-#if XCHAL_HAVE_LOOPS
-	loopgtz	\ar, \endlabelref
-#else /* XCHAL_HAVE_LOOPS */
-	bltz	\ar, \endlabelref
-	beqz	\ar, \endlabelref
-\startlabel:
-	addi	\ar, \ar, -1
-#endif /* XCHAL_HAVE_LOOPS */
-	.endm	// floopgtz_
-
-
-	.macro	floopend_	ar, startlabelref, endlabel
-	.ifndef	_infloop_
-	.err	// Error: floopend without matching floopXXX
-	.endif
-	.ifeq	_infloop_
-	.err	// Error: floopend without matching floopXXX
-	.endif
-	.set	_infloop_, 0
-#if ! XCHAL_HAVE_LOOPS
-	bnez	\ar, \startlabelref
-#endif /* XCHAL_HAVE_LOOPS */
-\endlabel:
-	.endm	// floopend_
-
-/*----------------------------------------------------------------------
- *  crsil  --  conditional RSIL (read/set interrupt level)
- *
- *  Executes the RSIL instruction if it exists, else just reads PS.
- *  The RSIL instruction does not exist in the new exception architecture
- *  if the interrupt option is not selected.
- */
-
-	.macro	crsil	ar, newlevel
-#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
-	rsil	\ar, \newlevel
-#else
-	rsr	\ar, PS
-#endif
-	.endm	// crsil
-
-/*----------------------------------------------------------------------
- *  safe_movi_a0  --  move constant into a0 when L32R is not safe
- *
- *  This macro is typically used by interrupt/exception handlers.
- *  Loads a 32-bit constant in a0, without using any other register,
- *  and without corrupting the LITBASE register, even when the
- *  value of the LITBASE register is unknown (eg. when application
- *  code and interrupt/exception handling code are built independently,
- *  and thus with independent values of the LITBASE register;
- *  debug monitors are one example of this).
- *
- *  Worst-case size of resulting code:  17 bytes.
- */
-
-	.macro	safe_movi_a0	constant
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
-	/*  Contort a PC-relative literal load even though we may be in litbase-relative mode: */
-	j	1f
-	.begin	no-transform			// ensure what follows is assembled exactly as-is
-	.align	4				// ensure constant and call0 target ...
-	.byte	0				// ... are 4-byte aligned (call0 instruction is 3 bytes long)
-1:	call0	2f				// read PC (that follows call0) in a0
-	.long	\constant			// 32-bit constant to load into a0
-2:
-	.end	no-transform
-	l32i	a0, a0, 0			// load constant
-#else
-	movi	a0, \constant			// no LITBASE, can assume PC-relative L32R
-#endif
-	.endm
-
-
-
-
-/*----------------------------------------------------------------------
- *  window_spill{4,8,12}
- *
- *  These macros spill callers' register windows to the stack.
- *  They work for both privileged and non-privileged tasks.
- *  Must be called from a windowed ABI context, eg. within
- *  a windowed ABI function (ie. valid stack frame, window
- *  exceptions enabled, not in exception mode, etc).
- *
- *  This macro requires a single invocation of the window_spill_common
- *  macro in the same assembly unit and section.
- *
- *  Note that using window_spill{4,8,12} macros is more efficient
- *  than calling a function implemented using window_spill_function,
- *  because the latter needs extra code to figure out the size of
- *  the call to the spilling function.
- *
- *  Example usage:
- *	
- *		.text
- *		.align	4
- *		.global	some_function
- *		.type	some_function,@function
- *	some_function:
- *		entry	a1, 16
- *		:
- *		:
- *
- *		window_spill4	// Spill windows of some_function's callers; preserves a0..a3 only;
- *				// to use window_spill{8,12} in this example function we'd have
- *				// to increase space allocated by the entry instruction, because
- *				// 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
- *				// for call8/window_spill8 or call12/window_spill12 respectively.
- *
- *		:
- *
- *		retw
- *
- *		window_spill_common	// instantiates code used by window_spill4
- *
- *
- *  On entry:
- *	none (if window_spill4)
- *	stack frame has enough space allocated for call8 (if window_spill8)
- *	stack frame has enough space allocated for call12 (if window_spill12)
- *  On exit:
- *	 a4..a15 clobbered (if window_spill4)
- *	 a8..a15 clobbered (if window_spill8)
- *	a12..a15 clobbered (if window_spill12)
- *	no caller windows are in live registers
- */
-
-	.macro	window_spill4
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 16
-	movi	a15, 0			// for 16-register files, no need to call to reach the end
-# elif XCHAL_NUM_AREGS == 32
-	call4	.L__wdwspill_assist28	// call deep enough to clear out any live callers
-# elif XCHAL_NUM_AREGS == 64
-	call4	.L__wdwspill_assist60	// call deep enough to clear out any live callers
-# endif
-#endif
-	.endm	// window_spill4
-
-	.macro	window_spill8
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 16
-	movi	a15, 0			// for 16-register files, no need to call to reach the end
-# elif XCHAL_NUM_AREGS == 32
-	call8	.L__wdwspill_assist24	// call deep enough to clear out any live callers
-# elif XCHAL_NUM_AREGS == 64
-	call8	.L__wdwspill_assist56	// call deep enough to clear out any live callers
-# endif
-#endif
-	.endm	// window_spill8
-
-	.macro	window_spill12
-#if XCHAL_HAVE_WINDOWED
-# if XCHAL_NUM_AREGS == 16
-	movi	a15, 0			// for 16-register files, no need to call to reach the end
-# elif XCHAL_NUM_AREGS == 32
-	call12	.L__wdwspill_assist20	// call deep enough to clear out any live callers
-# elif XCHAL_NUM_AREGS == 64
-	call12	.L__wdwspill_assist52	// call deep enough to clear out any live callers
-# endif
-#endif
-	.endm	// window_spill12
-
-
-/*----------------------------------------------------------------------
- *  window_spill_function
- *
- *  This macro outputs a function that will spill its caller's callers'
- *  register windows to the stack.  Eg. it could be used to implement
- *  a version of xthal_window_spill() that works in non-privileged tasks.
- *  This works for both privileged and non-privileged tasks.
- *
- *  Typical usage:
- *
- *		.text
- *		.align	4
- *		.global	my_spill_function
- *		.type	my_spill_function,@function
- *	my_spill_function:
- *		window_spill_function
- *
- *  On entry to resulting function:
- *	none
- *  On exit from resulting function:
- *	none (no caller windows are in live registers)
- */
-
-	.macro	window_spill_function
-#if XCHAL_HAVE_WINDOWED
-#  if XCHAL_NUM_AREGS == 32
-	entry	sp, 48
-	bbci.l	a0, 31, 1f		// branch if called with call4
-	bbsi.l	a0, 30, 2f		// branch if called with call12
-	call8	.L__wdwspill_assist16	// called with call8, only need another 8
-	retw
-1:	call12	.L__wdwspill_assist16	// called with call4, only need another 12
-	retw
-2:	call4	.L__wdwspill_assist16	// called with call12, only need another 4
-	retw
-#  elif XCHAL_NUM_AREGS == 64
-	entry	sp, 48
-	bbci.l	a0, 31, 1f		// branch if called with call4
-	bbsi.l	a0, 30, 2f		// branch if called with call12
-	call4	.L__wdwspill_assist52	// called with call8, only need a call4
-	retw
-1:	call8	.L__wdwspill_assist52	// called with call4, only need a call8
-	retw
-2:	call12	.L__wdwspill_assist40	// called with call12, can skip a call12
-	retw
-#  elif XCHAL_NUM_AREGS == 16
-	entry	sp, 16
-	bbci.l	a0, 31, 1f	// branch if called with call4
-	bbsi.l	a0, 30, 2f	// branch if called with call12
-	movi	a7, 0		// called with call8
-	retw
-1:	movi	a11, 0		// called with call4
-2:	retw			// if called with call12, everything already spilled
-
-//	movi	a15, 0		// trick to spill all but the direct caller
-//	j	1f
-//	//  The entry instruction is magical in the assembler (gets auto-aligned)
-//	//  so we have to jump to it to avoid falling through the padding.
-//	//  We need entry/retw to know where to return.
-//1:	entry	sp, 16
-//	retw
-#  else
-#   error "unrecognized address register file size"
-#  endif
-
-#endif /* XCHAL_HAVE_WINDOWED */
-	window_spill_common
-	.endm	// window_spill_function
-
-/*----------------------------------------------------------------------
- *  window_spill_common
- *
- *  Common code used by any number of invocations of the window_spill##
- *  and window_spill_function macros.
- *
- *  Must be instantiated exactly once within a given assembly unit,
- *  within call/j range of and same section as window_spill##
- *  macro invocations for that assembly unit.
- *  (Is automatically instantiated by the window_spill_function macro.)
- */
-
-	.macro	window_spill_common
-#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
-	.ifndef	.L__wdwspill_defined
-#  if XCHAL_NUM_AREGS >= 64
-.L__wdwspill_assist60:
-	entry	sp, 32
-	call8	.L__wdwspill_assist52
-	retw
-.L__wdwspill_assist56:
-	entry	sp, 16
-	call4	.L__wdwspill_assist52
-	retw
-.L__wdwspill_assist52:
-	entry	sp, 48
-	call12	.L__wdwspill_assist40
-	retw
-.L__wdwspill_assist40:
-	entry	sp, 48
-	call12	.L__wdwspill_assist28
-	retw
-#  endif
-.L__wdwspill_assist28:
-	entry	sp, 48
-	call12	.L__wdwspill_assist16
-	retw
-.L__wdwspill_assist24:
-	entry	sp, 32
-	call8	.L__wdwspill_assist16
-	retw
-.L__wdwspill_assist20:
-	entry	sp, 16
-	call4	.L__wdwspill_assist16
-	retw
-.L__wdwspill_assist16:
-	entry	sp, 16
-	movi	a15, 0
-	retw
-	.set	.L__wdwspill_defined, 1
-	.endif
-#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
-	.endm	// window_spill_common
-
-/*----------------------------------------------------------------------
- *  beqi32
- *
- *  macro implements version of beqi for arbitrary 32-bit immediate value
- *
- *     beqi32 ax, ay, imm32, label
- * 
- *  Compares value in register ax with imm32 value and jumps to label if
- *  equal. Clobbers register ay if needed
- *
- */
-   .macro beqi32	ax, ay, imm, label
-    .ifeq ((\imm-1) & ~7)	// 1..8 ?
-		beqi	\ax, \imm, \label
-    .else
-      .ifeq (\imm+1)		// -1 ?
-		beqi	\ax, \imm, \label
-      .else
-        .ifeq (\imm)		// 0 ?
-		beqz	\ax, \label
-        .else
-		//  We could also handle immediates 10,12,16,32,64,128,256 
-		//  but it would be a long macro...
-		movi	\ay, \imm
-		beq	\ax, \ay, \label
-        .endif
-      .endif
-    .endif
-   .endm // beqi32
-
-/*----------------------------------------------------------------------
- *  isync_retw_nop
- *
- *  This macro must be invoked immediately after ISYNC if ISYNC
- *  would otherwise be immediately followed by RETW (or other instruction
- *  modifying WindowBase or WindowStart), in a context where
- *  kernel vector mode may be selected, and level-one interrupts
- *  and window overflows may be enabled, on an XEA1 configuration.
- *
- *  On hardware with erratum "XEA1KWIN" (see <xtensa/core.h> for details),
- *  XEA1 code must have at least one instruction between ISYNC and RETW if
- *  run in kernel vector mode with interrupts and window overflows enabled.
- */
-	.macro	isync_retw_nop
-#if XCHAL_MAYHAVE_ERRATUM_XEA1KWIN
-	nop
-#endif
-	.endm
-
-/*----------------------------------------------------------------------
- *  isync_erratum453
- *
- *  This macro must be invoked at certain points in the code,
- *  such as in exception and interrupt vectors in particular,
- *  to work around erratum 453.
- */
-	.macro	isync_erratum453
-#if XCHAL_ERRATUM_453
-	isync
-#endif
-	.endm
-
-
-
-/*----------------------------------------------------------------------
- *  abs
- *
- *  implements abs on machines that do not have it configured
- */
-	
-#if !XCHAL_HAVE_ABS
-	.macro abs arr, ars
-	.ifc \arr, \ars
-	//src equal dest is less efficient
-	bgez \arr, 1f
-	neg \arr, \arr
-1:	
-	.else
-	neg \arr, \ars
-	movgez \arr, \ars, \ars
-	.endif
-	.endm
-#endif /* !XCHAL_HAVE_ABS */
-
-
-/*----------------------------------------------------------------------
- *  addx2
- *  
- *  implements addx2 on machines that do not have it configured
- *     
- */
-
-#if !XCHAL_HAVE_ADDX
-	.macro addx2 arr, ars, art
-	.ifc \arr, \art
-	.ifc \arr, \ars
-	// addx2 a, a, a     (not common)
-	.err
-	.else
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	.endif
-	.else
-	//addx2 a, b, c
-	//addx2 a, a, b
-	//addx2 a, b, b
-	slli \arr, \ars, 1
-	add  \arr, \arr, \art
-	.endif
-	.endm
-#endif /* !XCHAL_HAVE_ADDX */
-	
-/*----------------------------------------------------------------------
- *  addx4
- * 
- *  implements addx4 on machines that do not have it configured
- *
- */
-	
-#if !XCHAL_HAVE_ADDX
-	.macro addx4 arr, ars, art
-	.ifc \arr, \art
-	.ifc \arr, \ars
-	// addx4 a, a, a     (not common)
-	 .err
-	 .else
-	//# addx4 a, b, a
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	.endif
-	.else
-	//addx4 a, b, c
-	//addx4 a, a, b
-	//addx4 a, b, b
-	slli \arr, \ars, 2
-	add  \arr, \arr, \art
-	.endif
-	.endm
-#endif /* !XCHAL_HAVE_ADDX */
-
-/*----------------------------------------------------------------------
- *  addx8
- * 
- *  implements addx8 on machines that do not have it configured
- * 
- */
-
-#if !XCHAL_HAVE_ADDX
-	.macro addx8 arr, ars, art
-	.ifc \arr, \art
-	.ifc \arr, \ars
-	//addx8 a, a, a     (not common)
-	.err
-	.else
-	//addx8 a, b, a
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	add \arr, \ars, \art
-	.endif
-	.else
-	//addx8 a, b, c
-	//addx8 a, a, b
-	//addx8 a, b, b
-	slli \arr, \ars, 3
-	add  \arr, \arr, \art
-	.endif
-	.endm
-#endif /* !XCHAL_HAVE_ADDX */
-
-
-/*----------------------------------------------------------------------
- *  rfe_rfue
- * 
- *  Maps to RFUE on XEA1, and RFE on XEA2.  No mapping on XEAX.
- */
-
-#if XCHAL_HAVE_XEA1
-	.macro	rfe_rfue
-	rfue
-	.endm
-#elif XCHAL_HAVE_XEA2
-	.macro	rfe_rfue
-	rfe
-	.endm
-#endif
- 
-
-/*----------------------------------------------------------------------
- *  abi_entry
- * 
- *  Generate proper function entry sequence for the current ABI
- *  (windowed or call0).  Takes care of allocating stack space (up to 1kB)
- *  and saving the return PC, if necessary.  The corresponding abi_return
- *  macro does the corresponding stack deallocation and restoring return PC.
- *
- *  Parameters are:
- *
- *	locsize		Number of bytes to allocate on the stack
- *			for local variables (and for args to pass to
- *			callees, if any calls are made).  Defaults to zero.
- *			The macro rounds this up to a multiple of 16.
- *			NOTE:  large values are allowed (e.g. up to 1 GB).
- *
- *	callsize	Maximum call size made by this function.
- *			Leave zero (default) for leaf functions, i.e. if
- *			this function makes no calls to other functions.
- *			Otherwise must be set to 4, 8, or 12 according
- *			to whether the "largest" call made is a call[x]4,
- *			call[x]8, or call[x]12 (for call0 ABI, it makes
- *			no difference whether this is set to 4, 8 or 12,
- *			but it must be set to one of these values).
- *
- *  NOTE:  It is up to the caller to align the entry point, declare the
- *  function symbol, make it global, etc.
- *
- *  NOTE:  This macro relies on assembler relaxation for large values
- *  of locsize.  It might not work with the no-transform directive.
- *  NOTE:  For the call0 ABI, this macro ensures SP is allocated or
- *  de-allocated cleanly, i.e. without temporarily allocating too much
- *  (or allocating negatively!) due to addi relaxation.
- *
- *  NOTE:  Generating the proper sequence and register allocation for
- *  making calls in an ABI independent manner is a separate topic not
- *  covered by this macro.
- *
- *  NOTE:  To access arguments, you can't use a fixed offset from SP.
- *  The offset depends on the ABI, whether the function is leaf, etc.
- *  The simplest method is probably to use the .locsz symbol, which
- *  is set by this macro to the actual number of bytes allocated on
- *  the stack, in other words, to the offset from SP to the arguments.
- *  E.g. for a function whose arguments are all 32-bit integers, you
- *  can get the 7th and 8th arguments (1st and 2nd args stored on stack)
- *  using:
- *	l32i	a2, sp, .locsz
- *	l32i	a3, sp, .locsz+4
- *  (this example works as long as locsize is under L32I's offset limit
- *   of 1020 minus up to 48 bytes of ABI-specific stack usage;
- *   otherwise you might first need to do "addi a?, sp, .locsz"
- *   or similar sequence).
- *
- *  NOTE:  For call0 ABI, this macro (and abi_return) may clobber a9
- *  (a caller-saved register).
- *
- *  Examples:
- *		abi_entry
- *		abi_entry  5
- *		abi_entry  22, 8
- *		abi_entry  0, 4
- */
-
-	/*
-	 *  Compute .locsz and .callsz without emitting any instructions.
-	 *  Used by both abi_entry and abi_return.
-	 *  Assumes locsize >= 0.
-	 */
-	.macro	abi_entry_size locsize=0, callsize=0
-#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
-	.ifeq	\callsize
-	 .set	.callsz, 16
-	.else
-	 .ifeq	\callsize-4
-	  .set	.callsz, 16
-	 .else
-	  .ifeq	\callsize-8
-	   .set	.callsz, 32
-	  .else
-	   .ifeq \callsize-12
-	    .set .callsz, 48
-	   .else
-	    .error	"abi_entry: invalid call size \callsize"
-	   .endif
-	  .endif
-	 .endif
-	.endif
-	.set	.locsz, .callsz + ((\locsize + 15) & -16)
-#else
-	.set	.callsz, \callsize
-	.if	.callsz		/* if calls, need space for return PC */
-	 .set	.locsz, (\locsize + 4 + 15) & -16
-	.else
-	 .set	.locsz, (\locsize + 15) & -16
-	.endif
-#endif
-	.endm
-
-	.macro abi_entry locsize=0, callsize=0
-	.iflt	\locsize
-	 .error	"abi_entry: invalid negative size of locals (\locsize)"
-	.endif
-	abi_entry_size	\locsize, \callsize
-#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
-	.ifgt	.locsz - 32760	/* .locsz > 32760 (ENTRY's max range)? */
-	/*  Funky computation to try to have assembler use addmi efficiently if possible:  */
-	entry	sp, 0x7F00 + (.locsz & 0xF0)
-	addi	a12, sp, - ((.locsz & -0x100) - 0x7F00)
-	movsp	sp, a12
-	.else
-	entry	sp, .locsz
-	.endif
-#else
-	.if	.locsz
-	 .ifle	.locsz - 128	/* if locsz <= 128 */
-	addi	sp, sp, -.locsz
-	  .if	.callsz
-	s32i	a0, sp, .locsz - 4
-	  .endif
-	 .elseif  .callsz	/* locsz > 128, with calls: */
-	movi	a9, .locsz - 16		/* note: a9 is caller-saved */
-	addi	sp, sp, -16
-	s32i	a0, sp, 12
-	sub	sp, sp, a9
-	 .else			/* locsz > 128, no calls: */
-	movi	a9, .locsz
-	sub	sp, sp, a9
-	 .endif			/* end */
-	.endif
-#endif
-	.endm
-
-
-
-/*----------------------------------------------------------------------
- *  abi_return
- * 
- *  Generate proper function exit sequence for the current ABI
- *  (windowed or call0).  Takes care of freeing stack space and
- *  restoring the return PC, if necessary.
- *  NOTE:  This macro MUST be invoked following a corresponding
- *  abi_entry macro invocation.  For call0 ABI in particular,
- *  all stack and PC restoration are done according to the last
- *  abi_entry macro invoked before this macro in the assembly file.
- *
- *  Normally this macro takes no arguments.  However to allow
- *  for placing abi_return *before* abi_entry (as must be done
- *  for some highly optimized assembly), it optionally takes
- *  exactly the same arguments as abi_entry.
- */
-
-	.macro abi_return	locsize=-1, callsize=0
-	.ifge	\locsize
-	abi_entry_size	\locsize, \callsize
-	.endif
-#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
-	retw
-#else
-	.if	.locsz
-	 .iflt	.locsz - 128	/* if locsz < 128 */
-	  .if	.callsz
-	l32i	a0, sp, .locsz - 4
-	  .endif
-	addi	sp, sp, .locsz
-	 .elseif  .callsz	/* locsz >= 128, with calls: */
-	addi	a9, sp, .locsz - 16
-	l32i	a0, a9, 12
-	addi	sp, a9, 16
-	 .else			/* locsz >= 128, no calls: */
-	movi	a9, .locsz
-	add	sp, sp, a9
-	 .endif			/* end */
-	.endif
-	ret
-#endif
-	.endm
-
-
-/*
- * HW erratum fixes.
- */
-
-	.macro hw_erratum_487_fix
-#if defined XSHAL_ERRATUM_487_FIX
-	isync
-#endif
-	.endm
-
-
-#endif /*XTENSA_COREASM_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/corebits.h b/tools/sdk/include/esp32/xtensa/corebits.h
deleted file mode 100644
index 0ac0c8014c8..00000000000
--- a/tools/sdk/include/esp32/xtensa/corebits.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
- *
- * (In previous releases, these were defined in specreg.h, a generated file.
- *  This file is not generated, ie. it is processor configuration independent.)
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */
-
-/*
- * Copyright (c) 2005-2011 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_COREBITS_H
-#define XTENSA_COREBITS_H
-
-/*  EXCCAUSE register fields:  */
-#define EXCCAUSE_EXCCAUSE_SHIFT	0
-#define EXCCAUSE_EXCCAUSE_MASK	0x3F
-/*  EXCCAUSE register values:  */
-/*
- *  General Exception Causes
- *  (values of EXCCAUSE special register set by general exceptions,
- *   which vector to the user, kernel, or double-exception vectors).
- */
-#define EXCCAUSE_ILLEGAL		0	/* Illegal Instruction */
-#define EXCCAUSE_SYSCALL		1	/* System Call (SYSCALL instruction) */
-#define EXCCAUSE_INSTR_ERROR		2	/* Instruction Fetch Error */
-# define EXCCAUSE_IFETCHERROR		2	/* (backward compatibility macro, deprecated, avoid) */
-#define EXCCAUSE_LOAD_STORE_ERROR	3	/* Load Store Error */
-# define EXCCAUSE_LOADSTOREERROR	3	/* (backward compatibility macro, deprecated, avoid) */
-#define EXCCAUSE_LEVEL1_INTERRUPT	4	/* Level 1 Interrupt */
-# define EXCCAUSE_LEVEL1INTERRUPT	4	/* (backward compatibility macro, deprecated, avoid) */
-#define EXCCAUSE_ALLOCA			5	/* Stack Extension Assist (MOVSP instruction) for alloca */
-#define EXCCAUSE_DIVIDE_BY_ZERO		6	/* Integer Divide by Zero */
-#define EXCCAUSE_SPECULATION		7	/* Use of Failed Speculative Access (not implemented) */
-#define EXCCAUSE_PRIVILEGED		8	/* Privileged Instruction */
-#define EXCCAUSE_UNALIGNED		9	/* Unaligned Load or Store */
-/* Reserved				10..11 */
-#define EXCCAUSE_INSTR_DATA_ERROR	12	/* PIF Data Error on Instruction Fetch (RB-200x and later) */
-#define EXCCAUSE_LOAD_STORE_DATA_ERROR	13	/* PIF Data Error on Load or Store (RB-200x and later) */
-#define EXCCAUSE_INSTR_ADDR_ERROR	14	/* PIF Address Error on Instruction Fetch (RB-200x and later) */
-#define EXCCAUSE_LOAD_STORE_ADDR_ERROR	15	/* PIF Address Error on Load or Store (RB-200x and later) */
-#define EXCCAUSE_ITLB_MISS		16	/* ITLB Miss (no ITLB entry matches, hw refill also missed) */
-#define EXCCAUSE_ITLB_MULTIHIT		17	/* ITLB Multihit (multiple ITLB entries match) */
-#define EXCCAUSE_INSTR_RING		18	/* Ring Privilege Violation on Instruction Fetch */
-/* Reserved				19 */	/* Size Restriction on IFetch (not implemented) */
-#define EXCCAUSE_INSTR_PROHIBITED	20	/* Cache Attribute does not allow Instruction Fetch */
-/* Reserved				21..23 */
-#define EXCCAUSE_DTLB_MISS		24	/* DTLB Miss (no DTLB entry matches, hw refill also missed) */
-#define EXCCAUSE_DTLB_MULTIHIT		25	/* DTLB Multihit (multiple DTLB entries match) */
-#define EXCCAUSE_LOAD_STORE_RING	26	/* Ring Privilege Violation on Load or Store */
-/* Reserved				27 */	/* Size Restriction on Load/Store (not implemented) */
-#define EXCCAUSE_LOAD_PROHIBITED	28	/* Cache Attribute does not allow Load */
-#define EXCCAUSE_STORE_PROHIBITED	29	/* Cache Attribute does not allow Store */
-/* Reserved				30..31 */
-#define EXCCAUSE_CP_DISABLED(n)		(32+(n))	/* Access to Coprocessor 'n' when disabled */
-#define EXCCAUSE_CP0_DISABLED		32	/* Access to Coprocessor 0 when disabled */
-#define EXCCAUSE_CP1_DISABLED		33	/* Access to Coprocessor 1 when disabled */
-#define EXCCAUSE_CP2_DISABLED		34	/* Access to Coprocessor 2 when disabled */
-#define EXCCAUSE_CP3_DISABLED		35	/* Access to Coprocessor 3 when disabled */
-#define EXCCAUSE_CP4_DISABLED		36	/* Access to Coprocessor 4 when disabled */
-#define EXCCAUSE_CP5_DISABLED		37	/* Access to Coprocessor 5 when disabled */
-#define EXCCAUSE_CP6_DISABLED		38	/* Access to Coprocessor 6 when disabled */
-#define EXCCAUSE_CP7_DISABLED		39	/* Access to Coprocessor 7 when disabled */
-/* Reserved				40..63 */
-
-/*  PS register fields:  */
-#define PS_WOE_SHIFT		18
-#define PS_WOE_MASK		0x00040000
-#define PS_WOE			PS_WOE_MASK
-#define PS_CALLINC_SHIFT	16
-#define PS_CALLINC_MASK		0x00030000
-#define PS_CALLINC(n)		(((n)&3)<<PS_CALLINC_SHIFT)	/* n = 0..3 */
-#define PS_OWB_SHIFT		8
-#define PS_OWB_MASK		0x00000F00
-#define PS_OWB(n)		(((n)&15)<<PS_OWB_SHIFT)	/* n = 0..15 (or 0..7) */
-#define PS_RING_SHIFT		6
-#define PS_RING_MASK		0x000000C0
-#define PS_RING(n)		(((n)&3)<<PS_RING_SHIFT)	/* n = 0..3 */
-#define PS_UM_SHIFT		5
-#define PS_UM_MASK		0x00000020
-#define PS_UM			PS_UM_MASK
-#define PS_EXCM_SHIFT		4
-#define PS_EXCM_MASK		0x00000010
-#define PS_EXCM			PS_EXCM_MASK
-#define PS_INTLEVEL_SHIFT	0
-#define PS_INTLEVEL_MASK	0x0000000F
-#define PS_INTLEVEL(n)		((n)&PS_INTLEVEL_MASK)		/* n = 0..15 */
-/*  Backward compatibility (deprecated):  */
-#define PS_PROGSTACK_SHIFT	PS_UM_SHIFT
-#define PS_PROGSTACK_MASK	PS_UM_MASK
-#define PS_PROG_SHIFT		PS_UM_SHIFT
-#define PS_PROG_MASK		PS_UM_MASK
-#define PS_PROG			PS_UM
-
-/*  DBREAKCn register fields:  */
-#define DBREAKC_MASK_SHIFT		0
-#define DBREAKC_MASK_MASK		0x0000003F
-#define DBREAKC_LOADBREAK_SHIFT		30
-#define DBREAKC_LOADBREAK_MASK		0x40000000
-#define DBREAKC_STOREBREAK_SHIFT	31
-#define DBREAKC_STOREBREAK_MASK		0x80000000
-
-/*  DEBUGCAUSE register fields:  */
-#define DEBUGCAUSE_DEBUGINT_SHIFT	5
-#define DEBUGCAUSE_DEBUGINT_MASK	0x20	/* debug interrupt */
-#define DEBUGCAUSE_BREAKN_SHIFT		4
-#define DEBUGCAUSE_BREAKN_MASK		0x10	/* BREAK.N instruction */
-#define DEBUGCAUSE_BREAK_SHIFT		3
-#define DEBUGCAUSE_BREAK_MASK		0x08	/* BREAK instruction */
-#define DEBUGCAUSE_DBREAK_SHIFT		2
-#define DEBUGCAUSE_DBREAK_MASK		0x04	/* DBREAK match */
-#define DEBUGCAUSE_IBREAK_SHIFT		1
-#define DEBUGCAUSE_IBREAK_MASK		0x02	/* IBREAK match */
-#define DEBUGCAUSE_ICOUNT_SHIFT		0
-#define DEBUGCAUSE_ICOUNT_MASK		0x01	/* ICOUNT would increment to zero */
-
-/*  MESR register fields:  */
-#define MESR_MEME		0x00000001	/* memory error */
-#define MESR_MEME_SHIFT		0
-#define MESR_DME		0x00000002	/* double memory error */
-#define MESR_DME_SHIFT		1
-#define MESR_RCE		0x00000010	/* recorded memory error */
-#define MESR_RCE_SHIFT		4
-#define MESR_LCE		
-#define MESR_LCE_SHIFT		?
-#define MESR_LCE_L
-#define MESR_ERRENAB		0x00000100
-#define MESR_ERRENAB_SHIFT	8
-#define MESR_ERRTEST		0x00000200
-#define MESR_ERRTEST_SHIFT	9
-#define MESR_DATEXC		0x00000400
-#define MESR_DATEXC_SHIFT	10
-#define MESR_INSEXC		0x00000800
-#define MESR_INSEXC_SHIFT	11
-#define MESR_WAYNUM_SHIFT	16
-#define MESR_ACCTYPE_SHIFT	20
-#define MESR_MEMTYPE_SHIFT	24
-#define MESR_ERRTYPE_SHIFT	30
-
-/*  MEMCTL register fields:  */
-#define MEMCTL_SNOOP_EN_SHIFT	1
-#define MEMCTL_SNOOP_EN		0x02	/* enable snoop responses (default 0) */
-#define MEMCTL_L0IBUF_EN_SHIFT	0
-#define MEMCTL_L0IBUF_EN	0x01	/* enable loop instr. buffer (default 1) */
-#define MEMCTL_INV_EN_SHIFT	23
-#define MEMCTL_INV_EN		0x00800000	/* invalidate cache ways being increased */
-#define MEMCTL_DCWU_SHIFT	8
-#define MEMCTL_DCWU_BITS	5
-#define MEMCTL_DCWA_SHIFT	13
-#define MEMCTL_DCWA_BITS	5
-#define MEMCTL_ICWU_SHIFT	18
-#define MEMCTL_ICWU_BITS	5
-#define MEMCTL_DCWU_MASK	0x00001F00	/* Bits  8-12 dcache ways in use */
-#define MEMCTL_DCWA_MASK	0x0003E000	/* Bits 13-17 dcache ways allocatable */
-#define MEMCTL_ICWU_MASK	0x007C0000	/* Bits 18-22 icache ways in use */
-#define MEMCTL_DCWU_CLR_MASK	~(MEMCTL_DCWU_MASK)
-#define MEMCTL_DCWA_CLR_MASK	~(MEMCTL_DCWA_MASK)
-#define MEMCTL_ICWU_CLR_MASK	~(MEMCTL_ICWU_MASK)
-#define MEMCTL_DCW_CLR_MASK	(MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
-#define MEMCTL_IDCW_CLR_MASK	(MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
-
-
-#endif /*XTENSA_COREBITS_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/hal.h b/tools/sdk/include/esp32/xtensa/hal.h
deleted file mode 100644
index d4d95d9fe74..00000000000
--- a/tools/sdk/include/esp32/xtensa/hal.h
+++ /dev/null
@@ -1,1024 +0,0 @@
-/*
-   xtensa/hal.h -- contains a definition of the Core HAL interface
-
-   All definitions in this header file are independent of any specific
-   Xtensa processor configuration.  Thus software (eg. OS, application,
-   etc) can include this header file and be compiled into configuration-
-   independent objects that can be distributed and eventually linked
-   to the HAL library (libhal.a) to create a configuration-specific
-   final executable.
-
-   Certain definitions, however, are release/version-specific -- such as
-   the XTHAL_RELEASE_xxx macros (or additions made in later versions).
-
-
-   $Id: //depot/rel/Eaglenest/Xtensa/OS/target-os-src/hal.h.tpp#4 $
-
-   Copyright (c) 1999-2014 Cadence Design Systems, Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef XTENSA_HAL_H
-#define XTENSA_HAL_H
-
-
-/****************************************************************************
-	    Definitions Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-
-/*----------------------------------------------------------------------
-	   Constant Definitions  (shared with assembly)
-  ----------------------------------------------------------------------*/
-
-/*
- *  Software (Xtensa Tools) version information.  Not configuration-specific!
- *
- *  NOTE:  "release" is a misnomer here, these are really product "version"
- *	numbers.  A "release" is a collection of product versions
- *	made available at once (together) to customers.
- *	In the past, release and version names all matched in T####.# form,
- *	making the distinction irrelevant.  This is no longer the case.
- */
-#define XTHAL_RELEASE_MAJOR	11000
-#define XTHAL_RELEASE_MINOR	3
-#define XTHAL_RELEASE_NAME	"11.0.3"
-#define XTHAL_REL_11	1
-#define XTHAL_REL_11_0	1
-#define XTHAL_REL_11_0_3	1
-
-/*  HAL version numbers (these names are for backward compatibility):  */
-#define XTHAL_MAJOR_REV		XTHAL_RELEASE_MAJOR
-#define XTHAL_MINOR_REV		XTHAL_RELEASE_MINOR
-/*
- *  A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV:
- *
- *	SW Version	MAJOR	MINOR		Comment
- *	=======		=====	=====		=======
- *	T1015.n		n/a	n/a		(HAL not yet available)
- *	T1020.{0,1,2}	0	1		(HAL beta)
- *	T1020.{3,4}	0	2		First release.
- *	T1020.n (n>4)	0	2 or >3		(TBD)
- *	T1030.0		0	1		(HAL beta)
- *	T1030.{1,2}	0	3		Equivalent to first release.
- *	T1030.n (n>=3)	0	>= 3		(TBD)
- *	T1040.n		1040	n		Full CHAL available from T1040.2
- *	T1050.n		1050	n		.
- *	6.0.n		6000	n		Xtensa Tools v6   (RA-200x.n)
- *	7.0.n		7000	n		Xtensa Tools v7   (RB-200x.n)
- *	7.1.n		7010	n		Xtensa Tools v7.1 (RB-200x.(n+2))
- *	8.0.n		8000	n		Xtensa Tools v8   (RC-20xx.n)
- *	9.0.n		9000	n		Xtensa Tools v9   (RD-201x.n)
- *	10.0.n		10000	n		Xtensa Tools v10  (RE-201x.n)
- *
- *
- *  Note:  there is a distinction between the software version with
- *  which something is compiled (accessible using XTHAL_RELEASE_* macros)
- *  and the software version with which the HAL library was compiled
- *  (accessible using Xthal_release_* global variables).  This
- *  distinction is particularly relevant for vendors that distribute
- *  configuration-independent binaries (eg. an OS), where their customer
- *  might link it with a HAL of a different Xtensa software version.
- *  In this case, it may be appropriate for the OS to verify at run-time
- *  whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
- *  [Guidelines as to which version is compatible with which are not
- *  currently provided explicitly, but might be inferred from reading
- *  OSKit documentation for all releases -- compatibility is also highly
- *  dependent on which HAL features are used.  Each version is usually
- *  backward compatible, with very few exceptions if any.]
- */
-
-/*  Version comparison operators (among major/minor pairs):  */
-#define XTHAL_REL_GE(maja,mina, majb,minb)	((maja) > (majb) || \
-						 ((maja) == (majb) && (mina) >= (minb)))
-#define XTHAL_REL_GT(maja,mina, majb,minb)	((maja) > (majb) || \
-						 ((maja) == (majb) && (mina) > (minb)))
-#define XTHAL_REL_LE(maja,mina, majb,minb)	((maja) < (majb) || \
-						 ((maja) == (majb) && (mina) <= (minb)))
-#define XTHAL_REL_LT(maja,mina, majb,minb)	((maja) < (majb) || \
-						 ((maja) == (majb) && (mina) < (minb)))
-#define XTHAL_REL_EQ(maja,mina, majb,minb)	((maja) == (majb) && (mina) == (minb))
-
-/*  Fuzzy (3-way) logic operators:  */
-#define XTHAL_MAYBE		-1	/* 0=NO, 1=YES, -1=MAYBE */
-#define XTHAL_FUZZY_AND(a,b)	(((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE)
-#define XTHAL_FUZZY_OR(a,b)	(((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE)
-#define XTHAL_FUZZY_NOT(a)	(((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE)
-
-
-/*
- *  Architectural limit, independent of configuration:
- */
-#define XTHAL_MAX_CPS		8	/* max number of coprocessors (0..7) */
-
-/*  Misc:  */
-#define XTHAL_LITTLEENDIAN		0
-#define XTHAL_BIGENDIAN			1
-
-
-
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*----------------------------------------------------------------------
-				HAL
-  ----------------------------------------------------------------------*/
-
-/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
-extern const unsigned int Xthal_rev_no;
-
-
-/*----------------------------------------------------------------------
-			Optional/Custom Processor State
-  ----------------------------------------------------------------------*/
-
-/* save & restore the extra processor state */
-extern void xthal_save_extra(void *base);
-extern void xthal_restore_extra(void *base);
-
-extern void xthal_save_cpregs(void *base, int);
-extern void xthal_restore_cpregs(void *base, int);
-/* versions specific to each coprocessor id */
-extern void xthal_save_cp0(void *base);
-extern void xthal_save_cp1(void *base);
-extern void xthal_save_cp2(void *base);
-extern void xthal_save_cp3(void *base);
-extern void xthal_save_cp4(void *base);
-extern void xthal_save_cp5(void *base);
-extern void xthal_save_cp6(void *base);
-extern void xthal_save_cp7(void *base);
-extern void xthal_restore_cp0(void *base);
-extern void xthal_restore_cp1(void *base);
-extern void xthal_restore_cp2(void *base);
-extern void xthal_restore_cp3(void *base);
-extern void xthal_restore_cp4(void *base);
-extern void xthal_restore_cp5(void *base);
-extern void xthal_restore_cp6(void *base);
-extern void xthal_restore_cp7(void *base);
-/* pointers to each of the functions above */
-extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS];
-extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS];
-/* similarly for non-windowed ABI (may be same or different) */
-extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS];
-extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS];
-
-/*extern void xthal_save_all_extra(void *base);*/
-/*extern void xthal_restore_all_extra(void *base);*/
-
-/* space for processor state */
-extern const unsigned int Xthal_extra_size;
-extern const unsigned int Xthal_extra_align;
-extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
-extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
-extern const unsigned int Xthal_all_extra_size;
-extern const unsigned int Xthal_all_extra_align;
-/* coprocessor names */
-extern const char * const Xthal_cp_names[XTHAL_MAX_CPS];
-
-/* initialize the extra processor */
-/*extern void xthal_init_extra(void);*/
-/* initialize the TIE coprocessor */
-/*extern void xthal_init_cp(int);*/
-
-/* initialize the extra processor */
-extern void xthal_init_mem_extra(void *);
-/* initialize the TIE coprocessor */
-extern void xthal_init_mem_cp(void *, int);
-
-/* the number of TIE coprocessors contiguous from zero (for Tor2) */
-extern const unsigned int Xthal_num_coprocessors;
-
-/* actual number of coprocessors */
-extern const unsigned char Xthal_cp_num;
-/* index of highest numbered coprocessor, plus one */
-extern const unsigned char Xthal_cp_max;
-/* index of highest allowed coprocessor number, per cfg, plus one */
-/*extern const unsigned char Xthal_cp_maxcfg;*/
-/* bitmask of which coprocessors are present */
-extern const unsigned int  Xthal_cp_mask;
-
-/* read & write extra state register */
-/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
-/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
-
-/* read & write a TIE coprocessor register */
-/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
-/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
-
-/* return coprocessor number based on register */
-/*extern int xthal_which_cp(unsigned reg);*/
-
-
-/*----------------------------------------------------------------------
-   				Register Windows
-  ----------------------------------------------------------------------*/
-
-/* number of registers in register window */
-extern const unsigned int  Xthal_num_aregs;
-extern const unsigned char Xthal_num_aregs_log2;
-
-
-/*----------------------------------------------------------------------
-   				Cache
-  ----------------------------------------------------------------------*/
-
-/* size of the cache lines in log2(bytes) */
-extern const unsigned char Xthal_icache_linewidth;
-extern const unsigned char Xthal_dcache_linewidth;
-/* size of the cache lines in bytes (2^linewidth) */
-extern const unsigned short Xthal_icache_linesize;
-extern const unsigned short Xthal_dcache_linesize;
-
-/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
-extern const unsigned int  Xthal_icache_size;
-extern const unsigned int  Xthal_dcache_size;
-/* cache features */
-extern const unsigned char Xthal_dcache_is_writeback;
-
-/* invalidate the caches */
-
-extern void xthal_icache_region_invalidate( void *addr, unsigned size );
-extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
-# ifndef XTHAL_USE_CACHE_MACROS
-extern void xthal_icache_line_invalidate(void *addr);
-extern void xthal_dcache_line_invalidate(void *addr);
-# endif
-/* write dirty data back */
-extern void xthal_dcache_region_writeback( void *addr, unsigned size );
-# ifndef XTHAL_USE_CACHE_MACROS
-extern void xthal_dcache_line_writeback(void *addr);
-# endif
-/* write dirty data back and invalidate */
-extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
-# ifndef XTHAL_USE_CACHE_MACROS
-extern void xthal_dcache_line_writeback_inv(void *addr);
-/* sync icache and memory */
-extern void xthal_icache_sync( void );
-/* sync dcache and memory */
-extern void xthal_dcache_sync( void );
-#endif
-
-/* get number of icache ways enabled */
-extern unsigned int xthal_icache_get_ways(void);
-/* set number of icache ways enabled */
-extern void xthal_icache_set_ways(unsigned int ways);
-/* get number of dcache ways enabled */
-extern unsigned int xthal_dcache_get_ways(void);
-/* set number of dcache ways enabled */
-extern void xthal_dcache_set_ways(unsigned int ways);
-
-/* coherency (low-level -- not normally called directly) */
-extern void xthal_cache_coherence_on( void );
-extern void xthal_cache_coherence_off( void );
-/* coherency (high-level) */
-extern void xthal_cache_coherence_optin( void );
-extern void xthal_cache_coherence_optout( void );
-
-/*
- *  Cache prefetch control.
- *  The parameter to xthal_set_cache_prefetch() contains both
- *  a PREFCTL register value and a mask of which bits to actually modify.
- *  This allows easily combining field macros (below) by ORing,
- *  leaving unspecified fields unmodified.
- *
- *  For backward compatibility with the older version of this routine
- *  (that took 15-bit value and mask in a 32-bit parameter, for pre-RF
- *  cores with only the lower 15 bits of PREFCTL defined), the 32-bit
- *  value and mask are staggered as follows in a 64-bit parameter:
- *	param[63:48] are PREFCTL[31:16]		if param[31] is set
- *	param[47:32] are mask[31:16]		if param[31] is set
- *	param[31]    is set if mask is used, 0 if not
- *	param[31:16] are mask[15:0]		if param[31] is set
- *	param[31:16] are PREFCTL[31:16]		if param[31] is clear
- *	param[15:0]  are PREFCTL[15:0]
- *
- *  Limitation:  PREFCTL register bit 31 cannot be set without masking,
- *  and bit 15 must always be set when using masking, so it is hoped that
- *  these two bits will remain reserved, read-as-zero in PREFCTL.
- */
-#define XTHAL_PREFETCH_ENABLE		-1	/* enable inst+data prefetch */
-#define XTHAL_PREFETCH_DISABLE		0xFFFF0000 /* disab inst+data prefetch*/
-#define XTHAL_DCACHE_PREFETCH(n)	(0x800F0000+((n)&0xF))   /* data-side */
-#define XTHAL_DCACHE_PREFETCH_OFF	XTHAL_DCACHE_PREFETCH(0) /* disable */
-#define XTHAL_DCACHE_PREFETCH_LOW	XTHAL_DCACHE_PREFETCH(4) /* less aggr.*/
-#define XTHAL_DCACHE_PREFETCH_MEDIUM	XTHAL_DCACHE_PREFETCH(5) /* mid aggr. */
-#define XTHAL_DCACHE_PREFETCH_HIGH	XTHAL_DCACHE_PREFETCH(8) /* more aggr.*/
-#define XTHAL_DCACHE_PREFETCH_L1_OFF	0x90000000	/* to prefetch buffers*/
-#define XTHAL_DCACHE_PREFETCH_L1	0x90001000	/* direct to L1 dcache*/
-#define XTHAL_ICACHE_PREFETCH(n)	(0x80F00000+(((n)&0xF)<<4)) /* i-side */
-#define XTHAL_ICACHE_PREFETCH_OFF	XTHAL_ICACHE_PREFETCH(0) /* disable */
-#define XTHAL_ICACHE_PREFETCH_LOW	XTHAL_ICACHE_PREFETCH(4) /* less aggr.*/
-#define XTHAL_ICACHE_PREFETCH_MEDIUM	XTHAL_ICACHE_PREFETCH(5) /* mid aggr. */
-#define XTHAL_ICACHE_PREFETCH_HIGH	XTHAL_ICACHE_PREFETCH(8) /* more aggr.*/
-#define XTHAL_ICACHE_PREFETCH_L1_OFF	0xA0000000	/* (not implemented) */
-#define XTHAL_ICACHE_PREFETCH_L1	0xA0002000	/* (not implemented) */
-#define _XTHAL_PREFETCH_BLOCKS(n)	((n)<0?0:(n)<5?(n):(n)<15?((n)>>1)+2:9)
-#define XTHAL_PREFETCH_BLOCKS(n)	(0x0000000F80000000ULL + \
-					(((unsigned long long)_XTHAL_PREFETCH_BLOCKS(n))<<48))
-
-extern int  xthal_get_cache_prefetch( void );
-extern int  xthal_set_cache_prefetch( int );
-extern int  xthal_set_cache_prefetch_long( unsigned long long );
-/*  Only use the new extended function from now on:  */
-#define xthal_set_cache_prefetch	xthal_set_cache_prefetch_long
-#define xthal_set_cache_prefetch_nw	xthal_set_cache_prefetch_long_nw
-
-
-/*----------------------------------------------------------------------
-   				Debug
-  ----------------------------------------------------------------------*/
-
-/*  1 if debug option configured, 0 if not:  */
-extern const int Xthal_debug_configured;
-
-/*  Set (plant) and remove software breakpoint, both synchronizing cache:  */
-extern unsigned int xthal_set_soft_break(void *addr);
-extern void         xthal_remove_soft_break(void *addr, unsigned int);
-
-
-/*----------------------------------------------------------------------
-   				Disassembler
-  ----------------------------------------------------------------------*/
-
-/*  Max expected size of the return buffer for a disassembled instruction (hint only):  */
-#define XTHAL_DISASM_BUFSIZE	80
-
-/*  Disassembly option bits for selecting what to return:  */
-#define XTHAL_DISASM_OPT_ADDR	0x0001	/* display address */
-#define XTHAL_DISASM_OPT_OPHEX	0x0002	/* display opcode bytes in hex */
-#define XTHAL_DISASM_OPT_OPCODE	0x0004	/* display opcode name (mnemonic) */
-#define XTHAL_DISASM_OPT_PARMS	0x0008	/* display parameters */
-#define XTHAL_DISASM_OPT_ALL	0x0FFF	/* display everything */
-
-/* routine to get a string for the disassembled instruction */
-extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
-		       char *buffer, unsigned buflen, unsigned options );
-
-/* routine to get the size of the next instruction. Returns 0 for
-   illegal instruction */
-extern int xthal_disassemble_size( unsigned char *instr_buf );
-
-
-/*----------------------------------------------------------------------
-			Instruction/Data RAM/ROM Access
-  ----------------------------------------------------------------------*/
-
-extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
-extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
-
-
-/*----------------------------------------------------------------------
-                           MP Synchronization
-  ----------------------------------------------------------------------*/
-
-extern int      xthal_compare_and_set( int *addr, int test_val, int compare_val );
-
-/*extern const char  Xthal_have_s32c1i;*/
-
-
-/*----------------------------------------------------------------------
-                             Miscellaneous
-  ----------------------------------------------------------------------*/
-
-extern const unsigned int  Xthal_release_major;
-extern const unsigned int  Xthal_release_minor;
-extern const char * const  Xthal_release_name;
-extern const char * const  Xthal_release_internal;
-
-extern const unsigned char Xthal_memory_order;
-extern const unsigned char Xthal_have_windowed;
-extern const unsigned char Xthal_have_density;
-extern const unsigned char Xthal_have_booleans;
-extern const unsigned char Xthal_have_loops;
-extern const unsigned char Xthal_have_nsa;
-extern const unsigned char Xthal_have_minmax;
-extern const unsigned char Xthal_have_sext;
-extern const unsigned char Xthal_have_clamps;
-extern const unsigned char Xthal_have_mac16;
-extern const unsigned char Xthal_have_mul16;
-extern const unsigned char Xthal_have_fp;
-extern const unsigned char Xthal_have_speculation;
-extern const unsigned char Xthal_have_threadptr;
-
-extern const unsigned char Xthal_have_pif;
-extern const unsigned short Xthal_num_writebuffer_entries;
-
-extern const unsigned int  Xthal_build_unique_id;
-/*  Version info for hardware targeted by software upgrades:  */
-extern const unsigned int  Xthal_hw_configid0;
-extern const unsigned int  Xthal_hw_configid1;
-extern const unsigned int  Xthal_hw_release_major;
-extern const unsigned int  Xthal_hw_release_minor;
-extern const char * const  Xthal_hw_release_name;
-extern const char * const  Xthal_hw_release_internal;
-
-/*  Clear any remnant code-dependent state (i.e. clear loop count regs).  */
-extern void	xthal_clear_regcached_code( void );
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
-
-
-
-
-
-/****************************************************************************
-    Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-	   Constant Definitions  (shared with assembly)
-  ----------------------------------------------------------------------*/
-
-/*
- *  Architectural limits, independent of configuration.
- *  Note that these are ISA-defined limits, not micro-architecture implementation
- *  limits enforced by the Xtensa Processor Generator (which may be stricter than
- *  these below).
- */
-#define XTHAL_MAX_INTERRUPTS	32	/* max number of interrupts (0..31) */
-#define XTHAL_MAX_INTLEVELS	16	/* max number of interrupt levels (0..15) */
-					/* (as of T1040, implementation limit is 7: 0..6) */
-#define XTHAL_MAX_TIMERS	4	/* max number of timers (CCOMPARE0..CCOMPARE3) */
-					/* (as of T1040, implementation limit is 3: 0..2) */
-
-/*  Interrupt types:  */
-#define XTHAL_INTTYPE_UNCONFIGURED	0
-#define XTHAL_INTTYPE_SOFTWARE		1
-#define XTHAL_INTTYPE_EXTERN_EDGE	2
-#define XTHAL_INTTYPE_EXTERN_LEVEL	3
-#define XTHAL_INTTYPE_TIMER		4
-#define XTHAL_INTTYPE_NMI		5
-#define XTHAL_INTTYPE_WRITE_ERROR	6
-#define XTHAL_INTTYPE_PROFILING		7
-#define XTHAL_MAX_INTTYPES		8	/* number of interrupt types */
-
-/*  Timer related:  */
-#define XTHAL_TIMER_UNCONFIGURED	-1	/* Xthal_timer_interrupt[] value for non-existent timers */
-#define XTHAL_TIMER_UNASSIGNED	XTHAL_TIMER_UNCONFIGURED	/* (for backwards compatibility only) */
-
-/*  Local Memory ECC/Parity:  */
-#define XTHAL_MEMEP_PARITY	1
-#define XTHAL_MEMEP_ECC		2
-/*  Flags parameter to xthal_memep_inject_error():  */
-#define XTHAL_MEMEP_F_LOCAL		0	/* local memory (default) */
-#define XTHAL_MEMEP_F_DCACHE_DATA	4	/* data cache data */
-#define XTHAL_MEMEP_F_DCACHE_TAG	5	/* data cache tag */
-#define XTHAL_MEMEP_F_ICACHE_DATA	6	/* instruction cache data */
-#define XTHAL_MEMEP_F_ICACHE_TAG	7	/* instruction cache tag */
-#define XTHAL_MEMEP_F_CORRECTABLE	16	/* inject correctable error
-						   (default is non-corr.) */
-
-
-/*  Access Mode bits (tentative):  */	/* bit abbr unit short_name       PPC equ - Description */
-#define XTHAL_AMB_EXCEPTION	0	/* 001 E EX fls: EXception        none
-					   exception on any access (aka "illegal") */
-#define XTHAL_AMB_HITCACHE	1	/* 002 C CH fls: use Cache on Hit ~(I CI)
-					   [or H HC]  way from tag match;
-					   [or U UC] (ISA: same except Isolate case) */
-#define XTHAL_AMB_ALLOCATE	2	/* 004 A AL fl?: ALlocate         none
-					   [or F FI fill] refill cache on miss, way from LRU
-					   (ISA: Read/Write Miss Refill) */
-#define XTHAL_AMB_WRITETHRU	3	/* 008 W WT --s: WriteThrough     W WT
-					   store immediately to memory (ISA: same) */
-#define XTHAL_AMB_ISOLATE	4	/* 010 I IS fls: ISolate          none
-					   use cache regardless of hit-vs-miss,
-					   way from vaddr (ISA: use-cache-on-miss+hit) */
-#define XTHAL_AMB_GUARD		5	/* 020 G GU ?l?: GUard            G *
-					   non-speculative; spec/replay refs not permitted */
-#define XTHAL_AMB_COHERENT	6	/* 040 M MC ?ls: Mem/MP Coherent  M
-					   on read, other CPU/bus-master may need to supply data;
-					   on write, maybe redirect to or flush other CPU dirty line; etc */
-#if 0
-#define XTHAL_AMB_BUFFERABLE	x	/* 000 B BU --s: BUfferable       ?
-					   write response may return earlier than from final destination */
-#define XTHAL_AMB_ORDERED	x	/* 000 O OR fls: ORdered          G *
-					   mem accesses cannot be out of order */
-#define XTHAL_AMB_FUSEWRITES	x	/* 000 F FW --s: FuseWrites       none
-					   allow combining/merging/coalescing multiple writes
-					   (to same datapath data unit) into one
-					   (implied by writeback) */
-#define XTHAL_AMB_TRUSTED	x	/* 000 T TR ?l?: TRusted          none
-					   memory will not bus error (if it does,
-					   handle as fatal imprecise interrupt) */
-#define XTHAL_AMB_PREFETCH	x	/* 000 P PR fl?: PRefetch         none
-					   on refill, read line+1 into prefetch buffers */
-#define XTHAL_AMB_STREAM	x	/* 000 S ST ???: STreaming        none
-					   access one of N stream buffers */
-#endif /*0*/
-
-#define XTHAL_AM_EXCEPTION	(1<<XTHAL_AMB_EXCEPTION)
-#define XTHAL_AM_HITCACHE	(1<<XTHAL_AMB_HITCACHE)
-#define XTHAL_AM_ALLOCATE	(1<<XTHAL_AMB_ALLOCATE)
-#define XTHAL_AM_WRITETHRU	(1<<XTHAL_AMB_WRITETHRU)
-#define XTHAL_AM_ISOLATE	(1<<XTHAL_AMB_ISOLATE)
-#define XTHAL_AM_GUARD		(1<<XTHAL_AMB_GUARD)
-#define XTHAL_AM_COHERENT	(1<<XTHAL_AMB_COHERENT)
-#if 0
-#define XTHAL_AM_BUFFERABLE	(1<<XTHAL_AMB_BUFFERABLE)
-#define XTHAL_AM_ORDERED	(1<<XTHAL_AMB_ORDERED)
-#define XTHAL_AM_FUSEWRITES	(1<<XTHAL_AMB_FUSEWRITES)
-#define XTHAL_AM_TRUSTED	(1<<XTHAL_AMB_TRUSTED)
-#define XTHAL_AM_PREFETCH	(1<<XTHAL_AMB_PREFETCH)
-#define XTHAL_AM_STREAM		(1<<XTHAL_AMB_STREAM)
-#endif /*0*/
-
-/*
- *  Allowed Access Modes (bit combinations).
- *
- *  Columns are:
- *  "FOGIWACE"
- *	Access mode bits (see XTHAL_AMB_xxx above).
- *	<letter> = bit is set
- *	'-'      = bit is clear
- *	'.'      = bit is irrelevant / don't care, as follows:
- *			E=1 makes all others irrelevant
- *			W,F relevant only for stores
- *  "2345"
- *	Indicates which Xtensa releases support the corresponding
- *	access mode.  Releases for each character column are:
- *		2 = prior to T1020.2:   T1015 (V1.5), T1020.0, T1020.1
- *		3 = T1020.2 and later:  T1020.2+, T1030
- *		4 = T1040
- *		5 = T1050 (maybe), LX1, LX2, LX2.1
- *		7 = LX2.2
- *		8 = LX3, LX4
- *		9 = LX5
- *	And the character column contents are:
- *		<number> = supported by release(s)
- *		"." = unsupported by release(s)
- *		"?" = support unknown
- */
-						/* foMGIWACE 2345789 */
-/*  For instruction fetch:  */
-#define XTHAL_FAM_EXCEPTION		0x001	/* ........E 2345789 exception */
-/*efine XTHAL_FAM_ISOLATE*/	      /*0x012*/	/* .---I.-C- ....... isolate */
-#define XTHAL_FAM_BYPASS		0x000	/* .----.--- 2345789 bypass */
-/*efine XTHAL_FAM_NACACHED*/	      /*0x002*/	/* .----.-C- ....... cached no-allocate (frozen) */
-#define XTHAL_FAM_CACHED		0x006	/* .----.AC- 2345789 cached */
-/*  For data load:  */
-#define XTHAL_LAM_EXCEPTION		0x001	/* ........E 2345789 exception */
-#define XTHAL_LAM_ISOLATE		0x012	/* .---I.-C- 2345789 isolate */
-#define XTHAL_LAM_BYPASS		0x000	/* .O---.--- 2...... bypass speculative */
-#define XTHAL_LAM_BYPASSG		0x020	/* .O-G-.--- .345789 bypass guarded */
-#define XTHAL_LAM_CACHED_NOALLOC	0x002	/* .O---.-C- 2345789 cached no-allocate speculative */
-#define XTHAL_LAM_NACACHED		XTHAL_LAM_CACHED_NOALLOC
-#define XTHAL_LAM_NACACHEDG		0x022	/* .O-G-.-C- .?..... cached no-allocate guarded */
-#define XTHAL_LAM_CACHED		0x006	/* .----.AC- 2345789 cached speculative */
-#define XTHAL_LAM_COHCACHED		0x046	/* .-M--.AC- ....*89 cached speculative MP-coherent */
-/*  For data store:  */
-#define XTHAL_SAM_EXCEPTION		0x001	/* ........E 2345789 exception */
-#define XTHAL_SAM_ISOLATE		0x032	/* .--GI--C- 2345789 isolate */
-#define XTHAL_SAM_BYPASS		0x028	/* -O-G-W--- 2345789 bypass */
-#define XTHAL_SAM_WRITETHRU		0x02A	/* -O-G-W-C- 2345789 writethrough */
-/*efine XTHAL_SAM_WRITETHRU_ALLOC*/   /*0x02E*/	/* -O-G-WAC- ....... writethrough allocate */
-#define XTHAL_SAM_WRITEBACK		0x026	/* F--G--AC- ...5789 writeback */
-#define XTHAL_SAM_WRITEBACK_NOALLOC	0x022	/* ?--G---C- .....89 writeback no-allocate */
-#define XTHAL_SAM_COHWRITEBACK		0x066	/* F-MG--AC- ....*89 writeback MP-coherent */
-/*  For PIF attributes:  */			/* -PIwrWCBUUUU ...9 */
-#define XTHAL_PAM_BYPASS		0x000	/* xxx00000xxxx ...9 bypass non-bufferable */
-#define XTHAL_PAM_BYPASS_BUF		0x010	/* xxx0000bxxxx ...9 bypass */
-#define XTHAL_PAM_CACHED_NOALLOC	0x030	/* xxx0001bxxxx ...9 cached no-allocate */
-#define XTHAL_PAM_WRITETHRU		0x0B0	/* xxx0101bxxxx ...9 writethrough (WT) */
-#define XTHAL_PAM_WRITEBACK_NOALLOC	0x0F0	/* xxx0111bxxxx ...9 writeback no-alloc (WBNA) */
-#define XTHAL_PAM_WRITEBACK		0x1F0	/* xxx1111bxxxx ...9 writeback (WB) */
-/*efine XTHAL_PAM_NORMAL*/	      /*0x050*/	/* xxx0010bxxxx .... (unimplemented) */
-/*efine XTHAL_PAM_WRITETHRU_WA*/      /*0x130*/	/* xxx1001bxxxx .... (unimplemented, less likely) */
-/*efine XTHAL_PAM_WRITETHRU_RWA*/     /*0x1B0*/	/* xxx1101bxxxx .... (unimplemented, less likely) */
-/*efine XTHAL_PAM_WRITEBACK_WA*/      /*0x170*/	/* xxx1011bxxxx .... (unimplemented, less likely) */
-
-
-#if 0
-/*
-    Cache attribute encoding for CACHEATTR (per ISA):
-    (Note:  if this differs from ISA Ref Manual, ISA has precedence)
-
-	Inst-fetches	Loads		Stores
-	-------------	------------	-------------
-0x0	FCA_EXCEPTION	LCA_NACACHED	SCA_WRITETHRU	cached no-allocate (previously misnamed "uncached")
-0x1	FCA_CACHED	LCA_CACHED	SCA_WRITETHRU	cached
-0x2	FCA_BYPASS	LCA_BYPASS_G*	SCA_BYPASS	bypass cache (what most people call uncached)
-0x3	FCA_CACHED	LCA_CACHED	SCA_WRITEALLOCF	write-allocate
-		     or LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)
-0x4	FCA_CACHED	LCA_CACHED	SCA_WRITEBACK[M] write-back [MP-coherent]
-		     or LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)
-0x5	FCA_CACHED	LCA_CACHED	SCA_WRITEBACK_NOALLOC	write-back no-allocate
-     or	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)
-0x6..D	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	(reserved)
-0xE	FCA_EXCEPTION	LCA_ISOLATE	SCA_ISOLATE	isolate
-0xF	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	illegal
-     *  Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
-*/
-#endif /*0*/
-
-
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*----------------------------------------------------------------------
-   				Register Windows
-  ----------------------------------------------------------------------*/
-
-/*  This spill any live register windows (other than the caller's):
- *  (NOTE:  current implementation require privileged code, but
- *   a user-callable implementation is possible.)  */
-extern void      xthal_window_spill( void );
-
-
-/*----------------------------------------------------------------------
-			Optional/Custom Processor State
-  ----------------------------------------------------------------------*/
-
-/* validate & invalidate the TIE register file */
-extern void xthal_validate_cp(int);
-extern void xthal_invalidate_cp(int);
-
-/* read and write cpenable register */
-extern void xthal_set_cpenable(unsigned);
-extern unsigned xthal_get_cpenable(void);
-
-
-/*----------------------------------------------------------------------
-   				Interrupts
-  ----------------------------------------------------------------------*/
-
-/* the number of interrupt levels */
-extern const unsigned char Xthal_num_intlevels;
-/* the number of interrupts */
-extern const unsigned char Xthal_num_interrupts;
-/* the highest level of interrupts masked by PS.EXCM */
-extern const unsigned char Xthal_excm_level;
-
-/* mask for level of interrupts */
-extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
-/* mask for level 0 to N interrupts */
-extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
-
-/* level of each interrupt */
-extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
-
-/* type per interrupt */
-extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
-
-/* masks of each type of interrupt */
-extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
-
-/* interrupt numbers assigned to each timer interrupt */
-extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
-
-/*  INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions:  */
-extern unsigned  xthal_get_intenable( void );
-extern void      xthal_set_intenable( unsigned );
-extern unsigned  xthal_get_interrupt( void );
-#define xthal_get_intread	xthal_get_interrupt	/* backward compatibility */
-extern void      xthal_set_intset( unsigned );
-extern void      xthal_set_intclear( unsigned );
-
-
-/*----------------------------------------------------------------------
-   				Debug
-  ----------------------------------------------------------------------*/
-
-/*  Number of instruction and data break registers:  */
-extern const int Xthal_num_ibreak;
-extern const int Xthal_num_dbreak;
-
-
-/*----------------------------------------------------------------------
-   				Core Counter
-  ----------------------------------------------------------------------*/
-
-/* counter info */
-extern const unsigned char Xthal_have_ccount;	/* set if CCOUNT register present */
-extern const unsigned char Xthal_num_ccompare;	/* number of CCOMPAREn registers */
-
-/* get CCOUNT register (if not present return 0) */
-extern unsigned xthal_get_ccount(void);
-
-/* set and get CCOMPAREn registers (if not present, get returns 0) */
-extern void     xthal_set_ccompare(int, unsigned);
-extern unsigned xthal_get_ccompare(int);
-
-
-/*----------------------------------------------------------------------
-                             Miscellaneous
-  ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_have_prid;
-extern const unsigned char Xthal_have_exceptions;
-extern const unsigned char Xthal_xea_version;
-extern const unsigned char Xthal_have_interrupts;
-extern const unsigned char Xthal_have_highlevel_interrupts;
-extern const unsigned char Xthal_have_nmi;
-
-extern unsigned xthal_get_prid( void );
-
-
-/*----------------------------------------------------------------------
-		Virtual interrupt prioritization (DEPRECATED)
-  ----------------------------------------------------------------------*/
-
-/*  Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities:  */
-extern unsigned	xthal_vpri_to_intlevel(unsigned vpri);
-extern unsigned	xthal_intlevel_to_vpri(unsigned intlevel);
-
-/*  Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints:  */
-extern unsigned	xthal_int_enable(unsigned);
-extern unsigned	xthal_int_disable(unsigned);
-
-/*  Set/get virtual priority of an interrupt:  */
-extern int	xthal_set_int_vpri(int intnum, int vpri);
-extern int	xthal_get_int_vpri(int intnum);
-
-/*  Set/get interrupt lockout level for exclusive access to virtual priority data structures:  */
-extern void	xthal_set_vpri_locklevel(unsigned intlevel);
-extern unsigned	xthal_get_vpri_locklevel(void);
-
-/*  Set/get current virtual interrupt priority:  */
-extern unsigned	xthal_set_vpri(unsigned vpri);
-extern unsigned	xthal_get_vpri(void);
-extern unsigned	xthal_set_vpri_intlevel(unsigned intlevel);
-extern unsigned	xthal_set_vpri_lock(void);
-
-
-/*----------------------------------------------------------------------
-	Generic Interrupt Trampolining Support (DEPRECATED)
-  ----------------------------------------------------------------------*/
-
-typedef void (XtHalVoidFunc)(void);
-
-/*  Bitmask of interrupts currently trampolining down:  */
-extern unsigned Xthal_tram_pending;
-
-/*
- *  Bitmask of which interrupts currently trampolining down synchronously are
- *  actually enabled; this bitmask is necessary because INTENABLE cannot hold
- *  that state (sync-trampolining interrupts must be kept disabled while
- *  trampolining);  in the current implementation, any bit set here is not set
- *  in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level
- *  one), its enable bit must be moved from here to INTENABLE:
- */
-extern unsigned Xthal_tram_enabled;
-
-/*  Bitmask of interrupts configured for sync trampolining:  */
-extern unsigned Xthal_tram_sync;
-
-/*  Trampoline support functions:  */
-extern unsigned  xthal_tram_pending_to_service( void );
-extern void      xthal_tram_done( unsigned serviced_mask );
-extern int       xthal_tram_set_sync( int intnum, int sync );
-extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
-
-
-/*----------------------------------------------------------------------
-			Internal Memories
-  ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_num_instrom;
-extern const unsigned char Xthal_num_instram;
-extern const unsigned char Xthal_num_datarom;
-extern const unsigned char Xthal_num_dataram;
-extern const unsigned char Xthal_num_xlmi;
-
-/*  Each of the following arrays contains at least one entry,
- *  or as many entries as needed if more than one:  */
-extern const unsigned int  Xthal_instrom_vaddr[];
-extern const unsigned int  Xthal_instrom_paddr[];
-extern const unsigned int  Xthal_instrom_size [];
-extern const unsigned int  Xthal_instram_vaddr[];
-extern const unsigned int  Xthal_instram_paddr[];
-extern const unsigned int  Xthal_instram_size [];
-extern const unsigned int  Xthal_datarom_vaddr[];
-extern const unsigned int  Xthal_datarom_paddr[];
-extern const unsigned int  Xthal_datarom_size [];
-extern const unsigned int  Xthal_dataram_vaddr[];
-extern const unsigned int  Xthal_dataram_paddr[];
-extern const unsigned int  Xthal_dataram_size [];
-extern const unsigned int  Xthal_xlmi_vaddr[];
-extern const unsigned int  Xthal_xlmi_paddr[];
-extern const unsigned int  Xthal_xlmi_size [];
-
-
-/*----------------------------------------------------------------------
-   				Cache
-  ----------------------------------------------------------------------*/
-
-/* number of cache sets in log2(lines per way) */
-extern const unsigned char Xthal_icache_setwidth;
-extern const unsigned char Xthal_dcache_setwidth;
-/* cache set associativity (number of ways) */
-extern const unsigned int  Xthal_icache_ways;
-extern const unsigned int  Xthal_dcache_ways;
-/* cache features */
-extern const unsigned char Xthal_icache_line_lockable;
-extern const unsigned char Xthal_dcache_line_lockable;
-
-/* cache attribute register control (used by other HAL routines) */
-extern unsigned xthal_get_cacheattr( void );
-extern unsigned xthal_get_icacheattr( void );
-extern unsigned xthal_get_dcacheattr( void );
-extern void     xthal_set_cacheattr( unsigned );
-extern void     xthal_set_icacheattr( unsigned );
-extern void     xthal_set_dcacheattr( unsigned );
-/* set cache attribute (access modes) for a range of memory */
-extern int      xthal_set_region_attribute( void *addr, unsigned size,
-					    unsigned cattr, unsigned flags );
-/*  Bits of flags parameter to xthal_set_region_attribute():  */
-#define XTHAL_CAFLAG_EXPAND		0x000100	/* only expand allowed access to range, don't reduce it */
-#define XTHAL_CAFLAG_EXACT		0x000200	/* return error if can't apply change to exact range specified */
-#define XTHAL_CAFLAG_NO_PARTIAL		0x000400	/* don't apply change to regions partially covered by range */
-#define XTHAL_CAFLAG_NO_AUTO_WB		0x000800	/* don't writeback data after leaving writeback attribute */
-#define XTHAL_CAFLAG_NO_AUTO_INV	0x001000	/* don't invalidate after disabling cache (entering bypass) */
-
-/* enable caches */
-extern void xthal_icache_enable( void );	/* DEPRECATED */
-extern void xthal_dcache_enable( void );	/* DEPRECATED */
-/* disable caches */
-extern void xthal_icache_disable( void );	/* DEPRECATED */
-extern void xthal_dcache_disable( void );	/* DEPRECATED */
-
-/* invalidate the caches */
-extern void xthal_icache_all_invalidate( void );
-extern void xthal_dcache_all_invalidate( void );
-/* write dirty data back */
-extern void xthal_dcache_all_writeback( void );
-/* write dirty data back and invalidate */
-extern void xthal_dcache_all_writeback_inv( void );
-/* prefetch and lock specified memory range into cache */
-extern void xthal_icache_region_lock( void *addr, unsigned size );
-extern void xthal_dcache_region_lock( void *addr, unsigned size );
-# ifndef XTHAL_USE_CACHE_MACROS
-extern void xthal_icache_line_lock(void *addr);
-extern void xthal_dcache_line_lock(void *addr);
-# endif
-/* unlock from cache */
-extern void xthal_icache_all_unlock( void );
-extern void xthal_dcache_all_unlock( void );
-extern void xthal_icache_region_unlock( void *addr, unsigned size );
-extern void xthal_dcache_region_unlock( void *addr, unsigned size );
-# ifndef XTHAL_USE_CACHE_MACROS
-extern void xthal_icache_line_unlock(void *addr);
-extern void xthal_dcache_line_unlock(void *addr);
-# endif
-
-
-
-/*----------------------------------------------------------------------
-                         Local Memory ECC/Parity
-  ----------------------------------------------------------------------*/
-
-/*  Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx:  */
-extern void xthal_memep_inject_error(void *addr, int size, int flags);
-
-
-
-/*----------------------------------------------------------------------
-                         Memory Management Unit
-  ----------------------------------------------------------------------*/
-
-extern const unsigned char Xthal_have_spanning_way;
-extern const unsigned char Xthal_have_identity_map;
-extern const unsigned char Xthal_have_mimic_cacheattr;
-extern const unsigned char Xthal_have_xlt_cacheattr;
-extern const unsigned char Xthal_have_cacheattr;
-extern const unsigned char Xthal_have_tlbs;
-
-extern const unsigned char Xthal_mmu_asid_bits;		/* 0 .. 8 */
-extern const unsigned char Xthal_mmu_asid_kernel;
-extern const unsigned char Xthal_mmu_rings;		/* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
-extern const unsigned char Xthal_mmu_ring_bits;
-extern const unsigned char Xthal_mmu_sr_bits;
-extern const unsigned char Xthal_mmu_ca_bits;
-extern const unsigned int  Xthal_mmu_max_pte_page_size;
-extern const unsigned int  Xthal_mmu_min_pte_page_size;
-
-extern const unsigned char Xthal_itlb_way_bits;
-extern const unsigned char Xthal_itlb_ways;
-extern const unsigned char Xthal_itlb_arf_ways;
-extern const unsigned char Xthal_dtlb_way_bits;
-extern const unsigned char Xthal_dtlb_ways;
-extern const unsigned char Xthal_dtlb_arf_ways;
-
-/*  Convert between virtual and physical addresses (through static maps only):  */
-/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
-extern int  xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
-extern int  xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
-
-#define XCHAL_SUCCESS 0
-#define XCHAL_ADDRESS_MISALIGNED -1
-#define XCHAL_INEXACT -2
-#define XCHAL_INVALID_ADDRESS -3
-#define XCHAL_UNSUPPORTED_ON_THIS_ARCH -4
-#define XCHAL_NO_PAGES_MAPPED -5
-#define XTHAL_NO_MAPPING -6
-
-#define XCHAL_CA_R   (0xC0 | 0x40000000)
-#define XCHAL_CA_RX  (0xD0 | 0x40000000)
-#define XCHAL_CA_RW  (0xE0 | 0x40000000)
-#define XCHAL_CA_RWX (0xF0 | 0x40000000)
-
-extern int xthal_set_region_translation(void* vaddr, void* paddr, unsigned size, unsigned cache_atr, unsigned flags);
-extern int xthal_v2p(void*, void**, unsigned*, unsigned*);
-extern int xthal_invalidate_region(void* addr);
-extern int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned cattr);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-
-
-/****************************************************************************
-		EXPERIMENTAL and DEPRECATED Definitions
- ****************************************************************************/
-
-
-#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef INCLUDE_DEPRECATED_HAL_CODE
-extern const unsigned char Xthal_have_old_exc_arch;
-extern const unsigned char Xthal_have_mmu;
-extern const unsigned int  Xthal_num_regs;
-extern const unsigned char Xthal_num_iroms;
-extern const unsigned char Xthal_num_irams;
-extern const unsigned char Xthal_num_droms;
-extern const unsigned char Xthal_num_drams;
-extern const unsigned int  Xthal_configid0;
-extern const unsigned int  Xthal_configid1;
-#endif
-
-#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
-#define XTHAL_24_BIT_BREAK		0x80000000
-#define XTHAL_16_BIT_BREAK		0x40000000
-extern const unsigned short	Xthal_ill_inst_16[16];
-#define XTHAL_DEST_REG		0xf0000000	/* Mask for destination register */
-#define XTHAL_DEST_REG_INST	0x08000000	/* Branch address is in register */
-#define XTHAL_DEST_REL_INST	0x04000000	/* Branch address is relative */
-#define XTHAL_RFW_INST		0x00000800
-#define XTHAL_RFUE_INST		0x00000400
-#define XTHAL_RFI_INST		0x00000200
-#define XTHAL_RFE_INST		0x00000100
-#define XTHAL_RET_INST		0x00000080
-#define XTHAL_BREAK_INST	0x00000040
-#define XTHAL_SYSCALL_INST	0x00000020
-#define XTHAL_LOOP_END		0x00000010	/* Not set by xthal_inst_type */
-#define XTHAL_JUMP_INST		0x00000008	/* Call or jump instruction */
-#define XTHAL_BRANCH_INST	0x00000004	/* Branch instruction */
-#define XTHAL_24_BIT_INST	0x00000002
-#define XTHAL_16_BIT_INST   0x00000001
-typedef struct xthal_state {
-    unsigned	pc;
-    unsigned	ar[16];
-    unsigned	lbeg;
-    unsigned	lend;
-    unsigned	lcount;
-    unsigned	extra_ptr;
-    unsigned	cpregs_ptr[XTHAL_MAX_CPS];
-} XTHAL_STATE;
-extern unsigned int xthal_inst_type(void *addr);
-extern unsigned int xthal_branch_addr(void *addr);
-extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
-#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
-
-#endif /*XTENSA_HAL_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/specreg.h b/tools/sdk/include/esp32/xtensa/specreg.h
deleted file mode 100644
index 0b2edee0172..00000000000
--- a/tools/sdk/include/esp32/xtensa/specreg.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Xtensa Special Register symbolic names
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/specreg.h#2 $ */
-
-/*
- * Copyright (c) 2005-2011 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTENSA_SPECREG_H
-#define XTENSA_SPECREG_H
-
-/*  Special registers:  */
-#define LBEG		0
-#define LEND		1
-#define LCOUNT		2
-#define SAR		3
-#define BR		4
-#define LITBASE		5
-#define SCOMPARE1	12
-#define ACCLO		16
-#define ACCHI		17
-#define MR_0		32
-#define MR_1		33
-#define MR_2		34
-#define MR_3		35
-#define PREFCTL		40
-#define WINDOWBASE	72
-#define WINDOWSTART	73
-#define PTEVADDR	83
-#define RASID		90
-#define ITLBCFG		91
-#define DTLBCFG		92
-#define IBREAKENABLE	96
-#define MEMCTL		97
-#define CACHEATTR	98
-#define ATOMCTL		99
-#define DDR		104
-#define MECR		110
-#define IBREAKA_0	128
-#define IBREAKA_1	129
-#define DBREAKA_0	144
-#define DBREAKA_1	145
-#define DBREAKC_0	160
-#define DBREAKC_1	161
-#define CONFIGID0	176
-#define EPC_1		177
-#define EPC_2		178
-#define EPC_3		179
-#define EPC_4		180
-#define EPC_5		181
-#define EPC_6		182
-#define EPC_7		183
-#define DEPC		192
-#define EPS_2		194
-#define EPS_3		195
-#define EPS_4		196
-#define EPS_5		197
-#define EPS_6		198
-#define EPS_7		199
-#define CONFIGID1	208
-#define EXCSAVE_1	209
-#define EXCSAVE_2	210
-#define EXCSAVE_3	211
-#define EXCSAVE_4	212
-#define EXCSAVE_5	213
-#define EXCSAVE_6	214
-#define EXCSAVE_7	215
-#define CPENABLE	224
-#define INTERRUPT	226
-#define INTREAD		INTERRUPT	/* alternate name for backward compatibility */
-#define INTSET		INTERRUPT	/* alternate name for backward compatibility */
-#define INTCLEAR	227
-#define INTENABLE	228
-#define PS		230
-#define VECBASE		231
-#define EXCCAUSE	232
-#define DEBUGCAUSE	233
-#define CCOUNT		234
-#define PRID		235
-#define ICOUNT		236
-#define ICOUNTLEVEL	237
-#define EXCVADDR	238
-#define CCOMPARE_0	240
-#define CCOMPARE_1	241
-#define CCOMPARE_2	242
-#define MISC_REG_0	244
-#define MISC_REG_1	245
-#define MISC_REG_2	246
-#define MISC_REG_3	247
-
-/*  Special cases (bases of special register series):  */
-#define MR		32
-#define IBREAKA		128
-#define DBREAKA		144
-#define DBREAKC		160
-#define EPC		176
-#define EPS		192
-#define EXCSAVE		208
-#define CCOMPARE	240
-#define MISC_REG	244
-
-/*  Tensilica-defined user registers:  */
-#if 0
-/*#define ...	 21..24 */	/* (545CK) */
-/*#define ...	140..143 */	/* (545CK) */
-#define EXPSTATE	230	/* Diamond */
-#define THREADPTR	231	/* threadptr option */
-#define FCR		232	/* FPU */
-#define FSR		233	/* FPU */
-#define AE_OVF_SAR	240	/* HiFi2 */
-#define AE_BITHEAD	241	/* HiFi2 */
-#define AE_TS_FTS_BU_BP	242	/* HiFi2 */
-#define AE_SD_NO	243	/* HiFi2 */
-#define VSAR		240	/* VectraLX */
-#define ROUND_LO	242	/* VectraLX */
-#define ROUND_HI	243	/* VectraLX */
-#define CBEGIN		246	/* VectraLX */
-#define CEND		247	/* VectraLX */
-#endif
-
-#endif /* XTENSA_SPECREG_H */
-
diff --git a/tools/sdk/include/esp32/xtensa/traxreg.h b/tools/sdk/include/esp32/xtensa/traxreg.h
deleted file mode 100644
index 282ba1feef2..00000000000
--- a/tools/sdk/include/esp32/xtensa/traxreg.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/* TRAX register definitions
-
-   Copyright (c) 2006-2012 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _TRAX_REGISTERS_H_
-#define _TRAX_REGISTERS_H_
-
-#define SHOW	1
-#define HIDE	0
-
-#define RO	0
-#define RW	1
-
-/*  TRAX Register Numbers (from possible range of 0..127)  */
-#if 0
-#define TRAXREG_ID		0
-#define TRAXREG_CONTROL		1
-#define TRAXREG_STATUS		2
-#define TRAXREG_DATA		3
-#define TRAXREG_ADDRESS		4
-#define TRAXREG_TRIGGER		5
-#define TRAXREG_MATCH		6
-#define TRAXREG_DELAY		7
-#define TRAXREG_STARTADDR	8
-#define TRAXREG_ENDADDR		9
-/*  Internal use only (unpublished):  */
-#define TRAXREG_P4CHANGE	16
-#define TRAXREG_P4REV		17
-#define TRAXREG_P4DATE		18
-#define TRAXREG_P4TIME		19
-#define TRAXREG_PDSTATUS	20
-#define TRAXREG_PDDATA		21
-#define TRAXREG_STOP_PC		22
-#define TRAXREG_STOP_ICNT	23
-#define TRAXREG_MSG_STATUS	24
-#define TRAXREG_FSM_STATUS	25
-#define TRAXREG_IB_STATUS	26
-#define TRAXREG_MAX		27
-#define TRAXREG_ITCTRL		96
-#endif
-/* The registers above match the NAR addresses. So, their values are used for NAR access */
-
-/*  TRAX Register Fields  */
-
-/*  TRAX ID register fields:  */
-#define TRAX_ID_PRODNO          0xf0000000	/* product number (0=TRAX) */
-#define TRAX_ID_PRODOPT         0x0f000000	/* product options */
-#define TRAX_ID_MIW64		0x08000000	/* opt: instruction width */
-#define TRAX_ID_AMTRAX		0x04000000	/* opt: collection of options,
-						   internal (VER_2_0 or later)*/
-#define TRAX_ID_MAJVER(id)	(((id) >> 20) & 0x0f)
-#define TRAX_ID_MINVER(id)	(((id) >> 17) & 0x07)
-#define TRAX_ID_VER(id)		((TRAX_ID_MAJVER(id)<<4)|TRAX_ID_MINVER(id))
-#define TRAX_ID_STDCFG		0x00010000	/* standard config */
-#define TRAX_ID_CFGID		0x0000ffff	/* TRAX configuration ID */
-#define TRAX_ID_MEMSHARED	0x00001000	/* Memshared option in TRAX */
-#define TRAX_ID_FROM_VER(ver)	((((ver) & 0xf0) << 16) | (((ver) & 0x7) << 17))
-/*  Other TRAX ID register macros:  */
-/*  TRAX versions of interest (TRAX_ID_VER(), ie. MAJVER*16 + MINVER):  */
-#define TRAX_VER_1_0		0x10		/* RA */
-#define TRAX_VER_1_1		0x11		/* RB thru RC-2010.1 */
-#define TRAX_VER_2_0		0x20		/* RC-2010.2, RD-2010.0, 
-						   RD-2011.1 */
-#define TRAX_VER_2_1		0x21		/* RC-2011.3 / RD-2011.2 and 
-						   later */
-#define TRAX_VER_3_0		0x30		/* RE-2012.0 */
-#define	TRAX_VER_3_1		0x31		/* RE-2012.1 */
-#define TRAX_VER_HUAWEI_3	TRAX_VER_3_0	/* For Huawei, PRs: 25223, 25224
-						   , 24880 */
-
-
-/*  TRAX version 1.0 requires a couple software workarounds:  */
-#define TRAX_ID_1_0_ERRATUM(id)	(TRAX_ID_VER(id) == TRAX_VER_1_0)
-/*  TRAX version 2.0 requires software workaround for PR 22161:  */
-#define TRAX_ID_MEMSZ_ERRATUM(id)	(TRAX_ID_VER(id) == TRAX_VER_2_0)
-
-/*  TRAX Control register fields:  */
-#define TRAX_CONTROL_TREN	0x00000001
-#define TRAX_CONTROL_TRSTP	0x00000002
-#define TRAX_CONTROL_PCMEN	0x00000004
-#define TRAX_CONTROL_PTIEN	0x00000010
-#define TRAX_CONTROL_CTIEN	0x00000020
-#define TRAX_CONTROL_TMEN	0x00000080	/* 2.0+ */
-#define TRAX_CONTROL_CNTU	0x00000200
-#define TRAX_CONTROL_BIEN	0x00000400
-#define TRAX_CONTROL_BOEN	0x00000800
-#define TRAX_CONTROL_TSEN	0x00000800
-#define TRAX_CONTROL_SMPER	0x00007000
-#define TRAX_CONTROL_SMPER_SHIFT	12
-#define TRAX_CONTROL_PTOWT	0x00010000
-#define TRAX_CONTROL_CTOWT	0x00020000
-#define TRAX_CONTROL_PTOWS	0x00100000
-#define TRAX_CONTROL_CTOWS	0x00200000
-#define TRAX_CONTROL_ATID	0x7F000000	/* 2.0+, amtrax */
-#define TRAX_CONTROL_ATID_SHIFT		24
-#define TRAX_CONTROL_ATEN	0x80000000	/* 2.0+, amtrax */
-
-#define TRAX_CONTROL_PTOWS_ER	0x00020000	/* For 3.0 */
-#define TRAX_CONTROL_CTOWT_ER	0x00100000	/* For 3.0 */
-
-#define TRAX_CONTROL_ITCTO	0x00400000	/* For 3.0 */
-#define TRAX_CONTROL_ITCTIA	0x00800000	/* For 3.0 */
-#define TRAX_CONTROL_ITATV	0x01000000	/* For 3.0 */
-
-
-/*  TRAX Status register fields:  */
-#define TRAX_STATUS_TRACT	0x00000001
-#define TRAX_STATUS_TRIG	0x00000002
-#define TRAX_STATUS_PCMTG	0x00000004
-#define TRAX_STATUS_BUSY	0x00000008  /* ER ??? */
-#define TRAX_STATUS_PTITG	0x00000010
-#define TRAX_STATUS_CTITG	0x00000020
-#define TRAX_STATUS_MEMSZ	0x00001F00
-#define TRAX_STATUS_MEMSZ_SHIFT		8
-#define TRAX_STATUS_PTO		0x00010000
-#define TRAX_STATUS_CTO		0x00020000
-
-#define TRAX_STATUS_ITCTOA	0x00400000	/* For 3.0 */
-#define TRAX_STATUS_ITCTI	0x00800000	/* For 3.0 */
-#define TRAX_STATUS_ITATR	0x01000000	/* For 3.0 */
-
-
-/*  TRAX Address register fields:  */
-#define TRAX_ADDRESS_TWSAT	0x80000000
-#define TRAX_ADDRESS_TWSAT_SHIFT	31
-#define TRAX_ADDRESS_TOTALMASK	0x00FFFFFF
-// !!! VUakiVU. added for new TRAX:
-#define TRAX_ADDRESS_WRAPCNT	0x7FE00000	/* version ???... */
-#define TRAX_ADDRESS_WRAP_SHIFT		21
-
-/*  TRAX PCMatch register fields:  */
-#define TRAX_PCMATCH_PCML	0x0000001F
-#define TRAX_PCMATCH_PCML_SHIFT		0
-#define TRAX_PCMATCH_PCMS	0x80000000
-
-/*  Compute trace ram buffer size (in bytes) from status register:  */
-#define TRAX_MEM_SIZE(status)	(1L << (((status) & TRAX_STATUS_MEMSZ) >> TRAX_STATUS_MEMSZ_SHIFT))
-
-#if 0
-/*  Describes a field within a register:  */
-typedef struct {
-    const char*	name;
-// unsigned	width;
-// unsigned	shift;
-    char	width;
-    char	shift;
-    char	visible;		/* 0 = internal use only, 1 = shown */
-    char	reserved;
-} trax_regfield_t;
-#endif
-
-/*  Describes a TRAX register:  */
-typedef struct {
-    const char*	name;
-    unsigned	id;
-    char	width;
-    char	visible;
-    char	writable;
-    char	reserved;
-    //const trax_regfield_t * fieldset;
-} trax_regdef_t;
-
-
-extern const trax_regdef_t	trax_reglist[];
-extern const signed char	trax_readable_regs[];
-
-#ifdef  __cplusplus
-extern "C" {
-#endif
-
-/*  Prototypes:  */
-extern int		trax_find_reg(char * regname, char **errmsg);
-extern const char *	trax_regname(int regno);
-
-#ifdef  __cplusplus
-}
-#endif
-
-#endif /* _TRAX_REGISTERS_H_ */
-
diff --git a/tools/sdk/include/esp32/xtensa/xdm-regs.h b/tools/sdk/include/esp32/xtensa/xdm-regs.h
deleted file mode 100644
index 50ee0293387..00000000000
--- a/tools/sdk/include/esp32/xtensa/xdm-regs.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/* xdm-regs.h  -  Common register and related definitions for the XDM
-                  (Xtensa Debug Module) */
-
-/* Copyright (c) 2011-2012 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-
-#ifndef _XDM_REGS_H_
-#define _XDM_REGS_H_
-
-/*  NOTE:  This header file is included by C, assembler, and other sources.
-    So any C-specific or asm-specific content must be appropriately #ifdef'd.  */
-
-
-/*
- *  XDM registers can be accessed using APB, ERI, or JTAG (via NAR).
- *  Address offsets for APB and ERI are the same, and for JTAG
- *  is different (due to the limited 7-bit NAR addressing).
- *
- *  Here, we first provide the constants as APB / ERI address offsets.
- *  This is necessary for assembler code (which accesses XDM via ERI),
- *  because complex conversion macros between the two address maps
- *  don't work in the assembler.
- *  Conversion macros are used to convert these to/from JTAG (NAR),
- *  addresses, for software using JTAG.
- */
-/* FIXME: maybe provide only MISC+CS registers here, and leave specific
-   subsystem registers in separate headers? eg. for TRAX, PERF, OCD */
-
-/*       XDM_....     		ERI addr  [NAR addr] Description...... */
-
-/*  TRAX  */
-#define  XDM_TRAX_ID		0x0000	/*[0x00] ID */
-#define  XDM_TRAX_CONTROL 	0x0004	/*[0x01] Control */
-#define  XDM_TRAX_STATUS	0x0008	/*[0x02] Status */
-#define  XDM_TRAX_DATA		0x000C	/*[0x03] Data */
-#define  XDM_TRAX_ADDRESS	0x0010	/*[0x04] Address */
-#define  XDM_TRAX_TRIGGER	0x0014	/*[0x05] Stop PC */
-#define  XDM_TRAX_MATCH		0x0018	/*[0x06] Stop PC Range */
-#define  XDM_TRAX_DELAY		0x001C	/*[0x07] Post Stop Trigger Capture Size */
-#define  XDM_TRAX_STARTADDR	0x0020	/*[0x08] Trace Memory Start */
-#define  XDM_TRAX_ENDADDR	0x0024	/*[0x09] Trace Memory End */
-#define  XDM_TRAX_DEBUGPC	0x003C	/*[0x0F] Debug PC */
-#define  XDM_TRAX_P4CHANGE	0x0040	/*[0x10] X */
-#define  XDM_TRAX_TIME0		0x0040	/*[0x10] First Time Register */
-#define  XDM_TRAX_P4REV		0x0044	/*[0x11] X */
-#define  XDM_TRAX_TIME1		0x0044	/*[0x11] Second Time Register */
-#define  XDM_TRAX_P4DATE	0x0048	/*[0x12] X */
-#define  XDM_TRAX_INTTIME_MAX	0x0048 /*[0x12] maximal Value of Timestamp IntTime */
-#define  XDM_TRAX_P4TIME	0x004C	/*[0x13] X */
-#define  XDM_TRAX_PDSTATUS	0x0050	/*[0x14] Sample of PDebugStatus */
-#define  XDM_TRAX_PDDATA	0x0054	/*[0x15] Sample of PDebugData */
-#define  XDM_TRAX_STOP_PC	0x0058	/*[0x16] X */
-#define  XDM_TRAX_STOP_ICNT	0x005C	/*[0x16] X */
-#define  XDM_TRAX_MSG_STATUS	0x0060	/*[0x17] X */
-#define  XDM_TRAX_FSM_STATUS	0x0064	/*[0x18] X */
-#define  XDM_TRAX_IB_STATUS	0x0068	/*[0x19] X */
-#define  XDM_TRAX_STOPCNT	0x006C	/*[0x1A] X */
-
-/*  Performance Monitoring Counters  */
-#define  XDM_PERF_PMG		0x1000	/*[0x20] perf. mon. global control register */
-#define  XDM_PERF_INTPC		0x1010	/*[0x24] perf. mon. interrupt PC */
-#define  XDM_PERF_PM0		0x1080	/*[0x28] perf. mon. counter 0 value */
-#define  XDM_PERF_PM1		0x1084	/*[0x29] perf. mon. counter 1 value */
-#define  XDM_PERF_PM2		0x1088	/*[0x2A] perf. mon. counter 2 value */
-#define  XDM_PERF_PM3		0x108C	/*[0x2B] perf. mon. counter 3 value */
-#define  XDM_PERF_PM4		0x1090	/*[0x2C] perf. mon. counter 4 value */
-#define  XDM_PERF_PM5		0x1094	/*[0x2D] perf. mon. counter 5 value */
-#define  XDM_PERF_PM6		0x1098	/*[0x2E] perf. mon. counter 6 value */
-#define  XDM_PERF_PM7		0x109C	/*[0x2F] perf. mon. counter 7 value */
-#define  XDM_PERF_PM(n)		(0x1080+((n)<<2)) /* perfmon cnt n=0..7 value */
-#define  XDM_PERF_PMCTRL0	0x1100	/*[0x30] perf. mon. counter 0 control */
-#define  XDM_PERF_PMCTRL1	0x1104	/*[0x31] perf. mon. counter 1 control */
-#define  XDM_PERF_PMCTRL2	0x1108	/*[0x32] perf. mon. counter 2 control */
-#define  XDM_PERF_PMCTRL3	0x110C	/*[0x33] perf. mon. counter 3 control */
-#define  XDM_PERF_PMCTRL4	0x1110	/*[0x34] perf. mon. counter 4 control */
-#define  XDM_PERF_PMCTRL5	0x1114	/*[0x35] perf. mon. counter 5 control */
-#define  XDM_PERF_PMCTRL6	0x1118	/*[0x36] perf. mon. counter 6 control */
-#define  XDM_PERF_PMCTRL7	0x111C	/*[0x37] perf. mon. counter 7 control */
-#define  XDM_PERF_PMCTRL(n)	(0x1100+((n)<<2)) /* perfmon cnt n=0..7 control */
-#define  XDM_PERF_PMSTAT0	0x1180	/*[0x38] perf. mon. counter 0 status */
-#define  XDM_PERF_PMSTAT1	0x1184	/*[0x39] perf. mon. counter 1 status */
-#define  XDM_PERF_PMSTAT2	0x1188	/*[0x3A] perf. mon. counter 2 status */
-#define  XDM_PERF_PMSTAT3	0x118C	/*[0x3B] perf. mon. counter 3 status */
-#define  XDM_PERF_PMSTAT4	0x1190	/*[0x3C] perf. mon. counter 4 status */
-#define  XDM_PERF_PMSTAT5	0x1194	/*[0x3D] perf. mon. counter 5 status */
-#define  XDM_PERF_PMSTAT6	0x1198	/*[0x3E] perf. mon. counter 6 status */
-#define  XDM_PERF_PMSTAT7	0x119C	/*[0x3F] perf. mon. counter 7 status */
-#define  XDM_PERF_PMSTAT(n)	(0x1180+((n)<<2)) /* perfmon cnt n=0..7 status */
-
-/*  On-Chip-Debug (OCD)  */
-#define  XDM_OCD_ID		0x2000	/*[0x40] ID register */
-#define  XDM_OCD_DCR_CLR	0x2008	/*[0x42] Debug Control reg clear */
-#define  XDM_OCD_DCR_SET	0x200C	/*[0x43] Debug Control reg set */
-#define  XDM_OCD_DSR		0x2010	/*[0x44] Debug Status reg */
-#define  XDM_OCD_DDR		0x2014	/*[0x45] Debug Data reg */
-#define  XDM_OCD_DDREXEC	0x2018	/*[0x46] Debug Data reg + execute-DIR */
-#define  XDM_OCD_DIR0EXEC	0x201C	/*[0x47] Debug Instruction reg, word 0 + execute-DIR */
-#define  XDM_OCD_DIR0		0x2020	/*[0x48] Debug Instruction reg, word 1 */
-#define  XDM_OCD_DIR1		0x2024	/*[0x49] Debug Instruction reg, word 2 */
-#define  XDM_OCD_DIR2		0x2028	/*[0x4A] Debug Instruction reg, word 3 */
-#define  XDM_OCD_DIR3		0x202C	/*[0x49] Debug Instruction reg, word 4 */
-#define  XDM_OCD_DIR4		0x2030	/*[0x4C] Debug Instruction reg, word 5 */
-#define  XDM_OCD_DIR5		0x2034	/*[0x4D] Debug Instruction reg, word 5 */
-#define  XDM_OCD_DIR6		0x2038	/*[0x4E] Debug Instruction reg, word 6 */
-#define  XDM_OCD_DIR7		0x203C	/*[0x4F] Debug Instruction reg, word 7 */
-
-/*  Miscellaneous Registers  */
-#define  XDM_MISC_PWRCTL	0x3020	/*[0x58] Power and Reset Control */
-#define  XDM_MISC_PWRSTAT	0x3024	/*[0x59] Power and Reset Status */
-#define  XDM_MISC_ERISTAT	0x3028	/*[0x5A] ERI Transaction Status */
-#define  XDM_MISC_DATETIME	0x3034	/*[0x5D] [INTERNAL] Timestamps of build */
-#define  XDM_MISC_UBID		0x3038	/*[0x5E] [INTERNAL] Build Unique ID */
-#define  XDM_MISC_CID		0x303C	/*[0x5F] [INTERNAL] Customer ID */
-
-/*  CoreSight compatibility  */
-#define  XDM_CS_ITCTRL		0x3F00	/*[0x60] InTegration Mode control reg */
-#define  XDM_CS_CLAIMSET	0x3FA0	/*[0x68] Claim Tag Set reg */
-#define  XDM_CS_CLAIMCLR	0x3FA4	/*[0x69] Claim Tag Clear reg */
-#define  XDM_CS_LOCK_ACCESS	0x3FB0	/*[0x6B] Lock Access (writing 0xC5ACCE55 unlocks) */
-#define  XDM_CS_LOCK_STATUS	0x3FB4	/*[0x6D] Lock Status */
-#define  XDM_CS_AUTH_STATUS	0x3FB8	/*[0x6E] Authentication Status */
-#define  XDM_CS_DEV_ID		0x3FC8	/*[0x72] Device ID */
-#define  XDM_CS_DEV_TYPE	0x3FCC	/*[0x73] Device Type */
-#define  XDM_CS_PER_ID4		0x3FD0	/*[0x74] Peripheral ID reg byte 4 */
-#define  XDM_CS_PER_ID5		0x3FD4	/*[0x75] Peripheral ID reg byte 5 */
-#define  XDM_CS_PER_ID6		0x3FD8	/*[0x76] Peripheral ID reg byte 6 */
-#define  XDM_CS_PER_ID7		0x3FDC	/*[0x77] Peripheral ID reg byte 7 */
-#define  XDM_CS_PER_ID0		0x3FE0	/*[0x78] Peripheral ID reg byte 0 */
-#define  XDM_CS_PER_ID1		0x3FE4	/*[0x79] Peripheral ID reg byte 1 */
-#define  XDM_CS_PER_ID2		0x3FE8	/*[0x7A] Peripheral ID reg byte 2 */
-#define  XDM_CS_PER_ID3		0x3FEC	/*[0x7B] Peripheral ID reg byte 3 */
-#define  XDM_CS_COMP_ID0	0x3FF0	/*[0x7C] Component ID reg byte 0 */
-#define  XDM_CS_COMP_ID1	0x3FF4	/*[0x7D] Component ID reg byte 1 */
-#define  XDM_CS_COMP_ID2	0x3FF8	/*[0x7E] Component ID reg byte 2 */
-#define  XDM_CS_COMP_ID3	0x3FFC	/*[0x7F] Component ID reg byte 3 */
-
-#define CS_PER_ID0	0x00000003
-#define CS_PER_ID1	0x00000021
-#define CS_PER_ID2	0x0000000f
-#define CS_PER_ID3	0x00000000
-#define CS_PER_ID4	0x00000024
-
-#define CS_COMP_ID0	0x0000000d
-#define CS_COMP_ID1	0x00000090
-#define CS_COMP_ID2	0x00000005
-#define CS_COMP_ID3	0x000000b1
-
-#define CS_DEV_TYPE	0x00000015
-
-#define XTENSA_IDCODE	0x120034e5    // FIXME (upper bits not spec. out but BE is !)
-#define XTENSA_MFC_ID	(XTENSA_IDCODE & 0xFFF)
-#define CS_DEV_ID	XTENSA_IDCODE
-
-#define NXS_OCD_REG(val)  ((val >= 0x40) && (val <= 0x5F))
-#define NXS_TRAX_REG(val)  val <= 0x3F
-
-#define ERI_TRAX_REG(val)  ((val & 0xFFFF) < 0x1000)
-#define ERI_OCD_REG(val)   ((val & 0xFFFF) >= 0x2000) && ((val & 0xFFFF) < 0x4000))
-
-/*  Convert above 14-bit ERI/APB address/offset to 7-bit NAR address:  */
-#define _XDM_ERI_TO_NAR(a)	( ((a)&0x3F80)==0x0000 ? (((a)>>2) & 0x1F) \
-				: ((a)&0x3E00)==0x1000 ? (0x20 | (((a)>>2) & 7) | (((a)>>4) & 0x18)) \
-				: ((a)&0x3FC0)==0x2000 ? (0x40 | (((a)>>2) & 0xF)) \
-				: ((a)&0x3FE0)==0x3020 ? (0x50 | (((a)>>2) & 0xF)) \
-				: ((a)&0x3FFC)==0x3F00 ? 0x60 \
-				: ((a)&0x3F80)==0x3F80 ? (0x60 | (((a)>>2) & 0x1F)) \
-				: -1 )
-
-#define XDM_ERI_TO_NAR(a)	_XDM_ERI_TO_NAR(a & 0xFFFF)
-
-/* Convert 7-bit NAR address back to ERI/APB address/offset:  */
-#define _XDM_NAR_TO_APB(a)	((a) <= 0x1f                ? ((a) << 2)                   \
-				:(a) >= 0x20 && (a) <= 0x3F ? (0x1000 | (((a)&  7) << 2) | (((a)&0x18)<<4)) \
-				:(a) >= 0x40 && (a) <= 0x4F ? (0x2000 | (((a)&0xF) << 2))  \
-				:(a) >= 0x58 && (a) <= 0x5F ? (0x3000 | (((a)&0xF) << 2))  \
-				:(a) == 0x60                ? (0x3F00)                     \
-				:(a) >= 0x68 && (a) <= 0x7F ? (0x3F80 | (((a)&0x1F) << 2)) \
-				: -1)
-
-#define XDM_NAR_TO_APB(a)	_XDM_NAR_TO_APB((a & 0xFFFF))
-#define XDM_NAR_TO_ERI(a)	_XDM_NAR_TO_APB((a & 0xFFFF)) | 0x000000
-
-/* Convert APB to ERI address */
-#define XDM_APB_TO_ERI(a)	((a) | (0x100000))
-#define XDM_ERI_TO_APB(a)	((a) & (0x0FFFFF))
-
-/***********  Bit definitions within some of the above registers  ***********/
-#define OCD_ID_LSDDRP			0x01000000
-#define OCD_ID_LSDDRP_SHIFT			24
-#define OCD_ID_ENDIANESS		0x00000001
-#define OCD_ID_ENDIANESS_SHIFT			 0
-#define OCD_ID_PSO			0x0000000C
-#define OCD_ID_PSO_SHIFT			 2
-#define OCD_ID_TRACEPORT		0x00000080
-#define OCD_ID_TRACEPORT_SHIFT			 7
-
-/*  Power Status register.  NOTE:  different bit positions in JTAG vs. ERI/APB !!  */
-/*  ERI/APB:  */
-#define PWRSTAT_CORE_DOMAIN_ON		0x00000001	/* set if core is powered on */
-#define PWRSTAT_CORE_DOMAIN_ON_SHIFT		0
-#define PWRSTAT_WAKEUP_RESET		0x00000002	/* [ERI only] 0=cold start, 1=PSO wakeup */
-#define PWRSTAT_WAKEUP_RESET_SHIFT		1
-#define PWRSTAT_CACHES_LOST_POWER	0x00000004	/* [ERI only] set if caches (/localmems?) lost power */
-							/* FIXME: does this include local memories? */
-#define PWRSTAT_CACHES_LOST_POWER_SHIFT		2
-#define PWRSTAT_CORE_STILL_NEEDED	0x00000010	/* set if others keeping core awake */
-#define PWRSTAT_CORE_STILL_NEEDED_SHIFT		4
-#define PWRSTAT_MEM_DOMAIN_ON		0x00000100	/* set if memory domain is powered on */
-#define PWRSTAT_MEM_DOMAIN_ON_SHIFT		8
-#define PWRSTAT_DEBUG_DOMAIN_ON		0x00001000	/* set if debug domain is powered on */
-#define PWRSTAT_DEBUG_DOMAIN_ON_SHIFT		12
-#define PWRSTAT_ALL_ON			PWRSTAT_CORE_DOMAIN_ON | PWRSTAT_MEM_DOMAIN_ON | PWRSTAT_DEBUG_DOMAIN_ON
-#define PWRSTAT_CORE_WAS_RESET		0x00010000	/* [APB only] set if core got reset */
-#define PWRSTAT_CORE_WAS_RESET_SHIFT		16
-#define PWRSTAT_DEBUG_WAS_RESET		0x10000000	/* set if debug module got reset */
-#define PWRSTAT_DEBUG_WAS_RESET_SHIFT		28
-/*  JTAG:  */
-#define J_PWRSTAT_CORE_DOMAIN_ON	0x01		/* set if core is powered on */
-#define J_PWRSTAT_MEM_DOMAIN_ON		0x02		/* set if memory domain is powered on */
-#define J_PWRSTAT_DEBUG_DOMAIN_ON	0x04		/* set if debug domain is powered on */
-#define J_PWRSTAT_ALL_ON		J_PWRSTAT_CORE_DOMAIN_ON | J_PWRSTAT_MEM_DOMAIN_ON | J_PWRSTAT_DEBUG_DOMAIN_ON
-#define J_PWRSTAT_CORE_STILL_NEEDED	0x08		/* set if others keeping core awake */
-#define J_PWRSTAT_CORE_WAS_RESET	0x10		/* set if core got reset */
-#define J_PWRSTAT_DEBUG_WAS_RESET	0x40		/* set if debug module got reset */
-
-/*  Power Control register.  NOTE:  different bit positions in JTAG vs. ERI/APB !!  */
-/*  ERI/APB:  */
-#define PWRCTL_CORE_SHUTOFF		0x00000001	/* [ERI only] core wants to shut off on WAITI */
-#define PWRCTL_CORE_SHUTOFF_SHIFT		0
-#define PWRCTL_CORE_WAKEUP		0x00000001	/* [APB only] set to force core to stay powered on */
-#define PWRCTL_CORE_WAKEUP_SHIFT		0
-#define PWRCTL_MEM_WAKEUP		0x00000100	/* set to force memory domain to stay powered on */
-#define PWRCTL_MEM_WAKEUP_SHIFT			8
-#define PWRCTL_DEBUG_WAKEUP		0x00001000	/* set to force debug domain to stay powered on */
-#define PWRCTL_DEBUG_WAKEUP_SHIFT		12
-#define PWRCTL_ALL_ON			PWRCTL_CORE_WAKEUP | PWRCTL_MEM_WAKEUP | PWRCTL_DEBUG_WAKEUP
-#define PWRCTL_CORE_RESET		0x00010000	/* [APB only] set to assert core reset */
-#define PWRCTL_CORE_RESET_SHIFT			16
-#define PWRCTL_DEBUG_RESET		0x10000000	/* set to assert debug module reset */
-#define PWRCTL_DEBUG_RESET_SHIFT		28
-/*  JTAG:  */
-#define J_PWRCTL_CORE_WAKEUP		0x01		/* set to force core to stay powered on */
-#define J_PWRCTL_MEM_WAKEUP		0x02		/* set to force memory domain to stay powered on */
-#define J_PWRCTL_DEBUG_WAKEUP		0x04		/* set to force debug domain to stay powered on */
-#define J_DEBUG_USE			0x80		/*  */
-#define J_PWRCTL_ALL_ON			J_DEBUG_USE | J_PWRCTL_CORE_WAKEUP | J_PWRCTL_MEM_WAKEUP | J_PWRCTL_DEBUG_WAKEUP
-#define J_PWRCTL_DEBUG_ON		J_DEBUG_USE | J_PWRCTL_DEBUG_WAKEUP
-#define J_PWRCTL_CORE_RESET		0x10		/* set to assert core reset */
-#define J_PWRCTL_DEBUG_RESET		0x40		/* set to assert debug module reset */
-
-#define J_PWRCTL_WRITE_MASK		0xFF
-#define J_PWRSTAT_WRITE_MASK		0xFF
-
-#define PWRCTL_WRITE_MASK		~0
-#define PWRSTAT_WRITE_MASK		~0
-
-/************  The following are only relevant for JTAG, so perhaps belong in OCD only  **************/
-
-/*  XDM 5-bit JTAG Instruction Register (IR) values:  */
-#define XDM_IR_PWRCTL		0x08	/* select 8-bit Power/Reset Control (PRC) */
-#define XDM_IR_PWRSTAT		0x09	/* select 8-bit Power/Reset Status (PRS) */
-#define XDM_IR_NAR_SEL		0x1c	/* select altern. 8-bit NAR / 32-bit NDR (Nexus-style) */
-#define XDM_IR_NDR_SEL		0x1d	/* select altern. 32-bit NDR / 8-bit NAR
-					   (FIXME - functionality not yet in HW) */
-#define XDM_IR_IDCODE		0x1e	/* select 32-bit JTAG IDCODE */
-#define XDM_IR_BYPASS		0x1f	/* select 1-bit bypass */
-
-#define XDM_IR_WIDTH		5	/* width of IR for Xtensa TAP */
-
-/*  NAR register bits:  */
-#define XDM_NAR_WRITE		0x01
-#define XDM_NAR_ADDR_MASK	0xFE
-#define XDM_NAR_ADDR_SHIFT	1
-
-#define XDM_NAR_BUSY		0x02
-#define XDM_NAR_ERROR		0x01
-
-#define NEXUS_DIR_READ	0x00
-#define	NEXUS_DIR_WRITE	0x01
-
-/************  Define DCR register bits  **************/
-
-#define DCR_ENABLEOCD		0x0000001
-#define DCR_ENABLEOCD_SHIFT		0
-#define DCR_DEBUG_INT		0x0000002
-#define DCR_DEBUG_INT_SHIFT		1
-#define DCR_DEBUG_OVERRIDE	0x0000004
-#define DCR_DEBUG_OVERRIDE_SHIFT	2
-#define DCR_DEBUG_INTERCEPT	0x0000008
-#define DCR_DEBUG_INTERCEPT_SHIFT	3
-#define DCR_MASK_NMI		0x0000020
-#define DCR_MASK_NMI_SHIFT		5
-#define DCR_STEP_ENABLE		0x0000040
-#define DCR_STEP_ENABLE_SHIFT		6
-#define DCR_BREAK_IN_EN		0x0010000
-#define DCR_BREAK_IN_EN_SHIFT		16
-#define DCR_BREAK_OUT_EN	0x0020000
-#define DCR_BREAK_OUT_EN_SHIFT		17
-#define DCR_DEBUG_INT_EN	0x0040000
-#define DCR_DEBUG_INT_EN_SHIFT		18
-#define DCR_DBG_SW_ACTIVE	0x0100000
-#define DCR_DBG_SW_ACTIVE_SHIFT		20
-#define DCR_STALL_IN_EN		0x0200000
-#define DCR_STALL_IN_EN_SHIFT		21
-#define DCR_DEBUG_OUT_EN	0x0400000
-#define DCR_DEBUG_OUT_EN_SHIFT		22
-#define DCR_BREAK_OUT_ITO	0x1000000
-#define DCR_STALL_OUT_ITO	0x2000000
-#define DCR_STALL_OUT_ITO_SHIFT		25
-
-/************  Define DSR register bits  **************/
-
-#define DOSR_EXECDONE_ER	0x01
-#define DOSR_EXECDONE_SHIFT	0
-#define DOSR_EXCEPTION_ER	0x02
-#define DOSR_EXCEPTION_SHIFT	1
-#define DOSR_BUSY		0x04
-#define DOSR_BUSY_SHIFT		2
-#define DOSR_OVERRUN		0x08
-#define DOSR_OVERRUN_SHIFT	3
-#define DOSR_INOCDMODE_ER	0x10
-#define DOSR_INOCDMODE_SHIFT	4
-#define DOSR_CORE_WROTE_DDR_ER		0x400
-#define DOSR_CORE_WROTE_DDR_SHIFT	10
-#define DOSR_CORE_READ_DDR_ER		0x800
-#define DOSR_CORE_READ_DDR_SHIFT	11
-#define DOSR_HOST_WROTE_DDR_ER		0x4000
-#define DOSR_HOST_WROTE_DDR_SHIFT	14
-#define DOSR_HOST_READ_DDR_ER		0x8000
-#define DOSR_HOST_READ_DDR_SHIFT	15
-
-#define DOSR_DEBUG_PEND_BIN		0x10000
-#define DOSR_DEBUG_PEND_HOST		0x20000
-#define DOSR_DEBUG_PEND_TRAX		0x40000
-#define DOSR_DEBUG_BIN		        0x100000
-#define DOSR_DEBUG_HOST			0x200000
-#define DOSR_DEBUG_TRAX			0x400000
-#define DOSR_DEBUG_PEND_BIN_SHIFT	16
-#define DOSR_DEBUG_PEND_HOST_SHIFT	17
-#define DOSR_DEBUG_PEND_TRAX_SHIFT	18
-#define DOSR_DEBUG_BREAKIN              0x0100000
-#define DOSR_DEBUG_BREAKIN_SHIFT        20
-#define DOSR_DEBUG_HOST_SHIFT		21
-#define DOSR_DEBUG_TRAX_SHIFT		22
-
-#define DOSR_DEBUG_STALL		0x1000000
-#define DOSR_DEBUG_STALL_SHIFT		24
-
-#define DOSR_CORE_ON			0x40000000
-#define DOSR_CORE_ON_SHIFT		30
-#define DOSR_DEBUG_ON			0x80000000
-#define DOSR_DEBUG_ON_SHIFT		31
-
-/********** Performance monitor registers bits **********/
-
-#define PERF_PMG_ENABLE                 0x00000001 /* global enable bit */
-#define PERF_PMG_ENABLE_SHIFT           0
-
-#define PERF_PMCTRL_INT_ENABLE          0x00000001 /* assert interrupt on overflow */
-#define PERF_PMCTRL_INT_ENABLE_SHIFT    0
-#define PERF_PMCTRL_KRNLCNT             0x00000008 /* ignore TRACELEVEL */
-#define PERF_PMCTRL_KRNLCNT_SHIFT       3
-#define PERF_PMCTRL_TRACELEVEL          0x000000F0 /* count when CINTLEVEL <= TRACELEVEL */
-#define PERF_PMCTRL_TRACELEVEL_SHIFT    4
-#define PERF_PMCTRL_SELECT              0x00001F00 /* events group selector */
-#define PERF_PMCTRL_SELECT_SHIFT        8
-#define PERF_PMCTRL_MASK                0xFFFF0000 /* events mask */
-#define PERF_PMCTRL_MASK_SHIFT          16
-
-#define PERF_PMSTAT_OVERFLOW            0x00000001 /* counter overflowed */
-#define PERF_PMSTAT_OVERFLOW_SHIFT      0
-#define PERF_PMSTAT_INT                 0x00000010 /* interrupt asserted */
-#define PERF_PMSTAT_INT_SHIFT           4
-
-#if defined (USE_XDM_REGNAME) || defined (USE_DAP_REGNAME)
-/*  Describes XDM register:  */
-typedef struct {
-    int    reg;
-    char*  name;
-} regdef_t;
-
-/*char* regname(regdef_t* list, int regno)
-{
-  unsigned i;
-  for(i = 0 ; i < (sizeof(list) / sizeof(regdef_t)); i++){
-    if(list[i].reg == regno)
-      return list[i].name;
-  }
-  return "???";
-}*/
-
-/*
- *  Returns the name of the specified XDM register number,
- *  or simply "???" if the register number is not recognized.
- *  FIXME - requires -1 as the last entry - change to compare the name to ???
- *  or even better, make the code above to work.
- */
-static char * regname(regdef_t* list, int reg)
-{
-  int i = 0;
-  while (list[i].reg != -1){
-    if (list[i].reg == reg)
-      break;
-    i++;
-  }
-  return list[i].name;
-}
-
-#if defined (USE_XDM_REGNAME)
-regdef_t xdm_reglist[] =
-{
-  {XDM_TRAX_ID		  ,"TRAX_ID"      },
-  {XDM_TRAX_CONTROL	  ,"CONTROL"      },
-  {XDM_TRAX_STATUS	  ,"STATUS"       },
-  {XDM_TRAX_DATA          ,"DATA"         },
-  {XDM_TRAX_ADDRESS	  ,"ADDRESS"      },
-  {XDM_TRAX_TRIGGER	  ,"TRIGGER PC"   },
-  {XDM_TRAX_MATCH         ,"PC MATCH"     },
-  {XDM_TRAX_DELAY	  ,"DELAY CNT."   },
-  {XDM_TRAX_STARTADDR	  ,"START ADDRESS"},
-  {XDM_TRAX_ENDADDR	  ,"END ADDRESS"  },
-  {XDM_TRAX_DEBUGPC	  ,"DEBUG PC"  },
-  {XDM_TRAX_P4CHANGE	  ,"P4 CHANGE"    },
-  {XDM_TRAX_P4REV         ,"P4 REV."      },
-  {XDM_TRAX_P4DATE	  ,"P4 DATE"      },
-  {XDM_TRAX_P4TIME	  ,"P4 TIME"      },
-  {XDM_TRAX_PDSTATUS	  ,"PD STATUS"    },
-  {XDM_TRAX_PDDATA	  ,"PD DATA"      },
-  {XDM_TRAX_STOP_PC	  ,"STOP PC"      },
-  {XDM_TRAX_STOP_ICNT	  ,"STOP ICNT"    },
-  {XDM_TRAX_MSG_STATUS	  ,"MSG STAT."    },
-  {XDM_TRAX_FSM_STATUS	  ,"FSM STAT."    },
-  {XDM_TRAX_IB_STATUS	  ,"IB STAT."     },
-
-  {XDM_OCD_ID         ,"OCD_ID"  },
-  {XDM_OCD_DCR_CLR    ,"DCR_CLR" },
-  {XDM_OCD_DCR_SET    ,"DCR_SET" },
-  {XDM_OCD_DSR        ,"DOSR"    },
-  {XDM_OCD_DDR        ,"DDR"     },
-  {XDM_OCD_DDREXEC    ,"DDREXEC" },
-  {XDM_OCD_DIR0EXEC   ,"DIR0EXEC"},
-  {XDM_OCD_DIR0       ,"DIR0"    },
-  {XDM_OCD_DIR1       ,"DIR1"    },
-  {XDM_OCD_DIR2       ,"DIR2"    },
-  {XDM_OCD_DIR3       ,"DIR3"    },
-  {XDM_OCD_DIR4       ,"DIR4"    },
-  {XDM_OCD_DIR5       ,"DIR5"    },
-  {XDM_OCD_DIR6       ,"DIR6"    },
-  {XDM_OCD_DIR7       ,"DIR7"    },
-
-  {XDM_PERF_PMG       ,"PMG"    },
-  {XDM_PERF_INTPC     ,"INTPC"  },
-  {XDM_PERF_PM0       ,"PM0 "   },
-  {XDM_PERF_PM1       ,"PM1 "   },
-  {XDM_PERF_PM2       ,"PM2 "   },
-  {XDM_PERF_PM3       ,"PM3 "   },
-  {XDM_PERF_PM4       ,"PM4 "   },
-  {XDM_PERF_PM5       ,"PM5 "   },
-  {XDM_PERF_PM6       ,"PM6 "   },
-  {XDM_PERF_PM7       ,"PM7 "   },
-  {XDM_PERF_PMCTRL0   ,"PMCTRL0"},
-  {XDM_PERF_PMCTRL1   ,"PMCTRL1"},
-  {XDM_PERF_PMCTRL2   ,"PMCTRL2"},
-  {XDM_PERF_PMCTRL3   ,"PMCTRL3"},
-  {XDM_PERF_PMCTRL4   ,"PMCTRL4"},
-  {XDM_PERF_PMCTRL5   ,"PMCTRL5"},
-  {XDM_PERF_PMCTRL6   ,"PMCTRL6"},
-  {XDM_PERF_PMCTRL7   ,"PMCTRL7"},
-  {XDM_PERF_PMSTAT0   ,"PMSTAT0"},
-  {XDM_PERF_PMSTAT1   ,"PMSTAT1"},
-  {XDM_PERF_PMSTAT2   ,"PMSTAT2"},
-  {XDM_PERF_PMSTAT3   ,"PMSTAT3"},
-  {XDM_PERF_PMSTAT4   ,"PMSTAT4"},
-  {XDM_PERF_PMSTAT5   ,"PMSTAT5"},
-  {XDM_PERF_PMSTAT6   ,"PMSTAT6"},
-  {XDM_PERF_PMSTAT7   ,"PMSTAT7"},
-
-  {XDM_MISC_PWRCTL    ,"PWRCTL"  },
-  {XDM_MISC_PWRSTAT   ,"PWRSTAT" },
-  {XDM_MISC_ERISTAT   ,"ERISTAT" },
-  {XDM_MISC_DATETIME  ,"DATETIME"},
-  {XDM_MISC_UBID      ,"UBID"    },
-  {XDM_MISC_CID       ,"CID"     },
-
-  {XDM_CS_ITCTRL      ,"ITCTRL"     },
-  {XDM_CS_CLAIMSET    ,"CLAIMSET"   },
-  {XDM_CS_CLAIMCLR    ,"CLAIMCLR"   },
-  {XDM_CS_LOCK_ACCESS ,"LOCK_ACCESS"},
-  {XDM_CS_LOCK_STATUS ,"LOCK_STATUS"},
-  {XDM_CS_AUTH_STATUS ,"AUTH_STATUS"},
-  {XDM_CS_DEV_ID      ,"DEV_ID"     },
-  {XDM_CS_DEV_TYPE    ,"DEV_TYPE"   },
-  {XDM_CS_PER_ID4     ,"PER_ID4"    },
-  {XDM_CS_PER_ID5     ,"PER_ID5"    },
-  {XDM_CS_PER_ID6     ,"PER_ID6"    },
-  {XDM_CS_PER_ID7     ,"PER_ID7"    },
-  {XDM_CS_PER_ID0     ,"PER_ID0"    },
-  {XDM_CS_PER_ID1     ,"PER_ID1"    },
-  {XDM_CS_PER_ID2     ,"PER_ID2"    },
-  {XDM_CS_PER_ID3     ,"PER_ID3"    },
-  {XDM_CS_COMP_ID0    ,"COMP_ID0"   },
-  {XDM_CS_COMP_ID1    ,"COMP_ID1"   },
-  {XDM_CS_COMP_ID2    ,"COMP_ID2"   },
-  {XDM_CS_COMP_ID3    ,"COMP_ID3"   },
-  {-1                 ,"???"        },
-};
-#endif
-
-#endif
-
-#endif /* _XDM_REGS_H_ */
diff --git a/tools/sdk/include/esp32/xtensa/xt_perf_consts.h b/tools/sdk/include/esp32/xtensa/xt_perf_consts.h
deleted file mode 100644
index f063a31f775..00000000000
--- a/tools/sdk/include/esp32/xtensa/xt_perf_consts.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * Customer ID=11656; Build=0x5f626; Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef __XT_PERF_CONSTS_H__
-#define __XT_PERF_CONSTS_H__
-
-/*
- * Performance monitor counter selectors
- */
-
-#define XTPERF_CNT_COMMITTED_INSN        0x8002  /* Instructions committed          */
-#define XTPERF_CNT_BRANCH_PENALTY        0x8003  /* Branch penalty cycles           */
-#define XTPERF_CNT_PIPELINE_INTERLOCKS   0x8004  /* Pipeline interlocks cycles      */
-#define XTPERF_CNT_ICACHE_MISSES         0x8005  /* ICache misses penalty in cycles */
-#define XTPERF_CNT_DCACHE_MISSES         0x8006  /* DCache misses penalty in cycles */
-
-#define XTPERF_CNT_CYCLES         0  /* Count cycles */
-#define XTPERF_CNT_OVERFLOW       1  /* Overflow of counter n-1 (assuming this is counter n) */  
-#define XTPERF_CNT_INSN           2  /* Successfully completed instructions */
-#define XTPERF_CNT_D_STALL        3  /* Data-related GlobalStall cycles */
-#define XTPERF_CNT_I_STALL        4  /* Instruction-related and other GlobalStall cycles */
-#define XTPERF_CNT_EXR            5  /* Exceptions and pipeline replays */
-#define XTPERF_CNT_BUBBLES        6  /* Hold and other bubble cycles */
-#define XTPERF_CNT_I_TLB          7  /* Instruction TLB Accesses (per instruction retiring) */
-#define XTPERF_CNT_I_MEM          8  /* Instruction memory accesses (per instruction retiring) */
-#define XTPERF_CNT_D_TLB          9  /* Data TLB accesses */
-#define XTPERF_CNT_D_LOAD_U1      10 /* Data memory load instruction (load-store unit 1) */
-#define XTPERF_CNT_D_STORE_U1     11 /* Data memory store instruction (load-store unit 1) */
-#define XTPERF_CNT_D_ACCESS_U1    12 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 1) */
-#define XTPERF_CNT_D_LOAD_U2      13 /* Data memory load instruction (load-store unit 2) */
-#define XTPERF_CNT_D_STORE_U2     14 /* Data memory store instruction (load-store unit 2) */
-#define XTPERF_CNT_D_ACCESS_U2    15 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 2) */
-#define XTPERF_CNT_D_LOAD_U3      16 /* Data memory load instruction (load-store unit 3) */
-#define XTPERF_CNT_D_STORE_U3     17 /* Data memory store instruction (load-store unit 3) */
-#define XTPERF_CNT_D_ACCESS_U3    18 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 3) */
-#define XTPERF_CNT_MULTIPLE_LS    22 /* Multiple Load/Store */
-#define XTPERF_CNT_OUTBOUND_PIF   23 /* Outbound PIF transactions */
-#define XTPERF_CNT_INBOUND_PIF    24 /* Inbound PIF transactions */
-#define XTPERF_CNT_PREFETCH       26 /* Prefetch events */
-
-
-/*
- * Masks for each of the selector listed above
- */
-
-/* XTPERF_CNT_COMMITTED_INSN selector mask */
-
-#define XTPERF_MASK_COMMITTED_INSN               0x0001
-
-/* XTPERF_CNT_BRANCH_PENALTY selector mask */
- 
-#define XTPERF_MASK_BRANCH_PENALTY               0x0001
-
-/* XTPERF_CNT_PIPELINE_INTERLOCKS selector mask */
-
-#define XTPERF_MASK_PIPELINE_INTERLOCKS          0x0001
-
-/* XTPERF_CNT_ICACHE_MISSES selector mask */ 
-
-#define XTPERF_MASK_ICACHE_MISSES                0x0001
-
-/* XTPERF_CNT_DCACHE_MISSES selector mask */ 
-
-#define XTPERF_MASK_DCACHE_MISSES                0x0001
-
-/* XTPERF_CNT_CYCLES selector mask */
-
-#define XTPERF_MASK_CYCLES                       0x0001
-
-/* XTPERF_CNT_OVERFLOW selector mask */
-
-#define XTPERF_MASK_OVERFLOW                     0x0001
-
-/*
- * XTPERF_CNT_INSN selector mask
- */
-
-#define XTPERF_MASK_INSN_ALL                     0x8DFF
-
-#define XTPERF_MASK_INSN_JX                      0x0001 /* JX */
-#define XTPERF_MASK_INSN_CALLX                   0x0002 /* CALLXn */
-#define XTPERF_MASK_INSN_RET                     0x0004 /* call return i.e. RET, RETW */
-#define XTPERF_MASK_INSN_RF                      0x0008 /* supervisor return i.e. RFDE, RFE, RFI, RFWO, RFWU */
-#define XTPERF_MASK_INSN_BRANCH_TAKEN            0x0010 /* Conditional branch taken, or loopgtz/loopnez skips loop */
-#define XTPERF_MASK_INSN_J                       0x0020 /* J */
-#define XTPERF_MASK_INSN_CALL                    0x0040 /* CALLn */
-#define XTPERF_MASK_INSN_BRANCH_NOT_TAKEN        0x0080 /* Conditional branch fall through (aka. not-taken branch) */
-#define XTPERF_MASK_INSN_LOOP_TAKEN              0x0100 /* Loop instr falls into loop (aka. taken loop) */
-#define XTPERF_MASK_INSN_LOOP_BEG                0x0400 /* Loopback taken to LBEG */
-#define XTPERF_MASK_INSN_LOOP_END                0x0800 /* Loopback falls through to LEND */
-#define XTPERF_MASK_INSN_NON_BRANCH              0x8000 /* Non-branch instruction (aka. non-CTI) */
-
-/*
- * XTPERF_CNT_D_STALL selector mask
- */
-
-#define XTPERF_MASK_D_STALL_ALL                  0x01FE
-
-#define XTPERF_MASK_D_STALL_STORE_BUF_FULL       0x0002 /* Store buffer full stall */
-#define XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT   0x0004 /* Store buffer conflict stall */
-#define XTPERF_MASK_D_STALL_CACHE_MISS           0x0008 /* DCache-miss stall */
-#define XTPERF_MASK_D_STALL_BUSY                 0x0010 /* Data RAM/ROM/XLMI busy stall */
-#define XTPERF_MASK_D_STALL_IN_PIF               0x0020 /* Data inbound-PIF request stall (incl s32c1i) */
-#define XTPERF_MASK_D_STALL_MHT_LOOKUP           0x0040 /* MHT lookup stall */
-#define XTPERF_MASK_D_STALL_UNCACHED_LOAD        0x0080 /* Uncached load stall (included in MHT lookup stall) */
-#define XTPERF_MASK_D_STALL_BANK_CONFLICT        0x0100 /* Bank-conflict stall */
-
-/*
- * XTPERF_CNT_I_STALL selector mask
- */
-
-#define XTPERF_MASK_I_STALL_ALL                  0x01FF
-
-#define XTPERF_MASK_I_STALL_CACHE_MISS           0x0001 /* ICache-miss stall */
-#define XTPERF_MASK_I_STALL_BUSY                 0x0002 /* Instruction RAM/ROM busy stall */
-#define XTPERF_MASK_I_STALL_IN_PIF               0x0004 /* Instruction RAM inbound-PIF request stall */
-#define XTPERF_MASK_I_STALL_TIE_PORT             0x0008 /* TIE port stall */
-#define XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL      0x0010 /* External RunStall signal status */
-#define XTPERF_MASK_I_STALL_UNCACHED_FETCH       0x0020 /* Uncached fetch stall */
-#define XTPERF_MASK_I_STALL_FAST_L32R            0x0040 /* FastL32R stall */
-#define XTPERF_MASK_I_STALL_ITERATIVE_MUL        0x0080 /* Iterative multiply stall */
-#define XTPERF_MASK_I_STALL_ITERATIVE_DIV        0x0100 /* Iterative divide stall */
-
-/*
- * XTPERF_CNT_EXR selector mask
- */
-
-#define XTPERF_MASK_EXR_ALL                      0x01FF
-
-#define XTPERF_MASK_EXR_REPLAYS                  0x0001 /* Other Pipeline Replay (i.e. excludes $ miss etc.) */
-#define XTPERF_MASK_EXR_LEVEL1_INT               0x0002 /* Level-1 interrupt */
-#define XTPERF_MASK_EXR_LEVELH_INT               0x0004 /* Greater-than-level-1 interrupt */
-#define XTPERF_MASK_EXR_DEBUG                    0x0008 /* Debug exception */
-#define XTPERF_MASK_EXR_NMI                      0x0010 /* NMI */
-#define XTPERF_MASK_EXR_WINDOW                   0x0020 /* Window exception */
-#define XTPERF_MASK_EXR_ALLOCA                   0x0040 /* Alloca exception */
-#define XTPERF_MASK_EXR_OTHER                    0x0080 /* Other exceptions */
-#define XTPERF_MASK_EXR_MEM_ERR                  0x0100 /* HW-corrected memory error */
-
-/*
- * XTPERF_CNT_BUBBLES selector mask
- */
-
-#define XTPERF_MASK_BUBBLES_ALL                   0x01FD
-
-#define XTPERF_MASK_BUBBLES_PSO                   0x0001 /* Processor domain PSO bubble */
-#define XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS   0x0004 /* R hold caused by DCache miss */
-#define XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE  0x0008 /* R hold caused by Store release */
-#define XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP        0x0010 /* R hold caused by register dependency */
-#define XTPERF_MASK_BUBBLES_R_HOLD_WAIT           0x0020 /* R hold caused by MEMW, EXTW or EXCW */
-#define XTPERF_MASK_BUBBLES_R_HOLD_HALT           0x0040 /* R hold caused by Halt instruction (TX only) */
-#define XTPERF_MASK_BUBBLES_CTI                   0x0080 /* CTI bubble (e.g. branch delay slot) */
-#define XTPERF_MASK_BUBBLES_WAITI                 0x0100 /* WAITI bubble */
-
-/*
- * XTPERF_CNT_I_TLB selector mask
- */
-
-#define XTPERF_MASK_I_TLB_ALL                     0x000F
-
-#define XTPERF_MASK_I_TLB_HITS                    0x0001 /* Hit */
-#define XTPERF_MASK_I_TLB_REPLAYS                 0x0002 /* Replay of instruction due to ITLB miss */
-#define XTPERF_MASK_I_TLB_REFILLS                 0x0004 /* HW-assisted TLB Refill completes */
-#define XTPERF_MASK_I_TLB_MISSES                  0x0008 /* ITLB Miss Exception */
-
-/*
- * XTPERF_CNT_I_MEM selector mask
- */
-
-#define XTPERF_MASK_I_MEM_ALL                     0x000F
-
-#define XTPERF_MASK_I_MEM_CACHE_HITS              0x0001 /* ICache Hit */
-#define XTPERF_MASK_I_MEM_CACHE_MISSES            0x0002 /* ICache Miss (includes uncached) */
-#define XTPERF_MASK_I_MEM_IRAM                    0x0004 /* InstRAM or InstROM */
-#define XTPERF_MASK_I_MEM_BYPASS                  0x0008 /* Bypass (i.e. uncached) fetch */
-
-/*
- * XTPERF_CNT_D_TLB selector mask
- */
-
-#define XTPERF_MASK_D_TLB_ALL                     0x000F
-
-#define XTPERF_MASK_D_TLB_HITS                    0x0001 /* Hit */
-#define XTPERF_MASK_D_TLB_REPLAYS                 0x0002 /* Replay of instruction due to DTLB miss */
-#define XTPERF_MASK_D_TLB_REFILLS                 0x0004 /* HW-assisted TLB Refill completes */
-#define XTPERF_MASK_D_TLB_MISSES                  0x0008 /* DTLB Miss Exception */
-
-/*
- * XTPERF_CNT_D_LOAD_U* selector mask
- */
-
-#define XTPERF_MASK_D_LOAD_ALL                    0x000F
-
-#define XTPERF_MASK_D_LOAD_CACHE_HITS             0x0001 /* Cache Hit */
-#define XTPERF_MASK_D_LOAD_CACHE_MISSES           0x0002 /* Cache Miss */
-#define XTPERF_MASK_D_LOAD_LOCAL_MEM              0x0004 /* Local memory hit */
-#define XTPERF_MASK_D_LOAD_BYPASS                 0x0008 /* Bypass (i.e. uncached) load */
-
-/*
- * XTPERF_CNT_D_STORE_U* selector mask
- */
-
-#define XTPERF_MASK_D_STORE_ALL                    0x000F
-
-#define XTPERF_MASK_D_STORE_CACHE_HITS             0x0001 /* DCache Hit */
-#define XTPERF_MASK_D_STORE_CACHE_MISSES           0x0002 /* DCache Miss */
-#define XTPERF_MASK_D_STORE_LOCAL_MEM              0x0004 /* Local memory hit */
-#define XTPERF_MASK_D_STORE_PIF                    0x0008 /* PIF Store */
-
-/*
- * XTPERF_CNT_D_ACCESS_U* selector mask
- */
-
-#define XTPERF_MASK_D_ACCESS_ALL                   0x000F
-
-#define XTPERF_MASK_D_ACCESS_CACHE_MISSES          0x0001 /* DCache Miss */
-#define XTPERF_MASK_D_ACCESS_HITS_SHARED           0x0002 /* Hit Shared */
-#define XTPERF_MASK_D_ACCESS_HITS_EXCLUSIVE        0x0004 /* Hit Exclusive */
-#define XTPERF_MASK_D_ACCESS_HITS_MODIFIED         0x0008 /* Hit Modified */
-
-/*
- * XTPERF_CNT_MULTIPLE_LS selector mask
- */
-
-#define XTPERF_MASK_MULTIPLE_LS_ALL                0x003F
-
-#define XTPERF_MASK_MULTIPLE_LS_0S_0L              0x0001 /* 0 stores and 0 loads */
-#define XTPERF_MASK_MULTIPLE_LS_0S_1L              0x0002 /* 0 stores and 1 loads */
-#define XTPERF_MASK_MULTIPLE_LS_1S_0L              0x0004 /* 1 stores and 0 loads */
-#define XTPERF_MASK_MULTIPLE_LS_1S_1L              0x0008 /* 1 stores and 1 loads */
-#define XTPERF_MASK_MULTIPLE_LS_0S_2L              0x0010 /* 0 stores and 2 loads */
-#define XTPERF_MASK_MULTIPLE_LS_2S_0L              0x0020 /* 2 stores and 0 loads */
-
-/*
- * XTPERF_CNT_OUTBOUND_PIF selector mask
- */
-
-#define XTPERF_MASK_OUTBOUND_PIF_ALL               0x0003
-
-#define XTPERF_MASK_OUTBOUND_PIF_CASTOUT           0x0001 /* Castout */
-#define XTPERF_MASK_OUTBOUND_PIF_PREFETCH          0x0002 /* Prefetch */
-
-/*
- * XTPERF_CNT_INBOUND_PIF selector mask
- */
-
-#define XTPERF_MASK_INBOUND_PIF_ALL                0x0003
-
-#define XTPERF_MASK_INBOUND_PIF_I_DMA              0x0001 /* Instruction DMA */
-#define XTPERF_MASK_INBOUND_PIF_D_DMA              0x0002 /* Data DMA */
-
-/*
- * XTPERF_CNT_PREFETCH selector mask
- */
-
-#define XTPERF_MASK_PREFETCH_ALL                   0x002F
-
-#define XTPERF_MASK_PREFETCH_I_HIT                 0x0001 /* I prefetch-buffer-lookup hit */
-#define XTPERF_MASK_PREFETCH_D_HIT                 0x0002 /* D prefetch-buffer-lookup hit */
-#define XTPERF_MASK_PREFETCH_I_MISS                0x0004 /* I prefetch-buffer-lookup miss */
-#define XTPERF_MASK_PREFETCH_D_MISS                0x0008 /* D prefetch-buffer-lookup miss */
-#define XTPERF_MASK_PREFETCH_D_L1_FILL             0x0020 /* Fill directly to DCache L1 */
-
-#endif /* __XT_PERF_CONSTS_H__ */
diff --git a/tools/sdk/include/esp32/xtensa/xtensa-libdb-macros.h b/tools/sdk/include/esp32/xtensa/xtensa-libdb-macros.h
deleted file mode 100644
index fbbe50964c0..00000000000
--- a/tools/sdk/include/esp32/xtensa/xtensa-libdb-macros.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- *  xtensa-libdb-macros.h
- */
-
-/* $Id: //depot/rel/Eaglenest/Xtensa/Software/libdb/xtensa-libdb-macros.h#1 $ */
-
-/* Copyright (c) 2004-2008 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef __H_LIBDB_MACROS
-#define __H_LIBDB_MACROS
-
-/*
- *  This header file provides macros used to construct, identify and use
- *  "target numbers" that are assigned to various types of Xtensa processor
- *  registers and states.  These target numbers are used by GDB in the remote
- *  protocol, and are thus used by all GDB debugger agents (targets).
- *  They are also used in ELF debugger information sections (stabs, dwarf, etc).
- *
- *  These macros are separated from xtensa-libdb.h because they are needed
- *  by certain debugger agents that do not use or have access to libdb,
- *  e.g. the OCD daemon, RedBoot, XMON, etc.
- *
- *  For the time being, for compatibility with certain 3rd party debugger
- *  software vendors, target numbers are limited to 16 bits.  It is
- *  conceivable that this will be extended in the future to 32 bits.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef uint32
- #define uint32	unsigned int
-#endif
-#ifndef int32
- #define int32	int
-#endif
-
-
-/*
- *  Macros to form register "target numbers" for various standard registers/states:
- */
-#define XTENSA_DBREGN_INVALID		-1		/* not a valid target number */
-#define XTENSA_DBREGN_A(n)		(0x0000+(n))	/* address registers a0..a15 */
-#define XTENSA_DBREGN_B(n)		(0x0010+(n))	/* boolean bits b0..b15 */
-#define XTENSA_DBREGN_PC		 0x0020		/* program counter */
-				      /* 0x0021		   RESERVED for use by Tensilica */
-#define XTENSA_DBREGN_BO(n)		(0x0022+(n))	/* boolean octuple-bits bo0..bo1 */
-#define XTENSA_DBREGN_BQ(n)		(0x0024+(n))	/* boolean quadruple-bits bq0..bq3 */
-#define XTENSA_DBREGN_BD(n)		(0x0028+(n))	/* boolean double-bits bd0..bd7 */
-#define XTENSA_DBREGN_F(n)		(0x0030+(n))	/* floating point registers f0..f15 */
-#define XTENSA_DBREGN_VEC(n)		(0x0040+(n))	/* Vectra vec regs v0..v15 */
-#define XTENSA_DBREGN_VSEL(n)		(0x0050+(n))	/* Vectra sel s0..s3 (V1) ..s7 (V2) */
-#define XTENSA_DBREGN_VALIGN(n)		(0x0058+(n))	/* Vectra valign regs u0..u3 */
-#define XTENSA_DBREGN_VCOEFF(n)		(0x005C+(n))	/* Vectra I vcoeff regs c0..c1 */
-				      /* 0x005E..0x005F	   RESERVED for use by Tensilica */
-#define XTENSA_DBREGN_AEP(n)		(0x0060+(n))	/* HiFi2 Audio Engine regs aep0..aep7 */
-#define XTENSA_DBREGN_AEQ(n)		(0x0068+(n))	/* HiFi2 Audio Engine regs aeq0..aeq3 */
-				      /* 0x006C..0x00FF	   RESERVED for use by Tensilica */
-#define XTENSA_DBREGN_AR(n)		(0x0100+(n))	/* physical address regs ar0..ar63
-							   (note: only with window option) */
-				      /* 0x0140..0x01FF	   RESERVED for use by Tensilica */
-#define XTENSA_DBREGN_SREG(n)		(0x0200+(n))	/* special registers 0..255 (core) */
-#define XTENSA_DBREGN_BR		XTENSA_DBREGN_SREG(0x04)	/* all 16 boolean bits, BR */
-#define XTENSA_DBREGN_MR(n)		XTENSA_DBREGN_SREG(0x20+(n))	/* MAC16 registers m0..m3 */
-#define XTENSA_DBREGN_UREG(n)		(0x0300+(n))	/* user registers 0..255 (TIE) */
-				      /* 0x0400..0x0FFF	   RESERVED for use by Tensilica */
-				      /* 0x1000..0x1FFF	   user-defined regfiles */
-				      /* 0x2000..0xEFFF	   other states (and regfiles) */
-#define XTENSA_DBREGN_DBAGENT(n)	(0xF000+(n))	/* non-processor "registers" 0..4095 for
-							   3rd-party debugger agent defined use */
-				      /* > 0xFFFF (32-bit) RESERVED for use by Tensilica */
-/*#define XTENSA_DBREGN_CONTEXT(n)	(0x02000000+((n)<<20))*/	/* add this macro's value to a target
-							   number to identify a specific context 0..31
-							   for context-replicated registers */
-#define XTENSA_DBREGN_MASK		0xFFFF		/* mask of valid target_number bits */
-#define XTENSA_DBREGN_WRITE_SIDE	0x04000000	/* flag to request write half of a register
-							   split into distinct read and write entries
-							   with the same target number (currently only
-							   valid in a couple of libdb API functions;
-							   see xtensa-libdb.h for details) */
-
-/*
- *  Macros to identify specific ranges of target numbers (formed above):
- *  NOTE:  any context number (or other upper 12 bits) are considered
- *  modifiers and are thus stripped out for identification purposes.
- */
-#define XTENSA_DBREGN_IS_VALID(tn)	(((tn) & ~0xFFFF) == 0)	/* just tests it's 16-bit unsigned */
-#define XTENSA_DBREGN_IS_A(tn)		(((tn) & 0xFFF0)==0x0000)	/* is a0..a15 */
-#define XTENSA_DBREGN_IS_B(tn)		(((tn) & 0xFFF0)==0x0010)	/* is b0..b15 */
-#define XTENSA_DBREGN_IS_PC(tn)		(((tn) & 0xFFFF)==0x0020)	/* is program counter */
-#define XTENSA_DBREGN_IS_BO(tn)		(((tn) & 0xFFFE)==0x0022)	/* is bo0..bo1 */
-#define XTENSA_DBREGN_IS_BQ(tn)		(((tn) & 0xFFFC)==0x0024)	/* is bq0..bq3 */
-#define XTENSA_DBREGN_IS_BD(tn)		(((tn) & 0xFFF8)==0x0028)	/* is bd0..bd7 */
-#define XTENSA_DBREGN_IS_F(tn)		(((tn) & 0xFFF0)==0x0030)	/* is f0..f15 */
-#define XTENSA_DBREGN_IS_VEC(tn)	(((tn) & 0xFFF0)==0x0040)	/* is v0..v15 */
-#define XTENSA_DBREGN_IS_VSEL(tn)	(((tn) & 0xFFF8)==0x0050)	/* is s0..s7 (s0..s3 in V1) */
-#define XTENSA_DBREGN_IS_VALIGN(tn)	(((tn) & 0xFFFC)==0x0058)	/* is u0..u3 */
-#define XTENSA_DBREGN_IS_VCOEFF(tn)	(((tn) & 0xFFFE)==0x005C)	/* is c0..c1 */
-#define XTENSA_DBREGN_IS_AEP(tn)	(((tn) & 0xFFF8)==0x0060)	/* is aep0..aep7 */
-#define XTENSA_DBREGN_IS_AEQ(tn)	(((tn) & 0xFFFC)==0x0068)	/* is aeq0..aeq3 */
-#define XTENSA_DBREGN_IS_AR(tn)		(((tn) & 0xFFC0)==0x0100)	/* is ar0..ar63 */
-#define XTENSA_DBREGN_IS_SREG(tn)	(((tn) & 0xFF00)==0x0200)	/* is special register */
-#define XTENSA_DBREGN_IS_BR(tn)		(((tn) & 0xFFFF)==XTENSA_DBREGN_SREG(0x04))	/* is BR */
-#define XTENSA_DBREGN_IS_MR(tn)		(((tn) & 0xFFFC)==XTENSA_DBREGN_SREG(0x20))	/* m0..m3 */
-#define XTENSA_DBREGN_IS_UREG(tn)	(((tn) & 0xFF00)==0x0300)	/* is user register */
-#define XTENSA_DBREGN_IS_DBAGENT(tn)	(((tn) & 0xF000)==0xF000)	/* is non-processor */
-/*#define XTENSA_DBREGN_IS_CONTEXT(tn)	(((tn) & 0x02000000) != 0)*/	/* specifies context # */
-
-/*
- *  Macros to extract register index from a register "target number"
- *  when a specific range has been identified using one of the _IS_ macros above.
- *  These macros only return a useful value if the corresponding _IS_ macro returns true.
- */
-#define XTENSA_DBREGN_A_INDEX(tn)	((tn) & 0x0F)		/* 0..15  for a0..a15 */
-#define XTENSA_DBREGN_B_INDEX(tn)	((tn) & 0x0F)		/* 0..15  for b0..b15 */
-#define XTENSA_DBREGN_BO_INDEX(tn)	((tn) & 0x01)		/* 0..1   for bo0..bo1 */
-#define XTENSA_DBREGN_BQ_INDEX(tn)	((tn) & 0x03)		/* 0..3   for bq0..bq3 */
-#define XTENSA_DBREGN_BD_INDEX(tn)	((tn) & 0x07)		/* 0..7   for bd0..bd7 */
-#define XTENSA_DBREGN_F_INDEX(tn)	((tn) & 0x0F)		/* 0..15  for f0..f15 */
-#define XTENSA_DBREGN_VEC_INDEX(tn)	((tn) & 0x0F)		/* 0..15  for v0..v15 */
-#define XTENSA_DBREGN_VSEL_INDEX(tn)	((tn) & 0x07)		/* 0..7   for s0..s7 */
-#define XTENSA_DBREGN_VALIGN_INDEX(tn)	((tn) & 0x03)		/* 0..3   for u0..u3 */
-#define XTENSA_DBREGN_VCOEFF_INDEX(tn)	((tn) & 0x01)		/* 0..1   for c0..c1 */
-#define XTENSA_DBREGN_AEP_INDEX(tn)	((tn) & 0x07)		/* 0..7   for aep0..aep7 */
-#define XTENSA_DBREGN_AEQ_INDEX(tn)	((tn) & 0x03)		/* 0..3   for aeq0..aeq3 */
-#define XTENSA_DBREGN_AR_INDEX(tn)	((tn) & 0x3F)		/* 0..63  for ar0..ar63 */
-#define XTENSA_DBREGN_SREG_INDEX(tn)	((tn) & 0xFF)		/* 0..255 for special registers */
-#define XTENSA_DBREGN_MR_INDEX(tn)	((tn) & 0x03)		/* 0..3   for m0..m3 */
-#define XTENSA_DBREGN_UREG_INDEX(tn)	((tn) & 0xFF)		/* 0..255 for user registers */
-#define XTENSA_DBREGN_DBAGENT_INDEX(tn)	((tn) & 0xFFF)		/* 0..4095 for non-processor */
-/*#define XTENSA_DBREGN_CONTEXT_INDEX(tn)	(((tn) >> 20) & 0x1F)*/	/* 0..31  context numbers */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-      
-#endif /* __H_LIBDB_MACROS */
-
diff --git a/tools/sdk/include/esp32/xtensa/xtensa-versions.h b/tools/sdk/include/esp32/xtensa/xtensa-versions.h
deleted file mode 100644
index abed3a18dc9..00000000000
--- a/tools/sdk/include/esp32/xtensa/xtensa-versions.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
-   xtensa-versions.h -- definitions of Xtensa version and release numbers
-
-   This file defines most Xtensa-related product versions and releases
-   that exist so far.
-   It also provides a bit of information about which ones are current.
-   This file changes every release, as versions/releases get added.
-
-
-   $Id: //depot/rel/Eaglenest/Xtensa/Software/misc/xtensa-versions.h.tpp#2 $
-
-   Copyright (c) 2006-2010 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef XTENSA_VERSIONS_H
-#define XTENSA_VERSIONS_H
-
-
-/*
- *  NOTE:  A "release" is a collection of product versions
- *	made available at once (together) to customers.
- *	In the past, release and version names all matched in T####.# form,
- *	making the distinction irrelevant.
- *	Starting with the RA-2004.1 release, this is no longer the case.
- */
-
-
-/* Hardware (Xtensa/Diamond processor) versions:  */
-#define XTENSA_HWVERSION_T1020_0	102000	/* versions T1020.0 */
-#define  XTENSA_HWCIDSCHEME_T1020_0	 10
-#define  XTENSA_HWCIDVERS_T1020_0	 2
-#define XTENSA_HWVERSION_T1020_1	102001	/* versions T1020.1 */
-#define  XTENSA_HWCIDSCHEME_T1020_1	 10
-#define  XTENSA_HWCIDVERS_T1020_1	 3
-#define XTENSA_HWVERSION_T1020_2B	102002	/* versions T1020.2b */
-#define  XTENSA_HWCIDSCHEME_T1020_2B	 10
-#define  XTENSA_HWCIDVERS_T1020_2B	 5
-#define XTENSA_HWVERSION_T1020_2	102002	/* versions T1020.2 */
-#define  XTENSA_HWCIDSCHEME_T1020_2	 10
-#define  XTENSA_HWCIDVERS_T1020_2	 4
-#define XTENSA_HWVERSION_T1020_3	102003	/* versions T1020.3 */
-#define  XTENSA_HWCIDSCHEME_T1020_3	 10
-#define  XTENSA_HWCIDVERS_T1020_3	 6
-#define XTENSA_HWVERSION_T1020_4	102004	/* versions T1020.4 */
-#define  XTENSA_HWCIDSCHEME_T1020_4	 10
-#define  XTENSA_HWCIDVERS_T1020_4	 7
-#define XTENSA_HWVERSION_T1030_0	103000	/* versions T1030.0 */
-#define  XTENSA_HWCIDSCHEME_T1030_0	 10
-#define  XTENSA_HWCIDVERS_T1030_0	 9
-#define XTENSA_HWVERSION_T1030_1	103001	/* versions T1030.1 */
-#define  XTENSA_HWCIDSCHEME_T1030_1	 10
-#define  XTENSA_HWCIDVERS_T1030_1	 10
-#define XTENSA_HWVERSION_T1030_2	103002	/* versions T1030.2 */
-#define  XTENSA_HWCIDSCHEME_T1030_2	 10
-#define  XTENSA_HWCIDVERS_T1030_2	 11
-#define XTENSA_HWVERSION_T1030_3	103003	/* versions T1030.3 */
-#define  XTENSA_HWCIDSCHEME_T1030_3	 10
-#define  XTENSA_HWCIDVERS_T1030_3	 12
-#define XTENSA_HWVERSION_T1040_0	104000	/* versions T1040.0 */
-#define  XTENSA_HWCIDSCHEME_T1040_0	 10
-#define  XTENSA_HWCIDVERS_T1040_0	 15
-#define XTENSA_HWVERSION_T1040_1	104001	/* versions T1040.1 */
-#define  XTENSA_HWCIDSCHEME_T1040_1	 01
-#define  XTENSA_HWCIDVERS_T1040_1	 32
-#define XTENSA_HWVERSION_T1040_1P	104001	/* versions T1040.1-prehotfix */
-#define  XTENSA_HWCIDSCHEME_T1040_1P	 10
-#define  XTENSA_HWCIDVERS_T1040_1P	 16
-#define XTENSA_HWVERSION_T1040_2	104002	/* versions T1040.2 */
-#define  XTENSA_HWCIDSCHEME_T1040_2	 01
-#define  XTENSA_HWCIDVERS_T1040_2	 33
-#define XTENSA_HWVERSION_T1040_3	104003	/* versions T1040.3 */
-#define  XTENSA_HWCIDSCHEME_T1040_3	 01
-#define  XTENSA_HWCIDVERS_T1040_3	 34
-#define XTENSA_HWVERSION_T1050_0	105000	/* versions T1050.0 */
-#define  XTENSA_HWCIDSCHEME_T1050_0	 1100
-#define  XTENSA_HWCIDVERS_T1050_0	 1
-#define XTENSA_HWVERSION_T1050_1	105001	/* versions T1050.1 */
-#define  XTENSA_HWCIDSCHEME_T1050_1	 1100
-#define  XTENSA_HWCIDVERS_T1050_1	 2
-#define XTENSA_HWVERSION_T1050_2	105002	/* versions T1050.2 */
-#define  XTENSA_HWCIDSCHEME_T1050_2	 1100
-#define  XTENSA_HWCIDVERS_T1050_2	 4
-#define XTENSA_HWVERSION_T1050_3	105003	/* versions T1050.3 */
-#define  XTENSA_HWCIDSCHEME_T1050_3	 1100
-#define  XTENSA_HWCIDVERS_T1050_3	 6
-#define XTENSA_HWVERSION_T1050_4	105004	/* versions T1050.4 */
-#define  XTENSA_HWCIDSCHEME_T1050_4	 1100
-#define  XTENSA_HWCIDVERS_T1050_4	 7
-#define XTENSA_HWVERSION_T1050_5	105005	/* versions T1050.5 */
-#define  XTENSA_HWCIDSCHEME_T1050_5	 1100
-#define  XTENSA_HWCIDVERS_T1050_5	 8
-#define XTENSA_HWVERSION_RA_2004_1	210000	/* versions LX1.0.0 */
-#define  XTENSA_HWCIDSCHEME_RA_2004_1	 1100
-#define  XTENSA_HWCIDVERS_RA_2004_1	 3
-#define XTENSA_HWVERSION_RA_2005_1	210001	/* versions LX1.0.1 */
-#define  XTENSA_HWCIDSCHEME_RA_2005_1	 1100
-#define  XTENSA_HWCIDVERS_RA_2005_1	 20
-#define XTENSA_HWVERSION_RA_2005_2	210002	/* versions LX1.0.2 */
-#define  XTENSA_HWCIDSCHEME_RA_2005_2	 1100
-#define  XTENSA_HWCIDVERS_RA_2005_2	 21
-#define XTENSA_HWVERSION_RA_2005_3	210003	/* versions LX1.0.3, X6.0.3 */
-#define  XTENSA_HWCIDSCHEME_RA_2005_3	 1100
-#define  XTENSA_HWCIDVERS_RA_2005_3	 22
-#define XTENSA_HWVERSION_RA_2006_4	210004	/* versions LX1.0.4, X6.0.4 */
-#define  XTENSA_HWCIDSCHEME_RA_2006_4	 1100
-#define  XTENSA_HWCIDVERS_RA_2006_4	 23
-#define XTENSA_HWVERSION_RA_2006_5	210005	/* versions LX1.0.5, X6.0.5 */
-#define  XTENSA_HWCIDSCHEME_RA_2006_5	 1100
-#define  XTENSA_HWCIDVERS_RA_2006_5	 24
-#define XTENSA_HWVERSION_RA_2006_6	210006	/* versions LX1.0.6, X6.0.6 */
-#define  XTENSA_HWCIDSCHEME_RA_2006_6	 1100
-#define  XTENSA_HWCIDVERS_RA_2006_6	 25
-#define XTENSA_HWVERSION_RA_2007_7	210007	/* versions LX1.0.7, X6.0.7 */
-#define  XTENSA_HWCIDSCHEME_RA_2007_7	 1100
-#define  XTENSA_HWCIDVERS_RA_2007_7	 26
-#define XTENSA_HWVERSION_RA_2008_8	210008	/* versions LX1.0.8, X6.0.8 */
-#define  XTENSA_HWCIDSCHEME_RA_2008_8	 1100
-#define  XTENSA_HWCIDVERS_RA_2008_8	 27
-#define XTENSA_HWVERSION_RB_2006_0	220000	/* versions LX2.0.0, X7.0.0 */
-#define  XTENSA_HWCIDSCHEME_RB_2006_0	 1100
-#define  XTENSA_HWCIDVERS_RB_2006_0	 48
-#define XTENSA_HWVERSION_RB_2007_1	220001	/* versions LX2.0.1, X7.0.1 */
-#define  XTENSA_HWCIDSCHEME_RB_2007_1	 1100
-#define  XTENSA_HWCIDVERS_RB_2007_1	 49
-#define XTENSA_HWVERSION_RB_2007_2	221000	/* versions LX2.1.0, X7.1.0 */
-#define  XTENSA_HWCIDSCHEME_RB_2007_2	 1100
-#define  XTENSA_HWCIDVERS_RB_2007_2	 52
-#define XTENSA_HWVERSION_RB_2008_3	221001	/* versions LX2.1.1, X7.1.1 */
-#define  XTENSA_HWCIDSCHEME_RB_2008_3	 1100
-#define  XTENSA_HWCIDVERS_RB_2008_3	 53
-#define XTENSA_HWVERSION_RB_2008_4	221002	/* versions LX2.1.2, X7.1.2 */
-#define  XTENSA_HWCIDSCHEME_RB_2008_4	 1100
-#define  XTENSA_HWCIDVERS_RB_2008_4	 54
-#define XTENSA_HWVERSION_RB_2009_5	221003	/* versions LX2.1.3, X7.1.3 */
-#define  XTENSA_HWCIDSCHEME_RB_2009_5	 1100
-#define  XTENSA_HWCIDVERS_RB_2009_5	 55
-#define XTENSA_HWVERSION_RB_2007_2_MP	221100	/* versions LX2.1.8-MP, X7.1.8-MP */
-#define  XTENSA_HWCIDSCHEME_RB_2007_2_MP	 1100
-#define  XTENSA_HWCIDVERS_RB_2007_2_MP	 64
-#define XTENSA_HWVERSION_RC_2009_0	230000	/* versions LX3.0.0, X8.0.0, MX1.0.0 */
-#define  XTENSA_HWCIDSCHEME_RC_2009_0	 1100
-#define  XTENSA_HWCIDVERS_RC_2009_0	 65
-#define XTENSA_HWVERSION_RC_2010_1	230001	/* versions LX3.0.1, X8.0.1, MX1.0.1 */
-#define  XTENSA_HWCIDSCHEME_RC_2010_1	 1100
-#define  XTENSA_HWCIDVERS_RC_2010_1	 66
-#define XTENSA_HWVERSION_RC_2010_2	230002	/* versions LX3.0.2, X8.0.2, MX1.0.2 */
-#define  XTENSA_HWCIDSCHEME_RC_2010_2	 1100
-#define  XTENSA_HWCIDVERS_RC_2010_2	 67
-#define XTENSA_HWVERSION_RC_2011_3	230003	/* versions LX3.0.3, X8.0.3, MX1.0.3 */
-#define  XTENSA_HWCIDSCHEME_RC_2011_3	 1100
-#define  XTENSA_HWCIDVERS_RC_2011_3	 68
-#define XTENSA_HWVERSION_RD_2010_0	240000	/* versions LX4.0.0, X9.0.0, MX1.1.0, TX1.0.0 */
-#define  XTENSA_HWCIDSCHEME_RD_2010_0	 1100
-#define  XTENSA_HWCIDVERS_RD_2010_0	 80
-#define XTENSA_HWVERSION_RD_2011_1	240001	/* versions LX4.0.1, X9.0.1, MX1.1.1, TX1.0.1 */
-#define  XTENSA_HWCIDSCHEME_RD_2011_1	 1100
-#define  XTENSA_HWCIDVERS_RD_2011_1	 81
-#define XTENSA_HWVERSION_RD_2011_2	240002	/* versions LX4.0.2, X9.0.2, MX1.1.2, TX1.0.2 */
-#define  XTENSA_HWCIDSCHEME_RD_2011_2	 1100
-#define  XTENSA_HWCIDVERS_RD_2011_2	 82
-#define XTENSA_HWVERSION_RD_2011_3	240003	/* versions LX4.0.3, X9.0.3, MX1.1.3, TX1.0.3 */
-#define  XTENSA_HWCIDSCHEME_RD_2011_3	 1100
-#define  XTENSA_HWCIDVERS_RD_2011_3	 83
-#define XTENSA_HWVERSION_RD_2012_4	240004	/* versions LX4.0.4, X9.0.4, MX1.1.4, TX1.0.4 */
-#define  XTENSA_HWCIDSCHEME_RD_2012_4	 1100
-#define  XTENSA_HWCIDVERS_RD_2012_4	 84
-#define XTENSA_HWVERSION_RD_2012_5	240005	/* versions LX4.0.5, X9.0.5, MX1.1.5, TX1.0.5 */
-#define  XTENSA_HWCIDSCHEME_RD_2012_5	 1100
-#define  XTENSA_HWCIDVERS_RD_2012_5	 85
-#define XTENSA_HWVERSION_RE_2012_0	250000	/* versions LX5.0.0, X10.0.0, MX1.2.0, TX2.0.0 */
-#define  XTENSA_HWCIDSCHEME_RE_2012_0	 1100
-#define  XTENSA_HWCIDVERS_RE_2012_0	 96
-#define XTENSA_HWVERSION_RE_2012_1	250001	/* versions LX5.0.1, X10.0.1, MX1.2.1, TX2.0.1 */
-#define  XTENSA_HWCIDSCHEME_RE_2012_1	 1100
-#define  XTENSA_HWCIDVERS_RE_2012_1	 97
-#define XTENSA_HWVERSION_RE_2013_2	250002	/* versions LX5.0.2, X10.0.2, MX1.2.2, TX2.0.2 */
-#define  XTENSA_HWCIDSCHEME_RE_2013_2	 1100
-#define  XTENSA_HWCIDVERS_RE_2013_2	 98
-#define XTENSA_HWVERSION_RE_2013_3	250003	/* versions LX5.0.3, X10.0.3, MX1.2.3, TX2.0.3 */
-#define  XTENSA_HWCIDSCHEME_RE_2013_3	 1100
-#define  XTENSA_HWCIDVERS_RE_2013_3	 99
-#define XTENSA_HWVERSION_RE_2013_4	250004	/* versions LX5.0.4, X10.0.4, MX1.2.4, TX2.0.4 */
-#define  XTENSA_HWCIDSCHEME_RE_2013_4	 1100
-#define  XTENSA_HWCIDVERS_RE_2013_4	 100
-#define XTENSA_HWVERSION_RE_2014_5	250005	/* versions LX5.0.5, X10.0.5, MX1.2.5, TX2.0.5 */
-#define  XTENSA_HWCIDSCHEME_RE_2014_5	 1100
-#define  XTENSA_HWCIDVERS_RE_2014_5	 101
-#define XTENSA_HWVERSION_RE_2015_6	250006	/* versions LX5.0.6, X10.0.6, MX1.2.6, TX2.0.6 */
-#define  XTENSA_HWCIDSCHEME_RE_2015_6	 1100
-#define  XTENSA_HWCIDVERS_RE_2015_6	 102
-#define XTENSA_HWVERSION_RF_2014_0	260000	/* versions LX6.0.0, X11.0.0, MX1.3.0, TX3.0.0 */
-#define  XTENSA_HWCIDSCHEME_RF_2014_0	 1100
-#define  XTENSA_HWCIDVERS_RF_2014_0	 112
-#define XTENSA_HWVERSION_RF_2014_1	260001	/* versions LX6.0.1, X11.0.1 */
-#define  XTENSA_HWCIDSCHEME_RF_2014_1	 1100
-#define  XTENSA_HWCIDVERS_RF_2014_1	 113
-#define XTENSA_HWVERSION_RF_2015_2	260002	/* versions LX6.0.2, X11.0.2 */
-#define  XTENSA_HWCIDSCHEME_RF_2015_2	 1100
-#define  XTENSA_HWCIDVERS_RF_2015_2	 114
-#define XTENSA_HWVERSION_RF_2015_3	260003	/* versions LX6.0.3, X11.0.3 */
-#define  XTENSA_HWCIDSCHEME_RF_2015_3	 1100
-#define  XTENSA_HWCIDVERS_RF_2015_3	 115
-#define XTENSA_HWVERSION_RG_2015_0	270000	/* versions LX7.0.0, X12.0.0, NX1.0.0, SX1.0.0, MX1.4.0, TX4.0.0 */
-#define  XTENSA_HWCIDSCHEME_RG_2015_0	 1100
-#define  XTENSA_HWCIDVERS_RG_2015_0	 128
-
-/* Software (Xtensa Tools) versions:  */
-#define XTENSA_SWVERSION_T1020_0	102000	/* versions T1020.0 */
-#define XTENSA_SWVERSION_T1020_1	102001	/* versions T1020.1 */
-#define XTENSA_SWVERSION_T1020_2B	102002	/* versions T1020.2b */
-#define XTENSA_SWVERSION_T1020_2	102002	/* versions T1020.2 */
-#define XTENSA_SWVERSION_T1020_3	102003	/* versions T1020.3 */
-#define XTENSA_SWVERSION_T1020_4	102004	/* versions T1020.4 */
-#define XTENSA_SWVERSION_T1030_0	103000	/* versions T1030.0 */
-#define XTENSA_SWVERSION_T1030_1	103001	/* versions T1030.1 */
-#define XTENSA_SWVERSION_T1030_2	103002	/* versions T1030.2 */
-#define XTENSA_SWVERSION_T1030_3	103003	/* versions T1030.3 */
-#define XTENSA_SWVERSION_T1040_0	104000	/* versions T1040.0 */
-#define XTENSA_SWVERSION_T1040_1	104001	/* versions T1040.1 */
-#define XTENSA_SWVERSION_T1040_1P	104001	/* versions T1040.1-prehotfix */
-#define XTENSA_SWVERSION_T1040_2	104002	/* versions T1040.2 */
-#define XTENSA_SWVERSION_T1040_3	104003	/* versions T1040.3 */
-#define XTENSA_SWVERSION_T1050_0	105000	/* versions T1050.0 */
-#define XTENSA_SWVERSION_T1050_1	105001	/* versions T1050.1 */
-#define XTENSA_SWVERSION_T1050_2	105002	/* versions T1050.2 */
-#define XTENSA_SWVERSION_T1050_3	105003	/* versions T1050.3 */
-#define XTENSA_SWVERSION_T1050_4	105004	/* versions T1050.4 */
-#define XTENSA_SWVERSION_T1050_5	105005	/* versions T1050.5 */
-#define XTENSA_SWVERSION_RA_2004_1	600000	/* versions 6.0.0 */
-#define XTENSA_SWVERSION_RA_2005_1	600001	/* versions 6.0.1 */
-#define XTENSA_SWVERSION_RA_2005_2	600002	/* versions 6.0.2 */
-#define XTENSA_SWVERSION_RA_2005_3	600003	/* versions 6.0.3 */
-#define XTENSA_SWVERSION_RA_2006_4	600004	/* versions 6.0.4 */
-#define XTENSA_SWVERSION_RA_2006_5	600005	/* versions 6.0.5 */
-#define XTENSA_SWVERSION_RA_2006_6	600006	/* versions 6.0.6 */
-#define XTENSA_SWVERSION_RA_2007_7	600007	/* versions 6.0.7 */
-#define XTENSA_SWVERSION_RA_2008_8	600008	/* versions 6.0.8 */
-#define XTENSA_SWVERSION_RB_2006_0	700000	/* versions 7.0.0 */
-#define XTENSA_SWVERSION_RB_2007_1	700001	/* versions 7.0.1 */
-#define XTENSA_SWVERSION_RB_2007_2	701000	/* versions 7.1.0 */
-#define XTENSA_SWVERSION_RB_2008_3	701001	/* versions 7.1.1 */
-#define XTENSA_SWVERSION_RB_2008_4	701002	/* versions 7.1.2 */
-#define XTENSA_SWVERSION_RB_2009_5	701003	/* versions 7.1.3 */
-#define XTENSA_SWVERSION_RB_2007_2_MP	701100	/* versions 7.1.8-MP */
-#define XTENSA_SWVERSION_RC_2009_0	800000	/* versions 8.0.0 */
-#define XTENSA_SWVERSION_RC_2010_1	800001	/* versions 8.0.1 */
-#define XTENSA_SWVERSION_RC_2010_2	800002	/* versions 8.0.2 */
-#define XTENSA_SWVERSION_RC_2011_3	800003	/* versions 8.0.3 */
-#define XTENSA_SWVERSION_RD_2010_0	900000	/* versions 9.0.0 */
-#define XTENSA_SWVERSION_RD_2011_1	900001	/* versions 9.0.1 */
-#define XTENSA_SWVERSION_RD_2011_2	900002	/* versions 9.0.2 */
-#define XTENSA_SWVERSION_RD_2011_3	900003	/* versions 9.0.3 */
-#define XTENSA_SWVERSION_RD_2012_4	900004	/* versions 9.0.4 */
-#define XTENSA_SWVERSION_RD_2012_5	900005	/* versions 9.0.5 */
-#define XTENSA_SWVERSION_RE_2012_0	1000000	/* versions 10.0.0 */
-#define XTENSA_SWVERSION_RE_2012_1	1000001	/* versions 10.0.1 */
-#define XTENSA_SWVERSION_RE_2013_2	1000002	/* versions 10.0.2 */
-#define XTENSA_SWVERSION_RE_2013_3	1000003	/* versions 10.0.3 */
-#define XTENSA_SWVERSION_RE_2013_4	1000004	/* versions 10.0.4 */
-#define XTENSA_SWVERSION_RE_2014_5	1000005	/* versions 10.0.5 */
-#define XTENSA_SWVERSION_RE_2015_6	1000006	/* versions 10.0.6 */
-#define XTENSA_SWVERSION_RF_2014_0	1100000	/* versions 11.0.0 */
-#define XTENSA_SWVERSION_RF_2014_1	1100001	/* versions 11.0.1 */
-#define XTENSA_SWVERSION_RF_2015_2	1100002	/* versions 11.0.2 */
-#define XTENSA_SWVERSION_RF_2015_3	1100003	/* versions 11.0.3 */
-#define XTENSA_SWVERSION_RG_2015_0	1200000	/* versions 12.0.0 */
-#define XTENSA_SWVERSION_T1040_1_PREHOTFIX	XTENSA_SWVERSION_T1040_1P	/* T1040.1-prehotfix */
-#define XTENSA_SWVERSION_6_0_0	XTENSA_SWVERSION_RA_2004_1	/* 6.0.0 */
-#define XTENSA_SWVERSION_6_0_1	XTENSA_SWVERSION_RA_2005_1	/* 6.0.1 */
-#define XTENSA_SWVERSION_6_0_2	XTENSA_SWVERSION_RA_2005_2	/* 6.0.2 */
-#define XTENSA_SWVERSION_6_0_3	XTENSA_SWVERSION_RA_2005_3	/* 6.0.3 */
-#define XTENSA_SWVERSION_6_0_4	XTENSA_SWVERSION_RA_2006_4	/* 6.0.4 */
-#define XTENSA_SWVERSION_6_0_5	XTENSA_SWVERSION_RA_2006_5	/* 6.0.5 */
-#define XTENSA_SWVERSION_6_0_6	XTENSA_SWVERSION_RA_2006_6	/* 6.0.6 */
-#define XTENSA_SWVERSION_6_0_7	XTENSA_SWVERSION_RA_2007_7	/* 6.0.7 */
-#define XTENSA_SWVERSION_6_0_8	XTENSA_SWVERSION_RA_2008_8	/* 6.0.8 */
-#define XTENSA_SWVERSION_7_0_0	XTENSA_SWVERSION_RB_2006_0	/* 7.0.0 */
-#define XTENSA_SWVERSION_7_0_1	XTENSA_SWVERSION_RB_2007_1	/* 7.0.1 */
-#define XTENSA_SWVERSION_7_1_0	XTENSA_SWVERSION_RB_2007_2	/* 7.1.0 */
-#define XTENSA_SWVERSION_7_1_1	XTENSA_SWVERSION_RB_2008_3	/* 7.1.1 */
-#define XTENSA_SWVERSION_7_1_2	XTENSA_SWVERSION_RB_2008_4	/* 7.1.2 */
-#define XTENSA_SWVERSION_7_1_3	XTENSA_SWVERSION_RB_2009_5	/* 7.1.3 */
-#define XTENSA_SWVERSION_7_1_8_MP	XTENSA_SWVERSION_RB_2007_2_MP	/* 7.1.8-MP */
-#define XTENSA_SWVERSION_8_0_0	XTENSA_SWVERSION_RC_2009_0	/* 8.0.0 */
-#define XTENSA_SWVERSION_8_0_1	XTENSA_SWVERSION_RC_2010_1	/* 8.0.1 */
-#define XTENSA_SWVERSION_8_0_2	XTENSA_SWVERSION_RC_2010_2	/* 8.0.2 */
-#define XTENSA_SWVERSION_8_0_3	XTENSA_SWVERSION_RC_2011_3	/* 8.0.3 */
-#define XTENSA_SWVERSION_9_0_0	XTENSA_SWVERSION_RD_2010_0	/* 9.0.0 */
-#define XTENSA_SWVERSION_9_0_1	XTENSA_SWVERSION_RD_2011_1	/* 9.0.1 */
-#define XTENSA_SWVERSION_9_0_2	XTENSA_SWVERSION_RD_2011_2	/* 9.0.2 */
-#define XTENSA_SWVERSION_9_0_3	XTENSA_SWVERSION_RD_2011_3	/* 9.0.3 */
-#define XTENSA_SWVERSION_9_0_4	XTENSA_SWVERSION_RD_2012_4	/* 9.0.4 */
-#define XTENSA_SWVERSION_9_0_5	XTENSA_SWVERSION_RD_2012_5	/* 9.0.5 */
-#define XTENSA_SWVERSION_10_0_0	XTENSA_SWVERSION_RE_2012_0	/* 10.0.0 */
-#define XTENSA_SWVERSION_10_0_1	XTENSA_SWVERSION_RE_2012_1	/* 10.0.1 */
-#define XTENSA_SWVERSION_10_0_2	XTENSA_SWVERSION_RE_2013_2	/* 10.0.2 */
-#define XTENSA_SWVERSION_10_0_3	XTENSA_SWVERSION_RE_2013_3	/* 10.0.3 */
-#define XTENSA_SWVERSION_10_0_4	XTENSA_SWVERSION_RE_2013_4	/* 10.0.4 */
-#define XTENSA_SWVERSION_10_0_5	XTENSA_SWVERSION_RE_2014_5	/* 10.0.5 */
-#define XTENSA_SWVERSION_10_0_6	XTENSA_SWVERSION_RE_2015_6	/* 10.0.6 */
-#define XTENSA_SWVERSION_11_0_0	XTENSA_SWVERSION_RF_2014_0	/* 11.0.0 */
-#define XTENSA_SWVERSION_11_0_1	XTENSA_SWVERSION_RF_2014_1	/* 11.0.1 */
-#define XTENSA_SWVERSION_11_0_2	XTENSA_SWVERSION_RF_2015_2	/* 11.0.2 */
-#define XTENSA_SWVERSION_11_0_3	XTENSA_SWVERSION_RF_2015_3	/* 11.0.3 */
-#define XTENSA_SWVERSION_12_0_0	XTENSA_SWVERSION_RG_2015_0	/* 12.0.0 */
-
-
-/*  The current release:  */
-#define XTENSA_RELEASE_NAME		"RF-2015.3"
-#define XTENSA_RELEASE_CANONICAL_NAME	"RF-2015.3"
-
-/*  The product versions within the current release:  */
-#define XTENSA_SWVERSION		XTENSA_SWVERSION_RF_2015_3
-#define XTENSA_SWVERSION_NAME		"11.0.3"
-#define XTENSA_SWVERSION_CANONICAL_NAME	"11.0.3"
-#define XTENSA_SWVERSION_MAJORMID_NAME	"11.0"
-#define XTENSA_SWVERSION_MAJOR_NAME	"11"
-/*  For product licensing (not necessarily same as *_MAJORMID_NAME):  */
-#define XTENSA_SWVERSION_LICENSE_NAME	"11.0"
-
-/*  Note:  there may be multiple hardware products in one release,
-    and software can target older hardware, so the notion of
-    "current" hardware versions is partially configuration dependent.
-    For now, "current" hardware product version info is left out
-    to avoid confusion.  */
-
-#endif /*XTENSA_VERSIONS_H*/
-
diff --git a/tools/sdk/include/esp32/xtensa/xtensa-xer.h b/tools/sdk/include/esp32/xtensa/xtensa-xer.h
deleted file mode 100644
index 900bda33384..00000000000
--- a/tools/sdk/include/esp32/xtensa/xtensa-xer.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* xer-constants.h -- various constants describing external registers accessed 
-      via wer and rer.
-
-      TODO: find a better prefix. Also conditionalize certain constants based
-      on number of cores and interrupts actually present.  
-*/
-
-/*
- * Copyright (c) 1999-2008 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <xtensa/config/core.h>
-
-#define NUM_INTERRUPTS 27
-#define NUM_CORES       4
-
-/* Routing of NMI (BInterrupt2)	and interrupts 0..n-1 (BInterrupt3+) 
-   RER reads
-   WER writes
- */
-
-#define XER_MIROUT           0x0000
-#define XER_MIROUT_LAST      (XER_MIROUT + NUM_INTERRUPTS)
-
-
-/* IPI to core M (all 16 causes). 
-   
-   RER reads
-   WER clears
- */
-#define XER_MIPICAUSE        0x0100
-#define XER_MIPICAUSE_FIELD_A_FIRST 0x0
-#define XER_MIPICAUSE_FIELD_A_LAST  0x0
-#define XER_MIPICAUSE_FIELD_B_FIRST 0x1
-#define XER_MIPICAUSE_FIELD_B_LAST  0x3
-#define XER_MIPICAUSE_FIELD_C_FIRST 0x4
-#define XER_MIPICAUSE_FIELD_C_LAST  0x7
-#define XER_MIPICAUSE_FIELD_D_FIRST 0x8
-#define XER_MIPICAUSE_FIELD_D_LAST  0xF
-
-
-/* IPI from cause bit 0..15  
-
-   RER invalid
-   WER sets
-*/
-#define XER_MIPISET          0x0140
-#define XER_MIPISET_LAST     0x014F
-
-
-/* Global enable
-
-   RER read
-   WER clear
-*/
-#define XER_MIENG            0x0180
-
-
-/* Global enable
-
-   RER invalid
-   WER set
-*/
-#define XER_MIENG_SET        0x0184
-
-/* Global assert
-
-   RER read
-   WER clear
-*/
-#define XER_MIASG            0x0188
-
-
-/* Global enable
-
-   RER invalid
-   WER set
-*/
-#define XER_MIASG_SET        0x018C
-
-
-/* IPI partition register
-
-   RER read
-   WER write
-*/
-#define XER_PART            0x0190
-#define XER_IPI0            0x0
-#define XER_IPI1            0x1
-#define XER_IPI2            0x2
-#define XER_IPI3            0x3
-
-#define XER_PART_ROUTE_IPI(NUM, FIELD) ((NUM) << ((FIELD) << 2))
-
-#define XER_PART_ROUTE_IPI_CAUSE(TO_A, TO_B, TO_C, TO_D)		\
-  (XER_PART_ROUTE_IPI(TO_A, XER_IPI0) |					\
-   XER_PART_ROUTE_IPI(TO_B, XER_IPI1) |					\
-   XER_PART_ROUTE_IPI(TO_C, XER_IPI2) |					\
-   XER_PART_ROUTE_IPI(TO_D, XER_IPI3))
-
-#define XER_IPI_WAKE_EXT_INTERRUPT XCHAL_EXTINT0_NUM
-#define XER_IPI_WAKE_CAUSE  XER_MIPICAUSE_FIELD_C_FIRST
-#define XER_IPI_WAKE_ADDRESS    (XER_MIPISET + XER_IPI_WAKE_CAUSE)
-#define XER_DEFAULT_IPI_ROUTING XER_PART_ROUTE_IPI_CAUSE(XER_IPI1, XER_IPI0, XER_IPI2, XER_IPI3)
-
-
-/* System configuration ID
-
-   RER read
-   WER invalid
-*/
-#define XER_SYSCFGID        0x01A0
-
-
-/* RunStall to slave processors
-
-   RER read
-   WER write
-*/
-#define XER_MPSCORE        0x0200
-
-
-/* Cache coherency ON
-
-   RER read
-   WER write
-*/
-#define XER_CCON           0x0220
-
-
diff --git a/tools/sdk/include/esp32/xtensa/xtruntime-core-state.h b/tools/sdk/include/esp32/xtensa/xtruntime-core-state.h
deleted file mode 100644
index 37d203c2159..00000000000
--- a/tools/sdk/include/esp32/xtensa/xtruntime-core-state.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/*  xtruntime-core-state.h  -  core state save area (used eg. by PSO) */
-/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */
-
-/*
- * Copyright (c) 2012-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _XTOS_CORE_STATE_H_
-#define _XTOS_CORE_STATE_H_
-
-/*  Import STRUCT_xxx macros for defining structures:  */
-#include <xtensa/xtruntime-frames.h>
-#include <xtensa/config/core.h>
-#include <xtensa/config/tie.h>
-
-//#define XTOS_PSO_TEST	1		// uncommented for internal PSO testing only
-
-#define CORE_STATE_SIGNATURE	0xB1C5AFED	// pattern that indicates state was saved
-
-
-/*
- *  Save area for saving entire core state, such as across Power Shut-Off (PSO).
- */
-
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,CS_SA_,signature)		// for checking whether state was saved
-STRUCT_FIELD (long,4,CS_SA_,restore_label)
-STRUCT_FIELD (long,4,CS_SA_,aftersave_label)
-STRUCT_AFIELD(long,4,CS_SA_,areg,XCHAL_NUM_AREGS)
-#if XCHAL_HAVE_WINDOWED
-STRUCT_AFIELD(long,4,CS_SA_,caller_regs,16)	// save a max of 16 caller regs
-STRUCT_FIELD (long,4,CS_SA_,caller_regs_saved)  // flag to show if caller regs saved
-#endif
-#if XCHAL_HAVE_PSO_CDM
-STRUCT_FIELD (long,4,CS_SA_,pwrctl)
-#endif
-#if XCHAL_HAVE_WINDOWED
-STRUCT_FIELD (long,4,CS_SA_,windowbase)
-STRUCT_FIELD (long,4,CS_SA_,windowstart)
-#endif
-STRUCT_FIELD (long,4,CS_SA_,sar)
-#if XCHAL_HAVE_EXCEPTIONS
-STRUCT_FIELD (long,4,CS_SA_,epc1)
-STRUCT_FIELD (long,4,CS_SA_,ps)
-STRUCT_FIELD (long,4,CS_SA_,excsave1)
-# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
-STRUCT_FIELD (long,4,CS_SA_,depc)
-# endif
-#endif
-#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
-STRUCT_AFIELD(long,4,CS_SA_,epc,    XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
-STRUCT_AFIELD(long,4,CS_SA_,eps,    XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
-STRUCT_AFIELD(long,4,CS_SA_,excsave,XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
-#endif
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long,4,CS_SA_,lcount)
-STRUCT_FIELD (long,4,CS_SA_,lbeg)
-STRUCT_FIELD (long,4,CS_SA_,lend)
-#endif
-#if XCHAL_HAVE_ABSOLUTE_LITERALS
-STRUCT_FIELD (long,4,CS_SA_,litbase)
-#endif
-#if XCHAL_HAVE_VECBASE
-STRUCT_FIELD (long,4,CS_SA_,vecbase)
-#endif
-#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)	/* have ATOMCTL ? */
-STRUCT_FIELD (long,4,CS_SA_,atomctl)
-#endif
-#if XCHAL_HAVE_PREFETCH
-STRUCT_FIELD (long,4,CS_SA_,prefctl)
-#endif
-#if XCHAL_USE_MEMCTL
-STRUCT_FIELD (long,4,CS_SA_,memctl)
-#endif
-#if XCHAL_HAVE_CCOUNT
-STRUCT_FIELD (long,4,CS_SA_,ccount)
-STRUCT_AFIELD(long,4,CS_SA_,ccompare, XCHAL_NUM_TIMERS)
-#endif
-#if XCHAL_HAVE_INTERRUPTS
-STRUCT_FIELD (long,4,CS_SA_,intenable)
-STRUCT_FIELD (long,4,CS_SA_,interrupt)
-#endif
-#if XCHAL_HAVE_DEBUG
-STRUCT_FIELD (long,4,CS_SA_,icount)
-STRUCT_FIELD (long,4,CS_SA_,icountlevel)
-STRUCT_FIELD (long,4,CS_SA_,debugcause)
-// DDR not saved
-# if XCHAL_NUM_DBREAK
-STRUCT_AFIELD(long,4,CS_SA_,dbreakc, XCHAL_NUM_DBREAK)
-STRUCT_AFIELD(long,4,CS_SA_,dbreaka, XCHAL_NUM_DBREAK)
-# endif
-# if XCHAL_NUM_IBREAK
-STRUCT_AFIELD(long,4,CS_SA_,ibreaka, XCHAL_NUM_IBREAK)
-STRUCT_FIELD (long,4,CS_SA_,ibreakenable)
-# endif
-#endif
-#if XCHAL_NUM_MISC_REGS
-STRUCT_AFIELD(long,4,CS_SA_,misc,XCHAL_NUM_MISC_REGS)
-#endif
-#if XCHAL_HAVE_MEM_ECC_PARITY
-STRUCT_FIELD (long,4,CS_SA_,mepc)
-STRUCT_FIELD (long,4,CS_SA_,meps)
-STRUCT_FIELD (long,4,CS_SA_,mesave)
-STRUCT_FIELD (long,4,CS_SA_,mesr)
-STRUCT_FIELD (long,4,CS_SA_,mecr)
-STRUCT_FIELD (long,4,CS_SA_,mevaddr)
-#endif
-
-/*  We put this ahead of TLB and other TIE state,
-    to keep it within S32I/L32I offset range.  */
-#if XCHAL_HAVE_CP
-STRUCT_FIELD (long,4,CS_SA_,cpenable)
-#endif
-
-/*  TLB state  */
-#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
-STRUCT_AFIELD(long,4,CS_SA_,tlbs,8*2)
-#endif
-#if XCHAL_HAVE_PTP_MMU
-/*  Compute number of auto-refill (ARF) entries as max of I and D,
-    to simplify TLB save logic.  On the unusual configs with
-    ITLB ARF != DTLB ARF entries, we'll just end up
-    saving/restoring some extra entries redundantly.  */
-#  if XCHAL_DTLB_ARF_ENTRIES_LOG2 + XCHAL_ITLB_ARF_ENTRIES_LOG2 > 4
-#   define ARF_ENTRIES	8
-#  else
-#   define ARF_ENTRIES	4
-#  endif
-STRUCT_FIELD (long,4,CS_SA_,ptevaddr)
-STRUCT_FIELD (long,4,CS_SA_,rasid)
-STRUCT_FIELD (long,4,CS_SA_,dtlbcfg)
-STRUCT_FIELD (long,4,CS_SA_,itlbcfg)
-/*** WARNING:  past this point, field offsets may be larger than S32I/L32I range ***/
-STRUCT_AFIELD(long,4,CS_SA_,tlbs,((4*ARF_ENTRIES+4)*2+3)*2)
-# if XCHAL_HAVE_SPANNING_WAY	/* MMU v3 */
-STRUCT_AFIELD(long,4,CS_SA_,tlbs_ways56,(4+8)*2*2)
-# endif
-#endif
-
-/*  TIE state  */
-/*  NOTE: NCP area is aligned to XCHAL_TOTAL_SA_ALIGN not XCHAL_NCP_SA_ALIGN,
-    because the offsets of all subsequent coprocessor save areas are relative
-    to the NCP save area.  */
-STRUCT_AFIELD_A(char,1,XCHAL_TOTAL_SA_ALIGN,CS_SA_,ncp,XCHAL_NCP_SA_SIZE)
-#if XCHAL_HAVE_CP
-STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE)
-STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE)
-STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE)
-STRUCT_AFIELD_A(char,1,XCHAL_CP3_SA_ALIGN,CS_SA_,cp3,XCHAL_CP3_SA_SIZE)
-STRUCT_AFIELD_A(char,1,XCHAL_CP4_SA_ALIGN,CS_SA_,cp4,XCHAL_CP4_SA_SIZE)
-STRUCT_AFIELD_A(char,1,XCHAL_CP5_SA_ALIGN,CS_SA_,cp5,XCHAL_CP5_SA_SIZE)
-STRUCT_AFIELD_A(char,1,XCHAL_CP6_SA_ALIGN,CS_SA_,cp6,XCHAL_CP6_SA_SIZE)
-STRUCT_AFIELD_A(char,1,XCHAL_CP7_SA_ALIGN,CS_SA_,cp7,XCHAL_CP7_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP8_SA_ALIGN,CS_SA_,cp8,XCHAL_CP8_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP9_SA_ALIGN,CS_SA_,cp9,XCHAL_CP9_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP10_SA_ALIGN,CS_SA_,cp10,XCHAL_CP10_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP11_SA_ALIGN,CS_SA_,cp11,XCHAL_CP11_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP12_SA_ALIGN,CS_SA_,cp12,XCHAL_CP12_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP13_SA_ALIGN,CS_SA_,cp13,XCHAL_CP13_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP14_SA_ALIGN,CS_SA_,cp14,XCHAL_CP14_SA_SIZE)
-//STRUCT_AFIELD_A(char,1,XCHAL_CP15_SA_ALIGN,CS_SA_,cp15,XCHAL_CP15_SA_SIZE)
-#endif
-
-STRUCT_END(XtosCoreState)
-
-
-
-//  These are part of non-coprocessor state (ncp):
-#if XCHAL_HAVE_MAC16
-//STRUCT_FIELD (long,4,CS_SA_,acclo)
-//STRUCT_FIELD (long,4,CS_SA_,acchi)
-//STRUCT_AFIELD(long,4,CS_SA_,mr, 4)
-#endif
-#if XCHAL_HAVE_THREADPTR
-//STRUCT_FIELD (long,4,CS_SA_,threadptr)
-#endif
-#if XCHAL_HAVE_S32C1I
-//STRUCT_FIELD (long,4,CS_SA_,scompare1)
-#endif
-#if XCHAL_HAVE_BOOLEANS
-//STRUCT_FIELD (long,4,CS_SA_,br)
-#endif
-
-//  Not saved:
-//	EXCCAUSE ??
-//	DEBUGCAUSE ??
-//	EXCVADDR ??
-//	DDR
-//	INTERRUPT
-//	... locked cache lines ...
-
-#endif /* _XTOS_CORE_STATE_H_ */
-
diff --git a/tools/sdk/include/esp32/xtensa/xtruntime-frames.h b/tools/sdk/include/esp32/xtensa/xtruntime-frames.h
deleted file mode 100644
index 8b5a7463abe..00000000000
--- a/tools/sdk/include/esp32/xtensa/xtruntime-frames.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*  xtruntime-frames.h  -  exception stack frames for single-threaded run-time  */
-/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-frames.h#1 $ */
-
-/*
- * Copyright (c) 2002-2012 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _XTRUNTIME_FRAMES_H_
-#define _XTRUNTIME_FRAMES_H_
-
-#include <xtensa/config/core.h>
-
-/*  Macros that help define structures for both C and assembler:  */
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-#define STRUCT_BEGIN		.pushsection .text; .struct 0
-#define STRUCT_FIELD(ctype,size,pre,name)	pre##name:	.space	size
-#define STRUCT_AFIELD(ctype,size,pre,name,n)	pre##name:	.if n ; .space	(size)*(n) ; .endif
-#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n)	.balign align ; pre##name:	.if n ; .space (size)*(n) ; .endif
-#define STRUCT_END(sname)	sname##Size:; .popsection
-#else /*_ASMLANGUAGE||__ASSEMBLER__*/
-#define STRUCT_BEGIN		typedef struct {
-#define STRUCT_FIELD(ctype,size,pre,name)	ctype	name;
-#define STRUCT_AFIELD(ctype,size,pre,name,n)	ctype	name[n];
-#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n)	ctype	name[n] __attribute__((aligned(align)));
-#define STRUCT_END(sname)	} sname;
-#endif /*_ASMLANGUAGE||__ASSEMBLER__*/
-
-
-/*
- *  Kernel vector mode exception stack frame.
- *
- *  NOTE:  due to the limited range of addi used in the current
- *  kernel exception vector, and the fact that historically
- *  the vector is limited to 12 bytes, the size of this
- *  stack frame is limited to 128 bytes (currently at 64).
- */
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,KEXC_,pc)		/* "parm" */
-STRUCT_FIELD (long,4,KEXC_,ps)
-STRUCT_AFIELD(long,4,KEXC_,areg, 4)	/* a12 .. a15 */
-STRUCT_FIELD (long,4,KEXC_,sar)		/* "save" */
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long,4,KEXC_,lcount)
-STRUCT_FIELD (long,4,KEXC_,lbeg)
-STRUCT_FIELD (long,4,KEXC_,lend)
-#endif
-#if XCHAL_HAVE_MAC16
-STRUCT_FIELD (long,4,KEXC_,acclo)
-STRUCT_FIELD (long,4,KEXC_,acchi)
-STRUCT_AFIELD(long,4,KEXC_,mr, 4)
-#endif
-STRUCT_END(KernelFrame)
-
-
-/*
- *  User vector mode exception stack frame:
- *
- *  WARNING:  if you modify this structure, you MUST modify the
- *  computation of the pad size (ALIGNPAD) accordingly.
- */
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,UEXC_,pc)
-STRUCT_FIELD (long,4,UEXC_,ps)
-STRUCT_FIELD (long,4,UEXC_,sar)
-STRUCT_FIELD (long,4,UEXC_,vpri)
-#ifdef __XTENSA_CALL0_ABI__
-STRUCT_FIELD (long,4,UEXC_,a0)
-#endif
-STRUCT_FIELD (long,4,UEXC_,a2)
-STRUCT_FIELD (long,4,UEXC_,a3)
-STRUCT_FIELD (long,4,UEXC_,a4)
-STRUCT_FIELD (long,4,UEXC_,a5)
-#ifdef __XTENSA_CALL0_ABI__
-STRUCT_FIELD (long,4,UEXC_,a6)
-STRUCT_FIELD (long,4,UEXC_,a7)
-STRUCT_FIELD (long,4,UEXC_,a8)
-STRUCT_FIELD (long,4,UEXC_,a9)
-STRUCT_FIELD (long,4,UEXC_,a10)
-STRUCT_FIELD (long,4,UEXC_,a11)
-STRUCT_FIELD (long,4,UEXC_,a12)
-STRUCT_FIELD (long,4,UEXC_,a13)
-STRUCT_FIELD (long,4,UEXC_,a14)
-STRUCT_FIELD (long,4,UEXC_,a15)
-#endif
-STRUCT_FIELD (long,4,UEXC_,exccause)	/* NOTE: can probably rid of this one (pass direct) */
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long,4,UEXC_,lcount)
-STRUCT_FIELD (long,4,UEXC_,lbeg)
-STRUCT_FIELD (long,4,UEXC_,lend)
-#endif
-#if XCHAL_HAVE_MAC16
-STRUCT_FIELD (long,4,UEXC_,acclo)
-STRUCT_FIELD (long,4,UEXC_,acchi)
-STRUCT_AFIELD(long,4,UEXC_,mr, 4)
-#endif
-/* ALIGNPAD is the 16-byte alignment padding. */
-#ifdef __XTENSA_CALL0_ABI__
-# define CALL0_ABI	1
-#else
-# define CALL0_ABI	0
-#endif
-#define ALIGNPAD  ((3 + XCHAL_HAVE_LOOPS*1 + XCHAL_HAVE_MAC16*2 + CALL0_ABI*1) & 3)
-#if ALIGNPAD
-STRUCT_AFIELD(long,4,UEXC_,pad, ALIGNPAD)	/* 16-byte alignment padding */
-#endif
-/*STRUCT_AFIELD_A(char,1,XCHAL_CPEXTRA_SA_ALIGN,UEXC_,ureg, (XCHAL_CPEXTRA_SA_SIZE+3)&-4)*/	/* not used */
-STRUCT_END(UserFrame)
-
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-
-
-/*  Check for UserFrameSize small enough not to require rounding...:  */
-	/*  Skip 16-byte save area, then 32-byte space for 8 regs of call12
-	 *  (which overlaps with 16-byte GCC nested func chaining area),
-	 *  then exception stack frame:  */
-	.set	UserFrameTotalSize, 16+32+UserFrameSize
-	/*  Greater than 112 bytes? (max range of ADDI, both signs, when aligned to 16 bytes):  */
-	.ifgt	UserFrameTotalSize-112
-	/*  Round up to 256-byte multiple to accelerate immediate adds:  */
-	.set	UserFrameTotalSize, ((UserFrameTotalSize+255) & 0xFFFFFF00)
-	.endif
-# define ESF_TOTALSIZE	UserFrameTotalSize
-
-#endif /* _ASMLANGUAGE || __ASSEMBLER__ */
-
-
-#if XCHAL_NUM_CONTEXTS > 1
-/*  Structure of info stored on new context's stack for setup:  */
-STRUCT_BEGIN
-STRUCT_FIELD (long,4,INFO_,sp)
-STRUCT_FIELD (long,4,INFO_,arg1)
-STRUCT_FIELD (long,4,INFO_,funcpc)
-STRUCT_FIELD (long,4,INFO_,prevps)
-STRUCT_END(SetupInfo)
-#endif
-
-
-#define KERNELSTACKSIZE	1024
-
-
-#endif /* _XTRUNTIME_FRAMES_H_ */
-
diff --git a/tools/sdk/include/esp32/xtensa/xtruntime.h b/tools/sdk/include/esp32/xtensa/xtruntime.h
deleted file mode 100644
index 9dae1f4b23e..00000000000
--- a/tools/sdk/include/esp32/xtensa/xtruntime.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * xtruntime.h  --  general C definitions for single-threaded run-time
- *
- * Copyright (c) 2002-2013 Tensilica Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef XTRUNTIME_H
-#define XTRUNTIME_H
-
-#include <xtensa/config/core.h>
-#include <xtensa/config/specreg.h>
-#include <xtensa/xtruntime-core-state.h>
-
-#ifndef XTSTR
-#define _XTSTR(x)	# x
-#define XTSTR(x)	_XTSTR(x)
-#endif
-
-/*  _xtos_core_shutoff() flags parameter values:  */
-#define XTOS_KEEPON_MEM		0x00000100	/* ==PWRCTL_MEM_WAKEUP */
-#define XTOS_KEEPON_MEM_SHIFT	8
-#define XTOS_KEEPON_DEBUG	0x00001000	/* ==PWRCTL_DEBUG_WAKEUP */
-#define XTOS_KEEPON_DEBUG_SHIFT	12
-
-#define XTOS_COREF_PSO		0x00000001	/* do power shutoff */
-#define XTOS_COREF_PSO_SHIFT	0
-
-#define _xtos_set_execption_handler _xtos_set_exception_handler	/* backward compatibility */
-#define _xtos_set_saved_intenable	_xtos_ints_on	/* backward compatibility */
-#define _xtos_clear_saved_intenable	_xtos_ints_off	/* backward compatibility */
-
-#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*typedef void (_xtos_timerdelta_func)(int);*/
-#ifdef __cplusplus
-typedef void (_xtos_handler_func)(...);
-#else
-typedef void (_xtos_handler_func)();
-#endif
-typedef _xtos_handler_func *_xtos_handler;
-
-/*
- *  unsigned XTOS_SET_INTLEVEL(int intlevel);
- *  This macro sets the current interrupt level.
- *  The 'intlevel' parameter must be a constant.
- *  This macro returns a 32-bit value that must be passed to
- *  XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level.
- *  XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs
- *  it restores only PS.INTLEVEL rather than the entire PS register
- *  and thus is slower.
- */
-#if !XCHAL_HAVE_INTERRUPTS
-# define XTOS_SET_INTLEVEL(intlevel)		0
-# define XTOS_SET_MIN_INTLEVEL(intlevel)	0
-# define XTOS_RESTORE_INTLEVEL(restoreval)
-# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)
-#elif XCHAL_HAVE_XEA2
-/*  In XEA2, we can simply safely set PS.INTLEVEL directly:  */
-/*  NOTE: these asm macros don't modify memory, but they are marked
- *  as such to act as memory access barriers to the compiler because
- *  these macros are sometimes used to delineate critical sections;
- *  function calls are natural barriers (the compiler does not know
- *  whether a function modifies memory) unless declared to be inlined.  */
-# define XTOS_SET_INTLEVEL(intlevel)		({ unsigned __tmp; \
-			__asm__ __volatile__(	"rsil	%0, " XTSTR(intlevel) "\n" \
-						: "=a" (__tmp) : : "memory" ); \
-			__tmp;})
-# define XTOS_SET_MIN_INTLEVEL(intlevel)		({ unsigned __tmp, __tmp2, __tmp3; \
-			__asm__ __volatile__(	"rsr	%0, " XTSTR(PS) "\n"	/* get old (current) PS.INTLEVEL */ \
-						"movi	%2, " XTSTR(intlevel) "\n" \
-						"extui	%1, %0, 0, 4\n"	/* keep only INTLEVEL bits of parameter */ \
-						"blt	%2, %1, 1f\n" \
-						"rsil	%0, " XTSTR(intlevel) "\n" \
-						"1:\n" \
-						: "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \
-			__tmp;})
-# define XTOS_RESTORE_INTLEVEL(restoreval)	do{ unsigned __tmp = (restoreval); \
-			__asm__ __volatile__(	"wsr	%0, " XTSTR(PS) " ; rsync\n" \
-						: : "a" (__tmp) : "memory" ); \
-			}while(0)
-# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)	_xtos_set_intlevel(restoreval)
-#else
-/*  In XEA1, we have to rely on INTENABLE register virtualization:  */
-extern unsigned		_xtos_set_vpri( unsigned vpri );
-extern unsigned		_xtos_vpri_enabled;	/* current virtual priority */
-# define XTOS_SET_INTLEVEL(intlevel)		_xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
-# define XTOS_SET_MIN_INTLEVEL(intlevel)	_xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
-# define XTOS_RESTORE_INTLEVEL(restoreval)	_xtos_set_vpri(restoreval)
-# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)	_xtos_set_vpri(restoreval)
-#endif
-
-/*
- *  The following macros build upon the above.  They are generally used
- *  instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly.
- *  They all return a value that can be used with XTOS_RESTORE_INTLEVEL()
- *  or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore
- *  the effective interrupt level to what it was before the macro was invoked.
- *  In XEA2, the DISABLE macros are much faster than the MASK macros
- *  (in all configs, DISABLE sets the effective interrupt level, whereas MASK
- *  makes ensures the effective interrupt level is at least the level given
- *  without lowering it; in XEA2 with INTENABLE virtualization, these macros
- *  affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial
- *  MASK semantics).
- *
- *  A typical critical section sequence might be:
- *	unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS;
- *	... critical section ...
- *	XTOS_RESTORE_INTLEVEL(rval);
- */
-/*  Enable all interrupts (those activated with _xtos_ints_on()):  */
-#define XTOS_ENABLE_INTERRUPTS		XTOS_SET_INTLEVEL(0)
-/*  Disable low priority level interrupts (they can interact with the OS):  */
-#define XTOS_DISABLE_LOWPRI_INTERRUPTS	XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
-#define XTOS_MASK_LOWPRI_INTERRUPTS	XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
-/*  Disable interrupts that can interact with the OS:  */
-#define XTOS_DISABLE_EXCM_INTERRUPTS	XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
-#define XTOS_MASK_EXCM_INTERRUPTS	XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL)
-#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */
-/*  Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE:  */
-#define XTOS_DISABLE_LOCK_INTERRUPTS	XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL)
-#define XTOS_MASK_LOCK_INTERRUPTS	XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL)
-#endif
-/*  Disable ALL interrupts (not for common use, particularly if one's processor
- *  configuration has high-level interrupts and one cares about their latency):  */
-#define XTOS_DISABLE_ALL_INTERRUPTS	XTOS_SET_INTLEVEL(15)
-
-
-extern unsigned int	_xtos_ints_off( unsigned int mask );
-extern unsigned int	_xtos_ints_on( unsigned int mask );
-extern unsigned		_xtos_set_intlevel( int intlevel );
-extern unsigned		_xtos_set_min_intlevel( int intlevel );
-extern unsigned		_xtos_restore_intlevel( unsigned restoreval );
-extern unsigned		_xtos_restore_just_intlevel( unsigned restoreval );
-extern _xtos_handler	_xtos_set_interrupt_handler( int n, _xtos_handler f );
-extern _xtos_handler	_xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg );
-extern _xtos_handler	_xtos_set_exception_handler( int n, _xtos_handler f );
-
-extern void		_xtos_memep_initrams( void );
-extern void		_xtos_memep_enable( int flags );
-
-/*  For use with the tiny LSP (see LSP reference manual).  */
-#if XCHAL_NUM_INTLEVELS >= 1
-extern void		_xtos_dispatch_level1_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 2
-extern void		_xtos_dispatch_level2_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 3
-extern void		_xtos_dispatch_level3_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 4
-extern void		_xtos_dispatch_level4_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 5
-extern void		_xtos_dispatch_level5_interrupts( void );
-#endif
-#if XCHAL_NUM_INTLEVELS >= 6
-extern void		_xtos_dispatch_level6_interrupts( void );
-#endif
-
-/*  Deprecated (but kept because they were documented):  */
-extern unsigned int	_xtos_read_ints( void );		/* use xthal_get_interrupt() instead */
-extern void		_xtos_clear_ints( unsigned int mask );	/* use xthal_set_intclear() instead */
-
-
-/*  Power shut-off related routines.  */
-extern int		_xtos_core_shutoff(unsigned flags);
-extern int		_xtos_core_save(unsigned flags, XtosCoreState *savearea, void *code);
-extern void		_xtos_core_restore(unsigned retvalue, XtosCoreState *savearea);
-
-
-#if XCHAL_NUM_CONTEXTS > 1
-extern unsigned		_xtos_init_context(int context_num, int stack_size,
-					    _xtos_handler_func *start_func, int arg1);
-#endif
-
-/*  Deprecated:  */
-#if XCHAL_NUM_TIMERS > 0
-extern void		_xtos_timer_0_delta( int cycles );
-#endif
-#if XCHAL_NUM_TIMERS > 1
-extern void		_xtos_timer_1_delta( int cycles );
-#endif
-#if XCHAL_NUM_TIMERS > 2
-extern void		_xtos_timer_2_delta( int cycles );
-#endif
-#if XCHAL_NUM_TIMERS > 3
-extern void		_xtos_timer_3_delta( int cycles );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
-
-#endif /* XTRUNTIME_H */
-
diff --git a/tools/sdk/include/esp_adc_cal/esp_adc_cal.h b/tools/sdk/include/esp_adc_cal/esp_adc_cal.h
deleted file mode 100644
index af611357b49..00000000000
--- a/tools/sdk/include/esp_adc_cal/esp_adc_cal.h
+++ /dev/null
@@ -1,152 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_ADC_CAL_H__
-#define __ESP_ADC_CAL_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include "esp_err.h"
-#include "driver/adc.h"
-
-/**
- * @brief Type of calibration value used in characterization
- */
-typedef enum {
-    ESP_ADC_CAL_VAL_EFUSE_VREF = 0,         /**< Characterization based on reference voltage stored in eFuse*/
-    ESP_ADC_CAL_VAL_EFUSE_TP = 1,           /**< Characterization based on Two Point values stored in eFuse*/
-    ESP_ADC_CAL_VAL_DEFAULT_VREF = 2,       /**< Characterization based on default reference voltage*/
-} esp_adc_cal_value_t;
-
-/**
- * @brief Structure storing characteristics of an ADC
- *
- * @note Call esp_adc_cal_characterize() to initialize the structure
- */
-typedef struct {
-    adc_unit_t adc_num;                     /**< ADC number*/
-    adc_atten_t atten;                      /**< ADC attenuation*/
-    adc_bits_width_t bit_width;             /**< ADC bit width */
-    uint32_t coeff_a;                       /**< Gradient of ADC-Voltage curve*/
-    uint32_t coeff_b;                       /**< Offset of ADC-Voltage curve*/
-    uint32_t vref;                          /**< Vref used by lookup table*/
-    const uint32_t *low_curve;              /**< Pointer to low Vref curve of lookup table (NULL if unused)*/
-    const uint32_t *high_curve;             /**< Pointer to high Vref curve of lookup table (NULL if unused)*/
-} esp_adc_cal_characteristics_t;
-
-/**
- * @brief Checks if ADC calibration values are burned into eFuse
- *
- * This function checks if ADC reference voltage or Two Point values have been
- * burned to the eFuse of the current ESP32
- *
- * @param   value_type  Type of calibration value (ESP_ADC_CAL_VAL_EFUSE_VREF or ESP_ADC_CAL_VAL_EFUSE_TP)
- *
- * @return
- *      - ESP_OK: The calibration mode is supported in eFuse
- *      - ESP_ERR_NOT_SUPPORTED: Error, eFuse values are not burned
- *      - ESP_ERR_INVALID_ARG: Error, invalid argument (ESP_ADC_CAL_VAL_DEFAULT_VREF)
- */
-esp_err_t esp_adc_cal_check_efuse(esp_adc_cal_value_t value_type);
-
-/**
- * @brief Characterize an ADC at a particular attenuation
- *
- * This function will characterize the ADC at a particular attenuation and generate
- * the ADC-Voltage curve in the form of [y = coeff_a * x + coeff_b].
- * Characterization can be based on Two Point values, eFuse Vref, or default Vref
- * and the calibration values will be prioritized in that order.
- *
- * @note Two Point values and eFuse Vref can be enabled/disabled using menuconfig.
- *
- * @param[in]   adc_num         ADC to characterize (ADC_UNIT_1 or ADC_UNIT_2)
- * @param[in]   atten           Attenuation to characterize
- * @param[in]   bit_width       Bit width configuration of ADC
- * @param[in]   default_vref    Default ADC reference voltage in mV (used if eFuse values is not available)
- * @param[out]  chars           Pointer to empty structure used to store ADC characteristics
- *
- * @return
- *      - ESP_ADC_CAL_VAL_EFUSE_VREF: eFuse Vref used for characterization
- *      - ESP_ADC_CAL_VAL_EFUSE_TP: Two Point value used for characterization (only in Linear Mode)
- *      - ESP_ADC_CAL_VAL_DEFAULT_VREF: Default Vref used for characterization
- */
-esp_adc_cal_value_t esp_adc_cal_characterize(adc_unit_t adc_num,
-                                             adc_atten_t atten,
-                                             adc_bits_width_t bit_width,
-                                             uint32_t default_vref,
-                                             esp_adc_cal_characteristics_t *chars);
-
-/**
- * @brief   Convert an ADC reading to voltage in mV
- *
- * This function converts an ADC reading to a voltage in mV based on the ADC's
- * characteristics.
- *
- * @note    Characteristics structure must be initialized before this function
- *          is called (call esp_adc_cal_characterize())
- *
- * @param[in]   adc_reading     ADC reading
- * @param[in]   chars           Pointer to initialized structure containing ADC characteristics
- *
- * @return      Voltage in mV
- */
-uint32_t esp_adc_cal_raw_to_voltage(uint32_t adc_reading, const esp_adc_cal_characteristics_t *chars);
-
-/**
- * @brief   Reads an ADC and converts the reading to a voltage in mV
- *
- * This function reads an ADC then converts the raw reading to a voltage in mV
- * based on the characteristics provided. The ADC that is read is also
- * determined by the characteristics.
- *
- * @note    The Characteristics structure must be initialized before this
- *          function is called (call esp_adc_cal_characterize())
- *
- * @param[in]   channel     ADC Channel to read
- * @param[in]   chars       Pointer to initialized ADC characteristics structure
- * @param[out]  voltage     Pointer to store converted voltage
- *
- * @return
- *      - ESP_OK: ADC read and converted to mV
- *      - ESP_ERR_TIMEOUT: Error, timed out attempting to read ADC
- *      - ESP_ERR_INVALID_ARG: Error due to invalid arguments
- */
-esp_err_t esp_adc_cal_get_voltage(adc_channel_t channel, const esp_adc_cal_characteristics_t *chars, uint32_t *voltage);
-
-/* -------------------------- Deprecated API ------------------------------- */
-
-/** @cond */    //Doxygen command to hide deprecated function from API Reference
-/**
- * @deprecated  ADC1 characterization function. Deprecated in order to accommodate
- *              ADC2 and eFuse functionality. Use esp_adc_cal_characterize() instead
- */
-void esp_adc_cal_get_characteristics(uint32_t vref, adc_atten_t atten, adc_bits_width_t bit_width, esp_adc_cal_characteristics_t *chars) __attribute__((deprecated));
-
-/*
- * @deprecated  This function reads ADC1 and returns the corrected voltage. This
- *              has been deprecated in order to accommodate ADC2 support. Use the
- *              new function esp_adc_cal_get_voltage() instead.
- */
-uint32_t adc1_to_voltage(adc1_channel_t channel, const esp_adc_cal_characteristics_t *chars) __attribute__((deprecated));
-
-/** @endcond */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_ADC_CAL_H__ */
diff --git a/tools/sdk/include/esp_event/esp_event.h b/tools/sdk/include/esp_event/esp_event.h
deleted file mode 100644
index 48918398cf4..00000000000
--- a/tools/sdk/include/esp_event/esp_event.h
+++ /dev/null
@@ -1,326 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//         http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef ESP_EVENT_H_
-#define ESP_EVENT_H_
-
-#include "esp_err.h"
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/queue.h"
-#include "freertos/semphr.h"
-
-#include "esp_event_base.h"
-#include "esp_event_legacy.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/// Configuration for creating event loops
-typedef struct {
-    int32_t queue_size;                         /**< size of the event loop queue */
-    const char* task_name;                      /**< name of the event loop task; if NULL,
-                                                        a dedicated task is not created for event loop*/
-    UBaseType_t task_priority;                  /**< priority of the event loop task, ignored if task name is NULL */
-    uint32_t task_stack_size;                   /**< stack size of the event loop task, ignored if task name is NULL */
-    BaseType_t task_core_id;                    /**< core to which the event loop task is pinned to,
-                                                        ignored if task name is NULL */
-} esp_event_loop_args_t;
-
-/**
- * @brief Create a new event loop.
- *
- * @param[in] event_loop_args configuration structure for the event loop to create
- * @param[out] event_loop handle to the created event loop
- *
- * @return
- *  - ESP_OK: Success
- *  - ESP_ERR_NO_MEM: Cannot allocate memory for event loops list
- *  - ESP_FAIL: Failed to create task loop
- *  - Others: Fail
- */
-esp_err_t esp_event_loop_create(const esp_event_loop_args_t* event_loop_args, esp_event_loop_handle_t* event_loop);
-
-/**
- * @brief Delete an existing event loop.
- *
- * @param[in] event_loop event loop to delete
- *
- * @return
- *  - ESP_OK: Success
- *  - Others: Fail
- */
-esp_err_t esp_event_loop_delete(esp_event_loop_handle_t event_loop);
-
-/**
- * @brief Create default event loop
- *
- * @return
- *  - ESP_OK: Success
- *  - ESP_ERR_NO_MEM: Cannot allocate memory for event loops list
- *  - ESP_FAIL: Failed to create task loop
- *  - Others: Fail
- */
-esp_err_t esp_event_loop_create_default();
-
-/**
- * @brief Delete the default event loop
- *
- * @return
- *  - ESP_OK: Success
- *  - Others: Fail
- */
-esp_err_t esp_event_loop_delete_default();
-
-/**
- * @brief Dispatch events posted to an event loop.
- *
- * This function is used to dispatch events posted to a loop with no dedicated task, i.e task name was set to NULL
- * in event_loop_args argument during loop creation. This function includes an argument to limit the amount of time
- * it runs, returning control to the caller when that time expires (or some time afterwards). There is no guarantee
- * that a call to this function will exit at exactly the time of expiry. There is also no guarantee that events have
- * been dispatched during the call, as the function might have spent all of the alloted time waiting on the event queue.
- * Once an event has been unqueued, however, it is guaranteed to be dispatched. This guarantee contributes to not being
- * able to exit exactly at time of expiry as (1) blocking on internal mutexes is necessary for dispatching the unqueued
- * event, and (2) during  dispatch of the unqueued event there is no way to control the time occupied by handler code
- * execution. The guaranteed time of exit is therefore the alloted time + amount of time required to dispatch
- * the last unqueued event.
- *
- * In cases where waiting on the queue times out, ESP_OK is returned and not ESP_ERR_TIMEOUT, since it is
- * normal behavior.
- *
- * @param[in] event_loop event loop to dispatch posted events from
- * @param[in] ticks_to_run number of ticks to run the loop
- *
- * @note encountering an unknown event that has been posted to the loop will only generate a warning, not an error.
- *
- * @return
- *  - ESP_OK: Success
- *  - Others: Fail
- */
-esp_err_t esp_event_loop_run(esp_event_loop_handle_t event_loop, TickType_t ticks_to_run);
-
-/**
- * @brief Register an event handler to the system event loop.
- *
- * This function can be used to register a handler for either: (1) specific events,
- * (2) all events of a certain event base, or (3) all events known by the system event loop.
- *
- *  - specific events: specify exact event_base and event_id
- *  - all events of a certain base: specify exact event_base and use ESP_EVENT_ANY_ID as the event_id
- *  - all events known by the loop: use ESP_EVENT_ANY_BASE for event_base and ESP_EVENT_ANY_ID as the event_id
- *
- * Registering multiple handlers to events is possible. Registering a single handler to multiple events is
- * also possible. However, registering the same handler to the same event multiple times would cause the
- * previous registrations to be overwritten.
- *
- * @param[in] event_base the base id of the event to register the handler for
- * @param[in] event_id the id of the event to register the handler for
- * @param[in] event_handler the handler function which gets called when the event is dispatched
- * @param[in] event_handler_arg data, aside from event data, that is passed to the handler when it is called
- *
- * @note the event loop library does not maintain a copy of event_handler_arg, therefore the user should
- * ensure that event_handler_arg still points to a valid location by the time the handler gets called
- *
- * @return
- *  - ESP_OK: Success
- *  - ESP_ERR_NO_MEM: Cannot allocate memory for the handler
- *  - ESP_ERR_INVALID_ARG: Invalid combination of event base and event id
- *  - Others: Fail
- */
-esp_err_t esp_event_handler_register(esp_event_base_t event_base,
-                                        int32_t event_id,
-                                        esp_event_handler_t event_handler,
-                                        void* event_handler_arg);
-
-/**
- * @brief Register an event handler to a specific loop.
- *
- * This function behaves in the same manner as esp_event_handler_register, except the additional
- * specification of the event loop to register the handler to.
- *
- * @param[in] event_loop the event loop to register this handler function to
- * @param[in] event_base the base id of the event to register the handler for
- * @param[in] event_id the id of the event to register the handler for
- * @param[in] event_handler the handler function which gets called when the event is dispatched
- * @param[in] event_handler_arg data, aside from event data, that is passed to the handler when it is called
- *
- * @note the event loop library does not maintain a copy of event_handler_arg, therefore the user should
- * ensure that event_handler_arg still points to a valid location by the time the handler gets called
- *
- * @return
- *  - ESP_OK: Success
- *  - ESP_ERR_NO_MEM: Cannot allocate memory for the handler
- *  - ESP_ERR_INVALID_ARG: Invalid combination of event base and event id
- *  - Others: Fail
- */
-esp_err_t esp_event_handler_register_with(esp_event_loop_handle_t event_loop,
-                                            esp_event_base_t event_base,
-                                            int32_t event_id,
-                                            esp_event_handler_t event_handler,
-                                            void* event_handler_arg);
-
-/**
- * @brief Unregister a handler with the system event loop.
- *
- * This function can be used to unregister a handler so that it no longer gets called during dispatch.
- * Handlers can be unregistered for either: (1) specific events, (2) all events of a certain event base,
- * or (3) all events known by the system event loop
- *
- *  - specific events: specify exact event_base and event_id
- *  - all events of a certain base: specify exact event_base and use ESP_EVENT_ANY_ID as the event_id
- *  - all events known by the loop: use ESP_EVENT_ANY_BASE for event_base and ESP_EVENT_ANY_ID as the event_id
- *
- * This function ignores unregistration of handlers that has not been previously registered.
- *
- * @param[in] event_base the base of the event with which to unregister the handler
- * @param[in] event_id the id of the event with which to unregister the handler
- * @param[in] event_handler the handler to unregister
- *
- * @return ESP_OK success
- * @return ESP_ERR_INVALID_ARG invalid combination of event base and event id
- * @return others fail
- */
-esp_err_t esp_event_handler_unregister(esp_event_base_t event_base, int32_t event_id, esp_event_handler_t event_handler);
-
-/**
- * @brief Unregister a handler with the system event loop.
- *
- * This function behaves in the same manner as esp_event_handler_unregister, except the additional specification of
- * the event loop to unregister the handler with.
- *
- * @param[in] event_loop the event loop with which to unregister this handler function
- * @param[in] event_base the base of the event with which to unregister the handler
- * @param[in] event_id the id of the event with which to unregister the handler
- * @param[in] event_handler the handler to unregister
- *
- * @return
- *  - ESP_OK: Success
- *  - ESP_ERR_INVALID_ARG: Invalid combination of event base and event id
- *  - Others: Fail
- */
-esp_err_t esp_event_handler_unregister_with(esp_event_loop_handle_t event_loop,
-                                            esp_event_base_t event_base,
-                                            int32_t event_id,
-                                            esp_event_handler_t event_handler);
-
-/**
- * @brief Posts an event to the system default event loop. The event loop library keeps a copy of event_data and manages
- * the copy's lifetime automatically (allocation + deletion); this ensures that the data the
- * handler recieves is always valid.
- *
- * @param[in] event_base the event base that identifies the event
- * @param[in] event_id the the event id that identifies the event
- * @param[in] event_data the data, specific to the event occurence, that gets passed to the handler
- * @param[in] event_data_size the size of the event data
- * @param[in] ticks_to_wait number of ticks to block on a full event queue
- *
- * @note posting events from an ISR is not supported
- *
- * @return
- *  - ESP_OK: Success
- *  - ESP_ERR_TIMEOUT: Time to wait for event queue to unblock expired
- *  - ESP_ERR_INVALID_ARG: Invalid combination of event base and event id
- *  - Others: Fail
- */
-esp_err_t esp_event_post(esp_event_base_t event_base,
-                            int32_t event_id,
-                            void* event_data,
-                            size_t event_data_size,
-                            TickType_t ticks_to_wait);
-
-/**
- * @brief Posts an event to the specified event loop. The event loop library keeps a copy of event_data and manages
- * the copy's lifetime automatically (allocation + deletion); this ensures that the data the
- * handler recieves is always valid.
- *
- * This function behaves in the same manner as esp_event_post_to, except the additional specification of the event loop
- * to post the event to.
- *
- * @param[in] event_loop the event loop to post to
- * @param[in] event_base the event base that identifies the event
- * @param[in] event_id the the event id that identifies the event
- * @param[in] event_data the data, specific to the event occurence, that gets passed to the handler
- * @param[in] event_data_size the size of the event data
- * @param[in] ticks_to_wait number of ticks to block on a full event queue
- *
- * @note posting events from an ISR is not supported
- *
- * @return
- *  - ESP_OK: Success
- *  - ESP_ERR_TIMEOUT: Time to wait for event queue to unblock expired
- *  - ESP_ERR_INVALID_ARG: Invalid combination of event base and event id
- *  - Others: Fail
- */
-esp_err_t esp_event_post_to(esp_event_loop_handle_t event_loop,
-                            esp_event_base_t event_base,
-                            int32_t event_id,
-                            void* event_data,
-                            size_t event_data_size,
-                            TickType_t ticks_to_wait);
-
-/**
- * @brief Dumps statistics of all event loops.
- *
- * Dumps event loop info in the format:
- *
- @verbatim
-       event loop
-           handler
-           handler
-           ...
-       event loop
-           handler
-           handler
-           ...
-
-  where:
-
-   event loop
-       format: address,name rx:total_recieved dr:total_dropped
-       where:
-           address - memory address of the event loop
-           name - name of the event loop, 'none' if no dedicated task
-           total_recieved - number of successfully posted events
-           total_dropped - number of events unsuccessfully posted due to queue being full
-
-   handler
-       format: address ev:base,id inv:total_invoked run:total_runtime
-       where:
-           address - address of the handler function
-           base,id - the event specified by event base and id this handler executes
-           total_invoked - number of times this handler has been invoked
-           total_runtime - total amount of time used for invoking this handler
-
- @endverbatim
- *
- * @param[in] file the file stream to output to
- *
- * @note this function is a noop when CONFIG_EVENT_LOOP_PROFILING is disabled
- *
- * @return
- *  - ESP_OK: Success
- *  - ESP_ERR_NO_MEM: Cannot allocate memory for event loops list
- *  - Others: Fail
- */
-esp_err_t esp_event_dump(FILE* file);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif // #ifndef ESP_EVENT_H_
\ No newline at end of file
diff --git a/tools/sdk/include/esp_event/esp_event_base.h b/tools/sdk/include/esp_event/esp_event_base.h
deleted file mode 100644
index d2fd3804283..00000000000
--- a/tools/sdk/include/esp_event/esp_event_base.h
+++ /dev/null
@@ -1,43 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//         http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef ESP_EVENT_BASE_H_
-#define ESP_EVENT_BASE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Defines for declaring and defining event base
-#define ESP_EVENT_DECLARE_BASE(id) extern esp_event_base_t id;
-#define ESP_EVENT_DEFINE_BASE(id) esp_event_base_t id = #id;
-
-// Event loop library types
-typedef const char*  esp_event_base_t; /**< unique pointer to a subsystem that exposes events */
-typedef void*        esp_event_loop_handle_t; /**< a number that identifies an event with respect to a base */
-typedef void         (*esp_event_handler_t)(void* event_handler_arg, 
-                                        esp_event_base_t event_base, 
-                                        int32_t event_id, 
-                                        void* event_data); /**< function called when an event is posted to the queue */
-
-
-// Defines for registering/unregistering event handlers
-#define ESP_EVENT_ANY_BASE     NULL             /**< register handler for any event base */
-#define ESP_EVENT_ANY_ID       -1               /**< register handler for any event id */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // #ifndef ESP_EVENT_BASE_H_
diff --git a/tools/sdk/include/esp_http_client/esp_http_client.h b/tools/sdk/include/esp_http_client/esp_http_client.h
deleted file mode 100644
index 4ee0ff359b4..00000000000
--- a/tools/sdk/include/esp_http_client/esp_http_client.h
+++ /dev/null
@@ -1,489 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_HTTP_CLIENT_H
-#define _ESP_HTTP_CLIENT_H
-
-#include "freertos/FreeRTOS.h"
-#include "http_parser.h"
-#include "sdkconfig.h"
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DEFAULT_HTTP_BUF_SIZE (512)
-
-typedef struct esp_http_client *esp_http_client_handle_t;
-typedef struct esp_http_client_event *esp_http_client_event_handle_t;
-
-/**
- * @brief   HTTP Client events id
- */
-typedef enum {
-    HTTP_EVENT_ERROR = 0,       /*!< This event occurs when there are any errors during execution */
-    HTTP_EVENT_ON_CONNECTED,    /*!< Once the HTTP has been connected to the server, no data exchange has been performed */
-    HTTP_EVENT_HEADER_SENT,     /*!< After sending all the headers to the server */
-    HTTP_EVENT_ON_HEADER,       /*!< Occurs when receiving each header sent from the server */
-    HTTP_EVENT_ON_DATA,         /*!< Occurs when receiving data from the server, possibly multiple portions of the packet */
-    HTTP_EVENT_ON_FINISH,       /*!< Occurs when finish a HTTP session */
-    HTTP_EVENT_DISCONNECTED,    /*!< The connection has been disconnected */
-} esp_http_client_event_id_t;
-
-/**
- * @brief      HTTP Client events data
- */
-typedef struct esp_http_client_event {
-    esp_http_client_event_id_t event_id;    /*!< event_id, to know the cause of the event */
-    esp_http_client_handle_t client;        /*!< esp_http_client_handle_t context */
-    void *data;                             /*!< data of the event */
-    int data_len;                           /*!< data length of data */
-    void *user_data;                        /*!< user_data context, from esp_http_client_config_t user_data */
-    char *header_key;                       /*!< For HTTP_EVENT_ON_HEADER event_id, it's store current http header key */
-    char *header_value;                     /*!< For HTTP_EVENT_ON_HEADER event_id, it's store current http header value */
-} esp_http_client_event_t;
-
-
-/**
- * @brief      HTTP Client transport
- */
-typedef enum {
-    HTTP_TRANSPORT_UNKNOWN = 0x0,   /*!< Unknown */
-    HTTP_TRANSPORT_OVER_TCP,        /*!< Transport over tcp */
-    HTTP_TRANSPORT_OVER_SSL,        /*!< Transport over ssl */
-} esp_http_client_transport_t;
-
-typedef esp_err_t (*http_event_handle_cb)(esp_http_client_event_t *evt);
-
-/**
- * @brief HTTP method
- */
-typedef enum {
-    HTTP_METHOD_GET = 0,    /*!< HTTP GET Method */
-    HTTP_METHOD_POST,       /*!< HTTP POST Method */
-    HTTP_METHOD_PUT,        /*!< HTTP PUT Method */
-    HTTP_METHOD_PATCH,      /*!< HTTP PATCH Method */
-    HTTP_METHOD_DELETE,     /*!< HTTP DELETE Method */
-    HTTP_METHOD_HEAD,       /*!< HTTP HEAD Method */
-    HTTP_METHOD_NOTIFY,     /*!< HTTP NOTIFY Method */
-    HTTP_METHOD_SUBSCRIBE,  /*!< HTTP SUBSCRIBE Method */
-    HTTP_METHOD_UNSUBSCRIBE,/*!< HTTP UNSUBSCRIBE Method */
-    HTTP_METHOD_OPTIONS,    /*!< HTTP OPTIONS Method */
-    HTTP_METHOD_MAX,
-} esp_http_client_method_t;
-
-/**
- * @brief HTTP Authentication type
- */
-typedef enum {
-    HTTP_AUTH_TYPE_NONE = 0,    /*!< No authention */
-    HTTP_AUTH_TYPE_BASIC,       /*!< HTTP Basic authentication */
-    HTTP_AUTH_TYPE_DIGEST,      /*!< HTTP Disgest authentication */
-} esp_http_client_auth_type_t;
-
-/**
- * @brief HTTP configuration
- */
-typedef struct {
-    const char                  *url;                /*!< HTTP URL, the information on the URL is most important, it overrides the other fields below, if any */
-    const char                  *host;               /*!< Domain or IP as string */
-    int                         port;                /*!< Port to connect, default depend on esp_http_client_transport_t (80 or 443) */
-    const char                  *username;           /*!< Using for Http authentication */
-    const char                  *password;           /*!< Using for Http authentication */
-    esp_http_client_auth_type_t auth_type;           /*!< Http authentication type, see `esp_http_client_auth_type_t` */
-    const char                  *path;               /*!< HTTP Path, if not set, default is `/` */
-    const char                  *query;              /*!< HTTP query */
-    const char                  *cert_pem;           /*!< SSL server certification, PEM format as string, if the client requires to verify server */
-    const char                  *client_cert_pem;    /*!< SSL client certification, PEM format as string, if the server requires to verify client */
-    const char                  *client_key_pem;     /*!< SSL client key, PEM format as string, if the server requires to verify client */
-    esp_http_client_method_t    method;                   /*!< HTTP Method */
-    int                         timeout_ms;               /*!< Network timeout in milliseconds */
-    bool                        disable_auto_redirect;    /*!< Disable HTTP automatic redirects */
-    int                         max_redirection_count;    /*!< Max redirection number, using default value if zero*/
-    http_event_handle_cb        event_handler;             /*!< HTTP Event Handle */
-    esp_http_client_transport_t transport_type;           /*!< HTTP transport type, see `esp_http_client_transport_t` */
-    int                         buffer_size;              /*!< HTTP buffer size (both send and receive) */
-    void                        *user_data;               /*!< HTTP user_data context */
-    bool                        is_async;                 /*!< Set asynchronous mode, only supported with HTTPS for now */
-    bool                        use_global_ca_store;      /*!< Use a global ca_store for all the connections in which this bool is set. */
-    bool                        skip_cert_common_name_check;    /*!< Skip any validation of server certificate CN field */
-} esp_http_client_config_t;
-
-/**
- * Enum for the HTTP status codes.
- */
-typedef enum {
-    /* 3xx - Redirection */
-    HttpStatus_MovedPermanently  = 301,
-    HttpStatus_Found             = 302,
-
-    /* 4xx - Client Error */
-    HttpStatus_Unauthorized      = 401
-} HttpStatus_Code;
-
-#define ESP_ERR_HTTP_BASE               (0x7000)                    /*!< Starting number of HTTP error codes */
-#define ESP_ERR_HTTP_MAX_REDIRECT       (ESP_ERR_HTTP_BASE + 1)     /*!< The error exceeds the number of HTTP redirects */
-#define ESP_ERR_HTTP_CONNECT            (ESP_ERR_HTTP_BASE + 2)     /*!< Error open the HTTP connection */
-#define ESP_ERR_HTTP_WRITE_DATA         (ESP_ERR_HTTP_BASE + 3)     /*!< Error write HTTP data */
-#define ESP_ERR_HTTP_FETCH_HEADER       (ESP_ERR_HTTP_BASE + 4)     /*!< Error read HTTP header from server */
-#define ESP_ERR_HTTP_INVALID_TRANSPORT  (ESP_ERR_HTTP_BASE + 5)     /*!< There are no transport support for the input scheme */
-#define ESP_ERR_HTTP_CONNECTING         (ESP_ERR_HTTP_BASE + 6)     /*!< HTTP connection hasn't been established yet */
-#define ESP_ERR_HTTP_EAGAIN             (ESP_ERR_HTTP_BASE + 7)     /*!< Mapping of errno EAGAIN to esp_err_t */
-
-/**
- * @brief      Start a HTTP session
- *             This function must be the first function to call,
- *             and it returns a esp_http_client_handle_t that you must use as input to other functions in the interface.
- *             This call MUST have a corresponding call to esp_http_client_cleanup when the operation is complete.
- *
- * @param[in]  config   The configurations, see `http_client_config_t`
- *
- * @return
- *     - `esp_http_client_handle_t`
- *     - NULL if any errors
- */
-esp_http_client_handle_t esp_http_client_init(const esp_http_client_config_t *config);
-
-/**
- * @brief      Invoke this function after `esp_http_client_init` and all the options calls are made, and will perform the
- *             transfer as described in the options. It must be called with the same esp_http_client_handle_t as input as the esp_http_client_init call returned.
- *             esp_http_client_perform performs the entire request in either blocking or non-blocking manner. By default, the API performs request in a blocking manner and returns when done,
- *             or if it failed, and in non-blocking manner, it returns if EAGAIN/EWOULDBLOCK or EINPROGRESS is encountered, or if it failed. And in case of non-blocking request,
- *             the user may call this API multiple times unless request & response is complete or there is a failure. To enable non-blocking esp_http_client_perform(), `is_async` member of esp_http_client_config_t
- *             must be set while making a call to esp_http_client_init() API.
- *             You can do any amount of calls to esp_http_client_perform while using the same esp_http_client_handle_t. The underlying connection may be kept open if the server allows it.
- *             If you intend to transfer more than one file, you are even encouraged to do so.
- *             esp_http_client will then attempt to re-use the same connection for the following transfers, thus making the operations faster, less CPU intense and using less network resources.
- *             Just note that you will have to use `esp_http_client_set_**` between the invokes to set options for the following esp_http_client_perform.
- *
- * @note       You must never call this function simultaneously from two places using the same client handle.
- *             Let the function return first before invoking it another time.
- *             If you want parallel transfers, you must use several esp_http_client_handle_t.
- *             This function include `esp_http_client_open` -> `esp_http_client_write` -> `esp_http_client_fetch_headers` -> `esp_http_client_read` (and option) `esp_http_client_close`.
- *
- * @param      client  The esp_http_client handle
- *
- * @return
- *  - ESP_OK on successful
- *  - ESP_FAIL on error
- */
-esp_err_t esp_http_client_perform(esp_http_client_handle_t client);
-
-/**
- * @brief      Set URL for client, when performing this behavior, the options in the URL will replace the old ones
- *
- * @param[in]  client  The esp_http_client handle
- * @param[in]  url     The url
- *
- * @return
- *  - ESP_OK
- *  - ESP_FAIL
- */
-esp_err_t esp_http_client_set_url(esp_http_client_handle_t client, const char *url);
-
-/**
- * @brief      Set post data, this function must be called before `esp_http_client_perform`.
- *             Note: The data parameter passed to this function is a pointer and this function will not copy the data
- *
- * @param[in]  client  The esp_http_client handle
- * @param[in]  data    post data pointer
- * @param[in]  len     post length
- *
- * @return
- *  - ESP_OK
- *  - ESP_FAIL
- */
-esp_err_t esp_http_client_set_post_field(esp_http_client_handle_t client, const char *data, int len);
-
-/**
- * @brief      Get current post field information
- *
- * @param[in]  client  The client
- * @param[out] data    Point to post data pointer
- *
- * @return     Size of post data
- */
-int esp_http_client_get_post_field(esp_http_client_handle_t client, char **data);
-
-/**
- * @brief      Set http request header, this function must be called after esp_http_client_init and before any
- *             perform function
- *
- * @param[in]  client  The esp_http_client handle
- * @param[in]  key     The header key
- * @param[in]  value   The header value
- *
- * @return
- *  - ESP_OK
- *  - ESP_FAIL
- */
-esp_err_t esp_http_client_set_header(esp_http_client_handle_t client, const char *key, const char *value);
-
-/**
- * @brief      Get http request header.
- *             The value parameter will be set to NULL if there is no header which is same as
- *             the key specified, otherwise the address of header value will be assigned to value parameter.
- *             This function must be called after `esp_http_client_init`.
- *
- * @param[in]  client  The esp_http_client handle
- * @param[in]  key     The header key
- * @param[out] value   The header value
- *
- * @return
- *     - ESP_OK
- *     - ESP_FAIL
- */
-esp_err_t esp_http_client_get_header(esp_http_client_handle_t client, const char *key, char **value);
-
-/**
- * @brief      Get http request username.
- *             The address of username buffer will be assigned to value parameter.
- *             This function must be called after `esp_http_client_init`.
- *
- * @param[in]  client  The esp_http_client handle
- * @param[out] value   The username value
- *
- * @return
- *     - ESP_OK
- *     - ESP_ERR_INVALID_ARG
- */
-esp_err_t esp_http_client_get_username(esp_http_client_handle_t client, char **value);
-
-/**
- * @brief      Set http request username.
- *             The value of username parameter will be assigned to username buffer.
- *             If the username parameter is NULL then username buffer will be freed.
- *
- * @param[in]  client    The esp_http_client handle
- * @param[in]  username  The username value
- *
- * @return
- *     - ESP_OK
- *     - ESP_ERR_INVALID_ARG
- */
-esp_err_t esp_http_client_set_username(esp_http_client_handle_t client, const char *username);
-
-/**
- * @brief      Get http request password.
- *             The address of password buffer will be assigned to value parameter.
- *             This function must be called after `esp_http_client_init`.
- *
- * @param[in]  client  The esp_http_client handle
- * @param[out] value   The password value
- *
- * @return
- *     - ESP_OK
- *     - ESP_ERR_INVALID_ARG
- */
-esp_err_t esp_http_client_get_password(esp_http_client_handle_t client, char **value);
-
-/**
- * @brief      Set http request password.
- *             The value of password parameter will be assigned to password buffer.
- *             If the password parameter is NULL then password buffer will be freed.
- *
- * @param[in]  client    The esp_http_client handle
- * @param[in]  password  The password value
- *
- * @return
- *     - ESP_OK
- *     - ESP_ERR_INVALID_ARG
- */
-esp_err_t esp_http_client_set_password(esp_http_client_handle_t client, char *password);
-
-/**
- * @brief      Set http request method
- *
- * @param[in]  client  The esp_http_client handle
- * @param[in]  method  The method
- *
- * @return
- *     - ESP_OK
- *     - ESP_ERR_INVALID_ARG
- */
-esp_err_t esp_http_client_set_method(esp_http_client_handle_t client, esp_http_client_method_t method);
-
-/**
- * @brief      Delete http request header
- *
- * @param[in]  client  The esp_http_client handle
- * @param[in]  key     The key
- *
- * @return
- *  - ESP_OK
- *  - ESP_FAIL
- */
-esp_err_t esp_http_client_delete_header(esp_http_client_handle_t client, const char *key);
-
-/**
- * @brief      This function will be open the connection, write all header strings and return
- *
- * @param[in]  client     The esp_http_client handle
- * @param[in]  write_len  HTTP Content length need to write to the server
- *
- * @return
- *  - ESP_OK
- *  - ESP_FAIL
- */
-esp_err_t esp_http_client_open(esp_http_client_handle_t client, int write_len);
-
-/**
- * @brief     This function will write data to the HTTP connection previously opened by esp_http_client_open()
- *
- * @param[in]  client  The esp_http_client handle
- * @param      buffer  The buffer
- * @param[in]  len     This value must not be larger than the write_len parameter provided to esp_http_client_open()
- *
- * @return
- *     - (-1) if any errors
- *     - Length of data written
- */
-int esp_http_client_write(esp_http_client_handle_t client, const char *buffer, int len);
-
-/**
- * @brief      This function need to call after esp_http_client_open, it will read from http stream, process all receive headers
- *
- * @param[in]  client  The esp_http_client handle
- *
- * @return
- *     - (0) if stream doesn't contain content-length header, or chunked encoding (checked by `esp_http_client_is_chunked` response)
- *     - (-1: ESP_FAIL) if any errors
- *     - Download data length defined by content-length header
- */
-int esp_http_client_fetch_headers(esp_http_client_handle_t client);
-
-
-/**
- * @brief      Check response data is chunked
- *
- * @param[in]  client  The esp_http_client handle
- *
- * @return     true or false
- */
-bool esp_http_client_is_chunked_response(esp_http_client_handle_t client);
-
-/**
- * @brief      Read data from http stream
- *
- * @param[in]  client  The esp_http_client handle
- * @param      buffer  The buffer
- * @param[in]  len     The length
- *
- * @return
- *     - (-1) if any errors
- *     - Length of data was read
- */
-int esp_http_client_read(esp_http_client_handle_t client, char *buffer, int len);
-
-
-/**
- * @brief      Get http response status code, the valid value if this function invoke after `esp_http_client_perform`
- *
- * @param[in]  client  The esp_http_client handle
- *
- * @return     Status code
- */
-int esp_http_client_get_status_code(esp_http_client_handle_t client);
-
-/**
- * @brief      Get http response content length (from header Content-Length)
- *             the valid value if this function invoke after `esp_http_client_perform`
- *
- * @param[in]  client  The esp_http_client handle
- *
- * @return
- *     - (-1) Chunked transfer
- *     - Content-Length value as bytes
- */
-int esp_http_client_get_content_length(esp_http_client_handle_t client);
-
-/**
- * @brief      Close http connection, still kept all http request resources
- *
- * @param[in]  client  The esp_http_client handle
- *
- * @return
- *     - ESP_OK
- *     - ESP_FAIL
- */
-esp_err_t esp_http_client_close(esp_http_client_handle_t client);
-
-/**
- * @brief      This function must be the last function to call for an session.
- *             It is the opposite of the esp_http_client_init function and must be called with the same handle as input that a esp_http_client_init call returned.
- *             This might close all connections this handle has used and possibly has kept open until now.
- *             Don't call this function if you intend to transfer more files, re-using handles is a key to good performance with esp_http_client.
- *
- * @param[in]  client  The esp_http_client handle
- *
- * @return
- *     - ESP_OK
- *     - ESP_FAIL
- */
-esp_err_t esp_http_client_cleanup(esp_http_client_handle_t client);
-
-/**
- * @brief      Get transport type
- *
- * @param[in]  client   The esp_http_client handle
- *
- * @return
- *     - HTTP_TRANSPORT_UNKNOWN
- *     - HTTP_TRANSPORT_OVER_TCP
- *     - HTTP_TRANSPORT_OVER_SSL
- */
-esp_http_client_transport_t esp_http_client_get_transport_type(esp_http_client_handle_t client);
-
-/**
- * @brief      Set redirection URL.
- *             When received the 30x code from the server, the client stores the redirect URL provided by the server.
- *             This function will set the current URL to redirect to enable client to execute the redirection request.
- *
- * @param[in]  client  The esp_http_client handle
- *
- * @return      
- *     - ESP_OK
- *     - ESP_FAIL
- */
-esp_err_t esp_http_client_set_redirection(esp_http_client_handle_t client);
-
-/**
- * @brief      On receiving HTTP Status code 401, this API can be invoked to add authorization
- *             information.
- *
- * @note       There is a possibility of receiving body message with redirection status codes, thus make sure
- *             to flush off body data after calling this API.
- *
- * @param[in]  client   The esp_http_client handle
- */
-void esp_http_client_add_auth(esp_http_client_handle_t client);
-
-/**
- * @brief      Checks if entire data in the response has been read without any error.
- *
- * @param[in]  client   The esp_http_client handle
- * 
- * @return
- *     - true
- *     - false
- */
-bool esp_http_client_is_complete_data_received(esp_http_client_handle_t client);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif
diff --git a/tools/sdk/include/esp_http_server/esp_http_server.h b/tools/sdk/include/esp_http_server/esp_http_server.h
deleted file mode 100644
index fc448500ede..00000000000
--- a/tools/sdk/include/esp_http_server/esp_http_server.h
+++ /dev/null
@@ -1,1457 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_HTTP_SERVER_H_
-#define _ESP_HTTP_SERVER_H_
-
-#include <stdio.h>
-#include <string.h>
-#include <freertos/FreeRTOS.h>
-#include <freertos/task.h>
-#include <http_parser.h>
-#include <sdkconfig.h>
-#include <esp_err.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
-note: esp_https_server.h includes a customized copy of this
-initializer that should be kept in sync
-*/
-#define HTTPD_DEFAULT_CONFIG() {                        \
-        .task_priority      = tskIDLE_PRIORITY+5,       \
-        .stack_size         = 4096,                     \
-        .server_port        = 80,                       \
-        .ctrl_port          = 32768,                    \
-        .max_open_sockets   = 7,                        \
-        .max_uri_handlers   = 8,                        \
-        .max_resp_headers   = 8,                        \
-        .backlog_conn       = 5,                        \
-        .lru_purge_enable   = false,                    \
-        .recv_wait_timeout  = 5,                        \
-        .send_wait_timeout  = 5,                        \
-        .global_user_ctx = NULL,                        \
-        .global_user_ctx_free_fn = NULL,                \
-        .global_transport_ctx = NULL,                   \
-        .global_transport_ctx_free_fn = NULL,           \
-        .open_fn = NULL,                                \
-        .close_fn = NULL,                               \
-        .uri_match_fn = NULL                            \
-}
-
-#define ESP_ERR_HTTPD_BASE              (0x8000)                    /*!< Starting number of HTTPD error codes */
-#define ESP_ERR_HTTPD_HANDLERS_FULL     (ESP_ERR_HTTPD_BASE +  1)   /*!< All slots for registering URI handlers have been consumed */
-#define ESP_ERR_HTTPD_HANDLER_EXISTS    (ESP_ERR_HTTPD_BASE +  2)   /*!< URI handler with same method and target URI already registered */
-#define ESP_ERR_HTTPD_INVALID_REQ       (ESP_ERR_HTTPD_BASE +  3)   /*!< Invalid request pointer */
-#define ESP_ERR_HTTPD_RESULT_TRUNC      (ESP_ERR_HTTPD_BASE +  4)   /*!< Result string truncated */
-#define ESP_ERR_HTTPD_RESP_HDR          (ESP_ERR_HTTPD_BASE +  5)   /*!< Response header field larger than supported */
-#define ESP_ERR_HTTPD_RESP_SEND         (ESP_ERR_HTTPD_BASE +  6)   /*!< Error occured while sending response packet */
-#define ESP_ERR_HTTPD_ALLOC_MEM         (ESP_ERR_HTTPD_BASE +  7)   /*!< Failed to dynamically allocate memory for resource */
-#define ESP_ERR_HTTPD_TASK              (ESP_ERR_HTTPD_BASE +  8)   /*!< Failed to launch server task/thread */
-
-/* Symbol to be used as length parameter in httpd_resp_send APIs
- * for setting buffer length to string length */
-#define HTTPD_RESP_USE_STRLEN -1
-
-/* ************** Group: Initialization ************** */
-/** @name Initialization
- * APIs related to the Initialization of the web server
- * @{
- */
-
-/**
- * @brief   HTTP Server Instance Handle
- *
- * Every instance of the server will have a unique handle.
- */
-typedef void* httpd_handle_t;
-
-/**
- * @brief   HTTP Method Type wrapper over "enum http_method"
- *          available in "http_parser" library
- */
-typedef enum http_method httpd_method_t;
-
-/**
- * @brief  Prototype for freeing context data (if any)
- * @param[in] ctx   object to free
- */
-typedef void (*httpd_free_ctx_fn_t)(void *ctx);
-
-/**
- * @brief  Function prototype for opening a session.
- *
- * Called immediately after the socket was opened to set up the send/recv functions and
- * other parameters of the socket.
- *
- * @param[in] hd       server instance
- * @param[in] sockfd   session socket file descriptor
- * @return
- *  - ESP_OK   : On success
- *  - Any value other than ESP_OK will signal the server to close the socket immediately
- */
-typedef esp_err_t (*httpd_open_func_t)(httpd_handle_t hd, int sockfd);
-
-/**
- * @brief  Function prototype for closing a session.
- *
- * @note   It's possible that the socket descriptor is invalid at this point, the function
- *         is called for all terminated sessions. Ensure proper handling of return codes.
- *
- * @param[in] hd   server instance
- * @param[in] sockfd   session socket file descriptor
- */
-typedef void (*httpd_close_func_t)(httpd_handle_t hd, int sockfd);
-
-/**
- * @brief  Function prototype for URI matching.
- *
- * @param[in] reference_uri   URI/template with respect to which the other URI is matched
- * @param[in] uri_to_match    URI/template being matched to the reference URI/template
- * @param[in] match_upto      For specifying the actual length of `uri_to_match` up to
- *                            which the matching algorithm is to be applied (The maximum
- *                            value is `strlen(uri_to_match)`, independent of the length
- *                            of `reference_uri`)
- * @return true on match
- */
-typedef bool (*httpd_uri_match_func_t)(const char *reference_uri,
-                                       const char *uri_to_match,
-                                       size_t match_upto);
-
-/**
- * @brief   HTTP Server Configuration Structure
- *
- * @note    Use HTTPD_DEFAULT_CONFIG() to initialize the configuration
- *          to a default value and then modify only those fields that are
- *          specifically determined by the use case.
- */
-typedef struct httpd_config {
-    unsigned    task_priority;      /*!< Priority of FreeRTOS task which runs the server */
-    size_t      stack_size;         /*!< The maximum stack size allowed for the server task */
-
-    /**
-     * TCP Port number for receiving and transmitting HTTP traffic
-     */
-    uint16_t    server_port;
-
-    /**
-     * UDP Port number for asynchronously exchanging control signals
-     * between various components of the server
-     */
-    uint16_t    ctrl_port;
-
-    uint16_t    max_open_sockets;   /*!< Max number of sockets/clients connected at any time*/
-    uint16_t    max_uri_handlers;   /*!< Maximum allowed uri handlers */
-    uint16_t    max_resp_headers;   /*!< Maximum allowed additional headers in HTTP response */
-    uint16_t    backlog_conn;       /*!< Number of backlog connections */
-    bool        lru_purge_enable;   /*!< Purge "Least Recently Used" connection */
-    uint16_t    recv_wait_timeout;  /*!< Timeout for recv function (in seconds)*/
-    uint16_t    send_wait_timeout;  /*!< Timeout for send function (in seconds)*/
-
-    /**
-     * Global user context.
-     *
-     * This field can be used to store arbitrary user data within the server context.
-     * The value can be retrieved using the server handle, available e.g. in the httpd_req_t struct.
-     *
-     * When shutting down, the server frees up the user context by
-     * calling free() on the global_user_ctx field. If you wish to use a custom
-     * function for freeing the global user context, please specify that here.
-     */
-    void * global_user_ctx;
-
-    /**
-     * Free function for global user context
-     */
-    httpd_free_ctx_fn_t global_user_ctx_free_fn;
-
-    /**
-     * Global transport context.
-     *
-     * Similar to global_user_ctx, but used for session encoding or encryption (e.g. to hold the SSL context).
-     * It will be freed using free(), unless global_transport_ctx_free_fn is specified.
-     */
-    void * global_transport_ctx;
-
-    /**
-     * Free function for global transport context
-     */
-    httpd_free_ctx_fn_t global_transport_ctx_free_fn;
-
-    /**
-     * Custom session opening callback.
-     *
-     * Called on a new session socket just after accept(), but before reading any data.
-     *
-     * This is an opportunity to set up e.g. SSL encryption using global_transport_ctx
-     * and the send/recv/pending session overrides.
-     *
-     * If a context needs to be maintained between these functions, store it in the session using
-     * httpd_sess_set_transport_ctx() and retrieve it later with httpd_sess_get_transport_ctx()
-     *
-     * Returning a value other than ESP_OK will immediately close the new socket.
-     */
-    httpd_open_func_t open_fn;
-
-    /**
-     * Custom session closing callback.
-     *
-     * Called when a session is deleted, before freeing user and transport contexts and before
-     * closing the socket. This is a place for custom de-init code common to all sockets.
-     *
-     * Set the user or transport context to NULL if it was freed here, so the server does not
-     * try to free it again.
-     *
-     * This function is run for all terminated sessions, including sessions where the socket
-     * was closed by the network stack - that is, the file descriptor may not be valid anymore.
-     */
-    httpd_close_func_t close_fn;
-
-    /**
-     * URI matcher function.
-     *
-     * Called when searching for a matching URI:
-     *     1) whose request handler is to be executed right
-     *        after an HTTP request is successfully parsed
-     *     2) in order to prevent duplication while registering
-     *        a new URI handler using `httpd_register_uri_handler()`
-     *
-     * Available options are:
-     *     1) NULL : Internally do basic matching using `strncmp()`
-     *     2) `httpd_uri_match_wildcard()` : URI wildcard matcher
-     *
-     * Users can implement their own matching functions (See description
-     * of the `httpd_uri_match_func_t` function prototype)
-     */
-    httpd_uri_match_func_t uri_match_fn;
-} httpd_config_t;
-
-/**
- * @brief Starts the web server
- *
- * Create an instance of HTTP server and allocate memory/resources for it
- * depending upon the specified configuration.
- *
- * Example usage:
- * @code{c}
- *
- * //Function for starting the webserver
- * httpd_handle_t start_webserver(void)
- * {
- *      // Generate default configuration
- *      httpd_config_t config = HTTPD_DEFAULT_CONFIG();
- *
- *      // Empty handle to http_server
- *      httpd_handle_t server = NULL;
- *
- *      // Start the httpd server
- *      if (httpd_start(&server, &config) == ESP_OK) {
- *          // Register URI handlers
- *          httpd_register_uri_handler(server, &uri_get);
- *          httpd_register_uri_handler(server, &uri_post);
- *      }
- *      // If server failed to start, handle will be NULL
- *      return server;
- * }
- *
- * @endcode
- *
- * @param[in]  config   Configuration for new instance of the server
- * @param[out] handle   Handle to newly created instance of the server. NULL on error
- * @return
- *  - ESP_OK    : Instance created successfully
- *  - ESP_ERR_INVALID_ARG      : Null argument(s)
- *  - ESP_ERR_HTTPD_ALLOC_MEM  : Failed to allocate memory for instance
- *  - ESP_ERR_HTTPD_TASK       : Failed to launch server task
- */
-esp_err_t  httpd_start(httpd_handle_t *handle, const httpd_config_t *config);
-
-/**
- * @brief Stops the web server
- *
- * Deallocates memory/resources used by an HTTP server instance and
- * deletes it. Once deleted the handle can no longer be used for accessing
- * the instance.
- *
- * Example usage:
- * @code{c}
- *
- * // Function for stopping the webserver
- * void stop_webserver(httpd_handle_t server)
- * {
- *      // Ensure handle is non NULL
- *      if (server != NULL) {
- *          // Stop the httpd server
- *          httpd_stop(server);
- *      }
- * }
- *
- * @endcode
- *
- * @param[in] handle Handle to server returned by httpd_start
- * @return
- *  - ESP_OK : Server stopped successfully
- *  - ESP_ERR_INVALID_ARG : Handle argument is Null
- */
-esp_err_t httpd_stop(httpd_handle_t handle);
-
-/** End of Group Initialization
- * @}
- */
-
-/* ************** Group: URI Handlers ************** */
-/** @name URI Handlers
- * APIs related to the URI handlers
- * @{
- */
-
-/* Max supported HTTP request header length */
-#define HTTPD_MAX_REQ_HDR_LEN CONFIG_HTTPD_MAX_REQ_HDR_LEN
-
-/* Max supported HTTP request URI length */
-#define HTTPD_MAX_URI_LEN CONFIG_HTTPD_MAX_URI_LEN
-
-/**
- * @brief HTTP Request Data Structure
- */
-typedef struct httpd_req {
-    httpd_handle_t  handle;                     /*!< Handle to server instance */
-    int             method;                     /*!< The type of HTTP request, -1 if unsupported method */
-    const char      uri[HTTPD_MAX_URI_LEN + 1]; /*!< The URI of this request (1 byte extra for null termination) */
-    size_t          content_len;                /*!< Length of the request body */
-    void           *aux;                        /*!< Internally used members */
-
-    /**
-     * User context pointer passed during URI registration.
-     */
-    void *user_ctx;
-
-    /**
-     * Session Context Pointer
-     *
-     * A session context. Contexts are maintained across 'sessions' for a
-     * given open TCP connection. One session could have multiple request
-     * responses. The web server will ensure that the context persists
-     * across all these request and responses.
-     *
-     * By default, this is NULL. URI Handlers can set this to any meaningful
-     * value.
-     *
-     * If the underlying socket gets closed, and this pointer is non-NULL,
-     * the web server will free up the context by calling free(), unless
-     * free_ctx function is set.
-     */
-    void *sess_ctx;
-
-    /**
-     * Pointer to free context hook
-     *
-     * Function to free session context
-     *
-     * If the web server's socket closes, it frees up the session context by
-     * calling free() on the sess_ctx member. If you wish to use a custom
-     * function for freeing the session context, please specify that here.
-     */
-    httpd_free_ctx_fn_t free_ctx;
-
-    /**
-     * Flag indicating if Session Context changes should be ignored
-     *
-     * By default, if you change the sess_ctx in some URI handler, the http server
-     * will internally free the earlier context (if non NULL), after the URI handler
-     * returns. If you want to manage the allocation/reallocation/freeing of
-     * sess_ctx yourself, set this flag to true, so that the server will not
-     * perform any checks on it. The context will be cleared by the server
-     * (by calling free_ctx or free()) only if the socket gets closed.
-     */
-    bool ignore_sess_ctx_changes;
-} httpd_req_t;
-
-/**
- * @brief Structure for URI handler
- */
-typedef struct httpd_uri {
-    const char       *uri;    /*!< The URI to handle */
-    httpd_method_t    method; /*!< Method supported by the URI */
-
-    /**
-     * Handler to call for supported request method. This must
-     * return ESP_OK, or else the underlying socket will be closed.
-     */
-    esp_err_t (*handler)(httpd_req_t *r);
-
-    /**
-     * Pointer to user context data which will be available to handler
-     */
-    void *user_ctx;
-} httpd_uri_t;
-
-/**
- * @brief   Registers a URI handler
- *
- * @note    URI handlers can be registered in real time as long as the
- *          server handle is valid.
- *
- * Example usage:
- * @code{c}
- *
- * esp_err_t my_uri_handler(httpd_req_t* req)
- * {
- *     // Recv , Process and Send
- *     ....
- *     ....
- *     ....
- *
- *     // Fail condition
- *     if (....) {
- *         // Return fail to close session //
- *         return ESP_FAIL;
- *     }
- *
- *     // On success
- *     return ESP_OK;
- * }
- *
- * // URI handler structure
- * httpd_uri_t my_uri {
- *     .uri      = "/my_uri/path/xyz",
- *     .method   = HTTPD_GET,
- *     .handler  = my_uri_handler,
- *     .user_ctx = NULL
- * };
- *
- * // Register handler
- * if (httpd_register_uri_handler(server_handle, &my_uri) != ESP_OK) {
- *    // If failed to register handler
- *    ....
- * }
- *
- * @endcode
- *
- * @param[in] handle      handle to HTTPD server instance
- * @param[in] uri_handler pointer to handler that needs to be registered
- *
- * @return
- *  - ESP_OK : On successfully registering the handler
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_HTTPD_HANDLERS_FULL  : If no slots left for new handler
- *  - ESP_ERR_HTTPD_HANDLER_EXISTS : If handler with same URI and
- *                                   method is already registered
- */
-esp_err_t httpd_register_uri_handler(httpd_handle_t handle,
-                                     const httpd_uri_t *uri_handler);
-
-/**
- * @brief   Unregister a URI handler
- *
- * @param[in] handle    handle to HTTPD server instance
- * @param[in] uri       URI string
- * @param[in] method    HTTP method
- *
- * @return
- *  - ESP_OK : On successfully deregistering the handler
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_NOT_FOUND   : Handler with specified URI and method not found
- */
-esp_err_t httpd_unregister_uri_handler(httpd_handle_t handle,
-                                       const char *uri, httpd_method_t method);
-
-/**
- * @brief   Unregister all URI handlers with the specified uri string
- *
- * @param[in] handle   handle to HTTPD server instance
- * @param[in] uri      uri string specifying all handlers that need
- *                     to be deregisterd
- *
- * @return
- *  - ESP_OK : On successfully deregistering all such handlers
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_NOT_FOUND   : No handler registered with specified uri string
- */
-esp_err_t httpd_unregister_uri(httpd_handle_t handle, const char* uri);
-
-/** End of URI Handlers
- * @}
- */
-
-/* ************** Group: HTTP Error ************** */
-/** @name HTTP Error
- * Prototype for HTTP errors and error handling functions
- * @{
- */
-
-/**
- * @brief Error codes sent as HTTP response in case of errors
- *        encountered during processing of an HTTP request
- */
-typedef enum {
-    /* For any unexpected errors during parsing, like unexpected
-     * state transitions, or unhandled errors.
-     */
-    HTTPD_500_INTERNAL_SERVER_ERROR = 0,
-
-    /* For methods not supported by http_parser. Presently
-     * http_parser halts parsing when such methods are
-     * encountered and so the server responds with 400 Bad
-     * Request error instead.
-     */
-    HTTPD_501_METHOD_NOT_IMPLEMENTED,
-
-    /* When HTTP version is not 1.1 */
-    HTTPD_505_VERSION_NOT_SUPPORTED,
-
-    /* Returned when http_parser halts parsing due to incorrect
-     * syntax of request, unsupported method in request URI or
-     * due to chunked encoding / upgrade field present in headers
-     */
-    HTTPD_400_BAD_REQUEST,
-
-    /* When requested URI is not found */
-    HTTPD_404_NOT_FOUND,
-
-    /* When URI found, but method has no handler registered */
-    HTTPD_405_METHOD_NOT_ALLOWED,
-
-    /* Intended for recv timeout. Presently it's being sent
-     * for other recv errors as well. Client should expect the
-     * server to immediately close the connection after
-     * responding with this.
-     */
-    HTTPD_408_REQ_TIMEOUT,
-
-    /* Intended for responding to chunked encoding, which is
-     * not supported currently. Though unhandled http_parser
-     * callback for chunked request returns "400 Bad Request"
-     */
-    HTTPD_411_LENGTH_REQUIRED,
-
-    /* URI length greater than CONFIG_HTTPD_MAX_URI_LEN */
-    HTTPD_414_URI_TOO_LONG,
-
-    /* Headers section larger than CONFIG_HTTPD_MAX_REQ_HDR_LEN */
-    HTTPD_431_REQ_HDR_FIELDS_TOO_LARGE,
-
-    /* Used internally for retrieving the total count of errors */
-    HTTPD_ERR_CODE_MAX
-} httpd_err_code_t;
-
-/**
- * @brief  Function prototype for HTTP error handling.
- *
- * This function is executed upon HTTP errors generated during
- * internal processing of an HTTP request. This is used to override
- * the default behavior on error, which is to send HTTP error response
- * and close the underlying socket.
- *
- * @note
- *  - If implemented, the server will not automatically send out HTTP
- *    error response codes, therefore, httpd_resp_send_err() must be
- *    invoked inside this function if user wishes to generate HTTP
- *    error responses.
- *  - When invoked, the validity of `uri`, `method`, `content_len`
- *    and `user_ctx` fields of the httpd_req_t parameter is not
- *    guaranteed as the HTTP request may be partially received/parsed.
- *  - The function must return ESP_OK if underlying socket needs to
- *    be kept open. Any other value will ensure that the socket is
- *    closed. The return value is ignored when error is of type
- *    `HTTPD_500_INTERNAL_SERVER_ERROR` and the socket closed anyway.
- *
- * @param[in] req    HTTP request for which the error needs to be handled
- * @param[in] error  Error type
- *
- * @return
- *  - ESP_OK   : error handled successful
- *  - ESP_FAIL : failure indicates that the underlying socket needs to be closed
- */
-typedef esp_err_t (*httpd_err_handler_func_t)(httpd_req_t *req,
-                                              httpd_err_code_t error);
-
-/**
- * @brief  Function for registering HTTP error handlers
- *
- * This function maps a handler function to any supported error code
- * given by `httpd_err_code_t`. See prototype `httpd_err_handler_func_t`
- * above for details.
- *
- * @param[in] handle     HTTP server handle
- * @param[in] error      Error type
- * @param[in] handler_fn User implemented handler function
- *                       (Pass NULL to unset any previously set handler)
- *
- * @return
- *  - ESP_OK : handler registered successfully
- *  - ESP_ERR_INVALID_ARG : invalid error code or server handle
- */
-esp_err_t httpd_register_err_handler(httpd_handle_t handle,
-                                     httpd_err_code_t error,
-                                     httpd_err_handler_func_t handler_fn);
-
-/** End of HTTP Error
- * @}
- */
-
-/* ************** Group: TX/RX ************** */
-/** @name TX / RX
- * Prototype for HTTPDs low-level send/recv functions
- * @{
- */
-
-#define HTTPD_SOCK_ERR_FAIL      -1
-#define HTTPD_SOCK_ERR_INVALID   -2
-#define HTTPD_SOCK_ERR_TIMEOUT   -3
-
-/**
- * @brief  Prototype for HTTPDs low-level send function
- *
- * @note   User specified send function must handle errors internally,
- *         depending upon the set value of errno, and return specific
- *         HTTPD_SOCK_ERR_ codes, which will eventually be conveyed as
- *         return value of httpd_send() function
- *
- * @param[in] hd        server instance
- * @param[in] sockfd    session socket file descriptor
- * @param[in] buf       buffer with bytes to send
- * @param[in] buf_len   data size
- * @param[in] flags     flags for the send() function
- * @return
- *  - Bytes : The number of bytes sent successfully
- *  - HTTPD_SOCK_ERR_INVALID  : Invalid arguments
- *  - HTTPD_SOCK_ERR_TIMEOUT  : Timeout/interrupted while calling socket send()
- *  - HTTPD_SOCK_ERR_FAIL     : Unrecoverable error while calling socket send()
- */
-typedef int (*httpd_send_func_t)(httpd_handle_t hd, int sockfd, const char *buf, size_t buf_len, int flags);
-
-/**
- * @brief  Prototype for HTTPDs low-level recv function
- *
- * @note   User specified recv function must handle errors internally,
- *         depending upon the set value of errno, and return specific
- *         HTTPD_SOCK_ERR_ codes, which will eventually be conveyed as
- *         return value of httpd_req_recv() function
- *
- * @param[in] hd        server instance
- * @param[in] sockfd    session socket file descriptor
- * @param[in] buf       buffer with bytes to send
- * @param[in] buf_len   data size
- * @param[in] flags     flags for the send() function
- * @return
- *  - Bytes : The number of bytes received successfully
- *  - 0     : Buffer length parameter is zero / connection closed by peer
- *  - HTTPD_SOCK_ERR_INVALID  : Invalid arguments
- *  - HTTPD_SOCK_ERR_TIMEOUT  : Timeout/interrupted while calling socket recv()
- *  - HTTPD_SOCK_ERR_FAIL     : Unrecoverable error while calling socket recv()
- */
-typedef int (*httpd_recv_func_t)(httpd_handle_t hd, int sockfd, char *buf, size_t buf_len, int flags);
-
-/**
- * @brief  Prototype for HTTPDs low-level "get pending bytes" function
- *
- * @note   User specified pending function must handle errors internally,
- *         depending upon the set value of errno, and return specific
- *         HTTPD_SOCK_ERR_ codes, which will be handled accordingly in
- *         the server task.
- *
- * @param[in] hd       server instance
- * @param[in] sockfd   session socket file descriptor
- * @return
- *  - Bytes : The number of bytes waiting to be received
- *  - HTTPD_SOCK_ERR_INVALID  : Invalid arguments
- *  - HTTPD_SOCK_ERR_TIMEOUT  : Timeout/interrupted while calling socket pending()
- *  - HTTPD_SOCK_ERR_FAIL     : Unrecoverable error while calling socket pending()
- */
-typedef int (*httpd_pending_func_t)(httpd_handle_t hd, int sockfd);
-
-/** End of TX / RX
- * @}
- */
-
-/* ************** Group: Request/Response ************** */
-/** @name Request / Response
- * APIs related to the data send/receive by URI handlers.
- * These APIs are supposed to be called only from the context of
- * a URI handler where httpd_req_t* request pointer is valid.
- * @{
- */
-
-/**
- * @brief   Override web server's receive function (by session FD)
- *
- * This function overrides the web server's receive function. This same function is
- * used to read HTTP request packets.
- *
- * @note    This API is supposed to be called either from the context of
- *          - an http session APIs where sockfd is a valid parameter
- *          - a URI handler where sockfd is obtained using httpd_req_to_sockfd()
- *
- * @param[in] hd        HTTPD instance handle
- * @param[in] sockfd    Session socket FD
- * @param[in] recv_func The receive function to be set for this session
- *
- * @return
- *  - ESP_OK : On successfully registering override
- *  - ESP_ERR_INVALID_ARG : Null arguments
- */
-esp_err_t httpd_sess_set_recv_override(httpd_handle_t hd, int sockfd, httpd_recv_func_t recv_func);
-
-/**
- * @brief   Override web server's send function (by session FD)
- *
- * This function overrides the web server's send function. This same function is
- * used to send out any response to any HTTP request.
- *
- * @note    This API is supposed to be called either from the context of
- *          - an http session APIs where sockfd is a valid parameter
- *          - a URI handler where sockfd is obtained using httpd_req_to_sockfd()
- *
- * @param[in] hd        HTTPD instance handle
- * @param[in] sockfd    Session socket FD
- * @param[in] send_func The send function to be set for this session
- *
- * @return
- *  - ESP_OK : On successfully registering override
- *  - ESP_ERR_INVALID_ARG : Null arguments
- */
-esp_err_t httpd_sess_set_send_override(httpd_handle_t hd, int sockfd, httpd_send_func_t send_func);
-
-/**
- * @brief   Override web server's pending function (by session FD)
- *
- * This function overrides the web server's pending function. This function is
- * used to test for pending bytes in a socket.
- *
- * @note    This API is supposed to be called either from the context of
- *          - an http session APIs where sockfd is a valid parameter
- *          - a URI handler where sockfd is obtained using httpd_req_to_sockfd()
- *
- * @param[in] hd           HTTPD instance handle
- * @param[in] sockfd       Session socket FD
- * @param[in] pending_func The receive function to be set for this session
- *
- * @return
- *  - ESP_OK : On successfully registering override
- *  - ESP_ERR_INVALID_ARG : Null arguments
- */
-esp_err_t httpd_sess_set_pending_override(httpd_handle_t hd, int sockfd, httpd_pending_func_t pending_func);
-
-/**
- * @brief   Get the Socket Descriptor from the HTTP request
- *
- * This API will return the socket descriptor of the session for
- * which URI handler was executed on reception of HTTP request.
- * This is useful when user wants to call functions that require
- * session socket fd, from within a URI handler, ie. :
- *      httpd_sess_get_ctx(),
- *      httpd_sess_trigger_close(),
- *      httpd_sess_update_lru_counter().
- *
- * @note    This API is supposed to be called only from the context of
- *          a URI handler where httpd_req_t* request pointer is valid.
- *
- * @param[in] r The request whose socket descriptor should be found
- *
- * @return
- *  - Socket descriptor : The socket descriptor for this request
- *  - -1 : Invalid/NULL request pointer
- */
-int httpd_req_to_sockfd(httpd_req_t *r);
-
-/**
- * @brief   API to read content data from the HTTP request
- *
- * This API will read HTTP content data from the HTTP request into
- * provided buffer. Use content_len provided in httpd_req_t structure
- * to know the length of data to be fetched. If content_len is too
- * large for the buffer then user may have to make multiple calls to
- * this function, each time fetching 'buf_len' number of bytes,
- * while the pointer to content data is incremented internally by
- * the same number.
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - If an error is returned, the URI handler must further return an error.
- *    This will ensure that the erroneous socket is closed and cleaned up by
- *    the web server.
- *  - Presently Chunked Encoding is not supported
- *
- * @param[in] r         The request being responded to
- * @param[in] buf       Pointer to a buffer that the data will be read into
- * @param[in] buf_len   Length of the buffer
- *
- * @return
- *  - Bytes : Number of bytes read into the buffer successfully
- *  - 0     : Buffer length parameter is zero / connection closed by peer
- *  - HTTPD_SOCK_ERR_INVALID  : Invalid arguments
- *  - HTTPD_SOCK_ERR_TIMEOUT  : Timeout/interrupted while calling socket recv()
- *  - HTTPD_SOCK_ERR_FAIL     : Unrecoverable error while calling socket recv()
- */
-int httpd_req_recv(httpd_req_t *r, char *buf, size_t buf_len);
-
-/**
- * @brief   Search for a field in request headers and
- *          return the string length of it's value
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - Once httpd_resp_send() API is called all request headers
- *    are purged, so request headers need be copied into separate
- *    buffers if they are required later.
- *
- * @param[in]  r        The request being responded to
- * @param[in]  field    The header field to be searched in the request
- *
- * @return
- *  - Length    : If field is found in the request URL
- *  - Zero      : Field not found / Invalid request / Null arguments
- */
-size_t httpd_req_get_hdr_value_len(httpd_req_t *r, const char *field);
-
-/**
- * @brief   Get the value string of a field from the request headers
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - Once httpd_resp_send() API is called all request headers
- *    are purged, so request headers need be copied into separate
- *    buffers if they are required later.
- *  - If output size is greater than input, then the value is truncated,
- *    accompanied by truncation error as return value.
- *  - Use httpd_req_get_hdr_value_len() to know the right buffer length
- *
- * @param[in]  r        The request being responded to
- * @param[in]  field    The field to be searched in the header
- * @param[out] val      Pointer to the buffer into which the value will be copied if the field is found
- * @param[in]  val_size Size of the user buffer "val"
- *
- * @return
- *  - ESP_OK : Field found in the request header and value string copied
- *  - ESP_ERR_NOT_FOUND          : Key not found
- *  - ESP_ERR_INVALID_ARG        : Null arguments
- *  - ESP_ERR_HTTPD_INVALID_REQ  : Invalid HTTP request pointer
- *  - ESP_ERR_HTTPD_RESULT_TRUNC : Value string truncated
- */
-esp_err_t httpd_req_get_hdr_value_str(httpd_req_t *r, const char *field, char *val, size_t val_size);
-
-/**
- * @brief   Get Query string length from the request URL
- *
- * @note    This API is supposed to be called only from the context of
- *          a URI handler where httpd_req_t* request pointer is valid
- *
- * @param[in]  r    The request being responded to
- *
- * @return
- *  - Length    : Query is found in the request URL
- *  - Zero      : Query not found / Null arguments / Invalid request
- */
-size_t httpd_req_get_url_query_len(httpd_req_t *r);
-
-/**
- * @brief   Get Query string from the request URL
- *
- * @note
- *  - Presently, the user can fetch the full URL query string, but decoding
- *    will have to be performed by the user. Request headers can be read using
- *    httpd_req_get_hdr_value_str() to know the 'Content-Type' (eg. Content-Type:
- *    application/x-www-form-urlencoded) and then the appropriate decoding
- *    algorithm needs to be applied.
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid
- *  - If output size is greater than input, then the value is truncated,
- *    accompanied by truncation error as return value
- *  - Prior to calling this function, one can use httpd_req_get_url_query_len()
- *    to know the query string length beforehand and hence allocate the buffer
- *    of right size (usually query string length + 1 for null termination)
- *    for storing the query string
- *
- * @param[in]  r         The request being responded to
- * @param[out] buf       Pointer to the buffer into which the query string will be copied (if found)
- * @param[in]  buf_len   Length of output buffer
- *
- * @return
- *  - ESP_OK : Query is found in the request URL and copied to buffer
- *  - ESP_ERR_NOT_FOUND          : Query not found
- *  - ESP_ERR_INVALID_ARG        : Null arguments
- *  - ESP_ERR_HTTPD_INVALID_REQ  : Invalid HTTP request pointer
- *  - ESP_ERR_HTTPD_RESULT_TRUNC : Query string truncated
- */
-esp_err_t httpd_req_get_url_query_str(httpd_req_t *r, char *buf, size_t buf_len);
-
-/**
- * @brief   Helper function to get a URL query tag from a query
- *          string of the type param1=val1&param2=val2
- *
- * @note
- *  - The components of URL query string (keys and values) are not URLdecoded.
- *    The user must check for 'Content-Type' field in the request headers and
- *    then depending upon the specified encoding (URLencoded or otherwise) apply
- *    the appropriate decoding algorithm.
- *  - If actual value size is greater than val_size, then the value is truncated,
- *    accompanied by truncation error as return value.
- *
- * @param[in]  qry       Pointer to query string
- * @param[in]  key       The key to be searched in the query string
- * @param[out] val       Pointer to the buffer into which the value will be copied if the key is found
- * @param[in]  val_size  Size of the user buffer "val"
- *
- * @return
- *  - ESP_OK : Key is found in the URL query string and copied to buffer
- *  - ESP_ERR_NOT_FOUND          : Key not found
- *  - ESP_ERR_INVALID_ARG        : Null arguments
- *  - ESP_ERR_HTTPD_RESULT_TRUNC : Value string truncated
- */
-esp_err_t httpd_query_key_value(const char *qry, const char *key, char *val, size_t val_size);
-
-/**
- * @brief Test if a URI matches the given wildcard template.
- *
- * Template may end with "?" to make the previous character optional (typically a slash),
- * "*" for a wildcard match, and "?*" to make the previous character optional, and if present,
- * allow anything to follow.
- *
- * Example:
- *   - * matches everything
- *   - /foo/? matches /foo and /foo/
- *   - /foo/\* (sans the backslash) matches /foo/ and /foo/bar, but not /foo or /fo
- *   - /foo/?* or /foo/\*?  (sans the backslash) matches /foo/, /foo/bar, and also /foo, but not /foox or /fo
- *
- * The special characters "?" and "*" anywhere else in the template will be taken literally.
- *
- * @param[in] uri_template   URI template (pattern)
- * @param[in] uri_to_match   URI to be matched
- * @param[in] match_upto     how many characters of the URI buffer to test
- *                          (there may be trailing query string etc.)
- *
- * @return true if a match was found
- */
-bool httpd_uri_match_wildcard(const char *uri_template, const char *uri_to_match, size_t match_upto);
-
-/**
- * @brief   API to send a complete HTTP response.
- *
- * This API will send the data as an HTTP response to the request.
- * This assumes that you have the entire response ready in a single
- * buffer. If you wish to send response in incremental chunks use
- * httpd_resp_send_chunk() instead.
- *
- * If no status code and content-type were set, by default this
- * will send 200 OK status code and content type as text/html.
- * You may call the following functions before this API to configure
- * the response headers :
- *      httpd_resp_set_status() - for setting the HTTP status string,
- *      httpd_resp_set_type()   - for setting the Content Type,
- *      httpd_resp_set_hdr()    - for appending any additional field
- *                                value entries in the response header
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - Once this API is called, the request has been responded to.
- *  - No additional data can then be sent for the request.
- *  - Once this API is called, all request headers are purged, so
- *    request headers need be copied into separate buffers if
- *    they are required later.
- *
- * @param[in] r         The request being responded to
- * @param[in] buf       Buffer from where the content is to be fetched
- * @param[in] buf_len   Length of the buffer, HTTPD_RESP_USE_STRLEN to use strlen()
- *
- * @return
- *  - ESP_OK : On successfully sending the response packet
- *  - ESP_ERR_INVALID_ARG : Null request pointer
- *  - ESP_ERR_HTTPD_RESP_HDR    : Essential headers are too large for internal buffer
- *  - ESP_ERR_HTTPD_RESP_SEND   : Error in raw send
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request
- */
-esp_err_t httpd_resp_send(httpd_req_t *r, const char *buf, ssize_t buf_len);
-
-/**
- * @brief   API to send one HTTP chunk
- *
- * This API will send the data as an HTTP response to the
- * request. This API will use chunked-encoding and send the response
- * in the form of chunks. If you have the entire response contained in
- * a single buffer, please use httpd_resp_send() instead.
- *
- * If no status code and content-type were set, by default this will
- * send 200 OK status code and content type as text/html. You may
- * call the following functions before this API to configure the
- * response headers
- *      httpd_resp_set_status() - for setting the HTTP status string,
- *      httpd_resp_set_type()   - for setting the Content Type,
- *      httpd_resp_set_hdr()    - for appending any additional field
- *                                value entries in the response header
- *
- * @note
- * - This API is supposed to be called only from the context of
- *   a URI handler where httpd_req_t* request pointer is valid.
- * - When you are finished sending all your chunks, you must call
- *   this function with buf_len as 0.
- * - Once this API is called, all request headers are purged, so
- *   request headers need be copied into separate buffers if they
- *   are required later.
- *
- * @param[in] r         The request being responded to
- * @param[in] buf       Pointer to a buffer that stores the data
- * @param[in] buf_len   Length of the buffer, HTTPD_RESP_USE_STRLEN to use strlen()
- *
- * @return
- *  - ESP_OK : On successfully sending the response packet chunk
- *  - ESP_ERR_INVALID_ARG : Null request pointer
- *  - ESP_ERR_HTTPD_RESP_HDR    : Essential headers are too large for internal buffer
- *  - ESP_ERR_HTTPD_RESP_SEND   : Error in raw send
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request pointer
- */
-esp_err_t httpd_resp_send_chunk(httpd_req_t *r, const char *buf, ssize_t buf_len);
-
-/**
- * @brief   API to send a complete string as HTTP response.
- *
- * This API simply calls http_resp_send with buffer length
- * set to string length assuming the buffer contains a null
- * terminated string
- *
- * @param[in] r         The request being responded to
- * @param[in] str       String to be sent as response body
- *
- * @return
- *  - ESP_OK : On successfully sending the response packet
- *  - ESP_ERR_INVALID_ARG : Null request pointer
- *  - ESP_ERR_HTTPD_RESP_HDR    : Essential headers are too large for internal buffer
- *  - ESP_ERR_HTTPD_RESP_SEND   : Error in raw send
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request
- */
-static inline esp_err_t httpd_resp_sendstr(httpd_req_t *r, const char *str) {
-    return httpd_resp_send(r, str, (str == NULL) ? 0 : strlen(str));
-}
-
-/**
- * @brief   API to send a string as an HTTP response chunk.
- *
- * This API simply calls http_resp_send_chunk with buffer length
- * set to string length assuming the buffer contains a null
- * terminated string
- *
- * @param[in] r    The request being responded to
- * @param[in] str  String to be sent as response body (NULL to finish response packet)
- *
- * @return
- *  - ESP_OK : On successfully sending the response packet
- *  - ESP_ERR_INVALID_ARG : Null request pointer
- *  - ESP_ERR_HTTPD_RESP_HDR    : Essential headers are too large for internal buffer
- *  - ESP_ERR_HTTPD_RESP_SEND   : Error in raw send
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request
- */
-static inline esp_err_t httpd_resp_sendstr_chunk(httpd_req_t *r, const char *str) {
-    return httpd_resp_send_chunk(r, str, (str == NULL) ? 0 : strlen(str));
-}
-
-/* Some commonly used status codes */
-#define HTTPD_200      "200 OK"                     /*!< HTTP Response 200 */
-#define HTTPD_204      "204 No Content"             /*!< HTTP Response 204 */
-#define HTTPD_207      "207 Multi-Status"           /*!< HTTP Response 207 */
-#define HTTPD_400      "400 Bad Request"            /*!< HTTP Response 400 */
-#define HTTPD_404      "404 Not Found"              /*!< HTTP Response 404 */
-#define HTTPD_408      "408 Request Timeout"        /*!< HTTP Response 408 */
-#define HTTPD_500      "500 Internal Server Error"  /*!< HTTP Response 500 */
-
-/**
- * @brief   API to set the HTTP status code
- *
- * This API sets the status of the HTTP response to the value specified.
- * By default, the '200 OK' response is sent as the response.
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - This API only sets the status to this value. The status isn't
- *    sent out until any of the send APIs is executed.
- *  - Make sure that the lifetime of the status string is valid till
- *    send function is called.
- *
- * @param[in] r         The request being responded to
- * @param[in] status    The HTTP status code of this response
- *
- * @return
- *  - ESP_OK : On success
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request pointer
- */
-esp_err_t httpd_resp_set_status(httpd_req_t *r, const char *status);
-
-/* Some commonly used content types */
-#define HTTPD_TYPE_JSON   "application/json"            /*!< HTTP Content type JSON */
-#define HTTPD_TYPE_TEXT   "text/html"                   /*!< HTTP Content type text/HTML */
-#define HTTPD_TYPE_OCTET  "application/octet-stream"    /*!< HTTP Content type octext-stream */
-
-/**
- * @brief   API to set the HTTP content type
- *
- * This API sets the 'Content Type' field of the response.
- * The default content type is 'text/html'.
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - This API only sets the content type to this value. The type
- *    isn't sent out until any of the send APIs is executed.
- *  - Make sure that the lifetime of the type string is valid till
- *    send function is called.
- *
- * @param[in] r     The request being responded to
- * @param[in] type  The Content Type of the response
- *
- * @return
- *  - ESP_OK   : On success
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request pointer
- */
-esp_err_t httpd_resp_set_type(httpd_req_t *r, const char *type);
-
-/**
- * @brief   API to append any additional headers
- *
- * This API sets any additional header fields that need to be sent in the response.
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - The header isn't sent out until any of the send APIs is executed.
- *  - The maximum allowed number of additional headers is limited to
- *    value of max_resp_headers in config structure.
- *  - Make sure that the lifetime of the field value strings are valid till
- *    send function is called.
- *
- * @param[in] r     The request being responded to
- * @param[in] field The field name of the HTTP header
- * @param[in] value The value of this HTTP header
- *
- * @return
- *  - ESP_OK : On successfully appending new header
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_HTTPD_RESP_HDR    : Total additional headers exceed max allowed
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request pointer
- */
-esp_err_t httpd_resp_set_hdr(httpd_req_t *r, const char *field, const char *value);
-
-/**
- * @brief   For sending out error code in response to HTTP request.
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - Once this API is called, all request headers are purged, so
- *    request headers need be copied into separate buffers if
- *    they are required later.
- *  - If you wish to send additional data in the body of the
- *    response, please use the lower-level functions directly.
- *
- * @param[in] req     Pointer to the HTTP request for which the response needs to be sent
- * @param[in] error   Error type to send
- * @param[in] msg     Error message string (pass NULL for default message)
- *
- * @return
- *  - ESP_OK : On successfully sending the response packet
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_HTTPD_RESP_SEND   : Error in raw send
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request pointer
- */
-esp_err_t httpd_resp_send_err(httpd_req_t *req, httpd_err_code_t error, const char *msg);
-
-/**
- * @brief   Helper function for HTTP 404
- *
- * Send HTTP 404 message. If you wish to send additional data in the body of the
- * response, please use the lower-level functions directly.
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - Once this API is called, all request headers are purged, so
- *    request headers need be copied into separate buffers if
- *    they are required later.
- *
- * @param[in] r The request being responded to
- *
- * @return
- *  - ESP_OK : On successfully sending the response packet
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_HTTPD_RESP_SEND   : Error in raw send
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request pointer
- */
-static inline esp_err_t httpd_resp_send_404(httpd_req_t *r) {
-    return httpd_resp_send_err(r, HTTPD_404_NOT_FOUND, NULL);
-}
-
-/**
- * @brief   Helper function for HTTP 408
- *
- * Send HTTP 408 message. If you wish to send additional data in the body of the
- * response, please use the lower-level functions directly.
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - Once this API is called, all request headers are purged, so
- *    request headers need be copied into separate buffers if
- *    they are required later.
- *
- * @param[in] r The request being responded to
- *
- * @return
- *  - ESP_OK : On successfully sending the response packet
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_HTTPD_RESP_SEND   : Error in raw send
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request pointer
- */
-static inline esp_err_t httpd_resp_send_408(httpd_req_t *r) {
-    return httpd_resp_send_err(r, HTTPD_408_REQ_TIMEOUT, NULL);
-}
-
-/**
- * @brief   Helper function for HTTP 500
- *
- * Send HTTP 500 message. If you wish to send additional data in the body of the
- * response, please use the lower-level functions directly.
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - Once this API is called, all request headers are purged, so
- *    request headers need be copied into separate buffers if
- *    they are required later.
- *
- * @param[in] r The request being responded to
- *
- * @return
- *  - ESP_OK : On successfully sending the response packet
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_HTTPD_RESP_SEND   : Error in raw send
- *  - ESP_ERR_HTTPD_INVALID_REQ : Invalid request pointer
- */
-static inline esp_err_t httpd_resp_send_500(httpd_req_t *r) {
-    return httpd_resp_send_err(r, HTTPD_500_INTERNAL_SERVER_ERROR, NULL);
-}
-
-/**
- * @brief   Raw HTTP send
- *
- * Call this API if you wish to construct your custom response packet.
- * When using this, all essential header, eg. HTTP version, Status Code,
- * Content Type and Length, Encoding, etc. will have to be constructed
- * manually, and HTTP delimeters (CRLF) will need to be placed correctly
- * for separating sub-sections of the HTTP response packet.
- *
- * If the send override function is set, this API will end up
- * calling that function eventually to send data out.
- *
- * @note
- *  - This API is supposed to be called only from the context of
- *    a URI handler where httpd_req_t* request pointer is valid.
- *  - Unless the response has the correct HTTP structure (which the
- *    user must now ensure) it is not guaranteed that it will be
- *    recognized by the client. For most cases, you wouldn't have
- *    to call this API, but you would rather use either of :
- *          httpd_resp_send(),
- *          httpd_resp_send_chunk()
- *
- * @param[in] r         The request being responded to
- * @param[in] buf       Buffer from where the fully constructed packet is to be read
- * @param[in] buf_len   Length of the buffer
- *
- * @return
- *  - Bytes : Number of bytes that were sent successfully
- *  - HTTPD_SOCK_ERR_INVALID  : Invalid arguments
- *  - HTTPD_SOCK_ERR_TIMEOUT  : Timeout/interrupted while calling socket send()
- *  - HTTPD_SOCK_ERR_FAIL     : Unrecoverable error while calling socket send()
- */
-int httpd_send(httpd_req_t *r, const char *buf, size_t buf_len);
-
-/** End of Request / Response
- * @}
- */
-
-/* ************** Group: Session ************** */
-/** @name Session
- * Functions for controlling sessions and accessing context data
- * @{
- */
-
-/**
- * @brief   Get session context from socket descriptor
- *
- * Typically if a session context is created, it is available to URI handlers
- * through the httpd_req_t structure. But, there are cases where the web
- * server's send/receive functions may require the context (for example, for
- * accessing keying information etc). Since the send/receive function only have
- * the socket descriptor at their disposal, this API provides them with a way to
- * retrieve the session context.
- *
- * @param[in] handle    Handle to server returned by httpd_start
- * @param[in] sockfd    The socket descriptor for which the context should be extracted.
- *
- * @return
- *  - void* : Pointer to the context associated with this session
- *  - NULL  : Empty context / Invalid handle / Invalid socket fd
- */
-void *httpd_sess_get_ctx(httpd_handle_t handle, int sockfd);
-
-/**
- * @brief   Set session context by socket descriptor
- *
- * @param[in] handle    Handle to server returned by httpd_start
- * @param[in] sockfd    The socket descriptor for which the context should be extracted.
- * @param[in] ctx       Context object to assign to the session
- * @param[in] free_fn   Function that should be called to free the context
- */
-void httpd_sess_set_ctx(httpd_handle_t handle, int sockfd, void *ctx, httpd_free_ctx_fn_t free_fn);
-
-/**
- * @brief   Get session 'transport' context by socket descriptor
- * @see     httpd_sess_get_ctx()
- *
- * This context is used by the send/receive functions, for example to manage SSL context.
- *
- * @param[in] handle    Handle to server returned by httpd_start
- * @param[in] sockfd    The socket descriptor for which the context should be extracted.
- * @return
- *  - void* : Pointer to the transport context associated with this session
- *  - NULL  : Empty context / Invalid handle / Invalid socket fd
- */
-void *httpd_sess_get_transport_ctx(httpd_handle_t handle, int sockfd);
-
-/**
- * @brief   Set session 'transport' context by socket descriptor
- * @see     httpd_sess_set_ctx()
- *
- * @param[in] handle    Handle to server returned by httpd_start
- * @param[in] sockfd    The socket descriptor for which the context should be extracted.
- * @param[in] ctx       Transport context object to assign to the session
- * @param[in] free_fn   Function that should be called to free the transport context
- */
-void httpd_sess_set_transport_ctx(httpd_handle_t handle, int sockfd, void *ctx, httpd_free_ctx_fn_t free_fn);
-
-/**
- * @brief   Get HTTPD global user context (it was set in the server config struct)
- *
- * @param[in] handle    Handle to server returned by httpd_start
- * @return global user context
- */
-void *httpd_get_global_user_ctx(httpd_handle_t handle);
-
-/**
- * @brief   Get HTTPD global transport context (it was set in the server config struct)
- *
- * @param[in] handle    Handle to server returned by httpd_start
- * @return global transport context
- */
-void *httpd_get_global_transport_ctx(httpd_handle_t handle);
-
-/**
- * @brief   Trigger an httpd session close externally
- *
- * @note    Calling this API is only required in special circumstances wherein
- *          some application requires to close an httpd client session asynchronously.
- *
- * @param[in] handle    Handle to server returned by httpd_start
- * @param[in] sockfd    The socket descriptor of the session to be closed
- *
- * @return
- *  - ESP_OK    : On successfully initiating closure
- *  - ESP_FAIL  : Failure to queue work
- *  - ESP_ERR_NOT_FOUND   : Socket fd not found
- *  - ESP_ERR_INVALID_ARG : Null arguments
- */
-esp_err_t httpd_sess_trigger_close(httpd_handle_t handle, int sockfd);
-
-/**
- * @brief   Update LRU counter for a given socket
- *
- * LRU Counters are internally associated with each session to monitor
- * how recently a session exchanged traffic. When LRU purge is enabled,
- * if a client is requesting for connection but maximum number of
- * sockets/sessions is reached, then the session having the earliest
- * LRU counter is closed automatically.
- *
- * Updating the LRU counter manually prevents the socket from being purged
- * due to the Least Recently Used (LRU) logic, even though it might not
- * have received traffic for some time. This is useful when all open
- * sockets/session are frequently exchanging traffic but the user specifically
- * wants one of the sessions to be kept open, irrespective of when it last
- * exchanged a packet.
- *
- * @note    Calling this API is only necessary if the LRU Purge Enable option
- *          is enabled.
- *
- * @param[in] handle    Handle to server returned by httpd_start
- * @param[in] sockfd    The socket descriptor of the session for which LRU counter
- *                      is to be updated
- *
- * @return
- *  - ESP_OK : Socket found and LRU counter updated
- *  - ESP_ERR_NOT_FOUND   : Socket not found
- *  - ESP_ERR_INVALID_ARG : Null arguments
- */
-esp_err_t httpd_sess_update_lru_counter(httpd_handle_t handle, int sockfd);
-
-/** End of Session
- * @}
- */
-
-/* ************** Group: Work Queue ************** */
-/** @name Work Queue
- * APIs related to the HTTPD Work Queue
- * @{
- */
-
-/**
- * @brief   Prototype of the HTTPD work function
- *          Please refer to httpd_queue_work() for more details.
- * @param[in] arg   The arguments for this work function
- */
-typedef void (*httpd_work_fn_t)(void *arg);
-
-/**
- * @brief   Queue execution of a function in HTTPD's context
- *
- * This API queues a work function for asynchronous execution
- *
- * @note    Some protocols require that the web server generate some asynchronous data
- *          and send it to the persistently opened connection. This facility is for use
- *          by such protocols.
- *
- * @param[in] handle    Handle to server returned by httpd_start
- * @param[in] work      Pointer to the function to be executed in the HTTPD's context
- * @param[in] arg       Pointer to the arguments that should be passed to this function
- *
- * @return
- *  - ESP_OK   : On successfully queueing the work
- *  - ESP_FAIL : Failure in ctrl socket
- *  - ESP_ERR_INVALID_ARG : Null arguments
- */
-esp_err_t httpd_queue_work(httpd_handle_t handle, httpd_work_fn_t work, void *arg);
-
-/** End of Group Work Queue
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! _ESP_HTTP_SERVER_H_ */
diff --git a/tools/sdk/include/esp_http_server/http_server.h b/tools/sdk/include/esp_http_server/http_server.h
deleted file mode 100644
index 56f73c5b74c..00000000000
--- a/tools/sdk/include/esp_http_server/http_server.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#warning http_server.h has been renamed to esp_http_server.h, please update include directives
-#include "esp_http_server.h"
diff --git a/tools/sdk/include/esp_https_ota/esp_https_ota.h b/tools/sdk/include/esp_https_ota/esp_https_ota.h
deleted file mode 100644
index fd69f27f894..00000000000
--- a/tools/sdk/include/esp_https_ota/esp_https_ota.h
+++ /dev/null
@@ -1,181 +0,0 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <esp_http_client.h>
-#include <bootloader_common.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef void *esp_https_ota_handle_t;
-
-/**
- * @brief ESP HTTPS OTA configuration
- */
-typedef struct {
-    const esp_http_client_config_t *http_config;   /*!< ESP HTTP client configuration */
-} esp_https_ota_config_t;
-
-#define ESP_ERR_HTTPS_OTA_BASE            (0x9000)
-#define ESP_ERR_HTTPS_OTA_IN_PROGRESS     (ESP_ERR_HTTPS_OTA_BASE + 1)  /* OTA operation in progress */
-
-/**
- * @brief    HTTPS OTA Firmware upgrade.
- *
- * This function allocates HTTPS OTA Firmware upgrade context, establishes HTTPS connection, 
- * reads image data from HTTP stream and writes it to OTA partition and 
- * finishes HTTPS OTA Firmware upgrade operation.
- * This API supports URL redirection, but if CA cert of URLs differ then it
- * should be appended to `cert_pem` member of `config`.
- * 
- * @param[in]  config       pointer to esp_http_client_config_t structure.
- *
- * @note     This API handles the entire OTA operation, so if this API is being used
- *           then no other APIs from `esp_https_ota` component should be called.
- *           If more information and control is needed during the HTTPS OTA process,
- *           then one can use `esp_https_ota_begin` and subsequent APIs. If this API returns
- *           successfully, esp_restart() must be called to boot from the new firmware image.
- *
- * @return
- *    - ESP_OK: OTA data updated, next reboot will use specified partition.
- *    - ESP_FAIL: For generic failure.
- *    - ESP_ERR_INVALID_ARG: Invalid argument
- *    - ESP_ERR_OTA_VALIDATE_FAILED: Invalid app image
- *    - ESP_ERR_NO_MEM: Cannot allocate memory for OTA operation.
- *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
- *    - For other return codes, refer OTA documentation in esp-idf's app_update component.
- */
-esp_err_t esp_https_ota(const esp_http_client_config_t *config);
-
-/**
- * @brief    Start HTTPS OTA Firmware upgrade
- *
- * This function initializes ESP HTTPS OTA context and establishes HTTPS connection.
- * This function must be invoked first. If this function returns successfully, then `esp_https_ota_perform` should be
- * called to continue with the OTA process and there should be a call to `esp_https_ota_finish` on
- * completion of OTA operation or on failure in subsequent operations.
- * This API supports URL redirection, but if CA cert of URLs differ then it
- * should be appended to `cert_pem` member of `http_config`, which is a part of `ota_config`.
- * In case of error, this API explicitly sets `handle` to NULL.
- *
- * @param[in]   ota_config       pointer to esp_https_ota_config_t structure
- * @param[out]  handle           pointer to an allocated data of type `esp_https_ota_handle_t`
- *                               which will be initialised in this function
- *
- * @note     This API is blocking, so setting `is_async` member of `http_config` structure will
- *           result in an error.
- *
- * @return
- *    - ESP_OK: HTTPS OTA Firmware upgrade context initialised and HTTPS connection established
- *    - ESP_FAIL: For generic failure.
- *    - ESP_ERR_INVALID_ARG: Invalid argument (missing/incorrect config, certificate, etc.)
- *    - For other return codes, refer documentation in app_update component and esp_http_client 
- *      component in esp-idf.
- */
-esp_err_t esp_https_ota_begin(esp_https_ota_config_t *ota_config, esp_https_ota_handle_t *handle);
-
-/**
- * @brief    Read image data from HTTP stream and write it to OTA partition 
- *
- * This function reads image data from HTTP stream and writes it to OTA partition. This function 
- * must be called only if esp_https_ota_begin() returns successfully.
- * This function must be called in a loop since it returns after every HTTP read operation thus 
- * giving you the flexibility to stop OTA operation midway.
- * 
- * @param[in]  https_ota_handle  pointer to esp_https_ota_handle_t structure
- *
- * @return
- *    - ESP_ERR_HTTPS_OTA_IN_PROGRESS: OTA update is in progress, call this API again to continue.
- *    - ESP_OK: OTA update was successful
- *    - ESP_FAIL: OTA update failed
- *    - ESP_ERR_INVALID_ARG: Invalid argument
- *    - ESP_ERR_OTA_VALIDATE_FAILED: Invalid app image
- *    - ESP_ERR_NO_MEM: Cannot allocate memory for OTA operation.
- *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
- *    - For other return codes, refer OTA documentation in esp-idf's app_update component.
- */
-esp_err_t esp_https_ota_perform(esp_https_ota_handle_t https_ota_handle);
-
-/**
- * @brief   Checks if complete data was received or not
- *
- * @note    This API can be called just before esp_https_ota_finish() to validate if the complete image was indeed received.
- *
- * @param[in]   https_ota_handle pointer to esp_https_ota_handle_t structure
- *
- * @return
- *    - false
- *    - true
- */
-bool esp_https_ota_is_complete_data_received(esp_https_ota_handle_t https_ota_handle);
-
-/**
- * @brief    Clean-up HTTPS OTA Firmware upgrade and close HTTPS connection
- *
- * This function closes the HTTP connection and frees the ESP HTTPS OTA context.
- * This function switches the boot partition to the OTA partition containing the
- * new firmware image.
- *
- * @note     If this API returns successfully, esp_restart() must be called to
- *           boot from the new firmware image
- *
- * @param[in]  https_ota_handle   pointer to esp_https_ota_handle_t structure
- *
- * @return
- *    - ESP_OK: Clean-up successful
- *    - ESP_ERR_INVALID_STATE
- *    - ESP_ERR_INVALID_ARG: Invalid argument
- *    - ESP_ERR_OTA_VALIDATE_FAILED: Invalid app image
- */
-esp_err_t esp_https_ota_finish(esp_https_ota_handle_t https_ota_handle);
-
-
-/**
- * @brief   Reads app description from image header. The app description provides information
- *          like the "Firmware version" of the image.
- * 
- * @note    This API can be called only after esp_https_ota_begin() and before esp_https_ota_perform().
- *          Calling this API is not mandatory.
- *
- * @param[in]   https_ota_handle   pointer to esp_https_ota_handle_t structure
- * @param[out]  new_app_info       pointer to an allocated esp_app_desc_t structure
- * 
- * @return 
- *    - ESP_ERR_INVALID_ARG: Invalid arguments
- *    - ESP_FAIL: Failed to read image descriptor
- *    - ESP_OK: Successfully read image descriptor
- */
-esp_err_t esp_https_ota_get_img_desc(esp_https_ota_handle_t https_ota_handle, esp_app_desc_t *new_app_info);
-
-
-/*
-* @brief  This function returns OTA image data read so far.
-*
-* @note   This API should be called only if `esp_https_ota_perform()` has been called atleast once or
-*         if `esp_https_ota_get_img_desc` has been called before.
-*
-* @param[in]   https_ota_handle   pointer to esp_https_ota_handle_t structure
-*
-* @return
-*    - -1    On failure
-*    - total bytes read so far
-*/
-int esp_https_ota_get_image_len_read(esp_https_ota_handle_t https_ota_handle);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/esp_https_server/esp_https_server.h b/tools/sdk/include/esp_https_server/esp_https_server.h
deleted file mode 100644
index e69a5a294e9..00000000000
--- a/tools/sdk/include/esp_https_server/esp_https_server.h
+++ /dev/null
@@ -1,130 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_HTTPS_SERVER_H_
-#define _ESP_HTTPS_SERVER_H_
-
-#include <stdbool.h>
-#include "esp_err.h"
-#include "esp_http_server.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    HTTPD_SSL_TRANSPORT_SECURE,      // SSL Enabled
-    HTTPD_SSL_TRANSPORT_INSECURE     // SSL disabled
-} httpd_ssl_transport_mode_t;
-
-/**
- * HTTPS server config struct
- *
- * Please use HTTPD_SSL_CONFIG_DEFAULT() to initialize it.
- */
-struct httpd_ssl_config {
-    /**
-     * Underlying HTTPD server config
-     *
-     * Parameters like task stack size and priority can be adjusted here.
-     */
-    httpd_config_t httpd;
-
-    /** CA certificate */
-    const uint8_t *cacert_pem;
-
-    /** CA certificate byte length */
-    size_t cacert_len;
-
-    /** Private key */
-    const uint8_t *prvtkey_pem;
-
-    /** Private key byte length */
-    size_t prvtkey_len;
-
-    /** Transport Mode (default secure) */
-    httpd_ssl_transport_mode_t transport_mode;
-
-    /** Port used when transport mode is secure (default 443) */
-    uint16_t port_secure;
-
-    /** Port used when transport mode is insecure (default 80) */
-    uint16_t port_insecure;
-};
-
-typedef struct httpd_ssl_config httpd_ssl_config_t;
-
-/**
- * Default config struct init
- *
- * (http_server default config had to be copied for customization)
- *
- * Notes:
- * - port is set when starting the server, according to 'transport_mode'
- * - one socket uses ~ 40kB RAM with SSL, we reduce the default socket count to 4
- * - SSL sockets are usually long-lived, closing LRU prevents pool exhaustion DOS
- * - Stack size may need adjustments depending on the user application
- */
-#define HTTPD_SSL_CONFIG_DEFAULT() {              \
-    .httpd = {                                    \
-        .task_priority      = tskIDLE_PRIORITY+5, \
-        .stack_size         = 10240,              \
-        .server_port        = 0,                  \
-        .ctrl_port          = 32768,              \
-        .max_open_sockets   = 4,                  \
-        .max_uri_handlers   = 8,                  \
-        .max_resp_headers   = 8,                  \
-        .backlog_conn       = 5,                  \
-        .lru_purge_enable   = true,               \
-        .recv_wait_timeout  = 5,                  \
-        .send_wait_timeout  = 5,                  \
-        .global_user_ctx = NULL,                  \
-        .global_user_ctx_free_fn = NULL,          \
-        .global_transport_ctx = NULL,             \
-        .global_transport_ctx_free_fn = NULL,     \
-        .open_fn = NULL,                          \
-        .close_fn = NULL,                         \
-        .uri_match_fn = NULL                      \
-    },                                            \
-    .cacert_pem = NULL,                           \
-    .cacert_len = 0,                              \
-    .prvtkey_pem = NULL,                          \
-    .prvtkey_len = 0,                             \
-    .transport_mode = HTTPD_SSL_TRANSPORT_SECURE, \
-    .port_secure = 443,                           \
-    .port_insecure = 80,                          \
-}
-
-/**
- * Create a SSL capable HTTP server (secure mode may be disabled in config)
- *
- * @param[in,out] config - server config, must not be const. Does not have to stay valid after
- *                         calling this function.
- * @param[out] handle - storage for the server handle, must be a valid pointer
- * @return success
- */
-esp_err_t httpd_ssl_start(httpd_handle_t *handle, httpd_ssl_config_t *config);
-
-/**
- * Stop the server. Blocks until the server is shut down.
- *
- * @param[in] handle
- */
-void httpd_ssl_stop(httpd_handle_t handle);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _ESP_HTTPS_SERVER_H_
diff --git a/tools/sdk/include/esp_ringbuf/freertos/ringbuf.h b/tools/sdk/include/esp_ringbuf/freertos/ringbuf.h
deleted file mode 100644
index de8a3690952..00000000000
--- a/tools/sdk/include/esp_ringbuf/freertos/ringbuf.h
+++ /dev/null
@@ -1,415 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef FREERTOS_RINGBUF_H
-#define FREERTOS_RINGBUF_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h" must appear in source files before "include ringbuf.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <freertos/queue.h>
-
-/**
- * Type by which ring buffers are referenced. For example, a call to xRingbufferCreate()
- * returns a RingbufHandle_t variable that can then be used as a parameter to
- * xRingbufferSend(), xRingbufferReceive(), etc.
- */
-typedef void * RingbufHandle_t;
-
-typedef enum {
-	/**
-	 * No-split buffers will only store an item in contiguous memory and will
-	 * never split an item. Each item requires an 8 byte overhead for a header
-	 * and will always internally occupy a 32-bit aligned size of space.
-	 */
-	RINGBUF_TYPE_NOSPLIT = 0,
-	/**
-	 * Allow-split buffers will split an item into two parts if necessary in
-	 * order to store it. Each item requires an 8 byte overhead for a header,
-	 * splitting incurs an extra header. Each item will always internally occupy
-	 * a 32-bit aligned size of space.
-	 */
-	RINGBUF_TYPE_ALLOWSPLIT,
-	/**
-	 * Byte buffers store data as a sequence of bytes and do not maintain separate
-	 * items, therefore byte buffers have no overhead. All data is stored as a
-	 * sequence of byte and any number of bytes can be sent or retrieved each
-	 * time.
-	 */
-	RINGBUF_TYPE_BYTEBUF
-} ringbuf_type_t;
-
-/**
- * @brief       Create a ring buffer
- *
- * @param[in]   xBufferSize Size of the buffer in bytes. Note that items require
- *              space for overhead in no-split/allow-split buffers
- * @param[in]   xBufferType Type of ring buffer, see documentation.
- *
- * @note    xBufferSize of no-split/allow-split buffers will be rounded up to the nearest 32-bit aligned size.
- *
- * @return  A handle to the created ring buffer, or NULL in case of error.
- */
-RingbufHandle_t xRingbufferCreate(size_t xBufferSize, ringbuf_type_t xBufferType);
-
-/**
- * @brief Create a ring buffer of type RINGBUF_TYPE_NOSPLIT for a fixed item_size
- *
- * This API is similar to xRingbufferCreate(), but it will internally allocate
- * additional space for the headers.
- *
- * @param[in]   xItemSize   Size of each item to be put into the ring buffer
- * @param[in]   xItemNum    Maximum number of items the buffer needs to hold simultaneously
- *
- * @return  A RingbufHandle_t handle to the created ring buffer, or NULL in case of error.
- */
-RingbufHandle_t xRingbufferCreateNoSplit(size_t xItemSize, size_t xItemNum);
-
-/**
- * @brief       Insert an item into the ring buffer
- *
- * Attempt to insert an item into the ring buffer. This function will block until
- * enough free space is available or until it timesout.
- *
- * @param[in]   xRingbuffer     Ring buffer to insert the item into
- * @param[in]   pvItem          Pointer to data to insert. NULL is allowed if xItemSize is 0.
- * @param[in]   xItemSize       Size of data to insert.
- * @param[in]   xTicksToWait    Ticks to wait for room in the ring buffer.
- *
- * @note    For no-split/allow-split ring buffers, the actual size of memory that
- *          the item will occupy will be rounded up to the nearest 32-bit aligned
- *          size. This is done to ensure all items are always stored in 32-bit
- *          aligned fashion.
- *
- * @return
- *      - pdTRUE if succeeded
- *      - pdFALSE on time-out or when the data is larger than the maximum permissible size of the buffer
- */
-BaseType_t xRingbufferSend(RingbufHandle_t xRingbuffer, const void *pvItem, size_t xItemSize, TickType_t xTicksToWait);
-
-/**
- * @brief       Insert an item into the ring buffer in an ISR
- *
- * Attempt to insert an item into the ring buffer from an ISR. This function
- * will return immediately if there is insufficient free space in the buffer.
- *
- * @param[in]   xRingbuffer Ring buffer to insert the item into
- * @param[in]   pvItem      Pointer to data to insert. NULL is allowed if xItemSize is 0.
- * @param[in]   xItemSize   Size of data to insert.
- * @param[out]  pxHigherPriorityTaskWoken   Value pointed to will be set to pdTRUE if the function woke up a higher priority task.
- *
- * @note    For no-split/allow-split ring buffers, the actual size of memory that
- *          the item will occupy will be rounded up to the nearest 32-bit aligned
- *          size. This is done to ensure all items are always stored in 32-bit
- *          aligned fashion.
- *
- * @return
- *      - pdTRUE if succeeded
- *      - pdFALSE when the ring buffer does not have space.
- */
-BaseType_t xRingbufferSendFromISR(RingbufHandle_t xRingbuffer, const void *pvItem, size_t xItemSize, BaseType_t *pxHigherPriorityTaskWoken);
-
-/**
- * @brief   Retrieve an item from the ring buffer
- *
- * Attempt to retrieve an item from the ring buffer. This function will block
- * until an item is available or until it timesout.
- *
- * @param[in]   xRingbuffer     Ring buffer to retrieve the item from
- * @param[out]  pxItemSize      Pointer to a variable to which the size of the retrieved item will be written.
- * @param[in]   xTicksToWait    Ticks to wait for items in the ring buffer.
- *
- * @note    A call to vRingbufferReturnItem() is required after this to free the item retrieved.
- *
- * @return
- *      - Pointer to the retrieved item on success; *pxItemSize filled with the length of the item.
- *      - NULL on timeout, *pxItemSize is untouched in that case.
- */
-void *xRingbufferReceive(RingbufHandle_t xRingbuffer, size_t *pxItemSize, TickType_t xTicksToWait);
-
-/**
- * @brief   Retrieve an item from the ring buffer in an ISR
- *
- * Attempt to retrieve an item from the ring buffer. This function returns immediately
- * if there are no items available for retrieval
- *
- * @param[in]   xRingbuffer     Ring buffer to retrieve the item from
- * @param[out]  pxItemSize      Pointer to a variable to which the size of the
- *                              retrieved item will be written.
- *
- * @note    A call to vRingbufferReturnItemFromISR() is required after this to free the item retrieved.
- * @note    Byte buffers do not allow multiple retrievals before returning an item
- *
- * @return
- *      - Pointer to the retrieved item on success; *pxItemSize filled with the length of the item.
- *      - NULL when the ring buffer is empty, *pxItemSize is untouched in that case.
- */
-void *xRingbufferReceiveFromISR(RingbufHandle_t xRingbuffer, size_t *pxItemSize);
-
-/**
- * @brief   Retrieve a split item from an allow-split ring buffer
- *
- * Attempt to retrieve a split item from an allow-split ring buffer. If the item
- * is not split, only a single item is retried. If the item is split, both parts
- * will be retrieved. This function will block until an item is available or
- * until it timesout.
- *
- * @param[in]   xRingbuffer     Ring buffer to retrieve the item from
- * @param[out]  ppvHeadItem     Double pointer to first part (set to NULL if no items were retrieved)
- * @param[out]  ppvTailItem     Double pointer to second part (set to NULL if item is not split)
- * @param[out]  pxHeadItemSize  Pointer to size of first part (unmodified if no items were retrieved)
- * @param[out]  pxTailItemSize  Pointer to size of second part (unmodified if item is not split)
- * @param[in]   xTicksToWait    Ticks to wait for items in the ring buffer.
- *
- * @note    Call(s) to vRingbufferReturnItem() is required after this to free up the item(s) retrieved.
- * @note    This function should only be called on allow-split buffers
- *
- * @return
- *      - pdTRUE if an item (split or unsplit) was retrieved
- *      - pdFALSE when no item was retrieved
- */
-BaseType_t xRingbufferReceiveSplit(RingbufHandle_t xRingbuffer, void **ppvHeadItem, void **ppvTailItem, size_t *pxHeadItemSize, size_t *pxTailItemSize, TickType_t xTicksToWait);
-
-/**
- * @brief   Retrieve a split item from an allow-split ring buffer in an ISR
- *
- * Attempt to retrieve a split item from an allow-split ring buffer. If the item
- * is not split, only a single item is retried. If the item is split, both parts
- * will be retrieved. This function returns immediately if there are no items
- * available for retrieval
- *
- * @param[in]   xRingbuffer     Ring buffer to retrieve the item from
- * @param[out]  ppvHeadItem     Double pointer to first part (set to NULL if no items were retrieved)
- * @param[out]  ppvTailItem     Double pointer to second part (set to NULL if item is not split)
- * @param[out]  pxHeadItemSize  Pointer to size of first part (unmodified if no items were retrieved)
- * @param[out]  pxTailItemSize  Pointer to size of second part (unmodified if item is not split)
- *
- * @note    Calls to vRingbufferReturnItemFromISR() is required after this to free up the item(s) retrieved.
- * @note    This function should only be called on allow-split buffers
- *
- * @return
- *      - pdTRUE if an item (split or unsplit) was retrieved
- *      - pdFALSE when no item was retrieved
- */
-BaseType_t xRingbufferReceiveSplitFromISR(RingbufHandle_t xRingbuffer, void **ppvHeadItem, void **ppvTailItem, size_t *pxHeadItemSize, size_t *pxTailItemSize);
-
-/**
- * @brief   Retrieve bytes from a byte buffer, specifying the maximum amount of bytes to retrieve
- *
- * Attempt to retrieve data from a byte buffer whilst specifying a maximum number
- * of bytes to retrieve. This function will block until there is data available
- * for retrieval or until it timesout.
- *
- * @param[in]   xRingbuffer     Ring buffer to retrieve the item from
- * @param[out]  pxItemSize      Pointer to a variable to which the size of the retrieved item will be written.
- * @param[in]   xTicksToWait    Ticks to wait for items in the ring buffer.
- * @param[in]   xMaxSize        Maximum number of bytes to return.
- *
- * @note    A call to vRingbufferReturnItem() is required after this to free up the data retrieved.
- * @note    This function should only be called on byte buffers
- * @note    Byte buffers do not allow multiple retrievals before returning an item
- *
- * @return
- *      - Pointer to the retrieved item on success; *pxItemSize filled with
- *        the length of the item.
- *      - NULL on timeout, *pxItemSize is untouched in that case.
- */
-void *xRingbufferReceiveUpTo(RingbufHandle_t xRingbuffer, size_t *pxItemSize, TickType_t xTicksToWait, size_t xMaxSize);
-
-/**
- * @brief   Retrieve bytes from a byte buffer, specifying the maximum amount of
- *          bytes to retrieve. Call this from an ISR.
- *
- * Attempt to retrieve bytes from a byte buffer whilst specifying a maximum number
- * of bytes to retrieve. This function will return immediately if there is no data
- * available for retrieval.
- *
- * @param[in]   xRingbuffer Ring buffer to retrieve the item from
- * @param[out]  pxItemSize  Pointer to a variable to which the size of the retrieved item will be written.
- * @param[in]   xMaxSize    Maximum number of bytes to return.
- *
- * @note    A call to vRingbufferReturnItemFromISR() is required after this to free up the data received.
- * @note    This function should only be called on byte buffers
- * @note    Byte buffers do not allow multiple retrievals before returning an item
- *
- * @return
- *      - Pointer to the retrieved item on success; *pxItemSize filled with
- *        the length of the item.
- *      - NULL when the ring buffer is empty, *pxItemSize is untouched in that case.
- */
-void *xRingbufferReceiveUpToFromISR(RingbufHandle_t xRingbuffer, size_t *pxItemSize, size_t xMaxSize);
-
-/**
- * @brief   Return a previously-retrieved item to the ring buffer
- *
- * @param[in]   xRingbuffer Ring buffer the item was retrieved from
- * @param[in]   pvItem      Item that was received earlier
- *
- * @note    If a split item is retrieved, both parts should be returned by calling this function twice
- */
-void vRingbufferReturnItem(RingbufHandle_t xRingbuffer, void *pvItem);
-
-/**
- * @brief   Return a previously-retrieved item to the ring buffer from an ISR
- *
- * @param[in]   xRingbuffer Ring buffer the item was retrieved from
- * @param[in]   pvItem      Item that was received earlier
- * @param[out]  pxHigherPriorityTaskWoken   Value pointed to will be set to pdTRUE
- *                                          if the function woke up a higher priority task.
- *
- * @note    If a split item is retrieved, both parts should be returned by calling this function twice
- */
-void vRingbufferReturnItemFromISR(RingbufHandle_t xRingbuffer, void *pvItem, BaseType_t *pxHigherPriorityTaskWoken);
-
-/**
- * @brief   Delete a ring buffer
- *
- * @param[in]   xRingbuffer     Ring buffer to delete
- */
-void vRingbufferDelete(RingbufHandle_t xRingbuffer);
-
-/**
- * @brief   Get maximum size of an item that can be placed in the ring buffer
- *
- * This function returns the maximum size an item can have if it was placed in
- * an empty ring buffer.
- *
- * @param[in]   xRingbuffer     Ring buffer to query
- *
- * @return  Maximum size, in bytes, of an item that can be placed in a ring buffer.
- */
-size_t xRingbufferGetMaxItemSize(RingbufHandle_t xRingbuffer);
-
-/**
- * @brief   Get current free size available for an item/data in the buffer
- *
- * This gives the real time free space available for an item/data in the ring
- * buffer. This represents the maximum size an item/data can have if it was
- * currently sent to the ring buffer.
- *
- * @warning This API is not thread safe. So, if multiple threads are accessing
- *          the same ring buffer, it is the application's responsibility to
- *          ensure atomic access to this API and the subsequent Send
- *
- * @param[in]   xRingbuffer     Ring buffer to query
- *
- * @return  Current free size, in bytes, available for an entry
- */
-size_t xRingbufferGetCurFreeSize(RingbufHandle_t xRingbuffer);
-
-/**
- * @brief   Add the ring buffer's read semaphore to a queue set.
- *
- * The ring buffer's read semaphore indicates that data has been written
- * to the ring buffer. This function adds the ring buffer's read semaphore to
- * a queue set.
- *
- * @param[in]   xRingbuffer     Ring buffer to add to the queue set
- * @param[in]   xQueueSet       Queue set to add the ring buffer's read semaphore to
- *
- * @return
- *      - pdTRUE on success, pdFALSE otherwise
- */
-BaseType_t xRingbufferAddToQueueSetRead(RingbufHandle_t xRingbuffer, QueueSetHandle_t xQueueSet);
-
-
-/**
- * @brief   Check if the selected queue set member is the ring buffer's read semaphore
- *
- * This API checks if queue set member returned from xQueueSelectFromSet()
- * is the read semaphore of this ring buffer. If so, this indicates the ring buffer
- * has items waiting to be retrieved.
- *
- * @param[in]   xRingbuffer     Ring buffer which should be checked
- * @param[in]   xMember         Member returned from xQueueSelectFromSet
- *
- * @return
- *      - pdTRUE when semaphore belongs to ring buffer
- *      - pdFALSE otherwise.
- */
-BaseType_t xRingbufferCanRead(RingbufHandle_t xRingbuffer, QueueSetMemberHandle_t xMember);
-
-/**
- * @brief   Remove the ring buffer's read semaphore from a queue set.
- *
- * This specifically removes a ring buffer's read semaphore from a queue set. The
- * read semaphore is used to indicate when data has been written to the ring buffer
- *
- * @param[in]   xRingbuffer     Ring buffer to remove from the queue set
- * @param[in]   xQueueSet       Queue set to remove the ring buffer's read semaphore from
- *
- * @return
- *      - pdTRUE on success
- *      - pdFALSE otherwise
- */
-BaseType_t xRingbufferRemoveFromQueueSetRead(RingbufHandle_t xRingbuffer, QueueSetHandle_t xQueueSet);
-
-/**
- * @brief   Get information about ring buffer status
- *
- * Get information of the a ring buffer's current status such as
- * free/read/write pointer positions, and number of items waiting to be retrieved.
- * Arguments can be set to NULL if they are not required.
- *
- * @param[in]   xRingbuffer     Ring buffer to remove from the queue set
- * @param[out]  uxFree          Pointer use to store free pointer position
- * @param[out]  uxRead          Pointer use to store read pointer position
- * @param[out]  uxWrite         Pointer use to store write pointer position
- * @param[out]  uxItemsWaiting  Pointer use to store number of items (bytes for byte buffer) waiting to be retrieved
- */
-void vRingbufferGetInfo(RingbufHandle_t xRingbuffer, UBaseType_t *uxFree, UBaseType_t *uxRead, UBaseType_t *uxWrite, UBaseType_t *uxItemsWaiting);
-
-/**
- * @brief   Debugging function to print the internal pointers in the ring buffer
- *
- * @param   xRingbuffer Ring buffer to show
- */
-void xRingbufferPrintInfo(RingbufHandle_t xRingbuffer);
-
-/* -------------------------------- Deprecated Functions --------------------------- */
-
-/** @cond */    //Doxygen command to hide deprecated function from API Reference
-/*
- * Deprecated as function is not thread safe and does not check if an item is
- * actually available for retrieval. Use xRingbufferReceiveSplit() instead for
- * thread safe method of retrieve a split item.
- */
-bool xRingbufferIsNextItemWrapped(RingbufHandle_t xRingbuffer) __attribute__((deprecated));
-
-/*
- * Deprecated as queue sets are not meant to be used for writing to buffers. Adding
- * the ring buffer write semaphore to a queue set will break queue set usage rules,
- * as every read of a semaphore must be preceded by a call to xQueueSelectFromSet().
- * QueueSetWrite no longer supported.
- */
-BaseType_t xRingbufferAddToQueueSetWrite(RingbufHandle_t xRingbuffer, QueueSetHandle_t xQueueSet) __attribute__((deprecated));
-
-/*
- * Deprecated as queue sets are not meant to be used for writing to buffers.
- * QueueSetWrite no longer supported.
- */
-BaseType_t xRingbufferRemoveFromQueueSetWrite(RingbufHandle_t xRingbuffer, QueueSetHandle_t xQueueSet) __attribute__((deprecated));
-/** @endcond */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* FREERTOS_RINGBUF_H */
-
diff --git a/tools/sdk/include/esp_websocket_client/esp_websocket_client.h b/tools/sdk/include/esp_websocket_client/esp_websocket_client.h
deleted file mode 100644
index 6a8bca2b97b..00000000000
--- a/tools/sdk/include/esp_websocket_client/esp_websocket_client.h
+++ /dev/null
@@ -1,223 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_WEBSOCKET_CLIENT_H_
-#define _ESP_WEBSOCKET_CLIENT_H_
-
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <string.h>
-#include "freertos/FreeRTOS.h"
-#include "esp_err.h"
-#include "esp_event.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct esp_websocket_client *esp_websocket_client_handle_t;
-
-ESP_EVENT_DECLARE_BASE(WEBSOCKET_EVENTS);         // declaration of the task events family
-
-/**
- * @brief Websocket Client events id
- */
-typedef enum {
-    WEBSOCKET_EVENT_ANY = -1,
-    WEBSOCKET_EVENT_ERROR = 0,      /*!< This event occurs when there are any errors during execution */
-    WEBSOCKET_EVENT_CONNECTED,      /*!< Once the Websocket has been connected to the server, no data exchange has been performed */
-    WEBSOCKET_EVENT_DISCONNECTED,   /*!< The connection has been disconnected */
-    WEBSOCKET_EVENT_DATA,           /*!< When receiving data from the server, possibly multiple portions of the packet */
-    WEBSOCKET_EVENT_MAX
-} esp_websocket_event_id_t;
-
-/**
- * @brief Websocket event data
- */
-typedef struct {
-    const char *data_ptr;                   /*!< Data pointer */
-    int data_len;                           /*!< Data length */
-    uint8_t op_code;                        /*!< Received opcode */
-    esp_websocket_client_handle_t client;   /*!< esp_websocket_client_handle_t context */
-    void *user_context;                     /*!< user_data context, from esp_websocket_client_config_t user_data */
-    int payload_len;                        /*!< Total payload length, payloads exceeding buffer will be posted through multiple events */
-    int payload_offset;                     /*!< Actual offset for the data associated with this event */
-} esp_websocket_event_data_t;
-
-/**
- * @brief Websocket Client transport
- */
-typedef enum {
-    WEBSOCKET_TRANSPORT_UNKNOWN = 0x0,  /*!< Transport unknown */
-    WEBSOCKET_TRANSPORT_OVER_TCP,       /*!< Transport over tcp */
-    WEBSOCKET_TRANSPORT_OVER_SSL,       /*!< Transport over ssl */
-} esp_websocket_transport_t;
-
-/**
- * @brief Websocket client setup configuration
- */
-typedef struct {
-    const char                  *uri;                       /*!< Websocket URI, the information on the URI can be overrides the other fields below, if any */
-    const char                  *host;                      /*!< Domain or IP as string */
-    int                         port;                       /*!< Port to connect, default depend on esp_websocket_transport_t (80 or 443) */
-    const char                  *username;                  /*!< Using for Http authentication - Not supported for now */
-    const char                  *password;                  /*!< Using for Http authentication - Not supported for now */
-    const char                  *path;                      /*!< HTTP Path, if not set, default is `/` */
-    bool                        disable_auto_reconnect;     /*!< Disable the automatic reconnect function when disconnected */
-    void                        *user_context;              /*!< HTTP user data context */
-    int                         task_prio;                  /*!< Websocket task priority */
-    int                         task_stack;                 /*!< Websocket task stack */
-    int                         buffer_size;                /*!< Websocket buffer size */
-    const char                  *cert_pem;                  /*!< SSL Certification, PEM format as string, if the client requires to verify server */
-    esp_websocket_transport_t   transport;                  /*!< Websocket transport type, see `esp_websocket_transport_t */
-    char                        *subprotocol;               /*!< Websocket subprotocol */
-    char                        *user_agent;                /*!< Websocket user-agent */
-    char                        *headers;                   /*!< Websocket additional headers */
-    int                         pingpong_timeout_sec;       /*!< Period before connection is aborted due to no PONGs received, disabled if value is 0 */
-} esp_websocket_client_config_t;
-
-/**
- * @brief      Start a Websocket session
- *             This function must be the first function to call,
- *             and it returns a esp_websocket_client_handle_t that you must use as input to other functions in the interface.
- *             This call MUST have a corresponding call to esp_websocket_client_destroy when the operation is complete.
- *
- * @param[in]  config  The configuration
- *
- * @return
- *     - `esp_websocket_client_handle_t`
- *     - NULL if any errors
- */
-esp_websocket_client_handle_t esp_websocket_client_init(const esp_websocket_client_config_t *config);
-
-/**
- * @brief      Set URL for client, when performing this behavior, the options in the URL will replace the old ones
- *             Must stop the WebSocket client before set URI if the client has been connected
- *
- * @param[in]  client  The client
- * @param[in]  uri     The uri
- *
- * @return     esp_err_t
- */
-esp_err_t esp_websocket_client_set_uri(esp_websocket_client_handle_t client, const char *uri);
-
-/**
- * @brief      Open the WebSocket connection
- *
- * @param[in]  client  The client
- *
- * @return     esp_err_t
- */
-esp_err_t esp_websocket_client_start(esp_websocket_client_handle_t client);
-
-/**
- * @brief      Close the WebSocket connection
- *
- *  Notes:
- *  - Cannot be called from the websocket event handler 
- *
- * @param[in]  client  The client
- *
- * @return     esp_err_t
- */
-esp_err_t esp_websocket_client_stop(esp_websocket_client_handle_t client);
-
-/**
- * @brief      Destroy the WebSocket connection and free all resources.
- *             This function must be the last function to call for an session.
- *             It is the opposite of the esp_websocket_client_init function and must be called with the same handle as input that a esp_websocket_client_init call returned.
- *             This might close all connections this handle has used.
- * 
- *  Notes:
- *  - Cannot be called from the websocket event handler
- * 
- * @param[in]  client  The client
- *
- * @return     esp_err_t
- */
-esp_err_t esp_websocket_client_destroy(esp_websocket_client_handle_t client);
-
-/**
- * @brief      Generic write data to the WebSocket connection; defaults to binary send
- *
- * @param[in]  client  The client
- * @param[in]  data    The data
- * @param[in]  len     The length
- * @param[in]  timeout Write data timeout in RTOS ticks
- *
- * @return
- *     - Number of data was sent
- *     - (-1) if any errors
- */
-int esp_websocket_client_send(esp_websocket_client_handle_t client, const char *data, int len, TickType_t timeout);
-
-/**
- * @brief      Write binary data to the WebSocket connection (data send with WS OPCODE=02, i.e. binary)
- *
- * @param[in]  client  The client
- * @param[in]  data    The data
- * @param[in]  len     The length
- * @param[in]  timeout Write data timeout in RTOS ticks
- *
- * @return
- *     - Number of data was sent
- *     - (-1) if any errors
- */
-int esp_websocket_client_send_bin(esp_websocket_client_handle_t client, const char *data, int len, TickType_t timeout);
-
-/**
- * @brief      Write textual data to the WebSocket connection (data send with WS OPCODE=01, i.e. text)
- *
- * @param[in]  client  The client
- * @param[in]  data    The data
- * @param[in]  len     The length
- * @param[in]  timeout Write data timeout in RTOS ticks
- *
- * @return
- *     - Number of data was sent
- *     - (-1) if any errors
- */
-int esp_websocket_client_send_text(esp_websocket_client_handle_t client, const char *data, int len, TickType_t timeout);
-
-/**
- * @brief      Check the WebSocket client connection state
- *
- * @param[in]  client  The client handle
- *
- * @return
- *     - true
- *     - false
- */
-bool esp_websocket_client_is_connected(esp_websocket_client_handle_t client);
-
-/**
- * @brief Register the Websocket Events
- *
- * @param client            The client handle
- * @param event             The event id
- * @param event_handler     The callback function
- * @param event_handler_arg User context
- * @return esp_err_t
- */
-esp_err_t esp_websocket_register_events(esp_websocket_client_handle_t client,
-                                        esp_websocket_event_id_t event,
-                                        esp_event_handler_t event_handler,
-                                        void *event_handler_arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/espcoredump/esp_core_dump.h b/tools/sdk/include/espcoredump/esp_core_dump.h
deleted file mode 100644
index e19b45c98ad..00000000000
--- a/tools/sdk/include/espcoredump/esp_core_dump.h
+++ /dev/null
@@ -1,89 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef ESP_CORE_DUMP_H_
-#define ESP_CORE_DUMP_H_
-
-#include <stddef.h>
-#include "esp_err.h"
-#include "freertos/xtensa_context.h"
-
-/**************************************************************************************/
-/******************************** EXCEPTION MODE API **********************************/
-/**************************************************************************************/
-
-/**
- * @brief  Initializes core dump module internal data.
- *
- * @note  Should be called at system startup.
- */
-void esp_core_dump_init();
-
-/**
- * @brief  Saves core dump to flash.
- *
- * The structure of data stored in flash is as follows:
- *
- * |  TOTAL_LEN |  VERSION    | TASKS_NUM   | TCB_SIZE |
- * | TCB_ADDR_1 | STACK_TOP_1 | STACK_END_1 | TCB_1    | STACK_1 |
- * .            .       .         .
- * .            .       .         .
- * | TCB_ADDR_N | STACK_TOP_N | STACK_END_N | TCB_N    | STACK_N |
- * |    CRC32   |
- *
- * Core dump in flash consists of header and data for every task in the system at the moment of crash.
- * For flash data integrity control CRC is used at the end of core the dump data.
- * The structure of core dump data is described below in details.
- * 1) Core dump starts with header:
- * 1.1) TOTAL_LEN is total length of core dump data in flash including CRC. Size is 4 bytes.
- * 1.2) VERSION field keeps 4 byte version of core dump. 
- * 1.2) TASKS_NUM is the number of tasks for which data are stored. Size is 4 bytes.
- * 1.3) TCB_SIZE is the size of task's TCB structure. Size is 4 bytes.
- * 2) Core dump header is followed by the data for every task in the system.
- *    Task data are started with task header:
- * 2.1) TCB_ADDR is the address of TCB in memory. Size is 4 bytes.
- * 2.2) STACK_TOP is the top of task's stack (address of the topmost stack item). Size is 4 bytes.
- * 2.2) STACK_END is the end of task's stack (address from which task's stack starts). Size is 4 bytes.
- * 3) Task header is followed by TCB data. Size is TCB_SIZE bytes.
- * 4) Task's stack is placed after TCB data. Size is (STACK_END - STACK_TOP) bytes.
- * 5) CRC is placed at the end of the data.
- */
-void esp_core_dump_to_flash(XtExcFrame *frame);
-
-/**
- * @brief  Print base64-encoded core dump to UART.
- *
- * The structure of core dump data is the same as for data stored in flash (@see esp_core_dump_to_flash) with some notes:
- * 1) CRC is not present in core dump printed to UART.
- * 2) Since CRC is omitted TOTAL_LEN does not include its size.
- * 3) Printed base64 data are surrounded with special messages to help user recognize the start and end of actual data.
- */
-void esp_core_dump_to_uart(XtExcFrame *frame);
-
-
-/**************************************************************************************/
-/*********************************** USER MODE API ************************************/
-/**************************************************************************************/
-
-/**
- * @brief  Retrieves address and size of coredump data in flash.
- *         This function is always available, even when core dump is disabled in menuconfig.
- *
- * @param  out_addr   pointer to store image address in flash.
- * @param  out_size   pointer to store image size in flash (including CRC). In bytes.
- *
- * @return ESP_OK on success, otherwise \see esp_err_t
- */
-esp_err_t esp_core_dump_image_get(size_t* out_addr, size_t *out_size);
-
-#endif
diff --git a/tools/sdk/include/ethernet/esp_eth.h b/tools/sdk/include/ethernet/esp_eth.h
deleted file mode 100644
index f22cf4f7013..00000000000
--- a/tools/sdk/include/ethernet/esp_eth.h
+++ /dev/null
@@ -1,308 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_ETH_H__
-#define __ESP_ETH_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "esp_types.h"
-#include "esp_err.h"
-
-/**
- * @brief Ethernet interface mode
- *
- */
-typedef enum {
-    ETH_MODE_RMII = 0, /*!< RMII mode */
-    ETH_MODE_MII,      /*!< MII mode */
-} eth_mode_t;
-
-/**
- * @brief Ethernet clock mode
- *
- */
-typedef enum {
-    ETH_CLOCK_GPIO0_IN = 0,   /*!< RMII clock input to GPIO0 */
-    ETH_CLOCK_GPIO0_OUT = 1,  /*!< RMII clock output from GPIO0 */
-    ETH_CLOCK_GPIO16_OUT = 2, /*!< RMII clock output from GPIO16 */
-    ETH_CLOCK_GPIO17_OUT = 3  /*!< RMII clock output from GPIO17 */
-} eth_clock_mode_t;
-
-/**
- * @brief Ethernet Speed
- *
- */
-typedef enum {
-    ETH_SPEED_MODE_10M = 0, /*!< Ethernet speed: 10Mbps */
-    ETH_SPEED_MODE_100M,    /*!< Ethernet speed: 100Mbps */
-} eth_speed_mode_t;
-
-/**
- * @brief Ethernet Duplex
- *
- */
-typedef enum {
-    ETH_MODE_HALFDUPLEX = 0, /*!< Ethernet half duplex */
-    ETH_MODE_FULLDUPLEX,     /*!< Ethernet full duplex */
-} eth_duplex_mode_t;
-
-/**
- * @brief Ethernet PHY address
- *
- */
-typedef enum {
-    PHY0 = 0, /*!< PHY address 0 */
-    PHY1,     /*!< PHY address 1 */
-    PHY2,     /*!< PHY address 2 */
-    PHY3,     /*!< PHY address 3 */
-    PHY4,     /*!< PHY address 4 */
-    PHY5,     /*!< PHY address 5 */
-    PHY6,     /*!< PHY address 6 */
-    PHY7,     /*!< PHY address 7 */
-    PHY8,     /*!< PHY address 8 */
-    PHY9,     /*!< PHY address 9 */
-    PHY10,    /*!< PHY address 10 */
-    PHY11,    /*!< PHY address 11 */
-    PHY12,    /*!< PHY address 12 */
-    PHY13,    /*!< PHY address 13 */
-    PHY14,    /*!< PHY address 14 */
-    PHY15,    /*!< PHY address 15 */
-    PHY16,    /*!< PHY address 16 */
-    PHY17,    /*!< PHY address 17 */
-    PHY18,    /*!< PHY address 18 */
-    PHY19,    /*!< PHY address 19 */
-    PHY20,    /*!< PHY address 20 */
-    PHY21,    /*!< PHY address 21 */
-    PHY22,    /*!< PHY address 22 */
-    PHY23,    /*!< PHY address 23 */
-    PHY24,    /*!< PHY address 24 */
-    PHY25,    /*!< PHY address 25 */
-    PHY26,    /*!< PHY address 26 */
-    PHY27,    /*!< PHY address 27 */
-    PHY28,    /*!< PHY address 28 */
-    PHY29,    /*!< PHY address 29 */
-    PHY30,    /*!< PHY address 30 */
-    PHY31     /*!< PHY address 31 */
-} eth_phy_base_t;
-
-typedef bool (*eth_phy_check_link_func)(void);
-typedef void (*eth_phy_check_init_func)(void);
-typedef eth_speed_mode_t (*eth_phy_get_speed_mode_func)(void);
-typedef eth_duplex_mode_t (*eth_phy_get_duplex_mode_func)(void);
-typedef esp_err_t (*eth_phy_func)(void);
-typedef esp_err_t (*eth_tcpip_input_func)(void *buffer, uint16_t len, void *eb);
-typedef void (*eth_gpio_config_func)(void);
-typedef bool (*eth_phy_get_partner_pause_enable_func)(void);
-typedef void (*eth_phy_power_enable_func)(bool enable);
-
-/**
- * @brief ethernet configuration
- *
- */
-typedef struct {
-    eth_phy_base_t phy_addr;                                            /*!< PHY address (0~31) */
-    eth_mode_t mac_mode;                                                /*!< MAC mode: only support RMII now */
-    eth_clock_mode_t clock_mode;                                        /*!< external/internal clock mode selection */
-    eth_tcpip_input_func tcpip_input;                                   /*!< tcpip input func */
-    eth_phy_func phy_init;                                              /*!< phy init func */
-    eth_phy_check_link_func phy_check_link;                             /*!< phy check link func */
-    eth_phy_check_init_func phy_check_init;                             /*!< phy check init func */
-    eth_phy_get_speed_mode_func phy_get_speed_mode;                     /*!< phy check init func */
-    eth_phy_get_duplex_mode_func phy_get_duplex_mode;                   /*!< phy check init func */
-    eth_gpio_config_func gpio_config;                                   /*!< gpio config func  */
-    bool flow_ctrl_enable;                                              /*!< flag of flow ctrl enable */
-    eth_phy_get_partner_pause_enable_func phy_get_partner_pause_enable; /*!< get partner pause enable */
-    eth_phy_power_enable_func phy_power_enable;                         /*!< enable or disable phy power */
-    uint32_t reset_timeout_ms;                                          /*!< timeout value for reset emac */
-    bool promiscuous_enable;                                            /*!< set true to enable promiscuous mode */
-} eth_config_t;
-
-/**
- * @brief  Init ethernet mac
- *
- * @note   config can not be NULL, and phy chip must be suitable to phy init func.
- *
- * @param[in] config  mac init data.
- *
- * @return
- *      - ESP_OK
- *      - ESP_FAIL
- */
-esp_err_t esp_eth_init(eth_config_t *config);
-
-/**
- * @brief  Deinit ethernet mac
- *
- * @return
- *      - ESP_OK
- *      - ESP_FAIL
- *      - ESP_ERR_INVALID_STATE
- */
-esp_err_t esp_eth_deinit(void);
-
-/**
- * @brief  Init Ethernet mac driver only
- *
- * For the most part, you need not call this function directly. It gets called
- * from esp_eth_init().
- *
- * This function may be called, if you only need to initialize the Ethernet
- * driver without having to use the network stack on top.
- *
- * @note   config can not be NULL, and phy chip must be suitable to phy init func.
- * @param[in] config  mac init data.
- *
- * @return
- *      - ESP_OK
- *      - ESP_FAIL
- */
-esp_err_t esp_eth_init_internal(eth_config_t *config);
-
-/**
- * @brief  Send packet from tcp/ip to mac
- *
- * @note   buf can not be NULL, size must be less than 1580
- *
- * @param[in] buf:  start address of packet data.
- *
- * @param[in] size:  size (byte) of packet data.
- *
- * @return
- *      - ESP_OK
- *      - ESP_FAIL
- */
-esp_err_t esp_eth_tx(uint8_t *buf, uint16_t size);
-
-/**
- * @brief  Enable ethernet interface
- *
- * @note   Should be called after esp_eth_init
- *
- * @return
- *      - ESP_OK
- *      - ESP_FAIL
- */
-esp_err_t esp_eth_enable(void);
-
-/**
- * @brief  Disable ethernet interface
- *
- * @note   Should be called after esp_eth_init
- *
- * @return
- *      - ESP_OK
- *      - ESP_FAIL
- */
-esp_err_t esp_eth_disable(void);
-
-/**
- * @brief  Get mac addr
- *
- * @note   mac addr must be a valid unicast address
- *
- * @param[out] mac:  start address of mac address.
- */
-void esp_eth_get_mac(uint8_t mac[6]);
-
-/**
- * @brief  Write PHY reg with SMI interface.
- *
- * @note  PHY base addr must be right.
- *
- * @param[in] reg_num:  PHY reg num.
- *
- * @param[in] value: value which is written to PHY reg.
- */
-void esp_eth_smi_write(uint32_t reg_num, uint16_t value);
-
-/**
- * @brief  Read PHY reg with SMI interface.
- *
- * @note  PHY base addr must be right.
- *
- * @param[in] reg_num:  PHY reg num.
- *
- * @return value that is read from PHY reg
- */
-uint16_t esp_eth_smi_read(uint32_t reg_num);
-
-/**
- * @brief Continuously read a PHY register over SMI interface, wait until the register has the desired value.
- *
- * @note PHY base address must be right.
- *
- * @param reg_num: PHY register number
- * @param value: Value to wait for (masked with value_mask)
- * @param value_mask: Mask of bits to match in the register.
- * @param timeout_ms: Timeout to wait for this value (milliseconds). 0 means never timeout.
- *
- * @return ESP_OK if desired value matches, ESP_ERR_TIMEOUT if timed out.
- */
-esp_err_t esp_eth_smi_wait_value(uint32_t reg_num, uint16_t value, uint16_t value_mask, int timeout_ms);
-
-/**
- * @brief Continuously read a PHY register over SMI interface, wait until the register has all bits in a mask set.
- *
- * @note PHY base address must be right.
- *
- * @param reg_num: PHY register number
- * @param value_mask: Value mask to wait for (all bits in this mask must be set)
- * @param timeout_ms: Timeout to wait for this value (milliseconds). 0 means never timeout.
- *
- * @return ESP_OK if desired value matches, ESP_ERR_TIMEOUT if timed out.
- */
-static inline esp_err_t esp_eth_smi_wait_set(uint32_t reg_num, uint16_t value_mask, int timeout_ms)
-{
-    return esp_eth_smi_wait_value(reg_num, value_mask, value_mask, timeout_ms);
-}
-
-/**
- * @brief  Free emac rx buf.
- *
- * @note  buf can not be null, and it is tcpip input buf.
- *
- * @param[in] buf: start address of received packet data.
- *
- */
-void esp_eth_free_rx_buf(void *buf);
-
-/**
- * @brief  Set mac of ethernet interface.
- *
- * @note user can call this function after emac_init, and the new mac address will be enabled after emac_enable.
- *
- * @param[in] mac: the Mac address.
- *
- * @return
- *    - ESP_OK: succeed
- *    - ESP_ERR_INVALID_MAC: invalid mac address
- */
-esp_err_t esp_eth_set_mac(const uint8_t mac[6]);
-
-/**
- * @brief Get Ethernet link speed
- *
- * @return eth_speed_mode_t ETH_SPEED_MODE_10M when link speed is 10Mbps
- *                          ETH_SPEED_MODE_100M when link speed is 100Mbps
- */
-eth_speed_mode_t esp_eth_get_speed(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/ethernet/eth_phy/phy.h b/tools/sdk/include/ethernet/eth_phy/phy.h
deleted file mode 100644
index d38e9819d6d..00000000000
--- a/tools/sdk/include/ethernet/eth_phy/phy.h
+++ /dev/null
@@ -1,76 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "esp_eth.h"
-
-/**
- * @brief Common PHY-management functions.
- *
- * @note These are not enough to drive any particular Ethernet PHY.
- * They provide a common configuration structure and management functions.
- *
- */
-
-/**
- * @brief Configure fixed pins for RMII data interface.
- *
- * @note This configures GPIOs 0, 19, 22, 25, 26, 27 for use with RMII data interface.
- * These pins cannot be changed, and must be wired to ethernet functions.
- * This is not sufficient to fully configure the Ethernet PHY.
- * MDIO configuration interface pins (such as SMI MDC, MDO, MDI) must also be configured correctly in the GPIO matrix.
- *
- */
-void phy_rmii_configure_data_interface_pins(void);
-
-/**
- * @brief Configure variable pins for SMI ethernet functions.
- *
- * @param mdc_gpio MDC GPIO Pin number
- * @param mdio_gpio MDIO GPIO Pin number
- *
- * @note Calling this function along with mii_configure_default_pins() will fully configure the GPIOs for the ethernet PHY.
- */
-void phy_rmii_smi_configure_pins(uint8_t mdc_gpio, uint8_t mdio_gpio);
-
-/**
- * @brief Enable flow control in standard PHY MII register.
- *
- */
-void phy_mii_enable_flow_ctrl(void);
-
-/**
- * @brief Check Ethernet link status via MII interface
- *
- * @return true Link is on
- * @return false Link is off
- */
-bool phy_mii_check_link_status(void);
-
-/**
- * @brief Check pause frame ability of partner via MII interface
- *
- * @return true Partner is able to process pause frame
- * @return false Partner can not process pause frame
- */
-bool phy_mii_get_partner_pause_enable(void);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/ethernet/eth_phy/phy_ip101.h b/tools/sdk/include/ethernet/eth_phy/phy_ip101.h
deleted file mode 100644
index d18ef2d0964..00000000000
--- a/tools/sdk/include/ethernet/eth_phy/phy_ip101.h
+++ /dev/null
@@ -1,75 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "phy.h"
-
-/**
- * @brief Dump IP101 PHY SMI configuration registers
- *
- */
-void phy_ip101_dump_registers();
-
-/**
- * @brief Default IP101 phy_check_init function
- *
- */
-void phy_ip101_check_phy_init(void);
-
-/**
- * @brief Default IP101 phy_get_speed_mode function
- *
- * @return eth_speed_mode_t Ethernet speed mode
- */
-eth_speed_mode_t phy_ip101_get_speed_mode(void);
-
-/**
- * @brief Default IP101 phy_get_duplex_mode function
- *
- * @return eth_duplex_mode_t Ethernet duplex mode
- */
-eth_duplex_mode_t phy_ip101_get_duplex_mode(void);
-
-/**
- * @brief Default IP101 phy_power_enable function
- *
- */
-void phy_ip101_power_enable(bool);
-
-/**
- * @brief Default IP101 phy_init function
- *
- * @return esp_err_t
- *      - ESP_OK on success
- *      - ESP_FAIL on error
- */
-esp_err_t phy_ip101_init(void);
-
-/**
- * @brief Default IP101 PHY configuration
- *
- * @note This configuration is not suitable for use as-is,
- * it will need to be modified for your particular PHY hardware setup.
- *
- */
-extern const eth_config_t phy_ip101_default_ethernet_config;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/ethernet/eth_phy/phy_lan8720.h b/tools/sdk/include/ethernet/eth_phy/phy_lan8720.h
deleted file mode 100644
index 1448f36556c..00000000000
--- a/tools/sdk/include/ethernet/eth_phy/phy_lan8720.h
+++ /dev/null
@@ -1,75 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "phy.h"
-
-/**
- * @brief Dump LAN8720 PHY SMI configuration registers
- *
- */
-void phy_lan8720_dump_registers();
-
-/**
- * @brief Default LAN8720 phy_check_init function
- *
- */
-void phy_lan8720_check_phy_init(void);
-
-/**
- * @brief Default LAN8720 phy_get_speed_mode function
- *
- * @return eth_speed_mode_t Ethernet speed mode
- */
-eth_speed_mode_t phy_lan8720_get_speed_mode(void);
-
-/**
- * @brief Default LAN8720 phy_get_duplex_mode function
- *
- * @return eth_duplex_mode_t Ethernet duplex mode
- */
-eth_duplex_mode_t phy_lan8720_get_duplex_mode(void);
-
-/**
- * @brief Default LAN8720 phy_power_enable function
- *
- */
-void phy_lan8720_power_enable(bool);
-
-/**
- * @brief Default LAN8720 phy_init function
- *
- * @return esp_err_t
- *      - ESP_OK on success
- *      - ESP_FAIL on error
- */
-esp_err_t phy_lan8720_init(void);
-
-/**
- * @brief Default LAN8720 PHY configuration
- *
- * @note This configuration is not suitable for use as-is,
- * it will need to be modified for your particular PHY hardware setup.
- *
- */
-extern const eth_config_t phy_lan8720_default_ethernet_config;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/ethernet/eth_phy/phy_reg.h b/tools/sdk/include/ethernet/eth_phy/phy_reg.h
deleted file mode 100644
index 2a9a141676a..00000000000
--- a/tools/sdk/include/ethernet/eth_phy/phy_reg.h
+++ /dev/null
@@ -1,54 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief This header contains register/bit masks for the standard PHY MII registers that should be supported by all PHY models.
- *
- */
-
-#define MII_BASIC_MODE_CONTROL_REG              (0x0)
-#define MII_SOFTWARE_RESET                      BIT(15)
-#define MII_SPEED_SELECT                        BIT(13)
-#define MII_AUTO_NEGOTIATION_ENABLE             BIT(12)
-#define MII_POWER_DOWN                          BIT(11)
-#define MII_RESTART_AUTO_NEGOTIATION            BIT(9)
-#define MII_DUPLEX_MODE                         BIT(8)
-
-#define MII_BASIC_MODE_STATUS_REG               (0x1)
-#define MII_AUTO_NEGOTIATION_COMPLETE           BIT(5)
-#define MII_LINK_STATUS                         BIT(2)
-
-#define MII_PHY_IDENTIFIER_1_REG                (0x2)
-#define MII_PHY_IDENTIFIER_2_REG                (0x3)
-
-#define MII_AUTO_NEGOTIATION_ADVERTISEMENT_REG  (0x4)
-#define MII_ASM_DIR                             BIT(11)
-#define MII_PAUSE                               BIT(10)
-
-#define MII_PHY_LINK_PARTNER_ABILITY_REG        (0x5)
-#define MII_PARTNER_ASM_DIR                     BIT(11)
-#define MII_PARTNER_PAUSE                       BIT(10)
-
-/******************************legacy*******************************/
-#define MII_AUTO_NEG_ADVERTISEMENT_REG MII_AUTO_NEGOTIATION_ADVERTISEMENT_REG
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/ethernet/eth_phy/phy_tlk110.h b/tools/sdk/include/ethernet/eth_phy/phy_tlk110.h
deleted file mode 100644
index 077f13cece0..00000000000
--- a/tools/sdk/include/ethernet/eth_phy/phy_tlk110.h
+++ /dev/null
@@ -1,75 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "phy.h"
-
-/**
- * @brief Dump TLK110 PHY SMI configuration registers
- *
- */
-void phy_tlk110_dump_registers();
-
-/**
- * @brief Default TLK110 phy_check_init function
- *
- */
-void phy_tlk110_check_phy_init(void);
-
-/**
- * @brief Default TLK110 phy_get_speed_mode function
- *
- * @return eth_speed_mode_t Ethernet speed mode
- */
-eth_speed_mode_t phy_tlk110_get_speed_mode(void);
-
-/**
- * @brief Default TLK110 phy_get_duplex_mode function
- *
- * @return eth_duplex_mode_t Ethernet duplex mode
- */
-eth_duplex_mode_t phy_tlk110_get_duplex_mode(void);
-
-/**
- * @brief Default TLK110 phy_power_enable function
- *
- */
-void phy_tlk110_power_enable(bool);
-
-/**
- * @brief Default TLK110 phy_init function
- *
- * @return esp_err_t
- *      - ESP_OK on success
- *      - ESP_FAIL on error
- */
-esp_err_t phy_tlk110_init(void);
-
-/**
- * @brief Default TLK110 PHY configuration
- *
- * @note This configuration is not suitable for use as-is,
- * it will need to be modified for your particular PHY hardware setup.
- *
- */
-extern const eth_config_t phy_tlk110_default_ethernet_config;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/expat/ascii.h b/tools/sdk/include/expat/ascii.h
deleted file mode 100644
index c3587e57332..00000000000
--- a/tools/sdk/include/expat/ascii.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#define ASCII_A 0x41
-#define ASCII_B 0x42
-#define ASCII_C 0x43
-#define ASCII_D 0x44
-#define ASCII_E 0x45
-#define ASCII_F 0x46
-#define ASCII_G 0x47
-#define ASCII_H 0x48
-#define ASCII_I 0x49
-#define ASCII_J 0x4A
-#define ASCII_K 0x4B
-#define ASCII_L 0x4C
-#define ASCII_M 0x4D
-#define ASCII_N 0x4E
-#define ASCII_O 0x4F
-#define ASCII_P 0x50
-#define ASCII_Q 0x51
-#define ASCII_R 0x52
-#define ASCII_S 0x53
-#define ASCII_T 0x54
-#define ASCII_U 0x55
-#define ASCII_V 0x56
-#define ASCII_W 0x57
-#define ASCII_X 0x58
-#define ASCII_Y 0x59
-#define ASCII_Z 0x5A
-
-#define ASCII_a 0x61
-#define ASCII_b 0x62
-#define ASCII_c 0x63
-#define ASCII_d 0x64
-#define ASCII_e 0x65
-#define ASCII_f 0x66
-#define ASCII_g 0x67
-#define ASCII_h 0x68
-#define ASCII_i 0x69
-#define ASCII_j 0x6A
-#define ASCII_k 0x6B
-#define ASCII_l 0x6C
-#define ASCII_m 0x6D
-#define ASCII_n 0x6E
-#define ASCII_o 0x6F
-#define ASCII_p 0x70
-#define ASCII_q 0x71
-#define ASCII_r 0x72
-#define ASCII_s 0x73
-#define ASCII_t 0x74
-#define ASCII_u 0x75
-#define ASCII_v 0x76
-#define ASCII_w 0x77
-#define ASCII_x 0x78
-#define ASCII_y 0x79
-#define ASCII_z 0x7A
-
-#define ASCII_0 0x30
-#define ASCII_1 0x31
-#define ASCII_2 0x32
-#define ASCII_3 0x33
-#define ASCII_4 0x34
-#define ASCII_5 0x35
-#define ASCII_6 0x36
-#define ASCII_7 0x37
-#define ASCII_8 0x38
-#define ASCII_9 0x39
-
-#define ASCII_TAB 0x09
-#define ASCII_SPACE 0x20
-#define ASCII_EXCL 0x21
-#define ASCII_QUOT 0x22
-#define ASCII_AMP 0x26
-#define ASCII_APOS 0x27
-#define ASCII_MINUS 0x2D
-#define ASCII_PERIOD 0x2E
-#define ASCII_COLON 0x3A
-#define ASCII_SEMI 0x3B
-#define ASCII_LT 0x3C
-#define ASCII_EQUALS 0x3D
-#define ASCII_GT 0x3E
-#define ASCII_LSQB 0x5B
-#define ASCII_RSQB 0x5D
-#define ASCII_UNDERSCORE 0x5F
-#define ASCII_LPAREN 0x28
-#define ASCII_RPAREN 0x29
-#define ASCII_FF 0x0C
-#define ASCII_SLASH 0x2F
-#define ASCII_HASH 0x23
-#define ASCII_PIPE 0x7C
-#define ASCII_COMMA 0x2C
diff --git a/tools/sdk/include/expat/asciitab.h b/tools/sdk/include/expat/asciitab.h
deleted file mode 100644
index 63b1d1b4482..00000000000
--- a/tools/sdk/include/expat/asciitab.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/* 0x00 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x04 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x08 */ BT_NONXML, BT_S, BT_LF, BT_NONXML,
-    /* 0x0C */ BT_NONXML, BT_CR, BT_NONXML, BT_NONXML,
-    /* 0x10 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x14 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x18 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x1C */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x20 */ BT_S, BT_EXCL, BT_QUOT, BT_NUM,
-    /* 0x24 */ BT_OTHER, BT_PERCNT, BT_AMP, BT_APOS,
-    /* 0x28 */ BT_LPAR, BT_RPAR, BT_AST, BT_PLUS,
-    /* 0x2C */ BT_COMMA, BT_MINUS, BT_NAME, BT_SOL,
-    /* 0x30 */ BT_DIGIT, BT_DIGIT, BT_DIGIT, BT_DIGIT,
-    /* 0x34 */ BT_DIGIT, BT_DIGIT, BT_DIGIT, BT_DIGIT,
-    /* 0x38 */ BT_DIGIT, BT_DIGIT, BT_COLON, BT_SEMI,
-    /* 0x3C */ BT_LT, BT_EQUALS, BT_GT, BT_QUEST,
-    /* 0x40 */ BT_OTHER, BT_HEX, BT_HEX, BT_HEX,
-    /* 0x44 */ BT_HEX, BT_HEX, BT_HEX, BT_NMSTRT,
-    /* 0x48 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x4C */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x50 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x54 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x58 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_LSQB,
-    /* 0x5C */ BT_OTHER, BT_RSQB, BT_OTHER, BT_NMSTRT,
-    /* 0x60 */ BT_OTHER, BT_HEX, BT_HEX, BT_HEX,
-    /* 0x64 */ BT_HEX, BT_HEX, BT_HEX, BT_NMSTRT,
-    /* 0x68 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x6C */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x70 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x74 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x78 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_OTHER,
-    /* 0x7C */ BT_VERBAR, BT_OTHER, BT_OTHER, BT_OTHER,
diff --git a/tools/sdk/include/expat/expat.h b/tools/sdk/include/expat/expat.h
deleted file mode 100644
index 48a6e2a3291..00000000000
--- a/tools/sdk/include/expat/expat.h
+++ /dev/null
@@ -1,1024 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef Expat_INCLUDED
-#define Expat_INCLUDED 1
-
-#include <stdlib.h>
-#include "expat_external.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct XML_ParserStruct;
-typedef struct XML_ParserStruct *XML_Parser;
-
-typedef unsigned char XML_Bool;
-#define XML_TRUE ((XML_Bool)1)
-#define XML_FALSE ((XML_Bool)0)
-
-/* The XML_Status enum gives the possible return values for several
-   API functions.  The preprocessor #defines are included so this
-   stanza can be added to code that still needs to support older
-   versions of Expat 1.95.x:
-
-   #ifndef XML_STATUS_OK
-   #define XML_STATUS_OK    1
-   #define XML_STATUS_ERROR 0
-   #endif
-
-   Otherwise, the #define hackery is quite ugly and would have been
-   dropped.
-*/
-enum XML_Status {
-  XML_STATUS_ERROR = 0,
-#define XML_STATUS_ERROR XML_STATUS_ERROR
-  XML_STATUS_OK = 1,
-#define XML_STATUS_OK XML_STATUS_OK
-  XML_STATUS_SUSPENDED = 2
-#define XML_STATUS_SUSPENDED XML_STATUS_SUSPENDED
-};
-
-enum XML_Error {
-  XML_ERROR_NONE,
-  XML_ERROR_NO_MEMORY,
-  XML_ERROR_SYNTAX,
-  XML_ERROR_NO_ELEMENTS,
-  XML_ERROR_INVALID_TOKEN,
-  XML_ERROR_UNCLOSED_TOKEN,
-  XML_ERROR_PARTIAL_CHAR,
-  XML_ERROR_TAG_MISMATCH,
-  XML_ERROR_DUPLICATE_ATTRIBUTE,
-  XML_ERROR_JUNK_AFTER_DOC_ELEMENT,
-  XML_ERROR_PARAM_ENTITY_REF,
-  XML_ERROR_UNDEFINED_ENTITY,
-  XML_ERROR_RECURSIVE_ENTITY_REF,
-  XML_ERROR_ASYNC_ENTITY,
-  XML_ERROR_BAD_CHAR_REF,
-  XML_ERROR_BINARY_ENTITY_REF,
-  XML_ERROR_ATTRIBUTE_EXTERNAL_ENTITY_REF,
-  XML_ERROR_MISPLACED_XML_PI,
-  XML_ERROR_UNKNOWN_ENCODING,
-  XML_ERROR_INCORRECT_ENCODING,
-  XML_ERROR_UNCLOSED_CDATA_SECTION,
-  XML_ERROR_EXTERNAL_ENTITY_HANDLING,
-  XML_ERROR_NOT_STANDALONE,
-  XML_ERROR_UNEXPECTED_STATE,
-  XML_ERROR_ENTITY_DECLARED_IN_PE,
-  XML_ERROR_FEATURE_REQUIRES_XML_DTD,
-  XML_ERROR_CANT_CHANGE_FEATURE_ONCE_PARSING,
-  /* Added in 1.95.7. */
-  XML_ERROR_UNBOUND_PREFIX,
-  /* Added in 1.95.8. */
-  XML_ERROR_UNDECLARING_PREFIX,
-  XML_ERROR_INCOMPLETE_PE,
-  XML_ERROR_XML_DECL,
-  XML_ERROR_TEXT_DECL,
-  XML_ERROR_PUBLICID,
-  XML_ERROR_SUSPENDED,
-  XML_ERROR_NOT_SUSPENDED,
-  XML_ERROR_ABORTED,
-  XML_ERROR_FINISHED,
-  XML_ERROR_SUSPEND_PE,
-  /* Added in 2.0. */
-  XML_ERROR_RESERVED_PREFIX_XML,
-  XML_ERROR_RESERVED_PREFIX_XMLNS,
-  XML_ERROR_RESERVED_NAMESPACE_URI,
-  /* Added in 2.2.1. */
-  XML_ERROR_INVALID_ARGUMENT
-};
-
-enum XML_Content_Type {
-  XML_CTYPE_EMPTY = 1,
-  XML_CTYPE_ANY,
-  XML_CTYPE_MIXED,
-  XML_CTYPE_NAME,
-  XML_CTYPE_CHOICE,
-  XML_CTYPE_SEQ
-};
-
-enum XML_Content_Quant {
-  XML_CQUANT_NONE,
-  XML_CQUANT_OPT,
-  XML_CQUANT_REP,
-  XML_CQUANT_PLUS
-};
-
-/* If type == XML_CTYPE_EMPTY or XML_CTYPE_ANY, then quant will be
-   XML_CQUANT_NONE, and the other fields will be zero or NULL.
-   If type == XML_CTYPE_MIXED, then quant will be NONE or REP and
-   numchildren will contain number of elements that may be mixed in
-   and children point to an array of XML_Content cells that will be
-   all of XML_CTYPE_NAME type with no quantification.
-
-   If type == XML_CTYPE_NAME, then the name points to the name, and
-   the numchildren field will be zero and children will be NULL. The
-   quant fields indicates any quantifiers placed on the name.
-
-   CHOICE and SEQ will have name NULL, the number of children in
-   numchildren and children will point, recursively, to an array
-   of XML_Content cells.
-
-   The EMPTY, ANY, and MIXED types will only occur at top level.
-*/
-
-typedef struct XML_cp XML_Content;
-
-struct XML_cp {
-  enum XML_Content_Type type;
-  enum XML_Content_Quant quant;
-  XML_Char *name;
-  unsigned int numchildren;
-  XML_Content *children;
-};
-
-/* This is called for an element declaration. See above for
-   description of the model argument. It's the caller's responsibility
-   to free model when finished with it.
-*/
-typedef void(XMLCALL *XML_ElementDeclHandler)(void *userData,
-                                              const XML_Char *name,
-                                              XML_Content *model);
-
-XMLPARSEAPI(void)
-XML_SetElementDeclHandler(XML_Parser parser, XML_ElementDeclHandler eldecl);
-
-/* The Attlist declaration handler is called for *each* attribute. So
-   a single Attlist declaration with multiple attributes declared will
-   generate multiple calls to this handler. The "default" parameter
-   may be NULL in the case of the "#IMPLIED" or "#REQUIRED"
-   keyword. The "isrequired" parameter will be true and the default
-   value will be NULL in the case of "#REQUIRED". If "isrequired" is
-   true and default is non-NULL, then this is a "#FIXED" default.
-*/
-typedef void(XMLCALL *XML_AttlistDeclHandler)(
-    void *userData, const XML_Char *elname, const XML_Char *attname,
-    const XML_Char *att_type, const XML_Char *dflt, int isrequired);
-
-XMLPARSEAPI(void)
-XML_SetAttlistDeclHandler(XML_Parser parser, XML_AttlistDeclHandler attdecl);
-
-/* The XML declaration handler is called for *both* XML declarations
-   and text declarations. The way to distinguish is that the version
-   parameter will be NULL for text declarations. The encoding
-   parameter may be NULL for XML declarations. The standalone
-   parameter will be -1, 0, or 1 indicating respectively that there
-   was no standalone parameter in the declaration, that it was given
-   as no, or that it was given as yes.
-*/
-typedef void(XMLCALL *XML_XmlDeclHandler)(void *userData,
-                                          const XML_Char *version,
-                                          const XML_Char *encoding,
-                                          int standalone);
-
-XMLPARSEAPI(void)
-XML_SetXmlDeclHandler(XML_Parser parser, XML_XmlDeclHandler xmldecl);
-
-typedef struct {
-  void *(*malloc_fcn)(size_t size);
-  void *(*realloc_fcn)(void *ptr, size_t size);
-  void (*free_fcn)(void *ptr);
-} XML_Memory_Handling_Suite;
-
-/* Constructs a new parser; encoding is the encoding specified by the
-   external protocol or NULL if there is none specified.
-*/
-XMLPARSEAPI(XML_Parser)
-XML_ParserCreate(const XML_Char *encoding);
-
-/* Constructs a new parser and namespace processor.  Element type
-   names and attribute names that belong to a namespace will be
-   expanded; unprefixed attribute names are never expanded; unprefixed
-   element type names are expanded only if there is a default
-   namespace. The expanded name is the concatenation of the namespace
-   URI, the namespace separator character, and the local part of the
-   name.  If the namespace separator is '\0' then the namespace URI
-   and the local part will be concatenated without any separator.
-   It is a programming error to use the separator '\0' with namespace
-   triplets (see XML_SetReturnNSTriplet).
-*/
-XMLPARSEAPI(XML_Parser)
-XML_ParserCreateNS(const XML_Char *encoding, XML_Char namespaceSeparator);
-
-/* Constructs a new parser using the memory management suite referred to
-   by memsuite. If memsuite is NULL, then use the standard library memory
-   suite. If namespaceSeparator is non-NULL it creates a parser with
-   namespace processing as described above. The character pointed at
-   will serve as the namespace separator.
-
-   All further memory operations used for the created parser will come from
-   the given suite.
-*/
-XMLPARSEAPI(XML_Parser)
-XML_ParserCreate_MM(const XML_Char *encoding,
-                    const XML_Memory_Handling_Suite *memsuite,
-                    const XML_Char *namespaceSeparator);
-
-/* Prepare a parser object to be re-used.  This is particularly
-   valuable when memory allocation overhead is disproportionately high,
-   such as when a large number of small documnents need to be parsed.
-   All handlers are cleared from the parser, except for the
-   unknownEncodingHandler. The parser's external state is re-initialized
-   except for the values of ns and ns_triplets.
-
-   Added in Expat 1.95.3.
-*/
-XMLPARSEAPI(XML_Bool)
-XML_ParserReset(XML_Parser parser, const XML_Char *encoding);
-
-/* atts is array of name/value pairs, terminated by 0;
-   names and values are 0 terminated.
-*/
-typedef void(XMLCALL *XML_StartElementHandler)(void *userData,
-                                               const XML_Char *name,
-                                               const XML_Char **atts);
-
-typedef void(XMLCALL *XML_EndElementHandler)(void *userData,
-                                             const XML_Char *name);
-
-/* s is not 0 terminated. */
-typedef void(XMLCALL *XML_CharacterDataHandler)(void *userData,
-                                                const XML_Char *s, int len);
-
-/* target and data are 0 terminated */
-typedef void(XMLCALL *XML_ProcessingInstructionHandler)(void *userData,
-                                                        const XML_Char *target,
-                                                        const XML_Char *data);
-
-/* data is 0 terminated */
-typedef void(XMLCALL *XML_CommentHandler)(void *userData, const XML_Char *data);
-
-typedef void(XMLCALL *XML_StartCdataSectionHandler)(void *userData);
-typedef void(XMLCALL *XML_EndCdataSectionHandler)(void *userData);
-
-/* This is called for any characters in the XML document for which
-   there is no applicable handler.  This includes both characters that
-   are part of markup which is of a kind that is not reported
-   (comments, markup declarations), or characters that are part of a
-   construct which could be reported but for which no handler has been
-   supplied. The characters are passed exactly as they were in the XML
-   document except that they will be encoded in UTF-8 or UTF-16.
-   Line boundaries are not normalized. Note that a byte order mark
-   character is not passed to the default handler. There are no
-   guarantees about how characters are divided between calls to the
-   default handler: for example, a comment might be split between
-   multiple calls.
-*/
-typedef void(XMLCALL *XML_DefaultHandler)(void *userData, const XML_Char *s,
-                                          int len);
-
-/* This is called for the start of the DOCTYPE declaration, before
-   any DTD or internal subset is parsed.
-*/
-typedef void(XMLCALL *XML_StartDoctypeDeclHandler)(void *userData,
-                                                   const XML_Char *doctypeName,
-                                                   const XML_Char *sysid,
-                                                   const XML_Char *pubid,
-                                                   int has_internal_subset);
-
-/* This is called for the start of the DOCTYPE declaration when the
-   closing > is encountered, but after processing any external
-   subset.
-*/
-typedef void(XMLCALL *XML_EndDoctypeDeclHandler)(void *userData);
-
-/* This is called for entity declarations. The is_parameter_entity
-   argument will be non-zero if the entity is a parameter entity, zero
-   otherwise.
-
-   For internal entities (<!ENTITY foo "bar">), value will
-   be non-NULL and systemId, publicID, and notationName will be NULL.
-   The value string is NOT nul-terminated; the length is provided in
-   the value_length argument. Since it is legal to have zero-length
-   values, do not use this argument to test for internal entities.
-
-   For external entities, value will be NULL and systemId will be
-   non-NULL. The publicId argument will be NULL unless a public
-   identifier was provided. The notationName argument will have a
-   non-NULL value only for unparsed entity declarations.
-
-   Note that is_parameter_entity can't be changed to XML_Bool, since
-   that would break binary compatibility.
-*/
-typedef void(XMLCALL *XML_EntityDeclHandler)(
-    void *userData, const XML_Char *entityName, int is_parameter_entity,
-    const XML_Char *value, int value_length, const XML_Char *base,
-    const XML_Char *systemId, const XML_Char *publicId,
-    const XML_Char *notationName);
-
-XMLPARSEAPI(void)
-XML_SetEntityDeclHandler(XML_Parser parser, XML_EntityDeclHandler handler);
-
-/* OBSOLETE -- OBSOLETE -- OBSOLETE
-   This handler has been superseded by the EntityDeclHandler above.
-   It is provided here for backward compatibility.
-
-   This is called for a declaration of an unparsed (NDATA) entity.
-   The base argument is whatever was set by XML_SetBase. The
-   entityName, systemId and notationName arguments will never be
-   NULL. The other arguments may be.
-*/
-typedef void(XMLCALL *XML_UnparsedEntityDeclHandler)(
-    void *userData, const XML_Char *entityName, const XML_Char *base,
-    const XML_Char *systemId, const XML_Char *publicId,
-    const XML_Char *notationName);
-
-/* This is called for a declaration of notation.  The base argument is
-   whatever was set by XML_SetBase. The notationName will never be
-   NULL.  The other arguments can be.
-*/
-typedef void(XMLCALL *XML_NotationDeclHandler)(void *userData,
-                                               const XML_Char *notationName,
-                                               const XML_Char *base,
-                                               const XML_Char *systemId,
-                                               const XML_Char *publicId);
-
-/* When namespace processing is enabled, these are called once for
-   each namespace declaration. The call to the start and end element
-   handlers occur between the calls to the start and end namespace
-   declaration handlers. For an xmlns attribute, prefix will be
-   NULL.  For an xmlns="" attribute, uri will be NULL.
-*/
-typedef void(XMLCALL *XML_StartNamespaceDeclHandler)(void *userData,
-                                                     const XML_Char *prefix,
-                                                     const XML_Char *uri);
-
-typedef void(XMLCALL *XML_EndNamespaceDeclHandler)(void *userData,
-                                                   const XML_Char *prefix);
-
-/* This is called if the document is not standalone, that is, it has an
-   external subset or a reference to a parameter entity, but does not
-   have standalone="yes". If this handler returns XML_STATUS_ERROR,
-   then processing will not continue, and the parser will return a
-   XML_ERROR_NOT_STANDALONE error.
-   If parameter entity parsing is enabled, then in addition to the
-   conditions above this handler will only be called if the referenced
-   entity was actually read.
-*/
-typedef int(XMLCALL *XML_NotStandaloneHandler)(void *userData);
-
-/* This is called for a reference to an external parsed general
-   entity.  The referenced entity is not automatically parsed.  The
-   application can parse it immediately or later using
-   XML_ExternalEntityParserCreate.
-
-   The parser argument is the parser parsing the entity containing the
-   reference; it can be passed as the parser argument to
-   XML_ExternalEntityParserCreate.  The systemId argument is the
-   system identifier as specified in the entity declaration; it will
-   not be NULL.
-
-   The base argument is the system identifier that should be used as
-   the base for resolving systemId if systemId was relative; this is
-   set by XML_SetBase; it may be NULL.
-
-   The publicId argument is the public identifier as specified in the
-   entity declaration, or NULL if none was specified; the whitespace
-   in the public identifier will have been normalized as required by
-   the XML spec.
-
-   The context argument specifies the parsing context in the format
-   expected by the context argument to XML_ExternalEntityParserCreate;
-   context is valid only until the handler returns, so if the
-   referenced entity is to be parsed later, it must be copied.
-   context is NULL only when the entity is a parameter entity.
-
-   The handler should return XML_STATUS_ERROR if processing should not
-   continue because of a fatal error in the handling of the external
-   entity.  In this case the calling parser will return an
-   XML_ERROR_EXTERNAL_ENTITY_HANDLING error.
-
-   Note that unlike other handlers the first argument is the parser,
-   not userData.
-*/
-typedef int(XMLCALL *XML_ExternalEntityRefHandler)(XML_Parser parser,
-                                                   const XML_Char *context,
-                                                   const XML_Char *base,
-                                                   const XML_Char *systemId,
-                                                   const XML_Char *publicId);
-
-/* This is called in two situations:
-   1) An entity reference is encountered for which no declaration
-      has been read *and* this is not an error.
-   2) An internal entity reference is read, but not expanded, because
-      XML_SetDefaultHandler has been called.
-   Note: skipped parameter entities in declarations and skipped general
-         entities in attribute values cannot be reported, because
-         the event would be out of sync with the reporting of the
-         declarations or attribute values
-*/
-typedef void(XMLCALL *XML_SkippedEntityHandler)(void *userData,
-                                                const XML_Char *entityName,
-                                                int is_parameter_entity);
-
-/* This structure is filled in by the XML_UnknownEncodingHandler to
-   provide information to the parser about encodings that are unknown
-   to the parser.
-
-   The map[b] member gives information about byte sequences whose
-   first byte is b.
-
-   If map[b] is c where c is >= 0, then b by itself encodes the
-   Unicode scalar value c.
-
-   If map[b] is -1, then the byte sequence is malformed.
-
-   If map[b] is -n, where n >= 2, then b is the first byte of an
-   n-byte sequence that encodes a single Unicode scalar value.
-
-   The data member will be passed as the first argument to the convert
-   function.
-
-   The convert function is used to convert multibyte sequences; s will
-   point to a n-byte sequence where map[(unsigned char)*s] == -n.  The
-   convert function must return the Unicode scalar value represented
-   by this byte sequence or -1 if the byte sequence is malformed.
-
-   The convert function may be NULL if the encoding is a single-byte
-   encoding, that is if map[b] >= -1 for all bytes b.
-
-   When the parser is finished with the encoding, then if release is
-   not NULL, it will call release passing it the data member; once
-   release has been called, the convert function will not be called
-   again.
-
-   Expat places certain restrictions on the encodings that are supported
-   using this mechanism.
-
-   1. Every ASCII character that can appear in a well-formed XML document,
-      other than the characters
-
-      $@\^`{}~
-
-      must be represented by a single byte, and that byte must be the
-      same byte that represents that character in ASCII.
-
-   2. No character may require more than 4 bytes to encode.
-
-   3. All characters encoded must have Unicode scalar values <=
-      0xFFFF, (i.e., characters that would be encoded by surrogates in
-      UTF-16 are  not allowed).  Note that this restriction doesn't
-      apply to the built-in support for UTF-8 and UTF-16.
-
-   4. No Unicode character may be encoded by more than one distinct
-      sequence of bytes.
-*/
-typedef struct {
-  int map[256];
-  void *data;
-  int(XMLCALL *convert)(void *data, const char *s);
-  void(XMLCALL *release)(void *data);
-} XML_Encoding;
-
-/* This is called for an encoding that is unknown to the parser.
-
-   The encodingHandlerData argument is that which was passed as the
-   second argument to XML_SetUnknownEncodingHandler.
-
-   The name argument gives the name of the encoding as specified in
-   the encoding declaration.
-
-   If the callback can provide information about the encoding, it must
-   fill in the XML_Encoding structure, and return XML_STATUS_OK.
-   Otherwise it must return XML_STATUS_ERROR.
-
-   If info does not describe a suitable encoding, then the parser will
-   return an XML_UNKNOWN_ENCODING error.
-*/
-typedef int(XMLCALL *XML_UnknownEncodingHandler)(void *encodingHandlerData,
-                                                 const XML_Char *name,
-                                                 XML_Encoding *info);
-
-XMLPARSEAPI(void)
-XML_SetElementHandler(XML_Parser parser, XML_StartElementHandler start,
-                      XML_EndElementHandler end);
-
-XMLPARSEAPI(void)
-XML_SetStartElementHandler(XML_Parser parser, XML_StartElementHandler handler);
-
-XMLPARSEAPI(void)
-XML_SetEndElementHandler(XML_Parser parser, XML_EndElementHandler handler);
-
-XMLPARSEAPI(void)
-XML_SetCharacterDataHandler(XML_Parser parser,
-                            XML_CharacterDataHandler handler);
-
-XMLPARSEAPI(void)
-XML_SetProcessingInstructionHandler(XML_Parser parser,
-                                    XML_ProcessingInstructionHandler handler);
-XMLPARSEAPI(void)
-XML_SetCommentHandler(XML_Parser parser, XML_CommentHandler handler);
-
-XMLPARSEAPI(void)
-XML_SetCdataSectionHandler(XML_Parser parser,
-                           XML_StartCdataSectionHandler start,
-                           XML_EndCdataSectionHandler end);
-
-XMLPARSEAPI(void)
-XML_SetStartCdataSectionHandler(XML_Parser parser,
-                                XML_StartCdataSectionHandler start);
-
-XMLPARSEAPI(void)
-XML_SetEndCdataSectionHandler(XML_Parser parser,
-                              XML_EndCdataSectionHandler end);
-
-/* This sets the default handler and also inhibits expansion of
-   internal entities. These entity references will be passed to the
-   default handler, or to the skipped entity handler, if one is set.
-*/
-XMLPARSEAPI(void)
-XML_SetDefaultHandler(XML_Parser parser, XML_DefaultHandler handler);
-
-/* This sets the default handler but does not inhibit expansion of
-   internal entities.  The entity reference will not be passed to the
-   default handler.
-*/
-XMLPARSEAPI(void)
-XML_SetDefaultHandlerExpand(XML_Parser parser, XML_DefaultHandler handler);
-
-XMLPARSEAPI(void)
-XML_SetDoctypeDeclHandler(XML_Parser parser, XML_StartDoctypeDeclHandler start,
-                          XML_EndDoctypeDeclHandler end);
-
-XMLPARSEAPI(void)
-XML_SetStartDoctypeDeclHandler(XML_Parser parser,
-                               XML_StartDoctypeDeclHandler start);
-
-XMLPARSEAPI(void)
-XML_SetEndDoctypeDeclHandler(XML_Parser parser, XML_EndDoctypeDeclHandler end);
-
-XMLPARSEAPI(void)
-XML_SetUnparsedEntityDeclHandler(XML_Parser parser,
-                                 XML_UnparsedEntityDeclHandler handler);
-
-XMLPARSEAPI(void)
-XML_SetNotationDeclHandler(XML_Parser parser, XML_NotationDeclHandler handler);
-
-XMLPARSEAPI(void)
-XML_SetNamespaceDeclHandler(XML_Parser parser,
-                            XML_StartNamespaceDeclHandler start,
-                            XML_EndNamespaceDeclHandler end);
-
-XMLPARSEAPI(void)
-XML_SetStartNamespaceDeclHandler(XML_Parser parser,
-                                 XML_StartNamespaceDeclHandler start);
-
-XMLPARSEAPI(void)
-XML_SetEndNamespaceDeclHandler(XML_Parser parser,
-                               XML_EndNamespaceDeclHandler end);
-
-XMLPARSEAPI(void)
-XML_SetNotStandaloneHandler(XML_Parser parser,
-                            XML_NotStandaloneHandler handler);
-
-XMLPARSEAPI(void)
-XML_SetExternalEntityRefHandler(XML_Parser parser,
-                                XML_ExternalEntityRefHandler handler);
-
-/* If a non-NULL value for arg is specified here, then it will be
-   passed as the first argument to the external entity ref handler
-   instead of the parser object.
-*/
-XMLPARSEAPI(void)
-XML_SetExternalEntityRefHandlerArg(XML_Parser parser, void *arg);
-
-XMLPARSEAPI(void)
-XML_SetSkippedEntityHandler(XML_Parser parser,
-                            XML_SkippedEntityHandler handler);
-
-XMLPARSEAPI(void)
-XML_SetUnknownEncodingHandler(XML_Parser parser,
-                              XML_UnknownEncodingHandler handler,
-                              void *encodingHandlerData);
-
-/* This can be called within a handler for a start element, end
-   element, processing instruction or character data.  It causes the
-   corresponding markup to be passed to the default handler.
-*/
-XMLPARSEAPI(void)
-XML_DefaultCurrent(XML_Parser parser);
-
-/* If do_nst is non-zero, and namespace processing is in effect, and
-   a name has a prefix (i.e. an explicit namespace qualifier) then
-   that name is returned as a triplet in a single string separated by
-   the separator character specified when the parser was created: URI
-   + sep + local_name + sep + prefix.
-
-   If do_nst is zero, then namespace information is returned in the
-   default manner (URI + sep + local_name) whether or not the name
-   has a prefix.
-
-   Note: Calling XML_SetReturnNSTriplet after XML_Parse or
-     XML_ParseBuffer has no effect.
-*/
-
-XMLPARSEAPI(void)
-XML_SetReturnNSTriplet(XML_Parser parser, int do_nst);
-
-/* This value is passed as the userData argument to callbacks. */
-XMLPARSEAPI(void)
-XML_SetUserData(XML_Parser parser, void *userData);
-
-/* Returns the last value set by XML_SetUserData or NULL. */
-#define XML_GetUserData(parser) (*(void **)(parser))
-
-/* This is equivalent to supplying an encoding argument to
-   XML_ParserCreate. On success XML_SetEncoding returns non-zero,
-   zero otherwise.
-   Note: Calling XML_SetEncoding after XML_Parse or XML_ParseBuffer
-     has no effect and returns XML_STATUS_ERROR.
-*/
-XMLPARSEAPI(enum XML_Status)
-XML_SetEncoding(XML_Parser parser, const XML_Char *encoding);
-
-/* If this function is called, then the parser will be passed as the
-   first argument to callbacks instead of userData.  The userData will
-   still be accessible using XML_GetUserData.
-*/
-XMLPARSEAPI(void)
-XML_UseParserAsHandlerArg(XML_Parser parser);
-
-/* If useDTD == XML_TRUE is passed to this function, then the parser
-   will assume that there is an external subset, even if none is
-   specified in the document. In such a case the parser will call the
-   externalEntityRefHandler with a value of NULL for the systemId
-   argument (the publicId and context arguments will be NULL as well).
-   Note: For the purpose of checking WFC: Entity Declared, passing
-     useDTD == XML_TRUE will make the parser behave as if the document
-     had a DTD with an external subset.
-   Note: If this function is called, then this must be done before
-     the first call to XML_Parse or XML_ParseBuffer, since it will
-     have no effect after that.  Returns
-     XML_ERROR_CANT_CHANGE_FEATURE_ONCE_PARSING.
-   Note: If the document does not have a DOCTYPE declaration at all,
-     then startDoctypeDeclHandler and endDoctypeDeclHandler will not
-     be called, despite an external subset being parsed.
-   Note: If XML_DTD is not defined when Expat is compiled, returns
-     XML_ERROR_FEATURE_REQUIRES_XML_DTD.
-   Note: If parser == NULL, returns XML_ERROR_INVALID_ARGUMENT.
-*/
-XMLPARSEAPI(enum XML_Error)
-XML_UseForeignDTD(XML_Parser parser, XML_Bool useDTD);
-
-/* Sets the base to be used for resolving relative URIs in system
-   identifiers in declarations.  Resolving relative identifiers is
-   left to the application: this value will be passed through as the
-   base argument to the XML_ExternalEntityRefHandler,
-   XML_NotationDeclHandler and XML_UnparsedEntityDeclHandler. The base
-   argument will be copied.  Returns XML_STATUS_ERROR if out of memory,
-   XML_STATUS_OK otherwise.
-*/
-XMLPARSEAPI(enum XML_Status)
-XML_SetBase(XML_Parser parser, const XML_Char *base);
-
-XMLPARSEAPI(const XML_Char *)
-XML_GetBase(XML_Parser parser);
-
-/* Returns the number of the attribute/value pairs passed in last call
-   to the XML_StartElementHandler that were specified in the start-tag
-   rather than defaulted. Each attribute/value pair counts as 2; thus
-   this correspondds to an index into the atts array passed to the
-   XML_StartElementHandler.  Returns -1 if parser == NULL.
-*/
-XMLPARSEAPI(int)
-XML_GetSpecifiedAttributeCount(XML_Parser parser);
-
-/* Returns the index of the ID attribute passed in the last call to
-   XML_StartElementHandler, or -1 if there is no ID attribute or
-   parser == NULL.  Each attribute/value pair counts as 2; thus this
-   correspondds to an index into the atts array passed to the
-   XML_StartElementHandler.
-*/
-XMLPARSEAPI(int)
-XML_GetIdAttributeIndex(XML_Parser parser);
-
-#ifdef XML_ATTR_INFO
-/* Source file byte offsets for the start and end of attribute names and values.
-   The value indices are exclusive of surrounding quotes; thus in a UTF-8 source
-   file an attribute value of "blah" will yield:
-   info->valueEnd - info->valueStart = 4 bytes.
-*/
-typedef struct {
-  XML_Index nameStart;  /* Offset to beginning of the attribute name. */
-  XML_Index nameEnd;    /* Offset after the attribute name's last byte. */
-  XML_Index valueStart; /* Offset to beginning of the attribute value. */
-  XML_Index valueEnd;   /* Offset after the attribute value's last byte. */
-} XML_AttrInfo;
-
-/* Returns an array of XML_AttrInfo structures for the attribute/value pairs
-   passed in last call to the XML_StartElementHandler that were specified
-   in the start-tag rather than defaulted. Each attribute/value pair counts
-   as 1; thus the number of entries in the array is
-   XML_GetSpecifiedAttributeCount(parser) / 2.
-*/
-XMLPARSEAPI(const XML_AttrInfo *)
-XML_GetAttributeInfo(XML_Parser parser);
-#endif
-
-/* Parses some input. Returns XML_STATUS_ERROR if a fatal error is
-   detected.  The last call to XML_Parse must have isFinal true; len
-   may be zero for this call (or any other).
-
-   Though the return values for these functions has always been
-   described as a Boolean value, the implementation, at least for the
-   1.95.x series, has always returned exactly one of the XML_Status
-   values.
-*/
-XMLPARSEAPI(enum XML_Status)
-XML_Parse(XML_Parser parser, const char *s, int len, int isFinal);
-
-XMLPARSEAPI(void *)
-XML_GetBuffer(XML_Parser parser, int len);
-
-XMLPARSEAPI(enum XML_Status)
-XML_ParseBuffer(XML_Parser parser, int len, int isFinal);
-
-/* Stops parsing, causing XML_Parse() or XML_ParseBuffer() to return.
-   Must be called from within a call-back handler, except when aborting
-   (resumable = 0) an already suspended parser. Some call-backs may
-   still follow because they would otherwise get lost. Examples:
-   - endElementHandler() for empty elements when stopped in
-     startElementHandler(),
-   - endNameSpaceDeclHandler() when stopped in endElementHandler(),
-   and possibly others.
-
-   Can be called from most handlers, including DTD related call-backs,
-   except when parsing an external parameter entity and resumable != 0.
-   Returns XML_STATUS_OK when successful, XML_STATUS_ERROR otherwise.
-   Possible error codes:
-   - XML_ERROR_SUSPENDED: when suspending an already suspended parser.
-   - XML_ERROR_FINISHED: when the parser has already finished.
-   - XML_ERROR_SUSPEND_PE: when suspending while parsing an external PE.
-
-   When resumable != 0 (true) then parsing is suspended, that is,
-   XML_Parse() and XML_ParseBuffer() return XML_STATUS_SUSPENDED.
-   Otherwise, parsing is aborted, that is, XML_Parse() and XML_ParseBuffer()
-   return XML_STATUS_ERROR with error code XML_ERROR_ABORTED.
-
-   *Note*:
-   This will be applied to the current parser instance only, that is, if
-   there is a parent parser then it will continue parsing when the
-   externalEntityRefHandler() returns. It is up to the implementation of
-   the externalEntityRefHandler() to call XML_StopParser() on the parent
-   parser (recursively), if one wants to stop parsing altogether.
-
-   When suspended, parsing can be resumed by calling XML_ResumeParser().
-*/
-XMLPARSEAPI(enum XML_Status)
-XML_StopParser(XML_Parser parser, XML_Bool resumable);
-
-/* Resumes parsing after it has been suspended with XML_StopParser().
-   Must not be called from within a handler call-back. Returns same
-   status codes as XML_Parse() or XML_ParseBuffer().
-   Additional error code XML_ERROR_NOT_SUSPENDED possible.
-
-   *Note*:
-   This must be called on the most deeply nested child parser instance
-   first, and on its parent parser only after the child parser has finished,
-   to be applied recursively until the document entity's parser is restarted.
-   That is, the parent parser will not resume by itself and it is up to the
-   application to call XML_ResumeParser() on it at the appropriate moment.
-*/
-XMLPARSEAPI(enum XML_Status)
-XML_ResumeParser(XML_Parser parser);
-
-enum XML_Parsing { XML_INITIALIZED, XML_PARSING, XML_FINISHED, XML_SUSPENDED };
-
-typedef struct {
-  enum XML_Parsing parsing;
-  XML_Bool finalBuffer;
-} XML_ParsingStatus;
-
-/* Returns status of parser with respect to being initialized, parsing,
-   finished, or suspended and processing the final buffer.
-   XXX XML_Parse() and XML_ParseBuffer() should return XML_ParsingStatus,
-   XXX with XML_FINISHED_OK or XML_FINISHED_ERROR replacing XML_FINISHED
-*/
-XMLPARSEAPI(void)
-XML_GetParsingStatus(XML_Parser parser, XML_ParsingStatus *status);
-
-/* Creates an XML_Parser object that can parse an external general
-   entity; context is a '\0'-terminated string specifying the parse
-   context; encoding is a '\0'-terminated string giving the name of
-   the externally specified encoding, or NULL if there is no
-   externally specified encoding.  The context string consists of a
-   sequence of tokens separated by formfeeds (\f); a token consisting
-   of a name specifies that the general entity of the name is open; a
-   token of the form prefix=uri specifies the namespace for a
-   particular prefix; a token of the form =uri specifies the default
-   namespace.  This can be called at any point after the first call to
-   an ExternalEntityRefHandler so longer as the parser has not yet
-   been freed.  The new parser is completely independent and may
-   safely be used in a separate thread.  The handlers and userData are
-   initialized from the parser argument.  Returns NULL if out of memory.
-   Otherwise returns a new XML_Parser object.
-*/
-XMLPARSEAPI(XML_Parser)
-XML_ExternalEntityParserCreate(XML_Parser parser, const XML_Char *context,
-                               const XML_Char *encoding);
-
-enum XML_ParamEntityParsing {
-  XML_PARAM_ENTITY_PARSING_NEVER,
-  XML_PARAM_ENTITY_PARSING_UNLESS_STANDALONE,
-  XML_PARAM_ENTITY_PARSING_ALWAYS
-};
-
-/* Controls parsing of parameter entities (including the external DTD
-   subset). If parsing of parameter entities is enabled, then
-   references to external parameter entities (including the external
-   DTD subset) will be passed to the handler set with
-   XML_SetExternalEntityRefHandler.  The context passed will be 0.
-
-   Unlike external general entities, external parameter entities can
-   only be parsed synchronously.  If the external parameter entity is
-   to be parsed, it must be parsed during the call to the external
-   entity ref handler: the complete sequence of
-   XML_ExternalEntityParserCreate, XML_Parse/XML_ParseBuffer and
-   XML_ParserFree calls must be made during this call.  After
-   XML_ExternalEntityParserCreate has been called to create the parser
-   for the external parameter entity (context must be 0 for this
-   call), it is illegal to make any calls on the old parser until
-   XML_ParserFree has been called on the newly created parser.
-   If the library has been compiled without support for parameter
-   entity parsing (ie without XML_DTD being defined), then
-   XML_SetParamEntityParsing will return 0 if parsing of parameter
-   entities is requested; otherwise it will return non-zero.
-   Note: If XML_SetParamEntityParsing is called after XML_Parse or
-      XML_ParseBuffer, then it has no effect and will always return 0.
-   Note: If parser == NULL, the function will do nothing and return 0.
-*/
-XMLPARSEAPI(int)
-XML_SetParamEntityParsing(XML_Parser parser,
-                          enum XML_ParamEntityParsing parsing);
-
-/* Sets the hash salt to use for internal hash calculations.
-   Helps in preventing DoS attacks based on predicting hash
-   function behavior. This must be called before parsing is started.
-   Returns 1 if successful, 0 when called after parsing has started.
-   Note: If parser == NULL, the function will do nothing and return 0.
-*/
-XMLPARSEAPI(int)
-XML_SetHashSalt(XML_Parser parser, unsigned long hash_salt);
-
-/* If XML_Parse or XML_ParseBuffer have returned XML_STATUS_ERROR, then
-   XML_GetErrorCode returns information about the error.
-*/
-XMLPARSEAPI(enum XML_Error)
-XML_GetErrorCode(XML_Parser parser);
-
-/* These functions return information about the current parse
-   location.  They may be called from any callback called to report
-   some parse event; in this case the location is the location of the
-   first of the sequence of characters that generated the event.  When
-   called from callbacks generated by declarations in the document
-   prologue, the location identified isn't as neatly defined, but will
-   be within the relevant markup.  When called outside of the callback
-   functions, the position indicated will be just past the last parse
-   event (regardless of whether there was an associated callback).
-
-   They may also be called after returning from a call to XML_Parse
-   or XML_ParseBuffer.  If the return value is XML_STATUS_ERROR then
-   the location is the location of the character at which the error
-   was detected; otherwise the location is the location of the last
-   parse event, as described above.
-
-   Note: XML_GetCurrentLineNumber and XML_GetCurrentColumnNumber
-   return 0 to indicate an error.
-   Note: XML_GetCurrentByteIndex returns -1 to indicate an error.
-*/
-XMLPARSEAPI(XML_Size) XML_GetCurrentLineNumber(XML_Parser parser);
-XMLPARSEAPI(XML_Size) XML_GetCurrentColumnNumber(XML_Parser parser);
-XMLPARSEAPI(XML_Index) XML_GetCurrentByteIndex(XML_Parser parser);
-
-/* Return the number of bytes in the current event.
-   Returns 0 if the event is in an internal entity.
-*/
-XMLPARSEAPI(int)
-XML_GetCurrentByteCount(XML_Parser parser);
-
-/* If XML_CONTEXT_BYTES is defined, returns the input buffer, sets
-   the integer pointed to by offset to the offset within this buffer
-   of the current parse position, and sets the integer pointed to by size
-   to the size of this buffer (the number of input bytes). Otherwise
-   returns a NULL pointer. Also returns a NULL pointer if a parse isn't
-   active.
-
-   NOTE: The character pointer returned should not be used outside
-   the handler that makes the call.
-*/
-XMLPARSEAPI(const char *)
-XML_GetInputContext(XML_Parser parser, int *offset, int *size);
-
-/* For backwards compatibility with previous versions. */
-#define XML_GetErrorLineNumber XML_GetCurrentLineNumber
-#define XML_GetErrorColumnNumber XML_GetCurrentColumnNumber
-#define XML_GetErrorByteIndex XML_GetCurrentByteIndex
-
-/* Frees the content model passed to the element declaration handler */
-XMLPARSEAPI(void)
-XML_FreeContentModel(XML_Parser parser, XML_Content *model);
-
-/* Exposing the memory handling functions used in Expat */
-XMLPARSEAPI(void *)
-XML_ATTR_MALLOC
-XML_ATTR_ALLOC_SIZE(2)
-XML_MemMalloc(XML_Parser parser, size_t size);
-
-XMLPARSEAPI(void *)
-XML_ATTR_ALLOC_SIZE(3)
-XML_MemRealloc(XML_Parser parser, void *ptr, size_t size);
-
-XMLPARSEAPI(void)
-XML_MemFree(XML_Parser parser, void *ptr);
-
-/* Frees memory used by the parser. */
-XMLPARSEAPI(void)
-XML_ParserFree(XML_Parser parser);
-
-/* Returns a string describing the error. */
-XMLPARSEAPI(const XML_LChar *)
-XML_ErrorString(enum XML_Error code);
-
-/* Return a string containing the version number of this expat */
-XMLPARSEAPI(const XML_LChar *)
-XML_ExpatVersion(void);
-
-typedef struct {
-  int major;
-  int minor;
-  int micro;
-} XML_Expat_Version;
-
-/* Return an XML_Expat_Version structure containing numeric version
-   number information for this version of expat.
-*/
-XMLPARSEAPI(XML_Expat_Version)
-XML_ExpatVersionInfo(void);
-
-/* Added in Expat 1.95.5. */
-enum XML_FeatureEnum {
-  XML_FEATURE_END = 0,
-  XML_FEATURE_UNICODE,
-  XML_FEATURE_UNICODE_WCHAR_T,
-  XML_FEATURE_DTD,
-  XML_FEATURE_CONTEXT_BYTES,
-  XML_FEATURE_MIN_SIZE,
-  XML_FEATURE_SIZEOF_XML_CHAR,
-  XML_FEATURE_SIZEOF_XML_LCHAR,
-  XML_FEATURE_NS,
-  XML_FEATURE_LARGE_SIZE,
-  XML_FEATURE_ATTR_INFO
-  /* Additional features must be added to the end of this enum. */
-};
-
-typedef struct {
-  enum XML_FeatureEnum feature;
-  const XML_LChar *name;
-  long int value;
-} XML_Feature;
-
-XMLPARSEAPI(const XML_Feature *)
-XML_GetFeatureList(void);
-
-/* Expat follows the semantic versioning convention.
-   See http://semver.org.
-*/
-#define XML_MAJOR_VERSION 2
-#define XML_MINOR_VERSION 2
-#define XML_MICRO_VERSION 9
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* not Expat_INCLUDED */
diff --git a/tools/sdk/include/expat/expat_config.h b/tools/sdk/include/expat/expat_config.h
deleted file mode 100644
index b6b927a19bb..00000000000
--- a/tools/sdk/include/expat/expat_config.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* expat_config.h.  Generated from expat_config.h.in by configure.  */
-/* expat_config.h.in.  Generated from configure.ac by autoheader.  */
-
-/* 1234 = LIL_ENDIAN, 4321 = BIGENDIAN */
-#define BYTEORDER 1234
-/* Define to 1 if you have the `bcopy' function. */
-#define HAVE_BCOPY 1
-
-/* Define to 1 if you have the <dlfcn.h> header file. */
-#define HAVE_DLFCN_H 1
-
-/* Define to 1 if you have the <fcntl.h> header file. */
-#define HAVE_FCNTL_H 1
-
-/* Define to 1 if you have the `getpagesize' function. */
-#define HAVE_GETPAGESIZE 1
-/* Define to 1 if you have the <inttypes.h> header file. */
-#define HAVE_INTTYPES_H 1
-
-/* Define to 1 if you have the `memmove' function. */
-#define HAVE_MEMMOVE 1
-
-/* Define to 1 if you have the <memory.h> header file. */
-#define HAVE_MEMORY_H 1
-
-/* Define to 1 if you have a working `mmap' system call. */
-#define HAVE_MMAP 1
-
-/* Define to 1 if you have the <stdint.h> header file. */
-#define HAVE_STDINT_H 1
-
-/* Define to 1 if you have the <stdlib.h> header file. */
-#define HAVE_STDLIB_H 1
-
-/* Define to 1 if you have the <strings.h> header file. */
-#define HAVE_STRINGS_H 1
-
-/* Define to 1 if you have the <string.h> header file. */
-#define HAVE_STRING_H 1
-
-/* Define to 1 if you have the <sys/param.h> header file. */
-#define HAVE_SYS_PARAM_H 1
-
-/* Define to 1 if you have the <sys/stat.h> header file. */
-#define HAVE_SYS_STAT_H 1
-
-/* Define to 1 if you have the <sys/types.h> header file. */
-#define HAVE_SYS_TYPES_H 1
-
-/* Define to 1 if you have the <unistd.h> header file. */
-#define HAVE_UNISTD_H 1
-
-/* Define to the sub-directory where libtool stores uninstalled libraries. */
-#define LT_OBJDIR ".libs/"
-
-/* Name of package */
-#define PACKAGE "expat"
-
-/* Define to the address where bug reports for this package should be sent. */
-#define PACKAGE_BUGREPORT "expat-bugs@libexpat.org"
-
-/* Define to the full name of this package. */
-#define PACKAGE_NAME "expat"
-
-/* Define to the full name and version of this package. */
-#define PACKAGE_STRING "expat 2.2.5"
-
-/* Define to the one symbol short name of this package. */
-#define PACKAGE_TARNAME "expat"
-
-/* Define to the home page for this package. */
-#define PACKAGE_URL ""
-
-/* Define to the version of this package. */
-#define PACKAGE_VERSION "2.2.5"
-
-/* Define to 1 if you have the ANSI C header files. */
-#define STDC_HEADERS 1
-
-/* Version number of package */
-#define VERSION "2.2.5"
-
-/* whether byteorder is bigendian */
-/* #undef WORDS_BIGENDIAN */
-
-/* Define to specify how much context to retain around the current parse
-   point. */
-#define XML_CONTEXT_BYTES 1024
-
-/* Define to make parameter entity parsing functionality available. */
-#define XML_DTD 1
-
-/* Define to make XML Namespaces functionality available. */
-#define XML_NS 1
-
-/* Define to empty if `const' does not conform to ANSI C. */
-/* #undef const */
-
-/* Define to `long int' if <sys/types.h> does not define. */
-/* #undef off_t */
-
-/* Define to `unsigned int' if <sys/types.h> does not define. */
-/* #undef size_t */
diff --git a/tools/sdk/include/expat/expat_external.h b/tools/sdk/include/expat/expat_external.h
deleted file mode 100644
index b3b6e74d9d2..00000000000
--- a/tools/sdk/include/expat/expat_external.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef Expat_External_INCLUDED
-#define Expat_External_INCLUDED 1
-
-/* External API definitions */
-
-/* Expat tries very hard to make the API boundary very specifically
-   defined.  There are two macros defined to control this boundary;
-   each of these can be defined before including this header to
-   achieve some different behavior, but doing so it not recommended or
-   tested frequently.
-
-   XMLCALL    - The calling convention to use for all calls across the
-                "library boundary."  This will default to cdecl, and
-                try really hard to tell the compiler that's what we
-                want.
-
-   XMLIMPORT  - Whatever magic is needed to note that a function is
-                to be imported from a dynamically loaded library
-                (.dll, .so, or .sl, depending on your platform).
-
-   The XMLCALL macro was added in Expat 1.95.7.  The only one which is
-   expected to be directly useful in client code is XMLCALL.
-
-   Note that on at least some Unix versions, the Expat library must be
-   compiled with the cdecl calling convention as the default since
-   system headers may assume the cdecl convention.
-*/
-#ifndef XMLCALL
-#  if defined(_MSC_VER)
-#    define XMLCALL __cdecl
-#  elif defined(__GNUC__) && defined(__i386) && ! defined(__INTEL_COMPILER)
-#    define XMLCALL __attribute__((cdecl))
-#  else
-/* For any platform which uses this definition and supports more than
-   one calling convention, we need to extend this definition to
-   declare the convention used on that platform, if it's possible to
-   do so.
-
-   If this is the case for your platform, please file a bug report
-   with information on how to identify your platform via the C
-   pre-processor and how to specify the same calling convention as the
-   platform's malloc() implementation.
-*/
-#    define XMLCALL
-#  endif
-#endif /* not defined XMLCALL */
-
-#if ! defined(XML_STATIC) && ! defined(XMLIMPORT)
-#  ifndef XML_BUILDING_EXPAT
-/* using Expat from an application */
-
-#    if defined(_MSC_EXTENSIONS) && ! defined(__BEOS__) && ! defined(__CYGWIN__)
-#      define XMLIMPORT __declspec(dllimport)
-#    endif
-
-#  endif
-#endif /* not defined XML_STATIC */
-
-#ifndef XML_ENABLE_VISIBILITY
-#  define XML_ENABLE_VISIBILITY 0
-#endif
-
-#if ! defined(XMLIMPORT) && XML_ENABLE_VISIBILITY
-#  define XMLIMPORT __attribute__((visibility("default")))
-#endif
-
-/* If we didn't define it above, define it away: */
-#ifndef XMLIMPORT
-#  define XMLIMPORT
-#endif
-
-#if defined(__GNUC__)                                                          \
-    && (__GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 96))
-#  define XML_ATTR_MALLOC __attribute__((__malloc__))
-#else
-#  define XML_ATTR_MALLOC
-#endif
-
-#if defined(__GNUC__)                                                          \
-    && ((__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3))
-#  define XML_ATTR_ALLOC_SIZE(x) __attribute__((__alloc_size__(x)))
-#else
-#  define XML_ATTR_ALLOC_SIZE(x)
-#endif
-
-#define XMLPARSEAPI(type) XMLIMPORT type XMLCALL
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef XML_UNICODE_WCHAR_T
-#  ifndef XML_UNICODE
-#    define XML_UNICODE
-#  endif
-#  if defined(__SIZEOF_WCHAR_T__) && (__SIZEOF_WCHAR_T__ != 2)
-#    error "sizeof(wchar_t) != 2; Need -fshort-wchar for both Expat and libc"
-#  endif
-#endif
-
-#ifdef XML_UNICODE /* Information is UTF-16 encoded. */
-#  ifdef XML_UNICODE_WCHAR_T
-typedef wchar_t XML_Char;
-typedef wchar_t XML_LChar;
-#  else
-typedef unsigned short XML_Char;
-typedef char XML_LChar;
-#  endif /* XML_UNICODE_WCHAR_T */
-#else    /* Information is UTF-8 encoded. */
-typedef char XML_Char;
-typedef char XML_LChar;
-#endif   /* XML_UNICODE */
-
-#ifdef XML_LARGE_SIZE /* Use large integers for file/stream positions. */
-typedef long long XML_Index;
-typedef unsigned long long XML_Size;
-#else
-typedef long XML_Index;
-typedef unsigned long XML_Size;
-#endif /* XML_LARGE_SIZE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* not Expat_External_INCLUDED */
diff --git a/tools/sdk/include/expat/iasciitab.h b/tools/sdk/include/expat/iasciitab.h
deleted file mode 100644
index ea97cfcf678..00000000000
--- a/tools/sdk/include/expat/iasciitab.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/* Like asciitab.h, except that 0xD has code BT_S rather than BT_CR */
-/* 0x00 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x04 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x08 */ BT_NONXML, BT_S, BT_LF, BT_NONXML,
-    /* 0x0C */ BT_NONXML, BT_S, BT_NONXML, BT_NONXML,
-    /* 0x10 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x14 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x18 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x1C */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0x20 */ BT_S, BT_EXCL, BT_QUOT, BT_NUM,
-    /* 0x24 */ BT_OTHER, BT_PERCNT, BT_AMP, BT_APOS,
-    /* 0x28 */ BT_LPAR, BT_RPAR, BT_AST, BT_PLUS,
-    /* 0x2C */ BT_COMMA, BT_MINUS, BT_NAME, BT_SOL,
-    /* 0x30 */ BT_DIGIT, BT_DIGIT, BT_DIGIT, BT_DIGIT,
-    /* 0x34 */ BT_DIGIT, BT_DIGIT, BT_DIGIT, BT_DIGIT,
-    /* 0x38 */ BT_DIGIT, BT_DIGIT, BT_COLON, BT_SEMI,
-    /* 0x3C */ BT_LT, BT_EQUALS, BT_GT, BT_QUEST,
-    /* 0x40 */ BT_OTHER, BT_HEX, BT_HEX, BT_HEX,
-    /* 0x44 */ BT_HEX, BT_HEX, BT_HEX, BT_NMSTRT,
-    /* 0x48 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x4C */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x50 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x54 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x58 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_LSQB,
-    /* 0x5C */ BT_OTHER, BT_RSQB, BT_OTHER, BT_NMSTRT,
-    /* 0x60 */ BT_OTHER, BT_HEX, BT_HEX, BT_HEX,
-    /* 0x64 */ BT_HEX, BT_HEX, BT_HEX, BT_NMSTRT,
-    /* 0x68 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x6C */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x70 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x74 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0x78 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_OTHER,
-    /* 0x7C */ BT_VERBAR, BT_OTHER, BT_OTHER, BT_OTHER,
diff --git a/tools/sdk/include/expat/internal.h b/tools/sdk/include/expat/internal.h
deleted file mode 100644
index 60913dab762..00000000000
--- a/tools/sdk/include/expat/internal.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* internal.h
-
-   Internal definitions used by Expat.  This is not needed to compile
-   client code.
-
-   The following calling convention macros are defined for frequently
-   called functions:
-
-   FASTCALL    - Used for those internal functions that have a simple
-                 body and a low number of arguments and local variables.
-
-   PTRCALL     - Used for functions called though function pointers.
-
-   PTRFASTCALL - Like PTRCALL, but for low number of arguments.
-
-   inline      - Used for selected internal functions for which inlining
-                 may improve performance on some platforms.
-
-   Note: Use of these macros is based on judgement, not hard rules,
-         and therefore subject to change.
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#if defined(__GNUC__) && defined(__i386__) && ! defined(__MINGW32__)
-/* We'll use this version by default only where we know it helps.
-
-   regparm() generates warnings on Solaris boxes.   See SF bug #692878.
-
-   Instability reported with egcs on a RedHat Linux 7.3.
-   Let's comment out:
-   #define FASTCALL __attribute__((stdcall, regparm(3)))
-   and let's try this:
-*/
-#  define FASTCALL __attribute__((regparm(3)))
-#  define PTRFASTCALL __attribute__((regparm(3)))
-#endif
-
-/* Using __fastcall seems to have an unexpected negative effect under
-   MS VC++, especially for function pointers, so we won't use it for
-   now on that platform. It may be reconsidered for a future release
-   if it can be made more effective.
-   Likely reason: __fastcall on Windows is like stdcall, therefore
-   the compiler cannot perform stack optimizations for call clusters.
-*/
-
-/* Make sure all of these are defined if they aren't already. */
-
-#ifndef FASTCALL
-#  define FASTCALL
-#endif
-
-#ifndef PTRCALL
-#  define PTRCALL
-#endif
-
-#ifndef PTRFASTCALL
-#  define PTRFASTCALL
-#endif
-
-#ifndef XML_MIN_SIZE
-#  if ! defined(__cplusplus) && ! defined(inline)
-#    ifdef __GNUC__
-#      define inline __inline
-#    endif /* __GNUC__ */
-#  endif
-#endif /* XML_MIN_SIZE */
-
-#ifdef __cplusplus
-#  define inline inline
-#else
-#  ifndef inline
-#    define inline
-#  endif
-#endif
-
-#ifndef UNUSED_P
-#  define UNUSED_P(p) (void)p
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef XML_ENABLE_VISIBILITY
-#  if XML_ENABLE_VISIBILITY
-__attribute__((visibility("default")))
-#  endif
-#endif
-void
-_INTERNAL_trim_to_complete_utf8_characters(const char *from,
-                                           const char **fromLimRef);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/expat/latin1tab.h b/tools/sdk/include/expat/latin1tab.h
deleted file mode 100644
index 6f916041355..00000000000
--- a/tools/sdk/include/expat/latin1tab.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/* 0x80 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0x84 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0x88 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0x8C */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0x90 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0x94 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0x98 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0x9C */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0xA0 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0xA4 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0xA8 */ BT_OTHER, BT_OTHER, BT_NMSTRT, BT_OTHER,
-    /* 0xAC */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0xB0 */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0xB4 */ BT_OTHER, BT_NMSTRT, BT_OTHER, BT_NAME,
-    /* 0xB8 */ BT_OTHER, BT_OTHER, BT_NMSTRT, BT_OTHER,
-    /* 0xBC */ BT_OTHER, BT_OTHER, BT_OTHER, BT_OTHER,
-    /* 0xC0 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xC4 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xC8 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xCC */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xD0 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xD4 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_OTHER,
-    /* 0xD8 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xDC */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xE0 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xE4 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xE8 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xEC */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xF0 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xF4 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_OTHER,
-    /* 0xF8 */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
-    /* 0xFC */ BT_NMSTRT, BT_NMSTRT, BT_NMSTRT, BT_NMSTRT,
diff --git a/tools/sdk/include/expat/nametab.h b/tools/sdk/include/expat/nametab.h
deleted file mode 100644
index 3681df348ee..00000000000
--- a/tools/sdk/include/expat/nametab.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-static const unsigned namingBitmap[] = {
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x04000000,
-    0x87FFFFFE, 0x07FFFFFE, 0x00000000, 0x00000000, 0xFF7FFFFF, 0xFF7FFFFF,
-    0xFFFFFFFF, 0x7FF3FFFF, 0xFFFFFDFE, 0x7FFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-    0xFFFFE00F, 0xFC31FFFF, 0x00FFFFFF, 0x00000000, 0xFFFF0000, 0xFFFFFFFF,
-    0xFFFFFFFF, 0xF80001FF, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0xFFFFD740, 0xFFFFFFFB, 0x547F7FFF, 0x000FFFFD,
-    0xFFFFDFFE, 0xFFFFFFFF, 0xDFFEFFFF, 0xFFFFFFFF, 0xFFFF0003, 0xFFFFFFFF,
-    0xFFFF199F, 0x033FCFFF, 0x00000000, 0xFFFE0000, 0x027FFFFF, 0xFFFFFFFE,
-    0x0000007F, 0x00000000, 0xFFFF0000, 0x000707FF, 0x00000000, 0x07FFFFFE,
-    0x000007FE, 0xFFFE0000, 0xFFFFFFFF, 0x7CFFFFFF, 0x002F7FFF, 0x00000060,
-    0xFFFFFFE0, 0x23FFFFFF, 0xFF000000, 0x00000003, 0xFFF99FE0, 0x03C5FDFF,
-    0xB0000000, 0x00030003, 0xFFF987E0, 0x036DFDFF, 0x5E000000, 0x001C0000,
-    0xFFFBAFE0, 0x23EDFDFF, 0x00000000, 0x00000001, 0xFFF99FE0, 0x23CDFDFF,
-    0xB0000000, 0x00000003, 0xD63DC7E0, 0x03BFC718, 0x00000000, 0x00000000,
-    0xFFFDDFE0, 0x03EFFDFF, 0x00000000, 0x00000003, 0xFFFDDFE0, 0x03EFFDFF,
-    0x40000000, 0x00000003, 0xFFFDDFE0, 0x03FFFDFF, 0x00000000, 0x00000003,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xFFFFFFFE, 0x000D7FFF,
-    0x0000003F, 0x00000000, 0xFEF02596, 0x200D6CAE, 0x0000001F, 0x00000000,
-    0x00000000, 0x00000000, 0xFFFFFEFF, 0x000003FF, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0xFFFFFFFF, 0xFFFF003F, 0x007FFFFF, 0x0007DAED, 0x50000000,
-    0x82315001, 0x002C62AB, 0x40000000, 0xF580C900, 0x00000007, 0x02010800,
-    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0FFFFFFF, 0xFFFFFFFF,
-    0xFFFFFFFF, 0x03FFFFFF, 0x3F3FFFFF, 0xFFFFFFFF, 0xAAFF3F3F, 0x3FFFFFFF,
-    0xFFFFFFFF, 0x5FDFFFFF, 0x0FCF1FDC, 0x1FDC1FFF, 0x00000000, 0x00004C40,
-    0x00000000, 0x00000000, 0x00000007, 0x00000000, 0x00000000, 0x00000000,
-    0x00000080, 0x000003FE, 0xFFFFFFFE, 0xFFFFFFFF, 0x001FFFFF, 0xFFFFFFFE,
-    0xFFFFFFFF, 0x07FFFFFF, 0xFFFFFFE0, 0x00001FFF, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000003F, 0x00000000, 0x00000000,
-    0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F,
-    0x00000000, 0x00000000, 0x00000000, 0x07FF6000, 0x87FFFFFE, 0x07FFFFFE,
-    0x00000000, 0x00800000, 0xFF7FFFFF, 0xFF7FFFFF, 0x00FFFFFF, 0x00000000,
-    0xFFFF0000, 0xFFFFFFFF, 0xFFFFFFFF, 0xF80001FF, 0x00030003, 0x00000000,
-    0xFFFFFFFF, 0xFFFFFFFF, 0x0000003F, 0x00000003, 0xFFFFD7C0, 0xFFFFFFFB,
-    0x547F7FFF, 0x000FFFFD, 0xFFFFDFFE, 0xFFFFFFFF, 0xDFFEFFFF, 0xFFFFFFFF,
-    0xFFFF007B, 0xFFFFFFFF, 0xFFFF199F, 0x033FCFFF, 0x00000000, 0xFFFE0000,
-    0x027FFFFF, 0xFFFFFFFE, 0xFFFE007F, 0xBBFFFFFB, 0xFFFF0016, 0x000707FF,
-    0x00000000, 0x07FFFFFE, 0x0007FFFF, 0xFFFF03FF, 0xFFFFFFFF, 0x7CFFFFFF,
-    0xFFEF7FFF, 0x03FF3DFF, 0xFFFFFFEE, 0xF3FFFFFF, 0xFF1E3FFF, 0x0000FFCF,
-    0xFFF99FEE, 0xD3C5FDFF, 0xB080399F, 0x0003FFCF, 0xFFF987E4, 0xD36DFDFF,
-    0x5E003987, 0x001FFFC0, 0xFFFBAFEE, 0xF3EDFDFF, 0x00003BBF, 0x0000FFC1,
-    0xFFF99FEE, 0xF3CDFDFF, 0xB0C0398F, 0x0000FFC3, 0xD63DC7EC, 0xC3BFC718,
-    0x00803DC7, 0x0000FF80, 0xFFFDDFEE, 0xC3EFFDFF, 0x00603DDF, 0x0000FFC3,
-    0xFFFDDFEC, 0xC3EFFDFF, 0x40603DDF, 0x0000FFC3, 0xFFFDDFEC, 0xC3FFFDFF,
-    0x00803DCF, 0x0000FFC3, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0xFFFFFFFE, 0x07FF7FFF, 0x03FF7FFF, 0x00000000, 0xFEF02596, 0x3BFF6CAE,
-    0x03FF3F5F, 0x00000000, 0x03000000, 0xC2A003FF, 0xFFFFFEFF, 0xFFFE03FF,
-    0xFEBF0FDF, 0x02FE3FFF, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1FFF0000, 0x00000002,
-    0x000000A0, 0x003EFFFE, 0xFFFFFFFE, 0xFFFFFFFF, 0x661FFFFF, 0xFFFFFFFE,
-    0xFFFFFFFF, 0x77FFFFFF,
-};
-static const unsigned char nmstrtPages[] = {
-    0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x00, 0x00, 0x09, 0x0A, 0x0B,
-    0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x13, 0x00, 0x14, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x15, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x18,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00,
-};
-static const unsigned char namePages[] = {
-    0x19, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x00, 0x00, 0x1F, 0x20, 0x21,
-    0x22, 0x23, 0x24, 0x25, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x13, 0x26, 0x14, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x27, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-    0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x18,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00,
-};
diff --git a/tools/sdk/include/expat/siphash.h b/tools/sdk/include/expat/siphash.h
deleted file mode 100644
index bfee65a332f..00000000000
--- a/tools/sdk/include/expat/siphash.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/* ==========================================================================
- * siphash.h - SipHash-2-4 in a single header file
- * --------------------------------------------------------------------------
- * Derived by William Ahern from the reference implementation[1] published[2]
- * by Jean-Philippe Aumasson and Daniel J. Berstein.
- * Minimal changes by Sebastian Pipping and Victor Stinner on top, see below.
- * Licensed under the CC0 Public Domain Dedication license.
- *
- * 1. https://www.131002.net/siphash/siphash24.c
- * 2. https://www.131002.net/siphash/
- * --------------------------------------------------------------------------
- * HISTORY:
- *
- * 2019-08-03  (Sebastian Pipping)
- *   - Mark part of sip24_valid as to be excluded from clang-format
- *   - Re-format code using clang-format 9
- *
- * 2018-07-08  (Anton Maklakov)
- *   - Add "fall through" markers for GCC's -Wimplicit-fallthrough
- *
- * 2017-11-03  (Sebastian Pipping)
- *   - Hide sip_tobin and sip_binof unless SIPHASH_TOBIN macro is defined
- *
- * 2017-07-25  (Vadim Zeitlin)
- *   - Fix use of SIPHASH_MAIN macro
- *
- * 2017-07-05  (Sebastian Pipping)
- *   - Use _SIP_ULL macro to not require a C++11 compiler if compiled as C++
- *   - Add const qualifiers at two places
- *   - Ensure <=80 characters line length (assuming tab width 4)
- *
- * 2017-06-23  (Victor Stinner)
- *   - Address Win64 compile warnings
- *
- * 2017-06-18  (Sebastian Pipping)
- *   - Clarify license note in the header
- *   - Address C89 issues:
- *     - Stop using inline keyword (and let compiler decide)
- *     - Replace _Bool by int
- *     - Turn macro siphash24 into a function
- *     - Address invalid conversion (void pointer) by explicit cast
- *   - Address lack of stdint.h for Visual Studio 2003 to 2008
- *   - Always expose sip24_valid (for self-tests)
- *
- * 2012-11-04 - Born.  (William Ahern)
- * --------------------------------------------------------------------------
- * USAGE:
- *
- * SipHash-2-4 takes as input two 64-bit words as the key, some number of
- * message bytes, and outputs a 64-bit word as the message digest. This
- * implementation employs two data structures: a struct sipkey for
- * representing the key, and a struct siphash for representing the hash
- * state.
- *
- * For converting a 16-byte unsigned char array to a key, use either the
- * macro sip_keyof or the routine sip_tokey. The former instantiates a
- * compound literal key, while the latter requires a key object as a
- * parameter.
- *
- * 	unsigned char secret[16];
- * 	arc4random_buf(secret, sizeof secret);
- * 	struct sipkey *key = sip_keyof(secret);
- *
- * For hashing a message, use either the convenience macro siphash24 or the
- * routines sip24_init, sip24_update, and sip24_final.
- *
- * 	struct siphash state;
- * 	void *msg;
- * 	size_t len;
- * 	uint64_t hash;
- *
- * 	sip24_init(&state, key);
- * 	sip24_update(&state, msg, len);
- * 	hash = sip24_final(&state);
- *
- * or
- *
- * 	hash = siphash24(msg, len, key);
- *
- * To convert the 64-bit hash value to a canonical 8-byte little-endian
- * binary representation, use either the macro sip_binof or the routine
- * sip_tobin. The former instantiates and returns a compound literal array,
- * while the latter requires an array object as a parameter.
- * --------------------------------------------------------------------------
- * NOTES:
- *
- * o Neither sip_keyof, sip_binof, nor siphash24 will work with compilers
- *   lacking compound literal support. Instead, you must use the lower-level
- *   interfaces which take as parameters the temporary state objects.
- *
- * o Uppercase macros may evaluate parameters more than once. Lowercase
- *   macros should not exhibit any such side effects.
- * ==========================================================================
- */
-#ifndef SIPHASH_H
-#define SIPHASH_H
-
-#include <stddef.h> /* size_t */
-
-#if defined(_WIN32) && defined(_MSC_VER) && (_MSC_VER < 1600)
-/* For vs2003/7.1 up to vs2008/9.0; _MSC_VER 1600 is vs2010/10.0 */
-typedef unsigned __int8 uint8_t;
-typedef unsigned __int32 uint32_t;
-typedef unsigned __int64 uint64_t;
-#else
-#  include <stdint.h> /* uint64_t uint32_t uint8_t */
-#endif
-
-/*
- * Workaround to not require a C++11 compiler for using ULL suffix
- * if this code is included and compiled as C++; related GCC warning is:
- * warning: use of C++11 long long integer constant [-Wlong-long]
- */
-#define _SIP_ULL(high, low) (((uint64_t)high << 32) | low)
-
-#define SIP_ROTL(x, b) (uint64_t)(((x) << (b)) | ((x) >> (64 - (b))))
-
-#define SIP_U32TO8_LE(p, v)                                                    \
-  (p)[0] = (uint8_t)((v) >> 0);                                                \
-  (p)[1] = (uint8_t)((v) >> 8);                                                \
-  (p)[2] = (uint8_t)((v) >> 16);                                               \
-  (p)[3] = (uint8_t)((v) >> 24);
-
-#define SIP_U64TO8_LE(p, v)                                                    \
-  SIP_U32TO8_LE((p) + 0, (uint32_t)((v) >> 0));                                \
-  SIP_U32TO8_LE((p) + 4, (uint32_t)((v) >> 32));
-
-#define SIP_U8TO64_LE(p)                                                       \
-  (((uint64_t)((p)[0]) << 0) | ((uint64_t)((p)[1]) << 8)                       \
-   | ((uint64_t)((p)[2]) << 16) | ((uint64_t)((p)[3]) << 24)                   \
-   | ((uint64_t)((p)[4]) << 32) | ((uint64_t)((p)[5]) << 40)                   \
-   | ((uint64_t)((p)[6]) << 48) | ((uint64_t)((p)[7]) << 56))
-
-#define SIPHASH_INITIALIZER                                                    \
-  { 0, 0, 0, 0, {0}, 0, 0 }
-
-struct siphash {
-  uint64_t v0, v1, v2, v3;
-
-  unsigned char buf[8], *p;
-  uint64_t c;
-}; /* struct siphash */
-
-#define SIP_KEYLEN 16
-
-struct sipkey {
-  uint64_t k[2];
-}; /* struct sipkey */
-
-#define sip_keyof(k) sip_tokey(&(struct sipkey){{0}}, (k))
-
-static struct sipkey *
-sip_tokey(struct sipkey *key, const void *src) {
-  key->k[0] = SIP_U8TO64_LE((const unsigned char *)src);
-  key->k[1] = SIP_U8TO64_LE((const unsigned char *)src + 8);
-  return key;
-} /* sip_tokey() */
-
-#ifdef SIPHASH_TOBIN
-
-#  define sip_binof(v) sip_tobin((unsigned char[8]){0}, (v))
-
-static void *
-sip_tobin(void *dst, uint64_t u64) {
-  SIP_U64TO8_LE((unsigned char *)dst, u64);
-  return dst;
-} /* sip_tobin() */
-
-#endif /* SIPHASH_TOBIN */
-
-static void
-sip_round(struct siphash *H, const int rounds) {
-  int i;
-
-  for (i = 0; i < rounds; i++) {
-    H->v0 += H->v1;
-    H->v1 = SIP_ROTL(H->v1, 13);
-    H->v1 ^= H->v0;
-    H->v0 = SIP_ROTL(H->v0, 32);
-
-    H->v2 += H->v3;
-    H->v3 = SIP_ROTL(H->v3, 16);
-    H->v3 ^= H->v2;
-
-    H->v0 += H->v3;
-    H->v3 = SIP_ROTL(H->v3, 21);
-    H->v3 ^= H->v0;
-
-    H->v2 += H->v1;
-    H->v1 = SIP_ROTL(H->v1, 17);
-    H->v1 ^= H->v2;
-    H->v2 = SIP_ROTL(H->v2, 32);
-  }
-} /* sip_round() */
-
-static struct siphash *
-sip24_init(struct siphash *H, const struct sipkey *key) {
-  H->v0 = _SIP_ULL(0x736f6d65U, 0x70736575U) ^ key->k[0];
-  H->v1 = _SIP_ULL(0x646f7261U, 0x6e646f6dU) ^ key->k[1];
-  H->v2 = _SIP_ULL(0x6c796765U, 0x6e657261U) ^ key->k[0];
-  H->v3 = _SIP_ULL(0x74656462U, 0x79746573U) ^ key->k[1];
-
-  H->p = H->buf;
-  H->c = 0;
-
-  return H;
-} /* sip24_init() */
-
-#define sip_endof(a) (&(a)[sizeof(a) / sizeof *(a)])
-
-static struct siphash *
-sip24_update(struct siphash *H, const void *src, size_t len) {
-  const unsigned char *p = (const unsigned char *)src, *pe = p + len;
-  uint64_t m;
-
-  do {
-    while (p < pe && H->p < sip_endof(H->buf))
-      *H->p++ = *p++;
-
-    if (H->p < sip_endof(H->buf))
-      break;
-
-    m = SIP_U8TO64_LE(H->buf);
-    H->v3 ^= m;
-    sip_round(H, 2);
-    H->v0 ^= m;
-
-    H->p = H->buf;
-    H->c += 8;
-  } while (p < pe);
-
-  return H;
-} /* sip24_update() */
-
-static uint64_t
-sip24_final(struct siphash *H) {
-  const char left = (char)(H->p - H->buf);
-  uint64_t b = (H->c + left) << 56;
-
-  switch (left) {
-  case 7:
-    b |= (uint64_t)H->buf[6] << 48;
-    /* fall through */
-  case 6:
-    b |= (uint64_t)H->buf[5] << 40;
-    /* fall through */
-  case 5:
-    b |= (uint64_t)H->buf[4] << 32;
-    /* fall through */
-  case 4:
-    b |= (uint64_t)H->buf[3] << 24;
-    /* fall through */
-  case 3:
-    b |= (uint64_t)H->buf[2] << 16;
-    /* fall through */
-  case 2:
-    b |= (uint64_t)H->buf[1] << 8;
-    /* fall through */
-  case 1:
-    b |= (uint64_t)H->buf[0] << 0;
-    /* fall through */
-  case 0:
-    break;
-  }
-
-  H->v3 ^= b;
-  sip_round(H, 2);
-  H->v0 ^= b;
-  H->v2 ^= 0xff;
-  sip_round(H, 4);
-
-  return H->v0 ^ H->v1 ^ H->v2 ^ H->v3;
-} /* sip24_final() */
-
-static uint64_t
-siphash24(const void *src, size_t len, const struct sipkey *key) {
-  struct siphash state = SIPHASH_INITIALIZER;
-  return sip24_final(sip24_update(sip24_init(&state, key), src, len));
-} /* siphash24() */
-
-/*
- * SipHash-2-4 output with
- * k = 00 01 02 ...
- * and
- * in = (empty string)
- * in = 00 (1 byte)
- * in = 00 01 (2 bytes)
- * in = 00 01 02 (3 bytes)
- * ...
- * in = 00 01 02 ... 3e (63 bytes)
- */
-static int
-sip24_valid(void) {
-  /* clang-format off */
-  static const unsigned char vectors[64][8] = {
-    { 0x31, 0x0e, 0x0e, 0xdd, 0x47, 0xdb, 0x6f, 0x72, },
-    { 0xfd, 0x67, 0xdc, 0x93, 0xc5, 0x39, 0xf8, 0x74, },
-    { 0x5a, 0x4f, 0xa9, 0xd9, 0x09, 0x80, 0x6c, 0x0d, },
-    { 0x2d, 0x7e, 0xfb, 0xd7, 0x96, 0x66, 0x67, 0x85, },
-    { 0xb7, 0x87, 0x71, 0x27, 0xe0, 0x94, 0x27, 0xcf, },
-    { 0x8d, 0xa6, 0x99, 0xcd, 0x64, 0x55, 0x76, 0x18, },
-    { 0xce, 0xe3, 0xfe, 0x58, 0x6e, 0x46, 0xc9, 0xcb, },
-    { 0x37, 0xd1, 0x01, 0x8b, 0xf5, 0x00, 0x02, 0xab, },
-    { 0x62, 0x24, 0x93, 0x9a, 0x79, 0xf5, 0xf5, 0x93, },
-    { 0xb0, 0xe4, 0xa9, 0x0b, 0xdf, 0x82, 0x00, 0x9e, },
-    { 0xf3, 0xb9, 0xdd, 0x94, 0xc5, 0xbb, 0x5d, 0x7a, },
-    { 0xa7, 0xad, 0x6b, 0x22, 0x46, 0x2f, 0xb3, 0xf4, },
-    { 0xfb, 0xe5, 0x0e, 0x86, 0xbc, 0x8f, 0x1e, 0x75, },
-    { 0x90, 0x3d, 0x84, 0xc0, 0x27, 0x56, 0xea, 0x14, },
-    { 0xee, 0xf2, 0x7a, 0x8e, 0x90, 0xca, 0x23, 0xf7, },
-    { 0xe5, 0x45, 0xbe, 0x49, 0x61, 0xca, 0x29, 0xa1, },
-    { 0xdb, 0x9b, 0xc2, 0x57, 0x7f, 0xcc, 0x2a, 0x3f, },
-    { 0x94, 0x47, 0xbe, 0x2c, 0xf5, 0xe9, 0x9a, 0x69, },
-    { 0x9c, 0xd3, 0x8d, 0x96, 0xf0, 0xb3, 0xc1, 0x4b, },
-    { 0xbd, 0x61, 0x79, 0xa7, 0x1d, 0xc9, 0x6d, 0xbb, },
-    { 0x98, 0xee, 0xa2, 0x1a, 0xf2, 0x5c, 0xd6, 0xbe, },
-    { 0xc7, 0x67, 0x3b, 0x2e, 0xb0, 0xcb, 0xf2, 0xd0, },
-    { 0x88, 0x3e, 0xa3, 0xe3, 0x95, 0x67, 0x53, 0x93, },
-    { 0xc8, 0xce, 0x5c, 0xcd, 0x8c, 0x03, 0x0c, 0xa8, },
-    { 0x94, 0xaf, 0x49, 0xf6, 0xc6, 0x50, 0xad, 0xb8, },
-    { 0xea, 0xb8, 0x85, 0x8a, 0xde, 0x92, 0xe1, 0xbc, },
-    { 0xf3, 0x15, 0xbb, 0x5b, 0xb8, 0x35, 0xd8, 0x17, },
-    { 0xad, 0xcf, 0x6b, 0x07, 0x63, 0x61, 0x2e, 0x2f, },
-    { 0xa5, 0xc9, 0x1d, 0xa7, 0xac, 0xaa, 0x4d, 0xde, },
-    { 0x71, 0x65, 0x95, 0x87, 0x66, 0x50, 0xa2, 0xa6, },
-    { 0x28, 0xef, 0x49, 0x5c, 0x53, 0xa3, 0x87, 0xad, },
-    { 0x42, 0xc3, 0x41, 0xd8, 0xfa, 0x92, 0xd8, 0x32, },
-    { 0xce, 0x7c, 0xf2, 0x72, 0x2f, 0x51, 0x27, 0x71, },
-    { 0xe3, 0x78, 0x59, 0xf9, 0x46, 0x23, 0xf3, 0xa7, },
-    { 0x38, 0x12, 0x05, 0xbb, 0x1a, 0xb0, 0xe0, 0x12, },
-    { 0xae, 0x97, 0xa1, 0x0f, 0xd4, 0x34, 0xe0, 0x15, },
-    { 0xb4, 0xa3, 0x15, 0x08, 0xbe, 0xff, 0x4d, 0x31, },
-    { 0x81, 0x39, 0x62, 0x29, 0xf0, 0x90, 0x79, 0x02, },
-    { 0x4d, 0x0c, 0xf4, 0x9e, 0xe5, 0xd4, 0xdc, 0xca, },
-    { 0x5c, 0x73, 0x33, 0x6a, 0x76, 0xd8, 0xbf, 0x9a, },
-    { 0xd0, 0xa7, 0x04, 0x53, 0x6b, 0xa9, 0x3e, 0x0e, },
-    { 0x92, 0x59, 0x58, 0xfc, 0xd6, 0x42, 0x0c, 0xad, },
-    { 0xa9, 0x15, 0xc2, 0x9b, 0xc8, 0x06, 0x73, 0x18, },
-    { 0x95, 0x2b, 0x79, 0xf3, 0xbc, 0x0a, 0xa6, 0xd4, },
-    { 0xf2, 0x1d, 0xf2, 0xe4, 0x1d, 0x45, 0x35, 0xf9, },
-    { 0x87, 0x57, 0x75, 0x19, 0x04, 0x8f, 0x53, 0xa9, },
-    { 0x10, 0xa5, 0x6c, 0xf5, 0xdf, 0xcd, 0x9a, 0xdb, },
-    { 0xeb, 0x75, 0x09, 0x5c, 0xcd, 0x98, 0x6c, 0xd0, },
-    { 0x51, 0xa9, 0xcb, 0x9e, 0xcb, 0xa3, 0x12, 0xe6, },
-    { 0x96, 0xaf, 0xad, 0xfc, 0x2c, 0xe6, 0x66, 0xc7, },
-    { 0x72, 0xfe, 0x52, 0x97, 0x5a, 0x43, 0x64, 0xee, },
-    { 0x5a, 0x16, 0x45, 0xb2, 0x76, 0xd5, 0x92, 0xa1, },
-    { 0xb2, 0x74, 0xcb, 0x8e, 0xbf, 0x87, 0x87, 0x0a, },
-    { 0x6f, 0x9b, 0xb4, 0x20, 0x3d, 0xe7, 0xb3, 0x81, },
-    { 0xea, 0xec, 0xb2, 0xa3, 0x0b, 0x22, 0xa8, 0x7f, },
-    { 0x99, 0x24, 0xa4, 0x3c, 0xc1, 0x31, 0x57, 0x24, },
-    { 0xbd, 0x83, 0x8d, 0x3a, 0xaf, 0xbf, 0x8d, 0xb7, },
-    { 0x0b, 0x1a, 0x2a, 0x32, 0x65, 0xd5, 0x1a, 0xea, },
-    { 0x13, 0x50, 0x79, 0xa3, 0x23, 0x1c, 0xe6, 0x60, },
-    { 0x93, 0x2b, 0x28, 0x46, 0xe4, 0xd7, 0x06, 0x66, },
-    { 0xe1, 0x91, 0x5f, 0x5c, 0xb1, 0xec, 0xa4, 0x6c, },
-    { 0xf3, 0x25, 0x96, 0x5c, 0xa1, 0x6d, 0x62, 0x9f, },
-    { 0x57, 0x5f, 0xf2, 0x8e, 0x60, 0x38, 0x1b, 0xe5, },
-    { 0x72, 0x45, 0x06, 0xeb, 0x4c, 0x32, 0x8a, 0x95, }
-  };
-  /* clang-format on */
-
-  unsigned char in[64];
-  struct sipkey k;
-  size_t i;
-
-  sip_tokey(&k, "\000\001\002\003\004\005\006\007\010\011"
-                "\012\013\014\015\016\017");
-
-  for (i = 0; i < sizeof in; ++i) {
-    in[i] = (unsigned char)i;
-
-    if (siphash24(in, i, &k) != SIP_U8TO64_LE(vectors[i]))
-      return 0;
-  }
-
-  return 1;
-} /* sip24_valid() */
-
-#ifdef SIPHASH_MAIN
-
-#  include <stdio.h>
-
-int
-main(void) {
-  const int ok = sip24_valid();
-
-  if (ok)
-    puts("OK");
-  else
-    puts("FAIL");
-
-  return ! ok;
-} /* main() */
-
-#endif /* SIPHASH_MAIN */
-
-#endif /* SIPHASH_H */
diff --git a/tools/sdk/include/expat/utf8tab.h b/tools/sdk/include/expat/utf8tab.h
deleted file mode 100644
index a22986acbb9..00000000000
--- a/tools/sdk/include/expat/utf8tab.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/* 0x80 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0x84 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0x88 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0x8C */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0x90 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0x94 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0x98 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0x9C */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0xA0 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0xA4 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0xA8 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0xAC */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0xB0 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0xB4 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0xB8 */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0xBC */ BT_TRAIL, BT_TRAIL, BT_TRAIL, BT_TRAIL,
-    /* 0xC0 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2,
-    /* 0xC4 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2,
-    /* 0xC8 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2,
-    /* 0xCC */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2,
-    /* 0xD0 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2,
-    /* 0xD4 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2,
-    /* 0xD8 */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2,
-    /* 0xDC */ BT_LEAD2, BT_LEAD2, BT_LEAD2, BT_LEAD2,
-    /* 0xE0 */ BT_LEAD3, BT_LEAD3, BT_LEAD3, BT_LEAD3,
-    /* 0xE4 */ BT_LEAD3, BT_LEAD3, BT_LEAD3, BT_LEAD3,
-    /* 0xE8 */ BT_LEAD3, BT_LEAD3, BT_LEAD3, BT_LEAD3,
-    /* 0xEC */ BT_LEAD3, BT_LEAD3, BT_LEAD3, BT_LEAD3,
-    /* 0xF0 */ BT_LEAD4, BT_LEAD4, BT_LEAD4, BT_LEAD4,
-    /* 0xF4 */ BT_LEAD4, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0xF8 */ BT_NONXML, BT_NONXML, BT_NONXML, BT_NONXML,
-    /* 0xFC */ BT_NONXML, BT_NONXML, BT_MALFORM, BT_MALFORM,
diff --git a/tools/sdk/include/expat/winconfig.h b/tools/sdk/include/expat/winconfig.h
deleted file mode 100644
index 562a4a82dc1..00000000000
--- a/tools/sdk/include/expat/winconfig.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef WINCONFIG_H
-#define WINCONFIG_H
-
-#define WIN32_LEAN_AND_MEAN
-#include <windows.h>
-#undef WIN32_LEAN_AND_MEAN
-
-#include <memory.h>
-#include <string.h>
-
-#if defined(HAVE_EXPAT_CONFIG_H) /* e.g. MinGW */
-#  include <expat_config.h>
-#else /* !defined(HAVE_EXPAT_CONFIG_H) */
-
-#  define XML_NS 1
-#  define XML_DTD 1
-#  define XML_CONTEXT_BYTES 1024
-
-/* we will assume all Windows platforms are little endian */
-#  define BYTEORDER 1234
-
-#endif /* !defined(HAVE_EXPAT_CONFIG_H) */
-
-#endif /* ndef WINCONFIG_H */
diff --git a/tools/sdk/include/expat/xmlrole.h b/tools/sdk/include/expat/xmlrole.h
deleted file mode 100644
index 036aba64fd2..00000000000
--- a/tools/sdk/include/expat/xmlrole.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef XmlRole_INCLUDED
-#define XmlRole_INCLUDED 1
-
-#ifdef __VMS
-/*      0        1         2         3      0        1         2         3
-        1234567890123456789012345678901     1234567890123456789012345678901 */
-#  define XmlPrologStateInitExternalEntity XmlPrologStateInitExternalEnt
-#endif
-
-#include "xmltok.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-enum {
-  XML_ROLE_ERROR = -1,
-  XML_ROLE_NONE = 0,
-  XML_ROLE_XML_DECL,
-  XML_ROLE_INSTANCE_START,
-  XML_ROLE_DOCTYPE_NONE,
-  XML_ROLE_DOCTYPE_NAME,
-  XML_ROLE_DOCTYPE_SYSTEM_ID,
-  XML_ROLE_DOCTYPE_PUBLIC_ID,
-  XML_ROLE_DOCTYPE_INTERNAL_SUBSET,
-  XML_ROLE_DOCTYPE_CLOSE,
-  XML_ROLE_GENERAL_ENTITY_NAME,
-  XML_ROLE_PARAM_ENTITY_NAME,
-  XML_ROLE_ENTITY_NONE,
-  XML_ROLE_ENTITY_VALUE,
-  XML_ROLE_ENTITY_SYSTEM_ID,
-  XML_ROLE_ENTITY_PUBLIC_ID,
-  XML_ROLE_ENTITY_COMPLETE,
-  XML_ROLE_ENTITY_NOTATION_NAME,
-  XML_ROLE_NOTATION_NONE,
-  XML_ROLE_NOTATION_NAME,
-  XML_ROLE_NOTATION_SYSTEM_ID,
-  XML_ROLE_NOTATION_NO_SYSTEM_ID,
-  XML_ROLE_NOTATION_PUBLIC_ID,
-  XML_ROLE_ATTRIBUTE_NAME,
-  XML_ROLE_ATTRIBUTE_TYPE_CDATA,
-  XML_ROLE_ATTRIBUTE_TYPE_ID,
-  XML_ROLE_ATTRIBUTE_TYPE_IDREF,
-  XML_ROLE_ATTRIBUTE_TYPE_IDREFS,
-  XML_ROLE_ATTRIBUTE_TYPE_ENTITY,
-  XML_ROLE_ATTRIBUTE_TYPE_ENTITIES,
-  XML_ROLE_ATTRIBUTE_TYPE_NMTOKEN,
-  XML_ROLE_ATTRIBUTE_TYPE_NMTOKENS,
-  XML_ROLE_ATTRIBUTE_ENUM_VALUE,
-  XML_ROLE_ATTRIBUTE_NOTATION_VALUE,
-  XML_ROLE_ATTLIST_NONE,
-  XML_ROLE_ATTLIST_ELEMENT_NAME,
-  XML_ROLE_IMPLIED_ATTRIBUTE_VALUE,
-  XML_ROLE_REQUIRED_ATTRIBUTE_VALUE,
-  XML_ROLE_DEFAULT_ATTRIBUTE_VALUE,
-  XML_ROLE_FIXED_ATTRIBUTE_VALUE,
-  XML_ROLE_ELEMENT_NONE,
-  XML_ROLE_ELEMENT_NAME,
-  XML_ROLE_CONTENT_ANY,
-  XML_ROLE_CONTENT_EMPTY,
-  XML_ROLE_CONTENT_PCDATA,
-  XML_ROLE_GROUP_OPEN,
-  XML_ROLE_GROUP_CLOSE,
-  XML_ROLE_GROUP_CLOSE_REP,
-  XML_ROLE_GROUP_CLOSE_OPT,
-  XML_ROLE_GROUP_CLOSE_PLUS,
-  XML_ROLE_GROUP_CHOICE,
-  XML_ROLE_GROUP_SEQUENCE,
-  XML_ROLE_CONTENT_ELEMENT,
-  XML_ROLE_CONTENT_ELEMENT_REP,
-  XML_ROLE_CONTENT_ELEMENT_OPT,
-  XML_ROLE_CONTENT_ELEMENT_PLUS,
-  XML_ROLE_PI,
-  XML_ROLE_COMMENT,
-#ifdef XML_DTD
-  XML_ROLE_TEXT_DECL,
-  XML_ROLE_IGNORE_SECT,
-  XML_ROLE_INNER_PARAM_ENTITY_REF,
-#endif /* XML_DTD */
-  XML_ROLE_PARAM_ENTITY_REF
-};
-
-typedef struct prolog_state {
-  int(PTRCALL *handler)(struct prolog_state *state, int tok, const char *ptr,
-                        const char *end, const ENCODING *enc);
-  unsigned level;
-  int role_none;
-#ifdef XML_DTD
-  unsigned includeLevel;
-  int documentEntity;
-  int inEntityValue;
-#endif /* XML_DTD */
-} PROLOG_STATE;
-
-void XmlPrologStateInit(PROLOG_STATE *);
-#ifdef XML_DTD
-void XmlPrologStateInitExternalEntity(PROLOG_STATE *);
-#endif /* XML_DTD */
-
-#define XmlTokenRole(state, tok, ptr, end, enc)                                \
-  (((state)->handler)(state, tok, ptr, end, enc))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* not XmlRole_INCLUDED */
diff --git a/tools/sdk/include/expat/xmltok.h b/tools/sdk/include/expat/xmltok.h
deleted file mode 100644
index 2adbf5307be..00000000000
--- a/tools/sdk/include/expat/xmltok.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#ifndef XmlTok_INCLUDED
-#define XmlTok_INCLUDED 1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* The following token may be returned by XmlContentTok */
-#define XML_TOK_TRAILING_RSQB                                                  \
-  -5 /* ] or ]] at the end of the scan; might be                               \
-        start of illegal ]]> sequence */
-/* The following tokens may be returned by both XmlPrologTok and
-   XmlContentTok.
-*/
-#define XML_TOK_NONE -4 /* The string to be scanned is empty */
-#define XML_TOK_TRAILING_CR                                                    \
-  -3                            /* A CR at the end of the scan;                \
-                                   might be part of CRLF sequence */
-#define XML_TOK_PARTIAL_CHAR -2 /* only part of a multibyte sequence */
-#define XML_TOK_PARTIAL -1      /* only part of a token */
-#define XML_TOK_INVALID 0
-
-/* The following tokens are returned by XmlContentTok; some are also
-   returned by XmlAttributeValueTok, XmlEntityTok, XmlCdataSectionTok.
-*/
-#define XML_TOK_START_TAG_WITH_ATTS 1
-#define XML_TOK_START_TAG_NO_ATTS 2
-#define XML_TOK_EMPTY_ELEMENT_WITH_ATTS 3 /* empty element tag <e/> */
-#define XML_TOK_EMPTY_ELEMENT_NO_ATTS 4
-#define XML_TOK_END_TAG 5
-#define XML_TOK_DATA_CHARS 6
-#define XML_TOK_DATA_NEWLINE 7
-#define XML_TOK_CDATA_SECT_OPEN 8
-#define XML_TOK_ENTITY_REF 9
-#define XML_TOK_CHAR_REF 10 /* numeric character reference */
-
-/* The following tokens may be returned by both XmlPrologTok and
-   XmlContentTok.
-*/
-#define XML_TOK_PI 11       /* processing instruction */
-#define XML_TOK_XML_DECL 12 /* XML decl or text decl */
-#define XML_TOK_COMMENT 13
-#define XML_TOK_BOM 14 /* Byte order mark */
-
-/* The following tokens are returned only by XmlPrologTok */
-#define XML_TOK_PROLOG_S 15
-#define XML_TOK_DECL_OPEN 16  /* <!foo */
-#define XML_TOK_DECL_CLOSE 17 /* > */
-#define XML_TOK_NAME 18
-#define XML_TOK_NMTOKEN 19
-#define XML_TOK_POUND_NAME 20 /* #name */
-#define XML_TOK_OR 21         /* | */
-#define XML_TOK_PERCENT 22
-#define XML_TOK_OPEN_PAREN 23
-#define XML_TOK_CLOSE_PAREN 24
-#define XML_TOK_OPEN_BRACKET 25
-#define XML_TOK_CLOSE_BRACKET 26
-#define XML_TOK_LITERAL 27
-#define XML_TOK_PARAM_ENTITY_REF 28
-#define XML_TOK_INSTANCE_START 29
-
-/* The following occur only in element type declarations */
-#define XML_TOK_NAME_QUESTION 30        /* name? */
-#define XML_TOK_NAME_ASTERISK 31        /* name* */
-#define XML_TOK_NAME_PLUS 32            /* name+ */
-#define XML_TOK_COND_SECT_OPEN 33       /* <![ */
-#define XML_TOK_COND_SECT_CLOSE 34      /* ]]> */
-#define XML_TOK_CLOSE_PAREN_QUESTION 35 /* )? */
-#define XML_TOK_CLOSE_PAREN_ASTERISK 36 /* )* */
-#define XML_TOK_CLOSE_PAREN_PLUS 37     /* )+ */
-#define XML_TOK_COMMA 38
-
-/* The following token is returned only by XmlAttributeValueTok */
-#define XML_TOK_ATTRIBUTE_VALUE_S 39
-
-/* The following token is returned only by XmlCdataSectionTok */
-#define XML_TOK_CDATA_SECT_CLOSE 40
-
-/* With namespace processing this is returned by XmlPrologTok for a
-   name with a colon.
-*/
-#define XML_TOK_PREFIXED_NAME 41
-
-#ifdef XML_DTD
-#  define XML_TOK_IGNORE_SECT 42
-#endif /* XML_DTD */
-
-#ifdef XML_DTD
-#  define XML_N_STATES 4
-#else /* not XML_DTD */
-#  define XML_N_STATES 3
-#endif /* not XML_DTD */
-
-#define XML_PROLOG_STATE 0
-#define XML_CONTENT_STATE 1
-#define XML_CDATA_SECTION_STATE 2
-#ifdef XML_DTD
-#  define XML_IGNORE_SECTION_STATE 3
-#endif /* XML_DTD */
-
-#define XML_N_LITERAL_TYPES 2
-#define XML_ATTRIBUTE_VALUE_LITERAL 0
-#define XML_ENTITY_VALUE_LITERAL 1
-
-/* The size of the buffer passed to XmlUtf8Encode must be at least this. */
-#define XML_UTF8_ENCODE_MAX 4
-/* The size of the buffer passed to XmlUtf16Encode must be at least this. */
-#define XML_UTF16_ENCODE_MAX 2
-
-typedef struct position {
-  /* first line and first column are 0 not 1 */
-  XML_Size lineNumber;
-  XML_Size columnNumber;
-} POSITION;
-
-typedef struct {
-  const char *name;
-  const char *valuePtr;
-  const char *valueEnd;
-  char normalized;
-} ATTRIBUTE;
-
-struct encoding;
-typedef struct encoding ENCODING;
-
-typedef int(PTRCALL *SCANNER)(const ENCODING *, const char *, const char *,
-                              const char **);
-
-enum XML_Convert_Result {
-  XML_CONVERT_COMPLETED = 0,
-  XML_CONVERT_INPUT_INCOMPLETE = 1,
-  XML_CONVERT_OUTPUT_EXHAUSTED
-  = 2 /* and therefore potentially input remaining as well */
-};
-
-struct encoding {
-  SCANNER scanners[XML_N_STATES];
-  SCANNER literalScanners[XML_N_LITERAL_TYPES];
-  int(PTRCALL *nameMatchesAscii)(const ENCODING *, const char *, const char *,
-                                 const char *);
-  int(PTRFASTCALL *nameLength)(const ENCODING *, const char *);
-  const char *(PTRFASTCALL *skipS)(const ENCODING *, const char *);
-  int(PTRCALL *getAtts)(const ENCODING *enc, const char *ptr, int attsMax,
-                        ATTRIBUTE *atts);
-  int(PTRFASTCALL *charRefNumber)(const ENCODING *enc, const char *ptr);
-  int(PTRCALL *predefinedEntityName)(const ENCODING *, const char *,
-                                     const char *);
-  void(PTRCALL *updatePosition)(const ENCODING *, const char *ptr,
-                                const char *end, POSITION *);
-  int(PTRCALL *isPublicId)(const ENCODING *enc, const char *ptr,
-                           const char *end, const char **badPtr);
-  enum XML_Convert_Result(PTRCALL *utf8Convert)(const ENCODING *enc,
-                                                const char **fromP,
-                                                const char *fromLim, char **toP,
-                                                const char *toLim);
-  enum XML_Convert_Result(PTRCALL *utf16Convert)(const ENCODING *enc,
-                                                 const char **fromP,
-                                                 const char *fromLim,
-                                                 unsigned short **toP,
-                                                 const unsigned short *toLim);
-  int minBytesPerChar;
-  char isUtf8;
-  char isUtf16;
-};
-
-/* Scan the string starting at ptr until the end of the next complete
-   token, but do not scan past eptr.  Return an integer giving the
-   type of token.
-
-   Return XML_TOK_NONE when ptr == eptr; nextTokPtr will not be set.
-
-   Return XML_TOK_PARTIAL when the string does not contain a complete
-   token; nextTokPtr will not be set.
-
-   Return XML_TOK_INVALID when the string does not start a valid
-   token; nextTokPtr will be set to point to the character which made
-   the token invalid.
-
-   Otherwise the string starts with a valid token; nextTokPtr will be
-   set to point to the character following the end of that token.
-
-   Each data character counts as a single token, but adjacent data
-   characters may be returned together.  Similarly for characters in
-   the prolog outside literals, comments and processing instructions.
-*/
-
-#define XmlTok(enc, state, ptr, end, nextTokPtr)                               \
-  (((enc)->scanners[state])(enc, ptr, end, nextTokPtr))
-
-#define XmlPrologTok(enc, ptr, end, nextTokPtr)                                \
-  XmlTok(enc, XML_PROLOG_STATE, ptr, end, nextTokPtr)
-
-#define XmlContentTok(enc, ptr, end, nextTokPtr)                               \
-  XmlTok(enc, XML_CONTENT_STATE, ptr, end, nextTokPtr)
-
-#define XmlCdataSectionTok(enc, ptr, end, nextTokPtr)                          \
-  XmlTok(enc, XML_CDATA_SECTION_STATE, ptr, end, nextTokPtr)
-
-#ifdef XML_DTD
-
-#  define XmlIgnoreSectionTok(enc, ptr, end, nextTokPtr)                       \
-    XmlTok(enc, XML_IGNORE_SECTION_STATE, ptr, end, nextTokPtr)
-
-#endif /* XML_DTD */
-
-/* This is used for performing a 2nd-level tokenization on the content
-   of a literal that has already been returned by XmlTok.
-*/
-#define XmlLiteralTok(enc, literalType, ptr, end, nextTokPtr)                  \
-  (((enc)->literalScanners[literalType])(enc, ptr, end, nextTokPtr))
-
-#define XmlAttributeValueTok(enc, ptr, end, nextTokPtr)                        \
-  XmlLiteralTok(enc, XML_ATTRIBUTE_VALUE_LITERAL, ptr, end, nextTokPtr)
-
-#define XmlEntityValueTok(enc, ptr, end, nextTokPtr)                           \
-  XmlLiteralTok(enc, XML_ENTITY_VALUE_LITERAL, ptr, end, nextTokPtr)
-
-#define XmlNameMatchesAscii(enc, ptr1, end1, ptr2)                             \
-  (((enc)->nameMatchesAscii)(enc, ptr1, end1, ptr2))
-
-#define XmlNameLength(enc, ptr) (((enc)->nameLength)(enc, ptr))
-
-#define XmlSkipS(enc, ptr) (((enc)->skipS)(enc, ptr))
-
-#define XmlGetAttributes(enc, ptr, attsMax, atts)                              \
-  (((enc)->getAtts)(enc, ptr, attsMax, atts))
-
-#define XmlCharRefNumber(enc, ptr) (((enc)->charRefNumber)(enc, ptr))
-
-#define XmlPredefinedEntityName(enc, ptr, end)                                 \
-  (((enc)->predefinedEntityName)(enc, ptr, end))
-
-#define XmlUpdatePosition(enc, ptr, end, pos)                                  \
-  (((enc)->updatePosition)(enc, ptr, end, pos))
-
-#define XmlIsPublicId(enc, ptr, end, badPtr)                                   \
-  (((enc)->isPublicId)(enc, ptr, end, badPtr))
-
-#define XmlUtf8Convert(enc, fromP, fromLim, toP, toLim)                        \
-  (((enc)->utf8Convert)(enc, fromP, fromLim, toP, toLim))
-
-#define XmlUtf16Convert(enc, fromP, fromLim, toP, toLim)                       \
-  (((enc)->utf16Convert)(enc, fromP, fromLim, toP, toLim))
-
-typedef struct {
-  ENCODING initEnc;
-  const ENCODING **encPtr;
-} INIT_ENCODING;
-
-int XmlParseXmlDecl(int isGeneralTextEntity, const ENCODING *enc,
-                    const char *ptr, const char *end, const char **badPtr,
-                    const char **versionPtr, const char **versionEndPtr,
-                    const char **encodingNamePtr,
-                    const ENCODING **namedEncodingPtr, int *standalonePtr);
-
-int XmlInitEncoding(INIT_ENCODING *, const ENCODING **, const char *name);
-const ENCODING *XmlGetUtf8InternalEncoding(void);
-const ENCODING *XmlGetUtf16InternalEncoding(void);
-int FASTCALL XmlUtf8Encode(int charNumber, char *buf);
-int FASTCALL XmlUtf16Encode(int charNumber, unsigned short *buf);
-int XmlSizeOfUnknownEncoding(void);
-
-typedef int(XMLCALL *CONVERTER)(void *userData, const char *p);
-
-ENCODING *XmlInitUnknownEncoding(void *mem, int *table, CONVERTER convert,
-                                 void *userData);
-
-int XmlParseXmlDeclNS(int isGeneralTextEntity, const ENCODING *enc,
-                      const char *ptr, const char *end, const char **badPtr,
-                      const char **versionPtr, const char **versionEndPtr,
-                      const char **encodingNamePtr,
-                      const ENCODING **namedEncodingPtr, int *standalonePtr);
-
-int XmlInitEncodingNS(INIT_ENCODING *, const ENCODING **, const char *name);
-const ENCODING *XmlGetUtf8InternalEncodingNS(void);
-const ENCODING *XmlGetUtf16InternalEncodingNS(void);
-ENCODING *XmlInitUnknownEncodingNS(void *mem, int *table, CONVERTER convert,
-                                   void *userData);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* not XmlTok_INCLUDED */
diff --git a/tools/sdk/include/expat/xmltok_impl.h b/tools/sdk/include/expat/xmltok_impl.h
deleted file mode 100644
index e925dbc7e2c..00000000000
--- a/tools/sdk/include/expat/xmltok_impl.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
-                            __  __            _
-                         ___\ \/ /_ __   __ _| |_
-                        / _ \\  /| '_ \ / _` | __|
-                       |  __//  \| |_) | (_| | |_
-                        \___/_/\_\ .__/ \__,_|\__|
-                                 |_| XML parser
-
-   Copyright (c) 1997-2000 Thai Open Source Software Center Ltd
-   Copyright (c) 2000-2017 Expat development team
-   Licensed under the MIT license:
-
-   Permission is  hereby granted,  free of charge,  to any  person obtaining
-   a  copy  of  this  software   and  associated  documentation  files  (the
-   "Software"),  to  deal in  the  Software  without restriction,  including
-   without  limitation the  rights  to use,  copy,  modify, merge,  publish,
-   distribute, sublicense, and/or sell copies of the Software, and to permit
-   persons  to whom  the Software  is  furnished to  do so,  subject to  the
-   following conditions:
-
-   The above copyright  notice and this permission notice  shall be included
-   in all copies or substantial portions of the Software.
-
-   THE  SOFTWARE  IS  PROVIDED  "AS  IS",  WITHOUT  WARRANTY  OF  ANY  KIND,
-   EXPRESS  OR IMPLIED,  INCLUDING  BUT  NOT LIMITED  TO  THE WARRANTIES  OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
-   NO EVENT SHALL THE AUTHORS OR  COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-   DAMAGES OR  OTHER LIABILITY, WHETHER  IN AN  ACTION OF CONTRACT,  TORT OR
-   OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-   USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-enum {
-  BT_NONXML,   /* e.g. noncharacter-FFFF */
-  BT_MALFORM,  /* illegal, with regard to encoding */
-  BT_LT,       /* less than = "<" */
-  BT_AMP,      /* ampersand = "&" */
-  BT_RSQB,     /* right square bracket = "[" */
-  BT_LEAD2,    /* lead byte of a 2-byte UTF-8 character */
-  BT_LEAD3,    /* lead byte of a 3-byte UTF-8 character */
-  BT_LEAD4,    /* lead byte of a 4-byte UTF-8 character */
-  BT_TRAIL,    /* trailing unit, e.g. second 16-bit unit of a 4-byte char. */
-  BT_CR,       /* carriage return = "\r" */
-  BT_LF,       /* line feed = "\n" */
-  BT_GT,       /* greater than = ">" */
-  BT_QUOT,     /* quotation character = "\"" */
-  BT_APOS,     /* aposthrophe = "'" */
-  BT_EQUALS,   /* equal sign = "=" */
-  BT_QUEST,    /* question mark = "?" */
-  BT_EXCL,     /* exclamation mark = "!" */
-  BT_SOL,      /* solidus, slash = "/" */
-  BT_SEMI,     /* semicolon = ";" */
-  BT_NUM,      /* number sign = "#" */
-  BT_LSQB,     /* left square bracket = "[" */
-  BT_S,        /* white space, e.g. "\t", " "[, "\r"] */
-  BT_NMSTRT,   /* non-hex name start letter = "G".."Z" + "g".."z" + "_" */
-  BT_COLON,    /* colon = ":" */
-  BT_HEX,      /* hex letter = "A".."F" + "a".."f" */
-  BT_DIGIT,    /* digit = "0".."9" */
-  BT_NAME,     /* dot and middle dot = "." + chr(0xb7) */
-  BT_MINUS,    /* minus = "-" */
-  BT_OTHER,    /* known not to be a name or name start character */
-  BT_NONASCII, /* might be a name or name start character */
-  BT_PERCNT,   /* percent sign = "%" */
-  BT_LPAR,     /* left parenthesis = "(" */
-  BT_RPAR,     /* right parenthesis = "(" */
-  BT_AST,      /* asterisk = "*" */
-  BT_PLUS,     /* plus sign = "+" */
-  BT_COMMA,    /* comma = "," */
-  BT_VERBAR    /* vertical bar = "|" */
-};
-
-#include <stddef.h>
diff --git a/tools/sdk/include/fatfs/diskio.h b/tools/sdk/include/fatfs/diskio.h
deleted file mode 100644
index 572f03dce03..00000000000
--- a/tools/sdk/include/fatfs/diskio.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*-----------------------------------------------------------------------/
-/  Low level disk interface modlue include file   (C)ChaN, 2014          /
-/-----------------------------------------------------------------------*/
-
-#ifndef _DISKIO_DEFINED
-#define _DISKIO_DEFINED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "integer.h"
-#include "sdmmc_cmd.h"
-#include "driver/sdmmc_host.h"
-
-/* Status of Disk Functions */
-typedef BYTE	DSTATUS;
-
-/* Results of Disk Functions */
-typedef enum {
-	RES_OK = 0,		/* 0: Successful */
-	RES_ERROR,		/* 1: R/W Error */
-	RES_WRPRT,		/* 2: Write Protected */
-	RES_NOTRDY,		/* 3: Not Ready */
-	RES_PARERR		/* 4: Invalid Parameter */
-} DRESULT;
-
-
-/*---------------------------------------*/
-/* Prototypes for disk control functions */
-
-
-/* Redefine names of disk IO functions to prevent name collisions */
-#define disk_initialize     ff_disk_initialize
-#define disk_status         ff_disk_status
-#define disk_read           ff_disk_read
-#define disk_write          ff_disk_write
-#define disk_ioctl          ff_disk_ioctl
-
-
-DSTATUS disk_initialize (BYTE pdrv);
-DSTATUS disk_status (BYTE pdrv);
-DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
-DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
-DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
-
-/**
- * Structure of pointers to disk IO driver functions.
- *
- * See FatFs documentation for details about these functions
- */
-typedef struct {
-    DSTATUS (*init) (BYTE pdrv);    /*!< disk initialization function */
-    DSTATUS (*status) (BYTE pdrv);  /*!< disk status check function */
-    DRESULT (*read) (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);  /*!< sector read function */
-    DRESULT (*write) (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);   /*!< sector write function */
-    DRESULT (*ioctl) (BYTE pdrv, BYTE cmd, void* buff); /*!< function to get info about disk and do some misc operations */
-} ff_diskio_impl_t;
-
-/**
- * Register or unregister diskio driver for given drive number.
- *
- * When FATFS library calls one of disk_xxx functions for driver number pdrv,
- * corresponding function in discio_impl for given pdrv will be called.
- *
- * @param pdrv drive number
- * @param discio_impl   pointer to ff_diskio_impl_t structure with diskio functions
- *                      or NULL to unregister and free previously registered drive
- */
-void ff_diskio_register(BYTE pdrv, const ff_diskio_impl_t* discio_impl);
-
-#define ff_diskio_unregister(pdrv_) ff_diskio_register(pdrv_, NULL)
-
-/**
- * Register SD/MMC diskio driver
- *
- * @param pdrv  drive number
- * @param card  pointer to sdmmc_card_t structure describing a card; card should be initialized before calling f_mount.
- */
-void ff_diskio_register_sdmmc(BYTE pdrv, sdmmc_card_t* card);
-
-/**
- * Get next available drive number
- *
- * @param   out_pdrv            pointer to the byte to set if successful
- *
- * @return  ESP_OK              on success
- *          ESP_ERR_NOT_FOUND   if all drives are attached
- */
-esp_err_t ff_diskio_get_drive(BYTE* out_pdrv);
-
-/* Disk Status Bits (DSTATUS) */
-
-#define STA_NOINIT		0x01	/* Drive not initialized */
-#define STA_NODISK		0x02	/* No medium in the drive */
-#define STA_PROTECT		0x04	/* Write protected */
-
-
-/* Command code for disk_ioctrl fucntion */
-
-/* Generic command (Used by FatFs) */
-#define CTRL_SYNC			0	/* Complete pending write process (needed at _FS_READONLY == 0) */
-#define GET_SECTOR_COUNT	1	/* Get media size (needed at _USE_MKFS == 1) */
-#define GET_SECTOR_SIZE		2	/* Get sector size (needed at _MAX_SS != _MIN_SS) */
-#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at _USE_MKFS == 1) */
-#define CTRL_TRIM			4	/* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
-
-/* Generic command (Not used by FatFs) */
-#define CTRL_POWER			5	/* Get/Set power status */
-#define CTRL_LOCK			6	/* Lock/Unlock media removal */
-#define CTRL_EJECT			7	/* Eject media */
-#define CTRL_FORMAT			8	/* Create physical format on the media */
-
-/* MMC/SDC specific ioctl command */
-#define MMC_GET_TYPE		10	/* Get card type */
-#define MMC_GET_CSD			11	/* Get CSD */
-#define MMC_GET_CID			12	/* Get CID */
-#define MMC_GET_OCR			13	/* Get OCR */
-#define MMC_GET_SDSTAT		14	/* Get SD status */
-#define ISDIO_READ			55	/* Read data form SD iSDIO register */
-#define ISDIO_WRITE			56	/* Write data to SD iSDIO register */
-#define ISDIO_MRITE			57	/* Masked write data to SD iSDIO register */
-
-/* ATA/CF specific ioctl command */
-#define ATA_GET_REV			20	/* Get F/W revision */
-#define ATA_GET_MODEL		21	/* Get model name */
-#define ATA_GET_SN			22	/* Get serial number */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/fatfs/diskio_rawflash.h b/tools/sdk/include/fatfs/diskio_rawflash.h
deleted file mode 100644
index a7b61a4708a..00000000000
--- a/tools/sdk/include/fatfs/diskio_rawflash.h
+++ /dev/null
@@ -1,38 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DISKIO_RAWFLASH_DEFINED
-#define _DISKIO_RAWFLASH_DEFINED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "integer.h"
-#include "esp_partition.h"
-
-/**
- * Register spi flash partition
- *
- * @param pdrv  drive number
- * @param part_handle  pointer to raw flash partition.
- */
-esp_err_t ff_diskio_register_raw_partition(BYTE pdrv, const esp_partition_t* part_handle);
-BYTE ff_diskio_get_pdrv_raw(const esp_partition_t* part_handle);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _DISKIO_RAWFLASH_DEFINED
diff --git a/tools/sdk/include/fatfs/diskio_wl.h b/tools/sdk/include/fatfs/diskio_wl.h
deleted file mode 100644
index 9abff7ae06d..00000000000
--- a/tools/sdk/include/fatfs/diskio_wl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DISKIO_WL_DEFINED
-#define _DISKIO_WL_DEFINED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "integer.h"
-#include "wear_levelling.h"
-
-
-/**
- * Register spi flash partition 
- *
- * @param pdrv  drive number
- * @param flash_handle  handle of the wear levelling partition.
- */
-esp_err_t ff_diskio_register_wl_partition(BYTE pdrv, wl_handle_t flash_handle);
-BYTE ff_diskio_get_pdrv_wl(wl_handle_t flash_handle);
-void ff_diskio_clear_pdrv_wl(wl_handle_t flash_handle);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _DISKIO_WL_DEFINED
diff --git a/tools/sdk/include/fatfs/esp_vfs_fat.h b/tools/sdk/include/fatfs/esp_vfs_fat.h
deleted file mode 100644
index a2a05951e18..00000000000
--- a/tools/sdk/include/fatfs/esp_vfs_fat.h
+++ /dev/null
@@ -1,251 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-#include <stddef.h>
-#include "esp_err.h"
-#include "driver/gpio.h"
-#include "driver/sdmmc_types.h"
-#include "driver/sdmmc_host.h"
-#include "driver/sdspi_host.h"
-#include "ff.h"
-#include "wear_levelling.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Register FATFS with VFS component
- *
- * This function registers given FAT drive in VFS, at the specified base path.
- * If only one drive is used, fat_drive argument can be an empty string.
- * Refer to FATFS library documentation on how to specify FAT drive.
- * This function also allocates FATFS structure which should be used for f_mount
- * call.
- *
- * @note This function doesn't mount the drive into FATFS, it just connects
- *       POSIX and C standard library IO function with FATFS. You need to mount
- *       desired drive into FATFS separately.
- *
- * @param base_path  path prefix where FATFS should be registered
- * @param fat_drive  FATFS drive specification; if only one drive is used, can be an empty string
- * @param max_files  maximum number of files which can be open at the same time
- * @param[out] out_fs  pointer to FATFS structure which can be used for FATFS f_mount call is returned via this argument.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if esp_vfs_fat_register was already called
- *      - ESP_ERR_NO_MEM if not enough memory or too many VFSes already registered
- */
-esp_err_t esp_vfs_fat_register(const char* base_path, const char* fat_drive,
-        size_t max_files, FATFS** out_fs);
-
-/**
- * @brief Un-register FATFS from VFS
- *
- * @note FATFS structure returned by esp_vfs_fat_register is destroyed after
- *       this call. Make sure to call f_mount function to unmount it before
- *       calling esp_vfs_fat_unregister.
- *       This function is left for compatibility and will be changed in
- *       future versions to accept base_path and replace the method below
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if FATFS is not registered in VFS
- */
-esp_err_t esp_vfs_fat_unregister() __attribute__((deprecated));
-
-/**
- * @brief Un-register FATFS from VFS
- *
- * @note FATFS structure returned by esp_vfs_fat_register is destroyed after
- *       this call. Make sure to call f_mount function to unmount it before
- *       calling esp_vfs_fat_unregister_ctx.
- *       Difference between this function and the one above is that this one
- *       will release the correct drive, while the one above will release
- *       the last registered one
- *
- * @param base_path     path prefix where FATFS is registered. This is the same
- *                      used when esp_vfs_fat_register was called
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if FATFS is not registered in VFS
- */
-esp_err_t esp_vfs_fat_unregister_path(const char* base_path);
-
-
-/**
- * @brief Configuration arguments for esp_vfs_fat_sdmmc_mount and esp_vfs_fat_spiflash_mount functions
- */
-typedef struct {
-    /**
-     * If FAT partition can not be mounted, and this parameter is true,
-     * create partition table and format the filesystem.
-     */
-    bool format_if_mount_failed;
-    int max_files;                  ///< Max number of open files
-    /**
-     * If format_if_mount_failed is set, and mount fails, format the card
-     * with given allocation unit size. Must be a power of 2, between sector
-     * size and 128 * sector size.
-     * For SD cards, sector size is always 512 bytes. For wear_levelling,
-     * sector size is determined by CONFIG_WL_SECTOR_SIZE option.
-     *
-     * Using larger allocation unit size will result in higher read/write
-     * performance and higher overhead when storing small files.
-     *
-     * Setting this field to 0 will result in allocation unit set to the
-     * sector size.
-     */
-    size_t allocation_unit_size;
-} esp_vfs_fat_mount_config_t;
-
-// Compatibility definition
-typedef esp_vfs_fat_mount_config_t esp_vfs_fat_sdmmc_mount_config_t;
-
-/**
- * @brief Convenience function to get FAT filesystem on SD card registered in VFS
- *
- * This is an all-in-one function which does the following:
- * - initializes SDMMC driver or SPI driver with configuration in host_config
- * - initializes SD card with configuration in slot_config
- * - mounts FAT partition on SD card using FATFS library, with configuration in mount_config
- * - registers FATFS library with VFS, with prefix given by base_prefix variable
- *
- * This function is intended to make example code more compact.
- * For real world applications, developers should implement the logic of
- * probing SD card, locating and mounting partition, and registering FATFS in VFS,
- * with proper error checking and handling of exceptional conditions.
- *
- * @param base_path     path where partition should be registered (e.g. "/sdcard")
- * @param host_config   Pointer to structure describing SDMMC host. When using
- *                      SDMMC peripheral, this structure can be initialized using
- *                      SDMMC_HOST_DEFAULT() macro. When using SPI peripheral,
- *                      this structure can be initialized using SDSPI_HOST_DEFAULT()
- *                      macro.
- * @param slot_config   Pointer to structure with slot configuration.
- *                      For SDMMC peripheral, pass a pointer to sdmmc_slot_config_t
- *                      structure initialized using SDMMC_SLOT_CONFIG_DEFAULT.
- *                      For SPI peripheral, pass a pointer to sdspi_slot_config_t
- *                      structure initialized using SDSPI_SLOT_CONFIG_DEFAULT.
- * @param mount_config  pointer to structure with extra parameters for mounting FATFS
- * @param[out] out_card  if not NULL, pointer to the card information structure will be returned via this argument
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if esp_vfs_fat_sdmmc_mount was already called
- *      - ESP_ERR_NO_MEM if memory can not be allocated
- *      - ESP_FAIL if partition can not be mounted
- *      - other error codes from SDMMC or SPI drivers, SDMMC protocol, or FATFS drivers
- */
-esp_err_t esp_vfs_fat_sdmmc_mount(const char* base_path,
-    const sdmmc_host_t* host_config,
-    const void* slot_config,
-    const esp_vfs_fat_mount_config_t* mount_config,
-    sdmmc_card_t** out_card);
-
-/**
- * @brief Unmount FAT filesystem and release resources acquired using esp_vfs_fat_sdmmc_mount
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if esp_vfs_fat_sdmmc_mount hasn't been called
- */
-esp_err_t esp_vfs_fat_sdmmc_unmount();
-
-/**
- * @brief Convenience function to initialize FAT filesystem in SPI flash and register it in VFS
- *
- * This is an all-in-one function which does the following:
- *
- * - finds the partition with defined partition_label. Partition label should be
- *   configured in the partition table.
- * - initializes flash wear levelling library on top of the given partition
- * - mounts FAT partition using FATFS library on top of flash wear levelling
- *   library
- * - registers FATFS library with VFS, with prefix given by base_prefix variable
- *
- * This function is intended to make example code more compact.
- *
- * @param base_path        path where FATFS partition should be mounted (e.g. "/spiflash")
- * @param partition_label  label of the partition which should be used
- * @param mount_config     pointer to structure with extra parameters for mounting FATFS
- * @param[out] wl_handle   wear levelling driver handle
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NOT_FOUND if the partition table does not contain FATFS partition with given label
- *      - ESP_ERR_INVALID_STATE if esp_vfs_fat_spiflash_mount was already called
- *      - ESP_ERR_NO_MEM if memory can not be allocated
- *      - ESP_FAIL if partition can not be mounted
- *      - other error codes from wear levelling library, SPI flash driver, or FATFS drivers
- */
-esp_err_t esp_vfs_fat_spiflash_mount(const char* base_path,
-    const char* partition_label,
-    const esp_vfs_fat_mount_config_t* mount_config,
-    wl_handle_t* wl_handle);
-
-/**
- * @brief Unmount FAT filesystem and release resources acquired using esp_vfs_fat_spiflash_mount
- *
- * @param base_path  path where partition should be registered (e.g. "/spiflash")
- * @param wl_handle  wear levelling driver handle returned by esp_vfs_fat_spiflash_mount
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if esp_vfs_fat_spiflash_mount hasn't been called
- */
- esp_err_t esp_vfs_fat_spiflash_unmount(const char* base_path, wl_handle_t wl_handle);
-
-
-/**
- * @brief Convenience function to initialize read-only FAT filesystem and register it in VFS
- *
- * This is an all-in-one function which does the following:
- *
- * - finds the partition with defined partition_label. Partition label should be
- *   configured in the partition table.
- * - mounts FAT partition using FATFS library
- * - registers FATFS library with VFS, with prefix given by base_prefix variable
- *
- * @note Wear levelling is not used when FAT is mounted in read-only mode using this function.
- *
- * @param base_path        path where FATFS partition should be mounted (e.g. "/spiflash")
- * @param partition_label  label of the partition which should be used
- * @param mount_config     pointer to structure with extra parameters for mounting FATFS
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NOT_FOUND if the partition table does not contain FATFS partition with given label
- *      - ESP_ERR_INVALID_STATE if esp_vfs_fat_rawflash_mount was already called for the same partition
- *      - ESP_ERR_NO_MEM if memory can not be allocated
- *      - ESP_FAIL if partition can not be mounted
- *      - other error codes from SPI flash driver, or FATFS drivers
- */
-esp_err_t esp_vfs_fat_rawflash_mount(const char* base_path,
-    const char* partition_label,
-    const esp_vfs_fat_mount_config_t* mount_config);
-
-/**
- * @brief Unmount FAT filesystem and release resources acquired using esp_vfs_fat_rawflash_mount
- *
- * @param base_path  path where partition should be registered (e.g. "/spiflash")
- * @param partition_label label of partition to be unmounted
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_STATE if esp_vfs_fat_spiflash_mount hasn't been called
- */
- esp_err_t esp_vfs_fat_rawflash_unmount(const char* base_path, const char* partition_label);
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/fatfs/ff.h b/tools/sdk/include/fatfs/ff.h
deleted file mode 100644
index 55c1329827a..00000000000
--- a/tools/sdk/include/fatfs/ff.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*----------------------------------------------------------------------------/
-/  FatFs - Generic FAT Filesystem module  R0.13a                              /
-/-----------------------------------------------------------------------------/
-/
-/ Copyright (C) 2017, ChaN, all right reserved.
-/
-/ FatFs module is an open source software. Redistribution and use of FatFs in
-/ source and binary forms, with or without modification, are permitted provided
-/ that the following condition is met:
-
-/ 1. Redistributions of source code must retain the above copyright notice,
-/    this condition and the following disclaimer.
-/
-/ This software is provided by the copyright holder and contributors "AS IS"
-/ and any warranties related to this software are DISCLAIMED.
-/ The copyright owner or contributors be NOT LIABLE for any damages caused
-/ by use of this software.
-/
-/----------------------------------------------------------------------------*/
-
-
-#ifndef FF_DEFINED
-#define FF_DEFINED	89352	/* Revision ID */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "integer.h"	/* Basic integer types */
-#include "ffconf.h"		/* FatFs configuration options */
-
-#if FF_DEFINED != FFCONF_DEF
-#error Wrong configuration file (ffconf.h).
-#endif
-
-#ifdef FF_DEFINE_DIR
-#define FF_DIR DIR
-#endif
-
-
-/* Definitions of volume management */
-
-#if FF_MULTI_PARTITION		/* Multiple partition configuration */
-typedef struct {
-	BYTE pd;	/* Physical drive number */
-	BYTE pt;	/* Partition: 0:Auto detect, 1-4:Forced partition) */
-} PARTITION;
-extern PARTITION VolToPart[];	/* Volume - Partition resolution table */
-#endif
-
-
-
-/* Type of path name strings on FatFs API */
-
-#ifndef _INC_TCHAR
-#define _INC_TCHAR
-
-#if FF_USE_LFN && FF_LFN_UNICODE == 1 	/* Unicode in UTF-16 encoding */
-typedef WCHAR TCHAR;
-#define _T(x) L ## x
-#define _TEXT(x) L ## x
-#elif FF_USE_LFN && FF_LFN_UNICODE == 2	/* Unicode in UTF-8 encoding */
-typedef char TCHAR;
-#define _T(x) u8 ## x
-#define _TEXT(x) u8 ## x
-#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 2)
-#error Wrong FF_LFN_UNICODE setting
-#else									/* ANSI/OEM code in SBCS/DBCS */
-typedef char TCHAR;
-#define _T(x) x
-#define _TEXT(x) x
-#endif
-
-#endif
-
-
-
-/* Type of file size variables */
-
-#if FF_FS_EXFAT
-typedef QWORD FSIZE_t;
-#else
-typedef DWORD FSIZE_t;
-#endif
-
-
-
-/* Filesystem object structure (FATFS) */
-
-typedef struct {
-	BYTE	fs_type;		/* Filesystem type (0:N/A) */
-	BYTE	pdrv;			/* Physical drive number */
-	BYTE	n_fats;			/* Number of FATs (1 or 2) */
-	BYTE	wflag;			/* win[] flag (b0:dirty) */
-	BYTE	fsi_flag;		/* FSINFO flags (b7:disabled, b0:dirty) */
-	WORD	id;				/* Volume mount ID */
-	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
-	WORD	csize;			/* Cluster size [sectors] */
-#if FF_MAX_SS != FF_MIN_SS
-	WORD	ssize;			/* Sector size (512, 1024, 2048 or 4096) */
-#endif
-#if FF_USE_LFN
-	WCHAR*	lfnbuf;			/* LFN working buffer */
-#endif
-#if FF_FS_EXFAT
-	BYTE*	dirbuf;			/* Directory entry block scratchpad buffer for exFAT */
-#endif
-#if FF_FS_REENTRANT
-	FF_SYNC_t	sobj;		/* Identifier of sync object */
-#endif
-#if !FF_FS_READONLY
-	DWORD	last_clst;		/* Last allocated cluster */
-	DWORD	free_clst;		/* Number of free clusters */
-#endif
-#if FF_FS_RPATH
-	DWORD	cdir;			/* Current directory start cluster (0:root) */
-#if FF_FS_EXFAT
-	DWORD	cdc_scl;		/* Containing directory start cluster (invalid when cdir is 0) */
-	DWORD	cdc_size;		/* b31-b8:Size of containing directory, b7-b0: Chain status */
-	DWORD	cdc_ofs;		/* Offset in the containing directory (invalid when cdir is 0) */
-#endif
-#endif
-	DWORD	n_fatent;		/* Number of FAT entries (number of clusters + 2) */
-	DWORD	fsize;			/* Size of an FAT [sectors] */
-	DWORD	volbase;		/* Volume base sector */
-	DWORD	fatbase;		/* FAT base sector */
-	DWORD	dirbase;		/* Root directory base sector/cluster */
-	DWORD	database;		/* Data base sector */
-	DWORD	winsect;		/* Current sector appearing in the win[] */
-	BYTE	win[FF_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
-} FATFS;
-
-
-
-/* Object ID and allocation information (FFOBJID) */
-
-typedef struct {
-	FATFS*	fs;				/* Pointer to the hosting volume of this object */
-	WORD	id;				/* Hosting volume mount ID */
-	BYTE	attr;			/* Object attribute */
-	BYTE	stat;			/* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */
-	DWORD	sclust;			/* Object data start cluster (0:no cluster or root directory) */
-	FSIZE_t	objsize;		/* Object size (valid when sclust != 0) */
-#if FF_FS_EXFAT
-	DWORD	n_cont;			/* Size of first fragment - 1 (valid when stat == 3) */
-	DWORD	n_frag;			/* Size of last fragment needs to be written to FAT (valid when not zero) */
-	DWORD	c_scl;			/* Containing directory start cluster (valid when sclust != 0) */
-	DWORD	c_size;			/* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
-	DWORD	c_ofs;			/* Offset in the containing directory (valid when file object and sclust != 0) */
-#endif
-#if FF_FS_LOCK
-	UINT	lockid;			/* File lock ID origin from 1 (index of file semaphore table Files[]) */
-#endif
-} FFOBJID;
-
-
-
-/* File object structure (FIL) */
-
-typedef struct {
-	FFOBJID	obj;			/* Object identifier (must be the 1st member to detect invalid object pointer) */
-	BYTE	flag;			/* File status flags */
-	BYTE	err;			/* Abort flag (error code) */
-	FSIZE_t	fptr;			/* File read/write pointer (Zeroed on file open) */
-	DWORD	clust;			/* Current cluster of fpter (invalid when fptr is 0) */
-	DWORD	sect;			/* Sector number appearing in buf[] (0:invalid) */
-#if !FF_FS_READONLY
-	DWORD	dir_sect;		/* Sector number containing the directory entry (not used at exFAT) */
-	BYTE*	dir_ptr;		/* Pointer to the directory entry in the win[] (not used at exFAT) */
-#endif
-#if FF_USE_FASTSEEK
-	DWORD*	cltbl;			/* Pointer to the cluster link map table (nulled on open, set by application) */
-#endif
-#if !FF_FS_TINY
-	BYTE	buf[FF_MAX_SS];	/* File private data read/write window */
-#endif
-} FIL;
-
-
-
-/* Directory object structure (FF_DIR) */
-
-typedef struct {
-	FFOBJID	obj;			/* Object identifier */
-	DWORD	dptr;			/* Current read/write offset */
-	DWORD	clust;			/* Current cluster */
-	DWORD	sect;			/* Current sector (0:Read operation has terminated) */
-	BYTE*	dir;			/* Pointer to the directory item in the win[] */
-	BYTE	fn[12];			/* SFN (in/out) {body[8],ext[3],status[1]} */
-#if FF_USE_LFN
-	DWORD	blk_ofs;		/* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
-#endif
-#if FF_USE_FIND
-	const TCHAR* pat;		/* Pointer to the name matching pattern */
-#endif
-} FF_DIR;
-
-
-
-/* File information structure (FILINFO) */
-
-typedef struct {
-	FSIZE_t	fsize;			/* File size */
-	WORD	fdate;			/* Modified date */
-	WORD	ftime;			/* Modified time */
-	BYTE	fattrib;		/* File attribute */
-#if FF_USE_LFN
-	TCHAR	altname[FF_SFN_BUF + 1];/* Altenative file name */
-	TCHAR	fname[FF_LFN_BUF + 1];	/* Primary file name */
-#else
-	TCHAR	fname[12 + 1];	/* File name */
-#endif
-} FILINFO;
-
-
-
-/* File function return code (FRESULT) */
-
-typedef enum {
-	FR_OK = 0,				/* (0) Succeeded */
-	FR_DISK_ERR,			/* (1) A hard error occurred in the low level disk I/O layer */
-	FR_INT_ERR,				/* (2) Assertion failed */
-	FR_NOT_READY,			/* (3) The physical drive cannot work */
-	FR_NO_FILE,				/* (4) Could not find the file */
-	FR_NO_PATH,				/* (5) Could not find the path */
-	FR_INVALID_NAME,		/* (6) The path name format is invalid */
-	FR_DENIED,				/* (7) Access denied due to prohibited access or directory full */
-	FR_EXIST,				/* (8) Access denied due to prohibited access */
-	FR_INVALID_OBJECT,		/* (9) The file/directory object is invalid */
-	FR_WRITE_PROTECTED,		/* (10) The physical drive is write protected */
-	FR_INVALID_DRIVE,		/* (11) The logical drive number is invalid */
-	FR_NOT_ENABLED,			/* (12) The volume has no work area */
-	FR_NO_FILESYSTEM,		/* (13) There is no valid FAT volume */
-	FR_MKFS_ABORTED,		/* (14) The f_mkfs() aborted due to any problem */
-	FR_TIMEOUT,				/* (15) Could not get a grant to access the volume within defined period */
-	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
-	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
-	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > FF_FS_LOCK */
-	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
-} FRESULT;
-
-
-
-/*--------------------------------------------------------------*/
-/* FatFs module application interface                           */
-
-FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a file */
-FRESULT f_close (FIL* fp);											/* Close an open file object */
-FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
-FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
-FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
-FRESULT f_truncate (FIL* fp);										/* Truncate the file */
-FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
-FRESULT f_opendir (FF_DIR* dp, const TCHAR* path);						/* Open a directory */
-FRESULT f_closedir (FF_DIR* dp);										/* Close an open directory */
-FRESULT f_readdir (FF_DIR* dp, FILINFO* fno);							/* Read a directory item */
-FRESULT f_findfirst (FF_DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
-FRESULT f_findnext (FF_DIR* dp, FILINFO* fno);							/* Find next file */
-FRESULT f_mkdir (const TCHAR* path);								/* Create a sub directory */
-FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
-FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new);	/* Rename/Move a file or directory */
-FRESULT f_stat (const TCHAR* path, FILINFO* fno);					/* Get file status */
-FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask);			/* Change attribute of a file/dir */
-FRESULT f_utime (const TCHAR* path, const FILINFO* fno);			/* Change timestamp of a file/dir */
-FRESULT f_chdir (const TCHAR* path);								/* Change current directory */
-FRESULT f_chdrive (const TCHAR* path);								/* Change current drive */
-FRESULT f_getcwd (TCHAR* buff, UINT len);							/* Get current directory */
-FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get number of free clusters on the drive */
-FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
-FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
-FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
-FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt);					/* Allocate a contiguous block to the file */
-FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
-FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len);	/* Create a FAT volume */
-FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work);			/* Divide a physical drive into some partitions */
-FRESULT f_setcp (WORD cp);											/* Set current code page */
-int f_putc (TCHAR c, FIL* fp);										/* Put a character to the file */
-int f_puts (const TCHAR* str, FIL* cp);								/* Put a string to the file */
-int f_printf (FIL* fp, const TCHAR* str, ...);						/* Put a formatted string to the file */
-TCHAR* f_gets (TCHAR* buff, int len, FIL* fp);						/* Get a string from the file */
-
-#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
-#define f_error(fp) ((fp)->err)
-#define f_tell(fp) ((fp)->fptr)
-#define f_size(fp) ((fp)->obj.objsize)
-#define f_rewind(fp) f_lseek((fp), 0)
-#define f_rewinddir(dp) f_readdir((dp), 0)
-#define f_rmdir(path) f_unlink(path)
-#define f_unmount(path) f_mount(0, path, 0)
-
-#ifndef EOF
-#define EOF (-1)
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Additional user defined functions                            */
-
-/* RTC function */
-#if !FF_FS_READONLY && !FF_FS_NORTC
-DWORD get_fattime (void);
-#endif
-
-/* LFN support functions */
-#if FF_USE_LFN >= 1						/* Code conversion (defined in unicode.c) */
-WCHAR ff_oem2uni (WCHAR oem, WORD cp);	/* OEM code to Unicode conversion */
-WCHAR ff_uni2oem (DWORD uni, WORD cp);	/* Unicode to OEM code conversion */
-DWORD ff_wtoupper (DWORD uni);			/* Unicode upper-case conversion */
-#endif
-#if FF_USE_LFN == 3						/* Dynamic memory allocation */
-void* ff_memalloc (UINT msize);			/* Allocate memory block */
-void ff_memfree (void* mblock);			/* Free memory block */
-#endif
-
-/* Sync functions */
-#if FF_FS_REENTRANT
-int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj);	/* Create a sync object */
-int ff_req_grant (FF_SYNC_t sobj);		/* Lock sync object */
-void ff_rel_grant (FF_SYNC_t sobj);		/* Unlock sync object */
-int ff_del_syncobj (FF_SYNC_t sobj);	/* Delete a sync object */
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Flags and offset address                                     */
-
-
-/* File access mode and open method flags (3rd argument of f_open) */
-#define	FA_READ				0x01
-#define	FA_WRITE			0x02
-#define	FA_OPEN_EXISTING	0x00
-#define	FA_CREATE_NEW		0x04
-#define	FA_CREATE_ALWAYS	0x08
-#define	FA_OPEN_ALWAYS		0x10
-#define	FA_OPEN_APPEND		0x30
-
-/* Fast seek controls (2nd argument of f_lseek) */
-#define CREATE_LINKMAP	((FSIZE_t)0 - 1)
-
-/* Format options (2nd argument of f_mkfs) */
-#define FM_FAT		0x01
-#define FM_FAT32	0x02
-#define FM_EXFAT	0x04
-#define FM_ANY		0x07
-#define FM_SFD		0x08
-
-/* Filesystem type (FATFS.fs_type) */
-#define FS_FAT12	1
-#define FS_FAT16	2
-#define FS_FAT32	3
-#define FS_EXFAT	4
-
-/* File attribute bits for directory entry (FILINFO.fattrib) */
-#define	AM_RDO	0x01	/* Read only */
-#define	AM_HID	0x02	/* Hidden */
-#define	AM_SYS	0x04	/* System */
-#define AM_DIR	0x10	/* Directory */
-#define AM_ARC	0x20	/* Archive */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* FF_DEFINED */
diff --git a/tools/sdk/include/fatfs/ffconf.h b/tools/sdk/include/fatfs/ffconf.h
deleted file mode 100644
index 9513b51608d..00000000000
--- a/tools/sdk/include/fatfs/ffconf.h
+++ /dev/null
@@ -1,311 +0,0 @@
-#include <sys/param.h>
-#include "sdkconfig.h"
-/*---------------------------------------------------------------------------/
-/  FatFs - Configuration file
-/---------------------------------------------------------------------------*/
-
-#define FFCONF_DEF 89352	/* Revision ID */
-
-/*---------------------------------------------------------------------------/
-/ Function Configurations
-/---------------------------------------------------------------------------*/
-
-#define FF_FS_READONLY	0
-/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
-/  Read-only configuration removes writing API functions, f_write(), f_sync(),
-/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
-/  and optional writing functions as well. */
-
-
-#define FF_FS_MINIMIZE	0
-/* This option defines minimization level to remove some basic API functions.
-/
-/   0: Basic functions are fully enabled.
-/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
-/      are removed.
-/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
-/   3: f_lseek() function is removed in addition to 2. */
-
-
-#define FF_USE_STRFUNC	0
-/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
-/
-/  0: Disable string functions.
-/  1: Enable without LF-CRLF conversion.
-/  2: Enable with LF-CRLF conversion. */
-
-
-#define FF_USE_FIND		0
-/* This option switches filtered directory read functions, f_findfirst() and
-/  f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
-
-
-#define FF_USE_MKFS		1
-/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
-
-
-#define FF_USE_FASTSEEK	0
-/* This option switches fast seek function. (0:Disable or 1:Enable) */
-
-
-#define FF_USE_EXPAND	0
-/* This option switches f_expand function. (0:Disable or 1:Enable) */
-
-
-#define FF_USE_CHMOD	1
-/* This option switches attribute manipulation functions, f_chmod() and f_utime().
-/  (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
-
-
-#define FF_USE_LABEL	0
-/* This option switches volume label functions, f_getlabel() and f_setlabel().
-/  (0:Disable or 1:Enable) */
-
-
-#define FF_USE_FORWARD	0
-/* This option switches f_forward() function. (0:Disable or 1:Enable) */
-
-
-/*---------------------------------------------------------------------------/
-/ Locale and Namespace Configurations
-/---------------------------------------------------------------------------*/
-
-#define FF_CODE_PAGE	CONFIG_FATFS_CODEPAGE
-/* This option specifies the OEM code page to be used on the target system.
-/  Incorrect code page setting can cause a file open failure.
-/
-/   437 - U.S.
-/   720 - Arabic
-/   737 - Greek
-/   771 - KBL
-/   775 - Baltic
-/   850 - Latin 1
-/   852 - Latin 2
-/   855 - Cyrillic
-/   857 - Turkish
-/   860 - Portuguese
-/   861 - Icelandic
-/   862 - Hebrew
-/   863 - Canadian French
-/   864 - Arabic
-/   865 - Nordic
-/   866 - Russian
-/   869 - Greek 2
-/   932 - Japanese (DBCS)
-/   936 - Simplified Chinese (DBCS)
-/   949 - Korean (DBCS)
-/   950 - Traditional Chinese (DBCS)
-/     0 - Include all code pages above and configured by f_setcp()
-*/
-
-
-#if defined(CONFIG_FATFS_LFN_STACK)
-#define FF_USE_LFN    2
-#elif defined(CONFIG_FATFS_LFN_HEAP)
-#define FF_USE_LFN    3
-#else /* CONFIG_FATFS_LFN_NONE */
-#define FF_USE_LFN    0
-#endif
-
-#ifdef CONFIG_FATFS_MAX_LFN
-#define FF_MAX_LFN    CONFIG_FATFS_MAX_LFN
-#endif
-
-/* The FF_USE_LFN switches the support for LFN (long file name).
-/
-/   0: Disable LFN. FF_MAX_LFN has no effect.
-/   1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
-/   2: Enable LFN with dynamic working buffer on the STACK.
-/   3: Enable LFN with dynamic working buffer on the HEAP.
-/
-/  To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
-/  requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
-/  additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
-/  The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
-/  be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
-/  specification.
-/  When use stack for the working buffer, take care on stack overflow. When use heap
-/  memory for the working buffer, memory management functions, ff_memalloc() and
-/  ff_memfree() in ffsystem.c, need to be added to the project. */
-
-
-#ifdef CONFIG_FATFS_API_ENCODING_UTF_8
-#define FF_LFN_UNICODE      2
-#elif defined(CONFIG_FATFS_API_ENCODING_UTF_16)
-#define FF_LFN_UNICODE      1
-#else /* CONFIG_FATFS_API_ENCODING_ANSI_OEM */
-#define FF_LFN_UNICODE      0
-#endif
-/* This option switches the character encoding on the API when LFN is enabled.
-/
-/   0: ANSI/OEM in current CP (TCHAR = char)
-/   1: Unicode in UTF-16 (TCHAR = WCHAR)
-/   2: Unicode in UTF-8 (TCHAR = char)
-/
-/  Also behavior of string I/O functions will be affected by this option.
-/  When LFN is not enabled, this option has no effect. */
-
-
-#define FF_LFN_BUF		255
-#define FF_SFN_BUF		12
-/* This set of options defines size of file name members in the FILINFO structure
-/  which is used to read out directory items. These values should be suffcient for
-/  the file names to read. The maximum possible length of the read file name depends
-/  on character encoding. When LFN is not enabled, these options have no effect. */
-
-
-#define FF_STRF_ENCODE      3
-/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
-/  f_putc(), f_puts and f_printf() convert the character encoding in it.
-/  This option selects assumption of character encoding ON THE FILE to be
-/  read/written via those functions.
-/
-/   0: ANSI/OEM in current CP
-/   1: Unicode in UTF-16LE
-/   2: Unicode in UTF-16BE
-/   3: Unicode in UTF-8
-*/
-
-
-#define FF_FS_RPATH		0
-/* This option configures support for relative path.
-/
-/   0: Disable relative path and remove related functions.
-/   1: Enable relative path. f_chdir() and f_chdrive() are available.
-/   2: f_getcwd() function is available in addition to 1.
-*/
-
-
-/*---------------------------------------------------------------------------/
-/ Drive/Volume Configurations
-/---------------------------------------------------------------------------*/
-
-#define FF_VOLUMES		2
-/* Number of volumes (logical drives) to be used. (1-10) */
-
-
-#define FF_STR_VOLUME_ID	0
-#define FF_VOLUME_STRS		"RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
-/* FF_STR_VOLUME_ID switches string support for volume ID.
-/  When FF_STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
-/  number in the path name. FF_VOLUME_STRS defines the drive ID strings for each
-/  logical drives. Number of items must be equal to FF_VOLUMES. Valid characters for
-/  the drive ID strings are: A-Z and 0-9. */
-
-
-#define FF_MULTI_PARTITION	1
-/* This option switches support for multiple volumes on the physical drive.
-/  By default (0), each logical drive number is bound to the same physical drive
-/  number and only an FAT volume found on the physical drive will be mounted.
-/  When this function is enabled (1), each logical drive number can be bound to
-/  arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
-/  funciton will be available. */
-
-/* SD card sector size */
-#define FF_SS_SDCARD      512
-/* wear_levelling library sector size */
-#define FF_SS_WL          CONFIG_WL_SECTOR_SIZE
-
-#define FF_MIN_SS     MIN(FF_SS_SDCARD, FF_SS_WL)
-#define FF_MAX_SS     MAX(FF_SS_SDCARD, FF_SS_WL)
-/* This set of options configures the range of sector size to be supported. (512,
-/  1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
-/  harddisk. But a larger value may be required for on-board flash memory and some
-/  type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
-/  for variable sector size mode and disk_ioctl() function needs to implement
-/  GET_SECTOR_SIZE command. */
-
-
-#define FF_USE_TRIM		0
-/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
-/  To enable Trim function, also CTRL_TRIM command should be implemented to the
-/  disk_ioctl() function. */
-
-
-#define FF_FS_NOFSINFO	0
-/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
-/  option, and f_getfree() function at first time after volume mount will force
-/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
-/
-/  bit0=0: Use free cluster count in the FSINFO if available.
-/  bit0=1: Do not trust free cluster count in the FSINFO.
-/  bit1=0: Use last allocated cluster number in the FSINFO if available.
-/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
-*/
-
-
-
-/*---------------------------------------------------------------------------/
-/ System Configurations
-/---------------------------------------------------------------------------*/
-
-#define FF_FS_TINY		(!CONFIG_FATFS_PER_FILE_CACHE)
-/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
-/  At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
-/  Instead of private sector buffer eliminated from the file object, common sector
-/  buffer in the filesystem object (FATFS) is used for the file data transfer. */
-
-
-#define FF_FS_EXFAT		0
-/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
-/  When enable exFAT, also LFN needs to be enabled.
-/  Note that enabling exFAT discards ANSI C (C89) compatibility. */
-
-
-#define FF_FS_NORTC		0
-#define FF_NORTC_MON	1
-#define FF_NORTC_MDAY	1
-#define FF_NORTC_YEAR	2017
-/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
-/  any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
-/  the timestamp function. All objects modified by FatFs will have a fixed timestamp
-/  defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
-/  To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
-/  added to the project to read current time form real-time clock. FF_NORTC_MON,
-/  FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
-/  These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
-
-
-#define FF_FS_LOCK		CONFIG_FATFS_FS_LOCK
-/* The option FF_FS_LOCK switches file lock function to control duplicated file open
-/  and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
-/  is 1.
-/
-/  0:  Disable file lock function. To avoid volume corruption, application program
-/      should avoid illegal open, remove and rename to the open objects.
-/  >0: Enable file lock function. The value defines how many files/sub-directories
-/      can be opened simultaneously under file lock control. Note that the file
-/      lock control is independent of re-entrancy. */
-
-
-#define FF_FS_REENTRANT	1
-#define FF_FS_TIMEOUT	(CONFIG_FATFS_TIMEOUT_MS / portTICK_PERIOD_MS)
-#define FF_SYNC_t		SemaphoreHandle_t
-/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
-/  module itself. Note that regardless of this option, file access to different
-/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
-/  and f_fdisk() function, are always not re-entrant. Only file/directory access
-/  to the same volume is under control of this function.
-/
-/   0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
-/   1: Enable re-entrancy. Also user provided synchronization handlers,
-/      ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
-/      function, must be added to the project. Samples are available in
-/      option/syscall.c.
-/
-/  The FF_FS_TIMEOUT defines timeout period in unit of time tick.
-/  The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
-/  SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
-/  included somewhere in the scope of ff.h. */
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-
-/* Some memory allocation functions are declared here in addition to ff.h, so that
-   they can be used also by external code when LFN feature is disabled.
- */
-void* ff_memalloc (UINT msize);
-void* ff_memcalloc (UINT num, UINT size);
-
-
-/*--- End of configuration options ---*/
diff --git a/tools/sdk/include/fatfs/integer.h b/tools/sdk/include/fatfs/integer.h
deleted file mode 100644
index 4fcf5c443ff..00000000000
--- a/tools/sdk/include/fatfs/integer.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*-------------------------------------------*/
-/* Integer type definitions for FatFs module */
-/*-------------------------------------------*/
-
-#ifndef FF_INTEGER
-#define FF_INTEGER
-
-#ifdef _WIN32	/* FatFs development platform */
-
-#include <windows.h>
-#include <tchar.h>
-typedef unsigned __int64 QWORD;
-
-
-#else			/* Embedded platform */
-
-/* These types MUST be 16-bit or 32-bit */
-typedef int				INT;
-typedef unsigned int	UINT;
-
-/* This type MUST be 8-bit */
-typedef unsigned char	BYTE;
-
-/* These types MUST be 16-bit */
-typedef short			SHORT;
-typedef unsigned short	WORD;
-typedef unsigned short	WCHAR;
-
-/* These types MUST be 32-bit */
-typedef long			LONG;
-typedef unsigned long	DWORD;
-
-/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
-typedef unsigned long long QWORD;
-
-#endif
-
-#endif
diff --git a/tools/sdk/include/fatfs/vfs_fat_internal.h b/tools/sdk/include/fatfs/vfs_fat_internal.h
deleted file mode 100644
index dc3bae271ca..00000000000
--- a/tools/sdk/include/fatfs/vfs_fat_internal.h
+++ /dev/null
@@ -1,30 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "esp_vfs_fat.h"
-#include <sys/param.h>
-#include <stddef.h>
-
-static inline size_t esp_vfs_fat_get_allocation_unit_size(
-        size_t sector_size, size_t requested_size)
-{
-    size_t alloc_unit_size = requested_size;
-    const size_t max_sectors_per_cylinder = 128;
-    const size_t max_size = sector_size * max_sectors_per_cylinder;
-    alloc_unit_size = MAX(alloc_unit_size, sector_size);
-    alloc_unit_size = MIN(alloc_unit_size, max_size);
-    return alloc_unit_size;
-}
diff --git a/tools/sdk/include/fb_gfx/fb_gfx.h b/tools/sdk/include/fb_gfx/fb_gfx.h
deleted file mode 100644
index 079ff7bfe4a..00000000000
--- a/tools/sdk/include/fb_gfx/fb_gfx.h
+++ /dev/null
@@ -1,44 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _FB_GFX_H_
-#define _FB_GFX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-    typedef enum {
-        FB_RGB888, FB_BGR888, FB_RGB565, FB_BGR565
-    } fb_format_t;
-
-    typedef struct {
-            int width;
-            int height;
-            int bytes_per_pixel;
-            fb_format_t format;
-            uint8_t * data;
-    } fb_data_t;
-
-    void     fb_gfx_fillRect     (fb_data_t *fb, int32_t x, int32_t y, int32_t w, int32_t h, uint32_t color);
-    void     fb_gfx_drawFastHLine(fb_data_t *fb, int32_t x, int32_t y, int32_t w, uint32_t color);
-    void     fb_gfx_drawFastVLine(fb_data_t *fb, int32_t x, int32_t y, int32_t h, uint32_t color);
-    uint8_t  fb_gfx_putc         (fb_data_t *fb, int32_t x, int32_t y, uint32_t color, unsigned char c);
-    uint32_t fb_gfx_print        (fb_data_t *fb, int32_t x, int32_t y, uint32_t color, const char * str);
-    uint32_t fb_gfx_printf       (fb_data_t *fb, int32_t x, int32_t y, uint32_t color, const char *format, ...);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FB_GFX_H_ */
diff --git a/tools/sdk/include/freemodbus/mb.h b/tools/sdk/include/freemodbus/mb.h
deleted file mode 100644
index 8d6be7b4226..00000000000
--- a/tools/sdk/include/freemodbus/mb.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/* 
- * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU.
- * Copyright (c) 2006 Christian Walter <wolti@sil.at>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * File: $Id: mb.h,v 1.17 2006/12/07 22:10:34 wolti Exp $
- */
-
-#ifndef _MB_H
-#define _MB_H
-
-#include "port.h"
-
-#ifdef __cplusplus
-PR_BEGIN_EXTERN_C
-#endif
-
-#include "mbport.h"
-#include "mbproto.h"
-
-/*! \defgroup modbus Modbus
- * \code #include "mb.h" \endcode
- *
- * This module defines the interface for the application. It contains
- * the basic functions and types required to use the Modbus protocol stack.
- * A typical application will want to call eMBInit() first. If the device
- * is ready to answer network requests it must then call eMBEnable() to activate
- * the protocol stack. In the main loop the function eMBPoll() must be called
- * periodically. The time interval between pooling depends on the configured
- * Modbus timeout. If an RTOS is available a separate task should be created
- * and the task should always call the function eMBPoll().
- *
- * \code
- * // Initialize protocol stack in RTU mode for a slave with address 10 = 0x0A
- * eMBInit( MB_RTU, 0x0A, 38400, MB_PAR_EVEN );
- * // Enable the Modbus Protocol Stack.
- * eMBEnable(  );
- * for( ;; )
- * {
- *     // Call the main polling loop of the Modbus protocol stack.
- *     eMBPoll(  );
- *     ...
- * }
- * \endcode
- */
-
-/* ----------------------- Defines ------------------------------------------*/
-
-/*! \ingroup modbus
- * \brief Use the default Modbus TCP port (502)
- */
-#define MB_TCP_PORT_USE_DEFAULT 0   
-
-/* ----------------------- Type definitions ---------------------------------*/
-
-/*! \ingroup modbus
- * \brief Modbus serial transmission modes (RTU/ASCII).
- *
- * Modbus serial supports two transmission modes. Either ASCII or RTU. RTU
- * is faster but has more hardware requirements and requires a network with
- * a low jitter. ASCII is slower and more reliable on slower links (E.g. modems)
- */
-    typedef enum
-{
-    MB_RTU,                     /*!< RTU transmission mode. */
-    MB_ASCII,                   /*!< ASCII transmission mode. */
-    MB_TCP                      /*!< TCP mode. */
-} eMBMode;
-
-/*! \ingroup modbus
- * \brief If register should be written or read.
- *
- * This value is passed to the callback functions which support either
- * reading or writing register values. Writing means that the application
- * registers should be updated and reading means that the modbus protocol
- * stack needs to know the current register values.
- *
- * \see eMBRegHoldingCB( ), eMBRegCoilsCB( ), eMBRegDiscreteCB( ) and 
- *   eMBRegInputCB( ).
- */
-typedef enum
-{
-    MB_REG_READ,                /*!< Read register values and pass to protocol stack. */
-    MB_REG_WRITE                /*!< Update register values. */
-} eMBRegisterMode;
-
-/*! \ingroup modbus
- * \brief Errorcodes used by all function in the protocol stack.
- */
-typedef enum
-{
-    MB_ENOERR,                  /*!< no error. */
-    MB_ENOREG,                  /*!< illegal register address. */
-    MB_EINVAL,                  /*!< illegal argument. */
-    MB_EPORTERR,                /*!< porting layer error. */
-    MB_ENORES,                  /*!< insufficient resources. */
-    MB_EIO,                     /*!< I/O error. */
-    MB_EILLSTATE,               /*!< protocol stack in illegal state. */
-    MB_ETIMEDOUT                /*!< timeout error occurred. */
-} eMBErrorCode;
-
-
-/* ----------------------- Function prototypes ------------------------------*/
-/*! \ingroup modbus
- * \brief Initialize the Modbus protocol stack.
- *
- * This functions initializes the ASCII or RTU module and calls the
- * init functions of the porting layer to prepare the hardware. Please
- * note that the receiver is still disabled and no Modbus frames are
- * processed until eMBEnable( ) has been called.
- *
- * \param eMode If ASCII or RTU mode should be used.
- * \param ucSlaveAddress The slave address. Only frames sent to this
- *   address or to the broadcast address are processed.
- * \param ucPort The port to use. E.g. 1 for COM1 on windows. This value
- *   is platform dependent and some ports simply choose to ignore it.
- * \param ulBaudRate The baudrate. E.g. 19200. Supported baudrates depend
- *   on the porting layer.
- * \param eParity Parity used for serial transmission.
- *
- * \return If no error occurs the function returns eMBErrorCode::MB_ENOERR.
- *   The protocol is then in the disabled state and ready for activation
- *   by calling eMBEnable( ). Otherwise one of the following error codes 
- *   is returned:
- *    - eMBErrorCode::MB_EINVAL If the slave address was not valid. Valid
- *        slave addresses are in the range 1 - 247.
- *    - eMBErrorCode::MB_EPORTERR IF the porting layer returned an error.
- */
-eMBErrorCode    eMBInit( eMBMode eMode, UCHAR ucSlaveAddress,
-                         UCHAR ucPort, ULONG ulBaudRate, eMBParity eParity );
-
-/*! \ingroup modbus
- * \brief Initialize the Modbus protocol stack for Modbus TCP.
- *
- * This function initializes the Modbus TCP Module. Please note that
- * frame processing is still disabled until eMBEnable( ) is called.
- *
- * \param usTCPPort The TCP port to listen on.
- * \return If the protocol stack has been initialized correctly the function
- *   returns eMBErrorCode::MB_ENOERR. Otherwise one of the following error
- *   codes is returned:
- *    - eMBErrorCode::MB_EINVAL If the slave address was not valid. Valid
- *        slave addresses are in the range 1 - 247.
- *    - eMBErrorCode::MB_EPORTERR IF the porting layer returned an error.
- */
-eMBErrorCode    eMBTCPInit( USHORT usTCPPort );
-
-/*! \ingroup modbus
- * \brief Release resources used by the protocol stack.
- *
- * This function disables the Modbus protocol stack and release all
- * hardware resources. It must only be called when the protocol stack 
- * is disabled. 
- *
- * \note Note all ports implement this function. A port which wants to 
- *   get an callback must define the macro MB_PORT_HAS_CLOSE to 1.
- *
- * \return If the resources where released it return eMBErrorCode::MB_ENOERR.
- *   If the protocol stack is not in the disabled state it returns
- *   eMBErrorCode::MB_EILLSTATE.
- */
-eMBErrorCode    eMBClose( void );
-
-/*! \ingroup modbus
- * \brief Enable the Modbus protocol stack.
- *
- * This function enables processing of Modbus frames. Enabling the protocol
- * stack is only possible if it is in the disabled state.
- *
- * \return If the protocol stack is now in the state enabled it returns 
- *   eMBErrorCode::MB_ENOERR. If it was not in the disabled state it 
- *   return eMBErrorCode::MB_EILLSTATE.
- */
-eMBErrorCode    eMBEnable( void );
-
-/*! \ingroup modbus
- * \brief Disable the Modbus protocol stack.
- *
- * This function disables processing of Modbus frames.
- *
- * \return If the protocol stack has been disabled it returns 
- *  eMBErrorCode::MB_ENOERR. If it was not in the enabled state it returns
- *  eMBErrorCode::MB_EILLSTATE.
- */
-eMBErrorCode    eMBDisable( void );
-
-/*! \ingroup modbus
- * \brief The main pooling loop of the Modbus protocol stack.
- *
- * This function must be called periodically. The timer interval required
- * is given by the application dependent Modbus slave timeout. Internally the
- * function calls xMBPortEventGet() and waits for an event from the receiver or
- * transmitter state machines. 
- *
- * \return If the protocol stack is not in the enabled state the function
- *   returns eMBErrorCode::MB_EILLSTATE. Otherwise it returns 
- *   eMBErrorCode::MB_ENOERR.
- */
-eMBErrorCode    eMBPoll( void );
-
-/*! \ingroup modbus
- * \brief Configure the slave id of the device.
- *
- * This function should be called when the Modbus function <em>Report Slave ID</em>
- * is enabled ( By defining MB_FUNC_OTHER_REP_SLAVEID_ENABLED in mbconfig.h ).
- *
- * \param ucSlaveID Values is returned in the <em>Slave ID</em> byte of the
- *   <em>Report Slave ID</em> response.
- * \param xIsRunning If TRUE the <em>Run Indicator Status</em> byte is set to 0xFF.
- *   otherwise the <em>Run Indicator Status</em> is 0x00.
- * \param pucAdditional Values which should be returned in the <em>Additional</em>
- *   bytes of the <em> Report Slave ID</em> response.
- * \param usAdditionalLen Length of the buffer <code>pucAdditonal</code>.
- *
- * \return If the static buffer defined by MB_FUNC_OTHER_REP_SLAVEID_BUF in
- *   mbconfig.h is to small it returns eMBErrorCode::MB_ENORES. Otherwise
- *   it returns eMBErrorCode::MB_ENOERR.
- */
-eMBErrorCode    eMBSetSlaveID( UCHAR ucSlaveID, BOOL xIsRunning,
-                               UCHAR const *pucAdditional,
-                               USHORT usAdditionalLen );
-
-/*! \ingroup modbus
- * \brief Registers a callback handler for a given function code.
- *
- * This function registers a new callback handler for a given function code.
- * The callback handler supplied is responsible for interpreting the Modbus PDU and
- * the creation of an appropriate response. In case of an error it should return
- * one of the possible Modbus exceptions which results in a Modbus exception frame
- * sent by the protocol stack. 
- *
- * \param ucFunctionCode The Modbus function code for which this handler should
- *   be registers. Valid function codes are in the range 1 to 127.
- * \param pxHandler The function handler which should be called in case
- *   such a frame is received. If \c NULL a previously registered function handler
- *   for this function code is removed.
- *
- * \return eMBErrorCode::MB_ENOERR if the handler has been installed. If no
- *   more resources are available it returns eMBErrorCode::MB_ENORES. In this
- *   case the values in mbconfig.h should be adjusted. If the argument was not
- *   valid it returns eMBErrorCode::MB_EINVAL.
- */
-eMBErrorCode    eMBRegisterCB( UCHAR ucFunctionCode, 
-                               pxMBFunctionHandler pxHandler );
-
-/* ----------------------- Callback -----------------------------------------*/
-
-/*! \defgroup modbus_registers Modbus Registers
- * \code #include "mb.h" \endcode
- * The protocol stack does not internally allocate any memory for the
- * registers. This makes the protocol stack very small and also usable on
- * low end targets. In addition the values don't have to be in the memory
- * and could for example be stored in a flash.<br>
- * Whenever the protocol stack requires a value it calls one of the callback
- * function with the register address and the number of registers to read
- * as an argument. The application should then read the actual register values
- * (for example the ADC voltage) and should store the result in the supplied
- * buffer.<br>
- * If the protocol stack wants to update a register value because a write
- * register function was received a buffer with the new register values is
- * passed to the callback function. The function should then use these values
- * to update the application register values.
- */
-
-/*! \ingroup modbus_registers
- * \brief Callback function used if the value of a <em>Input Register</em>
- *   is required by the protocol stack. The starting register address is given
- *   by \c usAddress and the last register is given by <tt>usAddress +
- *   usNRegs - 1</tt>.
- *
- * \param pucRegBuffer A buffer where the callback function should write
- *   the current value of the modbus registers to.
- * \param usAddress The starting address of the register. Input registers
- *   are in the range 1 - 65535.
- * \param usNRegs Number of registers the callback function must supply.
- *
- * \return The function must return one of the following error codes:
- *   - eMBErrorCode::MB_ENOERR If no error occurred. In this case a normal
- *       Modbus response is sent.
- *   - eMBErrorCode::MB_ENOREG If the application can not supply values
- *       for registers within this range. In this case a 
- *       <b>ILLEGAL DATA ADDRESS</b> exception frame is sent as a response.
- *   - eMBErrorCode::MB_ETIMEDOUT If the requested register block is
- *       currently not available and the application dependent response
- *       timeout would be violated. In this case a <b>SLAVE DEVICE BUSY</b>
- *       exception is sent as a response.
- *   - eMBErrorCode::MB_EIO If an unrecoverable error occurred. In this case
- *       a <b>SLAVE DEVICE FAILURE</b> exception is sent as a response.
- */
-eMBErrorCode    eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress,
-                               USHORT usNRegs );
-
-/*! \ingroup modbus_registers
- * \brief Callback function used if a <em>Holding Register</em> value is
- *   read or written by the protocol stack. The starting register address
- *   is given by \c usAddress and the last register is given by
- *   <tt>usAddress + usNRegs - 1</tt>.
- *
- * \param pucRegBuffer If the application registers values should be updated the
- *   buffer points to the new registers values. If the protocol stack needs
- *   to now the current values the callback function should write them into
- *   this buffer.
- * \param usAddress The starting address of the register.
- * \param usNRegs Number of registers to read or write.
- * \param eMode If eMBRegisterMode::MB_REG_WRITE the application register 
- *   values should be updated from the values in the buffer. For example
- *   this would be the case when the Modbus master has issued an 
- *   <b>WRITE SINGLE REGISTER</b> command.
- *   If the value eMBRegisterMode::MB_REG_READ the application should copy 
- *   the current values into the buffer \c pucRegBuffer.
- *
- * \return The function must return one of the following error codes:
- *   - eMBErrorCode::MB_ENOERR If no error occurred. In this case a normal
- *       Modbus response is sent.
- *   - eMBErrorCode::MB_ENOREG If the application can not supply values
- *       for registers within this range. In this case a 
- *       <b>ILLEGAL DATA ADDRESS</b> exception frame is sent as a response.
- *   - eMBErrorCode::MB_ETIMEDOUT If the requested register block is
- *       currently not available and the application dependent response
- *       timeout would be violated. In this case a <b>SLAVE DEVICE BUSY</b>
- *       exception is sent as a response.
- *   - eMBErrorCode::MB_EIO If an unrecoverable error occurred. In this case
- *       a <b>SLAVE DEVICE FAILURE</b> exception is sent as a response.
- */
-eMBErrorCode    eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress,
-                                 USHORT usNRegs, eMBRegisterMode eMode );
-
-/*! \ingroup modbus_registers
- * \brief Callback function used if a <em>Coil Register</em> value is
- *   read or written by the protocol stack. If you are going to use
- *   this function you might use the functions xMBUtilSetBits(  ) and
- *   xMBUtilGetBits(  ) for working with bitfields.
- *
- * \param pucRegBuffer The bits are packed in bytes where the first coil
- *   starting at address \c usAddress is stored in the LSB of the
- *   first byte in the buffer <code>pucRegBuffer</code>.
- *   If the buffer should be written by the callback function unused
- *   coil values (I.e. if not a multiple of eight coils is used) should be set
- *   to zero.
- * \param usAddress The first coil number.
- * \param usNCoils Number of coil values requested.
- * \param eMode If eMBRegisterMode::MB_REG_WRITE the application values should
- *   be updated from the values supplied in the buffer \c pucRegBuffer.
- *   If eMBRegisterMode::MB_REG_READ the application should store the current
- *   values in the buffer \c pucRegBuffer.
- *
- * \return The function must return one of the following error codes:
- *   - eMBErrorCode::MB_ENOERR If no error occurred. In this case a normal
- *       Modbus response is sent.
- *   - eMBErrorCode::MB_ENOREG If the application does not map an coils
- *       within the requested address range. In this case a 
- *       <b>ILLEGAL DATA ADDRESS</b> is sent as a response.
- *   - eMBErrorCode::MB_ETIMEDOUT If the requested register block is
- *       currently not available and the application dependent response
- *       timeout would be violated. In this case a <b>SLAVE DEVICE BUSY</b>
- *       exception is sent as a response.
- *   - eMBErrorCode::MB_EIO If an unrecoverable error occurred. In this case
- *       a <b>SLAVE DEVICE FAILURE</b> exception is sent as a response.
- */
-eMBErrorCode    eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress,
-                               USHORT usNCoils, eMBRegisterMode eMode );
-
-/*! \ingroup modbus_registers
- * \brief Callback function used if a <em>Input Discrete Register</em> value is
- *   read by the protocol stack.
- *
- * If you are going to use his function you might use the functions
- * xMBUtilSetBits(  ) and xMBUtilGetBits(  ) for working with bitfields.
- *
- * \param pucRegBuffer The buffer should be updated with the current
- *   coil values. The first discrete input starting at \c usAddress must be
- *   stored at the LSB of the first byte in the buffer. If the requested number
- *   is not a multiple of eight the remaining bits should be set to zero.
- * \param usAddress The starting address of the first discrete input.
- * \param usNDiscrete Number of discrete input values.
- * \return The function must return one of the following error codes:
- *   - eMBErrorCode::MB_ENOERR If no error occurred. In this case a normal
- *       Modbus response is sent.
- *   - eMBErrorCode::MB_ENOREG If no such discrete inputs exists.
- *       In this case a <b>ILLEGAL DATA ADDRESS</b> exception frame is sent 
- *       as a response.
- *   - eMBErrorCode::MB_ETIMEDOUT If the requested register block is
- *       currently not available and the application dependent response
- *       timeout would be violated. In this case a <b>SLAVE DEVICE BUSY</b>
- *       exception is sent as a response.
- *   - eMBErrorCode::MB_EIO If an unrecoverable error occurred. In this case
- *       a <b>SLAVE DEVICE FAILURE</b> exception is sent as a response.
- */
-eMBErrorCode    eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress,
-                                  USHORT usNDiscrete );
-
-#ifdef __cplusplus
-PR_END_EXTERN_C
-#endif
-#endif
diff --git a/tools/sdk/include/freemodbus/mbconfig.h b/tools/sdk/include/freemodbus/mbconfig.h
deleted file mode 100644
index 54194de26d9..00000000000
--- a/tools/sdk/include/freemodbus/mbconfig.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* 
- * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU.
- * Copyright (c) 2006 Christian Walter <wolti@sil.at>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * File: $Id: mbconfig.h,v 1.15 2010/06/06 13:54:40 wolti Exp $
- */
-
-#ifndef _MB_CONFIG_H
-#define _MB_CONFIG_H
-
-#ifdef __cplusplus
-PR_BEGIN_EXTERN_C
-#endif
-/* ----------------------- Defines ------------------------------------------*/
-/*! \defgroup modbus_cfg Modbus Configuration
- *
- * Most modules in the protocol stack are completly optional and can be
- * excluded. This is specially important if target resources are very small
- * and program memory space should be saved.<br>
- *
- * All of these settings are available in the file <code>mbconfig.h</code>
- */
-/*! \addtogroup modbus_cfg
- *  @{
- */
-/*! \brief If Modbus ASCII support is enabled. */
-#define MB_ASCII_ENABLED                        (  0 )
-
-/*! \brief If Modbus RTU support is enabled. */
-#define MB_RTU_ENABLED                          (  1 )
-
-/*! \brief If Modbus TCP support is enabled. */
-#define MB_TCP_ENABLED                          (  0 )
-
-/*! \brief The character timeout value for Modbus ASCII.
- *
- * The character timeout value is not fixed for Modbus ASCII and is therefore
- * a configuration option. It should be set to the maximum expected delay
- * time of the network.
- */
-#define MB_ASCII_TIMEOUT_SEC                    (  1 )
-
-/*! \brief Timeout to wait in ASCII prior to enabling transmitter.
- *
- * If defined the function calls vMBPortSerialDelay with the argument
- * MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS to allow for a delay before
- * the serial transmitter is enabled. This is required because some
- * targets are so fast that there is no time between receiving and
- * transmitting the frame. If the master is to slow with enabling its 
- * receiver then he will not receive the response correctly.
- */
-#ifndef MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS
-#define MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS    ( 0 )
-#endif
-
-/*! \brief Maximum number of Modbus functions codes the protocol stack
- *    should support.
- *
- * The maximum number of supported Modbus functions must be greater than
- * the sum of all enabled functions in this file and custom function
- * handlers. If set to small adding more functions will fail.
- */
-#define MB_FUNC_HANDLERS_MAX                    ( 16 )
-
-/*! \brief Number of bytes which should be allocated for the <em>Report Slave ID
- *    </em>command.
- *
- * This number limits the maximum size of the additional segment in the
- * report slave id function. See eMBSetSlaveID(  ) for more information on
- * how to set this value. It is only used if MB_FUNC_OTHER_REP_SLAVEID_ENABLED
- * is set to <code>1</code>.
- */
-#define MB_FUNC_OTHER_REP_SLAVEID_BUF           ( 32 )
-
-/*! \brief If the <em>Report Slave ID</em> function should be enabled. */
-#define MB_FUNC_OTHER_REP_SLAVEID_ENABLED       (  CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT )
-
-/*! \brief If the <em>Read Input Registers</em> function should be enabled. */
-#define MB_FUNC_READ_INPUT_ENABLED              (  1 )
-
-/*! \brief If the <em>Read Holding Registers</em> function should be enabled. */
-#define MB_FUNC_READ_HOLDING_ENABLED            (  1 )
-
-/*! \brief If the <em>Write Single Register</em> function should be enabled. */
-#define MB_FUNC_WRITE_HOLDING_ENABLED           (  1 )
-
-/*! \brief If the <em>Write Multiple registers</em> function should be enabled. */
-#define MB_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED  (  1 )
-
-/*! \brief If the <em>Read Coils</em> function should be enabled. */
-#define MB_FUNC_READ_COILS_ENABLED              (  1 )
-
-/*! \brief If the <em>Write Coils</em> function should be enabled. */
-#define MB_FUNC_WRITE_COIL_ENABLED              (  1 )
-
-/*! \brief If the <em>Write Multiple Coils</em> function should be enabled. */
-#define MB_FUNC_WRITE_MULTIPLE_COILS_ENABLED    (  1 )
-
-/*! \brief If the <em>Read Discrete Inputs</em> function should be enabled. */
-#define MB_FUNC_READ_DISCRETE_INPUTS_ENABLED    (  1 )
-
-/*! \brief If the <em>Read/Write Multiple Registers</em> function should be enabled. */
-#define MB_FUNC_READWRITE_HOLDING_ENABLED       (  1 )
-
-/*! @} */
-#ifdef __cplusplus
-PR_END_EXTERN_C
-#endif
-#endif
diff --git a/tools/sdk/include/freemodbus/mbcontroller.h b/tools/sdk/include/freemodbus/mbcontroller.h
deleted file mode 100644
index 267fa34aed1..00000000000
--- a/tools/sdk/include/freemodbus/mbcontroller.h
+++ /dev/null
@@ -1,186 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-//  mbcontroller.h
-//  Implementation of the MbController
-
-#ifndef _MODBUS_CONTROLLER
-#define _MODBUS_CONTROLLER
-
-#include <stdint.h>                 // for standard int types definition
-#include <stddef.h>                 // for NULL and std defines
-#include "soc/soc.h"                // for BITN definitions
-#include "sdkconfig.h"              // for KConfig options
-#include "driver/uart.h"            // for uart port number defines
-
-/* ----------------------- Defines ------------------------------------------*/
-#define MB_INST_MIN_SIZE                    (2) // The minimal size of Modbus registers area in bytes
-#define MB_INST_MAX_SIZE                    (65535 * 2) // The maximum size of Modbus area in bytes
-
-#define MB_CONTROLLER_STACK_SIZE            (CONFIG_MB_CONTROLLER_STACK_SIZE) // Stack size for Modbus controller
-#define MB_CONTROLLER_PRIORITY              (CONFIG_MB_SERIAL_TASK_PRIO - 1) // priority of MB controller task
-#define MB_CONTROLLER_NOTIFY_QUEUE_SIZE     (CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE) // Number of messages in parameter notification queue
-#define MB_CONTROLLER_NOTIFY_TIMEOUT        (pdMS_TO_TICKS(CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT)) // notification timeout
-
-// Default port defines
-#define MB_DEVICE_ADDRESS   (1)             // Default slave device address in Modbus
-#define MB_DEVICE_SPEED     (115200)        // Default Modbus speed for now hard defined
-#define MB_UART_PORT        (UART_NUM_2)    // Default UART port number
-#define MB_PAR_INFO_TOUT    (10)            // Timeout for get parameter info
-#define MB_PARITY_NONE      (UART_PARITY_DISABLE)
-
-/**
- * @brief Event group for parameters notification
- */
-typedef enum
-{
-    MB_EVENT_NO_EVENTS = 0x00,
-    MB_EVENT_HOLDING_REG_WR = BIT0,         /*!< Modbus Event Write Holding registers. */
-    MB_EVENT_HOLDING_REG_RD = BIT1,         /*!< Modbus Event Read Holding registers. */
-    MB_EVENT_INPUT_REG_RD = BIT3,           /*!< Modbus Event Read Input registers. */
-    MB_EVENT_COILS_WR = BIT4,               /*!< Modbus Event Write Coils. */
-    MB_EVENT_COILS_RD = BIT5,               /*!< Modbus Event Read Coils. */
-    MB_EVENT_DISCRETE_RD = BIT6,            /*!< Modbus Event Read Discrete bits. */
-    MB_EVENT_STACK_STARTED = BIT7           /*!< Modbus Event Stack started */
-} mb_event_group_t;
-
-/**
- * @brief Type of Modbus parameter
- */
-typedef enum
-{
-    MB_PARAM_HOLDING,                /*!< Modbus Holding register. */
-    MB_PARAM_INPUT,                  /*!< Modbus Input register. */
-    MB_PARAM_COIL,                   /*!< Modbus Coils. */
-    MB_PARAM_DISCRETE,               /*!< Modbus Discrete bits. */
-    MB_PARAM_COUNT,
-    MB_PARAM_UNKNOWN = 0xFF
-} mb_param_type_t;
-
-/*!
- * \brief Modbus serial transmission modes (RTU/ASCII).
- */
-typedef enum
-{
-    MB_MODE_RTU,                     /*!< RTU transmission mode. */
-    MB_MODE_ASCII,                   /*!< ASCII transmission mode. */
-    MB_MODE_TCP                      /*!< TCP mode. */
-} mb_mode_type_t;
-
-/**
- * @brief Parameter access event information type
- */
-typedef struct {
-    uint32_t time_stamp;                    /*!< Timestamp of Modbus Event (uS)*/
-    uint16_t mb_offset;                     /*!< Modbus register offset */
-    mb_event_group_t type;                  /*!< Modbus event type */
-    uint8_t* address;                       /*!< Modbus data storage address */
-    size_t size;                            /*!< Modbus event register size (number of registers)*/
-} mb_param_info_t;
-
-/**
- * @brief Parameter storage area descriptor
- */
-typedef struct {
-    uint16_t start_offset;                  /*!< Modbus start address for area descriptor */
-    mb_param_type_t type;                   /*!< Type of storage area descriptor */
-    void* address;                          /*!< Instance address for storage area descriptor */
-    size_t size;                            /*!< Instance size for area descriptor (bytes) */
-} mb_register_area_descriptor_t;
-
-/**
- * @brief Device communication parameters
- */
-typedef struct {
-    mb_mode_type_t mode;                    /*!< Modbus communication mode */
-    uint8_t slave_addr;                     /*!< Modbus Slave Address */
-    uart_port_t port;                       /*!< Modbus communication port (UART) number */
-    uint32_t baudrate;                      /*!< Modbus baudrate */
-    uart_parity_t parity;                   /*!< Modbus UART parity settings */
-} mb_communication_info_t;
-
-/**
- * @brief Initialize modbus controller and stack
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t mbcontroller_init(void);
-
-/**
- * @brief Destroy Modbus controller and stack
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_FAIL Parameter error
- */
-esp_err_t mbcontroller_destroy(void);
-
-/**
- * @brief Start Modbus communication stack
- *
- * @return
- *     - ESP_OK   Success
- *     - ESP_ERR_INVALID_ARG Modbus stack start error
- */
-esp_err_t mbcontroller_start(void);
-
-/**
- * @brief Set Modbus communication parameters for the controller
- *
- * @param comm_info Communication parameters structure.
- *
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Incorrect parameter data
- */
-esp_err_t mbcontroller_setup(mb_communication_info_t comm_info);
-
-/**
- * @brief Wait for specific event on parameter change.
- *
- * @param group Group event bit mask to wait for change
- *
- * @return
- *     - mb_event_group_t event bits triggered
- */
-mb_event_group_t mbcontroller_check_event(mb_event_group_t group);
-
-/**
- * @brief Get parameter information
- *
- * @param[out] reg_info parameter info structure
- * @param timeout Timeout in milliseconds to read information from
- *                parameter queue
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_TIMEOUT Can not get data from parameter queue
- *                       or queue overflow
- */
-esp_err_t mbcontroller_get_param_info(mb_param_info_t* reg_info, uint32_t timeout);
-
-/**
- * @brief Set Modbus area descriptor
- *
- * @param descr_data Modbus registers area descriptor structure
- *
- * @return
- *     - ESP_OK: The appropriate descriptor is set
- *     - ESP_ERR_INVALID_ARG: The argument is incorrect
- */
-esp_err_t mbcontroller_set_descriptor(mb_register_area_descriptor_t descr_data);
-
-#endif
-
diff --git a/tools/sdk/include/freemodbus/mbframe.h b/tools/sdk/include/freemodbus/mbframe.h
deleted file mode 100644
index 99d59c613e3..00000000000
--- a/tools/sdk/include/freemodbus/mbframe.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* 
- * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU.
- * Copyright (c) 2006 Christian Walter <wolti@sil.at>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * File: $Id: mbframe.h,v 1.9 2006/12/07 22:10:34 wolti Exp $
- */
-
-#ifndef _MB_FRAME_H
-#define _MB_FRAME_H
-
-#ifdef __cplusplus
-PR_BEGIN_EXTERN_C
-#endif
-
-/*!
- * Constants which defines the format of a modbus frame. The example is
- * shown for a Modbus RTU/ASCII frame. Note that the Modbus PDU is not
- * dependent on the underlying transport.
- *
- * <code>
- * <------------------------ MODBUS SERIAL LINE PDU (1) ------------------->
- *              <----------- MODBUS PDU (1') ---------------->
- *  +-----------+---------------+----------------------------+-------------+
- *  | Address   | Function Code | Data                       | CRC/LRC     |
- *  +-----------+---------------+----------------------------+-------------+
- *  |           |               |                                   |
- * (2)        (3/2')           (3')                                (4)
- *
- * (1)  ... MB_SER_PDU_SIZE_MAX = 256
- * (2)  ... MB_SER_PDU_ADDR_OFF = 0
- * (3)  ... MB_SER_PDU_PDU_OFF  = 1
- * (4)  ... MB_SER_PDU_SIZE_CRC = 2
- *
- * (1') ... MB_PDU_SIZE_MAX     = 253
- * (2') ... MB_PDU_FUNC_OFF     = 0
- * (3') ... MB_PDU_DATA_OFF     = 1
- * </code>
- */
-
-/* ----------------------- Defines ------------------------------------------*/
-#define MB_PDU_SIZE_MAX     253 /*!< Maximum size of a PDU. */
-#define MB_PDU_SIZE_MIN     1   /*!< Function Code */
-#define MB_PDU_FUNC_OFF     0   /*!< Offset of function code in PDU. */
-#define MB_PDU_DATA_OFF     1   /*!< Offset for response data in PDU. */
-
-/* ----------------------- Prototypes  0-------------------------------------*/
-typedef void    ( *pvMBFrameStart ) ( void );
-
-typedef void    ( *pvMBFrameStop ) ( void );
-
-typedef eMBErrorCode( *peMBFrameReceive ) ( UCHAR * pucRcvAddress,
-                                            UCHAR ** pucFrame,
-                                            USHORT * pusLength );
-
-typedef eMBErrorCode( *peMBFrameSend ) ( UCHAR slaveAddress,
-                                         const UCHAR * pucFrame,
-                                         USHORT usLength );
-
-typedef void( *pvMBFrameClose ) ( void );
-
-#ifdef __cplusplus
-PR_END_EXTERN_C
-#endif
-#endif
diff --git a/tools/sdk/include/freemodbus/mbfunc.h b/tools/sdk/include/freemodbus/mbfunc.h
deleted file mode 100644
index aea14f75914..00000000000
--- a/tools/sdk/include/freemodbus/mbfunc.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* 
- * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU.
- * Copyright (c) 2006 Christian Walter <wolti@sil.at>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * File: $Id: mbfunc.h,v 1.12 2006/12/07 22:10:34 wolti Exp $
- */
-
-#ifndef _MB_FUNC_H
-#define _MB_FUNC_H
-
-#ifdef __cplusplus
-PR_BEGIN_EXTERN_C
-#endif
-#if MB_FUNC_OTHER_REP_SLAVEID_BUF > 0
-    eMBException eMBFuncReportSlaveID( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#if MB_FUNC_READ_INPUT_ENABLED > 0
-eMBException    eMBFuncReadInputRegister( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#if MB_FUNC_READ_HOLDING_ENABLED > 0
-eMBException    eMBFuncReadHoldingRegister( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#if MB_FUNC_WRITE_HOLDING_ENABLED > 0
-eMBException    eMBFuncWriteHoldingRegister( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#if MB_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED > 0
-eMBException    eMBFuncWriteMultipleHoldingRegister( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#if MB_FUNC_READ_COILS_ENABLED > 0
-eMBException    eMBFuncReadCoils( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#if MB_FUNC_WRITE_COIL_ENABLED > 0
-eMBException    eMBFuncWriteCoil( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#if MB_FUNC_WRITE_MULTIPLE_COILS_ENABLED > 0
-eMBException    eMBFuncWriteMultipleCoils( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#if MB_FUNC_READ_DISCRETE_INPUTS_ENABLED > 0
-eMBException    eMBFuncReadDiscreteInputs( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#if MB_FUNC_READWRITE_HOLDING_ENABLED > 0
-eMBException    eMBFuncReadWriteMultipleHoldingRegister( UCHAR * pucFrame, USHORT * usLen );
-#endif
-
-#ifdef __cplusplus
-PR_END_EXTERN_C
-#endif
-#endif
diff --git a/tools/sdk/include/freemodbus/mbport.h b/tools/sdk/include/freemodbus/mbport.h
deleted file mode 100644
index 8d334d0e0b5..00000000000
--- a/tools/sdk/include/freemodbus/mbport.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* 
- * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU.
- * Copyright (c) 2006 Christian Walter <wolti@sil.at>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * File: $Id: mbport.h,v 1.19 2010/06/06 13:54:40 wolti Exp $
- */
-
-#ifndef _MB_PORT_H
-#define _MB_PORT_H
-
-#ifdef __cplusplus
-PR_BEGIN_EXTERN_C
-#endif
-
-/* ----------------------- Type definitions ---------------------------------*/
-
-typedef enum
-{
-    EV_READY,                   /*!< Startup finished. */
-    EV_FRAME_RECEIVED,          /*!< Frame received. */
-    EV_EXECUTE,                 /*!< Execute function. */
-    EV_FRAME_SENT               /*!< Frame sent. */
-} eMBEventType;
-
-/*! \ingroup modbus
- * \brief Parity used for characters in serial mode.
- *
- * The parity which should be applied to the characters sent over the serial
- * link. Please note that this values are actually passed to the porting
- * layer and therefore not all parity modes might be available.
- */
-typedef enum
-{
-    MB_PAR_NONE,                /*!< No parity. */
-    MB_PAR_ODD,                 /*!< Odd parity. */
-    MB_PAR_EVEN                 /*!< Even parity. */
-} eMBParity;
-
-/* ----------------------- Supporting functions -----------------------------*/
-BOOL            xMBPortEventInit( void );
-
-BOOL            xMBPortEventPost( eMBEventType eEvent );
-
-BOOL            xMBPortEventGet(  /*@out@ */ eMBEventType * eEvent );
-
-/* ----------------------- Serial port functions ----------------------------*/
-
-BOOL            xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate,
-                                   UCHAR ucDataBits, eMBParity eParity );
-
-void            vMBPortClose( void );
-
-void            xMBPortSerialClose( void );
-
-void            vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable );
-
-BOOL            xMBPortSerialGetByte( CHAR * pucByte );
-
-BOOL            xMBPortSerialPutByte( CHAR ucByte );
-
-/* ----------------------- Timers functions ---------------------------------*/
-BOOL            xMBPortTimersInit( USHORT usTimeOut50us );
-
-void            xMBPortTimersClose( void );
-
-void            vMBPortTimersEnable( void );
-
-void            vMBPortTimersDisable( void );
-
-void            vMBPortTimersDelay( USHORT usTimeOutMS );
-
-/* ----------------------- Callback for the protocol stack ------------------*/
-/*!
- * \brief Callback function for the porting layer when a new byte is
- *   available.
- *
- * Depending upon the mode this callback function is used by the RTU or
- * ASCII transmission layers. In any case a call to xMBPortSerialGetByte()
- * must immediately return a new character.
- *
- * \return <code>TRUE</code> if a event was posted to the queue because
- *   a new byte was received. The port implementation should wake up the
- *   tasks which are currently blocked on the eventqueue.
- */
-extern          BOOL( *pxMBFrameCBByteReceived ) ( void );
-
-extern          BOOL( *pxMBFrameCBTransmitterEmpty ) ( void );
-
-extern          BOOL( *pxMBPortCBTimerExpired ) ( void );
-
-/* ----------------------- TCP port functions -------------------------------*/
-#if MB_TCP_ENABLED == 1
-BOOL            xMBTCPPortInit( USHORT usTCPPort );
-
-void            vMBTCPPortClose( void );
-
-void            vMBTCPPortDisable( void );
-
-BOOL            xMBTCPPortGetRequest( UCHAR **ppucMBTCPFrame, USHORT * usTCPLength );
-
-BOOL            xMBTCPPortSendResponse( const UCHAR *pucMBTCPFrame, USHORT usTCPLength );
-#endif
-
-#ifdef __cplusplus
-PR_END_EXTERN_C
-#endif
-#endif
diff --git a/tools/sdk/include/freemodbus/mbproto.h b/tools/sdk/include/freemodbus/mbproto.h
deleted file mode 100644
index 786aaf4030d..00000000000
--- a/tools/sdk/include/freemodbus/mbproto.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* 
- * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU.
- * Copyright (c) 2006 Christian Walter <wolti@sil.at>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * File: $Id: mbproto.h,v 1.14 2006/12/07 22:10:34 wolti Exp $
- */
-
-#ifndef _MB_PROTO_H
-#define _MB_PROTO_H
-
-#ifdef __cplusplus
-PR_BEGIN_EXTERN_C
-#endif
-/* ----------------------- Defines ------------------------------------------*/
-#define MB_ADDRESS_BROADCAST    ( 0 )   /*! Modbus broadcast address. */
-#define MB_ADDRESS_MIN          ( 1 )   /*! Smallest possible slave address. */
-#define MB_ADDRESS_MAX          ( 247 ) /*! Biggest possible slave address. */
-#define MB_FUNC_NONE                          (  0 )
-#define MB_FUNC_READ_COILS                    (  1 )
-#define MB_FUNC_READ_DISCRETE_INPUTS          (  2 )
-#define MB_FUNC_WRITE_SINGLE_COIL             (  5 )
-#define MB_FUNC_WRITE_MULTIPLE_COILS          ( 15 )
-#define MB_FUNC_READ_HOLDING_REGISTER         (  3 )
-#define MB_FUNC_READ_INPUT_REGISTER           (  4 )
-#define MB_FUNC_WRITE_REGISTER                (  6 )
-#define MB_FUNC_WRITE_MULTIPLE_REGISTERS      ( 16 )
-#define MB_FUNC_READWRITE_MULTIPLE_REGISTERS  ( 23 )
-#define MB_FUNC_DIAG_READ_EXCEPTION           (  7 )
-#define MB_FUNC_DIAG_DIAGNOSTIC               (  8 )
-#define MB_FUNC_DIAG_GET_COM_EVENT_CNT        ( 11 )
-#define MB_FUNC_DIAG_GET_COM_EVENT_LOG        ( 12 )
-#define MB_FUNC_OTHER_REPORT_SLAVEID          ( 17 )
-#define MB_FUNC_ERROR                         ( 128 )
-/* ----------------------- Type definitions ---------------------------------*/
-    typedef enum
-{
-    MB_EX_NONE = 0x00,
-    MB_EX_ILLEGAL_FUNCTION = 0x01,
-    MB_EX_ILLEGAL_DATA_ADDRESS = 0x02,
-    MB_EX_ILLEGAL_DATA_VALUE = 0x03,
-    MB_EX_SLAVE_DEVICE_FAILURE = 0x04,
-    MB_EX_ACKNOWLEDGE = 0x05,
-    MB_EX_SLAVE_BUSY = 0x06,
-    MB_EX_MEMORY_PARITY_ERROR = 0x08,
-    MB_EX_GATEWAY_PATH_FAILED = 0x0A,
-    MB_EX_GATEWAY_TGT_FAILED = 0x0B
-} eMBException;
-
-typedef         eMBException( *pxMBFunctionHandler ) ( UCHAR * pucFrame, USHORT * pusLength );
-
-typedef struct
-{
-    UCHAR           ucFunctionCode;
-    pxMBFunctionHandler pxHandler;
-} xMBFunctionHandler;
-
-#ifdef __cplusplus
-PR_END_EXTERN_C
-#endif
-#endif
diff --git a/tools/sdk/include/freemodbus/mbutils.h b/tools/sdk/include/freemodbus/mbutils.h
deleted file mode 100644
index 61495751d46..00000000000
--- a/tools/sdk/include/freemodbus/mbutils.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* 
- * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU.
- * Copyright (c) 2006 Christian Walter <wolti@sil.at>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * File: $Id: mbutils.h,v 1.5 2006/12/07 22:10:34 wolti Exp $
- */
-
-#ifndef _MB_UTILS_H
-#define _MB_UTILS_H
-
-#ifdef __cplusplus
-PR_BEGIN_EXTERN_C
-#endif
-/*! \defgroup modbus_utils Utilities
- *
- * This module contains some utility functions which can be used by
- * the application. It includes some special functions for working with
- * bitfields backed by a character array buffer.
- *
- */
-/*! \addtogroup modbus_utils
- *  @{
- */
-/*! \brief Function to set bits in a byte buffer.
- *
- * This function allows the efficient use of an array to implement bitfields.
- * The array used for storing the bits must always be a multiple of two
- * bytes. Up to eight bits can be set or cleared in one operation.
- *
- * \param ucByteBuf A buffer where the bit values are stored. Must be a
- *   multiple of 2 bytes. No length checking is performed and if
- *   usBitOffset / 8 is greater than the size of the buffer memory contents
- *   is overwritten.
- * \param usBitOffset The starting address of the bits to set. The first
- *   bit has the offset 0.
- * \param ucNBits Number of bits to modify. The value must always be smaller
- *   than 8.
- * \param ucValues Thew new values for the bits. The value for the first bit
- *   starting at <code>usBitOffset</code> is the LSB of the value
- *   <code>ucValues</code>
- *
- * \code
- * ucBits[2] = {0, 0};
- *
- * // Set bit 4 to 1 (read: set 1 bit starting at bit offset 4 to value 1)
- * xMBUtilSetBits( ucBits, 4, 1, 1 );
- *
- * // Set bit 7 to 1 and bit 8 to 0.
- * xMBUtilSetBits( ucBits, 7, 2, 0x01 );
- *
- * // Set bits 8 - 11 to 0x05 and bits 12 - 15 to 0x0A;
- * xMBUtilSetBits( ucBits, 8, 8, 0x5A);
- * \endcode
- */
-void            xMBUtilSetBits( UCHAR * ucByteBuf, USHORT usBitOffset,
-                                UCHAR ucNBits, UCHAR ucValues );
-
-/*! \brief Function to read bits in a byte buffer.
- *
- * This function is used to extract up bit values from an array. Up to eight
- * bit values can be extracted in one step.
- *
- * \param ucByteBuf A buffer where the bit values are stored.
- * \param usBitOffset The starting address of the bits to set. The first
- *   bit has the offset 0.
- * \param ucNBits Number of bits to modify. The value must always be smaller
- *   than 8.
- *
- * \code
- * UCHAR ucBits[2] = {0, 0};
- * UCHAR ucResult;
- *
- * // Extract the bits 3 - 10.
- * ucResult = xMBUtilGetBits( ucBits, 3, 8 );
- * \endcode
- */
-UCHAR           xMBUtilGetBits( UCHAR * ucByteBuf, USHORT usBitOffset,
-                                UCHAR ucNBits );
-
-/*! @} */
-
-#ifdef __cplusplus
-PR_END_EXTERN_C
-#endif
-#endif
diff --git a/tools/sdk/include/freertos/freertos/FreeRTOS.h b/tools/sdk/include/freertos/freertos/FreeRTOS.h
deleted file mode 100644
index 486d9c329aa..00000000000
--- a/tools/sdk/include/freertos/freertos/FreeRTOS.h
+++ /dev/null
@@ -1,1053 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef INC_FREERTOS_H
-#define INC_FREERTOS_H
-
-/*
- * Include the generic headers required for the FreeRTOS port being used.
- */
-#include <stddef.h>
-#include "sys/reent.h"
-
-/*
- * If stdint.h cannot be located then:
- *   + If using GCC ensure the -nostdint options is *not* being used.
- *   + Ensure the project's include path includes the directory in which your
- *     compiler stores stdint.h.
- *   + Set any compiler options necessary for it to support C99, as technically
- *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
- *     other way).
- *   + The FreeRTOS download includes a simple stdint.h definition that can be
- *     used in cases where none is provided by the compiler.  The files only
- *     contains the typedefs required to build FreeRTOS.  Read the instructions
- *     in FreeRTOS/source/stdint.readme for more information.
- */
-#include <stdint.h> /* READ COMMENT ABOVE. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Application specific configuration options. */
-#include "FreeRTOSConfig.h"
-
-/* Basic FreeRTOS definitions. */
-#include "projdefs.h"
-
-/* Definitions specific to the port being used. */
-#include "portable.h"
-
-/*
- * Check all the required application specific macros have been defined.
- * These macros are application specific and (as downloaded) are defined
- * within FreeRTOSConfig.h.
- */
-
-#ifndef configMINIMAL_STACK_SIZE
-	#error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.
-#endif
-
-#ifndef configMAX_PRIORITIES
-	#error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef configUSE_PREEMPTION
-	#error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef configUSE_IDLE_HOOK
-	#error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef configUSE_TICK_HOOK
-	#error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef configUSE_CO_ROUTINES
-	#error  Missing definition:  configUSE_CO_ROUTINES must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef INCLUDE_vTaskPrioritySet
-	#error Missing definition:  INCLUDE_vTaskPrioritySet must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef INCLUDE_uxTaskPriorityGet
-	#error Missing definition:  INCLUDE_uxTaskPriorityGet must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef INCLUDE_vTaskDelete
-	#error Missing definition:  INCLUDE_vTaskDelete must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef INCLUDE_vTaskSuspend
-	#error Missing definition:  INCLUDE_vTaskSuspend must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef INCLUDE_vTaskDelayUntil
-	#error Missing definition:  INCLUDE_vTaskDelayUntil must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef INCLUDE_vTaskDelay
-	#error Missing definition:  INCLUDE_vTaskDelay must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#ifndef configUSE_16_BIT_TICKS
-	#error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
-#endif
-
-#if configUSE_CO_ROUTINES != 0
-	#ifndef configMAX_CO_ROUTINE_PRIORITIES
-		#error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
-	#endif
-#endif
-
-#ifndef configMAX_PRIORITIES
-	#error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
-#endif
-
-#ifndef INCLUDE_xTaskGetIdleTaskHandle
-	#define INCLUDE_xTaskGetIdleTaskHandle 0
-#endif
-
-#ifndef INCLUDE_xTimerGetTimerDaemonTaskHandle
-	#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
-#endif
-
-#ifndef INCLUDE_xQueueGetMutexHolder
-	#define INCLUDE_xQueueGetMutexHolder 0
-#endif
-
-#ifndef INCLUDE_xSemaphoreGetMutexHolder
-	#define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder
-#endif
-
-#ifndef INCLUDE_pcTaskGetTaskName
-	#define INCLUDE_pcTaskGetTaskName 1
-#endif
-
-#ifndef configUSE_APPLICATION_TASK_TAG
-	#define configUSE_APPLICATION_TASK_TAG 0
-#endif
-
-#ifndef INCLUDE_uxTaskGetStackHighWaterMark
-	#define INCLUDE_uxTaskGetStackHighWaterMark 0
-#endif
-
-#ifndef INCLUDE_pxTaskGetStackStart
-	#define INCLUDE_pxTaskGetStackStart 0
-#endif
-
-#ifndef INCLUDE_eTaskGetState
-	#define INCLUDE_eTaskGetState 0
-#endif
-
-#ifndef configUSE_RECURSIVE_MUTEXES
-	#define configUSE_RECURSIVE_MUTEXES 0
-#endif
-
-#ifndef configUSE_MUTEXES
-	#define configUSE_MUTEXES 0
-#endif
-
-#ifndef configUSE_TIMERS
-	#define configUSE_TIMERS 0
-#endif
-
-#ifndef configUSE_COUNTING_SEMAPHORES
-	#define configUSE_COUNTING_SEMAPHORES 0
-#endif
-
-#ifndef configUSE_ALTERNATIVE_API
-	#define configUSE_ALTERNATIVE_API 0
-#endif
-
-#ifndef portCRITICAL_NESTING_IN_TCB
-	#define portCRITICAL_NESTING_IN_TCB 0
-#endif
-
-#ifndef configMAX_TASK_NAME_LEN
-	#define configMAX_TASK_NAME_LEN 16
-#endif
-
-#ifndef configIDLE_SHOULD_YIELD
-	#define configIDLE_SHOULD_YIELD		1
-#endif
-
-#if configMAX_TASK_NAME_LEN < 1
-	#error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
-#endif
-
-#ifndef INCLUDE_xTaskResumeFromISR
-	#define INCLUDE_xTaskResumeFromISR 1
-#endif
-
-#ifndef INCLUDE_xEventGroupSetBitFromISR
-	#define INCLUDE_xEventGroupSetBitFromISR 0
-#endif
-
-#ifndef INCLUDE_xTimerPendFunctionCall
-	#define INCLUDE_xTimerPendFunctionCall 0
-#endif
-
-#ifndef configASSERT
-	#define configASSERT( x )
-	#define configASSERT_DEFINED 0
-#else
-	#define configASSERT_DEFINED 1
-#endif
-
-/* The timers module relies on xTaskGetSchedulerState(). */
-#if configUSE_TIMERS == 1
-
-	#ifndef configTIMER_TASK_PRIORITY
-		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
-	#endif /* configTIMER_TASK_PRIORITY */
-
-	#ifndef configTIMER_QUEUE_LENGTH
-		#error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
-	#endif /* configTIMER_QUEUE_LENGTH */
-
-	#ifndef configTIMER_TASK_STACK_DEPTH
-		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
-	#endif /* configTIMER_TASK_STACK_DEPTH */
-
-#endif /* configUSE_TIMERS */
-
-#ifndef INCLUDE_xTaskGetSchedulerState
-	#define INCLUDE_xTaskGetSchedulerState 0
-#endif
-
-#ifndef INCLUDE_xTaskGetCurrentTaskHandle
-	#define INCLUDE_xTaskGetCurrentTaskHandle 0
-#endif
-
-
-#ifndef portSET_INTERRUPT_MASK_FROM_ISR
-	#define portSET_INTERRUPT_MASK_FROM_ISR() 0
-#endif
-
-#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
-	#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
-#endif
-
-#ifndef portCLEAN_UP_TCB
-	#define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
-#endif
-
-#ifndef portPRE_TASK_DELETE_HOOK
-	#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
-#endif
-
-#ifndef portSETUP_TCB
-	#define portSETUP_TCB( pxTCB ) ( void ) pxTCB
-#endif
-
-#ifndef configQUEUE_REGISTRY_SIZE
-	#define configQUEUE_REGISTRY_SIZE 0U
-#endif
-
-#if ( configQUEUE_REGISTRY_SIZE < 1 )
-	#define vQueueAddToRegistry( xQueue, pcName )
-	#define vQueueUnregisterQueue( xQueue )
-#endif
-
-#ifndef portPOINTER_SIZE_TYPE
-	#define portPOINTER_SIZE_TYPE uint32_t
-#endif
-
-/* Remove any unused trace macros. */
-#ifndef traceSTART
-	/* Used to perform any necessary initialisation - for example, open a file
-	into which trace is to be written. */
-	#define traceSTART()
-#endif
-
-#ifndef traceEND
-	/* Use to close a trace, for example close a file into which trace has been
-	written. */
-	#define traceEND()
-#endif
-
-#ifndef traceTASK_SWITCHED_IN
-	/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer
-	to the task control block of the selected task. */
-	#define traceTASK_SWITCHED_IN()
-#endif
-
-#ifndef traceINCREASE_TICK_COUNT
-	/* Called before stepping the tick count after waking from tickless idle
-	sleep. */
-	#define traceINCREASE_TICK_COUNT( x )
-#endif
-
-#ifndef traceLOW_POWER_IDLE_BEGIN
-	/* Called immediately before entering tickless idle. */
-	#define traceLOW_POWER_IDLE_BEGIN()
-#endif
-
-#ifndef	traceLOW_POWER_IDLE_END
-	/* Called when returning to the Idle task after a tickless idle. */
-	#define traceLOW_POWER_IDLE_END()
-#endif
-
-#ifndef traceTASK_SWITCHED_OUT
-	/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer
-	to the task control block of the task being switched out. */
-	#define traceTASK_SWITCHED_OUT()
-#endif
-
-#ifndef traceTASK_PRIORITY_INHERIT
-	/* Called when a task attempts to take a mutex that is already held by a
-	lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task
-	that holds the mutex.  uxInheritedPriority is the priority the mutex holder
-	will inherit (the priority of the task that is attempting to obtain the
-	muted. */
-	#define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
-#endif
-
-#ifndef traceTASK_PRIORITY_DISINHERIT
-	/* Called when a task releases a mutex, the holding of which had resulted in
-	the task inheriting the priority of a higher priority task.
-	pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
-	mutex.  uxOriginalPriority is the task's configured (base) priority. */
-	#define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
-#endif
-
-#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
-	/* Task is about to block because it cannot read from a
-	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
-	upon which the read was attempted.  pxCurrentTCB points to the TCB of the
-	task that attempted the read. */
-	#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
-#endif
-
-#ifndef traceBLOCKING_ON_QUEUE_SEND
-	/* Task is about to block because it cannot write to a
-	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
-	upon which the write was attempted.  pxCurrentTCB points to the TCB of the
-	task that attempted the write. */
-	#define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
-#endif
-
-#ifndef configCHECK_FOR_STACK_OVERFLOW
-	#define configCHECK_FOR_STACK_OVERFLOW 0
-#endif
-
-/* The following event macros are embedded in the kernel API calls. */
-
-#ifndef traceMOVED_TASK_TO_READY_STATE
-	#define traceMOVED_TASK_TO_READY_STATE( pxTCB )
-#endif
-
-#ifndef traceREADDED_TASK_TO_READY_STATE
-	#define traceREADDED_TASK_TO_READY_STATE( pxTCB )	traceMOVED_TASK_TO_READY_STATE( pxTCB )
-#endif
-
-#ifndef traceMOVED_TASK_TO_DELAYED_LIST
-	#define traceMOVED_TASK_TO_DELAYED_LIST()
-#endif
-
-#ifndef traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST
-	#define traceMOVED_TASK_TO_OVERFLOW_DELAYED_LIST()
-#endif
-
-#ifndef traceMOVED_TASK_TO_SUSPENDED_LIST
-	#define traceMOVED_TASK_TO_SUSPENDED_LIST( pxTCB )
-#endif
-
-#ifndef traceQUEUE_CREATE
-	#define traceQUEUE_CREATE( pxNewQueue )
-#endif
-
-#ifndef traceQUEUE_CREATE_FAILED
-	#define traceQUEUE_CREATE_FAILED( ucQueueType )
-#endif
-
-#ifndef traceCREATE_MUTEX
-	#define traceCREATE_MUTEX( pxNewQueue )
-#endif
-
-#ifndef traceCREATE_MUTEX_FAILED
-	#define traceCREATE_MUTEX_FAILED()
-#endif
-
-#ifndef traceGIVE_MUTEX_RECURSIVE
-	#define traceGIVE_MUTEX_RECURSIVE( pxMutex )
-#endif
-
-#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
-	#define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
-#endif
-
-#ifndef traceTAKE_MUTEX_RECURSIVE
-	#define traceTAKE_MUTEX_RECURSIVE( pxMutex )
-#endif
-
-#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
-	#define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
-#endif
-
-#ifndef traceCREATE_COUNTING_SEMAPHORE
-	#define traceCREATE_COUNTING_SEMAPHORE()
-#endif
-
-#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
-	#define traceCREATE_COUNTING_SEMAPHORE_FAILED()
-#endif
-
-#ifndef traceQUEUE_SEND
-	#define traceQUEUE_SEND( pxQueue )
-#endif
-
-#ifndef traceQUEUE_SEND_FAILED
-	#define traceQUEUE_SEND_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_RECEIVE
-	#define traceQUEUE_RECEIVE( pxQueue )
-#endif
-
-#ifndef traceQUEUE_PEEK
-	#define traceQUEUE_PEEK( pxQueue )
-#endif
-
-#ifndef traceQUEUE_PEEK_FROM_ISR
-	#define traceQUEUE_PEEK_FROM_ISR( pxQueue )
-#endif
-
-#ifndef traceQUEUE_RECEIVE_FAILED
-	#define traceQUEUE_RECEIVE_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_SEND_FROM_ISR
-	#define traceQUEUE_SEND_FROM_ISR( pxQueue )
-#endif
-
-#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
-	#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_RECEIVE_FROM_ISR
-	#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
-#endif
-
-#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
-	#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
-	#define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
-#endif
-
-#ifndef traceQUEUE_DELETE
-	#define traceQUEUE_DELETE( pxQueue )
-#endif
-
-#ifndef traceTASK_CREATE
-	#define traceTASK_CREATE( pxNewTCB )
-#endif
-
-#ifndef traceTASK_CREATE_FAILED
-	#define traceTASK_CREATE_FAILED()
-#endif
-
-#ifndef traceTASK_DELETE
-	#define traceTASK_DELETE( pxTaskToDelete )
-#endif
-
-#ifndef traceTASK_DELAY_UNTIL
-	#define traceTASK_DELAY_UNTIL()
-#endif
-
-#ifndef traceTASK_DELAY
-	#define traceTASK_DELAY()
-#endif
-
-#ifndef traceTASK_PRIORITY_SET
-	#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
-#endif
-
-#ifndef traceTASK_SUSPEND
-	#define traceTASK_SUSPEND( pxTaskToSuspend )
-#endif
-
-#ifndef traceTASK_RESUME
-	#define traceTASK_RESUME( pxTaskToResume )
-#endif
-
-#ifndef traceTASK_RESUME_FROM_ISR
-	#define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
-#endif
-
-#ifndef traceTASK_INCREMENT_TICK
-	#define traceTASK_INCREMENT_TICK( xTickCount )
-#endif
-
-#ifndef traceTIMER_CREATE
-	#define traceTIMER_CREATE( pxNewTimer )
-#endif
-
-#ifndef traceTIMER_CREATE_FAILED
-	#define traceTIMER_CREATE_FAILED()
-#endif
-
-#ifndef traceTIMER_COMMAND_SEND
-	#define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
-#endif
-
-#ifndef traceTIMER_EXPIRED
-	#define traceTIMER_EXPIRED( pxTimer )
-#endif
-
-#ifndef traceTIMER_COMMAND_RECEIVED
-	#define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
-#endif
-
-#ifndef traceMALLOC
-    #define traceMALLOC( pvAddress, uiSize )
-#endif
-
-#ifndef traceFREE
-    #define traceFREE( pvAddress, uiSize )
-#endif
-
-#ifndef traceEVENT_GROUP_CREATE
-	#define traceEVENT_GROUP_CREATE( xEventGroup )
-#endif
-
-#ifndef traceEVENT_GROUP_CREATE_FAILED
-	#define traceEVENT_GROUP_CREATE_FAILED()
-#endif
-
-#ifndef traceEVENT_GROUP_SYNC_BLOCK
-	#define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
-#endif
-
-#ifndef traceEVENT_GROUP_SYNC_END
-	#define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
-#endif
-
-#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
-	#define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
-#endif
-
-#ifndef traceEVENT_GROUP_WAIT_BITS_END
-	#define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
-#endif
-
-#ifndef traceEVENT_GROUP_CLEAR_BITS
-	#define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
-#endif
-
-#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
-	#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
-#endif
-
-#ifndef traceEVENT_GROUP_SET_BITS
-	#define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
-#endif
-
-#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
-	#define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
-#endif
-
-#ifndef traceEVENT_GROUP_DELETE
-	#define traceEVENT_GROUP_DELETE( xEventGroup )
-#endif
-
-#ifndef tracePEND_FUNC_CALL
-	#define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)
-#endif
-
-#ifndef tracePEND_FUNC_CALL_FROM_ISR
-	#define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)
-#endif
-
-#ifndef traceQUEUE_REGISTRY_ADD
-	#define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)
-#endif
-
-#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
- 	#define traceTASK_NOTIFY_GIVE_FROM_ISR()
- #endif
- 
-#ifndef traceISR_EXIT_TO_SCHEDULER
-	#define traceISR_EXIT_TO_SCHEDULER()
-#endif
-
-#ifndef traceISR_EXIT
-	#define traceISR_EXIT()
-#endif
-
-#ifndef traceISR_ENTER
-	#define traceISR_ENTER(_n_)
-#endif
-
-#ifndef configGENERATE_RUN_TIME_STATS
-	#define configGENERATE_RUN_TIME_STATS 0
-#endif
-
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
-
-	#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
-		#error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
-	#endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
-
-	#ifndef portGET_RUN_TIME_COUNTER_VALUE
-		#ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
-			#error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.
-		#endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
-	#endif /* portGET_RUN_TIME_COUNTER_VALUE */
-
-#endif /* configGENERATE_RUN_TIME_STATS */
-
-#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
-	#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
-#endif
-
-#ifndef configUSE_MALLOC_FAILED_HOOK
-	#define configUSE_MALLOC_FAILED_HOOK 0
-#endif
-
-#ifndef portPRIVILEGE_BIT
-	#define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )
-#endif
-
-#ifndef portYIELD_WITHIN_API
-	#define portYIELD_WITHIN_API portYIELD
-#endif
-
-#ifndef pvPortMallocAligned
-	#define pvPortMallocAligned( x, puxStackBuffer ) ( ( ( puxStackBuffer ) == NULL ) ? ( pvPortMalloc( ( x ) ) ) : ( puxStackBuffer ) )
-#endif
-
-#ifndef vPortFreeAligned
-	#define vPortFreeAligned( pvBlockToFree ) vPortFree( pvBlockToFree )
-#endif
-
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
-#endif
-
-#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
-	#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
-#endif
-
-#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
-	#error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
-#endif
-
-#ifndef configUSE_TICKLESS_IDLE
-	#define configUSE_TICKLESS_IDLE 0
-#endif
-
-#ifndef configPRE_SLEEP_PROCESSING
-	#define configPRE_SLEEP_PROCESSING( x )
-#endif
-
-#ifndef configPOST_SLEEP_PROCESSING
-	#define configPOST_SLEEP_PROCESSING( x )
-#endif
-
-#ifndef configUSE_QUEUE_SETS
-	#define configUSE_QUEUE_SETS 0
-#endif
-
-#ifndef portTASK_USES_FLOATING_POINT
-	#define portTASK_USES_FLOATING_POINT()
-#endif
-
-#ifndef configUSE_TIME_SLICING
-	#define configUSE_TIME_SLICING 1
-#endif
-
-#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
-	#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0
-#endif
-
-#ifndef configUSE_NEWLIB_REENTRANT
-	#define configUSE_NEWLIB_REENTRANT 0
-#endif
-
-#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
-	#define configUSE_STATS_FORMATTING_FUNCTIONS 0
-#endif
-
-#ifndef configTASKLIST_INCLUDE_COREID
-    #define configTASKLIST_INCLUDE_COREID   0
-#endif
-
-#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
-#endif
-
-#ifndef configUSE_TRACE_FACILITY
-	#define configUSE_TRACE_FACILITY 0
-#endif
-
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-#ifndef portASSERT_IF_IN_ISR
-	#define portASSERT_IF_IN_ISR()
-#endif
-
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
-#endif
-
-#ifndef configAPPLICATION_ALLOCATED_HEAP
-	#define configAPPLICATION_ALLOCATED_HEAP 0
-#endif
-
-#ifndef configUSE_TASK_NOTIFICATIONS
-	#define configUSE_TASK_NOTIFICATIONS 1
-#endif
-
-#ifndef portTICK_TYPE_IS_ATOMIC
-	#define portTICK_TYPE_IS_ATOMIC 0
-#endif
-
-#ifndef configSUPPORT_STATIC_ALLOCATION
-	/* Defaults to 0 for backward compatibility. */
-	#define configSUPPORT_STATIC_ALLOCATION 0
-#endif
-
-#ifndef configSUPPORT_DYNAMIC_ALLOCATION
-	/* Defaults to 1 for backward compatibility. */
-	#define configSUPPORT_DYNAMIC_ALLOCATION 1
-#endif
-
-#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
-	#error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
-#endif
-
-#if( portTICK_TYPE_IS_ATOMIC == 0 )
-	/* Either variables of tick type cannot be read atomically, or
-	portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
-	the tick count is returned to the standard critical section macros. */
-	#define portTICK_TYPE_ENTER_CRITICAL(mux) portENTER_CRITICAL(mux)
-	#define portTICK_TYPE_EXIT_CRITICAL(mux) portEXIT_CRITICAL(mux)
-	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
-	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
-#else
-	/* The tick type can be read atomically, so critical sections used when the
-	tick count is returned can be defined away. */
-	#define portTICK_TYPE_ENTER_CRITICAL()
-	#define portTICK_TYPE_EXIT_CRITICAL()
-	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0
-	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x
-#endif
-
-/* Definitions to allow backward compatibility with FreeRTOS versions prior to
-V8 if desired. */
-#ifndef configENABLE_BACKWARD_COMPATIBILITY
-	#define configENABLE_BACKWARD_COMPATIBILITY 1
-#endif
-
-#if configENABLE_BACKWARD_COMPATIBILITY == 1
-	#define eTaskStateGet eTaskGetState
-	#define portTickType TickType_t
-	#define xTaskHandle TaskHandle_t
-	#define xQueueHandle QueueHandle_t
-	#define xSemaphoreHandle SemaphoreHandle_t
-	#define xQueueSetHandle QueueSetHandle_t
-	#define xQueueSetMemberHandle QueueSetMemberHandle_t
-	#define xTimeOutType TimeOut_t
-	#define xMemoryRegion MemoryRegion_t
-	#define xTaskParameters TaskParameters_t
-	#define xTaskStatusType	TaskStatus_t
-	#define xTimerHandle TimerHandle_t
-	#define xCoRoutineHandle CoRoutineHandle_t
-	#define pdTASK_HOOK_CODE TaskHookFunction_t
-	#define portTICK_RATE_MS portTICK_PERIOD_MS
-
-	/* Backward compatibility within the scheduler code only - these definitions
-	are not really required but are included for completeness. */
-	#define tmrTIMER_CALLBACK TimerCallbackFunction_t
-	#define pdTASK_CODE TaskFunction_t
-	#define xListItem ListItem_t
-	#define xList List_t
-#endif /* configENABLE_BACKWARD_COMPATIBILITY */
-
-#ifndef configESP32_PER_TASK_DATA
-	#define configESP32_PER_TASK_DATA 1
-#endif
-
-/*
- * In line with software engineering best practice, FreeRTOS implements a strict
- * data hiding policy, so the real structures used by FreeRTOS to maintain the
- * state of tasks, queues, semaphores, etc. are not accessible to the application
- * code.  However, if the application writer wants to statically allocate such
- * an object then the size of the object needs to be know.  Dummy structures
- * that are guaranteed to have the same size and alignment requirements of the
- * real objects are used for this purpose.  The dummy list and list item
- * structures below are used for inclusion in such a dummy structure.
- */
-struct xSTATIC_LIST_ITEM
-{
-	TickType_t xDummy1;
-	void *pvDummy2[ 4 ];
-};
-typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
-
-/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
-struct xSTATIC_MINI_LIST_ITEM
-{
-	TickType_t xDummy1;
-	void *pvDummy2[ 2 ];
-};
-typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
-
-/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
-typedef struct xSTATIC_LIST
-{
-	UBaseType_t uxDummy1;
-	void *pvDummy2;
-	StaticMiniListItem_t xDummy3;
-} StaticList_t;
-
-/*
- * In line with software engineering best practice, especially when supplying a
- * library that is likely to change in future versions, FreeRTOS implements a
- * strict data hiding policy.  This means the Task structure used internally by
- * FreeRTOS is not accessible to application code.  However, if the application
- * writer wants to statically allocate the memory required to create a task then
- * the size of the task object needs to be know.  The StaticTask_t structure
- * below is provided for this purpose.  Its sizes and alignment requirements are
- * guaranteed to match those of the genuine structure, no matter which
- * architecture is being used, and no matter how the values in FreeRTOSConfig.h
- * are set.  Its contents are somewhat obfuscated in the hope users will
- * recognise that it would be unwise to make direct use of the structure members.
- */
-typedef struct xSTATIC_TCB
-{
-	void				*pxDummy1;
-	#if ( portUSING_MPU_WRAPPERS == 1 )
-		xMPU_SETTINGS	xDummy2;
-	#endif
-	StaticListItem_t	xDummy3[ 2 ];
-	UBaseType_t			uxDummy5;
-	void				*pxDummy6;
-	uint8_t				ucDummy7[ configMAX_TASK_NAME_LEN ];
-    UBaseType_t			uxDummyCoreId;
-	#if ( portSTACK_GROWTH > 0 || configENABLE_TASK_SNAPSHOT == 1 )
-		void            *pxDummy8;
-	#endif
-	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-		UBaseType_t		uxDummy9;
-        uint32_t        OldInterruptState;
-	#endif
-	#if ( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t		uxDummy10[ 2 ];
-	#endif
-	#if ( configUSE_MUTEXES == 1 )
-		UBaseType_t		uxDummy12[ 2 ];
-	#endif
-	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-		void			*pxDummy14;
-	#endif
-	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-		void			*pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
-    #if ( configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS )
-		void			*pvDummyLocalStorageCallBack[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
-	#endif
-	#endif
-	#if ( configGENERATE_RUN_TIME_STATS == 1 )
-		uint32_t		ulDummy16;
-	#endif
-	#if ( configUSE_NEWLIB_REENTRANT == 1 )
-		struct	_reent	xDummy17;
-	#endif
-	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-		uint32_t 		ulDummy18;
-		uint32_t 		ucDummy19;
-	#endif
-	#if( ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) \
-		 || ( portUSING_MPU_WRAPPERS == 1 ) )
-		uint8_t			uxDummy20;
-	#endif
-
-} StaticTask_t;
-
-/*
- * In line with software engineering best practice, especially when supplying a
- * library that is likely to change in future versions, FreeRTOS implements a
- * strict data hiding policy.  This means the Queue structure used internally by
- * FreeRTOS is not accessible to application code.  However, if the application
- * writer wants to statically allocate the memory required to create a queue
- * then the size of the queue object needs to be know.  The StaticQueue_t
- * structure below is provided for this purpose.  Its sizes and alignment
- * requirements are guaranteed to match those of the genuine structure, no
- * matter which architecture is being used, and no matter how the values in
- * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope
- * users will recognise that it would be unwise to make direct use of the
- * structure members.
- */
-typedef struct xSTATIC_QUEUE
-{
-	void *pvDummy1[ 3 ];
-
-	union
-	{
-		void *pvDummy2;
-		UBaseType_t uxDummy2;
-	} u;
-
-	StaticList_t xDummy3[ 2 ];
-	UBaseType_t uxDummy4[ 3 ];
-
-	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-		uint8_t ucDummy6;
-	#endif
-
-	#if ( configUSE_QUEUE_SETS == 1 )
-		void *pvDummy7;
-	#endif
-
-	#if ( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t uxDummy8;
-		uint8_t ucDummy9;
-	#endif
-
-	portMUX_TYPE muxDummy;		//Mutex required due to SMP
-
-} StaticQueue_t;
-typedef StaticQueue_t StaticSemaphore_t;
-
-/*
- * In line with software engineering best practice, especially when supplying a
- * library that is likely to change in future versions, FreeRTOS implements a
- * strict data hiding policy.  This means the event group structure used
- * internally by FreeRTOS is not accessible to application code.  However, if
- * the application writer wants to statically allocate the memory required to
- * create an event group then the size of the event group object needs to be
- * know.  The StaticEventGroup_t structure below is provided for this purpose.
- * Its sizes and alignment requirements are guaranteed to match those of the
- * genuine structure, no matter which architecture is being used, and no matter
- * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
- * obfuscated in the hope users will recognise that it would be unwise to make
- * direct use of the structure members.
- */
-typedef struct xSTATIC_EVENT_GROUP
-{
-	TickType_t xDummy1;
-	StaticList_t xDummy2;
-
-	#if( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t uxDummy3;
-	#endif
-
-	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-			uint8_t ucDummy4;
-	#endif
-
-	portMUX_TYPE muxDummy;		//Mutex required due to SMP
-
-} StaticEventGroup_t;
-
-/*
- * In line with software engineering best practice, especially when supplying a
- * library that is likely to change in future versions, FreeRTOS implements a
- * strict data hiding policy.  This means the software timer structure used
- * internally by FreeRTOS is not accessible to application code.  However, if
- * the application writer wants to statically allocate the memory required to
- * create a software timer then the size of the queue object needs to be know.
- * The StaticTimer_t structure below is provided for this purpose.  Its sizes
- * and alignment requirements are guaranteed to match those of the genuine
- * structure, no matter which architecture is being used, and no matter how the
- * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in
- * the hope users will recognise that it would be unwise to make direct use of
- * the structure members.
- */
-typedef struct xSTATIC_TIMER
-{
-	void				*pvDummy1;
-	StaticListItem_t	xDummy2;
-	TickType_t			xDummy3;
-	UBaseType_t			uxDummy4;
-	void 				*pvDummy5[ 2 ];
-	#if( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t		uxDummy6;
-	#endif
-
-	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-		uint8_t 		ucDummy7;
-	#endif
-
-} StaticTimer_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* INC_FREERTOS_H */
-
diff --git a/tools/sdk/include/freertos/freertos/FreeRTOSConfig.h b/tools/sdk/include/freertos/freertos/FreeRTOSConfig.h
deleted file mode 100644
index 80185f9e045..00000000000
--- a/tools/sdk/include/freertos/freertos/FreeRTOSConfig.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef FREERTOS_CONFIG_H
-#define FREERTOS_CONFIG_H
-
-#include "sdkconfig.h"
-
-
-/* ESP31 and ESP32 are dualcore processors. */
-#ifndef CONFIG_FREERTOS_UNICORE
-#define portNUM_PROCESSORS 2
-#else 
-#define portNUM_PROCESSORS 1
-#endif
-
-#define XT_USE_THREAD_SAFE_CLIB			0
-#define configASSERT_2	0
-#define portUSING_MPU_WRAPPERS 0
-#define configUSE_MUTEX 1
-#undef XT_USE_SWPRI
-
-#if CONFIG_FREERTOS_CORETIMER_0
-#define XT_TIMER_INDEX 0
-#elif CONFIG_FREERTOS_CORETIMER_1
-#define XT_TIMER_INDEX 1
-#endif
-
-#define configNUM_THREAD_LOCAL_STORAGE_POINTERS CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS
-#define configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS 1
-
-#ifndef __ASSEMBLER__
-
-/**
- * This function is defined to provide a deprecation warning whenever
- * XT_CLOCK_FREQ macro is used.
- * Update the code to use esp_clk_cpu_freq function instead.
- * @return current CPU clock frequency, in Hz
- */
-int xt_clock_freq(void) __attribute__((deprecated));
-
-#define XT_CLOCK_FREQ   (xt_clock_freq())
-
-#endif // __ASSEMBLER__
-
-
-/* Required for configuration-dependent settings */
-#include "xtensa_config.h"
-
-
-/* configASSERT behaviour */
-#ifndef __ASSEMBLER__
-#include <stdlib.h> /* for abort() */
-#include "rom/ets_sys.h"
-
-#if defined(CONFIG_FREERTOS_ASSERT_DISABLE)
-#define configASSERT(a) /* assertions disabled */
-#elif defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE)
-#define configASSERT(a) if (!(a)) {                                     \
-        ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__,  \
-                   __FUNCTION__);                                       \
-    }
-#else /* CONFIG_FREERTOS_ASSERT_FAIL_ABORT */
-#define configASSERT(a) if (!(a)) {                                     \
-        ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__,  \
-                   __FUNCTION__);                                       \
-        abort();                                                        \
-        }
-#endif
-
-#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION
-#define UNTESTED_FUNCTION() { ets_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0)
-#else
-#define UNTESTED_FUNCTION()
-#endif
-
-
-#endif /* def __ASSEMBLER__ */
-
-
-/*-----------------------------------------------------------
- * Application specific definitions.
- *
- * These definitions should be adjusted for your particular hardware and
- * application requirements.
- *
- * Note that the default heap size is deliberately kept small so that
- * the build is more likely to succeed for configurations with limited
- * memory.
- *
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. 
- *----------------------------------------------------------*/
-
-#define configUSE_PREEMPTION			1
-#define configUSE_IDLE_HOOK				1
-#define configUSE_TICK_HOOK				1
-
-#define configTICK_RATE_HZ				( CONFIG_FREERTOS_HZ )
-
-/* Default clock rate for simulator */
-//#define configCPU_CLOCK_HZ				80000000
-
-/* This has impact on speed of search for highest priority */
-#ifdef SMALL_TEST
-#define configMAX_PRIORITIES			( 7 )
-#else
-#define configMAX_PRIORITIES			( 25 )
-#endif
-
-#ifndef CONFIG_ESP32_APPTRACE_ENABLE
-#define configMINIMAL_STACK_SIZE		768
-#else
-/* apptrace module requires at least 2KB of stack per task */
-#define configMINIMAL_STACK_SIZE		2048
-#endif
-
-#ifndef configIDLE_TASK_STACK_SIZE
-#define configIDLE_TASK_STACK_SIZE CONFIG_FREERTOS_IDLE_TASK_STACKSIZE
-#endif
-
-/* The Xtensa port uses a separate interrupt stack. Adjust the stack size */
-/* to suit the needs of your specific application.                        */
-#ifndef configISR_STACK_SIZE
-#define configISR_STACK_SIZE			CONFIG_FREERTOS_ISR_STACKSIZE
-#endif
-
-/* Minimal heap size to make sure examples can run on memory limited
-   configs. Adjust this to suit your system. */
-
-
-//We define the heap to span all of the non-statically-allocated shared RAM. ToDo: Make sure there
-//is some space left for the app and main cpu when running outside of a thread.
-#define configAPPLICATION_ALLOCATED_HEAP 1
-#define configTOTAL_HEAP_SIZE			(&_heap_end - &_heap_start)//( ( size_t ) (64 * 1024) )
-
-#define configMAX_TASK_NAME_LEN			( CONFIG_FREERTOS_MAX_TASK_NAME_LEN )
-
-#ifdef CONFIG_FREERTOS_USE_TRACE_FACILITY
-#define configUSE_TRACE_FACILITY        1       /* Used by uxTaskGetSystemState(), and other trace facility functions */
-#endif
-
-#ifdef CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS
-#define configUSE_STATS_FORMATTING_FUNCTIONS    1   /* Used by vTaskList() */
-#endif
-
-#ifdef CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID
-#define configTASKLIST_INCLUDE_COREID   1
-#endif
-
-#ifdef CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS
-#define configGENERATE_RUN_TIME_STATS   1       /* Used by vTaskGetRunTimeStats() */
-#endif
-
-#define configUSE_TRACE_FACILITY_2      0		/* Provided by Xtensa port patch */
-#define configBENCHMARK					0		/* Provided by Xtensa port patch */
-#define configUSE_16_BIT_TICKS			0
-#define configIDLE_SHOULD_YIELD			0
-#define configQUEUE_REGISTRY_SIZE		CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE
-
-#define configUSE_MUTEXES				1
-#define configUSE_RECURSIVE_MUTEXES		1
-#define configUSE_COUNTING_SEMAPHORES	1
-
-#if CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE
-#define configCHECK_FOR_STACK_OVERFLOW	0
-#elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL
-#define configCHECK_FOR_STACK_OVERFLOW	1
-#elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY
-#define configCHECK_FOR_STACK_OVERFLOW	2
-#endif
-
-
-
-
-/* Co-routine definitions. */
-#define configUSE_CO_ROUTINES 			0
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
-
-/* Set the following definitions to 1 to include the API function, or zero
-   to exclude the API function. */
-
-#define INCLUDE_vTaskPrioritySet			1
-#define INCLUDE_uxTaskPriorityGet			1
-#define INCLUDE_vTaskDelete					1
-#define INCLUDE_vTaskCleanUpResources		0
-#define INCLUDE_vTaskSuspend				1
-#define INCLUDE_vTaskDelayUntil				1
-#define INCLUDE_vTaskDelay					1
-#define INCLUDE_uxTaskGetStackHighWaterMark	1
-#define INCLUDE_pcTaskGetTaskName			1
-#define INCLUDE_xTaskGetIdleTaskHandle      1
-#define INCLUDE_pxTaskGetStackStart			1
-
-#define INCLUDE_xSemaphoreGetMutexHolder    1
-
-/* The priority at which the tick interrupt runs.  This should probably be
-   kept at 1. */
-#define configKERNEL_INTERRUPT_PRIORITY		1
-
-/* The maximum interrupt priority from which FreeRTOS.org API functions can
-   be called.  Only API functions that end in ...FromISR() can be used within
-   interrupts. */
-#define configMAX_SYSCALL_INTERRUPT_PRIORITY	XCHAL_EXCM_LEVEL
-
-#define configUSE_NEWLIB_REENTRANT		1
-
-#define configSUPPORT_DYNAMIC_ALLOCATION    1
-#define configSUPPORT_STATIC_ALLOCATION CONFIG_SUPPORT_STATIC_ALLOCATION
-
-#ifndef __ASSEMBLER__
-#if CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK
-extern void vPortCleanUpTCB ( void *pxTCB );
-#define portCLEAN_UP_TCB( pxTCB )           vPortCleanUpTCB( pxTCB )
-#endif
-#endif
-
-/* Test FreeRTOS timers (with timer task) and more. */
-/* Some files don't compile if this flag is disabled */
-#define configUSE_TIMERS                    1
-#define configTIMER_TASK_PRIORITY           CONFIG_TIMER_TASK_PRIORITY
-#define configTIMER_QUEUE_LENGTH            CONFIG_TIMER_QUEUE_LENGTH
-#define configTIMER_TASK_STACK_DEPTH        CONFIG_TIMER_TASK_STACK_DEPTH
-
-#define INCLUDE_xTimerPendFunctionCall      1
-#define INCLUDE_eTaskGetState               1
-#define configUSE_QUEUE_SETS                1
-
-#define configUSE_TICKLESS_IDLE             CONFIG_FREERTOS_USE_TICKLESS_IDLE
-#if configUSE_TICKLESS_IDLE
-#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP   CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP
-#endif //configUSE_TICKLESS_IDLE
-
-#define configXT_BOARD                      1   /* Board mode */
-#define configXT_SIMULATOR					0
-
-#if CONFIG_ESP32_ENABLE_COREDUMP
-#define configENABLE_TASK_SNAPSHOT          1
-#endif
-#ifndef configENABLE_TASK_SNAPSHOT
-#define configENABLE_TASK_SNAPSHOT          1
-#endif
-
-#if CONFIG_SYSVIEW_ENABLE
-#ifndef __ASSEMBLER__
-#include "SEGGER_SYSVIEW_FreeRTOS.h"
-#undef INLINE // to avoid redefinition
-#endif /* def __ASSEMBLER__ */
-#endif
-
-#endif /* FREERTOS_CONFIG_H */
-
diff --git a/tools/sdk/include/freertos/freertos/StackMacros.h b/tools/sdk/include/freertos/freertos/StackMacros.h
deleted file mode 100644
index 50d2e198fc2..00000000000
--- a/tools/sdk/include/freertos/freertos/StackMacros.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef STACK_MACROS_H
-#define STACK_MACROS_H
-
-/*
- * Call the stack overflow hook function if the stack of the task being swapped
- * out is currently overflowed, or looks like it might have overflowed in the
- * past.
- *
- * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
- * the current stack state only - comparing the current top of stack value to
- * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
- * will also cause the last few stack bytes to be checked to ensure the value
- * to which the bytes were set when the task was created have not been
- * overwritten.  Note this second test does not guarantee that an overflowed
- * stack will always be recognised.
- */
-
-/*-----------------------------------------------------------*/
-
-#if( configCHECK_FOR_STACK_OVERFLOW == 0 )
-
-	/* FreeRTOSConfig.h is not set to check for stack overflows. */
-	#define taskFIRST_CHECK_FOR_STACK_OVERFLOW()
-	#define taskSECOND_CHECK_FOR_STACK_OVERFLOW()
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 0 */
-/*-----------------------------------------------------------*/
-
-#if( configCHECK_FOR_STACK_OVERFLOW == 1 )
-
-	/* FreeRTOSConfig.h is only set to use the first method of
-	overflow checking. */
-	#define taskSECOND_CHECK_FOR_STACK_OVERFLOW()
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) )
-
-	/* Only the current stack state is to be checked. */
-	#define taskFIRST_CHECK_FOR_STACK_OVERFLOW()														\
-	{																									\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB[ xPortGetCoreID() ]->pxTopOfStack <= pxCurrentTCB[ xPortGetCoreID() ]->pxStack )										\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB[ xPortGetCoreID() ], pxCurrentTCB[ xPortGetCoreID() ]->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW > 0 */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) )
-
-	/* Only the current stack state is to be checked. */
-	#define taskFIRST_CHECK_FOR_STACK_OVERFLOW()														\
-	{																									\
-																										\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB[ xPortGetCoreID() ]->pxTopOfStack >= pxCurrentTCB[ xPortGetCoreID() ]->pxEndOfStack )									\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB[ xPortGetCoreID() ], pxCurrentTCB[ xPortGetCoreID() ]->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
-
-	#define taskSECOND_CHECK_FOR_STACK_OVERFLOW()																						\
-	{																																	\
-	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
-																																		\
-																																		\
-		/* Has the extremity of the task stack ever been written over? */																\
-		if( memcmp( ( void * ) pxCurrentTCB[ xPortGetCoreID() ]->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )			\
-		{																																\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB[ xPortGetCoreID() ], pxCurrentTCB[ xPortGetCoreID() ]->pcTaskName );									\
-		}																																\
-	}
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
-
-	#define taskSECOND_CHECK_FOR_STACK_OVERFLOW()																						\
-	{																																	\
-	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB[ xPortGetCoreID() ]->pxEndOfStack;																		\
-	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
-																																		\
-																																		\
-		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
-																																		\
-		/* Has the extremity of the task stack ever been written over? */																\
-		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
-		{																																\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB[ xPortGetCoreID() ], pxCurrentTCB[ xPortGetCoreID() ]->pcTaskName );									\
-		}																																\
-	}
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-#endif /* STACK_MACROS_H */
-
diff --git a/tools/sdk/include/freertos/freertos/croutine.h b/tools/sdk/include/freertos/freertos/croutine.h
deleted file mode 100644
index 7dfd4b8c357..00000000000
--- a/tools/sdk/include/freertos/freertos/croutine.h
+++ /dev/null
@@ -1,762 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef CO_ROUTINE_H
-#define CO_ROUTINE_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include croutine.h"
-#endif
-
-#include "list.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Used to hide the implementation of the co-routine control block.  The
-control block structure however has to be included in the header due to
-the macro implementation of the co-routine functionality. */
-typedef void * CoRoutineHandle_t;
-
-/* Defines the prototype to which co-routine functions must conform. */
-typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
-
-typedef struct corCoRoutineControlBlock
-{
-	crCOROUTINE_CODE 	pxCoRoutineFunction;
-	ListItem_t			xGenericListItem;	/*< List item used to place the CRCB in ready and blocked queues. */
-	ListItem_t			xEventListItem;		/*< List item used to place the CRCB in event lists. */
-	UBaseType_t 		uxPriority;			/*< The priority of the co-routine in relation to other co-routines. */
-	UBaseType_t 		uxIndex;			/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
-	uint16_t 			uxState;			/*< Used internally by the co-routine implementation. */
-} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
-
-/**
- * croutine. h
- *<pre>
- BaseType_t xCoRoutineCreate(
-                                 crCOROUTINE_CODE pxCoRoutineCode,
-                                 UBaseType_t uxPriority,
-                                 UBaseType_t uxIndex
-                               );</pre>
- *
- * Create a new co-routine and add it to the list of co-routines that are
- * ready to run.
- *
- * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
- * functions require special syntax - see the co-routine section of the WEB
- * documentation for more information.
- *
- * @param uxPriority The priority with respect to other co-routines at which
- *  the co-routine will run.
- *
- * @param uxIndex Used to distinguish between different co-routines that
- * execute the same function.  See the example below and the co-routine section
- * of the WEB documentation for further information.
- *
- * @return pdPASS if the co-routine was successfully created and added to a ready
- * list, otherwise an error code defined with ProjDefs.h.
- *
- * Example usage:
-   <pre>
- // Co-routine to be created.
- void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- static const char cLedToFlash[ 2 ] = { 5, 6 };
- static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // This co-routine just delays for a fixed period, then toggles
-         // an LED.  Two co-routines are created using this function, so
-         // the uxIndex parameter is used to tell the co-routine which
-         // LED to flash and how int32_t to delay.  This assumes xQueue has
-         // already been created.
-         vParTestToggleLED( cLedToFlash[ uxIndex ] );
-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
-
- // Function that creates two co-routines.
- void vOtherFunction( void )
- {
- uint8_t ucParameterToPass;
- TaskHandle_t xHandle;
-
-     // Create two co-routines at priority 0.  The first is given index 0
-     // so (from the code above) toggles LED 5 every 200 ticks.  The second
-     // is given index 1 so toggles LED 6 every 400 ticks.
-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
-     {
-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
-     }
- }
-   </pre>
- * \defgroup xCoRoutineCreate xCoRoutineCreate
- * \ingroup Tasks
- */
-BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
-
-
-/**
- * croutine. h
- *<pre>
- void vCoRoutineSchedule( void );</pre>
- *
- * Run a co-routine.
- *
- * vCoRoutineSchedule() executes the highest priority co-routine that is able
- * to run.  The co-routine will execute until it either blocks, yields or is
- * preempted by a task.  Co-routines execute cooperatively so one
- * co-routine cannot be preempted by another, but can be preempted by a task.
- *
- * If an application comprises of both tasks and co-routines then
- * vCoRoutineSchedule should be called from the idle task (in an idle task
- * hook).
- *
- * Example usage:
-   <pre>
- // This idle task hook will schedule a co-routine each time it is called.
- // The rest of the idle task will execute between co-routine calls.
- void vApplicationIdleHook( void )
- {
-	vCoRoutineSchedule();
- }
-
- // Alternatively, if you do not require any other part of the idle task to
- // execute, the idle task hook can call vCoRoutineScheduler() within an
- // infinite loop.
- void vApplicationIdleHook( void )
- {
-    for( ;; )
-    {
-        vCoRoutineSchedule();
-    }
- }
- </pre>
- * \defgroup vCoRoutineSchedule vCoRoutineSchedule
- * \ingroup Tasks
- */
-void vCoRoutineSchedule( void );
-
-/**
- * croutine. h
- * <pre>
- crSTART( CoRoutineHandle_t xHandle );</pre>
- *
- * This macro MUST always be called at the start of a co-routine function.
- *
- * Example usage:
-   <pre>
- // Co-routine to be created.
- void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static int32_t ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }</pre>
- * \defgroup crSTART crSTART
- * \ingroup Tasks
- */
-#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
-
-/**
- * croutine. h
- * <pre>
- crEND();</pre>
- *
- * This macro MUST always be called at the end of a co-routine function.
- *
- * Example usage:
-   <pre>
- // Co-routine to be created.
- void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static int32_t ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }</pre>
- * \defgroup crSTART crSTART
- * \ingroup Tasks
- */
-#define crEND() }
-
-/*
- * These macros are intended for internal use by the co-routine implementation
- * only.  The macros should not be used directly by application writers.
- */
-#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
-#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
-
-/**
- * croutine. h
- *<pre>
- crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>
- *
- * Delay a co-routine for a fixed period of time.
- *
- * crDELAY can only be called from the co-routine function itself - not
- * from within a function called by the co-routine function.  This is because
- * co-routines do not maintain their own stack.
- *
- * @param xHandle The handle of the co-routine to delay.  This is the xHandle
- * parameter of the co-routine function.
- *
- * @param xTickToDelay The number of ticks that the co-routine should delay
- * for.  The actual amount of time this equates to is defined by
- * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
- * can be used to convert ticks to milliseconds.
- *
- * Example usage:
-   <pre>
- // Co-routine to be created.
- void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- // We are to delay for 200ms.
- static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-        // Delay for 200ms.
-        crDELAY( xHandle, xDelayTime );
-
-        // Do something here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }</pre>
- * \defgroup crDELAY crDELAY
- * \ingroup Tasks
- */
-#define crDELAY( xHandle, xTicksToDelay )												\
-	if( ( xTicksToDelay ) > 0 )															\
-	{																					\
-		vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );							\
-	}																					\
-	crSET_STATE0( ( xHandle ) );
-
-/**
- * <pre>
- crQUEUE_SEND(
-                  CoRoutineHandle_t xHandle,
-                  QueueHandle_t pxQueue,
-                  void *pvItemToQueue,
-                  TickType_t xTicksToWait,
-                  BaseType_t *pxResult
-             )</pre>
- *
- * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
- * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
- *
- * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
- * xQueueSend() and xQueueReceive() can only be used from tasks.
- *
- * crQUEUE_SEND can only be called from the co-routine function itself - not
- * from within a function called by the co-routine function.  This is because
- * co-routines do not maintain their own stack.
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xHandle The handle of the calling co-routine.  This is the xHandle
- * parameter of the co-routine function.
- *
- * @param pxQueue The handle of the queue on which the data will be posted.
- * The handle is obtained as the return value when the queue is created using
- * the xQueueCreate() API function.
- *
- * @param pvItemToQueue A pointer to the data being posted onto the queue.
- * The number of bytes of each queued item is specified when the queue is
- * created.  This number of bytes is copied from pvItemToQueue into the queue
- * itself.
- *
- * @param xTickToDelay The number of ticks that the co-routine should block
- * to wait for space to become available on the queue, should space not be
- * available immediately. The actual amount of time this equates to is defined
- * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
- * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
- * below).
- *
- * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
- * data was successfully posted onto the queue, otherwise it will be set to an
- * error defined within ProjDefs.h.
- *
- * Example usage:
-   <pre>
- // Co-routine function that blocks for a fixed period then posts a number onto
- // a queue.
- static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static BaseType_t xNumberToPost = 0;
- static BaseType_t xResult;
-
-    // Co-routines must begin with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // This assumes the queue has already been created.
-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
-
-        if( xResult != pdPASS )
-        {
-            // The message was not posted!
-        }
-
-        // Increment the number to be posted onto the queue.
-        xNumberToPost++;
-
-        // Delay for 100 ticks.
-        crDELAY( xHandle, 100 );
-    }
-
-    // Co-routines must end with a call to crEND().
-    crEND();
- }</pre>
- * \defgroup crQUEUE_SEND crQUEUE_SEND
- * \ingroup Tasks
- */
-#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )			\
-{																						\
-	*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );	\
-	if( *( pxResult ) == errQUEUE_BLOCKED )												\
-	{																					\
-		crSET_STATE0( ( xHandle ) );													\
-		*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );					\
-	}																					\
-	if( *pxResult == errQUEUE_YIELD )													\
-	{																					\
-		crSET_STATE1( ( xHandle ) );													\
-		*pxResult = pdPASS;																\
-	}																					\
-}
-
-/**
- * croutine. h
- * <pre>
-  crQUEUE_RECEIVE(
-                     CoRoutineHandle_t xHandle,
-                     QueueHandle_t pxQueue,
-                     void *pvBuffer,
-                     TickType_t xTicksToWait,
-                     BaseType_t *pxResult
-                 )</pre>
- *
- * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
- * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
- *
- * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
- * xQueueSend() and xQueueReceive() can only be used from tasks.
- *
- * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
- * from within a function called by the co-routine function.  This is because
- * co-routines do not maintain their own stack.
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xHandle The handle of the calling co-routine.  This is the xHandle
- * parameter of the co-routine function.
- *
- * @param pxQueue The handle of the queue from which the data will be received.
- * The handle is obtained as the return value when the queue is created using
- * the xQueueCreate() API function.
- *
- * @param pvBuffer The buffer into which the received item is to be copied.
- * The number of bytes of each queued item is specified when the queue is
- * created.  This number of bytes is copied into pvBuffer.
- *
- * @param xTickToDelay The number of ticks that the co-routine should block
- * to wait for data to become available from the queue, should data not be
- * available immediately. The actual amount of time this equates to is defined
- * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
- * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
- * crQUEUE_SEND example).
- *
- * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
- * data was successfully retrieved from the queue, otherwise it will be set to
- * an error code as defined within ProjDefs.h.
- *
- * Example usage:
- <pre>
- // A co-routine receives the number of an LED to flash from a queue.  It
- // blocks on the queue until the number is received.
- static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static BaseType_t xResult;
- static UBaseType_t uxLEDToFlash;
-
-    // All co-routines must start with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // Wait for data to become available on the queue.
-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-        if( xResult == pdPASS )
-        {
-            // We received the LED to flash - flash it!
-            vParTestToggleLED( uxLEDToFlash );
-        }
-    }
-
-    crEND();
- }</pre>
- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
- * \ingroup Tasks
- */
-#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )			\
-{																						\
-	*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );		\
-	if( *( pxResult ) == errQUEUE_BLOCKED ) 											\
-	{																					\
-		crSET_STATE0( ( xHandle ) );													\
-		*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );				\
-	}																					\
-	if( *( pxResult ) == errQUEUE_YIELD )												\
-	{																					\
-		crSET_STATE1( ( xHandle ) );													\
-		*( pxResult ) = pdPASS;															\
-	}																					\
-}
-
-/**
- * croutine. h
- * <pre>
-  crQUEUE_SEND_FROM_ISR(
-                            QueueHandle_t pxQueue,
-                            void *pvItemToQueue,
-                            BaseType_t xCoRoutinePreviouslyWoken
-                       )</pre>
- *
- * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
- * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
- * functions used by tasks.
- *
- * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
- * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
- * xQueueReceiveFromISR() can only be used to pass data between a task and and
- * ISR.
- *
- * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
- * that is being used from within a co-routine.
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
- * the same queue multiple times from a single interrupt.  The first call
- * should always pass in pdFALSE.  Subsequent calls should pass in
- * the value returned from the previous call.
- *
- * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
- * used by the ISR to determine if a context switch may be required following
- * the ISR.
- *
- * Example usage:
- <pre>
- // A co-routine that blocks on a queue waiting for characters to be received.
- static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- char cRxedChar;
- BaseType_t xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Wait for data to become available on the queue.  This assumes the
-         // queue xCommsRxQueue has already been created!
-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-         // Was a character received?
-         if( xResult == pdPASS )
-         {
-             // Process the character here.
-         }
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to send characters received on a serial port to
- // a co-routine.
- void vUART_ISR( void )
- {
- char cRxedChar;
- BaseType_t xCRWokenByPost = pdFALSE;
-
-     // We loop around reading characters until there are none left in the UART.
-     while( UART_RX_REG_NOT_EMPTY() )
-     {
-         // Obtain the character from the UART.
-         cRxedChar = UART_RX_REG;
-
-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
-         // the first time around the loop.  If the post causes a co-routine
-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
-         // In this manner we can ensure that if more than one co-routine is
-         // blocked on the queue only one is woken by this ISR no matter how
-         // many characters are posted to the queue.
-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
-     }
- }</pre>
- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
- * \ingroup Tasks
- */
-#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
-
-
-/**
- * croutine. h
- * <pre>
-  crQUEUE_SEND_FROM_ISR(
-                            QueueHandle_t pxQueue,
-                            void *pvBuffer,
-                            BaseType_t * pxCoRoutineWoken
-                       )</pre>
- *
- * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
- * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
- * functions used by tasks.
- *
- * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
- * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
- * xQueueReceiveFromISR() can only be used to pass data between a task and and
- * ISR.
- *
- * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
- * from a queue that is being used from within a co-routine (a co-routine
- * posted to the queue).
- *
- * See the co-routine section of the WEB documentation for information on
- * passing data between tasks and co-routines and between ISR's and
- * co-routines.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvBuffer A pointer to a buffer into which the received item will be
- * placed.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from the queue into
- * pvBuffer.
- *
- * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
- * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
- * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
- * *pxCoRoutineWoken will remain unchanged.
- *
- * @return pdTRUE an item was successfully received from the queue, otherwise
- * pdFALSE.
- *
- * Example usage:
- <pre>
- // A co-routine that posts a character to a queue then blocks for a fixed
- // period.  The character is incremented each time.
- static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // cChar holds its value while this co-routine is blocked and must therefore
- // be declared static.
- static char cCharToTx = 'a';
- BaseType_t xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Send the next character to the queue.
-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
-
-         if( xResult == pdPASS )
-         {
-             // The character was successfully posted to the queue.
-         }
-		 else
-		 {
-			// Could not post the character to the queue.
-		 }
-
-         // Enable the UART Tx interrupt to cause an interrupt in this
-		 // hypothetical UART.  The interrupt will obtain the character
-		 // from the queue and send it.
-		 ENABLE_RX_INTERRUPT();
-
-		 // Increment to the next character then block for a fixed period.
-		 // cCharToTx will maintain its value across the delay as it is
-		 // declared static.
-		 cCharToTx++;
-		 if( cCharToTx > 'x' )
-		 {
-			cCharToTx = 'a';
-		 }
-		 crDELAY( 100 );
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to receive characters to send on a UART.
- void vUART_ISR( void )
- {
- char cCharToTx;
- BaseType_t xCRWokenByPost = pdFALSE;
-
-     while( UART_TX_REG_EMPTY() )
-     {
-         // Are there any characters in the queue waiting to be sent?
-		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
-		 // is woken by the post - ensuring that only a single co-routine is
-		 // woken no matter how many times we go around this loop.
-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
-		 {
-			 SEND_CHARACTER( cCharToTx );
-		 }
-     }
- }</pre>
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
- * \ingroup Tasks
- */
-#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
-
-/*
- * This function is intended for internal use by the co-routine macros only.
- * The macro nature of the co-routine implementation requires that the
- * prototype appears here.  The function should not be used by application
- * writers.
- *
- * Removes the current co-routine from its ready list and places it in the
- * appropriate delayed list.
- */
-void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
-
-/*
- * This function is intended for internal use by the queue implementation only.
- * The function should not be used by application writers.
- *
- * Removes the highest priority co-routine from the event list and places it in
- * the pending ready list.
- */
-BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* CO_ROUTINE_H */
diff --git a/tools/sdk/include/freertos/freertos/deprecated_definitions.h b/tools/sdk/include/freertos/freertos/deprecated_definitions.h
deleted file mode 100644
index fb031cdde63..00000000000
--- a/tools/sdk/include/freertos/freertos/deprecated_definitions.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef DEPRECATED_DEFINITIONS_H
-#define DEPRECATED_DEFINITIONS_H
-
-
-/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
-pre-processor definition was used to ensure the pre-processor found the correct
-portmacro.h file for the port being used.  That scheme was deprecated in favour
-of setting the compiler's include path such that it found the correct
-portmacro.h file - removing the need for the constant and allowing the
-portmacro.h file to be located anywhere in relation to the port being used.  The
-definitions below remain in the code for backward compatibility only.  New
-projects should not use them. */
-
-#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
-	#include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
-	typedef void ( __interrupt __far *pxISR )();
-#endif
-
-#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
-	#include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
-	typedef void ( __interrupt __far *pxISR )();
-#endif
-
-#ifdef GCC_MEGA_AVR
-	#include "../portable/GCC/ATMega323/portmacro.h"
-#endif
-
-#ifdef IAR_MEGA_AVR
-	#include "../portable/IAR/ATMega323/portmacro.h"
-#endif
-
-#ifdef MPLAB_PIC24_PORT
-	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
-#endif
-
-#ifdef MPLAB_DSPIC_PORT
-	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
-#endif
-
-#ifdef MPLAB_PIC18F_PORT
-	#include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
-#endif
-
-#ifdef MPLAB_PIC32MX_PORT
-	#include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
-#endif
-
-#ifdef _FEDPICC
-	#include "libFreeRTOS/Include/portmacro.h"
-#endif
-
-#ifdef SDCC_CYGNAL
-	#include "../../Source/portable/SDCC/Cygnal/portmacro.h"
-#endif
-
-#ifdef GCC_ARM7
-	#include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
-#endif
-
-#ifdef GCC_ARM7_ECLIPSE
-	#include "portmacro.h"
-#endif
-
-#ifdef ROWLEY_LPC23xx
-	#include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
-#endif
-
-#ifdef IAR_MSP430
-	#include "..\..\Source\portable\IAR\MSP430\portmacro.h"
-#endif
-
-#ifdef GCC_MSP430
-	#include "../../Source/portable/GCC/MSP430F449/portmacro.h"
-#endif
-
-#ifdef ROWLEY_MSP430
-	#include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
-#endif
-
-#ifdef ARM7_LPC21xx_KEIL_RVDS
-	#include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
-#endif
-
-#ifdef SAM7_GCC
-	#include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
-#endif
-
-#ifdef SAM7_IAR
-	#include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
-#endif
-
-#ifdef SAM9XE_IAR
-	#include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
-#endif
-
-#ifdef LPC2000_IAR
-	#include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
-#endif
-
-#ifdef STR71X_IAR
-	#include "..\..\Source\portable\IAR\STR71x\portmacro.h"
-#endif
-
-#ifdef STR75X_IAR
-	#include "..\..\Source\portable\IAR\STR75x\portmacro.h"
-#endif
-
-#ifdef STR75X_GCC
-	#include "..\..\Source\portable\GCC\STR75x\portmacro.h"
-#endif
-
-#ifdef STR91X_IAR
-	#include "..\..\Source\portable\IAR\STR91x\portmacro.h"
-#endif
-
-#ifdef GCC_H8S
-	#include "../../Source/portable/GCC/H8S2329/portmacro.h"
-#endif
-
-#ifdef GCC_AT91FR40008
-	#include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
-#endif
-
-#ifdef RVDS_ARMCM3_LM3S102
-	#include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef GCC_ARMCM3_LM3S102
-	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef GCC_ARMCM3
-	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef IAR_ARM_CM3
-	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef IAR_ARMCM3_LM
-	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
-#endif
-
-#ifdef HCS12_CODE_WARRIOR
-	#include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
-#endif
-
-#ifdef MICROBLAZE_GCC
-	#include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
-#endif
-
-#ifdef TERN_EE
-	#include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
-#endif
-
-#ifdef GCC_HCS12
-	#include "../../Source/portable/GCC/HCS12/portmacro.h"
-#endif
-
-#ifdef GCC_MCF5235
-    #include "../../Source/portable/GCC/MCF5235/portmacro.h"
-#endif
-
-#ifdef COLDFIRE_V2_GCC
-	#include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
-#endif
-
-#ifdef COLDFIRE_V2_CODEWARRIOR
-	#include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
-#endif
-
-#ifdef GCC_PPC405
-	#include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
-#endif
-
-#ifdef GCC_PPC440
-	#include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
-#endif
-
-#ifdef _16FX_SOFTUNE
-	#include "..\..\Source\portable\Softune\MB96340\portmacro.h"
-#endif
-
-#ifdef BCC_INDUSTRIAL_PC_PORT
-	/* A short file name has to be used in place of the normal
-	FreeRTOSConfig.h when using the Borland compiler. */
-	#include "frconfig.h"
-	#include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
-    typedef void ( __interrupt __far *pxISR )();
-#endif
-
-#ifdef BCC_FLASH_LITE_186_PORT
-	/* A short file name has to be used in place of the normal
-	FreeRTOSConfig.h when using the Borland compiler. */
-	#include "frconfig.h"
-	#include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
-    typedef void ( __interrupt __far *pxISR )();
-#endif
-
-#ifdef __GNUC__
-   #ifdef __AVR32_AVR32A__
-	   #include "portmacro.h"
-   #endif
-#endif
-
-#ifdef __ICCAVR32__
-   #ifdef __CORE__
-      #if __CORE__ == __AVR32A__
-	      #include "portmacro.h"
-      #endif
-   #endif
-#endif
-
-#ifdef __91467D
-	#include "portmacro.h"
-#endif
-
-#ifdef __96340
-	#include "portmacro.h"
-#endif
-
-
-#ifdef __IAR_V850ES_Fx3__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_V850ES_Jx3__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_V850ES_Jx3_L__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_V850ES_Jx2__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_V850ES_Hx2__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
-#endif
-
-#ifdef __IAR_78K0R_Kx3__
-	#include "../../Source/portable/IAR/78K0R/portmacro.h"
-#endif
-
-#ifdef __IAR_78K0R_Kx3L__
-	#include "../../Source/portable/IAR/78K0R/portmacro.h"
-#endif
-
-#endif /* DEPRECATED_DEFINITIONS_H */
-
diff --git a/tools/sdk/include/freertos/freertos/event_groups.h b/tools/sdk/include/freertos/freertos/event_groups.h
deleted file mode 100644
index eda2456388d..00000000000
--- a/tools/sdk/include/freertos/freertos/event_groups.h
+++ /dev/null
@@ -1,726 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef EVENT_GROUPS_H
-#define EVENT_GROUPS_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
-#endif
-
-#include "timers.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * An event group is a collection of bits to which an application can assign a
- * meaning.  For example, an application may create an event group to convey
- * the status of various CAN bus related events in which bit 0 might mean "A CAN
- * message has been received and is ready for processing", bit 1 might mean "The
- * application has queued a message that is ready for sending onto the CAN
- * network", and bit 2 might mean "It is time to send a SYNC message onto the
- * CAN network" etc.  A task can then test the bit values to see which events
- * are active, and optionally enter the Blocked state to wait for a specified
- * bit or a group of specified bits to be active.  To continue the CAN bus
- * example, a CAN controlling task can enter the Blocked state (and therefore
- * not consume any processing time) until either bit 0, bit 1 or bit 2 are
- * active, at which time the bit that was actually active would inform the task
- * which action it had to take (process a received message, send a message, or
- * send a SYNC).
- *
- * The event groups implementation contains intelligence to avoid race
- * conditions that would otherwise occur were an application to use a simple
- * variable for the same purpose.  This is particularly important with respect
- * to when a bit within an event group is to be cleared, and when bits have to
- * be set and then tested atomically - as is the case where event groups are
- * used to create a synchronisation point between multiple tasks (a
- * 'rendezvous').
- *
- */
-
-
-
-/**
- * event_groups.h
- *
- * Type by which event groups are referenced.  For example, a call to
- * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
- * be used as a parameter to other event group functions.
- *
- * \ingroup EventGroup
- */
-typedef void * EventGroupHandle_t;
-
-/* 
- * The type that holds event bits always matches TickType_t - therefore the
- * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
- * 32 bits if set to 0. 
- *
- * \ingroup EventGroup
- */
-typedef TickType_t EventBits_t;
-
-/**
- * Create a new event group.
- *
- * Internally, within the FreeRTOS implementation, event groups use a [small]
- * block of memory, in which the event group's structure is stored.  If an event
- * groups is created using xEventGroupCreate() then the required memory is
- * automatically dynamically allocated inside the xEventGroupCreate() function.
- * (see http://www.freertos.org/a00111.html).  If an event group is created
- * using xEventGropuCreateStatic() then the application writer must instead
- * provide the memory that will get used by the event group.
- * xEventGroupCreateStatic() therefore allows an event group to be created
- * without using any dynamic memory allocation.
- *
- * Although event groups are not related to ticks, for internal implementation
- * reasons the number of bits available for use in an event group is dependent
- * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
- * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
- * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
- * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
- * event bits within an event group.
- *
- * @return If the event group was created then a handle to the event group is
- * returned.  If there was insufficient FreeRTOS heap available to create the
- * event group then NULL is returned.  See http://www.freertos.org/a00111.html
- *
- * Example usage:
- * @code{c}
- * 	// Declare a variable to hold the created event group.
- * 	EventGroupHandle_t xCreatedEventGroup;
- *
- * 	// Attempt to create the event group.
- * 	xCreatedEventGroup = xEventGroupCreate();
- *
- * 	// Was the event group created successfully?
- * 	if( xCreatedEventGroup == NULL )
- * 	{
- * 		// The event group was not created because there was insufficient
- * 		// FreeRTOS heap available.
- * 	}
- * 	else
- * 	{
- * 		// The event group was created.
- * 	}
- * @endcode
- * \ingroup EventGroup
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * Create a new event group.
- *
- * Internally, within the FreeRTOS implementation, event groups use a [small]
- * block of memory, in which the event group's structure is stored.  If an event
- * groups is created using xEventGropuCreate() then the required memory is
- * automatically dynamically allocated inside the xEventGroupCreate() function.
- * (see http://www.freertos.org/a00111.html).  If an event group is created
- * using xEventGropuCreateStatic() then the application writer must instead
- * provide the memory that will get used by the event group.
- * xEventGroupCreateStatic() therefore allows an event group to be created
- * without using any dynamic memory allocation.
- *
- * Although event groups are not related to ticks, for internal implementation
- * reasons the number of bits available for use in an event group is dependent
- * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
- * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
- * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
- * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
- * event bits within an event group.
- *
- * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
- * StaticEventGroup_t, which will be then be used to hold the event group's data
- * structures, removing the need for the memory to be allocated dynamically.
- *
- * @return If the event group was created then a handle to the event group is
- * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
- *
- * Example usage:
- * @code{c}
- * 	// StaticEventGroup_t is a publicly accessible structure that has the same
- * 	// size and alignment requirements as the real event group structure.  It is
- * 	// provided as a mechanism for applications to know the size of the event
- * 	// group (which is dependent on the architecture and configuration file
- * 	// settings) without breaking the strict data hiding policy by exposing the
- * 	// real event group internals.  This StaticEventGroup_t variable is passed
- * 	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
- * 	// the event group's data structures
- * 	StaticEventGroup_t xEventGroupBuffer;
- *
- * 	// Create the event group without dynamically allocating any memory.
- * 	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
- * @endcode
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * [Potentially] block to wait for one or more bits to be set within a
- * previously created event group.
- *
- * This function cannot be called from an interrupt.
- *
- * @param xEventGroup The event group in which the bits are being tested.  The
- * event group must have previously been created using a call to
- * xEventGroupCreate().
- *
- * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
- * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
- * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
- * uxBitsToWaitFor to 0x07.  Etc.
- *
- * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
- * uxBitsToWaitFor that are set within the event group will be cleared before
- * xEventGroupWaitBits() returns if the wait condition was met (if the function
- * returns for a reason other than a timeout).  If xClearOnExit is set to
- * pdFALSE then the bits set in the event group are not altered when the call to
- * xEventGroupWaitBits() returns.
- *
- * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
- * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
- * are set or the specified block time expires.  If xWaitForAllBits is set to
- * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
- * in uxBitsToWaitFor is set or the specified block time expires.  The block
- * time is specified by the xTicksToWait parameter.
- *
- * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
- * for one/all (depending on the xWaitForAllBits value) of the bits specified by
- * uxBitsToWaitFor to become set.
- *
- * @return The value of the event group at the time either the bits being waited
- * for became set, or the block time expired.  Test the return value to know
- * which bits were set.  If xEventGroupWaitBits() returned because its timeout
- * expired then not all the bits being waited for will be set.  If
- * xEventGroupWaitBits() returned because the bits it was waiting for were set
- * then the returned value is the event group value before any bits were
- * automatically cleared in the case that xClearOnExit parameter was set to
- * pdTRUE.
- *
- * Example usage:
- * @code{c}
- *    #define BIT_0	( 1 << 0 )
- *    #define BIT_4	( 1 << 4 )
- *
- *    void aFunction( EventGroupHandle_t xEventGroup )
- *    {
- *    EventBits_t uxBits;
- *    const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
- *
- * 		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
- * 		// the event group.  Clear the bits before exiting.
- * 		uxBits = xEventGroupWaitBits(
- * 					xEventGroup,	// The event group being tested.
- * 					BIT_0 | BIT_4,	// The bits within the event group to wait for.
- * 					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
- * 					pdFALSE,		// Don't wait for both bits, either bit will do.
- * 					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
- *
- * 		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
- * 		{
- * 			// xEventGroupWaitBits() returned because both bits were set.
- * 		}
- * 		else if( ( uxBits & BIT_0 ) != 0 )
- * 		{
- * 			// xEventGroupWaitBits() returned because just BIT_0 was set.
- * 		}
- * 		else if( ( uxBits & BIT_4 ) != 0 )
- * 		{
- * 			// xEventGroupWaitBits() returned because just BIT_4 was set.
- * 		}
- * 		else
- * 		{
- * 			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
- * 			// without either BIT_0 or BIT_4 becoming set.
- * 		}
- *    }
- * @endcode{c}
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * Clear bits within an event group.  This function cannot be called from an
- * interrupt.
- *
- * @param xEventGroup The event group in which the bits are to be cleared.
- *
- * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
- * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
- * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
- *
- * @return The value of the event group before the specified bits were cleared.
- *
- * Example usage:
- * @code{c}
- *    #define BIT_0	( 1 << 0 )
- *    #define BIT_4	( 1 << 4 )
- *
- *    void aFunction( EventGroupHandle_t xEventGroup )
- *    {
- *    EventBits_t uxBits;
- *
- * 		// Clear bit 0 and bit 4 in xEventGroup.
- * 		uxBits = xEventGroupClearBits(
- * 								xEventGroup,	// The event group being updated.
- * 								BIT_0 | BIT_4 );// The bits being cleared.
- *
- * 		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
- * 		{
- * 			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
- * 			// called.  Both will now be clear (not set).
- * 		}
- * 		else if( ( uxBits & BIT_0 ) != 0 )
- * 		{
- * 			// Bit 0 was set before xEventGroupClearBits() was called.  It will
- * 			// now be clear.
- * 		}
- * 		else if( ( uxBits & BIT_4 ) != 0 )
- * 		{
- * 			// Bit 4 was set before xEventGroupClearBits() was called.  It will
- * 			// now be clear.
- * 		}
- * 		else
- * 		{
- * 			// Neither bit 0 nor bit 4 were set in the first place.
- * 		}
- *    }
- * @endcode
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
-
-/**
- * A version of xEventGroupClearBits() that can be called from an interrupt.
- *
- * Setting bits in an event group is not a deterministic operation because there
- * are an unknown number of tasks that may be waiting for the bit or bits being
- * set.  FreeRTOS does not allow nondeterministic operations to be performed
- * while interrupts are disabled, so protects event groups that are accessed
- * from tasks by suspending the scheduler rather than disabling interrupts.  As
- * a result event groups cannot be accessed directly from an interrupt service
- * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the 
- * timer task to have the clear operation performed in the context of the timer 
- * task.
- *
- * @param xEventGroup The event group in which the bits are to be cleared.
- *
- * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
- * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
- * and bit 0 set uxBitsToClear to 0x09.
- *
- * @return If the request to execute the function was posted successfully then 
- * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned 
- * if the timer service queue was full.
- *
- * Example usage:
- * @code{c}
- *    #define BIT_0	( 1 << 0 )
- *    #define BIT_4	( 1 << 4 )
- *
- *    // An event group which it is assumed has already been created by a call to
- *    // xEventGroupCreate().
- *    EventGroupHandle_t xEventGroup;
- *
- *    void anInterruptHandler( void )
- *    {
- * 		// Clear bit 0 and bit 4 in xEventGroup.
- * 		xResult = xEventGroupClearBitsFromISR(
- * 							xEventGroup,	 // The event group being updated.
- * 							BIT_0 | BIT_4 ); // The bits being set.
- *
- * 		if( xResult == pdPASS )
- * 		{
- * 			// The message was posted successfully.
- * 		}
- *   }
- * @endcode
- * \ingroup EventGroup
- */
-#if( configUSE_TRACE_FACILITY == 1 )
-	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
-#else
-	#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
-#endif
-
-/**
- * Set bits within an event group.
- * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
- * is a version that can be called from an interrupt.
- *
- * Setting bits in an event group will automatically unblock tasks that are
- * blocked waiting for the bits.
- *
- * @param xEventGroup The event group in which the bits are to be set.
- *
- * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
- * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
- * and bit 0 set uxBitsToSet to 0x09.
- *
- * @return The value of the event group at the time the call to
- * xEventGroupSetBits() returns.  There are two reasons why the returned value
- * might have the bits specified by the uxBitsToSet parameter cleared.  First,
- * if setting a bit results in a task that was waiting for the bit leaving the
- * blocked state then it is possible the bit will be cleared automatically
- * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
- * unblocked (or otherwise Ready state) task that has a priority above that of
- * the task that called xEventGroupSetBits() will execute and may change the
- * event group value before the call to xEventGroupSetBits() returns.
- *
- * Example usage:
- * @code{c}
- *    #define BIT_0	( 1 << 0 )
- *    #define BIT_4	( 1 << 4 )
- *
- *    void aFunction( EventGroupHandle_t xEventGroup )
- *    {
- *    EventBits_t uxBits;
- *
- * 		// Set bit 0 and bit 4 in xEventGroup.
- * 		uxBits = xEventGroupSetBits(
- * 							xEventGroup,	// The event group being updated.
- * 							BIT_0 | BIT_4 );// The bits being set.
- *
- * 		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
- * 		{
- * 			// Both bit 0 and bit 4 remained set when the function returned.
- * 		}
- * 		else if( ( uxBits & BIT_0 ) != 0 )
- * 		{
- * 			// Bit 0 remained set when the function returned, but bit 4 was
- * 			// cleared.  It might be that bit 4 was cleared automatically as a
- * 			// task that was waiting for bit 4 was removed from the Blocked
- * 			// state.
- * 		}
- * 		else if( ( uxBits & BIT_4 ) != 0 )
- * 		{
- * 			// Bit 4 remained set when the function returned, but bit 0 was
- * 			// cleared.  It might be that bit 0 was cleared automatically as a
- * 			// task that was waiting for bit 0 was removed from the Blocked
- * 			// state.
- * 		}
- * 		else
- * 		{
- * 			// Neither bit 0 nor bit 4 remained set.  It might be that a task
- * 			// was waiting for both of the bits to be set, and the bits were
- * 			// cleared as the task left the Blocked state.
- * 		}
- *    }
- * @endcode{c}
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
-
-/**
- * A version of xEventGroupSetBits() that can be called from an interrupt.
- *
- * Setting bits in an event group is not a deterministic operation because there
- * are an unknown number of tasks that may be waiting for the bit or bits being
- * set.  FreeRTOS does not allow nondeterministic operations to be performed in
- * interrupts or from critical sections.  Therefore xEventGroupSetBitFromISR()
- * sends a message to the timer task to have the set operation performed in the
- * context of the timer task - where a scheduler lock is used in place of a
- * critical section.
- *
- * @param xEventGroup The event group in which the bits are to be set.
- *
- * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
- * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
- * and bit 0 set uxBitsToSet to 0x09.
- *
- * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
- * will result in a message being sent to the timer daemon task.  If the
- * priority of the timer daemon task is higher than the priority of the
- * currently running task (the task the interrupt interrupted) then
- * *pxHigherPriorityTaskWoken will be set to pdTRUE by
- * xEventGroupSetBitsFromISR(), indicating that a context switch should be
- * requested before the interrupt exits.  For that reason
- * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
- * example code below.
- *
- * @return If the request to execute the function was posted successfully then 
- * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned 
- * if the timer service queue was full.
- *
- * Example usage:
- * @code{c}
- *    #define BIT_0	( 1 << 0 )
- *    #define BIT_4	( 1 << 4 )
- *
- *    // An event group which it is assumed has already been created by a call to
- *    // xEventGroupCreate().
- *    EventGroupHandle_t xEventGroup;
- *
- *    void anInterruptHandler( void )
- *    {
- *    BaseType_t xHigherPriorityTaskWoken, xResult;
- *
- * 		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
- * 		xHigherPriorityTaskWoken = pdFALSE;
- *
- * 		// Set bit 0 and bit 4 in xEventGroup.
- * 		xResult = xEventGroupSetBitsFromISR(
- * 							xEventGroup,	// The event group being updated.
- * 							BIT_0 | BIT_4   // The bits being set.
- * 							&xHigherPriorityTaskWoken );
- *
- * 		// Was the message posted successfully?
- * 		if( xResult == pdPASS )
- * 		{
- * 			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
- * 			// switch should be requested.  The macro used is port specific and
- * 			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
- * 			// refer to the documentation page for the port being used.
- * 			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- * 		}
- *   }
- * @endcode
- * \ingroup EventGroup
- */
-#if( configUSE_TRACE_FACILITY == 1 )
-	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
-#else
-	#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
-#endif
-
-/**
- * Atomically set bits within an event group, then wait for a combination of
- * bits to be set within the same event group.  This functionality is typically
- * used to synchronise multiple tasks, where each task has to wait for the other
- * tasks to reach a synchronisation point before proceeding.
- *
- * This function cannot be used from an interrupt.
- *
- * The function will return before its block time expires if the bits specified
- * by the uxBitsToWait parameter are set, or become set within that time.  In
- * this case all the bits specified by uxBitsToWait will be automatically
- * cleared before the function returns.
- *
- * @param xEventGroup The event group in which the bits are being tested.  The
- * event group must have previously been created using a call to
- * xEventGroupCreate().
- *
- * @param uxBitsToSet The bits to set in the event group before determining
- * if, and possibly waiting for, all the bits specified by the uxBitsToWait
- * parameter are set.
- *
- * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
- * inside the event group.  For example, to wait for bit 0 and bit 2 set
- * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
- * uxBitsToWaitFor to 0x07.  Etc.
- *
- * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
- * for all of the bits specified by uxBitsToWaitFor to become set.
- *
- * @return The value of the event group at the time either the bits being waited
- * for became set, or the block time expired.  Test the return value to know
- * which bits were set.  If xEventGroupSync() returned because its timeout
- * expired then not all the bits being waited for will be set.  If
- * xEventGroupSync() returned because all the bits it was waiting for were
- * set then the returned value is the event group value before any bits were
- * automatically cleared.
- *
- * Example usage:
- * @code{c}
- *  // Bits used by the three tasks.
- *  #define TASK_0_BIT		( 1 << 0 )
- *  #define TASK_1_BIT		( 1 << 1 )
- *  #define TASK_2_BIT		( 1 << 2 )
- *
- *  #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
- *
- *  // Use an event group to synchronise three tasks.  It is assumed this event
- *  // group has already been created elsewhere.
- *  EventGroupHandle_t xEventBits;
- *
- *  void vTask0( void *pvParameters )
- *  {
- *  EventBits_t uxReturn;
- *  TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
- *
- * 	 for( ;; )
- * 	 {
- * 		// Perform task functionality here.
- *
- * 		// Set bit 0 in the event flag to note this task has reached the
- * 		// sync point.  The other two tasks will set the other two bits defined
- * 		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
- * 		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
- * 		// for this to happen.
- * 		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
- *
- * 		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
- * 		{
- * 			// All three tasks reached the synchronisation point before the call
- * 			// to xEventGroupSync() timed out.
- * 		}
- * 	}
- *  }
- *
- *  void vTask1( void *pvParameters )
- *  {
- * 	 for( ;; )
- * 	 {
- * 		// Perform task functionality here.
- *
- * 		// Set bit 1 in the event flag to note this task has reached the
- * 		// synchronisation point.  The other two tasks will set the other two
- * 		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
- * 		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
- * 		// indefinitely for this to happen.
- * 		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
- *
- * 		// xEventGroupSync() was called with an indefinite block time, so
- * 		// this task will only reach here if the syncrhonisation was made by all
- * 		// three tasks, so there is no need to test the return value.
- * 	 }
- *  }
- *
- *  void vTask2( void *pvParameters )
- *  {
- * 	 for( ;; )
- * 	 {
- * 		// Perform task functionality here.
- *
- * 		// Set bit 2 in the event flag to note this task has reached the
- * 		// synchronisation point.  The other two tasks will set the other two
- * 		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
- * 		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
- * 		// indefinitely for this to happen.
- * 		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
- *
- * 		// xEventGroupSync() was called with an indefinite block time, so
- * 		// this task will only reach here if the syncrhonisation was made by all
- * 		// three tasks, so there is no need to test the return value.
- * 	}
- *  }
- *
- * @endcode
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-
-/**
- * Returns the current value of the bits in an event group.  This function
- * cannot be used from an interrupt.
- *
- * @param xEventGroup The event group being queried.
- *
- * @return The event group bits at the time xEventGroupGetBits() was called.
- *
- * \ingroup EventGroup
- */
-#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
-
-/**
- * A version of xEventGroupGetBits() that can be called from an ISR.
- *
- * @param xEventGroup The event group being queried.
- *
- * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
- *
- * \ingroup EventGroup
- */
-EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
-
-/**
- *
- * Delete an event group that was previously created by a call to
- * xEventGroupCreate().  Tasks that are blocked on the event group will be
- * unblocked and obtain 0 as the event group's value.
- *
- * @param xEventGroup The event group being deleted.
- */
-void vEventGroupDelete( EventGroupHandle_t xEventGroup );
-
-/** @cond */
-
-/* For internal use only. */
-void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet );
-void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear );
-
-#if (configUSE_TRACE_FACILITY == 1)
-	UBaseType_t uxEventGroupGetNumber( void* xEventGroup );
-#endif
-
-/** @endcond */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* EVENT_GROUPS_H */
-
-
diff --git a/tools/sdk/include/freertos/freertos/list.h b/tools/sdk/include/freertos/freertos/list.h
deleted file mode 100644
index 8606deba5ae..00000000000
--- a/tools/sdk/include/freertos/freertos/list.h
+++ /dev/null
@@ -1,466 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-/*
- * This is the list implementation used by the scheduler.  While it is tailored
- * heavily for the schedulers needs, it is also available for use by
- * application code.
- *
- * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
- * numeric value (xItemValue).  Most of the time the lists are sorted in
- * descending item value order.
- *
- * Lists are created already containing one list item.  The value of this
- * item is the maximum possible that can be stored, it is therefore always at
- * the end of the list and acts as a marker.  The list member pxHead always
- * points to this marker - even though it is at the tail of the list.  This
- * is because the tail contains a wrap back pointer to the true head of
- * the list.
- *
- * In addition to it's value, each list item contains a pointer to the next
- * item in the list (pxNext), a pointer to the list it is in (pxContainer)
- * and a pointer to back to the object that contains it.  These later two
- * pointers are included for efficiency of list manipulation.  There is
- * effectively a two way link between the object containing the list item and
- * the list item itself.
- *
- *
- * \page ListIntroduction List Implementation
- * \ingroup FreeRTOSIntro
- */
-
-#ifndef INC_FREERTOS_H
-	#error FreeRTOS.h must be included before list.h
-#endif
-
-#ifndef LIST_H
-#define LIST_H
-
-/*
- * The list structure members are modified from within interrupts, and therefore
- * by rights should be declared volatile.  However, they are only modified in a
- * functionally atomic way (within critical sections of with the scheduler
- * suspended) and are either passed by reference into a function or indexed via
- * a volatile variable.  Therefore, in all use cases tested so far, the volatile
- * qualifier can be omitted in order to provide a moderate performance
- * improvement without adversely affecting functional behaviour.  The assembly
- * instructions generated by the IAR, ARM and GCC compilers when the respective
- * compiler's options were set for maximum optimisation has been inspected and
- * deemed to be as intended.  That said, as compiler technology advances, and
- * especially if aggressive cross module optimisation is used (a use case that
- * has not been exercised to any great extend) then it is feasible that the
- * volatile qualifier will be needed for correct optimisation.  It is expected
- * that a compiler removing essential code because, without the volatile
- * qualifier on the list structure members and with aggressive cross module
- * optimisation, the compiler deemed the code unnecessary will result in
- * complete and obvious failure of the scheduler.  If this is ever experienced
- * then the volatile qualifier can be inserted in the relevant places within the
- * list structures by simply defining configLIST_VOLATILE to volatile in
- * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
- * If configLIST_VOLATILE is not defined then the preprocessor directives below
- * will simply #define configLIST_VOLATILE away completely.
- *
- * To use volatile list structure members then add the following line to
- * FreeRTOSConfig.h (without the quotes):
- * "#define configLIST_VOLATILE volatile"
- */
-#ifndef configLIST_VOLATILE
-	#define configLIST_VOLATILE
-#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Macros that can be used to place known values within the list structures,
-then check that the known values do not get corrupted during the execution of
-the application.   These may catch the list data structures being overwritten in
-memory.  They will not catch data errors caused by incorrect configuration or
-use of FreeRTOS.*/
-#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
-	/* Define the macros to do nothing. */
-	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
-	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
-	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE
-	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE
-	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
-	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
-	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
-	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
-	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )
-	#define listTEST_LIST_INTEGRITY( pxList )
-#else
-	/* Define macros that add new members into the list structures. */
-	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue1;
-	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue2;
-	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue1;
-	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue2;
-
-	/* Define macros that set the new structure members to known values. */
-	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )		( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
-	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )	( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
-	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )		( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
-	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )		( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
-
-	/* Define macros that will assert if one of the structure members does not
-	contain its expected value. */
-	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )		configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
-	#define listTEST_LIST_INTEGRITY( pxList )			configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
-#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
-
-
-/*
- * Definition of the only type of object that a list can contain.
- */
-struct xLIST_ITEM
-{
-	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	configLIST_VOLATILE TickType_t xItemValue;			/*< The value being listed.  In most cases this is used to sort the list in descending order. */
-	struct xLIST_ITEM * configLIST_VOLATILE pxNext;		/*< Pointer to the next ListItem_t in the list. */
-	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;	/*< Pointer to the previous ListItem_t in the list. */
-	void * pvOwner;										/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
-	void * configLIST_VOLATILE pvContainer;				/*< Pointer to the list in which this list item is placed (if any). */
-	listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-};
-typedef struct xLIST_ITEM ListItem_t;					/* For some reason lint wants this as two separate definitions. */
-
-#if __GNUC_PREREQ(4, 6)
-_Static_assert(sizeof(StaticListItem_t) == sizeof(ListItem_t), "StaticListItem_t != ListItem_t");
-#endif
-
-struct xMINI_LIST_ITEM
-{
-	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	configLIST_VOLATILE TickType_t xItemValue;
-	struct xLIST_ITEM * configLIST_VOLATILE pxNext;
-	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
-};
-typedef struct xMINI_LIST_ITEM MiniListItem_t;
-
-#if __GNUC_PREREQ(4, 6)
-_Static_assert(sizeof(StaticMiniListItem_t) == sizeof(MiniListItem_t), "StaticMiniListItem_t != MiniListItem_t");
-#endif
-
-
-/*
- * Definition of the type of queue used by the scheduler.
- */
-typedef struct xLIST
-{
-	listFIRST_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	configLIST_VOLATILE UBaseType_t uxNumberOfItems;
-	ListItem_t * configLIST_VOLATILE pxIndex;		/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
-	MiniListItem_t xListEnd;						/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
-	listSECOND_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-} List_t;
-
-#if __GNUC_PREREQ(4, 6)
-_Static_assert(sizeof(StaticList_t) == sizeof(List_t), "StaticList_t != List_t");
-#endif
-
-/*
- * Access macro to set the owner of a list item.  The owner of a list item
- * is the object (usually a TCB) that contains the list item.
- *
- * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
- * \ingroup LinkedList
- */
-#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )		( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
-
-/*
- * Access macro to get the owner of a list item.  The owner of a list item
- * is the object (usually a TCB) that contains the list item.
- *
- * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
- * \ingroup LinkedList
- */
-#define listGET_LIST_ITEM_OWNER( pxListItem )	( ( pxListItem )->pvOwner )
-
-/*
- * Access macro to set the value of the list item.  In most cases the value is
- * used to sort the list in descending order.
- *
- * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
- * \ingroup LinkedList
- */
-#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )	( ( pxListItem )->xItemValue = ( xValue ) )
-
-/*
- * Access macro to retrieve the value of the list item.  The value can
- * represent anything - for example the priority of a task, or the time at
- * which a task should be unblocked.
- *
- * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
- * \ingroup LinkedList
- */
-#define listGET_LIST_ITEM_VALUE( pxListItem )	( ( pxListItem )->xItemValue )
-
-/*
- * Access macro to retrieve the value of the list item at the head of a given
- * list.
- *
- * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
- * \ingroup LinkedList
- */
-#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext->xItemValue )
-
-/*
- * Return the list item at the head of the list.
- *
- * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
- * \ingroup LinkedList
- */
-#define listGET_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext )
-
-/*
- * Return the list item at the head of the list.
- *
- * \page listGET_NEXT listGET_NEXT
- * \ingroup LinkedList
- */
-#define listGET_NEXT( pxListItem )	( ( pxListItem )->pxNext )
-
-/*
- * Return the list item that marks the end of the list
- *
- * \page listGET_END_MARKER listGET_END_MARKER
- * \ingroup LinkedList
- */
-#define listGET_END_MARKER( pxList )	( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
-
-/*
- * Access macro to determine if a list contains any items.  The macro will
- * only have the value true if the list is empty.
- *
- * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
- * \ingroup LinkedList
- */
-#define listLIST_IS_EMPTY( pxList )	( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) )
-
-/*
- * Access macro to return the number of items in the list.
- */
-#define listCURRENT_LIST_LENGTH( pxList )	( ( pxList )->uxNumberOfItems )
-
-/*
- * Access function to obtain the owner of the next entry in a list.
- *
- * The list member pxIndex is used to walk through a list.  Calling
- * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
- * and returns that entry's pxOwner parameter.  Using multiple calls to this
- * function it is therefore possible to move through every item contained in
- * a list.
- *
- * The pxOwner parameter of a list item is a pointer to the object that owns
- * the list item.  In the scheduler this is normally a task control block.
- * The pxOwner parameter effectively creates a two way link between the list
- * item and its owner.
- *
- * @param pxTCB pxTCB is set to the address of the owner of the next list item.
- * @param pxList The list from which the next item owner is to be returned.
- *
- * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
- * \ingroup LinkedList
- */
-#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )										\
-{																							\
-List_t * const pxConstList = ( pxList );													\
-	/* Increment the index to the next item and return the item, ensuring */				\
-	/* we don't return the marker used at the end of the list.  */							\
-	( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;							\
-	if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )	\
-	{																						\
-		( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;						\
-	}																						\
-	( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;											\
-}
-
-
-/*
- * Access function to obtain the owner of the first entry in a list.  Lists
- * are normally sorted in ascending item value order.
- *
- * This function returns the pxOwner member of the first item in the list.
- * The pxOwner parameter of a list item is a pointer to the object that owns
- * the list item.  In the scheduler this is normally a task control block.
- * The pxOwner parameter effectively creates a two way link between the list
- * item and its owner.
- *
- * @param pxList The list from which the owner of the head item is to be
- * returned.
- *
- * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
- * \ingroup LinkedList
- */
-#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
-
-/*
- * Check to see if a list item is within a list.  The list item maintains a
- * "container" pointer that points to the list it is in.  All this macro does
- * is check to see if the container and the list match.
- *
- * @param pxList The list we want to know if the list item is within.
- * @param pxListItem The list item we want to know if is in the list.
- * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
- */
-#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) )
-
-/*
- * Return the list a list item is contained within (referenced from).
- *
- * @param pxListItem The list item being queried.
- * @return A pointer to the List_t object that references the pxListItem
- */
-#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer )
-
-/*
- * This provides a crude means of knowing if a list has been initialised, as
- * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
- * function.
- */
-#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
-
-/*
- * Must be called before a list is used!  This initialises all the members
- * of the list structure and inserts the xListEnd item into the list as a
- * marker to the back of the list.
- *
- * @param pxList Pointer to the list being initialised.
- *
- * \page vListInitialise vListInitialise
- * \ingroup LinkedList
- */
-void vListInitialise( List_t * const pxList );
-
-/*
- * Must be called before a list item is used.  This sets the list container to
- * null so the item does not think that it is already contained in a list.
- *
- * @param pxItem Pointer to the list item being initialised.
- *
- * \page vListInitialiseItem vListInitialiseItem
- * \ingroup LinkedList
- */
-void vListInitialiseItem( ListItem_t * const pxItem );
-
-/*
- * Insert a list item into a list.  The item will be inserted into the list in
- * a position determined by its item value (descending item value order).
- *
- * @param pxList The list into which the item is to be inserted.
- *
- * @param pxNewListItem The item that is to be placed in the list.
- *
- * \page vListInsert vListInsert
- * \ingroup LinkedList
- */
-void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem );
-
-/*
- * Insert a list item into a list.  The item will be inserted in a position
- * such that it will be the last item within the list returned by multiple
- * calls to listGET_OWNER_OF_NEXT_ENTRY.
- *
- * The list member pvIndex is used to walk through a list.  Calling
- * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.
- * Placing an item in a list using vListInsertEnd effectively places the item
- * in the list position pointed to by pvIndex.  This means that every other
- * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
- * the pvIndex parameter again points to the item being inserted.
- *
- * @param pxList The list into which the item is to be inserted.
- *
- * @param pxNewListItem The list item to be inserted into the list.
- *
- * \page vListInsertEnd vListInsertEnd
- * \ingroup LinkedList
- */
-void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem );
-
-/*
- * Remove an item from a list.  The list item has a pointer to the list that
- * it is in, so only the list item need be passed into the function.
- *
- * @param uxListRemove The item to be removed.  The item will remove itself from
- * the list pointed to by it's pxContainer parameter.
- *
- * @return The number of items that remain in the list after the list item has
- * been removed.
- *
- * \page uxListRemove uxListRemove
- * \ingroup LinkedList
- */
-UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/tools/sdk/include/freertos/freertos/mpu_wrappers.h b/tools/sdk/include/freertos/freertos/mpu_wrappers.h
deleted file mode 100644
index 504f6d934da..00000000000
--- a/tools/sdk/include/freertos/freertos/mpu_wrappers.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef MPU_WRAPPERS_H
-#define MPU_WRAPPERS_H
-
-/* This file redefines API functions to be called through a wrapper macro, but
-only for ports that are using the MPU. */
-#if portUSING_MPU_WRAPPERS
-
-	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
-	included from queue.c or task.c to prevent it from having an effect within
-	those files. */
-	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-		#define xTaskGenericCreate				MPU_xTaskGenericCreate
-		#define vTaskAllocateMPURegions			MPU_vTaskAllocateMPURegions
-		#define vTaskDelete						MPU_vTaskDelete
-		#define vTaskDelayUntil					MPU_vTaskDelayUntil
-		#define vTaskDelay						MPU_vTaskDelay
-		#define uxTaskPriorityGet				MPU_uxTaskPriorityGet
-		#define vTaskPrioritySet				MPU_vTaskPrioritySet
-		#define eTaskGetState					MPU_eTaskGetState
-		#define vTaskSuspend					MPU_vTaskSuspend
-		#define vTaskResume						MPU_vTaskResume
-		#define vTaskSuspendAll					MPU_vTaskSuspendAll
-		#define xTaskResumeAll					MPU_xTaskResumeAll
-		#define xTaskGetTickCount				MPU_xTaskGetTickCount
-		#define uxTaskGetNumberOfTasks			MPU_uxTaskGetNumberOfTasks
-		#define vTaskList						MPU_vTaskList
-		#define vTaskGetRunTimeStats			MPU_vTaskGetRunTimeStats
-		#define vTaskSetApplicationTaskTag		MPU_vTaskSetApplicationTaskTag
-		#define xTaskGetApplicationTaskTag		MPU_xTaskGetApplicationTaskTag
-		#define xTaskCallApplicationTaskHook	MPU_xTaskCallApplicationTaskHook
-		#define uxTaskGetStackHighWaterMark		MPU_uxTaskGetStackHighWaterMark
-		#define xTaskGetCurrentTaskHandle		MPU_xTaskGetCurrentTaskHandle
-		#define xTaskGetSchedulerState			MPU_xTaskGetSchedulerState
-		#define xTaskGetIdleTaskHandle			MPU_xTaskGetIdleTaskHandle
-		#define uxTaskGetSystemState			MPU_uxTaskGetSystemState
-
-		#define xQueueGenericCreate				MPU_xQueueGenericCreate
-		#define xQueueCreateMutex				MPU_xQueueCreateMutex
-		#define xQueueGiveMutexRecursive		MPU_xQueueGiveMutexRecursive
-		#define xQueueTakeMutexRecursive		MPU_xQueueTakeMutexRecursive
-		#define xQueueCreateCountingSemaphore	MPU_xQueueCreateCountingSemaphore
-		#define xQueueGenericSend				MPU_xQueueGenericSend
-		#define xQueueAltGenericSend			MPU_xQueueAltGenericSend
-		#define xQueueAltGenericReceive			MPU_xQueueAltGenericReceive
-		#define xQueueGenericReceive			MPU_xQueueGenericReceive
-		#define uxQueueMessagesWaiting			MPU_uxQueueMessagesWaiting
-		#define vQueueDelete					MPU_vQueueDelete
-		#define xQueueGenericReset				MPU_xQueueGenericReset
-		#define xQueueCreateSet					MPU_xQueueCreateSet
-		#define xQueueSelectFromSet				MPU_xQueueSelectFromSet
-		#define xQueueAddToSet					MPU_xQueueAddToSet
-		#define xQueueRemoveFromSet				MPU_xQueueRemoveFromSet
-		#define xQueuePeekFromISR				MPU_xQueuePeekFromISR
-		#define xQueueGetMutexHolder			MPU_xQueueGetMutexHolder
-
-		#define pvPortMalloc					MPU_pvPortMalloc
-		#define vPortFree						MPU_vPortFree
-		#define xPortGetFreeHeapSize			MPU_xPortGetFreeHeapSize
-		#define vPortInitialiseBlocks			MPU_vPortInitialiseBlocks
-
-		#if configQUEUE_REGISTRY_SIZE > 0
-			#define vQueueAddToRegistry				MPU_vQueueAddToRegistry
-			#define vQueueUnregisterQueue			MPU_vQueueUnregisterQueue
-		#endif
-
-		/* Remove the privileged function macro. */
-		#define PRIVILEGED_FUNCTION
-
-	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-		/* Ensure API functions go in the privileged execution section. */
-		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
-		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
-
-	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-#else /* portUSING_MPU_WRAPPERS */
-
-	#define PRIVILEGED_FUNCTION
-	#define PRIVILEGED_DATA
-	#define portUSING_MPU_WRAPPERS 0
-
-#endif /* portUSING_MPU_WRAPPERS */
-
-
-#endif /* MPU_WRAPPERS_H */
-
diff --git a/tools/sdk/include/freertos/freertos/portable.h b/tools/sdk/include/freertos/freertos/portable.h
deleted file mode 100644
index 61cee76449b..00000000000
--- a/tools/sdk/include/freertos/freertos/portable.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-/*-----------------------------------------------------------
- * Portable layer API.  Each function must be defined for each port.
- *----------------------------------------------------------*/
-
-#ifndef PORTABLE_H
-#define PORTABLE_H
-
-/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
-pre-processor definition was used to ensure the pre-processor found the correct
-portmacro.h file for the port being used.  That scheme was deprecated in favour
-of setting the compiler's include path such that it found the correct
-portmacro.h file - removing the need for the constant and allowing the
-portmacro.h file to be located anywhere in relation to the port being used.
-Purely for reasons of backward compatibility the old method is still valid, but
-to make it clear that new projects should not use it, support for the port
-specific constants has been moved into the deprecated_definitions.h header
-file. */
-#include "deprecated_definitions.h"
-
-#include "soc/cpu.h"
-
-/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
-did not result in a portmacro.h header file being included - and it should be
-included here.  In this case the path to the correct portmacro.h header file
-must be set in the compiler's include path. */
-#ifndef portENTER_CRITICAL
-	#include "portmacro.h"
-#endif
-
-#if portBYTE_ALIGNMENT == 8
-	#define portBYTE_ALIGNMENT_MASK ( 0x0007U )
-#endif
-
-#if portBYTE_ALIGNMENT == 4
-	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
-#endif
-
-#if portBYTE_ALIGNMENT == 2
-	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
-#endif
-
-#if portBYTE_ALIGNMENT == 1
-	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
-#endif
-
-#ifndef portBYTE_ALIGNMENT_MASK
-	#error "Invalid portBYTE_ALIGNMENT definition"
-#endif
-
-#ifndef portNUM_CONFIGURABLE_REGIONS
-	#define portNUM_CONFIGURABLE_REGIONS 1
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "mpu_wrappers.h"
-#include "esp_system.h"
-
-/*
- * Setup the stack of a new task so it is ready to be placed under the
- * scheduler control.  The registers have to be placed on the stack in
- * the order that the port expects to find them.
- *
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Map to the memory management routines required for the port.
- *
- * Note that libc standard malloc/free are also available for
- * non-FreeRTOS-specific code, and behave the same as
- * pvPortMalloc()/vPortFree().
- */
-#define pvPortMalloc malloc
-#define vPortFree free
-#define xPortGetFreeHeapSize esp_get_free_heap_size
-#define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size
-
-/*
- * Setup the hardware ready for the scheduler to take control.  This generally
- * sets up a tick interrupt and sets timers for the correct tick frequency.
- */
-BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
- * the hardware is left in its original condition after the scheduler stops
- * executing.
- */
-void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
-
-
-/*
- * Send an interrupt to another core in order to make the task running
- * on it yield for a higher-priority task.
- */
-
-void vPortYieldOtherCore( BaseType_t coreid) PRIVILEGED_FUNCTION;
-
-
-/*
- Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
- watchpoint around.
- */
-void vPortSetStackWatchpoint( void* pxStackStart );
-
-/*
- * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
- * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
- */
-BaseType_t xPortInIsrContext();
-
-/*
- * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
- * before calling into high prio ISR context.
- */
-BaseType_t xPortInterruptedFromISRContext();
-
-/*
- * The structures and methods of manipulating the MPU are contained within the
- * port layer.
- *
- * Fills the xMPUSettings structure with the memory region information
- * contained in xRegions.
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	struct xMEMORY_REGION;
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t usStackDepth ) PRIVILEGED_FUNCTION;
-	void vPortReleaseTaskMPUSettings( xMPU_SETTINGS *xMPUSettings );
-#endif
-
-/* Multi-core: get current core ID */
-static inline uint32_t IRAM_ATTR xPortGetCoreID() {
-    int id;
-    __asm__ __volatile__ (
-        "rsr.prid %0\n"
-        " extui %0,%0,13,1"
-        :"=r"(id));
-    return id;
-}
-
-/* Get tick rate per second */
-uint32_t xPortGetTickRateHz(void);
-
-
-static inline bool IRAM_ATTR xPortCanYield(void)
-{
-    uint32_t ps_reg = 0;
-
-    //Get the current value of PS (processor status) register
-    RSR(PS, ps_reg);
-
-    /*
-     * intlevel = (ps_reg & 0xf);
-     * excm  = (ps_reg >> 4) & 0x1;
-     * CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3.
-     * However, just return true, only intlevel is zero.
-     */
-
-    return ((ps_reg & PS_INTLEVEL_MASK) == 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set);
-
-#endif /* PORTABLE_H */
-
diff --git a/tools/sdk/include/freertos/freertos/portbenchmark.h b/tools/sdk/include/freertos/freertos/portbenchmark.h
deleted file mode 100644
index 4ce41d3dad8..00000000000
--- a/tools/sdk/include/freertos/freertos/portbenchmark.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-*/
-
-/*
- * This utility helps benchmarking interrupt latency and context switches.
- * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
- * You will also need to download the FreeRTOS_trace patch that contains
- * portbenchmark.c and the complete version of portbenchmark.h
- */
-
-#ifndef PORTBENCHMARK_H
-#define PORTBENCHMARK_H
-
-#if configBENCHMARK
-    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
-#endif
-
-#define portbenchmarkINTERRUPT_DISABLE()
-#define portbenchmarkINTERRUPT_RESTORE(newstate)
-#define portbenchmarkIntLatency()
-#define portbenchmarkIntWait()
-#define portbenchmarkReset()
-#define portbenchmarkPrint()
-
-#endif /* PORTBENCHMARK */
diff --git a/tools/sdk/include/freertos/freertos/portmacro.h b/tools/sdk/include/freertos/freertos/portmacro.h
deleted file mode 100644
index 7fd94d5a0b9..00000000000
--- a/tools/sdk/include/freertos/freertos/portmacro.h
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that has become a de facto standard.             *
-     *                                                                       *
-     *    Help yourself get started quickly and support the FreeRTOS         *
-     *    project by purchasing a FreeRTOS tutorial book, reference          *
-     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
-     *                                                                       *
-     *    Thank you!                                                         *
-     *                                                                       *
-    ***************************************************************************
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
-    link: http://www.freertos.org/a00114.html
-
-    1 tab == 4 spaces!
-
-    ***************************************************************************
-     *                                                                       *
-     *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?"                                     *
-     *                                                                       *
-     *    http://www.FreeRTOS.org/FAQHelp.html                               *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
-    license and Real Time Engineers Ltd. contact details.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
-    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-#include <xtensa/config/system.h>	/* required for XSHAL_CLIB */
-#include <xtensa/xtruntime.h>
-#include "esp_crosscore_int.h"
-#include "esp_timer.h"              /* required for FreeRTOS run time stats */
-
-
-#include <esp_heap_caps.h>
-#include "soc/soc_memory_layout.h"
-
-//#include "xtensa_context.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-
-#define portCHAR		int8_t
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		int32_t
-#define portSHORT		int16_t
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	int
-
-typedef portSTACK_TYPE			StackType_t;
-typedef portBASE_TYPE			BaseType_t;
-typedef unsigned portBASE_TYPE	UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-// portbenchmark
-#include "portbenchmark.h"
-
-#include "sdkconfig.h"
-#include "esp_attr.h"
-
-/* "mux" data structure (spinlock) */
-typedef struct {
-	/* owner field values:
-	 * 0                - Uninitialized (invalid)
-	 * portMUX_FREE_VAL - Mux is free, can be locked by either CPU
-	 * CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core
-	 *
-	 * Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption
-	 */
-	uint32_t owner;
-	/* count field:
-	 * If mux is unlocked, count should be zero.
-	 * If mux is locked, count is non-zero & represents the number of recursive locks on the mux.
-	 */
-	uint32_t count;
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	const char *lastLockedFn;
-	int lastLockedLine;
-#endif
-} portMUX_TYPE;
-
-#define portMUX_FREE_VAL		0xB33FFFFF
-
-/* Special constants for vPortCPUAcquireMutexTimeout() */
-#define portMUX_NO_TIMEOUT      (-1)  /* When passed for 'timeout_cycles', spin forever if necessary */
-#define portMUX_TRY_LOCK        0     /* Try to acquire the spinlock a single time only */
-
-// Keep this in sync with the portMUX_TYPE struct definition please.
-#ifndef CONFIG_FREERTOS_PORTMUX_DEBUG
-#define portMUX_INITIALIZER_UNLOCKED {					\
-		.owner = portMUX_FREE_VAL,						\
-		.count = 0,										\
-	}
-#else
-#define portMUX_INITIALIZER_UNLOCKED {					\
-		.owner = portMUX_FREE_VAL,						\
-		.count = 0,										\
-		.lastLockedFn = "(never locked)",				\
-		.lastLockedLine = -1							\
-	}
-#endif
-
-
-#define portASSERT_IF_IN_ISR()        vPortAssertIfInISR()
-void vPortAssertIfInISR();
-
-#define portCRITICAL_NESTING_IN_TCB 1
-
-/*
-Modifications to portENTER_CRITICAL.
-
-For an introduction, see "Critical Sections & Disabling Interrupts" in docs/api-guides/freertos-smp.rst
-
-The original portENTER_CRITICAL only disabled the ISRs. This is enough for single-CPU operation: by
-disabling the interrupts, there is no task switch so no other tasks can meddle in the data, and because
-interrupts are disabled, ISRs can't corrupt data structures either.
-
-For multiprocessing, things get a bit more hairy. First of all, disabling the interrupts doesn't stop
-the tasks or ISRs on the other processors meddling with our CPU. For tasks, this is solved by adding
-a spinlock to the portENTER_CRITICAL macro. A task running on the other CPU accessing the same data will
-spinlock in the portENTER_CRITICAL code until the first CPU is done.
-
-For ISRs, we now also need muxes: while portENTER_CRITICAL disabling interrupts will stop ISRs on the same
-CPU from meddling with the data, it does not stop interrupts on the other cores from interfering with the
-data. For this, we also use a spinlock in the routines called by the ISR, but these spinlocks
-do not disable the interrupts (because they already are).
-
-This all assumes that interrupts are either entirely disabled or enabled. Interrupt priority levels
-will break this scheme.
-
-Remark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vTaskEnterCritical, meaning
-that either function can be called both from ISR as well as task context. This is not standard FreeRTOS 
-behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations.
-*/
-void vPortCPUInitializeMutex(portMUX_TYPE *mux);
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-void vPortCPUAcquireMutex(portMUX_TYPE *mux, const char *function, int line);
-bool vPortCPUAcquireMutexTimeout(portMUX_TYPE *mux, int timeout_cycles, const char *function, int line);
-void vPortCPUReleaseMutex(portMUX_TYPE *mux, const char *function, int line);
-
-
-void vTaskEnterCritical( portMUX_TYPE *mux, const char *function, int line );
-void vTaskExitCritical( portMUX_TYPE *mux, const char *function, int line );
-
-#ifdef CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
-/* Calling port*_CRITICAL from ISR context would cause an assert failure.
- * If the parent function is called from both ISR and Non-ISR context then call port*_CRITICAL_SAFE
- */
-#define portENTER_CRITICAL(mux)        do {                                                                                             \
-                                            if(!xPortInIsrContext()) {                                                                  \
-                                                vTaskEnterCritical(mux, __FUNCTION__, __LINE__);                                        \
-                                            } else {                                                                                    \
-                                                ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__, \
-                                                           __FUNCTION__);                                                               \
-                                                abort();                                                                                \
-                                            }                                                                                           \
-                                       } while(0)
-
-#define portEXIT_CRITICAL(mux)        do {                                                                                              \
-                                            if(!xPortInIsrContext()) {                                                                  \
-                                                vTaskExitCritical(mux, __FUNCTION__, __LINE__);                                         \
-                                            } else {                                                                                    \
-                                                ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__, \
-                                                           __FUNCTION__);                                                               \
-                                                abort();                                                                                \
-                                            }                                                                                           \
-                                       } while(0)
-#else
-#define portENTER_CRITICAL(mux)        vTaskEnterCritical(mux, __FUNCTION__, __LINE__)
-#define portEXIT_CRITICAL(mux)         vTaskExitCritical(mux, __FUNCTION__, __LINE__)
-#endif
-#define portENTER_CRITICAL_ISR(mux)    vTaskEnterCritical(mux, __FUNCTION__, __LINE__)
-#define portEXIT_CRITICAL_ISR(mux)     vTaskExitCritical(mux, __FUNCTION__, __LINE__)
-#else
-void vTaskExitCritical( portMUX_TYPE *mux );
-void vTaskEnterCritical( portMUX_TYPE *mux );
-void vPortCPUAcquireMutex(portMUX_TYPE *mux);
-
-/** @brief Acquire a portmux spinlock with a timeout
- *
- * @param mux Pointer to portmux to acquire.
- * @param timeout_cycles Timeout to spin, in CPU cycles. Pass portMUX_NO_TIMEOUT to wait forever,
- * portMUX_TRY_LOCK to try a single time to acquire the lock.
- *
- * @return true if mutex is successfully acquired, false on timeout.
- */
-bool vPortCPUAcquireMutexTimeout(portMUX_TYPE *mux, int timeout_cycles);
-void vPortCPUReleaseMutex(portMUX_TYPE *mux);
-
-#ifdef CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE
-/* Calling port*_CRITICAL from ISR context would cause an assert failure.
- * If the parent function is called from both ISR and Non-ISR context then call port*_CRITICAL_SAFE
- */
-#define portENTER_CRITICAL(mux)        do {                                                                                             \
-                                            if(!xPortInIsrContext()) {                                                                  \
-                                                vTaskEnterCritical(mux);                                                                \
-                                            } else {                                                                                    \
-                                                ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__, \
-                                                           __FUNCTION__);                                                               \
-                                                abort();                                                                                \
-                                            }                                                                                           \
-                                       } while(0)
-
-#define portEXIT_CRITICAL(mux)        do {                                                                                              \
-                                            if(!xPortInIsrContext()) {                                                                  \
-                                                vTaskExitCritical(mux);                                                                 \
-                                            } else {                                                                                    \
-                                                ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__, \
-                                                           __FUNCTION__);                                                               \
-                                                abort();                                                                                \
-                                            }                                                                                           \
-                                       } while(0)
-#else
-#define portENTER_CRITICAL(mux)        vTaskEnterCritical(mux)
-#define portEXIT_CRITICAL(mux)         vTaskExitCritical(mux)
-#endif
-#define portENTER_CRITICAL_ISR(mux)    vTaskEnterCritical(mux)
-#define portEXIT_CRITICAL_ISR(mux)     vTaskExitCritical(mux)
-#endif
-
-#define portENTER_CRITICAL_SAFE(mux)  do {                                             \
-                                         if (xPortInIsrContext()) {                    \
-                                             portENTER_CRITICAL_ISR(mux);              \
-                                         } else {                                      \
-                                             portENTER_CRITICAL(mux);                  \
-                                         }                                             \
-                                      } while(0)
-
-#define portEXIT_CRITICAL_SAFE(mux)  do {                                              \
-                                         if (xPortInIsrContext()) {                    \
-                                             portEXIT_CRITICAL_ISR(mux);               \
-                                         } else {                                      \
-                                             portEXIT_CRITICAL(mux);                   \
-                                         }                                             \
-                                      } while(0)
-
-
-// Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any?
-// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.
-//
-// Only applies to one CPU. See notes above & below for reasons not to use these.
-#define portDISABLE_INTERRUPTS()      do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
-#define portENABLE_INTERRUPTS()       do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
-
-// Cleaner solution allows nested interrupts disabling and restoring via local registers or stack.
-// They can be called from interrupts too.
-// WARNING: Only applies to current CPU. See notes above.
-static inline unsigned portENTER_CRITICAL_NESTED() {
-	unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL);
-	portbenchmarkINTERRUPT_DISABLE();
-	return state;
-}
-#define portEXIT_CRITICAL_NESTED(state)   do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)
-
-// These FreeRTOS versions are similar to the nested versions above
-#define portSET_INTERRUPT_MASK_FROM_ISR()            portENTER_CRITICAL_NESTED()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state)     portEXIT_CRITICAL_NESTED(state)
-
-//Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force
-//the stack memory to always be internal.
-#define portTcbMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
-#define portStackMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
-
-#define pvPortMallocTcbMem(size) heap_caps_malloc(size, portTcbMemoryCaps)
-#define pvPortMallocStackMem(size)  heap_caps_malloc(size, portStackMemoryCaps)
-
-//xTaskCreateStatic uses these functions to check incoming memory.
-#define portVALID_TCB_MEM(ptr) (esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr))
-#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-#define portVALID_STACK_MEM(ptr) esp_ptr_byte_accessible(ptr)
-#else
-#define portVALID_STACK_MEM(ptr) (esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr))
-#endif
-
-/*
- * Wrapper for the Xtensa compare-and-set instruction. This subroutine will atomically compare
- * *addr to 'compare'. If *addr == compare, *addr is set to *set. *set is updated with the previous
- * value of *addr (either 'compare' or some other value.)
- *
- * Warning: From the ISA docs: in some (unspecified) cases, the s32c1i instruction may return the
- * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the
- * ESP32 (portMUX assertions would fail).
- */
-static inline void uxPortCompareSet(volatile uint32_t *addr, uint32_t compare, uint32_t *set) {
-    __asm__ __volatile__ (
-        "WSR 	    %2,SCOMPARE1 \n"
-        "S32C1I     %0, %1, 0	 \n"
-        :"=r"(*set)
-        :"r"(addr), "r"(compare), "0"(*set)
-        );
-}
-
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			4
-#define portNOP()					XT_NOP()
-/*-----------------------------------------------------------*/
-
-/* Fine resolution time */
-#define portGET_RUN_TIME_COUNTER_VALUE()  xthal_get_ccount()
-//ccount or esp_timer are initialized elsewhere
-#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
-
-#ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
-/* Coarse resolution time (us) */
-#define portALT_GET_RUN_TIME_COUNTER_VALUE(x)    x = (uint32_t)esp_timer_get_time()
-#endif
-
-
-
-/* Kernel utilities. */
-void vPortYield( void );
-void _frxt_setup_switch( void );
-#define portYIELD()					vPortYield()
-#define portYIELD_FROM_ISR()        {traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch();}
-
-static inline uint32_t xPortGetCoreID();
-
-/* Yielding within an API call (when interrupts are off), means the yield should be delayed
-   until interrupts are re-enabled.
-
-   To do this, we use the "cross-core" interrupt as a trigger to yield on this core when interrupts are re-enabled.This
-   is the same interrupt & code path which is used to trigger a yield between CPUs, although in this case the yield is
-   happening on the same CPU.
-*/
-#define portYIELD_WITHIN_API() esp_crosscore_int_send_yield(xPortGetCoreID())
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-// When coprocessors are defined, we to maintain a pointer to coprocessors area.
-// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
-// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
-// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
-typedef struct {
-	#if XCHAL_CP_NUM > 0
-	volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
-	#endif
-
-	#if portUSING_MPU_WRAPPERS
-	// Define here mpu_settings, which is port dependent
-	int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
-	#endif
-
-	#if configUSE_TRACE_FACILITY_2
-	struct {
-		// Cf. porttraceStamp()
-		int taskstamp;        /* Stamp from inside task to see where we are */
-		int taskstampcount;   /* A counter usually incremented when we restart the task's loop */
-	} porttrace;
-	#endif
-} xMPU_SETTINGS;
-
-// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
-#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS   // If MPU wrappers not used, we still need to allocate coproc area
-	#undef portUSING_MPU_WRAPPERS
-	#define portUSING_MPU_WRAPPERS 1   // Enable it to allocate coproc area
-	#define MPU_WRAPPERS_H             // Override mpu_wrapper.h to disable unwanted code
-	#define PRIVILEGED_FUNCTION
-	#define PRIVILEGED_DATA
-#endif
-
-extern void esp_vApplicationIdleHook( void );
-extern void esp_vApplicationTickHook( void );
-
-#ifndef CONFIG_FREERTOS_LEGACY_HOOKS
-#define vApplicationIdleHook    esp_vApplicationIdleHook
-#define vApplicationTickHook    esp_vApplicationTickHook
-#endif /* !CONFIG_FREERTOS_LEGACY_HOOKS */
-
-void _xt_coproc_release(volatile void * coproc_sa_base);
-void vApplicationSleep( TickType_t xExpectedIdleTime );
-
-#define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime )
-
-// porttrace
-#if configUSE_TRACE_FACILITY_2
-#include "porttrace.h"
-#endif
-
-// configASSERT_2 if requested
-#if configASSERT_2
-#include <stdio.h>
-void exit(int);
-#define configASSERT( x )   if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }
-#endif
-
-#endif // __ASSEMBLER__
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/tools/sdk/include/freertos/freertos/porttrace.h b/tools/sdk/include/freertos/freertos/porttrace.h
deleted file mode 100644
index bf2fb412525..00000000000
--- a/tools/sdk/include/freertos/freertos/porttrace.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-/*
- * This utility helps tracing the entering and exiting from tasks. It maintains a circular buffer
- * of tasks in the order they execute, and their execution time.
- * In order to enable it, set configUSE_TRACE_FACILITY_2 to 1 in FreeRTOSConfig.h.
- * You will also need to download the FreeRTOS_trace patch that contains
- * porttrace.c and the complete version of porttrace.h
- */
-
-#ifndef PORTTRACE_H
-#define PORTTRACE_H
-
-#if configUSE_TRACE_FACILITY_2
-    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
-#endif
-
-#define porttracePrint(nelements)
-#define porttraceStamp(stamp, count_incr)
-
-#endif /* PORTTRACE_H */
diff --git a/tools/sdk/include/freertos/freertos/projdefs.h b/tools/sdk/include/freertos/freertos/projdefs.h
deleted file mode 100644
index 1bd39c58d8b..00000000000
--- a/tools/sdk/include/freertos/freertos/projdefs.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef PROJDEFS_H
-#define PROJDEFS_H
-
-/*
- * Defines the prototype to which task functions must conform.  Defined in this
- * file to ensure the type is known before portable.h is included.
- */
-typedef void (*TaskFunction_t)( void * );
-
-/* Converts a time in milliseconds to a time in ticks. */
-#define pdMS_TO_TICKS( xTimeInMs ) ( ( ( TickType_t ) ( xTimeInMs ) * configTICK_RATE_HZ ) / ( TickType_t ) 1000 )
-
-#define pdFALSE			( ( BaseType_t ) 0 )
-#define pdTRUE			( ( BaseType_t ) 1 )
-
-#define pdPASS			( pdTRUE )
-#define pdFAIL			( pdFALSE )
-#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
-#define errQUEUE_FULL	( ( BaseType_t ) 0 )
-
-/* Error definitions. */
-#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
-#define errQUEUE_BLOCKED						( -4 )
-#define errQUEUE_YIELD							( -5 )
-
-/* Macros used for basic data corruption checks. */
-#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
-	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
-#endif
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
-#else
-	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
-#endif
-
-#endif /* PROJDEFS_H */
-
-
-
diff --git a/tools/sdk/include/freertos/freertos/queue.h b/tools/sdk/include/freertos/freertos/queue.h
deleted file mode 100644
index e15152ee975..00000000000
--- a/tools/sdk/include/freertos/freertos/queue.h
+++ /dev/null
@@ -1,1648 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-
-#ifndef QUEUE_H
-#define QUEUE_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**
- * Type by which queues are referenced.  For example, a call to xQueueCreate()
- * returns an QueueHandle_t variable that can then be used as a parameter to
- * xQueueSend(), xQueueReceive(), etc.
- */
-typedef void * QueueHandle_t;
-
-/**
- * Type by which queue sets are referenced.  For example, a call to
- * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
- * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
- */
-typedef void * QueueSetHandle_t;
-
-/**
- * Queue sets can contain both queues and semaphores, so the
- * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
- * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
- */
-typedef void * QueueSetMemberHandle_t;
-
-/** @cond */
-/* For internal use only. */
-#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
-#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
-#define queueOVERWRITE			( ( BaseType_t ) 2 )
-
-/* For internal use only.  These definitions *must* match those in queue.c. */
-#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
-#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
-#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
-#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
-
-/** @endcond */
-
-/**
- * Creates a new queue instance.  This allocates the storage required by the
- * new queue and returns a handle for the queue.
- *
- * @param uxQueueLength The maximum number of items that the queue can contain.
- *
- * @param uxItemSize The number of bytes each item in the queue will require.
- * Items are queued by copy, not by reference, so this is the number of bytes
- * that will be copied for each posted item.  Each item on the queue must be
- * the same size.
- *
- * @return If the queue is successfully create then a handle to the newly
- * created queue is returned.  If the queue cannot be created then 0 is
- * returned.
- *
- * Example usage:
- * @code{c}
- *  struct AMessage
- *  {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- *  };
- *
- *  void vATask( void *pvParameters )
- *  {
- *  QueueHandle_t xQueue1, xQueue2;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *  if( xQueue1 == 0 )
- *  {
- *      // Queue was not created and must not be used.
- *  }
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *  if( xQueue2 == 0 )
- *  {
- *      // Queue was not created and must not be used.
- *  }
- *
- *  // ... Rest of task code.
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
-#endif
-
-/**
- * Creates a new queue instance, and returns a handle by which the new queue
- * can be referenced.
- *
- * Internally, within the FreeRTOS implementation, queues use two blocks of
- * memory.  The first block is used to hold the queue's data structures.  The
- * second block is used to hold items placed into the queue.  If a queue is
- * created using xQueueCreate() then both blocks of memory are automatically
- * dynamically allocated inside the xQueueCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a queue is created using
- * xQueueCreateStatic() then the application writer must provide the memory that
- * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
- * be created without using any dynamic memory allocation.
- *
- * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
- *
- * @param uxQueueLength The maximum number of items that the queue can contain.
- *
- * @param uxItemSize The number of bytes each item in the queue will require.
- * Items are queued by copy, not by reference, so this is the number of bytes
- * that will be copied for each posted item.  Each item on the queue must be
- * the same size.
- *
- * @param pucQueueStorage If uxItemSize is not zero then
- * pucQueueStorageBuffer must point to a uint8_t array that is at least large
- * enough to hold the maximum number of items that can be in the queue at any
- * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
- * zero then pucQueueStorageBuffer can be NULL.
- *
- * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
- * will be used to hold the queue's data structure.
- *
- * @return If the queue is created then a handle to the created queue is
- * returned.  If pxQueueBuffer is NULL then NULL is returned.
- *
- * Example usage:
- * @code{c}
- * struct AMessage
- * {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- * };
- *
- * #define QUEUE_LENGTH 10
- * #define ITEM_SIZE sizeof( uint32_t )
- *
- * // xQueueBuffer will hold the queue structure.
- * StaticQueue_t xQueueBuffer;
- *
- * // ucQueueStorage will hold the items posted to the queue.  Must be at least
- * // [(queue length) * ( queue item size)] bytes long.
- * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
- *
- * void vATask( void *pvParameters )
- * {
- *  QueueHandle_t xQueue1;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
- *                          ITEM_SIZE     // The size of each item in the queue
- *                          &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
- *                          &xQueueBuffer ); // The buffer that will hold the queue structure.
- *
- *  // The queue is guaranteed to be created successfully as no dynamic memory
- *  // allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
- *
- *  // ... Rest of task code.
- * }
- * @endcode
- * \ingroup QueueManagement
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * This is a macro that calls xQueueGenericSend().
- *
- * Post an item to the front of a queue.  The item is queued by copy, not by
- * reference.  This function must not be called from an interrupt service
- * routine.  See xQueueSendFromISR () for an alternative which may be used
- * in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * @code{c}
- *  struct AMessage
- *  {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- *  } xMessage;
- *
- *  uint32_t ulVar = 10UL;
- *
- *  void vATask( void *pvParameters )
- *  {
- *  QueueHandle_t xQueue1, xQueue2;
- *  struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *
- *  // ...
- *
- *  if( xQueue1 != 0 )
- *  {
- *      // Send an uint32_t.  Wait for 10 ticks for space to become
- *      // available if necessary.
- *      if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
- *      {
- *          // Failed to post the message, even after 10 ticks.
- *      }
- *  }
- *
- *  if( xQueue2 != 0 )
- *  {
- *      // Send a pointer to a struct AMessage object.  Don't block if the
- *      // queue is already full.
- *      pxMessage = & xMessage;
- *      xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *  }
- *
- *  // ... Rest of task code.
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
-
-/**
- * This is a macro that calls xQueueGenericSend().
- *
- * Post an item to the back of a queue.  The item is queued by copy, not by
- * reference.  This function must not be called from an interrupt service
- * routine.  See xQueueSendFromISR () for an alternative which may be used
- * in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the queue
- * is full.  The  time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * @code{c}
- *  struct AMessage
- *  {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- *  } xMessage;
- *
- *  uint32_t ulVar = 10UL;
- *
- *  void vATask( void *pvParameters )
- *  {
- *  QueueHandle_t xQueue1, xQueue2;
- *  struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *
- *  // ...
- *
- *  if( xQueue1 != 0 )
- *  {
- *      // Send an uint32_t.  Wait for 10 ticks for space to become
- *      // available if necessary.
- *      if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
- *      {
- *          // Failed to post the message, even after 10 ticks.
- *      }
- *  }
- *
- *  if( xQueue2 != 0 )
- *  {
- *      // Send a pointer to a struct AMessage object.  Don't block if the
- *      // queue is already full.
- *      pxMessage = & xMessage;
- *      xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *  }
- *
- *  // ... Rest of task code.
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
-
-/**
- * This is a macro that calls xQueueGenericSend().  It is included for
- * backward compatibility with versions of FreeRTOS.org that did not
- * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
- * equivalent to xQueueSendToBack().
- *
- * Post an item on a queue.  The item is queued by copy, not by reference.
- * This function must not be called from an interrupt service routine.
- * See xQueueSendFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * @code{c}
- *  struct AMessage
- *  {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- *  } xMessage;
- *
- *  uint32_t ulVar = 10UL;
- *
- *  void vATask( void *pvParameters )
- *  {
- *  QueueHandle_t xQueue1, xQueue2;
- *  struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *
- *  // ...
- *
- *  if( xQueue1 != 0 )
- *  {
- *      // Send an uint32_t.  Wait for 10 ticks for space to become
- *      // available if necessary.
- *      if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
- *      {
- *          // Failed to post the message, even after 10 ticks.
- *      }
- *  }
- *
- *  if( xQueue2 != 0 )
- *  {
- *      // Send a pointer to a struct AMessage object.  Don't block if the
- *      // queue is already full.
- *      pxMessage = & xMessage;
- *      xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *  }
- *
- *  // ... Rest of task code.
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
-
-/**
- * Only for use with queues that have a length of one - so the queue is either
- * empty or full.
- *
- * Post an item on a queue.  If the queue is already full then overwrite the
- * value held in the queue.  The item is queued by copy, not by reference.
- *
- * This function must not be called from an interrupt service routine.
- * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle of the queue to which the data is being sent.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
- * therefore has the same return values as xQueueSendToFront().  However, pdPASS
- * is the only value that can be returned because xQueueOverwrite() will write
- * to the queue even when the queue is already full.
- *
- * Example usage:
- * @code{c}
- *
- *  void vFunction( void *pvParameters )
- *  {
- *  QueueHandle_t xQueue;
- *  uint32_t ulVarToSend, ulValReceived;
- *
- *  // Create a queue to hold one uint32_t value.  It is strongly
- *  // recommended *not* to use xQueueOverwrite() on queues that can
- *  // contain more than one value, and doing so will trigger an assertion
- *  // if configASSERT() is defined.
- *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
- *
- *  // Write the value 10 to the queue using xQueueOverwrite().
- *  ulVarToSend = 10;
- *  xQueueOverwrite( xQueue, &ulVarToSend );
- *
- *  // Peeking the queue should now return 10, but leave the value 10 in
- *  // the queue.  A block time of zero is used as it is known that the
- *  // queue holds a value.
- *  ulValReceived = 0;
- *  xQueuePeek( xQueue, &ulValReceived, 0 );
- *
- *  if( ulValReceived != 10 )
- *  {
- *      // Error unless the item was removed by a different task.
- *  }
- *
- *  // The queue is still full.  Use xQueueOverwrite() to overwrite the
- *  // value held in the queue with 100.
- *  ulVarToSend = 100;
- *  xQueueOverwrite( xQueue, &ulVarToSend );
- *
- *  // This time read from the queue, leaving the queue empty once more.
- *  // A block time of 0 is used again.
- *  xQueueReceive( xQueue, &ulValReceived, 0 );
- *
- *  // The value read should be the last value written, even though the
- *  // queue was already full when the value was written.
- *  if( ulValReceived != 100 )
- *  {
- *      // Error!
- *  }
- *
- *  // ...
- * }
- * @endcode
- * \ingroup QueueManagement
- */
-#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
-
-
-/**
- * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
- * xQueueSendToBack() are used in place of calling this function directly.
- *
- * Post an item on a queue.  The item is queued by copy, not by reference.
- * This function must not be called from an interrupt service routine.
- * See xQueueSendFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
- * item at the back of the queue, or queueSEND_TO_FRONT to place the item
- * at the front of the queue (for high priority messages).
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * @code{c}
- *  struct AMessage
- *  {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- *  } xMessage;
- *
- *  uint32_t ulVar = 10UL;
- *
- *  void vATask( void *pvParameters )
- *  {
- *  QueueHandle_t xQueue1, xQueue2;
- *  struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 uint32_t values.
- *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *
- *  // ...
- *
- *  if( xQueue1 != 0 )
- *  {
- *      // Send an uint32_t.  Wait for 10 ticks for space to become
- *      // available if necessary.
- *      if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
- *      {
- *          // Failed to post the message, even after 10 ticks.
- *      }
- *  }
- *
- *  if( xQueue2 != 0 )
- *  {
- *      // Send a pointer to a struct AMessage object.  Don't block if the
- *      // queue is already full.
- *      pxMessage = & xMessage;
- *      xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
- *  }
- *
- *  // ... Rest of task code.
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-
-/**
- * This is a macro that calls the xQueueGenericReceive() function.
- *
- * Receive an item from a queue without removing the item from the queue.
- * The item is received by copy so a buffer of adequate size must be
- * provided.  The number of bytes copied into the buffer was defined when
- * the queue was created.
- *
- * Successfully received items remain on the queue so will be returned again
- * by the next call, or a call to xQueueReceive().
- *
- * This macro must not be used in an interrupt service routine.  See
- * xQueuePeekFromISR() for an alternative that can be called from an interrupt
- * service routine.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call.	 The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
- * is empty.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
- * @code{c}
- *  struct AMessage
- *  {
- *  char ucMessageID;
- *  char ucData[ 20 ];
- *  } xMessage;
- *
- *  QueueHandle_t xQueue;
- *
- *  // Task to create a queue and post a value.
- *  void vATask( void *pvParameters )
- *  {
- *  struct AMessage *pxMessage;
- *
- *  // Create a queue capable of containing 10 pointers to AMessage structures.
- *  // These should be passed by pointer as they contain a lot of data.
- *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *  if( xQueue == 0 )
- *  {
- *      // Failed to create the queue.
- *  }
- *
- *  // ...
- *
- *  // Send a pointer to a struct AMessage object.  Don't block if the
- *  // queue is already full.
- *  pxMessage = & xMessage;
- *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *
- *  // ... Rest of task code.
- *  }
- *
- *  // Task to peek the data from the queue.
- *  void vADifferentTask( void *pvParameters )
- *  {
- *  struct AMessage *pxRxedMessage;
- *
- *  if( xQueue != 0 )
- *  {
- *      // Peek a message on the created queue.  Block for 10 ticks if a
- *      // message is not immediately available.
- *      if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
- *      {
- *          // pcRxedMessage now points to the struct AMessage variable posted
- *          // by vATask, but the item still remains on the queue.
- *      }
- *  }
- *
- *  // ... Rest of task code.
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )
-
-/**
- * A version of xQueuePeek() that can be called from an interrupt service
- * routine (ISR).
- *
- * Receive an item from a queue without removing the item from the queue.
- * The item is received by copy so a buffer of adequate size must be
- * provided.  The number of bytes copied into the buffer was defined when
- * the queue was created.
- *
- * Successfully received items remain on the queue so will be returned again
- * by the next call, or a call to xQueueReceive().
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * \ingroup QueueManagement
- */
-BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * <pre>
- BaseType_t xQueueReceive(
-								 QueueHandle_t xQueue,
-								 void *pvBuffer,
-								 TickType_t xTicksToWait
-							);</pre>
- *
- * This is a macro that calls the xQueueGenericReceive() function.
- *
- * Receive an item from a queue.  The item is received by copy so a buffer of
- * adequate size must be provided.  The number of bytes copied into the buffer
- * was defined when the queue was created.
- *
- * Successfully received items are removed from the queue.
- *
- * This function must not be used in an interrupt service routine.  See
- * xQueueReceiveFromISR for an alternative that can.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call.	 xQueueReceive() will return immediately if xTicksToWait
- * is zero and the queue is empty.  The time is defined in tick periods so the
- * constant portTICK_PERIOD_MS should be used to convert to real time if this is
- * required.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
- * @code{c}
- *  struct AMessage
- *  {
- * 	char ucMessageID;
- * 	char ucData[ 20 ];
- *  } xMessage;
- *
- *  QueueHandle_t xQueue;
- *
- *  // Task to create a queue and post a value.
- *  void vATask( void *pvParameters )
- *  {
- *  struct AMessage *pxMessage;
- *
- * 	// Create a queue capable of containing 10 pointers to AMessage structures.
- * 	// These should be passed by pointer as they contain a lot of data.
- * 	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
- * 	if( xQueue == 0 )
- * 	{
- * 		// Failed to create the queue.
- * 	}
- *
- * 	// ...
- *
- * 	// Send a pointer to a struct AMessage object.  Don't block if the
- * 	// queue is already full.
- * 	pxMessage = & xMessage;
- * 	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *
- * 	// ... Rest of task code.
- *  }
- *
- *  // Task to receive from the queue.
- *  void vADifferentTask( void *pvParameters )
- *  {
- *  struct AMessage *pxRxedMessage;
- *
- * 	if( xQueue != 0 )
- * 	{
- * 		// Receive a message on the created queue.  Block for 10 ticks if a
- * 		// message is not immediately available.
- * 		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
- * 		{
- * 			// pcRxedMessage now points to the struct AMessage variable posted
- * 			// by vATask.
- * 		}
- * 	}
- *
- * 	// ... Rest of task code.
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )
-
-
-/**
- * It is preferred that the macro xQueueReceive() be used rather than calling
- * this function directly.
- *
- * Receive an item from a queue.  The item is received by copy so a buffer of
- * adequate size must be provided.  The number of bytes copied into the buffer
- * was defined when the queue was created.
- *
- * This function must not be used in an interrupt service routine.  See
- * xQueueReceiveFromISR for an alternative that can.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call.	 The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- * xQueueGenericReceive() will return immediately if the queue is empty and
- * xTicksToWait is 0.
- *
- * @param xJustPeek When set to true, the item received from the queue is not
- * actually removed from the queue - meaning a subsequent call to
- * xQueueReceive() will return the same item.  When set to false, the item
- * being received from the queue is also removed from the queue.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
- * @code{c}
- *  struct AMessage
- *  {
- * 	char ucMessageID;
- * 	char ucData[ 20 ];
- *  } xMessage;
- *
- *  QueueHandle_t xQueue;
- *
- *  // Task to create a queue and post a value.
- *  void vATask( void *pvParameters )
- *  {
- *  struct AMessage *pxMessage;
- *
- * 	// Create a queue capable of containing 10 pointers to AMessage structures.
- * 	// These should be passed by pointer as they contain a lot of data.
- * 	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
- * 	if( xQueue == 0 )
- * 	{
- * 		// Failed to create the queue.
- * 	}
- *
- * 	// ...
- *
- * 	// Send a pointer to a struct AMessage object.  Don't block if the
- * 	// queue is already full.
- * 	pxMessage = & xMessage;
- * 	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
- *
- * 	// ... Rest of task code.
- *  }
- *
- *  // Task to receive from the queue.
- *  void vADifferentTask( void *pvParameters )
- *  {
- *  struct AMessage *pxRxedMessage;
- *
- * 	if( xQueue != 0 )
- * 	{
- * 		// Receive a message on the created queue.  Block for 10 ticks if a
- * 		// message is not immediately available.
- * 		if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
- * 		{
- * 			// pcRxedMessage now points to the struct AMessage variable posted
- * 			// by vATask.
- * 		}
- * 	}
- *
- * 	// ... Rest of task code.
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek ) PRIVILEGED_FUNCTION;
-
-/**
- * Return the number of messages stored in a queue.
- *
- * @param xQueue A handle to the queue being queried.
- *
- * @return The number of messages available in the queue.
- *
- * \ingroup QueueManagement
- */
-UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * Return the number of free spaces available in a queue.  This is equal to the
- * number of items that can be sent to the queue before the queue becomes full
- * if no items are removed.
- *
- * @param xQueue A handle to the queue being queried.
- *
- * @return The number of spaces available in the queue.
- *
- * \ingroup QueueManagement
- */
-UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * Delete a queue - freeing all the memory allocated for storing of items
- * placed on the queue.
- *
- * @param xQueue A handle to the queue to be deleted.
- *
- * \ingroup QueueManagement
- */
-void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * This is a macro that calls xQueueGenericSendFromISR().
- *
- * Post an item to the front of a queue.  It is safe to use this macro from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param[out] pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
- * @code{c}
- *  void vBufferISR( void )
- *  {
- *  char cIn;
- *  BaseType_t xHigherPrioritTaskWoken;
- *
- * 	// We have not woken a task at the start of the ISR.
- * 	xHigherPriorityTaskWoken = pdFALSE;
- *
- * 	// Loop until the buffer is empty.
- * 	do
- * 	{
- * 		// Obtain a byte from the buffer.
- * 		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
- *
- * 		// Post the byte.
- * 		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
- *
- * 	} while( portINPUT_BYTE( BUFFER_COUNT ) );
- *
- * 	// Now the buffer is empty we can switch context if necessary.
- * 	if( xHigherPriorityTaskWoken )
- * 	{
- * 		portYIELD_FROM_ISR ();
- * 	}
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
-
-
-/**
- * This is a macro that calls xQueueGenericSendFromISR().
- *
- * Post an item to the back of a queue.  It is safe to use this macro from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param[out] pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
- * @code{c}
- *  void vBufferISR( void )
- *  {
- *  char cIn;
- *  BaseType_t xHigherPriorityTaskWoken;
- *
- * 	// We have not woken a task at the start of the ISR.
- * 	xHigherPriorityTaskWoken = pdFALSE;
- *
- * 	// Loop until the buffer is empty.
- * 	do
- * 	{
- * 		// Obtain a byte from the buffer.
- * 		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
- *
- * 		// Post the byte.
- * 		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
- *
- * 	} while( portINPUT_BYTE( BUFFER_COUNT ) );
- *
- * 	// Now the buffer is empty we can switch context if necessary.
- * 	if( xHigherPriorityTaskWoken )
- * 	{
- * 		portYIELD_FROM_ISR ();
- * 	}
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
-
-/**
- * A version of xQueueOverwrite() that can be used in an interrupt service
- * routine (ISR).
- *
- * Only for use with queues that can hold a single item - so the queue is either
- * empty or full.
- *
- * Post an item on a queue.  If the queue is already full then overwrite the
- * value held in the queue.  The item is queued by copy, not by reference.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param[out] pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return xQueueOverwriteFromISR() is a macro that calls
- * xQueueGenericSendFromISR(), and therefore has the same return values as
- * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
- * returned because xQueueOverwriteFromISR() will write to the queue even when
- * the queue is already full.
- *
- * Example usage:
- * @code{c}
- *  QueueHandle_t xQueue;
- *
- *  void vFunction( void *pvParameters )
- *  {
- *  	// Create a queue to hold one uint32_t value.  It is strongly
- * 	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
- * 	// contain more than one value, and doing so will trigger an assertion
- * 	// if configASSERT() is defined.
- * 	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
- * }
- *
- * void vAnInterruptHandler( void )
- * {
- * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- * uint32_t ulVarToSend, ulValReceived;
- *
- * 	// Write the value 10 to the queue using xQueueOverwriteFromISR().
- * 	ulVarToSend = 10;
- * 	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
- *
- * 	// The queue is full, but calling xQueueOverwriteFromISR() again will still
- * 	// pass because the value held in the queue will be overwritten with the
- * 	// new value.
- * 	ulVarToSend = 100;
- * 	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
- *
- * 	// Reading from the queue will now return 100.
- *
- * 	// ...
- *
- * 	if( xHigherPrioritytaskWoken == pdTRUE )
- * 	{
- * 		// Writing to the queue caused a task to unblock and the unblocked task
- * 		// has a priority higher than or equal to the priority of the currently
- * 		// executing task (the task this interrupt interrupted).  Perform a context
- * 		// switch so this interrupt returns directly to the unblocked task.
- * 		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
- * 	}
- * }
- * @endcode
- * \ingroup QueueManagement
- */
-#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
-
-/**
- * This is a macro that calls xQueueGenericSendFromISR().  It is included
- * for backward compatibility with versions of FreeRTOS.org that did not
- * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
- * macros.
- *
- * Post an item to the back of a queue.  It is safe to use this function from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param[out] pxHigherPriorityTaskWoken xQueueSendFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
- * @code{c}
- *  void vBufferISR( void )
- *  {
- *  char cIn;
- *  BaseType_t xHigherPriorityTaskWoken;
- *
- * 	// We have not woken a task at the start of the ISR.
- * 	xHigherPriorityTaskWoken = pdFALSE;
- *
- * 	// Loop until the buffer is empty.
- * 	do
- * 	{
- * 		// Obtain a byte from the buffer.
- * 		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
- *
- * 		// Post the byte.
- * 		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
- *
- * 	} while( portINPUT_BYTE( BUFFER_COUNT ) );
- *
- * 	// Now the buffer is empty we can switch context if necessary.
- * 	if( xHigherPriorityTaskWoken )
- * 	{
- * 		// Actual macro used here is port specific.
- * 		portYIELD_FROM_ISR ();
- * 	}
- *  }
- * @endcode
- *
- * \ingroup QueueManagement
- */
-#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
-
-/**@{*/
-/**
- * It is preferred that the macros xQueueSendFromISR(),
- * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
- * of calling this function directly.  xQueueGiveFromISR() is an
- * equivalent for use by semaphores that don't actually copy any data.
- *
- * Post an item on a queue.  It is safe to use this function from within an
- * interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param[out] pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
- * item at the back of the queue, or queueSEND_TO_FRONT to place the item
- * at the front of the queue (for high priority messages).
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
- * @code{c}
- *  void vBufferISR( void )
- *  {
- *  char cIn;
- *  BaseType_t xHigherPriorityTaskWokenByPost;
- *
- * 	// We have not woken a task at the start of the ISR.
- * 	xHigherPriorityTaskWokenByPost = pdFALSE;
- *
- * 	// Loop until the buffer is empty.
- * 	do
- * 	{
- * 		// Obtain a byte from the buffer.
- * 		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
- *
- * 		// Post each byte.
- * 		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
- *
- * 	} while( portINPUT_BYTE( BUFFER_COUNT ) );
- *
- * 	// Now the buffer is empty we can switch context if necessary.  Note that the
- * 	// name of the yield function required is port specific.
- * 	if( xHigherPriorityTaskWokenByPost )
- * 	{
- * 		taskYIELD_YIELD_FROM_ISR();
- * 	}
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-/**@}*/
-
-/**
- * Receive an item from a queue.  It is safe to use this function from within an
- * interrupt service routine.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param[out] pxHigherPriorityTaskWoken A task may be blocked waiting for space to become
- * available on the queue.  If xQueueReceiveFromISR causes such a task to
- * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
- * remain unchanged.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
- * @code{c}
- *  QueueHandle_t xQueue;
- *
- *  // Function to create a queue and post some values.
- *  void vAFunction( void *pvParameters )
- *  {
- *  char cValueToPost;
- *  const TickType_t xTicksToWait = ( TickType_t )0xff;
- *
- * 	// Create a queue capable of containing 10 characters.
- * 	xQueue = xQueueCreate( 10, sizeof( char ) );
- * 	if( xQueue == 0 )
- * 	{
- * 		// Failed to create the queue.
- * 	}
- *
- * 	// ...
- *
- * 	// Post some characters that will be used within an ISR.  If the queue
- * 	// is full then this task will block for xTicksToWait ticks.
- * 	cValueToPost = 'a';
- * 	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
- * 	cValueToPost = 'b';
- * 	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
- *
- * 	// ... keep posting characters ... this task may block when the queue
- * 	// becomes full.
- *
- * 	cValueToPost = 'c';
- * 	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
- *  }
- *
- *  // ISR that outputs all the characters received on the queue.
- *  void vISR_Routine( void )
- *  {
- *  BaseType_t xTaskWokenByReceive = pdFALSE;
- *  char cRxedChar;
- *
- * 	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
- * 	{
- * 		// A character was received.  Output the character now.
- * 		vOutputCharacter( cRxedChar );
- *
- * 		// If removing the character from the queue woke the task that was
- * 		// posting onto the queue cTaskWokenByReceive will have been set to
- * 		// pdTRUE.  No matter how many times this loop iterates only one
- * 		// task will be woken.
- * 	}
- *
- * 	if( cTaskWokenByPost != ( char ) pdFALSE;
- * 	{
- * 		taskYIELD ();
- * 	}
- *  }
- * @endcode
- * \ingroup QueueManagement
- */
-BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**@{*/
-/**
- * Utilities to query queues that are safe to use from an ISR.  These utilities
- * should be used only from witin an ISR, or within a critical section.
- */
-BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-/**@}*/
-
-/** @cond */
-/**
- * xQueueAltGenericSend() is an alternative version of xQueueGenericSend().
- * Likewise xQueueAltGenericReceive() is an alternative version of
- * xQueueGenericReceive().
- *
- * The source code that implements the alternative (Alt) API is much
- * simpler	because it executes everything from within a critical section.
- * This is	the approach taken by many other RTOSes, but FreeRTOS.org has the
- * preferred fully featured API too.  The fully featured API has more
- * complex	code that takes longer to execute, but makes much less use of
- * critical sections.  Therefore the alternative API sacrifices interrupt
- * responsiveness to gain execution speed, whereas the fully featured API
- * sacrifices execution speed to ensure better interrupt responsiveness.
- */
-BaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition );
-BaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking );
-#define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
-#define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
-#define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )
-#define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )
-
-/*
- * The functions defined above are for passing data to and from tasks.  The
- * functions below are the equivalents for passing data to and from
- * co-routines.
- *
- * These functions are called from the co-routine macro implementation and
- * should not be called directly from application code.  Instead use the macro
- * wrappers defined within croutine.h.
- */
-BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
-BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
-BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
-BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
-
-/*
- * For internal use only.  Use xSemaphoreCreateMutex(),
- * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
- * these functions directly.
- */
-QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
-void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
- * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
- */
-BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION;
-/** @endcond */
-
-/**
- * Reset a queue back to its original empty state.  pdPASS is returned if the
- * queue is successfully reset.  pdFAIL is returned if the queue could not be
- * reset because there are tasks blocked on the queue waiting to either
- * receive from the queue or send to the queue.
- *
- * @param xQueue The queue to reset
- * @return always returns pdPASS
- */
-#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
-
-/**
- * The registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
- * a queue, semaphore or mutex handle to the registry if you want the handle
- * to be available to a kernel aware debugger.  If you are not using a kernel
- * aware debugger then this function can be ignored.
- *
- * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
- * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
- * within FreeRTOSConfig.h for the registry to be available.  Its value
- * does not effect the number of queues, semaphores and mutexes that can be
- * created - just the number that the registry can hold.
- *
- * @param xQueue The handle of the queue being added to the registry.  This
- * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
- * handles can also be passed in here.
- *
- * @param pcName The name to be associated with the handle.  This is the
- * name that the kernel aware debugger will display.  The queue registry only
- * stores a pointer to the string - so the string must be persistent (global or
- * preferably in ROM/Flash), not on the stack.
- */
-#if configQUEUE_REGISTRY_SIZE > 0
-	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-#endif
-
-/**
- * The registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
- * a queue, semaphore or mutex handle to the registry if you want the handle
- * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
- * remove the queue, semaphore or mutex from the register.  If you are not using
- * a kernel aware debugger then this function can be ignored.
- *
- * @param xQueue The handle of the queue being removed from the registry.
- */
-#if configQUEUE_REGISTRY_SIZE > 0
-	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * @note This function has been back ported from FreeRTOS v9.0.0
- *
- * The queue registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
- * up and return the name of a queue in the queue registry from the queue's
- * handle.
- *
- * @param xQueue The handle of the queue the name of which will be returned.
- * @return If the queue is in the registry then a pointer to the name of the
- * queue is returned.  If the queue is not in the registry then NULL is
- * returned.
- */
-#if( configQUEUE_REGISTRY_SIZE > 0 )
-	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-#endif
-
-/**
- * Generic version of the function used to creaet a queue using dynamic memory
- * allocation.  This is called by other functions and macros that create other
- * RTOS objects that use the queue structure as their base.
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * Generic version of the function used to creaet a queue using dynamic memory
- * allocation.  This is called by other functions and macros that create other
- * RTOS objects that use the queue structure as their base.
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * Queue sets provide a mechanism to allow a task to block (pend) on a read
- * operation from multiple queues or semaphores simultaneously.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * A queue set must be explicitly created using a call to xQueueCreateSet()
- * before it can be used.  Once created, standard FreeRTOS queues and semaphores
- * can be added to the set using calls to xQueueAddToSet().
- * xQueueSelectFromSet() is then used to determine which, if any, of the queues
- * or semaphores contained in the set is in a state where a queue read or
- * semaphore take operation would be successful.
- *
- * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
- * for reasons why queue sets are very rarely needed in practice as there are
- * simpler methods of blocking on multiple objects.
- *
- * Note 2:  Blocking on a queue set that contains a mutex will not cause the
- * mutex holder to inherit the priority of the blocked task.
- *
- * Note 3:  An additional 4 bytes of RAM is required for each space in a every
- * queue added to a queue set.  Therefore counting semaphores that have a high
- * maximum count value should not be added to a queue set.
- *
- * Note 4:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param uxEventQueueLength Queue sets store events that occur on
- * the queues and semaphores contained in the set.  uxEventQueueLength specifies
- * the maximum number of events that can be queued at once.  To be absolutely
- * certain that events are not lost uxEventQueueLength should be set to the
- * total sum of the length of the queues added to the set, where binary
- * semaphores and mutexes have a length of 1, and counting semaphores have a
- * length set by their maximum count value.  Examples:
- *  + If a queue set is to hold a queue of length 5, another queue of length 12,
- *    and a binary semaphore, then uxEventQueueLength should be set to
- *    (5 + 12 + 1), or 18.
- *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
- *    should be set to (1 + 1 + 1 ), or 3.
- *  + If a queue set is to hold a counting semaphore that has a maximum count of
- *    5, and a counting semaphore that has a maximum count of 3, then
- *    uxEventQueueLength should be set to (5 + 3), or 8.
- *
- * @return If the queue set is created successfully then a handle to the created
- * queue set is returned.  Otherwise NULL is returned.
- */
-QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
-
-/**
- * Adds a queue or semaphore to a queue set that was previously created by a
- * call to xQueueCreateSet().
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * Note 1:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
- * the queue set (cast to an QueueSetMemberHandle_t type).
- *
- * @param xQueueSet The handle of the queue set to which the queue or semaphore
- * is being added.
- *
- * @return If the queue or semaphore was successfully added to the queue set
- * then pdPASS is returned.  If the queue could not be successfully added to the
- * queue set because it is already a member of a different queue set then pdFAIL
- * is returned.
- */
-BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/**
- * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
- * be removed from a set if the queue or semaphore is empty.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
- * from the queue set (cast to an QueueSetMemberHandle_t type).
- *
- * @param xQueueSet The handle of the queue set in which the queue or semaphore
- * is included.
- *
- * @return If the queue or semaphore was successfully removed from the queue set
- * then pdPASS is returned.  If the queue was not in the queue set, or the
- * queue (or semaphore) was not empty, then pdFAIL is returned.
- */
-BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/**
- * xQueueSelectFromSet() selects from the members of a queue set a queue or
- * semaphore that either contains data (in the case of a queue) or is available
- * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
- * allows a task to block (pend) on a read operation on all the queues and
- * semaphores in a queue set simultaneously.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
- * for reasons why queue sets are very rarely needed in practice as there are
- * simpler methods of blocking on multiple objects.
- *
- * Note 2:  Blocking on a queue set that contains a mutex will not cause the
- * mutex holder to inherit the priority of the blocked task.
- *
- * Note 3:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param xQueueSet The queue set on which the task will (potentially) block.
- *
- * @param xTicksToWait The maximum time, in ticks, that the calling task will
- * remain in the Blocked state (with other tasks executing) to wait for a member
- * of the queue set to be ready for a successful queue read or semaphore take
- * operation.
- *
- * @return xQueueSelectFromSet() will return the handle of a queue (cast to
- * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
- * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
- * in the queue set that is available, or NULL if no such queue or semaphore
- * exists before before the specified block time expires.
- */
-QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * A version of xQueueSelectFromSet() that can be used from an ISR.
- */
-QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/** @cond */
-/* Not public API functions. */
-void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
-void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-/** @endcond */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* QUEUE_H */
-
diff --git a/tools/sdk/include/freertos/freertos/semphr.h b/tools/sdk/include/freertos/freertos/semphr.h
deleted file mode 100644
index abe3819f8f3..00000000000
--- a/tools/sdk/include/freertos/freertos/semphr.h
+++ /dev/null
@@ -1,1118 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef SEMAPHORE_H
-#define SEMAPHORE_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
-#endif
-
-#include "queue.h"
-
-typedef QueueHandle_t SemaphoreHandle_t;
-
-#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
-#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
-#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
-
-/** @cond */
-/**
- * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
- * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
- * the vSemaphoreCreateBinary() macro are created in a state such that the
- * first call to 'take' the semaphore would pass, whereas binary semaphores
- * created using xSemaphoreCreateBinary() are created in a state such that the
- * the semaphore must first be 'given' before it can be 'taken'.
- *
- * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.
- * The queue length is 1 as this is a binary semaphore.  The data size is 0
- * as we don't want to actually store any data - we just want to know if the
- * queue is empty or full.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xSemaphore = NULL;
- *
- *  void vATask( void * pvParameters )
- *  {
- *     // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
- *     // This is a macro so pass the variable in directly.
- *     vSemaphoreCreateBinary( xSemaphore );
- *
- *     if( xSemaphore != NULL )
- *     {
- *         // The semaphore was created successfully.
- *         // The semaphore can now be used.
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define vSemaphoreCreateBinary( xSemaphore )																							\
-		{																																	\
-			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
-			if( ( xSemaphore ) != NULL )																									\
-			{																																\
-				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
-			}																																\
-		}
-#endif
-/** @endcond */
-
-/**
- * Creates a new binary semaphore instance, and returns a handle by which the
- * new semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, binary semaphores use a block
- * of memory, in which the semaphore structure is stored.  If a binary semaphore
- * is created using xSemaphoreCreateBinary() then the required memory is
- * automatically dynamically allocated inside the xSemaphoreCreateBinary()
- * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
- * is created using xSemaphoreCreateBinaryStatic() then the application writer
- * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
- * binary semaphore to be created without using any dynamic memory allocation.
- *
- * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
- * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
- * the vSemaphoreCreateBinary() macro are created in a state such that the
- * first call to 'take' the semaphore would pass, whereas binary semaphores
- * created using xSemaphoreCreateBinary() are created in a state such that the
- * the semaphore must first be 'given' before it can be 'taken'.
- *
- * Function that creates a semaphore by using the existing queue mechanism.
- * The queue length is 1 as this is a binary semaphore.  The data size is 0
- * as nothing is actually stored - all that is important is whether the queue is
- * empty or full (the binary semaphore is available or not).
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @return Handle to the created semaphore.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xSemaphore = NULL;
- *
- *  void vATask( void * pvParameters )
- *  {
- *     // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
- *     // This is a macro so pass the variable in directly.
- *     xSemaphore = xSemaphoreCreateBinary();
- *
- *     if( xSemaphore != NULL )
- *     {
- *         // The semaphore was created successfully.
- *         // The semaphore can now be used.
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
-#endif
-
-/**
- * Creates a new binary semaphore instance, and returns a handle by which the
- * new semaphore can be referenced.
- *
- * NOTE: In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, binary semaphores use a block
- * of memory, in which the semaphore structure is stored.  If a binary semaphore
- * is created using xSemaphoreCreateBinary() then the required memory is
- * automatically dynamically allocated inside the xSemaphoreCreateBinary()
- * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
- * is created using xSemaphoreCreateBinaryStatic() then the application writer
- * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
- * binary semaphore to be created without using any dynamic memory allocation.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @param pxStaticSemaphore Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the semaphore's data structure, removing the
- * need for the memory to be allocated dynamically.
- *
- * @return If the semaphore is created then a handle to the created semaphore is
- * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xSemaphore = NULL;
- *  StaticSemaphore_t xSemaphoreBuffer;
- *
- *  void vATask( void * pvParameters )
- *  {
- *     // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
- *     // The semaphore's data structures will be placed in the xSemaphoreBuffer
- *     // variable, the address of which is passed into the function.  The
- *     // function's parameter is not NULL, so the function will not attempt any
- *     // dynamic memory allocation, and therefore the function will not return
- *     // return NULL.
- *     xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
- *
- *     // Rest of task code goes here.
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been
- * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
- * xSemaphoreCreateCounting().
- *
- * @param xSemaphore A handle to the semaphore being taken - obtained when
- * the semaphore was created.
- *
- * @param xBlockTime The time in ticks to wait for the semaphore to become
- * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
- * real time.  A block time of zero can be used to poll the semaphore.  A block
- * time of portMAX_DELAY can be used to block indefinitely (provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
- *
- * @return pdTRUE if the semaphore was obtained.  pdFALSE
- * if xBlockTime expired without the semaphore becoming available.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xSemaphore = NULL;
- *
- *  // A task that creates a semaphore.
- *  void vATask( void * pvParameters )
- *  {
- *     // Create the semaphore to guard a shared resource.
- *     vSemaphoreCreateBinary( xSemaphore );
- *  }
- *
- *  // A task that uses the semaphore.
- *  void vAnotherTask( void * pvParameters )
- *  {
- *     // ... Do other things.
- *
- *     if( xSemaphore != NULL )
- *     {
- *         // See if we can obtain the semaphore.  If the semaphore is not available
- *         // wait 10 ticks to see if it becomes free.
- *         if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
- *         {
- *             // We were able to obtain the semaphore and can now access the
- *             // shared resource.
- *
- *             // ...
- *
- *             // We have finished accessing the shared resource.  Release the
- *             // semaphore.
- *             xSemaphoreGive( xSemaphore );
- *         }
- *         else
- *         {
- *             // We could not obtain the semaphore and can therefore not access
- *             // the shared resource safely.
- *         }
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )
-
-/**
- * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.
- * The mutex must have previously been created using a call to
- * xSemaphoreCreateRecursiveMutex();
- *
- * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
- * macro to be available.
- *
- * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * @param xMutex A handle to the mutex being obtained.  This is the
- * handle returned by xSemaphoreCreateRecursiveMutex();
- *
- * @param xBlockTime The time in ticks to wait for the semaphore to become
- * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
- * real time.  A block time of zero can be used to poll the semaphore.  If
- * the task already owns the semaphore then xSemaphoreTakeRecursive() will
- * return immediately no matter what the value of xBlockTime.
- *
- * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
- * expired without the semaphore becoming available.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xMutex = NULL;
- *
- *  // A task that creates a mutex.
- *  void vATask( void * pvParameters )
- *  {
- *     // Create the mutex to guard a shared resource.
- *     xMutex = xSemaphoreCreateRecursiveMutex();
- *  }
- *
- *  // A task that uses the mutex.
- *  void vAnotherTask( void * pvParameters )
- *  {
- *     // ... Do other things.
- *
- *     if( xMutex != NULL )
- *     {
- *         // See if we can obtain the mutex.  If the mutex is not available
- *         // wait 10 ticks to see if it becomes free.
- *         if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
- *         {
- *             // We were able to obtain the mutex and can now access the
- *             // shared resource.
- *
- *             // ...
- *             // For some reason due to the nature of the code further calls to
- * 			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
- * 			// code these would not be just sequential calls as this would make
- * 			// no sense.  Instead the calls are likely to be buried inside
- * 			// a more complex call structure.
- *             xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
- *             xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
- *
- *             // The mutex has now been 'taken' three times, so will not be
- * 			// available to another task until it has also been given back
- * 			// three times.  Again it is unlikely that real code would have
- * 			// these calls sequentially, but instead buried in a more complex
- * 			// call structure.  This is just for illustrative purposes.
- *             xSemaphoreGiveRecursive( xMutex );
- * 			xSemaphoreGiveRecursive( xMutex );
- * 			xSemaphoreGiveRecursive( xMutex );
- *
- * 			// Now the mutex can be taken by other tasks.
- *         }
- *         else
- *         {
- *             // We could not obtain the mutex and can therefore not access
- *             // the shared resource safely.
- *         }
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
-
-/** @cond */
-/*
- * xSemaphoreAltTake() is an alternative version of xSemaphoreTake().
- *
- * The source code that implements the alternative (Alt) API is much
- * simpler	because it executes everything from within a critical section.
- * This is	the approach taken by many other RTOSes, but FreeRTOS.org has the
- * preferred fully featured API too.  The fully featured API has more
- * complex	code that takes longer to execute, but makes much less use of
- * critical sections.  Therefore the alternative API sacrifices interrupt
- * responsiveness to gain execution speed, whereas the fully featured API
- * sacrifices execution speed to ensure better interrupt responsiveness.
- */
-#define xSemaphoreAltTake( xSemaphore, xBlockTime )		xQueueAltGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )
-/** @endcond */
-
-/**
- * <i>Macro</i> to release a semaphore.  The semaphore must have previously been
- * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
- * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
- *
- * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
- * an alternative which can be used from an ISR.
- *
- * This macro must also not be used on semaphores created using
- * xSemaphoreCreateRecursiveMutex().
- *
- * @param xSemaphore A handle to the semaphore being released.  This is the
- * handle returned when the semaphore was created.
- *
- * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
- * Semaphores are implemented using queues.  An error can occur if there is
- * no space on the queue to post a message - indicating that the
- * semaphore was not first obtained correctly.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xSemaphore = NULL;
- *
- *  void vATask( void * pvParameters )
- *  {
- *     // Create the semaphore to guard a shared resource.
- *     vSemaphoreCreateBinary( xSemaphore );
- *
- *     if( xSemaphore != NULL )
- *     {
- *         if( xSemaphoreGive( xSemaphore ) != pdTRUE )
- *         {
- *             // We would expect this call to fail because we cannot give
- *             // a semaphore without first "taking" it!
- *         }
- *
- *         // Obtain the semaphore - don't block if the semaphore is not
- *         // immediately available.
- *         if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
- *         {
- *             // We now have the semaphore and can access the shared resource.
- *
- *             // ...
- *
- *             // We have finished accessing the shared resource so can free the
- *             // semaphore.
- *             if( xSemaphoreGive( xSemaphore ) != pdTRUE )
- *             {
- *                 // We would not expect this call to fail because we must have
- *                 // obtained the semaphore to get here.
- *             }
- *         }
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
-
-/**
- * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.
- * The mutex must have previously been created using a call to
- * xSemaphoreCreateRecursiveMutex();
- *
- * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
- * macro to be available.
- *
- * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * @param xMutex A handle to the mutex being released, or 'given'.  This is the
- * handle returned by xSemaphoreCreateMutex();
- *
- * @return pdTRUE if the semaphore was given.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xMutex = NULL;
- *
- *  // A task that creates a mutex.
- *  void vATask( void * pvParameters )
- *  {
- *     // Create the mutex to guard a shared resource.
- *     xMutex = xSemaphoreCreateRecursiveMutex();
- *  }
- *
- *  // A task that uses the mutex.
- *  void vAnotherTask( void * pvParameters )
- *  {
- *     // ... Do other things.
- *
- *     if( xMutex != NULL )
- *     {
- *         // See if we can obtain the mutex.  If the mutex is not available
- *         // wait 10 ticks to see if it becomes free.
- *         if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
- *         {
- *             // We were able to obtain the mutex and can now access the
- *             // shared resource.
- *
- *             // ...
- *             // For some reason due to the nature of the code further calls to
- * 			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
- * 			// code these would not be just sequential calls as this would make
- * 			// no sense.  Instead the calls are likely to be buried inside
- * 			// a more complex call structure.
- *             xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
- *             xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
- *
- *             // The mutex has now been 'taken' three times, so will not be
- * 			// available to another task until it has also been given back
- * 			// three times.  Again it is unlikely that real code would have
- * 			// these calls sequentially, it would be more likely that the calls
- * 			// to xSemaphoreGiveRecursive() would be called as a call stack
- * 			// unwound.  This is just for demonstrative purposes.
- *             xSemaphoreGiveRecursive( xMutex );
- * 			xSemaphoreGiveRecursive( xMutex );
- * 			xSemaphoreGiveRecursive( xMutex );
- *
- * 			// Now the mutex can be taken by other tasks.
- *         }
- *         else
- *         {
- *             // We could not obtain the mutex and can therefore not access
- *             // the shared resource safely.
- *         }
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
-
-/** @cond */
-/*
- * xSemaphoreAltGive() is an alternative version of xSemaphoreGive().
- *
- * The source code that implements the alternative (Alt) API is much
- * simpler	because it executes everything from within a critical section.
- * This is	the approach taken by many other RTOSes, but FreeRTOS.org has the
- * preferred fully featured API too.  The fully featured API has more
- * complex	code that takes longer to execute, but makes much less use of
- * critical sections.  Therefore the alternative API sacrifices interrupt
- * responsiveness to gain execution speed, whereas the fully featured API
- * sacrifices execution speed to ensure better interrupt responsiveness.
- */
-#define xSemaphoreAltGive( xSemaphore )		xQueueAltGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
-
-/** @endcond */
-
-/**
- * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been
- * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting().
- *
- * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
- * must not be used with this macro.
- *
- * This macro can be used from an ISR.
- *
- * @param xSemaphore A handle to the semaphore being released.  This is the
- * handle returned when the semaphore was created.
- *
- * @param[out] pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
- *
- * Example usage:
- * @code{c}
- *  \#define LONG_TIME 0xffff
- *  \#define TICKS_TO_WAIT	10
- *  SemaphoreHandle_t xSemaphore = NULL;
- *
- *  // Repetitive task.
- *  void vATask( void * pvParameters )
- *  {
- *     for( ;; )
- *     {
- *         // We want this task to run every 10 ticks of a timer.  The semaphore
- *         // was created before this task was started.
- *
- *         // Block waiting for the semaphore to become available.
- *         if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
- *         {
- *             // It is time to execute.
- *
- *             // ...
- *
- *             // We have finished our task.  Return to the top of the loop where
- *             // we will block on the semaphore until it is time to execute
- *             // again.  Note when using the semaphore for synchronisation with an
- * 			// ISR in this manner there is no need to 'give' the semaphore back.
- *         }
- *     }
- *  }
- *
- *  // Timer ISR
- *  void vTimerISR( void * pvParameters )
- *  {
- *  static uint8_t ucLocalTickCount = 0;
- *  static BaseType_t xHigherPriorityTaskWoken;
- *
- *     // A timer tick has occurred.
- *
- *     // ... Do other time functions.
- *
- *     // Is it time for vATask () to run?
- * 	xHigherPriorityTaskWoken = pdFALSE;
- *     ucLocalTickCount++;
- *     if( ucLocalTickCount >= TICKS_TO_WAIT )
- *     {
- *         // Unblock the task by releasing the semaphore.
- *         xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
- *
- *         // Reset the count so we release the semaphore again in 10 ticks time.
- *         ucLocalTickCount = 0;
- *     }
- *
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // We can force a context switch here.  Context switching from an
- *         // ISR uses port specific syntax.  Check the demo task for your port
- *         // to find the syntax required.
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
-
-/**
- * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have
- * previously been created with a call to vSemaphoreCreateBinary() or
- * xSemaphoreCreateCounting().
- *
- * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
- * must not be used with this macro.
- *
- * This macro can be used from an ISR, however taking a semaphore from an ISR
- * is not a common operation.  It is likely to only be useful when taking a
- * counting semaphore when an interrupt is obtaining an object from a resource
- * pool (when the semaphore count indicates the number of resources available).
- *
- * @param xSemaphore A handle to the semaphore being taken.  This is the
- * handle returned when the semaphore was created.
- *
- * @param[out] pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the semaphore was successfully taken, otherwise
- * pdFALSE
- */
-#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
-
-/**
- * <i>Macro</i> that implements a mutex semaphore by using the existing queue
- * mechanism.
- *
- * Internally, within the FreeRTOS implementation, mutex semaphores use a block
- * of memory, in which the mutex structure is stored.  If a mutex is created
- * using xSemaphoreCreateMutex() then the required memory is automatically
- * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a mutex is created using
- * xSemaphoreCreateMutexStatic() then the application writer must provided the
- * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
- * without using any dynamic memory allocation.
- *
- * Mutexes created using this function can be accessed using the xSemaphoreTake()
- * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
- * xSemaphoreGiveRecursive() macros must not be used.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See vSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @return If the mutex was successfully created then a handle to the created
- * semaphore is returned.  If there was not enough heap to allocate the mutex
- * data structures then NULL is returned.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xSemaphore;
- *
- *  void vATask( void * pvParameters )
- *  {
- *     // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
- *     // This is a macro so pass the variable in directly.
- *     xSemaphore = xSemaphoreCreateMutex();
- *
- *     if( xSemaphore != NULL )
- *     {
- *         // The semaphore was created successfully.
- *         // The semaphore can now be used.
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
-#endif
-
-/**
- * Creates a new mutex type semaphore instance, and returns a handle by which
- * the new mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, mutex semaphores use a block
- * of memory, in which the mutex structure is stored.  If a mutex is created
- * using xSemaphoreCreateMutex() then the required memory is automatically
- * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a mutex is created using
- * xSemaphoreCreateMutexStatic() then the application writer must provided the
- * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
- * without using any dynamic memory allocation.
- *
- * Mutexes created using this function can be accessed using the xSemaphoreTake()
- * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
- * xSemaphoreGiveRecursive() macros must not be used.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
- * which will be used to hold the mutex's data structure, removing the need for
- * the memory to be allocated dynamically.
- *
- * @return If the mutex was successfully created then a handle to the created
- * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
- *
- * Example usage:
- * @code
- *  SemaphoreHandle_t xSemaphore;
- *  StaticSemaphore_t xMutexBuffer;
- *
- *  void vATask( void * pvParameters )
- *  {
- *     // A mutex cannot be used before it has been created.  xMutexBuffer is
- *     // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
- *     // attempted.
- *     xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
- *
- *     // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
- *     // so there is no need to check it.
- *  }
- * @endcode
- * \ingroup Semaphores
- */
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-
-/**
- * Creates a new recursive mutex type semaphore instance, and returns a handle
- * by which the new recursive mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
- * of memory, in which the mutex structure is stored.  If a recursive mutex is
- * created using xSemaphoreCreateRecursiveMutex() then the required memory is
- * automatically dynamically allocated inside the
- * xSemaphoreCreateRecursiveMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
- * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
- * provide the memory that will get used by the mutex.
- * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
- * be created without using any dynamic memory allocation.
- *
- * Mutexes created using this macro can be accessed using the
- * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
- * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See vSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
- *		SemaphoreHandle_t.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xSemaphore;
- *
- *  void vATask( void * pvParameters )
- *  {
- *     // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
- *     // This is a macro so pass the variable in directly.
- *     xSemaphore = xSemaphoreCreateRecursiveMutex();
- *
- *     if( xSemaphore != NULL )
- *     {
- *         // The semaphore was created successfully.
- *         // The semaphore can now be used.
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
-	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
-#endif
-
-/**
- * Creates a new recursive mutex type semaphore instance, and returns a handle
- * by which the new recursive mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
- * of memory, in which the mutex structure is stored.  If a recursive mutex is
- * created using xSemaphoreCreateRecursiveMutex() then the required memory is
- * automatically dynamically allocated inside the
- * xSemaphoreCreateRecursiveMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
- * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
- * provide the memory that will get used by the mutex.
- * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
- * be created without using any dynamic memory allocation.
- *
- * Mutexes created using this macro can be accessed using the
- * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
- * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @param pxStaticSemaphore Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the recursive mutex's data structure,
- * removing the need for the memory to be allocated dynamically.
- *
- * @return If the recursive mutex was successfully created then a handle to the
- * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
- * returned.
- *
- * Example usage:
- * @code
- *  SemaphoreHandle_t xSemaphore;
- *  StaticSemaphore_t xMutexBuffer;
- *
- *  void vATask( void * pvParameters )
- *  {
- *     // A recursive semaphore cannot be used before it is created.  Here a
- *     // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
- *     // The address of xMutexBuffer is passed into the function, and will hold
- *     // the mutexes data structures - so no dynamic memory allocation will be
- *     // attempted.
- *     xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
- *
- *     // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
- *     // so there is no need to check it.
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
-	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * Creates a new counting semaphore instance, and returns a handle by which the
- * new counting semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a counting semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, counting semaphores use a
- * block of memory, in which the counting semaphore structure is stored.  If a
- * counting semaphore is created using xSemaphoreCreateCounting() then the
- * required memory is automatically dynamically allocated inside the
- * xSemaphoreCreateCounting() function.  (see
- * http://www.freertos.org/a00111.html).  If a counting semaphore is created
- * using xSemaphoreCreateCountingStatic() then the application writer can
- * instead optionally provide the memory that will get used by the counting
- * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
- * semaphore to be created without using any dynamic memory allocation.
- *
- * Counting semaphores are typically used for two things:
- *
- * 1) Counting events.
- *
- *    In this usage scenario an event handler will 'give' a semaphore each time
- *    an event occurs (incrementing the semaphore count value), and a handler
- *    task will 'take' a semaphore each time it processes an event
- *    (decrementing the semaphore count value).  The count value is therefore
- *    the difference between the number of events that have occurred and the
- *    number that have been processed.  In this case it is desirable for the
- *    initial count value to be zero.
- *
- * 2) Resource management.
- *
- *    In this usage scenario the count value indicates the number of resources
- *    available.  To obtain control of a resource a task must first obtain a
- *    semaphore - decrementing the semaphore count value.  When the count value
- *    reaches zero there are no free resources.  When a task finishes with the
- *    resource it 'gives' the semaphore back - incrementing the semaphore count
- *    value.  In this case it is desirable for the initial count value to be
- *    equal to the maximum count value, indicating that all resources are free.
- *
- * @param uxMaxCount The maximum count value that can be reached.  When the
- *        semaphore reaches this value it can no longer be 'given'.
- *
- * @param uxInitialCount The count value assigned to the semaphore when it is
- *        created.
- *
- * @return Handle to the created semaphore.  Null if the semaphore could not be
- *         created.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xSemaphore;
- *
- *  void vATask( void * pvParameters )
- *  {
- *  SemaphoreHandle_t xSemaphore = NULL;
- *
- *     // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
- *     // The max value to which the semaphore can count should be 10, and the
- *     // initial value assigned to the count should be 0.
- *     xSemaphore = xSemaphoreCreateCounting( 10, 0 );
- *
- *     if( xSemaphore != NULL )
- *     {
- *         // The semaphore was created successfully.
- *         // The semaphore can now be used.
- *     }
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
-#endif
-
-/**
- * Creates a new counting semaphore instance, and returns a handle by which the
- * new counting semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a counting semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, counting semaphores use a
- * block of memory, in which the counting semaphore structure is stored.  If a
- * counting semaphore is created using xSemaphoreCreateCounting() then the
- * required memory is automatically dynamically allocated inside the
- * xSemaphoreCreateCounting() function.  (see
- * http://www.freertos.org/a00111.html).  If a counting semaphore is created
- * using xSemaphoreCreateCountingStatic() then the application writer must
- * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
- * counting semaphore to be created without using any dynamic memory allocation.
- *
- * Counting semaphores are typically used for two things:
- *
- * 1) Counting events.
- *
- *    In this usage scenario an event handler will 'give' a semaphore each time
- *    an event occurs (incrementing the semaphore count value), and a handler
- *    task will 'take' a semaphore each time it processes an event
- *    (decrementing the semaphore count value).  The count value is therefore
- *    the difference between the number of events that have occurred and the
- *    number that have been processed.  In this case it is desirable for the
- *    initial count value to be zero.
- *
- * 2) Resource management.
- *
- *    In this usage scenario the count value indicates the number of resources
- *    available.  To obtain control of a resource a task must first obtain a
- *    semaphore - decrementing the semaphore count value.  When the count value
- *    reaches zero there are no free resources.  When a task finishes with the
- *    resource it 'gives' the semaphore back - incrementing the semaphore count
- *    value.  In this case it is desirable for the initial count value to be
- *    equal to the maximum count value, indicating that all resources are free.
- *
- * @param uxMaxCount The maximum count value that can be reached.  When the
- *        semaphore reaches this value it can no longer be 'given'.
- *
- * @param uxInitialCount The count value assigned to the semaphore when it is
- *        created.
- *
- * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the semaphore's data structure, removing the
- * need for the memory to be allocated dynamically.
- *
- * @return If the counting semaphore was successfully created then a handle to
- * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
- * then NULL is returned.
- *
- * Example usage:
- * @code{c}
- *  SemaphoreHandle_t xSemaphore;
- *  StaticSemaphore_t xSemaphoreBuffer;
- *
- *  void vATask( void * pvParameters )
- *  {
- *  SemaphoreHandle_t xSemaphore = NULL;
- *
- *     // Counting semaphore cannot be used before they have been created.  Create
- *     // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
- *     // value to which the semaphore can count is 10, and the initial value
- *     // assigned to the count will be 0.  The address of xSemaphoreBuffer is
- *     // passed in and will be used to hold the semaphore structure, so no dynamic
- *     // memory allocation will be used.
- *     xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
- *
- *     // No memory allocation was attempted so xSemaphore cannot be NULL, so there
- *     // is no need to check its value.
- *  }
- * @endcode
- * \ingroup Semaphores
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * Delete a semaphore.  This function must be used with care.  For example,
- * do not delete a mutex type semaphore if the mutex is held by a task.
- *
- * @param xSemaphore A handle to the semaphore to be deleted.
- *
- * \ingroup Semaphores
- */
-#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
-
-/**
- * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
- * If xMutex is not a mutex type semaphore, or the mutex is available (not held
- * by a task), return NULL.
- *
- * Note: This is a good way of determining if the calling task is the mutex
- * holder, but not a good way of determining the identity of the mutex holder as
- * the holder may change between the function exiting and the returned value
- * being tested.
- */
-#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
-
-/**
- * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
- * its current count value.  If the semaphore is a binary semaphore then
- * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
- * semaphore is not available.
- *
- */
-#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
-
-#endif /* SEMAPHORE_H */
-
-
diff --git a/tools/sdk/include/freertos/freertos/task.h b/tools/sdk/include/freertos/freertos/task.h
deleted file mode 100644
index adefb3a8541..00000000000
--- a/tools/sdk/include/freertos/freertos/task.h
+++ /dev/null
@@ -1,2317 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
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-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
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-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-
-#ifndef INC_TASK_H
-#define INC_TASK_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include task.h"
-#endif
-
-#include <limits.h>
-
-#include "list.h"
-#include "portmacro.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * MACROS AND DEFINITIONS
- *----------------------------------------------------------*/
-
-#define tskKERNEL_VERSION_NUMBER "V8.2.0"
-#define tskKERNEL_VERSION_MAJOR 8
-#define tskKERNEL_VERSION_MINOR 2
-#define tskKERNEL_VERSION_BUILD 0
-
-/**
- * @brief Argument of xTaskCreatePinnedToCore indicating that task has no affinity
- */
-#define tskNO_AFFINITY INT_MAX
-
-/**
- * task. h
- *
- * Type by which tasks are referenced.  For example, a call to xTaskCreate
- * returns (via a pointer parameter) an TaskHandle_t variable that can then
- * be used as a parameter to vTaskDelete to delete the task.
- *
- * \ingroup Tasks
- */
-typedef void * TaskHandle_t;
-
-/**
- * Defines the prototype to which the application task hook function must
- * conform.
- */
-typedef BaseType_t (*TaskHookFunction_t)( void * );
-
-/** Task states returned by eTaskGetState. */
-typedef enum
-{
-	eRunning = 0,	/*!< A task is querying the state of itself, so must be running. */
-	eReady,			/*!< The task being queried is in a read or pending ready list. */
-	eBlocked,		/*!< The task being queried is in the Blocked state. */
-	eSuspended,		/*!< The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
-	eDeleted		/*!< The task being queried has been deleted, but its TCB has not yet been freed. */
-} eTaskState;
-
-/** Actions that can be performed when vTaskNotify() is called. */
-typedef enum
-{
-	eNoAction = 0,				/*!< Notify the task without updating its notify value. */
-	eSetBits,					/*!< Set bits in the task's notification value. */
-	eIncrement,					/*!< Increment the task's notification value. */
-	eSetValueWithOverwrite,		/*!< Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
-	eSetValueWithoutOverwrite	/*!< Set the task's notification value if the previous value has been read by the task. */
-} eNotifyAction;
-
-/** @cond */
-/**
- * Used internally only.
- */
-typedef struct xTIME_OUT
-{
-	BaseType_t xOverflowCount;
-	TickType_t xTimeOnEntering;
-} TimeOut_t;
-
-/**
- * Defines the memory ranges allocated to the task when an MPU is used.
- */
-typedef struct xMEMORY_REGION
-{
-	void *pvBaseAddress;
-	uint32_t ulLengthInBytes;
-	uint32_t ulParameters;
-} MemoryRegion_t;
-
-/**
- * Parameters required to create an MPU protected task.
- */
-typedef struct xTASK_PARAMETERS
-{
-	TaskFunction_t pvTaskCode;
-	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	uint32_t usStackDepth;
-	void *pvParameters;
-	UBaseType_t uxPriority;
-	StackType_t *puxStackBuffer;
-	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
-} TaskParameters_t;
-/** @endcond */
-
-/**
- *  Used with the uxTaskGetSystemState() function to return the state of each task in the system.
-*/
-typedef struct xTASK_STATUS
-{
-	TaskHandle_t xHandle;			/*!< The handle of the task to which the rest of the information in the structure relates. */
-	const char *pcTaskName;			/*!< A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	UBaseType_t xTaskNumber;		/*!< A number unique to the task. */
-	eTaskState eCurrentState;		/*!< The state in which the task existed when the structure was populated. */
-	UBaseType_t uxCurrentPriority;	/*!< The priority at which the task was running (may be inherited) when the structure was populated. */
-	UBaseType_t uxBasePriority;		/*!< The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
-	uint32_t ulRunTimeCounter;		/*!< The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
-	StackType_t *pxStackBase;		/*!< Points to the lowest address of the task's stack area. */
-	uint32_t usStackHighWaterMark;	/*!< The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
-#if configTASKLIST_INCLUDE_COREID
-	BaseType_t xCoreID;				/*!< Core this task is pinned to. This field is present if CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID is set. */
-#endif
-} TaskStatus_t;
-
-/**
- * Used with the uxTaskGetSnapshotAll() function to save memory snapshot of each task in the system.
- * We need this struct because TCB_t is defined (hidden) in tasks.c.
- */
-typedef struct xTASK_SNAPSHOT
-{
-	void        *pxTCB;         /*!< Address of task control block. */
-	StackType_t *pxTopOfStack;  /*!< Points to the location of the last item placed on the tasks stack. */
-	StackType_t *pxEndOfStack;  /*!< Points to the end of the stack. pxTopOfStack < pxEndOfStack, stack grows hi2lo
-									pxTopOfStack > pxEndOfStack, stack grows lo2hi*/
-} TaskSnapshot_t;
-
-/**
- * Possible return values for eTaskConfirmSleepModeStatus().
- */
-typedef enum
-{
-	eAbortSleep = 0,		/*!< A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
-	eStandardSleep,			/*!< Enter a sleep mode that will not last any longer than the expected idle time. */
-	eNoTasksWaitingTimeout	/*!< No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
-} eSleepModeStatus;
-
-
-/**
- * Defines the priority used by the idle task.  This must not be modified.
- *
- * \ingroup TaskUtils
- */
-#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
-
-/**
- * task. h
- *
- * Macro for forcing a context switch.
- *
- * \ingroup SchedulerControl
- */
-#define taskYIELD()					portYIELD()
-
-/**
- * task. h
- *
- * Macro to mark the start of a critical code region.  Preemptive context
- * switches cannot occur when in a critical region.
- *
- * @note This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \ingroup SchedulerControl
- */
-#ifdef _ESP_FREERTOS_INTERNAL
-#define taskENTER_CRITICAL(mux)		portENTER_CRITICAL(mux)
-#else
-#define taskENTER_CRITICAL(mux) _Pragma("GCC warning \"'taskENTER_CRITICAL(mux)' is deprecated in ESP-IDF, consider using 'portENTER_CRITICAL(mux)'\"") portENTER_CRITICAL(mux)
-#endif
-#define taskENTER_CRITICAL_ISR(mux)		portENTER_CRITICAL_ISR(mux)
-
-/**
- * task. h
- *
- * Macro to mark the end of a critical code region.  Preemptive context
- * switches cannot occur when in a critical region.
- *
- * @note This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \ingroup SchedulerControl
- */
-#ifdef _ESP_FREERTOS_INTERNAL
-#define taskEXIT_CRITICAL(mux)			portEXIT_CRITICAL(mux)
-#else
-#define taskEXIT_CRITICAL(mux) _Pragma("GCC warning \"'taskEXIT_CRITICAL(mux)' is deprecated in ESP-IDF, consider using 'portEXIT_CRITICAL(mux)'\"") portEXIT_CRITICAL(mux)
-#endif
-#define taskEXIT_CRITICAL_ISR(mux)		portEXIT_CRITICAL_ISR(mux)
-
-/**
- * task. h
- *
- * Macro to disable all maskable interrupts.
- *
- * \ingroup SchedulerControl
- */
-#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
-
-/**
- * task. h
- *
- * Macro to enable microcontroller interrupts.
- *
- * \ingroup SchedulerControl
- */
-#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
-
-/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
-0 to generate more optimal code when configASSERT() is defined as the constant
-is used in assert() statements. */
-#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
-#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
-#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
-
-
-/*-----------------------------------------------------------
- * TASK CREATION API
- *----------------------------------------------------------*/
-
-/**
- * Create a new task with a specified affinity.
- *
- * This function is similar to xTaskCreate, but allows setting task affinity
- * in SMP system.
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
- * is 16.
- *
- * @param usStackDepth The size of the task stack specified as the number of
- * bytes. Note that this differs from vanilla FreeRTOS.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task should run.  Systems that
- * include MPU support can optionally create tasks in a privileged (system)
- * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
- * example, to create a privileged task at priority 2 the uxPriority parameter
- * should be set to ( 2 | portPRIVILEGE_BIT ).
- *
- * @param pvCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @param xCoreID If the value is tskNO_AFFINITY, the created task is not
- * pinned to any CPU, and the scheduler can run it on any core available.
- * Other values indicate the index number of the CPU which the task should
- * be pinned to. Specifying values larger than (portNUM_PROCESSORS - 1) will
- * cause the function to fail.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * \ingroup Tasks
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	BaseType_t xTaskCreatePinnedToCore(	TaskFunction_t pvTaskCode,
-										const char * const pcName,
-										const uint32_t usStackDepth,
-										void * const pvParameters,
-										UBaseType_t uxPriority,
-										TaskHandle_t * const pvCreatedTask,
-										const BaseType_t xCoreID);
-
-#endif
-
-/**
- * Create a new task and add it to the list of tasks that are ready to run.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreate() then both blocks of memory are automatically dynamically
- * allocated inside the xTaskCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a task is created using
- * xTaskCreateStatic() then the application writer must provide the required
- * memory.  xTaskCreateStatic() therefore allows a task to be created without
- * using any dynamic memory allocation.
- *
- * See xTaskCreateStatic() for a version that does not use any dynamic memory
- * allocation.
- *
- * xTaskCreate() can only be used to create a task that has unrestricted
- * access to the entire microcontroller memory map.  Systems that include MPU
- * support can alternatively create an MPU constrained task using
- * xTaskCreateRestricted().
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
- * is 16.
- *
- * @param usStackDepth The size of the task stack specified as the number of
- * bytes. Note that this differs from vanilla FreeRTOS.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task should run.  Systems that
- * include MPU support can optionally create tasks in a privileged (system)
- * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
- * example, to create a privileged task at priority 2 the uxPriority parameter
- * should be set to ( 2 | portPRIVILEGE_BIT ).
- *
- * @param pvCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * @note If program uses thread local variables (ones specified with "__thread" keyword)
- * then storage for them will be allocated on the task's stack.
- *
- * Example usage:
- * @code{c}
- *  // Task to be created.
- *  void vTaskCode( void * pvParameters )
- *  {
- *   for( ;; )
- *   {
- *       // Task code goes here.
- *   }
- *  }
- *
- *  // Function that creates a task.
- *  void vOtherFunction( void )
- *  {
- *  static uint8_t ucParameterToPass;
- *  TaskHandle_t xHandle = NULL;
- *
- *   // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
- *   // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
- *   // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
- *   // the new task attempts to access it.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
- *      configASSERT( xHandle );
- *
- *   // Use the handle to delete the task.
- *      if( xHandle != NULL )
- *      {
- *       vTaskDelete( xHandle );
- *      }
- *  }
- * @endcode
- * \ingroup Tasks
- */
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	static inline IRAM_ATTR BaseType_t xTaskCreate(
-			TaskFunction_t pvTaskCode,
-			const char * const pcName,
-			const uint32_t usStackDepth,
-			void * const pvParameters,
-			UBaseType_t uxPriority,
-			TaskHandle_t * const pvCreatedTask)
-	{
-		return xTaskCreatePinnedToCore( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pvCreatedTask, tskNO_AFFINITY );
-	}
-
-#endif
-
-
-
-
-/**
- * Create a new task with a specified affinity.
- *
- * This function is similar to xTaskCreateStatic, but allows specifying
- * task affinity in an SMP system.
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  The maximum length of the string is defined by
- * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
- *
- * @param ulStackDepth The size of the task stack specified as the number of
- * bytes. Note that this differs from vanilla FreeRTOS.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task will run.
- *
- * @param pxStackBuffer Must point to a StackType_t array that has at least
- * ulStackDepth indexes - the array will then be used as the task's stack,
- * removing the need for the stack to be allocated dynamically.
- *
- * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
- * then be used to hold the task's data structures, removing the need for the
- * memory to be allocated dynamically.
- *
- * @param xCoreID If the value is tskNO_AFFINITY, the created task is not
- * pinned to any CPU, and the scheduler can run it on any core available.
- * Other values indicate the index number of the CPU which the task should
- * be pinned to. Specifying values larger than (portNUM_PROCESSORS - 1) will
- * cause the function to fail.
- *
- * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
- * be created and pdPASS is returned.  If either pxStackBuffer or pxTaskBuffer
- * are NULL then the task will not be created and
- * errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY is returned.
- *
- * \ingroup Tasks
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TaskHandle_t xTaskCreateStaticPinnedToCore(	TaskFunction_t pvTaskCode,
-												const char * const pcName,
-												const uint32_t ulStackDepth,
-												void * const pvParameters,
-												UBaseType_t uxPriority,
-												StackType_t * const pxStackBuffer,
-												StaticTask_t * const pxTaskBuffer,
-												const BaseType_t xCoreID );
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * Create a new task and add it to the list of tasks that are ready to run.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreate() then both blocks of memory are automatically dynamically
- * allocated inside the xTaskCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a task is created using
- * xTaskCreateStatic() then the application writer must provide the required
- * memory.  xTaskCreateStatic() therefore allows a task to be created without
- * using any dynamic memory allocation.
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  The maximum length of the string is defined by
- * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
- *
- * @param ulStackDepth The size of the task stack specified as the number of
- * bytes. Note that this differs from vanilla FreeRTOS.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task will run.
- *
- * @param pxStackBuffer Must point to a StackType_t array that has at least
- * ulStackDepth indexes - the array will then be used as the task's stack,
- * removing the need for the stack to be allocated dynamically.
- *
- * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
- * then be used to hold the task's data structures, removing the need for the
- * memory to be allocated dynamically.
- *
- * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
- * be created and pdPASS is returned.  If either pxStackBuffer or pxTaskBuffer
- * are NULL then the task will not be created and
- * errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY is returned.
- *
- * @note If program uses thread local variables (ones specified with "__thread" keyword)
- * then storage for them will be allocated on the task's stack.
- *
- * Example usage:
- * @code{c}
- *
- *     // Dimensions the buffer that the task being created will use as its stack.
- *     // NOTE:  This is the number of bytes the stack will hold, not the number of
- *     // words as found in vanilla FreeRTOS.
- *     #define STACK_SIZE 200
- *
- *     // Structure that will hold the TCB of the task being created.
- *     StaticTask_t xTaskBuffer;
- *
- *     // Buffer that the task being created will use as its stack.  Note this is
- *     // an array of StackType_t variables.  The size of StackType_t is dependent on
- *     // the RTOS port.
- *     StackType_t xStack[ STACK_SIZE ];
- *
- *     // Function that implements the task being created.
- *     void vTaskCode( void * pvParameters )
- *     {
- *         // The parameter value is expected to be 1 as 1 is passed in the
- *         // pvParameters value in the call to xTaskCreateStatic().
- *         configASSERT( ( uint32_t ) pvParameters == 1UL );
- *
- *         for( ;; )
- *         {
- *             // Task code goes here.
- *         }
- *     }
- *
- *     // Function that creates a task.
- *     void vOtherFunction( void )
- *     {
- *         TaskHandle_t xHandle = NULL;
- *
- *         // Create the task without using any dynamic memory allocation.
- *         xHandle = xTaskCreateStatic(
- *                       vTaskCode,       // Function that implements the task.
- *                       "NAME",          // Text name for the task.
- *                       STACK_SIZE,      // Stack size in bytes, not words.
- *                       ( void * ) 1,    // Parameter passed into the task.
- *                       tskIDLE_PRIORITY,// Priority at which the task is created.
- *                       xStack,          // Array to use as the task's stack.
- *                       &xTaskBuffer );  // Variable to hold the task's data structure.
- *
- *         // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
- *         // been created, and xHandle will be the task's handle.  Use the handle
- *         // to suspend the task.
- *         vTaskSuspend( xHandle );
- *     }
- * @endcode
- * \ingroup Tasks
- */
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	static inline IRAM_ATTR TaskHandle_t xTaskCreateStatic(
-			TaskFunction_t pvTaskCode,
-			const char * const pcName,
-			const uint32_t ulStackDepth,
-			void * const pvParameters,
-			UBaseType_t uxPriority,
-			StackType_t * const pxStackBuffer,
-			StaticTask_t * const pxTaskBuffer)
-	{
-		return xTaskCreateStaticPinnedToCore( pvTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, pxStackBuffer, pxTaskBuffer, tskNO_AFFINITY );
-	}
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/** @cond */
-/**
- * xTaskCreateRestricted() should only be used in systems that include an MPU
- * implementation.
- *
- * Create a new task and add it to the list of tasks that are ready to run.
- * The function parameters define the memory regions and associated access
- * permissions allocated to the task.
- *
- * @param pxTaskDefinition Pointer to a structure that contains a member
- * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
- * documentation) plus an optional stack buffer and the memory region
- * definitions.
- *
- * @param pxCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
- * @code{c}
- * // Create an TaskParameters_t structure that defines the task to be created.
- * static const TaskParameters_t xCheckTaskParameters =
- * {
- * 	vATask,		// pvTaskCode - the function that implements the task.
- * 	"ATask",	// pcName - just a text name for the task to assist debugging.
- * 	100,		// usStackDepth	- the stack size DEFINED IN BYTES.
- * 	NULL,		// pvParameters - passed into the task function as the function parameters.
- * 	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
- * 	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
- *
- * 	// xRegions - Allocate up to three separate memory regions for access by
- * 	// the task, with appropriate access permissions.  Different processors have
- * 	// different memory alignment requirements - refer to the FreeRTOS documentation
- * 	// for full information.
- * 	{
- * 		// Base address					Length	Parameters
- *         { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
- *         { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
- *         { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
- * 	}
- * };
- *
- * int main( void )
- * {
- * TaskHandle_t xHandle;
- *
- * 	// Create a task from the const structure defined above.  The task handle
- * 	// is requested (the second parameter is not NULL) but in this case just for
- * 	// demonstration purposes as its not actually used.
- * 	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
- *
- * 	// Start the scheduler.
- * 	vTaskStartScheduler();
- *
- * 	// Will only get here if there was insufficient memory to create the idle
- * 	// and/or timer task.
- * 	for( ;; );
- * }
- * @endcode
- * \ingroup Tasks
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-
-/**
- * Memory regions are assigned to a restricted task when the task is created by
- * a call to xTaskCreateRestricted().  These regions can be redefined using
- * vTaskAllocateMPURegions().
- *
- * @param xTask The handle of the task being updated.
- *
- * @param xRegions A pointer to an MemoryRegion_t structure that contains the
- * new memory region definitions.
- *
- * Example usage:
- *
- * @code{c}
- * // Define an array of MemoryRegion_t structures that configures an MPU region
- * // allowing read/write access for 1024 bytes starting at the beginning of the
- * // ucOneKByte array.  The other two of the maximum 3 definable regions are
- * // unused so set to zero.
- * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
- * {
- * 	// Base address		Length		Parameters
- * 	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
- * 	{ 0,				0,			0 },
- * 	{ 0,				0,			0 }
- * };
- *
- * void vATask( void *pvParameters )
- * {
- * 	// This task was created such that it has access to certain regions of
- * 	// memory as defined by the MPU configuration.  At some point it is
- * 	// desired that these MPU regions are replaced with that defined in the
- * 	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
- * 	// for this purpose.  NULL is used as the task handle to indicate that this
- * 	// function should modify the MPU regions of the calling task.
- * 	vTaskAllocateMPURegions( NULL, xAltRegions );
- *
- * 	// Now the task can continue its function, but from this point on can only
- * 	// access its stack and the ucOneKByte array (unless any other statically
- * 	// defined or shared regions have been declared elsewhere).
- * }
- * @endcode
- * \ingroup Tasks
- */
-void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
-
-/** @endcond */
-
-/**
- * Remove a task from the RTOS real time kernel's management.
- *
- * The task being deleted will be removed from all ready, blocked, suspended
- * and event lists.
- *
- * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * @note The idle task is responsible for freeing the kernel allocated
- * memory from tasks that have been deleted.  It is therefore important that
- * the idle task is not starved of microcontroller processing time if your
- * application makes any calls to vTaskDelete ().  Memory allocated by the
- * task code is not automatically freed, and should be freed before the task
- * is deleted.
- *
- * See the demo application file death.c for sample code that utilises
- * vTaskDelete ().
- *
- * @param xTaskToDelete The handle of the task to be deleted.  Passing NULL will
- * cause the calling task to be deleted.
- *
- * Example usage:
- * @code{c}
- *  void vOtherFunction( void )
- *  {
- *  TaskHandle_t xHandle;
- *
- * 	 // Create the task, storing the handle.
- * 	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- * 	 // Use the handle to delete the task.
- * 	 vTaskDelete( xHandle );
- *  }
- * @endcode
- * \ingroup Tasks
- */
-void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
- * TASK CONTROL API
- *----------------------------------------------------------*/
-
-/**
- * Delay a task for a given number of ticks.
- *
- * The actual time that the task remains blocked depends on the tick rate.
- * The constant portTICK_PERIOD_MS can be used to calculate real time from
- * the tick rate - with the resolution of one tick period.
- *
- * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * vTaskDelay() specifies a time at which the task wishes to unblock relative to
- * the time at which vTaskDelay() is called.  For example, specifying a block
- * period of 100 ticks will cause the task to unblock 100 ticks after
- * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
- * of controlling the frequency of a periodic task as the path taken through the
- * code, as well as other task and interrupt activity, will effect the frequency
- * at which vTaskDelay() gets called and therefore the time at which the task
- * next executes.  See vTaskDelayUntil() for an alternative API function designed
- * to facilitate fixed frequency execution.  It does this by specifying an
- * absolute time (rather than a relative time) at which the calling task should
- * unblock.
- *
- * @param xTicksToDelay The amount of time, in tick periods, that
- * the calling task should block.
- *
- * Example usage:
- * @code{c}
- *  void vTaskFunction( void * pvParameters )
- *  {
- *  // Block for 500ms.
- *  const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
- *
- * 	 for( ;; )
- * 	 {
- * 		 // Simply toggle the LED every 500ms, blocking between each toggle.
- * 		 vToggleLED();
- * 		 vTaskDelay( xDelay );
- * 	 }
- *  }
- * @endcode
- * \ingroup TaskCtrl
- */
-void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
-
-/**
- * Delay a task until a specified time.
- *
- * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * This function can be used by periodic tasks to ensure a constant execution frequency.
- *
- * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
- * cause a task to block for the specified number of ticks from the time vTaskDelay () is
- * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
- * execution frequency as the time between a task starting to execute and that task
- * calling vTaskDelay () may not be fixed [the task may take a different path though the
- * code between calls, or may get interrupted or preempted a different number of times
- * each time it executes].
- *
- * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
- * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
- * unblock.
- *
- * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
- * rate - with the resolution of one tick period.
- *
- * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
- * task was last unblocked.  The variable must be initialised with the current time
- * prior to its first use (see the example below).  Following this the variable is
- * automatically updated within vTaskDelayUntil ().
- *
- * @param xTimeIncrement The cycle time period.  The task will be unblocked at
- * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
- * same xTimeIncrement parameter value will cause the task to execute with
- * a fixed interface period.
- *
- * Example usage:
- * @code{c}
- *  // Perform an action every 10 ticks.
- *  void vTaskFunction( void * pvParameters )
- *  {
- *  TickType_t xLastWakeTime;
- *  const TickType_t xFrequency = 10;
- *
- * 	 // Initialise the xLastWakeTime variable with the current time.
- * 	 xLastWakeTime = xTaskGetTickCount ();
- * 	 for( ;; )
- * 	 {
- * 		 // Wait for the next cycle.
- * 		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
- *
- * 		 // Perform action here.
- * 	 }
- *  }
- * @endcode
- * \ingroup TaskCtrl
- */
-void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
-
-/**
- * Obtain the priority of any task.
- *
- * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * @param xTask Handle of the task to be queried.  Passing a NULL
- * handle results in the priority of the calling task being returned.
- *
- * @return The priority of xTask.
- *
- * Example usage:
- * @code{c}
- *  void vAFunction( void )
- *  {
- *  TaskHandle_t xHandle;
- *
- *   // Create a task, storing the handle.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- *   // ...
- *
- *   // Use the handle to obtain the priority of the created task.
- *   // It was created with tskIDLE_PRIORITY, but may have changed
- *   // it itself.
- *   if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
- *   {
- *       // The task has changed it's priority.
- *   }
- *
- *   // ...
- *
- *   // Is our priority higher than the created task?
- *   if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
- *   {
- *       // Our priority (obtained using NULL handle) is higher.
- *   }
- * }
- * @endcode
- * \ingroup TaskCtrl
- */
-UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * A version of uxTaskPriorityGet() that can be used from an ISR.
- *
- * @param xTask Handle of the task to be queried.  Passing a NULL
- * handle results in the priority of the calling task being returned.
- *
- * @return The priority of xTask.
- *
- */
-UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * Obtain the state of any task.
- *
- * States are encoded by the eTaskState enumerated type.
- *
- * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * @param xTask Handle of the task to be queried.
- *
- * @return The state of xTask at the time the function was called.  Note the
- * state of the task might change between the function being called, and the
- * functions return value being tested by the calling task.
- */
-eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * Set the priority of any task.
- *
- * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * A context switch will occur before the function returns if the priority
- * being set is higher than the currently executing task.
- *
- * @param xTask Handle to the task for which the priority is being set.
- * Passing a NULL handle results in the priority of the calling task being set.
- *
- * @param uxNewPriority The priority to which the task will be set.
- *
- * Example usage:
- * @code{c}
- *  void vAFunction( void )
- *  {
- *  TaskHandle_t xHandle;
- *
- *   // Create a task, storing the handle.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- *   // ...
- *
- *   // Use the handle to raise the priority of the created task.
- *   vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
- *
- *   // ...
- *
- *   // Use a NULL handle to raise our priority to the same value.
- *   vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- *  }
- * @endcode
- * \ingroup TaskCtrl
- */
-void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
-
-/**
- * Suspend a task.
- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * When suspended, a task will never get any microcontroller processing time,
- * no matter what its priority.
- *
- * Calls to vTaskSuspend are not accumulative -
- * i.e. calling vTaskSuspend () twice on the same task still only requires one
- * call to vTaskResume () to ready the suspended task.
- *
- * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
- * handle will cause the calling task to be suspended.
- *
- * Example usage:
- * @code{c}
- *  void vAFunction( void )
- *  {
- *  TaskHandle_t xHandle;
- *
- *   // Create a task, storing the handle.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- *   // ...
- *
- *   // Use the handle to suspend the created task.
- *   vTaskSuspend( xHandle );
- *
- *   // ...
- *
- *   // The created task will not run during this period, unless
- *   // another task calls vTaskResume( xHandle ).
- *
- *   //...
- *
- *
- *   // Suspend ourselves.
- *   vTaskSuspend( NULL );
- *
- *   // We cannot get here unless another task calls vTaskResume
- *   // with our handle as the parameter.
- *  }
- * @endcode
- * \ingroup TaskCtrl
- */
-void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
-
-/**
- * Resumes a suspended task.
- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * A task that has been suspended by one or more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * vTaskResume ().
- *
- * @param xTaskToResume Handle to the task being readied.
- *
- * Example usage:
- * @code{c}
- *  void vAFunction( void )
- *  {
- *  TaskHandle_t xHandle;
- *
- *   // Create a task, storing the handle.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
- *
- *   // ...
- *
- *   // Use the handle to suspend the created task.
- *   vTaskSuspend( xHandle );
- *
- *   // ...
- *
- *   // The created task will not run during this period, unless
- *   // another task calls vTaskResume( xHandle ).
- *
- *   //...
- *
- *
- *   // Resume the suspended task ourselves.
- *   vTaskResume( xHandle );
- *
- *   // The created task will once again get microcontroller processing
- *   // time in accordance with its priority within the system.
- *  }
- * @endcode
- * \ingroup TaskCtrl
- */
-void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
-
-/**
- * An implementation of vTaskResume() that can be called from within an ISR.
- *
- * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
- * available.  See the configuration section for more information.
- *
- * A task that has been suspended by one or more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * xTaskResumeFromISR ().
- *
- * xTaskResumeFromISR() should not be used to synchronise a task with an
- * interrupt if there is a chance that the interrupt could arrive prior to the
- * task being suspended - as this can lead to interrupts being missed. Use of a
- * semaphore as a synchronisation mechanism would avoid this eventuality.
- *
- * @param xTaskToResume Handle to the task being readied.
- *
- * @return pdTRUE if resuming the task should result in a context switch,
- * otherwise pdFALSE. This is used by the ISR to determine if a context switch
- * may be required following the ISR.
- *
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
- * SCHEDULER CONTROL
- *----------------------------------------------------------*/
-/** @cond */
-/**
- * Starts the real time kernel tick processing.
- *
- * After calling the kernel has control over which tasks are executed and when.
- *
- * See the demo application file main.c for an example of creating
- * tasks and starting the kernel.
- *
- * Example usage:
- * @code{c}
- *  void vAFunction( void )
- *  {
- *   // Create at least one task before starting the kernel.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- *
- *   // Start the real time kernel with preemption.
- *   vTaskStartScheduler ();
- *
- *   // Will not get here unless a task calls vTaskEndScheduler ()
- *  }
- * @endcode
- *
- * \ingroup SchedulerControl
- */
-void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * Stops the real time kernel tick.
- *
- * @note At the time of writing only the x86 real mode port, which runs on a PC
- * in place of DOS, implements this function.
- *
- * All created tasks will be automatically deleted and multitasking
- * (either preemptive or cooperative) will stop.
- * Execution then resumes from the point where vTaskStartScheduler ()
- * was called, as if vTaskStartScheduler () had just returned.
- *
- * See the demo application file main. c in the demo/PC directory for an
- * example that uses vTaskEndScheduler ().
- *
- * vTaskEndScheduler () requires an exit function to be defined within the
- * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
- * performs hardware specific operations such as stopping the kernel tick.
- *
- * vTaskEndScheduler () will cause all of the resources allocated by the
- * kernel to be freed - but will not free resources allocated by application
- * tasks.
- *
- * Example usage:
- * @code{c}
- *  void vTaskCode( void * pvParameters )
- *  {
- *   for( ;; )
- *   {
- *       // Task code goes here.
- *
- *       // At some point we want to end the real time kernel processing
- *       // so call ...
- *       vTaskEndScheduler ();
- *   }
- *  }
- *
- *  void vAFunction( void )
- *  {
- *   // Create at least one task before starting the kernel.
- *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
- *
- *   // Start the real time kernel with preemption.
- *   vTaskStartScheduler ();
- *
- *   // Will only get here when the vTaskCode () task has called
- *   // vTaskEndScheduler ().  When we get here we are back to single task
- *   // execution.
- *  }
- * @endcode
- * \ingroup SchedulerControl
- */
-void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
-
-/** @endcond */
-
-/**
- * Suspends the scheduler without disabling interrupts.
- *
- * Context switches will not occur while the scheduler is suspended.
- *
- * After calling vTaskSuspendAll () the calling task will continue to execute
- * without risk of being swapped out until a call to xTaskResumeAll () has been
- * made.
- *
- * API functions that have the potential to cause a context switch (for example,
- * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
- * is suspended.
- *
- * Example usage:
- * @code{c}
- *  void vTask1( void * pvParameters )
- *  {
- *   for( ;; )
- *   {
- *       // Task code goes here.
- *
- *       // ...
- *
- *       // At some point the task wants to perform a long operation during
- *       // which it does not want to get swapped out.  It cannot use
- *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
- *       // operation may cause interrupts to be missed - including the
- *       // ticks.
- *
- *       // Prevent the real time kernel swapping out the task.
- *       vTaskSuspendAll ();
- *
- *       // Perform the operation here.  There is no need to use critical
- *       // sections as we have all the microcontroller processing time.
- *       // During this time interrupts will still operate and the kernel
- *       // tick count will be maintained.
- *
- *       // ...
- *
- *       // The operation is complete.  Restart the kernel.
- *       xTaskResumeAll ();
- *   }
- *  }
- * @endcode
- * \ingroup SchedulerControl
- */
-void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
-
-/**
- * Resumes scheduler activity after it was suspended by a call to
- * vTaskSuspendAll().
- *
- * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
- * that were previously suspended by a call to vTaskSuspend().
- *
- * @return If resuming the scheduler caused a context switch then pdTRUE is
- *		  returned, otherwise pdFALSE is returned.
- *
- * Example usage:
- * @code{c}
- *  void vTask1( void * pvParameters )
- *  {
- *   for( ;; )
- *   {
- *       // Task code goes here.
- *
- *       // ...
- *
- *       // At some point the task wants to perform a long operation during
- *       // which it does not want to get swapped out.  It cannot use
- *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
- *       // operation may cause interrupts to be missed - including the
- *       // ticks.
- *
- *       // Prevent the real time kernel swapping out the task.
- *       vTaskSuspendAll ();
- *
- *       // Perform the operation here.  There is no need to use critical
- *       // sections as we have all the microcontroller processing time.
- *       // During this time interrupts will still operate and the real
- *       // time kernel tick count will be maintained.
- *
- *       // ...
- *
- *       // The operation is complete.  Restart the kernel.  We want to force
- *       // a context switch - but there is no point if resuming the scheduler
- *       // caused a context switch already.
- *       if( !xTaskResumeAll () )
- *       {
- *            taskYIELD ();
- *       }
- *   }
- *  }
- * @endcode
- * \ingroup SchedulerControl
- */
-BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
- * TASK UTILITIES
- *----------------------------------------------------------*/
-
-/**
- * Get tick count
- *
- * @return The count of ticks since vTaskStartScheduler was called.
- *
- * \ingroup TaskUtils
- */
-TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
-
-/**
- * Get tick count from ISR
- *
- * @return The count of ticks since vTaskStartScheduler was called.
- *
- * This is a version of xTaskGetTickCount() that is safe to be called from an
- * ISR - provided that TickType_t is the natural word size of the
- * microcontroller being used or interrupt nesting is either not supported or
- * not being used.
- *
- * \ingroup TaskUtils
- */
-TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
-
-/**
- * Get current number of tasks
- *
- * @return The number of tasks that the real time kernel is currently managing.
- * This includes all ready, blocked and suspended tasks.  A task that
- * has been deleted but not yet freed by the idle task will also be
- * included in the count.
- *
- * \ingroup TaskUtils
- */
-UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
-
-/**
- * Get task name
- *
- * @return The text (human readable) name of the task referenced by the handle
- * xTaskToQuery.  A task can query its own name by either passing in its own
- * handle, or by setting xTaskToQuery to NULL.  INCLUDE_pcTaskGetTaskName must be
- * set to 1 in FreeRTOSConfig.h for pcTaskGetTaskName() to be available.
- *
- * \ingroup TaskUtils
- */
-char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * Returns the high water mark of the stack associated with xTask.
- *
- * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * High water mark is the minimum free stack space there has been (in bytes
- * rather than words as found in vanilla FreeRTOS) since the task started.
- * The smaller the returned number the closer the task has come to overflowing its stack.
- *
- * @param xTask Handle of the task associated with the stack to be checked.
- * Set xTask to NULL to check the stack of the calling task.
- *
- * @return The smallest amount of free stack space there has been (in bytes
- * rather than words as found in vanilla FreeRTOS) since the task referenced by
- * xTask was created.
- */
-UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * Returns the start of the stack associated with xTask.
- *
- * INCLUDE_pxTaskGetStackStart must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * Returns the highest stack memory address on architectures where the stack grows down
- * from high memory, and the lowest memory address on architectures where the
- * stack grows up from low memory.
- *
- * @param xTask Handle of the task associated with the stack returned.
- * Set xTask to NULL to return the stack of the calling task.
- *
- * @return A pointer to the start of the stack.
- */
-uint8_t* pxTaskGetStackStart( TaskHandle_t xTask) PRIVILEGED_FUNCTION;
-
-/* When using trace macros it is sometimes necessary to include task.h before
-FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
-so the following two prototypes will cause a compilation error.  This can be
-fixed by simply guarding against the inclusion of these two prototypes unless
-they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
-constant. */
-#ifdef configUSE_APPLICATION_TASK_TAG
-	#if configUSE_APPLICATION_TASK_TAG == 1
-		/**
-		 * Sets pxHookFunction to be the task hook function used by the task xTask.
-		 * @param xTask Handle of the task to set the hook function for
-		 *              Passing xTask as NULL has the effect of setting the calling
-		 *              tasks hook function.
-		 * @param pxHookFunction  Pointer to the hook function.
-		 */
-		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
-
-		/**
-		 * Get the hook function assigned to given task.
-		 * @param xTask Handle of the task to get the hook function for
-		 *              Passing xTask as NULL has the effect of getting the calling
-		 *              tasks hook function.
-		 * @return The pxHookFunction value assigned to the task xTask.
-		 */
-		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
-#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
-#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-
-	/**
-	 * Set local storage pointer specific to the given task.
-	 *
-	 * Each task contains an array of pointers that is dimensioned by the
-	 * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.
-	 * The kernel does not use the pointers itself, so the application writer
-	 * can use the pointers for any purpose they wish.
-	 *
-	 * @param xTaskToSet  Task to set thread local storage pointer for
-	 * @param xIndex The index of the pointer to set, from 0 to
-	 *               configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1.
-	 * @param pvValue  Pointer value to set.
-	 */
-	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
-
-
-	/**
-	 * Get local storage pointer specific to the given task.
-	 *
-	 * Each task contains an array of pointers that is dimensioned by the
-	 * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.
-	 * The kernel does not use the pointers itself, so the application writer
-	 * can use the pointers for any purpose they wish.
-	 *
-	 * @param xTaskToQuery  Task to get thread local storage pointer for
-	 * @param xIndex The index of the pointer to get, from 0 to
-	 *               configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1.
-	 * @return  Pointer value
-	 */
-	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
-
-	#if ( configTHREAD_LOCAL_STORAGE_DELETE_CALLBACKS )
-
-		/**
-		 * Prototype of local storage pointer deletion callback.
-		 */
-		typedef void (*TlsDeleteCallbackFunction_t)( int, void * );
-
-		/**
-		 * Set local storage pointer and deletion callback.
-		 *
-		 * Each task contains an array of pointers that is dimensioned by the
-		 * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.
-		 * The kernel does not use the pointers itself, so the application writer
-		 * can use the pointers for any purpose they wish.
-		 *
-		 * Local storage pointers set for a task can reference dynamically
-		 * allocated resources. This function is similar to
-		 * vTaskSetThreadLocalStoragePointer, but provides a way to release
-		 * these resources when the task gets deleted. For each pointer,
-		 * a callback function can be set. This function will be called
-		 * when task is deleted, with the local storage pointer index
-		 * and value as arguments.
-		 *
-		 * @param xTaskToSet  Task to set thread local storage pointer for
-		 * @param xIndex The index of the pointer to set, from 0 to
-		 *               configNUM_THREAD_LOCAL_STORAGE_POINTERS - 1.
-		 * @param pvValue  Pointer value to set.
-		 * @param pvDelCallback  Function to call to dispose of the local
-		 *                       storage pointer when the task is deleted.
-		 */
-		void vTaskSetThreadLocalStoragePointerAndDelCallback( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue, TlsDeleteCallbackFunction_t pvDelCallback);
-	#endif
-
-#endif
-
-/**
- * Calls the hook function associated with xTask. Passing xTask as NULL has
- * the effect of calling the Running tasks (the calling task) hook function.
- *
- * @param xTask  Handle of the task to call the hook for.
- * @param pvParameter  Parameter passed to the hook function for the task to interpret as it
- * wants.  The return value is the value returned by the task hook function
- * registered by the user.
- */
-BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
-
-/**
- * Get the handle of idle task for the current CPU.
- *
- * xTaskGetIdleTaskHandle() is only available if
- * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
- *
- * @return The handle of the idle task.  It is not valid to call
- * xTaskGetIdleTaskHandle() before the scheduler has been started.
- */
-TaskHandle_t xTaskGetIdleTaskHandle( void );
-
-/**
- * Get the handle of idle task for the given CPU.
- *
- * xTaskGetIdleTaskHandleForCPU() is only available if
- * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
- *
- * @param cpuid The CPU to get the handle for
- *
- * @return Idle task handle of a given cpu. It is not valid to call
- * xTaskGetIdleTaskHandleForCPU() before the scheduler has been started.
- */
-TaskHandle_t xTaskGetIdleTaskHandleForCPU( UBaseType_t cpuid );
-
-/**
- * Get the state of tasks in the system.
- *
- * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
- * uxTaskGetSystemState() to be available.
- *
- * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
- * the system.  TaskStatus_t structures contain, among other things, members
- * for the task handle, task name, task priority, task state, and total amount
- * of run time consumed by the task.  See the TaskStatus_t structure
- * definition in this file for the full member list.
- *
- * @note  This function is intended for debugging use only as its use results in
- * the scheduler remaining suspended for an extended period.
- *
- * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
- * The array must contain at least one TaskStatus_t structure for each task
- * that is under the control of the RTOS.  The number of tasks under the control
- * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
- *
- * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
- * parameter.  The size is specified as the number of indexes in the array, or
- * the number of TaskStatus_t structures contained in the array, not by the
- * number of bytes in the array.
- *
- * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
- * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
- * total run time (as defined by the run time stats clock, see
- * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
- * pulTotalRunTime can be set to NULL to omit the total run time information.
- *
- * @return The number of TaskStatus_t structures that were populated by
- * uxTaskGetSystemState().  This should equal the number returned by the
- * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
- * in the uxArraySize parameter was too small.
- *
- * Example usage:
- * @code{c}
- * // This example demonstrates how a human readable table of run time stats
- * // information is generated from raw data provided by uxTaskGetSystemState().
- * // The human readable table is written to pcWriteBuffer
- * void vTaskGetRunTimeStats( char *pcWriteBuffer )
- * {
- * TaskStatus_t *pxTaskStatusArray;
- * volatile UBaseType_t uxArraySize, x;
- * uint32_t ulTotalRunTime, ulStatsAsPercentage;
- *
- *  // Make sure the write buffer does not contain a string.
- *  *pcWriteBuffer = 0x00;
- *
- *  // Take a snapshot of the number of tasks in case it changes while this
- *  // function is executing.
- *  uxArraySize = uxTaskGetNumberOfTasks();
- *
- *  // Allocate a TaskStatus_t structure for each task.  An array could be
- *  // allocated statically at compile time.
- *  pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
- *
- *  if( pxTaskStatusArray != NULL )
- *  {
- *      // Generate raw status information about each task.
- *      uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
- *
- *      // For percentage calculations.
- *      ulTotalRunTime /= 100UL;
- *
- *      // Avoid divide by zero errors.
- *      if( ulTotalRunTime > 0 )
- *      {
- *          // For each populated position in the pxTaskStatusArray array,
- *          // format the raw data as human readable ASCII data
- *          for( x = 0; x < uxArraySize; x++ )
- *          {
- *              // What percentage of the total run time has the task used?
- *              // This will always be rounded down to the nearest integer.
- *              // ulTotalRunTimeDiv100 has already been divided by 100.
- *              ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
- *
- *              if( ulStatsAsPercentage > 0UL )
- *              {
- *                  sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
- *              }
- *              else
- *              {
- *                  // If the percentage is zero here then the task has
- *                  // consumed less than 1% of the total run time.
- *                  sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
- *              }
- *
- *              pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
- *          }
- *      }
- *
- *      // The array is no longer needed, free the memory it consumes.
- *      vPortFree( pxTaskStatusArray );
- *  }
- * }
- * @endcode
- */
-UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );
-
-/**
- * List all the current tasks.
- *
- * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
- * both be defined as 1 for this function to be available.  See the
- * configuration section of the FreeRTOS.org website for more information.
- *
- * @note This function will disable interrupts for its duration.  It is
- * not intended for normal application runtime use but as a debug aid.
- *
- * Lists all the current tasks, along with their current state and stack
- * usage high water mark.
- *
- * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
- * suspended ('S').
- *
- * @note This function is provided for convenience only, and is used by many of the
- * demo applications.  Do not consider it to be part of the scheduler.
- *
- * vTaskList() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays task
- * names, states and stack usage.
- *
- * vTaskList() has a dependency on the sprintf() C library function that might
- * bloat the code size, use a lot of stack, and provide different results on
- * different platforms.  An alternative, tiny, third party, and limited
- * functionality implementation of sprintf() is provided in many of the
- * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
- * printf-stdarg.c does not provide a full snprintf() implementation!).
- *
- * It is recommended that production systems call uxTaskGetSystemState()
- * directly to get access to raw stats data, rather than indirectly through a
- * call to vTaskList().
- *
- * @param pcWriteBuffer A buffer into which the above mentioned details
- * will be written, in ASCII form.  This buffer is assumed to be large
- * enough to contain the generated report.  Approximately 40 bytes per
- * task should be sufficient.
- *
- * \ingroup TaskUtils
- */
-void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * Get the state of running tasks as a string
- *
- * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
- * must both be defined as 1 for this function to be available.  The application
- * must also then provide definitions for
- * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
- * to configure a peripheral timer/counter and return the timers current count
- * value respectively.  The counter should be at least 10 times the frequency of
- * the tick count.
- *
- * @note This function will disable interrupts for its duration.  It is
- * not intended for normal application runtime use but as a debug aid.
- *
- * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
- * accumulated execution time being stored for each task.  The resolution
- * of the accumulated time value depends on the frequency of the timer
- * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
- * Calling vTaskGetRunTimeStats() writes the total execution time of each
- * task into a buffer, both as an absolute count value and as a percentage
- * of the total system execution time.
- *
- * @note This function is provided for convenience only, and is used by many of the
- * demo applications.  Do not consider it to be part of the scheduler.
- *
- * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays the
- * amount of time each task has spent in the Running state in both absolute and
- * percentage terms.
- *
- * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
- * that might bloat the code size, use a lot of stack, and provide different
- * results on different platforms.  An alternative, tiny, third party, and
- * limited functionality implementation of sprintf() is provided in many of the
- * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
- * printf-stdarg.c does not provide a full snprintf() implementation!).
- *
- * It is recommended that production systems call uxTaskGetSystemState() directly
- * to get access to raw stats data, rather than indirectly through a call to
- * vTaskGetRunTimeStats().
- *
- * @param pcWriteBuffer A buffer into which the execution times will be
- * written, in ASCII form.  This buffer is assumed to be large enough to
- * contain the generated report.  Approximately 40 bytes per task should
- * be sufficient.
- *
- * \ingroup TaskUtils
- */
-void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * Send task notification.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
- * already in the Blocked state to wait for a notification when the notification
- * arrives then the task will automatically be removed from the Blocked state
- * (unblocked) and the notification cleared.
- *
- * A task can use xTaskNotifyWait() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTake() to [optionally] block
- * to wait for its notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param ulValue Data that can be sent with the notification.  How the data is
- * used depends on the value of the eAction parameter.
- *
- * @param eAction Specifies how the notification updates the task's notification
- * value, if at all.  Valid values for eAction are as follows:
- *	- eSetBits:
- *	  The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
- * 	  always returns pdPASS in this case.
- *
- *	- eIncrement:
- *	  The task's notification value is incremented.  ulValue is not used and
- *	  xTaskNotify() always returns pdPASS in this case.
- *
- *	- eSetValueWithOverwrite:
- *	  The task's notification value is set to the value of ulValue, even if the
- *	  task being notified had not yet processed the previous notification (the
- *	  task already had a notification pending).  xTaskNotify() always returns
- *	  pdPASS in this case.
- *
- *	- eSetValueWithoutOverwrite:
- *	  If the task being notified did not already have a notification pending then
- *	  the task's notification value is set to ulValue and xTaskNotify() will
- *	  return pdPASS.  If the task being notified already had a notification
- *	  pending then no action is performed and pdFAIL is returned.
- *
- *	- eNoAction:
- *	  The task receives a notification without its notification value being
- *	  updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
- *	  this case.
- *
- * @return Dependent on the value of eAction.  See the description of the
- * eAction parameter.
- *
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
-
-/**
- * Send task notification from an ISR.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * A version of xTaskNotify() that can be used from an interrupt service routine
- * (ISR).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
- * already in the Blocked state to wait for a notification when the notification
- * arrives then the task will automatically be removed from the Blocked state
- * (unblocked) and the notification cleared.
- *
- * A task can use xTaskNotifyWait() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTake() to [optionally] block
- * to wait for its notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param ulValue Data that can be sent with the notification.  How the data is
- * used depends on the value of the eAction parameter.
- *
- * @param eAction Specifies how the notification updates the task's notification
- * value, if at all.  Valid values for eAction are as follows:
- *	- eSetBits:
- *	  The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
- * 	  always returns pdPASS in this case.
- *
- *	- eIncrement:
- *	  The task's notification value is incremented.  ulValue is not used and
- *	  xTaskNotify() always returns pdPASS in this case.
- *
- *	- eSetValueWithOverwrite:
- *	  The task's notification value is set to the value of ulValue, even if the
- *	  task being notified had not yet processed the previous notification (the
- *	  task already had a notification pending).  xTaskNotify() always returns
- *	  pdPASS in this case.
- *
- *	- eSetValueWithoutOverwrite:
- *	  If the task being notified did not already have a notification pending then
- *	  the task's notification value is set to ulValue and xTaskNotify() will
- *	  return pdPASS.  If the task being notified already had a notification
- *	  pending then no action is performed and pdFAIL is returned.
- *
- *	- eNoAction:
- *	  The task receives a notification without its notification value being
- *	  updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
- *	  this case.
- *
- * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
- * task to which the notification was sent to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently running task.  If
- * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
- * be requested before the interrupt is exited.  How a context switch is
- * requested from an ISR is dependent on the port - see the documentation page
- * for the port in use.
- *
- * @return Dependent on the value of eAction.  See the description of the
- * eAction parameter.
- *
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
-
-/**
- * Wait for task notification
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
- * already in the Blocked state to wait for a notification when the notification
- * arrives then the task will automatically be removed from the Blocked state
- * (unblocked) and the notification cleared.
- *
- * A task can use xTaskNotifyWait() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTake() to [optionally] block
- * to wait for its notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
- * will be cleared in the calling task's notification value before the task
- * checks to see if any notifications are pending, and optionally blocks if no
- * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
- * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
- * the effect of resetting the task's notification value to 0.  Setting
- * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
- *
- * @param ulBitsToClearOnExit If a notification is pending or received before
- * the calling task exits the xTaskNotifyWait() function then the task's
- * notification value (see the xTaskNotify() API function) is passed out using
- * the pulNotificationValue parameter.  Then any bits that are set in
- * ulBitsToClearOnExit will be cleared in the task's notification value (note
- * *pulNotificationValue is set before any bits are cleared).  Setting
- * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
- * (if limits.h is not included) will have the effect of resetting the task's
- * notification value to 0 before the function exits.  Setting
- * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
- * when the function exits (in which case the value passed out in
- * pulNotificationValue will match the task's notification value).
- *
- * @param pulNotificationValue Used to pass the task's notification value out
- * of the function.  Note the value passed out will not be effected by the
- * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait in
- * the Blocked state for a notification to be received, should a notification
- * not already be pending when xTaskNotifyWait() was called.  The task
- * will not consume any processing time while it is in the Blocked state.  This
- * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
- * used to convert a time specified in milliseconds to a time specified in
- * ticks.
- *
- * @return If a notification was received (including notifications that were
- * already pending when xTaskNotifyWait was called) then pdPASS is
- * returned.  Otherwise pdFAIL is returned.
- *
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
-
-/**
- * Simplified macro for sending task notification.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
- * to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * xTaskNotifyGive() is a helper macro intended for use when task notifications
- * are used as light weight and faster binary or counting semaphore equivalents.
- * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
- * the equivalent action that instead uses a task notification is
- * xTaskNotifyGive().
- *
- * When task notifications are being used as a binary or counting semaphore
- * equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTake() API function rather than the
- * xTaskNotifyWait() API function.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
- * eAction parameter set to eIncrement - so pdPASS is always returned.
- *
- * \ingroup TaskNotifications
- */
-#define xTaskNotifyGive( xTaskToNotify ) xTaskNotify( ( xTaskToNotify ), 0, eIncrement )
-
-/**
- * Simplified macro for sending task notification from ISR.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
- * to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * A version of xTaskNotifyGive() that can be called from an interrupt service
- * routine (ISR).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * vTaskNotifyGiveFromISR() is intended for use when task notifications are
- * used as light weight and faster binary or counting semaphore equivalents.
- * Actual FreeRTOS semaphores are given from an ISR using the
- * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
- * a task notification is vTaskNotifyGiveFromISR().
- *
- * When task notifications are being used as a binary or counting semaphore
- * equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTake() API function rather than the
- * xTaskNotifyWait() API function.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
- * task to which the notification was sent to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently running task.  If
- * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
- * should be requested before the interrupt is exited.  How a context switch is
- * requested from an ISR is dependent on the port - see the documentation page
- * for the port in use.
- *
- * \ingroup TaskNotifications
- */
-void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken );
-
-/**
- * Simplified macro for receiving task notification.
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * ulTaskNotifyTake() is intended for use when a task notification is used as a
- * faster and lighter weight binary or counting semaphore alternative.  Actual
- * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
- * equivalent action that instead uses a task notification is
- * ulTaskNotifyTake().
- *
- * When a task is using its notification value as a binary or counting semaphore
- * other tasks should send notifications to it using the xTaskNotifyGive()
- * macro, or xTaskNotify() function with the eAction parameter set to
- * eIncrement.
- *
- * ulTaskNotifyTake() can either clear the task's notification value to
- * zero on exit, in which case the notification value acts like a binary
- * semaphore, or decrement the task's notification value on exit, in which case
- * the notification value acts like a counting semaphore.
- *
- * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
- * the task's notification value to be non-zero.  The task does not consume any
- * CPU time while it is in the Blocked state.
- *
- * Where as xTaskNotifyWait() will return when a notification is pending,
- * ulTaskNotifyTake() will return when the task's notification value is
- * not zero.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
- * notification value is decremented when the function exits.  In this way the
- * notification value acts like a counting semaphore.  If xClearCountOnExit is
- * not pdFALSE then the task's notification value is cleared to zero when the
- * function exits.  In this way the notification value acts like a binary
- * semaphore.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait in
- * the Blocked state for the task's notification value to be greater than zero,
- * should the count not already be greater than zero when
- * ulTaskNotifyTake() was called.  The task will not consume any processing
- * time while it is in the Blocked state.  This is specified in kernel ticks,
- * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
- * specified in milliseconds to a time specified in ticks.
- *
- * @return The task's notification count before it is either cleared to zero or
- * decremented (see the xClearCountOnExit parameter).
- *
- * \ingroup TaskNotifications
- */
-uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
-
-/*-----------------------------------------------------------
- * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
- *----------------------------------------------------------*/
-/** @cond */
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Called from the real time kernel tick (either preemptive or cooperative),
- * this increments the tick count and checks if any tasks that are blocked
- * for a finite period required removing from a blocked list and placing on
- * a ready list.  If a non-zero value is returned then a context switch is
- * required because either:
- *   + A task was removed from a blocked list because its timeout had expired,
- *     or
- *   + Time slicing is in use and there is a task of equal priority to the
- *     currently running task.
- */
-BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes the calling task from the ready list and places it both
- * on the list of tasks waiting for a particular event, and the
- * list of delayed tasks.  The task will be removed from both lists
- * and replaced on the ready list should either the event occur (and
- * there be no higher priority tasks waiting on the same event) or
- * the delay period expires.
- *
- * The 'unordered' version replaces the event list item value with the
- * xItemValue value, and inserts the list item at the end of the list.
- *
- * The 'ordered' version uses the existing event list item value (which is the
- * owning tasks priority) to insert the list item into the event list is task
- * priority order.
- *
- * @param pxEventList The list containing tasks that are blocked waiting
- * for the event to occur.
- *
- * @param xItemValue The item value to use for the event list item when the
- * event list is not ordered by task priority.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait
- * for the event to occur.  This is specified in kernel ticks,the constant
- * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
- * period.
- */
-void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * This function performs nearly the same function as vTaskPlaceOnEventList().
- * The difference being that this function does not permit tasks to block
- * indefinitely, whereas vTaskPlaceOnEventList() does.
- *
- */
-void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes a task from both the specified event list and the list of blocked
- * tasks, and places it on a ready queue.
- *
- * xTaskRemoveFromEventList()/xTaskRemoveFromUnorderedEventList() will be called
- * if either an event occurs to unblock a task, or the block timeout period
- * expires.
- *
- * xTaskRemoveFromEventList() is used when the event list is in task priority
- * order.  It removes the list item from the head of the event list as that will
- * have the highest priority owning task of all the tasks on the event list.
- * xTaskRemoveFromUnorderedEventList() is used when the event list is not
- * ordered and the event list items hold something other than the owning tasks
- * priority.  In this case the event list item value is updated to the value
- * passed in the xItemValue parameter.
- *
- * @return pdTRUE if the task being removed has a higher priority than the task
- * making the call, otherwise pdFALSE.
- */
-BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
-BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Sets the pointer to the current TCB to the TCB of the highest priority task
- * that is ready to run.
- */
-void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
-
-/*
- * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
- * THE EVENT BITS MODULE.
- */
-TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the handle of the calling task.
- */
-TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-
-
-/*
- * Return the handle of the task running on a certain CPU. Because of
- * the nature of SMP processing, there is no guarantee that this
- * value will still be valid on return and should only be used for
- * debugging purposes.
- */
-TaskHandle_t xTaskGetCurrentTaskHandleForCPU( BaseType_t cpuid );
-
-
-/*
- * Capture the current time status for future reference.
- */
-void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
-
-/*
- * Compare the time status now with that previously captured to see if the
- * timeout has expired.
- */
-BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * Shortcut used by the queue implementation to prevent unnecessary call to
- * taskYIELD();
- */
-void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Returns the scheduler state as taskSCHEDULER_RUNNING,
- * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
- */
-BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Raises the priority of the mutex holder to that of the calling task should
- * the mutex holder have a priority less than the calling task.
- */
-void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
-
-/*
- * Set the priority of a task back to its proper priority in the case that it
- * inherited a higher priority while it was holding a semaphore.
- */
-BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
-
-/*
- * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
- */
-UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-
-/*
- * Get the current core affinity of a task
- */
-BaseType_t xTaskGetAffinity( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/*
- * Set the uxTaskNumber of the task referenced by the xTask parameter to
- * uxHandle.
- */
-void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
-
-/*
- * Only available when configUSE_TICKLESS_IDLE is set to 1.
- * If tickless mode is being used, or a low power mode is implemented, then
- * the tick interrupt will not execute during idle periods.  When this is the
- * case, the tick count value maintained by the scheduler needs to be kept up
- * to date with the actual execution time by being skipped forward by a time
- * equal to the idle period.
- */
-void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
-
-/*
- * Only avilable when configUSE_TICKLESS_IDLE is set to 1.
- * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
- * specific sleep function to determine if it is ok to proceed with the sleep,
- * and if it is ok to proceed, if it is ok to sleep indefinitely.
- *
- * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
- * called with the scheduler suspended, not from within a critical section.  It
- * is therefore possible for an interrupt to request a context switch between
- * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
- * entered.  eTaskConfirmSleepModeStatus() should be called from a short
- * critical section between the timer being stopped and the sleep mode being
- * entered to ensure it is ok to proceed into the sleep mode.
- */
-eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Increment the mutex held count when a mutex is
- * taken and return the handle of the task that has taken the mutex.
- */
-void *pvTaskIncrementMutexHeldCount( void );
-
-/*
- * This function fills array with TaskSnapshot_t structures for every task in the system.
- * Used by core dump facility to get snapshots of all tasks in the system.
- * Only available when configENABLE_TASK_SNAPSHOT is set to 1.
- * @param pxTaskSnapshotArray Pointer to array of TaskSnapshot_t structures to store tasks snapshot data.
- * @param uxArraySize Size of tasks snapshots array.
- * @param pxTcbSz Pointer to store size of TCB.
- * @return Number of elements stored in array.
- */
-UBaseType_t uxTaskGetSnapshotAll( TaskSnapshot_t * const pxTaskSnapshotArray, const UBaseType_t uxArraySize, UBaseType_t * const pxTcbSz );
-
-/** @endcond */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* INC_TASK_H */
-
-
-
diff --git a/tools/sdk/include/freertos/freertos/timers.h b/tools/sdk/include/freertos/freertos/timers.h
deleted file mode 100644
index 17492e64c66..00000000000
--- a/tools/sdk/include/freertos/freertos/timers.h
+++ /dev/null
@@ -1,1258 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-
-#ifndef TIMERS_H
-#define TIMERS_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include timers.h"
-#endif
-
-/*lint -e537 This headers are only multiply included if the application code
-happens to also be including task.h. */
-#include "task.h"
-/*lint +e537 */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * MACROS AND DEFINITIONS
- *----------------------------------------------------------*/
-
-/* IDs for commands that can be sent/received on the timer queue.  These are to
-be used solely through the macros that make up the public software timer API,
-as defined below.  The commands that are sent from interrupts must use the
-highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
-or interrupt version of the queue send function should be used. */
-#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
-#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
-#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
-#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
-#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
-#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
-#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
-#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
-
-#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
-#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
-#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
-#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
-#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
-
-
-/**
- * Type by which software timers are referenced.  For example, a call to
- * xTimerCreate() returns an TimerHandle_t variable that can then be used to
- * reference the subject timer in calls to other software timer API functions
- * (for example, xTimerStart(), xTimerReset(), etc.).
- */
-typedef void * TimerHandle_t;
-
-/**
- * Defines the prototype to which timer callback functions must conform.
- */
-typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
-
-/**
- * Defines the prototype to which functions used with the
- * xTimerPendFunctionCallFromISR() function must conform.
- */
-typedef void (*PendedFunction_t)( void *, uint32_t );
-
-/**
- * Creates a new software timer instance, and returns a handle by which the
- * created software timer can be referenced.
- *
- * Internally, within the FreeRTOS implementation, software timers use a block
- * of memory, in which the timer data structure is stored.  If a software timer
- * is created using xTimerCreate() then the required memory is automatically
- * dynamically allocated inside the xTimerCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a software timer is created using
- * xTimerCreateStatic() then the application writer must provide the memory that
- * will get used by the software timer.  xTimerCreateStatic() therefore allows a
- * software timer to be created without using any dynamic memory allocation.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a
- * timer into the active state.
- *
- * @param pcTimerName A text name that is assigned to the timer.  This is done
- * purely to assist debugging.  The kernel itself only ever references a timer
- * by its handle, and never by its name.
- *
- * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
- * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
- * has been specified in milliseconds.  For example, if the timer must expire
- * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
- * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
- * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
- * equal to 1000.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
- * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- *
- * @param pvTimerID An identifier that is assigned to the timer being created.
- * Typically this would be used in the timer callback function to identify which
- * timer expired when the same callback function is assigned to more than one
- * timer.
- *
- * @param pxCallbackFunction The function to call when the timer expires.
- * Callback functions must have the prototype defined by TimerCallbackFunction_t,
- * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
- *
- * @return If the timer is successfully created then a handle to the newly
- * created timer is returned.  If the timer cannot be created (because either
- * there is insufficient FreeRTOS heap remaining to allocate the timer
- * structures, or the timer period was set to 0) then NULL is returned.
- *
- * Example usage:
- * @code{c}
- * #define NUM_TIMERS 5
- *
- * // An array to hold handles to the created timers.
- * TimerHandle_t xTimers[ NUM_TIMERS ];
- *
- * // An array to hold a count of the number of times each timer expires.
- * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
- *
- * // Define a callback function that will be used by multiple timer instances.
- * // The callback function does nothing but count the number of times the
- * // associated timer expires, and stop the timer once the timer has expired
- * // 10 times.
- * void vTimerCallback( TimerHandle_t pxTimer )
- * {
- * int32_t lArrayIndex;
- * const int32_t xMaxExpiryCountBeforeStopping = 10;
- *
- * 	   // Optionally do something if the pxTimer parameter is NULL.
- * 	   configASSERT( pxTimer );
- *
- *     // Which timer expired?
- *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
- *
- *     // Increment the number of times that pxTimer has expired.
- *     lExpireCounters[ lArrayIndex ] += 1;
- *
- *     // If the timer has expired 10 times then stop it from running.
- *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
- *     {
- *         // Do not use a block time if calling a timer API function from a
- *         // timer callback function, as doing so could cause a deadlock!
- *         xTimerStop( pxTimer, 0 );
- *     }
- * }
- *
- * void main( void )
- * {
- * int32_t x;
- *
- *     // Create then start some timers.  Starting the timers before the scheduler
- *     // has been started means the timers will start running immediately that
- *     // the scheduler starts.
- *     for( x = 0; x < NUM_TIMERS; x++ )
- *     {
- *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
- *                                         ( 100 * x ),   // The timer period in ticks.
- *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
- *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
- *                                         vTimerCallback // Each timer calls the same callback when it expires.
- *                                     );
- *
- *         if( xTimers[ x ] == NULL )
- *         {
- *             // The timer was not created.
- *         }
- *         else
- *         {
- *             // Start the timer.  No block time is specified, and even if one was
- *             // it would be ignored because the scheduler has not yet been
- *             // started.
- *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
- *             {
- *                 // The timer could not be set into the Active state.
- *             }
- *         }
- *     }
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timers running as they have already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endcode
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	TimerHandle_t xTimerCreate(	const char * const pcTimerName,
-								const TickType_t xTimerPeriodInTicks,
-								const UBaseType_t uxAutoReload,
-								void * const pvTimerID,
-								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-#endif
-
- /**
-  * Creates a new software timer instance, and returns a handle by which the
-  * created software timer can be referenced.
-  *
-  * Internally, within the FreeRTOS implementation, software timers use a block
-  * of memory, in which the timer data structure is stored.  If a software timer
-  * is created using xTimerCreate() then the required memory is automatically
-  * dynamically allocated inside the xTimerCreate() function.  (see
-  * http://www.freertos.org/a00111.html).  If a software timer is created using
-  * xTimerCreateStatic() then the application writer must provide the memory that
-  * will get used by the software timer.  xTimerCreateStatic() therefore allows a
-  * software timer to be created without using any dynamic memory allocation.
-  *
-  * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
-  * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
-  * xTimerChangePeriodFromISR() API functions can all be used to transition a
-  * timer into the active state.
-  *
-  * @param pcTimerName A text name that is assigned to the timer.  This is done
-  * purely to assist debugging.  The kernel itself only ever references a timer
-  * by its handle, and never by its name.
-  *
-  * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
-  * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
-  * has been specified in milliseconds.  For example, if the timer must expire
-  * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
-  * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
-  * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
-  * equal to 1000.
-  *
-  * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
-  * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
-  * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
-  * enter the dormant state after it expires.
-  *
-  * @param pvTimerID An identifier that is assigned to the timer being created.
-  * Typically this would be used in the timer callback function to identify which
-  * timer expired when the same callback function is assigned to more than one
-  * timer.
-  *
-  * @param pxCallbackFunction The function to call when the timer expires.
-  * Callback functions must have the prototype defined by TimerCallbackFunction_t,
-  * which is "void vCallbackFunction( TimerHandle_t xTimer );".
-  *
-  * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
-  * will be then be used to hold the software timer's data structures, removing
-  * the need for the memory to be allocated dynamically.
-  *
-  * @return If the timer is created then a handle to the created timer is
-  * returned.  If pxTimerBuffer was NULL then NULL is returned.
-  *
-  * Example usage:
-  * @code{c}
-  *
-  * // The buffer used to hold the software timer's data structure.
-  * static StaticTimer_t xTimerBuffer;
-  *
-  * // A variable that will be incremented by the software timer's callback
-  * // function.
-  * UBaseType_t uxVariableToIncrement = 0;
-  *
-  * // A software timer callback function that increments a variable passed to
-  * // it when the software timer was created.  After the 5th increment the
-  * // callback function stops the software timer.
-  * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
-  * {
-  * UBaseType_t *puxVariableToIncrement;
-  * BaseType_t xReturned;
-  *
-  *     // Obtain the address of the variable to increment from the timer ID.
-  *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
-  *
-  *     // Increment the variable to show the timer callback has executed.
-  *     ( *puxVariableToIncrement )++;
-  *
-  *     // If this callback has executed the required number of times, stop the
-  *     // timer.
-  *     if( *puxVariableToIncrement == 5 )
-  *     {
-  *         // This is called from a timer callback so must not block.
-  *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
-  *     }
-  * }
-  *
-  *
-  * void main( void )
-  * {
-  *     // Create the software time.  xTimerCreateStatic() has an extra parameter
-  *     // than the normal xTimerCreate() API function.  The parameter is a pointer
-  *     // to the StaticTimer_t structure that will hold the software timer
-  *     // structure.  If the parameter is passed as NULL then the structure will be
-  *     // allocated dynamically, just as if xTimerCreate() had been called.
-  *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
-  *                                  xTimerPeriod,     // The period of the timer in ticks.
-  *                                  pdTRUE,           // This is an auto-reload timer.
-  *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
-  *                                  prvTimerCallback, // The function to execute when the timer expires.
-  *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
-  *
-  *     // The scheduler has not started yet so a block time is not used.
-  *     xReturned = xTimerStart( xTimer, 0 );
-  *
-  *     // ...
-  *     // Create tasks here.
-  *     // ...
-  *
-  *     // Starting the scheduler will start the timers running as they have already
-  *     // been set into the active state.
-  *     vTaskStartScheduler();
-  *
-  *     // Should not reach here.
-  *     for( ;; );
-  * }
-  * @endcode
-  */
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,
-										const TickType_t xTimerPeriodInTicks,
-										const UBaseType_t uxAutoReload,
-										void * const pvTimerID,
-										TimerCallbackFunction_t pxCallbackFunction,
-										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
- #endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * Returns the ID assigned to the timer.
- *
- * IDs are assigned to timers using the pvTimerID parameter of the call to
- * xTimerCreated() that was used to create the timer.
- *
- * If the same callback function is assigned to multiple timers then the timer
- * ID can be used within the callback function to identify which timer actually
- * expired.
- *
- * @param xTimer The timer being queried.
- *
- * @return The ID assigned to the timer being queried.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- */
-void *pvTimerGetTimerID( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * Sets the ID assigned to the timer.
- *
- * IDs are assigned to timers using the pvTimerID parameter of the call to
- * xTimerCreated() that was used to create the timer.
- *
- * If the same callback function is assigned to multiple timers then the timer
- * ID can be used as time specific (timer local) storage.
- *
- * @param xTimer The timer being updated.
- *
- * @param pvNewID The ID to assign to the timer.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- */
-void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
-
-/**
- * Queries a timer to see if it is active or dormant.
- *
- * A timer will be dormant if:
- *
- *     1) It has been created but not started, or
- *
- *     2) It is an expired one-shot timer that has not been restarted.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
- * active state.
- *
- * @param xTimer The timer being queried.
- *
- * @return pdFALSE will be returned if the timer is dormant.  A value other than
- * pdFALSE will be returned if the timer is active.
- *
- * Example usage:
- * @code{c}
- * // This function assumes xTimer has already been created.
- * void vAFunction( TimerHandle_t xTimer )
- * {
- *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
- *     {
- *         // xTimer is active, do something.
- *     }
- *     else
- *     {
- *         // xTimer is not active, do something else.
- *     }
- * }
- * @endcode
- */
-BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * xTimerGetTimerDaemonTaskHandle() is only available if
- * INCLUDE_xTimerGetTimerDaemonTaskHandle is set to 1 in FreeRTOSConfig.h.
- *
- * Simply returns the handle of the timer service/daemon task.  It it not valid
- * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
- */
-TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
-
-/**
- * Returns the period of a timer.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return The period of the timer in ticks.
- */
-TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * Returns the time in ticks at which the timer will expire.  If this is less
- * than the current tick count then the expiry time has overflowed from the
- * current time.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return If the timer is running then the time in ticks at which the timer
- * will next expire is returned.  If the timer is not running then the return
- * value is undefined.
- */
-TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerStart() starts a timer that was previously created using the
- * xTimerCreate() API function.  If the timer had already been started and was
- * already in the active state, then xTimerStart() has equivalent functionality
- * to the xTimerReset() API function.
- *
- * Starting a timer ensures the timer is in the active state.  If the timer
- * is not stopped, deleted, or reset in the mean time, the callback function
- * associated with the timer will get called 'n' ticks after xTimerStart() was
- * called, where 'n' is the timers defined period.
- *
- * It is valid to call xTimerStart() before the scheduler has been started, but
- * when this is done the timer will not actually start until the scheduler is
- * started, and the timers expiry time will be relative to when the scheduler is
- * started, not relative to when xTimerStart() was called.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
- * to be available.
- *
- * @param xTimer The handle of the timer being started/restarted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the start command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the start command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system, although the
- * timers expiry time is relative to when xTimerStart() is actually called.  The
- * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- *
- */
-#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
-
-/**
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerStop() stops a timer that was previously started using either of the
- * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
- * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
- *
- * Stopping a timer ensures the timer is not in the active state.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
- * to be available.
- *
- * @param xTimer The handle of the timer being stopped.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the stop command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the stop command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- *
- */
-#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
-
-/**
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerChangePeriod() changes the period of a timer that was previously
- * created using the xTimerCreate() API function.
- *
- * xTimerChangePeriod() can be called to change the period of an active or
- * dormant state timer.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for
- * xTimerChangePeriod() to be available.
- *
- * @param xTimer The handle of the timer that is having its period changed.
- *
- * @param xNewPeriod The new period for xTimer. Timer periods are specified in
- * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
- * that has been specified in milliseconds.  For example, if the timer must
- * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
- * if the timer must expire after 500ms, then xNewPeriod can be set to
- * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
- * or equal to 1000.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the change period command to be
- * successfully sent to the timer command queue, should the queue already be
- * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
- * xTimerChangePeriod() is called before the scheduler is started.
- *
- * @return pdFAIL will be returned if the change period command could not be
- * sent to the timer command queue even after xTicksToWait ticks had passed.
- * pdPASS will be returned if the command was successfully sent to the timer
- * command queue.  When the command is actually processed will depend on the
- * priority of the timer service/daemon task relative to other tasks in the
- * system.  The timer service/daemon task priority is set by the
- * configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @code{c}
- * // This function assumes xTimer has already been created.  If the timer
- * // referenced by xTimer is already active when it is called, then the timer
- * // is deleted.  If the timer referenced by xTimer is not active when it is
- * // called, then the period of the timer is set to 500ms and the timer is
- * // started.
- * void vAFunction( TimerHandle_t xTimer )
- * {
- *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
- *     {
- *         // xTimer is already active - delete it.
- *         xTimerDelete( xTimer );
- *     }
- *     else
- *     {
- *         // xTimer is not active, change its period to 500ms.  This will also
- *         // cause the timer to start.  Block for a maximum of 100 ticks if the
- *         // change period command cannot immediately be sent to the timer
- *         // command queue.
- *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
- *         {
- *             // The command was successfully sent.
- *         }
- *         else
- *         {
- *             // The command could not be sent, even after waiting for 100 ticks
- *             // to pass.  Take appropriate action here.
- *         }
- *     }
- * }
- * @endcode
- */
- #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
-
-/**
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerDelete() deletes a timer that was previously created using the
- * xTimerCreate() API function.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for
- * xTimerDelete() to be available.
- *
- * @param xTimer The handle of the timer being deleted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the delete command to be
- * successfully sent to the timer command queue, should the queue already be
- * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
- * is called before the scheduler is started.
- *
- * @return pdFAIL will be returned if the delete command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerChangePeriod() API function example usage scenario.
- */
-#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
-
-/**
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerReset() re-starts a timer that was previously created using the
- * xTimerCreate() API function.  If the timer had already been started and was
- * already in the active state, then xTimerReset() will cause the timer to
- * re-evaluate its expiry time so that it is relative to when xTimerReset() was
- * called.  If the timer was in the dormant state then xTimerReset() has
- * equivalent functionality to the xTimerStart() API function.
- *
- * Resetting a timer ensures the timer is in the active state.  If the timer
- * is not stopped, deleted, or reset in the mean time, the callback function
- * associated with the timer will get called 'n' ticks after xTimerReset() was
- * called, where 'n' is the timers defined period.
- *
- * It is valid to call xTimerReset() before the scheduler has been started, but
- * when this is done the timer will not actually start until the scheduler is
- * started, and the timers expiry time will be relative to when the scheduler is
- * started, not relative to when xTimerReset() was called.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
- * to be available.
- *
- * @param xTimer The handle of the timer being reset/started/restarted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the reset command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the reset command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system, although the
- * timers expiry time is relative to when xTimerStart() is actually called.  The
- * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- * @code{c}
- * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer.
- *
- * TimerHandle_t xBacklightTimer = NULL;
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press event handler.
- * void vKeyPressEventHandler( char cKey )
- * {
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
- *     // if it cannot be sent immediately.
- *     vSetBacklightState( BACKLIGHT_ON );
- *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
- *     {
- *         // The reset command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- * }
- *
- * void main( void )
- * {
- * int32_t x;
- *
- *     // Create then start the one-shot timer that is responsible for turning
- *     // the back-light off if no keys are pressed within a 5 second period.
- *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
- *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
- *                                     pdFALSE,                    // The timer is a one-shot timer.
- *                                     0,                          // The id is not used by the callback so can take any value.
- *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
- *                                   );
- *
- *     if( xBacklightTimer == NULL )
- *     {
- *         // The timer was not created.
- *     }
- *     else
- *     {
- *         // Start the timer.  No block time is specified, and even if one was
- *         // it would be ignored because the scheduler has not yet been
- *         // started.
- *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
- *         {
- *             // The timer could not be set into the Active state.
- *         }
- *     }
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timer running as it has already
- *     // been set into the active state.
- *     xTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endcode
- */
-#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
-
-/**
- * A version of xTimerStart() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer being started/restarted.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerStartFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
- * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the start command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system, although the timers expiry time is
- * relative to when xTimerStartFromISR() is actually called.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- * @code{c}
- * // This scenario assumes xBacklightTimer has already been created.  When a
- * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer, and unlike the example given for
- * // the xTimerReset() function, the key press event handler is an interrupt
- * // service routine.
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press interrupt service routine.
- * void vKeyPressEventInterruptHandler( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // Ensure the LCD back-light is on, then restart the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  This is an interrupt service routine so can only
- *     // call FreeRTOS API functions that end in "FromISR".
- *     vSetBacklightState( BACKLIGHT_ON );
- *
- *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
- *     // as both cause the timer to re-calculate its expiry time.
- *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
- *     // declared (in this function).
- *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The start command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endcode
- */
-#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * A version of xTimerStop() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer being stopped.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerStopFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
- * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the stop command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system.  The timer service/daemon task
- * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @code{c}
- * // This scenario assumes xTimer has already been created and started.  When
- * // an interrupt occurs, the timer should be simply stopped.
- *
- * // The interrupt service routine that stops the timer.
- * void vAnExampleInterruptServiceRoutine( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // The interrupt has occurred - simply stop the timer.
- *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
- *     // (within this function).  As this is an interrupt service routine, only
- *     // FreeRTOS API functions that end in "FromISR" can be used.
- *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The stop command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endcode
- */
-#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * A version of xTimerChangePeriod() that can be called from an interrupt
- * service routine.
- *
- * @param xTimer The handle of the timer that is having its period changed.
- *
- * @param xNewPeriod The new period for xTimer. Timer periods are specified in
- * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
- * that has been specified in milliseconds.  For example, if the timer must
- * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
- * if the timer must expire after 500ms, then xNewPeriod can be set to
- * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
- * or equal to 1000.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
- * timer command queue, so has the potential to transition the timer service/
- * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
- * causes the timer service/daemon task to leave the Blocked state, and the
- * timer service/daemon task has a priority equal to or greater than the
- * currently executing task (the task that was interrupted), then
- * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
- * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
- * this value to pdTRUE then a context switch should be performed before the
- * interrupt exits.
- *
- * @return pdFAIL will be returned if the command to change the timers period
- * could not be sent to the timer command queue.  pdPASS will be returned if the
- * command was successfully sent to the timer command queue.  When the command
- * is actually processed will depend on the priority of the timer service/daemon
- * task relative to other tasks in the system.  The timer service/daemon task
- * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @code{c}
- * // This scenario assumes xTimer has already been created and started.  When
- * // an interrupt occurs, the period of xTimer should be changed to 500ms.
- *
- * // The interrupt service routine that changes the period of xTimer.
- * void vAnExampleInterruptServiceRoutine( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // The interrupt has occurred - change the period of xTimer to 500ms.
- *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
- *     // (within this function).  As this is an interrupt service routine, only
- *     // FreeRTOS API functions that end in "FromISR" can be used.
- *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The command to change the timers period was not executed
- *         // successfully.  Take appropriate action here.
- *     }
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endcode
- */
-#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * A version of xTimerReset() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer that is to be started, reset, or
- * restarted.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerResetFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
- * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the reset command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system, although the timers expiry time is
- * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
- * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @code{c}
- * // This scenario assumes xBacklightTimer has already been created.  When a
- * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer, and unlike the example given for
- * // the xTimerReset() function, the key press event handler is an interrupt
- * // service routine.
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press interrupt service routine.
- * void vKeyPressEventInterruptHandler( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  This is an interrupt service routine so can only
- *     // call FreeRTOS API functions that end in "FromISR".
- *     vSetBacklightState( BACKLIGHT_ON );
- *
- *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
- *     // as both cause the timer to re-calculate its expiry time.
- *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
- *     // declared (in this function).
- *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The reset command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endcode
- */
-#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
-
-
-/**
- * Used from application interrupt service routines to defer the execution of a
- * function to the RTOS daemon task (the timer service task, hence this function
- * is implemented in timers.c and is prefixed with 'Timer').
- *
- * Ideally an interrupt service routine (ISR) is kept as short as possible, but
- * sometimes an ISR either has a lot of processing to do, or needs to perform
- * processing that is not deterministic.  In these cases
- * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
- * to the RTOS daemon task.
- *
- * A mechanism is provided that allows the interrupt to return directly to the
- * task that will subsequently execute the pended callback function.  This
- * allows the callback function to execute contiguously in time with the
- * interrupt - just as if the callback had executed in the interrupt itself.
- *
- * @param xFunctionToPend The function to execute from the timer service/
- * daemon task.  The function must conform to the PendedFunction_t
- * prototype.
- *
- * @param pvParameter1 The value of the callback function's first parameter.
- * The parameter has a void * type to allow it to be used to pass any type.
- * For example, unsigned longs can be cast to a void *, or the void * can be
- * used to point to a structure.
- *
- * @param ulParameter2 The value of the callback function's second parameter.
- *
- * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
- * will result in a message being sent to the timer daemon task.  If the
- * priority of the timer daemon task (which is set using
- * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
- * the currently running task (the task the interrupt interrupted) then
- * *pxHigherPriorityTaskWoken will be set to pdTRUE within
- * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
- * requested before the interrupt exits.  For that reason
- * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
- * example code below.
- *
- * @return pdPASS is returned if the message was successfully sent to the
- * timer daemon task, otherwise pdFALSE is returned.
- *
- * Example usage:
- * @code{c}
- *
- *	// The callback function that will execute in the context of the daemon task.
- *  // Note callback functions must all use this same prototype.
- *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
- *	{
- *		BaseType_t xInterfaceToService;
- *
- *		// The interface that requires servicing is passed in the second
- *      // parameter.  The first parameter is not used in this case.
- *		xInterfaceToService = ( BaseType_t ) ulParameter2;
- *
- *		// ...Perform the processing here...
- *	}
- *
- *	// An ISR that receives data packets from multiple interfaces
- *  void vAnISR( void )
- *	{
- *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
- *
- *		// Query the hardware to determine which interface needs processing.
- *		xInterfaceToService = prvCheckInterfaces();
- *
- *      // The actual processing is to be deferred to a task.  Request the
- *      // vProcessInterface() callback function is executed, passing in the
- *		// number of the interface that needs processing.  The interface to
- *		// service is passed in the second parameter.  The first parameter is
- *		// not used in this case.
- *		xHigherPriorityTaskWoken = pdFALSE;
- *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
- *
- *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
- *		// switch should be requested.  The macro used is port specific and will
- *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
- *		// the documentation page for the port being used.
- *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- *
- *	}
- * @endcode
- */
-BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken );
-
- /**
-  * Used to defer the execution of a function to the RTOS daemon task (the timer
-  * service task, hence this function is implemented in timers.c and is prefixed
-  * with 'Timer').
-  *
-  * @param xFunctionToPend The function to execute from the timer service/
-  * daemon task.  The function must conform to the PendedFunction_t
-  * prototype.
-  *
-  * @param pvParameter1 The value of the callback function's first parameter.
-  * The parameter has a void * type to allow it to be used to pass any type.
-  * For example, unsigned longs can be cast to a void *, or the void * can be
-  * used to point to a structure.
-  *
-  * @param ulParameter2 The value of the callback function's second parameter.
-  *
-  * @param xTicksToWait Calling this function will result in a message being
-  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
-  * time the calling task should remain in the Blocked state (so not using any
-  * processing time) for space to become available on the timer queue if the
-  * queue is found to be full.
-  *
-  * @return pdPASS is returned if the message was successfully sent to the
-  * timer daemon task, otherwise pdFALSE is returned.
-  *
-  */
-BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
-
-/**
- * Returns the name that was assigned to a timer when the timer was created.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return The name assigned to the timer specified by the xTimer parameter.
- */
-const char * pcTimerGetTimerName( TimerHandle_t xTimer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/** @cond */
-/*
- * Functions beyond this part are not part of the public API and are intended
- * for use by the kernel only.
- */
-BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
-BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/** @endcond */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* TIMERS_H */
-
-
-
diff --git a/tools/sdk/include/freertos/freertos/xtensa_api.h b/tools/sdk/include/freertos/freertos/xtensa_api.h
deleted file mode 100644
index 19630ce5819..00000000000
--- a/tools/sdk/include/freertos/freertos/xtensa_api.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*******************************************************************************
-Copyright (c) 2006-2015 Cadence Design Systems Inc.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice shall be included
-in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-******************************************************************************/
-
-/******************************************************************************
-  Xtensa-specific API for RTOS ports.
-******************************************************************************/
-
-#ifndef __XTENSA_API_H__
-#define __XTENSA_API_H__
-
-#include <xtensa/hal.h>
-
-#include "xtensa_context.h"
-
-
-/* Typedef for C-callable interrupt handler function */
-typedef void (*xt_handler)(void *);
-
-/* Typedef for C-callable exception handler function */
-typedef void (*xt_exc_handler)(XtExcFrame *);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified exception. The handler
-  will be installed on the core that calls this function.
-
-    n        - Exception number (type)
-    f        - Handler function address, NULL to uninstall handler.
-
-  The handler will be passed a pointer to the exception frame, which is created
-  on the stack of the thread that caused the exception.
-
-  If the handler returns, the thread context will be restored and the faulting
-  instruction will be retried. Any values in the exception frame that are
-  modified by the handler will be restored as part of the context. For details
-  of the exception frame structure see xtensa_context.h.
--------------------------------------------------------------------------------
-*/
-extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified interrupt. The handler
-  will be installed on the core that calls this function.
- 
-    n        - Interrupt number.
-    f        - Handler function address, NULL to uninstall handler.
-    arg      - Argument to be passed to handler.
--------------------------------------------------------------------------------
-*/
-extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to enable the specified interrupts on the core that runs
-  this code.
-
-    mask     - Bit mask of interrupts to be enabled.
--------------------------------------------------------------------------------
-*/
-extern void xt_ints_on(unsigned int mask);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to disable the specified interrupts on the core that runs
-  this code.
-
-    mask     - Bit mask of interrupts to be disabled.
--------------------------------------------------------------------------------
-*/
-extern void xt_ints_off(unsigned int mask);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set the specified (s/w) interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intset(unsigned int arg)
-{
-    xthal_set_intset(arg);
-}
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to clear the specified (s/w or edge-triggered)
-  interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intclear(unsigned int arg)
-{
-    xthal_set_intclear(arg);
-}
-
-/*
--------------------------------------------------------------------------------
-  Call this function to get handler's argument for the specified interrupt.
- 
-    n        - Interrupt number.
--------------------------------------------------------------------------------
-*/
-extern void * xt_get_interrupt_handler_arg(int n);
-
-#endif /* __XTENSA_API_H__ */
-
diff --git a/tools/sdk/include/freertos/freertos/xtensa_config.h b/tools/sdk/include/freertos/freertos/xtensa_config.h
deleted file mode 100644
index 58baee2da71..00000000000
--- a/tools/sdk/include/freertos/freertos/xtensa_config.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-  Configuration-specific information for Xtensa build. This file must be
-  included in FreeRTOSConfig.h to properly set up the config-dependent
-  parameters correctly.
-
-  NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
-  be defined to be > 0 somewhere above or on the command line.
-
-*******************************************************************************/
-
-#ifndef XTENSA_CONFIG_H
-#define XTENSA_CONFIG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <xtensa/hal.h>
-#include <xtensa/config/core.h>
-#include <xtensa/config/system.h>	/* required for XSHAL_CLIB */
-
-#include "xtensa_context.h"
-
-
-/*-----------------------------------------------------------------------------
-*                                 STACK REQUIREMENTS
-*
-* This section defines the minimum stack size, and the extra space required to
-* be allocated for saving coprocessor state and/or C library state information
-* (if thread safety is enabled for the C library). The sizes are in bytes.
-*
-* Stack sizes for individual tasks should be derived from these minima based on
-* the maximum call depth of the task and the maximum level of interrupt nesting.
-* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
-* on the requirement for a task that calls nothing else but can be interrupted.
-* This assumes that interrupt handlers do not call more than a few levels deep.
-* If this is not true, i.e. one or more interrupt handlers make deep calls then
-* the minimum must be increased.
-*
-* If the Xtensa processor configuration includes coprocessors, then space is 
-* allocated to save the coprocessor state on the stack.
-*
-* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
-* is defined) then space is allocated to save the C library context in the TCB.
-* 
-* Allocating insufficient stack space is a common source of hard-to-find errors.
-* During development, it is best to enable the FreeRTOS stack checking features.
-*
-* Usage:
-* 
-* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
-*                            use of the C library. This will require extra stack
-*                            space to be allocated for tasks that use the C library
-*                            reentrant functions. See below for more information.
-* 
-* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
-* support thread safety. Check your core configuration to see which C library
-* was chosen for your system.
-* 
-* XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
-*                            that you do not use a stack smaller than this for any
-*                            task. In case you want to use stacks smaller than this
-*                            size, you must verify that the smaller size(s) will work
-*                            under all operating conditions.
-*
-* XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
-*                            that does not make C library reentrant calls. Add this
-*                            to the amount of stack space required by the task itself.
-*
-* XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
-*
------------------------------------------------------------------------------*/
-
-/* Extra space required for interrupt/exception hooks. */
-#ifdef XT_INTEXC_HOOKS
-  #ifdef __XTENSA_CALL0_ABI__
-    #define STK_INTEXC_EXTRA        0x200
-  #else
-    #define STK_INTEXC_EXTRA        0x180
-  #endif
-#else
-  #define STK_INTEXC_EXTRA          0
-#endif
-
-#define XT_CLIB_CONTEXT_AREA_SIZE         0
-
-/*------------------------------------------------------------------------------
-  Extra size -- interrupt frame plus coprocessor save area plus hook space.
-  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
-------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
-#else
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
-#endif
-
-/*------------------------------------------------------------------------------
-  Space allocated for user code -- function calls and local variables.
-  NOTE: This number can be adjusted to suit your needs. You must verify that the
-  amount of space you reserve is adequate for the worst-case conditions in your
-  application.
-  NOTE: The windowed ABI requires more stack, since space has to be reserved
-  for spilling register windows.
-------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-  #define XT_USER_SIZE            0x200
-#else
-  #define XT_USER_SIZE            0x400
-#endif
-
-/* Minimum recommended stack size. */
-#define XT_STACK_MIN_SIZE         ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
-
-/* OS overhead with and without C library thread context. */
-#define XT_STACK_EXTRA            (XT_XTRA_SIZE)
-#define XT_STACK_EXTRA_CLIB       (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XTENSA_CONFIG_H */
-
diff --git a/tools/sdk/include/freertos/freertos/xtensa_context.h b/tools/sdk/include/freertos/freertos/xtensa_context.h
deleted file mode 100644
index 9e6fe558f54..00000000000
--- a/tools/sdk/include/freertos/freertos/xtensa_context.h
+++ /dev/null
@@ -1,378 +0,0 @@
-/*******************************************************************************
-Copyright (c) 2006-2015 Cadence Design Systems Inc.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice shall be included
-in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-        XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
-
-This header contains definitions and macros for use primarily by Xtensa
-RTOS assembly coded source files. It includes and uses the Xtensa hardware
-abstraction layer (HAL) to deal with config specifics. It may also be
-included in C source files.
-
-!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
-
-NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
-
-*******************************************************************************/
-
-#ifndef XTENSA_CONTEXT_H
-#define XTENSA_CONTEXT_H
-
-#ifdef __ASSEMBLER__
-#include    <xtensa/coreasm.h>
-#endif
-
-#include    <xtensa/config/tie.h>
-#include    <xtensa/corebits.h>
-#include    <xtensa/config/system.h>
-#include <xtensa/xtruntime-frames.h>
-
-
-/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
-#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
-
-
-/*
--------------------------------------------------------------------------------
-  Macros that help define structures for both C and assembler.
--------------------------------------------------------------------------------
-*/
-
-#ifdef STRUCT_BEGIN
-#undef STRUCT_BEGIN
-#undef STRUCT_FIELD
-#undef STRUCT_AFIELD
-#undef STRUCT_END
-#endif
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-
-#define STRUCT_BEGIN            .pushsection .text; .struct 0
-#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
-#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
-#define STRUCT_END(sname)       sname##Size:; .popsection
-
-#else
-
-#define STRUCT_BEGIN            typedef struct {
-#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
-#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
-#define STRUCT_END(sname)       } sname;
-
-#endif //_ASMLANGUAGE || __ASSEMBLER__
-
-
-/*
--------------------------------------------------------------------------------
-  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
-
-  A stack frame of this structure is allocated for any interrupt or exception.
-  It goes on the current stack. If the RTOS has a system stack for handling 
-  interrupts, every thread stack must allow space for just one interrupt stack 
-  frame, then nested interrupt stack frames go on the system stack.
-
-  The frame includes basic registers (explicit) and "extra" registers introduced 
-  by user TIE or the use of the MAC16 option in the user's Xtensa config.
-  The frame size is minimized by omitting regs not applicable to user's config.
-
-  For Windowed ABI, this stack frame includes the interruptee's base save area,
-  another base save area to manage gcc nested functions, and a little temporary 
-  space to help manage the spilling of the register windows.
--------------------------------------------------------------------------------
-*/
-
-STRUCT_BEGIN
-STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
-STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
-STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
-STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
-STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
-STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
-STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
-STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
-STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
-STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
-STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
-STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
-STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
-STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
-STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
-STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
-STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
-STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
-STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
-STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
-STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
-STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
-STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
-STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
-#endif
-#ifndef __XTENSA_CALL0_ABI__
-/* Temporary space for saving stuff during window spill */
-STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
-STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
-STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
-#endif
-#ifdef XT_USE_SWPRI
-/* Storage for virtual priority mask */
-STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
-#endif
-#ifdef XT_USE_OVLY
-/* Storage for overlay state */
-STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
-#endif
-STRUCT_END(XtExcFrame)
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-#define XT_STK_NEXT1      XtExcFrameSize
-#else
-#define XT_STK_NEXT1      sizeof(XtExcFrame)
-#endif
-
-/* Allocate extra storage if needed */
-#if XCHAL_EXTRA_SA_SIZE != 0
-
-#if XCHAL_EXTRA_SA_ALIGN <= 16
-#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
-#else
-/* If need more alignment than stack, add space for dynamic alignment */
-#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
-#endif
-#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
-
-#else
-
-#define XT_STK_NEXT2            XT_STK_NEXT1   
-
-#endif
-
-/*
--------------------------------------------------------------------------------
-  This is the frame size. Add space for 4 registers (interruptee's base save
-  area) and some space for gcc nested functions if any.
--------------------------------------------------------------------------------
-*/
-#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
-
-
-/*
--------------------------------------------------------------------------------
-  SOLICITED STACK FRAME FOR A THREAD
-
-  A stack frame of this structure is allocated whenever a thread enters the 
-  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
-  It goes on the current thread's stack.
-
-  The solicited frame only includes registers that are required to be preserved
-  by the callee according to the compiler's ABI conventions, some space to save 
-  the return address for returning to the caller, and the caller's PS register.
-
-  For Windowed ABI, this stack frame includes the caller's base save area.
-
-  Note on XT_SOL_EXIT field:
-      It is necessary to distinguish a solicited from an interrupt stack frame.
-      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
-      always at the same offset (0). It can be written with a code (usually 0) 
-      to distinguish a solicted frame from an interrupt frame. An RTOS port may
-      opt to ignore this field if it has another way of distinguishing frames.
--------------------------------------------------------------------------------
-*/
-
-STRUCT_BEGIN
-#ifdef __XTENSA_CALL0_ABI__
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
-STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
-STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
-#else
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
-STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
-STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
-#endif
-STRUCT_END(XtSolFrame)
-
-/* Size of solicited stack frame */
-#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
-
-
-/*
--------------------------------------------------------------------------------
-  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
-
-  The RTOS must provide an area per thread to save the state of co-processors
-  when that thread does not have control. Co-processors are context-switched
-  lazily (on demand) only when a new thread uses a co-processor instruction,
-  otherwise a thread retains ownership of the co-processor even when it loses
-  control of the processor. An Xtensa co-processor exception is triggered when
-  any co-processor instruction is executed by a thread that is not the owner,
-  and the context switch of that co-processor is then peformed by the handler.
-  Ownership represents which thread's state is currently in the co-processor.
-
-  Co-processors may not be used by interrupt or exception handlers. If an 
-  co-processor instruction is executed by an interrupt or exception handler,
-  the co-processor exception handler will trigger a kernel panic and freeze.
-  This restriction is introduced to reduce the overhead of saving and restoring
-  co-processor state (which can be quite large) and in particular remove that
-  overhead from interrupt handlers.
-
-  The co-processor state save area may be in any convenient per-thread location
-  such as in the thread control block or above the thread stack area. It need
-  not be in the interrupt stack frame since interrupts don't use co-processors.
-
-  Along with the save area for each co-processor, two bitmasks with flags per 
-  co-processor (laid out as in the CPENABLE reg) help manage context-switching
-  co-processors as efficiently as possible:
-
-  XT_CPENABLE
-    The contents of a non-running thread's CPENABLE register.
-    It represents the co-processors owned (and whose state is still needed)
-    by the thread. When a thread is preempted, its CPENABLE is saved here.
-    When a thread solicits a context-swtich, its CPENABLE is cleared - the
-    compiler has saved the (caller-saved) co-proc state if it needs to.
-    When a non-running thread loses ownership of a CP, its bit is cleared.
-    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
-    Avoids co-processor exceptions when no change of ownership is needed.
-
-  XT_CPSTORED
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether the state of each co-processor is saved in the state 
-    save area. When a thread enters the kernel, only the state of co-procs
-    still enabled in CPENABLE is saved. When the co-processor exception 
-    handler assigns ownership of a co-processor to a thread, it restores 
-    the saved state only if this bit is set, and clears this bit.
-
-  XT_CP_CS_ST
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether callee-saved state is saved in the state save area.
-    Callee-saved state is saved by itself on a solicited context switch,
-    and restored when needed by the coprocessor exception handler.
-    Unsolicited switches will cause the entire coprocessor to be saved
-    when necessary.
-
-  XT_CP_ASA
-    Pointer to the aligned save area.  Allows it to be aligned more than
-    the overall save area (which might only be stack-aligned or TCB-aligned).
-    Especially relevant for Xtensa cores configured with a very large data
-    path that requires alignment greater than 16 bytes (ABI stack alignment).
--------------------------------------------------------------------------------
-*/
-
-#if XCHAL_CP_NUM > 0
-
-/*  Offsets of each coprocessor save area within the 'aligned save area':  */
-#define XT_CP0_SA   0
-#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
-#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
-#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
-#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
-#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
-#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
-#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
-#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
-
-/*  Offsets within the overall save area:  */
-#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
-#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
-#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
-#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
-/*  Overall size allows for dynamic alignment:  */
-#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
-#else
-#define XT_CP_SIZE  0
-#endif
-
-
-/*
- Macro to get the current core ID. Only uses the reg given as an argument.
- Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0)
- and 0xABAB on the APP CPU (1). We can distinguish between the two by checking
- bit 13: it's 1 on the APP and 0 on the PRO processor.
-*/
-#ifdef __ASSEMBLER__
-	.macro getcoreid reg
-	rsr.prid \reg
-	extui \reg,\reg,13,1
-	.endm
-#endif
-
-#define CORE_ID_PRO 0xCDCD
-#define CORE_ID_APP 0xABAB
-
-/*
--------------------------------------------------------------------------------
-  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
-
-  Convenient where the frame size requirements are the same for both ABIs.
-    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
-    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
-
-  where size = size of stack frame in bytes (must be >0 and aligned to 16).
-  For framed functions the frame is created and the return address saved at
-  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
-  For frameless functions, there is no frame and return address remains in a0.
-  Note: Because CPP macros expand to a single line, macros requiring multi-line 
-  expansions are implemented as assembler macros.
--------------------------------------------------------------------------------
-*/
-
-#ifdef __ASSEMBLER__
-#ifdef __XTENSA_CALL0_ABI__
-  /* Call0 */
-  #define ENTRY(sz)     entry1  sz
-    .macro  entry1 size=0x10
-    addi    sp, sp, -\size
-    s32i    a0, sp, 0
-    .endm
-  #define ENTRY0      
-  #define RET(sz)       ret1    sz
-    .macro  ret1 size=0x10
-    l32i    a0, sp, 0
-    addi    sp, sp, \size
-    ret
-    .endm
-  #define RET0          ret
-#else
-  /* Windowed */
-  #define ENTRY(sz)     entry   sp, sz
-  #define ENTRY0        entry   sp, 0x10
-  #define RET(sz)       retw
-  #define RET0          retw
-#endif
-#endif
-
-
-
-
-
-#endif /* XTENSA_CONTEXT_H */
-
diff --git a/tools/sdk/include/freertos/freertos/xtensa_rtos.h b/tools/sdk/include/freertos/freertos/xtensa_rtos.h
deleted file mode 100644
index 25d42da59bc..00000000000
--- a/tools/sdk/include/freertos/freertos/xtensa_rtos.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-        RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
-                            (FreeRTOS Port)
-
-This header is the primary glue between generic Xtensa RTOS support
-sources and a specific RTOS port for Xtensa.  It contains definitions
-and macros for use primarily by Xtensa assembly coded source files.
-
-Macros in this header map callouts from generic Xtensa files to specific
-RTOS functions. It may also be included in C source files.
-
-Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 
-architecture, using the Xtensa hardware abstraction layer (HAL) to deal 
-with configuration specifics.
-
-Should be included by all Xtensa generic and RTOS port-specific sources.
-
-*******************************************************************************/
-
-#ifndef XTENSA_RTOS_H
-#define XTENSA_RTOS_H
-
-#ifdef __ASSEMBLER__
-#include    <xtensa/coreasm.h>
-#else
-#include    <xtensa/config/core.h>
-#endif
-
-#include    <xtensa/corebits.h>
-#include    <xtensa/config/system.h>
-
-/*
-Include any RTOS specific definitions that are needed by this header.
-*/
-#include    "FreeRTOSConfig.h"
-
-/*
-Convert FreeRTOSConfig definitions to XTENSA definitions.
-However these can still be overridden from the command line.
-*/
-
-#ifndef XT_SIMULATOR
-  #if configXT_SIMULATOR
-    #define XT_SIMULATOR             1  /* Simulator mode */
-  #endif
-#endif
-
-#ifndef XT_BOARD
-  #if configXT_BOARD
-    #define XT_BOARD                 1  /* Board mode */
-  #endif
-#endif
-
-#ifndef XT_TIMER_INDEX
-  #if defined configXT_TIMER_INDEX
-    #define XT_TIMER_INDEX           configXT_TIMER_INDEX  /* Index of hardware timer to be used */
-  #endif
-#endif
-
-#ifndef XT_INTEXC_HOOKS
-  #if configXT_INTEXC_HOOKS
-    #define XT_INTEXC_HOOKS          1  /* Enables exception hooks */
-  #endif
-#endif
-
-#if !defined(XT_SIMULATOR) && !defined(XT_BOARD)
-  #error Either XT_SIMULATOR or XT_BOARD must be defined.
-#endif
-
-
-/*
-Name of RTOS (for messages).
-*/
-#define XT_RTOS_NAME    FreeRTOS
-
-/*
-Check some Xtensa configuration requirements and report error if not met.
-Error messages can be customize to the RTOS port.
-*/
-
-#if !XCHAL_HAVE_XEA2
-#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
-#endif
-
-
-/*******************************************************************************
-
-RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
-
-Define callout macros used in generic Xtensa code to interact with the RTOS.
-The macros are simply the function names for use in calls from assembler code.
-Some of these functions may call back to generic functions in xtensa_context.h .
-
-*******************************************************************************/
-
-/*
-Inform RTOS of entry into an interrupt handler that will affect it. 
-Allows RTOS to manage switch to any system stack and count nesting level.
-Called after minimal context has been saved, with interrupts disabled.
-RTOS port can call0 _xt_context_save to save the rest of the context.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_ENTER(void)
-#define XT_RTOS_INT_ENTER   _frxt_int_enter
-
-/*
-Inform RTOS of completion of an interrupt handler, and give control to
-RTOS to perform thread/task scheduling, switch back from any system stack
-and restore the context, and return to the exit dispatcher saved in the
-stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
-to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
-leaving only a minimal part of the context to be restored by the exit
-dispatcher. This function does not return to the place it was called from.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_EXIT(void)
-#define XT_RTOS_INT_EXIT    _frxt_int_exit
-
-/*
-Inform RTOS of the occurrence of a tick timer interrupt.
-If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
-May be coded in or called from C or assembly, per ABI conventions.
-RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
-*/
-// void XT_RTOS_TIMER_INT(void)
-#define XT_RTOS_TIMER_INT   _frxt_timer_int
-#define XT_TICK_PER_SEC     configTICK_RATE_HZ
-
-/*
-Return in a15 the base address of the co-processor state save area for the 
-thread that triggered a co-processor exception, or 0 if no thread was running.
-The state save area is structured as defined in xtensa_context.h and has size 
-XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
-in interrupt handlers or the RTOS kernel. May only be called from assembly code
-and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 
-The implementation may use only a2-4, a15 (all other regs must be preserved).
-*/
-// void* XT_RTOS_CP_STATE(void)
-#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
-
-
-/*******************************************************************************
-
-HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
-
-This Xtensa RTOS port provides hooks for dynamically installing exception
-and interrupt handlers to facilitate automated testing where each test
-case can install its own handler for user exceptions and each interrupt
-priority (level). This consists of an array of function pointers indexed
-by interrupt priority, with index 0 being the user exception handler hook.
-Each entry in the array is initially 0, and may be replaced by a function 
-pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
-
-The handler for low and medium priority obeys ABI conventions so may be coded
-in C. For the exception handler, the cause is the contents of the EXCCAUSE
-reg, and the result is -1 if handled, else the cause (still needs handling).
-For interrupt handlers, the cause is a mask of pending enabled interrupts at
-that level, and the result is the same mask with the bits for the handled
-interrupts cleared (those not cleared still need handling). This allows a test
-case to either pre-handle or override the default handling for the exception
-or interrupt level (see xtensa_vectors.S).
-
-High priority handlers (including NMI) must be coded in assembly, are always
-called by 'call0' regardless of ABI, must preserve all registers except a0,
-and must not use or modify the interrupted stack. The hook argument 'cause'
-is not passed and the result is ignored, so as not to burden the caller with
-saving and restoring a2 (it assumes only one interrupt per level - see the
-discussion in high priority interrupts in xtensa_vectors.S). The handler
-therefore should be coded to prototype 'void h(void)' even though it plugs
-into an array of handlers of prototype 'unsigned h(unsigned)'.
-
-To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
-
-*******************************************************************************/
-
-#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
-
-#ifndef __ASSEMBLER__
-typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
-extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
-#endif
-
-
-/*******************************************************************************
-
-CONVENIENCE INCLUSIONS.
-
-Ensures RTOS specific files need only include this one Xtensa-generic header.
-These headers are included last so they can use the RTOS definitions above.
-
-*******************************************************************************/
-
-#include    "xtensa_context.h"
-
-#ifdef XT_RTOS_TIMER_INT
-#include    "xtensa_timer.h"
-#endif
-
-
-/*******************************************************************************
-
-Xtensa Port Version.
-
-*******************************************************************************/
-
-#define XTENSA_PORT_VERSION             1.4.2
-#define XTENSA_PORT_VERSION_STRING      "1.4.2"
-
-#endif /* XTENSA_RTOS_H */
-
diff --git a/tools/sdk/include/freertos/freertos/xtensa_timer.h b/tools/sdk/include/freertos/freertos/xtensa_timer.h
deleted file mode 100644
index fa4f96098c0..00000000000
--- a/tools/sdk/include/freertos/freertos/xtensa_timer.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-        XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
-
-This header contains definitions and macros for use primarily by Xtensa
-RTOS assembly coded source files. It includes and uses the Xtensa hardware
-abstraction layer (HAL) to deal with config specifics. It may also be
-included in C source files.
-
-User may edit to modify timer selection and to specify clock frequency and
-tick duration to match timer interrupt to the real-time tick duration.
-
-If the RTOS has no timer interrupt, then there is no tick timer and the
-clock frequency is irrelevant, so all of these macros are left undefined
-and the Xtensa core configuration need not have a timer.
-
-*******************************************************************************/
-
-#ifndef XTENSA_TIMER_H
-#define XTENSA_TIMER_H
-
-#ifdef __ASSEMBLER__
-#include    <xtensa/coreasm.h>
-#endif
-
-#include    <xtensa/corebits.h>
-#include    <xtensa/config/system.h>
-
-#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
-
-#include    "FreeRTOSConfig.h"
-
-/*
-Select timer to use for periodic tick, and determine its interrupt number 
-and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
-in which case its validity is checked (it must exist in this core and must 
-not be on a high priority interrupt - an error will be reported in invalid).
-Otherwise select the first low or medium priority interrupt timer available.
-*/
-#if XCHAL_NUM_TIMERS == 0
-
-  #error "This Xtensa configuration is unsupported, it has no timers."
-
-#else
-
-#ifndef XT_TIMER_INDEX
-  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    3
-    #endif
-  #endif
-  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    2
-    #endif
-  #endif
-  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    1
-    #endif
-  #endif
-  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    0
-    #endif
-  #endif
-#endif
-#ifndef XT_TIMER_INDEX
-  #error "There is no suitable timer in this Xtensa configuration."
-#endif
-
-#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
-#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
-#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
-#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
-
-#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
-  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
-#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
-  #error "The timer interrupt cannot be high priority (use medium or low)."
-#endif
-
-#endif /* XCHAL_NUM_TIMERS */
-
-/*
-Set processor clock frequency, used to determine clock divisor for timer tick.
-User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
-If using a supported board via the board-independent API defined in xtbsp.h,
-this may be left undefined and frequency and tick divisor will be computed 
-and cached during run-time initialization.
-
-NOTE ON SIMULATOR:
-Under the Xtensa instruction set simulator, the frequency can only be estimated 
-because it depends on the speed of the host and the version of the simulator.
-Also because it runs much slower than hardware, it is not possible to achieve
-real-time performance for most applications under the simulator. A frequency
-too low does not allow enough time between timer interrupts, starving threads.
-To obtain a more convenient but non-real-time tick duration on the simulator, 
-compile with xt-xcc option "-DXT_SIMULATOR".
-Adjust this frequency to taste (it's not real-time anyway!).
-*/
-#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
-#define XT_CLOCK_FREQ       configCPU_CLOCK_HZ
-#endif
-
-#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
-  #error "XT_CLOCK_FREQ must be defined for the target platform."
-#endif
-
-/*
-Default number of timer "ticks" per second (default 100 for 10ms tick).
-RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
-User may redefine this to an optimal value for the application, either by
-editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
-"-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
-*/
-#ifndef XT_TICK_PER_SEC
-#define XT_TICK_PER_SEC    configTICK_RATE_HZ        /* 10 ms tick = 100 ticks per second */
-#endif
-
-/*
-Derivation of clock divisor for timer tick and interrupt (one per tick).
-*/
-#ifdef XT_CLOCK_FREQ
-#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
-#endif
-
-#ifndef __ASSEMBLER__
-extern unsigned _xt_tick_divisor;
-extern void     _xt_tick_divisor_init(void);
-#endif
-
-#endif  /* XTENSA_TIMER_H */
-
diff --git a/tools/sdk/include/heap/esp_heap_alloc_caps.h b/tools/sdk/include/heap/esp_heap_alloc_caps.h
deleted file mode 100644
index 7e6e25d6a85..00000000000
--- a/tools/sdk/include/heap/esp_heap_alloc_caps.h
+++ /dev/null
@@ -1,35 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-#warning "This header is deprecated, please use functions defined in esp_heap_caps.h instead."
-#include "esp_heap_caps.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Deprecated FreeRTOS-style esp_heap_alloc_caps.h functions follow */
-
-/* Please use heap_caps_malloc() instead of this function */
-void *pvPortMallocCaps(size_t xWantedSize, uint32_t caps) asm("heap_caps_malloc") __attribute__((deprecated));
-
-/* Please use heap_caps_get_minimum_free_size() instead of this function */
-size_t xPortGetMinimumEverFreeHeapSizeCaps( uint32_t caps ) asm("heap_caps_get_minimum_free_size") __attribute__((deprecated));
-
-/* Please use heap_caps_get_free_size() instead of this function */
-size_t xPortGetFreeHeapSizeCaps( uint32_t caps ) asm("heap_caps_get_free_size") __attribute__((deprecated));
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/heap/esp_heap_caps.h b/tools/sdk/include/heap/esp_heap_caps.h
deleted file mode 100644
index 5a7aa6bc2f3..00000000000
--- a/tools/sdk/include/heap/esp_heap_caps.h
+++ /dev/null
@@ -1,315 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include <stdint.h>
-#include <stdlib.h>
-#include "multi_heap.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Flags to indicate the capabilities of the various memory systems
- */
-#define MALLOC_CAP_EXEC             (1<<0)  ///< Memory must be able to run executable code
-#define MALLOC_CAP_32BIT            (1<<1)  ///< Memory must allow for aligned 32-bit data accesses
-#define MALLOC_CAP_8BIT             (1<<2)  ///< Memory must allow for 8/16/...-bit data accesses
-#define MALLOC_CAP_DMA              (1<<3)  ///< Memory must be able to accessed by DMA
-#define MALLOC_CAP_PID2             (1<<4)  ///< Memory must be mapped to PID2 memory space (PIDs are not currently used)
-#define MALLOC_CAP_PID3             (1<<5)  ///< Memory must be mapped to PID3 memory space (PIDs are not currently used)
-#define MALLOC_CAP_PID4             (1<<6)  ///< Memory must be mapped to PID4 memory space (PIDs are not currently used)
-#define MALLOC_CAP_PID5             (1<<7)  ///< Memory must be mapped to PID5 memory space (PIDs are not currently used)
-#define MALLOC_CAP_PID6             (1<<8)  ///< Memory must be mapped to PID6 memory space (PIDs are not currently used)
-#define MALLOC_CAP_PID7             (1<<9)  ///< Memory must be mapped to PID7 memory space (PIDs are not currently used)
-#define MALLOC_CAP_SPIRAM           (1<<10) ///< Memory must be in SPI RAM
-#define MALLOC_CAP_INTERNAL         (1<<11) ///< Memory must be internal; specifically it should not disappear when flash/spiram cache is switched off
-#define MALLOC_CAP_DEFAULT          (1<<12) ///< Memory can be returned in a non-capability-specific memory allocation (e.g. malloc(), calloc()) call
-#define MALLOC_CAP_INVALID          (1<<31) ///< Memory can't be used / list end marker
-
-/**
- * @brief Allocate a chunk of memory which has the given capabilities
- *
- * Equivalent semantics to libc malloc(), for capability-aware memory.
- *
- * In IDF, ``malloc(p)`` is equivalent to ``heap_caps_malloc(p, MALLOC_CAP_8BIT)``.
- *
- * @param size Size, in bytes, of the amount of memory to allocate
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory to be returned
- *
- * @return A pointer to the memory allocated on success, NULL on failure
- */
-void *heap_caps_malloc(size_t size, uint32_t caps);
-
-
-/**
- * @brief Free memory previously allocated via heap_caps_malloc() or heap_caps_realloc().
- *
- * Equivalent semantics to libc free(), for capability-aware memory.
- *
- *  In IDF, ``free(p)`` is equivalent to ``heap_caps_free(p)``.
- *
- * @param ptr Pointer to memory previously returned from heap_caps_malloc() or heap_caps_realloc(). Can be NULL.
- */
-void heap_caps_free( void *ptr);
-
-/**
- * @brief Reallocate memory previously allocated via heap_caps_malloc() or heap_caps_realloc().
- *
- * Equivalent semantics to libc realloc(), for capability-aware memory.
- *
- * In IDF, ``realloc(p, s)`` is equivalent to ``heap_caps_realloc(p, s, MALLOC_CAP_8BIT)``.
- *
- * 'caps' parameter can be different to the capabilities that any original 'ptr' was allocated with. In this way,
- * realloc can be used to "move" a buffer if necessary to ensure it meets a new set of capabilities.
- *
- * @param ptr Pointer to previously allocated memory, or NULL for a new allocation.
- * @param size Size of the new buffer requested, or 0 to free the buffer.
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory desired for the new allocation.
- *
- * @return Pointer to a new buffer of size 'size' with capabilities 'caps', or NULL if allocation failed.
- */
-void *heap_caps_realloc( void *ptr, size_t size, int caps);
-
-/**
- * @brief Allocate a chunk of memory which has the given capabilities. The initialized value in the memory is set to zero.
- *
- * Equivalent semantics to libc calloc(), for capability-aware memory.
- *
- * In IDF, ``calloc(p)`` is equivalent to ``heap_caps_calloc(p, MALLOC_CAP_8BIT)``.
- *
- * @param n    Number of continuing chunks of memory to allocate
- * @param size Size, in bytes, of a chunk of memory to allocate
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory to be returned
- *
- * @return A pointer to the memory allocated on success, NULL on failure
- */
-void *heap_caps_calloc(size_t n, size_t size, uint32_t caps);
-
-/**
- * @brief Get the total free size of all the regions that have the given capabilities
- *
- * This function takes all regions capable of having the given capabilities allocated in them
- * and adds up the free space they have.
- *
- * Note that because of heap fragmentation it is probably not possible to allocate a single block of memory
- * of this size. Use heap_caps_get_largest_free_block() for this purpose.
-
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory
- *
- * @return Amount of free bytes in the regions
- */
-size_t heap_caps_get_free_size( uint32_t caps );
-
-
-/**
- * @brief Get the total minimum free memory of all regions with the given capabilities
- *
- * This adds all the low water marks of the regions capable of delivering the memory
- * with the given capabilities.
- *
- * Note the result may be less than the global all-time minimum available heap of this kind, as "low water marks" are
- * tracked per-region. Individual regions' heaps may have reached their "low water marks" at different points in time. However
- * this result still gives a "worst case" indication for all-time minimum free heap.
- *
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory
- *
- * @return Amount of free bytes in the regions
- */
-size_t heap_caps_get_minimum_free_size( uint32_t caps );
-
-/**
- * @brief Get the largest free block of memory able to be allocated with the given capabilities.
- *
- * Returns the largest value of ``s`` for which ``heap_caps_malloc(s, caps)`` will succeed.
- *
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory
- *
- * @return Size of largest free block in bytes.
- */
-size_t heap_caps_get_largest_free_block( uint32_t caps );
-
-
-/**
- * @brief Get heap info for all regions with the given capabilities.
- *
- * Calls multi_heap_info() on all heaps which share the given capabilities.  The information returned is an aggregate
- * across all matching heaps.  The meanings of fields are the same as defined for multi_heap_info_t, except that
- * ``minimum_free_bytes`` has the same caveats described in heap_caps_get_minimum_free_size().
- *
- * @param info        Pointer to a structure which will be filled with relevant
- *                    heap metadata.
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory
- *
- */
-void heap_caps_get_info( multi_heap_info_t *info, uint32_t caps );
-
-
-/**
- * @brief Print a summary of all memory with the given capabilities.
- *
- * Calls multi_heap_info on all heaps which share the given capabilities, and
- * prints a two-line summary for each, then a total summary.
- *
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory
- *
- */
-void heap_caps_print_heap_info( uint32_t caps );
-
-/**
- * @brief Check integrity of all heap memory in the system.
- *
- * Calls multi_heap_check on all heaps. Optionally print errors if heaps are corrupt.
- *
- * Calling this function is equivalent to calling heap_caps_check_integrity
- * with the caps argument set to MALLOC_CAP_INVALID.
- *
- * @param print_errors Print specific errors if heap corruption is found.
- *
- * @return True if all heaps are valid, False if at least one heap is corrupt.
- */
-bool heap_caps_check_integrity_all(bool print_errors);
-
-/**
- * @brief Check integrity of all heaps with the given capabilities.
- *
- * Calls multi_heap_check on all heaps which share the given capabilities. Optionally
- * print errors if the heaps are corrupt.
- *
- * See also heap_caps_check_integrity_all to check all heap memory
- * in the system and heap_caps_check_integrity_addr to check memory
- * around a single address.
- *
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory
- * @param print_errors Print specific errors if heap corruption is found.
- *
- * @return True if all heaps are valid, False if at least one heap is corrupt.
- */
-bool heap_caps_check_integrity(uint32_t caps, bool print_errors);
-
-/**
- * @brief Check integrity of heap memory around a given address.
- *
- * This function can be used to check the integrity of a single region of heap memory,
- * which contains the given address.
- *
- * This can be useful if debugging heap integrity for corruption at a known address,
- * as it has a lower overhead than checking all heap regions. Note that if the corrupt
- * address moves around between runs (due to timing or other factors) then this approach
- * won't work and you should call heap_caps_check_integrity or
- * heap_caps_check_integrity_all instead.
- *
- * @note The entire heap region around the address is checked, not only the adjacent
- * heap blocks.
- *
- * @param addr Address in memory. Check for corruption in region containing this address.
- * @param print_errors Print specific errors if heap corruption is found.
- *
- * @return True if the heap containing the specified address is valid,
- * False if at least one heap is corrupt or the address doesn't belong to a heap region.
- */
-bool heap_caps_check_integrity_addr(intptr_t addr, bool print_errors);
-
-/**
- * @brief Enable malloc() in external memory and set limit below which 
- *        malloc() attempts are placed in internal memory.
- *
- * When external memory is in use, the allocation strategy is to initially try to
- * satisfy smaller allocation requests with internal memory and larger requests
- * with external memory. This sets the limit between the two, as well as generally
- * enabling allocation in external memory.
- *
- * @param limit       Limit, in bytes.
- */
-void heap_caps_malloc_extmem_enable(size_t limit);
-
-/**
- * @brief Allocate a chunk of memory as preference in decreasing order.
- *
- * @attention The variable parameters are bitwise OR of MALLOC_CAP_* flags indicating the type of memory.
- *            This API prefers to allocate memory with the first parameter. If failed, allocate memory with
- *            the next parameter. It will try in this order until allocating a chunk of memory successfully
- *            or fail to allocate memories with any of the parameters.
- *
- * @param size Size, in bytes, of the amount of memory to allocate
- * @param num Number of variable paramters
- *
- * @return A pointer to the memory allocated on success, NULL on failure
- */
-void *heap_caps_malloc_prefer( size_t size, size_t num, ... );
-
-/**
- * @brief Allocate a chunk of memory as preference in decreasing order.
- *
- * @param ptr Pointer to previously allocated memory, or NULL for a new allocation.
- * @param size Size of the new buffer requested, or 0 to free the buffer.
- * @param num Number of variable paramters
- *
- * @return Pointer to a new buffer of size 'size', or NULL if allocation failed.
- */
-void *heap_caps_realloc_prefer( void *ptr, size_t size, size_t num, ... );
-
-/**
- * @brief Allocate a chunk of memory as preference in decreasing order.
- *
- * @param n    Number of continuing chunks of memory to allocate
- * @param size Size, in bytes, of a chunk of memory to allocate
- * @param num  Number of variable paramters
- *
- * @return A pointer to the memory allocated on success, NULL on failure
- */
-void *heap_caps_calloc_prefer( size_t n, size_t size, size_t num, ... );
-
-/**
- * @brief Dump the full structure of all heaps with matching capabilities.
- *
- * Prints a large amount of output to serial (because of locking limitations,
- * the output bypasses stdout/stderr). For each (variable sized) block
- * in each matching heap, the following output is printed on a single line:
- *
- * - Block address (the data buffer returned by malloc is 4 bytes after this
- *   if heap debugging is set to Basic, or 8 bytes otherwise).
- * - Data size (the data size may be larger than the size requested by malloc,
- *   either due to heap fragmentation or because of heap debugging level).
- * - Address of next block in the heap.
- * - If the block is free, the address of the next free block is also printed.
- *
- * @param caps        Bitwise OR of MALLOC_CAP_* flags indicating the type
- *                    of memory
- */
-void heap_caps_dump(uint32_t caps);
-
-/**
- * @brief Dump the full structure of all heaps.
- *
- * Covers all registered heaps. Prints a large amount of output to serial.
- *
- * Output is the same as for heap_caps_dump.
- *
- */
-void heap_caps_dump_all();
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/heap/esp_heap_caps_init.h b/tools/sdk/include/heap/esp_heap_caps_init.h
deleted file mode 100644
index 3ae6b8e4fc4..00000000000
--- a/tools/sdk/include/heap/esp_heap_caps_init.h
+++ /dev/null
@@ -1,92 +0,0 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include "esp_err.h"
-#include "esp_heap_caps.h"
-#include "soc/soc_memory_layout.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Initialize the capability-aware heap allocator.
- *
- * This is called once in the IDF startup code. Do not call it
- * at other times.
- */
-void heap_caps_init();
-
-/**
- * @brief Enable heap(s) in memory regions where the startup stacks are located.
- *
- * On startup, the pro/app CPUs have a certain memory region they use as stack, so we
- * cannot do allocations in the regions these stack frames are. When FreeRTOS is
- * completely started, they do not use that memory anymore and heap(s) there can
- * be enabled.
- */
-void heap_caps_enable_nonos_stack_heaps();
-
-/**
- * @brief Add a region of memory to the collection of heaps at runtime.
- *
- * Most memory regions are defined in soc_memory_layout.c for the SoC,
- * and are registered via heap_caps_init(). Some regions can't be used
- * immediately and are later enabled via heap_caps_enable_nonos_stack_heaps().
- *
- * Call this function to add a region of memory to the heap at some later time.
- *
- * This function does not consider any of the "reserved" regions or other data in soc_memory_layout, caller needs to
- * consider this themselves.
- *
- * All memory within the region specified by start & end parameters must be otherwise unused.
- *
- * The capabilities of the newly registered memory will be determined by the start address, as looked up in the regions
- * specified in soc_memory_layout.c.
- *
- * Use heap_caps_add_region_with_caps() to register a region with custom capabilities.
- *
- * @param start Start address of new region.
- * @param end End address of new region.
- *
- * @return ESP_OK on success, ESP_ERR_INVALID_ARG if a parameter is invalid, ESP_ERR_NOT_FOUND if the
- * specified start address doesn't reside in a known region, or any error returned by heap_caps_add_region_with_caps().
- */
-esp_err_t heap_caps_add_region(intptr_t start, intptr_t end);
-
-
-/**
- * @brief Add a region of memory to the collection of heaps at runtime, with custom capabilities.
- *
- * Similar to heap_caps_add_region(), only custom memory capabilities are specified by the caller.
- *
- * @param caps Ordered array of capability masks for the new region, in order of priority. Must have length
- * SOC_MEMORY_TYPE_NO_PRIOS. Does not need to remain valid after the call returns.
- * @param start Start address of new region.
- * @param end End address of new region.
- *
- * @return 
- *         - ESP_OK on success
- *         - ESP_ERR_INVALID_ARG if a parameter is invalid
- *         - ESP_ERR_NO_MEM if no memory to register new heap.
- *         - ESP_ERR_INVALID_SIZE if the memory region is too small to fit a heap
- *         - ESP_FAIL if region overlaps the start and/or end of an existing region
- */
-esp_err_t heap_caps_add_region_with_caps(const uint32_t caps[], intptr_t start, intptr_t end);
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/heap/esp_heap_task_info.h b/tools/sdk/include/heap/esp_heap_task_info.h
deleted file mode 100644
index fca9a43ba66..00000000000
--- a/tools/sdk/include/heap/esp_heap_task_info.h
+++ /dev/null
@@ -1,98 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#ifdef CONFIG_HEAP_TASK_TRACKING
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// This macro controls how much space is provided for partitioning the per-task
-// heap allocation info according to one or more sets of heap capabilities.
-#define NUM_HEAP_TASK_CAPS 4
-
-/** @brief Structure to collect per-task heap allocation totals partitioned by selected caps */
-typedef struct {
-    TaskHandle_t task;                ///< Task to which these totals belong
-    size_t size[NUM_HEAP_TASK_CAPS];  ///< Total allocations partitioned by selected caps
-    size_t count[NUM_HEAP_TASK_CAPS]; ///< Number of blocks partitioned by selected caps
-} heap_task_totals_t;
-
-/** @brief Structure providing details about a block allocated by a task */
-typedef struct {
-    TaskHandle_t task;                ///< Task that allocated the block
-    void *address;                    ///< User address of allocated block
-    uint32_t size;                    ///< Size of the allocated block
-} heap_task_block_t;
-
-/** @brief Structure to provide parameters to heap_caps_get_per_task_info
- *
- * The 'caps' and 'mask' arrays allow partitioning the per-task heap allocation
- * totals by selected sets of heap region capabilities so that totals for
- * multiple regions can be accumulated in one scan.  The capabilities flags for
- * each region ANDed with mask[i] are compared to caps[i] in order; the
- * allocations in that region are added to totals->size[i] and totals->count[i]
- * for the first i that matches.  To collect the totals without any
- * partitioning, set mask[0] and caps[0] both to zero.  The allocation totals
- * are returned in the 'totals' array of heap_task_totals_t structs.  To allow
- * easily comparing the totals array between consecutive calls, that array can
- * be left populated from one call to the next so the order of tasks is the
- * same even if some tasks have freed their blocks or have been deleted.  The
- * number of blocks prepopulated is given by num_totals, which is updated upon
- * return.  If there are more tasks with allocations than the capacity of the
- * totals array (given by max_totals), information for the excess tasks will be
- * not be collected.  The totals array pointer can be NULL if the totals are
- * not desired.
- *
- * The 'tasks' array holds a list of handles for tasks whose block details are
- * to be returned in the 'blocks' array of heap_task_block_t structs.  If the
- * tasks array pointer is NULL, block details for all tasks will be returned up
- * to the capacity of the buffer array, given by max_blocks.  The function
- * return value tells the number of blocks filled into the array.  The blocks
- * array pointer can be NULL if block details are not desired, or max_blocks
- * can be set to zero.
- */
-typedef struct {
-    int32_t caps[NUM_HEAP_TASK_CAPS]; ///< Array of caps for partitioning task totals
-    int32_t mask[NUM_HEAP_TASK_CAPS]; ///< Array of masks under which caps must match
-    TaskHandle_t *tasks;              ///< Array of tasks whose block info is returned
-    size_t num_tasks;                 ///< Length of tasks array
-    heap_task_totals_t *totals;       ///< Array of structs to collect task totals
-    size_t *num_totals;               ///< Number of task structs currently in array
-    size_t max_totals;                ///< Capacity of array of task totals structs
-    heap_task_block_t *blocks;        ///< Array of task block details structs
-    size_t max_blocks;                ///< Capacity of array of task block info structs
-} heap_task_info_params_t;
-
-/**
- * @brief Return per-task heap allocation totals and lists of blocks.
- *
- * For each task that has allocated memory from the heap, return totals for
- * allocations within regions matching one or more sets of capabilities.
- *
- * Optionally also return an array of structs providing details about each
- * block allocated by one or more requested tasks, or by all tasks.
- *
- * @param params Structure to hold all the parameters for the function
- * (@see heap_task_info_params_t).
- * @return Number of block detail structs returned (@see heap_task_block_t).
- */
-extern size_t heap_caps_get_per_task_info(heap_task_info_params_t *params);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // CONFIG_HEAP_TASK_TRACKING
diff --git a/tools/sdk/include/heap/esp_heap_trace.h b/tools/sdk/include/heap/esp_heap_trace.h
deleted file mode 100644
index 5573d5e5abb..00000000000
--- a/tools/sdk/include/heap/esp_heap_trace.h
+++ /dev/null
@@ -1,144 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include "sdkconfig.h"
-#include <stdint.h>
-#include <esp_err.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(CONFIG_HEAP_TRACING) && !defined(HEAP_TRACE_SRCFILE)
-#warning "esp_heap_trace.h is included but heap tracing is disabled in menuconfig, functions are no-ops"
-#endif
-
-#ifndef CONFIG_HEAP_TRACING_STACK_DEPTH
-#define CONFIG_HEAP_TRACING_STACK_DEPTH 0
-#endif
-
-typedef enum {
-    HEAP_TRACE_ALL,
-    HEAP_TRACE_LEAKS,
-} heap_trace_mode_t;
-
-/**
- * @brief Trace record data type. Stores information about an allocated region of memory.
- */
-typedef struct {
-    uint32_t ccount; ///< CCOUNT of the CPU when the allocation was made. LSB (bit value 1) is the CPU number (0 or 1).
-    void *address;   ///< Address which was allocated
-    size_t size;     ///< Size of the allocation
-    void *alloced_by[CONFIG_HEAP_TRACING_STACK_DEPTH]; ///< Call stack of the caller which allocated the memory.
-    void *freed_by[CONFIG_HEAP_TRACING_STACK_DEPTH];   ///< Call stack of the caller which freed the memory (all zero if not freed.)
-} heap_trace_record_t;
-
-/**
- * @brief Initialise heap tracing in standalone mode.
- * @note Standalone mode is the only mode currently supported.
- *
- * This function must be called before any other heap tracing functions.
- *
- * To disable heap tracing and allow the buffer to be freed, stop tracing and then call heap_trace_init_standalone(NULL, 0);
- *
- * @param record_buffer Provide a buffer to use for heap trace data. Must remain valid any time heap tracing is enabled, meaning
- * it must be allocated from internal memory not in PSRAM.
- * @param num_records Size of the heap trace buffer, as number of record structures.
- * @return
- *  - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig.
- *  - ESP_ERR_INVALID_STATE Heap tracing is currently in progress.
- *  - ESP_OK Heap tracing initialised successfully.
- */
-esp_err_t heap_trace_init_standalone(heap_trace_record_t *record_buffer, size_t num_records);
-
-/**
- * @brief Start heap tracing. All heap allocations & frees will be traced, until heap_trace_stop() is called.
- *
- * @note heap_trace_init_standalone() must be called to provide a valid buffer, before this function is called.
- *
- * @note Calling this function while heap tracing is running will reset the heap trace state and continue tracing.
- *
- * @param mode Mode for tracing.
- * - HEAP_TRACE_ALL means all heap allocations and frees are traced.
- * - HEAP_TRACE_LEAKS means only suspected memory leaks are traced. (When memory is freed, the record is removed from the trace buffer.)
- * @return
- * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig.
- * - ESP_ERR_INVALID_STATE A non-zero-length buffer has not been set via heap_trace_init_standalone().
- * - ESP_OK Tracing is started.
- */
-esp_err_t heap_trace_start(heap_trace_mode_t mode);
-
-/**
- * @brief Stop heap tracing.
- *
- * @return
- * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig.
- * - ESP_ERR_INVALID_STATE Heap tracing was not in progress.
- * - ESP_OK Heap tracing stopped..
- */
-esp_err_t heap_trace_stop(void);
-
-/**
- * @brief Resume heap tracing which was previously stopped.
- *
- * Unlike heap_trace_start(), this function does not clear the
- * buffer of any pre-existing trace records.
- *
- * The heap trace mode is the same as when heap_trace_start() was
- * last called (or HEAP_TRACE_ALL if heap_trace_start() was never called).
- *
- * @return
- * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig.
- * - ESP_ERR_INVALID_STATE Heap tracing was already started.
- * - ESP_OK Heap tracing resumed.
- */
-esp_err_t heap_trace_resume(void);
-
-/**
- * @brief Return number of records in the heap trace buffer
- *
- * It is safe to call this function while heap tracing is running.
- */
-size_t heap_trace_get_count(void);
-
-/**
- * @brief Return a raw record from the heap trace buffer
- *
- * @note It is safe to call this function while heap tracing is running, however in HEAP_TRACE_LEAK mode record indexing may
- * skip entries unless heap tracing is stopped first.
- *
- * @param index Index (zero-based) of the record to return.
- * @param[out] record Record where the heap trace record will be copied.
- * @return
- * - ESP_ERR_NOT_SUPPORTED Project was compiled without heap tracing enabled in menuconfig.
- * - ESP_ERR_INVALID_STATE Heap tracing was not initialised.
- * - ESP_ERR_INVALID_ARG Index is out of bounds for current heap trace record count.
- * - ESP_OK Record returned successfully.
- */
-esp_err_t heap_trace_get(size_t index, heap_trace_record_t *record);
-
-/**
- * @brief Dump heap trace record data to stdout
- *
- * @note It is safe to call this function while heap tracing is running, however in HEAP_TRACE_LEAK mode the dump may skip
- * entries unless heap tracing is stopped first.
- *
- *
- */
-void heap_trace_dump(void);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/heap/multi_heap.h b/tools/sdk/include/heap/multi_heap.h
deleted file mode 100644
index dbd0cae8649..00000000000
--- a/tools/sdk/include/heap/multi_heap.h
+++ /dev/null
@@ -1,171 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-#include <stdint.h>
-#include <stdlib.h>
-#include <stdbool.h>
-
-/* multi_heap is a heap implementation for handling multiple
-   heterogenous heaps in a single program.
-
-   Any contiguous block of memory can be registered as a heap.
-*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @brief Opaque handle to a registered heap */
-typedef struct multi_heap_info *multi_heap_handle_t;
-
-/** @brief malloc() a buffer in a given heap
- *
- * Semantics are the same as standard malloc(), only the returned buffer will be allocated in the specified heap.
- *
- * @param heap Handle to a registered heap.
- * @param size Size of desired buffer.
- *
- * @return Pointer to new memory, or NULL if allocation fails.
- */
-void *multi_heap_malloc(multi_heap_handle_t heap, size_t size);
-
-/** @brief free() a buffer in a given heap.
- *
- * Semantics are the same as standard free(), only the argument 'p' must be NULL or have been allocated in the specified heap.
- *
- * @param heap Handle to a registered heap.
- * @param p NULL, or a pointer previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap.
- */
-void multi_heap_free(multi_heap_handle_t heap, void *p);
-
-/** @brief realloc() a buffer in a given heap.
- *
- * Semantics are the same as standard realloc(), only the argument 'p' must be NULL or have been allocated in the specified heap.
- *
- * @param heap Handle to a registered heap.
- * @param p NULL, or a pointer previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap.
- * @param size Desired new size for buffer.
- *
- * @return New buffer of 'size' containing contents of 'p', or NULL if reallocation failed.
- */
-void *multi_heap_realloc(multi_heap_handle_t heap, void *p, size_t size);
-
-
-/** @brief Return the size that a particular pointer was allocated with.
- *
- * @param heap Handle to a registered heap.
- * @param p Pointer, must have been previously returned from multi_heap_malloc() or multi_heap_realloc() for the same heap.
- *
- * @return Size of the memory allocated at this block. May be more than the original size argument, due
- * to padding and minimum block sizes.
- */
-size_t multi_heap_get_allocated_size(multi_heap_handle_t heap, void *p);
-
-
-/** @brief Register a new heap for use
- *
- * This function initialises a heap at the specified address, and returns a handle for future heap operations.
- *
- * There is no equivalent function for deregistering a heap - if all blocks in the heap are free, you can immediately start using the memory for other purposes.
- *
- * @param start Start address of the memory to use for a new heap.
- * @param size Size (in bytes) of the new heap.
- *
- * @return Handle of a new heap ready for use, or NULL if the heap region was too small to be initialised.
- */
-multi_heap_handle_t multi_heap_register(void *start, size_t size);
-
-
-/** @brief Associate a private lock pointer with a heap
- *
- * The lock argument is supplied to the MULTI_HEAP_LOCK() and MULTI_HEAP_UNLOCK() macros, defined in multi_heap_platform.h.
- *
- * The lock in question must be recursive.
- *
- * When the heap is first registered, the associated lock is NULL.
- *
- * @param heap Handle to a registered heap.
- * @param lock Optional pointer to a locking structure to associate with this heap.
- */
-void multi_heap_set_lock(multi_heap_handle_t heap, void* lock);
-
-/** @brief Dump heap information to stdout
- *
- * For debugging purposes, this function dumps information about every block in the heap to stdout.
- *
- * @param heap Handle to a registered heap.
- */
-void multi_heap_dump(multi_heap_handle_t heap);
-
-/** @brief Check heap integrity
- *
- * Walks the heap and checks all heap data structures are valid. If any errors are detected, an error-specific message
- * can be optionally printed to stderr. Print behaviour can be overriden at compile time by defining
- * MULTI_CHECK_FAIL_PRINTF in multi_heap_platform.h.
- *
- * @param heap Handle to a registered heap.
- * @param print_errors If true, errors will be printed to stderr.
- * @return true if heap is valid, false otherwise.
- */
-bool multi_heap_check(multi_heap_handle_t heap, bool print_errors);
-
-/** @brief Return free heap size
- *
- * Returns the number of bytes available in the heap.
- *
- * Equivalent to the total_free_bytes member returned by multi_heap_get_heap_info().
- *
- * Note that the heap may be fragmented, so the actual maximum size for a single malloc() may be lower. To know this
- * size, see the largest_free_block member returned by multi_heap_get_heap_info().
- *
- * @param heap Handle to a registered heap.
- * @return Number of free bytes.
- */
-size_t multi_heap_free_size(multi_heap_handle_t heap);
-
-/** @brief Return the lifetime minimum free heap size
- *
- * Equivalent to the minimum_free_bytes member returned by multi_heap_get_info().
- *
- * Returns the lifetime "low water mark" of possible values returned from multi_free_heap_size(), for the specified
- * heap.
- *
- * @param heap Handle to a registered heap.
- * @return Number of free bytes.
- */
-size_t multi_heap_minimum_free_size(multi_heap_handle_t heap);
-
-/** @brief Structure to access heap metadata via multi_heap_get_info */
-typedef struct {
-    size_t total_free_bytes;      ///<  Total free bytes in the heap. Equivalent to multi_free_heap_size().
-    size_t total_allocated_bytes; ///<  Total bytes allocated to data in the heap.
-    size_t largest_free_block;    ///<  Size of largest free block in the heap. This is the largest malloc-able size.
-    size_t minimum_free_bytes;    ///<  Lifetime minimum free heap size. Equivalent to multi_minimum_free_heap_size().
-    size_t allocated_blocks;      ///<  Number of (variable size) blocks allocated in the heap.
-    size_t free_blocks;           ///<  Number of (variable size) free blocks in the heap.
-    size_t total_blocks;          ///<  Total number of (variable size) blocks in the heap.
-} multi_heap_info_t;
-
-/** @brief Return metadata about a given heap
- *
- * Fills a multi_heap_info_t structure with information about the specified heap.
- *
- * @param heap Handle to a registered heap.
- * @param info Pointer to a structure to fill with heap metadata.
- */
-void multi_heap_get_info(multi_heap_handle_t heap, multi_heap_info_t *info);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/idf_test/idf_performance.h b/tools/sdk/include/idf_test/idf_performance.h
deleted file mode 100644
index ad60009f016..00000000000
--- a/tools/sdk/include/idf_test/idf_performance.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#pragma once
-
-/* declare the performance here */
-#define IDF_PERFORMANCE_MAX_HTTPS_REQUEST_BIN_SIZE                              800
-#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP                     200
-#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_PSRAM               300
-#define IDF_PERFORMANCE_MAX_FREERTOS_SPINLOCK_CYCLES_PER_OP_UNICORE             130
-#define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL                         1000
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                            30
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA                     27
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                               15
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA                        15
-/* Due to code size & linker layout differences interacting with cache, VFS
-   microbenchmark currently runs slower with PSRAM enabled. */
-#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME                           20000
-#define IDF_PERFORMANCE_MAX_VFS_OPEN_WRITE_CLOSE_TIME_PSRAM                     25000
-// throughput performance by iperf
-#define IDF_PERFORMANCE_MIN_TCP_RX_THROUGHPUT                                   50
-#define IDF_PERFORMANCE_MIN_TCP_TX_THROUGHPUT                                   40
-#define IDF_PERFORMANCE_MIN_UDP_RX_THROUGHPUT                                   80
-#define IDF_PERFORMANCE_MIN_UDP_TX_THROUGHPUT                                   50
-// events dispatched per second by event loop library
-#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH                                      25000
-#define IDF_PERFORMANCE_MIN_EVENT_DISPATCH_PSRAM                                21000
-// esp_sha() time to process 32KB of input data from RAM
-#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA1_32KB 5000
-#define IDF_PERFORMANCE_MAX_ESP32_TIME_SHA512_32KB 4500
diff --git a/tools/sdk/include/jsmn/jsmn.h b/tools/sdk/include/jsmn/jsmn.h
deleted file mode 100644
index 1df808e3946..00000000000
--- a/tools/sdk/include/jsmn/jsmn.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright (c) 2010 Serge A. Zaitsev
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/**
- * @file jsmn.h
- * @brief Definition of the JSMN (Jasmine) JSON parser.
- *
- * For more information on JSMN:
- * @see http://zserge.com/jsmn.html
- */
-
-#ifndef __JSMN_H_
-#define __JSMN_H_
-
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * JSON type identifier. Basic types are:
- * 	o Object
- * 	o Array
- * 	o String
- * 	o Other primitive: number, boolean (true/false) or null
- */
-typedef enum {
-	JSMN_UNDEFINED = 0,
-	JSMN_OBJECT = 1,
-	JSMN_ARRAY = 2,
-	JSMN_STRING = 3,
-	JSMN_PRIMITIVE = 4
-} jsmntype_t;
-
-enum jsmnerr {
-	/* Not enough tokens were provided */
-	JSMN_ERROR_NOMEM = -1,
-	/* Invalid character inside JSON string */
-	JSMN_ERROR_INVAL = -2,
-	/* The string is not a full JSON packet, more bytes expected */
-	JSMN_ERROR_PART = -3
-};
-
-/**
- * JSON token description.
- * @param		type	type (object, array, string etc.)
- * @param		start	start position in JSON data string
- * @param		end		end position in JSON data string
- */
-typedef struct {
-	jsmntype_t type;
-	int start;
-	int end;
-	int size;
-#ifdef JSMN_PARENT_LINKS
-	int parent;
-#endif
-} jsmntok_t;
-
-/**
- * JSON parser. Contains an array of token blocks available. Also stores
- * the string being parsed now and current position in that string
- */
-typedef struct {
-	unsigned int pos; /* offset in the JSON string */
-	unsigned int toknext; /* next token to allocate */
-	int toksuper; /* superior token node, e.g parent object or array */
-} jsmn_parser;
-
-/**
- * Create JSON parser over an array of tokens
- */
-void jsmn_init(jsmn_parser *parser);
-
-/**
- * Run JSON parser. It parses a JSON data string into and array of tokens, each describing
- * a single JSON object.
- */
-int jsmn_parse(jsmn_parser *parser, const char *js, size_t len,
-		jsmntok_t *tokens, unsigned int num_tokens);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __JSMN_H_ */
diff --git a/tools/sdk/include/json/cJSON.h b/tools/sdk/include/json/cJSON.h
deleted file mode 100644
index 592986b86e9..00000000000
--- a/tools/sdk/include/json/cJSON.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
-  Copyright (c) 2009-2017 Dave Gamble and cJSON contributors
-
-  Permission is hereby granted, free of charge, to any person obtaining a copy
-  of this software and associated documentation files (the "Software"), to deal
-  in the Software without restriction, including without limitation the rights
-  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-  copies of the Software, and to permit persons to whom the Software is
-  furnished to do so, subject to the following conditions:
-
-  The above copyright notice and this permission notice shall be included in
-  all copies or substantial portions of the Software.
-
-  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-  THE SOFTWARE.
-*/
-
-#ifndef cJSON__h
-#define cJSON__h
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#if !defined(__WINDOWS__) && (defined(WIN32) || defined(WIN64) || defined(_MSC_VER) || defined(_WIN32))
-#define __WINDOWS__
-#endif
-
-#ifdef __WINDOWS__
-
-/* When compiling for windows, we specify a specific calling convention to avoid issues where we are being called from a project with a different default calling convention.  For windows you have 3 define options:
-
-CJSON_HIDE_SYMBOLS - Define this in the case where you don't want to ever dllexport symbols
-CJSON_EXPORT_SYMBOLS - Define this on library build when you want to dllexport symbols (default)
-CJSON_IMPORT_SYMBOLS - Define this if you want to dllimport symbol
-
-For *nix builds that support visibility attribute, you can define similar behavior by
-
-setting default visibility to hidden by adding
--fvisibility=hidden (for gcc)
-or
--xldscope=hidden (for sun cc)
-to CFLAGS
-
-then using the CJSON_API_VISIBILITY flag to "export" the same symbols the way CJSON_EXPORT_SYMBOLS does
-
-*/
-
-#define CJSON_CDECL __cdecl
-#define CJSON_STDCALL __stdcall
-
-/* export symbols by default, this is necessary for copy pasting the C and header file */
-#if !defined(CJSON_HIDE_SYMBOLS) && !defined(CJSON_IMPORT_SYMBOLS) && !defined(CJSON_EXPORT_SYMBOLS)
-#define CJSON_EXPORT_SYMBOLS
-#endif
-
-#if defined(CJSON_HIDE_SYMBOLS)
-#define CJSON_PUBLIC(type)   type CJSON_STDCALL
-#elif defined(CJSON_EXPORT_SYMBOLS)
-#define CJSON_PUBLIC(type)   __declspec(dllexport) type CJSON_STDCALL
-#elif defined(CJSON_IMPORT_SYMBOLS)
-#define CJSON_PUBLIC(type)   __declspec(dllimport) type CJSON_STDCALL
-#endif
-#else /* !__WINDOWS__ */
-#define CJSON_CDECL
-#define CJSON_STDCALL
-
-#if (defined(__GNUC__) || defined(__SUNPRO_CC) || defined (__SUNPRO_C)) && defined(CJSON_API_VISIBILITY)
-#define CJSON_PUBLIC(type)   __attribute__((visibility("default"))) type
-#else
-#define CJSON_PUBLIC(type) type
-#endif
-#endif
-
-/* project version */
-#define CJSON_VERSION_MAJOR 1
-#define CJSON_VERSION_MINOR 7
-#define CJSON_VERSION_PATCH 12
-
-#include <stddef.h>
-
-/* cJSON Types: */
-#define cJSON_Invalid (0)
-#define cJSON_False  (1 << 0)
-#define cJSON_True   (1 << 1)
-#define cJSON_NULL   (1 << 2)
-#define cJSON_Number (1 << 3)
-#define cJSON_String (1 << 4)
-#define cJSON_Array  (1 << 5)
-#define cJSON_Object (1 << 6)
-#define cJSON_Raw    (1 << 7) /* raw json */
-
-#define cJSON_IsReference 256
-#define cJSON_StringIsConst 512
-
-/* The cJSON structure: */
-typedef struct cJSON
-{
-    /* next/prev allow you to walk array/object chains. Alternatively, use GetArraySize/GetArrayItem/GetObjectItem */
-    struct cJSON *next;
-    struct cJSON *prev;
-    /* An array or object item will have a child pointer pointing to a chain of the items in the array/object. */
-    struct cJSON *child;
-
-    /* The type of the item, as above. */
-    int type;
-
-    /* The item's string, if type==cJSON_String  and type == cJSON_Raw */
-    char *valuestring;
-    /* writing to valueint is DEPRECATED, use cJSON_SetNumberValue instead */
-    int valueint;
-    /* The item's number, if type==cJSON_Number */
-    double valuedouble;
-
-    /* The item's name string, if this item is the child of, or is in the list of subitems of an object. */
-    char *string;
-} cJSON;
-
-typedef struct cJSON_Hooks
-{
-      /* malloc/free are CDECL on Windows regardless of the default calling convention of the compiler, so ensure the hooks allow passing those functions directly. */
-      void *(CJSON_CDECL *malloc_fn)(size_t sz);
-      void (CJSON_CDECL *free_fn)(void *ptr);
-} cJSON_Hooks;
-
-typedef int cJSON_bool;
-
-/* Limits how deeply nested arrays/objects can be before cJSON rejects to parse them.
- * This is to prevent stack overflows. */
-#ifndef CJSON_NESTING_LIMIT
-#define CJSON_NESTING_LIMIT 1000
-#endif
-
-/* returns the version of cJSON as a string */
-CJSON_PUBLIC(const char*) cJSON_Version(void);
-
-/* Supply malloc, realloc and free functions to cJSON */
-CJSON_PUBLIC(void) cJSON_InitHooks(cJSON_Hooks* hooks);
-
-/* Memory Management: the caller is always responsible to free the results from all variants of cJSON_Parse (with cJSON_Delete) and cJSON_Print (with stdlib free, cJSON_Hooks.free_fn, or cJSON_free as appropriate). The exception is cJSON_PrintPreallocated, where the caller has full responsibility of the buffer. */
-/* Supply a block of JSON, and this returns a cJSON object you can interrogate. */
-CJSON_PUBLIC(cJSON *) cJSON_Parse(const char *value);
-/* ParseWithOpts allows you to require (and check) that the JSON is null terminated, and to retrieve the pointer to the final byte parsed. */
-/* If you supply a ptr in return_parse_end and parsing fails, then return_parse_end will contain a pointer to the error so will match cJSON_GetErrorPtr(). */
-CJSON_PUBLIC(cJSON *) cJSON_ParseWithOpts(const char *value, const char **return_parse_end, cJSON_bool require_null_terminated);
-
-/* Render a cJSON entity to text for transfer/storage. */
-CJSON_PUBLIC(char *) cJSON_Print(const cJSON *item);
-/* Render a cJSON entity to text for transfer/storage without any formatting. */
-CJSON_PUBLIC(char *) cJSON_PrintUnformatted(const cJSON *item);
-/* Render a cJSON entity to text using a buffered strategy. prebuffer is a guess at the final size. guessing well reduces reallocation. fmt=0 gives unformatted, =1 gives formatted */
-CJSON_PUBLIC(char *) cJSON_PrintBuffered(const cJSON *item, int prebuffer, cJSON_bool fmt);
-/* Render a cJSON entity to text using a buffer already allocated in memory with given length. Returns 1 on success and 0 on failure. */
-/* NOTE: cJSON is not always 100% accurate in estimating how much memory it will use, so to be safe allocate 5 bytes more than you actually need */
-CJSON_PUBLIC(cJSON_bool) cJSON_PrintPreallocated(cJSON *item, char *buffer, const int length, const cJSON_bool format);
-/* Delete a cJSON entity and all subentities. */
-CJSON_PUBLIC(void) cJSON_Delete(cJSON *c);
-
-/* Returns the number of items in an array (or object). */
-CJSON_PUBLIC(int) cJSON_GetArraySize(const cJSON *array);
-/* Retrieve item number "index" from array "array". Returns NULL if unsuccessful. */
-CJSON_PUBLIC(cJSON *) cJSON_GetArrayItem(const cJSON *array, int index);
-/* Get item "string" from object. Case insensitive. */
-CJSON_PUBLIC(cJSON *) cJSON_GetObjectItem(const cJSON * const object, const char * const string);
-CJSON_PUBLIC(cJSON *) cJSON_GetObjectItemCaseSensitive(const cJSON * const object, const char * const string);
-CJSON_PUBLIC(cJSON_bool) cJSON_HasObjectItem(const cJSON *object, const char *string);
-/* For analysing failed parses. This returns a pointer to the parse error. You'll probably need to look a few chars back to make sense of it. Defined when cJSON_Parse() returns 0. 0 when cJSON_Parse() succeeds. */
-CJSON_PUBLIC(const char *) cJSON_GetErrorPtr(void);
-
-/* Check if the item is a string and return its valuestring */
-CJSON_PUBLIC(char *) cJSON_GetStringValue(cJSON *item);
-
-/* These functions check the type of an item */
-CJSON_PUBLIC(cJSON_bool) cJSON_IsInvalid(const cJSON * const item);
-CJSON_PUBLIC(cJSON_bool) cJSON_IsFalse(const cJSON * const item);
-CJSON_PUBLIC(cJSON_bool) cJSON_IsTrue(const cJSON * const item);
-CJSON_PUBLIC(cJSON_bool) cJSON_IsBool(const cJSON * const item);
-CJSON_PUBLIC(cJSON_bool) cJSON_IsNull(const cJSON * const item);
-CJSON_PUBLIC(cJSON_bool) cJSON_IsNumber(const cJSON * const item);
-CJSON_PUBLIC(cJSON_bool) cJSON_IsString(const cJSON * const item);
-CJSON_PUBLIC(cJSON_bool) cJSON_IsArray(const cJSON * const item);
-CJSON_PUBLIC(cJSON_bool) cJSON_IsObject(const cJSON * const item);
-CJSON_PUBLIC(cJSON_bool) cJSON_IsRaw(const cJSON * const item);
-
-/* These calls create a cJSON item of the appropriate type. */
-CJSON_PUBLIC(cJSON *) cJSON_CreateNull(void);
-CJSON_PUBLIC(cJSON *) cJSON_CreateTrue(void);
-CJSON_PUBLIC(cJSON *) cJSON_CreateFalse(void);
-CJSON_PUBLIC(cJSON *) cJSON_CreateBool(cJSON_bool boolean);
-CJSON_PUBLIC(cJSON *) cJSON_CreateNumber(double num);
-CJSON_PUBLIC(cJSON *) cJSON_CreateString(const char *string);
-/* raw json */
-CJSON_PUBLIC(cJSON *) cJSON_CreateRaw(const char *raw);
-CJSON_PUBLIC(cJSON *) cJSON_CreateArray(void);
-CJSON_PUBLIC(cJSON *) cJSON_CreateObject(void);
-
-/* Create a string where valuestring references a string so
- * it will not be freed by cJSON_Delete */
-CJSON_PUBLIC(cJSON *) cJSON_CreateStringReference(const char *string);
-/* Create an object/arrray that only references it's elements so
- * they will not be freed by cJSON_Delete */
-CJSON_PUBLIC(cJSON *) cJSON_CreateObjectReference(const cJSON *child);
-CJSON_PUBLIC(cJSON *) cJSON_CreateArrayReference(const cJSON *child);
-
-/* These utilities create an Array of count items. */
-CJSON_PUBLIC(cJSON *) cJSON_CreateIntArray(const int *numbers, int count);
-CJSON_PUBLIC(cJSON *) cJSON_CreateFloatArray(const float *numbers, int count);
-CJSON_PUBLIC(cJSON *) cJSON_CreateDoubleArray(const double *numbers, int count);
-CJSON_PUBLIC(cJSON *) cJSON_CreateStringArray(const char **strings, int count);
-
-/* Append item to the specified array/object. */
-CJSON_PUBLIC(void) cJSON_AddItemToArray(cJSON *array, cJSON *item);
-CJSON_PUBLIC(void) cJSON_AddItemToObject(cJSON *object, const char *string, cJSON *item);
-/* Use this when string is definitely const (i.e. a literal, or as good as), and will definitely survive the cJSON object.
- * WARNING: When this function was used, make sure to always check that (item->type & cJSON_StringIsConst) is zero before
- * writing to `item->string` */
-CJSON_PUBLIC(void) cJSON_AddItemToObjectCS(cJSON *object, const char *string, cJSON *item);
-/* Append reference to item to the specified array/object. Use this when you want to add an existing cJSON to a new cJSON, but don't want to corrupt your existing cJSON. */
-CJSON_PUBLIC(void) cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item);
-CJSON_PUBLIC(void) cJSON_AddItemReferenceToObject(cJSON *object, const char *string, cJSON *item);
-
-/* Remove/Detatch items from Arrays/Objects. */
-CJSON_PUBLIC(cJSON *) cJSON_DetachItemViaPointer(cJSON *parent, cJSON * const item);
-CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromArray(cJSON *array, int which);
-CJSON_PUBLIC(void) cJSON_DeleteItemFromArray(cJSON *array, int which);
-CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObject(cJSON *object, const char *string);
-CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObjectCaseSensitive(cJSON *object, const char *string);
-CJSON_PUBLIC(void) cJSON_DeleteItemFromObject(cJSON *object, const char *string);
-CJSON_PUBLIC(void) cJSON_DeleteItemFromObjectCaseSensitive(cJSON *object, const char *string);
-
-/* Update array items. */
-CJSON_PUBLIC(void) cJSON_InsertItemInArray(cJSON *array, int which, cJSON *newitem); /* Shifts pre-existing items to the right. */
-CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemViaPointer(cJSON * const parent, cJSON * const item, cJSON * replacement);
-CJSON_PUBLIC(void) cJSON_ReplaceItemInArray(cJSON *array, int which, cJSON *newitem);
-CJSON_PUBLIC(void) cJSON_ReplaceItemInObject(cJSON *object,const char *string,cJSON *newitem);
-CJSON_PUBLIC(void) cJSON_ReplaceItemInObjectCaseSensitive(cJSON *object,const char *string,cJSON *newitem);
-
-/* Duplicate a cJSON item */
-CJSON_PUBLIC(cJSON *) cJSON_Duplicate(const cJSON *item, cJSON_bool recurse);
-/* Duplicate will create a new, identical cJSON item to the one you pass, in new memory that will
-need to be released. With recurse!=0, it will duplicate any children connected to the item.
-The item->next and ->prev pointers are always zero on return from Duplicate. */
-/* Recursively compare two cJSON items for equality. If either a or b is NULL or invalid, they will be considered unequal.
- * case_sensitive determines if object keys are treated case sensitive (1) or case insensitive (0) */
-CJSON_PUBLIC(cJSON_bool) cJSON_Compare(const cJSON * const a, const cJSON * const b, const cJSON_bool case_sensitive);
-
-
-CJSON_PUBLIC(void) cJSON_Minify(char *json);
-
-/* Helper functions for creating and adding items to an object at the same time.
- * They return the added item or NULL on failure. */
-CJSON_PUBLIC(cJSON*) cJSON_AddNullToObject(cJSON * const object, const char * const name);
-CJSON_PUBLIC(cJSON*) cJSON_AddTrueToObject(cJSON * const object, const char * const name);
-CJSON_PUBLIC(cJSON*) cJSON_AddFalseToObject(cJSON * const object, const char * const name);
-CJSON_PUBLIC(cJSON*) cJSON_AddBoolToObject(cJSON * const object, const char * const name, const cJSON_bool boolean);
-CJSON_PUBLIC(cJSON*) cJSON_AddNumberToObject(cJSON * const object, const char * const name, const double number);
-CJSON_PUBLIC(cJSON*) cJSON_AddStringToObject(cJSON * const object, const char * const name, const char * const string);
-CJSON_PUBLIC(cJSON*) cJSON_AddRawToObject(cJSON * const object, const char * const name, const char * const raw);
-CJSON_PUBLIC(cJSON*) cJSON_AddObjectToObject(cJSON * const object, const char * const name);
-CJSON_PUBLIC(cJSON*) cJSON_AddArrayToObject(cJSON * const object, const char * const name);
-
-/* When assigning an integer value, it needs to be propagated to valuedouble too. */
-#define cJSON_SetIntValue(object, number) ((object) ? (object)->valueint = (object)->valuedouble = (number) : (number))
-/* helper for the cJSON_SetNumberValue macro */
-CJSON_PUBLIC(double) cJSON_SetNumberHelper(cJSON *object, double number);
-#define cJSON_SetNumberValue(object, number) ((object != NULL) ? cJSON_SetNumberHelper(object, (double)number) : (number))
-
-/* Macro for iterating over an array or object */
-#define cJSON_ArrayForEach(element, array) for(element = (array != NULL) ? (array)->child : NULL; element != NULL; element = element->next)
-
-/* malloc/free objects using the malloc/free functions that have been set with cJSON_InitHooks */
-CJSON_PUBLIC(void *) cJSON_malloc(size_t size);
-CJSON_PUBLIC(void) cJSON_free(void *object);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/json/cJSON_Utils.h b/tools/sdk/include/json/cJSON_Utils.h
deleted file mode 100644
index a970c650467..00000000000
--- a/tools/sdk/include/json/cJSON_Utils.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
-  Copyright (c) 2009-2017 Dave Gamble and cJSON contributors
-
-  Permission is hereby granted, free of charge, to any person obtaining a copy
-  of this software and associated documentation files (the "Software"), to deal
-  in the Software without restriction, including without limitation the rights
-  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-  copies of the Software, and to permit persons to whom the Software is
-  furnished to do so, subject to the following conditions:
-
-  The above copyright notice and this permission notice shall be included in
-  all copies or substantial portions of the Software.
-
-  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-  THE SOFTWARE.
-*/
-
-#ifndef cJSON_Utils__h
-#define cJSON_Utils__h
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "cJSON.h"
-
-/* Implement RFC6901 (https://tools.ietf.org/html/rfc6901) JSON Pointer spec. */
-CJSON_PUBLIC(cJSON *) cJSONUtils_GetPointer(cJSON * const object, const char *pointer);
-CJSON_PUBLIC(cJSON *) cJSONUtils_GetPointerCaseSensitive(cJSON * const object, const char *pointer);
-
-/* Implement RFC6902 (https://tools.ietf.org/html/rfc6902) JSON Patch spec. */
-/* NOTE: This modifies objects in 'from' and 'to' by sorting the elements by their key */
-CJSON_PUBLIC(cJSON *) cJSONUtils_GeneratePatches(cJSON * const from, cJSON * const to);
-CJSON_PUBLIC(cJSON *) cJSONUtils_GeneratePatchesCaseSensitive(cJSON * const from, cJSON * const to);
-/* Utility for generating patch array entries. */
-CJSON_PUBLIC(void) cJSONUtils_AddPatchToArray(cJSON * const array, const char * const operation, const char * const path, const cJSON * const value);
-/* Returns 0 for success. */
-CJSON_PUBLIC(int) cJSONUtils_ApplyPatches(cJSON * const object, const cJSON * const patches);
-CJSON_PUBLIC(int) cJSONUtils_ApplyPatchesCaseSensitive(cJSON * const object, const cJSON * const patches);
-
-/*
-// Note that ApplyPatches is NOT atomic on failure. To implement an atomic ApplyPatches, use:
-//int cJSONUtils_AtomicApplyPatches(cJSON **object, cJSON *patches)
-//{
-//    cJSON *modme = cJSON_Duplicate(*object, 1);
-//    int error = cJSONUtils_ApplyPatches(modme, patches);
-//    if (!error)
-//    {
-//        cJSON_Delete(*object);
-//        *object = modme;
-//    }
-//    else
-//    {
-//        cJSON_Delete(modme);
-//    }
-//
-//    return error;
-//}
-// Code not added to library since this strategy is a LOT slower.
-*/
-
-/* Implement RFC7386 (https://tools.ietf.org/html/rfc7396) JSON Merge Patch spec. */
-/* target will be modified by patch. return value is new ptr for target. */
-CJSON_PUBLIC(cJSON *) cJSONUtils_MergePatch(cJSON *target, const cJSON * const patch);
-CJSON_PUBLIC(cJSON *) cJSONUtils_MergePatchCaseSensitive(cJSON *target, const cJSON * const patch);
-/* generates a patch to move from -> to */
-/* NOTE: This modifies objects in 'from' and 'to' by sorting the elements by their key */
-CJSON_PUBLIC(cJSON *) cJSONUtils_GenerateMergePatch(cJSON * const from, cJSON * const to);
-CJSON_PUBLIC(cJSON *) cJSONUtils_GenerateMergePatchCaseSensitive(cJSON * const from, cJSON * const to);
-
-/* Given a root object and a target object, construct a pointer from one to the other. */
-CJSON_PUBLIC(char *) cJSONUtils_FindPointerFromObjectTo(const cJSON * const object, const cJSON * const target);
-
-/* Sorts the members of the object into alphabetical order. */
-CJSON_PUBLIC(void) cJSONUtils_SortObject(cJSON * const object);
-CJSON_PUBLIC(void) cJSONUtils_SortObjectCaseSensitive(cJSON * const object);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/json/tests/common.h b/tools/sdk/include/json/tests/common.h
deleted file mode 100644
index 4db6bf8c2d1..00000000000
--- a/tools/sdk/include/json/tests/common.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
-  Copyright (c) 2009-2017 Dave Gamble and cJSON contributors
-
-  Permission is hereby granted, free of charge, to any person obtaining a copy
-  of this software and associated documentation files (the "Software"), to deal
-  in the Software without restriction, including without limitation the rights
-  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-  copies of the Software, and to permit persons to whom the Software is
-  furnished to do so, subject to the following conditions:
-
-  The above copyright notice and this permission notice shall be included in
-  all copies or substantial portions of the Software.
-
-  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-  THE SOFTWARE.
-*/
-
-#ifndef CJSON_TESTS_COMMON_H
-#define CJSON_TESTS_COMMON_H
-
-#include "../cJSON.c"
-
-void reset(cJSON *item);
-void reset(cJSON *item) {
-    if ((item != NULL) && (item->child != NULL))
-    {
-        cJSON_Delete(item->child);
-    }
-    if ((item->valuestring != NULL) && !(item->type & cJSON_IsReference))
-    {
-        global_hooks.deallocate(item->valuestring);
-    }
-    if ((item->string != NULL) && !(item->type & cJSON_StringIsConst))
-    {
-        global_hooks.deallocate(item->string);
-    }
-
-    memset(item, 0, sizeof(cJSON));
-}
-
-char* read_file(const char *filename);
-char* read_file(const char *filename) {
-    FILE *file = NULL;
-    long length = 0;
-    char *content = NULL;
-    size_t read_chars = 0;
-
-    /* open in read binary mode */
-    file = fopen(filename, "rb");
-    if (file == NULL)
-    {
-        goto cleanup;
-    }
-
-    /* get the length */
-    if (fseek(file, 0, SEEK_END) != 0)
-    {
-        goto cleanup;
-    }
-    length = ftell(file);
-    if (length < 0)
-    {
-        goto cleanup;
-    }
-    if (fseek(file, 0, SEEK_SET) != 0)
-    {
-        goto cleanup;
-    }
-
-    /* allocate content buffer */
-    content = (char*)malloc((size_t)length + sizeof(""));
-    if (content == NULL)
-    {
-        goto cleanup;
-    }
-
-    /* read the file into memory */
-    read_chars = fread(content, sizeof(char), (size_t)length, file);
-    if ((long)read_chars != length)
-    {
-        free(content);
-        content = NULL;
-        goto cleanup;
-    }
-    content[read_chars] = '\0';
-
-
-cleanup:
-    if (file != NULL)
-    {
-        fclose(file);
-    }
-
-    return content;
-}
-
-/* assertion helper macros */
-#define assert_has_type(item, item_type) TEST_ASSERT_BITS_MESSAGE(0xFF, item_type, item->type, "Item doesn't have expected type.")
-#define assert_has_no_reference(item) TEST_ASSERT_BITS_MESSAGE(cJSON_IsReference, 0, item->type, "Item should not have a string as reference.")
-#define assert_has_no_const_string(item) TEST_ASSERT_BITS_MESSAGE(cJSON_StringIsConst, 0, item->type, "Item should not have a const string.")
-#define assert_has_valuestring(item) TEST_ASSERT_NOT_NULL_MESSAGE(item->valuestring, "Valuestring is NULL.")
-#define assert_has_no_valuestring(item) TEST_ASSERT_NULL_MESSAGE(item->valuestring, "Valuestring is not NULL.")
-#define assert_has_string(item) TEST_ASSERT_NOT_NULL_MESSAGE(item->string, "String is NULL")
-#define assert_has_no_string(item) TEST_ASSERT_NULL_MESSAGE(item->string, "String is not NULL.")
-#define assert_not_in_list(item) \
-	TEST_ASSERT_NULL_MESSAGE(item->next, "Linked list next pointer is not NULL.");\
-	TEST_ASSERT_NULL_MESSAGE(item->prev, "Linked list previous pointer is not NULL.")
-#define assert_has_child(item) TEST_ASSERT_NOT_NULL_MESSAGE(item->child, "Item doesn't have a child.")
-#define assert_has_no_child(item) TEST_ASSERT_NULL_MESSAGE(item->child, "Item has a child.")
-#define assert_is_invalid(item) \
-	assert_has_type(item, cJSON_Invalid);\
-	assert_not_in_list(item);\
-	assert_has_no_child(item);\
-	assert_has_no_string(item);\
-	assert_has_no_valuestring(item)
-
-#endif
diff --git a/tools/sdk/include/json/tests/unity/examples/example_1/src/ProductionCode.h b/tools/sdk/include/json/tests/unity/examples/example_1/src/ProductionCode.h
deleted file mode 100644
index 250ca0dc6fe..00000000000
--- a/tools/sdk/include/json/tests/unity/examples/example_1/src/ProductionCode.h
+++ /dev/null
@@ -1,3 +0,0 @@
-
-int FindFunction_WhichIsBroken(int NumberToFind);
-int FunctionWhichReturnsLocalVariable(void);
diff --git a/tools/sdk/include/json/tests/unity/examples/example_1/src/ProductionCode2.h b/tools/sdk/include/json/tests/unity/examples/example_1/src/ProductionCode2.h
deleted file mode 100644
index 34ae980d182..00000000000
--- a/tools/sdk/include/json/tests/unity/examples/example_1/src/ProductionCode2.h
+++ /dev/null
@@ -1,2 +0,0 @@
-
-char* ThisFunctionHasNotBeenTested(int Poor, char* LittleFunction);
diff --git a/tools/sdk/include/json/tests/unity/examples/example_2/src/ProductionCode.h b/tools/sdk/include/json/tests/unity/examples/example_2/src/ProductionCode.h
deleted file mode 100644
index 250ca0dc6fe..00000000000
--- a/tools/sdk/include/json/tests/unity/examples/example_2/src/ProductionCode.h
+++ /dev/null
@@ -1,3 +0,0 @@
-
-int FindFunction_WhichIsBroken(int NumberToFind);
-int FunctionWhichReturnsLocalVariable(void);
diff --git a/tools/sdk/include/json/tests/unity/examples/example_2/src/ProductionCode2.h b/tools/sdk/include/json/tests/unity/examples/example_2/src/ProductionCode2.h
deleted file mode 100644
index 34ae980d182..00000000000
--- a/tools/sdk/include/json/tests/unity/examples/example_2/src/ProductionCode2.h
+++ /dev/null
@@ -1,2 +0,0 @@
-
-char* ThisFunctionHasNotBeenTested(int Poor, char* LittleFunction);
diff --git a/tools/sdk/include/json/tests/unity/examples/example_3/helper/UnityHelper.h b/tools/sdk/include/json/tests/unity/examples/example_3/helper/UnityHelper.h
deleted file mode 100644
index 151611158a9..00000000000
--- a/tools/sdk/include/json/tests/unity/examples/example_3/helper/UnityHelper.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _TESTHELPER_H
-#define _TESTHELPER_H
-
-#include "Types.h"
-
-void AssertEqualExampleStruct(const EXAMPLE_STRUCT_T expected, const EXAMPLE_STRUCT_T actual, const unsigned short line);
-
-#define UNITY_TEST_ASSERT_EQUAL_EXAMPLE_STRUCT_T(expected, actual, line, message) AssertEqualExampleStruct(expected, actual, line);
-
-#define TEST_ASSERT_EQUAL_EXAMPLE_STRUCT_T(expected, actual) UNITY_TEST_ASSERT_EQUAL_EXAMPLE_STRUCT_T(expected, actual, __LINE__, NULL);
-
-#endif // _TESTHELPER_H
diff --git a/tools/sdk/include/json/tests/unity/examples/example_3/src/ProductionCode.h b/tools/sdk/include/json/tests/unity/examples/example_3/src/ProductionCode.h
deleted file mode 100644
index 250ca0dc6fe..00000000000
--- a/tools/sdk/include/json/tests/unity/examples/example_3/src/ProductionCode.h
+++ /dev/null
@@ -1,3 +0,0 @@
-
-int FindFunction_WhichIsBroken(int NumberToFind);
-int FunctionWhichReturnsLocalVariable(void);
diff --git a/tools/sdk/include/json/tests/unity/examples/example_3/src/ProductionCode2.h b/tools/sdk/include/json/tests/unity/examples/example_3/src/ProductionCode2.h
deleted file mode 100644
index 34ae980d182..00000000000
--- a/tools/sdk/include/json/tests/unity/examples/example_3/src/ProductionCode2.h
+++ /dev/null
@@ -1,2 +0,0 @@
-
-char* ThisFunctionHasNotBeenTested(int Poor, char* LittleFunction);
diff --git a/tools/sdk/include/json/tests/unity/examples/unity_config.h b/tools/sdk/include/json/tests/unity/examples/unity_config.h
deleted file mode 100644
index a2f161a7a72..00000000000
--- a/tools/sdk/include/json/tests/unity/examples/unity_config.h
+++ /dev/null
@@ -1,239 +0,0 @@
-/* Unity Configuration
- * As of May 11th, 2016 at ThrowTheSwitch/Unity commit 837c529
- * Update: December 29th, 2016
- * See Also: Unity/docs/UnityConfigurationGuide.pdf
- *
- * Unity is designed to run on almost anything that is targeted by a C compiler.
- * It would be awesome if this could be done with zero configuration. While
- * there are some targets that come close to this dream, it is sadly not
- * universal. It is likely that you are going to need at least a couple of the
- * configuration options described in this document.
- *
- * All of Unity's configuration options are `#defines`. Most of these are simple
- * definitions. A couple are macros with arguments. They live inside the
- * unity_internals.h header file. We don't necessarily recommend opening that
- * file unless you really need to. That file is proof that a cross-platform
- * library is challenging to build. From a more positive perspective, it is also
- * proof that a great deal of complexity can be centralized primarily to one
- * place in order to provide a more consistent and simple experience elsewhere.
- *
- * Using These Options
- * It doesn't matter if you're using a target-specific compiler and a simulator
- * or a native compiler. In either case, you've got a couple choices for
- * configuring these options:
- *
- *  1. Because these options are specified via C defines, you can pass most of
- *     these options to your compiler through command line compiler flags. Even
- *     if you're using an embedded target that forces you to use their
- *     overbearing IDE for all configuration, there will be a place somewhere in
- *     your project to configure defines for your compiler.
- *  2. You can create a custom `unity_config.h` configuration file (present in
- *     your toolchain's search paths). In this file, you will list definitions
- *     and macros specific to your target. All you must do is define
- *     `UNITY_INCLUDE_CONFIG_H` and Unity will rely on `unity_config.h` for any
- *     further definitions it may need.
- */
-
-#ifndef UNITY_CONFIG_H
-#define UNITY_CONFIG_H
-
-/* ************************* AUTOMATIC INTEGER TYPES ***************************
- * C's concept of an integer varies from target to target. The C Standard has
- * rules about the `int` matching the register size of the target
- * microprocessor. It has rules about the `int` and how its size relates to
- * other integer types. An `int` on one target might be 16 bits while on another
- * target it might be 64. There are more specific types in compilers compliant
- * with C99 or later, but that's certainly not every compiler you are likely to
- * encounter. Therefore, Unity has a number of features for helping to adjust
- * itself to match your required integer sizes. It starts off by trying to do it
- * automatically.
- **************************************************************************** */
-
-/* The first attempt to guess your types is to check `limits.h`. Some compilers
- * that don't support `stdint.h` could include `limits.h`. If you don't
- * want Unity to check this file, define this to make it skip the inclusion.
- * Unity looks at UINT_MAX & ULONG_MAX, which were available since C89.
- */
-/* #define UNITY_EXCLUDE_LIMITS_H */
-
-/* The second thing that Unity does to guess your types is check `stdint.h`.
- * This file defines `UINTPTR_MAX`, since C99, that Unity can make use of to
- * learn about your system. It's possible you don't want it to do this or it's
- * possible that your system doesn't support `stdint.h`. If that's the case,
- * you're going to want to define this. That way, Unity will know to skip the
- * inclusion of this file and you won't be left with a compiler error.
- */
-/* #define UNITY_EXCLUDE_STDINT_H */
-
-/* ********************** MANUAL INTEGER TYPE DEFINITION ***********************
- * If you've disabled all of the automatic options above, you're going to have
- * to do the configuration yourself. There are just a handful of defines that
- * you are going to specify if you don't like the defaults.
- **************************************************************************** */
-
- /* Define this to be the number of bits an `int` takes up on your system. The
- * default, if not auto-detected, is 32 bits.
- *
- * Example:
- */
-/* #define UNITY_INT_WIDTH 16 */
-
-/* Define this to be the number of bits a `long` takes up on your system. The
- * default, if not autodetected, is 32 bits. This is used to figure out what
- * kind of 64-bit support your system can handle.  Does it need to specify a
- * `long` or a `long long` to get a 64-bit value. On 16-bit systems, this option
- * is going to be ignored.
- *
- * Example:
- */
-/* #define UNITY_LONG_WIDTH 16 */
-
-/* Define this to be the number of bits a pointer takes up on your system. The
- * default, if not autodetected, is 32-bits. If you're getting ugly compiler
- * warnings about casting from pointers, this is the one to look at.
- *
- * Example:
- */
-/* #define UNITY_POINTER_WIDTH 64 */
-
-/* Unity will automatically include 64-bit support if it auto-detects it, or if
- * your `int`, `long`, or pointer widths are greater than 32-bits. Define this
- * to enable 64-bit support if none of the other options already did it for you.
- * There can be a significant size and speed impact to enabling 64-bit support
- * on small targets, so don't define it if you don't need it.
- */
-/* #define UNITY_INCLUDE_64 */
-
-
-/* *************************** FLOATING POINT TYPES ****************************
- * In the embedded world, it's not uncommon for targets to have no support for
- * floating point operations at all or to have support that is limited to only
- * single precision. We are able to guess integer sizes on the fly because
- * integers are always available in at least one size. Floating point, on the
- * other hand, is sometimes not available at all. Trying to include `float.h` on
- * these platforms would result in an error. This leaves manual configuration as
- * the only option.
- **************************************************************************** */
-
- /* By default, Unity guesses that you will want single precision floating point
-  * support, but not double precision. It's easy to change either of these using
-  * the include and exclude options here. You may include neither, just float,
-  * or both, as suits your needs.
-  */
-/* #define UNITY_EXCLUDE_FLOAT  */
-#define UNITY_INCLUDE_DOUBLE
-/* #define UNITY_EXCLUDE_DOUBLE */
-
-/* For features that are enabled, the following floating point options also
- * become available.
- */
-
-/* Unity aims for as small of a footprint as possible and avoids most standard
- * library calls (some embedded platforms don't have a standard library!).
- * Because of this, its routines for printing integer values are minimalist and
- * hand-coded. To keep Unity universal, though, we eventually chose to develop
- * our own floating point print routines. Still, the display of floating point
- * values during a failure are optional. By default, Unity will print the
- * actual results of floating point assertion failures. So a failed assertion
- * will produce a message like "Expected 4.0 Was 4.25". If you would like less
- * verbose failure messages for floating point assertions, use this option to
- * give a failure message `"Values Not Within Delta"` and trim the binary size.
- */
-/* #define UNITY_EXCLUDE_FLOAT_PRINT */
-
-/* If enabled, Unity assumes you want your `FLOAT` asserts to compare standard C
- * floats. If your compiler supports a specialty floating point type, you can
- * always override this behavior by using this definition.
- *
- * Example:
- */
-/* #define UNITY_FLOAT_TYPE float16_t */
-
-/* If enabled, Unity assumes you want your `DOUBLE` asserts to compare standard
- * C doubles. If you would like to change this, you can specify something else
- * by using this option. For example, defining `UNITY_DOUBLE_TYPE` to `long
- * double` could enable gargantuan floating point types on your 64-bit processor
- * instead of the standard `double`.
- *
- * Example:
- */
-/* #define UNITY_DOUBLE_TYPE long double */
-
-/* If you look up `UNITY_ASSERT_EQUAL_FLOAT` and `UNITY_ASSERT_EQUAL_DOUBLE` as
- * documented in the Unity Assertion Guide, you will learn that they are not
- * really asserting that two values are equal but rather that two values are
- * "close enough" to equal. "Close enough" is controlled by these precision
- * configuration options. If you are working with 32-bit floats and/or 64-bit
- * doubles (the normal on most processors), you should have no need to change
- * these options. They are both set to give you approximately 1 significant bit
- * in either direction. The float precision is 0.00001 while the double is
- * 10^-12. For further details on how this works, see the appendix of the Unity
- * Assertion Guide.
- *
- * Example:
- */
-/* #define UNITY_FLOAT_PRECISION 0.001f  */
-/* #define UNITY_DOUBLE_PRECISION 0.001f */
-
-
-/* *************************** TOOLSET CUSTOMIZATION ***************************
- * In addition to the options listed above, there are a number of other options
- * which will come in handy to customize Unity's behavior for your specific
- * toolchain. It is possible that you may not need to touch any of these but
- * certain platforms, particularly those running in simulators, may need to jump
- * through extra hoops to operate properly. These macros will help in those
- * situations.
- **************************************************************************** */
-
-/* By default, Unity prints its results to `stdout` as it runs. This works
- * perfectly fine in most situations where you are using a native compiler for
- * testing. It works on some simulators as well so long as they have `stdout`
- * routed back to the command line. There are times, however, where the
- * simulator will lack support for dumping results or you will want to route
- * results elsewhere for other reasons. In these cases, you should define the
- * `UNITY_OUTPUT_CHAR` macro. This macro accepts a single character at a time
- * (as an `int`, since this is the parameter type of the standard C `putchar`
- * function most commonly used). You may replace this with whatever function
- * call you like.
- *
- * Example:
- * Say you are forced to run your test suite on an embedded processor with no
- * `stdout` option. You decide to route your test result output to a custom
- * serial `RS232_putc()` function you wrote like thus:
- */
-/* #define UNITY_OUTPUT_CHAR(a)                    RS232_putc(a) */
-/* #define UNITY_OUTPUT_CHAR_HEADER_DECLARATION    RS232_putc(int) */
-/* #define UNITY_OUTPUT_FLUSH()                    RS232_flush() */
-/* #define UNITY_OUTPUT_FLUSH_HEADER_DECLARATION   RS232_flush(void) */
-/* #define UNITY_OUTPUT_START()                    RS232_config(115200,1,8,0) */
-/* #define UNITY_OUTPUT_COMPLETE()                 RS232_close() */
-
-/* For some targets, Unity can make the otherwise required `setUp()` and
- * `tearDown()` functions optional. This is a nice convenience for test writers
- * since `setUp` and `tearDown` don't often actually _do_ anything. If you're
- * using gcc or clang, this option is automatically defined for you. Other
- * compilers can also support this behavior, if they support a C feature called
- * weak functions. A weak function is a function that is compiled into your
- * executable _unless_ a non-weak version of the same function is defined
- * elsewhere. If a non-weak version is found, the weak version is ignored as if
- * it never existed. If your compiler supports this feature, you can let Unity
- * know by defining `UNITY_SUPPORT_WEAK` as the function attributes that would
- * need to be applied to identify a function as weak. If your compiler lacks
- * support for weak functions, you will always need to define `setUp` and
- * `tearDown` functions (though they can be and often will be just empty). The
- * most common options for this feature are:
- */
-/* #define UNITY_SUPPORT_WEAK weak */
-/* #define UNITY_SUPPORT_WEAK __attribute__((weak)) */
-/* #define UNITY_NO_WEAK */
-
-/* Some compilers require a custom attribute to be assigned to pointers, like
- * `near` or `far`. In these cases, you can give Unity a safe default for these
- * by defining this option with the attribute you would like.
- *
- * Example:
- */
-/* #define UNITY_PTR_ATTRIBUTE __attribute__((far)) */
-/* #define UNITY_PTR_ATTRIBUTE near */
-
-#endif /* UNITY_CONFIG_H */
diff --git a/tools/sdk/include/json/tests/unity/extras/fixture/src/unity_fixture.h b/tools/sdk/include/json/tests/unity/extras/fixture/src/unity_fixture.h
deleted file mode 100644
index 6f8d6234b37..00000000000
--- a/tools/sdk/include/json/tests/unity/extras/fixture/src/unity_fixture.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright (c) 2010 James Grenning and Contributed to Unity Project
- * ==========================================
- *  Unity Project - A Test Framework for C
- *  Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
- *  [Released under MIT License. Please refer to license.txt for details]
- * ========================================== */
-
-#ifndef UNITY_FIXTURE_H_
-#define UNITY_FIXTURE_H_
-
-#include "unity.h"
-#include "unity_internals.h"
-#include "unity_fixture_malloc_overrides.h"
-#include "unity_fixture_internals.h"
-
-int UnityMain(int argc, const char* argv[], void (*runAllTests)(void));
-
-
-#define TEST_GROUP(group)\
-    static const char* TEST_GROUP_##group = #group
-
-#define TEST_SETUP(group) void TEST_##group##_SETUP(void);\
-    void TEST_##group##_SETUP(void)
-
-#define TEST_TEAR_DOWN(group) void TEST_##group##_TEAR_DOWN(void);\
-    void TEST_##group##_TEAR_DOWN(void)
-
-
-#define TEST(group, name) \
-    void TEST_##group##_##name##_(void);\
-    void TEST_##group##_##name##_run(void);\
-    void TEST_##group##_##name##_run(void)\
-    {\
-        UnityTestRunner(TEST_##group##_SETUP,\
-            TEST_##group##_##name##_,\
-            TEST_##group##_TEAR_DOWN,\
-            "TEST(" #group ", " #name ")",\
-            TEST_GROUP_##group, #name,\
-            __FILE__, __LINE__);\
-    }\
-    void  TEST_##group##_##name##_(void)
-
-#define IGNORE_TEST(group, name) \
-    void TEST_##group##_##name##_(void);\
-    void TEST_##group##_##name##_run(void);\
-    void TEST_##group##_##name##_run(void)\
-    {\
-        UnityIgnoreTest("IGNORE_TEST(" #group ", " #name ")", TEST_GROUP_##group, #name);\
-    }\
-    void TEST_##group##_##name##_(void)
-
-/* Call this for each test, insider the group runner */
-#define RUN_TEST_CASE(group, name) \
-    { void TEST_##group##_##name##_run(void);\
-      TEST_##group##_##name##_run(); }
-
-/* This goes at the bottom of each test file or in a separate c file */
-#define TEST_GROUP_RUNNER(group)\
-    void TEST_##group##_GROUP_RUNNER(void);\
-    void TEST_##group##_GROUP_RUNNER(void)
-
-/* Call this from main */
-#define RUN_TEST_GROUP(group)\
-    { void TEST_##group##_GROUP_RUNNER(void);\
-      TEST_##group##_GROUP_RUNNER(); }
-
-/* CppUTest Compatibility Macros */
-#ifndef UNITY_EXCLUDE_CPPUTEST_ASSERTS
-/* Sets a pointer and automatically restores it to its old value after teardown */
-#define UT_PTR_SET(ptr, newPointerValue)               UnityPointer_Set((void**)&(ptr), (void*)(newPointerValue), __LINE__)
-#define TEST_ASSERT_POINTERS_EQUAL(expected, actual)   TEST_ASSERT_EQUAL_PTR((expected), (actual))
-#define TEST_ASSERT_BYTES_EQUAL(expected, actual)      TEST_ASSERT_EQUAL_HEX8(0xff & (expected), 0xff & (actual))
-#define FAIL(message)                                  TEST_FAIL_MESSAGE((message))
-#define CHECK(condition)                               TEST_ASSERT_TRUE((condition))
-#define LONGS_EQUAL(expected, actual)                  TEST_ASSERT_EQUAL_INT((expected), (actual))
-#define STRCMP_EQUAL(expected, actual)                 TEST_ASSERT_EQUAL_STRING((expected), (actual))
-#define DOUBLES_EQUAL(expected, actual, delta)         TEST_ASSERT_DOUBLE_WITHIN((delta), (expected), (actual))
-#endif
-
-/* You must compile with malloc replacement, as defined in unity_fixture_malloc_overrides.h */
-void UnityMalloc_MakeMallocFailAfterCount(int count);
-
-#endif /* UNITY_FIXTURE_H_ */
diff --git a/tools/sdk/include/json/tests/unity/extras/fixture/src/unity_fixture_internals.h b/tools/sdk/include/json/tests/unity/extras/fixture/src/unity_fixture_internals.h
deleted file mode 100644
index aa0d9e7c0b9..00000000000
--- a/tools/sdk/include/json/tests/unity/extras/fixture/src/unity_fixture_internals.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright (c) 2010 James Grenning and Contributed to Unity Project
- * ==========================================
- *  Unity Project - A Test Framework for C
- *  Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
- *  [Released under MIT License. Please refer to license.txt for details]
- * ========================================== */
-
-#ifndef UNITY_FIXTURE_INTERNALS_H_
-#define UNITY_FIXTURE_INTERNALS_H_
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-struct UNITY_FIXTURE_T
-{
-    int Verbose;
-    unsigned int RepeatCount;
-    const char* NameFilter;
-    const char* GroupFilter;
-};
-extern struct UNITY_FIXTURE_T UnityFixture;
-
-typedef void unityfunction(void);
-void UnityTestRunner(unityfunction* setup,
-                     unityfunction* body,
-                     unityfunction* teardown,
-                     const char* printableName,
-                     const char* group,
-                     const char* name,
-                     const char* file, unsigned int line);
-
-void UnityIgnoreTest(const char* printableName, const char* group, const char* name);
-void UnityMalloc_StartTest(void);
-void UnityMalloc_EndTest(void);
-int UnityGetCommandLineOptions(int argc, const char* argv[]);
-void UnityConcludeFixtureTest(void);
-
-void UnityPointer_Set(void** ptr, void* newValue, UNITY_LINE_TYPE line);
-void UnityPointer_UndoAllSets(void);
-void UnityPointer_Init(void);
-#ifndef UNITY_MAX_POINTERS
-#define UNITY_MAX_POINTERS 5
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* UNITY_FIXTURE_INTERNALS_H_ */
diff --git a/tools/sdk/include/json/tests/unity/extras/fixture/src/unity_fixture_malloc_overrides.h b/tools/sdk/include/json/tests/unity/extras/fixture/src/unity_fixture_malloc_overrides.h
deleted file mode 100644
index 7daba50aae5..00000000000
--- a/tools/sdk/include/json/tests/unity/extras/fixture/src/unity_fixture_malloc_overrides.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Copyright (c) 2010 James Grenning and Contributed to Unity Project
- * ==========================================
- *  Unity Project - A Test Framework for C
- *  Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
- *  [Released under MIT License. Please refer to license.txt for details]
- * ========================================== */
-
-#ifndef UNITY_FIXTURE_MALLOC_OVERRIDES_H_
-#define UNITY_FIXTURE_MALLOC_OVERRIDES_H_
-
-#include <stddef.h>
-
-#ifdef UNITY_EXCLUDE_STDLIB_MALLOC
-/* Define this macro to remove the use of stdlib.h, malloc, and free.
- * Many embedded systems do not have a heap or malloc/free by default.
- * This internal unity_malloc() provides allocated memory deterministically from
- * the end of an array only, unity_free() only releases from end-of-array,
- * blocks are not coalesced, and memory not freed in LIFO order is stranded. */
-    #ifndef UNITY_INTERNAL_HEAP_SIZE_BYTES
-    #define UNITY_INTERNAL_HEAP_SIZE_BYTES 256
-    #endif
-#endif
-
-/* These functions are used by the Unity Fixture to allocate and release memory
- * on the heap and can be overridden with platform-specific implementations.
- * For example, when using FreeRTOS UNITY_FIXTURE_MALLOC becomes pvPortMalloc()
- * and UNITY_FIXTURE_FREE becomes vPortFree(). */
-#if !defined(UNITY_FIXTURE_MALLOC) || !defined(UNITY_FIXTURE_FREE)
-    #include <stdlib.h>
-    #define UNITY_FIXTURE_MALLOC(size) malloc(size)
-    #define UNITY_FIXTURE_FREE(ptr)    free(ptr)
-#else
-    extern void* UNITY_FIXTURE_MALLOC(size_t size);
-    extern void UNITY_FIXTURE_FREE(void* ptr);
-#endif
-
-#define malloc  unity_malloc
-#define calloc  unity_calloc
-#define realloc unity_realloc
-#define free    unity_free
-
-void* unity_malloc(size_t size);
-void* unity_calloc(size_t num, size_t size);
-void* unity_realloc(void * oldMem, size_t size);
-void unity_free(void * mem);
-
-#endif /* UNITY_FIXTURE_MALLOC_OVERRIDES_H_ */
diff --git a/tools/sdk/include/json/tests/unity/extras/fixture/test/unity_output_Spy.h b/tools/sdk/include/json/tests/unity/extras/fixture/test/unity_output_Spy.h
deleted file mode 100644
index b30a7f13bbe..00000000000
--- a/tools/sdk/include/json/tests/unity/extras/fixture/test/unity_output_Spy.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright (c) 2010 James Grenning and Contributed to Unity Project
- * ==========================================
- *  Unity Project - A Test Framework for C
- *  Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
- *  [Released under MIT License. Please refer to license.txt for details]
- * ========================================== */
-
-#ifndef D_unity_output_Spy_H
-#define D_unity_output_Spy_H
-
-void UnityOutputCharSpy_Create(int s);
-void UnityOutputCharSpy_Destroy(void);
-void UnityOutputCharSpy_OutputChar(int c);
-const char * UnityOutputCharSpy_Get(void);
-void UnityOutputCharSpy_Enable(int enable);
-
-#endif
diff --git a/tools/sdk/include/json/tests/unity/src/unity.h b/tools/sdk/include/json/tests/unity/src/unity.h
deleted file mode 100644
index 32ff0e6df46..00000000000
--- a/tools/sdk/include/json/tests/unity/src/unity.h
+++ /dev/null
@@ -1,503 +0,0 @@
-/* ==========================================
-    Unity Project - A Test Framework for C
-    Copyright (c) 2007-14 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-========================================== */
-
-#ifndef UNITY_FRAMEWORK_H
-#define UNITY_FRAMEWORK_H
-#define UNITY
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "unity_internals.h"
-
-/*-------------------------------------------------------
- * Test Setup / Teardown
- *-------------------------------------------------------*/
-
-/* These functions are intended to be called before and after each test. */
-void setUp(void);
-void tearDown(void);
-
-/* These functions are intended to be called at the beginning and end of an
- * entire test suite.  suiteTearDown() is passed the number of tests that
- * failed, and its return value becomes the exit code of main(). */
-void suiteSetUp(void);
-int suiteTearDown(int num_failures);
-
-/* If the compiler supports it, the following block provides stub
- * implementations of the above functions as weak symbols.  Note that on
- * some platforms (MinGW for example), weak function implementations need
- * to be in the same translation unit they are called from.  This can be
- * achieved by defining UNITY_INCLUDE_SETUP_STUBS before including unity.h. */
-#ifdef UNITY_INCLUDE_SETUP_STUBS
-  #ifdef UNITY_WEAK_ATTRIBUTE
-    UNITY_WEAK_ATTRIBUTE void setUp(void) { }
-    UNITY_WEAK_ATTRIBUTE void tearDown(void) { }
-    UNITY_WEAK_ATTRIBUTE void suiteSetUp(void) { }
-    UNITY_WEAK_ATTRIBUTE int suiteTearDown(int num_failures) { return num_failures; }
-  #elif defined(UNITY_WEAK_PRAGMA)
-    #pragma weak setUp
-    void setUp(void) { }
-    #pragma weak tearDown
-    void tearDown(void) { }
-    #pragma weak suiteSetUp
-    void suiteSetUp(void) { }
-    #pragma weak suiteTearDown
-    int suiteTearDown(int num_failures) { return num_failures; }
-  #endif
-#endif
-
-/*-------------------------------------------------------
- * Configuration Options
- *-------------------------------------------------------
- * All options described below should be passed as a compiler flag to all files using Unity. If you must add #defines, place them BEFORE the #include above.
-
- * Integers/longs/pointers
- *     - Unity attempts to automatically discover your integer sizes
- *       - define UNITY_EXCLUDE_STDINT_H to stop attempting to look in <stdint.h>
- *       - define UNITY_EXCLUDE_LIMITS_H to stop attempting to look in <limits.h>
- *     - If you cannot use the automatic methods above, you can force Unity by using these options:
- *       - define UNITY_SUPPORT_64
- *       - set UNITY_INT_WIDTH
- *       - set UNITY_LONG_WIDTH
- *       - set UNITY_POINTER_WIDTH
-
- * Floats
- *     - define UNITY_EXCLUDE_FLOAT to disallow floating point comparisons
- *     - define UNITY_FLOAT_PRECISION to specify the precision to use when doing TEST_ASSERT_EQUAL_FLOAT
- *     - define UNITY_FLOAT_TYPE to specify doubles instead of single precision floats
- *     - define UNITY_INCLUDE_DOUBLE to allow double floating point comparisons
- *     - define UNITY_EXCLUDE_DOUBLE to disallow double floating point comparisons (default)
- *     - define UNITY_DOUBLE_PRECISION to specify the precision to use when doing TEST_ASSERT_EQUAL_DOUBLE
- *     - define UNITY_DOUBLE_TYPE to specify something other than double
- *     - define UNITY_EXCLUDE_FLOAT_PRINT to trim binary size, won't print floating point values in errors
-
- * Output
- *     - by default, Unity prints to standard out with putchar.  define UNITY_OUTPUT_CHAR(a) with a different function if desired
- *     - define UNITY_DIFFERENTIATE_FINAL_FAIL to print FAILED (vs. FAIL) at test end summary - for automated search for failure
-
- * Optimization
- *     - by default, line numbers are stored in unsigned shorts.  Define UNITY_LINE_TYPE with a different type if your files are huge
- *     - by default, test and failure counters are unsigned shorts.  Define UNITY_COUNTER_TYPE with a different type if you want to save space or have more than 65535 Tests.
-
- * Test Cases
- *     - define UNITY_SUPPORT_TEST_CASES to include the TEST_CASE macro, though really it's mostly about the runner generator script
-
- * Parameterized Tests
- *     - you'll want to create a define of TEST_CASE(...) which basically evaluates to nothing
-
- * Tests with Arguments
- *     - you'll want to define UNITY_USE_COMMAND_LINE_ARGS if you have the test runner passing arguments to Unity
-
- *-------------------------------------------------------
- * Basic Fail and Ignore
- *-------------------------------------------------------*/
-
-#define TEST_FAIL_MESSAGE(message)                                                                 UNITY_TEST_FAIL(__LINE__, (message))
-#define TEST_FAIL()                                                                                UNITY_TEST_FAIL(__LINE__, NULL)
-#define TEST_IGNORE_MESSAGE(message)                                                               UNITY_TEST_IGNORE(__LINE__, (message))
-#define TEST_IGNORE()                                                                              UNITY_TEST_IGNORE(__LINE__, NULL)
-#define TEST_ONLY()
-
-/* It is not necessary for you to call PASS. A PASS condition is assumed if nothing fails.
- * This method allows you to abort a test immediately with a PASS state, ignoring the remainder of the test. */
-#define TEST_PASS()                                                                                TEST_ABORT()
-
-/* This macro does nothing, but it is useful for build tools (like Ceedling) to make use of this to figure out
- * which files should be linked to in order to perform a test. Use it like TEST_FILE("sandwiches.c") */
-#define TEST_FILE(a)
-
-/*-------------------------------------------------------
- * Test Asserts (simple)
- *-------------------------------------------------------*/
-
-/* Boolean */
-#define TEST_ASSERT(condition)                                                                     UNITY_TEST_ASSERT(       (condition), __LINE__, " Expression Evaluated To FALSE")
-#define TEST_ASSERT_TRUE(condition)                                                                UNITY_TEST_ASSERT(       (condition), __LINE__, " Expected TRUE Was FALSE")
-#define TEST_ASSERT_UNLESS(condition)                                                              UNITY_TEST_ASSERT(      !(condition), __LINE__, " Expression Evaluated To TRUE")
-#define TEST_ASSERT_FALSE(condition)                                                               UNITY_TEST_ASSERT(      !(condition), __LINE__, " Expected FALSE Was TRUE")
-#define TEST_ASSERT_NULL(pointer)                                                                  UNITY_TEST_ASSERT_NULL(    (pointer), __LINE__, " Expected NULL")
-#define TEST_ASSERT_NOT_NULL(pointer)                                                              UNITY_TEST_ASSERT_NOT_NULL((pointer), __LINE__, " Expected Non-NULL")
-
-/* Integers (of all sizes) */
-#define TEST_ASSERT_EQUAL_INT(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT8(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_INT8((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT16(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_INT16((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT32(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_INT32((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT64(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_INT64((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL(expected, actual)                                                        UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_NOT_EQUAL(expected, actual)                                                    UNITY_TEST_ASSERT(((expected) !=  (actual)), __LINE__, " Expected Not-Equal")
-#define TEST_ASSERT_EQUAL_UINT(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_UINT( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT8(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_UINT8( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT16(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT16( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT32(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT32( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT64(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT64( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX8(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_HEX8( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX16(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX16((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX32(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX64(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX64((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS(mask, expected, actual)                                                   UNITY_TEST_ASSERT_BITS((mask), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS_HIGH(mask, actual)                                                        UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(-1), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS_LOW(mask, actual)                                                         UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(0), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BIT_HIGH(bit, actual)                                                          UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(-1), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BIT_LOW(bit, actual)                                                           UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(0), (actual), __LINE__, NULL)
-
-/* Integer Greater Than/ Less Than (of all sizes) */
-#define TEST_ASSERT_GREATER_THAN(threshold, actual)                                                UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT(threshold, actual)                                            UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT8(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT16(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT32(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT64(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT8(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT16(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT32(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX8(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX16(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX32(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_HEX64((threshold), (actual), __LINE__, NULL)
-
-#define TEST_ASSERT_LESS_THAN(threshold, actual)                                                   UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT(threshold, actual)                                               UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT8(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT16(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT32(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT64(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT8(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT16(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT32(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT64(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX8(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX16(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX32(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX64(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX64((threshold), (actual), __LINE__, NULL)
-
-#define TEST_ASSERT_GREATER_OR_EQUAL(threshold, actual)                                            UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT(threshold, actual)                                        UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT8(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT16(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT32(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT64(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT8(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT16(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT32(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT64(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX8(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX16(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX32(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX64(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, NULL)
-
-#define TEST_ASSERT_LESS_OR_EQUAL(threshold, actual)                                               UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT(threshold, actual)                                           UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT8(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT16(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT32(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT64(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT8(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT16(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT32(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT64(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX8(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX16(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX32(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX64(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, NULL)
-
-/* Integer Ranges (of all sizes) */
-#define TEST_ASSERT_INT_WITHIN(delta, expected, actual)                                            UNITY_TEST_ASSERT_INT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT8_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_INT8_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT16_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_INT16_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT32_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_INT32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT64_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_INT64_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_UINT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT8_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_UINT8_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT16_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT16_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT32_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT64_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT64_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX_WITHIN(delta, expected, actual)                                            UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX8_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_HEX8_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX16_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_HEX16_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX32_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX64_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_HEX64_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-
-/* Structs and Strings */
-#define TEST_ASSERT_EQUAL_PTR(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_PTR((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_STRING(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_STRING((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_STRING_LEN(expected, actual, len)                                        UNITY_TEST_ASSERT_EQUAL_STRING_LEN((expected), (actual), (len), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_MEMORY(expected, actual, len)                                            UNITY_TEST_ASSERT_EQUAL_MEMORY((expected), (actual), (len), __LINE__, NULL)
-
-/* Arrays */
-#define TEST_ASSERT_EQUAL_INT_ARRAY(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EQUAL_INT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT8_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_INT8_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT16_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_INT16_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT32_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_INT32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT64_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT8_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_UINT8_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT16_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT16_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT32_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT64_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX_ARRAY(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX8_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_HEX8_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX16_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_HEX16_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX32_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX64_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_PTR_ARRAY(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EQUAL_PTR_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_STRING_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_STRING_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_MEMORY_ARRAY(expected, actual, len, num_elements)                        UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((expected), (actual), (len), (num_elements), __LINE__, NULL)
-
-/* Arrays Compared To Single Value */
-#define TEST_ASSERT_EACH_EQUAL_INT(expected, actual, num_elements)                                 UNITY_TEST_ASSERT_EACH_EQUAL_INT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT8(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_INT8((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT16(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_INT16((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT32(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_INT32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT64(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_INT64((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_UINT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT8(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_UINT8((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT16(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT16((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT32(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT64(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT64((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX(expected, actual, num_elements)                                 UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX8(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_HEX8((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX16(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_HEX16((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX32(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX64(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_HEX64((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_PTR(expected, actual, num_elements)                                 UNITY_TEST_ASSERT_EACH_EQUAL_PTR((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_STRING(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_STRING((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_MEMORY(expected, actual, len, num_elements)                         UNITY_TEST_ASSERT_EACH_EQUAL_MEMORY((expected), (actual), (len), (num_elements), __LINE__, NULL)
-
-/* Floating Point (If Enabled) */
-#define TEST_ASSERT_FLOAT_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_FLOAT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_FLOAT(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_FLOAT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_FLOAT_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_FLOAT(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_INF(actual)                                                           UNITY_TEST_ASSERT_FLOAT_IS_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NEG_INF(actual)                                                       UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NAN(actual)                                                           UNITY_TEST_ASSERT_FLOAT_IS_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_DETERMINATE(actual)                                                   UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_INF(actual)                                                       UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_NEG_INF(actual)                                                   UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_NAN(actual)                                                       UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE(actual)                                               UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE((actual), __LINE__, NULL)
-
-/* Double (If Enabled) */
-#define TEST_ASSERT_DOUBLE_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_DOUBLE_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_DOUBLE(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_DOUBLE((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_DOUBLE_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_DOUBLE(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_INF(actual)                                                          UNITY_TEST_ASSERT_DOUBLE_IS_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NEG_INF(actual)                                                      UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NAN(actual)                                                          UNITY_TEST_ASSERT_DOUBLE_IS_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_DETERMINATE(actual)                                                  UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_INF(actual)                                                      UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF(actual)                                                  UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_NAN(actual)                                                      UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual)                                              UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE((actual), __LINE__, NULL)
-
-/*-------------------------------------------------------
- * Test Asserts (with additional messages)
- *-------------------------------------------------------*/
-
-/* Boolean */
-#define TEST_ASSERT_MESSAGE(condition, message)                                                    UNITY_TEST_ASSERT(       (condition), __LINE__, (message))
-#define TEST_ASSERT_TRUE_MESSAGE(condition, message)                                               UNITY_TEST_ASSERT(       (condition), __LINE__, (message))
-#define TEST_ASSERT_UNLESS_MESSAGE(condition, message)                                             UNITY_TEST_ASSERT(      !(condition), __LINE__, (message))
-#define TEST_ASSERT_FALSE_MESSAGE(condition, message)                                              UNITY_TEST_ASSERT(      !(condition), __LINE__, (message))
-#define TEST_ASSERT_NULL_MESSAGE(pointer, message)                                                 UNITY_TEST_ASSERT_NULL(    (pointer), __LINE__, (message))
-#define TEST_ASSERT_NOT_NULL_MESSAGE(pointer, message)                                             UNITY_TEST_ASSERT_NOT_NULL((pointer), __LINE__, (message))
-
-/* Integers (of all sizes) */
-#define TEST_ASSERT_EQUAL_INT_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT8_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_INT8((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT16_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_INT16((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT32_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_INT32((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT64_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_INT64((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_MESSAGE(expected, actual, message)                                       UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_NOT_EQUAL_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT(((expected) !=  (actual)), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_UINT( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT8_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_UINT8( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT16_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT16( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT32_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT32( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT64_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT64( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX8_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_HEX8( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX16_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_HEX16((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX32_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX64_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_HEX64((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_BITS_MESSAGE(mask, expected, actual, message)                                  UNITY_TEST_ASSERT_BITS((mask), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_BITS_HIGH_MESSAGE(mask, actual, message)                                       UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(-1), (actual), __LINE__, (message))
-#define TEST_ASSERT_BITS_LOW_MESSAGE(mask, actual, message)                                        UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(0), (actual), __LINE__, (message))
-#define TEST_ASSERT_BIT_HIGH_MESSAGE(bit, actual, message)                                         UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(-1), (actual), __LINE__, (message))
-#define TEST_ASSERT_BIT_LOW_MESSAGE(bit, actual, message)                                          UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(0), (actual), __LINE__, (message))
-
-/* Integer Greater Than/ Less Than (of all sizes) */
-#define TEST_ASSERT_GREATER_THAN_MESSAGE(threshold, actual, message)                               UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT8_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT16_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT32_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT64_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT8_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT16_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT32_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT64_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX8_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX16_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX32_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX64_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_HEX64((threshold), (actual), __LINE__, (message))
-
-#define TEST_ASSERT_LESS_THAN_MESSAGE(threshold, actual, message)                                  UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT_MESSAGE(threshold, actual, message)                              UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT8_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT16_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT32_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT64_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT8_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT16_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT32_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT64_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX8_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX16_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX32_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX64_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_HEX64((threshold), (actual), __LINE__, (message))
-
-#define TEST_ASSERT_GREATER_OR_EQUAL_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT8_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT16_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT32_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT64_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT8_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT16_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT32_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT64_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX8_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX16_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX32_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX64_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, (message))
-
-#define TEST_ASSERT_LESS_OR_EQUAL_MESSAGE(threshold, actual, message)                              UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT8_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT16_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT32_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT64_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT8_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT16_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT32_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT64_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX8_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX16_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX32_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_THAN_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX64_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_THAN_HEX64((threshold), (actual), __LINE__, (message))
-
-/* Integer Ranges (of all sizes) */
-#define TEST_ASSERT_INT_WITHIN_MESSAGE(delta, expected, actual, message)                           UNITY_TEST_ASSERT_INT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT8_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_INT8_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT16_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_INT16_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT32_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_INT32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT64_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_INT64_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_UINT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT8_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_UINT8_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT16_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT16_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT32_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT64_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT64_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX_WITHIN_MESSAGE(delta, expected, actual, message)                           UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX8_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_HEX8_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX16_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_HEX16_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX32_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX64_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_HEX64_WITHIN((delta), (expected), (actual), __LINE__, (message))
-
-/* Structs and Strings */
-#define TEST_ASSERT_EQUAL_PTR_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_PTR((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_STRING_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_STRING((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_STRING_LEN_MESSAGE(expected, actual, len, message)                       UNITY_TEST_ASSERT_EQUAL_STRING_LEN((expected), (actual), (len), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_MEMORY_MESSAGE(expected, actual, len, message)                           UNITY_TEST_ASSERT_EQUAL_MEMORY((expected), (actual), (len), __LINE__, (message))
-
-/* Arrays */
-#define TEST_ASSERT_EQUAL_INT_ARRAY_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EQUAL_INT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT8_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_INT8_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT16_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_INT16_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT32_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_INT32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT64_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT8_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_UINT8_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT16_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT16_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT32_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT64_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX_ARRAY_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX8_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_HEX8_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX16_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_HEX16_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX32_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX64_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_PTR_ARRAY_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EQUAL_PTR_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_STRING_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_STRING_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_MEMORY_ARRAY_MESSAGE(expected, actual, len, num_elements, message)       UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((expected), (actual), (len), (num_elements), __LINE__, (message))
-
-/* Arrays Compared To Single Value*/
-#define TEST_ASSERT_EACH_EQUAL_INT_MESSAGE(expected, actual, num_elements, message)                UNITY_TEST_ASSERT_EACH_EQUAL_INT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT8_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_INT8((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT16_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_INT16((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT32_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_INT32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT64_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_INT64((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_UINT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT8_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_UINT8((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT16_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT16((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT32_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT64_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT64((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX_MESSAGE(expected, actual, num_elements, message)                UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX8_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_HEX8((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX16_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_HEX16((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX32_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX64_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_HEX64((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_PTR_MESSAGE(expected, actual, num_elements, message)                UNITY_TEST_ASSERT_EACH_EQUAL_PTR((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_STRING_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_STRING((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_MEMORY_MESSAGE(expected, actual, len, num_elements, message)        UNITY_TEST_ASSERT_EACH_EQUAL_MEMORY((expected), (actual), (len), (num_elements), __LINE__, (message))
-
-/* Floating Point (If Enabled) */
-#define TEST_ASSERT_FLOAT_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_FLOAT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_FLOAT_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_FLOAT((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_FLOAT_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_FLOAT_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_INF_MESSAGE(actual, message)                                          UNITY_TEST_ASSERT_FLOAT_IS_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NEG_INF_MESSAGE(actual, message)                                      UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NAN_MESSAGE(actual, message)                                          UNITY_TEST_ASSERT_FLOAT_IS_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_DETERMINATE_MESSAGE(actual, message)                                  UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_INF_MESSAGE(actual, message)                                      UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_NEG_INF_MESSAGE(actual, message)                                  UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_NAN_MESSAGE(actual, message)                                      UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE_MESSAGE(actual, message)                              UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE((actual), __LINE__, (message))
-
-/* Double (If Enabled) */
-#define TEST_ASSERT_DOUBLE_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_DOUBLE_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_DOUBLE_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_DOUBLE((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_DOUBLE_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_DOUBLE_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_INF_MESSAGE(actual, message)                                         UNITY_TEST_ASSERT_DOUBLE_IS_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NEG_INF_MESSAGE(actual, message)                                     UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NAN_MESSAGE(actual, message)                                         UNITY_TEST_ASSERT_DOUBLE_IS_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_DETERMINATE_MESSAGE(actual, message)                                 UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_INF_MESSAGE(actual, message)                                     UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF_MESSAGE(actual, message)                                 UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_NAN_MESSAGE(actual, message)                                     UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE_MESSAGE(actual, message)                             UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE((actual), __LINE__, (message))
-
-/* end of UNITY_FRAMEWORK_H */
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/tools/sdk/include/json/tests/unity/src/unity_internals.h b/tools/sdk/include/json/tests/unity/src/unity_internals.h
deleted file mode 100644
index f78cebace4e..00000000000
--- a/tools/sdk/include/json/tests/unity/src/unity_internals.h
+++ /dev/null
@@ -1,870 +0,0 @@
-/* ==========================================
-    Unity Project - A Test Framework for C
-    Copyright (c) 2007-14 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-========================================== */
-
-#ifndef UNITY_INTERNALS_H
-#define UNITY_INTERNALS_H
-
-#include "../examples/unity_config.h"
-
-#ifndef UNITY_EXCLUDE_SETJMP_H
-#include <setjmp.h>
-#endif
-
-#ifndef UNITY_EXCLUDE_MATH_H
-#include <math.h>
-#endif
-
-/* Unity Attempts to Auto-Detect Integer Types
- * Attempt 1: UINT_MAX, ULONG_MAX in <limits.h>, or default to 32 bits
- * Attempt 2: UINTPTR_MAX in <stdint.h>, or default to same size as long
- * The user may override any of these derived constants:
- * UNITY_INT_WIDTH, UNITY_LONG_WIDTH, UNITY_POINTER_WIDTH */
-#ifndef UNITY_EXCLUDE_STDINT_H
-#include <stdint.h>
-#endif
-
-#ifndef UNITY_EXCLUDE_LIMITS_H
-#include <limits.h>
-#endif
-
-/*-------------------------------------------------------
- * Guess Widths If Not Specified
- *-------------------------------------------------------*/
-
-/* Determine the size of an int, if not already specified.
- * We cannot use sizeof(int), because it is not yet defined
- * at this stage in the translation of the C program.
- * Therefore, infer it from UINT_MAX if possible. */
-#ifndef UNITY_INT_WIDTH
-  #ifdef UINT_MAX
-    #if (UINT_MAX == 0xFFFF)
-      #define UNITY_INT_WIDTH (16)
-    #elif (UINT_MAX == 0xFFFFFFFF)
-      #define UNITY_INT_WIDTH (32)
-    #elif (UINT_MAX == 0xFFFFFFFFFFFFFFFF)
-      #define UNITY_INT_WIDTH (64)
-    #endif
-  #else /* Set to default */
-    #define UNITY_INT_WIDTH (32)
-  #endif /* UINT_MAX */
-#endif
-
-/* Determine the size of a long, if not already specified. */
-#ifndef UNITY_LONG_WIDTH
-  #ifdef ULONG_MAX
-    #if (ULONG_MAX == 0xFFFF)
-      #define UNITY_LONG_WIDTH (16)
-    #elif (ULONG_MAX == 0xFFFFFFFF)
-      #define UNITY_LONG_WIDTH (32)
-    #elif (ULONG_MAX == 0xFFFFFFFFFFFFFFFF)
-      #define UNITY_LONG_WIDTH (64)
-    #endif
-  #else /* Set to default */
-    #define UNITY_LONG_WIDTH (32)
-  #endif /* ULONG_MAX */
-#endif
-
-/* Determine the size of a pointer, if not already specified. */
-#ifndef UNITY_POINTER_WIDTH
-  #ifdef UINTPTR_MAX
-    #if (UINTPTR_MAX <= 0xFFFF)
-      #define UNITY_POINTER_WIDTH (16)
-    #elif (UINTPTR_MAX <= 0xFFFFFFFF)
-      #define UNITY_POINTER_WIDTH (32)
-    #elif (UINTPTR_MAX <= 0xFFFFFFFFFFFFFFFF)
-      #define UNITY_POINTER_WIDTH (64)
-    #endif
-  #else /* Set to default */
-    #define UNITY_POINTER_WIDTH UNITY_LONG_WIDTH
-  #endif /* UINTPTR_MAX */
-#endif
-
-/*-------------------------------------------------------
- * Int Support (Define types based on detected sizes)
- *-------------------------------------------------------*/
-
-#if (UNITY_INT_WIDTH == 32)
-    typedef unsigned char   UNITY_UINT8;
-    typedef unsigned short  UNITY_UINT16;
-    typedef unsigned int    UNITY_UINT32;
-    typedef signed char     UNITY_INT8;
-    typedef signed short    UNITY_INT16;
-    typedef signed int      UNITY_INT32;
-#elif (UNITY_INT_WIDTH == 16)
-    typedef unsigned char   UNITY_UINT8;
-    typedef unsigned int    UNITY_UINT16;
-    typedef unsigned long   UNITY_UINT32;
-    typedef signed char     UNITY_INT8;
-    typedef signed int      UNITY_INT16;
-    typedef signed long     UNITY_INT32;
-#else
-    #error Invalid UNITY_INT_WIDTH specified! (16 or 32 are supported)
-#endif
-
-/*-------------------------------------------------------
- * 64-bit Support
- *-------------------------------------------------------*/
-
-#ifndef UNITY_SUPPORT_64
-  #if UNITY_LONG_WIDTH == 64 || UNITY_POINTER_WIDTH == 64
-    #define UNITY_SUPPORT_64
-  #endif
-#endif
-
-#ifndef UNITY_SUPPORT_64
-    /* No 64-bit Support */
-    typedef UNITY_UINT32 UNITY_UINT;
-    typedef UNITY_INT32 UNITY_INT;
-#else
-
-    /* 64-bit Support */
-  #if (UNITY_LONG_WIDTH == 32)
-    typedef unsigned long long UNITY_UINT64;
-    typedef signed long long   UNITY_INT64;
-  #elif (UNITY_LONG_WIDTH == 64)
-    typedef unsigned long      UNITY_UINT64;
-    typedef signed long        UNITY_INT64;
-  #else
-    #error Invalid UNITY_LONG_WIDTH specified! (32 or 64 are supported)
-  #endif
-    typedef UNITY_UINT64 UNITY_UINT;
-    typedef UNITY_INT64 UNITY_INT;
-
-#endif
-
-/*-------------------------------------------------------
- * Pointer Support
- *-------------------------------------------------------*/
-
-#if (UNITY_POINTER_WIDTH == 32)
-#define UNITY_PTR_TO_INT UNITY_INT32
-#define UNITY_DISPLAY_STYLE_POINTER UNITY_DISPLAY_STYLE_HEX32
-#elif (UNITY_POINTER_WIDTH == 64)
-#define UNITY_PTR_TO_INT UNITY_INT64
-#define UNITY_DISPLAY_STYLE_POINTER UNITY_DISPLAY_STYLE_HEX64
-#elif (UNITY_POINTER_WIDTH == 16)
-#define UNITY_PTR_TO_INT UNITY_INT16
-#define UNITY_DISPLAY_STYLE_POINTER UNITY_DISPLAY_STYLE_HEX16
-#else
-    #error Invalid UNITY_POINTER_WIDTH specified! (16, 32 or 64 are supported)
-#endif
-
-#ifndef UNITY_PTR_ATTRIBUTE
-#define UNITY_PTR_ATTRIBUTE
-#endif
-
-#ifndef UNITY_INTERNAL_PTR
-#define UNITY_INTERNAL_PTR UNITY_PTR_ATTRIBUTE const void*
-#endif
-
-/*-------------------------------------------------------
- * Float Support
- *-------------------------------------------------------*/
-
-#ifdef UNITY_EXCLUDE_FLOAT
-
-/* No Floating Point Support */
-#ifndef UNITY_EXCLUDE_DOUBLE
-#define UNITY_EXCLUDE_DOUBLE /* Remove double when excluding float support */
-#endif
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-#define UNITY_EXCLUDE_FLOAT_PRINT
-#endif
-
-#else
-
-/* Floating Point Support */
-#ifndef UNITY_FLOAT_PRECISION
-#define UNITY_FLOAT_PRECISION (0.00001f)
-#endif
-#ifndef UNITY_FLOAT_TYPE
-#define UNITY_FLOAT_TYPE float
-#endif
-typedef UNITY_FLOAT_TYPE UNITY_FLOAT;
-
-/* isinf & isnan macros should be provided by math.h */
-#ifndef isinf
-/* The value of Inf - Inf is NaN */
-#define isinf(n) (isnan((n) - (n)) && !isnan(n))
-#endif
-
-#ifndef isnan
-/* NaN is the only floating point value that does NOT equal itself.
- * Therefore if n != n, then it is NaN. */
-#define isnan(n) ((n != n) ? 1 : 0)
-#endif
-
-#endif
-
-/*-------------------------------------------------------
- * Double Float Support
- *-------------------------------------------------------*/
-
-/* unlike float, we DON'T include by default */
-#if defined(UNITY_EXCLUDE_DOUBLE) || !defined(UNITY_INCLUDE_DOUBLE)
-
-  /* No Floating Point Support */
-  #ifndef UNITY_EXCLUDE_DOUBLE
-  #define UNITY_EXCLUDE_DOUBLE
-  #else
-    #undef UNITY_INCLUDE_DOUBLE
-  #endif
-
-  #ifndef UNITY_EXCLUDE_FLOAT
-    #ifndef UNITY_DOUBLE_TYPE
-    #define UNITY_DOUBLE_TYPE double
-    #endif
-  typedef UNITY_FLOAT UNITY_DOUBLE;
-  /* For parameter in UnityPrintFloat(UNITY_DOUBLE), which aliases to double or float */
-  #endif
-
-#else
-
-  /* Double Floating Point Support */
-  #ifndef UNITY_DOUBLE_PRECISION
-  #define UNITY_DOUBLE_PRECISION (1e-12)
-  #endif
-
-  #ifndef UNITY_DOUBLE_TYPE
-  #define UNITY_DOUBLE_TYPE double
-  #endif
-  typedef UNITY_DOUBLE_TYPE UNITY_DOUBLE;
-
-#endif
-
-/*-------------------------------------------------------
- * Output Method: stdout (DEFAULT)
- *-------------------------------------------------------*/
-#ifndef UNITY_OUTPUT_CHAR
-/* Default to using putchar, which is defined in stdio.h */
-#include <stdio.h>
-#define UNITY_OUTPUT_CHAR(a) (void)putchar(a)
-#else
-  /* If defined as something else, make sure we declare it here so it's ready for use */
-  #ifdef UNITY_OUTPUT_CHAR_HEADER_DECLARATION
-extern void UNITY_OUTPUT_CHAR_HEADER_DECLARATION;
-  #endif
-#endif
-
-#ifndef UNITY_OUTPUT_FLUSH
-#ifdef UNITY_USE_FLUSH_STDOUT
-/* We want to use the stdout flush utility */
-#include <stdio.h>
-#define UNITY_OUTPUT_FLUSH() (void)fflush(stdout)
-#else
-/* We've specified nothing, therefore flush should just be ignored */
-#define UNITY_OUTPUT_FLUSH()
-#endif
-#else
-/* We've defined flush as something else, so make sure we declare it here so it's ready for use */
-#ifdef UNITY_OUTPUT_FLUSH_HEADER_DECLARATION
-extern void UNITY_OMIT_OUTPUT_FLUSH_HEADER_DECLARATION;
-#endif
-#endif
-
-#ifndef UNITY_OUTPUT_FLUSH
-#define UNITY_FLUSH_CALL()
-#else
-#define UNITY_FLUSH_CALL() UNITY_OUTPUT_FLUSH()
-#endif
-
-#ifndef UNITY_PRINT_EOL
-#define UNITY_PRINT_EOL()    UNITY_OUTPUT_CHAR('\n')
-#endif
-
-#ifndef UNITY_OUTPUT_START
-#define UNITY_OUTPUT_START()
-#endif
-
-#ifndef UNITY_OUTPUT_COMPLETE
-#define UNITY_OUTPUT_COMPLETE()
-#endif
-
-/*-------------------------------------------------------
- * Footprint
- *-------------------------------------------------------*/
-
-#ifndef UNITY_LINE_TYPE
-#define UNITY_LINE_TYPE UNITY_UINT
-#endif
-
-#ifndef UNITY_COUNTER_TYPE
-#define UNITY_COUNTER_TYPE UNITY_UINT
-#endif
-
-/*-------------------------------------------------------
- * Language Features Available
- *-------------------------------------------------------*/
-#if !defined(UNITY_WEAK_ATTRIBUTE) && !defined(UNITY_WEAK_PRAGMA)
-#   if defined(__GNUC__) || defined(__ghs__) /* __GNUC__ includes clang */
-#       if !(defined(__WIN32__) && defined(__clang__)) && !defined(__TMS470__)
-#           define UNITY_WEAK_ATTRIBUTE __attribute__((weak))
-#       endif
-#   endif
-#endif
-
-#ifdef UNITY_NO_WEAK
-#   undef UNITY_WEAK_ATTRIBUTE
-#   undef UNITY_WEAK_PRAGMA
-#endif
-
-
-/*-------------------------------------------------------
- * Internal Structs Needed
- *-------------------------------------------------------*/
-
-typedef void (*UnityTestFunction)(void);
-
-#define UNITY_DISPLAY_RANGE_INT  (0x10)
-#define UNITY_DISPLAY_RANGE_UINT (0x20)
-#define UNITY_DISPLAY_RANGE_HEX  (0x40)
-
-typedef enum
-{
-UNITY_DISPLAY_STYLE_INT = sizeof(int)+ UNITY_DISPLAY_RANGE_INT,
-    UNITY_DISPLAY_STYLE_INT8     = 1 + UNITY_DISPLAY_RANGE_INT,
-    UNITY_DISPLAY_STYLE_INT16    = 2 + UNITY_DISPLAY_RANGE_INT,
-    UNITY_DISPLAY_STYLE_INT32    = 4 + UNITY_DISPLAY_RANGE_INT,
-#ifdef UNITY_SUPPORT_64
-    UNITY_DISPLAY_STYLE_INT64    = 8 + UNITY_DISPLAY_RANGE_INT,
-#endif
-
-UNITY_DISPLAY_STYLE_UINT = sizeof(unsigned) + UNITY_DISPLAY_RANGE_UINT,
-    UNITY_DISPLAY_STYLE_UINT8    = 1 + UNITY_DISPLAY_RANGE_UINT,
-    UNITY_DISPLAY_STYLE_UINT16   = 2 + UNITY_DISPLAY_RANGE_UINT,
-    UNITY_DISPLAY_STYLE_UINT32   = 4 + UNITY_DISPLAY_RANGE_UINT,
-#ifdef UNITY_SUPPORT_64
-    UNITY_DISPLAY_STYLE_UINT64   = 8 + UNITY_DISPLAY_RANGE_UINT,
-#endif
-
-    UNITY_DISPLAY_STYLE_HEX8     = 1 + UNITY_DISPLAY_RANGE_HEX,
-    UNITY_DISPLAY_STYLE_HEX16    = 2 + UNITY_DISPLAY_RANGE_HEX,
-    UNITY_DISPLAY_STYLE_HEX32    = 4 + UNITY_DISPLAY_RANGE_HEX,
-#ifdef UNITY_SUPPORT_64
-    UNITY_DISPLAY_STYLE_HEX64    = 8 + UNITY_DISPLAY_RANGE_HEX,
-#endif
-
-    UNITY_DISPLAY_STYLE_UNKNOWN
-} UNITY_DISPLAY_STYLE_T;
-
-typedef enum
-{
-    UNITY_EQUAL_TO         = 1,
-    UNITY_GREATER_THAN     = 2,
-    UNITY_GREATER_OR_EQUAL = 2 + UNITY_EQUAL_TO,
-    UNITY_SMALLER_THAN     = 4,
-    UNITY_SMALLER_OR_EQUAL = 4 + UNITY_EQUAL_TO
-} UNITY_COMPARISON_T;
-
-#ifndef UNITY_EXCLUDE_FLOAT
-typedef enum UNITY_FLOAT_TRAIT
-{
-    UNITY_FLOAT_IS_NOT_INF       = 0,
-    UNITY_FLOAT_IS_INF,
-    UNITY_FLOAT_IS_NOT_NEG_INF,
-    UNITY_FLOAT_IS_NEG_INF,
-    UNITY_FLOAT_IS_NOT_NAN,
-    UNITY_FLOAT_IS_NAN,
-    UNITY_FLOAT_IS_NOT_DET,
-    UNITY_FLOAT_IS_DET,
-    UNITY_FLOAT_INVALID_TRAIT
-} UNITY_FLOAT_TRAIT_T;
-#endif
-
-typedef enum
-{
-    UNITY_ARRAY_TO_VAL = 0,
-    UNITY_ARRAY_TO_ARRAY
-} UNITY_FLAGS_T;
-
-struct UNITY_STORAGE_T
-{
-    const char* TestFile;
-    const char* CurrentTestName;
-#ifndef UNITY_EXCLUDE_DETAILS
-    const char* CurrentDetail1;
-    const char* CurrentDetail2;
-#endif
-    UNITY_LINE_TYPE CurrentTestLineNumber;
-    UNITY_COUNTER_TYPE NumberOfTests;
-    UNITY_COUNTER_TYPE TestFailures;
-    UNITY_COUNTER_TYPE TestIgnores;
-    UNITY_COUNTER_TYPE CurrentTestFailed;
-    UNITY_COUNTER_TYPE CurrentTestIgnored;
-#ifndef UNITY_EXCLUDE_SETJMP_H
-    jmp_buf AbortFrame;
-#endif
-};
-
-extern struct UNITY_STORAGE_T Unity;
-
-/*-------------------------------------------------------
- * Test Suite Management
- *-------------------------------------------------------*/
-
-void UnityBegin(const char* filename);
-int  UnityEnd(void);
-void UnityConcludeTest(void);
-void UnityDefaultTestRun(UnityTestFunction Func, const char* FuncName, const int FuncLineNum);
-
-/*-------------------------------------------------------
- * Details Support
- *-------------------------------------------------------*/
-
-#ifdef UNITY_EXCLUDE_DETAILS
-#define UNITY_CLR_DETAILS()
-#define UNITY_SET_DETAIL(d1)
-#define UNITY_SET_DETAILS(d1,d2)
-#else
-#define UNITY_CLR_DETAILS()      { Unity.CurrentDetail1 = 0;   Unity.CurrentDetail2 = 0;  }
-#define UNITY_SET_DETAIL(d1)     { Unity.CurrentDetail1 = d1;  Unity.CurrentDetail2 = 0;  }
-#define UNITY_SET_DETAILS(d1,d2) { Unity.CurrentDetail1 = d1;  Unity.CurrentDetail2 = d2; }
-
-#ifndef UNITY_DETAIL1_NAME
-#define UNITY_DETAIL1_NAME "Function"
-#endif
-
-#ifndef UNITY_DETAIL2_NAME
-#define UNITY_DETAIL2_NAME "Argument"
-#endif
-#endif
-
-/*-------------------------------------------------------
- * Test Output
- *-------------------------------------------------------*/
-
-void UnityPrint(const char* string);
-void UnityPrintLen(const char* string, const UNITY_UINT32 length);
-void UnityPrintMask(const UNITY_UINT mask, const UNITY_UINT number);
-void UnityPrintNumberByStyle(const UNITY_INT number, const UNITY_DISPLAY_STYLE_T style);
-void UnityPrintNumber(const UNITY_INT number);
-void UnityPrintNumberUnsigned(const UNITY_UINT number);
-void UnityPrintNumberHex(const UNITY_UINT number, const char nibbles);
-
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-void UnityPrintFloat(const UNITY_DOUBLE input_number);
-#endif
-
-/*-------------------------------------------------------
- * Test Assertion Functions
- *-------------------------------------------------------
- *  Use the macros below this section instead of calling
- *  these directly. The macros have a consistent naming
- *  convention and will pull in file and line information
- *  for you. */
-
-void UnityAssertEqualNumber(const UNITY_INT expected,
-                            const UNITY_INT actual,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber,
-                            const UNITY_DISPLAY_STYLE_T style);
-
-void UnityAssertGreaterOrLessOrEqualNumber(const UNITY_INT threshold,
-                                           const UNITY_INT actual,
-                                           const UNITY_COMPARISON_T compare,
-                                           const char *msg,
-                                           const UNITY_LINE_TYPE lineNumber,
-                                           const UNITY_DISPLAY_STYLE_T style);
-
-void UnityAssertEqualIntArray(UNITY_INTERNAL_PTR expected,
-                              UNITY_INTERNAL_PTR actual,
-                              const UNITY_UINT32 num_elements,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_DISPLAY_STYLE_T style,
-                              const UNITY_FLAGS_T flags);
-
-void UnityAssertBits(const UNITY_INT mask,
-                     const UNITY_INT expected,
-                     const UNITY_INT actual,
-                     const char* msg,
-                     const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualString(const char* expected,
-                            const char* actual,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualStringLen(const char* expected,
-                            const char* actual,
-                            const UNITY_UINT32 length,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualStringArray( UNITY_INTERNAL_PTR expected,
-                                  const char** actual,
-                                  const UNITY_UINT32 num_elements,
-                                  const char* msg,
-                                  const UNITY_LINE_TYPE lineNumber,
-                                  const UNITY_FLAGS_T flags);
-
-void UnityAssertEqualMemory( UNITY_INTERNAL_PTR expected,
-                             UNITY_INTERNAL_PTR actual,
-                             const UNITY_UINT32 length,
-                             const UNITY_UINT32 num_elements,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber,
-                             const UNITY_FLAGS_T flags);
-
-void UnityAssertNumbersWithin(const UNITY_UINT delta,
-                              const UNITY_INT expected,
-                              const UNITY_INT actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_DISPLAY_STYLE_T style);
-
-void UnityFail(const char* message, const UNITY_LINE_TYPE line);
-
-void UnityIgnore(const char* message, const UNITY_LINE_TYPE line);
-
-#ifndef UNITY_EXCLUDE_FLOAT
-void UnityAssertFloatsWithin(const UNITY_FLOAT delta,
-                             const UNITY_FLOAT expected,
-                             const UNITY_FLOAT actual,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualFloatArray(UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* expected,
-                                UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* actual,
-                                const UNITY_UINT32 num_elements,
-                                const char* msg,
-                                const UNITY_LINE_TYPE lineNumber,
-                                const UNITY_FLAGS_T flags);
-
-void UnityAssertFloatSpecial(const UNITY_FLOAT actual,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber,
-                             const UNITY_FLOAT_TRAIT_T style);
-#endif
-
-#ifndef UNITY_EXCLUDE_DOUBLE
-void UnityAssertDoublesWithin(const UNITY_DOUBLE delta,
-                              const UNITY_DOUBLE expected,
-                              const UNITY_DOUBLE actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualDoubleArray(UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* expected,
-                                 UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* actual,
-                                 const UNITY_UINT32 num_elements,
-                                 const char* msg,
-                                 const UNITY_LINE_TYPE lineNumber,
-                                 const UNITY_FLAGS_T flags);
-
-void UnityAssertDoubleSpecial(const UNITY_DOUBLE actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_FLOAT_TRAIT_T style);
-#endif
-
-/*-------------------------------------------------------
- * Helpers
- *-------------------------------------------------------*/
-
-UNITY_INTERNAL_PTR UnityNumToPtr(const UNITY_INT num, const UNITY_UINT8 size);
-#ifndef UNITY_EXCLUDE_FLOAT
-UNITY_INTERNAL_PTR UnityFloatToPtr(const float num);
-#endif
-#ifndef UNITY_EXCLUDE_DOUBLE
-UNITY_INTERNAL_PTR UnityDoubleToPtr(const double num);
-#endif
-
-/*-------------------------------------------------------
- * Error Strings We Might Need
- *-------------------------------------------------------*/
-
-extern const char UnityStrErrFloat[];
-extern const char UnityStrErrDouble[];
-extern const char UnityStrErr64[];
-
-/*-------------------------------------------------------
- * Test Running Macros
- *-------------------------------------------------------*/
-
-#ifndef UNITY_EXCLUDE_SETJMP_H
-#define TEST_PROTECT() (setjmp(Unity.AbortFrame) == 0)
-#define TEST_ABORT() longjmp(Unity.AbortFrame, 1)
-#else
-#define TEST_PROTECT() 1
-#define TEST_ABORT() return
-#endif
-
-/* This tricky series of macros gives us an optional line argument to treat it as RUN_TEST(func, num=__LINE__) */
-#ifndef RUN_TEST
-#ifdef __STDC_VERSION__
-#if __STDC_VERSION__ >= 199901L
-#define RUN_TEST(...) UnityDefaultTestRun(RUN_TEST_FIRST(__VA_ARGS__), RUN_TEST_SECOND(__VA_ARGS__))
-#define RUN_TEST_FIRST(...) RUN_TEST_FIRST_HELPER(__VA_ARGS__, throwaway)
-#define RUN_TEST_FIRST_HELPER(first, ...) (first), #first
-#define RUN_TEST_SECOND(...) RUN_TEST_SECOND_HELPER(__VA_ARGS__, __LINE__, throwaway)
-#define RUN_TEST_SECOND_HELPER(first, second, ...) (second)
-#endif
-#endif
-#endif
-
-/* If we can't do the tricky version, we'll just have to require them to always include the line number */
-#ifndef RUN_TEST
-#ifdef CMOCK
-#define RUN_TEST(func, num) UnityDefaultTestRun(func, #func, num)
-#else
-#define RUN_TEST(func) UnityDefaultTestRun(func, #func, __LINE__)
-#endif
-#endif
-
-#define TEST_LINE_NUM (Unity.CurrentTestLineNumber)
-#define TEST_IS_IGNORED (Unity.CurrentTestIgnored)
-#define UNITY_NEW_TEST(a) \
-    Unity.CurrentTestName = (a); \
-    Unity.CurrentTestLineNumber = (UNITY_LINE_TYPE)(__LINE__); \
-    Unity.NumberOfTests++;
-
-#ifndef UNITY_BEGIN
-#define UNITY_BEGIN() UnityBegin(__FILE__)
-#endif
-
-#ifndef UNITY_END
-#define UNITY_END() UnityEnd()
-#endif
-
-/*-----------------------------------------------
- * Command Line Argument Support
- *-----------------------------------------------*/
-
-#ifdef UNITY_USE_COMMAND_LINE_ARGS
-int UnityParseOptions(int argc, char** argv);
-int UnityTestMatches(void);
-#endif
-
-/*-------------------------------------------------------
- * Basic Fail and Ignore
- *-------------------------------------------------------*/
-
-#define UNITY_TEST_FAIL(line, message)   UnityFail(   (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_IGNORE(line, message) UnityIgnore( (message), (UNITY_LINE_TYPE)(line))
-
-/*-------------------------------------------------------
- * Test Asserts
- *-------------------------------------------------------*/
-
-#define UNITY_TEST_ASSERT(condition, line, message)                                              if (condition) {} else {UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), (message));}
-#define UNITY_TEST_ASSERT_NULL(pointer, line, message)                                           UNITY_TEST_ASSERT(((pointer) == NULL),  (UNITY_LINE_TYPE)(line), (message))
-#define UNITY_TEST_ASSERT_NOT_NULL(pointer, line, message)                                       UNITY_TEST_ASSERT(((pointer) != NULL),  (UNITY_LINE_TYPE)(line), (message))
-
-#define UNITY_TEST_ASSERT_EQUAL_INT(expected, actual, line, message)                             UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_EQUAL_INT8(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_EQUAL_INT16(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT16)(expected), (UNITY_INT)(UNITY_INT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_EQUAL_INT32(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT32)(expected), (UNITY_INT)(UNITY_INT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_EQUAL_UINT(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_EQUAL_UINT8(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_UINT8 )(expected), (UNITY_INT)(UNITY_UINT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_EQUAL_UINT16(expected, actual, line, message)                          UnityAssertEqualNumber((UNITY_INT)(UNITY_UINT16)(expected), (UNITY_INT)(UNITY_UINT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_EQUAL_UINT32(expected, actual, line, message)                          UnityAssertEqualNumber((UNITY_INT)(UNITY_UINT32)(expected), (UNITY_INT)(UNITY_UINT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_EQUAL_HEX8(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_EQUAL_HEX16(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT16)(expected), (UNITY_INT)(UNITY_INT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_EQUAL_HEX32(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT32)(expected), (UNITY_INT)(UNITY_INT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-#define UNITY_TEST_ASSERT_BITS(mask, expected, actual, line, message)                            UnityAssertBits((UNITY_INT)(mask), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line))
-
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT8(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT16(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT32(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT8(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT16(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT32(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT(threshold, actual, line, message)                 UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT8(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT16(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT32(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT(threshold, actual, line, message)                 UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT8(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT16(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT32(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_INT_WITHIN(delta, expected, actual, line, message)                     UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_INT8_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_INT16_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT16)(delta), (UNITY_INT)(UNITY_INT16)(expected), (UNITY_INT)(UNITY_INT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_INT32_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT32)(delta), (UNITY_INT)(UNITY_INT32)(expected), (UNITY_INT)(UNITY_INT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_UINT_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_UINT8_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_UINT16_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((UNITY_UINT16)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_UINT32_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((UNITY_UINT32)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_HEX8_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_HEX16_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT16)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_HEX32_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT32)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_EQUAL_PTR(expected, actual, line, message)                             UnityAssertEqualNumber((UNITY_PTR_TO_INT)(expected), (UNITY_PTR_TO_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_POINTER)
-#define UNITY_TEST_ASSERT_EQUAL_STRING(expected, actual, line, message)                          UnityAssertEqualString((const char*)(expected), (const char*)(actual), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_STRING_LEN(expected, actual, len, line, message)                 UnityAssertEqualStringLen((const char*)(expected), (const char*)(actual), (UNITY_UINT32)(len), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_MEMORY(expected, actual, len, line, message)                     UnityAssertEqualMemory((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(len), 1, (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-
-#define UNITY_TEST_ASSERT_EQUAL_INT_ARRAY(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT,     UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_INT8_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8,    UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_INT16_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_INT32_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT,    UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT8_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT16_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT32_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX8_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8,    UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX16_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_PTR_ARRAY(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_POINTER, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_STRING_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualStringArray((UNITY_INTERNAL_PTR)(expected), (const char**)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY(expected, actual, len, num_elements, line, message) UnityAssertEqualMemory((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(len), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT(expected, actual, num_elements, line, message)          UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)              expected, sizeof(int)),  (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT,     UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT8(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT8  )expected, 1),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8,    UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT16(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT16 )expected, 2),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT32(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT32 )expected, 4),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)              expected, sizeof(unsigned int)), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT,    UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT8(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT8 )expected, 1),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT16(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT16)expected, 2),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT32(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT32)expected, 4),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX8(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT8  )expected, 1),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8,    UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX16(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT16 )expected, 2),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX32(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT32 )expected, 4),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_PTR(expected, actual, num_elements, line, message)          UnityAssertEqualIntArray(UnityNumToPtr((UNITY_PTR_TO_INT)       expected, sizeof(int*)), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_POINTER, UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_STRING(expected, actual, num_elements, line, message)       UnityAssertEqualStringArray((UNITY_INTERNAL_PTR)(expected), (const char**)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_MEMORY(expected, actual, len, num_elements, line, message)  UnityAssertEqualMemory((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(len), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-
-#ifdef UNITY_SUPPORT_64
-#define UNITY_TEST_ASSERT_EQUAL_INT64(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64(expected, actual, line, message)                          UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT64(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT64)expected, 8), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT64(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT64)expected, 8), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64, UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX64(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT64)expected, 8), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_INT64_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_UINT64_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_HEX64_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT64(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#else
-#define UNITY_TEST_ASSERT_EQUAL_INT64(expected, actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64(expected, actual, line, message)                          UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64(expected, actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY(expected, actual, num_elements, line, message)      UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_INT64_WITHIN(delta, expected, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_UINT64_WITHIN(delta, expected, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_HEX64_WITHIN(delta, expected, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64(threshold, actual, line, message)              UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT64(threshold, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64(threshold, actual, line, message)              UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#endif
-
-#ifdef UNITY_EXCLUDE_FLOAT
-#define UNITY_TEST_ASSERT_FLOAT_WITHIN(delta, expected, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT(expected, actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT(expected, actual, num_elements, line, message)        UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_INF(actual, line, message)                                    UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF(actual, line, message)                                UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NAN(actual, line, message)                                    UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE(actual, line, message)                            UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF(actual, line, message)                                UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF(actual, line, message)                            UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN(actual, line, message)                                UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE(actual, line, message)                        UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#else
-#define UNITY_TEST_ASSERT_FLOAT_WITHIN(delta, expected, actual, line, message)                   UnityAssertFloatsWithin((UNITY_FLOAT)(delta), (UNITY_FLOAT)(expected), (UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT(expected, actual, line, message)                           UNITY_TEST_ASSERT_FLOAT_WITHIN((UNITY_FLOAT)(expected) * (UNITY_FLOAT)UNITY_FLOAT_PRECISION, (UNITY_FLOAT)(expected), (UNITY_FLOAT)(actual), (UNITY_LINE_TYPE)(line), (message))
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualFloatArray((UNITY_FLOAT*)(expected), (UNITY_FLOAT*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT(expected, actual, num_elements, line, message)        UnityAssertEqualFloatArray(UnityFloatToPtr(expected), (UNITY_FLOAT*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_FLOAT_IS_INF(actual, line, message)                                    UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF(actual, line, message)                                UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NEG_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NAN(actual, line, message)                                    UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NAN)
-#define UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE(actual, line, message)                            UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_DET)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF(actual, line, message)                                UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF(actual, line, message)                            UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NEG_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN(actual, line, message)                                UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NAN)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE(actual, line, message)                        UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_DET)
-#endif
-
-#ifdef UNITY_EXCLUDE_DOUBLE
-#define UNITY_TEST_ASSERT_DOUBLE_WITHIN(delta, expected, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE(expected, actual, line, message)                          UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY(expected, actual, num_elements, line, message)      UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_INF(actual, line, message)                                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF(actual, line, message)                               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NAN(actual, line, message)                                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE(actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF(actual, line, message)                               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF(actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN(actual, line, message)                               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual, line, message)                       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#else
-#define UNITY_TEST_ASSERT_DOUBLE_WITHIN(delta, expected, actual, line, message)                  UnityAssertDoublesWithin((UNITY_DOUBLE)(delta), (UNITY_DOUBLE)(expected), (UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)line)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE(expected, actual, line, message)                          UNITY_TEST_ASSERT_DOUBLE_WITHIN((UNITY_DOUBLE)(expected) * (UNITY_DOUBLE)UNITY_DOUBLE_PRECISION, (UNITY_DOUBLE)expected, (UNITY_DOUBLE)actual, (UNITY_LINE_TYPE)(line), message)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualDoubleArray((UNITY_DOUBLE*)(expected), (UNITY_DOUBLE*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)line, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE(expected, actual, num_elements, line, message)       UnityAssertEqualDoubleArray(UnityDoubleToPtr(expected), (UNITY_DOUBLE*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)line, UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_INF(actual, line, message)                                   UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF(actual, line, message)                               UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NEG_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NAN(actual, line, message)                                   UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NAN)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE(actual, line, message)                           UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_DET)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF(actual, line, message)                               UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF(actual, line, message)                           UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NEG_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN(actual, line, message)                               UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NAN)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual, line, message)                       UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_DET)
-#endif
-
-/* End of UNITY_INTERNALS_H */
-#endif
diff --git a/tools/sdk/include/json/tests/unity/test/expectdata/testsample_head1.h b/tools/sdk/include/json/tests/unity/test/expectdata/testsample_head1.h
deleted file mode 100644
index da6b7ab26bb..00000000000
--- a/tools/sdk/include/json/tests/unity/test/expectdata/testsample_head1.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* AUTOGENERATED FILE. DO NOT EDIT. */
-#ifndef _TESTSAMPLE_HEAD1_H
-#define _TESTSAMPLE_HEAD1_H
-
-#include "unity.h"
-#include "funky.h"
-#include "stanky.h"
-#include <setjmp.h>
-
-void test_TheFirstThingToTest(void);
-void test_TheSecondThingToTest(void);
-void test_TheThirdThingToTest(void);
-void test_TheFourthThingToTest(void);
-#endif
-
diff --git a/tools/sdk/include/json/tests/unity/test/expectdata/testsample_mock_head1.h b/tools/sdk/include/json/tests/unity/test/expectdata/testsample_mock_head1.h
deleted file mode 100644
index 30c509ad077..00000000000
--- a/tools/sdk/include/json/tests/unity/test/expectdata/testsample_mock_head1.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* AUTOGENERATED FILE. DO NOT EDIT. */
-#ifndef _TESTSAMPLE_MOCK_HEAD1_H
-#define _TESTSAMPLE_MOCK_HEAD1_H
-
-#include "unity.h"
-#include "cmock.h"
-#include "funky.h"
-#include <setjmp.h>
-
-void test_TheFirstThingToTest(void);
-void test_TheSecondThingToTest(void);
-#endif
-
diff --git a/tools/sdk/include/json/tests/unity/test/testdata/CException.h b/tools/sdk/include/json/tests/unity/test/testdata/CException.h
deleted file mode 100644
index 91ad3e1bf22..00000000000
--- a/tools/sdk/include/json/tests/unity/test/testdata/CException.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef CEXCEPTION_H
-#define CEXCEPTION_H
-
-#define CEXCEPTION_BEING_USED 1
-
-#define CEXCEPTION_NONE 0
-#define CEXCEPTION_T int e = 1; (void)
-#define Try          if (e)
-#define Catch(a)     if (!a)
-
-#endif //CEXCEPTION_H
diff --git a/tools/sdk/include/json/tests/unity/test/testdata/Defs.h b/tools/sdk/include/json/tests/unity/test/testdata/Defs.h
deleted file mode 100644
index d3a90c0d506..00000000000
--- a/tools/sdk/include/json/tests/unity/test/testdata/Defs.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef DEF_H
-#define DEF_H
-
-#define EXTERN_DECL
-
-extern int CounterSuiteSetup;
-
-#endif //DEF_H
diff --git a/tools/sdk/include/json/tests/unity/test/testdata/cmock.h b/tools/sdk/include/json/tests/unity/test/testdata/cmock.h
deleted file mode 100644
index c6149be1b01..00000000000
--- a/tools/sdk/include/json/tests/unity/test/testdata/cmock.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef CMOCK_H
-#define CMOCK_H
-
-int CMockMemFreeFinalCounter = 0;
-int mockMock_Init_Counter = 0;
-int mockMock_Verify_Counter = 0;
-int mockMock_Destroy_Counter = 0;
-
-void CMock_Guts_MemFreeFinal(void) { CMockMemFreeFinalCounter++; }
-void mockMock_Init(void)           { mockMock_Init_Counter++;    }
-void mockMock_Verify(void)         { mockMock_Verify_Counter++;  }
-void mockMock_Destroy(void)        { mockMock_Destroy_Counter++; }
-
-#endif //CMOCK_H
diff --git a/tools/sdk/include/json/tests/unity/test/testdata/mockMock.h b/tools/sdk/include/json/tests/unity/test/testdata/mockMock.h
deleted file mode 100644
index 0a2c616f797..00000000000
--- a/tools/sdk/include/json/tests/unity/test/testdata/mockMock.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef MOCK_MOCK_H
-#define MOCK_MOCK_H
-
-extern int mockMock_Init_Counter;
-extern int mockMock_Verify_Counter;
-extern int mockMock_Destroy_Counter;
-extern int CMockMemFreeFinalCounter;
-
-void mockMock_Init(void);
-void mockMock_Verify(void);
-void mockMock_Destroy(void);
-
-#endif //MOCK_MOCK_H
diff --git a/tools/sdk/include/libsodium/sodium.h b/tools/sdk/include/libsodium/sodium.h
deleted file mode 100644
index d0bb25c8741..00000000000
--- a/tools/sdk/include/libsodium/sodium.h
+++ /dev/null
@@ -1,68 +0,0 @@
-
-#ifndef sodium_H
-#define sodium_H
-
-#include "sodium/version.h"
-
-#include "sodium/core.h"
-#include "sodium/crypto_aead_aes256gcm.h"
-#include "sodium/crypto_aead_chacha20poly1305.h"
-#include "sodium/crypto_aead_xchacha20poly1305.h"
-#include "sodium/crypto_auth.h"
-#include "sodium/crypto_auth_hmacsha256.h"
-#include "sodium/crypto_auth_hmacsha512.h"
-#include "sodium/crypto_auth_hmacsha512256.h"
-#include "sodium/crypto_box.h"
-#include "sodium/crypto_box_curve25519xsalsa20poly1305.h"
-#include "sodium/crypto_core_hsalsa20.h"
-#include "sodium/crypto_core_hchacha20.h"
-#include "sodium/crypto_core_salsa20.h"
-#include "sodium/crypto_core_salsa2012.h"
-#include "sodium/crypto_core_salsa208.h"
-#include "sodium/crypto_generichash.h"
-#include "sodium/crypto_generichash_blake2b.h"
-#include "sodium/crypto_hash.h"
-#include "sodium/crypto_hash_sha256.h"
-#include "sodium/crypto_hash_sha512.h"
-#include "sodium/crypto_kdf.h"
-#include "sodium/crypto_kdf_blake2b.h"
-#include "sodium/crypto_kx.h"
-#include "sodium/crypto_onetimeauth.h"
-#include "sodium/crypto_onetimeauth_poly1305.h"
-#include "sodium/crypto_pwhash.h"
-#include "sodium/crypto_pwhash_argon2i.h"
-#include "sodium/crypto_pwhash_scryptsalsa208sha256.h"
-#include "sodium/crypto_scalarmult.h"
-#include "sodium/crypto_scalarmult_curve25519.h"
-#include "sodium/crypto_secretbox.h"
-#include "sodium/crypto_secretbox_xsalsa20poly1305.h"
-#include "sodium/crypto_shorthash.h"
-#include "sodium/crypto_shorthash_siphash24.h"
-#include "sodium/crypto_sign.h"
-#include "sodium/crypto_sign_ed25519.h"
-#include "sodium/crypto_stream.h"
-#include "sodium/crypto_stream_chacha20.h"
-#include "sodium/crypto_stream_salsa20.h"
-#include "sodium/crypto_stream_xsalsa20.h"
-#include "sodium/crypto_verify_16.h"
-#include "sodium/crypto_verify_32.h"
-#include "sodium/crypto_verify_64.h"
-#include "sodium/randombytes.h"
-#ifdef __native_client__
-# include "sodium/randombytes_nativeclient.h"
-#endif
-#include "sodium/randombytes_salsa20_random.h"
-#include "sodium/randombytes_sysrandom.h"
-#include "sodium/runtime.h"
-#include "sodium/utils.h"
-
-#ifndef SODIUM_LIBRARY_MINIMAL
-# include "sodium/crypto_box_curve25519xchacha20poly1305.h"
-# include "sodium/crypto_secretbox_xchacha20poly1305.h"
-# include "sodium/crypto_stream_aes128ctr.h"
-# include "sodium/crypto_stream_salsa2012.h"
-# include "sodium/crypto_stream_salsa208.h"
-# include "sodium/crypto_stream_xchacha20.h"
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/core.h b/tools/sdk/include/libsodium/sodium/core.h
deleted file mode 100644
index 3ca447628e4..00000000000
--- a/tools/sdk/include/libsodium/sodium/core.h
+++ /dev/null
@@ -1,19 +0,0 @@
-
-#ifndef sodium_core_H
-#define sodium_core_H
-
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-SODIUM_EXPORT
-int sodium_init(void)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_aead_aes256gcm.h b/tools/sdk/include/libsodium/sodium/crypto_aead_aes256gcm.h
deleted file mode 100644
index 972df54f6ec..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_aead_aes256gcm.h
+++ /dev/null
@@ -1,145 +0,0 @@
-#ifndef crypto_aead_aes256gcm_H
-#define crypto_aead_aes256gcm_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_is_available(void);
-
-#define crypto_aead_aes256gcm_KEYBYTES  32U
-SODIUM_EXPORT
-size_t crypto_aead_aes256gcm_keybytes(void);
-
-#define crypto_aead_aes256gcm_NSECBYTES 0U
-SODIUM_EXPORT
-size_t crypto_aead_aes256gcm_nsecbytes(void);
-
-#define crypto_aead_aes256gcm_NPUBBYTES 12U
-SODIUM_EXPORT
-size_t crypto_aead_aes256gcm_npubbytes(void);
-
-#define crypto_aead_aes256gcm_ABYTES    16U
-SODIUM_EXPORT
-size_t crypto_aead_aes256gcm_abytes(void);
-
-typedef CRYPTO_ALIGN(16) unsigned char crypto_aead_aes256gcm_state[512];
-
-SODIUM_EXPORT
-size_t crypto_aead_aes256gcm_statebytes(void);
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_encrypt(unsigned char *c,
-                                  unsigned long long *clen_p,
-                                  const unsigned char *m,
-                                  unsigned long long mlen,
-                                  const unsigned char *ad,
-                                  unsigned long long adlen,
-                                  const unsigned char *nsec,
-                                  const unsigned char *npub,
-                                  const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_decrypt(unsigned char *m,
-                                  unsigned long long *mlen_p,
-                                  unsigned char *nsec,
-                                  const unsigned char *c,
-                                  unsigned long long clen,
-                                  const unsigned char *ad,
-                                  unsigned long long adlen,
-                                  const unsigned char *npub,
-                                  const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_encrypt_detached(unsigned char *c,
-                                           unsigned char *mac,
-                                           unsigned long long *maclen_p,
-                                           const unsigned char *m,
-                                           unsigned long long mlen,
-                                           const unsigned char *ad,
-                                           unsigned long long adlen,
-                                           const unsigned char *nsec,
-                                           const unsigned char *npub,
-                                           const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_decrypt_detached(unsigned char *m,
-                                           unsigned char *nsec,
-                                           const unsigned char *c,
-                                           unsigned long long clen,
-                                           const unsigned char *mac,
-                                           const unsigned char *ad,
-                                           unsigned long long adlen,
-                                           const unsigned char *npub,
-                                           const unsigned char *k)
-        __attribute__ ((warn_unused_result));
-
-/* -- Precomputation interface -- */
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_beforenm(crypto_aead_aes256gcm_state *ctx_,
-                                   const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_encrypt_afternm(unsigned char *c,
-                                          unsigned long long *clen_p,
-                                          const unsigned char *m,
-                                          unsigned long long mlen,
-                                          const unsigned char *ad,
-                                          unsigned long long adlen,
-                                          const unsigned char *nsec,
-                                          const unsigned char *npub,
-                                          const crypto_aead_aes256gcm_state *ctx_);
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_decrypt_afternm(unsigned char *m,
-                                          unsigned long long *mlen_p,
-                                          unsigned char *nsec,
-                                          const unsigned char *c,
-                                          unsigned long long clen,
-                                          const unsigned char *ad,
-                                          unsigned long long adlen,
-                                          const unsigned char *npub,
-                                          const crypto_aead_aes256gcm_state *ctx_)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_encrypt_detached_afternm(unsigned char *c,
-                                                   unsigned char *mac,
-                                                   unsigned long long *maclen_p,
-                                                   const unsigned char *m,
-                                                   unsigned long long mlen,
-                                                   const unsigned char *ad,
-                                                   unsigned long long adlen,
-                                                   const unsigned char *nsec,
-                                                   const unsigned char *npub,
-                                                   const crypto_aead_aes256gcm_state *ctx_);
-
-SODIUM_EXPORT
-int crypto_aead_aes256gcm_decrypt_detached_afternm(unsigned char *m,
-                                                   unsigned char *nsec,
-                                                   const unsigned char *c,
-                                                   unsigned long long clen,
-                                                   const unsigned char *mac,
-                                                   const unsigned char *ad,
-                                                   unsigned long long adlen,
-                                                   const unsigned char *npub,
-                                                   const crypto_aead_aes256gcm_state *ctx_)
-        __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-void crypto_aead_aes256gcm_keygen(unsigned char k[crypto_aead_aes256gcm_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_aead_chacha20poly1305.h b/tools/sdk/include/libsodium/sodium/crypto_aead_chacha20poly1305.h
deleted file mode 100644
index 0bbc6885934..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_aead_chacha20poly1305.h
+++ /dev/null
@@ -1,162 +0,0 @@
-#ifndef crypto_aead_chacha20poly1305_H
-#define crypto_aead_chacha20poly1305_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-/* -- IETF ChaCha20-Poly1305 construction with a 96-bit nonce and a 32-bit internal counter -- */
-
-#define crypto_aead_chacha20poly1305_ietf_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_aead_chacha20poly1305_ietf_keybytes(void);
-
-#define crypto_aead_chacha20poly1305_ietf_NSECBYTES 0U
-SODIUM_EXPORT
-size_t crypto_aead_chacha20poly1305_ietf_nsecbytes(void);
-
-#define crypto_aead_chacha20poly1305_ietf_NPUBBYTES 12U
-
-SODIUM_EXPORT
-size_t crypto_aead_chacha20poly1305_ietf_npubbytes(void);
-
-#define crypto_aead_chacha20poly1305_ietf_ABYTES 16U
-SODIUM_EXPORT
-size_t crypto_aead_chacha20poly1305_ietf_abytes(void);
-
-SODIUM_EXPORT
-int crypto_aead_chacha20poly1305_ietf_encrypt(unsigned char *c,
-                                              unsigned long long *clen_p,
-                                              const unsigned char *m,
-                                              unsigned long long mlen,
-                                              const unsigned char *ad,
-                                              unsigned long long adlen,
-                                              const unsigned char *nsec,
-                                              const unsigned char *npub,
-                                              const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_aead_chacha20poly1305_ietf_decrypt(unsigned char *m,
-                                              unsigned long long *mlen_p,
-                                              unsigned char *nsec,
-                                              const unsigned char *c,
-                                              unsigned long long clen,
-                                              const unsigned char *ad,
-                                              unsigned long long adlen,
-                                              const unsigned char *npub,
-                                              const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_aead_chacha20poly1305_ietf_encrypt_detached(unsigned char *c,
-                                                       unsigned char *mac,
-                                                       unsigned long long *maclen_p,
-                                                       const unsigned char *m,
-                                                       unsigned long long mlen,
-                                                       const unsigned char *ad,
-                                                       unsigned long long adlen,
-                                                       const unsigned char *nsec,
-                                                       const unsigned char *npub,
-                                                       const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_aead_chacha20poly1305_ietf_decrypt_detached(unsigned char *m,
-                                                       unsigned char *nsec,
-                                                       const unsigned char *c,
-                                                       unsigned long long clen,
-                                                       const unsigned char *mac,
-                                                       const unsigned char *ad,
-                                                       unsigned long long adlen,
-                                                       const unsigned char *npub,
-                                                       const unsigned char *k)
-        __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-void crypto_aead_chacha20poly1305_ietf_keygen(unsigned char k[crypto_aead_chacha20poly1305_ietf_KEYBYTES]);
-
-/* -- Original ChaCha20-Poly1305 construction with a 64-bit nonce and a 64-bit internal counter -- */
-
-#define crypto_aead_chacha20poly1305_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_aead_chacha20poly1305_keybytes(void);
-
-#define crypto_aead_chacha20poly1305_NSECBYTES 0U
-SODIUM_EXPORT
-size_t crypto_aead_chacha20poly1305_nsecbytes(void);
-
-#define crypto_aead_chacha20poly1305_NPUBBYTES 8U
-SODIUM_EXPORT
-size_t crypto_aead_chacha20poly1305_npubbytes(void);
-
-#define crypto_aead_chacha20poly1305_ABYTES 16U
-SODIUM_EXPORT
-size_t crypto_aead_chacha20poly1305_abytes(void);
-
-SODIUM_EXPORT
-int crypto_aead_chacha20poly1305_encrypt(unsigned char *c,
-                                         unsigned long long *clen_p,
-                                         const unsigned char *m,
-                                         unsigned long long mlen,
-                                         const unsigned char *ad,
-                                         unsigned long long adlen,
-                                         const unsigned char *nsec,
-                                         const unsigned char *npub,
-                                         const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_aead_chacha20poly1305_decrypt(unsigned char *m,
-                                         unsigned long long *mlen_p,
-                                         unsigned char *nsec,
-                                         const unsigned char *c,
-                                         unsigned long long clen,
-                                         const unsigned char *ad,
-                                         unsigned long long adlen,
-                                         const unsigned char *npub,
-                                         const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_aead_chacha20poly1305_encrypt_detached(unsigned char *c,
-                                                  unsigned char *mac,
-                                                  unsigned long long *maclen_p,
-                                                  const unsigned char *m,
-                                                  unsigned long long mlen,
-                                                  const unsigned char *ad,
-                                                  unsigned long long adlen,
-                                                  const unsigned char *nsec,
-                                                  const unsigned char *npub,
-                                                  const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_aead_chacha20poly1305_decrypt_detached(unsigned char *m,
-                                                  unsigned char *nsec,
-                                                  const unsigned char *c,
-                                                  unsigned long long clen,
-                                                  const unsigned char *mac,
-                                                  const unsigned char *ad,
-                                                  unsigned long long adlen,
-                                                  const unsigned char *npub,
-                                                  const unsigned char *k)
-        __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-void crypto_aead_chacha20poly1305_keygen(unsigned char k[crypto_aead_chacha20poly1305_KEYBYTES]);
-
-/* Aliases */
-
-#define crypto_aead_chacha20poly1305_IETF_KEYBYTES  crypto_aead_chacha20poly1305_ietf_KEYBYTES
-#define crypto_aead_chacha20poly1305_IETF_NSECBYTES crypto_aead_chacha20poly1305_ietf_NSECBYTES
-#define crypto_aead_chacha20poly1305_IETF_NPUBBYTES crypto_aead_chacha20poly1305_ietf_NPUBBYTES
-#define crypto_aead_chacha20poly1305_IETF_ABYTES    crypto_aead_chacha20poly1305_ietf_ABYTES
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_aead_xchacha20poly1305.h b/tools/sdk/include/libsodium/sodium/crypto_aead_xchacha20poly1305.h
deleted file mode 100644
index f863ce88ca2..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_aead_xchacha20poly1305.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef crypto_aead_xchacha20poly1305_H
-#define crypto_aead_xchacha20poly1305_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_aead_xchacha20poly1305_ietf_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_aead_xchacha20poly1305_ietf_keybytes(void);
-
-#define crypto_aead_xchacha20poly1305_ietf_NSECBYTES 0U
-SODIUM_EXPORT
-size_t crypto_aead_xchacha20poly1305_ietf_nsecbytes(void);
-
-#define crypto_aead_xchacha20poly1305_ietf_NPUBBYTES 24U
-SODIUM_EXPORT
-size_t crypto_aead_xchacha20poly1305_ietf_npubbytes(void);
-
-#define crypto_aead_xchacha20poly1305_ietf_ABYTES 16U
-SODIUM_EXPORT
-size_t crypto_aead_xchacha20poly1305_ietf_abytes(void);
-
-SODIUM_EXPORT
-int crypto_aead_xchacha20poly1305_ietf_encrypt(unsigned char *c,
-                                               unsigned long long *clen_p,
-                                               const unsigned char *m,
-                                               unsigned long long mlen,
-                                               const unsigned char *ad,
-                                               unsigned long long adlen,
-                                               const unsigned char *nsec,
-                                               const unsigned char *npub,
-                                               const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_aead_xchacha20poly1305_ietf_decrypt(unsigned char *m,
-                                               unsigned long long *mlen_p,
-                                               unsigned char *nsec,
-                                               const unsigned char *c,
-                                               unsigned long long clen,
-                                               const unsigned char *ad,
-                                               unsigned long long adlen,
-                                               const unsigned char *npub,
-                                               const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_aead_xchacha20poly1305_ietf_encrypt_detached(unsigned char *c,
-                                                        unsigned char *mac,
-                                                        unsigned long long *maclen_p,
-                                                        const unsigned char *m,
-                                                        unsigned long long mlen,
-                                                        const unsigned char *ad,
-                                                        unsigned long long adlen,
-                                                        const unsigned char *nsec,
-                                                        const unsigned char *npub,
-                                                        const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_aead_xchacha20poly1305_ietf_decrypt_detached(unsigned char *m,
-                                                        unsigned char *nsec,
-                                                        const unsigned char *c,
-                                                        unsigned long long clen,
-                                                        const unsigned char *mac,
-                                                        const unsigned char *ad,
-                                                        unsigned long long adlen,
-                                                        const unsigned char *npub,
-                                                        const unsigned char *k)
-        __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-void crypto_aead_xchacha20poly1305_ietf_keygen(unsigned char k[crypto_aead_xchacha20poly1305_ietf_KEYBYTES]);
-
-/* Aliases */
-
-#define crypto_aead_xchacha20poly1305_IETF_KEYBYTES  crypto_aead_xchacha20poly1305_ietf_KEYBYTES
-#define crypto_aead_xchacha20poly1305_IETF_NSECBYTES crypto_aead_xchacha20poly1305_ietf_NSECBYTES
-#define crypto_aead_xchacha20poly1305_IETF_NPUBBYTES crypto_aead_xchacha20poly1305_ietf_NPUBBYTES
-#define crypto_aead_xchacha20poly1305_IETF_ABYTES    crypto_aead_xchacha20poly1305_ietf_ABYTES
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_auth.h b/tools/sdk/include/libsodium/sodium/crypto_auth.h
deleted file mode 100644
index 7174e7bcedd..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_auth.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef crypto_auth_H
-#define crypto_auth_H
-
-#include <stddef.h>
-
-#include "crypto_auth_hmacsha512256.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_auth_BYTES crypto_auth_hmacsha512256_BYTES
-SODIUM_EXPORT
-size_t  crypto_auth_bytes(void);
-
-#define crypto_auth_KEYBYTES crypto_auth_hmacsha512256_KEYBYTES
-SODIUM_EXPORT
-size_t  crypto_auth_keybytes(void);
-
-#define crypto_auth_PRIMITIVE "hmacsha512256"
-SODIUM_EXPORT
-const char *crypto_auth_primitive(void);
-
-SODIUM_EXPORT
-int crypto_auth(unsigned char *out, const unsigned char *in,
-                unsigned long long inlen, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_auth_verify(const unsigned char *h, const unsigned char *in,
-                       unsigned long long inlen, const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-void crypto_auth_keygen(unsigned char k[crypto_auth_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_auth_hmacsha256.h b/tools/sdk/include/libsodium/sodium/crypto_auth_hmacsha256.h
deleted file mode 100644
index deec5266e68..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_auth_hmacsha256.h
+++ /dev/null
@@ -1,68 +0,0 @@
-#ifndef crypto_auth_hmacsha256_H
-#define crypto_auth_hmacsha256_H
-
-#include <stddef.h>
-#include "crypto_hash_sha256.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_auth_hmacsha256_BYTES 32U
-SODIUM_EXPORT
-size_t crypto_auth_hmacsha256_bytes(void);
-
-#define crypto_auth_hmacsha256_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_auth_hmacsha256_keybytes(void);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha256(unsigned char *out,
-                           const unsigned char *in,
-                           unsigned long long inlen,
-                           const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha256_verify(const unsigned char *h,
-                                  const unsigned char *in,
-                                  unsigned long long inlen,
-                                  const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-/* ------------------------------------------------------------------------- */
-
-typedef struct crypto_auth_hmacsha256_state {
-    crypto_hash_sha256_state ictx;
-    crypto_hash_sha256_state octx;
-} crypto_auth_hmacsha256_state;
-
-SODIUM_EXPORT
-size_t crypto_auth_hmacsha256_statebytes(void);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha256_init(crypto_auth_hmacsha256_state *state,
-                                const unsigned char *key,
-                                size_t keylen);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha256_update(crypto_auth_hmacsha256_state *state,
-                                  const unsigned char *in,
-                                  unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha256_final(crypto_auth_hmacsha256_state *state,
-                                 unsigned char *out);
-
-
-SODIUM_EXPORT
-void crypto_auth_hmacsha256_keygen(unsigned char k[crypto_auth_hmacsha256_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_auth_hmacsha512.h b/tools/sdk/include/libsodium/sodium/crypto_auth_hmacsha512.h
deleted file mode 100644
index 77a55fbc008..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_auth_hmacsha512.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef crypto_auth_hmacsha512_H
-#define crypto_auth_hmacsha512_H
-
-#include <stddef.h>
-#include "crypto_hash_sha512.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_auth_hmacsha512_BYTES 64U
-SODIUM_EXPORT
-size_t crypto_auth_hmacsha512_bytes(void);
-
-#define crypto_auth_hmacsha512_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_auth_hmacsha512_keybytes(void);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512(unsigned char *out,
-                           const unsigned char *in,
-                           unsigned long long inlen,
-                           const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512_verify(const unsigned char *h,
-                                  const unsigned char *in,
-                                  unsigned long long inlen,
-                                  const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-/* ------------------------------------------------------------------------- */
-
-typedef struct crypto_auth_hmacsha512_state {
-    crypto_hash_sha512_state ictx;
-    crypto_hash_sha512_state octx;
-} crypto_auth_hmacsha512_state;
-
-SODIUM_EXPORT
-size_t crypto_auth_hmacsha512_statebytes(void);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512_init(crypto_auth_hmacsha512_state *state,
-                                const unsigned char *key,
-                                size_t keylen);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512_update(crypto_auth_hmacsha512_state *state,
-                                  const unsigned char *in,
-                                  unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512_final(crypto_auth_hmacsha512_state *state,
-                                 unsigned char *out);
-
-SODIUM_EXPORT
-void crypto_auth_hmacsha512_keygen(unsigned char k[crypto_auth_hmacsha512_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_auth_hmacsha512256.h b/tools/sdk/include/libsodium/sodium/crypto_auth_hmacsha512256.h
deleted file mode 100644
index 4842f3debc7..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_auth_hmacsha512256.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef crypto_auth_hmacsha512256_H
-#define crypto_auth_hmacsha512256_H
-
-#include <stddef.h>
-#include "crypto_auth_hmacsha512.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_auth_hmacsha512256_BYTES 32U
-SODIUM_EXPORT
-size_t crypto_auth_hmacsha512256_bytes(void);
-
-#define crypto_auth_hmacsha512256_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_auth_hmacsha512256_keybytes(void);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512256(unsigned char *out, const unsigned char *in,
-                              unsigned long long inlen,const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512256_verify(const unsigned char *h,
-                                     const unsigned char *in,
-                                     unsigned long long inlen,
-                                     const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-/* ------------------------------------------------------------------------- */
-
-typedef crypto_auth_hmacsha512_state crypto_auth_hmacsha512256_state;
-
-SODIUM_EXPORT
-size_t crypto_auth_hmacsha512256_statebytes(void);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512256_init(crypto_auth_hmacsha512256_state *state,
-                                   const unsigned char *key,
-                                   size_t keylen);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512256_update(crypto_auth_hmacsha512256_state *state,
-                                     const unsigned char *in,
-                                     unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_auth_hmacsha512256_final(crypto_auth_hmacsha512256_state *state,
-                                    unsigned char *out);
-
-SODIUM_EXPORT
-void crypto_auth_hmacsha512256_keygen(unsigned char k[crypto_auth_hmacsha512256_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_box.h b/tools/sdk/include/libsodium/sodium/crypto_box.h
deleted file mode 100644
index 614cd1e0ac1..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_box.h
+++ /dev/null
@@ -1,169 +0,0 @@
-#ifndef crypto_box_H
-#define crypto_box_H
-
-/*
- * THREAD SAFETY: crypto_box_keypair() is thread-safe,
- * provided that sodium_init() was called before.
- *
- * Other functions are always thread-safe.
- */
-
-#include <stddef.h>
-
-#include "crypto_box_curve25519xsalsa20poly1305.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_box_SEEDBYTES crypto_box_curve25519xsalsa20poly1305_SEEDBYTES
-SODIUM_EXPORT
-size_t  crypto_box_seedbytes(void);
-
-#define crypto_box_PUBLICKEYBYTES crypto_box_curve25519xsalsa20poly1305_PUBLICKEYBYTES
-SODIUM_EXPORT
-size_t  crypto_box_publickeybytes(void);
-
-#define crypto_box_SECRETKEYBYTES crypto_box_curve25519xsalsa20poly1305_SECRETKEYBYTES
-SODIUM_EXPORT
-size_t  crypto_box_secretkeybytes(void);
-
-#define crypto_box_NONCEBYTES crypto_box_curve25519xsalsa20poly1305_NONCEBYTES
-SODIUM_EXPORT
-size_t  crypto_box_noncebytes(void);
-
-#define crypto_box_MACBYTES crypto_box_curve25519xsalsa20poly1305_MACBYTES
-SODIUM_EXPORT
-size_t  crypto_box_macbytes(void);
-
-#define crypto_box_PRIMITIVE "curve25519xsalsa20poly1305"
-SODIUM_EXPORT
-const char *crypto_box_primitive(void);
-
-SODIUM_EXPORT
-int crypto_box_seed_keypair(unsigned char *pk, unsigned char *sk,
-                            const unsigned char *seed);
-
-SODIUM_EXPORT
-int crypto_box_keypair(unsigned char *pk, unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_box_easy(unsigned char *c, const unsigned char *m,
-                    unsigned long long mlen, const unsigned char *n,
-                    const unsigned char *pk, const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_open_easy(unsigned char *m, const unsigned char *c,
-                         unsigned long long clen, const unsigned char *n,
-                         const unsigned char *pk, const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_detached(unsigned char *c, unsigned char *mac,
-                        const unsigned char *m, unsigned long long mlen,
-                        const unsigned char *n, const unsigned char *pk,
-                        const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_open_detached(unsigned char *m, const unsigned char *c,
-                             const unsigned char *mac,
-                             unsigned long long clen,
-                             const unsigned char *n,
-                             const unsigned char *pk,
-                             const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-/* -- Precomputation interface -- */
-
-#define crypto_box_BEFORENMBYTES crypto_box_curve25519xsalsa20poly1305_BEFORENMBYTES
-SODIUM_EXPORT
-size_t  crypto_box_beforenmbytes(void);
-
-SODIUM_EXPORT
-int crypto_box_beforenm(unsigned char *k, const unsigned char *pk,
-                        const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_easy_afternm(unsigned char *c, const unsigned char *m,
-                            unsigned long long mlen, const unsigned char *n,
-                            const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_box_open_easy_afternm(unsigned char *m, const unsigned char *c,
-                                 unsigned long long clen, const unsigned char *n,
-                                 const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_detached_afternm(unsigned char *c, unsigned char *mac,
-                                const unsigned char *m, unsigned long long mlen,
-                                const unsigned char *n, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_box_open_detached_afternm(unsigned char *m, const unsigned char *c,
-                                     const unsigned char *mac,
-                                     unsigned long long clen, const unsigned char *n,
-                                     const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-/* -- Ephemeral SK interface -- */
-
-#define crypto_box_SEALBYTES (crypto_box_PUBLICKEYBYTES + crypto_box_MACBYTES)
-SODIUM_EXPORT
-size_t crypto_box_sealbytes(void);
-
-SODIUM_EXPORT
-int crypto_box_seal(unsigned char *c, const unsigned char *m,
-                    unsigned long long mlen, const unsigned char *pk);
-
-SODIUM_EXPORT
-int crypto_box_seal_open(unsigned char *m, const unsigned char *c,
-                         unsigned long long clen,
-                         const unsigned char *pk, const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-/* -- NaCl compatibility interface ; Requires padding -- */
-
-#define crypto_box_ZEROBYTES crypto_box_curve25519xsalsa20poly1305_ZEROBYTES
-SODIUM_EXPORT
-size_t  crypto_box_zerobytes(void);
-
-#define crypto_box_BOXZEROBYTES crypto_box_curve25519xsalsa20poly1305_BOXZEROBYTES
-SODIUM_EXPORT
-size_t  crypto_box_boxzerobytes(void);
-
-SODIUM_EXPORT
-int crypto_box(unsigned char *c, const unsigned char *m,
-               unsigned long long mlen, const unsigned char *n,
-               const unsigned char *pk, const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_open(unsigned char *m, const unsigned char *c,
-                    unsigned long long clen, const unsigned char *n,
-                    const unsigned char *pk, const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_afternm(unsigned char *c, const unsigned char *m,
-                       unsigned long long mlen, const unsigned char *n,
-                       const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_box_open_afternm(unsigned char *m, const unsigned char *c,
-                            unsigned long long clen, const unsigned char *n,
-                            const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_box_curve25519xchacha20poly1305.h b/tools/sdk/include/libsodium/sodium/crypto_box_curve25519xchacha20poly1305.h
deleted file mode 100644
index 29c9b255202..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_box_curve25519xchacha20poly1305.h
+++ /dev/null
@@ -1,130 +0,0 @@
-
-#ifndef crypto_box_curve25519xchacha20poly1305_H
-#define crypto_box_curve25519xchacha20poly1305_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_box_curve25519xchacha20poly1305_SEEDBYTES 32U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xchacha20poly1305_seedbytes(void);
-
-#define crypto_box_curve25519xchacha20poly1305_PUBLICKEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xchacha20poly1305_publickeybytes(void);
-
-#define crypto_box_curve25519xchacha20poly1305_SECRETKEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xchacha20poly1305_secretkeybytes(void);
-
-#define crypto_box_curve25519xchacha20poly1305_BEFORENMBYTES 32U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xchacha20poly1305_beforenmbytes(void);
-
-#define crypto_box_curve25519xchacha20poly1305_NONCEBYTES 24U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xchacha20poly1305_noncebytes(void);
-
-#define crypto_box_curve25519xchacha20poly1305_MACBYTES 16U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xchacha20poly1305_macbytes(void);
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_seed_keypair(unsigned char *pk,
-                                                        unsigned char *sk,
-                                                        const unsigned char *seed);
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_keypair(unsigned char *pk,
-                                                   unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_easy(unsigned char *c,
-                                                const unsigned char *m,
-                                                unsigned long long mlen,
-                                                const unsigned char *n,
-                                                const unsigned char *pk,
-                                                const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_open_easy(unsigned char *m,
-                                                     const unsigned char *c,
-                                                     unsigned long long clen,
-                                                     const unsigned char *n,
-                                                     const unsigned char *pk,
-                                                     const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_detached(unsigned char *c,
-                                                    unsigned char *mac,
-                                                    const unsigned char *m,
-                                                    unsigned long long mlen,
-                                                    const unsigned char *n,
-                                                    const unsigned char *pk,
-                                                    const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_open_detached(unsigned char *m,
-                                                         const unsigned char *c,
-                                                         const unsigned char *mac,
-                                                         unsigned long long clen,
-                                                         const unsigned char *n,
-                                                         const unsigned char *pk,
-                                                         const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-/* -- Precomputation interface -- */
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_beforenm(unsigned char *k,
-                                                    const unsigned char *pk,
-                                                    const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_easy_afternm(unsigned char *c,
-                                                        const unsigned char *m,
-                                                        unsigned long long mlen,
-                                                        const unsigned char *n,
-                                                        const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_open_easy_afternm(unsigned char *m,
-                                                             const unsigned char *c,
-                                                             unsigned long long clen,
-                                                             const unsigned char *n,
-                                                             const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_detached_afternm(unsigned char *c,
-                                                            unsigned char *mac,
-                                                            const unsigned char *m,
-                                                            unsigned long long mlen,
-                                                            const unsigned char *n,
-                                                            const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_box_curve25519xchacha20poly1305_open_detached_afternm(unsigned char *m,
-                                                                 const unsigned char *c,
-                                                                 const unsigned char *mac,
-                                                                 unsigned long long clen,
-                                                                 const unsigned char *n,
-                                                                 const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_box_curve25519xsalsa20poly1305.h b/tools/sdk/include/libsodium/sodium/crypto_box_curve25519xsalsa20poly1305.h
deleted file mode 100644
index 9b5a39c3fa4..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_box_curve25519xsalsa20poly1305.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#ifndef crypto_box_curve25519xsalsa20poly1305_H
-#define crypto_box_curve25519xsalsa20poly1305_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_box_curve25519xsalsa20poly1305_SEEDBYTES 32U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xsalsa20poly1305_seedbytes(void);
-
-#define crypto_box_curve25519xsalsa20poly1305_PUBLICKEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xsalsa20poly1305_publickeybytes(void);
-
-#define crypto_box_curve25519xsalsa20poly1305_SECRETKEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xsalsa20poly1305_secretkeybytes(void);
-
-#define crypto_box_curve25519xsalsa20poly1305_BEFORENMBYTES 32U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xsalsa20poly1305_beforenmbytes(void);
-
-#define crypto_box_curve25519xsalsa20poly1305_NONCEBYTES 24U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xsalsa20poly1305_noncebytes(void);
-
-#define crypto_box_curve25519xsalsa20poly1305_MACBYTES 16U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xsalsa20poly1305_macbytes(void);
-
-#define crypto_box_curve25519xsalsa20poly1305_BOXZEROBYTES 16U
-SODIUM_EXPORT
-size_t crypto_box_curve25519xsalsa20poly1305_boxzerobytes(void);
-
-#define crypto_box_curve25519xsalsa20poly1305_ZEROBYTES \
-    (crypto_box_curve25519xsalsa20poly1305_BOXZEROBYTES + \
-     crypto_box_curve25519xsalsa20poly1305_MACBYTES)
-SODIUM_EXPORT
-size_t crypto_box_curve25519xsalsa20poly1305_zerobytes(void);
-
-SODIUM_EXPORT
-int crypto_box_curve25519xsalsa20poly1305(unsigned char *c,
-                                          const unsigned char *m,
-                                          unsigned long long mlen,
-                                          const unsigned char *n,
-                                          const unsigned char *pk,
-                                          const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_curve25519xsalsa20poly1305_open(unsigned char *m,
-                                               const unsigned char *c,
-                                               unsigned long long clen,
-                                               const unsigned char *n,
-                                               const unsigned char *pk,
-                                               const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_curve25519xsalsa20poly1305_seed_keypair(unsigned char *pk,
-                                                       unsigned char *sk,
-                                                       const unsigned char *seed);
-
-SODIUM_EXPORT
-int crypto_box_curve25519xsalsa20poly1305_keypair(unsigned char *pk,
-                                                  unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_box_curve25519xsalsa20poly1305_beforenm(unsigned char *k,
-                                                   const unsigned char *pk,
-                                                   const unsigned char *sk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_box_curve25519xsalsa20poly1305_afternm(unsigned char *c,
-                                                  const unsigned char *m,
-                                                  unsigned long long mlen,
-                                                  const unsigned char *n,
-                                                  const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_box_curve25519xsalsa20poly1305_open_afternm(unsigned char *m,
-                                                       const unsigned char *c,
-                                                       unsigned long long clen,
-                                                       const unsigned char *n,
-                                                       const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_core_hchacha20.h b/tools/sdk/include/libsodium/sodium/crypto_core_hchacha20.h
deleted file mode 100644
index 05e5670c10e..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_core_hchacha20.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef crypto_core_hchacha20_H
-#define crypto_core_hchacha20_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_core_hchacha20_OUTPUTBYTES 32U
-SODIUM_EXPORT
-size_t crypto_core_hchacha20_outputbytes(void);
-
-#define crypto_core_hchacha20_INPUTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_hchacha20_inputbytes(void);
-
-#define crypto_core_hchacha20_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_core_hchacha20_keybytes(void);
-
-#define crypto_core_hchacha20_CONSTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_hchacha20_constbytes(void);
-
-SODIUM_EXPORT
-int crypto_core_hchacha20(unsigned char *out, const unsigned char *in,
-                          const unsigned char *k, const unsigned char *c);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_core_hsalsa20.h b/tools/sdk/include/libsodium/sodium/crypto_core_hsalsa20.h
deleted file mode 100644
index 82e475b8f67..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_core_hsalsa20.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef crypto_core_hsalsa20_H
-#define crypto_core_hsalsa20_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_core_hsalsa20_OUTPUTBYTES 32U
-SODIUM_EXPORT
-size_t crypto_core_hsalsa20_outputbytes(void);
-
-#define crypto_core_hsalsa20_INPUTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_hsalsa20_inputbytes(void);
-
-#define crypto_core_hsalsa20_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_core_hsalsa20_keybytes(void);
-
-#define crypto_core_hsalsa20_CONSTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_hsalsa20_constbytes(void);
-
-SODIUM_EXPORT
-int crypto_core_hsalsa20(unsigned char *out, const unsigned char *in,
-                         const unsigned char *k, const unsigned char *c);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_core_salsa20.h b/tools/sdk/include/libsodium/sodium/crypto_core_salsa20.h
deleted file mode 100644
index 160cc56d2c4..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_core_salsa20.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef crypto_core_salsa20_H
-#define crypto_core_salsa20_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_core_salsa20_OUTPUTBYTES 64U
-SODIUM_EXPORT
-size_t crypto_core_salsa20_outputbytes(void);
-
-#define crypto_core_salsa20_INPUTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_salsa20_inputbytes(void);
-
-#define crypto_core_salsa20_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_core_salsa20_keybytes(void);
-
-#define crypto_core_salsa20_CONSTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_salsa20_constbytes(void);
-
-SODIUM_EXPORT
-int crypto_core_salsa20(unsigned char *out, const unsigned char *in,
-                        const unsigned char *k, const unsigned char *c);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_core_salsa2012.h b/tools/sdk/include/libsodium/sodium/crypto_core_salsa2012.h
deleted file mode 100644
index bdd5f9fdbb2..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_core_salsa2012.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef crypto_core_salsa2012_H
-#define crypto_core_salsa2012_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_core_salsa2012_OUTPUTBYTES 64U
-SODIUM_EXPORT
-size_t crypto_core_salsa2012_outputbytes(void);
-
-#define crypto_core_salsa2012_INPUTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_salsa2012_inputbytes(void);
-
-#define crypto_core_salsa2012_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_core_salsa2012_keybytes(void);
-
-#define crypto_core_salsa2012_CONSTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_salsa2012_constbytes(void);
-
-SODIUM_EXPORT
-int crypto_core_salsa2012(unsigned char *out, const unsigned char *in,
-                          const unsigned char *k, const unsigned char *c);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_core_salsa208.h b/tools/sdk/include/libsodium/sodium/crypto_core_salsa208.h
deleted file mode 100644
index 3c13efa4ef3..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_core_salsa208.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef crypto_core_salsa208_H
-#define crypto_core_salsa208_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_core_salsa208_OUTPUTBYTES 64U
-SODIUM_EXPORT
-size_t crypto_core_salsa208_outputbytes(void);
-
-#define crypto_core_salsa208_INPUTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_salsa208_inputbytes(void);
-
-#define crypto_core_salsa208_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_core_salsa208_keybytes(void);
-
-#define crypto_core_salsa208_CONSTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_core_salsa208_constbytes(void);
-
-SODIUM_EXPORT
-int crypto_core_salsa208(unsigned char *out, const unsigned char *in,
-                         const unsigned char *k, const unsigned char *c);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_generichash.h b/tools/sdk/include/libsodium/sodium/crypto_generichash.h
deleted file mode 100644
index 2398fb9dbba..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_generichash.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef crypto_generichash_H
-#define crypto_generichash_H
-
-#include <stddef.h>
-
-#include "crypto_generichash_blake2b.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_generichash_BYTES_MIN crypto_generichash_blake2b_BYTES_MIN
-SODIUM_EXPORT
-size_t  crypto_generichash_bytes_min(void);
-
-#define crypto_generichash_BYTES_MAX crypto_generichash_blake2b_BYTES_MAX
-SODIUM_EXPORT
-size_t  crypto_generichash_bytes_max(void);
-
-#define crypto_generichash_BYTES crypto_generichash_blake2b_BYTES
-SODIUM_EXPORT
-size_t  crypto_generichash_bytes(void);
-
-#define crypto_generichash_KEYBYTES_MIN crypto_generichash_blake2b_KEYBYTES_MIN
-SODIUM_EXPORT
-size_t  crypto_generichash_keybytes_min(void);
-
-#define crypto_generichash_KEYBYTES_MAX crypto_generichash_blake2b_KEYBYTES_MAX
-SODIUM_EXPORT
-size_t  crypto_generichash_keybytes_max(void);
-
-#define crypto_generichash_KEYBYTES crypto_generichash_blake2b_KEYBYTES
-SODIUM_EXPORT
-size_t  crypto_generichash_keybytes(void);
-
-#define crypto_generichash_PRIMITIVE "blake2b"
-SODIUM_EXPORT
-const char *crypto_generichash_primitive(void);
-
-typedef crypto_generichash_blake2b_state crypto_generichash_state;
-
-SODIUM_EXPORT
-size_t  crypto_generichash_statebytes(void);
-
-SODIUM_EXPORT
-int crypto_generichash(unsigned char *out, size_t outlen,
-                       const unsigned char *in, unsigned long long inlen,
-                       const unsigned char *key, size_t keylen);
-
-SODIUM_EXPORT
-int crypto_generichash_init(crypto_generichash_state *state,
-                            const unsigned char *key,
-                            const size_t keylen, const size_t outlen);
-
-SODIUM_EXPORT
-int crypto_generichash_update(crypto_generichash_state *state,
-                              const unsigned char *in,
-                              unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_generichash_final(crypto_generichash_state *state,
-                             unsigned char *out, const size_t outlen);
-
-SODIUM_EXPORT
-void crypto_generichash_keygen(unsigned char k[crypto_generichash_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_generichash_blake2b.h b/tools/sdk/include/libsodium/sodium/crypto_generichash_blake2b.h
deleted file mode 100644
index 7b0c0820743..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_generichash_blake2b.h
+++ /dev/null
@@ -1,121 +0,0 @@
-#ifndef crypto_generichash_blake2b_H
-#define crypto_generichash_blake2b_H
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#if defined(__IBMC__) || defined(__SUNPRO_C) || defined(__SUNPRO_CC)
-# pragma pack(1)
-#else
-# pragma pack(push, 1)
-#endif
-
-typedef CRYPTO_ALIGN(64) struct crypto_generichash_blake2b_state {
-    uint64_t h[8];
-    uint64_t t[2];
-    uint64_t f[2];
-    uint8_t  buf[2 * 128];
-    size_t   buflen;
-    uint8_t  last_node;
-} crypto_generichash_blake2b_state;
-
-#if defined(__IBMC__) || defined(__SUNPRO_C) || defined(__SUNPRO_CC)
-# pragma pack()
-#else
-# pragma pack(pop)
-#endif
-
-#define crypto_generichash_blake2b_BYTES_MIN     16U
-SODIUM_EXPORT
-size_t crypto_generichash_blake2b_bytes_min(void);
-
-#define crypto_generichash_blake2b_BYTES_MAX     64U
-SODIUM_EXPORT
-size_t crypto_generichash_blake2b_bytes_max(void);
-
-#define crypto_generichash_blake2b_BYTES         32U
-SODIUM_EXPORT
-size_t crypto_generichash_blake2b_bytes(void);
-
-#define crypto_generichash_blake2b_KEYBYTES_MIN  16U
-SODIUM_EXPORT
-size_t crypto_generichash_blake2b_keybytes_min(void);
-
-#define crypto_generichash_blake2b_KEYBYTES_MAX  64U
-SODIUM_EXPORT
-size_t crypto_generichash_blake2b_keybytes_max(void);
-
-#define crypto_generichash_blake2b_KEYBYTES      32U
-SODIUM_EXPORT
-size_t crypto_generichash_blake2b_keybytes(void);
-
-#define crypto_generichash_blake2b_SALTBYTES     16U
-SODIUM_EXPORT
-size_t crypto_generichash_blake2b_saltbytes(void);
-
-#define crypto_generichash_blake2b_PERSONALBYTES 16U
-SODIUM_EXPORT
-size_t crypto_generichash_blake2b_personalbytes(void);
-
-SODIUM_EXPORT
-size_t crypto_generichash_blake2b_statebytes(void);
-
-SODIUM_EXPORT
-int crypto_generichash_blake2b(unsigned char *out, size_t outlen,
-                               const unsigned char *in,
-                               unsigned long long inlen,
-                               const unsigned char *key, size_t keylen);
-
-SODIUM_EXPORT
-int crypto_generichash_blake2b_salt_personal(unsigned char *out, size_t outlen,
-                                             const unsigned char *in,
-                                             unsigned long long inlen,
-                                             const unsigned char *key,
-                                             size_t keylen,
-                                             const unsigned char *salt,
-                                             const unsigned char *personal);
-
-SODIUM_EXPORT
-int crypto_generichash_blake2b_init(crypto_generichash_blake2b_state *state,
-                                    const unsigned char *key,
-                                    const size_t keylen, const size_t outlen);
-
-SODIUM_EXPORT
-int crypto_generichash_blake2b_init_salt_personal(crypto_generichash_blake2b_state *state,
-                                                  const unsigned char *key,
-                                                  const size_t keylen, const size_t outlen,
-                                                  const unsigned char *salt,
-                                                  const unsigned char *personal);
-
-SODIUM_EXPORT
-int crypto_generichash_blake2b_update(crypto_generichash_blake2b_state *state,
-                                      const unsigned char *in,
-                                      unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_generichash_blake2b_final(crypto_generichash_blake2b_state *state,
-                                     unsigned char *out,
-                                     const size_t outlen);
-
-SODIUM_EXPORT
-void crypto_generichash_blake2b_keygen(unsigned char k[crypto_generichash_blake2b_KEYBYTES]);
-
-/* ------------------------------------------------------------------------- */
-
-int _crypto_generichash_blake2b_pick_best_implementation(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_hash.h b/tools/sdk/include/libsodium/sodium/crypto_hash.h
deleted file mode 100644
index 302ed5c5ea2..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_hash.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef crypto_hash_H
-#define crypto_hash_H
-
-/*
- * WARNING: Unless you absolutely need to use SHA512 for interoperatibility,
- * purposes, you might want to consider crypto_generichash() instead.
- * Unlike SHA512, crypto_generichash() is not vulnerable to length
- * extension attacks.
- */
-
-#include <stddef.h>
-
-#include "crypto_hash_sha512.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_hash_BYTES crypto_hash_sha512_BYTES
-SODIUM_EXPORT
-size_t crypto_hash_bytes(void);
-
-SODIUM_EXPORT
-int crypto_hash(unsigned char *out, const unsigned char *in,
-                unsigned long long inlen);
-
-#define crypto_hash_PRIMITIVE "sha512"
-SODIUM_EXPORT
-const char *crypto_hash_primitive(void)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_hash_sha256.h b/tools/sdk/include/libsodium/sodium/crypto_hash_sha256.h
deleted file mode 100644
index f64d16e0e5c..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_hash_sha256.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef crypto_hash_sha256_H
-#define crypto_hash_sha256_H
-
-/*
- * WARNING: Unless you absolutely need to use SHA256 for interoperatibility,
- * purposes, you might want to consider crypto_generichash() instead.
- * Unlike SHA256, crypto_generichash() is not vulnerable to length
- * extension attacks.
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-typedef struct crypto_hash_sha256_state {
-    uint32_t state[8];
-    uint64_t count;
-    uint8_t  buf[64];
-} crypto_hash_sha256_state;
-
-SODIUM_EXPORT
-size_t crypto_hash_sha256_statebytes(void);
-
-#define crypto_hash_sha256_BYTES 32U
-SODIUM_EXPORT
-size_t crypto_hash_sha256_bytes(void);
-
-SODIUM_EXPORT
-int crypto_hash_sha256(unsigned char *out, const unsigned char *in,
-                       unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_hash_sha256_init(crypto_hash_sha256_state *state);
-
-SODIUM_EXPORT
-int crypto_hash_sha256_update(crypto_hash_sha256_state *state,
-                              const unsigned char *in,
-                              unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_hash_sha256_final(crypto_hash_sha256_state *state,
-                             unsigned char *out);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_hash_sha512.h b/tools/sdk/include/libsodium/sodium/crypto_hash_sha512.h
deleted file mode 100644
index 6b0330f14fe..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_hash_sha512.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef crypto_hash_sha512_H
-#define crypto_hash_sha512_H
-
-/*
- * WARNING: Unless you absolutely need to use SHA512 for interoperatibility,
- * purposes, you might want to consider crypto_generichash() instead.
- * Unlike SHA512, crypto_generichash() is not vulnerable to length
- * extension attacks.
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-typedef struct crypto_hash_sha512_state {
-    uint64_t state[8];
-    uint64_t count[2];
-    uint8_t  buf[128];
-} crypto_hash_sha512_state;
-
-SODIUM_EXPORT
-size_t crypto_hash_sha512_statebytes(void);
-
-#define crypto_hash_sha512_BYTES 64U
-SODIUM_EXPORT
-size_t crypto_hash_sha512_bytes(void);
-
-SODIUM_EXPORT
-int crypto_hash_sha512(unsigned char *out, const unsigned char *in,
-                       unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_hash_sha512_init(crypto_hash_sha512_state *state);
-
-SODIUM_EXPORT
-int crypto_hash_sha512_update(crypto_hash_sha512_state *state,
-                              const unsigned char *in,
-                              unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_hash_sha512_final(crypto_hash_sha512_state *state,
-                             unsigned char *out);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_kdf.h b/tools/sdk/include/libsodium/sodium/crypto_kdf.h
deleted file mode 100644
index 52e496a7449..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_kdf.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef crypto_kdf_H
-#define crypto_kdf_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-#include "crypto_kdf_blake2b.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_kdf_BYTES_MIN crypto_kdf_blake2b_BYTES_MIN
-SODIUM_EXPORT
-size_t crypto_kdf_bytes_min(void);
-
-#define crypto_kdf_BYTES_MAX crypto_kdf_blake2b_BYTES_MAX
-SODIUM_EXPORT
-size_t crypto_kdf_bytes_max(void);
-
-#define crypto_kdf_CONTEXTBYTES crypto_kdf_blake2b_CONTEXTBYTES
-SODIUM_EXPORT
-size_t crypto_kdf_contextbytes(void);
-
-#define crypto_kdf_KEYBYTES crypto_kdf_blake2b_KEYBYTES
-SODIUM_EXPORT
-size_t crypto_kdf_keybytes(void);
-
-#define crypto_kdf_PRIMITIVE "blake2b"
-SODIUM_EXPORT
-const char *crypto_kdf_primitive(void)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_kdf_derive_from_key(unsigned char *subkey, size_t subkey_len,
-                               uint64_t subkey_id,
-                               const char ctx[crypto_kdf_CONTEXTBYTES],
-                               const unsigned char key[crypto_kdf_KEYBYTES]);
-
-SODIUM_EXPORT
-void crypto_kdf_keygen(unsigned char k[crypto_kdf_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_kdf_blake2b.h b/tools/sdk/include/libsodium/sodium/crypto_kdf_blake2b.h
deleted file mode 100644
index 5480ebe82f1..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_kdf_blake2b.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef crypto_kdf_blake2b_H
-#define crypto_kdf_blake2b_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-#include "crypto_kdf_blake2b.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_kdf_blake2b_BYTES_MIN 16
-SODIUM_EXPORT
-size_t crypto_kdf_blake2b_bytes_min(void);
-
-#define crypto_kdf_blake2b_BYTES_MAX 64
-SODIUM_EXPORT
-size_t crypto_kdf_blake2b_bytes_max(void);
-
-#define crypto_kdf_blake2b_CONTEXTBYTES 8
-SODIUM_EXPORT
-size_t crypto_kdf_blake2b_contextbytes(void);
-
-#define crypto_kdf_blake2b_KEYBYTES 32
-SODIUM_EXPORT
-size_t crypto_kdf_blake2b_keybytes(void);
-
-SODIUM_EXPORT
-int crypto_kdf_blake2b_derive_from_key(unsigned char *subkey, size_t subkey_len,
-                                       uint64_t subkey_id,
-                                       const char ctx[crypto_kdf_blake2b_CONTEXTBYTES],
-                                       const unsigned char key[crypto_kdf_blake2b_KEYBYTES]);
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_kx.h b/tools/sdk/include/libsodium/sodium/crypto_kx.h
deleted file mode 100644
index d1fce90da57..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_kx.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef crypto_kx_H
-#define crypto_kx_H
-
-#include <stddef.h>
-
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_kx_PUBLICKEYBYTES 32
-SODIUM_EXPORT
-size_t crypto_kx_publickeybytes(void);
-
-#define crypto_kx_SECRETKEYBYTES 32
-SODIUM_EXPORT
-size_t crypto_kx_secretkeybytes(void);
-
-#define crypto_kx_SEEDBYTES 32
-SODIUM_EXPORT
-size_t crypto_kx_seedbytes(void);
-
-#define crypto_kx_SESSIONKEYBYTES 32
-SODIUM_EXPORT
-size_t crypto_kx_sessionkeybytes(void);
-
-#define crypto_kx_PRIMITIVE "x25519blake2b"
-SODIUM_EXPORT
-const char *crypto_kx_primitive(void);
-
-SODIUM_EXPORT
-int crypto_kx_seed_keypair(unsigned char pk[crypto_kx_PUBLICKEYBYTES],
-                           unsigned char sk[crypto_kx_SECRETKEYBYTES],
-                           const unsigned char seed[crypto_kx_SEEDBYTES]);
-
-SODIUM_EXPORT
-int crypto_kx_keypair(unsigned char pk[crypto_kx_PUBLICKEYBYTES],
-                      unsigned char sk[crypto_kx_SECRETKEYBYTES]);
-
-SODIUM_EXPORT
-int crypto_kx_client_session_keys(unsigned char rx[crypto_kx_SESSIONKEYBYTES],
-                                  unsigned char tx[crypto_kx_SESSIONKEYBYTES],
-                                  const unsigned char client_pk[crypto_kx_PUBLICKEYBYTES],
-                                  const unsigned char client_sk[crypto_kx_SECRETKEYBYTES],
-                                  const unsigned char server_pk[crypto_kx_PUBLICKEYBYTES])
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_kx_server_session_keys(unsigned char rx[crypto_kx_SESSIONKEYBYTES],
-                                  unsigned char tx[crypto_kx_SESSIONKEYBYTES],
-                                  const unsigned char server_pk[crypto_kx_PUBLICKEYBYTES],
-                                  const unsigned char server_sk[crypto_kx_SECRETKEYBYTES],
-                                  const unsigned char client_pk[crypto_kx_PUBLICKEYBYTES])
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_onetimeauth.h b/tools/sdk/include/libsodium/sodium/crypto_onetimeauth.h
deleted file mode 100644
index 5951c5b82d3..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_onetimeauth.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef crypto_onetimeauth_H
-#define crypto_onetimeauth_H
-
-#include <stddef.h>
-
-#include "crypto_onetimeauth_poly1305.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-typedef crypto_onetimeauth_poly1305_state crypto_onetimeauth_state;
-
-SODIUM_EXPORT
-size_t  crypto_onetimeauth_statebytes(void);
-
-#define crypto_onetimeauth_BYTES crypto_onetimeauth_poly1305_BYTES
-SODIUM_EXPORT
-size_t  crypto_onetimeauth_bytes(void);
-
-#define crypto_onetimeauth_KEYBYTES crypto_onetimeauth_poly1305_KEYBYTES
-SODIUM_EXPORT
-size_t  crypto_onetimeauth_keybytes(void);
-
-#define crypto_onetimeauth_PRIMITIVE "poly1305"
-SODIUM_EXPORT
-const char *crypto_onetimeauth_primitive(void);
-
-SODIUM_EXPORT
-int crypto_onetimeauth(unsigned char *out, const unsigned char *in,
-                       unsigned long long inlen, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_onetimeauth_verify(const unsigned char *h, const unsigned char *in,
-                              unsigned long long inlen, const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_onetimeauth_init(crypto_onetimeauth_state *state,
-                            const unsigned char *key);
-
-SODIUM_EXPORT
-int crypto_onetimeauth_update(crypto_onetimeauth_state *state,
-                              const unsigned char *in,
-                              unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_onetimeauth_final(crypto_onetimeauth_state *state,
-                             unsigned char *out);
-
-SODIUM_EXPORT
-void crypto_onetimeauth_keygen(unsigned char k[crypto_onetimeauth_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_onetimeauth_poly1305.h b/tools/sdk/include/libsodium/sodium/crypto_onetimeauth_poly1305.h
deleted file mode 100644
index 479e923dccb..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_onetimeauth_poly1305.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#ifndef crypto_onetimeauth_poly1305_H
-#define crypto_onetimeauth_poly1305_H
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <sys/types.h>
-
-#include "export.h"
-
-typedef CRYPTO_ALIGN(16) struct crypto_onetimeauth_poly1305_state {
-    unsigned char opaque[256];
-} crypto_onetimeauth_poly1305_state;
-
-SODIUM_EXPORT
-size_t crypto_onetimeauth_poly1305_statebytes(void);
-
-#define crypto_onetimeauth_poly1305_BYTES 16U
-SODIUM_EXPORT
-size_t crypto_onetimeauth_poly1305_bytes(void);
-
-#define crypto_onetimeauth_poly1305_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_onetimeauth_poly1305_keybytes(void);
-
-SODIUM_EXPORT
-int crypto_onetimeauth_poly1305(unsigned char *out,
-                                const unsigned char *in,
-                                unsigned long long inlen,
-                                const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_onetimeauth_poly1305_verify(const unsigned char *h,
-                                       const unsigned char *in,
-                                       unsigned long long inlen,
-                                       const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_onetimeauth_poly1305_init(crypto_onetimeauth_poly1305_state *state,
-                                     const unsigned char *key);
-
-SODIUM_EXPORT
-int crypto_onetimeauth_poly1305_update(crypto_onetimeauth_poly1305_state *state,
-                                       const unsigned char *in,
-                                       unsigned long long inlen);
-
-SODIUM_EXPORT
-int crypto_onetimeauth_poly1305_final(crypto_onetimeauth_poly1305_state *state,
-                                      unsigned char *out);
-
-SODIUM_EXPORT
-void crypto_onetimeauth_poly1305_keygen(unsigned char k[crypto_onetimeauth_poly1305_KEYBYTES]);
-
-/* ------------------------------------------------------------------------- */
-
-int _crypto_onetimeauth_poly1305_pick_best_implementation(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_pwhash.h b/tools/sdk/include/libsodium/sodium/crypto_pwhash.h
deleted file mode 100644
index 56eca0680c1..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_pwhash.h
+++ /dev/null
@@ -1,121 +0,0 @@
-#ifndef crypto_pwhash_H
-#define crypto_pwhash_H
-
-#include <stddef.h>
-
-#include "crypto_pwhash_argon2i.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_pwhash_ALG_ARGON2I13 crypto_pwhash_argon2i_ALG_ARGON2I13
-SODIUM_EXPORT
-int crypto_pwhash_alg_argon2i13(void);
-
-#define crypto_pwhash_ALG_DEFAULT crypto_pwhash_ALG_ARGON2I13
-SODIUM_EXPORT
-int crypto_pwhash_alg_default(void);
-
-#define crypto_pwhash_BYTES_MIN crypto_pwhash_argon2i_BYTES_MIN
-SODIUM_EXPORT
-size_t crypto_pwhash_bytes_min(void);
-
-#define crypto_pwhash_BYTES_MAX crypto_pwhash_argon2i_BYTES_MAX
-SODIUM_EXPORT
-size_t crypto_pwhash_bytes_max(void);
-
-#define crypto_pwhash_PASSWD_MIN crypto_pwhash_argon2i_PASSWD_MIN
-SODIUM_EXPORT
-size_t crypto_pwhash_passwd_min(void);
-
-#define crypto_pwhash_PASSWD_MAX crypto_pwhash_argon2i_PASSWD_MAX
-SODIUM_EXPORT
-size_t crypto_pwhash_passwd_max(void);
-
-#define crypto_pwhash_SALTBYTES crypto_pwhash_argon2i_SALTBYTES
-SODIUM_EXPORT
-size_t crypto_pwhash_saltbytes(void);
-
-#define crypto_pwhash_STRBYTES crypto_pwhash_argon2i_STRBYTES
-SODIUM_EXPORT
-size_t crypto_pwhash_strbytes(void);
-
-#define crypto_pwhash_STRPREFIX crypto_pwhash_argon2i_STRPREFIX
-SODIUM_EXPORT
-const char *crypto_pwhash_strprefix(void);
-
-#define crypto_pwhash_OPSLIMIT_MIN crypto_pwhash_argon2i_OPSLIMIT_MIN
-SODIUM_EXPORT
-size_t crypto_pwhash_opslimit_min(void);
-
-#define crypto_pwhash_OPSLIMIT_MAX crypto_pwhash_argon2i_OPSLIMIT_MAX
-SODIUM_EXPORT
-size_t crypto_pwhash_opslimit_max(void);
-
-#define crypto_pwhash_MEMLIMIT_MIN crypto_pwhash_argon2i_MEMLIMIT_MIN
-SODIUM_EXPORT
-size_t crypto_pwhash_memlimit_min(void);
-
-#define crypto_pwhash_MEMLIMIT_MAX crypto_pwhash_argon2i_MEMLIMIT_MAX
-SODIUM_EXPORT
-size_t crypto_pwhash_memlimit_max(void);
-
-#define crypto_pwhash_OPSLIMIT_INTERACTIVE crypto_pwhash_argon2i_OPSLIMIT_INTERACTIVE
-SODIUM_EXPORT
-size_t crypto_pwhash_opslimit_interactive(void);
-
-#define crypto_pwhash_MEMLIMIT_INTERACTIVE crypto_pwhash_argon2i_MEMLIMIT_INTERACTIVE
-SODIUM_EXPORT
-size_t crypto_pwhash_memlimit_interactive(void);
-
-#define crypto_pwhash_OPSLIMIT_MODERATE crypto_pwhash_argon2i_OPSLIMIT_MODERATE
-SODIUM_EXPORT
-size_t crypto_pwhash_opslimit_moderate(void);
-
-#define crypto_pwhash_MEMLIMIT_MODERATE crypto_pwhash_argon2i_MEMLIMIT_MODERATE
-SODIUM_EXPORT
-size_t crypto_pwhash_memlimit_moderate(void);
-
-#define crypto_pwhash_OPSLIMIT_SENSITIVE crypto_pwhash_argon2i_OPSLIMIT_SENSITIVE
-SODIUM_EXPORT
-size_t crypto_pwhash_opslimit_sensitive(void);
-
-#define crypto_pwhash_MEMLIMIT_SENSITIVE crypto_pwhash_argon2i_MEMLIMIT_SENSITIVE
-SODIUM_EXPORT
-size_t crypto_pwhash_memlimit_sensitive(void);
-
-SODIUM_EXPORT
-int crypto_pwhash(unsigned char * const out, unsigned long long outlen,
-                  const char * const passwd, unsigned long long passwdlen,
-                  const unsigned char * const salt,
-                  unsigned long long opslimit, size_t memlimit, int alg)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_pwhash_str(char out[crypto_pwhash_STRBYTES],
-                      const char * const passwd, unsigned long long passwdlen,
-                      unsigned long long opslimit, size_t memlimit)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_pwhash_str_verify(const char str[crypto_pwhash_STRBYTES],
-                             const char * const passwd,
-                             unsigned long long passwdlen)
-            __attribute__ ((warn_unused_result));
-
-#define crypto_pwhash_PRIMITIVE "argon2i"
-SODIUM_EXPORT
-const char *crypto_pwhash_primitive(void)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/tools/sdk/include/libsodium/sodium/crypto_pwhash_argon2i.h b/tools/sdk/include/libsodium/sodium/crypto_pwhash_argon2i.h
deleted file mode 100644
index d414b939d1f..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_pwhash_argon2i.h
+++ /dev/null
@@ -1,120 +0,0 @@
-#ifndef crypto_pwhash_argon2i_H
-#define crypto_pwhash_argon2i_H
-
-#include <limits.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_pwhash_argon2i_ALG_ARGON2I13 1
-SODIUM_EXPORT
-int crypto_pwhash_argon2i_alg_argon2i13(void);
-
-#define crypto_pwhash_argon2i_BYTES_MIN 16U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_bytes_min(void);
-
-#define crypto_pwhash_argon2i_BYTES_MAX 4294967295U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_bytes_max(void);
-
-#define crypto_pwhash_argon2i_PASSWD_MIN 0U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_passwd_min(void);
-
-#define crypto_pwhash_argon2i_PASSWD_MAX 4294967295U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_passwd_max(void);
-
-#define crypto_pwhash_argon2i_SALTBYTES 16U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_saltbytes(void);
-
-#define crypto_pwhash_argon2i_STRBYTES 128U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_strbytes(void);
-
-#define crypto_pwhash_argon2i_STRPREFIX "$argon2i$"
-SODIUM_EXPORT
-const char *crypto_pwhash_argon2i_strprefix(void);
-
-#define crypto_pwhash_argon2i_OPSLIMIT_MIN 3U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_opslimit_min(void);
-
-#define crypto_pwhash_argon2i_OPSLIMIT_MAX 4294967295U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_opslimit_max(void);
-
-#define crypto_pwhash_argon2i_MEMLIMIT_MIN 1U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_memlimit_min(void);
-
-#define crypto_pwhash_argon2i_MEMLIMIT_MAX ((SIZE_MAX >= 1ULL << 48) ? 4398046510080U : (SIZE_MAX >= 1ULL << 32) ? 2147483648U : 32768U)
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_memlimit_max(void);
-
-#define crypto_pwhash_argon2i_OPSLIMIT_INTERACTIVE 4U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_opslimit_interactive(void);
-
-#define crypto_pwhash_argon2i_MEMLIMIT_INTERACTIVE 33554432U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_memlimit_interactive(void);
-
-#define crypto_pwhash_argon2i_OPSLIMIT_MODERATE 6U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_opslimit_moderate(void);
-
-#define crypto_pwhash_argon2i_MEMLIMIT_MODERATE 134217728U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_memlimit_moderate(void);
-
-#define crypto_pwhash_argon2i_OPSLIMIT_SENSITIVE 8U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_opslimit_sensitive(void);
-
-#define crypto_pwhash_argon2i_MEMLIMIT_SENSITIVE 536870912U
-SODIUM_EXPORT
-size_t crypto_pwhash_argon2i_memlimit_sensitive(void);
-
-SODIUM_EXPORT
-int crypto_pwhash_argon2i(unsigned char * const out,
-                          unsigned long long outlen,
-                          const char * const passwd,
-                          unsigned long long passwdlen,
-                          const unsigned char * const salt,
-                          unsigned long long opslimit, size_t memlimit,
-                          int alg)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_pwhash_argon2i_str(char out[crypto_pwhash_argon2i_STRBYTES],
-                              const char * const passwd,
-                              unsigned long long passwdlen,
-                              unsigned long long opslimit, size_t memlimit)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_pwhash_argon2i_str_verify(const char str[crypto_pwhash_argon2i_STRBYTES],
-                                     const char * const passwd,
-                                     unsigned long long passwdlen)
-            __attribute__ ((warn_unused_result));
-
-/* ------------------------------------------------------------------------- */
-
-int _crypto_pwhash_argon2i_pick_best_implementation(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_pwhash_scryptsalsa208sha256.h b/tools/sdk/include/libsodium/sodium/crypto_pwhash_scryptsalsa208sha256.h
deleted file mode 100644
index 9f693e540e7..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_pwhash_scryptsalsa208sha256.h
+++ /dev/null
@@ -1,112 +0,0 @@
-#ifndef crypto_pwhash_scryptsalsa208sha256_H
-#define crypto_pwhash_scryptsalsa208sha256_H
-
-#include <limits.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_pwhash_scryptsalsa208sha256_BYTES_MIN 16U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_bytes_min(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_BYTES_MAX SIZE_MAX
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_bytes_max(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_PASSWD_MIN 0U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_passwd_min(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_PASSWD_MAX SIZE_MAX
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_passwd_max(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_SALTBYTES 32U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_saltbytes(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_STRBYTES 102U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_strbytes(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_STRPREFIX "$7$"
-SODIUM_EXPORT
-const char *crypto_pwhash_scryptsalsa208sha256_strprefix(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_OPSLIMIT_MIN 32768U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_opslimit_min(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_OPSLIMIT_MAX 4294967295U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_opslimit_max(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_MEMLIMIT_MIN 16777216U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_memlimit_min(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_MEMLIMIT_MAX ((SIZE_MAX >= 68719476736U) ? 68719476736U : SIZE_MAX)
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_memlimit_max(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_OPSLIMIT_INTERACTIVE 524288U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_opslimit_interactive(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_MEMLIMIT_INTERACTIVE 16777216U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_memlimit_interactive(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_OPSLIMIT_SENSITIVE 33554432U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_opslimit_sensitive(void);
-
-#define crypto_pwhash_scryptsalsa208sha256_MEMLIMIT_SENSITIVE 1073741824U
-SODIUM_EXPORT
-size_t crypto_pwhash_scryptsalsa208sha256_memlimit_sensitive(void);
-
-SODIUM_EXPORT
-int crypto_pwhash_scryptsalsa208sha256(unsigned char * const out,
-                                       unsigned long long outlen,
-                                       const char * const passwd,
-                                       unsigned long long passwdlen,
-                                       const unsigned char * const salt,
-                                       unsigned long long opslimit,
-                                       size_t memlimit)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_pwhash_scryptsalsa208sha256_str(char out[crypto_pwhash_scryptsalsa208sha256_STRBYTES],
-                                           const char * const passwd,
-                                           unsigned long long passwdlen,
-                                           unsigned long long opslimit,
-                                           size_t memlimit)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_pwhash_scryptsalsa208sha256_str_verify(const char str[crypto_pwhash_scryptsalsa208sha256_STRBYTES],
-                                                  const char * const passwd,
-                                                  unsigned long long passwdlen)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_pwhash_scryptsalsa208sha256_ll(const uint8_t * passwd, size_t passwdlen,
-                                          const uint8_t * salt, size_t saltlen,
-                                          uint64_t N, uint32_t r, uint32_t p,
-                                          uint8_t * buf, size_t buflen)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_scalarmult.h b/tools/sdk/include/libsodium/sodium/crypto_scalarmult.h
deleted file mode 100644
index 830c10f6473..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_scalarmult.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef crypto_scalarmult_H
-#define crypto_scalarmult_H
-
-#include <stddef.h>
-
-#include "crypto_scalarmult_curve25519.h"
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_scalarmult_BYTES crypto_scalarmult_curve25519_BYTES
-SODIUM_EXPORT
-size_t  crypto_scalarmult_bytes(void);
-
-#define crypto_scalarmult_SCALARBYTES crypto_scalarmult_curve25519_SCALARBYTES
-SODIUM_EXPORT
-size_t  crypto_scalarmult_scalarbytes(void);
-
-#define crypto_scalarmult_PRIMITIVE "curve25519"
-SODIUM_EXPORT
-const char *crypto_scalarmult_primitive(void);
-
-SODIUM_EXPORT
-int crypto_scalarmult_base(unsigned char *q, const unsigned char *n);
-
-SODIUM_EXPORT
-int crypto_scalarmult(unsigned char *q, const unsigned char *n,
-                      const unsigned char *p)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_scalarmult_curve25519.h b/tools/sdk/include/libsodium/sodium/crypto_scalarmult_curve25519.h
deleted file mode 100644
index 953f8923c5e..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_scalarmult_curve25519.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef crypto_scalarmult_curve25519_H
-#define crypto_scalarmult_curve25519_H
-
-#include <stddef.h>
-
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_scalarmult_curve25519_BYTES 32U
-SODIUM_EXPORT
-size_t crypto_scalarmult_curve25519_bytes(void);
-
-#define crypto_scalarmult_curve25519_SCALARBYTES 32U
-SODIUM_EXPORT
-size_t crypto_scalarmult_curve25519_scalarbytes(void);
-
-SODIUM_EXPORT
-int crypto_scalarmult_curve25519(unsigned char *q, const unsigned char *n,
-                                 const unsigned char *p)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_scalarmult_curve25519_base(unsigned char *q, const unsigned char *n);
-
-/* ------------------------------------------------------------------------- */
-
-int _crypto_scalarmult_curve25519_pick_best_implementation(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_secretbox.h b/tools/sdk/include/libsodium/sodium/crypto_secretbox.h
deleted file mode 100644
index 9b098200e0b..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_secretbox.h
+++ /dev/null
@@ -1,87 +0,0 @@
-#ifndef crypto_secretbox_H
-#define crypto_secretbox_H
-
-#include <stddef.h>
-
-#include "crypto_secretbox_xsalsa20poly1305.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_secretbox_KEYBYTES crypto_secretbox_xsalsa20poly1305_KEYBYTES
-SODIUM_EXPORT
-size_t  crypto_secretbox_keybytes(void);
-
-#define crypto_secretbox_NONCEBYTES crypto_secretbox_xsalsa20poly1305_NONCEBYTES
-SODIUM_EXPORT
-size_t  crypto_secretbox_noncebytes(void);
-
-#define crypto_secretbox_MACBYTES crypto_secretbox_xsalsa20poly1305_MACBYTES
-SODIUM_EXPORT
-size_t  crypto_secretbox_macbytes(void);
-
-#define crypto_secretbox_PRIMITIVE "xsalsa20poly1305"
-SODIUM_EXPORT
-const char *crypto_secretbox_primitive(void);
-
-SODIUM_EXPORT
-int crypto_secretbox_easy(unsigned char *c, const unsigned char *m,
-                          unsigned long long mlen, const unsigned char *n,
-                          const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_secretbox_open_easy(unsigned char *m, const unsigned char *c,
-                               unsigned long long clen, const unsigned char *n,
-                               const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_secretbox_detached(unsigned char *c, unsigned char *mac,
-                              const unsigned char *m,
-                              unsigned long long mlen,
-                              const unsigned char *n,
-                              const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_secretbox_open_detached(unsigned char *m,
-                                   const unsigned char *c,
-                                   const unsigned char *mac,
-                                   unsigned long long clen,
-                                   const unsigned char *n,
-                                   const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-void crypto_secretbox_keygen(unsigned char k[crypto_secretbox_KEYBYTES]);
-
-/* -- NaCl compatibility interface ; Requires padding -- */
-
-#define crypto_secretbox_ZEROBYTES crypto_secretbox_xsalsa20poly1305_ZEROBYTES
-SODIUM_EXPORT
-size_t  crypto_secretbox_zerobytes(void);
-
-#define crypto_secretbox_BOXZEROBYTES crypto_secretbox_xsalsa20poly1305_BOXZEROBYTES
-SODIUM_EXPORT
-size_t  crypto_secretbox_boxzerobytes(void);
-
-SODIUM_EXPORT
-int crypto_secretbox(unsigned char *c, const unsigned char *m,
-                     unsigned long long mlen, const unsigned char *n,
-                     const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_secretbox_open(unsigned char *m, const unsigned char *c,
-                          unsigned long long clen, const unsigned char *n,
-                          const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_secretbox_xchacha20poly1305.h b/tools/sdk/include/libsodium/sodium/crypto_secretbox_xchacha20poly1305.h
deleted file mode 100644
index 7a61a09174e..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_secretbox_xchacha20poly1305.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef crypto_secretbox_xchacha20poly1305_H
-#define crypto_secretbox_xchacha20poly1305_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_secretbox_xchacha20poly1305_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_secretbox_xchacha20poly1305_keybytes(void);
-
-#define crypto_secretbox_xchacha20poly1305_NONCEBYTES 24U
-SODIUM_EXPORT
-size_t crypto_secretbox_xchacha20poly1305_noncebytes(void);
-
-#define crypto_secretbox_xchacha20poly1305_MACBYTES 16U
-SODIUM_EXPORT
-size_t crypto_secretbox_xchacha20poly1305_macbytes(void);
-
-SODIUM_EXPORT
-int crypto_secretbox_xchacha20poly1305_easy(unsigned char *c,
-                                            const unsigned char *m,
-                                            unsigned long long mlen,
-                                            const unsigned char *n,
-                                            const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_secretbox_xchacha20poly1305_open_easy(unsigned char *m,
-                                                 const unsigned char *c,
-                                                 unsigned long long clen,
-                                                 const unsigned char *n,
-                                                 const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_secretbox_xchacha20poly1305_detached(unsigned char *c,
-                                                unsigned char *mac,
-                                                const unsigned char *m,
-                                                unsigned long long mlen,
-                                                const unsigned char *n,
-                                                const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_secretbox_xchacha20poly1305_open_detached(unsigned char *m,
-                                                     const unsigned char *c,
-                                                     const unsigned char *mac,
-                                                     unsigned long long clen,
-                                                     const unsigned char *n,
-                                                     const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_secretbox_xsalsa20poly1305.h b/tools/sdk/include/libsodium/sodium/crypto_secretbox_xsalsa20poly1305.h
deleted file mode 100644
index 5aa30805d6c..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_secretbox_xsalsa20poly1305.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef crypto_secretbox_xsalsa20poly1305_H
-#define crypto_secretbox_xsalsa20poly1305_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_secretbox_xsalsa20poly1305_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_secretbox_xsalsa20poly1305_keybytes(void);
-
-#define crypto_secretbox_xsalsa20poly1305_NONCEBYTES 24U
-SODIUM_EXPORT
-size_t crypto_secretbox_xsalsa20poly1305_noncebytes(void);
-
-#define crypto_secretbox_xsalsa20poly1305_MACBYTES 16U
-SODIUM_EXPORT
-size_t crypto_secretbox_xsalsa20poly1305_macbytes(void);
-
-#define crypto_secretbox_xsalsa20poly1305_BOXZEROBYTES 16U
-SODIUM_EXPORT
-size_t crypto_secretbox_xsalsa20poly1305_boxzerobytes(void);
-
-#define crypto_secretbox_xsalsa20poly1305_ZEROBYTES \
-    (crypto_secretbox_xsalsa20poly1305_BOXZEROBYTES + \
-     crypto_secretbox_xsalsa20poly1305_MACBYTES)
-SODIUM_EXPORT
-size_t crypto_secretbox_xsalsa20poly1305_zerobytes(void);
-
-SODIUM_EXPORT
-int crypto_secretbox_xsalsa20poly1305(unsigned char *c,
-                                      const unsigned char *m,
-                                      unsigned long long mlen,
-                                      const unsigned char *n,
-                                      const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_secretbox_xsalsa20poly1305_open(unsigned char *m,
-                                           const unsigned char *c,
-                                           unsigned long long clen,
-                                           const unsigned char *n,
-                                           const unsigned char *k)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-void crypto_secretbox_xsalsa20poly1305_keygen(unsigned char k[crypto_secretbox_xsalsa20poly1305_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_shorthash.h b/tools/sdk/include/libsodium/sodium/crypto_shorthash.h
deleted file mode 100644
index a4988082471..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_shorthash.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef crypto_shorthash_H
-#define crypto_shorthash_H
-
-#include <stddef.h>
-
-#include "crypto_shorthash_siphash24.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_shorthash_BYTES crypto_shorthash_siphash24_BYTES
-SODIUM_EXPORT
-size_t  crypto_shorthash_bytes(void);
-
-#define crypto_shorthash_KEYBYTES crypto_shorthash_siphash24_KEYBYTES
-SODIUM_EXPORT
-size_t  crypto_shorthash_keybytes(void);
-
-#define crypto_shorthash_PRIMITIVE "siphash24"
-SODIUM_EXPORT
-const char *crypto_shorthash_primitive(void);
-
-SODIUM_EXPORT
-int crypto_shorthash(unsigned char *out, const unsigned char *in,
-                     unsigned long long inlen, const unsigned char *k);
-
-SODIUM_EXPORT
-void crypto_shorthash_keygen(unsigned char k[crypto_shorthash_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_shorthash_siphash24.h b/tools/sdk/include/libsodium/sodium/crypto_shorthash_siphash24.h
deleted file mode 100644
index 745ed48fae9..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_shorthash_siphash24.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef crypto_shorthash_siphash24_H
-#define crypto_shorthash_siphash24_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-/* -- 64-bit output -- */
-
-#define crypto_shorthash_siphash24_BYTES 8U
-SODIUM_EXPORT
-size_t crypto_shorthash_siphash24_bytes(void);
-
-#define crypto_shorthash_siphash24_KEYBYTES 16U
-SODIUM_EXPORT
-size_t crypto_shorthash_siphash24_keybytes(void);
-
-SODIUM_EXPORT
-int crypto_shorthash_siphash24(unsigned char *out, const unsigned char *in,
-                               unsigned long long inlen, const unsigned char *k);
-
-#ifndef SODIUM_LIBRARY_MINIMAL
-/* -- 128-bit output -- */
-
-#define crypto_shorthash_siphashx24_BYTES 16U
-SODIUM_EXPORT
-size_t crypto_shorthash_siphashx24_bytes(void);
-
-#define crypto_shorthash_siphashx24_KEYBYTES 16U
-SODIUM_EXPORT
-size_t crypto_shorthash_siphashx24_keybytes(void);
-
-SODIUM_EXPORT
-int crypto_shorthash_siphashx24(unsigned char *out, const unsigned char *in,
-                                unsigned long long inlen, const unsigned char *k);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_sign.h b/tools/sdk/include/libsodium/sodium/crypto_sign.h
deleted file mode 100644
index b0335bf274c..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_sign.h
+++ /dev/null
@@ -1,99 +0,0 @@
-#ifndef crypto_sign_H
-#define crypto_sign_H
-
-/*
- * THREAD SAFETY: crypto_sign_keypair() is thread-safe,
- * provided that sodium_init() was called before.
- *
- * Other functions, including crypto_sign_seed_keypair() are always thread-safe.
- */
-
-#include <stddef.h>
-
-#include "crypto_sign_ed25519.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-typedef crypto_sign_ed25519ph_state crypto_sign_state;
-
-SODIUM_EXPORT
-size_t  crypto_sign_statebytes(void);
-
-#define crypto_sign_BYTES crypto_sign_ed25519_BYTES
-SODIUM_EXPORT
-size_t  crypto_sign_bytes(void);
-
-#define crypto_sign_SEEDBYTES crypto_sign_ed25519_SEEDBYTES
-SODIUM_EXPORT
-size_t  crypto_sign_seedbytes(void);
-
-#define crypto_sign_PUBLICKEYBYTES crypto_sign_ed25519_PUBLICKEYBYTES
-SODIUM_EXPORT
-size_t  crypto_sign_publickeybytes(void);
-
-#define crypto_sign_SECRETKEYBYTES crypto_sign_ed25519_SECRETKEYBYTES
-SODIUM_EXPORT
-size_t  crypto_sign_secretkeybytes(void);
-
-#define crypto_sign_PRIMITIVE "ed25519"
-SODIUM_EXPORT
-const char *crypto_sign_primitive(void);
-
-SODIUM_EXPORT
-int crypto_sign_seed_keypair(unsigned char *pk, unsigned char *sk,
-                             const unsigned char *seed);
-
-SODIUM_EXPORT
-int crypto_sign_keypair(unsigned char *pk, unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign(unsigned char *sm, unsigned long long *smlen_p,
-                const unsigned char *m, unsigned long long mlen,
-                const unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign_open(unsigned char *m, unsigned long long *mlen_p,
-                     const unsigned char *sm, unsigned long long smlen,
-                     const unsigned char *pk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_sign_detached(unsigned char *sig, unsigned long long *siglen_p,
-                         const unsigned char *m, unsigned long long mlen,
-                         const unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign_verify_detached(const unsigned char *sig,
-                                const unsigned char *m,
-                                unsigned long long mlen,
-                                const unsigned char *pk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_sign_init(crypto_sign_state *state);
-
-SODIUM_EXPORT
-int crypto_sign_update(crypto_sign_state *state,
-                       const unsigned char *m, unsigned long long mlen);
-
-SODIUM_EXPORT
-int crypto_sign_final_create(crypto_sign_state *state, unsigned char *sig,
-                             unsigned long long *siglen_p,
-                             const unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign_final_verify(crypto_sign_state *state, unsigned char *sig,
-                             const unsigned char *pk)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_sign_ed25519.h b/tools/sdk/include/libsodium/sodium/crypto_sign_ed25519.h
deleted file mode 100644
index 17c150f284a..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_sign_ed25519.h
+++ /dev/null
@@ -1,110 +0,0 @@
-#ifndef crypto_sign_ed25519_H
-#define crypto_sign_ed25519_H
-
-#include <stddef.h>
-#include "crypto_hash_sha512.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-typedef struct crypto_sign_ed25519ph_state {
-    crypto_hash_sha512_state hs;
-} crypto_sign_ed25519ph_state;
-
-SODIUM_EXPORT
-size_t crypto_sign_ed25519ph_statebytes(void);
-
-#define crypto_sign_ed25519_BYTES 64U
-SODIUM_EXPORT
-size_t crypto_sign_ed25519_bytes(void);
-
-#define crypto_sign_ed25519_SEEDBYTES 32U
-SODIUM_EXPORT
-size_t crypto_sign_ed25519_seedbytes(void);
-
-#define crypto_sign_ed25519_PUBLICKEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_sign_ed25519_publickeybytes(void);
-
-#define crypto_sign_ed25519_SECRETKEYBYTES (32U + 32U)
-SODIUM_EXPORT
-size_t crypto_sign_ed25519_secretkeybytes(void);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519(unsigned char *sm, unsigned long long *smlen_p,
-                        const unsigned char *m, unsigned long long mlen,
-                        const unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519_open(unsigned char *m, unsigned long long *mlen_p,
-                             const unsigned char *sm, unsigned long long smlen,
-                             const unsigned char *pk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_sign_ed25519_detached(unsigned char *sig,
-                                 unsigned long long *siglen_p,
-                                 const unsigned char *m,
-                                 unsigned long long mlen,
-                                 const unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519_verify_detached(const unsigned char *sig,
-                                        const unsigned char *m,
-                                        unsigned long long mlen,
-                                        const unsigned char *pk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_sign_ed25519_keypair(unsigned char *pk, unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519_seed_keypair(unsigned char *pk, unsigned char *sk,
-                                     const unsigned char *seed);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519_pk_to_curve25519(unsigned char *curve25519_pk,
-                                         const unsigned char *ed25519_pk)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int crypto_sign_ed25519_sk_to_curve25519(unsigned char *curve25519_sk,
-                                         const unsigned char *ed25519_sk);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519_sk_to_seed(unsigned char *seed,
-                                   const unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519_sk_to_pk(unsigned char *pk, const unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519ph_init(crypto_sign_ed25519ph_state *state);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519ph_update(crypto_sign_ed25519ph_state *state,
-                                 const unsigned char *m,
-                                 unsigned long long mlen);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519ph_final_create(crypto_sign_ed25519ph_state *state,
-                                       unsigned char *sig,
-                                       unsigned long long *siglen_p,
-                                       const unsigned char *sk);
-
-SODIUM_EXPORT
-int crypto_sign_ed25519ph_final_verify(crypto_sign_ed25519ph_state *state,
-                                       unsigned char *sig,
-                                       const unsigned char *pk)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_sign_edwards25519sha512batch.h b/tools/sdk/include/libsodium/sodium/crypto_sign_edwards25519sha512batch.h
deleted file mode 100644
index 2224a94e013..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_sign_edwards25519sha512batch.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#ifndef crypto_sign_edwards25519sha512batch_H
-#define crypto_sign_edwards25519sha512batch_H
-
-/*
- * WARNING: This construction was a prototype, which should not be used
- * any more in new projects.
- *
- * crypto_sign_edwards25519sha512batch is provided for applications
- * initially built with NaCl, but as recommended by the author of this
- * construction, new applications should use ed25519 instead.
- *
- * In Sodium, you should use the high-level crypto_sign_*() functions instead.
- */
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_sign_edwards25519sha512batch_BYTES 64U
-#define crypto_sign_edwards25519sha512batch_PUBLICKEYBYTES 32U
-#define crypto_sign_edwards25519sha512batch_SECRETKEYBYTES (32U + 32U)
-
-SODIUM_EXPORT
-int crypto_sign_edwards25519sha512batch(unsigned char *sm,
-                                        unsigned long long *smlen_p,
-                                        const unsigned char *m,
-                                        unsigned long long mlen,
-                                        const unsigned char *sk)
-       __attribute__ ((deprecated));
-
-SODIUM_EXPORT
-int crypto_sign_edwards25519sha512batch_open(unsigned char *m,
-                                             unsigned long long *mlen_p,
-                                             const unsigned char *sm,
-                                             unsigned long long smlen,
-                                             const unsigned char *pk)
-       __attribute__ ((deprecated));
-
-SODIUM_EXPORT
-int crypto_sign_edwards25519sha512batch_keypair(unsigned char *pk,
-                                                unsigned char *sk)
-       __attribute__ ((deprecated));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_stream.h b/tools/sdk/include/libsodium/sodium/crypto_stream.h
deleted file mode 100644
index 22de6ff52d3..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_stream.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef crypto_stream_H
-#define crypto_stream_H
-
-/*
- *  WARNING: This is just a stream cipher. It is NOT authenticated encryption.
- *  While it provides some protection against eavesdropping, it does NOT
- *  provide any security against active attacks.
- *  Unless you know what you're doing, what you are looking for is probably
- *  the crypto_box functions.
- */
-
-#include <stddef.h>
-
-#include "crypto_stream_xsalsa20.h"
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_stream_KEYBYTES crypto_stream_xsalsa20_KEYBYTES
-SODIUM_EXPORT
-size_t  crypto_stream_keybytes(void);
-
-#define crypto_stream_NONCEBYTES crypto_stream_xsalsa20_NONCEBYTES
-SODIUM_EXPORT
-size_t  crypto_stream_noncebytes(void);
-
-#define crypto_stream_PRIMITIVE "xsalsa20"
-SODIUM_EXPORT
-const char *crypto_stream_primitive(void);
-
-SODIUM_EXPORT
-int crypto_stream(unsigned char *c, unsigned long long clen,
-                  const unsigned char *n, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_xor(unsigned char *c, const unsigned char *m,
-                      unsigned long long mlen, const unsigned char *n,
-                      const unsigned char *k);
-
-SODIUM_EXPORT
-void crypto_stream_keygen(unsigned char k[crypto_stream_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_stream_aes128ctr.h b/tools/sdk/include/libsodium/sodium/crypto_stream_aes128ctr.h
deleted file mode 100644
index 33ee1b89714..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_stream_aes128ctr.h
+++ /dev/null
@@ -1,65 +0,0 @@
-#ifndef crypto_stream_aes128ctr_H
-#define crypto_stream_aes128ctr_H
-
-/*
- *  WARNING: This is just a stream cipher. It is NOT authenticated encryption.
- *  While it provides some protection against eavesdropping, it does NOT
- *  provide any security against active attacks.
- *  Unless you know what you're doing, what you are looking for is probably
- *  the crypto_box functions.
- */
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_stream_aes128ctr_KEYBYTES 16U
-SODIUM_EXPORT
-size_t crypto_stream_aes128ctr_keybytes(void);
-
-#define crypto_stream_aes128ctr_NONCEBYTES 16U
-SODIUM_EXPORT
-size_t crypto_stream_aes128ctr_noncebytes(void);
-
-#define crypto_stream_aes128ctr_BEFORENMBYTES 1408U
-SODIUM_EXPORT
-size_t crypto_stream_aes128ctr_beforenmbytes(void);
-
-SODIUM_EXPORT
-int crypto_stream_aes128ctr(unsigned char *out, unsigned long long outlen,
-                            const unsigned char *n, const unsigned char *k)
-            __attribute__ ((deprecated));
-
-SODIUM_EXPORT
-int crypto_stream_aes128ctr_xor(unsigned char *out, const unsigned char *in,
-                                unsigned long long inlen, const unsigned char *n,
-                                const unsigned char *k)
-            __attribute__ ((deprecated));
-
-SODIUM_EXPORT
-int crypto_stream_aes128ctr_beforenm(unsigned char *c, const unsigned char *k)
-            __attribute__ ((deprecated));
-
-SODIUM_EXPORT
-int crypto_stream_aes128ctr_afternm(unsigned char *out, unsigned long long len,
-                                    const unsigned char *nonce, const unsigned char *c)
-            __attribute__ ((deprecated));
-
-SODIUM_EXPORT
-int crypto_stream_aes128ctr_xor_afternm(unsigned char *out, const unsigned char *in,
-                                        unsigned long long len,
-                                        const unsigned char *nonce,
-                                        const unsigned char *c)
-            __attribute__ ((deprecated));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_stream_chacha20.h b/tools/sdk/include/libsodium/sodium/crypto_stream_chacha20.h
deleted file mode 100644
index cf3ffe89595..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_stream_chacha20.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef crypto_stream_chacha20_H
-#define crypto_stream_chacha20_H
-
-/*
- *  WARNING: This is just a stream cipher. It is NOT authenticated encryption.
- *  While it provides some protection against eavesdropping, it does NOT
- *  provide any security against active attacks.
- *  Unless you know what you're doing, what you are looking for is probably
- *  the crypto_box functions.
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_stream_chacha20_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_stream_chacha20_keybytes(void);
-
-#define crypto_stream_chacha20_NONCEBYTES 8U
-SODIUM_EXPORT
-size_t crypto_stream_chacha20_noncebytes(void);
-
-/* ChaCha20 with a 64-bit nonce and a 64-bit counter, as originally designed */
-
-SODIUM_EXPORT
-int crypto_stream_chacha20(unsigned char *c, unsigned long long clen,
-                           const unsigned char *n, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_chacha20_xor(unsigned char *c, const unsigned char *m,
-                               unsigned long long mlen, const unsigned char *n,
-                               const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_chacha20_xor_ic(unsigned char *c, const unsigned char *m,
-                                  unsigned long long mlen,
-                                  const unsigned char *n, uint64_t ic,
-                                  const unsigned char *k);
-
-SODIUM_EXPORT
-void crypto_stream_chacha20_keygen(unsigned char k[crypto_stream_chacha20_KEYBYTES]);
-
-/* ChaCha20 with a 96-bit nonce and a 32-bit counter (IETF) */
-
-#define crypto_stream_chacha20_ietf_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_stream_chacha20_ietf_keybytes(void);
-
-#define crypto_stream_chacha20_ietf_NONCEBYTES 12U
-SODIUM_EXPORT
-size_t crypto_stream_chacha20_ietf_noncebytes(void);
-
-SODIUM_EXPORT
-int crypto_stream_chacha20_ietf(unsigned char *c, unsigned long long clen,
-                                const unsigned char *n, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_chacha20_ietf_xor(unsigned char *c, const unsigned char *m,
-                                    unsigned long long mlen, const unsigned char *n,
-                                    const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_chacha20_ietf_xor_ic(unsigned char *c, const unsigned char *m,
-                                       unsigned long long mlen,
-                                       const unsigned char *n, uint32_t ic,
-                                       const unsigned char *k);
-
-SODIUM_EXPORT
-void crypto_stream_chacha20_ietf_keygen(unsigned char k[crypto_stream_chacha20_ietf_KEYBYTES]);
-
-/* ------------------------------------------------------------------------- */
-
-int _crypto_stream_chacha20_pick_best_implementation(void);
-
-/* Aliases */
-
-#define crypto_stream_chacha20_IETF_KEYBYTES crypto_stream_chacha20_ietf_KEYBYTES
-#define crypto_stream_chacha20_IETF_NONCEBYTES crypto_stream_chacha20_ietf_NONCEBYTES
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_stream_salsa20.h b/tools/sdk/include/libsodium/sodium/crypto_stream_salsa20.h
deleted file mode 100644
index 741140eb22d..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_stream_salsa20.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef crypto_stream_salsa20_H
-#define crypto_stream_salsa20_H
-
-/*
- *  WARNING: This is just a stream cipher. It is NOT authenticated encryption.
- *  While it provides some protection against eavesdropping, it does NOT
- *  provide any security against active attacks.
- *  Unless you know what you're doing, what you are looking for is probably
- *  the crypto_box functions.
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_stream_salsa20_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_stream_salsa20_keybytes(void);
-
-#define crypto_stream_salsa20_NONCEBYTES 8U
-SODIUM_EXPORT
-size_t crypto_stream_salsa20_noncebytes(void);
-
-SODIUM_EXPORT
-int crypto_stream_salsa20(unsigned char *c, unsigned long long clen,
-                          const unsigned char *n, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_salsa20_xor(unsigned char *c, const unsigned char *m,
-                              unsigned long long mlen, const unsigned char *n,
-                              const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_salsa20_xor_ic(unsigned char *c, const unsigned char *m,
-                                 unsigned long long mlen,
-                                 const unsigned char *n, uint64_t ic,
-                                 const unsigned char *k);
-
-SODIUM_EXPORT
-void crypto_stream_salsa20_keygen(unsigned char k[crypto_stream_salsa20_KEYBYTES]);
-
-/* ------------------------------------------------------------------------- */
-
-int _crypto_stream_salsa20_pick_best_implementation(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_stream_salsa2012.h b/tools/sdk/include/libsodium/sodium/crypto_stream_salsa2012.h
deleted file mode 100644
index d5c44282174..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_stream_salsa2012.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef crypto_stream_salsa2012_H
-#define crypto_stream_salsa2012_H
-
-/*
- *  WARNING: This is just a stream cipher. It is NOT authenticated encryption.
- *  While it provides some protection against eavesdropping, it does NOT
- *  provide any security against active attacks.
- *  Unless you know what you're doing, what you are looking for is probably
- *  the crypto_box functions.
- */
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_stream_salsa2012_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_stream_salsa2012_keybytes(void);
-
-#define crypto_stream_salsa2012_NONCEBYTES 8U
-SODIUM_EXPORT
-size_t crypto_stream_salsa2012_noncebytes(void);
-
-SODIUM_EXPORT
-int crypto_stream_salsa2012(unsigned char *c, unsigned long long clen,
-                            const unsigned char *n, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_salsa2012_xor(unsigned char *c, const unsigned char *m,
-                                unsigned long long mlen, const unsigned char *n,
-                                const unsigned char *k);
-
-SODIUM_EXPORT
-void crypto_stream_salsa2012_keygen(unsigned char k[crypto_stream_salsa2012_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_stream_salsa208.h b/tools/sdk/include/libsodium/sodium/crypto_stream_salsa208.h
deleted file mode 100644
index 02b4166e1ca..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_stream_salsa208.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef crypto_stream_salsa208_H
-#define crypto_stream_salsa208_H
-
-/*
- *  WARNING: This is just a stream cipher. It is NOT authenticated encryption.
- *  While it provides some protection against eavesdropping, it does NOT
- *  provide any security against active attacks.
- *  Unless you know what you're doing, what you are looking for is probably
- *  the crypto_box functions.
- */
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_stream_salsa208_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_stream_salsa208_keybytes(void);
-
-#define crypto_stream_salsa208_NONCEBYTES 8U
-SODIUM_EXPORT
-size_t crypto_stream_salsa208_noncebytes(void);
-
-SODIUM_EXPORT
-int crypto_stream_salsa208(unsigned char *c, unsigned long long clen,
-                           const unsigned char *n, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_salsa208_xor(unsigned char *c, const unsigned char *m,
-                               unsigned long long mlen, const unsigned char *n,
-                               const unsigned char *k);
-
-SODIUM_EXPORT
-void crypto_stream_salsa208_keygen(unsigned char k[crypto_stream_salsa208_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_stream_xchacha20.h b/tools/sdk/include/libsodium/sodium/crypto_stream_xchacha20.h
deleted file mode 100644
index f884798e740..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_stream_xchacha20.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef crypto_stream_xchacha20_H
-#define crypto_stream_xchacha20_H
-
-/*
- *  WARNING: This is just a stream cipher. It is NOT authenticated encryption.
- *  While it provides some protection against eavesdropping, it does NOT
- *  provide any security against active attacks.
- *  Unless you know what you're doing, what you are looking for is probably
- *  the crypto_box functions.
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_stream_xchacha20_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_stream_xchacha20_keybytes(void);
-
-#define crypto_stream_xchacha20_NONCEBYTES 24U
-SODIUM_EXPORT
-size_t crypto_stream_xchacha20_noncebytes(void);
-
-SODIUM_EXPORT
-int crypto_stream_xchacha20(unsigned char *c, unsigned long long clen,
-                            const unsigned char *n, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_xchacha20_xor(unsigned char *c, const unsigned char *m,
-                                unsigned long long mlen, const unsigned char *n,
-                                const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_xchacha20_xor_ic(unsigned char *c, const unsigned char *m,
-                                   unsigned long long mlen,
-                                   const unsigned char *n, uint64_t ic,
-                                   const unsigned char *k);
-
-SODIUM_EXPORT
-void crypto_stream_xchacha20_keygen(unsigned char k[crypto_stream_xchacha20_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_stream_xsalsa20.h b/tools/sdk/include/libsodium/sodium/crypto_stream_xsalsa20.h
deleted file mode 100644
index ed5ae3c3d3c..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_stream_xsalsa20.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef crypto_stream_xsalsa20_H
-#define crypto_stream_xsalsa20_H
-
-/*
- *  WARNING: This is just a stream cipher. It is NOT authenticated encryption.
- *  While it provides some protection against eavesdropping, it does NOT
- *  provide any security against active attacks.
- *  Unless you know what you're doing, what you are looking for is probably
- *  the crypto_box functions.
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-#define crypto_stream_xsalsa20_KEYBYTES 32U
-SODIUM_EXPORT
-size_t crypto_stream_xsalsa20_keybytes(void);
-
-#define crypto_stream_xsalsa20_NONCEBYTES 24U
-SODIUM_EXPORT
-size_t crypto_stream_xsalsa20_noncebytes(void);
-
-SODIUM_EXPORT
-int crypto_stream_xsalsa20(unsigned char *c, unsigned long long clen,
-                           const unsigned char *n, const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_xsalsa20_xor(unsigned char *c, const unsigned char *m,
-                               unsigned long long mlen, const unsigned char *n,
-                               const unsigned char *k);
-
-SODIUM_EXPORT
-int crypto_stream_xsalsa20_xor_ic(unsigned char *c, const unsigned char *m,
-                                  unsigned long long mlen,
-                                  const unsigned char *n, uint64_t ic,
-                                  const unsigned char *k);
-
-SODIUM_EXPORT
-void crypto_stream_xsalsa20_keygen(unsigned char k[crypto_stream_xsalsa20_KEYBYTES]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_verify_16.h b/tools/sdk/include/libsodium/sodium/crypto_verify_16.h
deleted file mode 100644
index 5e9eeabee84..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_verify_16.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef crypto_verify_16_H
-#define crypto_verify_16_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_verify_16_BYTES 16U
-SODIUM_EXPORT
-size_t crypto_verify_16_bytes(void);
-
-SODIUM_EXPORT
-int crypto_verify_16(const unsigned char *x, const unsigned char *y)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_verify_32.h b/tools/sdk/include/libsodium/sodium/crypto_verify_32.h
deleted file mode 100644
index 281b5a1bb79..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_verify_32.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef crypto_verify_32_H
-#define crypto_verify_32_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_verify_32_BYTES 32U
-SODIUM_EXPORT
-size_t crypto_verify_32_bytes(void);
-
-SODIUM_EXPORT
-int crypto_verify_32(const unsigned char *x, const unsigned char *y)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/crypto_verify_64.h b/tools/sdk/include/libsodium/sodium/crypto_verify_64.h
deleted file mode 100644
index 0dc7c304a99..00000000000
--- a/tools/sdk/include/libsodium/sodium/crypto_verify_64.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef crypto_verify_64_H
-#define crypto_verify_64_H
-
-#include <stddef.h>
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define crypto_verify_64_BYTES 64U
-SODIUM_EXPORT
-size_t crypto_verify_64_bytes(void);
-
-SODIUM_EXPORT
-int crypto_verify_64(const unsigned char *x, const unsigned char *y)
-            __attribute__ ((warn_unused_result));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/export.h b/tools/sdk/include/libsodium/sodium/export.h
deleted file mode 100644
index c33bced8188..00000000000
--- a/tools/sdk/include/libsodium/sodium/export.h
+++ /dev/null
@@ -1,44 +0,0 @@
-
-#ifndef sodium_export_H
-#define sodium_export_H
-
-#ifndef __GNUC__
-# ifdef __attribute__
-#  undef __attribute__
-# endif
-# define __attribute__(a)
-#endif
-
-#ifdef SODIUM_STATIC
-# define SODIUM_EXPORT
-#else
-# if defined(_MSC_VER)
-#  ifdef SODIUM_DLL_EXPORT
-#   define SODIUM_EXPORT __declspec(dllexport)
-#  else
-#   define SODIUM_EXPORT __declspec(dllimport)
-#  endif
-# else
-#  if defined(__SUNPRO_C)
-#   ifndef __GNU_C__
-#    define SODIUM_EXPORT __attribute__ (visibility(__global))
-#   else
-#    define SODIUM_EXPORT __attribute__ __global
-#   endif
-#  elif defined(_MSG_VER)
-#   define SODIUM_EXPORT extern __declspec(dllexport)
-#  else
-#   define SODIUM_EXPORT __attribute__ ((visibility ("default")))
-#  endif
-# endif
-#endif
-
-#ifndef CRYPTO_ALIGN
-# if defined(__INTEL_COMPILER) || defined(_MSC_VER)
-#  define CRYPTO_ALIGN(x) __declspec(align(x))
-# else
-#  define CRYPTO_ALIGN(x) __attribute__ ((aligned(x)))
-# endif
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/private/common.h b/tools/sdk/include/libsodium/sodium/private/common.h
deleted file mode 100644
index 5e27e5749f9..00000000000
--- a/tools/sdk/include/libsodium/sodium/private/common.h
+++ /dev/null
@@ -1,217 +0,0 @@
-#ifndef common_H
-#define common_H 1
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-
-#define COMPILER_ASSERT(X) (void) sizeof(char[(X) ? 1 : -1])
-
-#define ROTL32(X, B) rotl32((X), (B))
-static inline uint32_t
-rotl32(const uint32_t x, const int b)
-{
-    return (x << b) | (x >> (32 - b));
-}
-
-#define ROTL64(X, B) rotl64((X), (B))
-static inline uint64_t
-rotl64(const uint64_t x, const int b)
-{
-    return (x << b) | (x >> (64 - b));
-}
-
-#define ROTR32(X, B) rotr32((X), (B))
-static inline uint32_t
-rotr32(const uint32_t x, const int b)
-{
-    return (x >> b) | (x << (32 - b));
-}
-
-#define ROTR64(X, B) rotr64((X), (B))
-static inline uint64_t
-rotr64(const uint64_t x, const int b)
-{
-    return (x >> b) | (x << (64 - b));
-}
-
-#define LOAD64_LE(SRC) load64_le(SRC)
-static inline uint64_t
-load64_le(const uint8_t src[8])
-{
-#ifdef NATIVE_LITTLE_ENDIAN
-    uint64_t w;
-    memcpy(&w, src, sizeof w);
-    return w;
-#else
-    uint64_t w = (uint64_t) src[0];
-    w |= (uint64_t) src[1] <<  8;
-    w |= (uint64_t) src[2] << 16;
-    w |= (uint64_t) src[3] << 24;
-    w |= (uint64_t) src[4] << 32;
-    w |= (uint64_t) src[5] << 40;
-    w |= (uint64_t) src[6] << 48;
-    w |= (uint64_t) src[7] << 56;
-    return w;
-#endif
-}
-
-#define STORE64_LE(DST, W) store64_le((DST), (W))
-static inline void
-store64_le(uint8_t dst[8], uint64_t w)
-{
-#ifdef NATIVE_LITTLE_ENDIAN
-    memcpy(dst, &w, sizeof w);
-#else
-    dst[0] = (uint8_t) w; w >>= 8;
-    dst[1] = (uint8_t) w; w >>= 8;
-    dst[2] = (uint8_t) w; w >>= 8;
-    dst[3] = (uint8_t) w; w >>= 8;
-    dst[4] = (uint8_t) w; w >>= 8;
-    dst[5] = (uint8_t) w; w >>= 8;
-    dst[6] = (uint8_t) w; w >>= 8;
-    dst[7] = (uint8_t) w;
-#endif
-}
-
-#define LOAD32_LE(SRC) load32_le(SRC)
-static inline uint32_t
-load32_le(const uint8_t src[4])
-{
-#ifdef NATIVE_LITTLE_ENDIAN
-    uint32_t w;
-    memcpy(&w, src, sizeof w);
-    return w;
-#else
-    uint32_t w = (uint32_t) src[0];
-    w |= (uint32_t) src[1] <<  8;
-    w |= (uint32_t) src[2] << 16;
-    w |= (uint32_t) src[3] << 24;
-    return w;
-#endif
-}
-
-#define STORE32_LE(DST, W) store32_le((DST), (W))
-static inline void
-store32_le(uint8_t dst[4], uint32_t w)
-{
-#ifdef NATIVE_LITTLE_ENDIAN
-    memcpy(dst, &w, sizeof w);
-#else
-    dst[0] = (uint8_t) w; w >>= 8;
-    dst[1] = (uint8_t) w; w >>= 8;
-    dst[2] = (uint8_t) w; w >>= 8;
-    dst[3] = (uint8_t) w;
-#endif
-}
-
-/* ----- */
-
-#define LOAD64_BE(SRC) load64_be(SRC)
-static inline uint64_t
-load64_be(const uint8_t src[8])
-{
-#ifdef NATIVE_BIG_ENDIAN
-    uint64_t w;
-    memcpy(&w, src, sizeof w);
-    return w;
-#else
-    uint64_t w = (uint64_t) src[7];
-    w |= (uint64_t) src[6] <<  8;
-    w |= (uint64_t) src[5] << 16;
-    w |= (uint64_t) src[4] << 24;
-    w |= (uint64_t) src[3] << 32;
-    w |= (uint64_t) src[2] << 40;
-    w |= (uint64_t) src[1] << 48;
-    w |= (uint64_t) src[0] << 56;
-    return w;
-#endif
-}
-
-#define STORE64_BE(DST, W) store64_be((DST), (W))
-static inline void
-store64_be(uint8_t dst[8], uint64_t w)
-{
-#ifdef NATIVE_BIG_ENDIAN
-    memcpy(dst, &w, sizeof w);
-#else
-    dst[7] = (uint8_t) w; w >>= 8;
-    dst[6] = (uint8_t) w; w >>= 8;
-    dst[5] = (uint8_t) w; w >>= 8;
-    dst[4] = (uint8_t) w; w >>= 8;
-    dst[3] = (uint8_t) w; w >>= 8;
-    dst[2] = (uint8_t) w; w >>= 8;
-    dst[1] = (uint8_t) w; w >>= 8;
-    dst[0] = (uint8_t) w;
-#endif
-}
-
-#define LOAD32_BE(SRC) load32_be(SRC)
-static inline uint32_t
-load32_be(const uint8_t src[4])
-{
-#ifdef NATIVE_BIG_ENDIAN
-    uint32_t w;
-    memcpy(&w, src, sizeof w);
-    return w;
-#else
-    uint32_t w = (uint32_t) src[3];
-    w |= (uint32_t) src[2] <<  8;
-    w |= (uint32_t) src[1] << 16;
-    w |= (uint32_t) src[0] << 24;
-    return w;
-#endif
-}
-
-#define STORE32_BE(DST, W) store32_be((DST), (W))
-static inline void
-store32_be(uint8_t dst[4], uint32_t w)
-{
-#ifdef NATIVE_BIG_ENDIAN
-    memcpy(dst, &w, sizeof w);
-#else
-    dst[3] = (uint8_t) w; w >>= 8;
-    dst[2] = (uint8_t) w; w >>= 8;
-    dst[1] = (uint8_t) w; w >>= 8;
-    dst[0] = (uint8_t) w;
-#endif
-}
-
-#ifndef __GNUC__
-# ifdef __attribute__
-#  undef __attribute__
-# endif
-# define __attribute__(a)
-#endif
-
-#ifndef CRYPTO_ALIGN
-# if defined(__INTEL_COMPILER) || defined(_MSC_VER)
-#  define CRYPTO_ALIGN(x) __declspec(align(x))
-# else
-#  define CRYPTO_ALIGN(x) __attribute__ ((aligned(x)))
-# endif
-#endif
-
-#if defined(_MSC_VER) && \
-    (defined(_M_X64) || defined(_M_AMD64) || defined(_M_IX86))
-
-# include <intrin.h>
-
-# define HAVE_INTRIN_H    1
-# define HAVE_MMINTRIN_H  1
-# define HAVE_EMMINTRIN_H 1
-# define HAVE_PMMINTRIN_H 1
-# define HAVE_TMMINTRIN_H 1
-# define HAVE_SMMINTRIN_H 1
-# define HAVE_AVXINTRIN_H 1
-# if _MSC_VER >= 1600
-#  define HAVE_WMMINTRIN_H 1
-# endif
-# if _MSC_VER >= 1700 && defined(_M_X64)
-#  define HAVE_AVX2INTRIN_H 1
-# endif
-#elif defined(HAVE_INTRIN_H)
-# include <intrin.h>
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/private/curve25519_ref10.h b/tools/sdk/include/libsodium/sodium/private/curve25519_ref10.h
deleted file mode 100644
index 2b9caeb1f0d..00000000000
--- a/tools/sdk/include/libsodium/sodium/private/curve25519_ref10.h
+++ /dev/null
@@ -1,160 +0,0 @@
-#ifndef curve25519_ref10_H
-#define curve25519_ref10_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-#define fe crypto_core_curve25519_ref10_fe
-typedef int32_t fe[10];
-
-/*
- fe means field element.
- Here the field is \Z/(2^255-19).
- An element t, entries t[0]...t[9], represents the integer
- t[0]+2^26 t[1]+2^51 t[2]+2^77 t[3]+2^102 t[4]+...+2^230 t[9].
- Bounds on each t[i] vary depending on context.
- */
-
-#define fe_frombytes crypto_core_curve25519_ref10_fe_frombytes
-#define fe_tobytes crypto_core_curve25519_ref10_fe_tobytes
-#define fe_copy crypto_core_curve25519_ref10_fe_copy
-#define fe_isnonzero crypto_core_curve25519_ref10_fe_isnonzero
-#define fe_isnegative crypto_core_curve25519_ref10_fe_isnegative
-#define fe_0 crypto_core_curve25519_ref10_fe_0
-#define fe_1 crypto_core_curve25519_ref10_fe_1
-#define fe_cmov crypto_core_curve25519_ref10_fe_cmov
-#define fe_add crypto_core_curve25519_ref10_fe_add
-#define fe_sub crypto_core_curve25519_ref10_fe_sub
-#define fe_neg crypto_core_curve25519_ref10_fe_neg
-#define fe_mul crypto_core_curve25519_ref10_fe_mul
-#define fe_sq crypto_core_curve25519_ref10_fe_sq
-#define fe_sq2 crypto_core_curve25519_ref10_fe_sq2
-#define fe_invert crypto_core_curve25519_ref10_fe_invert
-#define fe_pow22523 crypto_core_curve25519_ref10_fe_pow22523
-
-extern void fe_frombytes(fe,const unsigned char *);
-extern void fe_tobytes(unsigned char *,const fe);
-
-extern void fe_copy(fe,const fe);
-extern int fe_isnonzero(const fe);
-extern int fe_isnegative(const fe);
-extern void fe_0(fe);
-extern void fe_1(fe);
-extern void fe_cmov(fe,const fe,unsigned int);
-extern void fe_add(fe,const fe,const fe);
-extern void fe_sub(fe,const fe,const fe);
-extern void fe_neg(fe,const fe);
-extern void fe_mul(fe,const fe,const fe);
-extern void fe_sq(fe,const fe);
-extern void fe_sq2(fe,const fe);
-extern void fe_invert(fe,const fe);
-extern void fe_pow22523(fe,const fe);
-
-/*
- ge means group element.
- *
- Here the group is the set of pairs (x,y) of field elements (see fe.h)
- satisfying -x^2 + y^2 = 1 + d x^2y^2
- where d = -121665/121666.
- *
- Representations:
- ge_p2 (projective): (X:Y:Z) satisfying x=X/Z, y=Y/Z
- ge_p3 (extended): (X:Y:Z:T) satisfying x=X/Z, y=Y/Z, XY=ZT
- ge_p1p1 (completed): ((X:Z),(Y:T)) satisfying x=X/Z, y=Y/T
- ge_precomp (Duif): (y+x,y-x,2dxy)
- */
-
-#define ge_p2 crypto_core_curve25519_ref10_ge_p2
-typedef struct {
-    fe X;
-    fe Y;
-    fe Z;
-} ge_p2;
-
-#define ge_p3 crypto_core_curve25519_ref10_ge_p3
-typedef struct {
-    fe X;
-    fe Y;
-    fe Z;
-    fe T;
-} ge_p3;
-
-#define ge_p1p1 crypto_core_curve25519_ref10_ge_p1p1
-typedef struct {
-    fe X;
-    fe Y;
-    fe Z;
-    fe T;
-} ge_p1p1;
-
-#define ge_precomp crypto_core_curve25519_ref10_ge_precomp
-typedef struct {
-    fe yplusx;
-    fe yminusx;
-    fe xy2d;
-} ge_precomp;
-
-#define ge_cached crypto_core_curve25519_ref10_ge_cached
-typedef struct {
-    fe YplusX;
-    fe YminusX;
-    fe Z;
-    fe T2d;
-} ge_cached;
-
-#define ge_frombytes_negate_vartime crypto_core_curve25519_ref10_ge_frombytes_negate_vartime
-#define ge_tobytes crypto_core_curve25519_ref10_ge_tobytes
-#define ge_p3_tobytes crypto_core_curve25519_ref10_ge_p3_tobytes
-
-#define ge_p2_0 crypto_core_curve25519_ref10_ge_p2_0
-#define ge_p3_0 crypto_core_curve25519_ref10_ge_p3_0
-#define ge_precomp_0 crypto_core_curve25519_ref10_ge_precomp_0
-#define ge_p3_to_p2 crypto_core_curve25519_ref10_ge_p3_to_p2
-#define ge_p3_to_cached crypto_core_curve25519_ref10_ge_p3_to_cached
-#define ge_p1p1_to_p2 crypto_core_curve25519_ref10_ge_p1p1_to_p2
-#define ge_p1p1_to_p3 crypto_core_curve25519_ref10_ge_p1p1_to_p3
-#define ge_p2_dbl crypto_core_curve25519_ref10_ge_p2_dbl
-#define ge_p3_dbl crypto_core_curve25519_ref10_ge_p3_dbl
-
-#define ge_madd crypto_core_curve25519_ref10_ge_madd
-#define ge_msub crypto_core_curve25519_ref10_ge_msub
-#define ge_add crypto_core_curve25519_ref10_ge_add
-#define ge_sub crypto_core_curve25519_ref10_ge_sub
-#define ge_scalarmult_base crypto_core_curve25519_ref10_ge_scalarmult_base
-#define ge_double_scalarmult_vartime crypto_core_curve25519_ref10_ge_double_scalarmult_vartime
-#define ge_scalarmult_vartime crypto_core_curve25519_ref10_ge_scalarmult_vartime
-
-extern void ge_tobytes(unsigned char *,const ge_p2 *);
-extern void ge_p3_tobytes(unsigned char *,const ge_p3 *);
-extern int ge_frombytes_negate_vartime(ge_p3 *,const unsigned char *);
-
-extern void ge_p2_0(ge_p2 *);
-extern void ge_p3_0(ge_p3 *);
-extern void ge_precomp_0(ge_precomp *);
-extern void ge_p3_to_p2(ge_p2 *,const ge_p3 *);
-extern void ge_p3_to_cached(ge_cached *,const ge_p3 *);
-extern void ge_p1p1_to_p2(ge_p2 *,const ge_p1p1 *);
-extern void ge_p1p1_to_p3(ge_p3 *,const ge_p1p1 *);
-extern void ge_p2_dbl(ge_p1p1 *,const ge_p2 *);
-extern void ge_p3_dbl(ge_p1p1 *,const ge_p3 *);
-
-extern void ge_madd(ge_p1p1 *,const ge_p3 *,const ge_precomp *);
-extern void ge_msub(ge_p1p1 *,const ge_p3 *,const ge_precomp *);
-extern void ge_add(ge_p1p1 *,const ge_p3 *,const ge_cached *);
-extern void ge_sub(ge_p1p1 *,const ge_p3 *,const ge_cached *);
-extern void ge_scalarmult_base(ge_p3 *,const unsigned char *);
-extern void ge_double_scalarmult_vartime(ge_p2 *,const unsigned char *,const ge_p3 *,const unsigned char *);
-extern void ge_scalarmult_vartime(ge_p3 *,const unsigned char *,const ge_p3 *);
-
-/*
- The set of scalars is \Z/l
- where l = 2^252 + 27742317777372353535851937790883648493.
- */
-
-#define sc_reduce crypto_core_curve25519_ref10_sc_reduce
-#define sc_muladd crypto_core_curve25519_ref10_sc_muladd
-
-extern void sc_reduce(unsigned char *);
-extern void sc_muladd(unsigned char *,const unsigned char *,const unsigned char *,const unsigned char *);
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/private/mutex.h b/tools/sdk/include/libsodium/sodium/private/mutex.h
deleted file mode 100644
index 322b6742b26..00000000000
--- a/tools/sdk/include/libsodium/sodium/private/mutex.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef mutex_H
-#define mutex_H 1
-
-extern int sodium_crit_enter(void);
-extern int sodium_crit_leave(void);
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/private/sse2_64_32.h b/tools/sdk/include/libsodium/sodium/private/sse2_64_32.h
deleted file mode 100644
index d0455b41b49..00000000000
--- a/tools/sdk/include/libsodium/sodium/private/sse2_64_32.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#ifndef sse2_64_32_H
-#define sse2_64_32_H 1
-
-#include "common.h"
-
-#ifdef HAVE_INTRIN_H
-# include <intrin.h>
-#endif
-
-#if defined(HAVE_EMMINTRIN_H) && \
-    !(defined(__amd64) || defined(__amd64__) || defined(__x86_64__) || \
-      defined(_M_X64) || defined(_M_AMD64))
-
-# include <emmintrin.h>
-# include <stdint.h>
-
-# ifndef _mm_set_epi64x
-#  define _mm_set_epi64x(Q0, Q1) sodium__mm_set_epi64x((Q0), (Q1))
-static inline __m128i
-sodium__mm_set_epi64x(int64_t q1, int64_t q0)
-{
-    union { int64_t as64; int32_t as32[2]; } x0, x1;
-    x0.as64 = q0; x1.as64 = q1;
-    return _mm_set_epi32(x1.as32[1], x1.as32[0], x0.as32[1], x0.as32[0]);
-}
-# endif
-
-# ifndef _mm_set1_epi64x
-#  define _mm_set1_epi64x(Q) sodium__mm_set1_epi64x(Q)
-static inline __m128i
-sodium__mm_set1_epi64x(int64_t q)
-{
-    return _mm_set_epi64x(q, q);
-}
-# endif
-
-# ifndef _mm_cvtsi64_si128
-#  define _mm_cvtsi64_si128(Q) sodium__mm_cvtsi64_si128(Q)
-static inline __m128i
-sodium__mm_cvtsi64_si128(int64_t q)
-{
-    union { int64_t as64; int32_t as32[2]; } x;
-    x.as64 = q;
-    return _mm_setr_epi32(x.as32[0], x.as32[1], 0, 0);
-}
-# endif
-
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/randombytes.h b/tools/sdk/include/libsodium/sodium/randombytes.h
deleted file mode 100644
index d112fb293e5..00000000000
--- a/tools/sdk/include/libsodium/sodium/randombytes.h
+++ /dev/null
@@ -1,66 +0,0 @@
-
-#ifndef randombytes_H
-#define randombytes_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-#include <sys/types.h>
-
-#include "export.h"
-
-#ifdef __cplusplus
-# ifdef __GNUC__
-#  pragma GCC diagnostic ignored "-Wlong-long"
-# endif
-extern "C" {
-#endif
-
-typedef struct randombytes_implementation {
-    const char *(*implementation_name)(void); /* required */
-    uint32_t    (*random)(void);              /* required */
-    void        (*stir)(void);                /* optional */
-    uint32_t    (*uniform)(const uint32_t upper_bound); /* optional, a default implementation will be used if NULL */
-    void        (*buf)(void * const buf, const size_t size); /* required */
-    int         (*close)(void);               /* optional */
-} randombytes_implementation;
-
-#define randombytes_SEEDBYTES 32U
-SODIUM_EXPORT
-size_t randombytes_seedbytes(void);
-
-SODIUM_EXPORT
-void randombytes_buf(void * const buf, const size_t size);
-
-SODIUM_EXPORT
-void randombytes_buf_deterministic(void * const buf, const size_t size,
-                                   const unsigned char seed[randombytes_SEEDBYTES]);
-
-SODIUM_EXPORT
-uint32_t randombytes_random(void);
-
-SODIUM_EXPORT
-uint32_t randombytes_uniform(const uint32_t upper_bound);
-
-SODIUM_EXPORT
-void randombytes_stir(void);
-
-SODIUM_EXPORT
-int randombytes_close(void);
-
-SODIUM_EXPORT
-int randombytes_set_implementation(randombytes_implementation *impl);
-
-SODIUM_EXPORT
-const char *randombytes_implementation_name(void);
-
-/* -- NaCl compatibility interface -- */
-
-SODIUM_EXPORT
-void randombytes(unsigned char * const buf, const unsigned long long buf_len);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/randombytes_nativeclient.h b/tools/sdk/include/libsodium/sodium/randombytes_nativeclient.h
deleted file mode 100644
index 5158d8c3c33..00000000000
--- a/tools/sdk/include/libsodium/sodium/randombytes_nativeclient.h
+++ /dev/null
@@ -1,23 +0,0 @@
-
-#ifndef randombytes_nativeclient_H
-#define randombytes_nativeclient_H
-
-#ifdef __native_client__
-
-# include "export.h"
-# include "randombytes.h"
-
-# ifdef __cplusplus
-extern "C" {
-# endif
-
-SODIUM_EXPORT
-extern struct randombytes_implementation randombytes_nativeclient_implementation;
-
-# ifdef __cplusplus
-}
-# endif
-
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/randombytes_salsa20_random.h b/tools/sdk/include/libsodium/sodium/randombytes_salsa20_random.h
deleted file mode 100644
index 4deae15b6d9..00000000000
--- a/tools/sdk/include/libsodium/sodium/randombytes_salsa20_random.h
+++ /dev/null
@@ -1,19 +0,0 @@
-
-#ifndef randombytes_salsa20_random_H
-#define randombytes_salsa20_random_H
-
-#include "export.h"
-#include "randombytes.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-SODIUM_EXPORT
-extern struct randombytes_implementation randombytes_salsa20_implementation;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/randombytes_sysrandom.h b/tools/sdk/include/libsodium/sodium/randombytes_sysrandom.h
deleted file mode 100644
index 9e27b674c79..00000000000
--- a/tools/sdk/include/libsodium/sodium/randombytes_sysrandom.h
+++ /dev/null
@@ -1,19 +0,0 @@
-
-#ifndef randombytes_sysrandom_H
-#define randombytes_sysrandom_H
-
-#include "export.h"
-#include "randombytes.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-SODIUM_EXPORT
-extern struct randombytes_implementation randombytes_sysrandom_implementation;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/runtime.h b/tools/sdk/include/libsodium/sodium/runtime.h
deleted file mode 100644
index 76859ea0e13..00000000000
--- a/tools/sdk/include/libsodium/sodium/runtime.h
+++ /dev/null
@@ -1,46 +0,0 @@
-
-#ifndef sodium_runtime_H
-#define sodium_runtime_H
-
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-SODIUM_EXPORT
-int sodium_runtime_has_neon(void);
-
-SODIUM_EXPORT
-int sodium_runtime_has_sse2(void);
-
-SODIUM_EXPORT
-int sodium_runtime_has_sse3(void);
-
-SODIUM_EXPORT
-int sodium_runtime_has_ssse3(void);
-
-SODIUM_EXPORT
-int sodium_runtime_has_sse41(void);
-
-SODIUM_EXPORT
-int sodium_runtime_has_avx(void);
-
-SODIUM_EXPORT
-int sodium_runtime_has_avx2(void);
-
-SODIUM_EXPORT
-int sodium_runtime_has_pclmul(void);
-
-SODIUM_EXPORT
-int sodium_runtime_has_aesni(void);
-
-/* ------------------------------------------------------------------------- */
-
-int _sodium_runtime_get_cpu_features(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/utils.h b/tools/sdk/include/libsodium/sodium/utils.h
deleted file mode 100644
index 0a7aadb434c..00000000000
--- a/tools/sdk/include/libsodium/sodium/utils.h
+++ /dev/null
@@ -1,131 +0,0 @@
-
-#ifndef sodium_utils_H
-#define sodium_utils_H
-
-#include <stddef.h>
-
-#include "export.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef SODIUM_C99
-# if defined(__cplusplus) || !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901L
-#  define SODIUM_C99(X)
-# else
-#  define SODIUM_C99(X) X
-# endif
-#endif
-
-SODIUM_EXPORT
-void sodium_memzero(void * const pnt, const size_t len);
-
-/*
- * WARNING: sodium_memcmp() must be used to verify if two secret keys
- * are equal, in constant time.
- * It returns 0 if the keys are equal, and -1 if they differ.
- * This function is not designed for lexicographical comparisons.
- */
-SODIUM_EXPORT
-int sodium_memcmp(const void * const b1_, const void * const b2_, size_t len)
-            __attribute__ ((warn_unused_result));
-
-/*
- * sodium_compare() returns -1 if b1_ < b2_, 1 if b1_ > b2_ and 0 if b1_ == b2_
- * It is suitable for lexicographical comparisons, or to compare nonces
- * and counters stored in little-endian format.
- * However, it is slower than sodium_memcmp().
- */
-SODIUM_EXPORT
-int sodium_compare(const unsigned char *b1_, const unsigned char *b2_,
-                   size_t len)
-            __attribute__ ((warn_unused_result));
-
-SODIUM_EXPORT
-int sodium_is_zero(const unsigned char *n, const size_t nlen);
-
-SODIUM_EXPORT
-void sodium_increment(unsigned char *n, const size_t nlen);
-
-SODIUM_EXPORT
-void sodium_add(unsigned char *a, const unsigned char *b, const size_t len);
-
-SODIUM_EXPORT
-char *sodium_bin2hex(char * const hex, const size_t hex_maxlen,
-                     const unsigned char * const bin, const size_t bin_len);
-
-SODIUM_EXPORT
-int sodium_hex2bin(unsigned char * const bin, const size_t bin_maxlen,
-                   const char * const hex, const size_t hex_len,
-                   const char * const ignore, size_t * const bin_len,
-                   const char ** const hex_end);
-
-SODIUM_EXPORT
-int sodium_mlock(void * const addr, const size_t len);
-
-SODIUM_EXPORT
-int sodium_munlock(void * const addr, const size_t len);
-
-/* WARNING: sodium_malloc() and sodium_allocarray() are not general-purpose
- * allocation functions.
- *
- * They return a pointer to a region filled with 0xd0 bytes, immediately
- * followed by a guard page.
- * As a result, accessing a single byte after the requested allocation size
- * will intentionally trigger a segmentation fault.
- *
- * A canary and an additional guard page placed before the beginning of the
- * region may also kill the process if a buffer underflow is detected.
- *
- * The memory layout is:
- * [unprotected region size (read only)][guard page (no access)][unprotected pages (read/write)][guard page (no access)]
- * With the layout of the unprotected pages being:
- * [optional padding][16-bytes canary][user region]
- *
- * However:
- * - These functions are significantly slower than standard functions
- * - Each allocation requires 3 or 4 additional pages
- * - The returned address will not be aligned if the allocation size is not
- *   a multiple of the required alignment. For this reason, these functions
- *   are designed to store data, such as secret keys and messages.
- *
- * sodium_malloc() can be used to allocate any libsodium data structure.
- *
- * The crypto_generichash_state structure is packed and its length is
- * either 357 or 361 bytes. For this reason, when using sodium_malloc() to
- * allocate a crypto_generichash_state structure, padding must be added in
- * order to ensure proper alignment. crypto_generichash_statebytes()
- * returns the rounded up structure size, and should be prefered to sizeof():
- * state = sodium_malloc(crypto_generichash_statebytes());
- */
-
-SODIUM_EXPORT
-void *sodium_malloc(const size_t size)
-            __attribute__ ((malloc));
-
-SODIUM_EXPORT
-void *sodium_allocarray(size_t count, size_t size)
-            __attribute__ ((malloc));
-
-SODIUM_EXPORT
-void sodium_free(void *ptr);
-
-SODIUM_EXPORT
-int sodium_mprotect_noaccess(void *ptr);
-
-SODIUM_EXPORT
-int sodium_mprotect_readonly(void *ptr);
-
-SODIUM_EXPORT
-int sodium_mprotect_readwrite(void *ptr);
-
-/* -------- */
-
-int _sodium_alloc_init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/libsodium/sodium/version.h b/tools/sdk/include/libsodium/sodium/version.h
deleted file mode 100644
index c0bf5869deb..00000000000
--- a/tools/sdk/include/libsodium/sodium/version.h
+++ /dev/null
@@ -1,35 +0,0 @@
-
-#ifndef sodium_version_H
-#define sodium_version_H
-
-#include <sodium/export.h>
-
-/* IMPORTANT: As we don't use autotools, these version are not automatically
-   updated if we change submodules. They need to be changed manually.
-*/
-
-#define SODIUM_VERSION_STRING "1.0.12-idf"
-
-/* Note: these are not the same as the overall version, see
-   configure.ac for the relevant macros */
-#define SODIUM_LIBRARY_VERSION_MAJOR 9
-#define SODIUM_LIBRARY_VERSION_MINOR 4
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-SODIUM_EXPORT
-const char *sodium_version_string(void);
-
-SODIUM_EXPORT
-int         sodium_library_version_major(void);
-
-SODIUM_EXPORT
-int         sodium_library_version_minor(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/log/esp_log.h b/tools/sdk/include/log/esp_log.h
deleted file mode 100644
index 8616c561033..00000000000
--- a/tools/sdk/include/log/esp_log.h
+++ /dev/null
@@ -1,328 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_LOG_H__
-#define __ESP_LOG_H__
-
-#include <stdint.h>
-#include <stdarg.h>
-#include "sdkconfig.h"
-#include <rom/ets_sys.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Log level
- *
- */
-typedef enum {
-    ESP_LOG_NONE,       /*!< No log output */
-    ESP_LOG_ERROR,      /*!< Critical errors, software module can not recover on its own */
-    ESP_LOG_WARN,       /*!< Error conditions from which recovery measures have been taken */
-    ESP_LOG_INFO,       /*!< Information messages which describe normal flow of events */
-    ESP_LOG_DEBUG,      /*!< Extra information which is not necessary for normal use (values, pointers, sizes, etc). */
-    ESP_LOG_VERBOSE     /*!< Bigger chunks of debugging information, or frequent messages which can potentially flood the output. */
-} esp_log_level_t;
-
-typedef int (*vprintf_like_t)(const char *, va_list);
-
-/**
- * @brief Set log level for given tag
- *
- * If logging for given component has already been enabled, changes previous setting.
- *
- * Note that this function can not raise log level above the level set using
- * CONFIG_LOG_DEFAULT_LEVEL setting in menuconfig.
- *
- * To raise log level above the default one for a given file, define
- * LOG_LOCAL_LEVEL to one of the ESP_LOG_* values, before including
- * esp_log.h in this file.
- *
- * @param tag Tag of the log entries to enable. Must be a non-NULL zero terminated string.
- *            Value "*" resets log level for all tags to the given value.
- *
- * @param level  Selects log level to enable. Only logs at this and lower verbosity
- * levels will be shown.
- */
-void esp_log_level_set(const char* tag, esp_log_level_t level);
-
-/**
- * @brief Set function used to output log entries
- *
- * By default, log output goes to UART0. This function can be used to redirect log
- * output to some other destination, such as file or network. Returns the original
- * log handler, which may be necessary to return output to the previous destination.
- *
- * @param func new Function used for output. Must have same signature as vprintf.
- *
- * @return func old Function used for output.
- */
-vprintf_like_t esp_log_set_vprintf(vprintf_like_t func);
-
-/**
- * @brief Function which returns timestamp to be used in log output
- *
- * This function is used in expansion of ESP_LOGx macros.
- * In the 2nd stage bootloader, and at early application startup stage
- * this function uses CPU cycle counter as time source. Later when
- * FreeRTOS scheduler start running, it switches to FreeRTOS tick count.
- *
- * For now, we ignore millisecond counter overflow.
- *
- * @return timestamp, in milliseconds
- */
-uint32_t esp_log_timestamp(void);
-
-/**
- * @brief Function which returns timestamp to be used in log output
- *
- * This function uses HW cycle counter and does not depend on OS,
- * so it can be safely used after application crash.
- *
- * @return timestamp, in milliseconds
- */
-uint32_t esp_log_early_timestamp(void);
-
-/**
- * @brief Write message into the log
- *
- * This function is not intended to be used directly. Instead, use one of
- * ESP_LOGE, ESP_LOGW, ESP_LOGI, ESP_LOGD, ESP_LOGV macros.
- *
- * This function or these macros should not be used from an interrupt.
- */
-void esp_log_write(esp_log_level_t level, const char* tag, const char* format, ...) __attribute__ ((format (printf, 3, 4)));
-
-/** @cond */
-
-/**
- * @brief Write message into the log, va_list variant
- * @see esp_log_write()
- *
- * This function is provided to ease integration toward other logging framework,
- * so that esp_log can be used as a log sink.
- */
-void esp_log_writev(esp_log_level_t level, const char* tag, const char* format, va_list args);
-
-#include "esp_log_internal.h"
-
-#ifndef LOG_LOCAL_LEVEL
-#ifndef BOOTLOADER_BUILD
-#define LOG_LOCAL_LEVEL  CONFIG_LOG_DEFAULT_LEVEL
-#else
-#define LOG_LOCAL_LEVEL  CONFIG_LOG_BOOTLOADER_LEVEL
-#endif
-#endif
-
-/** @endcond */
-
-/**
- * @brief Log a buffer of hex bytes at specified level, separated into 16 bytes each line.
- *
- * @param  tag      description tag
- * @param  buffer   Pointer to the buffer array
- * @param  buff_len length of buffer in bytes
- * @param  level    level of the log
- *
- */
-#define ESP_LOG_BUFFER_HEX_LEVEL( tag, buffer, buff_len, level ) \
-    do {\
-        if ( LOG_LOCAL_LEVEL >= (level) ) { \
-            esp_log_buffer_hex_internal( tag, buffer, buff_len, level ); \
-        } \
-    } while(0)
-
-/**
- * @brief Log a buffer of characters at specified level, separated into 16 bytes each line. Buffer should contain only printable characters.
- *
- * @param  tag      description tag
- * @param  buffer   Pointer to the buffer array
- * @param  buff_len length of buffer in bytes
- * @param  level    level of the log
- *
- */
-#define ESP_LOG_BUFFER_CHAR_LEVEL( tag, buffer, buff_len, level ) \
-    do {\
-        if ( LOG_LOCAL_LEVEL >= (level) ) { \
-            esp_log_buffer_char_internal( tag, buffer, buff_len, level ); \
-        } \
-    } while(0)
-
-/**
- * @brief Dump a buffer to the log at specified level.
- * 
- * The dump log shows just like the one below:
- * 
- *      W (195) log_example: 0x3ffb4280   45 53 50 33 32 20 69 73  20 67 72 65 61 74 2c 20  |ESP32 is great, |
- *      W (195) log_example: 0x3ffb4290   77 6f 72 6b 69 6e 67 20  61 6c 6f 6e 67 20 77 69  |working along wi|
- *      W (205) log_example: 0x3ffb42a0   74 68 20 74 68 65 20 49  44 46 2e 00              |th the IDF..|
- *      
- * It is highly recommend to use terminals with over 102 text width.
- * 
- * @param tag description tag
- * @param buffer Pointer to the buffer array
- * @param buff_len length of buffer in bytes
- * @param level level of the log
- */
-#define ESP_LOG_BUFFER_HEXDUMP( tag, buffer, buff_len, level ) \
-    do { \
-        if ( LOG_LOCAL_LEVEL >= (level) ) { \
-            esp_log_buffer_hexdump_internal( tag, buffer, buff_len, level); \
-        } \
-    } while(0)
-
-/**
- * @brief Log a buffer of hex bytes at Info level
- *
- * @param  tag      description tag
- * @param  buffer   Pointer to the buffer array
- * @param  buff_len length of buffer in bytes
- *
- * @see ``esp_log_buffer_hex_level``
- *
- */
-#define ESP_LOG_BUFFER_HEX(tag, buffer, buff_len) \
-    do { \
-        if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { \
-            ESP_LOG_BUFFER_HEX_LEVEL( tag, buffer, buff_len, ESP_LOG_INFO ); \
-        }\
-    } while(0)
-
-/**
- * @brief Log a buffer of characters at Info level. Buffer should contain only printable characters.
- *
- * @param  tag      description tag
- * @param  buffer   Pointer to the buffer array
- * @param  buff_len length of buffer in bytes
- *
- * @see ``esp_log_buffer_char_level``
- *
- */
-#define ESP_LOG_BUFFER_CHAR(tag, buffer, buff_len) \
-    do { \
-        if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { \
-            ESP_LOG_BUFFER_CHAR_LEVEL( tag, buffer, buff_len, ESP_LOG_INFO ); \
-        }\
-    } while(0)
-
-/** @cond */
-
-//to be back compatible
-#define esp_log_buffer_hex      ESP_LOG_BUFFER_HEX
-#define esp_log_buffer_char     ESP_LOG_BUFFER_CHAR
-
-
-#if CONFIG_LOG_COLORS
-#define LOG_COLOR_BLACK   "30"
-#define LOG_COLOR_RED     "31"
-#define LOG_COLOR_GREEN   "32"
-#define LOG_COLOR_BROWN   "33"
-#define LOG_COLOR_BLUE    "34"
-#define LOG_COLOR_PURPLE  "35"
-#define LOG_COLOR_CYAN    "36"
-#define LOG_COLOR(COLOR)  "\033[0;" COLOR "m"
-#define LOG_BOLD(COLOR)   "\033[1;" COLOR "m"
-#define LOG_RESET_COLOR   "\033[0m"
-#define LOG_COLOR_E       LOG_COLOR(LOG_COLOR_RED)
-#define LOG_COLOR_W       LOG_COLOR(LOG_COLOR_BROWN)
-#define LOG_COLOR_I       LOG_COLOR(LOG_COLOR_GREEN)
-#define LOG_COLOR_D
-#define LOG_COLOR_V
-#else //CONFIG_LOG_COLORS
-#define LOG_COLOR_E
-#define LOG_COLOR_W
-#define LOG_COLOR_I
-#define LOG_COLOR_D
-#define LOG_COLOR_V
-#define LOG_RESET_COLOR
-#endif //CONFIG_LOG_COLORS
-
-#define LOG_FORMAT(letter, format)  LOG_COLOR_ ## letter #letter " (%d) %s: " format LOG_RESET_COLOR "\n"
-
-/** @endcond */
-
-/// macro to output logs in startup code, before heap allocator and syscalls have been initialized. log at ``ESP_LOG_ERROR`` level. @see ``printf``,``ESP_LOGE``
-#define ESP_EARLY_LOGE( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_ERROR,   E, ##__VA_ARGS__)
-/// macro to output logs in startup code at ``ESP_LOG_WARN`` level.  @see ``ESP_EARLY_LOGE``,``ESP_LOGE``, ``printf``
-#define ESP_EARLY_LOGW( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_WARN,    W, ##__VA_ARGS__)
-/// macro to output logs in startup code at ``ESP_LOG_INFO`` level.  @see ``ESP_EARLY_LOGE``,``ESP_LOGE``, ``printf``
-#define ESP_EARLY_LOGI( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_INFO,    I, ##__VA_ARGS__)
-/// macro to output logs in startup code at ``ESP_LOG_DEBUG`` level.  @see ``ESP_EARLY_LOGE``,``ESP_LOGE``, ``printf``
-#define ESP_EARLY_LOGD( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_DEBUG,   D, ##__VA_ARGS__)
-/// macro to output logs in startup code at ``ESP_LOG_VERBOSE`` level.  @see ``ESP_EARLY_LOGE``,``ESP_LOGE``, ``printf``
-#define ESP_EARLY_LOGV( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_VERBOSE, V, ##__VA_ARGS__)
-
-#define ESP_LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) do {                         \
-        if (LOG_LOCAL_LEVEL >= log_level) {                                                          \
-            ets_printf(LOG_FORMAT(log_tag_letter, format), esp_log_timestamp(), tag, ##__VA_ARGS__); \
-        }} while(0)
-
-#ifndef BOOTLOADER_BUILD
-#define ESP_LOGE( tag, format, ... ) ESP_LOG_LEVEL_LOCAL(ESP_LOG_ERROR,   tag, format, ##__VA_ARGS__)
-#define ESP_LOGW( tag, format, ... ) ESP_LOG_LEVEL_LOCAL(ESP_LOG_WARN,    tag, format, ##__VA_ARGS__)
-#define ESP_LOGI( tag, format, ... ) ESP_LOG_LEVEL_LOCAL(ESP_LOG_INFO,    tag, format, ##__VA_ARGS__)
-#define ESP_LOGD( tag, format, ... ) ESP_LOG_LEVEL_LOCAL(ESP_LOG_DEBUG,   tag, format, ##__VA_ARGS__)
-#define ESP_LOGV( tag, format, ... ) ESP_LOG_LEVEL_LOCAL(ESP_LOG_VERBOSE, tag, format, ##__VA_ARGS__)
-#else
-/**
- * macro to output logs at ESP_LOG_ERROR level.
- *
- * @param tag tag of the log, which can be used to change the log level by ``esp_log_level_set`` at runtime.
- *
- * @see ``printf``
- */
-#define ESP_LOGE( tag, format, ... )  ESP_EARLY_LOGE(tag, format, ##__VA_ARGS__)
-/// macro to output logs at ``ESP_LOG_WARN`` level.  @see ``ESP_LOGE``
-#define ESP_LOGW( tag, format, ... )  ESP_EARLY_LOGW(tag, format, ##__VA_ARGS__)
-/// macro to output logs at ``ESP_LOG_INFO`` level.  @see ``ESP_LOGE``
-#define ESP_LOGI( tag, format, ... )  ESP_EARLY_LOGI(tag, format, ##__VA_ARGS__)
-/// macro to output logs at ``ESP_LOG_DEBUG`` level.  @see ``ESP_LOGE``
-#define ESP_LOGD( tag, format, ... )  ESP_EARLY_LOGD(tag, format, ##__VA_ARGS__)
-/// macro to output logs at ``ESP_LOG_VERBOSE`` level.  @see ``ESP_LOGE``
-#define ESP_LOGV( tag, format, ... )  ESP_EARLY_LOGV(tag, format, ##__VA_ARGS__)
-#endif  // BOOTLOADER_BUILD
-
-/** runtime macro to output logs at a specified level.
- * 
- * @param tag tag of the log, which can be used to change the log level by ``esp_log_level_set`` at runtime.
- * @param level level of the output log.
- * @param format format of the output log. see ``printf``
- * @param ... variables to be replaced into the log. see ``printf``
- *
- * @see ``printf``
- */
-#define ESP_LOG_LEVEL(level, tag, format, ...) do {                     \
-        if (level==ESP_LOG_ERROR )          { esp_log_write(ESP_LOG_ERROR,      tag, LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } \
-        else if (level==ESP_LOG_WARN )      { esp_log_write(ESP_LOG_WARN,       tag, LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } \
-        else if (level==ESP_LOG_DEBUG )     { esp_log_write(ESP_LOG_DEBUG,      tag, LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } \
-        else if (level==ESP_LOG_VERBOSE )   { esp_log_write(ESP_LOG_VERBOSE,    tag, LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } \
-        else                                { esp_log_write(ESP_LOG_INFO,       tag, LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } \
-    } while(0)
-
-/** runtime macro to output logs at a specified level. Also check the level with ``LOG_LOCAL_LEVEL``.
- *
- * @see ``printf``, ``ESP_LOG_LEVEL``
- */
-#define ESP_LOG_LEVEL_LOCAL(level, tag, format, ...) do {               \
-        if ( LOG_LOCAL_LEVEL >= level ) ESP_LOG_LEVEL(level, tag, format, ##__VA_ARGS__); \
-    } while(0)
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __ESP_LOG_H__ */
diff --git a/tools/sdk/include/log/esp_log_internal.h b/tools/sdk/include/log/esp_log_internal.h
deleted file mode 100644
index 94ec3463227..00000000000
--- a/tools/sdk/include/log/esp_log_internal.h
+++ /dev/null
@@ -1,24 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_LOG_INTERNAL_H__
-#define __ESP_LOG_INTERNAL_H__
-
-//these functions do not check level versus ESP_LOCAL_LEVEL, this should be done in esp_log.h
-void esp_log_buffer_hex_internal(const char *tag, const void *buffer, uint16_t buff_len, esp_log_level_t level);
-void esp_log_buffer_char_internal(const char *tag, const void *buffer, uint16_t buff_len, esp_log_level_t level);
-void esp_log_buffer_hexdump_internal( const char *tag, const void *buffer, uint16_t buff_len, esp_log_level_t log_level);
-
-#endif
-
diff --git a/tools/sdk/include/lwip/apps/sntp/sntp.h b/tools/sdk/include/lwip/apps/sntp/sntp.h
deleted file mode 100644
index 7758cfa7d7b..00000000000
--- a/tools/sdk/include/lwip/apps/sntp/sntp.h
+++ /dev/null
@@ -1,3 +0,0 @@
-#pragma once
-#warning "This header file is deprecated, please include esp_sntp.h instead."
-#include "esp_sntp.h"
diff --git a/tools/sdk/include/lwip/arch/cc.h b/tools/sdk/include/lwip/arch/cc.h
deleted file mode 100644
index b3ff59bc4f4..00000000000
--- a/tools/sdk/include/lwip/arch/cc.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef __ARCH_CC_H__
-#define __ARCH_CC_H__
-
-#include <stdint.h>
-#include <errno.h>
-#include <assert.h>
-#include <stdio.h>
-
-#include "arch/sys_arch.h"
-
-#define BYTE_ORDER LITTLE_ENDIAN
-
-#ifndef CONFIG_LWIP_ESP_LWIP_ASSERT
-#define LWIP_NOASSERT 1
-#endif
-
-typedef uint8_t  u8_t;
-typedef int8_t   s8_t;
-typedef uint16_t u16_t;
-typedef int16_t  s16_t;
-typedef uint32_t u32_t;
-typedef int32_t  s32_t;
-
-typedef unsigned long   mem_ptr_t;
-typedef int sys_prot_t;
-
-#define S16_F "d"
-#define U16_F "d"
-#define X16_F "x"
-
-#define S32_F "d"
-#define U32_F "d"
-#define X32_F "x"
-
-#define PACK_STRUCT_FIELD(x) x
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-#define PACK_STRUCT_BEGIN
-#define PACK_STRUCT_END
-
-#include <stdio.h>
-
-#define LWIP_PLATFORM_DIAG(x)   do {printf x;} while(0)
-// __assert_func is the assertion failure handler from newlib, defined in assert.h
-#define LWIP_PLATFORM_ASSERT(message) __assert_func(__FILE__, __LINE__, __ASSERT_FUNC, message)
-
-#ifdef NDEBUG
-#define LWIP_NOASSERT
-#else // Assertions enabled
-
-// If assertions are on, the default LWIP_ERROR handler behaviour is to
-// abort w/ an assertion failure. Don't do this, instead just print the error (if LWIP_DEBUG is set)
-// and run the handler (same as the LWIP_ERROR behaviour if LWIP_NOASSERT is set).
-#ifdef LWIP_DEBUG
-#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
-  puts(message); handler;}} while(0)
-#else
-// If LWIP_DEBUG is not set, return the error silently (default LWIP behaviour, also.)
-#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
-  handler;}} while(0)
-#endif // LWIP_DEBUG
-
-#endif /* NDEBUG */
-
-
-#endif /* __ARCH_CC_H__ */
diff --git a/tools/sdk/include/lwip/arch/perf.h b/tools/sdk/include/lwip/arch/perf.h
deleted file mode 100644
index 089facac1df..00000000000
--- a/tools/sdk/include/lwip/arch/perf.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef __PERF_H__
-#define __PERF_H__
-
-#define PERF_START    /* null definition */
-#define PERF_STOP(x)  /* null definition */
-
-#endif /* __PERF_H__ */
diff --git a/tools/sdk/include/lwip/arch/sys_arch.h b/tools/sdk/include/lwip/arch/sys_arch.h
deleted file mode 100644
index 9638fdfd621..00000000000
--- a/tools/sdk/include/lwip/arch/sys_arch.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
- 
-#ifndef __SYS_ARCH_H__
-#define __SYS_ARCH_H__
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/queue.h"
-#include "freertos/semphr.h"
-#include "arch/vfs_lwip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-typedef xSemaphoreHandle sys_sem_t;
-typedef xSemaphoreHandle sys_mutex_t;
-typedef xTaskHandle sys_thread_t;
-
-typedef struct sys_mbox_s {
-  xQueueHandle os_mbox;
-  void *owner;
-}* sys_mbox_t;
-
-
-#define LWIP_COMPAT_MUTEX 0
-
-#if !LWIP_COMPAT_MUTEX
-#define sys_mutex_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
-#define sys_mutex_set_invalid( x ) ( ( *x ) = NULL )
-#endif
-
-#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
-
-/* Define the sys_mbox_set_invalid() to empty to support lock-free mbox in ESP LWIP.
- * 
- * The basic idea about the lock-free mbox is that the mbox should always be valid unless
- * no socket APIs are using the socket and the socket is closed. ESP LWIP achieves this by
- * following two changes to official LWIP:
- * 1. Postpone the deallocation of mbox to netconn_free(), in other words, free the mbox when
- *    no one is using the socket.
- * 2. Define the sys_mbox_set_invalid() to empty if the mbox is not actually freed.
-
- * The second change is necessary. Consider a common scenario: the application task calls 
- * recv() to receive packets from the socket, the sys_mbox_valid() returns true. Because there
- * is no lock for the mbox, the LWIP CORE can call sys_mbox_set_invalid() to set the mbox at 
- * anytime and the thread-safe issue may happen.
- *
- * However, if the sys_mbox_set_invalid() is not called after sys_mbox_free(), e.g. in netconn_alloc(),
- * we need to initialize the mbox to invalid explicitly since sys_mbox_set_invalid() now is empty.
- */
-#define sys_mbox_set_invalid( x ) 
-
-#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
-#define sys_sem_set_invalid( x ) ( ( *x ) = NULL )
-
-void sys_delay_ms(uint32_t ms);
-sys_sem_t* sys_thread_sem_init(void);
-void sys_thread_sem_deinit(void);
-sys_sem_t* sys_thread_sem_get(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYS_ARCH_H__ */
-
diff --git a/tools/sdk/include/lwip/arch/vfs_lwip.h b/tools/sdk/include/lwip/arch/vfs_lwip.h
deleted file mode 100644
index 1957304b9f2..00000000000
--- a/tools/sdk/include/lwip/arch/vfs_lwip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void esp_vfs_lwip_sockets_register();
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/lwip/arpa/inet.h b/tools/sdk/include/lwip/arpa/inet.h
deleted file mode 100644
index 90428f687d7..00000000000
--- a/tools/sdk/include/lwip/arpa/inet.h
+++ /dev/null
@@ -1,20 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef INET_H_
-#define INET_H_
-
-#include "../../../lwip/src/include/lwip/inet.h"
-
-#endif /* INET_H_ */
diff --git a/tools/sdk/include/lwip/cc.h b/tools/sdk/include/lwip/cc.h
deleted file mode 100644
index b3ff59bc4f4..00000000000
--- a/tools/sdk/include/lwip/cc.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef __ARCH_CC_H__
-#define __ARCH_CC_H__
-
-#include <stdint.h>
-#include <errno.h>
-#include <assert.h>
-#include <stdio.h>
-
-#include "arch/sys_arch.h"
-
-#define BYTE_ORDER LITTLE_ENDIAN
-
-#ifndef CONFIG_LWIP_ESP_LWIP_ASSERT
-#define LWIP_NOASSERT 1
-#endif
-
-typedef uint8_t  u8_t;
-typedef int8_t   s8_t;
-typedef uint16_t u16_t;
-typedef int16_t  s16_t;
-typedef uint32_t u32_t;
-typedef int32_t  s32_t;
-
-typedef unsigned long   mem_ptr_t;
-typedef int sys_prot_t;
-
-#define S16_F "d"
-#define U16_F "d"
-#define X16_F "x"
-
-#define S32_F "d"
-#define U32_F "d"
-#define X32_F "x"
-
-#define PACK_STRUCT_FIELD(x) x
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-#define PACK_STRUCT_BEGIN
-#define PACK_STRUCT_END
-
-#include <stdio.h>
-
-#define LWIP_PLATFORM_DIAG(x)   do {printf x;} while(0)
-// __assert_func is the assertion failure handler from newlib, defined in assert.h
-#define LWIP_PLATFORM_ASSERT(message) __assert_func(__FILE__, __LINE__, __ASSERT_FUNC, message)
-
-#ifdef NDEBUG
-#define LWIP_NOASSERT
-#else // Assertions enabled
-
-// If assertions are on, the default LWIP_ERROR handler behaviour is to
-// abort w/ an assertion failure. Don't do this, instead just print the error (if LWIP_DEBUG is set)
-// and run the handler (same as the LWIP_ERROR behaviour if LWIP_NOASSERT is set).
-#ifdef LWIP_DEBUG
-#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
-  puts(message); handler;}} while(0)
-#else
-// If LWIP_DEBUG is not set, return the error silently (default LWIP behaviour, also.)
-#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
-  handler;}} while(0)
-#endif // LWIP_DEBUG
-
-#endif /* NDEBUG */
-
-
-#endif /* __ARCH_CC_H__ */
diff --git a/tools/sdk/include/lwip/debug/lwip_debug.h b/tools/sdk/include/lwip/debug/lwip_debug.h
deleted file mode 100644
index 4da520269ae..00000000000
--- a/tools/sdk/include/lwip/debug/lwip_debug.h
+++ /dev/null
@@ -1,25 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef _LWIP_DEBUG_H
-#define _LWIP_DEBUG_H
-
-void dbg_lwip_tcp_pcb_show(void);
-void dbg_lwip_udp_pcb_show(void);
-void dbg_lwip_tcp_rxtx_show(void);
-void dbg_lwip_udp_rxtx_show(void);
-void dbg_lwip_mem_cnt_show(void);
-
-#endif
diff --git a/tools/sdk/include/lwip/dhcpserver/dhcpserver.h b/tools/sdk/include/lwip/dhcpserver/dhcpserver.h
deleted file mode 100644
index a6ad51d9957..00000000000
--- a/tools/sdk/include/lwip/dhcpserver/dhcpserver.h
+++ /dev/null
@@ -1,95 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __DHCPS_H__
-#define __DHCPS_H__
-
-#include "sdkconfig.h"
-#include "lwip/ip_addr.h"
-
-typedef struct dhcps_state{
-        s16_t state;
-} dhcps_state;
-
-typedef struct dhcps_msg {
-        u8_t op, htype, hlen, hops;
-        u8_t xid[4];
-        u16_t secs, flags;
-        u8_t ciaddr[4];
-        u8_t yiaddr[4];
-        u8_t siaddr[4];
-        u8_t giaddr[4];
-        u8_t chaddr[16];
-        u8_t sname[64];
-        u8_t file[128];
-        u8_t options[312];
-}dhcps_msg;
-
-/*   Defined in esp_misc.h */
-typedef struct {
-	bool enable;
-	ip4_addr_t start_ip;
-	ip4_addr_t end_ip;
-} dhcps_lease_t;
-
-enum dhcps_offer_option{
-	OFFER_START = 0x00,
-	OFFER_ROUTER = 0x01,
-	OFFER_DNS = 0x02,
-	OFFER_END
-};
-
-#define DHCPS_COARSE_TIMER_SECS  1
-#define DHCPS_MAX_LEASE 0x64
-#define DHCPS_LEASE_TIME_DEF (120)
-#define DHCPS_LEASE_UNIT CONFIG_LWIP_DHCPS_LEASE_UNIT
-
-struct dhcps_pool{
-	ip4_addr_t ip;
-	u8_t mac[6];
-	u32_t lease_timer;
-};
-
-typedef u32_t dhcps_time_t;
-typedef u8_t dhcps_offer_t;
-
-typedef struct {
-        dhcps_offer_t dhcps_offer;
-        dhcps_offer_t dhcps_dns;
-        dhcps_time_t  dhcps_time;
-        dhcps_lease_t dhcps_poll;
-} dhcps_options_t;
-
-typedef void (*dhcps_cb_t)(u8_t client_ip[4]);
-
-static inline bool dhcps_router_enabled (dhcps_offer_t offer) 
-{
-    return (offer & OFFER_ROUTER) != 0;
-}
-
-static inline bool dhcps_dns_enabled (dhcps_offer_t offer) 
-{
-    return (offer & OFFER_DNS) != 0;
-}
-
-void dhcps_start(struct netif *netif, ip4_addr_t ip);
-void dhcps_stop(struct netif *netif);
-void *dhcps_option_info(u8_t op_id, u32_t opt_len);
-void dhcps_set_option_info(u8_t op_id, void *opt_info, u32_t opt_len);
-bool dhcp_search_ip_on_mac(u8_t *mac, ip4_addr_t *ip);
-void dhcps_dns_setserver(const ip_addr_t *dnsserver);
-ip4_addr_t dhcps_dns_getserver();
-void dhcps_set_new_lease_cb(dhcps_cb_t cb);
-
-#endif
-
diff --git a/tools/sdk/include/lwip/dhcpserver/dhcpserver_options.h b/tools/sdk/include/lwip/dhcpserver/dhcpserver_options.h
deleted file mode 100644
index 38d46f6bff2..00000000000
--- a/tools/sdk/include/lwip/dhcpserver/dhcpserver_options.h
+++ /dev/null
@@ -1,134 +0,0 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-/** DHCP Options
-
-    This macros are not part of the public dhcpserver.h interface.
- **/
-typedef enum
-{
-    /* RFC 1497 Vendor Extensions */
-
-    PAD = 0,
-    END = 255,
-
-    SUBNET_MASK = 1,
-    TIME_OFFSET = 2,
-    ROUTER = 3,
-    TIME_SERVER = 4,
-    NAME_SERVER = 5,
-    DOMAIN_NAME_SERVER = 6,
-    LOG_SERVER = 7,
-    COOKIE_SERVER = 8,
-    LPR_SERVER = 9,
-    IMPRESS_SERVER = 10,
-    RESOURCE_LOCATION_SERVER = 11,
-    HOST_NAME = 12,
-    BOOT_FILE_SIZE = 13,
-    MERIT_DUMP_FILE = 14,
-    DOMAIN_NAME = 15,
-    SWAP_SERVER = 16,
-    ROOT_PATH = 17,
-    EXTENSIONS_PATH = 18,
-
-    /* IP Layer Parameters per Host */
-
-    IP_FORWARDING = 19,
-    NON_LOCAL_SOURCE_ROUTING = 20,
-    POLICY_FILTER = 21,
-    MAXIMUM_DATAGRAM_REASSEMBLY_SIZE = 22,
-    DEFAULT_IP_TIME_TO_LIVE = 23,
-    PATH_MTU_AGING_TIMEOUT = 24,
-    PATH_MTU_PLATEAU_TABLE = 25,
-
-    /* IP Layer Parameters per Interface */
-
-    INTERFACE_MTU = 26,
-    ALL_SUBNETS_ARE_LOCAL = 27,
-    BROADCAST_ADDRESS = 28,
-    PERFORM_MASK_DISCOVERY = 29,
-    MASK_SUPPLIER = 30,
-    PERFORM_ROUTER_DISCOVERY = 31,
-    ROUTER_SOLICITATION_ADDRESS = 32,
-    STATIC_ROUTE = 33,
-
-    /* Link Layer Parameters per Interface */
-
-    TRAILER_ENCAPSULATION = 34,
-    ARP_CACHE_TIMEOUT = 35,
-    ETHERNET_ENCAPSULATION = 36,
-
-    /* TCP Parameters */
-
-    TCP_DEFAULT_TTL = 37,
-    TCP_KEEPALIVE_INTERVAL = 38,
-    TCP_KEEPALIVE_GARBAGE = 39,
-
-    /* Application and Service Parameters */
-
-    NETWORK_INFORMATION_SERVICE_DOMAIN = 40,
-    NETWORK_INFORMATION_SERVERS = 41,
-    NETWORK_TIME_PROTOCOL_SERVERS = 42,
-    VENDOR_SPECIFIC_INFORMATION = 43,
-    NETBIOS_OVER_TCP_IP_NAME_SERVER = 44,
-    NETBIOS_OVER_TCP_IP_DATAGRAM_DISTRIBUTION_SERVER = 45,
-    NETBIOS_OVER_TCP_IP_NODE_TYPE = 46,
-    NETBIOS_OVER_TCP_IP_SCOPE = 47,
-    X_WINDOW_SYSTEM_FONT_SERVER = 48,
-    X_WINDOW_SYSTEM_DISPLAY_MANAGER = 49,
-    NETWORK_INFORMATION_SERVICE_PLUS_DOMAIN = 64,
-    NETWORK_INFORMATION_SERVICE_PLUS_SERVERS = 65,
-    MOBILE_IP_HOME_AGENT = 68,
-    SMTP_SERVER = 69,
-    POP3_SERVER = 70,
-    NNTP_SERVER = 71,
-    DEFAULT_WWW_SERVER = 72,
-    DEFAULT_FINGER_SERVER = 73,
-    DEFAULT_IRC_SERVER = 74,
-    STREETTALK_SERVER = 75,
-    STREETTALK_DIRECTORY_ASSISTANCE_SERVER = 76,
-
-    /* DHCP Extensions */
-
-    REQUESTED_IP_ADDRESS = 50,
-    IP_ADDRESS_LEASE_TIME = 51,
-    OPTION_OVERLOAD = 52,
-    TFTP_SERVER_NAME = 66,
-    BOOTFILE_NAME = 67,
-    DHCP_MESSAGE_TYPE = 53,
-    SERVER_IDENTIFIER = 54,
-    PARAMETER_REQUEST_LIST = 55,
-    MESSAGE = 56,
-    MAXIMUM_DHCP_MESSAGE_SIZE = 57,
-    RENEWAL_T1_TIME_VALUE = 58,
-    REBINDING_T2_TIME_VALUE = 59,
-    VENDOR_CLASS_IDENTIFIER = 60,
-    CLIENT_IDENTIFIER = 61,
-
-    USER_CLASS = 77,
-    FQDN = 81,
-    DHCP_AGENT_OPTIONS = 82,
-    NDS_SERVERS = 85,
-    NDS_TREE_NAME = 86,
-    NDS_CONTEXT = 87,
-    CLIENT_LAST_TRANSACTION_TIME = 91,
-    ASSOCIATED_IP = 92,
-    USER_AUTHENTICATION_PROTOCOL = 98,
-    AUTO_CONFIGURE = 116,
-    NAME_SERVICE_SEARCH = 117,
-    SUBNET_SELECTION = 118,
-    DOMAIN_SEARCH = 119,
-    CLASSLESS_ROUTE = 121,
-} dhcp_msg_option;
diff --git a/tools/sdk/include/lwip/esp_ping.h b/tools/sdk/include/lwip/esp_ping.h
deleted file mode 100644
index 9abb883c233..00000000000
--- a/tools/sdk/include/lwip/esp_ping.h
+++ /dev/null
@@ -1,111 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef ESP_PING_H_
-#define ESP_PING_H_
-
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// gen_esp_err_to_name.py: include this as "esp_ping.h" because "components/lwip/include/apps/" is in the compiler path
-// and not "components/lwip/include"
-
-#define ESP_ERR_PING_BASE               0x6000
-
-#define ESP_ERR_PING_INVALID_PARAMS     ESP_ERR_PING_BASE + 0x01
-#define ESP_ERR_PING_NO_MEM             ESP_ERR_PING_BASE + 0x02
-
-#define ESP_PING_CHECK_OPTLEN(optlen, opttype) do { if ((optlen) < sizeof(opttype)) { return ESP_ERR_PING_INVALID_PARAMS; }}while(0)
-
-typedef struct _ping_found {
-    uint32_t resp_time;
-    uint32_t timeout_count;
-    uint32_t send_count;
-    uint32_t recv_count;
-    uint32_t err_count;
-    uint32_t bytes;
-    uint32_t total_bytes;
-    uint32_t total_time;
-    uint32_t min_time;
-    uint32_t max_time;
-    int8_t  ping_err;
-} esp_ping_found;
-
-typedef enum {
-    PING_TARGET_IP_ADDRESS          = 50,   /**< target IP address */
-    PING_TARGET_IP_ADDRESS_COUNT    = 51,   /**< target IP address total counter */
-    PING_TARGET_RCV_TIMEO           = 52,   /**< receive timeout in milliseconds */
-    PING_TARGET_DELAY_TIME          = 53,   /**< delay time in milliseconds */
-    PING_TARGET_ID                  = 54,   /**< identifier */
-    PING_TARGET_RES_FN              = 55,   /**< ping result callback function */
-    PING_TARGET_RES_RESET           = 56,   /**< ping result statistic reset */
-    PING_TARGET_DATA_LEN            = 57,   /**< ping data length*/
-    PING_TARGET_IP_TOS              = 58    /**< ping QOS*/
-} ping_target_id_t;
-
-typedef enum {
-    PING_RES_TIMEOUT = 0,
-    PING_RES_OK      = 1, 
-    PING_RES_FINISH  = 2,
-} ping_res_t;
-
-typedef void (* esp_ping_found_fn)(ping_target_id_t found_id, esp_ping_found *found_val);
-
-/**
- * @brief  Set PING function option
- *
- * @param[in]  opt_id: option index, 50 for IP, 51 for COUNT, 52 for RCV TIMEOUT, 53 for DELAY TIME, 54 for ID
- * @param[in]  opt_val: option parameter
- * @param[in]  opt_len: option length
- *
- * @return
- *      - ESP_OK
- *      - ESP_ERR_PING_INVALID_PARAMS
- */
-esp_err_t esp_ping_set_target(ping_target_id_t opt_id, void *opt_val, uint32_t opt_len);
-
-/**
- * @brief  Get PING function option
- *
- * @param[in]  opt_id: option index, 50 for IP, 51 for COUNT, 52 for RCV TIMEOUT, 53 for DELAY TIME, 54 for ID
- * @param[in]  opt_val: option parameter
- * @param[in]  opt_len: option length
- *
- * @return
- *      - ESP_OK
- *      - ESP_ERR_PING_INVALID_PARAMS
- */
-esp_err_t esp_ping_get_target(ping_target_id_t opt_id, void *opt_val, uint32_t opt_len);
-
-/**
- * @brief  Get PING function result action
- *
- * @param[in]  res_val: ping function action, 1 for successful, 0 for fail.
- *             res_len: response bytes
- *             res_time: response time
- *
- * @return
- *      - ESP_OK
- *      - ESP_ERR_PING_INVALID_PARAMS
- */
-esp_err_t esp_ping_result(uint8_t res_val, uint16_t res_len, uint32_t res_time);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ESP_PING_H_ */
diff --git a/tools/sdk/include/lwip/esp_sntp.h b/tools/sdk/include/lwip/esp_sntp.h
deleted file mode 100644
index 020f0cf36a9..00000000000
--- a/tools/sdk/include/lwip/esp_sntp.h
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_SNTP_H__
-#define __ESP_SNTP_H__
-
-#include "lwip/err.h"
-#include "lwip/apps/sntp.h"
-#include "sntp.h"
-
-#endif // __ESP_SNTP_H__
diff --git a/tools/sdk/include/lwip/lwip/api.h b/tools/sdk/include/lwip/lwip/api.h
deleted file mode 100644
index a4fed9bbfbf..00000000000
--- a/tools/sdk/include/lwip/lwip/api.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/**
- * @file
- * netconn API (to be used from non-TCPIP threads)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_API_H
-#define LWIP_HDR_API_H
-
-#include "lwip/opt.h"
-
-#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
-/* Note: Netconn API is always available when sockets are enabled -
- * sockets are implemented on top of them */
-
-#include "lwip/arch.h"
-#include "lwip/netbuf.h"
-#include "lwip/sys.h"
-#include "lwip/ip_addr.h"
-#include "lwip/err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Throughout this file, IP addresses and port numbers are expected to be in
- * the same byte order as in the corresponding pcb.
- */
-
-/* Flags for netconn_write (u8_t) */
-#define NETCONN_NOFLAG    0x00
-#define NETCONN_NOCOPY    0x00 /* Only for source code compatibility */
-#define NETCONN_COPY      0x01
-#define NETCONN_MORE      0x02
-#define NETCONN_DONTBLOCK 0x04
-
-/* Flags for struct netconn.flags (u8_t) */
-/** Should this netconn avoid blocking? */
-#define NETCONN_FLAG_NON_BLOCKING             0x02
-/** Was the last connect action a non-blocking one? */
-#define NETCONN_FLAG_IN_NONBLOCKING_CONNECT   0x04
-#if ESP_AUTO_RECV
-/** If this is set, a TCP netconn must call netconn_recved() to update
-    the TCP receive window (done automatically if not set). */
-#define NETCONN_FLAG_NO_AUTO_RECVED           0x08
-#endif
-/** If a nonblocking write has been rejected before, poll_tcp needs to
-    check if the netconn is writable again */
-#define NETCONN_FLAG_CHECK_WRITESPACE         0x10
-#if LWIP_IPV6
-/** If this flag is set then only IPv6 communication is allowed on the
-    netconn. As per RFC#3493 this features defaults to OFF allowing
-    dual-stack usage by default. */
-#define NETCONN_FLAG_IPV6_V6ONLY              0x20
-#endif /* LWIP_IPV6 */
-
-
-/* Helpers to process several netconn_types by the same code */
-#define NETCONNTYPE_GROUP(t)         ((t)&0xF0)
-#define NETCONNTYPE_DATAGRAM(t)      ((t)&0xE0)
-#if LWIP_IPV6
-#define NETCONN_TYPE_IPV6            0x08
-#define NETCONNTYPE_ISIPV6(t)        (((t)&NETCONN_TYPE_IPV6) != 0)
-#define NETCONNTYPE_ISUDPLITE(t)     (((t)&0xF3) == NETCONN_UDPLITE)
-#define NETCONNTYPE_ISUDPNOCHKSUM(t) (((t)&0xF3) == NETCONN_UDPNOCHKSUM)
-#else /* LWIP_IPV6 */
-#define NETCONNTYPE_ISIPV6(t)        (0)
-#define NETCONNTYPE_ISUDPLITE(t)     ((t) == NETCONN_UDPLITE)
-#define NETCONNTYPE_ISUDPNOCHKSUM(t) ((t) == NETCONN_UDPNOCHKSUM)
-#endif /* LWIP_IPV6 */
-
-/** @ingroup netconn_common
- * Protocol family and type of the netconn
- */
-enum netconn_type {
-  NETCONN_INVALID     = 0,
-  /** TCP IPv4 */
-  NETCONN_TCP         = 0x10,
-#if LWIP_IPV6
-  /** TCP IPv6 */
-  NETCONN_TCP_IPV6    = NETCONN_TCP | NETCONN_TYPE_IPV6 /* 0x18 */,
-#endif /* LWIP_IPV6 */
-  /** UDP IPv4 */
-  NETCONN_UDP         = 0x20,
-  /** UDP IPv4 lite */
-  NETCONN_UDPLITE     = 0x21,
-  /** UDP IPv4 no checksum */
-  NETCONN_UDPNOCHKSUM = 0x22,
-
-#if LWIP_IPV6
-  /** UDP IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
-  NETCONN_UDP_IPV6         = NETCONN_UDP | NETCONN_TYPE_IPV6 /* 0x28 */,
-  /** UDP IPv6 lite (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
-  NETCONN_UDPLITE_IPV6     = NETCONN_UDPLITE | NETCONN_TYPE_IPV6 /* 0x29 */,
-  /** UDP IPv6 no checksum (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
-  NETCONN_UDPNOCHKSUM_IPV6 = NETCONN_UDPNOCHKSUM | NETCONN_TYPE_IPV6 /* 0x2a */,
-#endif /* LWIP_IPV6 */
-
-  /** Raw connection IPv4 */
-  NETCONN_RAW         = 0x40
-#if LWIP_IPV6
-  /** Raw connection IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */
-  , NETCONN_RAW_IPV6    = NETCONN_RAW | NETCONN_TYPE_IPV6 /* 0x48 */
-#endif /* LWIP_IPV6 */
-};
-
-/** Current state of the netconn. Non-TCP netconns are always
- * in state NETCONN_NONE! */
-enum netconn_state {
-  NETCONN_NONE,
-  NETCONN_WRITE,
-  NETCONN_LISTEN,
-  NETCONN_CONNECT,
-  NETCONN_CLOSE
-};
-
-/** Used to inform the callback function about changes
- * 
- * Event explanation:
- * 
- * In the netconn implementation, there are three ways to block a client:
- * 
- * - accept mbox (sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, 0); in netconn_accept())
- * - receive mbox (sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0); in netconn_recv_data())
- * - send queue is full (sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); in lwip_netconn_do_write())
- * 
- * The events have to be seen as events signaling the state of these mboxes/semaphores. For non-blocking
- * connections, you need to know in advance whether a call to a netconn function call would block or not,
- * and these events tell you about that.
- * 
- * RCVPLUS events say: Safe to perform a potentially blocking call call once more. 
- * They are counted in sockets - three RCVPLUS events for accept mbox means you are safe
- * to call netconn_accept 3 times without being blocked.
- * Same thing for receive mbox.
- * 
- * RCVMINUS events say: Your call to to a possibly blocking function is "acknowledged".
- * Socket implementation decrements the counter.
- * 
- * For TX, there is no need to count, its merely a flag. SENDPLUS means you may send something.
- * SENDPLUS occurs when enough data was delivered to peer so netconn_send() can be called again.
- * A SENDMINUS event occurs when the next call to a netconn_send() would be blocking.
- */
-enum netconn_evt {
-  NETCONN_EVT_RCVPLUS,
-  NETCONN_EVT_RCVMINUS,
-  NETCONN_EVT_SENDPLUS,
-  NETCONN_EVT_SENDMINUS,
-  NETCONN_EVT_ERROR
-};
-
-#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
-/** Used for netconn_join_leave_group() */
-enum netconn_igmp {
-  NETCONN_JOIN,
-  NETCONN_LEAVE
-};
-#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
-
-#if LWIP_DNS
-/* Used for netconn_gethostbyname_addrtype(), these should match the DNS_ADDRTYPE defines in dns.h */
-#define NETCONN_DNS_DEFAULT   NETCONN_DNS_IPV4_IPV6
-#define NETCONN_DNS_IPV4      0
-#define NETCONN_DNS_IPV6      1
-#define NETCONN_DNS_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */
-#define NETCONN_DNS_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */
-#endif /* LWIP_DNS */
-
-/* forward-declare some structs to avoid to include their headers */
-struct ip_pcb;
-struct tcp_pcb;
-struct udp_pcb;
-struct raw_pcb;
-struct netconn;
-struct api_msg;
-
-/** A callback prototype to inform about events for a netconn */
-typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len);
-
-/** A netconn descriptor */
-struct netconn {
-  /** type of the netconn (TCP, UDP or RAW) */
-  enum netconn_type type;
-  /** current state of the netconn */
-  enum netconn_state state;
-  /** the lwIP internal protocol control block */
-  union {
-    struct ip_pcb  *ip;
-    struct tcp_pcb *tcp;
-    struct udp_pcb *udp;
-    struct raw_pcb *raw;
-  } pcb;
-  /** the last error this netconn had */
-  err_t last_err;
-#if !LWIP_NETCONN_SEM_PER_THREAD
-  /** sem that is used to synchronously execute functions in the core context */
-  sys_sem_t op_completed;
-#endif
-  /** mbox where received packets are stored until they are fetched
-      by the netconn application thread (can grow quite big) */
-  sys_mbox_t recvmbox;
-#if LWIP_TCP
-  /** mbox where new connections are stored until processed
-      by the application thread */
-  sys_mbox_t acceptmbox;
-#endif /* LWIP_TCP */
-  /** only used for socket layer */
-#if LWIP_SOCKET
-  int socket;
-#endif /* LWIP_SOCKET */
-#if LWIP_SO_SNDTIMEO
-  /** timeout to wait for sending data (which means enqueueing data for sending
-      in internal buffers) in milliseconds */
-  s32_t send_timeout;
-#endif /* LWIP_SO_RCVTIMEO */
-#if LWIP_SO_RCVTIMEO
-  /** timeout in milliseconds to wait for new data to be received
-      (or connections to arrive for listening netconns) */
-  int recv_timeout;
-#endif /* LWIP_SO_RCVTIMEO */
-#if LWIP_SO_RCVBUF
-  /** maximum amount of bytes queued in recvmbox
-      not used for TCP: adjust TCP_WND instead! */
-  int recv_bufsize;
-  /** number of bytes currently in recvmbox to be received,
-      tested against recv_bufsize to limit bytes on recvmbox
-      for UDP and RAW, used for FIONREAD */
-  int recv_avail;
-#endif /* LWIP_SO_RCVBUF */
-#if LWIP_SO_LINGER
-   /** values <0 mean linger is disabled, values > 0 are seconds to linger */
-  s16_t linger;
-#endif /* LWIP_SO_LINGER */
-  /** flags holding more netconn-internal state, see NETCONN_FLAG_* defines */
-  u8_t flags;
-#if LWIP_TCP
-  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
-      this temporarily stores how much is already sent. */
-  size_t write_offset;
-  /** TCP: when data passed to netconn_write doesn't fit into the send buffer,
-      this temporarily stores the message.
-      Also used during connect and close. */
-  struct api_msg *current_msg;
-#endif /* LWIP_TCP */
-  /** A callback function that is informed about events for this netconn */
-  netconn_callback callback;
-};
-
-/** Register an Network connection event */
-#define API_EVENT(c,e,l) if (c->callback) {         \
-                           (*c->callback)(c, e, l); \
-                         }
-
-/** Set conn->last_err to err but don't overwrite fatal errors */
-#define NETCONN_SET_SAFE_ERR(conn, err) do { if ((conn) != NULL) { \
-  SYS_ARCH_DECL_PROTECT(netconn_set_safe_err_lev); \
-  SYS_ARCH_PROTECT(netconn_set_safe_err_lev); \
-  if (!ERR_IS_FATAL((conn)->last_err)) { \
-    (conn)->last_err = err; \
-  } \
-  SYS_ARCH_UNPROTECT(netconn_set_safe_err_lev); \
-}} while(0);
-
-/* Network connection functions: */
-
-/** @ingroup netconn_common
- * Create new netconn connection
- * @param t @ref netconn_type */
-#define netconn_new(t)                  netconn_new_with_proto_and_callback(t, 0, NULL)
-#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c)
-struct netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto,
-                                             netconn_callback callback);
-err_t   netconn_delete(struct netconn *conn);
-/** Get the type of a netconn (as enum netconn_type). */
-#define netconn_type(conn) (conn->type)
-
-err_t   netconn_getaddr(struct netconn *conn, ip_addr_t *addr,
-                        u16_t *port, u8_t local);
-/** @ingroup netconn_common */
-#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0)
-/** @ingroup netconn_common */
-#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1)
-
-err_t   netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port);
-err_t   netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port);
-err_t   netconn_disconnect (struct netconn *conn);
-err_t   netconn_listen_with_backlog(struct netconn *conn, u8_t backlog);
-/** @ingroup netconn_tcp */
-#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG)
-err_t   netconn_accept(struct netconn *conn, struct netconn **new_conn);
-err_t   netconn_recv(struct netconn *conn, struct netbuf **new_buf);
-err_t   netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf);
-#if ESP_AUTO_RECV
-void    netconn_recved(struct netconn *conn, u32_t length);
-#endif
-err_t   netconn_sendto(struct netconn *conn, struct netbuf *buf,
-                             const ip_addr_t *addr, u16_t port);
-err_t   netconn_send(struct netconn *conn, struct netbuf *buf);
-err_t   netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size,
-                             u8_t apiflags, size_t *bytes_written);
-/** @ingroup netconn_tcp */
-#define netconn_write(conn, dataptr, size, apiflags) \
-          netconn_write_partly(conn, dataptr, size, apiflags, NULL)
-err_t   netconn_close(struct netconn *conn);
-err_t   netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx);
-
-#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
-err_t   netconn_join_leave_group(struct netconn *conn, const ip_addr_t *multiaddr,
-                             const ip_addr_t *netif_addr, enum netconn_igmp join_or_leave);
-#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
-#if LWIP_DNS
-#if LWIP_IPV4 && LWIP_IPV6
-err_t   netconn_gethostbyname_addrtype(const char *name, ip_addr_t *addr, u8_t dns_addrtype);
-#define netconn_gethostbyname(name, addr) netconn_gethostbyname_addrtype(name, addr, NETCONN_DNS_DEFAULT)
-#else /* LWIP_IPV4 && LWIP_IPV6 */
-err_t   netconn_gethostbyname(const char *name, ip_addr_t *addr);
-#define netconn_gethostbyname_addrtype(name, addr, dns_addrtype) netconn_gethostbyname(name, addr)
-#endif /* LWIP_IPV4 && LWIP_IPV6 */
-#endif /* LWIP_DNS */
-
-#define netconn_err(conn)               ((conn)->last_err)
-#define netconn_recv_bufsize(conn)      ((conn)->recv_bufsize)
-
-/** Set the blocking status of netconn calls (@todo: write/send is missing) */
-#define netconn_set_nonblocking(conn, val)  do { if(val) { \
-  (conn)->flags |= NETCONN_FLAG_NON_BLOCKING; \
-} else { \
-  (conn)->flags &= ~ NETCONN_FLAG_NON_BLOCKING; }} while(0)
-/** Get the blocking status of netconn calls (@todo: write/send is missing) */
-#define netconn_is_nonblocking(conn)        (((conn)->flags & NETCONN_FLAG_NON_BLOCKING) != 0)
-
-#if ESP_AUTO_RECV
-/** TCP: Set the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */
-#define netconn_set_noautorecved(conn, val)  do { if(val) { \
-  (conn)->flags |= NETCONN_FLAG_NO_AUTO_RECVED; \
-} else { \
-  (conn)->flags &= ~ NETCONN_FLAG_NO_AUTO_RECVED; }} while(0)
-/** TCP: Get the no-auto-recved status of netconn calls (see NETCONN_FLAG_NO_AUTO_RECVED) */
-#define netconn_get_noautorecved(conn)        (((conn)->flags & NETCONN_FLAG_NO_AUTO_RECVED) != 0)
-#endif
-
-#if LWIP_IPV6
-/** @ingroup netconn_common
- * TCP: Set the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY)
- */
-#define netconn_set_ipv6only(conn, val)  do { if(val) { \
-  (conn)->flags |= NETCONN_FLAG_IPV6_V6ONLY; \
-} else { \
-  (conn)->flags &= ~ NETCONN_FLAG_IPV6_V6ONLY; }} while(0)
-/** @ingroup netconn_common
- * TCP: Get the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY)
- */
-#define netconn_get_ipv6only(conn)        (((conn)->flags & NETCONN_FLAG_IPV6_V6ONLY) != 0)
-#endif /* LWIP_IPV6 */
-
-#if LWIP_SO_SNDTIMEO
-/** Set the send timeout in milliseconds */
-#define netconn_set_sendtimeout(conn, timeout)      ((conn)->send_timeout = (timeout))
-/** Get the send timeout in milliseconds */
-#define netconn_get_sendtimeout(conn)               ((conn)->send_timeout)
-#endif /* LWIP_SO_SNDTIMEO */
-#if LWIP_SO_RCVTIMEO
-/** Set the receive timeout in milliseconds */
-#define netconn_set_recvtimeout(conn, timeout)      ((conn)->recv_timeout = (timeout))
-/** Get the receive timeout in milliseconds */
-#define netconn_get_recvtimeout(conn)               ((conn)->recv_timeout)
-#endif /* LWIP_SO_RCVTIMEO */
-#if LWIP_SO_RCVBUF
-/** Set the receive buffer in bytes */
-#define netconn_set_recvbufsize(conn, recvbufsize)  ((conn)->recv_bufsize = (recvbufsize))
-/** Get the receive buffer in bytes */
-#define netconn_get_recvbufsize(conn)               ((conn)->recv_bufsize)
-#endif /* LWIP_SO_RCVBUF*/
-
-#if LWIP_NETCONN_SEM_PER_THREAD
-void netconn_thread_init(void);
-void netconn_thread_cleanup(void);
-#else /* LWIP_NETCONN_SEM_PER_THREAD */
-#define netconn_thread_init()
-#define netconn_thread_cleanup()
-#endif /* LWIP_NETCONN_SEM_PER_THREAD */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_NETCONN || LWIP_SOCKET */
-
-#endif /* LWIP_HDR_API_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/fs.h b/tools/sdk/include/lwip/lwip/apps/fs.h
deleted file mode 100644
index bb176fa0107..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/fs.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_APPS_FS_H
-#define LWIP_HDR_APPS_FS_H
-
-#include "httpd_opts.h"
-#include "lwip/err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define FS_READ_EOF     -1
-#define FS_READ_DELAYED -2
-
-#if HTTPD_PRECALCULATED_CHECKSUM
-struct fsdata_chksum {
-  u32_t offset;
-  u16_t chksum;
-  u16_t len;
-};
-#endif /* HTTPD_PRECALCULATED_CHECKSUM */
-
-#define FS_FILE_FLAGS_HEADER_INCLUDED     0x01
-#define FS_FILE_FLAGS_HEADER_PERSISTENT   0x02
-
-struct fs_file {
-  const char *data;
-  int len;
-  int index;
-  void *pextension;
-#if HTTPD_PRECALCULATED_CHECKSUM
-  const struct fsdata_chksum *chksum;
-  u16_t chksum_count;
-#endif /* HTTPD_PRECALCULATED_CHECKSUM */
-  u8_t flags;
-#if LWIP_HTTPD_CUSTOM_FILES
-  u8_t is_custom_file;
-#endif /* LWIP_HTTPD_CUSTOM_FILES */
-#if LWIP_HTTPD_FILE_STATE
-  void *state;
-#endif /* LWIP_HTTPD_FILE_STATE */
-};
-
-#if LWIP_HTTPD_FS_ASYNC_READ
-typedef void (*fs_wait_cb)(void *arg);
-#endif /* LWIP_HTTPD_FS_ASYNC_READ */
-
-err_t fs_open(struct fs_file *file, const char *name);
-void fs_close(struct fs_file *file);
-#if LWIP_HTTPD_DYNAMIC_FILE_READ
-#if LWIP_HTTPD_FS_ASYNC_READ
-int fs_read_async(struct fs_file *file, char *buffer, int count, fs_wait_cb callback_fn, void *callback_arg);
-#else /* LWIP_HTTPD_FS_ASYNC_READ */
-int fs_read(struct fs_file *file, char *buffer, int count);
-#endif /* LWIP_HTTPD_FS_ASYNC_READ */
-#endif /* LWIP_HTTPD_DYNAMIC_FILE_READ */
-#if LWIP_HTTPD_FS_ASYNC_READ
-int fs_is_file_ready(struct fs_file *file, fs_wait_cb callback_fn, void *callback_arg);
-#endif /* LWIP_HTTPD_FS_ASYNC_READ */
-int fs_bytes_left(struct fs_file *file);
-
-#if LWIP_HTTPD_FILE_STATE
-/** This user-defined function is called when a file is opened. */
-void *fs_state_init(struct fs_file *file, const char *name);
-/** This user-defined function is called when a file is closed. */
-void fs_state_free(struct fs_file *file, void *state);
-#endif /* #if LWIP_HTTPD_FILE_STATE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_FS_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/httpd.h b/tools/sdk/include/lwip/lwip/apps/httpd.h
deleted file mode 100644
index 40f1811e574..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/httpd.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/**
- * @file
- * HTTP server
- */
-
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- * This version of the file has been modified by Texas Instruments to offer
- * simple server-side-include (SSI) and Common Gateway Interface (CGI)
- * capability.
- */
-
-#ifndef LWIP_HDR_APPS_HTTPD_H
-#define LWIP_HDR_APPS_HTTPD_H
-
-#include "httpd_opts.h"
-#include "lwip/err.h"
-#include "lwip/pbuf.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_HTTPD_CGI
-
-/*
- * Function pointer for a CGI script handler.
- *
- * This function is called each time the HTTPD server is asked for a file
- * whose name was previously registered as a CGI function using a call to
- * http_set_cgi_handler. The iIndex parameter provides the index of the
- * CGI within the ppcURLs array passed to http_set_cgi_handler. Parameters
- * pcParam and pcValue provide access to the parameters provided along with
- * the URI. iNumParams provides a count of the entries in the pcParam and
- * pcValue arrays. Each entry in the pcParam array contains the name of a
- * parameter with the corresponding entry in the pcValue array containing the
- * value for that parameter. Note that pcParam may contain multiple elements
- * with the same name if, for example, a multi-selection list control is used
- * in the form generating the data.
- *
- * The function should return a pointer to a character string which is the
- * path and filename of the response that is to be sent to the connected
- * browser, for example "/thanks.htm" or "/response/error.ssi".
- *
- * The maximum number of parameters that will be passed to this function via
- * iNumParams is defined by LWIP_HTTPD_MAX_CGI_PARAMETERS. Any parameters in the incoming
- * HTTP request above this number will be discarded.
- *
- * Requests intended for use by this CGI mechanism must be sent using the GET
- * method (which encodes all parameters within the URI rather than in a block
- * later in the request). Attempts to use the POST method will result in the
- * request being ignored.
- *
- */
-typedef const char *(*tCGIHandler)(int iIndex, int iNumParams, char *pcParam[],
-                             char *pcValue[]);
-
-/*
- * Structure defining the base filename (URL) of a CGI and the associated
- * function which is to be called when that URL is requested.
- */
-typedef struct
-{
-    const char *pcCGIName;
-    tCGIHandler pfnCGIHandler;
-} tCGI;
-
-void http_set_cgi_handlers(const tCGI *pCGIs, int iNumHandlers);
-
-#endif /* LWIP_HTTPD_CGI */
-
-#if LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI
-
-#if LWIP_HTTPD_CGI_SSI
-/** Define this generic CGI handler in your application.
- * It is called once for every URI with parameters.
- * The parameters can be stored to 
- */
-extern void httpd_cgi_handler(const char* uri, int iNumParams, char **pcParam, char **pcValue
-#if defined(LWIP_HTTPD_FILE_STATE) && LWIP_HTTPD_FILE_STATE
-                                     , void *connection_state
-#endif /* LWIP_HTTPD_FILE_STATE */
-                                     );
-#endif /* LWIP_HTTPD_CGI_SSI */
-
-#endif /* LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI */
-
-#if LWIP_HTTPD_SSI
-
-/*
- * Function pointer for the SSI tag handler callback.
- *
- * This function will be called each time the HTTPD server detects a tag of the
- * form <!--#name--> in a .shtml, .ssi or .shtm file where "name" appears as
- * one of the tags supplied to http_set_ssi_handler in the ppcTags array.  The
- * returned insert string, which will be appended after the the string
- * "<!--#name-->" in file sent back to the client,should be written to pointer
- * pcInsert.  iInsertLen contains the size of the buffer pointed to by
- * pcInsert.  The iIndex parameter provides the zero-based index of the tag as
- * found in the ppcTags array and identifies the tag that is to be processed.
- *
- * The handler returns the number of characters written to pcInsert excluding
- * any terminating NULL or a negative number to indicate a failure (tag not
- * recognized, for example).
- *
- * Note that the behavior of this SSI mechanism is somewhat different from the
- * "normal" SSI processing as found in, for example, the Apache web server.  In
- * this case, the inserted text is appended following the SSI tag rather than
- * replacing the tag entirely.  This allows for an implementation that does not
- * require significant additional buffering of output data yet which will still
- * offer usable SSI functionality.  One downside to this approach is when
- * attempting to use SSI within JavaScript.  The SSI tag is structured to
- * resemble an HTML comment but this syntax does not constitute a comment
- * within JavaScript and, hence, leaving the tag in place will result in
- * problems in these cases.  To work around this, any SSI tag which needs to
- * output JavaScript code must do so in an encapsulated way, sending the whole
- * HTML <script>...</script> section as a single include.
- */
-typedef u16_t (*tSSIHandler)(
-#if LWIP_HTTPD_SSI_RAW
-                             const char* ssi_tag_name,
-#else /* LWIP_HTTPD_SSI_RAW */
-                             int iIndex,
-#endif /* LWIP_HTTPD_SSI_RAW */
-                             char *pcInsert, int iInsertLen
-#if LWIP_HTTPD_SSI_MULTIPART
-                             , u16_t current_tag_part, u16_t *next_tag_part
-#endif /* LWIP_HTTPD_SSI_MULTIPART */
-#if defined(LWIP_HTTPD_FILE_STATE) && LWIP_HTTPD_FILE_STATE
-                             , void *connection_state
-#endif /* LWIP_HTTPD_FILE_STATE */
-                             );
-
-/** Set the SSI handler function
- * (if LWIP_HTTPD_SSI_RAW==1, only the first argument is used)
- */
-void http_set_ssi_handler(tSSIHandler pfnSSIHandler,
-                          const char **ppcTags, int iNumTags);
-
-/** For LWIP_HTTPD_SSI_RAW==1, return this to indicate the tag is unknown.
- * In this case, the webserver writes a warning into the page.
- * You can also just return 0 to write nothing for unknown tags.
- */
-#define HTTPD_SSI_TAG_UNKNOWN 0xFFFF
-
-#endif /* LWIP_HTTPD_SSI */
-
-#if LWIP_HTTPD_SUPPORT_POST
-
-/* These functions must be implemented by the application */
-
-/** Called when a POST request has been received. The application can decide
- * whether to accept it or not.
- *
- * @param connection Unique connection identifier, valid until httpd_post_end
- *        is called.
- * @param uri The HTTP header URI receiving the POST request.
- * @param http_request The raw HTTP request (the first packet, normally).
- * @param http_request_len Size of 'http_request'.
- * @param content_len Content-Length from HTTP header.
- * @param response_uri Filename of response file, to be filled when denying the
- *        request
- * @param response_uri_len Size of the 'response_uri' buffer.
- * @param post_auto_wnd Set this to 0 to let the callback code handle window
- *        updates by calling 'httpd_post_data_recved' (to throttle rx speed)
- *        default is 1 (httpd handles window updates automatically)
- * @return ERR_OK: Accept the POST request, data may be passed in
- *         another err_t: Deny the POST request, send back 'bad request'.
- */
-err_t httpd_post_begin(void *connection, const char *uri, const char *http_request,
-                       u16_t http_request_len, int content_len, char *response_uri,
-                       u16_t response_uri_len, u8_t *post_auto_wnd);
-
-/** Called for each pbuf of data that has been received for a POST.
- * ATTENTION: The application is responsible for freeing the pbufs passed in!
- *
- * @param connection Unique connection identifier.
- * @param p Received data.
- * @return ERR_OK: Data accepted.
- *         another err_t: Data denied, http_post_get_response_uri will be called.
- */
-err_t httpd_post_receive_data(void *connection, struct pbuf *p);
-
-/** Called when all data is received or when the connection is closed.
- * The application must return the filename/URI of a file to send in response
- * to this POST request. If the response_uri buffer is untouched, a 404
- * response is returned.
- *
- * @param connection Unique connection identifier.
- * @param response_uri Filename of response file, to be filled when denying the request
- * @param response_uri_len Size of the 'response_uri' buffer.
- */
-void httpd_post_finished(void *connection, char *response_uri, u16_t response_uri_len);
-
-#if LWIP_HTTPD_POST_MANUAL_WND
-void httpd_post_data_recved(void *connection, u16_t recved_len);
-#endif /* LWIP_HTTPD_POST_MANUAL_WND */
-
-#endif /* LWIP_HTTPD_SUPPORT_POST */
-
-void httpd_init(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HTTPD_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/httpd_opts.h b/tools/sdk/include/lwip/lwip/apps/httpd_opts.h
deleted file mode 100644
index 340db15f663..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/httpd_opts.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/**
- * @file
- * HTTP server options list
- */
-
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- * This version of the file has been modified by Texas Instruments to offer
- * simple server-side-include (SSI) and Common Gateway Interface (CGI)
- * capability.
- */
-
-#ifndef LWIP_HDR_APPS_HTTPD_OPTS_H
-#define LWIP_HDR_APPS_HTTPD_OPTS_H
-
-#include "lwip/opt.h"
-
-/**
- * @defgroup httpd_opts Options
- * @ingroup httpd
- * @{
- */
-
-/** Set this to 1 to support CGI (old style) */
-#if !defined LWIP_HTTPD_CGI || defined __DOXYGEN__
-#define LWIP_HTTPD_CGI            0
-#endif
-
-/** Set this to 1 to support CGI (new style) */
-#if !defined LWIP_HTTPD_CGI_SSI || defined __DOXYGEN__
-#define LWIP_HTTPD_CGI_SSI        0
-#endif
-
-/** Set this to 1 to support SSI (Server-Side-Includes) */
-#if !defined LWIP_HTTPD_SSI || defined __DOXYGEN__
-#define LWIP_HTTPD_SSI            0
-#endif
-
-/** Set this to 1 to implement an SSI tag handler callback that gets a const char*
- * to the tag (instead of an index into a pre-registered array of known tags) */
-#if !defined LWIP_HTTPD_SSI_RAW || defined __DOXYGEN__
-#define LWIP_HTTPD_SSI_RAW        0
-#endif
-
-/** Set this to 1 to support HTTP POST */
-#if !defined LWIP_HTTPD_SUPPORT_POST || defined __DOXYGEN__
-#define LWIP_HTTPD_SUPPORT_POST   0
-#endif
-
-/* The maximum number of parameters that the CGI handler can be sent. */
-#if !defined LWIP_HTTPD_MAX_CGI_PARAMETERS || defined __DOXYGEN__
-#define LWIP_HTTPD_MAX_CGI_PARAMETERS 16
-#endif
-
-/** LWIP_HTTPD_SSI_MULTIPART==1: SSI handler function is called with 2 more
- * arguments indicating a counter for insert string that are too long to be
- * inserted at once: the SSI handler function must then set 'next_tag_part'
- * which will be passed back to it in the next call. */
-#if !defined LWIP_HTTPD_SSI_MULTIPART || defined __DOXYGEN__
-#define LWIP_HTTPD_SSI_MULTIPART    0
-#endif
-
-/* The maximum length of the string comprising the tag name */
-#if !defined LWIP_HTTPD_MAX_TAG_NAME_LEN || defined __DOXYGEN__
-#define LWIP_HTTPD_MAX_TAG_NAME_LEN 8
-#endif
-
-/* The maximum length of string that can be returned to replace any given tag */
-#if !defined LWIP_HTTPD_MAX_TAG_INSERT_LEN || defined __DOXYGEN__
-#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 192
-#endif
-
-#if !defined LWIP_HTTPD_POST_MANUAL_WND || defined __DOXYGEN__
-#define LWIP_HTTPD_POST_MANUAL_WND  0
-#endif
-
-/** This string is passed in the HTTP header as "Server: " */
-#if !defined HTTPD_SERVER_AGENT || defined __DOXYGEN__
-#define HTTPD_SERVER_AGENT "lwIP/" LWIP_VERSION_STRING " (http://savannah.nongnu.org/projects/lwip)"
-#endif
-
-/** Set this to 1 if you want to include code that creates HTTP headers
- * at runtime. Default is off: HTTP headers are then created statically
- * by the makefsdata tool. Static headers mean smaller code size, but
- * the (readonly) fsdata will grow a bit as every file includes the HTTP
- * header. */
-#if !defined LWIP_HTTPD_DYNAMIC_HEADERS || defined __DOXYGEN__
-#define LWIP_HTTPD_DYNAMIC_HEADERS 0
-#endif
-
-#if !defined HTTPD_DEBUG || defined __DOXYGEN__
-#define HTTPD_DEBUG         LWIP_DBG_OFF
-#endif
-
-/** Set this to 1 to use a memp pool for allocating 
- * struct http_state instead of the heap.
- */
-#if !defined HTTPD_USE_MEM_POOL || defined __DOXYGEN__
-#define HTTPD_USE_MEM_POOL  0
-#endif
-
-/** The server port for HTTPD to use */
-#if !defined HTTPD_SERVER_PORT || defined __DOXYGEN__
-#define HTTPD_SERVER_PORT                   80
-#endif
-
-/** Maximum retries before the connection is aborted/closed.
- * - number of times pcb->poll is called -> default is 4*500ms = 2s;
- * - reset when pcb->sent is called
- */
-#if !defined HTTPD_MAX_RETRIES || defined __DOXYGEN__
-#define HTTPD_MAX_RETRIES                   4
-#endif
-
-/** The poll delay is X*500ms */
-#if !defined HTTPD_POLL_INTERVAL || defined __DOXYGEN__
-#define HTTPD_POLL_INTERVAL                 4
-#endif
-
-/** Priority for tcp pcbs created by HTTPD (very low by default).
- *  Lower priorities get killed first when running out of memory.
- */
-#if !defined HTTPD_TCP_PRIO || defined __DOXYGEN__
-#define HTTPD_TCP_PRIO                      TCP_PRIO_MIN
-#endif
-
-/** Set this to 1 to enable timing each file sent */
-#if !defined LWIP_HTTPD_TIMING || defined __DOXYGEN__
-#define LWIP_HTTPD_TIMING                   0
-#endif
-/** Set this to 1 to enable timing each file sent */
-#if !defined HTTPD_DEBUG_TIMING || defined __DOXYGEN__
-#define HTTPD_DEBUG_TIMING                  LWIP_DBG_OFF
-#endif
-
-/** Set this to one to show error pages when parsing a request fails instead
-    of simply closing the connection. */
-#if !defined LWIP_HTTPD_SUPPORT_EXTSTATUS || defined __DOXYGEN__
-#define LWIP_HTTPD_SUPPORT_EXTSTATUS        0
-#endif
-
-/** Set this to 0 to drop support for HTTP/0.9 clients (to save some bytes) */
-#if !defined LWIP_HTTPD_SUPPORT_V09 || defined __DOXYGEN__
-#define LWIP_HTTPD_SUPPORT_V09              1
-#endif
-
-/** Set this to 1 to enable HTTP/1.1 persistent connections.
- * ATTENTION: If the generated file system includes HTTP headers, these must
- * include the "Connection: keep-alive" header (pass argument "-11" to makefsdata).
- */
-#if !defined LWIP_HTTPD_SUPPORT_11_KEEPALIVE || defined __DOXYGEN__
-#define LWIP_HTTPD_SUPPORT_11_KEEPALIVE     0
-#endif
-
-/** Set this to 1 to support HTTP request coming in in multiple packets/pbufs */
-#if !defined LWIP_HTTPD_SUPPORT_REQUESTLIST || defined __DOXYGEN__
-#define LWIP_HTTPD_SUPPORT_REQUESTLIST      1
-#endif
-
-#if LWIP_HTTPD_SUPPORT_REQUESTLIST
-/** Number of rx pbufs to enqueue to parse an incoming request (up to the first
-    newline) */
-#if !defined LWIP_HTTPD_REQ_QUEUELEN || defined __DOXYGEN__
-#define LWIP_HTTPD_REQ_QUEUELEN             5
-#endif
-
-/** Number of (TCP payload-) bytes (in pbufs) to enqueue to parse and incoming
-    request (up to the first double-newline) */
-#if !defined LWIP_HTTPD_REQ_BUFSIZE || defined __DOXYGEN__
-#define LWIP_HTTPD_REQ_BUFSIZE              LWIP_HTTPD_MAX_REQ_LENGTH
-#endif
-
-/** Defines the maximum length of a HTTP request line (up to the first CRLF,
-    copied from pbuf into this a global buffer when pbuf- or packet-queues
-    are received - otherwise the input pbuf is used directly) */
-#if !defined LWIP_HTTPD_MAX_REQ_LENGTH || defined __DOXYGEN__
-#define LWIP_HTTPD_MAX_REQ_LENGTH           LWIP_MIN(1023, (LWIP_HTTPD_REQ_QUEUELEN * PBUF_POOL_BUFSIZE))
-#endif
-#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */
-
-/** This is the size of a static buffer used when URIs end with '/'.
- * In this buffer, the directory requested is concatenated with all the
- * configured default file names.
- * Set to 0 to disable checking default filenames on non-root directories.
- */
-#if !defined LWIP_HTTPD_MAX_REQUEST_URI_LEN || defined __DOXYGEN__
-#define LWIP_HTTPD_MAX_REQUEST_URI_LEN      63
-#endif
-
-/** Maximum length of the filename to send as response to a POST request,
- * filled in by the application when a POST is finished.
- */
-#if !defined LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN || defined __DOXYGEN__
-#define LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN 63
-#endif
-
-/** Set this to 0 to not send the SSI tag (default is on, so the tag will
- * be sent in the HTML page */
-#if !defined LWIP_HTTPD_SSI_INCLUDE_TAG || defined __DOXYGEN__
-#define LWIP_HTTPD_SSI_INCLUDE_TAG           1
-#endif
-
-/** Set this to 1 to call tcp_abort when tcp_close fails with memory error.
- * This can be used to prevent consuming all memory in situations where the
- * HTTP server has low priority compared to other communication. */
-#if !defined LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR || defined __DOXYGEN__
-#define LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR  0
-#endif
-
-/** Set this to 1 to kill the oldest connection when running out of
- * memory for 'struct http_state' or 'struct http_ssi_state'.
- * ATTENTION: This puts all connections on a linked list, so may be kind of slow.
- */
-#if !defined LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED || defined __DOXYGEN__
-#define LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED 0
-#endif
-
-/** Set this to 1 to send URIs without extension without headers
- * (who uses this at all??) */
-#if !defined LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI || defined __DOXYGEN__
-#define LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI 0
-#endif
-
-/** Default: Tags are sent from struct http_state and are therefore volatile */
-#if !defined HTTP_IS_TAG_VOLATILE || defined __DOXYGEN__
-#define HTTP_IS_TAG_VOLATILE(ptr) TCP_WRITE_FLAG_COPY
-#endif
-
-/* By default, the httpd is limited to send 2*pcb->mss to keep resource usage low
-   when http is not an important protocol in the device. */
-#if !defined HTTPD_LIMIT_SENDING_TO_2MSS || defined __DOXYGEN__
-#define HTTPD_LIMIT_SENDING_TO_2MSS 1
-#endif
-
-/* Define this to a function that returns the maximum amount of data to enqueue.
-   The function have this signature: u16_t fn(struct tcp_pcb* pcb); */
-#if !defined HTTPD_MAX_WRITE_LEN || defined __DOXYGEN__
-#if HTTPD_LIMIT_SENDING_TO_2MSS
-#define HTTPD_MAX_WRITE_LEN(pcb)    (2 * tcp_mss(pcb))
-#endif
-#endif
-
-/*------------------- FS OPTIONS -------------------*/
-
-/** Set this to 1 and provide the functions:
- * - "int fs_open_custom(struct fs_file *file, const char *name)"
- *    Called first for every opened file to allow opening files
- *    that are not included in fsdata(_custom).c
- * - "void fs_close_custom(struct fs_file *file)"
- *    Called to free resources allocated by fs_open_custom().
- */
-#if !defined LWIP_HTTPD_CUSTOM_FILES || defined __DOXYGEN__
-#define LWIP_HTTPD_CUSTOM_FILES       0
-#endif
-
-/** Set this to 1 to support fs_read() to dynamically read file data.
- * Without this (default=off), only one-block files are supported,
- * and the contents must be ready after fs_open().
- */
-#if !defined LWIP_HTTPD_DYNAMIC_FILE_READ || defined __DOXYGEN__
-#define LWIP_HTTPD_DYNAMIC_FILE_READ  0
-#endif
-
-/** Set this to 1 to include an application state argument per file
- * that is opened. This allows to keep a state per connection/file.
- */
-#if !defined LWIP_HTTPD_FILE_STATE || defined __DOXYGEN__
-#define LWIP_HTTPD_FILE_STATE         0
-#endif
-
-/** HTTPD_PRECALCULATED_CHECKSUM==1: include precompiled checksums for
- * predefined (MSS-sized) chunks of the files to prevent having to calculate
- * the checksums at runtime. */
-#if !defined HTTPD_PRECALCULATED_CHECKSUM || defined __DOXYGEN__
-#define HTTPD_PRECALCULATED_CHECKSUM  0
-#endif
-
-/** LWIP_HTTPD_FS_ASYNC_READ==1: support asynchronous read operations
- * (fs_read_async returns FS_READ_DELAYED and calls a callback when finished).
- */
-#if !defined LWIP_HTTPD_FS_ASYNC_READ || defined __DOXYGEN__
-#define LWIP_HTTPD_FS_ASYNC_READ      0
-#endif
-
-/** Set this to 1 to include "fsdata_custom.c" instead of "fsdata.c" for the
- * file system (to prevent changing the file included in CVS) */
-#if !defined HTTPD_USE_CUSTOM_FSDATA || defined __DOXYGEN__
-#define HTTPD_USE_CUSTOM_FSDATA 0
-#endif
-
-/**
- * @}
- */
-
-#endif /* LWIP_HDR_APPS_HTTPD_OPTS_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/lwiperf.h b/tools/sdk/include/lwip/lwip/apps/lwiperf.h
deleted file mode 100644
index 7dbebb08264..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/lwiperf.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
- * @file
- * lwIP iPerf server implementation
- */
-
-/*
- * Copyright (c) 2014 Simon Goldschmidt
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Simon Goldschmidt
- *
- */
-#ifndef LWIP_HDR_APPS_LWIPERF_H
-#define LWIP_HDR_APPS_LWIPERF_H
-
-#include "lwip/opt.h"
-#include "lwip/ip_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define LWIPERF_TCP_PORT_DEFAULT  5001
-
-/** lwIPerf test results */
-enum lwiperf_report_type
-{
-  /** The server side test is done */
-  LWIPERF_TCP_DONE_SERVER,
-  /** The client side test is done */
-  LWIPERF_TCP_DONE_CLIENT,
-  /** Local error lead to test abort */
-  LWIPERF_TCP_ABORTED_LOCAL,
-  /** Data check error lead to test abort */
-  LWIPERF_TCP_ABORTED_LOCAL_DATAERROR,
-  /** Transmit error lead to test abort */
-  LWIPERF_TCP_ABORTED_LOCAL_TXERROR,
-  /** Remote side aborted the test */
-  LWIPERF_TCP_ABORTED_REMOTE
-};
-
-/** Prototype of a report function that is called when a session is finished.
-    This report function can show the test results.
-    @param report_type contains the test result */
-typedef void (*lwiperf_report_fn)(void *arg, enum lwiperf_report_type report_type,
-  const ip_addr_t* local_addr, u16_t local_port, const ip_addr_t* remote_addr, u16_t remote_port,
-  u32_t bytes_transferred, u32_t ms_duration, u32_t bandwidth_kbitpsec);
-
-
-void* lwiperf_start_tcp_server(const ip_addr_t* local_addr, u16_t local_port,
-                               lwiperf_report_fn report_fn, void* report_arg);
-void* lwiperf_start_tcp_server_default(lwiperf_report_fn report_fn, void* report_arg);
-void  lwiperf_abort(void* lwiperf_session);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_LWIPERF_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/mdns.h b/tools/sdk/include/lwip/lwip/apps/mdns.h
deleted file mode 100644
index d036816115d..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/mdns.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/**
- * @file
- * MDNS responder
- */
-
- /*
- * Copyright (c) 2015 Verisure Innovation AB
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Erik Ekman <erik@kryo.se>
- *
- */
-#ifndef LWIP_HDR_MDNS_H
-#define LWIP_HDR_MDNS_H
-
-#include "lwip/apps/mdns_opts.h"
-#include "lwip/netif.h"
-
-#if LWIP_MDNS_RESPONDER
-
-enum mdns_sd_proto {
-  DNSSD_PROTO_UDP = 0,
-  DNSSD_PROTO_TCP = 1
-};
-
-#define MDNS_LABEL_MAXLEN  63
-
-struct mdns_host;
-struct mdns_service;
-
-/** Callback function to add text to a reply, called when generating the reply */
-typedef void (*service_get_txt_fn_t)(struct mdns_service *service, void *txt_userdata);
-
-void mdns_resp_init(void);
-
-err_t mdns_resp_add_netif(struct netif *netif, const char *hostname, u32_t dns_ttl);
-err_t mdns_resp_remove_netif(struct netif *netif);
-
-err_t mdns_resp_add_service(struct netif *netif, const char *name, const char *service, enum mdns_sd_proto proto, u16_t port, u32_t dns_ttl, service_get_txt_fn_t txt_fn, void *txt_userdata);
-err_t mdns_resp_add_service_txtitem(struct mdns_service *service, const char *txt, u8_t txt_len);
-void mdns_resp_netif_settings_changed(struct netif *netif);
-
-#endif /* LWIP_MDNS_RESPONDER */
-
-#endif /* LWIP_HDR_MDNS_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/mdns_opts.h b/tools/sdk/include/lwip/lwip/apps/mdns_opts.h
deleted file mode 100644
index bf186bcce17..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/mdns_opts.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/**
- * @file
- * MDNS responder
- */
-
- /*
- * Copyright (c) 2015 Verisure Innovation AB
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Erik Ekman <erik@kryo.se>
- *
- */
-
-#ifndef LWIP_HDR_APPS_MDNS_OPTS_H
-#define LWIP_HDR_APPS_MDNS_OPTS_H
-
-#include "lwip/opt.h"
-
-/**
- * @defgroup mdns_opts Options
- * @ingroup mdns
- * @{
- */
-
-/**
- * LWIP_MDNS_RESPONDER==1: Turn on multicast DNS module. UDP must be available for MDNS
- * transport. IGMP is needed for IPv4 multicast.
- */
-#ifndef LWIP_MDNS_RESPONDER
-#define LWIP_MDNS_RESPONDER             0
-#endif /* LWIP_MDNS_RESPONDER */
-
-/** The maximum number of services per netif */
-#ifndef MDNS_MAX_SERVICES
-#define MDNS_MAX_SERVICES               1
-#endif
-
-/**
- * MDNS_DEBUG: Enable debugging for multicast DNS.
- */
-#ifndef MDNS_DEBUG
-#define MDNS_DEBUG                       LWIP_DBG_OFF
-#endif
-
-/**
- * @}
- */
-
-#endif /* LWIP_HDR_APPS_MDNS_OPTS_H */
-
diff --git a/tools/sdk/include/lwip/lwip/apps/mdns_priv.h b/tools/sdk/include/lwip/lwip/apps/mdns_priv.h
deleted file mode 100644
index 8ee6db86af4..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/mdns_priv.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/**
- * @file
- * MDNS responder private definitions
- */
-
- /*
- * Copyright (c) 2015 Verisure Innovation AB
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Erik Ekman <erik@kryo.se>
- *
- */
-#ifndef LWIP_HDR_MDNS_PRIV_H
-#define LWIP_HDR_MDNS_PRIV_H
-
-#include "lwip/apps/mdns_opts.h"
-#include "lwip/pbuf.h"
-
-#if LWIP_MDNS_RESPONDER
-
-/* Domain struct and methods - visible for unit tests */
-
-#define MDNS_DOMAIN_MAXLEN 256
-#define MDNS_READNAME_ERROR 0xFFFF
-
-struct mdns_domain {
-  /* Encoded domain name */
-  u8_t name[MDNS_DOMAIN_MAXLEN];
-  /* Total length of domain name, including zero */
-  u16_t length;
-  /* Set if compression of this domain is not allowed */
-  u8_t skip_compression;
-};
-
-err_t mdns_domain_add_label(struct mdns_domain *domain, const char *label, u8_t len);
-u16_t mdns_readname(struct pbuf *p, u16_t offset, struct mdns_domain *domain);
-int mdns_domain_eq(struct mdns_domain *a, struct mdns_domain *b);
-u16_t mdns_compress_domain(struct pbuf *pbuf, u16_t *offset, struct mdns_domain *domain);
-
-#endif /* LWIP_MDNS_RESPONDER */
-
-#endif /* LWIP_HDR_MDNS_PRIV_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/mqtt.h b/tools/sdk/include/lwip/lwip/apps/mqtt.h
deleted file mode 100644
index 34b230b888b..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/mqtt.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/**
- * @file
- * MQTT client
- */
-
-/*
- * Copyright (c) 2016 Erik Andersson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Erik Andersson
- *
- */
-#ifndef LWIP_HDR_APPS_MQTT_CLIENT_H
-#define LWIP_HDR_APPS_MQTT_CLIENT_H
-
-#include "lwip/apps/mqtt_opts.h"
-#include "lwip/err.h"
-#include "lwip/ip_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct mqtt_client_t mqtt_client_t;
-
-/** @ingroup mqtt
- * Default MQTT port */
-#define MQTT_PORT 1883
-
-/*---------------------------------------------------------------------------------------------- */
-/* Connection with server */
-
-/**
- * @ingroup mqtt
- * Client information and connection parameters */
-struct mqtt_connect_client_info_t {
-  /** Client identifier, must be set by caller */
-  const char *client_id;
-  /** User name and password, set to NULL if not used */
-  const char* client_user;
-  const char* client_pass;
-  /** keep alive time in seconds, 0 to disable keep alive functionality*/
-  u16_t keep_alive;
-  /** will topic, set to NULL if will is not to be used,
-      will_msg, will_qos and will retain are then ignored */
-  const char* will_topic;
-  const char* will_msg;
-  u8_t will_qos;
-  u8_t will_retain;
-};
-
-/**
- * @ingroup mqtt
- * Connection status codes */
-typedef enum
-{
-  MQTT_CONNECT_ACCEPTED                 = 0,
-  MQTT_CONNECT_REFUSED_PROTOCOL_VERSION = 1,
-  MQTT_CONNECT_REFUSED_IDENTIFIER       = 2,
-  MQTT_CONNECT_REFUSED_SERVER           = 3,
-  MQTT_CONNECT_REFUSED_USERNAME_PASS    = 4,
-  MQTT_CONNECT_REFUSED_NOT_AUTHORIZED_  = 5,
-  MQTT_CONNECT_DISCONNECTED             = 256,
-  MQTT_CONNECT_TIMEOUT                  = 257
-} mqtt_connection_status_t;
-
-/**
- * @ingroup mqtt
- * Function prototype for mqtt connection status callback. Called when
- * client has connected to the server after initiating a mqtt connection attempt by
- * calling mqtt_connect() or when connection is closed by server or an error
- *
- * @param client MQTT client itself
- * @param arg Additional argument to pass to the callback function
- * @param status Connect result code or disconnection notification @see mqtt_connection_status_t
- *
- */
-typedef void (*mqtt_connection_cb_t)(mqtt_client_t *client, void *arg, mqtt_connection_status_t status);
-
-
-/**
- * @ingroup mqtt
- * Data callback flags */
-enum {
-  /** Flag set when last fragment of data arrives in data callback */
-  MQTT_DATA_FLAG_LAST = 1
-};
-
-/** 
- * @ingroup mqtt
- * Function prototype for MQTT incoming publish data callback function. Called when data
- * arrives to a subscribed topic @see mqtt_subscribe
- *
- * @param arg Additional argument to pass to the callback function
- * @param data User data, pointed object, data may not be referenced after callback return,
-          NULL is passed when all publish data are delivered
- * @param len Length of publish data fragment
- * @param flags MQTT_DATA_FLAG_LAST set when this call contains the last part of data from publish message
- *
- */
-typedef void (*mqtt_incoming_data_cb_t)(void *arg, const u8_t *data, u16_t len, u8_t flags);
-
-
-/** 
- * @ingroup mqtt
- * Function prototype for MQTT incoming publish function. Called when an incoming publish
- * arrives to a subscribed topic @see mqtt_subscribe
- *
- * @param arg Additional argument to pass to the callback function
- * @param topic Zero terminated Topic text string, topic may not be referenced after callback return
- * @param tot_len Total length of publish data, if set to 0 (no publish payload) data callback will not be invoked
- */
-typedef void (*mqtt_incoming_publish_cb_t)(void *arg, const char *topic, u32_t tot_len);
-
-
-/**
- * @ingroup mqtt
- * Function prototype for mqtt request callback. Called when a subscribe, unsubscribe
- * or publish request has completed
- * @param arg Pointer to user data supplied when invoking request
- * @param err ERR_OK on success
- *            ERR_TIMEOUT if no response was received within timeout,
- *            ERR_ABRT if (un)subscribe was denied
- */
-typedef void (*mqtt_request_cb_t)(void *arg, err_t err);
-
-
-/**
- * Pending request item, binds application callback to pending server requests
- */
-struct mqtt_request_t
-{
-  /** Next item in list, NULL means this is the last in chain,
-      next pointing at itself means request is unallocated */
-  struct mqtt_request_t *next;
-  /** Callback to upper layer */
-  mqtt_request_cb_t cb;
-  void *arg;
-  /** MQTT packet identifier */
-  u16_t pkt_id;
-  /** Expire time relative to element before this  */
-  u16_t timeout_diff;
-};
-
-/** Ring buffer */
-struct mqtt_ringbuf_t {
-  u16_t put;
-  u16_t get;
-  u8_t buf[MQTT_OUTPUT_RINGBUF_SIZE];
-};
-
-/** MQTT client */
-struct mqtt_client_t
-{
-  /** Timers and timeouts */
-  u16_t cyclic_tick;
-  u16_t keep_alive;
-  u16_t server_watchdog;
-  /** Packet identifier generator*/
-  u16_t pkt_id_seq;
-  /** Packet identifier of pending incoming publish */
-  u16_t inpub_pkt_id;
-  /** Connection state */
-  u8_t conn_state;
-  struct tcp_pcb *conn;
-  /** Connection callback */
-  void *connect_arg;
-  mqtt_connection_cb_t connect_cb;
-  /** Pending requests to server */
-  struct mqtt_request_t *pend_req_queue;
-  struct mqtt_request_t req_list[MQTT_REQ_MAX_IN_FLIGHT];
-  void *inpub_arg;
-  /** Incoming data callback */
-  mqtt_incoming_data_cb_t data_cb;
-  mqtt_incoming_publish_cb_t pub_cb;
-  /** Input */
-  u32_t msg_idx;
-  u8_t rx_buffer[MQTT_VAR_HEADER_BUFFER_LEN];
-  /** Output ring-buffer */
-  struct mqtt_ringbuf_t output;
-};
-
-
-/** Connect to server */
-err_t mqtt_client_connect(mqtt_client_t *client, const ip_addr_t *ipaddr, u16_t port, mqtt_connection_cb_t cb, void *arg,
-                   const struct mqtt_connect_client_info_t *client_info);
-
-/** Disconnect from server */
-void mqtt_disconnect(mqtt_client_t *client);
-
-/** Create new client */
-mqtt_client_t *mqtt_client_new(void);
-
-/** Check connection status */
-u8_t mqtt_client_is_connected(mqtt_client_t *client);
-
-/** Set callback to call for incoming publish */
-void mqtt_set_inpub_callback(mqtt_client_t *client, mqtt_incoming_publish_cb_t,
-                             mqtt_incoming_data_cb_t data_cb, void *arg);
-
-/** Common function for subscribe and unsubscribe */
-err_t mqtt_sub_unsub(mqtt_client_t *client, const char *topic, u8_t qos, mqtt_request_cb_t cb, void *arg, u8_t sub);
-
-/** @ingroup mqtt
- *Subscribe to topic */
-#define mqtt_subscribe(client, topic, qos, cb, arg) mqtt_sub_unsub(client, topic, qos, cb, arg, 1)
-/** @ingroup mqtt
- *  Unsubscribe to topic */
-#define mqtt_unsubscribe(client, topic, cb, arg) mqtt_sub_unsub(client, topic, 0, cb, arg, 0)
-
-
-/** Publish data to topic */
-err_t mqtt_publish(mqtt_client_t *client, const char *topic, const void *payload, u16_t payload_length, u8_t qos, u8_t retain,
-                                    mqtt_request_cb_t cb, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_MQTT_CLIENT_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/mqtt_opts.h b/tools/sdk/include/lwip/lwip/apps/mqtt_opts.h
deleted file mode 100644
index ffefacd2595..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/mqtt_opts.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
- * @file
- * MQTT client options
- */
-
-/*
- * Copyright (c) 2016 Erik Andersson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Erik Andersson
- *
- */
-#ifndef LWIP_HDR_APPS_MQTT_OPTS_H
-#define LWIP_HDR_APPS_MQTT_OPTS_H
-
-#include "lwip/opt.h"
-
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup mqtt_opts Options
- * @ingroup mqtt
- * @{
- */
-
-/**
- * Output ring-buffer size, must be able to fit largest outgoing publish message topic+payloads
- */
-#ifndef MQTT_OUTPUT_RINGBUF_SIZE
-#define MQTT_OUTPUT_RINGBUF_SIZE 256
-#endif
-
-/**
- * Number of bytes in receive buffer, must be at least the size of the longest incoming topic + 8
- * If one wants to avoid fragmented incoming publish, set length to max incoming topic length + max payload length + 8
- */
-#ifndef MQTT_VAR_HEADER_BUFFER_LEN
-#define MQTT_VAR_HEADER_BUFFER_LEN 128
-#endif
-
-/**
- * Maximum number of pending subscribe, unsubscribe and publish requests to server .
- */
-#ifndef MQTT_REQ_MAX_IN_FLIGHT
-#define MQTT_REQ_MAX_IN_FLIGHT 4
-#endif
-
-/**
- * Seconds between each cyclic timer call.
- */
-#ifndef MQTT_CYCLIC_TIMER_INTERVAL
-#define MQTT_CYCLIC_TIMER_INTERVAL 5
-#endif
-
-/**
- * Publish, subscribe and unsubscribe request timeout in seconds.
- */
-#ifndef MQTT_REQ_TIMEOUT
-#define MQTT_REQ_TIMEOUT 30
-#endif
-
-/**
- * Seconds for MQTT connect response timeout after sending connect request
- */
-#ifndef MQTT_CONNECT_TIMOUT
-#define MQTT_CONNECT_TIMOUT 100
-#endif
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_MQTT_OPTS_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/netbiosns.h b/tools/sdk/include/lwip/lwip/apps/netbiosns.h
deleted file mode 100644
index c9f68d8d12c..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/netbiosns.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/**
- * @file
- * NETBIOS name service responder
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-#ifndef LWIP_HDR_APPS_NETBIOS_H
-#define LWIP_HDR_APPS_NETBIOS_H
-
-#include "lwip/apps/netbiosns_opts.h"
-
-void netbiosns_init(void);
-#ifndef NETBIOS_LWIP_NAME
-void netbiosns_set_name(const char* hostname);
-#endif
-void netbiosns_stop(void);
-
-#endif /* LWIP_HDR_APPS_NETBIOS_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/netbiosns_opts.h b/tools/sdk/include/lwip/lwip/apps/netbiosns_opts.h
deleted file mode 100644
index 0909ef7b94e..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/netbiosns_opts.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * @file
- * NETBIOS name service responder options
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-#ifndef LWIP_HDR_APPS_NETBIOS_OPTS_H
-#define LWIP_HDR_APPS_NETBIOS_OPTS_H
-
-#include "lwip/opt.h"
-
-/**
- * @defgroup netbiosns_opts Options
- * @ingroup netbiosns
- * @{
- */
-
-/** NetBIOS name of lwip device
- * This must be uppercase until NETBIOS_STRCMP() is defined to a string
- * comparision function that is case insensitive.
- * If you want to use the netif's hostname, use this (with LWIP_NETIF_HOSTNAME):
- * (ip_current_netif() != NULL ? ip_current_netif()->hostname != NULL ? ip_current_netif()->hostname : "" : "")
- *
- * If this is not defined, netbiosns_set_name() can be called at runtime to change the name.
- */
-#ifdef __DOXYGEN__
-#define NETBIOS_LWIP_NAME "NETBIOSLWIPDEV"
-#endif
-
-/**
- * @}
- */
-
-#endif /* LWIP_HDR_APPS_NETBIOS_OPTS_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/snmp.h b/tools/sdk/include/lwip/lwip/apps/snmp.h
deleted file mode 100644
index 10e8ff434bb..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/snmp.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
- * @file
- * SNMP server main API - start and basic configuration
- */
-
-/*
- * Copyright (c) 2001, 2002 Leon Woestenberg <leon.woestenberg@axon.tv>
- * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Leon Woestenberg <leon.woestenberg@axon.tv>
- *         Martin Hentschel <info@cl-soft.de>
- *
- */
-#ifndef LWIP_HDR_APPS_SNMP_H
-#define LWIP_HDR_APPS_SNMP_H
-
-#include "lwip/apps/snmp_opts.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/err.h"
-#include "lwip/apps/snmp_core.h"
-
-/** SNMP variable binding descriptor (publically needed for traps) */
-struct snmp_varbind
-{
-  /** pointer to next varbind, NULL for last in list */
-  struct snmp_varbind *next;
-  /** pointer to previous varbind, NULL for first in list */
-  struct snmp_varbind *prev;
-
-  /** object identifier */
-  struct snmp_obj_id oid;
-
-  /** value ASN1 type */
-  u8_t type;
-  /** object value length */
-  u16_t value_len;
-  /** object value */
-  void *value;
-};
-
-/**
- * @ingroup snmp_core
- * Agent setup, start listening to port 161.
- */
-void snmp_init(void);
-void snmp_set_mibs(const struct snmp_mib **mibs, u8_t num_mibs);
-
-void snmp_set_device_enterprise_oid(const struct snmp_obj_id* device_enterprise_oid);
-const struct snmp_obj_id* snmp_get_device_enterprise_oid(void);
-
-void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable);
-void snmp_trap_dst_ip_set(u8_t dst_idx, const ip_addr_t *dst);
-
-/** Generic trap: cold start */
-#define SNMP_GENTRAP_COLDSTART 0
-/** Generic trap: warm start */
-#define SNMP_GENTRAP_WARMSTART 1
-/** Generic trap: link down */
-#define SNMP_GENTRAP_LINKDOWN 2
-/** Generic trap: link up */
-#define SNMP_GENTRAP_LINKUP 3
-/** Generic trap: authentication failure */
-#define SNMP_GENTRAP_AUTH_FAILURE 4
-/** Generic trap: EGP neighbor lost */
-#define SNMP_GENTRAP_EGP_NEIGHBOR_LOSS 5
-/** Generic trap: enterprise specific */
-#define SNMP_GENTRAP_ENTERPRISE_SPECIFIC 6
-
-err_t snmp_send_trap_generic(s32_t generic_trap);
-err_t snmp_send_trap_specific(s32_t specific_trap, struct snmp_varbind *varbinds);
-err_t snmp_send_trap(const struct snmp_obj_id* oid, s32_t generic_trap, s32_t specific_trap, struct snmp_varbind *varbinds);
-
-#define SNMP_AUTH_TRAPS_DISABLED 0
-#define SNMP_AUTH_TRAPS_ENABLED  1
-void snmp_set_auth_traps_enabled(u8_t enable);
-u8_t snmp_get_auth_traps_enabled(void);
-
-const char * snmp_get_community(void);
-const char * snmp_get_community_write(void);
-const char * snmp_get_community_trap(void);
-void snmp_set_community(const char * const community);
-void snmp_set_community_write(const char * const community);
-void snmp_set_community_trap(const char * const community);
-
-void snmp_coldstart_trap(void);
-void snmp_authfail_trap(void);
-
-typedef void (*snmp_write_callback_fct)(const u32_t* oid, u8_t oid_len, void* callback_arg);
-void snmp_set_write_callback(snmp_write_callback_fct write_callback, void* callback_arg);
-
-#endif /* LWIP_SNMP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_SNMP_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/snmp_core.h b/tools/sdk/include/lwip/lwip/apps/snmp_core.h
deleted file mode 100644
index e781c532b38..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/snmp_core.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/**
- * @file
- * SNMP core API for implementing MIBs
- */
-
-/*
- * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: Christiaan Simons <christiaan.simons@axon.tv>
- *         Martin Hentschel <info@cl-soft.de>
- */
-
-#ifndef LWIP_HDR_APPS_SNMP_CORE_H
-#define LWIP_HDR_APPS_SNMP_CORE_H
-
-#include "lwip/apps/snmp_opts.h"
-
-#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/ip_addr.h"
-#include "lwip/err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* basic ASN1 defines */
-#define SNMP_ASN1_CLASS_UNIVERSAL   0x00
-#define SNMP_ASN1_CLASS_APPLICATION 0x40
-#define SNMP_ASN1_CLASS_CONTEXT     0x80
-#define SNMP_ASN1_CLASS_PRIVATE     0xC0
-
-#define SNMP_ASN1_CONTENTTYPE_PRIMITIVE   0x00
-#define SNMP_ASN1_CONTENTTYPE_CONSTRUCTED 0x20
-
-/* universal tags (from ASN.1 spec.) */
-#define SNMP_ASN1_UNIVERSAL_END_OF_CONTENT  0
-#define SNMP_ASN1_UNIVERSAL_INTEGER         2
-#define SNMP_ASN1_UNIVERSAL_OCTET_STRING    4
-#define SNMP_ASN1_UNIVERSAL_NULL            5
-#define SNMP_ASN1_UNIVERSAL_OBJECT_ID       6
-#define SNMP_ASN1_UNIVERSAL_SEQUENCE_OF    16
-
-/* application specific (SNMP) tags (from SNMPv2-SMI) */
-#define SNMP_ASN1_APPLICATION_IPADDR    0  /* [APPLICATION 0] IMPLICIT OCTET STRING (SIZE (4)) */
-#define SNMP_ASN1_APPLICATION_COUNTER   1  /* [APPLICATION 1] IMPLICIT INTEGER (0..4294967295) => u32_t */
-#define SNMP_ASN1_APPLICATION_GAUGE     2  /* [APPLICATION 2] IMPLICIT INTEGER (0..4294967295) => u32_t */
-#define SNMP_ASN1_APPLICATION_TIMETICKS 3  /* [APPLICATION 3] IMPLICIT INTEGER (0..4294967295) => u32_t */
-#define SNMP_ASN1_APPLICATION_OPAQUE    4  /* [APPLICATION 4] IMPLICIT OCTET STRING */
-#define SNMP_ASN1_APPLICATION_COUNTER64 6  /* [APPLICATION 6] IMPLICIT INTEGER (0..18446744073709551615) */
-
-/* context specific (SNMP) tags (from RFC 1905) */
-#define SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_INSTANCE 1
-
-/* full ASN1 type defines */
-#define SNMP_ASN1_TYPE_END_OF_CONTENT (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_END_OF_CONTENT)
-#define SNMP_ASN1_TYPE_INTEGER        (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_INTEGER)
-#define SNMP_ASN1_TYPE_OCTET_STRING   (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_OCTET_STRING)
-#define SNMP_ASN1_TYPE_NULL           (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_NULL)
-#define SNMP_ASN1_TYPE_OBJECT_ID      (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_OBJECT_ID)
-#define SNMP_ASN1_TYPE_SEQUENCE       (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_UNIVERSAL_SEQUENCE_OF)
-#define SNMP_ASN1_TYPE_IPADDR         (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_IPADDR)
-#define SNMP_ASN1_TYPE_IPADDRESS      SNMP_ASN1_TYPE_IPADDR
-#define SNMP_ASN1_TYPE_COUNTER        (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_COUNTER)
-#define SNMP_ASN1_TYPE_COUNTER32      SNMP_ASN1_TYPE_COUNTER
-#define SNMP_ASN1_TYPE_GAUGE          (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_GAUGE)
-#define SNMP_ASN1_TYPE_GAUGE32        SNMP_ASN1_TYPE_GAUGE
-#define SNMP_ASN1_TYPE_UNSIGNED32     SNMP_ASN1_TYPE_GAUGE
-#define SNMP_ASN1_TYPE_TIMETICKS      (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_TIMETICKS)
-#define SNMP_ASN1_TYPE_OPAQUE         (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_OPAQUE)
-#define SNMP_ASN1_TYPE_COUNTER64      (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_COUNTER64)
-
-#define SNMP_VARBIND_EXCEPTION_OFFSET 0xF0
-#define SNMP_VARBIND_EXCEPTION_MASK   0x0F
-
-/** error codes predefined by SNMP prot. */
-typedef enum {
-  SNMP_ERR_NOERROR             = 0,
-/* 
-outdated v1 error codes. do not use anmore!
-#define SNMP_ERR_NOSUCHNAME 2  use SNMP_ERR_NOSUCHINSTANCE instead
-#define SNMP_ERR_BADVALUE   3  use SNMP_ERR_WRONGTYPE,SNMP_ERR_WRONGLENGTH,SNMP_ERR_WRONGENCODING or SNMP_ERR_WRONGVALUE instead
-#define SNMP_ERR_READONLY   4  use SNMP_ERR_NOTWRITABLE instead
-*/
-  SNMP_ERR_GENERROR            = 5,
-  SNMP_ERR_NOACCESS            = 6,
-  SNMP_ERR_WRONGTYPE           = 7,
-  SNMP_ERR_WRONGLENGTH         = 8,
-  SNMP_ERR_WRONGENCODING       = 9,
-  SNMP_ERR_WRONGVALUE          = 10,
-  SNMP_ERR_NOCREATION          = 11,
-  SNMP_ERR_INCONSISTENTVALUE   = 12,
-  SNMP_ERR_RESOURCEUNAVAILABLE = 13,
-  SNMP_ERR_COMMITFAILED        = 14,
-  SNMP_ERR_UNDOFAILED          = 15,
-  SNMP_ERR_NOTWRITABLE         = 17,
-  SNMP_ERR_INCONSISTENTNAME    = 18,
-
-  SNMP_ERR_NOSUCHINSTANCE      = SNMP_VARBIND_EXCEPTION_OFFSET + SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_INSTANCE
-} snmp_err_t;
-
-/** internal object identifier representation */
-struct snmp_obj_id
-{
-  u8_t len;
-  u32_t id[SNMP_MAX_OBJ_ID_LEN];
-};
-
-struct snmp_obj_id_const_ref
-{
-  u8_t len;
-  const u32_t* id;
-};
-
-extern const struct snmp_obj_id_const_ref snmp_zero_dot_zero; /* administrative identifier from SNMPv2-SMI */
-
-/** SNMP variant value, used as reference in struct snmp_node_instance and table implementation */
-union snmp_variant_value
-{
-  void* ptr;
-  const void* const_ptr;
-  u32_t u32;
-  s32_t s32;
-};
-
-
-/**
-SNMP MIB node types
- tree node is the only node the stack can process in order to walk the tree,
- all other nodes are assumed to be leaf nodes.
- This cannot be an enum because users may want to define their own node types.
-*/
-#define SNMP_NODE_TREE         0x00
-/* predefined leaf node types */
-#define SNMP_NODE_SCALAR       0x01
-#define SNMP_NODE_SCALAR_ARRAY 0x02
-#define SNMP_NODE_TABLE        0x03
-#define SNMP_NODE_THREADSYNC   0x04
-
-/** node "base class" layout, the mandatory fields for a node  */
-struct snmp_node
-{
-  /** one out of SNMP_NODE_TREE or any leaf node type (like SNMP_NODE_SCALAR) */
-  u8_t node_type;
-  /** the number assigned to this node which used as part of the full OID */
-  u32_t oid;
-};
-
-/** SNMP node instance access types */
-typedef enum {
-  SNMP_NODE_INSTANCE_ACCESS_READ    = 1,
-  SNMP_NODE_INSTANCE_ACCESS_WRITE   = 2,
-  SNMP_NODE_INSTANCE_READ_ONLY      = SNMP_NODE_INSTANCE_ACCESS_READ,
-  SNMP_NODE_INSTANCE_READ_WRITE     = (SNMP_NODE_INSTANCE_ACCESS_READ | SNMP_NODE_INSTANCE_ACCESS_WRITE),
-  SNMP_NODE_INSTANCE_WRITE_ONLY     = SNMP_NODE_INSTANCE_ACCESS_WRITE,
-  SNMP_NODE_INSTANCE_NOT_ACCESSIBLE = 0
-} snmp_access_t;
-
-struct snmp_node_instance;
-
-typedef s16_t (*node_instance_get_value_method)(struct snmp_node_instance*, void*);
-typedef snmp_err_t (*node_instance_set_test_method)(struct snmp_node_instance*, u16_t, void*);
-typedef snmp_err_t (*node_instance_set_value_method)(struct snmp_node_instance*, u16_t, void*);
-typedef void (*node_instance_release_method)(struct snmp_node_instance*);
-
-#define SNMP_GET_VALUE_RAW_DATA 0x8000
-
-/** SNMP node instance */
-struct snmp_node_instance
-{
-  /** prefilled with the node, get_instance() is called on; may be changed by user to any value to pass an arbitrary node between calls to get_instance() and get_value/test_value/set_value */
-  const struct snmp_node* node;
-  /** prefilled with the instance id requested; for get_instance() this is the exact oid requested; for get_next_instance() this is the relative starting point, stack expects relative oid of next node here */
-  struct snmp_obj_id instance_oid;
-
-  /** ASN type for this object (see snmp_asn1.h for definitions) */
-  u8_t asn1_type;
-  /** one out of instance access types defined above (SNMP_NODE_INSTANCE_READ_ONLY,...) */
-  snmp_access_t access;
-
-  /** returns object value for the given object identifier. Return values <0 to indicate an error */
-  node_instance_get_value_method get_value;
-  /** tests length and/or range BEFORE setting */
-  node_instance_set_test_method set_test;
-  /** sets object value, only called when set_test() was successful */
-  node_instance_set_value_method set_value;
-  /** called in any case when the instance is not required anymore by stack (useful for freeing memory allocated in get_instance/get_next_instance methods) */
-  node_instance_release_method release_instance;
-
-  /** reference to pass arbitrary value between calls to get_instance() and get_value/test_value/set_value */
-  union snmp_variant_value reference;
-  /** see reference (if reference is a pointer, the length of underlying data may be stored here or anything else) */
-  u32_t reference_len;
-};
-
-
-/** SNMP tree node */
-struct snmp_tree_node
-{
-  /** inherited "base class" members */
-  struct snmp_node node;
-  u16_t subnode_count;
-  const struct snmp_node* const *subnodes;
-};
-
-#define SNMP_CREATE_TREE_NODE(oid, subnodes) \
-  {{ SNMP_NODE_TREE, (oid) }, \
-  (u16_t)LWIP_ARRAYSIZE(subnodes), (subnodes) }
-
-#define SNMP_CREATE_EMPTY_TREE_NODE(oid) \
-  {{ SNMP_NODE_TREE, (oid) }, \
-  0, NULL }
-
-/** SNMP leaf node */
-struct snmp_leaf_node
-{
-  /** inherited "base class" members */
-  struct snmp_node node;
-  snmp_err_t (*get_instance)(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-  snmp_err_t (*get_next_instance)(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-};
-
-/** represents a single mib with its base oid and root node */
-struct snmp_mib
-{
-  const u32_t *base_oid;
-  u8_t base_oid_len;
-  const struct snmp_node *root_node;
-};
-
-#define SNMP_MIB_CREATE(oid_list, root_node) { (oid_list), (u8_t)LWIP_ARRAYSIZE(oid_list), root_node }
-
-/** OID range structure */
-struct snmp_oid_range
-{
-  u32_t min;
-  u32_t max;
-};
-
-/** checks if incoming OID length and values are in allowed ranges */
-u8_t snmp_oid_in_range(const u32_t *oid_in, u8_t oid_len, const struct snmp_oid_range *oid_ranges, u8_t oid_ranges_len);
-
-typedef enum {
-  SNMP_NEXT_OID_STATUS_SUCCESS,
-  SNMP_NEXT_OID_STATUS_NO_MATCH,
-  SNMP_NEXT_OID_STATUS_BUF_TO_SMALL
-} snmp_next_oid_status_t;
-
-/** state for next_oid_init / next_oid_check functions */
-struct snmp_next_oid_state
-{
-  const u32_t* start_oid;
-  u8_t start_oid_len;
-
-  u32_t* next_oid;
-  u8_t next_oid_len;
-  u8_t next_oid_max_len;
-
-  snmp_next_oid_status_t status;
-  void* reference;
-};
-
-void snmp_next_oid_init(struct snmp_next_oid_state *state,
-  const u32_t *start_oid, u8_t start_oid_len,
-  u32_t *next_oid_buf, u8_t next_oid_max_len);
-u8_t snmp_next_oid_precheck(struct snmp_next_oid_state *state, const u32_t *oid, const u8_t oid_len);
-u8_t snmp_next_oid_check(struct snmp_next_oid_state *state, const u32_t *oid, const u8_t oid_len, void* reference);
-
-void snmp_oid_assign(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len);
-void snmp_oid_combine(struct snmp_obj_id* target, const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len);
-void snmp_oid_prefix(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len);
-void snmp_oid_append(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len);
-u8_t snmp_oid_equal(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len);
-s8_t snmp_oid_compare(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len);
-
-#if LWIP_IPV4
-u8_t snmp_oid_to_ip4(const u32_t *oid, ip4_addr_t *ip);
-void snmp_ip4_to_oid(const ip4_addr_t *ip, u32_t *oid);
-#endif /* LWIP_IPV4 */
-#if LWIP_IPV6
-u8_t snmp_oid_to_ip6(const u32_t *oid, ip6_addr_t *ip);
-void snmp_ip6_to_oid(const ip6_addr_t *ip, u32_t *oid);
-#endif /* LWIP_IPV6 */
-#if LWIP_IPV4 || LWIP_IPV6
-u8_t snmp_ip_to_oid(const ip_addr_t *ip, u32_t *oid);
-u8_t snmp_ip_port_to_oid(const ip_addr_t *ip, u16_t port, u32_t *oid);
-
-u8_t snmp_oid_to_ip(const u32_t *oid, u8_t oid_len, ip_addr_t *ip);
-u8_t snmp_oid_to_ip_port(const u32_t *oid, u8_t oid_len, ip_addr_t *ip, u16_t *port);
-#endif /* LWIP_IPV4 || LWIP_IPV6 */
-
-struct netif;
-u8_t netif_to_num(const struct netif *netif);
-
-snmp_err_t snmp_set_test_ok(struct snmp_node_instance* instance, u16_t value_len, void* value); /* generic function which can be used if test is always successful */
-
-err_t snmp_decode_bits(const u8_t *buf, u32_t buf_len, u32_t *bit_value);
-err_t snmp_decode_truthvalue(const s32_t *asn1_value, u8_t *bool_value);
-u8_t  snmp_encode_bits(u8_t *buf, u32_t buf_len, u32_t bit_value, u8_t bit_count);
-u8_t  snmp_encode_truthvalue(s32_t *asn1_value, u32_t bool_value);
-
-struct snmp_statistics
-{
-  u32_t inpkts;
-  u32_t outpkts;
-  u32_t inbadversions;
-  u32_t inbadcommunitynames;
-  u32_t inbadcommunityuses;
-  u32_t inasnparseerrs;
-  u32_t intoobigs;
-  u32_t innosuchnames;
-  u32_t inbadvalues;
-  u32_t inreadonlys;
-  u32_t ingenerrs;
-  u32_t intotalreqvars;
-  u32_t intotalsetvars;
-  u32_t ingetrequests;
-  u32_t ingetnexts;
-  u32_t insetrequests;
-  u32_t ingetresponses;
-  u32_t intraps;
-  u32_t outtoobigs;
-  u32_t outnosuchnames;
-  u32_t outbadvalues;
-  u32_t outgenerrs;
-  u32_t outgetrequests;
-  u32_t outgetnexts;
-  u32_t outsetrequests;
-  u32_t outgetresponses;
-  u32_t outtraps;
-};
-
-extern struct snmp_statistics snmp_stats;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_SNMP */
-
-#endif /* LWIP_HDR_APPS_SNMP_CORE_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/snmp_mib2.h b/tools/sdk/include/lwip/lwip/apps/snmp_mib2.h
deleted file mode 100644
index 2f4a68935e2..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/snmp_mib2.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
- * @file
- * SNMP MIB2 API
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Dirk Ziegelmeier <dziegel@gmx.de>
- *
- */
-#ifndef LWIP_HDR_APPS_SNMP_MIB2_H
-#define LWIP_HDR_APPS_SNMP_MIB2_H
-
-#include "lwip/apps/snmp_opts.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
-#if SNMP_LWIP_MIB2
-
-#include "lwip/apps/snmp_core.h"
-
-extern const struct snmp_mib mib2;
-
-#if SNMP_USE_NETCONN
-#include "lwip/apps/snmp_threadsync.h"
-void snmp_mib2_lwip_synchronizer(snmp_threadsync_called_fn fn, void* arg);
-extern struct snmp_threadsync_instance snmp_mib2_lwip_locks;
-#endif
-
-#ifndef SNMP_SYSSERVICES
-#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2))
-#endif
-
-void snmp_mib2_set_sysdescr(const u8_t* str, const u16_t* len); /* read-only be defintion */
-void snmp_mib2_set_syscontact(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize);
-void snmp_mib2_set_syscontact_readonly(const u8_t *ocstr, const u16_t *ocstrlen);
-void snmp_mib2_set_sysname(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize);
-void snmp_mib2_set_sysname_readonly(const u8_t *ocstr, const u16_t *ocstrlen);
-void snmp_mib2_set_syslocation(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize);
-void snmp_mib2_set_syslocation_readonly(const u8_t *ocstr, const u16_t *ocstrlen);
-
-#endif /* SNMP_LWIP_MIB2 */
-#endif /* LWIP_SNMP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_SNMP_MIB2_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/snmp_opts.h b/tools/sdk/include/lwip/lwip/apps/snmp_opts.h
deleted file mode 100644
index 6c9ba7beb33..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/snmp_opts.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/**
- * @file
- * SNMP server options list
- */
-
-/*
- * Copyright (c) 2015 Dirk Ziegelmeier
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Dirk Ziegelmeier
- *
- */
-#ifndef LWIP_HDR_SNMP_OPTS_H
-#define LWIP_HDR_SNMP_OPTS_H
-
-#include "lwip/opt.h"
-
-/**
- * @defgroup snmp_opts Options
- * @ingroup snmp
- * @{
- */
-
-/**
- * LWIP_SNMP==1: This enables the lwIP SNMP agent. UDP must be available
- * for SNMP transport.
- * If you want to use your own SNMP agent, leave this disabled.
- * To integrate MIB2 of an external agent, you need to enable
- * LWIP_MIB2_CALLBACKS and MIB2_STATS. This will give you the callbacks
- * and statistics counters you need to get MIB2 working.
- */
-#if !defined LWIP_SNMP || defined __DOXYGEN__
-#define LWIP_SNMP                       0
-#endif
-
-/**
- * SNMP_USE_NETCONN: Use netconn API instead of raw API.
- * Makes SNMP agent run in a worker thread, so blocking operations
- * can be done in MIB calls.
- */
-#if !defined SNMP_USE_NETCONN || defined __DOXYGEN__
-#define SNMP_USE_NETCONN           0
-#endif
-
-/**
- * SNMP_USE_RAW: Use raw API.
- * SNMP agent does not run in a worker thread, so blocking operations
- * should not be done in MIB calls.
- */
-#if !defined SNMP_USE_RAW || defined __DOXYGEN__
-#define SNMP_USE_RAW               1
-#endif
-
-#if SNMP_USE_NETCONN && SNMP_USE_RAW
-#error SNMP stack can use only one of the APIs {raw, netconn}
-#endif
-
-#if LWIP_SNMP && !SNMP_USE_NETCONN && !SNMP_USE_RAW
-#error SNMP stack needs a receive API and UDP {raw, netconn}
-#endif
-
-#if SNMP_USE_NETCONN
-/**
- * SNMP_STACK_SIZE: Stack size of SNMP netconn worker thread
- */
-#if !defined SNMP_STACK_SIZE || defined __DOXYGEN__
-#define SNMP_STACK_SIZE            DEFAULT_THREAD_STACKSIZE
-#endif
-
-/**
- * SNMP_THREAD_PRIO: SNMP netconn worker thread priority
- */
-#if !defined SNMP_THREAD_PRIO || defined __DOXYGEN__
-#define SNMP_THREAD_PRIO           DEFAULT_THREAD_PRIO
-#endif
-#endif /* SNMP_USE_NETCONN */
-
-/**
- * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap
- * destination is required
- */
-#if !defined SNMP_TRAP_DESTINATIONS || defined __DOXYGEN__
-#define SNMP_TRAP_DESTINATIONS          1
-#endif
-
-/**
- * Only allow SNMP write actions that are 'safe' (e.g. disabling netifs is not
- * a safe action and disabled when SNMP_SAFE_REQUESTS = 1).
- * Unsafe requests are disabled by default!
- */
-#if !defined SNMP_SAFE_REQUESTS || defined __DOXYGEN__
-#define SNMP_SAFE_REQUESTS              1
-#endif
-
-/**
- * The maximum length of strings used.
- */
-#if !defined SNMP_MAX_OCTET_STRING_LEN || defined __DOXYGEN__
-#define SNMP_MAX_OCTET_STRING_LEN       127
-#endif
-
-/**
- * The maximum number of Sub ID's inside an object identifier.
- * Indirectly this also limits the maximum depth of SNMP tree.
- */
-#if !defined SNMP_MAX_OBJ_ID_LEN || defined __DOXYGEN__
-#define SNMP_MAX_OBJ_ID_LEN             50
-#endif
-
-#if !defined SNMP_MAX_VALUE_SIZE || defined __DOXYGEN__
-/**
- * The maximum size of a value.
- */
-#define SNMP_MIN_VALUE_SIZE             (2 * sizeof(u32_t*)) /* size required to store the basic types (8 bytes for counter64) */
-/**
- * The minimum size of a value.
- */
-#define SNMP_MAX_VALUE_SIZE             LWIP_MAX(LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN), sizeof(u32_t)*(SNMP_MAX_OBJ_ID_LEN)), SNMP_MIN_VALUE_SIZE)
-#endif
-
-/**
- * The snmp read-access community. Used for write-access and traps, too
- * unless SNMP_COMMUNITY_WRITE or SNMP_COMMUNITY_TRAP are enabled, respectively.
- */
-#if !defined SNMP_COMMUNITY || defined __DOXYGEN__
-#define SNMP_COMMUNITY                  "public"
-#endif
-
-/**
- * The snmp write-access community.
- * Set this community to "" in order to disallow any write access.
- */
-#if !defined SNMP_COMMUNITY_WRITE || defined __DOXYGEN__
-#define SNMP_COMMUNITY_WRITE            "private"
-#endif
-
-/**
- * The snmp community used for sending traps.
- */
-#if !defined SNMP_COMMUNITY_TRAP || defined __DOXYGEN__
-#define SNMP_COMMUNITY_TRAP             "public"
-#endif
-
-/**
- * The maximum length of community string.
- * If community names shall be adjusted at runtime via snmp_set_community() calls,
- * enter here the possible maximum length (+1 for terminating null character).
- */
-#if !defined SNMP_MAX_COMMUNITY_STR_LEN || defined __DOXYGEN__
-#define SNMP_MAX_COMMUNITY_STR_LEN LWIP_MAX(LWIP_MAX(sizeof(SNMP_COMMUNITY), sizeof(SNMP_COMMUNITY_WRITE)), sizeof(SNMP_COMMUNITY_TRAP))
-#endif
-
-/**
- * The OID identifiying the device. This may be the enterprise OID itself or any OID located below it in tree.
- */
-#if !defined SNMP_DEVICE_ENTERPRISE_OID || defined __DOXYGEN__
-#define SNMP_LWIP_ENTERPRISE_OID 26381
-/**
- * IANA assigned enterprise ID for lwIP is 26381
- * @see http://www.iana.org/assignments/enterprise-numbers
- *
- * @note this enterprise ID is assigned to the lwIP project,
- * all object identifiers living under this ID are assigned
- * by the lwIP maintainers!
- * @note don't change this define, use snmp_set_device_enterprise_oid()
- *
- * If you need to create your own private MIB you'll need
- * to apply for your own enterprise ID with IANA:
- * http://www.iana.org/numbers.html
- */
-#define SNMP_DEVICE_ENTERPRISE_OID {1, 3, 6, 1, 4, 1, SNMP_LWIP_ENTERPRISE_OID}
-/**
- * Length of SNMP_DEVICE_ENTERPRISE_OID
- */
-#define SNMP_DEVICE_ENTERPRISE_OID_LEN 7
-#endif
-
-/**
- * SNMP_DEBUG: Enable debugging for SNMP messages.
- */
-#if !defined SNMP_DEBUG || defined __DOXYGEN__
-#define SNMP_DEBUG                      LWIP_DBG_OFF
-#endif
-
-/**
- * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs.
- */
-#if !defined SNMP_MIB_DEBUG || defined __DOXYGEN__
-#define SNMP_MIB_DEBUG                  LWIP_DBG_OFF
-#endif
-
-/**
- * Indicates if the MIB2 implementation of LWIP SNMP stack is used.
- */
-#if !defined SNMP_LWIP_MIB2 || defined __DOXYGEN__
-#define SNMP_LWIP_MIB2                      LWIP_SNMP
-#endif
-
-/**
- * Value return for sysDesc field of MIB2.
- */
-#if !defined SNMP_LWIP_MIB2_SYSDESC || defined __DOXYGEN__
-#define SNMP_LWIP_MIB2_SYSDESC              "lwIP"
-#endif
-
-/**
- * Value return for sysName field of MIB2.
- * To make sysName field settable, call snmp_mib2_set_sysname() to provide the necessary buffers.
- */
-#if !defined SNMP_LWIP_MIB2_SYSNAME || defined __DOXYGEN__
-#define SNMP_LWIP_MIB2_SYSNAME              "FQDN-unk"
-#endif
-
-/**
- * Value return for sysContact field of MIB2.
- * To make sysContact field settable, call snmp_mib2_set_syscontact() to provide the necessary buffers.
- */
-#if !defined SNMP_LWIP_MIB2_SYSCONTACT || defined __DOXYGEN__
-#define SNMP_LWIP_MIB2_SYSCONTACT           ""
-#endif
-
-/**
- * Value return for sysLocation field of MIB2.
- * To make sysLocation field settable, call snmp_mib2_set_syslocation() to provide the necessary buffers.
- */
-#if !defined SNMP_LWIP_MIB2_SYSLOCATION || defined __DOXYGEN__
-#define SNMP_LWIP_MIB2_SYSLOCATION          ""
-#endif
-
-/**
- * This value is used to limit the repetitions processed in GetBulk requests (value == 0 means no limitation).
- * This may be useful to limit the load for a single request.
- * According to SNMP RFC 1905 it is allowed to not return all requested variables from a GetBulk request if system load would be too high.
- * so the effect is that the client will do more requests to gather all data.
- * For the stack this could be useful in case that SNMP processing is done in TCP/IP thread. In this situation a request with many
- * repetitions could block the thread for a longer time. Setting limit here will keep the stack more responsive.
- */
-#if !defined SNMP_LWIP_GETBULK_MAX_REPETITIONS || defined __DOXYGEN__
-#define SNMP_LWIP_GETBULK_MAX_REPETITIONS 0
-#endif
-
-/**
- * @}
- */
-
-/*
-   ------------------------------------
-   ---------- SNMPv3 options ----------
-   ------------------------------------
-*/
-
-/**
- * LWIP_SNMP_V3==1: This enables EXPERIMENTAL SNMPv3 support. LWIP_SNMP must
- * also be enabled.
- * THIS IS UNDER DEVELOPMENT AND SHOULD NOT BE ENABLED IN PRODUCTS.
- */
-#ifndef LWIP_SNMP_V3
-#define LWIP_SNMP_V3               0
-#endif
-
-#ifndef LWIP_SNMP_V3_CRYPTO
-#define LWIP_SNMP_V3_CRYPTO        LWIP_SNMP_V3
-#endif
-
-#ifndef LWIP_SNMP_V3_MBEDTLS
-#define LWIP_SNMP_V3_MBEDTLS       LWIP_SNMP_V3
-#endif
-
-#endif /* LWIP_HDR_SNMP_OPTS_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/snmp_scalar.h b/tools/sdk/include/lwip/lwip/apps/snmp_scalar.h
deleted file mode 100644
index 40a060c6404..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/snmp_scalar.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/**
- * @file
- * SNMP server MIB API to implement scalar nodes
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Martin Hentschel <info@cl-soft.de>
- *
- */
-
-#ifndef LWIP_HDR_APPS_SNMP_SCALAR_H
-#define LWIP_HDR_APPS_SNMP_SCALAR_H
-
-#include "lwip/apps/snmp_opts.h"
-#include "lwip/apps/snmp_core.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
-
-/** basic scalar node */
-struct snmp_scalar_node
-{
-  /** inherited "base class" members */
-  struct snmp_leaf_node node;
-  u8_t asn1_type;
-  snmp_access_t access;
-  node_instance_get_value_method get_value;
-  node_instance_set_test_method set_test;
-  node_instance_set_value_method set_value;
-};
-
-
-snmp_err_t snmp_scalar_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-snmp_err_t snmp_scalar_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-
-#define SNMP_SCALAR_CREATE_NODE(oid, access, asn1_type, get_value_method, set_test_method, set_value_method) \
-  {{{ SNMP_NODE_SCALAR, (oid) }, \
-    snmp_scalar_get_instance, \
-    snmp_scalar_get_next_instance }, \
-    (asn1_type), (access), (get_value_method), (set_test_method), (set_value_method) }
-
-#define SNMP_SCALAR_CREATE_NODE_READONLY(oid, asn1_type, get_value_method) SNMP_SCALAR_CREATE_NODE(oid, SNMP_NODE_INSTANCE_READ_ONLY, asn1_type, get_value_method, NULL, NULL)
-
-/** scalar array node - a tree node which contains scalars only as children */
-struct snmp_scalar_array_node_def
-{
-  u32_t         oid;
-  u8_t          asn1_type;
-  snmp_access_t access;
-};
-
-typedef s16_t (*snmp_scalar_array_get_value_method)(const struct snmp_scalar_array_node_def*, void*);
-typedef snmp_err_t (*snmp_scalar_array_set_test_method)(const struct snmp_scalar_array_node_def*, u16_t, void*);
-typedef snmp_err_t (*snmp_scalar_array_set_value_method)(const struct snmp_scalar_array_node_def*, u16_t, void*);
-
-/** basic scalar array node */
-struct snmp_scalar_array_node
-{
-  /** inherited "base class" members */
-  struct snmp_leaf_node node;
-  u16_t array_node_count;
-  const struct snmp_scalar_array_node_def* array_nodes;
-  snmp_scalar_array_get_value_method get_value;
-  snmp_scalar_array_set_test_method set_test;
-  snmp_scalar_array_set_value_method set_value;
-};
-
-snmp_err_t snmp_scalar_array_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-snmp_err_t snmp_scalar_array_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-
-#define SNMP_SCALAR_CREATE_ARRAY_NODE(oid, array_nodes, get_value_method, set_test_method, set_value_method) \
-  {{{ SNMP_NODE_SCALAR_ARRAY, (oid) }, \
-    snmp_scalar_array_get_instance, \
-    snmp_scalar_array_get_next_instance }, \
-    (u16_t)LWIP_ARRAYSIZE(array_nodes), (array_nodes), (get_value_method), (set_test_method), (set_value_method) }
-
-#endif /* LWIP_SNMP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_SNMP_SCALAR_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/snmp_table.h b/tools/sdk/include/lwip/lwip/apps/snmp_table.h
deleted file mode 100644
index 4988b51c250..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/snmp_table.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/**
- * @file
- * SNMP server MIB API to implement table nodes
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Martin Hentschel <info@cl-soft.de>
- *
- */
-
-#ifndef LWIP_HDR_APPS_SNMP_TABLE_H
-#define LWIP_HDR_APPS_SNMP_TABLE_H
-
-#include "lwip/apps/snmp_opts.h"
-#include "lwip/apps/snmp_core.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
-
-/** default (customizable) read/write table */
-struct snmp_table_col_def
-{
-  u32_t index;
-  u8_t asn1_type;
-  snmp_access_t access;
-};
-
-/** table node */
-struct snmp_table_node
-{
-  /** inherited "base class" members */
-  struct snmp_leaf_node node;
-  u16_t column_count;
-  const struct snmp_table_col_def* columns;
-  snmp_err_t (*get_cell_instance)(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, struct snmp_node_instance* cell_instance);
-  snmp_err_t (*get_next_cell_instance)(const u32_t* column, struct snmp_obj_id* row_oid, struct snmp_node_instance* cell_instance);
-  /** returns object value for the given object identifier */
-  node_instance_get_value_method get_value;
-  /** tests length and/or range BEFORE setting */
-  node_instance_set_test_method set_test;
-  /** sets object value, only called when set_test() was successful */
-  node_instance_set_value_method set_value;
-};
-
-snmp_err_t snmp_table_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-snmp_err_t snmp_table_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-
-#define SNMP_TABLE_CREATE(oid, columns, get_cell_instance_method, get_next_cell_instance_method, get_value_method, set_test_method, set_value_method) \
-  {{{ SNMP_NODE_TABLE, (oid) }, \
-  snmp_table_get_instance, \
-  snmp_table_get_next_instance }, \
-  (u16_t)LWIP_ARRAYSIZE(columns), (columns), \
-  (get_cell_instance_method), (get_next_cell_instance_method), \
-  (get_value_method), (set_test_method), (set_value_method)}
-
-#define SNMP_TABLE_GET_COLUMN_FROM_OID(oid) ((oid)[1]) /* first array value is (fixed) row entry (fixed to 1) and 2nd value is column, follow3ed by instance */
-
-
-/** simple read-only table */
-typedef enum {
-  SNMP_VARIANT_VALUE_TYPE_U32,
-  SNMP_VARIANT_VALUE_TYPE_S32,
-  SNMP_VARIANT_VALUE_TYPE_PTR,
-  SNMP_VARIANT_VALUE_TYPE_CONST_PTR
-} snmp_table_column_data_type_t;
-
-struct snmp_table_simple_col_def
-{
-  u32_t index;
-  u8_t asn1_type;
-  snmp_table_column_data_type_t data_type; /* depending of what union member is used to store the value*/
-};
-
-/** simple read-only table node */
-struct snmp_table_simple_node
-{
-  /* inherited "base class" members */
-  struct snmp_leaf_node node;
-  u16_t column_count;
-  const struct snmp_table_simple_col_def* columns;
-  snmp_err_t (*get_cell_value)(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len);
-  snmp_err_t (*get_next_cell_instance_and_value)(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len);
-};
-
-snmp_err_t snmp_table_simple_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-snmp_err_t snmp_table_simple_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-
-#define SNMP_TABLE_CREATE_SIMPLE(oid, columns, get_cell_value_method, get_next_cell_instance_and_value_method) \
-  {{{ SNMP_NODE_TABLE, (oid) }, \
-  snmp_table_simple_get_instance, \
-  snmp_table_simple_get_next_instance }, \
-  (u16_t)LWIP_ARRAYSIZE(columns), (columns), (get_cell_value_method), (get_next_cell_instance_and_value_method) }
-
-s16_t snmp_table_extract_value_from_s32ref(struct snmp_node_instance* instance, void* value);
-s16_t snmp_table_extract_value_from_u32ref(struct snmp_node_instance* instance, void* value);
-s16_t snmp_table_extract_value_from_refconstptr(struct snmp_node_instance* instance, void* value);
-
-#endif /* LWIP_SNMP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_SNMP_TABLE_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/snmp_threadsync.h b/tools/sdk/include/lwip/lwip/apps/snmp_threadsync.h
deleted file mode 100644
index a25dbf2d0f0..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/snmp_threadsync.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/**
- * @file
- * SNMP server MIB API to implement thread synchronization
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Dirk Ziegelmeier <dziegel@gmx.de>
- *
- */
-
-#ifndef LWIP_HDR_APPS_SNMP_THREADSYNC_H
-#define LWIP_HDR_APPS_SNMP_THREADSYNC_H
-
-#include "lwip/apps/snmp_opts.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/apps/snmp_core.h"
-#include "lwip/sys.h"
-
-typedef void (*snmp_threadsync_called_fn)(void* arg);
-typedef void (*snmp_threadsync_synchronizer_fn)(snmp_threadsync_called_fn fn, void* arg);
-
-
-/** Thread sync runtime data. For internal usage only. */
-struct threadsync_data
-{
-  union {
-    snmp_err_t err;
-    s16_t s16;
-  } retval;
-  union {
-    const u32_t *root_oid;
-    void *value;
-  } arg1;
-  union {
-    u8_t root_oid_len;
-    u16_t len;
-  } arg2;
-  const struct snmp_threadsync_node *threadsync_node;
-  struct snmp_node_instance proxy_instance;
-};
-
-/** Thread sync instance. Needed EXCATLY once for every thread to be synced into. */
-struct snmp_threadsync_instance
-{
-  sys_sem_t                       sem;
-  sys_mutex_t                     sem_usage_mutex;
-  snmp_threadsync_synchronizer_fn sync_fn;
-  struct threadsync_data          data;
-};
-
-/** SNMP thread sync proxy leaf node */
-struct snmp_threadsync_node
-{
-  /* inherited "base class" members */
-  struct snmp_leaf_node           node;
-
-  const struct snmp_leaf_node     *target;
-  struct snmp_threadsync_instance *instance;
-};
-
-snmp_err_t snmp_threadsync_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-snmp_err_t snmp_threadsync_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance);
-
-/** Create thread sync proxy node */
-#define SNMP_CREATE_THREAD_SYNC_NODE(oid, target_leaf_node, threadsync_instance) \
-  {{{ SNMP_NODE_THREADSYNC, (oid) }, \
-    snmp_threadsync_get_instance, \
-    snmp_threadsync_get_next_instance }, \
-    (target_leaf_node), \
-    (threadsync_instance) }
-
-/** Create thread sync instance data */
-void snmp_threadsync_init(struct snmp_threadsync_instance *instance, snmp_threadsync_synchronizer_fn sync_fn);
-
-#endif /* LWIP_SNMP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_SNMP_THREADSYNC_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/snmpv3.h b/tools/sdk/include/lwip/lwip/apps/snmpv3.h
deleted file mode 100644
index c99fed4e101..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/snmpv3.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- * @file
- * Additional SNMPv3 functionality RFC3414 and RFC3826.
- */
-
-/*
- * Copyright (c) 2016 Elias Oenal.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: Elias Oenal <lwip@eliasoenal.com>
- */
-
-#ifndef LWIP_HDR_APPS_SNMP_V3_H
-#define LWIP_HDR_APPS_SNMP_V3_H
-
-#include "lwip/apps/snmp_opts.h"
-#include "lwip/err.h"
-
-#if LWIP_SNMP && LWIP_SNMP_V3
-
-#define SNMP_V3_AUTH_ALGO_INVAL  0
-#define SNMP_V3_AUTH_ALGO_MD5    1
-#define SNMP_V3_AUTH_ALGO_SHA    2
-
-#define SNMP_V3_PRIV_ALGO_INVAL  0
-#define SNMP_V3_PRIV_ALGO_DES    1
-#define SNMP_V3_PRIV_ALGO_AES    2
-
-#define SNMP_V3_PRIV_MODE_DECRYPT  0
-#define SNMP_V3_PRIV_MODE_ENCRYPT  1
-
-/*
- * The following callback functions must be implemented by the application.
- * There is a dummy implementation in snmpv3_dummy.c.
- */
-
-void snmpv3_get_engine_id(const char **id, u8_t *len);
-err_t snmpv3_set_engine_id(const char* id, u8_t len);
-
-u32_t snmpv3_get_engine_boots(void);
-void snmpv3_set_engine_boots(u32_t boots);
-
-u32_t snmpv3_get_engine_time(void);
-void snmpv3_reset_engine_time(void);
-
-err_t snmpv3_get_user(const char* username, u8_t *auth_algo, u8_t *auth_key, u8_t *priv_algo, u8_t *priv_key);
-
-/* The following functions are provided by the SNMPv3 agent */
-
-void snmpv3_engine_id_changed(void);
-
-void snmpv3_password_to_key_md5(
-    const u8_t *password,     /* IN */
-    u8_t        passwordlen,  /* IN */
-    const u8_t *engineID,     /* IN  - pointer to snmpEngineID  */
-    u8_t        engineLength, /* IN  - length of snmpEngineID */
-    u8_t       *key);         /* OUT - pointer to caller 16-octet buffer */
-
-void snmpv3_password_to_key_sha(
-    const u8_t *password,     /* IN */
-    u8_t        passwordlen,  /* IN */
-    const u8_t *engineID,     /* IN  - pointer to snmpEngineID  */
-    u8_t        engineLength, /* IN  - length of snmpEngineID */
-    u8_t       *key);         /* OUT - pointer to caller 20-octet buffer */
-
-#endif
-
-#endif /* LWIP_HDR_APPS_SNMP_V3_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/sntp.h b/tools/sdk/include/lwip/lwip/apps/sntp.h
deleted file mode 100644
index 40df9cc590f..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/sntp.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
- * @file
- * SNTP client API
- */
-
-/*
- * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Frédéric Bernon, Simon Goldschmidt
- *
- */
-#ifndef LWIP_HDR_APPS_SNTP_H
-#define LWIP_HDR_APPS_SNTP_H
-
-#include "lwip/apps/sntp_opts.h"
-#include "lwip/ip_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* SNTP operating modes: default is to poll using unicast.
-   The mode has to be set before calling sntp_init(). */
-#define SNTP_OPMODE_POLL            0
-#define SNTP_OPMODE_LISTENONLY      1
-void sntp_setoperatingmode(u8_t operating_mode);
-u8_t sntp_getoperatingmode(void);
-
-void sntp_init(void);
-void sntp_stop(void);
-u8_t sntp_enabled(void);
-
-void sntp_setserver(u8_t idx, const ip_addr_t *addr);
-const ip_addr_t* sntp_getserver(u8_t idx);
-
-#if SNTP_SERVER_DNS
-void sntp_setservername(u8_t idx, char *server);
-char *sntp_getservername(u8_t idx);
-#endif /* SNTP_SERVER_DNS */
-
-#if SNTP_GET_SERVERS_FROM_DHCP
-void sntp_servermode_dhcp(int set_servers_from_dhcp);
-#else /* SNTP_GET_SERVERS_FROM_DHCP */
-#define sntp_servermode_dhcp(x)
-#endif /* SNTP_GET_SERVERS_FROM_DHCP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_SNTP_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/sntp_opts.h b/tools/sdk/include/lwip/lwip/apps/sntp_opts.h
deleted file mode 100644
index dee0f0a41bd..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/sntp_opts.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/**
- * @file
- * SNTP client options list
- */
-
-/*
- * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Frédéric Bernon, Simon Goldschmidt
- *
- */
-#ifndef LWIP_HDR_APPS_SNTP_OPTS_H
-#define LWIP_HDR_APPS_SNTP_OPTS_H
-
-#include "lwip/opt.h"
-
-/**
- * @defgroup sntp_opts Options
- * @ingroup sntp
- * @{
- */
-
-/** SNTP macro to change system time in seconds
- * Define SNTP_SET_SYSTEM_TIME_US(sec, us) to set the time in microseconds instead of this one
- * if you need the additional precision.
- */
-#if !defined SNTP_SET_SYSTEM_TIME || defined __DOXYGEN__
-#define SNTP_SET_SYSTEM_TIME(sec)   LWIP_UNUSED_ARG(sec)
-#endif
-
-/** The maximum number of SNTP servers that can be set */
-#if !defined SNTP_MAX_SERVERS || defined __DOXYGEN__
-#define SNTP_MAX_SERVERS           LWIP_DHCP_MAX_NTP_SERVERS
-#endif
-
-/** Set this to 1 to implement the callback function called by dhcp when
- * NTP servers are received. */
-#if !defined SNTP_GET_SERVERS_FROM_DHCP || defined __DOXYGEN__
-#define SNTP_GET_SERVERS_FROM_DHCP LWIP_DHCP_GET_NTP_SRV
-#endif
-
-/** Set this to 1 to support DNS names (or IP address strings) to set sntp servers
- * One server address/name can be defined as default if SNTP_SERVER_DNS == 1:
- * \#define SNTP_SERVER_ADDRESS "pool.ntp.org"
- */
-#if !defined SNTP_SERVER_DNS || defined __DOXYGEN__
-#define SNTP_SERVER_DNS            1
-#endif
-
-/**
- * SNTP_DEBUG: Enable debugging for SNTP.
- */
-#if !defined SNTP_DEBUG || defined __DOXYGEN__
-#define SNTP_DEBUG                  LWIP_DBG_OFF
-#endif
-
-/** SNTP server port */
-#if !defined SNTP_PORT || defined __DOXYGEN__
-#define SNTP_PORT                   123
-#endif
-
-/** Set this to 1 to allow config of SNTP server(s) by DNS name */
-#if !defined SNTP_SERVER_DNS || defined __DOXYGEN__
-#define SNTP_SERVER_DNS             0
-#endif
-
-/** Sanity check:
- * Define this to
- * - 0 to turn off sanity checks (default; smaller code)
- * - >= 1 to check address and port of the response packet to ensure the
- *        response comes from the server we sent the request to.
- * - >= 2 to check returned Originate Timestamp against Transmit Timestamp
- *        sent to the server (to ensure response to older request).
- * - >= 3 @todo: discard reply if any of the LI, Stratum, or Transmit Timestamp
- *        fields is 0 or the Mode field is not 4 (unicast) or 5 (broadcast).
- * - >= 4 @todo: to check that the Root Delay and Root Dispersion fields are each
- *        greater than or equal to 0 and less than infinity, where infinity is
- *        currently a cozy number like one second. This check avoids using a
- *        server whose synchronization source has expired for a very long time.
- */
-#if !defined SNTP_CHECK_RESPONSE || defined __DOXYGEN__
-#define SNTP_CHECK_RESPONSE         0
-#endif
-
-/** According to the RFC, this shall be a random delay
- * between 1 and 5 minutes (in milliseconds) to prevent load peaks.
- * This can be defined to a random generation function,
- * which must return the delay in milliseconds as u32_t.
- * Turned off by default.
- */
-#if !defined SNTP_STARTUP_DELAY || defined __DOXYGEN__
-#define SNTP_STARTUP_DELAY          0
-#endif
-
-/** If you want the startup delay to be a function, define this
- * to a function (including the brackets) and define SNTP_STARTUP_DELAY to 1.
- */
-#if !defined SNTP_STARTUP_DELAY_FUNC || defined __DOXYGEN__
-#define SNTP_STARTUP_DELAY_FUNC     SNTP_STARTUP_DELAY
-#endif
-
-/** SNTP receive timeout - in milliseconds
- * Also used as retry timeout - this shouldn't be too low.
- * Default is 3 seconds.
- */
-#if !defined SNTP_RECV_TIMEOUT || defined __DOXYGEN__
-#define SNTP_RECV_TIMEOUT           3000
-#endif
-
-/** SNTP update delay - in milliseconds
- * Default is 1 hour. Must not be beolw 15 seconds by specification (i.e. 15000)
- */
-#if !defined SNTP_UPDATE_DELAY || defined __DOXYGEN__
-#define SNTP_UPDATE_DELAY           3600000
-#endif
-
-/** SNTP macro to get system time, used with SNTP_CHECK_RESPONSE >= 2
- * to send in request and compare in response.
- */
-#if !defined SNTP_GET_SYSTEM_TIME || defined __DOXYGEN__
-#define SNTP_GET_SYSTEM_TIME(sec, us)     do { (sec) = 0; (us) = 0; } while(0)
-#endif
-
-/** Default retry timeout (in milliseconds) if the response
- * received is invalid.
- * This is doubled with each retry until SNTP_RETRY_TIMEOUT_MAX is reached.
- */
-#if !defined SNTP_RETRY_TIMEOUT || defined __DOXYGEN__
-#define SNTP_RETRY_TIMEOUT          SNTP_RECV_TIMEOUT
-#endif
-
-/** Maximum retry timeout (in milliseconds). */
-#if !defined SNTP_RETRY_TIMEOUT_MAX || defined __DOXYGEN__
-#define SNTP_RETRY_TIMEOUT_MAX      (SNTP_RETRY_TIMEOUT * 10)
-#endif
-
-/** Increase retry timeout with every retry sent
- * Default is on to conform to RFC.
- */
-#if !defined SNTP_RETRY_TIMEOUT_EXP || defined __DOXYGEN__
-#define SNTP_RETRY_TIMEOUT_EXP      1
-#endif
-
-/**
- * @}
- */
-
-#endif /* LWIP_HDR_APPS_SNTP_OPTS_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/tftp_opts.h b/tools/sdk/include/lwip/lwip/apps/tftp_opts.h
deleted file mode 100644
index 6968a803b43..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/tftp_opts.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/****************************************************************//**
- *
- * @file tftp_opts.h
- *
- * @author   Logan Gunthorpe <logang@deltatee.com>
- *
- * @brief    Trivial File Transfer Protocol (RFC 1350) implementation options
- *
- * Copyright (c) Deltatee Enterprises Ltd. 2013
- * All rights reserved.
- *
- ********************************************************************/
-
-/* 
- * Redistribution and use in source and binary forms, with or without
- * modification,are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Logan Gunthorpe <logang@deltatee.com>
- *
- */
-
-#ifndef LWIP_HDR_APPS_TFTP_OPTS_H
-#define LWIP_HDR_APPS_TFTP_OPTS_H
-
-#include "lwip/opt.h"
-
-/**
- * @defgroup tftp_opts Options
- * @ingroup tftp
- * @{
- */
-
-/**
- * Enable TFTP debug messages
- */
-#if !defined TFTP_DEBUG || defined __DOXYGEN__
-#define TFTP_DEBUG            LWIP_DBG_ON
-#endif
-
-/**
- * TFTP server port
- */
-#if !defined TFTP_PORT || defined __DOXYGEN__
-#define TFTP_PORT             69
-#endif
-
-/**
- * TFTP timeout
- */
-#if !defined TFTP_TIMEOUT_MSECS || defined __DOXYGEN__
-#define TFTP_TIMEOUT_MSECS    10000
-#endif
-
-/**
- * Max. number of retries when a file is read from server
- */
-#if !defined TFTP_MAX_RETRIES || defined __DOXYGEN__
-#define TFTP_MAX_RETRIES      5
-#endif
-
-/**
- * TFTP timer cyclic interval
- */
-#if !defined TFTP_TIMER_MSECS || defined __DOXYGEN__
-#define TFTP_TIMER_MSECS      50
-#endif
-
-/**
- * Max. length of TFTP filename
- */
-#if !defined TFTP_MAX_FILENAME_LEN || defined __DOXYGEN__
-#define TFTP_MAX_FILENAME_LEN 20
-#endif
-
-/**
- * Max. length of TFTP mode
- */
-#if !defined TFTP_MAX_MODE_LEN || defined __DOXYGEN__
-#define TFTP_MAX_MODE_LEN     7
-#endif
-
-/**
- * @}
- */
-
-#endif /* LWIP_HDR_APPS_TFTP_OPTS_H */
diff --git a/tools/sdk/include/lwip/lwip/apps/tftp_server.h b/tools/sdk/include/lwip/lwip/apps/tftp_server.h
deleted file mode 100644
index 3fbe701e0a2..00000000000
--- a/tools/sdk/include/lwip/lwip/apps/tftp_server.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/****************************************************************//**
- *
- * @file tftp_server.h
- *
- * @author   Logan Gunthorpe <logang@deltatee.com>
- *
- * @brief    Trivial File Transfer Protocol (RFC 1350)
- *
- * Copyright (c) Deltatee Enterprises Ltd. 2013
- * All rights reserved.
- *
- ********************************************************************/
-
-/* 
- * Redistribution and use in source and binary forms, with or without
- * modification,are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Logan Gunthorpe <logang@deltatee.com>
- *
- */
-
-#ifndef LWIP_HDR_APPS_TFTP_SERVER_H
-#define LWIP_HDR_APPS_TFTP_SERVER_H
-
-#include "lwip/apps/tftp_opts.h"
-#include "lwip/err.h"
-#include "lwip/pbuf.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @ingroup tftp
- * TFTP context containing callback functions for TFTP transfers
- */
-struct tftp_context {
-  /**
-   * Open file for read/write.
-   * @param fname Filename
-   * @param mode Mode string from TFTP RFC 1350 (netascii, octet, mail)
-   * @param write Flag indicating read (0) or write (!= 0) access
-   * @returns File handle supplied to other functions
-   */
-  void* (*open)(const char* fname, const char* mode, u8_t write);
-  /**
-   * Close file handle
-   * @param handle File handle returned by open()
-   */
-  void (*close)(void* handle);
-  /**
-   * Read from file 
-   * @param handle File handle returned by open()
-   * @param buf Target buffer to copy read data to
-   * @param bytes Number of bytes to copy to buf
-   * @returns &gt;= 0: Success; &lt; 0: Error
-   */
-  int (*read)(void* handle, void* buf, int bytes);
-  /**
-   * Write to file
-   * @param handle File handle returned by open()
-   * @param pbuf PBUF adjusted such that payload pointer points
-   *             to the beginning of write data. In other words,
-   *             TFTP headers are stripped off.
-   * @returns &gt;= 0: Success; &lt; 0: Error
-   */
-  int (*write)(void* handle, struct pbuf* p);
-};
-
-err_t tftp_init(const struct tftp_context* ctx);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_APPS_TFTP_SERVER_H */
diff --git a/tools/sdk/include/lwip/lwip/arch.h b/tools/sdk/include/lwip/lwip/arch.h
deleted file mode 100644
index 31d92ca3f44..00000000000
--- a/tools/sdk/include/lwip/lwip/arch.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/**
- * @file
- * Support for different processor and compiler architectures
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_ARCH_H
-#define LWIP_HDR_ARCH_H
-
-#ifndef LITTLE_ENDIAN
-#define LITTLE_ENDIAN 1234
-#endif
-
-#ifndef BIG_ENDIAN
-#define BIG_ENDIAN 4321
-#endif
-
-#include "arch/cc.h"
-
-/**
- * @defgroup compiler_abstraction Compiler/platform abstraction
- * @ingroup sys_layer
- * All defines related to this section must not be placed in lwipopts.h,
- * but in arch/cc.h!
- * These options cannot be \#defined in lwipopts.h since they are not options
- * of lwIP itself, but options of the lwIP port to your system.
- * @{
- */
-
-/** Define the byte order of the system.
- * Needed for conversion of network data to host byte order.
- * Allowed values: LITTLE_ENDIAN and BIG_ENDIAN
- */
-#ifndef BYTE_ORDER
-#define BYTE_ORDER LITTLE_ENDIAN
-#endif
-
-/** Define random number generator function of your system */
-#ifdef __DOXYGEN__
-#define LWIP_RAND() ((u32_t)rand())
-#endif
-
-/** Platform specific diagnostic output.\n
- * Note the default implementation pulls in printf, which may
- * in turn pull in a lot of standard libary code. In resource-constrained 
- * systems, this should be defined to something less resource-consuming.
- */
-#ifndef LWIP_PLATFORM_DIAG
-#define LWIP_PLATFORM_DIAG(x) do {printf x;} while(0)
-#include <stdio.h>
-#include <stdlib.h>
-#endif
-
-/** Platform specific assertion handling.\n
- * Note the default implementation pulls in printf, fflush and abort, which may
- * in turn pull in a lot of standard libary code. In resource-constrained 
- * systems, this should be defined to something less resource-consuming.
- */
-#ifndef LWIP_PLATFORM_ASSERT
-#define LWIP_PLATFORM_ASSERT(x) do {printf("Assertion \"%s\" failed at line %d in %s\n", \
-                                     x, __LINE__, __FILE__); fflush(NULL); abort();} while(0)
-#include <stdio.h>
-#include <stdlib.h>
-#endif
-
-/** Define this to 1 in arch/cc.h of your port if you do not want to
- * include stddef.h header to get size_t. You need to typedef size_t
- * by yourself in this case.
- */
-#ifndef LWIP_NO_STDDEF_H
-#define LWIP_NO_STDDEF_H 0
-#endif
-
-#if !LWIP_NO_STDDEF_H
-#include <stddef.h> /* for size_t */
-#endif
-
-/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
- * the stdint.h header. You need to typedef the generic types listed in
- * lwip/arch.h yourself in this case (u8_t, u16_t...).
- */
-#ifndef LWIP_NO_STDINT_H
-#define LWIP_NO_STDINT_H 0
-#endif
-
-/* Define generic types used in lwIP */
-#if !LWIP_NO_STDINT_H
-#include <stdint.h>
-typedef uint8_t   u8_t;
-typedef int8_t    s8_t;
-typedef uint16_t  u16_t;
-typedef int16_t   s16_t;
-typedef uint32_t  u32_t;
-typedef int32_t   s32_t;
-#endif
-
-/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
- * the inttypes.h header. You need to define the format strings listed in
- * lwip/arch.h yourself in this case (X8_F, U16_F...).
- */
-#ifndef LWIP_NO_INTTYPES_H
-#define LWIP_NO_INTTYPES_H 0
-#endif
-
-/* Define (sn)printf formatters for these lwIP types */
-#if !LWIP_NO_INTTYPES_H
-#include <inttypes.h>
-#ifndef X8_F
-#define X8_F  "02" PRIx8
-#endif
-#ifndef U16_F
-#define U16_F PRIu16
-#endif
-#ifndef S16_F
-#define S16_F PRId16
-#endif
-#ifndef X16_F
-#define X16_F PRIx16
-#endif
-#ifndef U32_F
-#define U32_F PRIu32
-#endif
-#ifndef S32_F
-#define S32_F PRId32
-#endif
-#ifndef X32_F
-#define X32_F PRIx32
-#endif
-#ifndef SZT_F
-#define SZT_F PRIuPTR
-#endif
-#endif
-
-/** Define this to 1 in arch/cc.h of your port if your compiler does not provide
- * the limits.h header. You need to define the type limits yourself in this case
- * (e.g. INT_MAX).
- */
-#ifndef LWIP_NO_LIMITS_H
-#define LWIP_NO_LIMITS_H 0
-#endif
-
-/* Include limits.h? */
-#if !LWIP_NO_LIMITS_H
-#include <limits.h>
-#endif
-
-/** C++ const_cast<target_type>(val) equivalent to remove constness from a value (GCC -Wcast-qual) */
-#ifndef LWIP_CONST_CAST
-#define LWIP_CONST_CAST(target_type, val) ((target_type)((ptrdiff_t)val))
-#endif
-
-/** Get rid of alignment cast warnings (GCC -Wcast-align) */
-#ifndef LWIP_ALIGNMENT_CAST
-#define LWIP_ALIGNMENT_CAST(target_type, val) LWIP_CONST_CAST(target_type, val)
-#endif
-
-/** Get rid of warnings related to pointer-to-numeric and vice-versa casts,
- * e.g. "conversion from 'u8_t' to 'void *' of greater size"
- */
-#ifndef LWIP_PTR_NUMERIC_CAST
-#define LWIP_PTR_NUMERIC_CAST(target_type, val) LWIP_CONST_CAST(target_type, val)
-#endif
-
-/** Allocates a memory buffer of specified size that is of sufficient size to align
- * its start address using LWIP_MEM_ALIGN.
- * You can declare your own version here e.g. to enforce alignment without adding
- * trailing padding bytes (see LWIP_MEM_ALIGN_BUFFER) or your own section placement
- * requirements.\n
- * e.g. if you use gcc and need 32 bit alignment:\n
- * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[size] \_\_attribute\_\_((aligned(4)))\n
- * or more portable:\n
- * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u32_t variable_name[(size + sizeof(u32_t) - 1) / sizeof(u32_t)]
- */
-#ifndef LWIP_DECLARE_MEMORY_ALIGNED
-#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[LWIP_MEM_ALIGN_BUFFER(size)]
-#endif
-
-/** Calculate memory size for an aligned buffer - returns the next highest
- * multiple of MEM_ALIGNMENT (e.g. LWIP_MEM_ALIGN_SIZE(3) and
- * LWIP_MEM_ALIGN_SIZE(4) will both yield 4 for MEM_ALIGNMENT == 4).
- */
-#ifndef LWIP_MEM_ALIGN_SIZE
-#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1U) & ~(MEM_ALIGNMENT-1U))
-#endif
-
-/** Calculate safe memory size for an aligned buffer when using an unaligned
- * type as storage. This includes a safety-margin on (MEM_ALIGNMENT - 1) at the
- * start (e.g. if buffer is u8_t[] and actual data will be u32_t*)
- */
-#ifndef LWIP_MEM_ALIGN_BUFFER
-#define LWIP_MEM_ALIGN_BUFFER(size) (((size) + MEM_ALIGNMENT - 1U))
-#endif
-
-/** Align a memory pointer to the alignment defined by MEM_ALIGNMENT
- * so that ADDR % MEM_ALIGNMENT == 0
- */
-#ifndef LWIP_MEM_ALIGN
-#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1)))
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Packed structs support.
-  * Placed BEFORE declaration of a packed struct.\n
-  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
-  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
-  */
-#ifndef PACK_STRUCT_BEGIN
-#define PACK_STRUCT_BEGIN
-#endif /* PACK_STRUCT_BEGIN */
-
-/** Packed structs support.
-  * Placed AFTER declaration of a packed struct.\n
-  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
-  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
-  */
-#ifndef PACK_STRUCT_END
-#define PACK_STRUCT_END
-#endif /* PACK_STRUCT_END */
-
-/** Packed structs support.
-  * Placed between end of declaration of a packed struct and trailing semicolon.\n
-  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
-  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
-  */
-#ifndef PACK_STRUCT_STRUCT
-#if defined(__GNUC__) || defined(__clang__)
-#define PACK_STRUCT_STRUCT __attribute__((packed))
-#else
-#define PACK_STRUCT_STRUCT
-#endif
-#endif /* PACK_STRUCT_STRUCT */
-
-/** Packed structs support.
-  * Wraps u32_t and u16_t members.\n
-  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
-  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
-  */
-#ifndef PACK_STRUCT_FIELD
-#define PACK_STRUCT_FIELD(x) x
-#endif /* PACK_STRUCT_FIELD */
-
-/** Packed structs support.
-  * Wraps u8_t members, where some compilers warn that packing is not necessary.\n
-  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
-  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
-  */
-#ifndef PACK_STRUCT_FLD_8
-#define PACK_STRUCT_FLD_8(x) PACK_STRUCT_FIELD(x)
-#endif /* PACK_STRUCT_FLD_8 */
-
-/** Packed structs support.
-  * Wraps members that are packed structs themselves, where some compilers warn that packing is not necessary.\n
-  * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
-  * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
-  */
-#ifndef PACK_STRUCT_FLD_S
-#define PACK_STRUCT_FLD_S(x) PACK_STRUCT_FIELD(x)
-#endif /* PACK_STRUCT_FLD_S */
-
-/** Packed structs support using \#include files before and after struct to be packed.\n
- * The file included BEFORE the struct is "arch/bpstruct.h".\n
- * The file included AFTER the struct is "arch/epstruct.h".\n
- * This can be used to implement struct packing on MS Visual C compilers, see
- * the Win32 port in the lwIP contrib repository for reference.
- * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n
- * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here.
- */
-#ifdef __DOXYGEN__
-#define PACK_STRUCT_USE_INCLUDES
-#endif
-
-/** Eliminates compiler warning about unused arguments (GCC -Wextra -Wunused). */
-#ifndef LWIP_UNUSED_ARG
-#define LWIP_UNUSED_ARG(x) (void)x
-#endif /* LWIP_UNUSED_ARG */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_ARCH_H */
diff --git a/tools/sdk/include/lwip/lwip/autoip.h b/tools/sdk/include/lwip/lwip/autoip.h
deleted file mode 100644
index 1d85bccff8b..00000000000
--- a/tools/sdk/include/lwip/lwip/autoip.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- * @file
- *
- * AutoIP Automatic LinkLocal IP Configuration
- */
-
-/*
- *
- * Copyright (c) 2007 Dominik Spies <kontakt@dspies.de>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: Dominik Spies <kontakt@dspies.de>
- *
- * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
- * with RFC 3927.
- *
- */
-
-#ifndef LWIP_HDR_AUTOIP_H
-#define LWIP_HDR_AUTOIP_H
-
-#include "lwip/opt.h"
-
-#if LWIP_IPV4 && LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/netif.h"
-/* #include "lwip/udp.h" */
-#include "lwip/etharp.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** AutoIP Timing */
-#define AUTOIP_TMR_INTERVAL      100
-#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL)
-
-/** AutoIP state information per netif */
-struct autoip
-{
-  /** the currently selected, probed, announced or used LL IP-Address */
-  ip4_addr_t llipaddr;
-  /** current AutoIP state machine state */
-  u8_t state;
-  /** sent number of probes or announces, dependent on state */
-  u8_t sent_num;
-  /** ticks to wait, tick is AUTOIP_TMR_INTERVAL long */
-  u16_t ttw;
-  /** ticks until a conflict can be solved by defending */
-  u8_t lastconflict;
-  /** total number of probed/used Link Local IP-Addresses */
-  u8_t tried_llipaddr;
-};
-
-
-void autoip_set_struct(struct netif *netif, struct autoip *autoip);
-/** Remove a struct autoip previously set to the netif using autoip_set_struct() */
-#define autoip_remove_struct(netif) do { (netif)->autoip = NULL; } while (0)
-err_t autoip_start(struct netif *netif);
-err_t autoip_stop(struct netif *netif);
-void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr);
-void autoip_tmr(void);
-void autoip_network_changed(struct netif *netif);
-u8_t autoip_supplied_address(const struct netif *netif);
-
-/* for lwIP internal use by ip4.c */
-u8_t autoip_accept_packet(struct netif *netif, const ip4_addr_t *addr);
-
-#define netif_autoip_data(netif) ((struct autoip*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV4 && LWIP_AUTOIP */
-
-#endif /* LWIP_HDR_AUTOIP_H */
diff --git a/tools/sdk/include/lwip/lwip/debug.h b/tools/sdk/include/lwip/lwip/debug.h
deleted file mode 100644
index a142f1cff3c..00000000000
--- a/tools/sdk/include/lwip/lwip/debug.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
- * @file
- * Debug messages infrastructure
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_DEBUG_H
-#define LWIP_HDR_DEBUG_H
-
-#include "lwip/arch.h"
-#include "lwip/opt.h"
-
-/**
- * @defgroup debugging_levels LWIP_DBG_MIN_LEVEL and LWIP_DBG_TYPES_ON values
- * @ingroup lwip_opts_debugmsg
- * @{
- */
-
-/** @name Debug level (LWIP_DBG_MIN_LEVEL)
- * @{
- */
-/** Debug level: ALL messages*/
-#define LWIP_DBG_LEVEL_ALL     0x00
-/** Debug level: Warnings. bad checksums, dropped packets, ... */
-#define LWIP_DBG_LEVEL_WARNING 0x01
-/** Debug level: Serious. memory allocation failures, ... */
-#define LWIP_DBG_LEVEL_SERIOUS 0x02
-/** Debug level: Severe */
-#define LWIP_DBG_LEVEL_SEVERE  0x03
-/**
- * @}
- */
-
-#define LWIP_DBG_MASK_LEVEL    0x03
-/* compatibility define only */
-#define LWIP_DBG_LEVEL_OFF     LWIP_DBG_LEVEL_ALL
-
-/** @name Enable/disable debug messages completely (LWIP_DBG_TYPES_ON)
- * @{
- */
-/** flag for LWIP_DEBUGF to enable that debug message */
-#define LWIP_DBG_ON            0x80U
-/** flag for LWIP_DEBUGF to disable that debug message */
-#define LWIP_DBG_OFF           0x00U
-/**
- * @}
- */
-
-/** @name Debug message types (LWIP_DBG_TYPES_ON)
- * @{
- */
-/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */
-#define LWIP_DBG_TRACE         0x40U
-/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */
-#define LWIP_DBG_STATE         0x20U
-/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */
-#define LWIP_DBG_FRESH         0x10U
-/** flag for LWIP_DEBUGF to halt after printing this debug message */
-#define LWIP_DBG_HALT          0x08U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @defgroup lwip_assertions Assertion handling
- * @ingroup lwip_opts_debug
- * @{
- */
-/**
- * LWIP_NOASSERT: Disable LWIP_ASSERT checks:
- * To disable assertions define LWIP_NOASSERT in arch/cc.h.
- */
-#ifdef __DOXYGEN__
-#define LWIP_NOASSERT
-#undef LWIP_NOASSERT
-#endif
-/**
- * @}
- */
-
-#ifndef LWIP_NOASSERT
-#define LWIP_ASSERT(message, assertion) do { if (!(assertion)) { \
-  LWIP_PLATFORM_ASSERT(message); }} while(0)
-#ifndef LWIP_PLATFORM_ASSERT
-#error "If you want to use LWIP_ASSERT, LWIP_PLATFORM_ASSERT(message) needs to be defined in your arch/cc.h"
-#endif
-#else  /* LWIP_NOASSERT */
-#define LWIP_ASSERT(message, assertion)
-#endif /* LWIP_NOASSERT */
-
-#ifndef LWIP_ERROR
-#ifndef LWIP_NOASSERT
-#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_ASSERT(message)
-#elif defined LWIP_DEBUG
-#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_DIAG((message))
-#else
-#define LWIP_PLATFORM_ERROR(message)
-#endif
-
-/* if "expression" isn't true, then print "message" and execute "handler" expression */
-#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
-  LWIP_PLATFORM_ERROR(message); handler;}} while(0)
-#endif /* LWIP_ERROR */
-
-/** Enable debug message printing, but only if debug message type is enabled
- *  AND is of correct type AND is at least LWIP_DBG_LEVEL.
- */
-#ifdef __DOXYGEN__
-#define LWIP_DEBUG
-#undef LWIP_DEBUG
-#endif
-
-#ifdef LWIP_DEBUG
-#ifndef LWIP_PLATFORM_DIAG
-#error "If you want to use LWIP_DEBUG, LWIP_PLATFORM_DIAG(message) needs to be defined in your arch/cc.h"
-#endif
-#define LWIP_DEBUGF(debug, message) do { \
-                               if ( \
-                                   ((debug) & LWIP_DBG_ON) && \
-                                   ((debug) & LWIP_DBG_TYPES_ON) && \
-                                   ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \
-                                 LWIP_PLATFORM_DIAG(message); \
-                                 if ((debug) & LWIP_DBG_HALT) { \
-                                   while(1); \
-                                 } \
-                               } \
-                             } while(0)
-
-#else  /* LWIP_DEBUG */
-#define LWIP_DEBUGF(debug, message)
-#endif /* LWIP_DEBUG */
-
-#endif /* LWIP_HDR_DEBUG_H */
diff --git a/tools/sdk/include/lwip/lwip/def.h b/tools/sdk/include/lwip/lwip/def.h
deleted file mode 100644
index 82a9d896f0f..00000000000
--- a/tools/sdk/include/lwip/lwip/def.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/**
- * @file
- * various utility macros
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_DEF_H
-#define LWIP_HDR_DEF_H
-
-/* arch.h might define NULL already */
-#include "lwip/arch.h"
-#include "lwip/opt.h"
-#if LWIP_PERF
-#include "arch/perf.h"
-#else /* LWIP_PERF */
-#define PERF_START    /* null definition */
-#define PERF_STOP(x)  /* null definition */
-#endif /* LWIP_PERF */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define LWIP_MAX(x , y)  (((x) > (y)) ? (x) : (y))
-#define LWIP_MIN(x , y)  (((x) < (y)) ? (x) : (y))
-
-/* Get the number of entries in an array ('x' must NOT be a pointer!) */
-#define LWIP_ARRAYSIZE(x) (sizeof(x)/sizeof((x)[0]))
-
-/** Create u32_t value from bytes */
-#define LWIP_MAKEU32(a,b,c,d) (((u32_t)((a) & 0xff) << 24) | \
-                               ((u32_t)((b) & 0xff) << 16) | \
-                               ((u32_t)((c) & 0xff) << 8)  | \
-                                (u32_t)((d) & 0xff))
-
-#ifndef NULL
-#ifdef __cplusplus
-#define NULL 0
-#else
-#define NULL ((void *)0)
-#endif
-#endif
-
-#if BYTE_ORDER == BIG_ENDIAN
-#define lwip_htons(x) (x)
-#define lwip_ntohs(x) (x)
-#define lwip_htonl(x) (x)
-#define lwip_ntohl(x) (x)
-#define PP_HTONS(x) (x)
-#define PP_NTOHS(x) (x)
-#define PP_HTONL(x) (x)
-#define PP_NTOHL(x) (x)
-#else /* BYTE_ORDER != BIG_ENDIAN */
-#ifndef lwip_htons
-u16_t lwip_htons(u16_t x);
-#endif
-#define lwip_ntohs(x) lwip_htons(x)
-
-#ifndef lwip_htonl
-u32_t lwip_htonl(u32_t x);
-#endif
-#define lwip_ntohl(x) lwip_htonl(x)
-
-/* These macros should be calculated by the preprocessor and are used
-   with compile-time constants only (so that there is no little-endian
-   overhead at runtime). */
-#define PP_HTONS(x) ((((x) & 0x00ffUL) << 8) | (((x) & 0xff00UL) >> 8))
-#define PP_NTOHS(x) PP_HTONS(x)
-#define PP_HTONL(x) ((((x) & 0x000000ffUL) << 24) | \
-                     (((x) & 0x0000ff00UL) <<  8) | \
-                     (((x) & 0x00ff0000UL) >>  8) | \
-                     (((x) & 0xff000000UL) >> 24))
-#define PP_NTOHL(x) PP_HTONL(x)
-#endif /* BYTE_ORDER == BIG_ENDIAN */
-
-/* Provide usual function names as macros for users, but this can be turned off */
-#ifndef LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS
-#define htons(x) lwip_htons(x)
-#define ntohs(x) lwip_ntohs(x)
-#define htonl(x) lwip_htonl(x)
-#define ntohl(x) lwip_ntohl(x)
-#endif
-
-/* Functions that are not available as standard implementations.
- * In cc.h, you can #define these to implementations available on
- * your platform to save some code bytes if you use these functions
- * in your application, too.
- */
-
-#ifndef lwip_itoa
-/* This can be #defined to itoa() or snprintf(result, bufsize, "%d", number) depending on your platform */
-void  lwip_itoa(char* result, size_t bufsize, int number);
-#endif
-#ifndef lwip_strnicmp
-/* This can be #defined to strnicmp() or strncasecmp() depending on your platform */
-int   lwip_strnicmp(const char* str1, const char* str2, size_t len);
-#endif
-#ifndef lwip_stricmp
-/* This can be #defined to stricmp() or strcasecmp() depending on your platform */
-int   lwip_stricmp(const char* str1, const char* str2);
-#endif
-#ifndef lwip_strnstr
-/* This can be #defined to strnstr() depending on your platform */
-char* lwip_strnstr(const char* buffer, const char* token, size_t n);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_DEF_H */
diff --git a/tools/sdk/include/lwip/lwip/dhcp.h b/tools/sdk/include/lwip/lwip/dhcp.h
deleted file mode 100644
index c90029b4db4..00000000000
--- a/tools/sdk/include/lwip/lwip/dhcp.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/**
- * @file
- * DHCP client API
- */
-
-/*
- * Copyright (c) 2001-2004 Leon Woestenberg <leon.woestenberg@gmx.net>
- * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Leon Woestenberg <leon.woestenberg@gmx.net>
- *
- */
-#ifndef LWIP_HDR_DHCP_H
-#define LWIP_HDR_DHCP_H
-
-#include "lwip/opt.h"
-
-#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/netif.h"
-#include "lwip/udp.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** period (in seconds) of the application calling dhcp_coarse_tmr() */
-#if ESP_DHCP
-#define DHCP_COARSE_TIMER_SECS 1
-#else
-#define DHCP_COARSE_TIMER_SECS 60
-#endif
-/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */
-#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL)
-/** period (in milliseconds) of the application calling dhcp_fine_tmr() */
-#define DHCP_FINE_TIMER_MSECS   500
-
-#define DHCP_BOOT_FILE_LEN      128U
-
-/* AutoIP cooperation flags (struct dhcp.autoip_coop_state) */
-typedef enum {
-  DHCP_AUTOIP_COOP_STATE_OFF  = 0,
-  DHCP_AUTOIP_COOP_STATE_ON   = 1
-} dhcp_autoip_coop_state_enum_t;
-
-struct dhcp
-{
-  /** transaction identifier of last sent request */
-  u32_t xid;
-  /** incoming msg */
-  struct dhcp_msg *msg_in;
-  /** track PCB allocation state */
-  u8_t pcb_allocated;
-  /** current DHCP state machine state */
-  u8_t state;
-  /** retries of current request */
-  u8_t tries;
-#if LWIP_DHCP_AUTOIP_COOP
-  u8_t autoip_coop_state;
-#endif
-  u8_t subnet_mask_given;
-
-  struct pbuf *p_out; /* pbuf of outcoming msg */
-  struct dhcp_msg *msg_out; /* outgoing msg */
-  u16_t options_out_len; /* outgoing msg options length */
-  u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */
-#if ESP_DHCP_TIMER
-  u32_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
-  u32_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
-  u32_t t1_renew_time;  /* #ticks with period DHCP_COARSE_TIMER_SECS until next renew try */
-  u32_t t2_rebind_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next rebind try */
-  u32_t lease_used; /* #ticks with period DHCP_COARSE_TIMER_SECS since last received DHCP ack */
-  u32_t t0_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for lease time */
-#else
-  u16_t t1_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */
-  u16_t t2_timeout;  /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */
-  u16_t t1_renew_time;  /* #ticks with period DHCP_COARSE_TIMER_SECS until next renew try */
-  u16_t t2_rebind_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next rebind try */
-  u16_t lease_used; /* #ticks with period DHCP_COARSE_TIMER_SECS since last received DHCP ack */
-  u16_t t0_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for lease time */
-#endif
-  ip_addr_t server_ip_addr; /* dhcp server address that offered this lease (ip_addr_t because passed to UDP) */
-  ip4_addr_t offered_ip_addr;
-  ip4_addr_t offered_sn_mask;
-  ip4_addr_t offered_gw_addr;
-
-  u32_t offered_t0_lease; /* lease period (in seconds) */
-  u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */
-  u32_t offered_t2_rebind; /* recommended rebind time (usually 87.5 of lease period)  */
-#if LWIP_DHCP_BOOTP_FILE
-  ip4_addr_t offered_si_addr;
-  char boot_file_name[DHCP_BOOT_FILE_LEN];
-#endif /* LWIP_DHCP_BOOTPFILE */
-
-  /* Espressif add start. */
-#ifdef ESP_DHCP
-  void (*cb)(struct netif*); /* callback for dhcp, add a parameter to show dhcp status if needed */
-#else
-  void (*cb)(void); /* callback for dhcp, add a parameter to show dhcp status if needed */
-#endif
-  /* Espressif add end. */
-};
-
-
-void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp);
-/** Remove a struct dhcp previously set to the netif using dhcp_set_struct() */
-#define dhcp_remove_struct(netif) netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, NULL)
-void dhcp_cleanup(struct netif *netif);
-err_t dhcp_start(struct netif *netif);
-err_t dhcp_renew(struct netif *netif);
-err_t dhcp_release(struct netif *netif);
-void dhcp_stop(struct netif *netif);
-void dhcp_inform(struct netif *netif);
-void dhcp_network_changed(struct netif *netif);
-
-/* Espressif add start. */
-/** set callback for DHCP */
-#ifdef ESP_DHCP
-void dhcp_set_cb(struct netif *netif, void (*cb)(struct netif*));
-#else
-void dhcp_set_cb(struct netif *netif, void (*cb)(void));
-#endif
-/* Espressif add end. */
-
-#if DHCP_DOES_ARP_CHECK
-void dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr);
-#endif
-u8_t dhcp_supplied_address(const struct netif *netif);
-/* to be called every minute */
-void dhcp_coarse_tmr(void);
-/* to be called every half second */
-void dhcp_fine_tmr(void);
-
-#if LWIP_DHCP_GET_NTP_SRV
-/** This function must exist, in other to add offered NTP servers to
- * the NTP (or SNTP) engine.
- * See LWIP_DHCP_MAX_NTP_SERVERS */
-extern void dhcp_set_ntp_servers(u8_t num_ntp_servers, const ip4_addr_t* ntp_server_addrs);
-#endif /* LWIP_DHCP_GET_NTP_SRV */
-
-#define netif_dhcp_data(netif) ((struct dhcp*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_DHCP */
-
-#endif /*LWIP_HDR_DHCP_H*/
diff --git a/tools/sdk/include/lwip/lwip/dhcp6.h b/tools/sdk/include/lwip/lwip/dhcp6.h
deleted file mode 100644
index 455336d37dc..00000000000
--- a/tools/sdk/include/lwip/lwip/dhcp6.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/**
- * @file
- *
- * IPv6 address autoconfiguration as per RFC 4862.
- */
-
-/*
- * Copyright (c) 2010 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- * IPv6 address autoconfiguration as per RFC 4862.
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-
-#ifndef LWIP_HDR_IP6_DHCP6_H
-#define LWIP_HDR_IP6_DHCP6_H
-
-#include "lwip/opt.h"
-
-#if LWIP_IPV6_DHCP6  /* don't build if not configured for use in lwipopts.h */
-
-
-struct dhcp6
-{
-  /*@todo: implement DHCP6*/
-};
-
-#endif /* LWIP_IPV6_DHCP6 */
-
-#endif /* LWIP_HDR_IP6_DHCP6_H */
diff --git a/tools/sdk/include/lwip/lwip/dns.h b/tools/sdk/include/lwip/lwip/dns.h
deleted file mode 100644
index 250065aab56..00000000000
--- a/tools/sdk/include/lwip/lwip/dns.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/**
- * @file
- * DNS API
- */
-
-/**
- * lwip DNS resolver header file.
-
- * Author: Jim Pettinato
- *   April 2007
-
- * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef LWIP_HDR_DNS_H
-#define LWIP_HDR_DNS_H
-
-#include "lwip/opt.h"
-
-#if LWIP_DNS
-
-#include "lwip/ip_addr.h"
-#include "lwip/err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** DNS timer period */
-#define DNS_TMR_INTERVAL          1000
-
-/* DNS resolve types: */
-#define LWIP_DNS_ADDRTYPE_IPV4      0
-#define LWIP_DNS_ADDRTYPE_IPV6      1
-#define LWIP_DNS_ADDRTYPE_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */
-#define LWIP_DNS_ADDRTYPE_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */
-#if LWIP_IPV4 && LWIP_IPV6
-#ifndef LWIP_DNS_ADDRTYPE_DEFAULT
-#define LWIP_DNS_ADDRTYPE_DEFAULT   LWIP_DNS_ADDRTYPE_IPV4_IPV6
-#endif
-#elif LWIP_IPV4
-#define LWIP_DNS_ADDRTYPE_DEFAULT   LWIP_DNS_ADDRTYPE_IPV4
-#else
-#define LWIP_DNS_ADDRTYPE_DEFAULT   LWIP_DNS_ADDRTYPE_IPV6
-#endif
-
-#if DNS_LOCAL_HOSTLIST
-/** struct used for local host-list */
-struct local_hostlist_entry {
-  /** static hostname */
-  const char *name;
-  /** static host address in network byteorder */
-  ip_addr_t addr;
-  struct local_hostlist_entry *next;
-};
-#define DNS_LOCAL_HOSTLIST_ELEM(name, addr_init) {name, addr_init, NULL}
-#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
-#ifndef DNS_LOCAL_HOSTLIST_MAX_NAMELEN
-#define DNS_LOCAL_HOSTLIST_MAX_NAMELEN  DNS_MAX_NAME_LENGTH
-#endif
-#define LOCALHOSTLIST_ELEM_SIZE ((sizeof(struct local_hostlist_entry) + DNS_LOCAL_HOSTLIST_MAX_NAMELEN + 1))
-#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
-#endif /* DNS_LOCAL_HOSTLIST */
-
-#if LWIP_IPV4
-extern const ip_addr_t dns_mquery_v4group;
-#endif /* LWIP_IPV4 */
-#if LWIP_IPV6
-extern const ip_addr_t dns_mquery_v6group;
-#endif /* LWIP_IPV6 */
-
-/** Callback which is invoked when a hostname is found.
- * A function of this type must be implemented by the application using the DNS resolver.
- * @param name pointer to the name that was looked up.
- * @param ipaddr pointer to an ip_addr_t containing the IP address of the hostname,
- *        or NULL if the name could not be found (or on any other error).
- * @param callback_arg a user-specified callback argument passed to dns_gethostbyname
-*/
-typedef void (*dns_found_callback)(const char *name, const ip_addr_t *ipaddr, void *callback_arg);
-
-void             dns_init(void);
-void             dns_tmr(void);
-void             dns_setserver(u8_t numdns, const ip_addr_t *dnsserver);
-const ip_addr_t* dns_getserver(u8_t numdns);
-err_t            dns_gethostbyname(const char *hostname, ip_addr_t *addr,
-                                   dns_found_callback found, void *callback_arg);
-err_t            dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr,
-                                   dns_found_callback found, void *callback_arg,
-                                   u8_t dns_addrtype);
-#if ESP_DNS
-void             dns_clear_servers(bool keep_fallback);
-#endif
-
-
-#if DNS_LOCAL_HOSTLIST
-size_t         dns_local_iterate(dns_found_callback iterator_fn, void *iterator_arg);
-err_t          dns_local_lookup(const char *hostname, ip_addr_t *addr, u8_t dns_addrtype);
-#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC
-int            dns_local_removehost(const char *hostname, const ip_addr_t *addr);
-err_t          dns_local_addhost(const char *hostname, const ip_addr_t *addr);
-#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
-#endif /* DNS_LOCAL_HOSTLIST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_DNS */
-
-#endif /* LWIP_HDR_DNS_H */
diff --git a/tools/sdk/include/lwip/lwip/err.h b/tools/sdk/include/lwip/lwip/err.h
deleted file mode 100644
index 84e528d1ed8..00000000000
--- a/tools/sdk/include/lwip/lwip/err.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/**
- * @file
- * lwIP Error codes
- */
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_ERR_H
-#define LWIP_HDR_ERR_H
-
-#include "lwip/opt.h"
-#include "lwip/arch.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup infrastructure_errors Error codes
- * @ingroup infrastructure
- * @{
- */
-
-/** Define LWIP_ERR_T in cc.h if you want to use
- *  a different type for your platform (must be signed). */
-#ifdef LWIP_ERR_T
-typedef LWIP_ERR_T err_t;
-#else /* LWIP_ERR_T */
-typedef s8_t err_t;
-#endif /* LWIP_ERR_T*/
-
-/** Definitions for error constants. */
-typedef enum {
-/** No error, everything OK. */
-  ERR_OK         = 0,
-/** Out of memory error.     */
-  ERR_MEM        = -1,
-/** Buffer error.            */
-  ERR_BUF        = -2,
-/** Timeout.                 */
-  ERR_TIMEOUT    = -3,
-/** Routing problem.         */
-  ERR_RTE        = -4,
-/** Operation in progress    */
-  ERR_INPROGRESS = -5,
-/** Illegal value.           */
-  ERR_VAL        = -6,
-/** Operation would block.   */
-  ERR_WOULDBLOCK = -7,
-/** Address in use.          */
-  ERR_USE        = -8,
-/** Already connecting.      */
-  ERR_ALREADY    = -9,
-/** Conn already established.*/
-  ERR_ISCONN     = -10,
-/** Not connected.           */
-  ERR_CONN       = -11,
-/** Low-level netif error    */
-  ERR_IF         = -12,
-
-/** Connection aborted.      */
-  ERR_ABRT       = -13,
-/** Connection reset.        */
-  ERR_RST        = -14,
-/** Connection closed.       */
-  ERR_CLSD       = -15,
-/** Illegal argument.        */
-  ERR_ARG        = -16
-} err_enum_t;
-
-#define ERR_IS_FATAL(e) ((e) <= ERR_ABRT)
-
-/**
- * @}
- */
-
-#ifdef LWIP_DEBUG
-extern const char *lwip_strerr(err_t err);
-#else
-#define lwip_strerr(x) ""
-#endif /* LWIP_DEBUG */
-
-#if !NO_SYS
-int err_to_errno(err_t err);
-#endif /* !NO_SYS */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_ERR_H */
diff --git a/tools/sdk/include/lwip/lwip/errno.h b/tools/sdk/include/lwip/lwip/errno.h
deleted file mode 100644
index 641cffb09cc..00000000000
--- a/tools/sdk/include/lwip/lwip/errno.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/**
- * @file
- * Posix Errno defines
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_ERRNO_H
-#define LWIP_HDR_ERRNO_H
-
-#include "lwip/opt.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef LWIP_PROVIDE_ERRNO
-
-#define  EPERM            1  /* Operation not permitted */
-#define  ENOENT           2  /* No such file or directory */
-#define  ESRCH            3  /* No such process */
-#define  EINTR            4  /* Interrupted system call */
-#define  EIO              5  /* I/O error */
-#define  ENXIO            6  /* No such device or address */
-#define  E2BIG            7  /* Arg list too long */
-#define  ENOEXEC          8  /* Exec format error */
-#define  EBADF            9  /* Bad file number */
-#define  ECHILD          10  /* No child processes */
-#define  EAGAIN          11  /* Try again */
-#define  ENOMEM          12  /* Out of memory */
-#define  EACCES          13  /* Permission denied */
-#define  EFAULT          14  /* Bad address */
-#define  ENOTBLK         15  /* Block device required */
-#define  EBUSY           16  /* Device or resource busy */
-#define  EEXIST          17  /* File exists */
-#define  EXDEV           18  /* Cross-device link */
-#define  ENODEV          19  /* No such device */
-#define  ENOTDIR         20  /* Not a directory */
-#define  EISDIR          21  /* Is a directory */
-#define  EINVAL          22  /* Invalid argument */
-#define  ENFILE          23  /* File table overflow */
-#define  EMFILE          24  /* Too many open files */
-#define  ENOTTY          25  /* Not a typewriter */
-#define  ETXTBSY         26  /* Text file busy */
-#define  EFBIG           27  /* File too large */
-#define  ENOSPC          28  /* No space left on device */
-#define  ESPIPE          29  /* Illegal seek */
-#define  EROFS           30  /* Read-only file system */
-#define  EMLINK          31  /* Too many links */
-#define  EPIPE           32  /* Broken pipe */
-#define  EDOM            33  /* Math argument out of domain of func */
-#define  ERANGE          34  /* Math result not representable */
-#define  EDEADLK         35  /* Resource deadlock would occur */
-#define  ENAMETOOLONG    36  /* File name too long */
-#define  ENOLCK          37  /* No record locks available */
-#define  ENOSYS          38  /* Function not implemented */
-#define  ENOTEMPTY       39  /* Directory not empty */
-#define  ELOOP           40  /* Too many symbolic links encountered */
-#define  EWOULDBLOCK     EAGAIN  /* Operation would block */
-#define  ENOMSG          42  /* No message of desired type */
-#define  EIDRM           43  /* Identifier removed */
-#define  ECHRNG          44  /* Channel number out of range */
-#define  EL2NSYNC        45  /* Level 2 not synchronized */
-#define  EL3HLT          46  /* Level 3 halted */
-#define  EL3RST          47  /* Level 3 reset */
-#define  ELNRNG          48  /* Link number out of range */
-#define  EUNATCH         49  /* Protocol driver not attached */
-#define  ENOCSI          50  /* No CSI structure available */
-#define  EL2HLT          51  /* Level 2 halted */
-#define  EBADE           52  /* Invalid exchange */
-#define  EBADR           53  /* Invalid request descriptor */
-#define  EXFULL          54  /* Exchange full */
-#define  ENOANO          55  /* No anode */
-#define  EBADRQC         56  /* Invalid request code */
-#define  EBADSLT         57  /* Invalid slot */
-
-#define  EDEADLOCK       EDEADLK
-
-#define  EBFONT          59  /* Bad font file format */
-#define  ENOSTR          60  /* Device not a stream */
-#define  ENODATA         61  /* No data available */
-#define  ETIME           62  /* Timer expired */
-#define  ENOSR           63  /* Out of streams resources */
-#define  ENONET          64  /* Machine is not on the network */
-#define  ENOPKG          65  /* Package not installed */
-#define  EREMOTE         66  /* Object is remote */
-#define  ENOLINK         67  /* Link has been severed */
-#define  EADV            68  /* Advertise error */
-#define  ESRMNT          69  /* Srmount error */
-#define  ECOMM           70  /* Communication error on send */
-#define  EPROTO          71  /* Protocol error */
-#define  EMULTIHOP       72  /* Multihop attempted */
-#define  EDOTDOT         73  /* RFS specific error */
-#define  EBADMSG         74  /* Not a data message */
-#define  EOVERFLOW       75  /* Value too large for defined data type */
-#define  ENOTUNIQ        76  /* Name not unique on network */
-#define  EBADFD          77  /* File descriptor in bad state */
-#define  EREMCHG         78  /* Remote address changed */
-#define  ELIBACC         79  /* Can not access a needed shared library */
-#define  ELIBBAD         80  /* Accessing a corrupted shared library */
-#define  ELIBSCN         81  /* .lib section in a.out corrupted */
-#define  ELIBMAX         82  /* Attempting to link in too many shared libraries */
-#define  ELIBEXEC        83  /* Cannot exec a shared library directly */
-#define  EILSEQ          84  /* Illegal byte sequence */
-#define  ERESTART        85  /* Interrupted system call should be restarted */
-#define  ESTRPIPE        86  /* Streams pipe error */
-#define  EUSERS          87  /* Too many users */
-#define  ENOTSOCK        88  /* Socket operation on non-socket */
-#define  EDESTADDRREQ    89  /* Destination address required */
-#define  EMSGSIZE        90  /* Message too long */
-#define  EPROTOTYPE      91  /* Protocol wrong type for socket */
-#define  ENOPROTOOPT     92  /* Protocol not available */
-#define  EPROTONOSUPPORT 93  /* Protocol not supported */
-#define  ESOCKTNOSUPPORT 94  /* Socket type not supported */
-#define  EOPNOTSUPP      95  /* Operation not supported on transport endpoint */
-#define  EPFNOSUPPORT    96  /* Protocol family not supported */
-#define  EAFNOSUPPORT    97  /* Address family not supported by protocol */
-#define  EADDRINUSE      98  /* Address already in use */
-#define  EADDRNOTAVAIL   99  /* Cannot assign requested address */
-#define  ENETDOWN       100  /* Network is down */
-#define  ENETUNREACH    101  /* Network is unreachable */
-#define  ENETRESET      102  /* Network dropped connection because of reset */
-#define  ECONNABORTED   103  /* Software caused connection abort */
-#define  ECONNRESET     104  /* Connection reset by peer */
-#define  ENOBUFS        105  /* No buffer space available */
-#define  EISCONN        106  /* Transport endpoint is already connected */
-#define  ENOTCONN       107  /* Transport endpoint is not connected */
-#define  ESHUTDOWN      108  /* Cannot send after transport endpoint shutdown */
-#define  ETOOMANYREFS   109  /* Too many references: cannot splice */
-#define  ETIMEDOUT      110  /* Connection timed out */
-#define  ECONNREFUSED   111  /* Connection refused */
-#define  EHOSTDOWN      112  /* Host is down */
-#define  EHOSTUNREACH   113  /* No route to host */
-#define  EALREADY       114  /* Operation already in progress */
-#define  EINPROGRESS    115  /* Operation now in progress */
-#define  ESTALE         116  /* Stale NFS file handle */
-#define  EUCLEAN        117  /* Structure needs cleaning */
-#define  ENOTNAM        118  /* Not a XENIX named type file */
-#define  ENAVAIL        119  /* No XENIX semaphores available */
-#define  EISNAM         120  /* Is a named type file */
-#define  EREMOTEIO      121  /* Remote I/O error */
-#define  EDQUOT         122  /* Quota exceeded */
-
-#define  ENOMEDIUM      123  /* No medium found */
-#define  EMEDIUMTYPE    124  /* Wrong medium type */
-
-#ifndef errno
-extern int errno;
-#endif
-
-#else /* LWIP_PROVIDE_ERRNO */
-
-/* Define LWIP_ERRNO_INCLUDE to <errno.h> to include the error defines here */
-#ifdef LWIP_ERRNO_INCLUDE
-#include LWIP_ERRNO_INCLUDE
-#endif /* LWIP_ERRNO_INCLUDE */
-
-#endif /* LWIP_PROVIDE_ERRNO */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_ERRNO_H */
diff --git a/tools/sdk/include/lwip/lwip/etharp.h b/tools/sdk/include/lwip/lwip/etharp.h
deleted file mode 100644
index 0662f07241e..00000000000
--- a/tools/sdk/include/lwip/lwip/etharp.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/**
- * @file
- * Ethernet output function - handles OUTGOING ethernet level traffic, implements
- * ARP resolving.
- * To be used in most low-level netif implementations
- */
-
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * Copyright (c) 2003-2004 Leon Woestenberg <leon.woestenberg@axon.tv>
- * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-#ifndef LWIP_HDR_NETIF_ETHARP_H
-#define LWIP_HDR_NETIF_ETHARP_H
-
-#include "lwip/opt.h"
-
-#if LWIP_ARP || LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/pbuf.h"
-#include "lwip/ip4_addr.h"
-#include "lwip/netif.h"
-#include "lwip/ip4.h"
-#include "lwip/prot/ethernet.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_IPV4 && LWIP_ARP /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/prot/etharp.h"
-
-/** 1 seconds period */
-#define ARP_TMR_INTERVAL 1000
-
-#if ARP_QUEUEING
-/** struct for queueing outgoing packets for unknown address
-  * defined here to be accessed by memp.h
-  */
-struct etharp_q_entry {
-  struct etharp_q_entry *next;
-  struct pbuf *p;
-};
-#endif /* ARP_QUEUEING */
-
-#if ESP_GRATUITOUS_ARP
-#ifdef CONFIG_GARP_TMR_INTERVAL
-#define GARP_TMR_INTERVAL (CONFIG_GARP_TMR_INTERVAL*1000UL)
-#else
-#define GARP_TMR_INTERVAL 60000 
-#endif
-
-void garp_tmr(void);
-#endif
-
-#define etharp_init() /* Compatibility define, no init needed. */
-void etharp_tmr(void);
-s8_t etharp_find_addr(struct netif *netif, const ip4_addr_t *ipaddr,
-         struct eth_addr **eth_ret, const ip4_addr_t **ip_ret);
-u8_t etharp_get_entry(u8_t i, ip4_addr_t **ipaddr, struct netif **netif, struct eth_addr **eth_ret);
-err_t etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
-err_t etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q);
-err_t etharp_request(struct netif *netif, const ip4_addr_t *ipaddr);
-/** For Ethernet network interfaces, we might want to send "gratuitous ARP";
- *  this is an ARP packet sent by a node in order to spontaneously cause other
- *  nodes to update an entry in their ARP cache.
- *  From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */
-#define etharp_gratuitous(netif) etharp_request((netif), netif_ip4_addr(netif))
-void etharp_cleanup_netif(struct netif *netif);
-
-#if ETHARP_SUPPORT_STATIC_ENTRIES
-err_t etharp_add_static_entry(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr);
-err_t etharp_remove_static_entry(const ip4_addr_t *ipaddr);
-#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
-
-#endif /* LWIP_IPV4 && LWIP_ARP */
-
-void etharp_input(struct pbuf *p, struct netif *netif);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_ARP || LWIP_ETHERNET */
-
-#endif /* LWIP_HDR_NETIF_ETHARP_H */
diff --git a/tools/sdk/include/lwip/lwip/ethip6.h b/tools/sdk/include/lwip/lwip/ethip6.h
deleted file mode 100644
index 5e88dffd05f..00000000000
--- a/tools/sdk/include/lwip/lwip/ethip6.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/**
- * @file
- *
- * Ethernet output for IPv6. Uses ND tables for link-layer addressing.
- */
-
-/*
- * Copyright (c) 2010 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-
-#ifndef LWIP_HDR_ETHIP6_H
-#define LWIP_HDR_ETHIP6_H
-
-#include "lwip/opt.h"
-
-#if LWIP_IPV6 && LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/pbuf.h"
-#include "lwip/ip6.h"
-#include "lwip/ip6_addr.h"
-#include "lwip/netif.h"
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-err_t ethip6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV6 && LWIP_ETHERNET */
-
-#endif /* LWIP_HDR_ETHIP6_H */
diff --git a/tools/sdk/include/lwip/lwip/icmp.h b/tools/sdk/include/lwip/lwip/icmp.h
deleted file mode 100644
index f5a31fd4c07..00000000000
--- a/tools/sdk/include/lwip/lwip/icmp.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/**
- * @file
- * ICMP API
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_ICMP_H
-#define LWIP_HDR_ICMP_H
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/prot/icmp.h"
-
-#if LWIP_IPV6 && LWIP_ICMP6
-#include "lwip/icmp6.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ICMP destination unreachable codes */
-enum icmp_dur_type {
-  /** net unreachable */
-  ICMP_DUR_NET   = 0,
-  /** host unreachable */
-  ICMP_DUR_HOST  = 1,
-  /** protocol unreachable */
-  ICMP_DUR_PROTO = 2,
-  /** port unreachable */
-  ICMP_DUR_PORT  = 3,
-  /** fragmentation needed and DF set */
-  ICMP_DUR_FRAG  = 4,
-  /** source route failed */
-  ICMP_DUR_SR    = 5
-};
-
-/** ICMP time exceeded codes */
-enum icmp_te_type {
-  /** time to live exceeded in transit */
-  ICMP_TE_TTL  = 0,
-  /** fragment reassembly time exceeded */
-  ICMP_TE_FRAG = 1
-};
-
-#if LWIP_IPV4 && LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
-
-void icmp_input(struct pbuf *p, struct netif *inp);
-void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
-void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
-
-#endif /* LWIP_IPV4 && LWIP_ICMP */
-
-#if LWIP_IPV4 && LWIP_IPV6
-#if LWIP_ICMP && LWIP_ICMP6
-#define icmp_port_unreach(isipv6, pbuf) ((isipv6) ? \
-                                         icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT) : \
-                                         icmp_dest_unreach(pbuf, ICMP_DUR_PORT))
-#elif LWIP_ICMP
-#define icmp_port_unreach(isipv6, pbuf) do{ if(!(isipv6)) { icmp_dest_unreach(pbuf, ICMP_DUR_PORT);}}while(0)
-#elif LWIP_ICMP6
-#define icmp_port_unreach(isipv6, pbuf) do{ if(isipv6) { icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT);}}while(0)
-#else
-#define icmp_port_unreach(isipv6, pbuf)
-#endif
-#elif LWIP_IPV6 && LWIP_ICMP6
-#define icmp_port_unreach(isipv6, pbuf) icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT)
-#elif LWIP_IPV4 && LWIP_ICMP
-#define icmp_port_unreach(isipv6, pbuf) icmp_dest_unreach(pbuf, ICMP_DUR_PORT)
-#else /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) */
-#define icmp_port_unreach(isipv6, pbuf)
-#endif /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) LWIP_IPV4*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_ICMP_H */
diff --git a/tools/sdk/include/lwip/lwip/icmp6.h b/tools/sdk/include/lwip/lwip/icmp6.h
deleted file mode 100644
index a29dc8c1c23..00000000000
--- a/tools/sdk/include/lwip/lwip/icmp6.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/**
- * @file
- *
- * IPv6 version of ICMP, as per RFC 4443.
- */
-
-/*
- * Copyright (c) 2010 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-#ifndef LWIP_HDR_ICMP6_H
-#define LWIP_HDR_ICMP6_H
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip6_addr.h"
-#include "lwip/netif.h"
-#include "lwip/prot/icmp6.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_ICMP6 && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */
-
-void icmp6_input(struct pbuf *p, struct netif *inp);
-void icmp6_dest_unreach(struct pbuf *p, enum icmp6_dur_code c);
-void icmp6_packet_too_big(struct pbuf *p, u32_t mtu);
-void icmp6_time_exceeded(struct pbuf *p, enum icmp6_te_code c);
-void icmp6_param_problem(struct pbuf *p, enum icmp6_pp_code c, u32_t pointer);
-
-#endif /* LWIP_ICMP6 && LWIP_IPV6 */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* LWIP_HDR_ICMP6_H */
diff --git a/tools/sdk/include/lwip/lwip/igmp.h b/tools/sdk/include/lwip/lwip/igmp.h
deleted file mode 100644
index ffd80e680c3..00000000000
--- a/tools/sdk/include/lwip/lwip/igmp.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/**
- * @file
- * IGMP API
- */
-
-/*
- * Copyright (c) 2002 CITEL Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS''
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * This file is a contribution to the lwIP TCP/IP stack.
- * The Swedish Institute of Computer Science and Adam Dunkels
- * are specifically granted permission to redistribute this
- * source code.
-*/
-
-#ifndef LWIP_HDR_IGMP_H
-#define LWIP_HDR_IGMP_H
-
-#include "lwip/opt.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-#include "lwip/pbuf.h"
-
-#if LWIP_IPV4 && LWIP_IGMP /* don't build if not configured for use in lwipopts.h */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* IGMP timer */
-#define IGMP_TMR_INTERVAL              100 /* Milliseconds */
-#define IGMP_V1_DELAYING_MEMBER_TMR   (1000/IGMP_TMR_INTERVAL)
-#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL)
-
-/* Compatibility defines (don't use for new code) */
-#define IGMP_DEL_MAC_FILTER            NETIF_DEL_MAC_FILTER
-#define IGMP_ADD_MAC_FILTER            NETIF_ADD_MAC_FILTER
-
-/**
- * igmp group structure - there is
- * a list of groups for each interface
- * these should really be linked from the interface, but
- * if we keep them separate we will not affect the lwip original code
- * too much
- *
- * There will be a group for the all systems group address but this
- * will not run the state machine as it is used to kick off reports
- * from all the other groups
- */
-struct igmp_group {
-  /** next link */
-  struct igmp_group *next;
-  /** multicast address */
-  ip4_addr_t         group_address;
-  /** signifies we were the last person to report */
-  u8_t               last_reporter_flag;
-  /** current state of the group */
-  u8_t               group_state;
-  /** timer for reporting, negative is OFF */
-  u16_t              timer;
-  /** counter of simultaneous uses */
-  u8_t               use;
-};
-
-/*  Prototypes */
-void   igmp_init(void);
-err_t  igmp_start(struct netif *netif);
-err_t  igmp_stop(struct netif *netif);
-void   igmp_report_groups(struct netif *netif);
-struct igmp_group *igmp_lookfor_group(struct netif *ifp, const ip4_addr_t *addr);
-void   igmp_input(struct pbuf *p, struct netif *inp, const ip4_addr_t *dest);
-err_t  igmp_joingroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr);
-err_t  igmp_joingroup_netif(struct netif *netif, const ip4_addr_t *groupaddr);
-err_t  igmp_leavegroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr);
-err_t  igmp_leavegroup_netif(struct netif *netif, const ip4_addr_t *groupaddr);
-void   igmp_tmr(void);
-
-/** @ingroup igmp 
- * Get list head of IGMP groups for netif.
- * Note: The allsystems group IP is contained in the list as first entry.
- * @see @ref netif_set_igmp_mac_filter()
- */
-#define netif_igmp_data(netif) ((struct igmp_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV4 && LWIP_IGMP */
-
-#endif /* LWIP_HDR_IGMP_H */
diff --git a/tools/sdk/include/lwip/lwip/inet.h b/tools/sdk/include/lwip/lwip/inet.h
deleted file mode 100644
index 4a34f026533..00000000000
--- a/tools/sdk/include/lwip/lwip/inet.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/**
- * @file
- * This file (together with sockets.h) aims to provide structs and functions from
- * - arpa/inet.h
- * - netinet/in.h
- *
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_INET_H
-#define LWIP_HDR_INET_H
-
-#include "lwip/opt.h"
-#include "lwip/def.h"
-#include "lwip/ip_addr.h"
-#include "lwip/ip6_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* If your port already typedef's in_addr_t, define IN_ADDR_T_DEFINED
-   to prevent this code from redefining it. */
-#if !defined(in_addr_t) && !defined(IN_ADDR_T_DEFINED)
-typedef u32_t in_addr_t;
-#endif
-
-struct in_addr {
-  in_addr_t s_addr;
-};
-
-struct in6_addr {
-  union {
-    u32_t u32_addr[4];
-    u8_t  u8_addr[16];
-  } un;
-#define s6_addr  un.u8_addr
-};
-
-/** 255.255.255.255 */
-#define INADDR_NONE         IPADDR_NONE
-/** 127.0.0.1 */
-#define INADDR_LOOPBACK     IPADDR_LOOPBACK
-/** 0.0.0.0 */
-#define INADDR_ANY          IPADDR_ANY
-/** 255.255.255.255 */
-#define INADDR_BROADCAST    IPADDR_BROADCAST
-
-/** This macro can be used to initialize a variable of type struct in6_addr
-    to the IPv6 wildcard address. */
-#define IN6ADDR_ANY_INIT {{{0,0,0,0}}}
-/** This macro can be used to initialize a variable of type struct in6_addr
-    to the IPv6 loopback address. */
-#define IN6ADDR_LOOPBACK_INIT {{{0,0,0,PP_HTONL(1)}}}
-/** This variable is initialized by the system to contain the wildcard IPv6 address. */
-extern const struct in6_addr in6addr_any;
-
-/* Definitions of the bits in an (IPv4) Internet address integer.
-
-   On subnets, host and network parts are found according to
-   the subnet mask, not these masks.  */
-#define IN_CLASSA(a)        IP_CLASSA(a)
-#define IN_CLASSA_NET       IP_CLASSA_NET
-#define IN_CLASSA_NSHIFT    IP_CLASSA_NSHIFT
-#define IN_CLASSA_HOST      IP_CLASSA_HOST
-#define IN_CLASSA_MAX       IP_CLASSA_MAX
-
-#define IN_CLASSB(b)        IP_CLASSB(b)
-#define IN_CLASSB_NET       IP_CLASSB_NET
-#define IN_CLASSB_NSHIFT    IP_CLASSB_NSHIFT
-#define IN_CLASSB_HOST      IP_CLASSB_HOST
-#define IN_CLASSB_MAX       IP_CLASSB_MAX
-
-#define IN_CLASSC(c)        IP_CLASSC(c)
-#define IN_CLASSC_NET       IP_CLASSC_NET
-#define IN_CLASSC_NSHIFT    IP_CLASSC_NSHIFT
-#define IN_CLASSC_HOST      IP_CLASSC_HOST
-#define IN_CLASSC_MAX       IP_CLASSC_MAX
-
-#define IN_CLASSD(d)        IP_CLASSD(d)
-#define IN_CLASSD_NET       IP_CLASSD_NET     /* These ones aren't really */
-#define IN_CLASSD_NSHIFT    IP_CLASSD_NSHIFT  /*   net and host fields, but */
-#define IN_CLASSD_HOST      IP_CLASSD_HOST    /*   routing needn't know. */
-#define IN_CLASSD_MAX       IP_CLASSD_MAX
-
-#define IN_MULTICAST(a)     IP_MULTICAST(a)
-
-#define IN_EXPERIMENTAL(a)  IP_EXPERIMENTAL(a)
-#define IN_BADCLASS(a)      IP_BADCLASS(a)
-
-#define IN_LOOPBACKNET      IP_LOOPBACKNET
-
-
-#ifndef INET_ADDRSTRLEN
-#define INET_ADDRSTRLEN     IP4ADDR_STRLEN_MAX
-#endif
-#if LWIP_IPV6
-#ifndef INET6_ADDRSTRLEN
-#define INET6_ADDRSTRLEN    IP6ADDR_STRLEN_MAX
-#endif
-#endif
-
-#if LWIP_IPV4
-
-#define inet_addr_from_ip4addr(target_inaddr, source_ipaddr) ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr))
-#define inet_addr_to_ip4addr(target_ipaddr, source_inaddr)   (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr))
-/* ATTENTION: the next define only works because both s_addr and ip4_addr_t are an u32_t effectively! */
-#define inet_addr_to_ip4addr_p(target_ip4addr_p, source_inaddr)   ((target_ip4addr_p) = (ip4_addr_t*)&((source_inaddr)->s_addr))
-
-/* directly map this to the lwip internal functions */
-#define inet_addr(cp)                   ipaddr_addr(cp)
-#define inet_aton(cp, addr)             ip4addr_aton(cp, (ip4_addr_t*)addr)
-#define inet_ntoa(addr)                 ip4addr_ntoa((const ip4_addr_t*)&(addr))
-#define inet_ntoa_r(addr, buf, buflen)  ip4addr_ntoa_r((const ip4_addr_t*)&(addr), buf, buflen)
-
-#endif /* LWIP_IPV4 */
-
-#if LWIP_IPV6
-#define inet6_addr_from_ip6addr(target_in6addr, source_ip6addr) {(target_in6addr)->un.u32_addr[0] = (source_ip6addr)->addr[0]; \
-                                                                 (target_in6addr)->un.u32_addr[1] = (source_ip6addr)->addr[1]; \
-                                                                 (target_in6addr)->un.u32_addr[2] = (source_ip6addr)->addr[2]; \
-                                                                 (target_in6addr)->un.u32_addr[3] = (source_ip6addr)->addr[3];}
-#define inet6_addr_to_ip6addr(target_ip6addr, source_in6addr)   {(target_ip6addr)->addr[0] = (source_in6addr)->un.u32_addr[0]; \
-                                                                 (target_ip6addr)->addr[1] = (source_in6addr)->un.u32_addr[1]; \
-                                                                 (target_ip6addr)->addr[2] = (source_in6addr)->un.u32_addr[2]; \
-                                                                 (target_ip6addr)->addr[3] = (source_in6addr)->un.u32_addr[3];}
-/* ATTENTION: the next define only works because both in6_addr and ip6_addr_t are an u32_t[4] effectively! */
-#define inet6_addr_to_ip6addr_p(target_ip6addr_p, source_in6addr)   ((target_ip6addr_p) = (ip6_addr_t*)(source_in6addr))
-
-/* directly map this to the lwip internal functions */
-#define inet6_aton(cp, addr)            ip6addr_aton(cp, (ip6_addr_t*)addr)
-#define inet6_ntoa(addr)                ip6addr_ntoa((const ip6_addr_t*)&(addr))
-#define inet6_ntoa_r(addr, buf, buflen) ip6addr_ntoa_r((const ip6_addr_t*)&(addr), buf, buflen)
-
-#endif /* LWIP_IPV6 */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_INET_H */
diff --git a/tools/sdk/include/lwip/lwip/inet_chksum.h b/tools/sdk/include/lwip/lwip/inet_chksum.h
deleted file mode 100644
index 4e23d7f1944..00000000000
--- a/tools/sdk/include/lwip/lwip/inet_chksum.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- * @file
- * IP checksum calculation functions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_INET_CHKSUM_H
-#define LWIP_HDR_INET_CHKSUM_H
-
-#include "lwip/opt.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-
-/** Swap the bytes in an u16_t: much like lwip_htons() for little-endian */
-#ifndef SWAP_BYTES_IN_WORD
-#define SWAP_BYTES_IN_WORD(w) (((w) & 0xff) << 8) | (((w) & 0xff00) >> 8)
-#endif /* SWAP_BYTES_IN_WORD */
-
-/** Split an u32_t in two u16_ts and add them up */
-#ifndef FOLD_U32T
-#define FOLD_U32T(u)          (((u) >> 16) + ((u) & 0x0000ffffUL))
-#endif
-
-#if LWIP_CHECKSUM_ON_COPY
-/** Function-like macro: same as MEMCPY but returns the checksum of copied data
-    as u16_t */
-# ifndef LWIP_CHKSUM_COPY
-#  define LWIP_CHKSUM_COPY(dst, src, len) lwip_chksum_copy(dst, src, len)
-#  ifndef LWIP_CHKSUM_COPY_ALGORITHM
-#   define LWIP_CHKSUM_COPY_ALGORITHM 1
-#  endif /* LWIP_CHKSUM_COPY_ALGORITHM */
-# else /* LWIP_CHKSUM_COPY */
-#  define LWIP_CHKSUM_COPY_ALGORITHM 0
-# endif /* LWIP_CHKSUM_COPY */
-#else /* LWIP_CHECKSUM_ON_COPY */
-# define LWIP_CHKSUM_COPY_ALGORITHM 0
-#endif /* LWIP_CHECKSUM_ON_COPY */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-u16_t inet_chksum(const void *dataptr, u16_t len);
-u16_t inet_chksum_pbuf(struct pbuf *p);
-#if LWIP_CHKSUM_COPY_ALGORITHM
-u16_t lwip_chksum_copy(void *dst, const void *src, u16_t len);
-#endif /* LWIP_CHKSUM_COPY_ALGORITHM */
-
-#if LWIP_IPV4
-u16_t inet_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
-       const ip4_addr_t *src, const ip4_addr_t *dest);
-u16_t inet_chksum_pseudo_partial(struct pbuf *p, u8_t proto,
-       u16_t proto_len, u16_t chksum_len, const ip4_addr_t *src, const ip4_addr_t *dest);
-#endif /* LWIP_IPV4 */
-
-#if LWIP_IPV6
-u16_t ip6_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
-       const ip6_addr_t *src, const ip6_addr_t *dest);
-u16_t ip6_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
-       u16_t chksum_len, const ip6_addr_t *src, const ip6_addr_t *dest);
-#endif /* LWIP_IPV6 */
-
-
-u16_t ip_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len,
-       const ip_addr_t *src, const ip_addr_t *dest);
-u16_t ip_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len,
-       u16_t chksum_len, const ip_addr_t *src, const ip_addr_t *dest);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_INET_H */
-
diff --git a/tools/sdk/include/lwip/lwip/init.h b/tools/sdk/include/lwip/lwip/init.h
deleted file mode 100644
index 3c234cb58de..00000000000
--- a/tools/sdk/include/lwip/lwip/init.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/**
- * @file
- * lwIP initialization API
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_INIT_H
-#define LWIP_HDR_INIT_H
-
-#include "lwip/opt.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup lwip_version Version
- * @ingroup lwip
- * @{
- */
-
-/** X.x.x: Major version of the stack */
-#define LWIP_VERSION_MAJOR      2
-/** x.X.x: Minor version of the stack */
-#define LWIP_VERSION_MINOR      0
-/** x.x.X: Revision of the stack */
-#define LWIP_VERSION_REVISION   3
-/** For release candidates, this is set to 1..254
-  * For official releases, this is set to 255 (LWIP_RC_RELEASE)
-  * For development versions (Git), this is set to 0 (LWIP_RC_DEVELOPMENT) */
-#define LWIP_VERSION_RC         LWIP_RC_RELEASE
-
-/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */
-#define LWIP_RC_RELEASE         255
-/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for Git versions */
-#define LWIP_RC_DEVELOPMENT     0
-
-#define LWIP_VERSION_IS_RELEASE     (LWIP_VERSION_RC == LWIP_RC_RELEASE)
-#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT)
-#define LWIP_VERSION_IS_RC          ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT))
-
-/* Some helper defines to get a version string */
-#define LWIP_VERSTR2(x) #x
-#define LWIP_VERSTR(x) LWIP_VERSTR2(x)
-#if LWIP_VERSION_IS_RELEASE
-#define LWIP_VERSION_STRING_SUFFIX ""
-#elif LWIP_VERSION_IS_DEVELOPMENT
-#define LWIP_VERSION_STRING_SUFFIX "d"
-#else
-#define LWIP_VERSION_STRING_SUFFIX "rc" LWIP_VERSTR(LWIP_VERSION_RC)
-#endif
-
-/** Provides the version of the stack */
-#define LWIP_VERSION   (((u32_t)LWIP_VERSION_MAJOR) << 24   | ((u32_t)LWIP_VERSION_MINOR) << 16 | \
-                        ((u32_t)LWIP_VERSION_REVISION) << 8 | ((u32_t)LWIP_VERSION_RC))
-/** Provides the version of the stack as string */
-#define LWIP_VERSION_STRING     LWIP_VERSTR(LWIP_VERSION_MAJOR) "." LWIP_VERSTR(LWIP_VERSION_MINOR) "." LWIP_VERSTR(LWIP_VERSION_REVISION) LWIP_VERSION_STRING_SUFFIX
-
-/**
- * @}
- */
-
-/* Modules initialization */
-void lwip_init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_INIT_H */
diff --git a/tools/sdk/include/lwip/lwip/ip.h b/tools/sdk/include/lwip/lwip/ip.h
deleted file mode 100644
index 0673be9b4a8..00000000000
--- a/tools/sdk/include/lwip/lwip/ip.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/**
- * @file
- * IP API
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_IP_H
-#define LWIP_HDR_IP_H
-
-#include "lwip/opt.h"
-
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-#include "lwip/err.h"
-#include "lwip/netif.h"
-#include "lwip/ip4.h"
-#include "lwip/ip6.h"
-#include "lwip/prot/ip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* This is passed as the destination address to ip_output_if (not
-   to ip_output), meaning that an IP header already is constructed
-   in the pbuf. This is used when TCP retransmits. */
-#define LWIP_IP_HDRINCL  NULL
-
-/** pbufs passed to IP must have a ref-count of 1 as their payload pointer
-    gets altered as the packet is passed down the stack */
-#ifndef LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX
-#define LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p) LWIP_ASSERT("p->ref == 1", (p)->ref == 1)
-#endif
-
-#if LWIP_NETIF_HWADDRHINT
-#define IP_PCB_ADDRHINT ;u8_t addr_hint
-#else
-#define IP_PCB_ADDRHINT
-#endif /* LWIP_NETIF_HWADDRHINT */
-
-/** This is the common part of all PCB types. It needs to be at the
-   beginning of a PCB type definition. It is located here so that
-   changes to this common part are made in one location instead of
-   having to change all PCB structs. */
-#define IP_PCB \
-  /* ip addresses in network byte order */ \
-  ip_addr_t local_ip; \
-  ip_addr_t remote_ip; \
-   /* Socket options */  \
-  u8_t so_options;      \
-   /* Type Of Service */ \
-  u8_t tos;              \
-  /* Time To Live */     \
-  u8_t ttl               \
-  /* link layer address resolution hint */ \
-  IP_PCB_ADDRHINT
-
-struct ip_pcb {
-/* Common members of all PCB types */
-  IP_PCB;
-};
-
-/*
- * Option flags per-socket. These are the same like SO_XXX in sockets.h
- */
-#define SOF_REUSEADDR     0x04U  /* allow local address reuse */
-#define SOF_KEEPALIVE     0x08U  /* keep connections alive */
-#define SOF_BROADCAST     0x20U  /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
-
-/* These flags are inherited (e.g. from a listen-pcb to a connection-pcb): */
-#define SOF_INHERITED   (SOF_REUSEADDR|SOF_KEEPALIVE)
-
-/** Global variables of this module, kept in a struct for efficient access using base+index. */
-struct ip_globals
-{
-  /** The interface that accepted the packet for the current callback invocation. */
-  struct netif *current_netif;
-  /** The interface that received the packet for the current callback invocation. */
-  struct netif *current_input_netif;
-#if LWIP_IPV4
-  /** Header of the input packet currently being processed. */
-  struct ip_hdr *current_ip4_header;
-#endif /* LWIP_IPV4 */
-#if LWIP_IPV6
-  /** Header of the input IPv6 packet currently being processed. */
-  struct ip6_hdr *current_ip6_header;
-#endif /* LWIP_IPV6 */
-  /** Total header length of current_ip4/6_header (i.e. after this, the UDP/TCP header starts) */
-  u16_t current_ip_header_tot_len;
-  /** Source IP address of current_header */
-  ip_addr_t current_iphdr_src;
-  /** Destination IP address of current_header */
-  ip_addr_t current_iphdr_dest;
-};
-extern struct ip_globals ip_data;
-
-
-/** Get the interface that accepted the current packet.
- * This may or may not be the receiving netif, depending on your netif/network setup.
- * This function must only be called from a receive callback (udp_recv,
- * raw_recv, tcp_accept). It will return NULL otherwise. */
-#define ip_current_netif()      (ip_data.current_netif)
-/** Get the interface that received the current packet.
- * This function must only be called from a receive callback (udp_recv,
- * raw_recv, tcp_accept). It will return NULL otherwise. */
-#define ip_current_input_netif() (ip_data.current_input_netif)
-/** Total header length of ip(6)_current_header() (i.e. after this, the UDP/TCP header starts) */
-#define ip_current_header_tot_len() (ip_data.current_ip_header_tot_len)
-/** Source IP address of current_header */
-#define ip_current_src_addr()   (&ip_data.current_iphdr_src)
-/** Destination IP address of current_header */
-#define ip_current_dest_addr()  (&ip_data.current_iphdr_dest)
-
-#if LWIP_IPV4 && LWIP_IPV6
-/** Get the IPv4 header of the current packet.
- * This function must only be called from a receive callback (udp_recv,
- * raw_recv, tcp_accept). It will return NULL otherwise. */
-#define ip4_current_header()     ((const struct ip_hdr*)(ip_data.current_ip4_header))
-/** Get the IPv6 header of the current packet.
- * This function must only be called from a receive callback (udp_recv,
- * raw_recv, tcp_accept). It will return NULL otherwise. */
-#define ip6_current_header()      ((const struct ip6_hdr*)(ip_data.current_ip6_header))
-/** Returns TRUE if the current IP input packet is IPv6, FALSE if it is IPv4 */
-#define ip_current_is_v6()        (ip6_current_header() != NULL)
-/** Source IPv6 address of current_header */
-#define ip6_current_src_addr()    (ip_2_ip6(&ip_data.current_iphdr_src))
-/** Destination IPv6 address of current_header */
-#define ip6_current_dest_addr()   (ip_2_ip6(&ip_data.current_iphdr_dest))
-/** Get the transport layer protocol */
-#define ip_current_header_proto() (ip_current_is_v6() ? \
-                                   IP6H_NEXTH(ip6_current_header()) :\
-                                   IPH_PROTO(ip4_current_header()))
-/** Get the transport layer header */
-#define ip_next_header_ptr()     ((const void*)((ip_current_is_v6() ? \
-  (const u8_t*)ip6_current_header() : (const u8_t*)ip4_current_header())  + ip_current_header_tot_len()))
-
-/** Source IP4 address of current_header */
-#define ip4_current_src_addr()     (ip_2_ip4(&ip_data.current_iphdr_src))
-/** Destination IP4 address of current_header */
-#define ip4_current_dest_addr()    (ip_2_ip4(&ip_data.current_iphdr_dest))
-
-#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
-
-/** Get the IPv4 header of the current packet.
- * This function must only be called from a receive callback (udp_recv,
- * raw_recv, tcp_accept). It will return NULL otherwise. */
-#define ip4_current_header()     ((const struct ip_hdr*)(ip_data.current_ip4_header))
-/** Always returns FALSE when only supporting IPv4 only */
-#define ip_current_is_v6()        0
-/** Get the transport layer protocol */
-#define ip_current_header_proto() IPH_PROTO(ip4_current_header())
-/** Get the transport layer header */
-#define ip_next_header_ptr()     ((const void*)((const u8_t*)ip4_current_header() + ip_current_header_tot_len()))
-/** Source IP4 address of current_header */
-#define ip4_current_src_addr()     (&ip_data.current_iphdr_src)
-/** Destination IP4 address of current_header */
-#define ip4_current_dest_addr()    (&ip_data.current_iphdr_dest)
-
-#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */
-
-/** Get the IPv6 header of the current packet.
- * This function must only be called from a receive callback (udp_recv,
- * raw_recv, tcp_accept). It will return NULL otherwise. */
-#define ip6_current_header()      ((const struct ip6_hdr*)(ip_data.current_ip6_header))
-/** Always returns TRUE when only supporting IPv6 only */
-#define ip_current_is_v6()        1
-/** Get the transport layer protocol */
-#define ip_current_header_proto() IP6H_NEXTH(ip6_current_header())
-/** Get the transport layer header */
-#define ip_next_header_ptr()     ((const void*)((const u8_t*)ip6_current_header()))
-/** Source IP6 address of current_header */
-#define ip6_current_src_addr()    (&ip_data.current_iphdr_src)
-/** Destination IP6 address of current_header */
-#define ip6_current_dest_addr()   (&ip_data.current_iphdr_dest)
-
-#endif /* LWIP_IPV6 */
-
-/** Union source address of current_header */
-#define ip_current_src_addr()    (&ip_data.current_iphdr_src)
-/** Union destination address of current_header */
-#define ip_current_dest_addr()   (&ip_data.current_iphdr_dest)
-
-/** Gets an IP pcb option (SOF_* flags) */
-#define ip_get_option(pcb, opt)   ((pcb)->so_options & (opt))
-/** Sets an IP pcb option (SOF_* flags) */
-#define ip_set_option(pcb, opt)   ((pcb)->so_options |= (opt))
-/** Resets an IP pcb option (SOF_* flags) */
-#define ip_reset_option(pcb, opt) ((pcb)->so_options &= ~(opt))
-
-#if LWIP_IPV4 && LWIP_IPV6
-/**
- * @ingroup ip
- * Output IP packet, netif is selected by source address
- */
-#define ip_output(p, src, dest, ttl, tos, proto) \
-        (IP_IS_V6(dest) ? \
-        ip6_output(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto) : \
-        ip4_output(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto))
-/**
- * @ingroup ip
- * Output IP packet to specified interface
- */
-#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
-        (IP_IS_V6(dest) ? \
-        ip6_output_if(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \
-        ip4_output_if(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif))
-/**
- * @ingroup ip
- * Output IP packet to interface specifying source address
- */
-#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
-        (IP_IS_V6(dest) ? \
-        ip6_output_if_src(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \
-        ip4_output_if_src(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif))
-/** Output IP packet with addr_hint */
-#define ip_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) \
-        (IP_IS_V6(dest) ? \
-        ip6_output_hinted(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, addr_hint) : \
-        ip4_output_hinted(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, addr_hint))
-/**
- * @ingroup ip
- * Get netif for address combination. See \ref ip6_route and \ref ip4_route
- */
-#define ip_route(src, dest) \
-        (IP_IS_V6(dest) ? \
-        ip6_route(ip_2_ip6(src), ip_2_ip6(dest)) : \
-        ip4_route_src(ip_2_ip4(dest), ip_2_ip4(src)))
-/**
- * @ingroup ip
- * Get netif for IP.
- */
-#define ip_netif_get_local_ip(netif, dest) (IP_IS_V6(dest) ? \
-        ip6_netif_get_local_ip(netif, ip_2_ip6(dest)) : \
-        ip4_netif_get_local_ip(netif))
-#define ip_debug_print(is_ipv6, p) ((is_ipv6) ? ip6_debug_print(p) : ip4_debug_print(p))
-
-err_t ip_input(struct pbuf *p, struct netif *inp);
-
-#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
-
-#define ip_output(p, src, dest, ttl, tos, proto) \
-        ip4_output(p, src, dest, ttl, tos, proto)
-#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
-        ip4_output_if(p, src, dest, ttl, tos, proto, netif)
-#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
-        ip4_output_if_src(p, src, dest, ttl, tos, proto, netif)
-#define ip_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) \
-        ip4_output_hinted(p, src, dest, ttl, tos, proto, addr_hint)
-#define ip_route(src, dest) \
-        ip4_route_src(dest, src)
-#define ip_netif_get_local_ip(netif, dest) \
-        ip4_netif_get_local_ip(netif)
-#define ip_debug_print(is_ipv6, p) ip4_debug_print(p)
-
-#define ip_input ip4_input
-
-#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */
-
-#define ip_output(p, src, dest, ttl, tos, proto) \
-        ip6_output(p, src, dest, ttl, tos, proto)
-#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \
-        ip6_output_if(p, src, dest, ttl, tos, proto, netif)
-#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \
-        ip6_output_if_src(p, src, dest, ttl, tos, proto, netif)
-#define ip_output_hinted(p, src, dest, ttl, tos, proto, addr_hint) \
-        ip6_output_hinted(p, src, dest, ttl, tos, proto, addr_hint)
-#define ip_route(src, dest) \
-        ip6_route(src, dest)
-#define ip_netif_get_local_ip(netif, dest) \
-        ip6_netif_get_local_ip(netif, dest)
-#define ip_debug_print(is_ipv6, p) ip6_debug_print(p)
-
-#define ip_input ip6_input
-
-#endif /* LWIP_IPV6 */
-
-#define ip_route_get_local_ip(src, dest, netif, ipaddr) do { \
-  (netif) = ip_route(src, dest); \
-  (ipaddr) = ip_netif_get_local_ip(netif, dest); \
-}while(0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_IP_H */
-
-
diff --git a/tools/sdk/include/lwip/lwip/ip4.h b/tools/sdk/include/lwip/lwip/ip4.h
deleted file mode 100644
index 48246ecc257..00000000000
--- a/tools/sdk/include/lwip/lwip/ip4.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- * @file
- * IPv4 API
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_IP4_H
-#define LWIP_HDR_IP4_H
-
-#include "lwip/opt.h"
-
-#if LWIP_IPV4
-
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip4_addr.h"
-#include "lwip/err.h"
-#include "lwip/netif.h"
-#include "lwip/prot/ip4.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef LWIP_HOOK_IP4_ROUTE_SRC
-#define LWIP_IPV4_SRC_ROUTING   1
-#else
-#define LWIP_IPV4_SRC_ROUTING   0
-#endif
-
-/** Currently, the function ip_output_if_opt() is only used with IGMP */
-#define IP_OPTIONS_SEND   (LWIP_IPV4 && LWIP_IGMP)
-
-#define ip_init() /* Compatibility define, no init needed. */
-struct netif *ip4_route(const ip4_addr_t *dest);
-#if LWIP_IPV4_SRC_ROUTING
-struct netif *ip4_route_src(const ip4_addr_t *dest, const ip4_addr_t *src);
-#else /* LWIP_IPV4_SRC_ROUTING */
-#define ip4_route_src(dest, src) ip4_route(dest)
-#endif /* LWIP_IPV4_SRC_ROUTING */
-err_t ip4_input(struct pbuf *p, struct netif *inp);
-err_t ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
-       u8_t ttl, u8_t tos, u8_t proto);
-err_t ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
-       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
-err_t ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
-       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif);
-#if LWIP_NETIF_HWADDRHINT
-err_t ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
-       u8_t ttl, u8_t tos, u8_t proto, u8_t *addr_hint);
-#endif /* LWIP_NETIF_HWADDRHINT */
-#if IP_OPTIONS_SEND
-err_t ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
-       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
-       u16_t optlen);
-err_t ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
-       u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
-       u16_t optlen);
-#endif /* IP_OPTIONS_SEND */
-
-#if LWIP_MULTICAST_TX_OPTIONS
-void  ip4_set_default_multicast_netif(struct netif* default_multicast_netif);
-#endif /* LWIP_MULTICAST_TX_OPTIONS */
-
-#define ip4_netif_get_local_ip(netif) (((netif) != NULL) ? netif_ip_addr4(netif) : NULL)
-
-#if IP_DEBUG
-void ip4_debug_print(struct pbuf *p);
-#else
-#define ip4_debug_print(p)
-#endif /* IP_DEBUG */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV4 */
-
-#endif /* LWIP_HDR_IP_H */
-
-
diff --git a/tools/sdk/include/lwip/lwip/ip4_addr.h b/tools/sdk/include/lwip/lwip/ip4_addr.h
deleted file mode 100644
index 51b46b8d4c6..00000000000
--- a/tools/sdk/include/lwip/lwip/ip4_addr.h
+++ /dev/null
@@ -1,227 +0,0 @@
-/**
- * @file
- * IPv4 address API
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_IP4_ADDR_H
-#define LWIP_HDR_IP4_ADDR_H
-
-#include "lwip/opt.h"
-#include "lwip/def.h"
-
-#if LWIP_IPV4
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** This is the aligned version of ip4_addr_t,
-   used as local variable, on the stack, etc. */
-struct ip4_addr {
-  u32_t addr;
-};
-
-/** ip4_addr_t uses a struct for convenience only, so that the same defines can
- * operate both on ip4_addr_t as well as on ip4_addr_p_t. */
-typedef struct ip4_addr ip4_addr_t;
-
-/**
- * struct ipaddr2 is used in the definition of the ARP packet format in
- * order to support compilers that don't have structure packing.
- */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip4_addr2 {
-  PACK_STRUCT_FIELD(u16_t addrw[2]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/* Forward declaration to not include netif.h */
-struct netif;
-
-/** 255.255.255.255 */
-#define IPADDR_NONE         ((u32_t)0xffffffffUL)
-/** 127.0.0.1 */
-#define IPADDR_LOOPBACK     ((u32_t)0x7f000001UL)
-/** 0.0.0.0 */
-#define IPADDR_ANY          ((u32_t)0x00000000UL)
-/** 255.255.255.255 */
-#define IPADDR_BROADCAST    ((u32_t)0xffffffffUL)
-
-/* Definitions of the bits in an Internet address integer.
-
-   On subnets, host and network parts are found according to
-   the subnet mask, not these masks.  */
-#define IP_CLASSA(a)        ((((u32_t)(a)) & 0x80000000UL) == 0)
-#define IP_CLASSA_NET       0xff000000
-#define IP_CLASSA_NSHIFT    24
-#define IP_CLASSA_HOST      (0xffffffff & ~IP_CLASSA_NET)
-#define IP_CLASSA_MAX       128
-
-#define IP_CLASSB(a)        ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL)
-#define IP_CLASSB_NET       0xffff0000
-#define IP_CLASSB_NSHIFT    16
-#define IP_CLASSB_HOST      (0xffffffff & ~IP_CLASSB_NET)
-#define IP_CLASSB_MAX       65536
-
-#define IP_CLASSC(a)        ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL)
-#define IP_CLASSC_NET       0xffffff00
-#define IP_CLASSC_NSHIFT    8
-#define IP_CLASSC_HOST      (0xffffffff & ~IP_CLASSC_NET)
-
-#define IP_CLASSD(a)        (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL)
-#define IP_CLASSD_NET       0xf0000000          /* These ones aren't really */
-#define IP_CLASSD_NSHIFT    28                  /*   net and host fields, but */
-#define IP_CLASSD_HOST      0x0fffffff          /*   routing needn't know. */
-#define IP_MULTICAST(a)     IP_CLASSD(a)
-
-#define IP_EXPERIMENTAL(a)  (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
-#define IP_BADCLASS(a)      (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL)
-
-#define IP_LOOPBACKNET      127                 /* official! */
-
-/** Set an IP address given by the four byte-parts */
-#define IP4_ADDR(ipaddr, a,b,c,d)  (ipaddr)->addr = PP_HTONL(LWIP_MAKEU32(a,b,c,d))
-
-/** MEMCPY-like copying of IP addresses where addresses are known to be
- * 16-bit-aligned if the port is correctly configured (so a port could define
- * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */
-#ifndef IPADDR2_COPY
-#define IPADDR2_COPY(dest, src) SMEMCPY(dest, src, sizeof(ip4_addr_t))
-#endif
-
-/** Copy IP address - faster than ip4_addr_set: no NULL check */
-#define ip4_addr_copy(dest, src) ((dest).addr = (src).addr)
-/** Safely copy one IP address to another (src may be NULL) */
-#define ip4_addr_set(dest, src) ((dest)->addr = \
-                                    ((src) == NULL ? 0 : \
-                                    (src)->addr))
-/** Set complete address to zero */
-#define ip4_addr_set_zero(ipaddr)     ((ipaddr)->addr = 0)
-/** Set address to IPADDR_ANY (no need for lwip_htonl()) */
-#define ip4_addr_set_any(ipaddr)      ((ipaddr)->addr = IPADDR_ANY)
-/** Set address to loopback address */
-#define ip4_addr_set_loopback(ipaddr) ((ipaddr)->addr = PP_HTONL(IPADDR_LOOPBACK))
-/** Check if an address is in the loopback region */
-#define ip4_addr_isloopback(ipaddr)    (((ipaddr)->addr & PP_HTONL(IP_CLASSA_NET)) == PP_HTONL(((u32_t)IP_LOOPBACKNET) << 24))
-/** Safely copy one IP address to another and change byte order
- * from host- to network-order. */
-#define ip4_addr_set_hton(dest, src) ((dest)->addr = \
-                               ((src) == NULL ? 0:\
-                               lwip_htonl((src)->addr)))
-/** IPv4 only: set the IP address given as an u32_t */
-#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32))
-/** IPv4 only: get the IP address as an u32_t */
-#define ip4_addr_get_u32(src_ipaddr) ((src_ipaddr)->addr)
-
-/** Get the network address by combining host address with netmask */
-#define ip4_addr_get_network(target, host, netmask) do { ((target)->addr = ((host)->addr) & ((netmask)->addr)); } while(0)
-
-/**
- * Determine if two address are on the same network.
- *
- * @arg addr1 IP address 1
- * @arg addr2 IP address 2
- * @arg mask network identifier mask
- * @return !0 if the network identifiers of both address match
- */
-#define ip4_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \
-                                              (mask)->addr) == \
-                                             ((addr2)->addr & \
-                                              (mask)->addr))
-#define ip4_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr)
-
-#define ip4_addr_isany_val(addr1)   ((addr1).addr == IPADDR_ANY)
-#define ip4_addr_isany(addr1) ((addr1) == NULL || ip4_addr_isany_val(*(addr1)))
-
-#define ip4_addr_isbroadcast(addr1, netif) ip4_addr_isbroadcast_u32((addr1)->addr, netif)
-u8_t ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif);
-
-#define ip_addr_netmask_valid(netmask) ip4_addr_netmask_valid((netmask)->addr)
-u8_t ip4_addr_netmask_valid(u32_t netmask);
-
-#define ip4_addr_ismulticast(addr1) (((addr1)->addr & PP_HTONL(0xf0000000UL)) == PP_HTONL(0xe0000000UL))
-
-#define ip4_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL))
-
-#define ip4_addr_debug_print_parts(debug, a, b, c, d) \
-  LWIP_DEBUGF(debug, ("%" U16_F ".%" U16_F ".%" U16_F ".%" U16_F, a, b, c, d))
-#define ip4_addr_debug_print(debug, ipaddr) \
-  ip4_addr_debug_print_parts(debug, \
-                      (u16_t)((ipaddr) != NULL ? ip4_addr1_16(ipaddr) : 0),       \
-                      (u16_t)((ipaddr) != NULL ? ip4_addr2_16(ipaddr) : 0),       \
-                      (u16_t)((ipaddr) != NULL ? ip4_addr3_16(ipaddr) : 0),       \
-                      (u16_t)((ipaddr) != NULL ? ip4_addr4_16(ipaddr) : 0))
-#define ip4_addr_debug_print_val(debug, ipaddr) \
-  ip4_addr_debug_print_parts(debug, \
-                      ip4_addr1_16(&(ipaddr)),       \
-                      ip4_addr2_16(&(ipaddr)),       \
-                      ip4_addr3_16(&(ipaddr)),       \
-                      ip4_addr4_16(&(ipaddr)))
-
-/* Get one byte from the 4-byte address */
-#define ip4_addr1(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[0])
-#define ip4_addr2(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[1])
-#define ip4_addr3(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[2])
-#define ip4_addr4(ipaddr) (((const u8_t*)(&(ipaddr)->addr))[3])
-/* These are cast to u16_t, with the intent that they are often arguments
- * to printf using the U16_F format from cc.h. */
-#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr))
-#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr))
-#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr))
-#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr))
-
-#define IP4ADDR_STRLEN_MAX  16
-
-/** For backwards compatibility */
-#define ip_ntoa(ipaddr)  ipaddr_ntoa(ipaddr)
-
-u32_t ipaddr_addr(const char *cp);
-int ip4addr_aton(const char *cp, ip4_addr_t *addr);
-/** returns ptr to static buffer; not reentrant! */
-char *ip4addr_ntoa(const ip4_addr_t *addr);
-char *ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV4 */
-
-#endif /* LWIP_HDR_IP_ADDR_H */
diff --git a/tools/sdk/include/lwip/lwip/ip4_frag.h b/tools/sdk/include/lwip/lwip/ip4_frag.h
deleted file mode 100644
index ed5bf14a31c..00000000000
--- a/tools/sdk/include/lwip/lwip/ip4_frag.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/**
- * @file
- * IP fragmentation/reassembly
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Jani Monoses <jani@iv.ro>
- *
- */
-
-#ifndef LWIP_HDR_IP4_FRAG_H
-#define LWIP_HDR_IP4_FRAG_H
-
-#include "lwip/opt.h"
-#include "lwip/err.h"
-#include "lwip/pbuf.h"
-#include "lwip/netif.h"
-#include "lwip/ip_addr.h"
-#include "lwip/ip.h"
-
-#if LWIP_IPV4
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if IP_REASSEMBLY
-/* The IP reassembly timer interval in milliseconds. */
-#define IP_TMR_INTERVAL 1000
-
-/** IP reassembly helper struct.
- * This is exported because memp needs to know the size.
- */
-struct ip_reassdata {
-  struct ip_reassdata *next;
-  struct pbuf *p;
-  struct ip_hdr iphdr;
-  u16_t datagram_len;
-  u8_t flags;
-  u8_t timer;
-};
-
-void ip_reass_init(void);
-void ip_reass_tmr(void);
-struct pbuf * ip4_reass(struct pbuf *p);
-#endif /* IP_REASSEMBLY */
-
-#if IP_FRAG
-#if !LWIP_NETIF_TX_SINGLE_PBUF
-#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED
-#define LWIP_PBUF_CUSTOM_REF_DEFINED
-/** A custom pbuf that holds a reference to another pbuf, which is freed
- * when this custom pbuf is freed. This is used to create a custom PBUF_REF
- * that points into the original pbuf. */
-struct pbuf_custom_ref {
-  /** 'base class' */
-  struct pbuf_custom pc;
-  /** pointer to the original pbuf that is referenced */
-  struct pbuf *original;
-};
-#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */
-#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */
-
-err_t ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest);
-#endif /* IP_FRAG */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV4 */
-
-#endif /* LWIP_HDR_IP4_FRAG_H */
diff --git a/tools/sdk/include/lwip/lwip/ip6.h b/tools/sdk/include/lwip/lwip/ip6.h
deleted file mode 100644
index 099b94fb74f..00000000000
--- a/tools/sdk/include/lwip/lwip/ip6.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/**
- * @file
- *
- * IPv6 layer.
- */
-
-/*
- * Copyright (c) 2010 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-#ifndef LWIP_HDR_IP6_H
-#define LWIP_HDR_IP6_H
-
-#include "lwip/opt.h"
-
-#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/ip6_addr.h"
-#include "lwip/prot/ip6.h"
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/netif.h"
-
-#include "lwip/err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct netif *ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest);
-const ip_addr_t *ip6_select_source_address(struct netif *netif, const ip6_addr_t * dest);
-err_t         ip6_input(struct pbuf *p, struct netif *inp);
-err_t         ip6_output(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
-                         u8_t hl, u8_t tc, u8_t nexth);
-err_t         ip6_output_if(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
-                            u8_t hl, u8_t tc, u8_t nexth, struct netif *netif);
-err_t         ip6_output_if_src(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
-                            u8_t hl, u8_t tc, u8_t nexth, struct netif *netif);
-#if LWIP_NETIF_HWADDRHINT
-err_t         ip6_output_hinted(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest,
-                                u8_t hl, u8_t tc, u8_t nexth, u8_t *addr_hint);
-#endif /* LWIP_NETIF_HWADDRHINT */
-#if LWIP_IPV6_MLD
-err_t         ip6_options_add_hbh_ra(struct pbuf * p, u8_t nexth, u8_t value);
-#endif /* LWIP_IPV6_MLD */
-
-#define ip6_netif_get_local_ip(netif, dest) (((netif) != NULL) ? \
-  ip6_select_source_address(netif, dest) : NULL)
-
-#if IP6_DEBUG
-void ip6_debug_print(struct pbuf *p);
-#else
-#define ip6_debug_print(p)
-#endif /* IP6_DEBUG */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV6 */
-
-#endif /* LWIP_HDR_IP6_H */
diff --git a/tools/sdk/include/lwip/lwip/ip6_addr.h b/tools/sdk/include/lwip/lwip/ip6_addr.h
deleted file mode 100644
index ee381aeb233..00000000000
--- a/tools/sdk/include/lwip/lwip/ip6_addr.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/**
- * @file
- *
- * IPv6 addresses.
- */
-
-/*
- * Copyright (c) 2010 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- * Structs and macros for handling IPv6 addresses.
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-#ifndef LWIP_HDR_IP6_ADDR_H
-#define LWIP_HDR_IP6_ADDR_H
-
-#include "lwip/opt.h"
-#include "def.h"
-
-#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/** This is the aligned version of ip6_addr_t,
-    used as local variable, on the stack, etc. */
-struct ip6_addr {
-  u32_t addr[4];
-};
-
-/** IPv6 address */
-typedef struct ip6_addr ip6_addr_t;
-
-/** Set an IPv6 partial address given by byte-parts */
-#define IP6_ADDR_PART(ip6addr, index, a,b,c,d) \
-  (ip6addr)->addr[index] = PP_HTONL(LWIP_MAKEU32(a,b,c,d))
-
-/** Set a full IPv6 address by passing the 4 u32_t indices in network byte order
-    (use PP_HTONL() for constants) */
-#define IP6_ADDR(ip6addr, idx0, idx1, idx2, idx3) do { \
-  (ip6addr)->addr[0] = idx0; \
-  (ip6addr)->addr[1] = idx1; \
-  (ip6addr)->addr[2] = idx2; \
-  (ip6addr)->addr[3] = idx3; } while(0)
-
-/** Access address in 16-bit block */
-#define IP6_ADDR_BLOCK1(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xffff))
-/** Access address in 16-bit block */
-#define IP6_ADDR_BLOCK2(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0])) & 0xffff))
-/** Access address in 16-bit block */
-#define IP6_ADDR_BLOCK3(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1]) >> 16) & 0xffff))
-/** Access address in 16-bit block */
-#define IP6_ADDR_BLOCK4(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1])) & 0xffff))
-/** Access address in 16-bit block */
-#define IP6_ADDR_BLOCK5(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2]) >> 16) & 0xffff))
-/** Access address in 16-bit block */
-#define IP6_ADDR_BLOCK6(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2])) & 0xffff))
-/** Access address in 16-bit block */
-#define IP6_ADDR_BLOCK7(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3]) >> 16) & 0xffff))
-/** Access address in 16-bit block */
-#define IP6_ADDR_BLOCK8(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3])) & 0xffff))
-
-/** Copy IPv6 address - faster than ip6_addr_set: no NULL check */
-#define ip6_addr_copy(dest, src) do{(dest).addr[0] = (src).addr[0]; \
-                                    (dest).addr[1] = (src).addr[1]; \
-                                    (dest).addr[2] = (src).addr[2]; \
-                                    (dest).addr[3] = (src).addr[3];}while(0)
-/** Safely copy one IPv6 address to another (src may be NULL) */
-#define ip6_addr_set(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : (src)->addr[0]; \
-                                   (dest)->addr[1] = (src) == NULL ? 0 : (src)->addr[1]; \
-                                   (dest)->addr[2] = (src) == NULL ? 0 : (src)->addr[2]; \
-                                   (dest)->addr[3] = (src) == NULL ? 0 : (src)->addr[3];}while(0)
-
-/** Set complete address to zero */
-#define ip6_addr_set_zero(ip6addr)    do{(ip6addr)->addr[0] = 0; \
-                                         (ip6addr)->addr[1] = 0; \
-                                         (ip6addr)->addr[2] = 0; \
-                                         (ip6addr)->addr[3] = 0;}while(0)
-
-/** Set address to ipv6 'any' (no need for lwip_htonl()) */
-#define ip6_addr_set_any(ip6addr)       ip6_addr_set_zero(ip6addr)
-/** Set address to ipv6 loopback address */
-#define ip6_addr_set_loopback(ip6addr) do{(ip6addr)->addr[0] = 0; \
-                                          (ip6addr)->addr[1] = 0; \
-                                          (ip6addr)->addr[2] = 0; \
-                                          (ip6addr)->addr[3] = PP_HTONL(0x00000001UL);}while(0)
-/** Safely copy one IPv6 address to another and change byte order
- * from host- to network-order. */
-#define ip6_addr_set_hton(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : lwip_htonl((src)->addr[0]); \
-                                        (dest)->addr[1] = (src) == NULL ? 0 : lwip_htonl((src)->addr[1]); \
-                                        (dest)->addr[2] = (src) == NULL ? 0 : lwip_htonl((src)->addr[2]); \
-                                        (dest)->addr[3] = (src) == NULL ? 0 : lwip_htonl((src)->addr[3]);}while(0)
-
-
-/**
- * Determine if two IPv6 address are on the same network.
- *
- * @arg addr1 IPv6 address 1
- * @arg addr2 IPv6 address 2
- * @return !0 if the network identifiers of both address match
- */
-#define ip6_addr_netcmp(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \
-                                       ((addr1)->addr[1] == (addr2)->addr[1]))
-
-#define ip6_addr_cmp(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \
-                                    ((addr1)->addr[1] == (addr2)->addr[1]) && \
-                                    ((addr1)->addr[2] == (addr2)->addr[2]) && \
-                                    ((addr1)->addr[3] == (addr2)->addr[3]))
-
-#define ip6_get_subnet_id(ip6addr)   (lwip_htonl((ip6addr)->addr[2]) & 0x0000ffffUL)
-
-#define ip6_addr_isany_val(ip6addr) (((ip6addr).addr[0] == 0) && \
-                                     ((ip6addr).addr[1] == 0) && \
-                                     ((ip6addr).addr[2] == 0) && \
-                                     ((ip6addr).addr[3] == 0))
-#define ip6_addr_isany(ip6addr) (((ip6addr) == NULL) || ip6_addr_isany_val(*(ip6addr)))
-
-#define ip6_addr_isloopback(ip6addr) (((ip6addr)->addr[0] == 0UL) && \
-                                      ((ip6addr)->addr[1] == 0UL) && \
-                                      ((ip6addr)->addr[2] == 0UL) && \
-                                      ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
-
-#define ip6_addr_isglobal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xe0000000UL)) == PP_HTONL(0x20000000UL))
-
-#define ip6_addr_islinklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfe800000UL))
-
-#define ip6_addr_issitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfec00000UL))
-
-#define ip6_addr_isuniquelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xfe000000UL)) == PP_HTONL(0xfc000000UL))
-
-#define ip6_addr_isipv4mappedipv6(ip6addr) (((ip6addr)->addr[0] == 0) && ((ip6addr)->addr[1] == 0) && (((ip6addr)->addr[2]) == PP_HTONL(0x0000FFFFUL)))
-
-#define ip6_addr_ismulticast(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL))
-#define ip6_addr_multicast_transient_flag(ip6addr)  ((ip6addr)->addr[0] & PP_HTONL(0x00100000UL))
-#define ip6_addr_multicast_prefix_flag(ip6addr)     ((ip6addr)->addr[0] & PP_HTONL(0x00200000UL))
-#define ip6_addr_multicast_rendezvous_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00400000UL))
-#define ip6_addr_multicast_scope(ip6addr) ((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xf)
-#define IP6_MULTICAST_SCOPE_RESERVED            0x0
-#define IP6_MULTICAST_SCOPE_RESERVED0           0x0
-#define IP6_MULTICAST_SCOPE_INTERFACE_LOCAL     0x1
-#define IP6_MULTICAST_SCOPE_LINK_LOCAL          0x2
-#define IP6_MULTICAST_SCOPE_RESERVED3           0x3
-#define IP6_MULTICAST_SCOPE_ADMIN_LOCAL         0x4
-#define IP6_MULTICAST_SCOPE_SITE_LOCAL          0x5
-#define IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL  0x8
-#define IP6_MULTICAST_SCOPE_GLOBAL              0xe
-#define IP6_MULTICAST_SCOPE_RESERVEDF           0xf
-#define ip6_addr_ismulticast_iflocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff010000UL))
-#define ip6_addr_ismulticast_linklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff020000UL))
-#define ip6_addr_ismulticast_adminlocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff040000UL))
-#define ip6_addr_ismulticast_sitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff050000UL))
-#define ip6_addr_ismulticast_orglocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff080000UL))
-#define ip6_addr_ismulticast_global(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff0e0000UL))
-
-/* @todo define get/set for well-know multicast addresses, e.g. ff02::1 */
-#define ip6_addr_isallnodes_iflocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff010000UL)) && \
-    ((ip6addr)->addr[1] == 0UL) && \
-    ((ip6addr)->addr[2] == 0UL) && \
-    ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
-
-#define ip6_addr_isallnodes_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
-    ((ip6addr)->addr[1] == 0UL) && \
-    ((ip6addr)->addr[2] == 0UL) && \
-    ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL)))
-#define ip6_addr_set_allnodes_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
-                (ip6addr)->addr[1] = 0; \
-                (ip6addr)->addr[2] = 0; \
-                (ip6addr)->addr[3] = PP_HTONL(0x00000001UL);}while(0)
-
-#define ip6_addr_isallrouters_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
-    ((ip6addr)->addr[1] == 0UL) && \
-    ((ip6addr)->addr[2] == 0UL) && \
-    ((ip6addr)->addr[3] == PP_HTONL(0x00000002UL)))
-#define ip6_addr_set_allrouters_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
-                (ip6addr)->addr[1] = 0; \
-                (ip6addr)->addr[2] = 0; \
-                (ip6addr)->addr[3] = PP_HTONL(0x00000002UL);}while(0)
-
-#define ip6_addr_issolicitednode(ip6addr) ( ((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
-        ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \
-        (((ip6addr)->addr[3] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL)) )
-
-#define ip6_addr_set_solicitednode(ip6addr, if_id) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \
-                (ip6addr)->addr[1] = 0; \
-                (ip6addr)->addr[2] = PP_HTONL(0x00000001UL); \
-                (ip6addr)->addr[3] = (PP_HTONL(0xff000000UL) | (if_id));}while(0)
-
-#define ip6_addr_cmp_solicitednode(ip6addr, sn_addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \
-                                    ((ip6addr)->addr[1] == 0) && \
-                                    ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \
-                                    ((ip6addr)->addr[3] == (PP_HTONL(0xff000000UL) | (sn_addr)->addr[3])))
-
-/* IPv6 address states. */
-#define IP6_ADDR_INVALID      0x00
-#define IP6_ADDR_TENTATIVE    0x08
-#define IP6_ADDR_TENTATIVE_1  0x09 /* 1 probe sent */
-#define IP6_ADDR_TENTATIVE_2  0x0a /* 2 probes sent */
-#define IP6_ADDR_TENTATIVE_3  0x0b /* 3 probes sent */
-#define IP6_ADDR_TENTATIVE_4  0x0c /* 4 probes sent */
-#define IP6_ADDR_TENTATIVE_5  0x0d /* 5 probes sent */
-#define IP6_ADDR_TENTATIVE_6  0x0e /* 6 probes sent */
-#define IP6_ADDR_TENTATIVE_7  0x0f /* 7 probes sent */
-#define IP6_ADDR_VALID        0x10 /* This bit marks an address as valid (preferred or deprecated) */
-#define IP6_ADDR_PREFERRED    0x30
-#define IP6_ADDR_DEPRECATED   0x10 /* Same as VALID (valid but not preferred) */
-
-#define IP6_ADDR_TENTATIVE_COUNT_MASK 0x07 /* 1-7 probes sent */
-
-#define ip6_addr_isinvalid(addr_state) (addr_state == IP6_ADDR_INVALID)
-#define ip6_addr_istentative(addr_state) (addr_state & IP6_ADDR_TENTATIVE)
-#define ip6_addr_isvalid(addr_state) (addr_state & IP6_ADDR_VALID) /* Include valid, preferred, and deprecated. */
-#define ip6_addr_ispreferred(addr_state) (addr_state == IP6_ADDR_PREFERRED)
-#define ip6_addr_isdeprecated(addr_state) (addr_state == IP6_ADDR_DEPRECATED)
-
-#define ip6_addr_debug_print_parts(debug, a, b, c, d, e, f, g, h) \
-  LWIP_DEBUGF(debug, ("%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F, \
-                      a, b, c, d, e, f, g, h))
-#define ip6_addr_debug_print(debug, ipaddr) \
-  ip6_addr_debug_print_parts(debug, \
-                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK1(ipaddr) : 0),    \
-                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK2(ipaddr) : 0),    \
-                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK3(ipaddr) : 0),    \
-                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK4(ipaddr) : 0),    \
-                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK5(ipaddr) : 0),    \
-                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK6(ipaddr) : 0),    \
-                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK7(ipaddr) : 0),    \
-                      (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK8(ipaddr) : 0))
-#define ip6_addr_debug_print_val(debug, ipaddr) \
-  ip6_addr_debug_print_parts(debug, \
-                      IP6_ADDR_BLOCK1(&(ipaddr)),    \
-                      IP6_ADDR_BLOCK2(&(ipaddr)),    \
-                      IP6_ADDR_BLOCK3(&(ipaddr)),    \
-                      IP6_ADDR_BLOCK4(&(ipaddr)),    \
-                      IP6_ADDR_BLOCK5(&(ipaddr)),    \
-                      IP6_ADDR_BLOCK6(&(ipaddr)),    \
-                      IP6_ADDR_BLOCK7(&(ipaddr)),    \
-                      IP6_ADDR_BLOCK8(&(ipaddr)))
-
-#define IP6ADDR_STRLEN_MAX    46
-
-int ip6addr_aton(const char *cp, ip6_addr_t *addr);
-/** returns ptr to static buffer; not reentrant! */
-char *ip6addr_ntoa(const ip6_addr_t *addr);
-char *ip6addr_ntoa_r(const ip6_addr_t *addr, char *buf, int buflen);
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV6 */
-
-#endif /* LWIP_HDR_IP6_ADDR_H */
diff --git a/tools/sdk/include/lwip/lwip/ip6_frag.h b/tools/sdk/include/lwip/lwip/ip6_frag.h
deleted file mode 100644
index 6be274734b2..00000000000
--- a/tools/sdk/include/lwip/lwip/ip6_frag.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
- * @file
- *
- * IPv6 fragmentation and reassembly.
- */
-
-/*
- * Copyright (c) 2010 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-#ifndef LWIP_HDR_IP6_FRAG_H
-#define LWIP_HDR_IP6_FRAG_H
-
-#include "lwip/opt.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip6_addr.h"
-#include "lwip/ip6.h"
-#include "lwip/netif.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#if LWIP_IPV6 && LWIP_IPV6_REASS  /* don't build if not configured for use in lwipopts.h */
-
-/** IP6_FRAG_COPYHEADER==1: for platforms where sizeof(void*) > 4, this needs to
- * be enabled (to not overwrite part of the data). When enabled, the IPv6 header
- * is copied instead of referencing it, which gives more room for struct ip6_reass_helper */
-#ifndef IPV6_FRAG_COPYHEADER
-#define IPV6_FRAG_COPYHEADER   0
-#endif
-
-/** The IPv6 reassembly timer interval in milliseconds. */
-#define IP6_REASS_TMR_INTERVAL 1000
-
-/* Copy the complete header of the first fragment to struct ip6_reassdata
-   or just point to its original location in the first pbuf? */
-#if IPV6_FRAG_COPYHEADER
-#define IPV6_FRAG_HDRPTR
-#define IPV6_FRAG_HDRREF(hdr) (&(hdr))
-#else /* IPV6_FRAG_COPYHEADER */
-#define IPV6_FRAG_HDRPTR *
-#define IPV6_FRAG_HDRREF(hdr) (hdr)
-#endif /* IPV6_FRAG_COPYHEADER */
-
-/** IPv6 reassembly helper struct.
- * This is exported because memp needs to know the size.
- */
-struct ip6_reassdata {
-  struct ip6_reassdata *next;
-  struct pbuf *p;
-  struct ip6_hdr IPV6_FRAG_HDRPTR iphdr;
-  u32_t identification;
-  u16_t datagram_len;
-  u8_t nexth;
-  u8_t timer;
-};
-
-#define ip6_reass_init() /* Compatibility define */
-void ip6_reass_tmr(void);
-struct pbuf *ip6_reass(struct pbuf *p);
-
-#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */
-
-#if LWIP_IPV6 && LWIP_IPV6_FRAG  /* don't build if not configured for use in lwipopts.h */
-
-#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED
-#define LWIP_PBUF_CUSTOM_REF_DEFINED
-/** A custom pbuf that holds a reference to another pbuf, which is freed
- * when this custom pbuf is freed. This is used to create a custom PBUF_REF
- * that points into the original pbuf. */
-struct pbuf_custom_ref {
-  /** 'base class' */
-  struct pbuf_custom pc;
-  /** pointer to the original pbuf that is referenced */
-  struct pbuf *original;
-};
-#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */
-
-err_t ip6_frag(struct pbuf *p, struct netif *netif, const ip6_addr_t *dest);
-
-#endif /* LWIP_IPV6 && LWIP_IPV6_FRAG */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_IP6_FRAG_H */
diff --git a/tools/sdk/include/lwip/lwip/ip_addr.h b/tools/sdk/include/lwip/lwip/ip_addr.h
deleted file mode 100644
index ca09ed3982a..00000000000
--- a/tools/sdk/include/lwip/lwip/ip_addr.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/**
- * @file
- * IP address API (common IPv4 and IPv6)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_IP_ADDR_H
-#define LWIP_HDR_IP_ADDR_H
-
-#include "lwip/opt.h"
-#include "lwip/def.h"
-
-#include "lwip/ip4_addr.h"
-#include "lwip/ip6_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @ingroup ipaddr
- * IP address types for use in ip_addr_t.type member.
- * @see tcp_new_ip_type(), udp_new_ip_type(), raw_new_ip_type().
- */
-enum lwip_ip_addr_type {
-  /** IPv4 */
-  IPADDR_TYPE_V4 =   0U,
-  /** IPv6 */
-  IPADDR_TYPE_V6 =   6U,
-  /** IPv4+IPv6 ("dual-stack") */
-  IPADDR_TYPE_ANY = 46U
-};
-
-#if LWIP_IPV4 && LWIP_IPV6
-/**
- * @ingroup ipaddr
- * A union struct for both IP version's addresses.
- * ATTENTION: watch out for its size when adding IPv6 address scope!
- */
-typedef struct ip_addr {
-  union {
-    ip6_addr_t ip6;
-    ip4_addr_t ip4;
-  } u_addr;
-  /** @ref lwip_ip_addr_type */
-  u8_t type;
-} ip_addr_t;
-
-extern const ip_addr_t ip_addr_any_type;
-
-/** @ingroup ip4addr */
-#define IPADDR4_INIT(u32val)          { { { { u32val, 0ul, 0ul, 0ul } } }, IPADDR_TYPE_V4 }
-/** @ingroup ip4addr */
-#define IPADDR4_INIT_BYTES(a,b,c,d)   IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d)))
-/** @ingroup ip6addr */
-#define IPADDR6_INIT(a, b, c, d)      { { { { a, b, c, d } } }, IPADDR_TYPE_V6 }
-/** @ingroup ip6addr */
-#define IPADDR6_INIT_HOST(a, b, c, d) { { { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } } }, IPADDR_TYPE_V6 }
-
-/** @ingroup ipaddr */
-#define IP_IS_ANY_TYPE_VAL(ipaddr)    (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_ANY)
-/** @ingroup ipaddr */
-#define IPADDR_ANY_TYPE_INIT          { { { { 0ul, 0ul, 0ul, 0ul } } }, IPADDR_TYPE_ANY }
-
-/** @ingroup ip4addr */
-#define IP_IS_V4_VAL(ipaddr)          (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V4)
-/** @ingroup ip6addr */
-#define IP_IS_V6_VAL(ipaddr)          (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V6)
-/** @ingroup ip4addr */
-#define IP_IS_V4(ipaddr)              (((ipaddr) == NULL) || IP_IS_V4_VAL(*(ipaddr)))
-/** @ingroup ip6addr */
-#define IP_IS_V6(ipaddr)              (((ipaddr) != NULL) && IP_IS_V6_VAL(*(ipaddr)))
-
-#if ESP_LWIP
-#define IP_V6_EQ_PART(ipaddr, WORD, VAL) (ip_2_ip6(ipaddr)->addr[WORD] == htonl(VAL))
-#define IP_IS_V4MAPPEDV6(ipaddr) (IP_IS_V6(ipaddr) && IP_V6_EQ_PART(ipaddr, 0, 0) && IP_V6_EQ_PART(ipaddr, 1, 0) && IP_V6_EQ_PART(ipaddr, 2, 0x0000FFFF))
-#endif
-
-#define IP_SET_TYPE_VAL(ipaddr, iptype) do { (ipaddr).type = (iptype); }while(0)
-#define IP_SET_TYPE(ipaddr, iptype)     do { if((ipaddr) != NULL) { IP_SET_TYPE_VAL(*(ipaddr), iptype); }}while(0)
-#define IP_GET_TYPE(ipaddr)           ((ipaddr)->type)
-
-#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) (IP_GET_TYPE(&pcb->local_ip) == IP_GET_TYPE(ipaddr))
-#define IP_ADDR_PCB_VERSION_MATCH(pcb, ipaddr) (IP_IS_ANY_TYPE_VAL(pcb->local_ip) || IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr))
-
-/** @ingroup ip6addr
- * Convert generic ip address to specific protocol version
- */
-#define ip_2_ip6(ipaddr)   (&((ipaddr)->u_addr.ip6))
-/** @ingroup ip4addr
- * Convert generic ip address to specific protocol version
- */
-#define ip_2_ip4(ipaddr)   (&((ipaddr)->u_addr.ip4))
-
-/** @ingroup ip4addr */
-#define IP_ADDR4(ipaddr,a,b,c,d)      do { IP4_ADDR(ip_2_ip4(ipaddr),a,b,c,d); \
-                                           IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V4); } while(0)
-/** @ingroup ip6addr */
-#define IP_ADDR6(ipaddr,i0,i1,i2,i3)  do { IP6_ADDR(ip_2_ip6(ipaddr),i0,i1,i2,i3); \
-                                           IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V6); } while(0)
-/** @ingroup ip6addr */
-#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3)  IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3))
-
-/** @ingroup ipaddr */
-#define ip_addr_copy(dest, src)      do{ IP_SET_TYPE_VAL(dest, IP_GET_TYPE(&src)); if(IP_IS_V6_VAL(src)){ \
-  ip6_addr_copy(*ip_2_ip6(&(dest)), *ip_2_ip6(&(src))); }else{ \
-  ip4_addr_copy(*ip_2_ip4(&(dest)), *ip_2_ip4(&(src))); }}while(0)
-/** @ingroup ip6addr */
-#define ip_addr_copy_from_ip6(dest, src)      do{ \
-  ip6_addr_copy(*ip_2_ip6(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V6); }while(0)
-/** @ingroup ip4addr */
-#define ip_addr_copy_from_ip4(dest, src)      do{ \
-  ip4_addr_copy(*ip_2_ip4(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V4); }while(0)
-/** @ingroup ip4addr */
-#define ip_addr_set_ip4_u32(ipaddr, val)  do{if(ipaddr){ip4_addr_set_u32(ip_2_ip4(ipaddr), val); \
-  IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }}while(0)
-/** @ingroup ip4addr */
-#define ip_addr_get_ip4_u32(ipaddr)  (((ipaddr) && IP_IS_V4(ipaddr)) ? \
-  ip4_addr_get_u32(ip_2_ip4(ipaddr)) : 0)
-/** @ingroup ipaddr */
-#define ip_addr_set(dest, src) do{ IP_SET_TYPE(dest, IP_GET_TYPE(src)); if(IP_IS_V6(src)){ \
-  ip6_addr_set(ip_2_ip6(dest), ip_2_ip6(src)); }else{ \
-  ip4_addr_set(ip_2_ip4(dest), ip_2_ip4(src)); }}while(0)
-/** @ingroup ipaddr */
-#define ip_addr_set_ipaddr(dest, src) ip_addr_set(dest, src)
-/** @ingroup ipaddr */
-#define ip_addr_set_zero(ipaddr)     do{ \
-  ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, 0); }while(0)
-/** @ingroup ip5addr */
-#define ip_addr_set_zero_ip4(ipaddr)     do{ \
-  ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }while(0)
-/** @ingroup ip6addr */
-#define ip_addr_set_zero_ip6(ipaddr)     do{ \
-  ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }while(0)
-/** @ingroup ipaddr */
-#define ip_addr_set_any(is_ipv6, ipaddr)      do{if(is_ipv6){ \
-  ip6_addr_set_any(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \
-  ip4_addr_set_any(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }}while(0)
-/** @ingroup ipaddr */
-#define ip_addr_set_loopback(is_ipv6, ipaddr) do{if(is_ipv6){ \
-  ip6_addr_set_loopback(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \
-  ip4_addr_set_loopback(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }}while(0)
-/** @ingroup ipaddr */
-#define ip_addr_set_hton(dest, src)  do{if(IP_IS_V6(src)){ \
-  ip6_addr_set_hton(ip_2_ip6(ipaddr), (src)); IP_SET_TYPE(dest, IPADDR_TYPE_V6); }else{ \
-  ip4_addr_set_hton(ip_2_ip4(ipaddr), (src)); IP_SET_TYPE(dest, IPADDR_TYPE_V4); }}while(0)
-/** @ingroup ipaddr */
-#define ip_addr_get_network(target, host, netmask) do{if(IP_IS_V6(host)){ \
-  ip4_addr_set_zero(ip_2_ip4(target)); IP_SET_TYPE(target, IPADDR_TYPE_V6); } else { \
-  ip4_addr_get_network(ip_2_ip4(target), ip_2_ip4(host), ip_2_ip4(netmask)); IP_SET_TYPE(target, IPADDR_TYPE_V4); }}while(0)
-/** @ingroup ipaddr */
-#define ip_addr_netcmp(addr1, addr2, mask) ((IP_IS_V6(addr1) && IP_IS_V6(addr2)) ? \
-  0 : \
-  ip4_addr_netcmp(ip_2_ip4(addr1), ip_2_ip4(addr2), mask))
-/** @ingroup ipaddr */
-#define ip_addr_cmp(addr1, addr2)    ((IP_GET_TYPE(addr1) != IP_GET_TYPE(addr2)) ? 0 : (IP_IS_V6_VAL(*(addr1)) ? \
-  ip6_addr_cmp(ip_2_ip6(addr1), ip_2_ip6(addr2)) : \
-  ip4_addr_cmp(ip_2_ip4(addr1), ip_2_ip4(addr2))))
-/** @ingroup ipaddr */
-#define ip_addr_isany(ipaddr)        ((IP_IS_V6(ipaddr)) ? \
-  ip6_addr_isany(ip_2_ip6(ipaddr)) : \
-  ip4_addr_isany(ip_2_ip4(ipaddr)))
-/** @ingroup ipaddr */
-#define ip_addr_isany_val(ipaddr)        ((IP_IS_V6_VAL(ipaddr)) ? \
-  ip6_addr_isany_val(*ip_2_ip6(&(ipaddr))) : \
-  ip4_addr_isany_val(*ip_2_ip4(&(ipaddr))))
-/** @ingroup ipaddr */
-#define ip_addr_isbroadcast(ipaddr, netif) ((IP_IS_V6(ipaddr)) ? \
-  0 : \
-  ip4_addr_isbroadcast(ip_2_ip4(ipaddr), netif))
-/** @ingroup ipaddr */
-#define ip_addr_ismulticast(ipaddr)  ((IP_IS_V6(ipaddr)) ? \
-  ip6_addr_ismulticast(ip_2_ip6(ipaddr)) : \
-  ip4_addr_ismulticast(ip_2_ip4(ipaddr)))
-/** @ingroup ipaddr */
-#define ip_addr_isloopback(ipaddr)  ((IP_IS_V6(ipaddr)) ? \
-  ip6_addr_isloopback(ip_2_ip6(ipaddr)) : \
-  ip4_addr_isloopback(ip_2_ip4(ipaddr)))
-/** @ingroup ipaddr */
-#define ip_addr_islinklocal(ipaddr)  ((IP_IS_V6(ipaddr)) ? \
-  ip6_addr_islinklocal(ip_2_ip6(ipaddr)) : \
-  ip4_addr_islinklocal(ip_2_ip4(ipaddr)))
-#define ip_addr_debug_print(debug, ipaddr) do { if(IP_IS_V6(ipaddr)) { \
-  ip6_addr_debug_print(debug, ip_2_ip6(ipaddr)); } else { \
-  ip4_addr_debug_print(debug, ip_2_ip4(ipaddr)); }}while(0)
-#define ip_addr_debug_print_val(debug, ipaddr) do { if(IP_IS_V6_VAL(ipaddr)) { \
-  ip6_addr_debug_print_val(debug, *ip_2_ip6(&(ipaddr))); } else { \
-  ip4_addr_debug_print_val(debug, *ip_2_ip4(&(ipaddr))); }}while(0)
-/** @ingroup ipaddr */
-#define ipaddr_ntoa(addr)   (((addr) == NULL) ? "NULL" : \
-  ((IP_IS_V6(addr)) ? ip6addr_ntoa(ip_2_ip6(addr)) : ip4addr_ntoa(ip_2_ip4(addr))))
-/** @ingroup ipaddr */
-#define ipaddr_ntoa_r(addr, buf, buflen)   (((addr) == NULL) ? "NULL" : \
-  ((IP_IS_V6(addr)) ? ip6addr_ntoa_r(ip_2_ip6(addr), buf, buflen) : ip4addr_ntoa_r(ip_2_ip4(addr), buf, buflen)))
-int ipaddr_aton(const char *cp, ip_addr_t *addr);
-
-/** @ingroup ipaddr */
-#define IPADDR_STRLEN_MAX   IP6ADDR_STRLEN_MAX
-
-/** @ingroup ipaddr */
-#define ip4_2_ipv4_mapped_ipv6(ip6addr, ip4addr) do { \
-  (ip6addr)->addr[3] = (ip4addr)->addr; \
-  (ip6addr)->addr[2] = PP_HTONL(0x0000FFFFUL); \
-  (ip6addr)->addr[1] = 0; \
-  (ip6addr)->addr[0] = 0; } while(0);
-
-/** @ingroup ipaddr */
-#define unmap_ipv4_mapped_ipv6(ip4addr, ip6addr) \
-  (ip4addr)->addr = (ip6addr)->addr[3];
-
-#define IP46_ADDR_ANY(type) (((type) == IPADDR_TYPE_V6)? IP6_ADDR_ANY : IP4_ADDR_ANY)
-
-#else /* LWIP_IPV4 && LWIP_IPV6 */
-
-#define IP_ADDR_PCB_VERSION_MATCH(addr, pcb)         1
-#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) 1
-
-#if LWIP_IPV4
-
-typedef ip4_addr_t ip_addr_t;
-#define IPADDR4_INIT(u32val)                    { u32val }
-#define IPADDR4_INIT_BYTES(a,b,c,d)             IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d)))
-#define IP_IS_V4_VAL(ipaddr)                    1
-#define IP_IS_V6_VAL(ipaddr)                    0
-#define IP_IS_V4(ipaddr)                        1
-#define IP_IS_V6(ipaddr)                        0
-#define IP_IS_ANY_TYPE_VAL(ipaddr)              0
-#define IP_SET_TYPE_VAL(ipaddr, iptype)
-#define IP_SET_TYPE(ipaddr, iptype)
-#define IP_GET_TYPE(ipaddr)                     IPADDR_TYPE_V4
-#define ip_2_ip4(ipaddr)                        (ipaddr)
-#define IP_ADDR4(ipaddr,a,b,c,d)                IP4_ADDR(ipaddr,a,b,c,d)
-
-#define ip_addr_copy(dest, src)                 ip4_addr_copy(dest, src)
-#define ip_addr_copy_from_ip4(dest, src)        ip4_addr_copy(dest, src)
-#define ip_addr_set_ip4_u32(ipaddr, val)        ip4_addr_set_u32(ip_2_ip4(ipaddr), val)
-#define ip_addr_get_ip4_u32(ipaddr)             ip4_addr_get_u32(ip_2_ip4(ipaddr))
-#define ip_addr_set(dest, src)                  ip4_addr_set(dest, src)
-#define ip_addr_set_ipaddr(dest, src)           ip4_addr_set(dest, src)
-#define ip_addr_set_zero(ipaddr)                ip4_addr_set_zero(ipaddr)
-#define ip_addr_set_zero_ip4(ipaddr)            ip4_addr_set_zero(ipaddr)
-#define ip_addr_set_any(is_ipv6, ipaddr)        ip4_addr_set_any(ipaddr)
-#define ip_addr_set_loopback(is_ipv6, ipaddr)   ip4_addr_set_loopback(ipaddr)
-#define ip_addr_set_hton(dest, src)             ip4_addr_set_hton(dest, src)
-#define ip_addr_get_network(target, host, mask) ip4_addr_get_network(target, host, mask)
-#define ip_addr_netcmp(addr1, addr2, mask)      ip4_addr_netcmp(addr1, addr2, mask)
-#define ip_addr_cmp(addr1, addr2)               ip4_addr_cmp(addr1, addr2)
-#define ip_addr_isany(ipaddr)                   ip4_addr_isany(ipaddr)
-#define ip_addr_isany_val(ipaddr)               ip4_addr_isany_val(ipaddr)
-#define ip_addr_isloopback(ipaddr)              ip4_addr_isloopback(ipaddr)
-#define ip_addr_islinklocal(ipaddr)             ip4_addr_islinklocal(ipaddr)
-#define ip_addr_isbroadcast(addr, netif)        ip4_addr_isbroadcast(addr, netif)
-#define ip_addr_ismulticast(ipaddr)             ip4_addr_ismulticast(ipaddr)
-#define ip_addr_debug_print(debug, ipaddr)      ip4_addr_debug_print(debug, ipaddr)
-#define ip_addr_debug_print_val(debug, ipaddr)  ip4_addr_debug_print_val(debug, ipaddr)
-#define ipaddr_ntoa(ipaddr)                     ip4addr_ntoa(ipaddr)
-#define ipaddr_ntoa_r(ipaddr, buf, buflen)      ip4addr_ntoa_r(ipaddr, buf, buflen)
-#define ipaddr_aton(cp, addr)                   ip4addr_aton(cp, addr)
-
-#define IPADDR_STRLEN_MAX   IP4ADDR_STRLEN_MAX
-
-#define IP46_ADDR_ANY(type) (IP4_ADDR_ANY)
-
-#else /* LWIP_IPV4 */
-
-typedef ip6_addr_t ip_addr_t;
-#define IPADDR6_INIT(a, b, c, d)                { { a, b, c, d } }
-#define IPADDR6_INIT_HOST(a, b, c, d)           { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } }
-#define IP_IS_V4_VAL(ipaddr)                    0
-#define IP_IS_V6_VAL(ipaddr)                    1
-#define IP_IS_V4(ipaddr)                        0
-#define IP_IS_V6(ipaddr)                        1
-#define IP_IS_ANY_TYPE_VAL(ipaddr)              0
-#define IP_SET_TYPE_VAL(ipaddr, iptype)
-#define IP_SET_TYPE(ipaddr, iptype)
-#define IP_GET_TYPE(ipaddr)                     IPADDR_TYPE_V6
-#define ip_2_ip6(ipaddr)                        (ipaddr)
-#define IP_ADDR6(ipaddr,i0,i1,i2,i3)            IP6_ADDR(ipaddr,i0,i1,i2,i3)
-#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3)       IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3))
-
-#define ip_addr_copy(dest, src)                 ip6_addr_copy(dest, src)
-#define ip_addr_copy_from_ip6(dest, src)        ip6_addr_copy(dest, src)
-#define ip_addr_set(dest, src)                  ip6_addr_set(dest, src)
-#define ip_addr_set_ipaddr(dest, src)           ip6_addr_set(dest, src)
-#define ip_addr_set_zero(ipaddr)                ip6_addr_set_zero(ipaddr)
-#define ip_addr_set_zero_ip6(ipaddr)            ip6_addr_set_zero(ipaddr)
-#define ip_addr_set_any(is_ipv6, ipaddr)        ip6_addr_set_any(ipaddr)
-#define ip_addr_set_loopback(is_ipv6, ipaddr)   ip6_addr_set_loopback(ipaddr)
-#define ip_addr_set_hton(dest, src)             ip6_addr_set_hton(dest, src)
-#define ip_addr_get_network(target, host, mask) ip6_addr_set_zero(target)
-#define ip_addr_netcmp(addr1, addr2, mask)      0
-#define ip_addr_cmp(addr1, addr2)               ip6_addr_cmp(addr1, addr2)
-#define ip_addr_isany(ipaddr)                   ip6_addr_isany(ipaddr)
-#define ip_addr_isany_val(ipaddr)               ip6_addr_isany_val(ipaddr)
-#define ip_addr_isloopback(ipaddr)              ip6_addr_isloopback(ipaddr)
-#define ip_addr_islinklocal(ipaddr)             ip6_addr_islinklocal(ipaddr)
-#define ip_addr_isbroadcast(addr, netif)        0
-#define ip_addr_ismulticast(ipaddr)             ip6_addr_ismulticast(ipaddr)
-#define ip_addr_debug_print(debug, ipaddr)      ip6_addr_debug_print(debug, ipaddr)
-#define ip_addr_debug_print_val(debug, ipaddr)  ip6_addr_debug_print_val(debug, ipaddr)
-#define ipaddr_ntoa(ipaddr)                     ip6addr_ntoa(ipaddr)
-#define ipaddr_ntoa_r(ipaddr, buf, buflen)      ip6addr_ntoa_r(ipaddr, buf, buflen)
-#define ipaddr_aton(cp, addr)                   ip6addr_aton(cp, addr)
-
-#define IPADDR_STRLEN_MAX   IP6ADDR_STRLEN_MAX
-
-#define IP46_ADDR_ANY(type) (IP6_ADDR_ANY)
-
-#endif /* LWIP_IPV4 */
-#endif /* LWIP_IPV4 && LWIP_IPV6 */
-
-#if LWIP_IPV4
-
-extern const ip_addr_t ip_addr_any;
-extern const ip_addr_t ip_addr_broadcast;
-
-/**
- * @ingroup ip4addr
- * Can be used as a fixed/const ip_addr_t
- * for the IP wildcard.
- * Defined to @ref IP4_ADDR_ANY when IPv4 is enabled.
- * Defined to @ref IP6_ADDR_ANY in IPv6 only systems.
- * Use this if you can handle IPv4 _AND_ IPv6 addresses.
- * Use @ref IP4_ADDR_ANY or @ref IP6_ADDR_ANY when the IP
- * type matters.
- */
-#define IP_ADDR_ANY         IP4_ADDR_ANY
-/**
- * @ingroup ip4addr
- * Can be used as a fixed/const ip_addr_t
- * for the IPv4 wildcard and the broadcast address
- */
-#define IP4_ADDR_ANY        (&ip_addr_any)
-/**
- * @ingroup ip4addr
- * Can be used as a fixed/const ip4_addr_t
- * for the wildcard and the broadcast address
- */
-#define IP4_ADDR_ANY4       (ip_2_ip4(&ip_addr_any))
-
-/** @ingroup ip4addr */
-#define IP_ADDR_BROADCAST   (&ip_addr_broadcast)
-/** @ingroup ip4addr */
-#define IP4_ADDR_BROADCAST  (ip_2_ip4(&ip_addr_broadcast))
-
-#endif /* LWIP_IPV4*/
-
-#if LWIP_IPV6
-
-extern const ip_addr_t ip6_addr_any;
-
-/** 
- * @ingroup ip6addr
- * IP6_ADDR_ANY can be used as a fixed ip_addr_t
- * for the IPv6 wildcard address
- */
-#define IP6_ADDR_ANY   (&ip6_addr_any)
-/**
- * @ingroup ip6addr
- * IP6_ADDR_ANY6 can be used as a fixed ip6_addr_t
- * for the IPv6 wildcard address
- */
-#define IP6_ADDR_ANY6  (ip_2_ip6(&ip6_addr_any))
-
-#if !LWIP_IPV4
-/** IPv6-only configurations */
-#define IP_ADDR_ANY IP6_ADDR_ANY
-#endif /* !LWIP_IPV4 */
-
-#endif
-
-#if LWIP_IPV4 && LWIP_IPV6
-/** @ingroup ipaddr */
-#define IP_ANY_TYPE    (&ip_addr_any_type)
-#else
-#define IP_ANY_TYPE    IP_ADDR_ANY
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_IP_ADDR_H */
diff --git a/tools/sdk/include/lwip/lwip/mem.h b/tools/sdk/include/lwip/lwip/mem.h
deleted file mode 100644
index ff208d25c32..00000000000
--- a/tools/sdk/include/lwip/lwip/mem.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/**
- * @file
- * Heap API
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_MEM_H
-#define LWIP_HDR_MEM_H
-
-#include "lwip/opt.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if MEM_LIBC_MALLOC
-
-#include "lwip/arch.h"
-
-typedef size_t mem_size_t;
-#define MEM_SIZE_F SZT_F
-
-#elif MEM_USE_POOLS
-
-typedef u16_t mem_size_t;
-#define MEM_SIZE_F U16_F
-
-#else
-
-/* MEM_SIZE would have to be aligned, but using 64000 here instead of
- * 65535 leaves some room for alignment...
- */
-#if MEM_SIZE > 64000L
-typedef u32_t mem_size_t;
-#define MEM_SIZE_F U32_F
-#else
-typedef u16_t mem_size_t;
-#define MEM_SIZE_F U16_F
-#endif /* MEM_SIZE > 64000 */
-#endif
-
-void  mem_init(void);
-void *mem_trim(void *mem, mem_size_t size);
-void *mem_malloc(mem_size_t size);
-void *mem_calloc(mem_size_t count, mem_size_t size);
-void  mem_free(void *mem);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_MEM_H */
diff --git a/tools/sdk/include/lwip/lwip/memp.h b/tools/sdk/include/lwip/lwip/memp.h
deleted file mode 100644
index 562cd05bffd..00000000000
--- a/tools/sdk/include/lwip/lwip/memp.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/**
- * @file
- * Memory pool API
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-#ifndef LWIP_HDR_MEMP_H
-#define LWIP_HDR_MEMP_H
-
-#include "lwip/opt.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* run once with empty definition to handle all custom includes in lwippools.h */
-#define LWIP_MEMPOOL(name,num,size,desc)
-#include "lwip/priv/memp_std.h"
-
-/** Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */
-typedef enum {
-#define LWIP_MEMPOOL(name,num,size,desc)  MEMP_##name,
-#include "lwip/priv/memp_std.h"
-  MEMP_MAX
-} memp_t;
-
-#include "lwip/priv/memp_priv.h"
-#include "lwip/stats.h"
-
-extern const struct memp_desc* const memp_pools[MEMP_MAX];
-
-/**
- * @ingroup mempool
- * Declare prototype for private memory pool if it is used in multiple files
- */
-#define LWIP_MEMPOOL_PROTOTYPE(name) extern const struct memp_desc memp_ ## name
-
-#if MEMP_MEM_MALLOC
-
-#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \
-  LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \
-  const struct memp_desc memp_ ## name = { \
-    DECLARE_LWIP_MEMPOOL_DESC(desc) \
-    LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \
-    LWIP_MEM_ALIGN_SIZE(size) \
-  };
-
-#else /* MEMP_MEM_MALLOC */
-
-/**
- * @ingroup mempool
- * Declare a private memory pool
- * Private mempools example:
- * .h: only when pool is used in multiple .c files: LWIP_MEMPOOL_PROTOTYPE(my_private_pool);
- * .c:
- *   - in global variables section: LWIP_MEMPOOL_DECLARE(my_private_pool, 10, sizeof(foo), "Some description")
- *   - call ONCE before using pool (e.g. in some init() function): LWIP_MEMPOOL_INIT(my_private_pool);
- *   - allocate: void* my_new_mem = LWIP_MEMPOOL_ALLOC(my_private_pool);
- *   - free: LWIP_MEMPOOL_FREE(my_private_pool, my_new_mem);
- *
- * To relocate a pool, declare it as extern in cc.h. Example for GCC:
- *   extern u8_t __attribute__((section(".onchip_mem"))) memp_memory_my_private_pool[];
- */
-#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \
-  LWIP_DECLARE_MEMORY_ALIGNED(memp_memory_ ## name ## _base, ((num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size)))); \
-    \
-  LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \
-    \
-  static struct memp *memp_tab_ ## name; \
-    \
-  const struct memp_desc memp_ ## name = { \
-    DECLARE_LWIP_MEMPOOL_DESC(desc) \
-    LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \
-    LWIP_MEM_ALIGN_SIZE(size), \
-    (num), \
-    memp_memory_ ## name ## _base, \
-    &memp_tab_ ## name \
-  };
-
-#endif /* MEMP_MEM_MALLOC */
-
-/**
- * @ingroup mempool
- * Initialize a private memory pool
- */
-#define LWIP_MEMPOOL_INIT(name)    memp_init_pool(&memp_ ## name)
-/**
- * @ingroup mempool
- * Allocate from a private memory pool
- */
-#define LWIP_MEMPOOL_ALLOC(name)   memp_malloc_pool(&memp_ ## name)
-/**
- * @ingroup mempool
- * Free element from a private memory pool
- */
-#define LWIP_MEMPOOL_FREE(name, x) memp_free_pool(&memp_ ## name, (x))
-
-#if MEM_USE_POOLS
-/** This structure is used to save the pool one element came from.
- * This has to be defined here as it is required for pool size calculation. */
-struct memp_malloc_helper
-{
-   memp_t poolnr;
-#if MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS)
-   u16_t size;
-#endif /* MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) */
-};
-#endif /* MEM_USE_POOLS */
-
-void  memp_init(void);
-
-#if MEMP_OVERFLOW_CHECK
-void *memp_malloc_fn(memp_t type, const char* file, const int line);
-#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__)
-#else
-void *memp_malloc(memp_t type);
-#endif
-void  memp_free(memp_t type, void *mem);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_MEMP_H */
diff --git a/tools/sdk/include/lwip/lwip/mld6.h b/tools/sdk/include/lwip/lwip/mld6.h
deleted file mode 100644
index 7fa0797f272..00000000000
--- a/tools/sdk/include/lwip/lwip/mld6.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- * @file
- *
- * Multicast listener discovery for IPv6. Aims to be compliant with RFC 2710.
- * No support for MLDv2.
- */
-
-/*
- * Copyright (c) 2010 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-
-#ifndef LWIP_HDR_MLD6_H
-#define LWIP_HDR_MLD6_H
-
-#include "lwip/opt.h"
-
-#if LWIP_IPV6_MLD && LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/pbuf.h"
-#include "lwip/netif.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** MLD group */
-struct mld_group {
-  /** next link */
-  struct mld_group *next;
-  /** multicast address */
-  ip6_addr_t         group_address;
-  /** signifies we were the last person to report */
-  u8_t               last_reporter_flag;
-  /** current state of the group */
-  u8_t               group_state;
-  /** timer for reporting */
-  u16_t              timer;
-  /** counter of simultaneous uses */
-  u8_t               use;
-};
-
-#define MLD6_TMR_INTERVAL              100 /* Milliseconds */
-
-err_t  mld6_stop(struct netif *netif);
-void   mld6_report_groups(struct netif *netif);
-void   mld6_tmr(void);
-struct mld_group *mld6_lookfor_group(struct netif *ifp, const ip6_addr_t *addr);
-void   mld6_input(struct pbuf *p, struct netif *inp);
-err_t  mld6_joingroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr);
-err_t  mld6_joingroup_netif(struct netif *netif, const ip6_addr_t *groupaddr);
-err_t  mld6_leavegroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr);
-err_t  mld6_leavegroup_netif(struct netif *netif, const ip6_addr_t *groupaddr);
-
-/** @ingroup mld6
- * Get list head of MLD6 groups for netif.
- * Note: The allnodes group IP is NOT in the list, since it must always 
- * be received for correct IPv6 operation.
- * @see @ref netif_set_mld_mac_filter()
- */
-#define netif_mld6_data(netif) ((struct mld_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV6_MLD && LWIP_IPV6 */
-
-#endif /* LWIP_HDR_MLD6_H */
diff --git a/tools/sdk/include/lwip/lwip/nd6.h b/tools/sdk/include/lwip/lwip/nd6.h
deleted file mode 100644
index d9fba970729..00000000000
--- a/tools/sdk/include/lwip/lwip/nd6.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/**
- * @file
- *
- * Neighbor discovery and stateless address autoconfiguration for IPv6.
- * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862
- * (Address autoconfiguration).
- */
-
-/*
- * Copyright (c) 2010 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-
-#ifndef LWIP_HDR_ND6_H
-#define LWIP_HDR_ND6_H
-
-#include "lwip/opt.h"
-
-#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/ip6_addr.h"
-#include "lwip/err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** 1 second period */
-#define ND6_TMR_INTERVAL 1000
-
-struct pbuf;
-struct netif;
-
-void nd6_tmr(void);
-void nd6_input(struct pbuf *p, struct netif *inp);
-void nd6_clear_destination_cache(void);
-struct netif *nd6_find_route(const ip6_addr_t *ip6addr);
-err_t nd6_get_next_hop_addr_or_queue(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr, const u8_t **hwaddrp);
-u16_t nd6_get_destination_mtu(const ip6_addr_t *ip6addr, struct netif *netif);
-#if LWIP_ND6_TCP_REACHABILITY_HINTS
-void nd6_reachability_hint(const ip6_addr_t *ip6addr);
-#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */
-void nd6_cleanup_netif(struct netif *netif);
-#if LWIP_IPV6_MLD
-void nd6_adjust_mld_membership(struct netif *netif, s8_t addr_idx, u8_t new_state);
-#endif /* LWIP_IPV6_MLD */
-
-#if ESP_LWIP
-/** set nd6 callback when ipv6 addr state pref*/
-void nd6_set_cb(struct netif *netif, void (*cb)(struct netif *netif, u8_t ip_index));
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV6 */
-
-#endif /* LWIP_HDR_ND6_H */
diff --git a/tools/sdk/include/lwip/lwip/netbuf.h b/tools/sdk/include/lwip/lwip/netbuf.h
deleted file mode 100644
index e6865f80f94..00000000000
--- a/tools/sdk/include/lwip/lwip/netbuf.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/**
- * @file
- * netbuf API (for netconn API)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_NETBUF_H
-#define LWIP_HDR_NETBUF_H
-
-#include "lwip/opt.h"
-
-#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
-/* Note: Netconn API is always available when sockets are enabled -
- * sockets are implemented on top of them */
-
-#include "lwip/pbuf.h"
-#include "lwip/ip_addr.h"
-#include "lwip/ip6_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** This netbuf has dest-addr/port set */
-#define NETBUF_FLAG_DESTADDR    0x01
-/** This netbuf includes a checksum */
-#define NETBUF_FLAG_CHKSUM      0x02
-
-/** "Network buffer" - contains data and addressing info */
-struct netbuf {
-  struct pbuf *p, *ptr;
-  ip_addr_t addr;
-  u16_t port;
-#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY
-#if LWIP_CHECKSUM_ON_COPY
-  u8_t flags;
-#endif /* LWIP_CHECKSUM_ON_COPY */
-  u16_t toport_chksum;
-#if LWIP_NETBUF_RECVINFO
-  ip_addr_t toaddr;
-#endif /* LWIP_NETBUF_RECVINFO */
-#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */
-};
-
-/* Network buffer functions: */
-struct netbuf *   netbuf_new      (void);
-void              netbuf_delete   (struct netbuf *buf);
-void *            netbuf_alloc    (struct netbuf *buf, u16_t size);
-void              netbuf_free     (struct netbuf *buf);
-err_t             netbuf_ref      (struct netbuf *buf,
-                                   const void *dataptr, u16_t size);
-void              netbuf_chain    (struct netbuf *head, struct netbuf *tail);
-
-err_t             netbuf_data     (struct netbuf *buf,
-                                   void **dataptr, u16_t *len);
-s8_t              netbuf_next     (struct netbuf *buf);
-void              netbuf_first    (struct netbuf *buf);
-
-
-#define netbuf_copy_partial(buf, dataptr, len, offset) \
-  pbuf_copy_partial((buf)->p, (dataptr), (len), (offset))
-#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0)
-#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len)
-#define netbuf_len(buf)              ((buf)->p->tot_len)
-#define netbuf_fromaddr(buf)         (&((buf)->addr))
-#define netbuf_set_fromaddr(buf, fromaddr) ip_addr_set(&((buf)->addr), fromaddr)
-#define netbuf_fromport(buf)         ((buf)->port)
-#if LWIP_NETBUF_RECVINFO
-#define netbuf_destaddr(buf)         (&((buf)->toaddr))
-#define netbuf_set_destaddr(buf, destaddr) ip_addr_set(&((buf)->toaddr), destaddr)
-#if LWIP_CHECKSUM_ON_COPY
-#define netbuf_destport(buf)         (((buf)->flags & NETBUF_FLAG_DESTADDR) ? (buf)->toport_chksum : 0)
-#else /* LWIP_CHECKSUM_ON_COPY */
-#define netbuf_destport(buf)         ((buf)->toport_chksum)
-#endif /* LWIP_CHECKSUM_ON_COPY */
-#endif /* LWIP_NETBUF_RECVINFO */
-#if LWIP_CHECKSUM_ON_COPY
-#define netbuf_set_chksum(buf, chksum) do { (buf)->flags = NETBUF_FLAG_CHKSUM; \
-                                            (buf)->toport_chksum = chksum; } while(0)
-#endif /* LWIP_CHECKSUM_ON_COPY */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_NETCONN || LWIP_SOCKET */
-
-#endif /* LWIP_HDR_NETBUF_H */
diff --git a/tools/sdk/include/lwip/lwip/netdb.h b/tools/sdk/include/lwip/lwip/netdb.h
deleted file mode 100644
index e0b07accc9d..00000000000
--- a/tools/sdk/include/lwip/lwip/netdb.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * @file
- * NETDB API (sockets)
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Simon Goldschmidt
- *
- */
-#ifndef LWIP_HDR_NETDB_H
-#define LWIP_HDR_NETDB_H
-
-#include "lwip/opt.h"
-
-#if LWIP_DNS && LWIP_SOCKET
-
-#include "lwip/arch.h"
-#include "lwip/inet.h"
-#include "lwip/sockets.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* some rarely used options */
-#ifndef LWIP_DNS_API_DECLARE_H_ERRNO
-#define LWIP_DNS_API_DECLARE_H_ERRNO  1
-#endif
-
-#ifndef LWIP_DNS_API_DEFINE_ERRORS
-#define LWIP_DNS_API_DEFINE_ERRORS    1
-#endif
-
-#ifndef LWIP_DNS_API_DEFINE_FLAGS
-#define LWIP_DNS_API_DEFINE_FLAGS     1
-#endif
-
-#ifndef LWIP_DNS_API_DECLARE_STRUCTS
-#define LWIP_DNS_API_DECLARE_STRUCTS  1
-#endif
-
-#if LWIP_DNS_API_DEFINE_ERRORS
-/** Errors used by the DNS API functions, h_errno can be one of them */
-#define EAI_NONAME      200
-#define EAI_SERVICE     201
-#define EAI_FAIL        202
-#define EAI_MEMORY      203
-#define EAI_FAMILY      204
-
-#define HOST_NOT_FOUND  210
-#define NO_DATA         211
-#define NO_RECOVERY     212
-#define TRY_AGAIN       213
-#endif /* LWIP_DNS_API_DEFINE_ERRORS */
-
-#if LWIP_DNS_API_DEFINE_FLAGS
-/* input flags for struct addrinfo */
-#define AI_PASSIVE      0x01
-#define AI_CANONNAME    0x02
-#define AI_NUMERICHOST  0x04
-#define AI_NUMERICSERV  0x08
-#define AI_V4MAPPED     0x10
-#define AI_ALL          0x20
-#define AI_ADDRCONFIG   0x40
-#endif /* LWIP_DNS_API_DEFINE_FLAGS */
-
-#if LWIP_DNS_API_DECLARE_STRUCTS
-struct hostent {
-    char  *h_name;      /* Official name of the host. */
-    char **h_aliases;   /* A pointer to an array of pointers to alternative host names,
-                           terminated by a null pointer. */
-    int    h_addrtype;  /* Address type. */
-    int    h_length;    /* The length, in bytes, of the address. */
-    char **h_addr_list; /* A pointer to an array of pointers to network addresses (in
-                           network byte order) for the host, terminated by a null pointer. */
-#define h_addr h_addr_list[0] /* for backward compatibility */
-};
-
-struct addrinfo {
-    int               ai_flags;      /* Input flags. */
-    int               ai_family;     /* Address family of socket. */
-    int               ai_socktype;   /* Socket type. */
-    int               ai_protocol;   /* Protocol of socket. */
-    socklen_t         ai_addrlen;    /* Length of socket address. */
-    struct sockaddr  *ai_addr;       /* Socket address of socket. */
-    char             *ai_canonname;  /* Canonical name of service location. */
-    struct addrinfo  *ai_next;       /* Pointer to next in list. */
-};
-#endif /* LWIP_DNS_API_DECLARE_STRUCTS */
-
-#define NETDB_ELEM_SIZE           (sizeof(struct addrinfo) + sizeof(struct sockaddr_storage) + DNS_MAX_NAME_LENGTH + 1)
-
-#if LWIP_DNS_API_DECLARE_H_ERRNO
-/* application accessible error code set by the DNS API functions */
-extern int h_errno;
-#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/
-
-struct hostent *lwip_gethostbyname(const char *name);
-int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
-                size_t buflen, struct hostent **result, int *h_errnop);
-void lwip_freeaddrinfo(struct addrinfo *ai);
-int lwip_getaddrinfo(const char *nodename,
-       const char *servname,
-       const struct addrinfo *hints,
-       struct addrinfo **res);
-
-#if LWIP_COMPAT_SOCKETS
-#if ESP_LWIP
-#if LWIP_COMPAT_SOCKET_ADDR == 1
-/* Some libraries have problems with inet_... being macros, so please use this define 
-   to declare normal functions */
-static inline int gethostbyname_r(const char *name, struct hostent *ret, char *buf, size_t buflen, struct hostent **result, int *h_errnop)
-{ return lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop); }
-static inline struct hostent *gethostbyname(const char *name)
-{ return lwip_gethostbyname(name); }
-static inline void freeaddrinfo(struct addrinfo *ai)
-{ lwip_freeaddrinfo(ai); }
-static inline int getaddrinfo(const char *nodename, const char *servname, const struct addrinfo *hints, struct addrinfo **res)
-{ return lwip_getaddrinfo(nodename, servname, hints, res); }
-#else
-/* By default fall back to original inet_... macros */
-
-/** @ingroup netdbapi */
-#define gethostbyname(name) lwip_gethostbyname(name)
-/** @ingroup netdbapi */
-#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \
-       lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop)
-/** @ingroup netdbapi */
-#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo)
-/** @ingroup netdbapi */
-#define getaddrinfo(nodname, servname, hints, res) \
-       lwip_getaddrinfo(nodname, servname, hints, res)
-#endif /* LWIP_COMPAT_SOCKET_ADDR == 1 */
-
-#else /* ESP_LWIP */
-
-/** @ingroup netdbapi */
-#define gethostbyname(name) lwip_gethostbyname(name)
-/** @ingroup netdbapi */
-#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \
-       lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop)
-/** @ingroup netdbapi */
-#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo)
-/** @ingroup netdbapi */
-#define getaddrinfo(nodname, servname, hints, res) \
-       lwip_getaddrinfo(nodname, servname, hints, res)
-
-#endif /* ESP_LWIP */
-#endif /* LWIP_COMPAT_SOCKETS */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_DNS && LWIP_SOCKET */
-
-#endif /* LWIP_HDR_NETDB_H */
diff --git a/tools/sdk/include/lwip/lwip/netif.h b/tools/sdk/include/lwip/lwip/netif.h
deleted file mode 100644
index bcc9c5b1d0b..00000000000
--- a/tools/sdk/include/lwip/lwip/netif.h
+++ /dev/null
@@ -1,508 +0,0 @@
-/**
- * @file
- * netif API (to be used from TCPIP thread)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_NETIF_H
-#define LWIP_HDR_NETIF_H
-
-#include "lwip/opt.h"
-
-#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF)
-
-#include "lwip/err.h"
-
-#include "lwip/ip_addr.h"
-
-#include "lwip/def.h"
-#include "lwip/pbuf.h"
-#include "lwip/stats.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Throughout this file, IP addresses are expected to be in
- * the same byte order as in IP_PCB. */
-
-/** Must be the maximum of all used hardware address lengths
-    across all types of interfaces in use.
-    This does not have to be changed, normally. */
-#ifndef NETIF_MAX_HWADDR_LEN
-#define NETIF_MAX_HWADDR_LEN 6U
-#endif
-
-/**
- * @defgroup netif_flags Flags
- * @ingroup netif
- * @{
- */
-
-/** Whether the network interface is 'up'. This is
- * a software flag used to control whether this network
- * interface is enabled and processes traffic.
- * It must be set by the startup code before this netif can be used
- * (also for dhcp/autoip).
- */
-#define NETIF_FLAG_UP           0x01U
-/** If set, the netif has broadcast capability.
- * Set by the netif driver in its init function. */
-#define NETIF_FLAG_BROADCAST    0x02U
-/** If set, the interface has an active link
- *  (set by the network interface driver).
- * Either set by the netif driver in its init function (if the link
- * is up at that time) or at a later point once the link comes up
- * (if link detection is supported by the hardware). */
-#define NETIF_FLAG_LINK_UP      0x04U
-/** If set, the netif is an ethernet device using ARP.
- * Set by the netif driver in its init function.
- * Used to check input packet types and use of DHCP. */
-#define NETIF_FLAG_ETHARP       0x08U
-/** If set, the netif is an ethernet device. It might not use
- * ARP or TCP/IP if it is used for PPPoE only.
- */
-#define NETIF_FLAG_ETHERNET     0x10U
-/** If set, the netif has IGMP capability.
- * Set by the netif driver in its init function. */
-#define NETIF_FLAG_IGMP         0x20U
-/** If set, the netif has MLD6 capability.
- * Set by the netif driver in its init function. */
-#define NETIF_FLAG_MLD6         0x40U
-
-#if ESP_GRATUITOUS_ARP
-/** If set, the netif will send gratuitous ARP periodically */
-#define NETIF_FLAG_GARP         0x80U
-#endif
-
-/**
- * @}
- */
-
-enum lwip_internal_netif_client_data_index
-{
-#if LWIP_DHCP
-   LWIP_NETIF_CLIENT_DATA_INDEX_DHCP,
-#endif
-#if LWIP_AUTOIP
-   LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP,
-#endif
-#if LWIP_IGMP
-   LWIP_NETIF_CLIENT_DATA_INDEX_IGMP,
-#endif
-#if LWIP_IPV6_MLD
-   LWIP_NETIF_CLIENT_DATA_INDEX_MLD6,
-#endif
-   LWIP_NETIF_CLIENT_DATA_INDEX_MAX
-};
-
-#if LWIP_CHECKSUM_CTRL_PER_NETIF
-#define NETIF_CHECKSUM_GEN_IP       0x0001
-#define NETIF_CHECKSUM_GEN_UDP      0x0002
-#define NETIF_CHECKSUM_GEN_TCP      0x0004
-#define NETIF_CHECKSUM_GEN_ICMP     0x0008
-#define NETIF_CHECKSUM_GEN_ICMP6    0x0010
-#define NETIF_CHECKSUM_CHECK_IP     0x0100
-#define NETIF_CHECKSUM_CHECK_UDP    0x0200
-#define NETIF_CHECKSUM_CHECK_TCP    0x0400
-#define NETIF_CHECKSUM_CHECK_ICMP   0x0800
-#define NETIF_CHECKSUM_CHECK_ICMP6  0x1000
-#define NETIF_CHECKSUM_ENABLE_ALL   0xFFFF
-#define NETIF_CHECKSUM_DISABLE_ALL  0x0000
-#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
-
-struct netif;
-
-/** MAC Filter Actions, these are passed to a netif's igmp_mac_filter or
- * mld_mac_filter callback function. */
-enum netif_mac_filter_action {
-  /** Delete a filter entry */
-  NETIF_DEL_MAC_FILTER = 0,
-  /** Add a filter entry */
-  NETIF_ADD_MAC_FILTER = 1
-};
-
-/** Function prototype for netif init functions. Set up flags and output/linkoutput
- * callback functions in this function.
- *
- * @param netif The netif to initialize
- */
-typedef err_t (*netif_init_fn)(struct netif *netif);
-/** Function prototype for netif->input functions. This function is saved as 'input'
- * callback function in the netif struct. Call it when a packet has been received.
- *
- * @param p The received packet, copied into a pbuf
- * @param inp The netif which received the packet
- */
-typedef err_t (*netif_input_fn)(struct pbuf *p, struct netif *inp);
-
-#if LWIP_IPV4
-/** Function prototype for netif->output functions. Called by lwIP when a packet
- * shall be sent. For ethernet netif, set this to 'etharp_output' and set
- * 'linkoutput'.
- *
- * @param netif The netif which shall send a packet
- * @param p The packet to send (p->payload points to IP header)
- * @param ipaddr The IP address to which the packet shall be sent
- */
-typedef err_t (*netif_output_fn)(struct netif *netif, struct pbuf *p,
-       const ip4_addr_t *ipaddr);
-#endif /* LWIP_IPV4*/
-
-#if LWIP_IPV6
-/** Function prototype for netif->output_ip6 functions. Called by lwIP when a packet
- * shall be sent. For ethernet netif, set this to 'ethip6_output' and set
- * 'linkoutput'.
- *
- * @param netif The netif which shall send a packet
- * @param p The packet to send (p->payload points to IP header)
- * @param ipaddr The IPv6 address to which the packet shall be sent
- */
-typedef err_t (*netif_output_ip6_fn)(struct netif *netif, struct pbuf *p,
-       const ip6_addr_t *ipaddr);
-#endif /* LWIP_IPV6 */
-
-/** Function prototype for netif->linkoutput functions. Only used for ethernet
- * netifs. This function is called by ARP when a packet shall be sent.
- *
- * @param netif The netif which shall send a packet
- * @param p The packet to send (raw ethernet packet)
- */
-typedef err_t (*netif_linkoutput_fn)(struct netif *netif, struct pbuf *p);
-/** Function prototype for netif status- or link-callback functions. */
-typedef void (*netif_status_callback_fn)(struct netif *netif);
-#if LWIP_IPV4 && LWIP_IGMP
-/** Function prototype for netif igmp_mac_filter functions */
-typedef err_t (*netif_igmp_mac_filter_fn)(struct netif *netif,
-       const ip4_addr_t *group, enum netif_mac_filter_action action);
-#endif /* LWIP_IPV4 && LWIP_IGMP */
-#if LWIP_IPV6 && LWIP_IPV6_MLD
-/** Function prototype for netif mld_mac_filter functions */
-typedef err_t (*netif_mld_mac_filter_fn)(struct netif *netif,
-       const ip6_addr_t *group, enum netif_mac_filter_action action);
-#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
-
-#if LWIP_DHCP || LWIP_AUTOIP || LWIP_IGMP || LWIP_IPV6_MLD || (LWIP_NUM_NETIF_CLIENT_DATA > 0)
-u8_t netif_alloc_client_data_id(void);
-/** @ingroup netif_cd
- * Set client data. Obtain ID from netif_alloc_client_data_id().
- */
-#define netif_set_client_data(netif, id, data) netif_get_client_data(netif, id) = (data)
-/** @ingroup netif_cd
- * Get client data. Obtain ID from netif_alloc_client_data_id().
- */
-#define netif_get_client_data(netif, id)       (netif)->client_data[(id)]
-#endif /* LWIP_DHCP || LWIP_AUTOIP || (LWIP_NUM_NETIF_CLIENT_DATA > 0) */
-
-#if ESP_DHCP
-/*add DHCP event processing by LiuHan*/
-typedef void (*dhcp_event_fn)(void);
-#endif
-
-/** Generic data structure used for all lwIP network interfaces.
- *  The following fields should be filled in by the initialization
- *  function for the device driver: hwaddr_len, hwaddr[], mtu, flags */
-struct netif {
-  /** pointer to next in linked list */
-  struct netif *next;
-
-#if LWIP_IPV4
-  /** IP address configuration in network byte order */
-  ip_addr_t ip_addr;
-  ip_addr_t netmask;
-  ip_addr_t gw;
-#endif /* LWIP_IPV4 */
-#if LWIP_IPV6
-  /** Array of IPv6 addresses for this netif. */
-  ip_addr_t ip6_addr[LWIP_IPV6_NUM_ADDRESSES];
-  /** The state of each IPv6 address (Tentative, Preferred, etc).
-   * @see ip6_addr.h */
-  u8_t ip6_addr_state[LWIP_IPV6_NUM_ADDRESSES];
-#if ESP_LWIP
-  void (*ipv6_addr_cb)(struct netif* netif, u8_t ip_idex); /* callback for ipv6 addr states changed */
-#endif
-
-#endif /* LWIP_IPV6 */
-  /** This function is called by the network device driver
-   *  to pass a packet up the TCP/IP stack. */
-  netif_input_fn input;
-#if LWIP_IPV4
-  /** This function is called by the IP module when it wants
-   *  to send a packet on the interface. This function typically
-   *  first resolves the hardware address, then sends the packet.
-   *  For ethernet physical layer, this is usually etharp_output() */
-  netif_output_fn output;
-#endif /* LWIP_IPV4 */
-  /** This function is called by ethernet_output() when it wants
-   *  to send a packet on the interface. This function outputs
-   *  the pbuf as-is on the link medium. */
-  netif_linkoutput_fn linkoutput;
-#if LWIP_IPV6
-  /** This function is called by the IPv6 module when it wants
-   *  to send a packet on the interface. This function typically
-   *  first resolves the hardware address, then sends the packet.
-   *  For ethernet physical layer, this is usually ethip6_output() */
-  netif_output_ip6_fn output_ip6;
-#endif /* LWIP_IPV6 */
-#if LWIP_NETIF_STATUS_CALLBACK
-  /** This function is called when the netif state is set to up or down
-   */
-  netif_status_callback_fn status_callback;
-#endif /* LWIP_NETIF_STATUS_CALLBACK */
-#if LWIP_NETIF_LINK_CALLBACK
-  /** This function is called when the netif link is set to up or down
-   */
-  netif_status_callback_fn link_callback;
-#endif /* LWIP_NETIF_LINK_CALLBACK */
-#if LWIP_NETIF_REMOVE_CALLBACK
-  /** This function is called when the netif has been removed */
-  netif_status_callback_fn remove_callback;
-#endif /* LWIP_NETIF_REMOVE_CALLBACK */
-  /** This field can be set by the device driver and could point
-   *  to state information for the device. */
-  void *state;
-#ifdef netif_get_client_data
-  void* client_data[LWIP_NETIF_CLIENT_DATA_INDEX_MAX + LWIP_NUM_NETIF_CLIENT_DATA];
-#endif
-
-#if ESP_DHCP
-  struct udp_pcb *dhcps_pcb;	
-  dhcp_event_fn dhcp_event;
-#endif
-
-#if LWIP_IPV6_AUTOCONFIG
-  /** is this netif enabled for IPv6 autoconfiguration */
-  u8_t ip6_autoconfig_enabled;
-#endif /* LWIP_IPV6_AUTOCONFIG */
-#if LWIP_IPV6_SEND_ROUTER_SOLICIT
-  /** Number of Router Solicitation messages that remain to be sent. */
-  u8_t rs_count;
-#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */
-#if LWIP_NETIF_HOSTNAME
-  /* the hostname for this netif, NULL is a valid value */
-  const char*  hostname;
-#endif /* LWIP_NETIF_HOSTNAME */
-#if LWIP_CHECKSUM_CTRL_PER_NETIF
-  u16_t chksum_flags;
-#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
-  /** maximum transfer unit (in bytes) */
-  u16_t mtu;
-  /** number of bytes used in hwaddr */
-  u8_t hwaddr_len;
-  /** link level hardware address of this interface */
-  u8_t hwaddr[NETIF_MAX_HWADDR_LEN];
-  /** flags (@see @ref netif_flags) */
-  u8_t flags;
-  /** descriptive abbreviation */
-  char name[2];
-  /** number of this interface */
-  u8_t num;
-#if MIB2_STATS
-  /** link type (from "snmp_ifType" enum from snmp_mib2.h) */
-  u8_t link_type;
-  /** (estimate) link speed */
-  u32_t link_speed;
-  /** timestamp at last change made (up/down) */
-  u32_t ts;
-  /** counters */
-  struct stats_mib2_netif_ctrs mib2_counters;
-#endif /* MIB2_STATS */
-#if LWIP_IPV4 && LWIP_IGMP
-  /** This function could be called to add or delete an entry in the multicast
-      filter table of the ethernet MAC.*/
-  netif_igmp_mac_filter_fn igmp_mac_filter;
-#endif /* LWIP_IPV4 && LWIP_IGMP */
-#if LWIP_IPV6 && LWIP_IPV6_MLD
-  /** This function could be called to add or delete an entry in the IPv6 multicast
-      filter table of the ethernet MAC. */
-  netif_mld_mac_filter_fn mld_mac_filter;
-#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
-#if LWIP_NETIF_HWADDRHINT
-  u8_t *addr_hint;
-#endif /* LWIP_NETIF_HWADDRHINT */
-#if ENABLE_LOOPBACK
-  /* List of packets to be queued for ourselves. */
-  struct pbuf *loop_first;
-  struct pbuf *loop_last;
-#if LWIP_LOOPBACK_MAX_PBUFS
-  u16_t loop_cnt_current;
-#endif /* LWIP_LOOPBACK_MAX_PBUFS */
-#endif /* ENABLE_LOOPBACK */
-
-#if ESP_LWIP
-  void (*l2_buffer_free_notify)(void *user_buf); /* Allows LWIP to notify driver when a L2-supplied pbuf can be freed */
-  ip_addr_t last_ip_addr; /* Store last non-zero ip address */
-#endif
-};
-
-#if LWIP_CHECKSUM_CTRL_PER_NETIF
-#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags) do { \
-  (netif)->chksum_flags = chksumflags; } while(0)
-#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag) if (((netif) == NULL) || (((netif)->chksum_flags & (chksumflag)) != 0))
-#else /* LWIP_CHECKSUM_CTRL_PER_NETIF */
-#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags)
-#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag)
-#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
-
-/** The list of network interfaces. */
-extern struct netif *netif_list;
-/** The default network interface. */
-extern struct netif *netif_default;
-
-void netif_init(void);
-
-struct netif *netif_add(struct netif *netif,
-#if LWIP_IPV4
-                        const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
-#endif /* LWIP_IPV4 */
-                        void *state, netif_init_fn init, netif_input_fn input);
-#if LWIP_IPV4
-void netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
-                    const ip4_addr_t *gw);
-#endif /* LWIP_IPV4 */
-
-#if ESP_GRATUITOUS_ARP
-void netif_set_garp_flag(struct netif *netif);
-#endif
-
-void netif_remove(struct netif * netif);
-
-/* Returns a network interface given its name. The name is of the form
-   "et0", where the first two letters are the "name" field in the
-   netif structure, and the digit is in the num field in the same
-   structure. */
-struct netif *netif_find(const char *name);
-
-void netif_set_default(struct netif *netif);
-
-#if LWIP_IPV4
-void netif_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr);
-void netif_set_netmask(struct netif *netif, const ip4_addr_t *netmask);
-void netif_set_gw(struct netif *netif, const ip4_addr_t *gw);
-/** @ingroup netif_ip4 */
-#define netif_ip4_addr(netif)    ((const ip4_addr_t*)ip_2_ip4(&((netif)->ip_addr)))
-/** @ingroup netif_ip4 */
-#define netif_ip4_netmask(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->netmask)))
-/** @ingroup netif_ip4 */
-#define netif_ip4_gw(netif)      ((const ip4_addr_t*)ip_2_ip4(&((netif)->gw)))
-/** @ingroup netif_ip4 */
-#define netif_ip_addr4(netif)    ((const ip_addr_t*)&((netif)->ip_addr))
-/** @ingroup netif_ip4 */
-#define netif_ip_netmask4(netif) ((const ip_addr_t*)&((netif)->netmask))
-/** @ingroup netif_ip4 */
-#define netif_ip_gw4(netif)      ((const ip_addr_t*)&((netif)->gw))
-#endif /* LWIP_IPV4 */
-
-void netif_set_up(struct netif *netif);
-void netif_set_down(struct netif *netif);
-/** @ingroup netif
- * Ask if an interface is up
- */
-#if ESP_LWIP
-#define netif_is_up(netif) ( ((netif) && ((netif)->flags & NETIF_FLAG_UP)) ? (u8_t)1 : (u8_t)0)
-#else
-#define netif_is_up(netif) (((netif)->flags & NETIF_FLAG_UP) ? (u8_t)1 : (u8_t)0)
-#endif
-
-#if LWIP_NETIF_STATUS_CALLBACK
-void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback);
-#endif /* LWIP_NETIF_STATUS_CALLBACK */
-#if LWIP_NETIF_REMOVE_CALLBACK
-void netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback);
-#endif /* LWIP_NETIF_REMOVE_CALLBACK */
-
-void netif_set_link_up(struct netif *netif);
-void netif_set_link_down(struct netif *netif);
-/** Ask if a link is up */
-#define netif_is_link_up(netif) (((netif)->flags & NETIF_FLAG_LINK_UP) ? (u8_t)1 : (u8_t)0)
-
-#if LWIP_NETIF_LINK_CALLBACK
-void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback);
-#endif /* LWIP_NETIF_LINK_CALLBACK */
-
-#if LWIP_NETIF_HOSTNAME
-/** @ingroup netif */
-#define netif_set_hostname(netif, name) do { if((netif) != NULL) { (netif)->hostname = name; }}while(0)
-/** @ingroup netif */
-#define netif_get_hostname(netif) (((netif) != NULL) ? ((netif)->hostname) : NULL)
-#endif /* LWIP_NETIF_HOSTNAME */
-
-#if LWIP_IGMP
-/** @ingroup netif */
-#define netif_set_igmp_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->igmp_mac_filter = function; }}while(0)
-#define netif_get_igmp_mac_filter(netif) (((netif) != NULL) ? ((netif)->igmp_mac_filter) : NULL)
-#endif /* LWIP_IGMP */
-
-#if LWIP_IPV6 && LWIP_IPV6_MLD
-/** @ingroup netif */
-#define netif_set_mld_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->mld_mac_filter = function; }}while(0)
-#define netif_get_mld_mac_filter(netif) (((netif) != NULL) ? ((netif)->mld_mac_filter) : NULL)
-#define netif_mld_mac_filter(netif, addr, action) do { if((netif) && (netif)->mld_mac_filter) { (netif)->mld_mac_filter((netif), (addr), (action)); }}while(0)
-#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
-
-#if ENABLE_LOOPBACK
-err_t netif_loop_output(struct netif *netif, struct pbuf *p);
-void netif_poll(struct netif *netif);
-#if !LWIP_NETIF_LOOPBACK_MULTITHREADING
-void netif_poll_all(void);
-#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */
-#endif /* ENABLE_LOOPBACK */
-
-err_t netif_input(struct pbuf *p, struct netif *inp);
-
-#if LWIP_IPV6
-/** @ingroup netif_ip6 */
-#define netif_ip_addr6(netif, i)  ((const ip_addr_t*)(&((netif)->ip6_addr[i])))
-/** @ingroup netif_ip6 */
-#define netif_ip6_addr(netif, i)  ((const ip6_addr_t*)ip_2_ip6(&((netif)->ip6_addr[i])))
-void netif_ip6_addr_set(struct netif *netif, s8_t addr_idx, const ip6_addr_t *addr6);
-void netif_ip6_addr_set_parts(struct netif *netif, s8_t addr_idx, u32_t i0, u32_t i1, u32_t i2, u32_t i3);
-#define netif_ip6_addr_state(netif, i)  ((netif)->ip6_addr_state[i])
-void netif_ip6_addr_set_state(struct netif* netif, s8_t addr_idx, u8_t state);
-s8_t netif_get_ip6_addr_match(struct netif *netif, const ip6_addr_t *ip6addr);
-void netif_create_ip6_linklocal_address(struct netif *netif, u8_t from_mac_48bit);
-err_t netif_add_ip6_address(struct netif *netif, const ip6_addr_t *ip6addr, s8_t *chosen_idx);
-#define netif_set_ip6_autoconfig_enabled(netif, action) do { if(netif) { (netif)->ip6_autoconfig_enabled = (action); }}while(0)
-#endif /* LWIP_IPV6 */
-
-#if LWIP_NETIF_HWADDRHINT
-#define NETIF_SET_HWADDRHINT(netif, hint) ((netif)->addr_hint = (hint))
-#else /* LWIP_NETIF_HWADDRHINT */
-#define NETIF_SET_HWADDRHINT(netif, hint)
-#endif /* LWIP_NETIF_HWADDRHINT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_NETIF_H */
diff --git a/tools/sdk/include/lwip/lwip/netifapi.h b/tools/sdk/include/lwip/lwip/netifapi.h
deleted file mode 100644
index 8bd2b4f76f7..00000000000
--- a/tools/sdk/include/lwip/lwip/netifapi.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/**
- * @file
- * netif API (to be used from non-TCPIP threads)
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-#ifndef LWIP_HDR_NETIFAPI_H
-#define LWIP_HDR_NETIFAPI_H
-
-#include "lwip/opt.h"
-
-#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/sys.h"
-#include "lwip/netif.h"
-#include "lwip/dhcp.h"
-#include "lwip/autoip.h"
-#include "lwip/priv/tcpip_priv.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_MPU_COMPATIBLE
-#define NETIFAPI_IPADDR_DEF(type, m)  type m
-#else /* LWIP_MPU_COMPATIBLE */
-#define NETIFAPI_IPADDR_DEF(type, m)  const type * m
-#endif /* LWIP_MPU_COMPATIBLE */
-
-typedef void (*netifapi_void_fn)(struct netif *netif);
-typedef err_t (*netifapi_errt_fn)(struct netif *netif);
-
-struct netifapi_msg {
-  struct tcpip_api_call_data call;
-  struct netif *netif;
-  union {
-    struct {
-#if LWIP_IPV4
-      NETIFAPI_IPADDR_DEF(ip4_addr_t, ipaddr);
-      NETIFAPI_IPADDR_DEF(ip4_addr_t, netmask);
-      NETIFAPI_IPADDR_DEF(ip4_addr_t, gw);
-#endif /* LWIP_IPV4 */
-      void *state;
-      netif_init_fn init;
-      netif_input_fn input;
-    } add;
-    struct {
-      netifapi_void_fn voidfunc;
-      netifapi_errt_fn errtfunc;
-    } common;
-  } msg;
-};
-
-
-/* API for application */
-err_t netifapi_netif_add(struct netif *netif,
-#if LWIP_IPV4
-                         const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
-#endif /* LWIP_IPV4 */
-                         void *state, netif_init_fn init, netif_input_fn input);
-
-#if LWIP_IPV4
-err_t netifapi_netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr,
-                              const ip4_addr_t *netmask, const ip4_addr_t *gw);
-#endif /* LWIP_IPV4*/
-
-err_t netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc,
-                            netifapi_errt_fn errtfunc);
-
-/** @ingroup netifapi_netif */
-#define netifapi_netif_remove(n)        netifapi_netif_common(n, netif_remove, NULL)
-/** @ingroup netifapi_netif */
-#define netifapi_netif_set_up(n)        netifapi_netif_common(n, netif_set_up, NULL)
-/** @ingroup netifapi_netif */
-#define netifapi_netif_set_down(n)      netifapi_netif_common(n, netif_set_down, NULL)
-/** @ingroup netifapi_netif */
-#define netifapi_netif_set_default(n)   netifapi_netif_common(n, netif_set_default, NULL)
-/** @ingroup netifapi_netif */
-#define netifapi_netif_set_link_up(n)   netifapi_netif_common(n, netif_set_link_up, NULL)
-/** @ingroup netifapi_netif */
-#define netifapi_netif_set_link_down(n) netifapi_netif_common(n, netif_set_link_down, NULL)
-
-/**
- * @defgroup netifapi_dhcp4 DHCPv4
- * @ingroup netifapi
- * To be called from non-TCPIP threads
- */
-/** @ingroup netifapi_dhcp4 */
-#define netifapi_dhcp_start(n)        netifapi_netif_common(n, NULL, dhcp_start)
-/** @ingroup netifapi_dhcp4 */
-#define netifapi_dhcp_stop(n)         netifapi_netif_common(n, dhcp_stop, NULL)
-/** @ingroup netifapi_dhcp4 */
-#define netifapi_dhcp_inform(n)       netifapi_netif_common(n, dhcp_inform, NULL)
-/** @ingroup netifapi_dhcp4 */
-#define netifapi_dhcp_renew(n)        netifapi_netif_common(n, NULL, dhcp_renew)
-/** @ingroup netifapi_dhcp4 */
-#define netifapi_dhcp_release(n)      netifapi_netif_common(n, NULL, dhcp_release)
-
-/**
- * @defgroup netifapi_autoip AUTOIP
- * @ingroup netifapi
- * To be called from non-TCPIP threads
- */
-/** @ingroup netifapi_autoip */
-#define netifapi_autoip_start(n)      netifapi_netif_common(n, NULL, autoip_start)
-/** @ingroup netifapi_autoip */
-#define netifapi_autoip_stop(n)       netifapi_netif_common(n, NULL, autoip_stop)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_NETIF_API */
-
-#endif /* LWIP_HDR_NETIFAPI_H */
diff --git a/tools/sdk/include/lwip/lwip/opt.h b/tools/sdk/include/lwip/lwip/opt.h
deleted file mode 100644
index c08dcc0c952..00000000000
--- a/tools/sdk/include/lwip/lwip/opt.h
+++ /dev/null
@@ -1,2906 +0,0 @@
-/**
- * @file
- *
- * lwIP Options Configuration
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-/*
- * NOTE: || defined __DOXYGEN__ is a workaround for doxygen bug -
- * without this, doxygen does not see the actual #define
- */
-
-#if !defined LWIP_HDR_OPT_H
-#define LWIP_HDR_OPT_H
-
-/*
- * Include user defined options first. Anything not defined in these files
- * will be set to standard values. Override anything you don't like!
- */
-#include "lwipopts.h"
-#include "lwip/debug.h"
-
-/**
- * @defgroup lwip_opts Options (lwipopts.h)
- * @ingroup lwip
- *
- * @defgroup lwip_opts_debug Debugging
- * @ingroup lwip_opts
- *
- * @defgroup lwip_opts_infrastructure Infrastructure
- * @ingroup lwip_opts
- *
- * @defgroup lwip_opts_callback Callback-style APIs
- * @ingroup lwip_opts
- *
- * @defgroup lwip_opts_threadsafe_apis Thread-safe APIs
- * @ingroup lwip_opts
- */
-
- /*
-   ------------------------------------
-   -------------- NO SYS --------------
-   ------------------------------------
-*/
-/**
- * @defgroup lwip_opts_nosys NO_SYS
- * @ingroup lwip_opts_infrastructure
- * @{
- */
-/**
- * NO_SYS==1: Use lwIP without OS-awareness (no thread, semaphores, mutexes or
- * mboxes). This means threaded APIs cannot be used (socket, netconn,
- * i.e. everything in the 'api' folder), only the callback-style raw API is
- * available (and you have to watch out for yourself that you don't access
- * lwIP functions/structures from more than one context at a time!)
- */
-#if !defined NO_SYS || defined __DOXYGEN__
-#define NO_SYS                          0
-#endif
-/**
- * @}
- */
-
-/**
- * @defgroup lwip_opts_timers Timers
- * @ingroup lwip_opts_infrastructure
- * @{
- */
-/**
- * LWIP_TIMERS==0: Drop support for sys_timeout and lwip-internal cyclic timers.
- * (the array of lwip-internal cyclic timers is still provided)
- * (check NO_SYS_NO_TIMERS for compatibility to old versions)
- */
-#if !defined LWIP_TIMERS || defined __DOXYGEN__
-#ifdef NO_SYS_NO_TIMERS
-#define LWIP_TIMERS                     (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS))
-#else
-#define LWIP_TIMERS                     1
-#endif
-#endif
-
-/**
- * LWIP_TIMERS_CUSTOM==1: Provide your own timer implementation.
- * Function prototypes in timeouts.h and the array of lwip-internal cyclic timers
- * are still included, but the implementation is not. The following functions
- * will be required: sys_timeouts_init(), sys_timeout(), sys_untimeout(),
- *                   sys_timeouts_mbox_fetch()
- */
-#if !defined LWIP_TIMERS_CUSTOM || defined __DOXYGEN__
-#define LWIP_TIMERS_CUSTOM              0
-#endif
-/**
- * @}
- */
-
-/**
- * @defgroup lwip_opts_memcpy memcpy
- * @ingroup lwip_opts_infrastructure
- * @{
- */
-/**
- * MEMCPY: override this if you have a faster implementation at hand than the
- * one included in your C library
- */
-#if !defined MEMCPY || defined __DOXYGEN__
-#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
-#endif
-
-/**
- * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
- * call to memcpy() if the length is known at compile time and is small.
- */
-#if !defined SMEMCPY || defined __DOXYGEN__
-#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
-#endif
-/**
- * @}
- */
-
-/*
-   ------------------------------------
-   ----------- Core locking -----------
-   ------------------------------------
-*/
-/**
- * @defgroup lwip_opts_lock Core locking and MPU
- * @ingroup lwip_opts_infrastructure
- * @{
- */
-/**
- * LWIP_MPU_COMPATIBLE: enables special memory management mechanism
- * which makes lwip able to work on MPU (Memory Protection Unit) system
- * by not passing stack-pointers to other threads
- * (this decreases performance as memory is allocated from pools instead
- * of keeping it on the stack)
- */
-#if !defined LWIP_MPU_COMPATIBLE || defined __DOXYGEN__
-#define LWIP_MPU_COMPATIBLE             0
-#endif
-
-/**
- * LWIP_TCPIP_CORE_LOCKING
- * Creates a global mutex that is held during TCPIP thread operations.
- * Can be locked by client code to perform lwIP operations without changing
- * into TCPIP thread using callbacks. See LOCK_TCPIP_CORE() and
- * UNLOCK_TCPIP_CORE().
- * Your system should provide mutexes supporting priority inversion to use this.
- */
-#if !defined LWIP_TCPIP_CORE_LOCKING || defined __DOXYGEN__
-#define LWIP_TCPIP_CORE_LOCKING         1
-#endif
-
-/**
- * LWIP_TCPIP_CORE_LOCKING_INPUT: when LWIP_TCPIP_CORE_LOCKING is enabled,
- * this lets tcpip_input() grab the mutex for input packets as well,
- * instead of allocating a message and passing it to tcpip_thread.
- *
- * ATTENTION: this does not work when tcpip_input() is called from
- * interrupt context!
- */
-#if !defined LWIP_TCPIP_CORE_LOCKING_INPUT || defined __DOXYGEN__
-#define LWIP_TCPIP_CORE_LOCKING_INPUT   0
-#endif
-
-/**
- * SYS_LIGHTWEIGHT_PROT==1: enable inter-task protection (and task-vs-interrupt
- * protection) for certain critical regions during buffer allocation, deallocation
- * and memory allocation and deallocation.
- * ATTENTION: This is required when using lwIP from more than one context! If
- * you disable this, you must be sure what you are doing!
- */
-#if !defined SYS_LIGHTWEIGHT_PROT || defined __DOXYGEN__
-#define SYS_LIGHTWEIGHT_PROT            1
-#endif
-/**
- * @}
- */
-
-/*
-   ------------------------------------
-   ---------- Memory options ----------
-   ------------------------------------
-*/
-/**
- * @defgroup lwip_opts_mem Heap and memory pools
- * @ingroup lwip_opts_infrastructure
- * @{
- */
-/**
- * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
- * instead of the lwip internal allocator. Can save code size if you
- * already use it.
- */
-#if !defined MEM_LIBC_MALLOC || defined __DOXYGEN__
-#define MEM_LIBC_MALLOC                 0
-#endif
-
-/**
- * MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
- * Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
- * speed (heap alloc can be much slower than pool alloc) and usage from interrupts
- * (especially if your netif driver allocates PBUF_POOL pbufs for received frames
- * from interrupt)!
- * ATTENTION: Currently, this uses the heap for ALL pools (also for private pools,
- * not only for internal pools defined in memp_std.h)!
- */
-#if !defined MEMP_MEM_MALLOC || defined __DOXYGEN__
-#define MEMP_MEM_MALLOC                 0
-#endif
-
-/**
- * MEM_ALIGNMENT: should be set to the alignment of the CPU
- *    4 byte alignment -> \#define MEM_ALIGNMENT 4
- *    2 byte alignment -> \#define MEM_ALIGNMENT 2
- */
-#if !defined MEM_ALIGNMENT || defined __DOXYGEN__
-#define MEM_ALIGNMENT                   1
-#endif
-
-/**
- * MEM_SIZE: the size of the heap memory. If the application will send
- * a lot of data that needs to be copied, this should be set high.
- */
-#if !defined MEM_SIZE || defined __DOXYGEN__
-#define MEM_SIZE                        1600
-#endif
-
-/**
- * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
- * amount of bytes before and after each memp element in every pool and fills
- * it with a prominent default value.
- *    MEMP_OVERFLOW_CHECK == 0 no checking
- *    MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
- *    MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
- *      memp_malloc() or memp_free() is called (useful but slow!)
- */
-#if !defined MEMP_OVERFLOW_CHECK || defined __DOXYGEN__
-#define MEMP_OVERFLOW_CHECK             0
-#endif
-
-/**
- * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
- * sure that there are no cycles in the linked lists.
- */
-#if !defined MEMP_SANITY_CHECK || defined __DOXYGEN__
-#define MEMP_SANITY_CHECK               0
-#endif
-
-/**
- * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
- * of memory pools of various sizes. When mem_malloc is called, an element of
- * the smallest pool that can provide the length needed is returned.
- * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled.
- */
-#if !defined MEM_USE_POOLS || defined __DOXYGEN__
-#define MEM_USE_POOLS                   0
-#endif
-
-/**
- * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next
- * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more
- * reliable. */
-#if !defined MEM_USE_POOLS_TRY_BIGGER_POOL || defined __DOXYGEN__
-#define MEM_USE_POOLS_TRY_BIGGER_POOL   0
-#endif
-
-/**
- * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
- * that defines additional pools beyond the "standard" ones required
- * by lwIP. If you set this to 1, you must have lwippools.h in your
- * include path somewhere.
- */
-#if !defined MEMP_USE_CUSTOM_POOLS || defined __DOXYGEN__
-#define MEMP_USE_CUSTOM_POOLS           0
-#endif
-
-/**
- * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from
- * interrupt context (or another context that doesn't allow waiting for a
- * semaphore).
- * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT,
- * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs
- * with each loop so that mem_free can run.
- *
- * ATTENTION: As you can see from the above description, this leads to dis-/
- * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc
- * can need longer.
- *
- * If you don't want that, at least for NO_SYS=0, you can still use the following
- * functions to enqueue a deallocation call which then runs in the tcpip_thread
- * context:
- * - pbuf_free_callback(p);
- * - mem_free_callback(m);
- */
-#if !defined LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT || defined __DOXYGEN__
-#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0
-#endif
-/**
- * @}
- */
-
-/*
-   ------------------------------------------------
-   ---------- Internal Memory Pool Sizes ----------
-   ------------------------------------------------
-*/
-/**
- * @defgroup lwip_opts_memp Internal memory pools
- * @ingroup lwip_opts_infrastructure
- * @{
- */
-/**
- * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
- * If the application sends a lot of data out of ROM (or other static memory),
- * this should be set high.
- */
-#if !defined MEMP_NUM_PBUF || defined __DOXYGEN__
-#define MEMP_NUM_PBUF                   16
-#endif
-
-/**
- * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
- * (requires the LWIP_RAW option)
- */
-#if !defined MEMP_NUM_RAW_PCB || defined __DOXYGEN__
-#define MEMP_NUM_RAW_PCB                4
-#endif
-
-/**
- * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
- * per active UDP "connection".
- * (requires the LWIP_UDP option)
- */
-#if !defined MEMP_NUM_UDP_PCB || defined __DOXYGEN__
-#define MEMP_NUM_UDP_PCB                4
-#endif
-
-/**
- * MEMP_NUM_TCP_PCB: the number of simultaneously active TCP connections.
- * (requires the LWIP_TCP option)
- */
-#if !defined MEMP_NUM_TCP_PCB || defined __DOXYGEN__
-#define MEMP_NUM_TCP_PCB                5
-#endif
-
-/**
- * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
- * (requires the LWIP_TCP option)
- */
-#if !defined MEMP_NUM_TCP_PCB_LISTEN || defined __DOXYGEN__
-#define MEMP_NUM_TCP_PCB_LISTEN         8
-#endif
-
-/**
- * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
- * (requires the LWIP_TCP option)
- */
-#if !defined MEMP_NUM_TCP_SEG || defined __DOXYGEN__
-#define MEMP_NUM_TCP_SEG                16
-#endif
-
-/**
- * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for
- * reassembly (whole packets, not fragments!)
- */
-#if !defined MEMP_NUM_REASSDATA || defined __DOXYGEN__
-#define MEMP_NUM_REASSDATA              5
-#endif
-
-/**
- * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent
- * (fragments, not whole packets!).
- * This is only used with LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1
- * with DMA-enabled MACs where the packet is not yet sent when netif->output
- * returns.
- */
-#if !defined MEMP_NUM_FRAG_PBUF || defined __DOXYGEN__
-#define MEMP_NUM_FRAG_PBUF              15
-#endif
-
-/**
- * MEMP_NUM_ARP_QUEUE: the number of simultaneously queued outgoing
- * packets (pbufs) that are waiting for an ARP request (to resolve
- * their destination address) to finish.
- * (requires the ARP_QUEUEING option)
- */
-#if !defined MEMP_NUM_ARP_QUEUE || defined __DOXYGEN__
-#define MEMP_NUM_ARP_QUEUE              30
-#endif
-
-/**
- * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
- * can be members at the same time (one per netif - allsystems group -, plus one
- * per netif membership).
- * (requires the LWIP_IGMP option)
- */
-#if !defined MEMP_NUM_IGMP_GROUP || defined __DOXYGEN__
-#define MEMP_NUM_IGMP_GROUP             8
-#endif
-
-/**
- * MEMP_NUM_SYS_TIMEOUT: the number of simultaneously active timeouts.
- * The default number of timeouts is calculated here for all enabled modules.
- * The formula expects settings to be either '0' or '1'.
- */
-#if !defined MEMP_NUM_SYS_TIMEOUT || defined __DOXYGEN__
-#if ESP_LWIP
-#define MEMP_NUM_SYS_TIMEOUT            (LWIP_TCP + IP_REASSEMBLY + (LWIP_ARP + (ESP_GRATUITOUS_ARP ? 1 : 0)) + (2*LWIP_DHCP + (ESP_DHCPS_TIMER ? 1 : 0)) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + (PPP_SUPPORT*6*MEMP_NUM_PPP_PCB) + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0))
-#else
-#define MEMP_NUM_SYS_TIMEOUT            (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + (PPP_SUPPORT*6*MEMP_NUM_PPP_PCB) + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0))
-#endif
-#endif
-
-/**
- * MEMP_NUM_NETBUF: the number of struct netbufs.
- * (only needed if you use the sequential API, like api_lib.c)
- */
-#if !defined MEMP_NUM_NETBUF || defined __DOXYGEN__
-#define MEMP_NUM_NETBUF                 2
-#endif
-
-/**
- * MEMP_NUM_NETCONN: the number of struct netconns.
- * (only needed if you use the sequential API, like api_lib.c)
- */
-#if !defined MEMP_NUM_NETCONN || defined __DOXYGEN__
-#define MEMP_NUM_NETCONN                4
-#endif
-
-/**
- * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
- * for callback/timeout API communication.
- * (only needed if you use tcpip.c)
- */
-#if !defined MEMP_NUM_TCPIP_MSG_API || defined __DOXYGEN__
-#define MEMP_NUM_TCPIP_MSG_API          8
-#endif
-
-/**
- * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
- * for incoming packets.
- * (only needed if you use tcpip.c)
- */
-#if !defined MEMP_NUM_TCPIP_MSG_INPKT || defined __DOXYGEN__
-#define MEMP_NUM_TCPIP_MSG_INPKT        8
-#endif
-
-/**
- * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls
- * (before freeing the corresponding memory using lwip_freeaddrinfo()).
- */
-#if !defined MEMP_NUM_NETDB || defined __DOXYGEN__
-#define MEMP_NUM_NETDB                  1
-#endif
-
-/**
- * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list
- * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1.
- */
-#if !defined MEMP_NUM_LOCALHOSTLIST || defined __DOXYGEN__
-#define MEMP_NUM_LOCALHOSTLIST          1
-#endif
-
-/**
- * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
- */
-#if !defined PBUF_POOL_SIZE || defined __DOXYGEN__
-#define PBUF_POOL_SIZE                  16
-#endif
-
-/** MEMP_NUM_API_MSG: the number of concurrently active calls to various
- * socket, netconn, and tcpip functions
- */
-#if !defined MEMP_NUM_API_MSG || defined __DOXYGEN__
-#define MEMP_NUM_API_MSG                MEMP_NUM_TCPIP_MSG_API
-#endif
-
-/** MEMP_NUM_DNS_API_MSG: the number of concurrently active calls to netconn_gethostbyname
- */
-#if !defined MEMP_NUM_DNS_API_MSG || defined __DOXYGEN__
-#define MEMP_NUM_DNS_API_MSG            MEMP_NUM_TCPIP_MSG_API
-#endif
-
-/** MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA: the number of concurrently active calls
- * to getsockopt/setsockopt
- */
-#if !defined MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA || defined __DOXYGEN__
-#define MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA MEMP_NUM_TCPIP_MSG_API
-#endif
-
-/** MEMP_NUM_NETIFAPI_MSG: the number of concurrently active calls to the
- * netifapi functions
- */
-#if !defined MEMP_NUM_NETIFAPI_MSG || defined __DOXYGEN__
-#define MEMP_NUM_NETIFAPI_MSG           MEMP_NUM_TCPIP_MSG_API
-#endif
-/**
- * @}
- */
-
-/*
-   ---------------------------------
-   ---------- ARP options ----------
-   ---------------------------------
-*/
-/**
- * @defgroup lwip_opts_arp ARP
- * @ingroup lwip_opts_ipv4
- * @{
- */
-/**
- * LWIP_ARP==1: Enable ARP functionality.
- */
-#if !defined LWIP_ARP || defined __DOXYGEN__
-#define LWIP_ARP                        1
-#endif
-
-/**
- * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
- */
-#if !defined ARP_TABLE_SIZE || defined __DOXYGEN__
-#define ARP_TABLE_SIZE                  10
-#endif
-
-/** the time an ARP entry stays valid after its last update,
- *  for ARP_TMR_INTERVAL = 1000, this is
- *  (60 * 5) seconds = 5 minutes.
- */
-#if !defined ARP_MAXAGE || defined __DOXYGEN__
-#define ARP_MAXAGE                      300
-#endif
-
-/**
- * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
- * resolution. By default, only the most recent packet is queued per IP address.
- * This is sufficient for most protocols and mainly reduces TCP connection
- * startup time. Set this to 1 if you know your application sends more than one
- * packet in a row to an IP address that is not in the ARP cache.
- */
-#if !defined ARP_QUEUEING || defined __DOXYGEN__
-#define ARP_QUEUEING                    0
-#endif
-
-/** The maximum number of packets which may be queued for each
- *  unresolved address by other network layers. Defaults to 3, 0 means disabled.
- *  Old packets are dropped, new packets are queued.
- */
-#if !defined ARP_QUEUE_LEN || defined __DOXYGEN__
-#define ARP_QUEUE_LEN                   3
-#endif
-
-/**
- * ETHARP_SUPPORT_VLAN==1: support receiving and sending ethernet packets with
- * VLAN header. See the description of LWIP_HOOK_VLAN_CHECK and
- * LWIP_HOOK_VLAN_SET hooks to check/set VLAN headers.
- * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check.
- * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted.
- * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted.
- * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan)
- * that returns 1 to accept a packet or 0 to drop a packet.
- */
-#if !defined ETHARP_SUPPORT_VLAN || defined __DOXYGEN__
-#define ETHARP_SUPPORT_VLAN             0
-#endif
-
-/** LWIP_ETHERNET==1: enable ethernet support even though ARP might be disabled
- */
-#if !defined LWIP_ETHERNET || defined __DOXYGEN__
-#define LWIP_ETHERNET                   LWIP_ARP
-#endif
-
-/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure
- * alignment of payload after that header. Since the header is 14 bytes long,
- * without this padding e.g. addresses in the IP header will not be aligned
- * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms.
- */
-#if !defined ETH_PAD_SIZE || defined __DOXYGEN__
-#define ETH_PAD_SIZE                    0
-#endif
-
-/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table
- * entries (using etharp_add_static_entry/etharp_remove_static_entry).
- */
-#if !defined ETHARP_SUPPORT_STATIC_ENTRIES || defined __DOXYGEN__
-#define ETHARP_SUPPORT_STATIC_ENTRIES   0
-#endif
-
-/** ETHARP_TABLE_MATCH_NETIF==1: Match netif for ARP table entries.
- * If disabled, duplicate IP address on multiple netifs are not supported
- * (but this should only occur for AutoIP).
- */
-#if !defined ETHARP_TABLE_MATCH_NETIF || defined __DOXYGEN__
-#define ETHARP_TABLE_MATCH_NETIF        0
-#endif
-/**
- * @}
- */
-
-/*
-   --------------------------------
-   ---------- IP options ----------
-   --------------------------------
-*/
-/**
- * @defgroup lwip_opts_ipv4 IPv4
- * @ingroup lwip_opts
- * @{
- */
-/**
- * LWIP_IPV4==1: Enable IPv4
- */
-#if !defined LWIP_IPV4 || defined __DOXYGEN__
-#define LWIP_IPV4                       1
-#endif
-
-/**
- * IP_FORWARD==1: Enables the ability to forward IP packets across network
- * interfaces. If you are going to run lwIP on a device with only one network
- * interface, define this to 0.
- */
-#if !defined IP_FORWARD || defined __DOXYGEN__
-#define IP_FORWARD                      0
-#endif
-
-/**
- * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
- * this option does not affect outgoing packet sizes, which can be controlled
- * via IP_FRAG.
- */
-#if !defined IP_REASSEMBLY || defined __DOXYGEN__
-#define IP_REASSEMBLY                   1
-#endif
-
-/**
- * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
- * that this option does not affect incoming packet sizes, which can be
- * controlled via IP_REASSEMBLY.
- */
-#if !defined IP_FRAG || defined __DOXYGEN__
-#define IP_FRAG                         1
-#endif
-
-#if !LWIP_IPV4
-/* disable IPv4 extensions when IPv4 is disabled */
-#undef IP_FORWARD
-#define IP_FORWARD                      0
-#undef IP_REASSEMBLY
-#define IP_REASSEMBLY                   0
-#undef IP_FRAG
-#define IP_FRAG                         0
-#endif /* !LWIP_IPV4 */
-
-/**
- * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
- *      IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
- *      IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
- */
-#if !defined IP_OPTIONS_ALLOWED || defined __DOXYGEN__
-#define IP_OPTIONS_ALLOWED              1
-#endif
-
-/**
- * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
- * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
- * in this time, the whole packet is discarded.
- */
-#if !defined IP_REASS_MAXAGE || defined __DOXYGEN__
-#define IP_REASS_MAXAGE                 3
-#endif
-
-/**
- * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
- * Since the received pbufs are enqueued, be sure to configure
- * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
- * packets even if the maximum amount of fragments is enqueued for reassembly!
- */
-#if !defined IP_REASS_MAX_PBUFS || defined __DOXYGEN__
-#define IP_REASS_MAX_PBUFS              10
-#endif
-
-/**
- * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
- */
-#if !defined IP_DEFAULT_TTL || defined __DOXYGEN__
-#define IP_DEFAULT_TTL                  255
-#endif
-
-/**
- * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast
- * filter per pcb on udp and raw send operations. To enable broadcast filter
- * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1.
- */
-#if !defined IP_SOF_BROADCAST || defined __DOXYGEN__
-#define IP_SOF_BROADCAST                0
-#endif
-
-/**
- * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast
- * filter on recv operations.
- */
-#if !defined IP_SOF_BROADCAST_RECV || defined __DOXYGEN__
-#define IP_SOF_BROADCAST_RECV           0
-#endif
-
-/**
- * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back
- * out on the netif where it was received. This should only be used for
- * wireless networks.
- * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming
- * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags!
- */
-#if !defined IP_FORWARD_ALLOW_TX_ON_RX_NETIF || defined __DOXYGEN__
-#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0
-#endif
-
-/**
- * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first
- * local TCP/UDP pcb (default==0). This can prevent creating predictable port
- * numbers after booting a device.
- */
-#if !defined LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS || defined __DOXYGEN__
-#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 0
-#endif
-/**
- * @}
- */
-
-/*
-   ----------------------------------
-   ---------- ICMP options ----------
-   ----------------------------------
-*/
-/**
- * @defgroup lwip_opts_icmp ICMP
- * @ingroup lwip_opts_ipv4
- * @{
- */
-/**
- * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
- * Be careful, disable that make your product non-compliant to RFC1122
- */
-#if !defined LWIP_ICMP || defined __DOXYGEN__
-#define LWIP_ICMP                       1
-#endif
-
-/**
- * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
- */
-#if !defined ICMP_TTL || defined __DOXYGEN__
-#define ICMP_TTL                       (IP_DEFAULT_TTL)
-#endif
-
-/**
- * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
- */
-#if !defined LWIP_BROADCAST_PING || defined __DOXYGEN__
-#define LWIP_BROADCAST_PING             0
-#endif
-
-/**
- * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only)
- */
-#if !defined LWIP_MULTICAST_PING || defined __DOXYGEN__
-#define LWIP_MULTICAST_PING             0
-#endif
-/**
- * @}
- */
-
-/*
-   ---------------------------------
-   ---------- RAW options ----------
-   ---------------------------------
-*/
-/**
- * @defgroup lwip_opts_raw RAW
- * @ingroup lwip_opts_callback
- * @{
- */
-/**
- * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
- */
-#if !defined LWIP_RAW || defined __DOXYGEN__
-#define LWIP_RAW                        0
-#endif
-
-/**
- * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
- */
-#if !defined RAW_TTL || defined __DOXYGEN__
-#define RAW_TTL                        (IP_DEFAULT_TTL)
-#endif
-/**
- * @}
- */
-
-/*
-   ----------------------------------
-   ---------- DHCP options ----------
-   ----------------------------------
-*/
-/**
- * @defgroup lwip_opts_dhcp DHCP
- * @ingroup lwip_opts_ipv4
- * @{
- */
-/**
- * LWIP_DHCP==1: Enable DHCP module.
- */
-#if !defined LWIP_DHCP || defined __DOXYGEN__
-#define LWIP_DHCP                       0
-#endif
-#if !LWIP_IPV4
-/* disable DHCP when IPv4 is disabled */
-#undef LWIP_DHCP
-#define LWIP_DHCP                       0
-#endif /* !LWIP_IPV4 */
-
-/**
- * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
- */
-#if !defined DHCP_DOES_ARP_CHECK || defined __DOXYGEN__
-#define DHCP_DOES_ARP_CHECK             ((LWIP_DHCP) && (LWIP_ARP))
-#endif
-
-/**
- * LWIP_DHCP_CHECK_LINK_UP==1: dhcp_start() only really starts if the netif has
- * NETIF_FLAG_LINK_UP set in its flags. As this is only an optimization and
- * netif drivers might not set this flag, the default is off. If enabled,
- * netif_set_link_up() must be called to continue dhcp starting.
- */
-#if !defined LWIP_DHCP_CHECK_LINK_UP
-#define LWIP_DHCP_CHECK_LINK_UP         0
-#endif
-
-/**
- * LWIP_DHCP_BOOTP_FILE==1: Store offered_si_addr and boot_file_name.
- */
-#if !defined LWIP_DHCP_BOOTP_FILE || defined __DOXYGEN__
-#define LWIP_DHCP_BOOTP_FILE            0
-#endif
-
-/**
- * LWIP_DHCP_GETS_NTP==1: Request NTP servers with discover/select. For each
- * response packet, an callback is called, which has to be provided by the port:
- * void dhcp_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs);
-*/
-#if !defined LWIP_DHCP_GET_NTP_SRV || defined __DOXYGEN__
-#define LWIP_DHCP_GET_NTP_SRV           0
-#endif
-
-/**
- * The maximum of NTP servers requested
- */
-#if !defined LWIP_DHCP_MAX_NTP_SERVERS || defined __DOXYGEN__
-#define LWIP_DHCP_MAX_NTP_SERVERS       1
-#endif
-
-/**
- * LWIP_DHCP_MAX_DNS_SERVERS > 0: Request DNS servers with discover/select.
- * DHCP servers received in the response are passed to DNS via @ref dns_setserver()
- * (up to the maximum limit defined here).
- */
-#if !defined LWIP_DHCP_MAX_DNS_SERVERS || defined __DOXYGEN__
-#define LWIP_DHCP_MAX_DNS_SERVERS       DNS_MAX_SERVERS
-#endif
-/**
- * @}
- */
-
-#ifndef LWIP_DHCP_IP_ADDR_RESTORE
-#define LWIP_DHCP_IP_ADDR_RESTORE()       0
-#endif
-
-#ifndef LWIP_DHCP_IP_ADDR_STORE
-#define LWIP_DHCP_IP_ADDR_STORE()
-#endif
-
-#ifndef LWIP_DHCP_IP_ADDR_ERASE
-#define LWIP_DHCP_IP_ADDR_ERASE()
-#endif
-
-/*
-   ------------------------------------
-   ---------- AUTOIP options ----------
-   ------------------------------------
-*/
-/**
- * @defgroup lwip_opts_autoip AUTOIP
- * @ingroup lwip_opts_ipv4
- * @{
- */
-/**
- * LWIP_AUTOIP==1: Enable AUTOIP module.
- */
-#if !defined LWIP_AUTOIP || defined __DOXYGEN__
-#define LWIP_AUTOIP                     0
-#endif
-#if !LWIP_IPV4
-/* disable AUTOIP when IPv4 is disabled */
-#undef LWIP_AUTOIP
-#define LWIP_AUTOIP                     0
-#endif /* !LWIP_IPV4 */
-
-/**
- * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
- * the same interface at the same time.
- */
-#if !defined LWIP_DHCP_AUTOIP_COOP || defined __DOXYGEN__
-#define LWIP_DHCP_AUTOIP_COOP           0
-#endif
-
-/**
- * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
- * that should be sent before falling back on AUTOIP (the DHCP client keeps
- * running in this case). This can be set as low as 1 to get an AutoIP address
- * very  quickly, but you should be prepared to handle a changing IP address
- * when DHCP overrides AutoIP.
- */
-#if !defined LWIP_DHCP_AUTOIP_COOP_TRIES || defined __DOXYGEN__
-#define LWIP_DHCP_AUTOIP_COOP_TRIES     9
-#endif
-/**
- * @}
- */
-
-/*
-   ----------------------------------
-   ----- SNMP MIB2 support      -----
-   ----------------------------------
-*/
-/**
- * @defgroup lwip_opts_mib2 SNMP MIB2 callbacks
- * @ingroup lwip_opts_infrastructure
- * @{
- */
-/**
- * LWIP_MIB2_CALLBACKS==1: Turn on SNMP MIB2 callbacks.
- * Turn this on to get callbacks needed to implement MIB2.
- * Usually MIB2_STATS should be enabled, too.
- */
-#if !defined LWIP_MIB2_CALLBACKS || defined __DOXYGEN__
-#define LWIP_MIB2_CALLBACKS             0
-#endif
-/**
- * @}
- */
-
-/*
-   ----------------------------------
-   ----- Multicast/IGMP options -----
-   ----------------------------------
-*/
-/**
- * @defgroup lwip_opts_igmp IGMP
- * @ingroup lwip_opts_ipv4
- * @{
- */
-/**
- * LWIP_IGMP==1: Turn on IGMP module.
- */
-#if !defined LWIP_IGMP || defined __DOXYGEN__
-#define LWIP_IGMP                       0
-#endif
-#if !LWIP_IPV4
-#undef LWIP_IGMP
-#define LWIP_IGMP                       0
-#endif
-
-/**
- * LWIP_MULTICAST_TX_OPTIONS==1: Enable multicast TX support like the socket options
- * IP_MULTICAST_TTL/IP_MULTICAST_IF/IP_MULTICAST_LOOP
- */
-#if !defined LWIP_MULTICAST_TX_OPTIONS || defined __DOXYGEN__
-#define LWIP_MULTICAST_TX_OPTIONS       (LWIP_IGMP && LWIP_UDP)
-#endif
-/**
- * @}
- */
-
-/*
-   ----------------------------------
-   ---------- DNS options -----------
-   ----------------------------------
-*/
-/**
- * @defgroup lwip_opts_dns DNS
- * @ingroup lwip_opts_callback
- * @{
- */
-/**
- * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
- * transport.
- */
-#if !defined LWIP_DNS || defined __DOXYGEN__
-#define LWIP_DNS                        0
-#endif
-
-/** DNS maximum number of entries to maintain locally. */
-#if !defined DNS_TABLE_SIZE || defined __DOXYGEN__
-#define DNS_TABLE_SIZE                  4
-#endif
-
-/** DNS maximum host name length supported in the name table. */
-#if !defined DNS_MAX_NAME_LENGTH || defined __DOXYGEN__
-#define DNS_MAX_NAME_LENGTH             256
-#endif
-
-/** The maximum of DNS servers
- * The first server can be initialized automatically by defining
- * DNS_SERVER_ADDRESS(ipaddr), where 'ipaddr' is an 'ip_addr_t*'
- */
-#if !defined DNS_MAX_SERVERS || defined __DOXYGEN__
-#define DNS_MAX_SERVERS                 2
-#endif
-
-/** DNS do a name checking between the query and the response. */
-#if !defined DNS_DOES_NAME_CHECK || defined __DOXYGEN__
-#define DNS_DOES_NAME_CHECK             1
-#endif
-
-/** LWIP_DNS_SECURE: controls the security level of the DNS implementation
- * Use all DNS security features by default.
- * This is overridable but should only be needed by very small targets
- * or when using against non standard DNS servers. */
-#if !defined LWIP_DNS_SECURE || defined __DOXYGEN__
-#define LWIP_DNS_SECURE (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT)
-#endif
-
-/* A list of DNS security features follows */
-#define LWIP_DNS_SECURE_RAND_XID                1
-#define LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING 2
-#define LWIP_DNS_SECURE_RAND_SRC_PORT           4
-
-/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, you have to define an initializer:
- *  \#define DNS_LOCAL_HOSTLIST_INIT {DNS_LOCAL_HOSTLIST_ELEM("host_ip4", IPADDR4_INIT_BYTES(1,2,3,4)), \
- *                                    DNS_LOCAL_HOSTLIST_ELEM("host_ip6", IPADDR6_INIT_HOST(123, 234, 345, 456)}
- *
- *  Instead, you can also use an external function:
- *  \#define DNS_LOOKUP_LOCAL_EXTERN(x) extern err_t my_lookup_function(const char *name, ip_addr_t *addr, u8_t dns_addrtype)
- *  that looks up the IP address and returns ERR_OK if found (LWIP_DNS_ADDRTYPE_xxx is passed in dns_addrtype).
- */
-#if !defined DNS_LOCAL_HOSTLIST || defined __DOXYGEN__
-#define DNS_LOCAL_HOSTLIST              0
-#endif /* DNS_LOCAL_HOSTLIST */
-
-/** If this is turned on, the local host-list can be dynamically changed
- *  at runtime. */
-#if !defined DNS_LOCAL_HOSTLIST_IS_DYNAMIC || defined __DOXYGEN__
-#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC   0
-#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
-
-/** Set this to 1 to enable querying ".local" names via mDNS
- *  using a One-Shot Multicast DNS Query */
-#if !defined LWIP_DNS_SUPPORT_MDNS_QUERIES || defined __DOXYGEN__
-#define LWIP_DNS_SUPPORT_MDNS_QUERIES  0
-#endif
-/**
- * @}
- */
-
-/*
-   ---------------------------------
-   ---------- UDP options ----------
-   ---------------------------------
-*/
-/**
- * @defgroup lwip_opts_udp UDP
- * @ingroup lwip_opts_callback
- * @{
- */
-/**
- * LWIP_UDP==1: Turn on UDP.
- */
-#if !defined LWIP_UDP || defined __DOXYGEN__
-#define LWIP_UDP                        1
-#endif
-
-/**
- * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
- */
-#if !defined LWIP_UDPLITE || defined __DOXYGEN__
-#define LWIP_UDPLITE                    0
-#endif
-
-/**
- * UDP_TTL: Default Time-To-Live value.
- */
-#if !defined UDP_TTL || defined __DOXYGEN__
-#define UDP_TTL                         (IP_DEFAULT_TTL)
-#endif
-
-/**
- * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf.
- */
-#if !defined LWIP_NETBUF_RECVINFO || defined __DOXYGEN__
-#define LWIP_NETBUF_RECVINFO            0
-#endif
-/**
- * @}
- */
-
-/*
-   ---------------------------------
-   ---------- TCP options ----------
-   ---------------------------------
-*/
-/**
- * @defgroup lwip_opts_tcp TCP
- * @ingroup lwip_opts_callback
- * @{
- */
-/**
- * LWIP_TCP==1: Turn on TCP.
- */
-#if !defined LWIP_TCP || defined __DOXYGEN__
-#define LWIP_TCP                        1
-#endif
-
-/**
- * TCP_TTL: Default Time-To-Live value.
- */
-#if !defined TCP_TTL || defined __DOXYGEN__
-#define TCP_TTL                         (IP_DEFAULT_TTL)
-#endif
-
-/**
- * TCP_WND: The size of a TCP window.  This must be at least
- * (2 * TCP_MSS) for things to work well.
- * ATTENTION: when using TCP_RCV_SCALE, TCP_WND is the total size
- * with scaling applied. Maximum window value in the TCP header
- * will be TCP_WND >> TCP_RCV_SCALE
- */
-#if !defined TCP_WND || defined __DOXYGEN__
-#define TCP_WND                         (4 * TCP_MSS)
-#endif
-
-/**
- * TCP_MAXRTX: Maximum number of retransmissions of data segments.
- */
-#if !defined TCP_MAXRTX || defined __DOXYGEN__
-#define TCP_MAXRTX                      12
-#endif
-
-/**
- * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
- */
-#if !defined TCP_SYNMAXRTX || defined __DOXYGEN__
-#define TCP_SYNMAXRTX                   6
-#endif
-
-/**
- * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
- * Define to 0 if your device is low on memory.
- */
-#if !defined TCP_QUEUE_OOSEQ || defined __DOXYGEN__
-#define TCP_QUEUE_OOSEQ                 (LWIP_TCP)
-#endif
-
-/**
- * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default,
- * you might want to increase this.)
- * For the receive side, this MSS is advertised to the remote side
- * when opening a connection. For the transmit size, this MSS sets
- * an upper limit on the MSS advertised by the remote host.
- */
-#if !defined TCP_MSS || defined __DOXYGEN__
-#define TCP_MSS                         536
-#endif
-
-/**
- * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
- * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
- * reflects the available reassembly buffer size at the remote host) and the
- * largest size permitted by the IP layer" (RFC 1122)
- * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
- * netif used for a connection and limits the MSS if it would be too big otherwise.
- */
-#if !defined TCP_CALCULATE_EFF_SEND_MSS || defined __DOXYGEN__
-#define TCP_CALCULATE_EFF_SEND_MSS      1
-#endif
-
-
-/**
- * TCP_SND_BUF: TCP sender buffer space (bytes).
- * To achieve good performance, this should be at least 2 * TCP_MSS.
- */
-#if !defined TCP_SND_BUF || defined __DOXYGEN__
-#define TCP_SND_BUF                     (2 * TCP_MSS)
-#endif
-
-/**
- * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
- * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
- */
-#if !defined TCP_SND_QUEUELEN || defined __DOXYGEN__
-#define TCP_SND_QUEUELEN                ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS))
-#endif
-
-/**
- * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than
- * TCP_SND_BUF. It is the amount of space which must be available in the
- * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT).
- */
-#if !defined TCP_SNDLOWAT || defined __DOXYGEN__
-#define TCP_SNDLOWAT                    LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1)
-#endif
-
-/**
- * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less
- * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below
- * this number, select returns writable (combined with TCP_SNDLOWAT).
- */
-#if !defined TCP_SNDQUEUELOWAT || defined __DOXYGEN__
-#define TCP_SNDQUEUELOWAT               LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5)
-#endif
-
-/**
- * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb.
- * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==1.
- */
-#if !defined TCP_OOSEQ_MAX_BYTES || defined __DOXYGEN__
-#define TCP_OOSEQ_MAX_BYTES             0
-#endif
-
-/**
- * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb.
- * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==1.
- */
-#if !defined TCP_OOSEQ_MAX_PBUFS || defined __DOXYGEN__
-#define TCP_OOSEQ_MAX_PBUFS             0
-#endif
-
-/**
- * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
- */
-#if !defined TCP_LISTEN_BACKLOG || defined __DOXYGEN__
-#define TCP_LISTEN_BACKLOG              0
-#endif
-
-/**
- * The maximum allowed backlog for TCP listen netconns.
- * This backlog is used unless another is explicitly specified.
- * 0xff is the maximum (u8_t).
- */
-#if !defined TCP_DEFAULT_LISTEN_BACKLOG || defined __DOXYGEN__
-#define TCP_DEFAULT_LISTEN_BACKLOG      0xff
-#endif
-
-/**
- * TCP_OVERSIZE: The maximum number of bytes that tcp_write may
- * allocate ahead of time in an attempt to create shorter pbuf chains
- * for transmission. The meaningful range is 0 to TCP_MSS. Some
- * suggested values are:
- *
- * 0:         Disable oversized allocation. Each tcp_write() allocates a new
-              pbuf (old behaviour).
- * 1:         Allocate size-aligned pbufs with minimal excess. Use this if your
- *            scatter-gather DMA requires aligned fragments.
- * 128:       Limit the pbuf/memory overhead to 20%.
- * TCP_MSS:   Try to create unfragmented TCP packets.
- * TCP_MSS/4: Try to create 4 fragments or less per TCP packet.
- */
-#if !defined TCP_OVERSIZE || defined __DOXYGEN__
-#define TCP_OVERSIZE                    TCP_MSS
-#endif
-
-/**
- * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option.
- * The timestamp option is currently only used to help remote hosts, it is not
- * really used locally. Therefore, it is only enabled when a TS option is
- * received in the initial SYN packet from a remote host.
- */
-#if !defined LWIP_TCP_TIMESTAMPS || defined __DOXYGEN__
-#define LWIP_TCP_TIMESTAMPS             0
-#endif
-
-/**
- * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an
- * explicit window update
- */
-#if !defined TCP_WND_UPDATE_THRESHOLD || defined __DOXYGEN__
-#define TCP_WND_UPDATE_THRESHOLD   LWIP_MIN((TCP_WND / 4), (TCP_MSS * 4))
-#endif
-
-/**
- * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
- *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
- *         events (accept, sent, etc) that happen in the system.
- *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
- *         for the event. This is the default.
- */
-#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) || defined __DOXYGEN__
-#define LWIP_EVENT_API                  0
-#define LWIP_CALLBACK_API               1
-#else
-#ifndef LWIP_EVENT_API
-#define LWIP_EVENT_API                  0
-#endif
-#ifndef LWIP_CALLBACK_API
-#define LWIP_CALLBACK_API               0
-#endif
-#endif
-
-/**
- * LWIP_WND_SCALE and TCP_RCV_SCALE:
- * Set LWIP_WND_SCALE to 1 to enable window scaling.
- * Set TCP_RCV_SCALE to the desired scaling factor (shift count in the
- * range of [0..14]).
- * When LWIP_WND_SCALE is enabled but TCP_RCV_SCALE is 0, we can use a large
- * send window while having a small receive window only.
- */
-#if !defined LWIP_WND_SCALE || defined __DOXYGEN__
-#define LWIP_WND_SCALE                  0
-#define TCP_RCV_SCALE                   0
-#endif
-
-#if ESP_LWIP
-#if !defined LWIP_TCP_RTO_TIME || defined __DOXYGEN__
-#define LWIP_TCP_RTO_TIME             3000
-#endif
-#endif
-/**
- * @}
- */
-
-/*
-   ----------------------------------
-   ---------- Pbuf options ----------
-   ----------------------------------
-*/
-/**
- * @defgroup lwip_opts_pbuf PBUF
- * @ingroup lwip_opts
- * @{
- */
-/**
- * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
- * link level header. The default is 14, the standard value for
- * Ethernet.
- */
-#if !defined PBUF_LINK_HLEN || defined __DOXYGEN__
-#if defined LWIP_HOOK_VLAN_SET && !defined __DOXYGEN__
-#define PBUF_LINK_HLEN                  (18 + ETH_PAD_SIZE)
-#else /* LWIP_HOOK_VLAN_SET */
-#define PBUF_LINK_HLEN                  (14 + ETH_PAD_SIZE)
-#endif /* LWIP_HOOK_VLAN_SET */
-#endif
-
-/**
- * PBUF_LINK_ENCAPSULATION_HLEN: the number of bytes that should be allocated
- * for an additional encapsulation header before ethernet headers (e.g. 802.11)
- */
-#if !defined PBUF_LINK_ENCAPSULATION_HLEN || defined __DOXYGEN__
-#define PBUF_LINK_ENCAPSULATION_HLEN    0u
-#endif
-
-/**
- * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
- * designed to accommodate single full size TCP frame in one pbuf, including
- * TCP_MSS, IP header, and link header.
- */
-#if !defined PBUF_POOL_BUFSIZE || defined __DOXYGEN__
-#define PBUF_POOL_BUFSIZE               LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN)
-#endif
-/**
- * @}
- */
-
-/*
-   ------------------------------------------------
-   ---------- Network Interfaces options ----------
-   ------------------------------------------------
-*/
-/**
- * @defgroup lwip_opts_netif NETIF
- * @ingroup lwip_opts
- * @{
- */
-/**
- * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
- * field.
- */
-#if !defined LWIP_NETIF_HOSTNAME || defined __DOXYGEN__
-#define LWIP_NETIF_HOSTNAME             0
-#endif
-
-/**
- * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
- */
-#if !defined LWIP_NETIF_API || defined __DOXYGEN__
-#define LWIP_NETIF_API                  0
-#endif
-
-/**
- * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
- * changes its up/down status (i.e., due to DHCP IP acquisition)
- */
-#if !defined LWIP_NETIF_STATUS_CALLBACK || defined __DOXYGEN__
-#define LWIP_NETIF_STATUS_CALLBACK      0
-#endif
-
-/**
- * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
- * whenever the link changes (i.e., link down)
- */
-#if !defined LWIP_NETIF_LINK_CALLBACK || defined __DOXYGEN__
-#define LWIP_NETIF_LINK_CALLBACK        0
-#endif
-
-/**
- * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called
- * when a netif has been removed
- */
-#if !defined LWIP_NETIF_REMOVE_CALLBACK || defined __DOXYGEN__
-#define LWIP_NETIF_REMOVE_CALLBACK      0
-#endif
-
-/**
- * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
- * indices) in struct netif. TCP and UDP can make use of this to prevent
- * scanning the ARP table for every sent packet. While this is faster for big
- * ARP tables or many concurrent connections, it might be counterproductive
- * if you have a tiny ARP table or if there never are concurrent connections.
- */
-#if !defined LWIP_NETIF_HWADDRHINT || defined __DOXYGEN__
-#define LWIP_NETIF_HWADDRHINT           0
-#endif
-
-/**
- * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
- * to be sent into one single pbuf. This is for compatibility with DMA-enabled
- * MACs that do not support scatter-gather.
- * Beware that this might involve CPU-memcpy before transmitting that would not
- * be needed without this flag! Use this only if you need to!
- *
- * @todo: TCP and IP-frag do not work with this, yet:
- */
-#if !defined LWIP_NETIF_TX_SINGLE_PBUF || defined __DOXYGEN__
-#define LWIP_NETIF_TX_SINGLE_PBUF             0
-#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
-
-/**
- * LWIP_NUM_NETIF_CLIENT_DATA: Number of clients that may store
- * data in client_data member array of struct netif.
- */
-#if !defined LWIP_NUM_NETIF_CLIENT_DATA || defined __DOXYGEN__
-#define LWIP_NUM_NETIF_CLIENT_DATA            0
-#endif
-/**
- * @}
- */
-
-/*
-   ------------------------------------
-   ---------- LOOPIF options ----------
-   ------------------------------------
-*/
-/**
- * @defgroup lwip_opts_loop Loopback interface
- * @ingroup lwip_opts_netif
- * @{
- */
-/**
- * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1).
- * This is only needed when no real netifs are available. If at least one other
- * netif is available, loopback traffic uses this netif.
- */
-#if !defined LWIP_HAVE_LOOPIF || defined __DOXYGEN__
-#define LWIP_HAVE_LOOPIF                LWIP_NETIF_LOOPBACK
-#endif
-
-/**
- * LWIP_LOOPIF_MULTICAST==1: Support multicast/IGMP on loop interface (127.0.0.1).
- */
-#if !defined LWIP_LOOPIF_MULTICAST || defined __DOXYGEN__
-#define LWIP_LOOPIF_MULTICAST               0
-#endif
-
-/**
- * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
- * address equal to the netif IP address, looping them back up the stack.
- */
-#if !defined LWIP_NETIF_LOOPBACK || defined __DOXYGEN__
-#define LWIP_NETIF_LOOPBACK             0
-#endif
-
-/**
- * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
- * sending for each netif (0 = disabled)
- */
-#if !defined LWIP_LOOPBACK_MAX_PBUFS || defined __DOXYGEN__
-#define LWIP_LOOPBACK_MAX_PBUFS         0
-#endif
-
-/**
- * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in
- * the system, as netifs must change how they behave depending on this setting
- * for the LWIP_NETIF_LOOPBACK option to work.
- * Setting this is needed to avoid reentering non-reentrant functions like
- * tcp_input().
- *    LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a
- *       multithreaded environment like tcpip.c. In this case, netif->input()
- *       is called directly.
- *    LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
- *       The packets are put on a list and netif_poll() must be called in
- *       the main application loop.
- */
-#if !defined LWIP_NETIF_LOOPBACK_MULTITHREADING || defined __DOXYGEN__
-#define LWIP_NETIF_LOOPBACK_MULTITHREADING    (!NO_SYS)
-#endif
-/**
- * @}
- */
-
-/*
-   ------------------------------------
-   ---------- Thread options ----------
-   ------------------------------------
-*/
-/**
- * @defgroup lwip_opts_thread Threading
- * @ingroup lwip_opts_infrastructure
- * @{
- */
-/**
- * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
- */
-#if !defined TCPIP_THREAD_NAME || defined __DOXYGEN__
-#define TCPIP_THREAD_NAME              "tcpip_thread"
-#endif
-
-/**
- * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
- * The stack size value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#if !defined TCPIP_THREAD_STACKSIZE || defined __DOXYGEN__
-#define TCPIP_THREAD_STACKSIZE          0
-#endif
-
-/**
- * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
- * The priority value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#if !defined TCPIP_THREAD_PRIO || defined __DOXYGEN__
-#define TCPIP_THREAD_PRIO               1
-#endif
-
-/**
- * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
- * The queue size value itself is platform-dependent, but is passed to
- * sys_mbox_new() when tcpip_init is called.
- */
-#if !defined TCPIP_MBOX_SIZE || defined __DOXYGEN__
-#define TCPIP_MBOX_SIZE                 0
-#endif
-
-/**
- * Define this to something that triggers a watchdog. This is called from
- * tcpip_thread after processing a message.
- */
-#if !defined LWIP_TCPIP_THREAD_ALIVE || defined __DOXYGEN__
-#define LWIP_TCPIP_THREAD_ALIVE()
-#endif
-
-/**
- * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
- */
-#if !defined SLIPIF_THREAD_NAME || defined __DOXYGEN__
-#define SLIPIF_THREAD_NAME             "slipif_loop"
-#endif
-
-/**
- * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
- * The stack size value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#if !defined SLIPIF_THREAD_STACKSIZE || defined __DOXYGEN__
-#define SLIPIF_THREAD_STACKSIZE         0
-#endif
-
-/**
- * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
- * The priority value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#if !defined SLIPIF_THREAD_PRIO || defined __DOXYGEN__
-#define SLIPIF_THREAD_PRIO              1
-#endif
-
-/**
- * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
- */
-#if !defined DEFAULT_THREAD_NAME || defined __DOXYGEN__
-#define DEFAULT_THREAD_NAME            "lwIP"
-#endif
-
-/**
- * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
- * The stack size value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#if !defined DEFAULT_THREAD_STACKSIZE || defined __DOXYGEN__
-#define DEFAULT_THREAD_STACKSIZE        0
-#endif
-
-/**
- * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
- * The priority value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#if !defined DEFAULT_THREAD_PRIO || defined __DOXYGEN__
-#define DEFAULT_THREAD_PRIO             1
-#endif
-
-/**
- * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
- * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
- * to sys_mbox_new() when the recvmbox is created.
- */
-#if !defined DEFAULT_RAW_RECVMBOX_SIZE || defined __DOXYGEN__
-#define DEFAULT_RAW_RECVMBOX_SIZE       0
-#endif
-
-/**
- * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
- * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
- * to sys_mbox_new() when the recvmbox is created.
- */
-#if !defined DEFAULT_UDP_RECVMBOX_SIZE || defined __DOXYGEN__
-#define DEFAULT_UDP_RECVMBOX_SIZE       0
-#endif
-
-/**
- * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
- * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
- * to sys_mbox_new() when the recvmbox is created.
- */
-#if !defined DEFAULT_TCP_RECVMBOX_SIZE || defined __DOXYGEN__
-#define DEFAULT_TCP_RECVMBOX_SIZE       0
-#endif
-
-/**
- * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
- * The queue size value itself is platform-dependent, but is passed to
- * sys_mbox_new() when the acceptmbox is created.
- */
-#if !defined DEFAULT_ACCEPTMBOX_SIZE || defined __DOXYGEN__
-#define DEFAULT_ACCEPTMBOX_SIZE         0
-#endif
-/**
- * @}
- */
-
-/*
-   ----------------------------------------------
-   ---------- Sequential layer options ----------
-   ----------------------------------------------
-*/
-/**
- * @defgroup lwip_opts_netconn Netconn
- * @ingroup lwip_opts_threadsafe_apis
- * @{
- */
-/**
- * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
- */
-#if !defined LWIP_NETCONN || defined __DOXYGEN__
-#define LWIP_NETCONN                    1
-#endif
-
-/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout to create
- * timers running in tcpip_thread from another thread.
- */
-#if !defined LWIP_TCPIP_TIMEOUT || defined __DOXYGEN__
-#define LWIP_TCPIP_TIMEOUT              0
-#endif
-
-/** LWIP_NETCONN_SEM_PER_THREAD==1: Use one (thread-local) semaphore per
- * thread calling socket/netconn functions instead of allocating one
- * semaphore per netconn (and per select etc.)
- * ATTENTION: a thread-local semaphore for API calls is needed:
- * - LWIP_NETCONN_THREAD_SEM_GET() returning a sys_sem_t*
- * - LWIP_NETCONN_THREAD_SEM_ALLOC() creating the semaphore
- * - LWIP_NETCONN_THREAD_SEM_FREE() freeing the semaphore
- * The latter 2 can be invoked up by calling netconn_thread_init()/netconn_thread_cleanup().
- * Ports may call these for threads created with sys_thread_new().
- */
-#if !defined LWIP_NETCONN_SEM_PER_THREAD || defined __DOXYGEN__
-#define LWIP_NETCONN_SEM_PER_THREAD     0
-#endif
-
-/** LWIP_NETCONN_FULLDUPLEX==1: Enable code that allows reading from one thread,
- * writing from a 2nd thread and closing from a 3rd thread at the same time.
- * ATTENTION: This is currently really alpha! Some requirements:
- * - LWIP_NETCONN_SEM_PER_THREAD==1 is required to use one socket/netconn from
- *   multiple threads at once
- * - sys_mbox_free() has to unblock receive tasks waiting on recvmbox/acceptmbox
- *   and prevent a task pending on this during/after deletion
- */
-#if !defined LWIP_NETCONN_FULLDUPLEX || defined __DOXYGEN__
-#define LWIP_NETCONN_FULLDUPLEX         0
-#endif
-/**
- * @}
- */
-
-/*
-   ------------------------------------
-   ---------- Socket options ----------
-   ------------------------------------
-*/
-/**
- * @defgroup lwip_opts_socket Sockets
- * @ingroup lwip_opts_threadsafe_apis
- * @{
- */
-/**
- * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
- */
-#if !defined LWIP_SOCKET || defined __DOXYGEN__
-#define LWIP_SOCKET                     1
-#endif
-
-/* LWIP_SOCKET_SET_ERRNO==1: Set errno when socket functions cannot complete
- * successfully, as required by POSIX. Default is POSIX-compliant.
- */
-#if !defined LWIP_SOCKET_SET_ERRNO || defined __DOXYGEN__
-#define LWIP_SOCKET_SET_ERRNO           1
-#endif
-
-/**
- * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names through defines.
- * LWIP_COMPAT_SOCKETS==2: Same as ==1 but correctly named functions are created.
- * While this helps code completion, it might conflict with existing libraries.
- * (only used if you use sockets.c)
- */
-#if !defined LWIP_COMPAT_SOCKETS || defined __DOXYGEN__
-#define LWIP_COMPAT_SOCKETS             1
-#endif
-
-/**
- * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
- * Disable this option if you use a POSIX operating system that uses the same
- * names (read, write & close). (only used if you use sockets.c)
- */
-#if !defined LWIP_POSIX_SOCKETS_IO_NAMES || defined __DOXYGEN__
-#define LWIP_POSIX_SOCKETS_IO_NAMES     1
-#endif
-
-/**
- * LWIP_SOCKET_OFFSET==n: Increases the file descriptor number created by LwIP with n.
- * This can be useful when there are multiple APIs which create file descriptors.
- * When they all start with a different offset and you won't make them overlap you can
- * re implement read/write/close/ioctl/fnctl to send the requested action to the right
- * library (sharing select will need more work though).
- */
-#if !defined LWIP_SOCKET_OFFSET || defined __DOXYGEN__
-#define LWIP_SOCKET_OFFSET              0
-#endif
-
-/**
- * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
- * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
- * in seconds. (does not require sockets.c, and will affect tcp.c)
- */
-#if !defined LWIP_TCP_KEEPALIVE || defined __DOXYGEN__
-#define LWIP_TCP_KEEPALIVE              0
-#endif
-
-/**
- * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
- * SO_SNDTIMEO processing.
- */
-#if !defined LWIP_SO_SNDTIMEO || defined __DOXYGEN__
-#define LWIP_SO_SNDTIMEO                0
-#endif
-
-/**
- * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
- * SO_RCVTIMEO processing.
- */
-#if !defined LWIP_SO_RCVTIMEO || defined __DOXYGEN__
-#define LWIP_SO_RCVTIMEO                0
-#endif
-
-/**
- * LWIP_SO_SNDRCVTIMEO_NONSTANDARD==1: SO_RCVTIMEO/SO_SNDTIMEO take an int
- * (milliseconds, much like winsock does) instead of a struct timeval (default).
- */
-#if !defined LWIP_SO_SNDRCVTIMEO_NONSTANDARD || defined __DOXYGEN__
-#define LWIP_SO_SNDRCVTIMEO_NONSTANDARD 0
-#endif
-
-/**
- * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
- */
-#if !defined LWIP_SO_RCVBUF || defined __DOXYGEN__
-#define LWIP_SO_RCVBUF                  0
-#endif
-
-/**
- * LWIP_SO_LINGER==1: Enable SO_LINGER processing.
- */
-#if !defined LWIP_SO_LINGER || defined __DOXYGEN__
-#define LWIP_SO_LINGER                  0
-#endif
-
-/**
- * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize.
- */
-#if !defined RECV_BUFSIZE_DEFAULT || defined __DOXYGEN__
-#define RECV_BUFSIZE_DEFAULT            INT_MAX
-#endif
-
-/**
- * By default, TCP socket/netconn close waits 20 seconds max to send the FIN
- */
-#if !defined LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT || defined __DOXYGEN__
-#define LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT 20000
-#endif
-
-/**
- * SO_REUSE==1: Enable SO_REUSEADDR option.
- */
-#if !defined SO_REUSE || defined __DOXYGEN__
-#define SO_REUSE                        0
-#endif
-
-/**
- * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets
- * to all local matches if SO_REUSEADDR is turned on.
- * WARNING: Adds a memcpy for every packet if passing to more than one pcb!
- */
-#if !defined SO_REUSE_RXTOALL || defined __DOXYGEN__
-#define SO_REUSE_RXTOALL                0
-#endif
-
-/**
- * LWIP_FIONREAD_LINUXMODE==0 (default): ioctl/FIONREAD returns the amount of
- * pending data in the network buffer. This is the way windows does it. It's
- * the default for lwIP since it is smaller.
- * LWIP_FIONREAD_LINUXMODE==1: ioctl/FIONREAD returns the size of the next
- * pending datagram in bytes. This is the way linux does it. This code is only
- * here for compatibility.
- */
-#if !defined LWIP_FIONREAD_LINUXMODE || defined __DOXYGEN__
-#define LWIP_FIONREAD_LINUXMODE         0
-#endif
-/**
- * @}
- */
-
-/*
-   ----------------------------------------
-   ---------- Statistics options ----------
-   ----------------------------------------
-*/
-/**
- * @defgroup lwip_opts_stats Statistics
- * @ingroup lwip_opts_debug
- * @{
- */
-/**
- * LWIP_STATS==1: Enable statistics collection in lwip_stats.
- */
-#if !defined LWIP_STATS || defined __DOXYGEN__
-#define LWIP_STATS                      1
-#endif
-
-#if LWIP_STATS
-
-/**
- * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
- */
-#if !defined LWIP_STATS_DISPLAY || defined __DOXYGEN__
-#define LWIP_STATS_DISPLAY              0
-#endif
-
-/**
- * LINK_STATS==1: Enable link stats.
- */
-#if !defined LINK_STATS || defined __DOXYGEN__
-#define LINK_STATS                      1
-#endif
-
-/**
- * ETHARP_STATS==1: Enable etharp stats.
- */
-#if !defined ETHARP_STATS || defined __DOXYGEN__
-#define ETHARP_STATS                    (LWIP_ARP)
-#endif
-
-/**
- * IP_STATS==1: Enable IP stats.
- */
-#if !defined IP_STATS || defined __DOXYGEN__
-#define IP_STATS                        1
-#endif
-
-/**
- * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
- * on if using either frag or reass.
- */
-#if !defined IPFRAG_STATS || defined __DOXYGEN__
-#define IPFRAG_STATS                    (IP_REASSEMBLY || IP_FRAG)
-#endif
-
-/**
- * ICMP_STATS==1: Enable ICMP stats.
- */
-#if !defined ICMP_STATS || defined __DOXYGEN__
-#define ICMP_STATS                      1
-#endif
-
-/**
- * IGMP_STATS==1: Enable IGMP stats.
- */
-#if !defined IGMP_STATS || defined __DOXYGEN__
-#define IGMP_STATS                      (LWIP_IGMP)
-#endif
-
-/**
- * UDP_STATS==1: Enable UDP stats. Default is on if
- * UDP enabled, otherwise off.
- */
-#if !defined UDP_STATS || defined __DOXYGEN__
-#define UDP_STATS                       (LWIP_UDP)
-#endif
-
-/**
- * TCP_STATS==1: Enable TCP stats. Default is on if TCP
- * enabled, otherwise off.
- */
-#if !defined TCP_STATS || defined __DOXYGEN__
-#define TCP_STATS                       (LWIP_TCP)
-#endif
-
-/**
- * MEM_STATS==1: Enable mem.c stats.
- */
-#if !defined MEM_STATS || defined __DOXYGEN__
-#define MEM_STATS                       ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0))
-#endif
-
-/**
- * MEMP_STATS==1: Enable memp.c pool stats.
- */
-#if !defined MEMP_STATS || defined __DOXYGEN__
-#define MEMP_STATS                      (MEMP_MEM_MALLOC == 0)
-#endif
-
-/**
- * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
- */
-#if !defined SYS_STATS || defined __DOXYGEN__
-#define SYS_STATS                       (NO_SYS == 0)
-#endif
-
-/**
- * IP6_STATS==1: Enable IPv6 stats.
- */
-#if !defined IP6_STATS || defined __DOXYGEN__
-#define IP6_STATS                       (LWIP_IPV6)
-#endif
-
-/**
- * ICMP6_STATS==1: Enable ICMP for IPv6 stats.
- */
-#if !defined ICMP6_STATS || defined __DOXYGEN__
-#define ICMP6_STATS                     (LWIP_IPV6 && LWIP_ICMP6)
-#endif
-
-/**
- * IP6_FRAG_STATS==1: Enable IPv6 fragmentation stats.
- */
-#if !defined IP6_FRAG_STATS || defined __DOXYGEN__
-#define IP6_FRAG_STATS                  (LWIP_IPV6 && (LWIP_IPV6_FRAG || LWIP_IPV6_REASS))
-#endif
-
-/**
- * MLD6_STATS==1: Enable MLD for IPv6 stats.
- */
-#if !defined MLD6_STATS || defined __DOXYGEN__
-#define MLD6_STATS                      (LWIP_IPV6 && LWIP_IPV6_MLD)
-#endif
-
-/**
- * ND6_STATS==1: Enable Neighbor discovery for IPv6 stats.
- */
-#if !defined ND6_STATS || defined __DOXYGEN__
-#define ND6_STATS                       (LWIP_IPV6)
-#endif
-
-/**
- * MIB2_STATS==1: Stats for SNMP MIB2.
- */
-#if !defined MIB2_STATS || defined __DOXYGEN__
-#define MIB2_STATS                      0
-#endif
-
-#else
-
-#define LINK_STATS                      0
-#define ETHARP_STATS                    0
-#define IP_STATS                        0
-#define IPFRAG_STATS                    0
-#define ICMP_STATS                      0
-#define IGMP_STATS                      0
-#define UDP_STATS                       0
-#define TCP_STATS                       0
-#define MEM_STATS                       0
-#define MEMP_STATS                      0
-#define SYS_STATS                       0
-#define LWIP_STATS_DISPLAY              0
-#define IP6_STATS                       0
-#define ICMP6_STATS                     0
-#define IP6_FRAG_STATS                  0
-#define MLD6_STATS                      0
-#define ND6_STATS                       0
-#define MIB2_STATS                      0
-
-#endif /* LWIP_STATS */
-/**
- * @}
- */
-
-/*
-   --------------------------------------
-   ---------- Checksum options ----------
-   --------------------------------------
-*/
-/**
- * @defgroup lwip_opts_checksum Checksum
- * @ingroup lwip_opts_infrastructure
- * @{
- */
-/**
- * LWIP_CHECKSUM_CTRL_PER_NETIF==1: Checksum generation/check can be enabled/disabled
- * per netif.
- * ATTENTION: if enabled, the CHECKSUM_GEN_* and CHECKSUM_CHECK_* defines must be enabled!
- */
-#if !defined LWIP_CHECKSUM_CTRL_PER_NETIF || defined __DOXYGEN__
-#define LWIP_CHECKSUM_CTRL_PER_NETIF    0
-#endif
-
-/**
- * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
- */
-#if !defined CHECKSUM_GEN_IP || defined __DOXYGEN__
-#define CHECKSUM_GEN_IP                 1
-#endif
-
-/**
- * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
- */
-#if !defined CHECKSUM_GEN_UDP || defined __DOXYGEN__
-#define CHECKSUM_GEN_UDP                1
-#endif
-
-/**
- * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
- */
-#if !defined CHECKSUM_GEN_TCP || defined __DOXYGEN__
-#define CHECKSUM_GEN_TCP                1
-#endif
-
-/**
- * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets.
- */
-#if !defined CHECKSUM_GEN_ICMP || defined __DOXYGEN__
-#define CHECKSUM_GEN_ICMP               1
-#endif
-
-/**
- * CHECKSUM_GEN_ICMP6==1: Generate checksums in software for outgoing ICMP6 packets.
- */
-#if !defined CHECKSUM_GEN_ICMP6 || defined __DOXYGEN__
-#define CHECKSUM_GEN_ICMP6              1
-#endif
-
-/**
- * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
- */
-#if !defined CHECKSUM_CHECK_IP || defined __DOXYGEN__
-#define CHECKSUM_CHECK_IP               1
-#endif
-
-/**
- * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
- */
-#if !defined CHECKSUM_CHECK_UDP || defined __DOXYGEN__
-#define CHECKSUM_CHECK_UDP              1
-#endif
-
-/**
- * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
- */
-#if !defined CHECKSUM_CHECK_TCP || defined __DOXYGEN__
-#define CHECKSUM_CHECK_TCP              1
-#endif
-
-/**
- * CHECKSUM_CHECK_ICMP==1: Check checksums in software for incoming ICMP packets.
- */
-#if !defined CHECKSUM_CHECK_ICMP || defined __DOXYGEN__
-#define CHECKSUM_CHECK_ICMP             1
-#endif
-
-/**
- * CHECKSUM_CHECK_ICMP6==1: Check checksums in software for incoming ICMPv6 packets
- */
-#if !defined CHECKSUM_CHECK_ICMP6 || defined __DOXYGEN__
-#define CHECKSUM_CHECK_ICMP6            1
-#endif
-
-/**
- * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from
- * application buffers to pbufs.
- */
-#if !defined LWIP_CHECKSUM_ON_COPY || defined __DOXYGEN__
-#define LWIP_CHECKSUM_ON_COPY           0
-#endif
-/**
- * @}
- */
-
-/*
-   ---------------------------------------
-   ---------- IPv6 options ---------------
-   ---------------------------------------
-*/
-/**
- * @defgroup lwip_opts_ipv6 IPv6
- * @ingroup lwip_opts
- * @{
- */
-/**
- * LWIP_IPV6==1: Enable IPv6
- */
-#if !defined LWIP_IPV6 || defined __DOXYGEN__
-#define LWIP_IPV6                       0
-#endif
-
-/**
- * LWIP_IPV6_NUM_ADDRESSES: Number of IPv6 addresses per netif.
- */
-#if !defined LWIP_IPV6_NUM_ADDRESSES || defined __DOXYGEN__
-#define LWIP_IPV6_NUM_ADDRESSES         3
-#endif
-
-/**
- * LWIP_IPV6_FORWARD==1: Forward IPv6 packets across netifs
- */
-#if !defined LWIP_IPV6_FORWARD || defined __DOXYGEN__
-#define LWIP_IPV6_FORWARD               0
-#endif
-
-/**
- * LWIP_IPV6_FRAG==1: Fragment outgoing IPv6 packets that are too big.
- */
-#if !defined LWIP_IPV6_FRAG || defined __DOXYGEN__
-#define LWIP_IPV6_FRAG                  0
-#endif
-
-/**
- * LWIP_IPV6_REASS==1: reassemble incoming IPv6 packets that fragmented
- */
-#if !defined LWIP_IPV6_REASS || defined __DOXYGEN__
-#define LWIP_IPV6_REASS                 (LWIP_IPV6)
-#endif
-
-/**
- * LWIP_IPV6_SEND_ROUTER_SOLICIT==1: Send router solicitation messages during
- * network startup.
- */
-#if !defined LWIP_IPV6_SEND_ROUTER_SOLICIT || defined __DOXYGEN__
-#define LWIP_IPV6_SEND_ROUTER_SOLICIT   1
-#endif
-
-/**
- * LWIP_IPV6_AUTOCONFIG==1: Enable stateless address autoconfiguration as per RFC 4862.
- */
-#if !defined LWIP_IPV6_AUTOCONFIG || defined __DOXYGEN__
-#define LWIP_IPV6_AUTOCONFIG            (LWIP_IPV6)
-#endif
-
-/**
- * LWIP_IPV6_DUP_DETECT_ATTEMPTS=[0..7]: Number of duplicate address detection attempts.
- */
-#if !defined LWIP_IPV6_DUP_DETECT_ATTEMPTS || defined __DOXYGEN__
-#define LWIP_IPV6_DUP_DETECT_ATTEMPTS   1
-#endif
-/**
- * @}
- */
-
-/**
- * @defgroup lwip_opts_icmp6 ICMP6
- * @ingroup lwip_opts_ipv6
- * @{
- */
-/**
- * LWIP_ICMP6==1: Enable ICMPv6 (mandatory per RFC)
- */
-#if !defined LWIP_ICMP6 || defined __DOXYGEN__
-#define LWIP_ICMP6                      (LWIP_IPV6)
-#endif
-
-/**
- * LWIP_ICMP6_DATASIZE: bytes from original packet to send back in
- * ICMPv6 error messages.
- */
-#if !defined LWIP_ICMP6_DATASIZE || defined __DOXYGEN__
-#define LWIP_ICMP6_DATASIZE             8
-#endif
-
-/**
- * LWIP_ICMP6_HL: default hop limit for ICMPv6 messages
- */
-#if !defined LWIP_ICMP6_HL || defined __DOXYGEN__
-#define LWIP_ICMP6_HL                   255
-#endif
-/**
- * @}
- */
-
-/**
- * @defgroup lwip_opts_mld6 Multicast listener discovery
- * @ingroup lwip_opts_ipv6
- * @{
- */
-/**
- * LWIP_IPV6_MLD==1: Enable multicast listener discovery protocol.
- * If LWIP_IPV6 is enabled but this setting is disabled, the MAC layer must
- * indiscriminately pass all inbound IPv6 multicast traffic to lwIP.
- */
-#if !defined LWIP_IPV6_MLD || defined __DOXYGEN__
-#define LWIP_IPV6_MLD                   (LWIP_IPV6)
-#endif
-
-/**
- * MEMP_NUM_MLD6_GROUP: Max number of IPv6 multicast groups that can be joined.
- * There must be enough groups so that each netif can join the solicited-node
- * multicast group for each of its local addresses, plus one for MDNS if
- * applicable, plus any number of groups to be joined on UDP sockets.
- */
-#if !defined MEMP_NUM_MLD6_GROUP || defined __DOXYGEN__
-#define MEMP_NUM_MLD6_GROUP             4
-#endif
-/**
- * @}
- */
-
-/**
- * @defgroup lwip_opts_nd6 Neighbor discovery
- * @ingroup lwip_opts_ipv6
- * @{
- */
-/**
- * LWIP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address
- * is being resolved.
- */
-#if !defined LWIP_ND6_QUEUEING || defined __DOXYGEN__
-#define LWIP_ND6_QUEUEING               (LWIP_IPV6)
-#endif
-
-/**
- * ESP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address
- * is being resolved.
- */
-#if !defined ESP_ND6_QUEUEING || defined __DOXYGEN__
-#define ESP_ND6_QUEUEING               LWIP_IPV6
-#endif
-
-/**
- * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution.
- */
-#if !defined MEMP_NUM_ND6_QUEUE || defined __DOXYGEN__
-#define MEMP_NUM_ND6_QUEUE              20
-#endif
-
-/**
- * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache
- */
-#if !defined LWIP_ND6_NUM_NEIGHBORS || defined __DOXYGEN__
-#define LWIP_ND6_NUM_NEIGHBORS          10
-#endif
-
-/**
- * LWIP_ND6_NUM_DESTINATIONS: number of entries in IPv6 destination cache
- */
-#if !defined LWIP_ND6_NUM_DESTINATIONS || defined __DOXYGEN__
-#define LWIP_ND6_NUM_DESTINATIONS       10
-#endif
-
-/**
- * LWIP_ND6_NUM_PREFIXES: number of entries in IPv6 on-link prefixes cache
- */
-#if !defined LWIP_ND6_NUM_PREFIXES || defined __DOXYGEN__
-#define LWIP_ND6_NUM_PREFIXES           5
-#endif
-
-/**
- * LWIP_ND6_NUM_ROUTERS: number of entries in IPv6 default router cache
- */
-#if !defined LWIP_ND6_NUM_ROUTERS || defined __DOXYGEN__
-#define LWIP_ND6_NUM_ROUTERS            3
-#endif
-
-/**
- * LWIP_ND6_MAX_MULTICAST_SOLICIT: max number of multicast solicit messages to send
- * (neighbor solicit and router solicit)
- */
-#if !defined LWIP_ND6_MAX_MULTICAST_SOLICIT || defined __DOXYGEN__
-#define LWIP_ND6_MAX_MULTICAST_SOLICIT  3
-#endif
-
-/**
- * LWIP_ND6_MAX_UNICAST_SOLICIT: max number of unicast neighbor solicitation messages
- * to send during neighbor reachability detection.
- */
-#if !defined LWIP_ND6_MAX_UNICAST_SOLICIT || defined __DOXYGEN__
-#define LWIP_ND6_MAX_UNICAST_SOLICIT    3
-#endif
-
-/**
- * Unused: See ND RFC (time in milliseconds).
- */
-#if !defined LWIP_ND6_MAX_ANYCAST_DELAY_TIME || defined __DOXYGEN__
-#define LWIP_ND6_MAX_ANYCAST_DELAY_TIME 1000
-#endif
-
-/**
- * Unused: See ND RFC
- */
-#if !defined LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT || defined __DOXYGEN__
-#define LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT  3
-#endif
-
-/**
- * LWIP_ND6_REACHABLE_TIME: default neighbor reachable time (in milliseconds).
- * May be updated by router advertisement messages.
- */
-#if !defined LWIP_ND6_REACHABLE_TIME || defined __DOXYGEN__
-#define LWIP_ND6_REACHABLE_TIME         30000
-#endif
-
-/**
- * LWIP_ND6_RETRANS_TIMER: default retransmission timer for solicitation messages
- */
-#if !defined LWIP_ND6_RETRANS_TIMER || defined __DOXYGEN__
-#define LWIP_ND6_RETRANS_TIMER          1000
-#endif
-
-/**
- * LWIP_ND6_DELAY_FIRST_PROBE_TIME: Delay before first unicast neighbor solicitation
- * message is sent, during neighbor reachability detection.
- */
-#if !defined LWIP_ND6_DELAY_FIRST_PROBE_TIME || defined __DOXYGEN__
-#define LWIP_ND6_DELAY_FIRST_PROBE_TIME 5000
-#endif
-
-/**
- * LWIP_ND6_ALLOW_RA_UPDATES==1: Allow Router Advertisement messages to update
- * Reachable time and retransmission timers, and netif MTU.
- */
-#if !defined LWIP_ND6_ALLOW_RA_UPDATES || defined __DOXYGEN__
-#define LWIP_ND6_ALLOW_RA_UPDATES       1
-#endif
-
-/**
- * LWIP_ND6_TCP_REACHABILITY_HINTS==1: Allow TCP to provide Neighbor Discovery
- * with reachability hints for connected destinations. This helps avoid sending
- * unicast neighbor solicitation messages.
- */
-#if !defined LWIP_ND6_TCP_REACHABILITY_HINTS || defined __DOXYGEN__
-#define LWIP_ND6_TCP_REACHABILITY_HINTS 1
-#endif
-
-/**
- * LWIP_ND6_RDNSS_MAX_DNS_SERVERS > 0: Use IPv6 Router Advertisement Recursive
- * DNS Server Option (as per RFC 6106) to copy a defined maximum number of DNS
- * servers to the DNS module.
- */
-#if !defined LWIP_ND6_RDNSS_MAX_DNS_SERVERS || defined __DOXYGEN__
-#define LWIP_ND6_RDNSS_MAX_DNS_SERVERS  0
-#endif
-/**
- * @}
- */
-
-/**
- * LWIP_IPV6_DHCP6==1: enable DHCPv6 stateful address autoconfiguration.
- */
-#if !defined LWIP_IPV6_DHCP6 || defined __DOXYGEN__
-#define LWIP_IPV6_DHCP6                 0
-#endif
-
-/*
-   ---------------------------------------
-   ---------- Hook options ---------------
-   ---------------------------------------
-*/
-
-/**
- * @defgroup lwip_opts_hooks Hooks
- * @ingroup lwip_opts_infrastructure
- * Hooks are undefined by default, define them to a function if you need them.
- * @{
- */
-
-/**
- * LWIP_HOOK_FILENAME: Custom filename to #include in files that provide hooks.
- * Declare your hook function prototypes in there, you may also #include all headers
- * providing data types that are need in this file.
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_FILENAME "path/to/my/lwip_hooks.h"
-#endif
-
-/**
- * LWIP_HOOK_TCP_ISN:
- * Hook for generation of the Initial Sequence Number (ISN) for a new TCP
- * connection. The default lwIP ISN generation algorithm is very basic and may
- * allow for TCP spoofing attacks. This hook provides the means to implement
- * the standardized ISN generation algorithm from RFC 6528 (see contrib/adons/tcp_isn),
- * or any other desired algorithm as a replacement.
- * Called from tcp_connect() and tcp_listen_input() when an ISN is needed for
- * a new TCP connection, if TCP support (@ref LWIP_TCP) is enabled.\n
- * Signature: u32_t my_hook_tcp_isn(const ip_addr_t* local_ip, u16_t local_port, const ip_addr_t* remote_ip, u16_t remote_port);
- * - it may be necessary to use "struct ip_addr" (ip4_addr, ip6_addr) instead of "ip_addr_t" in function declarations\n
- * Arguments:
- * - local_ip: pointer to the local IP address of the connection
- * - local_port: local port number of the connection (host-byte order)
- * - remote_ip: pointer to the remote IP address of the connection
- * - remote_port: remote port number of the connection (host-byte order)\n
- * Return value:
- * - the 32-bit Initial Sequence Number to use for the new TCP connection.
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_TCP_ISN(local_ip, local_port, remote_ip, remote_port)
-#endif
-
-/**
- * LWIP_HOOK_IP4_INPUT(pbuf, input_netif):
- * - called from ip_input() (IPv4)
- * - pbuf: received struct pbuf passed to ip_input()
- * - input_netif: struct netif on which the packet has been received
- * Return values:
- * - 0: Hook has not consumed the packet, packet is processed as normal
- * - != 0: Hook has consumed the packet.
- * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook
- * (i.e. free it when done).
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_IP4_INPUT(pbuf, input_netif)
-#endif
-
-/**
- * LWIP_HOOK_IP4_ROUTE(dest):
- * - called from ip_route() (IPv4)
- * - dest: destination IPv4 address
- * Returns the destination netif or NULL if no destination netif is found. In
- * that case, ip_route() continues as normal.
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_IP4_ROUTE()
-#endif
-
-/**
- * LWIP_HOOK_IP4_ROUTE_SRC(dest, src):
- * - source-based routing for IPv4 (see LWIP_HOOK_IP4_ROUTE(), src may be NULL)
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_IP4_ROUTE_SRC(dest, src)
-#endif
-
-/**
- * LWIP_HOOK_ETHARP_GET_GW(netif, dest):
- * - called from etharp_output() (IPv4)
- * - netif: the netif used for sending
- * - dest: the destination IPv4 address
- * Returns the IPv4 address of the gateway to handle the specified destination
- * IPv4 address. If NULL is returned, the netif's default gateway is used.
- * The returned address MUST be directly reachable on the specified netif!
- * This function is meant to implement advanced IPv4 routing together with
- * LWIP_HOOK_IP4_ROUTE(). The actual routing/gateway table implementation is
- * not part of lwIP but can e.g. be hidden in the netif's state argument.
-*/
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_ETHARP_GET_GW(netif, dest)
-#endif
-
-/**
- * LWIP_HOOK_IP6_INPUT(pbuf, input_netif):
- * - called from ip6_input() (IPv6)
- * - pbuf: received struct pbuf passed to ip6_input()
- * - input_netif: struct netif on which the packet has been received
- * Return values:
- * - 0: Hook has not consumed the packet, packet is processed as normal
- * - != 0: Hook has consumed the packet.
- * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook
- * (i.e. free it when done).
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_IP6_INPUT(pbuf, input_netif)
-#endif
-
-/**
- * LWIP_HOOK_IP6_ROUTE(src, dest):
- * - called from ip6_route() (IPv6)
- * - src: sourc IPv6 address
- * - dest: destination IPv6 address
- * Returns the destination netif or NULL if no destination netif is found. In
- * that case, ip6_route() continues as normal.
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_IP6_ROUTE(src, dest)
-#endif
-
-/**
- * LWIP_HOOK_ND6_GET_GW(netif, dest):
- * - called from nd6_get_next_hop_entry() (IPv6)
- * - netif: the netif used for sending
- * - dest: the destination IPv6 address
- * Returns the IPv6 address of the next hop to handle the specified destination
- * IPv6 address. If NULL is returned, a NDP-discovered router is used instead.
- * The returned address MUST be directly reachable on the specified netif!
- * This function is meant to implement advanced IPv6 routing together with
- * LWIP_HOOK_IP6_ROUTE(). The actual routing/gateway table implementation is
- * not part of lwIP but can e.g. be hidden in the netif's state argument.
-*/
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_ND6_GET_GW(netif, dest)
-#endif
-
-/**
- * LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr):
- * - called from ethernet_input() if VLAN support is enabled
- * - netif: struct netif on which the packet has been received
- * - eth_hdr: struct eth_hdr of the packet
- * - vlan_hdr: struct eth_vlan_hdr of the packet
- * Return values:
- * - 0: Packet must be dropped.
- * - != 0: Packet must be accepted.
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr)
-#endif
-
-/**
- * LWIP_HOOK_VLAN_SET:
- * Hook can be used to set prio_vid field of vlan_hdr. If you need to store data
- * on per-netif basis to implement this callback, see @ref netif_cd.
- * Called from ethernet_output() if VLAN support (@ref ETHARP_SUPPORT_VLAN) is enabled.\n
- * Signature: s32_t my_hook_vlan_set(struct netif* netif, struct pbuf* pbuf, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type);\n
- * Arguments:
- * - netif: struct netif that the packet will be sent through
- * - p: struct pbuf packet to be sent
- * - src: source eth address
- * - dst: destination eth address
- * - eth_type: ethernet type to packet to be sent\n
- * 
- * 
- * Return values:
- * - &lt;0: Packet shall not contain VLAN header.
- * - 0 &lt;= return value &lt;= 0xFFFF: Packet shall contain VLAN header. Return value is prio_vid in host byte order.
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_VLAN_SET(netif, p, src, dst, eth_type)
-#endif
-
-/**
- * LWIP_HOOK_MEMP_AVAILABLE(memp_t_type):
- * - called from memp_free() when a memp pool was empty and an item is now available
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_MEMP_AVAILABLE(memp_t_type)
-#endif
-
-/**
- * LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif):
- * Called from ethernet_input() when an unknown eth type is encountered.
- * Return ERR_OK if packet is accepted, any error code otherwise.
- * Payload points to ethernet header!
- */
-#ifdef __DOXYGEN__
-#define LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif)
-#endif
-/**
- * @}
- */
-
-/*
-   ---------------------------------------
-   ---------- Debugging options ----------
-   ---------------------------------------
-*/
-/**
- * @defgroup lwip_opts_debugmsg Debug messages
- * @ingroup lwip_opts_debug
- * @{
- */
-/**
- * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
- * compared against this value. If it is smaller, then debugging
- * messages are written.
- * @see debugging_levels
- */
-#if !defined LWIP_DBG_MIN_LEVEL || defined __DOXYGEN__
-#define LWIP_DBG_MIN_LEVEL              LWIP_DBG_LEVEL_ALL
-#endif
-
-/**
- * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
- * debug messages of certain types.
- * @see debugging_levels
- */
-#if !defined LWIP_DBG_TYPES_ON || defined __DOXYGEN__
-#define LWIP_DBG_TYPES_ON               LWIP_DBG_ON
-#endif
-
-/**
- * ETHARP_DEBUG: Enable debugging in etharp.c.
- */
-#if !defined ETHARP_DEBUG || defined __DOXYGEN__
-#define ETHARP_DEBUG                    LWIP_DBG_OFF
-#endif
-
-/**
- * NETIF_DEBUG: Enable debugging in netif.c.
- */
-#if !defined NETIF_DEBUG || defined __DOXYGEN__
-#define NETIF_DEBUG                     LWIP_DBG_OFF
-#endif
-
-/**
- * PBUF_DEBUG: Enable debugging in pbuf.c.
- */
-#if !defined PBUF_DEBUG || defined __DOXYGEN__
-#define PBUF_DEBUG                      LWIP_DBG_OFF
-#endif
-
-/**
- * API_LIB_DEBUG: Enable debugging in api_lib.c.
- */
-#if !defined API_LIB_DEBUG || defined __DOXYGEN__
-#define API_LIB_DEBUG                   LWIP_DBG_OFF
-#endif
-
-/**
- * API_MSG_DEBUG: Enable debugging in api_msg.c.
- */
-#if !defined API_MSG_DEBUG || defined __DOXYGEN__
-#define API_MSG_DEBUG                   LWIP_DBG_OFF
-#endif
-
-/**
- * SOCKETS_DEBUG: Enable debugging in sockets.c.
- */
-#if !defined SOCKETS_DEBUG || defined __DOXYGEN__
-#define SOCKETS_DEBUG                   LWIP_DBG_OFF
-#endif
-
-/**
- * ICMP_DEBUG: Enable debugging in icmp.c.
- */
-#if !defined ICMP_DEBUG || defined __DOXYGEN__
-#define ICMP_DEBUG                      LWIP_DBG_OFF
-#endif
-
-/**
- * IGMP_DEBUG: Enable debugging in igmp.c.
- */
-#if !defined IGMP_DEBUG || defined __DOXYGEN__
-#define IGMP_DEBUG                      LWIP_DBG_OFF
-#endif
-
-/**
- * INET_DEBUG: Enable debugging in inet.c.
- */
-#if !defined INET_DEBUG || defined __DOXYGEN__
-#define INET_DEBUG                      LWIP_DBG_OFF
-#endif
-
-/**
- * IP_DEBUG: Enable debugging for IP.
- */
-#if !defined IP_DEBUG || defined __DOXYGEN__
-#define IP_DEBUG                        LWIP_DBG_OFF
-#endif
-
-/**
- * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
- */
-#if !defined IP_REASS_DEBUG || defined __DOXYGEN__
-#define IP_REASS_DEBUG                  LWIP_DBG_OFF
-#endif
-
-/**
- * RAW_DEBUG: Enable debugging in raw.c.
- */
-#if !defined RAW_DEBUG || defined __DOXYGEN__
-#define RAW_DEBUG                       LWIP_DBG_OFF
-#endif
-
-/**
- * MEM_DEBUG: Enable debugging in mem.c.
- */
-#if !defined MEM_DEBUG || defined __DOXYGEN__
-#define MEM_DEBUG                       LWIP_DBG_OFF
-#endif
-
-/**
- * MEMP_DEBUG: Enable debugging in memp.c.
- */
-#if !defined MEMP_DEBUG || defined __DOXYGEN__
-#define MEMP_DEBUG                      LWIP_DBG_OFF
-#endif
-
-/**
- * SYS_DEBUG: Enable debugging in sys.c.
- */
-#if !defined SYS_DEBUG || defined __DOXYGEN__
-#define SYS_DEBUG                       LWIP_DBG_OFF
-#endif
-
-/**
- * TIMERS_DEBUG: Enable debugging in timers.c.
- */
-#if !defined TIMERS_DEBUG || defined __DOXYGEN__
-#define TIMERS_DEBUG                    LWIP_DBG_OFF
-#endif
-
-/**
- * TCP_DEBUG: Enable debugging for TCP.
- */
-#if !defined TCP_DEBUG || defined __DOXYGEN__
-#define TCP_DEBUG                       LWIP_DBG_OFF
-#endif
-
-/**
- * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
- */
-#if !defined TCP_INPUT_DEBUG || defined __DOXYGEN__
-#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
-#endif
-
-/**
- * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
- */
-#if !defined TCP_FR_DEBUG || defined __DOXYGEN__
-#define TCP_FR_DEBUG                    LWIP_DBG_OFF
-#endif
-
-/**
- * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
- * timeout.
- */
-#if !defined TCP_RTO_DEBUG || defined __DOXYGEN__
-#define TCP_RTO_DEBUG                   LWIP_DBG_OFF
-#endif
-
-/**
- * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
- */
-#if !defined TCP_CWND_DEBUG || defined __DOXYGEN__
-#define TCP_CWND_DEBUG                  LWIP_DBG_OFF
-#endif
-
-/**
- * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
- */
-#if !defined TCP_WND_DEBUG || defined __DOXYGEN__
-#define TCP_WND_DEBUG                   LWIP_DBG_OFF
-#endif
-
-/**
- * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
- */
-#if !defined TCP_OUTPUT_DEBUG || defined __DOXYGEN__
-#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
-#endif
-
-/**
- * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
- */
-#if !defined TCP_RST_DEBUG || defined __DOXYGEN__
-#define TCP_RST_DEBUG                   LWIP_DBG_OFF
-#endif
-
-/**
- * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
- */
-#if !defined TCP_QLEN_DEBUG || defined __DOXYGEN__
-#define TCP_QLEN_DEBUG                  LWIP_DBG_OFF
-#endif
-
-/**
- * UDP_DEBUG: Enable debugging in UDP.
- */
-#if !defined UDP_DEBUG || defined __DOXYGEN__
-#define UDP_DEBUG                       LWIP_DBG_OFF
-#endif
-
-/**
- * TCPIP_DEBUG: Enable debugging in tcpip.c.
- */
-#if !defined TCPIP_DEBUG || defined __DOXYGEN__
-#define TCPIP_DEBUG                     LWIP_DBG_OFF
-#endif
-
-/**
- * SLIP_DEBUG: Enable debugging in slipif.c.
- */
-#if !defined SLIP_DEBUG || defined __DOXYGEN__
-#define SLIP_DEBUG                      LWIP_DBG_OFF
-#endif
-
-/**
- * DHCP_DEBUG: Enable debugging in dhcp.c.
- */
-#if !defined DHCP_DEBUG || defined __DOXYGEN__
-#define DHCP_DEBUG                      LWIP_DBG_OFF
-#endif
-
-/**
- * AUTOIP_DEBUG: Enable debugging in autoip.c.
- */
-#if !defined AUTOIP_DEBUG || defined __DOXYGEN__
-#define AUTOIP_DEBUG                    LWIP_DBG_OFF
-#endif
-
-/**
- * DNS_DEBUG: Enable debugging for DNS.
- */
-#if !defined DNS_DEBUG || defined __DOXYGEN__
-#define DNS_DEBUG                       LWIP_DBG_OFF
-#endif
-
-/**
- * IP6_DEBUG: Enable debugging for IPv6.
- */
-#if !defined IP6_DEBUG || defined __DOXYGEN__
-#define IP6_DEBUG                       LWIP_DBG_OFF
-#endif
-/**
- * @}
- */
-
-/*
-   --------------------------------------------------
-   ---------- Performance tracking options ----------
-   --------------------------------------------------
-*/
-/**
- * @defgroup lwip_opts_perf Performance
- * @ingroup lwip_opts_debug
- * @{
- */
-/**
- * LWIP_PERF: Enable performance testing for lwIP
- * (if enabled, arch/perf.h is included)
- */
-#if !defined LWIP_PERF || defined __DOXYGEN__
-#define LWIP_PERF                       0
-#endif
-/**
- * @}
- */
-
-#endif /* LWIP_HDR_OPT_H */
diff --git a/tools/sdk/include/lwip/lwip/pbuf.h b/tools/sdk/include/lwip/lwip/pbuf.h
deleted file mode 100644
index a8f1d951ade..00000000000
--- a/tools/sdk/include/lwip/lwip/pbuf.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/**
- * @file
- * pbuf API
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-#ifndef LWIP_HDR_PBUF_H
-#define LWIP_HDR_PBUF_H
-
-#include "lwip/opt.h"
-#include "lwip/err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LWIP_SUPPORT_CUSTOM_PBUF==1: Custom pbufs behave much like their pbuf type
- * but they are allocated by external code (initialised by calling
- * pbuf_alloced_custom()) and when pbuf_free gives up their last reference, they
- * are freed by calling pbuf_custom->custom_free_function().
- * Currently, the pbuf_custom code is only needed for one specific configuration
- * of IP_FRAG, unless required by external driver/application code. */
-#ifndef LWIP_SUPPORT_CUSTOM_PBUF
-#define LWIP_SUPPORT_CUSTOM_PBUF ((IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG))
-#endif
-
-/* @todo: We need a mechanism to prevent wasting memory in every pbuf
-   (TCP vs. UDP, IPv4 vs. IPv6: UDP/IPv4 packets may waste up to 28 bytes) */
-
-#define PBUF_TRANSPORT_HLEN 20
-#if LWIP_IPV6
-#define PBUF_IP_HLEN        40
-#else
-#define PBUF_IP_HLEN        20
-#endif
-
-/**
- * @ingroup pbuf
- * Enumeration of pbuf layers
- */
-typedef enum {
-  /** Includes spare room for transport layer header, e.g. UDP header.
-   * Use this if you intend to pass the pbuf to functions like udp_send().
-   */
-  PBUF_TRANSPORT,
-  /** Includes spare room for IP header.
-   * Use this if you intend to pass the pbuf to functions like raw_send().
-   */
-  PBUF_IP,
-  /** Includes spare room for link layer header (ethernet header).
-   * Use this if you intend to pass the pbuf to functions like ethernet_output().
-   * @see PBUF_LINK_HLEN
-   */
-  PBUF_LINK,
-  /** Includes spare room for additional encapsulation header before ethernet
-   * headers (e.g. 802.11).
-   * Use this if you intend to pass the pbuf to functions like netif->linkoutput().
-   * @see PBUF_LINK_ENCAPSULATION_HLEN
-   */
-  PBUF_RAW_TX,
-  /** Use this for input packets in a netif driver when calling netif->input()
-   * in the most common case - ethernet-layer netif driver. */
-  PBUF_RAW
-} pbuf_layer;
-
-/**
- * @ingroup pbuf
- * Enumeration of pbuf types
- */
-typedef enum {
-  /** pbuf data is stored in RAM, used for TX mostly, struct pbuf and its payload
-      are allocated in one piece of contiguous memory (so the first payload byte
-      can be calculated from struct pbuf).
-      pbuf_alloc() allocates PBUF_RAM pbufs as unchained pbufs (although that might
-      change in future versions).
-      This should be used for all OUTGOING packets (TX).*/
-  PBUF_RAM,
-  /** pbuf data is stored in ROM, i.e. struct pbuf and its payload are located in
-      totally different memory areas. Since it points to ROM, payload does not
-      have to be copied when queued for transmission. */
-  PBUF_ROM,
-  /** pbuf comes from the pbuf pool. Much like PBUF_ROM but payload might change
-      so it has to be duplicated when queued before transmitting, depending on
-      who has a 'ref' to it. */
-  PBUF_REF,
-  /** pbuf payload refers to RAM. This one comes from a pool and should be used
-      for RX. Payload can be chained (scatter-gather RX) but like PBUF_RAM, struct
-      pbuf and its payload are allocated in one piece of contiguous memory (so
-      the first payload byte can be calculated from struct pbuf).
-      Don't use this for TX, if the pool becomes empty e.g. because of TCP queuing,
-      you are unable to receive TCP acks! */
-  PBUF_POOL
-} pbuf_type;
-
-
-/** indicates this packet's data should be immediately passed to the application */
-#define PBUF_FLAG_PUSH      0x01U
-/** indicates this is a custom pbuf: pbuf_free calls pbuf_custom->custom_free_function()
-    when the last reference is released (plus custom PBUF_RAM cannot be trimmed) */
-#define PBUF_FLAG_IS_CUSTOM 0x02U
-/** indicates this pbuf is UDP multicast to be looped back */
-#define PBUF_FLAG_MCASTLOOP 0x04U
-/** indicates this pbuf was received as link-level broadcast */
-#define PBUF_FLAG_LLBCAST   0x08U
-/** indicates this pbuf was received as link-level multicast */
-#define PBUF_FLAG_LLMCAST   0x10U
-/** indicates this pbuf includes a TCP FIN flag */
-#define PBUF_FLAG_TCP_FIN   0x20U
-
-/** Main packet buffer struct */
-struct pbuf {
-  /** next pbuf in singly linked pbuf chain */
-  struct pbuf *next;
-
-  /** pointer to the actual data in the buffer */
-  void *payload;
-
-  /**
-   * total length of this buffer and all next buffers in chain
-   * belonging to the same packet.
-   *
-   * For non-queue packet chains this is the invariant:
-   * p->tot_len == p->len + (p->next? p->next->tot_len: 0)
-   */
-  u16_t tot_len;
-
-  /** length of this buffer */
-  u16_t len;
-
-  /** pbuf_type as u8_t instead of enum to save space */
-  u8_t /*pbuf_type*/ type;
-
-  /** misc flags */
-  u8_t flags;
-
-  /**
-   * the reference count always equals the number of pointers
-   * that refer to this pbuf. This can be pointers from an application,
-   * the stack itself, or pbuf->next pointers from a chain.
-   */
-  u16_t ref;
-
-#if ESP_LWIP
-  struct netif *l2_owner;
-  void *l2_buf;
-#endif
-};
-
-
-/** Helper struct for const-correctness only.
- * The only meaning of this one is to provide a const payload pointer
- * for PBUF_ROM type.
- */
-struct pbuf_rom {
-  /** next pbuf in singly linked pbuf chain */
-  struct pbuf *next;
-
-  /** pointer to the actual data in the buffer */
-  const void *payload;
-};
-
-#if LWIP_SUPPORT_CUSTOM_PBUF
-/** Prototype for a function to free a custom pbuf */
-typedef void (*pbuf_free_custom_fn)(struct pbuf *p);
-
-/** A custom pbuf: like a pbuf, but following a function pointer to free it. */
-struct pbuf_custom {
-  /** The actual pbuf */
-  struct pbuf pbuf;
-  /** This function is called when pbuf_free deallocates this pbuf(_custom) */
-  pbuf_free_custom_fn custom_free_function;
-};
-#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
-
-/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */
-#ifndef PBUF_POOL_FREE_OOSEQ
-#define PBUF_POOL_FREE_OOSEQ 1
-#endif /* PBUF_POOL_FREE_OOSEQ */
-#if LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ
-extern volatile u8_t pbuf_free_ooseq_pending;
-void pbuf_free_ooseq(void);
-/** When not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ()
-    at regular intervals from main level to check if ooseq pbufs need to be
-    freed! */
-#define PBUF_CHECK_FREE_OOSEQ() do { if(pbuf_free_ooseq_pending) { \
-  /* pbuf_alloc() reported PBUF_POOL to be empty -> try to free some \
-     ooseq queued pbufs now */ \
-  pbuf_free_ooseq(); }}while(0)
-#else /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ */
-  /* Otherwise declare an empty PBUF_CHECK_FREE_OOSEQ */
-  #define PBUF_CHECK_FREE_OOSEQ()
-#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ*/
-
-/* Initializes the pbuf module. This call is empty for now, but may not be in future. */
-#define pbuf_init()
-
-struct pbuf *pbuf_alloc(pbuf_layer l, u16_t length, pbuf_type type);
-#if LWIP_SUPPORT_CUSTOM_PBUF
-struct pbuf *pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type,
-                                 struct pbuf_custom *p, void *payload_mem,
-                                 u16_t payload_mem_len);
-#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
-void pbuf_realloc(struct pbuf *p, u16_t size);
-u8_t pbuf_header(struct pbuf *p, s16_t header_size);
-u8_t pbuf_header_force(struct pbuf *p, s16_t header_size);
-void pbuf_ref(struct pbuf *p);
-u8_t pbuf_free(struct pbuf *p);
-u16_t pbuf_clen(const struct pbuf *p);
-void pbuf_cat(struct pbuf *head, struct pbuf *tail);
-void pbuf_chain(struct pbuf *head, struct pbuf *tail);
-struct pbuf *pbuf_dechain(struct pbuf *p);
-err_t pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from);
-u16_t pbuf_copy_partial(const struct pbuf *p, void *dataptr, u16_t len, u16_t offset);
-err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len);
-err_t pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset);
-struct pbuf *pbuf_skip(struct pbuf* in, u16_t in_offset, u16_t* out_offset);
-struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer);
-#if LWIP_CHECKSUM_ON_COPY
-err_t pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr,
-                       u16_t len, u16_t *chksum);
-#endif /* LWIP_CHECKSUM_ON_COPY */
-#if LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
-void pbuf_split_64k(struct pbuf *p, struct pbuf **rest);
-#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
-
-u8_t pbuf_get_at(const struct pbuf* p, u16_t offset);
-int pbuf_try_get_at(const struct pbuf* p, u16_t offset);
-void pbuf_put_at(struct pbuf* p, u16_t offset, u8_t data);
-u16_t pbuf_memcmp(const struct pbuf* p, u16_t offset, const void* s2, u16_t n);
-u16_t pbuf_memfind(const struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset);
-u16_t pbuf_strstr(const struct pbuf* p, const char* substr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PBUF_H */
diff --git a/tools/sdk/include/lwip/lwip/priv/api_msg.h b/tools/sdk/include/lwip/lwip/priv/api_msg.h
deleted file mode 100644
index bcc0b5019af..00000000000
--- a/tools/sdk/include/lwip/lwip/priv/api_msg.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/**
- * @file
- * netconn API lwIP internal implementations (do not use in application code)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_API_MSG_H
-#define LWIP_HDR_API_MSG_H
-
-#include "lwip/opt.h"
-
-#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
-/* Note: Netconn API is always available when sockets are enabled -
- * sockets are implemented on top of them */
-
-#include "lwip/arch.h"
-#include "lwip/ip_addr.h"
-#include "lwip/err.h"
-#include "lwip/sys.h"
-#include "lwip/igmp.h"
-#include "lwip/api.h"
-#include "lwip/priv/tcpip_priv.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_MPU_COMPATIBLE
-#if LWIP_NETCONN_SEM_PER_THREAD
-#define API_MSG_M_DEF_SEM(m)  *m
-#else
-#define API_MSG_M_DEF_SEM(m)  API_MSG_M_DEF(m)
-#endif
-#else /* LWIP_MPU_COMPATIBLE */
-#define API_MSG_M_DEF_SEM(m)  API_MSG_M_DEF(m)
-#endif /* LWIP_MPU_COMPATIBLE */
-
-/* For the netconn API, these values are use as a bitmask! */
-#define NETCONN_SHUT_RD   1
-#define NETCONN_SHUT_WR   2
-#define NETCONN_SHUT_RDWR (NETCONN_SHUT_RD | NETCONN_SHUT_WR)
-
-/* IP addresses and port numbers are expected to be in
- * the same byte order as in the corresponding pcb.
- */
-/** This struct includes everything that is necessary to execute a function
-    for a netconn in another thread context (mainly used to process netconns
-    in the tcpip_thread context to be thread safe). */
-struct api_msg {
-  /** The netconn which to process - always needed: it includes the semaphore
-      which is used to block the application thread until the function finished. */
-  struct netconn *conn;
-  /** The return value of the function executed in tcpip_thread. */
-  err_t err;
-  /** Depending on the executed function, one of these union members is used */
-  union {
-    /** used for lwip_netconn_do_send */
-    struct netbuf *b;
-    /** used for lwip_netconn_do_newconn */
-    struct {
-      u8_t proto;
-    } n;
-    /** used for lwip_netconn_do_bind and lwip_netconn_do_connect */
-    struct {
-      API_MSG_M_DEF_C(ip_addr_t, ipaddr);
-      u16_t port;
-    } bc;
-    /** used for lwip_netconn_do_getaddr */
-    struct {
-      ip_addr_t API_MSG_M_DEF(ipaddr);
-      u16_t API_MSG_M_DEF(port);
-      u8_t local;
-    } ad;
-    /** used for lwip_netconn_do_write */
-    struct {
-      const void *dataptr;
-      size_t len;
-      u8_t apiflags;
-#if LWIP_SO_SNDTIMEO
-      u32_t time_started;
-#endif /* LWIP_SO_SNDTIMEO */
-    } w;
-    /** used for lwip_netconn_do_recv */
-    struct {
-      u32_t len;
-    } r;
-#if LWIP_TCP
-    /** used for lwip_netconn_do_close (/shutdown) */
-    struct {
-      u8_t shut;
-#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER
-      u32_t time_started;
-#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
-      u8_t polls_left;
-#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */
-    } sd;
-#endif /* LWIP_TCP */
-#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
-    /** used for lwip_netconn_do_join_leave_group */
-    struct {
-      API_MSG_M_DEF_C(ip_addr_t, multiaddr);
-      API_MSG_M_DEF_C(ip_addr_t, netif_addr);
-      enum netconn_igmp join_or_leave;
-    } jl;
-#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
-#if TCP_LISTEN_BACKLOG
-    struct {
-      u8_t backlog;
-    } lb;
-#endif /* TCP_LISTEN_BACKLOG */
-  } msg;
-#if LWIP_NETCONN_SEM_PER_THREAD
-  sys_sem_t* op_completed_sem;
-#endif /* LWIP_NETCONN_SEM_PER_THREAD */
-};
-
-#if LWIP_NETCONN_SEM_PER_THREAD
-#define LWIP_API_MSG_SEM(msg)          ((msg)->op_completed_sem)
-#else /* LWIP_NETCONN_SEM_PER_THREAD */
-#define LWIP_API_MSG_SEM(msg)          (&(msg)->conn->op_completed)
-#endif /* LWIP_NETCONN_SEM_PER_THREAD */
-
-
-#if LWIP_DNS
-/** As lwip_netconn_do_gethostbyname requires more arguments but doesn't require a netconn,
-    it has its own struct (to avoid struct api_msg getting bigger than necessary).
-    lwip_netconn_do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg
-    (see netconn_gethostbyname). */
-struct dns_api_msg {
-  /** Hostname to query or dotted IP address string */
-#if LWIP_MPU_COMPATIBLE
-  char name[DNS_MAX_NAME_LENGTH];
-#else /* LWIP_MPU_COMPATIBLE */
-  const char *name;
-#endif /* LWIP_MPU_COMPATIBLE */
-  /** The resolved address is stored here */
-  ip_addr_t API_MSG_M_DEF(addr);
-#if LWIP_IPV4 && LWIP_IPV6
-  /** Type of resolve call */
-  u8_t dns_addrtype;
-#endif /* LWIP_IPV4 && LWIP_IPV6 */
-  /** This semaphore is posted when the name is resolved, the application thread
-      should wait on it. */
-  sys_sem_t API_MSG_M_DEF_SEM(sem);
-  /** Errors are given back here */
-  err_t API_MSG_M_DEF(err);
-};
-#endif /* LWIP_DNS */
-
-#if LWIP_NETCONN_SEM_PER_THREAD
-#if ESP_THREAD_SAFE
-#define LWIP_NETCONN_THREAD_SEM_GET() sys_thread_sem_get()
-#define LWIP_NETCONN_THREAD_SEM_ALLOC() sys_thread_sem_init()
-#define LWIP_NETCONN_THREAD_SEM_FREE() sys_thread_sem_deinit()
-#endif
-#endif
-
-#if LWIP_TCP
-extern u8_t netconn_aborted;
-#endif /* LWIP_TCP */
-
-void lwip_netconn_do_newconn         (void *m);
-void lwip_netconn_do_delconn         (void *m);
-void lwip_netconn_do_bind            (void *m);
-void lwip_netconn_do_connect         (void *m);
-void lwip_netconn_do_disconnect      (void *m);
-void lwip_netconn_do_listen          (void *m);
-void lwip_netconn_do_send            (void *m);
-void lwip_netconn_do_recv            (void *m);
-#if TCP_LISTEN_BACKLOG
-void lwip_netconn_do_accepted        (void *m);
-#endif /* TCP_LISTEN_BACKLOG */
-void lwip_netconn_do_write           (void *m);
-void lwip_netconn_do_getaddr         (void *m);
-void lwip_netconn_do_close           (void *m);
-void lwip_netconn_do_shutdown        (void *m);
-#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD)
-void lwip_netconn_do_join_leave_group(void *m);
-#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */
-
-#if LWIP_DNS
-void lwip_netconn_do_gethostbyname(void *arg);
-#endif /* LWIP_DNS */
-
-struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback);
-void netconn_free(struct netconn *conn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_NETCONN || LWIP_SOCKET */
-
-#endif /* LWIP_HDR_API_MSG_H */
diff --git a/tools/sdk/include/lwip/lwip/priv/memp_priv.h b/tools/sdk/include/lwip/lwip/priv/memp_priv.h
deleted file mode 100644
index f246061dadf..00000000000
--- a/tools/sdk/include/lwip/lwip/priv/memp_priv.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/**
- * @file
- * memory pools lwIP internal implementations (do not use in application code)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-#ifndef LWIP_HDR_MEMP_PRIV_H
-#define LWIP_HDR_MEMP_PRIV_H
-
-#include "lwip/opt.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "lwip/mem.h"
-
-#if MEMP_OVERFLOW_CHECK
-/* if MEMP_OVERFLOW_CHECK is turned on, we reserve some bytes at the beginning
- * and at the end of each element, initialize them as 0xcd and check
- * them later. */
-/* If MEMP_OVERFLOW_CHECK is >= 2, on every call to memp_malloc or memp_free,
- * every single element in each pool is checked!
- * This is VERY SLOW but also very helpful. */
-/* MEMP_SANITY_REGION_BEFORE and MEMP_SANITY_REGION_AFTER can be overridden in
- * lwipopts.h to change the amount reserved for checking. */
-#ifndef MEMP_SANITY_REGION_BEFORE
-#define MEMP_SANITY_REGION_BEFORE  16
-#endif /* MEMP_SANITY_REGION_BEFORE*/
-#if MEMP_SANITY_REGION_BEFORE > 0
-#define MEMP_SANITY_REGION_BEFORE_ALIGNED    LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_BEFORE)
-#else
-#define MEMP_SANITY_REGION_BEFORE_ALIGNED    0
-#endif /* MEMP_SANITY_REGION_BEFORE*/
-#ifndef MEMP_SANITY_REGION_AFTER
-#define MEMP_SANITY_REGION_AFTER   16
-#endif /* MEMP_SANITY_REGION_AFTER*/
-#if MEMP_SANITY_REGION_AFTER > 0
-#define MEMP_SANITY_REGION_AFTER_ALIGNED     LWIP_MEM_ALIGN_SIZE(MEMP_SANITY_REGION_AFTER)
-#else
-#define MEMP_SANITY_REGION_AFTER_ALIGNED     0
-#endif /* MEMP_SANITY_REGION_AFTER*/
-
-/* MEMP_SIZE: save space for struct memp and for sanity check */
-#define MEMP_SIZE          (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEMP_SANITY_REGION_BEFORE_ALIGNED)
-#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEMP_SANITY_REGION_AFTER_ALIGNED)
-
-#else /* MEMP_OVERFLOW_CHECK */
-
-/* No sanity checks
- * We don't need to preserve the struct memp while not allocated, so we
- * can save a little space and set MEMP_SIZE to 0.
- */
-#define MEMP_SIZE           0
-#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x))
-
-#endif /* MEMP_OVERFLOW_CHECK */
-
-#if !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK
-struct memp {
-  struct memp *next;
-#if MEMP_OVERFLOW_CHECK
-  const char *file;
-  int line;
-#endif /* MEMP_OVERFLOW_CHECK */
-};
-#endif /* !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK */
-
-#if MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS
-/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */
-typedef enum {
-    /* Get the first (via:
-       MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/
-    MEMP_POOL_HELPER_FIRST = ((u8_t)
-#define LWIP_MEMPOOL(name,num,size,desc)
-#define LWIP_MALLOC_MEMPOOL_START 1
-#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0
-#define LWIP_MALLOC_MEMPOOL_END
-#include "lwip/priv/memp_std.h"
-    ) ,
-    /* Get the last (via:
-       MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */
-    MEMP_POOL_HELPER_LAST = ((u8_t)
-#define LWIP_MEMPOOL(name,num,size,desc)
-#define LWIP_MALLOC_MEMPOOL_START
-#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size *
-#define LWIP_MALLOC_MEMPOOL_END 1
-#include "lwip/priv/memp_std.h"
-    )
-} memp_pool_helper_t;
-
-/* The actual start and stop values are here (cast them over)
-   We use this helper type and these defines so we can avoid using const memp_t values */
-#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST)
-#define MEMP_POOL_LAST   ((memp_t) MEMP_POOL_HELPER_LAST)
-#endif /* MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS */
-
-/** Memory pool descriptor */
-struct memp_desc {
-#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY
-  /** Textual description */
-  const char *desc;
-#endif /* LWIP_DEBUG || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY */
-#if MEMP_STATS
-  /** Statistics */
-  struct stats_mem *stats;
-#endif
-
-  /** Element size */
-  u16_t size;
-
-#if !MEMP_MEM_MALLOC
-  /** Number of elements */
-  u16_t num;
-
-  /** Base address */
-  u8_t *base;
-
-  /** First free element of each pool. Elements form a linked list. */
-  struct memp **tab;
-#endif /* MEMP_MEM_MALLOC */
-};
-
-#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY
-#define DECLARE_LWIP_MEMPOOL_DESC(desc) (desc),
-#else
-#define DECLARE_LWIP_MEMPOOL_DESC(desc)
-#endif
-
-#if MEMP_STATS
-#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name) static struct stats_mem name;
-#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name) &name,
-#else
-#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name)
-#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name)
-#endif
-
-void memp_init_pool(const struct memp_desc *desc);
-
-#if MEMP_OVERFLOW_CHECK
-void *memp_malloc_pool_fn(const struct memp_desc* desc, const char* file, const int line);
-#define memp_malloc_pool(d) memp_malloc_pool_fn((d), __FILE__, __LINE__)
-#else
-void *memp_malloc_pool(const struct memp_desc *desc);
-#endif
-void  memp_free_pool(const struct memp_desc* desc, void *mem);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_MEMP_PRIV_H */
diff --git a/tools/sdk/include/lwip/lwip/priv/memp_std.h b/tools/sdk/include/lwip/lwip/priv/memp_std.h
deleted file mode 100644
index ce9fd500312..00000000000
--- a/tools/sdk/include/lwip/lwip/priv/memp_std.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/**
- * @file
- * lwIP internal memory pools (do not use in application code)
- * This file is deliberately included multiple times: once with empty
- * definition of LWIP_MEMPOOL() to handle all includes and multiple times
- * to build up various lists of mem pools.
- */
-
-/*
- * SETUP: Make sure we define everything we will need.
- *
- * We have create three types of pools:
- *   1) MEMPOOL - standard pools
- *   2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c
- *   3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct
- *
- * If the include'r doesn't require any special treatment of each of the types
- * above, then will declare #2 & #3 to be just standard mempools.
- */
-#ifndef LWIP_MALLOC_MEMPOOL
-/* This treats "malloc pools" just like any other pool.
-   The pools are a little bigger to provide 'size' as the amount of user data. */
-#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper))), "MALLOC_"#size)
-#define LWIP_MALLOC_MEMPOOL_START
-#define LWIP_MALLOC_MEMPOOL_END
-#endif /* LWIP_MALLOC_MEMPOOL */
-
-#ifndef LWIP_PBUF_MEMPOOL
-/* This treats "pbuf pools" just like any other pool.
- * Allocates buffers for a pbuf struct AND a payload size */
-#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (MEMP_ALIGN_SIZE(sizeof(struct pbuf)) + MEMP_ALIGN_SIZE(payload)), desc)
-#endif /* LWIP_PBUF_MEMPOOL */
-
-
-/*
- * A list of internal pools used by LWIP.
- *
- * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description)
- *     creates a pool name MEMP_pool_name. description is used in stats.c
- */
-#if LWIP_RAW
-LWIP_MEMPOOL(RAW_PCB,        MEMP_NUM_RAW_PCB,         sizeof(struct raw_pcb),        "RAW_PCB")
-#endif /* LWIP_RAW */
-
-#if LWIP_UDP
-LWIP_MEMPOOL(UDP_PCB,        MEMP_NUM_UDP_PCB,         sizeof(struct udp_pcb),        "UDP_PCB")
-#endif /* LWIP_UDP */
-
-#if LWIP_TCP
-LWIP_MEMPOOL(TCP_PCB,        MEMP_NUM_TCP_PCB,         sizeof(struct tcp_pcb),        "TCP_PCB")
-LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN,  sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN")
-LWIP_MEMPOOL(TCP_SEG,        MEMP_NUM_TCP_SEG,         sizeof(struct tcp_seg),        "TCP_SEG")
-#endif /* LWIP_TCP */
-
-#if LWIP_IPV4 && IP_REASSEMBLY
-LWIP_MEMPOOL(REASSDATA,      MEMP_NUM_REASSDATA,       sizeof(struct ip_reassdata),   "REASSDATA")
-#endif /* LWIP_IPV4 && IP_REASSEMBLY */
-#if (IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG)
-LWIP_MEMPOOL(FRAG_PBUF,      MEMP_NUM_FRAG_PBUF,       sizeof(struct pbuf_custom_ref),"FRAG_PBUF")
-#endif /* IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF || (LWIP_IPV6 && LWIP_IPV6_FRAG) */
-
-#if LWIP_NETCONN || LWIP_SOCKET
-LWIP_MEMPOOL(NETBUF,         MEMP_NUM_NETBUF,          sizeof(struct netbuf),         "NETBUF")
-LWIP_MEMPOOL(NETCONN,        MEMP_NUM_NETCONN,         sizeof(struct netconn),        "NETCONN")
-#endif /* LWIP_NETCONN || LWIP_SOCKET */
-
-#if NO_SYS==0
-LWIP_MEMPOOL(TCPIP_MSG_API,  MEMP_NUM_TCPIP_MSG_API,   sizeof(struct tcpip_msg),      "TCPIP_MSG_API")
-#if LWIP_MPU_COMPATIBLE
-LWIP_MEMPOOL(API_MSG,        MEMP_NUM_API_MSG,         sizeof(struct api_msg),        "API_MSG")
-#if LWIP_DNS
-LWIP_MEMPOOL(DNS_API_MSG,    MEMP_NUM_DNS_API_MSG,     sizeof(struct dns_api_msg),    "DNS_API_MSG")
-#endif
-#if LWIP_SOCKET && !LWIP_TCPIP_CORE_LOCKING
-LWIP_MEMPOOL(SOCKET_SETGETSOCKOPT_DATA, MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA, sizeof(struct lwip_setgetsockopt_data), "SOCKET_SETGETSOCKOPT_DATA")
-#endif
-#if LWIP_NETIF_API
-LWIP_MEMPOOL(NETIFAPI_MSG,   MEMP_NUM_NETIFAPI_MSG,    sizeof(struct netifapi_msg),   "NETIFAPI_MSG")
-#endif
-#endif /* LWIP_MPU_COMPATIBLE */
-#if !LWIP_TCPIP_CORE_LOCKING_INPUT
-LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg),      "TCPIP_MSG_INPKT")
-#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */
-#endif /* NO_SYS==0 */
-
-#if LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING
-LWIP_MEMPOOL(ARP_QUEUE,      MEMP_NUM_ARP_QUEUE,       sizeof(struct etharp_q_entry), "ARP_QUEUE")
-#endif /* LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING */
-
-#if LWIP_IGMP
-LWIP_MEMPOOL(IGMP_GROUP,     MEMP_NUM_IGMP_GROUP,      sizeof(struct igmp_group),     "IGMP_GROUP")
-#endif /* LWIP_IGMP */
-
-#if LWIP_TIMERS && !LWIP_TIMERS_CUSTOM
-LWIP_MEMPOOL(SYS_TIMEOUT,    MEMP_NUM_SYS_TIMEOUT,     sizeof(struct sys_timeo),      "SYS_TIMEOUT")
-#endif /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */
-
-#if LWIP_DNS && LWIP_SOCKET
-LWIP_MEMPOOL(NETDB,          MEMP_NUM_NETDB,           NETDB_ELEM_SIZE,               "NETDB")
-#endif /* LWIP_DNS && LWIP_SOCKET */
-#if LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC
-LWIP_MEMPOOL(LOCALHOSTLIST,  MEMP_NUM_LOCALHOSTLIST,   LOCALHOSTLIST_ELEM_SIZE,       "LOCALHOSTLIST")
-#endif /* LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
-
-#if LWIP_IPV6 && LWIP_ND6_QUEUEING
-LWIP_MEMPOOL(ND6_QUEUE,      MEMP_NUM_ND6_QUEUE,       sizeof(struct nd6_q_entry), "ND6_QUEUE")
-#endif /* LWIP_IPV6 && LWIP_ND6_QUEUEING */
-
-#if LWIP_IPV6 && LWIP_IPV6_REASS
-LWIP_MEMPOOL(IP6_REASSDATA,      MEMP_NUM_REASSDATA,       sizeof(struct ip6_reassdata),   "IP6_REASSDATA")
-#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */
-
-#if LWIP_IPV6 && LWIP_IPV6_MLD
-LWIP_MEMPOOL(MLD6_GROUP,     MEMP_NUM_MLD6_GROUP,      sizeof(struct mld_group),     "MLD6_GROUP")
-#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */
-
-
-/*
- * A list of pools of pbuf's used by LWIP.
- *
- * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description)
- *     creates a pool name MEMP_pool_name. description is used in stats.c
- *     This allocates enough space for the pbuf struct and a payload.
- *     (Example: pbuf_payload_size=0 allocates only size for the struct)
- */
-LWIP_PBUF_MEMPOOL(PBUF,      MEMP_NUM_PBUF,            0,                             "PBUF_REF/ROM")
-LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE,           PBUF_POOL_BUFSIZE,             "PBUF_POOL")
-
-
-/*
- * Allow for user-defined pools; this must be explicitly set in lwipopts.h
- * since the default is to NOT look for lwippools.h
- */
-#if MEMP_USE_CUSTOM_POOLS
-#include "lwippools.h"
-#endif /* MEMP_USE_CUSTOM_POOLS */
-
-/*
- * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later
- * (#undef is ignored for something that is not defined)
- */
-#undef LWIP_MEMPOOL
-#undef LWIP_MALLOC_MEMPOOL
-#undef LWIP_MALLOC_MEMPOOL_START
-#undef LWIP_MALLOC_MEMPOOL_END
-#undef LWIP_PBUF_MEMPOOL
diff --git a/tools/sdk/include/lwip/lwip/priv/nd6_priv.h b/tools/sdk/include/lwip/lwip/priv/nd6_priv.h
deleted file mode 100644
index 4bda0b793a3..00000000000
--- a/tools/sdk/include/lwip/lwip/priv/nd6_priv.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
- * @file
- *
- * Neighbor discovery and stateless address autoconfiguration for IPv6.
- * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862
- * (Address autoconfiguration).
- */
-
-/*
- * Copyright (c) 2010 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-
-#ifndef LWIP_HDR_ND6_PRIV_H
-#define LWIP_HDR_ND6_PRIV_H
-
-#include "lwip/opt.h"
-
-#if LWIP_IPV6  /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/pbuf.h"
-#include "lwip/ip6_addr.h"
-#include "lwip/netif.h"
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_ND6_QUEUEING
-/** struct for queueing outgoing packets for unknown address
-  * defined here to be accessed by memp.h
-  */
-struct nd6_q_entry {
-  struct nd6_q_entry *next;
-  struct pbuf *p;
-};
-#endif /* LWIP_ND6_QUEUEING */
-
-/** Struct for tables. */
-struct nd6_neighbor_cache_entry {
-  ip6_addr_t next_hop_address;
-  struct netif *netif;
-  u8_t lladdr[NETIF_MAX_HWADDR_LEN];
-  /*u32_t pmtu;*/
-#if LWIP_ND6_QUEUEING
-  /** Pointer to queue of pending outgoing packets on this entry. */
-  struct nd6_q_entry *q;
-#else /* LWIP_ND6_QUEUEING */
-  /** Pointer to a single pending outgoing packet on this entry. */
-  struct pbuf *q;
-#endif /* LWIP_ND6_QUEUEING */
-  u8_t state;
-  u8_t isrouter;
-  union {
-    u32_t reachable_time; /* in ms since value may originate from network packet */
-    u32_t delay_time;     /* ticks (ND6_TMR_INTERVAL) */
-    u32_t probes_sent;
-    u32_t stale_time;     /* ticks (ND6_TMR_INTERVAL) */
-  } counter;
-};
-
-struct nd6_destination_cache_entry {
-  ip6_addr_t destination_addr;
-  ip6_addr_t next_hop_addr;
-  u16_t pmtu;
-  u32_t age;
-};
-
-struct nd6_prefix_list_entry {
-  ip6_addr_t prefix;
-  struct netif *netif;
-  u32_t invalidation_timer; /* in ms since value may originate from network packet */
-#if LWIP_IPV6_AUTOCONFIG
-  u8_t flags;
-#define ND6_PREFIX_AUTOCONFIG_AUTONOMOUS 0x01
-#define ND6_PREFIX_AUTOCONFIG_ADDRESS_GENERATED 0x02
-#define ND6_PREFIX_AUTOCONFIG_ADDRESS_DUPLICATE 0x04
-#endif /* LWIP_IPV6_AUTOCONFIG */
-};
-
-struct nd6_router_list_entry {
-  struct nd6_neighbor_cache_entry *neighbor_entry;
-  u32_t invalidation_timer; /* in ms since value may originate from network packet */
-  u8_t flags;
-};
-
-enum nd6_neighbor_cache_entry_state {
-  ND6_NO_ENTRY = 0,
-  ND6_INCOMPLETE,
-  ND6_REACHABLE,
-  ND6_STALE,
-  ND6_DELAY,
-  ND6_PROBE
-};
-
-/* Router tables. */
-/* @todo make these static? and entries accessible through API? */
-extern struct nd6_neighbor_cache_entry neighbor_cache[];
-extern struct nd6_destination_cache_entry destination_cache[];
-extern struct nd6_prefix_list_entry prefix_list[];
-extern struct nd6_router_list_entry default_router_list[];
-
-/* Default values, can be updated by a RA message. */
-extern u32_t reachable_time;
-extern u32_t retrans_timer;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV6 */
-
-#endif /* LWIP_HDR_ND6_PRIV_H */
diff --git a/tools/sdk/include/lwip/lwip/priv/tcp_priv.h b/tools/sdk/include/lwip/lwip/priv/tcp_priv.h
deleted file mode 100644
index 73e8967e47d..00000000000
--- a/tools/sdk/include/lwip/lwip/priv/tcp_priv.h
+++ /dev/null
@@ -1,507 +0,0 @@
-/**
- * @file
- * TCP internal implementations (do not use in application code)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_TCP_PRIV_H
-#define LWIP_HDR_TCP_PRIV_H
-
-#include "lwip/opt.h"
-
-#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/tcp.h"
-#include "lwip/mem.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip.h"
-#include "lwip/icmp.h"
-#include "lwip/err.h"
-#include "lwip/ip6.h"
-#include "lwip/ip6_addr.h"
-#include "lwip/prot/tcp.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Functions for interfacing with TCP: */
-
-/* Lower layer interface to TCP: */
-void             tcp_init    (void);  /* Initialize this module. */
-void             tcp_tmr     (void);  /* Must be called every
-                                         TCP_TMR_INTERVAL
-                                         ms. (Typically 250 ms). */
-/* It is also possible to call these two functions at the right
-   intervals (instead of calling tcp_tmr()). */
-void             tcp_slowtmr (void);
-void             tcp_fasttmr (void);
-
-/* Call this from a netif driver (watch out for threading issues!) that has
-   returned a memory error on transmit and now has free buffers to send more.
-   This iterates all active pcbs that had an error and tries to call
-   tcp_output, so use this with care as it might slow down the system. */
-void             tcp_txnow   (void);
-
-/* Only used by IP to pass a TCP segment to TCP: */
-void             tcp_input   (struct pbuf *p, struct netif *inp);
-/* Used within the TCP code only: */
-struct tcp_pcb * tcp_alloc   (u8_t prio);
-void             tcp_abandon (struct tcp_pcb *pcb, int reset);
-err_t            tcp_send_empty_ack(struct tcp_pcb *pcb);
-void             tcp_rexmit  (struct tcp_pcb *pcb);
-void             tcp_rexmit_rto  (struct tcp_pcb *pcb);
-void             tcp_rexmit_fast (struct tcp_pcb *pcb);
-u32_t            tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb);
-err_t            tcp_process_refused_data(struct tcp_pcb *pcb);
-
-/**
- * This is the Nagle algorithm: try to combine user data to send as few TCP
- * segments as possible. Only send if
- * - no previously transmitted data on the connection remains unacknowledged or
- * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or
- * - the only unsent segment is at least pcb->mss bytes long (or there is more
- *   than one unsent segment - with lwIP, this can happen although unsent->len < mss)
- * - or if we are in fast-retransmit (TF_INFR)
- */
-#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \
-                            ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \
-                            (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \
-                              ((tpcb)->unsent->len >= (tpcb)->mss))) || \
-                            ((tcp_sndbuf(tpcb) == 0) || (tcp_sndqueuelen(tpcb) >= TCP_SND_QUEUELEN)) \
-                            ) ? 1 : 0)
-#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK)
-
-
-#define TCP_SEQ_LT(a,b)     ((s32_t)((u32_t)(a) - (u32_t)(b)) < 0)
-#define TCP_SEQ_LEQ(a,b)    ((s32_t)((u32_t)(a) - (u32_t)(b)) <= 0)
-#define TCP_SEQ_GT(a,b)     ((s32_t)((u32_t)(a) - (u32_t)(b)) > 0)
-#define TCP_SEQ_GEQ(a,b)    ((s32_t)((u32_t)(a) - (u32_t)(b)) >= 0)
-/* is b<=a<=c? */
-#if 0 /* see bug #10548 */
-#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b))
-#endif
-#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c))
-
-#ifndef TCP_TMR_INTERVAL
-#define TCP_TMR_INTERVAL       250  /* The TCP timer interval in milliseconds. */
-#endif /* TCP_TMR_INTERVAL */
-
-#ifndef TCP_FAST_INTERVAL
-#define TCP_FAST_INTERVAL      TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */
-#endif /* TCP_FAST_INTERVAL */
-
-#ifndef TCP_SLOW_INTERVAL
-#define TCP_SLOW_INTERVAL      (2*TCP_TMR_INTERVAL)  /* the coarse grained timeout in milliseconds */
-#endif /* TCP_SLOW_INTERVAL */
-
-#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */
-#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */
-
-#define TCP_OOSEQ_TIMEOUT        6U /* x RTO */
-
-#ifndef TCP_MSL
-#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */
-#endif
-
-/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */
-#ifndef  TCP_KEEPIDLE_DEFAULT
-#define  TCP_KEEPIDLE_DEFAULT     7200000UL /* Default KEEPALIVE timer in milliseconds */
-#endif
-
-#ifndef  TCP_KEEPINTVL_DEFAULT
-#define  TCP_KEEPINTVL_DEFAULT    75000UL   /* Default Time between KEEPALIVE probes in milliseconds */
-#endif
-
-#ifndef  TCP_KEEPCNT_DEFAULT
-#define  TCP_KEEPCNT_DEFAULT      9U        /* Default Counter for KEEPALIVE probes */
-#endif
-
-#define  TCP_MAXIDLE              TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT  /* Maximum KEEPALIVE probe time */
-
-#define TCP_TCPLEN(seg) ((seg)->len + (((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0) ? 1U : 0U))
-
-/** Flags used on input processing, not on pcb->flags
-*/
-#define TF_RESET     (u8_t)0x08U   /* Connection was reset. */
-#define TF_CLOSED    (u8_t)0x10U   /* Connection was successfully closed. */
-#define TF_GOT_FIN   (u8_t)0x20U   /* Connection was closed by the remote end. */
-
-
-#if LWIP_EVENT_API
-
-#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret) ret = lwip_tcp_event(arg, (pcb),\
-                LWIP_EVENT_ACCEPT, NULL, 0, err)
-#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                   LWIP_EVENT_SENT, NULL, space, ERR_OK)
-#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_RECV, (p), 0, (err))
-#define TCP_EVENT_CLOSED(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_RECV, NULL, 0, ERR_OK)
-#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\
-                LWIP_EVENT_CONNECTED, NULL, 0, (err))
-#define TCP_EVENT_POLL(pcb,ret)       do { if ((pcb)->state != SYN_RCVD) {                          \
-                ret = lwip_tcp_event((pcb)->callback_arg, (pcb), LWIP_EVENT_POLL, NULL, 0, ERR_OK); \
-                } else {                                                                            \
-                ret = ERR_ARG; } } while(0)
-#define TCP_EVENT_ERR(last_state,errf,arg,err)  do { if (last_state != SYN_RCVD) {                \
-                lwip_tcp_event((arg), NULL, LWIP_EVENT_ERR, NULL, 0, (err)); } } while(0)
-
-#else /* LWIP_EVENT_API */
-
-#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret)                 \
-  do {                                                         \
-    if((lpcb)->accept != NULL)                                 \
-      (ret) = (lpcb)->accept((arg),(pcb),(err));               \
-    else (ret) = ERR_ARG;                                      \
-  } while (0)
-
-#define TCP_EVENT_SENT(pcb,space,ret)                          \
-  do {                                                         \
-    if((pcb)->sent != NULL)                                    \
-      (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space));  \
-    else (ret) = ERR_OK;                                       \
-  } while (0)
-
-#define TCP_EVENT_RECV(pcb,p,err,ret)                          \
-  do {                                                         \
-    if((pcb)->recv != NULL) {                                  \
-      (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err));\
-    } else {                                                   \
-      (ret) = tcp_recv_null(NULL, (pcb), (p), (err));          \
-    }                                                          \
-  } while (0)
-
-#define TCP_EVENT_CLOSED(pcb,ret)                                \
-  do {                                                           \
-    if(((pcb)->recv != NULL)) {                                  \
-      (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),NULL,ERR_OK);\
-    } else {                                                     \
-      (ret) = ERR_OK;                                            \
-    }                                                            \
-  } while (0)
-
-#define TCP_EVENT_CONNECTED(pcb,err,ret)                         \
-  do {                                                           \
-    if((pcb)->connected != NULL)                                 \
-      (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \
-    else (ret) = ERR_OK;                                         \
-  } while (0)
-
-#define TCP_EVENT_POLL(pcb,ret)                                \
-  do {                                                         \
-    if((pcb)->poll != NULL)                                    \
-      (ret) = (pcb)->poll((pcb)->callback_arg,(pcb));          \
-    else (ret) = ERR_OK;                                       \
-  } while (0)
-
-#define TCP_EVENT_ERR(last_state,errf,arg,err)                 \
-  do {                                                         \
-    LWIP_UNUSED_ARG(last_state);                               \
-    if((errf) != NULL)                                         \
-      (errf)((arg),(err));                                     \
-  } while (0)
-
-#endif /* LWIP_EVENT_API */
-
-/** Enabled extra-check for TCP_OVERSIZE if LWIP_DEBUG is enabled */
-#if TCP_OVERSIZE && defined(LWIP_DEBUG)
-#define TCP_OVERSIZE_DBGCHECK 1
-#else
-#define TCP_OVERSIZE_DBGCHECK 0
-#endif
-
-/** Don't generate checksum on copy if CHECKSUM_GEN_TCP is disabled */
-#define TCP_CHECKSUM_ON_COPY  (LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_TCP)
-
-/* This structure represents a TCP segment on the unsent, unacked and ooseq queues */
-struct tcp_seg {
-  struct tcp_seg *next;    /* used when putting segments on a queue */
-  struct pbuf *p;          /* buffer containing data + TCP header */
-  u16_t len;               /* the TCP length of this segment */
-#if TCP_OVERSIZE_DBGCHECK
-  u16_t oversize_left;     /* Extra bytes available at the end of the last
-                              pbuf in unsent (used for asserting vs.
-                              tcp_pcb.unsent_oversize only) */
-#endif /* TCP_OVERSIZE_DBGCHECK */
-#if TCP_CHECKSUM_ON_COPY
-  u16_t chksum;
-  u8_t  chksum_swapped;
-#endif /* TCP_CHECKSUM_ON_COPY */
-  u8_t  flags;
-#define TF_SEG_OPTS_MSS         (u8_t)0x01U /* Include MSS option. */
-#define TF_SEG_OPTS_TS          (u8_t)0x02U /* Include timestamp option. */
-#define TF_SEG_DATA_CHECKSUMMED (u8_t)0x04U /* ALL data (not the header) is
-                                               checksummed into 'chksum' */
-#define TF_SEG_OPTS_WND_SCALE   (u8_t)0x08U /* Include WND SCALE option */
-  struct tcp_hdr *tcphdr;  /* the TCP header */
-};
-
-#define LWIP_TCP_OPT_EOL        0
-#define LWIP_TCP_OPT_NOP        1
-#define LWIP_TCP_OPT_MSS        2
-#define LWIP_TCP_OPT_WS         3
-#define LWIP_TCP_OPT_TS         8
-
-#define LWIP_TCP_OPT_LEN_MSS    4
-#if LWIP_TCP_TIMESTAMPS
-#define LWIP_TCP_OPT_LEN_TS     10
-#define LWIP_TCP_OPT_LEN_TS_OUT 12 /* aligned for output (includes NOP padding) */
-#else
-#define LWIP_TCP_OPT_LEN_TS_OUT 0
-#endif
-#if LWIP_WND_SCALE
-#define LWIP_TCP_OPT_LEN_WS     3
-#define LWIP_TCP_OPT_LEN_WS_OUT 4 /* aligned for output (includes NOP padding) */
-#else
-#define LWIP_TCP_OPT_LEN_WS_OUT 0
-#endif
-
-#define LWIP_TCP_OPT_LENGTH(flags) \
-  (flags & TF_SEG_OPTS_MSS       ? LWIP_TCP_OPT_LEN_MSS    : 0) + \
-  (flags & TF_SEG_OPTS_TS        ? LWIP_TCP_OPT_LEN_TS_OUT : 0) + \
-  (flags & TF_SEG_OPTS_WND_SCALE ? LWIP_TCP_OPT_LEN_WS_OUT : 0)
-
-/** This returns a TCP header option for MSS in an u32_t */
-#define TCP_BUILD_MSS_OPTION(mss) lwip_htonl(0x02040000 | ((mss) & 0xFFFF))
-
-#if LWIP_WND_SCALE
-#define TCPWNDSIZE_F       U32_F
-#define TCPWND_MAX         0xFFFFFFFFU
-#define TCPWND_CHECK16(x)  LWIP_ASSERT("window size > 0xFFFF", (x) <= 0xFFFF)
-#define TCPWND_MIN16(x)    ((u16_t)LWIP_MIN((x), 0xFFFF))
-#else /* LWIP_WND_SCALE */
-#define TCPWNDSIZE_F       U16_F
-#define TCPWND_MAX         0xFFFFU
-#define TCPWND_CHECK16(x)
-#define TCPWND_MIN16(x)    x
-#endif /* LWIP_WND_SCALE */
-
-/* Global variables: */
-extern struct tcp_pcb *tcp_input_pcb;
-extern u32_t tcp_ticks;
-extern u8_t tcp_active_pcbs_changed;
-
-/* The TCP PCB lists. */
-union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */
-  struct tcp_pcb_listen *listen_pcbs;
-  struct tcp_pcb *pcbs;
-};
-extern struct tcp_pcb *tcp_bound_pcbs;
-extern union tcp_listen_pcbs_t tcp_listen_pcbs;
-extern struct tcp_pcb *tcp_active_pcbs;  /* List of all TCP PCBs that are in a
-              state in which they accept or send
-              data. */
-extern struct tcp_pcb *tcp_tw_pcbs;      /* List of all TCP PCBs in TIME-WAIT. */
-
-#define NUM_TCP_PCB_LISTS_NO_TIME_WAIT  3
-#define NUM_TCP_PCB_LISTS               4
-extern struct tcp_pcb ** const tcp_pcb_lists[NUM_TCP_PCB_LISTS];
-
-/* Axioms about the above lists:
-   1) Every TCP PCB that is not CLOSED is in one of the lists.
-   2) A PCB is only in one of the lists.
-   3) All PCBs in the tcp_listen_pcbs list is in LISTEN state.
-   4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state.
-*/
-/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB
-   with a PCB list or removes a PCB from a list, respectively. */
-#ifndef TCP_DEBUG_PCB_LISTS
-#define TCP_DEBUG_PCB_LISTS 0
-#endif
-#if TCP_DEBUG_PCB_LISTS
-#define TCP_REG(pcbs, npcb) do {\
-                            struct tcp_pcb *tcp_tmp_pcb; \
-                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", (npcb), (npcb)->local_port)); \
-                            for (tcp_tmp_pcb = *(pcbs); \
-          tcp_tmp_pcb != NULL; \
-        tcp_tmp_pcb = tcp_tmp_pcb->next) { \
-                                LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != (npcb)); \
-                            } \
-                            LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", ((pcbs) == &tcp_bound_pcbs) || ((npcb)->state != CLOSED)); \
-                            (npcb)->next = *(pcbs); \
-                            LWIP_ASSERT("TCP_REG: npcb->next != npcb", (npcb)->next != (npcb)); \
-                            *(pcbs) = (npcb); \
-                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
-              tcp_timer_needed(); \
-                            } while(0)
-#define TCP_RMV(pcbs, npcb) do { \
-                            struct tcp_pcb *tcp_tmp_pcb; \
-                            LWIP_ASSERT("TCP_RMV: pcbs != NULL", *(pcbs) != NULL); \
-                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", (npcb), *(pcbs))); \
-                            if(*(pcbs) == (npcb)) { \
-                               *(pcbs) = (*pcbs)->next; \
-                            } else for (tcp_tmp_pcb = *(pcbs); tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \
-                               if(tcp_tmp_pcb->next == (npcb)) { \
-                                  tcp_tmp_pcb->next = (npcb)->next; \
-                                  break; \
-                               } \
-                            } \
-                            (npcb)->next = NULL; \
-                            LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \
-                            LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", (npcb), *(pcbs))); \
-                            } while(0)
-
-#else /* LWIP_DEBUG */
-
-#define TCP_REG(pcbs, npcb)                        \
-  do {                                             \
-    (npcb)->next = *pcbs;                          \
-    *(pcbs) = (npcb);                              \
-    tcp_timer_needed();                            \
-  } while (0)
-
-#define TCP_RMV(pcbs, npcb)                        \
-  do {                                             \
-    if(*(pcbs) == (npcb)) {                        \
-      (*(pcbs)) = (*pcbs)->next;                   \
-    }                                              \
-    else {                                         \
-      struct tcp_pcb *tcp_tmp_pcb;                 \
-      for (tcp_tmp_pcb = *pcbs;                    \
-          tcp_tmp_pcb != NULL;                     \
-          tcp_tmp_pcb = tcp_tmp_pcb->next) {       \
-        if(tcp_tmp_pcb->next == (npcb)) {          \
-          tcp_tmp_pcb->next = (npcb)->next;        \
-          break;                                   \
-        }                                          \
-      }                                            \
-    }                                              \
-    (npcb)->next = NULL;                           \
-  } while(0)
-
-#endif /* LWIP_DEBUG */
-
-#define TCP_REG_ACTIVE(npcb)                       \
-  do {                                             \
-    TCP_REG(&tcp_active_pcbs, npcb);               \
-    tcp_active_pcbs_changed = 1;                   \
-  } while (0)
-
-#define TCP_RMV_ACTIVE(npcb)                       \
-  do {                                             \
-    TCP_RMV(&tcp_active_pcbs, npcb);               \
-    tcp_active_pcbs_changed = 1;                   \
-  } while (0)
-
-#define TCP_PCB_REMOVE_ACTIVE(pcb)                 \
-  do {                                             \
-    tcp_pcb_remove(&tcp_active_pcbs, pcb);         \
-    tcp_active_pcbs_changed = 1;                   \
-  } while (0)
-
-
-/* Internal functions: */
-struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb);
-void tcp_pcb_purge(struct tcp_pcb *pcb);
-void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb);
-
-void tcp_segs_free(struct tcp_seg *seg);
-void tcp_seg_free(struct tcp_seg *seg);
-struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg);
-
-#define tcp_ack(pcb)                               \
-  do {                                             \
-    if((pcb)->flags & TF_ACK_DELAY) {              \
-      (pcb)->flags &= ~TF_ACK_DELAY;               \
-      (pcb)->flags |= TF_ACK_NOW;                  \
-    }                                              \
-    else {                                         \
-      (pcb)->flags |= TF_ACK_DELAY;                \
-    }                                              \
-  } while (0)
-
-#define tcp_ack_now(pcb)                           \
-  do {                                             \
-    (pcb)->flags |= TF_ACK_NOW;                    \
-  } while (0)
-
-err_t tcp_send_fin(struct tcp_pcb *pcb);
-err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags);
-
-void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg);
-
-void tcp_rst(u32_t seqno, u32_t ackno,
-       const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
-       u16_t local_port, u16_t remote_port);
-
-u32_t tcp_next_iss(struct tcp_pcb *pcb);
-
-err_t tcp_keepalive(struct tcp_pcb *pcb);
-err_t tcp_zero_window_probe(struct tcp_pcb *pcb);
-void  tcp_trigger_input_pcb_close(void);
-
-#if TCP_CALCULATE_EFF_SEND_MSS
-u16_t tcp_eff_send_mss_impl(u16_t sendmss, const ip_addr_t *dest
-#if LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING
-                           , const ip_addr_t *src
-#endif /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */
-                           );
-#if LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING
-#define tcp_eff_send_mss(sendmss, src, dest) tcp_eff_send_mss_impl(sendmss, dest, src)
-#else /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */
-#define tcp_eff_send_mss(sendmss, src, dest) tcp_eff_send_mss_impl(sendmss, dest)
-#endif /* LWIP_IPV6 || LWIP_IPV4_SRC_ROUTING */
-#endif /* TCP_CALCULATE_EFF_SEND_MSS */
-
-#if LWIP_CALLBACK_API
-err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
-#endif /* LWIP_CALLBACK_API */
-
-#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG
-void tcp_debug_print(struct tcp_hdr *tcphdr);
-void tcp_debug_print_flags(u8_t flags);
-void tcp_debug_print_state(enum tcp_state s);
-void tcp_debug_print_pcbs(void);
-s16_t tcp_pcbs_sane(void);
-#else
-#  define tcp_debug_print(tcphdr)
-#  define tcp_debug_print_flags(flags)
-#  define tcp_debug_print_state(s)
-#  define tcp_debug_print_pcbs()
-#  define tcp_pcbs_sane() 1
-#endif /* TCP_DEBUG */
-
-/** External function (implemented in timers.c), called when TCP detects
- * that a timer is needed (i.e. active- or time-wait-pcb found). */
-void tcp_timer_needed(void);
-
-void tcp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_TCP */
-
-#endif /* LWIP_HDR_TCP_PRIV_H */
diff --git a/tools/sdk/include/lwip/lwip/priv/tcpip_priv.h b/tools/sdk/include/lwip/lwip/priv/tcpip_priv.h
deleted file mode 100644
index 630efb14022..00000000000
--- a/tools/sdk/include/lwip/lwip/priv/tcpip_priv.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/**
- * @file
- * TCPIP API internal implementations (do not use in application code)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_TCPIP_PRIV_H
-#define LWIP_HDR_TCPIP_PRIV_H
-
-#include "lwip/opt.h"
-
-#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/tcpip.h"
-#include "lwip/sys.h"
-#include "lwip/timeouts.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct pbuf;
-struct netif;
-
-#if LWIP_MPU_COMPATIBLE
-#define API_VAR_REF(name)               (*(name))
-#define API_VAR_DECLARE(type, name)     type * name
-#define API_VAR_ALLOC(type, pool, name, errorval) do { \
-                                          name = (type *)memp_malloc(pool); \
-                                          if (name == NULL) { \
-                                            return errorval; \
-                                          } \
-                                        } while(0)
-#define API_VAR_ALLOC_POOL(type, pool, name, errorval) do { \
-                                          name = (type *)LWIP_MEMPOOL_ALLOC(pool); \
-                                          if (name == NULL) { \
-                                            return errorval; \
-                                          } \
-                                        } while(0)
-#define API_VAR_FREE(pool, name)        memp_free(pool, name)
-#define API_VAR_FREE_POOL(pool, name)   LWIP_MEMPOOL_FREE(pool, name)
-#define API_EXPR_REF(expr)              (&(expr))
-#if LWIP_NETCONN_SEM_PER_THREAD
-#define API_EXPR_REF_SEM(expr)          (expr)
-#else
-#define API_EXPR_REF_SEM(expr)          API_EXPR_REF(expr)
-#endif
-#define API_EXPR_DEREF(expr)            expr
-#define API_MSG_M_DEF(m)                m
-#define API_MSG_M_DEF_C(t, m)           t m
-#else /* LWIP_MPU_COMPATIBLE */
-#define API_VAR_REF(name)               name
-#define API_VAR_DECLARE(type, name)     type name
-#define API_VAR_ALLOC(type, pool, name, errorval)
-#define API_VAR_ALLOC_POOL(type, pool, name, errorval)
-#define API_VAR_FREE(pool, name)
-#define API_VAR_FREE_POOL(pool, name)
-#define API_EXPR_REF(expr)              expr
-#define API_EXPR_REF_SEM(expr)          API_EXPR_REF(expr)
-#define API_EXPR_DEREF(expr)            (*(expr))
-#define API_MSG_M_DEF(m)                *m
-#define API_MSG_M_DEF_C(t, m)           const t * m
-#endif /* LWIP_MPU_COMPATIBLE */
-
-err_t tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t* sem);
-
-struct tcpip_api_call_data
-{
-#if !LWIP_TCPIP_CORE_LOCKING
-  err_t err;
-#if !LWIP_NETCONN_SEM_PER_THREAD
-  sys_sem_t sem;
-#endif /* LWIP_NETCONN_SEM_PER_THREAD */
-#else /* !LWIP_TCPIP_CORE_LOCKING */
-  u8_t dummy; /* avoid empty struct :-( */
-#endif /* !LWIP_TCPIP_CORE_LOCKING */
-};
-typedef err_t (*tcpip_api_call_fn)(struct tcpip_api_call_data* call);
-err_t tcpip_api_call(tcpip_api_call_fn fn, struct tcpip_api_call_data *call);
-
-enum tcpip_msg_type {
-  TCPIP_MSG_API,
-  TCPIP_MSG_API_CALL,
-  TCPIP_MSG_INPKT,
-#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
-  TCPIP_MSG_TIMEOUT,
-  TCPIP_MSG_UNTIMEOUT,
-#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
-  TCPIP_MSG_CALLBACK,
-  TCPIP_MSG_CALLBACK_STATIC
-};
-
-struct tcpip_msg {
-  enum tcpip_msg_type type;
-  union {
-    struct {
-      tcpip_callback_fn function;
-      void* msg;
-    } api_msg;
-    struct {
-      tcpip_api_call_fn function;
-      struct tcpip_api_call_data *arg;
-      sys_sem_t *sem;
-    } api_call;
-    struct {
-      struct pbuf *p;
-      struct netif *netif;
-      netif_input_fn input_fn;
-    } inp;
-    struct {
-      tcpip_callback_fn function;
-      void *ctx;
-    } cb;
-#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
-    struct {
-      u32_t msecs;
-      sys_timeout_handler h;
-      void *arg;
-    } tmo;
-#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
-  } msg;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !NO_SYS */
-
-#endif /* LWIP_HDR_TCPIP_PRIV_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/autoip.h b/tools/sdk/include/lwip/lwip/prot/autoip.h
deleted file mode 100644
index 96f93f57809..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/autoip.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
- * @file
- * AutoIP protocol definitions
- */
-
-/*
- *
- * Copyright (c) 2007 Dominik Spies <kontakt@dspies.de>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: Dominik Spies <kontakt@dspies.de>
- *
- * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
- * with RFC 3927.
- *
- */
-
-#ifndef LWIP_HDR_PROT_AUTOIP_H
-#define LWIP_HDR_PROT_AUTOIP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* 169.254.0.0 */
-#define AUTOIP_NET              0xA9FE0000
-/* 169.254.1.0 */
-#define AUTOIP_RANGE_START      (AUTOIP_NET | 0x0100)
-/* 169.254.254.255 */
-#define AUTOIP_RANGE_END        (AUTOIP_NET | 0xFEFF)
-
-/* RFC 3927 Constants */
-#define PROBE_WAIT              1   /* second   (initial random delay)                 */
-#define PROBE_MIN               1   /* second   (minimum delay till repeated probe)    */
-#define PROBE_MAX               2   /* seconds  (maximum delay till repeated probe)    */
-#define PROBE_NUM               3   /*          (number of probe packets)              */
-#define ANNOUNCE_NUM            2   /*          (number of announcement packets)       */
-#define ANNOUNCE_INTERVAL       2   /* seconds  (time between announcement packets)    */
-#define ANNOUNCE_WAIT           2   /* seconds  (delay before announcing)              */
-#if ESP_LWIP
-#define MAX_CONFLICTS           LWIP_AUTOIP_MAX_CONFLICTS        /*          (max conflicts before rate limiting) */
-#define RATE_LIMIT_INTERVAL     LWIP_AUTOIP_RATE_LIMIT_INTERVAL  /* seconds  (delay between successive attempts) */
-#else
-#define MAX_CONFLICTS           10  /*          (max conflicts before rate limiting)   */
-#define RATE_LIMIT_INTERVAL     60  /* seconds  (delay between successive attempts)    */
-#endif
-#define DEFEND_INTERVAL         10  /* seconds  (min. wait between defensive ARPs)     */
-
-/* AutoIP client states */
-typedef enum {
-  AUTOIP_STATE_OFF        = 0,
-  AUTOIP_STATE_PROBING    = 1,
-  AUTOIP_STATE_ANNOUNCING = 2,
-  AUTOIP_STATE_BOUND      = 3
-} autoip_state_enum_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_AUTOIP_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/dhcp.h b/tools/sdk/include/lwip/lwip/prot/dhcp.h
deleted file mode 100644
index 036a33a895d..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/dhcp.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/**
- * @file
- * DHCP protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Leon Woestenberg <leon.woestenberg@gmx.net>
- * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Leon Woestenberg <leon.woestenberg@gmx.net>
- *
- */
-#ifndef LWIP_HDR_PROT_DHCP_H
-#define LWIP_HDR_PROT_DHCP_H
-
-#include "lwip/opt.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DHCP_CLIENT_PORT  68
-#define DHCP_SERVER_PORT  67
-
-
- /* DHCP message item offsets and length */
-#define DHCP_CHADDR_LEN   16U
-#define DHCP_SNAME_OFS    44U
-#define DHCP_SNAME_LEN    64U
-#define DHCP_FILE_OFS     108U
-#define DHCP_FILE_LEN     128U
-#define DHCP_MSG_LEN      236U
-#define DHCP_OPTIONS_OFS  (DHCP_MSG_LEN + 4U) /* 4 byte: cookie */
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/** minimum set of fields of any DHCP message */
-struct dhcp_msg
-{
-  PACK_STRUCT_FLD_8(u8_t op);
-  PACK_STRUCT_FLD_8(u8_t htype);
-  PACK_STRUCT_FLD_8(u8_t hlen);
-  PACK_STRUCT_FLD_8(u8_t hops);
-  PACK_STRUCT_FIELD(u32_t xid);
-  PACK_STRUCT_FIELD(u16_t secs);
-  PACK_STRUCT_FIELD(u16_t flags);
-  PACK_STRUCT_FLD_S(ip4_addr_p_t ciaddr);
-  PACK_STRUCT_FLD_S(ip4_addr_p_t yiaddr);
-  PACK_STRUCT_FLD_S(ip4_addr_p_t siaddr);
-  PACK_STRUCT_FLD_S(ip4_addr_p_t giaddr);
-  PACK_STRUCT_FLD_8(u8_t chaddr[DHCP_CHADDR_LEN]);
-  PACK_STRUCT_FLD_8(u8_t sname[DHCP_SNAME_LEN]);
-  PACK_STRUCT_FLD_8(u8_t file[DHCP_FILE_LEN]);
-  PACK_STRUCT_FIELD(u32_t cookie);
-#define DHCP_MIN_OPTIONS_LEN 68U
-/** make sure user does not configure this too small */
-#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN))
-#  undef DHCP_OPTIONS_LEN
-#endif
-/** allow this to be configured in lwipopts.h, but not too small */
-#if (!defined(DHCP_OPTIONS_LEN))
-/** set this to be sufficient for your options in outgoing DHCP msgs */
-#  define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN
-#endif
-  PACK_STRUCT_FLD_8(u8_t options[DHCP_OPTIONS_LEN]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-
-/* DHCP client states */
-typedef enum {
-  DHCP_STATE_OFF             = 0,
-  DHCP_STATE_REQUESTING      = 1,
-  DHCP_STATE_INIT            = 2,
-  DHCP_STATE_REBOOTING       = 3,
-  DHCP_STATE_REBINDING       = 4,
-  DHCP_STATE_RENEWING        = 5,
-  DHCP_STATE_SELECTING       = 6,
-  DHCP_STATE_INFORMING       = 7,
-  DHCP_STATE_CHECKING        = 8,
-  DHCP_STATE_PERMANENT       = 9,  /* not yet implemented */
-  DHCP_STATE_BOUND           = 10,
-  DHCP_STATE_RELEASING       = 11, /* not yet implemented */
-  DHCP_STATE_BACKING_OFF     = 12
-} dhcp_state_enum_t;
-
-/* DHCP op codes */
-#define DHCP_BOOTREQUEST            1
-#define DHCP_BOOTREPLY              2
-
-/* DHCP message types */
-#define DHCP_DISCOVER               1
-#define DHCP_OFFER                  2
-#define DHCP_REQUEST                3
-#define DHCP_DECLINE                4
-#define DHCP_ACK                    5
-#define DHCP_NAK                    6
-#define DHCP_RELEASE                7
-#define DHCP_INFORM                 8
-
-/** DHCP hardware type, currently only ethernet is supported */
-#define DHCP_HTYPE_ETH              1
-
-#define DHCP_MAGIC_COOKIE           0x63825363UL
-
-/* This is a list of options for BOOTP and DHCP, see RFC 2132 for descriptions */
-
-/* BootP options */
-#define DHCP_OPTION_PAD             0
-#define DHCP_OPTION_SUBNET_MASK     1 /* RFC 2132 3.3 */
-#define DHCP_OPTION_ROUTER          3
-#define DHCP_OPTION_DNS_SERVER      6
-#define DHCP_OPTION_HOSTNAME        12
-#define DHCP_OPTION_IP_TTL          23
-#define DHCP_OPTION_MTU             26
-#define DHCP_OPTION_BROADCAST       28
-#define DHCP_OPTION_TCP_TTL         37
-#define DHCP_OPTION_NTP             42
-#define DHCP_OPTION_END             255
-
-#if ESP_LWIP
-/**add options for support more router by liuHan**/
-#define DHCP_OPTION_DOMAIN_NAME     15
-#define DHCP_OPTION_PRD             31
-#define DHCP_OPTION_STATIC_ROUTER   33
-#define DHCP_OPTION_VSN             43
-#define DHCP_OPTION_NB_TINS         44
-#define DHCP_OPTION_NB_TINT         46
-#define DHCP_OPTION_NB_TIS          47
-#define DHCP_OPTION_CLASSLESS_STATIC_ROUTER 121
-#endif
-
-/* DHCP options */
-#define DHCP_OPTION_REQUESTED_IP    50 /* RFC 2132 9.1, requested IP address */
-#define DHCP_OPTION_LEASE_TIME      51 /* RFC 2132 9.2, time in seconds, in 4 bytes */
-#define DHCP_OPTION_OVERLOAD        52 /* RFC2132 9.3, use file and/or sname field for options */
-
-#define DHCP_OPTION_MESSAGE_TYPE    53 /* RFC 2132 9.6, important for DHCP */
-#define DHCP_OPTION_MESSAGE_TYPE_LEN 1
-
-#define DHCP_OPTION_SERVER_ID       54 /* RFC 2132 9.7, server IP address */
-#define DHCP_OPTION_PARAMETER_REQUEST_LIST  55 /* RFC 2132 9.8, requested option types */
-
-#define DHCP_OPTION_MAX_MSG_SIZE    57 /* RFC 2132 9.10, message size accepted >= 576 */
-#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2
-
-#define DHCP_OPTION_T1              58 /* T1 renewal time */
-#define DHCP_OPTION_T2              59 /* T2 rebinding time */
-#define DHCP_OPTION_US              60
-#define DHCP_OPTION_CLIENT_ID       61
-#define DHCP_OPTION_TFTP_SERVERNAME 66
-#define DHCP_OPTION_BOOTFILE        67
-
-/* possible combinations of overloading the file and sname fields with options */
-#define DHCP_OVERLOAD_NONE          0
-#define DHCP_OVERLOAD_FILE          1
-#define DHCP_OVERLOAD_SNAME         2
-#define DHCP_OVERLOAD_SNAME_FILE    3
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*LWIP_HDR_PROT_DHCP_H*/
diff --git a/tools/sdk/include/lwip/lwip/prot/dns.h b/tools/sdk/include/lwip/lwip/prot/dns.h
deleted file mode 100644
index 94782d6e9c1..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/dns.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/**
- * @file
- * DNS - host name to IP address resolver.
- */
-
-/*
- * Port to lwIP from uIP
- * by Jim Pettinato April 2007
- *
- * security fixes and more by Simon Goldschmidt
- *
- * uIP version Copyright (c) 2002-2003, Adam Dunkels.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
- * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef LWIP_HDR_PROT_DNS_H
-#define LWIP_HDR_PROT_DNS_H
-
-#include "lwip/arch.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** DNS server port address */
-#ifndef DNS_SERVER_PORT
-#define DNS_SERVER_PORT           53
-#endif
-
-/* DNS field TYPE used for "Resource Records" */
-#define DNS_RRTYPE_A              1     /* a host address */
-#define DNS_RRTYPE_NS             2     /* an authoritative name server */
-#define DNS_RRTYPE_MD             3     /* a mail destination (Obsolete - use MX) */
-#define DNS_RRTYPE_MF             4     /* a mail forwarder (Obsolete - use MX) */
-#define DNS_RRTYPE_CNAME          5     /* the canonical name for an alias */
-#define DNS_RRTYPE_SOA            6     /* marks the start of a zone of authority */
-#define DNS_RRTYPE_MB             7     /* a mailbox domain name (EXPERIMENTAL) */
-#define DNS_RRTYPE_MG             8     /* a mail group member (EXPERIMENTAL) */
-#define DNS_RRTYPE_MR             9     /* a mail rename domain name (EXPERIMENTAL) */
-#define DNS_RRTYPE_NULL           10    /* a null RR (EXPERIMENTAL) */
-#define DNS_RRTYPE_WKS            11    /* a well known service description */
-#define DNS_RRTYPE_PTR            12    /* a domain name pointer */
-#define DNS_RRTYPE_HINFO          13    /* host information */
-#define DNS_RRTYPE_MINFO          14    /* mailbox or mail list information */
-#define DNS_RRTYPE_MX             15    /* mail exchange */
-#define DNS_RRTYPE_TXT            16    /* text strings */
-#define DNS_RRTYPE_AAAA           28    /* IPv6 address */
-#define DNS_RRTYPE_SRV            33    /* service location */
-#define DNS_RRTYPE_ANY            255   /* any type */
-
-/* DNS field CLASS used for "Resource Records" */
-#define DNS_RRCLASS_IN            1     /* the Internet */
-#define DNS_RRCLASS_CS            2     /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */
-#define DNS_RRCLASS_CH            3     /* the CHAOS class */
-#define DNS_RRCLASS_HS            4     /* Hesiod [Dyer 87] */
-#define DNS_RRCLASS_ANY           255   /* any class */
-#define DNS_RRCLASS_FLUSH         0x800 /* Flush bit */
-
-/* DNS protocol flags */
-#define DNS_FLAG1_RESPONSE        0x80
-#define DNS_FLAG1_OPCODE_STATUS   0x10
-#define DNS_FLAG1_OPCODE_INVERSE  0x08
-#define DNS_FLAG1_OPCODE_STANDARD 0x00
-#define DNS_FLAG1_AUTHORATIVE     0x04
-#define DNS_FLAG1_TRUNC           0x02
-#define DNS_FLAG1_RD              0x01
-#define DNS_FLAG2_RA              0x80
-#define DNS_FLAG2_ERR_MASK        0x0f
-#define DNS_FLAG2_ERR_NONE        0x00
-#define DNS_FLAG2_ERR_NAME        0x03
-
-#define DNS_HDR_GET_OPCODE(hdr) ((((hdr)->flags1) >> 3) & 0xF)
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/** DNS message header */
-struct dns_hdr {
-  PACK_STRUCT_FIELD(u16_t id);
-  PACK_STRUCT_FLD_8(u8_t flags1);
-  PACK_STRUCT_FLD_8(u8_t flags2);
-  PACK_STRUCT_FIELD(u16_t numquestions);
-  PACK_STRUCT_FIELD(u16_t numanswers);
-  PACK_STRUCT_FIELD(u16_t numauthrr);
-  PACK_STRUCT_FIELD(u16_t numextrarr);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-#define SIZEOF_DNS_HDR 12
-
-
-/* Multicast DNS definitions */
-
-/** UDP port for multicast DNS queries */
-#ifndef DNS_MQUERY_PORT
-#define DNS_MQUERY_PORT             5353
-#endif
-
-/* IPv4 group for multicast DNS queries: 224.0.0.251 */
-#ifndef DNS_MQUERY_IPV4_GROUP_INIT
-#define DNS_MQUERY_IPV4_GROUP_INIT  IPADDR4_INIT_BYTES(224,0,0,251)
-#endif
-
-/* IPv6 group for multicast DNS queries: FF02::FB */
-#ifndef DNS_MQUERY_IPV6_GROUP_INIT
-#define DNS_MQUERY_IPV6_GROUP_INIT  IPADDR6_INIT_HOST(0xFF020000,0,0,0xFB)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_DNS_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/etharp.h b/tools/sdk/include/lwip/lwip/prot/etharp.h
deleted file mode 100644
index ec78305b822..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/etharp.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/**
- * @file
- * ARP protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_ETHARP_H
-#define LWIP_HDR_PROT_ETHARP_H
-
-#include "lwip/arch.h"
-#include "lwip/prot/ethernet.h"
-#include "lwip/ip4_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef ETHARP_HWADDR_LEN
-#define ETHARP_HWADDR_LEN     ETH_HWADDR_LEN
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/** the ARP message, see RFC 826 ("Packet format") */
-struct etharp_hdr {
-  PACK_STRUCT_FIELD(u16_t hwtype);
-  PACK_STRUCT_FIELD(u16_t proto);
-  PACK_STRUCT_FLD_8(u8_t  hwlen);
-  PACK_STRUCT_FLD_8(u8_t  protolen);
-  PACK_STRUCT_FIELD(u16_t opcode);
-  PACK_STRUCT_FLD_S(struct eth_addr shwaddr);
-  PACK_STRUCT_FLD_S(struct ip4_addr2 sipaddr);
-  PACK_STRUCT_FLD_S(struct eth_addr dhwaddr);
-  PACK_STRUCT_FLD_S(struct ip4_addr2 dipaddr);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define SIZEOF_ETHARP_HDR 28
-
-/* ARP hwtype values */
-enum etharp_hwtype {
-  HWTYPE_ETHERNET = 1
-  /* others not used */
-};
-
-/* ARP message types (opcodes) */
-enum etharp_opcode {
-  ARP_REQUEST = 1,
-  ARP_REPLY   = 2
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_ETHARP_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/ethernet.h b/tools/sdk/include/lwip/lwip/prot/ethernet.h
deleted file mode 100644
index e4baa29dc4d..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/ethernet.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/**
- * @file
- * Ethernet protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_ETHERNET_H
-#define LWIP_HDR_PROT_ETHERNET_H
-
-#include "lwip/arch.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef ETH_HWADDR_LEN
-#ifdef ETHARP_HWADDR_LEN
-#define ETH_HWADDR_LEN    ETHARP_HWADDR_LEN /* compatibility mode */
-#else
-#define ETH_HWADDR_LEN    6
-#endif
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct eth_addr {
-  PACK_STRUCT_FLD_8(u8_t addr[ETH_HWADDR_LEN]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/** Ethernet header */
-struct eth_hdr {
-#if ETH_PAD_SIZE
-  PACK_STRUCT_FLD_8(u8_t padding[ETH_PAD_SIZE]);
-#endif
-  PACK_STRUCT_FLD_S(struct eth_addr dest);
-  PACK_STRUCT_FLD_S(struct eth_addr src);
-  PACK_STRUCT_FIELD(u16_t type);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE)
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/** VLAN header inserted between ethernet header and payload
- * if 'type' in ethernet header is ETHTYPE_VLAN.
- * See IEEE802.Q */
-struct eth_vlan_hdr {
-  PACK_STRUCT_FIELD(u16_t prio_vid);
-  PACK_STRUCT_FIELD(u16_t tpid);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define SIZEOF_VLAN_HDR 4
-#define VLAN_ID(vlan_hdr) (lwip_htons((vlan_hdr)->prio_vid) & 0xFFF)
-
-/**
- * @ingroup ethernet
- * A list of often ethtypes (although lwIP does not use all of them): */
-enum eth_type {
-  /** Internet protocol v4 */
-  ETHTYPE_IP        = 0x0800U,
-  /** Address resolution protocol */
-  ETHTYPE_ARP       = 0x0806U, 
-  /** Wake on lan */
-  ETHTYPE_WOL       = 0x0842U,
-  /** RARP */
-  ETHTYPE_RARP      = 0x8035U,
-  /** Virtual local area network */
-  ETHTYPE_VLAN      = 0x8100U,
-  /** Internet protocol v6 */
-  ETHTYPE_IPV6      = 0x86DDU,
-  /** PPP Over Ethernet Discovery Stage */
-  ETHTYPE_PPPOEDISC = 0x8863U,
-  /** PPP Over Ethernet Session Stage */
-  ETHTYPE_PPPOE     = 0x8864U,
-  /** Jumbo Frames */
-  ETHTYPE_JUMBO     = 0x8870U,
-  /** Process field network */
-  ETHTYPE_PROFINET  = 0x8892U,
-  /** Ethernet for control automation technology */
-  ETHTYPE_ETHERCAT  = 0x88A4U,
-  /** Link layer discovery protocol */
-  ETHTYPE_LLDP      = 0x88CCU,
-  /** Serial real-time communication system */
-  ETHTYPE_SERCOS    = 0x88CDU,
-  /** Media redundancy protocol */
-  ETHTYPE_MRP       = 0x88E3U,
-  /** Precision time protocol */
-  ETHTYPE_PTP       = 0x88F7U,
-  /** Q-in-Q, 802.1ad */
-  ETHTYPE_QINQ      = 0x9100U
-};
-
-/** The 24-bit IANA IPv4-multicast OUI is 01-00-5e: */
-#define LL_IP4_MULTICAST_ADDR_0 0x01
-#define LL_IP4_MULTICAST_ADDR_1 0x00
-#define LL_IP4_MULTICAST_ADDR_2 0x5e
-
-/** IPv6 multicast uses this prefix */
-#define LL_IP6_MULTICAST_ADDR_0 0x33
-#define LL_IP6_MULTICAST_ADDR_1 0x33
-
-/** MEMCPY-like macro to copy to/from struct eth_addr's that are local variables
- * or known to be 32-bit aligned within the protocol header. */
-#ifndef ETHADDR32_COPY
-#define ETHADDR32_COPY(dst, src)  SMEMCPY(dst, src, ETH_HWADDR_LEN)
-#endif
-
-/** MEMCPY-like macro to copy to/from struct eth_addr's that are no local
- * variables and known to be 16-bit aligned within the protocol header. */
-#ifndef ETHADDR16_COPY
-#define ETHADDR16_COPY(dst, src)  SMEMCPY(dst, src, ETH_HWADDR_LEN)
-#endif
-
-#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETH_HWADDR_LEN) == 0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_ETHERNET_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/icmp.h b/tools/sdk/include/lwip/lwip/prot/icmp.h
deleted file mode 100644
index 7d19385c729..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/icmp.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/**
- * @file
- * ICMP protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_ICMP_H
-#define LWIP_HDR_PROT_ICMP_H
-
-#include "lwip/arch.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ICMP_ER   0    /* echo reply */
-#define ICMP_DUR  3    /* destination unreachable */
-#define ICMP_SQ   4    /* source quench */
-#define ICMP_RD   5    /* redirect */
-#define ICMP_ECHO 8    /* echo */
-#define ICMP_TE  11    /* time exceeded */
-#define ICMP_PP  12    /* parameter problem */
-#define ICMP_TS  13    /* timestamp */
-#define ICMP_TSR 14    /* timestamp reply */
-#define ICMP_IRQ 15    /* information request */
-#define ICMP_IR  16    /* information reply */
-#define ICMP_AM  17    /* address mask request */
-#define ICMP_AMR 18    /* address mask reply */
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-/** This is the standard ICMP header only that the u32_t data
- *  is split to two u16_t like ICMP echo needs it.
- *  This header is also used for other ICMP types that do not
- *  use the data part.
- */
-PACK_STRUCT_BEGIN
-struct icmp_echo_hdr {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u16_t id);
-  PACK_STRUCT_FIELD(u16_t seqno);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/* Compatibility defines, old versions used to combine type and code to an u16_t */
-#define ICMPH_TYPE(hdr) ((hdr)->type)
-#define ICMPH_CODE(hdr) ((hdr)->code)
-#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t))
-#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_ICMP_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/icmp6.h b/tools/sdk/include/lwip/lwip/prot/icmp6.h
deleted file mode 100644
index 3461120421e..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/icmp6.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/**
- * @file
- * ICMP6 protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_ICMP6_H
-#define LWIP_HDR_PROT_ICMP6_H
-
-#include "lwip/arch.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ICMP type */
-enum icmp6_type {
-  /** Destination unreachable */
-  ICMP6_TYPE_DUR = 1,
-  /** Packet too big */
-  ICMP6_TYPE_PTB = 2,
-  /** Time exceeded */
-  ICMP6_TYPE_TE = 3,
-  /** Parameter problem */
-  ICMP6_TYPE_PP = 4,
-  /** Private experimentation */
-  ICMP6_TYPE_PE1 = 100,
-  /** Private experimentation */
-  ICMP6_TYPE_PE2 = 101,
-  /** Reserved for expansion of error messages */
-  ICMP6_TYPE_RSV_ERR = 127,
-
-  /** Echo request */
-  ICMP6_TYPE_EREQ = 128,
-  /** Echo reply */
-  ICMP6_TYPE_EREP = 129,
-  /** Multicast listener query */
-  ICMP6_TYPE_MLQ = 130,
-  /** Multicast listener report */
-  ICMP6_TYPE_MLR = 131,
-  /** Multicast listener done */
-  ICMP6_TYPE_MLD = 132,
-  /** Router solicitation */
-  ICMP6_TYPE_RS = 133,
-  /** Router advertisement */
-  ICMP6_TYPE_RA = 134,
-  /** Neighbor solicitation */
-  ICMP6_TYPE_NS = 135,
-  /** Neighbor advertisement */
-  ICMP6_TYPE_NA = 136,
-  /** Redirect */
-  ICMP6_TYPE_RD = 137,
-  /** Multicast router advertisement */
-  ICMP6_TYPE_MRA = 151,
-  /** Multicast router solicitation */
-  ICMP6_TYPE_MRS = 152,
-  /** Multicast router termination */
-  ICMP6_TYPE_MRT = 153,
-  /** Private experimentation */
-  ICMP6_TYPE_PE3 = 200,
-  /** Private experimentation */
-  ICMP6_TYPE_PE4 = 201,
-  /** Reserved for expansion of informational messages */
-  ICMP6_TYPE_RSV_INF = 255
-};
-
-/** ICMP destination unreachable codes */
-enum icmp6_dur_code {
-  /** No route to destination */
-  ICMP6_DUR_NO_ROUTE = 0,
-  /** Communication with destination administratively prohibited */
-  ICMP6_DUR_PROHIBITED = 1,
-  /** Beyond scope of source address */
-  ICMP6_DUR_SCOPE = 2,
-  /** Address unreachable */
-  ICMP6_DUR_ADDRESS = 3,
-  /** Port unreachable */
-  ICMP6_DUR_PORT = 4,
-  /** Source address failed ingress/egress policy */
-  ICMP6_DUR_POLICY = 5,
-  /** Reject route to destination */
-  ICMP6_DUR_REJECT_ROUTE = 6
-};
-
-/** ICMP time exceeded codes */
-enum icmp6_te_code {
-  /** Hop limit exceeded in transit */
-  ICMP6_TE_HL = 0,
-  /** Fragment reassembly time exceeded */
-  ICMP6_TE_FRAG = 1
-};
-
-/** ICMP parameter code */
-enum icmp6_pp_code {
-  /** Erroneous header field encountered */
-  ICMP6_PP_FIELD = 0,
-  /** Unrecognized next header type encountered */
-  ICMP6_PP_HEADER = 1,
-  /** Unrecognized IPv6 option encountered */
-  ICMP6_PP_OPTION = 2
-};
-
-/** This is the standard ICMP6 header. */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct icmp6_hdr {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u32_t data);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** This is the ICMP6 header adapted for echo req/resp. */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct icmp6_echo_hdr {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u16_t id);
-  PACK_STRUCT_FIELD(u16_t seqno);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_ICMP6_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/igmp.h b/tools/sdk/include/lwip/lwip/prot/igmp.h
deleted file mode 100644
index d60cb31ee7c..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/igmp.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- * @file
- * IGMP protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_IGMP_H
-#define LWIP_HDR_PROT_IGMP_H
-
-#include "lwip/arch.h"
-#include "lwip/ip4_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * IGMP constants
- */
-#define IGMP_TTL                       1
-#define IGMP_MINLEN                    8
-#define ROUTER_ALERT                   0x9404U
-#define ROUTER_ALERTLEN                4
-
-/*
- * IGMP message types, including version number.
- */
-#define IGMP_MEMB_QUERY                0x11 /* Membership query         */
-#define IGMP_V1_MEMB_REPORT            0x12 /* Ver. 1 membership report */
-#define IGMP_V2_MEMB_REPORT            0x16 /* Ver. 2 membership report */
-#define IGMP_LEAVE_GROUP               0x17 /* Leave-group message      */
-
-/* Group  membership states */
-#define IGMP_GROUP_NON_MEMBER          0
-#define IGMP_GROUP_DELAYING_MEMBER     1
-#define IGMP_GROUP_IDLE_MEMBER         2
-
-/**
- * IGMP packet format.
- */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct igmp_msg {
-  PACK_STRUCT_FLD_8(u8_t         igmp_msgtype);
-  PACK_STRUCT_FLD_8(u8_t         igmp_maxresp);
-  PACK_STRUCT_FIELD(u16_t        igmp_checksum);
-  PACK_STRUCT_FLD_S(ip4_addr_p_t igmp_group_address);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_IGMP_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/ip.h b/tools/sdk/include/lwip/lwip/prot/ip.h
deleted file mode 100644
index bbfae367527..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/ip.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
- * @file
- * IP protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_IP_H
-#define LWIP_HDR_PROT_IP_H
-
-#include "lwip/arch.h"
-
-#define IP_PROTO_ICMP    1
-#define IP_PROTO_IGMP    2
-#define IP_PROTO_UDP     17
-#define IP_PROTO_UDPLITE 136
-#define IP_PROTO_TCP     6
-
-/** This operates on a void* by loading the first byte */
-#define IP_HDR_GET_VERSION(ptr)   ((*(u8_t*)(ptr)) >> 4)
-
-#endif /* LWIP_HDR_PROT_IP_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/ip4.h b/tools/sdk/include/lwip/lwip/prot/ip4.h
deleted file mode 100644
index bd442c6892c..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/ip4.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
- * @file
- * IPv4 protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_IP4_H
-#define LWIP_HDR_PROT_IP4_H
-
-#include "lwip/arch.h"
-#include "lwip/ip4_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** This is the packed version of ip4_addr_t,
-    used in network headers that are itself packed */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip4_addr_packed {
-  PACK_STRUCT_FIELD(u32_t addr);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-typedef struct ip4_addr_packed ip4_addr_p_t;
-
-/* Size of the IPv4 header. Same as 'sizeof(struct ip_hdr)'. */
-#define IP_HLEN 20
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-/* The IPv4 header */
-struct ip_hdr {
-  /* version / header length */
-  PACK_STRUCT_FLD_8(u8_t _v_hl);
-  /* type of service */
-  PACK_STRUCT_FLD_8(u8_t _tos);
-  /* total length */
-  PACK_STRUCT_FIELD(u16_t _len);
-  /* identification */
-  PACK_STRUCT_FIELD(u16_t _id);
-  /* fragment offset field */
-  PACK_STRUCT_FIELD(u16_t _offset);
-#define IP_RF 0x8000U        /* reserved fragment flag */
-#define IP_DF 0x4000U        /* don't fragment flag */
-#define IP_MF 0x2000U        /* more fragments flag */
-#define IP_OFFMASK 0x1fffU   /* mask for fragmenting bits */
-  /* time to live */
-  PACK_STRUCT_FLD_8(u8_t _ttl);
-  /* protocol*/
-  PACK_STRUCT_FLD_8(u8_t _proto);
-  /* checksum */
-  PACK_STRUCT_FIELD(u16_t _chksum);
-  /* source and destination IP addresses */
-  PACK_STRUCT_FLD_S(ip4_addr_p_t src);
-  PACK_STRUCT_FLD_S(ip4_addr_p_t dest);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/* Macros to get struct ip_hdr fields: */
-#define IPH_V(hdr)  ((hdr)->_v_hl >> 4)
-#define IPH_HL(hdr) ((hdr)->_v_hl & 0x0f)
-#define IPH_TOS(hdr) ((hdr)->_tos)
-#define IPH_LEN(hdr) ((hdr)->_len)
-#define IPH_ID(hdr) ((hdr)->_id)
-#define IPH_OFFSET(hdr) ((hdr)->_offset)
-#define IPH_TTL(hdr) ((hdr)->_ttl)
-#define IPH_PROTO(hdr) ((hdr)->_proto)
-#define IPH_CHKSUM(hdr) ((hdr)->_chksum)
-
-/* Macros to set struct ip_hdr fields: */
-#define IPH_VHL_SET(hdr, v, hl) (hdr)->_v_hl = (u8_t)((((v) << 4) | (hl)))
-#define IPH_TOS_SET(hdr, tos) (hdr)->_tos = (tos)
-#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len)
-#define IPH_ID_SET(hdr, id) (hdr)->_id = (id)
-#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off)
-#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl = (u8_t)(ttl)
-#define IPH_PROTO_SET(hdr, proto) (hdr)->_proto = (u8_t)(proto)
-#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum)
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_IP4_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/ip6.h b/tools/sdk/include/lwip/lwip/prot/ip6.h
deleted file mode 100644
index 6e1e2632bfc..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/ip6.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
- * @file
- * IPv6 protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_IP6_H
-#define LWIP_HDR_PROT_IP6_H
-
-#include "lwip/arch.h"
-#include "lwip/ip6_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-   
-/** This is the packed version of ip6_addr_t,
-    used in network headers that are itself packed */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip6_addr_packed {
-  PACK_STRUCT_FIELD(u32_t addr[4]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-typedef struct ip6_addr_packed ip6_addr_p_t;
-
-#define IP6_HLEN 40
-
-#define IP6_NEXTH_HOPBYHOP  0
-#define IP6_NEXTH_TCP       6
-#define IP6_NEXTH_UDP       17
-#define IP6_NEXTH_ENCAPS    41
-#define IP6_NEXTH_ROUTING   43
-#define IP6_NEXTH_FRAGMENT  44
-#define IP6_NEXTH_ICMP6     58
-#define IP6_NEXTH_NONE      59
-#define IP6_NEXTH_DESTOPTS  60
-#define IP6_NEXTH_UDPLITE   136
-
-/** The IPv6 header. */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip6_hdr {
-  /** version / traffic class / flow label */
-  PACK_STRUCT_FIELD(u32_t _v_tc_fl);
-  /** payload length */
-  PACK_STRUCT_FIELD(u16_t _plen);
-  /** next header */
-  PACK_STRUCT_FLD_8(u8_t _nexth);
-  /** hop limit */
-  PACK_STRUCT_FLD_8(u8_t _hoplim);
-  /** source and destination IP addresses */
-  PACK_STRUCT_FLD_S(ip6_addr_p_t src);
-  PACK_STRUCT_FLD_S(ip6_addr_p_t dest);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/* Hop-by-hop router alert option. */
-#define IP6_HBH_HLEN    8
-#define IP6_PAD1_OPTION         0
-#define IP6_PADN_ALERT_OPTION   1
-#define IP6_ROUTER_ALERT_OPTION 5
-#define IP6_ROUTER_ALERT_VALUE_MLD 0
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip6_hbh_hdr {
-  /* next header */
-  PACK_STRUCT_FLD_8(u8_t _nexth);
-  /* header length */
-  PACK_STRUCT_FLD_8(u8_t _hlen);
-  /* router alert option type */
-  PACK_STRUCT_FLD_8(u8_t _ra_opt_type);
-  /* router alert option data len */
-  PACK_STRUCT_FLD_8(u8_t _ra_opt_dlen);
-  /* router alert option data */
-  PACK_STRUCT_FIELD(u16_t _ra_opt_data);
-  /* PadN option type */
-  PACK_STRUCT_FLD_8(u8_t _padn_opt_type);
-  /* PadN option data len */
-  PACK_STRUCT_FLD_8(u8_t _padn_opt_dlen);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/* Fragment header. */
-#define IP6_FRAG_HLEN    8
-#define IP6_FRAG_OFFSET_MASK    0xfff8
-#define IP6_FRAG_MORE_FLAG      0x0001
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ip6_frag_hdr {
-  /* next header */
-  PACK_STRUCT_FLD_8(u8_t _nexth);
-  /* reserved */
-  PACK_STRUCT_FLD_8(u8_t reserved);
-  /* fragment offset */
-  PACK_STRUCT_FIELD(u16_t _fragment_offset);
-  /* fragmented packet identification */
-  PACK_STRUCT_FIELD(u32_t _identification);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#define IP6H_V(hdr)  ((lwip_ntohl((hdr)->_v_tc_fl) >> 28) & 0x0f)
-#define IP6H_TC(hdr) ((lwip_ntohl((hdr)->_v_tc_fl) >> 20) & 0xff)
-#define IP6H_FL(hdr) (lwip_ntohl((hdr)->_v_tc_fl) & 0x000fffff)
-#define IP6H_PLEN(hdr) (lwip_ntohs((hdr)->_plen))
-#define IP6H_NEXTH(hdr) ((hdr)->_nexth)
-#define IP6H_NEXTH_P(hdr) ((u8_t *)(hdr) + 6)
-#define IP6H_HOPLIM(hdr) ((hdr)->_hoplim)
-
-#define IP6H_VTCFL_SET(hdr, v, tc, fl) (hdr)->_v_tc_fl = (lwip_htonl((((u32_t)(v)) << 28) | (((u32_t)(tc)) << 20) | (fl)))
-#define IP6H_PLEN_SET(hdr, plen) (hdr)->_plen = lwip_htons(plen)
-#define IP6H_NEXTH_SET(hdr, nexth) (hdr)->_nexth = (nexth)
-#define IP6H_HOPLIM_SET(hdr, hl) (hdr)->_hoplim = (u8_t)(hl)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_IP6_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/mld6.h b/tools/sdk/include/lwip/lwip/prot/mld6.h
deleted file mode 100644
index be3a006af25..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/mld6.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/**
- * @file
- * MLD6 protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_MLD6_H
-#define LWIP_HDR_PROT_MLD6_H
-
-#include "lwip/arch.h"
-#include "lwip/prot/ip6.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Multicast listener report/query/done message header. */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct mld_header {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u16_t max_resp_delay);
-  PACK_STRUCT_FIELD(u16_t reserved);
-  PACK_STRUCT_FLD_S(ip6_addr_p_t multicast_address);
-  /* Options follow. */
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_MLD6_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/nd6.h b/tools/sdk/include/lwip/lwip/prot/nd6.h
deleted file mode 100644
index 2d4903d15b6..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/nd6.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/**
- * @file
- * ND6 protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_ND6_H
-#define LWIP_HDR_PROT_ND6_H
-
-#include "lwip/arch.h"
-#include "lwip/ip6_addr.h"
-#include "lwip/prot/ip6.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Neighbor solicitation message header. */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ns_header {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u32_t reserved);
-  PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
-  /* Options follow. */
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** Neighbor advertisement message header. */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct na_header {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FLD_8(u8_t flags);
-  PACK_STRUCT_FLD_8(u8_t reserved[3]);
-  PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
-  /* Options follow. */
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-#define ND6_FLAG_ROUTER      (0x80)
-#define ND6_FLAG_SOLICITED   (0x40)
-#define ND6_FLAG_OVERRIDE    (0x20)
-
-/** Router solicitation message header. */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct rs_header {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u32_t reserved);
-  /* Options follow. */
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** Router advertisement message header. */
-#define ND6_RA_FLAG_MANAGED_ADDR_CONFIG (0x80)
-#define ND6_RA_FLAG_OTHER_CONFIG (0x40)
-#define ND6_RA_FLAG_HOME_AGENT (0x20)
-#define ND6_RA_PREFERENCE_MASK (0x18)
-#define ND6_RA_PREFERENCE_HIGH (0x08)
-#define ND6_RA_PREFERENCE_MEDIUM (0x00)
-#define ND6_RA_PREFERENCE_LOW (0x18)
-#define ND6_RA_PREFERENCE_DISABLED (0x10)
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct ra_header {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FLD_8(u8_t current_hop_limit);
-  PACK_STRUCT_FLD_8(u8_t flags);
-  PACK_STRUCT_FIELD(u16_t router_lifetime);
-  PACK_STRUCT_FIELD(u32_t reachable_time);
-  PACK_STRUCT_FIELD(u32_t retrans_timer);
-  /* Options follow. */
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** Redirect message header. */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct redirect_header {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u32_t reserved);
-  PACK_STRUCT_FLD_S(ip6_addr_p_t target_address);
-  PACK_STRUCT_FLD_S(ip6_addr_p_t destination_address);
-  /* Options follow. */
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** Link-layer address option. */
-#define ND6_OPTION_TYPE_SOURCE_LLADDR (0x01)
-#define ND6_OPTION_TYPE_TARGET_LLADDR (0x02)
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct lladdr_option {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t length);
-  PACK_STRUCT_FLD_8(u8_t addr[NETIF_MAX_HWADDR_LEN]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** Prefix information option. */
-#define ND6_OPTION_TYPE_PREFIX_INFO (0x03)
-#define ND6_PREFIX_FLAG_ON_LINK (0x80)
-#define ND6_PREFIX_FLAG_AUTONOMOUS (0x40)
-#define ND6_PREFIX_FLAG_ROUTER_ADDRESS (0x20)
-#define ND6_PREFIX_FLAG_SITE_PREFIX (0x10)
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct prefix_option {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t length);
-  PACK_STRUCT_FLD_8(u8_t prefix_length);
-  PACK_STRUCT_FLD_8(u8_t flags);
-  PACK_STRUCT_FIELD(u32_t valid_lifetime);
-  PACK_STRUCT_FIELD(u32_t preferred_lifetime);
-  PACK_STRUCT_FLD_8(u8_t reserved2[3]);
-  PACK_STRUCT_FLD_8(u8_t site_prefix_length);
-  PACK_STRUCT_FLD_S(ip6_addr_p_t prefix);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** Redirected header option. */
-#define ND6_OPTION_TYPE_REDIR_HDR (0x04)
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct redirected_header_option {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t length);
-  PACK_STRUCT_FLD_8(u8_t reserved[6]);
-  /* Portion of redirected packet follows. */
-  /* PACK_STRUCT_FLD_8(u8_t redirected[8]); */
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** MTU option. */
-#define ND6_OPTION_TYPE_MTU (0x05)
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct mtu_option {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t length);
-  PACK_STRUCT_FIELD(u16_t reserved);
-  PACK_STRUCT_FIELD(u32_t mtu);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** Route information option. */
-#define ND6_OPTION_TYPE_ROUTE_INFO (24)
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct route_option {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t length);
-  PACK_STRUCT_FLD_8(u8_t prefix_length);
-  PACK_STRUCT_FLD_8(u8_t preference);
-  PACK_STRUCT_FIELD(u32_t route_lifetime);
-  PACK_STRUCT_FLD_S(ip6_addr_p_t prefix);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/** Recursive DNS Server Option. */
-#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS
-#define LWIP_RDNSS_OPTION_MAX_SERVERS LWIP_ND6_RDNSS_MAX_DNS_SERVERS
-#else
-#define LWIP_RDNSS_OPTION_MAX_SERVERS 1
-#endif
-#define ND6_OPTION_TYPE_RDNSS (25)
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct rdnss_option {
-  PACK_STRUCT_FLD_8(u8_t type);
-  PACK_STRUCT_FLD_8(u8_t length);
-  PACK_STRUCT_FIELD(u16_t reserved);
-  PACK_STRUCT_FIELD(u32_t lifetime);
-  PACK_STRUCT_FLD_S(ip6_addr_p_t rdnss_address[LWIP_RDNSS_OPTION_MAX_SERVERS]);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_ND6_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/tcp.h b/tools/sdk/include/lwip/lwip/prot/tcp.h
deleted file mode 100644
index 67fe7b9e5fc..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/tcp.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
- * @file
- * TCP protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_TCP_H
-#define LWIP_HDR_PROT_TCP_H
-
-#include "lwip/arch.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Length of the TCP header, excluding options. */
-#define TCP_HLEN 20
-
-/* Fields are (of course) in network byte order.
- * Some fields are converted to host byte order in tcp_input().
- */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct tcp_hdr {
-  PACK_STRUCT_FIELD(u16_t src);
-  PACK_STRUCT_FIELD(u16_t dest);
-  PACK_STRUCT_FIELD(u32_t seqno);
-  PACK_STRUCT_FIELD(u32_t ackno);
-  PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags);
-  PACK_STRUCT_FIELD(u16_t wnd);
-  PACK_STRUCT_FIELD(u16_t chksum);
-  PACK_STRUCT_FIELD(u16_t urgp);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-/* TCP header flags bits */
-#define TCP_FIN 0x01U
-#define TCP_SYN 0x02U
-#define TCP_RST 0x04U
-#define TCP_PSH 0x08U
-#define TCP_ACK 0x10U
-#define TCP_URG 0x20U
-#define TCP_ECE 0x40U
-#define TCP_CWR 0x80U
-/* Valid TCP header flags */
-#define TCP_FLAGS 0x3fU
-
-#define TCPH_HDRLEN(phdr) ((u16_t)(lwip_ntohs((phdr)->_hdrlen_rsvd_flags) >> 12))
-#define TCPH_FLAGS(phdr)  ((u16_t)(lwip_ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS))
-
-#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = lwip_htons(((len) << 12) | TCPH_FLAGS(phdr))
-#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS(~TCP_FLAGS)) | lwip_htons(flags))
-#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = (u16_t)(lwip_htons((u16_t)((len) << 12) | (flags)))
-
-#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | lwip_htons(flags))
-#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags & ~lwip_htons(flags))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_TCP_H */
diff --git a/tools/sdk/include/lwip/lwip/prot/udp.h b/tools/sdk/include/lwip/lwip/prot/udp.h
deleted file mode 100644
index 664f19a3e7b..00000000000
--- a/tools/sdk/include/lwip/lwip/prot/udp.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/**
- * @file
- * UDP protocol definitions
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_PROT_UDP_H
-#define LWIP_HDR_PROT_UDP_H
-
-#include "lwip/arch.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define UDP_HLEN 8
-
-/* Fields are (of course) in network byte order. */
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct udp_hdr {
-  PACK_STRUCT_FIELD(u16_t src);
-  PACK_STRUCT_FIELD(u16_t dest);  /* src/dest UDP ports */
-  PACK_STRUCT_FIELD(u16_t len);
-  PACK_STRUCT_FIELD(u16_t chksum);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_PROT_UDP_H */
diff --git a/tools/sdk/include/lwip/lwip/raw.h b/tools/sdk/include/lwip/lwip/raw.h
deleted file mode 100644
index 30aa1471096..00000000000
--- a/tools/sdk/include/lwip/lwip/raw.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/**
- * @file
- * raw API (to be used from TCPIP thread)\n
- * See also @ref raw_raw
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_RAW_H
-#define LWIP_HDR_RAW_H
-
-#include "lwip/opt.h"
-
-#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/pbuf.h"
-#include "lwip/def.h"
-#include "lwip/ip.h"
-#include "lwip/ip_addr.h"
-#include "lwip/ip6_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct raw_pcb;
-
-/** Function prototype for raw pcb receive callback functions.
- * @param arg user supplied argument (raw_pcb.recv_arg)
- * @param pcb the raw_pcb which received data
- * @param p the packet buffer that was received
- * @param addr the remote IP address from which the packet was received
- * @return 1 if the packet was 'eaten' (aka. deleted),
- *         0 if the packet lives on
- * If returning 1, the callback is responsible for freeing the pbuf
- * if it's not used any more.
- */
-typedef u8_t (*raw_recv_fn)(void *arg, struct raw_pcb *pcb, struct pbuf *p,
-    const ip_addr_t *addr);
-
-/** the RAW protocol control block */
-struct raw_pcb {
-  /* Common members of all PCB types */
-  IP_PCB;
-
-  struct raw_pcb *next;
-
-  u8_t protocol;
-
-  /** receive callback function */
-  raw_recv_fn recv;
-  /* user-supplied argument for the recv callback */
-  void *recv_arg;
-#if LWIP_IPV6
-  /* fields for handling checksum computations as per RFC3542. */
-  u16_t chksum_offset;
-  u8_t  chksum_reqd;
-#endif
-};
-
-/* The following functions is the application layer interface to the
-   RAW code. */
-struct raw_pcb * raw_new        (u8_t proto);
-struct raw_pcb * raw_new_ip_type(u8_t type, u8_t proto);
-void             raw_remove     (struct raw_pcb *pcb);
-err_t            raw_bind       (struct raw_pcb *pcb, const ip_addr_t *ipaddr);
-err_t            raw_connect    (struct raw_pcb *pcb, const ip_addr_t *ipaddr);
-
-err_t            raw_sendto     (struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *ipaddr);
-err_t            raw_send       (struct raw_pcb *pcb, struct pbuf *p);
-
-void             raw_recv       (struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg);
-
-/* The following functions are the lower layer interface to RAW. */
-u8_t             raw_input      (struct pbuf *p, struct netif *inp);
-#define raw_init() /* Compatibility define, no init needed. */
-
-void raw_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr);
-
-/* for compatibility with older implementation */
-#define raw_new_ip6(proto) raw_new_ip_type(IPADDR_TYPE_V6, proto)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_RAW */
-
-#endif /* LWIP_HDR_RAW_H */
diff --git a/tools/sdk/include/lwip/lwip/sio.h b/tools/sdk/include/lwip/lwip/sio.h
deleted file mode 100644
index 7643e195697..00000000000
--- a/tools/sdk/include/lwip/lwip/sio.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- */
-
-/*
- * This is the interface to the platform specific serial IO module
- * It needs to be implemented by those platforms which need SLIP or PPP
- */
-
-#ifndef SIO_H
-#define SIO_H
-
-#include "lwip/arch.h"
-#include "lwip/opt.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* If you want to define sio_fd_t elsewhere or differently,
-   define this in your cc.h file. */
-#ifndef __sio_fd_t_defined
-typedef void * sio_fd_t;
-#endif
-
-/* The following functions can be defined to something else in your cc.h file
-   or be implemented in your custom sio.c file. */
-
-#ifndef sio_open
-/**
- * Opens a serial device for communication.
- *
- * @param devnum device number
- * @return handle to serial device if successful, NULL otherwise
- */
-sio_fd_t sio_open(u8_t devnum);
-#endif
-
-#ifndef sio_send
-/**
- * Sends a single character to the serial device.
- *
- * @param c character to send
- * @param fd serial device handle
- *
- * @note This function will block until the character can be sent.
- */
-void sio_send(u8_t c, sio_fd_t fd);
-#endif
-
-#ifndef sio_recv
-/**
- * Receives a single character from the serial device.
- *
- * @param fd serial device handle
- *
- * @note This function will block until a character is received.
- */
-u8_t sio_recv(sio_fd_t fd);
-#endif
-
-#ifndef sio_read
-/**
- * Reads from the serial device.
- *
- * @param fd serial device handle
- * @param data pointer to data buffer for receiving
- * @param len maximum length (in bytes) of data to receive
- * @return number of bytes actually received - may be 0 if aborted by sio_read_abort
- *
- * @note This function will block until data can be received. The blocking
- * can be cancelled by calling sio_read_abort().
- */
-u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len);
-#endif
-
-#ifndef sio_tryread
-/**
- * Tries to read from the serial device. Same as sio_read but returns
- * immediately if no data is available and never blocks.
- *
- * @param fd serial device handle
- * @param data pointer to data buffer for receiving
- * @param len maximum length (in bytes) of data to receive
- * @return number of bytes actually received
- */
-u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len);
-#endif
-
-#ifndef sio_write
-/**
- * Writes to the serial device.
- *
- * @param fd serial device handle
- * @param data pointer to data to send
- * @param len length (in bytes) of data to send
- * @return number of bytes actually sent
- *
- * @note This function will block until all data can be sent.
- */
-u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len);
-#endif
-
-#ifndef sio_read_abort
-/**
- * Aborts a blocking sio_read() call.
- *
- * @param fd serial device handle
- */
-void sio_read_abort(sio_fd_t fd);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SIO_H */
diff --git a/tools/sdk/include/lwip/lwip/snmp.h b/tools/sdk/include/lwip/lwip/snmp.h
deleted file mode 100644
index 8704d0b4d29..00000000000
--- a/tools/sdk/include/lwip/lwip/snmp.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/**
- * @file
- * SNMP support API for implementing netifs and statitics for MIB2
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Dirk Ziegelmeier <dziegel@gmx.de>
- *
- */
-#ifndef LWIP_HDR_SNMP_H
-#define LWIP_HDR_SNMP_H
-
-#include "lwip/opt.h"
-#include "lwip/ip_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct udp_pcb;
-struct netif;
-
-/**
- * @defgroup netif_mib2 MIB2 statistics
- * @ingroup netif
- */
-
-/* MIB2 statistics functions */
-#if MIB2_STATS  /* don't build if not configured for use in lwipopts.h */
-/**
- * @ingroup netif_mib2
- * @see RFC1213, "MIB-II, 6. Definitions"
- */
-enum snmp_ifType {
-  snmp_ifType_other=1,                /* none of the following */
-  snmp_ifType_regular1822,
-  snmp_ifType_hdh1822,
-  snmp_ifType_ddn_x25,
-  snmp_ifType_rfc877_x25,
-  snmp_ifType_ethernet_csmacd,
-  snmp_ifType_iso88023_csmacd,
-  snmp_ifType_iso88024_tokenBus,
-  snmp_ifType_iso88025_tokenRing,
-  snmp_ifType_iso88026_man,
-  snmp_ifType_starLan,
-  snmp_ifType_proteon_10Mbit,
-  snmp_ifType_proteon_80Mbit,
-  snmp_ifType_hyperchannel,
-  snmp_ifType_fddi,
-  snmp_ifType_lapb,
-  snmp_ifType_sdlc,
-  snmp_ifType_ds1,                    /* T-1 */
-  snmp_ifType_e1,                     /* european equiv. of T-1 */
-  snmp_ifType_basicISDN,
-  snmp_ifType_primaryISDN,            /* proprietary serial */
-  snmp_ifType_propPointToPointSerial,
-  snmp_ifType_ppp,
-  snmp_ifType_softwareLoopback,
-  snmp_ifType_eon,                    /* CLNP over IP [11] */
-  snmp_ifType_ethernet_3Mbit,
-  snmp_ifType_nsip,                   /* XNS over IP */
-  snmp_ifType_slip,                   /* generic SLIP */
-  snmp_ifType_ultra,                  /* ULTRA technologies */
-  snmp_ifType_ds3,                    /* T-3 */
-  snmp_ifType_sip,                    /* SMDS */
-  snmp_ifType_frame_relay
-};
-
-/** This macro has a precision of ~49 days because sys_now returns u32_t. \#define your own if you want ~490 days. */
-#ifndef MIB2_COPY_SYSUPTIME_TO
-#define MIB2_COPY_SYSUPTIME_TO(ptrToVal) (*(ptrToVal) = (sys_now() / 10))
-#endif
-
-/**
- * @ingroup netif_mib2
- * Increment stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs)
- */
-#define MIB2_STATS_NETIF_INC(n, x)      do { ++(n)->mib2_counters.x; } while(0)
-/**
- * @ingroup netif_mib2
- * Add value to stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs)
- */
-#define MIB2_STATS_NETIF_ADD(n, x, val) do { (n)->mib2_counters.x += (val); } while(0)
-
-/**
- * @ingroup netif_mib2
- * Init MIB2 statistic counters in netif
- * @param netif Netif to init
- * @param type one of enum @ref snmp_ifType
- * @param speed your link speed here (units: bits per second)
- */
-#define MIB2_INIT_NETIF(netif, type, speed) do { \
-  (netif)->link_type = (type);  \
-  (netif)->link_speed = (speed);\
-  (netif)->ts = 0;              \
-  (netif)->mib2_counters.ifinoctets = 0;      \
-  (netif)->mib2_counters.ifinucastpkts = 0;   \
-  (netif)->mib2_counters.ifinnucastpkts = 0;  \
-  (netif)->mib2_counters.ifindiscards = 0;    \
-  (netif)->mib2_counters.ifinerrors = 0;    \
-  (netif)->mib2_counters.ifinunknownprotos = 0;    \
-  (netif)->mib2_counters.ifoutoctets = 0;     \
-  (netif)->mib2_counters.ifoutucastpkts = 0;  \
-  (netif)->mib2_counters.ifoutnucastpkts = 0; \
-  (netif)->mib2_counters.ifoutdiscards = 0; \
-  (netif)->mib2_counters.ifouterrors = 0; } while(0)
-#else /* MIB2_STATS */
-#ifndef MIB2_COPY_SYSUPTIME_TO
-#define MIB2_COPY_SYSUPTIME_TO(ptrToVal)
-#endif
-#define MIB2_INIT_NETIF(netif, type, speed)
-#define MIB2_STATS_NETIF_INC(n, x)
-#define MIB2_STATS_NETIF_ADD(n, x, val)
-#endif /* MIB2_STATS */
-
-/* LWIP MIB2 callbacks */
-#if LWIP_MIB2_CALLBACKS /* don't build if not configured for use in lwipopts.h */
-/* network interface */
-void mib2_netif_added(struct netif *ni);
-void mib2_netif_removed(struct netif *ni);
-
-#if LWIP_IPV4 && LWIP_ARP
-/* ARP (for atTable and ipNetToMediaTable) */
-void mib2_add_arp_entry(struct netif *ni, ip4_addr_t *ip);
-void mib2_remove_arp_entry(struct netif *ni, ip4_addr_t *ip);
-#else /* LWIP_IPV4 && LWIP_ARP */
-#define mib2_add_arp_entry(ni,ip)
-#define mib2_remove_arp_entry(ni,ip)
-#endif /* LWIP_IPV4 && LWIP_ARP */
-
-/* IP */
-#if LWIP_IPV4
-void mib2_add_ip4(struct netif *ni);
-void mib2_remove_ip4(struct netif *ni);
-void mib2_add_route_ip4(u8_t dflt, struct netif *ni);
-void mib2_remove_route_ip4(u8_t dflt, struct netif *ni);
-#endif /* LWIP_IPV4 */
-
-/* UDP */
-#if LWIP_UDP
-void mib2_udp_bind(struct udp_pcb *pcb);
-void mib2_udp_unbind(struct udp_pcb *pcb);
-#endif /* LWIP_UDP */
-
-#else /* LWIP_MIB2_CALLBACKS */
-/* LWIP_MIB2_CALLBACKS support not available */
-/* define everything to be empty */
-
-/* network interface */
-#define mib2_netif_added(ni)
-#define mib2_netif_removed(ni)
-
-/* ARP */
-#define mib2_add_arp_entry(ni,ip)
-#define mib2_remove_arp_entry(ni,ip)
-
-/* IP */
-#define mib2_add_ip4(ni)
-#define mib2_remove_ip4(ni)
-#define mib2_add_route_ip4(dflt, ni)
-#define mib2_remove_route_ip4(dflt, ni)
-
-/* UDP */
-#define mib2_udp_bind(pcb)
-#define mib2_udp_unbind(pcb)
-#endif /* LWIP_MIB2_CALLBACKS */
-
-/* for source-code compatibility reasons only, can be removed (not used internally) */
-#define NETIF_INIT_SNMP                MIB2_INIT_NETIF
-#define snmp_add_ifinoctets(ni,value)  MIB2_STATS_NETIF_ADD(ni, ifinoctets, value)
-#define snmp_inc_ifinucastpkts(ni)     MIB2_STATS_NETIF_INC(ni, ifinucastpkts)
-#define snmp_inc_ifinnucastpkts(ni)    MIB2_STATS_NETIF_INC(ni, ifinnucastpkts)
-#define snmp_inc_ifindiscards(ni)      MIB2_STATS_NETIF_INC(ni, ifindiscards)
-#define snmp_inc_ifinerrors(ni)        MIB2_STATS_NETIF_INC(ni, ifinerrors)
-#define snmp_inc_ifinunknownprotos(ni) MIB2_STATS_NETIF_INC(ni, ifinunknownprotos)
-#define snmp_add_ifoutoctets(ni,value) MIB2_STATS_NETIF_ADD(ni, ifoutoctets, value)
-#define snmp_inc_ifoutucastpkts(ni)    MIB2_STATS_NETIF_INC(ni, ifoutucastpkts)
-#define snmp_inc_ifoutnucastpkts(ni)   MIB2_STATS_NETIF_INC(ni, ifoutnucastpkts)
-#define snmp_inc_ifoutdiscards(ni)     MIB2_STATS_NETIF_INC(ni, ifoutdiscards)
-#define snmp_inc_ifouterrors(ni)       MIB2_STATS_NETIF_INC(ni, ifouterrors)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_SNMP_H */
diff --git a/tools/sdk/include/lwip/lwip/sockets.h b/tools/sdk/include/lwip/lwip/sockets.h
deleted file mode 100644
index eff3b42e46c..00000000000
--- a/tools/sdk/include/lwip/lwip/sockets.h
+++ /dev/null
@@ -1,738 +0,0 @@
-/**
- * @file
- * Socket API (to be used from non-TCPIP threads)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-
-#ifndef LWIP_HDR_SOCKETS_H
-#define LWIP_HDR_SOCKETS_H
-
-#include "lwip/opt.h"
-
-#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/ip_addr.h"
-#include "lwip/err.h"
-#include "lwip/inet.h"
-#include "lwip/errno.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* If your port already typedef's sa_family_t, define SA_FAMILY_T_DEFINED
-   to prevent this code from redefining it. */
-#if !defined(sa_family_t) && !defined(SA_FAMILY_T_DEFINED)
-typedef u8_t sa_family_t;
-#endif
-/* If your port already typedef's in_port_t, define IN_PORT_T_DEFINED
-   to prevent this code from redefining it. */
-#if !defined(in_port_t) && !defined(IN_PORT_T_DEFINED)
-typedef u16_t in_port_t;
-#endif
-
-#if LWIP_IPV4
-/* members are in network byte order */
-struct sockaddr_in {
-  u8_t            sin_len;
-  sa_family_t     sin_family;
-  in_port_t       sin_port;
-  struct in_addr  sin_addr;
-#define SIN_ZERO_LEN 8
-  char            sin_zero[SIN_ZERO_LEN];
-};
-#endif /* LWIP_IPV4 */
-
-#if LWIP_IPV6
-struct sockaddr_in6 {
-  u8_t            sin6_len;      /* length of this structure    */
-  sa_family_t     sin6_family;   /* AF_INET6                    */
-  in_port_t       sin6_port;     /* Transport layer port #      */
-  u32_t           sin6_flowinfo; /* IPv6 flow information       */
-  struct in6_addr sin6_addr;     /* IPv6 address                */
-  u32_t           sin6_scope_id; /* Set of interfaces for scope */
-};
-#endif /* LWIP_IPV6 */
-
-struct sockaddr {
-  u8_t        sa_len;
-  sa_family_t sa_family;
-  char        sa_data[14];
-};
-
-struct sockaddr_storage {
-  u8_t        s2_len;
-  sa_family_t ss_family;
-  char        s2_data1[2];
-  u32_t       s2_data2[3];
-#if LWIP_IPV6
-  u32_t       s2_data3[3];
-#endif /* LWIP_IPV6 */
-};
-
-/* If your port already typedef's socklen_t, define SOCKLEN_T_DEFINED
-   to prevent this code from redefining it. */
-#if !defined(socklen_t) && !defined(SOCKLEN_T_DEFINED)
-typedef u32_t socklen_t;
-#endif
-
-struct lwip_sock;
-
-#if !LWIP_TCPIP_CORE_LOCKING
-/** Maximum optlen used by setsockopt/getsockopt */
-#define LWIP_SETGETSOCKOPT_MAXOPTLEN 16
-
-/** This struct is used to pass data to the set/getsockopt_internal
- * functions running in tcpip_thread context (only a void* is allowed) */
-struct lwip_setgetsockopt_data {
-  /** socket index for which to change options */
-  int s;
-  /** level of the option to process */
-  int level;
-  /** name of the option to process */
-  int optname;
-  /** set: value to set the option to
-    * get: value of the option is stored here */
-#if LWIP_MPU_COMPATIBLE
-  u8_t optval[LWIP_SETGETSOCKOPT_MAXOPTLEN];
-#else
-  union {
-     void *p;
-     const void *pc;
-  } optval;
-#endif
-  /** size of *optval */
-  socklen_t optlen;
-  /** if an error occurs, it is temporarily stored here */
-  err_t err;
-  /** semaphore to wake up the calling task */
-  void* completed_sem;
-};
-#endif /* !LWIP_TCPIP_CORE_LOCKING */
-
-#if !defined(iovec)
-struct iovec {
-  void  *iov_base;
-  size_t iov_len;
-};
-#endif
-
-struct msghdr {
-  void         *msg_name;
-  socklen_t     msg_namelen;
-  struct iovec *msg_iov;
-  int           msg_iovlen;
-  void         *msg_control;
-  socklen_t     msg_controllen;
-  int           msg_flags;
-};
-
-/* Socket protocol types (TCP/UDP/RAW) */
-#define SOCK_STREAM     1
-#define SOCK_DGRAM      2
-#define SOCK_RAW        3
-
-/*
- * Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c)
- */
-#define SO_REUSEADDR   0x0004 /* Allow local address reuse */
-#define SO_KEEPALIVE   0x0008 /* keep connections alive */
-#define SO_BROADCAST   0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */
-
-
-/*
- * Additional options, not kept in so_options.
- */
-#define SO_DEBUG       0x0001 /* Unimplemented: turn on debugging info recording */
-#define SO_ACCEPTCONN  0x0002 /* socket has had listen() */
-#define SO_DONTROUTE   0x0010 /* Unimplemented: just use interface addresses */
-#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */
-#define SO_LINGER      0x0080 /* linger on close if data present */
-#define SO_DONTLINGER  ((int)(~SO_LINGER))
-#define SO_OOBINLINE   0x0100 /* Unimplemented: leave received OOB data in line */
-#define SO_REUSEPORT   0x0200 /* Unimplemented: allow local address & port reuse */
-#define SO_SNDBUF      0x1001 /* Unimplemented: send buffer size */
-#define SO_RCVBUF      0x1002 /* receive buffer size */
-#define SO_SNDLOWAT    0x1003 /* Unimplemented: send low-water mark */
-#define SO_RCVLOWAT    0x1004 /* Unimplemented: receive low-water mark */
-#define SO_SNDTIMEO    0x1005 /* send timeout */
-#define SO_RCVTIMEO    0x1006 /* receive timeout */
-#define SO_ERROR       0x1007 /* get error status and clear */
-#define SO_TYPE        0x1008 /* get socket type */
-#define SO_CONTIMEO    0x1009 /* Unimplemented: connect timeout */
-#define SO_NO_CHECK    0x100a /* don't create UDP checksum */
-
-
-/*
- * Structure used for manipulating linger option.
- */
-struct linger {
-       int l_onoff;                /* option on/off */
-       int l_linger;               /* linger time in seconds */
-};
-
-/*
- * Level number for (get/set)sockopt() to apply to socket itself.
- */
-#define  SOL_SOCKET  0xfff    /* options for socket level */
-
-
-#define AF_UNSPEC       0
-#define AF_INET         2
-#if LWIP_IPV6
-#define AF_INET6        10
-#else /* LWIP_IPV6 */
-#define AF_INET6        AF_UNSPEC
-#endif /* LWIP_IPV6 */
-#define PF_INET         AF_INET
-#define PF_INET6        AF_INET6
-#define PF_UNSPEC       AF_UNSPEC
-
-#define IPPROTO_IP      0
-#define IPPROTO_ICMP    1
-#define IPPROTO_TCP     6
-#define IPPROTO_UDP     17
-#if LWIP_IPV6
-#define IPPROTO_IPV6    41
-#define IPPROTO_ICMPV6  58
-#endif /* LWIP_IPV6 */
-#define IPPROTO_UDPLITE 136
-#define IPPROTO_RAW     255
-
-/* Flags we can use with send and recv. */
-#define MSG_PEEK       0x01    /* Peeks at an incoming message */
-#define MSG_WAITALL    0x02    /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */
-#define MSG_OOB        0x04    /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */
-#define MSG_DONTWAIT   0x08    /* Nonblocking i/o for this operation only */
-#define MSG_MORE       0x10    /* Sender will send more */
-
-
-/*
- * Options for level IPPROTO_IP
- */
-#define IP_TOS             1
-#define IP_TTL             2
-
-#if LWIP_TCP
-/*
- * Options for level IPPROTO_TCP
- */
-#define TCP_NODELAY    0x01    /* don't delay send to coalesce packets */
-#define TCP_KEEPALIVE  0x02    /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */
-#define TCP_KEEPIDLE   0x03    /* set pcb->keep_idle  - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */
-#define TCP_KEEPINTVL  0x04    /* set pcb->keep_intvl - Use seconds for get/setsockopt */
-#define TCP_KEEPCNT    0x05    /* set pcb->keep_cnt   - Use number of probes sent for get/setsockopt */
-#endif /* LWIP_TCP */
-
-#if LWIP_IPV6
-/*
- * Options for level IPPROTO_IPV6
- */
-#define IPV6_CHECKSUM       7  /* RFC3542: calculate and insert the ICMPv6 checksum for raw sockets. */
-#define IPV6_V6ONLY         27 /* RFC3493: boolean control to restrict AF_INET6 sockets to IPv6 communications only. */
-
-#if ESP_LWIP
-#if LWIP_IPV6_MLD
-/* Socket options for IPV6 multicast, uses the MLD interface to manage group memberships. RFC2133. */
-#define IPV6_MULTICAST_IF 0x300
-#define IPV6_MULTICAST_HOPS 0x301
-#define IPV6_MULTICAST_LOOP 0x302
-#define IPV6_ADD_MEMBERSHIP 0x303
-#define IPV6_DROP_MEMBERSHIP 0x304
-
-/* Structure used for IPV6_ADD/DROP_MEMBERSHIP */
-typedef struct ip6_mreq {
-    struct in6_addr ipv6mr_multiaddr; /* IPv6 multicast addr */
-    struct in6_addr ipv6mr_interface; /* local IP address of interface */
-} ip6_mreq;
-
-/* Commonly used synonyms for these options */
-#define IPV6_JOIN_GROUP IPV6_ADD_MEMBERSHIP
-#define IPV6_LEAVE_GROUP IPV6_DROP_MEMBERSHIP
-
-#endif /* LWIP_IPV6_MLD */
-#endif
-
-#endif /* LWIP_IPV6 */
-
-#if LWIP_UDP && LWIP_UDPLITE
-/*
- * Options for level IPPROTO_UDPLITE
- */
-#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */
-#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */
-#endif /* LWIP_UDP && LWIP_UDPLITE*/
-
-
-#if LWIP_MULTICAST_TX_OPTIONS
-/*
- * Options and types for UDP multicast traffic handling
- */
-#define IP_MULTICAST_TTL   5
-#define IP_MULTICAST_IF    6
-#define IP_MULTICAST_LOOP  7
-#endif /* LWIP_MULTICAST_TX_OPTIONS */
-
-#if LWIP_IGMP
-/*
- * Options and types related to multicast membership
- */
-#define IP_ADD_MEMBERSHIP  3
-#define IP_DROP_MEMBERSHIP 4
-
-typedef struct ip_mreq {
-    struct in_addr imr_multiaddr; /* IP multicast address of group */
-    struct in_addr imr_interface; /* local IP address of interface */
-} ip_mreq;
-#endif /* LWIP_IGMP */
-
-/*
- * The Type of Service provides an indication of the abstract
- * parameters of the quality of service desired.  These parameters are
- * to be used to guide the selection of the actual service parameters
- * when transmitting a datagram through a particular network.  Several
- * networks offer service precedence, which somehow treats high
- * precedence traffic as more important than other traffic (generally
- * by accepting only traffic above a certain precedence at time of high
- * load).  The major choice is a three way tradeoff between low-delay,
- * high-reliability, and high-throughput.
- * The use of the Delay, Throughput, and Reliability indications may
- * increase the cost (in some sense) of the service.  In many networks
- * better performance for one of these parameters is coupled with worse
- * performance on another.  Except for very unusual cases at most two
- * of these three indications should be set.
- */
-#define IPTOS_TOS_MASK          0x1E
-#define IPTOS_TOS(tos)          ((tos) & IPTOS_TOS_MASK)
-#define IPTOS_LOWDELAY          0x10
-#define IPTOS_THROUGHPUT        0x08
-#define IPTOS_RELIABILITY       0x04
-#define IPTOS_LOWCOST           0x02
-#define IPTOS_MINCOST           IPTOS_LOWCOST
-
-/*
- * The Network Control precedence designation is intended to be used
- * within a network only.  The actual use and control of that
- * designation is up to each network. The Internetwork Control
- * designation is intended for use by gateway control originators only.
- * If the actual use of these precedence designations is of concern to
- * a particular network, it is the responsibility of that network to
- * control the access to, and use of, those precedence designations.
- */
-#define IPTOS_PREC_MASK                 0xe0
-#define IPTOS_PREC(tos)                ((tos) & IPTOS_PREC_MASK)
-#define IPTOS_PREC_NETCONTROL           0xe0
-#define IPTOS_PREC_INTERNETCONTROL      0xc0
-#define IPTOS_PREC_CRITIC_ECP           0xa0
-#define IPTOS_PREC_FLASHOVERRIDE        0x80
-#define IPTOS_PREC_FLASH                0x60
-#define IPTOS_PREC_IMMEDIATE            0x40
-#define IPTOS_PREC_PRIORITY             0x20
-#define IPTOS_PREC_ROUTINE              0x00
-
-
-/*
- * Commands for ioctlsocket(),  taken from the BSD file fcntl.h.
- * lwip_ioctl only supports FIONREAD and FIONBIO, for now
- *
- * Ioctl's have the command encoded in the lower word,
- * and the size of any in or out parameters in the upper
- * word.  The high 2 bits of the upper word are used
- * to encode the in/out status of the parameter; for now
- * we restrict parameters to at most 128 bytes.
- */
-#if !defined(FIONREAD) || !defined(FIONBIO)
-#define IOCPARM_MASK    0x7fU           /* parameters must be < 128 bytes */
-#define IOC_VOID        0x20000000UL    /* no parameters */
-#define IOC_OUT         0x40000000UL    /* copy out parameters */
-#define IOC_IN          0x80000000UL    /* copy in parameters */
-#define IOC_INOUT       (IOC_IN|IOC_OUT)
-                                        /* 0x20000000 distinguishes new &
-                                           old ioctl's */
-#define _IO(x,y)        (IOC_VOID|((x)<<8)|(y))
-
-#define _IOR(x,y,t)     (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
-
-#define _IOW(x,y,t)     (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))
-#endif /* !defined(FIONREAD) || !defined(FIONBIO) */
-
-#ifndef FIONREAD
-#define FIONREAD    _IOR('f', 127, unsigned long) /* get # bytes to read */
-#endif
-#ifndef FIONBIO
-#define FIONBIO     _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */
-#endif
-
-/* Socket I/O Controls: unimplemented */
-#ifndef SIOCSHIWAT
-#define SIOCSHIWAT  _IOW('s',  0, unsigned long)  /* set high watermark */
-#define SIOCGHIWAT  _IOR('s',  1, unsigned long)  /* get high watermark */
-#define SIOCSLOWAT  _IOW('s',  2, unsigned long)  /* set low watermark */
-#define SIOCGLOWAT  _IOR('s',  3, unsigned long)  /* get low watermark */
-#define SIOCATMARK  _IOR('s',  7, unsigned long)  /* at oob mark? */
-#endif
-
-/* commands for fnctl */
-#ifndef F_GETFL
-#define F_GETFL 3
-#endif
-#ifndef F_SETFL
-#define F_SETFL 4
-#endif
-
-/* File status flags and file access modes for fnctl,
-   these are bits in an int. */
-#ifndef O_NONBLOCK
-#define O_NONBLOCK  1 /* nonblocking I/O */
-#endif
-#ifndef O_NDELAY
-#define O_NDELAY    1 /* same as O_NONBLOCK, for compatibility */
-#endif
-
-#ifndef SHUT_RD
-  #define SHUT_RD   0
-  #define SHUT_WR   1
-  #define SHUT_RDWR 2
-#endif
-
-/* FD_SET used for lwip_select */
-#ifndef FD_SET
-#undef  FD_SETSIZE
-/* Make FD_SETSIZE match NUM_SOCKETS in socket.c */
-#define FD_SETSIZE    MEMP_NUM_NETCONN
-#define FDSETSAFESET(n, code) do { \
-  if (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0)) { \
-  code; }} while(0)
-#define FDSETSAFEGET(n, code) (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0) ?\
-  (code) : 0)
-#define FD_SET(n, p)  FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] |=  (1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))
-#define FD_CLR(n, p)  FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] &= ~(1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))
-#define FD_ISSET(n,p) FDSETSAFEGET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] &   (1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))
-#define FD_ZERO(p)    memset((void*)(p), 0, sizeof(*(p)))
-
-typedef struct fd_set
-{
-  unsigned char fd_bits [(FD_SETSIZE+7)/8];
-} fd_set;
-
-#endif /* FD_SET */
-
-/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided
- * by your system, set this to 0 and include <sys/time.h> in cc.h */
-#ifndef LWIP_TIMEVAL_PRIVATE
-#define LWIP_TIMEVAL_PRIVATE 1
-#endif
-
-#if LWIP_TIMEVAL_PRIVATE
-struct timeval {
-  long    tv_sec;         /* seconds */
-  long    tv_usec;        /* and microseconds */
-};
-#endif /* LWIP_TIMEVAL_PRIVATE */
-
-#define lwip_socket_init() /* Compatibility define, no init needed. */
-void lwip_socket_thread_init(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */
-void lwip_socket_thread_cleanup(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */
-
-#if LWIP_COMPAT_SOCKETS == 2
-/* This helps code parsers/code completion by not having the COMPAT functions as defines */
-#define lwip_accept       accept
-#define lwip_bind         bind
-#define lwip_shutdown     shutdown
-#define lwip_getpeername  getpeername
-#define lwip_getsockname  getsockname
-#define lwip_setsockopt   setsockopt
-#define lwip_getsockopt   getsockopt
-#define lwip_close        closesocket
-#define lwip_connect      connect
-#define lwip_listen       listen
-#define lwip_recv         recv
-#define lwip_recvfrom     recvfrom
-#define lwip_send         send
-#define lwip_sendmsg      sendmsg
-#define lwip_sendto       sendto
-#define lwip_socket       socket
-#define lwip_select       select
-#define lwip_ioctlsocket  ioctl
-
-#if LWIP_POSIX_SOCKETS_IO_NAMES
-#define lwip_read         read
-#define lwip_write        write
-#define lwip_writev       writev
-#undef lwip_close
-#define lwip_close        close
-#define closesocket(s)    close(s)
-#define lwip_fcntl        fcntl
-#define lwip_ioctl        ioctl
-#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
-#endif /* LWIP_COMPAT_SOCKETS == 2 */
-
-int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
-int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen);
-int lwip_shutdown(int s, int how);
-int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen);
-int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen);
-int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen);
-int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen);
-int lwip_close(int s);
-int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen);
-int lwip_listen(int s, int backlog);
-int lwip_recv(int s, void *mem, size_t len, int flags);
-int lwip_read(int s, void *mem, size_t len);
-int lwip_recvfrom(int s, void *mem, size_t len, int flags,
-      struct sockaddr *from, socklen_t *fromlen);
-int lwip_send(int s, const void *dataptr, size_t size, int flags);
-int lwip_sendmsg(int s, const struct msghdr *message, int flags);
-int lwip_sendto(int s, const void *dataptr, size_t size, int flags,
-    const struct sockaddr *to, socklen_t tolen);
-int lwip_socket(int domain, int type, int protocol);
-int lwip_write(int s, const void *dataptr, size_t size);
-int lwip_writev(int s, const struct iovec *iov, int iovcnt);
-int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
-                struct timeval *timeout);
-int lwip_ioctl(int s, long cmd, void *argp);
-int lwip_fcntl(int s, int cmd, int val);
-
-#if LWIP_COMPAT_SOCKETS
-#if LWIP_COMPAT_SOCKETS != 2
-
-#if ESP_THREAD_SAFE
-
-int lwip_accept_r(int s, struct sockaddr *addr, socklen_t *addrlen);
-int lwip_bind_r(int s, const struct sockaddr *name, socklen_t namelen);
-int lwip_shutdown_r(int s, int how);
-int lwip_getpeername_r (int s, struct sockaddr *name, socklen_t *namelen);
-int lwip_getsockname_r (int s, struct sockaddr *name, socklen_t *namelen);
-int lwip_getsockopt_r (int s, int level, int optname, void *optval, socklen_t *optlen);
-int lwip_setsockopt_r (int s, int level, int optname, const void *optval, socklen_t optlen);
-int lwip_close_r(int s);
-int lwip_connect_r(int s, const struct sockaddr *name, socklen_t namelen);
-int lwip_listen_r(int s, int backlog);
-int lwip_recvmsg_r(int s, struct msghdr *message, int flags);
-int lwip_recv_r(int s, void *mem, size_t len, int flags);
-int lwip_read_r(int s, void *mem, size_t len); 
-int lwip_recvfrom_r(int s, void *mem, size_t len, int flags,
-      struct sockaddr *from, socklen_t *fromlen);
-int lwip_send_r(int s, const void *dataptr, size_t size, int flags);
-int lwip_sendmsg_r(int s, const struct msghdr *message, int flags);
-int lwip_sendto_r(int s, const void *dataptr, size_t size, int flags,
-    const struct sockaddr *to, socklen_t tolen);
-int lwip_socket(int domain, int type, int protocol);
-int lwip_write_r(int s, const void *dataptr, size_t size);
-int lwip_writev_r(int s, const struct iovec *iov, int iovcnt);
-int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset,
-                struct timeval *timeout);
-int lwip_ioctl_r(int s, long cmd, void *argp);
-int lwip_fcntl_r(int s, int cmd, int val);
-
-static inline int accept(int s,struct sockaddr *addr,socklen_t *addrlen)
-{ return lwip_accept_r(s,addr,addrlen); }
-static inline int bind(int s,const struct sockaddr *name, socklen_t namelen)
-{ return lwip_bind_r(s,name,namelen); }
-static inline int shutdown(int s,int how)
-{ return lwip_shutdown_r(s,how); }
-static inline int getpeername(int s,struct sockaddr *name,socklen_t *namelen)
-{ return lwip_getpeername_r(s,name,namelen); }
-static inline int getsockname(int s,struct sockaddr *name,socklen_t *namelen)
-{ return lwip_getsockname_r(s,name,namelen); }
-static inline int setsockopt(int s,int level,int optname,const void *opval,socklen_t optlen)
-{ return lwip_setsockopt_r(s,level,optname,opval,optlen); }
-static inline int getsockopt(int s,int level,int optname,void *opval,socklen_t *optlen)
-{ return lwip_getsockopt_r(s,level,optname,opval,optlen); }
-static inline int closesocket(int s)
-{ return lwip_close_r(s); }
-static inline int connect(int s,const struct sockaddr *name,socklen_t namelen)
-{ return lwip_connect_r(s,name,namelen); }
-static inline int listen(int s,int backlog)
-{ return lwip_listen_r(s,backlog); }
-static inline int recvmsg(int sockfd, struct msghdr *msg, int flags)
-{ return lwip_recvmsg_r(sockfd, msg, flags); } 
-static inline int recv(int s,void *mem,size_t len,int flags)
-{ return lwip_recv_r(s,mem,len,flags); }
-static inline int recvfrom(int s,void *mem,size_t len,int flags,struct sockaddr *from,socklen_t *fromlen)
-{ return lwip_recvfrom_r(s,mem,len,flags,from,fromlen); }
-static inline int send(int s,const void *dataptr,size_t size,int flags)
-{ return lwip_send_r(s,dataptr,size,flags); }
-static inline int sendmsg(int s,const struct msghdr *message,int flags)
-{ return lwip_sendmsg_r(s,message,flags); }
-static inline int sendto(int s,const void *dataptr,size_t size,int flags,const struct sockaddr *to,socklen_t tolen)
-{ return lwip_sendto_r(s,dataptr,size,flags,to,tolen); }
-static inline int socket(int domain,int type,int protocol)
-{ return lwip_socket(domain,type,protocol); }
-#ifndef ESP_HAS_SELECT
-static inline int select(int maxfdp1,fd_set *readset,fd_set *writeset,fd_set *exceptset,struct timeval *timeout)
-{ return lwip_select(maxfdp1,readset,writeset,exceptset,timeout); }
-#endif /* ESP_HAS_SELECT */
-static inline int ioctlsocket(int s,long cmd,void *argp)
-{ return lwip_ioctl_r(s,cmd,argp); }
-
-#if LWIP_POSIX_SOCKETS_IO_NAMES
-static inline int read(int s,void *mem,size_t len)
-{ return lwip_read_r(s,mem,len); }
-static inline int write(int s,const void *dataptr,size_t len)
-{ return lwip_write_r(s,dataptr,len); }
-static inline int writev(int s,const struct iovec *iov,int iovcnt)
-{ return lwip_writev_r(s,iov,iovcnt); }
-static inline int close(int s)
-{ return lwip_close_r(s); }
-static inline int fcntl(int s,int cmd,int val)
-{ return lwip_fcntl_r(s,cmd,val); }
-static inline int ioctl(int s,long cmd,void *argp)
-{ return lwip_ioctl_r(s,cmd,argp); }
-#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
-
-#else
-
-/** @ingroup socket */
-#define accept(s,addr,addrlen)                    lwip_accept(s,addr,addrlen)
-/** @ingroup socket */
-#define bind(s,name,namelen)                      lwip_bind(s,name,namelen)
-/** @ingroup socket */
-#define shutdown(s,how)                           lwip_shutdown(s,how)
-/** @ingroup socket */
-#define getpeername(s,name,namelen)               lwip_getpeername(s,name,namelen)
-/** @ingroup socket */
-#define getsockname(s,name,namelen)               lwip_getsockname(s,name,namelen)
-/** @ingroup socket */
-#define setsockopt(s,level,optname,opval,optlen)  lwip_setsockopt(s,level,optname,opval,optlen)
-/** @ingroup socket */
-#define getsockopt(s,level,optname,opval,optlen)  lwip_getsockopt(s,level,optname,opval,optlen)
-/** @ingroup socket */
-#define closesocket(s)                            lwip_close(s)
-/** @ingroup socket */
-#define connect(s,name,namelen)                   lwip_connect(s,name,namelen)
-/** @ingroup socket */
-#define listen(s,backlog)                         lwip_listen(s,backlog)
-/** @ingroup socket */
-#define recv(s,mem,len,flags)                     lwip_recv(s,mem,len,flags)
-/** @ingroup socket */
-#define recvfrom(s,mem,len,flags,from,fromlen)    lwip_recvfrom(s,mem,len,flags,from,fromlen)
-/** @ingroup socket */
-#define send(s,dataptr,size,flags)                lwip_send(s,dataptr,size,flags)
-/** @ingroup socket */
-#define sendmsg(s,message,flags)                  lwip_sendmsg(s,message,flags)
-/** @ingroup socket */
-#define sendto(s,dataptr,size,flags,to,tolen)     lwip_sendto(s,dataptr,size,flags,to,tolen)
-/** @ingroup socket */
-#define socket(domain,type,protocol)              lwip_socket(domain,type,protocol)
-/** @ingroup socket */
-#define select(maxfdp1,readset,writeset,exceptset,timeout)     lwip_select(maxfdp1,readset,writeset,exceptset,timeout)
-/** @ingroup socket */
-#define ioctlsocket(s,cmd,argp)                   lwip_ioctl(s,cmd,argp)
-
-#if LWIP_POSIX_SOCKETS_IO_NAMES
-/** @ingroup socket */
-#define read(s,mem,len)                           lwip_read(s,mem,len)
-/** @ingroup socket */
-#define write(s,dataptr,len)                      lwip_write(s,dataptr,len)
-/** @ingroup socket */
-#define writev(s,iov,iovcnt)                      lwip_writev(s,iov,iovcnt)
-/** @ingroup socket */
-#define close(s)                                  lwip_close(s)
-/** @ingroup socket */
-#define fcntl(s,cmd,val)                          lwip_fcntl(s,cmd,val)
-/** @ingroup socket */
-#define ioctl(s,cmd,argp)                         lwip_ioctl(s,cmd,argp)
-#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */
-
-#endif /* ESP_THREAD_SAFE */
-#endif /* LWIP_COMPAT_SOCKETS != 2 */
-
-#if ESP_LWIP
-#if LWIP_IPV4 && LWIP_IPV6
-#define lwip_inet_ntop(af,src,dst,size) \
-    (((af) == AF_INET6) ? ip6addr_ntoa_r((const ip6_addr_t*)(src),(dst),(size)) \
-    : (((af) == AF_INET) ? ip4addr_ntoa_r((const ip4_addr_t*)(src),(dst),(size)) : NULL))
-#define lwip_inet_pton(af,src,dst) \
-    (((af) == AF_INET6) ? ip6addr_aton((src),(ip6_addr_t*)(dst)) \
-    : (((af) == AF_INET) ? ip4addr_aton((src),(ip4_addr_t*)(dst)) : 0))
-#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
-#define lwip_inet_ntop(af,src,dst,size) \
-    (((af) == AF_INET) ? ip4addr_ntoa_r((const ip4_addr_t*)(src),(dst),(size)) : NULL)
-#define lwip_inet_pton(af,src,dst) \
-    (((af) == AF_INET) ? ip4addr_aton((src),(ip4_addr_t*)(dst)) : 0)
-#else /* LWIP_IPV4 && LWIP_IPV6 */
-#define lwip_inet_ntop(af,src,dst,size) \
-    (((af) == AF_INET6) ? ip6addr_ntoa_r((const ip6_addr_t*)(src),(dst),(size)) : NULL)
-#define lwip_inet_pton(af,src,dst) \
-    (((af) == AF_INET6) ? ip6addr_aton((src),(ip6_addr_t*)(dst)) : 0)
-#endif /* LWIP_IPV4 && LWIP_IPV6 */
-                                                           
-#if LWIP_COMPAT_SOCKET_INET == 1
-/* Some libraries have problems with inet_... being macros, so please use this define 
-   to declare normal functions */
-static inline const char *inet_ntop(int af, const void *src, char *dst, socklen_t size)
-{ lwip_inet_ntop(af, src, dst, size);    return dst; }
-static inline int inet_pton(int af, const char *src, void *dst)
-{ lwip_inet_pton(af, src, dst); return 1; }   
-#else
-/* By default fall back to original inet_... macros */
-# define inet_ntop(a,b,c,d) lwip_inet_ntop(a,b,c,d) 
-# define inet_pton(a,b,c)   lwip_inet_pton(a,b,c)   
-#endif /* LWIP_COMPAT_SOCKET_INET */
-
-#else /* ESP_LWIP*/
-
-#if LWIP_IPV4 && LWIP_IPV6
-/** @ingroup socket */
-#define inet_ntop(af,src,dst,size) \
-    (((af) == AF_INET6) ? ip6addr_ntoa_r((const ip6_addr_t*)(src),(dst),(size)) \
-     : (((af) == AF_INET) ? ip4addr_ntoa_r((const ip4_addr_t*)(src),(dst),(size)) : NULL))
-/** @ingroup socket */
-#define inet_pton(af,src,dst) \
-    (((af) == AF_INET6) ? ip6addr_aton((src),(ip6_addr_t*)(dst)) \
-     : (((af) == AF_INET) ? ip4addr_aton((src),(ip4_addr_t*)(dst)) : 0))
-#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */
-#define inet_ntop(af,src,dst,size) \
-    (((af) == AF_INET) ? ip4addr_ntoa_r((const ip4_addr_t*)(src),(dst),(size)) : NULL)
-#define inet_pton(af,src,dst) \
-    (((af) == AF_INET) ? ip4addr_aton((src),(ip4_addr_t*)(dst)) : 0)
-#else /* LWIP_IPV4 && LWIP_IPV6 */
-#define inet_ntop(af,src,dst,size) \
-    (((af) == AF_INET6) ? ip6addr_ntoa_r((const ip6_addr_t*)(src),(dst),(size)) : NULL)
-#define inet_pton(af,src,dst) \
-    (((af) == AF_INET6) ? ip6addr_aton((src),(ip6_addr_t*)(dst)) : 0)
-#endif /* LWIP_IPV4 && LWIP_IPV6 */
-
-#endif /* ESP_LWIP */
-#endif /* LWIP_COMPAT_SOCKETS */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_SOCKET */
-
-#endif /* LWIP_HDR_SOCKETS_H */
diff --git a/tools/sdk/include/lwip/lwip/stats.h b/tools/sdk/include/lwip/lwip/stats.h
deleted file mode 100644
index e883383feff..00000000000
--- a/tools/sdk/include/lwip/lwip/stats.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/**
- * @file
- * Statistics API (to be used from TCPIP thread)
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_STATS_H
-#define LWIP_HDR_STATS_H
-
-#include "lwip/opt.h"
-
-#include "lwip/mem.h"
-#include "lwip/memp.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_STATS
-
-#ifndef LWIP_STATS_LARGE
-#define LWIP_STATS_LARGE 0
-#endif
-
-#if LWIP_STATS_LARGE
-#define STAT_COUNTER     u32_t
-#define STAT_COUNTER_F   U32_F
-#else
-#define STAT_COUNTER     u16_t
-#define STAT_COUNTER_F   U16_F
-#endif
-
-/** Protocol related stats */
-struct stats_proto {
-  STAT_COUNTER xmit;             /* Transmitted packets. */
-  STAT_COUNTER recv;             /* Received packets. */
-  STAT_COUNTER fw;               /* Forwarded packets. */
-  STAT_COUNTER drop;             /* Dropped packets. */
-  STAT_COUNTER chkerr;           /* Checksum error. */
-  STAT_COUNTER lenerr;           /* Invalid length error. */
-  STAT_COUNTER memerr;           /* Out of memory error. */
-  STAT_COUNTER rterr;            /* Routing error. */
-  STAT_COUNTER proterr;          /* Protocol error. */
-  STAT_COUNTER opterr;           /* Error in options. */
-  STAT_COUNTER err;              /* Misc error. */
-  STAT_COUNTER cachehit;
-};
-
-/** IGMP stats */
-struct stats_igmp {
-  STAT_COUNTER xmit;             /* Transmitted packets. */
-  STAT_COUNTER recv;             /* Received packets. */
-  STAT_COUNTER drop;             /* Dropped packets. */
-  STAT_COUNTER chkerr;           /* Checksum error. */
-  STAT_COUNTER lenerr;           /* Invalid length error. */
-  STAT_COUNTER memerr;           /* Out of memory error. */
-  STAT_COUNTER proterr;          /* Protocol error. */
-  STAT_COUNTER rx_v1;            /* Received v1 frames. */
-  STAT_COUNTER rx_group;         /* Received group-specific queries. */
-  STAT_COUNTER rx_general;       /* Received general queries. */
-  STAT_COUNTER rx_report;        /* Received reports. */
-  STAT_COUNTER tx_join;          /* Sent joins. */
-  STAT_COUNTER tx_leave;         /* Sent leaves. */
-  STAT_COUNTER tx_report;        /* Sent reports. */
-};
-
-/** Memory stats */
-struct stats_mem {
-#if defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY
-  const char *name;
-#endif /* defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY */
-  STAT_COUNTER err;
-  mem_size_t avail;
-  mem_size_t used;
-  mem_size_t max;
-  STAT_COUNTER illegal;
-};
-
-/** System element stats */
-struct stats_syselem {
-  STAT_COUNTER used;
-  STAT_COUNTER max;
-  STAT_COUNTER err;
-};
-
-/** System stats */
-struct stats_sys {
-  struct stats_syselem sem;
-  struct stats_syselem mutex;
-  struct stats_syselem mbox;
-};
-
-/** SNMP MIB2 stats */
-struct stats_mib2 {
-  /* IP */
-  u32_t ipinhdrerrors;
-  u32_t ipinaddrerrors;
-  u32_t ipinunknownprotos;
-  u32_t ipindiscards;
-  u32_t ipindelivers;
-  u32_t ipoutrequests;
-  u32_t ipoutdiscards;
-  u32_t ipoutnoroutes;
-  u32_t ipreasmoks;
-  u32_t ipreasmfails;
-  u32_t ipfragoks;
-  u32_t ipfragfails;
-  u32_t ipfragcreates;
-  u32_t ipreasmreqds;
-  u32_t ipforwdatagrams;
-  u32_t ipinreceives;
-
-  /* TCP */
-  u32_t tcpactiveopens;
-  u32_t tcppassiveopens;
-  u32_t tcpattemptfails;
-  u32_t tcpestabresets;
-  u32_t tcpoutsegs;
-  u32_t tcpretranssegs;
-  u32_t tcpinsegs;
-  u32_t tcpinerrs;
-  u32_t tcpoutrsts;
-
-  /* UDP */
-  u32_t udpindatagrams;
-  u32_t udpnoports;
-  u32_t udpinerrors;
-  u32_t udpoutdatagrams;
-
-  /* ICMP */
-  u32_t icmpinmsgs;
-  u32_t icmpinerrors;
-  u32_t icmpindestunreachs;
-  u32_t icmpintimeexcds;
-  u32_t icmpinparmprobs;
-  u32_t icmpinsrcquenchs;
-  u32_t icmpinredirects;
-  u32_t icmpinechos;
-  u32_t icmpinechoreps;
-  u32_t icmpintimestamps;
-  u32_t icmpintimestampreps;
-  u32_t icmpinaddrmasks;
-  u32_t icmpinaddrmaskreps;
-  u32_t icmpoutmsgs;
-  u32_t icmpouterrors;
-  u32_t icmpoutdestunreachs;
-  u32_t icmpouttimeexcds;
-  u32_t icmpoutechos; /* can be incremented by user application ('ping') */
-  u32_t icmpoutechoreps;
-};
-
-/**
- * @ingroup netif_mib2
- * SNMP MIB2 interface stats
- */
-struct stats_mib2_netif_ctrs {
-  /** The total number of octets received on the interface, including framing characters */
-  u32_t ifinoctets;
-  /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were
-   * not addressed to a multicast or broadcast address at this sub-layer */
-  u32_t ifinucastpkts;
-  /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were
-   * addressed to a multicast or broadcast address at this sub-layer */
-  u32_t ifinnucastpkts;
-  /** The number of inbound packets which were chosen to be discarded even though no errors had
-   * been detected to prevent their being deliverable to a higher-layer protocol. One possible
-   * reason for discarding such a packet could be to free up buffer space */
-  u32_t ifindiscards;
-  /** For packet-oriented interfaces, the number of inbound packets that contained errors
-   * preventing them from being deliverable to a higher-layer protocol.  For character-
-   * oriented or fixed-length interfaces, the number of inbound transmission units that
-   * contained errors preventing them from being deliverable to a higher-layer protocol. */
-  u32_t ifinerrors;
-  /** For packet-oriented interfaces, the number of packets received via the interface which
-   * were discarded because of an unknown or unsupported protocol.  For character-oriented
-   * or fixed-length interfaces that support protocol multiplexing the number of transmission
-   * units received via the interface which were discarded because of an unknown or unsupported
-   * protocol. For any interface that does not support protocol multiplexing, this counter will
-   * always be 0 */
-  u32_t ifinunknownprotos;
-  /** The total number of octets transmitted out of the interface, including framing characters. */
-  u32_t ifoutoctets;
-  /** The total number of packets that higher-level protocols requested be transmitted, and
-   * which were not addressed to a multicast or broadcast address at this sub-layer, including
-   * those that were discarded or not sent. */
-  u32_t ifoutucastpkts;
-  /** The total number of packets that higher-level protocols requested be transmitted, and which
-   * were addressed to a multicast or broadcast address at this sub-layer, including
-   * those that were discarded or not sent. */
-  u32_t ifoutnucastpkts;
-  /** The number of outbound packets which were chosen to be discarded even though no errors had
-   * been detected to prevent their being transmitted.  One possible reason for discarding
-   * such a packet could be to free up buffer space. */
-  u32_t ifoutdiscards;
-  /** For packet-oriented interfaces, the number of outbound packets that could not be transmitted
-   * because of errors. For character-oriented or fixed-length interfaces, the number of outbound
-   * transmission units that could not be transmitted because of errors. */
-  u32_t ifouterrors;
-};
-
-#if ESP_STATS_DROP
-struct stats_esp {
-    /* mbox post fail stats */
-    u32_t  rx_rawmbox_post_fail;
-    u32_t  rx_udpmbox_post_fail;
-    u32_t  rx_tcpmbox_post_fail;
-    u32_t  err_tcp_rxmbox_post_fail;
-    u32_t  err_tcp_acceptmbox_post_fail;
-    u32_t  acceptmbox_post_fail;
-    u32_t  free_mbox_post_fail;
-    u32_t  tcpip_inpkt_post_fail;
-    u32_t  tcpip_cb_post_fail;
-
-    /* memory malloc/free/failed stats */
-    u32_t  wlanif_input_pbuf_fail;
-    u32_t  wlanif_outut_pbuf_fail;
-};
-#endif
-
-/** lwIP stats container */
-struct stats_ {
-#if LINK_STATS
-  /** Link level */
-  struct stats_proto link;
-#endif
-#if ETHARP_STATS
-  /** ARP */
-  struct stats_proto etharp;
-#endif
-#if IPFRAG_STATS
-  /** Fragmentation */
-  struct stats_proto ip_frag;
-#endif
-#if IP_STATS
-  /** IP */
-  struct stats_proto ip;
-#endif
-#if ICMP_STATS
-  /** ICMP */
-  struct stats_proto icmp;
-#endif
-#if IGMP_STATS
-  /** IGMP */
-  struct stats_igmp igmp;
-#endif
-#if UDP_STATS
-  /** UDP */
-  struct stats_proto udp;
-#endif
-#if TCP_STATS
-  /** TCP */
-  struct stats_proto tcp;
-#endif
-#if MEM_STATS
-  /** Heap */
-  struct stats_mem mem;
-#endif
-#if MEMP_STATS
-  /** Internal memory pools */
-  struct stats_mem *memp[MEMP_MAX];
-#endif
-#if SYS_STATS
-  /** System */
-  struct stats_sys sys;
-#endif
-#if IP6_STATS
-  /** IPv6 */
-  struct stats_proto ip6;
-#endif
-#if ICMP6_STATS
-  /** ICMP6 */
-  struct stats_proto icmp6;
-#endif
-#if IP6_FRAG_STATS
-  /** IPv6 fragmentation */
-  struct stats_proto ip6_frag;
-#endif
-#if MLD6_STATS
-  /** Multicast listener discovery */
-  struct stats_igmp mld6;
-#endif
-#if ND6_STATS
-  /** Neighbor discovery */
-  struct stats_proto nd6;
-#endif
-#if MIB2_STATS
-  /** SNMP MIB2 */
-  struct stats_mib2 mib2;
-#endif
-
-#if ESP_STATS_DROP
-  struct stats_esp esp;
-#endif
-};
-
-/** Global variable containing lwIP internal statistics. Add this to your debugger's watchlist. */
-extern struct stats_ lwip_stats;
-
-/** Init statistics */
-void stats_init(void);
-
-#define STATS_INC(x) ++lwip_stats.x
-#define STATS_DEC(x) --lwip_stats.x
-#define STATS_INC_USED(x, y) do { lwip_stats.x.used += y; \
-                                if (lwip_stats.x.max < lwip_stats.x.used) { \
-                                    lwip_stats.x.max = lwip_stats.x.used; \
-                                } \
-                             } while(0)
-#define STATS_GET(x) lwip_stats.x
-#else /* LWIP_STATS */
-#define stats_init()
-#define STATS_INC(x)
-#define STATS_DEC(x)
-#define STATS_INC_USED(x)
-#endif /* LWIP_STATS */
-
-#if TCP_STATS
-#define TCP_STATS_INC(x) STATS_INC(x)
-#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP")
-#else
-#define TCP_STATS_INC(x)
-#define TCP_STATS_DISPLAY()
-#endif
-
-#if UDP_STATS
-#define UDP_STATS_INC(x) STATS_INC(x)
-#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP")
-#else
-#define UDP_STATS_INC(x)
-#define UDP_STATS_DISPLAY()
-#endif
-
-#if ICMP_STATS
-#define ICMP_STATS_INC(x) STATS_INC(x)
-#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP")
-#else
-#define ICMP_STATS_INC(x)
-#define ICMP_STATS_DISPLAY()
-#endif
-
-#if IGMP_STATS
-#define IGMP_STATS_INC(x) STATS_INC(x)
-#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp, "IGMP")
-#else
-#define IGMP_STATS_INC(x)
-#define IGMP_STATS_DISPLAY()
-#endif
-
-#if IP_STATS
-#define IP_STATS_INC(x) STATS_INC(x)
-#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP")
-#else
-#define IP_STATS_INC(x)
-#define IP_STATS_DISPLAY()
-#endif
-
-#if IPFRAG_STATS
-#define IPFRAG_STATS_INC(x) STATS_INC(x)
-#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG")
-#else
-#define IPFRAG_STATS_INC(x)
-#define IPFRAG_STATS_DISPLAY()
-#endif
-
-#if ETHARP_STATS
-#define ETHARP_STATS_INC(x) STATS_INC(x)
-#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP")
-#else
-#define ETHARP_STATS_INC(x)
-#define ETHARP_STATS_DISPLAY()
-#endif
-
-#if LINK_STATS
-#define LINK_STATS_INC(x) STATS_INC(x)
-#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK")
-#else
-#define LINK_STATS_INC(x)
-#define LINK_STATS_DISPLAY()
-#endif
-
-#if MEM_STATS
-#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y
-#define MEM_STATS_INC(x) SYS_ARCH_INC(lwip_stats.mem.x, 1)
-#define MEM_STATS_INC_USED(x, y) SYS_ARCH_INC(lwip_stats.mem.x, y)
-#define MEM_STATS_DEC_USED(x, y) SYS_ARCH_DEC(lwip_stats.mem.x, y)
-#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP")
-#else
-#define MEM_STATS_AVAIL(x, y)
-#define MEM_STATS_INC(x)
-#define MEM_STATS_INC_USED(x, y)
-#define MEM_STATS_DEC_USED(x, y)
-#define MEM_STATS_DISPLAY()
-#endif
-
- #if MEMP_STATS
-#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i]->x)
-#define MEMP_STATS_DISPLAY(i) stats_display_memp(lwip_stats.memp[i], i)
-#define MEMP_STATS_GET(x, i) STATS_GET(memp[i]->x)
- #else
-#define MEMP_STATS_DEC(x, i)
-#define MEMP_STATS_DISPLAY(i)
-#define MEMP_STATS_GET(x, i) 0
-#endif
-
-#if SYS_STATS
-#define SYS_STATS_INC(x) STATS_INC(sys.x)
-#define SYS_STATS_DEC(x) STATS_DEC(sys.x)
-#define SYS_STATS_INC_USED(x) STATS_INC_USED(sys.x, 1)
-#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys)
-#else
-#define SYS_STATS_INC(x)
-#define SYS_STATS_DEC(x)
-#define SYS_STATS_INC_USED(x)
-#define SYS_STATS_DISPLAY()
-#endif
-
-#if IP6_STATS
-#define IP6_STATS_INC(x) STATS_INC(x)
-#define IP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6, "IPv6")
-#else
-#define IP6_STATS_INC(x)
-#define IP6_STATS_DISPLAY()
-#endif
-
-#if ICMP6_STATS
-#define ICMP6_STATS_INC(x) STATS_INC(x)
-#define ICMP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp6, "ICMPv6")
-#else
-#define ICMP6_STATS_INC(x)
-#define ICMP6_STATS_DISPLAY()
-#endif
-
-#if IP6_FRAG_STATS
-#define IP6_FRAG_STATS_INC(x) STATS_INC(x)
-#define IP6_FRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6_frag, "IPv6 FRAG")
-#else
-#define IP6_FRAG_STATS_INC(x)
-#define IP6_FRAG_STATS_DISPLAY()
-#endif
-
-#if MLD6_STATS
-#define MLD6_STATS_INC(x) STATS_INC(x)
-#define MLD6_STATS_DISPLAY() stats_display_igmp(&lwip_stats.mld6, "MLDv1")
-#else
-#define MLD6_STATS_INC(x)
-#define MLD6_STATS_DISPLAY()
-#endif
-
-#if ND6_STATS
-#define ND6_STATS_INC(x) STATS_INC(x)
-#define ND6_STATS_DISPLAY() stats_display_proto(&lwip_stats.nd6, "ND")
-#else
-#define ND6_STATS_INC(x)
-#define ND6_STATS_DISPLAY()
-#endif
-
-#if MIB2_STATS
-#define MIB2_STATS_INC(x) STATS_INC(x)
-#else
-#define MIB2_STATS_INC(x)
-#endif
-
-#if ESP_STATS_DROP
-#define ESP_STATS_DROP_INC(x) STATS_INC(x)
-#define ESP_STATS_DROP_DISPLAY() stats_display_esp(&lwip_stats.esp);
-#else
-#define ESP_STATS_DROP_INC(x)
-#define ESP_STATS_DROP_DISPLAY()
-#endif
-
-/* Display of statistics */
-#if LWIP_STATS_DISPLAY
-void stats_display(void);
-void stats_display_proto(struct stats_proto *proto, const char *name);
-void stats_display_igmp(struct stats_igmp *igmp, const char *name);
-void stats_display_mem(struct stats_mem *mem, const char *name);
-void stats_display_memp(struct stats_mem *mem, int index);
-void stats_display_sys(struct stats_sys *sys);
-#if ESP_STATS_DROP
-void stats_display_esp(struct stats_esp *esp);
-#endif
-
-#else /* LWIP_STATS_DISPLAY */
-#define stats_display()
-#define stats_display_proto(proto, name)
-#define stats_display_igmp(igmp, name)
-#define stats_display_mem(mem, name)
-#define stats_display_memp(mem, index)
-#define stats_display_sys(sys)
-#if ESP_STATS_DROP
-#define stats_display_esp(esp)
-#endif
-
-#endif /* LWIP_STATS_DISPLAY */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_STATS_H */
diff --git a/tools/sdk/include/lwip/lwip/sys.h b/tools/sdk/include/lwip/lwip/sys.h
deleted file mode 100644
index 695cae49dca..00000000000
--- a/tools/sdk/include/lwip/lwip/sys.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/**
- * @file
- * OS abstraction layer
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- */
-
-#ifndef LWIP_HDR_SYS_H
-#define LWIP_HDR_SYS_H
-
-#include "lwip/opt.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if NO_SYS
-
-/* For a totally minimal and standalone system, we provide null
-   definitions of the sys_ functions. */
-typedef u8_t sys_sem_t;
-typedef u8_t sys_mutex_t;
-typedef u8_t sys_mbox_t;
-
-#define sys_sem_new(s, c) ERR_OK
-#define sys_sem_signal(s)
-#define sys_sem_wait(s)
-#define sys_arch_sem_wait(s,t)
-#define sys_sem_free(s)
-#define sys_sem_valid(s) 0
-#define sys_sem_valid_val(s) 0
-#define sys_sem_set_invalid(s)
-#define sys_sem_set_invalid_val(s)
-#define sys_mutex_new(mu) ERR_OK
-#define sys_mutex_lock(mu)
-#define sys_mutex_unlock(mu)
-#define sys_mutex_free(mu)
-#define sys_mutex_valid(mu) 0
-#define sys_mutex_set_invalid(mu)
-#define sys_mbox_new(m, s) ERR_OK
-#define sys_mbox_fetch(m,d)
-#define sys_mbox_tryfetch(m,d)
-#define sys_mbox_post(m,d)
-#define sys_mbox_trypost(m,d)
-#define sys_mbox_free(m)
-#define sys_mbox_valid(m)
-#define sys_mbox_valid_val(m)
-#define sys_mbox_set_invalid(m)
-#define sys_mbox_set_invalid_val(m)
-
-#define sys_thread_new(n,t,a,s,p)
-
-#define sys_msleep(t)
-
-#else /* NO_SYS */
-
-/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */
-#define SYS_ARCH_TIMEOUT 0xffffffffUL
-
-/** sys_mbox_tryfetch() returns SYS_MBOX_EMPTY if appropriate.
- * For now we use the same magic value, but we allow this to change in future.
- */
-#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT
-
-#include "lwip/err.h"
-#include "arch/sys_arch.h"
-
-/** Function prototype for thread functions */
-typedef void (*lwip_thread_fn)(void *arg);
-
-/* Function prototypes for functions to be implemented by platform ports
-   (in sys_arch.c) */
-
-/* Mutex functions: */
-
-/** Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores
-    should be used instead */
-#ifndef LWIP_COMPAT_MUTEX
-#define LWIP_COMPAT_MUTEX 0
-#endif
-
-#if LWIP_COMPAT_MUTEX
-/* for old ports that don't have mutexes: define them to binary semaphores */
-#define sys_mutex_t                   sys_sem_t
-#define sys_mutex_new(mutex)          sys_sem_new(mutex, 1)
-#define sys_mutex_lock(mutex)         sys_sem_wait(mutex)
-#define sys_mutex_unlock(mutex)       sys_sem_signal(mutex)
-#define sys_mutex_free(mutex)         sys_sem_free(mutex)
-#define sys_mutex_valid(mutex)        sys_sem_valid(mutex)
-#define sys_mutex_set_invalid(mutex)  sys_sem_set_invalid(mutex)
-
-#else /* LWIP_COMPAT_MUTEX */
-
-/**
- * @ingroup sys_mutex
- * Create a new mutex.
- * Note that mutexes are expected to not be taken recursively by the lwIP code,
- * so both implementation types (recursive or non-recursive) should work.
- * @param mutex pointer to the mutex to create
- * @return ERR_OK if successful, another err_t otherwise
- */
-err_t sys_mutex_new(sys_mutex_t *mutex);
-/**
- * @ingroup sys_mutex
- * Lock a mutex
- * @param mutex the mutex to lock
- */
-void sys_mutex_lock(sys_mutex_t *mutex);
-/**
- * @ingroup sys_mutex
- * Unlock a mutex
- * @param mutex the mutex to unlock
- */
-void sys_mutex_unlock(sys_mutex_t *mutex);
-/**
- * @ingroup sys_mutex
- * Delete a semaphore
- * @param mutex the mutex to delete
- */
-void sys_mutex_free(sys_mutex_t *mutex);
-#ifndef sys_mutex_valid
-/**
- * @ingroup sys_mutex
- * Check if a mutex is valid/allocated: return 1 for valid, 0 for invalid
- */
-int sys_mutex_valid(sys_mutex_t *mutex);
-#endif
-#ifndef sys_mutex_set_invalid
-/**
- * @ingroup sys_mutex
- * Set a mutex invalid so that sys_mutex_valid returns 0
- */
-void sys_mutex_set_invalid(sys_mutex_t *mutex);
-#endif
-#endif /* LWIP_COMPAT_MUTEX */
-
-/* Semaphore functions: */
-
-/**
- * @ingroup sys_sem
- * Create a new semaphore
- * @param sem pointer to the semaphore to create
- * @param count initial count of the semaphore
- * @return ERR_OK if successful, another err_t otherwise
- */
-err_t sys_sem_new(sys_sem_t *sem, u8_t count);
-/**
- * @ingroup sys_sem
- * Signals a semaphore
- * @param sem the semaphore to signal
- */
-void sys_sem_signal(sys_sem_t *sem);
-
-#if ESP_LWIP
-/** Signals a semaphore (ISR version)
- * @param sem the semaphore to signal
- * @return non-zero if a higher priority task has been woken  */
-int sys_sem_signal_isr(sys_sem_t *sem);
-#endif
-
-/**
- * @ingroup sys_sem
- * Wait for a semaphore for the specified timeout
- * @param sem the semaphore to wait for
- * @param timeout timeout in milliseconds to wait (0 = wait forever)
- * @return time (in milliseconds) waited for the semaphore
- *         or SYS_ARCH_TIMEOUT on timeout
- */
-u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout);
-/**
- * @ingroup sys_sem
- * Delete a semaphore
- * @param sem semaphore to delete
- */
-void sys_sem_free(sys_sem_t *sem);
-/** Wait for a semaphore - forever/no timeout */
-#define sys_sem_wait(sem)                  sys_arch_sem_wait(sem, 0)
-#ifndef sys_sem_valid
-/**
- * @ingroup sys_sem
- * Check if a semaphore is valid/allocated: return 1 for valid, 0 for invalid
- */
-int sys_sem_valid(sys_sem_t *sem);
-#endif
-#ifndef sys_sem_set_invalid
-/**
- * @ingroup sys_sem
- * Set a semaphore invalid so that sys_sem_valid returns 0
- */
-void sys_sem_set_invalid(sys_sem_t *sem);
-#endif
-#ifndef sys_sem_valid_val
-/**
- * Same as sys_sem_valid() but taking a value, not a pointer
- */
-#define sys_sem_valid_val(sem)       sys_sem_valid(&(sem))
-#endif
-#ifndef sys_sem_set_invalid_val
-/**
- * Same as sys_sem_set_invalid() but taking a value, not a pointer
- */
-#define sys_sem_set_invalid_val(sem) sys_sem_set_invalid(&(sem))
-#endif
-
-#ifndef sys_msleep
-/**
- * @ingroup sys_misc
- * Sleep for specified number of ms
- */
-void sys_msleep(u32_t ms); /* only has a (close to) 1 ms resolution. */
-#endif
-
-/* Mailbox functions. */
-
-/**
- * @ingroup sys_mbox
- * Create a new mbox of specified size
- * @param mbox pointer to the mbox to create
- * @param size (minimum) number of messages in this mbox
- * @return ERR_OK if successful, another err_t otherwise
- */
-err_t sys_mbox_new(sys_mbox_t *mbox, int size);
-/**
- * @ingroup sys_mbox
- * Post a message to an mbox - may not fail
- * -> blocks if full, only used from tasks not from ISR
- * @param mbox mbox to posts the message
- * @param msg message to post (ATTENTION: can be NULL)
- */
-void sys_mbox_post(sys_mbox_t *mbox, void *msg);
-/**
- * @ingroup sys_mbox
- * Try to post a message to an mbox - may fail if full or ISR
- * @param mbox mbox to posts the message
- * @param msg message to post (ATTENTION: can be NULL)
- */
-err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg);
-/**
- * @ingroup sys_mbox
- * Wait for a new message to arrive in the mbox
- * @param mbox mbox to get a message from
- * @param msg pointer where the message is stored
- * @param timeout maximum time (in milliseconds) to wait for a message (0 = wait forever)
- * @return time (in milliseconds) waited for a message, may be 0 if not waited
-           or SYS_ARCH_TIMEOUT on timeout
- *         The returned time has to be accurate to prevent timer jitter!
- */
-u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout);
-
-#if ESP_THREAD_SAFE
-/**
- * @ingroup sys_mbox
- * Set the owner of the mbox
- * @param mbox mbox to set the owner
- * @param owner the owner of the mbox, it's a pointer to struct netconn
- */
-void sys_mbox_set_owner(sys_mbox_t *mbox, void *owner);
-#endif
-
-/* Allow port to override with a macro, e.g. special timeout for sys_arch_mbox_fetch() */
-#ifndef sys_arch_mbox_tryfetch
-/**
- * @ingroup sys_mbox
- * Wait for a new message to arrive in the mbox
- * @param mbox mbox to get a message from
- * @param msg pointer where the message is stored
- * @return 0 (milliseconds) if a message has been received
- *         or SYS_MBOX_EMPTY if the mailbox is empty
- */
-u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg);
-#endif
-/**
- * For now, we map straight to sys_arch implementation.
- */
-#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg)
-/**
- * @ingroup sys_mbox
- * Delete an mbox
- * @param mbox mbox to delete
- */
-void sys_mbox_free(sys_mbox_t *mbox);
-#define sys_mbox_fetch(mbox, msg) sys_arch_mbox_fetch(mbox, msg, 0)
-#ifndef sys_mbox_valid
-/**
- * @ingroup sys_mbox
- * Check if an mbox is valid/allocated: return 1 for valid, 0 for invalid
- */
-int sys_mbox_valid(sys_mbox_t *mbox);
-#endif
-#ifndef sys_mbox_set_invalid
-/**
- * @ingroup sys_mbox
- * Set an mbox invalid so that sys_mbox_valid returns 0
- */
-void sys_mbox_set_invalid(sys_mbox_t *mbox);
-#endif
-#ifndef sys_mbox_valid_val
-/**
- * Same as sys_mbox_valid() but taking a value, not a pointer
- */
-#define sys_mbox_valid_val(mbox)       sys_mbox_valid(&(mbox))
-#endif
-#ifndef sys_mbox_set_invalid_val
-/**
- * Same as sys_mbox_set_invalid() but taking a value, not a pointer
- */
-#define sys_mbox_set_invalid_val(mbox) sys_mbox_set_invalid(&(mbox))
-#endif
-
-
-/**
- * @ingroup sys_misc
- * The only thread function:
- * Creates a new thread
- * ATTENTION: although this function returns a value, it MUST NOT FAIL (ports have to assert this!)
- * @param name human-readable name for the thread (used for debugging purposes)
- * @param thread thread-function
- * @param arg parameter passed to 'thread'
- * @param stacksize stack size in bytes for the new thread (may be ignored by ports)
- * @param prio priority of the new thread (may be ignored by ports) */
-sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio);
-
-#endif /* NO_SYS */
-
-/* sys_init() must be called before anything else. */
-void sys_init(void);
-
-#ifndef sys_jiffies
-/**
- * Ticks/jiffies since power up.
- */
-u32_t sys_jiffies(void);
-#endif
-
-/**
- * @ingroup sys_time
- * Returns the current time in milliseconds,
- * may be the same as sys_jiffies or at least based on it.
- */
-u32_t sys_now(void);
-
-/* Critical Region Protection */
-/* These functions must be implemented in the sys_arch.c file.
-   In some implementations they can provide a more light-weight protection
-   mechanism than using semaphores. Otherwise semaphores can be used for
-   implementation */
-#ifndef SYS_ARCH_PROTECT
-/** SYS_LIGHTWEIGHT_PROT
- * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
- * for certain critical regions during buffer allocation, deallocation and memory
- * allocation and deallocation.
- */
-#if SYS_LIGHTWEIGHT_PROT
-
-/**
- * @ingroup sys_prot
- * SYS_ARCH_DECL_PROTECT
- * declare a protection variable. This macro will default to defining a variable of
- * type sys_prot_t. If a particular port needs a different implementation, then
- * this macro may be defined in sys_arch.h.
- */
-#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev
-/**
- * @ingroup sys_prot
- * SYS_ARCH_PROTECT
- * Perform a "fast" protect. This could be implemented by
- * disabling interrupts for an embedded system or by using a semaphore or
- * mutex. The implementation should allow calling SYS_ARCH_PROTECT when
- * already protected. The old protection level is returned in the variable
- * "lev". This macro will default to calling the sys_arch_protect() function
- * which should be implemented in sys_arch.c. If a particular port needs a
- * different implementation, then this macro may be defined in sys_arch.h
- */
-#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect()
-/**
- * @ingroup sys_prot
- * SYS_ARCH_UNPROTECT
- * Perform a "fast" set of the protection level to "lev". This could be
- * implemented by setting the interrupt level to "lev" within the MACRO or by
- * using a semaphore or mutex.  This macro will default to calling the
- * sys_arch_unprotect() function which should be implemented in
- * sys_arch.c. If a particular port needs a different implementation, then
- * this macro may be defined in sys_arch.h
- */
-#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev)
-sys_prot_t sys_arch_protect(void);
-void sys_arch_unprotect(sys_prot_t pval);
-
-#else
-
-#define SYS_ARCH_DECL_PROTECT(lev)
-#define SYS_ARCH_PROTECT(lev)
-#define SYS_ARCH_UNPROTECT(lev)
-
-#endif /* SYS_LIGHTWEIGHT_PROT */
-
-#endif /* SYS_ARCH_PROTECT */
-
-/*
- * Macros to set/get and increase/decrease variables in a thread-safe way.
- * Use these for accessing variable that are used from more than one thread.
- */
-
-#ifndef SYS_ARCH_INC
-#define SYS_ARCH_INC(var, val) do { \
-                                SYS_ARCH_DECL_PROTECT(old_level); \
-                                SYS_ARCH_PROTECT(old_level); \
-                                var += val; \
-                                SYS_ARCH_UNPROTECT(old_level); \
-                              } while(0)
-#endif /* SYS_ARCH_INC */
-
-#ifndef SYS_ARCH_DEC
-#define SYS_ARCH_DEC(var, val) do { \
-                                SYS_ARCH_DECL_PROTECT(old_level); \
-                                SYS_ARCH_PROTECT(old_level); \
-                                var -= val; \
-                                SYS_ARCH_UNPROTECT(old_level); \
-                              } while(0)
-#endif /* SYS_ARCH_DEC */
-
-#ifndef SYS_ARCH_GET
-#define SYS_ARCH_GET(var, ret) do { \
-                                SYS_ARCH_DECL_PROTECT(old_level); \
-                                SYS_ARCH_PROTECT(old_level); \
-                                ret = var; \
-                                SYS_ARCH_UNPROTECT(old_level); \
-                              } while(0)
-#endif /* SYS_ARCH_GET */
-
-#ifndef SYS_ARCH_SET
-#define SYS_ARCH_SET(var, val) do { \
-                                SYS_ARCH_DECL_PROTECT(old_level); \
-                                SYS_ARCH_PROTECT(old_level); \
-                                var = val; \
-                                SYS_ARCH_UNPROTECT(old_level); \
-                              } while(0)
-#endif /* SYS_ARCH_SET */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_SYS_H */
diff --git a/tools/sdk/include/lwip/lwip/tcp.h b/tools/sdk/include/lwip/lwip/tcp.h
deleted file mode 100644
index 30dbf147608..00000000000
--- a/tools/sdk/include/lwip/lwip/tcp.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/**
- * @file
- * TCP API (to be used from TCPIP thread)\n
- * See also @ref tcp_raw
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_TCP_H
-#define LWIP_HDR_TCP_H
-
-#include "lwip/opt.h"
-
-#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/mem.h"
-#include "lwip/pbuf.h"
-#include "lwip/ip.h"
-#include "lwip/icmp.h"
-#include "lwip/err.h"
-#include "lwip/ip6.h"
-#include "lwip/ip6_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct tcp_pcb;
-
-/** Function prototype for tcp accept callback functions. Called when a new
- * connection can be accepted on a listening pcb.
- *
- * @param arg Additional argument to pass to the callback function (@see tcp_arg())
- * @param newpcb The new connection pcb
- * @param err An error code if there has been an error accepting.
- *            Only return ERR_ABRT if you have called tcp_abort from within the
- *            callback function!
- */
-typedef err_t (*tcp_accept_fn)(void *arg, struct tcp_pcb *newpcb, err_t err);
-
-/** Function prototype for tcp receive callback functions. Called when data has
- * been received.
- *
- * @param arg Additional argument to pass to the callback function (@see tcp_arg())
- * @param tpcb The connection pcb which received data
- * @param p The received data (or NULL when the connection has been closed!)
- * @param err An error code if there has been an error receiving
- *            Only return ERR_ABRT if you have called tcp_abort from within the
- *            callback function!
- */
-typedef err_t (*tcp_recv_fn)(void *arg, struct tcp_pcb *tpcb,
-                             struct pbuf *p, err_t err);
-
-/** Function prototype for tcp sent callback functions. Called when sent data has
- * been acknowledged by the remote side. Use it to free corresponding resources.
- * This also means that the pcb has now space available to send new data.
- *
- * @param arg Additional argument to pass to the callback function (@see tcp_arg())
- * @param tpcb The connection pcb for which data has been acknowledged
- * @param len The amount of bytes acknowledged
- * @return ERR_OK: try to send some data by calling tcp_output
- *            Only return ERR_ABRT if you have called tcp_abort from within the
- *            callback function!
- */
-typedef err_t (*tcp_sent_fn)(void *arg, struct tcp_pcb *tpcb,
-                              u16_t len);
-
-/** Function prototype for tcp poll callback functions. Called periodically as
- * specified by @see tcp_poll.
- *
- * @param arg Additional argument to pass to the callback function (@see tcp_arg())
- * @param tpcb tcp pcb
- * @return ERR_OK: try to send some data by calling tcp_output
- *            Only return ERR_ABRT if you have called tcp_abort from within the
- *            callback function!
- */
-typedef err_t (*tcp_poll_fn)(void *arg, struct tcp_pcb *tpcb);
-
-/** Function prototype for tcp error callback functions. Called when the pcb
- * receives a RST or is unexpectedly closed for any other reason.
- *
- * @note The corresponding pcb is already freed when this callback is called!
- *
- * @param arg Additional argument to pass to the callback function (@see tcp_arg())
- * @param err Error code to indicate why the pcb has been closed
- *            ERR_ABRT: aborted through tcp_abort or by a TCP timer
- *            ERR_RST: the connection was reset by the remote host
- */
-typedef void  (*tcp_err_fn)(void *arg, err_t err);
-
-/** Function prototype for tcp connected callback functions. Called when a pcb
- * is connected to the remote side after initiating a connection attempt by
- * calling tcp_connect().
- *
- * @param arg Additional argument to pass to the callback function (@see tcp_arg())
- * @param tpcb The connection pcb which is connected
- * @param err An unused error code, always ERR_OK currently ;-) @todo!
- *            Only return ERR_ABRT if you have called tcp_abort from within the
- *            callback function!
- *
- * @note When a connection attempt fails, the error callback is currently called!
- */
-typedef err_t (*tcp_connected_fn)(void *arg, struct tcp_pcb *tpcb, err_t err);
-
-#if LWIP_WND_SCALE
-#define RCV_WND_SCALE(pcb, wnd) (((wnd) >> (pcb)->rcv_scale))
-#define SND_WND_SCALE(pcb, wnd) (((wnd) << (pcb)->snd_scale))
-#define TCPWND16(x)             ((u16_t)LWIP_MIN((x), 0xFFFF))
-#define TCP_WND_MAX(pcb)        ((tcpwnd_size_t)(((pcb)->flags & TF_WND_SCALE) ? TCP_WND : TCPWND16(TCP_WND)))
-typedef u32_t tcpwnd_size_t;
-#else
-#define RCV_WND_SCALE(pcb, wnd) (wnd)
-#define SND_WND_SCALE(pcb, wnd) (wnd)
-#define TCPWND16(x)             (x)
-#define TCP_WND_MAX(pcb)        TCP_WND
-typedef u16_t tcpwnd_size_t;
-#endif
-
-#if LWIP_WND_SCALE || TCP_LISTEN_BACKLOG || LWIP_TCP_TIMESTAMPS
-typedef u16_t tcpflags_t;
-#else
-typedef u8_t tcpflags_t;
-#endif
-
-enum tcp_state {
-  CLOSED      = 0,
-  LISTEN      = 1,
-  SYN_SENT    = 2,
-  SYN_RCVD    = 3,
-  ESTABLISHED = 4,
-  FIN_WAIT_1  = 5,
-  FIN_WAIT_2  = 6,
-  CLOSE_WAIT  = 7,
-  CLOSING     = 8,
-  LAST_ACK    = 9,
-  TIME_WAIT   = 10
-};
-
-/**
- * members common to struct tcp_pcb and struct tcp_listen_pcb
- */
-#define TCP_PCB_COMMON(type) \
-  type *next; /* for the linked list */ \
-  void *callback_arg; \
-  enum tcp_state state; /* TCP state */ \
-  u8_t prio; \
-  /* ports are in host byte order */ \
-  u16_t local_port
-
-
-/** the TCP protocol control block for listening pcbs */
-struct tcp_pcb_listen {
-/** Common members of all PCB types */
-  IP_PCB;
-/** Protocol specific PCB members */
-  TCP_PCB_COMMON(struct tcp_pcb_listen);
-
-#if LWIP_CALLBACK_API
-  /* Function to call when a listener has been connected. */
-  tcp_accept_fn accept;
-#endif /* LWIP_CALLBACK_API */
-
-#if TCP_LISTEN_BACKLOG
-  u8_t backlog;
-  u8_t accepts_pending;
-#endif /* TCP_LISTEN_BACKLOG */
-};
-
-
-/** the TCP protocol control block */
-struct tcp_pcb {
-/** common PCB members */
-  IP_PCB;
-/** protocol specific PCB members */
-  TCP_PCB_COMMON(struct tcp_pcb);
-
-  /* ports are in host byte order */
-  u16_t remote_port;
-
-  tcpflags_t flags;
-#define TF_ACK_DELAY   0x01U   /* Delayed ACK. */
-#define TF_ACK_NOW     0x02U   /* Immediate ACK. */
-#define TF_INFR        0x04U   /* In fast recovery. */
-#define TF_CLOSEPEND   0x08U   /* If this is set, tcp_close failed to enqueue the FIN (retried in tcp_tmr) */
-#define TF_RXCLOSED    0x10U   /* rx closed by tcp_shutdown */
-#define TF_FIN         0x20U   /* Connection was closed locally (FIN segment enqueued). */
-#define TF_NODELAY     0x40U   /* Disable Nagle algorithm */
-#define TF_NAGLEMEMERR 0x80U   /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */
-#if LWIP_WND_SCALE
-#define TF_WND_SCALE   0x0100U /* Window Scale option enabled */
-#endif
-#if TCP_LISTEN_BACKLOG
-#define TF_BACKLOGPEND 0x0200U /* If this is set, a connection pcb has increased the backlog on its listener */
-#endif
-#if LWIP_TCP_TIMESTAMPS
-#define TF_TIMESTAMP   0x0400U   /* Timestamp option enabled */
-#endif
-
-  /* the rest of the fields are in host byte order
-     as we have to do some math with them */
-
-  /* Timers */
-  u8_t polltmr, pollinterval;
-  u8_t last_timer;
-  u32_t tmr;
-
-  /* receiver variables */
-  u32_t rcv_nxt;   /* next seqno expected */
-  tcpwnd_size_t rcv_wnd;   /* receiver window available */
-  tcpwnd_size_t rcv_ann_wnd; /* receiver window to announce */
-  u32_t rcv_ann_right_edge; /* announced right edge of window */
-
-  /* Retransmission timer. */
-  s16_t rtime;
-
-  u16_t mss;   /* maximum segment size */
-
-  /* RTT (round trip time) estimation variables */
-  u32_t rttest; /* RTT estimate in 500ms ticks */
-  u32_t rtseq;  /* sequence number being timed */
-  s16_t sa, sv; /* @todo document this */
-
-  s16_t rto;    /* retransmission time-out */
-  u8_t nrtx;    /* number of retransmissions */
-
-  /* fast retransmit/recovery */
-  u8_t dupacks;
-  u32_t lastack; /* Highest acknowledged seqno. */
-
-  /* congestion avoidance/control variables */
-  tcpwnd_size_t cwnd;
-  tcpwnd_size_t ssthresh;
-
-  /* sender variables */
-  u32_t snd_nxt;   /* next new seqno to be sent */
-  u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last
-                             window update. */
-  u32_t snd_lbb;       /* Sequence number of next byte to be buffered. */
-  tcpwnd_size_t snd_wnd;   /* sender window */
-  tcpwnd_size_t snd_wnd_max; /* the maximum sender window announced by the remote host */
-
-  tcpwnd_size_t snd_buf;   /* Available buffer space for sending (in bytes). */
-#define TCP_SNDQUEUELEN_OVERFLOW (0xffffU-3)
-  u16_t snd_queuelen; /* Number of pbufs currently in the send buffer. */
-
-#if TCP_OVERSIZE
-  /* Extra bytes available at the end of the last pbuf in unsent. */
-  u16_t unsent_oversize;
-#endif /* TCP_OVERSIZE */
-
-  /* These are ordered by sequence number: */
-  struct tcp_seg *unsent;   /* Unsent (queued) segments. */
-  struct tcp_seg *unacked;  /* Sent but unacknowledged segments. */
-#if TCP_QUEUE_OOSEQ
-  struct tcp_seg *ooseq;    /* Received out of sequence segments. */
-#endif /* TCP_QUEUE_OOSEQ */
-
-  struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */
-
-#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
-  struct tcp_pcb_listen* listener;
-#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
-
-#if LWIP_CALLBACK_API
-  /* Function to be called when more send buffer space is available. */
-  tcp_sent_fn sent;
-  /* Function to be called when (in-sequence) data has arrived. */
-  tcp_recv_fn recv;
-  /* Function to be called when a connection has been set up. */
-  tcp_connected_fn connected;
-  /* Function which is called periodically. */
-  tcp_poll_fn poll;
-  /* Function to be called whenever a fatal error occurs. */
-  tcp_err_fn errf;
-#endif /* LWIP_CALLBACK_API */
-
-#if LWIP_TCP_TIMESTAMPS
-  u32_t ts_lastacksent;
-  u32_t ts_recent;
-#endif /* LWIP_TCP_TIMESTAMPS */
-
-  /* idle time before KEEPALIVE is sent */
-  u32_t keep_idle;
-#if LWIP_TCP_KEEPALIVE
-  u32_t keep_intvl;
-  u32_t keep_cnt;
-#endif /* LWIP_TCP_KEEPALIVE */
-
-  /* Persist timer counter */
-  u8_t persist_cnt;
-  /* Persist timer back-off */
-  u8_t persist_backoff;
-
-  /* KEEPALIVE counter */
-  u8_t keep_cnt_sent;
-
-#if LWIP_WND_SCALE
-  u8_t snd_scale;
-  u8_t rcv_scale;
-#endif
-
-#if ESP_STATS_TCP
-#define ESP_STATS_TCP_ARRAY_SIZE 20
-  u16_t retry_cnt[TCP_MAXRTX];
-  u16_t rto_cnt[ESP_STATS_TCP_ARRAY_SIZE];
-#endif
-};
-
-#if ESP_STATS_TCP
-#define ESP_STATS_TCP_PCB(_pcb) do {\
-  if ((_pcb)->unacked) {\
-    (_pcb)->retry_cnt[(_pcb)->nrtx]++;\
-    if ((_pcb)->rto < ESP_STATS_TCP_ARRAY_SIZE) {\
-      (_pcb)->rto_cnt[(_pcb)->rto]++;\
-    } else {\
-      (_pcb)->rto_cnt[ESP_STATS_TCP_ARRAY_SIZE-1] ++;\
-    }\
-  }\
-} while(0)
-#else
-#define ESP_STATS_TCP_PCB(pcb) 
-#endif
-
-#if LWIP_EVENT_API
-
-enum lwip_event {
-  LWIP_EVENT_ACCEPT,
-  LWIP_EVENT_SENT,
-  LWIP_EVENT_RECV,
-  LWIP_EVENT_CONNECTED,
-  LWIP_EVENT_POLL,
-  LWIP_EVENT_ERR
-};
-
-err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb,
-         enum lwip_event,
-         struct pbuf *p,
-         u16_t size,
-         err_t err);
-
-#endif /* LWIP_EVENT_API */
-
-/* Application program's interface: */
-struct tcp_pcb * tcp_new     (void);
-struct tcp_pcb * tcp_new_ip_type (u8_t type);
-
-void             tcp_arg     (struct tcp_pcb *pcb, void *arg);
-#if LWIP_CALLBACK_API
-void             tcp_recv    (struct tcp_pcb *pcb, tcp_recv_fn recv);
-void             tcp_sent    (struct tcp_pcb *pcb, tcp_sent_fn sent);
-void             tcp_err     (struct tcp_pcb *pcb, tcp_err_fn err);
-void             tcp_accept  (struct tcp_pcb *pcb, tcp_accept_fn accept);
-#endif /* LWIP_CALLBACK_API */
-void             tcp_poll    (struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval);
-
-#if LWIP_TCP_TIMESTAMPS
-#define          tcp_mss(pcb)             (((pcb)->flags & TF_TIMESTAMP) ? ((pcb)->mss - 12)  : (pcb)->mss)
-#else /* LWIP_TCP_TIMESTAMPS */
-#define          tcp_mss(pcb)             ((pcb)->mss)
-#endif /* LWIP_TCP_TIMESTAMPS */
-#define          tcp_sndbuf(pcb)          (TCPWND16((pcb)->snd_buf))
-#define          tcp_sndqueuelen(pcb)     ((pcb)->snd_queuelen)
-/** @ingroup tcp_raw */
-#define          tcp_nagle_disable(pcb)   ((pcb)->flags |= TF_NODELAY)
-/** @ingroup tcp_raw */
-#define          tcp_nagle_enable(pcb)    ((pcb)->flags = (tcpflags_t)((pcb)->flags & ~TF_NODELAY))
-/** @ingroup tcp_raw */
-#define          tcp_nagle_disabled(pcb)  (((pcb)->flags & TF_NODELAY) != 0)
-
-#if TCP_LISTEN_BACKLOG
-#define          tcp_backlog_set(pcb, new_backlog) do { \
-  LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", (pcb)->state == LISTEN); \
-  ((struct tcp_pcb_listen *)(pcb))->backlog = ((new_backlog) ? (new_backlog) : 1); } while(0)
-void             tcp_backlog_delayed(struct tcp_pcb* pcb);
-void             tcp_backlog_accepted(struct tcp_pcb* pcb);
-#else  /* TCP_LISTEN_BACKLOG */
-#define          tcp_backlog_set(pcb, new_backlog)
-#define          tcp_backlog_delayed(pcb)
-#define          tcp_backlog_accepted(pcb)
-#endif /* TCP_LISTEN_BACKLOG */
-#define          tcp_accepted(pcb) /* compatibility define, not needed any more */
-
-void             tcp_recved  (struct tcp_pcb *pcb, u16_t len);
-err_t            tcp_bind    (struct tcp_pcb *pcb, const ip_addr_t *ipaddr,
-                              u16_t port);
-err_t            tcp_connect (struct tcp_pcb *pcb, const ip_addr_t *ipaddr,
-                              u16_t port, tcp_connected_fn connected);
-
-struct tcp_pcb * tcp_listen_with_backlog_and_err(struct tcp_pcb *pcb, u8_t backlog, err_t *err);
-struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog);
-/** @ingroup tcp_raw */
-#define          tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG)
-
-void             tcp_abort (struct tcp_pcb *pcb);
-err_t            tcp_close   (struct tcp_pcb *pcb);
-err_t            tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx);
-
-/* Flags for "apiflags" parameter in tcp_write */
-#define TCP_WRITE_FLAG_COPY 0x01
-#define TCP_WRITE_FLAG_MORE 0x02
-
-err_t            tcp_write   (struct tcp_pcb *pcb, const void *dataptr, u16_t len,
-                              u8_t apiflags);
-
-void             tcp_setprio (struct tcp_pcb *pcb, u8_t prio);
-
-#define TCP_PRIO_MIN    1
-#define TCP_PRIO_NORMAL 64
-#define TCP_PRIO_MAX    127
-
-err_t            tcp_output  (struct tcp_pcb *pcb);
-
-
-const char* tcp_debug_state_str(enum tcp_state s);
-
-/* for compatibility with older implementation */
-#define tcp_new_ip6() tcp_new_ip_type(IPADDR_TYPE_V6)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_TCP */
-
-#endif /* LWIP_HDR_TCP_H */
diff --git a/tools/sdk/include/lwip/lwip/tcpip.h b/tools/sdk/include/lwip/lwip/tcpip.h
deleted file mode 100644
index f2f6b469f16..00000000000
--- a/tools/sdk/include/lwip/lwip/tcpip.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * @file
- * Functions to sync with TCPIP thread
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_TCPIP_H
-#define LWIP_HDR_TCPIP_H
-
-#include "lwip/opt.h"
-
-#if !NO_SYS /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/err.h"
-#include "lwip/timeouts.h"
-#include "lwip/netif.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_TCPIP_CORE_LOCKING
-/** The global semaphore to lock the stack. */
-extern sys_mutex_t lock_tcpip_core;
-/** Lock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */
-#define LOCK_TCPIP_CORE()     sys_mutex_lock(&lock_tcpip_core)
-/** Unlock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */
-#define UNLOCK_TCPIP_CORE()   sys_mutex_unlock(&lock_tcpip_core)
-#else /* LWIP_TCPIP_CORE_LOCKING */
-#define LOCK_TCPIP_CORE()
-#define UNLOCK_TCPIP_CORE()
-#endif /* LWIP_TCPIP_CORE_LOCKING */
-
-struct pbuf;
-struct netif;
-
-/** Function prototype for the init_done function passed to tcpip_init */
-typedef void (*tcpip_init_done_fn)(void *arg);
-/** Function prototype for functions passed to tcpip_callback() */
-typedef void (*tcpip_callback_fn)(void *ctx);
-
-/* Forward declarations */
-struct tcpip_callback_msg;
-
-void   tcpip_init(tcpip_init_done_fn tcpip_init_done, void *arg);
-
-err_t  tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn);
-err_t  tcpip_input(struct pbuf *p, struct netif *inp);
-
-err_t  tcpip_callback_with_block(tcpip_callback_fn function, void *ctx, u8_t block);
-/**
- * @ingroup lwip_os
- * @see tcpip_callback_with_block
- */
-#define tcpip_callback(f, ctx)  tcpip_callback_with_block(f, ctx, 1)
-
-struct tcpip_callback_msg* tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx);
-void   tcpip_callbackmsg_delete(struct tcpip_callback_msg* msg);
-err_t  tcpip_trycallback(struct tcpip_callback_msg* msg);
-
-/* free pbufs or heap memory from another context without blocking */
-err_t  pbuf_free_callback(struct pbuf *p);
-err_t  mem_free_callback(void *m);
-
-#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS
-err_t  tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg);
-err_t  tcpip_untimeout(sys_timeout_handler h, void *arg);
-#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !NO_SYS */
-
-#endif /* LWIP_HDR_TCPIP_H */
diff --git a/tools/sdk/include/lwip/lwip/timeouts.h b/tools/sdk/include/lwip/lwip/timeouts.h
deleted file mode 100644
index c9b93aa02ac..00000000000
--- a/tools/sdk/include/lwip/lwip/timeouts.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/**
- * @file
- * Timer implementations
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *         Simon Goldschmidt
- *
- */
-#ifndef LWIP_HDR_TIMEOUTS_H
-#define LWIP_HDR_TIMEOUTS_H
-
-#include "lwip/opt.h"
-#include "lwip/err.h"
-#if !NO_SYS
-#include "lwip/sys.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef LWIP_DEBUG_TIMERNAMES
-#ifdef LWIP_DEBUG
-#define LWIP_DEBUG_TIMERNAMES SYS_DEBUG
-#else /* LWIP_DEBUG */
-#define LWIP_DEBUG_TIMERNAMES 0
-#endif /* LWIP_DEBUG*/
-#endif
-
-/** Function prototype for a stack-internal timer function that has to be
- * called at a defined interval */
-typedef void (* lwip_cyclic_timer_handler)(void);
-
-/** This struct contains information about a stack-internal timer function
- that has to be called at a defined interval */
-struct lwip_cyclic_timer {
-  u32_t interval_ms;
-  lwip_cyclic_timer_handler handler;
-#if LWIP_DEBUG_TIMERNAMES
-  const char* handler_name;
-#endif /* LWIP_DEBUG_TIMERNAMES */
-};
-
-/** This array contains all stack-internal cyclic timers. To get the number of
- * timers, use LWIP_ARRAYSIZE() */
-extern const struct lwip_cyclic_timer lwip_cyclic_timers[];
-
-#if LWIP_TIMERS
-
-/** Function prototype for a timeout callback function. Register such a function
- * using sys_timeout().
- *
- * @param arg Additional argument to pass to the function - set up by sys_timeout()
- */
-typedef void (* sys_timeout_handler)(void *arg);
-
-struct sys_timeo {
-  struct sys_timeo *next;
-  u32_t time;
-  sys_timeout_handler h;
-  void *arg;
-#if LWIP_DEBUG_TIMERNAMES
-  const char* handler_name;
-#endif /* LWIP_DEBUG_TIMERNAMES */
-};
-
-void sys_timeouts_init(void);
-
-#if LWIP_DEBUG_TIMERNAMES
-void sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name);
-#define sys_timeout(msecs, handler, arg) sys_timeout_debug(msecs, handler, arg, #handler)
-#else /* LWIP_DEBUG_TIMERNAMES */
-void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg);
-#endif /* LWIP_DEBUG_TIMERNAMES */
-
-void sys_untimeout(sys_timeout_handler handler, void *arg);
-void sys_restart_timeouts(void);
-#if NO_SYS
-void sys_check_timeouts(void);
-u32_t sys_timeouts_sleeptime(void);
-#else /* NO_SYS */
-void sys_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg);
-#endif /* NO_SYS */
-
-
-#endif /* LWIP_TIMERS */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_TIMEOUTS_H */
diff --git a/tools/sdk/include/lwip/lwip/udp.h b/tools/sdk/include/lwip/lwip/udp.h
deleted file mode 100644
index b679a82ddc4..00000000000
--- a/tools/sdk/include/lwip/lwip/udp.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/**
- * @file
- * UDP API (to be used from TCPIP thread)\n
- * See also @ref udp_raw
- */
-
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_UDP_H
-#define LWIP_HDR_UDP_H
-
-#include "lwip/opt.h"
-
-#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/pbuf.h"
-#include "lwip/netif.h"
-#include "lwip/ip_addr.h"
-#include "lwip/ip.h"
-#include "lwip/ip6_addr.h"
-#include "lwip/prot/udp.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define UDP_FLAGS_NOCHKSUM       0x01U
-#define UDP_FLAGS_UDPLITE        0x02U
-#define UDP_FLAGS_CONNECTED      0x04U
-#define UDP_FLAGS_MULTICAST_LOOP 0x08U
-
-struct udp_pcb;
-
-/** Function prototype for udp pcb receive callback functions
- * addr and port are in same byte order as in the pcb
- * The callback is responsible for freeing the pbuf
- * if it's not used any more.
- *
- * ATTENTION: Be aware that 'addr' might point into the pbuf 'p' so freeing this pbuf
- *            can make 'addr' invalid, too.
- *
- * @param arg user supplied argument (udp_pcb.recv_arg)
- * @param pcb the udp_pcb which received data
- * @param p the packet buffer that was received
- * @param addr the remote IP address from which the packet was received
- * @param port the remote port from which the packet was received
- */
-typedef void (*udp_recv_fn)(void *arg, struct udp_pcb *pcb, struct pbuf *p,
-    const ip_addr_t *addr, u16_t port);
-
-/** the UDP protocol control block */
-struct udp_pcb {
-/** Common members of all PCB types */
-  IP_PCB;
-
-/* Protocol specific PCB members */
-
-  struct udp_pcb *next;
-
-  u8_t flags;
-  /** ports are in host byte order */
-  u16_t local_port, remote_port;
-
-#if LWIP_MULTICAST_TX_OPTIONS
-  /** outgoing network interface for multicast packets */
-  ip_addr_t multicast_ip;
-  /** TTL for outgoing multicast packets */
-  u8_t mcast_ttl;
-#endif /* LWIP_MULTICAST_TX_OPTIONS */
-
-#if LWIP_UDPLITE
-  /** used for UDP_LITE only */
-  u16_t chksum_len_rx, chksum_len_tx;
-#endif /* LWIP_UDPLITE */
-
-  /** receive callback function */
-  udp_recv_fn recv;
-  /** user-supplied argument for the recv callback */
-  void *recv_arg;
-};
-/* udp_pcbs export for external reference (e.g. SNMP agent) */
-extern struct udp_pcb *udp_pcbs;
-
-/* The following functions is the application layer interface to the
-   UDP code. */
-struct udp_pcb * udp_new        (void);
-struct udp_pcb * udp_new_ip_type(u8_t type);
-void             udp_remove     (struct udp_pcb *pcb);
-err_t            udp_bind       (struct udp_pcb *pcb, const ip_addr_t *ipaddr,
-                                 u16_t port);
-err_t            udp_connect    (struct udp_pcb *pcb, const ip_addr_t *ipaddr,
-                                 u16_t port);
-void             udp_disconnect (struct udp_pcb *pcb);
-void             udp_recv       (struct udp_pcb *pcb, udp_recv_fn recv,
-                                 void *recv_arg);
-err_t            udp_sendto_if  (struct udp_pcb *pcb, struct pbuf *p,
-                                 const ip_addr_t *dst_ip, u16_t dst_port,
-                                 struct netif *netif);
-err_t            udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p,
-                                 const ip_addr_t *dst_ip, u16_t dst_port,
-                                 struct netif *netif, const ip_addr_t *src_ip);
-err_t            udp_sendto     (struct udp_pcb *pcb, struct pbuf *p,
-                                 const ip_addr_t *dst_ip, u16_t dst_port);
-err_t            udp_send       (struct udp_pcb *pcb, struct pbuf *p);
-
-#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
-err_t            udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p,
-                                 const ip_addr_t *dst_ip, u16_t dst_port,
-                                 struct netif *netif, u8_t have_chksum,
-                                 u16_t chksum);
-err_t            udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p,
-                                 const ip_addr_t *dst_ip, u16_t dst_port,
-                                 u8_t have_chksum, u16_t chksum);
-err_t            udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p,
-                                 u8_t have_chksum, u16_t chksum);
-err_t            udp_sendto_if_src_chksum(struct udp_pcb *pcb, struct pbuf *p,
-                                 const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif,
-                                 u8_t have_chksum, u16_t chksum, const ip_addr_t *src_ip);
-#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
-
-#define          udp_flags(pcb) ((pcb)->flags)
-#define          udp_setflags(pcb, f)  ((pcb)->flags = (f))
-
-/* The following functions are the lower layer interface to UDP. */
-void             udp_input      (struct pbuf *p, struct netif *inp);
-
-void             udp_init       (void);
-
-/* for compatibility with older implementation */
-#define udp_new_ip6() udp_new_ip_type(IPADDR_TYPE_V6)
-
-#if LWIP_MULTICAST_TX_OPTIONS
-#define udp_set_multicast_netif_addr(pcb, ip4addr) ip_addr_copy_from_ip4((pcb)->multicast_ip, *(ip4addr))
-#define udp_get_multicast_netif_addr(pcb)          ip_2_ip4(&(pcb)->multicast_ip)
-#define udp_set_multicast_ttl(pcb, value)      do { (pcb)->mcast_ttl = value; } while(0)
-#define udp_get_multicast_ttl(pcb)                 ((pcb)->mcast_ttl)
-
-#if ESP_LWIP
-#if LWIP_IPV6_MLD
-#define udp_set_multicast_netif_ip6addr(pcb, ip6addr) ip_addr_copy_from_ip6((pcb)->multicast_ip, *(ip6addr))
-#define udp_get_multicast_netif_ip6addr(pcb)          ip_2_ip6(&(pcb)->multicast_ip)
-#endif
-#endif
-
-#endif /* LWIP_MULTICAST_TX_OPTIONS */
-
-#if UDP_DEBUG
-void udp_debug_print(struct udp_hdr *udphdr);
-#else
-#define udp_debug_print(udphdr)
-#endif
-
-void udp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_UDP */
-
-#endif /* LWIP_HDR_UDP_H */
diff --git a/tools/sdk/include/lwip/lwipopts.h b/tools/sdk/include/lwip/lwipopts.h
deleted file mode 100644
index f213aeef184..00000000000
--- a/tools/sdk/include/lwip/lwipopts.h
+++ /dev/null
@@ -1,936 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Simon Goldschmidt
- *
- */
-#ifndef __LWIPOPTS_H__
-#define __LWIPOPTS_H__
-
-#include <stdlib.h>
-#include <time.h>
-#include <unistd.h>
-#include <sys/time.h>
-#include <sys/fcntl.h>
-#include <sys/ioctl.h>
-#include <sys/types.h>
-#include <sys/select.h>
-#include "esp_task.h"
-#include "esp_system.h"
-#include "sdkconfig.h"
-#include "sntp.h"
-#include "netif/dhcp_state.h"
-
-/* Enable all Espressif-only options */
-
-/*
-   -----------------------------------------------
-   ---------- Platform specific locking ----------
-   -----------------------------------------------
-*/
-/**
- * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
- * critical regions during buffer allocation, deallocation and memory
- * allocation and deallocation.
- */
-#define SYS_LIGHTWEIGHT_PROT        1
-
-/**
- * MEMCPY: override this if you have a faster implementation at hand than the
- * one included in your C library
- */
-#define MEMCPY(dst,src,len)             memcpy(dst,src,len)
-
-/**
- * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
- * call to memcpy() if the length is known at compile time and is small.
- */
-#define SMEMCPY(dst,src,len)            memcpy(dst,src,len)
-
-#define LWIP_RAND       esp_random
-
-/*
-   ------------------------------------
-   ---------- Memory options ----------
-   ------------------------------------
-*/
-/**
- * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
- * instead of the lwip internal allocator. Can save code size if you
- * already use it.
- */
-#define MEM_LIBC_MALLOC        1
-
-/**
-* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
-* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
-* speed and usage from interrupts!
-*/
-#define MEMP_MEM_MALLOC                 1
-
-/**
- * MEM_ALIGNMENT: should be set to the alignment of the CPU
- *    4 byte alignment -> #define MEM_ALIGNMENT 4
- *    2 byte alignment -> #define MEM_ALIGNMENT 2
- */
-#define MEM_ALIGNMENT           4
-
-/*
-   ------------------------------------------------
-   ---------- Internal Memory Pool Sizes ----------
-   ------------------------------------------------
-*/
-
-/**
- * MEMP_NUM_NETCONN: the number of struct netconns.
- * (only needed if you use the sequential API, like api_lib.c)
- */
-#define MEMP_NUM_NETCONN                CONFIG_LWIP_MAX_SOCKETS
-
-/**
- * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
- * (requires the LWIP_RAW option)
- */
-#define MEMP_NUM_RAW_PCB                CONFIG_LWIP_MAX_RAW_PCBS
-
-/**
- * MEMP_NUM_TCP_PCB: the number of simultaneously active TCP connections.
- * (requires the LWIP_TCP option)
- */
-#define MEMP_NUM_TCP_PCB                CONFIG_LWIP_MAX_ACTIVE_TCP
-
-/**
- * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
- * (requires the LWIP_TCP option)
- */
-#define MEMP_NUM_TCP_PCB_LISTEN         CONFIG_LWIP_MAX_LISTENING_TCP
-
-/**
- * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
- * per active UDP "connection".
- * (requires the LWIP_UDP option)
- */
-#define MEMP_NUM_UDP_PCB                CONFIG_LWIP_MAX_UDP_PCBS
-
-/*
-   --------------------------------
-   ---------- ARP options -------
-   --------------------------------
-*/
-/**
- * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
- * resolution. By default, only the most recent packet is queued per IP address.
- * This is sufficient for most protocols and mainly reduces TCP connection
- * startup time. Set this to 1 if you know your application sends more than one
- * packet in a row to an IP address that is not in the ARP cache.
- */
-#define ARP_QUEUEING                    1
-
-/*
-   --------------------------------
-   ---------- IP options ----------
-   --------------------------------
-*/
-/**
- * IP_REASSEMBLY==1: Reassemble incoming fragmented IP4 packets. Note that
- * this option does not affect outgoing packet sizes, which can be controlled
- * via IP_FRAG.
- */
-#define IP_REASSEMBLY                   CONFIG_LWIP_IP4_REASSEMBLY
-
-/**
- * LWIP_IPV6_REASS==1: reassemble incoming IP6 packets that fragmented. Note that
- * this option does not affect outgoing packet sizes, which can be controlled
- * via LWIP_IPV6_FRAG.
- */
-#define LWIP_IPV6_REASS                 CONFIG_LWIP_IP6_REASSEMBLY
-
-/**
- * IP_FRAG==1: Fragment outgoing IP4 packets if their size exceeds MTU. Note
- * that this option does not affect incoming packet sizes, which can be
- * controlled via IP_REASSEMBLY.
- */
-#define IP_FRAG                         CONFIG_LWIP_IP4_FRAG
-
-/**
- * LWIP_IPV6_FRAG==1: Fragment outgoing IP6 packets if their size exceeds MTU. Note
- * that this option does not affect incoming packet sizes, which can be
- * controlled via IP_REASSEMBLY.
- */
-#define LWIP_IPV6_FRAG                  CONFIG_LWIP_IP6_FRAG
-
-/**
- * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
- * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
- * in this time, the whole packet is discarded.
- */
-#define IP_REASS_MAXAGE                 3
-
-/**
- * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
- * Since the received pbufs are enqueued, be sure to configure
- * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
- * packets even if the maximum amount of fragments is enqueued for reassembly!
- */
-#define IP_REASS_MAX_PBUFS              10
-
-/*
-   ----------------------------------
-   ---------- ICMP options ----------
-   ----------------------------------
-*/
-
-#define LWIP_BROADCAST_PING CONFIG_LWIP_BROADCAST_PING
-
-#define LWIP_MULTICAST_PING CONFIG_LWIP_MULTICAST_PING
-
-/*
-   ---------------------------------
-   ---------- RAW options ----------
-   ---------------------------------
-*/
-/**
- * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
- */
-#define LWIP_RAW                        1
-
-/*
-   ----------------------------------
-   ---------- DHCP options ----------
-   ----------------------------------
-*/
-/**
- * LWIP_DHCP==1: Enable DHCP module.
- */
-#define LWIP_DHCP                       1
-
-#define DHCP_MAXRTX                     0
-
-/**
- * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
- */
-#define DHCP_DOES_ARP_CHECK             CONFIG_LWIP_DHCP_DOES_ARP_CHECK
-
-
-/**
- * CONFIG_LWIP_DHCP_RESTORE_LAST_IP==1: Last valid IP address obtained from DHCP server
- * is restored after reset/power-up.
- */
-#if CONFIG_LWIP_DHCP_RESTORE_LAST_IP
-
-#define LWIP_DHCP_IP_ADDR_RESTORE()     dhcp_ip_addr_restore(netif)
-#define LWIP_DHCP_IP_ADDR_STORE()       dhcp_ip_addr_store(netif)
-#define LWIP_DHCP_IP_ADDR_ERASE()       dhcp_ip_addr_erase(esp_netif[tcpip_if])
-
-#endif
-
-/*
-   ------------------------------------
-   ---------- AUTOIP options ----------
-   ------------------------------------
-*/
-#ifdef CONFIG_LWIP_AUTOIP
-#define LWIP_AUTOIP                     1
-
-/**
-* LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
-* the same interface at the same time.
-*/
-#define LWIP_DHCP_AUTOIP_COOP           1
-
-/**
-* LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
-* that should be sent before falling back on AUTOIP. This can be set
-* as low as 1 to get an AutoIP address very quickly, but you should
-* be prepared to handle a changing IP address when DHCP overrides
-* AutoIP.
-*/
-#define LWIP_DHCP_AUTOIP_COOP_TRIES     CONFIG_LWIP_AUTOIP_TRIES
-
-#define LWIP_AUTOIP_MAX_CONFLICTS CONFIG_LWIP_AUTOIP_MAX_CONFLICTS
-
-#define LWIP_AUTOIP_RATE_LIMIT_INTERVAL CONFIG_LWIP_AUTOIP_RATE_LIMIT_INTERVAL
-
-#endif /* CONFIG_LWIP_AUTOIP */
-
-/*
-   ----------------------------------
-   ---------- SNMP options ----------
-   ----------------------------------
-*/
-/*
-   ----------------------------------
-   ---------- IGMP options ----------
-   ----------------------------------
-*/
-/**
- * LWIP_IGMP==1: Turn on IGMP module.
- */
-#define LWIP_IGMP                       1
-
-/*
-   ----------------------------------
-   ---------- DNS options -----------
-   ----------------------------------
-*/
-/**
- * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
- * transport.
- */
-#define LWIP_DNS                        1
-
-#define DNS_MAX_SERVERS                 3
-#define DNS_FALLBACK_SERVER_INDEX        (DNS_MAX_SERVERS - 1)
-
-/*
-   ---------------------------------
-   ---------- UDP options ----------
-   ---------------------------------
-*/
-/*
-   ---------------------------------
-   ---------- TCP options ----------
-   ---------------------------------
-*/
-
-
-/**
- * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
- * Define to 0 if your device is low on memory.
- */
-#define TCP_QUEUE_OOSEQ                 CONFIG_TCP_QUEUE_OOSEQ
-
-/**
- * ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES==1: Keep TCP connection when IP changed
- * scenario happens: 192.168.0.2 -> 0.0.0.0 -> 192.168.0.2 or 192.168.0.2 -> 0.0.0.0
- */
-
-#define ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES  CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES
-/*
- *     LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
- *         events (accept, sent, etc) that happen in the system.
- *     LWIP_CALLBACK_API==1: The PCB callback function is called directly
- *         for the event. This is the default.
-*/
-#define TCP_MSS                         CONFIG_TCP_MSS
-
-/**
- * TCP_MSL: The maximum segment lifetime in milliseconds
- */
-#define TCP_MSL                         CONFIG_TCP_MSL
-
-/**
- * TCP_MAXRTX: Maximum number of retransmissions of data segments.
- */
-#define TCP_MAXRTX                      CONFIG_TCP_MAXRTX
-
-/**
- * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
- */
-#define TCP_SYNMAXRTX                   CONFIG_TCP_SYNMAXRTX
-
-/**
- * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
- */
-#define TCP_LISTEN_BACKLOG              1
-
-
-/**
- * TCP_OVERSIZE: The maximum number of bytes that tcp_write may
- * allocate ahead of time
- */
-#ifdef CONFIG_TCP_OVERSIZE_MSS
-#define TCP_OVERSIZE                    TCP_MSS
-#endif
-#ifdef CONFIG_TCP_OVERSIZE_QUARTER_MSS
-#define TCP_OVERSIZE                    (TCP_MSS/4)
-#endif
-#ifdef CONFIG_TCP_OVERSIZE_DISABLE
-#define TCP_OVERSIZE                    0
-#endif
-#ifndef TCP_OVERSIZE
-#error "One of CONFIG_TCP_OVERSIZE_xxx options should be set by sdkconfig"
-#endif
-
-/**
- * LWIP_WND_SCALE and TCP_RCV_SCALE:
- * Set LWIP_WND_SCALE to 1 to enable window scaling.
- * Set TCP_RCV_SCALE to the desired scaling factor (shift count in the
- * range of [0..14]).
- * When LWIP_WND_SCALE is enabled but TCP_RCV_SCALE is 0, we can use a large
- * send window while having a small receive window only.
- */
-#ifdef CONFIG_LWIP_WND_SCALE
-#define LWIP_WND_SCALE                  1
-#define TCP_RCV_SCALE                   CONFIG_TCP_RCV_SCALE
-#endif
-
-/**
- * LWIP_TCP_RTO_TIME: TCP rto time.
- * Default is 3 second.
- */
-#define LWIP_TCP_RTO_TIME             CONFIG_LWIP_TCP_RTO_TIME
-
-/**
- * Set TCP hook for Initial Sequence Number (ISN)
- */
-#ifdef CONFIG_LWIP_TCP_ISN_HOOK
-#include <lwip/arch.h>
-struct ip_addr;
-u32_t lwip_hook_tcp_isn(const struct ip_addr *local_ip, u16_t local_port,
-                        const struct ip_addr *remote_ip, u16_t remote_port);
-#define LWIP_HOOK_TCP_ISN               lwip_hook_tcp_isn
-#endif
-
-/*
-   ----------------------------------
-   ---------- Pbuf options ----------
-   ----------------------------------
-*/
-
-/*
-   ------------------------------------------------
-   ---------- Network Interfaces options ----------
-   ------------------------------------------------
-*/
-
-/**
- * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
- * field.
- */
-#define LWIP_NETIF_HOSTNAME             1
-
-/**
- * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
- * to be sent into one single pbuf. This is for compatibility with DMA-enabled
- * MACs that do not support scatter-gather.
- * Beware that this might involve CPU-memcpy before transmitting that would not
- * be needed without this flag! Use this only if you need to!
- *
- * @todo: TCP and IP-frag do not work with this, yet:
- */
-#define LWIP_NETIF_TX_SINGLE_PBUF             1
-
-/*
-   ------------------------------------
-   ---------- LOOPIF options ----------
-   ------------------------------------
-*/
-#ifdef CONFIG_LWIP_NETIF_LOOPBACK
-/**
- * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
- * address equal to the netif IP address, looping them back up the stack.
- */
-#define LWIP_NETIF_LOOPBACK             1
-
-/**
- * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
- * sending for each netif (0 = disabled)
- */
-#define LWIP_LOOPBACK_MAX_PBUFS         CONFIG_LWIP_LOOPBACK_MAX_PBUFS
-#endif
-
-/*
-   ------------------------------------
-   ---------- SLIPIF options ----------
-   ------------------------------------
-*/
-
-/*
-   ------------------------------------
-   ---------- Thread options ----------
-   ------------------------------------
-*/
-/**
- * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
- */
-#define TCPIP_THREAD_NAME              "tiT"
-
-/**
- * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
- * The stack size value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#define TCPIP_THREAD_STACKSIZE          ESP_TASK_TCPIP_STACK
-
-/**
- * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
- * The priority value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#define TCPIP_THREAD_PRIO               ESP_TASK_TCPIP_PRIO
-
-/**
- * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
- * The queue size value itself is platform-dependent, but is passed to
- * sys_mbox_new() when tcpip_init is called.
- */
-#define TCPIP_MBOX_SIZE                 CONFIG_TCPIP_RECVMBOX_SIZE
-
-/**
- * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
- * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
- * to sys_mbox_new() when the recvmbox is created.
- */
-#define DEFAULT_UDP_RECVMBOX_SIZE       CONFIG_UDP_RECVMBOX_SIZE
-
-/**
- * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
- * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
- * to sys_mbox_new() when the recvmbox is created.
- */
-#define DEFAULT_TCP_RECVMBOX_SIZE       CONFIG_TCP_RECVMBOX_SIZE
-
-/**
- * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
- * The queue size value itself is platform-dependent, but is passed to
- * sys_mbox_new() when the acceptmbox is created.
- */
-#define DEFAULT_ACCEPTMBOX_SIZE         6
-
-/**
- * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
- * The stack size value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#define DEFAULT_THREAD_STACKSIZE        TCPIP_THREAD_STACKSIZE
-
-/**
- * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
- * The priority value itself is platform-dependent, but is passed to
- * sys_thread_new() when the thread is created.
- */
-#define DEFAULT_THREAD_PRIO             TCPIP_THREAD_PRIO
-
-/**
- * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
- * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
- * to sys_mbox_new() when the recvmbox is created.
- */
-#define DEFAULT_RAW_RECVMBOX_SIZE       6
-
-/*
-   ----------------------------------------------
-   ---------- Sequential layer options ----------
-   ----------------------------------------------
-*/
-/**
- * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
- * Don't use it if you're not an active lwIP project member
- */
-#define LWIP_TCPIP_CORE_LOCKING         0
-
-/*
-   ------------------------------------
-   ---------- Socket options ----------
-   ------------------------------------
-*/
-/**
- * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
- * SO_SNDTIMEO processing.
- */
-#define LWIP_SO_SNDTIMEO                1
-
-/**
- * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first
- * local TCP/UDP pcb (default==0). This can prevent creating predictable port
- * numbers after booting a device.
- */
-#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS   CONFIG_LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS
-
-/**
- * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
- * SO_RCVTIMEO processing.
- */
-#define LWIP_SO_RCVTIMEO                1
-
-/**
- * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
- * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
- * in seconds. (does not require sockets.c, and will affect tcp.c)
- */
-#define LWIP_TCP_KEEPALIVE              1
-
-/**
- * LWIP_SO_LINGER==1: Enable SO_LINGER processing.
- */
-#define LWIP_SO_LINGER                  CONFIG_LWIP_SO_LINGER
-
-/**
- * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
- */
-#define LWIP_SO_RCVBUF                  CONFIG_LWIP_SO_RCVBUF
-
-/**
- * SO_REUSE==1: Enable SO_REUSEADDR option.
- * This option is set via menuconfig.
- */
-#define SO_REUSE                        CONFIG_LWIP_SO_REUSE
-
-/**
- * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets
- * to all local matches if SO_REUSEADDR is turned on.
- * WARNING: Adds a memcpy for every packet if passing to more than one pcb!
- */
-#define SO_REUSE_RXTOALL                CONFIG_LWIP_SO_REUSE_RXTOALL
-
-/*
-   ----------------------------------------
-   ---------- Statistics options ----------
-   ----------------------------------------
-*/
-
-/**
- * LWIP_STATS==1: Enable statistics collection in lwip_stats.
- */
-#define LWIP_STATS                      CONFIG_LWIP_STATS
-
-#if LWIP_STATS
-
-/**
- * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
- */
-#define LWIP_STATS_DISPLAY              CONFIG_LWIP_STATS
-#endif
-
-
-/*
-   ---------------------------------
-   ---------- PPP options ----------
-   ---------------------------------
-*/
-
-/**
- * PPP_SUPPORT==1: Enable PPP.
- */
-#define PPP_SUPPORT                     CONFIG_PPP_SUPPORT
-
-#if PPP_SUPPORT
-
-/**
- * PPP_NOTIFY_PHASE==1: Support PPP notify phase.
- */
-#define PPP_NOTIFY_PHASE                CONFIG_PPP_NOTIFY_PHASE_SUPPORT
-
-/**
- * PAP_SUPPORT==1: Support PAP.
- */
-#define PAP_SUPPORT                     CONFIG_PPP_PAP_SUPPORT
-
-/**
- * CHAP_SUPPORT==1: Support CHAP.
- */
-#define CHAP_SUPPORT                    CONFIG_PPP_CHAP_SUPPORT
-
-/**
- * MSCHAP_SUPPORT==1: Support MSCHAP.
- */
-#define MSCHAP_SUPPORT                  CONFIG_PPP_MSCHAP_SUPPORT
-
-/**
- * CCP_SUPPORT==1: Support CCP.
- */
-#define MPPE_SUPPORT                    CONFIG_PPP_MPPE_SUPPORT
-
-/**
- * PPP_MAXIDLEFLAG: Max Xmit idle time (in ms) before resend flag char.
- * TODO: If PPP_MAXIDLEFLAG > 0 and next package is send during PPP_MAXIDLEFLAG time,
- *       then 0x7E is not added at the begining of PPP package but 0x7E termination
- *       is always at the end. This behaviour brokes PPP dial with GSM (PPPoS).
- *       The PPP package should always start and end with 0x7E.
- */
-
-#define PPP_MAXIDLEFLAG                 0
-
-/**
- * PPP_DEBUG: Enable debugging for PPP.
- */
-#define PPP_DEBUG_ON					CONFIG_PPP_DEBUG_ON
-
-#if PPP_DEBUG_ON
-#define PPP_DEBUG                       LWIP_DBG_ON
-#else
-#define PPP_DEBUG                       LWIP_DBG_OFF
-#endif
-
-#endif
-
-/*
-   --------------------------------------
-   ---------- Checksum options ----------
-   --------------------------------------
-*/
-
-/*
-   ---------------------------------------
-   ---------- IPv6 options ---------------
-   ---------------------------------------
-*/
-/**
- * LWIP_IPV6==1: Enable IPv6
- */
-#define LWIP_IPV6                       1
-
-/**
- * LWIP_ND6_RDNSS_MAX_DNS_SERVERS: Allow IPv6 DNS servers to be retrieved from
- * NDP, up to the maximum number of allowed DNS servers (minus fallback slot)
- */
-#define LWIP_ND6_RDNSS_MAX_DNS_SERVERS  0
-
-/**
- * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution.
- */
-#define MEMP_NUM_ND6_QUEUE              CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE
-
-/**
- * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache
- */
-#define LWIP_ND6_NUM_NEIGHBORS          CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS
-
-/*
-   ---------------------------------------
-   ---------- Hook options ---------------
-   ---------------------------------------
-*/
-#define LWIP_HOOK_IP4_ROUTE_SRC         ip4_route_src_hook
-/*
-   ---------------------------------------
-   ---------- Debugging options ----------
-   ---------------------------------------
-*/
-/**
- * ETHARP_DEBUG: Enable debugging in etharp.c.
- */
-#define ETHARP_DEBUG                    LWIP_DBG_OFF
-
-/**
- * NETIF_DEBUG: Enable debugging in netif.c.
- */
-#define NETIF_DEBUG                     LWIP_DBG_OFF
-
-/**
- * PBUF_DEBUG: Enable debugging in pbuf.c.
- */
-#define PBUF_DEBUG                      LWIP_DBG_OFF
-
-/**
- * API_LIB_DEBUG: Enable debugging in api_lib.c.
- */
-#define API_LIB_DEBUG                   LWIP_DBG_OFF
-
-/**
- * SOCKETS_DEBUG: Enable debugging in sockets.c.
- */
-#define SOCKETS_DEBUG                   LWIP_DBG_OFF
-
-/**
- * ICMP_DEBUG: Enable debugging in icmp.c.
- */
-#define ICMP_DEBUG                      LWIP_DBG_OFF
-
-/**
- * IP_DEBUG: Enable debugging for IP.
- */
-#define IP_DEBUG                        LWIP_DBG_OFF
-
-/**
- * MEMP_DEBUG: Enable debugging in memp.c.
- */
-#define MEMP_DEBUG                      LWIP_DBG_OFF
-
-/**
- * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
- */
-#define TCP_INPUT_DEBUG                 LWIP_DBG_OFF
-
-/**
- * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
- */
-#define TCP_OUTPUT_DEBUG                LWIP_DBG_OFF
-
-/**
- * TCPIP_DEBUG: Enable debugging in tcpip.c.
- */
-#define TCPIP_DEBUG                     LWIP_DBG_OFF
-
-/**
- * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be
- * updated with the source MAC and IP addresses supplied in the packet.
- * You may want to disable this if you do not trust LAN peers to have the
- * correct addresses, or as a limited approach to attempt to handle
- * spoofing. If disabled, lwIP will need to make a new ARP request if
- * the peer is not already in the ARP table, adding a little latency.
- * The peer *is* in the ARP table if it requested our address before.
- * Also notice that this slows down input processing of every IP packet!
- */
-#define ETHARP_TRUST_IP_MAC             CONFIG_LWIP_ETHARP_TRUST_IP_MAC
-
-/**
- * ETHARP_SUPPORT_VLAN==1: support receiving and sending ethernet packets with
- * VLAN header. See the description of LWIP_HOOK_VLAN_CHECK and
- * LWIP_HOOK_VLAN_SET hooks to check/set VLAN headers.
- * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check.
- * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted.
- * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted.
- * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan)
- * that returns 1 to accept a packet or 0 to drop a packet.
- */
-#define ETHARP_SUPPORT_VLAN             CONFIG_ETHARP_SUPPORT_VLAN
-
-/**
- * POSIX I/O functions are mapped to LWIP via the VFS layer
- * (see port/vfs_lwip.c)
- */
-#define LWIP_POSIX_SOCKETS_IO_NAMES     0
-
-/**
- * FD_SETSIZE from sys/types.h is the maximum number of supported file
- * descriptors and CONFIG_LWIP_MAX_SOCKETS defines the number of sockets;
- * LWIP_SOCKET_OFFSET is configured to use the largest numbers of file
- * descriptors for sockets. File descriptors from 0 to LWIP_SOCKET_OFFSET-1
- * are non-socket descriptors and from LWIP_SOCKET_OFFSET to FD_SETSIZE are
- * socket descriptors.
- */
-#define LWIP_SOCKET_OFFSET              (FD_SETSIZE - CONFIG_LWIP_MAX_SOCKETS)
-
-/* Enable all Espressif-only options */
-
-#define ESP_LWIP                        1
-#define ESP_LWIP_ARP                    1
-#define ESP_IPV6                        1
-#define ESP_PER_SOC_TCP_WND             0
-#define ESP_THREAD_SAFE                 1
-#define ESP_THREAD_SAFE_DEBUG           LWIP_DBG_OFF
-#define ESP_DHCP                        1
-#define ESP_DNS                         1
-#define ESP_PERF                        0
-#define ESP_IP4_ATON                    1
-#define ESP_LIGHT_SLEEP                 1
-#define ESP_L2_TO_L3_COPY               CONFIG_L2_TO_L3_COPY
-#define ESP_STATS_MEM                   CONFIG_LWIP_STATS
-#define ESP_STATS_DROP                  CONFIG_LWIP_STATS
-#define ESP_STATS_TCP                   0
-#define ESP_DHCP_TIMER                  1
-#define ESP_DHCPS_TIMER                 1
-#define ESP_LWIP_LOGI(...)              ESP_LOGI("lwip", __VA_ARGS__)
-#define ESP_PING                        1
-#define ESP_HAS_SELECT                  1
-#define ESP_AUTO_RECV                   1
-#define ESP_GRATUITOUS_ARP              CONFIG_ESP_GRATUITOUS_ARP
-
-#ifdef CONFIG_LWIP_IPV6_AUTOCONFIG
-#define ESP_IPV6_AUTOCONFIG             CONFIG_LWIP_IPV6_AUTOCONFIG
-#endif
-
-#ifdef ESP_IRAM_ATTR
-#undef ESP_IRAM_ATTR
-#endif
-#define ESP_IRAM_ATTR
-
-#if ESP_PERF
-#define DBG_PERF_PATH_SET(dir, point)
-#define DBG_PERF_FILTER_LEN             1000
-
-enum {
-  DBG_PERF_DIR_RX = 0,
-  DBG_PERF_DIR_TX,
-};
-
-enum {
-  DBG_PERF_POINT_INT       = 0,
-  DBG_PERF_POINT_WIFI_IN   = 1,
-  DBG_PERF_POINT_WIFI_OUT  = 2,
-  DBG_PERF_POINT_LWIP_IN   = 3,
-  DBG_PERF_POINT_LWIP_OUT  = 4,
-  DBG_PERF_POINT_SOC_IN    = 5,
-  DBG_PERF_POINT_SOC_OUT   = 6,
-};
-
-#else
-#define DBG_PERF_PATH_SET(dir, point)
-#define DBG_PERF_FILTER_LEN             1000
-#endif
-
-#define TCP_SND_BUF                     CONFIG_TCP_SND_BUF_DEFAULT
-#define TCP_WND                         CONFIG_TCP_WND_DEFAULT
-
-#if ESP_PER_SOC_TCP_WND
-#define TCP_WND_DEFAULT                 CONFIG_TCP_WND_DEFAULT
-#define TCP_SND_BUF_DEFAULT             CONFIG_TCP_SND_BUF_DEFAULT
-#define TCP_WND(pcb)                    (pcb->per_soc_tcp_wnd)
-#define TCP_SND_BUF(pcb)                (pcb->per_soc_tcp_snd_buf)
-#define TCP_SND_QUEUELEN(pcb)           ((4 * (TCP_SND_BUF((pcb))) + (TCP_MSS - 1))/(TCP_MSS))
-#define TCP_SNDLOWAT(pcb)               LWIP_MIN(LWIP_MAX(((TCP_SND_BUF((pcb)))/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF((pcb))) - 1)
-#define TCP_SNDQUEUELOWAT(pcb)          LWIP_MAX(((TCP_SND_QUEUELEN((pcb)))/2), 5)
-#define TCP_WND_UPDATE_THRESHOLD(pcb)   LWIP_MIN((TCP_WND((pcb)) / 4), (TCP_MSS * 4))
-#endif
-
-/**
- * DHCP_DEBUG: Enable debugging in dhcp.c.
- */
-#define DHCP_DEBUG                      LWIP_DBG_OFF
-#define LWIP_DEBUG                      LWIP_DBG_OFF
-#define TCP_DEBUG                       LWIP_DBG_OFF
-
-#define CHECKSUM_CHECK_UDP              0
-#define CHECKSUM_CHECK_IP               0
-
-#define LWIP_NETCONN_FULLDUPLEX         1
-#define LWIP_NETCONN_SEM_PER_THREAD     1
-
-#define LWIP_DHCP_MAX_NTP_SERVERS       CONFIG_LWIP_DHCP_MAX_NTP_SERVERS
-#define LWIP_TIMEVAL_PRIVATE            0
-
-/*
-   --------------------------------------
-   ------------ SNTP options ------------
-   --------------------------------------
-*/
-/*
- * SNTP update delay - in milliseconds
- */
-#define SNTP_UPDATE_DELAY              CONFIG_LWIP_SNTP_UPDATE_DELAY
-
-#define SNTP_SET_SYSTEM_TIME_US(sec, us)  \
-    do { \
-        struct timeval tv = { .tv_sec = sec, .tv_usec = us }; \
-        sntp_sync_time(&tv); \
-    } while (0);
-
-#define SNTP_GET_SYSTEM_TIME(sec, us) \
-    do { \
-        struct timeval tv = { .tv_sec = 0, .tv_usec = 0 }; \
-        gettimeofday(&tv, NULL); \
-        (sec) = tv.tv_sec;  \
-        (us) = tv.tv_usec; \
-        sntp_set_sync_status(SNTP_SYNC_STATUS_RESET); \
-    } while (0);
-
-#define SOC_SEND_LOG //printf
-
-#endif /* __LWIPOPTS_H__ */
diff --git a/tools/sdk/include/lwip/netdb.h b/tools/sdk/include/lwip/netdb.h
deleted file mode 100644
index 7f5d67a4652..00000000000
--- a/tools/sdk/include/lwip/netdb.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
- * @file
- * This file is a posix wrapper for lwip/netdb.h.
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#include "lwip/netdb.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  
-#ifdef ESP_PLATFORM
-int getnameinfo(const struct sockaddr *addr, socklen_t addrlen,
-                char *host, socklen_t hostlen,
-                char *serv, socklen_t servlen, int flags);
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/lwip/netif/dhcp_state.h b/tools/sdk/include/lwip/netif/dhcp_state.h
deleted file mode 100644
index ffea1164011..00000000000
--- a/tools/sdk/include/lwip/netif/dhcp_state.h
+++ /dev/null
@@ -1,33 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef _DHCP_STATE_H_
-#define _DHCP_STATE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-bool dhcp_ip_addr_restore(void *netif);
-
-void dhcp_ip_addr_store(void *netif);
-
-void dhcp_ip_addr_erase(void *netif);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*  _DHCP_STATE_H_ */
\ No newline at end of file
diff --git a/tools/sdk/include/lwip/netif/etharp.h b/tools/sdk/include/lwip/netif/etharp.h
deleted file mode 100644
index b536fd280fa..00000000000
--- a/tools/sdk/include/lwip/netif/etharp.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* ARP has been moved to core/ipv4, provide this #include for compatibility only */
-#include "lwip/etharp.h"
-#include "netif/ethernet.h"
diff --git a/tools/sdk/include/lwip/netif/ethernet.h b/tools/sdk/include/lwip/netif/ethernet.h
deleted file mode 100644
index 49649cbf8b2..00000000000
--- a/tools/sdk/include/lwip/netif/ethernet.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
- * @file
- * Ethernet input function - handles INCOMING ethernet level traffic
- * To be used in most low-level netif implementations
- */
-
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * Copyright (c) 2003-2004 Leon Woestenberg <leon.woestenberg@axon.tv>
- * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-
-#ifndef LWIP_HDR_NETIF_ETHERNET_H
-#define LWIP_HDR_NETIF_ETHERNET_H
-
-#include "lwip/opt.h"
-
-#include "lwip/pbuf.h"
-#include "lwip/netif.h"
-#include "lwip/prot/ethernet.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if LWIP_ARP || LWIP_ETHERNET
-
-/** Define this to 1 and define LWIP_ARP_FILTER_NETIF_FN(pbuf, netif, type)
- * to a filter function that returns the correct netif when using multiple
- * netifs on one hardware interface where the netif's low-level receive
- * routine cannot decide for the correct netif (e.g. when mapping multiple
- * IP addresses to one hardware interface).
- */
-#ifndef LWIP_ARP_FILTER_NETIF
-#define LWIP_ARP_FILTER_NETIF 0
-#endif
-
-err_t ethernet_input(struct pbuf *p, struct netif *netif);
-err_t ethernet_output(struct netif* netif, struct pbuf* p, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type);
-
-extern const struct eth_addr ethbroadcast, ethzero;
-
-#endif /* LWIP_ARP || LWIP_ETHERNET */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_NETIF_ETHERNET_H */
diff --git a/tools/sdk/include/lwip/netif/ethernetif.h b/tools/sdk/include/lwip/netif/ethernetif.h
deleted file mode 100644
index 134e8eb5fe1..00000000000
--- a/tools/sdk/include/lwip/netif/ethernetif.h
+++ /dev/null
@@ -1,35 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef _ETH_LWIP_IF_H_
-#define _ETH_LWIP_IF_H_
-
-#include "lwip/err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-err_t ethernetif_init(struct netif *netif);
-
-void ethernetif_input(struct netif *netif, void *buffer, u16_t len);
-
-void netif_reg_addr_change_cb(void* cb);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*  _ETH_LWIP_IF_H_ */
diff --git a/tools/sdk/include/lwip/netif/lowpan6.h b/tools/sdk/include/lwip/netif/lowpan6.h
deleted file mode 100644
index 4174644bb36..00000000000
--- a/tools/sdk/include/lwip/netif/lowpan6.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- * @file
- *
- * 6LowPAN output for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units.
- */
-
-/*
- * Copyright (c) 2015 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-
-#ifndef LWIP_HDR_LOWPAN6_H
-#define LWIP_HDR_LOWPAN6_H
-
-#include "netif/lowpan6_opts.h"
-
-#if LWIP_IPV6 && LWIP_6LOWPAN /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/pbuf.h"
-#include "lwip/ip.h"
-#include "lwip/ip_addr.h"
-#include "lwip/netif.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** 1 second period */
-#define LOWPAN6_TMR_INTERVAL 1000
-
-void lowpan6_tmr(void);
-
-err_t lowpan6_set_context(u8_t index, const ip6_addr_t * context);
-err_t lowpan6_set_short_addr(u8_t addr_high, u8_t addr_low);
-
-#if LWIP_IPV4
-err_t lowpan4_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
-#endif /* LWIP_IPV4 */
-err_t lowpan6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr);
-err_t lowpan6_input(struct pbuf * p, struct netif *netif);
-err_t lowpan6_if_init(struct netif *netif);
-
-/* pan_id in network byte order. */
-err_t lowpan6_set_pan_id(u16_t pan_id);
-
-#if !NO_SYS
-err_t tcpip_6lowpan_input(struct pbuf *p, struct netif *inp);
-#endif /* !NO_SYS */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_IPV6 && LWIP_6LOWPAN */
-
-#endif /* LWIP_HDR_LOWPAN6_H */
diff --git a/tools/sdk/include/lwip/netif/lowpan6_opts.h b/tools/sdk/include/lwip/netif/lowpan6_opts.h
deleted file mode 100644
index fb93ea05de6..00000000000
--- a/tools/sdk/include/lwip/netif/lowpan6_opts.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/**
- * @file
- * 6LowPAN options list
- */
-
-/*
- * Copyright (c) 2015 Inico Technologies Ltd.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Ivan Delamer <delamer@inicotech.com>
- *
- *
- * Please coordinate changes and requests with Ivan Delamer
- * <delamer@inicotech.com>
- */
-
-#ifndef LWIP_HDR_LOWPAN6_OPTS_H
-#define LWIP_HDR_LOWPAN6_OPTS_H
-
-#include "lwip/opt.h"
-
-#ifndef LWIP_6LOWPAN
-#define LWIP_6LOWPAN                     0
-#endif
-
-#ifndef LWIP_6LOWPAN_NUM_CONTEXTS
-#define LWIP_6LOWPAN_NUM_CONTEXTS        10
-#endif
-
-#ifndef LWIP_6LOWPAN_INFER_SHORT_ADDRESS
-#define LWIP_6LOWPAN_INFER_SHORT_ADDRESS 1
-#endif
-
-#ifndef LWIP_6LOWPAN_IPHC
-#define LWIP_6LOWPAN_IPHC                1
-#endif
-
-#ifndef LWIP_6LOWPAN_HW_CRC
-#define LWIP_6LOWPAN_HW_CRC              1
-#endif
-
-#ifndef LOWPAN6_DEBUG
-#define LOWPAN6_DEBUG                    LWIP_DBG_OFF
-#endif
-
-#endif /* LWIP_HDR_LOWPAN6_OPTS_H */
diff --git a/tools/sdk/include/lwip/netif/ppp/ccp.h b/tools/sdk/include/lwip/netif/ppp/ccp.h
deleted file mode 100644
index 14dd65962c7..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/ccp.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * ccp.h - Definitions for PPP Compression Control Protocol.
- *
- * Copyright (c) 1994-2002 Paul Mackerras. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. The name(s) of the authors of this software must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission.
- *
- * 3. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Paul Mackerras
- *     <paulus@samba.org>".
- *
- * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
- * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: ccp.h,v 1.12 2004/11/04 10:02:26 paulus Exp $
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && CCP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-#ifndef CCP_H
-#define CCP_H
-
-/*
- * CCP codes.
- */
-
-#define CCP_CONFREQ	1
-#define CCP_CONFACK	2
-#define CCP_TERMREQ	5
-#define CCP_TERMACK	6
-#define CCP_RESETREQ	14
-#define CCP_RESETACK	15
-
-/*
- * Max # bytes for a CCP option
- */
-
-#define CCP_MAX_OPTION_LENGTH	32
-
-/*
- * Parts of a CCP packet.
- */
-
-#define CCP_CODE(dp)		((dp)[0])
-#define CCP_ID(dp)		((dp)[1])
-#define CCP_LENGTH(dp)		(((dp)[2] << 8) + (dp)[3])
-#define CCP_HDRLEN		4
-
-#define CCP_OPT_CODE(dp)	((dp)[0])
-#define CCP_OPT_LENGTH(dp)	((dp)[1])
-#define CCP_OPT_MINLEN		2
-
-#if BSDCOMPRESS_SUPPORT
-/*
- * Definitions for BSD-Compress.
- */
-
-#define CI_BSD_COMPRESS		21	/* config. option for BSD-Compress */
-#define CILEN_BSD_COMPRESS	3	/* length of config. option */
-
-/* Macros for handling the 3rd byte of the BSD-Compress config option. */
-#define BSD_NBITS(x)		((x) & 0x1F)	/* number of bits requested */
-#define BSD_VERSION(x)		((x) >> 5)	/* version of option format */
-#define BSD_CURRENT_VERSION	1		/* current version number */
-#define BSD_MAKE_OPT(v, n)	(((v) << 5) | (n))
-
-#define BSD_MIN_BITS		9	/* smallest code size supported */
-#define BSD_MAX_BITS		15	/* largest code size supported */
-#endif /* BSDCOMPRESS_SUPPORT */
-
-#if DEFLATE_SUPPORT
-/*
- * Definitions for Deflate.
- */
-
-#define CI_DEFLATE		26	/* config option for Deflate */
-#define CI_DEFLATE_DRAFT	24	/* value used in original draft RFC */
-#define CILEN_DEFLATE		4	/* length of its config option */
-
-#define DEFLATE_MIN_SIZE	9
-#define DEFLATE_MAX_SIZE	15
-#define DEFLATE_METHOD_VAL	8
-#define DEFLATE_SIZE(x)		(((x) >> 4) + 8)
-#define DEFLATE_METHOD(x)	((x) & 0x0F)
-#define DEFLATE_MAKE_OPT(w)	((((w) - 8) << 4) + DEFLATE_METHOD_VAL)
-#define DEFLATE_CHK_SEQUENCE	0
-#endif /* DEFLATE_SUPPORT */
-
-#if MPPE_SUPPORT
-/*
- * Definitions for MPPE.
- */
-
-#define CI_MPPE                18      /* config option for MPPE */
-#define CILEN_MPPE              6      /* length of config option */
-#endif /* MPPE_SUPPORT */
-
-#if PREDICTOR_SUPPORT
-/*
- * Definitions for other, as yet unsupported, compression methods.
- */
-
-#define CI_PREDICTOR_1		1	/* config option for Predictor-1 */
-#define CILEN_PREDICTOR_1	2	/* length of its config option */
-#define CI_PREDICTOR_2		2	/* config option for Predictor-2 */
-#define CILEN_PREDICTOR_2	2	/* length of its config option */
-#endif /* PREDICTOR_SUPPORT */
-
-typedef struct ccp_options {
-#if DEFLATE_SUPPORT
-    unsigned int deflate          :1; /* do Deflate? */
-    unsigned int deflate_correct  :1; /* use correct code for deflate? */
-    unsigned int deflate_draft    :1; /* use draft RFC code for deflate? */
-#endif /* DEFLATE_SUPPORT */
-#if BSDCOMPRESS_SUPPORT
-    unsigned int bsd_compress     :1; /* do BSD Compress? */
-#endif /* BSDCOMPRESS_SUPPORT */
-#if PREDICTOR_SUPPORT
-    unsigned int predictor_1      :1; /* do Predictor-1? */
-    unsigned int predictor_2      :1; /* do Predictor-2? */
-#endif /* PREDICTOR_SUPPORT */
-
-#if MPPE_SUPPORT
-    u8_t mppe;			/* MPPE bitfield */
-#endif /* MPPE_SUPPORT */
-#if BSDCOMPRESS_SUPPORT
-    u_short bsd_bits;		/* # bits/code for BSD Compress */
-#endif /* BSDCOMPRESS_SUPPORT */
-#if DEFLATE_SUPPORT
-    u_short deflate_size;	/* lg(window size) for Deflate */
-#endif /* DEFLATE_SUPPORT */
-    u8_t method;		/* code for chosen compression method */
-} ccp_options;
-
-extern const struct protent ccp_protent;
-
-void ccp_resetrequest(ppp_pcb *pcb);  /* Issue a reset-request. */
-
-#endif /* CCP_H */
-#endif /* PPP_SUPPORT && CCP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/chap-md5.h b/tools/sdk/include/lwip/netif/ppp/chap-md5.h
deleted file mode 100644
index eb0269fe508..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/chap-md5.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * chap-md5.h - New CHAP/MD5 implementation.
- *
- * Copyright (c) 2003 Paul Mackerras. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. The name(s) of the authors of this software must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission.
- *
- * 3. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Paul Mackerras
- *     <paulus@samba.org>".
- *
- * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
- * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && CHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-extern const struct chap_digest_type md5_digest;
-
-#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/chap-new.h b/tools/sdk/include/lwip/netif/ppp/chap-new.h
deleted file mode 100644
index 64eae322029..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/chap-new.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * chap-new.c - New CHAP implementation.
- *
- * Copyright (c) 2003 Paul Mackerras. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. The name(s) of the authors of this software must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission.
- *
- * 3. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Paul Mackerras
- *     <paulus@samba.org>".
- *
- * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
- * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && CHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-#ifndef CHAP_H
-#define CHAP_H
-
-#include "ppp.h"
-
-/*
- * CHAP packets begin with a standard header with code, id, len (2 bytes).
- */
-#define CHAP_HDRLEN	4
-
-/*
- * Values for the code field.
- */
-#define CHAP_CHALLENGE	1
-#define CHAP_RESPONSE	2
-#define CHAP_SUCCESS	3
-#define CHAP_FAILURE	4
-
-/*
- * CHAP digest codes.
- */
-#define CHAP_MD5		5
-#if MSCHAP_SUPPORT
-#define CHAP_MICROSOFT		0x80
-#define CHAP_MICROSOFT_V2	0x81
-#endif /* MSCHAP_SUPPORT */
-
-/*
- * Semi-arbitrary limits on challenge and response fields.
- */
-#define MAX_CHALLENGE_LEN	64
-#define MAX_RESPONSE_LEN	64
-
-/*
- * These limits apply to challenge and response packets we send.
- * The +4 is the +1 that we actually need rounded up.
- */
-#define CHAL_MAX_PKTLEN	(PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_CHALLENGE_LEN + MAXNAMELEN)
-#define RESP_MAX_PKTLEN	(PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_RESPONSE_LEN + MAXNAMELEN)
-
-/* bitmask of supported algorithms */
-#if MSCHAP_SUPPORT
-#define MDTYPE_MICROSOFT_V2	0x1
-#define MDTYPE_MICROSOFT	0x2
-#endif /* MSCHAP_SUPPORT */
-#define MDTYPE_MD5		0x4
-#define MDTYPE_NONE		0
-
-#if MSCHAP_SUPPORT
-/* Return the digest alg. ID for the most preferred digest type. */
-#define CHAP_DIGEST(mdtype) \
-    ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \
-    ((mdtype) & MDTYPE_MICROSOFT_V2)? CHAP_MICROSOFT_V2: \
-    ((mdtype) & MDTYPE_MICROSOFT)? CHAP_MICROSOFT: \
-    0
-#else /* !MSCHAP_SUPPORT */
-#define CHAP_DIGEST(mdtype) \
-    ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \
-    0
-#endif /* MSCHAP_SUPPORT */
-
-/* Return the bit flag (lsb set) for our most preferred digest type. */
-#define CHAP_MDTYPE(mdtype) ((mdtype) ^ ((mdtype) - 1)) & (mdtype)
-
-/* Return the bit flag for a given digest algorithm ID. */
-#if MSCHAP_SUPPORT
-#define CHAP_MDTYPE_D(digest) \
-    ((digest) == CHAP_MICROSOFT_V2)? MDTYPE_MICROSOFT_V2: \
-    ((digest) == CHAP_MICROSOFT)? MDTYPE_MICROSOFT: \
-    ((digest) == CHAP_MD5)? MDTYPE_MD5: \
-    0
-#else /* !MSCHAP_SUPPORT */
-#define CHAP_MDTYPE_D(digest) \
-    ((digest) == CHAP_MD5)? MDTYPE_MD5: \
-    0
-#endif /* MSCHAP_SUPPORT */
-
-/* Can we do the requested digest? */
-#if MSCHAP_SUPPORT
-#define CHAP_CANDIGEST(mdtype, digest) \
-    ((digest) == CHAP_MICROSOFT_V2)? (mdtype) & MDTYPE_MICROSOFT_V2: \
-    ((digest) == CHAP_MICROSOFT)? (mdtype) & MDTYPE_MICROSOFT: \
-    ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \
-    0
-#else /* !MSCHAP_SUPPORT */
-#define CHAP_CANDIGEST(mdtype, digest) \
-    ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \
-    0
-#endif /* MSCHAP_SUPPORT */
-
-/*
- * The code for each digest type has to supply one of these.
- */
-struct chap_digest_type {
-	int code;
-
-#if PPP_SERVER
-	/*
-	 * Note: challenge and response arguments below are formatted as
-	 * a length byte followed by the actual challenge/response data.
-	 */
-	void (*generate_challenge)(ppp_pcb *pcb, unsigned char *challenge);
-	int (*verify_response)(ppp_pcb *pcb, int id, const char *name,
-		const unsigned char *secret, int secret_len,
-		const unsigned char *challenge, const unsigned char *response,
-		char *message, int message_space);
-#endif /* PPP_SERVER */
-	void (*make_response)(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name,
-		const unsigned char *challenge, const char *secret, int secret_len,
-		unsigned char *priv);
-	int (*check_success)(ppp_pcb *pcb, unsigned char *pkt, int len, unsigned char *priv);
-	void (*handle_failure)(ppp_pcb *pcb, unsigned char *pkt, int len);
-};
-
-/*
- * Each interface is described by chap structure.
- */
-#if CHAP_SUPPORT
-typedef struct chap_client_state {
-	u8_t flags;
-	const char *name;
-	const struct chap_digest_type *digest;
-	unsigned char priv[64];		/* private area for digest's use */
-} chap_client_state;
-
-#if PPP_SERVER
-typedef struct chap_server_state {
-	u8_t flags;
-	u8_t id;
-	const char *name;
-	const struct chap_digest_type *digest;
-	int challenge_xmits;
-	int challenge_pktlen;
-	unsigned char challenge[CHAL_MAX_PKTLEN];
-} chap_server_state;
-#endif /* PPP_SERVER */
-#endif /* CHAP_SUPPORT */
-
-#if 0 /* UNUSED */
-/* Hook for a plugin to validate CHAP challenge */
-extern int (*chap_verify_hook)(char *name, char *ourname, int id,
-			const struct chap_digest_type *digest,
-			unsigned char *challenge, unsigned char *response,
-			char *message, int message_space);
-#endif /* UNUSED */
-
-#if PPP_SERVER
-/* Called by authentication code to start authenticating the peer. */
-extern void chap_auth_peer(ppp_pcb *pcb, const char *our_name, int digest_code);
-#endif /* PPP_SERVER */
-
-/* Called by auth. code to start authenticating us to the peer. */
-extern void chap_auth_with_peer(ppp_pcb *pcb, const char *our_name, int digest_code);
-
-/* Represents the CHAP protocol to the main pppd code */
-extern const struct protent chap_protent;
-
-#endif /* CHAP_H */
-#endif /* PPP_SUPPORT && CHAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/chap_ms.h b/tools/sdk/include/lwip/netif/ppp/chap_ms.h
deleted file mode 100644
index 0795291158f..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/chap_ms.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * chap_ms.h - Challenge Handshake Authentication Protocol definitions.
- *
- * Copyright (c) 1995 Eric Rosenquist.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name(s) of the authors of this software must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission.
- *
- * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
- * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: chap_ms.h,v 1.13 2004/11/15 22:13:26 paulus Exp $
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && MSCHAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-#ifndef CHAPMS_INCLUDE
-#define CHAPMS_INCLUDE
-
-extern const struct chap_digest_type chapms_digest;
-extern const struct chap_digest_type chapms2_digest;
-
-#endif /* CHAPMS_INCLUDE */
-
-#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/eap.h b/tools/sdk/include/lwip/netif/ppp/eap.h
deleted file mode 100644
index 3ee9aaf81ae..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/eap.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * eap.h - Extensible Authentication Protocol for PPP (RFC 2284)
- *
- * Copyright (c) 2001 by Sun Microsystems, Inc.
- * All rights reserved.
- *
- * Non-exclusive rights to redistribute, modify, translate, and use
- * this software in source and binary forms, in whole or in part, is
- * hereby granted, provided that the above copyright notice is
- * duplicated in any source form, and that neither the name of the
- * copyright holder nor the author is used to endorse or promote
- * products derived from this software.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Original version by James Carlson
- *
- * $Id: eap.h,v 1.2 2003/06/11 23:56:26 paulus Exp $
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && EAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-#ifndef PPP_EAP_H
-#define	PPP_EAP_H
-
-#include "ppp.h"
-
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-/*
- * Packet header = Code, id, length.
- */
-#define	EAP_HEADERLEN	4
-
-
-/* EAP message codes. */
-#define	EAP_REQUEST	1
-#define	EAP_RESPONSE	2
-#define	EAP_SUCCESS	3
-#define	EAP_FAILURE	4
-
-/* EAP types */
-#define	EAPT_IDENTITY		1
-#define	EAPT_NOTIFICATION	2
-#define	EAPT_NAK		3	/* (response only) */
-#define	EAPT_MD5CHAP		4
-#define	EAPT_OTP		5	/* One-Time Password; RFC 1938 */
-#define	EAPT_TOKEN		6	/* Generic Token Card */
-/* 7 and 8 are unassigned. */
-#define	EAPT_RSA		9	/* RSA Public Key Authentication */
-#define	EAPT_DSS		10	/* DSS Unilateral */
-#define	EAPT_KEA		11	/* KEA */
-#define	EAPT_KEA_VALIDATE	12	/* KEA-VALIDATE	*/
-#define	EAPT_TLS		13	/* EAP-TLS */
-#define	EAPT_DEFENDER		14	/* Defender Token (AXENT) */
-#define	EAPT_W2K		15	/* Windows 2000 EAP */
-#define	EAPT_ARCOT		16	/* Arcot Systems */
-#define	EAPT_CISCOWIRELESS	17	/* Cisco Wireless */
-#define	EAPT_NOKIACARD		18	/* Nokia IP smart card */
-#define	EAPT_SRP		19	/* Secure Remote Password */
-/* 20 is deprecated */
-
-/* EAP SRP-SHA1 Subtypes */
-#define	EAPSRP_CHALLENGE	1	/* Request 1 - Challenge */
-#define	EAPSRP_CKEY		1	/* Response 1 - Client Key */
-#define	EAPSRP_SKEY		2	/* Request 2 - Server Key */
-#define	EAPSRP_CVALIDATOR	2	/* Response 2 - Client Validator */
-#define	EAPSRP_SVALIDATOR	3	/* Request 3 - Server Validator */
-#define	EAPSRP_ACK		3	/* Response 3 - final ack */
-#define	EAPSRP_LWRECHALLENGE	4	/* Req/resp 4 - Lightweight rechal */
-
-#define	SRPVAL_EBIT	0x00000001	/* Use shared key for ECP */
-
-#define	SRP_PSEUDO_ID	"pseudo_"
-#define	SRP_PSEUDO_LEN	7
-
-#define MD5_SIGNATURE_SIZE	16
-#define EAP_MIN_CHALLENGE_LENGTH	17
-#define EAP_MAX_CHALLENGE_LENGTH	24
-#define EAP_MIN_MAX_POWER_OF_TWO_CHALLENGE_LENGTH     3   /* 2^3-1 = 7, 17+7 = 24 */
-
-#define	EAP_STATES	\
-	"Initial", "Pending", "Closed", "Listen", "Identify", \
-	"SRP1", "SRP2", "SRP3", "MD5Chall", "Open", "SRP4", "BadAuth"
-
-#define	eap_client_active(pcb)	((pcb)->eap.es_client.ea_state == eapListen)
-#if PPP_SERVER
-#define	eap_server_active(pcb)	\
-	((pcb)->eap.es_server.ea_state >= eapIdentify && \
-	 (pcb)->eap.es_server.ea_state <= eapMD5Chall)
-#endif /* PPP_SERVER */
-
-/*
- * Complete EAP state for one PPP session.
- */
-enum eap_state_code {
-	eapInitial = 0,	/* No EAP authentication yet requested */
-	eapPending,	/* Waiting for LCP (no timer) */
-	eapClosed,	/* Authentication not in use */
-	eapListen,	/* Client ready (and timer running) */
-	eapIdentify,	/* EAP Identify sent */
-	eapSRP1,	/* Sent EAP SRP-SHA1 Subtype 1 */
-	eapSRP2,	/* Sent EAP SRP-SHA1 Subtype 2 */
-	eapSRP3,	/* Sent EAP SRP-SHA1 Subtype 3 */
-	eapMD5Chall,	/* Sent MD5-Challenge */
-	eapOpen,	/* Completed authentication */
-	eapSRP4,	/* Sent EAP SRP-SHA1 Subtype 4 */
-	eapBadAuth	/* Failed authentication */
-};
-
-struct eap_auth {
-	const char *ea_name;	/* Our name */
-	char ea_peer[MAXNAMELEN +1];	/* Peer's name */
-	void *ea_session;	/* Authentication library linkage */
-	u_char *ea_skey;	/* Shared encryption key */
-	u_short ea_namelen;	/* Length of our name */
-	u_short ea_peerlen;	/* Length of peer's name */
-	enum eap_state_code ea_state;
-	u_char ea_id;		/* Current id */
-	u_char ea_requests;	/* Number of Requests sent/received */
-	u_char ea_responses;	/* Number of Responses */
-	u_char ea_type;		/* One of EAPT_* */
-	u32_t ea_keyflags;	/* SRP shared key usage flags */
-};
-
-#ifndef EAP_MAX_CHALLENGE_LENGTH
-#define EAP_MAX_CHALLENGE_LENGTH	24
-#endif
-typedef struct eap_state {
-	struct eap_auth es_client;	/* Client (authenticatee) data */
-#if PPP_SERVER
-	struct eap_auth es_server;	/* Server (authenticator) data */
-#endif /* PPP_SERVER */
-	int es_savedtime;		/* Saved timeout */
-	int es_rechallenge;		/* EAP rechallenge interval */
-	int es_lwrechallenge;		/* SRP lightweight rechallenge inter */
-	u8_t es_usepseudo;		/* Use SRP Pseudonym if offered one */
-	int es_usedpseudo;		/* Set if we already sent PN */
-	int es_challen;			/* Length of challenge string */
-	u_char es_challenge[EAP_MAX_CHALLENGE_LENGTH];
-} eap_state;
-
-/*
- * Timeouts.
- */
-#if 0 /* moved to ppp_opts.h */
-#define	EAP_DEFTIMEOUT		3	/* Timeout (seconds) for rexmit */
-#define	EAP_DEFTRANSMITS	10	/* max # times to transmit */
-#define	EAP_DEFREQTIME		20	/* Time to wait for peer request */
-#define	EAP_DEFALLOWREQ		20	/* max # times to accept requests */
-#endif /* moved to ppp_opts.h */
-
-void eap_authwithpeer(ppp_pcb *pcb, const char *localname);
-void eap_authpeer(ppp_pcb *pcb, const char *localname);
-
-extern const struct protent eap_protent;
-
-#ifdef	__cplusplus
-}
-#endif
-
-#endif /* PPP_EAP_H */
-
-#endif /* PPP_SUPPORT && EAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/ecp.h b/tools/sdk/include/lwip/netif/ppp/ecp.h
deleted file mode 100644
index 5cdce29d5b2..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/ecp.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * ecp.h - Definitions for PPP Encryption Control Protocol.
- *
- * Copyright (c) 2002 Google, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name(s) of the authors of this software must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission.
- *
- * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
- * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: ecp.h,v 1.2 2003/01/10 07:12:36 fcusack Exp $
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && ECP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-typedef struct ecp_options {
-    bool required;		/* Is ECP required? */
-    unsigned enctype;		/* Encryption type */
-} ecp_options;
-
-extern fsm ecp_fsm[];
-extern ecp_options ecp_wantoptions[];
-extern ecp_options ecp_gotoptions[];
-extern ecp_options ecp_allowoptions[];
-extern ecp_options ecp_hisoptions[];
-
-extern const struct protent ecp_protent;
-
-#endif /* PPP_SUPPORT && ECP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/eui64.h b/tools/sdk/include/lwip/netif/ppp/eui64.h
deleted file mode 100644
index 20ac22eede7..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/eui64.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * eui64.h - EUI64 routines for IPv6CP.
- *
- * Copyright (c) 1999 Tommi Komulainen.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name(s) of the authors of this software must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission.
- *
- * 4. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Tommi Komulainen
- *     <Tommi.Komulainen@iki.fi>".
- *
- * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
- * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: eui64.h,v 1.6 2002/12/04 23:03:32 paulus Exp $
-*/
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && PPP_IPV6_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-#ifndef EUI64_H
-#define EUI64_H
-
-/*
- * @todo:
- *
- * Maybe this should be done by processing struct in6_addr directly...
- */
-typedef union
-{
-    u8_t e8[8];
-    u16_t e16[4];
-    u32_t e32[2];
-} eui64_t;
-
-#define eui64_iszero(e)		(((e).e32[0] | (e).e32[1]) == 0)
-#define eui64_equals(e, o)	(((e).e32[0] == (o).e32[0]) && \
-				((e).e32[1] == (o).e32[1]))
-#define eui64_zero(e)		(e).e32[0] = (e).e32[1] = 0;
-
-#define eui64_copy(s, d)	memcpy(&(d), &(s), sizeof(eui64_t))
-
-#define eui64_magic(e)		do {			\
-				(e).e32[0] = magic();	\
-				(e).e32[1] = magic();	\
-				(e).e8[0] &= ~2;	\
-				} while (0)
-#define eui64_magic_nz(x)	do {				\
-				eui64_magic(x);			\
-				} while (eui64_iszero(x))
-#define eui64_magic_ne(x, y)	do {				\
-				eui64_magic(x);			\
-				} while (eui64_equals(x, y))
-
-#define eui64_get(ll, cp)	do {				\
-				eui64_copy((*cp), (ll));	\
-				(cp) += sizeof(eui64_t);	\
-				} while (0)
-
-#define eui64_put(ll, cp)	do {				\
-				eui64_copy((ll), (*cp));	\
-				(cp) += sizeof(eui64_t);	\
-				} while (0)
-
-#define eui64_set32(e, l)	do {			\
-				(e).e32[0] = 0;		\
-				(e).e32[1] = lwip_htonl(l);	\
-				} while (0)
-#define eui64_setlo32(e, l)	eui64_set32(e, l)
-
-char *eui64_ntoa(eui64_t);	/* Returns ascii representation of id */
-
-#endif /* EUI64_H */
-#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/fsm.h b/tools/sdk/include/lwip/netif/ppp/fsm.h
deleted file mode 100644
index b6915d3b807..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/fsm.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions.
- *
- * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name "Carnegie Mellon University" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For permission or any legal
- *    details, please contact
- *      Office of Technology Transfer
- *      Carnegie Mellon University
- *      5000 Forbes Avenue
- *      Pittsburgh, PA  15213-3890
- *      (412) 268-4387, fax: (412) 268-7395
- *      tech-transfer@andrew.cmu.edu
- *
- * 4. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Computing Services
- *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
- *
- * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
- * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: fsm.h,v 1.10 2004/11/13 02:28:15 paulus Exp $
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef FSM_H
-#define	FSM_H
-
-#include "ppp.h"
-
-/*
- * Packet header = Code, id, length.
- */
-#define HEADERLEN	4
-
-
-/*
- *  CP (LCP, IPCP, etc.) codes.
- */
-#define CONFREQ		1	/* Configuration Request */
-#define CONFACK		2	/* Configuration Ack */
-#define CONFNAK		3	/* Configuration Nak */
-#define CONFREJ		4	/* Configuration Reject */
-#define TERMREQ		5	/* Termination Request */
-#define TERMACK		6	/* Termination Ack */
-#define CODEREJ		7	/* Code Reject */
-
-
-/*
- * Each FSM is described by an fsm structure and fsm callbacks.
- */
-typedef struct fsm {
-    ppp_pcb *pcb;		/* PPP Interface */
-    const struct fsm_callbacks *callbacks;	/* Callback routines */
-    const char *term_reason;	/* Reason for closing protocol */
-    u8_t seen_ack;		/* Have received valid Ack/Nak/Rej to Req */
-				  /* -- This is our only flag, we might use u_int :1 if we have more flags */
-    u16_t protocol;		/* Data Link Layer Protocol field value */
-    u8_t state;			/* State */
-    u8_t flags;			/* Contains option bits */
-    u8_t id;			/* Current id */
-    u8_t reqid;			/* Current request id */
-    u8_t retransmits;		/* Number of retransmissions left */
-    u8_t nakloops;		/* Number of nak loops since last ack */
-    u8_t rnakloops;		/* Number of naks received */
-    u8_t maxnakloops;		/* Maximum number of nak loops tolerated
-				   (necessary because IPCP require a custom large max nak loops value) */
-    u8_t term_reason_len;	/* Length of term_reason */
-} fsm;
-
-
-typedef struct fsm_callbacks {
-    void (*resetci)		/* Reset our Configuration Information */
-		(fsm *);
-    int  (*cilen)		/* Length of our Configuration Information */
-		(fsm *);
-    void (*addci) 		/* Add our Configuration Information */
-		(fsm *, u_char *, int *);
-    int  (*ackci)		/* ACK our Configuration Information */
-		(fsm *, u_char *, int);
-    int  (*nakci)		/* NAK our Configuration Information */
-		(fsm *, u_char *, int, int);
-    int  (*rejci)		/* Reject our Configuration Information */
-		(fsm *, u_char *, int);
-    int  (*reqci)		/* Request peer's Configuration Information */
-		(fsm *, u_char *, int *, int);
-    void (*up)			/* Called when fsm reaches PPP_FSM_OPENED state */
-		(fsm *);
-    void (*down)		/* Called when fsm leaves PPP_FSM_OPENED state */
-		(fsm *);
-    void (*starting)		/* Called when we want the lower layer */
-		(fsm *);
-    void (*finished)		/* Called when we don't want the lower layer */
-		(fsm *);
-    void (*protreject)		/* Called when Protocol-Reject received */
-		(int);
-    void (*retransmit)		/* Retransmission is necessary */
-		(fsm *);
-    int  (*extcode)		/* Called when unknown code received */
-		(fsm *, int, int, u_char *, int);
-    const char *proto_name;	/* String name for protocol (for messages) */
-} fsm_callbacks;
-
-
-/*
- * Link states.
- */
-#define PPP_FSM_INITIAL		0	/* Down, hasn't been opened */
-#define PPP_FSM_STARTING	1	/* Down, been opened */
-#define PPP_FSM_CLOSED		2	/* Up, hasn't been opened */
-#define PPP_FSM_STOPPED		3	/* Open, waiting for down event */
-#define PPP_FSM_CLOSING		4	/* Terminating the connection, not open */
-#define PPP_FSM_STOPPING	5	/* Terminating, but open */
-#define PPP_FSM_REQSENT		6	/* We've sent a Config Request */
-#define PPP_FSM_ACKRCVD		7	/* We've received a Config Ack */
-#define PPP_FSM_ACKSENT		8	/* We've sent a Config Ack */
-#define PPP_FSM_OPENED		9	/* Connection available */
-
-
-/*
- * Flags - indicate options controlling FSM operation
- */
-#define OPT_PASSIVE	1	/* Don't die if we don't get a response */
-#define OPT_RESTART	2	/* Treat 2nd OPEN as DOWN, UP */
-#define OPT_SILENT	4	/* Wait for peer to speak first */
-
-
-/*
- * Timeouts.
- */
-#if 0 /* moved to ppp_opts.h */
-#define DEFTIMEOUT	3	/* Timeout time in seconds */
-#define DEFMAXTERMREQS	2	/* Maximum Terminate-Request transmissions */
-#define DEFMAXCONFREQS	10	/* Maximum Configure-Request transmissions */
-#define DEFMAXNAKLOOPS	5	/* Maximum number of nak loops */
-#endif /* moved to ppp_opts.h */
-
-
-/*
- * Prototypes
- */
-void fsm_init(fsm *f);
-void fsm_lowerup(fsm *f);
-void fsm_lowerdown(fsm *f);
-void fsm_open(fsm *f);
-void fsm_close(fsm *f, const char *reason);
-void fsm_input(fsm *f, u_char *inpacket, int l);
-void fsm_protreject(fsm *f);
-void fsm_sdata(fsm *f, u_char code, u_char id, const u_char *data, int datalen);
-
-
-#endif /* FSM_H */
-#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/ipcp.h b/tools/sdk/include/lwip/netif/ppp/ipcp.h
deleted file mode 100644
index 45f46b31ff6..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/ipcp.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * ipcp.h - IP Control Protocol definitions.
- *
- * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name "Carnegie Mellon University" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For permission or any legal
- *    details, please contact
- *      Office of Technology Transfer
- *      Carnegie Mellon University
- *      5000 Forbes Avenue
- *      Pittsburgh, PA  15213-3890
- *      (412) 268-4387, fax: (412) 268-7395
- *      tech-transfer@andrew.cmu.edu
- *
- * 4. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Computing Services
- *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
- *
- * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
- * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: ipcp.h,v 1.14 2002/12/04 23:03:32 paulus Exp $
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && PPP_IPV4_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef IPCP_H
-#define	IPCP_H
-
-/*
- * Options.
- */
-#define CI_ADDRS	1	/* IP Addresses */
-#if VJ_SUPPORT
-#define CI_COMPRESSTYPE	2	/* Compression Type */
-#endif /* VJ_SUPPORT */
-#define	CI_ADDR		3
-
-#if LWIP_DNS
-#define CI_MS_DNS1      129	/* Primary DNS value */
-#define CI_MS_DNS2      131     /* Secondary DNS value */
-#endif /* LWIP_DNS */
-#if 0 /* UNUSED - WINS */
-#define CI_MS_WINS1     130     /* Primary WINS value */
-#define CI_MS_WINS2     132	/* Secondary WINS value */
-#endif /* UNUSED - WINS */
-
-#if VJ_SUPPORT
-#define MAX_STATES 16		/* from slcompress.h */
-
-#define IPCP_VJMODE_OLD 1	/* "old" mode (option # = 0x0037) */
-#define IPCP_VJMODE_RFC1172 2	/* "old-rfc"mode (option # = 0x002d) */
-#define IPCP_VJMODE_RFC1332 3	/* "new-rfc"mode (option # = 0x002d, */
-                                /*  maxslot and slot number compression) */
-
-#define IPCP_VJ_COMP 0x002d	/* current value for VJ compression option*/
-#define IPCP_VJ_COMP_OLD 0x0037	/* "old" (i.e, broken) value for VJ */
-				/* compression option*/ 
-#endif /* VJ_SUPPORT */
-
-typedef struct ipcp_options {
-    unsigned int neg_addr               :1; /* Negotiate IP Address? */
-    unsigned int old_addrs              :1; /* Use old (IP-Addresses) option? */
-    unsigned int req_addr               :1; /* Ask peer to send IP address? */
-#if 0 /* UNUSED */
-    unsigned int default_route          :1; /* Assign default route through interface? */
-    unsigned int replace_default_route  :1; /* Replace default route through interface? */
-#endif /* UNUSED */
-#if 0 /* UNUSED - PROXY ARP */
-    unsigned int proxy_arp              :1; /* Make proxy ARP entry for peer? */
-#endif /* UNUSED - PROXY ARP */
-#if VJ_SUPPORT
-    unsigned int neg_vj                 :1; /* Van Jacobson Compression? */
-    unsigned int old_vj                 :1; /* use old (short) form of VJ option? */
-    unsigned int cflag                  :1;
-#endif /* VJ_SUPPORT */
-    unsigned int accept_local           :1; /* accept peer's value for ouraddr */
-    unsigned int accept_remote          :1; /* accept peer's value for hisaddr */
-#if LWIP_DNS
-    unsigned int req_dns1               :1; /* Ask peer to send primary DNS address? */
-    unsigned int req_dns2               :1; /* Ask peer to send secondary DNS address? */
-#endif /* LWIP_DNS */
-
-    u32_t ouraddr, hisaddr;	/* Addresses in NETWORK BYTE ORDER */
-#if LWIP_DNS
-    u32_t dnsaddr[2];	/* Primary and secondary MS DNS entries */
-#endif /* LWIP_DNS */
-#if 0 /* UNUSED - WINS */
-    u32_t winsaddr[2];	/* Primary and secondary MS WINS entries */
-#endif /* UNUSED - WINS */
-
-#if VJ_SUPPORT
-    u16_t vj_protocol;		/* protocol value to use in VJ option */
-    u8_t  maxslotindex;		/* values for RFC1332 VJ compression neg. */
-#endif /* VJ_SUPPORT */
-} ipcp_options;
-
-#if 0 /* UNUSED, already defined by lwIP */
-char *ip_ntoa (u32_t);
-#endif /* UNUSED, already defined by lwIP */
-
-extern const struct protent ipcp_protent;
-
-#endif /* IPCP_H */
-#endif /* PPP_SUPPORT && PPP_IPV4_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/ipv6cp.h b/tools/sdk/include/lwip/netif/ppp/ipv6cp.h
deleted file mode 100644
index 07d1ae31867..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/ipv6cp.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * ipv6cp.h - PPP IPV6 Control Protocol.
- *
- * Copyright (c) 1999 Tommi Komulainen.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name(s) of the authors of this software must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission.
- *
- * 4. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Tommi Komulainen
- *     <Tommi.Komulainen@iki.fi>".
- *
- * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
- * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-/*  Original version, based on RFC2023 :
-
-    Copyright (c) 1995, 1996, 1997 Francis.Dupont@inria.fr, INRIA Rocquencourt,
-    Alain.Durand@imag.fr, IMAG,
-    Jean-Luc.Richier@imag.fr, IMAG-LSR.
-
-    Copyright (c) 1998, 1999 Francis.Dupont@inria.fr, GIE DYADE,
-    Alain.Durand@imag.fr, IMAG,
-    Jean-Luc.Richier@imag.fr, IMAG-LSR.
-
-    Ce travail a été fait au sein du GIE DYADE (Groupement d'Intérêt
-    Économique ayant pour membres BULL S.A. et l'INRIA).
-
-    Ce logiciel informatique est disponible aux conditions
-    usuelles dans la recherche, c'est-à-dire qu'il peut
-    être utilisé, copié, modifié, distribué à l'unique
-    condition que ce texte soit conservé afin que
-    l'origine de ce logiciel soit reconnue.
-
-    Le nom de l'Institut National de Recherche en Informatique
-    et en Automatique (INRIA), de l'IMAG, ou d'une personne morale
-    ou physique ayant participé à l'élaboration de ce logiciel ne peut
-    être utilisé sans son accord préalable explicite.
-
-    Ce logiciel est fourni tel quel sans aucune garantie,
-    support ou responsabilité d'aucune sorte.
-    Ce logiciel est dérivé de sources d'origine
-    "University of California at Berkeley" et
-    "Digital Equipment Corporation" couvertes par des copyrights.
-
-    L'Institut d'Informatique et de Mathématiques Appliquées de Grenoble (IMAG)
-    est une fédération d'unités mixtes de recherche du CNRS, de l'Institut National
-    Polytechnique de Grenoble et de l'Université Joseph Fourier regroupant
-    sept laboratoires dont le laboratoire Logiciels, Systèmes, Réseaux (LSR).
-
-    This work has been done in the context of GIE DYADE (joint R & D venture
-    between BULL S.A. and INRIA).
-
-    This software is available with usual "research" terms
-    with the aim of retain credits of the software. 
-    Permission to use, copy, modify and distribute this software for any
-    purpose and without fee is hereby granted, provided that the above
-    copyright notice and this permission notice appear in all copies,
-    and the name of INRIA, IMAG, or any contributor not be used in advertising
-    or publicity pertaining to this material without the prior explicit
-    permission. The software is provided "as is" without any
-    warranties, support or liabilities of any kind.
-    This software is derived from source code from
-    "University of California at Berkeley" and
-    "Digital Equipment Corporation" protected by copyrights.
-
-    Grenoble's Institute of Computer Science and Applied Mathematics (IMAG)
-    is a federation of seven research units funded by the CNRS, National
-    Polytechnic Institute of Grenoble and University Joseph Fourier.
-    The research unit in Software, Systems, Networks (LSR) is member of IMAG.
-*/
-
-/*
- * Derived from :
- *
- *
- * ipcp.h - IP Control Protocol definitions.
- *
- * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name "Carnegie Mellon University" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For permission or any legal
- *    details, please contact
- *      Office of Technology Transfer
- *      Carnegie Mellon University
- *      5000 Forbes Avenue
- *      Pittsburgh, PA  15213-3890
- *      (412) 268-4387, fax: (412) 268-7395
- *      tech-transfer@andrew.cmu.edu
- *
- * 4. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Computing Services
- *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
- *
- * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
- * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: ipv6cp.h,v 1.7 2002/12/04 23:03:32 paulus Exp $
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && PPP_IPV6_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-#ifndef IPV6CP_H
-#define	IPV6CP_H
-
-#include "eui64.h"
-
-/*
- * Options.
- */
-#define CI_IFACEID	1	/* Interface Identifier */
-#ifdef IPV6CP_COMP
-#define CI_COMPRESSTYPE	2	/* Compression Type     */
-#endif /* IPV6CP_COMP */
-
-/* No compression types yet defined.
- *#define IPV6CP_COMP	0x004f
- */
-typedef struct ipv6cp_options {
-    unsigned int neg_ifaceid    :1;  /* Negotiate interface identifier? */
-    unsigned int req_ifaceid    :1;  /* Ask peer to send interface identifier? */
-    unsigned int accept_local   :1;  /* accept peer's value for iface id? */
-    unsigned int opt_local      :1;  /* ourtoken set by option */
-    unsigned int opt_remote     :1;  /* histoken set by option */
-    unsigned int use_ip         :1;  /* use IP as interface identifier */
-#if 0
-    unsigned int use_persistent :1;  /* use uniquely persistent value for address */
-#endif
-#ifdef IPV6CP_COMP
-    unsigned int neg_vj         :1;  /* Van Jacobson Compression? */
-#endif /* IPV6CP_COMP */
-
-#ifdef IPV6CP_COMP
-    u_short vj_protocol;        /* protocol value to use in VJ option */
-#endif /* IPV6CP_COMP */
-    eui64_t ourid, hisid;       /* Interface identifiers */
-} ipv6cp_options;
-
-extern const struct protent ipv6cp_protent;
-
-#endif /* IPV6CP_H */
-#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/lcp.h b/tools/sdk/include/lwip/netif/ppp/lcp.h
deleted file mode 100644
index 12e2a05fc90..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/lcp.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * lcp.h - Link Control Protocol definitions.
- *
- * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name "Carnegie Mellon University" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For permission or any legal
- *    details, please contact
- *      Office of Technology Transfer
- *      Carnegie Mellon University
- *      5000 Forbes Avenue
- *      Pittsburgh, PA  15213-3890
- *      (412) 268-4387, fax: (412) 268-7395
- *      tech-transfer@andrew.cmu.edu
- *
- * 4. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Computing Services
- *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
- *
- * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
- * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: lcp.h,v 1.20 2004/11/14 22:53:42 carlsonj Exp $
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef LCP_H
-#define	LCP_H
-
-#include "ppp.h"
-
-/*
- * Options.
- */
-#define CI_VENDOR	0	/* Vendor Specific */
-#define CI_MRU		1	/* Maximum Receive Unit */
-#define CI_ASYNCMAP	2	/* Async Control Character Map */
-#define CI_AUTHTYPE	3	/* Authentication Type */
-#define CI_QUALITY	4	/* Quality Protocol */
-#define CI_MAGICNUMBER	5	/* Magic Number */
-#define CI_PCOMPRESSION	7	/* Protocol Field Compression */
-#define CI_ACCOMPRESSION 8	/* Address/Control Field Compression */
-#define CI_FCSALTERN	9	/* FCS-Alternatives */
-#define CI_SDP		10	/* Self-Describing-Pad */
-#define CI_NUMBERED	11	/* Numbered-Mode */
-#define CI_CALLBACK	13	/* callback */
-#define CI_MRRU		17	/* max reconstructed receive unit; multilink */
-#define CI_SSNHF	18	/* short sequence numbers for multilink */
-#define CI_EPDISC	19	/* endpoint discriminator */
-#define CI_MPPLUS	22	/* Multi-Link-Plus-Procedure */
-#define CI_LDISC	23	/* Link-Discriminator */
-#define CI_LCPAUTH	24	/* LCP Authentication */
-#define CI_COBS		25	/* Consistent Overhead Byte Stuffing */
-#define CI_PREFELIS	26	/* Prefix Elision */
-#define CI_MPHDRFMT	27	/* MP Header Format */
-#define CI_I18N		28	/* Internationalization */
-#define CI_SDL		29	/* Simple Data Link */
-
-/*
- * LCP-specific packet types (code numbers).
- */
-#define PROTREJ		8	/* Protocol Reject */
-#define ECHOREQ		9	/* Echo Request */
-#define ECHOREP		10	/* Echo Reply */
-#define DISCREQ		11	/* Discard Request */
-#define IDENTIF		12	/* Identification */
-#define TIMEREM		13	/* Time Remaining */
-
-/* Value used as data for CI_CALLBACK option */
-#define CBCP_OPT	6	/* Use callback control protocol */
-
-#if 0 /* moved to ppp_opts.h */
-#define DEFMRU	1500		/* Try for this */
-#define MINMRU	128		/* No MRUs below this */
-#define MAXMRU	16384		/* Normally limit MRU to this */
-#endif /* moved to ppp_opts.h */
-
-/* An endpoint discriminator, used with multilink. */
-#define MAX_ENDP_LEN	20	/* maximum length of discriminator value */
-struct epdisc {
-    unsigned char	class_; /* -- The word "class" is reserved in C++. */
-    unsigned char	length;
-    unsigned char	value[MAX_ENDP_LEN];
-};
-
-/*
- * The state of options is described by an lcp_options structure.
- */
-typedef struct lcp_options {
-    unsigned int passive           :1; /* Don't die if we don't get a response */
-    unsigned int silent            :1; /* Wait for the other end to start first */
-#if 0 /* UNUSED */
-    unsigned int restart           :1; /* Restart vs. exit after close */
-#endif /* UNUSED */
-    unsigned int neg_mru           :1; /* Negotiate the MRU? */
-    unsigned int neg_asyncmap      :1; /* Negotiate the async map? */
-#if PAP_SUPPORT
-    unsigned int neg_upap          :1; /* Ask for UPAP authentication? */
-#endif /* PAP_SUPPORT */
-#if CHAP_SUPPORT
-    unsigned int neg_chap          :1; /* Ask for CHAP authentication? */
-#endif /* CHAP_SUPPORT */
-#if EAP_SUPPORT
-    unsigned int neg_eap           :1; /* Ask for EAP authentication? */
-#endif /* EAP_SUPPORT */
-    unsigned int neg_magicnumber   :1; /* Ask for magic number? */
-    unsigned int neg_pcompression  :1; /* HDLC Protocol Field Compression? */
-    unsigned int neg_accompression :1; /* HDLC Address/Control Field Compression? */
-#if LQR_SUPPORT
-    unsigned int neg_lqr           :1; /* Negotiate use of Link Quality Reports */
-#endif /* LQR_SUPPORT */
-    unsigned int neg_cbcp          :1; /* Negotiate use of CBCP */
-#ifdef HAVE_MULTILINK
-    unsigned int neg_mrru          :1; /* negotiate multilink MRRU */
-#endif /* HAVE_MULTILINK */
-    unsigned int neg_ssnhf         :1; /* negotiate short sequence numbers */
-    unsigned int neg_endpoint      :1; /* negotiate endpoint discriminator */
-
-    u16_t mru;			/* Value of MRU */
-#ifdef HAVE_MULTILINK
-    u16_t mrru;			/* Value of MRRU, and multilink enable */
-#endif /* MULTILINK */
-#if CHAP_SUPPORT
-    u8_t chap_mdtype;		/* which MD types (hashing algorithm) */
-#endif /* CHAP_SUPPORT */
-    u32_t asyncmap;		/* Value of async map */
-    u32_t magicnumber;
-    u8_t  numloops;		/* Number of loops during magic number neg. */
-#if LQR_SUPPORT
-    u32_t lqr_period;	/* Reporting period for LQR 1/100ths second */
-#endif /* LQR_SUPPORT */
-    struct epdisc endpoint;	/* endpoint discriminator */
-} lcp_options;
-
-void lcp_open(ppp_pcb *pcb);
-void lcp_close(ppp_pcb *pcb, const char *reason);
-void lcp_lowerup(ppp_pcb *pcb);
-void lcp_lowerdown(ppp_pcb *pcb);
-void lcp_sprotrej(ppp_pcb *pcb, u_char *p, int len);    /* send protocol reject */
-
-extern const struct protent lcp_protent;
-
-#if 0 /* moved to ppp_opts.h */
-/* Default number of times we receive our magic number from the peer
-   before deciding the link is looped-back. */
-#define DEFLOOPBACKFAIL	10
-#endif /* moved to ppp_opts.h */
-
-#endif /* LCP_H */
-#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/magic.h b/tools/sdk/include/lwip/netif/ppp/magic.h
deleted file mode 100644
index a2a9b530e58..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/magic.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * magic.h - PPP Magic Number definitions.
- *
- * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name "Carnegie Mellon University" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For permission or any legal
- *    details, please contact
- *      Office of Technology Transfer
- *      Carnegie Mellon University
- *      5000 Forbes Avenue
- *      Pittsburgh, PA  15213-3890
- *      (412) 268-4387, fax: (412) 268-7395
- *      tech-transfer@andrew.cmu.edu
- *
- * 4. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Computing Services
- *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
- *
- * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
- * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: magic.h,v 1.5 2003/06/11 23:56:26 paulus Exp $
- */
-/*****************************************************************************
-* randm.h - Random number generator header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* Copyright (c) 1998 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher <marc@mbsi.ca>
-*   Ported to lwIP.
-* 98-05-29 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
-*   Extracted from avos.
-*****************************************************************************/
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef MAGIC_H
-#define MAGIC_H
-
-/***********************
-*** PUBLIC FUNCTIONS ***
-***********************/
-
-/*
- * Initialize the random number generator.
- */
-void magic_init(void);
-
-/*
- * Randomize our random seed value.  To be called for truely random events
- * such as user operations and network traffic.
- */
-void magic_randomize(void);
-
-/*
- * Return a new random number.
- */
-u32_t magic(void);	/* Returns the next magic number */
-
-/*
- * Fill buffer with random bytes
- *
- * Use the random pool to generate random data.  This degrades to pseudo
- * random when used faster than randomness is supplied using magic_churnrand().
- * Thus it's important to make sure that the results of this are not
- * published directly because one could predict the next result to at
- * least some degree.  Also, it's important to get a good seed before
- * the first use.
- */
-void magic_random_bytes(unsigned char *buf, u32_t buf_len);
-
-/*
- * Return a new random number between 0 and (2^pow)-1 included.
- */
-u32_t magic_pow(u8_t pow);
-
-#endif /* MAGIC_H */
-
-#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/mppe.h b/tools/sdk/include/lwip/netif/ppp/mppe.h
deleted file mode 100644
index 1ae8a5d9247..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/mppe.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * mppe.h - Definitions for MPPE
- *
- * Copyright (c) 2008 Paul Mackerras. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name(s) of the authors of this software must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission.
- *
- * 4. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Paul Mackerras
- *     <paulus@samba.org>".
- *
- * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
- * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && MPPE_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-#ifndef MPPE_H
-#define MPPE_H
-
-#include "netif/ppp/pppcrypt.h"
-
-#define MPPE_PAD		4	/* MPPE growth per frame */
-#define MPPE_MAX_KEY_LEN	16	/* largest key length (128-bit) */
-
-/* option bits for ccp_options.mppe */
-#define MPPE_OPT_40		0x01	/* 40 bit */
-#define MPPE_OPT_128		0x02	/* 128 bit */
-#define MPPE_OPT_STATEFUL	0x04	/* stateful mode */
-/* unsupported opts */
-#define MPPE_OPT_56		0x08	/* 56 bit */
-#define MPPE_OPT_MPPC		0x10	/* MPPC compression */
-#define MPPE_OPT_D		0x20	/* Unknown */
-#define MPPE_OPT_UNSUPPORTED (MPPE_OPT_56|MPPE_OPT_MPPC|MPPE_OPT_D)
-#define MPPE_OPT_UNKNOWN	0x40	/* Bits !defined in RFC 3078 were set */
-
-/*
- * This is not nice ... the alternative is a bitfield struct though.
- * And unfortunately, we cannot share the same bits for the option
- * names above since C and H are the same bit.  We could do a u_int32
- * but then we have to do a lwip_htonl() all the time and/or we still need
- * to know which octet is which.
- */
-#define MPPE_C_BIT		0x01	/* MPPC */
-#define MPPE_D_BIT		0x10	/* Obsolete, usage unknown */
-#define MPPE_L_BIT		0x20	/* 40-bit */
-#define MPPE_S_BIT		0x40	/* 128-bit */
-#define MPPE_M_BIT		0x80	/* 56-bit, not supported */
-#define MPPE_H_BIT		0x01	/* Stateless (in a different byte) */
-
-/* Does not include H bit; used for least significant octet only. */
-#define MPPE_ALL_BITS (MPPE_D_BIT|MPPE_L_BIT|MPPE_S_BIT|MPPE_M_BIT|MPPE_H_BIT)
-
-/* Build a CI from mppe opts (see RFC 3078) */
-#define MPPE_OPTS_TO_CI(opts, ci)		\
-    do {					\
-	u_char *ptr = ci; /* u_char[4] */	\
-						\
-	/* H bit */				\
-	if (opts & MPPE_OPT_STATEFUL)		\
-	    *ptr++ = 0x0;			\
-	else					\
-	    *ptr++ = MPPE_H_BIT;		\
-	*ptr++ = 0;				\
-	*ptr++ = 0;				\
-						\
-	/* S,L bits */				\
-	*ptr = 0;				\
-	if (opts & MPPE_OPT_128)		\
-	    *ptr |= MPPE_S_BIT;			\
-	if (opts & MPPE_OPT_40)			\
-	    *ptr |= MPPE_L_BIT;			\
-	/* M,D,C bits not supported */		\
-    } while (/* CONSTCOND */ 0)
-
-/* The reverse of the above */
-#define MPPE_CI_TO_OPTS(ci, opts)		\
-    do {					\
-	const u_char *ptr = ci; /* u_char[4] */	\
-						\
-	opts = 0;				\
-						\
-	/* H bit */				\
-	if (!(ptr[0] & MPPE_H_BIT))		\
-	    opts |= MPPE_OPT_STATEFUL;		\
-						\
-	/* S,L bits */				\
-	if (ptr[3] & MPPE_S_BIT)		\
-	    opts |= MPPE_OPT_128;		\
-	if (ptr[3] & MPPE_L_BIT)		\
-	    opts |= MPPE_OPT_40;		\
-						\
-	/* M,D,C bits */			\
-	if (ptr[3] & MPPE_M_BIT)		\
-	    opts |= MPPE_OPT_56;		\
-	if (ptr[3] & MPPE_D_BIT)		\
-	    opts |= MPPE_OPT_D;			\
-	if (ptr[3] & MPPE_C_BIT)		\
-	    opts |= MPPE_OPT_MPPC;		\
-						\
-	/* Other bits */			\
-	if (ptr[0] & ~MPPE_H_BIT)		\
-	    opts |= MPPE_OPT_UNKNOWN;		\
-	if (ptr[1] || ptr[2])			\
-	    opts |= MPPE_OPT_UNKNOWN;		\
-	if (ptr[3] & ~MPPE_ALL_BITS)		\
-	    opts |= MPPE_OPT_UNKNOWN;		\
-    } while (/* CONSTCOND */ 0)
-
-/* Shared MPPE padding between MSCHAP and MPPE */
-#define SHA1_PAD_SIZE 40
-
-static const u8_t mppe_sha1_pad1[SHA1_PAD_SIZE] = {
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-static const u8_t mppe_sha1_pad2[SHA1_PAD_SIZE] = {
-  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
-  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
-  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2,
-  0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2
-};
-
-/*
- * State for an MPPE (de)compressor.
- */
-typedef struct ppp_mppe_state {
-	lwip_arc4_context arc4;
-	u8_t master_key[MPPE_MAX_KEY_LEN];
-	u8_t session_key[MPPE_MAX_KEY_LEN];
-	u8_t keylen;                /* key length in bytes */
-	/* NB: 128-bit == 16, 40-bit == 8!
-	 * If we want to support 56-bit, the unit has to change to bits
-	 */
-	u8_t bits;                  /* MPPE control bits */
-	u16_t ccount;               /* 12-bit coherency count (seqno)  */
-	u16_t sanity_errors;        /* take down LCP if too many */
-	unsigned int stateful  :1;  /* stateful mode flag */
-	unsigned int discard   :1;  /* stateful mode packet loss flag */
-} ppp_mppe_state;
-
-void mppe_set_key(ppp_pcb *pcb, ppp_mppe_state *state, u8_t *key);
-void mppe_init(ppp_pcb *pcb, ppp_mppe_state *state, u8_t options);
-void mppe_comp_reset(ppp_pcb *pcb, ppp_mppe_state *state);
-err_t mppe_compress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb, u16_t protocol);
-void mppe_decomp_reset(ppp_pcb *pcb, ppp_mppe_state *state);
-err_t mppe_decompress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb);
-
-#endif /* MPPE_H */
-#endif /* PPP_SUPPORT && MPPE_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/arc4.h b/tools/sdk/include/lwip/netif/ppp/polarssl/arc4.h
deleted file mode 100644
index 4af724cd900..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/polarssl/arc4.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/**
- * \file arc4.h
- *
- *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
- *
- *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
- *
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *  
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above copyright
- *      notice, this list of conditions and the following disclaimer in the
- *      documentation and/or other materials provided with the distribution.
- *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *  
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if LWIP_INCLUDED_POLARSSL_ARC4
-
-#ifndef LWIP_INCLUDED_POLARSSL_ARC4_H
-#define LWIP_INCLUDED_POLARSSL_ARC4_H
-
-/**
- * \brief          ARC4 context structure
- */
-typedef struct
-{
-    int x;                      /*!< permutation index */
-    int y;                      /*!< permutation index */
-    unsigned char m[256];       /*!< permutation table */
-}
-arc4_context;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          ARC4 key schedule
- *
- * \param ctx      ARC4 context to be initialized
- * \param key      the secret key
- * \param keylen   length of the key
- */
-void arc4_setup( arc4_context *ctx, unsigned char *key, int keylen );
-
-/**
- * \brief          ARC4 cipher function
- *
- * \param ctx      ARC4 context
- * \param buf      buffer to be processed
- * \param buflen   amount of data in buf
- */
-void arc4_crypt( arc4_context *ctx, unsigned char *buf, int buflen );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_INCLUDED_POLARSSL_ARC4_H */
-
-#endif /* LWIP_INCLUDED_POLARSSL_ARC4 */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/des.h b/tools/sdk/include/lwip/netif/ppp/polarssl/des.h
deleted file mode 100644
index e893890ed76..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/polarssl/des.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/**
- * \file des.h
- *
- *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
- *
- *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
- *
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *  
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above copyright
- *      notice, this list of conditions and the following disclaimer in the
- *      documentation and/or other materials provided with the distribution.
- *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *  
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if LWIP_INCLUDED_POLARSSL_DES
-
-#ifndef LWIP_INCLUDED_POLARSSL_DES_H
-#define LWIP_INCLUDED_POLARSSL_DES_H
-
-#define DES_ENCRYPT     1
-#define DES_DECRYPT     0
-
-/**
- * \brief          DES context structure
- */
-typedef struct
-{
-    int mode;                   /*!<  encrypt/decrypt   */
-    unsigned long sk[32];       /*!<  DES subkeys       */
-}
-des_context;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          DES key schedule (56-bit, encryption)
- *
- * \param ctx      DES context to be initialized
- * \param key      8-byte secret key
- */
-void des_setkey_enc( des_context *ctx, unsigned char key[8] );
-
-/**
- * \brief          DES key schedule (56-bit, decryption)
- *
- * \param ctx      DES context to be initialized
- * \param key      8-byte secret key
- */
-void des_setkey_dec( des_context *ctx, unsigned char key[8] );
-
-/**
- * \brief          DES-ECB block encryption/decryption
- *
- * \param ctx      DES context
- * \param input    64-bit input block
- * \param output   64-bit output block
- */
-void des_crypt_ecb( des_context *ctx,
-                    const unsigned char input[8],
-                    unsigned char output[8] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_INCLUDED_POLARSSL_DES_H */
-
-#endif /* LWIP_INCLUDED_POLARSSL_DES */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/md4.h b/tools/sdk/include/lwip/netif/ppp/polarssl/md4.h
deleted file mode 100644
index 570445687e1..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/polarssl/md4.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
- * \file md4.h
- *
- *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
- *
- *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
- *
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *  
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above copyright
- *      notice, this list of conditions and the following disclaimer in the
- *      documentation and/or other materials provided with the distribution.
- *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *  
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if LWIP_INCLUDED_POLARSSL_MD4
-
-#ifndef LWIP_INCLUDED_POLARSSL_MD4_H
-#define LWIP_INCLUDED_POLARSSL_MD4_H
-
-/**
- * \brief          MD4 context structure
- */
-typedef struct
-{
-    unsigned long total[2];     /*!< number of bytes processed  */
-    unsigned long state[4];     /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-}
-md4_context;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          MD4 context setup
- *
- * \param ctx      context to be initialized
- */
-void md4_starts( md4_context *ctx );
-
-/**
- * \brief          MD4 process buffer
- *
- * \param ctx      MD4 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void md4_update( md4_context *ctx, const unsigned char *input, int ilen );
-
-/**
- * \brief          MD4 final digest
- *
- * \param ctx      MD4 context
- * \param output   MD4 checksum result
- */
-void md4_finish( md4_context *ctx, unsigned char output[16] );
-
-/**
- * \brief          Output = MD4( input buffer )
- *
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- * \param output   MD4 checksum result
- */
-void md4( unsigned char *input, int ilen, unsigned char output[16] );
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_INCLUDED_POLARSSL_MD4_H */
-
-#endif /* LWIP_INCLUDED_POLARSSL_MD4 */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/md5.h b/tools/sdk/include/lwip/netif/ppp/polarssl/md5.h
deleted file mode 100644
index 12440118906..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/polarssl/md5.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
- * \file md5.h
- *
- *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
- *
- *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
- *
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *  
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above copyright
- *      notice, this list of conditions and the following disclaimer in the
- *      documentation and/or other materials provided with the distribution.
- *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *  
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if LWIP_INCLUDED_POLARSSL_MD5
-
-#ifndef LWIP_INCLUDED_POLARSSL_MD5_H
-#define LWIP_INCLUDED_POLARSSL_MD5_H
-
-/**
- * \brief          MD5 context structure
- */
-typedef struct
-{
-    unsigned long total[2];     /*!< number of bytes processed  */
-    unsigned long state[4];     /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-}
-md5_context;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          MD5 context setup
- *
- * \param ctx      context to be initialized
- */
-void md5_starts( md5_context *ctx );
-
-/**
- * \brief          MD5 process buffer
- *
- * \param ctx      MD5 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void md5_update( md5_context *ctx, const unsigned char *input, int ilen );
-
-/**
- * \brief          MD5 final digest
- *
- * \param ctx      MD5 context
- * \param output   MD5 checksum result
- */
-void md5_finish( md5_context *ctx, unsigned char output[16] );
-
-/**
- * \brief          Output = MD5( input buffer )
- *
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- * \param output   MD5 checksum result
- */
-void md5( unsigned char *input, int ilen, unsigned char output[16] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_INCLUDED_POLARSSL_MD5_H */
-
-#endif /* LWIP_INCLUDED_POLARSSL_MD5 */
diff --git a/tools/sdk/include/lwip/netif/ppp/polarssl/sha1.h b/tools/sdk/include/lwip/netif/ppp/polarssl/sha1.h
deleted file mode 100644
index a4c53e07c50..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/polarssl/sha1.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
- * \file sha1.h
- *
- *  Based on XySSL: Copyright (C) 2006-2008  Christophe Devine
- *
- *  Copyright (C) 2009  Paul Bakker <polarssl_maintainer at polarssl dot org>
- *
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *  
- *    * Redistributions of source code must retain the above copyright
- *      notice, this list of conditions and the following disclaimer.
- *    * Redistributions in binary form must reproduce the above copyright
- *      notice, this list of conditions and the following disclaimer in the
- *      documentation and/or other materials provided with the distribution.
- *    * Neither the names of PolarSSL or XySSL nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *  
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- *  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if LWIP_INCLUDED_POLARSSL_SHA1
-
-#ifndef LWIP_INCLUDED_POLARSSL_SHA1_H
-#define LWIP_INCLUDED_POLARSSL_SHA1_H
-
-/**
- * \brief          SHA-1 context structure
- */
-typedef struct
-{
-    unsigned long total[2];     /*!< number of bytes processed  */
-    unsigned long state[5];     /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-}
-sha1_context;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          SHA-1 context setup
- *
- * \param ctx      context to be initialized
- */
-void sha1_starts( sha1_context *ctx );
-
-/**
- * \brief          SHA-1 process buffer
- *
- * \param ctx      SHA-1 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void sha1_update( sha1_context *ctx, const unsigned char *input, int ilen );
-
-/**
- * \brief          SHA-1 final digest
- *
- * \param ctx      SHA-1 context
- * \param output   SHA-1 checksum result
- */
-void sha1_finish( sha1_context *ctx, unsigned char output[20] );
-
-/**
- * \brief          Output = SHA-1( input buffer )
- *
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- * \param output   SHA-1 checksum result
- */
-void sha1( unsigned char *input, int ilen, unsigned char output[20] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_INCLUDED_POLARSSL_SHA1_H */
-
-#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */
diff --git a/tools/sdk/include/lwip/netif/ppp/ppp.h b/tools/sdk/include/lwip/netif/ppp/ppp.h
deleted file mode 100644
index 3d73c365708..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/ppp.h
+++ /dev/null
@@ -1,698 +0,0 @@
-/*****************************************************************************
-* ppp.h - Network Point to Point Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher <marc@mbsi.ca>
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
-*   Original derived from BSD codes.
-*****************************************************************************/
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef PPP_H
-#define PPP_H
-
-#include "lwip/def.h"
-#include "lwip/stats.h"
-#include "lwip/mem.h"
-#include "lwip/netif.h"
-#include "lwip/sys.h"
-#include "lwip/timeouts.h"
-#if PPP_IPV6_SUPPORT
-#include "lwip/ip6_addr.h"
-#endif /* PPP_IPV6_SUPPORT */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Disable non-working or rarely used PPP feature, so rarely that we don't want to bloat ppp_opts.h with them */
-#ifndef PPP_OPTIONS
-#define PPP_OPTIONS         0
-#endif
-
-#ifndef PPP_NOTIFY
-#define PPP_NOTIFY          0
-#endif
-
-#ifndef PPP_REMOTENAME
-#define PPP_REMOTENAME      0
-#endif
-
-#ifndef PPP_IDLETIMELIMIT
-#define PPP_IDLETIMELIMIT   0
-#endif
-
-#ifndef PPP_LCP_ADAPTIVE
-#define PPP_LCP_ADAPTIVE    0
-#endif
-
-#ifndef PPP_MAXCONNECT
-#define PPP_MAXCONNECT      0
-#endif
-
-#ifndef PPP_ALLOWED_ADDRS
-#define PPP_ALLOWED_ADDRS   0
-#endif
-
-#ifndef PPP_PROTOCOLNAME
-#define PPP_PROTOCOLNAME    0
-#endif
-
-#ifndef PPP_STATS_SUPPORT
-#define PPP_STATS_SUPPORT   0
-#endif
-
-#ifndef DEFLATE_SUPPORT
-#define DEFLATE_SUPPORT     0
-#endif
-
-#ifndef BSDCOMPRESS_SUPPORT
-#define BSDCOMPRESS_SUPPORT 0
-#endif
-
-#ifndef PREDICTOR_SUPPORT
-#define PREDICTOR_SUPPORT   0
-#endif
-
-/*************************
-*** PUBLIC DEFINITIONS ***
-*************************/
-
-/*
- * The basic PPP frame.
- */
-#define PPP_HDRLEN	4	/* octets for standard ppp header */
-#define PPP_FCSLEN	2	/* octets for FCS */
-
-/*
- * Values for phase.
- */
-#define PPP_PHASE_DEAD          0
-#define PPP_PHASE_MASTER        1
-#define PPP_PHASE_HOLDOFF       2
-#define PPP_PHASE_INITIALIZE    3
-#define PPP_PHASE_SERIALCONN    4
-#define PPP_PHASE_DORMANT       5
-#define PPP_PHASE_ESTABLISH     6
-#define PPP_PHASE_AUTHENTICATE  7
-#define PPP_PHASE_CALLBACK      8
-#define PPP_PHASE_NETWORK       9
-#define PPP_PHASE_RUNNING       10
-#define PPP_PHASE_TERMINATE     11
-#define PPP_PHASE_DISCONNECT    12
-
-/* Error codes. */
-#define PPPERR_NONE         0  /* No error. */
-#define PPPERR_PARAM        1  /* Invalid parameter. */
-#define PPPERR_OPEN         2  /* Unable to open PPP session. */
-#define PPPERR_DEVICE       3  /* Invalid I/O device for PPP. */
-#define PPPERR_ALLOC        4  /* Unable to allocate resources. */
-#define PPPERR_USER         5  /* User interrupt. */
-#define PPPERR_CONNECT      6  /* Connection lost. */
-#define PPPERR_AUTHFAIL     7  /* Failed authentication challenge. */
-#define PPPERR_PROTOCOL     8  /* Failed to meet protocol. */
-#define PPPERR_PEERDEAD     9  /* Connection timeout */
-#define PPPERR_IDLETIMEOUT  10 /* Idle Timeout */
-#define PPPERR_CONNECTTIME  11 /* Max connect time reached */
-#define PPPERR_LOOPBACK     12 /* Loopback detected */
-
-/* Whether auth support is enabled at all */
-#define PPP_AUTH_SUPPORT (PAP_SUPPORT || CHAP_SUPPORT || EAP_SUPPORT)
-
-/************************
-*** PUBLIC DATA TYPES ***
-************************/
-
-/*
- * Other headers require ppp_pcb definition for prototypes, but ppp_pcb
- * require some structure definition from other headers as well, we are
- * fixing the dependency loop here by declaring the ppp_pcb type then
- * by including headers containing necessary struct definition for ppp_pcb
- */
-typedef struct ppp_pcb_s ppp_pcb;
-
-/* Type definitions for BSD code. */
-#ifndef __u_char_defined
-typedef unsigned long  u_long;
-typedef unsigned int   u_int;
-typedef unsigned short u_short;
-typedef unsigned char  u_char;
-#endif
-
-#include "fsm.h"
-#include "lcp.h"
-#if CCP_SUPPORT
-#include "ccp.h"
-#endif /* CCP_SUPPORT */
-#if MPPE_SUPPORT
-#include "mppe.h"
-#endif /* MPPE_SUPPORT */
-#if PPP_IPV4_SUPPORT
-#include "ipcp.h"
-#endif /* PPP_IPV4_SUPPORT */
-#if PPP_IPV6_SUPPORT
-#include "ipv6cp.h"
-#endif /* PPP_IPV6_SUPPORT */
-#if PAP_SUPPORT
-#include "upap.h"
-#endif /* PAP_SUPPORT */
-#if CHAP_SUPPORT
-#include "chap-new.h"
-#endif /* CHAP_SUPPORT */
-#if EAP_SUPPORT
-#include "eap.h"
-#endif /* EAP_SUPPORT */
-#if VJ_SUPPORT
-#include "vj.h"
-#endif /* VJ_SUPPORT */
-
-/* Link status callback function prototype */
-typedef void (*ppp_link_status_cb_fn)(ppp_pcb *pcb, int err_code, void *ctx);
-
-/*
- * PPP configuration.
- */
-typedef struct ppp_settings_s {
-
-#if PPP_SERVER && PPP_AUTH_SUPPORT
-  unsigned int  auth_required       :1;      /* Peer is required to authenticate */
-  unsigned int  null_login          :1;      /* Username of "" and a password of "" are acceptable */
-#endif /* PPP_SERVER && PPP_AUTH_SUPPORT */
-#if PPP_REMOTENAME
-  unsigned int  explicit_remote     :1;      /* remote_name specified with remotename opt */
-#endif /* PPP_REMOTENAME */
-#if PAP_SUPPORT
-  unsigned int  refuse_pap          :1;      /* Don't proceed auth. with PAP */
-#endif /* PAP_SUPPORT */
-#if CHAP_SUPPORT
-  unsigned int  refuse_chap         :1;      /* Don't proceed auth. with CHAP */
-#endif /* CHAP_SUPPORT */
-#if MSCHAP_SUPPORT
-  unsigned int  refuse_mschap       :1;      /* Don't proceed auth. with MS-CHAP */
-  unsigned int  refuse_mschap_v2    :1;      /* Don't proceed auth. with MS-CHAPv2 */
-#endif /* MSCHAP_SUPPORT */
-#if EAP_SUPPORT
-  unsigned int  refuse_eap          :1;      /* Don't proceed auth. with EAP */
-#endif /* EAP_SUPPORT */
-#if LWIP_DNS
-  unsigned int  usepeerdns          :1;      /* Ask peer for DNS adds */
-#endif /* LWIP_DNS */
-  unsigned int  persist             :1;      /* Persist mode, always try to open the connection */
-#if PRINTPKT_SUPPORT
-  unsigned int  hide_password       :1;      /* Hide password in dumped packets */
-#endif /* PRINTPKT_SUPPORT */
-  unsigned int  noremoteip          :1;      /* Let him have no IP address */
-  unsigned int  lax_recv            :1;      /* accept control chars in asyncmap */
-  unsigned int  noendpoint          :1;      /* don't send/accept endpoint discriminator */
-#if PPP_LCP_ADAPTIVE
-  unsigned int lcp_echo_adaptive    :1;      /* request echo only if the link was idle */
-#endif /* PPP_LCP_ADAPTIVE */
-#if MPPE_SUPPORT
-  unsigned int require_mppe         :1;      /* Require MPPE (Microsoft Point to Point Encryption) */
-  unsigned int refuse_mppe_40       :1;      /* Allow MPPE 40-bit mode? */
-  unsigned int refuse_mppe_128      :1;      /* Allow MPPE 128-bit mode? */
-  unsigned int refuse_mppe_stateful :1;      /* Allow MPPE stateful mode? */
-#endif /* MPPE_SUPPORT */
-
-  u16_t  listen_time;                 /* time to listen first (ms), waiting for peer to send LCP packet */
-
-#if PPP_IDLETIMELIMIT
-  u16_t  idle_time_limit;             /* Disconnect if idle for this many seconds */
-#endif /* PPP_IDLETIMELIMIT */
-#if PPP_MAXCONNECT
-  u32_t  maxconnect;                  /* Maximum connect time (seconds) */
-#endif /* PPP_MAXCONNECT */
-
-#if PPP_AUTH_SUPPORT
-  /* auth data */
-  const char  *user;                   /* Username for PAP */
-  const char  *passwd;                 /* Password for PAP, secret for CHAP */
-#if PPP_REMOTENAME
-  char  remote_name[MAXNAMELEN   + 1]; /* Peer's name for authentication */
-#endif /* PPP_REMOTENAME */
-
-#if PAP_SUPPORT
-  u8_t  pap_timeout_time;        /* Timeout (seconds) for auth-req retrans. */
-  u8_t  pap_max_transmits;       /* Number of auth-reqs sent */
-#if PPP_SERVER
-  u8_t  pap_req_timeout;         /* Time to wait for auth-req from peer */
-#endif /* PPP_SERVER */
-#endif /* PAP_SUPPPORT */
-
-#if CHAP_SUPPORT
-  u8_t  chap_timeout_time;       /* Timeout (seconds) for retransmitting req */
-  u8_t  chap_max_transmits;      /* max # times to send challenge */
-#if PPP_SERVER
-  u8_t  chap_rechallenge_time;   /* Time to wait for auth-req from peer */
-#endif /* PPP_SERVER */
-#endif /* CHAP_SUPPPORT */
-
-#if EAP_SUPPORT
-  u8_t  eap_req_time;            /* Time to wait (for retransmit/fail) */
-  u8_t  eap_allow_req;           /* Max Requests allowed */
-#if PPP_SERVER
-  u8_t  eap_timeout_time;        /* Time to wait (for retransmit/fail) */
-  u8_t  eap_max_transmits;       /* Max Requests allowed */
-#endif /* PPP_SERVER */
-#endif /* EAP_SUPPORT */
-
-#endif /* PPP_AUTH_SUPPORT */
-
-  u8_t  fsm_timeout_time;            /* Timeout time in seconds */
-  u8_t  fsm_max_conf_req_transmits;  /* Maximum Configure-Request transmissions */
-  u8_t  fsm_max_term_transmits;      /* Maximum Terminate-Request transmissions */
-  u8_t  fsm_max_nak_loops;           /* Maximum number of nak loops tolerated */
-
-  u8_t  lcp_loopbackfail;     /* Number of times we receive our magic number from the peer
-                                 before deciding the link is looped-back. */
-  u8_t  lcp_echo_interval;    /* Interval between LCP echo-requests */
-  u8_t  lcp_echo_fails;       /* Tolerance to unanswered echo-requests */
-
-} ppp_settings;
-
-#if PPP_SERVER
-struct ppp_addrs {
-#if PPP_IPV4_SUPPORT
-  ip4_addr_t our_ipaddr, his_ipaddr, netmask;
-#if LWIP_DNS
-  ip4_addr_t dns1, dns2;
-#endif /* LWIP_DNS */
-#endif /* PPP_IPV4_SUPPORT */
-#if PPP_IPV6_SUPPORT
-  ip6_addr_t our6_ipaddr, his6_ipaddr;
-#endif /* PPP_IPV6_SUPPORT */
-};
-#endif /* PPP_SERVER */
-
-/*
- * PPP interface control block.
- */
-struct ppp_pcb_s {
-  ppp_settings settings;
-  const struct link_callbacks *link_cb;
-  void *link_ctx_cb;
-  void (*link_status_cb)(ppp_pcb *pcb, int err_code, void *ctx);  /* Status change callback */
-#if PPP_NOTIFY_PHASE
-  void (*notify_phase_cb)(ppp_pcb *pcb, u8_t phase, void *ctx);   /* Notify phase callback */
-#endif /* PPP_NOTIFY_PHASE */
-  void *ctx_cb;                  /* Callbacks optional pointer */
-  struct netif *netif;           /* PPP interface */
-  u8_t phase;                    /* where the link is at */
-  u8_t err_code;                 /* Code indicating why interface is down. */
-
-  /* flags */
-#if PPP_IPV4_SUPPORT
-  unsigned int ask_for_local           :1; /* request our address from peer */
-  unsigned int ipcp_is_open            :1; /* haven't called np_finished() */
-  unsigned int ipcp_is_up              :1; /* have called ipcp_up() */
-  unsigned int if4_up                  :1; /* True when the IPv4 interface is up. */
-#if 0 /* UNUSED - PROXY ARP */
-  unsigned int proxy_arp_set           :1; /* Have created proxy arp entry */
-#endif /* UNUSED - PROXY ARP */
-#endif /* PPP_IPV4_SUPPORT */
-#if PPP_IPV6_SUPPORT
-  unsigned int ipv6cp_is_up            :1; /* have called ip6cp_up() */
-  unsigned int if6_up                  :1; /* True when the IPv6 interface is up. */
-#endif /* PPP_IPV6_SUPPORT */
-  unsigned int lcp_echo_timer_running  :1; /* set if a timer is running */
-#if VJ_SUPPORT
-  unsigned int vj_enabled              :1; /* Flag indicating VJ compression enabled. */
-#endif /* VJ_SUPPORT */
-#if CCP_SUPPORT
-  unsigned int ccp_all_rejected        :1; /* we rejected all peer's options */
-#endif /* CCP_SUPPORT */
-#if MPPE_SUPPORT
-  unsigned int mppe_keys_set           :1; /* Have the MPPE keys been set? */
-#endif /* MPPE_SUPPORT */
-
-#if PPP_AUTH_SUPPORT
-  /* auth data */
-#if PPP_SERVER && defined(HAVE_MULTILINK)
-  char peer_authname[MAXNAMELEN + 1]; /* The name by which the peer authenticated itself to us. */
-#endif /* PPP_SERVER && defined(HAVE_MULTILINK) */
-  u16_t auth_pending;        /* Records which authentication operations haven't completed yet. */
-  u16_t auth_done;           /* Records which authentication operations have been completed. */
-
-#if PAP_SUPPORT
-  upap_state upap;           /* PAP data */
-#endif /* PAP_SUPPORT */
-
-#if CHAP_SUPPORT
-  chap_client_state chap_client;  /* CHAP client data */
-#if PPP_SERVER
-  chap_server_state chap_server;  /* CHAP server data */
-#endif /* PPP_SERVER */
-#endif /* CHAP_SUPPORT */
-
-#if EAP_SUPPORT
-  eap_state eap;            /* EAP data */
-#endif /* EAP_SUPPORT */
-#endif /* PPP_AUTH_SUPPORT */
-
-  fsm lcp_fsm;                   /* LCP fsm structure */
-  lcp_options lcp_wantoptions;   /* Options that we want to request */
-  lcp_options lcp_gotoptions;    /* Options that peer ack'd */
-  lcp_options lcp_allowoptions;  /* Options we allow peer to request */
-  lcp_options lcp_hisoptions;    /* Options that we ack'd */
-  u16_t peer_mru;                /* currently negotiated peer MRU */
-  u8_t lcp_echos_pending;        /* Number of outstanding echo msgs */
-  u8_t lcp_echo_number;          /* ID number of next echo frame */
-
-  u8_t num_np_open;              /* Number of network protocols which we have opened. */
-  u8_t num_np_up;                /* Number of network protocols which have come up. */
-
-#if VJ_SUPPORT
-  struct vjcompress vj_comp;     /* Van Jacobson compression header. */
-#endif /* VJ_SUPPORT */
-
-#if CCP_SUPPORT
-  fsm ccp_fsm;                   /* CCP fsm structure */
-  ccp_options ccp_wantoptions;   /* what to request the peer to use */
-  ccp_options ccp_gotoptions;    /* what the peer agreed to do */
-  ccp_options ccp_allowoptions;  /* what we'll agree to do */
-  ccp_options ccp_hisoptions;    /* what we agreed to do */
-  u8_t ccp_localstate;           /* Local state (mainly for handling reset-reqs and reset-acks). */
-  u8_t ccp_receive_method;       /* Method chosen on receive path */
-  u8_t ccp_transmit_method;      /* Method chosen on transmit path */
-#if MPPE_SUPPORT
-  ppp_mppe_state mppe_comp;      /* MPPE "compressor" structure */
-  ppp_mppe_state mppe_decomp;    /* MPPE "decompressor" structure */
-#endif /* MPPE_SUPPORT */
-#endif /* CCP_SUPPORT */
-
-#if PPP_IPV4_SUPPORT
-  fsm ipcp_fsm;                   /* IPCP fsm structure */
-  ipcp_options ipcp_wantoptions;  /* Options that we want to request */
-  ipcp_options ipcp_gotoptions;   /* Options that peer ack'd */
-  ipcp_options ipcp_allowoptions; /* Options we allow peer to request */
-  ipcp_options ipcp_hisoptions;   /* Options that we ack'd */
-#endif /* PPP_IPV4_SUPPORT */
-
-#if PPP_IPV6_SUPPORT
-  fsm ipv6cp_fsm;                     /* IPV6CP fsm structure */
-  ipv6cp_options ipv6cp_wantoptions;  /* Options that we want to request */
-  ipv6cp_options ipv6cp_gotoptions;   /* Options that peer ack'd */
-  ipv6cp_options ipv6cp_allowoptions; /* Options we allow peer to request */
-  ipv6cp_options ipv6cp_hisoptions;   /* Options that we ack'd */
-#endif /* PPP_IPV6_SUPPORT */
-};
-
-/************************
- *** PUBLIC FUNCTIONS ***
- ************************/
-
-/*
- * WARNING: For multi-threads environment, all ppp_set_* functions most
- * only be called while the PPP is in the dead phase (i.e. disconnected).
- */
-
-#if PPP_AUTH_SUPPORT
-/*
- * Set PPP authentication.
- *
- * Warning: Using PPPAUTHTYPE_ANY might have security consequences.
- * RFC 1994 says:
- *
- * In practice, within or associated with each PPP server, there is a
- * database which associates "user" names with authentication
- * information ("secrets").  It is not anticipated that a particular
- * named user would be authenticated by multiple methods.  This would
- * make the user vulnerable to attacks which negotiate the least secure
- * method from among a set (such as PAP rather than CHAP).  If the same
- * secret was used, PAP would reveal the secret to be used later with
- * CHAP.
- *
- * Instead, for each user name there should be an indication of exactly
- * one method used to authenticate that user name.  If a user needs to
- * make use of different authentication methods under different
- * circumstances, then distinct user names SHOULD be employed, each of
- * which identifies exactly one authentication method.
- *
- * Default is none auth type, unset (NULL) user and passwd.
- */
-#define PPPAUTHTYPE_NONE      0x00
-#define PPPAUTHTYPE_PAP       0x01
-#define PPPAUTHTYPE_CHAP      0x02
-#define PPPAUTHTYPE_MSCHAP    0x04
-#define PPPAUTHTYPE_MSCHAP_V2 0x08
-#define PPPAUTHTYPE_EAP       0x10
-#define PPPAUTHTYPE_ANY       0xff
-void ppp_set_auth(ppp_pcb *pcb, u8_t authtype, const char *user, const char *passwd);
-
-/*
- * If set, peer is required to authenticate. This is mostly necessary for PPP server support.
- *
- * Default is false.
- */
-#define ppp_set_auth_required(ppp, boolval) (ppp->settings.auth_required = boolval)
-#endif /* PPP_AUTH_SUPPORT */
-
-#if PPP_IPV4_SUPPORT
-/*
- * Set PPP interface "our" and "his" IPv4 addresses. This is mostly necessary for PPP server
- * support but it can also be used on a PPP link where each side choose its own IP address.
- *
- * Default is unset (0.0.0.0).
- */
-#define ppp_set_ipcp_ouraddr(ppp, addr) do { ppp->ipcp_wantoptions.ouraddr = ip4_addr_get_u32(addr); \
-                                             ppp->ask_for_local = ppp->ipcp_wantoptions.ouraddr != 0; } while(0)
-#define ppp_set_ipcp_hisaddr(ppp, addr) (ppp->ipcp_wantoptions.hisaddr = ip4_addr_get_u32(addr))
-#if LWIP_DNS
-/*
- * Set DNS server addresses that are sent if the peer asks for them. This is mostly necessary
- * for PPP server support.
- *
- * Default is unset (0.0.0.0).
- */
-#define ppp_set_ipcp_dnsaddr(ppp, index, addr) (ppp->ipcp_allowoptions.dnsaddr[index] = ip4_addr_get_u32(addr))
-
-/*
- * If set, we ask the peer for up to 2 DNS server addresses. Received DNS server addresses are
- * registered using the dns_setserver() function.
- *
- * Default is false.
- */
-#define ppp_set_usepeerdns(ppp, boolval) (ppp->settings.usepeerdns = boolval)
-#endif /* LWIP_DNS */
-#endif /* PPP_IPV4_SUPPORT */
-
-#if MPPE_SUPPORT
-/* Disable MPPE (Microsoft Point to Point Encryption). This parameter is exclusive. */
-#define PPP_MPPE_DISABLE           0x00
-/* Require the use of MPPE (Microsoft Point to Point Encryption). */
-#define PPP_MPPE_ENABLE            0x01
-/* Allow MPPE to use stateful mode. Stateless mode is still attempted first. */
-#define PPP_MPPE_ALLOW_STATEFUL    0x02
-/* Refuse the use of MPPE with 40-bit encryption. Conflict with PPP_MPPE_REFUSE_128. */
-#define PPP_MPPE_REFUSE_40         0x04
-/* Refuse the use of MPPE with 128-bit encryption. Conflict with PPP_MPPE_REFUSE_40. */
-#define PPP_MPPE_REFUSE_128        0x08
-/*
- * Set MPPE configuration
- *
- * Default is disabled.
- */
-void ppp_set_mppe(ppp_pcb *pcb, u8_t flags);
-#endif /* MPPE_SUPPORT */
-
-/*
- * Wait for up to intval milliseconds for a valid PPP packet from the peer.
- * At the end of this  time, or when a valid PPP packet is received from the
- * peer, we commence negotiation by sending our first LCP packet.
- *
- * Default is 0.
- */
-#define ppp_set_listen_time(ppp, intval) (ppp->settings.listen_time = intval)
-
-/*
- * If set, we will attempt to initiate a connection but if no reply is received from
- * the peer, we will then just wait passively for a valid LCP packet from the peer.
- *
- * Default is false.
- */
-#define ppp_set_passive(ppp, boolval) (ppp->lcp_wantoptions.passive = boolval)
-
-/*
- * If set, we will not transmit LCP packets to initiate a connection until a valid
- * LCP packet is received from the peer. This is what we usually call the server mode.
- *
- * Default is false.
- */
-#define ppp_set_silent(ppp, boolval) (ppp->lcp_wantoptions.silent = boolval)
-
-/*
- * If set, enable protocol field compression negotiation in both the receive and
- * the transmit direction.
- *
- * Default is true.
- */
-#define ppp_set_neg_pcomp(ppp, boolval) (ppp->lcp_wantoptions.neg_pcompression = \
-                                         ppp->lcp_allowoptions.neg_pcompression = boolval)
-
-/*
- * If set, enable Address/Control compression in both the receive and the transmit
- * direction.
- *
- * Default is true.
- */
-#define ppp_set_neg_accomp(ppp, boolval) (ppp->lcp_wantoptions.neg_accompression = \
-                                          ppp->lcp_allowoptions.neg_accompression = boolval)
-
-/*
- * If set, enable asyncmap negotiation. Otherwise forcing all control characters to
- * be escaped for both the transmit and the receive direction.
- *
- * Default is true.
- */
-#define ppp_set_neg_asyncmap(ppp, boolval) (ppp->lcp_wantoptions.neg_asyncmap = \
-                                            ppp->lcp_allowoptions.neg_asyncmap = boolval)
-
-/*
- * This option sets the Async-Control-Character-Map (ACCM) for this end of the link.
- * The ACCM is a set of 32 bits, one for each of the ASCII control characters with
- * values from 0 to 31, where a 1 bit  indicates that the corresponding control
- * character should not be used in PPP packets sent to this system. The map is
- * an unsigned 32 bits integer where the least significant bit (00000001) represents
- * character 0 and the most significant bit (80000000) represents character 31.
- * We will then ask the peer to send these characters as a 2-byte escape sequence.
- *
- * Default is 0.
- */
-#define ppp_set_asyncmap(ppp, intval) (ppp->lcp_wantoptions.asyncmap = intval)
-
-/*
- * Set a PPP interface as the default network interface
- * (used to output all packets for which no specific route is found).
- */
-#define ppp_set_default(ppp)         netif_set_default(ppp->netif)
-
-#if PPP_NOTIFY_PHASE
-/*
- * Set a PPP notify phase callback.
- *
- * This can be used for example to set a LED pattern depending on the
- * current phase of the PPP session.
- */
-typedef void (*ppp_notify_phase_cb_fn)(ppp_pcb *pcb, u8_t phase, void *ctx);
-void ppp_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb);
-#endif /* PPP_NOTIFY_PHASE */
-
-/*
- * Initiate a PPP connection.
- *
- * This can only be called if PPP is in the dead phase.
- *
- * Holdoff is the time to wait (in seconds) before initiating
- * the connection.
- *
- * If this port connects to a modem, the modem connection must be
- * established before calling this.
- */
-err_t ppp_connect(ppp_pcb *pcb, u16_t holdoff);
-
-#if PPP_SERVER
-/*
- * Listen for an incoming PPP connection.
- *
- * This can only be called if PPP is in the dead phase.
- *
- * If this port connects to a modem, the modem connection must be
- * established before calling this.
- */
-err_t ppp_listen(ppp_pcb *pcb);
-#endif /* PPP_SERVER */
-
-/*
- * Initiate the end of a PPP connection.
- * Any outstanding packets in the queues are dropped.
- *
- * Setting nocarrier to 1 close the PPP connection without initiating the
- * shutdown procedure. Always using nocarrier = 0 is still recommended,
- * this is going to take a little longer time if your link is down, but
- * is a safer choice for the PPP state machine.
- *
- * Return 0 on success, an error code on failure.
- */
-err_t ppp_close(ppp_pcb *pcb, u8_t nocarrier);
-
-/*
- * Release the control block.
- *
- * This can only be called if PPP is in the dead phase.
- *
- * You must use ppp_close() before if you wish to terminate
- * an established PPP session.
- *
- * Return 0 on success, an error code on failure.
- */
-err_t ppp_free(ppp_pcb *pcb);
-
-/*
- * PPP IOCTL commands.
- *
- * Get the up status - 0 for down, non-zero for up.  The argument must
- * point to an int.
- */
-#define PPPCTLG_UPSTATUS 0
-
-/*
- * Get the PPP error code.  The argument must point to an int.
- * Returns a PPPERR_* value.
- */
-#define PPPCTLG_ERRCODE  1
-
-/*
- * Get the fd associated with a PPP over serial
- */
-#define PPPCTLG_FD       2
-
-/*
- * Get and set parameters for the given connection.
- * Return 0 on success, an error code on failure.
- */
-err_t ppp_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg);
-
-/* Get the PPP netif interface */
-#define ppp_netif(ppp)               (ppp->netif)
-
-/* Set an lwIP-style status-callback for the selected PPP device */
-#define ppp_set_netif_statuscallback(ppp, status_cb)       \
-        netif_set_status_callback(ppp->netif, status_cb);
-
-/* Set an lwIP-style link-callback for the selected PPP device */
-#define ppp_set_netif_linkcallback(ppp, link_cb)           \
-        netif_set_link_callback(ppp->netif, link_cb);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PPP_H */
-
-#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/ppp_impl.h b/tools/sdk/include/lwip/netif/ppp/ppp_impl.h
deleted file mode 100644
index 1d4c7742f35..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/ppp_impl.h
+++ /dev/null
@@ -1,629 +0,0 @@
-/*****************************************************************************
-* ppp.h - Network Point to Point Protocol header file.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1997 Global Election Systems Inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 03-01-01 Marc Boucher <marc@mbsi.ca>
-*   Ported to lwIP.
-* 97-11-05 Guy Lancaster <glanca@gesn.com>, Global Election Systems Inc.
-*   Original derived from BSD codes.
-*****************************************************************************/
-#ifndef LWIP_HDR_PPP_IMPL_H
-#define LWIP_HDR_PPP_IMPL_H
-
-#include "netif/ppp/ppp_opts.h"
-
-#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifdef PPP_INCLUDE_SETTINGS_HEADER
-#include "ppp_settings.h"
-#endif
-
-#include <stdio.h> /* formats */
-#include <stdarg.h>
-#include <string.h>
-#include <stdlib.h> /* strtol() */
-
-#include "lwip/netif.h"
-#include "lwip/def.h"
-#include "lwip/timeouts.h"
-
-#include "ppp.h"
-#include "pppdebug.h"
-
-/*
- * Memory used for control packets.
- *
- * PPP_CTRL_PBUF_MAX_SIZE is the amount of memory we allocate when we
- * cannot figure out how much we are going to use before filling the buffer.
- */
-#if PPP_USE_PBUF_RAM
-#define PPP_CTRL_PBUF_TYPE       PBUF_RAM
-#define PPP_CTRL_PBUF_MAX_SIZE   512
-#else /* PPP_USE_PBUF_RAM */
-#define PPP_CTRL_PBUF_TYPE       PBUF_POOL
-#define PPP_CTRL_PBUF_MAX_SIZE   PBUF_POOL_BUFSIZE
-#endif /* PPP_USE_PBUF_RAM */
-
-/*
- * The basic PPP frame.
- */
-#define PPP_ADDRESS(p)	(((u_char *)(p))[0])
-#define PPP_CONTROL(p)	(((u_char *)(p))[1])
-#define PPP_PROTOCOL(p)	((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3])
-
-/*
- * Significant octet values.
- */
-#define	PPP_ALLSTATIONS	0xff	/* All-Stations broadcast address */
-#define	PPP_UI		0x03	/* Unnumbered Information */
-#define	PPP_FLAG	0x7e	/* Flag Sequence */
-#define	PPP_ESCAPE	0x7d	/* Asynchronous Control Escape */
-#define	PPP_TRANS	0x20	/* Asynchronous transparency modifier */
-
-/*
- * Protocol field values.
- */
-#define PPP_IP		0x21	/* Internet Protocol */
-#if 0 /* UNUSED */
-#define PPP_AT		0x29	/* AppleTalk Protocol */
-#define PPP_IPX		0x2b	/* IPX protocol */
-#endif /* UNUSED */
-#if VJ_SUPPORT
-#define	PPP_VJC_COMP	0x2d	/* VJ compressed TCP */
-#define	PPP_VJC_UNCOMP	0x2f	/* VJ uncompressed TCP */
-#endif /* VJ_SUPPORT */
-#if PPP_IPV6_SUPPORT
-#define PPP_IPV6	0x57	/* Internet Protocol Version 6 */
-#endif /* PPP_IPV6_SUPPORT */
-#if CCP_SUPPORT
-#define PPP_COMP	0xfd	/* compressed packet */
-#endif /* CCP_SUPPORT */
-#define PPP_IPCP	0x8021	/* IP Control Protocol */
-#if 0 /* UNUSED */
-#define PPP_ATCP	0x8029	/* AppleTalk Control Protocol */
-#define PPP_IPXCP	0x802b	/* IPX Control Protocol */
-#endif /* UNUSED */
-#if PPP_IPV6_SUPPORT
-#define PPP_IPV6CP	0x8057	/* IPv6 Control Protocol */
-#endif /* PPP_IPV6_SUPPORT */
-#if CCP_SUPPORT
-#define PPP_CCP		0x80fd	/* Compression Control Protocol */
-#endif /* CCP_SUPPORT */
-#if ECP_SUPPORT
-#define PPP_ECP		0x8053	/* Encryption Control Protocol */
-#endif /* ECP_SUPPORT */
-#define PPP_LCP		0xc021	/* Link Control Protocol */
-#if PAP_SUPPORT
-#define PPP_PAP		0xc023	/* Password Authentication Protocol */
-#endif /* PAP_SUPPORT */
-#if LQR_SUPPORT
-#define PPP_LQR		0xc025	/* Link Quality Report protocol */
-#endif /* LQR_SUPPORT */
-#if CHAP_SUPPORT
-#define PPP_CHAP	0xc223	/* Cryptographic Handshake Auth. Protocol */
-#endif /* CHAP_SUPPORT */
-#if CBCP_SUPPORT
-#define PPP_CBCP	0xc029	/* Callback Control Protocol */
-#endif /* CBCP_SUPPORT */
-#if EAP_SUPPORT
-#define PPP_EAP		0xc227	/* Extensible Authentication Protocol */
-#endif /* EAP_SUPPORT */
-
-/*
- * The following struct gives the addresses of procedures to call
- * for a particular lower link level protocol.
- */
-struct link_callbacks {
-  /* Start a connection (e.g. Initiate discovery phase) */
-  void (*connect) (ppp_pcb *pcb, void *ctx);
-#if PPP_SERVER
-  /* Listen for an incoming connection (Passive mode) */
-  void (*listen) (ppp_pcb *pcb, void *ctx);
-#endif /* PPP_SERVER */
-  /* End a connection (i.e. initiate disconnect phase) */
-  void (*disconnect) (ppp_pcb *pcb, void *ctx);
-  /* Free lower protocol control block */
-  err_t (*free) (ppp_pcb *pcb, void *ctx);
-  /* Write a pbuf to a ppp link, only used from PPP functions to send PPP packets. */
-  err_t (*write)(ppp_pcb *pcb, void *ctx, struct pbuf *p);
-  /* Send a packet from lwIP core (IPv4 or IPv6) */
-  err_t (*netif_output)(ppp_pcb *pcb, void *ctx, struct pbuf *p, u_short protocol);
-  /* configure the transmit-side characteristics of the PPP interface */
-  void (*send_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp);
-  /* confire the receive-side characteristics of the PPP interface */
-  void (*recv_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp);
-};
-
-/*
- * What to do with network protocol (NP) packets.
- */
-enum NPmode {
-    NPMODE_PASS,		/* pass the packet through */
-    NPMODE_DROP,		/* silently drop the packet */
-    NPMODE_ERROR,		/* return an error */
-    NPMODE_QUEUE		/* save it up for later. */
-};
-
-/*
- * Statistics.
- */
-#if PPP_STATS_SUPPORT
-struct pppstat	{
-    unsigned int ppp_ibytes;	/* bytes received */
-    unsigned int ppp_ipackets;	/* packets received */
-    unsigned int ppp_ierrors;	/* receive errors */
-    unsigned int ppp_obytes;	/* bytes sent */
-    unsigned int ppp_opackets;	/* packets sent */
-    unsigned int ppp_oerrors;	/* transmit errors */
-};
-
-#if VJ_SUPPORT
-struct vjstat {
-    unsigned int vjs_packets;	/* outbound packets */
-    unsigned int vjs_compressed; /* outbound compressed packets */
-    unsigned int vjs_searches;	/* searches for connection state */
-    unsigned int vjs_misses;	/* times couldn't find conn. state */
-    unsigned int vjs_uncompressedin; /* inbound uncompressed packets */
-    unsigned int vjs_compressedin; /* inbound compressed packets */
-    unsigned int vjs_errorin;	/* inbound unknown type packets */
-    unsigned int vjs_tossed;	/* inbound packets tossed because of error */
-};
-#endif /* VJ_SUPPORT */
-
-struct ppp_stats {
-    struct pppstat p;		/* basic PPP statistics */
-#if VJ_SUPPORT
-    struct vjstat vj;		/* VJ header compression statistics */
-#endif /* VJ_SUPPORT */
-};
-
-#if CCP_SUPPORT
-struct compstat {
-    unsigned int unc_bytes;	/* total uncompressed bytes */
-    unsigned int unc_packets;	/* total uncompressed packets */
-    unsigned int comp_bytes;	/* compressed bytes */
-    unsigned int comp_packets;	/* compressed packets */
-    unsigned int inc_bytes;	/* incompressible bytes */
-    unsigned int inc_packets;	/* incompressible packets */
-    unsigned int ratio;		/* recent compression ratio << 8 */
-};
-
-struct ppp_comp_stats {
-    struct compstat c;		/* packet compression statistics */
-    struct compstat d;		/* packet decompression statistics */
-};
-#endif /* CCP_SUPPORT */
-
-#endif /* PPP_STATS_SUPPORT */
-
-#if PPP_IDLETIMELIMIT
-/*
- * The following structure records the time in seconds since
- * the last NP packet was sent or received.
- */
-struct ppp_idle {
-    time_t xmit_idle;		/* time since last NP packet sent */
-    time_t recv_idle;		/* time since last NP packet received */
-};
-#endif /* PPP_IDLETIMELIMIT */
-
-/* values for epdisc.class */
-#define EPD_NULL	0	/* null discriminator, no data */
-#define EPD_LOCAL	1
-#define EPD_IP		2
-#define EPD_MAC		3
-#define EPD_MAGIC	4
-#define EPD_PHONENUM	5
-
-/*
- * Global variables.
- */
-#ifdef HAVE_MULTILINK
-extern u8_t	multilink;	/* enable multilink operation */
-extern u8_t	doing_multilink;
-extern u8_t	multilink_master;
-extern u8_t	bundle_eof;
-extern u8_t	bundle_terminating;
-#endif
-
-#ifdef MAXOCTETS
-extern unsigned int maxoctets;	     /* Maximum octetes per session (in bytes) */
-extern int       maxoctets_dir;      /* Direction :
-				      0 - in+out (default)
-				      1 - in
-				      2 - out
-				      3 - max(in,out) */
-extern int       maxoctets_timeout;  /* Timeout for check of octets limit */
-#define PPP_OCTETS_DIRECTION_SUM        0
-#define PPP_OCTETS_DIRECTION_IN         1
-#define PPP_OCTETS_DIRECTION_OUT        2
-#define PPP_OCTETS_DIRECTION_MAXOVERAL  3
-/* same as previos, but little different on RADIUS side */
-#define PPP_OCTETS_DIRECTION_MAXSESSION 4
-#endif
-
-/* Data input may be used by CCP and ECP, remove this entry
- * from struct protent to save some flash
- */
-#define PPP_DATAINPUT 0
-
-/*
- * The following struct gives the addresses of procedures to call
- * for a particular protocol.
- */
-struct protent {
-    u_short protocol;		/* PPP protocol number */
-    /* Initialization procedure */
-    void (*init) (ppp_pcb *pcb);
-    /* Process a received packet */
-    void (*input) (ppp_pcb *pcb, u_char *pkt, int len);
-    /* Process a received protocol-reject */
-    void (*protrej) (ppp_pcb *pcb);
-    /* Lower layer has come up */
-    void (*lowerup) (ppp_pcb *pcb);
-    /* Lower layer has gone down */
-    void (*lowerdown) (ppp_pcb *pcb);
-    /* Open the protocol */
-    void (*open) (ppp_pcb *pcb);
-    /* Close the protocol */
-    void (*close) (ppp_pcb *pcb, const char *reason);
-#if PRINTPKT_SUPPORT
-    /* Print a packet in readable form */
-    int  (*printpkt) (const u_char *pkt, int len,
-			  void (*printer) (void *, const char *, ...),
-			  void *arg);
-#endif /* PRINTPKT_SUPPORT */
-#if PPP_DATAINPUT
-    /* Process a received data packet */
-    void (*datainput) (ppp_pcb *pcb, u_char *pkt, int len);
-#endif /* PPP_DATAINPUT */
-#if PRINTPKT_SUPPORT
-    const char *name;		/* Text name of protocol */
-    const char *data_name;	/* Text name of corresponding data protocol */
-#endif /* PRINTPKT_SUPPORT */
-#if PPP_OPTIONS
-    option_t *options;		/* List of command-line options */
-    /* Check requested options, assign defaults */
-    void (*check_options) (void);
-#endif /* PPP_OPTIONS */
-#if DEMAND_SUPPORT
-    /* Configure interface for demand-dial */
-    int  (*demand_conf) (int unit);
-    /* Say whether to bring up link for this pkt */
-    int  (*active_pkt) (u_char *pkt, int len);
-#endif /* DEMAND_SUPPORT */
-};
-
-/* Table of pointers to supported protocols */
-extern const struct protent* const protocols[];
-
-
-/* Values for auth_pending, auth_done */
-#if PAP_SUPPORT
-#define PAP_WITHPEER	0x1
-#define PAP_PEER	0x2
-#endif /* PAP_SUPPORT */
-#if CHAP_SUPPORT
-#define CHAP_WITHPEER	0x4
-#define CHAP_PEER	0x8
-#endif /* CHAP_SUPPORT */
-#if EAP_SUPPORT
-#define EAP_WITHPEER	0x10
-#define EAP_PEER	0x20
-#endif /* EAP_SUPPORT */
-
-/* Values for auth_done only */
-#if CHAP_SUPPORT
-#define CHAP_MD5_WITHPEER	0x40
-#define CHAP_MD5_PEER		0x80
-#if MSCHAP_SUPPORT
-#define CHAP_MS_SHIFT		8	/* LSB position for MS auths */
-#define CHAP_MS_WITHPEER	0x100
-#define CHAP_MS_PEER		0x200
-#define CHAP_MS2_WITHPEER	0x400
-#define CHAP_MS2_PEER		0x800
-#endif /* MSCHAP_SUPPORT */
-#endif /* CHAP_SUPPORT */
-
-/* Supported CHAP protocols */
-#if CHAP_SUPPORT
-
-#if MSCHAP_SUPPORT
-#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MICROSOFT_V2 | MDTYPE_MICROSOFT | MDTYPE_MD5)
-#else /* MSCHAP_SUPPORT */
-#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MD5)
-#endif /* MSCHAP_SUPPORT */
-
-#else /* CHAP_SUPPORT */
-#define CHAP_MDTYPE_SUPPORTED (MDTYPE_NONE)
-#endif /* CHAP_SUPPORT */
-
-#if PPP_STATS_SUPPORT
-/*
- * PPP statistics structure
- */
-struct pppd_stats {
-    unsigned int	bytes_in;
-    unsigned int	bytes_out;
-    unsigned int	pkts_in;
-    unsigned int	pkts_out;
-};
-#endif /* PPP_STATS_SUPPORT */
-
-
-/*
- * PPP private functions
- */
-
- 
-/*
- * Functions called from lwIP core.
- */
-
-/* initialize the PPP subsystem */
-int ppp_init(void);
-
-/*
- * Functions called from PPP link protocols.
- */
-
-/* Create a new PPP control block */
-ppp_pcb *ppp_new(struct netif *pppif, const struct link_callbacks *callbacks, void *link_ctx_cb,
-                 ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
-
-/* Initiate LCP open request */
-void ppp_start(ppp_pcb *pcb);
-
-/* Called when link failed to setup */
-void ppp_link_failed(ppp_pcb *pcb);
-
-/* Called when link is normally down (i.e. it was asked to end) */
-void ppp_link_end(ppp_pcb *pcb);
-
-/* function called to process input packet */
-void ppp_input(ppp_pcb *pcb, struct pbuf *pb);
-
-/* helper function, merge a pbuf chain into one pbuf */
-struct pbuf *ppp_singlebuf(struct pbuf *p);
-
-
-/*
- * Functions called by PPP protocols.
- */
-
-/* function called by all PPP subsystems to send packets */
-err_t ppp_write(ppp_pcb *pcb, struct pbuf *p);
-
-/* functions called by auth.c link_terminated() */
-void ppp_link_terminated(ppp_pcb *pcb);
-
-void new_phase(ppp_pcb *pcb, int p);
-
-int ppp_send_config(ppp_pcb *pcb, int mtu, u32_t accm, int pcomp, int accomp);
-int ppp_recv_config(ppp_pcb *pcb, int mru, u32_t accm, int pcomp, int accomp);
-
-#if PPP_IPV4_SUPPORT
-int sifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr, u32_t netmask);
-int cifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr);
-#if 0 /* UNUSED - PROXY ARP */
-int sifproxyarp(ppp_pcb *pcb, u32_t his_adr);
-int cifproxyarp(ppp_pcb *pcb, u32_t his_adr);
-#endif /* UNUSED - PROXY ARP */
-#if LWIP_DNS
-int sdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2);
-int cdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2);
-#endif /* LWIP_DNS */
-#if VJ_SUPPORT
-int sifvjcomp(ppp_pcb *pcb, int vjcomp, int cidcomp, int maxcid);
-#endif /* VJ_SUPPORT */
-int sifup(ppp_pcb *pcb);
-int sifdown (ppp_pcb *pcb);
-u32_t get_mask(u32_t addr);
-#endif /* PPP_IPV4_SUPPORT */
-
-#if PPP_IPV6_SUPPORT
-int sif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64);
-int cif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64);
-int sif6up(ppp_pcb *pcb);
-int sif6down (ppp_pcb *pcb);
-#endif /* PPP_IPV6_SUPPORT */
-
-#if DEMAND_SUPPORT
-int sifnpmode(ppp_pcb *pcb, int proto, enum NPmode mode);
-#endif /* DEMAND_SUPPORt */
-
-void netif_set_mtu(ppp_pcb *pcb, int mtu);
-int netif_get_mtu(ppp_pcb *pcb);
-
-#if CCP_SUPPORT
-#if 0 /* unused */
-int ccp_test(ppp_pcb *pcb, u_char *opt_ptr, int opt_len, int for_transmit);
-#endif /* unused */
-void ccp_set(ppp_pcb *pcb, u8_t isopen, u8_t isup, u8_t receive_method, u8_t transmit_method);
-void ccp_reset_comp(ppp_pcb *pcb);
-void ccp_reset_decomp(ppp_pcb *pcb);
-#if 0 /* unused */
-int ccp_fatal_error(ppp_pcb *pcb);
-#endif /* unused */
-#endif /* CCP_SUPPORT */
-
-#if PPP_IDLETIMELIMIT
-int get_idle_time(ppp_pcb *pcb, struct ppp_idle *ip);
-#endif /* PPP_IDLETIMELIMIT */
-
-#if DEMAND_SUPPORT
-int get_loop_output(void);
-#endif /* DEMAND_SUPPORT */
-
-/* Optional protocol names list, to make our messages a little more informative. */
-#if PPP_PROTOCOLNAME
-const char * protocol_name(int proto);
-#endif /* PPP_PROTOCOLNAME  */
-
-/* Optional stats support, to get some statistics on the PPP interface */
-#if PPP_STATS_SUPPORT
-void print_link_stats(void); /* Print stats, if available */
-void reset_link_stats(int u); /* Reset (init) stats when link goes up */
-void update_link_stats(int u); /* Get stats at link termination */
-#endif /* PPP_STATS_SUPPORT */
-
-
-
-/*
- * Inline versions of get/put char/short/long.
- * Pointer is advanced; we assume that both arguments
- * are lvalues and will already be in registers.
- * cp MUST be u_char *.
- */
-#define GETCHAR(c, cp) { \
-	(c) = *(cp)++; \
-}
-#define PUTCHAR(c, cp) { \
-	*(cp)++ = (u_char) (c); \
-}
-#define GETSHORT(s, cp) { \
-	(s) = *(cp)++ << 8; \
-	(s) |= *(cp)++; \
-}
-#define PUTSHORT(s, cp) { \
-	*(cp)++ = (u_char) ((s) >> 8); \
-	*(cp)++ = (u_char) (s); \
-}
-#define GETLONG(l, cp) { \
-	(l) = *(cp)++ << 8; \
-	(l) |= *(cp)++; (l) <<= 8; \
-	(l) |= *(cp)++; (l) <<= 8; \
-	(l) |= *(cp)++; \
-}
-#define PUTLONG(l, cp) { \
-	*(cp)++ = (u_char) ((l) >> 24); \
-	*(cp)++ = (u_char) ((l) >> 16); \
-	*(cp)++ = (u_char) ((l) >> 8); \
-	*(cp)++ = (u_char) (l); \
-}
-
-#define INCPTR(n, cp)	((cp) += (n))
-#define DECPTR(n, cp)	((cp) -= (n))
-
-/*
- * System dependent definitions for user-level 4.3BSD UNIX implementation.
- */
-#define TIMEOUT(f, a, t)        do { sys_untimeout((f), (a)); sys_timeout((t)*1000, (f), (a)); } while(0)
-#define TIMEOUTMS(f, a, t)      do { sys_untimeout((f), (a)); sys_timeout((t), (f), (a)); } while(0)
-#define UNTIMEOUT(f, a)         sys_untimeout((f), (a))
-
-#define BZERO(s, n)		memset(s, 0, n)
-#define	BCMP(s1, s2, l)		memcmp(s1, s2, l)
-
-#define PRINTMSG(m, l)		{ ppp_info("Remote message: %0.*v", l, m); }
-
-/*
- * MAKEHEADER - Add Header fields to a packet.
- */
-#define MAKEHEADER(p, t) { \
-    PUTCHAR(PPP_ALLSTATIONS, p); \
-    PUTCHAR(PPP_UI, p); \
-    PUTSHORT(t, p); }
-
-/* Procedures exported from auth.c */
-void link_required(ppp_pcb *pcb);     /* we are starting to use the link */
-void link_terminated(ppp_pcb *pcb);   /* we are finished with the link */
-void link_down(ppp_pcb *pcb);	      /* the LCP layer has left the Opened state */
-void upper_layers_down(ppp_pcb *pcb); /* take all NCPs down */
-void link_established(ppp_pcb *pcb);  /* the link is up; authenticate now */
-void start_networks(ppp_pcb *pcb);    /* start all the network control protos */
-void continue_networks(ppp_pcb *pcb); /* start network [ip, etc] control protos */
-#if PPP_AUTH_SUPPORT
-#if PPP_SERVER
-int auth_check_passwd(ppp_pcb *pcb, char *auser, int userlen, char *apasswd, int passwdlen, const char **msg, int *msglen);
-                                /* check the user name and passwd against configuration */
-void auth_peer_fail(ppp_pcb *pcb, int protocol);
-				/* peer failed to authenticate itself */
-void auth_peer_success(ppp_pcb *pcb, int protocol, int prot_flavor, const char *name, int namelen);
-				/* peer successfully authenticated itself */
-#endif /* PPP_SERVER */
-void auth_withpeer_fail(ppp_pcb *pcb, int protocol);
-				/* we failed to authenticate ourselves */
-void auth_withpeer_success(ppp_pcb *pcb, int protocol, int prot_flavor);
-				/* we successfully authenticated ourselves */
-#endif /* PPP_AUTH_SUPPORT */
-void np_up(ppp_pcb *pcb, int proto);    /* a network protocol has come up */
-void np_down(ppp_pcb *pcb, int proto);  /* a network protocol has gone down */
-void np_finished(ppp_pcb *pcb, int proto); /* a network protocol no longer needs link */
-#if PPP_AUTH_SUPPORT
-int get_secret(ppp_pcb *pcb, const char *client, const char *server, char *secret, int *secret_len, int am_server);
-				/* get "secret" for chap */
-#endif /* PPP_AUTH_SUPPORT */
-
-/* Procedures exported from ipcp.c */
-/* int parse_dotted_ip (char *, u32_t *); */
-
-/* Procedures exported from demand.c */
-#if DEMAND_SUPPORT
-void demand_conf (void);	/* config interface(s) for demand-dial */
-void demand_block (void);	/* set all NPs to queue up packets */
-void demand_unblock (void); /* set all NPs to pass packets */
-void demand_discard (void); /* set all NPs to discard packets */
-void demand_rexmit (int, u32_t); /* retransmit saved frames for an NP*/
-int  loop_chars (unsigned char *, int); /* process chars from loopback */
-int  loop_frame (unsigned char *, int); /* should we bring link up? */
-#endif /* DEMAND_SUPPORT */
-
-/* Procedures exported from multilink.c */
-#ifdef HAVE_MULTILINK
-void mp_check_options (void); /* Check multilink-related options */
-int  mp_join_bundle (void);  /* join our link to an appropriate bundle */
-void mp_exit_bundle (void);  /* have disconnected our link from bundle */
-void mp_bundle_terminated (void);
-char *epdisc_to_str (struct epdisc *); /* string from endpoint discrim. */
-int  str_to_epdisc (struct epdisc *, char *); /* endpt disc. from str */
-#else
-#define mp_bundle_terminated()	/* nothing */
-#define mp_exit_bundle()	/* nothing */
-#define doing_multilink		0
-#define multilink_master	0
-#endif
-
-/* Procedures exported from utils.c. */
-void ppp_print_string(const u_char *p, int len, void (*printer) (void *, const char *, ...), void *arg);   /* Format a string for output */
-int ppp_slprintf(char *buf, int buflen, const char *fmt, ...);            /* sprintf++ */
-int ppp_vslprintf(char *buf, int buflen, const char *fmt, va_list args);  /* vsprintf++ */
-size_t ppp_strlcpy(char *dest, const char *src, size_t len);        /* safe strcpy */
-size_t ppp_strlcat(char *dest, const char *src, size_t len);        /* safe strncpy */
-void ppp_dbglog(const char *fmt, ...);    /* log a debug message */
-void ppp_info(const char *fmt, ...);      /* log an informational message */
-void ppp_notice(const char *fmt, ...);    /* log a notice-level message */
-void ppp_warn(const char *fmt, ...);      /* log a warning message */
-void ppp_error(const char *fmt, ...);     /* log an error message */
-void ppp_fatal(const char *fmt, ...);     /* log an error message and die(1) */
-#if PRINTPKT_SUPPORT
-void ppp_dump_packet(ppp_pcb *pcb, const char *tag, unsigned char *p, int len);
-                                /* dump packet to debug log if interesting */
-#endif /* PRINTPKT_SUPPORT */
-
-
-#endif /* PPP_SUPPORT */
-#endif /* LWIP_HDR_PPP_IMPL_H */
diff --git a/tools/sdk/include/lwip/netif/ppp/ppp_opts.h b/tools/sdk/include/lwip/netif/ppp/ppp_opts.h
deleted file mode 100644
index fa79c090f25..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/ppp_opts.h
+++ /dev/null
@@ -1,593 +0,0 @@
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#ifndef LWIP_PPP_OPTS_H
-#define LWIP_PPP_OPTS_H
-
-#include "lwip/opt.h"
-
-/**
- * PPP_SUPPORT==1: Enable PPP.
- */
-#ifndef PPP_SUPPORT
-#define PPP_SUPPORT                     0
-#endif
-
-/**
- * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
- */
-#ifndef PPPOE_SUPPORT
-#define PPPOE_SUPPORT                   0
-#endif
-
-/**
- * PPPOL2TP_SUPPORT==1: Enable PPP Over L2TP
- */
-#ifndef PPPOL2TP_SUPPORT
-#define PPPOL2TP_SUPPORT                0
-#endif
-
-/**
- * PPPOL2TP_AUTH_SUPPORT==1: Enable PPP Over L2TP Auth (enable MD5 support)
- */
-#ifndef PPPOL2TP_AUTH_SUPPORT
-#define PPPOL2TP_AUTH_SUPPORT           PPPOL2TP_SUPPORT
-#endif
-
-/**
- * PPPOS_SUPPORT==1: Enable PPP Over Serial
- */
-#ifndef PPPOS_SUPPORT
-#define PPPOS_SUPPORT                   PPP_SUPPORT
-#endif
-
-/**
- * LWIP_PPP_API==1: Enable PPP API (in pppapi.c)
- */
-#ifndef LWIP_PPP_API
-#define LWIP_PPP_API                    (PPP_SUPPORT && (NO_SYS == 0))
-#endif
-
-/**
- * MEMP_NUM_PPP_PCB: the number of simultaneously active PPP
- * connections (requires the PPP_SUPPORT option)
- */
-#ifndef MEMP_NUM_PPP_PCB
-#define MEMP_NUM_PPP_PCB       1
-#endif
-
-#if PPP_SUPPORT
-
-/**
- * MEMP_NUM_PPPOS_INTERFACES: the number of concurrently active PPPoS
- * interfaces (only used with PPPOS_SUPPORT==1)
- */
-#ifndef MEMP_NUM_PPPOS_INTERFACES
-#define MEMP_NUM_PPPOS_INTERFACES       MEMP_NUM_PPP_PCB
-#endif
-
-/**
- * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE
- * interfaces (only used with PPPOE_SUPPORT==1)
- */
-#ifndef MEMP_NUM_PPPOE_INTERFACES
-#define MEMP_NUM_PPPOE_INTERFACES       1
-#endif
-
-/**
- * MEMP_NUM_PPPOL2TP_INTERFACES: the number of concurrently active PPPoL2TP
- * interfaces (only used with PPPOL2TP_SUPPORT==1)
- */
-#ifndef MEMP_NUM_PPPOL2TP_INTERFACES
-#define MEMP_NUM_PPPOL2TP_INTERFACES       1
-#endif
-
-/**
- * MEMP_NUM_PPP_API_MSG: Number of concurrent PPP API messages (in pppapi.c)
- */
-#ifndef MEMP_NUM_PPP_API_MSG
-#define MEMP_NUM_PPP_API_MSG 5
-#endif
-
-/**
- * PPP_DEBUG: Enable debugging for PPP.
- */
-#ifndef PPP_DEBUG
-#define PPP_DEBUG                       LWIP_DBG_OFF
-#endif
-
-/**
- * PPP_INPROC_IRQ_SAFE==1 call pppos_input() using tcpip_callback().
- *
- * Please read the "PPPoS input path" chapter in the PPP documentation about this option.
- */
-#ifndef PPP_INPROC_IRQ_SAFE
-#define PPP_INPROC_IRQ_SAFE             0
-#endif
-
-/**
- * PRINTPKT_SUPPORT==1: Enable PPP print packet support
- *
- * Mandatory for debugging, it displays exchanged packet content in debug trace.
- */
-#ifndef PRINTPKT_SUPPORT
-#define PRINTPKT_SUPPORT                0
-#endif
-
-/**
- * PPP_IPV4_SUPPORT==1: Enable PPP IPv4 support
- */
-#ifndef PPP_IPV4_SUPPORT
-#define PPP_IPV4_SUPPORT                (LWIP_IPV4)
-#endif
-
-/**
- * PPP_IPV6_SUPPORT==1: Enable PPP IPv6 support
- */
-#ifndef PPP_IPV6_SUPPORT
-#define PPP_IPV6_SUPPORT                (LWIP_IPV6)
-#endif
-
-/**
- * PPP_NOTIFY_PHASE==1: Support PPP notify phase support
- *
- * PPP notify phase support allows you to set a callback which is
- * called on change of the internal PPP state machine.
- *
- * This can be used for example to set a LED pattern depending on the
- * current phase of the PPP session.
- */
-#ifndef PPP_NOTIFY_PHASE
-#define PPP_NOTIFY_PHASE                0
-#endif
-
-/**
- * pbuf_type PPP is using for LCP, PAP, CHAP, EAP, CCP, IPCP and IP6CP packets.
- *
- * Memory allocated must be single buffered for PPP to works, it requires pbuf
- * that are not going to be chained when allocated. This requires setting
- * PBUF_POOL_BUFSIZE to at least 512 bytes, which is quite huge for small systems.
- *
- * Setting PPP_USE_PBUF_RAM to 1 makes PPP use memory from heap where continuous
- * buffers are required, allowing you to use a smaller PBUF_POOL_BUFSIZE.
- */
-#ifndef PPP_USE_PBUF_RAM
-#define PPP_USE_PBUF_RAM                0
-#endif
-
-/**
- * PPP_FCS_TABLE: Keep a 256*2 byte table to speed up FCS calculation for PPPoS
- */
-#ifndef PPP_FCS_TABLE
-#define PPP_FCS_TABLE                   1
-#endif
-
-/**
- * PAP_SUPPORT==1: Support PAP.
- */
-#ifndef PAP_SUPPORT
-#define PAP_SUPPORT                     0
-#endif
-
-/**
- * CHAP_SUPPORT==1: Support CHAP.
- */
-#ifndef CHAP_SUPPORT
-#define CHAP_SUPPORT                    0
-#endif
-
-/**
- * MSCHAP_SUPPORT==1: Support MSCHAP.
- */
-#ifndef MSCHAP_SUPPORT
-#define MSCHAP_SUPPORT                  0
-#endif
-#if MSCHAP_SUPPORT
-/* MSCHAP requires CHAP support */
-#undef CHAP_SUPPORT
-#define CHAP_SUPPORT                    1
-#endif /* MSCHAP_SUPPORT */
-
-/**
- * EAP_SUPPORT==1: Support EAP.
- */
-#ifndef EAP_SUPPORT
-#define EAP_SUPPORT                     0
-#endif
-
-/**
- * CCP_SUPPORT==1: Support CCP.
- */
-#ifndef CCP_SUPPORT
-#define CCP_SUPPORT                     0
-#endif
-
-/**
- * MPPE_SUPPORT==1: Support MPPE.
- */
-#ifndef MPPE_SUPPORT
-#define MPPE_SUPPORT                    0
-#endif
-#if MPPE_SUPPORT
-/* MPPE requires CCP support */
-#undef CCP_SUPPORT
-#define CCP_SUPPORT                     1
-/* MPPE requires MSCHAP support */
-#undef MSCHAP_SUPPORT
-#define MSCHAP_SUPPORT                  1
-/* MSCHAP requires CHAP support */
-#undef CHAP_SUPPORT
-#define CHAP_SUPPORT                    1
-#endif /* MPPE_SUPPORT */
-
-/**
- * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
- */
-#ifndef CBCP_SUPPORT
-#define CBCP_SUPPORT                    0
-#endif
-
-/**
- * ECP_SUPPORT==1: Support ECP. CURRENTLY NOT SUPPORTED! DO NOT SET!
- */
-#ifndef ECP_SUPPORT
-#define ECP_SUPPORT                     0
-#endif
-
-/**
- * DEMAND_SUPPORT==1: Support dial on demand. CURRENTLY NOT SUPPORTED! DO NOT SET!
- */
-#ifndef DEMAND_SUPPORT
-#define DEMAND_SUPPORT                  0
-#endif
-
-/**
- * LQR_SUPPORT==1: Support Link Quality Report. Do nothing except exchanging some LCP packets.
- */
-#ifndef LQR_SUPPORT
-#define LQR_SUPPORT                     0
-#endif
-
-/**
- * PPP_SERVER==1: Enable PPP server support (waiting for incoming PPP session).
- *
- * Currently only supported for PPPoS.
- */
-#ifndef PPP_SERVER
-#define PPP_SERVER                      0
-#endif
-
-#if PPP_SERVER
-/*
- * PPP_OUR_NAME: Our name for authentication purposes
- */
-#ifndef PPP_OUR_NAME
-#define PPP_OUR_NAME                    "lwIP"
-#endif
-#endif /* PPP_SERVER */
-
-/**
- * VJ_SUPPORT==1: Support VJ header compression.
- */
-#ifndef VJ_SUPPORT
-#define VJ_SUPPORT                      1
-#endif
-/* VJ compression is only supported for TCP over IPv4 over PPPoS. */
-#if !PPPOS_SUPPORT || !PPP_IPV4_SUPPORT || !LWIP_TCP
-#undef VJ_SUPPORT
-#define VJ_SUPPORT                      0
-#endif /* !PPPOS_SUPPORT */
-
-/**
- * PPP_MD5_RANDM==1: Use MD5 for better randomness.
- * Enabled by default if CHAP, EAP, or L2TP AUTH support is enabled.
- */
-#ifndef PPP_MD5_RANDM
-#define PPP_MD5_RANDM                   (CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT)
-#endif
-
-/**
- * PolarSSL embedded library
- *
- *
- * lwIP contains some files fetched from the latest BSD release of
- * the PolarSSL project (PolarSSL 0.10.1-bsd) for ciphers and encryption
- * methods we need for lwIP PPP support.
- *
- * The PolarSSL files were cleaned to contain only the necessary struct
- * fields and functions needed for lwIP.
- *
- * The PolarSSL API was not changed at all, so if you are already using
- * PolarSSL you can choose to skip the compilation of the included PolarSSL
- * library into lwIP.
- *
- * If you are not using the embedded copy you must include external
- * libraries into your arch/cc.h port file.
- *
- * Beware of the stack requirements which can be a lot larger if you are not
- * using our cleaned PolarSSL library.
- */
-
-/**
- * LWIP_USE_EXTERNAL_POLARSSL: Use external PolarSSL library
- */
-#ifndef LWIP_USE_EXTERNAL_POLARSSL
-#define LWIP_USE_EXTERNAL_POLARSSL      0
-#endif
-
-/**
- * LWIP_USE_EXTERNAL_MBEDTLS: Use external mbed TLS library
- */
-#ifndef LWIP_USE_EXTERNAL_MBEDTLS
-#define LWIP_USE_EXTERNAL_MBEDTLS       0
-#endif
-
-/*
- * PPP Timeouts
- */
-
-/**
- * FSM_DEFTIMEOUT: Timeout time in seconds
- */
-#ifndef FSM_DEFTIMEOUT
-#define FSM_DEFTIMEOUT                  6
-#endif
-
-/**
- * FSM_DEFMAXTERMREQS: Maximum Terminate-Request transmissions
- */
-#ifndef FSM_DEFMAXTERMREQS
-#define FSM_DEFMAXTERMREQS              2
-#endif
-
-/**
- * FSM_DEFMAXCONFREQS: Maximum Configure-Request transmissions
- */
-#ifndef FSM_DEFMAXCONFREQS
-#define FSM_DEFMAXCONFREQS              10
-#endif
-
-/**
- * FSM_DEFMAXNAKLOOPS: Maximum number of nak loops
- */
-#ifndef FSM_DEFMAXNAKLOOPS
-#define FSM_DEFMAXNAKLOOPS              5
-#endif
-
-/**
- * UPAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req
- */
-#ifndef UPAP_DEFTIMEOUT
-#define UPAP_DEFTIMEOUT                 6
-#endif
-
-/**
- * UPAP_DEFTRANSMITS: Maximum number of auth-reqs to send
- */
-#ifndef UPAP_DEFTRANSMITS
-#define UPAP_DEFTRANSMITS               10
-#endif
-
-#if PPP_SERVER
-/**
- * UPAP_DEFREQTIME: Time to wait for auth-req from peer
- */
-#ifndef UPAP_DEFREQTIME
-#define UPAP_DEFREQTIME                 30
-#endif
-#endif /* PPP_SERVER */
-
-/**
- * CHAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req
- */
-#ifndef CHAP_DEFTIMEOUT
-#define CHAP_DEFTIMEOUT                 6
-#endif
-
-/**
- * CHAP_DEFTRANSMITS: max # times to send challenge
- */
-#ifndef CHAP_DEFTRANSMITS
-#define CHAP_DEFTRANSMITS               10
-#endif
-
-#if PPP_SERVER
-/**
- * CHAP_DEFRECHALLENGETIME: If this option is > 0, rechallenge the peer every n seconds
- */
-#ifndef CHAP_DEFRECHALLENGETIME
-#define CHAP_DEFRECHALLENGETIME         0
-#endif
-#endif /* PPP_SERVER */
-
-/**
- * EAP_DEFREQTIME: Time to wait for peer request
- */
-#ifndef EAP_DEFREQTIME
-#define EAP_DEFREQTIME                  6
-#endif
-
-/**
- * EAP_DEFALLOWREQ: max # times to accept requests
- */
-#ifndef EAP_DEFALLOWREQ
-#define EAP_DEFALLOWREQ                 10
-#endif
-
-#if PPP_SERVER
-/**
- * EAP_DEFTIMEOUT: Timeout (seconds) for rexmit
- */
-#ifndef EAP_DEFTIMEOUT
-#define EAP_DEFTIMEOUT                  6
-#endif
-
-/**
- * EAP_DEFTRANSMITS: max # times to transmit
- */
-#ifndef EAP_DEFTRANSMITS
-#define EAP_DEFTRANSMITS                10
-#endif
-#endif /* PPP_SERVER */
-
-/**
- * LCP_DEFLOOPBACKFAIL: Default number of times we receive our magic number from the peer
- * before deciding the link is looped-back.
- */
-#ifndef LCP_DEFLOOPBACKFAIL
-#define LCP_DEFLOOPBACKFAIL             10
-#endif
-
-/**
- * LCP_ECHOINTERVAL: Interval in seconds between keepalive echo requests, 0 to disable.
- */
-#ifndef LCP_ECHOINTERVAL
-#define LCP_ECHOINTERVAL                0
-#endif
-
-/**
- * LCP_MAXECHOFAILS: Number of unanswered echo requests before failure.
- */
-#ifndef LCP_MAXECHOFAILS
-#define LCP_MAXECHOFAILS                3
-#endif
-
-/**
- * PPP_MAXIDLEFLAG: Max Xmit idle time (in ms) before resend flag char.
- */
-#ifndef PPP_MAXIDLEFLAG
-#define PPP_MAXIDLEFLAG                 100
-#endif
-
-/**
- * PPP Packet sizes
- */
-
-/**
- * PPP_MRU: Default MRU
- */
-#ifndef PPP_MRU
-#define PPP_MRU                         1500
-#endif
-
-/**
- * PPP_DEFMRU: Default MRU to try
- */
-#ifndef PPP_DEFMRU
-#define PPP_DEFMRU                      1500
-#endif
-
-/**
- * PPP_MAXMRU: Normally limit MRU to this (pppd default = 16384)
- */
-#ifndef PPP_MAXMRU
-#define PPP_MAXMRU                      1500
-#endif
-
-/**
- * PPP_MINMRU: No MRUs below this
- */
-#ifndef PPP_MINMRU
-#define PPP_MINMRU                      128
-#endif
-
-/**
- * PPPOL2TP_DEFMRU: Default MTU and MRU for L2TP
- * Default = 1500 - PPPoE(6) - PPP Protocol(2) - IPv4 header(20) - UDP Header(8)
- * - L2TP Header(6) - HDLC Header(2) - PPP Protocol(2) - MPPE Header(2) - PPP Protocol(2)
- */
-#if PPPOL2TP_SUPPORT
-#ifndef PPPOL2TP_DEFMRU
-#define PPPOL2TP_DEFMRU                 1450
-#endif
-#endif /* PPPOL2TP_SUPPORT */
-
-/**
- * MAXNAMELEN: max length of hostname or name for auth
- */
-#ifndef MAXNAMELEN
-#define MAXNAMELEN                      256
-#endif
-
-/**
- * MAXSECRETLEN: max length of password or secret
- */
-#ifndef MAXSECRETLEN
-#define MAXSECRETLEN                    256
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Build triggers for embedded PolarSSL
- */
-#if !LWIP_USE_EXTERNAL_POLARSSL && !LWIP_USE_EXTERNAL_MBEDTLS
-
-/* CHAP, EAP, L2TP AUTH and MD5 Random require MD5 support */
-#if CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM
-#define LWIP_INCLUDED_POLARSSL_MD5      1
-#endif /* CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM */
-
-#if MSCHAP_SUPPORT
-
-/* MSCHAP require MD4 support */
-#define LWIP_INCLUDED_POLARSSL_MD4      1
-/* MSCHAP require SHA1 support */
-#define LWIP_INCLUDED_POLARSSL_SHA1     1
-/* MSCHAP require DES support */
-#define LWIP_INCLUDED_POLARSSL_DES      1
-
-/* MS-CHAP support is required for MPPE */
-#if MPPE_SUPPORT
-/* MPPE require ARC4 support */
-#define LWIP_INCLUDED_POLARSSL_ARC4     1
-#endif /* MPPE_SUPPORT */
-
-#endif /* MSCHAP_SUPPORT */
-
-#endif /* !LWIP_USE_EXTERNAL_POLARSSL && !LWIP_USE_EXTERNAL_MBEDTLS */
-
-/* Default value if unset */
-#ifndef LWIP_INCLUDED_POLARSSL_MD4
-#define LWIP_INCLUDED_POLARSSL_MD4      0
-#endif /* LWIP_INCLUDED_POLARSSL_MD4 */
-#ifndef LWIP_INCLUDED_POLARSSL_MD5
-#define LWIP_INCLUDED_POLARSSL_MD5      0
-#endif /* LWIP_INCLUDED_POLARSSL_MD5 */
-#ifndef LWIP_INCLUDED_POLARSSL_SHA1
-#define LWIP_INCLUDED_POLARSSL_SHA1     0
-#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */
-#ifndef LWIP_INCLUDED_POLARSSL_DES
-#define LWIP_INCLUDED_POLARSSL_DES      0
-#endif /* LWIP_INCLUDED_POLARSSL_DES */
-#ifndef LWIP_INCLUDED_POLARSSL_ARC4
-#define LWIP_INCLUDED_POLARSSL_ARC4     0
-#endif /* LWIP_INCLUDED_POLARSSL_ARC4 */
-
-#endif /* PPP_SUPPORT */
-
-#endif /* LWIP_PPP_OPTS_H */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppapi.h b/tools/sdk/include/lwip/netif/ppp/pppapi.h
deleted file mode 100644
index 9bda2a8cfd7..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/pppapi.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#ifndef LWIP_PPPAPI_H
-#define LWIP_PPPAPI_H
-
-#include "netif/ppp/ppp_opts.h"
-
-#if LWIP_PPP_API /* don't build if not configured for use in lwipopts.h */
-
-#include "lwip/sys.h"
-#include "lwip/netif.h"
-#include "lwip/priv/tcpip_priv.h"
-#include "netif/ppp/ppp.h"
-#if PPPOS_SUPPORT
-#include "netif/ppp/pppos.h"
-#endif /* PPPOS_SUPPORT */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct pppapi_msg_msg {
-  ppp_pcb *ppp;
-  union {
-#if ESP_LWIP
-    struct {
-      u8_t authtype;
-      const char *user;
-      const char *passwd;
-    } setauth;
-#endif
-#if PPP_NOTIFY_PHASE
-    struct {
-      ppp_notify_phase_cb_fn notify_phase_cb;
-    } setnotifyphasecb;
-#endif /* PPP_NOTIFY_PHASE */
-#if PPPOS_SUPPORT
-    struct {
-      struct netif *pppif;
-      pppos_output_cb_fn output_cb;
-      ppp_link_status_cb_fn link_status_cb;
-      void *ctx_cb;
-    } serialcreate;
-#endif /* PPPOS_SUPPORT */
-#if PPPOE_SUPPORT
-    struct {
-      struct netif *pppif;
-      struct netif *ethif;
-      const char *service_name;
-      const char *concentrator_name;
-      ppp_link_status_cb_fn link_status_cb;
-      void *ctx_cb;
-    } ethernetcreate;
-#endif /* PPPOE_SUPPORT */
-#if PPPOL2TP_SUPPORT
-    struct {
-      struct netif *pppif;
-      struct netif *netif;
-      API_MSG_M_DEF_C(ip_addr_t, ipaddr);
-      u16_t port;
-#if PPPOL2TP_AUTH_SUPPORT
-      const u8_t *secret;
-      u8_t secret_len;
-#endif /* PPPOL2TP_AUTH_SUPPORT */
-      ppp_link_status_cb_fn link_status_cb;
-      void *ctx_cb;
-    } l2tpcreate;
-#endif /* PPPOL2TP_SUPPORT */
-    struct {
-      u16_t holdoff;
-    } connect;
-    struct {
-      u8_t nocarrier;
-    } close;
-    struct {
-      u8_t cmd;
-      void *arg;
-    } ioctl;
-  } msg;
-};
-
-struct pppapi_msg {
-  struct tcpip_api_call_data call;
-  struct pppapi_msg_msg msg;
-};
-
-/* API for application */
-err_t pppapi_set_default(ppp_pcb *pcb);
-#if ESP_LWIP
-void pppapi_set_auth(ppp_pcb *pcb, u8_t authtype, const char *user, const char *passwd);
-#endif
-#if PPP_NOTIFY_PHASE
-err_t pppapi_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb);
-#endif /* PPP_NOTIFY_PHASE */
-#if PPPOS_SUPPORT
-ppp_pcb *pppapi_pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb, ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
-#endif /* PPPOS_SUPPORT */
-#if PPPOE_SUPPORT
-ppp_pcb *pppapi_pppoe_create(struct netif *pppif, struct netif *ethif, const char *service_name,
-                                const char *concentrator_name, ppp_link_status_cb_fn link_status_cb,
-                                void *ctx_cb);
-#endif /* PPPOE_SUPPORT */
-#if PPPOL2TP_SUPPORT
-ppp_pcb *pppapi_pppol2tp_create(struct netif *pppif, struct netif *netif, ip_addr_t *ipaddr, u16_t port,
-                            const u8_t *secret, u8_t secret_len,
-                            ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
-#endif /* PPPOL2TP_SUPPORT */
-err_t pppapi_connect(ppp_pcb *pcb, u16_t holdoff);
-#if PPP_SERVER
-err_t pppapi_listen(ppp_pcb *pcb);
-#endif /* PPP_SERVER */
-err_t pppapi_close(ppp_pcb *pcb, u8_t nocarrier);
-err_t pppapi_free(ppp_pcb *pcb);
-err_t pppapi_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_PPP_API */
-
-#endif /* LWIP_PPPAPI_H */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppcrypt.h b/tools/sdk/include/lwip/netif/ppp/pppcrypt.h
deleted file mode 100644
index a7b2099f25e..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/pppcrypt.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * pppcrypt.c - PPP/DES linkage for MS-CHAP and EAP SRP-SHA1
- *
- * Extracted from chap_ms.c by James Carlson.
- *
- * Copyright (c) 1995 Eric Rosenquist.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name(s) of the authors of this software must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission.
- *
- * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY
- * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-/* This header file is included in all PPP modules needing hashes and/or ciphers */
-
-#ifndef PPPCRYPT_H
-#define	PPPCRYPT_H
-
-/*
- * If included PolarSSL copy is not used, user is expected to include
- * external libraries in arch/cc.h (which is included by lwip/arch.h).
- */
-#include "lwip/arch.h"
-
-/*
- * Map hashes and ciphers functions to PolarSSL
- */
-#if !LWIP_USE_EXTERNAL_MBEDTLS
-
-#include "netif/ppp/polarssl/md4.h"
-#define lwip_md4_context md4_context
-#define lwip_md4_init(context)
-#define lwip_md4_starts md4_starts
-#define lwip_md4_update md4_update
-#define lwip_md4_finish md4_finish
-#define lwip_md4_free(context)
-
-#include "netif/ppp/polarssl/md5.h"
-#define lwip_md5_context md5_context
-#define lwip_md5_init(context)
-#define lwip_md5_starts md5_starts
-#define lwip_md5_update md5_update
-#define lwip_md5_finish md5_finish
-#define lwip_md5_free(context)
-
-#include "netif/ppp/polarssl/sha1.h"
-#define lwip_sha1_context sha1_context
-#define lwip_sha1_init(context)
-#define lwip_sha1_starts sha1_starts
-#define lwip_sha1_update sha1_update
-#define lwip_sha1_finish sha1_finish
-#define lwip_sha1_free(context)
-
-#include "netif/ppp/polarssl/des.h"
-#define lwip_des_context des_context
-#define lwip_des_init(context)
-#define lwip_des_setkey_enc des_setkey_enc
-#define lwip_des_crypt_ecb des_crypt_ecb
-#define lwip_des_free(context)
-
-#include "netif/ppp/polarssl/arc4.h"
-#define lwip_arc4_context arc4_context
-#define lwip_arc4_init(context)
-#define lwip_arc4_setup arc4_setup
-#define lwip_arc4_crypt arc4_crypt
-#define lwip_arc4_free(context)
-
-#endif /* !LWIP_USE_EXTERNAL_MBEDTLS */
-
-/*
- * Map hashes and ciphers functions to mbed TLS
- */
-#if LWIP_USE_EXTERNAL_MBEDTLS
-
-#define lwip_md4_context mbedtls_md4_context
-#define lwip_md4_init mbedtls_md4_init
-#define lwip_md4_starts mbedtls_md4_starts
-#define lwip_md4_update mbedtls_md4_update
-#define lwip_md4_finish mbedtls_md4_finish
-#define lwip_md4_free mbedtls_md4_free
-
-#define lwip_md5_context mbedtls_md5_context
-#define lwip_md5_init mbedtls_md5_init
-#define lwip_md5_starts mbedtls_md5_starts
-#define lwip_md5_update mbedtls_md5_update
-#define lwip_md5_finish mbedtls_md5_finish
-#define lwip_md5_free mbedtls_md5_free
-
-#define lwip_sha1_context mbedtls_sha1_context
-#define lwip_sha1_init mbedtls_sha1_init
-#define lwip_sha1_starts mbedtls_sha1_starts
-#define lwip_sha1_update mbedtls_sha1_update
-#define lwip_sha1_finish mbedtls_sha1_finish
-#define lwip_sha1_free mbedtls_sha1_free
-
-#define lwip_des_context mbedtls_des_context
-#define lwip_des_init mbedtls_des_init
-#define lwip_des_setkey_enc mbedtls_des_setkey_enc
-#define lwip_des_crypt_ecb mbedtls_des_crypt_ecb
-#define lwip_des_free mbedtls_des_free
-
-#define lwip_arc4_context mbedtls_arc4_context
-#define lwip_arc4_init mbedtls_arc4_init
-#define lwip_arc4_setup mbedtls_arc4_setup
-#define lwip_arc4_crypt(context, buffer, length) mbedtls_arc4_crypt(context, length, buffer, buffer)
-#define lwip_arc4_free mbedtls_arc4_free
-
-#endif /* LWIP_USE_EXTERNAL_MBEDTLS */
-
-void pppcrypt_56_to_64_bit_key(u_char *key, u_char *des_key);
-
-#endif /* PPPCRYPT_H */
-
-#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppdebug.h b/tools/sdk/include/lwip/netif/ppp/pppdebug.h
deleted file mode 100644
index 7ead0459104..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/pppdebug.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*****************************************************************************
-* pppdebug.h - System debugging utilities.
-*
-* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc.
-* portions Copyright (c) 1998 Global Election Systems Inc.
-* portions Copyright (c) 2001 by Cognizant Pty Ltd.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY (please don't use tabs!)
-*
-* 03-01-01 Marc Boucher <marc@mbsi.ca>
-*   Ported to lwIP.
-* 98-07-29 Guy Lancaster <lancasterg@acm.org>, Global Election Systems Inc.
-*   Original.
-*
-*****************************************************************************
-*/
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef PPPDEBUG_H
-#define PPPDEBUG_H
-
-/* Trace levels. */
-#define LOG_CRITICAL  (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
-#define LOG_ERR       (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE)
-#define LOG_NOTICE    (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
-#define LOG_WARNING   (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING)
-#define LOG_INFO      (PPP_DEBUG)
-#define LOG_DETAIL    (PPP_DEBUG)
-#define LOG_DEBUG     (PPP_DEBUG)
-
-#if PPP_DEBUG
-
-#define MAINDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
-#define SYSDEBUG(a)     LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
-#define FSMDEBUG(a)     LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
-#define LCPDEBUG(a)     LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
-#define IPCPDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
-#define IPV6CPDEBUG(a)  LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
-#define UPAPDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
-#define CHAPDEBUG(a)    LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a)
-#define PPPDEBUG(a, b)  LWIP_DEBUGF(a, b)
-
-#else /* PPP_DEBUG */
-
-#define MAINDEBUG(a)
-#define SYSDEBUG(a)
-#define FSMDEBUG(a)
-#define LCPDEBUG(a)
-#define IPCPDEBUG(a)
-#define IPV6CPDEBUG(a)
-#define UPAPDEBUG(a)
-#define CHAPDEBUG(a)
-#define PPPDEBUG(a, b)
-
-#endif /* PPP_DEBUG */
-
-#endif /* PPPDEBUG_H */
-
-#endif /* PPP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppoe.h b/tools/sdk/include/lwip/netif/ppp/pppoe.h
deleted file mode 100644
index 9f8f2892b43..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/pppoe.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*****************************************************************************
-* pppoe.h - PPP Over Ethernet implementation for lwIP.
-*
-* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc.
-*
-* The authors hereby grant permission to use, copy, modify, distribute,
-* and license this software and its documentation for any purpose, provided
-* that existing copyright notices are retained in all copies and that this
-* notice and the following disclaimer are included verbatim in any 
-* distributions. No written agreement, license, or royalty fee is required
-* for any of the authorized uses.
-*
-* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-******************************************************************************
-* REVISION HISTORY
-*
-* 06-01-01 Marc Boucher <marc@mbsi.ca>
-*   Ported to lwIP.
-*****************************************************************************/
-
-
-
-/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */
-
-/*-
- * Copyright (c) 2002 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Martin Husemann <martin@NetBSD.org>.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *        This product includes software developed by the NetBSD
- *        Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef PPP_OE_H
-#define PPP_OE_H
-
-#include "ppp.h"
-#include "lwip/etharp.h"
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct pppoehdr {
-  PACK_STRUCT_FLD_8(u8_t vertype);
-  PACK_STRUCT_FLD_8(u8_t code);
-  PACK_STRUCT_FIELD(u16_t session);
-  PACK_STRUCT_FIELD(u16_t plen);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/bpstruct.h"
-#endif
-PACK_STRUCT_BEGIN
-struct pppoetag {
-  PACK_STRUCT_FIELD(u16_t tag);
-  PACK_STRUCT_FIELD(u16_t len);
-} PACK_STRUCT_STRUCT;
-PACK_STRUCT_END
-#ifdef PACK_STRUCT_USE_INCLUDES
-#  include "arch/epstruct.h"
-#endif
-
-
-#define PPPOE_STATE_INITIAL   0
-#define PPPOE_STATE_PADI_SENT 1
-#define PPPOE_STATE_PADR_SENT 2
-#define PPPOE_STATE_SESSION   3
-/* passive */
-#define PPPOE_STATE_PADO_SENT 1
-
-#define PPPOE_HEADERLEN       sizeof(struct pppoehdr)
-#define PPPOE_VERTYPE         0x11    /* VER=1, TYPE = 1 */
-
-#define PPPOE_TAG_EOL         0x0000  /* end of list */
-#define PPPOE_TAG_SNAME       0x0101  /* service name */
-#define PPPOE_TAG_ACNAME      0x0102  /* access concentrator name */
-#define PPPOE_TAG_HUNIQUE     0x0103  /* host unique */
-#define PPPOE_TAG_ACCOOKIE    0x0104  /* AC cookie */
-#define PPPOE_TAG_VENDOR      0x0105  /* vendor specific */
-#define PPPOE_TAG_RELAYSID    0x0110  /* relay session id */
-#define PPPOE_TAG_SNAME_ERR   0x0201  /* service name error */
-#define PPPOE_TAG_ACSYS_ERR   0x0202  /* AC system error */
-#define PPPOE_TAG_GENERIC_ERR 0x0203  /* gerneric error */
-
-#define PPPOE_CODE_PADI       0x09    /* Active Discovery Initiation */
-#define PPPOE_CODE_PADO       0x07    /* Active Discovery Offer */
-#define PPPOE_CODE_PADR       0x19    /* Active Discovery Request */
-#define PPPOE_CODE_PADS       0x65    /* Active Discovery Session confirmation */
-#define PPPOE_CODE_PADT       0xA7    /* Active Discovery Terminate */
-
-#ifndef PPPOE_MAX_AC_COOKIE_LEN
-#define PPPOE_MAX_AC_COOKIE_LEN   64
-#endif
-
-struct pppoe_softc {
-  struct pppoe_softc *next;
-  struct netif *sc_ethif;      /* ethernet interface we are using */
-  ppp_pcb *pcb;                /* PPP PCB */
-
-  struct eth_addr sc_dest;     /* hardware address of concentrator */
-  u16_t sc_session;            /* PPPoE session id */
-  u8_t sc_state;               /* discovery phase or session connected */
-
-#ifdef PPPOE_TODO
-  u8_t *sc_service_name;       /* if != NULL: requested name of service */
-  u8_t *sc_concentrator_name;  /* if != NULL: requested concentrator id */
-#endif /* PPPOE_TODO */
-  u8_t sc_ac_cookie[PPPOE_MAX_AC_COOKIE_LEN]; /* content of AC cookie we must echo back */
-  u8_t sc_ac_cookie_len;       /* length of cookie data */
-#ifdef PPPOE_SERVER
-  u8_t *sc_hunique;            /* content of host unique we must echo back */
-  u8_t sc_hunique_len;         /* length of host unique */
-#endif
-  u8_t sc_padi_retried;        /* number of PADI retries already done */
-  u8_t sc_padr_retried;        /* number of PADR retries already done */
-};
-
-
-#define pppoe_init() /* compatibility define, no initialization needed */
-
-ppp_pcb *pppoe_create(struct netif *pppif,
-       struct netif *ethif,
-       const char *service_name, const char *concentrator_name,
-       ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
-
-/*
- * Functions called from lwIP
- * DO NOT CALL FROM lwIP USER APPLICATION.
- */
-void pppoe_disc_input(struct netif *netif, struct pbuf *p);
-void pppoe_data_input(struct netif *netif, struct pbuf *p);
-
-#endif /* PPP_OE_H */
-
-#endif /* PPP_SUPPORT && PPPOE_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppol2tp.h b/tools/sdk/include/lwip/netif/ppp/pppol2tp.h
deleted file mode 100644
index f03950e65df..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/pppol2tp.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/**
- * @file
- * Network Point to Point Protocol over Layer 2 Tunneling Protocol header file.
- *
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && PPPOL2TP_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef PPPOL2TP_H
-#define PPPOL2TP_H
-
-#include "ppp.h"
-
-/* Timeout */
-#define PPPOL2TP_CONTROL_TIMEOUT         (5*1000)  /* base for quick timeout calculation */
-#define PPPOL2TP_SLOW_RETRY              (60*1000) /* persistent retry interval */
-
-#define PPPOL2TP_MAXSCCRQ                4         /* retry SCCRQ four times (quickly) */
-#define PPPOL2TP_MAXICRQ                 4         /* retry IRCQ four times */
-#define PPPOL2TP_MAXICCN                 4         /* retry ICCN four times */
-
-/* L2TP header flags */
-#define PPPOL2TP_HEADERFLAG_CONTROL      0x8000
-#define PPPOL2TP_HEADERFLAG_LENGTH       0x4000
-#define PPPOL2TP_HEADERFLAG_SEQUENCE     0x0800
-#define PPPOL2TP_HEADERFLAG_OFFSET       0x0200
-#define PPPOL2TP_HEADERFLAG_PRIORITY     0x0100
-#define PPPOL2TP_HEADERFLAG_VERSION      0x0002
-
-/* Mandatory bits for control: Control, Length, Sequence, Version 2 */
-#define PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY     (PPPOL2TP_HEADERFLAG_CONTROL|PPPOL2TP_HEADERFLAG_LENGTH|PPPOL2TP_HEADERFLAG_SEQUENCE|PPPOL2TP_HEADERFLAG_VERSION)
-/* Forbidden bits for control: Offset, Priority */
-#define PPPOL2TP_HEADERFLAG_CONTROL_FORBIDDEN     (PPPOL2TP_HEADERFLAG_OFFSET|PPPOL2TP_HEADERFLAG_PRIORITY)
-
-/* Mandatory bits for data: Version 2 */
-#define PPPOL2TP_HEADERFLAG_DATA_MANDATORY        (PPPOL2TP_HEADERFLAG_VERSION)
-
-/* AVP (Attribute Value Pair) header */
-#define PPPOL2TP_AVPHEADERFLAG_MANDATORY  0x8000
-#define PPPOL2TP_AVPHEADERFLAG_HIDDEN     0x4000
-#define PPPOL2TP_AVPHEADERFLAG_LENGTHMASK 0x03ff
-
-/* -- AVP - Message type */
-#define PPPOL2TP_AVPTYPE_MESSAGE      0 /* Message type */
-
-/* Control Connection Management */
-#define PPPOL2TP_MESSAGETYPE_SCCRQ    1 /* Start Control Connection Request */
-#define PPPOL2TP_MESSAGETYPE_SCCRP    2 /* Start Control Connection Reply */
-#define PPPOL2TP_MESSAGETYPE_SCCCN    3 /* Start Control Connection Connected */
-#define PPPOL2TP_MESSAGETYPE_STOPCCN  4 /* Stop Control Connection Notification */
-#define PPPOL2TP_MESSAGETYPE_HELLO    6 /* Hello */
-/* Call Management */
-#define PPPOL2TP_MESSAGETYPE_OCRQ     7 /* Outgoing Call Request */
-#define PPPOL2TP_MESSAGETYPE_OCRP     8 /* Outgoing Call Reply */
-#define PPPOL2TP_MESSAGETYPE_OCCN     9 /* Outgoing Call Connected */
-#define PPPOL2TP_MESSAGETYPE_ICRQ    10 /* Incoming Call Request */
-#define PPPOL2TP_MESSAGETYPE_ICRP    11 /* Incoming Call Reply */
-#define PPPOL2TP_MESSAGETYPE_ICCN    12 /* Incoming Call Connected */
-#define PPPOL2TP_MESSAGETYPE_CDN     14 /* Call Disconnect Notify */
-/* Error reporting */
-#define PPPOL2TP_MESSAGETYPE_WEN     15 /* WAN Error Notify */
-/* PPP Session Control */
-#define PPPOL2TP_MESSAGETYPE_SLI     16 /* Set Link Info */
-
-/* -- AVP - Result code */
-#define PPPOL2TP_AVPTYPE_RESULTCODE   1 /* Result code */
-#define PPPOL2TP_RESULTCODE           1 /* General request to clear control connection */
-
-/* -- AVP - Protocol version (!= L2TP Header version) */
-#define PPPOL2TP_AVPTYPE_VERSION      2
-#define PPPOL2TP_VERSION         0x0100 /* L2TP Protocol version 1, revision 0 */
-
-/* -- AVP - Framing capabilities */
-#define PPPOL2TP_AVPTYPE_FRAMINGCAPABILITIES           3 /* Bearer capabilities */
-#define PPPOL2TP_FRAMINGCAPABILITIES          0x00000003 /* Async + Sync framing */
-
-/* -- AVP - Bearer capabilities */
-#define PPPOL2TP_AVPTYPE_BEARERCAPABILITIES           4 /* Bearer capabilities */
-#define PPPOL2TP_BEARERCAPABILITIES          0x00000003 /* Analog + Digital Access */
-
-/* -- AVP - Tie breaker */
-#define PPPOL2TP_AVPTYPE_TIEBREAKER   5
-
-/* -- AVP - Host name */
-#define PPPOL2TP_AVPTYPE_HOSTNAME     7 /* Host name */
-#define PPPOL2TP_HOSTNAME        "lwIP" /* FIXME: make it configurable */
-
-/* -- AVP - Vendor name */
-#define PPPOL2TP_AVPTYPE_VENDORNAME   8 /* Vendor name */
-#define PPPOL2TP_VENDORNAME      "lwIP" /* FIXME: make it configurable */
-
-/* -- AVP - Assign tunnel ID */
-#define PPPOL2TP_AVPTYPE_TUNNELID     9 /* Assign Tunnel ID */
-
-/* -- AVP - Receive window size */
-#define PPPOL2TP_AVPTYPE_RECEIVEWINDOWSIZE  10 /* Receive window size */
-#define PPPOL2TP_RECEIVEWINDOWSIZE           8 /* FIXME: make it configurable */
-
-/* -- AVP - Challenge */
-#define PPPOL2TP_AVPTYPE_CHALLENGE   11 /* Challenge */
-
-/* -- AVP - Cause code */
-#define PPPOL2TP_AVPTYPE_CAUSECODE   12 /* Cause code*/
-
-/* -- AVP - Challenge response */
-#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE   13 /* Challenge response */
-#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE_SIZE  16
-
-/* -- AVP - Assign session ID */
-#define PPPOL2TP_AVPTYPE_SESSIONID   14 /* Assign Session ID */
-
-/* -- AVP - Call serial number */
-#define PPPOL2TP_AVPTYPE_CALLSERIALNUMBER   15 /* Call Serial Number */
-
-/* -- AVP - Framing type */
-#define PPPOL2TP_AVPTYPE_FRAMINGTYPE         19 /* Framing Type */
-#define PPPOL2TP_FRAMINGTYPE         0x00000001 /* Sync framing */
-
-/* -- AVP - TX Connect Speed */
-#define PPPOL2TP_AVPTYPE_TXCONNECTSPEED      24 /* TX Connect Speed */
-#define PPPOL2TP_TXCONNECTSPEED       100000000 /* Connect speed: 100 Mbits/s */
-
-/* L2TP Session state */
-#define PPPOL2TP_STATE_INITIAL     0
-#define PPPOL2TP_STATE_SCCRQ_SENT  1
-#define PPPOL2TP_STATE_ICRQ_SENT   2
-#define PPPOL2TP_STATE_ICCN_SENT   3
-#define PPPOL2TP_STATE_DATA        4
-
-#define PPPOL2TP_OUTPUT_DATA_HEADER_LEN   6 /* Our data header len */
-
-/*
- * PPPoL2TP interface control block.
- */
-typedef struct pppol2tp_pcb_s pppol2tp_pcb;
-struct pppol2tp_pcb_s {
-  ppp_pcb *ppp;                /* PPP PCB */
-  u8_t phase;                  /* L2TP phase */
-  struct udp_pcb *udp;         /* UDP L2TP Socket */
-  struct netif *netif;         /* Output interface, used as a default route */
-  ip_addr_t remote_ip;         /* LNS IP Address */
-  u16_t remote_port;           /* LNS port */
-#if PPPOL2TP_AUTH_SUPPORT
-  const u8_t *secret;          /* Secret string */
-  u8_t secret_len;             /* Secret string length */
-  u8_t secret_rv[16];          /* Random vector */
-  u8_t challenge_hash[16];     /* Challenge response */
-  u8_t send_challenge;         /* Boolean whether the next sent packet should contains a challenge response */
-#endif /* PPPOL2TP_AUTH_SUPPORT */
-
-  u16_t tunnel_port;           /* Tunnel port */
-  u16_t our_ns;                /* NS to peer */
-  u16_t peer_nr;               /* NR from peer */
-  u16_t peer_ns;               /* NS from peer */
-  u16_t source_tunnel_id;      /* Tunnel ID assigned by peer */
-  u16_t remote_tunnel_id;      /* Tunnel ID assigned to peer */
-  u16_t source_session_id;     /* Session ID assigned by peer */
-  u16_t remote_session_id;     /* Session ID assigned to peer */
-
-  u8_t sccrq_retried;          /* number of SCCRQ retries already done */
-  u8_t icrq_retried;           /* number of ICRQ retries already done */
-  u8_t iccn_retried;           /* number of ICCN retries already done */
-};
-
-
-/* Create a new L2TP session. */
-ppp_pcb *pppol2tp_create(struct netif *pppif,
-       struct netif *netif, const ip_addr_t *ipaddr, u16_t port,
-       const u8_t *secret, u8_t secret_len,
-       ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
-
-#endif /* PPPOL2TP_H */
-#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/pppos.h b/tools/sdk/include/lwip/netif/ppp/pppos.h
deleted file mode 100644
index 380a965ce6a..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/pppos.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/**
- * @file
- * Network Point to Point Protocol over Serial header file.
- *
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && PPPOS_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef PPPOS_H
-#define PPPOS_H
-
-#include "lwip/sys.h"
-
-#include "ppp.h"
-#include "vj.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* PPP packet parser states.  Current state indicates operation yet to be
- * completed. */
-enum {
-  PDIDLE = 0,  /* Idle state - waiting. */
-  PDSTART,     /* Process start flag. */
-  PDADDRESS,   /* Process address field. */
-  PDCONTROL,   /* Process control field. */
-  PDPROTOCOL1, /* Process protocol field 1. */
-  PDPROTOCOL2, /* Process protocol field 2. */
-  PDDATA       /* Process data byte. */
-};
-
-/* PPPoS serial output callback function prototype */
-typedef u32_t (*pppos_output_cb_fn)(ppp_pcb *pcb, u8_t *data, u32_t len, void *ctx);
-
-/*
- * Extended asyncmap - allows any character to be escaped.
- */
-typedef u8_t ext_accm[32];
-
-/*
- * PPPoS interface control block.
- */
-typedef struct pppos_pcb_s pppos_pcb;
-struct pppos_pcb_s {
-  /* -- below are data that will NOT be cleared between two sessions */
-  ppp_pcb *ppp;                    /* PPP PCB */
-  pppos_output_cb_fn output_cb;    /* PPP serial output callback */
-
-  /* -- below are data that will be cleared between two sessions
-   *
-   * last_xmit must be the first member of cleared members, because it is
-   * used to know which part must not be cleared.
-   */
-  u32_t last_xmit;                 /* Time of last transmission. */
-  ext_accm out_accm;               /* Async-Ctl-Char-Map for output. */
-
-  /* flags */
-  unsigned int open            :1; /* Set if PPPoS is open */
-  unsigned int pcomp           :1; /* Does peer accept protocol compression? */
-  unsigned int accomp          :1; /* Does peer accept addr/ctl compression? */
-
-  /* PPPoS rx */
-  ext_accm in_accm;                /* Async-Ctl-Char-Map for input. */
-  struct pbuf *in_head, *in_tail;  /* The input packet. */
-  u16_t in_protocol;               /* The input protocol code. */
-  u16_t in_fcs;                    /* Input Frame Check Sequence value. */
-  u8_t in_state;                   /* The input process state. */
-  u8_t in_escaped;                 /* Escape next character. */
-};
-
-/* Create a new PPPoS session. */
-ppp_pcb *pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb,
-       ppp_link_status_cb_fn link_status_cb, void *ctx_cb);
-
-#if !NO_SYS && !PPP_INPROC_IRQ_SAFE
-/* Pass received raw characters to PPPoS to be decoded through lwIP TCPIP thread. */
-err_t pppos_input_tcpip(ppp_pcb *ppp, u8_t *s, int l);
-#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */
-
-/* PPP over Serial: this is the input function to be called for received data. */
-void pppos_input(ppp_pcb *ppp, u8_t* data, int len);
-
-
-/*
- * Functions called from lwIP
- * DO NOT CALL FROM lwIP USER APPLICATION.
- */
-#if !NO_SYS && !PPP_INPROC_IRQ_SAFE
-err_t pppos_input_sys(struct pbuf *p, struct netif *inp);
-#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PPPOS_H */
-#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/upap.h b/tools/sdk/include/lwip/netif/ppp/upap.h
deleted file mode 100644
index 7da792ecc72..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/upap.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * upap.h - User/Password Authentication Protocol definitions.
- *
- * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * 3. The name "Carnegie Mellon University" must not be used to
- *    endorse or promote products derived from this software without
- *    prior written permission. For permission or any legal
- *    details, please contact
- *      Office of Technology Transfer
- *      Carnegie Mellon University
- *      5000 Forbes Avenue
- *      Pittsburgh, PA  15213-3890
- *      (412) 268-4387, fax: (412) 268-7395
- *      tech-transfer@andrew.cmu.edu
- *
- * 4. Redistributions of any form whatsoever must retain the following
- *    acknowledgment:
- *    "This product includes software developed by Computing Services
- *     at Carnegie Mellon University (http://www.cmu.edu/computing/)."
- *
- * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO
- * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE
- * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
- * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
- * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- * $Id: upap.h,v 1.8 2002/12/04 23:03:33 paulus Exp $
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && PAP_SUPPORT  /* don't build if not configured for use in lwipopts.h */
-
-#ifndef UPAP_H
-#define UPAP_H
-
-#include "ppp.h"
-
-/*
- * Packet header = Code, id, length.
- */
-#define UPAP_HEADERLEN	4
-
-
-/*
- * UPAP codes.
- */
-#define UPAP_AUTHREQ	1	/* Authenticate-Request */
-#define UPAP_AUTHACK	2	/* Authenticate-Ack */
-#define UPAP_AUTHNAK	3	/* Authenticate-Nak */
-
-
-/*
- * Client states.
- */
-#define UPAPCS_INITIAL	0	/* Connection down */
-#define UPAPCS_CLOSED	1	/* Connection up, haven't requested auth */
-#define UPAPCS_PENDING	2	/* Connection down, have requested auth */
-#define UPAPCS_AUTHREQ	3	/* We've sent an Authenticate-Request */
-#define UPAPCS_OPEN	4	/* We've received an Ack */
-#define UPAPCS_BADAUTH	5	/* We've received a Nak */
-
-/*
- * Server states.
- */
-#define UPAPSS_INITIAL	0	/* Connection down */
-#define UPAPSS_CLOSED	1	/* Connection up, haven't requested auth */
-#define UPAPSS_PENDING	2	/* Connection down, have requested auth */
-#define UPAPSS_LISTEN	3	/* Listening for an Authenticate */
-#define UPAPSS_OPEN	4	/* We've sent an Ack */
-#define UPAPSS_BADAUTH	5	/* We've sent a Nak */
-
-
-/*
- * Timeouts.
- */
-#if 0 /* moved to ppp_opts.h */
-#define UPAP_DEFTIMEOUT	3	/* Timeout (seconds) for retransmitting req */
-#define UPAP_DEFREQTIME	30	/* Time to wait for auth-req from peer */
-#endif /* moved to ppp_opts.h */
-
-/*
- * Each interface is described by upap structure.
- */
-#if PAP_SUPPORT
-typedef struct upap_state {
-    const char *us_user;	/* User */
-    u8_t us_userlen;		/* User length */
-    const char *us_passwd;	/* Password */
-    u8_t us_passwdlen;		/* Password length */
-    u8_t us_clientstate;	/* Client state */
-#if PPP_SERVER
-    u8_t us_serverstate;	/* Server state */
-#endif /* PPP_SERVER */
-    u8_t us_id;		        /* Current id */
-    u8_t us_transmits;		/* Number of auth-reqs sent */
-} upap_state;
-#endif /* PAP_SUPPORT */
-
-
-void upap_authwithpeer(ppp_pcb *pcb, const char *user, const char *password);
-#if PPP_SERVER
-void upap_authpeer(ppp_pcb *pcb);
-#endif /* PPP_SERVER */
-
-extern const struct protent pap_protent;
-
-#endif /* UPAP_H */
-#endif /* PPP_SUPPORT && PAP_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/ppp/vj.h b/tools/sdk/include/lwip/netif/ppp/vj.h
deleted file mode 100644
index 7f389c846f7..00000000000
--- a/tools/sdk/include/lwip/netif/ppp/vj.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Definitions for tcp compression routines.
- *
- * $Id: vj.h,v 1.7 2010/02/22 17:52:09 goldsimon Exp $
- *
- * Copyright (c) 1989 Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the University of California, Berkeley.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989:
- * - Initial distribution.
- */
-
-#include "netif/ppp/ppp_opts.h"
-#if PPP_SUPPORT && VJ_SUPPORT /* don't build if not configured for use in lwipopts.h */
-
-#ifndef VJ_H
-#define VJ_H
-
-#include "lwip/ip.h"
-#include "lwip/priv/tcp_priv.h"
-
-#define MAX_SLOTS 16 /* must be > 2 and < 256 */
-#define MAX_HDR   128
-
-/*
- * Compressed packet format:
- *
- * The first octet contains the packet type (top 3 bits), TCP
- * 'push' bit, and flags that indicate which of the 4 TCP sequence
- * numbers have changed (bottom 5 bits).  The next octet is a
- * conversation number that associates a saved IP/TCP header with
- * the compressed packet.  The next two octets are the TCP checksum
- * from the original datagram.  The next 0 to 15 octets are
- * sequence number changes, one change per bit set in the header
- * (there may be no changes and there are two special cases where
- * the receiver implicitly knows what changed -- see below).
- *
- * There are 5 numbers which can change (they are always inserted
- * in the following order): TCP urgent pointer, window,
- * acknowlegement, sequence number and IP ID.  (The urgent pointer
- * is different from the others in that its value is sent, not the
- * change in value.)  Since typical use of SLIP links is biased
- * toward small packets (see comments on MTU/MSS below), changes
- * use a variable length coding with one octet for numbers in the
- * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the
- * range 256 - 65535 or 0.  (If the change in sequence number or
- * ack is more than 65535, an uncompressed packet is sent.)
- */
-
-/*
- * Packet types (must not conflict with IP protocol version)
- *
- * The top nibble of the first octet is the packet type.  There are
- * three possible types: IP (not proto TCP or tcp with one of the
- * control flags set); uncompressed TCP (a normal IP/TCP packet but
- * with the 8-bit protocol field replaced by an 8-bit connection id --
- * this type of packet syncs the sender & receiver); and compressed
- * TCP (described above).
- *
- * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and
- * is logically part of the 4-bit "changes" field that follows.  Top
- * three bits are actual packet type.  For backward compatibility
- * and in the interest of conserving bits, numbers are chosen so the
- * IP protocol version number (4) which normally appears in this nibble
- * means "IP packet".
- */
-
-/* packet types */
-#define TYPE_IP               0x40
-#define TYPE_UNCOMPRESSED_TCP 0x70
-#define TYPE_COMPRESSED_TCP   0x80
-#define TYPE_ERROR            0x00
-
-/* Bits in first octet of compressed packet */
-#define NEW_C 0x40 /* flag bits for what changed in a packet */
-#define NEW_I 0x20
-#define NEW_S 0x08
-#define NEW_A 0x04
-#define NEW_W 0x02
-#define NEW_U 0x01
-
-/* reserved, special-case values of above */
-#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */
-#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */
-#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U)
-
-#define TCP_PUSH_BIT 0x10
-
-
-/*
- * "state" data for each active tcp conversation on the wire.  This is
- * basically a copy of the entire IP/TCP header from the last packet
- * we saw from the conversation together with a small identifier
- * the transmit & receive ends of the line use to locate saved header.
- */
-struct cstate {
-  struct cstate *cs_next; /* next most recently used state (xmit only) */
-  u16_t cs_hlen;        /* size of hdr (receive only) */
-  u8_t cs_id;           /* connection # associated with this state */
-  u8_t cs_filler;
-  union {
-    char csu_hdr[MAX_HDR];
-    struct ip_hdr csu_ip;     /* ip/tcp hdr from most recent packet */
-  } vjcs_u;
-};
-#define cs_ip vjcs_u.csu_ip
-#define cs_hdr vjcs_u.csu_hdr
-
-
-struct vjstat {
-  u32_t vjs_packets;        /* outbound packets */
-  u32_t vjs_compressed;     /* outbound compressed packets */
-  u32_t vjs_searches;       /* searches for connection state */
-  u32_t vjs_misses;         /* times couldn't find conn. state */
-  u32_t vjs_uncompressedin; /* inbound uncompressed packets */
-  u32_t vjs_compressedin;   /* inbound compressed packets */
-  u32_t vjs_errorin;        /* inbound unknown type packets */
-  u32_t vjs_tossed;         /* inbound packets tossed because of error */
-};
-
-/*
- * all the state data for one serial line (we need one of these per line).
- */
-struct vjcompress {
-  struct cstate *last_cs;          /* most recently used tstate */
-  u8_t last_recv;                /* last rcvd conn. id */
-  u8_t last_xmit;                /* last sent conn. id */
-  u16_t flags;
-  u8_t maxSlotIndex;
-  u8_t compressSlot;             /* Flag indicating OK to compress slot ID. */
-#if LINK_STATS
-  struct vjstat stats;
-#endif
-  struct cstate tstate[MAX_SLOTS]; /* xmit connection states */
-  struct cstate rstate[MAX_SLOTS]; /* receive connection states */
-};
-
-/* flag values */
-#define VJF_TOSS 1U /* tossing rcvd frames because of input err */
-
-extern void  vj_compress_init    (struct vjcompress *comp);
-extern u8_t  vj_compress_tcp     (struct vjcompress *comp, struct pbuf **pb);
-extern void  vj_uncompress_err   (struct vjcompress *comp);
-extern int   vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp);
-extern int   vj_uncompress_tcp   (struct pbuf **nb, struct vjcompress *comp);
-
-#endif /* VJ_H */
-
-#endif /* PPP_SUPPORT && VJ_SUPPORT */
diff --git a/tools/sdk/include/lwip/netif/slipif.h b/tools/sdk/include/lwip/netif/slipif.h
deleted file mode 100644
index 65ba31f835b..00000000000
--- a/tools/sdk/include/lwip/netif/slipif.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**
- * @file
- *
- * SLIP netif API
- */
-
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Institute nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef LWIP_HDR_NETIF_SLIPIF_H
-#define LWIP_HDR_NETIF_SLIPIF_H
-
-#include "lwip/opt.h"
-#include "lwip/netif.h"
-
-/** Set this to 1 to start a thread that blocks reading on the serial line
- * (using sio_read()).
- */
-#ifndef SLIP_USE_RX_THREAD
-#define SLIP_USE_RX_THREAD !NO_SYS
-#endif
-
-/** Set this to 1 to enable functions to pass in RX bytes from ISR context.
- * If enabled, slipif_received_byte[s]() process incoming bytes and put assembled
- * packets on a queue, which is fed into lwIP from slipif_poll().
- * If disabled, slipif_poll() polls the serial line (using sio_tryread()).
- */
-#ifndef SLIP_RX_FROM_ISR
-#define SLIP_RX_FROM_ISR 0
-#endif
-
-/** Set this to 1 (default for SLIP_RX_FROM_ISR) to queue incoming packets
- * received by slipif_received_byte[s]() as long as PBUF_POOL pbufs are available.
- * If disabled, packets will be dropped if more than one packet is received.
- */
-#ifndef SLIP_RX_QUEUE
-#define SLIP_RX_QUEUE SLIP_RX_FROM_ISR
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-err_t slipif_init(struct netif * netif);
-void slipif_poll(struct netif *netif);
-#if SLIP_RX_FROM_ISR
-void slipif_process_rxqueue(struct netif *netif);
-void slipif_received_byte(struct netif *netif, u8_t data);
-void slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len);
-#endif /* SLIP_RX_FROM_ISR */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_HDR_NETIF_SLIPIF_H */
-
diff --git a/tools/sdk/include/lwip/netif/wlanif.h b/tools/sdk/include/lwip/netif/wlanif.h
deleted file mode 100644
index 9c79f5b0aff..00000000000
--- a/tools/sdk/include/lwip/netif/wlanif.h
+++ /dev/null
@@ -1,42 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef _WLAN_LWIP_IF_H_
-#define _WLAN_LWIP_IF_H_
-
-#include "esp_wifi.h"
-
-#include "esp_wifi_internal.h"
-
-#include "lwip/err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-err_t wlanif_init_ap(struct netif *netif);
-err_t wlanif_init_sta(struct netif *netif);
-
-void wlanif_input(struct netif *netif, void *buffer, u16_t len, void* eb);
-
-wifi_interface_t wifi_get_interface(void *dev);
-
-void netif_reg_addr_change_cb(void* cb);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*  _WLAN_LWIP_IF_H_ */
diff --git a/tools/sdk/include/lwip/netinet/in.h b/tools/sdk/include/lwip/netinet/in.h
deleted file mode 100644
index 7eaec63342f..00000000000
--- a/tools/sdk/include/lwip/netinet/in.h
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef IN_H_
-#define IN_H_
-
-#include "lwip/inet.h"
-
-#define IN6_IS_ADDR_MULTICAST(a)    IN_MULTICAST(a)
-
-#endif /* IN_H_ */
diff --git a/tools/sdk/include/lwip/perf.h b/tools/sdk/include/lwip/perf.h
deleted file mode 100644
index 089facac1df..00000000000
--- a/tools/sdk/include/lwip/perf.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2001, Swedish Institute of Computer Science.
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * This file is part of the lwIP TCP/IP stack.
- * 
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
-#ifndef __PERF_H__
-#define __PERF_H__
-
-#define PERF_START    /* null definition */
-#define PERF_STOP(x)  /* null definition */
-
-#endif /* __PERF_H__ */
diff --git a/tools/sdk/include/lwip/ping/ping.h b/tools/sdk/include/lwip/ping/ping.h
deleted file mode 100644
index 6e8eb24b2ad..00000000000
--- a/tools/sdk/include/lwip/ping/ping.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#ifndef LWIP_PING_H
-#define LWIP_PING_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * PING_USE_SOCKETS: Set to 1 to use sockets, otherwise the raw api is used
- */
-#ifndef PING_USE_SOCKETS
-#define PING_USE_SOCKETS    LWIP_SOCKET
-#endif
-
-
-int ping_init(void);
-
-#ifdef ESP_PING
-void ping_deinit(void);
-#endif
-
-#if !PING_USE_SOCKETS
-void ping_send_now(void);
-#endif /* !PING_USE_SOCKETS */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_PING_H */
diff --git a/tools/sdk/include/lwip/posix/errno.h b/tools/sdk/include/lwip/posix/errno.h
deleted file mode 100644
index 5917c75e24a..00000000000
--- a/tools/sdk/include/lwip/posix/errno.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/**
- * @file
- * This file is a posix wrapper for lwip/errno.h.
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#include "lwip/errno.h"
diff --git a/tools/sdk/include/lwip/posix/netdb.h b/tools/sdk/include/lwip/posix/netdb.h
deleted file mode 100644
index 363154f6889..00000000000
--- a/tools/sdk/include/lwip/posix/netdb.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/**
- * @file
- * This file is a posix wrapper for lwip/netdb.h.
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#include "lwip/netdb.h"
-
-#ifdef ESP_PLATFORM
-int getnameinfo(const struct sockaddr *addr, socklen_t addrlen,
-                char *host, socklen_t hostlen,
-                char *serv, socklen_t servlen, int flags);
-
-#endif
diff --git a/tools/sdk/include/lwip/posix/sys/socket.h b/tools/sdk/include/lwip/posix/sys/socket.h
deleted file mode 100644
index 0ed9baf3d9f..00000000000
--- a/tools/sdk/include/lwip/posix/sys/socket.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/**
- * @file
- * This file is a posix wrapper for lwip/sockets.h.
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#include "lwip/sockets.h"
diff --git a/tools/sdk/include/lwip/sntp.h b/tools/sdk/include/lwip/sntp.h
deleted file mode 100644
index a94981b5d9c..00000000000
--- a/tools/sdk/include/lwip/sntp.h
+++ /dev/null
@@ -1,127 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __SNTP_H__
-#define __SNTP_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * The time update takes place in the sntp_sync_time() function.
- * The user has the ability to redefine this function in order
- * to re-define its functionality. This function has two time update modes,
- * which can be set via the sntp_set_sync_mode() function.
- * Two modes are available:
- * - the first is an immediate update when receiving time from the sntp server,
- * - the second is a smooth time update (if the time error is no more than 35 minutes,
- *   and an immediate update if the error is more than 35 minutes).
- *
- * To receive notification of time synchronization,
- * you can use the callback function or get the synchronization status
- * via the sntp_get_sync_status() function.
- *
- * To determine the time synchronization time on the device, you can use:
- * 1) sntp_set_time_sync_notification_cb() function to set the callback function,
- *    which is convenient to use to receive notification of the update time.
- * 2) sntp_get_sync_status() function for getting time synchronization status.
- *    After the time synchronization is completed, the status will be
- *    SNTP_SYNC_STATUS_COMPLETED, after, it will be reseted to SNTP_SYNC_STATUS_RESET
- *    to wait for the next sync cycle.
- */
-
-/// SNTP time update mode
-typedef enum {
-    SNTP_SYNC_MODE_IMMED,   /*!< Update system time immediately when receiving a response from the SNTP server. */
-    SNTP_SYNC_MODE_SMOOTH,  /*!< Smooth time updating. Time error is gradually reduced using adjtime function. If the difference between SNTP response time and system time is large (more than 35 minutes) then update immediately. */
-} sntp_sync_mode_t;
-
-/// SNTP sync status
-typedef enum {
-    SNTP_SYNC_STATUS_RESET,         // Reset status.
-    SNTP_SYNC_STATUS_COMPLETED,     // Time is synchronized.
-    SNTP_SYNC_STATUS_IN_PROGRESS,   // Smooth time sync in progress.
-} sntp_sync_status_t;
-
-/**
- * @brief SNTP callback function for notifying about time sync event
- *
- * @param tv Time received from SNTP server.
- */
-typedef void (*sntp_sync_time_cb_t) (struct timeval *tv);
-
-/**
- * @brief This function updates the system time.
- *
- * This is a weak-linked function. It is possible to replace all SNTP update functionality
- * by placing a sntp_sync_time() function in the app firmware source.
- * If the default implementation is used, calling sntp_set_sync_mode() allows
- * the time synchronization mode to be changed to instant or smooth.
- * If a callback function is registered via sntp_set_time_sync_notification_cb(),
- * it will be called following time synchronization.
- *
- * @param tv Time received from SNTP server.
- */
-void sntp_sync_time(struct timeval *tv);
-
-/**
- * @brief Set the sync mode
- *
- * Allowable two mode: SNTP_SYNC_MODE_IMMED and SNTP_SYNC_MODE_SMOOTH.
- * @param sync_mode Sync mode.
- */
-void sntp_set_sync_mode(sntp_sync_mode_t sync_mode);
-
-/**
- * @brief Get set sync mode
- *
- * @return  SNTP_SYNC_MODE_IMMED: Update time immediately.
- *          SNTP_SYNC_MODE_SMOOTH: Smooth time updating.
- */
-sntp_sync_mode_t sntp_get_sync_mode(void);
-
-/**
- * @brief Get status of time sync
- *
- * After the update is completed, the status will be returned as SNTP_SYNC_STATUS_COMPLETED.
- * After that, the status will be reset to SNTP_SYNC_STATUS_RESET.
- * If the update operation is not completed yet, the status will be SNTP_SYNC_STATUS_RESET.
- * If a smooth mode was chosen and the synchronization is still continuing (adjtime works), then it will be SNTP_SYNC_STATUS_IN_PROGRESS.
- *
- * @return  SNTP_SYNC_STATUS_RESET: Reset status.
- *          SNTP_SYNC_STATUS_COMPLETED: Time is synchronized.
- *          SNTP_SYNC_STATUS_IN_PROGRESS: Smooth time sync in progress.
- */
-sntp_sync_status_t sntp_get_sync_status(void);
-
-/**
- * @brief Set status of time sync
- *
- * @param sync_status status of time sync (see sntp_sync_status_t)
- */
-void sntp_set_sync_status(sntp_sync_status_t sync_status);
-
-/**
- * @brief Set a callback function for time synchronization notification
- *
- * @param callback a callback function
- */
-void sntp_set_time_sync_notification_cb(sntp_sync_time_cb_t callback);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __SNTP_H__
diff --git a/tools/sdk/include/lwip/sntp/sntp.h b/tools/sdk/include/lwip/sntp/sntp.h
deleted file mode 100644
index a94981b5d9c..00000000000
--- a/tools/sdk/include/lwip/sntp/sntp.h
+++ /dev/null
@@ -1,127 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __SNTP_H__
-#define __SNTP_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * The time update takes place in the sntp_sync_time() function.
- * The user has the ability to redefine this function in order
- * to re-define its functionality. This function has two time update modes,
- * which can be set via the sntp_set_sync_mode() function.
- * Two modes are available:
- * - the first is an immediate update when receiving time from the sntp server,
- * - the second is a smooth time update (if the time error is no more than 35 minutes,
- *   and an immediate update if the error is more than 35 minutes).
- *
- * To receive notification of time synchronization,
- * you can use the callback function or get the synchronization status
- * via the sntp_get_sync_status() function.
- *
- * To determine the time synchronization time on the device, you can use:
- * 1) sntp_set_time_sync_notification_cb() function to set the callback function,
- *    which is convenient to use to receive notification of the update time.
- * 2) sntp_get_sync_status() function for getting time synchronization status.
- *    After the time synchronization is completed, the status will be
- *    SNTP_SYNC_STATUS_COMPLETED, after, it will be reseted to SNTP_SYNC_STATUS_RESET
- *    to wait for the next sync cycle.
- */
-
-/// SNTP time update mode
-typedef enum {
-    SNTP_SYNC_MODE_IMMED,   /*!< Update system time immediately when receiving a response from the SNTP server. */
-    SNTP_SYNC_MODE_SMOOTH,  /*!< Smooth time updating. Time error is gradually reduced using adjtime function. If the difference between SNTP response time and system time is large (more than 35 minutes) then update immediately. */
-} sntp_sync_mode_t;
-
-/// SNTP sync status
-typedef enum {
-    SNTP_SYNC_STATUS_RESET,         // Reset status.
-    SNTP_SYNC_STATUS_COMPLETED,     // Time is synchronized.
-    SNTP_SYNC_STATUS_IN_PROGRESS,   // Smooth time sync in progress.
-} sntp_sync_status_t;
-
-/**
- * @brief SNTP callback function for notifying about time sync event
- *
- * @param tv Time received from SNTP server.
- */
-typedef void (*sntp_sync_time_cb_t) (struct timeval *tv);
-
-/**
- * @brief This function updates the system time.
- *
- * This is a weak-linked function. It is possible to replace all SNTP update functionality
- * by placing a sntp_sync_time() function in the app firmware source.
- * If the default implementation is used, calling sntp_set_sync_mode() allows
- * the time synchronization mode to be changed to instant or smooth.
- * If a callback function is registered via sntp_set_time_sync_notification_cb(),
- * it will be called following time synchronization.
- *
- * @param tv Time received from SNTP server.
- */
-void sntp_sync_time(struct timeval *tv);
-
-/**
- * @brief Set the sync mode
- *
- * Allowable two mode: SNTP_SYNC_MODE_IMMED and SNTP_SYNC_MODE_SMOOTH.
- * @param sync_mode Sync mode.
- */
-void sntp_set_sync_mode(sntp_sync_mode_t sync_mode);
-
-/**
- * @brief Get set sync mode
- *
- * @return  SNTP_SYNC_MODE_IMMED: Update time immediately.
- *          SNTP_SYNC_MODE_SMOOTH: Smooth time updating.
- */
-sntp_sync_mode_t sntp_get_sync_mode(void);
-
-/**
- * @brief Get status of time sync
- *
- * After the update is completed, the status will be returned as SNTP_SYNC_STATUS_COMPLETED.
- * After that, the status will be reset to SNTP_SYNC_STATUS_RESET.
- * If the update operation is not completed yet, the status will be SNTP_SYNC_STATUS_RESET.
- * If a smooth mode was chosen and the synchronization is still continuing (adjtime works), then it will be SNTP_SYNC_STATUS_IN_PROGRESS.
- *
- * @return  SNTP_SYNC_STATUS_RESET: Reset status.
- *          SNTP_SYNC_STATUS_COMPLETED: Time is synchronized.
- *          SNTP_SYNC_STATUS_IN_PROGRESS: Smooth time sync in progress.
- */
-sntp_sync_status_t sntp_get_sync_status(void);
-
-/**
- * @brief Set status of time sync
- *
- * @param sync_status status of time sync (see sntp_sync_status_t)
- */
-void sntp_set_sync_status(sntp_sync_status_t sync_status);
-
-/**
- * @brief Set a callback function for time synchronization notification
- *
- * @param callback a callback function
- */
-void sntp_set_time_sync_notification_cb(sntp_sync_time_cb_t callback);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __SNTP_H__
diff --git a/tools/sdk/include/lwip/sys/socket.h b/tools/sdk/include/lwip/sys/socket.h
deleted file mode 100644
index 0ed9baf3d9f..00000000000
--- a/tools/sdk/include/lwip/sys/socket.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/**
- * @file
- * This file is a posix wrapper for lwip/sockets.h.
- */
-
-/*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- */
-
-#include "lwip/sockets.h"
diff --git a/tools/sdk/include/lwip/sys_arch.h b/tools/sdk/include/lwip/sys_arch.h
deleted file mode 100644
index 9638fdfd621..00000000000
--- a/tools/sdk/include/lwip/sys_arch.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels <adam@sics.se>
- *
- */
- 
-#ifndef __SYS_ARCH_H__
-#define __SYS_ARCH_H__
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/queue.h"
-#include "freertos/semphr.h"
-#include "arch/vfs_lwip.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-typedef xSemaphoreHandle sys_sem_t;
-typedef xSemaphoreHandle sys_mutex_t;
-typedef xTaskHandle sys_thread_t;
-
-typedef struct sys_mbox_s {
-  xQueueHandle os_mbox;
-  void *owner;
-}* sys_mbox_t;
-
-
-#define LWIP_COMPAT_MUTEX 0
-
-#if !LWIP_COMPAT_MUTEX
-#define sys_mutex_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
-#define sys_mutex_set_invalid( x ) ( ( *x ) = NULL )
-#endif
-
-#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
-
-/* Define the sys_mbox_set_invalid() to empty to support lock-free mbox in ESP LWIP.
- * 
- * The basic idea about the lock-free mbox is that the mbox should always be valid unless
- * no socket APIs are using the socket and the socket is closed. ESP LWIP achieves this by
- * following two changes to official LWIP:
- * 1. Postpone the deallocation of mbox to netconn_free(), in other words, free the mbox when
- *    no one is using the socket.
- * 2. Define the sys_mbox_set_invalid() to empty if the mbox is not actually freed.
-
- * The second change is necessary. Consider a common scenario: the application task calls 
- * recv() to receive packets from the socket, the sys_mbox_valid() returns true. Because there
- * is no lock for the mbox, the LWIP CORE can call sys_mbox_set_invalid() to set the mbox at 
- * anytime and the thread-safe issue may happen.
- *
- * However, if the sys_mbox_set_invalid() is not called after sys_mbox_free(), e.g. in netconn_alloc(),
- * we need to initialize the mbox to invalid explicitly since sys_mbox_set_invalid() now is empty.
- */
-#define sys_mbox_set_invalid( x ) 
-
-#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE )
-#define sys_sem_set_invalid( x ) ( ( *x ) = NULL )
-
-void sys_delay_ms(uint32_t ms);
-sys_sem_t* sys_thread_sem_init(void);
-void sys_thread_sem_deinit(void);
-sys_sem_t* sys_thread_sem_get(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYS_ARCH_H__ */
-
diff --git a/tools/sdk/include/lwip/tcp_isn.h b/tools/sdk/include/lwip/tcp_isn.h
deleted file mode 100644
index a40c4a1ad64..00000000000
--- a/tools/sdk/include/lwip/tcp_isn.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2016 The MINIX 3 Project.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * Author: David van Moolenbroek <david@minix3.org>
- */
-
-#ifndef LWIP_TCP_ISN_H
-#define LWIP_TCP_ISN_H
-
-#include "lwip/opt.h"
-#include "lwip/ip_addr.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void lwip_init_tcp_isn(u32_t boot_time, const u8_t *secret_16_bytes);
-u32_t lwip_hook_tcp_isn(const ip_addr_t *local_ip, u16_t local_port,
-                        const ip_addr_t *remote_ip, u16_t remote_port);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LWIP_TCP_ISN_H */
diff --git a/tools/sdk/include/lwip/vfs_lwip.h b/tools/sdk/include/lwip/vfs_lwip.h
deleted file mode 100644
index 1957304b9f2..00000000000
--- a/tools/sdk/include/lwip/vfs_lwip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void esp_vfs_lwip_sockets_register();
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/mbedtls/aes_alt.h b/tools/sdk/include/mbedtls/aes_alt.h
deleted file mode 100644
index cf87ea5c152..00000000000
--- a/tools/sdk/include/mbedtls/aes_alt.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/**
- * \file aes_alt.h
- *
- * \brief AES block cipher
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *
- */
-#ifndef AES_ALT_H
-#define AES_ALT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(MBEDTLS_AES_ALT)
-#include "hwcrypto/aes.h"
-
-typedef esp_aes_context mbedtls_aes_context;
-
-#define mbedtls_aes_init            esp_aes_init
-#define mbedtls_aes_free            esp_aes_free
-#define mbedtls_aes_setkey_enc      esp_aes_setkey
-#define mbedtls_aes_setkey_dec      esp_aes_setkey
-#define mbedtls_aes_crypt_ecb       esp_aes_crypt_ecb
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-#define mbedtls_aes_crypt_cbc       esp_aes_crypt_cbc
-#endif
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-#define mbedtls_aes_crypt_cfb128    esp_aes_crypt_cfb128
-#define mbedtls_aes_crypt_cfb8      esp_aes_crypt_cfb8
-#endif
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-#define mbedtls_aes_crypt_ctr       esp_aes_crypt_ctr
-#endif
-#if defined(MBEDTLS_CIPHER_MODE_XTS)
-typedef esp_aes_xts_context mbedtls_aes_xts_context;
-#define mbedtls_aes_xts_init            esp_aes_xts_init
-#define mbedtls_aes_xts_free            esp_aes_xts_free
-#define mbedtls_aes_xts_setkey_enc      esp_aes_xts_setkey_enc
-#define mbedtls_aes_xts_setkey_dec      esp_aes_xts_setkey_dec
-#define mbedtls_aes_crypt_xts       esp_aes_crypt_xts
-#endif
-#define mbedtls_internal_aes_encrypt         esp_internal_aes_encrypt
-#define mbedtls_internal_aes_decrypt         esp_internal_aes_decrypt
-#endif /* MBEDTLS_AES_ALT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/mbedtls/esp_mem.h b/tools/sdk/include/mbedtls/esp_mem.h
deleted file mode 100644
index da740830478..00000000000
--- a/tools/sdk/include/mbedtls/esp_mem.h
+++ /dev/null
@@ -1,20 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <stdlib.h>
-
-void *esp_mbedtls_mem_calloc(size_t n, size_t size);
-void esp_mbedtls_mem_free(void *ptr);
diff --git a/tools/sdk/include/mbedtls/mbedtls/aes.h b/tools/sdk/include/mbedtls/mbedtls/aes.h
deleted file mode 100644
index d20cdbd6da8..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/aes.h
+++ /dev/null
@@ -1,702 +0,0 @@
-/**
- * \file aes.h
- *
- * \brief   This file contains AES definitions and functions.
- *
- *          The Advanced Encryption Standard (AES) specifies a FIPS-approved
- *          cryptographic algorithm that can be used to protect electronic
- *          data.
- *
- *          The AES algorithm is a symmetric block cipher that can
- *          encrypt and decrypt information. For more information, see
- *          <em>FIPS Publication 197: Advanced Encryption Standard</em> and
- *          <em>ISO/IEC 18033-2:2006: Information technology -- Security
- *          techniques -- Encryption algorithms -- Part 2: Asymmetric
- *          ciphers</em>.
- *
- *          The AES-XTS block mode is standardized by NIST SP 800-38E
- *          <https://nvlpubs.nist.gov/nistpubs/legacy/sp/nistspecialpublication800-38e.pdf>
- *          and described in detail by IEEE P1619
- *          <https://ieeexplore.ieee.org/servlet/opac?punumber=4375278>.
- */
-
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved.
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_AES_H
-#define MBEDTLS_AES_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* padlock.c and aesni.c rely on these values! */
-#define MBEDTLS_AES_ENCRYPT     1 /**< AES encryption. */
-#define MBEDTLS_AES_DECRYPT     0 /**< AES decryption. */
-
-/* Error codes in range 0x0020-0x0022 */
-#define MBEDTLS_ERR_AES_INVALID_KEY_LENGTH                -0x0020  /**< Invalid key length. */
-#define MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH              -0x0022  /**< Invalid data input length. */
-
-/* Error codes in range 0x0021-0x0025 */
-#define MBEDTLS_ERR_AES_BAD_INPUT_DATA                    -0x0021  /**< Invalid input data. */
-
-/* MBEDTLS_ERR_AES_FEATURE_UNAVAILABLE is deprecated and should not be used. */
-#define MBEDTLS_ERR_AES_FEATURE_UNAVAILABLE               -0x0023  /**< Feature not available. For example, an unsupported AES key size. */
-
-/* MBEDTLS_ERR_AES_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_AES_HW_ACCEL_FAILED                   -0x0025  /**< AES hardware accelerator failed. */
-
-#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
-    !defined(inline) && !defined(__cplusplus)
-#define inline __inline
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_AES_ALT)
-// Regular implementation
-//
-
-/**
- * \brief The AES context-type definition.
- */
-typedef struct mbedtls_aes_context
-{
-    int nr;                     /*!< The number of rounds. */
-    uint32_t *rk;               /*!< AES round keys. */
-    uint32_t buf[68];           /*!< Unaligned data buffer. This buffer can
-                                     hold 32 extra Bytes, which can be used for
-                                     one of the following purposes:
-                                     <ul><li>Alignment if VIA padlock is
-                                             used.</li>
-                                     <li>Simplifying key expansion in the 256-bit
-                                         case by generating an extra round key.
-                                         </li></ul> */
-}
-mbedtls_aes_context;
-
-#if defined(MBEDTLS_CIPHER_MODE_XTS)
-/**
- * \brief The AES XTS context-type definition.
- */
-typedef struct mbedtls_aes_xts_context
-{
-    mbedtls_aes_context crypt; /*!< The AES context to use for AES block
-                                        encryption or decryption. */
-    mbedtls_aes_context tweak; /*!< The AES context used for tweak
-                                        computation. */
-} mbedtls_aes_xts_context;
-#endif /* MBEDTLS_CIPHER_MODE_XTS */
-
-#else  /* MBEDTLS_AES_ALT */
-#include "aes_alt.h"
-#endif /* MBEDTLS_AES_ALT */
-
-/**
- * \brief          This function initializes the specified AES context.
- *
- *                 It must be the first API called before using
- *                 the context.
- *
- * \param ctx      The AES context to initialize. This must not be \c NULL.
- */
-void mbedtls_aes_init( mbedtls_aes_context *ctx );
-
-/**
- * \brief          This function releases and clears the specified AES context.
- *
- * \param ctx      The AES context to clear.
- *                 If this is \c NULL, this function does nothing.
- *                 Otherwise, the context must have been at least initialized.
- */
-void mbedtls_aes_free( mbedtls_aes_context *ctx );
-
-#if defined(MBEDTLS_CIPHER_MODE_XTS)
-/**
- * \brief          This function initializes the specified AES XTS context.
- *
- *                 It must be the first API called before using
- *                 the context.
- *
- * \param ctx      The AES XTS context to initialize. This must not be \c NULL.
- */
-void mbedtls_aes_xts_init( mbedtls_aes_xts_context *ctx );
-
-/**
- * \brief          This function releases and clears the specified AES XTS context.
- *
- * \param ctx      The AES XTS context to clear.
- *                 If this is \c NULL, this function does nothing.
- *                 Otherwise, the context must have been at least initialized.
- */
-void mbedtls_aes_xts_free( mbedtls_aes_xts_context *ctx );
-#endif /* MBEDTLS_CIPHER_MODE_XTS */
-
-/**
- * \brief          This function sets the encryption key.
- *
- * \param ctx      The AES context to which the key should be bound.
- *                 It must be initialized.
- * \param key      The encryption key.
- *                 This must be a readable buffer of size \p keybits bits.
- * \param keybits  The size of data passed in bits. Valid options are:
- *                 <ul><li>128 bits</li>
- *                 <li>192 bits</li>
- *                 <li>256 bits</li></ul>
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
- */
-int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
-                    unsigned int keybits );
-
-/**
- * \brief          This function sets the decryption key.
- *
- * \param ctx      The AES context to which the key should be bound.
- *                 It must be initialized.
- * \param key      The decryption key.
- *                 This must be a readable buffer of size \p keybits bits.
- * \param keybits  The size of data passed. Valid options are:
- *                 <ul><li>128 bits</li>
- *                 <li>192 bits</li>
- *                 <li>256 bits</li></ul>
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
- */
-int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
-                    unsigned int keybits );
-
-#if defined(MBEDTLS_CIPHER_MODE_XTS)
-/**
- * \brief          This function prepares an XTS context for encryption and
- *                 sets the encryption key.
- *
- * \param ctx      The AES XTS context to which the key should be bound.
- *                 It must be initialized.
- * \param key      The encryption key. This is comprised of the XTS key1
- *                 concatenated with the XTS key2.
- *                 This must be a readable buffer of size \p keybits bits.
- * \param keybits  The size of \p key passed in bits. Valid options are:
- *                 <ul><li>256 bits (each of key1 and key2 is a 128-bit key)</li>
- *                 <li>512 bits (each of key1 and key2 is a 256-bit key)</li></ul>
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
- */
-int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx,
-                                const unsigned char *key,
-                                unsigned int keybits );
-
-/**
- * \brief          This function prepares an XTS context for decryption and
- *                 sets the decryption key.
- *
- * \param ctx      The AES XTS context to which the key should be bound.
- *                 It must be initialized.
- * \param key      The decryption key. This is comprised of the XTS key1
- *                 concatenated with the XTS key2.
- *                 This must be a readable buffer of size \p keybits bits.
- * \param keybits  The size of \p key passed in bits. Valid options are:
- *                 <ul><li>256 bits (each of key1 and key2 is a 128-bit key)</li>
- *                 <li>512 bits (each of key1 and key2 is a 256-bit key)</li></ul>
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure.
- */
-int mbedtls_aes_xts_setkey_dec( mbedtls_aes_xts_context *ctx,
-                                const unsigned char *key,
-                                unsigned int keybits );
-#endif /* MBEDTLS_CIPHER_MODE_XTS */
-
-/**
- * \brief          This function performs an AES single-block encryption or
- *                 decryption operation.
- *
- *                 It performs the operation defined in the \p mode parameter
- *                 (encrypt or decrypt), on the input data buffer defined in
- *                 the \p input parameter.
- *
- *                 mbedtls_aes_init(), and either mbedtls_aes_setkey_enc() or
- *                 mbedtls_aes_setkey_dec() must be called before the first
- *                 call to this API with the same context.
- *
- * \param ctx      The AES context to use for encryption or decryption.
- *                 It must be initialized and bound to a key.
- * \param mode     The AES operation: #MBEDTLS_AES_ENCRYPT or
- *                 #MBEDTLS_AES_DECRYPT.
- * \param input    The buffer holding the input data.
- *                 It must be readable and at least \c 16 Bytes long.
- * \param output   The buffer where the output data will be written.
- *                 It must be writeable and at least \c 16 Bytes long.
-
- * \return         \c 0 on success.
- */
-int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
-                    int mode,
-                    const unsigned char input[16],
-                    unsigned char output[16] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief  This function performs an AES-CBC encryption or decryption operation
- *         on full blocks.
- *
- *         It performs the operation defined in the \p mode
- *         parameter (encrypt/decrypt), on the input data buffer defined in
- *         the \p input parameter.
- *
- *         It can be called as many times as needed, until all the input
- *         data is processed. mbedtls_aes_init(), and either
- *         mbedtls_aes_setkey_enc() or mbedtls_aes_setkey_dec() must be called
- *         before the first call to this API with the same context.
- *
- * \note   This function operates on full blocks, that is, the input size
- *         must be a multiple of the AES block size of \c 16 Bytes.
- *
- * \note   Upon exit, the content of the IV is updated so that you can
- *         call the same function again on the next
- *         block(s) of data and get the same result as if it was
- *         encrypted in one call. This allows a "streaming" usage.
- *         If you need to retain the contents of the IV, you should
- *         either save it manually or use the cipher module instead.
- *
- *
- * \param ctx      The AES context to use for encryption or decryption.
- *                 It must be initialized and bound to a key.
- * \param mode     The AES operation: #MBEDTLS_AES_ENCRYPT or
- *                 #MBEDTLS_AES_DECRYPT.
- * \param length   The length of the input data in Bytes. This must be a
- *                 multiple of the block size (\c 16 Bytes).
- * \param iv       Initialization vector (updated after use).
- *                 It must be a readable and writeable buffer of \c 16 Bytes.
- * \param input    The buffer holding the input data.
- *                 It must be readable and of size \p length Bytes.
- * \param output   The buffer holding the output data.
- *                 It must be writeable and of size \p length Bytes.
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
- *                 on failure.
- */
-int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[16],
-                    const unsigned char *input,
-                    unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#if defined(MBEDTLS_CIPHER_MODE_XTS)
-/**
- * \brief      This function performs an AES-XTS encryption or decryption
- *             operation for an entire XTS data unit.
- *
- *             AES-XTS encrypts or decrypts blocks based on their location as
- *             defined by a data unit number. The data unit number must be
- *             provided by \p data_unit.
- *
- *             NIST SP 800-38E limits the maximum size of a data unit to 2^20
- *             AES blocks. If the data unit is larger than this, this function
- *             returns #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH.
- *
- * \param ctx          The AES XTS context to use for AES XTS operations.
- *                     It must be initialized and bound to a key.
- * \param mode         The AES operation: #MBEDTLS_AES_ENCRYPT or
- *                     #MBEDTLS_AES_DECRYPT.
- * \param length       The length of a data unit in Bytes. This can be any
- *                     length between 16 bytes and 2^24 bytes inclusive
- *                     (between 1 and 2^20 block cipher blocks).
- * \param data_unit    The address of the data unit encoded as an array of 16
- *                     bytes in little-endian format. For disk encryption, this
- *                     is typically the index of the block device sector that
- *                     contains the data.
- * \param input        The buffer holding the input data (which is an entire
- *                     data unit). This function reads \p length Bytes from \p
- *                     input.
- * \param output       The buffer holding the output data (which is an entire
- *                     data unit). This function writes \p length Bytes to \p
- *                     output.
- *
- * \return             \c 0 on success.
- * \return             #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH if \p length is
- *                     smaller than an AES block in size (16 Bytes) or if \p
- *                     length is larger than 2^20 blocks (16 MiB).
- */
-int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx,
-                           int mode,
-                           size_t length,
-                           const unsigned char data_unit[16],
-                           const unsigned char *input,
-                           unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_XTS */
-
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-/**
- * \brief This function performs an AES-CFB128 encryption or decryption
- *        operation.
- *
- *        It performs the operation defined in the \p mode
- *        parameter (encrypt or decrypt), on the input data buffer
- *        defined in the \p input parameter.
- *
- *        For CFB, you must set up the context with mbedtls_aes_setkey_enc(),
- *        regardless of whether you are performing an encryption or decryption
- *        operation, that is, regardless of the \p mode parameter. This is
- *        because CFB mode uses the same key schedule for encryption and
- *        decryption.
- *
- * \note  Upon exit, the content of the IV is updated so that you can
- *        call the same function again on the next
- *        block(s) of data and get the same result as if it was
- *        encrypted in one call. This allows a "streaming" usage.
- *        If you need to retain the contents of the
- *        IV, you must either save it manually or use the cipher
- *        module instead.
- *
- *
- * \param ctx      The AES context to use for encryption or decryption.
- *                 It must be initialized and bound to a key.
- * \param mode     The AES operation: #MBEDTLS_AES_ENCRYPT or
- *                 #MBEDTLS_AES_DECRYPT.
- * \param length   The length of the input data in Bytes.
- * \param iv_off   The offset in IV (updated after use).
- *                 It must point to a valid \c size_t.
- * \param iv       The initialization vector (updated after use).
- *                 It must be a readable and writeable buffer of \c 16 Bytes.
- * \param input    The buffer holding the input data.
- *                 It must be readable and of size \p length Bytes.
- * \param output   The buffer holding the output data.
- *                 It must be writeable and of size \p length Bytes.
- *
- * \return         \c 0 on success.
- */
-int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
-                       int mode,
-                       size_t length,
-                       size_t *iv_off,
-                       unsigned char iv[16],
-                       const unsigned char *input,
-                       unsigned char *output );
-
-/**
- * \brief This function performs an AES-CFB8 encryption or decryption
- *        operation.
- *
- *        It performs the operation defined in the \p mode
- *        parameter (encrypt/decrypt), on the input data buffer defined
- *        in the \p input parameter.
- *
- *        Due to the nature of CFB, you must use the same key schedule for
- *        both encryption and decryption operations. Therefore, you must
- *        use the context initialized with mbedtls_aes_setkey_enc() for
- *        both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT.
- *
- * \note  Upon exit, the content of the IV is updated so that you can
- *        call the same function again on the next
- *        block(s) of data and get the same result as if it was
- *        encrypted in one call. This allows a "streaming" usage.
- *        If you need to retain the contents of the
- *        IV, you should either save it manually or use the cipher
- *        module instead.
- *
- *
- * \param ctx      The AES context to use for encryption or decryption.
- *                 It must be initialized and bound to a key.
- * \param mode     The AES operation: #MBEDTLS_AES_ENCRYPT or
- *                 #MBEDTLS_AES_DECRYPT
- * \param length   The length of the input data.
- * \param iv       The initialization vector (updated after use).
- *                 It must be a readable and writeable buffer of \c 16 Bytes.
- * \param input    The buffer holding the input data.
- *                 It must be readable and of size \p length Bytes.
- * \param output   The buffer holding the output data.
- *                 It must be writeable and of size \p length Bytes.
- *
- * \return         \c 0 on success.
- */
-int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[16],
-                    const unsigned char *input,
-                    unsigned char *output );
-#endif /*MBEDTLS_CIPHER_MODE_CFB */
-
-#if defined(MBEDTLS_CIPHER_MODE_OFB)
-/**
- * \brief       This function performs an AES-OFB (Output Feedback Mode)
- *              encryption or decryption operation.
- *
- *              For OFB, you must set up the context with
- *              mbedtls_aes_setkey_enc(), regardless of whether you are
- *              performing an encryption or decryption operation. This is
- *              because OFB mode uses the same key schedule for encryption and
- *              decryption.
- *
- *              The OFB operation is identical for encryption or decryption,
- *              therefore no operation mode needs to be specified.
- *
- * \note        Upon exit, the content of iv, the Initialisation Vector, is
- *              updated so that you can call the same function again on the next
- *              block(s) of data and get the same result as if it was encrypted
- *              in one call. This allows a "streaming" usage, by initialising
- *              iv_off to 0 before the first call, and preserving its value
- *              between calls.
- *
- *              For non-streaming use, the iv should be initialised on each call
- *              to a unique value, and iv_off set to 0 on each call.
- *
- *              If you need to retain the contents of the initialisation vector,
- *              you must either save it manually or use the cipher module
- *              instead.
- *
- * \warning     For the OFB mode, the initialisation vector must be unique
- *              every encryption operation. Reuse of an initialisation vector
- *              will compromise security.
- *
- * \param ctx      The AES context to use for encryption or decryption.
- *                 It must be initialized and bound to a key.
- * \param length   The length of the input data.
- * \param iv_off   The offset in IV (updated after use).
- *                 It must point to a valid \c size_t.
- * \param iv       The initialization vector (updated after use).
- *                 It must be a readable and writeable buffer of \c 16 Bytes.
- * \param input    The buffer holding the input data.
- *                 It must be readable and of size \p length Bytes.
- * \param output   The buffer holding the output data.
- *                 It must be writeable and of size \p length Bytes.
- *
- * \return         \c 0 on success.
- */
-int mbedtls_aes_crypt_ofb( mbedtls_aes_context *ctx,
-                       size_t length,
-                       size_t *iv_off,
-                       unsigned char iv[16],
-                       const unsigned char *input,
-                       unsigned char *output );
-
-#endif /* MBEDTLS_CIPHER_MODE_OFB */
-
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-/**
- * \brief      This function performs an AES-CTR encryption or decryption
- *             operation.
- *
- *             This function performs the operation defined in the \p mode
- *             parameter (encrypt/decrypt), on the input data buffer
- *             defined in the \p input parameter.
- *
- *             Due to the nature of CTR, you must use the same key schedule
- *             for both encryption and decryption operations. Therefore, you
- *             must use the context initialized with mbedtls_aes_setkey_enc()
- *             for both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT.
- *
- * \warning    You must never reuse a nonce value with the same key. Doing so
- *             would void the encryption for the two messages encrypted with
- *             the same nonce and key.
- *
- *             There are two common strategies for managing nonces with CTR:
- *
- *             1. You can handle everything as a single message processed over
- *             successive calls to this function. In that case, you want to
- *             set \p nonce_counter and \p nc_off to 0 for the first call, and
- *             then preserve the values of \p nonce_counter, \p nc_off and \p
- *             stream_block across calls to this function as they will be
- *             updated by this function.
- *
- *             With this strategy, you must not encrypt more than 2**128
- *             blocks of data with the same key.
- *
- *             2. You can encrypt separate messages by dividing the \p
- *             nonce_counter buffer in two areas: the first one used for a
- *             per-message nonce, handled by yourself, and the second one
- *             updated by this function internally.
- *
- *             For example, you might reserve the first 12 bytes for the
- *             per-message nonce, and the last 4 bytes for internal use. In that
- *             case, before calling this function on a new message you need to
- *             set the first 12 bytes of \p nonce_counter to your chosen nonce
- *             value, the last 4 to 0, and \p nc_off to 0 (which will cause \p
- *             stream_block to be ignored). That way, you can encrypt at most
- *             2**96 messages of up to 2**32 blocks each with the same key.
- *
- *             The per-message nonce (or information sufficient to reconstruct
- *             it) needs to be communicated with the ciphertext and must be unique.
- *             The recommended way to ensure uniqueness is to use a message
- *             counter. An alternative is to generate random nonces, but this
- *             limits the number of messages that can be securely encrypted:
- *             for example, with 96-bit random nonces, you should not encrypt
- *             more than 2**32 messages with the same key.
- *
- *             Note that for both stategies, sizes are measured in blocks and
- *             that an AES block is 16 bytes.
- *
- * \warning    Upon return, \p stream_block contains sensitive data. Its
- *             content must not be written to insecure storage and should be
- *             securely discarded as soon as it's no longer needed.
- *
- * \param ctx              The AES context to use for encryption or decryption.
- *                         It must be initialized and bound to a key.
- * \param length           The length of the input data.
- * \param nc_off           The offset in the current \p stream_block, for
- *                         resuming within the current cipher stream. The
- *                         offset pointer should be 0 at the start of a stream.
- *                         It must point to a valid \c size_t.
- * \param nonce_counter    The 128-bit nonce and counter.
- *                         It must be a readable-writeable buffer of \c 16 Bytes.
- * \param stream_block     The saved stream block for resuming. This is
- *                         overwritten by the function.
- *                         It must be a readable-writeable buffer of \c 16 Bytes.
- * \param input            The buffer holding the input data.
- *                         It must be readable and of size \p length Bytes.
- * \param output           The buffer holding the output data.
- *                         It must be writeable and of size \p length Bytes.
- *
- * \return                 \c 0 on success.
- */
-int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
-                       size_t length,
-                       size_t *nc_off,
-                       unsigned char nonce_counter[16],
-                       unsigned char stream_block[16],
-                       const unsigned char *input,
-                       unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CTR */
-
-/**
- * \brief           Internal AES block encryption function. This is only
- *                  exposed to allow overriding it using
- *                  \c MBEDTLS_AES_ENCRYPT_ALT.
- *
- * \param ctx       The AES context to use for encryption.
- * \param input     The plaintext block.
- * \param output    The output (ciphertext) block.
- *
- * \return          \c 0 on success.
- */
-int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
-                                  const unsigned char input[16],
-                                  unsigned char output[16] );
-
-/**
- * \brief           Internal AES block decryption function. This is only
- *                  exposed to allow overriding it using see
- *                  \c MBEDTLS_AES_DECRYPT_ALT.
- *
- * \param ctx       The AES context to use for decryption.
- * \param input     The ciphertext block.
- * \param output    The output (plaintext) block.
- *
- * \return          \c 0 on success.
- */
-int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
-                                  const unsigned char input[16],
-                                  unsigned char output[16] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief           Deprecated internal AES block encryption function
- *                  without return value.
- *
- * \deprecated      Superseded by mbedtls_internal_aes_encrypt()
- *
- * \param ctx       The AES context to use for encryption.
- * \param input     Plaintext block.
- * \param output    Output (ciphertext) block.
- */
-MBEDTLS_DEPRECATED void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
-                                             const unsigned char input[16],
-                                             unsigned char output[16] );
-
-/**
- * \brief           Deprecated internal AES block decryption function
- *                  without return value.
- *
- * \deprecated      Superseded by mbedtls_internal_aes_decrypt()
- *
- * \param ctx       The AES context to use for decryption.
- * \param input     Ciphertext block.
- * \param output    Output (plaintext) block.
- */
-MBEDTLS_DEPRECATED void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
-                                             const unsigned char input[16],
-                                             unsigned char output[16] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief          Checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_aes_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* aes.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/aesni.h b/tools/sdk/include/mbedtls/mbedtls/aesni.h
deleted file mode 100644
index 91a4e0f1160..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/aesni.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/**
- * \file aesni.h
- *
- * \brief AES-NI for hardware AES acceleration on some Intel processors
- *
- * \warning These functions are only for internal use by other library
- *          functions; you must not call them directly.
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_AESNI_H
-#define MBEDTLS_AESNI_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "aes.h"
-
-#define MBEDTLS_AESNI_AES      0x02000000u
-#define MBEDTLS_AESNI_CLMUL    0x00000002u
-
-#if defined(MBEDTLS_HAVE_ASM) && defined(__GNUC__) &&  \
-    ( defined(__amd64__) || defined(__x86_64__) )   &&  \
-    ! defined(MBEDTLS_HAVE_X86_64)
-#define MBEDTLS_HAVE_X86_64
-#endif
-
-#if defined(MBEDTLS_HAVE_X86_64)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          Internal function to detect the AES-NI feature in CPUs.
- *
- * \note           This function is only for internal use by other library
- *                 functions; you must not call it directly.
- *
- * \param what     The feature to detect
- *                 (MBEDTLS_AESNI_AES or MBEDTLS_AESNI_CLMUL)
- *
- * \return         1 if CPU has support for the feature, 0 otherwise
- */
-int mbedtls_aesni_has_support( unsigned int what );
-
-/**
- * \brief          Internal AES-NI AES-ECB block encryption and decryption
- *
- * \note           This function is only for internal use by other library
- *                 functions; you must not call it directly.
- *
- * \param ctx      AES context
- * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param input    16-byte input block
- * \param output   16-byte output block
- *
- * \return         0 on success (cannot fail)
- */
-int mbedtls_aesni_crypt_ecb( mbedtls_aes_context *ctx,
-                             int mode,
-                             const unsigned char input[16],
-                             unsigned char output[16] );
-
-/**
- * \brief          Internal GCM multiplication: c = a * b in GF(2^128)
- *
- * \note           This function is only for internal use by other library
- *                 functions; you must not call it directly.
- *
- * \param c        Result
- * \param a        First operand
- * \param b        Second operand
- *
- * \note           Both operands and result are bit strings interpreted as
- *                 elements of GF(2^128) as per the GCM spec.
- */
-void mbedtls_aesni_gcm_mult( unsigned char c[16],
-                             const unsigned char a[16],
-                             const unsigned char b[16] );
-
-/**
- * \brief           Internal round key inversion. This function computes
- *                  decryption round keys from the encryption round keys.
- *
- * \note            This function is only for internal use by other library
- *                  functions; you must not call it directly.
- *
- * \param invkey    Round keys for the equivalent inverse cipher
- * \param fwdkey    Original round keys (for encryption)
- * \param nr        Number of rounds (that is, number of round keys minus one)
- */
-void mbedtls_aesni_inverse_key( unsigned char *invkey,
-                                const unsigned char *fwdkey,
-                                int nr );
-
-/**
- * \brief           Internal key expansion for encryption
- *
- * \note            This function is only for internal use by other library
- *                  functions; you must not call it directly.
- *
- * \param rk        Destination buffer where the round keys are written
- * \param key       Encryption key
- * \param bits      Key size in bits (must be 128, 192 or 256)
- *
- * \return          0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
- */
-int mbedtls_aesni_setkey_enc( unsigned char *rk,
-                              const unsigned char *key,
-                              size_t bits );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_HAVE_X86_64 */
-
-#endif /* MBEDTLS_AESNI_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/arc4.h b/tools/sdk/include/mbedtls/mbedtls/arc4.h
deleted file mode 100644
index ecaf3101221..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/arc4.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/**
- * \file arc4.h
- *
- * \brief The ARCFOUR stream cipher
- *
- * \warning   ARC4 is considered a weak cipher and its use constitutes a
- *            security risk. We recommend considering stronger ciphers instead.
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- *
- */
-#ifndef MBEDTLS_ARC4_H
-#define MBEDTLS_ARC4_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-/* MBEDTLS_ERR_ARC4_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_ARC4_HW_ACCEL_FAILED                  -0x0019  /**< ARC4 hardware accelerator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_ARC4_ALT)
-// Regular implementation
-//
-
-/**
- * \brief     ARC4 context structure
- *
- * \warning   ARC4 is considered a weak cipher and its use constitutes a
- *            security risk. We recommend considering stronger ciphers instead.
- *
- */
-typedef struct mbedtls_arc4_context
-{
-    int x;                      /*!< permutation index */
-    int y;                      /*!< permutation index */
-    unsigned char m[256];       /*!< permutation table */
-}
-mbedtls_arc4_context;
-
-#else  /* MBEDTLS_ARC4_ALT */
-#include "arc4_alt.h"
-#endif /* MBEDTLS_ARC4_ALT */
-
-/**
- * \brief          Initialize ARC4 context
- *
- * \param ctx      ARC4 context to be initialized
- *
- * \warning        ARC4 is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- *
- */
-void mbedtls_arc4_init( mbedtls_arc4_context *ctx );
-
-/**
- * \brief          Clear ARC4 context
- *
- * \param ctx      ARC4 context to be cleared
- *
- * \warning        ARC4 is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- *
- */
-void mbedtls_arc4_free( mbedtls_arc4_context *ctx );
-
-/**
- * \brief          ARC4 key schedule
- *
- * \param ctx      ARC4 context to be setup
- * \param key      the secret key
- * \param keylen   length of the key, in bytes
- *
- * \warning        ARC4 is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- *
- */
-void mbedtls_arc4_setup( mbedtls_arc4_context *ctx, const unsigned char *key,
-                 unsigned int keylen );
-
-/**
- * \brief          ARC4 cipher function
- *
- * \param ctx      ARC4 context
- * \param length   length of the input data
- * \param input    buffer holding the input data
- * \param output   buffer for the output data
- *
- * \return         0 if successful
- *
- * \warning        ARC4 is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- *
- */
-int mbedtls_arc4_crypt( mbedtls_arc4_context *ctx, size_t length, const unsigned char *input,
-                unsigned char *output );
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- *
- * \warning        ARC4 is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- *
- */
-int mbedtls_arc4_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* arc4.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/aria.h b/tools/sdk/include/mbedtls/mbedtls/aria.h
deleted file mode 100644
index 66f2668bf37..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/aria.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/**
- * \file aria.h
- *
- * \brief ARIA block cipher
- *
- *        The ARIA algorithm is a symmetric block cipher that can encrypt and
- *        decrypt information. It is defined by the Korean Agency for
- *        Technology and Standards (KATS) in <em>KS X 1213:2004</em> (in
- *        Korean, but see http://210.104.33.10/ARIA/index-e.html in English)
- *        and also described by the IETF in <em>RFC 5794</em>.
- */
-/*
- *  Copyright (C) 2006-2018, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_ARIA_H
-#define MBEDTLS_ARIA_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-#include "platform_util.h"
-
-#define MBEDTLS_ARIA_ENCRYPT     1 /**< ARIA encryption. */
-#define MBEDTLS_ARIA_DECRYPT     0 /**< ARIA decryption. */
-
-#define MBEDTLS_ARIA_BLOCKSIZE   16 /**< ARIA block size in bytes. */
-#define MBEDTLS_ARIA_MAX_ROUNDS  16 /**< Maxiumum number of rounds in ARIA. */
-#define MBEDTLS_ARIA_MAX_KEYSIZE 32 /**< Maximum size of an ARIA key in bytes. */
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#define MBEDTLS_ERR_ARIA_INVALID_KEY_LENGTH   MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( -0x005C )
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-#define MBEDTLS_ERR_ARIA_BAD_INPUT_DATA -0x005C /**< Bad input data. */
-
-#define MBEDTLS_ERR_ARIA_INVALID_INPUT_LENGTH -0x005E /**< Invalid data input length. */
-
-/* MBEDTLS_ERR_ARIA_FEATURE_UNAVAILABLE is deprecated and should not be used.
- */
-#define MBEDTLS_ERR_ARIA_FEATURE_UNAVAILABLE  -0x005A  /**< Feature not available. For example, an unsupported ARIA key size. */
-
-/* MBEDTLS_ERR_ARIA_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_ARIA_HW_ACCEL_FAILED      -0x0058  /**< ARIA hardware accelerator failed. */
-
-#if !defined(MBEDTLS_ARIA_ALT)
-// Regular implementation
-//
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief The ARIA context-type definition.
- */
-typedef struct mbedtls_aria_context
-{
-    unsigned char nr;           /*!< The number of rounds (12, 14 or 16) */
-    /*! The ARIA round keys. */
-    uint32_t rk[MBEDTLS_ARIA_MAX_ROUNDS + 1][MBEDTLS_ARIA_BLOCKSIZE / 4];
-}
-mbedtls_aria_context;
-
-#else  /* MBEDTLS_ARIA_ALT */
-#include "aria_alt.h"
-#endif /* MBEDTLS_ARIA_ALT */
-
-/**
- * \brief          This function initializes the specified ARIA context.
- *
- *                 It must be the first API called before using
- *                 the context.
- *
- * \param ctx      The ARIA context to initialize. This must not be \c NULL.
- */
-void mbedtls_aria_init( mbedtls_aria_context *ctx );
-
-/**
- * \brief          This function releases and clears the specified ARIA context.
- *
- * \param ctx      The ARIA context to clear. This may be \c NULL, in which
- *                 case this function returns immediately. If it is not \c NULL,
- *                 it must point to an initialized ARIA context.
- */
-void mbedtls_aria_free( mbedtls_aria_context *ctx );
-
-/**
- * \brief          This function sets the encryption key.
- *
- * \param ctx      The ARIA context to which the key should be bound.
- *                 This must be initialized.
- * \param key      The encryption key. This must be a readable buffer
- *                 of size \p keybits Bits.
- * \param keybits  The size of \p key in Bits. Valid options are:
- *                 <ul><li>128 bits</li>
- *                 <li>192 bits</li>
- *                 <li>256 bits</li></ul>
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_aria_setkey_enc( mbedtls_aria_context *ctx,
-                             const unsigned char *key,
-                             unsigned int keybits );
-
-/**
- * \brief          This function sets the decryption key.
- *
- * \param ctx      The ARIA context to which the key should be bound.
- *                 This must be initialized.
- * \param key      The decryption key. This must be a readable buffer
- *                 of size \p keybits Bits.
- * \param keybits  The size of data passed. Valid options are:
- *                 <ul><li>128 bits</li>
- *                 <li>192 bits</li>
- *                 <li>256 bits</li></ul>
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_aria_setkey_dec( mbedtls_aria_context *ctx,
-                             const unsigned char *key,
-                             unsigned int keybits );
-
-/**
- * \brief          This function performs an ARIA single-block encryption or
- *                 decryption operation.
- *
- *                 It performs encryption or decryption (depending on whether
- *                 the key was set for encryption on decryption) on the input
- *                 data buffer defined in the \p input parameter.
- *
- *                 mbedtls_aria_init(), and either mbedtls_aria_setkey_enc() or
- *                 mbedtls_aria_setkey_dec() must be called before the first
- *                 call to this API with the same context.
- *
- * \param ctx      The ARIA context to use for encryption or decryption.
- *                 This must be initialized and bound to a key.
- * \param input    The 16-Byte buffer holding the input data.
- * \param output   The 16-Byte buffer holding the output data.
-
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_aria_crypt_ecb( mbedtls_aria_context *ctx,
-                            const unsigned char input[MBEDTLS_ARIA_BLOCKSIZE],
-                            unsigned char output[MBEDTLS_ARIA_BLOCKSIZE] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief  This function performs an ARIA-CBC encryption or decryption operation
- *         on full blocks.
- *
- *         It performs the operation defined in the \p mode
- *         parameter (encrypt/decrypt), on the input data buffer defined in
- *         the \p input parameter.
- *
- *         It can be called as many times as needed, until all the input
- *         data is processed. mbedtls_aria_init(), and either
- *         mbedtls_aria_setkey_enc() or mbedtls_aria_setkey_dec() must be called
- *         before the first call to this API with the same context.
- *
- * \note   This function operates on aligned blocks, that is, the input size
- *         must be a multiple of the ARIA block size of 16 Bytes.
- *
- * \note   Upon exit, the content of the IV is updated so that you can
- *         call the same function again on the next
- *         block(s) of data and get the same result as if it was
- *         encrypted in one call. This allows a "streaming" usage.
- *         If you need to retain the contents of the IV, you should
- *         either save it manually or use the cipher module instead.
- *
- *
- * \param ctx      The ARIA context to use for encryption or decryption.
- *                 This must be initialized and bound to a key.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_ARIA_ENCRYPT for encryption, or
- *                 #MBEDTLS_ARIA_DECRYPT for decryption.
- * \param length   The length of the input data in Bytes. This must be a
- *                 multiple of the block size (16 Bytes).
- * \param iv       Initialization vector (updated after use).
- *                 This must be a readable buffer of size 16 Bytes.
- * \param input    The buffer holding the input data. This must
- *                 be a readable buffer of length \p length Bytes.
- * \param output   The buffer holding the output data. This must
- *                 be a writable buffer of length \p length Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_aria_crypt_cbc( mbedtls_aria_context *ctx,
-                            int mode,
-                            size_t length,
-                            unsigned char iv[MBEDTLS_ARIA_BLOCKSIZE],
-                            const unsigned char *input,
-                            unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-/**
- * \brief This function performs an ARIA-CFB128 encryption or decryption
- *        operation.
- *
- *        It performs the operation defined in the \p mode
- *        parameter (encrypt or decrypt), on the input data buffer
- *        defined in the \p input parameter.
- *
- *        For CFB, you must set up the context with mbedtls_aria_setkey_enc(),
- *        regardless of whether you are performing an encryption or decryption
- *        operation, that is, regardless of the \p mode parameter. This is
- *        because CFB mode uses the same key schedule for encryption and
- *        decryption.
- *
- * \note  Upon exit, the content of the IV is updated so that you can
- *        call the same function again on the next
- *        block(s) of data and get the same result as if it was
- *        encrypted in one call. This allows a "streaming" usage.
- *        If you need to retain the contents of the
- *        IV, you must either save it manually or use the cipher
- *        module instead.
- *
- *
- * \param ctx      The ARIA context to use for encryption or decryption.
- *                 This must be initialized and bound to a key.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_ARIA_ENCRYPT for encryption, or
- *                 #MBEDTLS_ARIA_DECRYPT for decryption.
- * \param length   The length of the input data \p input in Bytes.
- * \param iv_off   The offset in IV (updated after use).
- *                 This must not be larger than 15.
- * \param iv       The initialization vector (updated after use).
- *                 This must be a readable buffer of size 16 Bytes.
- * \param input    The buffer holding the input data. This must
- *                 be a readable buffer of length \p length Bytes.
- * \param output   The buffer holding the output data. This must
- *                 be a writable buffer of length \p length Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_aria_crypt_cfb128( mbedtls_aria_context *ctx,
-                               int mode,
-                               size_t length,
-                               size_t *iv_off,
-                               unsigned char iv[MBEDTLS_ARIA_BLOCKSIZE],
-                               const unsigned char *input,
-                               unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CFB */
-
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-/**
- * \brief      This function performs an ARIA-CTR encryption or decryption
- *             operation.
- *
- *             This function performs the operation defined in the \p mode
- *             parameter (encrypt/decrypt), on the input data buffer
- *             defined in the \p input parameter.
- *
- *             Due to the nature of CTR, you must use the same key schedule
- *             for both encryption and decryption operations. Therefore, you
- *             must use the context initialized with mbedtls_aria_setkey_enc()
- *             for both #MBEDTLS_ARIA_ENCRYPT and #MBEDTLS_ARIA_DECRYPT.
- *
- * \warning    You must never reuse a nonce value with the same key. Doing so
- *             would void the encryption for the two messages encrypted with
- *             the same nonce and key.
- *
- *             There are two common strategies for managing nonces with CTR:
- *
- *             1. You can handle everything as a single message processed over
- *             successive calls to this function. In that case, you want to
- *             set \p nonce_counter and \p nc_off to 0 for the first call, and
- *             then preserve the values of \p nonce_counter, \p nc_off and \p
- *             stream_block across calls to this function as they will be
- *             updated by this function.
- *
- *             With this strategy, you must not encrypt more than 2**128
- *             blocks of data with the same key.
- *
- *             2. You can encrypt separate messages by dividing the \p
- *             nonce_counter buffer in two areas: the first one used for a
- *             per-message nonce, handled by yourself, and the second one
- *             updated by this function internally.
- *
- *             For example, you might reserve the first 12 bytes for the
- *             per-message nonce, and the last 4 bytes for internal use. In that
- *             case, before calling this function on a new message you need to
- *             set the first 12 bytes of \p nonce_counter to your chosen nonce
- *             value, the last 4 to 0, and \p nc_off to 0 (which will cause \p
- *             stream_block to be ignored). That way, you can encrypt at most
- *             2**96 messages of up to 2**32 blocks each with the same key.
- *
- *             The per-message nonce (or information sufficient to reconstruct
- *             it) needs to be communicated with the ciphertext and must be unique.
- *             The recommended way to ensure uniqueness is to use a message
- *             counter. An alternative is to generate random nonces, but this
- *             limits the number of messages that can be securely encrypted:
- *             for example, with 96-bit random nonces, you should not encrypt
- *             more than 2**32 messages with the same key.
- *
- *             Note that for both stategies, sizes are measured in blocks and
- *             that an ARIA block is 16 bytes.
- *
- * \warning    Upon return, \p stream_block contains sensitive data. Its
- *             content must not be written to insecure storage and should be
- *             securely discarded as soon as it's no longer needed.
- *
- * \param ctx              The ARIA context to use for encryption or decryption.
- *                         This must be initialized and bound to a key.
- * \param length           The length of the input data \p input in Bytes.
- * \param nc_off           The offset in Bytes in the current \p stream_block,
- *                         for resuming within the current cipher stream. The
- *                         offset pointer should be \c 0 at the start of a
- *                         stream. This must not be larger than \c 15 Bytes.
- * \param nonce_counter    The 128-bit nonce and counter. This must point to
- *                         a read/write buffer of length \c 16 bytes.
- * \param stream_block     The saved stream block for resuming. This must
- *                         point to a read/write buffer of length \c 16 bytes.
- *                         This is overwritten by the function.
- * \param input            The buffer holding the input data. This must
- *                         be a readable buffer of length \p length Bytes.
- * \param output           The buffer holding the output data. This must
- *                         be a writable buffer of length \p length Bytes.
- *
- * \return                 \c 0 on success.
- * \return                 A negative error code on failure.
- */
-int mbedtls_aria_crypt_ctr( mbedtls_aria_context *ctx,
-                            size_t length,
-                            size_t *nc_off,
-                            unsigned char nonce_counter[MBEDTLS_ARIA_BLOCKSIZE],
-                            unsigned char stream_block[MBEDTLS_ARIA_BLOCKSIZE],
-                            const unsigned char *input,
-                            unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CTR */
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief          Checkup routine.
- *
- * \return         \c 0 on success, or \c 1 on failure.
- */
-int mbedtls_aria_self_test( int verbose );
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* aria.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/asn1.h b/tools/sdk/include/mbedtls/mbedtls/asn1.h
deleted file mode 100644
index c64038cdb5c..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/asn1.h
+++ /dev/null
@@ -1,385 +0,0 @@
-/**
- * \file asn1.h
- *
- * \brief Generic ASN.1 parsing
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_ASN1_H
-#define MBEDTLS_ASN1_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-#if defined(MBEDTLS_BIGNUM_C)
-#include "bignum.h"
-#endif
-
-/**
- * \addtogroup asn1_module
- * \{
- */
-
-/**
- * \name ASN1 Error codes
- * These error codes are OR'ed to X509 error codes for
- * higher error granularity.
- * ASN1 is a standard to specify data structures.
- * \{
- */
-#define MBEDTLS_ERR_ASN1_OUT_OF_DATA                      -0x0060  /**< Out of data when parsing an ASN1 data structure. */
-#define MBEDTLS_ERR_ASN1_UNEXPECTED_TAG                   -0x0062  /**< ASN1 tag was of an unexpected value. */
-#define MBEDTLS_ERR_ASN1_INVALID_LENGTH                   -0x0064  /**< Error when trying to determine the length or invalid length. */
-#define MBEDTLS_ERR_ASN1_LENGTH_MISMATCH                  -0x0066  /**< Actual length differs from expected length. */
-#define MBEDTLS_ERR_ASN1_INVALID_DATA                     -0x0068  /**< Data is invalid. (not used) */
-#define MBEDTLS_ERR_ASN1_ALLOC_FAILED                     -0x006A  /**< Memory allocation failed */
-#define MBEDTLS_ERR_ASN1_BUF_TOO_SMALL                    -0x006C  /**< Buffer too small when writing ASN.1 data structure. */
-
-/* \} name */
-
-/**
- * \name DER constants
- * These constants comply with the DER encoded ASN.1 type tags.
- * DER encoding uses hexadecimal representation.
- * An example DER sequence is:\n
- * - 0x02 -- tag indicating INTEGER
- * - 0x01 -- length in octets
- * - 0x05 -- value
- * Such sequences are typically read into \c ::mbedtls_x509_buf.
- * \{
- */
-#define MBEDTLS_ASN1_BOOLEAN                 0x01
-#define MBEDTLS_ASN1_INTEGER                 0x02
-#define MBEDTLS_ASN1_BIT_STRING              0x03
-#define MBEDTLS_ASN1_OCTET_STRING            0x04
-#define MBEDTLS_ASN1_NULL                    0x05
-#define MBEDTLS_ASN1_OID                     0x06
-#define MBEDTLS_ASN1_UTF8_STRING             0x0C
-#define MBEDTLS_ASN1_SEQUENCE                0x10
-#define MBEDTLS_ASN1_SET                     0x11
-#define MBEDTLS_ASN1_PRINTABLE_STRING        0x13
-#define MBEDTLS_ASN1_T61_STRING              0x14
-#define MBEDTLS_ASN1_IA5_STRING              0x16
-#define MBEDTLS_ASN1_UTC_TIME                0x17
-#define MBEDTLS_ASN1_GENERALIZED_TIME        0x18
-#define MBEDTLS_ASN1_UNIVERSAL_STRING        0x1C
-#define MBEDTLS_ASN1_BMP_STRING              0x1E
-#define MBEDTLS_ASN1_PRIMITIVE               0x00
-#define MBEDTLS_ASN1_CONSTRUCTED             0x20
-#define MBEDTLS_ASN1_CONTEXT_SPECIFIC        0x80
-
-/*
- * Bit masks for each of the components of an ASN.1 tag as specified in
- * ITU X.690 (08/2015), section 8.1 "General rules for encoding",
- * paragraph 8.1.2.2:
- *
- * Bit  8     7   6   5          1
- *     +-------+-----+------------+
- *     | Class | P/C | Tag number |
- *     +-------+-----+------------+
- */
-#define MBEDTLS_ASN1_TAG_CLASS_MASK          0xC0
-#define MBEDTLS_ASN1_TAG_PC_MASK             0x20
-#define MBEDTLS_ASN1_TAG_VALUE_MASK          0x1F
-
-/* \} name */
-/* \} addtogroup asn1_module */
-
-/** Returns the size of the binary string, without the trailing \\0 */
-#define MBEDTLS_OID_SIZE(x) (sizeof(x) - 1)
-
-/**
- * Compares an mbedtls_asn1_buf structure to a reference OID.
- *
- * Only works for 'defined' oid_str values (MBEDTLS_OID_HMAC_SHA1), you cannot use a
- * 'unsigned char *oid' here!
- */
-#define MBEDTLS_OID_CMP(oid_str, oid_buf)                                   \
-        ( ( MBEDTLS_OID_SIZE(oid_str) != (oid_buf)->len ) ||                \
-          memcmp( (oid_str), (oid_buf)->p, (oid_buf)->len) != 0 )
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name Functions to parse ASN.1 data structures
- * \{
- */
-
-/**
- * Type-length-value structure that allows for ASN1 using DER.
- */
-typedef struct mbedtls_asn1_buf
-{
-    int tag;                /**< ASN1 type, e.g. MBEDTLS_ASN1_UTF8_STRING. */
-    size_t len;             /**< ASN1 length, in octets. */
-    unsigned char *p;       /**< ASN1 data, e.g. in ASCII. */
-}
-mbedtls_asn1_buf;
-
-/**
- * Container for ASN1 bit strings.
- */
-typedef struct mbedtls_asn1_bitstring
-{
-    size_t len;                 /**< ASN1 length, in octets. */
-    unsigned char unused_bits;  /**< Number of unused bits at the end of the string */
-    unsigned char *p;           /**< Raw ASN1 data for the bit string */
-}
-mbedtls_asn1_bitstring;
-
-/**
- * Container for a sequence of ASN.1 items
- */
-typedef struct mbedtls_asn1_sequence
-{
-    mbedtls_asn1_buf buf;                   /**< Buffer containing the given ASN.1 item. */
-    struct mbedtls_asn1_sequence *next;    /**< The next entry in the sequence. */
-}
-mbedtls_asn1_sequence;
-
-/**
- * Container for a sequence or list of 'named' ASN.1 data items
- */
-typedef struct mbedtls_asn1_named_data
-{
-    mbedtls_asn1_buf oid;                   /**< The object identifier. */
-    mbedtls_asn1_buf val;                   /**< The named value. */
-    struct mbedtls_asn1_named_data *next;  /**< The next entry in the sequence. */
-    unsigned char next_merged;      /**< Merge next item into the current one? */
-}
-mbedtls_asn1_named_data;
-
-/**
- * \brief       Get the length of an ASN.1 element.
- *              Updates the pointer to immediately behind the length.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param len   The variable that will receive the value
- *
- * \return      0 if successful, MBEDTLS_ERR_ASN1_OUT_OF_DATA on reaching
- *              end of data, MBEDTLS_ERR_ASN1_INVALID_LENGTH if length is
- *              unparseable.
- */
-int mbedtls_asn1_get_len( unsigned char **p,
-                  const unsigned char *end,
-                  size_t *len );
-
-/**
- * \brief       Get the tag and length of the tag. Check for the requested tag.
- *              Updates the pointer to immediately behind the tag and length.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param len   The variable that will receive the length
- * \param tag   The expected tag
- *
- * \return      0 if successful, MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if tag did
- *              not match requested tag, or another specific ASN.1 error code.
- */
-int mbedtls_asn1_get_tag( unsigned char **p,
-                  const unsigned char *end,
-                  size_t *len, int tag );
-
-/**
- * \brief       Retrieve a boolean ASN.1 tag and its value.
- *              Updates the pointer to immediately behind the full tag.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param val   The variable that will receive the value
- *
- * \return      0 if successful or a specific ASN.1 error code.
- */
-int mbedtls_asn1_get_bool( unsigned char **p,
-                   const unsigned char *end,
-                   int *val );
-
-/**
- * \brief       Retrieve an integer ASN.1 tag and its value.
- *              Updates the pointer to immediately behind the full tag.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param val   The variable that will receive the value
- *
- * \return      0 if successful or a specific ASN.1 error code.
- */
-int mbedtls_asn1_get_int( unsigned char **p,
-                  const unsigned char *end,
-                  int *val );
-
-/**
- * \brief       Retrieve a bitstring ASN.1 tag and its value.
- *              Updates the pointer to immediately behind the full tag.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param bs    The variable that will receive the value
- *
- * \return      0 if successful or a specific ASN.1 error code.
- */
-int mbedtls_asn1_get_bitstring( unsigned char **p, const unsigned char *end,
-                        mbedtls_asn1_bitstring *bs);
-
-/**
- * \brief       Retrieve a bitstring ASN.1 tag without unused bits and its
- *              value.
- *              Updates the pointer to the beginning of the bit/octet string.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param len   Length of the actual bit/octect string in bytes
- *
- * \return      0 if successful or a specific ASN.1 error code.
- */
-int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end,
-                             size_t *len );
-
-/**
- * \brief       Parses and splits an ASN.1 "SEQUENCE OF <tag>"
- *              Updated the pointer to immediately behind the full sequence tag.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param cur   First variable in the chain to fill
- * \param tag   Type of sequence
- *
- * \return      0 if successful or a specific ASN.1 error code.
- */
-int mbedtls_asn1_get_sequence_of( unsigned char **p,
-                          const unsigned char *end,
-                          mbedtls_asn1_sequence *cur,
-                          int tag);
-
-#if defined(MBEDTLS_BIGNUM_C)
-/**
- * \brief       Retrieve a MPI value from an integer ASN.1 tag.
- *              Updates the pointer to immediately behind the full tag.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param X     The MPI that will receive the value
- *
- * \return      0 if successful or a specific ASN.1 or MPI error code.
- */
-int mbedtls_asn1_get_mpi( unsigned char **p,
-                  const unsigned char *end,
-                  mbedtls_mpi *X );
-#endif /* MBEDTLS_BIGNUM_C */
-
-/**
- * \brief       Retrieve an AlgorithmIdentifier ASN.1 sequence.
- *              Updates the pointer to immediately behind the full
- *              AlgorithmIdentifier.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param alg   The buffer to receive the OID
- * \param params The buffer to receive the params (if any)
- *
- * \return      0 if successful or a specific ASN.1 or MPI error code.
- */
-int mbedtls_asn1_get_alg( unsigned char **p,
-                  const unsigned char *end,
-                  mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params );
-
-/**
- * \brief       Retrieve an AlgorithmIdentifier ASN.1 sequence with NULL or no
- *              params.
- *              Updates the pointer to immediately behind the full
- *              AlgorithmIdentifier.
- *
- * \param p     The position in the ASN.1 data
- * \param end   End of data
- * \param alg   The buffer to receive the OID
- *
- * \return      0 if successful or a specific ASN.1 or MPI error code.
- */
-int mbedtls_asn1_get_alg_null( unsigned char **p,
-                       const unsigned char *end,
-                       mbedtls_asn1_buf *alg );
-
-/**
- * \brief       Find a specific named_data entry in a sequence or list based on
- *              the OID.
- *
- * \param list  The list to seek through
- * \param oid   The OID to look for
- * \param len   Size of the OID
- *
- * \return      NULL if not found, or a pointer to the existing entry.
- */
-mbedtls_asn1_named_data *mbedtls_asn1_find_named_data( mbedtls_asn1_named_data *list,
-                                       const char *oid, size_t len );
-
-/**
- * \brief       Free a mbedtls_asn1_named_data entry
- *
- * \param entry The named data entry to free
- */
-void mbedtls_asn1_free_named_data( mbedtls_asn1_named_data *entry );
-
-/**
- * \brief       Free all entries in a mbedtls_asn1_named_data list
- *              Head will be set to NULL
- *
- * \param head  Pointer to the head of the list of named data entries to free
- */
-void mbedtls_asn1_free_named_data_list( mbedtls_asn1_named_data **head );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* asn1.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/asn1write.h b/tools/sdk/include/mbedtls/mbedtls/asn1write.h
deleted file mode 100644
index 4fed59371ca..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/asn1write.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/**
- * \file asn1write.h
- *
- * \brief ASN.1 buffer writing functionality
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_ASN1_WRITE_H
-#define MBEDTLS_ASN1_WRITE_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "asn1.h"
-
-#define MBEDTLS_ASN1_CHK_ADD(g, f)                      \
-    do                                                  \
-    {                                                   \
-        if( ( ret = (f) ) < 0 )                         \
-            return( ret );                              \
-        else                                            \
-            (g) += ret;                                 \
-    } while( 0 )
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief           Write a length field in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param len       The length value to write.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_asn1_write_len( unsigned char **p, unsigned char *start,
-                            size_t len );
-/**
- * \brief           Write an ASN.1 tag in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param tag       The tag to write.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_asn1_write_tag( unsigned char **p, unsigned char *start,
-                            unsigned char tag );
-
-/**
- * \brief           Write raw buffer data.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param buf       The data buffer to write.
- * \param size      The length of the data buffer.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_asn1_write_raw_buffer( unsigned char **p, unsigned char *start,
-                                   const unsigned char *buf, size_t size );
-
-#if defined(MBEDTLS_BIGNUM_C)
-/**
- * \brief           Write a arbitrary-precision number (#MBEDTLS_ASN1_INTEGER)
- *                  in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param X         The MPI to write.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_asn1_write_mpi( unsigned char **p, unsigned char *start,
-                            const mbedtls_mpi *X );
-#endif /* MBEDTLS_BIGNUM_C */
-
-/**
- * \brief           Write a NULL tag (#MBEDTLS_ASN1_NULL) with zero data
- *                  in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_asn1_write_null( unsigned char **p, unsigned char *start );
-
-/**
- * \brief           Write an OID tag (#MBEDTLS_ASN1_OID) and data
- *                  in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param oid       The OID to write.
- * \param oid_len   The length of the OID.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_asn1_write_oid( unsigned char **p, unsigned char *start,
-                            const char *oid, size_t oid_len );
-
-/**
- * \brief           Write an AlgorithmIdentifier sequence in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param oid       The OID of the algorithm to write.
- * \param oid_len   The length of the algorithm's OID.
- * \param par_len   The length of the parameters, which must be already written.
- *                  If 0, NULL parameters are added
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_asn1_write_algorithm_identifier( unsigned char **p,
-                                             unsigned char *start,
-                                             const char *oid, size_t oid_len,
-                                             size_t par_len );
-
-/**
- * \brief           Write a boolean tag (#MBEDTLS_ASN1_BOOLEAN) and value
- *                  in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param boolean   The boolean value to write, either \c 0 or \c 1.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_asn1_write_bool( unsigned char **p, unsigned char *start,
-                             int boolean );
-
-/**
- * \brief           Write an int tag (#MBEDTLS_ASN1_INTEGER) and value
- *                  in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param val       The integer value to write.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_asn1_write_int( unsigned char **p, unsigned char *start, int val );
-
-/**
- * \brief           Write a string in ASN.1 format using a specific
- *                  string encoding tag.
-
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param tag       The string encoding tag to write, e.g.
- *                  #MBEDTLS_ASN1_UTF8_STRING.
- * \param text      The string to write.
- * \param text_len  The length of \p text in bytes (which might
- *                  be strictly larger than the number of characters).
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_asn1_write_tagged_string( unsigned char **p, unsigned char *start,
-                                      int tag, const char *text,
-                                      size_t text_len );
-
-/**
- * \brief           Write a string in ASN.1 format using the PrintableString
- *                  string encoding tag (#MBEDTLS_ASN1_PRINTABLE_STRING).
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param text      The string to write.
- * \param text_len  The length of \p text in bytes (which might
- *                  be strictly larger than the number of characters).
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_asn1_write_printable_string( unsigned char **p,
-                                         unsigned char *start,
-                                         const char *text, size_t text_len );
-
-/**
- * \brief           Write a UTF8 string in ASN.1 format using the UTF8String
- *                  string encoding tag (#MBEDTLS_ASN1_PRINTABLE_STRING).
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param text      The string to write.
- * \param text_len  The length of \p text in bytes (which might
- *                  be strictly larger than the number of characters).
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_asn1_write_utf8_string( unsigned char **p, unsigned char *start,
-                                    const char *text, size_t text_len );
-
-/**
- * \brief           Write a string in ASN.1 format using the IA5String
- *                  string encoding tag (#MBEDTLS_ASN1_IA5_STRING).
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param text      The string to write.
- * \param text_len  The length of \p text in bytes (which might
- *                  be strictly larger than the number of characters).
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_asn1_write_ia5_string( unsigned char **p, unsigned char *start,
-                                   const char *text, size_t text_len );
-
-/**
- * \brief           Write a bitstring tag (#MBEDTLS_ASN1_BIT_STRING) and
- *                  value in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param buf       The bitstring to write.
- * \param bits      The total number of bits in the bitstring.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_asn1_write_bitstring( unsigned char **p, unsigned char *start,
-                                  const unsigned char *buf, size_t bits );
-
-/**
- * \brief           Write an octet string tag (#MBEDTLS_ASN1_OCTET_STRING)
- *                  and value in ASN.1 format.
- *
- * \note            This function works backwards in data buffer.
- *
- * \param p         The reference to the current position pointer.
- * \param start     The start of the buffer, for bounds-checking.
- * \param buf       The buffer holding the data to write.
- * \param size      The length of the data buffer \p buf.
- *
- * \return          The number of bytes written to \p p on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_asn1_write_octet_string( unsigned char **p, unsigned char *start,
-                                     const unsigned char *buf, size_t size );
-
-/**
- * \brief           Create or find a specific named_data entry for writing in a
- *                  sequence or list based on the OID. If not already in there,
- *                  a new entry is added to the head of the list.
- *                  Warning: Destructive behaviour for the val data!
- *
- * \param list      The pointer to the location of the head of the list to seek
- *                  through (will be updated in case of a new entry).
- * \param oid       The OID to look for.
- * \param oid_len   The size of the OID.
- * \param val       The data to store (can be \c NULL if you want to fill
- *                  it by hand).
- * \param val_len   The minimum length of the data buffer needed.
- *
- * \return          A pointer to the new / existing entry on success.
- * \return          \c NULL if if there was a memory allocation error.
- */
-mbedtls_asn1_named_data *mbedtls_asn1_store_named_data( mbedtls_asn1_named_data **list,
-                                        const char *oid, size_t oid_len,
-                                        const unsigned char *val,
-                                        size_t val_len );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_ASN1_WRITE_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/base64.h b/tools/sdk/include/mbedtls/mbedtls/base64.h
deleted file mode 100644
index 215255e628e..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/base64.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- * \file base64.h
- *
- * \brief RFC 1521 base64 encoding/decoding
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_BASE64_H
-#define MBEDTLS_BASE64_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-#define MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL               -0x002A  /**< Output buffer too small. */
-#define MBEDTLS_ERR_BASE64_INVALID_CHARACTER              -0x002C  /**< Invalid character in input. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          Encode a buffer into base64 format
- *
- * \param dst      destination buffer
- * \param dlen     size of the destination buffer
- * \param olen     number of bytes written
- * \param src      source buffer
- * \param slen     amount of data to be encoded
- *
- * \return         0 if successful, or MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL.
- *                 *olen is always updated to reflect the amount
- *                 of data that has (or would have) been written.
- *                 If that length cannot be represented, then no data is
- *                 written to the buffer and *olen is set to the maximum
- *                 length representable as a size_t.
- *
- * \note           Call this function with dlen = 0 to obtain the
- *                 required buffer size in *olen
- */
-int mbedtls_base64_encode( unsigned char *dst, size_t dlen, size_t *olen,
-                   const unsigned char *src, size_t slen );
-
-/**
- * \brief          Decode a base64-formatted buffer
- *
- * \param dst      destination buffer (can be NULL for checking size)
- * \param dlen     size of the destination buffer
- * \param olen     number of bytes written
- * \param src      source buffer
- * \param slen     amount of data to be decoded
- *
- * \return         0 if successful, MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL, or
- *                 MBEDTLS_ERR_BASE64_INVALID_CHARACTER if the input data is
- *                 not correct. *olen is always updated to reflect the amount
- *                 of data that has (or would have) been written.
- *
- * \note           Call this function with *dst = NULL or dlen = 0 to obtain
- *                 the required buffer size in *olen
- */
-int mbedtls_base64_decode( unsigned char *dst, size_t dlen, size_t *olen,
-                   const unsigned char *src, size_t slen );
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- */
-int mbedtls_base64_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* base64.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/bignum.h b/tools/sdk/include/mbedtls/mbedtls/bignum.h
deleted file mode 100644
index 1e41d702456..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/bignum.h
+++ /dev/null
@@ -1,1016 +0,0 @@
-/**
- * \file bignum.h
- *
- * \brief Multi-precision integer library
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_BIGNUM_H
-#define MBEDTLS_BIGNUM_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-#if defined(MBEDTLS_FS_IO)
-#include <stdio.h>
-#endif
-
-#define MBEDTLS_ERR_MPI_FILE_IO_ERROR                     -0x0002  /**< An error occurred while reading from or writing to a file. */
-#define MBEDTLS_ERR_MPI_BAD_INPUT_DATA                    -0x0004  /**< Bad input parameters to function. */
-#define MBEDTLS_ERR_MPI_INVALID_CHARACTER                 -0x0006  /**< There is an invalid character in the digit string. */
-#define MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL                  -0x0008  /**< The buffer is too small to write to. */
-#define MBEDTLS_ERR_MPI_NEGATIVE_VALUE                    -0x000A  /**< The input arguments are negative or result in illegal output. */
-#define MBEDTLS_ERR_MPI_DIVISION_BY_ZERO                  -0x000C  /**< The input argument for division is zero, which is not allowed. */
-#define MBEDTLS_ERR_MPI_NOT_ACCEPTABLE                    -0x000E  /**< The input arguments are not acceptable. */
-#define MBEDTLS_ERR_MPI_ALLOC_FAILED                      -0x0010  /**< Memory allocation failed. */
-
-#define MBEDTLS_MPI_CHK(f)       \
-    do                           \
-    {                            \
-        if( ( ret = (f) ) != 0 ) \
-            goto cleanup;        \
-    } while( 0 )
-
-/*
- * Maximum size MPIs are allowed to grow to in number of limbs.
- */
-#define MBEDTLS_MPI_MAX_LIMBS                             10000
-
-#if !defined(MBEDTLS_MPI_WINDOW_SIZE)
-/*
- * Maximum window size used for modular exponentiation. Default: 6
- * Minimum value: 1. Maximum value: 6.
- *
- * Result is an array of ( 2 << MBEDTLS_MPI_WINDOW_SIZE ) MPIs used
- * for the sliding window calculation. (So 64 by default)
- *
- * Reduction in size, reduces speed.
- */
-#define MBEDTLS_MPI_WINDOW_SIZE                           6        /**< Maximum windows size used. */
-#endif /* !MBEDTLS_MPI_WINDOW_SIZE */
-
-#if !defined(MBEDTLS_MPI_MAX_SIZE)
-/*
- * Maximum size of MPIs allowed in bits and bytes for user-MPIs.
- * ( Default: 512 bytes => 4096 bits, Maximum tested: 2048 bytes => 16384 bits )
- *
- * Note: Calculations can temporarily result in larger MPIs. So the number
- * of limbs required (MBEDTLS_MPI_MAX_LIMBS) is higher.
- */
-#define MBEDTLS_MPI_MAX_SIZE                              1024     /**< Maximum number of bytes for usable MPIs. */
-#endif /* !MBEDTLS_MPI_MAX_SIZE */
-
-#define MBEDTLS_MPI_MAX_BITS                              ( 8 * MBEDTLS_MPI_MAX_SIZE )    /**< Maximum number of bits for usable MPIs. */
-
-/*
- * When reading from files with mbedtls_mpi_read_file() and writing to files with
- * mbedtls_mpi_write_file() the buffer should have space
- * for a (short) label, the MPI (in the provided radix), the newline
- * characters and the '\0'.
- *
- * By default we assume at least a 10 char label, a minimum radix of 10
- * (decimal) and a maximum of 4096 bit numbers (1234 decimal chars).
- * Autosized at compile time for at least a 10 char label, a minimum radix
- * of 10 (decimal) for a number of MBEDTLS_MPI_MAX_BITS size.
- *
- * This used to be statically sized to 1250 for a maximum of 4096 bit
- * numbers (1234 decimal chars).
- *
- * Calculate using the formula:
- *  MBEDTLS_MPI_RW_BUFFER_SIZE = ceil(MBEDTLS_MPI_MAX_BITS / ln(10) * ln(2)) +
- *                                LabelSize + 6
- */
-#define MBEDTLS_MPI_MAX_BITS_SCALE100          ( 100 * MBEDTLS_MPI_MAX_BITS )
-#define MBEDTLS_LN_2_DIV_LN_10_SCALE100                 332
-#define MBEDTLS_MPI_RW_BUFFER_SIZE             ( ((MBEDTLS_MPI_MAX_BITS_SCALE100 + MBEDTLS_LN_2_DIV_LN_10_SCALE100 - 1) / MBEDTLS_LN_2_DIV_LN_10_SCALE100) + 10 + 6 )
-
-#if !defined(MBEDTLS_BIGNUM_ALT)
-
-/*
- * Define the base integer type, architecture-wise.
- *
- * 32 or 64-bit integer types can be forced regardless of the underlying
- * architecture by defining MBEDTLS_HAVE_INT32 or MBEDTLS_HAVE_INT64
- * respectively and undefining MBEDTLS_HAVE_ASM.
- *
- * Double-width integers (e.g. 128-bit in 64-bit architectures) can be
- * disabled by defining MBEDTLS_NO_UDBL_DIVISION.
- */
-#if !defined(MBEDTLS_HAVE_INT32)
-    #if defined(_MSC_VER) && defined(_M_AMD64)
-        /* Always choose 64-bit when using MSC */
-        #if !defined(MBEDTLS_HAVE_INT64)
-            #define MBEDTLS_HAVE_INT64
-        #endif /* !MBEDTLS_HAVE_INT64 */
-        typedef  int64_t mbedtls_mpi_sint;
-        typedef uint64_t mbedtls_mpi_uint;
-    #elif defined(__GNUC__) && (                         \
-        defined(__amd64__) || defined(__x86_64__)     || \
-        defined(__ppc64__) || defined(__powerpc64__)  || \
-        defined(__ia64__)  || defined(__alpha__)      || \
-        ( defined(__sparc__) && defined(__arch64__) ) || \
-        defined(__s390x__) || defined(__mips64) )
-        #if !defined(MBEDTLS_HAVE_INT64)
-            #define MBEDTLS_HAVE_INT64
-        #endif /* MBEDTLS_HAVE_INT64 */
-        typedef  int64_t mbedtls_mpi_sint;
-        typedef uint64_t mbedtls_mpi_uint;
-        #if !defined(MBEDTLS_NO_UDBL_DIVISION)
-            /* mbedtls_t_udbl defined as 128-bit unsigned int */
-            typedef unsigned int mbedtls_t_udbl __attribute__((mode(TI)));
-            #define MBEDTLS_HAVE_UDBL
-        #endif /* !MBEDTLS_NO_UDBL_DIVISION */
-    #elif defined(__ARMCC_VERSION) && defined(__aarch64__)
-        /*
-         * __ARMCC_VERSION is defined for both armcc and armclang and
-         * __aarch64__ is only defined by armclang when compiling 64-bit code
-         */
-        #if !defined(MBEDTLS_HAVE_INT64)
-            #define MBEDTLS_HAVE_INT64
-        #endif /* !MBEDTLS_HAVE_INT64 */
-        typedef  int64_t mbedtls_mpi_sint;
-        typedef uint64_t mbedtls_mpi_uint;
-        #if !defined(MBEDTLS_NO_UDBL_DIVISION)
-            /* mbedtls_t_udbl defined as 128-bit unsigned int */
-            typedef __uint128_t mbedtls_t_udbl;
-            #define MBEDTLS_HAVE_UDBL
-        #endif /* !MBEDTLS_NO_UDBL_DIVISION */
-    #elif defined(MBEDTLS_HAVE_INT64)
-        /* Force 64-bit integers with unknown compiler */
-        typedef  int64_t mbedtls_mpi_sint;
-        typedef uint64_t mbedtls_mpi_uint;
-    #endif
-#endif /* !MBEDTLS_HAVE_INT32 */
-
-#if !defined(MBEDTLS_HAVE_INT64)
-    /* Default to 32-bit compilation */
-    #if !defined(MBEDTLS_HAVE_INT32)
-        #define MBEDTLS_HAVE_INT32
-    #endif /* !MBEDTLS_HAVE_INT32 */
-    typedef  int32_t mbedtls_mpi_sint;
-    typedef uint32_t mbedtls_mpi_uint;
-    #if !defined(MBEDTLS_NO_UDBL_DIVISION)
-        typedef uint64_t mbedtls_t_udbl;
-        #define MBEDTLS_HAVE_UDBL
-    #endif /* !MBEDTLS_NO_UDBL_DIVISION */
-#endif /* !MBEDTLS_HAVE_INT64 */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          MPI structure
- */
-typedef struct mbedtls_mpi
-{
-    int s;              /*!<  Sign: -1 if the mpi is negative, 1 otherwise */
-    size_t n;           /*!<  total # of limbs  */
-    mbedtls_mpi_uint *p;          /*!<  pointer to limbs  */
-}
-mbedtls_mpi;
-
-/**
- * \brief           Initialize an MPI context.
- *
- *                  This makes the MPI ready to be set or freed,
- *                  but does not define a value for the MPI.
- *
- * \param X         The MPI context to initialize. This must not be \c NULL.
- */
-void mbedtls_mpi_init( mbedtls_mpi *X );
-
-/**
- * \brief          This function frees the components of an MPI context.
- *
- * \param X        The MPI context to be cleared. This may be \c NULL,
- *                 in which case this function is a no-op. If it is
- *                 not \c NULL, it must point to an initialized MPI.
- */
-void mbedtls_mpi_free( mbedtls_mpi *X );
-
-/**
- * \brief          Enlarge an MPI to the specified number of limbs.
- *
- * \note           This function does nothing if the MPI is
- *                 already large enough.
- *
- * \param X        The MPI to grow. It must be initialized.
- * \param nblimbs  The target number of limbs.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed.
- * \return         Another negative error code on other kinds of failure.
- */
-int mbedtls_mpi_grow( mbedtls_mpi *X, size_t nblimbs );
-
-/**
- * \brief          This function resizes an MPI downwards, keeping at least the
- *                 specified number of limbs.
- *
- *                 If \c X is smaller than \c nblimbs, it is resized up
- *                 instead.
- *
- * \param X        The MPI to shrink. This must point to an initialized MPI.
- * \param nblimbs  The minimum number of limbs to keep.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed
- *                 (this can only happen when resizing up).
- * \return         Another negative error code on other kinds of failure.
- */
-int mbedtls_mpi_shrink( mbedtls_mpi *X, size_t nblimbs );
-
-/**
- * \brief          Make a copy of an MPI.
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param Y        The source MPI. This must point to an initialized MPI.
- *
- * \note           The limb-buffer in the destination MPI is enlarged
- *                 if necessary to hold the value in the source MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed.
- * \return         Another negative error code on other kinds of failure.
- */
-int mbedtls_mpi_copy( mbedtls_mpi *X, const mbedtls_mpi *Y );
-
-/**
- * \brief          Swap the contents of two MPIs.
- *
- * \param X        The first MPI. It must be initialized.
- * \param Y        The second MPI. It must be initialized.
- */
-void mbedtls_mpi_swap( mbedtls_mpi *X, mbedtls_mpi *Y );
-
-/**
- * \brief          Perform a safe conditional copy of MPI which doesn't
- *                 reveal whether the condition was true or not.
- *
- * \param X        The MPI to conditionally assign to. This must point
- *                 to an initialized MPI.
- * \param Y        The MPI to be assigned from. This must point to an
- *                 initialized MPI.
- * \param assign   The condition deciding whether to perform the
- *                 assignment or not. Possible values:
- *                 * \c 1: Perform the assignment `X = Y`.
- *                 * \c 0: Keep the original value of \p X.
- *
- * \note           This function is equivalent to
- *                      `if( assign ) mbedtls_mpi_copy( X, Y );`
- *                 except that it avoids leaking any information about whether
- *                 the assignment was done or not (the above code may leak
- *                 information through branch prediction and/or memory access
- *                 patterns analysis).
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed.
- * \return         Another negative error code on other kinds of failure.
- */
-int mbedtls_mpi_safe_cond_assign( mbedtls_mpi *X, const mbedtls_mpi *Y, unsigned char assign );
-
-/**
- * \brief          Perform a safe conditional swap which doesn't
- *                 reveal whether the condition was true or not.
- *
- * \param X        The first MPI. This must be initialized.
- * \param Y        The second MPI. This must be initialized.
- * \param assign   The condition deciding whether to perform
- *                 the swap or not. Possible values:
- *                 * \c 1: Swap the values of \p X and \p Y.
- *                 * \c 0: Keep the original values of \p X and \p Y.
- *
- * \note           This function is equivalent to
- *                      if( assign ) mbedtls_mpi_swap( X, Y );
- *                 except that it avoids leaking any information about whether
- *                 the assignment was done or not (the above code may leak
- *                 information through branch prediction and/or memory access
- *                 patterns analysis).
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed.
- * \return         Another negative error code on other kinds of failure.
- *
- */
-int mbedtls_mpi_safe_cond_swap( mbedtls_mpi *X, mbedtls_mpi *Y, unsigned char assign );
-
-/**
- * \brief          Store integer value in MPI.
- *
- * \param X        The MPI to set. This must be initialized.
- * \param z        The value to use.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed.
- * \return         Another negative error code on other kinds of failure.
- */
-int mbedtls_mpi_lset( mbedtls_mpi *X, mbedtls_mpi_sint z );
-
-/**
- * \brief          Get a specific bit from an MPI.
- *
- * \param X        The MPI to query. This must be initialized.
- * \param pos      Zero-based index of the bit to query.
- *
- * \return         \c 0 or \c 1 on success, depending on whether bit \c pos
- *                 of \c X is unset or set.
- * \return         A negative error code on failure.
- */
-int mbedtls_mpi_get_bit( const mbedtls_mpi *X, size_t pos );
-
-/**
- * \brief          Modify a specific bit in an MPI.
- *
- * \note           This function will grow the target MPI if necessary to set a
- *                 bit to \c 1 in a not yet existing limb. It will not grow if
- *                 the bit should be set to \c 0.
- *
- * \param X        The MPI to modify. This must be initialized.
- * \param pos      Zero-based index of the bit to modify.
- * \param val      The desired value of bit \c pos: \c 0 or \c 1.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed.
- * \return         Another negative error code on other kinds of failure.
- */
-int mbedtls_mpi_set_bit( mbedtls_mpi *X, size_t pos, unsigned char val );
-
-/**
- * \brief          Return the number of bits of value \c 0 before the
- *                 least significant bit of value \c 1.
- *
- * \note           This is the same as the zero-based index of
- *                 the least significant bit of value \c 1.
- *
- * \param X        The MPI to query.
- *
- * \return         The number of bits of value \c 0 before the least significant
- *                 bit of value \c 1 in \p X.
- */
-size_t mbedtls_mpi_lsb( const mbedtls_mpi *X );
-
-/**
- * \brief          Return the number of bits up to and including the most
- *                 significant bit of value \c 1.
- *
- * * \note         This is same as the one-based index of the most
- *                 significant bit of value \c 1.
- *
- * \param X        The MPI to query. This must point to an initialized MPI.
- *
- * \return         The number of bits up to and including the most
- *                 significant bit of value \c 1.
- */
-size_t mbedtls_mpi_bitlen( const mbedtls_mpi *X );
-
-/**
- * \brief          Return the total size of an MPI value in bytes.
- *
- * \param X        The MPI to use. This must point to an initialized MPI.
- *
- * \note           The value returned by this function may be less than
- *                 the number of bytes used to store \p X internally.
- *                 This happens if and only if there are trailing bytes
- *                 of value zero.
- *
- * \return         The least number of bytes capable of storing
- *                 the absolute value of \p X.
- */
-size_t mbedtls_mpi_size( const mbedtls_mpi *X );
-
-/**
- * \brief          Import an MPI from an ASCII string.
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param radix    The numeric base of the input string.
- * \param s        Null-terminated string buffer.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_mpi_read_string( mbedtls_mpi *X, int radix, const char *s );
-
-/**
- * \brief          Export an MPI to an ASCII string.
- *
- * \param X        The source MPI. This must point to an initialized MPI.
- * \param radix    The numeric base of the output string.
- * \param buf      The buffer to write the string to. This must be writable
- *                 buffer of length \p buflen Bytes.
- * \param buflen   The available size in Bytes of \p buf.
- * \param olen     The address at which to store the length of the string
- *                 written, including the  final \c NULL byte. This must
- *                 not be \c NULL.
- *
- * \note           You can call this function with `buflen == 0` to obtain the
- *                 minimum required buffer size in `*olen`.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if the target buffer \p buf
- *                 is too small to hold the value of \p X in the desired base.
- *                 In this case, `*olen` is nonetheless updated to contain the
- *                 size of \p buf required for a successful call.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_write_string( const mbedtls_mpi *X, int radix,
-                              char *buf, size_t buflen, size_t *olen );
-
-#if defined(MBEDTLS_FS_IO)
-/**
- * \brief          Read an MPI from a line in an opened file.
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param radix    The numeric base of the string representation used
- *                 in the source line.
- * \param fin      The input file handle to use. This must not be \c NULL.
- *
- * \note           On success, this function advances the file stream
- *                 to the end of the current line or to EOF.
- *
- *                 The function returns \c 0 on an empty line.
- *
- *                 Leading whitespaces are ignored, as is a
- *                 '0x' prefix for radix \c 16.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if the file read buffer
- *                 is too small.
- * \return         Another negative error code on failure.
- */
-int mbedtls_mpi_read_file( mbedtls_mpi *X, int radix, FILE *fin );
-
-/**
- * \brief          Export an MPI into an opened file.
- *
- * \param p        A string prefix to emit prior to the MPI data.
- *                 For example, this might be a label, or "0x" when
- *                 printing in base \c 16. This may be \c NULL if no prefix
- *                 is needed.
- * \param X        The source MPI. This must point to an initialized MPI.
- * \param radix    The numeric base to be used in the emitted string.
- * \param fout     The output file handle. This may be \c NULL, in which case
- *                 the output is written to \c stdout.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_mpi_write_file( const char *p, const mbedtls_mpi *X,
-                            int radix, FILE *fout );
-#endif /* MBEDTLS_FS_IO */
-
-/**
- * \brief          Import an MPI from unsigned big endian binary data.
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param buf      The input buffer. This must be a readable buffer of length
- *                 \p buflen Bytes.
- * \param buflen   The length of the input buffer \p p in Bytes.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_read_binary( mbedtls_mpi *X, const unsigned char *buf,
-                             size_t buflen );
-
-/**
- * \brief          Export an MPI into unsigned big endian binary data
- *                 of fixed size.
- *
- * \param X        The source MPI. This must point to an initialized MPI.
- * \param buf      The output buffer. This must be a writable buffer of length
- *                 \p buflen Bytes.
- * \param buflen   The size of the output buffer \p buf in Bytes.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p buf isn't
- *                 large enough to hold the value of \p X.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_write_binary( const mbedtls_mpi *X, unsigned char *buf,
-                              size_t buflen );
-
-/**
- * \brief          Perform a left-shift on an MPI: X <<= count
- *
- * \param X        The MPI to shift. This must point to an initialized MPI.
- * \param count    The number of bits to shift by.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_shift_l( mbedtls_mpi *X, size_t count );
-
-/**
- * \brief          Perform a right-shift on an MPI: X >>= count
- *
- * \param X        The MPI to shift. This must point to an initialized MPI.
- * \param count    The number of bits to shift by.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_shift_r( mbedtls_mpi *X, size_t count );
-
-/**
- * \brief          Compare the absolute values of two MPIs.
- *
- * \param X        The left-hand MPI. This must point to an initialized MPI.
- * \param Y        The right-hand MPI. This must point to an initialized MPI.
- *
- * \return         \c 1 if `|X|` is greater than `|Y|`.
- * \return         \c -1 if `|X|` is lesser than `|Y|`.
- * \return         \c 0 if `|X|` is equal to `|Y|`.
- */
-int mbedtls_mpi_cmp_abs( const mbedtls_mpi *X, const mbedtls_mpi *Y );
-
-/**
- * \brief          Compare two MPIs.
- *
- * \param X        The left-hand MPI. This must point to an initialized MPI.
- * \param Y        The right-hand MPI. This must point to an initialized MPI.
- *
- * \return         \c 1 if \p X is greater than \p Y.
- * \return         \c -1 if \p X is lesser than \p Y.
- * \return         \c 0 if \p X is equal to \p Y.
- */
-int mbedtls_mpi_cmp_mpi( const mbedtls_mpi *X, const mbedtls_mpi *Y );
-
-/**
- * \brief          Check if an MPI is less than the other in constant time.
- *
- * \param X        The left-hand MPI. This must point to an initialized MPI
- *                 with the same allocated length as Y.
- * \param Y        The right-hand MPI. This must point to an initialized MPI
- *                 with the same allocated length as X.
- * \param ret      The result of the comparison:
- *                 \c 1 if \p X is less than \p Y.
- *                 \c 0 if \p X is greater than or equal to \p Y.
- *
- * \return         0 on success.
- * \return         MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the allocated length of
- *                 the two input MPIs is not the same.
- */
-int mbedtls_mpi_lt_mpi_ct( const mbedtls_mpi *X, const mbedtls_mpi *Y,
-        unsigned *ret );
-
-/**
- * \brief          Compare an MPI with an integer.
- *
- * \param X        The left-hand MPI. This must point to an initialized MPI.
- * \param z        The integer value to compare \p X to.
- *
- * \return         \c 1 if \p X is greater than \p z.
- * \return         \c -1 if \p X is lesser than \p z.
- * \return         \c 0 if \p X is equal to \p z.
- */
-int mbedtls_mpi_cmp_int( const mbedtls_mpi *X, mbedtls_mpi_sint z );
-
-/**
- * \brief          Perform an unsigned addition of MPIs: X = |A| + |B|
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The first summand. This must point to an initialized MPI.
- * \param B        The second summand. This must point to an initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_add_abs( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         const mbedtls_mpi *B );
-
-/**
- * \brief          Perform an unsigned subtraction of MPIs: X = |A| - |B|
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The minuend. This must point to an initialized MPI.
- * \param B        The subtrahend. This must point to an initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p B is greater than \p A.
- * \return         Another negative error code on different kinds of failure.
- *
- */
-int mbedtls_mpi_sub_abs( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         const mbedtls_mpi *B );
-
-/**
- * \brief          Perform a signed addition of MPIs: X = A + B
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The first summand. This must point to an initialized MPI.
- * \param B        The second summand. This must point to an initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_add_mpi( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         const mbedtls_mpi *B );
-
-/**
- * \brief          Perform a signed subtraction of MPIs: X = A - B
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The minuend. This must point to an initialized MPI.
- * \param B        The subtrahend. This must point to an initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_sub_mpi( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         const mbedtls_mpi *B );
-
-/**
- * \brief          Perform a signed addition of an MPI and an integer: X = A + b
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The first summand. This must point to an initialized MPI.
- * \param b        The second summand.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_add_int( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         mbedtls_mpi_sint b );
-
-/**
- * \brief          Perform a signed subtraction of an MPI and an integer:
- *                 X = A - b
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The minuend. This must point to an initialized MPI.
- * \param b        The subtrahend.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_sub_int( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         mbedtls_mpi_sint b );
-
-/**
- * \brief          Perform a multiplication of two MPIs: X = A * B
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The first factor. This must point to an initialized MPI.
- * \param B        The second factor. This must point to an initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- *
- */
-int mbedtls_mpi_mul_mpi( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         const mbedtls_mpi *B );
-
-/**
- * \brief          Perform a multiplication of an MPI with an unsigned integer:
- *                 X = A * b
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The first factor. This must point to an initialized MPI.
- * \param b        The second factor.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- *
- */
-int mbedtls_mpi_mul_int( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         mbedtls_mpi_uint b );
-
-/**
- * \brief          Perform a division with remainder of two MPIs:
- *                 A = Q * B + R
- *
- * \param Q        The destination MPI for the quotient.
- *                 This may be \c NULL if the value of the
- *                 quotient is not needed.
- * \param R        The destination MPI for the remainder value.
- *                 This may be \c NULL if the value of the
- *                 remainder is not needed.
- * \param A        The dividend. This must point to an initialized MPi.
- * \param B        The divisor. This must point to an initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed.
- * \return         #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p B equals zero.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A,
-                         const mbedtls_mpi *B );
-
-/**
- * \brief          Perform a division with remainder of an MPI by an integer:
- *                 A = Q * b + R
- *
- * \param Q        The destination MPI for the quotient.
- *                 This may be \c NULL if the value of the
- *                 quotient is not needed.
- * \param R        The destination MPI for the remainder value.
- *                 This may be \c NULL if the value of the
- *                 remainder is not needed.
- * \param A        The dividend. This must point to an initialized MPi.
- * \param b        The divisor.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed.
- * \return         #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p b equals zero.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_div_int( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A,
-                         mbedtls_mpi_sint b );
-
-/**
- * \brief          Perform a modular reduction. R = A mod B
- *
- * \param R        The destination MPI for the residue value.
- *                 This must point to an initialized MPI.
- * \param A        The MPI to compute the residue of.
- *                 This must point to an initialized MPI.
- * \param B        The base of the modular reduction.
- *                 This must point to an initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p B equals zero.
- * \return         #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p B is negative.
- * \return         Another negative error code on different kinds of failure.
- *
- */
-int mbedtls_mpi_mod_mpi( mbedtls_mpi *R, const mbedtls_mpi *A,
-                         const mbedtls_mpi *B );
-
-/**
- * \brief          Perform a modular reduction with respect to an integer.
- *                 r = A mod b
- *
- * \param r        The address at which to store the residue.
- *                 This must not be \c NULL.
- * \param A        The MPI to compute the residue of.
- *                 This must point to an initialized MPi.
- * \param b        The integer base of the modular reduction.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p b equals zero.
- * \return         #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p b is negative.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_mod_int( mbedtls_mpi_uint *r, const mbedtls_mpi *A,
-                         mbedtls_mpi_sint b );
-
-/**
- * \brief          Perform a sliding-window exponentiation: X = A^E mod N
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The base of the exponentiation.
- *                 This must point to an initialized MPI.
- * \param E        The exponent MPI. This must point to an initialized MPI.
- * \param N        The base for the modular reduction. This must point to an
- *                 initialized MPI.
- * \param _RR      A helper MPI depending solely on \p N which can be used to
- *                 speed-up multiple modular exponentiations for the same value
- *                 of \p N. This may be \c NULL. If it is not \c NULL, it must
- *                 point to an initialized MPI. If it hasn't been used after
- *                 the call to mbedtls_mpi_init(), this function will compute
- *                 the helper value and store it in \p _RR for reuse on
- *                 subsequent calls to this function. Otherwise, the function
- *                 will assume that \p _RR holds the helper value set by a
- *                 previous call to mbedtls_mpi_exp_mod(), and reuse it.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \c N is negative or
- *                 even, or if \c E is negative.
- * \return         Another negative error code on different kinds of failures.
- *
- */
-int mbedtls_mpi_exp_mod( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         const mbedtls_mpi *E, const mbedtls_mpi *N,
-                         mbedtls_mpi *_RR );
-
-/**
- * \brief          Fill an MPI with a number of random bytes.
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param size     The number of random bytes to generate.
- * \param f_rng    The RNG function to use. This must not be \c NULL.
- * \param p_rng    The RNG parameter to be passed to \p f_rng. This may be
- *                 \c NULL if \p f_rng doesn't need a context argument.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on failure.
- *
- * \note           The bytes obtained from the RNG are interpreted
- *                 as a big-endian representation of an MPI; this can
- *                 be relevant in applications like deterministic ECDSA.
- */
-int mbedtls_mpi_fill_random( mbedtls_mpi *X, size_t size,
-                     int (*f_rng)(void *, unsigned char *, size_t),
-                     void *p_rng );
-
-/**
- * \brief          Compute the greatest common divisor: G = gcd(A, B)
- *
- * \param G        The destination MPI. This must point to an initialized MPI.
- * \param A        The first operand. This must point to an initialized MPI.
- * \param B        The second operand. This must point to an initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         Another negative error code on different kinds of failure.
- */
-int mbedtls_mpi_gcd( mbedtls_mpi *G, const mbedtls_mpi *A,
-                     const mbedtls_mpi *B );
-
-/**
- * \brief          Compute the modular inverse: X = A^-1 mod N
- *
- * \param X        The destination MPI. This must point to an initialized MPI.
- * \param A        The MPI to calculate the modular inverse of. This must point
- *                 to an initialized MPI.
- * \param N        The base of the modular inversion. This must point to an
- *                 initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p N is less than
- *                 or equal to one.
- * \return         #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p has no modular inverse
- *                 with respect to \p N.
- */
-int mbedtls_mpi_inv_mod( mbedtls_mpi *X, const mbedtls_mpi *A,
-                         const mbedtls_mpi *N );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          Perform a Miller-Rabin primality test with error
- *                 probability of 2<sup>-80</sup>.
- *
- * \deprecated     Superseded by mbedtls_mpi_is_prime_ext() which allows
- *                 specifying the number of Miller-Rabin rounds.
- *
- * \param X        The MPI to check for primality.
- *                 This must point to an initialized MPI.
- * \param f_rng    The RNG function to use. This must not be \c NULL.
- * \param p_rng    The RNG parameter to be passed to \p f_rng.
- *                 This may be \c NULL if \p f_rng doesn't use a
- *                 context parameter.
- *
- * \return         \c 0 if successful, i.e. \p X is probably prime.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p X is not prime.
- * \return         Another negative error code on other kinds of failure.
- */
-MBEDTLS_DEPRECATED int mbedtls_mpi_is_prime( const mbedtls_mpi *X,
-                          int (*f_rng)(void *, unsigned char *, size_t),
-                          void *p_rng );
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief          Miller-Rabin primality test.
- *
- * \warning        If \p X is potentially generated by an adversary, for example
- *                 when validating cryptographic parameters that you didn't
- *                 generate yourself and that are supposed to be prime, then
- *                 \p rounds should be at least the half of the security
- *                 strength of the cryptographic algorithm. On the other hand,
- *                 if \p X is chosen uniformly or non-adversially (as is the
- *                 case when mbedtls_mpi_gen_prime calls this function), then
- *                 \p rounds can be much lower.
- *
- * \param X        The MPI to check for primality.
- *                 This must point to an initialized MPI.
- * \param rounds   The number of bases to perform the Miller-Rabin primality
- *                 test for. The probability of returning 0 on a composite is
- *                 at most 2<sup>-2*\p rounds</sup>.
- * \param f_rng    The RNG function to use. This must not be \c NULL.
- * \param p_rng    The RNG parameter to be passed to \p f_rng.
- *                 This may be \c NULL if \p f_rng doesn't use
- *                 a context parameter.
- *
- * \return         \c 0 if successful, i.e. \p X is probably prime.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p X is not prime.
- * \return         Another negative error code on other kinds of failure.
- */
-int mbedtls_mpi_is_prime_ext( const mbedtls_mpi *X, int rounds,
-                              int (*f_rng)(void *, unsigned char *, size_t),
-                              void *p_rng );
-/**
- * \brief Flags for mbedtls_mpi_gen_prime()
- *
- * Each of these flags is a constraint on the result X returned by
- * mbedtls_mpi_gen_prime().
- */
-typedef enum {
-    MBEDTLS_MPI_GEN_PRIME_FLAG_DH =      0x0001, /**< (X-1)/2 is prime too */
-    MBEDTLS_MPI_GEN_PRIME_FLAG_LOW_ERR = 0x0002, /**< lower error rate from 2<sup>-80</sup> to 2<sup>-128</sup> */
-} mbedtls_mpi_gen_prime_flag_t;
-
-/**
- * \brief          Generate a prime number.
- *
- * \param X        The destination MPI to store the generated prime in.
- *                 This must point to an initialized MPi.
- * \param nbits    The required size of the destination MPI in bits.
- *                 This must be between \c 3 and #MBEDTLS_MPI_MAX_BITS.
- * \param flags    A mask of flags of type #mbedtls_mpi_gen_prime_flag_t.
- * \param f_rng    The RNG function to use. This must not be \c NULL.
- * \param p_rng    The RNG parameter to be passed to \p f_rng.
- *                 This may be \c NULL if \p f_rng doesn't use
- *                 a context parameter.
- *
- * \return         \c 0 if successful, in which case \p X holds a
- *                 probably prime number.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed.
- * \return         #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if `nbits` is not between
- *                 \c 3 and #MBEDTLS_MPI_MAX_BITS.
- */
-int mbedtls_mpi_gen_prime( mbedtls_mpi *X, size_t nbits, int flags,
-                   int (*f_rng)(void *, unsigned char *, size_t),
-                   void *p_rng );
-#else /* MBEDTLS_BIGNUM_ALT */
-#include "bignum_alt.h"
-#endif /* MBEDTLS_BIGNUM_ALT */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- */
-int mbedtls_mpi_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* bignum.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/blowfish.h b/tools/sdk/include/mbedtls/mbedtls/blowfish.h
deleted file mode 100644
index d2a1ebdbf41..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/blowfish.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/**
- * \file blowfish.h
- *
- * \brief Blowfish block cipher
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_BLOWFISH_H
-#define MBEDTLS_BLOWFISH_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-#include "platform_util.h"
-
-#define MBEDTLS_BLOWFISH_ENCRYPT     1
-#define MBEDTLS_BLOWFISH_DECRYPT     0
-#define MBEDTLS_BLOWFISH_MAX_KEY_BITS     448
-#define MBEDTLS_BLOWFISH_MIN_KEY_BITS     32
-#define MBEDTLS_BLOWFISH_ROUNDS      16         /**< Rounds to use. When increasing this value, make sure to extend the initialisation vectors */
-#define MBEDTLS_BLOWFISH_BLOCKSIZE   8          /* Blowfish uses 64 bit blocks */
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#define MBEDTLS_ERR_BLOWFISH_INVALID_KEY_LENGTH   MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( -0x0016 )
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-#define MBEDTLS_ERR_BLOWFISH_BAD_INPUT_DATA -0x0016 /**< Bad input data. */
-
-#define MBEDTLS_ERR_BLOWFISH_INVALID_INPUT_LENGTH -0x0018 /**< Invalid data input length. */
-
-/* MBEDTLS_ERR_BLOWFISH_HW_ACCEL_FAILED is deprecated and should not be used.
- */
-#define MBEDTLS_ERR_BLOWFISH_HW_ACCEL_FAILED                   -0x0017  /**< Blowfish hardware accelerator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_BLOWFISH_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          Blowfish context structure
- */
-typedef struct mbedtls_blowfish_context
-{
-    uint32_t P[MBEDTLS_BLOWFISH_ROUNDS + 2];    /*!<  Blowfish round keys    */
-    uint32_t S[4][256];                 /*!<  key dependent S-boxes  */
-}
-mbedtls_blowfish_context;
-
-#else  /* MBEDTLS_BLOWFISH_ALT */
-#include "blowfish_alt.h"
-#endif /* MBEDTLS_BLOWFISH_ALT */
-
-/**
- * \brief          Initialize a Blowfish context.
- *
- * \param ctx      The Blowfish context to be initialized.
- *                 This must not be \c NULL.
- */
-void mbedtls_blowfish_init( mbedtls_blowfish_context *ctx );
-
-/**
- * \brief          Clear a Blowfish context.
- *
- * \param ctx      The Blowfish context to be cleared.
- *                 This may be \c NULL, in which case this function
- *                 returns immediately. If it is not \c NULL, it must
- *                 point to an initialized Blowfish context.
- */
-void mbedtls_blowfish_free( mbedtls_blowfish_context *ctx );
-
-/**
- * \brief          Perform a Blowfish key schedule operation.
- *
- * \param ctx      The Blowfish context to perform the key schedule on.
- * \param key      The encryption key. This must be a readable buffer of
- *                 length \p keybits Bits.
- * \param keybits  The length of \p key in Bits. This must be between
- *                 \c 32 and \c 448 and a multiple of \c 8.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_blowfish_setkey( mbedtls_blowfish_context *ctx, const unsigned char *key,
-                     unsigned int keybits );
-
-/**
- * \brief          Perform a Blowfish-ECB block encryption/decryption operation.
- *
- * \param ctx      The Blowfish context to use. This must be initialized
- *                 and bound to a key.
- * \param mode     The mode of operation. Possible values are
- *                 #MBEDTLS_BLOWFISH_ENCRYPT for encryption, or
- *                 #MBEDTLS_BLOWFISH_DECRYPT for decryption.
- * \param input    The input block. This must be a readable buffer
- *                 of size \c 8 Bytes.
- * \param output   The output block. This must be a writable buffer
- *                 of size \c 8 Bytes.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_blowfish_crypt_ecb( mbedtls_blowfish_context *ctx,
-                        int mode,
-                        const unsigned char input[MBEDTLS_BLOWFISH_BLOCKSIZE],
-                        unsigned char output[MBEDTLS_BLOWFISH_BLOCKSIZE] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          Perform a Blowfish-CBC buffer encryption/decryption operation.
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      The Blowfish context to use. This must be initialized
- *                 and bound to a key.
- * \param mode     The mode of operation. Possible values are
- *                 #MBEDTLS_BLOWFISH_ENCRYPT for encryption, or
- *                 #MBEDTLS_BLOWFISH_DECRYPT for decryption.
- * \param length   The length of the input data in Bytes. This must be
- *                 multiple of \c 8.
- * \param iv       The initialization vector. This must be a read/write buffer
- *                 of length \c 8 Bytes. It is updated by this function.
- * \param input    The input data. This must be a readable buffer of length
- *                 \p length Bytes.
- * \param output   The output data. This must be a writable buffer of length
- *                 \p length Bytes.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_blowfish_crypt_cbc( mbedtls_blowfish_context *ctx,
-                        int mode,
-                        size_t length,
-                        unsigned char iv[MBEDTLS_BLOWFISH_BLOCKSIZE],
-                        const unsigned char *input,
-                        unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-/**
- * \brief          Perform a Blowfish CFB buffer encryption/decryption operation.
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      The Blowfish context to use. This must be initialized
- *                 and bound to a key.
- * \param mode     The mode of operation. Possible values are
- *                 #MBEDTLS_BLOWFISH_ENCRYPT for encryption, or
- *                 #MBEDTLS_BLOWFISH_DECRYPT for decryption.
- * \param length   The length of the input data in Bytes.
- * \param iv_off   The offset in the initialiation vector.
- *                 The value pointed to must be smaller than \c 8 Bytes.
- *                 It is updated by this function to support the aforementioned
- *                 streaming usage.
- * \param iv       The initialization vector. This must be a read/write buffer
- *                 of size \c 8 Bytes. It is updated after use.
- * \param input    The input data. This must be a readable buffer of length
- *                 \p length Bytes.
- * \param output   The output data. This must be a writable buffer of length
- *                 \p length Bytes.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_blowfish_crypt_cfb64( mbedtls_blowfish_context *ctx,
-                          int mode,
-                          size_t length,
-                          size_t *iv_off,
-                          unsigned char iv[MBEDTLS_BLOWFISH_BLOCKSIZE],
-                          const unsigned char *input,
-                          unsigned char *output );
-#endif /*MBEDTLS_CIPHER_MODE_CFB */
-
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-/**
- * \brief      Perform a Blowfish-CTR buffer encryption/decryption operation.
- *
- * \warning    You must never reuse a nonce value with the same key. Doing so
- *             would void the encryption for the two messages encrypted with
- *             the same nonce and key.
- *
- *             There are two common strategies for managing nonces with CTR:
- *
- *             1. You can handle everything as a single message processed over
- *             successive calls to this function. In that case, you want to
- *             set \p nonce_counter and \p nc_off to 0 for the first call, and
- *             then preserve the values of \p nonce_counter, \p nc_off and \p
- *             stream_block across calls to this function as they will be
- *             updated by this function.
- *
- *             With this strategy, you must not encrypt more than 2**64
- *             blocks of data with the same key.
- *
- *             2. You can encrypt separate messages by dividing the \p
- *             nonce_counter buffer in two areas: the first one used for a
- *             per-message nonce, handled by yourself, and the second one
- *             updated by this function internally.
- *
- *             For example, you might reserve the first 4 bytes for the
- *             per-message nonce, and the last 4 bytes for internal use. In that
- *             case, before calling this function on a new message you need to
- *             set the first 4 bytes of \p nonce_counter to your chosen nonce
- *             value, the last 4 to 0, and \p nc_off to 0 (which will cause \p
- *             stream_block to be ignored). That way, you can encrypt at most
- *             2**32 messages of up to 2**32 blocks each with the same key.
- *
- *             The per-message nonce (or information sufficient to reconstruct
- *             it) needs to be communicated with the ciphertext and must be unique.
- *             The recommended way to ensure uniqueness is to use a message
- *             counter.
- *
- *             Note that for both stategies, sizes are measured in blocks and
- *             that a Blowfish block is 8 bytes.
- *
- * \warning    Upon return, \p stream_block contains sensitive data. Its
- *             content must not be written to insecure storage and should be
- *             securely discarded as soon as it's no longer needed.
- *
- * \param ctx           The Blowfish context to use. This must be initialized
- *                      and bound to a key.
- * \param length        The length of the input data in Bytes.
- * \param nc_off        The offset in the current stream_block (for resuming
- *                      within current cipher stream). The offset pointer
- *                      should be \c 0 at the start of a stream and must be
- *                      smaller than \c 8. It is updated by this function.
- * \param nonce_counter The 64-bit nonce and counter. This must point to a
- *                      read/write buffer of length \c 8 Bytes.
- * \param stream_block  The saved stream-block for resuming. This must point to
- *                      a read/write buffer of length \c 8 Bytes.
- * \param input         The input data. This must be a readable buffer of
- *                      length \p length Bytes.
- * \param output        The output data. This must be a writable buffer of
- *                      length \p length Bytes.
- *
- * \return              \c 0 if successful.
- * \return              A negative error code on failure.
- */
-int mbedtls_blowfish_crypt_ctr( mbedtls_blowfish_context *ctx,
-                        size_t length,
-                        size_t *nc_off,
-                        unsigned char nonce_counter[MBEDTLS_BLOWFISH_BLOCKSIZE],
-                        unsigned char stream_block[MBEDTLS_BLOWFISH_BLOCKSIZE],
-                        const unsigned char *input,
-                        unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CTR */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* blowfish.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/bn_mul.h b/tools/sdk/include/mbedtls/mbedtls/bn_mul.h
deleted file mode 100644
index 42339b7b718..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/bn_mul.h
+++ /dev/null
@@ -1,943 +0,0 @@
-/**
- * \file bn_mul.h
- *
- * \brief Multi-precision integer library
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-/*
- *      Multiply source vector [s] with b, add result
- *       to destination vector [d] and set carry c.
- *
- *      Currently supports:
- *
- *         . IA-32 (386+)         . AMD64 / EM64T
- *         . IA-32 (SSE2)         . Motorola 68000
- *         . PowerPC, 32-bit      . MicroBlaze
- *         . PowerPC, 64-bit      . TriCore
- *         . SPARC v8             . ARM v3+
- *         . Alpha                . MIPS32
- *         . C, longlong          . C, generic
- */
-#ifndef MBEDTLS_BN_MUL_H
-#define MBEDTLS_BN_MUL_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "bignum.h"
-
-#if defined(MBEDTLS_HAVE_ASM)
-
-#ifndef asm
-#define asm __asm
-#endif
-
-/* armcc5 --gnu defines __GNUC__ but doesn't support GNU's extended asm */
-#if defined(__GNUC__) && \
-    ( !defined(__ARMCC_VERSION) || __ARMCC_VERSION >= 6000000 )
-
-/*
- * Disable use of the i386 assembly code below if option -O0, to disable all
- * compiler optimisations, is passed, detected with __OPTIMIZE__
- * This is done as the number of registers used in the assembly code doesn't
- * work with the -O0 option.
- */
-#if defined(__i386__) && defined(__OPTIMIZE__)
-
-#define MULADDC_INIT                        \
-    asm(                                    \
-        "movl   %%ebx, %0           \n\t"   \
-        "movl   %5, %%esi           \n\t"   \
-        "movl   %6, %%edi           \n\t"   \
-        "movl   %7, %%ecx           \n\t"   \
-        "movl   %8, %%ebx           \n\t"
-
-#define MULADDC_CORE                        \
-        "lodsl                      \n\t"   \
-        "mull   %%ebx               \n\t"   \
-        "addl   %%ecx,   %%eax      \n\t"   \
-        "adcl   $0,      %%edx      \n\t"   \
-        "addl   (%%edi), %%eax      \n\t"   \
-        "adcl   $0,      %%edx      \n\t"   \
-        "movl   %%edx,   %%ecx      \n\t"   \
-        "stosl                      \n\t"
-
-#if defined(MBEDTLS_HAVE_SSE2)
-
-#define MULADDC_HUIT                            \
-        "movd     %%ecx,     %%mm1      \n\t"   \
-        "movd     %%ebx,     %%mm0      \n\t"   \
-        "movd     (%%edi),   %%mm3      \n\t"   \
-        "paddq    %%mm3,     %%mm1      \n\t"   \
-        "movd     (%%esi),   %%mm2      \n\t"   \
-        "pmuludq  %%mm0,     %%mm2      \n\t"   \
-        "movd     4(%%esi),  %%mm4      \n\t"   \
-        "pmuludq  %%mm0,     %%mm4      \n\t"   \
-        "movd     8(%%esi),  %%mm6      \n\t"   \
-        "pmuludq  %%mm0,     %%mm6      \n\t"   \
-        "movd     12(%%esi), %%mm7      \n\t"   \
-        "pmuludq  %%mm0,     %%mm7      \n\t"   \
-        "paddq    %%mm2,     %%mm1      \n\t"   \
-        "movd     4(%%edi),  %%mm3      \n\t"   \
-        "paddq    %%mm4,     %%mm3      \n\t"   \
-        "movd     8(%%edi),  %%mm5      \n\t"   \
-        "paddq    %%mm6,     %%mm5      \n\t"   \
-        "movd     12(%%edi), %%mm4      \n\t"   \
-        "paddq    %%mm4,     %%mm7      \n\t"   \
-        "movd     %%mm1,     (%%edi)    \n\t"   \
-        "movd     16(%%esi), %%mm2      \n\t"   \
-        "pmuludq  %%mm0,     %%mm2      \n\t"   \
-        "psrlq    $32,       %%mm1      \n\t"   \
-        "movd     20(%%esi), %%mm4      \n\t"   \
-        "pmuludq  %%mm0,     %%mm4      \n\t"   \
-        "paddq    %%mm3,     %%mm1      \n\t"   \
-        "movd     24(%%esi), %%mm6      \n\t"   \
-        "pmuludq  %%mm0,     %%mm6      \n\t"   \
-        "movd     %%mm1,     4(%%edi)   \n\t"   \
-        "psrlq    $32,       %%mm1      \n\t"   \
-        "movd     28(%%esi), %%mm3      \n\t"   \
-        "pmuludq  %%mm0,     %%mm3      \n\t"   \
-        "paddq    %%mm5,     %%mm1      \n\t"   \
-        "movd     16(%%edi), %%mm5      \n\t"   \
-        "paddq    %%mm5,     %%mm2      \n\t"   \
-        "movd     %%mm1,     8(%%edi)   \n\t"   \
-        "psrlq    $32,       %%mm1      \n\t"   \
-        "paddq    %%mm7,     %%mm1      \n\t"   \
-        "movd     20(%%edi), %%mm5      \n\t"   \
-        "paddq    %%mm5,     %%mm4      \n\t"   \
-        "movd     %%mm1,     12(%%edi)  \n\t"   \
-        "psrlq    $32,       %%mm1      \n\t"   \
-        "paddq    %%mm2,     %%mm1      \n\t"   \
-        "movd     24(%%edi), %%mm5      \n\t"   \
-        "paddq    %%mm5,     %%mm6      \n\t"   \
-        "movd     %%mm1,     16(%%edi)  \n\t"   \
-        "psrlq    $32,       %%mm1      \n\t"   \
-        "paddq    %%mm4,     %%mm1      \n\t"   \
-        "movd     28(%%edi), %%mm5      \n\t"   \
-        "paddq    %%mm5,     %%mm3      \n\t"   \
-        "movd     %%mm1,     20(%%edi)  \n\t"   \
-        "psrlq    $32,       %%mm1      \n\t"   \
-        "paddq    %%mm6,     %%mm1      \n\t"   \
-        "movd     %%mm1,     24(%%edi)  \n\t"   \
-        "psrlq    $32,       %%mm1      \n\t"   \
-        "paddq    %%mm3,     %%mm1      \n\t"   \
-        "movd     %%mm1,     28(%%edi)  \n\t"   \
-        "addl     $32,       %%edi      \n\t"   \
-        "addl     $32,       %%esi      \n\t"   \
-        "psrlq    $32,       %%mm1      \n\t"   \
-        "movd     %%mm1,     %%ecx      \n\t"
-
-#define MULADDC_STOP                    \
-        "emms                   \n\t"   \
-        "movl   %4, %%ebx       \n\t"   \
-        "movl   %%ecx, %1       \n\t"   \
-        "movl   %%edi, %2       \n\t"   \
-        "movl   %%esi, %3       \n\t"   \
-        : "=m" (t), "=m" (c), "=m" (d), "=m" (s)        \
-        : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b)   \
-        : "eax", "ebx", "ecx", "edx", "esi", "edi"      \
-    );
-
-#else
-
-#define MULADDC_STOP                    \
-        "movl   %4, %%ebx       \n\t"   \
-        "movl   %%ecx, %1       \n\t"   \
-        "movl   %%edi, %2       \n\t"   \
-        "movl   %%esi, %3       \n\t"   \
-        : "=m" (t), "=m" (c), "=m" (d), "=m" (s)        \
-        : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b)   \
-        : "eax", "ebx", "ecx", "edx", "esi", "edi"      \
-    );
-#endif /* SSE2 */
-#endif /* i386 */
-
-#if defined(__amd64__) || defined (__x86_64__)
-
-#define MULADDC_INIT                        \
-    asm(                                    \
-        "xorq   %%r8, %%r8\n"
-
-#define MULADDC_CORE                        \
-        "movq   (%%rsi), %%rax\n"           \
-        "mulq   %%rbx\n"                    \
-        "addq   $8, %%rsi\n"                \
-        "addq   %%rcx, %%rax\n"             \
-        "movq   %%r8, %%rcx\n"              \
-        "adcq   $0, %%rdx\n"                \
-        "nop    \n"                         \
-        "addq   %%rax, (%%rdi)\n"           \
-        "adcq   %%rdx, %%rcx\n"             \
-        "addq   $8, %%rdi\n"
-
-#define MULADDC_STOP                        \
-        : "+c" (c), "+D" (d), "+S" (s)      \
-        : "b" (b)                           \
-        : "rax", "rdx", "r8"                \
-    );
-
-#endif /* AMD64 */
-
-#if defined(__mc68020__) || defined(__mcpu32__)
-
-#define MULADDC_INIT                    \
-    asm(                                \
-        "movl   %3, %%a2        \n\t"   \
-        "movl   %4, %%a3        \n\t"   \
-        "movl   %5, %%d3        \n\t"   \
-        "movl   %6, %%d2        \n\t"   \
-        "moveq  #0, %%d0        \n\t"
-
-#define MULADDC_CORE                    \
-        "movel  %%a2@+, %%d1    \n\t"   \
-        "mulul  %%d2, %%d4:%%d1 \n\t"   \
-        "addl   %%d3, %%d1      \n\t"   \
-        "addxl  %%d0, %%d4      \n\t"   \
-        "moveq  #0,   %%d3      \n\t"   \
-        "addl   %%d1, %%a3@+    \n\t"   \
-        "addxl  %%d4, %%d3      \n\t"
-
-#define MULADDC_STOP                    \
-        "movl   %%d3, %0        \n\t"   \
-        "movl   %%a3, %1        \n\t"   \
-        "movl   %%a2, %2        \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)              \
-        : "m" (s), "m" (d), "m" (c), "m" (b)        \
-        : "d0", "d1", "d2", "d3", "d4", "a2", "a3"  \
-    );
-
-#define MULADDC_HUIT                        \
-        "movel  %%a2@+,  %%d1       \n\t"   \
-        "mulul  %%d2,    %%d4:%%d1  \n\t"   \
-        "addxl  %%d3,    %%d1       \n\t"   \
-        "addxl  %%d0,    %%d4       \n\t"   \
-        "addl   %%d1,    %%a3@+     \n\t"   \
-        "movel  %%a2@+,  %%d1       \n\t"   \
-        "mulul  %%d2,    %%d3:%%d1  \n\t"   \
-        "addxl  %%d4,    %%d1       \n\t"   \
-        "addxl  %%d0,    %%d3       \n\t"   \
-        "addl   %%d1,    %%a3@+     \n\t"   \
-        "movel  %%a2@+,  %%d1       \n\t"   \
-        "mulul  %%d2,    %%d4:%%d1  \n\t"   \
-        "addxl  %%d3,    %%d1       \n\t"   \
-        "addxl  %%d0,    %%d4       \n\t"   \
-        "addl   %%d1,    %%a3@+     \n\t"   \
-        "movel  %%a2@+,  %%d1       \n\t"   \
-        "mulul  %%d2,    %%d3:%%d1  \n\t"   \
-        "addxl  %%d4,    %%d1       \n\t"   \
-        "addxl  %%d0,    %%d3       \n\t"   \
-        "addl   %%d1,    %%a3@+     \n\t"   \
-        "movel  %%a2@+,  %%d1       \n\t"   \
-        "mulul  %%d2,    %%d4:%%d1  \n\t"   \
-        "addxl  %%d3,    %%d1       \n\t"   \
-        "addxl  %%d0,    %%d4       \n\t"   \
-        "addl   %%d1,    %%a3@+     \n\t"   \
-        "movel  %%a2@+,  %%d1       \n\t"   \
-        "mulul  %%d2,    %%d3:%%d1  \n\t"   \
-        "addxl  %%d4,    %%d1       \n\t"   \
-        "addxl  %%d0,    %%d3       \n\t"   \
-        "addl   %%d1,    %%a3@+     \n\t"   \
-        "movel  %%a2@+,  %%d1       \n\t"   \
-        "mulul  %%d2,    %%d4:%%d1  \n\t"   \
-        "addxl  %%d3,    %%d1       \n\t"   \
-        "addxl  %%d0,    %%d4       \n\t"   \
-        "addl   %%d1,    %%a3@+     \n\t"   \
-        "movel  %%a2@+,  %%d1       \n\t"   \
-        "mulul  %%d2,    %%d3:%%d1  \n\t"   \
-        "addxl  %%d4,    %%d1       \n\t"   \
-        "addxl  %%d0,    %%d3       \n\t"   \
-        "addl   %%d1,    %%a3@+     \n\t"   \
-        "addxl  %%d0,    %%d3       \n\t"
-
-#endif /* MC68000 */
-
-#if defined(__powerpc64__) || defined(__ppc64__)
-
-#if defined(__MACH__) && defined(__APPLE__)
-
-#define MULADDC_INIT                        \
-    asm(                                    \
-        "ld     r3, %3              \n\t"   \
-        "ld     r4, %4              \n\t"   \
-        "ld     r5, %5              \n\t"   \
-        "ld     r6, %6              \n\t"   \
-        "addi   r3, r3, -8          \n\t"   \
-        "addi   r4, r4, -8          \n\t"   \
-        "addic  r5, r5,  0          \n\t"
-
-#define MULADDC_CORE                        \
-        "ldu    r7, 8(r3)           \n\t"   \
-        "mulld  r8, r7, r6          \n\t"   \
-        "mulhdu r9, r7, r6          \n\t"   \
-        "adde   r8, r8, r5          \n\t"   \
-        "ld     r7, 8(r4)           \n\t"   \
-        "addze  r5, r9              \n\t"   \
-        "addc   r8, r8, r7          \n\t"   \
-        "stdu   r8, 8(r4)           \n\t"
-
-#define MULADDC_STOP                        \
-        "addze  r5, r5              \n\t"   \
-        "addi   r4, r4, 8           \n\t"   \
-        "addi   r3, r3, 8           \n\t"   \
-        "std    r5, %0              \n\t"   \
-        "std    r4, %1              \n\t"   \
-        "std    r3, %2              \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)              \
-        : "m" (s), "m" (d), "m" (c), "m" (b)        \
-        : "r3", "r4", "r5", "r6", "r7", "r8", "r9"  \
-    );
-
-
-#else /* __MACH__ && __APPLE__ */
-
-#define MULADDC_INIT                        \
-    asm(                                    \
-        "ld     %%r3, %3            \n\t"   \
-        "ld     %%r4, %4            \n\t"   \
-        "ld     %%r5, %5            \n\t"   \
-        "ld     %%r6, %6            \n\t"   \
-        "addi   %%r3, %%r3, -8      \n\t"   \
-        "addi   %%r4, %%r4, -8      \n\t"   \
-        "addic  %%r5, %%r5,  0      \n\t"
-
-#define MULADDC_CORE                        \
-        "ldu    %%r7, 8(%%r3)       \n\t"   \
-        "mulld  %%r8, %%r7, %%r6    \n\t"   \
-        "mulhdu %%r9, %%r7, %%r6    \n\t"   \
-        "adde   %%r8, %%r8, %%r5    \n\t"   \
-        "ld     %%r7, 8(%%r4)       \n\t"   \
-        "addze  %%r5, %%r9          \n\t"   \
-        "addc   %%r8, %%r8, %%r7    \n\t"   \
-        "stdu   %%r8, 8(%%r4)       \n\t"
-
-#define MULADDC_STOP                        \
-        "addze  %%r5, %%r5          \n\t"   \
-        "addi   %%r4, %%r4, 8       \n\t"   \
-        "addi   %%r3, %%r3, 8       \n\t"   \
-        "std    %%r5, %0            \n\t"   \
-        "std    %%r4, %1            \n\t"   \
-        "std    %%r3, %2            \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)              \
-        : "m" (s), "m" (d), "m" (c), "m" (b)        \
-        : "r3", "r4", "r5", "r6", "r7", "r8", "r9"  \
-    );
-
-#endif /* __MACH__ && __APPLE__ */
-
-#elif defined(__powerpc__) || defined(__ppc__) /* end PPC64/begin PPC32  */
-
-#if defined(__MACH__) && defined(__APPLE__)
-
-#define MULADDC_INIT                    \
-    asm(                                \
-        "lwz    r3, %3          \n\t"   \
-        "lwz    r4, %4          \n\t"   \
-        "lwz    r5, %5          \n\t"   \
-        "lwz    r6, %6          \n\t"   \
-        "addi   r3, r3, -4      \n\t"   \
-        "addi   r4, r4, -4      \n\t"   \
-        "addic  r5, r5,  0      \n\t"
-
-#define MULADDC_CORE                    \
-        "lwzu   r7, 4(r3)       \n\t"   \
-        "mullw  r8, r7, r6      \n\t"   \
-        "mulhwu r9, r7, r6      \n\t"   \
-        "adde   r8, r8, r5      \n\t"   \
-        "lwz    r7, 4(r4)       \n\t"   \
-        "addze  r5, r9          \n\t"   \
-        "addc   r8, r8, r7      \n\t"   \
-        "stwu   r8, 4(r4)       \n\t"
-
-#define MULADDC_STOP                    \
-        "addze  r5, r5          \n\t"   \
-        "addi   r4, r4, 4       \n\t"   \
-        "addi   r3, r3, 4       \n\t"   \
-        "stw    r5, %0          \n\t"   \
-        "stw    r4, %1          \n\t"   \
-        "stw    r3, %2          \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)              \
-        : "m" (s), "m" (d), "m" (c), "m" (b)        \
-        : "r3", "r4", "r5", "r6", "r7", "r8", "r9"  \
-    );
-
-#else /* __MACH__ && __APPLE__ */
-
-#define MULADDC_INIT                        \
-    asm(                                    \
-        "lwz    %%r3, %3            \n\t"   \
-        "lwz    %%r4, %4            \n\t"   \
-        "lwz    %%r5, %5            \n\t"   \
-        "lwz    %%r6, %6            \n\t"   \
-        "addi   %%r3, %%r3, -4      \n\t"   \
-        "addi   %%r4, %%r4, -4      \n\t"   \
-        "addic  %%r5, %%r5,  0      \n\t"
-
-#define MULADDC_CORE                        \
-        "lwzu   %%r7, 4(%%r3)       \n\t"   \
-        "mullw  %%r8, %%r7, %%r6    \n\t"   \
-        "mulhwu %%r9, %%r7, %%r6    \n\t"   \
-        "adde   %%r8, %%r8, %%r5    \n\t"   \
-        "lwz    %%r7, 4(%%r4)       \n\t"   \
-        "addze  %%r5, %%r9          \n\t"   \
-        "addc   %%r8, %%r8, %%r7    \n\t"   \
-        "stwu   %%r8, 4(%%r4)       \n\t"
-
-#define MULADDC_STOP                        \
-        "addze  %%r5, %%r5          \n\t"   \
-        "addi   %%r4, %%r4, 4       \n\t"   \
-        "addi   %%r3, %%r3, 4       \n\t"   \
-        "stw    %%r5, %0            \n\t"   \
-        "stw    %%r4, %1            \n\t"   \
-        "stw    %%r3, %2            \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)              \
-        : "m" (s), "m" (d), "m" (c), "m" (b)        \
-        : "r3", "r4", "r5", "r6", "r7", "r8", "r9"  \
-    );
-
-#endif /* __MACH__ && __APPLE__ */
-
-#endif /* PPC32 */
-
-/*
- * The Sparc(64) assembly is reported to be broken.
- * Disable it for now, until we're able to fix it.
- */
-#if 0 && defined(__sparc__)
-#if defined(__sparc64__)
-
-#define MULADDC_INIT                                    \
-    asm(                                                \
-                "ldx     %3, %%o0               \n\t"   \
-                "ldx     %4, %%o1               \n\t"   \
-                "ld      %5, %%o2               \n\t"   \
-                "ld      %6, %%o3               \n\t"
-
-#define MULADDC_CORE                                    \
-                "ld      [%%o0], %%o4           \n\t"   \
-                "inc     4, %%o0                \n\t"   \
-                "ld      [%%o1], %%o5           \n\t"   \
-                "umul    %%o3, %%o4, %%o4       \n\t"   \
-                "addcc   %%o4, %%o2, %%o4       \n\t"   \
-                "rd      %%y, %%g1              \n\t"   \
-                "addx    %%g1, 0, %%g1          \n\t"   \
-                "addcc   %%o4, %%o5, %%o4       \n\t"   \
-                "st      %%o4, [%%o1]           \n\t"   \
-                "addx    %%g1, 0, %%o2          \n\t"   \
-                "inc     4, %%o1                \n\t"
-
-        #define MULADDC_STOP                            \
-                "st      %%o2, %0               \n\t"   \
-                "stx     %%o1, %1               \n\t"   \
-                "stx     %%o0, %2               \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)          \
-        : "m" (s), "m" (d), "m" (c), "m" (b)    \
-        : "g1", "o0", "o1", "o2", "o3", "o4",   \
-          "o5"                                  \
-        );
-
-#else /* __sparc64__ */
-
-#define MULADDC_INIT                                    \
-    asm(                                                \
-                "ld      %3, %%o0               \n\t"   \
-                "ld      %4, %%o1               \n\t"   \
-                "ld      %5, %%o2               \n\t"   \
-                "ld      %6, %%o3               \n\t"
-
-#define MULADDC_CORE                                    \
-                "ld      [%%o0], %%o4           \n\t"   \
-                "inc     4, %%o0                \n\t"   \
-                "ld      [%%o1], %%o5           \n\t"   \
-                "umul    %%o3, %%o4, %%o4       \n\t"   \
-                "addcc   %%o4, %%o2, %%o4       \n\t"   \
-                "rd      %%y, %%g1              \n\t"   \
-                "addx    %%g1, 0, %%g1          \n\t"   \
-                "addcc   %%o4, %%o5, %%o4       \n\t"   \
-                "st      %%o4, [%%o1]           \n\t"   \
-                "addx    %%g1, 0, %%o2          \n\t"   \
-                "inc     4, %%o1                \n\t"
-
-#define MULADDC_STOP                                    \
-                "st      %%o2, %0               \n\t"   \
-                "st      %%o1, %1               \n\t"   \
-                "st      %%o0, %2               \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)          \
-        : "m" (s), "m" (d), "m" (c), "m" (b)    \
-        : "g1", "o0", "o1", "o2", "o3", "o4",   \
-          "o5"                                  \
-        );
-
-#endif /* __sparc64__ */
-#endif /* __sparc__ */
-
-#if defined(__microblaze__) || defined(microblaze)
-
-#define MULADDC_INIT                    \
-    asm(                                \
-        "lwi   r3,   %3         \n\t"   \
-        "lwi   r4,   %4         \n\t"   \
-        "lwi   r5,   %5         \n\t"   \
-        "lwi   r6,   %6         \n\t"   \
-        "andi  r7,   r6, 0xffff \n\t"   \
-        "bsrli r6,   r6, 16     \n\t"
-
-#define MULADDC_CORE                    \
-        "lhui  r8,   r3,   0    \n\t"   \
-        "addi  r3,   r3,   2    \n\t"   \
-        "lhui  r9,   r3,   0    \n\t"   \
-        "addi  r3,   r3,   2    \n\t"   \
-        "mul   r10,  r9,  r6    \n\t"   \
-        "mul   r11,  r8,  r7    \n\t"   \
-        "mul   r12,  r9,  r7    \n\t"   \
-        "mul   r13,  r8,  r6    \n\t"   \
-        "bsrli  r8, r10,  16    \n\t"   \
-        "bsrli  r9, r11,  16    \n\t"   \
-        "add   r13, r13,  r8    \n\t"   \
-        "add   r13, r13,  r9    \n\t"   \
-        "bslli r10, r10,  16    \n\t"   \
-        "bslli r11, r11,  16    \n\t"   \
-        "add   r12, r12, r10    \n\t"   \
-        "addc  r13, r13,  r0    \n\t"   \
-        "add   r12, r12, r11    \n\t"   \
-        "addc  r13, r13,  r0    \n\t"   \
-        "lwi   r10,  r4,   0    \n\t"   \
-        "add   r12, r12, r10    \n\t"   \
-        "addc  r13, r13,  r0    \n\t"   \
-        "add   r12, r12,  r5    \n\t"   \
-        "addc   r5, r13,  r0    \n\t"   \
-        "swi   r12,  r4,   0    \n\t"   \
-        "addi   r4,  r4,   4    \n\t"
-
-#define MULADDC_STOP                    \
-        "swi   r5,   %0         \n\t"   \
-        "swi   r4,   %1         \n\t"   \
-        "swi   r3,   %2         \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)              \
-        : "m" (s), "m" (d), "m" (c), "m" (b)        \
-        : "r3", "r4", "r5", "r6", "r7", "r8",       \
-          "r9", "r10", "r11", "r12", "r13"          \
-    );
-
-#endif /* MicroBlaze */
-
-#if defined(__tricore__)
-
-#define MULADDC_INIT                            \
-    asm(                                        \
-        "ld.a   %%a2, %3                \n\t"   \
-        "ld.a   %%a3, %4                \n\t"   \
-        "ld.w   %%d4, %5                \n\t"   \
-        "ld.w   %%d1, %6                \n\t"   \
-        "xor    %%d5, %%d5              \n\t"
-
-#define MULADDC_CORE                            \
-        "ld.w   %%d0,   [%%a2+]         \n\t"   \
-        "madd.u %%e2, %%e4, %%d0, %%d1  \n\t"   \
-        "ld.w   %%d0,   [%%a3]          \n\t"   \
-        "addx   %%d2,    %%d2,  %%d0    \n\t"   \
-        "addc   %%d3,    %%d3,    0     \n\t"   \
-        "mov    %%d4,    %%d3           \n\t"   \
-        "st.w  [%%a3+],  %%d2           \n\t"
-
-#define MULADDC_STOP                            \
-        "st.w   %0, %%d4                \n\t"   \
-        "st.a   %1, %%a3                \n\t"   \
-        "st.a   %2, %%a2                \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)          \
-        : "m" (s), "m" (d), "m" (c), "m" (b)    \
-        : "d0", "d1", "e2", "d4", "a2", "a3"    \
-    );
-
-#endif /* TriCore */
-
-/*
- * Note, gcc -O0 by default uses r7 for the frame pointer, so it complains about
- * our use of r7 below, unless -fomit-frame-pointer is passed.
- *
- * On the other hand, -fomit-frame-pointer is implied by any -Ox options with
- * x !=0, which we can detect using __OPTIMIZE__ (which is also defined by
- * clang and armcc5 under the same conditions).
- *
- * So, only use the optimized assembly below for optimized build, which avoids
- * the build error and is pretty reasonable anyway.
- */
-#if defined(__GNUC__) && !defined(__OPTIMIZE__)
-#define MULADDC_CANNOT_USE_R7
-#endif
-
-#if defined(__arm__) && !defined(MULADDC_CANNOT_USE_R7)
-
-#if defined(__thumb__) && !defined(__thumb2__)
-
-#define MULADDC_INIT                                    \
-    asm(                                                \
-            "ldr    r0, %3                      \n\t"   \
-            "ldr    r1, %4                      \n\t"   \
-            "ldr    r2, %5                      \n\t"   \
-            "ldr    r3, %6                      \n\t"   \
-            "lsr    r7, r3, #16                 \n\t"   \
-            "mov    r9, r7                      \n\t"   \
-            "lsl    r7, r3, #16                 \n\t"   \
-            "lsr    r7, r7, #16                 \n\t"   \
-            "mov    r8, r7                      \n\t"
-
-#define MULADDC_CORE                                    \
-            "ldmia  r0!, {r6}                   \n\t"   \
-            "lsr    r7, r6, #16                 \n\t"   \
-            "lsl    r6, r6, #16                 \n\t"   \
-            "lsr    r6, r6, #16                 \n\t"   \
-            "mov    r4, r8                      \n\t"   \
-            "mul    r4, r6                      \n\t"   \
-            "mov    r3, r9                      \n\t"   \
-            "mul    r6, r3                      \n\t"   \
-            "mov    r5, r9                      \n\t"   \
-            "mul    r5, r7                      \n\t"   \
-            "mov    r3, r8                      \n\t"   \
-            "mul    r7, r3                      \n\t"   \
-            "lsr    r3, r6, #16                 \n\t"   \
-            "add    r5, r5, r3                  \n\t"   \
-            "lsr    r3, r7, #16                 \n\t"   \
-            "add    r5, r5, r3                  \n\t"   \
-            "add    r4, r4, r2                  \n\t"   \
-            "mov    r2, #0                      \n\t"   \
-            "adc    r5, r2                      \n\t"   \
-            "lsl    r3, r6, #16                 \n\t"   \
-            "add    r4, r4, r3                  \n\t"   \
-            "adc    r5, r2                      \n\t"   \
-            "lsl    r3, r7, #16                 \n\t"   \
-            "add    r4, r4, r3                  \n\t"   \
-            "adc    r5, r2                      \n\t"   \
-            "ldr    r3, [r1]                    \n\t"   \
-            "add    r4, r4, r3                  \n\t"   \
-            "adc    r2, r5                      \n\t"   \
-            "stmia  r1!, {r4}                   \n\t"
-
-#define MULADDC_STOP                                    \
-            "str    r2, %0                      \n\t"   \
-            "str    r1, %1                      \n\t"   \
-            "str    r0, %2                      \n\t"   \
-         : "=m" (c),  "=m" (d), "=m" (s)        \
-         : "m" (s), "m" (d), "m" (c), "m" (b)   \
-         : "r0", "r1", "r2", "r3", "r4", "r5",  \
-           "r6", "r7", "r8", "r9", "cc"         \
-         );
-
-#elif (__ARM_ARCH >= 6) && \
-    defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)
-
-#define MULADDC_INIT                            \
-    asm(
-
-#define MULADDC_CORE                            \
-            "ldr    r0, [%0], #4        \n\t"   \
-            "ldr    r1, [%1]            \n\t"   \
-            "umaal  r1, %2, %3, r0      \n\t"   \
-            "str    r1, [%1], #4        \n\t"
-
-#define MULADDC_STOP                            \
-         : "=r" (s),  "=r" (d), "=r" (c)        \
-         : "r" (b), "0" (s), "1" (d), "2" (c)   \
-         : "r0", "r1", "memory"                 \
-         );
-
-#else
-
-#define MULADDC_INIT                                    \
-    asm(                                                \
-            "ldr    r0, %3                      \n\t"   \
-            "ldr    r1, %4                      \n\t"   \
-            "ldr    r2, %5                      \n\t"   \
-            "ldr    r3, %6                      \n\t"
-
-#define MULADDC_CORE                                    \
-            "ldr    r4, [r0], #4                \n\t"   \
-            "mov    r5, #0                      \n\t"   \
-            "ldr    r6, [r1]                    \n\t"   \
-            "umlal  r2, r5, r3, r4              \n\t"   \
-            "adds   r7, r6, r2                  \n\t"   \
-            "adc    r2, r5, #0                  \n\t"   \
-            "str    r7, [r1], #4                \n\t"
-
-#define MULADDC_STOP                                    \
-            "str    r2, %0                      \n\t"   \
-            "str    r1, %1                      \n\t"   \
-            "str    r0, %2                      \n\t"   \
-         : "=m" (c),  "=m" (d), "=m" (s)        \
-         : "m" (s), "m" (d), "m" (c), "m" (b)   \
-         : "r0", "r1", "r2", "r3", "r4", "r5",  \
-           "r6", "r7", "cc"                     \
-         );
-
-#endif /* Thumb */
-
-#endif /* ARMv3 */
-
-#if defined(__alpha__)
-
-#define MULADDC_INIT                    \
-    asm(                                \
-        "ldq    $1, %3          \n\t"   \
-        "ldq    $2, %4          \n\t"   \
-        "ldq    $3, %5          \n\t"   \
-        "ldq    $4, %6          \n\t"
-
-#define MULADDC_CORE                    \
-        "ldq    $6,  0($1)      \n\t"   \
-        "addq   $1,  8, $1      \n\t"   \
-        "mulq   $6, $4, $7      \n\t"   \
-        "umulh  $6, $4, $6      \n\t"   \
-        "addq   $7, $3, $7      \n\t"   \
-        "cmpult $7, $3, $3      \n\t"   \
-        "ldq    $5,  0($2)      \n\t"   \
-        "addq   $7, $5, $7      \n\t"   \
-        "cmpult $7, $5, $5      \n\t"   \
-        "stq    $7,  0($2)      \n\t"   \
-        "addq   $2,  8, $2      \n\t"   \
-        "addq   $6, $3, $3      \n\t"   \
-        "addq   $5, $3, $3      \n\t"
-
-#define MULADDC_STOP                                    \
-        "stq    $3, %0          \n\t"   \
-        "stq    $2, %1          \n\t"   \
-        "stq    $1, %2          \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)              \
-        : "m" (s), "m" (d), "m" (c), "m" (b)        \
-        : "$1", "$2", "$3", "$4", "$5", "$6", "$7"  \
-    );
-#endif /* Alpha */
-
-#if defined(__mips__) && !defined(__mips64)
-
-#define MULADDC_INIT                    \
-    asm(                                \
-        "lw     $10, %3         \n\t"   \
-        "lw     $11, %4         \n\t"   \
-        "lw     $12, %5         \n\t"   \
-        "lw     $13, %6         \n\t"
-
-#define MULADDC_CORE                    \
-        "lw     $14, 0($10)     \n\t"   \
-        "multu  $13, $14        \n\t"   \
-        "addi   $10, $10, 4     \n\t"   \
-        "mflo   $14             \n\t"   \
-        "mfhi   $9              \n\t"   \
-        "addu   $14, $12, $14   \n\t"   \
-        "lw     $15, 0($11)     \n\t"   \
-        "sltu   $12, $14, $12   \n\t"   \
-        "addu   $15, $14, $15   \n\t"   \
-        "sltu   $14, $15, $14   \n\t"   \
-        "addu   $12, $12, $9    \n\t"   \
-        "sw     $15, 0($11)     \n\t"   \
-        "addu   $12, $12, $14   \n\t"   \
-        "addi   $11, $11, 4     \n\t"
-
-#define MULADDC_STOP                    \
-        "sw     $12, %0         \n\t"   \
-        "sw     $11, %1         \n\t"   \
-        "sw     $10, %2         \n\t"   \
-        : "=m" (c), "=m" (d), "=m" (s)                      \
-        : "m" (s), "m" (d), "m" (c), "m" (b)                \
-        : "$9", "$10", "$11", "$12", "$13", "$14", "$15", "lo", "hi" \
-    );
-
-#endif /* MIPS */
-#endif /* GNUC */
-
-#if (defined(_MSC_VER) && defined(_M_IX86)) || defined(__WATCOMC__)
-
-#define MULADDC_INIT                            \
-    __asm   mov     esi, s                      \
-    __asm   mov     edi, d                      \
-    __asm   mov     ecx, c                      \
-    __asm   mov     ebx, b
-
-#define MULADDC_CORE                            \
-    __asm   lodsd                               \
-    __asm   mul     ebx                         \
-    __asm   add     eax, ecx                    \
-    __asm   adc     edx, 0                      \
-    __asm   add     eax, [edi]                  \
-    __asm   adc     edx, 0                      \
-    __asm   mov     ecx, edx                    \
-    __asm   stosd
-
-#if defined(MBEDTLS_HAVE_SSE2)
-
-#define EMIT __asm _emit
-
-#define MULADDC_HUIT                            \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0xC9             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0xC3             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x1F             \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xCB             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x16             \
-    EMIT 0x0F  EMIT 0xF4  EMIT 0xD0             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x66  EMIT 0x04  \
-    EMIT 0x0F  EMIT 0xF4  EMIT 0xE0             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x76  EMIT 0x08  \
-    EMIT 0x0F  EMIT 0xF4  EMIT 0xF0             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x7E  EMIT 0x0C  \
-    EMIT 0x0F  EMIT 0xF4  EMIT 0xF8             \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xCA             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x5F  EMIT 0x04  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xDC             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x08  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xEE             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x67  EMIT 0x0C  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xFC             \
-    EMIT 0x0F  EMIT 0x7E  EMIT 0x0F             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x56  EMIT 0x10  \
-    EMIT 0x0F  EMIT 0xF4  EMIT 0xD0             \
-    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x66  EMIT 0x14  \
-    EMIT 0x0F  EMIT 0xF4  EMIT 0xE0             \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xCB             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x76  EMIT 0x18  \
-    EMIT 0x0F  EMIT 0xF4  EMIT 0xF0             \
-    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x04  \
-    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x5E  EMIT 0x1C  \
-    EMIT 0x0F  EMIT 0xF4  EMIT 0xD8             \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xCD             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x10  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xD5             \
-    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x08  \
-    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xCF             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x14  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xE5             \
-    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x0C  \
-    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xCA             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x18  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xF5             \
-    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x10  \
-    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xCC             \
-    EMIT 0x0F  EMIT 0x6E  EMIT 0x6F  EMIT 0x1C  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xDD             \
-    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x14  \
-    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xCE             \
-    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x18  \
-    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
-    EMIT 0x0F  EMIT 0xD4  EMIT 0xCB             \
-    EMIT 0x0F  EMIT 0x7E  EMIT 0x4F  EMIT 0x1C  \
-    EMIT 0x83  EMIT 0xC7  EMIT 0x20             \
-    EMIT 0x83  EMIT 0xC6  EMIT 0x20             \
-    EMIT 0x0F  EMIT 0x73  EMIT 0xD1  EMIT 0x20  \
-    EMIT 0x0F  EMIT 0x7E  EMIT 0xC9
-
-#define MULADDC_STOP                            \
-    EMIT 0x0F  EMIT 0x77                        \
-    __asm   mov     c, ecx                      \
-    __asm   mov     d, edi                      \
-    __asm   mov     s, esi                      \
-
-#else
-
-#define MULADDC_STOP                            \
-    __asm   mov     c, ecx                      \
-    __asm   mov     d, edi                      \
-    __asm   mov     s, esi                      \
-
-#endif /* SSE2 */
-#endif /* MSVC */
-
-#endif /* MBEDTLS_HAVE_ASM */
-
-#if !defined(MULADDC_CORE)
-#if defined(MBEDTLS_HAVE_UDBL)
-
-#define MULADDC_INIT                    \
-{                                       \
-    mbedtls_t_udbl r;                           \
-    mbedtls_mpi_uint r0, r1;
-
-#define MULADDC_CORE                    \
-    r   = *(s++) * (mbedtls_t_udbl) b;          \
-    r0  = (mbedtls_mpi_uint) r;                   \
-    r1  = (mbedtls_mpi_uint)( r >> biL );         \
-    r0 += c;  r1 += (r0 <  c);          \
-    r0 += *d; r1 += (r0 < *d);          \
-    c = r1; *(d++) = r0;
-
-#define MULADDC_STOP                    \
-}
-
-#else
-#define MULADDC_INIT                    \
-{                                       \
-    mbedtls_mpi_uint s0, s1, b0, b1;              \
-    mbedtls_mpi_uint r0, r1, rx, ry;              \
-    b0 = ( b << biH ) >> biH;           \
-    b1 = ( b >> biH );
-
-#define MULADDC_CORE                    \
-    s0 = ( *s << biH ) >> biH;          \
-    s1 = ( *s >> biH ); s++;            \
-    rx = s0 * b1; r0 = s0 * b0;         \
-    ry = s1 * b0; r1 = s1 * b1;         \
-    r1 += ( rx >> biH );                \
-    r1 += ( ry >> biH );                \
-    rx <<= biH; ry <<= biH;             \
-    r0 += rx; r1 += (r0 < rx);          \
-    r0 += ry; r1 += (r0 < ry);          \
-    r0 +=  c; r1 += (r0 <  c);          \
-    r0 += *d; r1 += (r0 < *d);          \
-    c = r1; *(d++) = r0;
-
-#define MULADDC_STOP                    \
-}
-
-#endif /* C (generic)  */
-#endif /* C (longlong) */
-
-#endif /* bn_mul.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/camellia.h b/tools/sdk/include/mbedtls/mbedtls/camellia.h
deleted file mode 100644
index 41d6f955bae..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/camellia.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/**
- * \file camellia.h
- *
- * \brief Camellia block cipher
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_CAMELLIA_H
-#define MBEDTLS_CAMELLIA_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-#include "platform_util.h"
-
-#define MBEDTLS_CAMELLIA_ENCRYPT     1
-#define MBEDTLS_CAMELLIA_DECRYPT     0
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#define MBEDTLS_ERR_CAMELLIA_INVALID_KEY_LENGTH   MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( -0x0024 )
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-#define MBEDTLS_ERR_CAMELLIA_BAD_INPUT_DATA -0x0024 /**< Bad input data. */
-
-#define MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH -0x0026 /**< Invalid data input length. */
-
-/* MBEDTLS_ERR_CAMELLIA_HW_ACCEL_FAILED is deprecated and should not be used.
- */
-#define MBEDTLS_ERR_CAMELLIA_HW_ACCEL_FAILED              -0x0027  /**< Camellia hardware accelerator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_CAMELLIA_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          CAMELLIA context structure
- */
-typedef struct mbedtls_camellia_context
-{
-    int nr;                     /*!<  number of rounds  */
-    uint32_t rk[68];            /*!<  CAMELLIA round keys    */
-}
-mbedtls_camellia_context;
-
-#else  /* MBEDTLS_CAMELLIA_ALT */
-#include "camellia_alt.h"
-#endif /* MBEDTLS_CAMELLIA_ALT */
-
-/**
- * \brief          Initialize a CAMELLIA context.
- *
- * \param ctx      The CAMELLIA context to be initialized.
- *                 This must not be \c NULL.
- */
-void mbedtls_camellia_init( mbedtls_camellia_context *ctx );
-
-/**
- * \brief          Clear a CAMELLIA context.
- *
- * \param ctx      The CAMELLIA context to be cleared. This may be \c NULL,
- *                 in which case this function returns immediately. If it is not
- *                 \c NULL, it must be initialized.
- */
-void mbedtls_camellia_free( mbedtls_camellia_context *ctx );
-
-/**
- * \brief          Perform a CAMELLIA key schedule operation for encryption.
- *
- * \param ctx      The CAMELLIA context to use. This must be initialized.
- * \param key      The encryption key to use. This must be a readable buffer
- *                 of size \p keybits Bits.
- * \param keybits  The length of \p key in Bits. This must be either \c 128,
- *                 \c 192 or \c 256.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_camellia_setkey_enc( mbedtls_camellia_context *ctx,
-                                 const unsigned char *key,
-                                 unsigned int keybits );
-
-/**
- * \brief          Perform a CAMELLIA key schedule operation for decryption.
- *
- * \param ctx      The CAMELLIA context to use. This must be initialized.
- * \param key      The decryption key. This must be a readable buffer
- *                 of size \p keybits Bits.
- * \param keybits  The length of \p key in Bits. This must be either \c 128,
- *                 \c 192 or \c 256.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_camellia_setkey_dec( mbedtls_camellia_context *ctx,
-                                 const unsigned char *key,
-                                 unsigned int keybits );
-
-/**
- * \brief          Perform a CAMELLIA-ECB block encryption/decryption operation.
- *
- * \param ctx      The CAMELLIA context to use. This must be initialized
- *                 and bound to a key.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT.
- * \param input    The input block. This must be a readable buffer
- *                 of size \c 16 Bytes.
- * \param output   The output block. This must be a writable buffer
- *                 of size \c 16 Bytes.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_camellia_crypt_ecb( mbedtls_camellia_context *ctx,
-                    int mode,
-                    const unsigned char input[16],
-                    unsigned char output[16] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          Perform a CAMELLIA-CBC buffer encryption/decryption operation.
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      The CAMELLIA context to use. This must be initialized
- *                 and bound to a key.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT.
- * \param length   The length in Bytes of the input data \p input.
- *                 This must be a multiple of \c 16 Bytes.
- * \param iv       The initialization vector. This must be a read/write buffer
- *                 of length \c 16 Bytes. It is updated to allow streaming
- *                 use as explained above.
- * \param input    The buffer holding the input data. This must point to a
- *                 readable buffer of length \p length Bytes.
- * \param output   The buffer holding the output data. This must point to a
- *                 writable buffer of length \p length Bytes.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_camellia_crypt_cbc( mbedtls_camellia_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[16],
-                    const unsigned char *input,
-                    unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-/**
- * \brief          Perform a CAMELLIA-CFB128 buffer encryption/decryption
- *                 operation.
- *
- * \note           Due to the nature of CFB mode, you should use the same
- *                 key for both encryption and decryption. In particular, calls
- *                 to this function should be preceded by a key-schedule via
- *                 mbedtls_camellia_setkey_enc() regardless of whether \p mode
- *                 is #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT.
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      The CAMELLIA context to use. This must be initialized
- *                 and bound to a key.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT.
- * \param length   The length of the input data \p input. Any value is allowed.
- * \param iv_off   The current offset in the IV. This must be smaller
- *                 than \c 16 Bytes. It is updated after this call to allow
- *                 the aforementioned streaming usage.
- * \param iv       The initialization vector. This must be a read/write buffer
- *                 of length \c 16 Bytes. It is updated after this call to
- *                 allow the aforementioned streaming usage.
- * \param input    The buffer holding the input data. This must be a readable
- *                 buffer of size \p length Bytes.
- * \param output   The buffer to hold the output data. This must be a writable
- *                 buffer of length \p length Bytes.
- *
- * \return         \c 0 if successful.
- * \return         A negative error code on failure.
- */
-int mbedtls_camellia_crypt_cfb128( mbedtls_camellia_context *ctx,
-                       int mode,
-                       size_t length,
-                       size_t *iv_off,
-                       unsigned char iv[16],
-                       const unsigned char *input,
-                       unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CFB */
-
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-/**
- * \brief      Perform a CAMELLIA-CTR buffer encryption/decryption operation.
- *
- * *note       Due to the nature of CTR mode, you should use the same
- *             key for both encryption and decryption. In particular, calls
- *             to this function should be preceded by a key-schedule via
- *             mbedtls_camellia_setkey_enc() regardless of whether \p mode
- *             is #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT.
- *
- * \warning    You must never reuse a nonce value with the same key. Doing so
- *             would void the encryption for the two messages encrypted with
- *             the same nonce and key.
- *
- *             There are two common strategies for managing nonces with CTR:
- *
- *             1. You can handle everything as a single message processed over
- *             successive calls to this function. In that case, you want to
- *             set \p nonce_counter and \p nc_off to 0 for the first call, and
- *             then preserve the values of \p nonce_counter, \p nc_off and \p
- *             stream_block across calls to this function as they will be
- *             updated by this function.
- *
- *             With this strategy, you must not encrypt more than 2**128
- *             blocks of data with the same key.
- *
- *             2. You can encrypt separate messages by dividing the \p
- *             nonce_counter buffer in two areas: the first one used for a
- *             per-message nonce, handled by yourself, and the second one
- *             updated by this function internally.
- *
- *             For example, you might reserve the first \c 12 Bytes for the
- *             per-message nonce, and the last \c 4 Bytes for internal use.
- *             In that case, before calling this function on a new message you
- *             need to set the first \c 12 Bytes of \p nonce_counter to your
- *             chosen nonce value, the last four to \c 0, and \p nc_off to \c 0
- *             (which will cause \p stream_block to be ignored). That way, you
- *             can encrypt at most \c 2**96 messages of up to \c 2**32 blocks
- *             each  with the same key.
- *
- *             The per-message nonce (or information sufficient to reconstruct
- *             it) needs to be communicated with the ciphertext and must be
- *             unique. The recommended way to ensure uniqueness is to use a
- *             message counter. An alternative is to generate random nonces,
- *             but this limits the number of messages that can be securely
- *             encrypted: for example, with 96-bit random nonces, you should
- *             not encrypt more than 2**32 messages with the same key.
- *
- *             Note that for both stategies, sizes are measured in blocks and
- *             that a CAMELLIA block is \c 16 Bytes.
- *
- * \warning    Upon return, \p stream_block contains sensitive data. Its
- *             content must not be written to insecure storage and should be
- *             securely discarded as soon as it's no longer needed.
- *
- * \param ctx           The CAMELLIA context to use. This must be initialized
- *                      and bound to a key.
- * \param length        The length of the input data \p input in Bytes.
- *                      Any value is allowed.
- * \param nc_off        The offset in the current \p stream_block (for resuming
- *                      within current cipher stream). The offset pointer to
- *                      should be \c 0 at the start of a stream. It is updated
- *                      at the end of this call.
- * \param nonce_counter The 128-bit nonce and counter. This must be a read/write
- *                      buffer of length \c 16 Bytes.
- * \param stream_block  The saved stream-block for resuming. This must be a
- *                      read/write buffer of length \c 16 Bytes.
- * \param input         The input data stream. This must be a readable buffer of
- *                      size \p length Bytes.
- * \param output        The output data stream. This must be a writable buffer
- *                      of size \p length Bytes.
- *
- * \return              \c 0 if successful.
- * \return              A negative error code on failure.
- */
-int mbedtls_camellia_crypt_ctr( mbedtls_camellia_context *ctx,
-                       size_t length,
-                       size_t *nc_off,
-                       unsigned char nonce_counter[16],
-                       unsigned char stream_block[16],
-                       const unsigned char *input,
-                       unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CTR */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- */
-int mbedtls_camellia_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* camellia.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ccm.h b/tools/sdk/include/mbedtls/mbedtls/ccm.h
deleted file mode 100644
index 3647d5094f5..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ccm.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/**
- * \file ccm.h
- *
- * \brief This file provides an API for the CCM authenticated encryption
- *        mode for block ciphers.
- *
- * CCM combines Counter mode encryption with CBC-MAC authentication
- * for 128-bit block ciphers.
- *
- * Input to CCM includes the following elements:
- * <ul><li>Payload - data that is both authenticated and encrypted.</li>
- * <li>Associated data (Adata) - data that is authenticated but not
- * encrypted, For example, a header.</li>
- * <li>Nonce - A unique value that is assigned to the payload and the
- * associated data.</li></ul>
- *
- * Definition of CCM:
- * http://csrc.nist.gov/publications/nistpubs/800-38C/SP800-38C_updated-July20_2007.pdf
- * RFC 3610 "Counter with CBC-MAC (CCM)"
- *
- * Related:
- * RFC 5116 "An Interface and Algorithms for Authenticated Encryption"
- *
- * Definition of CCM*:
- * IEEE 802.15.4 - IEEE Standard for Local and metropolitan area networks
- * Integer representation is fixed most-significant-octet-first order and
- * the representation of octets is most-significant-bit-first order. This is
- * consistent with RFC 3610.
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_CCM_H
-#define MBEDTLS_CCM_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "cipher.h"
-
-#define MBEDTLS_ERR_CCM_BAD_INPUT       -0x000D /**< Bad input parameters to the function. */
-#define MBEDTLS_ERR_CCM_AUTH_FAILED     -0x000F /**< Authenticated decryption failed. */
-
-/* MBEDTLS_ERR_CCM_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_CCM_HW_ACCEL_FAILED -0x0011 /**< CCM hardware accelerator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_CCM_ALT)
-// Regular implementation
-//
-
-/**
- * \brief    The CCM context-type definition. The CCM context is passed
- *           to the APIs called.
- */
-typedef struct mbedtls_ccm_context
-{
-    mbedtls_cipher_context_t cipher_ctx;    /*!< The cipher context used. */
-}
-mbedtls_ccm_context;
-
-#else  /* MBEDTLS_CCM_ALT */
-#include "ccm_alt.h"
-#endif /* MBEDTLS_CCM_ALT */
-
-/**
- * \brief           This function initializes the specified CCM context,
- *                  to make references valid, and prepare the context
- *                  for mbedtls_ccm_setkey() or mbedtls_ccm_free().
- *
- * \param ctx       The CCM context to initialize. This must not be \c NULL.
- */
-void mbedtls_ccm_init( mbedtls_ccm_context *ctx );
-
-/**
- * \brief           This function initializes the CCM context set in the
- *                  \p ctx parameter and sets the encryption key.
- *
- * \param ctx       The CCM context to initialize. This must be an initialized
- *                  context.
- * \param cipher    The 128-bit block cipher to use.
- * \param key       The encryption key. This must not be \c NULL.
- * \param keybits   The key size in bits. This must be acceptable by the cipher.
- *
- * \return          \c 0 on success.
- * \return          A CCM or cipher-specific error code on failure.
- */
-int mbedtls_ccm_setkey( mbedtls_ccm_context *ctx,
-                        mbedtls_cipher_id_t cipher,
-                        const unsigned char *key,
-                        unsigned int keybits );
-
-/**
- * \brief   This function releases and clears the specified CCM context
- *          and underlying cipher sub-context.
- *
- * \param ctx       The CCM context to clear. If this is \c NULL, the function
- *                  has no effect. Otherwise, this must be initialized.
- */
-void mbedtls_ccm_free( mbedtls_ccm_context *ctx );
-
-/**
- * \brief           This function encrypts a buffer using CCM.
- *
- * \note            The tag is written to a separate buffer. To concatenate
- *                  the \p tag with the \p output, as done in <em>RFC-3610:
- *                  Counter with CBC-MAC (CCM)</em>, use
- *                  \p tag = \p output + \p length, and make sure that the
- *                  output buffer is at least \p length + \p tag_len wide.
- *
- * \param ctx       The CCM context to use for encryption. This must be
- *                  initialized and bound to a key.
- * \param length    The length of the input data in Bytes.
- * \param iv        The initialization vector (nonce). This must be a readable
- *                  buffer of at least \p iv_len Bytes.
- * \param iv_len    The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12,
- *                  or 13. The length L of the message length field is
- *                  15 - \p iv_len.
- * \param add       The additional data field. If \p add_len is greater than
- *                  zero, \p add must be a readable buffer of at least that
- *                  length.
- * \param add_len   The length of additional data in Bytes.
- *                  This must be less than `2^16 - 2^8`.
- * \param input     The buffer holding the input data. If \p length is greater
- *                  than zero, \p input must be a readable buffer of at least
- *                  that length.
- * \param output    The buffer holding the output data. If \p length is greater
- *                  than zero, \p output must be a writable buffer of at least
- *                  that length.
- * \param tag       The buffer holding the authentication field. This must be a
- *                  readable buffer of at least \p tag_len Bytes.
- * \param tag_len   The length of the authentication field to generate in Bytes:
- *                  4, 6, 8, 10, 12, 14 or 16.
- *
- * \return          \c 0 on success.
- * \return          A CCM or cipher-specific error code on failure.
- */
-int mbedtls_ccm_encrypt_and_tag( mbedtls_ccm_context *ctx, size_t length,
-                         const unsigned char *iv, size_t iv_len,
-                         const unsigned char *add, size_t add_len,
-                         const unsigned char *input, unsigned char *output,
-                         unsigned char *tag, size_t tag_len );
-
-/**
- * \brief           This function encrypts a buffer using CCM*.
- *
- * \note            The tag is written to a separate buffer. To concatenate
- *                  the \p tag with the \p output, as done in <em>RFC-3610:
- *                  Counter with CBC-MAC (CCM)</em>, use
- *                  \p tag = \p output + \p length, and make sure that the
- *                  output buffer is at least \p length + \p tag_len wide.
- *
- * \note            When using this function in a variable tag length context,
- *                  the tag length has to be encoded into the \p iv passed to
- *                  this function.
- *
- * \param ctx       The CCM context to use for encryption. This must be
- *                  initialized and bound to a key.
- * \param length    The length of the input data in Bytes.
- * \param iv        The initialization vector (nonce). This must be a readable
- *                  buffer of at least \p iv_len Bytes.
- * \param iv_len    The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12,
- *                  or 13. The length L of the message length field is
- *                  15 - \p iv_len.
- * \param add       The additional data field. This must be a readable buffer of
- *                  at least \p add_len Bytes.
- * \param add_len   The length of additional data in Bytes.
- *                  This must be less than 2^16 - 2^8.
- * \param input     The buffer holding the input data. If \p length is greater
- *                  than zero, \p input must be a readable buffer of at least
- *                  that length.
- * \param output    The buffer holding the output data. If \p length is greater
- *                  than zero, \p output must be a writable buffer of at least
- *                  that length.
- * \param tag       The buffer holding the authentication field. This must be a
- *                  readable buffer of at least \p tag_len Bytes.
- * \param tag_len   The length of the authentication field to generate in Bytes:
- *                  0, 4, 6, 8, 10, 12, 14 or 16.
- *
- * \warning         Passing \c 0 as \p tag_len means that the message is no
- *                  longer authenticated.
- *
- * \return          \c 0 on success.
- * \return          A CCM or cipher-specific error code on failure.
- */
-int mbedtls_ccm_star_encrypt_and_tag( mbedtls_ccm_context *ctx, size_t length,
-                         const unsigned char *iv, size_t iv_len,
-                         const unsigned char *add, size_t add_len,
-                         const unsigned char *input, unsigned char *output,
-                         unsigned char *tag, size_t tag_len );
-
-/**
- * \brief           This function performs a CCM authenticated decryption of a
- *                  buffer.
- *
- * \param ctx       The CCM context to use for decryption. This must be
- *                  initialized and bound to a key.
- * \param length    The length of the input data in Bytes.
- * \param iv        The initialization vector (nonce). This must be a readable
- *                  buffer of at least \p iv_len Bytes.
- * \param iv_len    The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12,
- *                  or 13. The length L of the message length field is
- *                  15 - \p iv_len.
- * \param add       The additional data field. This must be a readable buffer
- *                  of at least that \p add_len Bytes..
- * \param add_len   The length of additional data in Bytes.
- *                  This must be less than 2^16 - 2^8.
- * \param input     The buffer holding the input data. If \p length is greater
- *                  than zero, \p input must be a readable buffer of at least
- *                  that length.
- * \param output    The buffer holding the output data. If \p length is greater
- *                  than zero, \p output must be a writable buffer of at least
- *                  that length.
- * \param tag       The buffer holding the authentication field. This must be a
- *                  readable buffer of at least \p tag_len Bytes.
- * \param tag_len   The length of the authentication field to generate in Bytes:
- *                  4, 6, 8, 10, 12, 14 or 16.
- *
- * \return          \c 0 on success. This indicates that the message is authentic.
- * \return          #MBEDTLS_ERR_CCM_AUTH_FAILED if the tag does not match.
- * \return          A cipher-specific error code on calculation failure.
- */
-int mbedtls_ccm_auth_decrypt( mbedtls_ccm_context *ctx, size_t length,
-                      const unsigned char *iv, size_t iv_len,
-                      const unsigned char *add, size_t add_len,
-                      const unsigned char *input, unsigned char *output,
-                      const unsigned char *tag, size_t tag_len );
-
-/**
- * \brief           This function performs a CCM* authenticated decryption of a
- *                  buffer.
- *
- * \note            When using this function in a variable tag length context,
- *                  the tag length has to be decoded from \p iv and passed to
- *                  this function as \p tag_len. (\p tag needs to be adjusted
- *                  accordingly.)
- *
- * \param ctx       The CCM context to use for decryption. This must be
- *                  initialized and bound to a key.
- * \param length    The length of the input data in Bytes.
- * \param iv        The initialization vector (nonce). This must be a readable
- *                  buffer of at least \p iv_len Bytes.
- * \param iv_len    The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12,
- *                  or 13. The length L of the message length field is
- *                  15 - \p iv_len.
- * \param add       The additional data field. This must be a readable buffer of
- *                  at least that \p add_len Bytes.
- * \param add_len   The length of additional data in Bytes.
- *                  This must be less than 2^16 - 2^8.
- * \param input     The buffer holding the input data. If \p length is greater
- *                  than zero, \p input must be a readable buffer of at least
- *                  that length.
- * \param output    The buffer holding the output data. If \p length is greater
- *                  than zero, \p output must be a writable buffer of at least
- *                  that length.
- * \param tag       The buffer holding the authentication field. This must be a
- *                  readable buffer of at least \p tag_len Bytes.
- * \param tag_len   The length of the authentication field in Bytes.
- *                  0, 4, 6, 8, 10, 12, 14 or 16.
- *
- * \warning         Passing \c 0 as \p tag_len means that the message is nos
- *                  longer authenticated.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_CCM_AUTH_FAILED if the tag does not match.
- * \return          A cipher-specific error code on calculation failure.
- */
-int mbedtls_ccm_star_auth_decrypt( mbedtls_ccm_context *ctx, size_t length,
-                      const unsigned char *iv, size_t iv_len,
-                      const unsigned char *add, size_t add_len,
-                      const unsigned char *input, unsigned char *output,
-                      const unsigned char *tag, size_t tag_len );
-
-#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C)
-/**
- * \brief          The CCM checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_ccm_self_test( int verbose );
-#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_CCM_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/certs.h b/tools/sdk/include/mbedtls/mbedtls/certs.h
deleted file mode 100644
index 2a645ad0d04..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/certs.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/**
- * \file certs.h
- *
- * \brief Sample certificates and DHM parameters for testing
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_CERTS_H
-#define MBEDTLS_CERTS_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* List of all PEM-encoded CA certificates, terminated by NULL;
- * PEM encoded if MBEDTLS_PEM_PARSE_C is enabled, DER encoded
- * otherwise. */
-extern const char * mbedtls_test_cas[];
-extern const size_t mbedtls_test_cas_len[];
-
-/* List of all DER-encoded CA certificates, terminated by NULL */
-extern const unsigned char * mbedtls_test_cas_der[];
-extern const size_t mbedtls_test_cas_der_len[];
-
-#if defined(MBEDTLS_PEM_PARSE_C)
-/* Concatenation of all CA certificates in PEM format if available */
-extern const char   mbedtls_test_cas_pem[];
-extern const size_t mbedtls_test_cas_pem_len;
-#endif /* MBEDTLS_PEM_PARSE_C */
-
-/*
- * CA test certificates
- */
-
-extern const char mbedtls_test_ca_crt_ec_pem[];
-extern const char mbedtls_test_ca_key_ec_pem[];
-extern const char mbedtls_test_ca_pwd_ec_pem[];
-extern const char mbedtls_test_ca_key_rsa_pem[];
-extern const char mbedtls_test_ca_pwd_rsa_pem[];
-extern const char mbedtls_test_ca_crt_rsa_sha1_pem[];
-extern const char mbedtls_test_ca_crt_rsa_sha256_pem[];
-
-extern const unsigned char mbedtls_test_ca_crt_ec_der[];
-extern const unsigned char mbedtls_test_ca_key_ec_der[];
-extern const unsigned char mbedtls_test_ca_key_rsa_der[];
-extern const unsigned char mbedtls_test_ca_crt_rsa_sha1_der[];
-extern const unsigned char mbedtls_test_ca_crt_rsa_sha256_der[];
-
-extern const size_t mbedtls_test_ca_crt_ec_pem_len;
-extern const size_t mbedtls_test_ca_key_ec_pem_len;
-extern const size_t mbedtls_test_ca_pwd_ec_pem_len;
-extern const size_t mbedtls_test_ca_key_rsa_pem_len;
-extern const size_t mbedtls_test_ca_pwd_rsa_pem_len;
-extern const size_t mbedtls_test_ca_crt_rsa_sha1_pem_len;
-extern const size_t mbedtls_test_ca_crt_rsa_sha256_pem_len;
-
-extern const size_t mbedtls_test_ca_crt_ec_der_len;
-extern const size_t mbedtls_test_ca_key_ec_der_len;
-extern const size_t mbedtls_test_ca_pwd_ec_der_len;
-extern const size_t mbedtls_test_ca_key_rsa_der_len;
-extern const size_t mbedtls_test_ca_pwd_rsa_der_len;
-extern const size_t mbedtls_test_ca_crt_rsa_sha1_der_len;
-extern const size_t mbedtls_test_ca_crt_rsa_sha256_der_len;
-
-/* Config-dependent dispatch between PEM and DER encoding
- * (PEM if enabled, otherwise DER) */
-
-extern const char mbedtls_test_ca_crt_ec[];
-extern const char mbedtls_test_ca_key_ec[];
-extern const char mbedtls_test_ca_pwd_ec[];
-extern const char mbedtls_test_ca_key_rsa[];
-extern const char mbedtls_test_ca_pwd_rsa[];
-extern const char mbedtls_test_ca_crt_rsa_sha1[];
-extern const char mbedtls_test_ca_crt_rsa_sha256[];
-
-extern const size_t mbedtls_test_ca_crt_ec_len;
-extern const size_t mbedtls_test_ca_key_ec_len;
-extern const size_t mbedtls_test_ca_pwd_ec_len;
-extern const size_t mbedtls_test_ca_key_rsa_len;
-extern const size_t mbedtls_test_ca_pwd_rsa_len;
-extern const size_t mbedtls_test_ca_crt_rsa_sha1_len;
-extern const size_t mbedtls_test_ca_crt_rsa_sha256_len;
-
-/* Config-dependent dispatch between SHA-1 and SHA-256
- * (SHA-256 if enabled, otherwise SHA-1) */
-
-extern const char mbedtls_test_ca_crt_rsa[];
-extern const size_t mbedtls_test_ca_crt_rsa_len;
-
-/* Config-dependent dispatch between EC and RSA
- * (RSA if enabled, otherwise EC) */
-
-extern const char * mbedtls_test_ca_crt;
-extern const char * mbedtls_test_ca_key;
-extern const char * mbedtls_test_ca_pwd;
-extern const size_t mbedtls_test_ca_crt_len;
-extern const size_t mbedtls_test_ca_key_len;
-extern const size_t mbedtls_test_ca_pwd_len;
-
-/*
- * Server test certificates
- */
-
-extern const char mbedtls_test_srv_crt_ec_pem[];
-extern const char mbedtls_test_srv_key_ec_pem[];
-extern const char mbedtls_test_srv_pwd_ec_pem[];
-extern const char mbedtls_test_srv_key_rsa_pem[];
-extern const char mbedtls_test_srv_pwd_rsa_pem[];
-extern const char mbedtls_test_srv_crt_rsa_sha1_pem[];
-extern const char mbedtls_test_srv_crt_rsa_sha256_pem[];
-
-extern const unsigned char mbedtls_test_srv_crt_ec_der[];
-extern const unsigned char mbedtls_test_srv_key_ec_der[];
-extern const unsigned char mbedtls_test_srv_key_rsa_der[];
-extern const unsigned char mbedtls_test_srv_crt_rsa_sha1_der[];
-extern const unsigned char mbedtls_test_srv_crt_rsa_sha256_der[];
-
-extern const size_t mbedtls_test_srv_crt_ec_pem_len;
-extern const size_t mbedtls_test_srv_key_ec_pem_len;
-extern const size_t mbedtls_test_srv_pwd_ec_pem_len;
-extern const size_t mbedtls_test_srv_key_rsa_pem_len;
-extern const size_t mbedtls_test_srv_pwd_rsa_pem_len;
-extern const size_t mbedtls_test_srv_crt_rsa_sha1_pem_len;
-extern const size_t mbedtls_test_srv_crt_rsa_sha256_pem_len;
-
-extern const size_t mbedtls_test_srv_crt_ec_der_len;
-extern const size_t mbedtls_test_srv_key_ec_der_len;
-extern const size_t mbedtls_test_srv_pwd_ec_der_len;
-extern const size_t mbedtls_test_srv_key_rsa_der_len;
-extern const size_t mbedtls_test_srv_pwd_rsa_der_len;
-extern const size_t mbedtls_test_srv_crt_rsa_sha1_der_len;
-extern const size_t mbedtls_test_srv_crt_rsa_sha256_der_len;
-
-/* Config-dependent dispatch between PEM and DER encoding
- * (PEM if enabled, otherwise DER) */
-
-extern const char mbedtls_test_srv_crt_ec[];
-extern const char mbedtls_test_srv_key_ec[];
-extern const char mbedtls_test_srv_pwd_ec[];
-extern const char mbedtls_test_srv_key_rsa[];
-extern const char mbedtls_test_srv_pwd_rsa[];
-extern const char mbedtls_test_srv_crt_rsa_sha1[];
-extern const char mbedtls_test_srv_crt_rsa_sha256[];
-
-extern const size_t mbedtls_test_srv_crt_ec_len;
-extern const size_t mbedtls_test_srv_key_ec_len;
-extern const size_t mbedtls_test_srv_pwd_ec_len;
-extern const size_t mbedtls_test_srv_key_rsa_len;
-extern const size_t mbedtls_test_srv_pwd_rsa_len;
-extern const size_t mbedtls_test_srv_crt_rsa_sha1_len;
-extern const size_t mbedtls_test_srv_crt_rsa_sha256_len;
-
-/* Config-dependent dispatch between SHA-1 and SHA-256
- * (SHA-256 if enabled, otherwise SHA-1) */
-
-extern const char mbedtls_test_srv_crt_rsa[];
-extern const size_t mbedtls_test_srv_crt_rsa_len;
-
-/* Config-dependent dispatch between EC and RSA
- * (RSA if enabled, otherwise EC) */
-
-extern const char * mbedtls_test_srv_crt;
-extern const char * mbedtls_test_srv_key;
-extern const char * mbedtls_test_srv_pwd;
-extern const size_t mbedtls_test_srv_crt_len;
-extern const size_t mbedtls_test_srv_key_len;
-extern const size_t mbedtls_test_srv_pwd_len;
-
-/*
- * Client test certificates
- */
-
-extern const char mbedtls_test_cli_crt_ec_pem[];
-extern const char mbedtls_test_cli_key_ec_pem[];
-extern const char mbedtls_test_cli_pwd_ec_pem[];
-extern const char mbedtls_test_cli_key_rsa_pem[];
-extern const char mbedtls_test_cli_pwd_rsa_pem[];
-extern const char mbedtls_test_cli_crt_rsa_pem[];
-
-extern const unsigned char mbedtls_test_cli_crt_ec_der[];
-extern const unsigned char mbedtls_test_cli_key_ec_der[];
-extern const unsigned char mbedtls_test_cli_key_rsa_der[];
-extern const unsigned char mbedtls_test_cli_crt_rsa_der[];
-
-extern const size_t mbedtls_test_cli_crt_ec_pem_len;
-extern const size_t mbedtls_test_cli_key_ec_pem_len;
-extern const size_t mbedtls_test_cli_pwd_ec_pem_len;
-extern const size_t mbedtls_test_cli_key_rsa_pem_len;
-extern const size_t mbedtls_test_cli_pwd_rsa_pem_len;
-extern const size_t mbedtls_test_cli_crt_rsa_pem_len;
-
-extern const size_t mbedtls_test_cli_crt_ec_der_len;
-extern const size_t mbedtls_test_cli_key_ec_der_len;
-extern const size_t mbedtls_test_cli_key_rsa_der_len;
-extern const size_t mbedtls_test_cli_crt_rsa_der_len;
-
-/* Config-dependent dispatch between PEM and DER encoding
- * (PEM if enabled, otherwise DER) */
-
-extern const char mbedtls_test_cli_crt_ec[];
-extern const char mbedtls_test_cli_key_ec[];
-extern const char mbedtls_test_cli_pwd_ec[];
-extern const char mbedtls_test_cli_key_rsa[];
-extern const char mbedtls_test_cli_pwd_rsa[];
-extern const char mbedtls_test_cli_crt_rsa[];
-
-extern const size_t mbedtls_test_cli_crt_ec_len;
-extern const size_t mbedtls_test_cli_key_ec_len;
-extern const size_t mbedtls_test_cli_pwd_ec_len;
-extern const size_t mbedtls_test_cli_key_rsa_len;
-extern const size_t mbedtls_test_cli_pwd_rsa_len;
-extern const size_t mbedtls_test_cli_crt_rsa_len;
-
-/* Config-dependent dispatch between EC and RSA
- * (RSA if enabled, otherwise EC) */
-
-extern const char * mbedtls_test_cli_crt;
-extern const char * mbedtls_test_cli_key;
-extern const char * mbedtls_test_cli_pwd;
-extern const size_t mbedtls_test_cli_crt_len;
-extern const size_t mbedtls_test_cli_key_len;
-extern const size_t mbedtls_test_cli_pwd_len;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* certs.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/chacha20.h b/tools/sdk/include/mbedtls/mbedtls/chacha20.h
deleted file mode 100644
index e2950e1a015..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/chacha20.h
+++ /dev/null
@@ -1,254 +0,0 @@
-/**
- * \file chacha20.h
- *
- * \brief   This file contains ChaCha20 definitions and functions.
- *
- *          ChaCha20 is a stream cipher that can encrypt and decrypt
- *          information. ChaCha was created by Daniel Bernstein as a variant of
- *          its Salsa cipher https://cr.yp.to/chacha/chacha-20080128.pdf
- *          ChaCha20 is the variant with 20 rounds, that was also standardized
- *          in RFC 7539.
- *
- * \author Daniel King <damaki.gh@gmail.com>
- */
-
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved.
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_CHACHA20_H
-#define MBEDTLS_CHACHA20_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA         -0x0051 /**< Invalid input parameter(s). */
-
-/* MBEDTLS_ERR_CHACHA20_FEATURE_UNAVAILABLE is deprecated and should not be
- * used. */
-#define MBEDTLS_ERR_CHACHA20_FEATURE_UNAVAILABLE    -0x0053 /**< Feature not available. For example, s part of the API is not implemented. */
-
-/* MBEDTLS_ERR_CHACHA20_HW_ACCEL_FAILED is deprecated and should not be used.
- */
-#define MBEDTLS_ERR_CHACHA20_HW_ACCEL_FAILED        -0x0055  /**< Chacha20 hardware accelerator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_CHACHA20_ALT)
-
-typedef struct mbedtls_chacha20_context
-{
-    uint32_t state[16];          /*! The state (before round operations). */
-    uint8_t  keystream8[64];     /*! Leftover keystream bytes. */
-    size_t keystream_bytes_used; /*! Number of keystream bytes already used. */
-}
-mbedtls_chacha20_context;
-
-#else  /* MBEDTLS_CHACHA20_ALT */
-#include "chacha20_alt.h"
-#endif /* MBEDTLS_CHACHA20_ALT */
-
-/**
- * \brief           This function initializes the specified ChaCha20 context.
- *
- *                  It must be the first API called before using
- *                  the context.
- *
- *                  It is usually followed by calls to
- *                  \c mbedtls_chacha20_setkey() and
- *                  \c mbedtls_chacha20_starts(), then one or more calls to
- *                  to \c mbedtls_chacha20_update(), and finally to
- *                  \c mbedtls_chacha20_free().
- *
- * \param ctx       The ChaCha20 context to initialize.
- *                  This must not be \c NULL.
- */
-void mbedtls_chacha20_init( mbedtls_chacha20_context *ctx );
-
-/**
- * \brief           This function releases and clears the specified
- *                  ChaCha20 context.
- *
- * \param ctx       The ChaCha20 context to clear. This may be \c NULL,
- *                  in which case this function is a no-op. If it is not
- *                  \c NULL, it must point to an initialized context.
- *
- */
-void mbedtls_chacha20_free( mbedtls_chacha20_context *ctx );
-
-/**
- * \brief           This function sets the encryption/decryption key.
- *
- * \note            After using this function, you must also call
- *                  \c mbedtls_chacha20_starts() to set a nonce before you
- *                  start encrypting/decrypting data with
- *                  \c mbedtls_chacha_update().
- *
- * \param ctx       The ChaCha20 context to which the key should be bound.
- *                  It must be initialized.
- * \param key       The encryption/decryption key. This must be \c 32 Bytes
- *                  in length.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA if ctx or key is NULL.
- */
-int mbedtls_chacha20_setkey( mbedtls_chacha20_context *ctx,
-                             const unsigned char key[32] );
-
-/**
- * \brief           This function sets the nonce and initial counter value.
- *
- * \note            A ChaCha20 context can be re-used with the same key by
- *                  calling this function to change the nonce.
- *
- * \warning         You must never use the same nonce twice with the same key.
- *                  This would void any confidentiality guarantees for the
- *                  messages encrypted with the same nonce and key.
- *
- * \param ctx       The ChaCha20 context to which the nonce should be bound.
- *                  It must be initialized and bound to a key.
- * \param nonce     The nonce. This must be \c 12 Bytes in size.
- * \param counter   The initial counter value. This is usually \c 0.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA if ctx or nonce is
- *                  NULL.
- */
-int mbedtls_chacha20_starts( mbedtls_chacha20_context* ctx,
-                             const unsigned char nonce[12],
-                             uint32_t counter );
-
-/**
- * \brief           This function encrypts or decrypts data.
- *
- *                  Since ChaCha20 is a stream cipher, the same operation is
- *                  used for encrypting and decrypting data.
- *
- * \note            The \p input and \p output pointers must either be equal or
- *                  point to non-overlapping buffers.
- *
- * \note            \c mbedtls_chacha20_setkey() and
- *                  \c mbedtls_chacha20_starts() must be called at least once
- *                  to setup the context before this function can be called.
- *
- * \note            This function can be called multiple times in a row in
- *                  order to encrypt of decrypt data piecewise with the same
- *                  key and nonce.
- *
- * \param ctx       The ChaCha20 context to use for encryption or decryption.
- *                  It must be initialized and bound to a key and nonce.
- * \param size      The length of the input data in Bytes.
- * \param input     The buffer holding the input data.
- *                  This pointer can be \c NULL if `size == 0`.
- * \param output    The buffer holding the output data.
- *                  This must be able to hold \p size Bytes.
- *                  This pointer can be \c NULL if `size == 0`.
- *
- * \return          \c 0 on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_chacha20_update( mbedtls_chacha20_context *ctx,
-                             size_t size,
-                             const unsigned char *input,
-                             unsigned char *output );
-
-/**
- * \brief           This function encrypts or decrypts data with ChaCha20 and
- *                  the given key and nonce.
- *
- *                  Since ChaCha20 is a stream cipher, the same operation is
- *                  used for encrypting and decrypting data.
- *
- * \warning         You must never use the same (key, nonce) pair more than
- *                  once. This would void any confidentiality guarantees for
- *                  the messages encrypted with the same nonce and key.
- *
- * \note            The \p input and \p output pointers must either be equal or
- *                  point to non-overlapping buffers.
- *
- * \param key       The encryption/decryption key.
- *                  This must be \c 32 Bytes in length.
- * \param nonce     The nonce. This must be \c 12 Bytes in size.
- * \param counter   The initial counter value. This is usually \c 0.
- * \param size      The length of the input data in Bytes.
- * \param input     The buffer holding the input data.
- *                  This pointer can be \c NULL if `size == 0`.
- * \param output    The buffer holding the output data.
- *                  This must be able to hold \p size Bytes.
- *                  This pointer can be \c NULL if `size == 0`.
- *
- * \return          \c 0 on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_chacha20_crypt( const unsigned char key[32],
-                            const unsigned char nonce[12],
-                            uint32_t counter,
-                            size_t size,
-                            const unsigned char* input,
-                            unsigned char* output );
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief           The ChaCha20 checkup routine.
- *
- * \return          \c 0 on success.
- * \return          \c 1 on failure.
- */
-int mbedtls_chacha20_self_test( int verbose );
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_CHACHA20_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/chachapoly.h b/tools/sdk/include/mbedtls/mbedtls/chachapoly.h
deleted file mode 100644
index bee5a3ab036..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/chachapoly.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/**
- * \file chachapoly.h
- *
- * \brief   This file contains the AEAD-ChaCha20-Poly1305 definitions and
- *          functions.
- *
- *          ChaCha20-Poly1305 is an algorithm for Authenticated Encryption
- *          with Associated Data (AEAD) that can be used to encrypt and
- *          authenticate data. It is based on ChaCha20 and Poly1305 by Daniel
- *          Bernstein and was standardized in RFC 7539.
- *
- * \author Daniel King <damaki.gh@gmail.com>
- */
-
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved.
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_CHACHAPOLY_H
-#define MBEDTLS_CHACHAPOLY_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-/* for shared error codes */
-#include "poly1305.h"
-
-#define MBEDTLS_ERR_CHACHAPOLY_BAD_STATE            -0x0054 /**< The requested operation is not permitted in the current state. */
-#define MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED          -0x0056 /**< Authenticated decryption failed: data was not authentic. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum
-{
-    MBEDTLS_CHACHAPOLY_ENCRYPT,     /**< The mode value for performing encryption. */
-    MBEDTLS_CHACHAPOLY_DECRYPT      /**< The mode value for performing decryption. */
-}
-mbedtls_chachapoly_mode_t;
-
-#if !defined(MBEDTLS_CHACHAPOLY_ALT)
-
-#include "chacha20.h"
-
-typedef struct mbedtls_chachapoly_context
-{
-    mbedtls_chacha20_context chacha20_ctx;  /**< The ChaCha20 context. */
-    mbedtls_poly1305_context poly1305_ctx;  /**< The Poly1305 context. */
-    uint64_t aad_len;                       /**< The length (bytes) of the Additional Authenticated Data. */
-    uint64_t ciphertext_len;                /**< The length (bytes) of the ciphertext. */
-    int state;                              /**< The current state of the context. */
-    mbedtls_chachapoly_mode_t mode;         /**< Cipher mode (encrypt or decrypt). */
-}
-mbedtls_chachapoly_context;
-
-#else /* !MBEDTLS_CHACHAPOLY_ALT */
-#include "chachapoly_alt.h"
-#endif /* !MBEDTLS_CHACHAPOLY_ALT */
-
-/**
- * \brief           This function initializes the specified ChaCha20-Poly1305 context.
- *
- *                  It must be the first API called before using
- *                  the context. It must be followed by a call to
- *                  \c mbedtls_chachapoly_setkey() before any operation can be
- *                  done, and to \c mbedtls_chachapoly_free() once all
- *                  operations with that context have been finished.
- *
- *                  In order to encrypt or decrypt full messages at once, for
- *                  each message you should make a single call to
- *                  \c mbedtls_chachapoly_crypt_and_tag() or
- *                  \c mbedtls_chachapoly_auth_decrypt().
- *
- *                  In order to encrypt messages piecewise, for each
- *                  message you should make a call to
- *                  \c mbedtls_chachapoly_starts(), then 0 or more calls to
- *                  \c mbedtls_chachapoly_update_aad(), then 0 or more calls to
- *                  \c mbedtls_chachapoly_update(), then one call to
- *                  \c mbedtls_chachapoly_finish().
- *
- * \warning         Decryption with the piecewise API is discouraged! Always
- *                  use \c mbedtls_chachapoly_auth_decrypt() when possible!
- *
- *                  If however this is not possible because the data is too
- *                  large to fit in memory, you need to:
- *
- *                  - call \c mbedtls_chachapoly_starts() and (if needed)
- *                  \c mbedtls_chachapoly_update_aad() as above,
- *                  - call \c mbedtls_chachapoly_update() multiple times and
- *                  ensure its output (the plaintext) is NOT used in any other
- *                  way than placing it in temporary storage at this point,
- *                  - call \c mbedtls_chachapoly_finish() to compute the
- *                  authentication tag and compared it in constant time to the
- *                  tag received with the ciphertext.
- *
- *                  If the tags are not equal, you must immediately discard
- *                  all previous outputs of \c mbedtls_chachapoly_update(),
- *                  otherwise you can now safely use the plaintext.
- *
- * \param ctx       The ChachaPoly context to initialize. Must not be \c NULL.
- */
-void mbedtls_chachapoly_init( mbedtls_chachapoly_context *ctx );
-
-/**
- * \brief           This function releases and clears the specified
- *                  ChaCha20-Poly1305 context.
- *
- * \param ctx       The ChachaPoly context to clear. This may be \c NULL, in which
- *                  case this function is a no-op.
- */
-void mbedtls_chachapoly_free( mbedtls_chachapoly_context *ctx );
-
-/**
- * \brief           This function sets the ChaCha20-Poly1305
- *                  symmetric encryption key.
- *
- * \param ctx       The ChaCha20-Poly1305 context to which the key should be
- *                  bound. This must be initialized.
- * \param key       The \c 256 Bit (\c 32 Bytes) key.
- *
- * \return          \c 0 on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_chachapoly_setkey( mbedtls_chachapoly_context *ctx,
-                               const unsigned char key[32] );
-
-/**
- * \brief           This function starts a ChaCha20-Poly1305 encryption or
- *                  decryption operation.
- *
- * \warning         You must never use the same nonce twice with the same key.
- *                  This would void any confidentiality and authenticity
- *                  guarantees for the messages encrypted with the same nonce
- *                  and key.
- *
- * \note            If the context is being used for AAD only (no data to
- *                  encrypt or decrypt) then \p mode can be set to any value.
- *
- * \warning         Decryption with the piecewise API is discouraged, see the
- *                  warning on \c mbedtls_chachapoly_init().
- *
- * \param ctx       The ChaCha20-Poly1305 context. This must be initialized
- *                  and bound to a key.
- * \param nonce     The nonce/IV to use for the message.
- *                  This must be a redable buffer of length \c 12 Bytes.
- * \param mode      The operation to perform: #MBEDTLS_CHACHAPOLY_ENCRYPT or
- *                  #MBEDTLS_CHACHAPOLY_DECRYPT (discouraged, see warning).
- *
- * \return          \c 0 on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_chachapoly_starts( mbedtls_chachapoly_context *ctx,
-                               const unsigned char nonce[12],
-                               mbedtls_chachapoly_mode_t mode );
-
-/**
- * \brief           This function feeds additional data to be authenticated
- *                  into an ongoing ChaCha20-Poly1305 operation.
- *
- *                  The Additional Authenticated Data (AAD), also called
- *                  Associated Data (AD) is only authenticated but not
- *                  encrypted nor included in the encrypted output. It is
- *                  usually transmitted separately from the ciphertext or
- *                  computed locally by each party.
- *
- * \note            This function is called before data is encrypted/decrypted.
- *                  I.e. call this function to process the AAD before calling
- *                  \c mbedtls_chachapoly_update().
- *
- *                  You may call this function multiple times to process
- *                  an arbitrary amount of AAD. It is permitted to call
- *                  this function 0 times, if no AAD is used.
- *
- *                  This function cannot be called any more if data has
- *                  been processed by \c mbedtls_chachapoly_update(),
- *                  or if the context has been finished.
- *
- * \warning         Decryption with the piecewise API is discouraged, see the
- *                  warning on \c mbedtls_chachapoly_init().
- *
- * \param ctx       The ChaCha20-Poly1305 context. This must be initialized
- *                  and bound to a key.
- * \param aad_len   The length in Bytes of the AAD. The length has no
- *                  restrictions.
- * \param aad       Buffer containing the AAD.
- *                  This pointer can be \c NULL if `aad_len == 0`.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_POLY1305_BAD_INPUT_DATA
- *                  if \p ctx or \p aad are NULL.
- * \return          #MBEDTLS_ERR_CHACHAPOLY_BAD_STATE
- *                  if the operations has not been started or has been
- *                  finished, or if the AAD has been finished.
- */
-int mbedtls_chachapoly_update_aad( mbedtls_chachapoly_context *ctx,
-                                   const unsigned char *aad,
-                                   size_t aad_len );
-
-/**
- * \brief           Thus function feeds data to be encrypted or decrypted
- *                  into an on-going ChaCha20-Poly1305
- *                  operation.
- *
- *                  The direction (encryption or decryption) depends on the
- *                  mode that was given when calling
- *                  \c mbedtls_chachapoly_starts().
- *
- *                  You may call this function multiple times to process
- *                  an arbitrary amount of data. It is permitted to call
- *                  this function 0 times, if no data is to be encrypted
- *                  or decrypted.
- *
- * \warning         Decryption with the piecewise API is discouraged, see the
- *                  warning on \c mbedtls_chachapoly_init().
- *
- * \param ctx       The ChaCha20-Poly1305 context to use. This must be initialized.
- * \param len       The length (in bytes) of the data to encrypt or decrypt.
- * \param input     The buffer containing the data to encrypt or decrypt.
- *                  This pointer can be \c NULL if `len == 0`.
- * \param output    The buffer to where the encrypted or decrypted data is
- *                  written. This must be able to hold \p len bytes.
- *                  This pointer can be \c NULL if `len == 0`.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_CHACHAPOLY_BAD_STATE
- *                  if the operation has not been started or has been
- *                  finished.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_chachapoly_update( mbedtls_chachapoly_context *ctx,
-                               size_t len,
-                               const unsigned char *input,
-                               unsigned char *output );
-
-/**
- * \brief           This function finished the ChaCha20-Poly1305 operation and
- *                  generates the MAC (authentication tag).
- *
- * \param ctx       The ChaCha20-Poly1305 context to use. This must be initialized.
- * \param mac       The buffer to where the 128-bit (16 bytes) MAC is written.
- *
- * \warning         Decryption with the piecewise API is discouraged, see the
- *                  warning on \c mbedtls_chachapoly_init().
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_CHACHAPOLY_BAD_STATE
- *                  if the operation has not been started or has been
- *                  finished.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_chachapoly_finish( mbedtls_chachapoly_context *ctx,
-                               unsigned char mac[16] );
-
-/**
- * \brief           This function performs a complete ChaCha20-Poly1305
- *                  authenticated encryption with the previously-set key.
- *
- * \note            Before using this function, you must set the key with
- *                  \c mbedtls_chachapoly_setkey().
- *
- * \warning         You must never use the same nonce twice with the same key.
- *                  This would void any confidentiality and authenticity
- *                  guarantees for the messages encrypted with the same nonce
- *                  and key.
- *
- * \param ctx       The ChaCha20-Poly1305 context to use (holds the key).
- *                  This must be initialized.
- * \param length    The length (in bytes) of the data to encrypt or decrypt.
- * \param nonce     The 96-bit (12 bytes) nonce/IV to use.
- * \param aad       The buffer containing the additional authenticated
- *                  data (AAD). This pointer can be \c NULL if `aad_len == 0`.
- * \param aad_len   The length (in bytes) of the AAD data to process.
- * \param input     The buffer containing the data to encrypt or decrypt.
- *                  This pointer can be \c NULL if `ilen == 0`.
- * \param output    The buffer to where the encrypted or decrypted data
- *                  is written. This pointer can be \c NULL if `ilen == 0`.
- * \param tag       The buffer to where the computed 128-bit (16 bytes) MAC
- *                  is written. This must not be \c NULL.
- *
- * \return          \c 0 on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_chachapoly_encrypt_and_tag( mbedtls_chachapoly_context *ctx,
-                                        size_t length,
-                                        const unsigned char nonce[12],
-                                        const unsigned char *aad,
-                                        size_t aad_len,
-                                        const unsigned char *input,
-                                        unsigned char *output,
-                                        unsigned char tag[16] );
-
-/**
- * \brief           This function performs a complete ChaCha20-Poly1305
- *                  authenticated decryption with the previously-set key.
- *
- * \note            Before using this function, you must set the key with
- *                  \c mbedtls_chachapoly_setkey().
- *
- * \param ctx       The ChaCha20-Poly1305 context to use (holds the key).
- * \param length    The length (in Bytes) of the data to decrypt.
- * \param nonce     The \c 96 Bit (\c 12 bytes) nonce/IV to use.
- * \param aad       The buffer containing the additional authenticated data (AAD).
- *                  This pointer can be \c NULL if `aad_len == 0`.
- * \param aad_len   The length (in bytes) of the AAD data to process.
- * \param tag       The buffer holding the authentication tag.
- *                  This must be a readable buffer of length \c 16 Bytes.
- * \param input     The buffer containing the data to decrypt.
- *                  This pointer can be \c NULL if `ilen == 0`.
- * \param output    The buffer to where the decrypted data is written.
- *                  This pointer can be \c NULL if `ilen == 0`.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED
- *                  if the data was not authentic.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_chachapoly_auth_decrypt( mbedtls_chachapoly_context *ctx,
-                                     size_t length,
-                                     const unsigned char nonce[12],
-                                     const unsigned char *aad,
-                                     size_t aad_len,
-                                     const unsigned char tag[16],
-                                     const unsigned char *input,
-                                     unsigned char *output );
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief           The ChaCha20-Poly1305 checkup routine.
- *
- * \return          \c 0 on success.
- * \return          \c 1 on failure.
- */
-int mbedtls_chachapoly_self_test( int verbose );
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_CHACHAPOLY_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/check_config.h b/tools/sdk/include/mbedtls/mbedtls/check_config.h
deleted file mode 100644
index 8ce73ceff11..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/check_config.h
+++ /dev/null
@@ -1,766 +0,0 @@
-/**
- * \file check_config.h
- *
- * \brief Consistency checks for configuration options
- */
-/*
- *  Copyright (C) 2006-2018, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-/*
- * It is recommended to include this file from your config.h
- * in order to catch dependency issues early.
- */
-
-#ifndef MBEDTLS_CHECK_CONFIG_H
-#define MBEDTLS_CHECK_CONFIG_H
-
-/*
- * We assume CHAR_BIT is 8 in many places. In practice, this is true on our
- * target platforms, so not an issue, but let's just be extra sure.
- */
-#include <limits.h>
-#if CHAR_BIT != 8
-#error "mbed TLS requires a platform with 8-bit chars"
-#endif
-
-#if defined(_WIN32)
-#if !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_C is required on Windows"
-#endif
-
-/* Fix the config here. Not convenient to put an #ifdef _WIN32 in config.h as
- * it would confuse config.pl. */
-#if !defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) && \
-    !defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO)
-#define MBEDTLS_PLATFORM_SNPRINTF_ALT
-#endif
-#endif /* _WIN32 */
-
-#if defined(TARGET_LIKE_MBED) && \
-    ( defined(MBEDTLS_NET_C) || defined(MBEDTLS_TIMING_C) )
-#error "The NET and TIMING modules are not available for mbed OS - please use the network and timing functions provided by mbed OS"
-#endif
-
-#if defined(MBEDTLS_DEPRECATED_WARNING) && \
-    !defined(__GNUC__) && !defined(__clang__)
-#error "MBEDTLS_DEPRECATED_WARNING only works with GCC and Clang"
-#endif
-
-#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_HAVE_TIME)
-#error "MBEDTLS_HAVE_TIME_DATE without MBEDTLS_HAVE_TIME does not make sense"
-#endif
-
-#if defined(MBEDTLS_AESNI_C) && !defined(MBEDTLS_HAVE_ASM)
-#error "MBEDTLS_AESNI_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_CTR_DRBG_C) && !defined(MBEDTLS_AES_C)
-#error "MBEDTLS_CTR_DRBG_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_DHM_C) && !defined(MBEDTLS_BIGNUM_C)
-#error "MBEDTLS_DHM_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT) && !defined(MBEDTLS_SSL_TRUNCATED_HMAC)
-#error "MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_CMAC_C) && \
-    !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_DES_C)
-#error "MBEDTLS_CMAC_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_NIST_KW_C) && \
-    ( !defined(MBEDTLS_AES_C) || !defined(MBEDTLS_CIPHER_C) )
-#error "MBEDTLS_NIST_KW_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECDH_C) && !defined(MBEDTLS_ECP_C)
-#error "MBEDTLS_ECDH_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECDSA_C) &&            \
-    ( !defined(MBEDTLS_ECP_C) ||           \
-      !defined(MBEDTLS_ASN1_PARSE_C) ||    \
-      !defined(MBEDTLS_ASN1_WRITE_C) )
-#error "MBEDTLS_ECDSA_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECJPAKE_C) &&           \
-    ( !defined(MBEDTLS_ECP_C) || !defined(MBEDTLS_MD_C) )
-#error "MBEDTLS_ECJPAKE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_RESTARTABLE)           && \
-    ( defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) || \
-      defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT)     || \
-      defined(MBEDTLS_ECDSA_SIGN_ALT)          || \
-      defined(MBEDTLS_ECDSA_VERIFY_ALT)        || \
-      defined(MBEDTLS_ECDSA_GENKEY_ALT)        || \
-      defined(MBEDTLS_ECP_INTERNAL_ALT)        || \
-      defined(MBEDTLS_ECP_ALT) )
-#error "MBEDTLS_ECP_RESTARTABLE defined, but it cannot coexist with an alternative ECP implementation"
-#endif
-
-#if defined(MBEDTLS_ECDSA_DETERMINISTIC) && !defined(MBEDTLS_HMAC_DRBG_C)
-#error "MBEDTLS_ECDSA_DETERMINISTIC defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_C) && ( !defined(MBEDTLS_BIGNUM_C) || (    \
-    !defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) &&                  \
-    !defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) &&                  \
-    !defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) &&                  \
-    !defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) &&                  \
-    !defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) &&                  \
-    !defined(MBEDTLS_ECP_DP_BP256R1_ENABLED)   &&                  \
-    !defined(MBEDTLS_ECP_DP_BP384R1_ENABLED)   &&                  \
-    !defined(MBEDTLS_ECP_DP_BP512R1_ENABLED)   &&                  \
-    !defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) &&                  \
-    !defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) &&                  \
-    !defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) &&                  \
-    !defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) &&                 \
-    !defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) ) )
-#error "MBEDTLS_ECP_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_C) && !(            \
-    defined(MBEDTLS_ECP_ALT) ||             \
-    defined(MBEDTLS_CTR_DRBG_C) ||          \
-    defined(MBEDTLS_HMAC_DRBG_C) ||         \
-    defined(MBEDTLS_SHA512_C) ||            \
-    defined(MBEDTLS_SHA256_C) ||            \
-    defined(MBEDTLS_ECP_NO_INTERNAL_RNG))
-#error "MBEDTLS_ECP_C requires a DRBG or SHA-2 module unless MBEDTLS_ECP_NO_INTERNAL_RNG is defined or an alternative implementation is used"
-#endif
-
-#if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_ASN1_PARSE_C)
-#error "MBEDTLS_PK_PARSE_C defined, but not all prerequesites"
-#endif
-
-#if defined(MBEDTLS_ENTROPY_C) && (!defined(MBEDTLS_SHA512_C) &&      \
-                                    !defined(MBEDTLS_SHA256_C))
-#error "MBEDTLS_ENTROPY_C defined, but not all prerequisites"
-#endif
-#if defined(MBEDTLS_ENTROPY_C) && defined(MBEDTLS_SHA512_C) &&         \
-    defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 64)
-#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high"
-#endif
-#if defined(MBEDTLS_ENTROPY_C) &&                                            \
-    ( !defined(MBEDTLS_SHA512_C) || defined(MBEDTLS_ENTROPY_FORCE_SHA256) ) \
-    && defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 32)
-#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high"
-#endif
-#if defined(MBEDTLS_ENTROPY_C) && \
-    defined(MBEDTLS_ENTROPY_FORCE_SHA256) && !defined(MBEDTLS_SHA256_C)
-#error "MBEDTLS_ENTROPY_FORCE_SHA256 defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_TEST_NULL_ENTROPY) && \
-    ( !defined(MBEDTLS_ENTROPY_C) || !defined(MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES) )
-#error "MBEDTLS_TEST_NULL_ENTROPY defined, but not all prerequisites"
-#endif
-#if defined(MBEDTLS_TEST_NULL_ENTROPY) && \
-     ( defined(MBEDTLS_ENTROPY_NV_SEED) || defined(MBEDTLS_ENTROPY_HARDWARE_ALT) || \
-    defined(MBEDTLS_HAVEGE_C) )
-#error "MBEDTLS_TEST_NULL_ENTROPY defined, but entropy sources too"
-#endif
-
-#if defined(MBEDTLS_GCM_C) && (                                        \
-        !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_CAMELLIA_C) )
-#error "MBEDTLS_GCM_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT)
-#error "MBEDTLS_ECP_RANDOMIZE_JAC_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT)
-#error "MBEDTLS_ECP_ADD_MIXED_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT)
-#error "MBEDTLS_ECP_DOUBLE_JAC_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT)
-#error "MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT)
-#error "MBEDTLS_ECP_NORMALIZE_JAC_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT)
-#error "MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT)
-#error "MBEDTLS_ECP_RANDOMIZE_MXZ_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT)
-#error "MBEDTLS_ECP_NORMALIZE_MXZ_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_HAVEGE_C) && !defined(MBEDTLS_TIMING_C)
-#error "MBEDTLS_HAVEGE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_HKDF_C) && !defined(MBEDTLS_MD_C)
-#error "MBEDTLS_HKDF_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_HMAC_DRBG_C) && !defined(MBEDTLS_MD_C)
-#error "MBEDTLS_HMAC_DRBG_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) &&                 \
-    ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) )
-#error "MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) &&                 \
-    ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) )
-#error "MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) && !defined(MBEDTLS_DHM_C)
-#error "MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) &&                     \
-    !defined(MBEDTLS_ECDH_C)
-#error "MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) &&                   \
-    ( !defined(MBEDTLS_DHM_C) || !defined(MBEDTLS_RSA_C) ||           \
-      !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) )
-#error "MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) &&                 \
-    ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_RSA_C) ||          \
-      !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) )
-#error "MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) &&                 \
-    ( !defined(MBEDTLS_ECDH_C) || !defined(MBEDTLS_ECDSA_C) ||          \
-      !defined(MBEDTLS_X509_CRT_PARSE_C) )
-#error "MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) &&                   \
-    ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \
-      !defined(MBEDTLS_PKCS1_V15) )
-#error "MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) &&                       \
-    ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \
-      !defined(MBEDTLS_PKCS1_V15) )
-#error "MBEDTLS_KEY_EXCHANGE_RSA_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) &&                    \
-    ( !defined(MBEDTLS_ECJPAKE_C) || !defined(MBEDTLS_SHA256_C) ||      \
-      !defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) )
-#error "MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) &&                          \
-    ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) )
-#error "MBEDTLS_MEMORY_BUFFER_ALLOC_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_MEMORY_BACKTRACE) && !defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C)
-#error "MBEDTLS_MEMORY_BACKTRACE defined, but not all prerequesites"
-#endif
-
-#if defined(MBEDTLS_MEMORY_DEBUG) && !defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C)
-#error "MBEDTLS_MEMORY_DEBUG defined, but not all prerequesites"
-#endif
-
-#if defined(MBEDTLS_PADLOCK_C) && !defined(MBEDTLS_HAVE_ASM)
-#error "MBEDTLS_PADLOCK_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PEM_PARSE_C) && !defined(MBEDTLS_BASE64_C)
-#error "MBEDTLS_PEM_PARSE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PEM_WRITE_C) && !defined(MBEDTLS_BASE64_C)
-#error "MBEDTLS_PEM_WRITE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PK_C) && \
-    ( !defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_ECP_C) )
-#error "MBEDTLS_PK_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_PK_C)
-#error "MBEDTLS_PK_PARSE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PK_WRITE_C) && !defined(MBEDTLS_PK_C)
-#error "MBEDTLS_PK_WRITE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PKCS11_C) && !defined(MBEDTLS_PK_C)
-#error "MBEDTLS_PKCS11_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_EXIT_ALT) && !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_EXIT_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) && !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_EXIT_MACRO defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) &&\
-    ( defined(MBEDTLS_PLATFORM_STD_EXIT) ||\
-        defined(MBEDTLS_PLATFORM_EXIT_ALT) )
-#error "MBEDTLS_PLATFORM_EXIT_MACRO and MBEDTLS_PLATFORM_STD_EXIT/MBEDTLS_PLATFORM_EXIT_ALT cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_TIME_ALT) &&\
-    ( !defined(MBEDTLS_PLATFORM_C) ||\
-        !defined(MBEDTLS_HAVE_TIME) )
-#error "MBEDTLS_PLATFORM_TIME_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_TIME_MACRO) &&\
-    ( !defined(MBEDTLS_PLATFORM_C) ||\
-        !defined(MBEDTLS_HAVE_TIME) )
-#error "MBEDTLS_PLATFORM_TIME_MACRO defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) &&\
-    ( !defined(MBEDTLS_PLATFORM_C) ||\
-        !defined(MBEDTLS_HAVE_TIME) )
-#error "MBEDTLS_PLATFORM_TIME_TYPE_MACRO defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_TIME_MACRO) &&\
-    ( defined(MBEDTLS_PLATFORM_STD_TIME) ||\
-        defined(MBEDTLS_PLATFORM_TIME_ALT) )
-#error "MBEDTLS_PLATFORM_TIME_MACRO and MBEDTLS_PLATFORM_STD_TIME/MBEDTLS_PLATFORM_TIME_ALT cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) &&\
-    ( defined(MBEDTLS_PLATFORM_STD_TIME) ||\
-        defined(MBEDTLS_PLATFORM_TIME_ALT) )
-#error "MBEDTLS_PLATFORM_TIME_TYPE_MACRO and MBEDTLS_PLATFORM_STD_TIME/MBEDTLS_PLATFORM_TIME_ALT cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_FPRINTF_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_FPRINTF_MACRO defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) &&\
-    ( defined(MBEDTLS_PLATFORM_STD_FPRINTF) ||\
-        defined(MBEDTLS_PLATFORM_FPRINTF_ALT) )
-#error "MBEDTLS_PLATFORM_FPRINTF_MACRO and MBEDTLS_PLATFORM_STD_FPRINTF/MBEDTLS_PLATFORM_FPRINTF_ALT cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\
-    ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) )
-#error "MBEDTLS_PLATFORM_FREE_MACRO defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\
-    defined(MBEDTLS_PLATFORM_STD_FREE)
-#error "MBEDTLS_PLATFORM_FREE_MACRO and MBEDTLS_PLATFORM_STD_FREE cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && !defined(MBEDTLS_PLATFORM_CALLOC_MACRO)
-#error "MBEDTLS_PLATFORM_CALLOC_MACRO must be defined if MBEDTLS_PLATFORM_FREE_MACRO is"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\
-    ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) )
-#error "MBEDTLS_PLATFORM_CALLOC_MACRO defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\
-    defined(MBEDTLS_PLATFORM_STD_CALLOC)
-#error "MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_STD_CALLOC cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && !defined(MBEDTLS_PLATFORM_FREE_MACRO)
-#error "MBEDTLS_PLATFORM_FREE_MACRO must be defined if MBEDTLS_PLATFORM_CALLOC_MACRO is"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_MEMORY) && !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_MEMORY defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_PRINTF_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_PRINTF_MACRO defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) &&\
-    ( defined(MBEDTLS_PLATFORM_STD_PRINTF) ||\
-        defined(MBEDTLS_PLATFORM_PRINTF_ALT) )
-#error "MBEDTLS_PLATFORM_PRINTF_MACRO and MBEDTLS_PLATFORM_STD_PRINTF/MBEDTLS_PLATFORM_PRINTF_ALT cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_SNPRINTF_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C)
-#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) &&\
-    ( defined(MBEDTLS_PLATFORM_STD_SNPRINTF) ||\
-        defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) )
-#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO and MBEDTLS_PLATFORM_STD_SNPRINTF/MBEDTLS_PLATFORM_SNPRINTF_ALT cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR) &&\
-    !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS)
-#error "MBEDTLS_PLATFORM_STD_MEM_HDR defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_CALLOC) && !defined(MBEDTLS_PLATFORM_MEMORY)
-#error "MBEDTLS_PLATFORM_STD_CALLOC defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_CALLOC) && !defined(MBEDTLS_PLATFORM_MEMORY)
-#error "MBEDTLS_PLATFORM_STD_CALLOC defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_FREE) && !defined(MBEDTLS_PLATFORM_MEMORY)
-#error "MBEDTLS_PLATFORM_STD_FREE defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_EXIT) &&\
-    !defined(MBEDTLS_PLATFORM_EXIT_ALT)
-#error "MBEDTLS_PLATFORM_STD_EXIT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_TIME) &&\
-    ( !defined(MBEDTLS_PLATFORM_TIME_ALT) ||\
-        !defined(MBEDTLS_HAVE_TIME) )
-#error "MBEDTLS_PLATFORM_STD_TIME defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_FPRINTF) &&\
-    !defined(MBEDTLS_PLATFORM_FPRINTF_ALT)
-#error "MBEDTLS_PLATFORM_STD_FPRINTF defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_PRINTF) &&\
-    !defined(MBEDTLS_PLATFORM_PRINTF_ALT)
-#error "MBEDTLS_PLATFORM_STD_PRINTF defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_SNPRINTF) &&\
-    !defined(MBEDTLS_PLATFORM_SNPRINTF_ALT)
-#error "MBEDTLS_PLATFORM_STD_SNPRINTF defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_ENTROPY_NV_SEED) &&\
-    ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_ENTROPY_C) )
-#error "MBEDTLS_ENTROPY_NV_SEED defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) &&\
-    !defined(MBEDTLS_ENTROPY_NV_SEED)
-#error "MBEDTLS_PLATFORM_NV_SEED_ALT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) &&\
-    !defined(MBEDTLS_PLATFORM_NV_SEED_ALT)
-#error "MBEDTLS_PLATFORM_STD_NV_SEED_READ defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) &&\
-    !defined(MBEDTLS_PLATFORM_NV_SEED_ALT)
-#error "MBEDTLS_PLATFORM_STD_NV_SEED_WRITE defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) &&\
-    ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) ||\
-      defined(MBEDTLS_PLATFORM_NV_SEED_ALT) )
-#error "MBEDTLS_PLATFORM_NV_SEED_READ_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_READ cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO) &&\
-    ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) ||\
-      defined(MBEDTLS_PLATFORM_NV_SEED_ALT) )
-#error "MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_WRITE cannot be defined simultaneously"
-#endif
-
-#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_BIGNUM_C) ||         \
-    !defined(MBEDTLS_OID_C) )
-#error "MBEDTLS_RSA_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_PKCS1_V21) &&         \
-    !defined(MBEDTLS_PKCS1_V15) )
-#error "MBEDTLS_RSA_C defined, but none of the PKCS1 versions enabled"
-#endif
-
-#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) &&                        \
-    ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_PKCS1_V21) )
-#error "MBEDTLS_X509_RSASSA_PSS_SUPPORT defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_PROTO_SSL3) && ( !defined(MBEDTLS_MD5_C) ||     \
-    !defined(MBEDTLS_SHA1_C) )
-#error "MBEDTLS_SSL_PROTO_SSL3 defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_PROTO_TLS1) && ( !defined(MBEDTLS_MD5_C) ||     \
-    !defined(MBEDTLS_SHA1_C) )
-#error "MBEDTLS_SSL_PROTO_TLS1 defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_PROTO_TLS1_1) && ( !defined(MBEDTLS_MD5_C) ||     \
-    !defined(MBEDTLS_SHA1_C) )
-#error "MBEDTLS_SSL_PROTO_TLS1_1 defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && ( !defined(MBEDTLS_SHA1_C) &&     \
-    !defined(MBEDTLS_SHA256_C) && !defined(MBEDTLS_SHA512_C) )
-#error "MBEDTLS_SSL_PROTO_TLS1_2 defined, but not all prerequisites"
-#endif
-
-#if (defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) ||  \
-     defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2)) && \
-    !(defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) ||                          \
-      defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) ||                      \
-      defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) ||                    \
-      defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) ||                  \
-      defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) ||                     \
-      defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) ||                   \
-      defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) ||                          \
-      defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) ||                      \
-      defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) ||                      \
-      defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) ||                    \
-      defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) )
-#error "One or more versions of the TLS protocol are enabled " \
-        "but no key exchange methods defined with MBEDTLS_KEY_EXCHANGE_xxxx"
-#endif
-
-#if defined(MBEDTLS_SSL_PROTO_DTLS)     && \
-    !defined(MBEDTLS_SSL_PROTO_TLS1_1)  && \
-    !defined(MBEDTLS_SSL_PROTO_TLS1_2)
-#error "MBEDTLS_SSL_PROTO_DTLS defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_CLI_C) && !defined(MBEDTLS_SSL_TLS_C)
-#error "MBEDTLS_SSL_CLI_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_TLS_C) && ( !defined(MBEDTLS_CIPHER_C) ||     \
-    !defined(MBEDTLS_MD_C) )
-#error "MBEDTLS_SSL_TLS_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_SRV_C) && !defined(MBEDTLS_SSL_TLS_C)
-#error "MBEDTLS_SSL_SRV_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_TLS_C) && (!defined(MBEDTLS_SSL_PROTO_SSL3) && \
-    !defined(MBEDTLS_SSL_PROTO_TLS1) && !defined(MBEDTLS_SSL_PROTO_TLS1_1) && \
-    !defined(MBEDTLS_SSL_PROTO_TLS1_2))
-#error "MBEDTLS_SSL_TLS_C defined, but no protocols are active"
-#endif
-
-#if defined(MBEDTLS_SSL_TLS_C) && (defined(MBEDTLS_SSL_PROTO_SSL3) && \
-    defined(MBEDTLS_SSL_PROTO_TLS1_1) && !defined(MBEDTLS_SSL_PROTO_TLS1))
-#error "Illegal protocol selection"
-#endif
-
-#if defined(MBEDTLS_SSL_TLS_C) && (defined(MBEDTLS_SSL_PROTO_TLS1) && \
-    defined(MBEDTLS_SSL_PROTO_TLS1_2) && !defined(MBEDTLS_SSL_PROTO_TLS1_1))
-#error "Illegal protocol selection"
-#endif
-
-#if defined(MBEDTLS_SSL_TLS_C) && (defined(MBEDTLS_SSL_PROTO_SSL3) && \
-    defined(MBEDTLS_SSL_PROTO_TLS1_2) && (!defined(MBEDTLS_SSL_PROTO_TLS1) || \
-    !defined(MBEDTLS_SSL_PROTO_TLS1_1)))
-#error "Illegal protocol selection"
-#endif
-
-#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && !defined(MBEDTLS_SSL_PROTO_DTLS)
-#error "MBEDTLS_SSL_DTLS_HELLO_VERIFY  defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && \
-    !defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY)
-#error "MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE  defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) &&                              \
-    ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) )
-#error "MBEDTLS_SSL_DTLS_ANTI_REPLAY  defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT) &&                              \
-    ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) )
-#error "MBEDTLS_SSL_DTLS_BADMAC_LIMIT  defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) &&   \
-    !defined(MBEDTLS_SSL_PROTO_TLS1)   &&      \
-    !defined(MBEDTLS_SSL_PROTO_TLS1_1) &&      \
-    !defined(MBEDTLS_SSL_PROTO_TLS1_2)
-#error "MBEDTLS_SSL_ENCRYPT_THEN_MAC defined, but not all prerequsites"
-#endif
-
-#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) && \
-    !defined(MBEDTLS_SSL_PROTO_TLS1)   &&          \
-    !defined(MBEDTLS_SSL_PROTO_TLS1_1) &&          \
-    !defined(MBEDTLS_SSL_PROTO_TLS1_2)
-#error "MBEDTLS_SSL_EXTENDED_MASTER_SECRET defined, but not all prerequsites"
-#endif
-
-#if defined(MBEDTLS_SSL_TICKET_C) && !defined(MBEDTLS_CIPHER_C)
-#error "MBEDTLS_SSL_TICKET_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) && \
-    !defined(MBEDTLS_SSL_PROTO_SSL3) && !defined(MBEDTLS_SSL_PROTO_TLS1)
-#error "MBEDTLS_SSL_CBC_RECORD_SPLITTING defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) && \
-        !defined(MBEDTLS_X509_CRT_PARSE_C)
-#error "MBEDTLS_SSL_SERVER_NAME_INDICATION defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_THREADING_PTHREAD)
-#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL)
-#error "MBEDTLS_THREADING_PTHREAD defined, but not all prerequisites"
-#endif
-#define MBEDTLS_THREADING_IMPL
-#endif
-
-#if defined(MBEDTLS_THREADING_ALT)
-#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL)
-#error "MBEDTLS_THREADING_ALT defined, but not all prerequisites"
-#endif
-#define MBEDTLS_THREADING_IMPL
-#endif
-
-#if defined(MBEDTLS_THREADING_C) && !defined(MBEDTLS_THREADING_IMPL)
-#error "MBEDTLS_THREADING_C defined, single threading implementation required"
-#endif
-#undef MBEDTLS_THREADING_IMPL
-
-#if defined(MBEDTLS_VERSION_FEATURES) && !defined(MBEDTLS_VERSION_C)
-#error "MBEDTLS_VERSION_FEATURES defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_X509_USE_C) && ( !defined(MBEDTLS_BIGNUM_C) ||  \
-    !defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_PARSE_C) ||      \
-    !defined(MBEDTLS_PK_PARSE_C) )
-#error "MBEDTLS_X509_USE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_X509_CREATE_C) && ( !defined(MBEDTLS_BIGNUM_C) ||  \
-    !defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_WRITE_C) ||       \
-    !defined(MBEDTLS_PK_WRITE_C) )
-#error "MBEDTLS_X509_CREATE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_CERTS_C) && !defined(MBEDTLS_X509_USE_C)
-#error "MBEDTLS_CERTS_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) )
-#error "MBEDTLS_X509_CRT_PARSE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_X509_CRL_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) )
-#error "MBEDTLS_X509_CRL_PARSE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_X509_CSR_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) )
-#error "MBEDTLS_X509_CSR_PARSE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_X509_CRT_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) )
-#error "MBEDTLS_X509_CRT_WRITE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_X509_CSR_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) )
-#error "MBEDTLS_X509_CSR_WRITE_C defined, but not all prerequisites"
-#endif
-
-#if defined(MBEDTLS_HAVE_INT32) && defined(MBEDTLS_HAVE_INT64)
-#error "MBEDTLS_HAVE_INT32 and MBEDTLS_HAVE_INT64 cannot be defined simultaneously"
-#endif /* MBEDTLS_HAVE_INT32 && MBEDTLS_HAVE_INT64 */
-
-#if ( defined(MBEDTLS_HAVE_INT32) || defined(MBEDTLS_HAVE_INT64) ) && \
-    defined(MBEDTLS_HAVE_ASM)
-#error "MBEDTLS_HAVE_INT32/MBEDTLS_HAVE_INT64 and MBEDTLS_HAVE_ASM cannot be defined simultaneously"
-#endif /* (MBEDTLS_HAVE_INT32 || MBEDTLS_HAVE_INT64) && MBEDTLS_HAVE_ASM */
-
-/*
- * Avoid warning from -pedantic. This is a convenient place for this
- * workaround since this is included by every single file before the
- * #if defined(MBEDTLS_xxx_C) that results in empty translation units.
- */
-typedef int mbedtls_iso_c_forbids_empty_translation_units;
-
-#endif /* MBEDTLS_CHECK_CONFIG_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/cipher.h b/tools/sdk/include/mbedtls/mbedtls/cipher.h
deleted file mode 100644
index 8672dd2b98b..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/cipher.h
+++ /dev/null
@@ -1,899 +0,0 @@
-/**
- * \file cipher.h
- *
- * \brief This file contains an abstraction interface for use with the cipher
- * primitives provided by the library. It provides a common interface to all of
- * the available cipher operations.
- *
- * \author Adriaan de Jong <dejong@fox-it.com>
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_CIPHER_H
-#define MBEDTLS_CIPHER_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include "platform_util.h"
-
-#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) || defined(MBEDTLS_CHACHAPOLY_C)
-#define MBEDTLS_CIPHER_MODE_AEAD
-#endif
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-#define MBEDTLS_CIPHER_MODE_WITH_PADDING
-#endif
-
-#if defined(MBEDTLS_ARC4_C) || defined(MBEDTLS_CIPHER_NULL_CIPHER) || \
-    defined(MBEDTLS_CHACHA20_C)
-#define MBEDTLS_CIPHER_MODE_STREAM
-#endif
-
-#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
-    !defined(inline) && !defined(__cplusplus)
-#define inline __inline
-#endif
-
-#define MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE  -0x6080  /**< The selected feature is not available. */
-#define MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA       -0x6100  /**< Bad input parameters. */
-#define MBEDTLS_ERR_CIPHER_ALLOC_FAILED         -0x6180  /**< Failed to allocate memory. */
-#define MBEDTLS_ERR_CIPHER_INVALID_PADDING      -0x6200  /**< Input data contains invalid padding and is rejected. */
-#define MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED  -0x6280  /**< Decryption of block requires a full block. */
-#define MBEDTLS_ERR_CIPHER_AUTH_FAILED          -0x6300  /**< Authentication failed (for AEAD modes). */
-#define MBEDTLS_ERR_CIPHER_INVALID_CONTEXT      -0x6380  /**< The context is invalid. For example, because it was freed. */
-
-/* MBEDTLS_ERR_CIPHER_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_CIPHER_HW_ACCEL_FAILED      -0x6400  /**< Cipher hardware accelerator failed. */
-
-#define MBEDTLS_CIPHER_VARIABLE_IV_LEN     0x01    /**< Cipher accepts IVs of variable length. */
-#define MBEDTLS_CIPHER_VARIABLE_KEY_LEN    0x02    /**< Cipher accepts keys of variable length. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief     Supported cipher types.
- *
- * \warning   RC4 and DES are considered weak ciphers and their use
- *            constitutes a security risk. Arm recommends considering stronger
- *            ciphers instead.
- */
-typedef enum {
-    MBEDTLS_CIPHER_ID_NONE = 0,  /**< Placeholder to mark the end of cipher ID lists. */
-    MBEDTLS_CIPHER_ID_NULL,      /**< The identity cipher, treated as a stream cipher. */
-    MBEDTLS_CIPHER_ID_AES,       /**< The AES cipher. */
-    MBEDTLS_CIPHER_ID_DES,       /**< The DES cipher. */
-    MBEDTLS_CIPHER_ID_3DES,      /**< The Triple DES cipher. */
-    MBEDTLS_CIPHER_ID_CAMELLIA,  /**< The Camellia cipher. */
-    MBEDTLS_CIPHER_ID_BLOWFISH,  /**< The Blowfish cipher. */
-    MBEDTLS_CIPHER_ID_ARC4,      /**< The RC4 cipher. */
-    MBEDTLS_CIPHER_ID_ARIA,      /**< The Aria cipher. */
-    MBEDTLS_CIPHER_ID_CHACHA20,  /**< The ChaCha20 cipher. */
-} mbedtls_cipher_id_t;
-
-/**
- * \brief     Supported {cipher type, cipher mode} pairs.
- *
- * \warning   RC4 and DES are considered weak ciphers and their use
- *            constitutes a security risk. Arm recommends considering stronger
- *            ciphers instead.
- */
-typedef enum {
-    MBEDTLS_CIPHER_NONE = 0,             /**< Placeholder to mark the end of cipher-pair lists. */
-    MBEDTLS_CIPHER_NULL,                 /**< The identity stream cipher. */
-    MBEDTLS_CIPHER_AES_128_ECB,          /**< AES cipher with 128-bit ECB mode. */
-    MBEDTLS_CIPHER_AES_192_ECB,          /**< AES cipher with 192-bit ECB mode. */
-    MBEDTLS_CIPHER_AES_256_ECB,          /**< AES cipher with 256-bit ECB mode. */
-    MBEDTLS_CIPHER_AES_128_CBC,          /**< AES cipher with 128-bit CBC mode. */
-    MBEDTLS_CIPHER_AES_192_CBC,          /**< AES cipher with 192-bit CBC mode. */
-    MBEDTLS_CIPHER_AES_256_CBC,          /**< AES cipher with 256-bit CBC mode. */
-    MBEDTLS_CIPHER_AES_128_CFB128,       /**< AES cipher with 128-bit CFB128 mode. */
-    MBEDTLS_CIPHER_AES_192_CFB128,       /**< AES cipher with 192-bit CFB128 mode. */
-    MBEDTLS_CIPHER_AES_256_CFB128,       /**< AES cipher with 256-bit CFB128 mode. */
-    MBEDTLS_CIPHER_AES_128_CTR,          /**< AES cipher with 128-bit CTR mode. */
-    MBEDTLS_CIPHER_AES_192_CTR,          /**< AES cipher with 192-bit CTR mode. */
-    MBEDTLS_CIPHER_AES_256_CTR,          /**< AES cipher with 256-bit CTR mode. */
-    MBEDTLS_CIPHER_AES_128_GCM,          /**< AES cipher with 128-bit GCM mode. */
-    MBEDTLS_CIPHER_AES_192_GCM,          /**< AES cipher with 192-bit GCM mode. */
-    MBEDTLS_CIPHER_AES_256_GCM,          /**< AES cipher with 256-bit GCM mode. */
-    MBEDTLS_CIPHER_CAMELLIA_128_ECB,     /**< Camellia cipher with 128-bit ECB mode. */
-    MBEDTLS_CIPHER_CAMELLIA_192_ECB,     /**< Camellia cipher with 192-bit ECB mode. */
-    MBEDTLS_CIPHER_CAMELLIA_256_ECB,     /**< Camellia cipher with 256-bit ECB mode. */
-    MBEDTLS_CIPHER_CAMELLIA_128_CBC,     /**< Camellia cipher with 128-bit CBC mode. */
-    MBEDTLS_CIPHER_CAMELLIA_192_CBC,     /**< Camellia cipher with 192-bit CBC mode. */
-    MBEDTLS_CIPHER_CAMELLIA_256_CBC,     /**< Camellia cipher with 256-bit CBC mode. */
-    MBEDTLS_CIPHER_CAMELLIA_128_CFB128,  /**< Camellia cipher with 128-bit CFB128 mode. */
-    MBEDTLS_CIPHER_CAMELLIA_192_CFB128,  /**< Camellia cipher with 192-bit CFB128 mode. */
-    MBEDTLS_CIPHER_CAMELLIA_256_CFB128,  /**< Camellia cipher with 256-bit CFB128 mode. */
-    MBEDTLS_CIPHER_CAMELLIA_128_CTR,     /**< Camellia cipher with 128-bit CTR mode. */
-    MBEDTLS_CIPHER_CAMELLIA_192_CTR,     /**< Camellia cipher with 192-bit CTR mode. */
-    MBEDTLS_CIPHER_CAMELLIA_256_CTR,     /**< Camellia cipher with 256-bit CTR mode. */
-    MBEDTLS_CIPHER_CAMELLIA_128_GCM,     /**< Camellia cipher with 128-bit GCM mode. */
-    MBEDTLS_CIPHER_CAMELLIA_192_GCM,     /**< Camellia cipher with 192-bit GCM mode. */
-    MBEDTLS_CIPHER_CAMELLIA_256_GCM,     /**< Camellia cipher with 256-bit GCM mode. */
-    MBEDTLS_CIPHER_DES_ECB,              /**< DES cipher with ECB mode. */
-    MBEDTLS_CIPHER_DES_CBC,              /**< DES cipher with CBC mode. */
-    MBEDTLS_CIPHER_DES_EDE_ECB,          /**< DES cipher with EDE ECB mode. */
-    MBEDTLS_CIPHER_DES_EDE_CBC,          /**< DES cipher with EDE CBC mode. */
-    MBEDTLS_CIPHER_DES_EDE3_ECB,         /**< DES cipher with EDE3 ECB mode. */
-    MBEDTLS_CIPHER_DES_EDE3_CBC,         /**< DES cipher with EDE3 CBC mode. */
-    MBEDTLS_CIPHER_BLOWFISH_ECB,         /**< Blowfish cipher with ECB mode. */
-    MBEDTLS_CIPHER_BLOWFISH_CBC,         /**< Blowfish cipher with CBC mode. */
-    MBEDTLS_CIPHER_BLOWFISH_CFB64,       /**< Blowfish cipher with CFB64 mode. */
-    MBEDTLS_CIPHER_BLOWFISH_CTR,         /**< Blowfish cipher with CTR mode. */
-    MBEDTLS_CIPHER_ARC4_128,             /**< RC4 cipher with 128-bit mode. */
-    MBEDTLS_CIPHER_AES_128_CCM,          /**< AES cipher with 128-bit CCM mode. */
-    MBEDTLS_CIPHER_AES_192_CCM,          /**< AES cipher with 192-bit CCM mode. */
-    MBEDTLS_CIPHER_AES_256_CCM,          /**< AES cipher with 256-bit CCM mode. */
-    MBEDTLS_CIPHER_CAMELLIA_128_CCM,     /**< Camellia cipher with 128-bit CCM mode. */
-    MBEDTLS_CIPHER_CAMELLIA_192_CCM,     /**< Camellia cipher with 192-bit CCM mode. */
-    MBEDTLS_CIPHER_CAMELLIA_256_CCM,     /**< Camellia cipher with 256-bit CCM mode. */
-    MBEDTLS_CIPHER_ARIA_128_ECB,         /**< Aria cipher with 128-bit key and ECB mode. */
-    MBEDTLS_CIPHER_ARIA_192_ECB,         /**< Aria cipher with 192-bit key and ECB mode. */
-    MBEDTLS_CIPHER_ARIA_256_ECB,         /**< Aria cipher with 256-bit key and ECB mode. */
-    MBEDTLS_CIPHER_ARIA_128_CBC,         /**< Aria cipher with 128-bit key and CBC mode. */
-    MBEDTLS_CIPHER_ARIA_192_CBC,         /**< Aria cipher with 192-bit key and CBC mode. */
-    MBEDTLS_CIPHER_ARIA_256_CBC,         /**< Aria cipher with 256-bit key and CBC mode. */
-    MBEDTLS_CIPHER_ARIA_128_CFB128,      /**< Aria cipher with 128-bit key and CFB-128 mode. */
-    MBEDTLS_CIPHER_ARIA_192_CFB128,      /**< Aria cipher with 192-bit key and CFB-128 mode. */
-    MBEDTLS_CIPHER_ARIA_256_CFB128,      /**< Aria cipher with 256-bit key and CFB-128 mode. */
-    MBEDTLS_CIPHER_ARIA_128_CTR,         /**< Aria cipher with 128-bit key and CTR mode. */
-    MBEDTLS_CIPHER_ARIA_192_CTR,         /**< Aria cipher with 192-bit key and CTR mode. */
-    MBEDTLS_CIPHER_ARIA_256_CTR,         /**< Aria cipher with 256-bit key and CTR mode. */
-    MBEDTLS_CIPHER_ARIA_128_GCM,         /**< Aria cipher with 128-bit key and GCM mode. */
-    MBEDTLS_CIPHER_ARIA_192_GCM,         /**< Aria cipher with 192-bit key and GCM mode. */
-    MBEDTLS_CIPHER_ARIA_256_GCM,         /**< Aria cipher with 256-bit key and GCM mode. */
-    MBEDTLS_CIPHER_ARIA_128_CCM,         /**< Aria cipher with 128-bit key and CCM mode. */
-    MBEDTLS_CIPHER_ARIA_192_CCM,         /**< Aria cipher with 192-bit key and CCM mode. */
-    MBEDTLS_CIPHER_ARIA_256_CCM,         /**< Aria cipher with 256-bit key and CCM mode. */
-    MBEDTLS_CIPHER_AES_128_OFB,          /**< AES 128-bit cipher in OFB mode. */
-    MBEDTLS_CIPHER_AES_192_OFB,          /**< AES 192-bit cipher in OFB mode. */
-    MBEDTLS_CIPHER_AES_256_OFB,          /**< AES 256-bit cipher in OFB mode. */
-    MBEDTLS_CIPHER_AES_128_XTS,          /**< AES 128-bit cipher in XTS block mode. */
-    MBEDTLS_CIPHER_AES_256_XTS,          /**< AES 256-bit cipher in XTS block mode. */
-    MBEDTLS_CIPHER_CHACHA20,             /**< ChaCha20 stream cipher. */
-    MBEDTLS_CIPHER_CHACHA20_POLY1305,    /**< ChaCha20-Poly1305 AEAD cipher. */
-} mbedtls_cipher_type_t;
-
-/** Supported cipher modes. */
-typedef enum {
-    MBEDTLS_MODE_NONE = 0,               /**< None. */
-    MBEDTLS_MODE_ECB,                    /**< The ECB cipher mode. */
-    MBEDTLS_MODE_CBC,                    /**< The CBC cipher mode. */
-    MBEDTLS_MODE_CFB,                    /**< The CFB cipher mode. */
-    MBEDTLS_MODE_OFB,                    /**< The OFB cipher mode. */
-    MBEDTLS_MODE_CTR,                    /**< The CTR cipher mode. */
-    MBEDTLS_MODE_GCM,                    /**< The GCM cipher mode. */
-    MBEDTLS_MODE_STREAM,                 /**< The stream cipher mode. */
-    MBEDTLS_MODE_CCM,                    /**< The CCM cipher mode. */
-    MBEDTLS_MODE_XTS,                    /**< The XTS cipher mode. */
-    MBEDTLS_MODE_CHACHAPOLY,             /**< The ChaCha-Poly cipher mode. */
-} mbedtls_cipher_mode_t;
-
-/** Supported cipher padding types. */
-typedef enum {
-    MBEDTLS_PADDING_PKCS7 = 0,     /**< PKCS7 padding (default).        */
-    MBEDTLS_PADDING_ONE_AND_ZEROS, /**< ISO/IEC 7816-4 padding.         */
-    MBEDTLS_PADDING_ZEROS_AND_LEN, /**< ANSI X.923 padding.             */
-    MBEDTLS_PADDING_ZEROS,         /**< Zero padding (not reversible). */
-    MBEDTLS_PADDING_NONE,          /**< Never pad (full blocks only).   */
-} mbedtls_cipher_padding_t;
-
-/** Type of operation. */
-typedef enum {
-    MBEDTLS_OPERATION_NONE = -1,
-    MBEDTLS_DECRYPT = 0,
-    MBEDTLS_ENCRYPT,
-} mbedtls_operation_t;
-
-enum {
-    /** Undefined key length. */
-    MBEDTLS_KEY_LENGTH_NONE = 0,
-    /** Key length, in bits (including parity), for DES keys. */
-    MBEDTLS_KEY_LENGTH_DES  = 64,
-    /** Key length in bits, including parity, for DES in two-key EDE. */
-    MBEDTLS_KEY_LENGTH_DES_EDE = 128,
-    /** Key length in bits, including parity, for DES in three-key EDE. */
-    MBEDTLS_KEY_LENGTH_DES_EDE3 = 192,
-};
-
-/** Maximum length of any IV, in Bytes. */
-#define MBEDTLS_MAX_IV_LENGTH      16
-/** Maximum block size of any cipher, in Bytes. */
-#define MBEDTLS_MAX_BLOCK_LENGTH   16
-
-/**
- * Base cipher information (opaque struct).
- */
-typedef struct mbedtls_cipher_base_t mbedtls_cipher_base_t;
-
-/**
- * CMAC context (opaque struct).
- */
-typedef struct mbedtls_cmac_context_t mbedtls_cmac_context_t;
-
-/**
- * Cipher information. Allows calling cipher functions
- * in a generic way.
- */
-typedef struct mbedtls_cipher_info_t
-{
-    /** Full cipher identifier. For example,
-     * MBEDTLS_CIPHER_AES_256_CBC.
-     */
-    mbedtls_cipher_type_t type;
-
-    /** The cipher mode. For example, MBEDTLS_MODE_CBC. */
-    mbedtls_cipher_mode_t mode;
-
-    /** The cipher key length, in bits. This is the
-     * default length for variable sized ciphers.
-     * Includes parity bits for ciphers like DES.
-     */
-    unsigned int key_bitlen;
-
-    /** Name of the cipher. */
-    const char * name;
-
-    /** IV or nonce size, in Bytes.
-     * For ciphers that accept variable IV sizes,
-     * this is the recommended size.
-     */
-    unsigned int iv_size;
-
-    /** Bitflag comprised of MBEDTLS_CIPHER_VARIABLE_IV_LEN and
-     *  MBEDTLS_CIPHER_VARIABLE_KEY_LEN indicating whether the
-     *  cipher supports variable IV or variable key sizes, respectively.
-     */
-    int flags;
-
-    /** The block size, in Bytes. */
-    unsigned int block_size;
-
-    /** Struct for base cipher information and functions. */
-    const mbedtls_cipher_base_t *base;
-
-} mbedtls_cipher_info_t;
-
-/**
- * Generic cipher context.
- */
-typedef struct mbedtls_cipher_context_t
-{
-    /** Information about the associated cipher. */
-    const mbedtls_cipher_info_t *cipher_info;
-
-    /** Key length to use. */
-    int key_bitlen;
-
-    /** Operation that the key of the context has been
-     * initialized for.
-     */
-    mbedtls_operation_t operation;
-
-#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING)
-    /** Padding functions to use, if relevant for
-     * the specific cipher mode.
-     */
-    void (*add_padding)( unsigned char *output, size_t olen, size_t data_len );
-    int (*get_padding)( unsigned char *input, size_t ilen, size_t *data_len );
-#endif
-
-    /** Buffer for input that has not been processed yet. */
-    unsigned char unprocessed_data[MBEDTLS_MAX_BLOCK_LENGTH];
-
-    /** Number of Bytes that have not been processed yet. */
-    size_t unprocessed_len;
-
-    /** Current IV or NONCE_COUNTER for CTR-mode, data unit (or sector) number
-     * for XTS-mode. */
-    unsigned char iv[MBEDTLS_MAX_IV_LENGTH];
-
-    /** IV size in Bytes, for ciphers with variable-length IVs. */
-    size_t iv_size;
-
-    /** The cipher-specific context. */
-    void *cipher_ctx;
-
-#if defined(MBEDTLS_CMAC_C)
-    /** CMAC-specific context. */
-    mbedtls_cmac_context_t *cmac_ctx;
-#endif
-} mbedtls_cipher_context_t;
-
-/**
- * \brief This function retrieves the list of ciphers supported by the generic
- * cipher module.
- *
- * \return      A statically-allocated array of ciphers. The last entry
- *              is zero.
- */
-const int *mbedtls_cipher_list( void );
-
-/**
- * \brief               This function retrieves the cipher-information
- *                      structure associated with the given cipher name.
- *
- * \param cipher_name   Name of the cipher to search for. This must not be
- *                      \c NULL.
- *
- * \return              The cipher information structure associated with the
- *                      given \p cipher_name.
- * \return              \c NULL if the associated cipher information is not found.
- */
-const mbedtls_cipher_info_t *mbedtls_cipher_info_from_string( const char *cipher_name );
-
-/**
- * \brief               This function retrieves the cipher-information
- *                      structure associated with the given cipher type.
- *
- * \param cipher_type   Type of the cipher to search for.
- *
- * \return              The cipher information structure associated with the
- *                      given \p cipher_type.
- * \return              \c NULL if the associated cipher information is not found.
- */
-const mbedtls_cipher_info_t *mbedtls_cipher_info_from_type( const mbedtls_cipher_type_t cipher_type );
-
-/**
- * \brief               This function retrieves the cipher-information
- *                      structure associated with the given cipher ID,
- *                      key size and mode.
- *
- * \param cipher_id     The ID of the cipher to search for. For example,
- *                      #MBEDTLS_CIPHER_ID_AES.
- * \param key_bitlen    The length of the key in bits.
- * \param mode          The cipher mode. For example, #MBEDTLS_MODE_CBC.
- *
- * \return              The cipher information structure associated with the
- *                      given \p cipher_id.
- * \return              \c NULL if the associated cipher information is not found.
- */
-const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values( const mbedtls_cipher_id_t cipher_id,
-                                              int key_bitlen,
-                                              const mbedtls_cipher_mode_t mode );
-
-/**
- * \brief               This function initializes a \p cipher_context as NONE.
- *
- * \param ctx           The context to be initialized. This must not be \c NULL.
- */
-void mbedtls_cipher_init( mbedtls_cipher_context_t *ctx );
-
-/**
- * \brief               This function frees and clears the cipher-specific
- *                      context of \p ctx. Freeing \p ctx itself remains the
- *                      responsibility of the caller.
- *
- * \param ctx           The context to be freed. If this is \c NULL, the
- *                      function has no effect, otherwise this must point to an
- *                      initialized context.
- */
-void mbedtls_cipher_free( mbedtls_cipher_context_t *ctx );
-
-
-/**
- * \brief               This function initializes and fills the cipher-context
- *                      structure with the appropriate values. It also clears
- *                      the structure.
- *
- * \param ctx           The context to initialize. This must be initialized.
- * \param cipher_info   The cipher to use.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on
- *                      parameter-verification failure.
- * \return              #MBEDTLS_ERR_CIPHER_ALLOC_FAILED if allocation of the
- *                      cipher-specific context fails.
- *
- * \internal Currently, the function also clears the structure.
- * In future versions, the caller will be required to call
- * mbedtls_cipher_init() on the structure first.
- */
-int mbedtls_cipher_setup( mbedtls_cipher_context_t *ctx,
-                          const mbedtls_cipher_info_t *cipher_info );
-
-/**
- * \brief        This function returns the block size of the given cipher.
- *
- * \param ctx    The context of the cipher. This must be initialized.
- *
- * \return       The block size of the underlying cipher.
- * \return       \c 0 if \p ctx has not been initialized.
- */
-static inline unsigned int mbedtls_cipher_get_block_size(
-    const mbedtls_cipher_context_t *ctx )
-{
-    MBEDTLS_INTERNAL_VALIDATE_RET( ctx != NULL, 0 );
-    if( ctx->cipher_info == NULL )
-        return 0;
-
-    return ctx->cipher_info->block_size;
-}
-
-/**
- * \brief        This function returns the mode of operation for
- *               the cipher. For example, MBEDTLS_MODE_CBC.
- *
- * \param ctx    The context of the cipher. This must be initialized.
- *
- * \return       The mode of operation.
- * \return       #MBEDTLS_MODE_NONE if \p ctx has not been initialized.
- */
-static inline mbedtls_cipher_mode_t mbedtls_cipher_get_cipher_mode(
-    const mbedtls_cipher_context_t *ctx )
-{
-    MBEDTLS_INTERNAL_VALIDATE_RET( ctx != NULL, MBEDTLS_MODE_NONE );
-    if( ctx->cipher_info == NULL )
-        return MBEDTLS_MODE_NONE;
-
-    return ctx->cipher_info->mode;
-}
-
-/**
- * \brief       This function returns the size of the IV or nonce
- *              of the cipher, in Bytes.
- *
- * \param ctx   The context of the cipher. This must be initialized.
- *
- * \return      The recommended IV size if no IV has been set.
- * \return      \c 0 for ciphers not using an IV or a nonce.
- * \return      The actual size if an IV has been set.
- */
-static inline int mbedtls_cipher_get_iv_size(
-    const mbedtls_cipher_context_t *ctx )
-{
-    MBEDTLS_INTERNAL_VALIDATE_RET( ctx != NULL, 0 );
-    if( ctx->cipher_info == NULL )
-        return 0;
-
-    if( ctx->iv_size != 0 )
-        return (int) ctx->iv_size;
-
-    return (int) ctx->cipher_info->iv_size;
-}
-
-/**
- * \brief               This function returns the type of the given cipher.
- *
- * \param ctx           The context of the cipher. This must be initialized.
- *
- * \return              The type of the cipher.
- * \return              #MBEDTLS_CIPHER_NONE if \p ctx has not been initialized.
- */
-static inline mbedtls_cipher_type_t mbedtls_cipher_get_type(
-    const mbedtls_cipher_context_t *ctx )
-{
-    MBEDTLS_INTERNAL_VALIDATE_RET(
-        ctx != NULL, MBEDTLS_CIPHER_NONE );
-    if( ctx->cipher_info == NULL )
-        return MBEDTLS_CIPHER_NONE;
-
-    return ctx->cipher_info->type;
-}
-
-/**
- * \brief               This function returns the name of the given cipher
- *                      as a string.
- *
- * \param ctx           The context of the cipher. This must be initialized.
- *
- * \return              The name of the cipher.
- * \return              NULL if \p ctx has not been not initialized.
- */
-static inline const char *mbedtls_cipher_get_name(
-    const mbedtls_cipher_context_t *ctx )
-{
-    MBEDTLS_INTERNAL_VALIDATE_RET( ctx != NULL, 0 );
-    if( ctx->cipher_info == NULL )
-        return 0;
-
-    return ctx->cipher_info->name;
-}
-
-/**
- * \brief               This function returns the key length of the cipher.
- *
- * \param ctx           The context of the cipher. This must be initialized.
- *
- * \return              The key length of the cipher in bits.
- * \return              #MBEDTLS_KEY_LENGTH_NONE if ctx \p has not been
- *                      initialized.
- */
-static inline int mbedtls_cipher_get_key_bitlen(
-    const mbedtls_cipher_context_t *ctx )
-{
-    MBEDTLS_INTERNAL_VALIDATE_RET(
-        ctx != NULL, MBEDTLS_KEY_LENGTH_NONE );
-    if( ctx->cipher_info == NULL )
-        return MBEDTLS_KEY_LENGTH_NONE;
-
-    return (int) ctx->cipher_info->key_bitlen;
-}
-
-/**
- * \brief          This function returns the operation of the given cipher.
- *
- * \param ctx      The context of the cipher. This must be initialized.
- *
- * \return         The type of operation: #MBEDTLS_ENCRYPT or #MBEDTLS_DECRYPT.
- * \return         #MBEDTLS_OPERATION_NONE if \p ctx has not been initialized.
- */
-static inline mbedtls_operation_t mbedtls_cipher_get_operation(
-    const mbedtls_cipher_context_t *ctx )
-{
-    MBEDTLS_INTERNAL_VALIDATE_RET(
-        ctx != NULL, MBEDTLS_OPERATION_NONE );
-    if( ctx->cipher_info == NULL )
-        return MBEDTLS_OPERATION_NONE;
-
-    return ctx->operation;
-}
-
-/**
- * \brief               This function sets the key to use with the given context.
- *
- * \param ctx           The generic cipher context. This must be initialized and
- *                      bound to a cipher information structure.
- * \param key           The key to use. This must be a readable buffer of at
- *                      least \p key_bitlen Bits.
- * \param key_bitlen    The key length to use, in Bits.
- * \param operation     The operation that the key will be used for:
- *                      #MBEDTLS_ENCRYPT or #MBEDTLS_DECRYPT.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on
- *                      parameter-verification failure.
- * \return              A cipher-specific error code on failure.
- */
-int mbedtls_cipher_setkey( mbedtls_cipher_context_t *ctx,
-                           const unsigned char *key,
-                           int key_bitlen,
-                           const mbedtls_operation_t operation );
-
-#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING)
-/**
- * \brief               This function sets the padding mode, for cipher modes
- *                      that use padding.
- *
- *                      The default passing mode is PKCS7 padding.
- *
- * \param ctx           The generic cipher context. This must be initialized and
- *                      bound to a cipher information structure.
- * \param mode          The padding mode.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE
- *                      if the selected padding mode is not supported.
- * \return              #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA if the cipher mode
- *                      does not support padding.
- */
-int mbedtls_cipher_set_padding_mode( mbedtls_cipher_context_t *ctx,
-                                     mbedtls_cipher_padding_t mode );
-#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */
-
-/**
- * \brief           This function sets the initialization vector (IV)
- *                  or nonce.
- *
- * \note            Some ciphers do not use IVs nor nonce. For these
- *                  ciphers, this function has no effect.
- *
- * \param ctx       The generic cipher context. This must be initialized and
- *                  bound to a cipher information structure.
- * \param iv        The IV to use, or NONCE_COUNTER for CTR-mode ciphers. This
- *                  must be a readable buffer of at least \p iv_len Bytes.
- * \param iv_len    The IV length for ciphers with variable-size IV.
- *                  This parameter is discarded by ciphers with fixed-size IV.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on
- *                  parameter-verification failure.
- */
-int mbedtls_cipher_set_iv( mbedtls_cipher_context_t *ctx,
-                           const unsigned char *iv,
-                           size_t iv_len );
-
-/**
- * \brief         This function resets the cipher state.
- *
- * \param ctx     The generic cipher context. This must be initialized.
- *
- * \return        \c 0 on success.
- * \return        #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on
- *                parameter-verification failure.
- */
-int mbedtls_cipher_reset( mbedtls_cipher_context_t *ctx );
-
-#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C)
-/**
- * \brief               This function adds additional data for AEAD ciphers.
- *                      Currently supported with GCM and ChaCha20+Poly1305.
- *                      This must be called exactly once, after
- *                      mbedtls_cipher_reset().
- *
- * \param ctx           The generic cipher context. This must be initialized.
- * \param ad            The additional data to use. This must be a readable
- *                      buffer of at least \p ad_len Bytes.
- * \param ad_len        the Length of \p ad Bytes.
- *
- * \return              \c 0 on success.
- * \return              A specific error code on failure.
- */
-int mbedtls_cipher_update_ad( mbedtls_cipher_context_t *ctx,
-                      const unsigned char *ad, size_t ad_len );
-#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */
-
-/**
- * \brief               The generic cipher update function. It encrypts or
- *                      decrypts using the given cipher context. Writes as
- *                      many block-sized blocks of data as possible to output.
- *                      Any data that cannot be written immediately is either
- *                      added to the next block, or flushed when
- *                      mbedtls_cipher_finish() is called.
- *                      Exception: For MBEDTLS_MODE_ECB, expects a single block
- *                      in size. For example, 16 Bytes for AES.
- *
- * \note                If the underlying cipher is used in GCM mode, all calls
- *                      to this function, except for the last one before
- *                      mbedtls_cipher_finish(), must have \p ilen as a
- *                      multiple of the block size of the cipher.
- *
- * \param ctx           The generic cipher context. This must be initialized and
- *                      bound to a key.
- * \param input         The buffer holding the input data. This must be a
- *                      readable buffer of at least \p ilen Bytes.
- * \param ilen          The length of the input data.
- * \param output        The buffer for the output data. This must be able to
- *                      hold at least `ilen + block_size`. This must not be the
- *                      same buffer as \p input.
- * \param olen          The length of the output data, to be updated with the
- *                      actual number of Bytes written. This must not be
- *                      \c NULL.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on
- *                      parameter-verification failure.
- * \return              #MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE on an
- *                      unsupported mode for a cipher.
- * \return              A cipher-specific error code on failure.
- */
-int mbedtls_cipher_update( mbedtls_cipher_context_t *ctx, const unsigned char *input,
-                   size_t ilen, unsigned char *output, size_t *olen );
-
-/**
- * \brief               The generic cipher finalization function. If data still
- *                      needs to be flushed from an incomplete block, the data
- *                      contained in it is padded to the size of
- *                      the last block, and written to the \p output buffer.
- *
- * \param ctx           The generic cipher context. This must be initialized and
- *                      bound to a key.
- * \param output        The buffer to write data to. This needs to be a writable
- *                      buffer of at least \p block_size Bytes.
- * \param olen          The length of the data written to the \p output buffer.
- *                      This may not be \c NULL.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on
- *                      parameter-verification failure.
- * \return              #MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED on decryption
- *                      expecting a full block but not receiving one.
- * \return              #MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding
- *                      while decrypting.
- * \return              A cipher-specific error code on failure.
- */
-int mbedtls_cipher_finish( mbedtls_cipher_context_t *ctx,
-                   unsigned char *output, size_t *olen );
-
-#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C)
-/**
- * \brief               This function writes a tag for AEAD ciphers.
- *                      Currently supported with GCM and ChaCha20+Poly1305.
- *                      This must be called after mbedtls_cipher_finish().
- *
- * \param ctx           The generic cipher context. This must be initialized,
- *                      bound to a key, and have just completed a cipher
- *                      operation through mbedtls_cipher_finish() the tag for
- *                      which should be written.
- * \param tag           The buffer to write the tag to. This must be a writable
- *                      buffer of at least \p tag_len Bytes.
- * \param tag_len       The length of the tag to write.
- *
- * \return              \c 0 on success.
- * \return              A specific error code on failure.
- */
-int mbedtls_cipher_write_tag( mbedtls_cipher_context_t *ctx,
-                      unsigned char *tag, size_t tag_len );
-
-/**
- * \brief               This function checks the tag for AEAD ciphers.
- *                      Currently supported with GCM and ChaCha20+Poly1305.
- *                      This must be called after mbedtls_cipher_finish().
- *
- * \param ctx           The generic cipher context. This must be initialized.
- * \param tag           The buffer holding the tag. This must be a readable
- *                      buffer of at least \p tag_len Bytes.
- * \param tag_len       The length of the tag to check.
- *
- * \return              \c 0 on success.
- * \return              A specific error code on failure.
- */
-int mbedtls_cipher_check_tag( mbedtls_cipher_context_t *ctx,
-                      const unsigned char *tag, size_t tag_len );
-#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */
-
-/**
- * \brief               The generic all-in-one encryption/decryption function,
- *                      for all ciphers except AEAD constructs.
- *
- * \param ctx           The generic cipher context. This must be initialized.
- * \param iv            The IV to use, or NONCE_COUNTER for CTR-mode ciphers.
- *                      This must be a readable buffer of at least \p iv_len
- *                      Bytes.
- * \param iv_len        The IV length for ciphers with variable-size IV.
- *                      This parameter is discarded by ciphers with fixed-size
- *                      IV.
- * \param input         The buffer holding the input data. This must be a
- *                      readable buffer of at least \p ilen Bytes.
- * \param ilen          The length of the input data in Bytes.
- * \param output        The buffer for the output data. This must be able to
- *                      hold at least `ilen + block_size`. This must not be the
- *                      same buffer as \p input.
- * \param olen          The length of the output data, to be updated with the
- *                      actual number of Bytes written. This must not be
- *                      \c NULL.
- *
- * \note                Some ciphers do not use IVs nor nonce. For these
- *                      ciphers, use \p iv = NULL and \p iv_len = 0.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on
- *                      parameter-verification failure.
- * \return              #MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED on decryption
- *                      expecting a full block but not receiving one.
- * \return              #MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding
- *                      while decrypting.
- * \return              A cipher-specific error code on failure.
- */
-int mbedtls_cipher_crypt( mbedtls_cipher_context_t *ctx,
-                  const unsigned char *iv, size_t iv_len,
-                  const unsigned char *input, size_t ilen,
-                  unsigned char *output, size_t *olen );
-
-#if defined(MBEDTLS_CIPHER_MODE_AEAD)
-/**
- * \brief               The generic autenticated encryption (AEAD) function.
- *
- * \param ctx           The generic cipher context. This must be initialized and
- *                      bound to a key.
- * \param iv            The IV to use, or NONCE_COUNTER for CTR-mode ciphers.
- *                      This must be a readable buffer of at least \p iv_len
- *                      Bytes.
- * \param iv_len        The IV length for ciphers with variable-size IV.
- *                      This parameter is discarded by ciphers with fixed-size IV.
- * \param ad            The additional data to authenticate. This must be a
- *                      readable buffer of at least \p ad_len Bytes.
- * \param ad_len        The length of \p ad.
- * \param input         The buffer holding the input data. This must be a
- *                      readable buffer of at least \p ilen Bytes.
- * \param ilen          The length of the input data.
- * \param output        The buffer for the output data. This must be able to
- *                      hold at least \p ilen Bytes.
- * \param olen          The length of the output data, to be updated with the
- *                      actual number of Bytes written. This must not be
- *                      \c NULL.
- * \param tag           The buffer for the authentication tag. This must be a
- *                      writable buffer of at least \p tag_len Bytes.
- * \param tag_len       The desired length of the authentication tag.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on
- *                      parameter-verification failure.
- * \return              A cipher-specific error code on failure.
- */
-int mbedtls_cipher_auth_encrypt( mbedtls_cipher_context_t *ctx,
-                         const unsigned char *iv, size_t iv_len,
-                         const unsigned char *ad, size_t ad_len,
-                         const unsigned char *input, size_t ilen,
-                         unsigned char *output, size_t *olen,
-                         unsigned char *tag, size_t tag_len );
-
-/**
- * \brief               The generic autenticated decryption (AEAD) function.
- *
- * \note                If the data is not authentic, then the output buffer
- *                      is zeroed out to prevent the unauthentic plaintext being
- *                      used, making this interface safer.
- *
- * \param ctx           The generic cipher context. This must be initialized and
- *                      and bound to a key.
- * \param iv            The IV to use, or NONCE_COUNTER for CTR-mode ciphers.
- *                      This must be a readable buffer of at least \p iv_len
- *                      Bytes.
- * \param iv_len        The IV length for ciphers with variable-size IV.
- *                      This parameter is discarded by ciphers with fixed-size IV.
- * \param ad            The additional data to be authenticated. This must be a
- *                      readable buffer of at least \p ad_len Bytes.
- * \param ad_len        The length of \p ad.
- * \param input         The buffer holding the input data. This must be a
- *                      readable buffer of at least \p ilen Bytes.
- * \param ilen          The length of the input data.
- * \param output        The buffer for the output data.
- *                      This must be able to hold at least \p ilen Bytes.
- * \param olen          The length of the output data, to be updated with the
- *                      actual number of Bytes written. This must not be
- *                      \c NULL.
- * \param tag           The buffer holding the authentication tag. This must be
- *                      a readable buffer of at least \p tag_len Bytes.
- * \param tag_len       The length of the authentication tag.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on
- *                      parameter-verification failure.
- * \return              #MBEDTLS_ERR_CIPHER_AUTH_FAILED if data is not authentic.
- * \return              A cipher-specific error code on failure.
- */
-int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx,
-                         const unsigned char *iv, size_t iv_len,
-                         const unsigned char *ad, size_t ad_len,
-                         const unsigned char *input, size_t ilen,
-                         unsigned char *output, size_t *olen,
-                         const unsigned char *tag, size_t tag_len );
-#endif /* MBEDTLS_CIPHER_MODE_AEAD */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_CIPHER_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h b/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h
deleted file mode 100644
index 558be52a7e0..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/cipher_internal.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/**
- * \file cipher_internal.h
- *
- * \brief Cipher wrappers.
- *
- * \author Adriaan de Jong <dejong@fox-it.com>
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_CIPHER_WRAP_H
-#define MBEDTLS_CIPHER_WRAP_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "cipher.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Base cipher information. The non-mode specific functions and values.
- */
-struct mbedtls_cipher_base_t
-{
-    /** Base Cipher type (e.g. MBEDTLS_CIPHER_ID_AES) */
-    mbedtls_cipher_id_t cipher;
-
-    /** Encrypt using ECB */
-    int (*ecb_func)( void *ctx, mbedtls_operation_t mode,
-                     const unsigned char *input, unsigned char *output );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-    /** Encrypt using CBC */
-    int (*cbc_func)( void *ctx, mbedtls_operation_t mode, size_t length,
-                     unsigned char *iv, const unsigned char *input,
-                     unsigned char *output );
-#endif
-
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-    /** Encrypt using CFB (Full length) */
-    int (*cfb_func)( void *ctx, mbedtls_operation_t mode, size_t length, size_t *iv_off,
-                     unsigned char *iv, const unsigned char *input,
-                     unsigned char *output );
-#endif
-
-#if defined(MBEDTLS_CIPHER_MODE_OFB)
-    /** Encrypt using OFB (Full length) */
-    int (*ofb_func)( void *ctx, size_t length, size_t *iv_off,
-                     unsigned char *iv,
-                     const unsigned char *input,
-                     unsigned char *output );
-#endif
-
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-    /** Encrypt using CTR */
-    int (*ctr_func)( void *ctx, size_t length, size_t *nc_off,
-                     unsigned char *nonce_counter, unsigned char *stream_block,
-                     const unsigned char *input, unsigned char *output );
-#endif
-
-#if defined(MBEDTLS_CIPHER_MODE_XTS)
-    /** Encrypt or decrypt using XTS. */
-    int (*xts_func)( void *ctx, mbedtls_operation_t mode, size_t length,
-                     const unsigned char data_unit[16],
-                     const unsigned char *input, unsigned char *output );
-#endif
-
-#if defined(MBEDTLS_CIPHER_MODE_STREAM)
-    /** Encrypt using STREAM */
-    int (*stream_func)( void *ctx, size_t length,
-                        const unsigned char *input, unsigned char *output );
-#endif
-
-    /** Set key for encryption purposes */
-    int (*setkey_enc_func)( void *ctx, const unsigned char *key,
-                            unsigned int key_bitlen );
-
-    /** Set key for decryption purposes */
-    int (*setkey_dec_func)( void *ctx, const unsigned char *key,
-                            unsigned int key_bitlen);
-
-    /** Allocate a new context */
-    void * (*ctx_alloc_func)( void );
-
-    /** Free the given context */
-    void (*ctx_free_func)( void *ctx );
-
-};
-
-typedef struct
-{
-    mbedtls_cipher_type_t type;
-    const mbedtls_cipher_info_t *info;
-} mbedtls_cipher_definition_t;
-
-extern const mbedtls_cipher_definition_t mbedtls_cipher_definitions[];
-
-extern int mbedtls_cipher_supported[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_CIPHER_WRAP_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/cmac.h b/tools/sdk/include/mbedtls/mbedtls/cmac.h
deleted file mode 100644
index 20747475679..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/cmac.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/**
- * \file cmac.h
- *
- * \brief This file contains CMAC definitions and functions.
- *
- * The Cipher-based Message Authentication Code (CMAC) Mode for
- * Authentication is defined in <em>RFC-4493: The AES-CMAC Algorithm</em>.
- */
-/*
- *  Copyright (C) 2015-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_CMAC_H
-#define MBEDTLS_CMAC_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "cipher.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* MBEDTLS_ERR_CMAC_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_CMAC_HW_ACCEL_FAILED -0x007A  /**< CMAC hardware accelerator failed. */
-
-#define MBEDTLS_AES_BLOCK_SIZE          16
-#define MBEDTLS_DES3_BLOCK_SIZE         8
-
-#if defined(MBEDTLS_AES_C)
-#define MBEDTLS_CIPHER_BLKSIZE_MAX      16  /**< The longest block used by CMAC is that of AES. */
-#else
-#define MBEDTLS_CIPHER_BLKSIZE_MAX      8   /**< The longest block used by CMAC is that of 3DES. */
-#endif
-
-#if !defined(MBEDTLS_CMAC_ALT)
-
-/**
- * The CMAC context structure.
- */
-struct mbedtls_cmac_context_t
-{
-    /** The internal state of the CMAC algorithm.  */
-    unsigned char       state[MBEDTLS_CIPHER_BLKSIZE_MAX];
-
-    /** Unprocessed data - either data that was not block aligned and is still
-     *  pending processing, or the final block. */
-    unsigned char       unprocessed_block[MBEDTLS_CIPHER_BLKSIZE_MAX];
-
-    /** The length of data pending processing. */
-    size_t              unprocessed_len;
-};
-
-#else  /* !MBEDTLS_CMAC_ALT */
-#include "cmac_alt.h"
-#endif /* !MBEDTLS_CMAC_ALT */
-
-/**
- * \brief               This function sets the CMAC key, and prepares to authenticate
- *                      the input data.
- *                      Must be called with an initialized cipher context.
- *
- * \param ctx           The cipher context used for the CMAC operation, initialized
- *                      as one of the following types: MBEDTLS_CIPHER_AES_128_ECB,
- *                      MBEDTLS_CIPHER_AES_192_ECB, MBEDTLS_CIPHER_AES_256_ECB,
- *                      or MBEDTLS_CIPHER_DES_EDE3_ECB.
- * \param key           The CMAC key.
- * \param keybits       The length of the CMAC key in bits.
- *                      Must be supported by the cipher.
- *
- * \return              \c 0 on success.
- * \return              A cipher-specific error code on failure.
- */
-int mbedtls_cipher_cmac_starts( mbedtls_cipher_context_t *ctx,
-                                const unsigned char *key, size_t keybits );
-
-/**
- * \brief               This function feeds an input buffer into an ongoing CMAC
- *                      computation.
- *
- *                      It is called between mbedtls_cipher_cmac_starts() or
- *                      mbedtls_cipher_cmac_reset(), and mbedtls_cipher_cmac_finish().
- *                      Can be called repeatedly.
- *
- * \param ctx           The cipher context used for the CMAC operation.
- * \param input         The buffer holding the input data.
- * \param ilen          The length of the input data.
- *
- * \return             \c 0 on success.
- * \return             #MBEDTLS_ERR_MD_BAD_INPUT_DATA
- *                     if parameter verification fails.
- */
-int mbedtls_cipher_cmac_update( mbedtls_cipher_context_t *ctx,
-                                const unsigned char *input, size_t ilen );
-
-/**
- * \brief               This function finishes the CMAC operation, and writes
- *                      the result to the output buffer.
- *
- *                      It is called after mbedtls_cipher_cmac_update().
- *                      It can be followed by mbedtls_cipher_cmac_reset() and
- *                      mbedtls_cipher_cmac_update(), or mbedtls_cipher_free().
- *
- * \param ctx           The cipher context used for the CMAC operation.
- * \param output        The output buffer for the CMAC checksum result.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_MD_BAD_INPUT_DATA
- *                      if parameter verification fails.
- */
-int mbedtls_cipher_cmac_finish( mbedtls_cipher_context_t *ctx,
-                                unsigned char *output );
-
-/**
- * \brief               This function prepares the authentication of another
- *                      message with the same key as the previous CMAC
- *                      operation.
- *
- *                      It is called after mbedtls_cipher_cmac_finish()
- *                      and before mbedtls_cipher_cmac_update().
- *
- * \param ctx           The cipher context used for the CMAC operation.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_MD_BAD_INPUT_DATA
- *                      if parameter verification fails.
- */
-int mbedtls_cipher_cmac_reset( mbedtls_cipher_context_t *ctx );
-
-/**
- * \brief               This function calculates the full generic CMAC
- *                      on the input buffer with the provided key.
- *
- *                      The function allocates the context, performs the
- *                      calculation, and frees the context.
- *
- *                      The CMAC result is calculated as
- *                      output = generic CMAC(cmac key, input buffer).
- *
- *
- * \param cipher_info   The cipher information.
- * \param key           The CMAC key.
- * \param keylen        The length of the CMAC key in bits.
- * \param input         The buffer holding the input data.
- * \param ilen          The length of the input data.
- * \param output        The buffer for the generic CMAC result.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_MD_BAD_INPUT_DATA
- *                      if parameter verification fails.
- */
-int mbedtls_cipher_cmac( const mbedtls_cipher_info_t *cipher_info,
-                         const unsigned char *key, size_t keylen,
-                         const unsigned char *input, size_t ilen,
-                         unsigned char *output );
-
-#if defined(MBEDTLS_AES_C)
-/**
- * \brief           This function implements the AES-CMAC-PRF-128 pseudorandom
- *                  function, as defined in
- *                  <em>RFC-4615: The Advanced Encryption Standard-Cipher-based
- *                  Message Authentication Code-Pseudo-Random Function-128
- *                  (AES-CMAC-PRF-128) Algorithm for the Internet Key
- *                  Exchange Protocol (IKE).</em>
- *
- * \param key       The key to use.
- * \param key_len   The key length in Bytes.
- * \param input     The buffer holding the input data.
- * \param in_len    The length of the input data in Bytes.
- * \param output    The buffer holding the generated 16 Bytes of
- *                  pseudorandom output.
- *
- * \return          \c 0 on success.
- */
-int mbedtls_aes_cmac_prf_128( const unsigned char *key, size_t key_len,
-                              const unsigned char *input, size_t in_len,
-                              unsigned char output[16] );
-#endif /* MBEDTLS_AES_C */
-
-#if defined(MBEDTLS_SELF_TEST) && ( defined(MBEDTLS_AES_C) || defined(MBEDTLS_DES_C) )
-/**
- * \brief          The CMAC checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_cmac_self_test( int verbose );
-#endif /* MBEDTLS_SELF_TEST && ( MBEDTLS_AES_C || MBEDTLS_DES_C ) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_CMAC_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h b/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h
deleted file mode 100644
index 71cc4f4d973..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/compat-1.3.h
+++ /dev/null
@@ -1,2558 +0,0 @@
-/**
- * \file compat-1.3.h
- *
- * \brief Compatibility definitions for using mbed TLS with client code written
- *  for the PolarSSL naming conventions.
- *
- * \deprecated Use the new names directly instead
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if ! defined(MBEDTLS_DEPRECATED_REMOVED)
-
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#warning "Including compat-1.3.h is deprecated"
-#endif
-
-#ifndef MBEDTLS_COMPAT13_H
-#define MBEDTLS_COMPAT13_H
-
-/*
- * config.h options
- */
-#if defined MBEDTLS_AESNI_C
-#define POLARSSL_AESNI_C MBEDTLS_AESNI_C
-#endif
-#if defined MBEDTLS_AES_ALT
-#define POLARSSL_AES_ALT MBEDTLS_AES_ALT
-#endif
-#if defined MBEDTLS_AES_C
-#define POLARSSL_AES_C MBEDTLS_AES_C
-#endif
-#if defined MBEDTLS_AES_ROM_TABLES
-#define POLARSSL_AES_ROM_TABLES MBEDTLS_AES_ROM_TABLES
-#endif
-#if defined MBEDTLS_ARC4_ALT
-#define POLARSSL_ARC4_ALT MBEDTLS_ARC4_ALT
-#endif
-#if defined MBEDTLS_ARC4_C
-#define POLARSSL_ARC4_C MBEDTLS_ARC4_C
-#endif
-#if defined MBEDTLS_ASN1_PARSE_C
-#define POLARSSL_ASN1_PARSE_C MBEDTLS_ASN1_PARSE_C
-#endif
-#if defined MBEDTLS_ASN1_WRITE_C
-#define POLARSSL_ASN1_WRITE_C MBEDTLS_ASN1_WRITE_C
-#endif
-#if defined MBEDTLS_BASE64_C
-#define POLARSSL_BASE64_C MBEDTLS_BASE64_C
-#endif
-#if defined MBEDTLS_BIGNUM_C
-#define POLARSSL_BIGNUM_C MBEDTLS_BIGNUM_C
-#endif
-#if defined MBEDTLS_BLOWFISH_ALT
-#define POLARSSL_BLOWFISH_ALT MBEDTLS_BLOWFISH_ALT
-#endif
-#if defined MBEDTLS_BLOWFISH_C
-#define POLARSSL_BLOWFISH_C MBEDTLS_BLOWFISH_C
-#endif
-#if defined MBEDTLS_CAMELLIA_ALT
-#define POLARSSL_CAMELLIA_ALT MBEDTLS_CAMELLIA_ALT
-#endif
-#if defined MBEDTLS_CAMELLIA_C
-#define POLARSSL_CAMELLIA_C MBEDTLS_CAMELLIA_C
-#endif
-#if defined MBEDTLS_CAMELLIA_SMALL_MEMORY
-#define POLARSSL_CAMELLIA_SMALL_MEMORY MBEDTLS_CAMELLIA_SMALL_MEMORY
-#endif
-#if defined MBEDTLS_CCM_C
-#define POLARSSL_CCM_C MBEDTLS_CCM_C
-#endif
-#if defined MBEDTLS_CERTS_C
-#define POLARSSL_CERTS_C MBEDTLS_CERTS_C
-#endif
-#if defined MBEDTLS_CIPHER_C
-#define POLARSSL_CIPHER_C MBEDTLS_CIPHER_C
-#endif
-#if defined MBEDTLS_CIPHER_MODE_CBC
-#define POLARSSL_CIPHER_MODE_CBC MBEDTLS_CIPHER_MODE_CBC
-#endif
-#if defined MBEDTLS_CIPHER_MODE_CFB
-#define POLARSSL_CIPHER_MODE_CFB MBEDTLS_CIPHER_MODE_CFB
-#endif
-#if defined MBEDTLS_CIPHER_MODE_CTR
-#define POLARSSL_CIPHER_MODE_CTR MBEDTLS_CIPHER_MODE_CTR
-#endif
-#if defined MBEDTLS_CIPHER_NULL_CIPHER
-#define POLARSSL_CIPHER_NULL_CIPHER MBEDTLS_CIPHER_NULL_CIPHER
-#endif
-#if defined MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
-#define POLARSSL_CIPHER_PADDING_ONE_AND_ZEROS MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
-#endif
-#if defined MBEDTLS_CIPHER_PADDING_PKCS7
-#define POLARSSL_CIPHER_PADDING_PKCS7 MBEDTLS_CIPHER_PADDING_PKCS7
-#endif
-#if defined MBEDTLS_CIPHER_PADDING_ZEROS
-#define POLARSSL_CIPHER_PADDING_ZEROS MBEDTLS_CIPHER_PADDING_ZEROS
-#endif
-#if defined MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
-#define POLARSSL_CIPHER_PADDING_ZEROS_AND_LEN MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
-#endif
-#if defined MBEDTLS_CTR_DRBG_C
-#define POLARSSL_CTR_DRBG_C MBEDTLS_CTR_DRBG_C
-#endif
-#if defined MBEDTLS_DEBUG_C
-#define POLARSSL_DEBUG_C MBEDTLS_DEBUG_C
-#endif
-#if defined MBEDTLS_DEPRECATED_REMOVED
-#define POLARSSL_DEPRECATED_REMOVED MBEDTLS_DEPRECATED_REMOVED
-#endif
-#if defined MBEDTLS_DEPRECATED_WARNING
-#define POLARSSL_DEPRECATED_WARNING MBEDTLS_DEPRECATED_WARNING
-#endif
-#if defined MBEDTLS_DES_ALT
-#define POLARSSL_DES_ALT MBEDTLS_DES_ALT
-#endif
-#if defined MBEDTLS_DES_C
-#define POLARSSL_DES_C MBEDTLS_DES_C
-#endif
-#if defined MBEDTLS_DHM_C
-#define POLARSSL_DHM_C MBEDTLS_DHM_C
-#endif
-#if defined MBEDTLS_ECDH_C
-#define POLARSSL_ECDH_C MBEDTLS_ECDH_C
-#endif
-#if defined MBEDTLS_ECDSA_C
-#define POLARSSL_ECDSA_C MBEDTLS_ECDSA_C
-#endif
-#if defined MBEDTLS_ECDSA_DETERMINISTIC
-#define POLARSSL_ECDSA_DETERMINISTIC MBEDTLS_ECDSA_DETERMINISTIC
-#endif
-#if defined MBEDTLS_ECP_C
-#define POLARSSL_ECP_C MBEDTLS_ECP_C
-#endif
-#if defined MBEDTLS_ECP_DP_BP256R1_ENABLED
-#define POLARSSL_ECP_DP_BP256R1_ENABLED MBEDTLS_ECP_DP_BP256R1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_BP384R1_ENABLED
-#define POLARSSL_ECP_DP_BP384R1_ENABLED MBEDTLS_ECP_DP_BP384R1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_BP512R1_ENABLED
-#define POLARSSL_ECP_DP_BP512R1_ENABLED MBEDTLS_ECP_DP_BP512R1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_CURVE25519_ENABLED
-#define POLARSSL_ECP_DP_M255_ENABLED MBEDTLS_ECP_DP_CURVE25519_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_SECP192K1_ENABLED
-#define POLARSSL_ECP_DP_SECP192K1_ENABLED MBEDTLS_ECP_DP_SECP192K1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_SECP192R1_ENABLED
-#define POLARSSL_ECP_DP_SECP192R1_ENABLED MBEDTLS_ECP_DP_SECP192R1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_SECP224K1_ENABLED
-#define POLARSSL_ECP_DP_SECP224K1_ENABLED MBEDTLS_ECP_DP_SECP224K1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_SECP224R1_ENABLED
-#define POLARSSL_ECP_DP_SECP224R1_ENABLED MBEDTLS_ECP_DP_SECP224R1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_SECP256K1_ENABLED
-#define POLARSSL_ECP_DP_SECP256K1_ENABLED MBEDTLS_ECP_DP_SECP256K1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#define POLARSSL_ECP_DP_SECP256R1_ENABLED MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_SECP384R1_ENABLED
-#define POLARSSL_ECP_DP_SECP384R1_ENABLED MBEDTLS_ECP_DP_SECP384R1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_DP_SECP521R1_ENABLED
-#define POLARSSL_ECP_DP_SECP521R1_ENABLED MBEDTLS_ECP_DP_SECP521R1_ENABLED
-#endif
-#if defined MBEDTLS_ECP_FIXED_POINT_OPTIM
-#define POLARSSL_ECP_FIXED_POINT_OPTIM MBEDTLS_ECP_FIXED_POINT_OPTIM
-#endif
-#if defined MBEDTLS_ECP_MAX_BITS
-#define POLARSSL_ECP_MAX_BITS MBEDTLS_ECP_MAX_BITS
-#endif
-#if defined MBEDTLS_ECP_NIST_OPTIM
-#define POLARSSL_ECP_NIST_OPTIM MBEDTLS_ECP_NIST_OPTIM
-#endif
-#if defined MBEDTLS_ECP_WINDOW_SIZE
-#define POLARSSL_ECP_WINDOW_SIZE MBEDTLS_ECP_WINDOW_SIZE
-#endif
-#if defined MBEDTLS_ENABLE_WEAK_CIPHERSUITES
-#define POLARSSL_ENABLE_WEAK_CIPHERSUITES MBEDTLS_ENABLE_WEAK_CIPHERSUITES
-#endif
-#if defined MBEDTLS_ENTROPY_C
-#define POLARSSL_ENTROPY_C MBEDTLS_ENTROPY_C
-#endif
-#if defined MBEDTLS_ENTROPY_FORCE_SHA256
-#define POLARSSL_ENTROPY_FORCE_SHA256 MBEDTLS_ENTROPY_FORCE_SHA256
-#endif
-#if defined MBEDTLS_ERROR_C
-#define POLARSSL_ERROR_C MBEDTLS_ERROR_C
-#endif
-#if defined MBEDTLS_ERROR_STRERROR_DUMMY
-#define POLARSSL_ERROR_STRERROR_DUMMY MBEDTLS_ERROR_STRERROR_DUMMY
-#endif
-#if defined MBEDTLS_FS_IO
-#define POLARSSL_FS_IO MBEDTLS_FS_IO
-#endif
-#if defined MBEDTLS_GCM_C
-#define POLARSSL_GCM_C MBEDTLS_GCM_C
-#endif
-#if defined MBEDTLS_GENPRIME
-#define POLARSSL_GENPRIME MBEDTLS_GENPRIME
-#endif
-#if defined MBEDTLS_HAVEGE_C
-#define POLARSSL_HAVEGE_C MBEDTLS_HAVEGE_C
-#endif
-#if defined MBEDTLS_HAVE_ASM
-#define POLARSSL_HAVE_ASM MBEDTLS_HAVE_ASM
-#endif
-#if defined MBEDTLS_HAVE_SSE2
-#define POLARSSL_HAVE_SSE2 MBEDTLS_HAVE_SSE2
-#endif
-#if defined MBEDTLS_HAVE_TIME
-#define POLARSSL_HAVE_TIME MBEDTLS_HAVE_TIME
-#endif
-#if defined MBEDTLS_HMAC_DRBG_C
-#define POLARSSL_HMAC_DRBG_C MBEDTLS_HMAC_DRBG_C
-#endif
-#if defined MBEDTLS_HMAC_DRBG_MAX_INPUT
-#define POLARSSL_HMAC_DRBG_MAX_INPUT MBEDTLS_HMAC_DRBG_MAX_INPUT
-#endif
-#if defined MBEDTLS_HMAC_DRBG_MAX_REQUEST
-#define POLARSSL_HMAC_DRBG_MAX_REQUEST MBEDTLS_HMAC_DRBG_MAX_REQUEST
-#endif
-#if defined MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT
-#define POLARSSL_HMAC_DRBG_MAX_SEED_INPUT MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT
-#endif
-#if defined MBEDTLS_HMAC_DRBG_RESEED_INTERVAL
-#define POLARSSL_HMAC_DRBG_RESEED_INTERVAL MBEDTLS_HMAC_DRBG_RESEED_INTERVAL
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
-#define POLARSSL_KEY_EXCHANGE_DHE_PSK_ENABLED MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
-#define POLARSSL_KEY_EXCHANGE_DHE_RSA_ENABLED MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
-#define POLARSSL_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
-#define POLARSSL_KEY_EXCHANGE_ECDHE_PSK_ENABLED MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
-#define POLARSSL_KEY_EXCHANGE_ECDHE_RSA_ENABLED MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
-#define POLARSSL_KEY_EXCHANGE_ECDH_ECDSA_ENABLED MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
-#define POLARSSL_KEY_EXCHANGE_ECDH_RSA_ENABLED MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-#define POLARSSL_KEY_EXCHANGE_PSK_ENABLED MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-#define POLARSSL_KEY_EXCHANGE_RSA_ENABLED MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-#endif
-#if defined MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
-#define POLARSSL_KEY_EXCHANGE_RSA_PSK_ENABLED MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
-#endif
-#if defined MBEDTLS_MD2_ALT
-#define POLARSSL_MD2_ALT MBEDTLS_MD2_ALT
-#endif
-#if defined MBEDTLS_MD2_C
-#define POLARSSL_MD2_C MBEDTLS_MD2_C
-#endif
-#if defined MBEDTLS_MD2_PROCESS_ALT
-#define POLARSSL_MD2_PROCESS_ALT MBEDTLS_MD2_PROCESS_ALT
-#endif
-#if defined MBEDTLS_MD4_ALT
-#define POLARSSL_MD4_ALT MBEDTLS_MD4_ALT
-#endif
-#if defined MBEDTLS_MD4_C
-#define POLARSSL_MD4_C MBEDTLS_MD4_C
-#endif
-#if defined MBEDTLS_MD4_PROCESS_ALT
-#define POLARSSL_MD4_PROCESS_ALT MBEDTLS_MD4_PROCESS_ALT
-#endif
-#if defined MBEDTLS_MD5_ALT
-#define POLARSSL_MD5_ALT MBEDTLS_MD5_ALT
-#endif
-#if defined MBEDTLS_MD5_C
-#define POLARSSL_MD5_C MBEDTLS_MD5_C
-#endif
-#if defined MBEDTLS_MD5_PROCESS_ALT
-#define POLARSSL_MD5_PROCESS_ALT MBEDTLS_MD5_PROCESS_ALT
-#endif
-#if defined MBEDTLS_MD_C
-#define POLARSSL_MD_C MBEDTLS_MD_C
-#endif
-#if defined MBEDTLS_MEMORY_ALIGN_MULTIPLE
-#define POLARSSL_MEMORY_ALIGN_MULTIPLE MBEDTLS_MEMORY_ALIGN_MULTIPLE
-#endif
-#if defined MBEDTLS_MEMORY_BACKTRACE
-#define POLARSSL_MEMORY_BACKTRACE MBEDTLS_MEMORY_BACKTRACE
-#endif
-#if defined MBEDTLS_MEMORY_BUFFER_ALLOC_C
-#define POLARSSL_MEMORY_BUFFER_ALLOC_C MBEDTLS_MEMORY_BUFFER_ALLOC_C
-#endif
-#if defined MBEDTLS_MEMORY_DEBUG
-#define POLARSSL_MEMORY_DEBUG MBEDTLS_MEMORY_DEBUG
-#endif
-#if defined MBEDTLS_MPI_MAX_SIZE
-#define POLARSSL_MPI_MAX_SIZE MBEDTLS_MPI_MAX_SIZE
-#endif
-#if defined MBEDTLS_MPI_WINDOW_SIZE
-#define POLARSSL_MPI_WINDOW_SIZE MBEDTLS_MPI_WINDOW_SIZE
-#endif
-#if defined MBEDTLS_NET_C
-#define POLARSSL_NET_C MBEDTLS_NET_C
-#endif
-#if defined MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-#define POLARSSL_NO_DEFAULT_ENTROPY_SOURCES MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-#endif
-#if defined MBEDTLS_NO_PLATFORM_ENTROPY
-#define POLARSSL_NO_PLATFORM_ENTROPY MBEDTLS_NO_PLATFORM_ENTROPY
-#endif
-#if defined MBEDTLS_OID_C
-#define POLARSSL_OID_C MBEDTLS_OID_C
-#endif
-#if defined MBEDTLS_PADLOCK_C
-#define POLARSSL_PADLOCK_C MBEDTLS_PADLOCK_C
-#endif
-#if defined MBEDTLS_PEM_PARSE_C
-#define POLARSSL_PEM_PARSE_C MBEDTLS_PEM_PARSE_C
-#endif
-#if defined MBEDTLS_PEM_WRITE_C
-#define POLARSSL_PEM_WRITE_C MBEDTLS_PEM_WRITE_C
-#endif
-#if defined MBEDTLS_PKCS11_C
-#define POLARSSL_PKCS11_C MBEDTLS_PKCS11_C
-#endif
-#if defined MBEDTLS_PKCS12_C
-#define POLARSSL_PKCS12_C MBEDTLS_PKCS12_C
-#endif
-#if defined MBEDTLS_PKCS1_V15
-#define POLARSSL_PKCS1_V15 MBEDTLS_PKCS1_V15
-#endif
-#if defined MBEDTLS_PKCS1_V21
-#define POLARSSL_PKCS1_V21 MBEDTLS_PKCS1_V21
-#endif
-#if defined MBEDTLS_PKCS5_C
-#define POLARSSL_PKCS5_C MBEDTLS_PKCS5_C
-#endif
-#if defined MBEDTLS_PK_C
-#define POLARSSL_PK_C MBEDTLS_PK_C
-#endif
-#if defined MBEDTLS_PK_PARSE_C
-#define POLARSSL_PK_PARSE_C MBEDTLS_PK_PARSE_C
-#endif
-#if defined MBEDTLS_PK_PARSE_EC_EXTENDED
-#define POLARSSL_PK_PARSE_EC_EXTENDED MBEDTLS_PK_PARSE_EC_EXTENDED
-#endif
-#if defined MBEDTLS_PK_RSA_ALT_SUPPORT
-#define POLARSSL_PK_RSA_ALT_SUPPORT MBEDTLS_PK_RSA_ALT_SUPPORT
-#endif
-#if defined MBEDTLS_PK_WRITE_C
-#define POLARSSL_PK_WRITE_C MBEDTLS_PK_WRITE_C
-#endif
-#if defined MBEDTLS_PLATFORM_C
-#define POLARSSL_PLATFORM_C MBEDTLS_PLATFORM_C
-#endif
-#if defined MBEDTLS_PLATFORM_EXIT_ALT
-#define POLARSSL_PLATFORM_EXIT_ALT MBEDTLS_PLATFORM_EXIT_ALT
-#endif
-#if defined MBEDTLS_PLATFORM_EXIT_MACRO
-#define POLARSSL_PLATFORM_EXIT_MACRO MBEDTLS_PLATFORM_EXIT_MACRO
-#endif
-#if defined MBEDTLS_PLATFORM_FPRINTF_ALT
-#define POLARSSL_PLATFORM_FPRINTF_ALT MBEDTLS_PLATFORM_FPRINTF_ALT
-#endif
-#if defined MBEDTLS_PLATFORM_FPRINTF_MACRO
-#define POLARSSL_PLATFORM_FPRINTF_MACRO MBEDTLS_PLATFORM_FPRINTF_MACRO
-#endif
-#if defined MBEDTLS_PLATFORM_FREE_MACRO
-#define POLARSSL_PLATFORM_FREE_MACRO MBEDTLS_PLATFORM_FREE_MACRO
-#endif
-#if defined MBEDTLS_PLATFORM_MEMORY
-#define POLARSSL_PLATFORM_MEMORY MBEDTLS_PLATFORM_MEMORY
-#endif
-#if defined MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-#define POLARSSL_PLATFORM_NO_STD_FUNCTIONS MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-#endif
-#if defined MBEDTLS_PLATFORM_PRINTF_ALT
-#define POLARSSL_PLATFORM_PRINTF_ALT MBEDTLS_PLATFORM_PRINTF_ALT
-#endif
-#if defined MBEDTLS_PLATFORM_PRINTF_MACRO
-#define POLARSSL_PLATFORM_PRINTF_MACRO MBEDTLS_PLATFORM_PRINTF_MACRO
-#endif
-#if defined MBEDTLS_PLATFORM_SNPRINTF_ALT
-#define POLARSSL_PLATFORM_SNPRINTF_ALT MBEDTLS_PLATFORM_SNPRINTF_ALT
-#endif
-#if defined MBEDTLS_PLATFORM_SNPRINTF_MACRO
-#define POLARSSL_PLATFORM_SNPRINTF_MACRO MBEDTLS_PLATFORM_SNPRINTF_MACRO
-#endif
-#if defined MBEDTLS_PLATFORM_STD_EXIT
-#define POLARSSL_PLATFORM_STD_EXIT MBEDTLS_PLATFORM_STD_EXIT
-#endif
-#if defined MBEDTLS_PLATFORM_STD_FPRINTF
-#define POLARSSL_PLATFORM_STD_FPRINTF MBEDTLS_PLATFORM_STD_FPRINTF
-#endif
-#if defined MBEDTLS_PLATFORM_STD_FREE
-#define POLARSSL_PLATFORM_STD_FREE MBEDTLS_PLATFORM_STD_FREE
-#endif
-#if defined MBEDTLS_PLATFORM_STD_MEM_HDR
-#define POLARSSL_PLATFORM_STD_MEM_HDR MBEDTLS_PLATFORM_STD_MEM_HDR
-#endif
-#if defined MBEDTLS_PLATFORM_STD_PRINTF
-#define POLARSSL_PLATFORM_STD_PRINTF MBEDTLS_PLATFORM_STD_PRINTF
-#endif
-#if defined MBEDTLS_PLATFORM_STD_SNPRINTF
-#define POLARSSL_PLATFORM_STD_SNPRINTF MBEDTLS_PLATFORM_STD_SNPRINTF
-#endif
-#if defined MBEDTLS_PSK_MAX_LEN
-#define POLARSSL_PSK_MAX_LEN MBEDTLS_PSK_MAX_LEN
-#endif
-#if defined MBEDTLS_REMOVE_ARC4_CIPHERSUITES
-#define POLARSSL_REMOVE_ARC4_CIPHERSUITES MBEDTLS_REMOVE_ARC4_CIPHERSUITES
-#endif
-#if defined MBEDTLS_RIPEMD160_ALT
-#define POLARSSL_RIPEMD160_ALT MBEDTLS_RIPEMD160_ALT
-#endif
-#if defined MBEDTLS_RIPEMD160_C
-#define POLARSSL_RIPEMD160_C MBEDTLS_RIPEMD160_C
-#endif
-#if defined MBEDTLS_RIPEMD160_PROCESS_ALT
-#define POLARSSL_RIPEMD160_PROCESS_ALT MBEDTLS_RIPEMD160_PROCESS_ALT
-#endif
-#if defined MBEDTLS_RSA_C
-#define POLARSSL_RSA_C MBEDTLS_RSA_C
-#endif
-#if defined MBEDTLS_RSA_NO_CRT
-#define POLARSSL_RSA_NO_CRT MBEDTLS_RSA_NO_CRT
-#endif
-#if defined MBEDTLS_SELF_TEST
-#define POLARSSL_SELF_TEST MBEDTLS_SELF_TEST
-#endif
-#if defined MBEDTLS_SHA1_ALT
-#define POLARSSL_SHA1_ALT MBEDTLS_SHA1_ALT
-#endif
-#if defined MBEDTLS_SHA1_C
-#define POLARSSL_SHA1_C MBEDTLS_SHA1_C
-#endif
-#if defined MBEDTLS_SHA1_PROCESS_ALT
-#define POLARSSL_SHA1_PROCESS_ALT MBEDTLS_SHA1_PROCESS_ALT
-#endif
-#if defined MBEDTLS_SHA256_ALT
-#define POLARSSL_SHA256_ALT MBEDTLS_SHA256_ALT
-#endif
-#if defined MBEDTLS_SHA256_C
-#define POLARSSL_SHA256_C MBEDTLS_SHA256_C
-#endif
-#if defined MBEDTLS_SHA256_PROCESS_ALT
-#define POLARSSL_SHA256_PROCESS_ALT MBEDTLS_SHA256_PROCESS_ALT
-#endif
-#if defined MBEDTLS_SHA512_ALT
-#define POLARSSL_SHA512_ALT MBEDTLS_SHA512_ALT
-#endif
-#if defined MBEDTLS_SHA512_C
-#define POLARSSL_SHA512_C MBEDTLS_SHA512_C
-#endif
-#if defined MBEDTLS_SHA512_PROCESS_ALT
-#define POLARSSL_SHA512_PROCESS_ALT MBEDTLS_SHA512_PROCESS_ALT
-#endif
-#if defined MBEDTLS_SSL_ALL_ALERT_MESSAGES
-#define POLARSSL_SSL_ALL_ALERT_MESSAGES MBEDTLS_SSL_ALL_ALERT_MESSAGES
-#endif
-#if defined MBEDTLS_SSL_ALPN
-#define POLARSSL_SSL_ALPN MBEDTLS_SSL_ALPN
-#endif
-#if defined MBEDTLS_SSL_CACHE_C
-#define POLARSSL_SSL_CACHE_C MBEDTLS_SSL_CACHE_C
-#endif
-#if defined MBEDTLS_SSL_CBC_RECORD_SPLITTING
-#define POLARSSL_SSL_CBC_RECORD_SPLITTING MBEDTLS_SSL_CBC_RECORD_SPLITTING
-#endif
-#if defined MBEDTLS_SSL_CLI_C
-#define POLARSSL_SSL_CLI_C MBEDTLS_SSL_CLI_C
-#endif
-#if defined MBEDTLS_SSL_COOKIE_C
-#define POLARSSL_SSL_COOKIE_C MBEDTLS_SSL_COOKIE_C
-#endif
-#if defined MBEDTLS_SSL_COOKIE_TIMEOUT
-#define POLARSSL_SSL_COOKIE_TIMEOUT MBEDTLS_SSL_COOKIE_TIMEOUT
-#endif
-#if defined MBEDTLS_SSL_DEBUG_ALL
-#define POLARSSL_SSL_DEBUG_ALL MBEDTLS_SSL_DEBUG_ALL
-#endif
-#if defined MBEDTLS_SSL_DTLS_ANTI_REPLAY
-#define POLARSSL_SSL_DTLS_ANTI_REPLAY MBEDTLS_SSL_DTLS_ANTI_REPLAY
-#endif
-#if defined MBEDTLS_SSL_DTLS_BADMAC_LIMIT
-#define POLARSSL_SSL_DTLS_BADMAC_LIMIT MBEDTLS_SSL_DTLS_BADMAC_LIMIT
-#endif
-#if defined MBEDTLS_SSL_DTLS_HELLO_VERIFY
-#define POLARSSL_SSL_DTLS_HELLO_VERIFY MBEDTLS_SSL_DTLS_HELLO_VERIFY
-#endif
-#if defined MBEDTLS_SSL_ENCRYPT_THEN_MAC
-#define POLARSSL_SSL_ENCRYPT_THEN_MAC MBEDTLS_SSL_ENCRYPT_THEN_MAC
-#endif
-#if defined MBEDTLS_SSL_EXTENDED_MASTER_SECRET
-#define POLARSSL_SSL_EXTENDED_MASTER_SECRET MBEDTLS_SSL_EXTENDED_MASTER_SECRET
-#endif
-#if defined MBEDTLS_SSL_FALLBACK_SCSV
-#define POLARSSL_SSL_FALLBACK_SCSV MBEDTLS_SSL_FALLBACK_SCSV
-#endif
-#if defined MBEDTLS_SSL_HW_RECORD_ACCEL
-#define POLARSSL_SSL_HW_RECORD_ACCEL MBEDTLS_SSL_HW_RECORD_ACCEL
-#endif
-#if defined MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
-#define POLARSSL_SSL_MAX_FRAGMENT_LENGTH MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
-#endif
-#if defined MBEDTLS_SSL_PROTO_DTLS
-#define POLARSSL_SSL_PROTO_DTLS MBEDTLS_SSL_PROTO_DTLS
-#endif
-#if defined MBEDTLS_SSL_PROTO_SSL3
-#define POLARSSL_SSL_PROTO_SSL3 MBEDTLS_SSL_PROTO_SSL3
-#endif
-#if defined MBEDTLS_SSL_PROTO_TLS1
-#define POLARSSL_SSL_PROTO_TLS1 MBEDTLS_SSL_PROTO_TLS1
-#endif
-#if defined MBEDTLS_SSL_PROTO_TLS1_1
-#define POLARSSL_SSL_PROTO_TLS1_1 MBEDTLS_SSL_PROTO_TLS1_1
-#endif
-#if defined MBEDTLS_SSL_PROTO_TLS1_2
-#define POLARSSL_SSL_PROTO_TLS1_2 MBEDTLS_SSL_PROTO_TLS1_2
-#endif
-#if defined MBEDTLS_SSL_RENEGOTIATION
-#define POLARSSL_SSL_RENEGOTIATION MBEDTLS_SSL_RENEGOTIATION
-#endif
-#if defined MBEDTLS_SSL_SERVER_NAME_INDICATION
-#define POLARSSL_SSL_SERVER_NAME_INDICATION MBEDTLS_SSL_SERVER_NAME_INDICATION
-#endif
-#if defined MBEDTLS_SSL_SESSION_TICKETS
-#define POLARSSL_SSL_SESSION_TICKETS MBEDTLS_SSL_SESSION_TICKETS
-#endif
-#if defined MBEDTLS_SSL_SRV_C
-#define POLARSSL_SSL_SRV_C MBEDTLS_SSL_SRV_C
-#endif
-#if defined MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
-#define POLARSSL_SSL_SRV_RESPECT_CLIENT_PREFERENCE MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
-#endif
-#if defined MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
-#define POLARSSL_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
-#endif
-#if defined MBEDTLS_SSL_TLS_C
-#define POLARSSL_SSL_TLS_C MBEDTLS_SSL_TLS_C
-#endif
-#if defined MBEDTLS_SSL_TRUNCATED_HMAC
-#define POLARSSL_SSL_TRUNCATED_HMAC MBEDTLS_SSL_TRUNCATED_HMAC
-#endif
-#if defined MBEDTLS_THREADING_ALT
-#define POLARSSL_THREADING_ALT MBEDTLS_THREADING_ALT
-#endif
-#if defined MBEDTLS_THREADING_C
-#define POLARSSL_THREADING_C MBEDTLS_THREADING_C
-#endif
-#if defined MBEDTLS_THREADING_PTHREAD
-#define POLARSSL_THREADING_PTHREAD MBEDTLS_THREADING_PTHREAD
-#endif
-#if defined MBEDTLS_TIMING_ALT
-#define POLARSSL_TIMING_ALT MBEDTLS_TIMING_ALT
-#endif
-#if defined MBEDTLS_TIMING_C
-#define POLARSSL_TIMING_C MBEDTLS_TIMING_C
-#endif
-#if defined MBEDTLS_VERSION_C
-#define POLARSSL_VERSION_C MBEDTLS_VERSION_C
-#endif
-#if defined MBEDTLS_VERSION_FEATURES
-#define POLARSSL_VERSION_FEATURES MBEDTLS_VERSION_FEATURES
-#endif
-#if defined MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
-#define POLARSSL_X509_ALLOW_EXTENSIONS_NON_V3 MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
-#endif
-#if defined MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
-#define POLARSSL_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
-#endif
-#if defined MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
-#define POLARSSL_X509_CHECK_EXTENDED_KEY_USAGE MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
-#endif
-#if defined MBEDTLS_X509_CHECK_KEY_USAGE
-#define POLARSSL_X509_CHECK_KEY_USAGE MBEDTLS_X509_CHECK_KEY_USAGE
-#endif
-#if defined MBEDTLS_X509_CREATE_C
-#define POLARSSL_X509_CREATE_C MBEDTLS_X509_CREATE_C
-#endif
-#if defined MBEDTLS_X509_CRL_PARSE_C
-#define POLARSSL_X509_CRL_PARSE_C MBEDTLS_X509_CRL_PARSE_C
-#endif
-#if defined MBEDTLS_X509_CRT_PARSE_C
-#define POLARSSL_X509_CRT_PARSE_C MBEDTLS_X509_CRT_PARSE_C
-#endif
-#if defined MBEDTLS_X509_CRT_WRITE_C
-#define POLARSSL_X509_CRT_WRITE_C MBEDTLS_X509_CRT_WRITE_C
-#endif
-#if defined MBEDTLS_X509_CSR_PARSE_C
-#define POLARSSL_X509_CSR_PARSE_C MBEDTLS_X509_CSR_PARSE_C
-#endif
-#if defined MBEDTLS_X509_CSR_WRITE_C
-#define POLARSSL_X509_CSR_WRITE_C MBEDTLS_X509_CSR_WRITE_C
-#endif
-#if defined MBEDTLS_X509_MAX_INTERMEDIATE_CA
-#define POLARSSL_X509_MAX_INTERMEDIATE_CA MBEDTLS_X509_MAX_INTERMEDIATE_CA
-#endif
-#if defined MBEDTLS_X509_RSASSA_PSS_SUPPORT
-#define POLARSSL_X509_RSASSA_PSS_SUPPORT MBEDTLS_X509_RSASSA_PSS_SUPPORT
-#endif
-#if defined MBEDTLS_X509_USE_C
-#define POLARSSL_X509_USE_C MBEDTLS_X509_USE_C
-#endif
-#if defined MBEDTLS_XTEA_ALT
-#define POLARSSL_XTEA_ALT MBEDTLS_XTEA_ALT
-#endif
-#if defined MBEDTLS_XTEA_C
-#define POLARSSL_XTEA_C MBEDTLS_XTEA_C
-#endif
-#if defined MBEDTLS_ZLIB_SUPPORT
-#define POLARSSL_ZLIB_SUPPORT MBEDTLS_ZLIB_SUPPORT
-#endif
-
-/*
- * Misc names (macros, types, functions, enum constants...)
- */
-#define AES_DECRYPT MBEDTLS_AES_DECRYPT
-#define AES_ENCRYPT MBEDTLS_AES_ENCRYPT
-#define ASN1_BIT_STRING MBEDTLS_ASN1_BIT_STRING
-#define ASN1_BMP_STRING MBEDTLS_ASN1_BMP_STRING
-#define ASN1_BOOLEAN MBEDTLS_ASN1_BOOLEAN
-#define ASN1_CHK_ADD MBEDTLS_ASN1_CHK_ADD
-#define ASN1_CONSTRUCTED MBEDTLS_ASN1_CONSTRUCTED
-#define ASN1_CONTEXT_SPECIFIC MBEDTLS_ASN1_CONTEXT_SPECIFIC
-#define ASN1_GENERALIZED_TIME MBEDTLS_ASN1_GENERALIZED_TIME
-#define ASN1_IA5_STRING MBEDTLS_ASN1_IA5_STRING
-#define ASN1_INTEGER MBEDTLS_ASN1_INTEGER
-#define ASN1_NULL MBEDTLS_ASN1_NULL
-#define ASN1_OCTET_STRING MBEDTLS_ASN1_OCTET_STRING
-#define ASN1_OID MBEDTLS_ASN1_OID
-#define ASN1_PRIMITIVE MBEDTLS_ASN1_PRIMITIVE
-#define ASN1_PRINTABLE_STRING MBEDTLS_ASN1_PRINTABLE_STRING
-#define ASN1_SEQUENCE MBEDTLS_ASN1_SEQUENCE
-#define ASN1_SET MBEDTLS_ASN1_SET
-#define ASN1_T61_STRING MBEDTLS_ASN1_T61_STRING
-#define ASN1_UNIVERSAL_STRING MBEDTLS_ASN1_UNIVERSAL_STRING
-#define ASN1_UTC_TIME MBEDTLS_ASN1_UTC_TIME
-#define ASN1_UTF8_STRING MBEDTLS_ASN1_UTF8_STRING
-#define BADCERT_CN_MISMATCH MBEDTLS_X509_BADCERT_CN_MISMATCH
-#define BADCERT_EXPIRED MBEDTLS_X509_BADCERT_EXPIRED
-#define BADCERT_FUTURE MBEDTLS_X509_BADCERT_FUTURE
-#define BADCERT_MISSING MBEDTLS_X509_BADCERT_MISSING
-#define BADCERT_NOT_TRUSTED MBEDTLS_X509_BADCERT_NOT_TRUSTED
-#define BADCERT_OTHER MBEDTLS_X509_BADCERT_OTHER
-#define BADCERT_REVOKED MBEDTLS_X509_BADCERT_REVOKED
-#define BADCERT_SKIP_VERIFY MBEDTLS_X509_BADCERT_SKIP_VERIFY
-#define BADCRL_EXPIRED MBEDTLS_X509_BADCRL_EXPIRED
-#define BADCRL_FUTURE MBEDTLS_X509_BADCRL_FUTURE
-#define BADCRL_NOT_TRUSTED MBEDTLS_X509_BADCRL_NOT_TRUSTED
-#define BLOWFISH_BLOCKSIZE MBEDTLS_BLOWFISH_BLOCKSIZE
-#define BLOWFISH_DECRYPT MBEDTLS_BLOWFISH_DECRYPT
-#define BLOWFISH_ENCRYPT MBEDTLS_BLOWFISH_ENCRYPT
-#define BLOWFISH_MAX_KEY MBEDTLS_BLOWFISH_MAX_KEY_BITS
-#define BLOWFISH_MIN_KEY MBEDTLS_BLOWFISH_MIN_KEY_BITS
-#define BLOWFISH_ROUNDS MBEDTLS_BLOWFISH_ROUNDS
-#define CAMELLIA_DECRYPT MBEDTLS_CAMELLIA_DECRYPT
-#define CAMELLIA_ENCRYPT MBEDTLS_CAMELLIA_ENCRYPT
-#define COLLECT_SIZE MBEDTLS_HAVEGE_COLLECT_SIZE
-#define CTR_DRBG_BLOCKSIZE MBEDTLS_CTR_DRBG_BLOCKSIZE
-#define CTR_DRBG_ENTROPY_LEN MBEDTLS_CTR_DRBG_ENTROPY_LEN
-#define CTR_DRBG_KEYBITS MBEDTLS_CTR_DRBG_KEYBITS
-#define CTR_DRBG_KEYSIZE MBEDTLS_CTR_DRBG_KEYSIZE
-#define CTR_DRBG_MAX_INPUT MBEDTLS_CTR_DRBG_MAX_INPUT
-#define CTR_DRBG_MAX_REQUEST MBEDTLS_CTR_DRBG_MAX_REQUEST
-#define CTR_DRBG_MAX_SEED_INPUT MBEDTLS_CTR_DRBG_MAX_SEED_INPUT
-#define CTR_DRBG_PR_OFF MBEDTLS_CTR_DRBG_PR_OFF
-#define CTR_DRBG_PR_ON MBEDTLS_CTR_DRBG_PR_ON
-#define CTR_DRBG_RESEED_INTERVAL MBEDTLS_CTR_DRBG_RESEED_INTERVAL
-#define CTR_DRBG_SEEDLEN MBEDTLS_CTR_DRBG_SEEDLEN
-#define DEPRECATED MBEDTLS_DEPRECATED
-#define DES_DECRYPT MBEDTLS_DES_DECRYPT
-#define DES_ENCRYPT MBEDTLS_DES_ENCRYPT
-#define DES_KEY_SIZE MBEDTLS_DES_KEY_SIZE
-#define ENTROPY_BLOCK_SIZE MBEDTLS_ENTROPY_BLOCK_SIZE
-#define ENTROPY_MAX_GATHER MBEDTLS_ENTROPY_MAX_GATHER
-#define ENTROPY_MAX_SEED_SIZE MBEDTLS_ENTROPY_MAX_SEED_SIZE
-#define ENTROPY_MAX_SOURCES MBEDTLS_ENTROPY_MAX_SOURCES
-#define ENTROPY_MIN_HARDCLOCK MBEDTLS_ENTROPY_MIN_HARDCLOCK
-#define ENTROPY_MIN_HAVEGE MBEDTLS_ENTROPY_MIN_HAVEGE
-#define ENTROPY_MIN_PLATFORM MBEDTLS_ENTROPY_MIN_PLATFORM
-#define ENTROPY_SOURCE_MANUAL MBEDTLS_ENTROPY_SOURCE_MANUAL
-#define EXT_AUTHORITY_KEY_IDENTIFIER MBEDTLS_X509_EXT_AUTHORITY_KEY_IDENTIFIER
-#define EXT_BASIC_CONSTRAINTS MBEDTLS_X509_EXT_BASIC_CONSTRAINTS
-#define EXT_CERTIFICATE_POLICIES MBEDTLS_X509_EXT_CERTIFICATE_POLICIES
-#define EXT_CRL_DISTRIBUTION_POINTS MBEDTLS_X509_EXT_CRL_DISTRIBUTION_POINTS
-#define EXT_EXTENDED_KEY_USAGE MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE
-#define EXT_FRESHEST_CRL MBEDTLS_X509_EXT_FRESHEST_CRL
-#define EXT_INIHIBIT_ANYPOLICY MBEDTLS_X509_EXT_INIHIBIT_ANYPOLICY
-#define EXT_ISSUER_ALT_NAME MBEDTLS_X509_EXT_ISSUER_ALT_NAME
-#define EXT_KEY_USAGE MBEDTLS_X509_EXT_KEY_USAGE
-#define EXT_NAME_CONSTRAINTS MBEDTLS_X509_EXT_NAME_CONSTRAINTS
-#define EXT_NS_CERT_TYPE MBEDTLS_X509_EXT_NS_CERT_TYPE
-#define EXT_POLICY_CONSTRAINTS MBEDTLS_X509_EXT_POLICY_CONSTRAINTS
-#define EXT_POLICY_MAPPINGS MBEDTLS_X509_EXT_POLICY_MAPPINGS
-#define EXT_SUBJECT_ALT_NAME MBEDTLS_X509_EXT_SUBJECT_ALT_NAME
-#define EXT_SUBJECT_DIRECTORY_ATTRS MBEDTLS_X509_EXT_SUBJECT_DIRECTORY_ATTRS
-#define EXT_SUBJECT_KEY_IDENTIFIER MBEDTLS_X509_EXT_SUBJECT_KEY_IDENTIFIER
-#define GCM_DECRYPT MBEDTLS_GCM_DECRYPT
-#define GCM_ENCRYPT MBEDTLS_GCM_ENCRYPT
-#define KU_CRL_SIGN MBEDTLS_X509_KU_CRL_SIGN
-#define KU_DATA_ENCIPHERMENT MBEDTLS_X509_KU_DATA_ENCIPHERMENT
-#define KU_DIGITAL_SIGNATURE MBEDTLS_X509_KU_DIGITAL_SIGNATURE
-#define KU_KEY_AGREEMENT MBEDTLS_X509_KU_KEY_AGREEMENT
-#define KU_KEY_CERT_SIGN MBEDTLS_X509_KU_KEY_CERT_SIGN
-#define KU_KEY_ENCIPHERMENT MBEDTLS_X509_KU_KEY_ENCIPHERMENT
-#define KU_NON_REPUDIATION MBEDTLS_X509_KU_NON_REPUDIATION
-#define LN_2_DIV_LN_10_SCALE100 MBEDTLS_LN_2_DIV_LN_10_SCALE100
-#define MEMORY_VERIFY_ALLOC MBEDTLS_MEMORY_VERIFY_ALLOC
-#define MEMORY_VERIFY_ALWAYS MBEDTLS_MEMORY_VERIFY_ALWAYS
-#define MEMORY_VERIFY_FREE MBEDTLS_MEMORY_VERIFY_FREE
-#define MEMORY_VERIFY_NONE MBEDTLS_MEMORY_VERIFY_NONE
-#define MPI_CHK MBEDTLS_MPI_CHK
-#define NET_PROTO_TCP MBEDTLS_NET_PROTO_TCP
-#define NET_PROTO_UDP MBEDTLS_NET_PROTO_UDP
-#define NS_CERT_TYPE_EMAIL MBEDTLS_X509_NS_CERT_TYPE_EMAIL
-#define NS_CERT_TYPE_EMAIL_CA MBEDTLS_X509_NS_CERT_TYPE_EMAIL_CA
-#define NS_CERT_TYPE_OBJECT_SIGNING MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING
-#define NS_CERT_TYPE_OBJECT_SIGNING_CA MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING_CA
-#define NS_CERT_TYPE_RESERVED MBEDTLS_X509_NS_CERT_TYPE_RESERVED
-#define NS_CERT_TYPE_SSL_CA MBEDTLS_X509_NS_CERT_TYPE_SSL_CA
-#define NS_CERT_TYPE_SSL_CLIENT MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT
-#define NS_CERT_TYPE_SSL_SERVER MBEDTLS_X509_NS_CERT_TYPE_SSL_SERVER
-#define OID_ANSI_X9_62 MBEDTLS_OID_ANSI_X9_62
-#define OID_ANSI_X9_62_FIELD_TYPE MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE
-#define OID_ANSI_X9_62_PRIME_FIELD MBEDTLS_OID_ANSI_X9_62_PRIME_FIELD
-#define OID_ANSI_X9_62_SIG MBEDTLS_OID_ANSI_X9_62_SIG
-#define OID_ANSI_X9_62_SIG_SHA2 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2
-#define OID_ANY_EXTENDED_KEY_USAGE MBEDTLS_OID_ANY_EXTENDED_KEY_USAGE
-#define OID_AT MBEDTLS_OID_AT
-#define OID_AT_CN MBEDTLS_OID_AT_CN
-#define OID_AT_COUNTRY MBEDTLS_OID_AT_COUNTRY
-#define OID_AT_DN_QUALIFIER MBEDTLS_OID_AT_DN_QUALIFIER
-#define OID_AT_GENERATION_QUALIFIER MBEDTLS_OID_AT_GENERATION_QUALIFIER
-#define OID_AT_GIVEN_NAME MBEDTLS_OID_AT_GIVEN_NAME
-#define OID_AT_INITIALS MBEDTLS_OID_AT_INITIALS
-#define OID_AT_LOCALITY MBEDTLS_OID_AT_LOCALITY
-#define OID_AT_ORGANIZATION MBEDTLS_OID_AT_ORGANIZATION
-#define OID_AT_ORG_UNIT MBEDTLS_OID_AT_ORG_UNIT
-#define OID_AT_POSTAL_ADDRESS MBEDTLS_OID_AT_POSTAL_ADDRESS
-#define OID_AT_POSTAL_CODE MBEDTLS_OID_AT_POSTAL_CODE
-#define OID_AT_PSEUDONYM MBEDTLS_OID_AT_PSEUDONYM
-#define OID_AT_SERIAL_NUMBER MBEDTLS_OID_AT_SERIAL_NUMBER
-#define OID_AT_STATE MBEDTLS_OID_AT_STATE
-#define OID_AT_SUR_NAME MBEDTLS_OID_AT_SUR_NAME
-#define OID_AT_TITLE MBEDTLS_OID_AT_TITLE
-#define OID_AT_UNIQUE_IDENTIFIER MBEDTLS_OID_AT_UNIQUE_IDENTIFIER
-#define OID_AUTHORITY_KEY_IDENTIFIER MBEDTLS_OID_AUTHORITY_KEY_IDENTIFIER
-#define OID_BASIC_CONSTRAINTS MBEDTLS_OID_BASIC_CONSTRAINTS
-#define OID_CERTICOM MBEDTLS_OID_CERTICOM
-#define OID_CERTIFICATE_POLICIES MBEDTLS_OID_CERTIFICATE_POLICIES
-#define OID_CLIENT_AUTH MBEDTLS_OID_CLIENT_AUTH
-#define OID_CMP MBEDTLS_OID_CMP
-#define OID_CODE_SIGNING MBEDTLS_OID_CODE_SIGNING
-#define OID_COUNTRY_US MBEDTLS_OID_COUNTRY_US
-#define OID_CRL_DISTRIBUTION_POINTS MBEDTLS_OID_CRL_DISTRIBUTION_POINTS
-#define OID_CRL_NUMBER MBEDTLS_OID_CRL_NUMBER
-#define OID_DES_CBC MBEDTLS_OID_DES_CBC
-#define OID_DES_EDE3_CBC MBEDTLS_OID_DES_EDE3_CBC
-#define OID_DIGEST_ALG_MD2 MBEDTLS_OID_DIGEST_ALG_MD2
-#define OID_DIGEST_ALG_MD4 MBEDTLS_OID_DIGEST_ALG_MD4
-#define OID_DIGEST_ALG_MD5 MBEDTLS_OID_DIGEST_ALG_MD5
-#define OID_DIGEST_ALG_SHA1 MBEDTLS_OID_DIGEST_ALG_SHA1
-#define OID_DIGEST_ALG_SHA224 MBEDTLS_OID_DIGEST_ALG_SHA224
-#define OID_DIGEST_ALG_SHA256 MBEDTLS_OID_DIGEST_ALG_SHA256
-#define OID_DIGEST_ALG_SHA384 MBEDTLS_OID_DIGEST_ALG_SHA384
-#define OID_DIGEST_ALG_SHA512 MBEDTLS_OID_DIGEST_ALG_SHA512
-#define OID_DOMAIN_COMPONENT MBEDTLS_OID_DOMAIN_COMPONENT
-#define OID_ECDSA_SHA1 MBEDTLS_OID_ECDSA_SHA1
-#define OID_ECDSA_SHA224 MBEDTLS_OID_ECDSA_SHA224
-#define OID_ECDSA_SHA256 MBEDTLS_OID_ECDSA_SHA256
-#define OID_ECDSA_SHA384 MBEDTLS_OID_ECDSA_SHA384
-#define OID_ECDSA_SHA512 MBEDTLS_OID_ECDSA_SHA512
-#define OID_EC_ALG_ECDH MBEDTLS_OID_EC_ALG_ECDH
-#define OID_EC_ALG_UNRESTRICTED MBEDTLS_OID_EC_ALG_UNRESTRICTED
-#define OID_EC_BRAINPOOL_V1 MBEDTLS_OID_EC_BRAINPOOL_V1
-#define OID_EC_GRP_BP256R1 MBEDTLS_OID_EC_GRP_BP256R1
-#define OID_EC_GRP_BP384R1 MBEDTLS_OID_EC_GRP_BP384R1
-#define OID_EC_GRP_BP512R1 MBEDTLS_OID_EC_GRP_BP512R1
-#define OID_EC_GRP_SECP192K1 MBEDTLS_OID_EC_GRP_SECP192K1
-#define OID_EC_GRP_SECP192R1 MBEDTLS_OID_EC_GRP_SECP192R1
-#define OID_EC_GRP_SECP224K1 MBEDTLS_OID_EC_GRP_SECP224K1
-#define OID_EC_GRP_SECP224R1 MBEDTLS_OID_EC_GRP_SECP224R1
-#define OID_EC_GRP_SECP256K1 MBEDTLS_OID_EC_GRP_SECP256K1
-#define OID_EC_GRP_SECP256R1 MBEDTLS_OID_EC_GRP_SECP256R1
-#define OID_EC_GRP_SECP384R1 MBEDTLS_OID_EC_GRP_SECP384R1
-#define OID_EC_GRP_SECP521R1 MBEDTLS_OID_EC_GRP_SECP521R1
-#define OID_EMAIL_PROTECTION MBEDTLS_OID_EMAIL_PROTECTION
-#define OID_EXTENDED_KEY_USAGE MBEDTLS_OID_EXTENDED_KEY_USAGE
-#define OID_FRESHEST_CRL MBEDTLS_OID_FRESHEST_CRL
-#define OID_GOV MBEDTLS_OID_GOV
-#define OID_HMAC_SHA1 MBEDTLS_OID_HMAC_SHA1
-#define OID_ID_CE MBEDTLS_OID_ID_CE
-#define OID_INIHIBIT_ANYPOLICY MBEDTLS_OID_INIHIBIT_ANYPOLICY
-#define OID_ISO_CCITT_DS MBEDTLS_OID_ISO_CCITT_DS
-#define OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ISO_IDENTIFIED_ORG
-#define OID_ISO_ITU_COUNTRY MBEDTLS_OID_ISO_ITU_COUNTRY
-#define OID_ISO_ITU_US_ORG MBEDTLS_OID_ISO_ITU_US_ORG
-#define OID_ISO_MEMBER_BODIES MBEDTLS_OID_ISO_MEMBER_BODIES
-#define OID_ISSUER_ALT_NAME MBEDTLS_OID_ISSUER_ALT_NAME
-#define OID_KEY_USAGE MBEDTLS_OID_KEY_USAGE
-#define OID_KP MBEDTLS_OID_KP
-#define OID_MGF1 MBEDTLS_OID_MGF1
-#define OID_NAME_CONSTRAINTS MBEDTLS_OID_NAME_CONSTRAINTS
-#define OID_NETSCAPE MBEDTLS_OID_NETSCAPE
-#define OID_NS_BASE_URL MBEDTLS_OID_NS_BASE_URL
-#define OID_NS_CA_POLICY_URL MBEDTLS_OID_NS_CA_POLICY_URL
-#define OID_NS_CA_REVOCATION_URL MBEDTLS_OID_NS_CA_REVOCATION_URL
-#define OID_NS_CERT MBEDTLS_OID_NS_CERT
-#define OID_NS_CERT_SEQUENCE MBEDTLS_OID_NS_CERT_SEQUENCE
-#define OID_NS_CERT_TYPE MBEDTLS_OID_NS_CERT_TYPE
-#define OID_NS_COMMENT MBEDTLS_OID_NS_COMMENT
-#define OID_NS_DATA_TYPE MBEDTLS_OID_NS_DATA_TYPE
-#define OID_NS_RENEWAL_URL MBEDTLS_OID_NS_RENEWAL_URL
-#define OID_NS_REVOCATION_URL MBEDTLS_OID_NS_REVOCATION_URL
-#define OID_NS_SSL_SERVER_NAME MBEDTLS_OID_NS_SSL_SERVER_NAME
-#define OID_OCSP_SIGNING MBEDTLS_OID_OCSP_SIGNING
-#define OID_OIW_SECSIG MBEDTLS_OID_OIW_SECSIG
-#define OID_OIW_SECSIG_ALG MBEDTLS_OID_OIW_SECSIG_ALG
-#define OID_OIW_SECSIG_SHA1 MBEDTLS_OID_OIW_SECSIG_SHA1
-#define OID_ORGANIZATION MBEDTLS_OID_ORGANIZATION
-#define OID_ORG_ANSI_X9_62 MBEDTLS_OID_ORG_ANSI_X9_62
-#define OID_ORG_CERTICOM MBEDTLS_OID_ORG_CERTICOM
-#define OID_ORG_DOD MBEDTLS_OID_ORG_DOD
-#define OID_ORG_GOV MBEDTLS_OID_ORG_GOV
-#define OID_ORG_NETSCAPE MBEDTLS_OID_ORG_NETSCAPE
-#define OID_ORG_OIW MBEDTLS_OID_ORG_OIW
-#define OID_ORG_RSA_DATA_SECURITY MBEDTLS_OID_ORG_RSA_DATA_SECURITY
-#define OID_ORG_TELETRUST MBEDTLS_OID_ORG_TELETRUST
-#define OID_PKCS MBEDTLS_OID_PKCS
-#define OID_PKCS1 MBEDTLS_OID_PKCS1
-#define OID_PKCS12 MBEDTLS_OID_PKCS12
-#define OID_PKCS12_PBE MBEDTLS_OID_PKCS12_PBE
-#define OID_PKCS12_PBE_SHA1_DES2_EDE_CBC MBEDTLS_OID_PKCS12_PBE_SHA1_DES2_EDE_CBC
-#define OID_PKCS12_PBE_SHA1_DES3_EDE_CBC MBEDTLS_OID_PKCS12_PBE_SHA1_DES3_EDE_CBC
-#define OID_PKCS12_PBE_SHA1_RC2_128_CBC MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_128_CBC
-#define OID_PKCS12_PBE_SHA1_RC2_40_CBC MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_40_CBC
-#define OID_PKCS12_PBE_SHA1_RC4_128 MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_128
-#define OID_PKCS12_PBE_SHA1_RC4_40 MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_40
-#define OID_PKCS1_MD2 MBEDTLS_OID_PKCS1_MD2
-#define OID_PKCS1_MD4 MBEDTLS_OID_PKCS1_MD4
-#define OID_PKCS1_MD5 MBEDTLS_OID_PKCS1_MD5
-#define OID_PKCS1_RSA MBEDTLS_OID_PKCS1_RSA
-#define OID_PKCS1_SHA1 MBEDTLS_OID_PKCS1_SHA1
-#define OID_PKCS1_SHA224 MBEDTLS_OID_PKCS1_SHA224
-#define OID_PKCS1_SHA256 MBEDTLS_OID_PKCS1_SHA256
-#define OID_PKCS1_SHA384 MBEDTLS_OID_PKCS1_SHA384
-#define OID_PKCS1_SHA512 MBEDTLS_OID_PKCS1_SHA512
-#define OID_PKCS5 MBEDTLS_OID_PKCS5
-#define OID_PKCS5_PBES2 MBEDTLS_OID_PKCS5_PBES2
-#define OID_PKCS5_PBE_MD2_DES_CBC MBEDTLS_OID_PKCS5_PBE_MD2_DES_CBC
-#define OID_PKCS5_PBE_MD2_RC2_CBC MBEDTLS_OID_PKCS5_PBE_MD2_RC2_CBC
-#define OID_PKCS5_PBE_MD5_DES_CBC MBEDTLS_OID_PKCS5_PBE_MD5_DES_CBC
-#define OID_PKCS5_PBE_MD5_RC2_CBC MBEDTLS_OID_PKCS5_PBE_MD5_RC2_CBC
-#define OID_PKCS5_PBE_SHA1_DES_CBC MBEDTLS_OID_PKCS5_PBE_SHA1_DES_CBC
-#define OID_PKCS5_PBE_SHA1_RC2_CBC MBEDTLS_OID_PKCS5_PBE_SHA1_RC2_CBC
-#define OID_PKCS5_PBKDF2 MBEDTLS_OID_PKCS5_PBKDF2
-#define OID_PKCS5_PBMAC1 MBEDTLS_OID_PKCS5_PBMAC1
-#define OID_PKCS9 MBEDTLS_OID_PKCS9
-#define OID_PKCS9_CSR_EXT_REQ MBEDTLS_OID_PKCS9_CSR_EXT_REQ
-#define OID_PKCS9_EMAIL MBEDTLS_OID_PKCS9_EMAIL
-#define OID_PKIX MBEDTLS_OID_PKIX
-#define OID_POLICY_CONSTRAINTS MBEDTLS_OID_POLICY_CONSTRAINTS
-#define OID_POLICY_MAPPINGS MBEDTLS_OID_POLICY_MAPPINGS
-#define OID_PRIVATE_KEY_USAGE_PERIOD MBEDTLS_OID_PRIVATE_KEY_USAGE_PERIOD
-#define OID_RSASSA_PSS MBEDTLS_OID_RSASSA_PSS
-#define OID_RSA_COMPANY MBEDTLS_OID_RSA_COMPANY
-#define OID_RSA_SHA_OBS MBEDTLS_OID_RSA_SHA_OBS
-#define OID_SERVER_AUTH MBEDTLS_OID_SERVER_AUTH
-#define OID_SIZE MBEDTLS_OID_SIZE
-#define OID_SUBJECT_ALT_NAME MBEDTLS_OID_SUBJECT_ALT_NAME
-#define OID_SUBJECT_DIRECTORY_ATTRS MBEDTLS_OID_SUBJECT_DIRECTORY_ATTRS
-#define OID_SUBJECT_KEY_IDENTIFIER MBEDTLS_OID_SUBJECT_KEY_IDENTIFIER
-#define OID_TELETRUST MBEDTLS_OID_TELETRUST
-#define OID_TIME_STAMPING MBEDTLS_OID_TIME_STAMPING
-#define PADLOCK_ACE MBEDTLS_PADLOCK_ACE
-#define PADLOCK_ALIGN16 MBEDTLS_PADLOCK_ALIGN16
-#define PADLOCK_PHE MBEDTLS_PADLOCK_PHE
-#define PADLOCK_PMM MBEDTLS_PADLOCK_PMM
-#define PADLOCK_RNG MBEDTLS_PADLOCK_RNG
-#define PKCS12_DERIVE_IV MBEDTLS_PKCS12_DERIVE_IV
-#define PKCS12_DERIVE_KEY MBEDTLS_PKCS12_DERIVE_KEY
-#define PKCS12_DERIVE_MAC_KEY MBEDTLS_PKCS12_DERIVE_MAC_KEY
-#define PKCS12_PBE_DECRYPT MBEDTLS_PKCS12_PBE_DECRYPT
-#define PKCS12_PBE_ENCRYPT MBEDTLS_PKCS12_PBE_ENCRYPT
-#define PKCS5_DECRYPT MBEDTLS_PKCS5_DECRYPT
-#define PKCS5_ENCRYPT MBEDTLS_PKCS5_ENCRYPT
-#define POLARSSL_AESNI_AES MBEDTLS_AESNI_AES
-#define POLARSSL_AESNI_CLMUL MBEDTLS_AESNI_CLMUL
-#define POLARSSL_AESNI_H MBEDTLS_AESNI_H
-#define POLARSSL_AES_H MBEDTLS_AES_H
-#define POLARSSL_ARC4_H MBEDTLS_ARC4_H
-#define POLARSSL_ASN1_H MBEDTLS_ASN1_H
-#define POLARSSL_ASN1_WRITE_H MBEDTLS_ASN1_WRITE_H
-#define POLARSSL_BASE64_H MBEDTLS_BASE64_H
-#define POLARSSL_BIGNUM_H MBEDTLS_BIGNUM_H
-#define POLARSSL_BLOWFISH_H MBEDTLS_BLOWFISH_H
-#define POLARSSL_BN_MUL_H MBEDTLS_BN_MUL_H
-#define POLARSSL_CAMELLIA_H MBEDTLS_CAMELLIA_H
-#define POLARSSL_CCM_H MBEDTLS_CCM_H
-#define POLARSSL_CERTS_H MBEDTLS_CERTS_H
-#define POLARSSL_CHECK_CONFIG_H MBEDTLS_CHECK_CONFIG_H
-#define POLARSSL_CIPHERSUITE_NODTLS MBEDTLS_CIPHERSUITE_NODTLS
-#define POLARSSL_CIPHERSUITE_SHORT_TAG MBEDTLS_CIPHERSUITE_SHORT_TAG
-#define POLARSSL_CIPHERSUITE_WEAK MBEDTLS_CIPHERSUITE_WEAK
-#define POLARSSL_CIPHER_AES_128_CBC MBEDTLS_CIPHER_AES_128_CBC
-#define POLARSSL_CIPHER_AES_128_CCM MBEDTLS_CIPHER_AES_128_CCM
-#define POLARSSL_CIPHER_AES_128_CFB128 MBEDTLS_CIPHER_AES_128_CFB128
-#define POLARSSL_CIPHER_AES_128_CTR MBEDTLS_CIPHER_AES_128_CTR
-#define POLARSSL_CIPHER_AES_128_ECB MBEDTLS_CIPHER_AES_128_ECB
-#define POLARSSL_CIPHER_AES_128_GCM MBEDTLS_CIPHER_AES_128_GCM
-#define POLARSSL_CIPHER_AES_192_CBC MBEDTLS_CIPHER_AES_192_CBC
-#define POLARSSL_CIPHER_AES_192_CCM MBEDTLS_CIPHER_AES_192_CCM
-#define POLARSSL_CIPHER_AES_192_CFB128 MBEDTLS_CIPHER_AES_192_CFB128
-#define POLARSSL_CIPHER_AES_192_CTR MBEDTLS_CIPHER_AES_192_CTR
-#define POLARSSL_CIPHER_AES_192_ECB MBEDTLS_CIPHER_AES_192_ECB
-#define POLARSSL_CIPHER_AES_192_GCM MBEDTLS_CIPHER_AES_192_GCM
-#define POLARSSL_CIPHER_AES_256_CBC MBEDTLS_CIPHER_AES_256_CBC
-#define POLARSSL_CIPHER_AES_256_CCM MBEDTLS_CIPHER_AES_256_CCM
-#define POLARSSL_CIPHER_AES_256_CFB128 MBEDTLS_CIPHER_AES_256_CFB128
-#define POLARSSL_CIPHER_AES_256_CTR MBEDTLS_CIPHER_AES_256_CTR
-#define POLARSSL_CIPHER_AES_256_ECB MBEDTLS_CIPHER_AES_256_ECB
-#define POLARSSL_CIPHER_AES_256_GCM MBEDTLS_CIPHER_AES_256_GCM
-#define POLARSSL_CIPHER_ARC4_128 MBEDTLS_CIPHER_ARC4_128
-#define POLARSSL_CIPHER_BLOWFISH_CBC MBEDTLS_CIPHER_BLOWFISH_CBC
-#define POLARSSL_CIPHER_BLOWFISH_CFB64 MBEDTLS_CIPHER_BLOWFISH_CFB64
-#define POLARSSL_CIPHER_BLOWFISH_CTR MBEDTLS_CIPHER_BLOWFISH_CTR
-#define POLARSSL_CIPHER_BLOWFISH_ECB MBEDTLS_CIPHER_BLOWFISH_ECB
-#define POLARSSL_CIPHER_CAMELLIA_128_CBC MBEDTLS_CIPHER_CAMELLIA_128_CBC
-#define POLARSSL_CIPHER_CAMELLIA_128_CCM MBEDTLS_CIPHER_CAMELLIA_128_CCM
-#define POLARSSL_CIPHER_CAMELLIA_128_CFB128 MBEDTLS_CIPHER_CAMELLIA_128_CFB128
-#define POLARSSL_CIPHER_CAMELLIA_128_CTR MBEDTLS_CIPHER_CAMELLIA_128_CTR
-#define POLARSSL_CIPHER_CAMELLIA_128_ECB MBEDTLS_CIPHER_CAMELLIA_128_ECB
-#define POLARSSL_CIPHER_CAMELLIA_128_GCM MBEDTLS_CIPHER_CAMELLIA_128_GCM
-#define POLARSSL_CIPHER_CAMELLIA_192_CBC MBEDTLS_CIPHER_CAMELLIA_192_CBC
-#define POLARSSL_CIPHER_CAMELLIA_192_CCM MBEDTLS_CIPHER_CAMELLIA_192_CCM
-#define POLARSSL_CIPHER_CAMELLIA_192_CFB128 MBEDTLS_CIPHER_CAMELLIA_192_CFB128
-#define POLARSSL_CIPHER_CAMELLIA_192_CTR MBEDTLS_CIPHER_CAMELLIA_192_CTR
-#define POLARSSL_CIPHER_CAMELLIA_192_ECB MBEDTLS_CIPHER_CAMELLIA_192_ECB
-#define POLARSSL_CIPHER_CAMELLIA_192_GCM MBEDTLS_CIPHER_CAMELLIA_192_GCM
-#define POLARSSL_CIPHER_CAMELLIA_256_CBC MBEDTLS_CIPHER_CAMELLIA_256_CBC
-#define POLARSSL_CIPHER_CAMELLIA_256_CCM MBEDTLS_CIPHER_CAMELLIA_256_CCM
-#define POLARSSL_CIPHER_CAMELLIA_256_CFB128 MBEDTLS_CIPHER_CAMELLIA_256_CFB128
-#define POLARSSL_CIPHER_CAMELLIA_256_CTR MBEDTLS_CIPHER_CAMELLIA_256_CTR
-#define POLARSSL_CIPHER_CAMELLIA_256_ECB MBEDTLS_CIPHER_CAMELLIA_256_ECB
-#define POLARSSL_CIPHER_CAMELLIA_256_GCM MBEDTLS_CIPHER_CAMELLIA_256_GCM
-#define POLARSSL_CIPHER_DES_CBC MBEDTLS_CIPHER_DES_CBC
-#define POLARSSL_CIPHER_DES_ECB MBEDTLS_CIPHER_DES_ECB
-#define POLARSSL_CIPHER_DES_EDE3_CBC MBEDTLS_CIPHER_DES_EDE3_CBC
-#define POLARSSL_CIPHER_DES_EDE3_ECB MBEDTLS_CIPHER_DES_EDE3_ECB
-#define POLARSSL_CIPHER_DES_EDE_CBC MBEDTLS_CIPHER_DES_EDE_CBC
-#define POLARSSL_CIPHER_DES_EDE_ECB MBEDTLS_CIPHER_DES_EDE_ECB
-#define POLARSSL_CIPHER_H MBEDTLS_CIPHER_H
-#define POLARSSL_CIPHER_ID_3DES MBEDTLS_CIPHER_ID_3DES
-#define POLARSSL_CIPHER_ID_AES MBEDTLS_CIPHER_ID_AES
-#define POLARSSL_CIPHER_ID_ARC4 MBEDTLS_CIPHER_ID_ARC4
-#define POLARSSL_CIPHER_ID_BLOWFISH MBEDTLS_CIPHER_ID_BLOWFISH
-#define POLARSSL_CIPHER_ID_CAMELLIA MBEDTLS_CIPHER_ID_CAMELLIA
-#define POLARSSL_CIPHER_ID_DES MBEDTLS_CIPHER_ID_DES
-#define POLARSSL_CIPHER_ID_NONE MBEDTLS_CIPHER_ID_NONE
-#define POLARSSL_CIPHER_ID_NULL MBEDTLS_CIPHER_ID_NULL
-#define POLARSSL_CIPHER_MODE_AEAD MBEDTLS_CIPHER_MODE_AEAD
-#define POLARSSL_CIPHER_MODE_STREAM MBEDTLS_CIPHER_MODE_STREAM
-#define POLARSSL_CIPHER_MODE_WITH_PADDING MBEDTLS_CIPHER_MODE_WITH_PADDING
-#define POLARSSL_CIPHER_NONE MBEDTLS_CIPHER_NONE
-#define POLARSSL_CIPHER_NULL MBEDTLS_CIPHER_NULL
-#define POLARSSL_CIPHER_VARIABLE_IV_LEN MBEDTLS_CIPHER_VARIABLE_IV_LEN
-#define POLARSSL_CIPHER_VARIABLE_KEY_LEN MBEDTLS_CIPHER_VARIABLE_KEY_LEN
-#define POLARSSL_CIPHER_WRAP_H MBEDTLS_CIPHER_WRAP_H
-#define POLARSSL_CONFIG_H MBEDTLS_CONFIG_H
-#define POLARSSL_CTR_DRBG_H MBEDTLS_CTR_DRBG_H
-#define POLARSSL_DEBUG_H MBEDTLS_DEBUG_H
-#define POLARSSL_DECRYPT MBEDTLS_DECRYPT
-#define POLARSSL_DES_H MBEDTLS_DES_H
-#define POLARSSL_DHM_H MBEDTLS_DHM_H
-#define POLARSSL_DHM_RFC3526_MODP_2048_G MBEDTLS_DHM_RFC3526_MODP_2048_G
-#define POLARSSL_DHM_RFC3526_MODP_2048_P MBEDTLS_DHM_RFC3526_MODP_2048_P
-#define POLARSSL_DHM_RFC3526_MODP_3072_G MBEDTLS_DHM_RFC3526_MODP_3072_G
-#define POLARSSL_DHM_RFC3526_MODP_3072_P MBEDTLS_DHM_RFC3526_MODP_3072_P
-#define POLARSSL_DHM_RFC5114_MODP_2048_G MBEDTLS_DHM_RFC5114_MODP_2048_G
-#define POLARSSL_DHM_RFC5114_MODP_2048_P MBEDTLS_DHM_RFC5114_MODP_2048_P
-#define POLARSSL_ECDH_H MBEDTLS_ECDH_H
-#define POLARSSL_ECDH_OURS MBEDTLS_ECDH_OURS
-#define POLARSSL_ECDH_THEIRS MBEDTLS_ECDH_THEIRS
-#define POLARSSL_ECDSA_H MBEDTLS_ECDSA_H
-#define POLARSSL_ECP_DP_BP256R1 MBEDTLS_ECP_DP_BP256R1
-#define POLARSSL_ECP_DP_BP384R1 MBEDTLS_ECP_DP_BP384R1
-#define POLARSSL_ECP_DP_BP512R1 MBEDTLS_ECP_DP_BP512R1
-#define POLARSSL_ECP_DP_M255 MBEDTLS_ECP_DP_CURVE25519
-#define POLARSSL_ECP_DP_MAX MBEDTLS_ECP_DP_MAX
-#define POLARSSL_ECP_DP_NONE MBEDTLS_ECP_DP_NONE
-#define POLARSSL_ECP_DP_SECP192K1 MBEDTLS_ECP_DP_SECP192K1
-#define POLARSSL_ECP_DP_SECP192R1 MBEDTLS_ECP_DP_SECP192R1
-#define POLARSSL_ECP_DP_SECP224K1 MBEDTLS_ECP_DP_SECP224K1
-#define POLARSSL_ECP_DP_SECP224R1 MBEDTLS_ECP_DP_SECP224R1
-#define POLARSSL_ECP_DP_SECP256K1 MBEDTLS_ECP_DP_SECP256K1
-#define POLARSSL_ECP_DP_SECP256R1 MBEDTLS_ECP_DP_SECP256R1
-#define POLARSSL_ECP_DP_SECP384R1 MBEDTLS_ECP_DP_SECP384R1
-#define POLARSSL_ECP_DP_SECP521R1 MBEDTLS_ECP_DP_SECP521R1
-#define POLARSSL_ECP_H MBEDTLS_ECP_H
-#define POLARSSL_ECP_MAX_BYTES MBEDTLS_ECP_MAX_BYTES
-#define POLARSSL_ECP_MAX_PT_LEN MBEDTLS_ECP_MAX_PT_LEN
-#define POLARSSL_ECP_PF_COMPRESSED MBEDTLS_ECP_PF_COMPRESSED
-#define POLARSSL_ECP_PF_UNCOMPRESSED MBEDTLS_ECP_PF_UNCOMPRESSED
-#define POLARSSL_ECP_TLS_NAMED_CURVE MBEDTLS_ECP_TLS_NAMED_CURVE
-#define POLARSSL_ENCRYPT MBEDTLS_ENCRYPT
-#define POLARSSL_ENTROPY_H MBEDTLS_ENTROPY_H
-#define POLARSSL_ENTROPY_POLL_H MBEDTLS_ENTROPY_POLL_H
-#define POLARSSL_ENTROPY_SHA256_ACCUMULATOR MBEDTLS_ENTROPY_SHA256_ACCUMULATOR
-#define POLARSSL_ENTROPY_SHA512_ACCUMULATOR MBEDTLS_ENTROPY_SHA512_ACCUMULATOR
-#define POLARSSL_ERROR_H MBEDTLS_ERROR_H
-#define POLARSSL_ERR_AES_INVALID_INPUT_LENGTH MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
-#define POLARSSL_ERR_AES_INVALID_KEY_LENGTH MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
-#define POLARSSL_ERR_ASN1_BUF_TOO_SMALL MBEDTLS_ERR_ASN1_BUF_TOO_SMALL
-#define POLARSSL_ERR_ASN1_INVALID_DATA MBEDTLS_ERR_ASN1_INVALID_DATA
-#define POLARSSL_ERR_ASN1_INVALID_LENGTH MBEDTLS_ERR_ASN1_INVALID_LENGTH
-#define POLARSSL_ERR_ASN1_LENGTH_MISMATCH MBEDTLS_ERR_ASN1_LENGTH_MISMATCH
-#define POLARSSL_ERR_ASN1_MALLOC_FAILED MBEDTLS_ERR_ASN1_ALLOC_FAILED
-#define POLARSSL_ERR_ASN1_OUT_OF_DATA MBEDTLS_ERR_ASN1_OUT_OF_DATA
-#define POLARSSL_ERR_ASN1_UNEXPECTED_TAG MBEDTLS_ERR_ASN1_UNEXPECTED_TAG
-#define POLARSSL_ERR_BASE64_BUFFER_TOO_SMALL MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL
-#define POLARSSL_ERR_BASE64_INVALID_CHARACTER MBEDTLS_ERR_BASE64_INVALID_CHARACTER
-#define POLARSSL_ERR_BLOWFISH_INVALID_INPUT_LENGTH MBEDTLS_ERR_BLOWFISH_INVALID_INPUT_LENGTH
-#define POLARSSL_ERR_BLOWFISH_INVALID_KEY_LENGTH MBEDTLS_ERR_BLOWFISH_INVALID_KEY_LENGTH
-#define POLARSSL_ERR_CAMELLIA_INVALID_INPUT_LENGTH MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH
-#define POLARSSL_ERR_CAMELLIA_INVALID_KEY_LENGTH MBEDTLS_ERR_CAMELLIA_INVALID_KEY_LENGTH
-#define POLARSSL_ERR_CCM_AUTH_FAILED MBEDTLS_ERR_CCM_AUTH_FAILED
-#define POLARSSL_ERR_CCM_BAD_INPUT MBEDTLS_ERR_CCM_BAD_INPUT
-#define POLARSSL_ERR_CIPHER_ALLOC_FAILED MBEDTLS_ERR_CIPHER_ALLOC_FAILED
-#define POLARSSL_ERR_CIPHER_AUTH_FAILED MBEDTLS_ERR_CIPHER_AUTH_FAILED
-#define POLARSSL_ERR_CIPHER_BAD_INPUT_DATA MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA
-#define POLARSSL_ERR_CIPHER_FEATURE_UNAVAILABLE MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_CIPHER_FULL_BLOCK_EXPECTED MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED
-#define POLARSSL_ERR_CIPHER_INVALID_PADDING MBEDTLS_ERR_CIPHER_INVALID_PADDING
-#define POLARSSL_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED
-#define POLARSSL_ERR_CTR_DRBG_FILE_IO_ERROR MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR
-#define POLARSSL_ERR_CTR_DRBG_INPUT_TOO_BIG MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG
-#define POLARSSL_ERR_CTR_DRBG_REQUEST_TOO_BIG MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG
-#define POLARSSL_ERR_DES_INVALID_INPUT_LENGTH MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
-#define POLARSSL_ERR_DHM_BAD_INPUT_DATA MBEDTLS_ERR_DHM_BAD_INPUT_DATA
-#define POLARSSL_ERR_DHM_CALC_SECRET_FAILED MBEDTLS_ERR_DHM_CALC_SECRET_FAILED
-#define POLARSSL_ERR_DHM_FILE_IO_ERROR MBEDTLS_ERR_DHM_FILE_IO_ERROR
-#define POLARSSL_ERR_DHM_INVALID_FORMAT MBEDTLS_ERR_DHM_INVALID_FORMAT
-#define POLARSSL_ERR_DHM_MAKE_PARAMS_FAILED MBEDTLS_ERR_DHM_MAKE_PARAMS_FAILED
-#define POLARSSL_ERR_DHM_MAKE_PUBLIC_FAILED MBEDTLS_ERR_DHM_MAKE_PUBLIC_FAILED
-#define POLARSSL_ERR_DHM_MALLOC_FAILED MBEDTLS_ERR_DHM_ALLOC_FAILED
-#define POLARSSL_ERR_DHM_READ_PARAMS_FAILED MBEDTLS_ERR_DHM_READ_PARAMS_FAILED
-#define POLARSSL_ERR_DHM_READ_PUBLIC_FAILED MBEDTLS_ERR_DHM_READ_PUBLIC_FAILED
-#define POLARSSL_ERR_ECP_BAD_INPUT_DATA MBEDTLS_ERR_ECP_BAD_INPUT_DATA
-#define POLARSSL_ERR_ECP_BUFFER_TOO_SMALL MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL
-#define POLARSSL_ERR_ECP_FEATURE_UNAVAILABLE MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_ECP_INVALID_KEY MBEDTLS_ERR_ECP_INVALID_KEY
-#define POLARSSL_ERR_ECP_MALLOC_FAILED MBEDTLS_ERR_ECP_ALLOC_FAILED
-#define POLARSSL_ERR_ECP_RANDOM_FAILED MBEDTLS_ERR_ECP_RANDOM_FAILED
-#define POLARSSL_ERR_ECP_SIG_LEN_MISMATCH MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH
-#define POLARSSL_ERR_ECP_VERIFY_FAILED MBEDTLS_ERR_ECP_VERIFY_FAILED
-#define POLARSSL_ERR_ENTROPY_FILE_IO_ERROR MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR
-#define POLARSSL_ERR_ENTROPY_MAX_SOURCES MBEDTLS_ERR_ENTROPY_MAX_SOURCES
-#define POLARSSL_ERR_ENTROPY_NO_SOURCES_DEFINED MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED
-#define POLARSSL_ERR_ENTROPY_SOURCE_FAILED MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
-#define POLARSSL_ERR_GCM_AUTH_FAILED MBEDTLS_ERR_GCM_AUTH_FAILED
-#define POLARSSL_ERR_GCM_BAD_INPUT MBEDTLS_ERR_GCM_BAD_INPUT
-#define POLARSSL_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED
-#define POLARSSL_ERR_HMAC_DRBG_FILE_IO_ERROR MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR
-#define POLARSSL_ERR_HMAC_DRBG_INPUT_TOO_BIG MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG
-#define POLARSSL_ERR_HMAC_DRBG_REQUEST_TOO_BIG MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG
-#define POLARSSL_ERR_MD_ALLOC_FAILED MBEDTLS_ERR_MD_ALLOC_FAILED
-#define POLARSSL_ERR_MD_BAD_INPUT_DATA MBEDTLS_ERR_MD_BAD_INPUT_DATA
-#define POLARSSL_ERR_MD_FEATURE_UNAVAILABLE MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_MD_FILE_IO_ERROR MBEDTLS_ERR_MD_FILE_IO_ERROR
-#define POLARSSL_ERR_MPI_BAD_INPUT_DATA MBEDTLS_ERR_MPI_BAD_INPUT_DATA
-#define POLARSSL_ERR_MPI_BUFFER_TOO_SMALL MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL
-#define POLARSSL_ERR_MPI_DIVISION_BY_ZERO MBEDTLS_ERR_MPI_DIVISION_BY_ZERO
-#define POLARSSL_ERR_MPI_FILE_IO_ERROR MBEDTLS_ERR_MPI_FILE_IO_ERROR
-#define POLARSSL_ERR_MPI_INVALID_CHARACTER MBEDTLS_ERR_MPI_INVALID_CHARACTER
-#define POLARSSL_ERR_MPI_MALLOC_FAILED MBEDTLS_ERR_MPI_ALLOC_FAILED
-#define POLARSSL_ERR_MPI_NEGATIVE_VALUE MBEDTLS_ERR_MPI_NEGATIVE_VALUE
-#define POLARSSL_ERR_MPI_NOT_ACCEPTABLE MBEDTLS_ERR_MPI_NOT_ACCEPTABLE
-#define POLARSSL_ERR_NET_ACCEPT_FAILED MBEDTLS_ERR_NET_ACCEPT_FAILED
-#define POLARSSL_ERR_NET_BIND_FAILED MBEDTLS_ERR_NET_BIND_FAILED
-#define POLARSSL_ERR_NET_CONNECT_FAILED MBEDTLS_ERR_NET_CONNECT_FAILED
-#define POLARSSL_ERR_NET_CONN_RESET MBEDTLS_ERR_NET_CONN_RESET
-#define POLARSSL_ERR_NET_LISTEN_FAILED MBEDTLS_ERR_NET_LISTEN_FAILED
-#define POLARSSL_ERR_NET_RECV_FAILED MBEDTLS_ERR_NET_RECV_FAILED
-#define POLARSSL_ERR_NET_SEND_FAILED MBEDTLS_ERR_NET_SEND_FAILED
-#define POLARSSL_ERR_NET_SOCKET_FAILED MBEDTLS_ERR_NET_SOCKET_FAILED
-#define POLARSSL_ERR_NET_TIMEOUT MBEDTLS_ERR_SSL_TIMEOUT
-#define POLARSSL_ERR_NET_UNKNOWN_HOST MBEDTLS_ERR_NET_UNKNOWN_HOST
-#define POLARSSL_ERR_NET_WANT_READ MBEDTLS_ERR_SSL_WANT_READ
-#define POLARSSL_ERR_NET_WANT_WRITE MBEDTLS_ERR_SSL_WANT_WRITE
-#define POLARSSL_ERR_OID_BUF_TOO_SMALL MBEDTLS_ERR_OID_BUF_TOO_SMALL
-#define POLARSSL_ERR_OID_NOT_FOUND MBEDTLS_ERR_OID_NOT_FOUND
-#define POLARSSL_ERR_PADLOCK_DATA_MISALIGNED MBEDTLS_ERR_PADLOCK_DATA_MISALIGNED
-#define POLARSSL_ERR_PEM_BAD_INPUT_DATA MBEDTLS_ERR_PEM_BAD_INPUT_DATA
-#define POLARSSL_ERR_PEM_FEATURE_UNAVAILABLE MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_PEM_INVALID_DATA MBEDTLS_ERR_PEM_INVALID_DATA
-#define POLARSSL_ERR_PEM_INVALID_ENC_IV MBEDTLS_ERR_PEM_INVALID_ENC_IV
-#define POLARSSL_ERR_PEM_MALLOC_FAILED MBEDTLS_ERR_PEM_ALLOC_FAILED
-#define POLARSSL_ERR_PEM_NO_HEADER_FOOTER_PRESENT MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT
-#define POLARSSL_ERR_PEM_PASSWORD_MISMATCH MBEDTLS_ERR_PEM_PASSWORD_MISMATCH
-#define POLARSSL_ERR_PEM_PASSWORD_REQUIRED MBEDTLS_ERR_PEM_PASSWORD_REQUIRED
-#define POLARSSL_ERR_PEM_UNKNOWN_ENC_ALG MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG
-#define POLARSSL_ERR_PKCS12_BAD_INPUT_DATA MBEDTLS_ERR_PKCS12_BAD_INPUT_DATA
-#define POLARSSL_ERR_PKCS12_FEATURE_UNAVAILABLE MBEDTLS_ERR_PKCS12_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_PKCS12_PASSWORD_MISMATCH MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH
-#define POLARSSL_ERR_PKCS12_PBE_INVALID_FORMAT MBEDTLS_ERR_PKCS12_PBE_INVALID_FORMAT
-#define POLARSSL_ERR_PKCS5_BAD_INPUT_DATA MBEDTLS_ERR_PKCS5_BAD_INPUT_DATA
-#define POLARSSL_ERR_PKCS5_FEATURE_UNAVAILABLE MBEDTLS_ERR_PKCS5_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_PKCS5_INVALID_FORMAT MBEDTLS_ERR_PKCS5_INVALID_FORMAT
-#define POLARSSL_ERR_PKCS5_PASSWORD_MISMATCH MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH
-#define POLARSSL_ERR_PK_BAD_INPUT_DATA MBEDTLS_ERR_PK_BAD_INPUT_DATA
-#define POLARSSL_ERR_PK_FEATURE_UNAVAILABLE MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_PK_FILE_IO_ERROR MBEDTLS_ERR_PK_FILE_IO_ERROR
-#define POLARSSL_ERR_PK_INVALID_ALG MBEDTLS_ERR_PK_INVALID_ALG
-#define POLARSSL_ERR_PK_INVALID_PUBKEY MBEDTLS_ERR_PK_INVALID_PUBKEY
-#define POLARSSL_ERR_PK_KEY_INVALID_FORMAT MBEDTLS_ERR_PK_KEY_INVALID_FORMAT
-#define POLARSSL_ERR_PK_KEY_INVALID_VERSION MBEDTLS_ERR_PK_KEY_INVALID_VERSION
-#define POLARSSL_ERR_PK_MALLOC_FAILED MBEDTLS_ERR_PK_ALLOC_FAILED
-#define POLARSSL_ERR_PK_PASSWORD_MISMATCH MBEDTLS_ERR_PK_PASSWORD_MISMATCH
-#define POLARSSL_ERR_PK_PASSWORD_REQUIRED MBEDTLS_ERR_PK_PASSWORD_REQUIRED
-#define POLARSSL_ERR_PK_SIG_LEN_MISMATCH MBEDTLS_ERR_PK_SIG_LEN_MISMATCH
-#define POLARSSL_ERR_PK_TYPE_MISMATCH MBEDTLS_ERR_PK_TYPE_MISMATCH
-#define POLARSSL_ERR_PK_UNKNOWN_NAMED_CURVE MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE
-#define POLARSSL_ERR_PK_UNKNOWN_PK_ALG MBEDTLS_ERR_PK_UNKNOWN_PK_ALG
-#define POLARSSL_ERR_RSA_BAD_INPUT_DATA MBEDTLS_ERR_RSA_BAD_INPUT_DATA
-#define POLARSSL_ERR_RSA_INVALID_PADDING MBEDTLS_ERR_RSA_INVALID_PADDING
-#define POLARSSL_ERR_RSA_KEY_CHECK_FAILED MBEDTLS_ERR_RSA_KEY_CHECK_FAILED
-#define POLARSSL_ERR_RSA_KEY_GEN_FAILED MBEDTLS_ERR_RSA_KEY_GEN_FAILED
-#define POLARSSL_ERR_RSA_OUTPUT_TOO_LARGE MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE
-#define POLARSSL_ERR_RSA_PRIVATE_FAILED MBEDTLS_ERR_RSA_PRIVATE_FAILED
-#define POLARSSL_ERR_RSA_PUBLIC_FAILED MBEDTLS_ERR_RSA_PUBLIC_FAILED
-#define POLARSSL_ERR_RSA_RNG_FAILED MBEDTLS_ERR_RSA_RNG_FAILED
-#define POLARSSL_ERR_RSA_VERIFY_FAILED MBEDTLS_ERR_RSA_VERIFY_FAILED
-#define POLARSSL_ERR_SSL_BAD_HS_CERTIFICATE MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE
-#define POLARSSL_ERR_SSL_BAD_HS_CERTIFICATE_REQUEST MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_REQUEST
-#define POLARSSL_ERR_SSL_BAD_HS_CERTIFICATE_VERIFY MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_VERIFY
-#define POLARSSL_ERR_SSL_BAD_HS_CHANGE_CIPHER_SPEC MBEDTLS_ERR_SSL_BAD_HS_CHANGE_CIPHER_SPEC
-#define POLARSSL_ERR_SSL_BAD_HS_CLIENT_HELLO MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO
-#define POLARSSL_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE
-#define POLARSSL_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_CS MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_CS
-#define POLARSSL_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_RP MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_RP
-#define POLARSSL_ERR_SSL_BAD_HS_FINISHED MBEDTLS_ERR_SSL_BAD_HS_FINISHED
-#define POLARSSL_ERR_SSL_BAD_HS_NEW_SESSION_TICKET MBEDTLS_ERR_SSL_BAD_HS_NEW_SESSION_TICKET
-#define POLARSSL_ERR_SSL_BAD_HS_PROTOCOL_VERSION MBEDTLS_ERR_SSL_BAD_HS_PROTOCOL_VERSION
-#define POLARSSL_ERR_SSL_BAD_HS_SERVER_HELLO MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO
-#define POLARSSL_ERR_SSL_BAD_HS_SERVER_HELLO_DONE MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO_DONE
-#define POLARSSL_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE MBEDTLS_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE
-#define POLARSSL_ERR_SSL_BAD_INPUT_DATA MBEDTLS_ERR_SSL_BAD_INPUT_DATA
-#define POLARSSL_ERR_SSL_BUFFER_TOO_SMALL MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL
-#define POLARSSL_ERR_SSL_CA_CHAIN_REQUIRED MBEDTLS_ERR_SSL_CA_CHAIN_REQUIRED
-#define POLARSSL_ERR_SSL_CERTIFICATE_REQUIRED MBEDTLS_ERR_SSL_CERTIFICATE_REQUIRED
-#define POLARSSL_ERR_SSL_CERTIFICATE_TOO_LARGE MBEDTLS_ERR_SSL_CERTIFICATE_TOO_LARGE
-#define POLARSSL_ERR_SSL_COMPRESSION_FAILED MBEDTLS_ERR_SSL_COMPRESSION_FAILED
-#define POLARSSL_ERR_SSL_CONN_EOF MBEDTLS_ERR_SSL_CONN_EOF
-#define POLARSSL_ERR_SSL_COUNTER_WRAPPING MBEDTLS_ERR_SSL_COUNTER_WRAPPING
-#define POLARSSL_ERR_SSL_FATAL_ALERT_MESSAGE MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE
-#define POLARSSL_ERR_SSL_FEATURE_UNAVAILABLE MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_SSL_HELLO_VERIFY_REQUIRED MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED
-#define POLARSSL_ERR_SSL_HW_ACCEL_FAILED MBEDTLS_ERR_SSL_HW_ACCEL_FAILED
-#define POLARSSL_ERR_SSL_HW_ACCEL_FALLTHROUGH MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH
-#define POLARSSL_ERR_SSL_INTERNAL_ERROR MBEDTLS_ERR_SSL_INTERNAL_ERROR
-#define POLARSSL_ERR_SSL_INVALID_MAC MBEDTLS_ERR_SSL_INVALID_MAC
-#define POLARSSL_ERR_SSL_INVALID_RECORD MBEDTLS_ERR_SSL_INVALID_RECORD
-#define POLARSSL_ERR_SSL_MALLOC_FAILED MBEDTLS_ERR_SSL_ALLOC_FAILED
-#define POLARSSL_ERR_SSL_NO_CIPHER_CHOSEN MBEDTLS_ERR_SSL_NO_CIPHER_CHOSEN
-#define POLARSSL_ERR_SSL_NO_CLIENT_CERTIFICATE MBEDTLS_ERR_SSL_NO_CLIENT_CERTIFICATE
-#define POLARSSL_ERR_SSL_NO_RNG MBEDTLS_ERR_SSL_NO_RNG
-#define POLARSSL_ERR_SSL_NO_USABLE_CIPHERSUITE MBEDTLS_ERR_SSL_NO_USABLE_CIPHERSUITE
-#define POLARSSL_ERR_SSL_PEER_CLOSE_NOTIFY MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY
-#define POLARSSL_ERR_SSL_PEER_VERIFY_FAILED MBEDTLS_ERR_SSL_PEER_VERIFY_FAILED
-#define POLARSSL_ERR_SSL_PK_TYPE_MISMATCH MBEDTLS_ERR_SSL_PK_TYPE_MISMATCH
-#define POLARSSL_ERR_SSL_PRIVATE_KEY_REQUIRED MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED
-#define POLARSSL_ERR_SSL_SESSION_TICKET_EXPIRED MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED
-#define POLARSSL_ERR_SSL_UNEXPECTED_MESSAGE MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE
-#define POLARSSL_ERR_SSL_UNKNOWN_CIPHER MBEDTLS_ERR_SSL_UNKNOWN_CIPHER
-#define POLARSSL_ERR_SSL_UNKNOWN_IDENTITY MBEDTLS_ERR_SSL_UNKNOWN_IDENTITY
-#define POLARSSL_ERR_SSL_WAITING_SERVER_HELLO_RENEGO MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO
-#define POLARSSL_ERR_THREADING_BAD_INPUT_DATA MBEDTLS_ERR_THREADING_BAD_INPUT_DATA
-#define POLARSSL_ERR_THREADING_FEATURE_UNAVAILABLE MBEDTLS_ERR_THREADING_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_THREADING_MUTEX_ERROR MBEDTLS_ERR_THREADING_MUTEX_ERROR
-#define POLARSSL_ERR_X509_BAD_INPUT_DATA MBEDTLS_ERR_X509_BAD_INPUT_DATA
-#define POLARSSL_ERR_X509_CERT_UNKNOWN_FORMAT MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT
-#define POLARSSL_ERR_X509_CERT_VERIFY_FAILED MBEDTLS_ERR_X509_CERT_VERIFY_FAILED
-#define POLARSSL_ERR_X509_FEATURE_UNAVAILABLE MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE
-#define POLARSSL_ERR_X509_FILE_IO_ERROR MBEDTLS_ERR_X509_FILE_IO_ERROR
-#define POLARSSL_ERR_X509_INVALID_ALG MBEDTLS_ERR_X509_INVALID_ALG
-#define POLARSSL_ERR_X509_INVALID_DATE MBEDTLS_ERR_X509_INVALID_DATE
-#define POLARSSL_ERR_X509_INVALID_EXTENSIONS MBEDTLS_ERR_X509_INVALID_EXTENSIONS
-#define POLARSSL_ERR_X509_INVALID_FORMAT MBEDTLS_ERR_X509_INVALID_FORMAT
-#define POLARSSL_ERR_X509_INVALID_NAME MBEDTLS_ERR_X509_INVALID_NAME
-#define POLARSSL_ERR_X509_INVALID_SERIAL MBEDTLS_ERR_X509_INVALID_SERIAL
-#define POLARSSL_ERR_X509_INVALID_SIGNATURE MBEDTLS_ERR_X509_INVALID_SIGNATURE
-#define POLARSSL_ERR_X509_INVALID_VERSION MBEDTLS_ERR_X509_INVALID_VERSION
-#define POLARSSL_ERR_X509_MALLOC_FAILED MBEDTLS_ERR_X509_ALLOC_FAILED
-#define POLARSSL_ERR_X509_SIG_MISMATCH MBEDTLS_ERR_X509_SIG_MISMATCH
-#define POLARSSL_ERR_X509_UNKNOWN_OID MBEDTLS_ERR_X509_UNKNOWN_OID
-#define POLARSSL_ERR_X509_UNKNOWN_SIG_ALG MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG
-#define POLARSSL_ERR_X509_UNKNOWN_VERSION MBEDTLS_ERR_X509_UNKNOWN_VERSION
-#define POLARSSL_ERR_XTEA_INVALID_INPUT_LENGTH MBEDTLS_ERR_XTEA_INVALID_INPUT_LENGTH
-#define POLARSSL_GCM_H MBEDTLS_GCM_H
-#define POLARSSL_HAVEGE_H MBEDTLS_HAVEGE_H
-#define POLARSSL_HAVE_INT32 MBEDTLS_HAVE_INT32
-#define POLARSSL_HAVE_INT64 MBEDTLS_HAVE_INT64
-#define POLARSSL_HAVE_UDBL MBEDTLS_HAVE_UDBL
-#define POLARSSL_HAVE_X86 MBEDTLS_HAVE_X86
-#define POLARSSL_HAVE_X86_64 MBEDTLS_HAVE_X86_64
-#define POLARSSL_HMAC_DRBG_H MBEDTLS_HMAC_DRBG_H
-#define POLARSSL_HMAC_DRBG_PR_OFF MBEDTLS_HMAC_DRBG_PR_OFF
-#define POLARSSL_HMAC_DRBG_PR_ON MBEDTLS_HMAC_DRBG_PR_ON
-#define POLARSSL_KEY_EXCHANGE_DHE_PSK MBEDTLS_KEY_EXCHANGE_DHE_PSK
-#define POLARSSL_KEY_EXCHANGE_DHE_RSA MBEDTLS_KEY_EXCHANGE_DHE_RSA
-#define POLARSSL_KEY_EXCHANGE_ECDHE_ECDSA MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA
-#define POLARSSL_KEY_EXCHANGE_ECDHE_PSK MBEDTLS_KEY_EXCHANGE_ECDHE_PSK
-#define POLARSSL_KEY_EXCHANGE_ECDHE_RSA MBEDTLS_KEY_EXCHANGE_ECDHE_RSA
-#define POLARSSL_KEY_EXCHANGE_ECDH_ECDSA MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA
-#define POLARSSL_KEY_EXCHANGE_ECDH_RSA MBEDTLS_KEY_EXCHANGE_ECDH_RSA
-#define POLARSSL_KEY_EXCHANGE_NONE MBEDTLS_KEY_EXCHANGE_NONE
-#define POLARSSL_KEY_EXCHANGE_PSK MBEDTLS_KEY_EXCHANGE_PSK
-#define POLARSSL_KEY_EXCHANGE_RSA MBEDTLS_KEY_EXCHANGE_RSA
-#define POLARSSL_KEY_EXCHANGE_RSA_PSK MBEDTLS_KEY_EXCHANGE_RSA_PSK
-#define POLARSSL_KEY_EXCHANGE__SOME__ECDHE_ENABLED MBEDTLS_KEY_EXCHANGE__SOME__ECDHE_ENABLED
-#define POLARSSL_KEY_EXCHANGE__SOME__PSK_ENABLED MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED
-#define POLARSSL_KEY_EXCHANGE__WITH_CERT__ENABLED MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED
-#define POLARSSL_KEY_LENGTH_DES MBEDTLS_KEY_LENGTH_DES
-#define POLARSSL_KEY_LENGTH_DES_EDE MBEDTLS_KEY_LENGTH_DES_EDE
-#define POLARSSL_KEY_LENGTH_DES_EDE3 MBEDTLS_KEY_LENGTH_DES_EDE3
-#define POLARSSL_KEY_LENGTH_NONE MBEDTLS_KEY_LENGTH_NONE
-#define POLARSSL_MAX_BLOCK_LENGTH MBEDTLS_MAX_BLOCK_LENGTH
-#define POLARSSL_MAX_IV_LENGTH MBEDTLS_MAX_IV_LENGTH
-#define POLARSSL_MD2_H MBEDTLS_MD2_H
-#define POLARSSL_MD4_H MBEDTLS_MD4_H
-#define POLARSSL_MD5_H MBEDTLS_MD5_H
-#define POLARSSL_MD_H MBEDTLS_MD_H
-#define POLARSSL_MD_MAX_SIZE MBEDTLS_MD_MAX_SIZE
-#define POLARSSL_MD_MD2 MBEDTLS_MD_MD2
-#define POLARSSL_MD_MD4 MBEDTLS_MD_MD4
-#define POLARSSL_MD_MD5 MBEDTLS_MD_MD5
-#define POLARSSL_MD_NONE MBEDTLS_MD_NONE
-#define POLARSSL_MD_RIPEMD160 MBEDTLS_MD_RIPEMD160
-#define POLARSSL_MD_SHA1 MBEDTLS_MD_SHA1
-#define POLARSSL_MD_SHA224 MBEDTLS_MD_SHA224
-#define POLARSSL_MD_SHA256 MBEDTLS_MD_SHA256
-#define POLARSSL_MD_SHA384 MBEDTLS_MD_SHA384
-#define POLARSSL_MD_SHA512 MBEDTLS_MD_SHA512
-#define POLARSSL_MD_WRAP_H MBEDTLS_MD_WRAP_H
-#define POLARSSL_MEMORY_BUFFER_ALLOC_H MBEDTLS_MEMORY_BUFFER_ALLOC_H
-#define POLARSSL_MODE_CBC MBEDTLS_MODE_CBC
-#define POLARSSL_MODE_CCM MBEDTLS_MODE_CCM
-#define POLARSSL_MODE_CFB MBEDTLS_MODE_CFB
-#define POLARSSL_MODE_CTR MBEDTLS_MODE_CTR
-#define POLARSSL_MODE_ECB MBEDTLS_MODE_ECB
-#define POLARSSL_MODE_GCM MBEDTLS_MODE_GCM
-#define POLARSSL_MODE_NONE MBEDTLS_MODE_NONE
-#define POLARSSL_MODE_OFB MBEDTLS_MODE_OFB
-#define POLARSSL_MODE_STREAM MBEDTLS_MODE_STREAM
-#define POLARSSL_MPI_MAX_BITS MBEDTLS_MPI_MAX_BITS
-#define POLARSSL_MPI_MAX_BITS_SCALE100 MBEDTLS_MPI_MAX_BITS_SCALE100
-#define POLARSSL_MPI_MAX_LIMBS MBEDTLS_MPI_MAX_LIMBS
-#define POLARSSL_MPI_RW_BUFFER_SIZE MBEDTLS_MPI_RW_BUFFER_SIZE
-#define POLARSSL_NET_H MBEDTLS_NET_SOCKETS_H
-#define POLARSSL_NET_LISTEN_BACKLOG MBEDTLS_NET_LISTEN_BACKLOG
-#define POLARSSL_OID_H MBEDTLS_OID_H
-#define POLARSSL_OPERATION_NONE MBEDTLS_OPERATION_NONE
-#define POLARSSL_PADDING_NONE MBEDTLS_PADDING_NONE
-#define POLARSSL_PADDING_ONE_AND_ZEROS MBEDTLS_PADDING_ONE_AND_ZEROS
-#define POLARSSL_PADDING_PKCS7 MBEDTLS_PADDING_PKCS7
-#define POLARSSL_PADDING_ZEROS MBEDTLS_PADDING_ZEROS
-#define POLARSSL_PADDING_ZEROS_AND_LEN MBEDTLS_PADDING_ZEROS_AND_LEN
-#define POLARSSL_PADLOCK_H MBEDTLS_PADLOCK_H
-#define POLARSSL_PEM_H MBEDTLS_PEM_H
-#define POLARSSL_PKCS11_H MBEDTLS_PKCS11_H
-#define POLARSSL_PKCS12_H MBEDTLS_PKCS12_H
-#define POLARSSL_PKCS5_H MBEDTLS_PKCS5_H
-#define POLARSSL_PK_DEBUG_ECP MBEDTLS_PK_DEBUG_ECP
-#define POLARSSL_PK_DEBUG_MAX_ITEMS MBEDTLS_PK_DEBUG_MAX_ITEMS
-#define POLARSSL_PK_DEBUG_MPI MBEDTLS_PK_DEBUG_MPI
-#define POLARSSL_PK_DEBUG_NONE MBEDTLS_PK_DEBUG_NONE
-#define POLARSSL_PK_ECDSA MBEDTLS_PK_ECDSA
-#define POLARSSL_PK_ECKEY MBEDTLS_PK_ECKEY
-#define POLARSSL_PK_ECKEY_DH MBEDTLS_PK_ECKEY_DH
-#define POLARSSL_PK_H MBEDTLS_PK_H
-#define POLARSSL_PK_NONE MBEDTLS_PK_NONE
-#define POLARSSL_PK_RSA MBEDTLS_PK_RSA
-#define POLARSSL_PK_RSASSA_PSS MBEDTLS_PK_RSASSA_PSS
-#define POLARSSL_PK_RSA_ALT MBEDTLS_PK_RSA_ALT
-#define POLARSSL_PK_WRAP_H MBEDTLS_PK_WRAP_H
-#define POLARSSL_PLATFORM_H MBEDTLS_PLATFORM_H
-#define POLARSSL_PREMASTER_SIZE MBEDTLS_PREMASTER_SIZE
-#define POLARSSL_RIPEMD160_H MBEDTLS_RIPEMD160_H
-#define POLARSSL_RSA_H MBEDTLS_RSA_H
-#define POLARSSL_SHA1_H MBEDTLS_SHA1_H
-#define POLARSSL_SHA256_H MBEDTLS_SHA256_H
-#define POLARSSL_SHA512_H MBEDTLS_SHA512_H
-#define POLARSSL_SSL_CACHE_H MBEDTLS_SSL_CACHE_H
-#define POLARSSL_SSL_CIPHERSUITES_H MBEDTLS_SSL_CIPHERSUITES_H
-#define POLARSSL_SSL_COOKIE_H MBEDTLS_SSL_COOKIE_H
-#define POLARSSL_SSL_H MBEDTLS_SSL_H
-#define POLARSSL_THREADING_H MBEDTLS_THREADING_H
-#define POLARSSL_THREADING_IMPL MBEDTLS_THREADING_IMPL
-#define POLARSSL_TIMING_H MBEDTLS_TIMING_H
-#define POLARSSL_VERSION_H MBEDTLS_VERSION_H
-#define POLARSSL_VERSION_MAJOR MBEDTLS_VERSION_MAJOR
-#define POLARSSL_VERSION_MINOR MBEDTLS_VERSION_MINOR
-#define POLARSSL_VERSION_NUMBER MBEDTLS_VERSION_NUMBER
-#define POLARSSL_VERSION_PATCH MBEDTLS_VERSION_PATCH
-#define POLARSSL_VERSION_STRING MBEDTLS_VERSION_STRING
-#define POLARSSL_VERSION_STRING_FULL MBEDTLS_VERSION_STRING_FULL
-#define POLARSSL_X509_CRL_H MBEDTLS_X509_CRL_H
-#define POLARSSL_X509_CRT_H MBEDTLS_X509_CRT_H
-#define POLARSSL_X509_CSR_H MBEDTLS_X509_CSR_H
-#define POLARSSL_X509_H MBEDTLS_X509_H
-#define POLARSSL_XTEA_H MBEDTLS_XTEA_H
-#define RSA_CRYPT MBEDTLS_RSA_CRYPT
-#define RSA_PKCS_V15 MBEDTLS_RSA_PKCS_V15
-#define RSA_PKCS_V21 MBEDTLS_RSA_PKCS_V21
-#define RSA_PRIVATE MBEDTLS_RSA_PRIVATE
-#define RSA_PUBLIC MBEDTLS_RSA_PUBLIC
-#define RSA_SALT_LEN_ANY MBEDTLS_RSA_SALT_LEN_ANY
-#define RSA_SIGN MBEDTLS_RSA_SIGN
-#define SSL_ALERT_LEVEL_FATAL MBEDTLS_SSL_ALERT_LEVEL_FATAL
-#define SSL_ALERT_LEVEL_WARNING MBEDTLS_SSL_ALERT_LEVEL_WARNING
-#define SSL_ALERT_MSG_ACCESS_DENIED MBEDTLS_SSL_ALERT_MSG_ACCESS_DENIED
-#define SSL_ALERT_MSG_BAD_CERT MBEDTLS_SSL_ALERT_MSG_BAD_CERT
-#define SSL_ALERT_MSG_BAD_RECORD_MAC MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC
-#define SSL_ALERT_MSG_CERT_EXPIRED MBEDTLS_SSL_ALERT_MSG_CERT_EXPIRED
-#define SSL_ALERT_MSG_CERT_REVOKED MBEDTLS_SSL_ALERT_MSG_CERT_REVOKED
-#define SSL_ALERT_MSG_CERT_UNKNOWN MBEDTLS_SSL_ALERT_MSG_CERT_UNKNOWN
-#define SSL_ALERT_MSG_CLOSE_NOTIFY MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY
-#define SSL_ALERT_MSG_DECODE_ERROR MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR
-#define SSL_ALERT_MSG_DECOMPRESSION_FAILURE MBEDTLS_SSL_ALERT_MSG_DECOMPRESSION_FAILURE
-#define SSL_ALERT_MSG_DECRYPTION_FAILED MBEDTLS_SSL_ALERT_MSG_DECRYPTION_FAILED
-#define SSL_ALERT_MSG_DECRYPT_ERROR MBEDTLS_SSL_ALERT_MSG_DECRYPT_ERROR
-#define SSL_ALERT_MSG_EXPORT_RESTRICTION MBEDTLS_SSL_ALERT_MSG_EXPORT_RESTRICTION
-#define SSL_ALERT_MSG_HANDSHAKE_FAILURE MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE
-#define SSL_ALERT_MSG_ILLEGAL_PARAMETER MBEDTLS_SSL_ALERT_MSG_ILLEGAL_PARAMETER
-#define SSL_ALERT_MSG_INAPROPRIATE_FALLBACK MBEDTLS_SSL_ALERT_MSG_INAPROPRIATE_FALLBACK
-#define SSL_ALERT_MSG_INSUFFICIENT_SECURITY MBEDTLS_SSL_ALERT_MSG_INSUFFICIENT_SECURITY
-#define SSL_ALERT_MSG_INTERNAL_ERROR MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR
-#define SSL_ALERT_MSG_NO_APPLICATION_PROTOCOL MBEDTLS_SSL_ALERT_MSG_NO_APPLICATION_PROTOCOL
-#define SSL_ALERT_MSG_NO_CERT MBEDTLS_SSL_ALERT_MSG_NO_CERT
-#define SSL_ALERT_MSG_NO_RENEGOTIATION MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION
-#define SSL_ALERT_MSG_PROTOCOL_VERSION MBEDTLS_SSL_ALERT_MSG_PROTOCOL_VERSION
-#define SSL_ALERT_MSG_RECORD_OVERFLOW MBEDTLS_SSL_ALERT_MSG_RECORD_OVERFLOW
-#define SSL_ALERT_MSG_UNEXPECTED_MESSAGE MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE
-#define SSL_ALERT_MSG_UNKNOWN_CA MBEDTLS_SSL_ALERT_MSG_UNKNOWN_CA
-#define SSL_ALERT_MSG_UNKNOWN_PSK_IDENTITY MBEDTLS_SSL_ALERT_MSG_UNKNOWN_PSK_IDENTITY
-#define SSL_ALERT_MSG_UNRECOGNIZED_NAME MBEDTLS_SSL_ALERT_MSG_UNRECOGNIZED_NAME
-#define SSL_ALERT_MSG_UNSUPPORTED_CERT MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_CERT
-#define SSL_ALERT_MSG_UNSUPPORTED_EXT MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_EXT
-#define SSL_ALERT_MSG_USER_CANCELED MBEDTLS_SSL_ALERT_MSG_USER_CANCELED
-#define SSL_ANTI_REPLAY_DISABLED MBEDTLS_SSL_ANTI_REPLAY_DISABLED
-#define SSL_ANTI_REPLAY_ENABLED MBEDTLS_SSL_ANTI_REPLAY_ENABLED
-#define SSL_ARC4_DISABLED MBEDTLS_SSL_ARC4_DISABLED
-#define SSL_ARC4_ENABLED MBEDTLS_SSL_ARC4_ENABLED
-#define SSL_BUFFER_LEN ( ( ( MBEDTLS_SSL_IN_BUFFER_LEN ) < ( MBEDTLS_SSL_OUT_BUFFER_LEN ) ) \
-                         ? ( MBEDTLS_SSL_IN_BUFFER_LEN ) : ( MBEDTLS_SSL_OUT_BUFFER_LEN ) )
-#define SSL_CACHE_DEFAULT_MAX_ENTRIES MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES
-#define SSL_CACHE_DEFAULT_TIMEOUT MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT
-#define SSL_CBC_RECORD_SPLITTING_DISABLED MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED
-#define SSL_CBC_RECORD_SPLITTING_ENABLED MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED
-#define SSL_CERTIFICATE_REQUEST MBEDTLS_SSL_CERTIFICATE_REQUEST
-#define SSL_CERTIFICATE_VERIFY MBEDTLS_SSL_CERTIFICATE_VERIFY
-#define SSL_CERT_TYPE_ECDSA_SIGN MBEDTLS_SSL_CERT_TYPE_ECDSA_SIGN
-#define SSL_CERT_TYPE_RSA_SIGN MBEDTLS_SSL_CERT_TYPE_RSA_SIGN
-#define SSL_CHANNEL_INBOUND MBEDTLS_SSL_CHANNEL_INBOUND
-#define SSL_CHANNEL_OUTBOUND MBEDTLS_SSL_CHANNEL_OUTBOUND
-#define SSL_CIPHERSUITES MBEDTLS_SSL_CIPHERSUITES
-#define SSL_CLIENT_CERTIFICATE MBEDTLS_SSL_CLIENT_CERTIFICATE
-#define SSL_CLIENT_CHANGE_CIPHER_SPEC MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC
-#define SSL_CLIENT_FINISHED MBEDTLS_SSL_CLIENT_FINISHED
-#define SSL_CLIENT_HELLO MBEDTLS_SSL_CLIENT_HELLO
-#define SSL_CLIENT_KEY_EXCHANGE MBEDTLS_SSL_CLIENT_KEY_EXCHANGE
-#define SSL_COMPRESSION_ADD MBEDTLS_SSL_COMPRESSION_ADD
-#define SSL_COMPRESS_DEFLATE MBEDTLS_SSL_COMPRESS_DEFLATE
-#define SSL_COMPRESS_NULL MBEDTLS_SSL_COMPRESS_NULL
-#define SSL_DEBUG_BUF MBEDTLS_SSL_DEBUG_BUF
-#define SSL_DEBUG_CRT MBEDTLS_SSL_DEBUG_CRT
-#define SSL_DEBUG_ECP MBEDTLS_SSL_DEBUG_ECP
-#define SSL_DEBUG_MPI MBEDTLS_SSL_DEBUG_MPI
-#define SSL_DEBUG_MSG MBEDTLS_SSL_DEBUG_MSG
-#define SSL_DEBUG_RET MBEDTLS_SSL_DEBUG_RET
-#define SSL_DEFAULT_TICKET_LIFETIME MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME
-#define SSL_DTLS_TIMEOUT_DFL_MAX MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MAX
-#define SSL_DTLS_TIMEOUT_DFL_MIN MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MIN
-#define SSL_EMPTY_RENEGOTIATION_INFO MBEDTLS_SSL_EMPTY_RENEGOTIATION_INFO
-#define SSL_ETM_DISABLED MBEDTLS_SSL_ETM_DISABLED
-#define SSL_ETM_ENABLED MBEDTLS_SSL_ETM_ENABLED
-#define SSL_EXTENDED_MS_DISABLED MBEDTLS_SSL_EXTENDED_MS_DISABLED
-#define SSL_EXTENDED_MS_ENABLED MBEDTLS_SSL_EXTENDED_MS_ENABLED
-#define SSL_FALLBACK_SCSV MBEDTLS_SSL_FALLBACK_SCSV
-#define SSL_FLUSH_BUFFERS MBEDTLS_SSL_FLUSH_BUFFERS
-#define SSL_HANDSHAKE_OVER MBEDTLS_SSL_HANDSHAKE_OVER
-#define SSL_HANDSHAKE_WRAPUP MBEDTLS_SSL_HANDSHAKE_WRAPUP
-#define SSL_HASH_MD5 MBEDTLS_SSL_HASH_MD5
-#define SSL_HASH_NONE MBEDTLS_SSL_HASH_NONE
-#define SSL_HASH_SHA1 MBEDTLS_SSL_HASH_SHA1
-#define SSL_HASH_SHA224 MBEDTLS_SSL_HASH_SHA224
-#define SSL_HASH_SHA256 MBEDTLS_SSL_HASH_SHA256
-#define SSL_HASH_SHA384 MBEDTLS_SSL_HASH_SHA384
-#define SSL_HASH_SHA512 MBEDTLS_SSL_HASH_SHA512
-#define SSL_HELLO_REQUEST MBEDTLS_SSL_HELLO_REQUEST
-#define SSL_HS_CERTIFICATE MBEDTLS_SSL_HS_CERTIFICATE
-#define SSL_HS_CERTIFICATE_REQUEST MBEDTLS_SSL_HS_CERTIFICATE_REQUEST
-#define SSL_HS_CERTIFICATE_VERIFY MBEDTLS_SSL_HS_CERTIFICATE_VERIFY
-#define SSL_HS_CLIENT_HELLO MBEDTLS_SSL_HS_CLIENT_HELLO
-#define SSL_HS_CLIENT_KEY_EXCHANGE MBEDTLS_SSL_HS_CLIENT_KEY_EXCHANGE
-#define SSL_HS_FINISHED MBEDTLS_SSL_HS_FINISHED
-#define SSL_HS_HELLO_REQUEST MBEDTLS_SSL_HS_HELLO_REQUEST
-#define SSL_HS_HELLO_VERIFY_REQUEST MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST
-#define SSL_HS_NEW_SESSION_TICKET MBEDTLS_SSL_HS_NEW_SESSION_TICKET
-#define SSL_HS_SERVER_HELLO MBEDTLS_SSL_HS_SERVER_HELLO
-#define SSL_HS_SERVER_HELLO_DONE MBEDTLS_SSL_HS_SERVER_HELLO_DONE
-#define SSL_HS_SERVER_KEY_EXCHANGE MBEDTLS_SSL_HS_SERVER_KEY_EXCHANGE
-#define SSL_INITIAL_HANDSHAKE MBEDTLS_SSL_INITIAL_HANDSHAKE
-#define SSL_IS_CLIENT MBEDTLS_SSL_IS_CLIENT
-#define SSL_IS_FALLBACK MBEDTLS_SSL_IS_FALLBACK
-#define SSL_IS_NOT_FALLBACK MBEDTLS_SSL_IS_NOT_FALLBACK
-#define SSL_IS_SERVER MBEDTLS_SSL_IS_SERVER
-#define SSL_LEGACY_ALLOW_RENEGOTIATION MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION
-#define SSL_LEGACY_BREAK_HANDSHAKE MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE
-#define SSL_LEGACY_NO_RENEGOTIATION MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION
-#define SSL_LEGACY_RENEGOTIATION MBEDTLS_SSL_LEGACY_RENEGOTIATION
-#define SSL_MAC_ADD MBEDTLS_SSL_MAC_ADD
-#define SSL_MAJOR_VERSION_3 MBEDTLS_SSL_MAJOR_VERSION_3
-#define SSL_MAX_CONTENT_LEN MBEDTLS_SSL_MAX_CONTENT_LEN
-#define SSL_MAX_FRAG_LEN_1024 MBEDTLS_SSL_MAX_FRAG_LEN_1024
-#define SSL_MAX_FRAG_LEN_2048 MBEDTLS_SSL_MAX_FRAG_LEN_2048
-#define SSL_MAX_FRAG_LEN_4096 MBEDTLS_SSL_MAX_FRAG_LEN_4096
-#define SSL_MAX_FRAG_LEN_512 MBEDTLS_SSL_MAX_FRAG_LEN_512
-#define SSL_MAX_FRAG_LEN_INVALID MBEDTLS_SSL_MAX_FRAG_LEN_INVALID
-#define SSL_MAX_FRAG_LEN_NONE MBEDTLS_SSL_MAX_FRAG_LEN_NONE
-#define SSL_MAX_MAJOR_VERSION MBEDTLS_SSL_MAX_MAJOR_VERSION
-#define SSL_MAX_MINOR_VERSION MBEDTLS_SSL_MAX_MINOR_VERSION
-#define SSL_MINOR_VERSION_0 MBEDTLS_SSL_MINOR_VERSION_0
-#define SSL_MINOR_VERSION_1 MBEDTLS_SSL_MINOR_VERSION_1
-#define SSL_MINOR_VERSION_2 MBEDTLS_SSL_MINOR_VERSION_2
-#define SSL_MINOR_VERSION_3 MBEDTLS_SSL_MINOR_VERSION_3
-#define SSL_MIN_MAJOR_VERSION MBEDTLS_SSL_MIN_MAJOR_VERSION
-#define SSL_MIN_MINOR_VERSION MBEDTLS_SSL_MIN_MINOR_VERSION
-#define SSL_MSG_ALERT MBEDTLS_SSL_MSG_ALERT
-#define SSL_MSG_APPLICATION_DATA MBEDTLS_SSL_MSG_APPLICATION_DATA
-#define SSL_MSG_CHANGE_CIPHER_SPEC MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC
-#define SSL_MSG_HANDSHAKE MBEDTLS_SSL_MSG_HANDSHAKE
-#define SSL_PADDING_ADD MBEDTLS_SSL_PADDING_ADD
-#define SSL_RENEGOTIATION MBEDTLS_SSL_RENEGOTIATION
-#define SSL_RENEGOTIATION_DISABLED MBEDTLS_SSL_RENEGOTIATION_DISABLED
-#define SSL_RENEGOTIATION_DONE MBEDTLS_SSL_RENEGOTIATION_DONE
-#define SSL_RENEGOTIATION_ENABLED MBEDTLS_SSL_RENEGOTIATION_ENABLED
-#define SSL_RENEGOTIATION_NOT_ENFORCED MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED
-#define SSL_RENEGOTIATION_PENDING MBEDTLS_SSL_RENEGOTIATION_PENDING
-#define SSL_RENEGO_MAX_RECORDS_DEFAULT MBEDTLS_SSL_RENEGO_MAX_RECORDS_DEFAULT
-#define SSL_RETRANS_FINISHED MBEDTLS_SSL_RETRANS_FINISHED
-#define SSL_RETRANS_PREPARING MBEDTLS_SSL_RETRANS_PREPARING
-#define SSL_RETRANS_SENDING MBEDTLS_SSL_RETRANS_SENDING
-#define SSL_RETRANS_WAITING MBEDTLS_SSL_RETRANS_WAITING
-#define SSL_SECURE_RENEGOTIATION MBEDTLS_SSL_SECURE_RENEGOTIATION
-#define SSL_SERVER_CERTIFICATE MBEDTLS_SSL_SERVER_CERTIFICATE
-#define SSL_SERVER_CHANGE_CIPHER_SPEC MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC
-#define SSL_SERVER_FINISHED MBEDTLS_SSL_SERVER_FINISHED
-#define SSL_SERVER_HELLO MBEDTLS_SSL_SERVER_HELLO
-#define SSL_SERVER_HELLO_DONE MBEDTLS_SSL_SERVER_HELLO_DONE
-#define SSL_SERVER_HELLO_VERIFY_REQUEST_SENT MBEDTLS_SSL_SERVER_HELLO_VERIFY_REQUEST_SENT
-#define SSL_SERVER_KEY_EXCHANGE MBEDTLS_SSL_SERVER_KEY_EXCHANGE
-#define SSL_SERVER_NEW_SESSION_TICKET MBEDTLS_SSL_SERVER_NEW_SESSION_TICKET
-#define SSL_SESSION_TICKETS_DISABLED MBEDTLS_SSL_SESSION_TICKETS_DISABLED
-#define SSL_SESSION_TICKETS_ENABLED MBEDTLS_SSL_SESSION_TICKETS_ENABLED
-#define SSL_SIG_ANON MBEDTLS_SSL_SIG_ANON
-#define SSL_SIG_ECDSA MBEDTLS_SSL_SIG_ECDSA
-#define SSL_SIG_RSA MBEDTLS_SSL_SIG_RSA
-#define SSL_TRANSPORT_DATAGRAM MBEDTLS_SSL_TRANSPORT_DATAGRAM
-#define SSL_TRANSPORT_STREAM MBEDTLS_SSL_TRANSPORT_STREAM
-#define SSL_TRUNCATED_HMAC_LEN MBEDTLS_SSL_TRUNCATED_HMAC_LEN
-#define SSL_TRUNC_HMAC_DISABLED MBEDTLS_SSL_TRUNC_HMAC_DISABLED
-#define SSL_TRUNC_HMAC_ENABLED MBEDTLS_SSL_TRUNC_HMAC_ENABLED
-#define SSL_VERIFY_DATA_MAX_LEN MBEDTLS_SSL_VERIFY_DATA_MAX_LEN
-#define SSL_VERIFY_NONE MBEDTLS_SSL_VERIFY_NONE
-#define SSL_VERIFY_OPTIONAL MBEDTLS_SSL_VERIFY_OPTIONAL
-#define SSL_VERIFY_REQUIRED MBEDTLS_SSL_VERIFY_REQUIRED
-#define TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
-#define TLS_DHE_PSK_WITH_AES_128_CBC_SHA MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
-#define TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
-#define TLS_DHE_PSK_WITH_AES_128_CCM MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM
-#define TLS_DHE_PSK_WITH_AES_128_CCM_8 MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM_8
-#define TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
-#define TLS_DHE_PSK_WITH_AES_256_CBC_SHA MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
-#define TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
-#define TLS_DHE_PSK_WITH_AES_256_CCM MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM
-#define TLS_DHE_PSK_WITH_AES_256_CCM_8 MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM_8
-#define TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
-#define TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
-#define TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
-#define TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
-#define TLS_DHE_PSK_WITH_NULL_SHA MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA
-#define TLS_DHE_PSK_WITH_NULL_SHA256 MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256
-#define TLS_DHE_PSK_WITH_NULL_SHA384 MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384
-#define TLS_DHE_PSK_WITH_RC4_128_SHA MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
-#define TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
-#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
-#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
-#define TLS_DHE_RSA_WITH_AES_128_CCM MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM
-#define TLS_DHE_RSA_WITH_AES_128_CCM_8 MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM_8
-#define TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
-#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
-#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
-#define TLS_DHE_RSA_WITH_AES_256_CCM MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM
-#define TLS_DHE_RSA_WITH_AES_256_CCM_8 MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM_8
-#define TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
-#define TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
-#define TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
-#define TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
-#define TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
-#define TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
-#define TLS_DHE_RSA_WITH_DES_CBC_SHA MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA
-#define TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
-#define TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
-#define TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
-#define TLS_ECDHE_ECDSA_WITH_AES_128_CCM MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM
-#define TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8
-#define TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
-#define TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
-#define TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
-#define TLS_ECDHE_ECDSA_WITH_AES_256_CCM MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM
-#define TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8
-#define TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
-#define TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
-#define TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
-#define TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
-#define TLS_ECDHE_ECDSA_WITH_NULL_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA
-#define TLS_ECDHE_ECDSA_WITH_RC4_128_SHA MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
-#define TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
-#define TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
-#define TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
-#define TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
-#define TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
-#define TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
-#define TLS_ECDHE_PSK_WITH_NULL_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA
-#define TLS_ECDHE_PSK_WITH_NULL_SHA256 MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256
-#define TLS_ECDHE_PSK_WITH_NULL_SHA384 MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384
-#define TLS_ECDHE_PSK_WITH_RC4_128_SHA MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
-#define TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
-#define TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
-#define TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
-#define TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
-#define TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
-#define TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
-#define TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
-#define TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
-#define TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
-#define TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
-#define TLS_ECDHE_RSA_WITH_NULL_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA
-#define TLS_ECDHE_RSA_WITH_RC4_128_SHA MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
-#define TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
-#define TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
-#define TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
-#define TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
-#define TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
-#define TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
-#define TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
-#define TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
-#define TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
-#define TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
-#define TLS_ECDH_ECDSA_WITH_NULL_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA
-#define TLS_ECDH_ECDSA_WITH_RC4_128_SHA MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
-#define TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
-#define TLS_ECDH_RSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
-#define TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
-#define TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
-#define TLS_ECDH_RSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
-#define TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
-#define TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
-#define TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
-#define TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
-#define TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
-#define TLS_ECDH_RSA_WITH_NULL_SHA MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA
-#define TLS_ECDH_RSA_WITH_RC4_128_SHA MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
-#define TLS_EXT_ALPN MBEDTLS_TLS_EXT_ALPN
-#define TLS_EXT_ENCRYPT_THEN_MAC MBEDTLS_TLS_EXT_ENCRYPT_THEN_MAC
-#define TLS_EXT_EXTENDED_MASTER_SECRET MBEDTLS_TLS_EXT_EXTENDED_MASTER_SECRET
-#define TLS_EXT_MAX_FRAGMENT_LENGTH MBEDTLS_TLS_EXT_MAX_FRAGMENT_LENGTH
-#define TLS_EXT_RENEGOTIATION_INFO MBEDTLS_TLS_EXT_RENEGOTIATION_INFO
-#define TLS_EXT_SERVERNAME MBEDTLS_TLS_EXT_SERVERNAME
-#define TLS_EXT_SERVERNAME_HOSTNAME MBEDTLS_TLS_EXT_SERVERNAME_HOSTNAME
-#define TLS_EXT_SESSION_TICKET MBEDTLS_TLS_EXT_SESSION_TICKET
-#define TLS_EXT_SIG_ALG MBEDTLS_TLS_EXT_SIG_ALG
-#define TLS_EXT_SUPPORTED_ELLIPTIC_CURVES MBEDTLS_TLS_EXT_SUPPORTED_ELLIPTIC_CURVES
-#define TLS_EXT_SUPPORTED_POINT_FORMATS MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS
-#define TLS_EXT_SUPPORTED_POINT_FORMATS_PRESENT MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS_PRESENT
-#define TLS_EXT_TRUNCATED_HMAC MBEDTLS_TLS_EXT_TRUNCATED_HMAC
-#define TLS_PSK_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
-#define TLS_PSK_WITH_AES_128_CBC_SHA MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
-#define TLS_PSK_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
-#define TLS_PSK_WITH_AES_128_CCM MBEDTLS_TLS_PSK_WITH_AES_128_CCM
-#define TLS_PSK_WITH_AES_128_CCM_8 MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8
-#define TLS_PSK_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
-#define TLS_PSK_WITH_AES_256_CBC_SHA MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
-#define TLS_PSK_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
-#define TLS_PSK_WITH_AES_256_CCM MBEDTLS_TLS_PSK_WITH_AES_256_CCM
-#define TLS_PSK_WITH_AES_256_CCM_8 MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8
-#define TLS_PSK_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
-#define TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
-#define TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
-#define TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
-#define TLS_PSK_WITH_NULL_SHA MBEDTLS_TLS_PSK_WITH_NULL_SHA
-#define TLS_PSK_WITH_NULL_SHA256 MBEDTLS_TLS_PSK_WITH_NULL_SHA256
-#define TLS_PSK_WITH_NULL_SHA384 MBEDTLS_TLS_PSK_WITH_NULL_SHA384
-#define TLS_PSK_WITH_RC4_128_SHA MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
-#define TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
-#define TLS_RSA_PSK_WITH_AES_128_CBC_SHA MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
-#define TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
-#define TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
-#define TLS_RSA_PSK_WITH_AES_256_CBC_SHA MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
-#define TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
-#define TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
-#define TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
-#define TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
-#define TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
-#define TLS_RSA_PSK_WITH_NULL_SHA MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA
-#define TLS_RSA_PSK_WITH_NULL_SHA256 MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256
-#define TLS_RSA_PSK_WITH_NULL_SHA384 MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384
-#define TLS_RSA_PSK_WITH_RC4_128_SHA MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
-#define TLS_RSA_WITH_3DES_EDE_CBC_SHA MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
-#define TLS_RSA_WITH_AES_128_CBC_SHA MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
-#define TLS_RSA_WITH_AES_128_CBC_SHA256 MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
-#define TLS_RSA_WITH_AES_128_CCM MBEDTLS_TLS_RSA_WITH_AES_128_CCM
-#define TLS_RSA_WITH_AES_128_CCM_8 MBEDTLS_TLS_RSA_WITH_AES_128_CCM_8
-#define TLS_RSA_WITH_AES_128_GCM_SHA256 MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
-#define TLS_RSA_WITH_AES_256_CBC_SHA MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
-#define TLS_RSA_WITH_AES_256_CBC_SHA256 MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
-#define TLS_RSA_WITH_AES_256_CCM MBEDTLS_TLS_RSA_WITH_AES_256_CCM
-#define TLS_RSA_WITH_AES_256_CCM_8 MBEDTLS_TLS_RSA_WITH_AES_256_CCM_8
-#define TLS_RSA_WITH_AES_256_GCM_SHA384 MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
-#define TLS_RSA_WITH_CAMELLIA_128_CBC_SHA MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
-#define TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
-#define TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
-#define TLS_RSA_WITH_CAMELLIA_256_CBC_SHA MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
-#define TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
-#define TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
-#define TLS_RSA_WITH_DES_CBC_SHA MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA
-#define TLS_RSA_WITH_NULL_MD5 MBEDTLS_TLS_RSA_WITH_NULL_MD5
-#define TLS_RSA_WITH_NULL_SHA MBEDTLS_TLS_RSA_WITH_NULL_SHA
-#define TLS_RSA_WITH_NULL_SHA256 MBEDTLS_TLS_RSA_WITH_NULL_SHA256
-#define TLS_RSA_WITH_RC4_128_MD5 MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
-#define TLS_RSA_WITH_RC4_128_SHA MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
-#define X509_CRT_VERSION_1 MBEDTLS_X509_CRT_VERSION_1
-#define X509_CRT_VERSION_2 MBEDTLS_X509_CRT_VERSION_2
-#define X509_CRT_VERSION_3 MBEDTLS_X509_CRT_VERSION_3
-#define X509_FORMAT_DER MBEDTLS_X509_FORMAT_DER
-#define X509_FORMAT_PEM MBEDTLS_X509_FORMAT_PEM
-#define X509_MAX_DN_NAME_SIZE MBEDTLS_X509_MAX_DN_NAME_SIZE
-#define X509_RFC5280_MAX_SERIAL_LEN MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN
-#define X509_RFC5280_UTC_TIME_LEN MBEDTLS_X509_RFC5280_UTC_TIME_LEN
-#define XTEA_DECRYPT MBEDTLS_XTEA_DECRYPT
-#define XTEA_ENCRYPT MBEDTLS_XTEA_ENCRYPT
-#define _asn1_bitstring mbedtls_asn1_bitstring
-#define _asn1_buf mbedtls_asn1_buf
-#define _asn1_named_data mbedtls_asn1_named_data
-#define _asn1_sequence mbedtls_asn1_sequence
-#define _ssl_cache_context mbedtls_ssl_cache_context
-#define _ssl_cache_entry mbedtls_ssl_cache_entry
-#define _ssl_ciphersuite_t mbedtls_ssl_ciphersuite_t
-#define _ssl_context mbedtls_ssl_context
-#define _ssl_flight_item mbedtls_ssl_flight_item
-#define _ssl_handshake_params mbedtls_ssl_handshake_params
-#define _ssl_key_cert mbedtls_ssl_key_cert
-#define _ssl_premaster_secret mbedtls_ssl_premaster_secret
-#define _ssl_session mbedtls_ssl_session
-#define _ssl_transform mbedtls_ssl_transform
-#define _x509_crl mbedtls_x509_crl
-#define _x509_crl_entry mbedtls_x509_crl_entry
-#define _x509_crt mbedtls_x509_crt
-#define _x509_csr mbedtls_x509_csr
-#define _x509_time mbedtls_x509_time
-#define _x509write_cert mbedtls_x509write_cert
-#define _x509write_csr mbedtls_x509write_csr
-#define aes_context mbedtls_aes_context
-#define aes_crypt_cbc mbedtls_aes_crypt_cbc
-#define aes_crypt_cfb128 mbedtls_aes_crypt_cfb128
-#define aes_crypt_cfb8 mbedtls_aes_crypt_cfb8
-#define aes_crypt_ctr mbedtls_aes_crypt_ctr
-#define aes_crypt_ecb mbedtls_aes_crypt_ecb
-#define aes_free mbedtls_aes_free
-#define aes_init mbedtls_aes_init
-#define aes_self_test mbedtls_aes_self_test
-#define aes_setkey_dec mbedtls_aes_setkey_dec
-#define aes_setkey_enc mbedtls_aes_setkey_enc
-#define aesni_crypt_ecb mbedtls_aesni_crypt_ecb
-#define aesni_gcm_mult mbedtls_aesni_gcm_mult
-#define aesni_inverse_key mbedtls_aesni_inverse_key
-#define aesni_setkey_enc mbedtls_aesni_setkey_enc
-#define aesni_supports mbedtls_aesni_has_support
-#define alarmed mbedtls_timing_alarmed
-#define arc4_context mbedtls_arc4_context
-#define arc4_crypt mbedtls_arc4_crypt
-#define arc4_free mbedtls_arc4_free
-#define arc4_init mbedtls_arc4_init
-#define arc4_self_test mbedtls_arc4_self_test
-#define arc4_setup mbedtls_arc4_setup
-#define asn1_bitstring mbedtls_asn1_bitstring
-#define asn1_buf mbedtls_asn1_buf
-#define asn1_find_named_data mbedtls_asn1_find_named_data
-#define asn1_free_named_data mbedtls_asn1_free_named_data
-#define asn1_free_named_data_list mbedtls_asn1_free_named_data_list
-#define asn1_get_alg mbedtls_asn1_get_alg
-#define asn1_get_alg_null mbedtls_asn1_get_alg_null
-#define asn1_get_bitstring mbedtls_asn1_get_bitstring
-#define asn1_get_bitstring_null mbedtls_asn1_get_bitstring_null
-#define asn1_get_bool mbedtls_asn1_get_bool
-#define asn1_get_int mbedtls_asn1_get_int
-#define asn1_get_len mbedtls_asn1_get_len
-#define asn1_get_mpi mbedtls_asn1_get_mpi
-#define asn1_get_sequence_of mbedtls_asn1_get_sequence_of
-#define asn1_get_tag mbedtls_asn1_get_tag
-#define asn1_named_data mbedtls_asn1_named_data
-#define asn1_sequence mbedtls_asn1_sequence
-#define asn1_store_named_data mbedtls_asn1_store_named_data
-#define asn1_write_algorithm_identifier mbedtls_asn1_write_algorithm_identifier
-#define asn1_write_bitstring mbedtls_asn1_write_bitstring
-#define asn1_write_bool mbedtls_asn1_write_bool
-#define asn1_write_ia5_string mbedtls_asn1_write_ia5_string
-#define asn1_write_int mbedtls_asn1_write_int
-#define asn1_write_len mbedtls_asn1_write_len
-#define asn1_write_mpi mbedtls_asn1_write_mpi
-#define asn1_write_null mbedtls_asn1_write_null
-#define asn1_write_octet_string mbedtls_asn1_write_octet_string
-#define asn1_write_oid mbedtls_asn1_write_oid
-#define asn1_write_printable_string mbedtls_asn1_write_printable_string
-#define asn1_write_raw_buffer mbedtls_asn1_write_raw_buffer
-#define asn1_write_tag mbedtls_asn1_write_tag
-#define base64_decode mbedtls_base64_decode
-#define base64_encode mbedtls_base64_encode
-#define base64_self_test mbedtls_base64_self_test
-#define blowfish_context mbedtls_blowfish_context
-#define blowfish_crypt_cbc mbedtls_blowfish_crypt_cbc
-#define blowfish_crypt_cfb64 mbedtls_blowfish_crypt_cfb64
-#define blowfish_crypt_ctr mbedtls_blowfish_crypt_ctr
-#define blowfish_crypt_ecb mbedtls_blowfish_crypt_ecb
-#define blowfish_free mbedtls_blowfish_free
-#define blowfish_init mbedtls_blowfish_init
-#define blowfish_setkey mbedtls_blowfish_setkey
-#define camellia_context mbedtls_camellia_context
-#define camellia_crypt_cbc mbedtls_camellia_crypt_cbc
-#define camellia_crypt_cfb128 mbedtls_camellia_crypt_cfb128
-#define camellia_crypt_ctr mbedtls_camellia_crypt_ctr
-#define camellia_crypt_ecb mbedtls_camellia_crypt_ecb
-#define camellia_free mbedtls_camellia_free
-#define camellia_init mbedtls_camellia_init
-#define camellia_self_test mbedtls_camellia_self_test
-#define camellia_setkey_dec mbedtls_camellia_setkey_dec
-#define camellia_setkey_enc mbedtls_camellia_setkey_enc
-#define ccm_auth_decrypt mbedtls_ccm_auth_decrypt
-#define ccm_context mbedtls_ccm_context
-#define ccm_encrypt_and_tag mbedtls_ccm_encrypt_and_tag
-#define ccm_free mbedtls_ccm_free
-#define ccm_init mbedtls_ccm_init
-#define ccm_self_test mbedtls_ccm_self_test
-#define cipher_auth_decrypt mbedtls_cipher_auth_decrypt
-#define cipher_auth_encrypt mbedtls_cipher_auth_encrypt
-#define cipher_base_t mbedtls_cipher_base_t
-#define cipher_check_tag mbedtls_cipher_check_tag
-#define cipher_context_t mbedtls_cipher_context_t
-#define cipher_crypt mbedtls_cipher_crypt
-#define cipher_definition_t mbedtls_cipher_definition_t
-#define cipher_definitions mbedtls_cipher_definitions
-#define cipher_finish mbedtls_cipher_finish
-#define cipher_free mbedtls_cipher_free
-#define cipher_get_block_size mbedtls_cipher_get_block_size
-#define cipher_get_cipher_mode mbedtls_cipher_get_cipher_mode
-#define cipher_get_iv_size mbedtls_cipher_get_iv_size
-#define cipher_get_key_size mbedtls_cipher_get_key_bitlen
-#define cipher_get_name mbedtls_cipher_get_name
-#define cipher_get_operation mbedtls_cipher_get_operation
-#define cipher_get_type mbedtls_cipher_get_type
-#define cipher_id_t mbedtls_cipher_id_t
-#define cipher_info_from_string mbedtls_cipher_info_from_string
-#define cipher_info_from_type mbedtls_cipher_info_from_type
-#define cipher_info_from_values mbedtls_cipher_info_from_values
-#define cipher_info_t mbedtls_cipher_info_t
-#define cipher_init mbedtls_cipher_init
-#define cipher_init_ctx mbedtls_cipher_setup
-#define cipher_list mbedtls_cipher_list
-#define cipher_mode_t mbedtls_cipher_mode_t
-#define cipher_padding_t mbedtls_cipher_padding_t
-#define cipher_reset mbedtls_cipher_reset
-#define cipher_set_iv mbedtls_cipher_set_iv
-#define cipher_set_padding_mode mbedtls_cipher_set_padding_mode
-#define cipher_setkey mbedtls_cipher_setkey
-#define cipher_type_t mbedtls_cipher_type_t
-#define cipher_update mbedtls_cipher_update
-#define cipher_update_ad mbedtls_cipher_update_ad
-#define cipher_write_tag mbedtls_cipher_write_tag
-#define ctr_drbg_context mbedtls_ctr_drbg_context
-#define ctr_drbg_free mbedtls_ctr_drbg_free
-#define ctr_drbg_init mbedtls_ctr_drbg_init
-#define ctr_drbg_random mbedtls_ctr_drbg_random
-#define ctr_drbg_random_with_add mbedtls_ctr_drbg_random_with_add
-#define ctr_drbg_reseed mbedtls_ctr_drbg_reseed
-#define ctr_drbg_self_test mbedtls_ctr_drbg_self_test
-#define ctr_drbg_set_entropy_len mbedtls_ctr_drbg_set_entropy_len
-#define ctr_drbg_set_prediction_resistance mbedtls_ctr_drbg_set_prediction_resistance
-#define ctr_drbg_set_reseed_interval mbedtls_ctr_drbg_set_reseed_interval
-#define ctr_drbg_update mbedtls_ctr_drbg_update
-#define ctr_drbg_update_seed_file mbedtls_ctr_drbg_update_seed_file
-#define ctr_drbg_write_seed_file mbedtls_ctr_drbg_write_seed_file
-#define debug_print_buf mbedtls_debug_print_buf
-#define debug_print_crt mbedtls_debug_print_crt
-#define debug_print_ecp mbedtls_debug_print_ecp
-#define debug_print_mpi mbedtls_debug_print_mpi
-#define debug_print_msg mbedtls_debug_print_msg
-#define debug_print_ret mbedtls_debug_print_ret
-#define debug_set_threshold mbedtls_debug_set_threshold
-#define des3_context mbedtls_des3_context
-#define des3_crypt_cbc mbedtls_des3_crypt_cbc
-#define des3_crypt_ecb mbedtls_des3_crypt_ecb
-#define des3_free mbedtls_des3_free
-#define des3_init mbedtls_des3_init
-#define des3_set2key_dec mbedtls_des3_set2key_dec
-#define des3_set2key_enc mbedtls_des3_set2key_enc
-#define des3_set3key_dec mbedtls_des3_set3key_dec
-#define des3_set3key_enc mbedtls_des3_set3key_enc
-#define des_context mbedtls_des_context
-#define des_crypt_cbc mbedtls_des_crypt_cbc
-#define des_crypt_ecb mbedtls_des_crypt_ecb
-#define des_free mbedtls_des_free
-#define des_init mbedtls_des_init
-#define des_key_check_key_parity mbedtls_des_key_check_key_parity
-#define des_key_check_weak mbedtls_des_key_check_weak
-#define des_key_set_parity mbedtls_des_key_set_parity
-#define des_self_test mbedtls_des_self_test
-#define des_setkey_dec mbedtls_des_setkey_dec
-#define des_setkey_enc mbedtls_des_setkey_enc
-#define dhm_calc_secret mbedtls_dhm_calc_secret
-#define dhm_context mbedtls_dhm_context
-#define dhm_free mbedtls_dhm_free
-#define dhm_init mbedtls_dhm_init
-#define dhm_make_params mbedtls_dhm_make_params
-#define dhm_make_public mbedtls_dhm_make_public
-#define dhm_parse_dhm mbedtls_dhm_parse_dhm
-#define dhm_parse_dhmfile mbedtls_dhm_parse_dhmfile
-#define dhm_read_params mbedtls_dhm_read_params
-#define dhm_read_public mbedtls_dhm_read_public
-#define dhm_self_test mbedtls_dhm_self_test
-#define ecdh_calc_secret mbedtls_ecdh_calc_secret
-#define ecdh_compute_shared mbedtls_ecdh_compute_shared
-#define ecdh_context mbedtls_ecdh_context
-#define ecdh_free mbedtls_ecdh_free
-#define ecdh_gen_public mbedtls_ecdh_gen_public
-#define ecdh_get_params mbedtls_ecdh_get_params
-#define ecdh_init mbedtls_ecdh_init
-#define ecdh_make_params mbedtls_ecdh_make_params
-#define ecdh_make_public mbedtls_ecdh_make_public
-#define ecdh_read_params mbedtls_ecdh_read_params
-#define ecdh_read_public mbedtls_ecdh_read_public
-#define ecdh_side mbedtls_ecdh_side
-#define ecdsa_context mbedtls_ecdsa_context
-#define ecdsa_free mbedtls_ecdsa_free
-#define ecdsa_from_keypair mbedtls_ecdsa_from_keypair
-#define ecdsa_genkey mbedtls_ecdsa_genkey
-#define ecdsa_info mbedtls_ecdsa_info
-#define ecdsa_init mbedtls_ecdsa_init
-#define ecdsa_read_signature mbedtls_ecdsa_read_signature
-#define ecdsa_sign mbedtls_ecdsa_sign
-#define ecdsa_sign_det mbedtls_ecdsa_sign_det
-#define ecdsa_verify mbedtls_ecdsa_verify
-#define ecdsa_write_signature mbedtls_ecdsa_write_signature
-#define ecdsa_write_signature_det mbedtls_ecdsa_write_signature_det
-#define eckey_info mbedtls_eckey_info
-#define eckeydh_info mbedtls_eckeydh_info
-#define ecp_check_privkey mbedtls_ecp_check_privkey
-#define ecp_check_pub_priv mbedtls_ecp_check_pub_priv
-#define ecp_check_pubkey mbedtls_ecp_check_pubkey
-#define ecp_copy mbedtls_ecp_copy
-#define ecp_curve_info mbedtls_ecp_curve_info
-#define ecp_curve_info_from_grp_id mbedtls_ecp_curve_info_from_grp_id
-#define ecp_curve_info_from_name mbedtls_ecp_curve_info_from_name
-#define ecp_curve_info_from_tls_id mbedtls_ecp_curve_info_from_tls_id
-#define ecp_curve_list mbedtls_ecp_curve_list
-#define ecp_gen_key mbedtls_ecp_gen_key
-#define ecp_gen_keypair mbedtls_ecp_gen_keypair
-#define ecp_group mbedtls_ecp_group
-#define ecp_group_copy mbedtls_ecp_group_copy
-#define ecp_group_free mbedtls_ecp_group_free
-#define ecp_group_id mbedtls_ecp_group_id
-#define ecp_group_init mbedtls_ecp_group_init
-#define ecp_grp_id_list mbedtls_ecp_grp_id_list
-#define ecp_is_zero mbedtls_ecp_is_zero
-#define ecp_keypair mbedtls_ecp_keypair
-#define ecp_keypair_free mbedtls_ecp_keypair_free
-#define ecp_keypair_init mbedtls_ecp_keypair_init
-#define ecp_mul mbedtls_ecp_mul
-#define ecp_point mbedtls_ecp_point
-#define ecp_point_free mbedtls_ecp_point_free
-#define ecp_point_init mbedtls_ecp_point_init
-#define ecp_point_read_binary mbedtls_ecp_point_read_binary
-#define ecp_point_read_string mbedtls_ecp_point_read_string
-#define ecp_point_write_binary mbedtls_ecp_point_write_binary
-#define ecp_self_test mbedtls_ecp_self_test
-#define ecp_set_zero mbedtls_ecp_set_zero
-#define ecp_tls_read_group mbedtls_ecp_tls_read_group
-#define ecp_tls_read_point mbedtls_ecp_tls_read_point
-#define ecp_tls_write_group mbedtls_ecp_tls_write_group
-#define ecp_tls_write_point mbedtls_ecp_tls_write_point
-#define ecp_use_known_dp mbedtls_ecp_group_load
-#define entropy_add_source mbedtls_entropy_add_source
-#define entropy_context mbedtls_entropy_context
-#define entropy_free mbedtls_entropy_free
-#define entropy_func mbedtls_entropy_func
-#define entropy_gather mbedtls_entropy_gather
-#define entropy_init mbedtls_entropy_init
-#define entropy_self_test mbedtls_entropy_self_test
-#define entropy_update_manual mbedtls_entropy_update_manual
-#define entropy_update_seed_file mbedtls_entropy_update_seed_file
-#define entropy_write_seed_file mbedtls_entropy_write_seed_file
-#define error_strerror mbedtls_strerror
-#define f_source_ptr mbedtls_entropy_f_source_ptr
-#define gcm_auth_decrypt mbedtls_gcm_auth_decrypt
-#define gcm_context mbedtls_gcm_context
-#define gcm_crypt_and_tag mbedtls_gcm_crypt_and_tag
-#define gcm_finish mbedtls_gcm_finish
-#define gcm_free mbedtls_gcm_free
-#define gcm_init mbedtls_gcm_init
-#define gcm_self_test mbedtls_gcm_self_test
-#define gcm_starts mbedtls_gcm_starts
-#define gcm_update mbedtls_gcm_update
-#define get_timer mbedtls_timing_get_timer
-#define hardclock mbedtls_timing_hardclock
-#define hardclock_poll mbedtls_hardclock_poll
-#define havege_free mbedtls_havege_free
-#define havege_init mbedtls_havege_init
-#define havege_poll mbedtls_havege_poll
-#define havege_random mbedtls_havege_random
-#define havege_state mbedtls_havege_state
-#define hmac_drbg_context mbedtls_hmac_drbg_context
-#define hmac_drbg_free mbedtls_hmac_drbg_free
-#define hmac_drbg_init mbedtls_hmac_drbg_init
-#define hmac_drbg_random mbedtls_hmac_drbg_random
-#define hmac_drbg_random_with_add mbedtls_hmac_drbg_random_with_add
-#define hmac_drbg_reseed mbedtls_hmac_drbg_reseed
-#define hmac_drbg_self_test mbedtls_hmac_drbg_self_test
-#define hmac_drbg_set_entropy_len mbedtls_hmac_drbg_set_entropy_len
-#define hmac_drbg_set_prediction_resistance mbedtls_hmac_drbg_set_prediction_resistance
-#define hmac_drbg_set_reseed_interval mbedtls_hmac_drbg_set_reseed_interval
-#define hmac_drbg_update mbedtls_hmac_drbg_update
-#define hmac_drbg_update_seed_file mbedtls_hmac_drbg_update_seed_file
-#define hmac_drbg_write_seed_file mbedtls_hmac_drbg_write_seed_file
-#define hr_time mbedtls_timing_hr_time
-#define key_exchange_type_t mbedtls_key_exchange_type_t
-#define md mbedtls_md
-#define md2 mbedtls_md2
-#define md2_context mbedtls_md2_context
-#define md2_finish mbedtls_md2_finish
-#define md2_free mbedtls_md2_free
-#define md2_info mbedtls_md2_info
-#define md2_init mbedtls_md2_init
-#define md2_process mbedtls_md2_process
-#define md2_self_test mbedtls_md2_self_test
-#define md2_starts mbedtls_md2_starts
-#define md2_update mbedtls_md2_update
-#define md4 mbedtls_md4
-#define md4_context mbedtls_md4_context
-#define md4_finish mbedtls_md4_finish
-#define md4_free mbedtls_md4_free
-#define md4_info mbedtls_md4_info
-#define md4_init mbedtls_md4_init
-#define md4_process mbedtls_md4_process
-#define md4_self_test mbedtls_md4_self_test
-#define md4_starts mbedtls_md4_starts
-#define md4_update mbedtls_md4_update
-#define md5 mbedtls_md5
-#define md5_context mbedtls_md5_context
-#define md5_finish mbedtls_md5_finish
-#define md5_free mbedtls_md5_free
-#define md5_info mbedtls_md5_info
-#define md5_init mbedtls_md5_init
-#define md5_process mbedtls_md5_process
-#define md5_self_test mbedtls_md5_self_test
-#define md5_starts mbedtls_md5_starts
-#define md5_update mbedtls_md5_update
-#define md_context_t mbedtls_md_context_t
-#define md_file mbedtls_md_file
-#define md_finish mbedtls_md_finish
-#define md_free mbedtls_md_free
-#define md_get_name mbedtls_md_get_name
-#define md_get_size mbedtls_md_get_size
-#define md_get_type mbedtls_md_get_type
-#define md_hmac mbedtls_md_hmac
-#define md_hmac_finish mbedtls_md_hmac_finish
-#define md_hmac_reset mbedtls_md_hmac_reset
-#define md_hmac_starts mbedtls_md_hmac_starts
-#define md_hmac_update mbedtls_md_hmac_update
-#define md_info_from_string mbedtls_md_info_from_string
-#define md_info_from_type mbedtls_md_info_from_type
-#define md_info_t mbedtls_md_info_t
-#define md_init mbedtls_md_init
-#define md_init_ctx mbedtls_md_init_ctx
-#define md_list mbedtls_md_list
-#define md_process mbedtls_md_process
-#define md_starts mbedtls_md_starts
-#define md_type_t mbedtls_md_type_t
-#define md_update mbedtls_md_update
-#define memory_buffer_alloc_cur_get mbedtls_memory_buffer_alloc_cur_get
-#define memory_buffer_alloc_free mbedtls_memory_buffer_alloc_free
-#define memory_buffer_alloc_init mbedtls_memory_buffer_alloc_init
-#define memory_buffer_alloc_max_get mbedtls_memory_buffer_alloc_max_get
-#define memory_buffer_alloc_max_reset mbedtls_memory_buffer_alloc_max_reset
-#define memory_buffer_alloc_self_test mbedtls_memory_buffer_alloc_self_test
-#define memory_buffer_alloc_status mbedtls_memory_buffer_alloc_status
-#define memory_buffer_alloc_verify mbedtls_memory_buffer_alloc_verify
-#define memory_buffer_set_verify mbedtls_memory_buffer_set_verify
-#define mpi mbedtls_mpi
-#define mpi_add_abs mbedtls_mpi_add_abs
-#define mpi_add_int mbedtls_mpi_add_int
-#define mpi_add_mpi mbedtls_mpi_add_mpi
-#define mpi_cmp_abs mbedtls_mpi_cmp_abs
-#define mpi_cmp_int mbedtls_mpi_cmp_int
-#define mpi_cmp_mpi mbedtls_mpi_cmp_mpi
-#define mpi_copy mbedtls_mpi_copy
-#define mpi_div_int mbedtls_mpi_div_int
-#define mpi_div_mpi mbedtls_mpi_div_mpi
-#define mpi_exp_mod mbedtls_mpi_exp_mod
-#define mpi_fill_random mbedtls_mpi_fill_random
-#define mpi_free mbedtls_mpi_free
-#define mpi_gcd mbedtls_mpi_gcd
-#define mpi_gen_prime mbedtls_mpi_gen_prime
-#define mpi_get_bit mbedtls_mpi_get_bit
-#define mpi_grow mbedtls_mpi_grow
-#define mpi_init mbedtls_mpi_init
-#define mpi_inv_mod mbedtls_mpi_inv_mod
-#define mpi_is_prime mbedtls_mpi_is_prime
-#define mpi_lsb mbedtls_mpi_lsb
-#define mpi_lset mbedtls_mpi_lset
-#define mpi_mod_int mbedtls_mpi_mod_int
-#define mpi_mod_mpi mbedtls_mpi_mod_mpi
-#define mpi_msb mbedtls_mpi_bitlen
-#define mpi_mul_int mbedtls_mpi_mul_int
-#define mpi_mul_mpi mbedtls_mpi_mul_mpi
-#define mpi_read_binary mbedtls_mpi_read_binary
-#define mpi_read_file mbedtls_mpi_read_file
-#define mpi_read_string mbedtls_mpi_read_string
-#define mpi_safe_cond_assign mbedtls_mpi_safe_cond_assign
-#define mpi_safe_cond_swap mbedtls_mpi_safe_cond_swap
-#define mpi_self_test mbedtls_mpi_self_test
-#define mpi_set_bit mbedtls_mpi_set_bit
-#define mpi_shift_l mbedtls_mpi_shift_l
-#define mpi_shift_r mbedtls_mpi_shift_r
-#define mpi_shrink mbedtls_mpi_shrink
-#define mpi_size mbedtls_mpi_size
-#define mpi_sub_abs mbedtls_mpi_sub_abs
-#define mpi_sub_int mbedtls_mpi_sub_int
-#define mpi_sub_mpi mbedtls_mpi_sub_mpi
-#define mpi_swap mbedtls_mpi_swap
-#define mpi_write_binary mbedtls_mpi_write_binary
-#define mpi_write_file mbedtls_mpi_write_file
-#define mpi_write_string mbedtls_mpi_write_string
-#define net_accept mbedtls_net_accept
-#define net_bind mbedtls_net_bind
-#define net_close mbedtls_net_free
-#define net_connect mbedtls_net_connect
-#define net_recv mbedtls_net_recv
-#define net_recv_timeout mbedtls_net_recv_timeout
-#define net_send mbedtls_net_send
-#define net_set_block mbedtls_net_set_block
-#define net_set_nonblock mbedtls_net_set_nonblock
-#define net_usleep mbedtls_net_usleep
-#define oid_descriptor_t mbedtls_oid_descriptor_t
-#define oid_get_attr_short_name mbedtls_oid_get_attr_short_name
-#define oid_get_cipher_alg mbedtls_oid_get_cipher_alg
-#define oid_get_ec_grp mbedtls_oid_get_ec_grp
-#define oid_get_extended_key_usage mbedtls_oid_get_extended_key_usage
-#define oid_get_md_alg mbedtls_oid_get_md_alg
-#define oid_get_numeric_string mbedtls_oid_get_numeric_string
-#define oid_get_oid_by_ec_grp mbedtls_oid_get_oid_by_ec_grp
-#define oid_get_oid_by_md mbedtls_oid_get_oid_by_md
-#define oid_get_oid_by_pk_alg mbedtls_oid_get_oid_by_pk_alg
-#define oid_get_oid_by_sig_alg mbedtls_oid_get_oid_by_sig_alg
-#define oid_get_pk_alg mbedtls_oid_get_pk_alg
-#define oid_get_pkcs12_pbe_alg mbedtls_oid_get_pkcs12_pbe_alg
-#define oid_get_sig_alg mbedtls_oid_get_sig_alg
-#define oid_get_sig_alg_desc mbedtls_oid_get_sig_alg_desc
-#define oid_get_x509_ext_type mbedtls_oid_get_x509_ext_type
-#define operation_t mbedtls_operation_t
-#define padlock_supports mbedtls_padlock_has_support
-#define padlock_xcryptcbc mbedtls_padlock_xcryptcbc
-#define padlock_xcryptecb mbedtls_padlock_xcryptecb
-#define pem_context mbedtls_pem_context
-#define pem_free mbedtls_pem_free
-#define pem_init mbedtls_pem_init
-#define pem_read_buffer mbedtls_pem_read_buffer
-#define pem_write_buffer mbedtls_pem_write_buffer
-#define pk_can_do mbedtls_pk_can_do
-#define pk_check_pair mbedtls_pk_check_pair
-#define pk_context mbedtls_pk_context
-#define pk_debug mbedtls_pk_debug
-#define pk_debug_item mbedtls_pk_debug_item
-#define pk_debug_type mbedtls_pk_debug_type
-#define pk_decrypt mbedtls_pk_decrypt
-#define pk_ec mbedtls_pk_ec
-#define pk_encrypt mbedtls_pk_encrypt
-#define pk_free mbedtls_pk_free
-#define pk_get_len mbedtls_pk_get_len
-#define pk_get_name mbedtls_pk_get_name
-#define pk_get_size mbedtls_pk_get_bitlen
-#define pk_get_type mbedtls_pk_get_type
-#define pk_info_from_type mbedtls_pk_info_from_type
-#define pk_info_t mbedtls_pk_info_t
-#define pk_init mbedtls_pk_init
-#define pk_init_ctx mbedtls_pk_setup
-#define pk_init_ctx_rsa_alt mbedtls_pk_setup_rsa_alt
-#define pk_load_file mbedtls_pk_load_file
-#define pk_parse_key mbedtls_pk_parse_key
-#define pk_parse_keyfile mbedtls_pk_parse_keyfile
-#define pk_parse_public_key mbedtls_pk_parse_public_key
-#define pk_parse_public_keyfile mbedtls_pk_parse_public_keyfile
-#define pk_parse_subpubkey mbedtls_pk_parse_subpubkey
-#define pk_rsa mbedtls_pk_rsa
-#define pk_rsa_alt_decrypt_func mbedtls_pk_rsa_alt_decrypt_func
-#define pk_rsa_alt_key_len_func mbedtls_pk_rsa_alt_key_len_func
-#define pk_rsa_alt_sign_func mbedtls_pk_rsa_alt_sign_func
-#define pk_rsassa_pss_options mbedtls_pk_rsassa_pss_options
-#define pk_sign mbedtls_pk_sign
-#define pk_type_t mbedtls_pk_type_t
-#define pk_verify mbedtls_pk_verify
-#define pk_verify_ext mbedtls_pk_verify_ext
-#define pk_write_key_der mbedtls_pk_write_key_der
-#define pk_write_key_pem mbedtls_pk_write_key_pem
-#define pk_write_pubkey mbedtls_pk_write_pubkey
-#define pk_write_pubkey_der mbedtls_pk_write_pubkey_der
-#define pk_write_pubkey_pem mbedtls_pk_write_pubkey_pem
-#define pkcs11_context mbedtls_pkcs11_context
-#define pkcs11_decrypt mbedtls_pkcs11_decrypt
-#define pkcs11_priv_key_free mbedtls_pkcs11_priv_key_free
-#define pkcs11_priv_key_init mbedtls_pkcs11_priv_key_bind
-#define pkcs11_sign mbedtls_pkcs11_sign
-#define pkcs11_x509_cert_init mbedtls_pkcs11_x509_cert_bind
-#define pkcs12_derivation mbedtls_pkcs12_derivation
-#define pkcs12_pbe mbedtls_pkcs12_pbe
-#define pkcs12_pbe_sha1_rc4_128 mbedtls_pkcs12_pbe_sha1_rc4_128
-#define pkcs5_pbes2 mbedtls_pkcs5_pbes2
-#define pkcs5_pbkdf2_hmac mbedtls_pkcs5_pbkdf2_hmac
-#define pkcs5_self_test mbedtls_pkcs5_self_test
-#define platform_entropy_poll mbedtls_platform_entropy_poll
-#define platform_set_exit mbedtls_platform_set_exit
-#define platform_set_fprintf mbedtls_platform_set_fprintf
-#define platform_set_printf mbedtls_platform_set_printf
-#define platform_set_snprintf mbedtls_platform_set_snprintf
-#define polarssl_exit mbedtls_exit
-#define polarssl_fprintf mbedtls_fprintf
-#define polarssl_free mbedtls_free
-#define polarssl_mutex_free mbedtls_mutex_free
-#define polarssl_mutex_init mbedtls_mutex_init
-#define polarssl_mutex_lock mbedtls_mutex_lock
-#define polarssl_mutex_unlock mbedtls_mutex_unlock
-#define polarssl_printf mbedtls_printf
-#define polarssl_snprintf mbedtls_snprintf
-#define polarssl_strerror mbedtls_strerror
-#define ripemd160 mbedtls_ripemd160
-#define ripemd160_context mbedtls_ripemd160_context
-#define ripemd160_finish mbedtls_ripemd160_finish
-#define ripemd160_free mbedtls_ripemd160_free
-#define ripemd160_info mbedtls_ripemd160_info
-#define ripemd160_init mbedtls_ripemd160_init
-#define ripemd160_process mbedtls_ripemd160_process
-#define ripemd160_self_test mbedtls_ripemd160_self_test
-#define ripemd160_starts mbedtls_ripemd160_starts
-#define ripemd160_update mbedtls_ripemd160_update
-#define rsa_alt_context mbedtls_rsa_alt_context
-#define rsa_alt_info mbedtls_rsa_alt_info
-#define rsa_check_privkey mbedtls_rsa_check_privkey
-#define rsa_check_pub_priv mbedtls_rsa_check_pub_priv
-#define rsa_check_pubkey mbedtls_rsa_check_pubkey
-#define rsa_context mbedtls_rsa_context
-#define rsa_copy mbedtls_rsa_copy
-#define rsa_free mbedtls_rsa_free
-#define rsa_gen_key mbedtls_rsa_gen_key
-#define rsa_info mbedtls_rsa_info
-#define rsa_init mbedtls_rsa_init
-#define rsa_pkcs1_decrypt mbedtls_rsa_pkcs1_decrypt
-#define rsa_pkcs1_encrypt mbedtls_rsa_pkcs1_encrypt
-#define rsa_pkcs1_sign mbedtls_rsa_pkcs1_sign
-#define rsa_pkcs1_verify mbedtls_rsa_pkcs1_verify
-#define rsa_private mbedtls_rsa_private
-#define rsa_public mbedtls_rsa_public
-#define rsa_rsaes_oaep_decrypt mbedtls_rsa_rsaes_oaep_decrypt
-#define rsa_rsaes_oaep_encrypt mbedtls_rsa_rsaes_oaep_encrypt
-#define rsa_rsaes_pkcs1_v15_decrypt mbedtls_rsa_rsaes_pkcs1_v15_decrypt
-#define rsa_rsaes_pkcs1_v15_encrypt mbedtls_rsa_rsaes_pkcs1_v15_encrypt
-#define rsa_rsassa_pkcs1_v15_sign mbedtls_rsa_rsassa_pkcs1_v15_sign
-#define rsa_rsassa_pkcs1_v15_verify mbedtls_rsa_rsassa_pkcs1_v15_verify
-#define rsa_rsassa_pss_sign mbedtls_rsa_rsassa_pss_sign
-#define rsa_rsassa_pss_verify mbedtls_rsa_rsassa_pss_verify
-#define rsa_rsassa_pss_verify_ext mbedtls_rsa_rsassa_pss_verify_ext
-#define rsa_self_test mbedtls_rsa_self_test
-#define rsa_set_padding mbedtls_rsa_set_padding
-#define safer_memcmp mbedtls_ssl_safer_memcmp
-#define set_alarm mbedtls_set_alarm
-#define sha1 mbedtls_sha1
-#define sha1_context mbedtls_sha1_context
-#define sha1_finish mbedtls_sha1_finish
-#define sha1_free mbedtls_sha1_free
-#define sha1_info mbedtls_sha1_info
-#define sha1_init mbedtls_sha1_init
-#define sha1_process mbedtls_sha1_process
-#define sha1_self_test mbedtls_sha1_self_test
-#define sha1_starts mbedtls_sha1_starts
-#define sha1_update mbedtls_sha1_update
-#define sha224_info mbedtls_sha224_info
-#define sha256 mbedtls_sha256
-#define sha256_context mbedtls_sha256_context
-#define sha256_finish mbedtls_sha256_finish
-#define sha256_free mbedtls_sha256_free
-#define sha256_info mbedtls_sha256_info
-#define sha256_init mbedtls_sha256_init
-#define sha256_process mbedtls_sha256_process
-#define sha256_self_test mbedtls_sha256_self_test
-#define sha256_starts mbedtls_sha256_starts
-#define sha256_update mbedtls_sha256_update
-#define sha384_info mbedtls_sha384_info
-#define sha512 mbedtls_sha512
-#define sha512_context mbedtls_sha512_context
-#define sha512_finish mbedtls_sha512_finish
-#define sha512_free mbedtls_sha512_free
-#define sha512_info mbedtls_sha512_info
-#define sha512_init mbedtls_sha512_init
-#define sha512_process mbedtls_sha512_process
-#define sha512_self_test mbedtls_sha512_self_test
-#define sha512_starts mbedtls_sha512_starts
-#define sha512_update mbedtls_sha512_update
-#define source_state mbedtls_entropy_source_state
-#define ssl_cache_context mbedtls_ssl_cache_context
-#define ssl_cache_entry mbedtls_ssl_cache_entry
-#define ssl_cache_free mbedtls_ssl_cache_free
-#define ssl_cache_get mbedtls_ssl_cache_get
-#define ssl_cache_init mbedtls_ssl_cache_init
-#define ssl_cache_set mbedtls_ssl_cache_set
-#define ssl_cache_set_max_entries mbedtls_ssl_cache_set_max_entries
-#define ssl_cache_set_timeout mbedtls_ssl_cache_set_timeout
-#define ssl_check_cert_usage mbedtls_ssl_check_cert_usage
-#define ssl_ciphersuite_from_id mbedtls_ssl_ciphersuite_from_id
-#define ssl_ciphersuite_from_string mbedtls_ssl_ciphersuite_from_string
-#define ssl_ciphersuite_t mbedtls_ssl_ciphersuite_t
-#define ssl_ciphersuite_uses_ec mbedtls_ssl_ciphersuite_uses_ec
-#define ssl_ciphersuite_uses_psk mbedtls_ssl_ciphersuite_uses_psk
-#define ssl_close_notify mbedtls_ssl_close_notify
-#define ssl_context mbedtls_ssl_context
-#define ssl_cookie_check mbedtls_ssl_cookie_check
-#define ssl_cookie_check_t mbedtls_ssl_cookie_check_t
-#define ssl_cookie_ctx mbedtls_ssl_cookie_ctx
-#define ssl_cookie_free mbedtls_ssl_cookie_free
-#define ssl_cookie_init mbedtls_ssl_cookie_init
-#define ssl_cookie_set_timeout mbedtls_ssl_cookie_set_timeout
-#define ssl_cookie_setup mbedtls_ssl_cookie_setup
-#define ssl_cookie_write mbedtls_ssl_cookie_write
-#define ssl_cookie_write_t mbedtls_ssl_cookie_write_t
-#define ssl_derive_keys mbedtls_ssl_derive_keys
-#define ssl_dtls_replay_check mbedtls_ssl_dtls_replay_check
-#define ssl_dtls_replay_update mbedtls_ssl_dtls_replay_update
-#define ssl_fetch_input mbedtls_ssl_fetch_input
-#define ssl_flight_item mbedtls_ssl_flight_item
-#define ssl_flush_output mbedtls_ssl_flush_output
-#define ssl_free mbedtls_ssl_free
-#define ssl_get_alpn_protocol mbedtls_ssl_get_alpn_protocol
-#define ssl_get_bytes_avail mbedtls_ssl_get_bytes_avail
-#define ssl_get_ciphersuite mbedtls_ssl_get_ciphersuite
-#define ssl_get_ciphersuite_id mbedtls_ssl_get_ciphersuite_id
-#define ssl_get_ciphersuite_name mbedtls_ssl_get_ciphersuite_name
-#define ssl_get_ciphersuite_sig_pk_alg mbedtls_ssl_get_ciphersuite_sig_pk_alg
-#define ssl_get_peer_cert mbedtls_ssl_get_peer_cert
-#define ssl_get_record_expansion mbedtls_ssl_get_record_expansion
-#define ssl_get_session mbedtls_ssl_get_session
-#define ssl_get_verify_result mbedtls_ssl_get_verify_result
-#define ssl_get_version mbedtls_ssl_get_version
-#define ssl_handshake mbedtls_ssl_handshake
-#define ssl_handshake_client_step mbedtls_ssl_handshake_client_step
-#define ssl_handshake_free mbedtls_ssl_handshake_free
-#define ssl_handshake_params mbedtls_ssl_handshake_params
-#define ssl_handshake_server_step mbedtls_ssl_handshake_server_step
-#define ssl_handshake_step mbedtls_ssl_handshake_step
-#define ssl_handshake_wrapup mbedtls_ssl_handshake_wrapup
-#define ssl_hdr_len mbedtls_ssl_hdr_len
-#define ssl_hs_hdr_len mbedtls_ssl_hs_hdr_len
-#define ssl_hw_record_activate mbedtls_ssl_hw_record_activate
-#define ssl_hw_record_finish mbedtls_ssl_hw_record_finish
-#define ssl_hw_record_init mbedtls_ssl_hw_record_init
-#define ssl_hw_record_read mbedtls_ssl_hw_record_read
-#define ssl_hw_record_reset mbedtls_ssl_hw_record_reset
-#define ssl_hw_record_write mbedtls_ssl_hw_record_write
-#define ssl_init mbedtls_ssl_init
-#define ssl_key_cert mbedtls_ssl_key_cert
-#define ssl_legacy_renegotiation mbedtls_ssl_conf_legacy_renegotiation
-#define ssl_list_ciphersuites mbedtls_ssl_list_ciphersuites
-#define ssl_md_alg_from_hash mbedtls_ssl_md_alg_from_hash
-#define ssl_optimize_checksum mbedtls_ssl_optimize_checksum
-#define ssl_own_cert mbedtls_ssl_own_cert
-#define ssl_own_key mbedtls_ssl_own_key
-#define ssl_parse_certificate mbedtls_ssl_parse_certificate
-#define ssl_parse_change_cipher_spec mbedtls_ssl_parse_change_cipher_spec
-#define ssl_parse_finished mbedtls_ssl_parse_finished
-#define ssl_pk_alg_from_sig mbedtls_ssl_pk_alg_from_sig
-#define ssl_pkcs11_decrypt mbedtls_ssl_pkcs11_decrypt
-#define ssl_pkcs11_key_len mbedtls_ssl_pkcs11_key_len
-#define ssl_pkcs11_sign mbedtls_ssl_pkcs11_sign
-#define ssl_psk_derive_premaster mbedtls_ssl_psk_derive_premaster
-#define ssl_read mbedtls_ssl_read
-#define ssl_read_record mbedtls_ssl_read_record
-#define ssl_read_version mbedtls_ssl_read_version
-#define ssl_recv_flight_completed mbedtls_ssl_recv_flight_completed
-#define ssl_renegotiate mbedtls_ssl_renegotiate
-#define ssl_resend mbedtls_ssl_resend
-#define ssl_reset_checksum mbedtls_ssl_reset_checksum
-#define ssl_send_alert_message mbedtls_ssl_send_alert_message
-#define ssl_send_fatal_handshake_failure mbedtls_ssl_send_fatal_handshake_failure
-#define ssl_send_flight_completed mbedtls_ssl_send_flight_completed
-#define ssl_session mbedtls_ssl_session
-#define ssl_session_free mbedtls_ssl_session_free
-#define ssl_session_init mbedtls_ssl_session_init
-#define ssl_session_reset mbedtls_ssl_session_reset
-#define ssl_set_alpn_protocols mbedtls_ssl_conf_alpn_protocols
-#define ssl_set_arc4_support mbedtls_ssl_conf_arc4_support
-#define ssl_set_authmode mbedtls_ssl_conf_authmode
-#define ssl_set_bio mbedtls_ssl_set_bio
-#define ssl_set_ca_chain mbedtls_ssl_conf_ca_chain
-#define ssl_set_cbc_record_splitting mbedtls_ssl_conf_cbc_record_splitting
-#define ssl_set_ciphersuites mbedtls_ssl_conf_ciphersuites
-#define ssl_set_ciphersuites_for_version mbedtls_ssl_conf_ciphersuites_for_version
-#define ssl_set_client_transport_id mbedtls_ssl_set_client_transport_id
-#define ssl_set_curves mbedtls_ssl_conf_curves
-#define ssl_set_dbg mbedtls_ssl_conf_dbg
-#define ssl_set_dh_param mbedtls_ssl_conf_dh_param
-#define ssl_set_dh_param_ctx mbedtls_ssl_conf_dh_param_ctx
-#define ssl_set_dtls_anti_replay mbedtls_ssl_conf_dtls_anti_replay
-#define ssl_set_dtls_badmac_limit mbedtls_ssl_conf_dtls_badmac_limit
-#define ssl_set_dtls_cookies mbedtls_ssl_conf_dtls_cookies
-#define ssl_set_encrypt_then_mac mbedtls_ssl_conf_encrypt_then_mac
-#define ssl_set_endpoint mbedtls_ssl_conf_endpoint
-#define ssl_set_extended_master_secret mbedtls_ssl_conf_extended_master_secret
-#define ssl_set_fallback mbedtls_ssl_conf_fallback
-#define ssl_set_handshake_timeout mbedtls_ssl_conf_handshake_timeout
-#define ssl_set_hostname mbedtls_ssl_set_hostname
-#define ssl_set_max_frag_len mbedtls_ssl_conf_max_frag_len
-#define ssl_set_max_version mbedtls_ssl_conf_max_version
-#define ssl_set_min_version mbedtls_ssl_conf_min_version
-#define ssl_set_own_cert mbedtls_ssl_conf_own_cert
-#define ssl_set_psk mbedtls_ssl_conf_psk
-#define ssl_set_psk_cb mbedtls_ssl_conf_psk_cb
-#define ssl_set_renegotiation mbedtls_ssl_conf_renegotiation
-#define ssl_set_renegotiation_enforced mbedtls_ssl_conf_renegotiation_enforced
-#define ssl_set_renegotiation_period mbedtls_ssl_conf_renegotiation_period
-#define ssl_set_rng mbedtls_ssl_conf_rng
-#define ssl_set_session mbedtls_ssl_set_session
-#define ssl_set_session_cache mbedtls_ssl_conf_session_cache
-#define ssl_set_session_tickets mbedtls_ssl_conf_session_tickets
-#define ssl_set_sni mbedtls_ssl_conf_sni
-#define ssl_set_transport mbedtls_ssl_conf_transport
-#define ssl_set_truncated_hmac mbedtls_ssl_conf_truncated_hmac
-#define ssl_set_verify mbedtls_ssl_conf_verify
-#define ssl_sig_from_pk mbedtls_ssl_sig_from_pk
-#define ssl_states mbedtls_ssl_states
-#define ssl_transform mbedtls_ssl_transform
-#define ssl_transform_free mbedtls_ssl_transform_free
-#define ssl_write mbedtls_ssl_write
-#define ssl_write_certificate mbedtls_ssl_write_certificate
-#define ssl_write_change_cipher_spec mbedtls_ssl_write_change_cipher_spec
-#define ssl_write_finished mbedtls_ssl_write_finished
-#define ssl_write_record mbedtls_ssl_write_record
-#define ssl_write_version mbedtls_ssl_write_version
-#define supported_ciphers mbedtls_cipher_supported
-#define t_sint mbedtls_mpi_sint
-#define t_udbl mbedtls_t_udbl
-#define t_uint mbedtls_mpi_uint
-#define test_ca_crt mbedtls_test_ca_crt
-#define test_ca_crt_ec mbedtls_test_ca_crt_ec
-#define test_ca_crt_rsa mbedtls_test_ca_crt_rsa
-#define test_ca_key mbedtls_test_ca_key
-#define test_ca_key_ec mbedtls_test_ca_key_ec
-#define test_ca_key_rsa mbedtls_test_ca_key_rsa
-#define test_ca_list mbedtls_test_cas_pem
-#define test_ca_pwd mbedtls_test_ca_pwd
-#define test_ca_pwd_ec mbedtls_test_ca_pwd_ec
-#define test_ca_pwd_rsa mbedtls_test_ca_pwd_rsa
-#define test_cli_crt mbedtls_test_cli_crt
-#define test_cli_crt_ec mbedtls_test_cli_crt_ec
-#define test_cli_crt_rsa mbedtls_test_cli_crt_rsa
-#define test_cli_key mbedtls_test_cli_key
-#define test_cli_key_ec mbedtls_test_cli_key_ec
-#define test_cli_key_rsa mbedtls_test_cli_key_rsa
-#define test_srv_crt mbedtls_test_srv_crt
-#define test_srv_crt_ec mbedtls_test_srv_crt_ec
-#define test_srv_crt_rsa mbedtls_test_srv_crt_rsa
-#define test_srv_key mbedtls_test_srv_key
-#define test_srv_key_ec mbedtls_test_srv_key_ec
-#define test_srv_key_rsa mbedtls_test_srv_key_rsa
-#define threading_mutex_t mbedtls_threading_mutex_t
-#define threading_set_alt mbedtls_threading_set_alt
-#define timing_self_test mbedtls_timing_self_test
-#define version_check_feature mbedtls_version_check_feature
-#define version_get_number mbedtls_version_get_number
-#define version_get_string mbedtls_version_get_string
-#define version_get_string_full mbedtls_version_get_string_full
-#define x509_bitstring mbedtls_x509_bitstring
-#define x509_buf mbedtls_x509_buf
-#define x509_crl mbedtls_x509_crl
-#define x509_crl_entry mbedtls_x509_crl_entry
-#define x509_crl_free mbedtls_x509_crl_free
-#define x509_crl_info mbedtls_x509_crl_info
-#define x509_crl_init mbedtls_x509_crl_init
-#define x509_crl_parse mbedtls_x509_crl_parse
-#define x509_crl_parse_der mbedtls_x509_crl_parse_der
-#define x509_crl_parse_file mbedtls_x509_crl_parse_file
-#define x509_crt mbedtls_x509_crt
-#define x509_crt_check_extended_key_usage mbedtls_x509_crt_check_extended_key_usage
-#define x509_crt_check_key_usage mbedtls_x509_crt_check_key_usage
-#define x509_crt_free mbedtls_x509_crt_free
-#define x509_crt_info mbedtls_x509_crt_info
-#define x509_crt_init mbedtls_x509_crt_init
-#define x509_crt_parse mbedtls_x509_crt_parse
-#define x509_crt_parse_der mbedtls_x509_crt_parse_der
-#define x509_crt_parse_file mbedtls_x509_crt_parse_file
-#define x509_crt_parse_path mbedtls_x509_crt_parse_path
-#define x509_crt_revoked mbedtls_x509_crt_is_revoked
-#define x509_crt_verify mbedtls_x509_crt_verify
-#define x509_csr mbedtls_x509_csr
-#define x509_csr_free mbedtls_x509_csr_free
-#define x509_csr_info mbedtls_x509_csr_info
-#define x509_csr_init mbedtls_x509_csr_init
-#define x509_csr_parse mbedtls_x509_csr_parse
-#define x509_csr_parse_der mbedtls_x509_csr_parse_der
-#define x509_csr_parse_file mbedtls_x509_csr_parse_file
-#define x509_dn_gets mbedtls_x509_dn_gets
-#define x509_get_alg mbedtls_x509_get_alg
-#define x509_get_alg_null mbedtls_x509_get_alg_null
-#define x509_get_ext mbedtls_x509_get_ext
-#define x509_get_name mbedtls_x509_get_name
-#define x509_get_rsassa_pss_params mbedtls_x509_get_rsassa_pss_params
-#define x509_get_serial mbedtls_x509_get_serial
-#define x509_get_sig mbedtls_x509_get_sig
-#define x509_get_sig_alg mbedtls_x509_get_sig_alg
-#define x509_get_time mbedtls_x509_get_time
-#define x509_key_size_helper mbedtls_x509_key_size_helper
-#define x509_name mbedtls_x509_name
-#define x509_self_test mbedtls_x509_self_test
-#define x509_sequence mbedtls_x509_sequence
-#define x509_serial_gets mbedtls_x509_serial_gets
-#define x509_set_extension mbedtls_x509_set_extension
-#define x509_sig_alg_gets mbedtls_x509_sig_alg_gets
-#define x509_string_to_names mbedtls_x509_string_to_names
-#define x509_time mbedtls_x509_time
-#define x509_time_expired mbedtls_x509_time_is_past
-#define x509_time_future mbedtls_x509_time_is_future
-#define x509_write_extensions mbedtls_x509_write_extensions
-#define x509_write_names mbedtls_x509_write_names
-#define x509_write_sig mbedtls_x509_write_sig
-#define x509write_cert mbedtls_x509write_cert
-#define x509write_crt_der mbedtls_x509write_crt_der
-#define x509write_crt_free mbedtls_x509write_crt_free
-#define x509write_crt_init mbedtls_x509write_crt_init
-#define x509write_crt_pem mbedtls_x509write_crt_pem
-#define x509write_crt_set_authority_key_identifier mbedtls_x509write_crt_set_authority_key_identifier
-#define x509write_crt_set_basic_constraints mbedtls_x509write_crt_set_basic_constraints
-#define x509write_crt_set_extension mbedtls_x509write_crt_set_extension
-#define x509write_crt_set_issuer_key mbedtls_x509write_crt_set_issuer_key
-#define x509write_crt_set_issuer_name mbedtls_x509write_crt_set_issuer_name
-#define x509write_crt_set_key_usage mbedtls_x509write_crt_set_key_usage
-#define x509write_crt_set_md_alg mbedtls_x509write_crt_set_md_alg
-#define x509write_crt_set_ns_cert_type mbedtls_x509write_crt_set_ns_cert_type
-#define x509write_crt_set_serial mbedtls_x509write_crt_set_serial
-#define x509write_crt_set_subject_key mbedtls_x509write_crt_set_subject_key
-#define x509write_crt_set_subject_key_identifier mbedtls_x509write_crt_set_subject_key_identifier
-#define x509write_crt_set_subject_name mbedtls_x509write_crt_set_subject_name
-#define x509write_crt_set_validity mbedtls_x509write_crt_set_validity
-#define x509write_crt_set_version mbedtls_x509write_crt_set_version
-#define x509write_csr mbedtls_x509write_csr
-#define x509write_csr_der mbedtls_x509write_csr_der
-#define x509write_csr_free mbedtls_x509write_csr_free
-#define x509write_csr_init mbedtls_x509write_csr_init
-#define x509write_csr_pem mbedtls_x509write_csr_pem
-#define x509write_csr_set_extension mbedtls_x509write_csr_set_extension
-#define x509write_csr_set_key mbedtls_x509write_csr_set_key
-#define x509write_csr_set_key_usage mbedtls_x509write_csr_set_key_usage
-#define x509write_csr_set_md_alg mbedtls_x509write_csr_set_md_alg
-#define x509write_csr_set_ns_cert_type mbedtls_x509write_csr_set_ns_cert_type
-#define x509write_csr_set_subject_name mbedtls_x509write_csr_set_subject_name
-#define xtea_context mbedtls_xtea_context
-#define xtea_crypt_cbc mbedtls_xtea_crypt_cbc
-#define xtea_crypt_ecb mbedtls_xtea_crypt_ecb
-#define xtea_free mbedtls_xtea_free
-#define xtea_init mbedtls_xtea_init
-#define xtea_self_test mbedtls_xtea_self_test
-#define xtea_setup mbedtls_xtea_setup
-
-#endif /* compat-1.3.h */
-#endif /* MBEDTLS_DEPRECATED_REMOVED */
diff --git a/tools/sdk/include/mbedtls/mbedtls/config.h b/tools/sdk/include/mbedtls/mbedtls/config.h
deleted file mode 100644
index f7e55aef5cf..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/config.h
+++ /dev/null
@@ -1,3393 +0,0 @@
-/**
- * \file config.h
- *
- * \brief Configuration options (set of defines)
- *
- *  This set of compile-time options may be used to enable
- *  or disable features selectively, and reduce the global
- *  memory footprint.
- */
-/*
- *  Copyright (C) 2006-2018, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE)
-#define _CRT_SECURE_NO_DEPRECATE 1
-#endif
-
-/**
- * \name SECTION: System support
- *
- * This section sets system specific settings.
- * \{
- */
-
-/**
- * \def MBEDTLS_HAVE_ASM
- *
- * The compiler has support for asm().
- *
- * Requires support for asm() in compiler.
- *
- * Used in:
- *      library/aria.c
- *      library/timing.c
- *      include/mbedtls/bn_mul.h
- *
- * Required by:
- *      MBEDTLS_AESNI_C
- *      MBEDTLS_PADLOCK_C
- *
- * Comment to disable the use of assembly code.
- */
-#define MBEDTLS_HAVE_ASM
-
-/**
- * \def MBEDTLS_NO_UDBL_DIVISION
- *
- * The platform lacks support for double-width integer division (64-bit
- * division on a 32-bit platform, 128-bit division on a 64-bit platform).
- *
- * Used in:
- *      include/mbedtls/bignum.h
- *      library/bignum.c
- *
- * The bignum code uses double-width division to speed up some operations.
- * Double-width division is often implemented in software that needs to
- * be linked with the program. The presence of a double-width integer
- * type is usually detected automatically through preprocessor macros,
- * but the automatic detection cannot know whether the code needs to
- * and can be linked with an implementation of division for that type.
- * By default division is assumed to be usable if the type is present.
- * Uncomment this option to prevent the use of double-width division.
- *
- * Note that division for the native integer type is always required.
- * Furthermore, a 64-bit type is always required even on a 32-bit
- * platform, but it need not support multiplication or division. In some
- * cases it is also desirable to disable some double-width operations. For
- * example, if double-width division is implemented in software, disabling
- * it can reduce code size in some embedded targets.
- */
-//#define MBEDTLS_NO_UDBL_DIVISION
-
-/**
- * \def MBEDTLS_NO_64BIT_MULTIPLICATION
- *
- * The platform lacks support for 32x32 -> 64-bit multiplication.
- *
- * Used in:
- *      library/poly1305.c
- *
- * Some parts of the library may use multiplication of two unsigned 32-bit
- * operands with a 64-bit result in order to speed up computations. On some
- * platforms, this is not available in hardware and has to be implemented in
- * software, usually in a library provided by the toolchain.
- *
- * Sometimes it is not desirable to have to link to that library. This option
- * removes the dependency of that library on platforms that lack a hardware
- * 64-bit multiplier by embedding a software implementation in Mbed TLS.
- *
- * Note that depending on the compiler, this may decrease performance compared
- * to using the library function provided by the toolchain.
- */
-//#define MBEDTLS_NO_64BIT_MULTIPLICATION
-
-/**
- * \def MBEDTLS_HAVE_SSE2
- *
- * CPU supports SSE2 instruction set.
- *
- * Uncomment if the CPU supports SSE2 (IA-32 specific).
- */
-//#define MBEDTLS_HAVE_SSE2
-
-/**
- * \def MBEDTLS_HAVE_TIME
- *
- * System has time.h and time().
- * The time does not need to be correct, only time differences are used,
- * by contrast with MBEDTLS_HAVE_TIME_DATE
- *
- * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT,
- * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and
- * MBEDTLS_PLATFORM_STD_TIME.
- *
- * Comment if your system does not support time functions
- */
-#define MBEDTLS_HAVE_TIME
-
-/**
- * \def MBEDTLS_HAVE_TIME_DATE
- *
- * System has time.h, time(), and an implementation for
- * mbedtls_platform_gmtime_r() (see below).
- * The time needs to be correct (not necessarily very accurate, but at least
- * the date should be correct). This is used to verify the validity period of
- * X.509 certificates.
- *
- * Comment if your system does not have a correct clock.
- *
- * \note mbedtls_platform_gmtime_r() is an abstraction in platform_util.h that
- * behaves similarly to the gmtime_r() function from the C standard. Refer to
- * the documentation for mbedtls_platform_gmtime_r() for more information.
- *
- * \note It is possible to configure an implementation for
- * mbedtls_platform_gmtime_r() at compile-time by using the macro
- * MBEDTLS_PLATFORM_GMTIME_R_ALT.
- */
-#define MBEDTLS_HAVE_TIME_DATE
-
-/**
- * \def MBEDTLS_PLATFORM_MEMORY
- *
- * Enable the memory allocation layer.
- *
- * By default mbed TLS uses the system-provided calloc() and free().
- * This allows different allocators (self-implemented or provided) to be
- * provided to the platform abstraction layer.
- *
- * Enabling MBEDTLS_PLATFORM_MEMORY without the
- * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide
- * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and
- * free() function pointer at runtime.
- *
- * Enabling MBEDTLS_PLATFORM_MEMORY and specifying
- * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the
- * alternate function at compile time.
- *
- * Requires: MBEDTLS_PLATFORM_C
- *
- * Enable this layer to allow use of alternative memory allocators.
- */
-//#define MBEDTLS_PLATFORM_MEMORY
-
-/**
- * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
- *
- * Do not assign standard functions in the platform layer (e.g. calloc() to
- * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF)
- *
- * This makes sure there are no linking errors on platforms that do not support
- * these functions. You will HAVE to provide alternatives, either at runtime
- * via the platform_set_xxx() functions or at compile time by setting
- * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a
- * MBEDTLS_PLATFORM_XXX_MACRO.
- *
- * Requires: MBEDTLS_PLATFORM_C
- *
- * Uncomment to prevent default assignment of standard functions in the
- * platform layer.
- */
-//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-
-/**
- * \def MBEDTLS_PLATFORM_EXIT_ALT
- *
- * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the
- * function in the platform abstraction layer.
- *
- * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will
- * provide a function "mbedtls_platform_set_printf()" that allows you to set an
- * alternative printf function pointer.
- *
- * All these define require MBEDTLS_PLATFORM_C to be defined!
- *
- * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows;
- * it will be enabled automatically by check_config.h
- *
- * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as
- * MBEDTLS_PLATFORM_XXX_MACRO!
- *
- * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME
- *
- * Uncomment a macro to enable alternate implementation of specific base
- * platform function
- */
-//#define MBEDTLS_PLATFORM_EXIT_ALT
-//#define MBEDTLS_PLATFORM_TIME_ALT
-//#define MBEDTLS_PLATFORM_FPRINTF_ALT
-//#define MBEDTLS_PLATFORM_PRINTF_ALT
-//#define MBEDTLS_PLATFORM_SNPRINTF_ALT
-//#define MBEDTLS_PLATFORM_NV_SEED_ALT
-//#define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT
-
-/**
- * \def MBEDTLS_DEPRECATED_WARNING
- *
- * Mark deprecated functions so that they generate a warning if used.
- * Functions deprecated in one version will usually be removed in the next
- * version. You can enable this to help you prepare the transition to a new
- * major version by making sure your code is not using these functions.
- *
- * This only works with GCC and Clang. With other compilers, you may want to
- * use MBEDTLS_DEPRECATED_REMOVED
- *
- * Uncomment to get warnings on using deprecated functions.
- */
-//#define MBEDTLS_DEPRECATED_WARNING
-
-/**
- * \def MBEDTLS_DEPRECATED_REMOVED
- *
- * Remove deprecated functions so that they generate an error if used.
- * Functions deprecated in one version will usually be removed in the next
- * version. You can enable this to help you prepare the transition to a new
- * major version by making sure your code is not using these functions.
- *
- * Uncomment to get errors on using deprecated functions.
- */
-//#define MBEDTLS_DEPRECATED_REMOVED
-
-/**
- * \def MBEDTLS_CHECK_PARAMS
- *
- * This configuration option controls whether the library validates more of
- * the parameters passed to it.
- *
- * When this flag is not defined, the library only attempts to validate an
- * input parameter if: (1) they may come from the outside world (such as the
- * network, the filesystem, etc.) or (2) not validating them could result in
- * internal memory errors such as overflowing a buffer controlled by the
- * library. On the other hand, it doesn't attempt to validate parameters whose
- * values are fully controlled by the application (such as pointers).
- *
- * When this flag is defined, the library additionally attempts to validate
- * parameters that are fully controlled by the application, and should always
- * be valid if the application code is fully correct and trusted.
- *
- * For example, when a function accepts as input a pointer to a buffer that may
- * contain untrusted data, and its documentation mentions that this pointer
- * must not be NULL:
- * - The pointer is checked to be non-NULL only if this option is enabled.
- * - The content of the buffer is always validated.
- *
- * When this flag is defined, if a library function receives a parameter that
- * is invalid:
- * 1. The function will invoke the macro MBEDTLS_PARAM_FAILED().
- * 2. If MBEDTLS_PARAM_FAILED() did not terminate the program, the function
- *   will immediately return. If the function returns an Mbed TLS error code,
- *   the error code in this case is MBEDTLS_ERR_xxx_BAD_INPUT_DATA.
- *
- * When defining this flag, you also need to arrange a definition for
- * MBEDTLS_PARAM_FAILED(). You can do this by any of the following methods:
- * - By default, the library defines MBEDTLS_PARAM_FAILED() to call a
- *   function mbedtls_param_failed(), but the library does not define this
- *   function. If you do not make any other arrangements, you must provide
- *   the function mbedtls_param_failed() in your application.
- *   See `platform_util.h` for its prototype.
- * - If you enable the macro #MBEDTLS_CHECK_PARAMS_ASSERT, then the
- *   library defines #MBEDTLS_PARAM_FAILED(\c cond) to be `assert(cond)`.
- *   You can still supply an alternative definition of
- *   MBEDTLS_PARAM_FAILED(), which may call `assert`.
- * - If you define a macro MBEDTLS_PARAM_FAILED() before including `config.h`
- *   or you uncomment the definition of MBEDTLS_PARAM_FAILED() in `config.h`,
- *   the library will call the macro that you defined and will not supply
- *   its own version. Note that if MBEDTLS_PARAM_FAILED() calls `assert`,
- *   you need to enable #MBEDTLS_CHECK_PARAMS_ASSERT so that library source
- *   files include `<assert.h>`.
- *
- * Uncomment to enable validation of application-controlled parameters.
- */
-//#define MBEDTLS_CHECK_PARAMS
-
-/**
- * \def MBEDTLS_CHECK_PARAMS_ASSERT
- *
- * Allow MBEDTLS_PARAM_FAILED() to call `assert`, and make it default to
- * `assert`. This macro is only used if #MBEDTLS_CHECK_PARAMS is defined.
- *
- * If this macro is not defined, then MBEDTLS_PARAM_FAILED() defaults to
- * calling a function mbedtls_param_failed(). See the documentation of
- * #MBEDTLS_CHECK_PARAMS for details.
- *
- * Uncomment to allow MBEDTLS_PARAM_FAILED() to call `assert`.
- */
-//#define MBEDTLS_CHECK_PARAMS_ASSERT
-
-/* \} name SECTION: System support */
-
-/**
- * \name SECTION: mbed TLS feature support
- *
- * This section sets support for features that are or are not needed
- * within the modules that are enabled.
- * \{
- */
-
-/**
- * \def MBEDTLS_TIMING_ALT
- *
- * Uncomment to provide your own alternate implementation for mbedtls_timing_hardclock(),
- * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay()
- *
- * Only works if you have MBEDTLS_TIMING_C enabled.
- *
- * You will need to provide a header "timing_alt.h" and an implementation at
- * compile time.
- */
-//#define MBEDTLS_TIMING_ALT
-
-/**
- * \def MBEDTLS_AES_ALT
- *
- * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your
- * alternate core implementation of a symmetric crypto, an arithmetic or hash
- * module (e.g. platform specific assembly optimized implementations). Keep
- * in mind that the function prototypes should remain the same.
- *
- * This replaces the whole module. If you only want to replace one of the
- * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags.
- *
- * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer
- * provide the "struct mbedtls_aes_context" definition and omit the base
- * function declarations and implementations. "aes_alt.h" will be included from
- * "aes.h" to include the new function definitions.
- *
- * Uncomment a macro to enable alternate implementation of the corresponding
- * module.
- *
- * \warning   MD2, MD4, MD5, ARC4, DES and SHA-1 are considered weak and their
- *            use constitutes a security risk. If possible, we recommend
- *            avoiding dependencies on them, and considering stronger message
- *            digests and ciphers instead.
- *
- */
-//#define MBEDTLS_AES_ALT
-//#define MBEDTLS_ARC4_ALT
-//#define MBEDTLS_ARIA_ALT
-//#define MBEDTLS_BLOWFISH_ALT
-//#define MBEDTLS_CAMELLIA_ALT
-//#define MBEDTLS_CCM_ALT
-//#define MBEDTLS_CHACHA20_ALT
-//#define MBEDTLS_CHACHAPOLY_ALT
-//#define MBEDTLS_CMAC_ALT
-//#define MBEDTLS_DES_ALT
-//#define MBEDTLS_DHM_ALT
-//#define MBEDTLS_ECJPAKE_ALT
-//#define MBEDTLS_GCM_ALT
-//#define MBEDTLS_NIST_KW_ALT
-//#define MBEDTLS_MD2_ALT
-//#define MBEDTLS_MD4_ALT
-//#define MBEDTLS_MD5_ALT
-//#define MBEDTLS_POLY1305_ALT
-//#define MBEDTLS_RIPEMD160_ALT
-//#define MBEDTLS_RSA_ALT
-//#define MBEDTLS_SHA1_ALT
-//#define MBEDTLS_SHA256_ALT
-//#define MBEDTLS_SHA512_ALT
-//#define MBEDTLS_XTEA_ALT
-
-/*
- * When replacing the elliptic curve module, pleace consider, that it is
- * implemented with two .c files:
- *      - ecp.c
- *      - ecp_curves.c
- * You can replace them very much like all the other MBEDTLS__MODULE_NAME__ALT
- * macros as described above. The only difference is that you have to make sure
- * that you provide functionality for both .c files.
- */
-//#define MBEDTLS_ECP_ALT
-
-/**
- * \def MBEDTLS_MD2_PROCESS_ALT
- *
- * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you
- * alternate core implementation of symmetric crypto or hash function. Keep in
- * mind that function prototypes should remain the same.
- *
- * This replaces only one function. The header file from mbed TLS is still
- * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags.
- *
- * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will
- * no longer provide the mbedtls_sha1_process() function, but it will still provide
- * the other function (using your mbedtls_sha1_process() function) and the definition
- * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible
- * with this definition.
- *
- * \note Because of a signature change, the core AES encryption and decryption routines are
- *       currently named mbedtls_aes_internal_encrypt and mbedtls_aes_internal_decrypt,
- *       respectively. When setting up alternative implementations, these functions should
- *       be overridden, but the wrapper functions mbedtls_aes_decrypt and mbedtls_aes_encrypt
- *       must stay untouched.
- *
- * \note If you use the AES_xxx_ALT macros, then is is recommended to also set
- *       MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES
- *       tables.
- *
- * Uncomment a macro to enable alternate implementation of the corresponding
- * function.
- *
- * \warning   MD2, MD4, MD5, DES and SHA-1 are considered weak and their use
- *            constitutes a security risk. If possible, we recommend avoiding
- *            dependencies on them, and considering stronger message digests
- *            and ciphers instead.
- *
- * \warning   If both MBEDTLS_ECDSA_SIGN_ALT and MBEDTLS_ECDSA_DETERMINISTIC are
- *            enabled, then the deterministic ECDH signature functions pass the
- *            the static HMAC-DRBG as RNG to mbedtls_ecdsa_sign(). Therefore
- *            alternative implementations should use the RNG only for generating
- *            the ephemeral key and nothing else. If this is not possible, then
- *            MBEDTLS_ECDSA_DETERMINISTIC should be disabled and an alternative
- *            implementation should be provided for mbedtls_ecdsa_sign_det_ext()
- *            (and for mbedtls_ecdsa_sign_det() too if backward compatibility is
- *            desirable).
- *
- */
-//#define MBEDTLS_MD2_PROCESS_ALT
-//#define MBEDTLS_MD4_PROCESS_ALT
-//#define MBEDTLS_MD5_PROCESS_ALT
-//#define MBEDTLS_RIPEMD160_PROCESS_ALT
-//#define MBEDTLS_SHA1_PROCESS_ALT
-//#define MBEDTLS_SHA256_PROCESS_ALT
-//#define MBEDTLS_SHA512_PROCESS_ALT
-//#define MBEDTLS_DES_SETKEY_ALT
-//#define MBEDTLS_DES_CRYPT_ECB_ALT
-//#define MBEDTLS_DES3_CRYPT_ECB_ALT
-//#define MBEDTLS_AES_SETKEY_ENC_ALT
-//#define MBEDTLS_AES_SETKEY_DEC_ALT
-//#define MBEDTLS_AES_ENCRYPT_ALT
-//#define MBEDTLS_AES_DECRYPT_ALT
-//#define MBEDTLS_ECDH_GEN_PUBLIC_ALT
-//#define MBEDTLS_ECDH_COMPUTE_SHARED_ALT
-//#define MBEDTLS_ECDSA_VERIFY_ALT
-//#define MBEDTLS_ECDSA_SIGN_ALT
-//#define MBEDTLS_ECDSA_GENKEY_ALT
-
-/**
- * \def MBEDTLS_ECP_INTERNAL_ALT
- *
- * Expose a part of the internal interface of the Elliptic Curve Point module.
- *
- * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use your
- * alternative core implementation of elliptic curve arithmetic. Keep in mind
- * that function prototypes should remain the same.
- *
- * This partially replaces one function. The header file from mbed TLS is still
- * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation
- * is still present and it is used for group structures not supported by the
- * alternative.
- *
- * Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT
- * and implementing the following functions:
- *      unsigned char mbedtls_internal_ecp_grp_capable(
- *          const mbedtls_ecp_group *grp )
- *      int  mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp )
- *      void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp )
- * The mbedtls_internal_ecp_grp_capable function should return 1 if the
- * replacement functions implement arithmetic for the given group and 0
- * otherwise.
- * The functions mbedtls_internal_ecp_init and mbedtls_internal_ecp_free are
- * called before and after each point operation and provide an opportunity to
- * implement optimized set up and tear down instructions.
- *
- * Example: In case you uncomment MBEDTLS_ECP_INTERNAL_ALT and
- * MBEDTLS_ECP_DOUBLE_JAC_ALT, mbed TLS will still provide the ecp_double_jac
- * function, but will use your mbedtls_internal_ecp_double_jac if the group is
- * supported (your mbedtls_internal_ecp_grp_capable function returns 1 when
- * receives it as an argument). If the group is not supported then the original
- * implementation is used. The other functions and the definition of
- * mbedtls_ecp_group and mbedtls_ecp_point will not change, so your
- * implementation of mbedtls_internal_ecp_double_jac and
- * mbedtls_internal_ecp_grp_capable must be compatible with this definition.
- *
- * Uncomment a macro to enable alternate implementation of the corresponding
- * function.
- */
-/* Required for all the functions in this section */
-//#define MBEDTLS_ECP_INTERNAL_ALT
-/* Support for Weierstrass curves with Jacobi representation */
-//#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT
-//#define MBEDTLS_ECP_ADD_MIXED_ALT
-//#define MBEDTLS_ECP_DOUBLE_JAC_ALT
-//#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT
-//#define MBEDTLS_ECP_NORMALIZE_JAC_ALT
-/* Support for curves with Montgomery arithmetic */
-//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT
-//#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT
-//#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT
-
-/**
- * \def MBEDTLS_TEST_NULL_ENTROPY
- *
- * Enables testing and use of mbed TLS without any configured entropy sources.
- * This permits use of the library on platforms before an entropy source has
- * been integrated (see for example the MBEDTLS_ENTROPY_HARDWARE_ALT or the
- * MBEDTLS_ENTROPY_NV_SEED switches).
- *
- * WARNING! This switch MUST be disabled in production builds, and is suitable
- * only for development.
- * Enabling the switch negates any security provided by the library.
- *
- * Requires MBEDTLS_ENTROPY_C, MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
- *
- */
-//#define MBEDTLS_TEST_NULL_ENTROPY
-
-/**
- * \def MBEDTLS_ENTROPY_HARDWARE_ALT
- *
- * Uncomment this macro to let mbed TLS use your own implementation of a
- * hardware entropy collector.
- *
- * Your function must be called \c mbedtls_hardware_poll(), have the same
- * prototype as declared in entropy_poll.h, and accept NULL as first argument.
- *
- * Uncomment to use your own hardware entropy collector.
- */
-//#define MBEDTLS_ENTROPY_HARDWARE_ALT
-
-/**
- * \def MBEDTLS_AES_ROM_TABLES
- *
- * Use precomputed AES tables stored in ROM.
- *
- * Uncomment this macro to use precomputed AES tables stored in ROM.
- * Comment this macro to generate AES tables in RAM at runtime.
- *
- * Tradeoff: Using precomputed ROM tables reduces RAM usage by ~8kb
- * (or ~2kb if \c MBEDTLS_AES_FEWER_TABLES is used) and reduces the
- * initialization time before the first AES operation can be performed.
- * It comes at the cost of additional ~8kb ROM use (resp. ~2kb if \c
- * MBEDTLS_AES_FEWER_TABLES below is used), and potentially degraded
- * performance if ROM access is slower than RAM access.
- *
- * This option is independent of \c MBEDTLS_AES_FEWER_TABLES.
- *
- */
-//#define MBEDTLS_AES_ROM_TABLES
-
-/**
- * \def MBEDTLS_AES_FEWER_TABLES
- *
- * Use less ROM/RAM for AES tables.
- *
- * Uncommenting this macro omits 75% of the AES tables from
- * ROM / RAM (depending on the value of \c MBEDTLS_AES_ROM_TABLES)
- * by computing their values on the fly during operations
- * (the tables are entry-wise rotations of one another).
- *
- * Tradeoff: Uncommenting this reduces the RAM / ROM footprint
- * by ~6kb but at the cost of more arithmetic operations during
- * runtime. Specifically, one has to compare 4 accesses within
- * different tables to 4 accesses with additional arithmetic
- * operations within the same table. The performance gain/loss
- * depends on the system and memory details.
- *
- * This option is independent of \c MBEDTLS_AES_ROM_TABLES.
- *
- */
-//#define MBEDTLS_AES_FEWER_TABLES
-
-/**
- * \def MBEDTLS_CAMELLIA_SMALL_MEMORY
- *
- * Use less ROM for the Camellia implementation (saves about 768 bytes).
- *
- * Uncomment this macro to use less memory for Camellia.
- */
-//#define MBEDTLS_CAMELLIA_SMALL_MEMORY
-
-/**
- * \def MBEDTLS_CIPHER_MODE_CBC
- *
- * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers.
- */
-#define MBEDTLS_CIPHER_MODE_CBC
-
-/**
- * \def MBEDTLS_CIPHER_MODE_CFB
- *
- * Enable Cipher Feedback mode (CFB) for symmetric ciphers.
- */
-#define MBEDTLS_CIPHER_MODE_CFB
-
-/**
- * \def MBEDTLS_CIPHER_MODE_CTR
- *
- * Enable Counter Block Cipher mode (CTR) for symmetric ciphers.
- */
-#define MBEDTLS_CIPHER_MODE_CTR
-
-/**
- * \def MBEDTLS_CIPHER_MODE_OFB
- *
- * Enable Output Feedback mode (OFB) for symmetric ciphers.
- */
-#define MBEDTLS_CIPHER_MODE_OFB
-
-/**
- * \def MBEDTLS_CIPHER_MODE_XTS
- *
- * Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES.
- */
-#define MBEDTLS_CIPHER_MODE_XTS
-
-/**
- * \def MBEDTLS_CIPHER_NULL_CIPHER
- *
- * Enable NULL cipher.
- * Warning: Only do so when you know what you are doing. This allows for
- * encryption or channels without any security!
- *
- * Requires MBEDTLS_ENABLE_WEAK_CIPHERSUITES as well to enable
- * the following ciphersuites:
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA
- *      MBEDTLS_TLS_RSA_WITH_NULL_SHA256
- *      MBEDTLS_TLS_RSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_RSA_WITH_NULL_MD5
- *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA
- *      MBEDTLS_TLS_PSK_WITH_NULL_SHA384
- *      MBEDTLS_TLS_PSK_WITH_NULL_SHA256
- *      MBEDTLS_TLS_PSK_WITH_NULL_SHA
- *
- * Uncomment this macro to enable the NULL cipher and ciphersuites
- */
-//#define MBEDTLS_CIPHER_NULL_CIPHER
-
-/**
- * \def MBEDTLS_CIPHER_PADDING_PKCS7
- *
- * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for
- * specific padding modes in the cipher layer with cipher modes that support
- * padding (e.g. CBC)
- *
- * If you disable all padding modes, only full blocks can be used with CBC.
- *
- * Enable padding modes in the cipher layer.
- */
-#define MBEDTLS_CIPHER_PADDING_PKCS7
-#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
-#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
-#define MBEDTLS_CIPHER_PADDING_ZEROS
-
-/** \def MBEDTLS_CTR_DRBG_USE_128_BIT_KEY
- *
- * Uncomment this macro to use a 128-bit key in the CTR_DRBG module.
- * By default, CTR_DRBG uses a 256-bit key.
- */
-//#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY
-
-/**
- * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES
- *
- * Enable weak ciphersuites in SSL / TLS.
- * Warning: Only do so when you know what you are doing. This allows for
- * channels with virtually no security at all!
- *
- * This enables the following ciphersuites:
- *      MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA
- *
- * Uncomment this macro to enable weak ciphersuites
- *
- * \warning   DES is considered a weak cipher and its use constitutes a
- *            security risk. We recommend considering stronger ciphers instead.
- */
-//#define MBEDTLS_ENABLE_WEAK_CIPHERSUITES
-
-/**
- * \def MBEDTLS_REMOVE_ARC4_CIPHERSUITES
- *
- * Remove RC4 ciphersuites by default in SSL / TLS.
- * This flag removes the ciphersuites based on RC4 from the default list as
- * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible to
- * enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including them
- * explicitly.
- *
- * Uncomment this macro to remove RC4 ciphersuites by default.
- */
-#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES
-
-/**
- * \def MBEDTLS_REMOVE_3DES_CIPHERSUITES
- *
- * Remove 3DES ciphersuites by default in SSL / TLS.
- * This flag removes the ciphersuites based on 3DES from the default list as
- * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible
- * to enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including
- * them explicitly.
- *
- * A man-in-the-browser attacker can recover authentication tokens sent through
- * a TLS connection using a 3DES based cipher suite (see "On the Practical
- * (In-)Security of 64-bit Block Ciphers" by Karthikeyan Bhargavan and Gaëtan
- * Leurent, see https://sweet32.info/SWEET32_CCS16.pdf). If this attack falls
- * in your threat model or you are unsure, then you should keep this option
- * enabled to remove 3DES based cipher suites.
- *
- * Comment this macro to keep 3DES in the default ciphersuite list.
- */
-#define MBEDTLS_REMOVE_3DES_CIPHERSUITES
-
-/**
- * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED
- *
- * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve
- * module.  By default all supported curves are enabled.
- *
- * Comment macros to disable the curve and functions for it
- */
-#define MBEDTLS_ECP_DP_SECP192R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP521R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP192K1_ENABLED
-#define MBEDTLS_ECP_DP_SECP224K1_ENABLED
-#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
-#define MBEDTLS_ECP_DP_BP256R1_ENABLED
-#define MBEDTLS_ECP_DP_BP384R1_ENABLED
-#define MBEDTLS_ECP_DP_BP512R1_ENABLED
-#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
-#define MBEDTLS_ECP_DP_CURVE448_ENABLED
-
-/**
- * \def MBEDTLS_ECP_NIST_OPTIM
- *
- * Enable specific 'modulo p' routines for each NIST prime.
- * Depending on the prime and architecture, makes operations 4 to 8 times
- * faster on the corresponding curve.
- *
- * Comment this macro to disable NIST curves optimisation.
- */
-#define MBEDTLS_ECP_NIST_OPTIM
-
-/**
- * \def MBEDTLS_ECP_NO_INTERNAL_RNG
- *
- * When this option is disabled, mbedtls_ecp_mul() will make use of an
- * internal RNG when called with a NULL \c f_rng argument, in order to protect
- * against some side-channel attacks.
- *
- * This protection introduces a dependency of the ECP module on one of the
- * DRBG or SHA modules (HMAC-DRBG, CTR-DRBG, SHA-512 or SHA-256.) For very
- * constrained applications that don't require this protection (for example,
- * because you're only doing signature verification, so not manipulating any
- * secret, or because local/physical side-channel attacks are outside your
- * threat model), it might be desirable to get rid of that dependency.
- *
- * \warning Enabling this option makes some uses of ECP vulnerable to some
- * side-channel attacks. Only enable it if you know that's not a problem for
- * your use case.
- *
- * Uncomment this macro to disable some counter-measures in ECP.
- */
-//#define MBEDTLS_ECP_NO_INTERNAL_RNG
-
-/**
- * \def MBEDTLS_ECP_RESTARTABLE
- *
- * Enable "non-blocking" ECC operations that can return early and be resumed.
- *
- * This allows various functions to pause by returning
- * #MBEDTLS_ERR_ECP_IN_PROGRESS (or, for functions in the SSL module,
- * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS) and then be called later again in
- * order to further progress and eventually complete their operation. This is
- * controlled through mbedtls_ecp_set_max_ops() which limits the maximum
- * number of ECC operations a function may perform before pausing; see
- * mbedtls_ecp_set_max_ops() for more information.
- *
- * This is useful in non-threaded environments if you want to avoid blocking
- * for too long on ECC (and, hence, X.509 or SSL/TLS) operations.
- *
- * Uncomment this macro to enable restartable ECC computations.
- *
- * \note  This option only works with the default software implementation of
- *        elliptic curve functionality. It is incompatible with
- *        MBEDTLS_ECP_ALT, MBEDTLS_ECDH_XXX_ALT and MBEDTLS_ECDSA_XXX_ALT.
- */
-//#define MBEDTLS_ECP_RESTARTABLE
-
-/**
- * \def MBEDTLS_ECDSA_DETERMINISTIC
- *
- * Enable deterministic ECDSA (RFC 6979).
- * Standard ECDSA is "fragile" in the sense that lack of entropy when signing
- * may result in a compromise of the long-term signing key. This is avoided by
- * the deterministic variant.
- *
- * Requires: MBEDTLS_HMAC_DRBG_C
- *
- * Comment this macro to disable deterministic ECDSA.
- */
-#define MBEDTLS_ECDSA_DETERMINISTIC
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
- *
- * Enable the PSK based ciphersuite modes in SSL / TLS.
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
- */
-#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
- *
- * Enable the DHE-PSK based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_DHM_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
- *
- * \warning    Using DHE constitutes a security risk as it
- *             is not possible to validate custom DH parameters.
- *             If possible, it is recommended users should consider
- *             preferring other methods of key exchange.
- *             See dhm.h for more details.
- *
- */
-#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
- *
- * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
- */
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
- *
- * Enable the RSA-PSK based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
- *           MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
- */
-#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
- *
- * Enable the RSA-only based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
- *           MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
- */
-#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
- *
- * Enable the DHE-RSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
- *           MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
- *
- * \warning    Using DHE constitutes a security risk as it
- *             is not possible to validate custom DH parameters.
- *             If possible, it is recommended users should consider
- *             preferring other methods of key exchange.
- *             See dhm.h for more details.
- *
- */
-#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
- *
- * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
- *           MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
- */
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
- *
- * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C,
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
- */
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
- *
- * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
- */
-#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
- *
- * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
- */
-#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
- *
- * Enable the ECJPAKE based ciphersuite modes in SSL / TLS.
- *
- * \warning This is currently experimental. EC J-PAKE support is based on the
- * Thread v1.0.0 specification; incompatible changes to the specification
- * might still happen. For this reason, this is disabled by default.
- *
- * Requires: MBEDTLS_ECJPAKE_C
- *           MBEDTLS_SHA256_C
- *           MBEDTLS_ECP_DP_SECP256R1_ENABLED
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
- */
-//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
-
-/**
- * \def MBEDTLS_PK_PARSE_EC_EXTENDED
- *
- * Enhance support for reading EC keys using variants of SEC1 not allowed by
- * RFC 5915 and RFC 5480.
- *
- * Currently this means parsing the SpecifiedECDomain choice of EC
- * parameters (only known groups are supported, not arbitrary domains, to
- * avoid validation issues).
- *
- * Disable if you only need to support RFC 5915 + 5480 key formats.
- */
-#define MBEDTLS_PK_PARSE_EC_EXTENDED
-
-/**
- * \def MBEDTLS_ERROR_STRERROR_DUMMY
- *
- * Enable a dummy error function to make use of mbedtls_strerror() in
- * third party libraries easier when MBEDTLS_ERROR_C is disabled
- * (no effect when MBEDTLS_ERROR_C is enabled).
- *
- * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're
- * not using mbedtls_strerror() or error_strerror() in your application.
- *
- * Disable if you run into name conflicts and want to really remove the
- * mbedtls_strerror()
- */
-#define MBEDTLS_ERROR_STRERROR_DUMMY
-
-/**
- * \def MBEDTLS_GENPRIME
- *
- * Enable the prime-number generation code.
- *
- * Requires: MBEDTLS_BIGNUM_C
- */
-#define MBEDTLS_GENPRIME
-
-/**
- * \def MBEDTLS_FS_IO
- *
- * Enable functions that use the filesystem.
- */
-#define MBEDTLS_FS_IO
-
-/**
- * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
- *
- * Do not add default entropy sources. These are the platform specific,
- * mbedtls_timing_hardclock and HAVEGE based poll functions.
- *
- * This is useful to have more control over the added entropy sources in an
- * application.
- *
- * Uncomment this macro to prevent loading of default entropy functions.
- */
-//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-
-/**
- * \def MBEDTLS_NO_PLATFORM_ENTROPY
- *
- * Do not use built-in platform entropy functions.
- * This is useful if your platform does not support
- * standards like the /dev/urandom or Windows CryptoAPI.
- *
- * Uncomment this macro to disable the built-in platform entropy functions.
- */
-//#define MBEDTLS_NO_PLATFORM_ENTROPY
-
-/**
- * \def MBEDTLS_ENTROPY_FORCE_SHA256
- *
- * Force the entropy accumulator to use a SHA-256 accumulator instead of the
- * default SHA-512 based one (if both are available).
- *
- * Requires: MBEDTLS_SHA256_C
- *
- * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option
- * if you have performance concerns.
- *
- * This option is only useful if both MBEDTLS_SHA256_C and
- * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used.
- */
-//#define MBEDTLS_ENTROPY_FORCE_SHA256
-
-/**
- * \def MBEDTLS_ENTROPY_NV_SEED
- *
- * Enable the non-volatile (NV) seed file-based entropy source.
- * (Also enables the NV seed read/write functions in the platform layer)
- *
- * This is crucial (if not required) on systems that do not have a
- * cryptographic entropy source (in hardware or kernel) available.
- *
- * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C
- *
- * \note The read/write functions that are used by the entropy source are
- *       determined in the platform layer, and can be modified at runtime and/or
- *       compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used.
- *
- * \note If you use the default implementation functions that read a seedfile
- *       with regular fopen(), please make sure you make a seedfile with the
- *       proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at
- *       least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from
- *       and written to or you will get an entropy source error! The default
- *       implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE
- *       bytes from the file.
- *
- * \note The entropy collector will write to the seed file before entropy is
- *       given to an external source, to update it.
- */
-//#define MBEDTLS_ENTROPY_NV_SEED
-
-/**
- * \def MBEDTLS_MEMORY_DEBUG
- *
- * Enable debugging of buffer allocator memory issues. Automatically prints
- * (to stderr) all (fatal) messages on memory allocation issues. Enables
- * function for 'debug output' of allocated memory.
- *
- * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
- *
- * Uncomment this macro to let the buffer allocator print out error messages.
- */
-//#define MBEDTLS_MEMORY_DEBUG
-
-/**
- * \def MBEDTLS_MEMORY_BACKTRACE
- *
- * Include backtrace information with each allocated block.
- *
- * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
- *           GLIBC-compatible backtrace() an backtrace_symbols() support
- *
- * Uncomment this macro to include backtrace information
- */
-//#define MBEDTLS_MEMORY_BACKTRACE
-
-/**
- * \def MBEDTLS_PK_RSA_ALT_SUPPORT
- *
- * Support external private RSA keys (eg from a HSM) in the PK layer.
- *
- * Comment this macro to disable support for external private RSA keys.
- */
-#define MBEDTLS_PK_RSA_ALT_SUPPORT
-
-/**
- * \def MBEDTLS_PKCS1_V15
- *
- * Enable support for PKCS#1 v1.5 encoding.
- *
- * Requires: MBEDTLS_RSA_C
- *
- * This enables support for PKCS#1 v1.5 operations.
- */
-#define MBEDTLS_PKCS1_V15
-
-/**
- * \def MBEDTLS_PKCS1_V21
- *
- * Enable support for PKCS#1 v2.1 encoding.
- *
- * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C
- *
- * This enables support for RSAES-OAEP and RSASSA-PSS operations.
- */
-#define MBEDTLS_PKCS1_V21
-
-/**
- * \def MBEDTLS_RSA_NO_CRT
- *
- * Do not use the Chinese Remainder Theorem
- * for the RSA private operation.
- *
- * Uncomment this macro to disable the use of CRT in RSA.
- *
- */
-//#define MBEDTLS_RSA_NO_CRT
-
-/**
- * \def MBEDTLS_SELF_TEST
- *
- * Enable the checkup functions (*_self_test).
- */
-#define MBEDTLS_SELF_TEST
-
-/**
- * \def MBEDTLS_SHA256_SMALLER
- *
- * Enable an implementation of SHA-256 that has lower ROM footprint but also
- * lower performance.
- *
- * The default implementation is meant to be a reasonnable compromise between
- * performance and size. This version optimizes more aggressively for size at
- * the expense of performance. Eg on Cortex-M4 it reduces the size of
- * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about
- * 30%.
- *
- * Uncomment to enable the smaller implementation of SHA256.
- */
-//#define MBEDTLS_SHA256_SMALLER
-
-/**
- * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES
- *
- * Enable sending of alert messages in case of encountered errors as per RFC.
- * If you choose not to send the alert messages, mbed TLS can still communicate
- * with other servers, only debugging of failures is harder.
- *
- * The advantage of not sending alert messages, is that no information is given
- * about reasons for failures thus preventing adversaries of gaining intel.
- *
- * Enable sending of all alert messages
- */
-#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
-
-/**
- * \def MBEDTLS_SSL_ASYNC_PRIVATE
- *
- * Enable asynchronous external private key operations in SSL. This allows
- * you to configure an SSL connection to call an external cryptographic
- * module to perform private key operations instead of performing the
- * operation inside the library.
- *
- */
-//#define MBEDTLS_SSL_ASYNC_PRIVATE
-
-/**
- * \def MBEDTLS_SSL_DEBUG_ALL
- *
- * Enable the debug messages in SSL module for all issues.
- * Debug messages have been disabled in some places to prevent timing
- * attacks due to (unbalanced) debugging function calls.
- *
- * If you need all error reporting you should enable this during debugging,
- * but remove this for production servers that should log as well.
- *
- * Uncomment this macro to report all debug messages on errors introducing
- * a timing side-channel.
- *
- */
-//#define MBEDTLS_SSL_DEBUG_ALL
-
-/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC
- *
- * Enable support for Encrypt-then-MAC, RFC 7366.
- *
- * This allows peers that both support it to use a more robust protection for
- * ciphersuites using CBC, providing deep resistance against timing attacks
- * on the padding or underlying cipher.
- *
- * This only affects CBC ciphersuites, and is useless if none is defined.
- *
- * Requires: MBEDTLS_SSL_PROTO_TLS1    or
- *           MBEDTLS_SSL_PROTO_TLS1_1  or
- *           MBEDTLS_SSL_PROTO_TLS1_2
- *
- * Comment this macro to disable support for Encrypt-then-MAC
- */
-#define MBEDTLS_SSL_ENCRYPT_THEN_MAC
-
-/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET
- *
- * Enable support for Extended Master Secret, aka Session Hash
- * (draft-ietf-tls-session-hash-02).
- *
- * This was introduced as "the proper fix" to the Triple Handshake familiy of
- * attacks, but it is recommended to always use it (even if you disable
- * renegotiation), since it actually fixes a more fundamental issue in the
- * original SSL/TLS design, and has implications beyond Triple Handshake.
- *
- * Requires: MBEDTLS_SSL_PROTO_TLS1    or
- *           MBEDTLS_SSL_PROTO_TLS1_1  or
- *           MBEDTLS_SSL_PROTO_TLS1_2
- *
- * Comment this macro to disable support for Extended Master Secret.
- */
-#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET
-
-/**
- * \def MBEDTLS_SSL_FALLBACK_SCSV
- *
- * Enable support for FALLBACK_SCSV (draft-ietf-tls-downgrade-scsv-00).
- *
- * For servers, it is recommended to always enable this, unless you support
- * only one version of TLS, or know for sure that none of your clients
- * implements a fallback strategy.
- *
- * For clients, you only need this if you're using a fallback strategy, which
- * is not recommended in the first place, unless you absolutely need it to
- * interoperate with buggy (version-intolerant) servers.
- *
- * Comment this macro to disable support for FALLBACK_SCSV
- */
-#define MBEDTLS_SSL_FALLBACK_SCSV
-
-/**
- * \def MBEDTLS_SSL_HW_RECORD_ACCEL
- *
- * Enable hooking functions in SSL module for hardware acceleration of
- * individual records.
- *
- * Uncomment this macro to enable hooking functions.
- */
-//#define MBEDTLS_SSL_HW_RECORD_ACCEL
-
-/**
- * \def MBEDTLS_SSL_CBC_RECORD_SPLITTING
- *
- * Enable 1/n-1 record splitting for CBC mode in SSLv3 and TLS 1.0.
- *
- * This is a countermeasure to the BEAST attack, which also minimizes the risk
- * of interoperability issues compared to sending 0-length records.
- *
- * Comment this macro to disable 1/n-1 record splitting.
- */
-#define MBEDTLS_SSL_CBC_RECORD_SPLITTING
-
-/**
- * \def MBEDTLS_SSL_RENEGOTIATION
- *
- * Enable support for TLS renegotiation.
- *
- * The two main uses of renegotiation are (1) refresh keys on long-lived
- * connections and (2) client authentication after the initial handshake.
- * If you don't need renegotiation, it's probably better to disable it, since
- * it has been associated with security issues in the past and is easy to
- * misuse/misunderstand.
- *
- * Comment this to disable support for renegotiation.
- *
- * \note   Even if this option is disabled, both client and server are aware
- *         of the Renegotiation Indication Extension (RFC 5746) used to
- *         prevent the SSL renegotiation attack (see RFC 5746 Sect. 1).
- *         (See \c mbedtls_ssl_conf_legacy_renegotiation for the
- *          configuration of this extension).
- *
- */
-#define MBEDTLS_SSL_RENEGOTIATION
-
-/**
- * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
- *
- * Enable support for receiving and parsing SSLv2 Client Hello messages for the
- * SSL Server module (MBEDTLS_SSL_SRV_C).
- *
- * Uncomment this macro to enable support for SSLv2 Client Hello messages.
- */
-//#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
-
-/**
- * \def MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
- *
- * Pick the ciphersuite according to the client's preferences rather than ours
- * in the SSL Server module (MBEDTLS_SSL_SRV_C).
- *
- * Uncomment this macro to respect client's ciphersuite order
- */
-//#define MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
-
-/**
- * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
- *
- * Enable support for RFC 6066 max_fragment_length extension in SSL.
- *
- * Comment this macro to disable support for the max_fragment_length extension
- */
-#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
-
-/**
- * \def MBEDTLS_SSL_PROTO_SSL3
- *
- * Enable support for SSL 3.0.
- *
- * Requires: MBEDTLS_MD5_C
- *           MBEDTLS_SHA1_C
- *
- * Comment this macro to disable support for SSL 3.0
- */
-//#define MBEDTLS_SSL_PROTO_SSL3
-
-/**
- * \def MBEDTLS_SSL_PROTO_TLS1
- *
- * Enable support for TLS 1.0.
- *
- * Requires: MBEDTLS_MD5_C
- *           MBEDTLS_SHA1_C
- *
- * Comment this macro to disable support for TLS 1.0
- */
-#define MBEDTLS_SSL_PROTO_TLS1
-
-/**
- * \def MBEDTLS_SSL_PROTO_TLS1_1
- *
- * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled).
- *
- * Requires: MBEDTLS_MD5_C
- *           MBEDTLS_SHA1_C
- *
- * Comment this macro to disable support for TLS 1.1 / DTLS 1.0
- */
-#define MBEDTLS_SSL_PROTO_TLS1_1
-
-/**
- * \def MBEDTLS_SSL_PROTO_TLS1_2
- *
- * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled).
- *
- * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C
- *           (Depends on ciphersuites)
- *
- * Comment this macro to disable support for TLS 1.2 / DTLS 1.2
- */
-#define MBEDTLS_SSL_PROTO_TLS1_2
-
-/**
- * \def MBEDTLS_SSL_PROTO_DTLS
- *
- * Enable support for DTLS (all available versions).
- *
- * Enable this and MBEDTLS_SSL_PROTO_TLS1_1 to enable DTLS 1.0,
- * and/or this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2.
- *
- * Requires: MBEDTLS_SSL_PROTO_TLS1_1
- *        or MBEDTLS_SSL_PROTO_TLS1_2
- *
- * Comment this macro to disable support for DTLS
- */
-#define MBEDTLS_SSL_PROTO_DTLS
-
-/**
- * \def MBEDTLS_SSL_ALPN
- *
- * Enable support for RFC 7301 Application Layer Protocol Negotiation.
- *
- * Comment this macro to disable support for ALPN.
- */
-#define MBEDTLS_SSL_ALPN
-
-/**
- * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY
- *
- * Enable support for the anti-replay mechanism in DTLS.
- *
- * Requires: MBEDTLS_SSL_TLS_C
- *           MBEDTLS_SSL_PROTO_DTLS
- *
- * \warning Disabling this is often a security risk!
- * See mbedtls_ssl_conf_dtls_anti_replay() for details.
- *
- * Comment this to disable anti-replay in DTLS.
- */
-#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
-
-/**
- * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY
- *
- * Enable support for HelloVerifyRequest on DTLS servers.
- *
- * This feature is highly recommended to prevent DTLS servers being used as
- * amplifiers in DoS attacks against other hosts. It should always be enabled
- * unless you know for sure amplification cannot be a problem in the
- * environment in which your server operates.
- *
- * \warning Disabling this can ba a security risk! (see above)
- *
- * Requires: MBEDTLS_SSL_PROTO_DTLS
- *
- * Comment this to disable support for HelloVerifyRequest.
- */
-#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
-
-/**
- * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
- *
- * Enable server-side support for clients that reconnect from the same port.
- *
- * Some clients unexpectedly close the connection and try to reconnect using the
- * same source port. This needs special support from the server to handle the
- * new connection securely, as described in section 4.2.8 of RFC 6347. This
- * flag enables that support.
- *
- * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY
- *
- * Comment this to disable support for clients reusing the source port.
- */
-#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
-
-/**
- * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT
- *
- * Enable support for a limit of records with bad MAC.
- *
- * See mbedtls_ssl_conf_dtls_badmac_limit().
- *
- * Requires: MBEDTLS_SSL_PROTO_DTLS
- */
-#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT
-
-/**
- * \def MBEDTLS_SSL_SESSION_TICKETS
- *
- * Enable support for RFC 5077 session tickets in SSL.
- * Client-side, provides full support for session tickets (maintenance of a
- * session store remains the responsibility of the application, though).
- * Server-side, you also need to provide callbacks for writing and parsing
- * tickets, including authenticated encryption and key management. Example
- * callbacks are provided by MBEDTLS_SSL_TICKET_C.
- *
- * Comment this macro to disable support for SSL session tickets
- */
-#define MBEDTLS_SSL_SESSION_TICKETS
-
-/**
- * \def MBEDTLS_SSL_EXPORT_KEYS
- *
- * Enable support for exporting key block and master secret.
- * This is required for certain users of TLS, e.g. EAP-TLS.
- *
- * Comment this macro to disable support for key export
- */
-#define MBEDTLS_SSL_EXPORT_KEYS
-
-/**
- * \def MBEDTLS_SSL_SERVER_NAME_INDICATION
- *
- * Enable support for RFC 6066 server name indication (SNI) in SSL.
- *
- * Requires: MBEDTLS_X509_CRT_PARSE_C
- *
- * Comment this macro to disable support for server name indication in SSL
- */
-#define MBEDTLS_SSL_SERVER_NAME_INDICATION
-
-/**
- * \def MBEDTLS_SSL_TRUNCATED_HMAC
- *
- * Enable support for RFC 6066 truncated HMAC in SSL.
- *
- * Comment this macro to disable support for truncated HMAC in SSL
- */
-#define MBEDTLS_SSL_TRUNCATED_HMAC
-
-/**
- * \def MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT
- *
- * Fallback to old (pre-2.7), non-conforming implementation of the truncated
- * HMAC extension which also truncates the HMAC key. Note that this option is
- * only meant for a transitory upgrade period and is likely to be removed in
- * a future version of the library.
- *
- * \warning The old implementation is non-compliant and has a security weakness
- *          (2^80 brute force attack on the HMAC key used for a single,
- *          uninterrupted connection). This should only be enabled temporarily
- *          when (1) the use of truncated HMAC is essential in order to save
- *          bandwidth, and (2) the peer is an Mbed TLS stack that doesn't use
- *          the fixed implementation yet (pre-2.7).
- *
- * \deprecated This option is deprecated and will likely be removed in a
- *             future version of Mbed TLS.
- *
- * Uncomment to fallback to old, non-compliant truncated HMAC implementation.
- *
- * Requires: MBEDTLS_SSL_TRUNCATED_HMAC
- */
-//#define MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT
-
-/**
- * \def MBEDTLS_THREADING_ALT
- *
- * Provide your own alternate threading implementation.
- *
- * Requires: MBEDTLS_THREADING_C
- *
- * Uncomment this to allow your own alternate threading implementation.
- */
-//#define MBEDTLS_THREADING_ALT
-
-/**
- * \def MBEDTLS_THREADING_PTHREAD
- *
- * Enable the pthread wrapper layer for the threading layer.
- *
- * Requires: MBEDTLS_THREADING_C
- *
- * Uncomment this to enable pthread mutexes.
- */
-//#define MBEDTLS_THREADING_PTHREAD
-
-/**
- * \def MBEDTLS_VERSION_FEATURES
- *
- * Allow run-time checking of compile-time enabled features. Thus allowing users
- * to check at run-time if the library is for instance compiled with threading
- * support via mbedtls_version_check_feature().
- *
- * Requires: MBEDTLS_VERSION_C
- *
- * Comment this to disable run-time checking and save ROM space
- */
-#define MBEDTLS_VERSION_FEATURES
-
-/**
- * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
- *
- * If set, the X509 parser will not break-off when parsing an X509 certificate
- * and encountering an extension in a v1 or v2 certificate.
- *
- * Uncomment to prevent an error.
- */
-//#define MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
-
-/**
- * \def MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
- *
- * If set, the X509 parser will not break-off when parsing an X509 certificate
- * and encountering an unknown critical extension.
- *
- * \warning Depending on your PKI use, enabling this can be a security risk!
- *
- * Uncomment to prevent an error.
- */
-//#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
-
-/**
- * \def MBEDTLS_X509_CHECK_KEY_USAGE
- *
- * Enable verification of the keyUsage extension (CA and leaf certificates).
- *
- * Disabling this avoids problems with mis-issued and/or misused
- * (intermediate) CA and leaf certificates.
- *
- * \warning Depending on your PKI use, disabling this can be a security risk!
- *
- * Comment to skip keyUsage checking for both CA and leaf certificates.
- */
-#define MBEDTLS_X509_CHECK_KEY_USAGE
-
-/**
- * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
- *
- * Enable verification of the extendedKeyUsage extension (leaf certificates).
- *
- * Disabling this avoids problems with mis-issued and/or misused certificates.
- *
- * \warning Depending on your PKI use, disabling this can be a security risk!
- *
- * Comment to skip extendedKeyUsage checking for certificates.
- */
-#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
-
-/**
- * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT
- *
- * Enable parsing and verification of X.509 certificates, CRLs and CSRS
- * signed with RSASSA-PSS (aka PKCS#1 v2.1).
- *
- * Comment this macro to disallow using RSASSA-PSS in certificates.
- */
-#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
-
-/**
- * \def MBEDTLS_ZLIB_SUPPORT
- *
- * If set, the SSL/TLS module uses ZLIB to support compression and
- * decompression of packet data.
- *
- * \warning TLS-level compression MAY REDUCE SECURITY! See for example the
- * CRIME attack. Before enabling this option, you should examine with care if
- * CRIME or similar exploits may be applicable to your use case.
- *
- * \note Currently compression can't be used with DTLS.
- *
- * \deprecated This feature is deprecated and will be removed
- *             in the next major revision of the library.
- *
- * Used in: library/ssl_tls.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * This feature requires zlib library and headers to be present.
- *
- * Uncomment to enable use of ZLIB
- */
-//#define MBEDTLS_ZLIB_SUPPORT
-/* \} name SECTION: mbed TLS feature support */
-
-/**
- * \name SECTION: mbed TLS modules
- *
- * This section enables or disables entire modules in mbed TLS
- * \{
- */
-
-/**
- * \def MBEDTLS_AESNI_C
- *
- * Enable AES-NI support on x86-64.
- *
- * Module:  library/aesni.c
- * Caller:  library/aes.c
- *
- * Requires: MBEDTLS_HAVE_ASM
- *
- * This modules adds support for the AES-NI instructions on x86-64
- */
-#define MBEDTLS_AESNI_C
-
-/**
- * \def MBEDTLS_AES_C
- *
- * Enable the AES block cipher.
- *
- * Module:  library/aes.c
- * Caller:  library/cipher.c
- *          library/pem.c
- *          library/ctr_drbg.c
- *
- * This module enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
- *
- * PEM_PARSE uses AES for decrypting encrypted keys.
- */
-#define MBEDTLS_AES_C
-
-/**
- * \def MBEDTLS_ARC4_C
- *
- * Enable the ARCFOUR stream cipher.
- *
- * Module:  library/arc4.c
- * Caller:  library/cipher.c
- *
- * This module enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
- *      MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
- *
- * \warning   ARC4 is considered a weak cipher and its use constitutes a
- *            security risk. If possible, we recommend avoidng dependencies on
- *            it, and considering stronger ciphers instead.
- *
- */
-#define MBEDTLS_ARC4_C
-
-/**
- * \def MBEDTLS_ASN1_PARSE_C
- *
- * Enable the generic ASN1 parser.
- *
- * Module:  library/asn1.c
- * Caller:  library/x509.c
- *          library/dhm.c
- *          library/pkcs12.c
- *          library/pkcs5.c
- *          library/pkparse.c
- */
-#define MBEDTLS_ASN1_PARSE_C
-
-/**
- * \def MBEDTLS_ASN1_WRITE_C
- *
- * Enable the generic ASN1 writer.
- *
- * Module:  library/asn1write.c
- * Caller:  library/ecdsa.c
- *          library/pkwrite.c
- *          library/x509_create.c
- *          library/x509write_crt.c
- *          library/x509write_csr.c
- */
-#define MBEDTLS_ASN1_WRITE_C
-
-/**
- * \def MBEDTLS_BASE64_C
- *
- * Enable the Base64 module.
- *
- * Module:  library/base64.c
- * Caller:  library/pem.c
- *
- * This module is required for PEM support (required by X.509).
- */
-#define MBEDTLS_BASE64_C
-
-/**
- * \def MBEDTLS_BIGNUM_C
- *
- * Enable the multi-precision integer library.
- *
- * Module:  library/bignum.c
- * Caller:  library/dhm.c
- *          library/ecp.c
- *          library/ecdsa.c
- *          library/rsa.c
- *          library/rsa_internal.c
- *          library/ssl_tls.c
- *
- * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support.
- */
-#define MBEDTLS_BIGNUM_C
-
-/**
- * \def MBEDTLS_BLOWFISH_C
- *
- * Enable the Blowfish block cipher.
- *
- * Module:  library/blowfish.c
- */
-#define MBEDTLS_BLOWFISH_C
-
-/**
- * \def MBEDTLS_CAMELLIA_C
- *
- * Enable the Camellia block cipher.
- *
- * Module:  library/camellia.c
- * Caller:  library/cipher.c
- *
- * This module enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
- */
-#define MBEDTLS_CAMELLIA_C
-
-/**
- * \def MBEDTLS_ARIA_C
- *
- * Enable the ARIA block cipher.
- *
- * Module:  library/aria.c
- * Caller:  library/cipher.c
- *
- * This module enables the following ciphersuites (if other requisites are
- * enabled as well):
- *
- *      MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384
- *      MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384
- *      MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256
- *      MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384
- */
-//#define MBEDTLS_ARIA_C
-
-/**
- * \def MBEDTLS_CCM_C
- *
- * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher.
- *
- * Module:  library/ccm.c
- *
- * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
- *
- * This module enables the AES-CCM ciphersuites, if other requisites are
- * enabled as well.
- */
-#define MBEDTLS_CCM_C
-
-/**
- * \def MBEDTLS_CERTS_C
- *
- * Enable the test certificates.
- *
- * Module:  library/certs.c
- * Caller:
- *
- * This module is used for testing (ssl_client/server).
- */
-#define MBEDTLS_CERTS_C
-
-/**
- * \def MBEDTLS_CHACHA20_C
- *
- * Enable the ChaCha20 stream cipher.
- *
- * Module:  library/chacha20.c
- */
-#define MBEDTLS_CHACHA20_C
-
-/**
- * \def MBEDTLS_CHACHAPOLY_C
- *
- * Enable the ChaCha20-Poly1305 AEAD algorithm.
- *
- * Module:  library/chachapoly.c
- *
- * This module requires: MBEDTLS_CHACHA20_C, MBEDTLS_POLY1305_C
- */
-#define MBEDTLS_CHACHAPOLY_C
-
-/**
- * \def MBEDTLS_CIPHER_C
- *
- * Enable the generic cipher layer.
- *
- * Module:  library/cipher.c
- * Caller:  library/ssl_tls.c
- *
- * Uncomment to enable generic cipher wrappers.
- */
-#define MBEDTLS_CIPHER_C
-
-/**
- * \def MBEDTLS_CMAC_C
- *
- * Enable the CMAC (Cipher-based Message Authentication Code) mode for block
- * ciphers.
- *
- * Module:  library/cmac.c
- *
- * Requires: MBEDTLS_AES_C or MBEDTLS_DES_C
- *
- */
-//#define MBEDTLS_CMAC_C
-
-/**
- * \def MBEDTLS_CTR_DRBG_C
- *
- * Enable the CTR_DRBG AES-based random generator.
- * The CTR_DRBG generator uses AES-256 by default.
- * To use AES-128 instead, enable \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY above.
- *
- * \note To achieve a 256-bit security strength with CTR_DRBG,
- *       you must use AES-256 *and* use sufficient entropy.
- *       See ctr_drbg.h for more details.
- *
- * Module:  library/ctr_drbg.c
- * Caller:
- *
- * Requires: MBEDTLS_AES_C
- *
- * This module provides the CTR_DRBG AES random number generator.
- */
-#define MBEDTLS_CTR_DRBG_C
-
-/**
- * \def MBEDTLS_DEBUG_C
- *
- * Enable the debug functions.
- *
- * Module:  library/debug.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *
- * This module provides debugging functions.
- */
-#define MBEDTLS_DEBUG_C
-
-/**
- * \def MBEDTLS_DES_C
- *
- * Enable the DES block cipher.
- *
- * Module:  library/des.c
- * Caller:  library/pem.c
- *          library/cipher.c
- *
- * This module enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
- *
- * PEM_PARSE uses DES/3DES for decrypting encrypted keys.
- *
- * \warning   DES is considered a weak cipher and its use constitutes a
- *            security risk. We recommend considering stronger ciphers instead.
- */
-#define MBEDTLS_DES_C
-
-/**
- * \def MBEDTLS_DHM_C
- *
- * Enable the Diffie-Hellman-Merkle module.
- *
- * Module:  library/dhm.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * This module is used by the following key exchanges:
- *      DHE-RSA, DHE-PSK
- *
- * \warning    Using DHE constitutes a security risk as it
- *             is not possible to validate custom DH parameters.
- *             If possible, it is recommended users should consider
- *             preferring other methods of key exchange.
- *             See dhm.h for more details.
- *
- */
-#define MBEDTLS_DHM_C
-
-/**
- * \def MBEDTLS_ECDH_C
- *
- * Enable the elliptic curve Diffie-Hellman library.
- *
- * Module:  library/ecdh.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * This module is used by the following key exchanges:
- *      ECDHE-ECDSA, ECDHE-RSA, DHE-PSK
- *
- * Requires: MBEDTLS_ECP_C
- */
-#define MBEDTLS_ECDH_C
-
-/**
- * \def MBEDTLS_ECDSA_C
- *
- * Enable the elliptic curve DSA library.
- *
- * Module:  library/ecdsa.c
- * Caller:
- *
- * This module is used by the following key exchanges:
- *      ECDHE-ECDSA
- *
- * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C
- */
-#define MBEDTLS_ECDSA_C
-
-/**
- * \def MBEDTLS_ECJPAKE_C
- *
- * Enable the elliptic curve J-PAKE library.
- *
- * \warning This is currently experimental. EC J-PAKE support is based on the
- * Thread v1.0.0 specification; incompatible changes to the specification
- * might still happen. For this reason, this is disabled by default.
- *
- * Module:  library/ecjpake.c
- * Caller:
- *
- * This module is used by the following key exchanges:
- *      ECJPAKE
- *
- * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C
- */
-//#define MBEDTLS_ECJPAKE_C
-
-/**
- * \def MBEDTLS_ECP_C
- *
- * Enable the elliptic curve over GF(p) library.
- *
- * Module:  library/ecp.c
- * Caller:  library/ecdh.c
- *          library/ecdsa.c
- *          library/ecjpake.c
- *
- * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED
- */
-#define MBEDTLS_ECP_C
-
-/**
- * \def MBEDTLS_ENTROPY_C
- *
- * Enable the platform-specific entropy code.
- *
- * Module:  library/entropy.c
- * Caller:
- *
- * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C
- *
- * This module provides a generic entropy pool
- */
-#define MBEDTLS_ENTROPY_C
-
-/**
- * \def MBEDTLS_ERROR_C
- *
- * Enable error code to error string conversion.
- *
- * Module:  library/error.c
- * Caller:
- *
- * This module enables mbedtls_strerror().
- */
-#define MBEDTLS_ERROR_C
-
-/**
- * \def MBEDTLS_GCM_C
- *
- * Enable the Galois/Counter Mode (GCM) for AES.
- *
- * Module:  library/gcm.c
- *
- * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
- *
- * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other
- * requisites are enabled as well.
- */
-#define MBEDTLS_GCM_C
-
-/**
- * \def MBEDTLS_HAVEGE_C
- *
- * Enable the HAVEGE random generator.
- *
- * Warning: the HAVEGE random generator is not suitable for virtualized
- *          environments
- *
- * Warning: the HAVEGE random generator is dependent on timing and specific
- *          processor traits. It is therefore not advised to use HAVEGE as
- *          your applications primary random generator or primary entropy pool
- *          input. As a secondary input to your entropy pool, it IS able add
- *          the (limited) extra entropy it provides.
- *
- * Module:  library/havege.c
- * Caller:
- *
- * Requires: MBEDTLS_TIMING_C
- *
- * Uncomment to enable the HAVEGE random generator.
- */
-//#define MBEDTLS_HAVEGE_C
-
-/**
- * \def MBEDTLS_HKDF_C
- *
- * Enable the HKDF algorithm (RFC 5869).
- *
- * Module:  library/hkdf.c
- * Caller:
- *
- * Requires: MBEDTLS_MD_C
- *
- * This module adds support for the Hashed Message Authentication Code
- * (HMAC)-based key derivation function (HKDF).
- */
-#define MBEDTLS_HKDF_C
-
-/**
- * \def MBEDTLS_HMAC_DRBG_C
- *
- * Enable the HMAC_DRBG random generator.
- *
- * Module:  library/hmac_drbg.c
- * Caller:
- *
- * Requires: MBEDTLS_MD_C
- *
- * Uncomment to enable the HMAC_DRBG random number geerator.
- */
-#define MBEDTLS_HMAC_DRBG_C
-
-/**
- * \def MBEDTLS_NIST_KW_C
- *
- * Enable the Key Wrapping mode for 128-bit block ciphers,
- * as defined in NIST SP 800-38F. Only KW and KWP modes
- * are supported. At the moment, only AES is approved by NIST.
- *
- * Module:  library/nist_kw.c
- *
- * Requires: MBEDTLS_AES_C and MBEDTLS_CIPHER_C
- */
-//#define MBEDTLS_NIST_KW_C
-
-/**
- * \def MBEDTLS_MD_C
- *
- * Enable the generic message digest layer.
- *
- * Module:  library/md.c
- * Caller:
- *
- * Uncomment to enable generic message digest wrappers.
- */
-#define MBEDTLS_MD_C
-
-/**
- * \def MBEDTLS_MD2_C
- *
- * Enable the MD2 hash algorithm.
- *
- * Module:  library/md2.c
- * Caller:
- *
- * Uncomment to enable support for (rare) MD2-signed X.509 certs.
- *
- * \warning   MD2 is considered a weak message digest and its use constitutes a
- *            security risk. If possible, we recommend avoiding dependencies on
- *            it, and considering stronger message digests instead.
- *
- */
-//#define MBEDTLS_MD2_C
-
-/**
- * \def MBEDTLS_MD4_C
- *
- * Enable the MD4 hash algorithm.
- *
- * Module:  library/md4.c
- * Caller:
- *
- * Uncomment to enable support for (rare) MD4-signed X.509 certs.
- *
- * \warning   MD4 is considered a weak message digest and its use constitutes a
- *            security risk. If possible, we recommend avoiding dependencies on
- *            it, and considering stronger message digests instead.
- *
- */
-//#define MBEDTLS_MD4_C
-
-/**
- * \def MBEDTLS_MD5_C
- *
- * Enable the MD5 hash algorithm.
- *
- * Module:  library/md5.c
- * Caller:  library/md.c
- *          library/pem.c
- *          library/ssl_tls.c
- *
- * This module is required for SSL/TLS up to version 1.1, and for TLS 1.2
- * depending on the handshake parameters. Further, it is used for checking
- * MD5-signed certificates, and for PBKDF1 when decrypting PEM-encoded
- * encrypted keys.
- *
- * \warning   MD5 is considered a weak message digest and its use constitutes a
- *            security risk. If possible, we recommend avoiding dependencies on
- *            it, and considering stronger message digests instead.
- *
- */
-#define MBEDTLS_MD5_C
-
-/**
- * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C
- *
- * Enable the buffer allocator implementation that makes use of a (stack)
- * based buffer to 'allocate' dynamic memory. (replaces calloc() and free()
- * calls)
- *
- * Module:  library/memory_buffer_alloc.c
- *
- * Requires: MBEDTLS_PLATFORM_C
- *           MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS)
- *
- * Enable this module to enable the buffer memory allocator.
- */
-//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
-
-/**
- * \def MBEDTLS_NET_C
- *
- * Enable the TCP and UDP over IPv6/IPv4 networking routines.
- *
- * \note This module only works on POSIX/Unix (including Linux, BSD and OS X)
- * and Windows. For other platforms, you'll want to disable it, and write your
- * own networking callbacks to be passed to \c mbedtls_ssl_set_bio().
- *
- * \note See also our Knowledge Base article about porting to a new
- * environment:
- * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
- *
- * Module:  library/net_sockets.c
- *
- * This module provides networking routines.
- */
-#define MBEDTLS_NET_C
-
-/**
- * \def MBEDTLS_OID_C
- *
- * Enable the OID database.
- *
- * Module:  library/oid.c
- * Caller:  library/asn1write.c
- *          library/pkcs5.c
- *          library/pkparse.c
- *          library/pkwrite.c
- *          library/rsa.c
- *          library/x509.c
- *          library/x509_create.c
- *          library/x509_crl.c
- *          library/x509_crt.c
- *          library/x509_csr.c
- *          library/x509write_crt.c
- *          library/x509write_csr.c
- *
- * This modules translates between OIDs and internal values.
- */
-#define MBEDTLS_OID_C
-
-/**
- * \def MBEDTLS_PADLOCK_C
- *
- * Enable VIA Padlock support on x86.
- *
- * Module:  library/padlock.c
- * Caller:  library/aes.c
- *
- * Requires: MBEDTLS_HAVE_ASM
- *
- * This modules adds support for the VIA PadLock on x86.
- */
-#define MBEDTLS_PADLOCK_C
-
-/**
- * \def MBEDTLS_PEM_PARSE_C
- *
- * Enable PEM decoding / parsing.
- *
- * Module:  library/pem.c
- * Caller:  library/dhm.c
- *          library/pkparse.c
- *          library/x509_crl.c
- *          library/x509_crt.c
- *          library/x509_csr.c
- *
- * Requires: MBEDTLS_BASE64_C
- *
- * This modules adds support for decoding / parsing PEM files.
- */
-#define MBEDTLS_PEM_PARSE_C
-
-/**
- * \def MBEDTLS_PEM_WRITE_C
- *
- * Enable PEM encoding / writing.
- *
- * Module:  library/pem.c
- * Caller:  library/pkwrite.c
- *          library/x509write_crt.c
- *          library/x509write_csr.c
- *
- * Requires: MBEDTLS_BASE64_C
- *
- * This modules adds support for encoding / writing PEM files.
- */
-#define MBEDTLS_PEM_WRITE_C
-
-/**
- * \def MBEDTLS_PK_C
- *
- * Enable the generic public (asymetric) key layer.
- *
- * Module:  library/pk.c
- * Caller:  library/ssl_tls.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C
- *
- * Uncomment to enable generic public key wrappers.
- */
-#define MBEDTLS_PK_C
-
-/**
- * \def MBEDTLS_PK_PARSE_C
- *
- * Enable the generic public (asymetric) key parser.
- *
- * Module:  library/pkparse.c
- * Caller:  library/x509_crt.c
- *          library/x509_csr.c
- *
- * Requires: MBEDTLS_PK_C
- *
- * Uncomment to enable generic public key parse functions.
- */
-#define MBEDTLS_PK_PARSE_C
-
-/**
- * \def MBEDTLS_PK_WRITE_C
- *
- * Enable the generic public (asymetric) key writer.
- *
- * Module:  library/pkwrite.c
- * Caller:  library/x509write.c
- *
- * Requires: MBEDTLS_PK_C
- *
- * Uncomment to enable generic public key write functions.
- */
-#define MBEDTLS_PK_WRITE_C
-
-/**
- * \def MBEDTLS_PKCS5_C
- *
- * Enable PKCS#5 functions.
- *
- * Module:  library/pkcs5.c
- *
- * Requires: MBEDTLS_MD_C
- *
- * This module adds support for the PKCS#5 functions.
- */
-#define MBEDTLS_PKCS5_C
-
-/**
- * \def MBEDTLS_PKCS11_C
- *
- * Enable wrapper for PKCS#11 smartcard support.
- *
- * Module:  library/pkcs11.c
- * Caller:  library/pk.c
- *
- * Requires: MBEDTLS_PK_C
- *
- * This module enables SSL/TLS PKCS #11 smartcard support.
- * Requires the presence of the PKCS#11 helper library (libpkcs11-helper)
- */
-//#define MBEDTLS_PKCS11_C
-
-/**
- * \def MBEDTLS_PKCS12_C
- *
- * Enable PKCS#12 PBE functions.
- * Adds algorithms for parsing PKCS#8 encrypted private keys
- *
- * Module:  library/pkcs12.c
- * Caller:  library/pkparse.c
- *
- * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C
- * Can use:  MBEDTLS_ARC4_C
- *
- * This module enables PKCS#12 functions.
- */
-#define MBEDTLS_PKCS12_C
-
-/**
- * \def MBEDTLS_PLATFORM_C
- *
- * Enable the platform abstraction layer that allows you to re-assign
- * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit().
- *
- * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT
- * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned
- * above to be specified at runtime or compile time respectively.
- *
- * \note This abstraction layer must be enabled on Windows (including MSYS2)
- * as other module rely on it for a fixed snprintf implementation.
- *
- * Module:  library/platform.c
- * Caller:  Most other .c files
- *
- * This module enables abstraction of common (libc) functions.
- */
-#define MBEDTLS_PLATFORM_C
-
-/**
- * \def MBEDTLS_POLY1305_C
- *
- * Enable the Poly1305 MAC algorithm.
- *
- * Module:  library/poly1305.c
- * Caller:  library/chachapoly.c
- */
-#define MBEDTLS_POLY1305_C
-
-/**
- * \def MBEDTLS_RIPEMD160_C
- *
- * Enable the RIPEMD-160 hash algorithm.
- *
- * Module:  library/ripemd160.c
- * Caller:  library/md.c
- *
- */
-#define MBEDTLS_RIPEMD160_C
-
-/**
- * \def MBEDTLS_RSA_C
- *
- * Enable the RSA public-key cryptosystem.
- *
- * Module:  library/rsa.c
- *          library/rsa_internal.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *          library/x509.c
- *
- * This module is used by the following key exchanges:
- *      RSA, DHE-RSA, ECDHE-RSA, RSA-PSK
- *
- * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C
- */
-#define MBEDTLS_RSA_C
-
-/**
- * \def MBEDTLS_SHA1_C
- *
- * Enable the SHA1 cryptographic hash algorithm.
- *
- * Module:  library/sha1.c
- * Caller:  library/md.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *          library/x509write_crt.c
- *
- * This module is required for SSL/TLS up to version 1.1, for TLS 1.2
- * depending on the handshake parameters, and for SHA1-signed certificates.
- *
- * \warning   SHA-1 is considered a weak message digest and its use constitutes
- *            a security risk. If possible, we recommend avoiding dependencies
- *            on it, and considering stronger message digests instead.
- *
- */
-#define MBEDTLS_SHA1_C
-
-/**
- * \def MBEDTLS_SHA256_C
- *
- * Enable the SHA-224 and SHA-256 cryptographic hash algorithms.
- *
- * Module:  library/sha256.c
- * Caller:  library/entropy.c
- *          library/md.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *
- * This module adds support for SHA-224 and SHA-256.
- * This module is required for the SSL/TLS 1.2 PRF function.
- */
-#define MBEDTLS_SHA256_C
-
-/**
- * \def MBEDTLS_SHA512_C
- *
- * Enable the SHA-384 and SHA-512 cryptographic hash algorithms.
- *
- * Module:  library/sha512.c
- * Caller:  library/entropy.c
- *          library/md.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * This module adds support for SHA-384 and SHA-512.
- */
-#define MBEDTLS_SHA512_C
-
-/**
- * \def MBEDTLS_SSL_CACHE_C
- *
- * Enable simple SSL cache implementation.
- *
- * Module:  library/ssl_cache.c
- * Caller:
- *
- * Requires: MBEDTLS_SSL_CACHE_C
- */
-#define MBEDTLS_SSL_CACHE_C
-
-/**
- * \def MBEDTLS_SSL_COOKIE_C
- *
- * Enable basic implementation of DTLS cookies for hello verification.
- *
- * Module:  library/ssl_cookie.c
- * Caller:
- */
-#define MBEDTLS_SSL_COOKIE_C
-
-/**
- * \def MBEDTLS_SSL_TICKET_C
- *
- * Enable an implementation of TLS server-side callbacks for session tickets.
- *
- * Module:  library/ssl_ticket.c
- * Caller:
- *
- * Requires: MBEDTLS_CIPHER_C
- */
-#define MBEDTLS_SSL_TICKET_C
-
-/**
- * \def MBEDTLS_SSL_CLI_C
- *
- * Enable the SSL/TLS client code.
- *
- * Module:  library/ssl_cli.c
- * Caller:
- *
- * Requires: MBEDTLS_SSL_TLS_C
- *
- * This module is required for SSL/TLS client support.
- */
-#define MBEDTLS_SSL_CLI_C
-
-/**
- * \def MBEDTLS_SSL_SRV_C
- *
- * Enable the SSL/TLS server code.
- *
- * Module:  library/ssl_srv.c
- * Caller:
- *
- * Requires: MBEDTLS_SSL_TLS_C
- *
- * This module is required for SSL/TLS server support.
- */
-#define MBEDTLS_SSL_SRV_C
-
-/**
- * \def MBEDTLS_SSL_TLS_C
- *
- * Enable the generic SSL/TLS code.
- *
- * Module:  library/ssl_tls.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C
- *           and at least one of the MBEDTLS_SSL_PROTO_XXX defines
- *
- * This module is required for SSL/TLS.
- */
-#define MBEDTLS_SSL_TLS_C
-
-/**
- * \def MBEDTLS_THREADING_C
- *
- * Enable the threading abstraction layer.
- * By default mbed TLS assumes it is used in a non-threaded environment or that
- * contexts are not shared between threads. If you do intend to use contexts
- * between threads, you will need to enable this layer to prevent race
- * conditions. See also our Knowledge Base article about threading:
- * https://tls.mbed.org/kb/development/thread-safety-and-multi-threading
- *
- * Module:  library/threading.c
- *
- * This allows different threading implementations (self-implemented or
- * provided).
- *
- * You will have to enable either MBEDTLS_THREADING_ALT or
- * MBEDTLS_THREADING_PTHREAD.
- *
- * Enable this layer to allow use of mutexes within mbed TLS
- */
-//#define MBEDTLS_THREADING_C
-
-/**
- * \def MBEDTLS_TIMING_C
- *
- * Enable the semi-portable timing interface.
- *
- * \note The provided implementation only works on POSIX/Unix (including Linux,
- * BSD and OS X) and Windows. On other platforms, you can either disable that
- * module and provide your own implementations of the callbacks needed by
- * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide
- * your own implementation of the whole module by setting
- * \c MBEDTLS_TIMING_ALT in the current file.
- *
- * \note See also our Knowledge Base article about porting to a new
- * environment:
- * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS
- *
- * Module:  library/timing.c
- * Caller:  library/havege.c
- *
- * This module is used by the HAVEGE random number generator.
- */
-#define MBEDTLS_TIMING_C
-
-/**
- * \def MBEDTLS_VERSION_C
- *
- * Enable run-time version information.
- *
- * Module:  library/version.c
- *
- * This module provides run-time version information.
- */
-#define MBEDTLS_VERSION_C
-
-/**
- * \def MBEDTLS_X509_USE_C
- *
- * Enable X.509 core for using certificates.
- *
- * Module:  library/x509.c
- * Caller:  library/x509_crl.c
- *          library/x509_crt.c
- *          library/x509_csr.c
- *
- * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C,
- *           MBEDTLS_PK_PARSE_C
- *
- * This module is required for the X.509 parsing modules.
- */
-#define MBEDTLS_X509_USE_C
-
-/**
- * \def MBEDTLS_X509_CRT_PARSE_C
- *
- * Enable X.509 certificate parsing.
- *
- * Module:  library/x509_crt.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *
- * Requires: MBEDTLS_X509_USE_C
- *
- * This module is required for X.509 certificate parsing.
- */
-#define MBEDTLS_X509_CRT_PARSE_C
-
-/**
- * \def MBEDTLS_X509_CRL_PARSE_C
- *
- * Enable X.509 CRL parsing.
- *
- * Module:  library/x509_crl.c
- * Caller:  library/x509_crt.c
- *
- * Requires: MBEDTLS_X509_USE_C
- *
- * This module is required for X.509 CRL parsing.
- */
-#define MBEDTLS_X509_CRL_PARSE_C
-
-/**
- * \def MBEDTLS_X509_CSR_PARSE_C
- *
- * Enable X.509 Certificate Signing Request (CSR) parsing.
- *
- * Module:  library/x509_csr.c
- * Caller:  library/x509_crt_write.c
- *
- * Requires: MBEDTLS_X509_USE_C
- *
- * This module is used for reading X.509 certificate request.
- */
-#define MBEDTLS_X509_CSR_PARSE_C
-
-/**
- * \def MBEDTLS_X509_CREATE_C
- *
- * Enable X.509 core for creating certificates.
- *
- * Module:  library/x509_create.c
- *
- * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C
- *
- * This module is the basis for creating X.509 certificates and CSRs.
- */
-#define MBEDTLS_X509_CREATE_C
-
-/**
- * \def MBEDTLS_X509_CRT_WRITE_C
- *
- * Enable creating X.509 certificates.
- *
- * Module:  library/x509_crt_write.c
- *
- * Requires: MBEDTLS_X509_CREATE_C
- *
- * This module is required for X.509 certificate creation.
- */
-#define MBEDTLS_X509_CRT_WRITE_C
-
-/**
- * \def MBEDTLS_X509_CSR_WRITE_C
- *
- * Enable creating X.509 Certificate Signing Requests (CSR).
- *
- * Module:  library/x509_csr_write.c
- *
- * Requires: MBEDTLS_X509_CREATE_C
- *
- * This module is required for X.509 certificate request writing.
- */
-#define MBEDTLS_X509_CSR_WRITE_C
-
-/**
- * \def MBEDTLS_XTEA_C
- *
- * Enable the XTEA block cipher.
- *
- * Module:  library/xtea.c
- * Caller:
- */
-#define MBEDTLS_XTEA_C
-
-/* \} name SECTION: mbed TLS modules */
-
-/**
- * \name SECTION: Module configuration options
- *
- * This section allows for the setting of module specific sizes and
- * configuration options. The default values are already present in the
- * relevant header files and should suffice for the regular use cases.
- *
- * Our advice is to enable options and change their values here
- * only if you have a good reason and know the consequences.
- *
- * Please check the respective header file for documentation on these
- * parameters (to prevent duplicate documentation).
- * \{
- */
-
-/* MPI / BIGNUM options */
-//#define MBEDTLS_MPI_WINDOW_SIZE            6 /**< Maximum windows size used. */
-//#define MBEDTLS_MPI_MAX_SIZE            1024 /**< Maximum number of bytes for usable MPIs. */
-
-/* CTR_DRBG options */
-//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN               48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */
-//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL        10000 /**< Interval before reseed is performed by default */
-//#define MBEDTLS_CTR_DRBG_MAX_INPUT                256 /**< Maximum number of additional input bytes */
-//#define MBEDTLS_CTR_DRBG_MAX_REQUEST             1024 /**< Maximum number of requested bytes per call */
-//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT           384 /**< Maximum size of (re)seed buffer */
-
-/* HMAC_DRBG options */
-//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL   10000 /**< Interval before reseed is performed by default */
-//#define MBEDTLS_HMAC_DRBG_MAX_INPUT           256 /**< Maximum number of additional input bytes */
-//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST        1024 /**< Maximum number of requested bytes per call */
-//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT      384 /**< Maximum size of (re)seed buffer */
-
-/* ECP options */
-//#define MBEDTLS_ECP_MAX_BITS             521 /**< Maximum bit size of groups */
-//#define MBEDTLS_ECP_WINDOW_SIZE            6 /**< Maximum window size used */
-//#define MBEDTLS_ECP_FIXED_POINT_OPTIM      1 /**< Enable fixed-point speed-up */
-
-/* Entropy options */
-//#define MBEDTLS_ENTROPY_MAX_SOURCES                20 /**< Maximum number of sources supported */
-//#define MBEDTLS_ENTROPY_MAX_GATHER                128 /**< Maximum amount requested from entropy sources */
-//#define MBEDTLS_ENTROPY_MIN_HARDWARE               32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */
-
-/* Memory buffer allocator options */
-//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE      4 /**< Align on multiples of this value */
-
-/* Platform options */
-//#define MBEDTLS_PLATFORM_STD_MEM_HDR   <stdlib.h> /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */
-//#define MBEDTLS_PLATFORM_STD_CALLOC        calloc /**< Default allocator to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_FREE            free /**< Default free to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_EXIT            exit /**< Default exit to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_TIME            time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
-//#define MBEDTLS_PLATFORM_STD_FPRINTF      fprintf /**< Default fprintf to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_PRINTF        printf /**< Default printf to use, can be undefined */
-/* Note: your snprintf must correctly zero-terminate the buffer! */
-//#define MBEDTLS_PLATFORM_STD_SNPRINTF    snprintf /**< Default snprintf to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS       0 /**< Default exit value to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE       1 /**< Default exit value to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ   mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE  mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE  "seedfile" /**< Seed file to read/write with default implementation */
-
-/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */
-/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */
-//#define MBEDTLS_PLATFORM_CALLOC_MACRO        calloc /**< Default allocator macro to use, can be undefined */
-//#define MBEDTLS_PLATFORM_FREE_MACRO            free /**< Default free macro to use, can be undefined */
-//#define MBEDTLS_PLATFORM_EXIT_MACRO            exit /**< Default exit macro to use, can be undefined */
-//#define MBEDTLS_PLATFORM_TIME_MACRO            time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
-//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO       time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */
-//#define MBEDTLS_PLATFORM_FPRINTF_MACRO      fprintf /**< Default fprintf macro to use, can be undefined */
-//#define MBEDTLS_PLATFORM_PRINTF_MACRO        printf /**< Default printf macro to use, can be undefined */
-/* Note: your snprintf must correctly zero-terminate the buffer! */
-//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO    snprintf /**< Default snprintf macro to use, can be undefined */
-//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO   mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */
-//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO  mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */
-
-/**
- * \brief       This macro is invoked by the library when an invalid parameter
- *              is detected that is only checked with #MBEDTLS_CHECK_PARAMS
- *              (see the documentation of that option for context).
- *
- *              When you leave this undefined here, the library provides
- *              a default definition. If the macro #MBEDTLS_CHECK_PARAMS_ASSERT
- *              is defined, the default definition is `assert(cond)`,
- *              otherwise the default definition calls a function
- *              mbedtls_param_failed(). This function is declared in
- *              `platform_util.h` for the benefit of the library, but
- *              you need to define in your application.
- *
- *              When you define this here, this replaces the default
- *              definition in platform_util.h (which no longer declares the
- *              function mbedtls_param_failed()) and it is your responsibility
- *              to make sure this macro expands to something suitable (in
- *              particular, that all the necessary declarations are visible
- *              from within the library - you can ensure that by providing
- *              them in this file next to the macro definition).
- *              If you define this macro to call `assert`, also define
- *              #MBEDTLS_CHECK_PARAMS_ASSERT so that library source files
- *              include `<assert.h>`.
- *
- *              Note that you may define this macro to expand to nothing, in
- *              which case you don't have to worry about declarations or
- *              definitions. However, you will then be notified about invalid
- *              parameters only in non-void functions, and void function will
- *              just silently return early on invalid parameters, which
- *              partially negates the benefits of enabling
- *              #MBEDTLS_CHECK_PARAMS in the first place, so is discouraged.
- *
- * \param cond  The expression that should evaluate to true, but doesn't.
- */
-//#define MBEDTLS_PARAM_FAILED( cond )               assert( cond )
-
-/* SSL Cache options */
-//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT       86400 /**< 1 day  */
-//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES      50 /**< Maximum entries in cache */
-
-/* SSL options */
-
-/** \def MBEDTLS_SSL_MAX_CONTENT_LEN
- *
- * Maximum length (in bytes) of incoming and outgoing plaintext fragments.
- *
- * This determines the size of both the incoming and outgoing TLS I/O buffers
- * in such a way that both are capable of holding the specified amount of
- * plaintext data, regardless of the protection mechanism used.
- *
- * To configure incoming and outgoing I/O buffers separately, use
- * #MBEDTLS_SSL_IN_CONTENT_LEN and #MBEDTLS_SSL_OUT_CONTENT_LEN,
- * which overwrite the value set by this option.
- *
- * \note When using a value less than the default of 16KB on the client, it is
- *       recommended to use the Maximum Fragment Length (MFL) extension to
- *       inform the server about this limitation. On the server, there
- *       is no supported, standardized way of informing the client about
- *       restriction on the maximum size of incoming messages, and unless
- *       the limitation has been communicated by other means, it is recommended
- *       to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN
- *       while keeping the default value of 16KB for the incoming buffer.
- *
- * Uncomment to set the maximum plaintext size of both
- * incoming and outgoing I/O buffers.
- */
-//#define MBEDTLS_SSL_MAX_CONTENT_LEN             16384
-
-/** \def MBEDTLS_SSL_IN_CONTENT_LEN
- *
- * Maximum length (in bytes) of incoming plaintext fragments.
- *
- * This determines the size of the incoming TLS I/O buffer in such a way
- * that it is capable of holding the specified amount of plaintext data,
- * regardless of the protection mechanism used.
- *
- * If this option is undefined, it inherits its value from
- * #MBEDTLS_SSL_MAX_CONTENT_LEN.
- *
- * \note When using a value less than the default of 16KB on the client, it is
- *       recommended to use the Maximum Fragment Length (MFL) extension to
- *       inform the server about this limitation. On the server, there
- *       is no supported, standardized way of informing the client about
- *       restriction on the maximum size of incoming messages, and unless
- *       the limitation has been communicated by other means, it is recommended
- *       to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN
- *       while keeping the default value of 16KB for the incoming buffer.
- *
- * Uncomment to set the maximum plaintext size of the incoming I/O buffer
- * independently of the outgoing I/O buffer.
- */
-//#define MBEDTLS_SSL_IN_CONTENT_LEN              16384
-
-/** \def MBEDTLS_SSL_OUT_CONTENT_LEN
- *
- * Maximum length (in bytes) of outgoing plaintext fragments.
- *
- * This determines the size of the outgoing TLS I/O buffer in such a way
- * that it is capable of holding the specified amount of plaintext data,
- * regardless of the protection mechanism used.
- *
- * If this option undefined, it inherits its value from
- * #MBEDTLS_SSL_MAX_CONTENT_LEN.
- *
- * It is possible to save RAM by setting a smaller outward buffer, while keeping
- * the default inward 16384 byte buffer to conform to the TLS specification.
- *
- * The minimum required outward buffer size is determined by the handshake
- * protocol's usage. Handshaking will fail if the outward buffer is too small.
- * The specific size requirement depends on the configured ciphers and any
- * certificate data which is sent during the handshake.
- *
- * Uncomment to set the maximum plaintext size of the outgoing I/O buffer
- * independently of the incoming I/O buffer.
- */
-//#define MBEDTLS_SSL_OUT_CONTENT_LEN             16384
-
-/** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING
- *
- * Maximum number of heap-allocated bytes for the purpose of
- * DTLS handshake message reassembly and future message buffering.
- *
- * This should be at least 9/8 * MBEDTLSSL_IN_CONTENT_LEN
- * to account for a reassembled handshake message of maximum size,
- * together with its reassembly bitmap.
- *
- * A value of 2 * MBEDTLS_SSL_IN_CONTENT_LEN (32768 by default)
- * should be sufficient for all practical situations as it allows
- * to reassembly a large handshake message (such as a certificate)
- * while buffering multiple smaller handshake messages.
- *
- */
-//#define MBEDTLS_SSL_DTLS_MAX_BUFFERING             32768
-
-//#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME     86400 /**< Lifetime of session tickets (if enabled) */
-//#define MBEDTLS_PSK_MAX_LEN               32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */
-//#define MBEDTLS_SSL_COOKIE_TIMEOUT        60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */
-
-/**
- * Complete list of ciphersuites to use, in order of preference.
- *
- * \warning No dependency checking is done on that field! This option can only
- * be used to restrict the set of available ciphersuites. It is your
- * responsibility to make sure the needed modules are active.
- *
- * Use this to save a few hundred bytes of ROM (default ordering of all
- * available ciphersuites) and a few to a few hundred bytes of RAM.
- *
- * The value below is only an example, not the default.
- */
-//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
-
-/* X509 options */
-//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA   8   /**< Maximum number of intermediate CAs in a verification chain. */
-//#define MBEDTLS_X509_MAX_FILE_PATH_LEN     512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */
-
-/**
- * Allow SHA-1 in the default TLS configuration for certificate signing.
- * Without this build-time option, SHA-1 support must be activated explicitly
- * through mbedtls_ssl_conf_cert_profile. Turning on this option is not
- * recommended because of it is possible to generate SHA-1 collisions, however
- * this may be safe for legacy infrastructure where additional controls apply.
- *
- * \warning   SHA-1 is considered a weak message digest and its use constitutes
- *            a security risk. If possible, we recommend avoiding dependencies
- *            on it, and considering stronger message digests instead.
- *
- */
-// #define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES
-
-/**
- * Allow SHA-1 in the default TLS configuration for TLS 1.2 handshake
- * signature and ciphersuite selection. Without this build-time option, SHA-1
- * support must be activated explicitly through mbedtls_ssl_conf_sig_hashes.
- * The use of SHA-1 in TLS <= 1.1 and in HMAC-SHA-1 is always allowed by
- * default. At the time of writing, there is no practical attack on the use
- * of SHA-1 in handshake signatures, hence this option is turned on by default
- * to preserve compatibility with existing peers, but the general
- * warning applies nonetheless:
- *
- * \warning   SHA-1 is considered a weak message digest and its use constitutes
- *            a security risk. If possible, we recommend avoiding dependencies
- *            on it, and considering stronger message digests instead.
- *
- */
-#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE
-
-/**
- * Uncomment the macro to let mbed TLS use your alternate implementation of
- * mbedtls_platform_zeroize(). This replaces the default implementation in
- * platform_util.c.
- *
- * mbedtls_platform_zeroize() is a widely used function across the library to
- * zero a block of memory. The implementation is expected to be secure in the
- * sense that it has been written to prevent the compiler from removing calls
- * to mbedtls_platform_zeroize() as part of redundant code elimination
- * optimizations. However, it is difficult to guarantee that calls to
- * mbedtls_platform_zeroize() will not be optimized by the compiler as older
- * versions of the C language standards do not provide a secure implementation
- * of memset(). Therefore, MBEDTLS_PLATFORM_ZEROIZE_ALT enables users to
- * configure their own implementation of mbedtls_platform_zeroize(), for
- * example by using directives specific to their compiler, features from newer
- * C standards (e.g using memset_s() in C11) or calling a secure memset() from
- * their system (e.g explicit_bzero() in BSD).
- */
-//#define MBEDTLS_PLATFORM_ZEROIZE_ALT
-
-/**
- * Uncomment the macro to let Mbed TLS use your alternate implementation of
- * mbedtls_platform_gmtime_r(). This replaces the default implementation in
- * platform_util.c.
- *
- * gmtime() is not a thread-safe function as defined in the C standard. The
- * library will try to use safer implementations of this function, such as
- * gmtime_r() when available. However, if Mbed TLS cannot identify the target
- * system, the implementation of mbedtls_platform_gmtime_r() will default to
- * using the standard gmtime(). In this case, calls from the library to
- * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex
- * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the
- * library are also guarded with this mutex to avoid race conditions. However,
- * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will
- * unconditionally use the implementation for mbedtls_platform_gmtime_r()
- * supplied at compile time.
- */
-//#define MBEDTLS_PLATFORM_GMTIME_R_ALT
-
-/* \} name SECTION: Customisation configuration options */
-
-/* Target and application specific configurations
- *
- * Allow user to override any previous default.
- *
- */
-#if defined(MBEDTLS_USER_CONFIG_FILE)
-#include MBEDTLS_USER_CONFIG_FILE
-#endif
-
-#include "check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h b/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h
deleted file mode 100644
index 894fa17130f..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ctr_drbg.h
+++ /dev/null
@@ -1,539 +0,0 @@
-/**
- * \file ctr_drbg.h
- *
- * \brief    This file contains definitions and functions for the
- *           CTR_DRBG pseudorandom generator.
- *
- * CTR_DRBG is a standardized way of building a PRNG from a block-cipher
- * in counter mode operation, as defined in <em>NIST SP 800-90A:
- * Recommendation for Random Number Generation Using Deterministic Random
- * Bit Generators</em>.
- *
- * The Mbed TLS implementation of CTR_DRBG uses AES-256 (default) or AES-128
- * (if \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled at compile time)
- * as the underlying block cipher, with a derivation function.
- * The initial seeding grabs #MBEDTLS_CTR_DRBG_ENTROPY_LEN bytes of entropy.
- * See the documentation of mbedtls_ctr_drbg_seed() for more details.
- *
- * Based on NIST SP 800-90A §10.2.1 table 3 and NIST SP 800-57 part 1 table 2,
- * here are the security strengths achieved in typical configuration:
- * - 256 bits under the default configuration of the library, with AES-256
- *   and with #MBEDTLS_CTR_DRBG_ENTROPY_LEN set to 48 or more.
- * - 256 bits if AES-256 is used, #MBEDTLS_CTR_DRBG_ENTROPY_LEN is set
- *   to 32 or more, and the DRBG is initialized with an explicit
- *   nonce in the \c custom parameter to mbedtls_ctr_drbg_seed().
- * - 128 bits if AES-256 is used but #MBEDTLS_CTR_DRBG_ENTROPY_LEN is
- *   between 24 and 47 and the DRBG is not initialized with an explicit
- *   nonce (see mbedtls_ctr_drbg_seed()).
- * - 128 bits if AES-128 is used (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY enabled)
- *   and #MBEDTLS_CTR_DRBG_ENTROPY_LEN is set to 24 or more (which is
- *   always the case unless it is explicitly set to a different value
- *   in config.h).
- *
- * Note that the value of #MBEDTLS_CTR_DRBG_ENTROPY_LEN defaults to:
- * - \c 48 if the module \c MBEDTLS_SHA512_C is enabled and the symbol
- *   \c MBEDTLS_ENTROPY_FORCE_SHA256 is disabled at compile time.
- *   This is the default configuration of the library.
- * - \c 32 if the module \c MBEDTLS_SHA512_C is disabled at compile time.
- * - \c 32 if \c MBEDTLS_ENTROPY_FORCE_SHA256 is enabled at compile time.
- */
-/*
- *  Copyright (C) 2006-2019, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_CTR_DRBG_H
-#define MBEDTLS_CTR_DRBG_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "aes.h"
-
-#if defined(MBEDTLS_THREADING_C)
-#include "threading.h"
-#endif
-
-#define MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED        -0x0034  /**< The entropy source failed. */
-#define MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG              -0x0036  /**< The requested random buffer length is too big. */
-#define MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG                -0x0038  /**< The input (entropy + additional data) is too large. */
-#define MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR                -0x003A  /**< Read or write error in file. */
-
-#define MBEDTLS_CTR_DRBG_BLOCKSIZE          16 /**< The block size used by the cipher. */
-
-#if defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY)
-#define MBEDTLS_CTR_DRBG_KEYSIZE            16
-/**< The key size in bytes used by the cipher.
- *
- * Compile-time choice: 16 bytes (128 bits)
- * because #MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled.
- */
-#else
-#define MBEDTLS_CTR_DRBG_KEYSIZE            32
-/**< The key size in bytes used by the cipher.
- *
- * Compile-time choice: 32 bytes (256 bits)
- * because \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled.
- */
-#endif
-
-#define MBEDTLS_CTR_DRBG_KEYBITS            ( MBEDTLS_CTR_DRBG_KEYSIZE * 8 ) /**< The key size for the DRBG operation, in bits. */
-#define MBEDTLS_CTR_DRBG_SEEDLEN            ( MBEDTLS_CTR_DRBG_KEYSIZE + MBEDTLS_CTR_DRBG_BLOCKSIZE ) /**< The seed length, calculated as (counter + AES key). */
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h or define them using the compiler command
- * line.
- * \{
- */
-
-/** \def MBEDTLS_CTR_DRBG_ENTROPY_LEN
- *
- * \brief The amount of entropy used per seed by default, in bytes.
- */
-#if !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN)
-#if defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256)
-/** This is 48 bytes because the entropy module uses SHA-512
- * (\c MBEDTLS_ENTROPY_FORCE_SHA256 is disabled).
- */
-#define MBEDTLS_CTR_DRBG_ENTROPY_LEN        48
-
-#else /* defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) */
-
-/** This is 32 bytes because the entropy module uses SHA-256
- * (the SHA512 module is disabled or
- * \c MBEDTLS_ENTROPY_FORCE_SHA256 is enabled).
- */
-#if !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY)
-/** \warning To achieve a 256-bit security strength, you must pass a nonce
- *           to mbedtls_ctr_drbg_seed().
- */
-#endif /* !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) */
-#define MBEDTLS_CTR_DRBG_ENTROPY_LEN        32
-#endif /* defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) */
-#endif /* !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) */
-
-#if !defined(MBEDTLS_CTR_DRBG_RESEED_INTERVAL)
-#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL    10000
-/**< The interval before reseed is performed by default. */
-#endif
-
-#if !defined(MBEDTLS_CTR_DRBG_MAX_INPUT)
-#define MBEDTLS_CTR_DRBG_MAX_INPUT          256
-/**< The maximum number of additional input Bytes. */
-#endif
-
-#if !defined(MBEDTLS_CTR_DRBG_MAX_REQUEST)
-#define MBEDTLS_CTR_DRBG_MAX_REQUEST        1024
-/**< The maximum number of requested Bytes per call. */
-#endif
-
-#if !defined(MBEDTLS_CTR_DRBG_MAX_SEED_INPUT)
-#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT     384
-/**< The maximum size of seed or reseed buffer in bytes. */
-#endif
-
-/* \} name SECTION: Module settings */
-
-#define MBEDTLS_CTR_DRBG_PR_OFF             0
-/**< Prediction resistance is disabled. */
-#define MBEDTLS_CTR_DRBG_PR_ON              1
-/**< Prediction resistance is enabled. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          The CTR_DRBG context structure.
- */
-typedef struct mbedtls_ctr_drbg_context
-{
-    unsigned char counter[16];  /*!< The counter (V). */
-    int reseed_counter;         /*!< The reseed counter. */
-    int prediction_resistance;  /*!< This determines whether prediction
-                                     resistance is enabled, that is
-                                     whether to systematically reseed before
-                                     each random generation. */
-    size_t entropy_len;         /*!< The amount of entropy grabbed on each
-                                     seed or reseed operation. */
-    int reseed_interval;        /*!< The reseed interval. */
-
-    mbedtls_aes_context aes_ctx;        /*!< The AES context. */
-
-    /*
-     * Callbacks (Entropy)
-     */
-    int (*f_entropy)(void *, unsigned char *, size_t);
-                                /*!< The entropy callback function. */
-
-    void *p_entropy;            /*!< The context for the entropy function. */
-
-#if defined(MBEDTLS_THREADING_C)
-    mbedtls_threading_mutex_t mutex;
-#endif
-}
-mbedtls_ctr_drbg_context;
-
-/**
- * \brief               This function initializes the CTR_DRBG context,
- *                      and prepares it for mbedtls_ctr_drbg_seed()
- *                      or mbedtls_ctr_drbg_free().
- *
- * \param ctx           The CTR_DRBG context to initialize.
- */
-void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx );
-
-/**
- * \brief               This function seeds and sets up the CTR_DRBG
- *                      entropy source for future reseeds.
- *
- * A typical choice for the \p f_entropy and \p p_entropy parameters is
- * to use the entropy module:
- * - \p f_entropy is mbedtls_entropy_func();
- * - \p p_entropy is an instance of ::mbedtls_entropy_context initialized
- *   with mbedtls_entropy_init() (which registers the platform's default
- *   entropy sources).
- *
- * The entropy length is #MBEDTLS_CTR_DRBG_ENTROPY_LEN by default.
- * You can override it by calling mbedtls_ctr_drbg_set_entropy_len().
- *
- * You can provide a personalization string in addition to the
- * entropy source, to make this instantiation as unique as possible.
- *
- * \note                The _seed_material_ value passed to the derivation
- *                      function in the CTR_DRBG Instantiate Process
- *                      described in NIST SP 800-90A §10.2.1.3.2
- *                      is the concatenation of the string obtained from
- *                      calling \p f_entropy and the \p custom string.
- *                      The origin of the nonce depends on the value of
- *                      the entropy length relative to the security strength.
- *                      - If the entropy length is at least 1.5 times the
- *                        security strength then the nonce is taken from the
- *                        string obtained with \p f_entropy.
- *                      - If the entropy length is less than the security
- *                        strength, then the nonce is taken from \p custom.
- *                        In this case, for compliance with SP 800-90A,
- *                        you must pass a unique value of \p custom at
- *                        each invocation. See SP 800-90A §8.6.7 for more
- *                        details.
- */
-#if MBEDTLS_CTR_DRBG_ENTROPY_LEN < MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2
-/** \warning            When #MBEDTLS_CTR_DRBG_ENTROPY_LEN is less than
- *                      #MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2, to achieve the
- *                      maximum security strength permitted by CTR_DRBG,
- *                      you must pass a value of \p custom that is a nonce:
- *                      this value must never be repeated in subsequent
- *                      runs of the same application or on a different
- *                      device.
- */
-#endif
-/**
- * \param ctx           The CTR_DRBG context to seed.
- *                      It must have been initialized with
- *                      mbedtls_ctr_drbg_init().
- *                      After a successful call to mbedtls_ctr_drbg_seed(),
- *                      you may not call mbedtls_ctr_drbg_seed() again on
- *                      the same context unless you call
- *                      mbedtls_ctr_drbg_free() and mbedtls_ctr_drbg_init()
- *                      again first.
- * \param f_entropy     The entropy callback, taking as arguments the
- *                      \p p_entropy context, the buffer to fill, and the
- *                      length of the buffer.
- *                      \p f_entropy is always called with a buffer size
- *                      equal to the entropy length.
- * \param p_entropy     The entropy context to pass to \p f_entropy.
- * \param custom        The personalization string.
- *                      This can be \c NULL, in which case the personalization
- *                      string is empty regardless of the value of \p len.
- * \param len           The length of the personalization string.
- *                      This must be at most
- *                      #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT
- *                      - #MBEDTLS_CTR_DRBG_ENTROPY_LEN.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure.
- */
-int mbedtls_ctr_drbg_seed( mbedtls_ctr_drbg_context *ctx,
-                   int (*f_entropy)(void *, unsigned char *, size_t),
-                   void *p_entropy,
-                   const unsigned char *custom,
-                   size_t len );
-
-/**
- * \brief               This function clears CTR_CRBG context data.
- *
- * \param ctx           The CTR_DRBG context to clear.
- */
-void mbedtls_ctr_drbg_free( mbedtls_ctr_drbg_context *ctx );
-
-/**
- * \brief               This function turns prediction resistance on or off.
- *                      The default value is off.
- *
- * \note                If enabled, entropy is gathered at the beginning of
- *                      every call to mbedtls_ctr_drbg_random_with_add()
- *                      or mbedtls_ctr_drbg_random().
- *                      Only use this if your entropy source has sufficient
- *                      throughput.
- *
- * \param ctx           The CTR_DRBG context.
- * \param resistance    #MBEDTLS_CTR_DRBG_PR_ON or #MBEDTLS_CTR_DRBG_PR_OFF.
- */
-void mbedtls_ctr_drbg_set_prediction_resistance( mbedtls_ctr_drbg_context *ctx,
-                                         int resistance );
-
-/**
- * \brief               This function sets the amount of entropy grabbed on each
- *                      seed or reseed.
- *
- * The default value is #MBEDTLS_CTR_DRBG_ENTROPY_LEN.
- *
- * \note                The security strength of CTR_DRBG is bounded by the
- *                      entropy length. Thus:
- *                      - When using AES-256
- *                        (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled,
- *                        which is the default),
- *                        \p len must be at least 32 (in bytes)
- *                        to achieve a 256-bit strength.
- *                      - When using AES-128
- *                        (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled)
- *                        \p len must be at least 16 (in bytes)
- *                        to achieve a 128-bit strength.
- *
- * \param ctx           The CTR_DRBG context.
- * \param len           The amount of entropy to grab, in bytes.
- *                      This must be at most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT.
- */
-void mbedtls_ctr_drbg_set_entropy_len( mbedtls_ctr_drbg_context *ctx,
-                               size_t len );
-
-/**
- * \brief               This function sets the reseed interval.
- *
- * The reseed interval is the number of calls to mbedtls_ctr_drbg_random()
- * or mbedtls_ctr_drbg_random_with_add() after which the entropy function
- * is called again.
- *
- * The default value is #MBEDTLS_CTR_DRBG_RESEED_INTERVAL.
- *
- * \param ctx           The CTR_DRBG context.
- * \param interval      The reseed interval.
- */
-void mbedtls_ctr_drbg_set_reseed_interval( mbedtls_ctr_drbg_context *ctx,
-                                   int interval );
-
-/**
- * \brief               This function reseeds the CTR_DRBG context, that is
- *                      extracts data from the entropy source.
- *
- * \param ctx           The CTR_DRBG context.
- * \param additional    Additional data to add to the state. Can be \c NULL.
- * \param len           The length of the additional data.
- *                      This must be less than
- *                      #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len
- *                      where \c entropy_len is the entropy length
- *                      configured for the context.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure.
- */
-int mbedtls_ctr_drbg_reseed( mbedtls_ctr_drbg_context *ctx,
-                     const unsigned char *additional, size_t len );
-
-/**
- * \brief              This function updates the state of the CTR_DRBG context.
- *
- * \param ctx          The CTR_DRBG context.
- * \param additional   The data to update the state with. This must not be
- *                     \c NULL unless \p add_len is \c 0.
- * \param add_len      Length of \p additional in bytes. This must be at
- *                     most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT.
- *
- * \return             \c 0 on success.
- * \return             #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if
- *                     \p add_len is more than
- *                     #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT.
- * \return             An error from the underlying AES cipher on failure.
- */
-int mbedtls_ctr_drbg_update_ret( mbedtls_ctr_drbg_context *ctx,
-                                 const unsigned char *additional,
-                                 size_t add_len );
-
-/**
- * \brief   This function updates a CTR_DRBG instance with additional
- *          data and uses it to generate random data.
- *
- * This function automatically reseeds if the reseed counter is exceeded
- * or prediction resistance is enabled.
- *
- * \param p_rng         The CTR_DRBG context. This must be a pointer to a
- *                      #mbedtls_ctr_drbg_context structure.
- * \param output        The buffer to fill.
- * \param output_len    The length of the buffer in bytes.
- * \param additional    Additional data to update. Can be \c NULL, in which
- *                      case the additional data is empty regardless of
- *                      the value of \p add_len.
- * \param add_len       The length of the additional data
- *                      if \p additional is not \c NULL.
- *                      This must be less than #MBEDTLS_CTR_DRBG_MAX_INPUT
- *                      and less than
- *                      #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len
- *                      where \c entropy_len is the entropy length
- *                      configured for the context.
- *
- * \return    \c 0 on success.
- * \return    #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or
- *            #MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure.
- */
-int mbedtls_ctr_drbg_random_with_add( void *p_rng,
-                              unsigned char *output, size_t output_len,
-                              const unsigned char *additional, size_t add_len );
-
-/**
- * \brief   This function uses CTR_DRBG to generate random data.
- *
- * This function automatically reseeds if the reseed counter is exceeded
- * or prediction resistance is enabled.
- *
- *
- * \param p_rng         The CTR_DRBG context. This must be a pointer to a
- *                      #mbedtls_ctr_drbg_context structure.
- * \param output        The buffer to fill.
- * \param output_len    The length of the buffer in bytes.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or
- *                      #MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure.
- */
-int mbedtls_ctr_drbg_random( void *p_rng,
-                     unsigned char *output, size_t output_len );
-
-
-#if ! defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED    __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief              This function updates the state of the CTR_DRBG context.
- *
- * \deprecated         Superseded by mbedtls_ctr_drbg_update_ret()
- *                     in 2.16.0.
- *
- * \note               If \p add_len is greater than
- *                     #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT, only the first
- *                     #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT Bytes are used.
- *                     The remaining Bytes are silently discarded.
- *
- * \param ctx          The CTR_DRBG context.
- * \param additional   The data to update the state with.
- * \param add_len      Length of \p additional data.
- */
-MBEDTLS_DEPRECATED void mbedtls_ctr_drbg_update(
-    mbedtls_ctr_drbg_context *ctx,
-    const unsigned char *additional,
-    size_t add_len );
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-#if defined(MBEDTLS_FS_IO)
-/**
- * \brief               This function writes a seed file.
- *
- * \param ctx           The CTR_DRBG context.
- * \param path          The name of the file.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error.
- * \return              #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on reseed
- *                      failure.
- */
-int mbedtls_ctr_drbg_write_seed_file( mbedtls_ctr_drbg_context *ctx, const char *path );
-
-/**
- * \brief               This function reads and updates a seed file. The seed
- *                      is added to this instance.
- *
- * \param ctx           The CTR_DRBG context.
- * \param path          The name of the file.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error.
- * \return              #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on
- *                      reseed failure.
- * \return              #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if the existing
- *                      seed file is too large.
- */
-int mbedtls_ctr_drbg_update_seed_file( mbedtls_ctr_drbg_context *ctx, const char *path );
-#endif /* MBEDTLS_FS_IO */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief               The CTR_DRBG checkup routine.
- *
- * \return              \c 0 on success.
- * \return              \c 1 on failure.
- */
-int mbedtls_ctr_drbg_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-/* Internal functions (do not call directly) */
-int mbedtls_ctr_drbg_seed_entropy_len( mbedtls_ctr_drbg_context *,
-                               int (*)(void *, unsigned char *, size_t), void *,
-                               const unsigned char *, size_t, size_t );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ctr_drbg.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/debug.h b/tools/sdk/include/mbedtls/mbedtls/debug.h
deleted file mode 100644
index 11928e98183..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/debug.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/**
- * \file debug.h
- *
- * \brief Functions for controlling and providing debug output from the library.
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_DEBUG_H
-#define MBEDTLS_DEBUG_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "ssl.h"
-
-#if defined(MBEDTLS_ECP_C)
-#include "ecp.h"
-#endif
-
-#if defined(MBEDTLS_DEBUG_C)
-
-#define MBEDTLS_DEBUG_STRIP_PARENS( ... )   __VA_ARGS__
-
-#define MBEDTLS_SSL_DEBUG_MSG( level, args )                    \
-    mbedtls_debug_print_msg( ssl, level, __FILE__, __LINE__,    \
-                             MBEDTLS_DEBUG_STRIP_PARENS args )
-
-#define MBEDTLS_SSL_DEBUG_RET( level, text, ret )                \
-    mbedtls_debug_print_ret( ssl, level, __FILE__, __LINE__, text, ret )
-
-#define MBEDTLS_SSL_DEBUG_BUF( level, text, buf, len )           \
-    mbedtls_debug_print_buf( ssl, level, __FILE__, __LINE__, text, buf, len )
-
-#if defined(MBEDTLS_BIGNUM_C)
-#define MBEDTLS_SSL_DEBUG_MPI( level, text, X )                  \
-    mbedtls_debug_print_mpi( ssl, level, __FILE__, __LINE__, text, X )
-#endif
-
-#if defined(MBEDTLS_ECP_C)
-#define MBEDTLS_SSL_DEBUG_ECP( level, text, X )                  \
-    mbedtls_debug_print_ecp( ssl, level, __FILE__, __LINE__, text, X )
-#endif
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-#define MBEDTLS_SSL_DEBUG_CRT( level, text, crt )                \
-    mbedtls_debug_print_crt( ssl, level, __FILE__, __LINE__, text, crt )
-#endif
-
-#if defined(MBEDTLS_ECDH_C)
-#define MBEDTLS_SSL_DEBUG_ECDH( level, ecdh, attr )               \
-    mbedtls_debug_printf_ecdh( ssl, level, __FILE__, __LINE__, ecdh, attr )
-#endif
-
-#else /* MBEDTLS_DEBUG_C */
-
-#define MBEDTLS_SSL_DEBUG_MSG( level, args )            do { } while( 0 )
-#define MBEDTLS_SSL_DEBUG_RET( level, text, ret )       do { } while( 0 )
-#define MBEDTLS_SSL_DEBUG_BUF( level, text, buf, len )  do { } while( 0 )
-#define MBEDTLS_SSL_DEBUG_MPI( level, text, X )         do { } while( 0 )
-#define MBEDTLS_SSL_DEBUG_ECP( level, text, X )         do { } while( 0 )
-#define MBEDTLS_SSL_DEBUG_CRT( level, text, crt )       do { } while( 0 )
-#define MBEDTLS_SSL_DEBUG_ECDH( level, ecdh, attr )     do { } while( 0 )
-
-#endif /* MBEDTLS_DEBUG_C */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief   Set the threshold error level to handle globally all debug output.
- *          Debug messages that have a level over the threshold value are
- *          discarded.
- *          (Default value: 0 = No debug )
- *
- * \param threshold     theshold level of messages to filter on. Messages at a
- *                      higher level will be discarded.
- *                          - Debug levels
- *                              - 0 No debug
- *                              - 1 Error
- *                              - 2 State change
- *                              - 3 Informational
- *                              - 4 Verbose
- */
-void mbedtls_debug_set_threshold( int threshold );
-
-/**
- * \brief    Print a message to the debug output. This function is always used
- *          through the MBEDTLS_SSL_DEBUG_MSG() macro, which supplies the ssl
- *          context, file and line number parameters.
- *
- * \param ssl       SSL context
- * \param level     error level of the debug message
- * \param file      file the message has occurred in
- * \param line      line number the message has occurred at
- * \param format    format specifier, in printf format
- * \param ...       variables used by the format specifier
- *
- * \attention       This function is intended for INTERNAL usage within the
- *                  library only.
- */
-void mbedtls_debug_print_msg( const mbedtls_ssl_context *ssl, int level,
-                              const char *file, int line,
-                              const char *format, ... );
-
-/**
- * \brief   Print the return value of a function to the debug output. This
- *          function is always used through the MBEDTLS_SSL_DEBUG_RET() macro,
- *          which supplies the ssl context, file and line number parameters.
- *
- * \param ssl       SSL context
- * \param level     error level of the debug message
- * \param file      file the error has occurred in
- * \param line      line number the error has occurred in
- * \param text      the name of the function that returned the error
- * \param ret       the return code value
- *
- * \attention       This function is intended for INTERNAL usage within the
- *                  library only.
- */
-void mbedtls_debug_print_ret( const mbedtls_ssl_context *ssl, int level,
-                      const char *file, int line,
-                      const char *text, int ret );
-
-/**
- * \brief   Output a buffer of size len bytes to the debug output. This function
- *          is always used through the MBEDTLS_SSL_DEBUG_BUF() macro,
- *          which supplies the ssl context, file and line number parameters.
- *
- * \param ssl       SSL context
- * \param level     error level of the debug message
- * \param file      file the error has occurred in
- * \param line      line number the error has occurred in
- * \param text      a name or label for the buffer being dumped. Normally the
- *                  variable or buffer name
- * \param buf       the buffer to be outputted
- * \param len       length of the buffer
- *
- * \attention       This function is intended for INTERNAL usage within the
- *                  library only.
- */
-void mbedtls_debug_print_buf( const mbedtls_ssl_context *ssl, int level,
-                      const char *file, int line, const char *text,
-                      const unsigned char *buf, size_t len );
-
-#if defined(MBEDTLS_BIGNUM_C)
-/**
- * \brief   Print a MPI variable to the debug output. This function is always
- *          used through the MBEDTLS_SSL_DEBUG_MPI() macro, which supplies the
- *          ssl context, file and line number parameters.
- *
- * \param ssl       SSL context
- * \param level     error level of the debug message
- * \param file      file the error has occurred in
- * \param line      line number the error has occurred in
- * \param text      a name or label for the MPI being output. Normally the
- *                  variable name
- * \param X         the MPI variable
- *
- * \attention       This function is intended for INTERNAL usage within the
- *                  library only.
- */
-void mbedtls_debug_print_mpi( const mbedtls_ssl_context *ssl, int level,
-                      const char *file, int line,
-                      const char *text, const mbedtls_mpi *X );
-#endif
-
-#if defined(MBEDTLS_ECP_C)
-/**
- * \brief   Print an ECP point to the debug output. This function is always
- *          used through the MBEDTLS_SSL_DEBUG_ECP() macro, which supplies the
- *          ssl context, file and line number parameters.
- *
- * \param ssl       SSL context
- * \param level     error level of the debug message
- * \param file      file the error has occurred in
- * \param line      line number the error has occurred in
- * \param text      a name or label for the ECP point being output. Normally the
- *                  variable name
- * \param X         the ECP point
- *
- * \attention       This function is intended for INTERNAL usage within the
- *                  library only.
- */
-void mbedtls_debug_print_ecp( const mbedtls_ssl_context *ssl, int level,
-                      const char *file, int line,
-                      const char *text, const mbedtls_ecp_point *X );
-#endif
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-/**
- * \brief   Print a X.509 certificate structure to the debug output. This
- *          function is always used through the MBEDTLS_SSL_DEBUG_CRT() macro,
- *          which supplies the ssl context, file and line number parameters.
- *
- * \param ssl       SSL context
- * \param level     error level of the debug message
- * \param file      file the error has occurred in
- * \param line      line number the error has occurred in
- * \param text      a name or label for the certificate being output
- * \param crt       X.509 certificate structure
- *
- * \attention       This function is intended for INTERNAL usage within the
- *                  library only.
- */
-void mbedtls_debug_print_crt( const mbedtls_ssl_context *ssl, int level,
-                      const char *file, int line,
-                      const char *text, const mbedtls_x509_crt *crt );
-#endif
-
-#if defined(MBEDTLS_ECDH_C)
-typedef enum
-{
-    MBEDTLS_DEBUG_ECDH_Q,
-    MBEDTLS_DEBUG_ECDH_QP,
-    MBEDTLS_DEBUG_ECDH_Z,
-} mbedtls_debug_ecdh_attr;
-
-/**
- * \brief   Print a field of the ECDH structure in the SSL context to the debug
- *          output. This function is always used through the
- *          MBEDTLS_SSL_DEBUG_ECDH() macro, which supplies the ssl context, file
- *          and line number parameters.
- *
- * \param ssl       SSL context
- * \param level     error level of the debug message
- * \param file      file the error has occurred in
- * \param line      line number the error has occurred in
- * \param ecdh      the ECDH context
- * \param attr      the identifier of the attribute being output
- *
- * \attention       This function is intended for INTERNAL usage within the
- *                  library only.
- */
-void mbedtls_debug_printf_ecdh( const mbedtls_ssl_context *ssl, int level,
-                                const char *file, int line,
-                                const mbedtls_ecdh_context *ecdh,
-                                mbedtls_debug_ecdh_attr attr );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* debug.h */
-
diff --git a/tools/sdk/include/mbedtls/mbedtls/des.h b/tools/sdk/include/mbedtls/mbedtls/des.h
deleted file mode 100644
index 4c6441d7d94..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/des.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/**
- * \file des.h
- *
- * \brief DES block cipher
- *
- * \warning   DES is considered a weak cipher and its use constitutes a
- *            security risk. We recommend considering stronger ciphers
- *            instead.
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- *
- */
-#ifndef MBEDTLS_DES_H
-#define MBEDTLS_DES_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-#define MBEDTLS_DES_ENCRYPT     1
-#define MBEDTLS_DES_DECRYPT     0
-
-#define MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH              -0x0032  /**< The data input has an invalid length. */
-
-/* MBEDTLS_ERR_DES_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_DES_HW_ACCEL_FAILED                   -0x0033  /**< DES hardware accelerator failed. */
-
-#define MBEDTLS_DES_KEY_SIZE    8
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_DES_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          DES context structure
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-typedef struct mbedtls_des_context
-{
-    uint32_t sk[32];            /*!<  DES subkeys       */
-}
-mbedtls_des_context;
-
-/**
- * \brief          Triple-DES context structure
- */
-typedef struct mbedtls_des3_context
-{
-    uint32_t sk[96];            /*!<  3DES subkeys      */
-}
-mbedtls_des3_context;
-
-#else  /* MBEDTLS_DES_ALT */
-#include "des_alt.h"
-#endif /* MBEDTLS_DES_ALT */
-
-/**
- * \brief          Initialize DES context
- *
- * \param ctx      DES context to be initialized
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-void mbedtls_des_init( mbedtls_des_context *ctx );
-
-/**
- * \brief          Clear DES context
- *
- * \param ctx      DES context to be cleared
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-void mbedtls_des_free( mbedtls_des_context *ctx );
-
-/**
- * \brief          Initialize Triple-DES context
- *
- * \param ctx      DES3 context to be initialized
- */
-void mbedtls_des3_init( mbedtls_des3_context *ctx );
-
-/**
- * \brief          Clear Triple-DES context
- *
- * \param ctx      DES3 context to be cleared
- */
-void mbedtls_des3_free( mbedtls_des3_context *ctx );
-
-/**
- * \brief          Set key parity on the given key to odd.
- *
- *                 DES keys are 56 bits long, but each byte is padded with
- *                 a parity bit to allow verification.
- *
- * \param key      8-byte secret key
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-void mbedtls_des_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          Check that key parity on the given key is odd.
- *
- *                 DES keys are 56 bits long, but each byte is padded with
- *                 a parity bit to allow verification.
- *
- * \param key      8-byte secret key
- *
- * \return         0 is parity was ok, 1 if parity was not correct.
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          Check that key is not a weak or semi-weak DES key
- *
- * \param key      8-byte secret key
- *
- * \return         0 if no weak key was found, 1 if a weak key was identified.
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-int mbedtls_des_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          DES key schedule (56-bit, encryption)
- *
- * \param ctx      DES context to be initialized
- * \param key      8-byte secret key
- *
- * \return         0
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          DES key schedule (56-bit, decryption)
- *
- * \param ctx      DES context to be initialized
- * \param key      8-byte secret key
- *
- * \return         0
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief          Triple-DES key schedule (112-bit, encryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      16-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief          Triple-DES key schedule (112-bit, decryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      16-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief          Triple-DES key schedule (168-bit, encryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      24-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief          Triple-DES key schedule (168-bit, decryption)
- *
- * \param ctx      3DES context to be initialized
- * \param key      24-byte secret key
- *
- * \return         0
- */
-int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx,
-                      const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief          DES-ECB block encryption/decryption
- *
- * \param ctx      DES context
- * \param input    64-bit input block
- * \param output   64-bit output block
- *
- * \return         0 if successful
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx,
-                    const unsigned char input[8],
-                    unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          DES-CBC buffer encryption/decryption
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      DES context
- * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[8],
-                    const unsigned char *input,
-                    unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief          3DES-ECB block encryption/decryption
- *
- * \param ctx      3DES context
- * \param input    64-bit input block
- * \param output   64-bit output block
- *
- * \return         0 if successful
- */
-int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx,
-                     const unsigned char input[8],
-                     unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          3DES-CBC buffer encryption/decryption
- *
- * \note           Upon exit, the content of the IV is updated so that you can
- *                 call the function same function again on the following
- *                 block(s) of data and get the same result as if it was
- *                 encrypted in one call. This allows a "streaming" usage.
- *                 If on the other hand you need to retain the contents of the
- *                 IV, you should either save it manually or use the cipher
- *                 module instead.
- *
- * \param ctx      3DES context
- * \param mode     MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
- */
-int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx,
-                     int mode,
-                     size_t length,
-                     unsigned char iv[8],
-                     const unsigned char *input,
-                     unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief          Internal function for key expansion.
- *                 (Only exposed to allow overriding it,
- *                 see MBEDTLS_DES_SETKEY_ALT)
- *
- * \param SK       Round keys
- * \param key      Base key
- *
- * \warning        DES is considered a weak cipher and its use constitutes a
- *                 security risk. We recommend considering stronger ciphers
- *                 instead.
- */
-void mbedtls_des_setkey( uint32_t SK[32],
-                         const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- */
-int mbedtls_des_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* des.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/dhm.h b/tools/sdk/include/mbedtls/mbedtls/dhm.h
deleted file mode 100644
index 5c04ed19fb4..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/dhm.h
+++ /dev/null
@@ -1,1123 +0,0 @@
-/**
- * \file dhm.h
- *
- * \brief   This file contains Diffie-Hellman-Merkle (DHM) key exchange
- *          definitions and functions.
- *
- * Diffie-Hellman-Merkle (DHM) key exchange is defined in
- * <em>RFC-2631: Diffie-Hellman Key Agreement Method</em> and
- * <em>Public-Key Cryptography Standards (PKCS) #3: Diffie
- * Hellman Key Agreement Standard</em>.
- *
- * <em>RFC-3526: More Modular Exponential (MODP) Diffie-Hellman groups for
- * Internet Key Exchange (IKE)</em> defines a number of standardized
- * Diffie-Hellman groups for IKE.
- *
- * <em>RFC-5114: Additional Diffie-Hellman Groups for Use with IETF
- * Standards</em> defines a number of standardized Diffie-Hellman
- * groups that can be used.
- *
- * \warning  The security of the DHM key exchange relies on the proper choice
- *           of prime modulus - optimally, it should be a safe prime. The usage
- *           of non-safe primes both decreases the difficulty of the underlying
- *           discrete logarithm problem and can lead to small subgroup attacks
- *           leaking private exponent bits when invalid public keys are used
- *           and not detected. This is especially relevant if the same DHM
- *           parameters are reused for multiple key exchanges as in static DHM,
- *           while the criticality of small-subgroup attacks is lower for
- *           ephemeral DHM.
- *
- * \warning  For performance reasons, the code does neither perform primality
- *           nor safe primality tests, nor the expensive checks for invalid
- *           subgroups. Moreover, even if these were performed, non-standardized
- *           primes cannot be trusted because of the possibility of backdoors
- *           that can't be effectively checked for.
- *
- * \warning  Diffie-Hellman-Merkle is therefore a security risk when not using
- *           standardized primes generated using a trustworthy ("nothing up
- *           my sleeve") method, such as the RFC 3526 / 7919 primes. In the TLS
- *           protocol, DH parameters need to be negotiated, so using the default
- *           primes systematically is not always an option. If possible, use
- *           Elliptic Curve Diffie-Hellman (ECDH), which has better performance,
- *           and for which the TLS protocol mandates the use of standard
- *           parameters.
- *
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_DHM_H
-#define MBEDTLS_DHM_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-#include "bignum.h"
-
-/*
- * DHM Error codes
- */
-#define MBEDTLS_ERR_DHM_BAD_INPUT_DATA                    -0x3080  /**< Bad input parameters. */
-#define MBEDTLS_ERR_DHM_READ_PARAMS_FAILED                -0x3100  /**< Reading of the DHM parameters failed. */
-#define MBEDTLS_ERR_DHM_MAKE_PARAMS_FAILED                -0x3180  /**< Making of the DHM parameters failed. */
-#define MBEDTLS_ERR_DHM_READ_PUBLIC_FAILED                -0x3200  /**< Reading of the public values failed. */
-#define MBEDTLS_ERR_DHM_MAKE_PUBLIC_FAILED                -0x3280  /**< Making of the public value failed. */
-#define MBEDTLS_ERR_DHM_CALC_SECRET_FAILED                -0x3300  /**< Calculation of the DHM secret failed. */
-#define MBEDTLS_ERR_DHM_INVALID_FORMAT                    -0x3380  /**< The ASN.1 data is not formatted correctly. */
-#define MBEDTLS_ERR_DHM_ALLOC_FAILED                      -0x3400  /**< Allocation of memory failed. */
-#define MBEDTLS_ERR_DHM_FILE_IO_ERROR                     -0x3480  /**< Read or write of file failed. */
-
-/* MBEDTLS_ERR_DHM_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_DHM_HW_ACCEL_FAILED                   -0x3500  /**< DHM hardware accelerator failed. */
-
-#define MBEDTLS_ERR_DHM_SET_GROUP_FAILED                  -0x3580  /**< Setting the modulus and generator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_DHM_ALT)
-
-/**
- * \brief          The DHM context structure.
- */
-typedef struct mbedtls_dhm_context
-{
-    size_t len;         /*!<  The size of \p P in Bytes. */
-    mbedtls_mpi P;      /*!<  The prime modulus. */
-    mbedtls_mpi G;      /*!<  The generator. */
-    mbedtls_mpi X;      /*!<  Our secret value. */
-    mbedtls_mpi GX;     /*!<  Our public key = \c G^X mod \c P. */
-    mbedtls_mpi GY;     /*!<  The public key of the peer = \c G^Y mod \c P. */
-    mbedtls_mpi K;      /*!<  The shared secret = \c G^(XY) mod \c P. */
-    mbedtls_mpi RP;     /*!<  The cached value = \c R^2 mod \c P. */
-    mbedtls_mpi Vi;     /*!<  The blinding value. */
-    mbedtls_mpi Vf;     /*!<  The unblinding value. */
-    mbedtls_mpi pX;     /*!<  The previous \c X. */
-}
-mbedtls_dhm_context;
-
-#else /* MBEDTLS_DHM_ALT */
-#include "dhm_alt.h"
-#endif /* MBEDTLS_DHM_ALT */
-
-/**
- * \brief          This function initializes the DHM context.
- *
- * \param ctx      The DHM context to initialize.
- */
-void mbedtls_dhm_init( mbedtls_dhm_context *ctx );
-
-/**
- * \brief          This function parses the DHM parameters in a
- *                 TLS ServerKeyExchange handshake message
- *                 (DHM modulus, generator, and public key).
- *
- * \note           In a TLS handshake, this is the how the client
- *                 sets up its DHM context from the server's public
- *                 DHM key material.
- *
- * \param ctx      The DHM context to use. This must be initialized.
- * \param p        On input, *p must be the start of the input buffer.
- *                 On output, *p is updated to point to the end of the data
- *                 that has been read. On success, this is the first byte
- *                 past the end of the ServerKeyExchange parameters.
- *                 On error, this is the point at which an error has been
- *                 detected, which is usually not useful except to debug
- *                 failures.
- * \param end      The end of the input buffer.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_DHM_XXX error code on failure.
- */
-int mbedtls_dhm_read_params( mbedtls_dhm_context *ctx,
-                             unsigned char **p,
-                             const unsigned char *end );
-
-/**
- * \brief          This function generates a DHM key pair and exports its
- *                 public part together with the DHM parameters in the format
- *                 used in a TLS ServerKeyExchange handshake message.
- *
- * \note           This function assumes that the DHM parameters \c ctx->P
- *                 and \c ctx->G have already been properly set. For that, use
- *                 mbedtls_dhm_set_group() below in conjunction with
- *                 mbedtls_mpi_read_binary() and mbedtls_mpi_read_string().
- *
- * \note           In a TLS handshake, this is the how the server generates
- *                 and exports its DHM key material.
- *
- * \param ctx      The DHM context to use. This must be initialized
- *                 and have the DHM parameters set. It may or may not
- *                 already have imported the peer's public key.
- * \param x_size   The private key size in Bytes.
- * \param olen     The address at which to store the number of Bytes
- *                 written on success. This must not be \c NULL.
- * \param output   The destination buffer. This must be a writable buffer of
- *                 sufficient size to hold the reduced binary presentation of
- *                 the modulus, the generator and the public key, each wrapped
- *                 with a 2-byte length field. It is the responsibility of the
- *                 caller to ensure that enough space is available. Refer to
- *                 mbedtls_mpi_size() to computing the byte-size of an MPI.
- * \param f_rng    The RNG function. Must not be \c NULL.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be
- *                 \c NULL if \p f_rng doesn't need a context parameter.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_DHM_XXX error code on failure.
- */
-int mbedtls_dhm_make_params( mbedtls_dhm_context *ctx, int x_size,
-                     unsigned char *output, size_t *olen,
-                     int (*f_rng)(void *, unsigned char *, size_t),
-                     void *p_rng );
-
-/**
- * \brief          This function sets the prime modulus and generator.
- *
- * \note           This function can be used to set \c ctx->P, \c ctx->G
- *                 in preparation for mbedtls_dhm_make_params().
- *
- * \param ctx      The DHM context to configure. This must be initialized.
- * \param P        The MPI holding the DHM prime modulus. This must be
- *                 an initialized MPI.
- * \param G        The MPI holding the DHM generator. This must be an
- *                 initialized MPI.
- *
- * \return         \c 0 if successful.
- * \return         An \c MBEDTLS_ERR_DHM_XXX error code on failure.
- */
-int mbedtls_dhm_set_group( mbedtls_dhm_context *ctx,
-                           const mbedtls_mpi *P,
-                           const mbedtls_mpi *G );
-
-/**
- * \brief          This function imports the raw public value of the peer.
- *
- * \note           In a TLS handshake, this is the how the server imports
- *                 the Client's public DHM key.
- *
- * \param ctx      The DHM context to use. This must be initialized and have
- *                 its DHM parameters set, e.g. via mbedtls_dhm_set_group().
- *                 It may or may not already have generated its own private key.
- * \param input    The input buffer containing the \c G^Y value of the peer.
- *                 This must be a readable buffer of size \p ilen Bytes.
- * \param ilen     The size of the input buffer \p input in Bytes.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_DHM_XXX error code on failure.
- */
-int mbedtls_dhm_read_public( mbedtls_dhm_context *ctx,
-                     const unsigned char *input, size_t ilen );
-
-/**
- * \brief          This function creates a DHM key pair and exports
- *                 the raw public key in big-endian format.
- *
- * \note           The destination buffer is always fully written
- *                 so as to contain a big-endian representation of G^X mod P.
- *                 If it is larger than \c ctx->len, it is padded accordingly
- *                 with zero-bytes at the beginning.
- *
- * \param ctx      The DHM context to use. This must be initialized and
- *                 have the DHM parameters set. It may or may not already
- *                 have imported the peer's public key.
- * \param x_size   The private key size in Bytes.
- * \param output   The destination buffer. This must be a writable buffer of
- *                 size \p olen Bytes.
- * \param olen     The length of the destination buffer. This must be at least
- *                 equal to `ctx->len` (the size of \c P).
- * \param f_rng    The RNG function. This must not be \c NULL.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be \c NULL
- *                 if \p f_rng doesn't need a context argument.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_DHM_XXX error code on failure.
- */
-int mbedtls_dhm_make_public( mbedtls_dhm_context *ctx, int x_size,
-                     unsigned char *output, size_t olen,
-                     int (*f_rng)(void *, unsigned char *, size_t),
-                     void *p_rng );
-
-/**
- * \brief          This function derives and exports the shared secret
- *                 \c (G^Y)^X mod \c P.
- *
- * \note           If \p f_rng is not \c NULL, it is used to blind the input as
- *                 a countermeasure against timing attacks. Blinding is used
- *                 only if our private key \c X is re-used, and not used
- *                 otherwise. We recommend always passing a non-NULL
- *                 \p f_rng argument.
- *
- * \param ctx           The DHM context to use. This must be initialized
- *                      and have its own private key generated and the peer's
- *                      public key imported.
- * \param output        The buffer to write the generated shared key to. This
- *                      must be a writable buffer of size \p output_size Bytes.
- * \param output_size   The size of the destination buffer. This must be at
- *                      least the size of \c ctx->len (the size of \c P).
- * \param olen          On exit, holds the actual number of Bytes written.
- * \param f_rng         The RNG function, for blinding purposes. This may
- *                      b \c NULL if blinding isn't needed.
- * \param p_rng         The RNG context. This may be \c NULL if \p f_rng
- *                      doesn't need a context argument.
- *
- * \return              \c 0 on success.
- * \return              An \c MBEDTLS_ERR_DHM_XXX error code on failure.
- */
-int mbedtls_dhm_calc_secret( mbedtls_dhm_context *ctx,
-                     unsigned char *output, size_t output_size, size_t *olen,
-                     int (*f_rng)(void *, unsigned char *, size_t),
-                     void *p_rng );
-
-/**
- * \brief          This function frees and clears the components
- *                 of a DHM context.
- *
- * \param ctx      The DHM context to free and clear. This may be \c NULL,
- *                 in which case this function is a no-op. If it is not \c NULL,
- *                 it must point to an initialized DHM context.
- */
-void mbedtls_dhm_free( mbedtls_dhm_context *ctx );
-
-#if defined(MBEDTLS_ASN1_PARSE_C)
-/** \ingroup x509_module */
-/**
- * \brief             This function parses DHM parameters in PEM or DER format.
- *
- * \param dhm         The DHM context to import the DHM parameters into.
- *                    This must be initialized.
- * \param dhmin       The input buffer. This must be a readable buffer of
- *                    length \p dhminlen Bytes.
- * \param dhminlen    The size of the input buffer \p dhmin, including the
- *                    terminating \c NULL Byte for PEM data.
- *
- * \return            \c 0 on success.
- * \return            An \c MBEDTLS_ERR_DHM_XXX or \c MBEDTLS_ERR_PEM_XXX error
- *                    code on failure.
- */
-int mbedtls_dhm_parse_dhm( mbedtls_dhm_context *dhm, const unsigned char *dhmin,
-                           size_t dhminlen );
-
-#if defined(MBEDTLS_FS_IO)
-/** \ingroup x509_module */
-/**
- * \brief          This function loads and parses DHM parameters from a file.
- *
- * \param dhm      The DHM context to load the parameters to.
- *                 This must be initialized.
- * \param path     The filename to read the DHM parameters from.
- *                 This must not be \c NULL.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_DHM_XXX or \c MBEDTLS_ERR_PEM_XXX
- *                 error code on failure.
- */
-int mbedtls_dhm_parse_dhmfile( mbedtls_dhm_context *dhm, const char *path );
-#endif /* MBEDTLS_FS_IO */
-#endif /* MBEDTLS_ASN1_PARSE_C */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          The DMH checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_dhm_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * RFC 3526, RFC 5114 and RFC 7919 standardize a number of
- * Diffie-Hellman groups, some of which are included here
- * for use within the SSL/TLS module and the user's convenience
- * when configuring the Diffie-Hellman parameters by hand
- * through \c mbedtls_ssl_conf_dh_param.
- *
- * The following lists the source of the above groups in the standards:
- * - RFC 5114 section 2.2:  2048-bit MODP Group with 224-bit Prime Order Subgroup
- * - RFC 3526 section 3:    2048-bit MODP Group
- * - RFC 3526 section 4:    3072-bit MODP Group
- * - RFC 3526 section 5:    4096-bit MODP Group
- * - RFC 7919 section A.1:  ffdhe2048
- * - RFC 7919 section A.2:  ffdhe3072
- * - RFC 7919 section A.3:  ffdhe4096
- * - RFC 7919 section A.4:  ffdhe6144
- * - RFC 7919 section A.5:  ffdhe8192
- *
- * The constants with suffix "_p" denote the chosen prime moduli, while
- * the constants with suffix "_g" denote the chosen generator
- * of the associated prime field.
- *
- * The constants further suffixed with "_bin" are provided in binary format,
- * while all other constants represent null-terminated strings holding the
- * hexadecimal presentation of the respective numbers.
- *
- * The primes from RFC 3526 and RFC 7919 have been generating by the following
- * trust-worthy procedure:
- * - Fix N in { 2048, 3072, 4096, 6144, 8192 } and consider the N-bit number
- *   the first and last 64 bits are all 1, and the remaining N - 128 bits of
- *   which are 0x7ff...ff.
- * - Add the smallest multiple of the first N - 129 bits of the binary expansion
- *   of pi (for RFC 5236) or e (for RFC 7919) to this intermediate bit-string
- *   such that the resulting integer is a safe-prime.
- * - The result is the respective RFC 3526 / 7919 prime, and the corresponding
- *   generator is always chosen to be 2 (which is a square for these prime,
- *   hence the corresponding subgroup has order (p-1)/2 and avoids leaking a
- *   bit in the private exponent).
- *
- */
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-
-/**
- * \warning The origin of the primes in RFC 5114 is not documented and
- *          their use therefore constitutes a security risk!
- *
- * \deprecated The hex-encoded primes from RFC 5114 are deprecated and are
- *             likely to be removed in a future version of the library without
- *             replacement.
- */
-
-/**
- * The hexadecimal presentation of the prime underlying the
- * 2048-bit MODP Group with 224-bit Prime Order Subgroup, as defined
- * in <em>RFC-5114: Additional Diffie-Hellman Groups for Use with
- * IETF Standards</em>.
- */
-#define MBEDTLS_DHM_RFC5114_MODP_2048_P                         \
-    MBEDTLS_DEPRECATED_STRING_CONSTANT(                         \
-        "AD107E1E9123A9D0D660FAA79559C51FA20D64E5683B9FD1"      \
-        "B54B1597B61D0A75E6FA141DF95A56DBAF9A3C407BA1DF15"      \
-        "EB3D688A309C180E1DE6B85A1274A0A66D3F8152AD6AC212"      \
-        "9037C9EDEFDA4DF8D91E8FEF55B7394B7AD5B7D0B6C12207"      \
-        "C9F98D11ED34DBF6C6BA0B2C8BBC27BE6A00E0A0B9C49708"      \
-        "B3BF8A317091883681286130BC8985DB1602E714415D9330"      \
-        "278273C7DE31EFDC7310F7121FD5A07415987D9ADC0A486D"      \
-        "CDF93ACC44328387315D75E198C641A480CD86A1B9E587E8"      \
-        "BE60E69CC928B2B9C52172E413042E9B23F10B0E16E79763"      \
-        "C9B53DCF4BA80A29E3FB73C16B8E75B97EF363E2FFA31F71"      \
-        "CF9DE5384E71B81C0AC4DFFE0C10E64F" )
-
-/**
- * The hexadecimal presentation of the chosen generator of the 2048-bit MODP
- * Group with 224-bit Prime Order Subgroup, as defined in <em>RFC-5114:
- * Additional Diffie-Hellman Groups for Use with IETF Standards</em>.
- */
-#define MBEDTLS_DHM_RFC5114_MODP_2048_G                         \
-    MBEDTLS_DEPRECATED_STRING_CONSTANT(                         \
-        "AC4032EF4F2D9AE39DF30B5C8FFDAC506CDEBE7B89998CAF"      \
-        "74866A08CFE4FFE3A6824A4E10B9A6F0DD921F01A70C4AFA"      \
-        "AB739D7700C29F52C57DB17C620A8652BE5E9001A8D66AD7"      \
-        "C17669101999024AF4D027275AC1348BB8A762D0521BC98A"      \
-        "E247150422EA1ED409939D54DA7460CDB5F6C6B250717CBE"      \
-        "F180EB34118E98D119529A45D6F834566E3025E316A330EF"      \
-        "BB77A86F0C1AB15B051AE3D428C8F8ACB70A8137150B8EEB"      \
-        "10E183EDD19963DDD9E263E4770589EF6AA21E7F5F2FF381"      \
-        "B539CCE3409D13CD566AFBB48D6C019181E1BCFE94B30269"      \
-        "EDFE72FE9B6AA4BD7B5A0F1C71CFFF4C19C418E1F6EC0179"      \
-        "81BC087F2A7065B384B890D3191F2BFA" )
-
-/**
- * The hexadecimal presentation of the prime underlying the 2048-bit MODP
- * Group, as defined in <em>RFC-3526: More Modular Exponential (MODP)
- * Diffie-Hellman groups for Internet Key Exchange (IKE)</em>.
- *
- * \deprecated The hex-encoded primes from RFC 3625 are deprecated and
- *             superseded by the corresponding macros providing them as
- *             binary constants. Their hex-encoded constants are likely
- *             to be removed in a future version of the library.
- *
- */
-#define MBEDTLS_DHM_RFC3526_MODP_2048_P                         \
-    MBEDTLS_DEPRECATED_STRING_CONSTANT(                         \
-        "FFFFFFFFFFFFFFFFC90FDAA22168C234C4C6628B80DC1CD1"      \
-        "29024E088A67CC74020BBEA63B139B22514A08798E3404DD"      \
-        "EF9519B3CD3A431B302B0A6DF25F14374FE1356D6D51C245"      \
-        "E485B576625E7EC6F44C42E9A637ED6B0BFF5CB6F406B7ED"      \
-        "EE386BFB5A899FA5AE9F24117C4B1FE649286651ECE45B3D"      \
-        "C2007CB8A163BF0598DA48361C55D39A69163FA8FD24CF5F"      \
-        "83655D23DCA3AD961C62F356208552BB9ED529077096966D"      \
-        "670C354E4ABC9804F1746C08CA18217C32905E462E36CE3B"      \
-        "E39E772C180E86039B2783A2EC07A28FB5C55DF06F4C52C9"      \
-        "DE2BCBF6955817183995497CEA956AE515D2261898FA0510"      \
-        "15728E5A8AACAA68FFFFFFFFFFFFFFFF" )
-
-/**
- * The hexadecimal presentation of the chosen generator of the 2048-bit MODP
- * Group, as defined in <em>RFC-3526: More Modular Exponential (MODP)
- * Diffie-Hellman groups for Internet Key Exchange (IKE)</em>.
- */
-#define MBEDTLS_DHM_RFC3526_MODP_2048_G                         \
-    MBEDTLS_DEPRECATED_STRING_CONSTANT( "02" )
-
-/**
- * The hexadecimal presentation of the prime underlying the 3072-bit MODP
- * Group, as defined in <em>RFC-3072: More Modular Exponential (MODP)
- * Diffie-Hellman groups for Internet Key Exchange (IKE)</em>.
- */
-#define MBEDTLS_DHM_RFC3526_MODP_3072_P                         \
-    MBEDTLS_DEPRECATED_STRING_CONSTANT(                         \
-        "FFFFFFFFFFFFFFFFC90FDAA22168C234C4C6628B80DC1CD1"      \
-        "29024E088A67CC74020BBEA63B139B22514A08798E3404DD"      \
-        "EF9519B3CD3A431B302B0A6DF25F14374FE1356D6D51C245"      \
-        "E485B576625E7EC6F44C42E9A637ED6B0BFF5CB6F406B7ED"      \
-        "EE386BFB5A899FA5AE9F24117C4B1FE649286651ECE45B3D"      \
-        "C2007CB8A163BF0598DA48361C55D39A69163FA8FD24CF5F"      \
-        "83655D23DCA3AD961C62F356208552BB9ED529077096966D"      \
-        "670C354E4ABC9804F1746C08CA18217C32905E462E36CE3B"      \
-        "E39E772C180E86039B2783A2EC07A28FB5C55DF06F4C52C9"      \
-        "DE2BCBF6955817183995497CEA956AE515D2261898FA0510"      \
-        "15728E5A8AAAC42DAD33170D04507A33A85521ABDF1CBA64"      \
-        "ECFB850458DBEF0A8AEA71575D060C7DB3970F85A6E1E4C7"      \
-        "ABF5AE8CDB0933D71E8C94E04A25619DCEE3D2261AD2EE6B"      \
-        "F12FFA06D98A0864D87602733EC86A64521F2B18177B200C"      \
-        "BBE117577A615D6C770988C0BAD946E208E24FA074E5AB31"      \
-        "43DB5BFCE0FD108E4B82D120A93AD2CAFFFFFFFFFFFFFFFF" )
-
-/**
- * The hexadecimal presentation of the chosen generator of the 3072-bit MODP
- * Group, as defined in <em>RFC-3526: More Modular Exponential (MODP)
- * Diffie-Hellman groups for Internet Key Exchange (IKE)</em>.
- */
-#define MBEDTLS_DHM_RFC3526_MODP_3072_G                      \
-    MBEDTLS_DEPRECATED_STRING_CONSTANT( "02" )
-
-/**
- * The hexadecimal presentation of the prime underlying the 4096-bit MODP
- * Group, as defined in <em>RFC-3526: More Modular Exponential (MODP)
- * Diffie-Hellman groups for Internet Key Exchange (IKE)</em>.
- */
-#define MBEDTLS_DHM_RFC3526_MODP_4096_P                      \
-    MBEDTLS_DEPRECATED_STRING_CONSTANT(                      \
-        "FFFFFFFFFFFFFFFFC90FDAA22168C234C4C6628B80DC1CD1"   \
-        "29024E088A67CC74020BBEA63B139B22514A08798E3404DD"   \
-        "EF9519B3CD3A431B302B0A6DF25F14374FE1356D6D51C245"   \
-        "E485B576625E7EC6F44C42E9A637ED6B0BFF5CB6F406B7ED"   \
-        "EE386BFB5A899FA5AE9F24117C4B1FE649286651ECE45B3D"   \
-        "C2007CB8A163BF0598DA48361C55D39A69163FA8FD24CF5F"   \
-        "83655D23DCA3AD961C62F356208552BB9ED529077096966D"   \
-        "670C354E4ABC9804F1746C08CA18217C32905E462E36CE3B"   \
-        "E39E772C180E86039B2783A2EC07A28FB5C55DF06F4C52C9"   \
-        "DE2BCBF6955817183995497CEA956AE515D2261898FA0510"   \
-        "15728E5A8AAAC42DAD33170D04507A33A85521ABDF1CBA64"   \
-        "ECFB850458DBEF0A8AEA71575D060C7DB3970F85A6E1E4C7"   \
-        "ABF5AE8CDB0933D71E8C94E04A25619DCEE3D2261AD2EE6B"   \
-        "F12FFA06D98A0864D87602733EC86A64521F2B18177B200C"   \
-        "BBE117577A615D6C770988C0BAD946E208E24FA074E5AB31"   \
-        "43DB5BFCE0FD108E4B82D120A92108011A723C12A787E6D7"   \
-        "88719A10BDBA5B2699C327186AF4E23C1A946834B6150BDA"   \
-        "2583E9CA2AD44CE8DBBBC2DB04DE8EF92E8EFC141FBECAA6"   \
-        "287C59474E6BC05D99B2964FA090C3A2233BA186515BE7ED"   \
-        "1F612970CEE2D7AFB81BDD762170481CD0069127D5B05AA9"   \
-        "93B4EA988D8FDDC186FFB7DC90A6C08F4DF435C934063199"   \
-        "FFFFFFFFFFFFFFFF" )
-
-/**
- * The hexadecimal presentation of the chosen generator of the 4096-bit MODP
- * Group, as defined in <em>RFC-3526: More Modular Exponential (MODP)
- * Diffie-Hellman groups for Internet Key Exchange (IKE)</em>.
- */
-#define MBEDTLS_DHM_RFC3526_MODP_4096_G                      \
-    MBEDTLS_DEPRECATED_STRING_CONSTANT( "02" )
-
-#endif /* MBEDTLS_DEPRECATED_REMOVED */
-
-/*
- * Trustworthy DHM parameters in binary form
- */
-
-#define MBEDTLS_DHM_RFC3526_MODP_2048_P_BIN {        \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \
-     0xC9, 0x0F, 0xDA, 0xA2, 0x21, 0x68, 0xC2, 0x34, \
-     0xC4, 0xC6, 0x62, 0x8B, 0x80, 0xDC, 0x1C, 0xD1, \
-     0x29, 0x02, 0x4E, 0x08, 0x8A, 0x67, 0xCC, 0x74, \
-     0x02, 0x0B, 0xBE, 0xA6, 0x3B, 0x13, 0x9B, 0x22, \
-     0x51, 0x4A, 0x08, 0x79, 0x8E, 0x34, 0x04, 0xDD, \
-     0xEF, 0x95, 0x19, 0xB3, 0xCD, 0x3A, 0x43, 0x1B, \
-     0x30, 0x2B, 0x0A, 0x6D, 0xF2, 0x5F, 0x14, 0x37, \
-     0x4F, 0xE1, 0x35, 0x6D, 0x6D, 0x51, 0xC2, 0x45, \
-     0xE4, 0x85, 0xB5, 0x76, 0x62, 0x5E, 0x7E, 0xC6, \
-     0xF4, 0x4C, 0x42, 0xE9, 0xA6, 0x37, 0xED, 0x6B, \
-     0x0B, 0xFF, 0x5C, 0xB6, 0xF4, 0x06, 0xB7, 0xED, \
-     0xEE, 0x38, 0x6B, 0xFB, 0x5A, 0x89, 0x9F, 0xA5, \
-     0xAE, 0x9F, 0x24, 0x11, 0x7C, 0x4B, 0x1F, 0xE6, \
-     0x49, 0x28, 0x66, 0x51, 0xEC, 0xE4, 0x5B, 0x3D, \
-     0xC2, 0x00, 0x7C, 0xB8, 0xA1, 0x63, 0xBF, 0x05, \
-     0x98, 0xDA, 0x48, 0x36, 0x1C, 0x55, 0xD3, 0x9A, \
-     0x69, 0x16, 0x3F, 0xA8, 0xFD, 0x24, 0xCF, 0x5F, \
-     0x83, 0x65, 0x5D, 0x23, 0xDC, 0xA3, 0xAD, 0x96, \
-     0x1C, 0x62, 0xF3, 0x56, 0x20, 0x85, 0x52, 0xBB, \
-     0x9E, 0xD5, 0x29, 0x07, 0x70, 0x96, 0x96, 0x6D, \
-     0x67, 0x0C, 0x35, 0x4E, 0x4A, 0xBC, 0x98, 0x04, \
-     0xF1, 0x74, 0x6C, 0x08, 0xCA, 0x18, 0x21, 0x7C, \
-     0x32, 0x90, 0x5E, 0x46, 0x2E, 0x36, 0xCE, 0x3B, \
-     0xE3, 0x9E, 0x77, 0x2C, 0x18, 0x0E, 0x86, 0x03, \
-     0x9B, 0x27, 0x83, 0xA2, 0xEC, 0x07, 0xA2, 0x8F, \
-     0xB5, 0xC5, 0x5D, 0xF0, 0x6F, 0x4C, 0x52, 0xC9, \
-     0xDE, 0x2B, 0xCB, 0xF6, 0x95, 0x58, 0x17, 0x18, \
-     0x39, 0x95, 0x49, 0x7C, 0xEA, 0x95, 0x6A, 0xE5, \
-     0x15, 0xD2, 0x26, 0x18, 0x98, 0xFA, 0x05, 0x10, \
-     0x15, 0x72, 0x8E, 0x5A, 0x8A, 0xAC, 0xAA, 0x68, \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
-
-#define MBEDTLS_DHM_RFC3526_MODP_2048_G_BIN { 0x02 }
-
-#define MBEDTLS_DHM_RFC3526_MODP_3072_P_BIN {       \
-    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \
-    0xC9, 0x0F, 0xDA, 0xA2, 0x21, 0x68, 0xC2, 0x34, \
-    0xC4, 0xC6, 0x62, 0x8B, 0x80, 0xDC, 0x1C, 0xD1, \
-    0x29, 0x02, 0x4E, 0x08, 0x8A, 0x67, 0xCC, 0x74, \
-    0x02, 0x0B, 0xBE, 0xA6, 0x3B, 0x13, 0x9B, 0x22, \
-    0x51, 0x4A, 0x08, 0x79, 0x8E, 0x34, 0x04, 0xDD, \
-    0xEF, 0x95, 0x19, 0xB3, 0xCD, 0x3A, 0x43, 0x1B, \
-    0x30, 0x2B, 0x0A, 0x6D, 0xF2, 0x5F, 0x14, 0x37, \
-    0x4F, 0xE1, 0x35, 0x6D, 0x6D, 0x51, 0xC2, 0x45, \
-    0xE4, 0x85, 0xB5, 0x76, 0x62, 0x5E, 0x7E, 0xC6, \
-    0xF4, 0x4C, 0x42, 0xE9, 0xA6, 0x37, 0xED, 0x6B, \
-    0x0B, 0xFF, 0x5C, 0xB6, 0xF4, 0x06, 0xB7, 0xED, \
-    0xEE, 0x38, 0x6B, 0xFB, 0x5A, 0x89, 0x9F, 0xA5, \
-    0xAE, 0x9F, 0x24, 0x11, 0x7C, 0x4B, 0x1F, 0xE6, \
-    0x49, 0x28, 0x66, 0x51, 0xEC, 0xE4, 0x5B, 0x3D, \
-    0xC2, 0x00, 0x7C, 0xB8, 0xA1, 0x63, 0xBF, 0x05, \
-    0x98, 0xDA, 0x48, 0x36, 0x1C, 0x55, 0xD3, 0x9A, \
-    0x69, 0x16, 0x3F, 0xA8, 0xFD, 0x24, 0xCF, 0x5F, \
-    0x83, 0x65, 0x5D, 0x23, 0xDC, 0xA3, 0xAD, 0x96, \
-    0x1C, 0x62, 0xF3, 0x56, 0x20, 0x85, 0x52, 0xBB, \
-    0x9E, 0xD5, 0x29, 0x07, 0x70, 0x96, 0x96, 0x6D, \
-    0x67, 0x0C, 0x35, 0x4E, 0x4A, 0xBC, 0x98, 0x04, \
-    0xF1, 0x74, 0x6C, 0x08, 0xCA, 0x18, 0x21, 0x7C, \
-    0x32, 0x90, 0x5E, 0x46, 0x2E, 0x36, 0xCE, 0x3B, \
-    0xE3, 0x9E, 0x77, 0x2C, 0x18, 0x0E, 0x86, 0x03, \
-    0x9B, 0x27, 0x83, 0xA2, 0xEC, 0x07, 0xA2, 0x8F, \
-    0xB5, 0xC5, 0x5D, 0xF0, 0x6F, 0x4C, 0x52, 0xC9, \
-    0xDE, 0x2B, 0xCB, 0xF6, 0x95, 0x58, 0x17, 0x18, \
-    0x39, 0x95, 0x49, 0x7C, 0xEA, 0x95, 0x6A, 0xE5, \
-    0x15, 0xD2, 0x26, 0x18, 0x98, 0xFA, 0x05, 0x10, \
-    0x15, 0x72, 0x8E, 0x5A, 0x8A, 0xAA, 0xC4, 0x2D, \
-    0xAD, 0x33, 0x17, 0x0D, 0x04, 0x50, 0x7A, 0x33, \
-    0xA8, 0x55, 0x21, 0xAB, 0xDF, 0x1C, 0xBA, 0x64, \
-    0xEC, 0xFB, 0x85, 0x04, 0x58, 0xDB, 0xEF, 0x0A, \
-    0x8A, 0xEA, 0x71, 0x57, 0x5D, 0x06, 0x0C, 0x7D, \
-    0xB3, 0x97, 0x0F, 0x85, 0xA6, 0xE1, 0xE4, 0xC7, \
-    0xAB, 0xF5, 0xAE, 0x8C, 0xDB, 0x09, 0x33, 0xD7, \
-    0x1E, 0x8C, 0x94, 0xE0, 0x4A, 0x25, 0x61, 0x9D, \
-    0xCE, 0xE3, 0xD2, 0x26, 0x1A, 0xD2, 0xEE, 0x6B, \
-    0xF1, 0x2F, 0xFA, 0x06, 0xD9, 0x8A, 0x08, 0x64, \
-    0xD8, 0x76, 0x02, 0x73, 0x3E, 0xC8, 0x6A, 0x64, \
-    0x52, 0x1F, 0x2B, 0x18, 0x17, 0x7B, 0x20, 0x0C, \
-    0xBB, 0xE1, 0x17, 0x57, 0x7A, 0x61, 0x5D, 0x6C, \
-    0x77, 0x09, 0x88, 0xC0, 0xBA, 0xD9, 0x46, 0xE2, \
-    0x08, 0xE2, 0x4F, 0xA0, 0x74, 0xE5, 0xAB, 0x31, \
-    0x43, 0xDB, 0x5B, 0xFC, 0xE0, 0xFD, 0x10, 0x8E, \
-    0x4B, 0x82, 0xD1, 0x20, 0xA9, 0x3A, 0xD2, 0xCA, \
-    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
-
-#define MBEDTLS_DHM_RFC3526_MODP_3072_G_BIN { 0x02 }
-
-#define MBEDTLS_DHM_RFC3526_MODP_4096_P_BIN  {       \
-    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,  \
-    0xC9, 0x0F, 0xDA, 0xA2, 0x21, 0x68, 0xC2, 0x34,  \
-    0xC4, 0xC6, 0x62, 0x8B, 0x80, 0xDC, 0x1C, 0xD1,  \
-    0x29, 0x02, 0x4E, 0x08, 0x8A, 0x67, 0xCC, 0x74,  \
-    0x02, 0x0B, 0xBE, 0xA6, 0x3B, 0x13, 0x9B, 0x22,  \
-    0x51, 0x4A, 0x08, 0x79, 0x8E, 0x34, 0x04, 0xDD,  \
-    0xEF, 0x95, 0x19, 0xB3, 0xCD, 0x3A, 0x43, 0x1B,  \
-    0x30, 0x2B, 0x0A, 0x6D, 0xF2, 0x5F, 0x14, 0x37,  \
-    0x4F, 0xE1, 0x35, 0x6D, 0x6D, 0x51, 0xC2, 0x45,  \
-    0xE4, 0x85, 0xB5, 0x76, 0x62, 0x5E, 0x7E, 0xC6,  \
-    0xF4, 0x4C, 0x42, 0xE9, 0xA6, 0x37, 0xED, 0x6B,  \
-    0x0B, 0xFF, 0x5C, 0xB6, 0xF4, 0x06, 0xB7, 0xED,  \
-    0xEE, 0x38, 0x6B, 0xFB, 0x5A, 0x89, 0x9F, 0xA5,  \
-    0xAE, 0x9F, 0x24, 0x11, 0x7C, 0x4B, 0x1F, 0xE6,  \
-    0x49, 0x28, 0x66, 0x51, 0xEC, 0xE4, 0x5B, 0x3D,  \
-    0xC2, 0x00, 0x7C, 0xB8, 0xA1, 0x63, 0xBF, 0x05,  \
-    0x98, 0xDA, 0x48, 0x36, 0x1C, 0x55, 0xD3, 0x9A,  \
-    0x69, 0x16, 0x3F, 0xA8, 0xFD, 0x24, 0xCF, 0x5F,  \
-    0x83, 0x65, 0x5D, 0x23, 0xDC, 0xA3, 0xAD, 0x96,  \
-    0x1C, 0x62, 0xF3, 0x56, 0x20, 0x85, 0x52, 0xBB,  \
-    0x9E, 0xD5, 0x29, 0x07, 0x70, 0x96, 0x96, 0x6D,  \
-    0x67, 0x0C, 0x35, 0x4E, 0x4A, 0xBC, 0x98, 0x04,  \
-    0xF1, 0x74, 0x6C, 0x08, 0xCA, 0x18, 0x21, 0x7C,  \
-    0x32, 0x90, 0x5E, 0x46, 0x2E, 0x36, 0xCE, 0x3B,  \
-    0xE3, 0x9E, 0x77, 0x2C, 0x18, 0x0E, 0x86, 0x03,  \
-    0x9B, 0x27, 0x83, 0xA2, 0xEC, 0x07, 0xA2, 0x8F,  \
-    0xB5, 0xC5, 0x5D, 0xF0, 0x6F, 0x4C, 0x52, 0xC9,  \
-    0xDE, 0x2B, 0xCB, 0xF6, 0x95, 0x58, 0x17, 0x18,  \
-    0x39, 0x95, 0x49, 0x7C, 0xEA, 0x95, 0x6A, 0xE5,  \
-    0x15, 0xD2, 0x26, 0x18, 0x98, 0xFA, 0x05, 0x10,  \
-    0x15, 0x72, 0x8E, 0x5A, 0x8A, 0xAA, 0xC4, 0x2D,  \
-    0xAD, 0x33, 0x17, 0x0D, 0x04, 0x50, 0x7A, 0x33,  \
-    0xA8, 0x55, 0x21, 0xAB, 0xDF, 0x1C, 0xBA, 0x64,  \
-    0xEC, 0xFB, 0x85, 0x04, 0x58, 0xDB, 0xEF, 0x0A,  \
-    0x8A, 0xEA, 0x71, 0x57, 0x5D, 0x06, 0x0C, 0x7D,  \
-    0xB3, 0x97, 0x0F, 0x85, 0xA6, 0xE1, 0xE4, 0xC7,  \
-    0xAB, 0xF5, 0xAE, 0x8C, 0xDB, 0x09, 0x33, 0xD7,  \
-    0x1E, 0x8C, 0x94, 0xE0, 0x4A, 0x25, 0x61, 0x9D,  \
-    0xCE, 0xE3, 0xD2, 0x26, 0x1A, 0xD2, 0xEE, 0x6B,  \
-    0xF1, 0x2F, 0xFA, 0x06, 0xD9, 0x8A, 0x08, 0x64,  \
-    0xD8, 0x76, 0x02, 0x73, 0x3E, 0xC8, 0x6A, 0x64,  \
-    0x52, 0x1F, 0x2B, 0x18, 0x17, 0x7B, 0x20, 0x0C,  \
-    0xBB, 0xE1, 0x17, 0x57, 0x7A, 0x61, 0x5D, 0x6C,  \
-    0x77, 0x09, 0x88, 0xC0, 0xBA, 0xD9, 0x46, 0xE2,  \
-    0x08, 0xE2, 0x4F, 0xA0, 0x74, 0xE5, 0xAB, 0x31,  \
-    0x43, 0xDB, 0x5B, 0xFC, 0xE0, 0xFD, 0x10, 0x8E,  \
-    0x4B, 0x82, 0xD1, 0x20, 0xA9, 0x21, 0x08, 0x01,  \
-    0x1A, 0x72, 0x3C, 0x12, 0xA7, 0x87, 0xE6, 0xD7,  \
-    0x88, 0x71, 0x9A, 0x10, 0xBD, 0xBA, 0x5B, 0x26,  \
-    0x99, 0xC3, 0x27, 0x18, 0x6A, 0xF4, 0xE2, 0x3C,  \
-    0x1A, 0x94, 0x68, 0x34, 0xB6, 0x15, 0x0B, 0xDA,  \
-    0x25, 0x83, 0xE9, 0xCA, 0x2A, 0xD4, 0x4C, 0xE8,  \
-    0xDB, 0xBB, 0xC2, 0xDB, 0x04, 0xDE, 0x8E, 0xF9,  \
-    0x2E, 0x8E, 0xFC, 0x14, 0x1F, 0xBE, 0xCA, 0xA6,  \
-    0x28, 0x7C, 0x59, 0x47, 0x4E, 0x6B, 0xC0, 0x5D,  \
-    0x99, 0xB2, 0x96, 0x4F, 0xA0, 0x90, 0xC3, 0xA2,  \
-    0x23, 0x3B, 0xA1, 0x86, 0x51, 0x5B, 0xE7, 0xED,  \
-    0x1F, 0x61, 0x29, 0x70, 0xCE, 0xE2, 0xD7, 0xAF,  \
-    0xB8, 0x1B, 0xDD, 0x76, 0x21, 0x70, 0x48, 0x1C,  \
-    0xD0, 0x06, 0x91, 0x27, 0xD5, 0xB0, 0x5A, 0xA9,  \
-    0x93, 0xB4, 0xEA, 0x98, 0x8D, 0x8F, 0xDD, 0xC1,  \
-    0x86, 0xFF, 0xB7, 0xDC, 0x90, 0xA6, 0xC0, 0x8F,  \
-    0x4D, 0xF4, 0x35, 0xC9, 0x34, 0x06, 0x31, 0x99,  \
-    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
-
-#define MBEDTLS_DHM_RFC3526_MODP_4096_G_BIN { 0x02 }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE2048_P_BIN {        \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \
-     0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \
-     0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \
-     0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \
-     0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \
-     0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \
-     0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \
-     0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \
-     0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \
-     0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \
-     0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \
-     0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \
-     0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \
-     0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \
-     0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \
-     0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \
-     0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \
-     0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \
-     0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \
-     0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \
-     0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \
-     0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \
-     0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \
-     0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \
-     0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \
-     0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \
-     0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \
-     0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \
-     0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \
-     0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \
-     0x88, 0x6B, 0x42, 0x38, 0x61, 0x28, 0x5C, 0x97, \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE2048_G_BIN { 0x02 }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE3072_P_BIN { \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \
-     0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \
-     0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \
-     0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \
-     0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \
-     0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \
-     0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \
-     0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \
-     0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \
-     0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \
-     0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \
-     0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \
-     0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \
-     0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \
-     0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \
-     0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \
-     0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \
-     0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \
-     0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \
-     0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \
-     0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \
-     0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \
-     0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \
-     0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \
-     0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \
-     0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \
-     0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \
-     0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \
-     0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \
-     0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \
-     0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \
-     0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \
-     0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \
-     0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \
-     0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \
-     0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \
-     0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \
-     0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \
-     0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \
-     0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \
-     0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \
-     0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \
-     0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \
-     0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \
-     0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \
-     0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \
-     0x25, 0xE4, 0x1D, 0x2B, 0x66, 0xC6, 0x2E, 0x37, \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE3072_G_BIN { 0x02 }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE4096_P_BIN {        \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \
-     0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \
-     0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \
-     0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \
-     0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \
-     0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \
-     0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \
-     0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \
-     0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \
-     0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \
-     0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \
-     0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \
-     0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \
-     0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \
-     0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \
-     0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \
-     0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \
-     0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \
-     0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \
-     0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \
-     0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \
-     0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \
-     0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \
-     0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \
-     0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \
-     0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \
-     0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \
-     0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \
-     0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \
-     0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \
-     0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \
-     0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \
-     0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \
-     0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \
-     0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \
-     0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \
-     0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \
-     0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \
-     0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \
-     0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \
-     0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \
-     0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \
-     0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \
-     0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \
-     0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \
-     0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \
-     0x25, 0xE4, 0x1D, 0x2B, 0x66, 0x9E, 0x1E, 0xF1, \
-     0x6E, 0x6F, 0x52, 0xC3, 0x16, 0x4D, 0xF4, 0xFB, \
-     0x79, 0x30, 0xE9, 0xE4, 0xE5, 0x88, 0x57, 0xB6, \
-     0xAC, 0x7D, 0x5F, 0x42, 0xD6, 0x9F, 0x6D, 0x18, \
-     0x77, 0x63, 0xCF, 0x1D, 0x55, 0x03, 0x40, 0x04, \
-     0x87, 0xF5, 0x5B, 0xA5, 0x7E, 0x31, 0xCC, 0x7A, \
-     0x71, 0x35, 0xC8, 0x86, 0xEF, 0xB4, 0x31, 0x8A, \
-     0xED, 0x6A, 0x1E, 0x01, 0x2D, 0x9E, 0x68, 0x32, \
-     0xA9, 0x07, 0x60, 0x0A, 0x91, 0x81, 0x30, 0xC4, \
-     0x6D, 0xC7, 0x78, 0xF9, 0x71, 0xAD, 0x00, 0x38, \
-     0x09, 0x29, 0x99, 0xA3, 0x33, 0xCB, 0x8B, 0x7A, \
-     0x1A, 0x1D, 0xB9, 0x3D, 0x71, 0x40, 0x00, 0x3C, \
-     0x2A, 0x4E, 0xCE, 0xA9, 0xF9, 0x8D, 0x0A, 0xCC, \
-     0x0A, 0x82, 0x91, 0xCD, 0xCE, 0xC9, 0x7D, 0xCF, \
-     0x8E, 0xC9, 0xB5, 0x5A, 0x7F, 0x88, 0xA4, 0x6B, \
-     0x4D, 0xB5, 0xA8, 0x51, 0xF4, 0x41, 0x82, 0xE1, \
-     0xC6, 0x8A, 0x00, 0x7E, 0x5E, 0x65, 0x5F, 0x6A, \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE4096_G_BIN { 0x02 }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE6144_P_BIN {        \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \
-     0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \
-     0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \
-     0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \
-     0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \
-     0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \
-     0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \
-     0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \
-     0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \
-     0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \
-     0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \
-     0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \
-     0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \
-     0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \
-     0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \
-     0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \
-     0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \
-     0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \
-     0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \
-     0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \
-     0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \
-     0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \
-     0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \
-     0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \
-     0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \
-     0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \
-     0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \
-     0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \
-     0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \
-     0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \
-     0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \
-     0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \
-     0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \
-     0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \
-     0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \
-     0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \
-     0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \
-     0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \
-     0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \
-     0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \
-     0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \
-     0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \
-     0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \
-     0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \
-     0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \
-     0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \
-     0x25, 0xE4, 0x1D, 0x2B, 0x66, 0x9E, 0x1E, 0xF1, \
-     0x6E, 0x6F, 0x52, 0xC3, 0x16, 0x4D, 0xF4, 0xFB, \
-     0x79, 0x30, 0xE9, 0xE4, 0xE5, 0x88, 0x57, 0xB6, \
-     0xAC, 0x7D, 0x5F, 0x42, 0xD6, 0x9F, 0x6D, 0x18, \
-     0x77, 0x63, 0xCF, 0x1D, 0x55, 0x03, 0x40, 0x04, \
-     0x87, 0xF5, 0x5B, 0xA5, 0x7E, 0x31, 0xCC, 0x7A, \
-     0x71, 0x35, 0xC8, 0x86, 0xEF, 0xB4, 0x31, 0x8A, \
-     0xED, 0x6A, 0x1E, 0x01, 0x2D, 0x9E, 0x68, 0x32, \
-     0xA9, 0x07, 0x60, 0x0A, 0x91, 0x81, 0x30, 0xC4, \
-     0x6D, 0xC7, 0x78, 0xF9, 0x71, 0xAD, 0x00, 0x38, \
-     0x09, 0x29, 0x99, 0xA3, 0x33, 0xCB, 0x8B, 0x7A, \
-     0x1A, 0x1D, 0xB9, 0x3D, 0x71, 0x40, 0x00, 0x3C, \
-     0x2A, 0x4E, 0xCE, 0xA9, 0xF9, 0x8D, 0x0A, 0xCC, \
-     0x0A, 0x82, 0x91, 0xCD, 0xCE, 0xC9, 0x7D, 0xCF, \
-     0x8E, 0xC9, 0xB5, 0x5A, 0x7F, 0x88, 0xA4, 0x6B, \
-     0x4D, 0xB5, 0xA8, 0x51, 0xF4, 0x41, 0x82, 0xE1, \
-     0xC6, 0x8A, 0x00, 0x7E, 0x5E, 0x0D, 0xD9, 0x02, \
-     0x0B, 0xFD, 0x64, 0xB6, 0x45, 0x03, 0x6C, 0x7A, \
-     0x4E, 0x67, 0x7D, 0x2C, 0x38, 0x53, 0x2A, 0x3A, \
-     0x23, 0xBA, 0x44, 0x42, 0xCA, 0xF5, 0x3E, 0xA6, \
-     0x3B, 0xB4, 0x54, 0x32, 0x9B, 0x76, 0x24, 0xC8, \
-     0x91, 0x7B, 0xDD, 0x64, 0xB1, 0xC0, 0xFD, 0x4C, \
-     0xB3, 0x8E, 0x8C, 0x33, 0x4C, 0x70, 0x1C, 0x3A, \
-     0xCD, 0xAD, 0x06, 0x57, 0xFC, 0xCF, 0xEC, 0x71, \
-     0x9B, 0x1F, 0x5C, 0x3E, 0x4E, 0x46, 0x04, 0x1F, \
-     0x38, 0x81, 0x47, 0xFB, 0x4C, 0xFD, 0xB4, 0x77, \
-     0xA5, 0x24, 0x71, 0xF7, 0xA9, 0xA9, 0x69, 0x10, \
-     0xB8, 0x55, 0x32, 0x2E, 0xDB, 0x63, 0x40, 0xD8, \
-     0xA0, 0x0E, 0xF0, 0x92, 0x35, 0x05, 0x11, 0xE3, \
-     0x0A, 0xBE, 0xC1, 0xFF, 0xF9, 0xE3, 0xA2, 0x6E, \
-     0x7F, 0xB2, 0x9F, 0x8C, 0x18, 0x30, 0x23, 0xC3, \
-     0x58, 0x7E, 0x38, 0xDA, 0x00, 0x77, 0xD9, 0xB4, \
-     0x76, 0x3E, 0x4E, 0x4B, 0x94, 0xB2, 0xBB, 0xC1, \
-     0x94, 0xC6, 0x65, 0x1E, 0x77, 0xCA, 0xF9, 0x92, \
-     0xEE, 0xAA, 0xC0, 0x23, 0x2A, 0x28, 0x1B, 0xF6, \
-     0xB3, 0xA7, 0x39, 0xC1, 0x22, 0x61, 0x16, 0x82, \
-     0x0A, 0xE8, 0xDB, 0x58, 0x47, 0xA6, 0x7C, 0xBE, \
-     0xF9, 0xC9, 0x09, 0x1B, 0x46, 0x2D, 0x53, 0x8C, \
-     0xD7, 0x2B, 0x03, 0x74, 0x6A, 0xE7, 0x7F, 0x5E, \
-     0x62, 0x29, 0x2C, 0x31, 0x15, 0x62, 0xA8, 0x46, \
-     0x50, 0x5D, 0xC8, 0x2D, 0xB8, 0x54, 0x33, 0x8A, \
-     0xE4, 0x9F, 0x52, 0x35, 0xC9, 0x5B, 0x91, 0x17, \
-     0x8C, 0xCF, 0x2D, 0xD5, 0xCA, 0xCE, 0xF4, 0x03, \
-     0xEC, 0x9D, 0x18, 0x10, 0xC6, 0x27, 0x2B, 0x04, \
-     0x5B, 0x3B, 0x71, 0xF9, 0xDC, 0x6B, 0x80, 0xD6, \
-     0x3F, 0xDD, 0x4A, 0x8E, 0x9A, 0xDB, 0x1E, 0x69, \
-     0x62, 0xA6, 0x95, 0x26, 0xD4, 0x31, 0x61, 0xC1, \
-     0xA4, 0x1D, 0x57, 0x0D, 0x79, 0x38, 0xDA, 0xD4, \
-     0xA4, 0x0E, 0x32, 0x9C, 0xD0, 0xE4, 0x0E, 0x65, \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE6144_G_BIN { 0x02 }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE8192_P_BIN {        \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \
-     0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \
-     0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \
-     0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \
-     0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \
-     0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \
-     0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \
-     0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \
-     0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \
-     0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \
-     0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \
-     0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \
-     0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \
-     0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \
-     0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \
-     0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \
-     0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \
-     0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \
-     0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \
-     0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \
-     0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \
-     0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \
-     0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \
-     0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \
-     0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \
-     0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \
-     0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \
-     0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \
-     0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \
-     0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \
-     0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \
-     0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \
-     0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \
-     0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \
-     0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \
-     0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \
-     0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \
-     0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \
-     0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \
-     0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \
-     0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \
-     0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \
-     0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \
-     0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \
-     0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \
-     0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \
-     0x25, 0xE4, 0x1D, 0x2B, 0x66, 0x9E, 0x1E, 0xF1, \
-     0x6E, 0x6F, 0x52, 0xC3, 0x16, 0x4D, 0xF4, 0xFB, \
-     0x79, 0x30, 0xE9, 0xE4, 0xE5, 0x88, 0x57, 0xB6, \
-     0xAC, 0x7D, 0x5F, 0x42, 0xD6, 0x9F, 0x6D, 0x18, \
-     0x77, 0x63, 0xCF, 0x1D, 0x55, 0x03, 0x40, 0x04, \
-     0x87, 0xF5, 0x5B, 0xA5, 0x7E, 0x31, 0xCC, 0x7A, \
-     0x71, 0x35, 0xC8, 0x86, 0xEF, 0xB4, 0x31, 0x8A, \
-     0xED, 0x6A, 0x1E, 0x01, 0x2D, 0x9E, 0x68, 0x32, \
-     0xA9, 0x07, 0x60, 0x0A, 0x91, 0x81, 0x30, 0xC4, \
-     0x6D, 0xC7, 0x78, 0xF9, 0x71, 0xAD, 0x00, 0x38, \
-     0x09, 0x29, 0x99, 0xA3, 0x33, 0xCB, 0x8B, 0x7A, \
-     0x1A, 0x1D, 0xB9, 0x3D, 0x71, 0x40, 0x00, 0x3C, \
-     0x2A, 0x4E, 0xCE, 0xA9, 0xF9, 0x8D, 0x0A, 0xCC, \
-     0x0A, 0x82, 0x91, 0xCD, 0xCE, 0xC9, 0x7D, 0xCF, \
-     0x8E, 0xC9, 0xB5, 0x5A, 0x7F, 0x88, 0xA4, 0x6B, \
-     0x4D, 0xB5, 0xA8, 0x51, 0xF4, 0x41, 0x82, 0xE1, \
-     0xC6, 0x8A, 0x00, 0x7E, 0x5E, 0x0D, 0xD9, 0x02, \
-     0x0B, 0xFD, 0x64, 0xB6, 0x45, 0x03, 0x6C, 0x7A, \
-     0x4E, 0x67, 0x7D, 0x2C, 0x38, 0x53, 0x2A, 0x3A, \
-     0x23, 0xBA, 0x44, 0x42, 0xCA, 0xF5, 0x3E, 0xA6, \
-     0x3B, 0xB4, 0x54, 0x32, 0x9B, 0x76, 0x24, 0xC8, \
-     0x91, 0x7B, 0xDD, 0x64, 0xB1, 0xC0, 0xFD, 0x4C, \
-     0xB3, 0x8E, 0x8C, 0x33, 0x4C, 0x70, 0x1C, 0x3A, \
-     0xCD, 0xAD, 0x06, 0x57, 0xFC, 0xCF, 0xEC, 0x71, \
-     0x9B, 0x1F, 0x5C, 0x3E, 0x4E, 0x46, 0x04, 0x1F, \
-     0x38, 0x81, 0x47, 0xFB, 0x4C, 0xFD, 0xB4, 0x77, \
-     0xA5, 0x24, 0x71, 0xF7, 0xA9, 0xA9, 0x69, 0x10, \
-     0xB8, 0x55, 0x32, 0x2E, 0xDB, 0x63, 0x40, 0xD8, \
-     0xA0, 0x0E, 0xF0, 0x92, 0x35, 0x05, 0x11, 0xE3, \
-     0x0A, 0xBE, 0xC1, 0xFF, 0xF9, 0xE3, 0xA2, 0x6E, \
-     0x7F, 0xB2, 0x9F, 0x8C, 0x18, 0x30, 0x23, 0xC3, \
-     0x58, 0x7E, 0x38, 0xDA, 0x00, 0x77, 0xD9, 0xB4, \
-     0x76, 0x3E, 0x4E, 0x4B, 0x94, 0xB2, 0xBB, 0xC1, \
-     0x94, 0xC6, 0x65, 0x1E, 0x77, 0xCA, 0xF9, 0x92, \
-     0xEE, 0xAA, 0xC0, 0x23, 0x2A, 0x28, 0x1B, 0xF6, \
-     0xB3, 0xA7, 0x39, 0xC1, 0x22, 0x61, 0x16, 0x82, \
-     0x0A, 0xE8, 0xDB, 0x58, 0x47, 0xA6, 0x7C, 0xBE, \
-     0xF9, 0xC9, 0x09, 0x1B, 0x46, 0x2D, 0x53, 0x8C, \
-     0xD7, 0x2B, 0x03, 0x74, 0x6A, 0xE7, 0x7F, 0x5E, \
-     0x62, 0x29, 0x2C, 0x31, 0x15, 0x62, 0xA8, 0x46, \
-     0x50, 0x5D, 0xC8, 0x2D, 0xB8, 0x54, 0x33, 0x8A, \
-     0xE4, 0x9F, 0x52, 0x35, 0xC9, 0x5B, 0x91, 0x17, \
-     0x8C, 0xCF, 0x2D, 0xD5, 0xCA, 0xCE, 0xF4, 0x03, \
-     0xEC, 0x9D, 0x18, 0x10, 0xC6, 0x27, 0x2B, 0x04, \
-     0x5B, 0x3B, 0x71, 0xF9, 0xDC, 0x6B, 0x80, 0xD6, \
-     0x3F, 0xDD, 0x4A, 0x8E, 0x9A, 0xDB, 0x1E, 0x69, \
-     0x62, 0xA6, 0x95, 0x26, 0xD4, 0x31, 0x61, 0xC1, \
-     0xA4, 0x1D, 0x57, 0x0D, 0x79, 0x38, 0xDA, 0xD4, \
-     0xA4, 0x0E, 0x32, 0x9C, 0xCF, 0xF4, 0x6A, 0xAA, \
-     0x36, 0xAD, 0x00, 0x4C, 0xF6, 0x00, 0xC8, 0x38, \
-     0x1E, 0x42, 0x5A, 0x31, 0xD9, 0x51, 0xAE, 0x64, \
-     0xFD, 0xB2, 0x3F, 0xCE, 0xC9, 0x50, 0x9D, 0x43, \
-     0x68, 0x7F, 0xEB, 0x69, 0xED, 0xD1, 0xCC, 0x5E, \
-     0x0B, 0x8C, 0xC3, 0xBD, 0xF6, 0x4B, 0x10, 0xEF, \
-     0x86, 0xB6, 0x31, 0x42, 0xA3, 0xAB, 0x88, 0x29, \
-     0x55, 0x5B, 0x2F, 0x74, 0x7C, 0x93, 0x26, 0x65, \
-     0xCB, 0x2C, 0x0F, 0x1C, 0xC0, 0x1B, 0xD7, 0x02, \
-     0x29, 0x38, 0x88, 0x39, 0xD2, 0xAF, 0x05, 0xE4, \
-     0x54, 0x50, 0x4A, 0xC7, 0x8B, 0x75, 0x82, 0x82, \
-     0x28, 0x46, 0xC0, 0xBA, 0x35, 0xC3, 0x5F, 0x5C, \
-     0x59, 0x16, 0x0C, 0xC0, 0x46, 0xFD, 0x82, 0x51, \
-     0x54, 0x1F, 0xC6, 0x8C, 0x9C, 0x86, 0xB0, 0x22, \
-     0xBB, 0x70, 0x99, 0x87, 0x6A, 0x46, 0x0E, 0x74, \
-     0x51, 0xA8, 0xA9, 0x31, 0x09, 0x70, 0x3F, 0xEE, \
-     0x1C, 0x21, 0x7E, 0x6C, 0x38, 0x26, 0xE5, 0x2C, \
-     0x51, 0xAA, 0x69, 0x1E, 0x0E, 0x42, 0x3C, 0xFC, \
-     0x99, 0xE9, 0xE3, 0x16, 0x50, 0xC1, 0x21, 0x7B, \
-     0x62, 0x48, 0x16, 0xCD, 0xAD, 0x9A, 0x95, 0xF9, \
-     0xD5, 0xB8, 0x01, 0x94, 0x88, 0xD9, 0xC0, 0xA0, \
-     0xA1, 0xFE, 0x30, 0x75, 0xA5, 0x77, 0xE2, 0x31, \
-     0x83, 0xF8, 0x1D, 0x4A, 0x3F, 0x2F, 0xA4, 0x57, \
-     0x1E, 0xFC, 0x8C, 0xE0, 0xBA, 0x8A, 0x4F, 0xE8, \
-     0xB6, 0x85, 0x5D, 0xFE, 0x72, 0xB0, 0xA6, 0x6E, \
-     0xDE, 0xD2, 0xFB, 0xAB, 0xFB, 0xE5, 0x8A, 0x30, \
-     0xFA, 0xFA, 0xBE, 0x1C, 0x5D, 0x71, 0xA8, 0x7E, \
-     0x2F, 0x74, 0x1E, 0xF8, 0xC1, 0xFE, 0x86, 0xFE, \
-     0xA6, 0xBB, 0xFD, 0xE5, 0x30, 0x67, 0x7F, 0x0D, \
-     0x97, 0xD1, 0x1D, 0x49, 0xF7, 0xA8, 0x44, 0x3D, \
-     0x08, 0x22, 0xE5, 0x06, 0xA9, 0xF4, 0x61, 0x4E, \
-     0x01, 0x1E, 0x2A, 0x94, 0x83, 0x8F, 0xF8, 0x8C, \
-     0xD6, 0x8C, 0x8B, 0xB7, 0xC5, 0xC6, 0x42, 0x4C, \
-     0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
-
-#define MBEDTLS_DHM_RFC7919_FFDHE8192_G_BIN { 0x02 }
-
-#endif /* dhm.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ecdh.h b/tools/sdk/include/mbedtls/mbedtls/ecdh.h
deleted file mode 100644
index a0052df4719..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ecdh.h
+++ /dev/null
@@ -1,467 +0,0 @@
-/**
- * \file ecdh.h
- *
- * \brief This file contains ECDH definitions and functions.
- *
- * The Elliptic Curve Diffie-Hellman (ECDH) protocol is an anonymous
- * key agreement protocol allowing two parties to establish a shared
- * secret over an insecure channel. Each party must have an
- * elliptic-curve public–private key pair.
- *
- * For more information, see <em>NIST SP 800-56A Rev. 2: Recommendation for
- * Pair-Wise Key Establishment Schemes Using Discrete Logarithm
- * Cryptography</em>.
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_ECDH_H
-#define MBEDTLS_ECDH_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "ecp.h"
-
-/*
- * Use a backward compatible ECDH context.
- *
- * This flag is always enabled for now and future versions might add a
- * configuration option that conditionally undefines this flag.
- * The configuration option in question may have a different name.
- *
- * Features undefining this flag, must have a warning in their description in
- * config.h stating that the feature breaks backward compatibility.
- */
-#define MBEDTLS_ECDH_LEGACY_CONTEXT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Defines the source of the imported EC key.
- */
-typedef enum
-{
-    MBEDTLS_ECDH_OURS,   /**< Our key. */
-    MBEDTLS_ECDH_THEIRS, /**< The key of the peer. */
-} mbedtls_ecdh_side;
-
-#if !defined(MBEDTLS_ECDH_LEGACY_CONTEXT)
-/**
- * Defines the ECDH implementation used.
- *
- * Later versions of the library may add new variants, therefore users should
- * not make any assumptions about them.
- */
-typedef enum
-{
-    MBEDTLS_ECDH_VARIANT_NONE = 0,   /*!< Implementation not defined. */
-    MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0,/*!< The default Mbed TLS implementation */
-} mbedtls_ecdh_variant;
-
-/**
- * The context used by the default ECDH implementation.
- *
- * Later versions might change the structure of this context, therefore users
- * should not make any assumptions about the structure of
- * mbedtls_ecdh_context_mbed.
- */
-typedef struct mbedtls_ecdh_context_mbed
-{
-    mbedtls_ecp_group grp;   /*!< The elliptic curve used. */
-    mbedtls_mpi d;           /*!< The private key. */
-    mbedtls_ecp_point Q;     /*!< The public key. */
-    mbedtls_ecp_point Qp;    /*!< The value of the public key of the peer. */
-    mbedtls_mpi z;           /*!< The shared secret. */
-#if defined(MBEDTLS_ECP_RESTARTABLE)
-    mbedtls_ecp_restart_ctx rs; /*!< The restart context for EC computations. */
-#endif
-} mbedtls_ecdh_context_mbed;
-#endif
-
-/**
- *
- * \warning         Performing multiple operations concurrently on the same
- *                  ECDSA context is not supported; objects of this type
- *                  should not be shared between multiple threads.
- * \brief           The ECDH context structure.
- */
-typedef struct mbedtls_ecdh_context
-{
-#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT)
-    mbedtls_ecp_group grp;   /*!< The elliptic curve used. */
-    mbedtls_mpi d;           /*!< The private key. */
-    mbedtls_ecp_point Q;     /*!< The public key. */
-    mbedtls_ecp_point Qp;    /*!< The value of the public key of the peer. */
-    mbedtls_mpi z;           /*!< The shared secret. */
-    int point_format;        /*!< The format of point export in TLS messages. */
-    mbedtls_ecp_point Vi;    /*!< The blinding value. */
-    mbedtls_ecp_point Vf;    /*!< The unblinding value. */
-    mbedtls_mpi _d;          /*!< The previous \p d. */
-#if defined(MBEDTLS_ECP_RESTARTABLE)
-    int restart_enabled;        /*!< The flag for restartable mode. */
-    mbedtls_ecp_restart_ctx rs; /*!< The restart context for EC computations. */
-#endif /* MBEDTLS_ECP_RESTARTABLE */
-#else
-    uint8_t point_format;       /*!< The format of point export in TLS messages
-                                  as defined in RFC 4492. */
-    mbedtls_ecp_group_id grp_id;/*!< The elliptic curve used. */
-    mbedtls_ecdh_variant var;   /*!< The ECDH implementation/structure used. */
-    union
-    {
-        mbedtls_ecdh_context_mbed   mbed_ecdh;
-    } ctx;                      /*!< Implementation-specific context. The
-                                  context in use is specified by the \c var
-                                  field. */
-#if defined(MBEDTLS_ECP_RESTARTABLE)
-    uint8_t restart_enabled;    /*!< The flag for restartable mode. Functions of
-                                  an alternative implementation not supporting
-                                  restartable mode must return
-                                  MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED error
-                                  if this flag is set. */
-#endif /* MBEDTLS_ECP_RESTARTABLE */
-#endif /* MBEDTLS_ECDH_LEGACY_CONTEXT */
-}
-mbedtls_ecdh_context;
-
-/**
- * \brief           This function generates an ECDH keypair on an elliptic
- *                  curve.
- *
- *                  This function performs the first of two core computations
- *                  implemented during the ECDH key exchange. The second core
- *                  computation is performed by mbedtls_ecdh_compute_shared().
- *
- * \see             ecp.h
- *
- * \param grp       The ECP group to use. This must be initialized and have
- *                  domain parameters loaded, for example through
- *                  mbedtls_ecp_load() or mbedtls_ecp_tls_read_group().
- * \param d         The destination MPI (private key).
- *                  This must be initialized.
- * \param Q         The destination point (public key).
- *                  This must be initialized.
- * \param f_rng     The RNG function to use. This must not be \c NULL.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may be
- *                  \c NULL in case \p f_rng doesn't need a context argument.
- *
- * \return          \c 0 on success.
- * \return          Another \c MBEDTLS_ERR_ECP_XXX or
- *                  \c MBEDTLS_MPI_XXX error code on failure.
- */
-int mbedtls_ecdh_gen_public( mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q,
-                     int (*f_rng)(void *, unsigned char *, size_t),
-                     void *p_rng );
-
-/**
- * \brief           This function computes the shared secret.
- *
- *                  This function performs the second of two core computations
- *                  implemented during the ECDH key exchange. The first core
- *                  computation is performed by mbedtls_ecdh_gen_public().
- *
- * \see             ecp.h
- *
- * \note            If \p f_rng is not NULL, it is used to implement
- *                  countermeasures against side-channel attacks.
- *                  For more information, see mbedtls_ecp_mul().
- *
- * \param grp       The ECP group to use. This must be initialized and have
- *                  domain parameters loaded, for example through
- *                  mbedtls_ecp_load() or mbedtls_ecp_tls_read_group().
- * \param z         The destination MPI (shared secret).
- *                  This must be initialized.
- * \param Q         The public key from another party.
- *                  This must be initialized.
- * \param d         Our secret exponent (private key).
- *                  This must be initialized.
- * \param f_rng     The RNG function. This may be \c NULL if randomization
- *                  of intermediate results during the ECP computations is
- *                  not needed (discouraged). See the documentation of
- *                  mbedtls_ecp_mul() for more.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may be
- *                  \c NULL if \p f_rng is \c NULL or doesn't need a
- *                  context argument.
- *
- * \return          \c 0 on success.
- * \return          Another \c MBEDTLS_ERR_ECP_XXX or
- *                  \c MBEDTLS_MPI_XXX error code on failure.
- */
-int mbedtls_ecdh_compute_shared( mbedtls_ecp_group *grp, mbedtls_mpi *z,
-                         const mbedtls_ecp_point *Q, const mbedtls_mpi *d,
-                         int (*f_rng)(void *, unsigned char *, size_t),
-                         void *p_rng );
-
-/**
- * \brief           This function initializes an ECDH context.
- *
- * \param ctx       The ECDH context to initialize. This must not be \c NULL.
- */
-void mbedtls_ecdh_init( mbedtls_ecdh_context *ctx );
-
-/**
- * \brief           This function sets up the ECDH context with the information
- *                  given.
- *
- *                  This function should be called after mbedtls_ecdh_init() but
- *                  before mbedtls_ecdh_make_params(). There is no need to call
- *                  this function before mbedtls_ecdh_read_params().
- *
- *                  This is the first function used by a TLS server for ECDHE
- *                  ciphersuites.
- *
- * \param ctx       The ECDH context to set up. This must be initialized.
- * \param grp_id    The group id of the group to set up the context for.
- *
- * \return          \c 0 on success.
- */
-int mbedtls_ecdh_setup( mbedtls_ecdh_context *ctx,
-                        mbedtls_ecp_group_id grp_id );
-
-/**
- * \brief           This function frees a context.
- *
- * \param ctx       The context to free. This may be \c NULL, in which
- *                  case this function does nothing. If it is not \c NULL,
- *                  it must point to an initialized ECDH context.
- */
-void mbedtls_ecdh_free( mbedtls_ecdh_context *ctx );
-
-/**
- * \brief           This function generates an EC key pair and exports its
- *                  in the format used in a TLS ServerKeyExchange handshake
- *                  message.
- *
- *                  This is the second function used by a TLS server for ECDHE
- *                  ciphersuites. (It is called after mbedtls_ecdh_setup().)
- *
- * \see             ecp.h
- *
- * \param ctx       The ECDH context to use. This must be initialized
- *                  and bound to a group, for example via mbedtls_ecdh_setup().
- * \param olen      The address at which to store the number of Bytes written.
- * \param buf       The destination buffer. This must be a writable buffer of
- *                  length \p blen Bytes.
- * \param blen      The length of the destination buffer \p buf in Bytes.
- * \param f_rng     The RNG function to use. This must not be \c NULL.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may be
- *                  \c NULL in case \p f_rng doesn't need a context argument.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                  operations was reached: see \c mbedtls_ecp_set_max_ops().
- * \return          Another \c MBEDTLS_ERR_ECP_XXX error code on failure.
- */
-int mbedtls_ecdh_make_params( mbedtls_ecdh_context *ctx, size_t *olen,
-                      unsigned char *buf, size_t blen,
-                      int (*f_rng)(void *, unsigned char *, size_t),
-                      void *p_rng );
-
-/**
- * \brief           This function parses the ECDHE parameters in a
- *                  TLS ServerKeyExchange handshake message.
- *
- * \note            In a TLS handshake, this is the how the client
- *                  sets up its ECDHE context from the server's public
- *                  ECDHE key material.
- *
- * \see             ecp.h
- *
- * \param ctx       The ECDHE context to use. This must be initialized.
- * \param buf       On input, \c *buf must be the start of the input buffer.
- *                  On output, \c *buf is updated to point to the end of the
- *                  data that has been read. On success, this is the first byte
- *                  past the end of the ServerKeyExchange parameters.
- *                  On error, this is the point at which an error has been
- *                  detected, which is usually not useful except to debug
- *                  failures.
- * \param end       The end of the input buffer.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX error code on failure.
- *
- */
-int mbedtls_ecdh_read_params( mbedtls_ecdh_context *ctx,
-                              const unsigned char **buf,
-                              const unsigned char *end );
-
-/**
- * \brief           This function sets up an ECDH context from an EC key.
- *
- *                  It is used by clients and servers in place of the
- *                  ServerKeyEchange for static ECDH, and imports ECDH
- *                  parameters from the EC key information of a certificate.
- *
- * \see             ecp.h
- *
- * \param ctx       The ECDH context to set up. This must be initialized.
- * \param key       The EC key to use. This must be initialized.
- * \param side      Defines the source of the key. Possible values are:
- *                  - #MBEDTLS_ECDH_OURS: The key is ours.
- *                  - #MBEDTLS_ECDH_THEIRS: The key is that of the peer.
- *
- * \return          \c 0 on success.
- * \return          Another \c MBEDTLS_ERR_ECP_XXX error code on failure.
- *
- */
-int mbedtls_ecdh_get_params( mbedtls_ecdh_context *ctx,
-                             const mbedtls_ecp_keypair *key,
-                             mbedtls_ecdh_side side );
-
-/**
- * \brief           This function generates a public key and exports it
- *                  as a TLS ClientKeyExchange payload.
- *
- *                  This is the second function used by a TLS client for ECDH(E)
- *                  ciphersuites.
- *
- * \see             ecp.h
- *
- * \param ctx       The ECDH context to use. This must be initialized
- *                  and bound to a group, the latter usually by
- *                  mbedtls_ecdh_read_params().
- * \param olen      The address at which to store the number of Bytes written.
- *                  This must not be \c NULL.
- * \param buf       The destination buffer. This must be a writable buffer
- *                  of length \p blen Bytes.
- * \param blen      The size of the destination buffer \p buf in Bytes.
- * \param f_rng     The RNG function to use. This must not be \c NULL.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may be
- *                  \c NULL in case \p f_rng doesn't need a context argument.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                  operations was reached: see \c mbedtls_ecp_set_max_ops().
- * \return          Another \c MBEDTLS_ERR_ECP_XXX error code on failure.
- */
-int mbedtls_ecdh_make_public( mbedtls_ecdh_context *ctx, size_t *olen,
-                      unsigned char *buf, size_t blen,
-                      int (*f_rng)(void *, unsigned char *, size_t),
-                      void *p_rng );
-
-/**
- * \brief       This function parses and processes the ECDHE payload of a
- *              TLS ClientKeyExchange message.
- *
- *              This is the third function used by a TLS server for ECDH(E)
- *              ciphersuites. (It is called after mbedtls_ecdh_setup() and
- *              mbedtls_ecdh_make_params().)
- *
- * \see         ecp.h
- *
- * \param ctx   The ECDH context to use. This must be initialized
- *              and bound to a group, for example via mbedtls_ecdh_setup().
- * \param buf   The pointer to the ClientKeyExchange payload. This must
- *              be a readable buffer of length \p blen Bytes.
- * \param blen  The length of the input buffer \p buf in Bytes.
- *
- * \return      \c 0 on success.
- * \return      An \c MBEDTLS_ERR_ECP_XXX error code on failure.
- */
-int mbedtls_ecdh_read_public( mbedtls_ecdh_context *ctx,
-                              const unsigned char *buf, size_t blen );
-
-/**
- * \brief           This function derives and exports the shared secret.
- *
- *                  This is the last function used by both TLS client
- *                  and servers.
- *
- * \note            If \p f_rng is not NULL, it is used to implement
- *                  countermeasures against side-channel attacks.
- *                  For more information, see mbedtls_ecp_mul().
- *
- * \see             ecp.h
-
- * \param ctx       The ECDH context to use. This must be initialized
- *                  and have its own private key generated and the peer's
- *                  public key imported.
- * \param olen      The address at which to store the total number of
- *                  Bytes written on success. This must not be \c NULL.
- * \param buf       The buffer to write the generated shared key to. This
- *                  must be a writable buffer of size \p blen Bytes.
- * \param blen      The length of the destination buffer \p buf in Bytes.
- * \param f_rng     The RNG function, for blinding purposes. This may
- *                  b \c NULL if blinding isn't needed.
- * \param p_rng     The RNG context. This may be \c NULL if \p f_rng
- *                  doesn't need a context argument.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                  operations was reached: see \c mbedtls_ecp_set_max_ops().
- * \return          Another \c MBEDTLS_ERR_ECP_XXX error code on failure.
- */
-int mbedtls_ecdh_calc_secret( mbedtls_ecdh_context *ctx, size_t *olen,
-                      unsigned char *buf, size_t blen,
-                      int (*f_rng)(void *, unsigned char *, size_t),
-                      void *p_rng );
-
-#if defined(MBEDTLS_ECP_RESTARTABLE)
-/**
- * \brief           This function enables restartable EC computations for this
- *                  context.  (Default: disabled.)
- *
- * \see             \c mbedtls_ecp_set_max_ops()
- *
- * \note            It is not possible to safely disable restartable
- *                  computations once enabled, except by free-ing the context,
- *                  which cancels possible in-progress operations.
- *
- * \param ctx       The ECDH context to use. This must be initialized.
- */
-void mbedtls_ecdh_enable_restart( mbedtls_ecdh_context *ctx );
-#endif /* MBEDTLS_ECP_RESTARTABLE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ecdh.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ecdsa.h b/tools/sdk/include/mbedtls/mbedtls/ecdsa.h
deleted file mode 100644
index bc219dcad75..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ecdsa.h
+++ /dev/null
@@ -1,631 +0,0 @@
-/**
- * \file ecdsa.h
- *
- * \brief This file contains ECDSA definitions and functions.
- *
- * The Elliptic Curve Digital Signature Algorithm (ECDSA) is defined in
- * <em>Standards for Efficient Cryptography Group (SECG):
- * SEC1 Elliptic Curve Cryptography</em>.
- * The use of ECDSA for TLS is defined in <em>RFC-4492: Elliptic Curve
- * Cryptography (ECC) Cipher Suites for Transport Layer Security (TLS)</em>.
- *
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_ECDSA_H
-#define MBEDTLS_ECDSA_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "ecp.h"
-#include "md.h"
-
-/*
- * RFC-4492 page 20:
- *
- *     Ecdsa-Sig-Value ::= SEQUENCE {
- *         r       INTEGER,
- *         s       INTEGER
- *     }
- *
- * Size is at most
- *    1 (tag) + 1 (len) + 1 (initial 0) + ECP_MAX_BYTES for each of r and s,
- *    twice that + 1 (tag) + 2 (len) for the sequence
- * (assuming ECP_MAX_BYTES is less than 126 for r and s,
- * and less than 124 (total len <= 255) for the sequence)
- */
-#if MBEDTLS_ECP_MAX_BYTES > 124
-#error "MBEDTLS_ECP_MAX_BYTES bigger than expected, please fix MBEDTLS_ECDSA_MAX_LEN"
-#endif
-/** The maximal size of an ECDSA signature in Bytes. */
-#define MBEDTLS_ECDSA_MAX_LEN  ( 3 + 2 * ( 3 + MBEDTLS_ECP_MAX_BYTES ) )
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief           The ECDSA context structure.
- *
- * \warning         Performing multiple operations concurrently on the same
- *                  ECDSA context is not supported; objects of this type
- *                  should not be shared between multiple threads.
- */
-typedef mbedtls_ecp_keypair mbedtls_ecdsa_context;
-
-#if defined(MBEDTLS_ECP_RESTARTABLE)
-
-/**
- * \brief           Internal restart context for ecdsa_verify()
- *
- * \note            Opaque struct, defined in ecdsa.c
- */
-typedef struct mbedtls_ecdsa_restart_ver mbedtls_ecdsa_restart_ver_ctx;
-
-/**
- * \brief           Internal restart context for ecdsa_sign()
- *
- * \note            Opaque struct, defined in ecdsa.c
- */
-typedef struct mbedtls_ecdsa_restart_sig mbedtls_ecdsa_restart_sig_ctx;
-
-#if defined(MBEDTLS_ECDSA_DETERMINISTIC)
-/**
- * \brief           Internal restart context for ecdsa_sign_det()
- *
- * \note            Opaque struct, defined in ecdsa.c
- */
-typedef struct mbedtls_ecdsa_restart_det mbedtls_ecdsa_restart_det_ctx;
-#endif
-
-/**
- * \brief           General context for resuming ECDSA operations
- */
-typedef struct
-{
-    mbedtls_ecp_restart_ctx ecp;        /*!<  base context for ECP restart and
-                                              shared administrative info    */
-    mbedtls_ecdsa_restart_ver_ctx *ver; /*!<  ecdsa_verify() sub-context    */
-    mbedtls_ecdsa_restart_sig_ctx *sig; /*!<  ecdsa_sign() sub-context      */
-#if defined(MBEDTLS_ECDSA_DETERMINISTIC)
-    mbedtls_ecdsa_restart_det_ctx *det; /*!<  ecdsa_sign_det() sub-context  */
-#endif
-} mbedtls_ecdsa_restart_ctx;
-
-#else /* MBEDTLS_ECP_RESTARTABLE */
-
-/* Now we can declare functions that take a pointer to that */
-typedef void mbedtls_ecdsa_restart_ctx;
-
-#endif /* MBEDTLS_ECP_RESTARTABLE */
-
-/**
- * \brief           This function computes the ECDSA signature of a
- *                  previously-hashed message.
- *
- * \note            The deterministic version implemented in
- *                  mbedtls_ecdsa_sign_det() is usually preferred.
- *
- * \note            If the bitlength of the message hash is larger than the
- *                  bitlength of the group order, then the hash is truncated
- *                  as defined in <em>Standards for Efficient Cryptography Group
- *                  (SECG): SEC1 Elliptic Curve Cryptography</em>, section
- *                  4.1.3, step 5.
- *
- * \see             ecp.h
- *
- * \param grp       The context for the elliptic curve to use.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param r         The MPI context in which to store the first part
- *                  the signature. This must be initialized.
- * \param s         The MPI context in which to store the second part
- *                  the signature. This must be initialized.
- * \param d         The private signing key. This must be initialized.
- * \param buf       The content to be signed. This is usually the hash of
- *                  the original data to be signed. This must be a readable
- *                  buffer of length \p blen Bytes. It may be \c NULL if
- *                  \p blen is zero.
- * \param blen      The length of \p buf in Bytes.
- * \param f_rng     The RNG function. This must not be \c NULL.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may be
- *                  \c NULL if \p f_rng doesn't need a context parameter.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX
- *                  or \c MBEDTLS_MPI_XXX error code on failure.
- */
-int mbedtls_ecdsa_sign( mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s,
-                const mbedtls_mpi *d, const unsigned char *buf, size_t blen,
-                int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
-
-#if defined(MBEDTLS_ECDSA_DETERMINISTIC)
-/**
- * \brief           This function computes the ECDSA signature of a
- *                  previously-hashed message, deterministic version.
- *
- *                  For more information, see <em>RFC-6979: Deterministic
- *                  Usage of the Digital Signature Algorithm (DSA) and Elliptic
- *                  Curve Digital Signature Algorithm (ECDSA)</em>.
- *
- * \note            If the bitlength of the message hash is larger than the
- *                  bitlength of the group order, then the hash is truncated as
- *                  defined in <em>Standards for Efficient Cryptography Group
- *                  (SECG): SEC1 Elliptic Curve Cryptography</em>, section
- *                  4.1.3, step 5.
- *
- * \warning         Since the output of the internal RNG is always the same for
- *                  the same key and message, this limits the efficiency of
- *                  blinding and leaks information through side channels. For
- *                  secure behavior use mbedtls_ecdsa_sign_det_ext() instead.
- *
- *                  (Optimally the blinding is a random value that is different
- *                  on every execution. In this case the blinding is still
- *                  random from the attackers perspective, but is the same on
- *                  each execution. This means that this blinding does not
- *                  prevent attackers from recovering secrets by combining
- *                  several measurement traces, but may prevent some attacks
- *                  that exploit relationships between secret data.)
- *
- * \see             ecp.h
- *
- * \param grp       The context for the elliptic curve to use.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param r         The MPI context in which to store the first part
- *                  the signature. This must be initialized.
- * \param s         The MPI context in which to store the second part
- *                  the signature. This must be initialized.
- * \param d         The private signing key. This must be initialized
- *                  and setup, for example through mbedtls_ecp_gen_privkey().
- * \param buf       The hashed content to be signed. This must be a readable
- *                  buffer of length \p blen Bytes. It may be \c NULL if
- *                  \p blen is zero.
- * \param blen      The length of \p buf in Bytes.
- * \param md_alg    The hash algorithm used to hash the original data.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX
- *                  error code on failure.
- */
-int mbedtls_ecdsa_sign_det( mbedtls_ecp_group *grp, mbedtls_mpi *r,
-                            mbedtls_mpi *s, const mbedtls_mpi *d,
-                            const unsigned char *buf, size_t blen,
-                            mbedtls_md_type_t md_alg );
-/**
- * \brief           This function computes the ECDSA signature of a
- *                  previously-hashed message, deterministic version.
- *
- *                  For more information, see <em>RFC-6979: Deterministic
- *                  Usage of the Digital Signature Algorithm (DSA) and Elliptic
- *                  Curve Digital Signature Algorithm (ECDSA)</em>.
- *
- * \note            If the bitlength of the message hash is larger than the
- *                  bitlength of the group order, then the hash is truncated as
- *                  defined in <em>Standards for Efficient Cryptography Group
- *                  (SECG): SEC1 Elliptic Curve Cryptography</em>, section
- *                  4.1.3, step 5.
- *
- * \see             ecp.h
- *
- * \param grp           The context for the elliptic curve to use.
- *                      This must be initialized and have group parameters
- *                      set, for example through mbedtls_ecp_group_load().
- * \param r             The MPI context in which to store the first part
- *                      the signature. This must be initialized.
- * \param s             The MPI context in which to store the second part
- *                      the signature. This must be initialized.
- * \param d             The private signing key. This must be initialized
- *                      and setup, for example through mbedtls_ecp_gen_privkey().
- * \param buf           The hashed content to be signed. This must be a readable
- *                      buffer of length \p blen Bytes. It may be \c NULL if
- *                      \p blen is zero.
- * \param blen          The length of \p buf in Bytes.
- * \param md_alg        The hash algorithm used to hash the original data.
- * \param f_rng_blind   The RNG function used for blinding. This must not be
- *                      \c NULL.
- * \param p_rng_blind   The RNG context to be passed to \p f_rng. This may be
- *                      \c NULL if \p f_rng doesn't need a context parameter.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX
- *                  error code on failure.
- */
-int mbedtls_ecdsa_sign_det_ext( mbedtls_ecp_group *grp, mbedtls_mpi *r,
-                                mbedtls_mpi *s, const mbedtls_mpi *d,
-                                const unsigned char *buf, size_t blen,
-                                mbedtls_md_type_t md_alg,
-                                int (*f_rng_blind)(void *, unsigned char *,
-                                                   size_t),
-                                void *p_rng_blind );
-#endif /* MBEDTLS_ECDSA_DETERMINISTIC */
-
-/**
- * \brief           This function verifies the ECDSA signature of a
- *                  previously-hashed message.
- *
- * \note            If the bitlength of the message hash is larger than the
- *                  bitlength of the group order, then the hash is truncated as
- *                  defined in <em>Standards for Efficient Cryptography Group
- *                  (SECG): SEC1 Elliptic Curve Cryptography</em>, section
- *                  4.1.4, step 3.
- *
- * \see             ecp.h
- *
- * \param grp       The ECP group to use.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param buf       The hashed content that was signed. This must be a readable
- *                  buffer of length \p blen Bytes. It may be \c NULL if
- *                  \p blen is zero.
- * \param blen      The length of \p buf in Bytes.
- * \param Q         The public key to use for verification. This must be
- *                  initialized and setup.
- * \param r         The first integer of the signature.
- *                  This must be initialized.
- * \param s         The second integer of the signature.
- *                  This must be initialized.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the signature
- *                  is invalid.
- * \return          An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX
- *                  error code on failure for any other reason.
- */
-int mbedtls_ecdsa_verify( mbedtls_ecp_group *grp,
-                          const unsigned char *buf, size_t blen,
-                          const mbedtls_ecp_point *Q, const mbedtls_mpi *r,
-                          const mbedtls_mpi *s);
-
-/**
- * \brief           This function computes the ECDSA signature and writes it
- *                  to a buffer, serialized as defined in <em>RFC-4492:
- *                  Elliptic Curve Cryptography (ECC) Cipher Suites for
- *                  Transport Layer Security (TLS)</em>.
- *
- * \warning         It is not thread-safe to use the same context in
- *                  multiple threads.
- *
- * \note            The deterministic version is used if
- *                  #MBEDTLS_ECDSA_DETERMINISTIC is defined. For more
- *                  information, see <em>RFC-6979: Deterministic Usage
- *                  of the Digital Signature Algorithm (DSA) and Elliptic
- *                  Curve Digital Signature Algorithm (ECDSA)</em>.
- *
- * \note            If the bitlength of the message hash is larger than the
- *                  bitlength of the group order, then the hash is truncated as
- *                  defined in <em>Standards for Efficient Cryptography Group
- *                  (SECG): SEC1 Elliptic Curve Cryptography</em>, section
- *                  4.1.3, step 5.
- *
- * \see             ecp.h
- *
- * \param ctx       The ECDSA context to use. This must be initialized
- *                  and have a group and private key bound to it, for example
- *                  via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair().
- * \param md_alg    The message digest that was used to hash the message.
- * \param hash      The message hash to be signed. This must be a readable
- *                  buffer of length \p blen Bytes.
- * \param hlen      The length of the hash \p hash in Bytes.
- * \param sig       The buffer to which to write the signature. This must be a
- *                  writable buffer of length at least twice as large as the
- *                  size of the curve used, plus 9. For example, 73 Bytes if
- *                  a 256-bit curve is used. A buffer length of
- *                  #MBEDTLS_ECDSA_MAX_LEN is always safe.
- * \param slen      The address at which to store the actual length of
- *                  the signature written. Must not be \c NULL.
- * \param f_rng     The RNG function. This must not be \c NULL if
- *                  #MBEDTLS_ECDSA_DETERMINISTIC is unset. Otherwise,
- *                  it is unused and may be set to \c NULL.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may be
- *                  \c NULL if \p f_rng is \c NULL or doesn't use a context.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or
- *                  \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_ecdsa_write_signature( mbedtls_ecdsa_context *ctx,
-                                   mbedtls_md_type_t md_alg,
-                           const unsigned char *hash, size_t hlen,
-                           unsigned char *sig, size_t *slen,
-                           int (*f_rng)(void *, unsigned char *, size_t),
-                           void *p_rng );
-
-/**
- * \brief           This function computes the ECDSA signature and writes it
- *                  to a buffer, in a restartable way.
- *
- * \see             \c mbedtls_ecdsa_write_signature()
- *
- * \note            This function is like \c mbedtls_ecdsa_write_signature()
- *                  but it can return early and restart according to the limit
- *                  set with \c mbedtls_ecp_set_max_ops() to reduce blocking.
- *
- * \param ctx       The ECDSA context to use. This must be initialized
- *                  and have a group and private key bound to it, for example
- *                  via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair().
- * \param md_alg    The message digest that was used to hash the message.
- * \param hash      The message hash to be signed. This must be a readable
- *                  buffer of length \p blen Bytes.
- * \param hlen      The length of the hash \p hash in Bytes.
- * \param sig       The buffer to which to write the signature. This must be a
- *                  writable buffer of length at least twice as large as the
- *                  size of the curve used, plus 9. For example, 73 Bytes if
- *                  a 256-bit curve is used. A buffer length of
- *                  #MBEDTLS_ECDSA_MAX_LEN is always safe.
- * \param slen      The address at which to store the actual length of
- *                  the signature written. Must not be \c NULL.
- * \param f_rng     The RNG function. This must not be \c NULL if
- *                  #MBEDTLS_ECDSA_DETERMINISTIC is unset. Otherwise,
- *                  it is unused and may be set to \c NULL.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may be
- *                  \c NULL if \p f_rng is \c NULL or doesn't use a context.
- * \param rs_ctx    The restart context to use. This may be \c NULL to disable
- *                  restarting. If it is not \c NULL, it must point to an
- *                  initialized restart context.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                  operations was reached: see \c mbedtls_ecp_set_max_ops().
- * \return          Another \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or
- *                  \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_ecdsa_write_signature_restartable( mbedtls_ecdsa_context *ctx,
-                           mbedtls_md_type_t md_alg,
-                           const unsigned char *hash, size_t hlen,
-                           unsigned char *sig, size_t *slen,
-                           int (*f_rng)(void *, unsigned char *, size_t),
-                           void *p_rng,
-                           mbedtls_ecdsa_restart_ctx *rs_ctx );
-
-#if defined(MBEDTLS_ECDSA_DETERMINISTIC)
-#if ! defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED    __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief           This function computes an ECDSA signature and writes
- *                  it to a buffer, serialized as defined in <em>RFC-4492:
- *                  Elliptic Curve Cryptography (ECC) Cipher Suites for
- *                  Transport Layer Security (TLS)</em>.
- *
- *                  The deterministic version is defined in <em>RFC-6979:
- *                  Deterministic Usage of the Digital Signature Algorithm (DSA)
- *                  and Elliptic Curve Digital Signature Algorithm (ECDSA)</em>.
- *
- * \warning         It is not thread-safe to use the same context in
- *                  multiple threads.
- *
- * \note            If the bitlength of the message hash is larger than the
- *                  bitlength of the group order, then the hash is truncated as
- *                  defined in <em>Standards for Efficient Cryptography Group
- *                  (SECG): SEC1 Elliptic Curve Cryptography</em>, section
- *                  4.1.3, step 5.
- *
- * \see             ecp.h
- *
- * \deprecated      Superseded by mbedtls_ecdsa_write_signature() in
- *                  Mbed TLS version 2.0 and later.
- *
- * \param ctx       The ECDSA context to use. This must be initialized
- *                  and have a group and private key bound to it, for example
- *                  via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair().
- * \param hash      The message hash to be signed. This must be a readable
- *                  buffer of length \p blen Bytes.
- * \param hlen      The length of the hash \p hash in Bytes.
- * \param sig       The buffer to which to write the signature. This must be a
- *                  writable buffer of length at least twice as large as the
- *                  size of the curve used, plus 9. For example, 73 Bytes if
- *                  a 256-bit curve is used. A buffer length of
- *                  #MBEDTLS_ECDSA_MAX_LEN is always safe.
- * \param slen      The address at which to store the actual length of
- *                  the signature written. Must not be \c NULL.
- * \param md_alg    The message digest that was used to hash the message.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or
- *                  \c MBEDTLS_ERR_ASN1_XXX error code on failure.
- */
-int mbedtls_ecdsa_write_signature_det( mbedtls_ecdsa_context *ctx,
-                               const unsigned char *hash, size_t hlen,
-                               unsigned char *sig, size_t *slen,
-                               mbedtls_md_type_t md_alg ) MBEDTLS_DEPRECATED;
-#undef MBEDTLS_DEPRECATED
-#endif /* MBEDTLS_DEPRECATED_REMOVED */
-#endif /* MBEDTLS_ECDSA_DETERMINISTIC */
-
-/**
- * \brief           This function reads and verifies an ECDSA signature.
- *
- * \note            If the bitlength of the message hash is larger than the
- *                  bitlength of the group order, then the hash is truncated as
- *                  defined in <em>Standards for Efficient Cryptography Group
- *                  (SECG): SEC1 Elliptic Curve Cryptography</em>, section
- *                  4.1.4, step 3.
- *
- * \see             ecp.h
- *
- * \param ctx       The ECDSA context to use. This must be initialized
- *                  and have a group and public key bound to it.
- * \param hash      The message hash that was signed. This must be a readable
- *                  buffer of length \p size Bytes.
- * \param hlen      The size of the hash \p hash.
- * \param sig       The signature to read and verify. This must be a readable
- *                  buffer of length \p slen Bytes.
- * \param slen      The size of \p sig in Bytes.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid.
- * \return          #MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH if there is a valid
- *                  signature in \p sig, but its length is less than \p siglen.
- * \return          An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_ERR_MPI_XXX
- *                  error code on failure for any other reason.
- */
-int mbedtls_ecdsa_read_signature( mbedtls_ecdsa_context *ctx,
-                          const unsigned char *hash, size_t hlen,
-                          const unsigned char *sig, size_t slen );
-
-/**
- * \brief           This function reads and verifies an ECDSA signature,
- *                  in a restartable way.
- *
- * \see             \c mbedtls_ecdsa_read_signature()
- *
- * \note            This function is like \c mbedtls_ecdsa_read_signature()
- *                  but it can return early and restart according to the limit
- *                  set with \c mbedtls_ecp_set_max_ops() to reduce blocking.
- *
- * \param ctx       The ECDSA context to use. This must be initialized
- *                  and have a group and public key bound to it.
- * \param hash      The message hash that was signed. This must be a readable
- *                  buffer of length \p size Bytes.
- * \param hlen      The size of the hash \p hash.
- * \param sig       The signature to read and verify. This must be a readable
- *                  buffer of length \p slen Bytes.
- * \param slen      The size of \p sig in Bytes.
- * \param rs_ctx    The restart context to use. This may be \c NULL to disable
- *                  restarting. If it is not \c NULL, it must point to an
- *                  initialized restart context.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid.
- * \return          #MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH if there is a valid
- *                  signature in \p sig, but its length is less than \p siglen.
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                  operations was reached: see \c mbedtls_ecp_set_max_ops().
- * \return          Another \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_ERR_MPI_XXX
- *                  error code on failure for any other reason.
- */
-int mbedtls_ecdsa_read_signature_restartable( mbedtls_ecdsa_context *ctx,
-                          const unsigned char *hash, size_t hlen,
-                          const unsigned char *sig, size_t slen,
-                          mbedtls_ecdsa_restart_ctx *rs_ctx );
-
-/**
- * \brief          This function generates an ECDSA keypair on the given curve.
- *
- * \see            ecp.h
- *
- * \param ctx      The ECDSA context to store the keypair in.
- *                 This must be initialized.
- * \param gid      The elliptic curve to use. One of the various
- *                 \c MBEDTLS_ECP_DP_XXX macros depending on configuration.
- * \param f_rng    The RNG function to use. This must not be \c NULL.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be
- *                 \c NULL if \p f_rng doesn't need a context argument.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_ECP_XXX code on failure.
- */
-int mbedtls_ecdsa_genkey( mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid,
-                  int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
-
-/**
- * \brief           This function sets up an ECDSA context from an EC key pair.
- *
- * \see             ecp.h
- *
- * \param ctx       The ECDSA context to setup. This must be initialized.
- * \param key       The EC key to use. This must be initialized and hold
- *                  a private-public key pair or a public key. In the former
- *                  case, the ECDSA context may be used for signature creation
- *                  and verification after this call. In the latter case, it
- *                  may be used for signature verification.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX code on failure.
- */
-int mbedtls_ecdsa_from_keypair( mbedtls_ecdsa_context *ctx,
-                                const mbedtls_ecp_keypair *key );
-
-/**
- * \brief           This function initializes an ECDSA context.
- *
- * \param ctx       The ECDSA context to initialize.
- *                  This must not be \c NULL.
- */
-void mbedtls_ecdsa_init( mbedtls_ecdsa_context *ctx );
-
-/**
- * \brief           This function frees an ECDSA context.
- *
- * \param ctx       The ECDSA context to free. This may be \c NULL,
- *                  in which case this function does nothing. If it
- *                  is not \c NULL, it must be initialized.
- */
-void mbedtls_ecdsa_free( mbedtls_ecdsa_context *ctx );
-
-#if defined(MBEDTLS_ECP_RESTARTABLE)
-/**
- * \brief           Initialize a restart context.
- *
- * \param ctx       The restart context to initialize.
- *                  This must not be \c NULL.
- */
-void mbedtls_ecdsa_restart_init( mbedtls_ecdsa_restart_ctx *ctx );
-
-/**
- * \brief           Free the components of a restart context.
- *
- * \param ctx       The restart context to free. This may be \c NULL,
- *                  in which case this function does nothing. If it
- *                  is not \c NULL, it must be initialized.
- */
-void mbedtls_ecdsa_restart_free( mbedtls_ecdsa_restart_ctx *ctx );
-#endif /* MBEDTLS_ECP_RESTARTABLE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ecdsa.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ecjpake.h b/tools/sdk/include/mbedtls/mbedtls/ecjpake.h
deleted file mode 100644
index 1b6c6ac244e..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ecjpake.h
+++ /dev/null
@@ -1,304 +0,0 @@
-/**
- * \file ecjpake.h
- *
- * \brief Elliptic curve J-PAKE
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_ECJPAKE_H
-#define MBEDTLS_ECJPAKE_H
-
-/*
- * J-PAKE is a password-authenticated key exchange that allows deriving a
- * strong shared secret from a (potentially low entropy) pre-shared
- * passphrase, with forward secrecy and mutual authentication.
- * https://en.wikipedia.org/wiki/Password_Authenticated_Key_Exchange_by_Juggling
- *
- * This file implements the Elliptic Curve variant of J-PAKE,
- * as defined in Chapter 7.4 of the Thread v1.0 Specification,
- * available to members of the Thread Group http://threadgroup.org/
- *
- * As the J-PAKE algorithm is inherently symmetric, so is our API.
- * Each party needs to send its first round message, in any order, to the
- * other party, then each sends its second round message, in any order.
- * The payloads are serialized in a way suitable for use in TLS, but could
- * also be use outside TLS.
- */
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "ecp.h"
-#include "md.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Roles in the EC J-PAKE exchange
- */
-typedef enum {
-    MBEDTLS_ECJPAKE_CLIENT = 0,         /**< Client                         */
-    MBEDTLS_ECJPAKE_SERVER,             /**< Server                         */
-} mbedtls_ecjpake_role;
-
-#if !defined(MBEDTLS_ECJPAKE_ALT)
-/**
- * EC J-PAKE context structure.
- *
- * J-PAKE is a symmetric protocol, except for the identifiers used in
- * Zero-Knowledge Proofs, and the serialization of the second message
- * (KeyExchange) as defined by the Thread spec.
- *
- * In order to benefit from this symmetry, we choose a different naming
- * convetion from the Thread v1.0 spec. Correspondance is indicated in the
- * description as a pair C: client name, S: server name
- */
-typedef struct mbedtls_ecjpake_context
-{
-    const mbedtls_md_info_t *md_info;   /**< Hash to use                    */
-    mbedtls_ecp_group grp;              /**< Elliptic curve                 */
-    mbedtls_ecjpake_role role;          /**< Are we client or server?       */
-    int point_format;                   /**< Format for point export        */
-
-    mbedtls_ecp_point Xm1;              /**< My public key 1   C: X1, S: X3 */
-    mbedtls_ecp_point Xm2;              /**< My public key 2   C: X2, S: X4 */
-    mbedtls_ecp_point Xp1;              /**< Peer public key 1 C: X3, S: X1 */
-    mbedtls_ecp_point Xp2;              /**< Peer public key 2 C: X4, S: X2 */
-    mbedtls_ecp_point Xp;               /**< Peer public key   C: Xs, S: Xc */
-
-    mbedtls_mpi xm1;                    /**< My private key 1  C: x1, S: x3 */
-    mbedtls_mpi xm2;                    /**< My private key 2  C: x2, S: x4 */
-
-    mbedtls_mpi s;                      /**< Pre-shared secret (passphrase) */
-} mbedtls_ecjpake_context;
-
-#else  /* MBEDTLS_ECJPAKE_ALT */
-#include "ecjpake_alt.h"
-#endif /* MBEDTLS_ECJPAKE_ALT */
-
-/**
- * \brief           Initialize an ECJPAKE context.
- *
- * \param ctx       The ECJPAKE context to initialize.
- *                  This must not be \c NULL.
- */
-void mbedtls_ecjpake_init( mbedtls_ecjpake_context *ctx );
-
-/**
- * \brief           Set up an ECJPAKE context for use.
- *
- * \note            Currently the only values for hash/curve allowed by the
- *                  standard are #MBEDTLS_MD_SHA256/#MBEDTLS_ECP_DP_SECP256R1.
- *
- * \param ctx       The ECJPAKE context to set up. This must be initialized.
- * \param role      The role of the caller. This must be either
- *                  #MBEDTLS_ECJPAKE_CLIENT or #MBEDTLS_ECJPAKE_SERVER.
- * \param hash      The identifier of the hash function to use,
- *                  for example #MBEDTLS_MD_SHA256.
- * \param curve     The identifier of the elliptic curve to use,
- *                  for example #MBEDTLS_ECP_DP_SECP256R1.
- * \param secret    The pre-shared secret (passphrase). This must be
- *                  a readable buffer of length \p len Bytes. It need
- *                  only be valid for the duration of this call.
- * \param len       The length of the pre-shared secret \p secret.
- *
- * \return          \c 0 if successful.
- * \return          A negative error code on failure.
- */
-int mbedtls_ecjpake_setup( mbedtls_ecjpake_context *ctx,
-                           mbedtls_ecjpake_role role,
-                           mbedtls_md_type_t hash,
-                           mbedtls_ecp_group_id curve,
-                           const unsigned char *secret,
-                           size_t len );
-
-/**
- * \brief           Check if an ECJPAKE context is ready for use.
- *
- * \param ctx       The ECJPAKE context to check. This must be
- *                  initialized.
- *
- * \return          \c 0 if the context is ready for use.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA otherwise.
- */
-int mbedtls_ecjpake_check( const mbedtls_ecjpake_context *ctx );
-
-/**
- * \brief           Generate and write the first round message
- *                  (TLS: contents of the Client/ServerHello extension,
- *                  excluding extension type and length bytes).
- *
- * \param ctx       The ECJPAKE context to use. This must be
- *                  initialized and set up.
- * \param buf       The buffer to write the contents to. This must be a
- *                  writable buffer of length \p len Bytes.
- * \param len       The length of \p buf in Bytes.
- * \param olen      The address at which to store the total number
- *                  of Bytes written to \p buf. This must not be \c NULL.
- * \param f_rng     The RNG function to use. This must not be \c NULL.
- * \param p_rng     The RNG parameter to be passed to \p f_rng. This
- *                  may be \c NULL if \p f_rng doesn't use a context.
- *
- * \return          \c 0 if successful.
- * \return          A negative error code on failure.
- */
-int mbedtls_ecjpake_write_round_one( mbedtls_ecjpake_context *ctx,
-                            unsigned char *buf, size_t len, size_t *olen,
-                            int (*f_rng)(void *, unsigned char *, size_t),
-                            void *p_rng );
-
-/**
- * \brief           Read and process the first round message
- *                  (TLS: contents of the Client/ServerHello extension,
- *                  excluding extension type and length bytes).
- *
- * \param ctx       The ECJPAKE context to use. This must be initialized
- *                  and set up.
- * \param buf       The buffer holding the first round message. This must
- *                  be a readable buffer of length \p len Bytes.
- * \param len       The length in Bytes of \p buf.
- *
- * \return          \c 0 if successful.
- * \return          A negative error code on failure.
- */
-int mbedtls_ecjpake_read_round_one( mbedtls_ecjpake_context *ctx,
-                                    const unsigned char *buf,
-                                    size_t len );
-
-/**
- * \brief           Generate and write the second round message
- *                  (TLS: contents of the Client/ServerKeyExchange).
- *
- * \param ctx       The ECJPAKE context to use. This must be initialized,
- *                  set up, and already have performed round one.
- * \param buf       The buffer to write the round two contents to.
- *                  This must be a writable buffer of length \p len Bytes.
- * \param len       The size of \p buf in Bytes.
- * \param olen      The address at which to store the total number of Bytes
- *                  written to \p buf. This must not be \c NULL.
- * \param f_rng     The RNG function to use. This must not be \c NULL.
- * \param p_rng     The RNG parameter to be passed to \p f_rng. This
- *                  may be \c NULL if \p f_rng doesn't use a context.
- *
- * \return          \c 0 if successful.
- * \return          A negative error code on failure.
- */
-int mbedtls_ecjpake_write_round_two( mbedtls_ecjpake_context *ctx,
-                            unsigned char *buf, size_t len, size_t *olen,
-                            int (*f_rng)(void *, unsigned char *, size_t),
-                            void *p_rng );
-
-/**
- * \brief           Read and process the second round message
- *                  (TLS: contents of the Client/ServerKeyExchange).
- *
- * \param ctx       The ECJPAKE context to use. This must be initialized
- *                  and set up and already have performed round one.
- * \param buf       The buffer holding the second round message. This must
- *                  be a readable buffer of length \p len Bytes.
- * \param len       The length in Bytes of \p buf.
- *
- * \return          \c 0 if successful.
- * \return          A negative error code on failure.
- */
-int mbedtls_ecjpake_read_round_two( mbedtls_ecjpake_context *ctx,
-                                    const unsigned char *buf,
-                                    size_t len );
-
-/**
- * \brief           Derive the shared secret
- *                  (TLS: Pre-Master Secret).
- *
- * \param ctx       The ECJPAKE context to use. This must be initialized,
- *                  set up and have performed both round one and two.
- * \param buf       The buffer to write the derived secret to. This must
- *                  be a writable buffer of length \p len Bytes.
- * \param len       The length of \p buf in Bytes.
- * \param olen      The address at which to store the total number of Bytes
- *                  written to \p buf. This must not be \c NULL.
- * \param f_rng     The RNG function to use. This must not be \c NULL.
- * \param p_rng     The RNG parameter to be passed to \p f_rng. This
- *                  may be \c NULL if \p f_rng doesn't use a context.
- *
- * \return          \c 0 if successful.
- * \return          A negative error code on failure.
- */
-int mbedtls_ecjpake_derive_secret( mbedtls_ecjpake_context *ctx,
-                            unsigned char *buf, size_t len, size_t *olen,
-                            int (*f_rng)(void *, unsigned char *, size_t),
-                            void *p_rng );
-
-/**
- * \brief           This clears an ECJPAKE context and frees any
- *                  embedded data structure.
- *
- * \param ctx       The ECJPAKE context to free. This may be \c NULL,
- *                  in which case this function does nothing. If it is not
- *                  \c NULL, it must point to an initialized ECJPAKE context.
- */
-void mbedtls_ecjpake_free( mbedtls_ecjpake_context *ctx );
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if a test failed
- */
-int mbedtls_ecjpake_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ecjpake.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ecp.h b/tools/sdk/include/mbedtls/mbedtls/ecp.h
deleted file mode 100644
index 8db206060b2..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ecp.h
+++ /dev/null
@@ -1,1162 +0,0 @@
-/**
- * \file ecp.h
- *
- * \brief This file provides an API for Elliptic Curves over GF(P) (ECP).
- *
- * The use of ECP in cryptography and TLS is defined in
- * <em>Standards for Efficient Cryptography Group (SECG): SEC1
- * Elliptic Curve Cryptography</em> and
- * <em>RFC-4492: Elliptic Curve Cryptography (ECC) Cipher Suites
- * for Transport Layer Security (TLS)</em>.
- *
- * <em>RFC-2409: The Internet Key Exchange (IKE)</em> defines ECP
- * group types.
- *
- */
-
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_ECP_H
-#define MBEDTLS_ECP_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "bignum.h"
-
-/*
- * ECP error codes
- */
-#define MBEDTLS_ERR_ECP_BAD_INPUT_DATA                    -0x4F80  /**< Bad input parameters to function. */
-#define MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL                  -0x4F00  /**< The buffer is too small to write to. */
-#define MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE               -0x4E80  /**< The requested feature is not available, for example, the requested curve is not supported. */
-#define MBEDTLS_ERR_ECP_VERIFY_FAILED                     -0x4E00  /**< The signature is not valid. */
-#define MBEDTLS_ERR_ECP_ALLOC_FAILED                      -0x4D80  /**< Memory allocation failed. */
-#define MBEDTLS_ERR_ECP_RANDOM_FAILED                     -0x4D00  /**< Generation of random value, such as ephemeral key, failed. */
-#define MBEDTLS_ERR_ECP_INVALID_KEY                       -0x4C80  /**< Invalid private or public key. */
-#define MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH                  -0x4C00  /**< The buffer contains a valid signature followed by more data. */
-
-/* MBEDTLS_ERR_ECP_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_ECP_HW_ACCEL_FAILED                   -0x4B80  /**< The ECP hardware accelerator failed. */
-
-#define MBEDTLS_ERR_ECP_IN_PROGRESS                       -0x4B00  /**< Operation in progress, call again with the same parameters to continue. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Domain-parameter identifiers: curve, subgroup, and generator.
- *
- * \note Only curves over prime fields are supported.
- *
- * \warning This library does not support validation of arbitrary domain
- * parameters. Therefore, only standardized domain parameters from trusted
- * sources should be used. See mbedtls_ecp_group_load().
- */
-typedef enum
-{
-    MBEDTLS_ECP_DP_NONE = 0,       /*!< Curve not defined. */
-    MBEDTLS_ECP_DP_SECP192R1,      /*!< Domain parameters for the 192-bit curve defined by FIPS 186-4 and SEC1. */
-    MBEDTLS_ECP_DP_SECP224R1,      /*!< Domain parameters for the 224-bit curve defined by FIPS 186-4 and SEC1. */
-    MBEDTLS_ECP_DP_SECP256R1,      /*!< Domain parameters for the 256-bit curve defined by FIPS 186-4 and SEC1. */
-    MBEDTLS_ECP_DP_SECP384R1,      /*!< Domain parameters for the 384-bit curve defined by FIPS 186-4 and SEC1. */
-    MBEDTLS_ECP_DP_SECP521R1,      /*!< Domain parameters for the 521-bit curve defined by FIPS 186-4 and SEC1. */
-    MBEDTLS_ECP_DP_BP256R1,        /*!< Domain parameters for 256-bit Brainpool curve. */
-    MBEDTLS_ECP_DP_BP384R1,        /*!< Domain parameters for 384-bit Brainpool curve. */
-    MBEDTLS_ECP_DP_BP512R1,        /*!< Domain parameters for 512-bit Brainpool curve. */
-    MBEDTLS_ECP_DP_CURVE25519,     /*!< Domain parameters for Curve25519. */
-    MBEDTLS_ECP_DP_SECP192K1,      /*!< Domain parameters for 192-bit "Koblitz" curve. */
-    MBEDTLS_ECP_DP_SECP224K1,      /*!< Domain parameters for 224-bit "Koblitz" curve. */
-    MBEDTLS_ECP_DP_SECP256K1,      /*!< Domain parameters for 256-bit "Koblitz" curve. */
-    MBEDTLS_ECP_DP_CURVE448,       /*!< Domain parameters for Curve448. */
-} mbedtls_ecp_group_id;
-
-/**
- * The number of supported curves, plus one for #MBEDTLS_ECP_DP_NONE.
- *
- * \note Montgomery curves are currently excluded.
- */
-#define MBEDTLS_ECP_DP_MAX     12
-
-/**
- * Curve information, for use by other modules.
- */
-typedef struct mbedtls_ecp_curve_info
-{
-    mbedtls_ecp_group_id grp_id;    /*!< An internal identifier. */
-    uint16_t tls_id;                /*!< The TLS NamedCurve identifier. */
-    uint16_t bit_size;              /*!< The curve size in bits. */
-    const char *name;               /*!< A human-friendly name. */
-} mbedtls_ecp_curve_info;
-
-/**
- * \brief           The ECP point structure, in Jacobian coordinates.
- *
- * \note            All functions expect and return points satisfying
- *                  the following condition: <code>Z == 0</code> or
- *                  <code>Z == 1</code>. Other values of \p Z are
- *                  used only by internal functions.
- *                  The point is zero, or "at infinity", if <code>Z == 0</code>.
- *                  Otherwise, \p X and \p Y are its standard (affine)
- *                  coordinates.
- */
-typedef struct mbedtls_ecp_point
-{
-    mbedtls_mpi X;          /*!< The X coordinate of the ECP point. */
-    mbedtls_mpi Y;          /*!< The Y coordinate of the ECP point. */
-    mbedtls_mpi Z;          /*!< The Z coordinate of the ECP point. */
-}
-mbedtls_ecp_point;
-
-#if !defined(MBEDTLS_ECP_ALT)
-/*
- * default mbed TLS elliptic curve arithmetic implementation
- *
- * (in case MBEDTLS_ECP_ALT is defined then the developer has to provide an
- * alternative implementation for the whole module and it will replace this
- * one.)
- */
-
-/**
- * \brief           The ECP group structure.
- *
- * We consider two types of curve equations:
- * <ul><li>Short Weierstrass: <code>y^2 = x^3 + A x + B mod P</code>
- * (SEC1 + RFC-4492)</li>
- * <li>Montgomery: <code>y^2 = x^3 + A x^2 + x mod P</code> (Curve25519,
- * Curve448)</li></ul>
- * In both cases, the generator (\p G) for a prime-order subgroup is fixed.
- *
- * For Short Weierstrass, this subgroup is the whole curve, and its
- * cardinality is denoted by \p N. Our code requires that \p N is an
- * odd prime as mbedtls_ecp_mul() requires an odd number, and
- * mbedtls_ecdsa_sign() requires that it is prime for blinding purposes.
- *
- * For Montgomery curves, we do not store \p A, but <code>(A + 2) / 4</code>,
- * which is the quantity used in the formulas. Additionally, \p nbits is
- * not the size of \p N but the required size for private keys.
- *
- * If \p modp is NULL, reduction modulo \p P is done using a generic algorithm.
- * Otherwise, \p modp must point to a function that takes an \p mbedtls_mpi in the
- * range of <code>0..2^(2*pbits)-1</code>, and transforms it in-place to an integer
- * which is congruent mod \p P to the given MPI, and is close enough to \p pbits
- * in size, so that it may be efficiently brought in the 0..P-1 range by a few
- * additions or subtractions. Therefore, it is only an approximative modular
- * reduction. It must return 0 on success and non-zero on failure.
- *
- * \note        Alternative implementations must keep the group IDs distinct. If
- *              two group structures have the same ID, then they must be
- *              identical.
- *
- */
-typedef struct mbedtls_ecp_group
-{
-    mbedtls_ecp_group_id id;    /*!< An internal group identifier. */
-    mbedtls_mpi P;              /*!< The prime modulus of the base field. */
-    mbedtls_mpi A;              /*!< For Short Weierstrass: \p A in the equation. For
-                                     Montgomery curves: <code>(A + 2) / 4</code>. */
-    mbedtls_mpi B;              /*!< For Short Weierstrass: \p B in the equation.
-                                     For Montgomery curves: unused. */
-    mbedtls_ecp_point G;        /*!< The generator of the subgroup used. */
-    mbedtls_mpi N;              /*!< The order of \p G. */
-    size_t pbits;               /*!< The number of bits in \p P.*/
-    size_t nbits;               /*!< For Short Weierstrass: The number of bits in \p P.
-                                     For Montgomery curves: the number of bits in the
-                                     private keys. */
-    unsigned int h;             /*!< \internal 1 if the constants are static. */
-    int (*modp)(mbedtls_mpi *); /*!< The function for fast pseudo-reduction
-                                     mod \p P (see above).*/
-    int (*t_pre)(mbedtls_ecp_point *, void *);  /*!< Unused. */
-    int (*t_post)(mbedtls_ecp_point *, void *); /*!< Unused. */
-    void *t_data;               /*!< Unused. */
-    mbedtls_ecp_point *T;       /*!< Pre-computed points for ecp_mul_comb(). */
-    size_t T_size;              /*!< The number of pre-computed points. */
-}
-mbedtls_ecp_group;
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h, or define them using the compiler command line.
- * \{
- */
-
-#if !defined(MBEDTLS_ECP_MAX_BITS)
-/**
- * The maximum size of the groups, that is, of \c N and \c P.
- */
-#define MBEDTLS_ECP_MAX_BITS     521   /**< The maximum size of groups, in bits. */
-#endif
-
-#define MBEDTLS_ECP_MAX_BYTES    ( ( MBEDTLS_ECP_MAX_BITS + 7 ) / 8 )
-#define MBEDTLS_ECP_MAX_PT_LEN   ( 2 * MBEDTLS_ECP_MAX_BYTES + 1 )
-
-#if !defined(MBEDTLS_ECP_WINDOW_SIZE)
-/*
- * Maximum "window" size used for point multiplication.
- * Default: 6.
- * Minimum value: 2. Maximum value: 7.
- *
- * Result is an array of at most ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) )
- * points used for point multiplication. This value is directly tied to EC
- * peak memory usage, so decreasing it by one should roughly cut memory usage
- * by two (if large curves are in use).
- *
- * Reduction in size may reduce speed, but larger curves are impacted first.
- * Sample performances (in ECDHE handshakes/s, with FIXED_POINT_OPTIM = 1):
- *      w-size:     6       5       4       3       2
- *      521       145     141     135     120      97
- *      384       214     209     198     177     146
- *      256       320     320     303     262     226
- *      224       475     475     453     398     342
- *      192       640     640     633     587     476
- */
-#define MBEDTLS_ECP_WINDOW_SIZE    6   /**< The maximum window size used. */
-#endif /* MBEDTLS_ECP_WINDOW_SIZE */
-
-#if !defined(MBEDTLS_ECP_FIXED_POINT_OPTIM)
-/*
- * Trade memory for speed on fixed-point multiplication.
- *
- * This speeds up repeated multiplication of the generator (that is, the
- * multiplication in ECDSA signatures, and half of the multiplications in
- * ECDSA verification and ECDHE) by a factor roughly 3 to 4.
- *
- * The cost is increasing EC peak memory usage by a factor roughly 2.
- *
- * Change this value to 0 to reduce peak memory usage.
- */
-#define MBEDTLS_ECP_FIXED_POINT_OPTIM  1   /**< Enable fixed-point speed-up. */
-#endif /* MBEDTLS_ECP_FIXED_POINT_OPTIM */
-
-/* \} name SECTION: Module settings */
-
-#else  /* MBEDTLS_ECP_ALT */
-#include "ecp_alt.h"
-#endif /* MBEDTLS_ECP_ALT */
-
-#if defined(MBEDTLS_ECP_RESTARTABLE)
-
-/**
- * \brief           Internal restart context for multiplication
- *
- * \note            Opaque struct
- */
-typedef struct mbedtls_ecp_restart_mul mbedtls_ecp_restart_mul_ctx;
-
-/**
- * \brief           Internal restart context for ecp_muladd()
- *
- * \note            Opaque struct
- */
-typedef struct mbedtls_ecp_restart_muladd mbedtls_ecp_restart_muladd_ctx;
-
-/**
- * \brief           General context for resuming ECC operations
- */
-typedef struct
-{
-    unsigned ops_done;                  /*!<  current ops count             */
-    unsigned depth;                     /*!<  call depth (0 = top-level)    */
-    mbedtls_ecp_restart_mul_ctx *rsm;   /*!<  ecp_mul_comb() sub-context    */
-    mbedtls_ecp_restart_muladd_ctx *ma; /*!<  ecp_muladd() sub-context      */
-} mbedtls_ecp_restart_ctx;
-
-/*
- * Operation counts for restartable functions
- */
-#define MBEDTLS_ECP_OPS_CHK   3 /*!< basic ops count for ecp_check_pubkey()  */
-#define MBEDTLS_ECP_OPS_DBL   8 /*!< basic ops count for ecp_double_jac()    */
-#define MBEDTLS_ECP_OPS_ADD  11 /*!< basic ops count for see ecp_add_mixed() */
-#define MBEDTLS_ECP_OPS_INV 120 /*!< empirical equivalent for mpi_mod_inv()  */
-
-/**
- * \brief           Internal; for restartable functions in other modules.
- *                  Check and update basic ops budget.
- *
- * \param grp       Group structure
- * \param rs_ctx    Restart context
- * \param ops       Number of basic ops to do
- *
- * \return          \c 0 if doing \p ops basic ops is still allowed,
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS otherwise.
- */
-int mbedtls_ecp_check_budget( const mbedtls_ecp_group *grp,
-                              mbedtls_ecp_restart_ctx *rs_ctx,
-                              unsigned ops );
-
-/* Utility macro for checking and updating ops budget */
-#define MBEDTLS_ECP_BUDGET( ops )   \
-    MBEDTLS_MPI_CHK( mbedtls_ecp_check_budget( grp, rs_ctx, \
-                                               (unsigned) (ops) ) );
-
-#else /* MBEDTLS_ECP_RESTARTABLE */
-
-#define MBEDTLS_ECP_BUDGET( ops )   /* no-op; for compatibility */
-
-/* We want to declare restartable versions of existing functions anyway */
-typedef void mbedtls_ecp_restart_ctx;
-
-#endif /* MBEDTLS_ECP_RESTARTABLE */
-
-/**
- * \brief    The ECP key-pair structure.
- *
- * A generic key-pair that may be used for ECDSA and fixed ECDH, for example.
- *
- * \note    Members are deliberately in the same order as in the
- *          ::mbedtls_ecdsa_context structure.
- */
-typedef struct mbedtls_ecp_keypair
-{
-    mbedtls_ecp_group grp;      /*!<  Elliptic curve and base point     */
-    mbedtls_mpi d;              /*!<  our secret value                  */
-    mbedtls_ecp_point Q;        /*!<  our public value                  */
-}
-mbedtls_ecp_keypair;
-
-/*
- * Point formats, from RFC 4492's enum ECPointFormat
- */
-#define MBEDTLS_ECP_PF_UNCOMPRESSED    0   /**< Uncompressed point format. */
-#define MBEDTLS_ECP_PF_COMPRESSED      1   /**< Compressed point format. */
-
-/*
- * Some other constants from RFC 4492
- */
-#define MBEDTLS_ECP_TLS_NAMED_CURVE    3   /**< The named_curve of ECCurveType. */
-
-#if defined(MBEDTLS_ECP_RESTARTABLE)
-/**
- * \brief           Set the maximum number of basic operations done in a row.
- *
- *                  If more operations are needed to complete a computation,
- *                  #MBEDTLS_ERR_ECP_IN_PROGRESS will be returned by the
- *                  function performing the computation. It is then the
- *                  caller's responsibility to either call again with the same
- *                  parameters until it returns 0 or an error code; or to free
- *                  the restart context if the operation is to be aborted.
- *
- *                  It is strictly required that all input parameters and the
- *                  restart context be the same on successive calls for the
- *                  same operation, but output parameters need not be the
- *                  same; they must not be used until the function finally
- *                  returns 0.
- *
- *                  This only applies to functions whose documentation
- *                  mentions they may return #MBEDTLS_ERR_ECP_IN_PROGRESS (or
- *                  #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS for functions in the
- *                  SSL module). For functions that accept a "restart context"
- *                  argument, passing NULL disables restart and makes the
- *                  function equivalent to the function with the same name
- *                  with \c _restartable removed. For functions in the ECDH
- *                  module, restart is disabled unless the function accepts
- *                  an "ECDH context" argument and
- *                  mbedtls_ecdh_enable_restart() was previously called on
- *                  that context. For function in the SSL module, restart is
- *                  only enabled for specific sides and key exchanges
- *                  (currently only for clients and ECDHE-ECDSA).
- *
- * \param max_ops   Maximum number of basic operations done in a row.
- *                  Default: 0 (unlimited).
- *                  Lower (non-zero) values mean ECC functions will block for
- *                  a lesser maximum amount of time.
- *
- * \note            A "basic operation" is defined as a rough equivalent of a
- *                  multiplication in GF(p) for the NIST P-256 curve.
- *                  As an indication, with default settings, a scalar
- *                  multiplication (full run of \c mbedtls_ecp_mul()) is:
- *                  - about 3300 basic operations for P-256
- *                  - about 9400 basic operations for P-384
- *
- * \note            Very low values are not always respected: sometimes
- *                  functions need to block for a minimum number of
- *                  operations, and will do so even if max_ops is set to a
- *                  lower value.  That minimum depends on the curve size, and
- *                  can be made lower by decreasing the value of
- *                  \c MBEDTLS_ECP_WINDOW_SIZE.  As an indication, here is the
- *                  lowest effective value for various curves and values of
- *                  that parameter (w for short):
- *                          w=6     w=5     w=4     w=3     w=2
- *                  P-256   208     208     160     136     124
- *                  P-384   682     416     320     272     248
- *                  P-521  1364     832     640     544     496
- *
- * \note            This setting is currently ignored by Curve25519.
- */
-void mbedtls_ecp_set_max_ops( unsigned max_ops );
-
-/**
- * \brief           Check if restart is enabled (max_ops != 0)
- *
- * \return          \c 0 if \c max_ops == 0 (restart disabled)
- * \return          \c 1 otherwise (restart enabled)
- */
-int mbedtls_ecp_restart_is_enabled( void );
-#endif /* MBEDTLS_ECP_RESTARTABLE */
-
-/**
- * \brief           This function retrieves the information defined in
- *                  mbedtls_ecp_curve_info() for all supported curves in order
- *                  of preference.
- *
- * \return          A statically allocated array. The last entry is 0.
- */
-const mbedtls_ecp_curve_info *mbedtls_ecp_curve_list( void );
-
-/**
- * \brief           This function retrieves the list of internal group
- *                  identifiers of all supported curves in the order of
- *                  preference.
- *
- * \return          A statically allocated array,
- *                  terminated with MBEDTLS_ECP_DP_NONE.
- */
-const mbedtls_ecp_group_id *mbedtls_ecp_grp_id_list( void );
-
-/**
- * \brief           This function retrieves curve information from an internal
- *                  group identifier.
- *
- * \param grp_id    An \c MBEDTLS_ECP_DP_XXX value.
- *
- * \return          The associated curve information on success.
- * \return          NULL on failure.
- */
-const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_grp_id( mbedtls_ecp_group_id grp_id );
-
-/**
- * \brief           This function retrieves curve information from a TLS
- *                  NamedCurve value.
- *
- * \param tls_id    An \c MBEDTLS_ECP_DP_XXX value.
- *
- * \return          The associated curve information on success.
- * \return          NULL on failure.
- */
-const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_tls_id( uint16_t tls_id );
-
-/**
- * \brief           This function retrieves curve information from a
- *                  human-readable name.
- *
- * \param name      The human-readable name.
- *
- * \return          The associated curve information on success.
- * \return          NULL on failure.
- */
-const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_name( const char *name );
-
-/**
- * \brief           This function initializes a point as zero.
- *
- * \param pt        The point to initialize.
- */
-void mbedtls_ecp_point_init( mbedtls_ecp_point *pt );
-
-/**
- * \brief           This function initializes an ECP group context
- *                  without loading any domain parameters.
- *
- * \note            After this function is called, domain parameters
- *                  for various ECP groups can be loaded through the
- *                  mbedtls_ecp_group_load() or mbedtls_ecp_tls_read_group()
- *                  functions.
- */
-void mbedtls_ecp_group_init( mbedtls_ecp_group *grp );
-
-/**
- * \brief           This function initializes a key pair as an invalid one.
- *
- * \param key       The key pair to initialize.
- */
-void mbedtls_ecp_keypair_init( mbedtls_ecp_keypair *key );
-
-/**
- * \brief           This function frees the components of a point.
- *
- * \param pt        The point to free.
- */
-void mbedtls_ecp_point_free( mbedtls_ecp_point *pt );
-
-/**
- * \brief           This function frees the components of an ECP group.
- *
- * \param grp       The group to free. This may be \c NULL, in which
- *                  case this function returns immediately. If it is not
- *                  \c NULL, it must point to an initialized ECP group.
- */
-void mbedtls_ecp_group_free( mbedtls_ecp_group *grp );
-
-/**
- * \brief           This function frees the components of a key pair.
- *
- * \param key       The key pair to free. This may be \c NULL, in which
- *                  case this function returns immediately. If it is not
- *                  \c NULL, it must point to an initialized ECP key pair.
- */
-void mbedtls_ecp_keypair_free( mbedtls_ecp_keypair *key );
-
-#if defined(MBEDTLS_ECP_RESTARTABLE)
-/**
- * \brief           Initialize a restart context.
- *
- * \param ctx       The restart context to initialize. This must
- *                  not be \c NULL.
- */
-void mbedtls_ecp_restart_init( mbedtls_ecp_restart_ctx *ctx );
-
-/**
- * \brief           Free the components of a restart context.
- *
- * \param ctx       The restart context to free. This may be \c NULL, in which
- *                  case this function returns immediately. If it is not
- *                  \c NULL, it must point to an initialized restart context.
- */
-void mbedtls_ecp_restart_free( mbedtls_ecp_restart_ctx *ctx );
-#endif /* MBEDTLS_ECP_RESTARTABLE */
-
-/**
- * \brief           This function copies the contents of point \p Q into
- *                  point \p P.
- *
- * \param P         The destination point. This must be initialized.
- * \param Q         The source point. This must be initialized.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure.
- * \return          Another negative error code for other kinds of failure.
- */
-int mbedtls_ecp_copy( mbedtls_ecp_point *P, const mbedtls_ecp_point *Q );
-
-/**
- * \brief           This function copies the contents of group \p src into
- *                  group \p dst.
- *
- * \param dst       The destination group. This must be initialized.
- * \param src       The source group. This must be initialized.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_group_copy( mbedtls_ecp_group *dst,
-                            const mbedtls_ecp_group *src );
-
-/**
- * \brief           This function sets a point to the point at infinity.
- *
- * \param pt        The point to set. This must be initialized.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_set_zero( mbedtls_ecp_point *pt );
-
-/**
- * \brief           This function checks if a point is the point at infinity.
- *
- * \param pt        The point to test. This must be initialized.
- *
- * \return          \c 1 if the point is zero.
- * \return          \c 0 if the point is non-zero.
- * \return          A negative error code on failure.
- */
-int mbedtls_ecp_is_zero( mbedtls_ecp_point *pt );
-
-/**
- * \brief           This function compares two points.
- *
- * \note            This assumes that the points are normalized. Otherwise,
- *                  they may compare as "not equal" even if they are.
- *
- * \param P         The first point to compare. This must be initialized.
- * \param Q         The second point to compare. This must be initialized.
- *
- * \return          \c 0 if the points are equal.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the points are not equal.
- */
-int mbedtls_ecp_point_cmp( const mbedtls_ecp_point *P,
-                           const mbedtls_ecp_point *Q );
-
-/**
- * \brief           This function imports a non-zero point from two ASCII
- *                  strings.
- *
- * \param P         The destination point. This must be initialized.
- * \param radix     The numeric base of the input.
- * \param x         The first affine coordinate, as a null-terminated string.
- * \param y         The second affine coordinate, as a null-terminated string.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_MPI_XXX error code on failure.
- */
-int mbedtls_ecp_point_read_string( mbedtls_ecp_point *P, int radix,
-                           const char *x, const char *y );
-
-/**
- * \brief           This function exports a point into unsigned binary data.
- *
- * \param grp       The group to which the point should belong.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param P         The point to export. This must be initialized.
- * \param format    The point format. This must be either
- *                  #MBEDTLS_ECP_PF_COMPRESSED or #MBEDTLS_ECP_PF_UNCOMPRESSED.
- * \param olen      The address at which to store the length of
- *                  the output in Bytes. This must not be \c NULL.
- * \param buf       The output buffer. This must be a writable buffer
- *                  of length \p buflen Bytes.
- * \param buflen    The length of the output buffer \p buf in Bytes.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the output buffer
- *                  is too small to hold the point.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_point_write_binary( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *P,
-                            int format, size_t *olen,
-                            unsigned char *buf, size_t buflen );
-
-/**
- * \brief           This function imports a point from unsigned binary data.
- *
- * \note            This function does not check that the point actually
- *                  belongs to the given group, see mbedtls_ecp_check_pubkey()
- *                  for that.
- *
- * \param grp       The group to which the point should belong.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param P         The destination context to import the point to.
- *                  This must be initialized.
- * \param buf       The input buffer. This must be a readable buffer
- *                  of length \p ilen Bytes.
- * \param ilen      The length of the input buffer \p buf in Bytes.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the input is invalid.
- * \return          #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure.
- * \return          #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the point format
- *                  is not implemented.
- */
-int mbedtls_ecp_point_read_binary( const mbedtls_ecp_group *grp,
-                                   mbedtls_ecp_point *P,
-                                   const unsigned char *buf, size_t ilen );
-
-/**
- * \brief           This function imports a point from a TLS ECPoint record.
- *
- * \note            On function return, \p *buf is updated to point immediately
- *                  after the ECPoint record.
- *
- * \param grp       The ECP group to use.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param pt        The destination point.
- * \param buf       The address of the pointer to the start of the input buffer.
- * \param len       The length of the buffer.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_MPI_XXX error code on initialization
- *                  failure.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid.
- */
-int mbedtls_ecp_tls_read_point( const mbedtls_ecp_group *grp,
-                                mbedtls_ecp_point *pt,
-                                const unsigned char **buf, size_t len );
-
-/**
- * \brief           This function exports a point as a TLS ECPoint record
- *                  defined in RFC 4492, Section 5.4.
- *
- * \param grp       The ECP group to use.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param pt        The point to be exported. This must be initialized.
- * \param format    The point format to use. This must be either
- *                  #MBEDTLS_ECP_PF_COMPRESSED or #MBEDTLS_ECP_PF_UNCOMPRESSED.
- * \param olen      The address at which to store the length in Bytes
- *                  of the data written.
- * \param buf       The target buffer. This must be a writable buffer of
- *                  length \p blen Bytes.
- * \param blen      The length of the target buffer \p buf in Bytes.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the input is invalid.
- * \return          #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the target buffer
- *                  is too small to hold the exported point.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_tls_write_point( const mbedtls_ecp_group *grp,
-                                 const mbedtls_ecp_point *pt,
-                                 int format, size_t *olen,
-                                 unsigned char *buf, size_t blen );
-
-/**
- * \brief           This function sets up an ECP group context
- *                  from a standardized set of domain parameters.
- *
- * \note            The index should be a value of the NamedCurve enum,
- *                  as defined in <em>RFC-4492: Elliptic Curve Cryptography
- *                  (ECC) Cipher Suites for Transport Layer Security (TLS)</em>,
- *                  usually in the form of an \c MBEDTLS_ECP_DP_XXX macro.
- *
- * \param grp       The group context to setup. This must be initialized.
- * \param id        The identifier of the domain parameter set to load.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if \p id doesn't
- *                  correspond to a known group.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_group_load( mbedtls_ecp_group *grp, mbedtls_ecp_group_id id );
-
-/**
- * \brief           This function sets up an ECP group context from a TLS
- *                  ECParameters record as defined in RFC 4492, Section 5.4.
- *
- * \note            The read pointer \p buf is updated to point right after
- *                  the ECParameters record on exit.
- *
- * \param grp       The group context to setup. This must be initialized.
- * \param buf       The address of the pointer to the start of the input buffer.
- * \param len       The length of the input buffer \c *buf in Bytes.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid.
- * \return          #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the group is not
- *                  recognized.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_tls_read_group( mbedtls_ecp_group *grp,
-                                const unsigned char **buf, size_t len );
-
-/**
- * \brief           This function extracts an elliptic curve group ID from a
- *                  TLS ECParameters record as defined in RFC 4492, Section 5.4.
- *
- * \note            The read pointer \p buf is updated to point right after
- *                  the ECParameters record on exit.
- *
- * \param grp       The address at which to store the group id.
- *                  This must not be \c NULL.
- * \param buf       The address of the pointer to the start of the input buffer.
- * \param len       The length of the input buffer \c *buf in Bytes.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid.
- * \return          #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the group is not
- *                  recognized.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_tls_read_group_id( mbedtls_ecp_group_id *grp,
-                                   const unsigned char **buf,
-                                   size_t len );
-/**
- * \brief           This function exports an elliptic curve as a TLS
- *                  ECParameters record as defined in RFC 4492, Section 5.4.
- *
- * \param grp       The ECP group to be exported.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param olen      The address at which to store the number of Bytes written.
- *                  This must not be \c NULL.
- * \param buf       The buffer to write to. This must be a writable buffer
- *                  of length \p blen Bytes.
- * \param blen      The length of the output buffer \p buf in Bytes.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the output
- *                  buffer is too small to hold the exported group.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_tls_write_group( const mbedtls_ecp_group *grp,
-                                 size_t *olen,
-                                 unsigned char *buf, size_t blen );
-
-/**
- * \brief           This function performs a scalar multiplication of a point
- *                  by an integer: \p R = \p m * \p P.
- *
- *                  It is not thread-safe to use same group in multiple threads.
- *
- * \note            To prevent timing attacks, this function
- *                  executes the exact same sequence of base-field
- *                  operations for any valid \p m. It avoids any if-branch or
- *                  array index depending on the value of \p m.
- *
- * \note            If \p f_rng is not NULL, it is used to randomize
- *                  intermediate results to prevent potential timing attacks
- *                  targeting these results. We recommend always providing
- *                  a non-NULL \p f_rng. The overhead is negligible.
- *                  Note: unless #MBEDTLS_ECP_NO_INTERNAL_RNG is defined, when
- *                  \p f_rng is NULL, an internal RNG (seeded from the value
- *                  of \p m) will be used instead.
- *
- * \param grp       The ECP group to use.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param R         The point in which to store the result of the calculation.
- *                  This must be initialized.
- * \param m         The integer by which to multiply. This must be initialized.
- * \param P         The point to multiply. This must be initialized.
- * \param f_rng     The RNG function. This may be \c NULL if randomization
- *                  of intermediate results isn't desired (discouraged).
- * \param p_rng     The RNG context to be passed to \p p_rng.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_INVALID_KEY if \p m is not a valid private
- *                  key, or \p P is not a valid public key.
- * \return          #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_mul( mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
-             const mbedtls_mpi *m, const mbedtls_ecp_point *P,
-             int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
-
-/**
- * \brief           This function performs multiplication of a point by
- *                  an integer: \p R = \p m * \p P in a restartable way.
- *
- * \see             mbedtls_ecp_mul()
- *
- * \note            This function does the same as \c mbedtls_ecp_mul(), but
- *                  it can return early and restart according to the limit set
- *                  with \c mbedtls_ecp_set_max_ops() to reduce blocking.
- *
- * \param grp       The ECP group to use.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param R         The point in which to store the result of the calculation.
- *                  This must be initialized.
- * \param m         The integer by which to multiply. This must be initialized.
- * \param P         The point to multiply. This must be initialized.
- * \param f_rng     The RNG function. This may be \c NULL if randomization
- *                  of intermediate results isn't desired (discouraged).
- * \param p_rng     The RNG context to be passed to \p p_rng.
- * \param rs_ctx    The restart context (NULL disables restart).
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_INVALID_KEY if \p m is not a valid private
- *                  key, or \p P is not a valid public key.
- * \return          #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure.
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                  operations was reached: see \c mbedtls_ecp_set_max_ops().
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_mul_restartable( mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
-             const mbedtls_mpi *m, const mbedtls_ecp_point *P,
-             int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
-             mbedtls_ecp_restart_ctx *rs_ctx );
-
-/**
- * \brief           This function performs multiplication and addition of two
- *                  points by integers: \p R = \p m * \p P + \p n * \p Q
- *
- *                  It is not thread-safe to use same group in multiple threads.
- *
- * \note            In contrast to mbedtls_ecp_mul(), this function does not
- *                  guarantee a constant execution flow and timing.
- *
- * \param grp       The ECP group to use.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param R         The point in which to store the result of the calculation.
- *                  This must be initialized.
- * \param m         The integer by which to multiply \p P.
- *                  This must be initialized.
- * \param P         The point to multiply by \p m. This must be initialized.
- * \param n         The integer by which to multiply \p Q.
- *                  This must be initialized.
- * \param Q         The point to be multiplied by \p n.
- *                  This must be initialized.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_INVALID_KEY if \p m or \p n are not
- *                  valid private keys, or \p P or \p Q are not valid public
- *                  keys.
- * \return          #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_muladd( mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
-             const mbedtls_mpi *m, const mbedtls_ecp_point *P,
-             const mbedtls_mpi *n, const mbedtls_ecp_point *Q );
-
-/**
- * \brief           This function performs multiplication and addition of two
- *                  points by integers: \p R = \p m * \p P + \p n * \p Q in a
- *                  restartable way.
- *
- * \see             \c mbedtls_ecp_muladd()
- *
- * \note            This function works the same as \c mbedtls_ecp_muladd(),
- *                  but it can return early and restart according to the limit
- *                  set with \c mbedtls_ecp_set_max_ops() to reduce blocking.
- *
- * \param grp       The ECP group to use.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param R         The point in which to store the result of the calculation.
- *                  This must be initialized.
- * \param m         The integer by which to multiply \p P.
- *                  This must be initialized.
- * \param P         The point to multiply by \p m. This must be initialized.
- * \param n         The integer by which to multiply \p Q.
- *                  This must be initialized.
- * \param Q         The point to be multiplied by \p n.
- *                  This must be initialized.
- * \param rs_ctx    The restart context (NULL disables restart).
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_ECP_INVALID_KEY if \p m or \p n are not
- *                  valid private keys, or \p P or \p Q are not valid public
- *                  keys.
- * \return          #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure.
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                  operations was reached: see \c mbedtls_ecp_set_max_ops().
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_muladd_restartable(
-             mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
-             const mbedtls_mpi *m, const mbedtls_ecp_point *P,
-             const mbedtls_mpi *n, const mbedtls_ecp_point *Q,
-             mbedtls_ecp_restart_ctx *rs_ctx );
-
-/**
- * \brief           This function checks that a point is a valid public key
- *                  on this curve.
- *
- *                  It only checks that the point is non-zero, has
- *                  valid coordinates and lies on the curve. It does not verify
- *                  that it is indeed a multiple of \p G. This additional
- *                  check is computationally more expensive, is not required
- *                  by standards, and should not be necessary if the group
- *                  used has a small cofactor. In particular, it is useless for
- *                  the NIST groups which all have a cofactor of 1.
- *
- * \note            This function uses bare components rather than an
- *                  ::mbedtls_ecp_keypair structure, to ease use with other
- *                  structures, such as ::mbedtls_ecdh_context or
- *                  ::mbedtls_ecdsa_context.
- *
- * \param grp       The ECP group the point should belong to.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param pt        The point to check. This must be initialized.
- *
- * \return          \c 0 if the point is a valid public key.
- * \return          #MBEDTLS_ERR_ECP_INVALID_KEY if the point is not
- *                  a valid public key for the given curve.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp,
-                              const mbedtls_ecp_point *pt );
-
-/**
- * \brief           This function checks that an \p mbedtls_mpi is a
- *                  valid private key for this curve.
- *
- * \note            This function uses bare components rather than an
- *                  ::mbedtls_ecp_keypair structure to ease use with other
- *                  structures, such as ::mbedtls_ecdh_context or
- *                  ::mbedtls_ecdsa_context.
- *
- * \param grp       The ECP group the private key should belong to.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param d         The integer to check. This must be initialized.
- *
- * \return          \c 0 if the point is a valid private key.
- * \return          #MBEDTLS_ERR_ECP_INVALID_KEY if the point is not a valid
- *                  private key for the given curve.
- * \return          Another negative error code on other kinds of failure.
- */
-int mbedtls_ecp_check_privkey( const mbedtls_ecp_group *grp,
-                               const mbedtls_mpi *d );
-
-/**
- * \brief           This function generates a private key.
- *
- * \param grp       The ECP group to generate a private key for.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param d         The destination MPI (secret part). This must be initialized.
- * \param f_rng     The RNG function. This must not be \c NULL.
- * \param p_rng     The RNG parameter to be passed to \p f_rng. This may be
- *                  \c NULL if \p f_rng doesn't need a context argument.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code
- *                  on failure.
- */
-int mbedtls_ecp_gen_privkey( const mbedtls_ecp_group *grp,
-                     mbedtls_mpi *d,
-                     int (*f_rng)(void *, unsigned char *, size_t),
-                     void *p_rng );
-
-/**
- * \brief           This function generates a keypair with a configurable base
- *                  point.
- *
- * \note            This function uses bare components rather than an
- *                  ::mbedtls_ecp_keypair structure to ease use with other
- *                  structures, such as ::mbedtls_ecdh_context or
- *                  ::mbedtls_ecdsa_context.
- *
- * \param grp       The ECP group to generate a key pair for.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param G         The base point to use. This must be initialized
- *                  and belong to \p grp. It replaces the default base
- *                  point \c grp->G used by mbedtls_ecp_gen_keypair().
- * \param d         The destination MPI (secret part).
- *                  This must be initialized.
- * \param Q         The destination point (public part).
- *                  This must be initialized.
- * \param f_rng     The RNG function. This must not be \c NULL.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may
- *                  be \c NULL if \p f_rng doesn't need a context argument.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code
- *                  on failure.
- */
-int mbedtls_ecp_gen_keypair_base( mbedtls_ecp_group *grp,
-                                  const mbedtls_ecp_point *G,
-                                  mbedtls_mpi *d, mbedtls_ecp_point *Q,
-                                  int (*f_rng)(void *, unsigned char *, size_t),
-                                  void *p_rng );
-
-/**
- * \brief           This function generates an ECP keypair.
- *
- * \note            This function uses bare components rather than an
- *                  ::mbedtls_ecp_keypair structure to ease use with other
- *                  structures, such as ::mbedtls_ecdh_context or
- *                  ::mbedtls_ecdsa_context.
- *
- * \param grp       The ECP group to generate a key pair for.
- *                  This must be initialized and have group parameters
- *                  set, for example through mbedtls_ecp_group_load().
- * \param d         The destination MPI (secret part).
- *                  This must be initialized.
- * \param Q         The destination point (public part).
- *                  This must be initialized.
- * \param f_rng     The RNG function. This must not be \c NULL.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may
- *                  be \c NULL if \p f_rng doesn't need a context argument.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code
- *                  on failure.
- */
-int mbedtls_ecp_gen_keypair( mbedtls_ecp_group *grp, mbedtls_mpi *d,
-                             mbedtls_ecp_point *Q,
-                             int (*f_rng)(void *, unsigned char *, size_t),
-                             void *p_rng );
-
-/**
- * \brief           This function generates an ECP key.
- *
- * \param grp_id    The ECP group identifier.
- * \param key       The destination key. This must be initialized.
- * \param f_rng     The RNG function to use. This must not be \c NULL.
- * \param p_rng     The RNG context to be passed to \p f_rng. This may
- *                  be \c NULL if \p f_rng doesn't need a context argument.
- *
- * \return          \c 0 on success.
- * \return          An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code
- *                  on failure.
- */
-int mbedtls_ecp_gen_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key,
-                         int (*f_rng)(void *, unsigned char *, size_t),
-                         void *p_rng );
-
-/**
- * \brief           This function checks that the keypair objects
- *                  \p pub and \p prv have the same group and the
- *                  same public point, and that the private key in
- *                  \p prv is consistent with the public key.
- *
- * \param pub       The keypair structure holding the public key. This
- *                  must be initialized. If it contains a private key, that
- *                  part is ignored.
- * \param prv       The keypair structure holding the full keypair.
- *                  This must be initialized.
- *
- * \return          \c 0 on success, meaning that the keys are valid and match.
- * \return          #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the keys are invalid or do not match.
- * \return          An \c MBEDTLS_ERR_ECP_XXX or an \c MBEDTLS_ERR_MPI_XXX
- *                  error code on calculation failure.
- */
-int mbedtls_ecp_check_pub_priv( const mbedtls_ecp_keypair *pub,
-                                const mbedtls_ecp_keypair *prv );
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          The ECP checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_ecp_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ecp.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ecp_internal.h b/tools/sdk/include/mbedtls/mbedtls/ecp_internal.h
deleted file mode 100644
index 4e9445ae444..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ecp_internal.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/**
- * \file ecp_internal.h
- *
- * \brief Function declarations for alternative implementation of elliptic curve
- * point arithmetic.
- */
-/*
- *  Copyright (C) 2016, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-/*
- * References:
- *
- * [1] BERNSTEIN, Daniel J. Curve25519: new Diffie-Hellman speed records.
- *     <http://cr.yp.to/ecdh/curve25519-20060209.pdf>
- *
- * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis
- *     for elliptic curve cryptosystems. In : Cryptographic Hardware and
- *     Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302.
- *     <http://link.springer.com/chapter/10.1007/3-540-48059-5_25>
- *
- * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to
- *     render ECC resistant against Side Channel Attacks. IACR Cryptology
- *     ePrint Archive, 2004, vol. 2004, p. 342.
- *     <http://eprint.iacr.org/2004/342.pdf>
- *
- * [4] Certicom Research. SEC 2: Recommended Elliptic Curve Domain Parameters.
- *     <http://www.secg.org/sec2-v2.pdf>
- *
- * [5] HANKERSON, Darrel, MENEZES, Alfred J., VANSTONE, Scott. Guide to Elliptic
- *     Curve Cryptography.
- *
- * [6] Digital Signature Standard (DSS), FIPS 186-4.
- *     <http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.186-4.pdf>
- *
- * [7] Elliptic Curve Cryptography (ECC) Cipher Suites for Transport Layer
- *     Security (TLS), RFC 4492.
- *     <https://tools.ietf.org/search/rfc4492>
- *
- * [8] <http://www.hyperelliptic.org/EFD/g1p/auto-shortw-jacobian.html>
- *
- * [9] COHEN, Henri. A Course in Computational Algebraic Number Theory.
- *     Springer Science & Business Media, 1 Aug 2000
- */
-
-#ifndef MBEDTLS_ECP_INTERNAL_H
-#define MBEDTLS_ECP_INTERNAL_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_ECP_INTERNAL_ALT)
-
-/**
- * \brief           Indicate if the Elliptic Curve Point module extension can
- *                  handle the group.
- *
- * \param grp       The pointer to the elliptic curve group that will be the
- *                  basis of the cryptographic computations.
- *
- * \return          Non-zero if successful.
- */
-unsigned char mbedtls_internal_ecp_grp_capable( const mbedtls_ecp_group *grp );
-
-/**
- * \brief           Initialise the Elliptic Curve Point module extension.
- *
- *                  If mbedtls_internal_ecp_grp_capable returns true for a
- *                  group, this function has to be able to initialise the
- *                  module for it.
- *
- *                  This module can be a driver to a crypto hardware
- *                  accelerator, for which this could be an initialise function.
- *
- * \param grp       The pointer to the group the module needs to be
- *                  initialised for.
- *
- * \return          0 if successful.
- */
-int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp );
-
-/**
- * \brief           Frees and deallocates the Elliptic Curve Point module
- *                  extension.
- *
- * \param grp       The pointer to the group the module was initialised for.
- */
-void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp );
-
-#if defined(ECP_SHORTWEIERSTRASS)
-
-#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT)
-/**
- * \brief           Randomize jacobian coordinates:
- *                  (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l.
- *
- * \param grp       Pointer to the group representing the curve.
- *
- * \param pt        The point on the curve to be randomised, given with Jacobian
- *                  coordinates.
- *
- * \param f_rng     A function pointer to the random number generator.
- *
- * \param p_rng     A pointer to the random number generator state.
- *
- * \return          0 if successful.
- */
-int mbedtls_internal_ecp_randomize_jac( const mbedtls_ecp_group *grp,
-        mbedtls_ecp_point *pt, int (*f_rng)(void *, unsigned char *, size_t),
-        void *p_rng );
-#endif
-
-#if defined(MBEDTLS_ECP_ADD_MIXED_ALT)
-/**
- * \brief           Addition: R = P + Q, mixed affine-Jacobian coordinates.
- *
- *                  The coordinates of Q must be normalized (= affine),
- *                  but those of P don't need to. R is not normalized.
- *
- *                  This function is used only as a subrutine of
- *                  ecp_mul_comb().
- *
- *                  Special cases: (1) P or Q is zero, (2) R is zero,
- *                      (3) P == Q.
- *                  None of these cases can happen as intermediate step in
- *                  ecp_mul_comb():
- *                      - at each step, P, Q and R are multiples of the base
- *                      point, the factor being less than its order, so none of
- *                      them is zero;
- *                      - Q is an odd multiple of the base point, P an even
- *                      multiple, due to the choice of precomputed points in the
- *                      modified comb method.
- *                  So branches for these cases do not leak secret information.
- *
- *                  We accept Q->Z being unset (saving memory in tables) as
- *                  meaning 1.
- *
- *                  Cost in field operations if done by [5] 3.22:
- *                      1A := 8M + 3S
- *
- * \param grp       Pointer to the group representing the curve.
- *
- * \param R         Pointer to a point structure to hold the result.
- *
- * \param P         Pointer to the first summand, given with Jacobian
- *                  coordinates
- *
- * \param Q         Pointer to the second summand, given with affine
- *                  coordinates.
- *
- * \return          0 if successful.
- */
-int mbedtls_internal_ecp_add_mixed( const mbedtls_ecp_group *grp,
-        mbedtls_ecp_point *R, const mbedtls_ecp_point *P,
-        const mbedtls_ecp_point *Q );
-#endif
-
-/**
- * \brief           Point doubling R = 2 P, Jacobian coordinates.
- *
- *                  Cost:   1D := 3M + 4S    (A ==  0)
- *                          4M + 4S          (A == -3)
- *                          3M + 6S + 1a     otherwise
- *                  when the implementation is based on the "dbl-1998-cmo-2"
- *                  doubling formulas in [8] and standard optimizations are
- *                  applied when curve parameter A is one of { 0, -3 }.
- *
- * \param grp       Pointer to the group representing the curve.
- *
- * \param R         Pointer to a point structure to hold the result.
- *
- * \param P         Pointer to the point that has to be doubled, given with
- *                  Jacobian coordinates.
- *
- * \return          0 if successful.
- */
-#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT)
-int mbedtls_internal_ecp_double_jac( const mbedtls_ecp_group *grp,
-        mbedtls_ecp_point *R, const mbedtls_ecp_point *P );
-#endif
-
-/**
- * \brief           Normalize jacobian coordinates of an array of (pointers to)
- *                  points.
- *
- *                  Using Montgomery's trick to perform only one inversion mod P
- *                  the cost is:
- *                      1N(t) := 1I + (6t - 3)M + 1S
- *                  (See for example Algorithm 10.3.4. in [9])
- *
- *                  This function is used only as a subrutine of
- *                  ecp_mul_comb().
- *
- *                  Warning: fails (returning an error) if one of the points is
- *                  zero!
- *                  This should never happen, see choice of w in ecp_mul_comb().
- *
- * \param grp       Pointer to the group representing the curve.
- *
- * \param T         Array of pointers to the points to normalise.
- *
- * \param t_len     Number of elements in the array.
- *
- * \return          0 if successful,
- *                      an error if one of the points is zero.
- */
-#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT)
-int mbedtls_internal_ecp_normalize_jac_many( const mbedtls_ecp_group *grp,
-        mbedtls_ecp_point *T[], size_t t_len );
-#endif
-
-/**
- * \brief           Normalize jacobian coordinates so that Z == 0 || Z == 1.
- *
- *                  Cost in field operations if done by [5] 3.2.1:
- *                      1N := 1I + 3M + 1S
- *
- * \param grp       Pointer to the group representing the curve.
- *
- * \param pt        pointer to the point to be normalised. This is an
- *                  input/output parameter.
- *
- * \return          0 if successful.
- */
-#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT)
-int mbedtls_internal_ecp_normalize_jac( const mbedtls_ecp_group *grp,
-        mbedtls_ecp_point *pt );
-#endif
-
-#endif /* ECP_SHORTWEIERSTRASS */
-
-#if defined(ECP_MONTGOMERY)
-
-#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT)
-int mbedtls_internal_ecp_double_add_mxz( const mbedtls_ecp_group *grp,
-        mbedtls_ecp_point *R, mbedtls_ecp_point *S, const mbedtls_ecp_point *P,
-        const mbedtls_ecp_point *Q, const mbedtls_mpi *d );
-#endif
-
-/**
- * \brief           Randomize projective x/z coordinates:
- *                      (X, Z) -> (l X, l Z) for random l
- *
- * \param grp       pointer to the group representing the curve
- *
- * \param P         the point on the curve to be randomised given with
- *                  projective coordinates. This is an input/output parameter.
- *
- * \param f_rng     a function pointer to the random number generator
- *
- * \param p_rng     a pointer to the random number generator state
- *
- * \return          0 if successful
- */
-#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT)
-int mbedtls_internal_ecp_randomize_mxz( const mbedtls_ecp_group *grp,
-        mbedtls_ecp_point *P, int (*f_rng)(void *, unsigned char *, size_t),
-        void *p_rng );
-#endif
-
-/**
- * \brief           Normalize Montgomery x/z coordinates: X = X/Z, Z = 1.
- *
- * \param grp       pointer to the group representing the curve
- *
- * \param P         pointer to the point to be normalised. This is an
- *                  input/output parameter.
- *
- * \return          0 if successful
- */
-#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT)
-int mbedtls_internal_ecp_normalize_mxz( const mbedtls_ecp_group *grp,
-        mbedtls_ecp_point *P );
-#endif
-
-#endif /* ECP_MONTGOMERY */
-
-#endif /* MBEDTLS_ECP_INTERNAL_ALT */
-
-#endif /* ecp_internal.h */
-
diff --git a/tools/sdk/include/mbedtls/mbedtls/entropy.h b/tools/sdk/include/mbedtls/mbedtls/entropy.h
deleted file mode 100644
index fd70cd7e9e0..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/entropy.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/**
- * \file entropy.h
- *
- * \brief Entropy accumulator implementation
- */
-/*
- *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_ENTROPY_H
-#define MBEDTLS_ENTROPY_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-#if defined(MBEDTLS_SHA512_C) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256)
-#include "sha512.h"
-#define MBEDTLS_ENTROPY_SHA512_ACCUMULATOR
-#else
-#if defined(MBEDTLS_SHA256_C)
-#define MBEDTLS_ENTROPY_SHA256_ACCUMULATOR
-#include "sha256.h"
-#endif
-#endif
-
-#if defined(MBEDTLS_THREADING_C)
-#include "threading.h"
-#endif
-
-#if defined(MBEDTLS_HAVEGE_C)
-#include "havege.h"
-#endif
-
-#define MBEDTLS_ERR_ENTROPY_SOURCE_FAILED                 -0x003C  /**< Critical entropy source failure. */
-#define MBEDTLS_ERR_ENTROPY_MAX_SOURCES                   -0x003E  /**< No more sources can be added. */
-#define MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED            -0x0040  /**< No sources have been added to poll. */
-#define MBEDTLS_ERR_ENTROPY_NO_STRONG_SOURCE              -0x003D  /**< No strong sources have been added to poll. */
-#define MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR                 -0x003F  /**< Read/write error in file. */
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h or define them on the compiler command line.
- * \{
- */
-
-#if !defined(MBEDTLS_ENTROPY_MAX_SOURCES)
-#define MBEDTLS_ENTROPY_MAX_SOURCES     20      /**< Maximum number of sources supported */
-#endif
-
-#if !defined(MBEDTLS_ENTROPY_MAX_GATHER)
-#define MBEDTLS_ENTROPY_MAX_GATHER      128     /**< Maximum amount requested from entropy sources */
-#endif
-
-/* \} name SECTION: Module settings */
-
-#if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR)
-#define MBEDTLS_ENTROPY_BLOCK_SIZE      64      /**< Block size of entropy accumulator (SHA-512) */
-#else
-#define MBEDTLS_ENTROPY_BLOCK_SIZE      32      /**< Block size of entropy accumulator (SHA-256) */
-#endif
-
-#define MBEDTLS_ENTROPY_MAX_SEED_SIZE   1024    /**< Maximum size of seed we read from seed file */
-#define MBEDTLS_ENTROPY_SOURCE_MANUAL   MBEDTLS_ENTROPY_MAX_SOURCES
-
-#define MBEDTLS_ENTROPY_SOURCE_STRONG   1       /**< Entropy source is strong   */
-#define MBEDTLS_ENTROPY_SOURCE_WEAK     0       /**< Entropy source is weak     */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief           Entropy poll callback pointer
- *
- * \param data      Callback-specific data pointer
- * \param output    Data to fill
- * \param len       Maximum size to provide
- * \param olen      The actual amount of bytes put into the buffer (Can be 0)
- *
- * \return          0 if no critical failures occurred,
- *                  MBEDTLS_ERR_ENTROPY_SOURCE_FAILED otherwise
- */
-typedef int (*mbedtls_entropy_f_source_ptr)(void *data, unsigned char *output, size_t len,
-                            size_t *olen);
-
-/**
- * \brief           Entropy source state
- */
-typedef struct mbedtls_entropy_source_state
-{
-    mbedtls_entropy_f_source_ptr    f_source;   /**< The entropy source callback */
-    void *          p_source;   /**< The callback data pointer */
-    size_t          size;       /**< Amount received in bytes */
-    size_t          threshold;  /**< Minimum bytes required before release */
-    int             strong;     /**< Is the source strong? */
-}
-mbedtls_entropy_source_state;
-
-/**
- * \brief           Entropy context structure
- */
-typedef struct mbedtls_entropy_context
-{
-    int accumulator_started;
-#if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR)
-    mbedtls_sha512_context  accumulator;
-#else
-    mbedtls_sha256_context  accumulator;
-#endif
-    int             source_count;
-    mbedtls_entropy_source_state    source[MBEDTLS_ENTROPY_MAX_SOURCES];
-#if defined(MBEDTLS_HAVEGE_C)
-    mbedtls_havege_state    havege_data;
-#endif
-#if defined(MBEDTLS_THREADING_C)
-    mbedtls_threading_mutex_t mutex;    /*!< mutex                  */
-#endif
-#if defined(MBEDTLS_ENTROPY_NV_SEED)
-    int initial_entropy_run;
-#endif
-}
-mbedtls_entropy_context;
-
-/**
- * \brief           Initialize the context
- *
- * \param ctx       Entropy context to initialize
- */
-void mbedtls_entropy_init( mbedtls_entropy_context *ctx );
-
-/**
- * \brief           Free the data in the context
- *
- * \param ctx       Entropy context to free
- */
-void mbedtls_entropy_free( mbedtls_entropy_context *ctx );
-
-/**
- * \brief           Adds an entropy source to poll
- *                  (Thread-safe if MBEDTLS_THREADING_C is enabled)
- *
- * \param ctx       Entropy context
- * \param f_source  Entropy function
- * \param p_source  Function data
- * \param threshold Minimum required from source before entropy is released
- *                  ( with mbedtls_entropy_func() ) (in bytes)
- * \param strong    MBEDTLS_ENTROPY_SOURCE_STRONG or
- *                  MBEDTLS_ENTROPY_SOURCE_WEAK.
- *                  At least one strong source needs to be added.
- *                  Weaker sources (such as the cycle counter) can be used as
- *                  a complement.
- *
- * \return          0 if successful or MBEDTLS_ERR_ENTROPY_MAX_SOURCES
- */
-int mbedtls_entropy_add_source( mbedtls_entropy_context *ctx,
-                        mbedtls_entropy_f_source_ptr f_source, void *p_source,
-                        size_t threshold, int strong );
-
-/**
- * \brief           Trigger an extra gather poll for the accumulator
- *                  (Thread-safe if MBEDTLS_THREADING_C is enabled)
- *
- * \param ctx       Entropy context
- *
- * \return          0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
- */
-int mbedtls_entropy_gather( mbedtls_entropy_context *ctx );
-
-/**
- * \brief           Retrieve entropy from the accumulator
- *                  (Maximum length: MBEDTLS_ENTROPY_BLOCK_SIZE)
- *                  (Thread-safe if MBEDTLS_THREADING_C is enabled)
- *
- * \param data      Entropy context
- * \param output    Buffer to fill
- * \param len       Number of bytes desired, must be at most MBEDTLS_ENTROPY_BLOCK_SIZE
- *
- * \return          0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
- */
-int mbedtls_entropy_func( void *data, unsigned char *output, size_t len );
-
-/**
- * \brief           Add data to the accumulator manually
- *                  (Thread-safe if MBEDTLS_THREADING_C is enabled)
- *
- * \param ctx       Entropy context
- * \param data      Data to add
- * \param len       Length of data
- *
- * \return          0 if successful
- */
-int mbedtls_entropy_update_manual( mbedtls_entropy_context *ctx,
-                           const unsigned char *data, size_t len );
-
-#if defined(MBEDTLS_ENTROPY_NV_SEED)
-/**
- * \brief           Trigger an update of the seed file in NV by using the
- *                  current entropy pool.
- *
- * \param ctx       Entropy context
- *
- * \return          0 if successful
- */
-int mbedtls_entropy_update_nv_seed( mbedtls_entropy_context *ctx );
-#endif /* MBEDTLS_ENTROPY_NV_SEED */
-
-#if defined(MBEDTLS_FS_IO)
-/**
- * \brief               Write a seed file
- *
- * \param ctx           Entropy context
- * \param path          Name of the file
- *
- * \return              0 if successful,
- *                      MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error, or
- *                      MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
- */
-int mbedtls_entropy_write_seed_file( mbedtls_entropy_context *ctx, const char *path );
-
-/**
- * \brief               Read and update a seed file. Seed is added to this
- *                      instance. No more than MBEDTLS_ENTROPY_MAX_SEED_SIZE bytes are
- *                      read from the seed file. The rest is ignored.
- *
- * \param ctx           Entropy context
- * \param path          Name of the file
- *
- * \return              0 if successful,
- *                      MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error,
- *                      MBEDTLS_ERR_ENTROPY_SOURCE_FAILED
- */
-int mbedtls_entropy_update_seed_file( mbedtls_entropy_context *ctx, const char *path );
-#endif /* MBEDTLS_FS_IO */
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief          Checkup routine
- *
- *                 This module self-test also calls the entropy self-test,
- *                 mbedtls_entropy_source_self_test();
- *
- * \return         0 if successful, or 1 if a test failed
- */
-int mbedtls_entropy_self_test( int verbose );
-
-#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT)
-/**
- * \brief          Checkup routine
- *
- *                 Verifies the integrity of the hardware entropy source
- *                 provided by the function 'mbedtls_hardware_poll()'.
- *
- *                 Note this is the only hardware entropy source that is known
- *                 at link time, and other entropy sources configured
- *                 dynamically at runtime by the function
- *                 mbedtls_entropy_add_source() will not be tested.
- *
- * \return         0 if successful, or 1 if a test failed
- */
-int mbedtls_entropy_source_self_test( int verbose );
-#endif /* MBEDTLS_ENTROPY_HARDWARE_ALT */
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* entropy.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h b/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h
deleted file mode 100644
index 9843a9e460b..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/entropy_poll.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/**
- * \file entropy_poll.h
- *
- * \brief Platform-specific and custom entropy polling functions
- */
-/*
- *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_ENTROPY_POLL_H
-#define MBEDTLS_ENTROPY_POLL_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Default thresholds for built-in sources, in bytes
- */
-#define MBEDTLS_ENTROPY_MIN_PLATFORM     32     /**< Minimum for platform source    */
-#define MBEDTLS_ENTROPY_MIN_HAVEGE       32     /**< Minimum for HAVEGE             */
-#define MBEDTLS_ENTROPY_MIN_HARDCLOCK     4     /**< Minimum for mbedtls_timing_hardclock()        */
-#if !defined(MBEDTLS_ENTROPY_MIN_HARDWARE)
-#define MBEDTLS_ENTROPY_MIN_HARDWARE     32     /**< Minimum for the hardware source */
-#endif
-
-/**
- * \brief           Entropy poll callback that provides 0 entropy.
- */
-#if defined(MBEDTLS_TEST_NULL_ENTROPY)
-    int mbedtls_null_entropy_poll( void *data,
-                                unsigned char *output, size_t len, size_t *olen );
-#endif
-
-#if !defined(MBEDTLS_NO_PLATFORM_ENTROPY)
-/**
- * \brief           Platform-specific entropy poll callback
- */
-int mbedtls_platform_entropy_poll( void *data,
-                           unsigned char *output, size_t len, size_t *olen );
-#endif
-
-#if defined(MBEDTLS_HAVEGE_C)
-/**
- * \brief           HAVEGE based entropy poll callback
- *
- * Requires an HAVEGE state as its data pointer.
- */
-int mbedtls_havege_poll( void *data,
-                 unsigned char *output, size_t len, size_t *olen );
-#endif
-
-#if defined(MBEDTLS_TIMING_C)
-/**
- * \brief           mbedtls_timing_hardclock-based entropy poll callback
- */
-int mbedtls_hardclock_poll( void *data,
-                    unsigned char *output, size_t len, size_t *olen );
-#endif
-
-#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT)
-/**
- * \brief           Entropy poll callback for a hardware source
- *
- * \warning         This is not provided by mbed TLS!
- *                  See \c MBEDTLS_ENTROPY_HARDWARE_ALT in config.h.
- *
- * \note            This must accept NULL as its first argument.
- */
-int mbedtls_hardware_poll( void *data,
-                           unsigned char *output, size_t len, size_t *olen );
-#endif
-
-#if defined(MBEDTLS_ENTROPY_NV_SEED)
-/**
- * \brief           Entropy poll callback for a non-volatile seed file
- *
- * \note            This must accept NULL as its first argument.
- */
-int mbedtls_nv_seed_poll( void *data,
-                          unsigned char *output, size_t len, size_t *olen );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* entropy_poll.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/error.h b/tools/sdk/include/mbedtls/mbedtls/error.h
deleted file mode 100644
index 3ee7bbba892..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/error.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/**
- * \file error.h
- *
- * \brief Error to string translation
- */
-/*
- *  Copyright (C) 2006-2018, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_ERROR_H
-#define MBEDTLS_ERROR_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-/**
- * Error code layout.
- *
- * Currently we try to keep all error codes within the negative space of 16
- * bits signed integers to support all platforms (-0x0001 - -0x7FFF). In
- * addition we'd like to give two layers of information on the error if
- * possible.
- *
- * For that purpose the error codes are segmented in the following manner:
- *
- * 16 bit error code bit-segmentation
- *
- * 1 bit  - Unused (sign bit)
- * 3 bits - High level module ID
- * 5 bits - Module-dependent error code
- * 7 bits - Low level module errors
- *
- * For historical reasons, low-level error codes are divided in even and odd,
- * even codes were assigned first, and -1 is reserved for other errors.
- *
- * Low-level module errors (0x0002-0x007E, 0x0003-0x007F)
- *
- * Module   Nr  Codes assigned
- * MPI       7  0x0002-0x0010
- * GCM       3  0x0012-0x0014   0x0013-0x0013
- * BLOWFISH  3  0x0016-0x0018   0x0017-0x0017
- * THREADING 3  0x001A-0x001E
- * AES       5  0x0020-0x0022   0x0021-0x0025
- * CAMELLIA  3  0x0024-0x0026   0x0027-0x0027
- * XTEA      2  0x0028-0x0028   0x0029-0x0029
- * BASE64    2  0x002A-0x002C
- * OID       1  0x002E-0x002E   0x000B-0x000B
- * PADLOCK   1  0x0030-0x0030
- * DES       2  0x0032-0x0032   0x0033-0x0033
- * CTR_DBRG  4  0x0034-0x003A
- * ENTROPY   3  0x003C-0x0040   0x003D-0x003F
- * NET      13  0x0042-0x0052   0x0043-0x0049
- * ARIA      4  0x0058-0x005E
- * ASN1      7  0x0060-0x006C
- * CMAC      1  0x007A-0x007A
- * PBKDF2    1  0x007C-0x007C
- * HMAC_DRBG 4                  0x0003-0x0009
- * CCM       3                  0x000D-0x0011
- * ARC4      1                  0x0019-0x0019
- * MD2       1                  0x002B-0x002B
- * MD4       1                  0x002D-0x002D
- * MD5       1                  0x002F-0x002F
- * RIPEMD160 1                  0x0031-0x0031
- * SHA1      1                  0x0035-0x0035 0x0073-0x0073
- * SHA256    1                  0x0037-0x0037 0x0074-0x0074
- * SHA512    1                  0x0039-0x0039 0x0075-0x0075
- * CHACHA20  3                  0x0051-0x0055
- * POLY1305  3                  0x0057-0x005B
- * CHACHAPOLY 2 0x0054-0x0056
- * PLATFORM  1  0x0070-0x0072
- *
- * High-level module nr (3 bits - 0x0...-0x7...)
- * Name      ID  Nr of Errors
- * PEM       1   9
- * PKCS#12   1   4 (Started from top)
- * X509      2   20
- * PKCS5     2   4 (Started from top)
- * DHM       3   11
- * PK        3   15 (Started from top)
- * RSA       4   11
- * ECP       4   10 (Started from top)
- * MD        5   5
- * HKDF      5   1 (Started from top)
- * SSL       5   1 (Started from 0x5E80)
- * CIPHER    6   8
- * SSL       6   23 (Started from top)
- * SSL       7   32
- *
- * Module dependent error code (5 bits 0x.00.-0x.F8.)
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief Translate a mbed TLS error code into a string representation,
- *        Result is truncated if necessary and always includes a terminating
- *        null byte.
- *
- * \param errnum    error code
- * \param buffer    buffer to place representation in
- * \param buflen    length of the buffer
- */
-void mbedtls_strerror( int errnum, char *buffer, size_t buflen );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* error.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/esp_config.h b/tools/sdk/include/mbedtls/mbedtls/esp_config.h
deleted file mode 100644
index 85f2abe37de..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/esp_config.h
+++ /dev/null
@@ -1,2760 +0,0 @@
-/**
- *
- * \brief Default mbedTLS configuration options for esp-idf
- *
- *  This set of compile-time options may be used to enable
- *  or disable features selectively, and reduce the global
- *  memory footprint.
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-#include "sdkconfig.h"
-
-#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE)
-#define _CRT_SECURE_NO_DEPRECATE 1
-#endif
-
-/**
- * \name SECTION: System support
- *
- * This section sets system specific settings.
- * \{
- */
-
-/**
- * \def MBEDTLS_HAVE_ASM
- *
- * The compiler has support for asm().
- *
- * Requires support for asm() in compiler.
- *
- * Used in:
- *      library/timing.c
- *      library/padlock.c
- *      include/mbedtls/bn_mul.h
- *
- * Comment to disable the use of assembly code.
- */
-#define MBEDTLS_HAVE_ASM
-
-/**
- * \def MBEDTLS_HAVE_SSE2
- *
- * CPU supports SSE2 instruction set.
- *
- * Uncomment if the CPU supports SSE2 (IA-32 specific).
- */
-//#define MBEDTLS_HAVE_SSE2
-
-/**
- * \def MBEDTLS_HAVE_TIME
- *
- * System has time.h and time().
- * The time does not need to be correct, only time differences are used,
- * by contrast with MBEDTLS_HAVE_TIME_DATE
- *
- * Comment if your system does not support time functions
- */
-#ifdef CONFIG_MBEDTLS_HAVE_TIME
-#define MBEDTLS_HAVE_TIME
-#endif
-
-/**
- * \def MBEDTLS_HAVE_TIME_DATE
- *
- * System has time.h and time(), gmtime() and the clock is correct.
- * The time needs to be correct (not necesarily very accurate, but at least
- * the date should be correct). This is used to verify the validity period of
- * X.509 certificates.
- *
- * Comment if your system does not have a correct clock.
- */
-#ifdef CONFIG_MBEDTLS_HAVE_TIME_DATE
-#define MBEDTLS_HAVE_TIME_DATE
-#endif
-
-/**
- * \def MBEDTLS_PLATFORM_MEMORY
- *
- * Enable the memory allocation layer.
- *
- * By default mbed TLS uses the system-provided calloc() and free().
- * This allows different allocators (self-implemented or provided) to be
- * provided to the platform abstraction layer.
- *
- * Enabling MBEDTLS_PLATFORM_MEMORY without the
- * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide
- * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and
- * free() function pointer at runtime.
- *
- * Enabling MBEDTLS_PLATFORM_MEMORY and specifying
- * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the
- * alternate function at compile time.
- *
- * Requires: MBEDTLS_PLATFORM_C
- *
- * Enable this layer to allow use of alternative memory allocators.
- */
-#define MBEDTLS_PLATFORM_MEMORY
-
-/** Override calloc(), free() except for case where memory allocation scheme is not set to custom */
-#ifndef CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC
-#include "esp_mem.h"
-#define MBEDTLS_PLATFORM_STD_CALLOC		esp_mbedtls_mem_calloc
-#define MBEDTLS_PLATFORM_STD_FREE		esp_mbedtls_mem_free
-#endif
-
-/**
- * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
- *
- * Do not assign standard functions in the platform layer (e.g. calloc() to
- * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF)
- *
- * This makes sure there are no linking errors on platforms that do not support
- * these functions. You will HAVE to provide alternatives, either at runtime
- * via the platform_set_xxx() functions or at compile time by setting
- * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a
- * MBEDTLS_PLATFORM_XXX_MACRO.
- *
- * Requires: MBEDTLS_PLATFORM_C
- *
- * Uncomment to prevent default assignment of standard functions in the
- * platform layer.
- */
-//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-
-/**
- * \def MBEDTLS_PLATFORM_EXIT_ALT
- *
- * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the
- * function in the platform abstraction layer.
- *
- * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will
- * provide a function "mbedtls_platform_set_printf()" that allows you to set an
- * alternative printf function pointer.
- *
- * All these define require MBEDTLS_PLATFORM_C to be defined!
- *
- * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows;
- * it will be enabled automatically by check_config.h
- *
- * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as
- * MBEDTLS_PLATFORM_XXX_MACRO!
- *
- * Uncomment a macro to enable alternate implementation of specific base
- * platform function
- */
-//#define MBEDTLS_PLATFORM_EXIT_ALT
-//#define MBEDTLS_PLATFORM_FPRINTF_ALT
-//#define MBEDTLS_PLATFORM_PRINTF_ALT
-//#define MBEDTLS_PLATFORM_SNPRINTF_ALT
-
-/**
- * \def MBEDTLS_DEPRECATED_WARNING
- *
- * Mark deprecated functions so that they generate a warning if used.
- * Functions deprecated in one version will usually be removed in the next
- * version. You can enable this to help you prepare the transition to a new
- * major version by making sure your code is not using these functions.
- *
- * This only works with GCC and Clang. With other compilers, you may want to
- * use MBEDTLS_DEPRECATED_REMOVED
- *
- * Uncomment to get warnings on using deprecated functions.
- */
-//#define MBEDTLS_DEPRECATED_WARNING
-
-/**
- * \def MBEDTLS_DEPRECATED_REMOVED
- *
- * Remove deprecated functions so that they generate an error if used.
- * Functions deprecated in one version will usually be removed in the next
- * version. You can enable this to help you prepare the transition to a new
- * major version by making sure your code is not using these functions.
- *
- * Uncomment to get errors on using deprecated functions.
- */
-//#define MBEDTLS_DEPRECATED_REMOVED
-
-/* \} name SECTION: System support */
-
-/**
- * \name SECTION: mbed TLS feature support
- *
- * This section sets support for features that are or are not needed
- * within the modules that are enabled.
- * \{
- */
-
-/**
- * \def MBEDTLS_TIMING_ALT
- *
- * Uncomment to provide your own alternate implementation for mbedtls_timing_hardclock(),
- * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay()
- *
- * Only works if you have MBEDTLS_TIMING_C enabled.
- *
- * You will need to provide a header "timing_alt.h" and an implementation at
- * compile time.
- */
-//#define MBEDTLS_TIMING_ALT
-
-/**
- * \def MBEDTLS_AES_ALT
- *
- * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your
- * alternate core implementation of a symmetric crypto or hash module (e.g.
- * platform specific assembly optimized implementations). Keep in mind that
- * the function prototypes should remain the same.
- *
- * This replaces the whole module. If you only want to replace one of the
- * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags.
- *
- * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer
- * provide the "struct mbedtls_aes_context" definition and omit the base function
- * declarations and implementations. "aes_alt.h" will be included from
- * "aes.h" to include the new function definitions.
- *
- * Uncomment a macro to enable alternate implementation of the corresponding
- * module.
- */
-//#define MBEDTLS_ARC4_ALT
-//#define MBEDTLS_BLOWFISH_ALT
-//#define MBEDTLS_CAMELLIA_ALT
-//#define MBEDTLS_DES_ALT
-//#define MBEDTLS_XTEA_ALT
-//#define MBEDTLS_MD2_ALT
-//#define MBEDTLS_MD4_ALT
-//#define MBEDTLS_MD5_ALT
-//#define MBEDTLS_RIPEMD160_ALT
-
-/* The following units have ESP32 hardware support,
-   uncommenting each _ALT macro will use the
-   hardware-accelerated implementation. */
-#ifdef CONFIG_MBEDTLS_HARDWARE_AES
-#define MBEDTLS_AES_ALT
-#endif
-
-/* MBEDTLS_SHAxx_ALT to enable hardware SHA support
-   with software fallback.
-*/
-#ifdef CONFIG_MBEDTLS_HARDWARE_SHA
-#define MBEDTLS_SHA1_ALT
-#define MBEDTLS_SHA256_ALT
-#define MBEDTLS_SHA512_ALT
-#endif
-
-/* The following MPI (bignum) functions have ESP32 hardware support,
-   Uncommenting these macros will use the hardware-accelerated
-   implementations.
-*/
-#ifdef CONFIG_MBEDTLS_HARDWARE_MPI
-#define MBEDTLS_MPI_EXP_MOD_ALT
-#define MBEDTLS_MPI_MUL_MPI_ALT
-#endif
-
-/**
- * \def MBEDTLS_MD2_PROCESS_ALT
- *
- * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you
- * alternate core implementation of symmetric crypto or hash function. Keep in
- * mind that function prototypes should remain the same.
- *
- * This replaces only one function. The header file from mbed TLS is still
- * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags.
- *
- * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will
- * no longer provide the mbedtls_sha1_process() function, but it will still provide
- * the other function (using your mbedtls_sha1_process() function) and the definition
- * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible
- * with this definition.
- *
- * Note: if you use the AES_xxx_ALT macros, then is is recommended to also set
- * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES
- * tables.
- *
- * Uncomment a macro to enable alternate implementation of the corresponding
- * function.
- */
-//#define MBEDTLS_MD2_PROCESS_ALT
-//#define MBEDTLS_MD4_PROCESS_ALT
-//#define MBEDTLS_MD5_PROCESS_ALT
-//#define MBEDTLS_RIPEMD160_PROCESS_ALT
-//#define MBEDTLS_SHA1_PROCESS_ALT
-//#define MBEDTLS_SHA256_PROCESS_ALT
-//#define MBEDTLS_SHA512_PROCESS_ALT
-//#define MBEDTLS_DES_SETKEY_ALT
-//#define MBEDTLS_DES_CRYPT_ECB_ALT
-//#define MBEDTLS_DES3_CRYPT_ECB_ALT
-//#define MBEDTLS_AES_SETKEY_ENC_ALT
-//#define MBEDTLS_AES_SETKEY_DEC_ALT
-//#define MBEDTLS_AES_ENCRYPT_ALT
-//#define MBEDTLS_AES_DECRYPT_ALT
-
-/**
- * \def MBEDTLS_ENTROPY_HARDWARE_ALT
- *
- * Uncomment this macro to let mbed TLS use your own implementation of a
- * hardware entropy collector.
- *
- * Your function must be called \c mbedtls_hardware_poll(), have the same
- * prototype as declared in entropy_poll.h, and accept NULL as first argument.
- *
- * Uncomment to use your own hardware entropy collector.
- */
-#define MBEDTLS_ENTROPY_HARDWARE_ALT
-
-/**
- * \def MBEDTLS_AES_ROM_TABLES
- *
- * Store the AES tables in ROM.
- *
- * Uncomment this macro to store the AES tables in ROM.
- */
-#define MBEDTLS_AES_ROM_TABLES
-
-/**
- * \def MBEDTLS_CAMELLIA_SMALL_MEMORY
- *
- * Use less ROM for the Camellia implementation (saves about 768 bytes).
- *
- * Uncomment this macro to use less memory for Camellia.
- */
-//#define MBEDTLS_CAMELLIA_SMALL_MEMORY
-
-/**
- * \def MBEDTLS_CIPHER_MODE_CBC
- *
- * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers.
- */
-#define MBEDTLS_CIPHER_MODE_CBC
-
-/**
- * \def MBEDTLS_CIPHER_MODE_CFB
- *
- * Enable Cipher Feedback mode (CFB) for symmetric ciphers.
- */
-#define MBEDTLS_CIPHER_MODE_CFB
-
-/**
- * \def MBEDTLS_CIPHER_MODE_CTR
- *
- * Enable Counter Block Cipher mode (CTR) for symmetric ciphers.
- */
-#define MBEDTLS_CIPHER_MODE_CTR
-
-/**
- * \def MBEDTLS_CIPHER_MODE_XTS
- *
- * Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES.
- */
-#define MBEDTLS_CIPHER_MODE_XTS
-
-/**
- * \def MBEDTLS_CIPHER_NULL_CIPHER
- *
- * Enable NULL cipher.
- * Warning: Only do so when you know what you are doing. This allows for
- * encryption or channels without any security!
- *
- * Requires MBEDTLS_ENABLE_WEAK_CIPHERSUITES as well to enable
- * the following ciphersuites:
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA
- *      MBEDTLS_TLS_RSA_WITH_NULL_SHA256
- *      MBEDTLS_TLS_RSA_WITH_NULL_SHA
- *      MBEDTLS_TLS_RSA_WITH_NULL_MD5
- *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA
- *      MBEDTLS_TLS_PSK_WITH_NULL_SHA384
- *      MBEDTLS_TLS_PSK_WITH_NULL_SHA256
- *      MBEDTLS_TLS_PSK_WITH_NULL_SHA
- *
- * Uncomment this macro to enable the NULL cipher and ciphersuites
- */
-//#define MBEDTLS_CIPHER_NULL_CIPHER
-
-/**
- * \def MBEDTLS_CIPHER_PADDING_PKCS7
- *
- * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for
- * specific padding modes in the cipher layer with cipher modes that support
- * padding (e.g. CBC)
- *
- * If you disable all padding modes, only full blocks can be used with CBC.
- *
- * Enable padding modes in the cipher layer.
- */
-#define MBEDTLS_CIPHER_PADDING_PKCS7
-#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS
-#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN
-#define MBEDTLS_CIPHER_PADDING_ZEROS
-
-/**
- * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES
- *
- * Enable weak ciphersuites in SSL / TLS.
- * Warning: Only do so when you know what you are doing. This allows for
- * channels with virtually no security at all!
- *
- * This enables the following ciphersuites:
- *      MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA
- *
- * Uncomment this macro to enable weak ciphersuites
- */
-//#define MBEDTLS_ENABLE_WEAK_CIPHERSUITES
-
-/**
- * \def MBEDTLS_REMOVE_ARC4_CIPHERSUITES
- *
- * Remove RC4 ciphersuites by default in SSL / TLS.
- * This flag removes the ciphersuites based on RC4 from the default list as
- * returned by mbedtls_ssl_list_ciphersuites(). However, it is still possible to
- * enable (some of) them with mbedtls_ssl_conf_ciphersuites() by including them
- * explicitly.
- *
- * Uncomment this macro to remove RC4 ciphersuites by default.
- */
-#ifdef CONFIG_MBEDTLS_RC4_ENABLED
-#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES
-#endif
-
-/**
- * \def MBEDTLS_ECP_RESTARTABLE
- *
- * Enable "non-blocking" ECC operations that can return early and be resumed.
- *
- * This allows various functions to pause by returning
- * #MBEDTLS_ERR_ECP_IN_PROGRESS (or, for functions in the SSL module,
- * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS) and then be called later again in
- * order to further progress and eventually complete their operation. This is
- * controlled through mbedtls_ecp_set_max_ops() which limits the maximum
- * number of ECC operations a function may perform before pausing; see
- * mbedtls_ecp_set_max_ops() for more information.
- *
- * This is useful in non-threaded environments if you want to avoid blocking
- * for too long on ECC (and, hence, X.509 or SSL/TLS) operations.
- *
- * Uncomment this macro to enable restartable ECC computations.
- *
- * \note  This option only works with the default software implementation of
- *        elliptic curve functionality. It is incompatible with
- *        MBEDTLS_ECP_ALT, MBEDTLS_ECDH_XXX_ALT and MBEDTLS_ECDSA_XXX_ALT.
- */
-#ifdef CONFIG_MBEDTLS_ECP_RESTARTABLE
-#define MBEDTLS_ECP_RESTARTABLE
-#endif
-
-/**
- * \def MBEDTLS_CMAC_C
- *
- * Enable the CMAC (Cipher-based Message Authentication Code) mode for block
- * ciphers.
- *
- * Module:  library/cmac.c
- *
- * Requires: MBEDTLS_AES_C or MBEDTLS_DES_C
- *
- */
-#ifdef CONFIG_MBEDTLS_CMAC_C
-#define MBEDTLS_CMAC_C
-#endif
-
-/**
- * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED
- *
- * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve
- * module.  By default all supported curves are enabled.
- *
- * Comment macros to disable the curve and functions for it
- */
-#ifdef CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP192R1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP521R1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED
-#define MBEDTLS_ECP_DP_SECP192K1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED
-#define MBEDTLS_ECP_DP_SECP224K1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED
-#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED
-#define MBEDTLS_ECP_DP_BP256R1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED
-#define MBEDTLS_ECP_DP_BP384R1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED
-#define MBEDTLS_ECP_DP_BP512R1_ENABLED
-#endif
-#ifdef CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED
-#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_ECP_NIST_OPTIM
- *
- * Enable specific 'modulo p' routines for each NIST prime.
- * Depending on the prime and architecture, makes operations 4 to 8 times
- * faster on the corresponding curve.
- *
- * Comment this macro to disable NIST curves optimisation.
- */
-#ifdef CONFIG_MBEDTLS_ECP_NIST_OPTIM
-#define MBEDTLS_ECP_NIST_OPTIM
-#endif
-
-/**
- * \def MBEDTLS_ECDSA_DETERMINISTIC
- *
- * Enable deterministic ECDSA (RFC 6979).
- * Standard ECDSA is "fragile" in the sense that lack of entropy when signing
- * may result in a compromise of the long-term signing key. This is avoided by
- * the deterministic variant.
- *
- * Requires: MBEDTLS_HMAC_DRBG_C
- *
- * Comment this macro to disable deterministic ECDSA.
- */
-#define MBEDTLS_ECDSA_DETERMINISTIC
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
- *
- * Enable the PSK based ciphersuite modes in SSL / TLS.
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_PSK
-#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
- *
- * Enable the DHE-PSK based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_DHM_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK
-#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
- *
- * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
- *
- * Enable the RSA-PSK based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
- *           MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK
-#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
- *
- * Enable the RSA-only based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
- *           MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_RSA
-#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
- *
- * Enable the DHE-RSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
- *           MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA
-#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
- *
- * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15,
- *           MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
- *
- * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C,
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
- *
- * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA
-#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
- *
- * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS.
- *
- * Requires: MBEDTLS_ECDH_C, MBEDTLS_X509_CRT_PARSE_C
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
- */
-#ifdef CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA
-#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
-#endif
-
-/**
- * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
- *
- * Enable the ECJPAKE based ciphersuite modes in SSL / TLS.
- *
- * \warning This is currently experimental. EC J-PAKE support is based on the
- * Thread v1.0.0 specification; incompatible changes to the specification
- * might still happen. For this reason, this is disabled by default.
- *
- * Requires: MBEDTLS_ECJPAKE_C
- *           MBEDTLS_SHA256_C
- *           MBEDTLS_ECP_DP_SECP256R1_ENABLED
- *
- * This enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
- */
-//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
-
-/**
- * \def MBEDTLS_PK_PARSE_EC_EXTENDED
- *
- * Enhance support for reading EC keys using variants of SEC1 not allowed by
- * RFC 5915 and RFC 5480.
- *
- * Currently this means parsing the SpecifiedECDomain choice of EC
- * parameters (only known groups are supported, not arbitrary domains, to
- * avoid validation issues).
- *
- * Disable if you only need to support RFC 5915 + 5480 key formats.
- */
-#define MBEDTLS_PK_PARSE_EC_EXTENDED
-
-/**
- * \def MBEDTLS_ERROR_STRERROR_DUMMY
- *
- * Enable a dummy error function to make use of mbedtls_strerror() in
- * third party libraries easier when MBEDTLS_ERROR_C is disabled
- * (no effect when MBEDTLS_ERROR_C is enabled).
- *
- * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're
- * not using mbedtls_strerror() or error_strerror() in your application.
- *
- * Disable if you run into name conflicts and want to really remove the
- * mbedtls_strerror()
- */
-#define MBEDTLS_ERROR_STRERROR_DUMMY
-
-/**
- * \def MBEDTLS_GENPRIME
- *
- * Enable the prime-number generation code.
- *
- * Requires: MBEDTLS_BIGNUM_C
- */
-#define MBEDTLS_GENPRIME
-
-/**
- * \def MBEDTLS_FS_IO
- *
- * Enable functions that use the filesystem.
- */
-#define MBEDTLS_FS_IO
-
-/**
- * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
- *
- * Do not add default entropy sources. These are the platform specific,
- * mbedtls_timing_hardclock and HAVEGE based poll functions.
- *
- * This is useful to have more control over the added entropy sources in an
- * application.
- *
- * Uncomment this macro to prevent loading of default entropy functions.
- */
-//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-
-/**
- * \def MBEDTLS_NO_PLATFORM_ENTROPY
- *
- * Do not use built-in platform entropy functions.
- * This is useful if your platform does not support
- * standards like the /dev/urandom or Windows CryptoAPI.
- *
- * Uncomment this macro to disable the built-in platform entropy functions.
- */
-#define MBEDTLS_NO_PLATFORM_ENTROPY
-
-/**
- * \def MBEDTLS_ENTROPY_FORCE_SHA256
- *
- * Force the entropy accumulator to use a SHA-256 accumulator instead of the
- * default SHA-512 based one (if both are available).
- *
- * Requires: MBEDTLS_SHA256_C
- *
- * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option
- * if you have performance concerns.
- *
- * This option is only useful if both MBEDTLS_SHA256_C and
- * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used.
- */
-//#define MBEDTLS_ENTROPY_FORCE_SHA256
-
-/**
- * \def MBEDTLS_MEMORY_DEBUG
- *
- * Enable debugging of buffer allocator memory issues. Automatically prints
- * (to stderr) all (fatal) messages on memory allocation issues. Enables
- * function for 'debug output' of allocated memory.
- *
- * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
- *
- * Uncomment this macro to let the buffer allocator print out error messages.
- */
-//#define MBEDTLS_MEMORY_DEBUG
-
-/**
- * \def MBEDTLS_MEMORY_BACKTRACE
- *
- * Include backtrace information with each allocated block.
- *
- * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C
- *           GLIBC-compatible backtrace() an backtrace_symbols() support
- *
- * Uncomment this macro to include backtrace information
- */
-//#define MBEDTLS_MEMORY_BACKTRACE
-
-/**
- * \def MBEDTLS_PK_RSA_ALT_SUPPORT
- *
- * Support external private RSA keys (eg from a HSM) in the PK layer.
- *
- * Comment this macro to disable support for external private RSA keys.
- */
-#define MBEDTLS_PK_RSA_ALT_SUPPORT
-
-/**
- * \def MBEDTLS_PKCS1_V15
- *
- * Enable support for PKCS#1 v1.5 encoding.
- *
- * Requires: MBEDTLS_RSA_C
- *
- * This enables support for PKCS#1 v1.5 operations.
- */
-#define MBEDTLS_PKCS1_V15
-
-/**
- * \def MBEDTLS_PKCS1_V21
- *
- * Enable support for PKCS#1 v2.1 encoding.
- *
- * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C
- *
- * This enables support for RSAES-OAEP and RSASSA-PSS operations.
- */
-#define MBEDTLS_PKCS1_V21
-
-/**
- * \def MBEDTLS_RSA_NO_CRT
- *
- * Do not use the Chinese Remainder Theorem for the RSA private operation.
- *
- * Uncomment this macro to disable the use of CRT in RSA.
- *
- */
-//#define MBEDTLS_RSA_NO_CRT
-
-/**
- * \def MBEDTLS_SELF_TEST
- *
- * Enable the checkup functions (*_self_test).
- */
-#define MBEDTLS_SELF_TEST
-
-/**
- * \def MBEDTLS_SHA256_SMALLER
- *
- * Enable an implementation of SHA-256 that has lower ROM footprint but also
- * lower performance.
- *
- * The default implementation is meant to be a reasonnable compromise between
- * performance and size. This version optimizes more aggressively for size at
- * the expense of performance. Eg on Cortex-M4 it reduces the size of
- * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about
- * 30%.
- *
- * Uncomment to enable the smaller implementation of SHA256.
- */
-//#define MBEDTLS_SHA256_SMALLER
-
-/**
- * \def MBEDTLS_SSL_AEAD_RANDOM_IV
- *
- * Generate a random IV rather than using the record sequence number as a
- * nonce for ciphersuites using and AEAD algorithm (GCM or CCM).
- *
- * Using the sequence number is generally recommended.
- *
- * Uncomment this macro to always use random IVs with AEAD ciphersuites.
- */
-//#define MBEDTLS_SSL_AEAD_RANDOM_IV
-
-/**
- * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES
- *
- * Enable sending of alert messages in case of encountered errors as per RFC.
- * If you choose not to send the alert messages, mbed TLS can still communicate
- * with other servers, only debugging of failures is harder.
- *
- * The advantage of not sending alert messages, is that no information is given
- * about reasons for failures thus preventing adversaries of gaining intel.
- *
- * Enable sending of all alert messages
- */
-#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
-
-/**
- * \def MBEDTLS_SSL_DEBUG_ALL
- *
- * Enable the debug messages in SSL module for all issues.
- * Debug messages have been disabled in some places to prevent timing
- * attacks due to (unbalanced) debugging function calls.
- *
- * If you need all error reporting you should enable this during debugging,
- * but remove this for production servers that should log as well.
- *
- * Uncomment this macro to report all debug messages on errors introducing
- * a timing side-channel.
- *
- */
-//#define MBEDTLS_SSL_DEBUG_ALL
-
-/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC
- *
- * Enable support for Encrypt-then-MAC, RFC 7366.
- *
- * This allows peers that both support it to use a more robust protection for
- * ciphersuites using CBC, providing deep resistance against timing attacks
- * on the padding or underlying cipher.
- *
- * This only affects CBC ciphersuites, and is useless if none is defined.
- *
- * Requires: MBEDTLS_SSL_PROTO_TLS1    or
- *           MBEDTLS_SSL_PROTO_TLS1_1  or
- *           MBEDTLS_SSL_PROTO_TLS1_2
- *
- * Comment this macro to disable support for Encrypt-then-MAC
- */
-#ifdef CONFIG_MBEDTLS_TLS_ENABLED
-#define MBEDTLS_SSL_ENCRYPT_THEN_MAC
-#endif
-
-/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET
- *
- * Enable support for Extended Master Secret, aka Session Hash
- * (draft-ietf-tls-session-hash-02).
- *
- * This was introduced as "the proper fix" to the Triple Handshake familiy of
- * attacks, but it is recommended to always use it (even if you disable
- * renegotiation), since it actually fixes a more fundamental issue in the
- * original SSL/TLS design, and has implications beyond Triple Handshake.
- *
- * Requires: MBEDTLS_SSL_PROTO_TLS1    or
- *           MBEDTLS_SSL_PROTO_TLS1_1  or
- *           MBEDTLS_SSL_PROTO_TLS1_2
- *
- * Comment this macro to disable support for Extended Master Secret.
- */
-#ifdef CONFIG_MBEDTLS_TLS_ENABLED
-#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET
-#endif
-
-/**
- * \def MBEDTLS_SSL_FALLBACK_SCSV
- *
- * Enable support for FALLBACK_SCSV (draft-ietf-tls-downgrade-scsv-00).
- *
- * For servers, it is recommended to always enable this, unless you support
- * only one version of TLS, or know for sure that none of your clients
- * implements a fallback strategy.
- *
- * For clients, you only need this if you're using a fallback strategy, which
- * is not recommended in the first place, unless you absolutely need it to
- * interoperate with buggy (version-intolerant) servers.
- *
- * Comment this macro to disable support for FALLBACK_SCSV
- */
-#define MBEDTLS_SSL_FALLBACK_SCSV
-
-/**
- * \def MBEDTLS_SSL_HW_RECORD_ACCEL
- *
- * Enable hooking functions in SSL module for hardware acceleration of
- * individual records.
- *
- * Uncomment this macro to enable hooking functions.
- */
-//#define MBEDTLS_SSL_HW_RECORD_ACCEL
-
-/**
- * \def MBEDTLS_SSL_CBC_RECORD_SPLITTING
- *
- * Enable 1/n-1 record splitting for CBC mode in SSLv3 and TLS 1.0.
- *
- * This is a countermeasure to the BEAST attack, which also minimizes the risk
- * of interoperability issues compared to sending 0-length records.
- *
- * Comment this macro to disable 1/n-1 record splitting.
- */
-#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1)
-#define MBEDTLS_SSL_CBC_RECORD_SPLITTING
-#endif
-
-/**
- * \def MBEDTLS_SSL_RENEGOTIATION
- *
- * Disable support for TLS renegotiation.
- *
- * The two main uses of renegotiation are (1) refresh keys on long-lived
- * connections and (2) client authentication after the initial handshake.
- * If you don't need renegotiation, it's probably better to disable it, since
- * it has been associated with security issues in the past and is easy to
- * misuse/misunderstand.
- *
- * Comment this to disable support for renegotiation.
- */
-#ifdef CONFIG_MBEDTLS_SSL_RENEGOTIATION
-#define MBEDTLS_SSL_RENEGOTIATION
-#endif
-
-/**
- * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
- *
- * Enable support for receiving and parsing SSLv2 Client Hello messages for the
- * SSL Server module (MBEDTLS_SSL_SRV_C).
- *
- * Uncomment this macro to enable support for SSLv2 Client Hello messages.
- */
-//#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO
-
-/**
- * \def MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
- *
- * Pick the ciphersuite according to the client's preferences rather than ours
- * in the SSL Server module (MBEDTLS_SSL_SRV_C).
- *
- * Uncomment this macro to respect client's ciphersuite order
- */
-//#define MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE
-
-/**
- * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
- *
- * Enable support for RFC 6066 max_fragment_length extension in SSL.
- *
- * Comment this macro to disable support for the max_fragment_length extension
- */
-#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
-
-/**
- * \def MBEDTLS_SSL_PROTO_SSL3
- *
- * Enable support for SSL 3.0.
- *
- * Requires: MBEDTLS_MD5_C
- *           MBEDTLS_SHA1_C
- *
- * Comment this macro to disable support for SSL 3.0
- */
-#ifdef CONFIG_MBEDTLS_SSL_PROTO_SSL3
-#define MBEDTLS_SSL_PROTO_SSL3
-#endif
-
-/**
- * \def MBEDTLS_SSL_PROTO_TLS1
- *
- * Enable support for TLS 1.0.
- *
- * Requires: MBEDTLS_MD5_C
- *           MBEDTLS_SHA1_C
- *
- * Comment this macro to disable support for TLS 1.0
- */
-#ifdef CONFIG_MBEDTLS_SSL_PROTO_TLS1
-#define MBEDTLS_SSL_PROTO_TLS1
-#endif
-
-/**
- * \def MBEDTLS_SSL_PROTO_TLS1_1
- *
- * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled).
- *
- * Requires: MBEDTLS_MD5_C
- *           MBEDTLS_SHA1_C
- *
- * Comment this macro to disable support for TLS 1.1 / DTLS 1.0
- */
-#ifdef CONFIG_MBEDTLS_SSL_PROTO_TLS1_1
-#define MBEDTLS_SSL_PROTO_TLS1_1
-#endif
-
-/**
- * \def MBEDTLS_SSL_PROTO_TLS1_2
- *
- * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled).
- *
- * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C
- *           (Depends on ciphersuites)
- *
- * Comment this macro to disable support for TLS 1.2 / DTLS 1.2
- */
-#ifdef CONFIG_MBEDTLS_SSL_PROTO_TLS1_2
-#define MBEDTLS_SSL_PROTO_TLS1_2
-#endif
-
-/**
- * \def MBEDTLS_SSL_PROTO_DTLS
- *
- * Enable support for DTLS (all available versions).
- *
- * Enable this and MBEDTLS_SSL_PROTO_TLS1_1 to enable DTLS 1.0,
- * and/or this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2.
- *
- * Requires: MBEDTLS_SSL_PROTO_TLS1_1
- *        or MBEDTLS_SSL_PROTO_TLS1_2
- *
- * Comment this macro to disable support for DTLS
- */
-#ifdef CONFIG_MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_PROTO_DTLS
-#endif
-
-/**
- * \def MBEDTLS_SSL_ALPN
- *
- * Enable support for RFC 7301 Application Layer Protocol Negotiation.
- *
- * Comment this macro to disable support for ALPN.
- */
-#ifdef CONFIG_MBEDTLS_SSL_ALPN
-#define MBEDTLS_SSL_ALPN
-#endif
-
-/**
- * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY
- *
- * Enable support for the anti-replay mechanism in DTLS.
- *
- * Requires: MBEDTLS_SSL_TLS_C
- *           MBEDTLS_SSL_PROTO_DTLS
- *
- * \warning Disabling this is often a security risk!
- * See mbedtls_ssl_conf_dtls_anti_replay() for details.
- *
- * Comment this to disable anti-replay in DTLS.
- */
-#ifdef CONFIG_MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
-#endif
-
-/**
- * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY
- *
- * Enable support for HelloVerifyRequest on DTLS servers.
- *
- * This feature is highly recommended to prevent DTLS servers being used as
- * amplifiers in DoS attacks against other hosts. It should always be enabled
- * unless you know for sure amplification cannot be a problem in the
- * environment in which your server operates.
- *
- * \warning Disabling this can ba a security risk! (see above)
- *
- * Requires: MBEDTLS_SSL_PROTO_DTLS
- *
- * Comment this to disable support for HelloVerifyRequest.
- */
-#ifdef CONFIG_MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
-#endif
-
-/**
- * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
- *
- * Enable server-side support for clients that reconnect from the same port.
- *
- * Some clients unexpectedly close the connection and try to reconnect using the
- * same source port. This needs special support from the server to handle the
- * new connection securely, as described in section 4.2.8 of RFC 6347. This
- * flag enables that support.
- *
- * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY
- *
- * Comment this to disable support for clients reusing the source port.
- */
-#ifdef CONFIG_MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE
-#endif
-
-/**
- * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT
- *
- * Enable support for a limit of records with bad MAC.
- *
- * See mbedtls_ssl_conf_dtls_badmac_limit().
- *
- * Requires: MBEDTLS_SSL_PROTO_DTLS
- */
-#ifdef CONFIG_MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT
-#endif
-
-/**
- * \def MBEDTLS_SSL_SESSION_TICKETS
- *
- * Enable support for RFC 5077 session tickets in SSL.
- * Client-side, provides full support for session tickets (maintainance of a
- * session store remains the responsibility of the application, though).
- * Server-side, you also need to provide callbacks for writing and parsing
- * tickets, including authenticated encryption and key management. Example
- * callbacks are provided by MBEDTLS_SSL_TICKET_C.
- *
- * Comment this macro to disable support for SSL session tickets
- */
-#ifdef CONFIG_MBEDTLS_SSL_SESSION_TICKETS
-#define MBEDTLS_SSL_SESSION_TICKETS
-#endif
-
-/**
- * \def MBEDTLS_SSL_EXPORT_KEYS
- *
- * Enable support for exporting key block and master secret.
- * This is required for certain users of TLS, e.g. EAP-TLS.
- *
- * Comment this macro to disable support for key export
- */
-#define MBEDTLS_SSL_EXPORT_KEYS
-
-/**
- * \def MBEDTLS_SSL_SERVER_NAME_INDICATION
- *
- * Enable support for RFC 6066 server name indication (SNI) in SSL.
- *
- * Requires: MBEDTLS_X509_CRT_PARSE_C
- *
- * Comment this macro to disable support for server name indication in SSL
- */
-#define MBEDTLS_SSL_SERVER_NAME_INDICATION
-
-/**
- * \def MBEDTLS_SSL_TRUNCATED_HMAC
- *
- * Enable support for RFC 6066 truncated HMAC in SSL.
- *
- * Comment this macro to disable support for truncated HMAC in SSL
- */
-#define MBEDTLS_SSL_TRUNCATED_HMAC
-
-/**
- * \def MBEDTLS_THREADING_ALT
- *
- * Provide your own alternate threading implementation.
- *
- * Requires: MBEDTLS_THREADING_C
- *
- * Uncomment this to allow your own alternate threading implementation.
- */
-//#define MBEDTLS_THREADING_ALT
-
-/**
- * \def MBEDTLS_THREADING_PTHREAD
- *
- * Enable the pthread wrapper layer for the threading layer.
- *
- * Requires: MBEDTLS_THREADING_C
- *
- * Uncomment this to enable pthread mutexes.
- */
-//#define MBEDTLS_THREADING_PTHREAD
-
-/**
- * \def MBEDTLS_VERSION_FEATURES
- *
- * Allow run-time checking of compile-time enabled features. Thus allowing users
- * to check at run-time if the library is for instance compiled with threading
- * support via mbedtls_version_check_feature().
- *
- * Requires: MBEDTLS_VERSION_C
- *
- * Comment this to disable run-time checking and save ROM space
- */
-#define MBEDTLS_VERSION_FEATURES
-
-/**
- * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
- *
- * If set, the X509 parser will not break-off when parsing an X509 certificate
- * and encountering an extension in a v1 or v2 certificate.
- *
- * Uncomment to prevent an error.
- */
-//#define MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3
-
-/**
- * \def MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
- *
- * If set, the X509 parser will not break-off when parsing an X509 certificate
- * and encountering an unknown critical extension.
- *
- * \warning Depending on your PKI use, enabling this can be a security risk!
- *
- * Uncomment to prevent an error.
- */
-//#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
-
-/**
- * \def MBEDTLS_X509_CHECK_KEY_USAGE
- *
- * Enable verification of the keyUsage extension (CA and leaf certificates).
- *
- * Disabling this avoids problems with mis-issued and/or misused
- * (intermediate) CA and leaf certificates.
- *
- * \warning Depending on your PKI use, disabling this can be a security risk!
- *
- * Comment to skip keyUsage checking for both CA and leaf certificates.
- */
-#define MBEDTLS_X509_CHECK_KEY_USAGE
-
-/**
- * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
- *
- * Enable verification of the extendedKeyUsage extension (leaf certificates).
- *
- * Disabling this avoids problems with mis-issued and/or misused certificates.
- *
- * \warning Depending on your PKI use, disabling this can be a security risk!
- *
- * Comment to skip extendedKeyUsage checking for certificates.
- */
-#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
-
-/**
- * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT
- *
- * Enable parsing and verification of X.509 certificates, CRLs and CSRS
- * signed with RSASSA-PSS (aka PKCS#1 v2.1).
- *
- * Comment this macro to disallow using RSASSA-PSS in certificates.
- */
-#define MBEDTLS_X509_RSASSA_PSS_SUPPORT
-
-/**
- * \def MBEDTLS_ZLIB_SUPPORT
- *
- * If set, the SSL/TLS module uses ZLIB to support compression and
- * decompression of packet data.
- *
- * \warning TLS-level compression MAY REDUCE SECURITY! See for example the
- * CRIME attack. Before enabling this option, you should examine with care if
- * CRIME or similar exploits may be a applicable to your use case.
- *
- * \note Currently compression can't be used with DTLS.
- *
- * Used in: library/ssl_tls.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * This feature requires zlib library and headers to be present.
- *
- * Uncomment to enable use of ZLIB
- */
-//#define MBEDTLS_ZLIB_SUPPORT
-/* \} name SECTION: mbed TLS feature support */
-
-/**
- * \name SECTION: mbed TLS modules
- *
- * This section enables or disables entire modules in mbed TLS
- * \{
- */
-
-/**
- * \def MBEDTLS_AESNI_C
- *
- * Enable AES-NI support on x86-64.
- *
- * Module:  library/aesni.c
- * Caller:  library/aes.c
- *
- * Requires: MBEDTLS_HAVE_ASM
- *
- * This modules adds support for the AES-NI instructions on x86-64
- */
-#define MBEDTLS_AESNI_C
-
-/**
- * \def MBEDTLS_AES_C
- *
- * Enable the AES block cipher.
- *
- * Module:  library/aes.c
- * Caller:  library/ssl_tls.c
- *          library/pem.c
- *          library/ctr_drbg.c
- *
- * This module enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384
- *      MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256
- *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256
- *      MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA
- *
- * PEM_PARSE uses AES for decrypting encrypted keys.
- */
-#ifdef CONFIG_MBEDTLS_AES_C
-#define MBEDTLS_AES_C
-#endif
-
-/**
- * \def MBEDTLS_ARC4_C
- *
- * Enable the ARCFOUR stream cipher.
- *
- * Module:  library/arc4.c
- * Caller:  library/ssl_tls.c
- *
- * This module enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_RSA_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_RSA_WITH_RC4_128_MD5
- *      MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA
- *      MBEDTLS_TLS_PSK_WITH_RC4_128_SHA
- */
-#if defined(CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT) || defined(CONFIG_MBEDTLS_RC4_ENABLED)
-#define MBEDTLS_ARC4_C
-#endif
-
-/**
- * \def MBEDTLS_ASN1_PARSE_C
- *
- * Enable the generic ASN1 parser.
- *
- * Module:  library/asn1.c
- * Caller:  library/x509.c
- *          library/dhm.c
- *          library/pkcs12.c
- *          library/pkcs5.c
- *          library/pkparse.c
- */
-#define MBEDTLS_ASN1_PARSE_C
-
-/**
- * \def MBEDTLS_ASN1_WRITE_C
- *
- * Enable the generic ASN1 writer.
- *
- * Module:  library/asn1write.c
- * Caller:  library/ecdsa.c
- *          library/pkwrite.c
- *          library/x509_create.c
- *          library/x509write_crt.c
- *          library/mbedtls_x509write_csr.c
- */
-#define MBEDTLS_ASN1_WRITE_C
-
-/**
- * \def MBEDTLS_BASE64_C
- *
- * Enable the Base64 module.
- *
- * Module:  library/base64.c
- * Caller:  library/pem.c
- *
- * This module is required for PEM support (required by X.509).
- */
-#define MBEDTLS_BASE64_C
-
-/**
- * \def MBEDTLS_BIGNUM_C
- *
- * Enable the multi-precision integer library.
- *
- * Module:  library/bignum.c
- * Caller:  library/dhm.c
- *          library/ecp.c
- *          library/ecdsa.c
- *          library/rsa.c
- *          library/ssl_tls.c
- *
- * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support.
- */
-#define MBEDTLS_BIGNUM_C
-
-/**
- * \def MBEDTLS_BLOWFISH_C
- *
- * Enable the Blowfish block cipher.
- *
- * Module:  library/blowfish.c
- */
-#ifdef CONFIG_MBEDTLS_BLOWFISH_C
-#define MBEDTLS_BLOWFISH_C
-#endif
-
-/**
- * \def MBEDTLS_CAMELLIA_C
- *
- * Enable the Camellia block cipher.
- *
- * Module:  library/camellia.c
- * Caller:  library/ssl_tls.c
- *
- * This module enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256
- *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256
- */
-#ifdef CONFIG_MBEDTLS_CAMELLIA_C
-#define MBEDTLS_CAMELLIA_C
-#endif
-
-/**
- * \def MBEDTLS_CCM_C
- *
- * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher.
- *
- * Module:  library/ccm.c
- *
- * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
- *
- * This module enables the AES-CCM ciphersuites, if other requisites are
- * enabled as well.
- */
-#ifdef CONFIG_MBEDTLS_CCM_C
-#define MBEDTLS_CCM_C
-#endif
-
-/**
- * \def MBEDTLS_CERTS_C
- *
- * Enable the test certificates.
- *
- * Module:  library/certs.c
- * Caller:
- *
- * This module is used for testing (ssl_client/server).
- */
-#define MBEDTLS_CERTS_C
-
-/**
- * \def MBEDTLS_CIPHER_C
- *
- * Enable the generic cipher layer.
- *
- * Module:  library/cipher.c
- * Caller:  library/ssl_tls.c
- *
- * Uncomment to enable generic cipher wrappers.
- */
-#define MBEDTLS_CIPHER_C
-
-/**
- * \def MBEDTLS_CTR_DRBG_C
- *
- * Enable the CTR_DRBG AES-256-based random generator.
- *
- * Module:  library/ctr_drbg.c
- * Caller:
- *
- * Requires: MBEDTLS_AES_C
- *
- * This module provides the CTR_DRBG AES-256 random number generator.
- */
-#define MBEDTLS_CTR_DRBG_C
-
-/**
- * \def MBEDTLS_DEBUG_C
- *
- * Enable the debug functions.
- *
- * Module:  library/debug.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *
- * This module provides debugging functions.
- */
-#if CONFIG_MBEDTLS_DEBUG
-#define MBEDTLS_DEBUG_C
-#endif
-
-/**
- * \def MBEDTLS_DES_C
- *
- * Enable the DES block cipher.
- *
- * Module:  library/des.c
- * Caller:  library/pem.c
- *          library/ssl_tls.c
- *
- * This module enables the following ciphersuites (if other requisites are
- * enabled as well):
- *      MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA
- *      MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA
- *
- * PEM_PARSE uses DES/3DES for decrypting encrypted keys.
- */
-#ifdef CONFIG_MBEDTLS_DES_C
-#define MBEDTLS_DES_C
-#endif
-
-/**
- * \def MBEDTLS_DHM_C
- *
- * Enable the Diffie-Hellman-Merkle module.
- *
- * Module:  library/dhm.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * This module is used by the following key exchanges:
- *      DHE-RSA, DHE-PSK
- */
-#define MBEDTLS_DHM_C
-
-/**
- * \def MBEDTLS_ECDH_C
- *
- * Enable the elliptic curve Diffie-Hellman library.
- *
- * Module:  library/ecdh.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * This module is used by the following key exchanges:
- *      ECDHE-ECDSA, ECDHE-RSA, DHE-PSK
- *
- * Requires: MBEDTLS_ECP_C
- */
-#ifdef CONFIG_MBEDTLS_ECDH_C
-#define MBEDTLS_ECDH_C
-#endif
-
-/**
- * \def MBEDTLS_ECDSA_C
- *
- * Enable the elliptic curve DSA library.
- *
- * Module:  library/ecdsa.c
- * Caller:
- *
- * This module is used by the following key exchanges:
- *      ECDHE-ECDSA
- *
- * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C
- */
-#ifdef CONFIG_MBEDTLS_ECDSA_C
-#define MBEDTLS_ECDSA_C
-#endif
-
-/**
- * \def MBEDTLS_ECJPAKE_C
- *
- * Enable the elliptic curve J-PAKE library.
- *
- * \warning This is currently experimental. EC J-PAKE support is based on the
- * Thread v1.0.0 specification; incompatible changes to the specification
- * might still happen. For this reason, this is disabled by default.
- *
- * Module:  library/ecjpake.c
- * Caller:
- *
- * This module is used by the following key exchanges:
- *      ECJPAKE
- *
- * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C
- */
-//#define MBEDTLS_ECJPAKE_C
-
-/**
- * \def MBEDTLS_ECP_C
- *
- * Enable the elliptic curve over GF(p) library.
- *
- * Module:  library/ecp.c
- * Caller:  library/ecdh.c
- *          library/ecdsa.c
- *          library/ecjpake.c
- *
- * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED
- */
-#ifdef CONFIG_MBEDTLS_ECP_C
-#define MBEDTLS_ECP_C
-#endif
-
-/**
- * \def MBEDTLS_ENTROPY_C
- *
- * Enable the platform-specific entropy code.
- *
- * Module:  library/entropy.c
- * Caller:
- *
- * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C
- *
- * This module provides a generic entropy pool
- */
-#define MBEDTLS_ENTROPY_C
-
-/**
- * \def MBEDTLS_ERROR_C
- *
- * Enable error code to error string conversion.
- *
- * Module:  library/error.c
- * Caller:
- *
- * This module enables mbedtls_strerror().
- */
-#define MBEDTLS_ERROR_C
-
-/**
- * \def MBEDTLS_GCM_C
- *
- * Enable the Galois/Counter Mode (GCM) for AES.
- *
- * Module:  library/gcm.c
- *
- * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C
- *
- * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other
- * requisites are enabled as well.
- */
-#ifdef CONFIG_MBEDTLS_GCM_C
-#define MBEDTLS_GCM_C
-#endif
-
-/**
- * \def MBEDTLS_HAVEGE_C
- *
- * Enable the HAVEGE random generator.
- *
- * Warning: the HAVEGE random generator is not suitable for virtualized
- *          environments
- *
- * Warning: the HAVEGE random generator is dependent on timing and specific
- *          processor traits. It is therefore not advised to use HAVEGE as
- *          your applications primary random generator or primary entropy pool
- *          input. As a secondary input to your entropy pool, it IS able add
- *          the (limited) extra entropy it provides.
- *
- * Module:  library/havege.c
- * Caller:
- *
- * Requires: MBEDTLS_TIMING_C
- *
- * Uncomment to enable the HAVEGE random generator.
- */
-//#define MBEDTLS_HAVEGE_C
-
-/**
- * \def MBEDTLS_HMAC_DRBG_C
- *
- * Enable the HMAC_DRBG random generator.
- *
- * Module:  library/hmac_drbg.c
- * Caller:
- *
- * Requires: MBEDTLS_MD_C
- *
- * Uncomment to enable the HMAC_DRBG random number geerator.
- */
-#define MBEDTLS_HMAC_DRBG_C
-
-/**
- * \def MBEDTLS_MD_C
- *
- * Enable the generic message digest layer.
- *
- * Module:  library/mbedtls_md.c
- * Caller:
- *
- * Uncomment to enable generic message digest wrappers.
- */
-#define MBEDTLS_MD_C
-
-/**
- * \def MBEDTLS_MD2_C
- *
- * Enable the MD2 hash algorithm.
- *
- * Module:  library/mbedtls_md2.c
- * Caller:
- *
- * Uncomment to enable support for (rare) MD2-signed X.509 certs.
- */
-//#define MBEDTLS_MD2_C
-
-/**
- * \def MBEDTLS_MD4_C
- *
- * Enable the MD4 hash algorithm.
- *
- * Module:  library/mbedtls_md4.c
- * Caller:
- *
- * Uncomment to enable support for (rare) MD4-signed X.509 certs.
- */
-//#define MBEDTLS_MD4_C
-
-/**
- * \def MBEDTLS_MD5_C
- *
- * Enable the MD5 hash algorithm.
- *
- * Module:  library/mbedtls_md5.c
- * Caller:  library/mbedtls_md.c
- *          library/pem.c
- *          library/ssl_tls.c
- *
- * This module is required for SSL/TLS and X.509.
- * PEM_PARSE uses MD5 for decrypting encrypted keys.
- */
-#define MBEDTLS_MD5_C
-
-/**
- * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C
- *
- * Enable the buffer allocator implementation that makes use of a (stack)
- * based buffer to 'allocate' dynamic memory. (replaces calloc() and free()
- * calls)
- *
- * Module:  library/memory_buffer_alloc.c
- *
- * Requires: MBEDTLS_PLATFORM_C
- *           MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS)
- *
- * Enable this module to enable the buffer memory allocator.
- */
-//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
-
-/**
- * \def MBEDTLS_NET_C
- *
- * Enable the TCP/IP networking routines.
- *
- * Module:  library/net.c
- *
- * This module provides TCP/IP networking routines.
- */
-//#define MBEDTLS_NET_C
-
-/**
- * \def MBEDTLS_OID_C
- *
- * Enable the OID database.
- *
- * Module:  library/oid.c
- * Caller:  library/asn1write.c
- *          library/pkcs5.c
- *          library/pkparse.c
- *          library/pkwrite.c
- *          library/rsa.c
- *          library/x509.c
- *          library/x509_create.c
- *          library/mbedtls_x509_crl.c
- *          library/mbedtls_x509_crt.c
- *          library/mbedtls_x509_csr.c
- *          library/x509write_crt.c
- *          library/mbedtls_x509write_csr.c
- *
- * This modules translates between OIDs and internal values.
- */
-#define MBEDTLS_OID_C
-
-/**
- * \def MBEDTLS_PADLOCK_C
- *
- * Enable VIA Padlock support on x86.
- *
- * Module:  library/padlock.c
- * Caller:  library/aes.c
- *
- * Requires: MBEDTLS_HAVE_ASM
- *
- * This modules adds support for the VIA PadLock on x86.
- */
-#define MBEDTLS_PADLOCK_C
-
-/**
- * \def MBEDTLS_PEM_PARSE_C
- *
- * Enable PEM decoding / parsing.
- *
- * Module:  library/pem.c
- * Caller:  library/dhm.c
- *          library/pkparse.c
- *          library/mbedtls_x509_crl.c
- *          library/mbedtls_x509_crt.c
- *          library/mbedtls_x509_csr.c
- *
- * Requires: MBEDTLS_BASE64_C
- *
- * This modules adds support for decoding / parsing PEM files.
- */
-#ifdef CONFIG_MBEDTLS_PEM_PARSE_C
-#define MBEDTLS_PEM_PARSE_C
-#endif
-
-/**
- * \def MBEDTLS_PEM_WRITE_C
- *
- * Enable PEM encoding / writing.
- *
- * Module:  library/pem.c
- * Caller:  library/pkwrite.c
- *          library/x509write_crt.c
- *          library/mbedtls_x509write_csr.c
- *
- * Requires: MBEDTLS_BASE64_C
- *
- * This modules adds support for encoding / writing PEM files.
- */
-#ifdef CONFIG_MBEDTLS_PEM_WRITE_C
-#define MBEDTLS_PEM_WRITE_C
-#endif
-
-/**
- * \def MBEDTLS_PK_C
- *
- * Enable the generic public (asymetric) key layer.
- *
- * Module:  library/pk.c
- * Caller:  library/ssl_tls.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C
- *
- * Uncomment to enable generic public key wrappers.
- */
-#define MBEDTLS_PK_C
-
-/**
- * \def MBEDTLS_PK_PARSE_C
- *
- * Enable the generic public (asymetric) key parser.
- *
- * Module:  library/pkparse.c
- * Caller:  library/mbedtls_x509_crt.c
- *          library/mbedtls_x509_csr.c
- *
- * Requires: MBEDTLS_PK_C
- *
- * Uncomment to enable generic public key parse functions.
- */
-#define MBEDTLS_PK_PARSE_C
-
-/**
- * \def MBEDTLS_PK_WRITE_C
- *
- * Enable the generic public (asymetric) key writer.
- *
- * Module:  library/pkwrite.c
- * Caller:  library/x509write.c
- *
- * Requires: MBEDTLS_PK_C
- *
- * Uncomment to enable generic public key write functions.
- */
-#define MBEDTLS_PK_WRITE_C
-
-/**
- * \def MBEDTLS_PKCS5_C
- *
- * Enable PKCS#5 functions.
- *
- * Module:  library/pkcs5.c
- *
- * Requires: MBEDTLS_MD_C
- *
- * This module adds support for the PKCS#5 functions.
- */
-#define MBEDTLS_PKCS5_C
-
-/**
- * \def MBEDTLS_PKCS11_C
- *
- * Enable wrapper for PKCS#11 smartcard support.
- *
- * Module:  library/pkcs11.c
- * Caller:  library/pk.c
- *
- * Requires: MBEDTLS_PK_C
- *
- * This module enables SSL/TLS PKCS #11 smartcard support.
- * Requires the presence of the PKCS#11 helper library (libpkcs11-helper)
- */
-//#define MBEDTLS_PKCS11_C
-
-/**
- * \def MBEDTLS_PKCS12_C
- *
- * Enable PKCS#12 PBE functions.
- * Adds algorithms for parsing PKCS#8 encrypted private keys
- *
- * Module:  library/pkcs12.c
- * Caller:  library/pkparse.c
- *
- * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C
- * Can use:  MBEDTLS_ARC4_C
- *
- * This module enables PKCS#12 functions.
- */
-#define MBEDTLS_PKCS12_C
-
-/**
- * \def MBEDTLS_PLATFORM_C
- *
- * Enable the platform abstraction layer that allows you to re-assign
- * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit().
- *
- * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT
- * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned
- * above to be specified at runtime or compile time respectively.
- *
- * \note This abstraction layer must be enabled on Windows (including MSYS2)
- * as other module rely on it for a fixed snprintf implementation.
- *
- * Module:  library/platform.c
- * Caller:  Most other .c files
- *
- * This module enables abstraction of common (libc) functions.
- */
-#define MBEDTLS_PLATFORM_C
-
-/**
- * \def MBEDTLS_RIPEMD160_C
- *
- * Enable the RIPEMD-160 hash algorithm.
- *
- * Module:  library/mbedtls_ripemd160.c
- * Caller:  library/mbedtls_md.c
- *
- */
-#ifdef CONFIG_MBEDTLS_RIPEMD160_C
-#define MBEDTLS_RIPEMD160_C
-#endif
-
-/**
- * \def MBEDTLS_RSA_C
- *
- * Enable the RSA public-key cryptosystem.
- *
- * Module:  library/rsa.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *          library/x509.c
- *
- * This module is used by the following key exchanges:
- *      RSA, DHE-RSA, ECDHE-RSA, RSA-PSK
- *
- * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C
- */
-#define MBEDTLS_RSA_C
-
-/**
- * \def MBEDTLS_SHA1_C
- *
- * Enable the SHA1 cryptographic hash algorithm.
- *
- * Module:  library/mbedtls_sha1.c
- * Caller:  library/mbedtls_md.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *          library/x509write_crt.c
- *
- * This module is required for SSL/TLS and SHA1-signed certificates.
- */
-#define MBEDTLS_SHA1_C
-
-/**
- * \def MBEDTLS_SHA256_C
- *
- * Enable the SHA-224 and SHA-256 cryptographic hash algorithms.
- *
- * Module:  library/mbedtls_sha256.c
- * Caller:  library/entropy.c
- *          library/mbedtls_md.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *
- * This module adds support for SHA-224 and SHA-256.
- * This module is required for the SSL/TLS 1.2 PRF function.
- */
-#define MBEDTLS_SHA256_C
-
-/**
- * \def MBEDTLS_SHA512_C
- *
- * Enable the SHA-384 and SHA-512 cryptographic hash algorithms.
- *
- * Module:  library/mbedtls_sha512.c
- * Caller:  library/entropy.c
- *          library/mbedtls_md.c
- *          library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * This module adds support for SHA-384 and SHA-512.
- */
-#define MBEDTLS_SHA512_C
-
-/**
- * \def MBEDTLS_SSL_CACHE_C
- *
- * Enable simple SSL cache implementation.
- *
- * Module:  library/ssl_cache.c
- * Caller:
- *
- * Requires: MBEDTLS_SSL_CACHE_C
- */
-#define MBEDTLS_SSL_CACHE_C
-
-/**
- * \def MBEDTLS_SSL_COOKIE_C
- *
- * Enable basic implementation of DTLS cookies for hello verification.
- *
- * Module:  library/ssl_cookie.c
- * Caller:
- */
-#define MBEDTLS_SSL_COOKIE_C
-
-/**
- * \def MBEDTLS_SSL_TICKET_C
- *
- * Enable an implementation of TLS server-side callbacks for session tickets.
- *
- * Module:  library/ssl_ticket.c
- * Caller:
- *
- * Requires: MBEDTLS_CIPHER_C
- */
-#define MBEDTLS_SSL_TICKET_C
-
-/**
- * \def MBEDTLS_SSL_CLI_C
- *
- * Enable the SSL/TLS client code.
- *
- * Module:  library/ssl_cli.c
- * Caller:
- *
- * Requires: MBEDTLS_SSL_TLS_C
- *
- * This module is required for SSL/TLS client support.
- */
-#ifdef CONFIG_MBEDTLS_TLS_CLIENT
-#define MBEDTLS_SSL_CLI_C
-#endif
-
-/**
- * \def MBEDTLS_SSL_SRV_C
- *
- * Enable the SSL/TLS server code.
- *
- * Module:  library/ssl_srv.c
- * Caller:
- *
- * Requires: MBEDTLS_SSL_TLS_C
- *
- * This module is required for SSL/TLS server support.
- */
-#ifdef CONFIG_MBEDTLS_TLS_SERVER
-#define MBEDTLS_SSL_SRV_C
-#endif
-
-/**
- * \def MBEDTLS_SSL_TLS_C
- *
- * Enable the generic SSL/TLS code.
- *
- * Module:  library/ssl_tls.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *
- * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C
- *           and at least one of the MBEDTLS_SSL_PROTO_XXX defines
- *
- * This module is required for SSL/TLS.
- */
-#ifdef CONFIG_MBEDTLS_TLS_ENABLED
-#define MBEDTLS_SSL_TLS_C
-#endif
-
-/**
- * \def MBEDTLS_THREADING_C
- *
- * Enable the threading abstraction layer.
- * By default mbed TLS assumes it is used in a non-threaded environment or that
- * contexts are not shared between threads. If you do intend to use contexts
- * between threads, you will need to enable this layer to prevent race
- * conditions.
- *
- * Module:  library/threading.c
- *
- * This allows different threading implementations (self-implemented or
- * provided).
- *
- * You will have to enable either MBEDTLS_THREADING_ALT or
- * MBEDTLS_THREADING_PTHREAD.
- *
- * Enable this layer to allow use of mutexes within mbed TLS
- */
-//#define MBEDTLS_THREADING_C
-
-/**
- * \def MBEDTLS_TIMING_C
- *
- * Enable the portable timing interface.
- *
- * Module:  library/timing.c
- * Caller:  library/havege.c
- *
- * This module is used by the HAVEGE random number generator.
- */
-//#define MBEDTLS_TIMING_C
-
-/**
- * \def MBEDTLS_VERSION_C
- *
- * Enable run-time version information.
- *
- * Module:  library/version.c
- *
- * This module provides run-time version information.
- */
-#define MBEDTLS_VERSION_C
-
-/**
- * \def MBEDTLS_X509_USE_C
- *
- * Enable X.509 core for using certificates.
- *
- * Module:  library/x509.c
- * Caller:  library/mbedtls_x509_crl.c
- *          library/mbedtls_x509_crt.c
- *          library/mbedtls_x509_csr.c
- *
- * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C,
- *           MBEDTLS_PK_PARSE_C
- *
- * This module is required for the X.509 parsing modules.
- */
-#define MBEDTLS_X509_USE_C
-
-/**
- * \def MBEDTLS_X509_CRT_PARSE_C
- *
- * Enable X.509 certificate parsing.
- *
- * Module:  library/mbedtls_x509_crt.c
- * Caller:  library/ssl_cli.c
- *          library/ssl_srv.c
- *          library/ssl_tls.c
- *
- * Requires: MBEDTLS_X509_USE_C
- *
- * This module is required for X.509 certificate parsing.
- */
-#define MBEDTLS_X509_CRT_PARSE_C
-
-/**
- * \def MBEDTLS_X509_CRL_PARSE_C
- *
- * Enable X.509 CRL parsing.
- *
- * Module:  library/mbedtls_x509_crl.c
- * Caller:  library/mbedtls_x509_crt.c
- *
- * Requires: MBEDTLS_X509_USE_C
- *
- * This module is required for X.509 CRL parsing.
- */
-#ifdef CONFIG_MBEDTLS_X509_CRL_PARSE_C
-#define MBEDTLS_X509_CRL_PARSE_C
-#endif
-
-/**
- * \def MBEDTLS_X509_CSR_PARSE_C
- *
- * Enable X.509 Certificate Signing Request (CSR) parsing.
- *
- * Module:  library/mbedtls_x509_csr.c
- * Caller:  library/x509_crt_write.c
- *
- * Requires: MBEDTLS_X509_USE_C
- *
- * This module is used for reading X.509 certificate request.
- */
-#ifdef CONFIG_MBEDTLS_X509_CSR_PARSE_C
-#define MBEDTLS_X509_CSR_PARSE_C
-#endif
-
-/**
- * \def MBEDTLS_X509_CREATE_C
- *
- * Enable X.509 core for creating certificates.
- *
- * Module:  library/x509_create.c
- *
- * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C
- *
- * This module is the basis for creating X.509 certificates and CSRs.
- */
-#define MBEDTLS_X509_CREATE_C
-
-/**
- * \def MBEDTLS_X509_CRT_WRITE_C
- *
- * Enable creating X.509 certificates.
- *
- * Module:  library/x509_crt_write.c
- *
- * Requires: MBEDTLS_X509_CREATE_C
- *
- * This module is required for X.509 certificate creation.
- */
-#define MBEDTLS_X509_CRT_WRITE_C
-
-/**
- * \def MBEDTLS_X509_CSR_WRITE_C
- *
- * Enable creating X.509 Certificate Signing Requests (CSR).
- *
- * Module:  library/x509_csr_write.c
- *
- * Requires: MBEDTLS_X509_CREATE_C
- *
- * This module is required for X.509 certificate request writing.
- */
-#define MBEDTLS_X509_CSR_WRITE_C
-
-/**
- * \def MBEDTLS_XTEA_C
- *
- * Enable the XTEA block cipher.
- *
- * Module:  library/xtea.c
- * Caller:
- */
-#ifdef CONFIG_MBEDTLS_XTEA_C
-#define MBEDTLS_XTEA_C
-#endif
-
-/* \} name SECTION: mbed TLS modules */
-
-/**
- * \name SECTION: Module configuration options
- *
- * This section allows for the setting of module specific sizes and
- * configuration options. The default values are already present in the
- * relevant header files and should suffice for the regular use cases.
- *
- * Our advice is to enable options and change their values here
- * only if you have a good reason and know the consequences.
- *
- * Please check the respective header file for documentation on these
- * parameters (to prevent duplicate documentation).
- * \{
- */
-
-/* MPI / BIGNUM options */
-//#define MBEDTLS_MPI_WINDOW_SIZE            6 /**< Maximum windows size used. */
-//#define MBEDTLS_MPI_MAX_SIZE            1024 /**< Maximum number of bytes for usable MPIs. */
-
-/* CTR_DRBG options */
-//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN               48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */
-//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL        10000 /**< Interval before reseed is performed by default */
-//#define MBEDTLS_CTR_DRBG_MAX_INPUT                256 /**< Maximum number of additional input bytes */
-//#define MBEDTLS_CTR_DRBG_MAX_REQUEST             1024 /**< Maximum number of requested bytes per call */
-//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT           384 /**< Maximum size of (re)seed buffer */
-
-/* HMAC_DRBG options */
-//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL   10000 /**< Interval before reseed is performed by default */
-//#define MBEDTLS_HMAC_DRBG_MAX_INPUT           256 /**< Maximum number of additional input bytes */
-//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST        1024 /**< Maximum number of requested bytes per call */
-//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT      384 /**< Maximum size of (re)seed buffer */
-
-/* ECP options */
-//#define MBEDTLS_ECP_MAX_BITS             521 /**< Maximum bit size of groups */
-//#define MBEDTLS_ECP_WINDOW_SIZE            6 /**< Maximum window size used */
-//#define MBEDTLS_ECP_FIXED_POINT_OPTIM      1 /**< Enable fixed-point speed-up */
-
-/* Entropy options */
-//#define MBEDTLS_ENTROPY_MAX_SOURCES                20 /**< Maximum number of sources supported */
-//#define MBEDTLS_ENTROPY_MAX_GATHER                128 /**< Maximum amount requested from entropy sources */
-
-/* Memory buffer allocator options */
-//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE      4 /**< Align on multiples of this value */
-
-/* Platform options */
-//#define MBEDTLS_PLATFORM_STD_MEM_HDR   <stdlib.h> /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */
-//#define MBEDTLS_PLATFORM_STD_CALLOC        calloc /**< Default allocator to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_FREE            free /**< Default free to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_EXIT            exit /**< Default exit to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_FPRINTF      fprintf /**< Default fprintf to use, can be undefined */
-//#define MBEDTLS_PLATFORM_STD_PRINTF        printf /**< Default printf to use, can be undefined */
-/* Note: your snprintf must correclty zero-terminate the buffer! */
-//#define MBEDTLS_PLATFORM_STD_SNPRINTF    snprintf /**< Default snprintf to use, can be undefined */
-
-/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */
-/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */
-//#define MBEDTLS_PLATFORM_CALLOC_MACRO        calloc /**< Default allocator macro to use, can be undefined */
-//#define MBEDTLS_PLATFORM_FREE_MACRO            free /**< Default free macro to use, can be undefined */
-//#define MBEDTLS_PLATFORM_EXIT_MACRO            exit /**< Default exit macro to use, can be undefined */
-//#define MBEDTLS_PLATFORM_FPRINTF_MACRO      fprintf /**< Default fprintf macro to use, can be undefined */
-//#define MBEDTLS_PLATFORM_PRINTF_MACRO        printf /**< Default printf macro to use, can be undefined */
-/* Note: your snprintf must correclty zero-terminate the buffer! */
-//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO    snprintf /**< Default snprintf macro to use, can be undefined */
-
-/* SSL Cache options */
-//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT       86400 /**< 1 day  */
-//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES      50 /**< Maximum entries in cache */
-
-/* SSL options */
-#ifndef CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN
-
-#define MBEDTLS_SSL_MAX_CONTENT_LEN             CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */
-
-#else
-
-/** \def MBEDTLS_SSL_IN_CONTENT_LEN
- *
- * Maximum incoming fragment length in bytes.
- *
- * Uncomment to set the size of the inward TLS buffer independently of the
- * outward buffer.
- */
-#define MBEDTLS_SSL_IN_CONTENT_LEN              CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN
-
-/** \def MBEDTLS_SSL_OUT_CONTENT_LEN
- *
- * Maximum outgoing fragment length in bytes.
- *
- * Uncomment to set the size of the outward TLS buffer independently of the
- * inward buffer.
- *
- * It is possible to save RAM by setting a smaller outward buffer, while keeping
- * the default inward 16384 byte buffer to conform to the TLS specification.
- *
- * The minimum required outward buffer size is determined by the handshake
- * protocol's usage. Handshaking will fail if the outward buffer is too small.
- * The specific size requirement depends on the configured ciphers and any
- * certificate data which is sent during the handshake.
- *
- * For absolute minimum RAM usage, it's best to enable
- * MBEDTLS_SSL_MAX_FRAGMENT_LENGTH and reduce MBEDTLS_SSL_MAX_CONTENT_LEN. This
- * reduces both incoming and outgoing buffer sizes. However this is only
- * guaranteed if the other end of the connection also supports the TLS
- * max_fragment_len extension. Otherwise the connection may fail.
- */
-#define MBEDTLS_SSL_OUT_CONTENT_LEN             CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN
-
-#endif /* !CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN */
-
-//#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME     86400 /**< Lifetime of session tickets (if enabled) */
-//#define MBEDTLS_PSK_MAX_LEN               32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */
-//#define MBEDTLS_SSL_COOKIE_TIMEOUT        60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */
-
-/**
- * Complete list of ciphersuites to use, in order of preference.
- *
- * \warning No dependency checking is done on that field! This option can only
- * be used to restrict the set of available ciphersuites. It is your
- * responsibility to make sure the needed modules are active.
- *
- * Use this to save a few hundred bytes of ROM (default ordering of all
- * available ciphersuites) and a few to a few hundred bytes of RAM.
- *
- * The value below is only an example, not the default.
- */
-//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
-
-/* X509 options */
-//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA   8   /**< Maximum number of intermediate CAs in a verification chain. */
-
-/**
- * Allow SHA-1 in the default TLS configuration for TLS 1.2 handshake
- * signature and ciphersuite selection. Without this build-time option, SHA-1
- * support must be activated explicitly through mbedtls_ssl_conf_sig_hashes.
- * The use of SHA-1 in TLS <= 1.1 and in HMAC-SHA-1 is always allowed by
- * default. At the time of writing, there is no practical attack on the use
- * of SHA-1 in handshake signatures, hence this option is turned on by default
- * for compatibility with existing peers.
- */
-#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE
-
-/* \} name SECTION: Module configuration options */
-
-#if defined(TARGET_LIKE_MBED)
-#include "mbedtls/target_config.h"
-#endif
-
-/*
- * Allow user to override any previous default.
- *
- * Use two macro names for that, as:
- * - with yotta the prefix YOTTA_CFG_ is forced
- * - without yotta is looks weird to have a YOTTA prefix.
- */
-#if defined(YOTTA_CFG_MBEDTLS_USER_CONFIG_FILE)
-#include YOTTA_CFG_MBEDTLS_USER_CONFIG_FILE
-#elif defined(MBEDTLS_USER_CONFIG_FILE)
-#include MBEDTLS_USER_CONFIG_FILE
-#endif
-
-#include "mbedtls/check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/esp_debug.h b/tools/sdk/include/mbedtls/mbedtls/esp_debug.h
deleted file mode 100644
index 8e23a5ea322..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/esp_debug.h
+++ /dev/null
@@ -1,57 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_DEBUG_H_
-#define _ESP_DEBUG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "sdkconfig.h"
-#ifdef CONFIG_MBEDTLS_DEBUG
-
-/** @brief Enable mbedTLS debug logging via the esp_log mechanism.
- *
- * mbedTLS internal debugging is filtered from a specified mbedTLS
- * threshold level to esp_log level at runtime:
- *
- * - 1 - Warning
- * - 2 - Info
- * - 3 - Debug
- * - 4 - Verbose
- *
- * (Note that mbedTLS debug thresholds are not always consistently used.)
- *
- * This function will set the esp log level for "mbedtls" to the specified mbedTLS
- * threshold level that matches. However, the overall max ESP log level must be set high
- * enough in menuconfig, or some messages may be filtered at compile time.
- *
- * @param conf mbedtls_ssl_config structure
- * @param mbedTLS debug threshold, 0-4. Messages are filtered at runtime.
- */
-void mbedtls_esp_enable_debug_log(mbedtls_ssl_config *conf, int threshold);
-
-/** @brief Disable mbedTLS debug logging via the esp_log mechanism.
- *
- */
-void mbedtls_esp_disable_debug_log(mbedtls_ssl_config *conf);
-
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ESP_DEBUG_H__ */
diff --git a/tools/sdk/include/mbedtls/mbedtls/gcm.h b/tools/sdk/include/mbedtls/mbedtls/gcm.h
deleted file mode 100644
index 52d03b0ce89..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/gcm.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/**
- * \file gcm.h
- *
- * \brief This file contains GCM definitions and functions.
- *
- * The Galois/Counter Mode (GCM) for 128-bit block ciphers is defined
- * in <em>D. McGrew, J. Viega, The Galois/Counter Mode of Operation
- * (GCM), Natl. Inst. Stand. Technol.</em>
- *
- * For more information on GCM, see <em>NIST SP 800-38D: Recommendation for
- * Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC</em>.
- *
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_GCM_H
-#define MBEDTLS_GCM_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "cipher.h"
-
-#include <stdint.h>
-
-#define MBEDTLS_GCM_ENCRYPT     1
-#define MBEDTLS_GCM_DECRYPT     0
-
-#define MBEDTLS_ERR_GCM_AUTH_FAILED                       -0x0012  /**< Authenticated decryption failed. */
-
-/* MBEDTLS_ERR_GCM_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_GCM_HW_ACCEL_FAILED                   -0x0013  /**< GCM hardware accelerator failed. */
-
-#define MBEDTLS_ERR_GCM_BAD_INPUT                         -0x0014  /**< Bad input parameters to function. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_GCM_ALT)
-
-/**
- * \brief          The GCM context structure.
- */
-typedef struct mbedtls_gcm_context
-{
-    mbedtls_cipher_context_t cipher_ctx;  /*!< The cipher context used. */
-    uint64_t HL[16];                      /*!< Precalculated HTable low. */
-    uint64_t HH[16];                      /*!< Precalculated HTable high. */
-    uint64_t len;                         /*!< The total length of the encrypted data. */
-    uint64_t add_len;                     /*!< The total length of the additional data. */
-    unsigned char base_ectr[16];          /*!< The first ECTR for tag. */
-    unsigned char y[16];                  /*!< The Y working value. */
-    unsigned char buf[16];                /*!< The buf working value. */
-    int mode;                             /*!< The operation to perform:
-                                               #MBEDTLS_GCM_ENCRYPT or
-                                               #MBEDTLS_GCM_DECRYPT. */
-}
-mbedtls_gcm_context;
-
-#else  /* !MBEDTLS_GCM_ALT */
-#include "gcm_alt.h"
-#endif /* !MBEDTLS_GCM_ALT */
-
-/**
- * \brief           This function initializes the specified GCM context,
- *                  to make references valid, and prepares the context
- *                  for mbedtls_gcm_setkey() or mbedtls_gcm_free().
- *
- *                  The function does not bind the GCM context to a particular
- *                  cipher, nor set the key. For this purpose, use
- *                  mbedtls_gcm_setkey().
- *
- * \param ctx       The GCM context to initialize. This must not be \c NULL.
- */
-void mbedtls_gcm_init( mbedtls_gcm_context *ctx );
-
-/**
- * \brief           This function associates a GCM context with a
- *                  cipher algorithm and a key.
- *
- * \param ctx       The GCM context. This must be initialized.
- * \param cipher    The 128-bit block cipher to use.
- * \param key       The encryption key. This must be a readable buffer of at
- *                  least \p keybits bits.
- * \param keybits   The key size in bits. Valid options are:
- *                  <ul><li>128 bits</li>
- *                  <li>192 bits</li>
- *                  <li>256 bits</li></ul>
- *
- * \return          \c 0 on success.
- * \return          A cipher-specific error code on failure.
- */
-int mbedtls_gcm_setkey( mbedtls_gcm_context *ctx,
-                        mbedtls_cipher_id_t cipher,
-                        const unsigned char *key,
-                        unsigned int keybits );
-
-/**
- * \brief           This function performs GCM encryption or decryption of a buffer.
- *
- * \note            For encryption, the output buffer can be the same as the
- *                  input buffer. For decryption, the output buffer cannot be
- *                  the same as input buffer. If the buffers overlap, the output
- *                  buffer must trail at least 8 Bytes behind the input buffer.
- *
- * \warning         When this function performs a decryption, it outputs the
- *                  authentication tag and does not verify that the data is
- *                  authentic. You should use this function to perform encryption
- *                  only. For decryption, use mbedtls_gcm_auth_decrypt() instead.
- *
- * \param ctx       The GCM context to use for encryption or decryption. This
- *                  must be initialized.
- * \param mode      The operation to perform:
- *                  - #MBEDTLS_GCM_ENCRYPT to perform authenticated encryption.
- *                    The ciphertext is written to \p output and the
- *                    authentication tag is written to \p tag.
- *                  - #MBEDTLS_GCM_DECRYPT to perform decryption.
- *                    The plaintext is written to \p output and the
- *                    authentication tag is written to \p tag.
- *                    Note that this mode is not recommended, because it does
- *                    not verify the authenticity of the data. For this reason,
- *                    you should use mbedtls_gcm_auth_decrypt() instead of
- *                    calling this function in decryption mode.
- * \param length    The length of the input data, which is equal to the length
- *                  of the output data.
- * \param iv        The initialization vector. This must be a readable buffer of
- *                  at least \p iv_len Bytes.
- * \param iv_len    The length of the IV.
- * \param add       The buffer holding the additional data. This must be of at
- *                  least that size in Bytes.
- * \param add_len   The length of the additional data.
- * \param input     The buffer holding the input data. If \p length is greater
- *                  than zero, this must be a readable buffer of at least that
- *                  size in Bytes.
- * \param output    The buffer for holding the output data. If \p length is greater
- *                  than zero, this must be a writable buffer of at least that
- *                  size in Bytes.
- * \param tag_len   The length of the tag to generate.
- * \param tag       The buffer for holding the tag. This must be a readable
- *                  buffer of at least \p tag_len Bytes.
- *
- * \return          \c 0 if the encryption or decryption was performed
- *                  successfully. Note that in #MBEDTLS_GCM_DECRYPT mode,
- *                  this does not indicate that the data is authentic.
- * \return          #MBEDTLS_ERR_GCM_BAD_INPUT if the lengths or pointers are
- *                  not valid or a cipher-specific error code if the encryption
- *                  or decryption failed.
- */
-int mbedtls_gcm_crypt_and_tag( mbedtls_gcm_context *ctx,
-                       int mode,
-                       size_t length,
-                       const unsigned char *iv,
-                       size_t iv_len,
-                       const unsigned char *add,
-                       size_t add_len,
-                       const unsigned char *input,
-                       unsigned char *output,
-                       size_t tag_len,
-                       unsigned char *tag );
-
-/**
- * \brief           This function performs a GCM authenticated decryption of a
- *                  buffer.
- *
- * \note            For decryption, the output buffer cannot be the same as
- *                  input buffer. If the buffers overlap, the output buffer
- *                  must trail at least 8 Bytes behind the input buffer.
- *
- * \param ctx       The GCM context. This must be initialized.
- * \param length    The length of the ciphertext to decrypt, which is also
- *                  the length of the decrypted plaintext.
- * \param iv        The initialization vector. This must be a readable buffer
- *                  of at least \p iv_len Bytes.
- * \param iv_len    The length of the IV.
- * \param add       The buffer holding the additional data. This must be of at
- *                  least that size in Bytes.
- * \param add_len   The length of the additional data.
- * \param tag       The buffer holding the tag to verify. This must be a
- *                  readable buffer of at least \p tag_len Bytes.
- * \param tag_len   The length of the tag to verify.
- * \param input     The buffer holding the ciphertext. If \p length is greater
- *                  than zero, this must be a readable buffer of at least that
- *                  size.
- * \param output    The buffer for holding the decrypted plaintext. If \p length
- *                  is greater than zero, this must be a writable buffer of at
- *                  least that size.
- *
- * \return          \c 0 if successful and authenticated.
- * \return          #MBEDTLS_ERR_GCM_AUTH_FAILED if the tag does not match.
- * \return          #MBEDTLS_ERR_GCM_BAD_INPUT if the lengths or pointers are
- *                  not valid or a cipher-specific error code if the decryption
- *                  failed.
- */
-int mbedtls_gcm_auth_decrypt( mbedtls_gcm_context *ctx,
-                      size_t length,
-                      const unsigned char *iv,
-                      size_t iv_len,
-                      const unsigned char *add,
-                      size_t add_len,
-                      const unsigned char *tag,
-                      size_t tag_len,
-                      const unsigned char *input,
-                      unsigned char *output );
-
-/**
- * \brief           This function starts a GCM encryption or decryption
- *                  operation.
- *
- * \param ctx       The GCM context. This must be initialized.
- * \param mode      The operation to perform: #MBEDTLS_GCM_ENCRYPT or
- *                  #MBEDTLS_GCM_DECRYPT.
- * \param iv        The initialization vector. This must be a readable buffer of
- *                  at least \p iv_len Bytes.
- * \param iv_len    The length of the IV.
- * \param add       The buffer holding the additional data, or \c NULL
- *                  if \p add_len is \c 0.
- * \param add_len   The length of the additional data. If \c 0,
- *                  \p add may be \c NULL.
- *
- * \return          \c 0 on success.
- */
-int mbedtls_gcm_starts( mbedtls_gcm_context *ctx,
-                int mode,
-                const unsigned char *iv,
-                size_t iv_len,
-                const unsigned char *add,
-                size_t add_len );
-
-/**
- * \brief           This function feeds an input buffer into an ongoing GCM
- *                  encryption or decryption operation.
- *
- *    `             The function expects input to be a multiple of 16
- *                  Bytes. Only the last call before calling
- *                  mbedtls_gcm_finish() can be less than 16 Bytes.
- *
- * \note            For decryption, the output buffer cannot be the same as
- *                  input buffer. If the buffers overlap, the output buffer
- *                  must trail at least 8 Bytes behind the input buffer.
- *
- * \param ctx       The GCM context. This must be initialized.
- * \param length    The length of the input data. This must be a multiple of
- *                  16 except in the last call before mbedtls_gcm_finish().
- * \param input     The buffer holding the input data. If \p length is greater
- *                  than zero, this must be a readable buffer of at least that
- *                  size in Bytes.
- * \param output    The buffer for holding the output data. If \p length is
- *                  greater than zero, this must be a writable buffer of at
- *                  least that size in Bytes.
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_GCM_BAD_INPUT on failure.
- */
-int mbedtls_gcm_update( mbedtls_gcm_context *ctx,
-                size_t length,
-                const unsigned char *input,
-                unsigned char *output );
-
-/**
- * \brief           This function finishes the GCM operation and generates
- *                  the authentication tag.
- *
- *                  It wraps up the GCM stream, and generates the
- *                  tag. The tag can have a maximum length of 16 Bytes.
- *
- * \param ctx       The GCM context. This must be initialized.
- * \param tag       The buffer for holding the tag. This must be a readable
- *                  buffer of at least \p tag_len Bytes.
- * \param tag_len   The length of the tag to generate. This must be at least
- *                  four.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_GCM_BAD_INPUT on failure.
- */
-int mbedtls_gcm_finish( mbedtls_gcm_context *ctx,
-                unsigned char *tag,
-                size_t tag_len );
-
-/**
- * \brief           This function clears a GCM context and the underlying
- *                  cipher sub-context.
- *
- * \param ctx       The GCM context to clear. If this is \c NULL, the call has
- *                  no effect. Otherwise, this must be initialized.
- */
-void mbedtls_gcm_free( mbedtls_gcm_context *ctx );
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          The GCM checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_gcm_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* gcm.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/havege.h b/tools/sdk/include/mbedtls/mbedtls/havege.h
deleted file mode 100644
index 75ab3cb9637..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/havege.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
- * \file havege.h
- *
- * \brief HAVEGE: HArdware Volatile Entropy Gathering and Expansion
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_HAVEGE_H
-#define MBEDTLS_HAVEGE_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-#define MBEDTLS_HAVEGE_COLLECT_SIZE 1024
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          HAVEGE state structure
- */
-typedef struct mbedtls_havege_state
-{
-    int PT1, PT2, offset[2];
-    int pool[MBEDTLS_HAVEGE_COLLECT_SIZE];
-    int WALK[8192];
-}
-mbedtls_havege_state;
-
-/**
- * \brief          HAVEGE initialization
- *
- * \param hs       HAVEGE state to be initialized
- */
-void mbedtls_havege_init( mbedtls_havege_state *hs );
-
-/**
- * \brief          Clear HAVEGE state
- *
- * \param hs       HAVEGE state to be cleared
- */
-void mbedtls_havege_free( mbedtls_havege_state *hs );
-
-/**
- * \brief          HAVEGE rand function
- *
- * \param p_rng    A HAVEGE state
- * \param output   Buffer to fill
- * \param len      Length of buffer
- *
- * \return         0
- */
-int mbedtls_havege_random( void *p_rng, unsigned char *output, size_t len );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* havege.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/hkdf.h b/tools/sdk/include/mbedtls/mbedtls/hkdf.h
deleted file mode 100644
index a8db554d9f4..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/hkdf.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/**
- * \file hkdf.h
- *
- * \brief   This file contains the HKDF interface.
- *
- *          The HMAC-based Extract-and-Expand Key Derivation Function (HKDF) is
- *          specified by RFC 5869.
- */
-/*
- *  Copyright (C) 2016-2019, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_HKDF_H
-#define MBEDTLS_HKDF_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "md.h"
-
-/**
- *  \name HKDF Error codes
- *  \{
- */
-#define MBEDTLS_ERR_HKDF_BAD_INPUT_DATA  -0x5F80  /**< Bad input parameters to function. */
-/* \} name */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *  \brief  This is the HMAC-based Extract-and-Expand Key Derivation Function
- *          (HKDF).
- *
- *  \param  md        A hash function; md.size denotes the length of the hash
- *                    function output in bytes.
- *  \param  salt      An optional salt value (a non-secret random value);
- *                    if the salt is not provided, a string of all zeros of
- *                    md.size length is used as the salt.
- *  \param  salt_len  The length in bytes of the optional \p salt.
- *  \param  ikm       The input keying material.
- *  \param  ikm_len   The length in bytes of \p ikm.
- *  \param  info      An optional context and application specific information
- *                    string. This can be a zero-length string.
- *  \param  info_len  The length of \p info in bytes.
- *  \param  okm       The output keying material of \p okm_len bytes.
- *  \param  okm_len   The length of the output keying material in bytes. This
- *                    must be less than or equal to 255 * md.size bytes.
- *
- *  \return 0 on success.
- *  \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid.
- *  \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying
- *          MD layer.
- */
-int mbedtls_hkdf( const mbedtls_md_info_t *md, const unsigned char *salt,
-                  size_t salt_len, const unsigned char *ikm, size_t ikm_len,
-                  const unsigned char *info, size_t info_len,
-                  unsigned char *okm, size_t okm_len );
-
-/**
- *  \brief  Take the input keying material \p ikm and extract from it a
- *          fixed-length pseudorandom key \p prk.
- *
- *  \warning    This function should only be used if the security of it has been
- *              studied and established in that particular context (eg. TLS 1.3
- *              key schedule). For standard HKDF security guarantees use
- *              \c mbedtls_hkdf instead.
- *
- *  \param       md        A hash function; md.size denotes the length of the
- *                         hash function output in bytes.
- *  \param       salt      An optional salt value (a non-secret random value);
- *                         if the salt is not provided, a string of all zeros
- *                         of md.size length is used as the salt.
- *  \param       salt_len  The length in bytes of the optional \p salt.
- *  \param       ikm       The input keying material.
- *  \param       ikm_len   The length in bytes of \p ikm.
- *  \param[out]  prk       A pseudorandom key of at least md.size bytes.
- *
- *  \return 0 on success.
- *  \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid.
- *  \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying
- *          MD layer.
- */
-int mbedtls_hkdf_extract( const mbedtls_md_info_t *md,
-                          const unsigned char *salt, size_t salt_len,
-                          const unsigned char *ikm, size_t ikm_len,
-                          unsigned char *prk );
-
-/**
- *  \brief  Expand the supplied \p prk into several additional pseudorandom
- *          keys, which is the output of the HKDF.
- *
- *  \warning    This function should only be used if the security of it has been
- *              studied and established in that particular context (eg. TLS 1.3
- *              key schedule). For standard HKDF security guarantees use
- *              \c mbedtls_hkdf instead.
- *
- *  \param  md        A hash function; md.size denotes the length of the hash
- *                    function output in bytes.
- *  \param  prk       A pseudorandom key of at least md.size bytes. \p prk is
- *                    usually the output from the HKDF extract step.
- *  \param  prk_len   The length in bytes of \p prk.
- *  \param  info      An optional context and application specific information
- *                    string. This can be a zero-length string.
- *  \param  info_len  The length of \p info in bytes.
- *  \param  okm       The output keying material of \p okm_len bytes.
- *  \param  okm_len   The length of the output keying material in bytes. This
- *                    must be less than or equal to 255 * md.size bytes.
- *
- *  \return 0 on success.
- *  \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid.
- *  \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying
- *          MD layer.
- */
-int mbedtls_hkdf_expand( const mbedtls_md_info_t *md, const unsigned char *prk,
-                         size_t prk_len, const unsigned char *info,
-                         size_t info_len, unsigned char *okm, size_t okm_len );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* hkdf.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h b/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h
deleted file mode 100644
index 231fb459bcf..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/hmac_drbg.h
+++ /dev/null
@@ -1,442 +0,0 @@
-/**
- * \file hmac_drbg.h
- *
- * \brief The HMAC_DRBG pseudorandom generator.
- *
- * This module implements the HMAC_DRBG pseudorandom generator described
- * in <em>NIST SP 800-90A: Recommendation for Random Number Generation Using
- * Deterministic Random Bit Generators</em>.
- */
-/*
- *  Copyright (C) 2006-2019, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_HMAC_DRBG_H
-#define MBEDTLS_HMAC_DRBG_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "md.h"
-
-#if defined(MBEDTLS_THREADING_C)
-#include "threading.h"
-#endif
-
-/*
- * Error codes
- */
-#define MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG              -0x0003  /**< Too many random requested in single call. */
-#define MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG                -0x0005  /**< Input too large (Entropy + additional). */
-#define MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR                -0x0007  /**< Read/write error in file. */
-#define MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED        -0x0009  /**< The entropy source failed. */
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h or define them on the compiler command line.
- * \{
- */
-
-#if !defined(MBEDTLS_HMAC_DRBG_RESEED_INTERVAL)
-#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL   10000   /**< Interval before reseed is performed by default */
-#endif
-
-#if !defined(MBEDTLS_HMAC_DRBG_MAX_INPUT)
-#define MBEDTLS_HMAC_DRBG_MAX_INPUT         256     /**< Maximum number of additional input bytes */
-#endif
-
-#if !defined(MBEDTLS_HMAC_DRBG_MAX_REQUEST)
-#define MBEDTLS_HMAC_DRBG_MAX_REQUEST       1024    /**< Maximum number of requested bytes per call */
-#endif
-
-#if !defined(MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT)
-#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT    384     /**< Maximum size of (re)seed buffer */
-#endif
-
-/* \} name SECTION: Module settings */
-
-#define MBEDTLS_HMAC_DRBG_PR_OFF   0   /**< No prediction resistance       */
-#define MBEDTLS_HMAC_DRBG_PR_ON    1   /**< Prediction resistance enabled  */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * HMAC_DRBG context.
- */
-typedef struct mbedtls_hmac_drbg_context
-{
-    /* Working state: the key K is not stored explicitly,
-     * but is implied by the HMAC context */
-    mbedtls_md_context_t md_ctx;                    /*!< HMAC context (inc. K)  */
-    unsigned char V[MBEDTLS_MD_MAX_SIZE];  /*!< V in the spec          */
-    int reseed_counter;                     /*!< reseed counter         */
-
-    /* Administrative state */
-    size_t entropy_len;         /*!< entropy bytes grabbed on each (re)seed */
-    int prediction_resistance;  /*!< enable prediction resistance (Automatic
-                                     reseed before every random generation) */
-    int reseed_interval;        /*!< reseed interval   */
-
-    /* Callbacks */
-    int (*f_entropy)(void *, unsigned char *, size_t); /*!< entropy function */
-    void *p_entropy;            /*!< context for the entropy function        */
-
-#if defined(MBEDTLS_THREADING_C)
-    mbedtls_threading_mutex_t mutex;
-#endif
-} mbedtls_hmac_drbg_context;
-
-/**
- * \brief               HMAC_DRBG context initialization.
- *
- * This function makes the context ready for mbedtls_hmac_drbg_seed(),
- * mbedtls_hmac_drbg_seed_buf() or mbedtls_hmac_drbg_free().
- *
- * \param ctx           HMAC_DRBG context to be initialized.
- */
-void mbedtls_hmac_drbg_init( mbedtls_hmac_drbg_context *ctx );
-
-/**
- * \brief               HMAC_DRBG initial seeding.
- *
- * Set the initial seed and set up the entropy source for future reseeds.
- *
- * A typical choice for the \p f_entropy and \p p_entropy parameters is
- * to use the entropy module:
- * - \p f_entropy is mbedtls_entropy_func();
- * - \p p_entropy is an instance of ::mbedtls_entropy_context initialized
- *   with mbedtls_entropy_init() (which registers the platform's default
- *   entropy sources).
- *
- * You can provide a personalization string in addition to the
- * entropy source, to make this instantiation as unique as possible.
- *
- * \note                By default, the security strength as defined by NIST is:
- *                      - 128 bits if \p md_info is SHA-1;
- *                      - 192 bits if \p md_info is SHA-224;
- *                      - 256 bits if \p md_info is SHA-256, SHA-384 or SHA-512.
- *                      Note that SHA-256 is just as efficient as SHA-224.
- *                      The security strength can be reduced if a smaller
- *                      entropy length is set with
- *                      mbedtls_hmac_drbg_set_entropy_len().
- *
- * \note                The default entropy length is the security strength
- *                      (converted from bits to bytes). You can override
- *                      it by calling mbedtls_hmac_drbg_set_entropy_len().
- *
- * \note                During the initial seeding, this function calls
- *                      the entropy source to obtain a nonce
- *                      whose length is half the entropy length.
- *
- * \param ctx           HMAC_DRBG context to be seeded.
- * \param md_info       MD algorithm to use for HMAC_DRBG.
- * \param f_entropy     The entropy callback, taking as arguments the
- *                      \p p_entropy context, the buffer to fill, and the
- *                      length of the buffer.
- *                      \p f_entropy is always called with a length that is
- *                      less than or equal to the entropy length.
- * \param p_entropy     The entropy context to pass to \p f_entropy.
- * \param custom        The personalization string.
- *                      This can be \c NULL, in which case the personalization
- *                      string is empty regardless of the value of \p len.
- * \param len           The length of the personalization string.
- *                      This must be at most #MBEDTLS_HMAC_DRBG_MAX_INPUT
- *                      and also at most
- *                      #MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT - \p entropy_len * 3 / 2
- *                      where \p entropy_len is the entropy length
- *                      described above.
- *
- * \return              \c 0 if successful.
- * \return              #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info is
- *                      invalid.
- * \return              #MBEDTLS_ERR_MD_ALLOC_FAILED if there was not enough
- *                      memory to allocate context data.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED
- *                      if the call to \p f_entropy failed.
- */
-int mbedtls_hmac_drbg_seed( mbedtls_hmac_drbg_context *ctx,
-                    const mbedtls_md_info_t * md_info,
-                    int (*f_entropy)(void *, unsigned char *, size_t),
-                    void *p_entropy,
-                    const unsigned char *custom,
-                    size_t len );
-
-/**
- * \brief               Initilisation of simpified HMAC_DRBG (never reseeds).
- *
- * This function is meant for use in algorithms that need a pseudorandom
- * input such as deterministic ECDSA.
- *
- * \param ctx           HMAC_DRBG context to be initialised.
- * \param md_info       MD algorithm to use for HMAC_DRBG.
- * \param data          Concatenation of the initial entropy string and
- *                      the additional data.
- * \param data_len      Length of \p data in bytes.
- *
- * \return              \c 0 if successful. or
- * \return              #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info is
- *                      invalid.
- * \return              #MBEDTLS_ERR_MD_ALLOC_FAILED if there was not enough
- *                      memory to allocate context data.
- */
-int mbedtls_hmac_drbg_seed_buf( mbedtls_hmac_drbg_context *ctx,
-                        const mbedtls_md_info_t * md_info,
-                        const unsigned char *data, size_t data_len );
-
-/**
- * \brief               This function turns prediction resistance on or off.
- *                      The default value is off.
- *
- * \note                If enabled, entropy is gathered at the beginning of
- *                      every call to mbedtls_hmac_drbg_random_with_add()
- *                      or mbedtls_hmac_drbg_random().
- *                      Only use this if your entropy source has sufficient
- *                      throughput.
- *
- * \param ctx           The HMAC_DRBG context.
- * \param resistance    #MBEDTLS_HMAC_DRBG_PR_ON or #MBEDTLS_HMAC_DRBG_PR_OFF.
- */
-void mbedtls_hmac_drbg_set_prediction_resistance( mbedtls_hmac_drbg_context *ctx,
-                                          int resistance );
-
-/**
- * \brief               This function sets the amount of entropy grabbed on each
- *                      seed or reseed.
- *
- * See the documentation of mbedtls_hmac_drbg_seed() for the default value.
- *
- * \param ctx           The HMAC_DRBG context.
- * \param len           The amount of entropy to grab, in bytes.
- */
-void mbedtls_hmac_drbg_set_entropy_len( mbedtls_hmac_drbg_context *ctx,
-                                size_t len );
-
-/**
- * \brief               Set the reseed interval.
- *
- * The reseed interval is the number of calls to mbedtls_hmac_drbg_random()
- * or mbedtls_hmac_drbg_random_with_add() after which the entropy function
- * is called again.
- *
- * The default value is #MBEDTLS_HMAC_DRBG_RESEED_INTERVAL.
- *
- * \param ctx           The HMAC_DRBG context.
- * \param interval      The reseed interval.
- */
-void mbedtls_hmac_drbg_set_reseed_interval( mbedtls_hmac_drbg_context *ctx,
-                                    int interval );
-
-/**
- * \brief               This function updates the state of the HMAC_DRBG context.
- *
- * \param ctx           The HMAC_DRBG context.
- * \param additional    The data to update the state with.
- *                      If this is \c NULL, there is no additional data.
- * \param add_len       Length of \p additional in bytes.
- *                      Unused if \p additional is \c NULL.
- *
- * \return              \c 0 on success, or an error from the underlying
- *                      hash calculation.
- */
-int mbedtls_hmac_drbg_update_ret( mbedtls_hmac_drbg_context *ctx,
-                       const unsigned char *additional, size_t add_len );
-
-/**
- * \brief               This function reseeds the HMAC_DRBG context, that is
- *                      extracts data from the entropy source.
- *
- * \param ctx           The HMAC_DRBG context.
- * \param additional    Additional data to add to the state.
- *                      If this is \c NULL, there is no additional data
- *                      and \p len should be \c 0.
- * \param len           The length of the additional data.
- *                      This must be at most #MBEDTLS_HMAC_DRBG_MAX_INPUT
- *                      and also at most
- *                      #MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT - \p entropy_len
- *                      where \p entropy_len is the entropy length
- *                      (see mbedtls_hmac_drbg_set_entropy_len()).
- *
- * \return              \c 0 if successful.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED
- *                      if a call to the entropy function failed.
- */
-int mbedtls_hmac_drbg_reseed( mbedtls_hmac_drbg_context *ctx,
-                      const unsigned char *additional, size_t len );
-
-/**
- * \brief   This function updates an HMAC_DRBG instance with additional
- *          data and uses it to generate random data.
- *
- * This function automatically reseeds if the reseed counter is exceeded
- * or prediction resistance is enabled.
- *
- * \param p_rng         The HMAC_DRBG context. This must be a pointer to a
- *                      #mbedtls_hmac_drbg_context structure.
- * \param output        The buffer to fill.
- * \param output_len    The length of the buffer in bytes.
- *                      This must be at most #MBEDTLS_HMAC_DRBG_MAX_REQUEST.
- * \param additional    Additional data to update with.
- *                      If this is \c NULL, there is no additional data
- *                      and \p add_len should be \c 0.
- * \param add_len       The length of the additional data.
- *                      This must be at most #MBEDTLS_HMAC_DRBG_MAX_INPUT.
- *
- * \return              \c 0 if successful.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED
- *                      if a call to the entropy source failed.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG if
- *                      \p output_len > #MBEDTLS_HMAC_DRBG_MAX_REQUEST.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG if
- *                      \p add_len > #MBEDTLS_HMAC_DRBG_MAX_INPUT.
- */
-int mbedtls_hmac_drbg_random_with_add( void *p_rng,
-                               unsigned char *output, size_t output_len,
-                               const unsigned char *additional,
-                               size_t add_len );
-
-/**
- * \brief   This function uses HMAC_DRBG to generate random data.
- *
- * This function automatically reseeds if the reseed counter is exceeded
- * or prediction resistance is enabled.
- *
- * \param p_rng         The HMAC_DRBG context. This must be a pointer to a
- *                      #mbedtls_hmac_drbg_context structure.
- * \param output        The buffer to fill.
- * \param out_len       The length of the buffer in bytes.
- *                      This must be at most #MBEDTLS_HMAC_DRBG_MAX_REQUEST.
- *
- * \return              \c 0 if successful.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED
- *                      if a call to the entropy source failed.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG if
- *                      \p out_len > #MBEDTLS_HMAC_DRBG_MAX_REQUEST.
- */
-int mbedtls_hmac_drbg_random( void *p_rng, unsigned char *output, size_t out_len );
-
-/**
- * \brief               Free an HMAC_DRBG context
- *
- * \param ctx           The HMAC_DRBG context to free.
- */
-void mbedtls_hmac_drbg_free( mbedtls_hmac_drbg_context *ctx );
-
-#if ! defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED    __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief               This function updates the state of the HMAC_DRBG context.
- *
- * \deprecated          Superseded by mbedtls_hmac_drbg_update_ret()
- *                      in 2.16.0.
- *
- * \param ctx           The HMAC_DRBG context.
- * \param additional    The data to update the state with.
- *                      If this is \c NULL, there is no additional data.
- * \param add_len       Length of \p additional in bytes.
- *                      Unused if \p additional is \c NULL.
- */
-MBEDTLS_DEPRECATED void mbedtls_hmac_drbg_update(
-    mbedtls_hmac_drbg_context *ctx,
-    const unsigned char *additional, size_t add_len );
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-#if defined(MBEDTLS_FS_IO)
-/**
- * \brief               This function writes a seed file.
- *
- * \param ctx           The HMAC_DRBG context.
- * \param path          The name of the file.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR on file error.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED on reseed
- *                      failure.
- */
-int mbedtls_hmac_drbg_write_seed_file( mbedtls_hmac_drbg_context *ctx, const char *path );
-
-/**
- * \brief               This function reads and updates a seed file. The seed
- *                      is added to this instance.
- *
- * \param ctx           The HMAC_DRBG context.
- * \param path          The name of the file.
- *
- * \return              \c 0 on success.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR on file error.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED on
- *                      reseed failure.
- * \return              #MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG if the existing
- *                      seed file is too large.
- */
-int mbedtls_hmac_drbg_update_seed_file( mbedtls_hmac_drbg_context *ctx, const char *path );
-#endif /* MBEDTLS_FS_IO */
-
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief               The HMAC_DRBG Checkup routine.
- *
- * \return              \c 0 if successful.
- * \return              \c 1 if the test failed.
- */
-int mbedtls_hmac_drbg_self_test( int verbose );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* hmac_drbg.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md.h b/tools/sdk/include/mbedtls/mbedtls/md.h
deleted file mode 100644
index 6a21f059082..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/md.h
+++ /dev/null
@@ -1,497 +0,0 @@
- /**
- * \file md.h
- *
- * \brief This file contains the generic message-digest wrapper.
- *
- * \author Adriaan de Jong <dejong@fox-it.com>
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_MD_H
-#define MBEDTLS_MD_H
-
-#include <stddef.h>
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#define MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE                -0x5080  /**< The selected feature is not available. */
-#define MBEDTLS_ERR_MD_BAD_INPUT_DATA                     -0x5100  /**< Bad input parameters to function. */
-#define MBEDTLS_ERR_MD_ALLOC_FAILED                       -0x5180  /**< Failed to allocate memory. */
-#define MBEDTLS_ERR_MD_FILE_IO_ERROR                      -0x5200  /**< Opening or reading of file failed. */
-
-/* MBEDTLS_ERR_MD_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_MD_HW_ACCEL_FAILED                    -0x5280  /**< MD hardware accelerator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief     Supported message digests.
- *
- * \warning   MD2, MD4, MD5 and SHA-1 are considered weak message digests and
- *            their use constitutes a security risk. We recommend considering
- *            stronger message digests instead.
- *
- */
-typedef enum {
-    MBEDTLS_MD_NONE=0,    /**< None. */
-    MBEDTLS_MD_MD2,       /**< The MD2 message digest. */
-    MBEDTLS_MD_MD4,       /**< The MD4 message digest. */
-    MBEDTLS_MD_MD5,       /**< The MD5 message digest. */
-    MBEDTLS_MD_SHA1,      /**< The SHA-1 message digest. */
-    MBEDTLS_MD_SHA224,    /**< The SHA-224 message digest. */
-    MBEDTLS_MD_SHA256,    /**< The SHA-256 message digest. */
-    MBEDTLS_MD_SHA384,    /**< The SHA-384 message digest. */
-    MBEDTLS_MD_SHA512,    /**< The SHA-512 message digest. */
-    MBEDTLS_MD_RIPEMD160, /**< The RIPEMD-160 message digest. */
-} mbedtls_md_type_t;
-
-#if defined(MBEDTLS_SHA512_C)
-#define MBEDTLS_MD_MAX_SIZE         64  /* longest known is SHA512 */
-#else
-#define MBEDTLS_MD_MAX_SIZE         32  /* longest known is SHA256 or less */
-#endif
-
-/**
- * Opaque struct defined in md_internal.h.
- */
-typedef struct mbedtls_md_info_t mbedtls_md_info_t;
-
-/**
- * The generic message-digest context.
- */
-typedef struct mbedtls_md_context_t
-{
-    /** Information about the associated message digest. */
-    const mbedtls_md_info_t *md_info;
-
-    /** The digest-specific context. */
-    void *md_ctx;
-
-    /** The HMAC part of the context. */
-    void *hmac_ctx;
-} mbedtls_md_context_t;
-
-/**
- * \brief           This function returns the list of digests supported by the
- *                  generic digest module.
- *
- * \note            The list starts with the strongest available hashes.
- *
- * \return          A statically allocated array of digests. Each element
- *                  in the returned list is an integer belonging to the
- *                  message-digest enumeration #mbedtls_md_type_t.
- *                  The last entry is 0.
- */
-const int *mbedtls_md_list( void );
-
-/**
- * \brief           This function returns the message-digest information
- *                  associated with the given digest name.
- *
- * \param md_name   The name of the digest to search for.
- *
- * \return          The message-digest information associated with \p md_name.
- * \return          NULL if the associated message-digest information is not found.
- */
-const mbedtls_md_info_t *mbedtls_md_info_from_string( const char *md_name );
-
-/**
- * \brief           This function returns the message-digest information
- *                  associated with the given digest type.
- *
- * \param md_type   The type of digest to search for.
- *
- * \return          The message-digest information associated with \p md_type.
- * \return          NULL if the associated message-digest information is not found.
- */
-const mbedtls_md_info_t *mbedtls_md_info_from_type( mbedtls_md_type_t md_type );
-
-/**
- * \brief           This function initializes a message-digest context without
- *                  binding it to a particular message-digest algorithm.
- *
- *                  This function should always be called first. It prepares the
- *                  context for mbedtls_md_setup() for binding it to a
- *                  message-digest algorithm.
- */
-void mbedtls_md_init( mbedtls_md_context_t *ctx );
-
-/**
- * \brief           This function clears the internal structure of \p ctx and
- *                  frees any embedded internal structure, but does not free
- *                  \p ctx itself.
- *
- *                  If you have called mbedtls_md_setup() on \p ctx, you must
- *                  call mbedtls_md_free() when you are no longer using the
- *                  context.
- *                  Calling this function if you have previously
- *                  called mbedtls_md_init() and nothing else is optional.
- *                  You must not call this function if you have not called
- *                  mbedtls_md_init().
- */
-void mbedtls_md_free( mbedtls_md_context_t *ctx );
-
-#if ! defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED    __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief           This function selects the message digest algorithm to use,
- *                  and allocates internal structures.
- *
- *                  It should be called after mbedtls_md_init() or mbedtls_md_free().
- *                  Makes it necessary to call mbedtls_md_free() later.
- *
- * \deprecated      Superseded by mbedtls_md_setup() in 2.0.0
- *
- * \param ctx       The context to set up.
- * \param md_info   The information structure of the message-digest algorithm
- *                  to use.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                  failure.
- * \return          #MBEDTLS_ERR_MD_ALLOC_FAILED on memory-allocation failure.
- */
-int mbedtls_md_init_ctx( mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info ) MBEDTLS_DEPRECATED;
-#undef MBEDTLS_DEPRECATED
-#endif /* MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief           This function selects the message digest algorithm to use,
- *                  and allocates internal structures.
- *
- *                  It should be called after mbedtls_md_init() or
- *                  mbedtls_md_free(). Makes it necessary to call
- *                  mbedtls_md_free() later.
- *
- * \param ctx       The context to set up.
- * \param md_info   The information structure of the message-digest algorithm
- *                  to use.
- * \param hmac      Defines if HMAC is used. 0: HMAC is not used (saves some memory),
- *                  or non-zero: HMAC is used with this context.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                  failure.
- * \return          #MBEDTLS_ERR_MD_ALLOC_FAILED on memory-allocation failure.
- */
-int mbedtls_md_setup( mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info, int hmac );
-
-/**
- * \brief           This function clones the state of an message-digest
- *                  context.
- *
- * \note            You must call mbedtls_md_setup() on \c dst before calling
- *                  this function.
- *
- * \note            The two contexts must have the same type,
- *                  for example, both are SHA-256.
- *
- * \warning         This function clones the message-digest state, not the
- *                  HMAC state.
- *
- * \param dst       The destination context.
- * \param src       The context to be cloned.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification failure.
- */
-int mbedtls_md_clone( mbedtls_md_context_t *dst,
-                      const mbedtls_md_context_t *src );
-
-/**
- * \brief           This function extracts the message-digest size from the
- *                  message-digest information structure.
- *
- * \param md_info   The information structure of the message-digest algorithm
- *                  to use.
- *
- * \return          The size of the message-digest output in Bytes.
- */
-unsigned char mbedtls_md_get_size( const mbedtls_md_info_t *md_info );
-
-/**
- * \brief           This function extracts the message-digest type from the
- *                  message-digest information structure.
- *
- * \param md_info   The information structure of the message-digest algorithm
- *                  to use.
- *
- * \return          The type of the message digest.
- */
-mbedtls_md_type_t mbedtls_md_get_type( const mbedtls_md_info_t *md_info );
-
-/**
- * \brief           This function extracts the message-digest name from the
- *                  message-digest information structure.
- *
- * \param md_info   The information structure of the message-digest algorithm
- *                  to use.
- *
- * \return          The name of the message digest.
- */
-const char *mbedtls_md_get_name( const mbedtls_md_info_t *md_info );
-
-/**
- * \brief           This function starts a message-digest computation.
- *
- *                  You must call this function after setting up the context
- *                  with mbedtls_md_setup(), and before passing data with
- *                  mbedtls_md_update().
- *
- * \param ctx       The generic message-digest context.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                  failure.
- */
-int mbedtls_md_starts( mbedtls_md_context_t *ctx );
-
-/**
- * \brief           This function feeds an input buffer into an ongoing
- *                  message-digest computation.
- *
- *                  You must call mbedtls_md_starts() before calling this
- *                  function. You may call this function multiple times.
- *                  Afterwards, call mbedtls_md_finish().
- *
- * \param ctx       The generic message-digest context.
- * \param input     The buffer holding the input data.
- * \param ilen      The length of the input data.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                  failure.
- */
-int mbedtls_md_update( mbedtls_md_context_t *ctx, const unsigned char *input, size_t ilen );
-
-/**
- * \brief           This function finishes the digest operation,
- *                  and writes the result to the output buffer.
- *
- *                  Call this function after a call to mbedtls_md_starts(),
- *                  followed by any number of calls to mbedtls_md_update().
- *                  Afterwards, you may either clear the context with
- *                  mbedtls_md_free(), or call mbedtls_md_starts() to reuse
- *                  the context for another digest operation with the same
- *                  algorithm.
- *
- * \param ctx       The generic message-digest context.
- * \param output    The buffer for the generic message-digest checksum result.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                  failure.
- */
-int mbedtls_md_finish( mbedtls_md_context_t *ctx, unsigned char *output );
-
-/**
- * \brief          This function calculates the message-digest of a buffer,
- *                 with respect to a configurable message-digest algorithm
- *                 in a single call.
- *
- *                 The result is calculated as
- *                 Output = message_digest(input buffer).
- *
- * \param md_info  The information structure of the message-digest algorithm
- *                 to use.
- * \param input    The buffer holding the data.
- * \param ilen     The length of the input data.
- * \param output   The generic message-digest checksum result.
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                 failure.
- */
-int mbedtls_md( const mbedtls_md_info_t *md_info, const unsigned char *input, size_t ilen,
-        unsigned char *output );
-
-#if defined(MBEDTLS_FS_IO)
-/**
- * \brief          This function calculates the message-digest checksum
- *                 result of the contents of the provided file.
- *
- *                 The result is calculated as
- *                 Output = message_digest(file contents).
- *
- * \param md_info  The information structure of the message-digest algorithm
- *                 to use.
- * \param path     The input file name.
- * \param output   The generic message-digest checksum result.
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_MD_FILE_IO_ERROR on an I/O error accessing
- *                 the file pointed by \p path.
- * \return         #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info was NULL.
- */
-int mbedtls_md_file( const mbedtls_md_info_t *md_info, const char *path,
-                     unsigned char *output );
-#endif /* MBEDTLS_FS_IO */
-
-/**
- * \brief           This function sets the HMAC key and prepares to
- *                  authenticate a new message.
- *
- *                  Call this function after mbedtls_md_setup(), to use
- *                  the MD context for an HMAC calculation, then call
- *                  mbedtls_md_hmac_update() to provide the input data, and
- *                  mbedtls_md_hmac_finish() to get the HMAC value.
- *
- * \param ctx       The message digest context containing an embedded HMAC
- *                  context.
- * \param key       The HMAC secret key.
- * \param keylen    The length of the HMAC key in Bytes.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                  failure.
- */
-int mbedtls_md_hmac_starts( mbedtls_md_context_t *ctx, const unsigned char *key,
-                    size_t keylen );
-
-/**
- * \brief           This function feeds an input buffer into an ongoing HMAC
- *                  computation.
- *
- *                  Call mbedtls_md_hmac_starts() or mbedtls_md_hmac_reset()
- *                  before calling this function.
- *                  You may call this function multiple times to pass the
- *                  input piecewise.
- *                  Afterwards, call mbedtls_md_hmac_finish().
- *
- * \param ctx       The message digest context containing an embedded HMAC
- *                  context.
- * \param input     The buffer holding the input data.
- * \param ilen      The length of the input data.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                  failure.
- */
-int mbedtls_md_hmac_update( mbedtls_md_context_t *ctx, const unsigned char *input,
-                    size_t ilen );
-
-/**
- * \brief           This function finishes the HMAC operation, and writes
- *                  the result to the output buffer.
- *
- *                  Call this function after mbedtls_md_hmac_starts() and
- *                  mbedtls_md_hmac_update() to get the HMAC value. Afterwards
- *                  you may either call mbedtls_md_free() to clear the context,
- *                  or call mbedtls_md_hmac_reset() to reuse the context with
- *                  the same HMAC key.
- *
- * \param ctx       The message digest context containing an embedded HMAC
- *                  context.
- * \param output    The generic HMAC checksum result.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                  failure.
- */
-int mbedtls_md_hmac_finish( mbedtls_md_context_t *ctx, unsigned char *output);
-
-/**
- * \brief           This function prepares to authenticate a new message with
- *                  the same key as the previous HMAC operation.
- *
- *                  You may call this function after mbedtls_md_hmac_finish().
- *                  Afterwards call mbedtls_md_hmac_update() to pass the new
- *                  input.
- *
- * \param ctx       The message digest context containing an embedded HMAC
- *                  context.
- *
- * \return          \c 0 on success.
- * \return          #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                  failure.
- */
-int mbedtls_md_hmac_reset( mbedtls_md_context_t *ctx );
-
-/**
- * \brief          This function calculates the full generic HMAC
- *                 on the input buffer with the provided key.
- *
- *                 The function allocates the context, performs the
- *                 calculation, and frees the context.
- *
- *                 The HMAC result is calculated as
- *                 output = generic HMAC(hmac key, input buffer).
- *
- * \param md_info  The information structure of the message-digest algorithm
- *                 to use.
- * \param key      The HMAC secret key.
- * \param keylen   The length of the HMAC secret key in Bytes.
- * \param input    The buffer holding the input data.
- * \param ilen     The length of the input data.
- * \param output   The generic HMAC result.
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification
- *                 failure.
- */
-int mbedtls_md_hmac( const mbedtls_md_info_t *md_info, const unsigned char *key, size_t keylen,
-                const unsigned char *input, size_t ilen,
-                unsigned char *output );
-
-/* Internal use */
-int mbedtls_md_process( mbedtls_md_context_t *ctx, const unsigned char *data );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_MD_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md2.h b/tools/sdk/include/mbedtls/mbedtls/md2.h
deleted file mode 100644
index 6d563b41bec..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/md2.h
+++ /dev/null
@@ -1,333 +0,0 @@
-/**
- * \file md2.h
- *
- * \brief MD2 message digest algorithm (hash function)
- *
- * \warning MD2 is considered a weak message digest and its use constitutes a
- *          security risk. We recommend considering stronger message digests
- *          instead.
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- *
- */
-#ifndef MBEDTLS_MD2_H
-#define MBEDTLS_MD2_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-/* MBEDTLS_ERR_MD2_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_MD2_HW_ACCEL_FAILED                   -0x002B  /**< MD2 hardware accelerator failed */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_MD2_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          MD2 context structure
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-typedef struct mbedtls_md2_context
-{
-    unsigned char cksum[16];    /*!< checksum of the data block */
-    unsigned char state[48];    /*!< intermediate digest state  */
-    unsigned char buffer[16];   /*!< data block being processed */
-    size_t left;                /*!< amount of data in buffer   */
-}
-mbedtls_md2_context;
-
-#else  /* MBEDTLS_MD2_ALT */
-#include "md2_alt.h"
-#endif /* MBEDTLS_MD2_ALT */
-
-/**
- * \brief          Initialize MD2 context
- *
- * \param ctx      MD2 context to be initialized
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-void mbedtls_md2_init( mbedtls_md2_context *ctx );
-
-/**
- * \brief          Clear MD2 context
- *
- * \param ctx      MD2 context to be cleared
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-void mbedtls_md2_free( mbedtls_md2_context *ctx );
-
-/**
- * \brief          Clone (the state of) an MD2 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-void mbedtls_md2_clone( mbedtls_md2_context *dst,
-                        const mbedtls_md2_context *src );
-
-/**
- * \brief          MD2 context setup
- *
- * \param ctx      context to be initialized
- *
- * \return         0 if successful
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md2_starts_ret( mbedtls_md2_context *ctx );
-
-/**
- * \brief          MD2 process buffer
- *
- * \param ctx      MD2 context
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- *
- * \return         0 if successful
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md2_update_ret( mbedtls_md2_context *ctx,
-                            const unsigned char *input,
-                            size_t ilen );
-
-/**
- * \brief          MD2 final digest
- *
- * \param ctx      MD2 context
- * \param output   MD2 checksum result
- *
- * \return         0 if successful
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md2_finish_ret( mbedtls_md2_context *ctx,
-                            unsigned char output[16] );
-
-/**
- * \brief          MD2 process data block (internal use only)
- *
- * \param ctx      MD2 context
- *
- * \return         0 if successful
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_internal_md2_process( mbedtls_md2_context *ctx );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          MD2 context setup
- *
- * \deprecated     Superseded by mbedtls_md2_starts_ret() in 2.7.0
- *
- * \param ctx      context to be initialized
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md2_starts( mbedtls_md2_context *ctx );
-
-/**
- * \brief          MD2 process buffer
- *
- * \deprecated     Superseded by mbedtls_md2_update_ret() in 2.7.0
- *
- * \param ctx      MD2 context
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md2_update( mbedtls_md2_context *ctx,
-                                            const unsigned char *input,
-                                            size_t ilen );
-
-/**
- * \brief          MD2 final digest
- *
- * \deprecated     Superseded by mbedtls_md2_finish_ret() in 2.7.0
- *
- * \param ctx      MD2 context
- * \param output   MD2 checksum result
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md2_finish( mbedtls_md2_context *ctx,
-                                            unsigned char output[16] );
-
-/**
- * \brief          MD2 process data block (internal use only)
- *
- * \deprecated     Superseded by mbedtls_internal_md2_process() in 2.7.0
- *
- * \param ctx      MD2 context
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md2_process( mbedtls_md2_context *ctx );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief          Output = MD2( input buffer )
- *
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- * \param output   MD2 checksum result
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md2_ret( const unsigned char *input,
-                     size_t ilen,
-                     unsigned char output[16] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          Output = MD2( input buffer )
- *
- * \deprecated     Superseded by mbedtls_md2_ret() in 2.7.0
- *
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- * \param output   MD2 checksum result
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md2( const unsigned char *input,
-                                     size_t ilen,
-                                     unsigned char output[16] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- *
- * \warning        MD2 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md2_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_md2.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md4.h b/tools/sdk/include/mbedtls/mbedtls/md4.h
deleted file mode 100644
index 3f4bcdc607b..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/md4.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/**
- * \file md4.h
- *
- * \brief MD4 message digest algorithm (hash function)
- *
- * \warning MD4 is considered a weak message digest and its use constitutes a
- *          security risk. We recommend considering stronger message digests
- *          instead.
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- *
- */
-#ifndef MBEDTLS_MD4_H
-#define MBEDTLS_MD4_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* MBEDTLS_ERR_MD4_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_MD4_HW_ACCEL_FAILED                   -0x002D  /**< MD4 hardware accelerator failed */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_MD4_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          MD4 context structure
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-typedef struct mbedtls_md4_context
-{
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[4];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-}
-mbedtls_md4_context;
-
-#else  /* MBEDTLS_MD4_ALT */
-#include "md4_alt.h"
-#endif /* MBEDTLS_MD4_ALT */
-
-/**
- * \brief          Initialize MD4 context
- *
- * \param ctx      MD4 context to be initialized
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-void mbedtls_md4_init( mbedtls_md4_context *ctx );
-
-/**
- * \brief          Clear MD4 context
- *
- * \param ctx      MD4 context to be cleared
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-void mbedtls_md4_free( mbedtls_md4_context *ctx );
-
-/**
- * \brief          Clone (the state of) an MD4 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-void mbedtls_md4_clone( mbedtls_md4_context *dst,
-                        const mbedtls_md4_context *src );
-
-/**
- * \brief          MD4 context setup
- *
- * \param ctx      context to be initialized
- *
- * \return         0 if successful
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- */
-int mbedtls_md4_starts_ret( mbedtls_md4_context *ctx );
-
-/**
- * \brief          MD4 process buffer
- *
- * \param ctx      MD4 context
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- *
- * \return         0 if successful
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md4_update_ret( mbedtls_md4_context *ctx,
-                            const unsigned char *input,
-                            size_t ilen );
-
-/**
- * \brief          MD4 final digest
- *
- * \param ctx      MD4 context
- * \param output   MD4 checksum result
- *
- * \return         0 if successful
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md4_finish_ret( mbedtls_md4_context *ctx,
-                            unsigned char output[16] );
-
-/**
- * \brief          MD4 process data block (internal use only)
- *
- * \param ctx      MD4 context
- * \param data     buffer holding one block of data
- *
- * \return         0 if successful
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_internal_md4_process( mbedtls_md4_context *ctx,
-                                  const unsigned char data[64] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          MD4 context setup
- *
- * \deprecated     Superseded by mbedtls_md4_starts_ret() in 2.7.0
- *
- * \param ctx      context to be initialized
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md4_starts( mbedtls_md4_context *ctx );
-
-/**
- * \brief          MD4 process buffer
- *
- * \deprecated     Superseded by mbedtls_md4_update_ret() in 2.7.0
- *
- * \param ctx      MD4 context
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md4_update( mbedtls_md4_context *ctx,
-                                            const unsigned char *input,
-                                            size_t ilen );
-
-/**
- * \brief          MD4 final digest
- *
- * \deprecated     Superseded by mbedtls_md4_finish_ret() in 2.7.0
- *
- * \param ctx      MD4 context
- * \param output   MD4 checksum result
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md4_finish( mbedtls_md4_context *ctx,
-                                            unsigned char output[16] );
-
-/**
- * \brief          MD4 process data block (internal use only)
- *
- * \deprecated     Superseded by mbedtls_internal_md4_process() in 2.7.0
- *
- * \param ctx      MD4 context
- * \param data     buffer holding one block of data
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md4_process( mbedtls_md4_context *ctx,
-                                             const unsigned char data[64] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief          Output = MD4( input buffer )
- *
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- * \param output   MD4 checksum result
- *
- * \return         0 if successful
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md4_ret( const unsigned char *input,
-                     size_t ilen,
-                     unsigned char output[16] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          Output = MD4( input buffer )
- *
- * \deprecated     Superseded by mbedtls_md4_ret() in 2.7.0
- *
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- * \param output   MD4 checksum result
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md4( const unsigned char *input,
-                                     size_t ilen,
-                                     unsigned char output[16] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- *
- * \warning        MD4 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md4_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_md4.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md5.h b/tools/sdk/include/mbedtls/mbedtls/md5.h
deleted file mode 100644
index 34279c72121..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/md5.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/**
- * \file md5.h
- *
- * \brief MD5 message digest algorithm (hash function)
- *
- * \warning   MD5 is considered a weak message digest and its use constitutes a
- *            security risk. We recommend considering stronger message
- *            digests instead.
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_MD5_H
-#define MBEDTLS_MD5_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* MBEDTLS_ERR_MD5_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_MD5_HW_ACCEL_FAILED                   -0x002F  /**< MD5 hardware accelerator failed */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_MD5_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          MD5 context structure
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-typedef struct mbedtls_md5_context
-{
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[4];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-}
-mbedtls_md5_context;
-
-#else  /* MBEDTLS_MD5_ALT */
-#include "md5_alt.h"
-#endif /* MBEDTLS_MD5_ALT */
-
-/**
- * \brief          Initialize MD5 context
- *
- * \param ctx      MD5 context to be initialized
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-void mbedtls_md5_init( mbedtls_md5_context *ctx );
-
-/**
- * \brief          Clear MD5 context
- *
- * \param ctx      MD5 context to be cleared
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-void mbedtls_md5_free( mbedtls_md5_context *ctx );
-
-/**
- * \brief          Clone (the state of) an MD5 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-void mbedtls_md5_clone( mbedtls_md5_context *dst,
-                        const mbedtls_md5_context *src );
-
-/**
- * \brief          MD5 context setup
- *
- * \param ctx      context to be initialized
- *
- * \return         0 if successful
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md5_starts_ret( mbedtls_md5_context *ctx );
-
-/**
- * \brief          MD5 process buffer
- *
- * \param ctx      MD5 context
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- *
- * \return         0 if successful
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md5_update_ret( mbedtls_md5_context *ctx,
-                            const unsigned char *input,
-                            size_t ilen );
-
-/**
- * \brief          MD5 final digest
- *
- * \param ctx      MD5 context
- * \param output   MD5 checksum result
- *
- * \return         0 if successful
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md5_finish_ret( mbedtls_md5_context *ctx,
-                            unsigned char output[16] );
-
-/**
- * \brief          MD5 process data block (internal use only)
- *
- * \param ctx      MD5 context
- * \param data     buffer holding one block of data
- *
- * \return         0 if successful
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_internal_md5_process( mbedtls_md5_context *ctx,
-                                  const unsigned char data[64] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          MD5 context setup
- *
- * \deprecated     Superseded by mbedtls_md5_starts_ret() in 2.7.0
- *
- * \param ctx      context to be initialized
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md5_starts( mbedtls_md5_context *ctx );
-
-/**
- * \brief          MD5 process buffer
- *
- * \deprecated     Superseded by mbedtls_md5_update_ret() in 2.7.0
- *
- * \param ctx      MD5 context
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md5_update( mbedtls_md5_context *ctx,
-                                            const unsigned char *input,
-                                            size_t ilen );
-
-/**
- * \brief          MD5 final digest
- *
- * \deprecated     Superseded by mbedtls_md5_finish_ret() in 2.7.0
- *
- * \param ctx      MD5 context
- * \param output   MD5 checksum result
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md5_finish( mbedtls_md5_context *ctx,
-                                            unsigned char output[16] );
-
-/**
- * \brief          MD5 process data block (internal use only)
- *
- * \deprecated     Superseded by mbedtls_internal_md5_process() in 2.7.0
- *
- * \param ctx      MD5 context
- * \param data     buffer holding one block of data
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md5_process( mbedtls_md5_context *ctx,
-                                             const unsigned char data[64] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief          Output = MD5( input buffer )
- *
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- * \param output   MD5 checksum result
- *
- * \return         0 if successful
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md5_ret( const unsigned char *input,
-                     size_t ilen,
-                     unsigned char output[16] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          Output = MD5( input buffer )
- *
- * \deprecated     Superseded by mbedtls_md5_ret() in 2.7.0
- *
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- * \param output   MD5 checksum result
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_md5( const unsigned char *input,
-                                     size_t ilen,
-                                     unsigned char output[16] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- *
- * \warning        MD5 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-int mbedtls_md5_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_md5.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/md_internal.h b/tools/sdk/include/mbedtls/mbedtls/md_internal.h
deleted file mode 100644
index 154b8bbc270..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/md_internal.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/**
- * \file md_internal.h
- *
- * \brief Message digest wrappers.
- *
- * \warning This in an internal header. Do not include directly.
- *
- * \author Adriaan de Jong <dejong@fox-it.com>
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_MD_WRAP_H
-#define MBEDTLS_MD_WRAP_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "md.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Message digest information.
- * Allows message digest functions to be called in a generic way.
- */
-struct mbedtls_md_info_t
-{
-    /** Digest identifier */
-    mbedtls_md_type_t type;
-
-    /** Name of the message digest */
-    const char * name;
-
-    /** Output length of the digest function in bytes */
-    int size;
-
-    /** Block length of the digest function in bytes */
-    int block_size;
-
-    /** Digest initialisation function */
-    int (*starts_func)( void *ctx );
-
-    /** Digest update function */
-    int (*update_func)( void *ctx, const unsigned char *input, size_t ilen );
-
-    /** Digest finalisation function */
-    int (*finish_func)( void *ctx, unsigned char *output );
-
-    /** Generic digest function */
-    int (*digest_func)( const unsigned char *input, size_t ilen,
-                        unsigned char *output );
-
-    /** Allocate a new context */
-    void * (*ctx_alloc_func)( void );
-
-    /** Free the given context */
-    void (*ctx_free_func)( void *ctx );
-
-    /** Clone state from a context */
-    void (*clone_func)( void *dst, const void *src );
-
-    /** Internal use only */
-    int (*process_func)( void *ctx, const unsigned char *input );
-};
-
-#if defined(MBEDTLS_MD2_C)
-extern const mbedtls_md_info_t mbedtls_md2_info;
-#endif
-#if defined(MBEDTLS_MD4_C)
-extern const mbedtls_md_info_t mbedtls_md4_info;
-#endif
-#if defined(MBEDTLS_MD5_C)
-extern const mbedtls_md_info_t mbedtls_md5_info;
-#endif
-#if defined(MBEDTLS_RIPEMD160_C)
-extern const mbedtls_md_info_t mbedtls_ripemd160_info;
-#endif
-#if defined(MBEDTLS_SHA1_C)
-extern const mbedtls_md_info_t mbedtls_sha1_info;
-#endif
-#if defined(MBEDTLS_SHA256_C)
-extern const mbedtls_md_info_t mbedtls_sha224_info;
-extern const mbedtls_md_info_t mbedtls_sha256_info;
-#endif
-#if defined(MBEDTLS_SHA512_C)
-extern const mbedtls_md_info_t mbedtls_sha384_info;
-extern const mbedtls_md_info_t mbedtls_sha512_info;
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_MD_WRAP_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h b/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h
deleted file mode 100644
index c1e0926b13f..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/memory_buffer_alloc.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/**
- * \file memory_buffer_alloc.h
- *
- * \brief Buffer-based memory allocator
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_MEMORY_BUFFER_ALLOC_H
-#define MBEDTLS_MEMORY_BUFFER_ALLOC_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h or define them on the compiler command line.
- * \{
- */
-
-#if !defined(MBEDTLS_MEMORY_ALIGN_MULTIPLE)
-#define MBEDTLS_MEMORY_ALIGN_MULTIPLE       4 /**< Align on multiples of this value */
-#endif
-
-/* \} name SECTION: Module settings */
-
-#define MBEDTLS_MEMORY_VERIFY_NONE         0
-#define MBEDTLS_MEMORY_VERIFY_ALLOC        (1 << 0)
-#define MBEDTLS_MEMORY_VERIFY_FREE         (1 << 1)
-#define MBEDTLS_MEMORY_VERIFY_ALWAYS       (MBEDTLS_MEMORY_VERIFY_ALLOC | MBEDTLS_MEMORY_VERIFY_FREE)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief   Initialize use of stack-based memory allocator.
- *          The stack-based allocator does memory management inside the
- *          presented buffer and does not call calloc() and free().
- *          It sets the global mbedtls_calloc() and mbedtls_free() pointers
- *          to its own functions.
- *          (Provided mbedtls_calloc() and mbedtls_free() are thread-safe if
- *           MBEDTLS_THREADING_C is defined)
- *
- * \note    This code is not optimized and provides a straight-forward
- *          implementation of a stack-based memory allocator.
- *
- * \param buf   buffer to use as heap
- * \param len   size of the buffer
- */
-void mbedtls_memory_buffer_alloc_init( unsigned char *buf, size_t len );
-
-/**
- * \brief   Free the mutex for thread-safety and clear remaining memory
- */
-void mbedtls_memory_buffer_alloc_free( void );
-
-/**
- * \brief   Determine when the allocator should automatically verify the state
- *          of the entire chain of headers / meta-data.
- *          (Default: MBEDTLS_MEMORY_VERIFY_NONE)
- *
- * \param verify    One of MBEDTLS_MEMORY_VERIFY_NONE, MBEDTLS_MEMORY_VERIFY_ALLOC,
- *                  MBEDTLS_MEMORY_VERIFY_FREE or MBEDTLS_MEMORY_VERIFY_ALWAYS
- */
-void mbedtls_memory_buffer_set_verify( int verify );
-
-#if defined(MBEDTLS_MEMORY_DEBUG)
-/**
- * \brief   Print out the status of the allocated memory (primarily for use
- *          after a program should have de-allocated all memory)
- *          Prints out a list of 'still allocated' blocks and their stack
- *          trace if MBEDTLS_MEMORY_BACKTRACE is defined.
- */
-void mbedtls_memory_buffer_alloc_status( void );
-
-/**
- * \brief   Get the peak heap usage so far
- *
- * \param max_used      Peak number of bytes in use or committed. This
- *                      includes bytes in allocated blocks too small to split
- *                      into smaller blocks but larger than the requested size.
- * \param max_blocks    Peak number of blocks in use, including free and used
- */
-void mbedtls_memory_buffer_alloc_max_get( size_t *max_used, size_t *max_blocks );
-
-/**
- * \brief   Reset peak statistics
- */
-void mbedtls_memory_buffer_alloc_max_reset( void );
-
-/**
- * \brief   Get the current heap usage
- *
- * \param cur_used      Current number of bytes in use or committed. This
- *                      includes bytes in allocated blocks too small to split
- *                      into smaller blocks but larger than the requested size.
- * \param cur_blocks    Current number of blocks in use, including free and used
- */
-void mbedtls_memory_buffer_alloc_cur_get( size_t *cur_used, size_t *cur_blocks );
-#endif /* MBEDTLS_MEMORY_DEBUG */
-
-/**
- * \brief   Verifies that all headers in the memory buffer are correct
- *          and contain sane values. Helps debug buffer-overflow errors.
- *
- *          Prints out first failure if MBEDTLS_MEMORY_DEBUG is defined.
- *          Prints out full header information if MBEDTLS_MEMORY_DEBUG
- *          is defined. (Includes stack trace information for each block if
- *          MBEDTLS_MEMORY_BACKTRACE is defined as well).
- *
- * \return             0 if verified, 1 otherwise
- */
-int mbedtls_memory_buffer_alloc_verify( void );
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if a test failed
- */
-int mbedtls_memory_buffer_alloc_self_test( int verbose );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* memory_buffer_alloc.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/net.h b/tools/sdk/include/mbedtls/mbedtls/net.h
deleted file mode 100644
index bba4a359406..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/net.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**
- * \file net.h
- *
- * \brief Deprecated header file that includes net_sockets.h
- *
- * \deprecated Superseded by mbedtls/net_sockets.h
- */
-/*
- *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#include "net_sockets.h"
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#warning "Deprecated header file: Superseded by mbedtls/net_sockets.h"
-#endif /* MBEDTLS_DEPRECATED_WARNING */
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
diff --git a/tools/sdk/include/mbedtls/mbedtls/net_sockets.h b/tools/sdk/include/mbedtls/mbedtls/net_sockets.h
deleted file mode 100644
index d4d23fe9d89..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/net_sockets.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/**
- * \file net_sockets.h
- *
- * \brief   Network sockets abstraction layer to integrate Mbed TLS into a
- *          BSD-style sockets API.
- *
- *          The network sockets module provides an example integration of the
- *          Mbed TLS library into a BSD sockets implementation. The module is
- *          intended to be an example of how Mbed TLS can be integrated into a
- *          networking stack, as well as to be Mbed TLS's network integration
- *          for its supported platforms.
- *
- *          The module is intended only to be used with the Mbed TLS library and
- *          is not intended to be used by third party application software
- *          directly.
- *
- *          The supported platforms are as follows:
- *              * Microsoft Windows and Windows CE
- *              * POSIX/Unix platforms including Linux, OS X
- *
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_NET_SOCKETS_H
-#define MBEDTLS_NET_SOCKETS_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "ssl.h"
-
-#include <stddef.h>
-#include <stdint.h>
-
-#define MBEDTLS_ERR_NET_SOCKET_FAILED                     -0x0042  /**< Failed to open a socket. */
-#define MBEDTLS_ERR_NET_CONNECT_FAILED                    -0x0044  /**< The connection to the given server / port failed. */
-#define MBEDTLS_ERR_NET_BIND_FAILED                       -0x0046  /**< Binding of the socket failed. */
-#define MBEDTLS_ERR_NET_LISTEN_FAILED                     -0x0048  /**< Could not listen on the socket. */
-#define MBEDTLS_ERR_NET_ACCEPT_FAILED                     -0x004A  /**< Could not accept the incoming connection. */
-#define MBEDTLS_ERR_NET_RECV_FAILED                       -0x004C  /**< Reading information from the socket failed. */
-#define MBEDTLS_ERR_NET_SEND_FAILED                       -0x004E  /**< Sending information through the socket failed. */
-#define MBEDTLS_ERR_NET_CONN_RESET                        -0x0050  /**< Connection was reset by peer. */
-#define MBEDTLS_ERR_NET_UNKNOWN_HOST                      -0x0052  /**< Failed to get an IP address for the given hostname. */
-#define MBEDTLS_ERR_NET_BUFFER_TOO_SMALL                  -0x0043  /**< Buffer is too small to hold the data. */
-#define MBEDTLS_ERR_NET_INVALID_CONTEXT                   -0x0045  /**< The context is invalid, eg because it was free()ed. */
-#define MBEDTLS_ERR_NET_POLL_FAILED                       -0x0047  /**< Polling the net context failed. */
-#define MBEDTLS_ERR_NET_BAD_INPUT_DATA                    -0x0049  /**< Input invalid. */
-
-#define MBEDTLS_NET_LISTEN_BACKLOG         10 /**< The backlog that listen() should use. */
-
-#define MBEDTLS_NET_PROTO_TCP 0 /**< The TCP transport protocol */
-#define MBEDTLS_NET_PROTO_UDP 1 /**< The UDP transport protocol */
-
-#define MBEDTLS_NET_POLL_READ  1 /**< Used in \c mbedtls_net_poll to check for pending data  */
-#define MBEDTLS_NET_POLL_WRITE 2 /**< Used in \c mbedtls_net_poll to check if write possible */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Wrapper type for sockets.
- *
- * Currently backed by just a file descriptor, but might be more in the future
- * (eg two file descriptors for combined IPv4 + IPv6 support, or additional
- * structures for hand-made UDP demultiplexing).
- */
-typedef struct mbedtls_net_context
-{
-    int fd;             /**< The underlying file descriptor                 */
-}
-mbedtls_net_context;
-
-/**
- * \brief          Initialize a context
- *                 Just makes the context ready to be used or freed safely.
- *
- * \param ctx      Context to initialize
- */
-void mbedtls_net_init( mbedtls_net_context *ctx );
-
-/**
- * \brief          Initiate a connection with host:port in the given protocol
- *
- * \param ctx      Socket to use
- * \param host     Host to connect to
- * \param port     Port to connect to
- * \param proto    Protocol: MBEDTLS_NET_PROTO_TCP or MBEDTLS_NET_PROTO_UDP
- *
- * \return         0 if successful, or one of:
- *                      MBEDTLS_ERR_NET_SOCKET_FAILED,
- *                      MBEDTLS_ERR_NET_UNKNOWN_HOST,
- *                      MBEDTLS_ERR_NET_CONNECT_FAILED
- *
- * \note           Sets the socket in connected mode even with UDP.
- */
-int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char *port, int proto );
-
-/**
- * \brief          Create a receiving socket on bind_ip:port in the chosen
- *                 protocol. If bind_ip == NULL, all interfaces are bound.
- *
- * \param ctx      Socket to use
- * \param bind_ip  IP to bind to, can be NULL
- * \param port     Port number to use
- * \param proto    Protocol: MBEDTLS_NET_PROTO_TCP or MBEDTLS_NET_PROTO_UDP
- *
- * \return         0 if successful, or one of:
- *                      MBEDTLS_ERR_NET_SOCKET_FAILED,
- *                      MBEDTLS_ERR_NET_BIND_FAILED,
- *                      MBEDTLS_ERR_NET_LISTEN_FAILED
- *
- * \note           Regardless of the protocol, opens the sockets and binds it.
- *                 In addition, make the socket listening if protocol is TCP.
- */
-int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char *port, int proto );
-
-/**
- * \brief           Accept a connection from a remote client
- *
- * \param bind_ctx  Relevant socket
- * \param client_ctx Will contain the connected client socket
- * \param client_ip Will contain the client IP address, can be NULL
- * \param buf_size  Size of the client_ip buffer
- * \param ip_len    Will receive the size of the client IP written,
- *                  can be NULL if client_ip is null
- *
- * \return          0 if successful, or
- *                  MBEDTLS_ERR_NET_ACCEPT_FAILED, or
- *                  MBEDTLS_ERR_NET_BUFFER_TOO_SMALL if buf_size is too small,
- *                  MBEDTLS_ERR_SSL_WANT_READ if bind_fd was set to
- *                  non-blocking and accept() would block.
- */
-int mbedtls_net_accept( mbedtls_net_context *bind_ctx,
-                        mbedtls_net_context *client_ctx,
-                        void *client_ip, size_t buf_size, size_t *ip_len );
-
-/**
- * \brief          Check and wait for the context to be ready for read/write
- *
- * \param ctx      Socket to check
- * \param rw       Bitflag composed of MBEDTLS_NET_POLL_READ and
- *                 MBEDTLS_NET_POLL_WRITE specifying the events
- *                 to wait for:
- *                 - If MBEDTLS_NET_POLL_READ is set, the function
- *                   will return as soon as the net context is available
- *                   for reading.
- *                 - If MBEDTLS_NET_POLL_WRITE is set, the function
- *                   will return as soon as the net context is available
- *                   for writing.
- * \param timeout  Maximal amount of time to wait before returning,
- *                 in milliseconds. If \c timeout is zero, the
- *                 function returns immediately. If \c timeout is
- *                 -1u, the function blocks potentially indefinitely.
- *
- * \return         Bitmask composed of MBEDTLS_NET_POLL_READ/WRITE
- *                 on success or timeout, or a negative return code otherwise.
- */
-int mbedtls_net_poll( mbedtls_net_context *ctx, uint32_t rw, uint32_t timeout );
-
-/**
- * \brief          Set the socket blocking
- *
- * \param ctx      Socket to set
- *
- * \return         0 if successful, or a non-zero error code
- */
-int mbedtls_net_set_block( mbedtls_net_context *ctx );
-
-/**
- * \brief          Set the socket non-blocking
- *
- * \param ctx      Socket to set
- *
- * \return         0 if successful, or a non-zero error code
- */
-int mbedtls_net_set_nonblock( mbedtls_net_context *ctx );
-
-/**
- * \brief          Portable usleep helper
- *
- * \param usec     Amount of microseconds to sleep
- *
- * \note           Real amount of time slept will not be less than
- *                 select()'s timeout granularity (typically, 10ms).
- */
-void mbedtls_net_usleep( unsigned long usec );
-
-/**
- * \brief          Read at most 'len' characters. If no error occurs,
- *                 the actual amount read is returned.
- *
- * \param ctx      Socket
- * \param buf      The buffer to write to
- * \param len      Maximum length of the buffer
- *
- * \return         the number of bytes received,
- *                 or a non-zero error code; with a non-blocking socket,
- *                 MBEDTLS_ERR_SSL_WANT_READ indicates read() would block.
- */
-int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len );
-
-/**
- * \brief          Write at most 'len' characters. If no error occurs,
- *                 the actual amount read is returned.
- *
- * \param ctx      Socket
- * \param buf      The buffer to read from
- * \param len      The length of the buffer
- *
- * \return         the number of bytes sent,
- *                 or a non-zero error code; with a non-blocking socket,
- *                 MBEDTLS_ERR_SSL_WANT_WRITE indicates write() would block.
- */
-int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len );
-
-/**
- * \brief          Read at most 'len' characters, blocking for at most
- *                 'timeout' seconds. If no error occurs, the actual amount
- *                 read is returned.
- *
- * \param ctx      Socket
- * \param buf      The buffer to write to
- * \param len      Maximum length of the buffer
- * \param timeout  Maximum number of milliseconds to wait for data
- *                 0 means no timeout (wait forever)
- *
- * \return         the number of bytes received,
- *                 or a non-zero error code:
- *                 MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out,
- *                 MBEDTLS_ERR_SSL_WANT_READ if interrupted by a signal.
- *
- * \note           This function will block (until data becomes available or
- *                 timeout is reached) even if the socket is set to
- *                 non-blocking. Handling timeouts with non-blocking reads
- *                 requires a different strategy.
- */
-int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len,
-                      uint32_t timeout );
-
-/**
- * \brief          Gracefully shutdown the connection and free associated data
- *
- * \param ctx      The context to free
- */
-void mbedtls_net_free( mbedtls_net_context *ctx );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* net_sockets.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/nist_kw.h b/tools/sdk/include/mbedtls/mbedtls/nist_kw.h
deleted file mode 100644
index f2b9cebf9ca..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/nist_kw.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/**
- * \file nist_kw.h
- *
- * \brief This file provides an API for key wrapping (KW) and key wrapping with
- *        padding (KWP) as defined in NIST SP 800-38F.
- *        https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-38F.pdf
- *
- *        Key wrapping specifies a deterministic authenticated-encryption mode
- *        of operation, according to <em>NIST SP 800-38F: Recommendation for
- *        Block Cipher Modes of Operation: Methods for Key Wrapping</em>. Its
- *        purpose is to protect cryptographic keys.
- *
- *        Its equivalent is RFC 3394 for KW, and RFC 5649 for KWP.
- *        https://tools.ietf.org/html/rfc3394
- *        https://tools.ietf.org/html/rfc5649
- *
- */
-/*
- *  Copyright (C) 2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_NIST_KW_H
-#define MBEDTLS_NIST_KW_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "cipher.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum
-{
-    MBEDTLS_KW_MODE_KW = 0,
-    MBEDTLS_KW_MODE_KWP = 1
-} mbedtls_nist_kw_mode_t;
-
-#if !defined(MBEDTLS_NIST_KW_ALT)
-// Regular implementation
-//
-
-/**
- * \brief    The key wrapping context-type definition. The key wrapping context is passed
- *           to the APIs called.
- *
- * \note     The definition of this type may change in future library versions.
- *           Don't make any assumptions on this context!
- */
-typedef struct {
-    mbedtls_cipher_context_t cipher_ctx;    /*!< The cipher context used. */
-} mbedtls_nist_kw_context;
-
-#else  /* MBEDTLS_NIST_key wrapping_ALT */
-#include "nist_kw_alt.h"
-#endif /* MBEDTLS_NIST_KW_ALT */
-
-/**
- * \brief           This function initializes the specified key wrapping context
- *                  to make references valid and prepare the context
- *                  for mbedtls_nist_kw_setkey() or mbedtls_nist_kw_free().
- *
- * \param ctx       The key wrapping context to initialize.
- *
- */
-void mbedtls_nist_kw_init( mbedtls_nist_kw_context *ctx );
-
-/**
- * \brief           This function initializes the key wrapping context set in the
- *                  \p ctx parameter and sets the encryption key.
- *
- * \param ctx       The key wrapping context.
- * \param cipher    The 128-bit block cipher to use. Only AES is supported.
- * \param key       The Key Encryption Key (KEK).
- * \param keybits   The KEK size in bits. This must be acceptable by the cipher.
- * \param is_wrap   Specify whether the operation within the context is wrapping or unwrapping
- *
- * \return          \c 0 on success.
- * \return          \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for any invalid input.
- * \return          \c MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE for 128-bit block ciphers
- *                  which are not supported.
- * \return          cipher-specific error code on failure of the underlying cipher.
- */
-int mbedtls_nist_kw_setkey( mbedtls_nist_kw_context *ctx,
-                            mbedtls_cipher_id_t cipher,
-                            const unsigned char *key,
-                            unsigned int keybits,
-                            const int is_wrap );
-
-/**
- * \brief   This function releases and clears the specified key wrapping context
- *          and underlying cipher sub-context.
- *
- * \param ctx       The key wrapping context to clear.
- */
-void mbedtls_nist_kw_free( mbedtls_nist_kw_context *ctx );
-
-/**
- * \brief           This function encrypts a buffer using key wrapping.
- *
- * \param ctx       The key wrapping context to use for encryption.
- * \param mode      The key wrapping mode to use (MBEDTLS_KW_MODE_KW or MBEDTLS_KW_MODE_KWP)
- * \param input     The buffer holding the input data.
- * \param in_len    The length of the input data in Bytes.
- *                  The input uses units of 8 Bytes called semiblocks.
- *                  <ul><li>For KW mode: a multiple of 8 bytes between 16 and 2^57-8 inclusive. </li>
- *                  <li>For KWP mode: any length between 1 and 2^32-1 inclusive.</li></ul>
- * \param[out] output    The buffer holding the output data.
- *                  <ul><li>For KW mode: Must be at least 8 bytes larger than \p in_len.</li>
- *                  <li>For KWP mode: Must be at least 8 bytes larger rounded up to a multiple of
- *                  8 bytes for KWP (15 bytes at most).</li></ul>
- * \param[out] out_len The number of bytes written to the output buffer. \c 0 on failure.
- * \param[in] out_size The capacity of the output buffer.
- *
- * \return          \c 0 on success.
- * \return          \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for invalid input length.
- * \return          cipher-specific error code on failure of the underlying cipher.
- */
-int mbedtls_nist_kw_wrap( mbedtls_nist_kw_context *ctx, mbedtls_nist_kw_mode_t mode,
-                          const unsigned char *input, size_t in_len,
-                          unsigned char *output, size_t* out_len, size_t out_size );
-
-/**
- * \brief           This function decrypts a buffer using key wrapping.
- *
- * \param ctx       The key wrapping context to use for decryption.
- * \param mode      The key wrapping mode to use (MBEDTLS_KW_MODE_KW or MBEDTLS_KW_MODE_KWP)
- * \param input     The buffer holding the input data.
- * \param in_len    The length of the input data in Bytes.
- *                  The input uses units of 8 Bytes called semiblocks.
- *                  The input must be a multiple of semiblocks.
- *                  <ul><li>For KW mode: a multiple of 8 bytes between 24 and 2^57 inclusive. </li>
- *                  <li>For KWP mode: a multiple of 8 bytes between 16 and 2^32 inclusive.</li></ul>
- * \param[out] output    The buffer holding the output data.
- *                  The output buffer's minimal length is 8 bytes shorter than \p in_len.
- * \param[out] out_len The number of bytes written to the output buffer. \c 0 on failure.
- *                  For KWP mode, the length could be up to 15 bytes shorter than \p in_len,
- *                  depending on how much padding was added to the data.
- * \param[in] out_size The capacity of the output buffer.
- *
- * \return          \c 0 on success.
- * \return          \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for invalid input length.
- * \return          \c MBEDTLS_ERR_CIPHER_AUTH_FAILED for verification failure of the ciphertext.
- * \return          cipher-specific error code on failure of the underlying cipher.
- */
-int mbedtls_nist_kw_unwrap( mbedtls_nist_kw_context *ctx, mbedtls_nist_kw_mode_t mode,
-                            const unsigned char *input, size_t in_len,
-                            unsigned char *output, size_t* out_len, size_t out_size);
-
-
-#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C)
-/**
- * \brief          The key wrapping checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_nist_kw_self_test( int verbose );
-#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_NIST_KW_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/oid.h b/tools/sdk/include/mbedtls/mbedtls/oid.h
deleted file mode 100644
index 7fe4b386215..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/oid.h
+++ /dev/null
@@ -1,632 +0,0 @@
-/**
- * \file oid.h
- *
- * \brief Object Identifier (OID) database
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_OID_H
-#define MBEDTLS_OID_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "asn1.h"
-#include "pk.h"
-
-#include <stddef.h>
-
-#if defined(MBEDTLS_CIPHER_C)
-#include "cipher.h"
-#endif
-
-#if defined(MBEDTLS_MD_C)
-#include "md.h"
-#endif
-
-#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C)
-#include "x509.h"
-#endif
-
-#define MBEDTLS_ERR_OID_NOT_FOUND                         -0x002E  /**< OID is not found. */
-#define MBEDTLS_ERR_OID_BUF_TOO_SMALL                     -0x000B  /**< output buffer is too small */
-
-/*
- * Top level OID tuples
- */
-#define MBEDTLS_OID_ISO_MEMBER_BODIES           "\x2a"          /* {iso(1) member-body(2)} */
-#define MBEDTLS_OID_ISO_IDENTIFIED_ORG          "\x2b"          /* {iso(1) identified-organization(3)} */
-#define MBEDTLS_OID_ISO_CCITT_DS                "\x55"          /* {joint-iso-ccitt(2) ds(5)} */
-#define MBEDTLS_OID_ISO_ITU_COUNTRY             "\x60"          /* {joint-iso-itu-t(2) country(16)} */
-
-/*
- * ISO Member bodies OID parts
- */
-#define MBEDTLS_OID_COUNTRY_US                  "\x86\x48"      /* {us(840)} */
-#define MBEDTLS_OID_ORG_RSA_DATA_SECURITY       "\x86\xf7\x0d"  /* {rsadsi(113549)} */
-#define MBEDTLS_OID_RSA_COMPANY                 MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \
-                                        MBEDTLS_OID_ORG_RSA_DATA_SECURITY /* {iso(1) member-body(2) us(840) rsadsi(113549)} */
-#define MBEDTLS_OID_ORG_ANSI_X9_62              "\xce\x3d" /* ansi-X9-62(10045) */
-#define MBEDTLS_OID_ANSI_X9_62                  MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \
-                                        MBEDTLS_OID_ORG_ANSI_X9_62
-
-/*
- * ISO Identified organization OID parts
- */
-#define MBEDTLS_OID_ORG_DOD                     "\x06"          /* {dod(6)} */
-#define MBEDTLS_OID_ORG_OIW                     "\x0e"
-#define MBEDTLS_OID_OIW_SECSIG                  MBEDTLS_OID_ORG_OIW "\x03"
-#define MBEDTLS_OID_OIW_SECSIG_ALG              MBEDTLS_OID_OIW_SECSIG "\x02"
-#define MBEDTLS_OID_OIW_SECSIG_SHA1             MBEDTLS_OID_OIW_SECSIG_ALG "\x1a"
-#define MBEDTLS_OID_ORG_CERTICOM                "\x81\x04"  /* certicom(132) */
-#define MBEDTLS_OID_CERTICOM                    MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_CERTICOM
-#define MBEDTLS_OID_ORG_TELETRUST               "\x24" /* teletrust(36) */
-#define MBEDTLS_OID_TELETRUST                   MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_TELETRUST
-
-/*
- * ISO ITU OID parts
- */
-#define MBEDTLS_OID_ORGANIZATION                "\x01"          /* {organization(1)} */
-#define MBEDTLS_OID_ISO_ITU_US_ORG              MBEDTLS_OID_ISO_ITU_COUNTRY MBEDTLS_OID_COUNTRY_US MBEDTLS_OID_ORGANIZATION /* {joint-iso-itu-t(2) country(16) us(840) organization(1)} */
-
-#define MBEDTLS_OID_ORG_GOV                     "\x65"          /* {gov(101)} */
-#define MBEDTLS_OID_GOV                         MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_GOV /* {joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101)} */
-
-#define MBEDTLS_OID_ORG_NETSCAPE                "\x86\xF8\x42"  /* {netscape(113730)} */
-#define MBEDTLS_OID_NETSCAPE                    MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_NETSCAPE /* Netscape OID {joint-iso-itu-t(2) country(16) us(840) organization(1) netscape(113730)} */
-
-/* ISO arc for standard certificate and CRL extensions */
-#define MBEDTLS_OID_ID_CE                       MBEDTLS_OID_ISO_CCITT_DS "\x1D" /**< id-ce OBJECT IDENTIFIER  ::=  {joint-iso-ccitt(2) ds(5) 29} */
-
-#define MBEDTLS_OID_NIST_ALG                    MBEDTLS_OID_GOV "\x03\x04" /** { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithm(4) */
-
-/**
- * Private Internet Extensions
- * { iso(1) identified-organization(3) dod(6) internet(1)
- *                      security(5) mechanisms(5) pkix(7) }
- */
-#define MBEDTLS_OID_PKIX                        MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_DOD "\x01\x05\x05\x07"
-
-/*
- * Arc for standard naming attributes
- */
-#define MBEDTLS_OID_AT                          MBEDTLS_OID_ISO_CCITT_DS "\x04" /**< id-at OBJECT IDENTIFIER ::= {joint-iso-ccitt(2) ds(5) 4} */
-#define MBEDTLS_OID_AT_CN                       MBEDTLS_OID_AT "\x03" /**< id-at-commonName AttributeType:= {id-at 3} */
-#define MBEDTLS_OID_AT_SUR_NAME                 MBEDTLS_OID_AT "\x04" /**< id-at-surName AttributeType:= {id-at 4} */
-#define MBEDTLS_OID_AT_SERIAL_NUMBER            MBEDTLS_OID_AT "\x05" /**< id-at-serialNumber AttributeType:= {id-at 5} */
-#define MBEDTLS_OID_AT_COUNTRY                  MBEDTLS_OID_AT "\x06" /**< id-at-countryName AttributeType:= {id-at 6} */
-#define MBEDTLS_OID_AT_LOCALITY                 MBEDTLS_OID_AT "\x07" /**< id-at-locality AttributeType:= {id-at 7} */
-#define MBEDTLS_OID_AT_STATE                    MBEDTLS_OID_AT "\x08" /**< id-at-state AttributeType:= {id-at 8} */
-#define MBEDTLS_OID_AT_ORGANIZATION             MBEDTLS_OID_AT "\x0A" /**< id-at-organizationName AttributeType:= {id-at 10} */
-#define MBEDTLS_OID_AT_ORG_UNIT                 MBEDTLS_OID_AT "\x0B" /**< id-at-organizationalUnitName AttributeType:= {id-at 11} */
-#define MBEDTLS_OID_AT_TITLE                    MBEDTLS_OID_AT "\x0C" /**< id-at-title AttributeType:= {id-at 12} */
-#define MBEDTLS_OID_AT_POSTAL_ADDRESS           MBEDTLS_OID_AT "\x10" /**< id-at-postalAddress AttributeType:= {id-at 16} */
-#define MBEDTLS_OID_AT_POSTAL_CODE              MBEDTLS_OID_AT "\x11" /**< id-at-postalCode AttributeType:= {id-at 17} */
-#define MBEDTLS_OID_AT_GIVEN_NAME               MBEDTLS_OID_AT "\x2A" /**< id-at-givenName AttributeType:= {id-at 42} */
-#define MBEDTLS_OID_AT_INITIALS                 MBEDTLS_OID_AT "\x2B" /**< id-at-initials AttributeType:= {id-at 43} */
-#define MBEDTLS_OID_AT_GENERATION_QUALIFIER     MBEDTLS_OID_AT "\x2C" /**< id-at-generationQualifier AttributeType:= {id-at 44} */
-#define MBEDTLS_OID_AT_UNIQUE_IDENTIFIER        MBEDTLS_OID_AT "\x2D" /**< id-at-uniqueIdentifier AttributType:= {id-at 45} */
-#define MBEDTLS_OID_AT_DN_QUALIFIER             MBEDTLS_OID_AT "\x2E" /**< id-at-dnQualifier AttributeType:= {id-at 46} */
-#define MBEDTLS_OID_AT_PSEUDONYM                MBEDTLS_OID_AT "\x41" /**< id-at-pseudonym AttributeType:= {id-at 65} */
-
-#define MBEDTLS_OID_DOMAIN_COMPONENT            "\x09\x92\x26\x89\x93\xF2\x2C\x64\x01\x19" /** id-domainComponent AttributeType:= {itu-t(0) data(9) pss(2342) ucl(19200300) pilot(100) pilotAttributeType(1) domainComponent(25)} */
-
-/*
- * OIDs for standard certificate extensions
- */
-#define MBEDTLS_OID_AUTHORITY_KEY_IDENTIFIER    MBEDTLS_OID_ID_CE "\x23" /**< id-ce-authorityKeyIdentifier OBJECT IDENTIFIER ::=  { id-ce 35 } */
-#define MBEDTLS_OID_SUBJECT_KEY_IDENTIFIER      MBEDTLS_OID_ID_CE "\x0E" /**< id-ce-subjectKeyIdentifier OBJECT IDENTIFIER ::=  { id-ce 14 } */
-#define MBEDTLS_OID_KEY_USAGE                   MBEDTLS_OID_ID_CE "\x0F" /**< id-ce-keyUsage OBJECT IDENTIFIER ::=  { id-ce 15 } */
-#define MBEDTLS_OID_CERTIFICATE_POLICIES        MBEDTLS_OID_ID_CE "\x20" /**< id-ce-certificatePolicies OBJECT IDENTIFIER ::=  { id-ce 32 } */
-#define MBEDTLS_OID_POLICY_MAPPINGS             MBEDTLS_OID_ID_CE "\x21" /**< id-ce-policyMappings OBJECT IDENTIFIER ::=  { id-ce 33 } */
-#define MBEDTLS_OID_SUBJECT_ALT_NAME            MBEDTLS_OID_ID_CE "\x11" /**< id-ce-subjectAltName OBJECT IDENTIFIER ::=  { id-ce 17 } */
-#define MBEDTLS_OID_ISSUER_ALT_NAME             MBEDTLS_OID_ID_CE "\x12" /**< id-ce-issuerAltName OBJECT IDENTIFIER ::=  { id-ce 18 } */
-#define MBEDTLS_OID_SUBJECT_DIRECTORY_ATTRS     MBEDTLS_OID_ID_CE "\x09" /**< id-ce-subjectDirectoryAttributes OBJECT IDENTIFIER ::=  { id-ce 9 } */
-#define MBEDTLS_OID_BASIC_CONSTRAINTS           MBEDTLS_OID_ID_CE "\x13" /**< id-ce-basicConstraints OBJECT IDENTIFIER ::=  { id-ce 19 } */
-#define MBEDTLS_OID_NAME_CONSTRAINTS            MBEDTLS_OID_ID_CE "\x1E" /**< id-ce-nameConstraints OBJECT IDENTIFIER ::=  { id-ce 30 } */
-#define MBEDTLS_OID_POLICY_CONSTRAINTS          MBEDTLS_OID_ID_CE "\x24" /**< id-ce-policyConstraints OBJECT IDENTIFIER ::=  { id-ce 36 } */
-#define MBEDTLS_OID_EXTENDED_KEY_USAGE          MBEDTLS_OID_ID_CE "\x25" /**< id-ce-extKeyUsage OBJECT IDENTIFIER ::= { id-ce 37 } */
-#define MBEDTLS_OID_CRL_DISTRIBUTION_POINTS     MBEDTLS_OID_ID_CE "\x1F" /**< id-ce-cRLDistributionPoints OBJECT IDENTIFIER ::=  { id-ce 31 } */
-#define MBEDTLS_OID_INIHIBIT_ANYPOLICY          MBEDTLS_OID_ID_CE "\x36" /**< id-ce-inhibitAnyPolicy OBJECT IDENTIFIER ::=  { id-ce 54 } */
-#define MBEDTLS_OID_FRESHEST_CRL                MBEDTLS_OID_ID_CE "\x2E" /**< id-ce-freshestCRL OBJECT IDENTIFIER ::=  { id-ce 46 } */
-
-/*
- * Netscape certificate extensions
- */
-#define MBEDTLS_OID_NS_CERT                 MBEDTLS_OID_NETSCAPE "\x01"
-#define MBEDTLS_OID_NS_CERT_TYPE            MBEDTLS_OID_NS_CERT  "\x01"
-#define MBEDTLS_OID_NS_BASE_URL             MBEDTLS_OID_NS_CERT  "\x02"
-#define MBEDTLS_OID_NS_REVOCATION_URL       MBEDTLS_OID_NS_CERT  "\x03"
-#define MBEDTLS_OID_NS_CA_REVOCATION_URL    MBEDTLS_OID_NS_CERT  "\x04"
-#define MBEDTLS_OID_NS_RENEWAL_URL          MBEDTLS_OID_NS_CERT  "\x07"
-#define MBEDTLS_OID_NS_CA_POLICY_URL        MBEDTLS_OID_NS_CERT  "\x08"
-#define MBEDTLS_OID_NS_SSL_SERVER_NAME      MBEDTLS_OID_NS_CERT  "\x0C"
-#define MBEDTLS_OID_NS_COMMENT              MBEDTLS_OID_NS_CERT  "\x0D"
-#define MBEDTLS_OID_NS_DATA_TYPE            MBEDTLS_OID_NETSCAPE "\x02"
-#define MBEDTLS_OID_NS_CERT_SEQUENCE        MBEDTLS_OID_NS_DATA_TYPE "\x05"
-
-/*
- * OIDs for CRL extensions
- */
-#define MBEDTLS_OID_PRIVATE_KEY_USAGE_PERIOD    MBEDTLS_OID_ID_CE "\x10"
-#define MBEDTLS_OID_CRL_NUMBER                  MBEDTLS_OID_ID_CE "\x14" /**< id-ce-cRLNumber OBJECT IDENTIFIER ::= { id-ce 20 } */
-
-/*
- * X.509 v3 Extended key usage OIDs
- */
-#define MBEDTLS_OID_ANY_EXTENDED_KEY_USAGE      MBEDTLS_OID_EXTENDED_KEY_USAGE "\x00" /**< anyExtendedKeyUsage OBJECT IDENTIFIER ::= { id-ce-extKeyUsage 0 } */
-
-#define MBEDTLS_OID_KP                          MBEDTLS_OID_PKIX "\x03" /**< id-kp OBJECT IDENTIFIER ::= { id-pkix 3 } */
-#define MBEDTLS_OID_SERVER_AUTH                 MBEDTLS_OID_KP "\x01" /**< id-kp-serverAuth OBJECT IDENTIFIER ::= { id-kp 1 } */
-#define MBEDTLS_OID_CLIENT_AUTH                 MBEDTLS_OID_KP "\x02" /**< id-kp-clientAuth OBJECT IDENTIFIER ::= { id-kp 2 } */
-#define MBEDTLS_OID_CODE_SIGNING                MBEDTLS_OID_KP "\x03" /**< id-kp-codeSigning OBJECT IDENTIFIER ::= { id-kp 3 } */
-#define MBEDTLS_OID_EMAIL_PROTECTION            MBEDTLS_OID_KP "\x04" /**< id-kp-emailProtection OBJECT IDENTIFIER ::= { id-kp 4 } */
-#define MBEDTLS_OID_TIME_STAMPING               MBEDTLS_OID_KP "\x08" /**< id-kp-timeStamping OBJECT IDENTIFIER ::= { id-kp 8 } */
-#define MBEDTLS_OID_OCSP_SIGNING                MBEDTLS_OID_KP "\x09" /**< id-kp-OCSPSigning OBJECT IDENTIFIER ::= { id-kp 9 } */
-
-/*
- * PKCS definition OIDs
- */
-
-#define MBEDTLS_OID_PKCS                MBEDTLS_OID_RSA_COMPANY "\x01" /**< pkcs OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) 1 } */
-#define MBEDTLS_OID_PKCS1               MBEDTLS_OID_PKCS "\x01" /**< pkcs-1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 1 } */
-#define MBEDTLS_OID_PKCS5               MBEDTLS_OID_PKCS "\x05" /**< pkcs-5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 5 } */
-#define MBEDTLS_OID_PKCS9               MBEDTLS_OID_PKCS "\x09" /**< pkcs-9 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 9 } */
-#define MBEDTLS_OID_PKCS12              MBEDTLS_OID_PKCS "\x0c" /**< pkcs-12 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 12 } */
-
-/*
- * PKCS#1 OIDs
- */
-#define MBEDTLS_OID_PKCS1_RSA           MBEDTLS_OID_PKCS1 "\x01" /**< rsaEncryption OBJECT IDENTIFIER ::= { pkcs-1 1 } */
-#define MBEDTLS_OID_PKCS1_MD2           MBEDTLS_OID_PKCS1 "\x02" /**< md2WithRSAEncryption ::= { pkcs-1 2 } */
-#define MBEDTLS_OID_PKCS1_MD4           MBEDTLS_OID_PKCS1 "\x03" /**< md4WithRSAEncryption ::= { pkcs-1 3 } */
-#define MBEDTLS_OID_PKCS1_MD5           MBEDTLS_OID_PKCS1 "\x04" /**< md5WithRSAEncryption ::= { pkcs-1 4 } */
-#define MBEDTLS_OID_PKCS1_SHA1          MBEDTLS_OID_PKCS1 "\x05" /**< sha1WithRSAEncryption ::= { pkcs-1 5 } */
-#define MBEDTLS_OID_PKCS1_SHA224        MBEDTLS_OID_PKCS1 "\x0e" /**< sha224WithRSAEncryption ::= { pkcs-1 14 } */
-#define MBEDTLS_OID_PKCS1_SHA256        MBEDTLS_OID_PKCS1 "\x0b" /**< sha256WithRSAEncryption ::= { pkcs-1 11 } */
-#define MBEDTLS_OID_PKCS1_SHA384        MBEDTLS_OID_PKCS1 "\x0c" /**< sha384WithRSAEncryption ::= { pkcs-1 12 } */
-#define MBEDTLS_OID_PKCS1_SHA512        MBEDTLS_OID_PKCS1 "\x0d" /**< sha512WithRSAEncryption ::= { pkcs-1 13 } */
-
-#define MBEDTLS_OID_RSA_SHA_OBS         "\x2B\x0E\x03\x02\x1D"
-
-#define MBEDTLS_OID_PKCS9_EMAIL         MBEDTLS_OID_PKCS9 "\x01" /**< emailAddress AttributeType ::= { pkcs-9 1 } */
-
-/* RFC 4055 */
-#define MBEDTLS_OID_RSASSA_PSS          MBEDTLS_OID_PKCS1 "\x0a" /**< id-RSASSA-PSS ::= { pkcs-1 10 } */
-#define MBEDTLS_OID_MGF1                MBEDTLS_OID_PKCS1 "\x08" /**< id-mgf1 ::= { pkcs-1 8 } */
-
-/*
- * Digest algorithms
- */
-#define MBEDTLS_OID_DIGEST_ALG_MD2              MBEDTLS_OID_RSA_COMPANY "\x02\x02" /**< id-mbedtls_md2 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 2 } */
-#define MBEDTLS_OID_DIGEST_ALG_MD4              MBEDTLS_OID_RSA_COMPANY "\x02\x04" /**< id-mbedtls_md4 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 4 } */
-#define MBEDTLS_OID_DIGEST_ALG_MD5              MBEDTLS_OID_RSA_COMPANY "\x02\x05" /**< id-mbedtls_md5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 5 } */
-#define MBEDTLS_OID_DIGEST_ALG_SHA1             MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_OIW_SECSIG_SHA1 /**< id-mbedtls_sha1 OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 26 } */
-#define MBEDTLS_OID_DIGEST_ALG_SHA224           MBEDTLS_OID_NIST_ALG "\x02\x04" /**< id-sha224 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 4 } */
-#define MBEDTLS_OID_DIGEST_ALG_SHA256           MBEDTLS_OID_NIST_ALG "\x02\x01" /**< id-mbedtls_sha256 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 1 } */
-
-#define MBEDTLS_OID_DIGEST_ALG_SHA384           MBEDTLS_OID_NIST_ALG "\x02\x02" /**< id-sha384 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 2 } */
-
-#define MBEDTLS_OID_DIGEST_ALG_SHA512           MBEDTLS_OID_NIST_ALG "\x02\x03" /**< id-mbedtls_sha512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 3 } */
-
-#define MBEDTLS_OID_HMAC_SHA1                   MBEDTLS_OID_RSA_COMPANY "\x02\x07" /**< id-hmacWithSHA1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 7 } */
-
-#define MBEDTLS_OID_HMAC_SHA224                 MBEDTLS_OID_RSA_COMPANY "\x02\x08" /**< id-hmacWithSHA224 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 8 } */
-
-#define MBEDTLS_OID_HMAC_SHA256                 MBEDTLS_OID_RSA_COMPANY "\x02\x09" /**< id-hmacWithSHA256 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 9 } */
-
-#define MBEDTLS_OID_HMAC_SHA384                 MBEDTLS_OID_RSA_COMPANY "\x02\x0A" /**< id-hmacWithSHA384 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 10 } */
-
-#define MBEDTLS_OID_HMAC_SHA512                 MBEDTLS_OID_RSA_COMPANY "\x02\x0B" /**< id-hmacWithSHA512 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 11 } */
-
-/*
- * Encryption algorithms
- */
-#define MBEDTLS_OID_DES_CBC                     MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_OIW_SECSIG_ALG "\x07" /**< desCBC OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 7 } */
-#define MBEDTLS_OID_DES_EDE3_CBC                MBEDTLS_OID_RSA_COMPANY "\x03\x07" /**< des-ede3-cbc OBJECT IDENTIFIER ::= { iso(1) member-body(2) -- us(840) rsadsi(113549) encryptionAlgorithm(3) 7 } */
-#define MBEDTLS_OID_AES                         MBEDTLS_OID_NIST_ALG "\x01" /** aes OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithm(4) 1 } */
-
-/*
- * Key Wrapping algorithms
- */
-/*
- * RFC 5649
- */
-#define MBEDTLS_OID_AES128_KW                   MBEDTLS_OID_AES "\x05" /** id-aes128-wrap     OBJECT IDENTIFIER ::= { aes 5 } */
-#define MBEDTLS_OID_AES128_KWP                  MBEDTLS_OID_AES "\x08" /** id-aes128-wrap-pad OBJECT IDENTIFIER ::= { aes 8 } */
-#define MBEDTLS_OID_AES192_KW                   MBEDTLS_OID_AES "\x19" /** id-aes192-wrap     OBJECT IDENTIFIER ::= { aes 25 } */
-#define MBEDTLS_OID_AES192_KWP                  MBEDTLS_OID_AES "\x1c" /** id-aes192-wrap-pad OBJECT IDENTIFIER ::= { aes 28 } */
-#define MBEDTLS_OID_AES256_KW                   MBEDTLS_OID_AES "\x2d" /** id-aes256-wrap     OBJECT IDENTIFIER ::= { aes 45 } */
-#define MBEDTLS_OID_AES256_KWP                  MBEDTLS_OID_AES "\x30" /** id-aes256-wrap-pad OBJECT IDENTIFIER ::= { aes 48 } */
-/*
- * PKCS#5 OIDs
- */
-#define MBEDTLS_OID_PKCS5_PBKDF2                MBEDTLS_OID_PKCS5 "\x0c" /**< id-PBKDF2 OBJECT IDENTIFIER ::= {pkcs-5 12} */
-#define MBEDTLS_OID_PKCS5_PBES2                 MBEDTLS_OID_PKCS5 "\x0d" /**< id-PBES2 OBJECT IDENTIFIER ::= {pkcs-5 13} */
-#define MBEDTLS_OID_PKCS5_PBMAC1                MBEDTLS_OID_PKCS5 "\x0e" /**< id-PBMAC1 OBJECT IDENTIFIER ::= {pkcs-5 14} */
-
-/*
- * PKCS#5 PBES1 algorithms
- */
-#define MBEDTLS_OID_PKCS5_PBE_MD2_DES_CBC       MBEDTLS_OID_PKCS5 "\x01" /**< pbeWithMD2AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 1} */
-#define MBEDTLS_OID_PKCS5_PBE_MD2_RC2_CBC       MBEDTLS_OID_PKCS5 "\x04" /**< pbeWithMD2AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 4} */
-#define MBEDTLS_OID_PKCS5_PBE_MD5_DES_CBC       MBEDTLS_OID_PKCS5 "\x03" /**< pbeWithMD5AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 3} */
-#define MBEDTLS_OID_PKCS5_PBE_MD5_RC2_CBC       MBEDTLS_OID_PKCS5 "\x06" /**< pbeWithMD5AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 6} */
-#define MBEDTLS_OID_PKCS5_PBE_SHA1_DES_CBC      MBEDTLS_OID_PKCS5 "\x0a" /**< pbeWithSHA1AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 10} */
-#define MBEDTLS_OID_PKCS5_PBE_SHA1_RC2_CBC      MBEDTLS_OID_PKCS5 "\x0b" /**< pbeWithSHA1AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 11} */
-
-/*
- * PKCS#8 OIDs
- */
-#define MBEDTLS_OID_PKCS9_CSR_EXT_REQ           MBEDTLS_OID_PKCS9 "\x0e" /**< extensionRequest OBJECT IDENTIFIER ::= {pkcs-9 14} */
-
-/*
- * PKCS#12 PBE OIDs
- */
-#define MBEDTLS_OID_PKCS12_PBE                      MBEDTLS_OID_PKCS12 "\x01" /**< pkcs-12PbeIds OBJECT IDENTIFIER ::= {pkcs-12 1} */
-
-#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_128         MBEDTLS_OID_PKCS12_PBE "\x01" /**< pbeWithSHAAnd128BitRC4 OBJECT IDENTIFIER ::= {pkcs-12PbeIds 1} */
-#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC4_40          MBEDTLS_OID_PKCS12_PBE "\x02" /**< pbeWithSHAAnd40BitRC4 OBJECT IDENTIFIER ::= {pkcs-12PbeIds 2} */
-#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES3_EDE_CBC    MBEDTLS_OID_PKCS12_PBE "\x03" /**< pbeWithSHAAnd3-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 3} */
-#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES2_EDE_CBC    MBEDTLS_OID_PKCS12_PBE "\x04" /**< pbeWithSHAAnd2-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 4} */
-#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_128_CBC     MBEDTLS_OID_PKCS12_PBE "\x05" /**< pbeWithSHAAnd128BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 5} */
-#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_40_CBC      MBEDTLS_OID_PKCS12_PBE "\x06" /**< pbeWithSHAAnd40BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 6} */
-
-/*
- * EC key algorithms from RFC 5480
- */
-
-/* id-ecPublicKey OBJECT IDENTIFIER ::= {
- *       iso(1) member-body(2) us(840) ansi-X9-62(10045) keyType(2) 1 } */
-#define MBEDTLS_OID_EC_ALG_UNRESTRICTED         MBEDTLS_OID_ANSI_X9_62 "\x02\01"
-
-/*   id-ecDH OBJECT IDENTIFIER ::= {
- *     iso(1) identified-organization(3) certicom(132)
- *     schemes(1) ecdh(12) } */
-#define MBEDTLS_OID_EC_ALG_ECDH                 MBEDTLS_OID_CERTICOM "\x01\x0c"
-
-/*
- * ECParameters namedCurve identifiers, from RFC 5480, RFC 5639, and SEC2
- */
-
-/* secp192r1 OBJECT IDENTIFIER ::= {
- *   iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 1 } */
-#define MBEDTLS_OID_EC_GRP_SECP192R1        MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x01"
-
-/* secp224r1 OBJECT IDENTIFIER ::= {
- *   iso(1) identified-organization(3) certicom(132) curve(0) 33 } */
-#define MBEDTLS_OID_EC_GRP_SECP224R1        MBEDTLS_OID_CERTICOM "\x00\x21"
-
-/* secp256r1 OBJECT IDENTIFIER ::= {
- *   iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 7 } */
-#define MBEDTLS_OID_EC_GRP_SECP256R1        MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x07"
-
-/* secp384r1 OBJECT IDENTIFIER ::= {
- *   iso(1) identified-organization(3) certicom(132) curve(0) 34 } */
-#define MBEDTLS_OID_EC_GRP_SECP384R1        MBEDTLS_OID_CERTICOM "\x00\x22"
-
-/* secp521r1 OBJECT IDENTIFIER ::= {
- *   iso(1) identified-organization(3) certicom(132) curve(0) 35 } */
-#define MBEDTLS_OID_EC_GRP_SECP521R1        MBEDTLS_OID_CERTICOM "\x00\x23"
-
-/* secp192k1 OBJECT IDENTIFIER ::= {
- *   iso(1) identified-organization(3) certicom(132) curve(0) 31 } */
-#define MBEDTLS_OID_EC_GRP_SECP192K1        MBEDTLS_OID_CERTICOM "\x00\x1f"
-
-/* secp224k1 OBJECT IDENTIFIER ::= {
- *   iso(1) identified-organization(3) certicom(132) curve(0) 32 } */
-#define MBEDTLS_OID_EC_GRP_SECP224K1        MBEDTLS_OID_CERTICOM "\x00\x20"
-
-/* secp256k1 OBJECT IDENTIFIER ::= {
- *   iso(1) identified-organization(3) certicom(132) curve(0) 10 } */
-#define MBEDTLS_OID_EC_GRP_SECP256K1        MBEDTLS_OID_CERTICOM "\x00\x0a"
-
-/* RFC 5639 4.1
- * ecStdCurvesAndGeneration OBJECT IDENTIFIER::= {iso(1)
- * identified-organization(3) teletrust(36) algorithm(3) signature-
- * algorithm(3) ecSign(2) 8}
- * ellipticCurve OBJECT IDENTIFIER ::= {ecStdCurvesAndGeneration 1}
- * versionOne OBJECT IDENTIFIER ::= {ellipticCurve 1} */
-#define MBEDTLS_OID_EC_BRAINPOOL_V1         MBEDTLS_OID_TELETRUST "\x03\x03\x02\x08\x01\x01"
-
-/* brainpoolP256r1 OBJECT IDENTIFIER ::= {versionOne 7} */
-#define MBEDTLS_OID_EC_GRP_BP256R1          MBEDTLS_OID_EC_BRAINPOOL_V1 "\x07"
-
-/* brainpoolP384r1 OBJECT IDENTIFIER ::= {versionOne 11} */
-#define MBEDTLS_OID_EC_GRP_BP384R1          MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0B"
-
-/* brainpoolP512r1 OBJECT IDENTIFIER ::= {versionOne 13} */
-#define MBEDTLS_OID_EC_GRP_BP512R1          MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0D"
-
-/*
- * SEC1 C.1
- *
- * prime-field OBJECT IDENTIFIER ::= { id-fieldType 1 }
- * id-fieldType OBJECT IDENTIFIER ::= { ansi-X9-62 fieldType(1)}
- */
-#define MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE   MBEDTLS_OID_ANSI_X9_62 "\x01"
-#define MBEDTLS_OID_ANSI_X9_62_PRIME_FIELD  MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE "\x01"
-
-/*
- * ECDSA signature identifiers, from RFC 5480
- */
-#define MBEDTLS_OID_ANSI_X9_62_SIG          MBEDTLS_OID_ANSI_X9_62 "\x04" /* signatures(4) */
-#define MBEDTLS_OID_ANSI_X9_62_SIG_SHA2     MBEDTLS_OID_ANSI_X9_62_SIG "\x03" /* ecdsa-with-SHA2(3) */
-
-/* ecdsa-with-SHA1 OBJECT IDENTIFIER ::= {
- *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) 1 } */
-#define MBEDTLS_OID_ECDSA_SHA1              MBEDTLS_OID_ANSI_X9_62_SIG "\x01"
-
-/* ecdsa-with-SHA224 OBJECT IDENTIFIER ::= {
- *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4)
- *   ecdsa-with-SHA2(3) 1 } */
-#define MBEDTLS_OID_ECDSA_SHA224            MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x01"
-
-/* ecdsa-with-SHA256 OBJECT IDENTIFIER ::= {
- *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4)
- *   ecdsa-with-SHA2(3) 2 } */
-#define MBEDTLS_OID_ECDSA_SHA256            MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x02"
-
-/* ecdsa-with-SHA384 OBJECT IDENTIFIER ::= {
- *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4)
- *   ecdsa-with-SHA2(3) 3 } */
-#define MBEDTLS_OID_ECDSA_SHA384            MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x03"
-
-/* ecdsa-with-SHA512 OBJECT IDENTIFIER ::= {
- *   iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4)
- *   ecdsa-with-SHA2(3) 4 } */
-#define MBEDTLS_OID_ECDSA_SHA512            MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x04"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief Base OID descriptor structure
- */
-typedef struct mbedtls_oid_descriptor_t
-{
-    const char *asn1;               /*!< OID ASN.1 representation       */
-    size_t asn1_len;                /*!< length of asn1                 */
-    const char *name;               /*!< official name (e.g. from RFC)  */
-    const char *description;        /*!< human friendly description     */
-} mbedtls_oid_descriptor_t;
-
-/**
- * \brief           Translate an ASN.1 OID into its numeric representation
- *                  (e.g. "\x2A\x86\x48\x86\xF7\x0D" into "1.2.840.113549")
- *
- * \param buf       buffer to put representation in
- * \param size      size of the buffer
- * \param oid       OID to translate
- *
- * \return          Length of the string written (excluding final NULL) or
- *                  MBEDTLS_ERR_OID_BUF_TOO_SMALL in case of error
- */
-int mbedtls_oid_get_numeric_string( char *buf, size_t size, const mbedtls_asn1_buf *oid );
-
-#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C)
-/**
- * \brief          Translate an X.509 extension OID into local values
- *
- * \param oid      OID to use
- * \param ext_type place to store the extension type
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_x509_ext_type( const mbedtls_asn1_buf *oid, int *ext_type );
-#endif
-
-/**
- * \brief          Translate an X.509 attribute type OID into the short name
- *                 (e.g. the OID for an X520 Common Name into "CN")
- *
- * \param oid      OID to use
- * \param short_name    place to store the string pointer
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_attr_short_name( const mbedtls_asn1_buf *oid, const char **short_name );
-
-/**
- * \brief          Translate PublicKeyAlgorithm OID into pk_type
- *
- * \param oid      OID to use
- * \param pk_alg   place to store public key algorithm
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_pk_alg( const mbedtls_asn1_buf *oid, mbedtls_pk_type_t *pk_alg );
-
-/**
- * \brief          Translate pk_type into PublicKeyAlgorithm OID
- *
- * \param pk_alg   Public key type to look for
- * \param oid      place to store ASN.1 OID string pointer
- * \param olen     length of the OID
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_oid_by_pk_alg( mbedtls_pk_type_t pk_alg,
-                           const char **oid, size_t *olen );
-
-#if defined(MBEDTLS_ECP_C)
-/**
- * \brief          Translate NamedCurve OID into an EC group identifier
- *
- * \param oid      OID to use
- * \param grp_id   place to store group id
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_ec_grp( const mbedtls_asn1_buf *oid, mbedtls_ecp_group_id *grp_id );
-
-/**
- * \brief          Translate EC group identifier into NamedCurve OID
- *
- * \param grp_id   EC group identifier
- * \param oid      place to store ASN.1 OID string pointer
- * \param olen     length of the OID
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_oid_by_ec_grp( mbedtls_ecp_group_id grp_id,
-                           const char **oid, size_t *olen );
-#endif /* MBEDTLS_ECP_C */
-
-#if defined(MBEDTLS_MD_C)
-/**
- * \brief          Translate SignatureAlgorithm OID into md_type and pk_type
- *
- * \param oid      OID to use
- * \param md_alg   place to store message digest algorithm
- * \param pk_alg   place to store public key algorithm
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_sig_alg( const mbedtls_asn1_buf *oid,
-                     mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg );
-
-/**
- * \brief          Translate SignatureAlgorithm OID into description
- *
- * \param oid      OID to use
- * \param desc     place to store string pointer
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_sig_alg_desc( const mbedtls_asn1_buf *oid, const char **desc );
-
-/**
- * \brief          Translate md_type and pk_type into SignatureAlgorithm OID
- *
- * \param md_alg   message digest algorithm
- * \param pk_alg   public key algorithm
- * \param oid      place to store ASN.1 OID string pointer
- * \param olen     length of the OID
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_oid_by_sig_alg( mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg,
-                            const char **oid, size_t *olen );
-
-/**
- * \brief          Translate hash algorithm OID into md_type
- *
- * \param oid      OID to use
- * \param md_alg   place to store message digest algorithm
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_md_alg( const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg );
-
-/**
- * \brief          Translate hmac algorithm OID into md_type
- *
- * \param oid      OID to use
- * \param md_hmac  place to store message hmac algorithm
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_md_hmac( const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_hmac );
-#endif /* MBEDTLS_MD_C */
-
-/**
- * \brief          Translate Extended Key Usage OID into description
- *
- * \param oid      OID to use
- * \param desc     place to store string pointer
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_extended_key_usage( const mbedtls_asn1_buf *oid, const char **desc );
-
-/**
- * \brief          Translate md_type into hash algorithm OID
- *
- * \param md_alg   message digest algorithm
- * \param oid      place to store ASN.1 OID string pointer
- * \param olen     length of the OID
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_oid_by_md( mbedtls_md_type_t md_alg, const char **oid, size_t *olen );
-
-#if defined(MBEDTLS_CIPHER_C)
-/**
- * \brief          Translate encryption algorithm OID into cipher_type
- *
- * \param oid           OID to use
- * \param cipher_alg    place to store cipher algorithm
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_cipher_alg( const mbedtls_asn1_buf *oid, mbedtls_cipher_type_t *cipher_alg );
-#endif /* MBEDTLS_CIPHER_C */
-
-#if defined(MBEDTLS_PKCS12_C)
-/**
- * \brief          Translate PKCS#12 PBE algorithm OID into md_type and
- *                 cipher_type
- *
- * \param oid           OID to use
- * \param md_alg        place to store message digest algorithm
- * \param cipher_alg    place to store cipher algorithm
- *
- * \return         0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND
- */
-int mbedtls_oid_get_pkcs12_pbe_alg( const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg,
-                            mbedtls_cipher_type_t *cipher_alg );
-#endif /* MBEDTLS_PKCS12_C */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* oid.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/padlock.h b/tools/sdk/include/mbedtls/mbedtls/padlock.h
deleted file mode 100644
index bd476f5f385..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/padlock.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/**
- * \file padlock.h
- *
- * \brief VIA PadLock ACE for HW encryption/decryption supported by some
- *        processors
- *
- * \warning These functions are only for internal use by other library
- *          functions; you must not call them directly.
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_PADLOCK_H
-#define MBEDTLS_PADLOCK_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "aes.h"
-
-#define MBEDTLS_ERR_PADLOCK_DATA_MISALIGNED               -0x0030  /**< Input data should be aligned. */
-
-#if defined(__has_feature)
-#if __has_feature(address_sanitizer)
-#define MBEDTLS_HAVE_ASAN
-#endif
-#endif
-
-/* Some versions of ASan result in errors about not enough registers */
-#if defined(MBEDTLS_HAVE_ASM) && defined(__GNUC__) && defined(__i386__) && \
-    !defined(MBEDTLS_HAVE_ASAN)
-
-#ifndef MBEDTLS_HAVE_X86
-#define MBEDTLS_HAVE_X86
-#endif
-
-#include <stdint.h>
-
-#define MBEDTLS_PADLOCK_RNG 0x000C
-#define MBEDTLS_PADLOCK_ACE 0x00C0
-#define MBEDTLS_PADLOCK_PHE 0x0C00
-#define MBEDTLS_PADLOCK_PMM 0x3000
-
-#define MBEDTLS_PADLOCK_ALIGN16(x) (uint32_t *) (16 + ((int32_t) (x) & ~15))
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          Internal PadLock detection routine
- *
- * \note           This function is only for internal use by other library
- *                 functions; you must not call it directly.
- *
- * \param feature  The feature to detect
- *
- * \return         1 if CPU has support for the feature, 0 otherwise
- */
-int mbedtls_padlock_has_support( int feature );
-
-/**
- * \brief          Internal PadLock AES-ECB block en(de)cryption
- *
- * \note           This function is only for internal use by other library
- *                 functions; you must not call it directly.
- *
- * \param ctx      AES context
- * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param input    16-byte input block
- * \param output   16-byte output block
- *
- * \return         0 if success, 1 if operation failed
- */
-int mbedtls_padlock_xcryptecb( mbedtls_aes_context *ctx,
-                               int mode,
-                               const unsigned char input[16],
-                               unsigned char output[16] );
-
-/**
- * \brief          Internal PadLock AES-CBC buffer en(de)cryption
- *
- * \note           This function is only for internal use by other library
- *                 functions; you must not call it directly.
- *
- * \param ctx      AES context
- * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param length   length of the input data
- * \param iv       initialization vector (updated after use)
- * \param input    buffer holding the input data
- * \param output   buffer holding the output data
- *
- * \return         0 if success, 1 if operation failed
- */
-int mbedtls_padlock_xcryptcbc( mbedtls_aes_context *ctx,
-                               int mode,
-                               size_t length,
-                               unsigned char iv[16],
-                               const unsigned char *input,
-                               unsigned char *output );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAVE_X86  */
-
-#endif /* padlock.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pem.h b/tools/sdk/include/mbedtls/mbedtls/pem.h
deleted file mode 100644
index 16b6101415a..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/pem.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/**
- * \file pem.h
- *
- * \brief Privacy Enhanced Mail (PEM) decoding
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_PEM_H
-#define MBEDTLS_PEM_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-
-/**
- * \name PEM Error codes
- * These error codes are returned in case of errors reading the
- * PEM data.
- * \{
- */
-#define MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT          -0x1080  /**< No PEM header or footer found. */
-#define MBEDTLS_ERR_PEM_INVALID_DATA                      -0x1100  /**< PEM string is not as expected. */
-#define MBEDTLS_ERR_PEM_ALLOC_FAILED                      -0x1180  /**< Failed to allocate memory. */
-#define MBEDTLS_ERR_PEM_INVALID_ENC_IV                    -0x1200  /**< RSA IV is not in hex-format. */
-#define MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG                   -0x1280  /**< Unsupported key encryption algorithm. */
-#define MBEDTLS_ERR_PEM_PASSWORD_REQUIRED                 -0x1300  /**< Private key password can't be empty. */
-#define MBEDTLS_ERR_PEM_PASSWORD_MISMATCH                 -0x1380  /**< Given private key password does not allow for correct decryption. */
-#define MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE               -0x1400  /**< Unavailable feature, e.g. hashing/encryption combination. */
-#define MBEDTLS_ERR_PEM_BAD_INPUT_DATA                    -0x1480  /**< Bad input parameters to function. */
-/* \} name */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(MBEDTLS_PEM_PARSE_C)
-/**
- * \brief       PEM context structure
- */
-typedef struct mbedtls_pem_context
-{
-    unsigned char *buf;     /*!< buffer for decoded data             */
-    size_t buflen;          /*!< length of the buffer                */
-    unsigned char *info;    /*!< buffer for extra header information */
-}
-mbedtls_pem_context;
-
-/**
- * \brief       PEM context setup
- *
- * \param ctx   context to be initialized
- */
-void mbedtls_pem_init( mbedtls_pem_context *ctx );
-
-/**
- * \brief       Read a buffer for PEM information and store the resulting
- *              data into the specified context buffers.
- *
- * \param ctx       context to use
- * \param header    header string to seek and expect
- * \param footer    footer string to seek and expect
- * \param data      source data to look in (must be nul-terminated)
- * \param pwd       password for decryption (can be NULL)
- * \param pwdlen    length of password
- * \param use_len   destination for total length used (set after header is
- *                  correctly read, so unless you get
- *                  MBEDTLS_ERR_PEM_BAD_INPUT_DATA or
- *                  MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT, use_len is
- *                  the length to skip)
- *
- * \note            Attempts to check password correctness by verifying if
- *                  the decrypted text starts with an ASN.1 sequence of
- *                  appropriate length
- *
- * \return          0 on success, or a specific PEM error code
- */
-int mbedtls_pem_read_buffer( mbedtls_pem_context *ctx, const char *header, const char *footer,
-                     const unsigned char *data,
-                     const unsigned char *pwd,
-                     size_t pwdlen, size_t *use_len );
-
-/**
- * \brief       PEM context memory freeing
- *
- * \param ctx   context to be freed
- */
-void mbedtls_pem_free( mbedtls_pem_context *ctx );
-#endif /* MBEDTLS_PEM_PARSE_C */
-
-#if defined(MBEDTLS_PEM_WRITE_C)
-/**
- * \brief           Write a buffer of PEM information from a DER encoded
- *                  buffer.
- *
- * \param header    header string to write
- * \param footer    footer string to write
- * \param der_data  DER data to write
- * \param der_len   length of the DER data
- * \param buf       buffer to write to
- * \param buf_len   length of output buffer
- * \param olen      total length written / required (if buf_len is not enough)
- *
- * \return          0 on success, or a specific PEM or BASE64 error code. On
- *                  MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL olen is the required
- *                  size.
- */
-int mbedtls_pem_write_buffer( const char *header, const char *footer,
-                      const unsigned char *der_data, size_t der_len,
-                      unsigned char *buf, size_t buf_len, size_t *olen );
-#endif /* MBEDTLS_PEM_WRITE_C */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* pem.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pk.h b/tools/sdk/include/mbedtls/mbedtls/pk.h
deleted file mode 100644
index 408f7baee7d..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/pk.h
+++ /dev/null
@@ -1,782 +0,0 @@
-/**
- * \file pk.h
- *
- * \brief Public Key abstraction layer
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_PK_H
-#define MBEDTLS_PK_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "md.h"
-
-#if defined(MBEDTLS_RSA_C)
-#include "rsa.h"
-#endif
-
-#if defined(MBEDTLS_ECP_C)
-#include "ecp.h"
-#endif
-
-#if defined(MBEDTLS_ECDSA_C)
-#include "ecdsa.h"
-#endif
-
-#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
-    !defined(inline) && !defined(__cplusplus)
-#define inline __inline
-#endif
-
-#define MBEDTLS_ERR_PK_ALLOC_FAILED        -0x3F80  /**< Memory allocation failed. */
-#define MBEDTLS_ERR_PK_TYPE_MISMATCH       -0x3F00  /**< Type mismatch, eg attempt to encrypt with an ECDSA key */
-#define MBEDTLS_ERR_PK_BAD_INPUT_DATA      -0x3E80  /**< Bad input parameters to function. */
-#define MBEDTLS_ERR_PK_FILE_IO_ERROR       -0x3E00  /**< Read/write of file failed. */
-#define MBEDTLS_ERR_PK_KEY_INVALID_VERSION -0x3D80  /**< Unsupported key version */
-#define MBEDTLS_ERR_PK_KEY_INVALID_FORMAT  -0x3D00  /**< Invalid key tag or value. */
-#define MBEDTLS_ERR_PK_UNKNOWN_PK_ALG      -0x3C80  /**< Key algorithm is unsupported (only RSA and EC are supported). */
-#define MBEDTLS_ERR_PK_PASSWORD_REQUIRED   -0x3C00  /**< Private key password can't be empty. */
-#define MBEDTLS_ERR_PK_PASSWORD_MISMATCH   -0x3B80  /**< Given private key password does not allow for correct decryption. */
-#define MBEDTLS_ERR_PK_INVALID_PUBKEY      -0x3B00  /**< The pubkey tag or value is invalid (only RSA and EC are supported). */
-#define MBEDTLS_ERR_PK_INVALID_ALG         -0x3A80  /**< The algorithm tag or value is invalid. */
-#define MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE -0x3A00  /**< Elliptic curve is unsupported (only NIST curves are supported). */
-#define MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE -0x3980  /**< Unavailable feature, e.g. RSA disabled for RSA key. */
-#define MBEDTLS_ERR_PK_SIG_LEN_MISMATCH    -0x3900  /**< The buffer contains a valid signature followed by more data. */
-
-/* MBEDTLS_ERR_PK_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_PK_HW_ACCEL_FAILED     -0x3880  /**< PK hardware accelerator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          Public key types
- */
-typedef enum {
-    MBEDTLS_PK_NONE=0,
-    MBEDTLS_PK_RSA,
-    MBEDTLS_PK_ECKEY,
-    MBEDTLS_PK_ECKEY_DH,
-    MBEDTLS_PK_ECDSA,
-    MBEDTLS_PK_RSA_ALT,
-    MBEDTLS_PK_RSASSA_PSS,
-} mbedtls_pk_type_t;
-
-/**
- * \brief           Options for RSASSA-PSS signature verification.
- *                  See \c mbedtls_rsa_rsassa_pss_verify_ext()
- */
-typedef struct mbedtls_pk_rsassa_pss_options
-{
-    mbedtls_md_type_t mgf1_hash_id;
-    int expected_salt_len;
-
-} mbedtls_pk_rsassa_pss_options;
-
-/**
- * \brief           Types for interfacing with the debug module
- */
-typedef enum
-{
-    MBEDTLS_PK_DEBUG_NONE = 0,
-    MBEDTLS_PK_DEBUG_MPI,
-    MBEDTLS_PK_DEBUG_ECP,
-} mbedtls_pk_debug_type;
-
-/**
- * \brief           Item to send to the debug module
- */
-typedef struct mbedtls_pk_debug_item
-{
-    mbedtls_pk_debug_type type;
-    const char *name;
-    void *value;
-} mbedtls_pk_debug_item;
-
-/** Maximum number of item send for debugging, plus 1 */
-#define MBEDTLS_PK_DEBUG_MAX_ITEMS 3
-
-/**
- * \brief           Public key information and operations
- */
-typedef struct mbedtls_pk_info_t mbedtls_pk_info_t;
-
-/**
- * \brief           Public key container
- */
-typedef struct mbedtls_pk_context
-{
-    const mbedtls_pk_info_t *   pk_info; /**< Public key information         */
-    void *                      pk_ctx;  /**< Underlying public key context  */
-} mbedtls_pk_context;
-
-#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE)
-/**
- * \brief           Context for resuming operations
- */
-typedef struct
-{
-    const mbedtls_pk_info_t *   pk_info; /**< Public key information         */
-    void *                      rs_ctx;  /**< Underlying restart context     */
-} mbedtls_pk_restart_ctx;
-#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */
-/* Now we can declare functions that take a pointer to that */
-typedef void mbedtls_pk_restart_ctx;
-#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */
-
-#if defined(MBEDTLS_RSA_C)
-/**
- * Quick access to an RSA context inside a PK context.
- *
- * \warning You must make sure the PK context actually holds an RSA context
- * before using this function!
- */
-static inline mbedtls_rsa_context *mbedtls_pk_rsa( const mbedtls_pk_context pk )
-{
-    return( (mbedtls_rsa_context *) (pk).pk_ctx );
-}
-#endif /* MBEDTLS_RSA_C */
-
-#if defined(MBEDTLS_ECP_C)
-/**
- * Quick access to an EC context inside a PK context.
- *
- * \warning You must make sure the PK context actually holds an EC context
- * before using this function!
- */
-static inline mbedtls_ecp_keypair *mbedtls_pk_ec( const mbedtls_pk_context pk )
-{
-    return( (mbedtls_ecp_keypair *) (pk).pk_ctx );
-}
-#endif /* MBEDTLS_ECP_C */
-
-#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT)
-/**
- * \brief           Types for RSA-alt abstraction
- */
-typedef int (*mbedtls_pk_rsa_alt_decrypt_func)( void *ctx, int mode, size_t *olen,
-                    const unsigned char *input, unsigned char *output,
-                    size_t output_max_len );
-typedef int (*mbedtls_pk_rsa_alt_sign_func)( void *ctx,
-                    int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
-                    int mode, mbedtls_md_type_t md_alg, unsigned int hashlen,
-                    const unsigned char *hash, unsigned char *sig );
-typedef size_t (*mbedtls_pk_rsa_alt_key_len_func)( void *ctx );
-#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */
-
-/**
- * \brief           Return information associated with the given PK type
- *
- * \param pk_type   PK type to search for.
- *
- * \return          The PK info associated with the type or NULL if not found.
- */
-const mbedtls_pk_info_t *mbedtls_pk_info_from_type( mbedtls_pk_type_t pk_type );
-
-/**
- * \brief           Initialize a #mbedtls_pk_context (as NONE).
- *
- * \param ctx       The context to initialize.
- *                  This must not be \c NULL.
- */
-void mbedtls_pk_init( mbedtls_pk_context *ctx );
-
-/**
- * \brief           Free the components of a #mbedtls_pk_context.
- *
- * \param ctx       The context to clear. It must have been initialized.
- *                  If this is \c NULL, this function does nothing.
- */
-void mbedtls_pk_free( mbedtls_pk_context *ctx );
-
-#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE)
-/**
- * \brief           Initialize a restart context
- *
- * \param ctx       The context to initialize.
- *                  This must not be \c NULL.
- */
-void mbedtls_pk_restart_init( mbedtls_pk_restart_ctx *ctx );
-
-/**
- * \brief           Free the components of a restart context
- *
- * \param ctx       The context to clear. It must have been initialized.
- *                  If this is \c NULL, this function does nothing.
- */
-void mbedtls_pk_restart_free( mbedtls_pk_restart_ctx *ctx );
-#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */
-
-/**
- * \brief           Initialize a PK context with the information given
- *                  and allocates the type-specific PK subcontext.
- *
- * \param ctx       Context to initialize. It must not have been set
- *                  up yet (type #MBEDTLS_PK_NONE).
- * \param info      Information to use
- *
- * \return          0 on success,
- *                  MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input,
- *                  MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure.
- *
- * \note            For contexts holding an RSA-alt key, use
- *                  \c mbedtls_pk_setup_rsa_alt() instead.
- */
-int mbedtls_pk_setup( mbedtls_pk_context *ctx, const mbedtls_pk_info_t *info );
-
-#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT)
-/**
- * \brief           Initialize an RSA-alt context
- *
- * \param ctx       Context to initialize. It must not have been set
- *                  up yet (type #MBEDTLS_PK_NONE).
- * \param key       RSA key pointer
- * \param decrypt_func  Decryption function
- * \param sign_func     Signing function
- * \param key_len_func  Function returning key length in bytes
- *
- * \return          0 on success, or MBEDTLS_ERR_PK_BAD_INPUT_DATA if the
- *                  context wasn't already initialized as RSA_ALT.
- *
- * \note            This function replaces \c mbedtls_pk_setup() for RSA-alt.
- */
-int mbedtls_pk_setup_rsa_alt( mbedtls_pk_context *ctx, void * key,
-                         mbedtls_pk_rsa_alt_decrypt_func decrypt_func,
-                         mbedtls_pk_rsa_alt_sign_func sign_func,
-                         mbedtls_pk_rsa_alt_key_len_func key_len_func );
-#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */
-
-/**
- * \brief           Get the size in bits of the underlying key
- *
- * \param ctx       The context to query. It must have been initialized.
- *
- * \return          Key size in bits, or 0 on error
- */
-size_t mbedtls_pk_get_bitlen( const mbedtls_pk_context *ctx );
-
-/**
- * \brief           Get the length in bytes of the underlying key
- *
- * \param ctx       The context to query. It must have been initialized.
- *
- * \return          Key length in bytes, or 0 on error
- */
-static inline size_t mbedtls_pk_get_len( const mbedtls_pk_context *ctx )
-{
-    return( ( mbedtls_pk_get_bitlen( ctx ) + 7 ) / 8 );
-}
-
-/**
- * \brief           Tell if a context can do the operation given by type
- *
- * \param ctx       The context to query. It must have been initialized.
- * \param type      The desired type.
- *
- * \return          1 if the context can do operations on the given type.
- * \return          0 if the context cannot do the operations on the given
- *                  type. This is always the case for a context that has
- *                  been initialized but not set up, or that has been
- *                  cleared with mbedtls_pk_free().
- */
-int mbedtls_pk_can_do( const mbedtls_pk_context *ctx, mbedtls_pk_type_t type );
-
-/**
- * \brief           Verify signature (including padding if relevant).
- *
- * \param ctx       The PK context to use. It must have been set up.
- * \param md_alg    Hash algorithm used (see notes)
- * \param hash      Hash of the message to sign
- * \param hash_len  Hash length or 0 (see notes)
- * \param sig       Signature to verify
- * \param sig_len   Signature length
- *
- * \return          0 on success (signature is valid),
- *                  #MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if there is a valid
- *                  signature in sig but its length is less than \p siglen,
- *                  or a specific error code.
- *
- * \note            For RSA keys, the default padding type is PKCS#1 v1.5.
- *                  Use \c mbedtls_pk_verify_ext( MBEDTLS_PK_RSASSA_PSS, ... )
- *                  to verify RSASSA_PSS signatures.
- *
- * \note            If hash_len is 0, then the length associated with md_alg
- *                  is used instead, or an error returned if it is invalid.
- *
- * \note            md_alg may be MBEDTLS_MD_NONE, only if hash_len != 0
- */
-int mbedtls_pk_verify( mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg,
-               const unsigned char *hash, size_t hash_len,
-               const unsigned char *sig, size_t sig_len );
-
-/**
- * \brief           Restartable version of \c mbedtls_pk_verify()
- *
- * \note            Performs the same job as \c mbedtls_pk_verify(), but can
- *                  return early and restart according to the limit set with
- *                  \c mbedtls_ecp_set_max_ops() to reduce blocking for ECC
- *                  operations. For RSA, same as \c mbedtls_pk_verify().
- *
- * \param ctx       The PK context to use. It must have been set up.
- * \param md_alg    Hash algorithm used (see notes)
- * \param hash      Hash of the message to sign
- * \param hash_len  Hash length or 0 (see notes)
- * \param sig       Signature to verify
- * \param sig_len   Signature length
- * \param rs_ctx    Restart context (NULL to disable restart)
- *
- * \return          See \c mbedtls_pk_verify(), or
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                  operations was reached: see \c mbedtls_ecp_set_max_ops().
- */
-int mbedtls_pk_verify_restartable( mbedtls_pk_context *ctx,
-               mbedtls_md_type_t md_alg,
-               const unsigned char *hash, size_t hash_len,
-               const unsigned char *sig, size_t sig_len,
-               mbedtls_pk_restart_ctx *rs_ctx );
-
-/**
- * \brief           Verify signature, with options.
- *                  (Includes verification of the padding depending on type.)
- *
- * \param type      Signature type (inc. possible padding type) to verify
- * \param options   Pointer to type-specific options, or NULL
- * \param ctx       The PK context to use. It must have been set up.
- * \param md_alg    Hash algorithm used (see notes)
- * \param hash      Hash of the message to sign
- * \param hash_len  Hash length or 0 (see notes)
- * \param sig       Signature to verify
- * \param sig_len   Signature length
- *
- * \return          0 on success (signature is valid),
- *                  #MBEDTLS_ERR_PK_TYPE_MISMATCH if the PK context can't be
- *                  used for this type of signatures,
- *                  #MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if there is a valid
- *                  signature in sig but its length is less than \p siglen,
- *                  or a specific error code.
- *
- * \note            If hash_len is 0, then the length associated with md_alg
- *                  is used instead, or an error returned if it is invalid.
- *
- * \note            md_alg may be MBEDTLS_MD_NONE, only if hash_len != 0
- *
- * \note            If type is MBEDTLS_PK_RSASSA_PSS, then options must point
- *                  to a mbedtls_pk_rsassa_pss_options structure,
- *                  otherwise it must be NULL.
- */
-int mbedtls_pk_verify_ext( mbedtls_pk_type_t type, const void *options,
-                   mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg,
-                   const unsigned char *hash, size_t hash_len,
-                   const unsigned char *sig, size_t sig_len );
-
-/**
- * \brief           Make signature, including padding if relevant.
- *
- * \param ctx       The PK context to use. It must have been set up
- *                  with a private key.
- * \param md_alg    Hash algorithm used (see notes)
- * \param hash      Hash of the message to sign
- * \param hash_len  Hash length or 0 (see notes)
- * \param sig       Place to write the signature
- * \param sig_len   Number of bytes written
- * \param f_rng     RNG function
- * \param p_rng     RNG parameter
- *
- * \return          0 on success, or a specific error code.
- *
- * \note            For RSA keys, the default padding type is PKCS#1 v1.5.
- *                  There is no interface in the PK module to make RSASSA-PSS
- *                  signatures yet.
- *
- * \note            If hash_len is 0, then the length associated with md_alg
- *                  is used instead, or an error returned if it is invalid.
- *
- * \note            For RSA, md_alg may be MBEDTLS_MD_NONE if hash_len != 0.
- *                  For ECDSA, md_alg may never be MBEDTLS_MD_NONE.
- *
- * \note            In order to ensure enough space for the signature, the
- *                  \p sig buffer size must be of at least
- *                  `max(MBEDTLS_ECDSA_MAX_LEN, MBEDTLS_MPI_MAX_SIZE)` bytes.
- */
-int mbedtls_pk_sign( mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg,
-             const unsigned char *hash, size_t hash_len,
-             unsigned char *sig, size_t *sig_len,
-             int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
-
-/**
- * \brief           Restartable version of \c mbedtls_pk_sign()
- *
- * \note            Performs the same job as \c mbedtls_pk_sign(), but can
- *                  return early and restart according to the limit set with
- *                  \c mbedtls_ecp_set_max_ops() to reduce blocking for ECC
- *                  operations. For RSA, same as \c mbedtls_pk_sign().
- *
- * \note            In order to ensure enough space for the signature, the
- *                  \p sig buffer size must be of at least
- *                  `max(MBEDTLS_ECDSA_MAX_LEN, MBEDTLS_MPI_MAX_SIZE)` bytes.
- *
- * \param ctx       The PK context to use. It must have been set up
- *                  with a private key.
- * \param md_alg    Hash algorithm used (see notes)
- * \param hash      Hash of the message to sign
- * \param hash_len  Hash length or 0 (see notes)
- * \param sig       Place to write the signature
- * \param sig_len   Number of bytes written
- * \param f_rng     RNG function
- * \param p_rng     RNG parameter
- * \param rs_ctx    Restart context (NULL to disable restart)
- *
- * \return          See \c mbedtls_pk_sign(), or
- * \return          #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                  operations was reached: see \c mbedtls_ecp_set_max_ops().
- */
-int mbedtls_pk_sign_restartable( mbedtls_pk_context *ctx,
-             mbedtls_md_type_t md_alg,
-             const unsigned char *hash, size_t hash_len,
-             unsigned char *sig, size_t *sig_len,
-             int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
-             mbedtls_pk_restart_ctx *rs_ctx );
-
-/**
- * \brief           Decrypt message (including padding if relevant).
- *
- * \param ctx       The PK context to use. It must have been set up
- *                  with a private key.
- * \param input     Input to decrypt
- * \param ilen      Input size
- * \param output    Decrypted output
- * \param olen      Decrypted message length
- * \param osize     Size of the output buffer
- * \param f_rng     RNG function
- * \param p_rng     RNG parameter
- *
- * \note            For RSA keys, the default padding type is PKCS#1 v1.5.
- *
- * \return          0 on success, or a specific error code.
- */
-int mbedtls_pk_decrypt( mbedtls_pk_context *ctx,
-                const unsigned char *input, size_t ilen,
-                unsigned char *output, size_t *olen, size_t osize,
-                int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
-
-/**
- * \brief           Encrypt message (including padding if relevant).
- *
- * \param ctx       The PK context to use. It must have been set up.
- * \param input     Message to encrypt
- * \param ilen      Message size
- * \param output    Encrypted output
- * \param olen      Encrypted output length
- * \param osize     Size of the output buffer
- * \param f_rng     RNG function
- * \param p_rng     RNG parameter
- *
- * \note            For RSA keys, the default padding type is PKCS#1 v1.5.
- *
- * \return          0 on success, or a specific error code.
- */
-int mbedtls_pk_encrypt( mbedtls_pk_context *ctx,
-                const unsigned char *input, size_t ilen,
-                unsigned char *output, size_t *olen, size_t osize,
-                int (*f_rng)(void *, unsigned char *, size_t), void *p_rng );
-
-/**
- * \brief           Check if a public-private pair of keys matches.
- *
- * \param pub       Context holding a public key.
- * \param prv       Context holding a private (and public) key.
- *
- * \return          0 on success or MBEDTLS_ERR_PK_BAD_INPUT_DATA
- */
-int mbedtls_pk_check_pair( const mbedtls_pk_context *pub, const mbedtls_pk_context *prv );
-
-/**
- * \brief           Export debug information
- *
- * \param ctx       The PK context to use. It must have been initialized.
- * \param items     Place to write debug items
- *
- * \return          0 on success or MBEDTLS_ERR_PK_BAD_INPUT_DATA
- */
-int mbedtls_pk_debug( const mbedtls_pk_context *ctx, mbedtls_pk_debug_item *items );
-
-/**
- * \brief           Access the type name
- *
- * \param ctx       The PK context to use. It must have been initialized.
- *
- * \return          Type name on success, or "invalid PK"
- */
-const char * mbedtls_pk_get_name( const mbedtls_pk_context *ctx );
-
-/**
- * \brief           Get the key type
- *
- * \param ctx       The PK context to use. It must have been initialized.
- *
- * \return          Type on success.
- * \return          #MBEDTLS_PK_NONE for a context that has not been set up.
- */
-mbedtls_pk_type_t mbedtls_pk_get_type( const mbedtls_pk_context *ctx );
-
-#if defined(MBEDTLS_PK_PARSE_C)
-/** \ingroup pk_module */
-/**
- * \brief           Parse a private key in PEM or DER format
- *
- * \param ctx       The PK context to fill. It must have been initialized
- *                  but not set up.
- * \param key       Input buffer to parse.
- *                  The buffer must contain the input exactly, with no
- *                  extra trailing material. For PEM, the buffer must
- *                  contain a null-terminated string.
- * \param keylen    Size of \b key in bytes.
- *                  For PEM data, this includes the terminating null byte,
- *                  so \p keylen must be equal to `strlen(key) + 1`.
- * \param pwd       Optional password for decryption.
- *                  Pass \c NULL if expecting a non-encrypted key.
- *                  Pass a string of \p pwdlen bytes if expecting an encrypted
- *                  key; a non-encrypted key will also be accepted.
- *                  The empty password is not supported.
- * \param pwdlen    Size of the password in bytes.
- *                  Ignored if \p pwd is \c NULL.
- *
- * \note            On entry, ctx must be empty, either freshly initialised
- *                  with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a
- *                  specific key type, check the result with mbedtls_pk_can_do().
- *
- * \note            The key is also checked for correctness.
- *
- * \return          0 if successful, or a specific PK or PEM error code
- */
-int mbedtls_pk_parse_key( mbedtls_pk_context *ctx,
-                  const unsigned char *key, size_t keylen,
-                  const unsigned char *pwd, size_t pwdlen );
-
-/** \ingroup pk_module */
-/**
- * \brief           Parse a public key in PEM or DER format
- *
- * \param ctx       The PK context to fill. It must have been initialized
- *                  but not set up.
- * \param key       Input buffer to parse.
- *                  The buffer must contain the input exactly, with no
- *                  extra trailing material. For PEM, the buffer must
- *                  contain a null-terminated string.
- * \param keylen    Size of \b key in bytes.
- *                  For PEM data, this includes the terminating null byte,
- *                  so \p keylen must be equal to `strlen(key) + 1`.
- *
- * \note            On entry, ctx must be empty, either freshly initialised
- *                  with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a
- *                  specific key type, check the result with mbedtls_pk_can_do().
- *
- * \note            The key is also checked for correctness.
- *
- * \return          0 if successful, or a specific PK or PEM error code
- */
-int mbedtls_pk_parse_public_key( mbedtls_pk_context *ctx,
-                         const unsigned char *key, size_t keylen );
-
-#if defined(MBEDTLS_FS_IO)
-/** \ingroup pk_module */
-/**
- * \brief           Load and parse a private key
- *
- * \param ctx       The PK context to fill. It must have been initialized
- *                  but not set up.
- * \param path      filename to read the private key from
- * \param password  Optional password to decrypt the file.
- *                  Pass \c NULL if expecting a non-encrypted key.
- *                  Pass a null-terminated string if expecting an encrypted
- *                  key; a non-encrypted key will also be accepted.
- *                  The empty password is not supported.
- *
- * \note            On entry, ctx must be empty, either freshly initialised
- *                  with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a
- *                  specific key type, check the result with mbedtls_pk_can_do().
- *
- * \note            The key is also checked for correctness.
- *
- * \return          0 if successful, or a specific PK or PEM error code
- */
-int mbedtls_pk_parse_keyfile( mbedtls_pk_context *ctx,
-                      const char *path, const char *password );
-
-/** \ingroup pk_module */
-/**
- * \brief           Load and parse a public key
- *
- * \param ctx       The PK context to fill. It must have been initialized
- *                  but not set up.
- * \param path      filename to read the public key from
- *
- * \note            On entry, ctx must be empty, either freshly initialised
- *                  with mbedtls_pk_init() or reset with mbedtls_pk_free(). If
- *                  you need a specific key type, check the result with
- *                  mbedtls_pk_can_do().
- *
- * \note            The key is also checked for correctness.
- *
- * \return          0 if successful, or a specific PK or PEM error code
- */
-int mbedtls_pk_parse_public_keyfile( mbedtls_pk_context *ctx, const char *path );
-#endif /* MBEDTLS_FS_IO */
-#endif /* MBEDTLS_PK_PARSE_C */
-
-#if defined(MBEDTLS_PK_WRITE_C)
-/**
- * \brief           Write a private key to a PKCS#1 or SEC1 DER structure
- *                  Note: data is written at the end of the buffer! Use the
- *                        return value to determine where you should start
- *                        using the buffer
- *
- * \param ctx       PK context which must contain a valid private key.
- * \param buf       buffer to write to
- * \param size      size of the buffer
- *
- * \return          length of data written if successful, or a specific
- *                  error code
- */
-int mbedtls_pk_write_key_der( mbedtls_pk_context *ctx, unsigned char *buf, size_t size );
-
-/**
- * \brief           Write a public key to a SubjectPublicKeyInfo DER structure
- *                  Note: data is written at the end of the buffer! Use the
- *                        return value to determine where you should start
- *                        using the buffer
- *
- * \param ctx       PK context which must contain a valid public or private key.
- * \param buf       buffer to write to
- * \param size      size of the buffer
- *
- * \return          length of data written if successful, or a specific
- *                  error code
- */
-int mbedtls_pk_write_pubkey_der( mbedtls_pk_context *ctx, unsigned char *buf, size_t size );
-
-#if defined(MBEDTLS_PEM_WRITE_C)
-/**
- * \brief           Write a public key to a PEM string
- *
- * \param ctx       PK context which must contain a valid public or private key.
- * \param buf       Buffer to write to. The output includes a
- *                  terminating null byte.
- * \param size      Size of the buffer in bytes.
- *
- * \return          0 if successful, or a specific error code
- */
-int mbedtls_pk_write_pubkey_pem( mbedtls_pk_context *ctx, unsigned char *buf, size_t size );
-
-/**
- * \brief           Write a private key to a PKCS#1 or SEC1 PEM string
- *
- * \param ctx       PK context which must contain a valid private key.
- * \param buf       Buffer to write to. The output includes a
- *                  terminating null byte.
- * \param size      Size of the buffer in bytes.
- *
- * \return          0 if successful, or a specific error code
- */
-int mbedtls_pk_write_key_pem( mbedtls_pk_context *ctx, unsigned char *buf, size_t size );
-#endif /* MBEDTLS_PEM_WRITE_C */
-#endif /* MBEDTLS_PK_WRITE_C */
-
-/*
- * WARNING: Low-level functions. You probably do not want to use these unless
- *          you are certain you do ;)
- */
-
-#if defined(MBEDTLS_PK_PARSE_C)
-/**
- * \brief           Parse a SubjectPublicKeyInfo DER structure
- *
- * \param p         the position in the ASN.1 data
- * \param end       end of the buffer
- * \param pk        The PK context to fill. It must have been initialized
- *                  but not set up.
- *
- * \return          0 if successful, or a specific PK error code
- */
-int mbedtls_pk_parse_subpubkey( unsigned char **p, const unsigned char *end,
-                        mbedtls_pk_context *pk );
-#endif /* MBEDTLS_PK_PARSE_C */
-
-#if defined(MBEDTLS_PK_WRITE_C)
-/**
- * \brief           Write a subjectPublicKey to ASN.1 data
- *                  Note: function works backwards in data buffer
- *
- * \param p         reference to current position pointer
- * \param start     start of the buffer (for bounds-checking)
- * \param key       PK context which must contain a valid public or private key.
- *
- * \return          the length written or a negative error code
- */
-int mbedtls_pk_write_pubkey( unsigned char **p, unsigned char *start,
-                     const mbedtls_pk_context *key );
-#endif /* MBEDTLS_PK_WRITE_C */
-
-/*
- * Internal module functions. You probably do not want to use these unless you
- * know you do.
- */
-#if defined(MBEDTLS_FS_IO)
-int mbedtls_pk_load_file( const char *path, unsigned char **buf, size_t *n );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_PK_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pk_internal.h b/tools/sdk/include/mbedtls/mbedtls/pk_internal.h
deleted file mode 100644
index 1cd05943bac..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/pk_internal.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/**
- * \file pk_internal.h
- *
- * \brief Public Key abstraction layer: wrapper functions
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_PK_WRAP_H
-#define MBEDTLS_PK_WRAP_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "pk.h"
-
-struct mbedtls_pk_info_t
-{
-    /** Public key type */
-    mbedtls_pk_type_t type;
-
-    /** Type name */
-    const char *name;
-
-    /** Get key size in bits */
-    size_t (*get_bitlen)( const void * );
-
-    /** Tell if the context implements this type (e.g. ECKEY can do ECDSA) */
-    int (*can_do)( mbedtls_pk_type_t type );
-
-    /** Verify signature */
-    int (*verify_func)( void *ctx, mbedtls_md_type_t md_alg,
-                        const unsigned char *hash, size_t hash_len,
-                        const unsigned char *sig, size_t sig_len );
-
-    /** Make signature */
-    int (*sign_func)( void *ctx, mbedtls_md_type_t md_alg,
-                      const unsigned char *hash, size_t hash_len,
-                      unsigned char *sig, size_t *sig_len,
-                      int (*f_rng)(void *, unsigned char *, size_t),
-                      void *p_rng );
-
-#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE)
-    /** Verify signature (restartable) */
-    int (*verify_rs_func)( void *ctx, mbedtls_md_type_t md_alg,
-                           const unsigned char *hash, size_t hash_len,
-                           const unsigned char *sig, size_t sig_len,
-                           void *rs_ctx );
-
-    /** Make signature (restartable) */
-    int (*sign_rs_func)( void *ctx, mbedtls_md_type_t md_alg,
-                         const unsigned char *hash, size_t hash_len,
-                         unsigned char *sig, size_t *sig_len,
-                         int (*f_rng)(void *, unsigned char *, size_t),
-                         void *p_rng, void *rs_ctx );
-#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */
-
-    /** Decrypt message */
-    int (*decrypt_func)( void *ctx, const unsigned char *input, size_t ilen,
-                         unsigned char *output, size_t *olen, size_t osize,
-                         int (*f_rng)(void *, unsigned char *, size_t),
-                         void *p_rng );
-
-    /** Encrypt message */
-    int (*encrypt_func)( void *ctx, const unsigned char *input, size_t ilen,
-                         unsigned char *output, size_t *olen, size_t osize,
-                         int (*f_rng)(void *, unsigned char *, size_t),
-                         void *p_rng );
-
-    /** Check public-private key pair */
-    int (*check_pair_func)( const void *pub, const void *prv );
-
-    /** Allocate a new context */
-    void * (*ctx_alloc_func)( void );
-
-    /** Free the given context */
-    void (*ctx_free_func)( void *ctx );
-
-#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE)
-    /** Allocate the restart context */
-    void * (*rs_alloc_func)( void );
-
-    /** Free the restart context */
-    void (*rs_free_func)( void *rs_ctx );
-#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */
-
-    /** Interface with the debug module */
-    void (*debug_func)( const void *ctx, mbedtls_pk_debug_item *items );
-
-};
-#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT)
-/* Container for RSA-alt */
-typedef struct
-{
-    void *key;
-    mbedtls_pk_rsa_alt_decrypt_func decrypt_func;
-    mbedtls_pk_rsa_alt_sign_func sign_func;
-    mbedtls_pk_rsa_alt_key_len_func key_len_func;
-} mbedtls_rsa_alt_context;
-#endif
-
-#if defined(MBEDTLS_RSA_C)
-extern const mbedtls_pk_info_t mbedtls_rsa_info;
-#endif
-
-#if defined(MBEDTLS_ECP_C)
-extern const mbedtls_pk_info_t mbedtls_eckey_info;
-extern const mbedtls_pk_info_t mbedtls_eckeydh_info;
-#endif
-
-#if defined(MBEDTLS_ECDSA_C)
-extern const mbedtls_pk_info_t mbedtls_ecdsa_info;
-#endif
-
-#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT)
-extern const mbedtls_pk_info_t mbedtls_rsa_alt_info;
-#endif
-
-#endif /* MBEDTLS_PK_WRAP_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pkcs11.h b/tools/sdk/include/mbedtls/mbedtls/pkcs11.h
deleted file mode 100644
index e1446120c85..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/pkcs11.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/**
- * \file pkcs11.h
- *
- * \brief Wrapper for PKCS#11 library libpkcs11-helper
- *
- * \author Adriaan de Jong <dejong@fox-it.com>
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_PKCS11_H
-#define MBEDTLS_PKCS11_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_PKCS11_C)
-
-#include "x509_crt.h"
-
-#include <pkcs11-helper-1.0/pkcs11h-certificate.h>
-
-#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
-    !defined(inline) && !defined(__cplusplus)
-#define inline __inline
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Context for PKCS #11 private keys.
- */
-typedef struct mbedtls_pkcs11_context
-{
-        pkcs11h_certificate_t pkcs11h_cert;
-        int len;
-} mbedtls_pkcs11_context;
-
-/**
- * Initialize a mbedtls_pkcs11_context.
- * (Just making memory references valid.)
- */
-void mbedtls_pkcs11_init( mbedtls_pkcs11_context *ctx );
-
-/**
- * Fill in a mbed TLS certificate, based on the given PKCS11 helper certificate.
- *
- * \param cert          X.509 certificate to fill
- * \param pkcs11h_cert  PKCS #11 helper certificate
- *
- * \return              0 on success.
- */
-int mbedtls_pkcs11_x509_cert_bind( mbedtls_x509_crt *cert, pkcs11h_certificate_t pkcs11h_cert );
-
-/**
- * Set up a mbedtls_pkcs11_context storing the given certificate. Note that the
- * mbedtls_pkcs11_context will take over control of the certificate, freeing it when
- * done.
- *
- * \param priv_key      Private key structure to fill.
- * \param pkcs11_cert   PKCS #11 helper certificate
- *
- * \return              0 on success
- */
-int mbedtls_pkcs11_priv_key_bind( mbedtls_pkcs11_context *priv_key,
-        pkcs11h_certificate_t pkcs11_cert );
-
-/**
- * Free the contents of the given private key context. Note that the structure
- * itself is not freed.
- *
- * \param priv_key      Private key structure to cleanup
- */
-void mbedtls_pkcs11_priv_key_free( mbedtls_pkcs11_context *priv_key );
-
-/**
- * \brief          Do an RSA private key decrypt, then remove the message
- *                 padding
- *
- * \param ctx      PKCS #11 context
- * \param mode     must be MBEDTLS_RSA_PRIVATE, for compatibility with rsa.c's signature
- * \param input    buffer holding the encrypted data
- * \param output   buffer that will hold the plaintext
- * \param olen     will contain the plaintext length
- * \param output_max_len    maximum length of the output buffer
- *
- * \return         0 if successful, or an MBEDTLS_ERR_RSA_XXX error code
- *
- * \note           The output buffer must be as large as the size
- *                 of ctx->N (eg. 128 bytes if RSA-1024 is used) otherwise
- *                 an error is thrown.
- */
-int mbedtls_pkcs11_decrypt( mbedtls_pkcs11_context *ctx,
-                       int mode, size_t *olen,
-                       const unsigned char *input,
-                       unsigned char *output,
-                       size_t output_max_len );
-
-/**
- * \brief          Do a private RSA to sign a message digest
- *
- * \param ctx      PKCS #11 context
- * \param mode     must be MBEDTLS_RSA_PRIVATE, for compatibility with rsa.c's signature
- * \param md_alg   a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data)
- * \param hashlen  message digest length (for MBEDTLS_MD_NONE only)
- * \param hash     buffer holding the message digest
- * \param sig      buffer that will hold the ciphertext
- *
- * \return         0 if the signing operation was successful,
- *                 or an MBEDTLS_ERR_RSA_XXX error code
- *
- * \note           The "sig" buffer must be as large as the size
- *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
- */
-int mbedtls_pkcs11_sign( mbedtls_pkcs11_context *ctx,
-                    int mode,
-                    mbedtls_md_type_t md_alg,
-                    unsigned int hashlen,
-                    const unsigned char *hash,
-                    unsigned char *sig );
-
-/**
- * SSL/TLS wrappers for PKCS#11 functions
- */
-static inline int mbedtls_ssl_pkcs11_decrypt( void *ctx, int mode, size_t *olen,
-                        const unsigned char *input, unsigned char *output,
-                        size_t output_max_len )
-{
-    return mbedtls_pkcs11_decrypt( (mbedtls_pkcs11_context *) ctx, mode, olen, input, output,
-                           output_max_len );
-}
-
-static inline int mbedtls_ssl_pkcs11_sign( void *ctx,
-                     int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
-                     int mode, mbedtls_md_type_t md_alg, unsigned int hashlen,
-                     const unsigned char *hash, unsigned char *sig )
-{
-    ((void) f_rng);
-    ((void) p_rng);
-    return mbedtls_pkcs11_sign( (mbedtls_pkcs11_context *) ctx, mode, md_alg,
-                        hashlen, hash, sig );
-}
-
-static inline size_t mbedtls_ssl_pkcs11_key_len( void *ctx )
-{
-    return ( (mbedtls_pkcs11_context *) ctx )->len;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_PKCS11_C */
-
-#endif /* MBEDTLS_PKCS11_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pkcs12.h b/tools/sdk/include/mbedtls/mbedtls/pkcs12.h
deleted file mode 100644
index c418e8f243d..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/pkcs12.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/**
- * \file pkcs12.h
- *
- * \brief PKCS#12 Personal Information Exchange Syntax
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_PKCS12_H
-#define MBEDTLS_PKCS12_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "md.h"
-#include "cipher.h"
-#include "asn1.h"
-
-#include <stddef.h>
-
-#define MBEDTLS_ERR_PKCS12_BAD_INPUT_DATA                 -0x1F80  /**< Bad input parameters to function. */
-#define MBEDTLS_ERR_PKCS12_FEATURE_UNAVAILABLE            -0x1F00  /**< Feature not available, e.g. unsupported encryption scheme. */
-#define MBEDTLS_ERR_PKCS12_PBE_INVALID_FORMAT             -0x1E80  /**< PBE ASN.1 data not as expected. */
-#define MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH              -0x1E00  /**< Given private key password does not allow for correct decryption. */
-
-#define MBEDTLS_PKCS12_DERIVE_KEY       1   /**< encryption/decryption key */
-#define MBEDTLS_PKCS12_DERIVE_IV        2   /**< initialization vector     */
-#define MBEDTLS_PKCS12_DERIVE_MAC_KEY   3   /**< integrity / MAC key       */
-
-#define MBEDTLS_PKCS12_PBE_DECRYPT      0
-#define MBEDTLS_PKCS12_PBE_ENCRYPT      1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(MBEDTLS_ASN1_PARSE_C)
-
-/**
- * \brief            PKCS12 Password Based function (encryption / decryption)
- *                   for pbeWithSHAAnd128BitRC4
- *
- * \param pbe_params an ASN1 buffer containing the pkcs-12PbeParams structure
- * \param mode       either MBEDTLS_PKCS12_PBE_ENCRYPT or MBEDTLS_PKCS12_PBE_DECRYPT
- * \param pwd        the password used (may be NULL if no password is used)
- * \param pwdlen     length of the password (may be 0)
- * \param input      the input data
- * \param len        data length
- * \param output     the output buffer
- *
- * \return           0 if successful, or a MBEDTLS_ERR_XXX code
- */
-int mbedtls_pkcs12_pbe_sha1_rc4_128( mbedtls_asn1_buf *pbe_params, int mode,
-                             const unsigned char *pwd,  size_t pwdlen,
-                             const unsigned char *input, size_t len,
-                             unsigned char *output );
-
-/**
- * \brief            PKCS12 Password Based function (encryption / decryption)
- *                   for cipher-based and mbedtls_md-based PBE's
- *
- * \param pbe_params an ASN1 buffer containing the pkcs-12PbeParams structure
- * \param mode       either MBEDTLS_PKCS12_PBE_ENCRYPT or MBEDTLS_PKCS12_PBE_DECRYPT
- * \param cipher_type the cipher used
- * \param md_type     the mbedtls_md used
- * \param pwd        the password used (may be NULL if no password is used)
- * \param pwdlen     length of the password (may be 0)
- * \param input      the input data
- * \param len        data length
- * \param output     the output buffer
- *
- * \return           0 if successful, or a MBEDTLS_ERR_XXX code
- */
-int mbedtls_pkcs12_pbe( mbedtls_asn1_buf *pbe_params, int mode,
-                mbedtls_cipher_type_t cipher_type, mbedtls_md_type_t md_type,
-                const unsigned char *pwd,  size_t pwdlen,
-                const unsigned char *input, size_t len,
-                unsigned char *output );
-
-#endif /* MBEDTLS_ASN1_PARSE_C */
-
-/**
- * \brief            The PKCS#12 derivation function uses a password and a salt
- *                   to produce pseudo-random bits for a particular "purpose".
- *
- *                   Depending on the given id, this function can produce an
- *                   encryption/decryption key, an nitialization vector or an
- *                   integrity key.
- *
- * \param data       buffer to store the derived data in
- * \param datalen    length to fill
- * \param pwd        password to use (may be NULL if no password is used)
- * \param pwdlen     length of the password (may be 0)
- * \param salt       salt buffer to use
- * \param saltlen    length of the salt
- * \param mbedtls_md         mbedtls_md type to use during the derivation
- * \param id         id that describes the purpose (can be MBEDTLS_PKCS12_DERIVE_KEY,
- *                   MBEDTLS_PKCS12_DERIVE_IV or MBEDTLS_PKCS12_DERIVE_MAC_KEY)
- * \param iterations number of iterations
- *
- * \return          0 if successful, or a MD, BIGNUM type error.
- */
-int mbedtls_pkcs12_derivation( unsigned char *data, size_t datalen,
-                       const unsigned char *pwd, size_t pwdlen,
-                       const unsigned char *salt, size_t saltlen,
-                       mbedtls_md_type_t mbedtls_md, int id, int iterations );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* pkcs12.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/pkcs5.h b/tools/sdk/include/mbedtls/mbedtls/pkcs5.h
deleted file mode 100644
index c3f645aff1b..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/pkcs5.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/**
- * \file pkcs5.h
- *
- * \brief PKCS#5 functions
- *
- * \author Mathias Olsson <mathias@kompetensum.com>
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_PKCS5_H
-#define MBEDTLS_PKCS5_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "asn1.h"
-#include "md.h"
-
-#include <stddef.h>
-#include <stdint.h>
-
-#define MBEDTLS_ERR_PKCS5_BAD_INPUT_DATA                  -0x2f80  /**< Bad input parameters to function. */
-#define MBEDTLS_ERR_PKCS5_INVALID_FORMAT                  -0x2f00  /**< Unexpected ASN.1 data. */
-#define MBEDTLS_ERR_PKCS5_FEATURE_UNAVAILABLE             -0x2e80  /**< Requested encryption or digest alg not available. */
-#define MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH               -0x2e00  /**< Given private key password does not allow for correct decryption. */
-
-#define MBEDTLS_PKCS5_DECRYPT      0
-#define MBEDTLS_PKCS5_ENCRYPT      1
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(MBEDTLS_ASN1_PARSE_C)
-
-/**
- * \brief          PKCS#5 PBES2 function
- *
- * \param pbe_params the ASN.1 algorithm parameters
- * \param mode       either MBEDTLS_PKCS5_DECRYPT or MBEDTLS_PKCS5_ENCRYPT
- * \param pwd        password to use when generating key
- * \param pwdlen     length of password
- * \param data       data to process
- * \param datalen    length of data
- * \param output     output buffer
- *
- * \returns        0 on success, or a MBEDTLS_ERR_XXX code if verification fails.
- */
-int mbedtls_pkcs5_pbes2( const mbedtls_asn1_buf *pbe_params, int mode,
-                 const unsigned char *pwd,  size_t pwdlen,
-                 const unsigned char *data, size_t datalen,
-                 unsigned char *output );
-
-#endif /* MBEDTLS_ASN1_PARSE_C */
-
-/**
- * \brief          PKCS#5 PBKDF2 using HMAC
- *
- * \param ctx      Generic HMAC context
- * \param password Password to use when generating key
- * \param plen     Length of password
- * \param salt     Salt to use when generating key
- * \param slen     Length of salt
- * \param iteration_count       Iteration count
- * \param key_length            Length of generated key in bytes
- * \param output   Generated key. Must be at least as big as key_length
- *
- * \returns        0 on success, or a MBEDTLS_ERR_XXX code if verification fails.
- */
-int mbedtls_pkcs5_pbkdf2_hmac( mbedtls_md_context_t *ctx, const unsigned char *password,
-                       size_t plen, const unsigned char *salt, size_t slen,
-                       unsigned int iteration_count,
-                       uint32_t key_length, unsigned char *output );
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- */
-int mbedtls_pkcs5_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* pkcs5.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/platform.h b/tools/sdk/include/mbedtls/mbedtls/platform.h
deleted file mode 100644
index dcb5a88eebd..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/platform.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/**
- * \file platform.h
- *
- * \brief This file contains the definitions and functions of the
- *        Mbed TLS platform abstraction layer.
- *
- *        The platform abstraction layer removes the need for the library
- *        to directly link to standard C library functions or operating
- *        system services, making the library easier to port and embed.
- *        Application developers and users of the library can provide their own
- *        implementations of these functions, or implementations specific to
- *        their platform, which can be statically linked to the library or
- *        dynamically configured at runtime.
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_PLATFORM_H
-#define MBEDTLS_PLATFORM_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_HAVE_TIME)
-#include "platform_time.h"
-#endif
-
-#define MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED     -0x0070 /**< Hardware accelerator failed */
-#define MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED -0x0072 /**< The requested feature is not supported by the platform */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h or define them on the compiler command line.
- * \{
- */
-
-#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS)
-#include <stdio.h>
-#include <stdlib.h>
-#include <time.h>
-#if !defined(MBEDTLS_PLATFORM_STD_SNPRINTF)
-#if defined(_WIN32)
-#define MBEDTLS_PLATFORM_STD_SNPRINTF   mbedtls_platform_win32_snprintf /**< The default \c snprintf function to use.  */
-#else
-#define MBEDTLS_PLATFORM_STD_SNPRINTF   snprintf /**< The default \c snprintf function to use.  */
-#endif
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_PRINTF)
-#define MBEDTLS_PLATFORM_STD_PRINTF   printf /**< The default \c printf function to use. */
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_FPRINTF)
-#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< The default \c fprintf function to use. */
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_CALLOC)
-#define MBEDTLS_PLATFORM_STD_CALLOC   calloc /**< The default \c calloc function to use. */
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_FREE)
-#define MBEDTLS_PLATFORM_STD_FREE       free /**< The default \c free function to use. */
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_EXIT)
-#define MBEDTLS_PLATFORM_STD_EXIT      exit /**< The default \c exit function to use. */
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_TIME)
-#define MBEDTLS_PLATFORM_STD_TIME       time    /**< The default \c time function to use. */
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS)
-#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS  EXIT_SUCCESS /**< The default exit value to use. */
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE)
-#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE  EXIT_FAILURE /**< The default exit value to use. */
-#endif
-#if defined(MBEDTLS_FS_IO)
-#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ)
-#define MBEDTLS_PLATFORM_STD_NV_SEED_READ   mbedtls_platform_std_nv_seed_read
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE)
-#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE  mbedtls_platform_std_nv_seed_write
-#endif
-#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_FILE)
-#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE   "seedfile"
-#endif
-#endif /* MBEDTLS_FS_IO */
-#else /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */
-#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR)
-#include MBEDTLS_PLATFORM_STD_MEM_HDR
-#endif
-#endif /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */
-
-
-/* \} name SECTION: Module settings */
-
-/*
- * The function pointers for calloc and free.
- */
-#if defined(MBEDTLS_PLATFORM_MEMORY)
-#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && \
-    defined(MBEDTLS_PLATFORM_CALLOC_MACRO)
-#define mbedtls_free       MBEDTLS_PLATFORM_FREE_MACRO
-#define mbedtls_calloc     MBEDTLS_PLATFORM_CALLOC_MACRO
-#else
-/* For size_t */
-#include <stddef.h>
-extern void *mbedtls_calloc( size_t n, size_t size );
-extern void mbedtls_free( void *ptr );
-
-/**
- * \brief               This function dynamically sets the memory-management
- *                      functions used by the library, during runtime.
- *
- * \param calloc_func   The \c calloc function implementation.
- * \param free_func     The \c free function implementation.
- *
- * \return              \c 0.
- */
-int mbedtls_platform_set_calloc_free( void * (*calloc_func)( size_t, size_t ),
-                              void (*free_func)( void * ) );
-#endif /* MBEDTLS_PLATFORM_FREE_MACRO && MBEDTLS_PLATFORM_CALLOC_MACRO */
-#else /* !MBEDTLS_PLATFORM_MEMORY */
-#define mbedtls_free       free
-#define mbedtls_calloc     calloc
-#endif /* MBEDTLS_PLATFORM_MEMORY && !MBEDTLS_PLATFORM_{FREE,CALLOC}_MACRO */
-
-/*
- * The function pointers for fprintf
- */
-#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT)
-/* We need FILE * */
-#include <stdio.h>
-extern int (*mbedtls_fprintf)( FILE *stream, const char *format, ... );
-
-/**
- * \brief                This function dynamically configures the fprintf
- *                       function that is called when the
- *                       mbedtls_fprintf() function is invoked by the library.
- *
- * \param fprintf_func   The \c fprintf function implementation.
- *
- * \return               \c 0.
- */
-int mbedtls_platform_set_fprintf( int (*fprintf_func)( FILE *stream, const char *,
-                                               ... ) );
-#else
-#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO)
-#define mbedtls_fprintf    MBEDTLS_PLATFORM_FPRINTF_MACRO
-#else
-#define mbedtls_fprintf    fprintf
-#endif /* MBEDTLS_PLATFORM_FPRINTF_MACRO */
-#endif /* MBEDTLS_PLATFORM_FPRINTF_ALT */
-
-/*
- * The function pointers for printf
- */
-#if defined(MBEDTLS_PLATFORM_PRINTF_ALT)
-extern int (*mbedtls_printf)( const char *format, ... );
-
-/**
- * \brief               This function dynamically configures the snprintf
- *                      function that is called when the mbedtls_snprintf()
- *                      function is invoked by the library.
- *
- * \param printf_func   The \c printf function implementation.
- *
- * \return              \c 0 on success.
- */
-int mbedtls_platform_set_printf( int (*printf_func)( const char *, ... ) );
-#else /* !MBEDTLS_PLATFORM_PRINTF_ALT */
-#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO)
-#define mbedtls_printf     MBEDTLS_PLATFORM_PRINTF_MACRO
-#else
-#define mbedtls_printf     printf
-#endif /* MBEDTLS_PLATFORM_PRINTF_MACRO */
-#endif /* MBEDTLS_PLATFORM_PRINTF_ALT */
-
-/*
- * The function pointers for snprintf
- *
- * The snprintf implementation should conform to C99:
- * - it *must* always correctly zero-terminate the buffer
- *   (except when n == 0, then it must leave the buffer untouched)
- * - however it is acceptable to return -1 instead of the required length when
- *   the destination buffer is too short.
- */
-#if defined(_WIN32)
-/* For Windows (inc. MSYS2), we provide our own fixed implementation */
-int mbedtls_platform_win32_snprintf( char *s, size_t n, const char *fmt, ... );
-#endif
-
-#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT)
-extern int (*mbedtls_snprintf)( char * s, size_t n, const char * format, ... );
-
-/**
- * \brief                 This function allows configuring a custom
- *                        \c snprintf function pointer.
- *
- * \param snprintf_func   The \c snprintf function implementation.
- *
- * \return                \c 0 on success.
- */
-int mbedtls_platform_set_snprintf( int (*snprintf_func)( char * s, size_t n,
-                                                 const char * format, ... ) );
-#else /* MBEDTLS_PLATFORM_SNPRINTF_ALT */
-#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO)
-#define mbedtls_snprintf   MBEDTLS_PLATFORM_SNPRINTF_MACRO
-#else
-#define mbedtls_snprintf   MBEDTLS_PLATFORM_STD_SNPRINTF
-#endif /* MBEDTLS_PLATFORM_SNPRINTF_MACRO */
-#endif /* MBEDTLS_PLATFORM_SNPRINTF_ALT */
-
-/*
- * The function pointers for exit
- */
-#if defined(MBEDTLS_PLATFORM_EXIT_ALT)
-extern void (*mbedtls_exit)( int status );
-
-/**
- * \brief             This function dynamically configures the exit
- *                    function that is called when the mbedtls_exit()
- *                    function is invoked by the library.
- *
- * \param exit_func   The \c exit function implementation.
- *
- * \return            \c 0 on success.
- */
-int mbedtls_platform_set_exit( void (*exit_func)( int status ) );
-#else
-#if defined(MBEDTLS_PLATFORM_EXIT_MACRO)
-#define mbedtls_exit   MBEDTLS_PLATFORM_EXIT_MACRO
-#else
-#define mbedtls_exit   exit
-#endif /* MBEDTLS_PLATFORM_EXIT_MACRO */
-#endif /* MBEDTLS_PLATFORM_EXIT_ALT */
-
-/*
- * The default exit values
- */
-#if defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS)
-#define MBEDTLS_EXIT_SUCCESS MBEDTLS_PLATFORM_STD_EXIT_SUCCESS
-#else
-#define MBEDTLS_EXIT_SUCCESS 0
-#endif
-#if defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE)
-#define MBEDTLS_EXIT_FAILURE MBEDTLS_PLATFORM_STD_EXIT_FAILURE
-#else
-#define MBEDTLS_EXIT_FAILURE 1
-#endif
-
-/*
- * The function pointers for reading from and writing a seed file to
- * Non-Volatile storage (NV) in a platform-independent way
- *
- * Only enabled when the NV seed entropy source is enabled
- */
-#if defined(MBEDTLS_ENTROPY_NV_SEED)
-#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) && defined(MBEDTLS_FS_IO)
-/* Internal standard platform definitions */
-int mbedtls_platform_std_nv_seed_read( unsigned char *buf, size_t buf_len );
-int mbedtls_platform_std_nv_seed_write( unsigned char *buf, size_t buf_len );
-#endif
-
-#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT)
-extern int (*mbedtls_nv_seed_read)( unsigned char *buf, size_t buf_len );
-extern int (*mbedtls_nv_seed_write)( unsigned char *buf, size_t buf_len );
-
-/**
- * \brief   This function allows configuring custom seed file writing and
- *          reading functions.
- *
- * \param   nv_seed_read_func   The seed reading function implementation.
- * \param   nv_seed_write_func  The seed writing function implementation.
- *
- * \return  \c 0 on success.
- */
-int mbedtls_platform_set_nv_seed(
-            int (*nv_seed_read_func)( unsigned char *buf, size_t buf_len ),
-            int (*nv_seed_write_func)( unsigned char *buf, size_t buf_len )
-            );
-#else
-#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) && \
-    defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO)
-#define mbedtls_nv_seed_read    MBEDTLS_PLATFORM_NV_SEED_READ_MACRO
-#define mbedtls_nv_seed_write   MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO
-#else
-#define mbedtls_nv_seed_read    mbedtls_platform_std_nv_seed_read
-#define mbedtls_nv_seed_write   mbedtls_platform_std_nv_seed_write
-#endif
-#endif /* MBEDTLS_PLATFORM_NV_SEED_ALT */
-#endif /* MBEDTLS_ENTROPY_NV_SEED */
-
-#if !defined(MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT)
-
-/**
- * \brief   The platform context structure.
- *
- * \note    This structure may be used to assist platform-specific
- *          setup or teardown operations.
- */
-typedef struct mbedtls_platform_context
-{
-    char dummy; /**< A placeholder member, as empty structs are not portable. */
-}
-mbedtls_platform_context;
-
-#else
-#include "platform_alt.h"
-#endif /* !MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT */
-
-/**
- * \brief   This function performs any platform-specific initialization
- *          operations.
- *
- * \note    This function should be called before any other library functions.
- *
- *          Its implementation is platform-specific, and unless
- *          platform-specific code is provided, it does nothing.
- *
- * \note    The usage and necessity of this function is dependent on the platform.
- *
- * \param   ctx     The platform context.
- *
- * \return  \c 0 on success.
- */
-int mbedtls_platform_setup( mbedtls_platform_context *ctx );
-/**
- * \brief   This function performs any platform teardown operations.
- *
- * \note    This function should be called after every other Mbed TLS module
- *          has been correctly freed using the appropriate free function.
- *
- *          Its implementation is platform-specific, and unless
- *          platform-specific code is provided, it does nothing.
- *
- * \note    The usage and necessity of this function is dependent on the platform.
- *
- * \param   ctx     The platform context.
- *
- */
-void mbedtls_platform_teardown( mbedtls_platform_context *ctx );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* platform.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/platform_time.h b/tools/sdk/include/mbedtls/mbedtls/platform_time.h
deleted file mode 100644
index a45870c3a65..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/platform_time.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file platform_time.h
- *
- * \brief mbed TLS Platform time abstraction
- */
-/*
- *  Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_PLATFORM_TIME_H
-#define MBEDTLS_PLATFORM_TIME_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h or define them on the compiler command line.
- * \{
- */
-
-/*
- * The time_t datatype
- */
-#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO)
-typedef MBEDTLS_PLATFORM_TIME_TYPE_MACRO mbedtls_time_t;
-#else
-/* For time_t */
-#include <time.h>
-typedef time_t mbedtls_time_t;
-#endif /* MBEDTLS_PLATFORM_TIME_TYPE_MACRO */
-
-/*
- * The function pointers for time
- */
-#if defined(MBEDTLS_PLATFORM_TIME_ALT)
-extern mbedtls_time_t (*mbedtls_time)( mbedtls_time_t* time );
-
-/**
- * \brief   Set your own time function pointer
- *
- * \param   time_func   the time function implementation
- *
- * \return              0
- */
-int mbedtls_platform_set_time( mbedtls_time_t (*time_func)( mbedtls_time_t* time ) );
-#else
-#if defined(MBEDTLS_PLATFORM_TIME_MACRO)
-#define mbedtls_time    MBEDTLS_PLATFORM_TIME_MACRO
-#else
-#define mbedtls_time   time
-#endif /* MBEDTLS_PLATFORM_TIME_MACRO */
-#endif /* MBEDTLS_PLATFORM_TIME_ALT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* platform_time.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/platform_util.h b/tools/sdk/include/mbedtls/mbedtls/platform_util.h
deleted file mode 100644
index f10574afe6f..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/platform_util.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/**
- * \file platform_util.h
- *
- * \brief Common and shared functions used by multiple modules in the Mbed TLS
- *        library.
- */
-/*
- *  Copyright (C) 2018, Arm Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_PLATFORM_UTIL_H
-#define MBEDTLS_PLATFORM_UTIL_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#if defined(MBEDTLS_HAVE_TIME_DATE)
-#include "platform_time.h"
-#include <time.h>
-#endif /* MBEDTLS_HAVE_TIME_DATE */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(MBEDTLS_CHECK_PARAMS)
-
-#if defined(MBEDTLS_CHECK_PARAMS_ASSERT)
-/* Allow the user to define MBEDTLS_PARAM_FAILED to something like assert
- * (which is what our config.h suggests). */
-#include <assert.h>
-#endif /* MBEDTLS_CHECK_PARAMS_ASSERT */
-
-#if defined(MBEDTLS_PARAM_FAILED)
-/** An alternative definition of MBEDTLS_PARAM_FAILED has been set in config.h.
- *
- * This flag can be used to check whether it is safe to assume that
- * MBEDTLS_PARAM_FAILED() will expand to a call to mbedtls_param_failed().
- */
-#define MBEDTLS_PARAM_FAILED_ALT
-
-#elif defined(MBEDTLS_CHECK_PARAMS_ASSERT)
-#define MBEDTLS_PARAM_FAILED( cond ) assert( cond )
-#define MBEDTLS_PARAM_FAILED_ALT
-
-#else /* MBEDTLS_PARAM_FAILED */
-#define MBEDTLS_PARAM_FAILED( cond ) \
-    mbedtls_param_failed( #cond, __FILE__, __LINE__ )
-
-/**
- * \brief       User supplied callback function for parameter validation failure.
- *              See #MBEDTLS_CHECK_PARAMS for context.
- *
- *              This function will be called unless an alternative treatement
- *              is defined through the #MBEDTLS_PARAM_FAILED macro.
- *
- *              This function can return, and the operation will be aborted, or
- *              alternatively, through use of setjmp()/longjmp() can resume
- *              execution in the application code.
- *
- * \param failure_condition The assertion that didn't hold.
- * \param file  The file where the assertion failed.
- * \param line  The line in the file where the assertion failed.
- */
-void mbedtls_param_failed( const char *failure_condition,
-                           const char *file,
-                           int line );
-#endif /* MBEDTLS_PARAM_FAILED */
-
-/* Internal macro meant to be called only from within the library. */
-#define MBEDTLS_INTERNAL_VALIDATE_RET( cond, ret )  \
-    do {                                            \
-        if( !(cond) )                               \
-        {                                           \
-            MBEDTLS_PARAM_FAILED( cond );           \
-            return( ret );                          \
-        }                                           \
-    } while( 0 )
-
-/* Internal macro meant to be called only from within the library. */
-#define MBEDTLS_INTERNAL_VALIDATE( cond )           \
-    do {                                            \
-        if( !(cond) )                               \
-        {                                           \
-            MBEDTLS_PARAM_FAILED( cond );           \
-            return;                                 \
-        }                                           \
-    } while( 0 )
-
-#else /* MBEDTLS_CHECK_PARAMS */
-
-/* Internal macros meant to be called only from within the library. */
-#define MBEDTLS_INTERNAL_VALIDATE_RET( cond, ret )  do { } while( 0 )
-#define MBEDTLS_INTERNAL_VALIDATE( cond )           do { } while( 0 )
-
-#endif /* MBEDTLS_CHECK_PARAMS */
-
-/* Internal helper macros for deprecating API constants. */
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-/* Deliberately don't (yet) export MBEDTLS_DEPRECATED here
- * to avoid conflict with other headers which define and use
- * it, too. We might want to move all these definitions here at
- * some point for uniformity. */
-#define MBEDTLS_DEPRECATED __attribute__((deprecated))
-MBEDTLS_DEPRECATED typedef char const * mbedtls_deprecated_string_constant_t;
-#define MBEDTLS_DEPRECATED_STRING_CONSTANT( VAL )       \
-    ( (mbedtls_deprecated_string_constant_t) ( VAL ) )
-MBEDTLS_DEPRECATED typedef int mbedtls_deprecated_numeric_constant_t;
-#define MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( VAL )       \
-    ( (mbedtls_deprecated_numeric_constant_t) ( VAL ) )
-#undef MBEDTLS_DEPRECATED
-#else /* MBEDTLS_DEPRECATED_WARNING */
-#define MBEDTLS_DEPRECATED_STRING_CONSTANT( VAL ) VAL
-#define MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( VAL ) VAL
-#endif /* MBEDTLS_DEPRECATED_WARNING */
-#endif /* MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief       Securely zeroize a buffer
- *
- *              The function is meant to wipe the data contained in a buffer so
- *              that it can no longer be recovered even if the program memory
- *              is later compromised. Call this function on sensitive data
- *              stored on the stack before returning from a function, and on
- *              sensitive data stored on the heap before freeing the heap
- *              object.
- *
- *              It is extremely difficult to guarantee that calls to
- *              mbedtls_platform_zeroize() are not removed by aggressive
- *              compiler optimizations in a portable way. For this reason, Mbed
- *              TLS provides the configuration option
- *              MBEDTLS_PLATFORM_ZEROIZE_ALT, which allows users to configure
- *              mbedtls_platform_zeroize() to use a suitable implementation for
- *              their platform and needs
- *
- * \param buf   Buffer to be zeroized
- * \param len   Length of the buffer in bytes
- *
- */
-void mbedtls_platform_zeroize( void *buf, size_t len );
-
-#if defined(MBEDTLS_HAVE_TIME_DATE)
-/**
- * \brief      Platform-specific implementation of gmtime_r()
- *
- *             The function is a thread-safe abstraction that behaves
- *             similarly to the gmtime_r() function from Unix/POSIX.
- *
- *             Mbed TLS will try to identify the underlying platform and
- *             make use of an appropriate underlying implementation (e.g.
- *             gmtime_r() for POSIX and gmtime_s() for Windows). If this is
- *             not possible, then gmtime() will be used. In this case, calls
- *             from the library to gmtime() will be guarded by the mutex
- *             mbedtls_threading_gmtime_mutex if MBEDTLS_THREADING_C is
- *             enabled. It is recommended that calls from outside the library
- *             are also guarded by this mutex.
- *
- *             If MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, then Mbed TLS will
- *             unconditionally use the alternative implementation for
- *             mbedtls_platform_gmtime_r() supplied by the user at compile time.
- *
- * \param tt     Pointer to an object containing time (in seconds) since the
- *               epoch to be converted
- * \param tm_buf Pointer to an object where the results will be stored
- *
- * \return      Pointer to an object of type struct tm on success, otherwise
- *              NULL
- */
-struct tm *mbedtls_platform_gmtime_r( const mbedtls_time_t *tt,
-                                      struct tm *tm_buf );
-#endif /* MBEDTLS_HAVE_TIME_DATE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_PLATFORM_UTIL_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/poly1305.h b/tools/sdk/include/mbedtls/mbedtls/poly1305.h
deleted file mode 100644
index 6e45b2c2ba0..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/poly1305.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/**
- * \file poly1305.h
- *
- * \brief   This file contains Poly1305 definitions and functions.
- *
- *          Poly1305 is a one-time message authenticator that can be used to
- *          authenticate messages. Poly1305-AES was created by Daniel
- *          Bernstein https://cr.yp.to/mac/poly1305-20050329.pdf The generic
- *          Poly1305 algorithm (not tied to AES) was also standardized in RFC
- *          7539.
- *
- * \author Daniel King <damaki.gh@gmail.com>
- */
-
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved.
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-
-#ifndef MBEDTLS_POLY1305_H
-#define MBEDTLS_POLY1305_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stdint.h>
-#include <stddef.h>
-
-#define MBEDTLS_ERR_POLY1305_BAD_INPUT_DATA         -0x0057 /**< Invalid input parameter(s). */
-
-/* MBEDTLS_ERR_POLY1305_FEATURE_UNAVAILABLE is deprecated and should not be
- * used. */
-#define MBEDTLS_ERR_POLY1305_FEATURE_UNAVAILABLE    -0x0059 /**< Feature not available. For example, s part of the API is not implemented. */
-
-/* MBEDTLS_ERR_POLY1305_HW_ACCEL_FAILED is deprecated and should not be used.
- */
-#define MBEDTLS_ERR_POLY1305_HW_ACCEL_FAILED        -0x005B  /**< Poly1305 hardware accelerator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_POLY1305_ALT)
-
-typedef struct mbedtls_poly1305_context
-{
-    uint32_t r[4];      /** The value for 'r' (low 128 bits of the key). */
-    uint32_t s[4];      /** The value for 's' (high 128 bits of the key). */
-    uint32_t acc[5];    /** The accumulator number. */
-    uint8_t queue[16];  /** The current partial block of data. */
-    size_t queue_len;   /** The number of bytes stored in 'queue'. */
-}
-mbedtls_poly1305_context;
-
-#else  /* MBEDTLS_POLY1305_ALT */
-#include "poly1305_alt.h"
-#endif /* MBEDTLS_POLY1305_ALT */
-
-/**
- * \brief           This function initializes the specified Poly1305 context.
- *
- *                  It must be the first API called before using
- *                  the context.
- *
- *                  It is usually followed by a call to
- *                  \c mbedtls_poly1305_starts(), then one or more calls to
- *                  \c mbedtls_poly1305_update(), then one call to
- *                  \c mbedtls_poly1305_finish(), then finally
- *                  \c mbedtls_poly1305_free().
- *
- * \param ctx       The Poly1305 context to initialize. This must
- *                  not be \c NULL.
- */
-void mbedtls_poly1305_init( mbedtls_poly1305_context *ctx );
-
-/**
- * \brief           This function releases and clears the specified
- *                  Poly1305 context.
- *
- * \param ctx       The Poly1305 context to clear. This may be \c NULL, in which
- *                  case this function is a no-op. If it is not \c NULL, it must
- *                  point to an initialized Poly1305 context.
- */
-void mbedtls_poly1305_free( mbedtls_poly1305_context *ctx );
-
-/**
- * \brief           This function sets the one-time authentication key.
- *
- * \warning         The key must be unique and unpredictable for each
- *                  invocation of Poly1305.
- *
- * \param ctx       The Poly1305 context to which the key should be bound.
- *                  This must be initialized.
- * \param key       The buffer containing the \c 32 Byte (\c 256 Bit) key.
- *
- * \return          \c 0 on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_poly1305_starts( mbedtls_poly1305_context *ctx,
-                             const unsigned char key[32] );
-
-/**
- * \brief           This functions feeds an input buffer into an ongoing
- *                  Poly1305 computation.
- *
- *                  It is called between \c mbedtls_cipher_poly1305_starts() and
- *                  \c mbedtls_cipher_poly1305_finish().
- *                  It can be called repeatedly to process a stream of data.
- *
- * \param ctx       The Poly1305 context to use for the Poly1305 operation.
- *                  This must be initialized and bound to a key.
- * \param ilen      The length of the input data in Bytes.
- *                  Any value is accepted.
- * \param input     The buffer holding the input data.
- *                  This pointer can be \c NULL if `ilen == 0`.
- *
- * \return          \c 0 on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_poly1305_update( mbedtls_poly1305_context *ctx,
-                             const unsigned char *input,
-                             size_t ilen );
-
-/**
- * \brief           This function generates the Poly1305 Message
- *                  Authentication Code (MAC).
- *
- * \param ctx       The Poly1305 context to use for the Poly1305 operation.
- *                  This must be initialized and bound to a key.
- * \param mac       The buffer to where the MAC is written. This must
- *                  be a writable buffer of length \c 16 Bytes.
- *
- * \return          \c 0 on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_poly1305_finish( mbedtls_poly1305_context *ctx,
-                             unsigned char mac[16] );
-
-/**
- * \brief           This function calculates the Poly1305 MAC of the input
- *                  buffer with the provided key.
- *
- * \warning         The key must be unique and unpredictable for each
- *                  invocation of Poly1305.
- *
- * \param key       The buffer containing the \c 32 Byte (\c 256 Bit) key.
- * \param ilen      The length of the input data in Bytes.
- *                  Any value is accepted.
- * \param input     The buffer holding the input data.
- *                  This pointer can be \c NULL if `ilen == 0`.
- * \param mac       The buffer to where the MAC is written. This must be
- *                  a writable buffer of length \c 16 Bytes.
- *
- * \return          \c 0 on success.
- * \return          A negative error code on failure.
- */
-int mbedtls_poly1305_mac( const unsigned char key[32],
-                          const unsigned char *input,
-                          size_t ilen,
-                          unsigned char mac[16] );
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief           The Poly1305 checkup routine.
- *
- * \return          \c 0 on success.
- * \return          \c 1 on failure.
- */
-int mbedtls_poly1305_self_test( int verbose );
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_POLY1305_H */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ripemd160.h b/tools/sdk/include/mbedtls/mbedtls/ripemd160.h
deleted file mode 100644
index 505c39252e5..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ripemd160.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/**
- * \file ripemd160.h
- *
- * \brief RIPE MD-160 message digest
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_RIPEMD160_H
-#define MBEDTLS_RIPEMD160_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* MBEDTLS_ERR_RIPEMD160_HW_ACCEL_FAILED is deprecated and should not be used.
- */
-#define MBEDTLS_ERR_RIPEMD160_HW_ACCEL_FAILED             -0x0031  /**< RIPEMD160 hardware accelerator failed */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_RIPEMD160_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          RIPEMD-160 context structure
- */
-typedef struct mbedtls_ripemd160_context
-{
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[5];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-}
-mbedtls_ripemd160_context;
-
-#else  /* MBEDTLS_RIPEMD160_ALT */
-#include "ripemd160.h"
-#endif /* MBEDTLS_RIPEMD160_ALT */
-
-/**
- * \brief          Initialize RIPEMD-160 context
- *
- * \param ctx      RIPEMD-160 context to be initialized
- */
-void mbedtls_ripemd160_init( mbedtls_ripemd160_context *ctx );
-
-/**
- * \brief          Clear RIPEMD-160 context
- *
- * \param ctx      RIPEMD-160 context to be cleared
- */
-void mbedtls_ripemd160_free( mbedtls_ripemd160_context *ctx );
-
-/**
- * \brief          Clone (the state of) an RIPEMD-160 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void mbedtls_ripemd160_clone( mbedtls_ripemd160_context *dst,
-                        const mbedtls_ripemd160_context *src );
-
-/**
- * \brief          RIPEMD-160 context setup
- *
- * \param ctx      context to be initialized
- *
- * \return         0 if successful
- */
-int mbedtls_ripemd160_starts_ret( mbedtls_ripemd160_context *ctx );
-
-/**
- * \brief          RIPEMD-160 process buffer
- *
- * \param ctx      RIPEMD-160 context
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- *
- * \return         0 if successful
- */
-int mbedtls_ripemd160_update_ret( mbedtls_ripemd160_context *ctx,
-                                  const unsigned char *input,
-                                  size_t ilen );
-
-/**
- * \brief          RIPEMD-160 final digest
- *
- * \param ctx      RIPEMD-160 context
- * \param output   RIPEMD-160 checksum result
- *
- * \return         0 if successful
- */
-int mbedtls_ripemd160_finish_ret( mbedtls_ripemd160_context *ctx,
-                                  unsigned char output[20] );
-
-/**
- * \brief          RIPEMD-160 process data block (internal use only)
- *
- * \param ctx      RIPEMD-160 context
- * \param data     buffer holding one block of data
- *
- * \return         0 if successful
- */
-int mbedtls_internal_ripemd160_process( mbedtls_ripemd160_context *ctx,
-                                        const unsigned char data[64] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          RIPEMD-160 context setup
- *
- * \deprecated     Superseded by mbedtls_ripemd160_starts_ret() in 2.7.0
- *
- * \param ctx      context to be initialized
- */
-MBEDTLS_DEPRECATED void mbedtls_ripemd160_starts(
-                                            mbedtls_ripemd160_context *ctx );
-
-/**
- * \brief          RIPEMD-160 process buffer
- *
- * \deprecated     Superseded by mbedtls_ripemd160_update_ret() in 2.7.0
- *
- * \param ctx      RIPEMD-160 context
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- */
-MBEDTLS_DEPRECATED void mbedtls_ripemd160_update(
-                                                mbedtls_ripemd160_context *ctx,
-                                                const unsigned char *input,
-                                                size_t ilen );
-
-/**
- * \brief          RIPEMD-160 final digest
- *
- * \deprecated     Superseded by mbedtls_ripemd160_finish_ret() in 2.7.0
- *
- * \param ctx      RIPEMD-160 context
- * \param output   RIPEMD-160 checksum result
- */
-MBEDTLS_DEPRECATED void mbedtls_ripemd160_finish(
-                                                mbedtls_ripemd160_context *ctx,
-                                                unsigned char output[20] );
-
-/**
- * \brief          RIPEMD-160 process data block (internal use only)
- *
- * \deprecated     Superseded by mbedtls_internal_ripemd160_process() in 2.7.0
- *
- * \param ctx      RIPEMD-160 context
- * \param data     buffer holding one block of data
- */
-MBEDTLS_DEPRECATED void mbedtls_ripemd160_process(
-                                            mbedtls_ripemd160_context *ctx,
-                                            const unsigned char data[64] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief          Output = RIPEMD-160( input buffer )
- *
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- * \param output   RIPEMD-160 checksum result
- *
- * \return         0 if successful
- */
-int mbedtls_ripemd160_ret( const unsigned char *input,
-                           size_t ilen,
-                           unsigned char output[20] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          Output = RIPEMD-160( input buffer )
- *
- * \deprecated     Superseded by mbedtls_ripemd160_ret() in 2.7.0
- *
- * \param input    buffer holding the data
- * \param ilen     length of the input data
- * \param output   RIPEMD-160 checksum result
- */
-MBEDTLS_DEPRECATED void mbedtls_ripemd160( const unsigned char *input,
-                                           size_t ilen,
-                                           unsigned char output[20] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- */
-int mbedtls_ripemd160_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_ripemd160.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/rsa.h b/tools/sdk/include/mbedtls/mbedtls/rsa.h
deleted file mode 100644
index cd22fc4c1fb..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/rsa.h
+++ /dev/null
@@ -1,1301 +0,0 @@
-/**
- * \file rsa.h
- *
- * \brief This file provides an API for the RSA public-key cryptosystem.
- *
- * The RSA public-key cryptosystem is defined in <em>Public-Key
- * Cryptography Standards (PKCS) #1 v1.5: RSA Encryption</em>
- * and <em>Public-Key Cryptography Standards (PKCS) #1 v2.1:
- * RSA Cryptography Specifications</em>.
- *
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_RSA_H
-#define MBEDTLS_RSA_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "bignum.h"
-#include "md.h"
-
-#if defined(MBEDTLS_THREADING_C)
-#include "threading.h"
-#endif
-
-/*
- * RSA Error codes
- */
-#define MBEDTLS_ERR_RSA_BAD_INPUT_DATA                    -0x4080  /**< Bad input parameters to function. */
-#define MBEDTLS_ERR_RSA_INVALID_PADDING                   -0x4100  /**< Input data contains invalid padding and is rejected. */
-#define MBEDTLS_ERR_RSA_KEY_GEN_FAILED                    -0x4180  /**< Something failed during generation of a key. */
-#define MBEDTLS_ERR_RSA_KEY_CHECK_FAILED                  -0x4200  /**< Key failed to pass the validity check of the library. */
-#define MBEDTLS_ERR_RSA_PUBLIC_FAILED                     -0x4280  /**< The public key operation failed. */
-#define MBEDTLS_ERR_RSA_PRIVATE_FAILED                    -0x4300  /**< The private key operation failed. */
-#define MBEDTLS_ERR_RSA_VERIFY_FAILED                     -0x4380  /**< The PKCS#1 verification failed. */
-#define MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE                  -0x4400  /**< The output buffer for decryption is not large enough. */
-#define MBEDTLS_ERR_RSA_RNG_FAILED                        -0x4480  /**< The random generator failed to generate non-zeros. */
-
-/* MBEDTLS_ERR_RSA_UNSUPPORTED_OPERATION is deprecated and should not be used.
- */
-#define MBEDTLS_ERR_RSA_UNSUPPORTED_OPERATION             -0x4500  /**< The implementation does not offer the requested operation, for example, because of security violations or lack of functionality. */
-
-/* MBEDTLS_ERR_RSA_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_RSA_HW_ACCEL_FAILED                   -0x4580  /**< RSA hardware accelerator failed. */
-
-/*
- * RSA constants
- */
-#define MBEDTLS_RSA_PUBLIC      0 /**< Request private key operation. */
-#define MBEDTLS_RSA_PRIVATE     1 /**< Request public key operation. */
-
-#define MBEDTLS_RSA_PKCS_V15    0 /**< Use PKCS#1 v1.5 encoding. */
-#define MBEDTLS_RSA_PKCS_V21    1 /**< Use PKCS#1 v2.1 encoding. */
-
-#define MBEDTLS_RSA_SIGN        1 /**< Identifier for RSA signature operations. */
-#define MBEDTLS_RSA_CRYPT       2 /**< Identifier for RSA encryption and decryption operations. */
-
-#define MBEDTLS_RSA_SALT_LEN_ANY    -1
-
-/*
- * The above constants may be used even if the RSA module is compile out,
- * eg for alternative (PKCS#11) RSA implemenations in the PK layers.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_RSA_ALT)
-// Regular implementation
-//
-
-/**
- * \brief   The RSA context structure.
- *
- * \note    Direct manipulation of the members of this structure
- *          is deprecated. All manipulation should instead be done through
- *          the public interface functions.
- */
-typedef struct mbedtls_rsa_context
-{
-    int ver;                    /*!<  Always 0.*/
-    size_t len;                 /*!<  The size of \p N in Bytes. */
-
-    mbedtls_mpi N;              /*!<  The public modulus. */
-    mbedtls_mpi E;              /*!<  The public exponent. */
-
-    mbedtls_mpi D;              /*!<  The private exponent. */
-    mbedtls_mpi P;              /*!<  The first prime factor. */
-    mbedtls_mpi Q;              /*!<  The second prime factor. */
-
-    mbedtls_mpi DP;             /*!<  <code>D % (P - 1)</code>. */
-    mbedtls_mpi DQ;             /*!<  <code>D % (Q - 1)</code>. */
-    mbedtls_mpi QP;             /*!<  <code>1 / (Q % P)</code>. */
-
-    mbedtls_mpi RN;             /*!<  cached <code>R^2 mod N</code>. */
-
-    mbedtls_mpi RP;             /*!<  cached <code>R^2 mod P</code>. */
-    mbedtls_mpi RQ;             /*!<  cached <code>R^2 mod Q</code>. */
-
-    mbedtls_mpi Vi;             /*!<  The cached blinding value. */
-    mbedtls_mpi Vf;             /*!<  The cached un-blinding value. */
-
-    int padding;                /*!< Selects padding mode:
-                                     #MBEDTLS_RSA_PKCS_V15 for 1.5 padding and
-                                     #MBEDTLS_RSA_PKCS_V21 for OAEP or PSS. */
-    int hash_id;                /*!< Hash identifier of mbedtls_md_type_t type,
-                                     as specified in md.h for use in the MGF
-                                     mask generating function used in the
-                                     EME-OAEP and EMSA-PSS encodings. */
-#if defined(MBEDTLS_THREADING_C)
-    mbedtls_threading_mutex_t mutex;    /*!<  Thread-safety mutex. */
-#endif
-}
-mbedtls_rsa_context;
-
-#else  /* MBEDTLS_RSA_ALT */
-#include "rsa_alt.h"
-#endif /* MBEDTLS_RSA_ALT */
-
-/**
- * \brief          This function initializes an RSA context.
- *
- * \note           Set padding to #MBEDTLS_RSA_PKCS_V21 for the RSAES-OAEP
- *                 encryption scheme and the RSASSA-PSS signature scheme.
- *
- * \note           The \p hash_id parameter is ignored when using
- *                 #MBEDTLS_RSA_PKCS_V15 padding.
- *
- * \note           The choice of padding mode is strictly enforced for private key
- *                 operations, since there might be security concerns in
- *                 mixing padding modes. For public key operations it is
- *                 a default value, which can be overridden by calling specific
- *                 \c rsa_rsaes_xxx or \c rsa_rsassa_xxx functions.
- *
- * \note           The hash selected in \p hash_id is always used for OEAP
- *                 encryption. For PSS signatures, it is always used for
- *                 making signatures, but can be overridden for verifying them.
- *                 If set to #MBEDTLS_MD_NONE, it is always overridden.
- *
- * \param ctx      The RSA context to initialize. This must not be \c NULL.
- * \param padding  The padding mode to use. This must be either
- *                 #MBEDTLS_RSA_PKCS_V15 or #MBEDTLS_RSA_PKCS_V21.
- * \param hash_id  The hash identifier of ::mbedtls_md_type_t type, if
- *                 \p padding is #MBEDTLS_RSA_PKCS_V21. It is unused
- *                 otherwise.
- */
-void mbedtls_rsa_init( mbedtls_rsa_context *ctx,
-                       int padding,
-                       int hash_id );
-
-/**
- * \brief          This function imports a set of core parameters into an
- *                 RSA context.
- *
- * \note           This function can be called multiple times for successive
- *                 imports, if the parameters are not simultaneously present.
- *
- *                 Any sequence of calls to this function should be followed
- *                 by a call to mbedtls_rsa_complete(), which checks and
- *                 completes the provided information to a ready-for-use
- *                 public or private RSA key.
- *
- * \note           See mbedtls_rsa_complete() for more information on which
- *                 parameters are necessary to set up a private or public
- *                 RSA key.
- *
- * \note           The imported parameters are copied and need not be preserved
- *                 for the lifetime of the RSA context being set up.
- *
- * \param ctx      The initialized RSA context to store the parameters in.
- * \param N        The RSA modulus. This may be \c NULL.
- * \param P        The first prime factor of \p N. This may be \c NULL.
- * \param Q        The second prime factor of \p N. This may be \c NULL.
- * \param D        The private exponent. This may be \c NULL.
- * \param E        The public exponent. This may be \c NULL.
- *
- * \return         \c 0 on success.
- * \return         A non-zero error code on failure.
- */
-int mbedtls_rsa_import( mbedtls_rsa_context *ctx,
-                        const mbedtls_mpi *N,
-                        const mbedtls_mpi *P, const mbedtls_mpi *Q,
-                        const mbedtls_mpi *D, const mbedtls_mpi *E );
-
-/**
- * \brief          This function imports core RSA parameters, in raw big-endian
- *                 binary format, into an RSA context.
- *
- * \note           This function can be called multiple times for successive
- *                 imports, if the parameters are not simultaneously present.
- *
- *                 Any sequence of calls to this function should be followed
- *                 by a call to mbedtls_rsa_complete(), which checks and
- *                 completes the provided information to a ready-for-use
- *                 public or private RSA key.
- *
- * \note           See mbedtls_rsa_complete() for more information on which
- *                 parameters are necessary to set up a private or public
- *                 RSA key.
- *
- * \note           The imported parameters are copied and need not be preserved
- *                 for the lifetime of the RSA context being set up.
- *
- * \param ctx      The initialized RSA context to store the parameters in.
- * \param N        The RSA modulus. This may be \c NULL.
- * \param N_len    The Byte length of \p N; it is ignored if \p N == NULL.
- * \param P        The first prime factor of \p N. This may be \c NULL.
- * \param P_len    The Byte length of \p P; it ns ignored if \p P == NULL.
- * \param Q        The second prime factor of \p N. This may be \c NULL.
- * \param Q_len    The Byte length of \p Q; it is ignored if \p Q == NULL.
- * \param D        The private exponent. This may be \c NULL.
- * \param D_len    The Byte length of \p D; it is ignored if \p D == NULL.
- * \param E        The public exponent. This may be \c NULL.
- * \param E_len    The Byte length of \p E; it is ignored if \p E == NULL.
- *
- * \return         \c 0 on success.
- * \return         A non-zero error code on failure.
- */
-int mbedtls_rsa_import_raw( mbedtls_rsa_context *ctx,
-                            unsigned char const *N, size_t N_len,
-                            unsigned char const *P, size_t P_len,
-                            unsigned char const *Q, size_t Q_len,
-                            unsigned char const *D, size_t D_len,
-                            unsigned char const *E, size_t E_len );
-
-/**
- * \brief          This function completes an RSA context from
- *                 a set of imported core parameters.
- *
- *                 To setup an RSA public key, precisely \p N and \p E
- *                 must have been imported.
- *
- *                 To setup an RSA private key, sufficient information must
- *                 be present for the other parameters to be derivable.
- *
- *                 The default implementation supports the following:
- *                 <ul><li>Derive \p P, \p Q from \p N, \p D, \p E.</li>
- *                 <li>Derive \p N, \p D from \p P, \p Q, \p E.</li></ul>
- *                 Alternative implementations need not support these.
- *
- *                 If this function runs successfully, it guarantees that
- *                 the RSA context can be used for RSA operations without
- *                 the risk of failure or crash.
- *
- * \warning        This function need not perform consistency checks
- *                 for the imported parameters. In particular, parameters that
- *                 are not needed by the implementation might be silently
- *                 discarded and left unchecked. To check the consistency
- *                 of the key material, see mbedtls_rsa_check_privkey().
- *
- * \param ctx      The initialized RSA context holding imported parameters.
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_RSA_BAD_INPUT_DATA if the attempted derivations
- *                 failed.
- *
- */
-int mbedtls_rsa_complete( mbedtls_rsa_context *ctx );
-
-/**
- * \brief          This function exports the core parameters of an RSA key.
- *
- *                 If this function runs successfully, the non-NULL buffers
- *                 pointed to by \p N, \p P, \p Q, \p D, and \p E are fully
- *                 written, with additional unused space filled leading by
- *                 zero Bytes.
- *
- *                 Possible reasons for returning
- *                 #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED:<ul>
- *                 <li>An alternative RSA implementation is in use, which
- *                 stores the key externally, and either cannot or should
- *                 not export it into RAM.</li>
- *                 <li>A SW or HW implementation might not support a certain
- *                 deduction. For example, \p P, \p Q from \p N, \p D,
- *                 and \p E if the former are not part of the
- *                 implementation.</li></ul>
- *
- *                 If the function fails due to an unsupported operation,
- *                 the RSA context stays intact and remains usable.
- *
- * \param ctx      The initialized RSA context.
- * \param N        The MPI to hold the RSA modulus.
- *                 This may be \c NULL if this field need not be exported.
- * \param P        The MPI to hold the first prime factor of \p N.
- *                 This may be \c NULL if this field need not be exported.
- * \param Q        The MPI to hold the second prime factor of \p N.
- *                 This may be \c NULL if this field need not be exported.
- * \param D        The MPI to hold the private exponent.
- *                 This may be \c NULL if this field need not be exported.
- * \param E        The MPI to hold the public exponent.
- *                 This may be \c NULL if this field need not be exported.
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED if exporting the
- *                 requested parameters cannot be done due to missing
- *                 functionality or because of security policies.
- * \return         A non-zero return code on any other failure.
- *
- */
-int mbedtls_rsa_export( const mbedtls_rsa_context *ctx,
-                        mbedtls_mpi *N, mbedtls_mpi *P, mbedtls_mpi *Q,
-                        mbedtls_mpi *D, mbedtls_mpi *E );
-
-/**
- * \brief          This function exports core parameters of an RSA key
- *                 in raw big-endian binary format.
- *
- *                 If this function runs successfully, the non-NULL buffers
- *                 pointed to by \p N, \p P, \p Q, \p D, and \p E are fully
- *                 written, with additional unused space filled leading by
- *                 zero Bytes.
- *
- *                 Possible reasons for returning
- *                 #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED:<ul>
- *                 <li>An alternative RSA implementation is in use, which
- *                 stores the key externally, and either cannot or should
- *                 not export it into RAM.</li>
- *                 <li>A SW or HW implementation might not support a certain
- *                 deduction. For example, \p P, \p Q from \p N, \p D,
- *                 and \p E if the former are not part of the
- *                 implementation.</li></ul>
- *                 If the function fails due to an unsupported operation,
- *                 the RSA context stays intact and remains usable.
- *
- * \note           The length parameters are ignored if the corresponding
- *                 buffer pointers are NULL.
- *
- * \param ctx      The initialized RSA context.
- * \param N        The Byte array to store the RSA modulus,
- *                 or \c NULL if this field need not be exported.
- * \param N_len    The size of the buffer for the modulus.
- * \param P        The Byte array to hold the first prime factor of \p N,
- *                 or \c NULL if this field need not be exported.
- * \param P_len    The size of the buffer for the first prime factor.
- * \param Q        The Byte array to hold the second prime factor of \p N,
- *                 or \c NULL if this field need not be exported.
- * \param Q_len    The size of the buffer for the second prime factor.
- * \param D        The Byte array to hold the private exponent,
- *                 or \c NULL if this field need not be exported.
- * \param D_len    The size of the buffer for the private exponent.
- * \param E        The Byte array to hold the public exponent,
- *                 or \c NULL if this field need not be exported.
- * \param E_len    The size of the buffer for the public exponent.
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED if exporting the
- *                 requested parameters cannot be done due to missing
- *                 functionality or because of security policies.
- * \return         A non-zero return code on any other failure.
- */
-int mbedtls_rsa_export_raw( const mbedtls_rsa_context *ctx,
-                            unsigned char *N, size_t N_len,
-                            unsigned char *P, size_t P_len,
-                            unsigned char *Q, size_t Q_len,
-                            unsigned char *D, size_t D_len,
-                            unsigned char *E, size_t E_len );
-
-/**
- * \brief          This function exports CRT parameters of a private RSA key.
- *
- * \note           Alternative RSA implementations not using CRT-parameters
- *                 internally can implement this function based on
- *                 mbedtls_rsa_deduce_opt().
- *
- * \param ctx      The initialized RSA context.
- * \param DP       The MPI to hold \c D modulo `P-1`,
- *                 or \c NULL if it need not be exported.
- * \param DQ       The MPI to hold \c D modulo `Q-1`,
- *                 or \c NULL if it need not be exported.
- * \param QP       The MPI to hold modular inverse of \c Q modulo \c P,
- *                 or \c NULL if it need not be exported.
- *
- * \return         \c 0 on success.
- * \return         A non-zero error code on failure.
- *
- */
-int mbedtls_rsa_export_crt( const mbedtls_rsa_context *ctx,
-                            mbedtls_mpi *DP, mbedtls_mpi *DQ, mbedtls_mpi *QP );
-
-/**
- * \brief          This function sets padding for an already initialized RSA
- *                 context. See mbedtls_rsa_init() for details.
- *
- * \param ctx      The initialized RSA context to be configured.
- * \param padding  The padding mode to use. This must be either
- *                 #MBEDTLS_RSA_PKCS_V15 or #MBEDTLS_RSA_PKCS_V21.
- * \param hash_id  The #MBEDTLS_RSA_PKCS_V21 hash identifier.
- */
-void mbedtls_rsa_set_padding( mbedtls_rsa_context *ctx, int padding,
-                              int hash_id );
-
-/**
- * \brief          This function retrieves the length of RSA modulus in Bytes.
- *
- * \param ctx      The initialized RSA context.
- *
- * \return         The length of the RSA modulus in Bytes.
- *
- */
-size_t mbedtls_rsa_get_len( const mbedtls_rsa_context *ctx );
-
-/**
- * \brief          This function generates an RSA keypair.
- *
- * \note           mbedtls_rsa_init() must be called before this function,
- *                 to set up the RSA context.
- *
- * \param ctx      The initialized RSA context used to hold the key.
- * \param f_rng    The RNG function to be used for key generation.
- *                 This must not be \c NULL.
- * \param p_rng    The RNG context to be passed to \p f_rng.
- *                 This may be \c NULL if \p f_rng doesn't need a context.
- * \param nbits    The size of the public key in bits.
- * \param exponent The public exponent to use. For example, \c 65537.
- *                 This must be odd and greater than \c 1.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_gen_key( mbedtls_rsa_context *ctx,
-                         int (*f_rng)(void *, unsigned char *, size_t),
-                         void *p_rng,
-                         unsigned int nbits, int exponent );
-
-/**
- * \brief          This function checks if a context contains at least an RSA
- *                 public key.
- *
- *                 If the function runs successfully, it is guaranteed that
- *                 enough information is present to perform an RSA public key
- *                 operation using mbedtls_rsa_public().
- *
- * \param ctx      The initialized RSA context to check.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- *
- */
-int mbedtls_rsa_check_pubkey( const mbedtls_rsa_context *ctx );
-
-/**
- * \brief      This function checks if a context contains an RSA private key
- *             and perform basic consistency checks.
- *
- * \note       The consistency checks performed by this function not only
- *             ensure that mbedtls_rsa_private() can be called successfully
- *             on the given context, but that the various parameters are
- *             mutually consistent with high probability, in the sense that
- *             mbedtls_rsa_public() and mbedtls_rsa_private() are inverses.
- *
- * \warning    This function should catch accidental misconfigurations
- *             like swapping of parameters, but it cannot establish full
- *             trust in neither the quality nor the consistency of the key
- *             material that was used to setup the given RSA context:
- *             <ul><li>Consistency: Imported parameters that are irrelevant
- *             for the implementation might be silently dropped. If dropped,
- *             the current function does not have access to them,
- *             and therefore cannot check them. See mbedtls_rsa_complete().
- *             If you want to check the consistency of the entire
- *             content of an PKCS1-encoded RSA private key, for example, you
- *             should use mbedtls_rsa_validate_params() before setting
- *             up the RSA context.
- *             Additionally, if the implementation performs empirical checks,
- *             these checks substantiate but do not guarantee consistency.</li>
- *             <li>Quality: This function is not expected to perform
- *             extended quality assessments like checking that the prime
- *             factors are safe. Additionally, it is the responsibility of the
- *             user to ensure the trustworthiness of the source of his RSA
- *             parameters, which goes beyond what is effectively checkable
- *             by the library.</li></ul>
- *
- * \param ctx  The initialized RSA context to check.
- *
- * \return     \c 0 on success.
- * \return     An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_check_privkey( const mbedtls_rsa_context *ctx );
-
-/**
- * \brief          This function checks a public-private RSA key pair.
- *
- *                 It checks each of the contexts, and makes sure they match.
- *
- * \param pub      The initialized RSA context holding the public key.
- * \param prv      The initialized RSA context holding the private key.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_check_pub_priv( const mbedtls_rsa_context *pub,
-                                const mbedtls_rsa_context *prv );
-
-/**
- * \brief          This function performs an RSA public key operation.
- *
- * \param ctx      The initialized RSA context to use.
- * \param input    The input buffer. This must be a readable buffer
- *                 of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- * \param output   The output buffer. This must be a writable buffer
- *                 of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- *
- * \note           This function does not handle message padding.
- *
- * \note           Make sure to set \p input[0] = 0 or ensure that
- *                 input is smaller than \p N.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_public( mbedtls_rsa_context *ctx,
-                const unsigned char *input,
-                unsigned char *output );
-
-/**
- * \brief          This function performs an RSA private key operation.
- *
- * \note           Blinding is used if and only if a PRNG is provided.
- *
- * \note           If blinding is used, both the base of exponentation
- *                 and the exponent are blinded, providing protection
- *                 against some side-channel attacks.
- *
- * \warning        It is deprecated and a security risk to not provide
- *                 a PRNG here and thereby prevent the use of blinding.
- *                 Future versions of the library may enforce the presence
- *                 of a PRNG.
- *
- * \param ctx      The initialized RSA context to use.
- * \param f_rng    The RNG function, used for blinding. It is discouraged
- *                 and deprecated to pass \c NULL here, in which case
- *                 blinding will be omitted.
- * \param p_rng    The RNG context to pass to \p f_rng. This may be \c NULL
- *                 if \p f_rng is \c NULL or if \p f_rng doesn't need a context.
- * \param input    The input buffer. This must be a readable buffer
- *                 of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- * \param output   The output buffer. This must be a writable buffer
- *                 of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- *
- */
-int mbedtls_rsa_private( mbedtls_rsa_context *ctx,
-                 int (*f_rng)(void *, unsigned char *, size_t),
-                 void *p_rng,
-                 const unsigned char *input,
-                 unsigned char *output );
-
-/**
- * \brief          This function adds the message padding, then performs an RSA
- *                 operation.
- *
- *                 It is the generic wrapper for performing a PKCS#1 encryption
- *                 operation using the \p mode from the context.
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 implicitly set to #MBEDTLS_RSA_PUBLIC.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PRIVATE and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA context to use.
- * \param f_rng    The RNG to use. It is mandatory for PKCS#1 v2.1 padding
- *                 encoding, and for PKCS#1 v1.5 padding encoding when used
- *                 with \p mode set to #MBEDTLS_RSA_PUBLIC. For PKCS#1 v1.5
- *                 padding encoding and \p mode set to #MBEDTLS_RSA_PRIVATE,
- *                 it is used for blinding and should be provided in this
- *                 case; see mbedtls_rsa_private() for more.
- * \param p_rng    The RNG context to be passed to \p f_rng. May be
- *                 \c NULL if \p f_rng is \c NULL or if \p f_rng doesn't
- *                 need a context argument.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated).
- * \param ilen     The length of the plaintext in Bytes.
- * \param input    The input data to encrypt. This must be a readable
- *                 buffer of size \p ilen Bytes. This must not be \c NULL.
- * \param output   The output buffer. This must be a writable buffer
- *                 of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_pkcs1_encrypt( mbedtls_rsa_context *ctx,
-                       int (*f_rng)(void *, unsigned char *, size_t),
-                       void *p_rng,
-                       int mode, size_t ilen,
-                       const unsigned char *input,
-                       unsigned char *output );
-
-/**
- * \brief          This function performs a PKCS#1 v1.5 encryption operation
- *                 (RSAES-PKCS1-v1_5-ENCRYPT).
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 implicitly set to #MBEDTLS_RSA_PUBLIC.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PRIVATE and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA context to use.
- * \param f_rng    The RNG function to use. It is needed for padding generation
- *                 if \p mode is #MBEDTLS_RSA_PUBLIC. If \p mode is
- *                 #MBEDTLS_RSA_PRIVATE (discouraged), it is used for
- *                 blinding and should be provided; see mbedtls_rsa_private().
- * \param p_rng    The RNG context to be passed to \p f_rng. This may
- *                 be \c NULL if \p f_rng is \c NULL or if \p f_rng
- *                 doesn't need a context argument.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated).
- * \param ilen     The length of the plaintext in Bytes.
- * \param input    The input data to encrypt. This must be a readable
- *                 buffer of size \p ilen Bytes. This must not be \c NULL.
- * \param output   The output buffer. This must be a writable buffer
- *                 of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_rsaes_pkcs1_v15_encrypt( mbedtls_rsa_context *ctx,
-                                 int (*f_rng)(void *, unsigned char *, size_t),
-                                 void *p_rng,
-                                 int mode, size_t ilen,
-                                 const unsigned char *input,
-                                 unsigned char *output );
-
-/**
- * \brief            This function performs a PKCS#1 v2.1 OAEP encryption
- *                   operation (RSAES-OAEP-ENCRYPT).
- *
- * \note             The output buffer must be as large as the size
- *                   of ctx->N. For example, 128 Bytes if RSA-1024 is used.
- *
- * \deprecated       It is deprecated and discouraged to call this function
- *                   in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library
- *                   are likely to remove the \p mode argument and have it
- *                   implicitly set to #MBEDTLS_RSA_PUBLIC.
- *
- * \note             Alternative implementations of RSA need not support
- *                   mode being set to #MBEDTLS_RSA_PRIVATE and might instead
- *                   return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx        The initnialized RSA context to use.
- * \param f_rng      The RNG function to use. This is needed for padding
- *                   generation and must be provided.
- * \param p_rng      The RNG context to be passed to \p f_rng. This may
- *                   be \c NULL if \p f_rng doesn't need a context argument.
- * \param mode       The mode of operation. This must be either
- *                   #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated).
- * \param label      The buffer holding the custom label to use.
- *                   This must be a readable buffer of length \p label_len
- *                   Bytes. It may be \c NULL if \p label_len is \c 0.
- * \param label_len  The length of the label in Bytes.
- * \param ilen       The length of the plaintext buffer \p input in Bytes.
- * \param input      The input data to encrypt. This must be a readable
- *                   buffer of size \p ilen Bytes. This must not be \c NULL.
- * \param output     The output buffer. This must be a writable buffer
- *                   of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                   for an 2048-bit RSA modulus.
- *
- * \return           \c 0 on success.
- * \return           An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_rsaes_oaep_encrypt( mbedtls_rsa_context *ctx,
-                            int (*f_rng)(void *, unsigned char *, size_t),
-                            void *p_rng,
-                            int mode,
-                            const unsigned char *label, size_t label_len,
-                            size_t ilen,
-                            const unsigned char *input,
-                            unsigned char *output );
-
-/**
- * \brief          This function performs an RSA operation, then removes the
- *                 message padding.
- *
- *                 It is the generic wrapper for performing a PKCS#1 decryption
- *                 operation using the \p mode from the context.
- *
- * \note           The output buffer length \c output_max_len should be
- *                 as large as the size \p ctx->len of \p ctx->N (for example,
- *                 128 Bytes if RSA-1024 is used) to be able to hold an
- *                 arbitrary decrypted message. If it is not large enough to
- *                 hold the decryption of the particular ciphertext provided,
- *                 the function returns \c MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE.
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 implicitly set to #MBEDTLS_RSA_PRIVATE.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PUBLIC and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA context to use.
- * \param f_rng    The RNG function. If \p mode is #MBEDTLS_RSA_PRIVATE,
- *                 this is used for blinding and should be provided; see
- *                 mbedtls_rsa_private() for more. If \p mode is
- *                 #MBEDTLS_RSA_PUBLIC, it is ignored.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be
- *                 \c NULL if \p f_rng is \c NULL or doesn't need a context.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated).
- * \param olen     The address at which to store the length of
- *                 the plaintext. This must not be \c NULL.
- * \param input    The ciphertext buffer. This must be a readable buffer
- *                 of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- * \param output   The buffer used to hold the plaintext. This must
- *                 be a writable buffer of length \p output_max_len Bytes.
- * \param output_max_len The length in Bytes of the output buffer \p output.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_pkcs1_decrypt( mbedtls_rsa_context *ctx,
-                       int (*f_rng)(void *, unsigned char *, size_t),
-                       void *p_rng,
-                       int mode, size_t *olen,
-                       const unsigned char *input,
-                       unsigned char *output,
-                       size_t output_max_len );
-
-/**
- * \brief          This function performs a PKCS#1 v1.5 decryption
- *                 operation (RSAES-PKCS1-v1_5-DECRYPT).
- *
- * \note           The output buffer length \c output_max_len should be
- *                 as large as the size \p ctx->len of \p ctx->N, for example,
- *                 128 Bytes if RSA-1024 is used, to be able to hold an
- *                 arbitrary decrypted message. If it is not large enough to
- *                 hold the decryption of the particular ciphertext provided,
- *                 the function returns #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE.
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 implicitly set to #MBEDTLS_RSA_PRIVATE.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PUBLIC and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA context to use.
- * \param f_rng    The RNG function. If \p mode is #MBEDTLS_RSA_PRIVATE,
- *                 this is used for blinding and should be provided; see
- *                 mbedtls_rsa_private() for more. If \p mode is
- *                 #MBEDTLS_RSA_PUBLIC, it is ignored.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be
- *                 \c NULL if \p f_rng is \c NULL or doesn't need a context.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated).
- * \param olen     The address at which to store the length of
- *                 the plaintext. This must not be \c NULL.
- * \param input    The ciphertext buffer. This must be a readable buffer
- *                 of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- * \param output   The buffer used to hold the plaintext. This must
- *                 be a writable buffer of length \p output_max_len Bytes.
- * \param output_max_len The length in Bytes of the output buffer \p output.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- *
- */
-int mbedtls_rsa_rsaes_pkcs1_v15_decrypt( mbedtls_rsa_context *ctx,
-                                 int (*f_rng)(void *, unsigned char *, size_t),
-                                 void *p_rng,
-                                 int mode, size_t *olen,
-                                 const unsigned char *input,
-                                 unsigned char *output,
-                                 size_t output_max_len );
-
-/**
- * \brief            This function performs a PKCS#1 v2.1 OAEP decryption
- *                   operation (RSAES-OAEP-DECRYPT).
- *
- * \note             The output buffer length \c output_max_len should be
- *                   as large as the size \p ctx->len of \p ctx->N, for
- *                   example, 128 Bytes if RSA-1024 is used, to be able to
- *                   hold an arbitrary decrypted message. If it is not
- *                   large enough to hold the decryption of the particular
- *                   ciphertext provided, the function returns
- *                   #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE.
- *
- * \deprecated       It is deprecated and discouraged to call this function
- *                   in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library
- *                   are likely to remove the \p mode argument and have it
- *                   implicitly set to #MBEDTLS_RSA_PRIVATE.
- *
- * \note             Alternative implementations of RSA need not support
- *                   mode being set to #MBEDTLS_RSA_PUBLIC and might instead
- *                   return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx        The initialized RSA context to use.
- * \param f_rng      The RNG function. If \p mode is #MBEDTLS_RSA_PRIVATE,
- *                   this is used for blinding and should be provided; see
- *                   mbedtls_rsa_private() for more. If \p mode is
- *                   #MBEDTLS_RSA_PUBLIC, it is ignored.
- * \param p_rng      The RNG context to be passed to \p f_rng. This may be
- *                   \c NULL if \p f_rng is \c NULL or doesn't need a context.
- * \param mode       The mode of operation. This must be either
- *                   #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated).
- * \param label      The buffer holding the custom label to use.
- *                   This must be a readable buffer of length \p label_len
- *                   Bytes. It may be \c NULL if \p label_len is \c 0.
- * \param label_len  The length of the label in Bytes.
- * \param olen       The address at which to store the length of
- *                   the plaintext. This must not be \c NULL.
- * \param input      The ciphertext buffer. This must be a readable buffer
- *                   of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                   for an 2048-bit RSA modulus.
- * \param output     The buffer used to hold the plaintext. This must
- *                   be a writable buffer of length \p output_max_len Bytes.
- * \param output_max_len The length in Bytes of the output buffer \p output.
- *
- * \return         \c 0 on success.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_rsaes_oaep_decrypt( mbedtls_rsa_context *ctx,
-                            int (*f_rng)(void *, unsigned char *, size_t),
-                            void *p_rng,
-                            int mode,
-                            const unsigned char *label, size_t label_len,
-                            size_t *olen,
-                            const unsigned char *input,
-                            unsigned char *output,
-                            size_t output_max_len );
-
-/**
- * \brief          This function performs a private RSA operation to sign
- *                 a message digest using PKCS#1.
- *
- *                 It is the generic wrapper for performing a PKCS#1
- *                 signature using the \p mode from the context.
- *
- * \note           The \p sig buffer must be as large as the size
- *                 of \p ctx->N. For example, 128 Bytes if RSA-1024 is used.
- *
- * \note           For PKCS#1 v2.1 encoding, see comments on
- *                 mbedtls_rsa_rsassa_pss_sign() for details on
- *                 \p md_alg and \p hash_id.
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 implicitly set to #MBEDTLS_RSA_PRIVATE.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PUBLIC and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA context to use.
- * \param f_rng    The RNG function to use. If the padding mode is PKCS#1 v2.1,
- *                 this must be provided. If the padding mode is PKCS#1 v1.5 and
- *                 \p mode is #MBEDTLS_RSA_PRIVATE, it is used for blinding
- *                 and should be provided; see mbedtls_rsa_private() for more
- *                 more. It is ignored otherwise.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be \c NULL
- *                 if \p f_rng is \c NULL or doesn't need a context argument.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated).
- * \param md_alg   The message-digest algorithm used to hash the original data.
- *                 Use #MBEDTLS_MD_NONE for signing raw data.
- * \param hashlen  The length of the message digest.
- *                 Ths is only used if \p md_alg is #MBEDTLS_MD_NONE.
- * \param hash     The buffer holding the message digest or raw data.
- *                 If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable
- *                 buffer of length \p hashlen Bytes. If \p md_alg is not
- *                 #MBEDTLS_MD_NONE, it must be a readable buffer of length
- *                 the size of the hash corresponding to \p md_alg.
- * \param sig      The buffer to hold the signature. This must be a writable
- *                 buffer of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus. A buffer length of
- *                 #MBEDTLS_MPI_MAX_SIZE is always safe.
- *
- * \return         \c 0 if the signing operation was successful.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_pkcs1_sign( mbedtls_rsa_context *ctx,
-                    int (*f_rng)(void *, unsigned char *, size_t),
-                    void *p_rng,
-                    int mode,
-                    mbedtls_md_type_t md_alg,
-                    unsigned int hashlen,
-                    const unsigned char *hash,
-                    unsigned char *sig );
-
-/**
- * \brief          This function performs a PKCS#1 v1.5 signature
- *                 operation (RSASSA-PKCS1-v1_5-SIGN).
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 implicitly set to #MBEDTLS_RSA_PRIVATE.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PUBLIC and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA context to use.
- * \param f_rng    The RNG function. If \p mode is #MBEDTLS_RSA_PRIVATE,
- *                 this is used for blinding and should be provided; see
- *                 mbedtls_rsa_private() for more. If \p mode is
- *                 #MBEDTLS_RSA_PUBLIC, it is ignored.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be \c NULL
- *                 if \p f_rng is \c NULL or doesn't need a context argument.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated).
- * \param md_alg   The message-digest algorithm used to hash the original data.
- *                 Use #MBEDTLS_MD_NONE for signing raw data.
- * \param hashlen  The length of the message digest.
- *                 Ths is only used if \p md_alg is #MBEDTLS_MD_NONE.
- * \param hash     The buffer holding the message digest or raw data.
- *                 If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable
- *                 buffer of length \p hashlen Bytes. If \p md_alg is not
- *                 #MBEDTLS_MD_NONE, it must be a readable buffer of length
- *                 the size of the hash corresponding to \p md_alg.
- * \param sig      The buffer to hold the signature. This must be a writable
- *                 buffer of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus. A buffer length of
- *                 #MBEDTLS_MPI_MAX_SIZE is always safe.
- *
- * \return         \c 0 if the signing operation was successful.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_rsassa_pkcs1_v15_sign( mbedtls_rsa_context *ctx,
-                               int (*f_rng)(void *, unsigned char *, size_t),
-                               void *p_rng,
-                               int mode,
-                               mbedtls_md_type_t md_alg,
-                               unsigned int hashlen,
-                               const unsigned char *hash,
-                               unsigned char *sig );
-
-/**
- * \brief          This function performs a PKCS#1 v2.1 PSS signature
- *                 operation (RSASSA-PSS-SIGN).
- *
- * \note           The \p hash_id in the RSA context is the one used for the
- *                 encoding. \p md_alg in the function call is the type of hash
- *                 that is encoded. According to <em>RFC-3447: Public-Key
- *                 Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography
- *                 Specifications</em> it is advised to keep both hashes the
- *                 same.
- *
- * \note           This function always uses the maximum possible salt size,
- *                 up to the length of the payload hash. This choice of salt
- *                 size complies with FIPS 186-4 §5.5 (e) and RFC 8017 (PKCS#1
- *                 v2.2) §9.1.1 step 3. Furthermore this function enforces a
- *                 minimum salt size which is the hash size minus 2 bytes. If
- *                 this minimum size is too large given the key size (the salt
- *                 size, plus the hash size, plus 2 bytes must be no more than
- *                 the key size in bytes), this function returns
- *                 #MBEDTLS_ERR_RSA_BAD_INPUT_DATA.
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PUBLIC mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 implicitly set to #MBEDTLS_RSA_PRIVATE.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PUBLIC and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA context to use.
- * \param f_rng    The RNG function. It must not be \c NULL.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be \c NULL
- *                 if \p f_rng doesn't need a context argument.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PRIVATE or #MBEDTLS_RSA_PUBLIC (deprecated).
- * \param md_alg   The message-digest algorithm used to hash the original data.
- *                 Use #MBEDTLS_MD_NONE for signing raw data.
- * \param hashlen  The length of the message digest.
- *                 Ths is only used if \p md_alg is #MBEDTLS_MD_NONE.
- * \param hash     The buffer holding the message digest or raw data.
- *                 If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable
- *                 buffer of length \p hashlen Bytes. If \p md_alg is not
- *                 #MBEDTLS_MD_NONE, it must be a readable buffer of length
- *                 the size of the hash corresponding to \p md_alg.
- * \param sig      The buffer to hold the signature. This must be a writable
- *                 buffer of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus. A buffer length of
- *                 #MBEDTLS_MPI_MAX_SIZE is always safe.
- *
- * \return         \c 0 if the signing operation was successful.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_rsassa_pss_sign( mbedtls_rsa_context *ctx,
-                         int (*f_rng)(void *, unsigned char *, size_t),
-                         void *p_rng,
-                         int mode,
-                         mbedtls_md_type_t md_alg,
-                         unsigned int hashlen,
-                         const unsigned char *hash,
-                         unsigned char *sig );
-
-/**
- * \brief          This function performs a public RSA operation and checks
- *                 the message digest.
- *
- *                 This is the generic wrapper for performing a PKCS#1
- *                 verification using the mode from the context.
- *
- * \note           For PKCS#1 v2.1 encoding, see comments on
- *                 mbedtls_rsa_rsassa_pss_verify() about \p md_alg and
- *                 \p hash_id.
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 set to #MBEDTLS_RSA_PUBLIC.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PRIVATE and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA public key context to use.
- * \param f_rng    The RNG function to use. If \p mode is #MBEDTLS_RSA_PRIVATE,
- *                 this is used for blinding and should be provided; see
- *                 mbedtls_rsa_private() for more. Otherwise, it is ignored.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be
- *                 \c NULL if \p f_rng is \c NULL or doesn't need a context.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated).
- * \param md_alg   The message-digest algorithm used to hash the original data.
- *                 Use #MBEDTLS_MD_NONE for signing raw data.
- * \param hashlen  The length of the message digest.
- *                 This is only used if \p md_alg is #MBEDTLS_MD_NONE.
- * \param hash     The buffer holding the message digest or raw data.
- *                 If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable
- *                 buffer of length \p hashlen Bytes. If \p md_alg is not
- *                 #MBEDTLS_MD_NONE, it must be a readable buffer of length
- *                 the size of the hash corresponding to \p md_alg.
- * \param sig      The buffer holding the signature. This must be a readable
- *                 buffer of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- *
- * \return         \c 0 if the verify operation was successful.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_pkcs1_verify( mbedtls_rsa_context *ctx,
-                      int (*f_rng)(void *, unsigned char *, size_t),
-                      void *p_rng,
-                      int mode,
-                      mbedtls_md_type_t md_alg,
-                      unsigned int hashlen,
-                      const unsigned char *hash,
-                      const unsigned char *sig );
-
-/**
- * \brief          This function performs a PKCS#1 v1.5 verification
- *                 operation (RSASSA-PKCS1-v1_5-VERIFY).
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 set to #MBEDTLS_RSA_PUBLIC.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PRIVATE and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA public key context to use.
- * \param f_rng    The RNG function to use. If \p mode is #MBEDTLS_RSA_PRIVATE,
- *                 this is used for blinding and should be provided; see
- *                 mbedtls_rsa_private() for more. Otherwise, it is ignored.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be
- *                 \c NULL if \p f_rng is \c NULL or doesn't need a context.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated).
- * \param md_alg   The message-digest algorithm used to hash the original data.
- *                 Use #MBEDTLS_MD_NONE for signing raw data.
- * \param hashlen  The length of the message digest.
- *                 This is only used if \p md_alg is #MBEDTLS_MD_NONE.
- * \param hash     The buffer holding the message digest or raw data.
- *                 If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable
- *                 buffer of length \p hashlen Bytes. If \p md_alg is not
- *                 #MBEDTLS_MD_NONE, it must be a readable buffer of length
- *                 the size of the hash corresponding to \p md_alg.
- * \param sig      The buffer holding the signature. This must be a readable
- *                 buffer of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- *
- * \return         \c 0 if the verify operation was successful.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_rsassa_pkcs1_v15_verify( mbedtls_rsa_context *ctx,
-                                 int (*f_rng)(void *, unsigned char *, size_t),
-                                 void *p_rng,
-                                 int mode,
-                                 mbedtls_md_type_t md_alg,
-                                 unsigned int hashlen,
-                                 const unsigned char *hash,
-                                 const unsigned char *sig );
-
-/**
- * \brief          This function performs a PKCS#1 v2.1 PSS verification
- *                 operation (RSASSA-PSS-VERIFY).
- *
- *                 The hash function for the MGF mask generating function
- *                 is that specified in the RSA context.
- *
- * \note           The \p hash_id in the RSA context is the one used for the
- *                 verification. \p md_alg in the function call is the type of
- *                 hash that is verified. According to <em>RFC-3447: Public-Key
- *                 Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography
- *                 Specifications</em> it is advised to keep both hashes the
- *                 same. If \p hash_id in the RSA context is unset,
- *                 the \p md_alg from the function call is used.
- *
- * \deprecated     It is deprecated and discouraged to call this function
- *                 in #MBEDTLS_RSA_PRIVATE mode. Future versions of the library
- *                 are likely to remove the \p mode argument and have it
- *                 implicitly set to #MBEDTLS_RSA_PUBLIC.
- *
- * \note           Alternative implementations of RSA need not support
- *                 mode being set to #MBEDTLS_RSA_PRIVATE and might instead
- *                 return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED.
- *
- * \param ctx      The initialized RSA public key context to use.
- * \param f_rng    The RNG function to use. If \p mode is #MBEDTLS_RSA_PRIVATE,
- *                 this is used for blinding and should be provided; see
- *                 mbedtls_rsa_private() for more. Otherwise, it is ignored.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be
- *                 \c NULL if \p f_rng is \c NULL or doesn't need a context.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE (deprecated).
- * \param md_alg   The message-digest algorithm used to hash the original data.
- *                 Use #MBEDTLS_MD_NONE for signing raw data.
- * \param hashlen  The length of the message digest.
- *                 This is only used if \p md_alg is #MBEDTLS_MD_NONE.
- * \param hash     The buffer holding the message digest or raw data.
- *                 If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable
- *                 buffer of length \p hashlen Bytes. If \p md_alg is not
- *                 #MBEDTLS_MD_NONE, it must be a readable buffer of length
- *                 the size of the hash corresponding to \p md_alg.
- * \param sig      The buffer holding the signature. This must be a readable
- *                 buffer of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- *
- * \return         \c 0 if the verify operation was successful.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_rsassa_pss_verify( mbedtls_rsa_context *ctx,
-                           int (*f_rng)(void *, unsigned char *, size_t),
-                           void *p_rng,
-                           int mode,
-                           mbedtls_md_type_t md_alg,
-                           unsigned int hashlen,
-                           const unsigned char *hash,
-                           const unsigned char *sig );
-
-/**
- * \brief          This function performs a PKCS#1 v2.1 PSS verification
- *                 operation (RSASSA-PSS-VERIFY).
- *
- *                 The hash function for the MGF mask generating function
- *                 is that specified in \p mgf1_hash_id.
- *
- * \note           The \p sig buffer must be as large as the size
- *                 of \p ctx->N. For example, 128 Bytes if RSA-1024 is used.
- *
- * \note           The \p hash_id in the RSA context is ignored.
- *
- * \param ctx      The initialized RSA public key context to use.
- * \param f_rng    The RNG function to use. If \p mode is #MBEDTLS_RSA_PRIVATE,
- *                 this is used for blinding and should be provided; see
- *                 mbedtls_rsa_private() for more. Otherwise, it is ignored.
- * \param p_rng    The RNG context to be passed to \p f_rng. This may be
- *                 \c NULL if \p f_rng is \c NULL or doesn't need a context.
- * \param mode     The mode of operation. This must be either
- *                 #MBEDTLS_RSA_PUBLIC or #MBEDTLS_RSA_PRIVATE.
- * \param md_alg   The message-digest algorithm used to hash the original data.
- *                 Use #MBEDTLS_MD_NONE for signing raw data.
- * \param hashlen  The length of the message digest.
- *                 This is only used if \p md_alg is #MBEDTLS_MD_NONE.
- * \param hash     The buffer holding the message digest or raw data.
- *                 If \p md_alg is #MBEDTLS_MD_NONE, this must be a readable
- *                 buffer of length \p hashlen Bytes. If \p md_alg is not
- *                 #MBEDTLS_MD_NONE, it must be a readable buffer of length
- *                 the size of the hash corresponding to \p md_alg.
- * \param mgf1_hash_id      The message digest used for mask generation.
- * \param expected_salt_len The length of the salt used in padding. Use
- *                          #MBEDTLS_RSA_SALT_LEN_ANY to accept any salt length.
- * \param sig      The buffer holding the signature. This must be a readable
- *                 buffer of length \c ctx->len Bytes. For example, \c 256 Bytes
- *                 for an 2048-bit RSA modulus.
- *
- * \return         \c 0 if the verify operation was successful.
- * \return         An \c MBEDTLS_ERR_RSA_XXX error code on failure.
- */
-int mbedtls_rsa_rsassa_pss_verify_ext( mbedtls_rsa_context *ctx,
-                               int (*f_rng)(void *, unsigned char *, size_t),
-                               void *p_rng,
-                               int mode,
-                               mbedtls_md_type_t md_alg,
-                               unsigned int hashlen,
-                               const unsigned char *hash,
-                               mbedtls_md_type_t mgf1_hash_id,
-                               int expected_salt_len,
-                               const unsigned char *sig );
-
-/**
- * \brief          This function copies the components of an RSA context.
- *
- * \param dst      The destination context. This must be initialized.
- * \param src      The source context. This must be initialized.
- *
- * \return         \c 0 on success.
- * \return         #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory allocation failure.
- */
-int mbedtls_rsa_copy( mbedtls_rsa_context *dst, const mbedtls_rsa_context *src );
-
-/**
- * \brief          This function frees the components of an RSA key.
- *
- * \param ctx      The RSA context to free. May be \c NULL, in which case
- *                 this function is a no-op. If it is not \c NULL, it must
- *                 point to an initialized RSA context.
- */
-void mbedtls_rsa_free( mbedtls_rsa_context *ctx );
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          The RSA checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_rsa_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* rsa.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/rsa_internal.h b/tools/sdk/include/mbedtls/mbedtls/rsa_internal.h
deleted file mode 100644
index 2464e6b082b..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/rsa_internal.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/**
- * \file rsa_internal.h
- *
- * \brief Context-independent RSA helper functions
- *
- *  This module declares some RSA-related helper functions useful when
- *  implementing the RSA interface. These functions are provided in a separate
- *  compilation unit in order to make it easy for designers of alternative RSA
- *  implementations to use them in their own code, as it is conceived that the
- *  functionality they provide will be necessary for most complete
- *  implementations.
- *
- *  End-users of Mbed TLS who are not providing their own alternative RSA
- *  implementations should not use these functions directly, and should instead
- *  use only the functions declared in rsa.h.
- *
- *  The interface provided by this module will be maintained through LTS (Long
- *  Term Support) branches of Mbed TLS, but may otherwise be subject to change,
- *  and must be considered an internal interface of the library.
- *
- *  There are two classes of helper functions:
- *
- *  (1) Parameter-generating helpers. These are:
- *      - mbedtls_rsa_deduce_primes
- *      - mbedtls_rsa_deduce_private_exponent
- *      - mbedtls_rsa_deduce_crt
- *       Each of these functions takes a set of core RSA parameters and
- *       generates some other, or CRT related parameters.
- *
- *  (2) Parameter-checking helpers. These are:
- *      - mbedtls_rsa_validate_params
- *      - mbedtls_rsa_validate_crt
- *      They take a set of core or CRT related RSA parameters and check their
- *      validity.
- *
- */
-/*
- *  Copyright (C) 2006-2017, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- *
- */
-
-#ifndef MBEDTLS_RSA_INTERNAL_H
-#define MBEDTLS_RSA_INTERNAL_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "bignum.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**
- * \brief          Compute RSA prime moduli P, Q from public modulus N=PQ
- *                 and a pair of private and public key.
- *
- * \note           This is a 'static' helper function not operating on
- *                 an RSA context. Alternative implementations need not
- *                 overwrite it.
- *
- * \param N        RSA modulus N = PQ, with P, Q to be found
- * \param E        RSA public exponent
- * \param D        RSA private exponent
- * \param P        Pointer to MPI holding first prime factor of N on success
- * \param Q        Pointer to MPI holding second prime factor of N on success
- *
- * \return
- *                 - 0 if successful. In this case, P and Q constitute a
- *                   factorization of N.
- *                 - A non-zero error code otherwise.
- *
- * \note           It is neither checked that P, Q are prime nor that
- *                 D, E are modular inverses wrt. P-1 and Q-1. For that,
- *                 use the helper function \c mbedtls_rsa_validate_params.
- *
- */
-int mbedtls_rsa_deduce_primes( mbedtls_mpi const *N, mbedtls_mpi const *E,
-                               mbedtls_mpi const *D,
-                               mbedtls_mpi *P, mbedtls_mpi *Q );
-
-/**
- * \brief          Compute RSA private exponent from
- *                 prime moduli and public key.
- *
- * \note           This is a 'static' helper function not operating on
- *                 an RSA context. Alternative implementations need not
- *                 overwrite it.
- *
- * \param P        First prime factor of RSA modulus
- * \param Q        Second prime factor of RSA modulus
- * \param E        RSA public exponent
- * \param D        Pointer to MPI holding the private exponent on success.
- *
- * \return
- *                 - 0 if successful. In this case, D is set to a simultaneous
- *                   modular inverse of E modulo both P-1 and Q-1.
- *                 - A non-zero error code otherwise.
- *
- * \note           This function does not check whether P and Q are primes.
- *
- */
-int mbedtls_rsa_deduce_private_exponent( mbedtls_mpi const *P,
-                                         mbedtls_mpi const *Q,
-                                         mbedtls_mpi const *E,
-                                         mbedtls_mpi *D );
-
-
-/**
- * \brief          Generate RSA-CRT parameters
- *
- * \note           This is a 'static' helper function not operating on
- *                 an RSA context. Alternative implementations need not
- *                 overwrite it.
- *
- * \param P        First prime factor of N
- * \param Q        Second prime factor of N
- * \param D        RSA private exponent
- * \param DP       Output variable for D modulo P-1
- * \param DQ       Output variable for D modulo Q-1
- * \param QP       Output variable for the modular inverse of Q modulo P.
- *
- * \return         0 on success, non-zero error code otherwise.
- *
- * \note           This function does not check whether P, Q are
- *                 prime and whether D is a valid private exponent.
- *
- */
-int mbedtls_rsa_deduce_crt( const mbedtls_mpi *P, const mbedtls_mpi *Q,
-                            const mbedtls_mpi *D, mbedtls_mpi *DP,
-                            mbedtls_mpi *DQ, mbedtls_mpi *QP );
-
-
-/**
- * \brief          Check validity of core RSA parameters
- *
- * \note           This is a 'static' helper function not operating on
- *                 an RSA context. Alternative implementations need not
- *                 overwrite it.
- *
- * \param N        RSA modulus N = PQ
- * \param P        First prime factor of N
- * \param Q        Second prime factor of N
- * \param D        RSA private exponent
- * \param E        RSA public exponent
- * \param f_rng    PRNG to be used for primality check, or NULL
- * \param p_rng    PRNG context for f_rng, or NULL
- *
- * \return
- *                 - 0 if the following conditions are satisfied
- *                   if all relevant parameters are provided:
- *                    - P prime if f_rng != NULL (%)
- *                    - Q prime if f_rng != NULL (%)
- *                    - 1 < N = P * Q
- *                    - 1 < D, E < N
- *                    - D and E are modular inverses modulo P-1 and Q-1
- *                   (%) This is only done if MBEDTLS_GENPRIME is defined.
- *                 - A non-zero error code otherwise.
- *
- * \note           The function can be used with a restricted set of arguments
- *                 to perform specific checks only. E.g., calling it with
- *                 (-,P,-,-,-) and a PRNG amounts to a primality check for P.
- */
-int mbedtls_rsa_validate_params( const mbedtls_mpi *N, const mbedtls_mpi *P,
-                                 const mbedtls_mpi *Q, const mbedtls_mpi *D,
-                                 const mbedtls_mpi *E,
-                                 int (*f_rng)(void *, unsigned char *, size_t),
-                                 void *p_rng );
-
-/**
- * \brief          Check validity of RSA CRT parameters
- *
- * \note           This is a 'static' helper function not operating on
- *                 an RSA context. Alternative implementations need not
- *                 overwrite it.
- *
- * \param P        First prime factor of RSA modulus
- * \param Q        Second prime factor of RSA modulus
- * \param D        RSA private exponent
- * \param DP       MPI to check for D modulo P-1
- * \param DQ       MPI to check for D modulo P-1
- * \param QP       MPI to check for the modular inverse of Q modulo P.
- *
- * \return
- *                 - 0 if the following conditions are satisfied:
- *                    - D = DP mod P-1 if P, D, DP != NULL
- *                    - Q = DQ mod P-1 if P, D, DQ != NULL
- *                    - QP = Q^-1 mod P if P, Q, QP != NULL
- *                 - \c MBEDTLS_ERR_RSA_KEY_CHECK_FAILED if check failed,
- *                   potentially including \c MBEDTLS_ERR_MPI_XXX if some
- *                   MPI calculations failed.
- *                 - \c MBEDTLS_ERR_RSA_BAD_INPUT_DATA if insufficient
- *                   data was provided to check DP, DQ or QP.
- *
- * \note           The function can be used with a restricted set of arguments
- *                 to perform specific checks only. E.g., calling it with the
- *                 parameters (P, -, D, DP, -, -) will check DP = D mod P-1.
- */
-int mbedtls_rsa_validate_crt( const mbedtls_mpi *P,  const mbedtls_mpi *Q,
-                              const mbedtls_mpi *D,  const mbedtls_mpi *DP,
-                              const mbedtls_mpi *DQ, const mbedtls_mpi *QP );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* rsa_internal.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/sha1.h b/tools/sdk/include/mbedtls/mbedtls/sha1.h
deleted file mode 100644
index e69db8a15a0..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/sha1.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/**
- * \file sha1.h
- *
- * \brief This file contains SHA-1 definitions and functions.
- *
- * The Secure Hash Algorithm 1 (SHA-1) cryptographic hash function is defined in
- * <em>FIPS 180-4: Secure Hash Standard (SHS)</em>.
- *
- * \warning   SHA-1 is considered a weak message digest and its use constitutes
- *            a security risk. We recommend considering stronger message
- *            digests instead.
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SHA1_H
-#define MBEDTLS_SHA1_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* MBEDTLS_ERR_SHA1_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_SHA1_HW_ACCEL_FAILED                  -0x0035  /**< SHA-1 hardware accelerator failed */
-#define MBEDTLS_ERR_SHA1_BAD_INPUT_DATA                   -0x0073  /**< SHA-1 input data was malformed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_SHA1_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          The SHA-1 context structure.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- */
-typedef struct mbedtls_sha1_context
-{
-    uint32_t total[2];          /*!< The number of Bytes processed.  */
-    uint32_t state[5];          /*!< The intermediate digest state.  */
-    unsigned char buffer[64];   /*!< The data block being processed. */
-}
-mbedtls_sha1_context;
-
-#else  /* MBEDTLS_SHA1_ALT */
-#include "sha1_alt.h"
-#endif /* MBEDTLS_SHA1_ALT */
-
-/**
- * \brief          This function initializes a SHA-1 context.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \param ctx      The SHA-1 context to initialize.
- *                 This must not be \c NULL.
- *
- */
-void mbedtls_sha1_init( mbedtls_sha1_context *ctx );
-
-/**
- * \brief          This function clears a SHA-1 context.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \param ctx      The SHA-1 context to clear. This may be \c NULL,
- *                 in which case this function does nothing. If it is
- *                 not \c NULL, it must point to an initialized
- *                 SHA-1 context.
- *
- */
-void mbedtls_sha1_free( mbedtls_sha1_context *ctx );
-
-/**
- * \brief          This function clones the state of a SHA-1 context.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \param dst      The SHA-1 context to clone to. This must be initialized.
- * \param src      The SHA-1 context to clone from. This must be initialized.
- *
- */
-void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
-                         const mbedtls_sha1_context *src );
-
-/**
- * \brief          This function starts a SHA-1 checksum calculation.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \param ctx      The SHA-1 context to initialize. This must be initialized.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- *
- */
-int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx );
-
-/**
- * \brief          This function feeds an input buffer into an ongoing SHA-1
- *                 checksum calculation.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \param ctx      The SHA-1 context. This must be initialized
- *                 and have a hash operation started.
- * \param input    The buffer holding the input data.
- *                 This must be a readable buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data \p input in Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx,
-                             const unsigned char *input,
-                             size_t ilen );
-
-/**
- * \brief          This function finishes the SHA-1 operation, and writes
- *                 the result to the output buffer.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \param ctx      The SHA-1 context to use. This must be initialized and
- *                 have a hash operation started.
- * \param output   The SHA-1 checksum result. This must be a writable
- *                 buffer of length \c 20 Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx,
-                             unsigned char output[20] );
-
-/**
- * \brief          SHA-1 process data block (internal use only).
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \param ctx      The SHA-1 context to use. This must be initialized.
- * \param data     The data block being processed. This must be a
- *                 readable buffer of length \c 64 Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- *
- */
-int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx,
-                                   const unsigned char data[64] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          This function starts a SHA-1 checksum calculation.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \deprecated     Superseded by mbedtls_sha1_starts_ret() in 2.7.0.
- *
- * \param ctx      The SHA-1 context to initialize. This must be initialized.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_sha1_starts( mbedtls_sha1_context *ctx );
-
-/**
- * \brief          This function feeds an input buffer into an ongoing SHA-1
- *                 checksum calculation.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \deprecated     Superseded by mbedtls_sha1_update_ret() in 2.7.0.
- *
- * \param ctx      The SHA-1 context. This must be initialized and
- *                 have a hash operation started.
- * \param input    The buffer holding the input data.
- *                 This must be a readable buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data \p input in Bytes.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_sha1_update( mbedtls_sha1_context *ctx,
-                                             const unsigned char *input,
-                                             size_t ilen );
-
-/**
- * \brief          This function finishes the SHA-1 operation, and writes
- *                 the result to the output buffer.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \deprecated     Superseded by mbedtls_sha1_finish_ret() in 2.7.0.
- *
- * \param ctx      The SHA-1 context. This must be initialized and
- *                 have a hash operation started.
- * \param output   The SHA-1 checksum result.
- *                 This must be a writable buffer of length \c 20 Bytes.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha1_finish( mbedtls_sha1_context *ctx,
-                                             unsigned char output[20] );
-
-/**
- * \brief          SHA-1 process data block (internal use only).
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \deprecated     Superseded by mbedtls_internal_sha1_process() in 2.7.0.
- *
- * \param ctx      The SHA-1 context. This must be initialized.
- * \param data     The data block being processed.
- *                 This must be a readable buffer of length \c 64 bytes.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_sha1_process( mbedtls_sha1_context *ctx,
-                                              const unsigned char data[64] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief          This function calculates the SHA-1 checksum of a buffer.
- *
- *                 The function allocates the context, performs the
- *                 calculation, and frees the context.
- *
- *                 The SHA-1 result is calculated as
- *                 output = SHA-1(input buffer).
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \param input    The buffer holding the input data.
- *                 This must be a readable buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data \p input in Bytes.
- * \param output   The SHA-1 checksum result.
- *                 This must be a writable buffer of length \c 20 Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- *
- */
-int mbedtls_sha1_ret( const unsigned char *input,
-                      size_t ilen,
-                      unsigned char output[20] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          This function calculates the SHA-1 checksum of a buffer.
- *
- *                 The function allocates the context, performs the
- *                 calculation, and frees the context.
- *
- *                 The SHA-1 result is calculated as
- *                 output = SHA-1(input buffer).
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \deprecated     Superseded by mbedtls_sha1_ret() in 2.7.0
- *
- * \param input    The buffer holding the input data.
- *                 This must be a readable buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data \p input in Bytes.
- * \param output   The SHA-1 checksum result. This must be a writable
- *                 buffer of size \c 20 Bytes.
- *
- */
-MBEDTLS_DEPRECATED void mbedtls_sha1( const unsigned char *input,
-                                      size_t ilen,
-                                      unsigned char output[20] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          The SHA-1 checkup routine.
- *
- * \warning        SHA-1 is considered a weak message digest and its use
- *                 constitutes a security risk. We recommend considering
- *                 stronger message digests instead.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- *
- */
-int mbedtls_sha1_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_sha1.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/sha256.h b/tools/sdk/include/mbedtls/mbedtls/sha256.h
deleted file mode 100644
index 5b03bc31dc9..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/sha256.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/**
- * \file sha256.h
- *
- * \brief This file contains SHA-224 and SHA-256 definitions and functions.
- *
- * The Secure Hash Algorithms 224 and 256 (SHA-224 and SHA-256) cryptographic
- * hash functions are defined in <em>FIPS 180-4: Secure Hash Standard (SHS)</em>.
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SHA256_H
-#define MBEDTLS_SHA256_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED                -0x0037  /**< SHA-256 hardware accelerator failed */
-#define MBEDTLS_ERR_SHA256_BAD_INPUT_DATA                 -0x0074  /**< SHA-256 input data was malformed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_SHA256_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          The SHA-256 context structure.
- *
- *                 The structure is used both for SHA-256 and for SHA-224
- *                 checksum calculations. The choice between these two is
- *                 made in the call to mbedtls_sha256_starts_ret().
- */
-typedef struct mbedtls_sha256_context
-{
-    uint32_t total[2];          /*!< The number of Bytes processed.  */
-    uint32_t state[8];          /*!< The intermediate digest state.  */
-    unsigned char buffer[64];   /*!< The data block being processed. */
-    int is224;                  /*!< Determines which function to use:
-                                     0: Use SHA-256, or 1: Use SHA-224. */
-}
-mbedtls_sha256_context;
-
-#else  /* MBEDTLS_SHA256_ALT */
-#include "sha256_alt.h"
-#endif /* MBEDTLS_SHA256_ALT */
-
-/**
- * \brief          This function initializes a SHA-256 context.
- *
- * \param ctx      The SHA-256 context to initialize. This must not be \c NULL.
- */
-void mbedtls_sha256_init( mbedtls_sha256_context *ctx );
-
-/**
- * \brief          This function clears a SHA-256 context.
- *
- * \param ctx      The SHA-256 context to clear. This may be \c NULL, in which
- *                 case this function returns immediately. If it is not \c NULL,
- *                 it must point to an initialized SHA-256 context.
- */
-void mbedtls_sha256_free( mbedtls_sha256_context *ctx );
-
-/**
- * \brief          This function clones the state of a SHA-256 context.
- *
- * \param dst      The destination context. This must be initialized.
- * \param src      The context to clone. This must be initialized.
- */
-void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
-                           const mbedtls_sha256_context *src );
-
-/**
- * \brief          This function starts a SHA-224 or SHA-256 checksum
- *                 calculation.
- *
- * \param ctx      The context to use. This must be initialized.
- * \param is224    This determines which function to use. This must be
- *                 either \c 0 for SHA-256, or \c 1 for SHA-224.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 );
-
-/**
- * \brief          This function feeds an input buffer into an ongoing
- *                 SHA-256 checksum calculation.
- *
- * \param ctx      The SHA-256 context. This must be initialized
- *                 and have a hash operation started.
- * \param input    The buffer holding the data. This must be a readable
- *                 buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data in Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx,
-                               const unsigned char *input,
-                               size_t ilen );
-
-/**
- * \brief          This function finishes the SHA-256 operation, and writes
- *                 the result to the output buffer.
- *
- * \param ctx      The SHA-256 context. This must be initialized
- *                 and have a hash operation started.
- * \param output   The SHA-224 or SHA-256 checksum result.
- *                 This must be a writable buffer of length \c 32 Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx,
-                               unsigned char output[32] );
-
-/**
- * \brief          This function processes a single data block within
- *                 the ongoing SHA-256 computation. This function is for
- *                 internal use only.
- *
- * \param ctx      The SHA-256 context. This must be initialized.
- * \param data     The buffer holding one block of data. This must
- *                 be a readable buffer of length \c 64 Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx,
-                                     const unsigned char data[64] );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          This function starts a SHA-224 or SHA-256 checksum
- *                 calculation.
- *
- * \deprecated     Superseded by mbedtls_sha256_starts_ret() in 2.7.0.
- *
- * \param ctx      The context to use. This must be initialized.
- * \param is224    Determines which function to use. This must be
- *                 either \c 0 for SHA-256, or \c 1 for SHA-224.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha256_starts( mbedtls_sha256_context *ctx,
-                                               int is224 );
-
-/**
- * \brief          This function feeds an input buffer into an ongoing
- *                 SHA-256 checksum calculation.
- *
- * \deprecated     Superseded by mbedtls_sha256_update_ret() in 2.7.0.
- *
- * \param ctx      The SHA-256 context to use. This must be
- *                 initialized and have a hash operation started.
- * \param input    The buffer holding the data. This must be a readable
- *                 buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data in Bytes.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha256_update( mbedtls_sha256_context *ctx,
-                                               const unsigned char *input,
-                                               size_t ilen );
-
-/**
- * \brief          This function finishes the SHA-256 operation, and writes
- *                 the result to the output buffer.
- *
- * \deprecated     Superseded by mbedtls_sha256_finish_ret() in 2.7.0.
- *
- * \param ctx      The SHA-256 context. This must be initialized and
- *                 have a hash operation started.
- * \param output   The SHA-224 or SHA-256 checksum result. This must be
- *                 a writable buffer of length \c 32 Bytes.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha256_finish( mbedtls_sha256_context *ctx,
-                                               unsigned char output[32] );
-
-/**
- * \brief          This function processes a single data block within
- *                 the ongoing SHA-256 computation. This function is for
- *                 internal use only.
- *
- * \deprecated     Superseded by mbedtls_internal_sha256_process() in 2.7.0.
- *
- * \param ctx      The SHA-256 context. This must be initialized.
- * \param data     The buffer holding one block of data. This must be
- *                 a readable buffer of size \c 64 Bytes.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha256_process( mbedtls_sha256_context *ctx,
-                                                const unsigned char data[64] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief          This function calculates the SHA-224 or SHA-256
- *                 checksum of a buffer.
- *
- *                 The function allocates the context, performs the
- *                 calculation, and frees the context.
- *
- *                 The SHA-256 result is calculated as
- *                 output = SHA-256(input buffer).
- *
- * \param input    The buffer holding the data. This must be a readable
- *                 buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data in Bytes.
- * \param output   The SHA-224 or SHA-256 checksum result. This must
- *                 be a writable buffer of length \c 32 Bytes.
- * \param is224    Determines which function to use. This must be
- *                 either \c 0 for SHA-256, or \c 1 for SHA-224.
- */
-int mbedtls_sha256_ret( const unsigned char *input,
-                        size_t ilen,
-                        unsigned char output[32],
-                        int is224 );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-
-/**
- * \brief          This function calculates the SHA-224 or SHA-256 checksum
- *                 of a buffer.
- *
- *                 The function allocates the context, performs the
- *                 calculation, and frees the context.
- *
- *                 The SHA-256 result is calculated as
- *                 output = SHA-256(input buffer).
- *
- * \deprecated     Superseded by mbedtls_sha256_ret() in 2.7.0.
- *
- * \param input    The buffer holding the data. This must be a readable
- *                 buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data in Bytes.
- * \param output   The SHA-224 or SHA-256 checksum result. This must be
- *                 a writable buffer of length \c 32 Bytes.
- * \param is224    Determines which function to use. This must be either
- *                 \c 0 for SHA-256, or \c 1 for SHA-224.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha256( const unsigned char *input,
-                                        size_t ilen,
-                                        unsigned char output[32],
-                                        int is224 );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          The SHA-224 and SHA-256 checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_sha256_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_sha256.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/sha512.h b/tools/sdk/include/mbedtls/mbedtls/sha512.h
deleted file mode 100644
index 2fbc69f80e6..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/sha512.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/**
- * \file sha512.h
- * \brief This file contains SHA-384 and SHA-512 definitions and functions.
- *
- * The Secure Hash Algorithms 384 and 512 (SHA-384 and SHA-512) cryptographic
- * hash functions are defined in <em>FIPS 180-4: Secure Hash Standard (SHS)</em>.
- */
-/*
- *  Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of Mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SHA512_H
-#define MBEDTLS_SHA512_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* MBEDTLS_ERR_SHA512_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_SHA512_HW_ACCEL_FAILED                -0x0039  /**< SHA-512 hardware accelerator failed */
-#define MBEDTLS_ERR_SHA512_BAD_INPUT_DATA                 -0x0075  /**< SHA-512 input data was malformed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_SHA512_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          The SHA-512 context structure.
- *
- *                 The structure is used both for SHA-384 and for SHA-512
- *                 checksum calculations. The choice between these two is
- *                 made in the call to mbedtls_sha512_starts_ret().
- */
-typedef struct mbedtls_sha512_context
-{
-    uint64_t total[2];          /*!< The number of Bytes processed. */
-    uint64_t state[8];          /*!< The intermediate digest state. */
-    unsigned char buffer[128];  /*!< The data block being processed. */
-    int is384;                  /*!< Determines which function to use:
-                                     0: Use SHA-512, or 1: Use SHA-384. */
-}
-mbedtls_sha512_context;
-
-#else  /* MBEDTLS_SHA512_ALT */
-#include "sha512_alt.h"
-#endif /* MBEDTLS_SHA512_ALT */
-
-/**
- * \brief          This function initializes a SHA-512 context.
- *
- * \param ctx      The SHA-512 context to initialize. This must
- *                 not be \c NULL.
- */
-void mbedtls_sha512_init( mbedtls_sha512_context *ctx );
-
-/**
- * \brief          This function clears a SHA-512 context.
- *
- * \param ctx      The SHA-512 context to clear. This may be \c NULL,
- *                 in which case this function does nothing. If it
- *                 is not \c NULL, it must point to an initialized
- *                 SHA-512 context.
- */
-void mbedtls_sha512_free( mbedtls_sha512_context *ctx );
-
-/**
- * \brief          This function clones the state of a SHA-512 context.
- *
- * \param dst      The destination context. This must be initialized.
- * \param src      The context to clone. This must be initialized.
- */
-void mbedtls_sha512_clone( mbedtls_sha512_context *dst,
-                           const mbedtls_sha512_context *src );
-
-/**
- * \brief          This function starts a SHA-384 or SHA-512 checksum
- *                 calculation.
- *
- * \param ctx      The SHA-512 context to use. This must be initialized.
- * \param is384    Determines which function to use. This must be
- *                 either \c for SHA-512, or \c 1 for SHA-384.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_sha512_starts_ret( mbedtls_sha512_context *ctx, int is384 );
-
-/**
- * \brief          This function feeds an input buffer into an ongoing
- *                 SHA-512 checksum calculation.
- *
- * \param ctx      The SHA-512 context. This must be initialized
- *                 and have a hash operation started.
- * \param input    The buffer holding the input data. This must
- *                 be a readable buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data in Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx,
-                    const unsigned char *input,
-                    size_t ilen );
-
-/**
- * \brief          This function finishes the SHA-512 operation, and writes
- *                 the result to the output buffer. This function is for
- *                 internal use only.
- *
- * \param ctx      The SHA-512 context. This must be initialized
- *                 and have a hash operation started.
- * \param output   The SHA-384 or SHA-512 checksum result.
- *                 This must be a writable buffer of length \c 64 Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx,
-                               unsigned char output[64] );
-
-/**
- * \brief          This function processes a single data block within
- *                 the ongoing SHA-512 computation.
- *
- * \param ctx      The SHA-512 context. This must be initialized.
- * \param data     The buffer holding one block of data. This
- *                 must be a readable buffer of length \c 128 Bytes.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_internal_sha512_process( mbedtls_sha512_context *ctx,
-                                     const unsigned char data[128] );
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-/**
- * \brief          This function starts a SHA-384 or SHA-512 checksum
- *                 calculation.
- *
- * \deprecated     Superseded by mbedtls_sha512_starts_ret() in 2.7.0
- *
- * \param ctx      The SHA-512 context to use. This must be initialized.
- * \param is384    Determines which function to use. This must be either
- *                 \c 0 for SHA-512 or \c 1 for SHA-384.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha512_starts( mbedtls_sha512_context *ctx,
-                                               int is384 );
-
-/**
- * \brief          This function feeds an input buffer into an ongoing
- *                 SHA-512 checksum calculation.
- *
- * \deprecated     Superseded by mbedtls_sha512_update_ret() in 2.7.0.
- *
- * \param ctx      The SHA-512 context. This must be initialized
- *                 and have a hash operation started.
- * \param input    The buffer holding the data. This must be a readable
- *                 buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data in Bytes.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha512_update( mbedtls_sha512_context *ctx,
-                                               const unsigned char *input,
-                                               size_t ilen );
-
-/**
- * \brief          This function finishes the SHA-512 operation, and writes
- *                 the result to the output buffer.
- *
- * \deprecated     Superseded by mbedtls_sha512_finish_ret() in 2.7.0.
- *
- * \param ctx      The SHA-512 context. This must be initialized
- *                 and have a hash operation started.
- * \param output   The SHA-384 or SHA-512 checksum result. This must
- *                 be a writable buffer of size \c 64 Bytes.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha512_finish( mbedtls_sha512_context *ctx,
-                                               unsigned char output[64] );
-
-/**
- * \brief          This function processes a single data block within
- *                 the ongoing SHA-512 computation. This function is for
- *                 internal use only.
- *
- * \deprecated     Superseded by mbedtls_internal_sha512_process() in 2.7.0.
- *
- * \param ctx      The SHA-512 context. This must be initialized.
- * \param data     The buffer holding one block of data. This must be
- *                 a readable buffer of length \c 128 Bytes.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha512_process(
-                                            mbedtls_sha512_context *ctx,
-                                            const unsigned char data[128] );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief          This function calculates the SHA-512 or SHA-384
- *                 checksum of a buffer.
- *
- *                 The function allocates the context, performs the
- *                 calculation, and frees the context.
- *
- *                 The SHA-512 result is calculated as
- *                 output = SHA-512(input buffer).
- *
- * \param input    The buffer holding the input data. This must be
- *                 a readable buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data in Bytes.
- * \param output   The SHA-384 or SHA-512 checksum result.
- *                 This must be a writable buffer of length \c 64 Bytes.
- * \param is384    Determines which function to use. This must be either
- *                 \c 0 for SHA-512, or \c 1 for SHA-384.
- *
- * \return         \c 0 on success.
- * \return         A negative error code on failure.
- */
-int mbedtls_sha512_ret( const unsigned char *input,
-                        size_t ilen,
-                        unsigned char output[64],
-                        int is384 );
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-
-/**
- * \brief          This function calculates the SHA-512 or SHA-384
- *                 checksum of a buffer.
- *
- *                 The function allocates the context, performs the
- *                 calculation, and frees the context.
- *
- *                 The SHA-512 result is calculated as
- *                 output = SHA-512(input buffer).
- *
- * \deprecated     Superseded by mbedtls_sha512_ret() in 2.7.0
- *
- * \param input    The buffer holding the data. This must be a
- *                 readable buffer of length \p ilen Bytes.
- * \param ilen     The length of the input data in Bytes.
- * \param output   The SHA-384 or SHA-512 checksum result. This must
- *                 be a writable buffer of length \c 64 Bytes.
- * \param is384    Determines which function to use. This must be either
- *                 \c 0 for SHA-512, or \c 1 for SHA-384.
- */
-MBEDTLS_DEPRECATED void mbedtls_sha512( const unsigned char *input,
-                                        size_t ilen,
-                                        unsigned char output[64],
-                                        int is384 );
-
-#undef MBEDTLS_DEPRECATED
-#endif /* !MBEDTLS_DEPRECATED_REMOVED */
-
-#if defined(MBEDTLS_SELF_TEST)
-
- /**
- * \brief          The SHA-384 or SHA-512 checkup routine.
- *
- * \return         \c 0 on success.
- * \return         \c 1 on failure.
- */
-int mbedtls_sha512_self_test( int verbose );
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_sha512.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl.h b/tools/sdk/include/mbedtls/mbedtls/ssl.h
deleted file mode 100644
index 6f56983562e..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ssl.h
+++ /dev/null
@@ -1,3293 +0,0 @@
-/**
- * \file ssl.h
- *
- * \brief SSL/TLS functions.
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SSL_H
-#define MBEDTLS_SSL_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "bignum.h"
-#include "ecp.h"
-
-#include "ssl_ciphersuites.h"
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-#include "x509_crt.h"
-#include "x509_crl.h"
-#endif
-
-#if defined(MBEDTLS_DHM_C)
-#include "dhm.h"
-#endif
-
-#if defined(MBEDTLS_ECDH_C)
-#include "ecdh.h"
-#endif
-
-#if defined(MBEDTLS_ZLIB_SUPPORT)
-
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#warning "Record compression support via MBEDTLS_ZLIB_SUPPORT is deprecated and will be removed in the next major revision of the library"
-#endif
-
-#if defined(MBEDTLS_DEPRECATED_REMOVED)
-#error "Record compression support via MBEDTLS_ZLIB_SUPPORT is deprecated and cannot be used if MBEDTLS_DEPRECATED_REMOVED is set"
-#endif
-
-#include "zlib.h"
-#endif
-
-#if defined(MBEDTLS_HAVE_TIME)
-#include "platform_time.h"
-#endif
-
-/*
- * SSL Error codes
- */
-#define MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE               -0x7080  /**< The requested feature is not available. */
-#define MBEDTLS_ERR_SSL_BAD_INPUT_DATA                    -0x7100  /**< Bad input parameters to function. */
-#define MBEDTLS_ERR_SSL_INVALID_MAC                       -0x7180  /**< Verification of the message MAC failed. */
-#define MBEDTLS_ERR_SSL_INVALID_RECORD                    -0x7200  /**< An invalid SSL record was received. */
-#define MBEDTLS_ERR_SSL_CONN_EOF                          -0x7280  /**< The connection indicated an EOF. */
-#define MBEDTLS_ERR_SSL_UNKNOWN_CIPHER                    -0x7300  /**< An unknown cipher was received. */
-#define MBEDTLS_ERR_SSL_NO_CIPHER_CHOSEN                  -0x7380  /**< The server has no ciphersuites in common with the client. */
-#define MBEDTLS_ERR_SSL_NO_RNG                            -0x7400  /**< No RNG was provided to the SSL module. */
-#define MBEDTLS_ERR_SSL_NO_CLIENT_CERTIFICATE             -0x7480  /**< No client certification received from the client, but required by the authentication mode. */
-#define MBEDTLS_ERR_SSL_CERTIFICATE_TOO_LARGE             -0x7500  /**< Our own certificate(s) is/are too large to send in an SSL message. */
-#define MBEDTLS_ERR_SSL_CERTIFICATE_REQUIRED              -0x7580  /**< The own certificate is not set, but needed by the server. */
-#define MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED              -0x7600  /**< The own private key or pre-shared key is not set, but needed. */
-#define MBEDTLS_ERR_SSL_CA_CHAIN_REQUIRED                 -0x7680  /**< No CA Chain is set, but required to operate. */
-#define MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE                -0x7700  /**< An unexpected message was received from our peer. */
-#define MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE               -0x7780  /**< A fatal alert message was received from our peer. */
-#define MBEDTLS_ERR_SSL_PEER_VERIFY_FAILED                -0x7800  /**< Verification of our peer failed. */
-#define MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY                 -0x7880  /**< The peer notified us that the connection is going to be closed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO               -0x7900  /**< Processing of the ClientHello handshake message failed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO               -0x7980  /**< Processing of the ServerHello handshake message failed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE                -0x7A00  /**< Processing of the Certificate handshake message failed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_REQUEST        -0x7A80  /**< Processing of the CertificateRequest handshake message failed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE        -0x7B00  /**< Processing of the ServerKeyExchange handshake message failed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO_DONE          -0x7B80  /**< Processing of the ServerHelloDone handshake message failed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE        -0x7C00  /**< Processing of the ClientKeyExchange handshake message failed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_RP     -0x7C80  /**< Processing of the ClientKeyExchange handshake message failed in DHM / ECDH Read Public. */
-#define MBEDTLS_ERR_SSL_BAD_HS_CLIENT_KEY_EXCHANGE_CS     -0x7D00  /**< Processing of the ClientKeyExchange handshake message failed in DHM / ECDH Calculate Secret. */
-#define MBEDTLS_ERR_SSL_BAD_HS_CERTIFICATE_VERIFY         -0x7D80  /**< Processing of the CertificateVerify handshake message failed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_CHANGE_CIPHER_SPEC         -0x7E00  /**< Processing of the ChangeCipherSpec handshake message failed. */
-#define MBEDTLS_ERR_SSL_BAD_HS_FINISHED                   -0x7E80  /**< Processing of the Finished handshake message failed. */
-#define MBEDTLS_ERR_SSL_ALLOC_FAILED                      -0x7F00  /**< Memory allocation failed */
-#define MBEDTLS_ERR_SSL_HW_ACCEL_FAILED                   -0x7F80  /**< Hardware acceleration function returned with error */
-#define MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH              -0x6F80  /**< Hardware acceleration function skipped / left alone data */
-#define MBEDTLS_ERR_SSL_COMPRESSION_FAILED                -0x6F00  /**< Processing of the compression / decompression failed */
-#define MBEDTLS_ERR_SSL_BAD_HS_PROTOCOL_VERSION           -0x6E80  /**< Handshake protocol not within min/max boundaries */
-#define MBEDTLS_ERR_SSL_BAD_HS_NEW_SESSION_TICKET         -0x6E00  /**< Processing of the NewSessionTicket handshake message failed. */
-#define MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED            -0x6D80  /**< Session ticket has expired. */
-#define MBEDTLS_ERR_SSL_PK_TYPE_MISMATCH                  -0x6D00  /**< Public key type mismatch (eg, asked for RSA key exchange and presented EC key) */
-#define MBEDTLS_ERR_SSL_UNKNOWN_IDENTITY                  -0x6C80  /**< Unknown identity received (eg, PSK identity) */
-#define MBEDTLS_ERR_SSL_INTERNAL_ERROR                    -0x6C00  /**< Internal error (eg, unexpected failure in lower-level module) */
-#define MBEDTLS_ERR_SSL_COUNTER_WRAPPING                  -0x6B80  /**< A counter would wrap (eg, too many messages exchanged). */
-#define MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO       -0x6B00  /**< Unexpected message at ServerHello in renegotiation. */
-#define MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED             -0x6A80  /**< DTLS client must retry for hello verification */
-#define MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL                  -0x6A00  /**< A buffer is too small to receive or write a message */
-#define MBEDTLS_ERR_SSL_NO_USABLE_CIPHERSUITE             -0x6980  /**< None of the common ciphersuites is usable (eg, no suitable certificate, see debug messages). */
-#define MBEDTLS_ERR_SSL_WANT_READ                         -0x6900  /**< No data of requested type currently available on underlying transport. */
-#define MBEDTLS_ERR_SSL_WANT_WRITE                        -0x6880  /**< Connection requires a write call. */
-#define MBEDTLS_ERR_SSL_TIMEOUT                           -0x6800  /**< The operation timed out. */
-#define MBEDTLS_ERR_SSL_CLIENT_RECONNECT                  -0x6780  /**< The client initiated a reconnect from the same port. */
-#define MBEDTLS_ERR_SSL_UNEXPECTED_RECORD                 -0x6700  /**< Record header looks valid but is not expected. */
-#define MBEDTLS_ERR_SSL_NON_FATAL                         -0x6680  /**< The alert message received indicates a non-fatal error. */
-#define MBEDTLS_ERR_SSL_INVALID_VERIFY_HASH               -0x6600  /**< Couldn't set the hash for verifying CertificateVerify */
-#define MBEDTLS_ERR_SSL_CONTINUE_PROCESSING               -0x6580  /**< Internal-only message signaling that further message-processing should be done */
-#define MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS                 -0x6500  /**< The asynchronous operation is not completed yet. */
-#define MBEDTLS_ERR_SSL_EARLY_MESSAGE                     -0x6480  /**< Internal-only message signaling that a message arrived early. */
-#define MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS                -0x7000  /**< A cryptographic operation is in progress. Try again later. */
-#define MBEDTLS_ERR_SSL_BAD_CONFIG                        -0x5E80  /**< Invalid value in SSL config */
-
-/*
- * Various constants
- */
-#define MBEDTLS_SSL_MAJOR_VERSION_3             3
-#define MBEDTLS_SSL_MINOR_VERSION_0             0   /*!< SSL v3.0 */
-#define MBEDTLS_SSL_MINOR_VERSION_1             1   /*!< TLS v1.0 */
-#define MBEDTLS_SSL_MINOR_VERSION_2             2   /*!< TLS v1.1 */
-#define MBEDTLS_SSL_MINOR_VERSION_3             3   /*!< TLS v1.2 */
-
-#define MBEDTLS_SSL_TRANSPORT_STREAM            0   /*!< TLS      */
-#define MBEDTLS_SSL_TRANSPORT_DATAGRAM          1   /*!< DTLS     */
-
-#define MBEDTLS_SSL_MAX_HOST_NAME_LEN           255 /*!< Maximum host name defined in RFC 1035 */
-#define MBEDTLS_SSL_MAX_ALPN_NAME_LEN           255 /*!< Maximum size in bytes of a protocol name in alpn ext., RFC 7301 */
-
-#define MBEDTLS_SSL_MAX_ALPN_LIST_LEN           65535 /*!< Maximum size in bytes of list in alpn ext., RFC 7301          */
-
-/* RFC 6066 section 4, see also mfl_code_to_length in ssl_tls.c
- * NONE must be zero so that memset()ing structure to zero works */
-#define MBEDTLS_SSL_MAX_FRAG_LEN_NONE           0   /*!< don't use this extension   */
-#define MBEDTLS_SSL_MAX_FRAG_LEN_512            1   /*!< MaxFragmentLength 2^9      */
-#define MBEDTLS_SSL_MAX_FRAG_LEN_1024           2   /*!< MaxFragmentLength 2^10     */
-#define MBEDTLS_SSL_MAX_FRAG_LEN_2048           3   /*!< MaxFragmentLength 2^11     */
-#define MBEDTLS_SSL_MAX_FRAG_LEN_4096           4   /*!< MaxFragmentLength 2^12     */
-#define MBEDTLS_SSL_MAX_FRAG_LEN_INVALID        5   /*!< first invalid value        */
-
-#define MBEDTLS_SSL_IS_CLIENT                   0
-#define MBEDTLS_SSL_IS_SERVER                   1
-
-#define MBEDTLS_SSL_IS_NOT_FALLBACK             0
-#define MBEDTLS_SSL_IS_FALLBACK                 1
-
-#define MBEDTLS_SSL_EXTENDED_MS_DISABLED        0
-#define MBEDTLS_SSL_EXTENDED_MS_ENABLED         1
-
-#define MBEDTLS_SSL_ETM_DISABLED                0
-#define MBEDTLS_SSL_ETM_ENABLED                 1
-
-#define MBEDTLS_SSL_COMPRESS_NULL               0
-#define MBEDTLS_SSL_COMPRESS_DEFLATE            1
-
-#define MBEDTLS_SSL_VERIFY_NONE                 0
-#define MBEDTLS_SSL_VERIFY_OPTIONAL             1
-#define MBEDTLS_SSL_VERIFY_REQUIRED             2
-#define MBEDTLS_SSL_VERIFY_UNSET                3 /* Used only for sni_authmode */
-
-#define MBEDTLS_SSL_LEGACY_RENEGOTIATION        0
-#define MBEDTLS_SSL_SECURE_RENEGOTIATION        1
-
-#define MBEDTLS_SSL_RENEGOTIATION_DISABLED      0
-#define MBEDTLS_SSL_RENEGOTIATION_ENABLED       1
-
-#define MBEDTLS_SSL_ANTI_REPLAY_DISABLED        0
-#define MBEDTLS_SSL_ANTI_REPLAY_ENABLED         1
-
-#define MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED  -1
-#define MBEDTLS_SSL_RENEGO_MAX_RECORDS_DEFAULT  16
-
-#define MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION     0
-#define MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION  1
-#define MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE      2
-
-#define MBEDTLS_SSL_TRUNC_HMAC_DISABLED         0
-#define MBEDTLS_SSL_TRUNC_HMAC_ENABLED          1
-#define MBEDTLS_SSL_TRUNCATED_HMAC_LEN          10  /* 80 bits, rfc 6066 section 7 */
-
-#define MBEDTLS_SSL_SESSION_TICKETS_DISABLED     0
-#define MBEDTLS_SSL_SESSION_TICKETS_ENABLED      1
-
-#define MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED    0
-#define MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED     1
-
-#define MBEDTLS_SSL_ARC4_ENABLED                0
-#define MBEDTLS_SSL_ARC4_DISABLED               1
-
-#define MBEDTLS_SSL_PRESET_DEFAULT              0
-#define MBEDTLS_SSL_PRESET_SUITEB               2
-
-#define MBEDTLS_SSL_CERT_REQ_CA_LIST_ENABLED       1
-#define MBEDTLS_SSL_CERT_REQ_CA_LIST_DISABLED      0
-
-/*
- * Default range for DTLS retransmission timer value, in milliseconds.
- * RFC 6347 4.2.4.1 says from 1 second to 60 seconds.
- */
-#define MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MIN    1000
-#define MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MAX   60000
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h or define them on the compiler command line.
- * \{
- */
-
-#if !defined(MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME)
-#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME     86400 /**< Lifetime of session tickets (if enabled) */
-#endif
-
-/*
- * Maximum fragment length in bytes,
- * determines the size of each of the two internal I/O buffers.
- *
- * Note: the RFC defines the default size of SSL / TLS messages. If you
- * change the value here, other clients / servers may not be able to
- * communicate with you anymore. Only change this value if you control
- * both sides of the connection and have it reduced at both sides, or
- * if you're using the Max Fragment Length extension and you know all your
- * peers are using it too!
- */
-#if !defined(MBEDTLS_SSL_MAX_CONTENT_LEN)
-#define MBEDTLS_SSL_MAX_CONTENT_LEN         16384   /**< Size of the input / output buffer */
-#endif
-
-#if !defined(MBEDTLS_SSL_IN_CONTENT_LEN)
-#define MBEDTLS_SSL_IN_CONTENT_LEN MBEDTLS_SSL_MAX_CONTENT_LEN
-#endif
-
-#if !defined(MBEDTLS_SSL_OUT_CONTENT_LEN)
-#define MBEDTLS_SSL_OUT_CONTENT_LEN MBEDTLS_SSL_MAX_CONTENT_LEN
-#endif
-
-/*
- * Maximum number of heap-allocated bytes for the purpose of
- * DTLS handshake message reassembly and future message buffering.
- */
-#if !defined(MBEDTLS_SSL_DTLS_MAX_BUFFERING)
-#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768
-#endif
-
-/* \} name SECTION: Module settings */
-
-/*
- * Length of the verify data for secure renegotiation
- */
-#if defined(MBEDTLS_SSL_PROTO_SSL3)
-#define MBEDTLS_SSL_VERIFY_DATA_MAX_LEN 36
-#else
-#define MBEDTLS_SSL_VERIFY_DATA_MAX_LEN 12
-#endif
-
-/*
- * Signaling ciphersuite values (SCSV)
- */
-#define MBEDTLS_SSL_EMPTY_RENEGOTIATION_INFO    0xFF   /**< renegotiation info ext */
-#define MBEDTLS_SSL_FALLBACK_SCSV_VALUE         0x5600 /**< RFC 7507 section 2 */
-
-/*
- * Supported Signature and Hash algorithms (For TLS 1.2)
- * RFC 5246 section 7.4.1.4.1
- */
-#define MBEDTLS_SSL_HASH_NONE                0
-#define MBEDTLS_SSL_HASH_MD5                 1
-#define MBEDTLS_SSL_HASH_SHA1                2
-#define MBEDTLS_SSL_HASH_SHA224              3
-#define MBEDTLS_SSL_HASH_SHA256              4
-#define MBEDTLS_SSL_HASH_SHA384              5
-#define MBEDTLS_SSL_HASH_SHA512              6
-
-#define MBEDTLS_SSL_SIG_ANON                 0
-#define MBEDTLS_SSL_SIG_RSA                  1
-#define MBEDTLS_SSL_SIG_ECDSA                3
-
-/*
- * Client Certificate Types
- * RFC 5246 section 7.4.4 plus RFC 4492 section 5.5
- */
-#define MBEDTLS_SSL_CERT_TYPE_RSA_SIGN       1
-#define MBEDTLS_SSL_CERT_TYPE_ECDSA_SIGN    64
-
-/*
- * Message, alert and handshake types
- */
-#define MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC     20
-#define MBEDTLS_SSL_MSG_ALERT                  21
-#define MBEDTLS_SSL_MSG_HANDSHAKE              22
-#define MBEDTLS_SSL_MSG_APPLICATION_DATA       23
-
-#define MBEDTLS_SSL_ALERT_LEVEL_WARNING         1
-#define MBEDTLS_SSL_ALERT_LEVEL_FATAL           2
-
-#define MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY           0  /* 0x00 */
-#define MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE    10  /* 0x0A */
-#define MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC        20  /* 0x14 */
-#define MBEDTLS_SSL_ALERT_MSG_DECRYPTION_FAILED     21  /* 0x15 */
-#define MBEDTLS_SSL_ALERT_MSG_RECORD_OVERFLOW       22  /* 0x16 */
-#define MBEDTLS_SSL_ALERT_MSG_DECOMPRESSION_FAILURE 30  /* 0x1E */
-#define MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE     40  /* 0x28 */
-#define MBEDTLS_SSL_ALERT_MSG_NO_CERT               41  /* 0x29 */
-#define MBEDTLS_SSL_ALERT_MSG_BAD_CERT              42  /* 0x2A */
-#define MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_CERT      43  /* 0x2B */
-#define MBEDTLS_SSL_ALERT_MSG_CERT_REVOKED          44  /* 0x2C */
-#define MBEDTLS_SSL_ALERT_MSG_CERT_EXPIRED          45  /* 0x2D */
-#define MBEDTLS_SSL_ALERT_MSG_CERT_UNKNOWN          46  /* 0x2E */
-#define MBEDTLS_SSL_ALERT_MSG_ILLEGAL_PARAMETER     47  /* 0x2F */
-#define MBEDTLS_SSL_ALERT_MSG_UNKNOWN_CA            48  /* 0x30 */
-#define MBEDTLS_SSL_ALERT_MSG_ACCESS_DENIED         49  /* 0x31 */
-#define MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR          50  /* 0x32 */
-#define MBEDTLS_SSL_ALERT_MSG_DECRYPT_ERROR         51  /* 0x33 */
-#define MBEDTLS_SSL_ALERT_MSG_EXPORT_RESTRICTION    60  /* 0x3C */
-#define MBEDTLS_SSL_ALERT_MSG_PROTOCOL_VERSION      70  /* 0x46 */
-#define MBEDTLS_SSL_ALERT_MSG_INSUFFICIENT_SECURITY 71  /* 0x47 */
-#define MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR        80  /* 0x50 */
-#define MBEDTLS_SSL_ALERT_MSG_INAPROPRIATE_FALLBACK 86  /* 0x56 */
-#define MBEDTLS_SSL_ALERT_MSG_USER_CANCELED         90  /* 0x5A */
-#define MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION     100  /* 0x64 */
-#define MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_EXT      110  /* 0x6E */
-#define MBEDTLS_SSL_ALERT_MSG_UNRECOGNIZED_NAME    112  /* 0x70 */
-#define MBEDTLS_SSL_ALERT_MSG_UNKNOWN_PSK_IDENTITY 115  /* 0x73 */
-#define MBEDTLS_SSL_ALERT_MSG_NO_APPLICATION_PROTOCOL 120 /* 0x78 */
-
-#define MBEDTLS_SSL_HS_HELLO_REQUEST            0
-#define MBEDTLS_SSL_HS_CLIENT_HELLO             1
-#define MBEDTLS_SSL_HS_SERVER_HELLO             2
-#define MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST     3
-#define MBEDTLS_SSL_HS_NEW_SESSION_TICKET       4
-#define MBEDTLS_SSL_HS_CERTIFICATE             11
-#define MBEDTLS_SSL_HS_SERVER_KEY_EXCHANGE     12
-#define MBEDTLS_SSL_HS_CERTIFICATE_REQUEST     13
-#define MBEDTLS_SSL_HS_SERVER_HELLO_DONE       14
-#define MBEDTLS_SSL_HS_CERTIFICATE_VERIFY      15
-#define MBEDTLS_SSL_HS_CLIENT_KEY_EXCHANGE     16
-#define MBEDTLS_SSL_HS_FINISHED                20
-
-/*
- * TLS extensions
- */
-#define MBEDTLS_TLS_EXT_SERVERNAME                   0
-#define MBEDTLS_TLS_EXT_SERVERNAME_HOSTNAME          0
-
-#define MBEDTLS_TLS_EXT_MAX_FRAGMENT_LENGTH          1
-
-#define MBEDTLS_TLS_EXT_TRUNCATED_HMAC               4
-
-#define MBEDTLS_TLS_EXT_SUPPORTED_ELLIPTIC_CURVES   10
-#define MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS     11
-
-#define MBEDTLS_TLS_EXT_SIG_ALG                     13
-
-#define MBEDTLS_TLS_EXT_ALPN                        16
-
-#define MBEDTLS_TLS_EXT_ENCRYPT_THEN_MAC            22 /* 0x16 */
-#define MBEDTLS_TLS_EXT_EXTENDED_MASTER_SECRET  0x0017 /* 23 */
-
-#define MBEDTLS_TLS_EXT_SESSION_TICKET              35
-
-#define MBEDTLS_TLS_EXT_ECJPAKE_KKPP               256 /* experimental */
-
-#define MBEDTLS_TLS_EXT_RENEGOTIATION_INFO      0xFF01
-
-/*
- * Size defines
- */
-#if !defined(MBEDTLS_PSK_MAX_LEN)
-#define MBEDTLS_PSK_MAX_LEN            32 /* 256 bits */
-#endif
-
-/* Dummy type used only for its size */
-union mbedtls_ssl_premaster_secret
-{
-#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED)
-    unsigned char _pms_rsa[48];                         /* RFC 5246 8.1.1 */
-#endif
-#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)
-    unsigned char _pms_dhm[MBEDTLS_MPI_MAX_SIZE];      /* RFC 5246 8.1.2 */
-#endif
-#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)    || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)  || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED)     || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED)
-    unsigned char _pms_ecdh[MBEDTLS_ECP_MAX_BYTES];    /* RFC 4492 5.10 */
-#endif
-#if defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED)
-    unsigned char _pms_psk[4 + 2 * MBEDTLS_PSK_MAX_LEN];       /* RFC 4279 2 */
-#endif
-#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED)
-    unsigned char _pms_dhe_psk[4 + MBEDTLS_MPI_MAX_SIZE
-                                 + MBEDTLS_PSK_MAX_LEN];       /* RFC 4279 3 */
-#endif
-#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED)
-    unsigned char _pms_rsa_psk[52 + MBEDTLS_PSK_MAX_LEN];      /* RFC 4279 4 */
-#endif
-#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED)
-    unsigned char _pms_ecdhe_psk[4 + MBEDTLS_ECP_MAX_BYTES
-                                   + MBEDTLS_PSK_MAX_LEN];     /* RFC 5489 2 */
-#endif
-#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
-    unsigned char _pms_ecjpake[32];     /* Thread spec: SHA-256 output */
-#endif
-};
-
-#define MBEDTLS_PREMASTER_SIZE     sizeof( union mbedtls_ssl_premaster_secret )
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * SSL state machine
- */
-typedef enum
-{
-    MBEDTLS_SSL_HELLO_REQUEST,
-    MBEDTLS_SSL_CLIENT_HELLO,
-    MBEDTLS_SSL_SERVER_HELLO,
-    MBEDTLS_SSL_SERVER_CERTIFICATE,
-    MBEDTLS_SSL_SERVER_KEY_EXCHANGE,
-    MBEDTLS_SSL_CERTIFICATE_REQUEST,
-    MBEDTLS_SSL_SERVER_HELLO_DONE,
-    MBEDTLS_SSL_CLIENT_CERTIFICATE,
-    MBEDTLS_SSL_CLIENT_KEY_EXCHANGE,
-    MBEDTLS_SSL_CERTIFICATE_VERIFY,
-    MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC,
-    MBEDTLS_SSL_CLIENT_FINISHED,
-    MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC,
-    MBEDTLS_SSL_SERVER_FINISHED,
-    MBEDTLS_SSL_FLUSH_BUFFERS,
-    MBEDTLS_SSL_HANDSHAKE_WRAPUP,
-    MBEDTLS_SSL_HANDSHAKE_OVER,
-    MBEDTLS_SSL_SERVER_NEW_SESSION_TICKET,
-    MBEDTLS_SSL_SERVER_HELLO_VERIFY_REQUEST_SENT,
-}
-mbedtls_ssl_states;
-
-/**
- * \brief          Callback type: send data on the network.
- *
- * \note           That callback may be either blocking or non-blocking.
- *
- * \param ctx      Context for the send callback (typically a file descriptor)
- * \param buf      Buffer holding the data to send
- * \param len      Length of the data to send
- *
- * \return         The callback must return the number of bytes sent if any,
- *                 or a non-zero error code.
- *                 If performing non-blocking I/O, \c MBEDTLS_ERR_SSL_WANT_WRITE
- *                 must be returned when the operation would block.
- *
- * \note           The callback is allowed to send fewer bytes than requested.
- *                 It must always return the number of bytes actually sent.
- */
-typedef int mbedtls_ssl_send_t( void *ctx,
-                                const unsigned char *buf,
-                                size_t len );
-
-/**
- * \brief          Callback type: receive data from the network.
- *
- * \note           That callback may be either blocking or non-blocking.
- *
- * \param ctx      Context for the receive callback (typically a file
- *                 descriptor)
- * \param buf      Buffer to write the received data to
- * \param len      Length of the receive buffer
- *
- * \return         The callback must return the number of bytes received,
- *                 or a non-zero error code.
- *                 If performing non-blocking I/O, \c MBEDTLS_ERR_SSL_WANT_READ
- *                 must be returned when the operation would block.
- *
- * \note           The callback may receive fewer bytes than the length of the
- *                 buffer. It must always return the number of bytes actually
- *                 received and written to the buffer.
- */
-typedef int mbedtls_ssl_recv_t( void *ctx,
-                                unsigned char *buf,
-                                size_t len );
-
-/**
- * \brief          Callback type: receive data from the network, with timeout
- *
- * \note           That callback must block until data is received, or the
- *                 timeout delay expires, or the operation is interrupted by a
- *                 signal.
- *
- * \param ctx      Context for the receive callback (typically a file descriptor)
- * \param buf      Buffer to write the received data to
- * \param len      Length of the receive buffer
- * \param timeout  Maximum nomber of millisecondes to wait for data
- *                 0 means no timeout (potentially waiting forever)
- *
- * \return         The callback must return the number of bytes received,
- *                 or a non-zero error code:
- *                 \c MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out,
- *                 \c MBEDTLS_ERR_SSL_WANT_READ if interrupted by a signal.
- *
- * \note           The callback may receive fewer bytes than the length of the
- *                 buffer. It must always return the number of bytes actually
- *                 received and written to the buffer.
- */
-typedef int mbedtls_ssl_recv_timeout_t( void *ctx,
-                                        unsigned char *buf,
-                                        size_t len,
-                                        uint32_t timeout );
-/**
- * \brief          Callback type: set a pair of timers/delays to watch
- *
- * \param ctx      Context pointer
- * \param int_ms   Intermediate delay in milliseconds
- * \param fin_ms   Final delay in milliseconds
- *                 0 cancels the current timer.
- *
- * \note           This callback must at least store the necessary information
- *                 for the associated \c mbedtls_ssl_get_timer_t callback to
- *                 return correct information.
- *
- * \note           If using a event-driven style of programming, an event must
- *                 be generated when the final delay is passed. The event must
- *                 cause a call to \c mbedtls_ssl_handshake() with the proper
- *                 SSL context to be scheduled. Care must be taken to ensure
- *                 that at most one such call happens at a time.
- *
- * \note           Only one timer at a time must be running. Calling this
- *                 function while a timer is running must cancel it. Cancelled
- *                 timers must not generate any event.
- */
-typedef void mbedtls_ssl_set_timer_t( void * ctx,
-                                      uint32_t int_ms,
-                                      uint32_t fin_ms );
-
-/**
- * \brief          Callback type: get status of timers/delays
- *
- * \param ctx      Context pointer
- *
- * \return         This callback must return:
- *                 -1 if cancelled (fin_ms == 0),
- *                  0 if none of the delays have passed,
- *                  1 if only the intermediate delay has passed,
- *                  2 if the final delay has passed.
- */
-typedef int mbedtls_ssl_get_timer_t( void * ctx );
-
-/* Defined below */
-typedef struct mbedtls_ssl_session mbedtls_ssl_session;
-typedef struct mbedtls_ssl_context mbedtls_ssl_context;
-typedef struct mbedtls_ssl_config  mbedtls_ssl_config;
-
-/* Defined in ssl_internal.h */
-typedef struct mbedtls_ssl_transform mbedtls_ssl_transform;
-typedef struct mbedtls_ssl_handshake_params mbedtls_ssl_handshake_params;
-typedef struct mbedtls_ssl_sig_hash_set_t mbedtls_ssl_sig_hash_set_t;
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-typedef struct mbedtls_ssl_key_cert mbedtls_ssl_key_cert;
-#endif
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-typedef struct mbedtls_ssl_flight_item mbedtls_ssl_flight_item;
-#endif
-
-#if defined(MBEDTLS_SSL_ASYNC_PRIVATE)
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-/**
- * \brief           Callback type: start external signature operation.
- *
- *                  This callback is called during an SSL handshake to start
- *                  a signature decryption operation using an
- *                  external processor. The parameter \p cert contains
- *                  the public key; it is up to the callback function to
- *                  determine how to access the associated private key.
- *
- *                  This function typically sends or enqueues a request, and
- *                  does not wait for the operation to complete. This allows
- *                  the handshake step to be non-blocking.
- *
- *                  The parameters \p ssl and \p cert are guaranteed to remain
- *                  valid throughout the handshake. On the other hand, this
- *                  function must save the contents of \p hash if the value
- *                  is needed for later processing, because the \p hash buffer
- *                  is no longer valid after this function returns.
- *
- *                  This function may call mbedtls_ssl_set_async_operation_data()
- *                  to store an operation context for later retrieval
- *                  by the resume or cancel callback.
- *
- * \note            For RSA signatures, this function must produce output
- *                  that is consistent with PKCS#1 v1.5 in the same way as
- *                  mbedtls_rsa_pkcs1_sign(). Before the private key operation,
- *                  apply the padding steps described in RFC 8017, section 9.2
- *                  "EMSA-PKCS1-v1_5" as follows.
- *                  - If \p md_alg is #MBEDTLS_MD_NONE, apply the PKCS#1 v1.5
- *                    encoding, treating \p hash as the DigestInfo to be
- *                    padded. In other words, apply EMSA-PKCS1-v1_5 starting
- *                    from step 3, with `T = hash` and `tLen = hash_len`.
- *                  - If `md_alg != MBEDTLS_MD_NONE`, apply the PKCS#1 v1.5
- *                    encoding, treating \p hash as the hash to be encoded and
- *                    padded. In other words, apply EMSA-PKCS1-v1_5 starting
- *                    from step 2, with `digestAlgorithm` obtained by calling
- *                    mbedtls_oid_get_oid_by_md() on \p md_alg.
- *
- * \note            For ECDSA signatures, the output format is the DER encoding
- *                  `Ecdsa-Sig-Value` defined in
- *                  [RFC 4492 section 5.4](https://tools.ietf.org/html/rfc4492#section-5.4).
- *
- * \param ssl             The SSL connection instance. It should not be
- *                        modified other than via
- *                        mbedtls_ssl_set_async_operation_data().
- * \param cert            Certificate containing the public key.
- *                        In simple cases, this is one of the pointers passed to
- *                        mbedtls_ssl_conf_own_cert() when configuring the SSL
- *                        connection. However, if other callbacks are used, this
- *                        property may not hold. For example, if an SNI callback
- *                        is registered with mbedtls_ssl_conf_sni(), then
- *                        this callback determines what certificate is used.
- * \param md_alg          Hash algorithm.
- * \param hash            Buffer containing the hash. This buffer is
- *                        no longer valid when the function returns.
- * \param hash_len        Size of the \c hash buffer in bytes.
- *
- * \return          0 if the operation was started successfully and the SSL
- *                  stack should call the resume callback immediately.
- * \return          #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if the operation
- *                  was started successfully and the SSL stack should return
- *                  immediately without calling the resume callback yet.
- * \return          #MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH if the external
- *                  processor does not support this key. The SSL stack will
- *                  use the private key object instead.
- * \return          Any other error indicates a fatal failure and is
- *                  propagated up the call chain. The callback should
- *                  use \c MBEDTLS_ERR_PK_xxx error codes, and <b>must not</b>
- *                  use \c MBEDTLS_ERR_SSL_xxx error codes except as
- *                  directed in the documentation of this callback.
- */
-typedef int mbedtls_ssl_async_sign_t( mbedtls_ssl_context *ssl,
-                                      mbedtls_x509_crt *cert,
-                                      mbedtls_md_type_t md_alg,
-                                      const unsigned char *hash,
-                                      size_t hash_len );
-
-/**
- * \brief           Callback type: start external decryption operation.
- *
- *                  This callback is called during an SSL handshake to start
- *                  an RSA decryption operation using an
- *                  external processor. The parameter \p cert contains
- *                  the public key; it is up to the callback function to
- *                  determine how to access the associated private key.
- *
- *                  This function typically sends or enqueues a request, and
- *                  does not wait for the operation to complete. This allows
- *                  the handshake step to be non-blocking.
- *
- *                  The parameters \p ssl and \p cert are guaranteed to remain
- *                  valid throughout the handshake. On the other hand, this
- *                  function must save the contents of \p input if the value
- *                  is needed for later processing, because the \p input buffer
- *                  is no longer valid after this function returns.
- *
- *                  This function may call mbedtls_ssl_set_async_operation_data()
- *                  to store an operation context for later retrieval
- *                  by the resume or cancel callback.
- *
- * \warning         RSA decryption as used in TLS is subject to a potential
- *                  timing side channel attack first discovered by Bleichenbacher
- *                  in 1998. This attack can be remotely exploitable
- *                  in practice. To avoid this attack, you must ensure that
- *                  if the callback performs an RSA decryption, the time it
- *                  takes to execute and return the result does not depend
- *                  on whether the RSA decryption succeeded or reported
- *                  invalid padding.
- *
- * \param ssl             The SSL connection instance. It should not be
- *                        modified other than via
- *                        mbedtls_ssl_set_async_operation_data().
- * \param cert            Certificate containing the public key.
- *                        In simple cases, this is one of the pointers passed to
- *                        mbedtls_ssl_conf_own_cert() when configuring the SSL
- *                        connection. However, if other callbacks are used, this
- *                        property may not hold. For example, if an SNI callback
- *                        is registered with mbedtls_ssl_conf_sni(), then
- *                        this callback determines what certificate is used.
- * \param input           Buffer containing the input ciphertext. This buffer
- *                        is no longer valid when the function returns.
- * \param input_len       Size of the \p input buffer in bytes.
- *
- * \return          0 if the operation was started successfully and the SSL
- *                  stack should call the resume callback immediately.
- * \return          #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if the operation
- *                  was started successfully and the SSL stack should return
- *                  immediately without calling the resume callback yet.
- * \return          #MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH if the external
- *                  processor does not support this key. The SSL stack will
- *                  use the private key object instead.
- * \return          Any other error indicates a fatal failure and is
- *                  propagated up the call chain. The callback should
- *                  use \c MBEDTLS_ERR_PK_xxx error codes, and <b>must not</b>
- *                  use \c MBEDTLS_ERR_SSL_xxx error codes except as
- *                  directed in the documentation of this callback.
- */
-typedef int mbedtls_ssl_async_decrypt_t( mbedtls_ssl_context *ssl,
-                                         mbedtls_x509_crt *cert,
-                                         const unsigned char *input,
-                                         size_t input_len );
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-/**
- * \brief           Callback type: resume external operation.
- *
- *                  This callback is called during an SSL handshake to resume
- *                  an external operation started by the
- *                  ::mbedtls_ssl_async_sign_t or
- *                  ::mbedtls_ssl_async_decrypt_t callback.
- *
- *                  This function typically checks the status of a pending
- *                  request or causes the request queue to make progress, and
- *                  does not wait for the operation to complete. This allows
- *                  the handshake step to be non-blocking.
- *
- *                  This function may call mbedtls_ssl_get_async_operation_data()
- *                  to retrieve an operation context set by the start callback.
- *                  It may call mbedtls_ssl_set_async_operation_data() to modify
- *                  this context.
- *
- *                  Note that when this function returns a status other than
- *                  #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, it must free any
- *                  resources associated with the operation.
- *
- * \param ssl             The SSL connection instance. It should not be
- *                        modified other than via
- *                        mbedtls_ssl_set_async_operation_data().
- * \param output          Buffer containing the output (signature or decrypted
- *                        data) on success.
- * \param output_len      On success, number of bytes written to \p output.
- * \param output_size     Size of the \p output buffer in bytes.
- *
- * \return          0 if output of the operation is available in the
- *                  \p output buffer.
- * \return          #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if the operation
- *                  is still in progress. Subsequent requests for progress
- *                  on the SSL connection will call the resume callback
- *                  again.
- * \return          Any other error means that the operation is aborted.
- *                  The SSL handshake is aborted. The callback should
- *                  use \c MBEDTLS_ERR_PK_xxx error codes, and <b>must not</b>
- *                  use \c MBEDTLS_ERR_SSL_xxx error codes except as
- *                  directed in the documentation of this callback.
- */
-typedef int mbedtls_ssl_async_resume_t( mbedtls_ssl_context *ssl,
-                                        unsigned char *output,
-                                        size_t *output_len,
-                                        size_t output_size );
-
-/**
- * \brief           Callback type: cancel external operation.
- *
- *                  This callback is called if an SSL connection is closed
- *                  while an asynchronous operation is in progress. Note that
- *                  this callback is not called if the
- *                  ::mbedtls_ssl_async_resume_t callback has run and has
- *                  returned a value other than
- *                  #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, since in that case
- *                  the asynchronous operation has already completed.
- *
- *                  This function may call mbedtls_ssl_get_async_operation_data()
- *                  to retrieve an operation context set by the start callback.
- *
- * \param ssl             The SSL connection instance. It should not be
- *                        modified.
- */
-typedef void mbedtls_ssl_async_cancel_t( mbedtls_ssl_context *ssl );
-#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */
-
-/*
- * This structure is used for storing current session data.
- */
-struct mbedtls_ssl_session
-{
-#if defined(MBEDTLS_HAVE_TIME)
-    mbedtls_time_t start;       /*!< starting time      */
-#endif
-    int ciphersuite;            /*!< chosen ciphersuite */
-    int compression;            /*!< chosen compression */
-    size_t id_len;              /*!< session id length  */
-    unsigned char id[32];       /*!< session identifier */
-    unsigned char master[48];   /*!< the master secret  */
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-    mbedtls_x509_crt *peer_cert;        /*!< peer X.509 cert chain */
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-    uint32_t verify_result;          /*!<  verification result     */
-
-#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_CLI_C)
-    unsigned char *ticket;      /*!< RFC 5077 session ticket */
-    size_t ticket_len;          /*!< session ticket length   */
-    uint32_t ticket_lifetime;   /*!< ticket lifetime hint    */
-#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_CLI_C */
-
-#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH)
-    unsigned char mfl_code;     /*!< MaxFragmentLength negotiated by peer */
-#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */
-
-#if defined(MBEDTLS_SSL_TRUNCATED_HMAC)
-    int trunc_hmac;             /*!< flag for truncated hmac activation   */
-#endif /* MBEDTLS_SSL_TRUNCATED_HMAC */
-
-#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC)
-    int encrypt_then_mac;       /*!< flag for EtM activation                */
-#endif
-};
-
-/**
- * SSL/TLS configuration to be shared between mbedtls_ssl_context structures.
- */
-struct mbedtls_ssl_config
-{
-    /* Group items by size (largest first) to minimize padding overhead */
-
-    /*
-     * Pointers
-     */
-
-    const int *ciphersuite_list[4]; /*!< allowed ciphersuites per version   */
-
-    /** Callback for printing debug output                                  */
-    void (*f_dbg)(void *, int, const char *, int, const char *);
-    void *p_dbg;                    /*!< context for the debug function     */
-
-    /** Callback for getting (pseudo-)random numbers                        */
-    int  (*f_rng)(void *, unsigned char *, size_t);
-    void *p_rng;                    /*!< context for the RNG function       */
-
-    /** Callback to retrieve a session from the cache                       */
-    int (*f_get_cache)(void *, mbedtls_ssl_session *);
-    /** Callback to store a session into the cache                          */
-    int (*f_set_cache)(void *, const mbedtls_ssl_session *);
-    void *p_cache;                  /*!< context for cache callbacks        */
-
-#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION)
-    /** Callback for setting cert according to SNI extension                */
-    int (*f_sni)(void *, mbedtls_ssl_context *, const unsigned char *, size_t);
-    void *p_sni;                    /*!< context for SNI callback           */
-#endif
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-    /** Callback to customize X.509 certificate chain verification          */
-    int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *);
-    void *p_vrfy;                   /*!< context for X.509 verify calllback */
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
-    /** Callback to retrieve PSK key from identity                          */
-    int (*f_psk)(void *, mbedtls_ssl_context *, const unsigned char *, size_t);
-    void *p_psk;                    /*!< context for PSK callback           */
-#endif
-
-#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C)
-    /** Callback to create & write a cookie for ClientHello veirifcation    */
-    int (*f_cookie_write)( void *, unsigned char **, unsigned char *,
-                           const unsigned char *, size_t );
-    /** Callback to verify validity of a ClientHello cookie                 */
-    int (*f_cookie_check)( void *, const unsigned char *, size_t,
-                           const unsigned char *, size_t );
-    void *p_cookie;                 /*!< context for the cookie callbacks   */
-#endif
-
-#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_SRV_C)
-    /** Callback to create & write a session ticket                         */
-    int (*f_ticket_write)( void *, const mbedtls_ssl_session *,
-            unsigned char *, const unsigned char *, size_t *, uint32_t * );
-    /** Callback to parse a session ticket into a session structure         */
-    int (*f_ticket_parse)( void *, mbedtls_ssl_session *, unsigned char *, size_t);
-    void *p_ticket;                 /*!< context for the ticket callbacks   */
-#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_SRV_C */
-
-#if defined(MBEDTLS_SSL_EXPORT_KEYS)
-    /** Callback to export key block and master secret                      */
-    int (*f_export_keys)( void *, const unsigned char *,
-            const unsigned char *, size_t, size_t, size_t );
-    void *p_export_keys;            /*!< context for key export callback    */
-#endif
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-    const mbedtls_x509_crt_profile *cert_profile; /*!< verification profile */
-    mbedtls_ssl_key_cert *key_cert; /*!< own certificate/key pair(s)        */
-    mbedtls_x509_crt *ca_chain;     /*!< trusted CAs                        */
-    mbedtls_x509_crl *ca_crl;       /*!< trusted CAs CRLs                   */
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-#if defined(MBEDTLS_SSL_ASYNC_PRIVATE)
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-    mbedtls_ssl_async_sign_t *f_async_sign_start; /*!< start asynchronous signature operation */
-    mbedtls_ssl_async_decrypt_t *f_async_decrypt_start; /*!< start asynchronous decryption operation */
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-    mbedtls_ssl_async_resume_t *f_async_resume; /*!< resume asynchronous operation */
-    mbedtls_ssl_async_cancel_t *f_async_cancel; /*!< cancel asynchronous operation */
-    void *p_async_config_data; /*!< Configuration data set by mbedtls_ssl_conf_async_private_cb(). */
-#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */
-
-#if defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED)
-    const int *sig_hashes;          /*!< allowed signature hashes           */
-#endif
-
-#if defined(MBEDTLS_ECP_C)
-    const mbedtls_ecp_group_id *curve_list; /*!< allowed curves             */
-#endif
-
-#if defined(MBEDTLS_DHM_C)
-    mbedtls_mpi dhm_P;              /*!< prime modulus for DHM              */
-    mbedtls_mpi dhm_G;              /*!< generator for DHM                  */
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
-    unsigned char *psk;             /*!< pre-shared key. This field should
-                                         only be set via
-                                         mbedtls_ssl_conf_psk() */
-    size_t         psk_len;         /*!< length of the pre-shared key. This
-                                         field should only be set via
-                                         mbedtls_ssl_conf_psk() */
-    unsigned char *psk_identity;    /*!< identity for PSK negotiation. This
-                                         field should only be set via
-                                         mbedtls_ssl_conf_psk() */
-    size_t         psk_identity_len;/*!< length of identity. This field should
-                                         only be set via
-                                         mbedtls_ssl_conf_psk() */
-#endif
-
-#if defined(MBEDTLS_SSL_ALPN)
-    const char **alpn_list;         /*!< ordered list of protocols          */
-#endif
-
-    /*
-     * Numerical settings (int then char)
-     */
-
-    uint32_t read_timeout;          /*!< timeout for mbedtls_ssl_read (ms)  */
-
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-    uint32_t hs_timeout_min;        /*!< initial value of the handshake
-                                         retransmission timeout (ms)        */
-    uint32_t hs_timeout_max;        /*!< maximum value of the handshake
-                                         retransmission timeout (ms)        */
-#endif
-
-#if defined(MBEDTLS_SSL_RENEGOTIATION)
-    int renego_max_records;         /*!< grace period for renegotiation     */
-    unsigned char renego_period[8]; /*!< value of the record counters
-                                         that triggers renegotiation        */
-#endif
-
-#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT)
-    unsigned int badmac_limit;      /*!< limit of records with a bad MAC    */
-#endif
-
-#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_CLI_C)
-    unsigned int dhm_min_bitlen;    /*!< min. bit length of the DHM prime   */
-#endif
-
-    unsigned char max_major_ver;    /*!< max. major version used            */
-    unsigned char max_minor_ver;    /*!< max. minor version used            */
-    unsigned char min_major_ver;    /*!< min. major version used            */
-    unsigned char min_minor_ver;    /*!< min. minor version used            */
-
-    /*
-     * Flags (bitfields)
-     */
-
-    unsigned int endpoint : 1;      /*!< 0: client, 1: server               */
-    unsigned int transport : 1;     /*!< stream (TLS) or datagram (DTLS)    */
-    unsigned int authmode : 2;      /*!< MBEDTLS_SSL_VERIFY_XXX             */
-    /* needed even with renego disabled for LEGACY_BREAK_HANDSHAKE          */
-    unsigned int allow_legacy_renegotiation : 2 ; /*!< MBEDTLS_LEGACY_XXX   */
-#if defined(MBEDTLS_ARC4_C)
-    unsigned int arc4_disabled : 1; /*!< blacklist RC4 ciphersuites?        */
-#endif
-#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH)
-    unsigned int mfl_code : 3;      /*!< desired fragment length            */
-#endif
-#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC)
-    unsigned int encrypt_then_mac : 1 ; /*!< negotiate encrypt-then-mac?    */
-#endif
-#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET)
-    unsigned int extended_ms : 1;   /*!< negotiate extended master secret?  */
-#endif
-#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY)
-    unsigned int anti_replay : 1;   /*!< detect and prevent replay?         */
-#endif
-#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING)
-    unsigned int cbc_record_splitting : 1;  /*!< do cbc record splitting    */
-#endif
-#if defined(MBEDTLS_SSL_RENEGOTIATION)
-    unsigned int disable_renegotiation : 1; /*!< disable renegotiation?     */
-#endif
-#if defined(MBEDTLS_SSL_TRUNCATED_HMAC)
-    unsigned int trunc_hmac : 1;    /*!< negotiate truncated hmac?          */
-#endif
-#if defined(MBEDTLS_SSL_SESSION_TICKETS)
-    unsigned int session_tickets : 1;   /*!< use session tickets?           */
-#endif
-#if defined(MBEDTLS_SSL_FALLBACK_SCSV) && defined(MBEDTLS_SSL_CLI_C)
-    unsigned int fallback : 1;      /*!< is this a fallback?                */
-#endif
-#if defined(MBEDTLS_SSL_SRV_C)
-    unsigned int cert_req_ca_list : 1;  /*!< enable sending CA list in
-                                          Certificate Request messages?     */
-#endif
-};
-
-
-struct mbedtls_ssl_context
-{
-    const mbedtls_ssl_config *conf; /*!< configuration information          */
-
-    /*
-     * Miscellaneous
-     */
-    int state;                  /*!< SSL handshake: current state     */
-#if defined(MBEDTLS_SSL_RENEGOTIATION)
-    int renego_status;          /*!< Initial, in progress, pending?   */
-    int renego_records_seen;    /*!< Records since renego request, or with DTLS,
-                                  number of retransmissions of request if
-                                  renego_max_records is < 0           */
-#endif /* MBEDTLS_SSL_RENEGOTIATION */
-
-    int major_ver;              /*!< equal to  MBEDTLS_SSL_MAJOR_VERSION_3    */
-    int minor_ver;              /*!< either 0 (SSL3) or 1 (TLS1.0)    */
-
-#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT)
-    unsigned badmac_seen;       /*!< records with a bad MAC received    */
-#endif /* MBEDTLS_SSL_DTLS_BADMAC_LIMIT */
-
-    mbedtls_ssl_send_t *f_send; /*!< Callback for network send */
-    mbedtls_ssl_recv_t *f_recv; /*!< Callback for network receive */
-    mbedtls_ssl_recv_timeout_t *f_recv_timeout;
-                                /*!< Callback for network receive with timeout */
-
-    void *p_bio;                /*!< context for I/O operations   */
-
-    /*
-     * Session layer
-     */
-    mbedtls_ssl_session *session_in;            /*!<  current session data (in)   */
-    mbedtls_ssl_session *session_out;           /*!<  current session data (out)  */
-    mbedtls_ssl_session *session;               /*!<  negotiated session data     */
-    mbedtls_ssl_session *session_negotiate;     /*!<  session data in negotiation */
-
-    mbedtls_ssl_handshake_params *handshake;    /*!<  params required only during
-                                              the handshake process        */
-
-    /*
-     * Record layer transformations
-     */
-    mbedtls_ssl_transform *transform_in;        /*!<  current transform params (in)   */
-    mbedtls_ssl_transform *transform_out;       /*!<  current transform params (in)   */
-    mbedtls_ssl_transform *transform;           /*!<  negotiated transform params     */
-    mbedtls_ssl_transform *transform_negotiate; /*!<  transform params in negotiation */
-
-    /*
-     * Timers
-     */
-    void *p_timer;              /*!< context for the timer callbacks */
-
-    mbedtls_ssl_set_timer_t *f_set_timer;       /*!< set timer callback */
-    mbedtls_ssl_get_timer_t *f_get_timer;       /*!< get timer callback */
-
-    /*
-     * Record layer (incoming data)
-     */
-    unsigned char *in_buf;      /*!< input buffer                     */
-    unsigned char *in_ctr;      /*!< 64-bit incoming message counter
-                                     TLS: maintained by us
-                                     DTLS: read from peer             */
-    unsigned char *in_hdr;      /*!< start of record header           */
-    unsigned char *in_len;      /*!< two-bytes message length field   */
-    unsigned char *in_iv;       /*!< ivlen-byte IV                    */
-    unsigned char *in_msg;      /*!< message contents (in_iv+ivlen)   */
-    unsigned char *in_offt;     /*!< read offset in application data  */
-
-    int in_msgtype;             /*!< record header: message type      */
-    size_t in_msglen;           /*!< record header: message length    */
-    size_t in_left;             /*!< amount of data read so far       */
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-    uint16_t in_epoch;          /*!< DTLS epoch for incoming records  */
-    size_t next_record_offset;  /*!< offset of the next record in datagram
-                                     (equal to in_left if none)       */
-#endif /* MBEDTLS_SSL_PROTO_DTLS */
-#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY)
-    uint64_t in_window_top;     /*!< last validated record seq_num    */
-    uint64_t in_window;         /*!< bitmask for replay detection     */
-#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */
-
-    size_t in_hslen;            /*!< current handshake message length,
-                                     including the handshake header   */
-    int nb_zero;                /*!< # of 0-length encrypted messages */
-
-    int keep_current_message;   /*!< drop or reuse current message
-                                     on next call to record layer? */
-
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-    uint8_t disable_datagram_packing;  /*!< Disable packing multiple records
-                                        *   within a single datagram.  */
-#endif /* MBEDTLS_SSL_PROTO_DTLS */
-
-    /*
-     * Record layer (outgoing data)
-     */
-    unsigned char *out_buf;     /*!< output buffer                    */
-    unsigned char *out_ctr;     /*!< 64-bit outgoing message counter  */
-    unsigned char *out_hdr;     /*!< start of record header           */
-    unsigned char *out_len;     /*!< two-bytes message length field   */
-    unsigned char *out_iv;      /*!< ivlen-byte IV                    */
-    unsigned char *out_msg;     /*!< message contents (out_iv+ivlen)  */
-
-    int out_msgtype;            /*!< record header: message type      */
-    size_t out_msglen;          /*!< record header: message length    */
-    size_t out_left;            /*!< amount of data not yet written   */
-
-    unsigned char cur_out_ctr[8]; /*!<  Outgoing record sequence  number. */
-
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-    uint16_t mtu;               /*!< path mtu, used to fragment outgoing messages */
-#endif /* MBEDTLS_SSL_PROTO_DTLS */
-
-#if defined(MBEDTLS_ZLIB_SUPPORT)
-    unsigned char *compress_buf;        /*!<  zlib data buffer        */
-#endif /* MBEDTLS_ZLIB_SUPPORT */
-#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING)
-    signed char split_done;     /*!< current record already splitted? */
-#endif /* MBEDTLS_SSL_CBC_RECORD_SPLITTING */
-
-    /*
-     * PKI layer
-     */
-    int client_auth;                    /*!<  flag for client auth.   */
-
-    /*
-     * User settings
-     */
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-    char *hostname;             /*!< expected peer CN for verification
-                                     (and SNI if available)                 */
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-#if defined(MBEDTLS_SSL_ALPN)
-    const char *alpn_chosen;    /*!<  negotiated protocol                   */
-#endif /* MBEDTLS_SSL_ALPN */
-
-    /*
-     * Information for DTLS hello verify
-     */
-#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C)
-    unsigned char  *cli_id;         /*!<  transport-level ID of the client  */
-    size_t          cli_id_len;     /*!<  length of cli_id                  */
-#endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY && MBEDTLS_SSL_SRV_C */
-
-    /*
-     * Secure renegotiation
-     */
-    /* needed to know when to send extension on server */
-    int secure_renegotiation;           /*!<  does peer support legacy or
-                                              secure renegotiation           */
-#if defined(MBEDTLS_SSL_RENEGOTIATION)
-    size_t verify_data_len;             /*!<  length of verify data stored   */
-    char own_verify_data[MBEDTLS_SSL_VERIFY_DATA_MAX_LEN]; /*!<  previous handshake verify data */
-    char peer_verify_data[MBEDTLS_SSL_VERIFY_DATA_MAX_LEN]; /*!<  previous handshake verify data */
-#endif /* MBEDTLS_SSL_RENEGOTIATION */
-};
-
-#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL)
-
-#define MBEDTLS_SSL_CHANNEL_OUTBOUND    0
-#define MBEDTLS_SSL_CHANNEL_INBOUND     1
-
-extern int (*mbedtls_ssl_hw_record_init)(mbedtls_ssl_context *ssl,
-                const unsigned char *key_enc, const unsigned char *key_dec,
-                size_t keylen,
-                const unsigned char *iv_enc,  const unsigned char *iv_dec,
-                size_t ivlen,
-                const unsigned char *mac_enc, const unsigned char *mac_dec,
-                size_t maclen);
-extern int (*mbedtls_ssl_hw_record_activate)(mbedtls_ssl_context *ssl, int direction);
-extern int (*mbedtls_ssl_hw_record_reset)(mbedtls_ssl_context *ssl);
-extern int (*mbedtls_ssl_hw_record_write)(mbedtls_ssl_context *ssl);
-extern int (*mbedtls_ssl_hw_record_read)(mbedtls_ssl_context *ssl);
-extern int (*mbedtls_ssl_hw_record_finish)(mbedtls_ssl_context *ssl);
-#endif /* MBEDTLS_SSL_HW_RECORD_ACCEL */
-
-/**
- * \brief               Return the name of the ciphersuite associated with the
- *                      given ID
- *
- * \param ciphersuite_id SSL ciphersuite ID
- *
- * \return              a string containing the ciphersuite name
- */
-const char *mbedtls_ssl_get_ciphersuite_name( const int ciphersuite_id );
-
-/**
- * \brief               Return the ID of the ciphersuite associated with the
- *                      given name
- *
- * \param ciphersuite_name SSL ciphersuite name
- *
- * \return              the ID with the ciphersuite or 0 if not found
- */
-int mbedtls_ssl_get_ciphersuite_id( const char *ciphersuite_name );
-
-/**
- * \brief          Initialize an SSL context
- *                 Just makes the context ready for mbedtls_ssl_setup() or
- *                 mbedtls_ssl_free()
- *
- * \param ssl      SSL context
- */
-void mbedtls_ssl_init( mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Set up an SSL context for use
- *
- * \note           No copy of the configuration context is made, it can be
- *                 shared by many mbedtls_ssl_context structures.
- *
- * \warning        The conf structure will be accessed during the session.
- *                 It must not be modified or freed as long as the session
- *                 is active.
- *
- * \warning        This function must be called exactly once per context.
- *                 Calling mbedtls_ssl_setup again is not supported, even
- *                 if no session is active.
- *
- * \param ssl      SSL context
- * \param conf     SSL configuration to use
- *
- * \return         0 if successful, or MBEDTLS_ERR_SSL_ALLOC_FAILED if
- *                 memory allocation failed
- */
-int mbedtls_ssl_setup( mbedtls_ssl_context *ssl,
-                       const mbedtls_ssl_config *conf );
-
-/**
- * \brief          Reset an already initialized SSL context for re-use
- *                 while retaining application-set variables, function
- *                 pointers and data.
- *
- * \param ssl      SSL context
- * \return         0 if successful, or MBEDTLS_ERR_SSL_ALLOC_FAILED,
-                   MBEDTLS_ERR_SSL_HW_ACCEL_FAILED or
- *                 MBEDTLS_ERR_SSL_COMPRESSION_FAILED
- */
-int mbedtls_ssl_session_reset( mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Set the current endpoint type
- *
- * \param conf     SSL configuration
- * \param endpoint must be MBEDTLS_SSL_IS_CLIENT or MBEDTLS_SSL_IS_SERVER
- */
-void mbedtls_ssl_conf_endpoint( mbedtls_ssl_config *conf, int endpoint );
-
-/**
- * \brief           Set the transport type (TLS or DTLS).
- *                  Default: TLS
- *
- * \note            For DTLS, you must either provide a recv callback that
- *                  doesn't block, or one that handles timeouts, see
- *                  \c mbedtls_ssl_set_bio(). You also need to provide timer
- *                  callbacks with \c mbedtls_ssl_set_timer_cb().
- *
- * \param conf      SSL configuration
- * \param transport transport type:
- *                  MBEDTLS_SSL_TRANSPORT_STREAM for TLS,
- *                  MBEDTLS_SSL_TRANSPORT_DATAGRAM for DTLS.
- */
-void mbedtls_ssl_conf_transport( mbedtls_ssl_config *conf, int transport );
-
-/**
- * \brief          Set the certificate verification mode
- *                 Default: NONE on server, REQUIRED on client
- *
- * \param conf     SSL configuration
- * \param authmode can be:
- *
- *  MBEDTLS_SSL_VERIFY_NONE:      peer certificate is not checked
- *                        (default on server)
- *                        (insecure on client)
- *
- *  MBEDTLS_SSL_VERIFY_OPTIONAL:  peer certificate is checked, however the
- *                        handshake continues even if verification failed;
- *                        mbedtls_ssl_get_verify_result() can be called after the
- *                        handshake is complete.
- *
- *  MBEDTLS_SSL_VERIFY_REQUIRED:  peer *must* present a valid certificate,
- *                        handshake is aborted if verification failed.
- *                        (default on client)
- *
- * \note On client, MBEDTLS_SSL_VERIFY_REQUIRED is the recommended mode.
- * With MBEDTLS_SSL_VERIFY_OPTIONAL, the user needs to call mbedtls_ssl_get_verify_result() at
- * the right time(s), which may not be obvious, while REQUIRED always perform
- * the verification as soon as possible. For example, REQUIRED was protecting
- * against the "triple handshake" attack even before it was found.
- */
-void mbedtls_ssl_conf_authmode( mbedtls_ssl_config *conf, int authmode );
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-/**
- * \brief          Set the verification callback (Optional).
- *
- *                 If set, the verify callback is called for each
- *                 certificate in the chain. For implementation
- *                 information, please see \c mbedtls_x509_crt_verify()
- *
- * \param conf     SSL configuration
- * \param f_vrfy   verification function
- * \param p_vrfy   verification parameter
- */
-void mbedtls_ssl_conf_verify( mbedtls_ssl_config *conf,
-                     int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *),
-                     void *p_vrfy );
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-/**
- * \brief          Set the random number generator callback
- *
- * \param conf     SSL configuration
- * \param f_rng    RNG function
- * \param p_rng    RNG parameter
- */
-void mbedtls_ssl_conf_rng( mbedtls_ssl_config *conf,
-                  int (*f_rng)(void *, unsigned char *, size_t),
-                  void *p_rng );
-
-/**
- * \brief          Set the debug callback
- *
- *                 The callback has the following argument:
- *                 void *           opaque context for the callback
- *                 int              debug level
- *                 const char *     file name
- *                 int              line number
- *                 const char *     message
- *
- * \param conf     SSL configuration
- * \param f_dbg    debug function
- * \param p_dbg    debug parameter
- */
-void mbedtls_ssl_conf_dbg( mbedtls_ssl_config *conf,
-                  void (*f_dbg)(void *, int, const char *, int, const char *),
-                  void  *p_dbg );
-
-/**
- * \brief          Set the underlying BIO callbacks for write, read and
- *                 read-with-timeout.
- *
- * \param ssl      SSL context
- * \param p_bio    parameter (context) shared by BIO callbacks
- * \param f_send   write callback
- * \param f_recv   read callback
- * \param f_recv_timeout blocking read callback with timeout.
- *
- * \note           One of f_recv or f_recv_timeout can be NULL, in which case
- *                 the other is used. If both are non-NULL, f_recv_timeout is
- *                 used and f_recv is ignored (as if it were NULL).
- *
- * \note           The two most common use cases are:
- *                 - non-blocking I/O, f_recv != NULL, f_recv_timeout == NULL
- *                 - blocking I/O, f_recv == NULL, f_recv_timout != NULL
- *
- * \note           For DTLS, you need to provide either a non-NULL
- *                 f_recv_timeout callback, or a f_recv that doesn't block.
- *
- * \note           See the documentations of \c mbedtls_ssl_sent_t,
- *                 \c mbedtls_ssl_recv_t and \c mbedtls_ssl_recv_timeout_t for
- *                 the conventions those callbacks must follow.
- *
- * \note           On some platforms, net_sockets.c provides
- *                 \c mbedtls_net_send(), \c mbedtls_net_recv() and
- *                 \c mbedtls_net_recv_timeout() that are suitable to be used
- *                 here.
- */
-void mbedtls_ssl_set_bio( mbedtls_ssl_context *ssl,
-                          void *p_bio,
-                          mbedtls_ssl_send_t *f_send,
-                          mbedtls_ssl_recv_t *f_recv,
-                          mbedtls_ssl_recv_timeout_t *f_recv_timeout );
-
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-/**
- * \brief          Set the Maximum Tranport Unit (MTU).
- *                 Special value: 0 means unset (no limit).
- *                 This represents the maximum size of a datagram payload
- *                 handled by the transport layer (usually UDP) as determined
- *                 by the network link and stack. In practice, this controls
- *                 the maximum size datagram the DTLS layer will pass to the
- *                 \c f_send() callback set using \c mbedtls_ssl_set_bio().
- *
- * \note           The limit on datagram size is converted to a limit on
- *                 record payload by subtracting the current overhead of
- *                 encapsulation and encryption/authentication if any.
- *
- * \note           This can be called at any point during the connection, for
- *                 example when a Path Maximum Transfer Unit (PMTU)
- *                 estimate becomes available from other sources,
- *                 such as lower (or higher) protocol layers.
- *
- * \note           This setting only controls the size of the packets we send,
- *                 and does not restrict the size of the datagrams we're
- *                 willing to receive. Client-side, you can request the
- *                 server to use smaller records with \c
- *                 mbedtls_ssl_conf_max_frag_len().
- *
- * \note           If both a MTU and a maximum fragment length have been
- *                 configured (or negotiated with the peer), the resulting
- *                 lower limit on record payload (see first note) is used.
- *
- * \note           This can only be used to decrease the maximum size
- *                 of datagrams (hence records, see first note) sent. It
- *                 cannot be used to increase the maximum size of records over
- *                 the limit set by #MBEDTLS_SSL_OUT_CONTENT_LEN.
- *
- * \note           Values lower than the current record layer expansion will
- *                 result in an error when trying to send data.
- *
- * \note           Using record compression together with a non-zero MTU value
- *                 will result in an error when trying to send data.
- *
- * \param ssl      SSL context
- * \param mtu      Value of the path MTU in bytes
- */
-void mbedtls_ssl_set_mtu( mbedtls_ssl_context *ssl, uint16_t mtu );
-#endif /* MBEDTLS_SSL_PROTO_DTLS */
-
-/**
- * \brief          Set the timeout period for mbedtls_ssl_read()
- *                 (Default: no timeout.)
- *
- * \param conf     SSL configuration context
- * \param timeout  Timeout value in milliseconds.
- *                 Use 0 for no timeout (default).
- *
- * \note           With blocking I/O, this will only work if a non-NULL
- *                 \c f_recv_timeout was set with \c mbedtls_ssl_set_bio().
- *                 With non-blocking I/O, this will only work if timer
- *                 callbacks were set with \c mbedtls_ssl_set_timer_cb().
- *
- * \note           With non-blocking I/O, you may also skip this function
- *                 altogether and handle timeouts at the application layer.
- */
-void mbedtls_ssl_conf_read_timeout( mbedtls_ssl_config *conf, uint32_t timeout );
-
-/**
- * \brief          Set the timer callbacks (Mandatory for DTLS.)
- *
- * \param ssl      SSL context
- * \param p_timer  parameter (context) shared by timer callbacks
- * \param f_set_timer   set timer callback
- * \param f_get_timer   get timer callback. Must return:
- *
- * \note           See the documentation of \c mbedtls_ssl_set_timer_t and
- *                 \c mbedtls_ssl_get_timer_t for the conventions this pair of
- *                 callbacks must follow.
- *
- * \note           On some platforms, timing.c provides
- *                 \c mbedtls_timing_set_delay() and
- *                 \c mbedtls_timing_get_delay() that are suitable for using
- *                 here, except if using an event-driven style.
- *
- * \note           See also the "DTLS tutorial" article in our knowledge base.
- *                 https://tls.mbed.org/kb/how-to/dtls-tutorial
- */
-void mbedtls_ssl_set_timer_cb( mbedtls_ssl_context *ssl,
-                               void *p_timer,
-                               mbedtls_ssl_set_timer_t *f_set_timer,
-                               mbedtls_ssl_get_timer_t *f_get_timer );
-
-/**
- * \brief           Callback type: generate and write session ticket
- *
- * \note            This describes what a callback implementation should do.
- *                  This callback should generate an encrypted and
- *                  authenticated ticket for the session and write it to the
- *                  output buffer. Here, ticket means the opaque ticket part
- *                  of the NewSessionTicket structure of RFC 5077.
- *
- * \param p_ticket  Context for the callback
- * \param session   SSL session to be written in the ticket
- * \param start     Start of the output buffer
- * \param end       End of the output buffer
- * \param tlen      On exit, holds the length written
- * \param lifetime  On exit, holds the lifetime of the ticket in seconds
- *
- * \return          0 if successful, or
- *                  a specific MBEDTLS_ERR_XXX code.
- */
-typedef int mbedtls_ssl_ticket_write_t( void *p_ticket,
-                                        const mbedtls_ssl_session *session,
-                                        unsigned char *start,
-                                        const unsigned char *end,
-                                        size_t *tlen,
-                                        uint32_t *lifetime );
-
-#if defined(MBEDTLS_SSL_EXPORT_KEYS)
-/**
- * \brief           Callback type: Export key block and master secret
- *
- * \note            This is required for certain uses of TLS, e.g. EAP-TLS
- *                  (RFC 5216) and Thread. The key pointers are ephemeral and
- *                  therefore must not be stored. The master secret and keys
- *                  should not be used directly except as an input to a key
- *                  derivation function.
- *
- * \param p_expkey  Context for the callback
- * \param ms        Pointer to master secret (fixed length: 48 bytes)
- * \param kb        Pointer to key block, see RFC 5246 section 6.3
- *                  (variable length: 2 * maclen + 2 * keylen + 2 * ivlen).
- * \param maclen    MAC length
- * \param keylen    Key length
- * \param ivlen     IV length
- *
- * \return          0 if successful, or
- *                  a specific MBEDTLS_ERR_XXX code.
- */
-typedef int mbedtls_ssl_export_keys_t( void *p_expkey,
-                                const unsigned char *ms,
-                                const unsigned char *kb,
-                                size_t maclen,
-                                size_t keylen,
-                                size_t ivlen );
-#endif /* MBEDTLS_SSL_EXPORT_KEYS */
-
-/**
- * \brief           Callback type: parse and load session ticket
- *
- * \note            This describes what a callback implementation should do.
- *                  This callback should parse a session ticket as generated
- *                  by the corresponding mbedtls_ssl_ticket_write_t function,
- *                  and, if the ticket is authentic and valid, load the
- *                  session.
- *
- * \note            The implementation is allowed to modify the first len
- *                  bytes of the input buffer, eg to use it as a temporary
- *                  area for the decrypted ticket contents.
- *
- * \param p_ticket  Context for the callback
- * \param session   SSL session to be loaded
- * \param buf       Start of the buffer containing the ticket
- * \param len       Length of the ticket.
- *
- * \return          0 if successful, or
- *                  MBEDTLS_ERR_SSL_INVALID_MAC if not authentic, or
- *                  MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED if expired, or
- *                  any other non-zero code for other failures.
- */
-typedef int mbedtls_ssl_ticket_parse_t( void *p_ticket,
-                                        mbedtls_ssl_session *session,
-                                        unsigned char *buf,
-                                        size_t len );
-
-#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_SRV_C)
-/**
- * \brief           Configure SSL session ticket callbacks (server only).
- *                  (Default: none.)
- *
- * \note            On server, session tickets are enabled by providing
- *                  non-NULL callbacks.
- *
- * \note            On client, use \c mbedtls_ssl_conf_session_tickets().
- *
- * \param conf      SSL configuration context
- * \param f_ticket_write    Callback for writing a ticket
- * \param f_ticket_parse    Callback for parsing a ticket
- * \param p_ticket          Context shared by the two callbacks
- */
-void mbedtls_ssl_conf_session_tickets_cb( mbedtls_ssl_config *conf,
-        mbedtls_ssl_ticket_write_t *f_ticket_write,
-        mbedtls_ssl_ticket_parse_t *f_ticket_parse,
-        void *p_ticket );
-#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_SRV_C */
-
-#if defined(MBEDTLS_SSL_EXPORT_KEYS)
-/**
- * \brief           Configure key export callback.
- *                  (Default: none.)
- *
- * \note            See \c mbedtls_ssl_export_keys_t.
- *
- * \param conf      SSL configuration context
- * \param f_export_keys     Callback for exporting keys
- * \param p_export_keys     Context for the callback
- */
-void mbedtls_ssl_conf_export_keys_cb( mbedtls_ssl_config *conf,
-        mbedtls_ssl_export_keys_t *f_export_keys,
-        void *p_export_keys );
-#endif /* MBEDTLS_SSL_EXPORT_KEYS */
-
-#if defined(MBEDTLS_SSL_ASYNC_PRIVATE)
-/**
- * \brief           Configure asynchronous private key operation callbacks.
- *
- * \param conf              SSL configuration context
- * \param f_async_sign      Callback to start a signature operation. See
- *                          the description of ::mbedtls_ssl_async_sign_t
- *                          for more information. This may be \c NULL if the
- *                          external processor does not support any signature
- *                          operation; in this case the private key object
- *                          associated with the certificate will be used.
- * \param f_async_decrypt   Callback to start a decryption operation. See
- *                          the description of ::mbedtls_ssl_async_decrypt_t
- *                          for more information. This may be \c NULL if the
- *                          external processor does not support any decryption
- *                          operation; in this case the private key object
- *                          associated with the certificate will be used.
- * \param f_async_resume    Callback to resume an asynchronous operation. See
- *                          the description of ::mbedtls_ssl_async_resume_t
- *                          for more information. This may not be \c NULL unless
- *                          \p f_async_sign and \p f_async_decrypt are both
- *                          \c NULL.
- * \param f_async_cancel    Callback to cancel an asynchronous operation. See
- *                          the description of ::mbedtls_ssl_async_cancel_t
- *                          for more information. This may be \c NULL if
- *                          no cleanup is needed.
- * \param config_data       A pointer to configuration data which can be
- *                          retrieved with
- *                          mbedtls_ssl_conf_get_async_config_data(). The
- *                          library stores this value without dereferencing it.
- */
-void mbedtls_ssl_conf_async_private_cb( mbedtls_ssl_config *conf,
-                                        mbedtls_ssl_async_sign_t *f_async_sign,
-                                        mbedtls_ssl_async_decrypt_t *f_async_decrypt,
-                                        mbedtls_ssl_async_resume_t *f_async_resume,
-                                        mbedtls_ssl_async_cancel_t *f_async_cancel,
-                                        void *config_data );
-
-/**
- * \brief           Retrieve the configuration data set by
- *                  mbedtls_ssl_conf_async_private_cb().
- *
- * \param conf      SSL configuration context
- * \return          The configuration data set by
- *                  mbedtls_ssl_conf_async_private_cb().
- */
-void *mbedtls_ssl_conf_get_async_config_data( const mbedtls_ssl_config *conf );
-
-/**
- * \brief           Retrieve the asynchronous operation user context.
- *
- * \note            This function may only be called while a handshake
- *                  is in progress.
- *
- * \param ssl       The SSL context to access.
- *
- * \return          The asynchronous operation user context that was last
- *                  set during the current handshake. If
- *                  mbedtls_ssl_set_async_operation_data() has not yet been
- *                  called during the current handshake, this function returns
- *                  \c NULL.
- */
-void *mbedtls_ssl_get_async_operation_data( const mbedtls_ssl_context *ssl );
-
-/**
- * \brief           Retrieve the asynchronous operation user context.
- *
- * \note            This function may only be called while a handshake
- *                  is in progress.
- *
- * \param ssl       The SSL context to access.
- * \param ctx       The new value of the asynchronous operation user context.
- *                  Call mbedtls_ssl_get_async_operation_data() later during the
- *                  same handshake to retrieve this value.
- */
-void mbedtls_ssl_set_async_operation_data( mbedtls_ssl_context *ssl,
-                                 void *ctx );
-#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */
-
-/**
- * \brief          Callback type: generate a cookie
- *
- * \param ctx      Context for the callback
- * \param p        Buffer to write to,
- *                 must be updated to point right after the cookie
- * \param end      Pointer to one past the end of the output buffer
- * \param info     Client ID info that was passed to
- *                 \c mbedtls_ssl_set_client_transport_id()
- * \param ilen     Length of info in bytes
- *
- * \return         The callback must return 0 on success,
- *                 or a negative error code.
- */
-typedef int mbedtls_ssl_cookie_write_t( void *ctx,
-                                unsigned char **p, unsigned char *end,
-                                const unsigned char *info, size_t ilen );
-
-/**
- * \brief          Callback type: verify a cookie
- *
- * \param ctx      Context for the callback
- * \param cookie   Cookie to verify
- * \param clen     Length of cookie
- * \param info     Client ID info that was passed to
- *                 \c mbedtls_ssl_set_client_transport_id()
- * \param ilen     Length of info in bytes
- *
- * \return         The callback must return 0 if cookie is valid,
- *                 or a negative error code.
- */
-typedef int mbedtls_ssl_cookie_check_t( void *ctx,
-                                const unsigned char *cookie, size_t clen,
-                                const unsigned char *info, size_t ilen );
-
-#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C)
-/**
- * \brief           Register callbacks for DTLS cookies
- *                  (Server only. DTLS only.)
- *
- *                  Default: dummy callbacks that fail, in order to force you to
- *                  register working callbacks (and initialize their context).
- *
- *                  To disable HelloVerifyRequest, register NULL callbacks.
- *
- * \warning         Disabling hello verification allows your server to be used
- *                  for amplification in DoS attacks against other hosts.
- *                  Only disable if you known this can't happen in your
- *                  particular environment.
- *
- * \note            See comments on \c mbedtls_ssl_handshake() about handling
- *                  the MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED that is expected
- *                  on the first handshake attempt when this is enabled.
- *
- * \note            This is also necessary to handle client reconnection from
- *                  the same port as described in RFC 6347 section 4.2.8 (only
- *                  the variant with cookies is supported currently). See
- *                  comments on \c mbedtls_ssl_read() for details.
- *
- * \param conf              SSL configuration
- * \param f_cookie_write    Cookie write callback
- * \param f_cookie_check    Cookie check callback
- * \param p_cookie          Context for both callbacks
- */
-void mbedtls_ssl_conf_dtls_cookies( mbedtls_ssl_config *conf,
-                           mbedtls_ssl_cookie_write_t *f_cookie_write,
-                           mbedtls_ssl_cookie_check_t *f_cookie_check,
-                           void *p_cookie );
-
-/**
- * \brief          Set client's transport-level identification info.
- *                 (Server only. DTLS only.)
- *
- *                 This is usually the IP address (and port), but could be
- *                 anything identify the client depending on the underlying
- *                 network stack. Used for HelloVerifyRequest with DTLS.
- *                 This is *not* used to route the actual packets.
- *
- * \param ssl      SSL context
- * \param info     Transport-level info identifying the client (eg IP + port)
- * \param ilen     Length of info in bytes
- *
- * \note           An internal copy is made, so the info buffer can be reused.
- *
- * \return         0 on success,
- *                 MBEDTLS_ERR_SSL_BAD_INPUT_DATA if used on client,
- *                 MBEDTLS_ERR_SSL_ALLOC_FAILED if out of memory.
- */
-int mbedtls_ssl_set_client_transport_id( mbedtls_ssl_context *ssl,
-                                 const unsigned char *info,
-                                 size_t ilen );
-
-#endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY && MBEDTLS_SSL_SRV_C */
-
-#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY)
-/**
- * \brief          Enable or disable anti-replay protection for DTLS.
- *                 (DTLS only, no effect on TLS.)
- *                 Default: enabled.
- *
- * \param conf     SSL configuration
- * \param mode     MBEDTLS_SSL_ANTI_REPLAY_ENABLED or MBEDTLS_SSL_ANTI_REPLAY_DISABLED.
- *
- * \warning        Disabling this is a security risk unless the application
- *                 protocol handles duplicated packets in a safe way. You
- *                 should not disable this without careful consideration.
- *                 However, if your application already detects duplicated
- *                 packets and needs information about them to adjust its
- *                 transmission strategy, then you'll want to disable this.
- */
-void mbedtls_ssl_conf_dtls_anti_replay( mbedtls_ssl_config *conf, char mode );
-#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */
-
-#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT)
-/**
- * \brief          Set a limit on the number of records with a bad MAC
- *                 before terminating the connection.
- *                 (DTLS only, no effect on TLS.)
- *                 Default: 0 (disabled).
- *
- * \param conf     SSL configuration
- * \param limit    Limit, or 0 to disable.
- *
- * \note           If the limit is N, then the connection is terminated when
- *                 the Nth non-authentic record is seen.
- *
- * \note           Records with an invalid header are not counted, only the
- *                 ones going through the authentication-decryption phase.
- *
- * \note           This is a security trade-off related to the fact that it's
- *                 often relatively easy for an active attacker ot inject UDP
- *                 datagrams. On one hand, setting a low limit here makes it
- *                 easier for such an attacker to forcibly terminated a
- *                 connection. On the other hand, a high limit or no limit
- *                 might make us waste resources checking authentication on
- *                 many bogus packets.
- */
-void mbedtls_ssl_conf_dtls_badmac_limit( mbedtls_ssl_config *conf, unsigned limit );
-#endif /* MBEDTLS_SSL_DTLS_BADMAC_LIMIT */
-
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-
-/**
- * \brief          Allow or disallow packing of multiple handshake records
- *                 within a single datagram.
- *
- * \param ssl           The SSL context to configure.
- * \param allow_packing This determines whether datagram packing may
- *                      be used or not. A value of \c 0 means that every
- *                      record will be sent in a separate datagram; a
- *                      value of \c 1 means that, if space permits,
- *                      multiple handshake messages (including CCS) belonging to
- *                      a single flight may be packed within a single datagram.
- *
- * \note           This is enabled by default and should only be disabled
- *                 for test purposes, or if datagram packing causes
- *                 interoperability issues with peers that don't support it.
- *
- * \note           Allowing datagram packing reduces the network load since
- *                 there's less overhead if multiple messages share the same
- *                 datagram. Also, it increases the handshake efficiency
- *                 since messages belonging to a single datagram will not
- *                 be reordered in transit, and so future message buffering
- *                 or flight retransmission (if no buffering is used) as
- *                 means to deal with reordering are needed less frequently.
- *
- * \note           Application records are not affected by this option and
- *                 are currently always sent in separate datagrams.
- *
- */
-void mbedtls_ssl_set_datagram_packing( mbedtls_ssl_context *ssl,
-                                       unsigned allow_packing );
-
-/**
- * \brief          Set retransmit timeout values for the DTLS handshake.
- *                 (DTLS only, no effect on TLS.)
- *
- * \param conf     SSL configuration
- * \param min      Initial timeout value in milliseconds.
- *                 Default: 1000 (1 second).
- * \param max      Maximum timeout value in milliseconds.
- *                 Default: 60000 (60 seconds).
- *
- * \note           Default values are from RFC 6347 section 4.2.4.1.
- *
- * \note           The 'min' value should typically be slightly above the
- *                 expected round-trip time to your peer, plus whatever time
- *                 it takes for the peer to process the message. For example,
- *                 if your RTT is about 600ms and you peer needs up to 1s to
- *                 do the cryptographic operations in the handshake, then you
- *                 should set 'min' slightly above 1600. Lower values of 'min'
- *                 might cause spurious resends which waste network resources,
- *                 while larger value of 'min' will increase overall latency
- *                 on unreliable network links.
- *
- * \note           The more unreliable your network connection is, the larger
- *                 your max / min ratio needs to be in order to achieve
- *                 reliable handshakes.
- *
- * \note           Messages are retransmitted up to log2(ceil(max/min)) times.
- *                 For example, if min = 1s and max = 5s, the retransmit plan
- *                 goes: send ... 1s -> resend ... 2s -> resend ... 4s ->
- *                 resend ... 5s -> give up and return a timeout error.
- */
-void mbedtls_ssl_conf_handshake_timeout( mbedtls_ssl_config *conf, uint32_t min, uint32_t max );
-#endif /* MBEDTLS_SSL_PROTO_DTLS */
-
-#if defined(MBEDTLS_SSL_SRV_C)
-/**
- * \brief          Set the session cache callbacks (server-side only)
- *                 If not set, no session resuming is done (except if session
- *                 tickets are enabled too).
- *
- *                 The session cache has the responsibility to check for stale
- *                 entries based on timeout. See RFC 5246 for recommendations.
- *
- *                 Warning: session.peer_cert is cleared by the SSL/TLS layer on
- *                 connection shutdown, so do not cache the pointer! Either set
- *                 it to NULL or make a full copy of the certificate.
- *
- *                 The get callback is called once during the initial handshake
- *                 to enable session resuming. The get function has the
- *                 following parameters: (void *parameter, mbedtls_ssl_session *session)
- *                 If a valid entry is found, it should fill the master of
- *                 the session object with the cached values and return 0,
- *                 return 1 otherwise. Optionally peer_cert can be set as well
- *                 if it is properly present in cache entry.
- *
- *                 The set callback is called once during the initial handshake
- *                 to enable session resuming after the entire handshake has
- *                 been finished. The set function has the following parameters:
- *                 (void *parameter, const mbedtls_ssl_session *session). The function
- *                 should create a cache entry for future retrieval based on
- *                 the data in the session structure and should keep in mind
- *                 that the mbedtls_ssl_session object presented (and all its referenced
- *                 data) is cleared by the SSL/TLS layer when the connection is
- *                 terminated. It is recommended to add metadata to determine if
- *                 an entry is still valid in the future. Return 0 if
- *                 successfully cached, return 1 otherwise.
- *
- * \param conf           SSL configuration
- * \param p_cache        parmater (context) for both callbacks
- * \param f_get_cache    session get callback
- * \param f_set_cache    session set callback
- */
-void mbedtls_ssl_conf_session_cache( mbedtls_ssl_config *conf,
-        void *p_cache,
-        int (*f_get_cache)(void *, mbedtls_ssl_session *),
-        int (*f_set_cache)(void *, const mbedtls_ssl_session *) );
-#endif /* MBEDTLS_SSL_SRV_C */
-
-#if defined(MBEDTLS_SSL_CLI_C)
-/**
- * \brief          Request resumption of session (client-side only)
- *                 Session data is copied from presented session structure.
- *
- * \param ssl      SSL context
- * \param session  session context
- *
- * \return         0 if successful,
- *                 MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed,
- *                 MBEDTLS_ERR_SSL_BAD_INPUT_DATA if used server-side or
- *                 arguments are otherwise invalid
- *
- * \sa             mbedtls_ssl_get_session()
- */
-int mbedtls_ssl_set_session( mbedtls_ssl_context *ssl, const mbedtls_ssl_session *session );
-#endif /* MBEDTLS_SSL_CLI_C */
-
-/**
- * \brief               Set the list of allowed ciphersuites and the preference
- *                      order. First in the list has the highest preference.
- *                      (Overrides all version-specific lists)
- *
- *                      The ciphersuites array is not copied, and must remain
- *                      valid for the lifetime of the ssl_config.
- *
- *                      Note: The server uses its own preferences
- *                      over the preference of the client unless
- *                      MBEDTLS_SSL_SRV_RESPECT_CLIENT_PREFERENCE is defined!
- *
- * \param conf          SSL configuration
- * \param ciphersuites  0-terminated list of allowed ciphersuites
- */
-void mbedtls_ssl_conf_ciphersuites( mbedtls_ssl_config *conf,
-                                   const int *ciphersuites );
-
-/**
- * \brief               Set the list of allowed ciphersuites and the
- *                      preference order for a specific version of the protocol.
- *                      (Only useful on the server side)
- *
- *                      The ciphersuites array is not copied, and must remain
- *                      valid for the lifetime of the ssl_config.
- *
- * \param conf          SSL configuration
- * \param ciphersuites  0-terminated list of allowed ciphersuites
- * \param major         Major version number (only MBEDTLS_SSL_MAJOR_VERSION_3
- *                      supported)
- * \param minor         Minor version number (MBEDTLS_SSL_MINOR_VERSION_0,
- *                      MBEDTLS_SSL_MINOR_VERSION_1 and MBEDTLS_SSL_MINOR_VERSION_2,
- *                      MBEDTLS_SSL_MINOR_VERSION_3 supported)
- *
- * \note                With DTLS, use MBEDTLS_SSL_MINOR_VERSION_2 for DTLS 1.0
- *                      and MBEDTLS_SSL_MINOR_VERSION_3 for DTLS 1.2
- */
-void mbedtls_ssl_conf_ciphersuites_for_version( mbedtls_ssl_config *conf,
-                                       const int *ciphersuites,
-                                       int major, int minor );
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-/**
- * \brief          Set the X.509 security profile used for verification
- *
- * \note           The restrictions are enforced for all certificates in the
- *                 chain. However, signatures in the handshake are not covered
- *                 by this setting but by \b mbedtls_ssl_conf_sig_hashes().
- *
- * \param conf     SSL configuration
- * \param profile  Profile to use
- */
-void mbedtls_ssl_conf_cert_profile( mbedtls_ssl_config *conf,
-                                    const mbedtls_x509_crt_profile *profile );
-
-/**
- * \brief          Set the data required to verify peer certificate
- *
- * \note           See \c mbedtls_x509_crt_verify() for notes regarding the
- *                 parameters ca_chain (maps to trust_ca for that function)
- *                 and ca_crl.
- *
- * \param conf     SSL configuration
- * \param ca_chain trusted CA chain (meaning all fully trusted top-level CAs)
- * \param ca_crl   trusted CA CRLs
- */
-void mbedtls_ssl_conf_ca_chain( mbedtls_ssl_config *conf,
-                               mbedtls_x509_crt *ca_chain,
-                               mbedtls_x509_crl *ca_crl );
-
-/**
- * \brief          Set own certificate chain and private key
- *
- * \note           own_cert should contain in order from the bottom up your
- *                 certificate chain. The top certificate (self-signed)
- *                 can be omitted.
- *
- * \note           On server, this function can be called multiple times to
- *                 provision more than one cert/key pair (eg one ECDSA, one
- *                 RSA with SHA-256, one RSA with SHA-1). An adequate
- *                 certificate will be selected according to the client's
- *                 advertised capabilities. In case multiple certificates are
- *                 adequate, preference is given to the one set by the first
- *                 call to this function, then second, etc.
- *
- * \note           On client, only the first call has any effect. That is,
- *                 only one client certificate can be provisioned. The
- *                 server's preferences in its CertficateRequest message will
- *                 be ignored and our only cert will be sent regardless of
- *                 whether it matches those preferences - the server can then
- *                 decide what it wants to do with it.
- *
- * \note           The provided \p pk_key needs to match the public key in the
- *                 first certificate in \p own_cert, or all handshakes using
- *                 that certificate will fail. It is your responsibility
- *                 to ensure that; this function will not perform any check.
- *                 You may use mbedtls_pk_check_pair() in order to perform
- *                 this check yourself, but be aware that this function can
- *                 be computationally expensive on some key types.
- *
- * \param conf     SSL configuration
- * \param own_cert own public certificate chain
- * \param pk_key   own private key
- *
- * \return         0 on success or MBEDTLS_ERR_SSL_ALLOC_FAILED
- */
-int mbedtls_ssl_conf_own_cert( mbedtls_ssl_config *conf,
-                              mbedtls_x509_crt *own_cert,
-                              mbedtls_pk_context *pk_key );
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
-/**
- * \brief          Set the Pre Shared Key (PSK) and the expected identity name
- *
- * \note           This is mainly useful for clients. Servers will usually
- *                 want to use \c mbedtls_ssl_conf_psk_cb() instead.
- *
- * \note           Currently clients can only register one pre-shared key.
- *                 In other words, the servers' identity hint is ignored.
- *                 Support for setting multiple PSKs on clients and selecting
- *                 one based on the identity hint is not a planned feature but
- *                 feedback is welcomed.
- *
- * \param conf     SSL configuration
- * \param psk      pointer to the pre-shared key
- * \param psk_len  pre-shared key length
- * \param psk_identity      pointer to the pre-shared key identity
- * \param psk_identity_len  identity key length
- *
- * \return         0 if successful or MBEDTLS_ERR_SSL_ALLOC_FAILED
- */
-int mbedtls_ssl_conf_psk( mbedtls_ssl_config *conf,
-                const unsigned char *psk, size_t psk_len,
-                const unsigned char *psk_identity, size_t psk_identity_len );
-
-
-/**
- * \brief          Set the Pre Shared Key (PSK) for the current handshake
- *
- * \note           This should only be called inside the PSK callback,
- *                 ie the function passed to \c mbedtls_ssl_conf_psk_cb().
- *
- * \param ssl      SSL context
- * \param psk      pointer to the pre-shared key
- * \param psk_len  pre-shared key length
- *
- * \return         0 if successful or MBEDTLS_ERR_SSL_ALLOC_FAILED
- */
-int mbedtls_ssl_set_hs_psk( mbedtls_ssl_context *ssl,
-                            const unsigned char *psk, size_t psk_len );
-
-/**
- * \brief          Set the PSK callback (server-side only).
- *
- *                 If set, the PSK callback is called for each
- *                 handshake where a PSK ciphersuite was negotiated.
- *                 The caller provides the identity received and wants to
- *                 receive the actual PSK data and length.
- *
- *                 The callback has the following parameters: (void *parameter,
- *                 mbedtls_ssl_context *ssl, const unsigned char *psk_identity,
- *                 size_t identity_len)
- *                 If a valid PSK identity is found, the callback should use
- *                 \c mbedtls_ssl_set_hs_psk() on the ssl context to set the
- *                 correct PSK and return 0.
- *                 Any other return value will result in a denied PSK identity.
- *
- * \note           If you set a PSK callback using this function, then you
- *                 don't need to set a PSK key and identity using
- *                 \c mbedtls_ssl_conf_psk().
- *
- * \param conf     SSL configuration
- * \param f_psk    PSK identity function
- * \param p_psk    PSK identity parameter
- */
-void mbedtls_ssl_conf_psk_cb( mbedtls_ssl_config *conf,
-                     int (*f_psk)(void *, mbedtls_ssl_context *, const unsigned char *,
-                                  size_t),
-                     void *p_psk );
-#endif /* MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED */
-
-#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_SRV_C)
-
-#if !defined(MBEDTLS_DEPRECATED_REMOVED)
-
-#if defined(MBEDTLS_DEPRECATED_WARNING)
-#define MBEDTLS_DEPRECATED    __attribute__((deprecated))
-#else
-#define MBEDTLS_DEPRECATED
-#endif
-
-/**
- * \brief          Set the Diffie-Hellman public P and G values,
- *                 read as hexadecimal strings (server-side only)
- *                 (Default values: MBEDTLS_DHM_RFC3526_MODP_2048_[PG])
- *
- * \param conf     SSL configuration
- * \param dhm_P    Diffie-Hellman-Merkle modulus
- * \param dhm_G    Diffie-Hellman-Merkle generator
- *
- * \deprecated     Superseded by \c mbedtls_ssl_conf_dh_param_bin.
- *
- * \return         0 if successful
- */
-MBEDTLS_DEPRECATED int mbedtls_ssl_conf_dh_param( mbedtls_ssl_config *conf,
-                                                  const char *dhm_P,
-                                                  const char *dhm_G );
-
-#endif /* MBEDTLS_DEPRECATED_REMOVED */
-
-/**
- * \brief          Set the Diffie-Hellman public P and G values
- *                 from big-endian binary presentations.
- *                 (Default values: MBEDTLS_DHM_RFC3526_MODP_2048_[PG]_BIN)
- *
- * \param conf     SSL configuration
- * \param dhm_P    Diffie-Hellman-Merkle modulus in big-endian binary form
- * \param P_len    Length of DHM modulus
- * \param dhm_G    Diffie-Hellman-Merkle generator in big-endian binary form
- * \param G_len    Length of DHM generator
- *
- * \return         0 if successful
- */
-int mbedtls_ssl_conf_dh_param_bin( mbedtls_ssl_config *conf,
-                                   const unsigned char *dhm_P, size_t P_len,
-                                   const unsigned char *dhm_G,  size_t G_len );
-
-/**
- * \brief          Set the Diffie-Hellman public P and G values,
- *                 read from existing context (server-side only)
- *
- * \param conf     SSL configuration
- * \param dhm_ctx  Diffie-Hellman-Merkle context
- *
- * \return         0 if successful
- */
-int mbedtls_ssl_conf_dh_param_ctx( mbedtls_ssl_config *conf, mbedtls_dhm_context *dhm_ctx );
-#endif /* MBEDTLS_DHM_C && defined(MBEDTLS_SSL_SRV_C) */
-
-#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_CLI_C)
-/**
- * \brief          Set the minimum length for Diffie-Hellman parameters.
- *                 (Client-side only.)
- *                 (Default: 1024 bits.)
- *
- * \param conf     SSL configuration
- * \param bitlen   Minimum bit length of the DHM prime
- */
-void mbedtls_ssl_conf_dhm_min_bitlen( mbedtls_ssl_config *conf,
-                                      unsigned int bitlen );
-#endif /* MBEDTLS_DHM_C && MBEDTLS_SSL_CLI_C */
-
-#if defined(MBEDTLS_ECP_C)
-/**
- * \brief          Set the allowed curves in order of preference.
- *                 (Default: all defined curves.)
- *
- *                 On server: this only affects selection of the ECDHE curve;
- *                 the curves used for ECDH and ECDSA are determined by the
- *                 list of available certificates instead.
- *
- *                 On client: this affects the list of curves offered for any
- *                 use. The server can override our preference order.
- *
- *                 Both sides: limits the set of curves accepted for use in
- *                 ECDHE and in the peer's end-entity certificate.
- *
- * \note           This has no influence on which curves are allowed inside the
- *                 certificate chains, see \c mbedtls_ssl_conf_cert_profile()
- *                 for that. For the end-entity certificate however, the key
- *                 will be accepted only if it is allowed both by this list
- *                 and by the cert profile.
- *
- * \note           This list should be ordered by decreasing preference
- *                 (preferred curve first).
- *
- * \param conf     SSL configuration
- * \param curves   Ordered list of allowed curves,
- *                 terminated by MBEDTLS_ECP_DP_NONE.
- */
-void mbedtls_ssl_conf_curves( mbedtls_ssl_config *conf,
-                              const mbedtls_ecp_group_id *curves );
-#endif /* MBEDTLS_ECP_C */
-
-#if defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED)
-/**
- * \brief          Set the allowed hashes for signatures during the handshake.
- *                 (Default: all available hashes except MD5.)
- *
- * \note           This only affects which hashes are offered and can be used
- *                 for signatures during the handshake. Hashes for message
- *                 authentication and the TLS PRF are controlled by the
- *                 ciphersuite, see \c mbedtls_ssl_conf_ciphersuites(). Hashes
- *                 used for certificate signature are controlled by the
- *                 verification profile, see \c mbedtls_ssl_conf_cert_profile().
- *
- * \note           This list should be ordered by decreasing preference
- *                 (preferred hash first).
- *
- * \param conf     SSL configuration
- * \param hashes   Ordered list of allowed signature hashes,
- *                 terminated by \c MBEDTLS_MD_NONE.
- */
-void mbedtls_ssl_conf_sig_hashes( mbedtls_ssl_config *conf,
-                                  const int *hashes );
-#endif /* MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED */
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-/**
- * \brief          Set or reset the hostname to check against the received
- *                 server certificate. It sets the ServerName TLS extension,
- *                 too, if that extension is enabled. (client-side only)
- *
- * \param ssl      SSL context
- * \param hostname the server hostname, may be NULL to clear hostname
-
- * \note           Maximum hostname length MBEDTLS_SSL_MAX_HOST_NAME_LEN.
- *
- * \return         0 if successful, MBEDTLS_ERR_SSL_ALLOC_FAILED on
- *                 allocation failure, MBEDTLS_ERR_SSL_BAD_INPUT_DATA on
- *                 too long input hostname.
- *
- *                 Hostname set to the one provided on success (cleared
- *                 when NULL). On allocation failure hostname is cleared.
- *                 On too long input failure, old hostname is unchanged.
- */
-int mbedtls_ssl_set_hostname( mbedtls_ssl_context *ssl, const char *hostname );
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION)
-/**
- * \brief          Set own certificate and key for the current handshake
- *
- * \note           Same as \c mbedtls_ssl_conf_own_cert() but for use within
- *                 the SNI callback.
- *
- * \param ssl      SSL context
- * \param own_cert own public certificate chain
- * \param pk_key   own private key
- *
- * \return         0 on success or MBEDTLS_ERR_SSL_ALLOC_FAILED
- */
-int mbedtls_ssl_set_hs_own_cert( mbedtls_ssl_context *ssl,
-                                 mbedtls_x509_crt *own_cert,
-                                 mbedtls_pk_context *pk_key );
-
-/**
- * \brief          Set the data required to verify peer certificate for the
- *                 current handshake
- *
- * \note           Same as \c mbedtls_ssl_conf_ca_chain() but for use within
- *                 the SNI callback.
- *
- * \param ssl      SSL context
- * \param ca_chain trusted CA chain (meaning all fully trusted top-level CAs)
- * \param ca_crl   trusted CA CRLs
- */
-void mbedtls_ssl_set_hs_ca_chain( mbedtls_ssl_context *ssl,
-                                  mbedtls_x509_crt *ca_chain,
-                                  mbedtls_x509_crl *ca_crl );
-
-/**
- * \brief          Set authmode for the current handshake.
- *
- * \note           Same as \c mbedtls_ssl_conf_authmode() but for use within
- *                 the SNI callback.
- *
- * \param ssl      SSL context
- * \param authmode MBEDTLS_SSL_VERIFY_NONE, MBEDTLS_SSL_VERIFY_OPTIONAL or
- *                 MBEDTLS_SSL_VERIFY_REQUIRED
- */
-void mbedtls_ssl_set_hs_authmode( mbedtls_ssl_context *ssl,
-                                  int authmode );
-
-/**
- * \brief          Set server side ServerName TLS extension callback
- *                 (optional, server-side only).
- *
- *                 If set, the ServerName callback is called whenever the
- *                 server receives a ServerName TLS extension from the client
- *                 during a handshake. The ServerName callback has the
- *                 following parameters: (void *parameter, mbedtls_ssl_context *ssl,
- *                 const unsigned char *hostname, size_t len). If a suitable
- *                 certificate is found, the callback must set the
- *                 certificate(s) and key(s) to use with \c
- *                 mbedtls_ssl_set_hs_own_cert() (can be called repeatedly),
- *                 and may optionally adjust the CA and associated CRL with \c
- *                 mbedtls_ssl_set_hs_ca_chain() as well as the client
- *                 authentication mode with \c mbedtls_ssl_set_hs_authmode(),
- *                 then must return 0. If no matching name is found, the
- *                 callback must either set a default cert, or
- *                 return non-zero to abort the handshake at this point.
- *
- * \param conf     SSL configuration
- * \param f_sni    verification function
- * \param p_sni    verification parameter
- */
-void mbedtls_ssl_conf_sni( mbedtls_ssl_config *conf,
-                  int (*f_sni)(void *, mbedtls_ssl_context *, const unsigned char *,
-                               size_t),
-                  void *p_sni );
-#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */
-
-#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
-/**
- * \brief          Set the EC J-PAKE password for current handshake.
- *
- * \note           An internal copy is made, and destroyed as soon as the
- *                 handshake is completed, or when the SSL context is reset or
- *                 freed.
- *
- * \note           The SSL context needs to be already set up. The right place
- *                 to call this function is between \c mbedtls_ssl_setup() or
- *                 \c mbedtls_ssl_reset() and \c mbedtls_ssl_handshake().
- *
- * \param ssl      SSL context
- * \param pw       EC J-PAKE password (pre-shared secret)
- * \param pw_len   length of pw in bytes
- *
- * \return         0 on success, or a negative error code.
- */
-int mbedtls_ssl_set_hs_ecjpake_password( mbedtls_ssl_context *ssl,
-                                         const unsigned char *pw,
-                                         size_t pw_len );
-#endif /*MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */
-
-#if defined(MBEDTLS_SSL_ALPN)
-/**
- * \brief          Set the supported Application Layer Protocols.
- *
- * \param conf     SSL configuration
- * \param protos   Pointer to a NULL-terminated list of supported protocols,
- *                 in decreasing preference order. The pointer to the list is
- *                 recorded by the library for later reference as required, so
- *                 the lifetime of the table must be atleast as long as the
- *                 lifetime of the SSL configuration structure.
- *
- * \return         0 on success, or MBEDTLS_ERR_SSL_BAD_INPUT_DATA.
- */
-int mbedtls_ssl_conf_alpn_protocols( mbedtls_ssl_config *conf, const char **protos );
-
-/**
- * \brief          Get the name of the negotiated Application Layer Protocol.
- *                 This function should be called after the handshake is
- *                 completed.
- *
- * \param ssl      SSL context
- *
- * \return         Protcol name, or NULL if no protocol was negotiated.
- */
-const char *mbedtls_ssl_get_alpn_protocol( const mbedtls_ssl_context *ssl );
-#endif /* MBEDTLS_SSL_ALPN */
-
-/**
- * \brief          Set the maximum supported version sent from the client side
- *                 and/or accepted at the server side
- *                 (Default: MBEDTLS_SSL_MAX_MAJOR_VERSION, MBEDTLS_SSL_MAX_MINOR_VERSION)
- *
- * \note           This ignores ciphersuites from higher versions.
- *
- * \note           With DTLS, use MBEDTLS_SSL_MINOR_VERSION_2 for DTLS 1.0 and
- *                 MBEDTLS_SSL_MINOR_VERSION_3 for DTLS 1.2
- *
- * \param conf     SSL configuration
- * \param major    Major version number (only MBEDTLS_SSL_MAJOR_VERSION_3 supported)
- * \param minor    Minor version number (MBEDTLS_SSL_MINOR_VERSION_0,
- *                 MBEDTLS_SSL_MINOR_VERSION_1 and MBEDTLS_SSL_MINOR_VERSION_2,
- *                 MBEDTLS_SSL_MINOR_VERSION_3 supported)
- */
-void mbedtls_ssl_conf_max_version( mbedtls_ssl_config *conf, int major, int minor );
-
-/**
- * \brief          Set the minimum accepted SSL/TLS protocol version
- *                 (Default: TLS 1.0)
- *
- * \note           Input outside of the SSL_MAX_XXXXX_VERSION and
- *                 SSL_MIN_XXXXX_VERSION range is ignored.
- *
- * \note           MBEDTLS_SSL_MINOR_VERSION_0 (SSL v3) should be avoided.
- *
- * \note           With DTLS, use MBEDTLS_SSL_MINOR_VERSION_2 for DTLS 1.0 and
- *                 MBEDTLS_SSL_MINOR_VERSION_3 for DTLS 1.2
- *
- * \param conf     SSL configuration
- * \param major    Major version number (only MBEDTLS_SSL_MAJOR_VERSION_3 supported)
- * \param minor    Minor version number (MBEDTLS_SSL_MINOR_VERSION_0,
- *                 MBEDTLS_SSL_MINOR_VERSION_1 and MBEDTLS_SSL_MINOR_VERSION_2,
- *                 MBEDTLS_SSL_MINOR_VERSION_3 supported)
- */
-void mbedtls_ssl_conf_min_version( mbedtls_ssl_config *conf, int major, int minor );
-
-#if defined(MBEDTLS_SSL_FALLBACK_SCSV) && defined(MBEDTLS_SSL_CLI_C)
-/**
- * \brief          Set the fallback flag (client-side only).
- *                 (Default: MBEDTLS_SSL_IS_NOT_FALLBACK).
- *
- * \note           Set to MBEDTLS_SSL_IS_FALLBACK when preparing a fallback
- *                 connection, that is a connection with max_version set to a
- *                 lower value than the value you're willing to use. Such
- *                 fallback connections are not recommended but are sometimes
- *                 necessary to interoperate with buggy (version-intolerant)
- *                 servers.
- *
- * \warning        You should NOT set this to MBEDTLS_SSL_IS_FALLBACK for
- *                 non-fallback connections! This would appear to work for a
- *                 while, then cause failures when the server is upgraded to
- *                 support a newer TLS version.
- *
- * \param conf     SSL configuration
- * \param fallback MBEDTLS_SSL_IS_NOT_FALLBACK or MBEDTLS_SSL_IS_FALLBACK
- */
-void mbedtls_ssl_conf_fallback( mbedtls_ssl_config *conf, char fallback );
-#endif /* MBEDTLS_SSL_FALLBACK_SCSV && MBEDTLS_SSL_CLI_C */
-
-#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC)
-/**
- * \brief           Enable or disable Encrypt-then-MAC
- *                  (Default: MBEDTLS_SSL_ETM_ENABLED)
- *
- * \note            This should always be enabled, it is a security
- *                  improvement, and should not cause any interoperability
- *                  issue (used only if the peer supports it too).
- *
- * \param conf      SSL configuration
- * \param etm       MBEDTLS_SSL_ETM_ENABLED or MBEDTLS_SSL_ETM_DISABLED
- */
-void mbedtls_ssl_conf_encrypt_then_mac( mbedtls_ssl_config *conf, char etm );
-#endif /* MBEDTLS_SSL_ENCRYPT_THEN_MAC */
-
-#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET)
-/**
- * \brief           Enable or disable Extended Master Secret negotiation.
- *                  (Default: MBEDTLS_SSL_EXTENDED_MS_ENABLED)
- *
- * \note            This should always be enabled, it is a security fix to the
- *                  protocol, and should not cause any interoperability issue
- *                  (used only if the peer supports it too).
- *
- * \param conf      SSL configuration
- * \param ems       MBEDTLS_SSL_EXTENDED_MS_ENABLED or MBEDTLS_SSL_EXTENDED_MS_DISABLED
- */
-void mbedtls_ssl_conf_extended_master_secret( mbedtls_ssl_config *conf, char ems );
-#endif /* MBEDTLS_SSL_EXTENDED_MASTER_SECRET */
-
-#if defined(MBEDTLS_ARC4_C)
-/**
- * \brief          Disable or enable support for RC4
- *                 (Default: MBEDTLS_SSL_ARC4_DISABLED)
- *
- * \warning        Use of RC4 in DTLS/TLS has been prohibited by RFC 7465
- *                 for security reasons. Use at your own risk.
- *
- * \note           This function is deprecated and will likely be removed in
- *                 a future version of the library.
- *                 RC4 is disabled by default at compile time and needs to be
- *                 actively enabled for use with legacy systems.
- *
- * \param conf     SSL configuration
- * \param arc4     MBEDTLS_SSL_ARC4_ENABLED or MBEDTLS_SSL_ARC4_DISABLED
- */
-void mbedtls_ssl_conf_arc4_support( mbedtls_ssl_config *conf, char arc4 );
-#endif /* MBEDTLS_ARC4_C */
-
-#if defined(MBEDTLS_SSL_SRV_C)
-/**
- * \brief          Whether to send a list of acceptable CAs in
- *                 CertificateRequest messages.
- *                 (Default: do send)
- *
- * \param conf     SSL configuration
- * \param cert_req_ca_list   MBEDTLS_SSL_CERT_REQ_CA_LIST_ENABLED or
- *                          MBEDTLS_SSL_CERT_REQ_CA_LIST_DISABLED
- */
-void mbedtls_ssl_conf_cert_req_ca_list( mbedtls_ssl_config *conf,
-                                          char cert_req_ca_list );
-#endif /* MBEDTLS_SSL_SRV_C */
-
-#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH)
-/**
- * \brief          Set the maximum fragment length to emit and/or negotiate.
- *                 (Typical: the smaller of #MBEDTLS_SSL_IN_CONTENT_LEN and
- *                 #MBEDTLS_SSL_OUT_CONTENT_LEN, usually `2^14` bytes)
- *                 (Server: set maximum fragment length to emit,
- *                 usually negotiated by the client during handshake)
- *                 (Client: set maximum fragment length to emit *and*
- *                 negotiate with the server during handshake)
- *                 (Default: #MBEDTLS_SSL_MAX_FRAG_LEN_NONE)
- *
- * \note           On the client side, the maximum fragment length extension
- *                 *will not* be used, unless the maximum fragment length has
- *                 been set via this function to a value different than
- *                 #MBEDTLS_SSL_MAX_FRAG_LEN_NONE.
- *
- * \note           This sets the maximum length for a record's payload,
- *                 excluding record overhead that will be added to it, see
- *                 \c mbedtls_ssl_get_record_expansion().
- *
- * \note           With TLS, this currently only affects ApplicationData (sent
- *                 with \c mbedtls_ssl_read()), not handshake messages.
- *                 With DTLS, this affects both ApplicationData and handshake.
- *
- * \note           For DTLS, it is also possible to set a limit for the total
- *                 size of daragrams passed to the transport layer, including
- *                 record overhead, see \c mbedtls_ssl_set_mtu().
- *
- * \param conf     SSL configuration
- * \param mfl_code Code for maximum fragment length (allowed values:
- *                 MBEDTLS_SSL_MAX_FRAG_LEN_512,  MBEDTLS_SSL_MAX_FRAG_LEN_1024,
- *                 MBEDTLS_SSL_MAX_FRAG_LEN_2048, MBEDTLS_SSL_MAX_FRAG_LEN_4096)
- *
- * \return         0 if successful or MBEDTLS_ERR_SSL_BAD_INPUT_DATA
- */
-int mbedtls_ssl_conf_max_frag_len( mbedtls_ssl_config *conf, unsigned char mfl_code );
-#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */
-
-#if defined(MBEDTLS_SSL_TRUNCATED_HMAC)
-/**
- * \brief          Activate negotiation of truncated HMAC
- *                 (Default: MBEDTLS_SSL_TRUNC_HMAC_DISABLED)
- *
- * \param conf     SSL configuration
- * \param truncate Enable or disable (MBEDTLS_SSL_TRUNC_HMAC_ENABLED or
- *                                    MBEDTLS_SSL_TRUNC_HMAC_DISABLED)
- */
-void mbedtls_ssl_conf_truncated_hmac( mbedtls_ssl_config *conf, int truncate );
-#endif /* MBEDTLS_SSL_TRUNCATED_HMAC */
-
-#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING)
-/**
- * \brief          Enable / Disable 1/n-1 record splitting
- *                 (Default: MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED)
- *
- * \note           Only affects SSLv3 and TLS 1.0, not higher versions.
- *                 Does not affect non-CBC ciphersuites in any version.
- *
- * \param conf     SSL configuration
- * \param split    MBEDTLS_SSL_CBC_RECORD_SPLITTING_ENABLED or
- *                 MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED
- */
-void mbedtls_ssl_conf_cbc_record_splitting( mbedtls_ssl_config *conf, char split );
-#endif /* MBEDTLS_SSL_CBC_RECORD_SPLITTING */
-
-#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_CLI_C)
-/**
- * \brief          Enable / Disable session tickets (client only).
- *                 (Default: MBEDTLS_SSL_SESSION_TICKETS_ENABLED.)
- *
- * \note           On server, use \c mbedtls_ssl_conf_session_tickets_cb().
- *
- * \param conf     SSL configuration
- * \param use_tickets   Enable or disable (MBEDTLS_SSL_SESSION_TICKETS_ENABLED or
- *                                         MBEDTLS_SSL_SESSION_TICKETS_DISABLED)
- */
-void mbedtls_ssl_conf_session_tickets( mbedtls_ssl_config *conf, int use_tickets );
-#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_CLI_C */
-
-#if defined(MBEDTLS_SSL_RENEGOTIATION)
-/**
- * \brief          Enable / Disable renegotiation support for connection when
- *                 initiated by peer
- *                 (Default: MBEDTLS_SSL_RENEGOTIATION_DISABLED)
- *
- * \warning        It is recommended to always disable renegotation unless you
- *                 know you need it and you know what you're doing. In the
- *                 past, there have been several issues associated with
- *                 renegotiation or a poor understanding of its properties.
- *
- * \note           Server-side, enabling renegotiation also makes the server
- *                 susceptible to a resource DoS by a malicious client.
- *
- * \param conf    SSL configuration
- * \param renegotiation     Enable or disable (MBEDTLS_SSL_RENEGOTIATION_ENABLED or
- *                                             MBEDTLS_SSL_RENEGOTIATION_DISABLED)
- */
-void mbedtls_ssl_conf_renegotiation( mbedtls_ssl_config *conf, int renegotiation );
-#endif /* MBEDTLS_SSL_RENEGOTIATION */
-
-/**
- * \brief          Prevent or allow legacy renegotiation.
- *                 (Default: MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION)
- *
- *                 MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION allows connections to
- *                 be established even if the peer does not support
- *                 secure renegotiation, but does not allow renegotiation
- *                 to take place if not secure.
- *                 (Interoperable and secure option)
- *
- *                 MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION allows renegotiations
- *                 with non-upgraded peers. Allowing legacy renegotiation
- *                 makes the connection vulnerable to specific man in the
- *                 middle attacks. (See RFC 5746)
- *                 (Most interoperable and least secure option)
- *
- *                 MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE breaks off connections
- *                 if peer does not support secure renegotiation. Results
- *                 in interoperability issues with non-upgraded peers
- *                 that do not support renegotiation altogether.
- *                 (Most secure option, interoperability issues)
- *
- * \param conf     SSL configuration
- * \param allow_legacy  Prevent or allow (SSL_NO_LEGACY_RENEGOTIATION,
- *                                        SSL_ALLOW_LEGACY_RENEGOTIATION or
- *                                        MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE)
- */
-void mbedtls_ssl_conf_legacy_renegotiation( mbedtls_ssl_config *conf, int allow_legacy );
-
-#if defined(MBEDTLS_SSL_RENEGOTIATION)
-/**
- * \brief          Enforce renegotiation requests.
- *                 (Default: enforced, max_records = 16)
- *
- *                 When we request a renegotiation, the peer can comply or
- *                 ignore the request. This function allows us to decide
- *                 whether to enforce our renegotiation requests by closing
- *                 the connection if the peer doesn't comply.
- *
- *                 However, records could already be in transit from the peer
- *                 when the request is emitted. In order to increase
- *                 reliability, we can accept a number of records before the
- *                 expected handshake records.
- *
- *                 The optimal value is highly dependent on the specific usage
- *                 scenario.
- *
- * \note           With DTLS and server-initiated renegotiation, the
- *                 HelloRequest is retransmited every time mbedtls_ssl_read() times
- *                 out or receives Application Data, until:
- *                 - max_records records have beens seen, if it is >= 0, or
- *                 - the number of retransmits that would happen during an
- *                 actual handshake has been reached.
- *                 Please remember the request might be lost a few times
- *                 if you consider setting max_records to a really low value.
- *
- * \warning        On client, the grace period can only happen during
- *                 mbedtls_ssl_read(), as opposed to mbedtls_ssl_write() and mbedtls_ssl_renegotiate()
- *                 which always behave as if max_record was 0. The reason is,
- *                 if we receive application data from the server, we need a
- *                 place to write it, which only happens during mbedtls_ssl_read().
- *
- * \param conf     SSL configuration
- * \param max_records Use MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED if you don't want to
- *                 enforce renegotiation, or a non-negative value to enforce
- *                 it but allow for a grace period of max_records records.
- */
-void mbedtls_ssl_conf_renegotiation_enforced( mbedtls_ssl_config *conf, int max_records );
-
-/**
- * \brief          Set record counter threshold for periodic renegotiation.
- *                 (Default: 2^48 - 1)
- *
- *                 Renegotiation is automatically triggered when a record
- *                 counter (outgoing or ingoing) crosses the defined
- *                 threshold. The default value is meant to prevent the
- *                 connection from being closed when the counter is about to
- *                 reached its maximal value (it is not allowed to wrap).
- *
- *                 Lower values can be used to enforce policies such as "keys
- *                 must be refreshed every N packets with cipher X".
- *
- *                 The renegotiation period can be disabled by setting
- *                 conf->disable_renegotiation to
- *                 MBEDTLS_SSL_RENEGOTIATION_DISABLED.
- *
- * \note           When the configured transport is
- *                 MBEDTLS_SSL_TRANSPORT_DATAGRAM the maximum renegotiation
- *                 period is 2^48 - 1, and for MBEDTLS_SSL_TRANSPORT_STREAM,
- *                 the maximum renegotiation period is 2^64 - 1.
- *
- * \param conf     SSL configuration
- * \param period   The threshold value: a big-endian 64-bit number.
- */
-void mbedtls_ssl_conf_renegotiation_period( mbedtls_ssl_config *conf,
-                                   const unsigned char period[8] );
-#endif /* MBEDTLS_SSL_RENEGOTIATION */
-
-/**
- * \brief          Check if there is data already read from the
- *                 underlying transport but not yet processed.
- *
- * \param ssl      SSL context
- *
- * \return         0 if nothing's pending, 1 otherwise.
- *
- * \note           This is different in purpose and behaviour from
- *                 \c mbedtls_ssl_get_bytes_avail in that it considers
- *                 any kind of unprocessed data, not only unread
- *                 application data. If \c mbedtls_ssl_get_bytes
- *                 returns a non-zero value, this function will
- *                 also signal pending data, but the converse does
- *                 not hold. For example, in DTLS there might be
- *                 further records waiting to be processed from
- *                 the current underlying transport's datagram.
- *
- * \note           If this function returns 1 (data pending), this
- *                 does not imply that a subsequent call to
- *                 \c mbedtls_ssl_read will provide any data;
- *                 e.g., the unprocessed data might turn out
- *                 to be an alert or a handshake message.
- *
- * \note           This function is useful in the following situation:
- *                 If the SSL/TLS module successfully returns from an
- *                 operation - e.g. a handshake or an application record
- *                 read - and you're awaiting incoming data next, you
- *                 must not immediately idle on the underlying transport
- *                 to have data ready, but you need to check the value
- *                 of this function first. The reason is that the desired
- *                 data might already be read but not yet processed.
- *                 If, in contrast, a previous call to the SSL/TLS module
- *                 returned MBEDTLS_ERR_SSL_WANT_READ, it is not necessary
- *                 to call this function, as the latter error code entails
- *                 that all internal data has been processed.
- *
- */
-int mbedtls_ssl_check_pending( const mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Return the number of application data bytes
- *                 remaining to be read from the current record.
- *
- * \param ssl      SSL context
- *
- * \return         How many bytes are available in the application
- *                 data record read buffer.
- *
- * \note           When working over a datagram transport, this is
- *                 useful to detect the current datagram's boundary
- *                 in case \c mbedtls_ssl_read has written the maximal
- *                 amount of data fitting into the input buffer.
- *
- */
-size_t mbedtls_ssl_get_bytes_avail( const mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Return the result of the certificate verification
- *
- * \param ssl      The SSL context to use.
- *
- * \return         \c 0 if the certificate verification was successful.
- * \return         \c -1u if the result is not available. This may happen
- *                 e.g. if the handshake aborts early, or a verification
- *                 callback returned a fatal error.
- * \return         A bitwise combination of \c MBEDTLS_X509_BADCERT_XXX
- *                 and \c MBEDTLS_X509_BADCRL_XXX failure flags; see x509.h.
- */
-uint32_t mbedtls_ssl_get_verify_result( const mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Return the name of the current ciphersuite
- *
- * \param ssl      SSL context
- *
- * \return         a string containing the ciphersuite name
- */
-const char *mbedtls_ssl_get_ciphersuite( const mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Return the current SSL version (SSLv3/TLSv1/etc)
- *
- * \param ssl      SSL context
- *
- * \return         a string containing the SSL version
- */
-const char *mbedtls_ssl_get_version( const mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Return the (maximum) number of bytes added by the record
- *                 layer: header + encryption/MAC overhead (inc. padding)
- *
- * \note           This function is not available (always returns an error)
- *                 when record compression is enabled.
- *
- * \param ssl      SSL context
- *
- * \return         Current maximum record expansion in bytes, or
- *                 MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if compression is
- *                 enabled, which makes expansion much less predictable
- */
-int mbedtls_ssl_get_record_expansion( const mbedtls_ssl_context *ssl );
-
-#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH)
-/**
- * \brief          Return the maximum fragment length (payload, in bytes).
- *                 This is the value negotiated with peer if any,
- *                 or the locally configured value.
- *
- * \sa             mbedtls_ssl_conf_max_frag_len()
- * \sa             mbedtls_ssl_get_max_record_payload()
- *
- * \param ssl      SSL context
- *
- * \return         Current maximum fragment length.
- */
-size_t mbedtls_ssl_get_max_frag_len( const mbedtls_ssl_context *ssl );
-#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */
-
-/**
- * \brief          Return the current maximum outgoing record payload in bytes.
- *                 This takes into account the config.h setting \c
- *                 MBEDTLS_SSL_OUT_CONTENT_LEN, the configured and negotiated
- *                 max fragment length extension if used, and for DTLS the
- *                 path MTU as configured and current record expansion.
- *
- * \note           With DTLS, \c mbedtls_ssl_write() will return an error if
- *                 called with a larger length value.
- *                 With TLS, \c mbedtls_ssl_write() will fragment the input if
- *                 necessary and return the number of bytes written; it is up
- *                 to the caller to call \c mbedtls_ssl_write() again in
- *                 order to send the remaining bytes if any.
- *
- * \note           This function is not available (always returns an error)
- *                 when record compression is enabled.
- *
- * \sa             mbedtls_ssl_set_mtu()
- * \sa             mbedtls_ssl_get_max_frag_len()
- * \sa             mbedtls_ssl_get_record_expansion()
- *
- * \param ssl      SSL context
- *
- * \return         Current maximum payload for an outgoing record,
- *                 or a negative error code.
- */
-int mbedtls_ssl_get_max_out_record_payload( const mbedtls_ssl_context *ssl );
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-/**
- * \brief          Return the peer certificate from the current connection
- *
- *                 Note: Can be NULL in case no certificate was sent during
- *                 the handshake. Different calls for the same connection can
- *                 return the same or different pointers for the same
- *                 certificate and even a different certificate altogether.
- *                 The peer cert CAN change in a single connection if
- *                 renegotiation is performed.
- *
- * \param ssl      SSL context
- *
- * \return         the current peer certificate
- */
-const mbedtls_x509_crt *mbedtls_ssl_get_peer_cert( const mbedtls_ssl_context *ssl );
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-#if defined(MBEDTLS_SSL_CLI_C)
-/**
- * \brief          Save session in order to resume it later (client-side only)
- *                 Session data is copied to presented session structure.
- *
- *
- * \param ssl      SSL context
- * \param session  session context
- *
- * \return         0 if successful,
- *                 MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed,
- *                 MBEDTLS_ERR_SSL_BAD_INPUT_DATA if used server-side or
- *                 arguments are otherwise invalid.
- *
- * \note           Only the server certificate is copied, and not the full chain,
- *                 so you should not attempt to validate the certificate again
- *                 by calling \c mbedtls_x509_crt_verify() on it.
- *                 Instead, you should use the results from the verification
- *                 in the original handshake by calling \c mbedtls_ssl_get_verify_result()
- *                 after loading the session again into a new SSL context
- *                 using \c mbedtls_ssl_set_session().
- *
- * \note           Once the session object is not needed anymore, you should
- *                 free it by calling \c mbedtls_ssl_session_free().
- *
- * \sa             mbedtls_ssl_set_session()
- */
-int mbedtls_ssl_get_session( const mbedtls_ssl_context *ssl, mbedtls_ssl_session *session );
-#endif /* MBEDTLS_SSL_CLI_C */
-
-/**
- * \brief          Perform the SSL handshake
- *
- * \param ssl      SSL context
- *
- * \return         \c 0 if successful.
- * \return         #MBEDTLS_ERR_SSL_WANT_READ or #MBEDTLS_ERR_SSL_WANT_WRITE
- *                 if the handshake is incomplete and waiting for data to
- *                 be available for reading from or writing to the underlying
- *                 transport - in this case you must call this function again
- *                 when the underlying transport is ready for the operation.
- * \return         #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if an asynchronous
- *                 operation is in progress (see
- *                 mbedtls_ssl_conf_async_private_cb()) - in this case you
- *                 must call this function again when the operation is ready.
- * \return         #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS if a cryptographic
- *                 operation is in progress (see mbedtls_ecp_set_max_ops()) -
- *                 in this case you must call this function again to complete
- *                 the handshake when you're done attending other tasks.
- * \return         #MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED if DTLS is in use
- *                 and the client did not demonstrate reachability yet - in
- *                 this case you must stop using the context (see below).
- * \return         Another SSL error code - in this case you must stop using
- *                 the context (see below).
- *
- * \warning        If this function returns something other than
- *                 \c 0,
- *                 #MBEDTLS_ERR_SSL_WANT_READ,
- *                 #MBEDTLS_ERR_SSL_WANT_WRITE,
- *                 #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or
- *                 #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS,
- *                 you must stop using the SSL context for reading or writing,
- *                 and either free it or call \c mbedtls_ssl_session_reset()
- *                 on it before re-using it for a new connection; the current
- *                 connection must be closed.
- *
- * \note           If DTLS is in use, then you may choose to handle
- *                 #MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED specially for logging
- *                 purposes, as it is an expected return value rather than an
- *                 actual error, but you still need to reset/free the context.
- *
- * \note           Remarks regarding event-driven DTLS:
- *                 If the function returns #MBEDTLS_ERR_SSL_WANT_READ, no datagram
- *                 from the underlying transport layer is currently being processed,
- *                 and it is safe to idle until the timer or the underlying transport
- *                 signal a new event. This is not true for a successful handshake,
- *                 in which case the datagram of the underlying transport that is
- *                 currently being processed might or might not contain further
- *                 DTLS records.
- */
-int mbedtls_ssl_handshake( mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Perform a single step of the SSL handshake
- *
- * \note           The state of the context (ssl->state) will be at
- *                 the next state after this function returns \c 0. Do not
- *                 call this function if state is MBEDTLS_SSL_HANDSHAKE_OVER.
- *
- * \param ssl      SSL context
- *
- * \return         See mbedtls_ssl_handshake().
- *
- * \warning        If this function returns something other than \c 0,
- *                 #MBEDTLS_ERR_SSL_WANT_READ, #MBEDTLS_ERR_SSL_WANT_WRITE,
- *                 #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or
- *                 #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, you must stop using
- *                 the SSL context for reading or writing, and either free it
- *                 or call \c mbedtls_ssl_session_reset() on it before
- *                 re-using it for a new connection; the current connection
- *                 must be closed.
- */
-int mbedtls_ssl_handshake_step( mbedtls_ssl_context *ssl );
-
-#if defined(MBEDTLS_SSL_RENEGOTIATION)
-/**
- * \brief          Initiate an SSL renegotiation on the running connection.
- *                 Client: perform the renegotiation right now.
- *                 Server: request renegotiation, which will be performed
- *                 during the next call to mbedtls_ssl_read() if honored by
- *                 client.
- *
- * \param ssl      SSL context
- *
- * \return         0 if successful, or any mbedtls_ssl_handshake() return
- *                 value except #MBEDTLS_ERR_SSL_CLIENT_RECONNECT that can't
- *                 happen during a renegotiation.
- *
- * \warning        If this function returns something other than \c 0,
- *                 #MBEDTLS_ERR_SSL_WANT_READ, #MBEDTLS_ERR_SSL_WANT_WRITE,
- *                 #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or
- *                 #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, you must stop using
- *                 the SSL context for reading or writing, and either free it
- *                 or call \c mbedtls_ssl_session_reset() on it before
- *                 re-using it for a new connection; the current connection
- *                 must be closed.
- *
- */
-int mbedtls_ssl_renegotiate( mbedtls_ssl_context *ssl );
-#endif /* MBEDTLS_SSL_RENEGOTIATION */
-
-/**
- * \brief          Read at most 'len' application data bytes
- *
- * \param ssl      SSL context
- * \param buf      buffer that will hold the data
- * \param len      maximum number of bytes to read
- *
- * \return         The (positive) number of bytes read if successful.
- * \return         \c 0 if the read end of the underlying transport was closed
- *                 - in this case you must stop using the context (see below).
- * \return         #MBEDTLS_ERR_SSL_WANT_READ or #MBEDTLS_ERR_SSL_WANT_WRITE
- *                 if the handshake is incomplete and waiting for data to
- *                 be available for reading from or writing to the underlying
- *                 transport - in this case you must call this function again
- *                 when the underlying transport is ready for the operation.
- * \return         #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if an asynchronous
- *                 operation is in progress (see
- *                 mbedtls_ssl_conf_async_private_cb()) - in this case you
- *                 must call this function again when the operation is ready.
- * \return         #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS if a cryptographic
- *                 operation is in progress (see mbedtls_ecp_set_max_ops()) -
- *                 in this case you must call this function again to complete
- *                 the handshake when you're done attending other tasks.
- * \return         #MBEDTLS_ERR_SSL_CLIENT_RECONNECT if we're at the server
- *                 side of a DTLS connection and the client is initiating a
- *                 new connection using the same source port. See below.
- * \return         Another SSL error code - in this case you must stop using
- *                 the context (see below).
- *
- * \warning        If this function returns something other than
- *                 a positive value,
- *                 #MBEDTLS_ERR_SSL_WANT_READ,
- *                 #MBEDTLS_ERR_SSL_WANT_WRITE,
- *                 #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS,
- *                 #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS or
- *                 #MBEDTLS_ERR_SSL_CLIENT_RECONNECT,
- *                 you must stop using the SSL context for reading or writing,
- *                 and either free it or call \c mbedtls_ssl_session_reset()
- *                 on it before re-using it for a new connection; the current
- *                 connection must be closed.
- *
- * \note           When this function returns #MBEDTLS_ERR_SSL_CLIENT_RECONNECT
- *                 (which can only happen server-side), it means that a client
- *                 is initiating a new connection using the same source port.
- *                 You can either treat that as a connection close and wait
- *                 for the client to resend a ClientHello, or directly
- *                 continue with \c mbedtls_ssl_handshake() with the same
- *                 context (as it has been reset internally). Either way, you
- *                 must make sure this is seen by the application as a new
- *                 connection: application state, if any, should be reset, and
- *                 most importantly the identity of the client must be checked
- *                 again. WARNING: not validating the identity of the client
- *                 again, or not transmitting the new identity to the
- *                 application layer, would allow authentication bypass!
- *
- * \note           Remarks regarding event-driven DTLS:
- *                 - If the function returns #MBEDTLS_ERR_SSL_WANT_READ, no datagram
- *                   from the underlying transport layer is currently being processed,
- *                   and it is safe to idle until the timer or the underlying transport
- *                   signal a new event.
- *                 - This function may return MBEDTLS_ERR_SSL_WANT_READ even if data was
- *                   initially available on the underlying transport, as this data may have
- *                   been only e.g. duplicated messages or a renegotiation request.
- *                   Therefore, you must be prepared to receive MBEDTLS_ERR_SSL_WANT_READ even
- *                   when reacting to an incoming-data event from the underlying transport.
- *                 - On success, the datagram of the underlying transport that is currently
- *                   being processed may contain further DTLS records. You should call
- *                   \c mbedtls_ssl_check_pending to check for remaining records.
- *
- */
-int mbedtls_ssl_read( mbedtls_ssl_context *ssl, unsigned char *buf, size_t len );
-
-/**
- * \brief          Try to write exactly 'len' application data bytes
- *
- * \warning        This function will do partial writes in some cases. If the
- *                 return value is non-negative but less than length, the
- *                 function must be called again with updated arguments:
- *                 buf + ret, len - ret (if ret is the return value) until
- *                 it returns a value equal to the last 'len' argument.
- *
- * \param ssl      SSL context
- * \param buf      buffer holding the data
- * \param len      how many bytes must be written
- *
- * \return         The (non-negative) number of bytes actually written if
- *                 successful (may be less than \p len).
- * \return         #MBEDTLS_ERR_SSL_WANT_READ or #MBEDTLS_ERR_SSL_WANT_WRITE
- *                 if the handshake is incomplete and waiting for data to
- *                 be available for reading from or writing to the underlying
- *                 transport - in this case you must call this function again
- *                 when the underlying transport is ready for the operation.
- * \return         #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if an asynchronous
- *                 operation is in progress (see
- *                 mbedtls_ssl_conf_async_private_cb()) - in this case you
- *                 must call this function again when the operation is ready.
- * \return         #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS if a cryptographic
- *                 operation is in progress (see mbedtls_ecp_set_max_ops()) -
- *                 in this case you must call this function again to complete
- *                 the handshake when you're done attending other tasks.
- * \return         Another SSL error code - in this case you must stop using
- *                 the context (see below).
- *
- * \warning        If this function returns something other than
- *                 a non-negative value,
- *                 #MBEDTLS_ERR_SSL_WANT_READ,
- *                 #MBEDTLS_ERR_SSL_WANT_WRITE,
- *                 #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or
- *                 #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS,
- *                 you must stop using the SSL context for reading or writing,
- *                 and either free it or call \c mbedtls_ssl_session_reset()
- *                 on it before re-using it for a new connection; the current
- *                 connection must be closed.
- *
- * \note           When this function returns #MBEDTLS_ERR_SSL_WANT_WRITE/READ,
- *                 it must be called later with the *same* arguments,
- *                 until it returns a value greater that or equal to 0. When
- *                 the function returns #MBEDTLS_ERR_SSL_WANT_WRITE there may be
- *                 some partial data in the output buffer, however this is not
- *                 yet sent.
- *
- * \note           If the requested length is greater than the maximum
- *                 fragment length (either the built-in limit or the one set
- *                 or negotiated with the peer), then:
- *                 - with TLS, less bytes than requested are written.
- *                 - with DTLS, MBEDTLS_ERR_SSL_BAD_INPUT_DATA is returned.
- *                 \c mbedtls_ssl_get_max_frag_len() may be used to query the
- *                 active maximum fragment length.
- *
- * \note           Attempting to write 0 bytes will result in an empty TLS
- *                 application record being sent.
- */
-int mbedtls_ssl_write( mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len );
-
-/**
- * \brief           Send an alert message
- *
- * \param ssl       SSL context
- * \param level     The alert level of the message
- *                  (MBEDTLS_SSL_ALERT_LEVEL_WARNING or MBEDTLS_SSL_ALERT_LEVEL_FATAL)
- * \param message   The alert message (SSL_ALERT_MSG_*)
- *
- * \return          0 if successful, or a specific SSL error code.
- *
- * \note           If this function returns something other than 0 or
- *                 MBEDTLS_ERR_SSL_WANT_READ/WRITE, you must stop using
- *                 the SSL context for reading or writing, and either free it or
- *                 call \c mbedtls_ssl_session_reset() on it before re-using it
- *                 for a new connection; the current connection must be closed.
- */
-int mbedtls_ssl_send_alert_message( mbedtls_ssl_context *ssl,
-                            unsigned char level,
-                            unsigned char message );
-/**
- * \brief          Notify the peer that the connection is being closed
- *
- * \param ssl      SSL context
- *
- * \return          0 if successful, or a specific SSL error code.
- *
- * \note           If this function returns something other than 0 or
- *                 MBEDTLS_ERR_SSL_WANT_READ/WRITE, you must stop using
- *                 the SSL context for reading or writing, and either free it or
- *                 call \c mbedtls_ssl_session_reset() on it before re-using it
- *                 for a new connection; the current connection must be closed.
- */
-int mbedtls_ssl_close_notify( mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Free referenced items in an SSL context and clear memory
- *
- * \param ssl      SSL context
- */
-void mbedtls_ssl_free( mbedtls_ssl_context *ssl );
-
-/**
- * \brief          Initialize an SSL configuration context
- *                 Just makes the context ready for
- *                 mbedtls_ssl_config_defaults() or mbedtls_ssl_config_free().
- *
- * \note           You need to call mbedtls_ssl_config_defaults() unless you
- *                 manually set all of the relevant fields yourself.
- *
- * \param conf     SSL configuration context
- */
-void mbedtls_ssl_config_init( mbedtls_ssl_config *conf );
-
-/**
- * \brief          Load reasonnable default SSL configuration values.
- *                 (You need to call mbedtls_ssl_config_init() first.)
- *
- * \param conf     SSL configuration context
- * \param endpoint MBEDTLS_SSL_IS_CLIENT or MBEDTLS_SSL_IS_SERVER
- * \param transport MBEDTLS_SSL_TRANSPORT_STREAM for TLS, or
- *                  MBEDTLS_SSL_TRANSPORT_DATAGRAM for DTLS
- * \param preset   a MBEDTLS_SSL_PRESET_XXX value
- *
- * \note           See \c mbedtls_ssl_conf_transport() for notes on DTLS.
- *
- * \return         0 if successful, or
- *                 MBEDTLS_ERR_XXX_ALLOC_FAILED on memory allocation error.
- */
-int mbedtls_ssl_config_defaults( mbedtls_ssl_config *conf,
-                                 int endpoint, int transport, int preset );
-
-/**
- * \brief          Free an SSL configuration context
- *
- * \param conf     SSL configuration context
- */
-void mbedtls_ssl_config_free( mbedtls_ssl_config *conf );
-
-/**
- * \brief          Initialize SSL session structure
- *
- * \param session  SSL session
- */
-void mbedtls_ssl_session_init( mbedtls_ssl_session *session );
-
-/**
- * \brief          Free referenced items in an SSL session including the
- *                 peer certificate and clear memory
- *
- * \note           A session object can be freed even if the SSL context
- *                 that was used to retrieve the session is still in use.
- *
- * \param session  SSL session
- */
-void mbedtls_ssl_session_free( mbedtls_ssl_session *session );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ssl.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h b/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h
deleted file mode 100644
index e987c29e110..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ssl_cache.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/**
- * \file ssl_cache.h
- *
- * \brief SSL session cache implementation
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SSL_CACHE_H
-#define MBEDTLS_SSL_CACHE_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "ssl.h"
-
-#if defined(MBEDTLS_THREADING_C)
-#include "threading.h"
-#endif
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h or define them on the compiler command line.
- * \{
- */
-
-#if !defined(MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT)
-#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT       86400   /*!< 1 day  */
-#endif
-
-#if !defined(MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES)
-#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES      50   /*!< Maximum entries in cache */
-#endif
-
-/* \} name SECTION: Module settings */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct mbedtls_ssl_cache_context mbedtls_ssl_cache_context;
-typedef struct mbedtls_ssl_cache_entry mbedtls_ssl_cache_entry;
-
-/**
- * \brief   This structure is used for storing cache entries
- */
-struct mbedtls_ssl_cache_entry
-{
-#if defined(MBEDTLS_HAVE_TIME)
-    mbedtls_time_t timestamp;           /*!< entry timestamp    */
-#endif
-    mbedtls_ssl_session session;        /*!< entry session      */
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-    mbedtls_x509_buf peer_cert;         /*!< entry peer_cert    */
-#endif
-    mbedtls_ssl_cache_entry *next;      /*!< chain pointer      */
-};
-
-/**
- * \brief Cache context
- */
-struct mbedtls_ssl_cache_context
-{
-    mbedtls_ssl_cache_entry *chain;     /*!< start of the chain     */
-    int timeout;                /*!< cache entry timeout    */
-    int max_entries;            /*!< maximum entries        */
-#if defined(MBEDTLS_THREADING_C)
-    mbedtls_threading_mutex_t mutex;    /*!< mutex                  */
-#endif
-};
-
-/**
- * \brief          Initialize an SSL cache context
- *
- * \param cache    SSL cache context
- */
-void mbedtls_ssl_cache_init( mbedtls_ssl_cache_context *cache );
-
-/**
- * \brief          Cache get callback implementation
- *                 (Thread-safe if MBEDTLS_THREADING_C is enabled)
- *
- * \param data     SSL cache context
- * \param session  session to retrieve entry for
- */
-int mbedtls_ssl_cache_get( void *data, mbedtls_ssl_session *session );
-
-/**
- * \brief          Cache set callback implementation
- *                 (Thread-safe if MBEDTLS_THREADING_C is enabled)
- *
- * \param data     SSL cache context
- * \param session  session to store entry for
- */
-int mbedtls_ssl_cache_set( void *data, const mbedtls_ssl_session *session );
-
-#if defined(MBEDTLS_HAVE_TIME)
-/**
- * \brief          Set the cache timeout
- *                 (Default: MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT (1 day))
- *
- *                 A timeout of 0 indicates no timeout.
- *
- * \param cache    SSL cache context
- * \param timeout  cache entry timeout in seconds
- */
-void mbedtls_ssl_cache_set_timeout( mbedtls_ssl_cache_context *cache, int timeout );
-#endif /* MBEDTLS_HAVE_TIME */
-
-/**
- * \brief          Set the maximum number of cache entries
- *                 (Default: MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES (50))
- *
- * \param cache    SSL cache context
- * \param max      cache entry maximum
- */
-void mbedtls_ssl_cache_set_max_entries( mbedtls_ssl_cache_context *cache, int max );
-
-/**
- * \brief          Free referenced items in a cache context and clear memory
- *
- * \param cache    SSL cache context
- */
-void mbedtls_ssl_cache_free( mbedtls_ssl_cache_context *cache );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ssl_cache.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h b/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h
deleted file mode 100644
index 8969141165e..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ssl_ciphersuites.h
+++ /dev/null
@@ -1,567 +0,0 @@
-/**
- * \file ssl_ciphersuites.h
- *
- * \brief SSL Ciphersuites for mbed TLS
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SSL_CIPHERSUITES_H
-#define MBEDTLS_SSL_CIPHERSUITES_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "pk.h"
-#include "cipher.h"
-#include "md.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Supported ciphersuites (Official IANA names)
- */
-#define MBEDTLS_TLS_RSA_WITH_NULL_MD5                    0x01   /**< Weak! */
-#define MBEDTLS_TLS_RSA_WITH_NULL_SHA                    0x02   /**< Weak! */
-
-#define MBEDTLS_TLS_RSA_WITH_RC4_128_MD5                 0x04
-#define MBEDTLS_TLS_RSA_WITH_RC4_128_SHA                 0x05
-#define MBEDTLS_TLS_RSA_WITH_DES_CBC_SHA                 0x09   /**< Weak! Not in TLS 1.2 */
-
-#define MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA            0x0A
-
-#define MBEDTLS_TLS_DHE_RSA_WITH_DES_CBC_SHA             0x15   /**< Weak! Not in TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA        0x16
-
-#define MBEDTLS_TLS_PSK_WITH_NULL_SHA                    0x2C   /**< Weak! */
-#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA                0x2D   /**< Weak! */
-#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA                0x2E   /**< Weak! */
-#define MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA             0x2F
-
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA         0x33
-#define MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA             0x35
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA         0x39
-
-#define MBEDTLS_TLS_RSA_WITH_NULL_SHA256                 0x3B   /**< Weak! */
-#define MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256          0x3C   /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256          0x3D   /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA        0x41
-#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA    0x45
-
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256      0x67   /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256      0x6B   /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA        0x84
-#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA    0x88
-
-#define MBEDTLS_TLS_PSK_WITH_RC4_128_SHA                 0x8A
-#define MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA            0x8B
-#define MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA             0x8C
-#define MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA             0x8D
-
-#define MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA             0x8E
-#define MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA        0x8F
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA         0x90
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA         0x91
-
-#define MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA             0x92
-#define MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA        0x93
-#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA         0x94
-#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA         0x95
-
-#define MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256          0x9C   /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384          0x9D   /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256      0x9E   /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384      0x9F   /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256          0xA8   /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384          0xA9   /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256      0xAA   /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384      0xAB   /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256      0xAC   /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384      0xAD   /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256          0xAE
-#define MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384          0xAF
-#define MBEDTLS_TLS_PSK_WITH_NULL_SHA256                 0xB0   /**< Weak! */
-#define MBEDTLS_TLS_PSK_WITH_NULL_SHA384                 0xB1   /**< Weak! */
-
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256      0xB2
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384      0xB3
-#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256             0xB4   /**< Weak! */
-#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384             0xB5   /**< Weak! */
-
-#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256      0xB6
-#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384      0xB7
-#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256             0xB8   /**< Weak! */
-#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384             0xB9   /**< Weak! */
-
-#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256     0xBA   /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xBE   /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256     0xC0   /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 0xC4   /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA             0xC001 /**< Weak! */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_RC4_128_SHA          0xC002 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_3DES_EDE_CBC_SHA     0xC003 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA      0xC004 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA      0xC005 /**< Not in SSL3! */
-
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA            0xC006 /**< Weak! */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA         0xC007 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA    0xC008 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA     0xC009 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA     0xC00A /**< Not in SSL3! */
-
-#define MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA               0xC00B /**< Weak! */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_RC4_128_SHA            0xC00C /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_3DES_EDE_CBC_SHA       0xC00D /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA        0xC00E /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA        0xC00F /**< Not in SSL3! */
-
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA              0xC010 /**< Weak! */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA           0xC011 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA      0xC012 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA       0xC013 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA       0xC014 /**< Not in SSL3! */
-
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256  0xC023 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384  0xC024 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256   0xC025 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384   0xC026 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256    0xC027 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384    0xC028 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256     0xC029 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384     0xC02A /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256  0xC02B /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384  0xC02C /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256   0xC02D /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384   0xC02E /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256    0xC02F /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384    0xC030 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256     0xC031 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384     0xC032 /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA           0xC033 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA      0xC034 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA       0xC035 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA       0xC036 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256    0xC037 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384    0xC038 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA              0xC039 /**< Weak! No SSL3! */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256           0xC03A /**< Weak! No SSL3! */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384           0xC03B /**< Weak! No SSL3! */
-
-#define MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256         0xC03C /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384         0xC03D /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256     0xC044 /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384     0xC045 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256 0xC048 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384 0xC049 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256  0xC04A /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384  0xC04B /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256   0xC04C /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384   0xC04D /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256    0xC04E /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384    0xC04F /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256         0xC050 /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384         0xC051 /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256     0xC052 /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384     0xC053 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256 0xC05C /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384 0xC05D /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256  0xC05E /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384  0xC05F /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256   0xC060 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384   0xC061 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256    0xC062 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384    0xC063 /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256         0xC064 /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384         0xC065 /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256     0xC066 /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384     0xC067 /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256     0xC068 /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384     0xC069 /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256         0xC06A /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384         0xC06B /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256     0xC06C /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384     0xC06D /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256     0xC06E /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384     0xC06F /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256   0xC070 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384   0xC071 /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 0xC072 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 0xC073 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256  0xC074 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384  0xC075 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256   0xC076 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384   0xC077 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256    0xC078 /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384    0xC079 /**< Not in SSL3! */
-
-#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256         0xC07A /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384         0xC07B /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256     0xC07C /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384     0xC07D /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 0xC086 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 0xC087 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256  0xC088 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384  0xC089 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256   0xC08A /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384   0xC08B /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256    0xC08C /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384    0xC08D /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256       0xC08E /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384       0xC08F /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256   0xC090 /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384   0xC091 /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256   0xC092 /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384   0xC093 /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256       0xC094
-#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384       0xC095
-#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256   0xC096
-#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384   0xC097
-#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256   0xC098
-#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384   0xC099
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC09A /**< Not in SSL3! */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC09B /**< Not in SSL3! */
-
-#define MBEDTLS_TLS_RSA_WITH_AES_128_CCM                0xC09C  /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_WITH_AES_256_CCM                0xC09D  /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM            0xC09E  /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM            0xC09F  /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_WITH_AES_128_CCM_8              0xC0A0  /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_WITH_AES_256_CCM_8              0xC0A1  /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM_8          0xC0A2  /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM_8          0xC0A3  /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_AES_128_CCM                0xC0A4  /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_AES_256_CCM                0xC0A5  /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM            0xC0A6  /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM            0xC0A7  /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8              0xC0A8  /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8              0xC0A9  /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM_8          0xC0AA  /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM_8          0xC0AB  /**< TLS 1.2 */
-/* The last two are named with PSK_DHE in the RFC, which looks like a typo */
-
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM        0xC0AC  /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM        0xC0AD  /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8      0xC0AE  /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8      0xC0AF  /**< TLS 1.2 */
-
-#define MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8          0xC0FF  /**< experimental */
-
-/* RFC 7905 */
-#define MBEDTLS_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256   0xCCA8 /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 0xCCA9 /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256     0xCCAA /**< TLS 1.2 */
-#define MBEDTLS_TLS_PSK_WITH_CHACHA20_POLY1305_SHA256         0xCCAB /**< TLS 1.2 */
-#define MBEDTLS_TLS_ECDHE_PSK_WITH_CHACHA20_POLY1305_SHA256   0xCCAC /**< TLS 1.2 */
-#define MBEDTLS_TLS_DHE_PSK_WITH_CHACHA20_POLY1305_SHA256     0xCCAD /**< TLS 1.2 */
-#define MBEDTLS_TLS_RSA_PSK_WITH_CHACHA20_POLY1305_SHA256     0xCCAE /**< TLS 1.2 */
-
-/* Reminder: update mbedtls_ssl_premaster_secret when adding a new key exchange.
- * Reminder: update MBEDTLS_KEY_EXCHANGE__xxx below
- */
-typedef enum {
-    MBEDTLS_KEY_EXCHANGE_NONE = 0,
-    MBEDTLS_KEY_EXCHANGE_RSA,
-    MBEDTLS_KEY_EXCHANGE_DHE_RSA,
-    MBEDTLS_KEY_EXCHANGE_ECDHE_RSA,
-    MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA,
-    MBEDTLS_KEY_EXCHANGE_PSK,
-    MBEDTLS_KEY_EXCHANGE_DHE_PSK,
-    MBEDTLS_KEY_EXCHANGE_RSA_PSK,
-    MBEDTLS_KEY_EXCHANGE_ECDHE_PSK,
-    MBEDTLS_KEY_EXCHANGE_ECDH_RSA,
-    MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA,
-    MBEDTLS_KEY_EXCHANGE_ECJPAKE,
-} mbedtls_key_exchange_type_t;
-
-/* Key exchanges using a certificate */
-#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED)           || \
-    defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)       || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)     || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)   || \
-    defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED)       || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED)      || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED
-#endif
-
-/* Key exchanges allowing client certificate requests */
-#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED)           ||       \
-    defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)       ||       \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED)      ||       \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)     ||       \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED)    ||       \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE__CERT_REQ_ALLOWED__ENABLED
-#endif
-
-/* Key exchanges involving server signature in ServerKeyExchange */
-#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)       || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)     || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE__WITH_SERVER_SIGNATURE__ENABLED
-#endif
-
-/* Key exchanges using ECDH */
-#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED)      || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE__SOME__ECDH_ENABLED
-#endif
-
-/* Key exchanges that don't involve ephemeral keys */
-#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED)           || \
-    defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED)           || \
-    defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED)       || \
-    defined(MBEDTLS_KEY_EXCHANGE__SOME__ECDH_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE__SOME_NON_PFS__ENABLED
-#endif
-
-/* Key exchanges that involve ephemeral keys */
-#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)       || \
-    defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED)       || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)     || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED)     || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)   || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE__SOME_PFS__ENABLED
-#endif
-
-/* Key exchanges using a PSK */
-#if defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED)           || \
-    defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED)       || \
-    defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED)       || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED
-#endif
-
-/* Key exchanges using DHE */
-#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)       || \
-    defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE__SOME__DHE_ENABLED
-#endif
-
-/* Key exchanges using ECDHE */
-#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)     || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)   || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE__SOME__ECDHE_ENABLED
-#endif
-
-typedef struct mbedtls_ssl_ciphersuite_t mbedtls_ssl_ciphersuite_t;
-
-#define MBEDTLS_CIPHERSUITE_WEAK       0x01    /**< Weak ciphersuite flag  */
-#define MBEDTLS_CIPHERSUITE_SHORT_TAG  0x02    /**< Short authentication tag,
-                                                     eg for CCM_8 */
-#define MBEDTLS_CIPHERSUITE_NODTLS     0x04    /**< Can't be used with DTLS */
-
-/**
- * \brief   This structure is used for storing ciphersuite information
- */
-struct mbedtls_ssl_ciphersuite_t
-{
-    int id;
-    const char * name;
-
-    mbedtls_cipher_type_t cipher;
-    mbedtls_md_type_t mac;
-    mbedtls_key_exchange_type_t key_exchange;
-
-    int min_major_ver;
-    int min_minor_ver;
-    int max_major_ver;
-    int max_minor_ver;
-
-    unsigned char flags;
-};
-
-const int *mbedtls_ssl_list_ciphersuites( void );
-
-const mbedtls_ssl_ciphersuite_t *mbedtls_ssl_ciphersuite_from_string( const char *ciphersuite_name );
-const mbedtls_ssl_ciphersuite_t *mbedtls_ssl_ciphersuite_from_id( int ciphersuite_id );
-
-#if defined(MBEDTLS_PK_C)
-mbedtls_pk_type_t mbedtls_ssl_get_ciphersuite_sig_pk_alg( const mbedtls_ssl_ciphersuite_t *info );
-mbedtls_pk_type_t mbedtls_ssl_get_ciphersuite_sig_alg( const mbedtls_ssl_ciphersuite_t *info );
-#endif
-
-int mbedtls_ssl_ciphersuite_uses_ec( const mbedtls_ssl_ciphersuite_t *info );
-int mbedtls_ssl_ciphersuite_uses_psk( const mbedtls_ssl_ciphersuite_t *info );
-
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME_PFS__ENABLED)
-static inline int mbedtls_ssl_ciphersuite_has_pfs( const mbedtls_ssl_ciphersuite_t *info )
-{
-    switch( info->key_exchange )
-    {
-        case MBEDTLS_KEY_EXCHANGE_DHE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_DHE_PSK:
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_PSK:
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA:
-        case MBEDTLS_KEY_EXCHANGE_ECJPAKE:
-            return( 1 );
-
-        default:
-            return( 0 );
-    }
-}
-#endif /* MBEDTLS_KEY_EXCHANGE__SOME_PFS__ENABLED */
-
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME_NON_PFS__ENABLED)
-static inline int mbedtls_ssl_ciphersuite_no_pfs( const mbedtls_ssl_ciphersuite_t *info )
-{
-    switch( info->key_exchange )
-    {
-        case MBEDTLS_KEY_EXCHANGE_ECDH_RSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA:
-        case MBEDTLS_KEY_EXCHANGE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_PSK:
-        case MBEDTLS_KEY_EXCHANGE_RSA_PSK:
-            return( 1 );
-
-        default:
-            return( 0 );
-    }
-}
-#endif /* MBEDTLS_KEY_EXCHANGE__SOME_NON_PFS__ENABLED */
-
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME__ECDH_ENABLED)
-static inline int mbedtls_ssl_ciphersuite_uses_ecdh( const mbedtls_ssl_ciphersuite_t *info )
-{
-    switch( info->key_exchange )
-    {
-        case MBEDTLS_KEY_EXCHANGE_ECDH_RSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA:
-            return( 1 );
-
-        default:
-            return( 0 );
-    }
-}
-#endif /* MBEDTLS_KEY_EXCHANGE__SOME__ECDH_ENABLED */
-
-static inline int mbedtls_ssl_ciphersuite_cert_req_allowed( const mbedtls_ssl_ciphersuite_t *info )
-{
-    switch( info->key_exchange )
-    {
-        case MBEDTLS_KEY_EXCHANGE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_DHE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDH_RSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA:
-            return( 1 );
-
-        default:
-            return( 0 );
-    }
-}
-
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME__DHE_ENABLED)
-static inline int mbedtls_ssl_ciphersuite_uses_dhe( const mbedtls_ssl_ciphersuite_t *info )
-{
-    switch( info->key_exchange )
-    {
-        case MBEDTLS_KEY_EXCHANGE_DHE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_DHE_PSK:
-            return( 1 );
-
-        default:
-            return( 0 );
-    }
-}
-#endif /* MBEDTLS_KEY_EXCHANGE__SOME__DHE_ENABLED) */
-
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME__ECDHE_ENABLED)
-static inline int mbedtls_ssl_ciphersuite_uses_ecdhe( const mbedtls_ssl_ciphersuite_t *info )
-{
-    switch( info->key_exchange )
-    {
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_PSK:
-            return( 1 );
-
-        default:
-            return( 0 );
-    }
-}
-#endif /* MBEDTLS_KEY_EXCHANGE__SOME__ECDHE_ENABLED) */
-
-#if defined(MBEDTLS_KEY_EXCHANGE__WITH_SERVER_SIGNATURE__ENABLED)
-static inline int mbedtls_ssl_ciphersuite_uses_server_signature( const mbedtls_ssl_ciphersuite_t *info )
-{
-    switch( info->key_exchange )
-    {
-        case MBEDTLS_KEY_EXCHANGE_DHE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA:
-        case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA:
-            return( 1 );
-
-        default:
-            return( 0 );
-    }
-}
-#endif /* MBEDTLS_KEY_EXCHANGE__WITH_SERVER_SIGNATURE__ENABLED */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ssl_ciphersuites.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h b/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h
deleted file mode 100644
index 71e056781c5..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ssl_cookie.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/**
- * \file ssl_cookie.h
- *
- * \brief DTLS cookie callbacks implementation
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SSL_COOKIE_H
-#define MBEDTLS_SSL_COOKIE_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "ssl.h"
-
-#if defined(MBEDTLS_THREADING_C)
-#include "threading.h"
-#endif
-
-/**
- * \name SECTION: Module settings
- *
- * The configuration options you can set for this module are in this section.
- * Either change them in config.h or define them on the compiler command line.
- * \{
- */
-#ifndef MBEDTLS_SSL_COOKIE_TIMEOUT
-#define MBEDTLS_SSL_COOKIE_TIMEOUT     60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */
-#endif
-
-/* \} name SECTION: Module settings */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief          Context for the default cookie functions.
- */
-typedef struct mbedtls_ssl_cookie_ctx
-{
-    mbedtls_md_context_t    hmac_ctx;   /*!< context for the HMAC portion   */
-#if !defined(MBEDTLS_HAVE_TIME)
-    unsigned long   serial;     /*!< serial number for expiration   */
-#endif
-    unsigned long   timeout;    /*!< timeout delay, in seconds if HAVE_TIME,
-                                     or in number of tickets issued */
-
-#if defined(MBEDTLS_THREADING_C)
-    mbedtls_threading_mutex_t mutex;
-#endif
-} mbedtls_ssl_cookie_ctx;
-
-/**
- * \brief          Initialize cookie context
- */
-void mbedtls_ssl_cookie_init( mbedtls_ssl_cookie_ctx *ctx );
-
-/**
- * \brief          Setup cookie context (generate keys)
- */
-int mbedtls_ssl_cookie_setup( mbedtls_ssl_cookie_ctx *ctx,
-                      int (*f_rng)(void *, unsigned char *, size_t),
-                      void *p_rng );
-
-/**
- * \brief          Set expiration delay for cookies
- *                 (Default MBEDTLS_SSL_COOKIE_TIMEOUT)
- *
- * \param ctx      Cookie contex
- * \param delay    Delay, in seconds if HAVE_TIME, or in number of cookies
- *                 issued in the meantime.
- *                 0 to disable expiration (NOT recommended)
- */
-void mbedtls_ssl_cookie_set_timeout( mbedtls_ssl_cookie_ctx *ctx, unsigned long delay );
-
-/**
- * \brief          Free cookie context
- */
-void mbedtls_ssl_cookie_free( mbedtls_ssl_cookie_ctx *ctx );
-
-/**
- * \brief          Generate cookie, see \c mbedtls_ssl_cookie_write_t
- */
-mbedtls_ssl_cookie_write_t mbedtls_ssl_cookie_write;
-
-/**
- * \brief          Verify cookie, see \c mbedtls_ssl_cookie_write_t
- */
-mbedtls_ssl_cookie_check_t mbedtls_ssl_cookie_check;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ssl_cookie.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h b/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h
deleted file mode 100644
index b371094f1e8..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ssl_internal.h
+++ /dev/null
@@ -1,850 +0,0 @@
-/**
- * \file ssl_internal.h
- *
- * \brief Internal functions shared by the SSL modules
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SSL_INTERNAL_H
-#define MBEDTLS_SSL_INTERNAL_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "ssl.h"
-#include "cipher.h"
-
-#if defined(MBEDTLS_MD5_C)
-#include "md5.h"
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#include "sha1.h"
-#endif
-
-#if defined(MBEDTLS_SHA256_C)
-#include "sha256.h"
-#endif
-
-#if defined(MBEDTLS_SHA512_C)
-#include "sha512.h"
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
-#include "ecjpake.h"
-#endif
-
-#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \
-    !defined(inline) && !defined(__cplusplus)
-#define inline __inline
-#endif
-
-/* Determine minimum supported version */
-#define MBEDTLS_SSL_MIN_MAJOR_VERSION           MBEDTLS_SSL_MAJOR_VERSION_3
-
-#if defined(MBEDTLS_SSL_PROTO_SSL3)
-#define MBEDTLS_SSL_MIN_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_0
-#else
-#if defined(MBEDTLS_SSL_PROTO_TLS1)
-#define MBEDTLS_SSL_MIN_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_1
-#else
-#if defined(MBEDTLS_SSL_PROTO_TLS1_1)
-#define MBEDTLS_SSL_MIN_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_2
-#else
-#if defined(MBEDTLS_SSL_PROTO_TLS1_2)
-#define MBEDTLS_SSL_MIN_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_3
-#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */
-#endif /* MBEDTLS_SSL_PROTO_TLS1_1 */
-#endif /* MBEDTLS_SSL_PROTO_TLS1   */
-#endif /* MBEDTLS_SSL_PROTO_SSL3   */
-
-#define MBEDTLS_SSL_MIN_VALID_MINOR_VERSION MBEDTLS_SSL_MINOR_VERSION_1
-#define MBEDTLS_SSL_MIN_VALID_MAJOR_VERSION MBEDTLS_SSL_MAJOR_VERSION_3
-
-/* Determine maximum supported version */
-#define MBEDTLS_SSL_MAX_MAJOR_VERSION           MBEDTLS_SSL_MAJOR_VERSION_3
-
-#if defined(MBEDTLS_SSL_PROTO_TLS1_2)
-#define MBEDTLS_SSL_MAX_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_3
-#else
-#if defined(MBEDTLS_SSL_PROTO_TLS1_1)
-#define MBEDTLS_SSL_MAX_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_2
-#else
-#if defined(MBEDTLS_SSL_PROTO_TLS1)
-#define MBEDTLS_SSL_MAX_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_1
-#else
-#if defined(MBEDTLS_SSL_PROTO_SSL3)
-#define MBEDTLS_SSL_MAX_MINOR_VERSION           MBEDTLS_SSL_MINOR_VERSION_0
-#endif /* MBEDTLS_SSL_PROTO_SSL3   */
-#endif /* MBEDTLS_SSL_PROTO_TLS1   */
-#endif /* MBEDTLS_SSL_PROTO_TLS1_1 */
-#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */
-
-/* Shorthand for restartable ECC */
-#if defined(MBEDTLS_ECP_RESTARTABLE) && \
-    defined(MBEDTLS_SSL_CLI_C) && \
-    defined(MBEDTLS_SSL_PROTO_TLS1_2) && \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)
-#define MBEDTLS_SSL__ECP_RESTARTABLE
-#endif
-
-#define MBEDTLS_SSL_INITIAL_HANDSHAKE           0
-#define MBEDTLS_SSL_RENEGOTIATION_IN_PROGRESS   1   /* In progress */
-#define MBEDTLS_SSL_RENEGOTIATION_DONE          2   /* Done or aborted */
-#define MBEDTLS_SSL_RENEGOTIATION_PENDING       3   /* Requested (server only) */
-
-/*
- * DTLS retransmission states, see RFC 6347 4.2.4
- *
- * The SENDING state is merged in PREPARING for initial sends,
- * but is distinct for resends.
- *
- * Note: initial state is wrong for server, but is not used anyway.
- */
-#define MBEDTLS_SSL_RETRANS_PREPARING       0
-#define MBEDTLS_SSL_RETRANS_SENDING         1
-#define MBEDTLS_SSL_RETRANS_WAITING         2
-#define MBEDTLS_SSL_RETRANS_FINISHED        3
-
-/*
- * Allow extra bytes for record, authentication and encryption overhead:
- * counter (8) + header (5) + IV(16) + MAC (16-48) + padding (0-256)
- * and allow for a maximum of 1024 of compression expansion if
- * enabled.
- */
-#if defined(MBEDTLS_ZLIB_SUPPORT)
-#define MBEDTLS_SSL_COMPRESSION_ADD          1024
-#else
-#define MBEDTLS_SSL_COMPRESSION_ADD             0
-#endif
-
-#if defined(MBEDTLS_ARC4_C) || defined(MBEDTLS_CIPHER_MODE_CBC)
-/* Ciphersuites using HMAC */
-#if defined(MBEDTLS_SHA512_C)
-#define MBEDTLS_SSL_MAC_ADD                 48  /* SHA-384 used for HMAC */
-#elif defined(MBEDTLS_SHA256_C)
-#define MBEDTLS_SSL_MAC_ADD                 32  /* SHA-256 used for HMAC */
-#else
-#define MBEDTLS_SSL_MAC_ADD                 20  /* SHA-1   used for HMAC */
-#endif
-#else
-/* AEAD ciphersuites: GCM and CCM use a 128 bits tag */
-#define MBEDTLS_SSL_MAC_ADD                 16
-#endif
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-#define MBEDTLS_SSL_PADDING_ADD            256
-#else
-#define MBEDTLS_SSL_PADDING_ADD              0
-#endif
-
-#define MBEDTLS_SSL_PAYLOAD_OVERHEAD ( MBEDTLS_SSL_COMPRESSION_ADD +    \
-                                       MBEDTLS_MAX_IV_LENGTH +          \
-                                       MBEDTLS_SSL_MAC_ADD +            \
-                                       MBEDTLS_SSL_PADDING_ADD          \
-                                       )
-
-#define MBEDTLS_SSL_IN_PAYLOAD_LEN ( MBEDTLS_SSL_PAYLOAD_OVERHEAD + \
-                                     ( MBEDTLS_SSL_IN_CONTENT_LEN ) )
-
-#define MBEDTLS_SSL_OUT_PAYLOAD_LEN ( MBEDTLS_SSL_PAYLOAD_OVERHEAD + \
-                                      ( MBEDTLS_SSL_OUT_CONTENT_LEN ) )
-
-/* The maximum number of buffered handshake messages. */
-#define MBEDTLS_SSL_MAX_BUFFERED_HS 4
-
-/* Maximum length we can advertise as our max content length for
-   RFC 6066 max_fragment_length extension negotiation purposes
-   (the lesser of both sizes, if they are unequal.)
- */
-#define MBEDTLS_TLS_EXT_ADV_CONTENT_LEN (                            \
-        (MBEDTLS_SSL_IN_CONTENT_LEN > MBEDTLS_SSL_OUT_CONTENT_LEN)   \
-        ? ( MBEDTLS_SSL_OUT_CONTENT_LEN )                            \
-        : ( MBEDTLS_SSL_IN_CONTENT_LEN )                             \
-        )
-
-/* Maximum size in bytes of list in sig-hash algorithm ext., RFC 5246 */
-#define MBEDTLS_SSL_MAX_SIG_HASH_ALG_LIST_LEN  65534
-
-/* Maximum size in bytes of list in supported elliptic curve ext., RFC 4492 */
-#define MBEDTLS_SSL_MAX_CURVE_LIST_LEN         65535
-
-/*
- * Check that we obey the standard's message size bounds
- */
-
-#if MBEDTLS_SSL_MAX_CONTENT_LEN > 16384
-#error "Bad configuration - record content too large."
-#endif
-
-#if MBEDTLS_SSL_IN_CONTENT_LEN > MBEDTLS_SSL_MAX_CONTENT_LEN
-#error "Bad configuration - incoming record content should not be larger than MBEDTLS_SSL_MAX_CONTENT_LEN."
-#endif
-
-#if MBEDTLS_SSL_OUT_CONTENT_LEN > MBEDTLS_SSL_MAX_CONTENT_LEN
-#error "Bad configuration - outgoing record content should not be larger than MBEDTLS_SSL_MAX_CONTENT_LEN."
-#endif
-
-#if MBEDTLS_SSL_IN_PAYLOAD_LEN > MBEDTLS_SSL_MAX_CONTENT_LEN + 2048
-#error "Bad configuration - incoming protected record payload too large."
-#endif
-
-#if MBEDTLS_SSL_OUT_PAYLOAD_LEN > MBEDTLS_SSL_MAX_CONTENT_LEN + 2048
-#error "Bad configuration - outgoing protected record payload too large."
-#endif
-
-/* Calculate buffer sizes */
-
-/* Note: Even though the TLS record header is only 5 bytes
-   long, we're internally using 8 bytes to store the
-   implicit sequence number. */
-#define MBEDTLS_SSL_HEADER_LEN 13
-
-#define MBEDTLS_SSL_IN_BUFFER_LEN  \
-    ( ( MBEDTLS_SSL_HEADER_LEN ) + ( MBEDTLS_SSL_IN_PAYLOAD_LEN ) )
-
-#define MBEDTLS_SSL_OUT_BUFFER_LEN  \
-    ( ( MBEDTLS_SSL_HEADER_LEN ) + ( MBEDTLS_SSL_OUT_PAYLOAD_LEN ) )
-
-#ifdef MBEDTLS_ZLIB_SUPPORT
-/* Compression buffer holds both IN and OUT buffers, so should be size of the larger */
-#define MBEDTLS_SSL_COMPRESS_BUFFER_LEN (                               \
-        ( MBEDTLS_SSL_IN_BUFFER_LEN > MBEDTLS_SSL_OUT_BUFFER_LEN )      \
-        ? MBEDTLS_SSL_IN_BUFFER_LEN                                     \
-        : MBEDTLS_SSL_OUT_BUFFER_LEN                                    \
-        )
-#endif
-
-/*
- * TLS extension flags (for extensions with outgoing ServerHello content
- * that need it (e.g. for RENEGOTIATION_INFO the server already knows because
- * of state of the renegotiation flag, so no indicator is required)
- */
-#define MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS_PRESENT (1 << 0)
-#define MBEDTLS_TLS_EXT_ECJPAKE_KKPP_OK                 (1 << 1)
-
-/**
- * \brief        This function checks if the remaining size in a buffer is
- *               greater or equal than a needed space.
- *
- * \param cur    Pointer to the current position in the buffer.
- * \param end    Pointer to one past the end of the buffer.
- * \param need   Needed space in bytes.
- *
- * \return       Zero if the needed space is available in the buffer, non-zero
- *               otherwise.
- */
-static inline int mbedtls_ssl_chk_buf_ptr( const uint8_t *cur,
-                                           const uint8_t *end, size_t need )
-{
-    return( ( cur > end ) || ( need > (size_t)( end - cur ) ) );
-}
-
-/**
- * \brief        This macro checks if the remaining size in a buffer is
- *               greater or equal than a needed space. If it is not the case,
- *               it returns an SSL_BUFFER_TOO_SMALL error.
- *
- * \param cur    Pointer to the current position in the buffer.
- * \param end    Pointer to one past the end of the buffer.
- * \param need   Needed space in bytes.
- *
- */
-#define MBEDTLS_SSL_CHK_BUF_PTR( cur, end, need )                        \
-    do {                                                                 \
-        if( mbedtls_ssl_chk_buf_ptr( ( cur ), ( end ), ( need ) ) != 0 ) \
-        {                                                                \
-            return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL );                  \
-        }                                                                \
-    } while( 0 )
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \
-    defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED)
-/*
- * Abstraction for a grid of allowed signature-hash-algorithm pairs.
- */
-struct mbedtls_ssl_sig_hash_set_t
-{
-    /* At the moment, we only need to remember a single suitable
-     * hash algorithm per signature algorithm. As long as that's
-     * the case - and we don't need a general lookup function -
-     * we can implement the sig-hash-set as a map from signatures
-     * to hash algorithms. */
-    mbedtls_md_type_t rsa;
-    mbedtls_md_type_t ecdsa;
-};
-#endif /* MBEDTLS_SSL_PROTO_TLS1_2 &&
-          MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED */
-
-/*
- * This structure contains the parameters only needed during handshake.
- */
-struct mbedtls_ssl_handshake_params
-{
-    /*
-     * Handshake specific crypto variables
-     */
-
-#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \
-    defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED)
-    mbedtls_ssl_sig_hash_set_t hash_algs;             /*!<  Set of suitable sig-hash pairs */
-#endif
-#if defined(MBEDTLS_DHM_C)
-    mbedtls_dhm_context dhm_ctx;                /*!<  DHM key exchange        */
-#endif
-#if defined(MBEDTLS_ECDH_C)
-    mbedtls_ecdh_context ecdh_ctx;              /*!<  ECDH key exchange       */
-#endif
-#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
-    mbedtls_ecjpake_context ecjpake_ctx;        /*!< EC J-PAKE key exchange */
-#if defined(MBEDTLS_SSL_CLI_C)
-    unsigned char *ecjpake_cache;               /*!< Cache for ClientHello ext */
-    size_t ecjpake_cache_len;                   /*!< Length of cached data */
-#endif
-#endif /* MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */
-#if defined(MBEDTLS_ECDH_C) || defined(MBEDTLS_ECDSA_C) || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
-    const mbedtls_ecp_curve_info **curves;      /*!<  Supported elliptic curves */
-#endif
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
-    unsigned char *psk;                 /*!<  PSK from the callback         */
-    size_t psk_len;                     /*!<  Length of PSK from callback   */
-#endif
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-    mbedtls_ssl_key_cert *key_cert;     /*!< chosen key/cert pair (server)  */
-#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION)
-    int sni_authmode;                   /*!< authmode from SNI callback     */
-    mbedtls_ssl_key_cert *sni_key_cert; /*!< key/cert list from SNI         */
-    mbedtls_x509_crt *sni_ca_chain;     /*!< trusted CAs from SNI callback  */
-    mbedtls_x509_crl *sni_ca_crl;       /*!< trusted CAs CRLs from SNI      */
-#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-#if defined(MBEDTLS_SSL__ECP_RESTARTABLE)
-    int ecrs_enabled;                   /*!< Handshake supports EC restart? */
-    mbedtls_x509_crt_restart_ctx ecrs_ctx;  /*!< restart context            */
-    enum { /* this complements ssl->state with info on intra-state operations */
-        ssl_ecrs_none = 0,              /*!< nothing going on (yet)         */
-        ssl_ecrs_crt_verify,            /*!< Certificate: crt_verify()      */
-        ssl_ecrs_ske_start_processing,  /*!< ServerKeyExchange: pk_verify() */
-        ssl_ecrs_cke_ecdh_calc_secret,  /*!< ClientKeyExchange: ECDH step 2 */
-        ssl_ecrs_crt_vrfy_sign,         /*!< CertificateVerify: pk_sign()   */
-    } ecrs_state;                       /*!< current (or last) operation    */
-    size_t ecrs_n;                      /*!< place for saving a length      */
-#endif
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-    unsigned int out_msg_seq;           /*!<  Outgoing handshake sequence number */
-    unsigned int in_msg_seq;            /*!<  Incoming handshake sequence number */
-
-    unsigned char *verify_cookie;       /*!<  Cli: HelloVerifyRequest cookie
-                                              Srv: unused                    */
-    unsigned char verify_cookie_len;    /*!<  Cli: cookie length
-                                              Srv: flag for sending a cookie */
-
-    uint32_t retransmit_timeout;        /*!<  Current value of timeout       */
-    unsigned char retransmit_state;     /*!<  Retransmission state           */
-    mbedtls_ssl_flight_item *flight;    /*!<  Current outgoing flight        */
-    mbedtls_ssl_flight_item *cur_msg;   /*!<  Current message in flight      */
-    unsigned char *cur_msg_p;           /*!<  Position in current message    */
-    unsigned int in_flight_start_seq;   /*!<  Minimum message sequence in the
-                                              flight being received          */
-    mbedtls_ssl_transform *alt_transform_out;   /*!<  Alternative transform for
-                                              resending messages             */
-    unsigned char alt_out_ctr[8];       /*!<  Alternative record epoch/counter
-                                              for resending messages         */
-
-    struct
-    {
-        size_t total_bytes_buffered; /*!< Cumulative size of heap allocated
-                                      *   buffers used for message buffering. */
-
-        uint8_t seen_ccs;               /*!< Indicates if a CCS message has
-                                         *   been seen in the current flight. */
-
-        struct mbedtls_ssl_hs_buffer
-        {
-            unsigned is_valid      : 1;
-            unsigned is_fragmented : 1;
-            unsigned is_complete   : 1;
-            unsigned char *data;
-            size_t data_len;
-        } hs[MBEDTLS_SSL_MAX_BUFFERED_HS];
-
-        struct
-        {
-            unsigned char *data;
-            size_t len;
-            unsigned epoch;
-        } future_record;
-
-    } buffering;
-
-    uint16_t mtu;                       /*!<  Handshake mtu, used to fragment outgoing messages */
-#endif /* MBEDTLS_SSL_PROTO_DTLS */
-
-    /*
-     * Checksum contexts
-     */
-#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) || \
-    defined(MBEDTLS_SSL_PROTO_TLS1_1)
-       mbedtls_md5_context fin_md5;
-      mbedtls_sha1_context fin_sha1;
-#endif
-#if defined(MBEDTLS_SSL_PROTO_TLS1_2)
-#if defined(MBEDTLS_SHA256_C)
-    mbedtls_sha256_context fin_sha256;
-#endif
-#if defined(MBEDTLS_SHA512_C)
-    mbedtls_sha512_context fin_sha512;
-#endif
-#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */
-
-    void (*update_checksum)(mbedtls_ssl_context *, const unsigned char *, size_t);
-    void (*calc_verify)(mbedtls_ssl_context *, unsigned char *);
-    void (*calc_finished)(mbedtls_ssl_context *, unsigned char *, int);
-    int  (*tls_prf)(const unsigned char *, size_t, const char *,
-                    const unsigned char *, size_t,
-                    unsigned char *, size_t);
-
-    size_t pmslen;                      /*!<  premaster length        */
-
-    unsigned char randbytes[64];        /*!<  random bytes            */
-    unsigned char premaster[MBEDTLS_PREMASTER_SIZE];
-                                        /*!<  premaster secret        */
-
-    int resume;                         /*!<  session resume indicator*/
-    int max_major_ver;                  /*!< max. major version client*/
-    int max_minor_ver;                  /*!< max. minor version client*/
-    int cli_exts;                       /*!< client extension presence*/
-
-#if defined(MBEDTLS_SSL_SESSION_TICKETS)
-    int new_session_ticket;             /*!< use NewSessionTicket?    */
-#endif /* MBEDTLS_SSL_SESSION_TICKETS */
-#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET)
-    int extended_ms;                    /*!< use Extended Master Secret? */
-#endif
-
-#if defined(MBEDTLS_SSL_ASYNC_PRIVATE)
-    unsigned int async_in_progress : 1; /*!< an asynchronous operation is in progress */
-#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */
-
-#if defined(MBEDTLS_SSL_ASYNC_PRIVATE)
-    /** Asynchronous operation context. This field is meant for use by the
-     * asynchronous operation callbacks (mbedtls_ssl_config::f_async_sign_start,
-     * mbedtls_ssl_config::f_async_decrypt_start,
-     * mbedtls_ssl_config::f_async_resume, mbedtls_ssl_config::f_async_cancel).
-     * The library does not use it internally. */
-    void *user_async_ctx;
-#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */
-};
-
-typedef struct mbedtls_ssl_hs_buffer mbedtls_ssl_hs_buffer;
-
-/*
- * This structure contains a full set of runtime transform parameters
- * either in negotiation or active.
- */
-struct mbedtls_ssl_transform
-{
-    /*
-     * Session specific crypto layer
-     */
-    const mbedtls_ssl_ciphersuite_t *ciphersuite_info;
-                                        /*!<  Chosen cipersuite_info  */
-    unsigned int keylen;                /*!<  symmetric key length (bytes)  */
-    size_t minlen;                      /*!<  min. ciphertext length  */
-    size_t ivlen;                       /*!<  IV length               */
-    size_t fixed_ivlen;                 /*!<  Fixed part of IV (AEAD) */
-    size_t maclen;                      /*!<  MAC length              */
-
-    unsigned char iv_enc[16];           /*!<  IV (encryption)         */
-    unsigned char iv_dec[16];           /*!<  IV (decryption)         */
-
-#if defined(MBEDTLS_SSL_PROTO_SSL3)
-    /* Needed only for SSL v3.0 secret */
-    unsigned char mac_enc[20];          /*!<  SSL v3.0 secret (enc)   */
-    unsigned char mac_dec[20];          /*!<  SSL v3.0 secret (dec)   */
-#endif /* MBEDTLS_SSL_PROTO_SSL3 */
-
-    mbedtls_md_context_t md_ctx_enc;            /*!<  MAC (encryption)        */
-    mbedtls_md_context_t md_ctx_dec;            /*!<  MAC (decryption)        */
-
-    mbedtls_cipher_context_t cipher_ctx_enc;    /*!<  encryption context      */
-    mbedtls_cipher_context_t cipher_ctx_dec;    /*!<  decryption context      */
-
-    /*
-     * Session specific compression layer
-     */
-#if defined(MBEDTLS_ZLIB_SUPPORT)
-    z_stream ctx_deflate;               /*!<  compression context     */
-    z_stream ctx_inflate;               /*!<  decompression context   */
-#endif
-};
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-/*
- * List of certificate + private key pairs
- */
-struct mbedtls_ssl_key_cert
-{
-    mbedtls_x509_crt *cert;                 /*!< cert                       */
-    mbedtls_pk_context *key;                /*!< private key                */
-    mbedtls_ssl_key_cert *next;             /*!< next key/cert pair         */
-};
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-/*
- * List of handshake messages kept around for resending
- */
-struct mbedtls_ssl_flight_item
-{
-    unsigned char *p;       /*!< message, including handshake headers   */
-    size_t len;             /*!< length of p                            */
-    unsigned char type;     /*!< type of the message: handshake or CCS  */
-    mbedtls_ssl_flight_item *next;  /*!< next handshake message(s)              */
-};
-#endif /* MBEDTLS_SSL_PROTO_DTLS */
-
-#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \
-    defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED)
-
-/* Find an entry in a signature-hash set matching a given hash algorithm. */
-mbedtls_md_type_t mbedtls_ssl_sig_hash_set_find( mbedtls_ssl_sig_hash_set_t *set,
-                                                 mbedtls_pk_type_t sig_alg );
-/* Add a signature-hash-pair to a signature-hash set */
-void mbedtls_ssl_sig_hash_set_add( mbedtls_ssl_sig_hash_set_t *set,
-                                   mbedtls_pk_type_t sig_alg,
-                                   mbedtls_md_type_t md_alg );
-/* Allow exactly one hash algorithm for each signature. */
-void mbedtls_ssl_sig_hash_set_const_hash( mbedtls_ssl_sig_hash_set_t *set,
-                                          mbedtls_md_type_t md_alg );
-
-/* Setup an empty signature-hash set */
-static inline void mbedtls_ssl_sig_hash_set_init( mbedtls_ssl_sig_hash_set_t *set )
-{
-    mbedtls_ssl_sig_hash_set_const_hash( set, MBEDTLS_MD_NONE );
-}
-
-#endif /* MBEDTLS_SSL_PROTO_TLS1_2) &&
-          MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED */
-
-/**
- * \brief           Free referenced items in an SSL transform context and clear
- *                  memory
- *
- * \param transform SSL transform context
- */
-void mbedtls_ssl_transform_free( mbedtls_ssl_transform *transform );
-
-/**
- * \brief           Free referenced items in an SSL handshake context and clear
- *                  memory
- *
- * \param ssl       SSL context
- */
-void mbedtls_ssl_handshake_free( mbedtls_ssl_context *ssl );
-
-int mbedtls_ssl_handshake_client_step( mbedtls_ssl_context *ssl );
-int mbedtls_ssl_handshake_server_step( mbedtls_ssl_context *ssl );
-void mbedtls_ssl_handshake_wrapup( mbedtls_ssl_context *ssl );
-
-int mbedtls_ssl_send_fatal_handshake_failure( mbedtls_ssl_context *ssl );
-
-void mbedtls_ssl_reset_checksum( mbedtls_ssl_context *ssl );
-int mbedtls_ssl_derive_keys( mbedtls_ssl_context *ssl );
-
-int mbedtls_ssl_handle_message_type( mbedtls_ssl_context *ssl );
-int mbedtls_ssl_prepare_handshake_record( mbedtls_ssl_context *ssl );
-void mbedtls_ssl_update_handshake_status( mbedtls_ssl_context *ssl );
-
-/**
- * \brief       Update record layer
- *
- *              This function roughly separates the implementation
- *              of the logic of (D)TLS from the implementation
- *              of the secure transport.
- *
- * \param  ssl              The SSL context to use.
- * \param  update_hs_digest This indicates if the handshake digest
- *                          should be automatically updated in case
- *                          a handshake message is found.
- *
- * \return      0 or non-zero error code.
- *
- * \note        A clarification on what is called 'record layer' here
- *              is in order, as many sensible definitions are possible:
- *
- *              The record layer takes as input an untrusted underlying
- *              transport (stream or datagram) and transforms it into
- *              a serially multiplexed, secure transport, which
- *              conceptually provides the following:
- *
- *              (1) Three datagram based, content-agnostic transports
- *                  for handshake, alert and CCS messages.
- *              (2) One stream- or datagram-based transport
- *                  for application data.
- *              (3) Functionality for changing the underlying transform
- *                  securing the contents.
- *
- *              The interface to this functionality is given as follows:
- *
- *              a Updating
- *                [Currently implemented by mbedtls_ssl_read_record]
- *
- *                Check if and on which of the four 'ports' data is pending:
- *                Nothing, a controlling datagram of type (1), or application
- *                data (2). In any case data is present, internal buffers
- *                provide access to the data for the user to process it.
- *                Consumption of type (1) datagrams is done automatically
- *                on the next update, invalidating that the internal buffers
- *                for previous datagrams, while consumption of application
- *                data (2) is user-controlled.
- *
- *              b Reading of application data
- *                [Currently manual adaption of ssl->in_offt pointer]
- *
- *                As mentioned in the last paragraph, consumption of data
- *                is different from the automatic consumption of control
- *                datagrams (1) because application data is treated as a stream.
- *
- *              c Tracking availability of application data
- *                [Currently manually through decreasing ssl->in_msglen]
- *
- *                For efficiency and to retain datagram semantics for
- *                application data in case of DTLS, the record layer
- *                provides functionality for checking how much application
- *                data is still available in the internal buffer.
- *
- *              d Changing the transformation securing the communication.
- *
- *              Given an opaque implementation of the record layer in the
- *              above sense, it should be possible to implement the logic
- *              of (D)TLS on top of it without the need to know anything
- *              about the record layer's internals. This is done e.g.
- *              in all the handshake handling functions, and in the
- *              application data reading function mbedtls_ssl_read.
- *
- * \note        The above tries to give a conceptual picture of the
- *              record layer, but the current implementation deviates
- *              from it in some places. For example, our implementation of
- *              the update functionality through mbedtls_ssl_read_record
- *              discards datagrams depending on the current state, which
- *              wouldn't fall under the record layer's responsibility
- *              following the above definition.
- *
- */
-int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl,
-                             unsigned update_hs_digest );
-int mbedtls_ssl_fetch_input( mbedtls_ssl_context *ssl, size_t nb_want );
-
-int mbedtls_ssl_write_handshake_msg( mbedtls_ssl_context *ssl );
-int mbedtls_ssl_write_record( mbedtls_ssl_context *ssl, uint8_t force_flush );
-int mbedtls_ssl_flush_output( mbedtls_ssl_context *ssl );
-
-int mbedtls_ssl_parse_certificate( mbedtls_ssl_context *ssl );
-int mbedtls_ssl_write_certificate( mbedtls_ssl_context *ssl );
-
-int mbedtls_ssl_parse_change_cipher_spec( mbedtls_ssl_context *ssl );
-int mbedtls_ssl_write_change_cipher_spec( mbedtls_ssl_context *ssl );
-
-int mbedtls_ssl_parse_finished( mbedtls_ssl_context *ssl );
-int mbedtls_ssl_write_finished( mbedtls_ssl_context *ssl );
-
-void mbedtls_ssl_optimize_checksum( mbedtls_ssl_context *ssl,
-                            const mbedtls_ssl_ciphersuite_t *ciphersuite_info );
-
-#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED)
-int mbedtls_ssl_psk_derive_premaster( mbedtls_ssl_context *ssl, mbedtls_key_exchange_type_t key_ex );
-#endif
-
-#if defined(MBEDTLS_PK_C)
-unsigned char mbedtls_ssl_sig_from_pk( mbedtls_pk_context *pk );
-unsigned char mbedtls_ssl_sig_from_pk_alg( mbedtls_pk_type_t type );
-mbedtls_pk_type_t mbedtls_ssl_pk_alg_from_sig( unsigned char sig );
-#endif
-
-mbedtls_md_type_t mbedtls_ssl_md_alg_from_hash( unsigned char hash );
-unsigned char mbedtls_ssl_hash_from_md_alg( int md );
-int mbedtls_ssl_set_calc_verify_md( mbedtls_ssl_context *ssl, int md );
-
-#if defined(MBEDTLS_ECP_C)
-int mbedtls_ssl_check_curve( const mbedtls_ssl_context *ssl, mbedtls_ecp_group_id grp_id );
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED)
-int mbedtls_ssl_check_sig_hash( const mbedtls_ssl_context *ssl,
-                                mbedtls_md_type_t md );
-#endif
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-static inline mbedtls_pk_context *mbedtls_ssl_own_key( mbedtls_ssl_context *ssl )
-{
-    mbedtls_ssl_key_cert *key_cert;
-
-    if( ssl->handshake != NULL && ssl->handshake->key_cert != NULL )
-        key_cert = ssl->handshake->key_cert;
-    else
-        key_cert = ssl->conf->key_cert;
-
-    return( key_cert == NULL ? NULL : key_cert->key );
-}
-
-static inline mbedtls_x509_crt *mbedtls_ssl_own_cert( mbedtls_ssl_context *ssl )
-{
-    mbedtls_ssl_key_cert *key_cert;
-
-    if( ssl->handshake != NULL && ssl->handshake->key_cert != NULL )
-        key_cert = ssl->handshake->key_cert;
-    else
-        key_cert = ssl->conf->key_cert;
-
-    return( key_cert == NULL ? NULL : key_cert->cert );
-}
-
-/*
- * Check usage of a certificate wrt extensions:
- * keyUsage, extendedKeyUsage (later), and nSCertType (later).
- *
- * Warning: cert_endpoint is the endpoint of the cert (ie, of our peer when we
- * check a cert we received from them)!
- *
- * Return 0 if everything is OK, -1 if not.
- */
-int mbedtls_ssl_check_cert_usage( const mbedtls_x509_crt *cert,
-                          const mbedtls_ssl_ciphersuite_t *ciphersuite,
-                          int cert_endpoint,
-                          uint32_t *flags );
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-void mbedtls_ssl_write_version( int major, int minor, int transport,
-                        unsigned char ver[2] );
-void mbedtls_ssl_read_version( int *major, int *minor, int transport,
-                       const unsigned char ver[2] );
-
-static inline size_t mbedtls_ssl_hdr_len( const mbedtls_ssl_context *ssl )
-{
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-    if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM )
-        return( 13 );
-#else
-    ((void) ssl);
-#endif
-    return( 5 );
-}
-
-static inline size_t mbedtls_ssl_hs_hdr_len( const mbedtls_ssl_context *ssl )
-{
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-    if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM )
-        return( 12 );
-#else
-    ((void) ssl);
-#endif
-    return( 4 );
-}
-
-#if defined(MBEDTLS_SSL_PROTO_DTLS)
-void mbedtls_ssl_send_flight_completed( mbedtls_ssl_context *ssl );
-void mbedtls_ssl_recv_flight_completed( mbedtls_ssl_context *ssl );
-int mbedtls_ssl_resend( mbedtls_ssl_context *ssl );
-int mbedtls_ssl_flight_transmit( mbedtls_ssl_context *ssl );
-#endif
-
-/* Visible for testing purposes only */
-#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY)
-int mbedtls_ssl_dtls_replay_check( mbedtls_ssl_context *ssl );
-void mbedtls_ssl_dtls_replay_update( mbedtls_ssl_context *ssl );
-#endif
-
-/* constant-time buffer comparison */
-static inline int mbedtls_ssl_safer_memcmp( const void *a, const void *b, size_t n )
-{
-    size_t i;
-    volatile const unsigned char *A = (volatile const unsigned char *) a;
-    volatile const unsigned char *B = (volatile const unsigned char *) b;
-    volatile unsigned char diff = 0;
-
-    for( i = 0; i < n; i++ )
-    {
-        /* Read volatile data in order before computing diff.
-         * This avoids IAR compiler warning:
-         * 'the order of volatile accesses is undefined ..' */
-        unsigned char x = A[i], y = B[i];
-        diff |= x ^ y;
-    }
-
-    return( diff );
-}
-
-#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) || \
-    defined(MBEDTLS_SSL_PROTO_TLS1_1)
-int mbedtls_ssl_get_key_exchange_md_ssl_tls( mbedtls_ssl_context *ssl,
-                                        unsigned char *output,
-                                        unsigned char *data, size_t data_len );
-#endif /* MBEDTLS_SSL_PROTO_SSL3 || MBEDTLS_SSL_PROTO_TLS1 || \
-          MBEDTLS_SSL_PROTO_TLS1_1 */
-
-#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) || \
-    defined(MBEDTLS_SSL_PROTO_TLS1_2)
-int mbedtls_ssl_get_key_exchange_md_tls1_2( mbedtls_ssl_context *ssl,
-                                            unsigned char *hash, size_t *hashlen,
-                                            unsigned char *data, size_t data_len,
-                                            mbedtls_md_type_t md_alg );
-#endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 || \
-          MBEDTLS_SSL_PROTO_TLS1_2 */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ssl_internal.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h b/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h
deleted file mode 100644
index ac3be043374..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/ssl_ticket.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
- * \file ssl_ticket.h
- *
- * \brief TLS server ticket callbacks implementation
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SSL_TICKET_H
-#define MBEDTLS_SSL_TICKET_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-/*
- * This implementation of the session ticket callbacks includes key
- * management, rotating the keys periodically in order to preserve forward
- * secrecy, when MBEDTLS_HAVE_TIME is defined.
- */
-
-#include "ssl.h"
-#include "cipher.h"
-
-#if defined(MBEDTLS_THREADING_C)
-#include "threading.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief   Information for session ticket protection
- */
-typedef struct mbedtls_ssl_ticket_key
-{
-    unsigned char name[4];          /*!< random key identifier              */
-    uint32_t generation_time;       /*!< key generation timestamp (seconds) */
-    mbedtls_cipher_context_t ctx;   /*!< context for auth enc/decryption    */
-}
-mbedtls_ssl_ticket_key;
-
-/**
- * \brief   Context for session ticket handling functions
- */
-typedef struct mbedtls_ssl_ticket_context
-{
-    mbedtls_ssl_ticket_key keys[2]; /*!< ticket protection keys             */
-    unsigned char active;           /*!< index of the currently active key  */
-
-    uint32_t ticket_lifetime;       /*!< lifetime of tickets in seconds     */
-
-    /** Callback for getting (pseudo-)random numbers                        */
-    int  (*f_rng)(void *, unsigned char *, size_t);
-    void *p_rng;                    /*!< context for the RNG function       */
-
-#if defined(MBEDTLS_THREADING_C)
-    mbedtls_threading_mutex_t mutex;
-#endif
-}
-mbedtls_ssl_ticket_context;
-
-/**
- * \brief           Initialize a ticket context.
- *                  (Just make it ready for mbedtls_ssl_ticket_setup()
- *                  or mbedtls_ssl_ticket_free().)
- *
- * \param ctx       Context to be initialized
- */
-void mbedtls_ssl_ticket_init( mbedtls_ssl_ticket_context *ctx );
-
-/**
- * \brief           Prepare context to be actually used
- *
- * \param ctx       Context to be set up
- * \param f_rng     RNG callback function
- * \param p_rng     RNG callback context
- * \param cipher    AEAD cipher to use for ticket protection.
- *                  Recommended value: MBEDTLS_CIPHER_AES_256_GCM.
- * \param lifetime  Tickets lifetime in seconds
- *                  Recommended value: 86400 (one day).
- *
- * \note            It is highly recommended to select a cipher that is at
- *                  least as strong as the the strongest ciphersuite
- *                  supported. Usually that means a 256-bit key.
- *
- * \note            The lifetime of the keys is twice the lifetime of tickets.
- *                  It is recommended to pick a reasonnable lifetime so as not
- *                  to negate the benefits of forward secrecy.
- *
- * \return          0 if successful,
- *                  or a specific MBEDTLS_ERR_XXX error code
- */
-int mbedtls_ssl_ticket_setup( mbedtls_ssl_ticket_context *ctx,
-    int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
-    mbedtls_cipher_type_t cipher,
-    uint32_t lifetime );
-
-/**
- * \brief           Implementation of the ticket write callback
- *
- * \note            See \c mbedtls_ssl_ticket_write_t for description
- */
-mbedtls_ssl_ticket_write_t mbedtls_ssl_ticket_write;
-
-/**
- * \brief           Implementation of the ticket parse callback
- *
- * \note            See \c mbedtls_ssl_ticket_parse_t for description
- */
-mbedtls_ssl_ticket_parse_t mbedtls_ssl_ticket_parse;
-
-/**
- * \brief           Free a context's content and zeroize it.
- *
- * \param ctx       Context to be cleaned up
- */
-void mbedtls_ssl_ticket_free( mbedtls_ssl_ticket_context *ctx );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ssl_ticket.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/threading.h b/tools/sdk/include/mbedtls/mbedtls/threading.h
deleted file mode 100644
index b6ec4df8e95..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/threading.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/**
- * \file threading.h
- *
- * \brief Threading abstraction layer
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_THREADING_H
-#define MBEDTLS_THREADING_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stdlib.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* MBEDTLS_ERR_THREADING_FEATURE_UNAVAILABLE is deprecated and should not be
- * used. */
-#define MBEDTLS_ERR_THREADING_FEATURE_UNAVAILABLE         -0x001A  /**< The selected feature is not available. */
-
-#define MBEDTLS_ERR_THREADING_BAD_INPUT_DATA              -0x001C  /**< Bad input parameters to function. */
-#define MBEDTLS_ERR_THREADING_MUTEX_ERROR                 -0x001E  /**< Locking / unlocking / free failed with error code. */
-
-#if defined(MBEDTLS_THREADING_PTHREAD)
-#include <pthread.h>
-typedef struct mbedtls_threading_mutex_t
-{
-    pthread_mutex_t mutex;
-    char is_valid;
-} mbedtls_threading_mutex_t;
-#endif
-
-#if defined(MBEDTLS_THREADING_ALT)
-/* You should define the mbedtls_threading_mutex_t type in your header */
-#include "threading_alt.h"
-
-/**
- * \brief           Set your alternate threading implementation function
- *                  pointers and initialize global mutexes. If used, this
- *                  function must be called once in the main thread before any
- *                  other mbed TLS function is called, and
- *                  mbedtls_threading_free_alt() must be called once in the main
- *                  thread after all other mbed TLS functions.
- *
- * \note            mutex_init() and mutex_free() don't return a status code.
- *                  If mutex_init() fails, it should leave its argument (the
- *                  mutex) in a state such that mutex_lock() will fail when
- *                  called with this argument.
- *
- * \param mutex_init    the init function implementation
- * \param mutex_free    the free function implementation
- * \param mutex_lock    the lock function implementation
- * \param mutex_unlock  the unlock function implementation
- */
-void mbedtls_threading_set_alt( void (*mutex_init)( mbedtls_threading_mutex_t * ),
-                       void (*mutex_free)( mbedtls_threading_mutex_t * ),
-                       int (*mutex_lock)( mbedtls_threading_mutex_t * ),
-                       int (*mutex_unlock)( mbedtls_threading_mutex_t * ) );
-
-/**
- * \brief               Free global mutexes.
- */
-void mbedtls_threading_free_alt( void );
-#endif /* MBEDTLS_THREADING_ALT */
-
-#if defined(MBEDTLS_THREADING_C)
-/*
- * The function pointers for mutex_init, mutex_free, mutex_ and mutex_unlock
- *
- * All these functions are expected to work or the result will be undefined.
- */
-extern void (*mbedtls_mutex_init)( mbedtls_threading_mutex_t *mutex );
-extern void (*mbedtls_mutex_free)( mbedtls_threading_mutex_t *mutex );
-extern int (*mbedtls_mutex_lock)( mbedtls_threading_mutex_t *mutex );
-extern int (*mbedtls_mutex_unlock)( mbedtls_threading_mutex_t *mutex );
-
-/*
- * Global mutexes
- */
-#if defined(MBEDTLS_FS_IO)
-extern mbedtls_threading_mutex_t mbedtls_threading_readdir_mutex;
-#endif
-
-#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_PLATFORM_GMTIME_R_ALT)
-/* This mutex may or may not be used in the default definition of
- * mbedtls_platform_gmtime_r(), but in order to determine that,
- * we need to check POSIX features, hence modify _POSIX_C_SOURCE.
- * With the current approach, this declaration is orphaned, lacking
- * an accompanying definition, in case mbedtls_platform_gmtime_r()
- * doesn't need it, but that's not a problem. */
-extern mbedtls_threading_mutex_t mbedtls_threading_gmtime_mutex;
-#endif /* MBEDTLS_HAVE_TIME_DATE && !MBEDTLS_PLATFORM_GMTIME_R_ALT */
-
-#endif /* MBEDTLS_THREADING_C */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* threading.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/timing.h b/tools/sdk/include/mbedtls/mbedtls/timing.h
deleted file mode 100644
index 149ccfb6660..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/timing.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/**
- * \file timing.h
- *
- * \brief Portable interface to timeouts and to the CPU cycle counter
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_TIMING_H
-#define MBEDTLS_TIMING_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_TIMING_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          timer structure
- */
-struct mbedtls_timing_hr_time
-{
-    unsigned char opaque[32];
-};
-
-/**
- * \brief          Context for mbedtls_timing_set/get_delay()
- */
-typedef struct mbedtls_timing_delay_context
-{
-    struct mbedtls_timing_hr_time   timer;
-    uint32_t                        int_ms;
-    uint32_t                        fin_ms;
-} mbedtls_timing_delay_context;
-
-#else  /* MBEDTLS_TIMING_ALT */
-#include "timing_alt.h"
-#endif /* MBEDTLS_TIMING_ALT */
-
-extern volatile int mbedtls_timing_alarmed;
-
-/**
- * \brief          Return the CPU cycle counter value
- *
- * \warning        This is only a best effort! Do not rely on this!
- *                 In particular, it is known to be unreliable on virtual
- *                 machines.
- *
- * \note           This value starts at an unspecified origin and
- *                 may wrap around.
- */
-unsigned long mbedtls_timing_hardclock( void );
-
-/**
- * \brief          Return the elapsed time in milliseconds
- *
- * \param val      points to a timer structure
- * \param reset    If 0, query the elapsed time. Otherwise (re)start the timer.
- *
- * \return         Elapsed time since the previous reset in ms. When
- *                 restarting, this is always 0.
- *
- * \note           To initialize a timer, call this function with reset=1.
- *
- *                 Determining the elapsed time and resetting the timer is not
- *                 atomic on all platforms, so after the sequence
- *                 `{ get_timer(1); ...; time1 = get_timer(1); ...; time2 =
- *                 get_timer(0) }` the value time1+time2 is only approximately
- *                 the delay since the first reset.
- */
-unsigned long mbedtls_timing_get_timer( struct mbedtls_timing_hr_time *val, int reset );
-
-/**
- * \brief          Setup an alarm clock
- *
- * \param seconds  delay before the "mbedtls_timing_alarmed" flag is set
- *                 (must be >=0)
- *
- * \warning        Only one alarm at a time  is supported. In a threaded
- *                 context, this means one for the whole process, not one per
- *                 thread.
- */
-void mbedtls_set_alarm( int seconds );
-
-/**
- * \brief          Set a pair of delays to watch
- *                 (See \c mbedtls_timing_get_delay().)
- *
- * \param data     Pointer to timing data.
- *                 Must point to a valid \c mbedtls_timing_delay_context struct.
- * \param int_ms   First (intermediate) delay in milliseconds.
- *                 The effect if int_ms > fin_ms is unspecified.
- * \param fin_ms   Second (final) delay in milliseconds.
- *                 Pass 0 to cancel the current delay.
- *
- * \note           To set a single delay, either use \c mbedtls_timing_set_timer
- *                 directly or use this function with int_ms == fin_ms.
- */
-void mbedtls_timing_set_delay( void *data, uint32_t int_ms, uint32_t fin_ms );
-
-/**
- * \brief          Get the status of delays
- *                 (Memory helper: number of delays passed.)
- *
- * \param data     Pointer to timing data
- *                 Must point to a valid \c mbedtls_timing_delay_context struct.
- *
- * \return         -1 if cancelled (fin_ms = 0),
- *                  0 if none of the delays are passed,
- *                  1 if only the intermediate delay is passed,
- *                  2 if the final delay is passed.
- */
-int mbedtls_timing_get_delay( void *data );
-
-#if defined(MBEDTLS_SELF_TEST)
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if a test failed
- */
-int mbedtls_timing_self_test( int verbose );
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* timing.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/version.h b/tools/sdk/include/mbedtls/mbedtls/version.h
deleted file mode 100644
index 2bff31d51f1..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/version.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- * \file version.h
- *
- * \brief Run-time version information
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-/*
- * This set of compile-time defines and run-time variables can be used to
- * determine the version number of the mbed TLS library used.
- */
-#ifndef MBEDTLS_VERSION_H
-#define MBEDTLS_VERSION_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-/**
- * The version number x.y.z is split into three parts.
- * Major, Minor, Patchlevel
- */
-#define MBEDTLS_VERSION_MAJOR  2
-#define MBEDTLS_VERSION_MINOR  16
-#define MBEDTLS_VERSION_PATCH  7
-
-/**
- * The single version number has the following structure:
- *    MMNNPP00
- *    Major version | Minor version | Patch version
- */
-#define MBEDTLS_VERSION_NUMBER         0x02100700
-#define MBEDTLS_VERSION_STRING         "2.16.7"
-#define MBEDTLS_VERSION_STRING_FULL    "mbed TLS 2.16.7"
-
-#if defined(MBEDTLS_VERSION_C)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Get the version number.
- *
- * \return          The constructed version number in the format
- *                  MMNNPP00 (Major, Minor, Patch).
- */
-unsigned int mbedtls_version_get_number( void );
-
-/**
- * Get the version string ("x.y.z").
- *
- * \param string    The string that will receive the value.
- *                  (Should be at least 9 bytes in size)
- */
-void mbedtls_version_get_string( char *string );
-
-/**
- * Get the full version string ("mbed TLS x.y.z").
- *
- * \param string    The string that will receive the value. The mbed TLS version
- *                  string will use 18 bytes AT MOST including a terminating
- *                  null byte.
- *                  (So the buffer should be at least 18 bytes to receive this
- *                  version string).
- */
-void mbedtls_version_get_string_full( char *string );
-
-/**
- * \brief           Check if support for a feature was compiled into this
- *                  mbed TLS binary. This allows you to see at runtime if the
- *                  library was for instance compiled with or without
- *                  Multi-threading support.
- *
- * \note            only checks against defines in the sections "System
- *                  support", "mbed TLS modules" and "mbed TLS feature
- *                  support" in config.h
- *
- * \param feature   The string for the define to check (e.g. "MBEDTLS_AES_C")
- *
- * \return          0 if the feature is present,
- *                  -1 if the feature is not present and
- *                  -2 if support for feature checking as a whole was not
- *                  compiled in.
- */
-int mbedtls_version_check_feature( const char *feature );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_VERSION_C */
-
-#endif /* version.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/x509.h b/tools/sdk/include/mbedtls/mbedtls/x509.h
deleted file mode 100644
index e9f2fc60245..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/x509.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/**
- * \file x509.h
- *
- * \brief X.509 generic defines and structures
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_X509_H
-#define MBEDTLS_X509_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "asn1.h"
-#include "pk.h"
-
-#if defined(MBEDTLS_RSA_C)
-#include "rsa.h"
-#endif
-
-/**
- * \addtogroup x509_module
- * \{
- */
-
-#if !defined(MBEDTLS_X509_MAX_INTERMEDIATE_CA)
-/**
- * Maximum number of intermediate CAs in a verification chain.
- * That is, maximum length of the chain, excluding the end-entity certificate
- * and the trusted root certificate.
- *
- * Set this to a low value to prevent an adversary from making you waste
- * resources verifying an overlong certificate chain.
- */
-#define MBEDTLS_X509_MAX_INTERMEDIATE_CA   8
-#endif
-
-/**
- * \name X509 Error codes
- * \{
- */
-#define MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE              -0x2080  /**< Unavailable feature, e.g. RSA hashing/encryption combination. */
-#define MBEDTLS_ERR_X509_UNKNOWN_OID                      -0x2100  /**< Requested OID is unknown. */
-#define MBEDTLS_ERR_X509_INVALID_FORMAT                   -0x2180  /**< The CRT/CRL/CSR format is invalid, e.g. different type expected. */
-#define MBEDTLS_ERR_X509_INVALID_VERSION                  -0x2200  /**< The CRT/CRL/CSR version element is invalid. */
-#define MBEDTLS_ERR_X509_INVALID_SERIAL                   -0x2280  /**< The serial tag or value is invalid. */
-#define MBEDTLS_ERR_X509_INVALID_ALG                      -0x2300  /**< The algorithm tag or value is invalid. */
-#define MBEDTLS_ERR_X509_INVALID_NAME                     -0x2380  /**< The name tag or value is invalid. */
-#define MBEDTLS_ERR_X509_INVALID_DATE                     -0x2400  /**< The date tag or value is invalid. */
-#define MBEDTLS_ERR_X509_INVALID_SIGNATURE                -0x2480  /**< The signature tag or value invalid. */
-#define MBEDTLS_ERR_X509_INVALID_EXTENSIONS               -0x2500  /**< The extension tag or value is invalid. */
-#define MBEDTLS_ERR_X509_UNKNOWN_VERSION                  -0x2580  /**< CRT/CRL/CSR has an unsupported version number. */
-#define MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG                  -0x2600  /**< Signature algorithm (oid) is unsupported. */
-#define MBEDTLS_ERR_X509_SIG_MISMATCH                     -0x2680  /**< Signature algorithms do not match. (see \c ::mbedtls_x509_crt sig_oid) */
-#define MBEDTLS_ERR_X509_CERT_VERIFY_FAILED               -0x2700  /**< Certificate verification failed, e.g. CRL, CA or signature check failed. */
-#define MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT              -0x2780  /**< Format not recognized as DER or PEM. */
-#define MBEDTLS_ERR_X509_BAD_INPUT_DATA                   -0x2800  /**< Input invalid. */
-#define MBEDTLS_ERR_X509_ALLOC_FAILED                     -0x2880  /**< Allocation of memory failed. */
-#define MBEDTLS_ERR_X509_FILE_IO_ERROR                    -0x2900  /**< Read/write of file failed. */
-#define MBEDTLS_ERR_X509_BUFFER_TOO_SMALL                 -0x2980  /**< Destination buffer is too small. */
-#define MBEDTLS_ERR_X509_FATAL_ERROR                      -0x3000  /**< A fatal error occurred, eg the chain is too long or the vrfy callback failed. */
-/* \} name */
-
-/**
- * \name X509 Verify codes
- * \{
- */
-/* Reminder: update x509_crt_verify_strings[] in library/x509_crt.c */
-#define MBEDTLS_X509_BADCERT_EXPIRED             0x01  /**< The certificate validity has expired. */
-#define MBEDTLS_X509_BADCERT_REVOKED             0x02  /**< The certificate has been revoked (is on a CRL). */
-#define MBEDTLS_X509_BADCERT_CN_MISMATCH         0x04  /**< The certificate Common Name (CN) does not match with the expected CN. */
-#define MBEDTLS_X509_BADCERT_NOT_TRUSTED         0x08  /**< The certificate is not correctly signed by the trusted CA. */
-#define MBEDTLS_X509_BADCRL_NOT_TRUSTED          0x10  /**< The CRL is not correctly signed by the trusted CA. */
-#define MBEDTLS_X509_BADCRL_EXPIRED              0x20  /**< The CRL is expired. */
-#define MBEDTLS_X509_BADCERT_MISSING             0x40  /**< Certificate was missing. */
-#define MBEDTLS_X509_BADCERT_SKIP_VERIFY         0x80  /**< Certificate verification was skipped. */
-#define MBEDTLS_X509_BADCERT_OTHER             0x0100  /**< Other reason (can be used by verify callback) */
-#define MBEDTLS_X509_BADCERT_FUTURE            0x0200  /**< The certificate validity starts in the future. */
-#define MBEDTLS_X509_BADCRL_FUTURE             0x0400  /**< The CRL is from the future */
-#define MBEDTLS_X509_BADCERT_KEY_USAGE         0x0800  /**< Usage does not match the keyUsage extension. */
-#define MBEDTLS_X509_BADCERT_EXT_KEY_USAGE     0x1000  /**< Usage does not match the extendedKeyUsage extension. */
-#define MBEDTLS_X509_BADCERT_NS_CERT_TYPE      0x2000  /**< Usage does not match the nsCertType extension. */
-#define MBEDTLS_X509_BADCERT_BAD_MD            0x4000  /**< The certificate is signed with an unacceptable hash. */
-#define MBEDTLS_X509_BADCERT_BAD_PK            0x8000  /**< The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA). */
-#define MBEDTLS_X509_BADCERT_BAD_KEY         0x010000  /**< The certificate is signed with an unacceptable key (eg bad curve, RSA too short). */
-#define MBEDTLS_X509_BADCRL_BAD_MD           0x020000  /**< The CRL is signed with an unacceptable hash. */
-#define MBEDTLS_X509_BADCRL_BAD_PK           0x040000  /**< The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA). */
-#define MBEDTLS_X509_BADCRL_BAD_KEY          0x080000  /**< The CRL is signed with an unacceptable key (eg bad curve, RSA too short). */
-
-/* \} name */
-/* \} addtogroup x509_module */
-
-/*
- * X.509 v3 Key Usage Extension flags
- * Reminder: update x509_info_key_usage() when adding new flags.
- */
-#define MBEDTLS_X509_KU_DIGITAL_SIGNATURE            (0x80)  /* bit 0 */
-#define MBEDTLS_X509_KU_NON_REPUDIATION              (0x40)  /* bit 1 */
-#define MBEDTLS_X509_KU_KEY_ENCIPHERMENT             (0x20)  /* bit 2 */
-#define MBEDTLS_X509_KU_DATA_ENCIPHERMENT            (0x10)  /* bit 3 */
-#define MBEDTLS_X509_KU_KEY_AGREEMENT                (0x08)  /* bit 4 */
-#define MBEDTLS_X509_KU_KEY_CERT_SIGN                (0x04)  /* bit 5 */
-#define MBEDTLS_X509_KU_CRL_SIGN                     (0x02)  /* bit 6 */
-#define MBEDTLS_X509_KU_ENCIPHER_ONLY                (0x01)  /* bit 7 */
-#define MBEDTLS_X509_KU_DECIPHER_ONLY              (0x8000)  /* bit 8 */
-
-/*
- * Netscape certificate types
- * (http://www.mozilla.org/projects/security/pki/nss/tech-notes/tn3.html)
- */
-
-#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT         (0x80)  /* bit 0 */
-#define MBEDTLS_X509_NS_CERT_TYPE_SSL_SERVER         (0x40)  /* bit 1 */
-#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL              (0x20)  /* bit 2 */
-#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING     (0x10)  /* bit 3 */
-#define MBEDTLS_X509_NS_CERT_TYPE_RESERVED           (0x08)  /* bit 4 */
-#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CA             (0x04)  /* bit 5 */
-#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL_CA           (0x02)  /* bit 6 */
-#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING_CA  (0x01)  /* bit 7 */
-
-/*
- * X.509 extension types
- *
- * Comments refer to the status for using certificates. Status can be
- * different for writing certificates or reading CRLs or CSRs.
- */
-#define MBEDTLS_X509_EXT_AUTHORITY_KEY_IDENTIFIER    (1 << 0)
-#define MBEDTLS_X509_EXT_SUBJECT_KEY_IDENTIFIER      (1 << 1)
-#define MBEDTLS_X509_EXT_KEY_USAGE                   (1 << 2)
-#define MBEDTLS_X509_EXT_CERTIFICATE_POLICIES        (1 << 3)
-#define MBEDTLS_X509_EXT_POLICY_MAPPINGS             (1 << 4)
-#define MBEDTLS_X509_EXT_SUBJECT_ALT_NAME            (1 << 5)    /* Supported (DNS) */
-#define MBEDTLS_X509_EXT_ISSUER_ALT_NAME             (1 << 6)
-#define MBEDTLS_X509_EXT_SUBJECT_DIRECTORY_ATTRS     (1 << 7)
-#define MBEDTLS_X509_EXT_BASIC_CONSTRAINTS           (1 << 8)    /* Supported */
-#define MBEDTLS_X509_EXT_NAME_CONSTRAINTS            (1 << 9)
-#define MBEDTLS_X509_EXT_POLICY_CONSTRAINTS          (1 << 10)
-#define MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE          (1 << 11)
-#define MBEDTLS_X509_EXT_CRL_DISTRIBUTION_POINTS     (1 << 12)
-#define MBEDTLS_X509_EXT_INIHIBIT_ANYPOLICY          (1 << 13)
-#define MBEDTLS_X509_EXT_FRESHEST_CRL                (1 << 14)
-
-#define MBEDTLS_X509_EXT_NS_CERT_TYPE                (1 << 16)
-
-/*
- * Storage format identifiers
- * Recognized formats: PEM and DER
- */
-#define MBEDTLS_X509_FORMAT_DER                 1
-#define MBEDTLS_X509_FORMAT_PEM                 2
-
-#define MBEDTLS_X509_MAX_DN_NAME_SIZE         256 /**< Maximum value size of a DN entry */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \addtogroup x509_module
- * \{ */
-
-/**
- * \name Structures for parsing X.509 certificates, CRLs and CSRs
- * \{
- */
-
-/**
- * Type-length-value structure that allows for ASN1 using DER.
- */
-typedef mbedtls_asn1_buf mbedtls_x509_buf;
-
-/**
- * Container for ASN1 bit strings.
- */
-typedef mbedtls_asn1_bitstring mbedtls_x509_bitstring;
-
-/**
- * Container for ASN1 named information objects.
- * It allows for Relative Distinguished Names (e.g. cn=localhost,ou=code,etc.).
- */
-typedef mbedtls_asn1_named_data mbedtls_x509_name;
-
-/**
- * Container for a sequence of ASN.1 items
- */
-typedef mbedtls_asn1_sequence mbedtls_x509_sequence;
-
-/** Container for date and time (precision in seconds). */
-typedef struct mbedtls_x509_time
-{
-    int year, mon, day;         /**< Date. */
-    int hour, min, sec;         /**< Time. */
-}
-mbedtls_x509_time;
-
-/** \} name Structures for parsing X.509 certificates, CRLs and CSRs */
-/** \} addtogroup x509_module */
-
-/**
- * \brief          Store the certificate DN in printable form into buf;
- *                 no more than size characters will be written.
- *
- * \param buf      Buffer to write to
- * \param size     Maximum size of buffer
- * \param dn       The X509 name to represent
- *
- * \return         The length of the string written (not including the
- *                 terminated nul byte), or a negative error code.
- */
-int mbedtls_x509_dn_gets( char *buf, size_t size, const mbedtls_x509_name *dn );
-
-/**
- * \brief          Store the certificate serial in printable form into buf;
- *                 no more than size characters will be written.
- *
- * \param buf      Buffer to write to
- * \param size     Maximum size of buffer
- * \param serial   The X509 serial to represent
- *
- * \return         The length of the string written (not including the
- *                 terminated nul byte), or a negative error code.
- */
-int mbedtls_x509_serial_gets( char *buf, size_t size, const mbedtls_x509_buf *serial );
-
-/**
- * \brief          Check a given mbedtls_x509_time against the system time
- *                 and tell if it's in the past.
- *
- * \note           Intended usage is "if( is_past( valid_to ) ) ERROR".
- *                 Hence the return value of 1 if on internal errors.
- *
- * \param to       mbedtls_x509_time to check
- *
- * \return         1 if the given time is in the past or an error occurred,
- *                 0 otherwise.
- */
-int mbedtls_x509_time_is_past( const mbedtls_x509_time *to );
-
-/**
- * \brief          Check a given mbedtls_x509_time against the system time
- *                 and tell if it's in the future.
- *
- * \note           Intended usage is "if( is_future( valid_from ) ) ERROR".
- *                 Hence the return value of 1 if on internal errors.
- *
- * \param from     mbedtls_x509_time to check
- *
- * \return         1 if the given time is in the future or an error occurred,
- *                 0 otherwise.
- */
-int mbedtls_x509_time_is_future( const mbedtls_x509_time *from );
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- */
-int mbedtls_x509_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-/*
- * Internal module functions. You probably do not want to use these unless you
- * know you do.
- */
-int mbedtls_x509_get_name( unsigned char **p, const unsigned char *end,
-                   mbedtls_x509_name *cur );
-int mbedtls_x509_get_alg_null( unsigned char **p, const unsigned char *end,
-                       mbedtls_x509_buf *alg );
-int mbedtls_x509_get_alg( unsigned char **p, const unsigned char *end,
-                  mbedtls_x509_buf *alg, mbedtls_x509_buf *params );
-#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT)
-int mbedtls_x509_get_rsassa_pss_params( const mbedtls_x509_buf *params,
-                                mbedtls_md_type_t *md_alg, mbedtls_md_type_t *mgf_md,
-                                int *salt_len );
-#endif
-int mbedtls_x509_get_sig( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *sig );
-int mbedtls_x509_get_sig_alg( const mbedtls_x509_buf *sig_oid, const mbedtls_x509_buf *sig_params,
-                      mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg,
-                      void **sig_opts );
-int mbedtls_x509_get_time( unsigned char **p, const unsigned char *end,
-                   mbedtls_x509_time *t );
-int mbedtls_x509_get_serial( unsigned char **p, const unsigned char *end,
-                     mbedtls_x509_buf *serial );
-int mbedtls_x509_get_ext( unsigned char **p, const unsigned char *end,
-                  mbedtls_x509_buf *ext, int tag );
-int mbedtls_x509_sig_alg_gets( char *buf, size_t size, const mbedtls_x509_buf *sig_oid,
-                       mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg,
-                       const void *sig_opts );
-int mbedtls_x509_key_size_helper( char *buf, size_t buf_size, const char *name );
-int mbedtls_x509_string_to_names( mbedtls_asn1_named_data **head, const char *name );
-int mbedtls_x509_set_extension( mbedtls_asn1_named_data **head, const char *oid, size_t oid_len,
-                        int critical, const unsigned char *val,
-                        size_t val_len );
-int mbedtls_x509_write_extensions( unsigned char **p, unsigned char *start,
-                           mbedtls_asn1_named_data *first );
-int mbedtls_x509_write_names( unsigned char **p, unsigned char *start,
-                      mbedtls_asn1_named_data *first );
-int mbedtls_x509_write_sig( unsigned char **p, unsigned char *start,
-                    const char *oid, size_t oid_len,
-                    unsigned char *sig, size_t size );
-
-#define MBEDTLS_X509_SAFE_SNPRINTF                          \
-    do {                                                    \
-        if( ret < 0 || (size_t) ret >= n )                  \
-            return( MBEDTLS_ERR_X509_BUFFER_TOO_SMALL );    \
-                                                            \
-        n -= (size_t) ret;                                  \
-        p += (size_t) ret;                                  \
-    } while( 0 )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* x509.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/x509_crl.h b/tools/sdk/include/mbedtls/mbedtls/x509_crl.h
deleted file mode 100644
index 0e37f65e8f0..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/x509_crl.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/**
- * \file x509_crl.h
- *
- * \brief X.509 certificate revocation list parsing
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_X509_CRL_H
-#define MBEDTLS_X509_CRL_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "x509.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \addtogroup x509_module
- * \{ */
-
-/**
- * \name Structures and functions for parsing CRLs
- * \{
- */
-
-/**
- * Certificate revocation list entry.
- * Contains the CA-specific serial numbers and revocation dates.
- */
-typedef struct mbedtls_x509_crl_entry
-{
-    mbedtls_x509_buf raw;
-
-    mbedtls_x509_buf serial;
-
-    mbedtls_x509_time revocation_date;
-
-    mbedtls_x509_buf entry_ext;
-
-    struct mbedtls_x509_crl_entry *next;
-}
-mbedtls_x509_crl_entry;
-
-/**
- * Certificate revocation list structure.
- * Every CRL may have multiple entries.
- */
-typedef struct mbedtls_x509_crl
-{
-    mbedtls_x509_buf raw;           /**< The raw certificate data (DER). */
-    mbedtls_x509_buf tbs;           /**< The raw certificate body (DER). The part that is To Be Signed. */
-
-    int version;            /**< CRL version (1=v1, 2=v2) */
-    mbedtls_x509_buf sig_oid;       /**< CRL signature type identifier */
-
-    mbedtls_x509_buf issuer_raw;    /**< The raw issuer data (DER). */
-
-    mbedtls_x509_name issuer;       /**< The parsed issuer data (named information object). */
-
-    mbedtls_x509_time this_update;
-    mbedtls_x509_time next_update;
-
-    mbedtls_x509_crl_entry entry;   /**< The CRL entries containing the certificate revocation times for this CA. */
-
-    mbedtls_x509_buf crl_ext;
-
-    mbedtls_x509_buf sig_oid2;
-    mbedtls_x509_buf sig;
-    mbedtls_md_type_t sig_md;           /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */
-    mbedtls_pk_type_t sig_pk;           /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */
-    void *sig_opts;             /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */
-
-    struct mbedtls_x509_crl *next;
-}
-mbedtls_x509_crl;
-
-/**
- * \brief          Parse a DER-encoded CRL and append it to the chained list
- *
- * \param chain    points to the start of the chain
- * \param buf      buffer holding the CRL data in DER format
- * \param buflen   size of the buffer
- *                 (including the terminating null byte for PEM data)
- *
- * \return         0 if successful, or a specific X509 or PEM error code
- */
-int mbedtls_x509_crl_parse_der( mbedtls_x509_crl *chain,
-                        const unsigned char *buf, size_t buflen );
-/**
- * \brief          Parse one or more CRLs and append them to the chained list
- *
- * \note           Multiple CRLs are accepted only if using PEM format
- *
- * \param chain    points to the start of the chain
- * \param buf      buffer holding the CRL data in PEM or DER format
- * \param buflen   size of the buffer
- *                 (including the terminating null byte for PEM data)
- *
- * \return         0 if successful, or a specific X509 or PEM error code
- */
-int mbedtls_x509_crl_parse( mbedtls_x509_crl *chain, const unsigned char *buf, size_t buflen );
-
-#if defined(MBEDTLS_FS_IO)
-/**
- * \brief          Load one or more CRLs and append them to the chained list
- *
- * \note           Multiple CRLs are accepted only if using PEM format
- *
- * \param chain    points to the start of the chain
- * \param path     filename to read the CRLs from (in PEM or DER encoding)
- *
- * \return         0 if successful, or a specific X509 or PEM error code
- */
-int mbedtls_x509_crl_parse_file( mbedtls_x509_crl *chain, const char *path );
-#endif /* MBEDTLS_FS_IO */
-
-/**
- * \brief          Returns an informational string about the CRL.
- *
- * \param buf      Buffer to write to
- * \param size     Maximum size of buffer
- * \param prefix   A line prefix
- * \param crl      The X509 CRL to represent
- *
- * \return         The length of the string written (not including the
- *                 terminated nul byte), or a negative error code.
- */
-int mbedtls_x509_crl_info( char *buf, size_t size, const char *prefix,
-                   const mbedtls_x509_crl *crl );
-
-/**
- * \brief          Initialize a CRL (chain)
- *
- * \param crl      CRL chain to initialize
- */
-void mbedtls_x509_crl_init( mbedtls_x509_crl *crl );
-
-/**
- * \brief          Unallocate all CRL data
- *
- * \param crl      CRL chain to free
- */
-void mbedtls_x509_crl_free( mbedtls_x509_crl *crl );
-
-/* \} name */
-/* \} addtogroup x509_module */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_x509_crl.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/x509_crt.h b/tools/sdk/include/mbedtls/mbedtls/x509_crt.h
deleted file mode 100644
index 4aae923ea02..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/x509_crt.h
+++ /dev/null
@@ -1,812 +0,0 @@
-/**
- * \file x509_crt.h
- *
- * \brief X.509 certificate parsing and writing
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_X509_CRT_H
-#define MBEDTLS_X509_CRT_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "x509.h"
-#include "x509_crl.h"
-
-/**
- * \addtogroup x509_module
- * \{
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \name Structures and functions for parsing and writing X.509 certificates
- * \{
- */
-
-/**
- * Container for an X.509 certificate. The certificate may be chained.
- */
-typedef struct mbedtls_x509_crt
-{
-    mbedtls_x509_buf raw;               /**< The raw certificate data (DER). */
-    mbedtls_x509_buf tbs;               /**< The raw certificate body (DER). The part that is To Be Signed. */
-
-    int version;                /**< The X.509 version. (1=v1, 2=v2, 3=v3) */
-    mbedtls_x509_buf serial;            /**< Unique id for certificate issued by a specific CA. */
-    mbedtls_x509_buf sig_oid;           /**< Signature algorithm, e.g. sha1RSA */
-
-    mbedtls_x509_buf issuer_raw;        /**< The raw issuer data (DER). Used for quick comparison. */
-    mbedtls_x509_buf subject_raw;       /**< The raw subject data (DER). Used for quick comparison. */
-
-    mbedtls_x509_name issuer;           /**< The parsed issuer data (named information object). */
-    mbedtls_x509_name subject;          /**< The parsed subject data (named information object). */
-
-    mbedtls_x509_time valid_from;       /**< Start time of certificate validity. */
-    mbedtls_x509_time valid_to;         /**< End time of certificate validity. */
-
-    mbedtls_pk_context pk;              /**< Container for the public key context. */
-
-    mbedtls_x509_buf issuer_id;         /**< Optional X.509 v2/v3 issuer unique identifier. */
-    mbedtls_x509_buf subject_id;        /**< Optional X.509 v2/v3 subject unique identifier. */
-    mbedtls_x509_buf v3_ext;            /**< Optional X.509 v3 extensions.  */
-    mbedtls_x509_sequence subject_alt_names;    /**< Optional list of Subject Alternative Names (Only dNSName supported). */
-
-    int ext_types;              /**< Bit string containing detected and parsed extensions */
-    int ca_istrue;              /**< Optional Basic Constraint extension value: 1 if this certificate belongs to a CA, 0 otherwise. */
-    int max_pathlen;            /**< Optional Basic Constraint extension value: The maximum path length to the root certificate. Path length is 1 higher than RFC 5280 'meaning', so 1+ */
-
-    unsigned int key_usage;     /**< Optional key usage extension value: See the values in x509.h */
-
-    mbedtls_x509_sequence ext_key_usage; /**< Optional list of extended key usage OIDs. */
-
-    unsigned char ns_cert_type; /**< Optional Netscape certificate type extension value: See the values in x509.h */
-
-    mbedtls_x509_buf sig;               /**< Signature: hash of the tbs part signed with the private key. */
-    mbedtls_md_type_t sig_md;           /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */
-    mbedtls_pk_type_t sig_pk;           /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */
-    void *sig_opts;             /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */
-
-    struct mbedtls_x509_crt *next;     /**< Next certificate in the CA-chain. */
-}
-mbedtls_x509_crt;
-
-/**
- * Build flag from an algorithm/curve identifier (pk, md, ecp)
- * Since 0 is always XXX_NONE, ignore it.
- */
-#define MBEDTLS_X509_ID_FLAG( id )   ( 1 << ( (id) - 1 ) )
-
-/**
- * Security profile for certificate verification.
- *
- * All lists are bitfields, built by ORing flags from MBEDTLS_X509_ID_FLAG().
- */
-typedef struct mbedtls_x509_crt_profile
-{
-    uint32_t allowed_mds;       /**< MDs for signatures         */
-    uint32_t allowed_pks;       /**< PK algs for signatures     */
-    uint32_t allowed_curves;    /**< Elliptic curves for ECDSA  */
-    uint32_t rsa_min_bitlen;    /**< Minimum size for RSA keys  */
-}
-mbedtls_x509_crt_profile;
-
-#define MBEDTLS_X509_CRT_VERSION_1              0
-#define MBEDTLS_X509_CRT_VERSION_2              1
-#define MBEDTLS_X509_CRT_VERSION_3              2
-
-#define MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN 32
-#define MBEDTLS_X509_RFC5280_UTC_TIME_LEN   15
-
-#if !defined( MBEDTLS_X509_MAX_FILE_PATH_LEN )
-#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512
-#endif
-
-/**
- * Container for writing a certificate (CRT)
- */
-typedef struct mbedtls_x509write_cert
-{
-    int version;
-    mbedtls_mpi serial;
-    mbedtls_pk_context *subject_key;
-    mbedtls_pk_context *issuer_key;
-    mbedtls_asn1_named_data *subject;
-    mbedtls_asn1_named_data *issuer;
-    mbedtls_md_type_t md_alg;
-    char not_before[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1];
-    char not_after[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1];
-    mbedtls_asn1_named_data *extensions;
-}
-mbedtls_x509write_cert;
-
-/**
- * Item in a verification chain: cert and flags for it
- */
-typedef struct {
-    mbedtls_x509_crt *crt;
-    uint32_t flags;
-} mbedtls_x509_crt_verify_chain_item;
-
-/**
- * Max size of verification chain: end-entity + intermediates + trusted root
- */
-#define MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE  ( MBEDTLS_X509_MAX_INTERMEDIATE_CA + 2 )
-
-/**
- * Verification chain as built by \c mbedtls_crt_verify_chain()
- */
-typedef struct
-{
-    mbedtls_x509_crt_verify_chain_item items[MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE];
-    unsigned len;
-} mbedtls_x509_crt_verify_chain;
-
-#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE)
-
-/**
- * \brief       Context for resuming X.509 verify operations
- */
-typedef struct
-{
-    /* for check_signature() */
-    mbedtls_pk_restart_ctx pk;
-
-    /* for find_parent_in() */
-    mbedtls_x509_crt *parent; /* non-null iff parent_in in progress */
-    mbedtls_x509_crt *fallback_parent;
-    int fallback_signature_is_good;
-
-    /* for find_parent() */
-    int parent_is_trusted; /* -1 if find_parent is not in progress */
-
-    /* for verify_chain() */
-    enum {
-        x509_crt_rs_none,
-        x509_crt_rs_find_parent,
-    } in_progress;  /* none if no operation is in progress */
-    int self_cnt;
-    mbedtls_x509_crt_verify_chain ver_chain;
-
-} mbedtls_x509_crt_restart_ctx;
-
-#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */
-
-/* Now we can declare functions that take a pointer to that */
-typedef void mbedtls_x509_crt_restart_ctx;
-
-#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-/**
- * Default security profile. Should provide a good balance between security
- * and compatibility with current deployments.
- */
-extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_default;
-
-/**
- * Expected next default profile. Recommended for new deployments.
- * Currently targets a 128-bit security level, except for RSA-2048.
- */
-extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_next;
-
-/**
- * NSA Suite B profile.
- */
-extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_suiteb;
-
-/**
- * \brief          Parse a single DER formatted certificate and add it
- *                 to the chained list.
- *
- * \param chain    points to the start of the chain
- * \param buf      buffer holding the certificate DER data
- * \param buflen   size of the buffer
- *
- * \return         0 if successful, or a specific X509 or PEM error code
- */
-int mbedtls_x509_crt_parse_der( mbedtls_x509_crt *chain, const unsigned char *buf,
-                        size_t buflen );
-
-/**
- * \brief          Parse one DER-encoded or one or more concatenated PEM-encoded
- *                 certificates and add them to the chained list.
- *
- *                 For CRTs in PEM encoding, the function parses permissively:
- *                 if at least one certificate can be parsed, the function
- *                 returns the number of certificates for which parsing failed
- *                 (hence \c 0 if all certificates were parsed successfully).
- *                 If no certificate could be parsed, the function returns
- *                 the first (negative) error encountered during parsing.
- *
- *                 PEM encoded certificates may be interleaved by other data
- *                 such as human readable descriptions of their content, as
- *                 long as the certificates are enclosed in the PEM specific
- *                 '-----{BEGIN/END} CERTIFICATE-----' delimiters.
- *
- * \param chain    The chain to which to add the parsed certificates.
- * \param buf      The buffer holding the certificate data in PEM or DER format.
- *                 For certificates in PEM encoding, this may be a concatenation
- *                 of multiple certificates; for DER encoding, the buffer must
- *                 comprise exactly one certificate.
- * \param buflen   The size of \p buf, including the terminating \c NULL byte
- *                 in case of PEM encoded data.
- *
- * \return         \c 0 if all certificates were parsed successfully.
- * \return         The (positive) number of certificates that couldn't
- *                 be parsed if parsing was partly successful (see above).
- * \return         A negative X509 or PEM error code otherwise.
- *
- */
-int mbedtls_x509_crt_parse( mbedtls_x509_crt *chain, const unsigned char *buf, size_t buflen );
-
-#if defined(MBEDTLS_FS_IO)
-/**
- * \brief          Load one or more certificates and add them
- *                 to the chained list. Parses permissively. If some
- *                 certificates can be parsed, the result is the number
- *                 of failed certificates it encountered. If none complete
- *                 correctly, the first error is returned.
- *
- * \param chain    points to the start of the chain
- * \param path     filename to read the certificates from
- *
- * \return         0 if all certificates parsed successfully, a positive number
- *                 if partly successful or a specific X509 or PEM error code
- */
-int mbedtls_x509_crt_parse_file( mbedtls_x509_crt *chain, const char *path );
-
-/**
- * \brief          Load one or more certificate files from a path and add them
- *                 to the chained list. Parses permissively. If some
- *                 certificates can be parsed, the result is the number
- *                 of failed certificates it encountered. If none complete
- *                 correctly, the first error is returned.
- *
- * \param chain    points to the start of the chain
- * \param path     directory / folder to read the certificate files from
- *
- * \return         0 if all certificates parsed successfully, a positive number
- *                 if partly successful or a specific X509 or PEM error code
- */
-int mbedtls_x509_crt_parse_path( mbedtls_x509_crt *chain, const char *path );
-#endif /* MBEDTLS_FS_IO */
-
-/**
- * \brief          Returns an informational string about the
- *                 certificate.
- *
- * \param buf      Buffer to write to
- * \param size     Maximum size of buffer
- * \param prefix   A line prefix
- * \param crt      The X509 certificate to represent
- *
- * \return         The length of the string written (not including the
- *                 terminated nul byte), or a negative error code.
- */
-int mbedtls_x509_crt_info( char *buf, size_t size, const char *prefix,
-                   const mbedtls_x509_crt *crt );
-
-/**
- * \brief          Returns an informational string about the
- *                 verification status of a certificate.
- *
- * \param buf      Buffer to write to
- * \param size     Maximum size of buffer
- * \param prefix   A line prefix
- * \param flags    Verification flags created by mbedtls_x509_crt_verify()
- *
- * \return         The length of the string written (not including the
- *                 terminated nul byte), or a negative error code.
- */
-int mbedtls_x509_crt_verify_info( char *buf, size_t size, const char *prefix,
-                          uint32_t flags );
-
-/**
- * \brief          Verify the certificate signature
- *
- *                 The verify callback is a user-supplied callback that
- *                 can clear / modify / add flags for a certificate. If set,
- *                 the verification callback is called for each
- *                 certificate in the chain (from the trust-ca down to the
- *                 presented crt). The parameters for the callback are:
- *                 (void *parameter, mbedtls_x509_crt *crt, int certificate_depth,
- *                 int *flags). With the flags representing current flags for
- *                 that specific certificate and the certificate depth from
- *                 the bottom (Peer cert depth = 0).
- *
- *                 All flags left after returning from the callback
- *                 are also returned to the application. The function should
- *                 return 0 for anything (including invalid certificates)
- *                 other than fatal error, as a non-zero return code
- *                 immediately aborts the verification process. For fatal
- *                 errors, a specific error code should be used (different
- *                 from MBEDTLS_ERR_X509_CERT_VERIFY_FAILED which should not
- *                 be returned at this point), or MBEDTLS_ERR_X509_FATAL_ERROR
- *                 can be used if no better code is available.
- *
- * \note           In case verification failed, the results can be displayed
- *                 using \c mbedtls_x509_crt_verify_info()
- *
- * \note           Same as \c mbedtls_x509_crt_verify_with_profile() with the
- *                 default security profile.
- *
- * \note           It is your responsibility to provide up-to-date CRLs for
- *                 all trusted CAs. If no CRL is provided for the CA that was
- *                 used to sign the certificate, CRL verification is skipped
- *                 silently, that is *without* setting any flag.
- *
- * \note           The \c trust_ca list can contain two types of certificates:
- *                 (1) those of trusted root CAs, so that certificates
- *                 chaining up to those CAs will be trusted, and (2)
- *                 self-signed end-entity certificates to be trusted (for
- *                 specific peers you know) - in that case, the self-signed
- *                 certificate doesn't need to have the CA bit set.
- *
- * \param crt      a certificate (chain) to be verified
- * \param trust_ca the list of trusted CAs (see note above)
- * \param ca_crl   the list of CRLs for trusted CAs (see note above)
- * \param cn       expected Common Name (can be set to
- *                 NULL if the CN must not be verified)
- * \param flags    result of the verification
- * \param f_vrfy   verification function
- * \param p_vrfy   verification parameter
- *
- * \return         0 (and flags set to 0) if the chain was verified and valid,
- *                 MBEDTLS_ERR_X509_CERT_VERIFY_FAILED if the chain was verified
- *                 but found to be invalid, in which case *flags will have one
- *                 or more MBEDTLS_X509_BADCERT_XXX or MBEDTLS_X509_BADCRL_XXX
- *                 flags set, or another error (and flags set to 0xffffffff)
- *                 in case of a fatal error encountered during the
- *                 verification process.
- */
-int mbedtls_x509_crt_verify( mbedtls_x509_crt *crt,
-                     mbedtls_x509_crt *trust_ca,
-                     mbedtls_x509_crl *ca_crl,
-                     const char *cn, uint32_t *flags,
-                     int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *),
-                     void *p_vrfy );
-
-/**
- * \brief          Verify the certificate signature according to profile
- *
- * \note           Same as \c mbedtls_x509_crt_verify(), but with explicit
- *                 security profile.
- *
- * \note           The restrictions on keys (RSA minimum size, allowed curves
- *                 for ECDSA) apply to all certificates: trusted root,
- *                 intermediate CAs if any, and end entity certificate.
- *
- * \param crt      a certificate (chain) to be verified
- * \param trust_ca the list of trusted CAs
- * \param ca_crl   the list of CRLs for trusted CAs
- * \param profile  security profile for verification
- * \param cn       expected Common Name (can be set to
- *                 NULL if the CN must not be verified)
- * \param flags    result of the verification
- * \param f_vrfy   verification function
- * \param p_vrfy   verification parameter
- *
- * \return         0 if successful or MBEDTLS_ERR_X509_CERT_VERIFY_FAILED
- *                 in which case *flags will have one or more
- *                 MBEDTLS_X509_BADCERT_XXX or MBEDTLS_X509_BADCRL_XXX flags
- *                 set,
- *                 or another error in case of a fatal error encountered
- *                 during the verification process.
- */
-int mbedtls_x509_crt_verify_with_profile( mbedtls_x509_crt *crt,
-                     mbedtls_x509_crt *trust_ca,
-                     mbedtls_x509_crl *ca_crl,
-                     const mbedtls_x509_crt_profile *profile,
-                     const char *cn, uint32_t *flags,
-                     int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *),
-                     void *p_vrfy );
-
-/**
- * \brief          Restartable version of \c mbedtls_crt_verify_with_profile()
- *
- * \note           Performs the same job as \c mbedtls_crt_verify_with_profile()
- *                 but can return early and restart according to the limit
- *                 set with \c mbedtls_ecp_set_max_ops() to reduce blocking.
- *
- * \param crt      a certificate (chain) to be verified
- * \param trust_ca the list of trusted CAs
- * \param ca_crl   the list of CRLs for trusted CAs
- * \param profile  security profile for verification
- * \param cn       expected Common Name (can be set to
- *                 NULL if the CN must not be verified)
- * \param flags    result of the verification
- * \param f_vrfy   verification function
- * \param p_vrfy   verification parameter
- * \param rs_ctx   restart context (NULL to disable restart)
- *
- * \return         See \c mbedtls_crt_verify_with_profile(), or
- * \return         #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of
- *                 operations was reached: see \c mbedtls_ecp_set_max_ops().
- */
-int mbedtls_x509_crt_verify_restartable( mbedtls_x509_crt *crt,
-                     mbedtls_x509_crt *trust_ca,
-                     mbedtls_x509_crl *ca_crl,
-                     const mbedtls_x509_crt_profile *profile,
-                     const char *cn, uint32_t *flags,
-                     int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *),
-                     void *p_vrfy,
-                     mbedtls_x509_crt_restart_ctx *rs_ctx );
-
-#if defined(MBEDTLS_X509_CHECK_KEY_USAGE)
-/**
- * \brief          Check usage of certificate against keyUsage extension.
- *
- * \param crt      Leaf certificate used.
- * \param usage    Intended usage(s) (eg MBEDTLS_X509_KU_KEY_ENCIPHERMENT
- *                 before using the certificate to perform an RSA key
- *                 exchange).
- *
- * \note           Except for decipherOnly and encipherOnly, a bit set in the
- *                 usage argument means this bit MUST be set in the
- *                 certificate. For decipherOnly and encipherOnly, it means
- *                 that bit MAY be set.
- *
- * \return         0 is these uses of the certificate are allowed,
- *                 MBEDTLS_ERR_X509_BAD_INPUT_DATA if the keyUsage extension
- *                 is present but does not match the usage argument.
- *
- * \note           You should only call this function on leaf certificates, on
- *                 (intermediate) CAs the keyUsage extension is automatically
- *                 checked by \c mbedtls_x509_crt_verify().
- */
-int mbedtls_x509_crt_check_key_usage( const mbedtls_x509_crt *crt,
-                                      unsigned int usage );
-#endif /* MBEDTLS_X509_CHECK_KEY_USAGE) */
-
-#if defined(MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE)
-/**
- * \brief           Check usage of certificate against extendedKeyUsage.
- *
- * \param crt       Leaf certificate used.
- * \param usage_oid Intended usage (eg MBEDTLS_OID_SERVER_AUTH or
- *                  MBEDTLS_OID_CLIENT_AUTH).
- * \param usage_len Length of usage_oid (eg given by MBEDTLS_OID_SIZE()).
- *
- * \return          0 if this use of the certificate is allowed,
- *                  MBEDTLS_ERR_X509_BAD_INPUT_DATA if not.
- *
- * \note            Usually only makes sense on leaf certificates.
- */
-int mbedtls_x509_crt_check_extended_key_usage( const mbedtls_x509_crt *crt,
-                                               const char *usage_oid,
-                                               size_t usage_len );
-#endif /* MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE */
-
-#if defined(MBEDTLS_X509_CRL_PARSE_C)
-/**
- * \brief          Verify the certificate revocation status
- *
- * \param crt      a certificate to be verified
- * \param crl      the CRL to verify against
- *
- * \return         1 if the certificate is revoked, 0 otherwise
- *
- */
-int mbedtls_x509_crt_is_revoked( const mbedtls_x509_crt *crt, const mbedtls_x509_crl *crl );
-#endif /* MBEDTLS_X509_CRL_PARSE_C */
-
-/**
- * \brief          Initialize a certificate (chain)
- *
- * \param crt      Certificate chain to initialize
- */
-void mbedtls_x509_crt_init( mbedtls_x509_crt *crt );
-
-/**
- * \brief          Unallocate all certificate data
- *
- * \param crt      Certificate chain to free
- */
-void mbedtls_x509_crt_free( mbedtls_x509_crt *crt );
-
-#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE)
-/**
- * \brief           Initialize a restart context
- */
-void mbedtls_x509_crt_restart_init( mbedtls_x509_crt_restart_ctx *ctx );
-
-/**
- * \brief           Free the components of a restart context
- */
-void mbedtls_x509_crt_restart_free( mbedtls_x509_crt_restart_ctx *ctx );
-#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */
-#endif /* MBEDTLS_X509_CRT_PARSE_C */
-
-/* \} name */
-/* \} addtogroup x509_module */
-
-#if defined(MBEDTLS_X509_CRT_WRITE_C)
-/**
- * \brief           Initialize a CRT writing context
- *
- * \param ctx       CRT context to initialize
- */
-void mbedtls_x509write_crt_init( mbedtls_x509write_cert *ctx );
-
-/**
- * \brief           Set the verion for a Certificate
- *                  Default: MBEDTLS_X509_CRT_VERSION_3
- *
- * \param ctx       CRT context to use
- * \param version   version to set (MBEDTLS_X509_CRT_VERSION_1, MBEDTLS_X509_CRT_VERSION_2 or
- *                                  MBEDTLS_X509_CRT_VERSION_3)
- */
-void mbedtls_x509write_crt_set_version( mbedtls_x509write_cert *ctx, int version );
-
-/**
- * \brief           Set the serial number for a Certificate.
- *
- * \param ctx       CRT context to use
- * \param serial    serial number to set
- *
- * \return          0 if successful
- */
-int mbedtls_x509write_crt_set_serial( mbedtls_x509write_cert *ctx, const mbedtls_mpi *serial );
-
-/**
- * \brief           Set the validity period for a Certificate
- *                  Timestamps should be in string format for UTC timezone
- *                  i.e. "YYYYMMDDhhmmss"
- *                  e.g. "20131231235959" for December 31st 2013
- *                       at 23:59:59
- *
- * \param ctx       CRT context to use
- * \param not_before    not_before timestamp
- * \param not_after     not_after timestamp
- *
- * \return          0 if timestamp was parsed successfully, or
- *                  a specific error code
- */
-int mbedtls_x509write_crt_set_validity( mbedtls_x509write_cert *ctx, const char *not_before,
-                                const char *not_after );
-
-/**
- * \brief           Set the issuer name for a Certificate
- *                  Issuer names should contain a comma-separated list
- *                  of OID types and values:
- *                  e.g. "C=UK,O=ARM,CN=mbed TLS CA"
- *
- * \param ctx           CRT context to use
- * \param issuer_name   issuer name to set
- *
- * \return          0 if issuer name was parsed successfully, or
- *                  a specific error code
- */
-int mbedtls_x509write_crt_set_issuer_name( mbedtls_x509write_cert *ctx,
-                                   const char *issuer_name );
-
-/**
- * \brief           Set the subject name for a Certificate
- *                  Subject names should contain a comma-separated list
- *                  of OID types and values:
- *                  e.g. "C=UK,O=ARM,CN=mbed TLS Server 1"
- *
- * \param ctx           CRT context to use
- * \param subject_name  subject name to set
- *
- * \return          0 if subject name was parsed successfully, or
- *                  a specific error code
- */
-int mbedtls_x509write_crt_set_subject_name( mbedtls_x509write_cert *ctx,
-                                    const char *subject_name );
-
-/**
- * \brief           Set the subject public key for the certificate
- *
- * \param ctx       CRT context to use
- * \param key       public key to include
- */
-void mbedtls_x509write_crt_set_subject_key( mbedtls_x509write_cert *ctx, mbedtls_pk_context *key );
-
-/**
- * \brief           Set the issuer key used for signing the certificate
- *
- * \param ctx       CRT context to use
- * \param key       private key to sign with
- */
-void mbedtls_x509write_crt_set_issuer_key( mbedtls_x509write_cert *ctx, mbedtls_pk_context *key );
-
-/**
- * \brief           Set the MD algorithm to use for the signature
- *                  (e.g. MBEDTLS_MD_SHA1)
- *
- * \param ctx       CRT context to use
- * \param md_alg    MD algorithm to use
- */
-void mbedtls_x509write_crt_set_md_alg( mbedtls_x509write_cert *ctx, mbedtls_md_type_t md_alg );
-
-/**
- * \brief           Generic function to add to or replace an extension in the
- *                  CRT
- *
- * \param ctx       CRT context to use
- * \param oid       OID of the extension
- * \param oid_len   length of the OID
- * \param critical  if the extension is critical (per the RFC's definition)
- * \param val       value of the extension OCTET STRING
- * \param val_len   length of the value data
- *
- * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
- */
-int mbedtls_x509write_crt_set_extension( mbedtls_x509write_cert *ctx,
-                                 const char *oid, size_t oid_len,
-                                 int critical,
-                                 const unsigned char *val, size_t val_len );
-
-/**
- * \brief           Set the basicConstraints extension for a CRT
- *
- * \param ctx       CRT context to use
- * \param is_ca     is this a CA certificate
- * \param max_pathlen   maximum length of certificate chains below this
- *                      certificate (only for CA certificates, -1 is
- *                      inlimited)
- *
- * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
- */
-int mbedtls_x509write_crt_set_basic_constraints( mbedtls_x509write_cert *ctx,
-                                         int is_ca, int max_pathlen );
-
-#if defined(MBEDTLS_SHA1_C)
-/**
- * \brief           Set the subjectKeyIdentifier extension for a CRT
- *                  Requires that mbedtls_x509write_crt_set_subject_key() has been
- *                  called before
- *
- * \param ctx       CRT context to use
- *
- * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
- */
-int mbedtls_x509write_crt_set_subject_key_identifier( mbedtls_x509write_cert *ctx );
-
-/**
- * \brief           Set the authorityKeyIdentifier extension for a CRT
- *                  Requires that mbedtls_x509write_crt_set_issuer_key() has been
- *                  called before
- *
- * \param ctx       CRT context to use
- *
- * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
- */
-int mbedtls_x509write_crt_set_authority_key_identifier( mbedtls_x509write_cert *ctx );
-#endif /* MBEDTLS_SHA1_C */
-
-/**
- * \brief           Set the Key Usage Extension flags
- *                  (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN)
- *
- * \param ctx       CRT context to use
- * \param key_usage key usage flags to set
- *
- * \return          0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED
- */
-int mbedtls_x509write_crt_set_key_usage( mbedtls_x509write_cert *ctx,
-                                         unsigned int key_usage );
-
-/**
- * \brief           Set the Netscape Cert Type flags
- *                  (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL)
- *
- * \param ctx           CRT context to use
- * \param ns_cert_type  Netscape Cert Type flags to set
- *
- * \return          0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED
- */
-int mbedtls_x509write_crt_set_ns_cert_type( mbedtls_x509write_cert *ctx,
-                                    unsigned char ns_cert_type );
-
-/**
- * \brief           Free the contents of a CRT write context
- *
- * \param ctx       CRT context to free
- */
-void mbedtls_x509write_crt_free( mbedtls_x509write_cert *ctx );
-
-/**
- * \brief           Write a built up certificate to a X509 DER structure
- *                  Note: data is written at the end of the buffer! Use the
- *                        return value to determine where you should start
- *                        using the buffer
- *
- * \param ctx       certificate to write away
- * \param buf       buffer to write to
- * \param size      size of the buffer
- * \param f_rng     RNG function (for signature, see note)
- * \param p_rng     RNG parameter
- *
- * \return          length of data written if successful, or a specific
- *                  error code
- *
- * \note            f_rng may be NULL if RSA is used for signature and the
- *                  signature is made offline (otherwise f_rng is desirable
- *                  for countermeasures against timing attacks).
- *                  ECDSA signatures always require a non-NULL f_rng.
- */
-int mbedtls_x509write_crt_der( mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size,
-                       int (*f_rng)(void *, unsigned char *, size_t),
-                       void *p_rng );
-
-#if defined(MBEDTLS_PEM_WRITE_C)
-/**
- * \brief           Write a built up certificate to a X509 PEM string
- *
- * \param ctx       certificate to write away
- * \param buf       buffer to write to
- * \param size      size of the buffer
- * \param f_rng     RNG function (for signature, see note)
- * \param p_rng     RNG parameter
- *
- * \return          0 if successful, or a specific error code
- *
- * \note            f_rng may be NULL if RSA is used for signature and the
- *                  signature is made offline (otherwise f_rng is desirable
- *                  for countermeasures against timing attacks).
- *                  ECDSA signatures always require a non-NULL f_rng.
- */
-int mbedtls_x509write_crt_pem( mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size,
-                       int (*f_rng)(void *, unsigned char *, size_t),
-                       void *p_rng );
-#endif /* MBEDTLS_PEM_WRITE_C */
-#endif /* MBEDTLS_X509_CRT_WRITE_C */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_x509_crt.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/x509_csr.h b/tools/sdk/include/mbedtls/mbedtls/x509_csr.h
deleted file mode 100644
index 8ba2cda0dc5..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/x509_csr.h
+++ /dev/null
@@ -1,334 +0,0 @@
-/**
- * \file x509_csr.h
- *
- * \brief X.509 certificate signing request parsing and writing
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_X509_CSR_H
-#define MBEDTLS_X509_CSR_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include "x509.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \addtogroup x509_module
- * \{ */
-
-/**
- * \name Structures and functions for X.509 Certificate Signing Requests (CSR)
- * \{
- */
-
-/**
- * Certificate Signing Request (CSR) structure.
- */
-typedef struct mbedtls_x509_csr
-{
-    mbedtls_x509_buf raw;           /**< The raw CSR data (DER). */
-    mbedtls_x509_buf cri;           /**< The raw CertificateRequestInfo body (DER). */
-
-    int version;            /**< CSR version (1=v1). */
-
-    mbedtls_x509_buf  subject_raw;  /**< The raw subject data (DER). */
-    mbedtls_x509_name subject;      /**< The parsed subject data (named information object). */
-
-    mbedtls_pk_context pk;          /**< Container for the public key context. */
-
-    mbedtls_x509_buf sig_oid;
-    mbedtls_x509_buf sig;
-    mbedtls_md_type_t sig_md;       /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */
-    mbedtls_pk_type_t sig_pk;       /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */
-    void *sig_opts;         /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */
-}
-mbedtls_x509_csr;
-
-/**
- * Container for writing a CSR
- */
-typedef struct mbedtls_x509write_csr
-{
-    mbedtls_pk_context *key;
-    mbedtls_asn1_named_data *subject;
-    mbedtls_md_type_t md_alg;
-    mbedtls_asn1_named_data *extensions;
-}
-mbedtls_x509write_csr;
-
-#if defined(MBEDTLS_X509_CSR_PARSE_C)
-/**
- * \brief          Load a Certificate Signing Request (CSR) in DER format
- *
- * \note           CSR attributes (if any) are currently silently ignored.
- *
- * \param csr      CSR context to fill
- * \param buf      buffer holding the CRL data
- * \param buflen   size of the buffer
- *
- * \return         0 if successful, or a specific X509 error code
- */
-int mbedtls_x509_csr_parse_der( mbedtls_x509_csr *csr,
-                        const unsigned char *buf, size_t buflen );
-
-/**
- * \brief          Load a Certificate Signing Request (CSR), DER or PEM format
- *
- * \note           See notes for \c mbedtls_x509_csr_parse_der()
- *
- * \param csr      CSR context to fill
- * \param buf      buffer holding the CRL data
- * \param buflen   size of the buffer
- *                 (including the terminating null byte for PEM data)
- *
- * \return         0 if successful, or a specific X509 or PEM error code
- */
-int mbedtls_x509_csr_parse( mbedtls_x509_csr *csr, const unsigned char *buf, size_t buflen );
-
-#if defined(MBEDTLS_FS_IO)
-/**
- * \brief          Load a Certificate Signing Request (CSR)
- *
- * \note           See notes for \c mbedtls_x509_csr_parse()
- *
- * \param csr      CSR context to fill
- * \param path     filename to read the CSR from
- *
- * \return         0 if successful, or a specific X509 or PEM error code
- */
-int mbedtls_x509_csr_parse_file( mbedtls_x509_csr *csr, const char *path );
-#endif /* MBEDTLS_FS_IO */
-
-/**
- * \brief          Returns an informational string about the
- *                 CSR.
- *
- * \param buf      Buffer to write to
- * \param size     Maximum size of buffer
- * \param prefix   A line prefix
- * \param csr      The X509 CSR to represent
- *
- * \return         The length of the string written (not including the
- *                 terminated nul byte), or a negative error code.
- */
-int mbedtls_x509_csr_info( char *buf, size_t size, const char *prefix,
-                   const mbedtls_x509_csr *csr );
-
-/**
- * \brief          Initialize a CSR
- *
- * \param csr      CSR to initialize
- */
-void mbedtls_x509_csr_init( mbedtls_x509_csr *csr );
-
-/**
- * \brief          Unallocate all CSR data
- *
- * \param csr      CSR to free
- */
-void mbedtls_x509_csr_free( mbedtls_x509_csr *csr );
-#endif /* MBEDTLS_X509_CSR_PARSE_C */
-
-/* \} name */
-/* \} addtogroup x509_module */
-
-#if defined(MBEDTLS_X509_CSR_WRITE_C)
-/**
- * \brief           Initialize a CSR context
- *
- * \param ctx       CSR context to initialize
- */
-void mbedtls_x509write_csr_init( mbedtls_x509write_csr *ctx );
-
-/**
- * \brief           Set the subject name for a CSR
- *                  Subject names should contain a comma-separated list
- *                  of OID types and values:
- *                  e.g. "C=UK,O=ARM,CN=mbed TLS Server 1"
- *
- * \param ctx           CSR context to use
- * \param subject_name  subject name to set
- *
- * \return          0 if subject name was parsed successfully, or
- *                  a specific error code
- */
-int mbedtls_x509write_csr_set_subject_name( mbedtls_x509write_csr *ctx,
-                                    const char *subject_name );
-
-/**
- * \brief           Set the key for a CSR (public key will be included,
- *                  private key used to sign the CSR when writing it)
- *
- * \param ctx       CSR context to use
- * \param key       Asymetric key to include
- */
-void mbedtls_x509write_csr_set_key( mbedtls_x509write_csr *ctx, mbedtls_pk_context *key );
-
-/**
- * \brief           Set the MD algorithm to use for the signature
- *                  (e.g. MBEDTLS_MD_SHA1)
- *
- * \param ctx       CSR context to use
- * \param md_alg    MD algorithm to use
- */
-void mbedtls_x509write_csr_set_md_alg( mbedtls_x509write_csr *ctx, mbedtls_md_type_t md_alg );
-
-/**
- * \brief           Set the Key Usage Extension flags
- *                  (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN)
- *
- * \param ctx       CSR context to use
- * \param key_usage key usage flags to set
- *
- * \return          0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED
- *
- * \note            The <code>decipherOnly</code> flag from the Key Usage
- *                  extension is represented by bit 8 (i.e.
- *                  <code>0x8000</code>), which cannot typically be represented
- *                  in an unsigned char. Therefore, the flag
- *                  <code>decipherOnly</code> (i.e.
- *                  #MBEDTLS_X509_KU_DECIPHER_ONLY) cannot be set using this
- *                  function.
- */
-int mbedtls_x509write_csr_set_key_usage( mbedtls_x509write_csr *ctx, unsigned char key_usage );
-
-/**
- * \brief           Set the Netscape Cert Type flags
- *                  (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL)
- *
- * \param ctx           CSR context to use
- * \param ns_cert_type  Netscape Cert Type flags to set
- *
- * \return          0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED
- */
-int mbedtls_x509write_csr_set_ns_cert_type( mbedtls_x509write_csr *ctx,
-                                    unsigned char ns_cert_type );
-
-/**
- * \brief           Generic function to add to or replace an extension in the
- *                  CSR
- *
- * \param ctx       CSR context to use
- * \param oid       OID of the extension
- * \param oid_len   length of the OID
- * \param val       value of the extension OCTET STRING
- * \param val_len   length of the value data
- *
- * \return          0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED
- */
-int mbedtls_x509write_csr_set_extension( mbedtls_x509write_csr *ctx,
-                                 const char *oid, size_t oid_len,
-                                 const unsigned char *val, size_t val_len );
-
-/**
- * \brief           Free the contents of a CSR context
- *
- * \param ctx       CSR context to free
- */
-void mbedtls_x509write_csr_free( mbedtls_x509write_csr *ctx );
-
-/**
- * \brief           Write a CSR (Certificate Signing Request) to a
- *                  DER structure
- *                  Note: data is written at the end of the buffer! Use the
- *                        return value to determine where you should start
- *                        using the buffer
- *
- * \param ctx       CSR to write away
- * \param buf       buffer to write to
- * \param size      size of the buffer
- * \param f_rng     RNG function (for signature, see note)
- * \param p_rng     RNG parameter
- *
- * \return          length of data written if successful, or a specific
- *                  error code
- *
- * \note            f_rng may be NULL if RSA is used for signature and the
- *                  signature is made offline (otherwise f_rng is desirable
- *                  for countermeasures against timing attacks).
- *                  ECDSA signatures always require a non-NULL f_rng.
- */
-int mbedtls_x509write_csr_der( mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size,
-                       int (*f_rng)(void *, unsigned char *, size_t),
-                       void *p_rng );
-
-#if defined(MBEDTLS_PEM_WRITE_C)
-/**
- * \brief           Write a CSR (Certificate Signing Request) to a
- *                  PEM string
- *
- * \param ctx       CSR to write away
- * \param buf       buffer to write to
- * \param size      size of the buffer
- * \param f_rng     RNG function (for signature, see note)
- * \param p_rng     RNG parameter
- *
- * \return          0 if successful, or a specific error code
- *
- * \note            f_rng may be NULL if RSA is used for signature and the
- *                  signature is made offline (otherwise f_rng is desirable
- *                  for countermeasures against timing attacks).
- *                  ECDSA signatures always require a non-NULL f_rng.
- */
-int mbedtls_x509write_csr_pem( mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size,
-                       int (*f_rng)(void *, unsigned char *, size_t),
-                       void *p_rng );
-#endif /* MBEDTLS_PEM_WRITE_C */
-#endif /* MBEDTLS_X509_CSR_WRITE_C */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* mbedtls_x509_csr.h */
diff --git a/tools/sdk/include/mbedtls/mbedtls/xtea.h b/tools/sdk/include/mbedtls/mbedtls/xtea.h
deleted file mode 100644
index d372110215f..00000000000
--- a/tools/sdk/include/mbedtls/mbedtls/xtea.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * \file xtea.h
- *
- * \brief XTEA block cipher (32-bit)
- */
-/*
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_XTEA_H
-#define MBEDTLS_XTEA_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#include <stddef.h>
-#include <stdint.h>
-
-#define MBEDTLS_XTEA_ENCRYPT     1
-#define MBEDTLS_XTEA_DECRYPT     0
-
-#define MBEDTLS_ERR_XTEA_INVALID_INPUT_LENGTH             -0x0028  /**< The data input has an invalid length. */
-
-/* MBEDTLS_ERR_XTEA_HW_ACCEL_FAILED is deprecated and should not be used. */
-#define MBEDTLS_ERR_XTEA_HW_ACCEL_FAILED                  -0x0029  /**< XTEA hardware accelerator failed. */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(MBEDTLS_XTEA_ALT)
-// Regular implementation
-//
-
-/**
- * \brief          XTEA context structure
- */
-typedef struct mbedtls_xtea_context
-{
-    uint32_t k[4];       /*!< key */
-}
-mbedtls_xtea_context;
-
-#else  /* MBEDTLS_XTEA_ALT */
-#include "xtea_alt.h"
-#endif /* MBEDTLS_XTEA_ALT */
-
-/**
- * \brief          Initialize XTEA context
- *
- * \param ctx      XTEA context to be initialized
- */
-void mbedtls_xtea_init( mbedtls_xtea_context *ctx );
-
-/**
- * \brief          Clear XTEA context
- *
- * \param ctx      XTEA context to be cleared
- */
-void mbedtls_xtea_free( mbedtls_xtea_context *ctx );
-
-/**
- * \brief          XTEA key schedule
- *
- * \param ctx      XTEA context to be initialized
- * \param key      the secret key
- */
-void mbedtls_xtea_setup( mbedtls_xtea_context *ctx, const unsigned char key[16] );
-
-/**
- * \brief          XTEA cipher function
- *
- * \param ctx      XTEA context
- * \param mode     MBEDTLS_XTEA_ENCRYPT or MBEDTLS_XTEA_DECRYPT
- * \param input    8-byte input block
- * \param output   8-byte output block
- *
- * \return         0 if successful
- */
-int mbedtls_xtea_crypt_ecb( mbedtls_xtea_context *ctx,
-                    int mode,
-                    const unsigned char input[8],
-                    unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief          XTEA CBC cipher function
- *
- * \param ctx      XTEA context
- * \param mode     MBEDTLS_XTEA_ENCRYPT or MBEDTLS_XTEA_DECRYPT
- * \param length   the length of input, multiple of 8
- * \param iv       initialization vector for CBC mode
- * \param input    input block
- * \param output   output block
- *
- * \return         0 if successful,
- *                 MBEDTLS_ERR_XTEA_INVALID_INPUT_LENGTH if the length % 8 != 0
- */
-int mbedtls_xtea_crypt_cbc( mbedtls_xtea_context *ctx,
-                    int mode,
-                    size_t length,
-                    unsigned char iv[8],
-                    const unsigned char *input,
-                    unsigned char *output);
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#if defined(MBEDTLS_SELF_TEST)
-
-/**
- * \brief          Checkup routine
- *
- * \return         0 if successful, or 1 if the test failed
- */
-int mbedtls_xtea_self_test( int verbose );
-
-#endif /* MBEDTLS_SELF_TEST */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* xtea.h */
diff --git a/tools/sdk/include/mbedtls/sha1_alt.h b/tools/sdk/include/mbedtls/sha1_alt.h
deleted file mode 100644
index 54b77408780..00000000000
--- a/tools/sdk/include/mbedtls/sha1_alt.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *  SHA-1 implementation with hardware ESP32 support added.
- *  Uses mbedTLS software implementation for failover when concurrent
- *  SHA operations are in use.
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE LTD
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- */
-#ifndef _SHA1_ALT_H_
-#define _SHA1_ALT_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(MBEDTLS_SHA1_ALT)
-
-typedef enum {
-    ESP_MBEDTLS_SHA1_UNUSED, /* first block hasn't been processed yet */
-    ESP_MBEDTLS_SHA1_HARDWARE, /* using hardware SHA engine */
-    ESP_MBEDTLS_SHA1_SOFTWARE, /* using software SHA */
-} esp_mbedtls_sha1_mode;
-
-/**
- * \brief          SHA-1 context structure
- */
-typedef struct
-{
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[5];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-    esp_mbedtls_sha1_mode mode;
-}
-mbedtls_sha1_context;
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/tools/sdk/include/mbedtls/sha256_alt.h b/tools/sdk/include/mbedtls/sha256_alt.h
deleted file mode 100644
index 436f5324c8c..00000000000
--- a/tools/sdk/include/mbedtls/sha256_alt.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *  SHA-256 implementation with hardware ESP32 support added.
- *  Uses mbedTLS software implementation for failover when concurrent
- *  SHA operations are in use.
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE LTD
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- */
-#ifndef _SHA256_ALT_H_
-#define _SHA256_ALT_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(MBEDTLS_SHA256_ALT)
-
-typedef enum {
-    ESP_MBEDTLS_SHA256_UNUSED, /* first block hasn't been processed yet */
-    ESP_MBEDTLS_SHA256_HARDWARE, /* using hardware SHA engine */
-    ESP_MBEDTLS_SHA256_SOFTWARE, /* using software SHA */
-} esp_mbedtls_sha256_mode;
-
-/**
- * \brief          SHA-256 context structure
- */
-typedef struct
-{
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[8];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-    int is224;                  /*!< 0 => SHA-256, else SHA-224 */
-    esp_mbedtls_sha256_mode mode;
-}
-mbedtls_sha256_context;
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/mbedtls/sha512_alt.h b/tools/sdk/include/mbedtls/sha512_alt.h
deleted file mode 100644
index 36b8fc9d244..00000000000
--- a/tools/sdk/include/mbedtls/sha512_alt.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *  SHA-512 implementation with hardware ESP32 support added.
- *  Uses mbedTLS software implementation for failover when concurrent
- *  SHA operations are in use.
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE LTD
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- */
-#ifndef _SHA512_ALT_H_
-#define _SHA512_ALT_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(MBEDTLS_SHA512_ALT)
-
-typedef enum {
-    ESP_MBEDTLS_SHA512_UNUSED, /* first block hasn't been processed yet */
-    ESP_MBEDTLS_SHA512_HARDWARE, /* using hardware SHA engine */
-    ESP_MBEDTLS_SHA512_SOFTWARE, /* using software SHA */
-} esp_mbedtls_sha512_mode;
-
-/**
- * \brief          SHA-512 context structure
- */
-typedef struct
-{
-    uint64_t total[2];          /*!< number of bytes processed  */
-    uint64_t state[8];          /*!< intermediate digest state  */
-    unsigned char buffer[128];  /*!< data block being processed */
-    int is384;                  /*!< 0 => SHA-512, else SHA-384 */
-    esp_mbedtls_sha512_mode mode;
-}
-mbedtls_sha512_context;
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/mdns/mdns.h b/tools/sdk/include/mdns/mdns.h
deleted file mode 100644
index a5ebb809f6b..00000000000
--- a/tools/sdk/include/mdns/mdns.h
+++ /dev/null
@@ -1,362 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef ESP_MDNS_H_
-#define ESP_MDNS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <tcpip_adapter.h>
-#include "esp_event.h"
-
-#define MDNS_TYPE_A                 0x0001
-#define MDNS_TYPE_PTR               0x000C
-#define MDNS_TYPE_TXT               0x0010
-#define MDNS_TYPE_AAAA              0x001C
-#define MDNS_TYPE_SRV               0x0021
-#define MDNS_TYPE_OPT               0x0029
-#define MDNS_TYPE_NSEC              0x002F
-#define MDNS_TYPE_ANY               0x00FF
-
-/**
- * @brief   mDNS enum to specify the ip_protocol type
- */
-typedef enum {
-    MDNS_IP_PROTOCOL_V4,
-    MDNS_IP_PROTOCOL_V6,
-    MDNS_IP_PROTOCOL_MAX
-} mdns_ip_protocol_t;
-
-/**
- * @brief   mDNS basic text item structure
- *          Used in mdns_service_add()
- */
-typedef struct {
-    char * key;                             /*!< item key name */
-    char * value;                           /*!< item value string */
-} mdns_txt_item_t;
-
-/**
- * @brief   mDNS query linked list IP item
- */
-typedef struct mdns_ip_addr_s {
-    ip_addr_t addr;                         /*!< IP address */
-    struct mdns_ip_addr_s * next;           /*!< next IP, or NULL for the last IP in the list */
-} mdns_ip_addr_t;
-
-/**
- * @brief   mDNS query result structure
- */
-typedef struct mdns_result_s {
-    struct mdns_result_s * next;            /*!< next result, or NULL for the last result in the list */
-
-    tcpip_adapter_if_t tcpip_if;            /*!< interface on which the result came (AP/STA/ETH) */
-    mdns_ip_protocol_t ip_protocol;         /*!< ip_protocol type of the interface (v4/v6) */
-    // PTR
-    char * instance_name;                   /*!< instance name */
-    // SRV
-    char * hostname;                        /*!< hostname */
-    uint16_t port;                          /*!< service port */
-    // TXT
-    mdns_txt_item_t * txt;                  /*!< txt record */
-    size_t txt_count;                       /*!< number of txt items */
-    // A and AAAA
-    mdns_ip_addr_t * addr;                  /*!< linked list of IP addreses found */
-} mdns_result_t;
-
-/**
- * @brief  Initialize mDNS on given interface
- *
- * @return
- *     - ESP_OK on success
- *     - ESP_ERR_INVALID_ARG when bad tcpip_if is given
- *     - ESP_ERR_INVALID_STATE when the network returned error
- *     - ESP_ERR_NO_MEM on memory error
- *     - ESP_ERR_WIFI_NOT_INIT when WiFi is not initialized by eps_wifi_init
- */
-esp_err_t mdns_init();
-
-/**
- * @brief  Stop and free mDNS server
- *
- */
-void mdns_free();
-
-/**
- * @brief  Set the hostname for mDNS server
- *         required if you want to advertise services
- *
- * @param  hostname     Hostname to set
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NO_MEM memory error
- */
-esp_err_t mdns_hostname_set(const char * hostname);
-
-/**
- * @brief  Set the default instance name for mDNS server
- *
- * @param  instance_name     Instance name to set
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NO_MEM memory error
- */
-esp_err_t mdns_instance_name_set(const char * instance_name);
-
-/**
- * @brief  Add service to mDNS server
- *
- * @param  instance_name    instance name to set. If NULL,
- *                          global instance name or hostname will be used
- * @param  service_type     service type (_http, _ftp, etc)
- * @param  proto            service protocol (_tcp, _udp)
- * @param  port             service port
- * @param  num_items        number of items in TXT data
- * @param  txt              string array of TXT data (eg. {{"var","val"},{"other","2"}})
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NO_MEM memory error
- */
-esp_err_t mdns_service_add(const char * instance_name, const char * service_type, const char * proto, uint16_t port, mdns_txt_item_t txt[], size_t num_items);
-
-/**
- * @brief  Remove service from mDNS server
- *
- * @param  service_type service type (_http, _ftp, etc)
- * @param  proto        service protocol (_tcp, _udp)
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NOT_FOUND Service not found
- *     - ESP_FAIL unknown error
- */
-esp_err_t mdns_service_remove(const char * service_type, const char * proto);
-
-/**
- * @brief  Set instance name for service
- *
- * @param  service_type     service type (_http, _ftp, etc)
- * @param  proto            service protocol (_tcp, _udp)
- * @param  instance_name    instance name to set
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NOT_FOUND Service not found
- *     - ESP_ERR_NO_MEM memory error
- */
-esp_err_t mdns_service_instance_name_set(const char * service_type, const char * proto, const char * instance_name);
-
-/**
- * @brief  Set service port
- *
- * @param  service_type service type (_http, _ftp, etc)
- * @param  proto        service protocol (_tcp, _udp)
- * @param  port         service port
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NOT_FOUND Service not found
- */
-esp_err_t mdns_service_port_set(const char * service_type, const char * proto, uint16_t port);
-
-/**
- * @brief  Replace all TXT items for service
- *
- * @param  service_type service type (_http, _ftp, etc)
- * @param  proto        service protocol (_tcp, _udp)
- * @param  num_items    number of items in TXT data
- * @param  txt          array of TXT data (eg. {{"var","val"},{"other","2"}})
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NOT_FOUND Service not found
- *     - ESP_ERR_NO_MEM memory error
- */
-esp_err_t mdns_service_txt_set(const char * service_type, const char * proto, mdns_txt_item_t txt[], uint8_t num_items);
-
-/**
- * @brief  Set/Add TXT item for service TXT record
- *
- * @param  service_type service type (_http, _ftp, etc)
- * @param  proto        service protocol (_tcp, _udp)
- * @param  key          the key that you want to add/update
- * @param  value        the new value of the key
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NOT_FOUND Service not found
- *     - ESP_ERR_NO_MEM memory error
- */
-esp_err_t mdns_service_txt_item_set(const char * service_type, const char * proto, const char * key, const char * value);
-
-/**
- * @brief  Remove TXT item for service TXT record
- *
- * @param  service_type service type (_http, _ftp, etc)
- * @param  proto        service protocol (_tcp, _udp)
- * @param  key          the key that you want to remove
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- *     - ESP_ERR_NOT_FOUND Service not found
- *     - ESP_ERR_NO_MEM memory error
- */
-esp_err_t mdns_service_txt_item_remove(const char * service_type, const char * proto, const char * key);
-
-/**
- * @brief  Remove and free all services from mDNS server
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_ARG Parameter error
- */
-esp_err_t mdns_service_remove_all();
-
-/**
- * @brief  Query mDNS for host or service
- *         All following query methods are derived from this one
- *
- * @param  name         service instance or host name (NULL for PTR queries)
- * @param  service_type service type (_http, _arduino, _ftp etc.) (NULL for host queries)
- * @param  proto        service protocol (_tcp, _udp, etc.) (NULL for host queries)
- * @param  type         type of query (MDNS_TYPE_*)
- * @param  timeout      time in milliseconds to wait for answers.
- * @param  max_results  maximum results to be collected
- * @param  results      pointer to the results of the query
- *                      results must be freed using mdns_query_results_free below
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_STATE  mDNS is not running
- *     - ESP_ERR_NO_MEM         memory error
- *     - ESP_ERR_INVALID_ARG    timeout was not given
- */
-esp_err_t mdns_query(const char * name, const char * service_type, const char * proto, uint16_t type, uint32_t timeout, size_t max_results, mdns_result_t ** results);
-
-/**
- * @brief  Free query results
- *
- * @param  results      linked list of results to be freed
- */
-void mdns_query_results_free(mdns_result_t * results);
-
-/**
- * @brief  Query mDNS for service
- *
- * @param  service_type service type (_http, _arduino, _ftp etc.)
- * @param  proto        service protocol (_tcp, _udp, etc.)
- * @param  timeout      time in milliseconds to wait for answer.
- * @param  max_results  maximum results to be collected
- * @param  results      pointer to the results of the query
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_STATE  mDNS is not running
- *     - ESP_ERR_NO_MEM         memory error
- *     - ESP_ERR_INVALID_ARG    parameter error
- */
-esp_err_t mdns_query_ptr(const char * service_type, const char * proto, uint32_t timeout, size_t max_results, mdns_result_t ** results);
-
-/**
- * @brief  Query mDNS for SRV record
- *
- * @param  instance_name    service instance name
- * @param  service_type     service type (_http, _arduino, _ftp etc.)
- * @param  proto            service protocol (_tcp, _udp, etc.)
- * @param  timeout          time in milliseconds to wait for answer.
- * @param  result           pointer to the result of the query
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_STATE  mDNS is not running
- *     - ESP_ERR_NO_MEM         memory error
- *     - ESP_ERR_INVALID_ARG    parameter error
- */
-esp_err_t mdns_query_srv(const char * instance_name, const char * service_type, const char * proto, uint32_t timeout, mdns_result_t ** result);
-
-/**
- * @brief  Query mDNS for TXT record
- *
- * @param  instance_name    service instance name
- * @param  service_type     service type (_http, _arduino, _ftp etc.)
- * @param  proto            service protocol (_tcp, _udp, etc.)
- * @param  timeout          time in milliseconds to wait for answer.
- * @param  result           pointer to the result of the query
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_STATE  mDNS is not running
- *     - ESP_ERR_NO_MEM         memory error
- *     - ESP_ERR_INVALID_ARG    parameter error
- */
-esp_err_t mdns_query_txt(const char * instance_name, const char * service_type, const char * proto, uint32_t timeout, mdns_result_t ** result);
-
-/**
- * @brief  Query mDNS for A record
- *
- * @param  host_name    host name to look for
- * @param  timeout      time in milliseconds to wait for answer.
- * @param  addr         pointer to the resulting IP4 address
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_STATE  mDNS is not running
- *     - ESP_ERR_NO_MEM         memory error
- *     - ESP_ERR_INVALID_ARG    parameter error
- */
-esp_err_t mdns_query_a(const char * host_name, uint32_t timeout, ip4_addr_t * addr);
-
-/**
- * @brief  Query mDNS for A record
- *
- * @param  host_name    host name to look for
- * @param  timeout      time in milliseconds to wait for answer. If 0, max_results needs to be defined
- * @param  addr         pointer to the resulting IP6 address
- *
- * @return
- *     - ESP_OK success
- *     - ESP_ERR_INVALID_STATE  mDNS is not running
- *     - ESP_ERR_NO_MEM         memory error
- *     - ESP_ERR_INVALID_ARG    parameter error
- */
-esp_err_t mdns_query_aaaa(const char * host_name, uint32_t timeout, ip6_addr_t * addr);
-
-/**
- * @brief   System event handler
- *          This method controls the service state on all active interfaces and applications are required
- *          to call it from the system event handler for normal operation of mDNS service.
- *
- * @param  ctx          The system event context
- * @param  event        The system event
- */
-esp_err_t mdns_handle_system_event(void *ctx, system_event_t *event);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ESP_MDNS_H_ */
diff --git a/tools/sdk/include/mdns/mdns_console.h b/tools/sdk/include/mdns/mdns_console.h
deleted file mode 100644
index 5c8b0b5a49e..00000000000
--- a/tools/sdk/include/mdns/mdns_console.h
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _MDNS_CONSOLE_H_
-#define _MDNS_CONSOLE_H_
-
-/**
- * @brief  Register MDNS functions with the console component
- */
-void mdns_console_register();
-
-#endif /* _MDNS_CONSOLE_H_ */
diff --git a/tools/sdk/include/micro-ecc/types.h b/tools/sdk/include/micro-ecc/types.h
deleted file mode 100644
index 9ee81438fac..00000000000
--- a/tools/sdk/include/micro-ecc/types.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* Copyright 2015, Kenneth MacKay. Licensed under the BSD 2-clause license. */
-
-#ifndef _UECC_TYPES_H_
-#define _UECC_TYPES_H_
-
-#ifndef uECC_PLATFORM
-    #if __AVR__
-        #define uECC_PLATFORM uECC_avr
-    #elif defined(__thumb2__) || defined(_M_ARMT) /* I think MSVC only supports Thumb-2 targets */
-        #define uECC_PLATFORM uECC_arm_thumb2
-    #elif defined(__thumb__)
-        #define uECC_PLATFORM uECC_arm_thumb
-    #elif defined(__arm__) || defined(_M_ARM)
-        #define uECC_PLATFORM uECC_arm
-    #elif defined(__aarch64__)
-        #define uECC_PLATFORM uECC_arm64
-    #elif defined(__i386__) || defined(_M_IX86) || defined(_X86_) || defined(__I86__)
-        #define uECC_PLATFORM uECC_x86
-    #elif defined(__amd64__) || defined(_M_X64)
-        #define uECC_PLATFORM uECC_x86_64
-    #else
-        #define uECC_PLATFORM uECC_arch_other
-    #endif
-#endif
-
-#ifndef uECC_ARM_USE_UMAAL
-    #if (uECC_PLATFORM == uECC_arm) && (__ARM_ARCH >= 6)
-        #define uECC_ARM_USE_UMAAL 1
-    #elif (uECC_PLATFORM == uECC_arm_thumb2) && (__ARM_ARCH >= 6) && !__ARM_ARCH_7M__
-        #define uECC_ARM_USE_UMAAL 1
-    #else
-        #define uECC_ARM_USE_UMAAL 0
-    #endif
-#endif
-
-#ifndef uECC_WORD_SIZE
-    #if uECC_PLATFORM == uECC_avr
-        #define uECC_WORD_SIZE 1
-    #elif (uECC_PLATFORM == uECC_x86_64 || uECC_PLATFORM == uECC_arm64)
-        #define uECC_WORD_SIZE 8
-    #else
-        #define uECC_WORD_SIZE 4
-    #endif
-#endif
-
-#if (uECC_WORD_SIZE != 1) && (uECC_WORD_SIZE != 4) && (uECC_WORD_SIZE != 8)
-    #error "Unsupported value for uECC_WORD_SIZE"
-#endif
-
-#if ((uECC_PLATFORM == uECC_avr) && (uECC_WORD_SIZE != 1))
-    #pragma message ("uECC_WORD_SIZE must be 1 for AVR")
-    #undef uECC_WORD_SIZE
-    #define uECC_WORD_SIZE 1
-#endif
-
-#if ((uECC_PLATFORM == uECC_arm || uECC_PLATFORM == uECC_arm_thumb || \
-        uECC_PLATFORM ==  uECC_arm_thumb2) && \
-     (uECC_WORD_SIZE != 4))
-    #pragma message ("uECC_WORD_SIZE must be 4 for ARM")
-    #undef uECC_WORD_SIZE
-    #define uECC_WORD_SIZE 4
-#endif
-
-#if defined(__SIZEOF_INT128__) || ((__clang_major__ * 100 + __clang_minor__) >= 302)
-    #define SUPPORTS_INT128 1
-#else
-    #define SUPPORTS_INT128 0
-#endif
-
-typedef int8_t wordcount_t;
-typedef int16_t bitcount_t;
-typedef int8_t cmpresult_t;
-
-#if (uECC_WORD_SIZE == 1)
-
-typedef uint8_t uECC_word_t;
-typedef uint16_t uECC_dword_t;
-
-#define HIGH_BIT_SET 0x80
-#define uECC_WORD_BITS 8
-#define uECC_WORD_BITS_SHIFT 3
-#define uECC_WORD_BITS_MASK 0x07
-
-#elif (uECC_WORD_SIZE == 4)
-
-typedef uint32_t uECC_word_t;
-typedef uint64_t uECC_dword_t;
-
-#define HIGH_BIT_SET 0x80000000
-#define uECC_WORD_BITS 32
-#define uECC_WORD_BITS_SHIFT 5
-#define uECC_WORD_BITS_MASK 0x01F
-
-#elif (uECC_WORD_SIZE == 8)
-
-typedef uint64_t uECC_word_t;
-#if SUPPORTS_INT128
-typedef unsigned __int128 uECC_dword_t;
-#endif
-
-#define HIGH_BIT_SET 0x8000000000000000ull
-#define uECC_WORD_BITS 64
-#define uECC_WORD_BITS_SHIFT 6
-#define uECC_WORD_BITS_MASK 0x03F
-
-#endif /* uECC_WORD_SIZE */
-
-#endif /* _UECC_TYPES_H_ */
diff --git a/tools/sdk/include/micro-ecc/uECC.h b/tools/sdk/include/micro-ecc/uECC.h
deleted file mode 100644
index 43a19d63cb2..00000000000
--- a/tools/sdk/include/micro-ecc/uECC.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/* Copyright 2014, Kenneth MacKay. Licensed under the BSD 2-clause license. */
-
-#ifndef _UECC_H_
-#define _UECC_H_
-
-#include <stdint.h>
-
-/* Platform selection options.
-If uECC_PLATFORM is not defined, the code will try to guess it based on compiler macros.
-Possible values for uECC_PLATFORM are defined below: */
-#define uECC_arch_other 0
-#define uECC_x86        1
-#define uECC_x86_64     2
-#define uECC_arm        3
-#define uECC_arm_thumb  4
-#define uECC_arm_thumb2 5
-#define uECC_arm64      6
-#define uECC_avr        7
-
-/* If desired, you can define uECC_WORD_SIZE as appropriate for your platform (1, 4, or 8 bytes).
-If uECC_WORD_SIZE is not explicitly defined then it will be automatically set based on your
-platform. */
-
-/* Optimization level; trade speed for code size.
-   Larger values produce code that is faster but larger.
-   Currently supported values are 0 - 4; 0 is unusably slow for most applications.
-   Optimization level 4 currently only has an effect ARM platforms where more than one
-   curve is enabled. */
-#ifndef uECC_OPTIMIZATION_LEVEL
-    #define uECC_OPTIMIZATION_LEVEL 2
-#endif
-
-/* uECC_SQUARE_FUNC - If enabled (defined as nonzero), this will cause a specific function to be
-used for (scalar) squaring instead of the generic multiplication function. This can make things
-faster somewhat faster, but increases the code size. */
-#ifndef uECC_SQUARE_FUNC
-    #define uECC_SQUARE_FUNC 0
-#endif
-
-/* uECC_VLI_NATIVE_LITTLE_ENDIAN - If enabled (defined as nonzero), this will switch to native
-little-endian format for *all* arrays passed in and out of the public API. This includes public 
-and private keys, shared secrets, signatures and message hashes. 
-Using this switch reduces the amount of call stack memory used by uECC, since less intermediate
-translations are required. 
-Note that this will *only* work on native little-endian processors and it will treat the uint8_t
-arrays passed into the public API as word arrays, therefore requiring the provided byte arrays 
-to be word aligned on architectures that do not support unaligned accesses.
-IMPORTANT: Keys and signatures generated with uECC_VLI_NATIVE_LITTLE_ENDIAN=1 are incompatible
-with keys and signatures generated with uECC_VLI_NATIVE_LITTLE_ENDIAN=0; all parties must use
-the same endianness. */
-#ifndef uECC_VLI_NATIVE_LITTLE_ENDIAN
-    #define uECC_VLI_NATIVE_LITTLE_ENDIAN 0
-#endif
-
-/* Curve support selection. Set to 0 to remove that curve. */
-#ifndef uECC_SUPPORTS_secp160r1
-    #define uECC_SUPPORTS_secp160r1 1
-#endif
-#ifndef uECC_SUPPORTS_secp192r1
-    #define uECC_SUPPORTS_secp192r1 1
-#endif
-#ifndef uECC_SUPPORTS_secp224r1
-    #define uECC_SUPPORTS_secp224r1 1
-#endif
-#ifndef uECC_SUPPORTS_secp256r1
-    #define uECC_SUPPORTS_secp256r1 1
-#endif
-#ifndef uECC_SUPPORTS_secp256k1
-    #define uECC_SUPPORTS_secp256k1 1
-#endif
-
-/* Specifies whether compressed point format is supported.
-   Set to 0 to disable point compression/decompression functions. */
-#ifndef uECC_SUPPORT_COMPRESSED_POINT
-    #define uECC_SUPPORT_COMPRESSED_POINT 1
-#endif
-
-struct uECC_Curve_t;
-typedef const struct uECC_Curve_t * uECC_Curve;
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#if uECC_SUPPORTS_secp160r1
-uECC_Curve uECC_secp160r1(void);
-#endif
-#if uECC_SUPPORTS_secp192r1
-uECC_Curve uECC_secp192r1(void);
-#endif
-#if uECC_SUPPORTS_secp224r1
-uECC_Curve uECC_secp224r1(void);
-#endif
-#if uECC_SUPPORTS_secp256r1
-uECC_Curve uECC_secp256r1(void);
-#endif
-#if uECC_SUPPORTS_secp256k1
-uECC_Curve uECC_secp256k1(void);
-#endif
-
-/* uECC_RNG_Function type
-The RNG function should fill 'size' random bytes into 'dest'. It should return 1 if
-'dest' was filled with random data, or 0 if the random data could not be generated.
-The filled-in values should be either truly random, or from a cryptographically-secure PRNG.
-
-A correctly functioning RNG function must be set (using uECC_set_rng()) before calling
-uECC_make_key() or uECC_sign().
-
-Setting a correctly functioning RNG function improves the resistance to side-channel attacks
-for uECC_shared_secret() and uECC_sign_deterministic().
-
-A correct RNG function is set by default when building for Windows, Linux, or OS X.
-If you are building on another POSIX-compliant system that supports /dev/random or /dev/urandom,
-you can define uECC_POSIX to use the predefined RNG. For embedded platforms there is no predefined
-RNG function; you must provide your own.
-*/
-typedef int (*uECC_RNG_Function)(uint8_t *dest, unsigned size);
-
-/* uECC_set_rng() function.
-Set the function that will be used to generate random bytes. The RNG function should
-return 1 if the random data was generated, or 0 if the random data could not be generated.
-
-On platforms where there is no predefined RNG function (eg embedded platforms), this must
-be called before uECC_make_key() or uECC_sign() are used.
-
-Inputs:
-    rng_function - The function that will be used to generate random bytes.
-*/
-void uECC_set_rng(uECC_RNG_Function rng_function);
-
-/* uECC_get_rng() function.
-
-Returns the function that will be used to generate random bytes.
-*/
-uECC_RNG_Function uECC_get_rng(void);
-
-/* uECC_curve_private_key_size() function.
-
-Returns the size of a private key for the curve in bytes.
-*/
-int uECC_curve_private_key_size(uECC_Curve curve);
-
-/* uECC_curve_public_key_size() function.
-
-Returns the size of a public key for the curve in bytes.
-*/
-int uECC_curve_public_key_size(uECC_Curve curve);
-
-/* uECC_make_key() function.
-Create a public/private key pair.
-
-Outputs:
-    public_key  - Will be filled in with the public key. Must be at least 2 * the curve size
-                  (in bytes) long. For example, if the curve is secp256r1, public_key must be 64
-                  bytes long.
-    private_key - Will be filled in with the private key. Must be as long as the curve order; this
-                  is typically the same as the curve size, except for secp160r1. For example, if the
-                  curve is secp256r1, private_key must be 32 bytes long.
-
-                  For secp160r1, private_key must be 21 bytes long! Note that the first byte will
-                  almost always be 0 (there is about a 1 in 2^80 chance of it being non-zero).
-
-Returns 1 if the key pair was generated successfully, 0 if an error occurred.
-*/
-int uECC_make_key(uint8_t *public_key, uint8_t *private_key, uECC_Curve curve);
-
-/* uECC_shared_secret() function.
-Compute a shared secret given your secret key and someone else's public key.
-Note: It is recommended that you hash the result of uECC_shared_secret() before using it for
-symmetric encryption or HMAC.
-
-Inputs:
-    public_key  - The public key of the remote party.
-    private_key - Your private key.
-
-Outputs:
-    secret - Will be filled in with the shared secret value. Must be the same size as the
-             curve size; for example, if the curve is secp256r1, secret must be 32 bytes long.
-
-Returns 1 if the shared secret was generated successfully, 0 if an error occurred.
-*/
-int uECC_shared_secret(const uint8_t *public_key,
-                       const uint8_t *private_key,
-                       uint8_t *secret,
-                       uECC_Curve curve);
-
-#if uECC_SUPPORT_COMPRESSED_POINT
-/* uECC_compress() function.
-Compress a public key.
-
-Inputs:
-    public_key - The public key to compress.
-
-Outputs:
-    compressed - Will be filled in with the compressed public key. Must be at least
-                 (curve size + 1) bytes long; for example, if the curve is secp256r1,
-                 compressed must be 33 bytes long.
-*/
-void uECC_compress(const uint8_t *public_key, uint8_t *compressed, uECC_Curve curve);
-
-/* uECC_decompress() function.
-Decompress a compressed public key.
-
-Inputs:
-    compressed - The compressed public key.
-
-Outputs:
-    public_key - Will be filled in with the decompressed public key.
-*/
-void uECC_decompress(const uint8_t *compressed, uint8_t *public_key, uECC_Curve curve);
-#endif /* uECC_SUPPORT_COMPRESSED_POINT */
-
-/* uECC_valid_public_key() function.
-Check to see if a public key is valid.
-
-Note that you are not required to check for a valid public key before using any other uECC
-functions. However, you may wish to avoid spending CPU time computing a shared secret or
-verifying a signature using an invalid public key.
-
-Inputs:
-    public_key - The public key to check.
-
-Returns 1 if the public key is valid, 0 if it is invalid.
-*/
-int uECC_valid_public_key(const uint8_t *public_key, uECC_Curve curve);
-
-/* uECC_compute_public_key() function.
-Compute the corresponding public key for a private key.
-
-Inputs:
-    private_key - The private key to compute the public key for
-
-Outputs:
-    public_key - Will be filled in with the corresponding public key
-
-Returns 1 if the key was computed successfully, 0 if an error occurred.
-*/
-int uECC_compute_public_key(const uint8_t *private_key, uint8_t *public_key, uECC_Curve curve);
-
-/* uECC_sign() function.
-Generate an ECDSA signature for a given hash value.
-
-Usage: Compute a hash of the data you wish to sign (SHA-2 is recommended) and pass it in to
-this function along with your private key.
-
-Inputs:
-    private_key  - Your private key.
-    message_hash - The hash of the message to sign.
-    hash_size    - The size of message_hash in bytes.
-
-Outputs:
-    signature - Will be filled in with the signature value. Must be at least 2 * curve size long.
-                For example, if the curve is secp256r1, signature must be 64 bytes long.
-
-Returns 1 if the signature generated successfully, 0 if an error occurred.
-*/
-int uECC_sign(const uint8_t *private_key,
-              const uint8_t *message_hash,
-              unsigned hash_size,
-              uint8_t *signature,
-              uECC_Curve curve);
-
-/* uECC_HashContext structure.
-This is used to pass in an arbitrary hash function to uECC_sign_deterministic().
-The structure will be used for multiple hash computations; each time a new hash
-is computed, init_hash() will be called, followed by one or more calls to
-update_hash(), and finally a call to finish_hash() to produce the resulting hash.
-
-The intention is that you will create a structure that includes uECC_HashContext
-followed by any hash-specific data. For example:
-
-typedef struct SHA256_HashContext {
-    uECC_HashContext uECC;
-    SHA256_CTX ctx;
-} SHA256_HashContext;
-
-void init_SHA256(uECC_HashContext *base) {
-    SHA256_HashContext *context = (SHA256_HashContext *)base;
-    SHA256_Init(&context->ctx);
-}
-
-void update_SHA256(uECC_HashContext *base,
-                   const uint8_t *message,
-                   unsigned message_size) {
-    SHA256_HashContext *context = (SHA256_HashContext *)base;
-    SHA256_Update(&context->ctx, message, message_size);
-}
-
-void finish_SHA256(uECC_HashContext *base, uint8_t *hash_result) {
-    SHA256_HashContext *context = (SHA256_HashContext *)base;
-    SHA256_Final(hash_result, &context->ctx);
-}
-
-... when signing ...
-{
-    uint8_t tmp[32 + 32 + 64];
-    SHA256_HashContext ctx = {{&init_SHA256, &update_SHA256, &finish_SHA256, 64, 32, tmp}};
-    uECC_sign_deterministic(key, message_hash, &ctx.uECC, signature);
-}
-*/
-typedef struct uECC_HashContext {
-    void (*init_hash)(const struct uECC_HashContext *context);
-    void (*update_hash)(const struct uECC_HashContext *context,
-                        const uint8_t *message,
-                        unsigned message_size);
-    void (*finish_hash)(const struct uECC_HashContext *context, uint8_t *hash_result);
-    unsigned block_size; /* Hash function block size in bytes, eg 64 for SHA-256. */
-    unsigned result_size; /* Hash function result size in bytes, eg 32 for SHA-256. */
-    uint8_t *tmp; /* Must point to a buffer of at least (2 * result_size + block_size) bytes. */
-} uECC_HashContext;
-
-/* uECC_sign_deterministic() function.
-Generate an ECDSA signature for a given hash value, using a deterministic algorithm
-(see RFC 6979). You do not need to set the RNG using uECC_set_rng() before calling
-this function; however, if the RNG is defined it will improve resistance to side-channel
-attacks.
-
-Usage: Compute a hash of the data you wish to sign (SHA-2 is recommended) and pass it to
-this function along with your private key and a hash context. Note that the message_hash
-does not need to be computed with the same hash function used by hash_context.
-
-Inputs:
-    private_key  - Your private key.
-    message_hash - The hash of the message to sign.
-    hash_size    - The size of message_hash in bytes.
-    hash_context - A hash context to use.
-
-Outputs:
-    signature - Will be filled in with the signature value.
-
-Returns 1 if the signature generated successfully, 0 if an error occurred.
-*/
-int uECC_sign_deterministic(const uint8_t *private_key,
-                            const uint8_t *message_hash,
-                            unsigned hash_size,
-                            const uECC_HashContext *hash_context,
-                            uint8_t *signature,
-                            uECC_Curve curve);
-
-/* uECC_verify() function.
-Verify an ECDSA signature.
-
-Usage: Compute the hash of the signed data using the same hash as the signer and
-pass it to this function along with the signer's public key and the signature values (r and s).
-
-Inputs:
-    public_key   - The signer's public key.
-    message_hash - The hash of the signed data.
-    hash_size    - The size of message_hash in bytes.
-    signature    - The signature value.
-
-Returns 1 if the signature is valid, 0 if it is invalid.
-*/
-int uECC_verify(const uint8_t *public_key,
-                const uint8_t *message_hash,
-                unsigned hash_size,
-                const uint8_t *signature,
-                uECC_Curve curve);
-
-#ifdef __cplusplus
-} /* end of extern "C" */
-#endif
-
-#endif /* _UECC_H_ */
diff --git a/tools/sdk/include/micro-ecc/uECC_vli.h b/tools/sdk/include/micro-ecc/uECC_vli.h
deleted file mode 100644
index 864cc333569..00000000000
--- a/tools/sdk/include/micro-ecc/uECC_vli.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* Copyright 2015, Kenneth MacKay. Licensed under the BSD 2-clause license. */
-
-#ifndef _UECC_VLI_H_
-#define _UECC_VLI_H_
-
-#include "uECC.h"
-#include "types.h"
-
-/* Functions for raw large-integer manipulation. These are only available
-   if uECC.c is compiled with uECC_ENABLE_VLI_API defined to 1. */
-#ifndef uECC_ENABLE_VLI_API
-    #define uECC_ENABLE_VLI_API 0
-#endif
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#if uECC_ENABLE_VLI_API
-
-void uECC_vli_clear(uECC_word_t *vli, wordcount_t num_words);
-
-/* Constant-time comparison to zero - secure way to compare long integers */
-/* Returns 1 if vli == 0, 0 otherwise. */
-uECC_word_t uECC_vli_isZero(const uECC_word_t *vli, wordcount_t num_words);
-
-/* Returns nonzero if bit 'bit' of vli is set. */
-uECC_word_t uECC_vli_testBit(const uECC_word_t *vli, bitcount_t bit);
-
-/* Counts the number of bits required to represent vli. */
-bitcount_t uECC_vli_numBits(const uECC_word_t *vli, const wordcount_t max_words);
-
-/* Sets dest = src. */
-void uECC_vli_set(uECC_word_t *dest, const uECC_word_t *src, wordcount_t num_words);
-
-/* Constant-time comparison function - secure way to compare long integers */
-/* Returns one if left == right, zero otherwise */
-uECC_word_t uECC_vli_equal(const uECC_word_t *left,
-                           const uECC_word_t *right,
-                           wordcount_t num_words);
-
-/* Constant-time comparison function - secure way to compare long integers */
-/* Returns sign of left - right, in constant time. */
-cmpresult_t uECC_vli_cmp(const uECC_word_t *left, const uECC_word_t *right, wordcount_t num_words);
-
-/* Computes vli = vli >> 1. */
-void uECC_vli_rshift1(uECC_word_t *vli, wordcount_t num_words);
-
-/* Computes result = left + right, returning carry. Can modify in place. */
-uECC_word_t uECC_vli_add(uECC_word_t *result,
-                         const uECC_word_t *left,
-                         const uECC_word_t *right,
-                         wordcount_t num_words);
-
-/* Computes result = left - right, returning borrow. Can modify in place. */
-uECC_word_t uECC_vli_sub(uECC_word_t *result,
-                         const uECC_word_t *left,
-                         const uECC_word_t *right,
-                         wordcount_t num_words);
-
-/* Computes result = left * right. Result must be 2 * num_words long. */
-void uECC_vli_mult(uECC_word_t *result,
-                   const uECC_word_t *left,
-                   const uECC_word_t *right,
-                   wordcount_t num_words);
-
-/* Computes result = left^2. Result must be 2 * num_words long. */
-void uECC_vli_square(uECC_word_t *result, const uECC_word_t *left, wordcount_t num_words);
-
-/* Computes result = (left + right) % mod.
-   Assumes that left < mod and right < mod, and that result does not overlap mod. */
-void uECC_vli_modAdd(uECC_word_t *result,
-                     const uECC_word_t *left,
-                     const uECC_word_t *right,
-                     const uECC_word_t *mod,
-                     wordcount_t num_words);
-
-/* Computes result = (left - right) % mod.
-   Assumes that left < mod and right < mod, and that result does not overlap mod. */
-void uECC_vli_modSub(uECC_word_t *result,
-                     const uECC_word_t *left,
-                     const uECC_word_t *right,
-                     const uECC_word_t *mod,
-                     wordcount_t num_words);
-
-/* Computes result = product % mod, where product is 2N words long.
-   Currently only designed to work for mod == curve->p or curve_n. */
-void uECC_vli_mmod(uECC_word_t *result,
-                   uECC_word_t *product,
-                   const uECC_word_t *mod,
-                   wordcount_t num_words);
-
-/* Calculates result = product (mod curve->p), where product is up to
-   2 * curve->num_words long. */
-void uECC_vli_mmod_fast(uECC_word_t *result, uECC_word_t *product, uECC_Curve curve);
-
-/* Computes result = (left * right) % mod.
-   Currently only designed to work for mod == curve->p or curve_n. */
-void uECC_vli_modMult(uECC_word_t *result,
-                      const uECC_word_t *left,
-                      const uECC_word_t *right,
-                      const uECC_word_t *mod,
-                      wordcount_t num_words);
-
-/* Computes result = (left * right) % curve->p. */
-void uECC_vli_modMult_fast(uECC_word_t *result,
-                           const uECC_word_t *left,
-                           const uECC_word_t *right,
-                           uECC_Curve curve);
-
-/* Computes result = left^2 % mod.
-   Currently only designed to work for mod == curve->p or curve_n. */
-void uECC_vli_modSquare(uECC_word_t *result,
-                        const uECC_word_t *left,
-                        const uECC_word_t *mod,
-                        wordcount_t num_words);
-
-/* Computes result = left^2 % curve->p. */
-void uECC_vli_modSquare_fast(uECC_word_t *result, const uECC_word_t *left, uECC_Curve curve);
-
-/* Computes result = (1 / input) % mod.*/
-void uECC_vli_modInv(uECC_word_t *result,
-                     const uECC_word_t *input,
-                     const uECC_word_t *mod,
-                     wordcount_t num_words);
-
-#if uECC_SUPPORT_COMPRESSED_POINT
-/* Calculates a = sqrt(a) (mod curve->p) */
-void uECC_vli_mod_sqrt(uECC_word_t *a, uECC_Curve curve);
-#endif
-
-/* Converts an integer in uECC native format to big-endian bytes. */
-void uECC_vli_nativeToBytes(uint8_t *bytes, int num_bytes, const uECC_word_t *native);
-/* Converts big-endian bytes to an integer in uECC native format. */
-void uECC_vli_bytesToNative(uECC_word_t *native, const uint8_t *bytes, int num_bytes);
-
-unsigned uECC_curve_num_words(uECC_Curve curve);
-unsigned uECC_curve_num_bytes(uECC_Curve curve);
-unsigned uECC_curve_num_bits(uECC_Curve curve);
-unsigned uECC_curve_num_n_words(uECC_Curve curve);
-unsigned uECC_curve_num_n_bytes(uECC_Curve curve);
-unsigned uECC_curve_num_n_bits(uECC_Curve curve);
-
-const uECC_word_t *uECC_curve_p(uECC_Curve curve);
-const uECC_word_t *uECC_curve_n(uECC_Curve curve);
-const uECC_word_t *uECC_curve_G(uECC_Curve curve);
-const uECC_word_t *uECC_curve_b(uECC_Curve curve);
-
-int uECC_valid_point(const uECC_word_t *point, uECC_Curve curve);
-
-/* Multiplies a point by a scalar. Points are represented by the X coordinate followed by
-   the Y coordinate in the same array, both coordinates are curve->num_words long. Note
-   that scalar must be curve->num_n_words long (NOT curve->num_words). */
-void uECC_point_mult(uECC_word_t *result,
-                     const uECC_word_t *point,
-                     const uECC_word_t *scalar,
-                     uECC_Curve curve);
-
-/* Generates a random integer in the range 0 < random < top.
-   Both random and top have num_words words. */
-int uECC_generate_random_int(uECC_word_t *random,
-                             const uECC_word_t *top,
-                             wordcount_t num_words);
-
-#endif /* uECC_ENABLE_VLI_API */
-
-#ifdef __cplusplus
-} /* end of extern "C" */
-#endif
-
-#endif /* _UECC_VLI_H_ */
diff --git a/tools/sdk/include/mqtt/mqtt_client.h b/tools/sdk/include/mqtt/mqtt_client.h
deleted file mode 100644
index e365cb8463c..00000000000
--- a/tools/sdk/include/mqtt/mqtt_client.h
+++ /dev/null
@@ -1,354 +0,0 @@
-/*
- * This file is subject to the terms and conditions defined in
- * file 'LICENSE', which is part of this source code package.
- * Tuan PM <tuanpm at live dot com>
- */
-
-#ifndef _MQTT_CLIENT_H_
-#define _MQTT_CLIENT_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <string.h>
-#include "esp_err.h"
-
-#include "mqtt_config.h"
-#include "esp_event.h"
-#if CONFIG_ESP_TLS_USE_DS_PERIPHERAL
-#include "rsa_sign_alt.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef ESP_EVENT_DECLARE_BASE
-// Define event loop types if macros not available
-typedef void * esp_event_loop_handle_t;
-typedef void * esp_event_handler_t;
-#endif
-
-typedef struct esp_mqtt_client *esp_mqtt_client_handle_t;
-
-/**
- * @brief MQTT event types.
- *
- * User event handler receives context data in `esp_mqtt_event_t` structure with
- *  - `user_context` - user data from `esp_mqtt_client_config_t`
- *  - `client` - mqtt client handle
- *  - various other data depending on event type
- *
- */
-typedef enum {
-    MQTT_EVENT_ANY = -1,
-    MQTT_EVENT_ERROR = 0,          /*!< on error event, additional context: connection return code, error handle from esp_tls (if supported) */
-    MQTT_EVENT_CONNECTED,          /*!< connected event, additional context: session_present flag */
-    MQTT_EVENT_DISCONNECTED,       /*!< disconnected event */
-    MQTT_EVENT_SUBSCRIBED,         /*!< subscribed event, additional context: msg_id */
-    MQTT_EVENT_UNSUBSCRIBED,       /*!< unsubscribed event */
-    MQTT_EVENT_PUBLISHED,          /*!< published event, additional context:  msg_id */
-    MQTT_EVENT_DATA,               /*!< data event, additional context:
-                                        - msg_id               message id
-                                        - topic                pointer to the received topic
-                                        - topic_len            length of the topic
-                                        - data                 pointer to the received data
-                                        - data_len             length of the data for this event
-                                        - current_data_offset  offset of the current data for this event
-                                        - total_data_len       total length of the data received
-                                        Note: Multiple MQTT_EVENT_DATA could be fired for one message, if it is
-                                        longer than internal buffer. In that case only first event contains topic
-                                        pointer and length, other contain data only with current data length
-                                        and current data offset updating.
-                                         */
-    MQTT_EVENT_BEFORE_CONNECT,     /*!< The event occurs before connecting */
-} esp_mqtt_event_id_t;
-
-/**
- * MQTT connection error codes propagated via ERROR event
- */
-typedef enum {
-    MQTT_CONNECTION_ACCEPTED = 0,                   /*!< Connection accepted  */
-    MQTT_CONNECTION_REFUSE_PROTOCOL,                /*!< MQTT connection refused reason: Wrong protocol */
-    MQTT_CONNECTION_REFUSE_ID_REJECTED,             /*!< MQTT connection refused reason: ID rejected */
-    MQTT_CONNECTION_REFUSE_SERVER_UNAVAILABLE,      /*!< MQTT connection refused reason: Server unavailable */
-    MQTT_CONNECTION_REFUSE_BAD_USERNAME,            /*!< MQTT connection refused reason: Wrong user */
-    MQTT_CONNECTION_REFUSE_NOT_AUTHORIZED           /*!< MQTT connection refused reason: Wrong username or password */
-} esp_mqtt_connect_return_code_t;
-
-/**
- * MQTT connection error codes propagated via ERROR event
- */
-typedef enum {
-    MQTT_ERROR_TYPE_NONE = 0,
-    MQTT_ERROR_TYPE_ESP_TLS,
-    MQTT_ERROR_TYPE_CONNECTION_REFUSED,
-} esp_mqtt_error_type_t;
-
-typedef enum {
-    MQTT_TRANSPORT_UNKNOWN = 0x0,
-    MQTT_TRANSPORT_OVER_TCP,      /*!< MQTT over TCP, using scheme: ``mqtt`` */
-    MQTT_TRANSPORT_OVER_SSL,      /*!< MQTT over SSL, using scheme: ``mqtts`` */
-    MQTT_TRANSPORT_OVER_WS,       /*!< MQTT over Websocket, using scheme:: ``ws`` */
-    MQTT_TRANSPORT_OVER_WSS       /*!< MQTT over Websocket Secure, using scheme: ``wss`` */
-} esp_mqtt_transport_t;
-
-/**
- *  MQTT protocol version used for connection
- */
-typedef enum {
-    MQTT_PROTOCOL_UNDEFINED = 0,
-    MQTT_PROTOCOL_V_3_1,
-    MQTT_PROTOCOL_V_3_1_1
-} esp_mqtt_protocol_ver_t;
-
-/**
- * @brief MQTT error code structure to be passed as a contextual information into ERROR event
- *
- * Important: This structure extends `esp_tls_last_error` error structure and is backward compatible with it
- * (so might be down-casted and treated as `esp_tls_last_error` error, but recommended to update applications if used this way previously)
- *
- * Use this structure directly checking error_type first and then appropriate error code depending on the source of the error:
- *
- * | error_type | related member variables | note |
- * | MQTT_ERROR_TYPE_ESP_TLS | esp_tls_last_esp_err, esp_tls_stack_err, esp_tls_cert_verify_flags | Error reported from esp-tls |
- * | MQTT_ERROR_TYPE_CONNECTION_REFUSED | connect_return_code | Internal error reported from MQTT broker on connection |
- */
-typedef struct esp_mqtt_error_codes {
-    /* compatible portion of the struct corresponding to struct esp_tls_last_error */
-    esp_err_t esp_tls_last_esp_err;              /*!< last esp_err code reported from esp-tls component */
-    int       esp_tls_stack_err;                 /*!< tls specific error code reported from underlying tls stack */
-    int       esp_tls_cert_verify_flags;         /*!< tls flags reported from underlying tls stack during certificate verification */
-    /* esp-mqtt specific structure extension */
-    esp_mqtt_error_type_t error_type;            /*!< error type referring to the source of the error */
-    esp_mqtt_connect_return_code_t connect_return_code; /*!< connection refused error code reported from MQTT broker on connection */
-} esp_mqtt_error_codes_t;
-
-/**
- * MQTT event configuration structure
- */
-typedef struct {
-    esp_mqtt_event_id_t event_id;       /*!< MQTT event type */
-    esp_mqtt_client_handle_t client;    /*!< MQTT client handle for this event */
-    void *user_context;                 /*!< User context passed from MQTT client config */
-    char *data;                         /*!< Data associated with this event */
-    int data_len;                       /*!< Length of the data for this event */
-    int total_data_len;                 /*!< Total length of the data (longer data are supplied with multiple events) */
-    int current_data_offset;            /*!< Actual offset for the data associated with this event */
-    char *topic;                        /*!< Topic associated with this event */
-    int topic_len;                      /*!< Length of the topic for this event associated with this event */
-    int msg_id;                         /*!< MQTT messaged id of message */
-    int session_present;                /*!< MQTT session_present flag for connection event */
-    esp_mqtt_error_codes_t *error_handle; /*!< esp-mqtt error handle including esp-tls errors as well as internal mqtt errors */
-} esp_mqtt_event_t;
-
-typedef esp_mqtt_event_t *esp_mqtt_event_handle_t;
-
-typedef esp_err_t (* mqtt_event_callback_t)(esp_mqtt_event_handle_t event);
-
-/**
- * MQTT client configuration structure
- */
-typedef struct {
-    mqtt_event_callback_t event_handle;     /*!< handle for MQTT events as a callback in legacy mode */
-    esp_event_loop_handle_t event_loop_handle; /*!< handle for MQTT event loop library */
-    const char *host;                       /*!< MQTT server domain (ipv4 as string) */
-    const char *uri;                        /*!< Complete MQTT broker URI */
-    uint32_t port;                          /*!< MQTT server port */
-    const char *client_id;                  /*!< default client id is ``ESP32_%CHIPID%`` where %CHIPID% are last 3 bytes of MAC address in hex format */
-    const char *username;                   /*!< MQTT username */
-    const char *password;                   /*!< MQTT password */
-    const char *lwt_topic;                  /*!< LWT (Last Will and Testament) message topic (NULL by default) */
-    const char *lwt_msg;                    /*!< LWT message (NULL by default) */
-    int lwt_qos;                            /*!< LWT message qos */
-    int lwt_retain;                         /*!< LWT retained message flag */
-    int lwt_msg_len;                        /*!< LWT message length */
-    int disable_clean_session;              /*!< mqtt clean session, default clean_session is true */
-    int keepalive;                          /*!< mqtt keepalive, default is 120 seconds */
-    bool disable_auto_reconnect;            /*!< this mqtt client will reconnect to server (when errors/disconnect). Set disable_auto_reconnect=true to disable */
-    void *user_context;                     /*!< pass user context to this option, then can receive that context in ``event->user_context`` */
-    int task_prio;                          /*!< MQTT task priority, default is 5, can be changed in ``make menuconfig`` */
-    int task_stack;                         /*!< MQTT task stack size, default is 6144 bytes, can be changed in ``make menuconfig`` */
-    int buffer_size;                        /*!< size of MQTT send/receive buffer, default is 1024 (only receive buffer size if ``out_buffer_size`` defined) */
-    const char *cert_pem;                   /*!< Pointer to certificate data in PEM or DER format for server verify (with SSL), default is NULL, not required to verify the server. PEM-format must have a terminating NULL-character. DER-format requires the length to be passed in cert_len. */
-    size_t cert_len;                        /*!< Length of the buffer pointed to by cert_pem. May be 0 for null-terminated pem */
-    const char *client_cert_pem;            /*!< Pointer to certificate data in PEM or DER format for SSL mutual authentication, default is NULL, not required if mutual authentication is not needed. If it is not NULL, also `client_key_pem` has to be provided. PEM-format must have a terminating NULL-character. DER-format requires the length to be passed in client_cert_len. */
-    size_t client_cert_len;                 /*!< Length of the buffer pointed to by client_cert_pem. May be 0 for null-terminated pem */
-    const char *client_key_pem;             /*!< Pointer to private key data in PEM or DER format for SSL mutual authentication, default is NULL, not required if mutual authentication is not needed. If it is not NULL, also `client_cert_pem` has to be provided. PEM-format must have a terminating NULL-character. DER-format requires the length to be passed in client_key_len */
-    size_t client_key_len;                  /*!< Length of the buffer pointed to by client_key_pem. May be 0 for null-terminated pem */
-    esp_mqtt_transport_t transport;         /*!< overrides URI transport */
-    int refresh_connection_after_ms;        /*!< Refresh connection after this value (in milliseconds) */
-    const struct psk_key_hint* psk_hint_key;     /*!< Pointer to PSK struct defined in esp_tls.h to enable PSK authentication (as alternative to certificate verification). If not NULL and server/client certificates are NULL, PSK is enabled */
-    bool          use_global_ca_store;      /*!< Use a global ca_store for all the connections in which this bool is set. */
-    int reconnect_timeout_ms;               /*!< Reconnect to the broker after this value in miliseconds if auto reconnect is not disabled */
-    const char **alpn_protos;               /*!< NULL-terminated list of supported application protocols to be used for ALPN */
-    const char *clientkey_password;         /*!< Client key decryption password string */
-    int clientkey_password_len;             /*!< String length of the password pointed to by clientkey_password */
-    esp_mqtt_protocol_ver_t protocol_ver;   /*!< MQTT protocol version used for connection, defaults to value from menuconfig*/
-    int out_buffer_size;                    /*!< size of MQTT output buffer. If not defined, both output and input buffers have the same size defined as ``buffer_size`` */
-    bool skip_cert_common_name_check;       /*!< Skip any validation of server certificate CN field, this reduces the security of TLS and makes the mqtt client susceptible to MITM attacks  */
-    bool use_secure_element;                /*!< enable secure element for enabling SSL connection */
-    void *ds_data;                          /*!< carrier of handle for digital signature parameters */
-} esp_mqtt_client_config_t;
-
-/**
- * @brief Creates mqtt client handle based on the configuration
- *
- * @param config    mqtt configuration structure
- *
- * @return mqtt_client_handle if successfully created, NULL on error
- */
-esp_mqtt_client_handle_t esp_mqtt_client_init(const esp_mqtt_client_config_t *config);
-
-/**
- * @brief Sets mqtt connection URI. This API is usually used to overrides the URI
- * configured in esp_mqtt_client_init
- *
- * @param client    mqtt client handle
- * @param uri
- *
- * @return ESP_FAIL if URI parse error, ESP_OK on success
- */
-esp_err_t esp_mqtt_client_set_uri(esp_mqtt_client_handle_t client, const char *uri);
-
-/**
- * @brief Starts mqtt client with already created client handle
- *
- * @param client    mqtt client handle
- *
- * @return ESP_OK on success
- *         ESP_ERR_INVALID_ARG on wrong initialization
- *         ESP_FAIL on other error
- */
-esp_err_t esp_mqtt_client_start(esp_mqtt_client_handle_t client);
-
-/**
- * @brief This api is typically used to force reconnection upon a specific event
- *
- * @param client    mqtt client handle
- *
- * @return ESP_OK on success
- *         ESP_FAIL if client is in invalid state
- */
-esp_err_t esp_mqtt_client_reconnect(esp_mqtt_client_handle_t client);
-
-/**
- * @brief This api is typically used to force disconnection from the broker
- *
- * @param client    mqtt client handle
- *
- * @return ESP_OK on success
- */
-esp_err_t esp_mqtt_client_disconnect(esp_mqtt_client_handle_t client);
-
-/**
- * @brief Stops mqtt client tasks
- *
- *  * Notes:
- *  - Cannot be called from the mqtt event handler
- *
- * @param client    mqtt client handle
- *
- * @return ESP_OK on success
- *         ESP_FAIL if client is in invalid state
- */
-esp_err_t esp_mqtt_client_stop(esp_mqtt_client_handle_t client);
-
-/**
- * @brief Subscribe the client to defined topic with defined qos
- *
- * Notes:
- * - Client must be connected to send subscribe message
- * - This API is could be executed from a user task or
- * from a mqtt event callback i.e. internal mqtt task
- * (API is protected by internal mutex, so it might block
- * if a longer data receive operation is in progress.
- *
- * @param client    mqtt client handle
- * @param topic
- * @param qos
- *
- * @return message_id of the subscribe message on success
- *         -1 on failure
- */
-int esp_mqtt_client_subscribe(esp_mqtt_client_handle_t client, const char *topic, int qos);
-
-/**
- * @brief Unsubscribe the client from defined topic
- *
- * Notes:
- * - Client must be connected to send unsubscribe message
- * - It is thread safe, please refer to `esp_mqtt_client_subscribe` for details
- *
- * @param client    mqtt client handle
- * @param topic
- *
- * @return message_id of the subscribe message on success
- *         -1 on failure
- */
-int esp_mqtt_client_unsubscribe(esp_mqtt_client_handle_t client, const char *topic);
-
-/**
- * @brief Client to send a publish message to the broker
- *
- * Notes:
- * - This API might block for several seconds, either due to network timeout (10s)
- *   or if publishing payloads longer than internal buffer (due to message
- *   fragmentation)
- * - Client doesn't have to be connected to send publish message
- *   (although it would drop all qos=0 messages, qos>1 messages would be enqueued)
- * - It is thread safe, please refer to `esp_mqtt_client_subscribe` for details
- *
- * @param client    mqtt client handle
- * @param topic     topic string
- * @param data      payload string (set to NULL, sending empty payload message)
- * @param len       data length, if set to 0, length is calculated from payload string
- * @param qos       qos of publish message
- * @param retain    retain flag
- *
- * @return message_id of the publish message (for QoS 0 message_id will always be zero) on success.
- *         -1 on failure.
- */
-int esp_mqtt_client_publish(esp_mqtt_client_handle_t client, const char *topic, const char *data, int len, int qos, int retain);
-
-/**
- * @brief Destroys the client handle
- *
- * Notes:
- *  - Cannot be called from the mqtt event handler
- *
- * @param client    mqtt client handle
- *
- * @return ESP_OK
- */
-esp_err_t esp_mqtt_client_destroy(esp_mqtt_client_handle_t client);
-
-/**
- * @brief Set configuration structure, typically used when updating the config (i.e. on "before_connect" event
- *
- * @param client    mqtt client handle
- *
- * @param config    mqtt configuration structure
- *
- * @return ESP_ERR_NO_MEM if failed to allocate
- *         ESP_OK on success
- */
-esp_err_t esp_mqtt_set_config(esp_mqtt_client_handle_t client, const esp_mqtt_client_config_t *config);
-
-/**
- * @brief Registers mqtt event
- *
- * @param client            mqtt client handle
- * @param event             event type
- * @param event_handler     handler callback
- * @param event_handler_arg handlers context
- *
- * @return ESP_ERR_NO_MEM if failed to allocate
- *         ESP_OK on success
- */
-esp_err_t esp_mqtt_client_register_event(esp_mqtt_client_handle_t client, esp_mqtt_event_id_t event, esp_event_handler_t event_handler, void* event_handler_arg);
-
-#ifdef __cplusplus
-}
-#endif //__cplusplus
-
-#endif
diff --git a/tools/sdk/include/mqtt/mqtt_config.h b/tools/sdk/include/mqtt/mqtt_config.h
deleted file mode 100644
index e259a2a1188..00000000000
--- a/tools/sdk/include/mqtt/mqtt_config.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is subject to the terms and conditions defined in
- * file 'LICENSE', which is part of this source code package.
- * Tuan PM <tuanpm at live dot com>
- */
-#ifndef _MQTT_CONFIG_H_
-#define _MQTT_CONFIG_H_
-
-#include "sdkconfig.h"
-
-#ifdef CONFIG_MQTT_PROTOCOL_311
-#define MQTT_PROTOCOL_311
-#endif
-
-#define MQTT_RECON_DEFAULT_MS       (10*1000)
-#define MQTT_POLL_READ_TIMEOUT_MS   (1000)
-
-#if CONFIG_MQTT_BUFFER_SIZE
-#define MQTT_BUFFER_SIZE_BYTE       CONFIG_MQTT_BUFFER_SIZE
-#else
-#define MQTT_BUFFER_SIZE_BYTE       1024
-#endif
-
-#define MQTT_MAX_HOST_LEN           64
-#define MQTT_MAX_CLIENT_LEN         32
-#define MQTT_MAX_USERNAME_LEN       32
-#define MQTT_MAX_PASSWORD_LEN       65
-#define MQTT_MAX_LWT_TOPIC          32
-#define MQTT_MAX_LWT_MSG            128
-
-#if CONFIG_MQTT_TASK_PRIORITY
-#define MQTT_TASK_PRIORITY          CONFIG_MQTT_TASK_PRIORITY
-#else
-#define MQTT_TASK_PRIORITY          5
-#endif
-
-#if CONFIG_MQTT_TASK_STACK_SIZE
-#define MQTT_TASK_STACK             CONFIG_MQTT_TASK_STACK_SIZE
-#else
-#define MQTT_TASK_STACK             (6*1024)
-#endif
-
-#define MQTT_KEEPALIVE_TICK         (120)
-#define MQTT_CMD_QUEUE_SIZE         (10)
-#define MQTT_NETWORK_TIMEOUT_MS     (10000)
-
-#ifdef CONFIG_MQTT_TCP_DEFAULT_PORT
-#define MQTT_TCP_DEFAULT_PORT       CONFIG_MQTT_TCP_DEFAULT_PORT
-#else
-#define MQTT_TCP_DEFAULT_PORT       1883
-#endif
-
-#ifdef CONFIG_MQTT_SSL_DEFAULT_PORT
-#define MQTT_SSL_DEFAULT_PORT       CONFIG_MQTT_SSL_DEFAULT_PORT
-#else
-#define MQTT_SSL_DEFAULT_PORT       8883
-#endif
-
-#ifdef CONFIG_MQTT_WS_DEFAULT_PORT
-#define MQTT_WS_DEFAULT_PORT        CONFIG_MQTT_WS_DEFAULT_PORT
-#else
-#define MQTT_WS_DEFAULT_PORT        80
-#endif
-
-#ifdef MQTT_WSS_DEFAULT_PORT
-#define MQTT_WSS_DEFAULT_PORT       CONFIG_MQTT_WSS_DEFAULT_PORT
-#else
-#define MQTT_WSS_DEFAULT_PORT       443
-#endif
-
-#define MQTT_CORE_SELECTION_ENABLED CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED
-
-#ifdef  CONFIG_MQTT_DISABLE_API_LOCKS
-#define MQTT_DISABLE_API_LOCKS          CONFIG_MQTT_DISABLE_API_LOCKS
-#endif
-
-#ifdef CONFIG_MQTT_USE_CORE_0
-#define MQTT_TASK_CORE    0
-#else
-#ifdef CONFIG_MQTT_USE_CORE_1
-#define MQTT_TASK_CORE 1
-#else
-#define MQTT_TASK_CORE 0
-#endif
-#endif
-
-#ifdef  CONFIG_OUTBOX_EXPIRED_TIMEOUT_MS
-#define OUTBOX_EXPIRED_TIMEOUT_MS   CONFIG_OUTBOX_EXPIRED_TIMEOUT_MS
-#else
-#define OUTBOX_EXPIRED_TIMEOUT_MS   (30*1000)
-#endif
-
-#define MQTT_ENABLE_SSL             CONFIG_MQTT_TRANSPORT_SSL
-#define MQTT_ENABLE_WS              CONFIG_MQTT_TRANSPORT_WEBSOCKET
-#define MQTT_ENABLE_WSS             CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE
-
-
-#define OUTBOX_MAX_SIZE             (4*1024)
-#endif
diff --git a/tools/sdk/include/mqtt/mqtt_supported_features.h b/tools/sdk/include/mqtt/mqtt_supported_features.h
deleted file mode 100644
index 9f1acf2ffad..00000000000
--- a/tools/sdk/include/mqtt/mqtt_supported_features.h
+++ /dev/null
@@ -1,62 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _MQTT_SUPPORTED_FEATURES_H_
-#define _MQTT_SUPPORTED_FEATURES_H_
-
-#if __has_include("esp_idf_version.h")
-#include "esp_idf_version.h"
-#endif
-
-/**
- * @brief This header defines supported features of IDF which mqtt module
- *        could use depending on specific version of ESP-IDF.
- *        In case "esp_idf_version.h" were not found, all additional
- *        features would be disabled
- */
-
-#ifdef ESP_IDF_VERSION
-
-#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(3, 3, 0)
-// Features supported from 3.3
-#define MQTT_SUPPORTED_FEATURE_EVENT_LOOP
-#define MQTT_SUPPORTED_FEATURE_SKIP_CRT_CMN_NAME_CHECK
-#endif
-
-#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 0, 0)
-// Features supported in 4.0
-#define MQTT_SUPPORTED_FEATURE_WS_SUBPROTOCOL
-#define MQTT_SUPPORTED_FEATURE_TRANSPORT_ERR_REPORTING
-#endif
-
-#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 1, 0)
-// Features supported in 4.1
-#define MQTT_SUPPORTED_FEATURE_PSK_AUTHENTICATION
-#define MQTT_SUPPORTED_FEATURE_DER_CERTIFICATES
-#define MQTT_SUPPORTED_FEATURE_ALPN
-#define MQTT_SUPPORTED_FEATURE_CLIENT_KEY_PASSWORD
-#endif
-
-#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)
-// Features supported in 4.2
-#define MQTT_SUPPORTED_FEATURE_SECURE_ELEMENT
-#endif
-
-#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 3, 0)
-// Features supported in 4.3
-#define MQTT_SUPPORTED_FEATURE_DIGITAL_SIGNATURE
-#endif
-
-#endif /* ESP_IDF_VERSION */
-#endif // _MQTT_SUPPORTED_FEATURES_H_
diff --git a/tools/sdk/include/newlib/_ansi.h b/tools/sdk/include/newlib/_ansi.h
deleted file mode 100644
index 5fb99070096..00000000000
--- a/tools/sdk/include/newlib/_ansi.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Provide support for both ANSI and non-ANSI environments.  */
-
-/* Some ANSI environments are "broken" in the sense that __STDC__ cannot be
-   relied upon to have it's intended meaning.  Therefore we must use our own
-   concoction: _HAVE_STDC.  Always use _HAVE_STDC instead of __STDC__ in newlib
-   sources!
-
-   To get a strict ANSI C environment, define macro __STRICT_ANSI__.  This will
-   "comment out" the non-ANSI parts of the ANSI header files (non-ANSI header
-   files aren't affected).  */
-
-#ifndef	_ANSIDECL_H_
-#define	_ANSIDECL_H_
-
-#include <newlib.h>
-#include <sys/config.h>
-
-/* First try to figure out whether we really are in an ANSI C environment.  */
-/* FIXME: This probably needs some work.  Perhaps sys/config.h can be
-   prevailed upon to give us a clue.  */
-
-#ifdef __STDC__
-#define _HAVE_STDC
-#endif
-
-/*  ISO C++.  */
-
-#ifdef __cplusplus
-#if !(defined(_BEGIN_STD_C) && defined(_END_STD_C))
-#ifdef _HAVE_STD_CXX
-#define _BEGIN_STD_C namespace std { extern "C" {
-#define _END_STD_C  } }
-#else
-#define _BEGIN_STD_C extern "C" {
-#define _END_STD_C  }
-#endif
-#if __GNUC_PREREQ (3, 3)
-#define _NOTHROW __attribute__ ((__nothrow__))
-#else
-#define _NOTHROW throw()
-#endif
-#endif
-#else
-#define _BEGIN_STD_C
-#define _END_STD_C
-#define _NOTHROW
-#endif
-
-#ifdef _HAVE_STDC
-#define	_PTR		void *
-#define	_AND		,
-#define	_NOARGS		void
-#define	_CONST		const
-#define	_VOLATILE	volatile
-#define	_SIGNED		signed
-#define	_DOTS		, ...
-#define _VOID void
-#ifdef __CYGWIN__
-#define	_EXFUN_NOTHROW(name, proto)	__cdecl name proto _NOTHROW
-#define	_EXFUN(name, proto)		__cdecl name proto
-#define	_EXPARM(name, proto)		(* __cdecl name) proto
-#define	_EXFNPTR(name, proto)		(__cdecl * name) proto
-#else
-#define	_EXFUN_NOTHROW(name, proto)	name proto _NOTHROW
-#define	_EXFUN(name, proto)		name proto
-#define _EXPARM(name, proto)		(* name) proto
-#define _EXFNPTR(name, proto)		(* name) proto
-#endif
-#define	_DEFUN(name, arglist, args)	name(args)
-#define	_DEFUN_VOID(name)		name(_NOARGS)
-#define _CAST_VOID (void)
-#ifndef _LONG_DOUBLE
-#define _LONG_DOUBLE long double
-#endif
-#ifndef _PARAMS
-#define _PARAMS(paramlist)		paramlist
-#endif
-#else	
-#define	_PTR		char *
-#define	_AND		;
-#define	_NOARGS
-#define	_CONST
-#define	_VOLATILE
-#define	_SIGNED
-#define	_DOTS
-#define _VOID void
-#define	_EXFUN(name, proto)		name()
-#define	_EXFUN_NOTHROW(name, proto)	name()
-#define	_DEFUN(name, arglist, args)	name arglist args;
-#define	_DEFUN_VOID(name)		name()
-#define _CAST_VOID
-#define _LONG_DOUBLE double
-#ifndef _PARAMS
-#define _PARAMS(paramlist)		()
-#endif
-#endif
-
-/* Support gcc's __attribute__ facility.  */
-
-#ifdef __GNUC__
-#define _ATTRIBUTE(attrs) __attribute__ (attrs)
-#else
-#define _ATTRIBUTE(attrs)
-#endif
-
-/*  The traditional meaning of 'extern inline' for GCC is not
-  to emit the function body unless the address is explicitly
-  taken.  However this behaviour is changing to match the C99
-  standard, which uses 'extern inline' to indicate that the
-  function body *must* be emitted.  Likewise, a function declared
-  without either 'extern' or 'static' defaults to extern linkage
-  (C99 6.2.2p5), and the compiler may choose whether to use the
-  inline version or call the extern linkage version (6.7.4p6).
-  If we are using GCC, but do not have the new behaviour, we need
-  to use extern inline; if we are using a new GCC with the
-  C99-compatible behaviour, or a non-GCC compiler (which we will
-  have to hope is C99, since there is no other way to achieve the
-  effect of omitting the function if it isn't referenced) we use
-  'static inline', which c99 defines to mean more-or-less the same
-  as the Gnu C 'extern inline'.  */
-#if defined(__GNUC__) && !defined(__GNUC_STDC_INLINE__)
-/* We're using GCC, but without the new C99-compatible behaviour.  */
-#define _ELIDABLE_INLINE extern __inline__ _ATTRIBUTE ((__always_inline__))
-#else
-/* We're using GCC in C99 mode, or an unknown compiler which
-  we just have to hope obeys the C99 semantics of inline.  */
-#define _ELIDABLE_INLINE static __inline__
-#endif
-
-#if __GNUC_PREREQ (3, 1)
-#define _NOINLINE		__attribute__ ((__noinline__))
-#define _NOINLINE_STATIC	_NOINLINE static
-#else
-/* On non-GNU compilers and GCC prior to version 3.1 the compiler can't be
-   trusted not to inline if it is static. */
-#define _NOINLINE
-#define _NOINLINE_STATIC
-#endif
-
-#endif /* _ANSIDECL_H_ */
diff --git a/tools/sdk/include/newlib/_syslist.h b/tools/sdk/include/newlib/_syslist.h
deleted file mode 100644
index 271644efa93..00000000000
--- a/tools/sdk/include/newlib/_syslist.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* internal use only -- mapping of "system calls" for libraries that lose
-   and only provide C names, so that we end up in violation of ANSI */
-#ifndef __SYSLIST_H
-#define __SYSLIST_H
-
-#ifdef MISSING_SYSCALL_NAMES
-#define _close close
-#define _execve execve
-#define _fcntl fcntl
-#define _fork fork
-#define _fstat fstat
-#define _getpid getpid
-#define _gettimeofday gettimeofday
-#define _isatty isatty
-#define _kill kill
-#define _link link
-#define _lseek lseek
-#define _mkdir mkdir
-#define _open open
-#define _read read
-#define _sbrk sbrk
-#define _stat stat
-#define _times times
-#define _unlink unlink
-#define _wait wait
-#define _write write
-#endif /* MISSING_SYSCALL_NAMES */
-
-#if defined MISSING_SYSCALL_NAMES || !defined HAVE_OPENDIR
-/* If the system call interface is missing opendir, readdir, and
-   closedir, there is an implementation of these functions in
-   libc/posix that is implemented using open, getdents, and close. 
-   Note, these functions are currently not in the libc/syscalls
-   directory.  */
-#define _opendir opendir
-#define _readdir readdir
-#define _closedir closedir
-#endif /* MISSING_SYSCALL_NAMES || !HAVE_OPENDIR */
-
-#endif /* !__SYSLIST_H_ */
diff --git a/tools/sdk/include/newlib/alloca.h b/tools/sdk/include/newlib/alloca.h
deleted file mode 100644
index 2ea0fd9b37a..00000000000
--- a/tools/sdk/include/newlib/alloca.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* libc/include/alloca.h - Allocate memory on stack */
-
-/* Written 2000 by Werner Almesberger */
-/* Rearranged for general inclusion by stdlib.h.
-   2001, Corinna Vinschen <vinschen@redhat.com> */
-
-#ifndef _NEWLIB_ALLOCA_H
-#define _NEWLIB_ALLOCA_H
-
-#include "_ansi.h"
-#include <sys/reent.h>
-
-#undef alloca
-
-#ifdef __GNUC__
-#define alloca(size) __builtin_alloca(size)
-#else
-void * _EXFUN(alloca,(size_t));
-#endif
-
-#endif
diff --git a/tools/sdk/include/newlib/ar.h b/tools/sdk/include/newlib/ar.h
deleted file mode 100644
index ac2e4ca920d..00000000000
--- a/tools/sdk/include/newlib/ar.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*	$NetBSD: ar.h,v 1.4 1994/10/26 00:55:43 cgd Exp $	*/
-
-/*-
- * Copyright (c) 1991, 1993
- *	The Regents of the University of California.  All rights reserved.
- * (c) UNIX System Laboratories, Inc.
- * All or some portions of this file are derived from material licensed
- * to the University of California by American Telephone and Telegraph
- * Co. or Unix System Laboratories, Inc. and are reproduced herein with
- * the permission of UNIX System Laboratories, Inc.
- *
- * This code is derived from software contributed to Berkeley by
- * Hugh Smith at The University of Guelph.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)ar.h	8.2 (Berkeley) 1/21/94
- */
-
-#ifndef _AR_H_
-#define	_AR_H_
-
-/* Pre-4BSD archives had these magic numbers in them. */
-#define	OARMAG1	0177555
-#define	OARMAG2	0177545
-
-#define	ARMAG		"!<arch>\n"	/* ar "magic number" */
-#define	SARMAG		8		/* strlen(ARMAG); */
-
-#define	AR_EFMT1	"#1/"		/* extended format #1 */
-
-struct ar_hdr {
-	char ar_name[16];		/* name */
-	char ar_date[12];		/* modification time */
-	char ar_uid[6];			/* user id */
-	char ar_gid[6];			/* group id */
-	char ar_mode[8];		/* octal file permissions */
-	char ar_size[10];		/* size in bytes */
-#define	ARFMAG	"`\n"
-	char ar_fmag[2];		/* consistency check */
-};
-
-#endif /* !_AR_H_ */
diff --git a/tools/sdk/include/newlib/argz.h b/tools/sdk/include/newlib/argz.h
deleted file mode 100644
index 02c9adbf3f9..00000000000
--- a/tools/sdk/include/newlib/argz.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright (C) 2002 by  Red Hat, Incorporated. All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software
- * is freely granted, provided that this notice is preserved.
- */
-
-#ifndef _ARGZ_H_
-#define _ARGZ_H_
-
-#include <errno.h>
-#include <sys/types.h>
-
-#include "_ansi.h"
-
-_BEGIN_STD_C
-
-/* The newlib implementation of these functions assumes that sizeof(char) == 1. */
-error_t argz_create (char *const argv[], char **argz, size_t *argz_len);
-error_t argz_create_sep (const char *string, int sep, char **argz, size_t *argz_len);
-size_t argz_count (const char *argz, size_t argz_len);
-void argz_extract (char *argz, size_t argz_len, char **argv);
-void argz_stringify (char *argz, size_t argz_len, int sep);
-error_t argz_add (char **argz, size_t *argz_len, const char *str);
-error_t argz_add_sep (char **argz, size_t *argz_len, const char *str, int sep);
-error_t argz_append (char **argz, size_t *argz_len, const char *buf, size_t buf_len);
-error_t argz_delete (char **argz, size_t *argz_len, char *entry);
-error_t argz_insert (char **argz, size_t *argz_len, char *before, const char *entry);
-char * argz_next (char *argz, size_t argz_len, const char *entry);
-error_t argz_replace (char **argz, size_t *argz_len, const char *str, const char *with, unsigned *replace_count);
-
-_END_STD_C
-
-#endif /* _ARGZ_H_ */
diff --git a/tools/sdk/include/newlib/assert.h b/tools/sdk/include/newlib/assert.h
deleted file mode 100644
index df46c030b28..00000000000
--- a/tools/sdk/include/newlib/assert.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
-	assert.h
-*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "_ansi.h"
-
-#undef assert
-
-#ifdef NDEBUG           /* required by ANSI standard */
-# define assert(__e) ((void) sizeof(__e))
-#else
-# define assert(__e) ((__e) ? (void)0 : __assert_func (__FILE__, __LINE__, \
-						       __ASSERT_FUNC, #__e))
-
-# ifndef __ASSERT_FUNC
-  /* Use g++'s demangled names in C++.  */
-#  if defined __cplusplus && defined __GNUC__
-#   define __ASSERT_FUNC __PRETTY_FUNCTION__
-
-  /* C99 requires the use of __func__.  */
-#  elif __STDC_VERSION__ >= 199901L
-#   define __ASSERT_FUNC __func__
-
-  /* Older versions of gcc don't have __func__ but can use __FUNCTION__.  */
-#  elif __GNUC__ >= 2
-#   define __ASSERT_FUNC __FUNCTION__
-
-  /* failed to detect __func__ support.  */
-#  else
-#   define __ASSERT_FUNC ((char *) 0)
-#  endif
-# endif /* !__ASSERT_FUNC */
-#endif /* !NDEBUG */
-
-void _EXFUN(__assert, (const char *, int, const char *)
-	    _ATTRIBUTE ((__noreturn__)));
-void _EXFUN(__assert_func, (const char *, int, const char *, const char *)
-	    _ATTRIBUTE ((__noreturn__)));
-
-#if __STDC_VERSION__ >= 201112L && !defined __cplusplus
-# define static_assert _Static_assert
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/newlib/complex.h b/tools/sdk/include/newlib/complex.h
deleted file mode 100644
index 969b20e5f9a..00000000000
--- a/tools/sdk/include/newlib/complex.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/* $NetBSD: complex.h,v 1.3 2010/09/15 16:11:30 christos Exp $ */
-
-/*
- * Written by Matthias Drochner.
- * Public domain.
- */
-
-#ifndef	_COMPLEX_H
-#define	_COMPLEX_H
-
-#define complex _Complex
-#define _Complex_I 1.0fi
-#define I _Complex_I
-
-#include <sys/cdefs.h>
-
-__BEGIN_DECLS
-
-/* 7.3.5 Trigonometric functions */
-/* 7.3.5.1 The cacos functions */
-double complex cacos(double complex);
-float complex cacosf(float complex);
-
-/* 7.3.5.2 The casin functions */
-double complex casin(double complex);
-float complex casinf(float complex);
-
-/* 7.3.5.1 The catan functions */
-double complex catan(double complex);
-float complex catanf(float complex);
-
-/* 7.3.5.1 The ccos functions */
-double complex ccos(double complex);
-float complex ccosf(float complex);
-
-/* 7.3.5.1 The csin functions */
-double complex csin(double complex);
-float complex csinf(float complex);
-
-/* 7.3.5.1 The ctan functions */
-double complex ctan(double complex);
-float complex ctanf(float complex);
-
-/* 7.3.6 Hyperbolic functions */
-/* 7.3.6.1 The cacosh functions */
-double complex cacosh(double complex);
-float complex cacoshf(float complex);
-
-/* 7.3.6.2 The casinh functions */
-double complex casinh(double complex);
-float complex casinhf(float complex);
-
-/* 7.3.6.3 The catanh functions */
-double complex catanh(double complex);
-float complex catanhf(float complex);
-
-/* 7.3.6.4 The ccosh functions */
-double complex ccosh(double complex);
-float complex ccoshf(float complex);
-
-/* 7.3.6.5 The csinh functions */
-double complex csinh(double complex);
-float complex csinhf(float complex);
-
-/* 7.3.6.6 The ctanh functions */
-double complex ctanh(double complex);
-float complex ctanhf(float complex);
-
-/* 7.3.7 Exponential and logarithmic functions */
-/* 7.3.7.1 The cexp functions */
-double complex cexp(double complex);
-float complex cexpf(float complex);
-
-/* 7.3.7.2 The clog functions */
-double complex clog(double complex);
-float complex clogf(float complex);
-
-/* 7.3.8 Power and absolute-value functions */
-/* 7.3.8.1 The cabs functions */
-/*#ifndef __LIBM0_SOURCE__ */
-/* avoid conflict with historical cabs(struct complex) */
-/* double cabs(double complex) __RENAME(__c99_cabs);
-   float cabsf(float complex) __RENAME(__c99_cabsf);
-   #endif
-*/
-double cabs(double complex) ;
-float cabsf(float complex) ;
-
-/* 7.3.8.2 The cpow functions */
-double complex cpow(double complex, double complex);
-float complex cpowf(float complex, float complex);
-
-/* 7.3.8.3 The csqrt functions */
-double complex csqrt(double complex);
-float complex csqrtf(float complex);
-
-/* 7.3.9 Manipulation functions */
-/* 7.3.9.1 The carg functions */ 
-double carg(double complex);
-float cargf(float complex);
-
-/* 7.3.9.2 The cimag functions */
-double cimag(double complex);
-float cimagf(float complex);
-/*long double cimagl(long double complex); */
-
-/* 7.3.9.3 The conj functions */
-double complex conj(double complex);
-float complex conjf(float complex);
-/*long double complex conjl(long double complex); */
-
-/* 7.3.9.4 The cproj functions */
-double complex cproj(double complex);
-float complex cprojf(float complex);
-/*long double complex cprojl(long double complex); */
-
-/* 7.3.9.5 The creal functions */
-double creal(double complex);
-float crealf(float complex);
-/*long double creall(long double complex); */
-
-__END_DECLS
-
-#endif	/* ! _COMPLEX_H */
diff --git a/tools/sdk/include/newlib/config.h b/tools/sdk/include/newlib/config.h
deleted file mode 100644
index 69d49adf95b..00000000000
--- a/tools/sdk/include/newlib/config.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __SYS_CONFIG_H__
-#define __SYS_CONFIG_H__
-
-#include <machine/ieeefp.h>  /* floating point macros */
-#include <sys/features.h>	/* POSIX defs */
-
-#ifndef __EXPORT
-#define __EXPORT
-#endif
-
-#ifndef __IMPORT
-#define __IMPORT
-#endif
-
-/* Define return type of read/write routines.  In POSIX, the return type
-   for read()/write() is "ssize_t" but legacy newlib code has been using
-   "int" for some time.  If not specified, "int" is defaulted.  */
-#ifndef _READ_WRITE_RETURN_TYPE
-#define _READ_WRITE_RETURN_TYPE int
-#endif
-/* Define `count' parameter of read/write routines.  In POSIX, the `count'
-   parameter is "size_t" but legacy newlib code has been using "int" for some
-   time.  If not specified, "int" is defaulted.  */
-#ifndef _READ_WRITE_BUFSIZE_TYPE
-#define _READ_WRITE_BUFSIZE_TYPE int
-#endif
-
-#endif /* __SYS_CONFIG_H__ */
diff --git a/tools/sdk/include/newlib/ctype.h b/tools/sdk/include/newlib/ctype.h
deleted file mode 100644
index 1eb3f787f88..00000000000
--- a/tools/sdk/include/newlib/ctype.h
+++ /dev/null
@@ -1,113 +0,0 @@
-#ifndef _CTYPE_H_
-#define _CTYPE_H_
-
-#include "_ansi.h"
-
-_BEGIN_STD_C
-
-int _EXFUN(isalnum, (int __c));
-int _EXFUN(isalpha, (int __c));
-int _EXFUN(iscntrl, (int __c));
-int _EXFUN(isdigit, (int __c));
-int _EXFUN(isgraph, (int __c));
-int _EXFUN(islower, (int __c));
-int _EXFUN(isprint, (int __c));
-int _EXFUN(ispunct, (int __c));
-int _EXFUN(isspace, (int __c));
-int _EXFUN(isupper, (int __c));
-int _EXFUN(isxdigit,(int __c));
-int _EXFUN(tolower, (int __c));
-int _EXFUN(toupper, (int __c));
-
-#if !defined(__STRICT_ANSI__) || defined(__cplusplus) || __STDC_VERSION__ >= 199901L
-int _EXFUN(isblank, (int __c));
-#endif
-
-#ifndef __STRICT_ANSI__
-int _EXFUN(isascii, (int __c));
-int _EXFUN(toascii, (int __c));
-#define _tolower(__c) ((unsigned char)(__c) - 'A' + 'a')
-#define _toupper(__c) ((unsigned char)(__c) - 'a' + 'A')
-#endif
-
-#define	_U	01
-#define	_L	02
-#define	_N	04
-#define	_S	010
-#define _P	020
-#define _C	040
-#define _X	0100
-#define	_B	0200
-
-#ifndef _MB_CAPABLE
-_CONST
-#endif
-extern	__IMPORT char	* _CONST __ctype_ptr__;
-
-#ifndef __cplusplus
-/* These macros are intentionally written in a manner that will trigger
-   a gcc -Wall warning if the user mistakenly passes a 'char' instead
-   of an int containing an 'unsigned char'.  Note that the sizeof will
-   always be 1, which is what we want for mapping EOF to __ctype_ptr__[0];
-   the use of a raw index inside the sizeof triggers the gcc warning if
-   __c was of type char, and sizeof masks side effects of the extra __c.
-   Meanwhile, the real index to __ctype_ptr__+1 must be cast to int,
-   since isalpha(0x100000001LL) must equal isalpha(1), rather than being
-   an out-of-bounds reference on a 64-bit machine.  */
-#define __ctype_lookup(__c) ((__ctype_ptr__+sizeof(""[__c]))[(int)(__c)])
-
-#define	isalpha(__c)	(__ctype_lookup(__c)&(_U|_L))
-#define	isupper(__c)	((__ctype_lookup(__c)&(_U|_L))==_U)
-#define	islower(__c)	((__ctype_lookup(__c)&(_U|_L))==_L)
-#define	isdigit(__c)	(__ctype_lookup(__c)&_N)
-#define	isxdigit(__c)	(__ctype_lookup(__c)&(_X|_N))
-#define	isspace(__c)	(__ctype_lookup(__c)&_S)
-#define ispunct(__c)	(__ctype_lookup(__c)&_P)
-#define isalnum(__c)	(__ctype_lookup(__c)&(_U|_L|_N))
-#define isprint(__c)	(__ctype_lookup(__c)&(_P|_U|_L|_N|_B))
-#define	isgraph(__c)	(__ctype_lookup(__c)&(_P|_U|_L|_N))
-#define iscntrl(__c)	(__ctype_lookup(__c)&_C)
-
-#if defined(__GNUC__) && \
-    (!defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901L)
-#define isblank(__c) \
-  __extension__ ({ __typeof__ (__c) __x = (__c);		\
-        (__ctype_lookup(__x)&_B) || (int) (__x) == '\t';})
-#endif
-
-
-/* Non-gcc versions will get the library versions, and will be
-   slightly slower.  These macros are not NLS-aware so they are
-   disabled if the system supports the extended character sets. */
-# if defined(__GNUC__)
-#  if !defined (_MB_EXTENDED_CHARSETS_ISO) && !defined (_MB_EXTENDED_CHARSETS_WINDOWS)
-#   define toupper(__c) \
-  __extension__ ({ __typeof__ (__c) __x = (__c);	\
-      islower (__x) ? (int) __x - 'a' + 'A' : (int) __x;})
-#   define tolower(__c) \
-  __extension__ ({ __typeof__ (__c) __x = (__c);	\
-      isupper (__x) ? (int) __x - 'A' + 'a' : (int) __x;})
-#  else /* _MB_EXTENDED_CHARSETS* */
-/* Allow a gcc warning if the user passed 'char', but defer to the
-   function.  */
-#   define toupper(__c) \
-  __extension__ ({ __typeof__ (__c) __x = (__c);	\
-      (void) __ctype_ptr__[__x]; (toupper) (__x);})
-#   define tolower(__c) \
-  __extension__ ({ __typeof__ (__c) __x = (__c);	\
-      (void) __ctype_ptr__[__x]; (tolower) (__x);})
-#  endif /* _MB_EXTENDED_CHARSETS* */
-# endif /* __GNUC__ */
-#endif /* !__cplusplus */
-
-#ifndef __STRICT_ANSI__
-#define isascii(__c)	((unsigned)(__c)<=0177)
-#define toascii(__c)	((__c)&0177)
-#endif
-
-/* For C++ backward-compatibility only.  */
-extern	__IMPORT _CONST char	_ctype_[];
-
-_END_STD_C
-
-#endif /* _CTYPE_H_ */
diff --git a/tools/sdk/include/newlib/dirent.h b/tools/sdk/include/newlib/dirent.h
deleted file mode 100644
index 6fefc03cbdc..00000000000
--- a/tools/sdk/include/newlib/dirent.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _DIRENT_H_
-#define _DIRENT_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include <sys/dirent.h>
-
-#if !defined(MAXNAMLEN) && !defined(_POSIX_SOURCE)
-#define MAXNAMLEN 1024
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*_DIRENT_H_*/
diff --git a/tools/sdk/include/newlib/envlock.h b/tools/sdk/include/newlib/envlock.h
deleted file mode 100644
index 9bb6a813ea5..00000000000
--- a/tools/sdk/include/newlib/envlock.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* envlock.h -- header file for env routines.  */
-
-#ifndef _INCLUDE_ENVLOCK_H_
-#define _INCLUDE_ENVLOCK_H_
-
-#include <_ansi.h>
-#include <sys/reent.h>
-
-#define ENV_LOCK __env_lock(reent_ptr)
-#define ENV_UNLOCK __env_unlock(reent_ptr)
-
-void _EXFUN(__env_lock,(struct _reent *reent));
-void _EXFUN(__env_unlock,(struct _reent *reent));
-
-#endif /* _INCLUDE_ENVLOCK_H_ */
diff --git a/tools/sdk/include/newlib/envz.h b/tools/sdk/include/newlib/envz.h
deleted file mode 100644
index e6a31c31d65..00000000000
--- a/tools/sdk/include/newlib/envz.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright (C) 2002 by  Red Hat, Incorporated. All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software
- * is freely granted, provided that this notice is preserved.
- */
-
-#include <errno.h>
-#include <sys/types.h>
-
-/* The newlib implementation of these functions assumes that sizeof(char) == 1. */
-char * envz_entry (const char *envz, size_t envz_len, const char *name);
-char * envz_get (const char *envz, size_t envz_len, const char *name);
-error_t envz_add (char **envz, size_t *envz_len, const char *name, const char *value);
-error_t envz_merge (char **envz, size_t *envz_len, const char *envz2, size_t envz2_len, int override);
-void envz_remove(char **envz, size_t *envz_len, const char *name);
-void envz_strip (char **envz, size_t *envz_len);
diff --git a/tools/sdk/include/newlib/errno.h b/tools/sdk/include/newlib/errno.h
deleted file mode 100644
index 7cc2ca86f84..00000000000
--- a/tools/sdk/include/newlib/errno.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ERRNO_H__
-#define __ERRNO_H__
-
-#ifndef __error_t_defined
-typedef int error_t;
-#define __error_t_defined 1
-#endif
-
-#include <sys/errno.h>
-
-#endif /* !__ERRNO_H__ */
diff --git a/tools/sdk/include/newlib/esp_newlib.h b/tools/sdk/include/newlib/esp_newlib.h
deleted file mode 100644
index 31adf7d8473..00000000000
--- a/tools/sdk/include/newlib/esp_newlib.h
+++ /dev/null
@@ -1,46 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_NEWLIB_H__
-#define __ESP_NEWLIB_H__
-
-#include <sys/reent.h>
-
-/**
- * Replacement for newlib's _REENT_INIT_PTR and __sinit.
- *
- * Called from startup code and FreeRTOS, not intended to be called from
- * application code.
- */
-void esp_reent_init(struct _reent* r);
-
-/**
- * Function which sets up syscall table used by newlib functions in ROM.
- *
- * Called from the startup code, not intended to be called from application
- * code.
- */
-void esp_setup_syscall_table();
-
-/**
- * Update current microsecond time from RTC
- */
-void esp_set_time_from_rtc();
-
-/*
- * Sync counters RTC and FRC. Update boot_time.
- */
-void esp_sync_counters_rtc_and_frc();
-
-#endif //__ESP_NEWLIB_H__
diff --git a/tools/sdk/include/newlib/fastmath.h b/tools/sdk/include/newlib/fastmath.h
deleted file mode 100644
index 95eea5f3421..00000000000
--- a/tools/sdk/include/newlib/fastmath.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _FASTMATH_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-#define _FASTMATH_H_
-
-#include <math.h>
-#include <machine/fastmath.h>
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FASTMATH_H_ */
diff --git a/tools/sdk/include/newlib/fcntl.h b/tools/sdk/include/newlib/fcntl.h
deleted file mode 100644
index 86a9167757a..00000000000
--- a/tools/sdk/include/newlib/fcntl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <sys/fcntl.h>
diff --git a/tools/sdk/include/newlib/fenv.h b/tools/sdk/include/newlib/fenv.h
deleted file mode 100644
index 2fa76f758da..00000000000
--- a/tools/sdk/include/newlib/fenv.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* Copyright (c) 2011 Tensilica Inc.  ALL RIGHTS RESERVED.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions
-   are met:
-
-   1. Redistributions of source code must retain the above copyright
-      notice, this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above
-      copyright notice, this list of conditions and the following
-      disclaimer in the documentation and/or other materials provided
-      with the distribution.
-
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-   FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
-   TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
-   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-   OF THE POSSIBILITY OF SUCH DAMAGE.  */
-
-
-#ifndef _FENV_H
-#define _FENV_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef unsigned long fenv_t;
-typedef unsigned long fexcept_t;
-
-#define FE_DIVBYZERO   0x08
-#define FE_INEXACT     0x01
-#define FE_INVALID     0x10
-#define FE_OVERFLOW    0x04
-#define FE_UNDERFLOW   0x02
-
-#define FE_ALL_EXCEPT \
-  (FE_DIVBYZERO  |		      \
-   FE_INEXACT    |		      \
-   FE_INVALID    |		      \
-   FE_OVERFLOW   |		      \
-   FE_UNDERFLOW)
-
-#define FE_DOWNWARD   0x3
-#define FE_TONEAREST  0x0
-#define FE_TOWARDZERO 0x1
-#define FE_UPWARD     0x2
-
-#define FE_DFL_ENV ((const fenv_t *) 0)
-
-int  feclearexcept(int);
-int  fegetexceptflag(fexcept_t *, int);
-int  feraiseexcept(int);
-int  fesetexceptflag(const fexcept_t *, int);
-int  fetestexcept(int);
-int  fegetround(void);
-int  fesetround(int);
-int  fegetenv(fenv_t *);
-int  feholdexcept(fenv_t *);
-int  fesetenv(const fenv_t *);
-int  feupdateenv(const fenv_t *);
-
-/* glibc extensions  */
-int feenableexcept(int excepts);
-int fedisableexcept(int excepts);
-int fegetexcept(void);
-
-#define _FE_EXCEPTION_FLAGS_OFFSET 7
-#define _FE_EXCEPTION_FLAG_MASK (FE_ALL_EXCEPT << _FE_EXCEPTION_FLAGS_OFFSET)
-#define _FE_EXCEPTION_ENABLE_OFFSET 2
-#define _FE_EXCEPTION_ENABLE_MASK (FE_ALL_EXCEPT << _FE_EXCEPTION_ENABLE_OFFSET)
-#define _FE_ROUND_MODE_OFFSET 0
-#define _FE_ROUND_MODE_MASK (0x3 << _FE_ROUND_MODE_OFFSET)
-#define _FE_FLOATING_ENV_MASK (_FE_EXCEPTION_FLAG_MASK | _FE_EXCEPTION_ENABLE_MASK | _FE_ROUND_MODE_MASK)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/newlib/fnmatch.h b/tools/sdk/include/newlib/fnmatch.h
deleted file mode 100644
index 06311fc4b11..00000000000
--- a/tools/sdk/include/newlib/fnmatch.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*-
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD: src/include/fnmatch.h,v 1.10 2002/03/23 17:24:53 imp Exp $
- *	@(#)fnmatch.h	8.1 (Berkeley) 6/2/93
- */
-
-#ifndef	_FNMATCH_H_
-#define	_FNMATCH_H_
-
-#define	FNM_NOMATCH	1	/* Match failed. */
-
-#define	FNM_NOESCAPE	0x01	/* Disable backslash escaping. */
-#define	FNM_PATHNAME	0x02	/* Slash must be matched by slash. */
-#define	FNM_PERIOD	0x04	/* Period must be matched by period. */
-
-#if defined(_GNU_SOURCE) || !defined(_ANSI_SOURCE) && !defined(_POSIX_SOURCE)
-#define	FNM_LEADING_DIR	0x08	/* Ignore /<tail> after Imatch. */
-#define	FNM_CASEFOLD	0x10	/* Case insensitive search. */
-#define	FNM_IGNORECASE	FNM_CASEFOLD
-#define	FNM_FILE_NAME	FNM_PATHNAME
-#endif
-
-#include <sys/cdefs.h>
-
-__BEGIN_DECLS
-int	 fnmatch(const char *, const char *, int);
-__END_DECLS
-
-#endif /* !_FNMATCH_H_ */
diff --git a/tools/sdk/include/newlib/getopt.h b/tools/sdk/include/newlib/getopt.h
deleted file mode 100644
index e12d253d47b..00000000000
--- a/tools/sdk/include/newlib/getopt.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/****************************************************************************
-
-getopt.h - Read command line options
-
-AUTHOR: Gregory Pietsch
-CREATED Thu Jan 09 22:37:00 1997
-
-DESCRIPTION:
-
-The getopt() function parses the command line arguments.  Its arguments argc
-and argv are the argument count and array as passed to the main() function
-on program invocation.  The argument optstring is a list of available option
-characters.  If such a character is followed by a colon (`:'), the option
-takes an argument, which is placed in optarg.  If such a character is
-followed by two colons, the option takes an optional argument, which is
-placed in optarg.  If the option does not take an argument, optarg is NULL.
-
-The external variable optind is the index of the next array element of argv
-to be processed; it communicates from one call to the next which element to
-process.
-
-The getopt_long() function works like getopt() except that it also accepts
-long options started by two dashes `--'.  If these take values, it is either
-in the form
-
---arg=value
-
- or
-
---arg value
-
-It takes the additional arguments longopts which is a pointer to the first
-element of an array of type GETOPT_LONG_OPTION_T, defined below.  The last
-element of the array has to be filled with NULL for the name field.
-
-The longind pointer points to the index of the current long option relative
-to longopts if it is non-NULL.
-
-The getopt() function returns the option character if the option was found
-successfully, `:' if there was a missing parameter for one of the options,
-`?' for an unknown option character, and EOF for the end of the option list.
-
-The getopt_long() function's return value is described below.
-
-The function getopt_long_only() is identical to getopt_long(), except that a
-plus sign `+' can introduce long options as well as `--'.
-
-Describe how to deal with options that follow non-option ARGV-elements.
-
-If the caller did not specify anything, the default is REQUIRE_ORDER if the
-environment variable POSIXLY_CORRECT is defined, PERMUTE otherwise.
-
-REQUIRE_ORDER means don't recognize them as options; stop option processing
-when the first non-option is seen.  This is what Unix does.  This mode of
-operation is selected by either setting the environment variable
-POSIXLY_CORRECT, or using `+' as the first character of the optstring
-parameter.
-
-PERMUTE is the default.  We permute the contents of ARGV as we scan, so that
-eventually all the non-options are at the end.  This allows options to be
-given in any order, even with programs that were not written to expect this.
-
-RETURN_IN_ORDER is an option available to programs that were written to
-expect options and other ARGV-elements in any order and that care about the
-ordering of the two.  We describe each non-option ARGV-element as if it were
-the argument of an option with character code 1.  Using `-' as the first
-character of the optstring parameter selects this mode of operation.
-
-The special argument `--' forces an end of option-scanning regardless of the
-value of `ordering'.  In the case of RETURN_IN_ORDER, only `--' can cause
-getopt() and friends to return EOF with optind != argc.
-
-COPYRIGHT NOTICE AND DISCLAIMER:
-
-Copyright (C) 1997 Gregory Pietsch
-
-This file and the accompanying getopt.c implementation file are hereby 
-placed in the public domain without restrictions.  Just give the author 
-credit, don't claim you wrote it or prevent anyone else from using it.
-
-Gregory Pietsch's current e-mail address:
-gpietsch@comcast.net
-****************************************************************************/
-
-/* This is a glibc-extension header file. */
-
-#ifndef GETOPT_H
-#define GETOPT_H
-
-#include <_ansi.h>
-
-/* include files needed by this include file */
-
-#define no_argument		0
-#define required_argument	1
-#define optional_argument	2
-
-#ifdef __cplusplus
-extern "C"
-{
-
-#endif				/* __cplusplus */
-
-/* types defined by this include file */
-  struct option
-  {
-    const char *name;		/* the name of the long option */
-    int has_arg;		/* one of the above macros */
-    int *flag;			/* determines if getopt_long() returns a
-				 * value for a long option; if it is
-				 * non-NULL, 0 is returned as a function
-				 * value and the value of val is stored in
-				 * the area pointed to by flag.  Otherwise,
-				 * val is returned. */
-    int val;			/* determines the value to return if flag is
-				 * NULL. */
-
-  };
-
-/* While getopt.h is a glibc extension, the following are newlib extensions.
- * They are optionally included via the __need_getopt_newlib flag.  */
-
-#ifdef __need_getopt_newlib
-
-  /* macros defined by this include file */
-  #define NO_ARG          	no_argument
-  #define REQUIRED_ARG    	required_argument
-  #define OPTIONAL_ARG    	optional_argument
-
-  /* The GETOPT_DATA_INITIALIZER macro is used to initialize a statically-
-     allocated variable of type struct getopt_data.  */
-  #define GETOPT_DATA_INITIALIZER	{0,0,0,0,0}
-
-  /* These #defines are to make accessing the reentrant functions easier.  */
-  #define getopt_r		__getopt_r
-  #define getopt_long_r		__getopt_long_r
-  #define getopt_long_only_r	__getopt_long_only_r
-
-  /* The getopt_data structure is for reentrancy. Its members are similar to
-     the externally-defined variables.  */
-  typedef struct getopt_data
-  {
-    char *optarg;
-    int optind, opterr, optopt, optwhere;
-  } getopt_data;
-
-#endif /* __need_getopt_newlib */
-
-  /* externally-defined variables */
-  extern char *optarg;
-  extern int optind;
-  extern int opterr;
-  extern int optopt;
-
-  /* function prototypes */
-  int _EXFUN (getopt,
-	      (int __argc, char *const __argv[], const char *__optstring));
-
-  int _EXFUN (getopt_long,
-	      (int __argc, char *const __argv[], const char *__shortopts,
-	       const struct option * __longopts, int *__longind));
-
-  int _EXFUN (getopt_long_only,
-	      (int __argc, char *const __argv[], const char *__shortopts,
-	       const struct option * __longopts, int *__longind));
-
-#ifdef __need_getopt_newlib
-  int _EXFUN (__getopt_r,
-	      (int __argc, char *const __argv[], const char *__optstring,
-	       struct getopt_data * __data));
-
-  int _EXFUN (__getopt_long_r,
-	      (int __argc, char *const __argv[], const char *__shortopts,
-	       const struct option * __longopts, int *__longind,
-	       struct getopt_data * __data));
-
-  int _EXFUN (__getopt_long_only_r,
-	      (int __argc, char *const __argv[], const char *__shortopts,
-	       const struct option * __longopts, int *__longind,
-	       struct getopt_data * __data));
-#endif /* __need_getopt_newlib */
-
-#ifdef __cplusplus
-};
-
-#endif /* __cplusplus  */
-
-#endif /* GETOPT_H */
-
-/* END OF FILE getopt.h */
diff --git a/tools/sdk/include/newlib/glob.h b/tools/sdk/include/newlib/glob.h
deleted file mode 100644
index 7a300e69d46..00000000000
--- a/tools/sdk/include/newlib/glob.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 1989, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * Guido van Rossum.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)glob.h	8.1 (Berkeley) 6/2/93
- * $FreeBSD: src/include/glob.h,v 1.6 2002/03/23 17:24:53 imp Exp $
- */
-
-#ifndef _GLOB_H_
-#define	_GLOB_H_
-
-#include <sys/cdefs.h>
-
-struct stat;
-typedef struct {
-	int gl_pathc;		/* Count of total paths so far. */
-	int gl_matchc;		/* Count of paths matching pattern. */
-	int gl_offs;		/* Reserved at beginning of gl_pathv. */
-	int gl_flags;		/* Copy of flags parameter to glob. */
-	char **gl_pathv;	/* List of paths matching pattern. */
-				/* Copy of errfunc parameter to glob. */
-	int (*gl_errfunc)(const char *, int);
-
-	/*
-	 * Alternate filesystem access methods for glob; replacement
-	 * versions of closedir(3), readdir(3), opendir(3), stat(2)
-	 * and lstat(2).
-	 */
-	void (*gl_closedir)(void *);
-	struct dirent *(*gl_readdir)(void *);
-	void *(*gl_opendir)(const char *);
-	int (*gl_lstat)(const char *, struct stat *);
-	int (*gl_stat)(const char *, struct stat *);
-} glob_t;
-
-#define	GLOB_APPEND	0x0001	/* Append to output from previous call. */
-#define	GLOB_DOOFFS	0x0002	/* Use gl_offs. */
-#define	GLOB_ERR	0x0004	/* Return on error. */
-#define	GLOB_MARK	0x0008	/* Append / to matching directories. */
-#define	GLOB_NOCHECK	0x0010	/* Return pattern itself if nothing matches. */
-#define	GLOB_NOSORT	0x0020	/* Don't sort. */
-
-#define	GLOB_ALTDIRFUNC	0x0040	/* Use alternately specified directory funcs. */
-#define	GLOB_BRACE	0x0080	/* Expand braces ala csh. */
-#define	GLOB_MAGCHAR	0x0100	/* Pattern had globbing characters. */
-#define	GLOB_NOMAGIC	0x0200	/* GLOB_NOCHECK without magic chars (csh). */
-#define	GLOB_QUOTE	0x0400	/* Quote special chars with \. */
-#define	GLOB_TILDE	0x0800	/* Expand tilde names from the passwd file. */
-#define	GLOB_LIMIT	0x1000	/* limit number of returned paths */
-
-/* backwards compatibility, this is the old name for this option */
-#define GLOB_MAXPATH	GLOB_LIMIT
-
-#define	GLOB_NOSPACE	(-1)	/* Malloc call failed. */
-#define	GLOB_ABEND	(-2)	/* Unignored error. */
-
-__BEGIN_DECLS
-int	glob(const char *__restrict, int, int (*)(const char *, int), 
-		glob_t *__restrict);
-void	globfree(glob_t *);
-__END_DECLS
-
-#endif /* !_GLOB_H_ */
diff --git a/tools/sdk/include/newlib/grp.h b/tools/sdk/include/newlib/grp.h
deleted file mode 100644
index c3a5a676c89..00000000000
--- a/tools/sdk/include/newlib/grp.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*	$NetBSD: grp.h,v 1.7 1995/04/29 05:30:40 cgd Exp $	*/
-
-/*-
- * Copyright (c) 1989, 1993
- *	The Regents of the University of California.  All rights reserved.
- * (c) UNIX System Laboratories, Inc.
- * All or some portions of this file are derived from material licensed
- * to the University of California by American Telephone and Telegraph
- * Co. or Unix System Laboratories, Inc. and are reproduced herein with
- * the permission of UNIX System Laboratories, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)grp.h	8.2 (Berkeley) 1/21/94
- */
-
-#ifndef _GRP_H_
-#define	_GRP_H_
-
-#include <sys/cdefs.h>
-#include <sys/types.h>
-#ifdef __CYGWIN__
-#include <cygwin/grp.h>
-#endif
-
-#if !defined(_POSIX_SOURCE) && !defined(_XOPEN_SOURCE)
-#define	_PATH_GROUP		"/etc/group"
-#endif
-
-struct group {
-	char	*gr_name;		/* group name */
-	char	*gr_passwd;		/* group password */
-	gid_t	gr_gid;			/* group id */
-	char	**gr_mem;		/* group members */
-};
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef __INSIDE_CYGWIN__
-struct group	*getgrgid (gid_t);
-struct group	*getgrnam (const char *);
-int		 getgrnam_r (const char *, struct group *,
-			char *, size_t, struct group **);
-int		 getgrgid_r (gid_t, struct group *,
-			char *, size_t, struct group **);
-#ifndef _POSIX_SOURCE
-struct group	*getgrent (void);
-void		 setgrent (void);
-void		 endgrent (void);
-#ifndef __CYGWIN__
-void		 setgrfile (const char *);
-#endif /* !__CYGWIN__ */
-#ifndef _XOPEN_SOURCE
-#ifndef __CYGWIN__
-char		*group_from_gid (gid_t, int);
-int		 setgroupent (int);
-#endif /* !__CYGWIN__ */
-int		 initgroups (const char *, gid_t);
-#endif /* !_XOPEN_SOURCE */
-#endif /* !_POSIX_SOURCE */
-#endif /* !__INSIDE_CYGWIN__ */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !_GRP_H_ */
diff --git a/tools/sdk/include/newlib/iconv.h b/tools/sdk/include/newlib/iconv.h
deleted file mode 100644
index 4c023e9df77..00000000000
--- a/tools/sdk/include/newlib/iconv.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2003-2004, Artem B. Bityuckiy, SoftMine Corporation.
- * Rights transferred to Franklin Electronic Publishers.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-#ifndef _ICONV_H_
-#define _ICONV_H_
-
-#include <_ansi.h>
-#include <reent.h>
-#include <sys/types.h>
-#include <sys/_types.h>
-
-/* iconv_t: charset conversion descriptor type */
-typedef _iconv_t iconv_t;
-
-_BEGIN_STD_C
-
-#ifndef _REENT_ONLY
-iconv_t
-_EXFUN(iconv_open, (_CONST char *, _CONST char *));
-
-size_t
-_EXFUN(iconv, (iconv_t, char **__restrict, size_t *__restrict, 
-               char **__restrict, size_t *__restrict));
-
-int
-_EXFUN(iconv_close, (iconv_t));
-#endif
-
-iconv_t
-_EXFUN(_iconv_open_r, (struct _reent *, _CONST char *, _CONST char *));
-
-size_t
-_EXFUN(_iconv_r, (struct _reent *, iconv_t, _CONST char **,
-                  size_t *, char **, size_t *));
-
-int
-_EXFUN(_iconv_close_r, (struct _reent *, iconv_t));
-
-_END_STD_C
-
-#endif /* #ifndef _ICONV_H_ */
diff --git a/tools/sdk/include/newlib/ieeefp.h b/tools/sdk/include/newlib/ieeefp.h
deleted file mode 100644
index 0b06fb7861e..00000000000
--- a/tools/sdk/include/newlib/ieeefp.h
+++ /dev/null
@@ -1,256 +0,0 @@
-#ifndef _IEEE_FP_H_
-#define _IEEE_FP_H_
-
-#include "_ansi.h"
-
-#include <machine/ieeefp.h>
-
-_BEGIN_STD_C
-
-/* FIXME FIXME FIXME:
-   Neither of __ieee_{float,double}_shape_tape seem to be used anywhere
-   except in libm/test.  If that is the case, please delete these from here.
-   If that is not the case, please insert documentation here describing why
-   they're needed.  */
-
-#ifdef __IEEE_BIG_ENDIAN
-
-typedef union 
-{
-  double value;
-  struct 
-  {
-    unsigned int sign : 1;
-    unsigned int exponent: 11;
-    unsigned int fraction0:4;
-    unsigned int fraction1:16;
-    unsigned int fraction2:16;
-    unsigned int fraction3:16;
-    
-  } number;
-  struct 
-  {
-    unsigned int sign : 1;
-    unsigned int exponent: 11;
-    unsigned int quiet:1;
-    unsigned int function0:3;
-    unsigned int function1:16;
-    unsigned int function2:16;
-    unsigned int function3:16;
-  } nan;
-  struct 
-  {
-    unsigned long msw;
-    unsigned long lsw;
-  } parts;
-    long aslong[2];
-} __ieee_double_shape_type;
-
-#endif
-
-#ifdef __IEEE_LITTLE_ENDIAN
-
-typedef union 
-{
-  double value;
-  struct 
-  {
-#ifdef __SMALL_BITFIELDS
-    unsigned int fraction3:16;
-    unsigned int fraction2:16;
-    unsigned int fraction1:16;
-    unsigned int fraction0: 4;
-#else
-    unsigned int fraction1:32;
-    unsigned int fraction0:20;
-#endif
-    unsigned int exponent :11;
-    unsigned int sign     : 1;
-  } number;
-  struct 
-  {
-#ifdef __SMALL_BITFIELDS
-    unsigned int function3:16;
-    unsigned int function2:16;
-    unsigned int function1:16;
-    unsigned int function0:3;
-#else
-    unsigned int function1:32;
-    unsigned int function0:19;
-#endif
-    unsigned int quiet:1;
-    unsigned int exponent: 11;
-    unsigned int sign : 1;
-  } nan;
-  struct 
-  {
-    unsigned long lsw;
-    unsigned long msw;
-  } parts;
-
-  long aslong[2];
-
-} __ieee_double_shape_type;
-
-#endif
-
-#ifdef __IEEE_BIG_ENDIAN
-
-typedef union
-{
-  float value;
-  struct 
-  {
-    unsigned int sign : 1;
-    unsigned int exponent: 8;
-    unsigned int fraction0: 7;
-    unsigned int fraction1: 16;
-  } number;
-  struct 
-  {
-    unsigned int sign:1;
-    unsigned int exponent:8;
-    unsigned int quiet:1;
-    unsigned int function0:6;
-    unsigned int function1:16;
-  } nan;
-  long p1;
-  
-} __ieee_float_shape_type;
-
-#endif
-
-#ifdef __IEEE_LITTLE_ENDIAN
-
-typedef union
-{
-  float value;
-  struct 
-  {
-    unsigned int fraction0: 7;
-    unsigned int fraction1: 16;
-    unsigned int exponent: 8;
-    unsigned int sign : 1;
-  } number;
-  struct 
-  {
-    unsigned int function1:16;
-    unsigned int function0:6;
-    unsigned int quiet:1;
-    unsigned int exponent:8;
-    unsigned int sign:1;
-  } nan;
-  long p1;
-  
-} __ieee_float_shape_type;
-
-#endif
-
-
-
-
-
-/* FLOATING ROUNDING */
-
-typedef int fp_rnd;
-#define FP_RN 0 	/* Round to nearest 		*/
-#define FP_RM 1		/* Round down 			*/
-#define FP_RP 2		/* Round up 			*/
-#define FP_RZ 3		/* Round to zero (trunate) 	*/
-
-fp_rnd _EXFUN(fpgetround,(void));
-fp_rnd _EXFUN(fpsetround, (fp_rnd));
-
-/* EXCEPTIONS */
-
-typedef int fp_except;
-#define FP_X_INV 0x10	/* Invalid operation 		*/
-#define FP_X_DX  0x80	/* Divide by zero		*/
-#define FP_X_OFL 0x04	/* Overflow exception		*/
-#define FP_X_UFL 0x02	/* Underflow exception		*/
-#define FP_X_IMP 0x01	/* imprecise exception		*/
-
-fp_except _EXFUN(fpgetmask,(void));
-fp_except _EXFUN(fpsetmask,(fp_except));
-fp_except _EXFUN(fpgetsticky,(void));
-fp_except _EXFUN(fpsetsticky, (fp_except));
-
-/* INTEGER ROUNDING */
-
-typedef int fp_rdi;
-#define FP_RDI_TOZ 0	/* Round to Zero 		*/
-#define FP_RDI_RD  1	/* Follow float mode		*/
-
-fp_rdi _EXFUN(fpgetroundtoi,(void));
-fp_rdi _EXFUN(fpsetroundtoi,(fp_rdi));
-
-#undef isnan
-#undef isinf
-
-int _EXFUN(isnan, (double));
-int _EXFUN(isinf, (double));
-int _EXFUN(finite, (double));
-
-
-
-int _EXFUN(isnanf, (float));
-int _EXFUN(isinff, (float));
-int _EXFUN(finitef, (float));
-
-#define __IEEE_DBL_EXPBIAS 1023
-#define __IEEE_FLT_EXPBIAS 127
-
-#define __IEEE_DBL_EXPLEN 11
-#define __IEEE_FLT_EXPLEN 8
-
-
-#define __IEEE_DBL_FRACLEN (64 - (__IEEE_DBL_EXPLEN + 1))
-#define __IEEE_FLT_FRACLEN (32 - (__IEEE_FLT_EXPLEN + 1))
-
-#define __IEEE_DBL_MAXPOWTWO	((double)(1L << 32 - 2) * (1L << (32-11) - 32 + 1))
-#define __IEEE_FLT_MAXPOWTWO	((float)(1L << (32-8) - 1))
-
-#define __IEEE_DBL_NAN_EXP 0x7ff
-#define __IEEE_FLT_NAN_EXP 0xff
-
-#ifndef __ieeefp_isnanf
-#define __ieeefp_isnanf(x) (((*(long *)&(x) & 0x7f800000L)==0x7f800000L) && \
-			    ((*(long *)&(x) & 0x007fffffL)!=0000000000L))
-#endif
-#define isnanf(x)	__ieeefp_isnanf(x)
-
-#ifndef __ieeefp_isinff
-#define __ieeefp_isinff(x) (((*(long *)&(x) & 0x7f800000L)==0x7f800000L) && \
-			    ((*(long *)&(x) & 0x007fffffL)==0000000000L))
-#endif
-#define isinff(x)	__ieeefp_isinff(x)
-
-#ifndef __ieeefp_finitef
-#define __ieeefp_finitef(x) (((*(long *)&(x) & 0x7f800000L)!=0x7f800000L))
-#endif
-#define finitef(x)	__ieeefp_finitef(x)
-
-#ifdef _DOUBLE_IS_32BITS
-#undef __IEEE_DBL_EXPBIAS
-#define __IEEE_DBL_EXPBIAS __IEEE_FLT_EXPBIAS
-
-#undef __IEEE_DBL_EXPLEN
-#define __IEEE_DBL_EXPLEN __IEEE_FLT_EXPLEN
-
-#undef __IEEE_DBL_FRACLEN
-#define __IEEE_DBL_FRACLEN __IEEE_FLT_FRACLEN
-
-#undef __IEEE_DBL_MAXPOWTWO
-#define __IEEE_DBL_MAXPOWTWO __IEEE_FLT_MAXPOWTWO
-
-#undef __IEEE_DBL_NAN_EXP
-#define __IEEE_DBL_NAN_EXP __IEEE_FLT_NAN_EXP
-
-#undef __ieee_double_shape_type
-#define __ieee_double_shape_type __ieee_float_shape_type
-
-#endif /* _DOUBLE_IS_32BITS */
-
-_END_STD_C
-
-#endif /* _IEEE_FP_H_ */
diff --git a/tools/sdk/include/newlib/inttypes.h b/tools/sdk/include/newlib/inttypes.h
deleted file mode 100644
index 39bf1351131..00000000000
--- a/tools/sdk/include/newlib/inttypes.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright (c) 2004, 2005 by
- * Ralf Corsepius, Ulm/Germany. All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software
- * is freely granted, provided that this notice is preserved.
- */
-
-/**
- *  @file  inttypes.h
- */
-
-#ifndef _INTTYPES_H
-#define _INTTYPES_H
-
-#include <newlib.h>
-#include <sys/_intsup.h>
-#include <stdint.h>
-#define __need_wchar_t
-#include <stddef.h>
-
-#define __STRINGIFY(a) #a
-
-/* 8-bit types */
-#define __PRI8(x) __STRINGIFY(x)
-
-/* NOTICE: scanning 8-bit types requires use of the hh specifier
- * which is only supported on newlib platforms that
- * are built with C99 I/O format support enabled.  If the flag in
- * newlib.h hasn't been set during configuration to indicate this, the 8-bit
- * scanning format macros are disabled here as they result in undefined
- * behaviour which can include memory overwrite.  Overriding the flag after the
- * library has been built is not recommended as it will expose the underlying
- * undefined behaviour.
- */
-
-#if defined(_WANT_IO_C99_FORMATS)
-  #define __SCN8(x) __STRINGIFY(hh##x)
-#endif /* _WANT_IO_C99_FORMATS */
-
-
-#define PRId8		__PRI8(d)
-#define PRIi8		__PRI8(i)
-#define PRIo8		__PRI8(o)
-#define PRIu8		__PRI8(u)
-#define PRIx8		__PRI8(x)
-#define PRIX8		__PRI8(X)
-
-/* Macros below are only enabled for a newlib built with C99 I/O format support. */
-#if defined(_WANT_IO_C99_FORMATS)
-
-#define SCNd8		__SCN8(d)
-#define SCNi8		__SCN8(i)
-#define SCNo8		__SCN8(o)
-#define SCNu8		__SCN8(u)
-#define SCNx8		__SCN8(x)
-
-#endif /* _WANT_IO_C99_FORMATS */
-
-
-#define PRIdLEAST8	__PRI8(d)
-#define PRIiLEAST8	__PRI8(i)
-#define PRIoLEAST8	__PRI8(o)
-#define PRIuLEAST8	__PRI8(u)
-#define PRIxLEAST8	__PRI8(x)
-#define PRIXLEAST8	__PRI8(X)
-
-/* Macros below are only enabled for a newlib built with C99 I/O format support. */
-#if defined(_WANT_IO_C99_FORMATS)
-
-  #define SCNdLEAST8	__SCN8(d)
-  #define SCNiLEAST8	__SCN8(i)
-  #define SCNoLEAST8	__SCN8(o)
-  #define SCNuLEAST8	__SCN8(u)
-  #define SCNxLEAST8	__SCN8(x)
-
-#endif /* _WANT_IO_C99_FORMATS */
-
-#define PRIdFAST8	__PRI8(d)
-#define PRIiFAST8	__PRI8(i)
-#define PRIoFAST8	__PRI8(o)
-#define PRIuFAST8	__PRI8(u)
-#define PRIxFAST8	__PRI8(x)
-#define PRIXFAST8	__PRI8(X)
-
-/* Macros below are only enabled for a newlib built with C99 I/O format support. */
-#if defined(_WANT_IO_C99_FORMATS)
-
-  #define SCNdFAST8	__SCN8(d)
-  #define SCNiFAST8	__SCN8(i)
-  #define SCNoFAST8	__SCN8(o)
-  #define SCNuFAST8	__SCN8(u)
-  #define SCNxFAST8	__SCN8(x)
-
-#endif /* _WANT_IO_C99_FORMATS */
-
-/* 16-bit types */
-#define __PRI16(x) __STRINGIFY(x)
-#define __SCN16(x) __STRINGIFY(h##x)
-
-
-#define PRId16		__PRI16(d)
-#define PRIi16		__PRI16(i)
-#define PRIo16		__PRI16(o)
-#define PRIu16		__PRI16(u)
-#define PRIx16		__PRI16(x)
-#define PRIX16		__PRI16(X)
-
-#define SCNd16		__SCN16(d)
-#define SCNi16		__SCN16(i)
-#define SCNo16		__SCN16(o)
-#define SCNu16		__SCN16(u)
-#define SCNx16		__SCN16(x)
-
-
-#define PRIdLEAST16	__PRI16(d)
-#define PRIiLEAST16	__PRI16(i)
-#define PRIoLEAST16	__PRI16(o)
-#define PRIuLEAST16	__PRI16(u)
-#define PRIxLEAST16	__PRI16(x)
-#define PRIXLEAST16	__PRI16(X)
-
-#define SCNdLEAST16	__SCN16(d)
-#define SCNiLEAST16	__SCN16(i)
-#define SCNoLEAST16	__SCN16(o)
-#define SCNuLEAST16	__SCN16(u)
-#define SCNxLEAST16	__SCN16(x)
-
-
-#define PRIdFAST16	__PRI16(d)
-#define PRIiFAST16	__PRI16(i)
-#define PRIoFAST16	__PRI16(o)
-#define PRIuFAST16	__PRI16(u)
-#define PRIxFAST16	__PRI16(x)
-#define PRIXFAST16	__PRI16(X)
-
-#define SCNdFAST16	__SCN16(d)
-#define SCNiFAST16	__SCN16(i)
-#define SCNoFAST16	__SCN16(o)
-#define SCNuFAST16	__SCN16(u)
-#define SCNxFAST16	__SCN16(x)
-
-/* 32-bit types */
-#if __have_long32
-#define __PRI32(x) __STRINGIFY(l##x)
-#define __SCN32(x) __STRINGIFY(l##x)
-#else
-#define __PRI32(x) __STRINGIFY(x)
-#define __SCN32(x) __STRINGIFY(x)
-#endif
-
-#define PRId32		__PRI32(d)
-#define PRIi32		__PRI32(i)
-#define PRIo32		__PRI32(o)
-#define PRIu32		__PRI32(u)
-#define PRIx32		__PRI32(x)
-#define PRIX32		__PRI32(X)
-
-#define SCNd32		__SCN32(d)
-#define SCNi32		__SCN32(i)
-#define SCNo32		__SCN32(o)
-#define SCNu32		__SCN32(u)
-#define SCNx32		__SCN32(x)
-
-
-#define PRIdLEAST32	__PRI32(d)
-#define PRIiLEAST32	__PRI32(i)
-#define PRIoLEAST32	__PRI32(o)
-#define PRIuLEAST32	__PRI32(u)
-#define PRIxLEAST32	__PRI32(x)
-#define PRIXLEAST32	__PRI32(X)
-
-#define SCNdLEAST32	__SCN32(d)
-#define SCNiLEAST32	__SCN32(i)
-#define SCNoLEAST32	__SCN32(o)
-#define SCNuLEAST32	__SCN32(u)
-#define SCNxLEAST32	__SCN32(x)
-
-
-#define PRIdFAST32	__PRI32(d)
-#define PRIiFAST32	__PRI32(i)
-#define PRIoFAST32	__PRI32(o)
-#define PRIuFAST32	__PRI32(u)
-#define PRIxFAST32	__PRI32(x)
-#define PRIXFAST32	__PRI32(X)
-
-#define SCNdFAST32	__SCN32(d)
-#define SCNiFAST32	__SCN32(i)
-#define SCNoFAST32	__SCN32(o)
-#define SCNuFAST32	__SCN32(u)
-#define SCNxFAST32	__SCN32(x)
-
-
-/* 64-bit types */
-#if __have_long64
-#define __PRI64(x) __STRINGIFY(l##x)
-#define __SCN64(x) __STRINGIFY(l##x)
-#elif __have_longlong64
-#define __PRI64(x) __STRINGIFY(ll##x)
-#define __SCN64(x) __STRINGIFY(ll##x)
-#else
-#define __PRI64(x) __STRINGIFY(x)
-#define __SCN64(x) __STRINGIFY(x)
-#endif
-
-#define PRId64		__PRI64(d)
-#define PRIi64		__PRI64(i)
-#define PRIo64		__PRI64(o)
-#define PRIu64		__PRI64(u)
-#define PRIx64		__PRI64(x)
-#define PRIX64		__PRI64(X)
-
-#define SCNd64		__SCN64(d)
-#define SCNi64		__SCN64(i)
-#define SCNo64		__SCN64(o)
-#define SCNu64		__SCN64(u)
-#define SCNx64		__SCN64(x)
-
-#if __int64_t_defined
-#define PRIdLEAST64	__PRI64(d)
-#define PRIiLEAST64	__PRI64(i)
-#define PRIoLEAST64	__PRI64(o)
-#define PRIuLEAST64	__PRI64(u)
-#define PRIxLEAST64	__PRI64(x)
-#define PRIXLEAST64	__PRI64(X)
-
-#define SCNdLEAST64	__SCN64(d)
-#define SCNiLEAST64	__SCN64(i)
-#define SCNoLEAST64	__SCN64(o)
-#define SCNuLEAST64	__SCN64(u)
-#define SCNxLEAST64	__SCN64(x)
-
-
-#define PRIdFAST64	__PRI64(d)
-#define PRIiFAST64	__PRI64(i)
-#define PRIoFAST64	__PRI64(o)
-#define PRIuFAST64	__PRI64(u)
-#define PRIxFAST64	__PRI64(x)
-#define PRIXFAST64	__PRI64(X)
-
-#define SCNdFAST64	__SCN64(d)
-#define SCNiFAST64	__SCN64(i)
-#define SCNoFAST64	__SCN64(o)
-#define SCNuFAST64	__SCN64(u)
-#define SCNxFAST64	__SCN64(x)
-#endif
-
-/* max-bit types */
-#if __have_long64
-#define __PRIMAX(x) __STRINGIFY(l##x)
-#define __SCNMAX(x) __STRINGIFY(l##x)
-#elif __have_longlong64
-#define __PRIMAX(x) __STRINGIFY(ll##x)
-#define __SCNMAX(x) __STRINGIFY(ll##x)
-#else
-#define __PRIMAX(x) __STRINGIFY(x)
-#define __SCNMAX(x) __STRINGIFY(x)
-#endif
-
-#define PRIdMAX		__PRIMAX(d)
-#define PRIiMAX		__PRIMAX(i)
-#define PRIoMAX		__PRIMAX(o)
-#define PRIuMAX		__PRIMAX(u)
-#define PRIxMAX		__PRIMAX(x)
-#define PRIXMAX		__PRIMAX(X)
-
-#define SCNdMAX		__SCNMAX(d)
-#define SCNiMAX		__SCNMAX(i)
-#define SCNoMAX		__SCNMAX(o)
-#define SCNuMAX		__SCNMAX(u)
-#define SCNxMAX		__SCNMAX(x)
-
-/* ptr types */
-#if defined(_UINTPTR_EQ_ULONGLONG)
-# define __PRIPTR(x) __STRINGIFY(ll##x)
-# define __SCNPTR(x) __STRINGIFY(ll##x)
-#elif defined(_UINTPTR_EQ_ULONG)
-# define __PRIPTR(x) __STRINGIFY(l##x)
-# define __SCNPTR(x) __STRINGIFY(l##x)
-#else
-# define __PRIPTR(x) __STRINGIFY(x)
-# define __SCNPTR(x) __STRINGIFY(x)
-#endif
-
-#define PRIdPTR		__PRIPTR(d)
-#define PRIiPTR		__PRIPTR(i)
-#define PRIoPTR		__PRIPTR(o)
-#define PRIuPTR		__PRIPTR(u)
-#define PRIxPTR		__PRIPTR(x)
-#define PRIXPTR		__PRIPTR(X)
-
-#define SCNdPTR		__SCNPTR(d)
-#define SCNiPTR		__SCNPTR(i)
-#define SCNoPTR		__SCNPTR(o)
-#define SCNuPTR		__SCNPTR(u)
-#define SCNxPTR		__SCNPTR(x)
-
-
-typedef struct {
-  intmax_t	quot;
-  intmax_t	rem;
-} imaxdiv_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern intmax_t  imaxabs(intmax_t j);
-extern imaxdiv_t imaxdiv(intmax_t numer, intmax_t denomer);
-extern intmax_t  strtoimax(const char *__restrict, char **__restrict, int);
-extern uintmax_t strtoumax(const char *__restrict, char **__restrict, int);
-extern intmax_t  wcstoimax(const wchar_t *__restrict, wchar_t **__restrict, int);
-extern uintmax_t wcstoumax(const wchar_t *__restrict, wchar_t **__restrict, int);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/newlib/langinfo.h b/tools/sdk/include/newlib/langinfo.h
deleted file mode 100644
index 9040adeff5e..00000000000
--- a/tools/sdk/include/newlib/langinfo.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/*-
- * Copyright (c) 2001 Alexey Zelkin <phantom@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD: src/include/langinfo.h,v 1.5 2002/03/23 17:24:53 imp Exp $
- */
-
-#ifndef _LANGINFO_H_
-#define	_LANGINFO_H_
-
-#include <newlib.h>
-#include <sys/config.h>
-#include <sys/cdefs.h>
-
-typedef int nl_item;
-
-enum __nl_item
-{
-  /* POSIX and BSD defined items have to stick to the original values
-     to maintain backward compatibility. */
-  _NL_CTYPE_CODESET_NAME = 0,	/* codeset name */
-#define CODESET _NL_CTYPE_CODESET_NAME
-  D_T_FMT,			/* string for formatting date and time */
-#define D_T_FMT D_T_FMT
-  D_FMT,			/* date format string */
-#define D_FMT D_FMT
-  T_FMT,			/* time format string */
-#define T_FMT T_FMT
-  T_FMT_AMPM,			/* a.m. or p.m. time formatting string */
-#define T_FMT_AMPM T_FMT_AMPM
-  AM_STR,			/* Ante Meridian affix */
-#define AM_STR AM_STR
-  PM_STR,			/* Post Meridian affix */
-#define PM_STR PM_STR
-
-/* week day names */
-  DAY_1,
-#define DAY_1 DAY_1
-  DAY_2,
-#define DAY_2 DAY_2
-  DAY_3,
-#define DAY_3 DAY_3
-  DAY_4,
-#define DAY_4 DAY_4
-  DAY_5,
-#define DAY_5 DAY_5
-  DAY_6,
-#define DAY_6 DAY_6
-  DAY_7,
-#define DAY_7 DAY_7
-
-/* abbreviated week day names */
-  ABDAY_1,
-#define ABDAY_1 ABDAY_1
-  ABDAY_2,
-#define ABDAY_2 ABDAY_2
-  ABDAY_3,
-#define ABDAY_3 ABDAY_3
-  ABDAY_4,
-#define ABDAY_4 ABDAY_4
-  ABDAY_5,
-#define ABDAY_5 ABDAY_5
-  ABDAY_6,
-#define ABDAY_6 ABDAY_6
-  ABDAY_7,
-#define ABDAY_7 ABDAY_7
-
-/* month names */
-  MON_1,
-#define MON_1 MON_1
-  MON_2,
-#define MON_2 MON_2
-  MON_3,
-#define MON_3 MON_3
-  MON_4,
-#define MON_4 MON_4
-  MON_5,
-#define MON_5 MON_5
-  MON_6,
-#define MON_6 MON_6
-  MON_7,
-#define MON_7 MON_7
-  MON_8,
-#define MON_8 MON_8
-  MON_9,
-#define MON_9 MON_9
-  MON_10,
-#define MON_10 MON_10
-  MON_11,
-#define MON_11 MON_11
-  MON_12,
-#define MON_12 MON_12
-
-/* abbreviated month names */
-  ABMON_1,
-#define ABMON_1 ABMON_1
-  ABMON_2,
-#define ABMON_2 ABMON_2
-  ABMON_3,
-#define ABMON_3 ABMON_3
-  ABMON_4,
-#define ABMON_4 ABMON_4
-  ABMON_5,
-#define ABMON_5 ABMON_5
-  ABMON_6,
-#define ABMON_6 ABMON_6
-  ABMON_7,
-#define ABMON_7 ABMON_7
-  ABMON_8,
-#define ABMON_8 ABMON_8
-  ABMON_9,
-#define ABMON_9 ABMON_9
-  ABMON_10,
-#define ABMON_10 ABMON_10
-  ABMON_11,
-#define ABMON_11 ABMON_11
-  ABMON_12,
-#define ABMON_12 ABMON_12
-
-  ERA,				/* era description segments */
-#define ERA ERA
-  ERA_D_FMT,			/* era date format string */
-#define ERA_D_FMT ERA_D_FMT
-  ERA_D_T_FMT,			/* era date and time format string */
-#define ERA_D_T_FMT ERA_D_T_FMT
-  ERA_T_FMT,			/* era time format string */
-#define ERA_T_FMT ERA_T_FMT
-  ALT_DIGITS,			/* alternative symbols for digits */
-#define ALT_DIGITS ALT_DIGITS
-
-  RADIXCHAR,			/* radix char */
-#define RADIXCHAR RADIXCHAR
-  THOUSEP,			/* separator for thousands */
-#define THOUSEP THOUSEP
-
-  YESEXPR,			/* affirmative response expression */
-#define YESEXPR YESEXPR
-  NOEXPR,			/* negative response expression */
-#define NOEXPR NOEXPR
-  YESSTR,			/* affirmative response for yes/no queries */
-#define YESSTR YESSTR
-  NOSTR,			/* negative response for yes/no queries */
-#define NOSTR NOSTR
-
-  CRNCYSTR,			/* currency symbol */
-#define CRNCYSTR CRNCYSTR
-
-  D_MD_ORDER,			/* month/day order (BSD extension) */
-#define D_MD_ORDER D_MD_ORDER
-
-  _NL_TIME_DATE_FMT = 84,	/* date fmt used by date(1) (GNU extension) */
-#define _DATE_FMT _NL_TIME_DATE_FMT
-
-#ifdef __HAVE_LOCALE_INFO__
-  _NL_CTYPE_MB_CUR_MAX,
-  _NL_MESSAGES_CODESET,
-
-#ifdef __HAVE_LOCALE_INFO_EXTENDED__
-
-  /* NOTE:
-  
-     Always maintain the order and position of existing entries!
-     Always append new entry to the list, prior to the definition
-     of _NL_LOCALE_EXTENDED_LAST_ENTRY. */
-
-  _NL_LOCALE_EXTENDED_FIRST_ENTRY,
-
-  _NL_CTYPE_OUTDIGITS0_MB,
-  _NL_CTYPE_OUTDIGITS1_MB,
-  _NL_CTYPE_OUTDIGITS2_MB,
-  _NL_CTYPE_OUTDIGITS3_MB,
-  _NL_CTYPE_OUTDIGITS4_MB,
-  _NL_CTYPE_OUTDIGITS5_MB,
-  _NL_CTYPE_OUTDIGITS6_MB,
-  _NL_CTYPE_OUTDIGITS7_MB,
-  _NL_CTYPE_OUTDIGITS8_MB,
-  _NL_CTYPE_OUTDIGITS9_MB,
-  _NL_CTYPE_OUTDIGITS0_WC,
-  _NL_CTYPE_OUTDIGITS1_WC,
-  _NL_CTYPE_OUTDIGITS2_WC,
-  _NL_CTYPE_OUTDIGITS3_WC,
-  _NL_CTYPE_OUTDIGITS4_WC,
-  _NL_CTYPE_OUTDIGITS5_WC,
-  _NL_CTYPE_OUTDIGITS6_WC,
-  _NL_CTYPE_OUTDIGITS7_WC,
-  _NL_CTYPE_OUTDIGITS8_WC,
-  _NL_CTYPE_OUTDIGITS9_WC,
-
-  _NL_TIME_CODESET,
-  _NL_TIME_WMON_1,
-  _NL_TIME_WMON_2,
-  _NL_TIME_WMON_3,
-  _NL_TIME_WMON_4,
-  _NL_TIME_WMON_5,
-  _NL_TIME_WMON_6,
-  _NL_TIME_WMON_7,
-  _NL_TIME_WMON_8,
-  _NL_TIME_WMON_9,
-  _NL_TIME_WMON_10,
-  _NL_TIME_WMON_11,
-  _NL_TIME_WMON_12,
-  _NL_TIME_WMONTH_1,
-  _NL_TIME_WMONTH_2,
-  _NL_TIME_WMONTH_3,
-  _NL_TIME_WMONTH_4,
-  _NL_TIME_WMONTH_5,
-  _NL_TIME_WMONTH_6,
-  _NL_TIME_WMONTH_7,
-  _NL_TIME_WMONTH_8,
-  _NL_TIME_WMONTH_9,
-  _NL_TIME_WMONTH_10,
-  _NL_TIME_WMONTH_11,
-  _NL_TIME_WMONTH_12,
-  _NL_TIME_WWDAY_1,
-  _NL_TIME_WWDAY_2,
-  _NL_TIME_WWDAY_3,
-  _NL_TIME_WWDAY_4,
-  _NL_TIME_WWDAY_5,
-  _NL_TIME_WWDAY_6,
-  _NL_TIME_WWDAY_7,
-  _NL_TIME_WWEEKDAY_1,
-  _NL_TIME_WWEEKDAY_2,
-  _NL_TIME_WWEEKDAY_3,
-  _NL_TIME_WWEEKDAY_4,
-  _NL_TIME_WWEEKDAY_5,
-  _NL_TIME_WWEEKDAY_6,
-  _NL_TIME_WWEEKDAY_7,
-  _NL_TIME_WT_FMT,
-  _NL_TIME_WD_FMT,
-  _NL_TIME_WD_T_FMT,
-  _NL_TIME_WAM_STR,
-  _NL_TIME_WPM_STR,
-  _NL_TIME_WDATE_FMT,
-  _NL_TIME_WT_FMT_AMPM,
-  _NL_TIME_WERA,
-  _NL_TIME_WERA_D_FMT,
-  _NL_TIME_WERA_D_T_FMT,
-  _NL_TIME_WERA_T_FMT,
-  _NL_TIME_WALT_DIGITS,
-
-  _NL_NUMERIC_CODESET,
-  _NL_NUMERIC_GROUPING,
-  _NL_NUMERIC_DECIMAL_POINT_WC,
-  _NL_NUMERIC_THOUSANDS_SEP_WC,
-
-  _NL_MONETARY_INT_CURR_SYMBOL,
-  _NL_MONETARY_CURRENCY_SYMBOL,
-  _NL_MONETARY_MON_DECIMAL_POINT,
-  _NL_MONETARY_MON_THOUSANDS_SEP,
-  _NL_MONETARY_MON_GROUPING,
-  _NL_MONETARY_POSITIVE_SIGN,
-  _NL_MONETARY_NEGATIVE_SIGN,
-  _NL_MONETARY_INT_FRAC_DIGITS,
-  _NL_MONETARY_FRAC_DIGITS,
-  _NL_MONETARY_P_CS_PRECEDES,
-  _NL_MONETARY_P_SEP_BY_SPACE,
-  _NL_MONETARY_N_CS_PRECEDES,
-  _NL_MONETARY_N_SEP_BY_SPACE,
-  _NL_MONETARY_P_SIGN_POSN,
-  _NL_MONETARY_N_SIGN_POSN,
-  _NL_MONETARY_INT_P_CS_PRECEDES,
-  _NL_MONETARY_INT_P_SEP_BY_SPACE,
-  _NL_MONETARY_INT_N_CS_PRECEDES,
-  _NL_MONETARY_INT_N_SEP_BY_SPACE,
-  _NL_MONETARY_INT_P_SIGN_POSN,
-  _NL_MONETARY_INT_N_SIGN_POSN,
-  _NL_MONETARY_CODESET,
-  _NL_MONETARY_WINT_CURR_SYMBOL,
-  _NL_MONETARY_WCURRENCY_SYMBOL,
-  _NL_MONETARY_WMON_DECIMAL_POINT,
-  _NL_MONETARY_WMON_THOUSANDS_SEP,
-  _NL_MONETARY_WPOSITIVE_SIGN,
-  _NL_MONETARY_WNEGATIVE_SIGN,
-
-  _NL_MESSAGES_WYESEXPR,
-  _NL_MESSAGES_WNOEXPR,
-  _NL_MESSAGES_WYESSTR,
-  _NL_MESSAGES_WNOSTR,
-
-  _NL_COLLATE_CODESET,
-
-  /* This MUST be the last entry since it's used to check for an array
-     index in nl_langinfo(). */
-  _NL_LOCALE_EXTENDED_LAST_ENTRY
-
-#endif /* __HAVE_LOCALE_INFO_EXTENDED__ */
-#endif /* __HAVE_LOCALE_INFO__ */
-
-};
-
-__BEGIN_DECLS
-char	*nl_langinfo(nl_item);
-__END_DECLS
-
-#endif /* !_LANGINFO_H_ */
diff --git a/tools/sdk/include/newlib/libgen.h b/tools/sdk/include/newlib/libgen.h
deleted file mode 100644
index abfab0e5c72..00000000000
--- a/tools/sdk/include/newlib/libgen.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * libgen.h - defined by XPG4
- */
-
-#ifndef _LIBGEN_H_
-#define _LIBGEN_H_
-
-#include "_ansi.h"
-#include <sys/reent.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-char      *_EXFUN(basename,     (char *));
-char      *_EXFUN(dirname,     (char *));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _LIBGEN_H_ */
-
diff --git a/tools/sdk/include/newlib/limits.h b/tools/sdk/include/newlib/limits.h
deleted file mode 100644
index 633b44593eb..00000000000
--- a/tools/sdk/include/newlib/limits.h
+++ /dev/null
@@ -1,146 +0,0 @@
-#ifndef _LIBC_LIMITS_H_
-# define _LIBC_LIMITS_H_	1
-
-#include <newlib.h>
-
-# ifdef _MB_LEN_MAX
-#  define MB_LEN_MAX	_MB_LEN_MAX
-# else
-#  define MB_LEN_MAX    1
-# endif
-
-/* Maximum number of positional arguments, if _WANT_IO_POS_ARGS.  */
-# ifndef NL_ARGMAX
-#  define NL_ARGMAX 32
-# endif
-
-/* if do not have #include_next support, then we
-   have to define the limits here. */
-# if !defined __GNUC__ || __GNUC__ < 2
-
-#  ifndef _LIMITS_H
-#   define _LIMITS_H	1
-
-#   include <sys/config.h>
-
-/* Number of bits in a `char'.  */
-#   undef CHAR_BIT
-#   define CHAR_BIT 8
-
-/* Minimum and maximum values a `signed char' can hold.  */
-#   undef SCHAR_MIN
-#   define SCHAR_MIN (-128)
-#   undef SCHAR_MAX
-#   define SCHAR_MAX 127
-
-/* Maximum value an `unsigned char' can hold.  (Minimum is 0).  */
-#   undef UCHAR_MAX
-#   define UCHAR_MAX 255
-
-/* Minimum and maximum values a `char' can hold.  */
-#   ifdef __CHAR_UNSIGNED__
-#    undef CHAR_MIN
-#    define CHAR_MIN 0
-#    undef CHAR_MAX
-#    define CHAR_MAX 255
-#   else
-#    undef CHAR_MIN
-#    define CHAR_MIN (-128)
-#    undef CHAR_MAX
-#    define CHAR_MAX 127
-#   endif
-
-/* Minimum and maximum values a `signed short int' can hold.  */
-#   undef SHRT_MIN
-/* For the sake of 16 bit hosts, we may not use -32768 */
-#   define SHRT_MIN (-32767-1)
-#   undef SHRT_MAX
-#   define SHRT_MAX 32767
-
-/* Maximum value an `unsigned short int' can hold.  (Minimum is 0).  */
-#   undef USHRT_MAX
-#   define USHRT_MAX 65535
-
-/* Minimum and maximum values a `signed int' can hold.  */
-#   ifndef __INT_MAX__
-#    define __INT_MAX__ 2147483647
-#   endif
-#   undef INT_MIN
-#   define INT_MIN (-INT_MAX-1)
-#   undef INT_MAX
-#   define INT_MAX __INT_MAX__
-
-/* Maximum value an `unsigned int' can hold.  (Minimum is 0).  */
-#   undef UINT_MAX
-#   define UINT_MAX (INT_MAX * 2U + 1)
-
-/* Minimum and maximum values a `signed long int' can hold.
-   (Same as `int').  */
-#   ifndef __LONG_MAX__
-#    if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) || defined (__sparcv9)
-#     define __LONG_MAX__ 9223372036854775807L
-#    else
-#     define __LONG_MAX__ 2147483647L
-#    endif /* __alpha__ || sparc64 */
-#   endif
-#   undef LONG_MIN
-#   define LONG_MIN (-LONG_MAX-1)
-#   undef LONG_MAX
-#   define LONG_MAX __LONG_MAX__
-
-/* Maximum value an `unsigned long int' can hold.  (Minimum is 0).  */
-#   undef ULONG_MAX
-#   define ULONG_MAX (LONG_MAX * 2UL + 1)
-
-#   ifndef __LONG_LONG_MAX__
-#    define __LONG_LONG_MAX__ 9223372036854775807LL
-#   endif
-
-#   if (defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) ||   \
-  (defined(__cplusplus) && __cplusplus >= 201103L)
-/* Minimum and maximum values a `signed long long int' can hold.  */
-#    undef LLONG_MIN
-#    define LLONG_MIN (-LLONG_MAX-1)
-#    undef LLONG_MAX
-#    define LLONG_MAX __LONG_LONG_MAX__
-
-/* Maximum value an `unsigned long long int' can hold.  (Minimum is 0).  */
-#    undef ULLONG_MAX
-#    define ULLONG_MAX (LLONG_MAX * 2ULL + 1)
-#   endif
-
-#  if defined (__GNU_LIBRARY__) ? defined (__USE_GNU) : !defined (__STRICT_ANSI__)
-/* Minimum and maximum values a `signed long long int' can hold.  */
-#    undef LONG_LONG_MIN
-#    define LONG_LONG_MIN (-LONG_LONG_MAX-1)
-#    undef LONG_LONG_MAX
-#    define LONG_LONG_MAX __LONG_LONG_MAX__
-
-/* Maximum value an `unsigned long long int' can hold.  (Minimum is 0).  */
-#    undef ULONG_LONG_MAX
-#    define ULONG_LONG_MAX (LONG_LONG_MAX * 2ULL + 1)
-#   endif
-
-#  endif /* _LIMITS_H  */
-# endif	 /* GCC 2.  */
-
-#endif	 /* !_LIBC_LIMITS_H_ */
-
-#if defined __GNUC__ && !defined _GCC_LIMITS_H_
-/* `_GCC_LIMITS_H_' is what GCC's file defines.  */
-# include_next <limits.h>
-#endif /* __GNUC__ && !_GCC_LIMITS_H_ */
-
-#ifndef _POSIX2_RE_DUP_MAX
-/* The maximum number of repeated occurrences of a regular expression
- *    permitted when using the interval notation `\{M,N\}'.  */
-#define _POSIX2_RE_DUP_MAX              255
-#endif /* _POSIX2_RE_DUP_MAX  */
-
-#ifndef ARG_MAX
-#define ARG_MAX		4096
-#endif
-
-#ifndef PATH_MAX
-#define PATH_MAX	1024
-#endif
diff --git a/tools/sdk/include/newlib/locale.h b/tools/sdk/include/newlib/locale.h
deleted file mode 100644
index cbd658e410c..00000000000
--- a/tools/sdk/include/newlib/locale.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
-	locale.h
-	Values appropriate for the formatting of monetary and other
-	numberic quantities.
-*/
-
-#ifndef _LOCALE_H_
-#define _LOCALE_H_
-
-#include "_ansi.h"
-
-#define __need_NULL
-#include <stddef.h>
-
-#define LC_ALL	    0
-#define LC_COLLATE  1
-#define LC_CTYPE    2
-#define LC_MONETARY 3
-#define LC_NUMERIC  4
-#define LC_TIME     5
-#define LC_MESSAGES 6
-
-_BEGIN_STD_C
-
-struct lconv
-{
-  char *decimal_point;
-  char *thousands_sep;
-  char *grouping;
-  char *int_curr_symbol;
-  char *currency_symbol;
-  char *mon_decimal_point;
-  char *mon_thousands_sep;
-  char *mon_grouping;
-  char *positive_sign;
-  char *negative_sign;
-  char int_frac_digits;
-  char frac_digits;
-  char p_cs_precedes;
-  char p_sep_by_space;
-  char n_cs_precedes;
-  char n_sep_by_space;
-  char p_sign_posn;
-  char n_sign_posn;
-  char int_n_cs_precedes;
-  char int_n_sep_by_space;
-  char int_n_sign_posn;
-  char int_p_cs_precedes;
-  char int_p_sep_by_space;
-  char int_p_sign_posn;
-};
-
-#ifndef _REENT_ONLY
-char *_EXFUN(setlocale,(int category, const char *locale));
-struct lconv *_EXFUN(localeconv,(void));
-#endif
-
-struct _reent;
-char *_EXFUN(_setlocale_r,(struct _reent *, int category, const char *locale));
-struct lconv *_EXFUN(_localeconv_r,(struct _reent *));
-
-_END_STD_C
-
-#endif /* _LOCALE_H_ */
diff --git a/tools/sdk/include/newlib/machine/_default_types.h b/tools/sdk/include/newlib/machine/_default_types.h
deleted file mode 100644
index 03bdc523e3c..00000000000
--- a/tools/sdk/include/newlib/machine/_default_types.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * _default_types implementation for xtensa lx106 arch
- *
- * Simplified version of generic _default_types.h, ignores gcc
- * built-in standard types.
- */
-
-#ifndef _MACHINE__DEFAULT_TYPES_H
-#define _MACHINE__DEFAULT_TYPES_H
-
-#include <sys/features.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef signed char __int8_t ;
-typedef unsigned char __uint8_t ;
-#define ___int8_t_defined 1
-
-typedef signed short __int16_t;
-typedef unsigned short __uint16_t;
-#define ___int16_t_defined 1
-
-typedef signed int __int32_t;
-typedef unsigned int __uint32_t;
-#define ___int32_t_defined 1
-
-typedef signed long long __int64_t;
-typedef unsigned long long __uint64_t;
-#define ___int64_t_defined 1
-
-typedef __int8_t __int_least8_t;
-typedef __uint8_t __uint_least8_t;
-#define ___int_least8_t_defined
-
-typedef __int16_t __int_least16_t;
-typedef __uint16_t __uint_least16_t;
-#define ___int_least16_t_defined
-
-typedef __int32_t __int_least32_t;
-typedef __uint32_t __uint_least32_t;
-#define ___int_least32_t_defined
-
-typedef __int64_t __int_least64_t;
-typedef __uint64_t __uint_least64_t;
-#define ___int_least64_t_defined
-
-typedef __INTPTR_TYPE__ __intptr_t;
-typedef __UINTPTR_TYPE__ __uintptr_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _MACHINE__DEFAULT_TYPES_H */
diff --git a/tools/sdk/include/newlib/machine/_types.h b/tools/sdk/include/newlib/machine/_types.h
deleted file mode 100644
index 17e6d51e3da..00000000000
--- a/tools/sdk/include/newlib/machine/_types.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- *  $Id$
- */
-
-#ifndef _MACHINE__TYPES_H
-#define _MACHINE__TYPES_H
-#include <machine/_default_types.h>
-#endif
diff --git a/tools/sdk/include/newlib/machine/ansi.h b/tools/sdk/include/newlib/machine/ansi.h
deleted file mode 100644
index 737b6d06666..00000000000
--- a/tools/sdk/include/newlib/machine/ansi.h
+++ /dev/null
@@ -1 +0,0 @@
-/* dummy header file to support BSD compiler */
diff --git a/tools/sdk/include/newlib/machine/endian.h b/tools/sdk/include/newlib/machine/endian.h
deleted file mode 100644
index 07ebc8f63a3..00000000000
--- a/tools/sdk/include/newlib/machine/endian.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __MACHINE_ENDIAN_H__
-
-#include <sys/config.h>
-
-#ifndef BIG_ENDIAN
-#define BIG_ENDIAN 4321
-#endif
-#ifndef LITTLE_ENDIAN
-#define LITTLE_ENDIAN 1234
-#endif
-
-#ifndef BYTE_ORDER
-#if defined(__IEEE_LITTLE_ENDIAN) || defined(__IEEE_BYTES_LITTLE_ENDIAN)
-#define BYTE_ORDER LITTLE_ENDIAN
-#else
-#define BYTE_ORDER BIG_ENDIAN
-#endif
-#endif
-
-#endif /* __MACHINE_ENDIAN_H__ */
diff --git a/tools/sdk/include/newlib/machine/fastmath.h b/tools/sdk/include/newlib/machine/fastmath.h
deleted file mode 100644
index b13befa228b..00000000000
--- a/tools/sdk/include/newlib/machine/fastmath.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#ifdef __sysvnecv70_target
-double EXFUN(fast_sin,(double));
-double EXFUN(fast_cos,(double));
-double EXFUN(fast_tan,(double));
-
-double EXFUN(fast_asin,(double));
-double EXFUN(fast_acos,(double));
-double EXFUN(fast_atan,(double));
-
-double EXFUN(fast_sinh,(double));
-double EXFUN(fast_cosh,(double));
-double EXFUN(fast_tanh,(double));
-
-double EXFUN(fast_asinh,(double));
-double EXFUN(fast_acosh,(double));
-double EXFUN(fast_atanh,(double));
-
-double EXFUN(fast_abs,(double));
-double EXFUN(fast_sqrt,(double));
-double EXFUN(fast_exp2,(double));
-double EXFUN(fast_exp10,(double));
-double EXFUN(fast_expe,(double));
-double EXFUN(fast_log10,(double));
-double EXFUN(fast_log2,(double));
-double EXFUN(fast_loge,(double));
-
-
-#define	sin(x)		fast_sin(x)
-#define	cos(x)		fast_cos(x)
-#define	tan(x)		fast_tan(x)
-#define	asin(x)		fast_asin(x)
-#define	acos(x)		fast_acos(x)
-#define	atan(x)		fast_atan(x)
-#define	sinh(x)		fast_sinh(x)
-#define	cosh(x)		fast_cosh(x)
-#define	tanh(x)		fast_tanh(x)
-#define	asinh(x)	fast_asinh(x)
-#define	acosh(x)	fast_acosh(x)
-#define	atanh(x)	fast_atanh(x)
-#define	abs(x)		fast_abs(x)
-#define	sqrt(x)		fast_sqrt(x)
-#define	exp2(x)		fast_exp2(x)
-#define	exp10(x)	fast_exp10(x)
-#define	expe(x)		fast_expe(x)
-#define	log10(x)	fast_log10(x)
-#define	log2(x)		fast_log2(x)
-#define	loge(x)		fast_loge(x)
-
-#ifdef _HAVE_STDC
-/* These functions are in assembler, they really do take floats. This
-   can only be used with a real ANSI compiler */
-
-float EXFUN(fast_sinf,(float));
-float EXFUN(fast_cosf,(float));
-float EXFUN(fast_tanf,(float));
-
-float EXFUN(fast_asinf,(float));
-float EXFUN(fast_acosf,(float));
-float EXFUN(fast_atanf,(float));
-
-float EXFUN(fast_sinhf,(float));
-float EXFUN(fast_coshf,(float));
-float EXFUN(fast_tanhf,(float));
-
-float EXFUN(fast_asinhf,(float));
-float EXFUN(fast_acoshf,(float));
-float EXFUN(fast_atanhf,(float));
-
-float EXFUN(fast_absf,(float));
-float EXFUN(fast_sqrtf,(float));
-float EXFUN(fast_exp2f,(float));
-float EXFUN(fast_exp10f,(float));
-float EXFUN(fast_expef,(float));
-float EXFUN(fast_log10f,(float));
-float EXFUN(fast_log2f,(float));
-float EXFUN(fast_logef,(float));
-#define	sinf(x)		fast_sinf(x)
-#define	cosf(x)		fast_cosf(x)
-#define	tanf(x)		fast_tanf(x)
-#define	asinf(x)	fast_asinf(x)
-#define	acosf(x)	fast_acosf(x)
-#define	atanf(x)	fast_atanf(x)
-#define	sinhf(x)	fast_sinhf(x)
-#define	coshf(x)	fast_coshf(x)
-#define	tanhf(x)	fast_tanhf(x)
-#define	asinhf(x)	fast_asinhf(x)
-#define	acoshf(x)	fast_acoshf(x)
-#define	atanhf(x)	fast_atanhf(x)
-#define	absf(x)		fast_absf(x)
-#define	sqrtf(x)	fast_sqrtf(x)
-#define	exp2f(x)	fast_exp2f(x)
-#define	exp10f(x)	fast_exp10f(x)
-#define	expef(x)	fast_expef(x)
-#define	log10f(x)	fast_log10f(x)
-#define	log2f(x)	fast_log2f(x)
-#define	logef(x)	fast_logef(x)
-#endif
-/* Override the functions defined in math.h */
-#endif /* __sysvnecv70_target */
-
diff --git a/tools/sdk/include/newlib/machine/ieeefp.h b/tools/sdk/include/newlib/machine/ieeefp.h
deleted file mode 100644
index f11dc053535..00000000000
--- a/tools/sdk/include/newlib/machine/ieeefp.h
+++ /dev/null
@@ -1,434 +0,0 @@
-#ifndef __IEEE_BIG_ENDIAN
-#ifndef __IEEE_LITTLE_ENDIAN
-
-/* This file can define macros to choose variations of the IEEE float
-   format:
-
-   _FLT_LARGEST_EXPONENT_IS_NORMAL
-
-	Defined if the float format uses the largest exponent for finite
-	numbers rather than NaN and infinity representations.  Such a
-	format cannot represent NaNs or infinities at all, but it's FLT_MAX
-	is twice the IEEE value.
-
-   _FLT_NO_DENORMALS
-
-	Defined if the float format does not support IEEE denormals.  Every
-	float with a zero exponent is taken to be a zero representation.
- 
-   ??? At the moment, there are no equivalent macros above for doubles and
-   the macros are not fully supported by --enable-newlib-hw-fp.
-
-   __IEEE_BIG_ENDIAN
-
-        Defined if the float format is big endian.  This is mutually exclusive
-        with __IEEE_LITTLE_ENDIAN.
-
-   __IEEE_LITTLE_ENDIAN
- 
-        Defined if the float format is little endian.  This is mutually exclusive
-        with __IEEE_BIG_ENDIAN.
-
-   Note that one of __IEEE_BIG_ENDIAN or __IEEE_LITTLE_ENDIAN must be specified for a
-   platform or error will occur.
-
-   __IEEE_BYTES_LITTLE_ENDIAN
-
-        This flag is used in conjunction with __IEEE_BIG_ENDIAN to describe a situation 
-	whereby multiple words of an IEEE floating point are in big endian order, but the
-	words themselves are little endian with respect to the bytes.
-
-   _DOUBLE_IS_32BITS 
-
-        This is used on platforms that support double by using the 32-bit IEEE
-        float type.
-
-   _FLOAT_ARG
-
-        This represents what type a float arg is passed as.  It is used when the type is
-        not promoted to double.
-	
-*/
-
-#if (defined(__arm__) || defined(__thumb__)) && !defined(__MAVERICK__)
-/* ARM traditionally used big-endian words; and within those words the
-   byte ordering was big or little endian depending upon the target.
-   Modern floating-point formats are naturally ordered; in this case
-   __VFP_FP__ will be defined, even if soft-float.  */
-#ifdef __VFP_FP__
-# ifdef __ARMEL__
-#  define __IEEE_LITTLE_ENDIAN
-# else
-#  define __IEEE_BIG_ENDIAN
-# endif
-#else
-# define __IEEE_BIG_ENDIAN
-# ifdef __ARMEL__
-#  define __IEEE_BYTES_LITTLE_ENDIAN
-# endif
-#endif
-#endif
-
-#if defined (__aarch64__)
-#if defined (__AARCH64EL__)
-#define __IEEE_LITTLE_ENDIAN
-#else
-#define __IEEE_BIG_ENDIAN
-#endif
-#endif
-
-#ifdef __epiphany__
-#define __IEEE_LITTLE_ENDIAN
-#define Sudden_Underflow 1
-#endif
-
-#ifdef __hppa__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __nds32__
-#ifdef __big_endian__
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-
-#ifdef __SPU__
-#define __IEEE_BIG_ENDIAN
-
-#define isfinite(__y) \
-	(__extension__ ({int __cy; \
-		(sizeof (__y) == sizeof (float))  ? (1) : \
-		(__cy = fpclassify(__y)) != FP_INFINITE && __cy != FP_NAN;}))
-
-#define isinf(__x) ((sizeof (__x) == sizeof (float))  ?  (0) : __isinfd(__x))
-#define isnan(__x) ((sizeof (__x) == sizeof (float))  ?  (0) : __isnand(__x))
-
-/*
- * Macros for use in ieeefp.h. We can't just define the real ones here
- * (like those above) as we have name space issues when this is *not*
- * included via generic the ieeefp.h.
- */
-#define __ieeefp_isnanf(x)	0
-#define __ieeefp_isinff(x)	0
-#define __ieeefp_finitef(x)	1
-#endif
-
-#ifdef __sparc__
-#ifdef __LITTLE_ENDIAN_DATA__
-#define __IEEE_LITTLE_ENDIAN
-#else
-#define __IEEE_BIG_ENDIAN
-#endif
-#endif
-
-#if defined(__m68k__) || defined(__mc68000__)
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
-#define __IEEE_BIG_ENDIAN
-#ifdef __HAVE_SHORT_DOUBLE__
-# define _DOUBLE_IS_32BITS
-#endif
-#endif
-
-#if defined (__H8300__) || defined (__H8300H__) || defined (__H8300S__) || defined (__H8500__) || defined (__H8300SX__)
-#define __IEEE_BIG_ENDIAN
-#define _FLOAT_ARG float
-#define _DOUBLE_IS_32BITS
-#endif
-
-#if defined (__xc16x__) || defined (__xc16xL__) || defined (__xc16xS__)
-#define __IEEE_LITTLE_ENDIAN
-#define _FLOAT_ARG float
-#define _DOUBLE_IS_32BITS
-#endif
-
-
-#ifdef __sh__
-#ifdef __LITTLE_ENDIAN__
-#define __IEEE_LITTLE_ENDIAN
-#else
-#define __IEEE_BIG_ENDIAN
-#endif
-#if defined(__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE_ONLY__) || defined(__SH2A_SINGLE_ONLY__)
-#define _DOUBLE_IS_32BITS
-#endif
-#endif
-
-#ifdef _AM29K
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef _WIN32
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __i386__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __i960__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __lm32__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __M32R__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#if defined(_C4x) || defined(_C3x)
-#define __IEEE_BIG_ENDIAN
-#define _DOUBLE_IS_32BITS
-#endif
-
-#ifdef __TMS320C6X__
-#ifdef _BIG_ENDIAN
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-
-#ifdef __TIC80__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __MIPSEL__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#ifdef __MIPSEB__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __MMIX__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __D30V__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-/* necv70 was __IEEE_LITTLE_ENDIAN. */
-
-#ifdef __W65__
-#define __IEEE_LITTLE_ENDIAN
-#define _DOUBLE_IS_32BITS
-#endif
-
-#if defined(__Z8001__) || defined(__Z8002__)
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __m88k__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __mn10300__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __mn10200__
-#define __IEEE_LITTLE_ENDIAN
-#define _DOUBLE_IS_32BITS
-#endif
-
-#ifdef __v800
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __v850
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __D10V__
-#define __IEEE_BIG_ENDIAN
-#if __DOUBLE__ == 32
-#define _DOUBLE_IS_32BITS
-#endif
-#endif
-
-#ifdef __PPC__
-#if (defined(_BIG_ENDIAN) && _BIG_ENDIAN) || (defined(_AIX) && _AIX)
-#define __IEEE_BIG_ENDIAN
-#else
-#if (defined(_LITTLE_ENDIAN) && _LITTLE_ENDIAN) || (defined(__sun__) && __sun__) || (defined(_WIN32) && _WIN32)
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-#endif
-
-#ifdef __xstormy16__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __arc__
-#ifdef __big_endian__
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-
-#ifdef __CRX__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __fr30__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __mcore__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __mt__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __frv__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __moxie__
-#ifdef __MOXIE_BIG_ENDIAN__
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-
-#ifdef __ia64__
-#ifdef __BIG_ENDIAN__
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-
-#ifdef __AVR__
-#define __IEEE_LITTLE_ENDIAN
-#define _DOUBLE_IS_32BITS
-#endif
-
-#if defined(__or1k__) || defined(__OR1K__) || defined(__OR1KND__)
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __IP2K__
-#define __IEEE_BIG_ENDIAN
-#define __SMALL_BITFIELDS
-#define _DOUBLE_IS_32BITS
-#endif
-
-#ifdef __iq2000__
-#define __IEEE_BIG_ENDIAN
-#endif
-
-#ifdef __MAVERICK__
-#ifdef __ARMEL__
-#  define __IEEE_LITTLE_ENDIAN
-#else  /* must be __ARMEB__ */
-#  define __IEEE_BIG_ENDIAN
-#endif /* __ARMEL__ */
-#endif /* __MAVERICK__ */
-
-#ifdef __m32c__
-#define __IEEE_LITTLE_ENDIAN
-#define __SMALL_BITFIELDS
-#endif
-
-#ifdef __CRIS__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __BFIN__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __x86_64__
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifdef __mep__
-#ifdef __LITTLE_ENDIAN__
-#define __IEEE_LITTLE_ENDIAN
-#else
-#define __IEEE_BIG_ENDIAN
-#endif
-#endif
-
-#ifdef __MICROBLAZE__
-#ifndef __MICROBLAZEEL__
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-#endif
-
-#ifdef __MSP430__
-#define __IEEE_LITTLE_ENDIAN
-#define __SMALL_BITFIELDS	/* 16 Bit INT */
-#endif
-
-#ifdef __RL78__
-#define __IEEE_LITTLE_ENDIAN
-#define __SMALL_BITFIELDS	/* 16 Bit INT */
-#ifndef __RL78_64BIT_DOUBLES__
-#define _DOUBLE_IS_32BITS
-#endif
-#endif
-
-#ifdef __RX__
-
-#ifdef __RX_BIG_ENDIAN__
-#define __IEEE_BIG_ENDIAN
-#else
-#define __IEEE_LITTLE_ENDIAN
-#endif
-
-#ifndef __RX_64BIT_DOUBLES__
-#define _DOUBLE_IS_32BITS
-#endif
-
-#ifdef __RX_16BIT_INTS__
-#define __SMALL_BITFIELDS
-#endif
-
-#endif
-
-#if (defined(__CR16__) || defined(__CR16C__) ||defined(__CR16CP__))
-#define __IEEE_LITTLE_ENDIAN
-#define __SMALL_BITFIELDS	/* 16 Bit INT */
-#endif
-
-#ifdef __NIOS2__
-# ifdef __nios2_big_endian__
-#  define __IEEE_BIG_ENDIAN
-# else
-#  define __IEEE_LITTLE_ENDIAN
-# endif
-#endif
-
-#if (defined(__XTENSA__))
-# ifdef __XTENSA_EB__
-#  define __IEEE_BIG_ENDIAN
-# else
-#  define __IEEE_LITTLE_ENDIAN
-# endif
-#endif
-
-#ifndef __IEEE_BIG_ENDIAN
-#ifndef __IEEE_LITTLE_ENDIAN
-#error Endianess not declared!!
-#endif /* not __IEEE_LITTLE_ENDIAN */
-#endif /* not __IEEE_BIG_ENDIAN */
-
-#endif /* not __IEEE_LITTLE_ENDIAN */
-#endif /* not __IEEE_BIG_ENDIAN */
-
diff --git a/tools/sdk/include/newlib/machine/malloc.h b/tools/sdk/include/newlib/machine/malloc.h
deleted file mode 100644
index fdada9ed7f2..00000000000
--- a/tools/sdk/include/newlib/machine/malloc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef	_MACHMALLOC_H_
-#define	_MACHMALLOC_H_
-
-/* place holder so platforms may add malloc.h extensions */
-
-#endif	/* _MACHMALLOC_H_ */
-
-
diff --git a/tools/sdk/include/newlib/machine/param.h b/tools/sdk/include/newlib/machine/param.h
deleted file mode 100644
index bdf8bf70f51..00000000000
--- a/tools/sdk/include/newlib/machine/param.h
+++ /dev/null
@@ -1 +0,0 @@
-/* Place holder for machine-specific param.h.  */
diff --git a/tools/sdk/include/newlib/machine/setjmp-dj.h b/tools/sdk/include/newlib/machine/setjmp-dj.h
deleted file mode 100644
index 6ca5e65269f..00000000000
--- a/tools/sdk/include/newlib/machine/setjmp-dj.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 1991 DJ Delorie
- * All rights reserved.
- *
- * Redistribution, modification, and use in source and binary forms is permitted
- * provided that the above copyright notice and following paragraph are
- * duplicated in all such forms.
- *
- * This file is distributed WITHOUT ANY WARRANTY; without even the implied
- * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-/* Modified to use SETJMP_DJ_H rather than SETJMP_H to avoid
-   conflicting with setjmp.h.  Ian Taylor, Cygnus support, April,
-   1993.  */
-
-#ifndef _SETJMP_DJ_H_
-#define _SETJMP_DJ_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-  unsigned long eax;
-  unsigned long ebx;
-  unsigned long ecx;
-  unsigned long edx;
-  unsigned long esi;
-  unsigned long edi;
-  unsigned long ebp;
-  unsigned long esp;
-  unsigned long eip;
-} jmp_buf[1];
-
-extern int setjmp(jmp_buf);
-extern void longjmp(jmp_buf, int);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/newlib/machine/setjmp.h b/tools/sdk/include/newlib/machine/setjmp.h
deleted file mode 100644
index 9f9d9e49b53..00000000000
--- a/tools/sdk/include/newlib/machine/setjmp.h
+++ /dev/null
@@ -1,453 +0,0 @@
-
-_BEGIN_STD_C
-
-#if defined(__or1k__) || defined(__or1knd__)
-#define _JBLEN 31 /* 32 GPRs - r0 */
-#define _JBTYPE unsigned long
-#endif
-
-#if defined(__arm__) || defined(__thumb__)
-/*
- * All callee preserved registers:
- * v1 - v7, fp, ip, sp, lr, f4, f5, f6, f7
- */
-#define _JBLEN 23
-#endif
-
-#if defined(__aarch64__)
-#define _JBLEN 22
-#define _JBTYPE long long
-#endif
-
-#if defined(__AVR__)
-#define _JBLEN 24
-#endif
-
-#ifdef __sparc__
-/*
- * onsstack,sigmask,sp,pc,npc,psr,g1,o0,wbcnt (sigcontext).
- * All else recovered by under/over(flow) handling.
- */
-#define	_JBLEN	13
-#endif
-
-#ifdef __BFIN__
-#define _JBLEN  40
-#endif
-
-#ifdef __epiphany__
-/* All callee preserved registers: r4-r10,fp, sp, lr,r15, r32-r39  */
-#define _JBTYPE long long
-#define _JBLEN 10
-#endif
-
-/* necv70 was 9 as well. */
-
-#if defined(__m68k__) || defined(__mc68000__)
-/*
- * onsstack,sigmask,sp,pc,psl,d2-d7,a2-a6,
- * fp2-fp7	for 68881.
- * All else recovered by under/over(flow) handling.
- */
-#define	_JBLEN	34
-#endif
-
-#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
-/*
- * D, X, Y are not saved.
- * Only take into account the pseudo soft registers (max 32).
- */
-#define _JBLEN  32
-#endif
-
-#ifdef __nds32__
-/* 17 words for GPRs,
-   1 word for $fpcfg.freg and 30 words for FPUs
-   Reserved 2 words for aligement-adjustment. When storeing double-precision
-   floating-point register into memory, the address has to be
-   double-word-aligned.
-   Check libc/machine/nds32/setjmp.S for more information.  */
-#if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__
-#define	_JBLEN 50
-#else
-#define _JBLEN 18
-#endif
-#endif
-
-#if defined(__Z8001__) || defined(__Z8002__)
-/* 16 regs + pc */
-#define _JBLEN 20
-#endif
-
-#ifdef _AM29K
-/*
- * onsstack,sigmask,sp,pc,npc,psr,g1,o0,wbcnt (sigcontext).
- * All else recovered by under/over(flow) handling.
- */
-#define	_JBLEN	9
-#endif
-
-#ifdef __i386__
-# if defined(__CYGWIN__) && !defined (_JBLEN)
-#  define _JBLEN (13 * 4)
-# elif defined(__unix__) || defined(__rtems__)
-#  define _JBLEN	9
-# else
-#  include "setjmp-dj.h"
-# endif
-#endif
-
-#ifdef __x86_64__
-# ifdef __CYGWIN__
-#  define _JBTYPE long
-#  define _JBLEN  32
-# else
-#  define _JBTYPE long long
-#  define _JBLEN  8
-# endif
-#endif
-
-#ifdef __i960__
-#define _JBLEN 35
-#endif
-
-#ifdef __M32R__
-/* Only 8 words are currently needed.  10 gives us some slop if we need
-   to expand.  */
-#define _JBLEN 10
-#endif
-
-#ifdef __mips__
-# if defined(__mips64)
-#  define _JBTYPE long long
-# endif
-# ifdef __mips_soft_float
-#  define _JBLEN 11
-# else
-#  define _JBLEN 23
-# endif
-#endif
-
-#ifdef __m88000__
-#define _JBLEN 21
-#endif
-
-#ifdef __H8300__
-#define _JBLEN 5
-#define _JBTYPE int
-#endif
-
-#ifdef __H8300H__
-/* same as H8/300 but registers are twice as big */
-#define _JBLEN 5
-#define _JBTYPE long
-#endif
-
-#if defined (__H8300S__) || defined (__H8300SX__)
-/* same as H8/300 but registers are twice as big */
-#define _JBLEN 5
-#define _JBTYPE long
-#endif
-
-#ifdef __H8500__
-#define _JBLEN 4
-#endif
-
-#ifdef  __sh__
-#if __SH5__
-#define _JBLEN 50
-#define _JBTYPE long long
-#else
-#define _JBLEN 20
-#endif /* __SH5__ */
-#endif
-
-#ifdef  __v800
-#define _JBLEN 28
-#endif
-
-#ifdef __PPC__
-#ifdef __ALTIVEC__
-#define _JBLEN 64
-#else
-#define _JBLEN 32
-#endif
-#define _JBTYPE double
-#endif
-
-#ifdef __MICROBLAZE__
-#define _JBLEN  20
-#define _JBTYPE unsigned int
-#endif
-
-#ifdef __hppa__
-/* %r30, %r2-%r18, %r27, pad, %fr12-%fr15.
-   Note space exists for the FP registers, but they are not
-   saved.  */
-#define _JBLEN 28
-#endif
-
-#if defined(__mn10300__) || defined(__mn10200__)
-#ifdef __AM33_2__
-#define _JBLEN 26
-#else
-/* A guess */
-#define _JBLEN 10
-#endif
-#endif
-
-#ifdef __v850
-/* I think our setjmp is saving 15 regs at the moment.  Gives us one word
-   slop if we need to expand.  */
-#define _JBLEN 16
-#endif
-
-#if defined(_C4x)
-#define _JBLEN 10
-#endif
-#if defined(_C3x)
-#define _JBLEN 9
-#endif
-
-#ifdef __TMS320C6X__
-#define _JBLEN 13
-#endif
-
-#ifdef __TIC80__
-#define _JBLEN 13
-#endif
-
-#ifdef __D10V__
-#define _JBLEN 8
-#endif
-
-#ifdef __D30V__
-#define _JBLEN ((64 /* GPR */ + (2*2) /* ACs */ + 18 /* CRs */) / 2)
-#define _JBTYPE double
-#endif
-
-#ifdef __frv__
-#define _JBLEN (68/2)  /* room for 68 32-bit regs */
-#define _JBTYPE double
-#endif
-
-#ifdef __moxie__
-#define _JBLEN 16
-#endif
-
-#ifdef __CRX__
-#define _JBLEN 9
-#endif
-
-#if (defined(__CR16__) || defined(__CR16C__) ||defined(__CR16CP__))
-/* r6, r7, r8, r9, r10, r11, r12 (r12L, r12H), 
- * r13 (r13L, r13H), ra(raL, raH), sp(spL, spH) */
-#define _JBLEN 14
-#define _JBTYPE unsigned short
-#endif
-
-#ifdef __fr30__
-#define _JBLEN 10
-#endif
-
-#ifdef __iq2000__
-#define _JBLEN 32
-#endif
-
-#ifdef __mcore__
-#define _JBLEN 16
-#endif
-
-#ifdef __MMIX__
-/* Using a layout compatible with GCC's built-in.  */
-#define _JBLEN 5
-#define _JBTYPE unsigned long
-#endif
-
-#ifdef __mt__
-#define _JBLEN 16
-#endif
-
-#ifdef __SPU__
-#define _JBLEN 50 
-#define _JBTYPE __vector signed int
-#endif
-
-#ifdef __xstormy16__
-/* 4 GPRs plus SP plus PC. */
-#define _JBLEN 8
-#endif
-
-#ifdef __XTENSA__
-#if __XTENSA_WINDOWED_ABI__
-
-/* The jmp_buf structure for Xtensa windowed ABI holds the following
-   (where "proc" is the procedure that calls setjmp): 4-12 registers
-   from the window of proc, the 4 words from the save area at proc's $sp
-   (in case a subsequent alloca in proc moves $sp), and the return
-   address within proc.  Everything else is saved on the stack in the
-   normal save areas.  The jmp_buf structure is:
-  
-  	struct jmp_buf {
-  	    int regs[12];
-  	    int save[4];
-  	    void *return_address;
-  	}
-  
-   See the setjmp code for details.  */
-
-#define _JBLEN		17	/* 12 + 4 + 1 */
-
-#else /* __XTENSA_CALL0_ABI__ */
-
-#define _JBLEN		6	/* a0, a1, a12, a13, a14, a15 */
-
-#endif /* __XTENSA_CALL0_ABI__ */
-#endif /* __XTENSA__ */
-
-#ifdef __mep__
-/* 16 GPRs, pc, hi, lo */
-#define _JBLEN 19
-#endif
-
-#ifdef __CRIS__
-#define _JBLEN 18
-#endif
-
-#ifdef __lm32__
-#define _JBLEN 19
-#endif
-
-#ifdef __m32c__
-#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
-#define _JBLEN (22/2)
-#else
-#define _JBLEN (34/2)
-#endif
-#define _JBTYPE unsigned short
-#endif /* __m32c__ */
-
-#ifdef __MSP430__
-#define _JBLEN 9
-
-#ifdef __MSP430X_LARGE__
-#define _JBTYPE unsigned long
-#else
-#define _JBTYPE unsigned short
-#endif
-#endif
-
-#ifdef __RL78__
-/* Three banks of registers, SP, CS, ES, PC */
-#define _JBLEN (8*3+8)
-#define _JBTYPE unsigned char
-#endif
-
-/*
- * There are two versions of setjmp()/longjmp():
- *   1) Compiler (gcc) built-in versions.
- *   2) Function-call versions.
- *
- * The built-in versions are used most of the time.  When used, gcc replaces
- * calls to setjmp()/longjmp() with inline assembly code.  The built-in 
- * versions save/restore a variable number of registers.
-
- * _JBLEN is set to 40 to be ultra-safe with the built-in versions.
- * It only needs to be 12 for the function-call versions
- * but this data structure is used by both versions.
- */
-#ifdef __NIOS2__
-#define _JBLEN 40
-#define _JBTYPE unsigned long
-#endif
-
-#ifdef __RX__
-#define _JBLEN 0x44
-#endif
-
-#ifdef _JBLEN
-#ifdef _JBTYPE
-typedef	_JBTYPE jmp_buf[_JBLEN];
-#else
-typedef	int jmp_buf[_JBLEN];
-#endif
-#endif
-
-_END_STD_C
-
-#if defined(__CYGWIN__) || defined(__rtems__)
-#include <signal.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* POSIX sigsetjmp/siglongjmp macros */
-#ifdef _JBTYPE
-typedef _JBTYPE sigjmp_buf[_JBLEN+1+((sizeof (_JBTYPE) + sizeof (sigset_t) - 1)
-				     /sizeof (_JBTYPE))];
-#else
-typedef int sigjmp_buf[_JBLEN+1+(sizeof (sigset_t)/sizeof (int))];
-#endif
-
-#define _SAVEMASK	_JBLEN
-#define _SIGMASK	(_JBLEN+1)
-
-#ifdef __CYGWIN__
-# define _CYGWIN_WORKING_SIGSETJMP
-#endif
-
-#ifdef _POSIX_THREADS
-#define __SIGMASK_FUNC pthread_sigmask
-#else
-#define __SIGMASK_FUNC sigprocmask
-#endif
-
-#if defined(__GNUC__)
-
-#define sigsetjmp(env, savemask) \
-            __extension__ \
-            ({ \
-              sigjmp_buf *_sjbuf = &(env); \
-              ((*_sjbuf)[_SAVEMASK] = savemask,\
-              __SIGMASK_FUNC (SIG_SETMASK, 0, (sigset_t *)((*_sjbuf) + _SIGMASK)),\
-              setjmp (*_sjbuf)); \
-            })
-
-#define siglongjmp(env, val) \
-            __extension__ \
-            ({ \
-              sigjmp_buf *_sjbuf = &(env); \
-              ((((*_sjbuf)[_SAVEMASK]) ? \
-               __SIGMASK_FUNC (SIG_SETMASK, (sigset_t *)((*_sjbuf) + _SIGMASK), 0)\
-               : 0), \
-               longjmp (*_sjbuf, val)); \
-            })
-
-#else /* !__GNUC__ */
-
-#define sigsetjmp(env, savemask) ((env)[_SAVEMASK] = savemask,\
-               __SIGMASK_FUNC (SIG_SETMASK, 0, (sigset_t *) ((env) + _SIGMASK)),\
-               setjmp (env))
-
-#define siglongjmp(env, val) ((((env)[_SAVEMASK])?\
-               __SIGMASK_FUNC (SIG_SETMASK, (sigset_t *) ((env) + _SIGMASK), 0):0),\
-               longjmp (env, val))
-
-#endif
-
-/* POSIX _setjmp/_longjmp, maintained for XSI compatibility.  These
-   are equivalent to sigsetjmp/siglongjmp when not saving the signal mask.
-   New applications should use sigsetjmp/siglongjmp instead. */
-#ifdef __CYGWIN__
-extern void _longjmp(jmp_buf, int);
-extern int _setjmp(jmp_buf);
-#else
-#define _setjmp(env)		sigsetjmp ((env), 0)
-#define _longjmp(env, val)	siglongjmp ((env), (val))
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __CYGWIN__ or __rtems__ */
diff --git a/tools/sdk/include/newlib/machine/stdlib.h b/tools/sdk/include/newlib/machine/stdlib.h
deleted file mode 100644
index fa3f3a1390d..00000000000
--- a/tools/sdk/include/newlib/machine/stdlib.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef	_MACHSTDLIB_H_
-#define	_MACHSTDLIB_H_
-
-/* place holder so platforms may add stdlib.h extensions */
-
-#endif	/* _MACHSTDLIB_H_ */
-
-
diff --git a/tools/sdk/include/newlib/machine/termios.h b/tools/sdk/include/newlib/machine/termios.h
deleted file mode 100644
index 41fd459385c..00000000000
--- a/tools/sdk/include/newlib/machine/termios.h
+++ /dev/null
@@ -1 +0,0 @@
-#define __MAX_BAUD  B4000000
diff --git a/tools/sdk/include/newlib/machine/time.h b/tools/sdk/include/newlib/machine/time.h
deleted file mode 100644
index 06e2ccffb15..00000000000
--- a/tools/sdk/include/newlib/machine/time.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef	_MACHTIME_H_
-#define	_MACHTIME_H_
-
-#if defined(__rtems__)
-#define _CLOCKS_PER_SEC_  sysconf(_SC_CLK_TCK)
-#else  /* !__rtems__ */
-#if defined(__aarch64__) || defined(__arm__) || defined(__thumb__)
-#define _CLOCKS_PER_SEC_ 100
-#endif
-#endif /* !__rtems__ */
-
-#ifdef __SPU__
-#include <sys/types.h>
-int nanosleep (const struct timespec *, struct timespec *);
-#endif
-
-#endif	/* _MACHTIME_H_ */
-
-
diff --git a/tools/sdk/include/newlib/machine/types.h b/tools/sdk/include/newlib/machine/types.h
deleted file mode 100644
index 40a75faa5bf..00000000000
--- a/tools/sdk/include/newlib/machine/types.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef	_MACHTYPES_H_
-#define	_MACHTYPES_H_
-
-/*
- *  The following section is RTEMS specific and is needed to more
- *  closely match the types defined in the BSD machine/types.h.
- *  This is needed to let the RTEMS/BSD TCP/IP stack compile.
- */
-#if defined(__rtems__)
-#include <machine/_types.h>
-#endif
-
-#define	_CLOCK_T_	unsigned long		/* clock() */
-#define	_TIME_T_	long			/* time() */
-#define _CLOCKID_T_ 	unsigned long
-#define _TIMER_T_   	unsigned long
-
-#ifndef _HAVE_SYSTYPES
-typedef long int __off_t;
-typedef int __pid_t;
-#ifdef __GNUC__
-__extension__ typedef long long int __loff_t;
-#else
-typedef long int __loff_t;
-#endif
-#endif
-
-#endif	/* _MACHTYPES_H_ */
-
-
diff --git a/tools/sdk/include/newlib/malloc.h b/tools/sdk/include/newlib/malloc.h
deleted file mode 100644
index 41b5efdc0a1..00000000000
--- a/tools/sdk/include/newlib/malloc.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* malloc.h -- header file for memory routines.  */
-
-#ifndef _INCLUDE_MALLOC_H_
-#define _INCLUDE_MALLOC_H_
-
-#include <_ansi.h>
-#include <sys/reent.h>
-
-#define __need_size_t
-#include <stddef.h>
-
-/* include any machine-specific extensions */
-#include <machine/malloc.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* This version of struct mallinfo must match the one in
-   libc/stdlib/mallocr.c.  */
-
-struct mallinfo {
-  size_t arena;    /* total space allocated from system */
-  size_t ordblks;  /* number of non-inuse chunks */
-  size_t smblks;   /* unused -- always zero */
-  size_t hblks;    /* number of mmapped regions */
-  size_t hblkhd;   /* total space in mmapped regions */
-  size_t usmblks;  /* unused -- always zero */
-  size_t fsmblks;  /* unused -- always zero */
-  size_t uordblks; /* total allocated space */
-  size_t fordblks; /* total non-inuse space */
-  size_t keepcost; /* top-most, releasable (via malloc_trim) space */
-};	
-
-/* The routines.  */
-
-extern _PTR malloc _PARAMS ((size_t));
-#ifdef __CYGWIN__
-#undef _malloc_r
-#define _malloc_r(r, s) malloc (s)
-#else
-extern _PTR _malloc_r _PARAMS ((struct _reent *, size_t));
-#endif
-
-extern _VOID free _PARAMS ((_PTR));
-#ifdef __CYGWIN__
-#undef _free_r
-#define _free_r(r, p) free (p)
-#else
-extern _VOID _free_r _PARAMS ((struct _reent *, _PTR));
-#endif
-
-extern _PTR realloc _PARAMS ((_PTR, size_t));
-#ifdef __CYGWIN__
-#undef _realloc_r
-#define _realloc_r(r, p, s) realloc (p, s)
-#else
-extern _PTR _realloc_r _PARAMS ((struct _reent *, _PTR, size_t));
-#endif
-
-extern _PTR calloc _PARAMS ((size_t, size_t));
-#ifdef __CYGWIN__
-#undef _calloc_r
-#define _calloc_r(r, s1, s2) calloc (s1, s2);
-#else
-extern _PTR _calloc_r _PARAMS ((struct _reent *, size_t, size_t));
-#endif
-
-extern _PTR memalign _PARAMS ((size_t, size_t));
-#ifdef __CYGWIN__
-#undef _memalign_r
-#define _memalign_r(r, s1, s2) memalign (s1, s2);
-#else
-extern _PTR _memalign_r _PARAMS ((struct _reent *, size_t, size_t));
-#endif
-
-extern struct mallinfo mallinfo _PARAMS ((void));
-#ifdef __CYGWIN__
-#undef _mallinfo_r
-#define _mallinfo_r(r) mallinfo ()
-#else
-extern struct mallinfo _mallinfo_r _PARAMS ((struct _reent *));
-#endif
-
-extern void malloc_stats _PARAMS ((void));
-#ifdef __CYGWIN__
-#undef _malloc_stats_r
-#define _malloc_stats_r(r) malloc_stats ()
-#else
-extern void _malloc_stats_r _PARAMS ((struct _reent *));
-#endif
-
-extern int mallopt _PARAMS ((int, int));
-#ifdef __CYGWIN__
-#undef _mallopt_r
-#define _mallopt_r(i1, i2) mallopt (i1, i2)
-#else
-extern int _mallopt_r _PARAMS ((struct _reent *, int, int));
-#endif
-
-extern size_t malloc_usable_size _PARAMS ((_PTR));
-#ifdef __CYGWIN__
-#undef _malloc_usable_size_r
-#define _malloc_usable_size_r(r, p) malloc_usable_size (p)
-#else
-extern size_t _malloc_usable_size_r _PARAMS ((struct _reent *, _PTR));
-#endif
-
-/* These aren't too useful on an embedded system, but we define them
-   anyhow.  */
-
-extern _PTR valloc _PARAMS ((size_t));
-#ifdef __CYGWIN__
-#undef _valloc_r
-#define _valloc_r(r, s) valloc (s)
-#else
-extern _PTR _valloc_r _PARAMS ((struct _reent *, size_t));
-#endif
-
-extern _PTR pvalloc _PARAMS ((size_t));
-#ifdef __CYGWIN__
-#undef _pvalloc_r
-#define _pvalloc_r(r, s) pvalloc (s)
-#else
-extern _PTR _pvalloc_r _PARAMS ((struct _reent *, size_t));
-#endif
-
-extern int malloc_trim _PARAMS ((size_t));
-#ifdef __CYGWIN__
-#undef _malloc_trim_r
-#define _malloc_trim_r(r, s) malloc_trim (s)
-#else
-extern int _malloc_trim_r _PARAMS ((struct _reent *, size_t));
-#endif
-
-/* A compatibility routine for an earlier version of the allocator.  */
-
-extern _VOID mstats _PARAMS ((char *));
-#ifdef __CYGWIN__
-#undef _mstats_r
-#define _mstats_r(r, p) mstats (p)
-#else
-extern _VOID _mstats_r _PARAMS ((struct _reent *, char *));
-#endif
-
-/* SVID2/XPG mallopt options */
-
-#define M_MXFAST  1    /* UNUSED in this malloc */
-#define M_NLBLKS  2    /* UNUSED in this malloc */
-#define M_GRAIN   3    /* UNUSED in this malloc */
-#define M_KEEP    4    /* UNUSED in this malloc */
-
-/* mallopt options that actually do something */
-  
-#define M_TRIM_THRESHOLD    -1
-#define M_TOP_PAD           -2
-#define M_MMAP_THRESHOLD    -3 
-#define M_MMAP_MAX          -4
-
-#ifndef __CYGWIN__
-/* Some systems provide this, so do too for compatibility.  */
-extern void cfree _PARAMS ((_PTR));
-#endif /* __CYGWIN__ */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _INCLUDE_MALLOC_H_ */
diff --git a/tools/sdk/include/newlib/math.h b/tools/sdk/include/newlib/math.h
deleted file mode 100644
index d16ce30741d..00000000000
--- a/tools/sdk/include/newlib/math.h
+++ /dev/null
@@ -1,615 +0,0 @@
-#ifndef  _MATH_H_
-
-#define  _MATH_H_
-
-#include <sys/reent.h>
-#include <machine/ieeefp.h>
-#include "_ansi.h"
-
-_BEGIN_STD_C
-
-/* __dmath, __fmath, and __ldmath are only here for backwards compatibility
- * in case any code used them.  They are no longer used by Newlib, itself,
- * other than legacy.  */
-union __dmath
-{
-  double d;
-  __ULong i[2];
-};
-
-union __fmath
-{
-  float f;
-  __ULong i[1];
-};
-
-#if defined(_HAVE_LONG_DOUBLE)
-union __ldmath
-{
-  long double ld;
-  __ULong i[4];
-};
-#endif
-
-/* Natural log of 2 */
-#define _M_LN2        0.693147180559945309417
-
-#if __GNUC_PREREQ (3, 3)
- /* gcc >= 3.3 implicitly defines builtins for HUGE_VALx values.  */
-
-# ifndef HUGE_VAL
-#  define HUGE_VAL (__builtin_huge_val())
-# endif
-
-# ifndef HUGE_VALF
-#  define HUGE_VALF (__builtin_huge_valf())
-# endif
-
-# ifndef HUGE_VALL
-#  define HUGE_VALL (__builtin_huge_vall())
-# endif
-
-# ifndef INFINITY
-#  define INFINITY (__builtin_inff())
-# endif
-
-# ifndef NAN
-#  define NAN (__builtin_nanf(""))
-# endif
-
-#else /* !gcc >= 3.3  */
-
- /*      No builtins.  Use fixed defines instead.  (All 3 HUGE plus the INFINITY
-  * and NAN macros are required to be constant expressions.  Using a variable--
-  * even a static const--does not meet this requirement, as it cannot be
-  * evaluated at translation time.)
-  *      The infinities are done using numbers that are far in excess of
-  * something that would be expected to be encountered in a floating-point
-  * implementation.  (A more certain way uses values from float.h, but that is
-  * avoided because system includes are not supposed to include each other.)
-  *      This method might produce warnings from some compilers.  (It does in
-  * newer GCCs, but not for ones that would hit this #else.)  If this happens,
-  * please report details to the Newlib mailing list.  */
-
- #ifndef HUGE_VAL
-  #define HUGE_VAL (1.0e999999999)
- #endif
-
- #ifndef HUGE_VALF
-  #define HUGE_VALF (1.0e999999999F)
- #endif
-
- #if !defined(HUGE_VALL)  &&  defined(_HAVE_LONG_DOUBLE)
-  #define HUGE_VALL (1.0e999999999L)
- #endif
-
- #if !defined(INFINITY)
-  #define INFINITY (HUGE_VALF)
- #endif
-
- #if !defined(NAN)
-  #if defined(__GNUC__)  &&  defined(__cplusplus)
-    /* Exception:  older g++ versions warn about the divide by 0 used in the
-     * normal case (even though older gccs do not).  This trick suppresses the
-     * warning, but causes errors for plain gcc, so is only used in the one
-     * special case.  */
-    static const union { __ULong __i[1]; float __d; } __Nanf = {0x7FC00000};
-    #define NAN (__Nanf.__d)
-  #else
-    #define NAN (0.0F/0.0F)
-  #endif
- #endif
-
-#endif /* !gcc >= 3.3  */
-
-/* Reentrant ANSI C functions.  */
-
-#ifndef __math_68881
-extern double atan _PARAMS((double));
-extern double cos _PARAMS((double));
-extern double sin _PARAMS((double));
-extern double tan _PARAMS((double));
-extern double tanh _PARAMS((double));
-extern double frexp _PARAMS((double, int *));
-extern double modf _PARAMS((double, double *));
-extern double ceil _PARAMS((double));
-extern double fabs _PARAMS((double));
-extern double floor _PARAMS((double));
-#endif /* ! defined (__math_68881) */
-
-/* Non reentrant ANSI C functions.  */
-
-#ifndef _REENT_ONLY
-#ifndef __math_68881
-extern double acos _PARAMS((double));
-extern double asin _PARAMS((double));
-extern double atan2 _PARAMS((double, double));
-extern double cosh _PARAMS((double));
-extern double sinh _PARAMS((double));
-extern double exp _PARAMS((double));
-extern double ldexp _PARAMS((double, int));
-extern double log _PARAMS((double));
-extern double log10 _PARAMS((double));
-extern double pow _PARAMS((double, double));
-extern double sqrt _PARAMS((double));
-extern double fmod _PARAMS((double, double));
-#endif /* ! defined (__math_68881) */
-#endif /* ! defined (_REENT_ONLY) */
-
-#if !defined(__STRICT_ANSI__) || defined(__cplusplus) || \
-  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L)
-
-/* ISO C99 types and macros. */
-
-/* FIXME:  FLT_EVAL_METHOD should somehow be gotten from float.h (which is hard,
- * considering that the standard says the includes it defines should not
- * include other includes that it defines) and that value used.  (This can be
- * solved, but autoconf has a bug which makes the solution more difficult, so
- * it has been skipped for now.)  */
-#if !defined(FLT_EVAL_METHOD) && defined(__FLT_EVAL_METHOD__)
-  #define FLT_EVAL_METHOD __FLT_EVAL_METHOD__
-  #define __TMP_FLT_EVAL_METHOD
-#endif /* FLT_EVAL_METHOD */
-#if defined FLT_EVAL_METHOD
-  #if FLT_EVAL_METHOD == 0
-    typedef float  float_t;
-    typedef double double_t;
-   #elif FLT_EVAL_METHOD == 1
-    typedef double float_t;
-    typedef double double_t;
-   #elif FLT_EVAL_METHOD == 2
-    typedef long double float_t;
-    typedef long double double_t;
-   #else
-    /* Implementation-defined.  Assume float_t and double_t have been
-     * defined previously for this configuration (e.g. config.h). */
-  #endif
-#else
-    /* Assume basic definitions.  */
-    typedef float  float_t;
-    typedef double double_t;
-#endif
-#if defined(__TMP_FLT_EVAL_METHOD)
-  #undef FLT_EVAL_METHOD
-#endif
-
-#define FP_NAN         0
-#define FP_INFINITE    1
-#define FP_ZERO        2
-#define FP_SUBNORMAL   3
-#define FP_NORMAL      4
-
-#ifndef FP_ILOGB0
-# define FP_ILOGB0 (-INT_MAX)
-#endif
-#ifndef FP_ILOGBNAN
-# define FP_ILOGBNAN INT_MAX
-#endif
-
-#ifndef MATH_ERRNO
-# define MATH_ERRNO 1
-#endif
-#ifndef MATH_ERREXCEPT
-# define MATH_ERREXCEPT 2
-#endif
-#ifndef math_errhandling
-# define math_errhandling MATH_ERRNO
-#endif
-
-extern int __isinff (float x);
-extern int __isinfd (double x);
-extern int __isnanf (float x);
-extern int __isnand (double x);
-extern int __fpclassifyf (float x);
-extern int __fpclassifyd (double x);
-extern int __signbitf (float x);
-extern int __signbitd (double x);
-
-#define fpclassify(__x) \
-	((sizeof(__x) == sizeof(float))  ? __fpclassifyf(__x) : \
-	__fpclassifyd(__x))
-
-#ifndef isfinite
-  #define isfinite(__y) \
-          (__extension__ ({int __cy = fpclassify(__y); \
-                           __cy != FP_INFINITE && __cy != FP_NAN;}))
-#endif
-
-/* Note: isinf and isnan were once functions in newlib that took double
- *       arguments.  C99 specifies that these names are reserved for macros
- *       supporting multiple floating point types.  Thus, they are
- *       now defined as macros.  Implementations of the old functions
- *       taking double arguments still exist for compatibility purposes
- *       (prototypes for them are in <ieeefp.h>).  */
-#ifndef isinf
-  #define isinf(y) (fpclassify(y) == FP_INFINITE)
-#endif
-
-#ifndef isnan
-  #define isnan(y) (fpclassify(y) == FP_NAN)
-#endif
-
-#define isnormal(y) (fpclassify(y) == FP_NORMAL)
-#define signbit(__x) \
-	((sizeof(__x) == sizeof(float))  ?  __signbitf(__x) : \
-		__signbitd(__x))
-
-#define isgreater(x,y) \
-          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
-                           !isunordered(__x,__y) && (__x > __y);}))
-#define isgreaterequal(x,y) \
-          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
-                           !isunordered(__x,__y) && (__x >= __y);}))
-#define isless(x,y) \
-          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
-                           !isunordered(__x,__y) && (__x < __y);}))
-#define islessequal(x,y) \
-          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
-                           !isunordered(__x,__y) && (__x <= __y);}))
-#define islessgreater(x,y) \
-          (__extension__ ({__typeof__(x) __x = (x); __typeof__(y) __y = (y); \
-                           !isunordered(__x,__y) && (__x < __y || __x > __y);}))
-
-#define isunordered(a,b) \
-          (__extension__ ({__typeof__(a) __a = (a); __typeof__(b) __b = (b); \
-                           fpclassify(__a) == FP_NAN || fpclassify(__b) == FP_NAN;}))
-
-/* Non ANSI double precision functions.  */
-
-extern double infinity _PARAMS((void));
-extern double nan _PARAMS((const char *));
-extern int finite _PARAMS((double));
-extern double copysign _PARAMS((double, double));
-extern double logb _PARAMS((double));
-extern int ilogb _PARAMS((double));
-
-extern double asinh _PARAMS((double));
-extern double cbrt _PARAMS((double));
-extern double nextafter _PARAMS((double, double));
-extern double rint _PARAMS((double));
-extern double scalbn _PARAMS((double, int));
-
-extern double exp2 _PARAMS((double));
-extern double scalbln _PARAMS((double, long int));
-extern double tgamma _PARAMS((double));
-extern double nearbyint _PARAMS((double));
-extern long int lrint _PARAMS((double));
-extern long long int llrint _PARAMS((double));
-extern double round _PARAMS((double));
-extern long int lround _PARAMS((double));
-extern long long int llround _PARAMS((double));
-extern double trunc _PARAMS((double));
-extern double remquo _PARAMS((double, double, int *));
-extern double fdim _PARAMS((double, double));
-extern double fmax _PARAMS((double, double));
-extern double fmin _PARAMS((double, double));
-extern double fma _PARAMS((double, double, double));
-
-#ifndef __math_68881
-extern double log1p _PARAMS((double));
-extern double expm1 _PARAMS((double));
-#endif /* ! defined (__math_68881) */
-
-#ifndef _REENT_ONLY
-extern double acosh _PARAMS((double));
-extern double atanh _PARAMS((double));
-extern double remainder _PARAMS((double, double));
-extern double gamma _PARAMS((double));
-extern double lgamma _PARAMS((double));
-extern double erf _PARAMS((double));
-extern double erfc _PARAMS((double));
-extern double log2 _PARAMS((double));
-#if !defined(__cplusplus)
-#define log2(x) (log (x) / _M_LN2)
-#endif
-
-#ifndef __math_68881
-extern double hypot _PARAMS((double, double));
-#endif
-
-#endif /* ! defined (_REENT_ONLY) */
-
-/* Single precision versions of ANSI functions.  */
-
-extern float atanf _PARAMS((float));
-extern float cosf _PARAMS((float));
-extern float sinf _PARAMS((float));
-extern float tanf _PARAMS((float));
-extern float tanhf _PARAMS((float));
-extern float frexpf _PARAMS((float, int *));
-extern float modff _PARAMS((float, float *));
-extern float ceilf _PARAMS((float));
-extern float fabsf _PARAMS((float));
-extern float floorf _PARAMS((float));
-
-#ifndef _REENT_ONLY
-extern float acosf _PARAMS((float));
-extern float asinf _PARAMS((float));
-extern float atan2f _PARAMS((float, float));
-extern float coshf _PARAMS((float));
-extern float sinhf _PARAMS((float));
-extern float expf _PARAMS((float));
-extern float ldexpf _PARAMS((float, int));
-extern float logf _PARAMS((float));
-extern float log10f _PARAMS((float));
-extern float powf _PARAMS((float, float));
-extern float sqrtf _PARAMS((float));
-extern float fmodf _PARAMS((float, float));
-#endif /* ! defined (_REENT_ONLY) */
-
-/* Other single precision functions.  */
-
-extern float exp2f _PARAMS((float));
-extern float scalblnf _PARAMS((float, long int));
-extern float tgammaf _PARAMS((float));
-extern float nearbyintf _PARAMS((float));
-extern long int lrintf _PARAMS((float));
-extern long long int llrintf _PARAMS((float));
-extern float roundf _PARAMS((float));
-extern long int lroundf _PARAMS((float));
-extern long long int llroundf _PARAMS((float));
-extern float truncf _PARAMS((float));
-extern float remquof _PARAMS((float, float, int *));
-extern float fdimf _PARAMS((float, float));
-extern float fmaxf _PARAMS((float, float));
-extern float fminf _PARAMS((float, float));
-extern float fmaf _PARAMS((float, float, float));
-
-extern float infinityf _PARAMS((void));
-extern float nanf _PARAMS((const char *));
-extern int finitef _PARAMS((float));
-extern float copysignf _PARAMS((float, float));
-extern float logbf _PARAMS((float));
-extern int ilogbf _PARAMS((float));
-
-extern float asinhf _PARAMS((float));
-extern float cbrtf _PARAMS((float));
-extern float nextafterf _PARAMS((float, float));
-extern float rintf _PARAMS((float));
-extern float scalbnf _PARAMS((float, int));
-extern float log1pf _PARAMS((float));
-extern float expm1f _PARAMS((float));
-
-#ifndef _REENT_ONLY
-extern float acoshf _PARAMS((float));
-extern float atanhf _PARAMS((float));
-extern float remainderf _PARAMS((float, float));
-extern float gammaf _PARAMS((float));
-extern float lgammaf _PARAMS((float));
-extern float erff _PARAMS((float));
-extern float erfcf _PARAMS((float));
-extern float log2f _PARAMS((float));
-extern float hypotf _PARAMS((float, float));
-#endif /* ! defined (_REENT_ONLY) */
-
-/* On platforms where long double equals double.  */
-#ifdef _LDBL_EQ_DBL
-/* Reentrant ANSI C functions.  */
-#ifndef __math_68881
-extern long double atanl _PARAMS((long double));
-extern long double cosl _PARAMS((long double));
-extern long double sinl _PARAMS((long double));
-extern long double tanl _PARAMS((long double));
-extern long double tanhl _PARAMS((long double));
-extern long double frexpl _PARAMS((long double, int *));
-extern long double modfl _PARAMS((long double, long double *));
-extern long double ceill _PARAMS((long double));
-extern long double fabsl _PARAMS((long double));
-extern long double floorl _PARAMS((long double));
-extern long double log1pl _PARAMS((long double));
-extern long double expm1l _PARAMS((long double));
-#endif /* ! defined (__math_68881) */
-/* Non reentrant ANSI C functions.  */
-#ifndef _REENT_ONLY
-#ifndef __math_68881
-extern long double acosl _PARAMS((long double));
-extern long double asinl _PARAMS((long double));
-extern long double atan2l _PARAMS((long double, long double));
-extern long double coshl _PARAMS((long double));
-extern long double sinhl _PARAMS((long double));
-extern long double expl _PARAMS((long double));
-extern long double ldexpl _PARAMS((long double, int));
-extern long double logl _PARAMS((long double));
-extern long double log10l _PARAMS((long double));
-extern long double powl _PARAMS((long double, long double));
-extern long double sqrtl _PARAMS((long double));
-extern long double fmodl _PARAMS((long double, long double));
-extern long double hypotl _PARAMS((long double, long double));
-#endif /* ! defined (__math_68881) */
-#endif /* ! defined (_REENT_ONLY) */
-extern long double copysignl _PARAMS((long double, long double));
-extern long double nanl _PARAMS((const char *));
-extern int ilogbl _PARAMS((long double));
-extern long double asinhl _PARAMS((long double));
-extern long double cbrtl _PARAMS((long double));
-extern long double nextafterl _PARAMS((long double, long double));
-extern float nexttowardf _PARAMS((float, long double));
-extern double nexttoward _PARAMS((double, long double));
-extern long double nexttowardl _PARAMS((long double, long double));
-extern long double logbl _PARAMS((long double));
-extern long double log2l _PARAMS((long double));
-extern long double rintl _PARAMS((long double));
-extern long double scalbnl _PARAMS((long double, int));
-extern long double exp2l _PARAMS((long double));
-extern long double scalblnl _PARAMS((long double, long));
-extern long double tgammal _PARAMS((long double));
-extern long double nearbyintl _PARAMS((long double));
-extern long int lrintl _PARAMS((long double));
-extern long long int llrintl _PARAMS((long double));
-extern long double roundl _PARAMS((long double));
-extern long lroundl _PARAMS((long double));
-extern long long int llroundl _PARAMS((long double));
-extern long double truncl _PARAMS((long double));
-extern long double remquol _PARAMS((long double, long double, int *));
-extern long double fdiml _PARAMS((long double, long double));
-extern long double fmaxl _PARAMS((long double, long double));
-extern long double fminl _PARAMS((long double, long double));
-extern long double fmal _PARAMS((long double, long double, long double));
-#ifndef _REENT_ONLY
-extern long double acoshl _PARAMS((long double));
-extern long double atanhl _PARAMS((long double));
-extern long double remainderl _PARAMS((long double, long double));
-extern long double lgammal _PARAMS((long double));
-extern long double erfl _PARAMS((long double));
-extern long double erfcl _PARAMS((long double));
-#endif /* ! defined (_REENT_ONLY) */
-#else /* !_LDBL_EQ_DBL */
-#ifdef __i386__
-/* Other long double precision functions.  */
-extern _LONG_DOUBLE rintl _PARAMS((_LONG_DOUBLE));
-extern long int lrintl _PARAMS((_LONG_DOUBLE));
-extern long long int llrintl _PARAMS((_LONG_DOUBLE));
-#endif /* __i386__ */
-#endif /* !_LDBL_EQ_DBL */
-
-#endif /* !defined (__STRICT_ANSI__) || defined(__cplusplus) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */
-
-#if !defined (__STRICT_ANSI__) || defined(__cplusplus)
-
-extern double drem _PARAMS((double, double));
-extern void sincos _PARAMS((double, double *, double *));
-extern double gamma_r _PARAMS((double, int *));
-extern double lgamma_r _PARAMS((double, int *));
-
-extern double y0 _PARAMS((double));
-extern double y1 _PARAMS((double));
-extern double yn _PARAMS((int, double));
-extern double j0 _PARAMS((double));
-extern double j1 _PARAMS((double));
-extern double jn _PARAMS((int, double));
-
-extern float dremf _PARAMS((float, float));
-extern void sincosf _PARAMS((float, float *, float *));
-extern float gammaf_r _PARAMS((float, int *));
-extern float lgammaf_r _PARAMS((float, int *));
-
-extern float y0f _PARAMS((float));
-extern float y1f _PARAMS((float));
-extern float ynf _PARAMS((int, float));
-extern float j0f _PARAMS((float));
-extern float j1f _PARAMS((float));
-extern float jnf _PARAMS((int, float));
-
-/* GNU extensions */
-# ifndef exp10
-extern double exp10 _PARAMS((double));
-# endif
-# ifndef pow10
-extern double pow10 _PARAMS((double));
-# endif
-# ifndef exp10f
-extern float exp10f _PARAMS((float));
-# endif
-# ifndef pow10f
-extern float pow10f _PARAMS((float));
-# endif
-
-#endif /* !defined (__STRICT_ANSI__) || defined(__cplusplus) */
-
-#ifndef __STRICT_ANSI__
-
-/* The gamma functions use a global variable, signgam.  */
-#ifndef _REENT_ONLY
-#define signgam (*__signgam())
-extern int *__signgam _PARAMS((void));
-#endif /* ! defined (_REENT_ONLY) */
-
-#define __signgam_r(ptr) _REENT_SIGNGAM(ptr)
-
-/* The exception structure passed to the matherr routine.  */
-/* We have a problem when using C++ since `exception' is a reserved
-   name in C++.  */
-#ifdef __cplusplus
-struct __exception
-#else
-struct exception
-#endif
-{
-  int type;
-  char *name;
-  double arg1;
-  double arg2;
-  double retval;
-  int err;
-};
-
-#ifdef __cplusplus
-extern int matherr _PARAMS((struct __exception *e));
-#else
-extern int matherr _PARAMS((struct exception *e));
-#endif
-
-/* Values for the type field of struct exception.  */
-
-#define DOMAIN 1
-#define SING 2
-#define OVERFLOW 3
-#define UNDERFLOW 4
-#define TLOSS 5
-#define PLOSS 6
-
-#endif /* ! defined (__STRICT_ANSI__) */
-
-/* Useful constants.  */
-
-#if !defined(__STRICT_ANSI__) || ((_XOPEN_SOURCE - 0) >= 500)
-
-#define MAXFLOAT	3.40282347e+38F
-
-#define M_E		2.7182818284590452354
-#define M_LOG2E		1.4426950408889634074
-#define M_LOG10E	0.43429448190325182765
-#define M_LN2		_M_LN2
-#define M_LN10		2.30258509299404568402
-#define M_PI		3.14159265358979323846
-#define M_PI_2		1.57079632679489661923
-#define M_PI_4		0.78539816339744830962
-#define M_1_PI		0.31830988618379067154
-#define M_2_PI		0.63661977236758134308
-#define M_2_SQRTPI	1.12837916709551257390
-#define M_SQRT2		1.41421356237309504880
-#define M_SQRT1_2	0.70710678118654752440
-
-#endif
-
-#ifndef __STRICT_ANSI__
-
-#define M_TWOPI         (M_PI * 2.0)
-#define M_3PI_4		2.3561944901923448370E0
-#define M_SQRTPI        1.77245385090551602792981
-#define M_LN2LO         1.9082149292705877000E-10
-#define M_LN2HI         6.9314718036912381649E-1
-#define M_SQRT3	1.73205080756887719000
-#define M_IVLN10        0.43429448190325182765 /* 1 / log(10) */
-#define M_LOG2_E        _M_LN2
-#define M_INVLN2        1.4426950408889633870E0  /* 1 / log(2) */
-
-/* Global control over fdlibm error handling.  */
-
-enum __fdlibm_version
-{
-  __fdlibm_ieee = -1,
-  __fdlibm_svid,
-  __fdlibm_xopen,
-  __fdlibm_posix
-};
-
-#define _LIB_VERSION_TYPE enum __fdlibm_version
-#define _LIB_VERSION __fdlib_version
-
-extern __IMPORT _LIB_VERSION_TYPE _LIB_VERSION;
-
-#define _IEEE_  __fdlibm_ieee
-#define _SVID_  __fdlibm_svid
-#define _XOPEN_ __fdlibm_xopen
-#define _POSIX_ __fdlibm_posix
-
-#endif /* ! defined (__STRICT_ANSI__) */
-
-_END_STD_C
-
-#ifdef __FAST_MATH__
-#include <machine/fastmath.h>
-#endif
-
-#endif /* _MATH_H_ */
diff --git a/tools/sdk/include/newlib/net/if.h b/tools/sdk/include/newlib/net/if.h
deleted file mode 100644
index 8760bb156ee..00000000000
--- a/tools/sdk/include/newlib/net/if.h
+++ /dev/null
@@ -1,45 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_PLATFORM_NET_IF_H_
-#define _ESP_PLATFORM_NET_IF_H_
-
-#define	MSG_DONTROUTE   0x4     /* send without using routing tables */
-#define	SOCK_SEQPACKET  5       /* sequenced packet stream */
-#define	MSG_EOR         0x8     /* data completes record */
-#define	SOCK_SEQPACKET  5       /* sequenced packet stream */
-#define	SOMAXCONN       128
-
-#define	IF_NAMESIZE     16
-
-#define	IPV6_UNICAST_HOPS   4  /* int; IP6 hops */
-
-#define	NI_MAXHOST  1025
-#define	NI_MAXSERV  32
-#define	NI_NUMERICSERV  0x00000008
-#define	NI_DGRAM        0x00000010
-
-
-struct ipv6_mreq {
-    struct in6_addr ipv6mr_multiaddr;
-    unsigned int    ipv6mr_interface;
-};
-
-typedef u32_t socklen_t;
-
-
-unsigned int if_nametoindex(const char *ifname);
-
-char *if_indextoname(unsigned int ifindex, char *ifname);
-
-#endif // _ESP_PLATFORM_NET_IF_H_
diff --git a/tools/sdk/include/newlib/newlib.h b/tools/sdk/include/newlib/newlib.h
deleted file mode 100644
index e9bf5664561..00000000000
--- a/tools/sdk/include/newlib/newlib.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/* newlib.h.  Generated from newlib.hin by configure.  */
-/* newlib.hin.  Manually edited from the output of autoheader to
-   remove all PACKAGE_ macros which will collide with any user
-   package using newlib header files and having its own package name,
-   version, etc...  */
-#ifndef __NEWLIB_H__
-
-#define __NEWLIB_H__ 1
-
-/* EL/IX level */
-/* #undef _ELIX_LEVEL */
-
-/* Newlib version */
-#define _NEWLIB_VERSION "2.2.0"
-
-/* C99 formats support (such as %a, %zu, ...) in IO functions like
- * printf/scanf enabled */
-/* #undef _WANT_IO_C99_FORMATS */
-
-/* long long type support in IO functions like printf/scanf enabled */
-/* #undef _WANT_IO_LONG_LONG */
-
-/* Register application finalization function using atexit. */
-/* #undef _WANT_REGISTER_FINI */
-
-/* long double type support in IO functions like printf/scanf enabled */
-/* #undef _WANT_IO_LONG_DOUBLE */
-
-/* Positional argument support in printf functions enabled.  */
-/* #undef _WANT_IO_POS_ARGS */
-
-/* Optional reentrant struct support.  Used mostly on platforms with
-   very restricted storage.  */
-#define _WANT_REENT_SMALL 1
-
-/* Multibyte supported */
-/* #undef _MB_CAPABLE */
-
-/* MB_LEN_MAX */
-#define _MB_LEN_MAX 1
-
-/* ICONV enabled */
-/* #undef _ICONV_ENABLED */
-
-/* Enable ICONV external CCS files loading capabilities */
-/* #undef _ICONV_ENABLE_EXTERNAL_CCS */
-
-/* Define if the linker supports .preinit_array/.init_array/.fini_array
- * sections.  */
-#define HAVE_INITFINI_ARRAY 1
-
-/* True if atexit() may dynamically allocate space for cleanup
-   functions.  */
-#define _ATEXIT_DYNAMIC_ALLOC 1
-
-/* True if long double supported.  */
-#define _HAVE_LONG_DOUBLE 1
-
-/* Define if compiler supports -fno-tree-loop-distribute-patterns. */
-#define _HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1
-
-/* True if long double supported and it is equal to double.  */
-#define _LDBL_EQ_DBL 1
- 
-/* Define if uintptr_t is unsigned long on this architecture */
-/* #undef _UINTPTR_EQ_ULONG */
-
-/* Define if uintptr_t is unsigned long long on this architecture */
-/* #undef _UINTPTR_EQ_ULONGLONG */
-
-/* Define if ivo supported in streamio.  */
-#define _FVWRITE_IN_STREAMIO 1
-
-/* Define if fseek functions support seek optimization.  */
-#define _FSEEK_OPTIMIZATION 1
-
-/* Define if wide char orientation is supported.  */
-#define _WIDE_ORIENT 1
-
-/* Define if unbuffered stream file optimization is supported.  */
-#define _UNBUF_STREAM_OPT 1
-
-/* Define if lite version of exit supported.  */
-/* #undef _LITE_EXIT */
-
-/* Define if declare atexit data as global.  */
-/* #undef _REENT_GLOBAL_ATEXIT */
-
-/* Define if small footprint nano-formatted-IO implementation used.  */
-#define _NANO_FORMATTED_IO 1
-
-/*
- * Iconv encodings enabled ("to" direction)
- */
-/* #undef _ICONV_TO_ENCODING_BIG5 */
-/* #undef _ICONV_TO_ENCODING_CP775 */
-/* #undef _ICONV_TO_ENCODING_CP850 */
-/* #undef _ICONV_TO_ENCODING_CP852 */
-/* #undef _ICONV_TO_ENCODING_CP855 */
-/* #undef _ICONV_TO_ENCODING_CP866 */
-/* #undef _ICONV_TO_ENCODING_EUC_JP */
-/* #undef _ICONV_TO_ENCODING_EUC_TW */
-/* #undef _ICONV_TO_ENCODING_EUC_KR */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_1 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_10 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_11 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_13 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_14 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_15 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_2 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_3 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_4 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_5 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_6 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_7 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_8 */
-/* #undef _ICONV_TO_ENCODING_ISO_8859_9 */
-/* #undef _ICONV_TO_ENCODING_ISO_IR_111 */
-/* #undef _ICONV_TO_ENCODING_KOI8_R */
-/* #undef _ICONV_TO_ENCODING_KOI8_RU */
-/* #undef _ICONV_TO_ENCODING_KOI8_U */
-/* #undef _ICONV_TO_ENCODING_KOI8_UNI */
-/* #undef _ICONV_TO_ENCODING_UCS_2 */
-/* #undef _ICONV_TO_ENCODING_UCS_2_INTERNAL */
-/* #undef _ICONV_TO_ENCODING_UCS_2BE */
-/* #undef _ICONV_TO_ENCODING_UCS_2LE */
-/* #undef _ICONV_TO_ENCODING_UCS_4 */
-/* #undef _ICONV_TO_ENCODING_UCS_4_INTERNAL */
-/* #undef _ICONV_TO_ENCODING_UCS_4BE */
-/* #undef _ICONV_TO_ENCODING_UCS_4LE */
-/* #undef _ICONV_TO_ENCODING_US_ASCII */
-/* #undef _ICONV_TO_ENCODING_UTF_16 */
-/* #undef _ICONV_TO_ENCODING_UTF_16BE */
-/* #undef _ICONV_TO_ENCODING_UTF_16LE */
-/* #undef _ICONV_TO_ENCODING_UTF_8 */
-/* #undef _ICONV_TO_ENCODING_WIN_1250 */
-/* #undef _ICONV_TO_ENCODING_WIN_1251 */
-/* #undef _ICONV_TO_ENCODING_WIN_1252 */
-/* #undef _ICONV_TO_ENCODING_WIN_1253 */
-/* #undef _ICONV_TO_ENCODING_WIN_1254 */
-/* #undef _ICONV_TO_ENCODING_WIN_1255 */
-/* #undef _ICONV_TO_ENCODING_WIN_1256 */
-/* #undef _ICONV_TO_ENCODING_WIN_1257 */
-/* #undef _ICONV_TO_ENCODING_WIN_1258 */
-
-/*
- * Iconv encodings enabled ("from" direction)
- */
-/* #undef _ICONV_FROM_ENCODING_BIG5 */
-/* #undef _ICONV_FROM_ENCODING_CP775 */
-/* #undef _ICONV_FROM_ENCODING_CP850 */
-/* #undef _ICONV_FROM_ENCODING_CP852 */
-/* #undef _ICONV_FROM_ENCODING_CP855 */
-/* #undef _ICONV_FROM_ENCODING_CP866 */
-/* #undef _ICONV_FROM_ENCODING_EUC_JP */
-/* #undef _ICONV_FROM_ENCODING_EUC_TW */
-/* #undef _ICONV_FROM_ENCODING_EUC_KR */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_1 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_10 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_11 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_13 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_14 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_15 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_2 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_3 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_4 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_5 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_6 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_7 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_8 */
-/* #undef _ICONV_FROM_ENCODING_ISO_8859_9 */
-/* #undef _ICONV_FROM_ENCODING_ISO_IR_111 */
-/* #undef _ICONV_FROM_ENCODING_KOI8_R */
-/* #undef _ICONV_FROM_ENCODING_KOI8_RU */
-/* #undef _ICONV_FROM_ENCODING_KOI8_U */
-/* #undef _ICONV_FROM_ENCODING_KOI8_UNI */
-/* #undef _ICONV_FROM_ENCODING_UCS_2 */
-/* #undef _ICONV_FROM_ENCODING_UCS_2_INTERNAL */
-/* #undef _ICONV_FROM_ENCODING_UCS_2BE */
-/* #undef _ICONV_FROM_ENCODING_UCS_2LE */
-/* #undef _ICONV_FROM_ENCODING_UCS_4 */
-/* #undef _ICONV_FROM_ENCODING_UCS_4_INTERNAL */
-/* #undef _ICONV_FROM_ENCODING_UCS_4BE */
-/* #undef _ICONV_FROM_ENCODING_UCS_4LE */
-/* #undef _ICONV_FROM_ENCODING_US_ASCII */
-/* #undef _ICONV_FROM_ENCODING_UTF_16 */
-/* #undef _ICONV_FROM_ENCODING_UTF_16BE */
-/* #undef _ICONV_FROM_ENCODING_UTF_16LE */
-/* #undef _ICONV_FROM_ENCODING_UTF_8 */
-/* #undef _ICONV_FROM_ENCODING_WIN_1250 */
-/* #undef _ICONV_FROM_ENCODING_WIN_1251 */
-/* #undef _ICONV_FROM_ENCODING_WIN_1252 */
-/* #undef _ICONV_FROM_ENCODING_WIN_1253 */
-/* #undef _ICONV_FROM_ENCODING_WIN_1254 */
-/* #undef _ICONV_FROM_ENCODING_WIN_1255 */
-/* #undef _ICONV_FROM_ENCODING_WIN_1256 */
-/* #undef _ICONV_FROM_ENCODING_WIN_1257 */
-/* #undef _ICONV_FROM_ENCODING_WIN_1258 */
-
-#endif /* !__NEWLIB_H__ */
-
diff --git a/tools/sdk/include/newlib/paths.h b/tools/sdk/include/newlib/paths.h
deleted file mode 100644
index b1c70f588a5..00000000000
--- a/tools/sdk/include/newlib/paths.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef	_PATHS_H_
-#define _PATHS_H_
-
-#define _PATH_DEV	"/dev/"
-#define _PATH_DEVNULL   "/dev/null"
-#define _PATH_DEVZERO   "/dev/zero"
-#define _PATH_BSHELL    "/bin/sh"
-
-#endif /* _PATHS_H_ */
diff --git a/tools/sdk/include/newlib/pthread.h b/tools/sdk/include/newlib/pthread.h
deleted file mode 100644
index db1f9c1ca3c..00000000000
--- a/tools/sdk/include/newlib/pthread.h
+++ /dev/null
@@ -1,431 +0,0 @@
-/*  pthread.h
- *
- *  Written by Joel Sherrill <joel@OARcorp.com>.
- *
- *  COPYRIGHT (c) 1989-2013.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  Permission to use, copy, modify, and distribute this software for any
- *  purpose without fee is hereby granted, provided that this entire notice
- *  is included in all copies of any software which is or includes a copy
- *  or modification of this software.
- *
- *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
- *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
- *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
- *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- *  $Id$
- */
-
-#ifndef __PTHREAD_h
-#define __PTHREAD_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <unistd.h>
-
-#if defined(_POSIX_THREADS)
-
-#include <sys/types.h>
-#include <time.h>
-#include <sys/sched.h>
-#include <sys/cdefs.h>
-
-struct _pthread_cleanup_context {
-  void (*_routine)(void *);
-  void *_arg;
-  int _canceltype;
-  struct _pthread_cleanup_context *_previous;
-};
-
-/* Register Fork Handlers */
-int	_EXFUN(pthread_atfork,(void (*prepare)(void), void (*parent)(void),
-                   void (*child)(void)));
-          
-/* Mutex Initialization Attributes, P1003.1c/Draft 10, p. 81 */
-
-int	_EXFUN(pthread_mutexattr_init, (pthread_mutexattr_t *__attr));
-int	_EXFUN(pthread_mutexattr_destroy, (pthread_mutexattr_t *__attr));
-int	_EXFUN(pthread_mutexattr_getpshared,
-		(_CONST pthread_mutexattr_t *__attr, int  *__pshared));
-int	_EXFUN(pthread_mutexattr_setpshared,
-		(pthread_mutexattr_t *__attr, int __pshared));
-
-#if defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES)
-
-/* Single UNIX Specification 2 Mutex Attributes types */
-
-int _EXFUN(pthread_mutexattr_gettype,
-		(_CONST pthread_mutexattr_t *__attr, int *__kind));
-int _EXFUN(pthread_mutexattr_settype,
-		(pthread_mutexattr_t *__attr, int __kind));
-
-#endif
-
-/* Initializing and Destroying a Mutex, P1003.1c/Draft 10, p. 87 */
-
-int	_EXFUN(pthread_mutex_init,
-	(pthread_mutex_t *__mutex, _CONST pthread_mutexattr_t *__attr));
-int	_EXFUN(pthread_mutex_destroy, (pthread_mutex_t *__mutex));
-
-/* This is used to statically initialize a pthread_mutex_t. Example:
-  
-    pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
- */
-
-#define PTHREAD_MUTEX_INITIALIZER  ((pthread_mutex_t) 0xFFFFFFFF)
-
-/*  Locking and Unlocking a Mutex, P1003.1c/Draft 10, p. 93
-    NOTE: P1003.4b/D8 adds pthread_mutex_timedlock(), p. 29 */
-
-int	_EXFUN(pthread_mutex_lock, (pthread_mutex_t *__mutex));
-int	_EXFUN(pthread_mutex_trylock, (pthread_mutex_t *__mutex));
-int	_EXFUN(pthread_mutex_unlock, (pthread_mutex_t *__mutex));
-
-#if defined(_POSIX_TIMEOUTS)
-
-int	_EXFUN(pthread_mutex_timedlock,
-	(pthread_mutex_t *__mutex, _CONST struct timespec *__timeout));
-
-#endif /* _POSIX_TIMEOUTS */
-
-/* Condition Variable Initialization Attributes, P1003.1c/Draft 10, p. 96 */
- 
-int	_EXFUN(pthread_condattr_init, (pthread_condattr_t *__attr));
-int	_EXFUN(pthread_condattr_destroy, (pthread_condattr_t *__attr));
-int	_EXFUN(pthread_condattr_getpshared,
-		(_CONST pthread_condattr_t *__attr, int *__pshared));
-int	_EXFUN(pthread_condattr_setpshared,
-		(pthread_condattr_t *__attr, int __pshared));
- 
-/* Initializing and Destroying a Condition Variable, P1003.1c/Draft 10, p. 87 */
- 
-int	_EXFUN(pthread_cond_init,
-	(pthread_cond_t *__cond, _CONST pthread_condattr_t *__attr));
-int	_EXFUN(pthread_cond_destroy, (pthread_cond_t *__mutex));
- 
-/* This is used to statically initialize a pthread_cond_t. Example:
-  
-    pthread_cond_t cond = PTHREAD_COND_INITIALIZER;
- */
- 
-#define PTHREAD_COND_INITIALIZER  ((pthread_cond_t) 0xFFFFFFFF)
- 
-/* Broadcasting and Signaling a Condition, P1003.1c/Draft 10, p. 101 */
- 
-int	_EXFUN(pthread_cond_signal, (pthread_cond_t *__cond));
-int	_EXFUN(pthread_cond_broadcast, (pthread_cond_t *__cond));
- 
-/* Waiting on a Condition, P1003.1c/Draft 10, p. 105 */
- 
-int	_EXFUN(pthread_cond_wait,
-	(pthread_cond_t *__cond, pthread_mutex_t *__mutex));
- 
-int	_EXFUN(pthread_cond_timedwait,
-		(pthread_cond_t *__cond, pthread_mutex_t *__mutex,
-		_CONST struct timespec *__abstime));
- 
-#if defined(_POSIX_THREAD_PRIORITY_SCHEDULING)
-
-/* Thread Creation Scheduling Attributes, P1003.1c/Draft 10, p. 120 */
-
-int	_EXFUN(pthread_attr_setscope,
-		(pthread_attr_t *__attr, int __contentionscope));
-int	_EXFUN(pthread_attr_getscope,
-	(_CONST pthread_attr_t *__attr, int *__contentionscope));
-int	_EXFUN(pthread_attr_setinheritsched,
-	(pthread_attr_t *__attr, int __inheritsched));
-int	_EXFUN(pthread_attr_getinheritsched,
-	(_CONST pthread_attr_t *__attr, int *__inheritsched));
-int	_EXFUN(pthread_attr_setschedpolicy,
-	(pthread_attr_t *__attr, int __policy));
-int	_EXFUN(pthread_attr_getschedpolicy,
-	(_CONST pthread_attr_t *__attr, int *__policy));
-
-#endif /* defined(_POSIX_THREAD_PRIORITY_SCHEDULING) */
-
-int	_EXFUN(pthread_attr_setschedparam,
-	(pthread_attr_t *__attr, _CONST struct sched_param *__param));
-int	_EXFUN(pthread_attr_getschedparam,
-	(_CONST pthread_attr_t *__attr, struct sched_param *__param));
-
-#if defined(_POSIX_THREAD_PRIORITY_SCHEDULING)
-
-/* Dynamic Thread Scheduling Parameters Access, P1003.1c/Draft 10, p. 124 */
-
-int	_EXFUN(pthread_getschedparam,
-	(pthread_t __pthread, int *__policy, struct sched_param *__param));
-int	_EXFUN(pthread_setschedparam,
-	(pthread_t __pthread, int __policy, struct sched_param *__param));
-
-#endif /* defined(_POSIX_THREAD_PRIORITY_SCHEDULING) */
-
-#if defined(_POSIX_THREAD_PRIO_INHERIT) || defined(_POSIX_THREAD_PRIO_PROTECT)
-
-/* Mutex Initialization Scheduling Attributes, P1003.1c/Draft 10, p. 128 */
- 
-int	_EXFUN(pthread_mutexattr_setprotocol,
-	(pthread_mutexattr_t *__attr, int __protocol));
-int	_EXFUN(pthread_mutexattr_getprotocol,
-	(_CONST pthread_mutexattr_t *__attr, int *__protocol));
-int	_EXFUN(pthread_mutexattr_setprioceiling,
-	(pthread_mutexattr_t *__attr, int __prioceiling));
-int	_EXFUN(pthread_mutexattr_getprioceiling,
-	(_CONST pthread_mutexattr_t *__attr, int *__prioceiling));
-
-#endif /* _POSIX_THREAD_PRIO_INHERIT || _POSIX_THREAD_PRIO_PROTECT */
-
-#if defined(_POSIX_THREAD_PRIO_PROTECT)
-
-/* Change the Priority Ceiling of a Mutex, P1003.1c/Draft 10, p. 131 */
-
-int	_EXFUN(pthread_mutex_setprioceiling,
-	(pthread_mutex_t *__mutex, int __prioceiling, int *__old_ceiling));
-int	_EXFUN(pthread_mutex_getprioceiling,
-	(pthread_mutex_t *__mutex, int *__prioceiling));
-
-#endif /* _POSIX_THREAD_PRIO_PROTECT */
-
-/* Thread Creation Attributes, P1003.1c/Draft 10, p, 140 */
-
-int	_EXFUN(pthread_attr_init, (pthread_attr_t *__attr));
-int	_EXFUN(pthread_attr_destroy, (pthread_attr_t *__attr));
-int	_EXFUN(pthread_attr_setstack, (pthread_attr_t *attr,
-	void *__stackaddr, size_t __stacksize));
-int	_EXFUN(pthread_attr_getstack, (_CONST pthread_attr_t *attr,
-	void **__stackaddr, size_t *__stacksize));
-int	_EXFUN(pthread_attr_getstacksize,
-	(_CONST pthread_attr_t *__attr, size_t *__stacksize));
-int	_EXFUN(pthread_attr_setstacksize,
-	(pthread_attr_t *__attr, size_t __stacksize));
-int	_EXFUN(pthread_attr_getstackaddr,
-	(_CONST pthread_attr_t *__attr, void **__stackaddr));
-int	_EXFUN(pthread_attr_setstackaddr,
-	(pthread_attr_t  *__attr, void *__stackaddr));
-int	_EXFUN(pthread_attr_getdetachstate,
-	(_CONST pthread_attr_t *__attr, int *__detachstate));
-int	_EXFUN(pthread_attr_setdetachstate,
-	(pthread_attr_t *__attr, int __detachstate));
-int	_EXFUN(pthread_attr_getguardsize,
-	(_CONST pthread_attr_t *__attr, size_t *__guardsize));
-int	_EXFUN(pthread_attr_setguardsize,
-	(pthread_attr_t *__attr, size_t __guardsize));
-
-/* POSIX thread APIs beyond the POSIX standard but provided 
- * in GNU/Linux. They may be provided by other OSes for
- * compatibility.
- */
-#if defined(__GNU_VISIBLE)
-#if defined(__rtems__) 
-int	_EXFUN(pthread_attr_setaffinity_np,
-	(pthread_attr_t *__attr, size_t __cpusetsize, 
-	const cpu_set_t *__cpuset));
-int 	_EXFUN(pthread_attr_getaffinity_np,
-	(const pthread_attr_t *__attr, size_t __cpusetsize,
-	cpu_set_t *__cpuset));
-
-int	_EXFUN(pthread_setaffinity_np,
-	(pthread_t __id, size_t __cpusetsize, const cpu_set_t *__cpuset));
-int	_EXFUN(pthread_getaffinity_np,
-	(const pthread_t __id, size_t __cpusetsize, cpu_set_t *__cpuset));
-
-int	_EXFUN(pthread_getattr_np,
-	(pthread_t __id, pthread_attr_t *__attr));
-#endif /* defined(__rtems__) */
-#endif /* defined(__GNU_VISIBLE) */
-
-/* Thread Creation, P1003.1c/Draft 10, p. 144 */
-
-int	_EXFUN(pthread_create,
-	(pthread_t *__pthread, _CONST pthread_attr_t  *__attr,
-	void *(*__start_routine)( void * ), void *__arg));
-
-/* Wait for Thread Termination, P1003.1c/Draft 10, p. 147 */
-
-int	_EXFUN(pthread_join, (pthread_t __pthread, void **__value_ptr));
-
-/* Detaching a Thread, P1003.1c/Draft 10, p. 149 */
-
-int	_EXFUN(pthread_detach, (pthread_t __pthread));
-
-/* Thread Termination, p1003.1c/Draft 10, p. 150 */
-
-void	_EXFUN(pthread_exit, (void *__value_ptr));
-
-/* Get Calling Thread's ID, p1003.1c/Draft 10, p. XXX */
-
-pthread_t	_EXFUN(pthread_self, (void));
-
-/* Compare Thread IDs, p1003.1c/Draft 10, p. 153 */
-
-int	_EXFUN(pthread_equal, (pthread_t __t1, pthread_t __t2));
-
-/* Dynamic Package Initialization */
-
-/* This is used to statically initialize a pthread_once_t. Example:
-  
-    pthread_once_t once = PTHREAD_ONCE_INIT;
-  
-    NOTE:  This is named inconsistently -- it should be INITIALIZER.  */
- 
-#define PTHREAD_ONCE_INIT  { 1, 0 }  /* is initialized and not run */
- 
-int	_EXFUN(pthread_once,
-	(pthread_once_t *__once_control, void (*__init_routine)(void)));
-
-/* Thread-Specific Data Key Create, P1003.1c/Draft 10, p. 163 */
-
-int	_EXFUN(pthread_key_create,
-	(pthread_key_t *__key, void (*__destructor)( void * )));
-
-/* Thread-Specific Data Management, P1003.1c/Draft 10, p. 165 */
-
-int	_EXFUN(pthread_setspecific,
-	(pthread_key_t __key, _CONST void *__value));
-void *	_EXFUN(pthread_getspecific, (pthread_key_t __key));
-
-/* Thread-Specific Data Key Deletion, P1003.1c/Draft 10, p. 167 */
-
-int	_EXFUN(pthread_key_delete, (pthread_key_t __key));
-
-/* Execution of a Thread, P1003.1c/Draft 10, p. 181 */
-
-#define PTHREAD_CANCEL_ENABLE  0
-#define PTHREAD_CANCEL_DISABLE 1
-
-#define PTHREAD_CANCEL_DEFERRED 0
-#define PTHREAD_CANCEL_ASYNCHRONOUS 1
-
-#define PTHREAD_CANCELED ((void *) -1)
-
-int	_EXFUN(pthread_cancel, (pthread_t __pthread));
-
-/* Setting Cancelability State, P1003.1c/Draft 10, p. 183 */
-
-int	_EXFUN(pthread_setcancelstate, (int __state, int *__oldstate));
-int	_EXFUN(pthread_setcanceltype, (int __type, int *__oldtype));
-void 	_EXFUN(pthread_testcancel, (void));
-
-/* Establishing Cancellation Handlers, P1003.1c/Draft 10, p. 184 */
-
-void	_EXFUN(_pthread_cleanup_push,
-	(struct _pthread_cleanup_context *_context,
-	void (*_routine)(void *), void *_arg));
-
-void	_EXFUN(_pthread_cleanup_pop,
-	(struct _pthread_cleanup_context *_context,
-	int _execute));
-
-/* It is intentional to open and close the scope in two different macros */
-#define pthread_cleanup_push(_routine, _arg) \
-  do { \
-    struct _pthread_cleanup_context _pthread_clup_ctx; \
-    _pthread_cleanup_push(&_pthread_clup_ctx, (_routine), (_arg))
-
-#define pthread_cleanup_pop(_execute) \
-    _pthread_cleanup_pop(&_pthread_clup_ctx, (_execute)); \
-  } while (0)
-
-#if defined(_GNU_SOURCE)
-void	_EXFUN(_pthread_cleanup_push_defer,
-	(struct _pthread_cleanup_context *_context,
-	void (*_routine)(void *), void *_arg));
-
-void	_EXFUN(_pthread_cleanup_pop_restore,
-	(struct _pthread_cleanup_context *_context,
-	int _execute));
-
-/* It is intentional to open and close the scope in two different macros */
-#define pthread_cleanup_push_defer_np(_routine, _arg) \
-  do { \
-    struct _pthread_cleanup_context _pthread_clup_ctx; \
-    _pthread_cleanup_push_defer(&_pthread_clup_ctx, (_routine), (_arg))
-
-#define pthread_cleanup_pop_restore_np(_execute) \
-    _pthread_cleanup_pop_restore(&_pthread_clup_ctx, (_execute)); \
-  } while (0)
-#endif /* defined(_GNU_SOURCE) */
-
-#if defined(_POSIX_THREAD_CPUTIME)
- 
-/* Accessing a Thread CPU-time Clock, P1003.4b/D8, p. 58 */
- 
-int	_EXFUN(pthread_getcpuclockid,
-	(pthread_t __pthread_id, clockid_t *__clock_id));
- 
-#endif /* defined(_POSIX_THREAD_CPUTIME) */
-
-
-#endif /* defined(_POSIX_THREADS) */
-
-#if defined(_POSIX_BARRIERS)
-
-int	_EXFUN(pthread_barrierattr_init, (pthread_barrierattr_t *__attr));
-int	_EXFUN(pthread_barrierattr_destroy, (pthread_barrierattr_t *__attr));
-int	_EXFUN(pthread_barrierattr_getpshared,
-	(_CONST pthread_barrierattr_t *__attr, int *__pshared));
-int	_EXFUN(pthread_barrierattr_setpshared,
-	(pthread_barrierattr_t *__attr, int __pshared));
-
-#define PTHREAD_BARRIER_SERIAL_THREAD -1
-
-int	_EXFUN(pthread_barrier_init,
-	(pthread_barrier_t *__barrier,
-	_CONST pthread_barrierattr_t *__attr, unsigned __count));
-int	_EXFUN(pthread_barrier_destroy, (pthread_barrier_t *__barrier));
-int	_EXFUN(pthread_barrier_wait,(pthread_barrier_t *__barrier));
-
-#endif /* defined(_POSIX_BARRIERS) */
-
-#if defined(_POSIX_SPIN_LOCKS)
-
-int	_EXFUN(pthread_spin_init,
-	(pthread_spinlock_t *__spinlock, int __pshared));
-int	_EXFUN(pthread_spin_destroy, (pthread_spinlock_t *__spinlock));
-int	_EXFUN(pthread_spin_lock, (pthread_spinlock_t *__spinlock));
-int	_EXFUN(pthread_spin_trylock, (pthread_spinlock_t *__spinlock));
-int	_EXFUN(pthread_spin_unlock, (pthread_spinlock_t *__spinlock));
-
-#endif /* defined(_POSIX_SPIN_LOCKS) */
-
-#if defined(_POSIX_READER_WRITER_LOCKS)
-
-/* This is used to statically initialize a pthread_rwlock_t. Example:
-  
-    pthread_mutex_t mutex = PTHREAD_RWLOCK_INITIALIZER;
- */
-
-#define PTHREAD_RWLOCK_INITIALIZER  ((pthread_rwlock_t) 0xFFFFFFFF)
-
-int	_EXFUN(pthread_rwlockattr_init, (pthread_rwlockattr_t *__attr));
-int	_EXFUN(pthread_rwlockattr_destroy, (pthread_rwlockattr_t *__attr));
-int	_EXFUN(pthread_rwlockattr_getpshared,
-	(_CONST pthread_rwlockattr_t *__attr, int *__pshared));
-int	_EXFUN(pthread_rwlockattr_setpshared,
-	(pthread_rwlockattr_t *__attr, int __pshared));
-
-int	_EXFUN(pthread_rwlock_init,
-	(pthread_rwlock_t *__rwlock, _CONST pthread_rwlockattr_t *__attr));
-int	_EXFUN(pthread_rwlock_destroy, (pthread_rwlock_t *__rwlock));
-int	_EXFUN(pthread_rwlock_rdlock,(pthread_rwlock_t *__rwlock));
-int	_EXFUN(pthread_rwlock_tryrdlock,(pthread_rwlock_t *__rwlock));
-int	_EXFUN(pthread_rwlock_timedrdlock,
-        (pthread_rwlock_t *__rwlock, _CONST struct timespec *__abstime));
-int	_EXFUN(pthread_rwlock_unlock,(pthread_rwlock_t *__rwlock));
-int	_EXFUN(pthread_rwlock_wrlock,(pthread_rwlock_t *__rwlock));
-int	_EXFUN(pthread_rwlock_trywrlock,(pthread_rwlock_t *__rwlock));
-int	_EXFUN(pthread_rwlock_timedwrlock,
-        (pthread_rwlock_t *__rwlock, _CONST struct timespec *__abstime));
-
-#endif /* defined(_POSIX_READER_WRITER_LOCKS) */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/* end of include file */
diff --git a/tools/sdk/include/newlib/pwd.h b/tools/sdk/include/newlib/pwd.h
deleted file mode 100644
index 3dea4ee2d1a..00000000000
--- a/tools/sdk/include/newlib/pwd.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*-
- * Copyright (c) 1989 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)pwd.h	5.13 (Berkeley) 5/28/91
- */
-
-#ifndef _PWD_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-#define	_PWD_H_
-
-#include <sys/cdefs.h>
-#include <sys/types.h>
-
-#if __BSD_VISIBLE
-#define	_PATH_PASSWD		"/etc/passwd"
-
-#define	_PASSWORD_LEN		128	/* max length, not counting NULL */
-#endif
-
-struct passwd {
-	char	*pw_name;		/* user name */
-	char	*pw_passwd;		/* encrypted password */
-	uid_t	pw_uid;			/* user uid */
-	gid_t	pw_gid;			/* user gid */
-	char	*pw_comment;		/* comment */
-	char	*pw_gecos;		/* Honeywell login info */
-	char	*pw_dir;		/* home directory */
-	char	*pw_shell;		/* default shell */
-};
-
-#ifndef __INSIDE_CYGWIN__
-struct passwd	*getpwuid (uid_t);
-struct passwd	*getpwnam (const char *);
-
-#if __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE >= 500
-int 		 getpwnam_r (const char *, struct passwd *,
-			char *, size_t , struct passwd **);
-int		 getpwuid_r (uid_t, struct passwd *, char *,
-			size_t, struct passwd **);
-#endif
-
-#if __XSI_VISIBLE >= 500
-struct passwd	*getpwent (void);
-void		 setpwent (void);
-void		 endpwent (void);
-#endif
-
-#if __BSD_VISIBLE
-int		 setpassent (int);
-#endif
-#endif /*!__INSIDE_CYGWIN__*/
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _PWD_H_ */
diff --git a/tools/sdk/include/newlib/reent.h b/tools/sdk/include/newlib/reent.h
deleted file mode 100644
index 861be71d353..00000000000
--- a/tools/sdk/include/newlib/reent.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/* This header file provides the reentrancy.  */
-
-/* The reentrant system calls here serve two purposes:
-
-   1) Provide reentrant versions of the system calls the ANSI C library
-      requires.
-   2) Provide these system calls in a namespace clean way.
-
-   It is intended that *all* system calls that the ANSI C library needs
-   be declared here.  It documents them all in one place.  All library access
-   to the system is via some form of these functions.
-
-   The target may provide the needed syscalls by any of the following:
-
-   1) Define the reentrant versions of the syscalls directly.
-      (eg: _open_r, _close_r, etc.).  Please keep the namespace clean.
-      When you do this, set "syscall_dir" to "syscalls" and add
-      -DREENTRANT_SYSCALLS_PROVIDED to newlib_cflags in configure.host.
-
-   2) Define namespace clean versions of the system calls by prefixing
-      them with '_' (eg: _open, _close, etc.).  Technically, there won't be
-      true reentrancy at the syscall level, but the library will be namespace
-      clean.
-      When you do this, set "syscall_dir" to "syscalls" in configure.host.
-
-   3) Define or otherwise provide the regular versions of the syscalls
-      (eg: open, close, etc.).  The library won't be reentrant nor namespace
-      clean, but at least it will work.
-      When you do this, add -DMISSING_SYSCALL_NAMES to newlib_cflags in
-      configure.host.
-
-   4) Define or otherwise provide the regular versions of the syscalls,
-      and do not supply functional interfaces for any of the reentrant
-      calls. With this method, the reentrant syscalls are redefined to
-      directly call the regular system call without the reentrancy argument.
-      When you do this, specify both -DREENTRANT_SYSCALLS_PROVIDED and 
-      -DMISSING_SYSCALL_NAMES via newlib_cflags in configure.host and do
-      not specify "syscall_dir".
-
-   Stubs of the reentrant versions of the syscalls exist in the libc/reent
-   source directory and are provided if REENTRANT_SYSCALLS_PROVIDED isn't 
-   defined.  These stubs call the native system calls: _open, _close, etc. 
-   if MISSING_SYSCALL_NAMES is *not* defined, otherwise they call the
-   non-underscored versions: open, close, etc. when MISSING_SYSCALL_NAMES
-   *is* defined.
-
-   By default, newlib functions call the reentrant syscalls internally,
-   passing a reentrancy structure as an argument.  This reentrancy structure
-   contains data that is thread-specific.  For example, the errno value is
-   kept in the reentrancy structure.  If multiple threads exist, each will
-   keep a separate errno value which is intuitive since the application flow
-   cannot check for failure reliably otherwise.
-
-   The reentrant syscalls are either provided by the platform, by the 
-   libc/reent stubs, or in the case of both MISSING_SYSCALL_NAMES and 
-   REENTRANT_SYSCALLS_PROVIDED being defined, the calls are redefined to
-   simply call the regular syscalls with no reentrancy struct argument.
-
-   A single-threaded application does not need to worry about the reentrancy
-   structure.  It is used internally.  
-
-   A multi-threaded application needs either to manually manage reentrancy 
-   structures or use dynamic reentrancy.
-   
-   Manually managing reentrancy structures entails calling special reentrant
-   versions of newlib functions that have an additional reentrancy argument.
-   For example, _printf_r.  By convention, the first argument is the
-   reentrancy structure.  By default, the normal version of the function
-   uses the default reentrancy structure: _REENT.  The reentrancy structure
-   is passed internally, eventually to the reentrant syscalls themselves.
-   How the structures are stored and accessed in this model is up to the
-   application.
-
-   Dynamic reentrancy is specified by the __DYNAMIC_REENT__ flag.  This
-   flag denotes setting up a macro to replace _REENT with a function call
-   to __getreent().  This function needs to be implemented by the platform
-   and it is meant to return the reentrancy structure for the current
-   thread.  When the regular C functions (e.g. printf) go to call internal
-   routines with the default _REENT structure, they end up calling with 
-   the reentrancy structure for the thread.  Thus, application code does not
-   need to call the _r routines nor worry about reentrancy structures.  */
-
-/* WARNING: All identifiers here must begin with an underscore.  This file is
-   included by stdio.h and others and we therefore must only use identifiers
-   in the namespace allotted to us.  */
-
-#ifndef _REENT_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-#define _REENT_H_
-
-#include <sys/reent.h>
-#include <sys/_types.h>
-#include <machine/types.h>
-
-#define __need_size_t
-#define __need_ptrdiff_t
-#include <stddef.h>
-
-/* FIXME: not namespace clean */
-struct stat;
-struct tms;
-struct timeval;
-struct timezone;
-
-#if defined(REENTRANT_SYSCALLS_PROVIDED) && defined(MISSING_SYSCALL_NAMES)
-
-#define _close_r(__reent, __fd)                   close(__fd)
-#define _execve_r(__reent, __f, __arg, __env)     execve(__f, __arg, __env)
-#define _fcntl_r(__reent, __fd, __cmd, __arg)     fcntl(__fd, __cmd, __arg)
-#define _fork_r(__reent)                          fork()
-#define _fstat_r(__reent, __fdes, __stat)         fstat(__fdes, __stat)
-#define _getpid_r(__reent)                        getpid()
-#define _isatty_r(__reent, __desc)                isatty(__desc)
-#define _kill_r(__reent, __pid, __signal)         kill(__pid, __signal)
-#define _link_r(__reent, __oldpath, __newpath)    link(__oldpath, __newpath)
-#define _lseek_r(__reent, __fdes, __off, __w)     lseek(__fdes, __off, __w)
-#define _mkdir_r(__reent, __path, __m)		  mkdir(__path, __m)
-#define _open_r(__reent, __path, __flag, __m)     open(__path, __flag, __m)
-#define _read_r(__reent, __fd, __buff, __cnt)     read(__fd, __buff, __cnt)
-#define _rename_r(__reent, __old, __new)	  rename(__old, __new)
-#define _sbrk_r(__reent, __incr)                  sbrk(__incr)
-#define _stat_r(__reent, __path, __buff)          stat(__path, __buff)
-#define _times_r(__reent, __time)                 times(__time)
-#define _unlink_r(__reent, __path)                unlink(__path)
-#define _wait_r(__reent, __status)                wait(__status)
-#define _write_r(__reent, __fd, __buff, __cnt)    write(__fd, __buff, __cnt)
-#define _gettimeofday_r(__reent, __tp, __tzp)     gettimeofday(__tp, __tzp)
-
-#ifdef __LARGE64_FILES
-#define _lseek64_r(__reent, __fd, __off, __w)     lseek64(__fd, __off, __w)
-#define _fstat64_r(__reent, __fd, __buff)         fstat64(__fd, __buff)
-#define _open64_r(__reent, __path, __flag, __m)   open64(__path, __flag, __m)
-#endif
-
-#else
-/* Reentrant versions of system calls.  */
-
-extern int _close_r _PARAMS ((struct _reent *, int));
-extern int _execve_r _PARAMS ((struct _reent *, const char *, char *const *, char *const *));
-extern int _fcntl_r _PARAMS ((struct _reent *, int, int, int));
-extern int _fork_r _PARAMS ((struct _reent *));
-extern int _fstat_r _PARAMS ((struct _reent *, int, struct stat *));
-extern int _getpid_r _PARAMS ((struct _reent *));
-extern int _isatty_r _PARAMS ((struct _reent *, int));
-extern int _kill_r _PARAMS ((struct _reent *, int, int));
-extern int _link_r _PARAMS ((struct _reent *, const char *, const char *));
-extern _off_t _lseek_r _PARAMS ((struct _reent *, int, _off_t, int));
-extern int _mkdir_r _PARAMS ((struct _reent *, const char *, int));
-extern int _open_r _PARAMS ((struct _reent *, const char *, int, int));
-extern _ssize_t _read_r _PARAMS ((struct _reent *, int, void *, size_t));
-extern int _rename_r _PARAMS ((struct _reent *, const char *, const char *));
-extern void *_sbrk_r _PARAMS ((struct _reent *, ptrdiff_t));
-extern int _stat_r _PARAMS ((struct _reent *, const char *, struct stat *));
-extern _CLOCK_T_ _times_r _PARAMS ((struct _reent *, struct tms *));
-extern int _unlink_r _PARAMS ((struct _reent *, const char *));
-extern int _wait_r _PARAMS ((struct _reent *, int *));
-extern _ssize_t _write_r _PARAMS ((struct _reent *, int, const void *, size_t));
-
-/* This one is not guaranteed to be available on all targets.  */
-extern int _gettimeofday_r _PARAMS ((struct _reent *, struct timeval *__tp, void *__tzp));
-
-#ifdef __LARGE64_FILES
-
-
-#if defined(__CYGWIN__)
-#define stat64 stat
-#endif
-struct stat64;
-
-extern _off64_t _lseek64_r _PARAMS ((struct _reent *, int, _off64_t, int));
-extern int _fstat64_r _PARAMS ((struct _reent *, int, struct stat64 *));
-extern int _open64_r _PARAMS ((struct _reent *, const char *, int, int));
-extern int _stat64_r _PARAMS ((struct _reent *, const char *, struct stat64 *));
-
-/* Don't pollute namespace if not building newlib. */
-#if defined (__CYGWIN__) && !defined (_COMPILING_NEWLIB)
-#undef stat64
-#endif
-
-#endif
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _REENT_H_ */
diff --git a/tools/sdk/include/newlib/regdef.h b/tools/sdk/include/newlib/regdef.h
deleted file mode 100644
index 8cf144b85f3..00000000000
--- a/tools/sdk/include/newlib/regdef.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* regdef.h -- define register names.  */
-
-/* This is a standard include file for MIPS targets.  Other target
-   probably don't define it, and attempts to include this file will
-   fail.  */
-
-#include <machine/regdef.h>
diff --git a/tools/sdk/include/newlib/regex.h b/tools/sdk/include/newlib/regex.h
deleted file mode 100644
index fa3e26879ae..00000000000
--- a/tools/sdk/include/newlib/regex.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*-
- * Copyright (c) 1992 Henry Spencer.
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * Henry Spencer of the University of Toronto.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)regex.h	8.2 (Berkeley) 1/3/94
- * $FreeBSD: src/include/regex.h,v 1.4 2002/03/23 17:24:53 imp Exp $
- */
-
-#ifndef _REGEX_H_
-#define	_REGEX_H_
-
-#include <sys/cdefs.h>
-
-/* types */
-typedef off_t regoff_t;
-
-typedef struct {
-	int re_magic;
-	size_t re_nsub;		/* number of parenthesized subexpressions */
-	__const char *re_endp;	/* end pointer for REG_PEND */
-	struct re_guts *re_g;	/* none of your business :-) */
-} regex_t;
-
-typedef struct {
-	regoff_t rm_so;		/* start of match */
-	regoff_t rm_eo;		/* end of match */
-} regmatch_t;
-
-/* regcomp() flags */
-#define	REG_BASIC	0000
-#define	REG_EXTENDED	0001
-#define	REG_ICASE	0002
-#define	REG_NOSUB	0004
-#define	REG_NEWLINE	0010
-#define	REG_NOSPEC	0020
-#define	REG_PEND	0040
-#define	REG_DUMP	0200
-
-/* regerror() flags */
-#define	REG_NOMATCH	 1
-#define	REG_BADPAT	 2
-#define	REG_ECOLLATE	 3
-#define	REG_ECTYPE	 4
-#define	REG_EESCAPE	 5
-#define	REG_ESUBREG	 6
-#define	REG_EBRACK	 7
-#define	REG_EPAREN	 8
-#define	REG_EBRACE	 9
-#define	REG_BADBR	10
-#define	REG_ERANGE	11
-#define	REG_ESPACE	12
-#define	REG_BADRPT	13
-#define	REG_EMPTY	14
-#define	REG_ASSERT	15
-#define	REG_INVARG	16
-#define	REG_ATOI	255	/* convert name to number (!) */
-#define	REG_ITOA	0400	/* convert number to name (!) */
-
-/* regexec() flags */
-#define	REG_NOTBOL	00001
-#define	REG_NOTEOL	00002
-#define	REG_STARTEND	00004
-#define	REG_TRACE	00400	/* tracing of execution */
-#define	REG_LARGE	01000	/* force large representation */
-#define	REG_BACKR	02000	/* force use of backref code */
-
-__BEGIN_DECLS
-int	regcomp(regex_t *__restrict, const char *__restrict, int);
-size_t	regerror(int, const regex_t *__restrict, char *__restrict, size_t);
-int	regexec(const regex_t *__restrict, const char *__restrict,
-			size_t, regmatch_t [__restrict], int);
-void	regfree(regex_t *);
-__END_DECLS
-
-#endif /* !_REGEX_H_ */
diff --git a/tools/sdk/include/newlib/sched.h b/tools/sdk/include/newlib/sched.h
deleted file mode 100644
index 504ad5274a4..00000000000
--- a/tools/sdk/include/newlib/sched.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- *  Written by Joel Sherrill <joel@OARcorp.com>.
- *
- *  COPYRIGHT (c) 1989-2010.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  Permission to use, copy, modify, and distribute this software for any
- *  purpose without fee is hereby granted, provided that this entire notice
- *  is included in all copies of any software which is or includes a copy
- *  or modification of this software.
- *
- *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
- *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
- *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
- *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- *  $Id$
- */
-
-#ifndef _SCHED_H_
-#define _SCHED_H_
-
-#include <sys/types.h>
-#include <sys/sched.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(_POSIX_PRIORITY_SCHEDULING)
-/*
- *  XBD 13 - Set Scheduling Parameters, P1003.1b-2008, p. 1803
- */
-int sched_setparam(
-  pid_t                     __pid,
-  const struct sched_param *__param
-);
-
-/*
- *  XBD 13 - Set Scheduling Parameters, P1003.1b-2008, p. 1800
- */
-int sched_getparam(
-  pid_t                     __pid,
-  struct sched_param       *__param
-);
-
-/*
- *  XBD 13 - Set Scheduling Policy and Scheduling Parameters,
- *         P1003.1b-2008, p. 1805
- */
-int sched_setscheduler(
-  pid_t                     __pid,
-  int                       __policy,
-  const struct sched_param *__param
-);
-
-/*
- *  XBD 13 - Get Scheduling Policy, P1003.1b-2008, p. 1801
- */
-int sched_getscheduler(
-  pid_t                     __pid
-);
-
-/*
- *  XBD 13 - Get Scheduling Parameter Limits, P1003.1b-2008, p. 1799
- */
-int sched_get_priority_max(
-  int __policy
-);
-
-int sched_get_priority_min(
-  int  __policy
-);
-
-/*
- *  XBD 13 - Get Scheduling Parameter Limits, P1003.1b-2008, p. 1802
- */
-int sched_rr_get_interval(
-  pid_t             __pid,
-  struct timespec  *__interval
-);
-#endif /* _POSIX_PRIORITY_SCHEDULING */
-
-#if defined(_POSIX_THREADS) || defined(_POSIX_PRIORITY_SCHEDULING)
-
-/*
- *  XBD 13 - Yield Processor, P1003.1b-2008, p. 1807
- */
-int sched_yield( void );
-
-#endif /* _POSIX_THREADS or _POSIX_PRIORITY_SCHEDULING */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SCHED_H_ */
diff --git a/tools/sdk/include/newlib/search.h b/tools/sdk/include/newlib/search.h
deleted file mode 100644
index ed321b0f645..00000000000
--- a/tools/sdk/include/newlib/search.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*	$NetBSD: search.h,v 1.12 1999/02/22 10:34:28 christos Exp $	*/
-/* $FreeBSD: src/include/search.h,v 1.4 2002/03/23 17:24:53 imp Exp $ */
-
-/*
- * Written by J.T. Conklin <jtc@netbsd.org>
- * Public domain.
- */
-
-#ifndef _SEARCH_H_
-#define _SEARCH_H_
-
-#include <sys/cdefs.h>
-#include <machine/ansi.h>
-#include <sys/types.h>
-
-typedef struct entry {
-	char *key;
-	void *data;
-} ENTRY;
-
-typedef enum {
-	FIND, ENTER
-} ACTION;
-
-typedef enum {
-	preorder,
-	postorder,
-	endorder,
-	leaf
-} VISIT;
-
-#ifdef _SEARCH_PRIVATE
-typedef struct node {
-	char         *key;
-	struct node  *llink, *rlink;
-} node_t;
-#endif
-
-struct hsearch_data
-{
-  struct internal_head *htable;
-  size_t htablesize;
-};
-
-#ifndef __compar_fn_t_defined
-#define __compar_fn_t_defined
-typedef int (*__compar_fn_t) (const void *, const void *);
-#endif
-
-__BEGIN_DECLS
-int	 hcreate(size_t);
-void	 hdestroy(void);
-ENTRY	*hsearch(ENTRY, ACTION);
-int	 hcreate_r(size_t, struct hsearch_data *);
-void	 hdestroy_r(struct hsearch_data *);
-int	hsearch_r(ENTRY, ACTION, ENTRY **, struct hsearch_data *);
-void	*tdelete(const void *__restrict, void **__restrict, __compar_fn_t);
-void	tdestroy (void *, void (*)(void *));
-void	*tfind(const void *, void **, __compar_fn_t);
-void	*tsearch(const void *, void **, __compar_fn_t);
-void      twalk(const void *, void (*)(const void *, VISIT, int));
-__END_DECLS
-
-#endif /* !_SEARCH_H_ */
diff --git a/tools/sdk/include/newlib/setjmp.h b/tools/sdk/include/newlib/setjmp.h
deleted file mode 100644
index 3d815d9b9b3..00000000000
--- a/tools/sdk/include/newlib/setjmp.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
-	setjmp.h
-	stubs for future use.
-*/
-
-#ifndef _SETJMP_H_
-#define _SETJMP_H_
-
-#include "_ansi.h"
-#include <machine/setjmp.h>
-
-_BEGIN_STD_C
-
-#ifdef __GNUC__
-void	_EXFUN(longjmp,(jmp_buf __jmpb, int __retval))
-			__attribute__ ((__noreturn__));
-#else
-void	_EXFUN(longjmp,(jmp_buf __jmpb, int __retval));
-#endif
-int	_EXFUN(setjmp,(jmp_buf __jmpb));
-#define setjmp(env) setjmp(env)
-
-
-_END_STD_C
-
-#endif /* _SETJMP_H_ */
-
diff --git a/tools/sdk/include/newlib/signal.h b/tools/sdk/include/newlib/signal.h
deleted file mode 100644
index 8c50a2eb30c..00000000000
--- a/tools/sdk/include/newlib/signal.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef _SIGNAL_H_
-#define _SIGNAL_H_
-
-#include "_ansi.h"
-#include <sys/signal.h>
-
-_BEGIN_STD_C
-
-typedef int	sig_atomic_t;		/* Atomic entity type (ANSI) */
-#ifndef _POSIX_SOURCE
-typedef _sig_func_ptr sig_t;		/* BSD naming */
-typedef _sig_func_ptr sighandler_t;	/* glibc naming */
-#endif /* !_POSIX_SOURCE */
-
-#define SIG_DFL ((_sig_func_ptr)0)	/* Default action */
-#define SIG_IGN ((_sig_func_ptr)1)	/* Ignore action */
-#define SIG_ERR ((_sig_func_ptr)-1)	/* Error return */
-
-struct _reent;
-
-_sig_func_ptr _EXFUN(_signal_r, (struct _reent *, int, _sig_func_ptr));
-int	_EXFUN(_raise_r, (struct _reent *, int));
-
-#ifndef _REENT_ONLY
-_sig_func_ptr _EXFUN(signal, (int, _sig_func_ptr));
-int	_EXFUN(raise, (int));
-void	_EXFUN(psignal, (int, const char *));
-#endif
-
-_END_STD_C
-
-#endif /* _SIGNAL_H_ */
diff --git a/tools/sdk/include/newlib/spawn.h b/tools/sdk/include/newlib/spawn.h
deleted file mode 100644
index 5a6692f1155..00000000000
--- a/tools/sdk/include/newlib/spawn.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*-
- * Copyright (c) 2008 Ed Schouten <ed@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _SPAWN_H_
-#define _SPAWN_H_
-
-#include <_ansi.h>
-#include <sys/cdefs.h>
-#include <sys/types.h>
-#include <sys/_types.h>
-#define __need_sigset_t
-#include <signal.h>
-
-struct sched_param;
-
-typedef struct __posix_spawnattr		*posix_spawnattr_t;
-typedef struct __posix_spawn_file_actions	*posix_spawn_file_actions_t;
-
-#define POSIX_SPAWN_RESETIDS		0x01
-#define POSIX_SPAWN_SETPGROUP		0x02
-#define POSIX_SPAWN_SETSCHEDPARAM	0x04
-#define POSIX_SPAWN_SETSCHEDULER	0x08
-#define POSIX_SPAWN_SETSIGDEF		0x10
-#define POSIX_SPAWN_SETSIGMASK		0x20
-
-_BEGIN_STD_C
-/*
- * Spawn routines
- *
- * XXX both arrays should be __restrict, but this does not work when GCC
- * is invoked with -std=c99.
- */
-int _EXFUN(posix_spawn, (pid_t *  __restrict, const char * __restrict,
-	const posix_spawn_file_actions_t *, const posix_spawnattr_t * __restrict,
-	char * const [], char * const [])
-);
-int _EXFUN(posix_spawnp, (pid_t * __restrict, const char * __restrict,
-	const posix_spawn_file_actions_t *, const posix_spawnattr_t * __restrict,
-	char * const [], char * const [])
-);
-
-/*
- * File descriptor actions
- */
-int _EXFUN(posix_spawn_file_actions_init, (posix_spawn_file_actions_t *));
-int _EXFUN(posix_spawn_file_actions_destroy, (posix_spawn_file_actions_t *));
-
-int _EXFUN(posix_spawn_file_actions_addopen,
-	(posix_spawn_file_actions_t * __restrict, int, const char * __restrict, int, mode_t)
-);
-int _EXFUN(posix_spawn_file_actions_adddup2,
-	(posix_spawn_file_actions_t *, int, int)
-);
-int _EXFUN(posix_spawn_file_actions_addclose,
-	(posix_spawn_file_actions_t *, int)
-);
-
-/*
- * Spawn attributes
- */
-int _EXFUN(posix_spawnattr_init, (posix_spawnattr_t *));
-int _EXFUN(posix_spawnattr_destroy, (posix_spawnattr_t *));
-
-int _EXFUN(posix_spawnattr_getflags,
-	(const posix_spawnattr_t * __restrict, short * __restrict)
-);
-int _EXFUN(posix_spawnattr_getpgroup,
-	(const posix_spawnattr_t * __restrict, pid_t * __restrict));
-int _EXFUN(posix_spawnattr_getschedparam,
-	(const posix_spawnattr_t * __restrict, struct sched_param * __restrict)
-);
-int _EXFUN(posix_spawnattr_getschedpolicy,
-	(const posix_spawnattr_t * __restrict, int * __restrict)
-);
-int _EXFUN(posix_spawnattr_getsigdefault,
-	(const posix_spawnattr_t * __restrict, sigset_t * __restrict)
-);
-int _EXFUN(posix_spawnattr_getsigmask,
-	(const posix_spawnattr_t * __restrict, sigset_t * __restrict)
-);
-
-int _EXFUN(posix_spawnattr_setflags, (posix_spawnattr_t *, short));
-int _EXFUN(posix_spawnattr_setpgroup, (posix_spawnattr_t *, pid_t));
-int _EXFUN(posix_spawnattr_setschedparam,
-	(posix_spawnattr_t * __restrict, const struct sched_param * __restrict)
-);
-int _EXFUN(posix_spawnattr_setschedpolicy, (posix_spawnattr_t *, int));
-int _EXFUN(posix_spawnattr_setsigdefault,
-	(posix_spawnattr_t * __restrict, const sigset_t * __restrict)
-);
-int _EXFUN(posix_spawnattr_setsigmask,
-	(posix_spawnattr_t * __restrict, const sigset_t * __restrict)
-);
-_END_STD_C
-
-#endif /* !_SPAWN_H_ */
diff --git a/tools/sdk/include/newlib/stdatomic.h b/tools/sdk/include/newlib/stdatomic.h
deleted file mode 100644
index beba325b1a2..00000000000
--- a/tools/sdk/include/newlib/stdatomic.h
+++ /dev/null
@@ -1,414 +0,0 @@
-/*-
- * Copyright (c) 2011 Ed Schouten <ed@FreeBSD.org>
- *                    David Chisnall <theraven@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _STDATOMIC_H_
-#define	_STDATOMIC_H_
-
-#include <sys/cdefs.h>
-#include <sys/_types.h>
-#include <stdint.h>
-
-#if __has_extension(c_atomic) || __has_extension(cxx_atomic)
-#define	__CLANG_ATOMICS
-#elif __GNUC_PREREQ__(4, 7)
-#define	__GNUC_ATOMICS
-#elif defined(__GNUC__)
-#define	__SYNC_ATOMICS
-#else
-#error "stdatomic.h does not support your compiler"
-#endif
-
-/*
- * 7.17.1 Atomic lock-free macros.
- */
-
-#ifdef __GCC_ATOMIC_BOOL_LOCK_FREE
-#define	ATOMIC_BOOL_LOCK_FREE		__GCC_ATOMIC_BOOL_LOCK_FREE
-#endif
-#ifdef __GCC_ATOMIC_CHAR_LOCK_FREE
-#define	ATOMIC_CHAR_LOCK_FREE		__GCC_ATOMIC_CHAR_LOCK_FREE
-#endif
-#ifdef __GCC_ATOMIC_CHAR16_T_LOCK_FREE
-#define	ATOMIC_CHAR16_T_LOCK_FREE	__GCC_ATOMIC_CHAR16_T_LOCK_FREE
-#endif
-#ifdef __GCC_ATOMIC_CHAR32_T_LOCK_FREE
-#define	ATOMIC_CHAR32_T_LOCK_FREE	__GCC_ATOMIC_CHAR32_T_LOCK_FREE
-#endif
-#ifdef __GCC_ATOMIC_WCHAR_T_LOCK_FREE
-#define	ATOMIC_WCHAR_T_LOCK_FREE	__GCC_ATOMIC_WCHAR_T_LOCK_FREE
-#endif
-#ifdef __GCC_ATOMIC_SHORT_LOCK_FREE
-#define	ATOMIC_SHORT_LOCK_FREE		__GCC_ATOMIC_SHORT_LOCK_FREE
-#endif
-#ifdef __GCC_ATOMIC_INT_LOCK_FREE
-#define	ATOMIC_INT_LOCK_FREE		__GCC_ATOMIC_INT_LOCK_FREE
-#endif
-#ifdef __GCC_ATOMIC_LONG_LOCK_FREE
-#define	ATOMIC_LONG_LOCK_FREE		__GCC_ATOMIC_LONG_LOCK_FREE
-#endif
-#ifdef __GCC_ATOMIC_LLONG_LOCK_FREE
-#define	ATOMIC_LLONG_LOCK_FREE		__GCC_ATOMIC_LLONG_LOCK_FREE
-#endif
-#ifdef __GCC_ATOMIC_POINTER_LOCK_FREE
-#define	ATOMIC_POINTER_LOCK_FREE	__GCC_ATOMIC_POINTER_LOCK_FREE
-#endif
-
-/*
- * 7.17.2 Initialization.
- */
-
-#if defined(__CLANG_ATOMICS)
-#define	ATOMIC_VAR_INIT(value)		(value)
-#define	atomic_init(obj, value)		__c11_atomic_init(obj, value)
-#else
-#define	ATOMIC_VAR_INIT(value)		{ .__val = (value) }
-#define	atomic_init(obj, value)		((void)((obj)->__val = (value)))
-#endif
-
-/*
- * Clang and recent GCC both provide predefined macros for the memory
- * orderings.  If we are using a compiler that doesn't define them, use the
- * clang values - these will be ignored in the fallback path.
- */
-
-#ifndef __ATOMIC_RELAXED
-#define __ATOMIC_RELAXED		0
-#endif
-#ifndef __ATOMIC_CONSUME
-#define __ATOMIC_CONSUME		1
-#endif
-#ifndef __ATOMIC_ACQUIRE
-#define __ATOMIC_ACQUIRE		2
-#endif
-#ifndef __ATOMIC_RELEASE
-#define __ATOMIC_RELEASE		3
-#endif
-#ifndef __ATOMIC_ACQ_REL
-#define __ATOMIC_ACQ_REL		4
-#endif
-#ifndef __ATOMIC_SEQ_CST
-#define __ATOMIC_SEQ_CST		5
-#endif
-
-/*
- * 7.17.3 Order and consistency.
- *
- * The memory_order_* constants that denote the barrier behaviour of the
- * atomic operations.
- */
-
-typedef enum {
-	memory_order_relaxed = __ATOMIC_RELAXED,
-	memory_order_consume = __ATOMIC_CONSUME,
-	memory_order_acquire = __ATOMIC_ACQUIRE,
-	memory_order_release = __ATOMIC_RELEASE,
-	memory_order_acq_rel = __ATOMIC_ACQ_REL,
-	memory_order_seq_cst = __ATOMIC_SEQ_CST
-} memory_order;
-
-/*
- * 7.17.4 Fences.
- */
-
-static __inline void
-atomic_thread_fence(memory_order __order __unused)
-{
-
-#ifdef __CLANG_ATOMICS
-	__c11_atomic_thread_fence(__order);
-#elif defined(__GNUC_ATOMICS)
-	__atomic_thread_fence(__order);
-#else
-	__sync_synchronize();
-#endif
-}
-
-static __inline void
-atomic_signal_fence(memory_order __order __unused)
-{
-
-#ifdef __CLANG_ATOMICS
-	__c11_atomic_signal_fence(__order);
-#elif defined(__GNUC_ATOMICS)
-	__atomic_signal_fence(__order);
-#else
-	__asm volatile ("" ::: "memory");
-#endif
-}
-
-/*
- * 7.17.5 Lock-free property.
- */
-
-#if defined(_KERNEL)
-/* Atomics in kernelspace are always lock-free. */
-#define	atomic_is_lock_free(obj) \
-	((void)(obj), (_Bool)1)
-#elif defined(__CLANG_ATOMICS)
-#define	atomic_is_lock_free(obj) \
-	__atomic_is_lock_free(sizeof(*(obj)), obj)
-#elif defined(__GNUC_ATOMICS)
-#define	atomic_is_lock_free(obj) \
-	__atomic_is_lock_free(sizeof((obj)->__val), &(obj)->__val)
-#else
-#define	atomic_is_lock_free(obj) \
-	((void)(obj), sizeof((obj)->__val) <= sizeof(void *))
-#endif
-
-/*
- * 7.17.6 Atomic integer types.
- */
-
-typedef _Atomic(_Bool)			atomic_bool;
-typedef _Atomic(char)			atomic_char;
-typedef _Atomic(signed char)		atomic_schar;
-typedef _Atomic(unsigned char)		atomic_uchar;
-typedef _Atomic(short)			atomic_short;
-typedef _Atomic(unsigned short)		atomic_ushort;
-typedef _Atomic(int)			atomic_int;
-typedef _Atomic(unsigned int)		atomic_uint;
-typedef _Atomic(long)			atomic_long;
-typedef _Atomic(unsigned long)		atomic_ulong;
-typedef _Atomic(long long)		atomic_llong;
-typedef _Atomic(unsigned long long)	atomic_ullong;
-#if 0
-typedef _Atomic(__char16_t)		atomic_char16_t;
-typedef _Atomic(__char32_t)		atomic_char32_t;
-#endif
-typedef _Atomic(wchar_t)		atomic_wchar_t;
-typedef _Atomic(int_least8_t)		atomic_int_least8_t;
-typedef _Atomic(uint_least8_t)		atomic_uint_least8_t;
-typedef _Atomic(int_least16_t)		atomic_int_least16_t;
-typedef _Atomic(uint_least16_t)		atomic_uint_least16_t;
-typedef _Atomic(int_least32_t)		atomic_int_least32_t;
-typedef _Atomic(uint_least32_t)		atomic_uint_least32_t;
-typedef _Atomic(int_least64_t)		atomic_int_least64_t;
-typedef _Atomic(uint_least64_t)		atomic_uint_least64_t;
-typedef _Atomic(int_fast8_t)		atomic_int_fast8_t;
-typedef _Atomic(uint_fast8_t)		atomic_uint_fast8_t;
-typedef _Atomic(int_fast16_t)		atomic_int_fast16_t;
-typedef _Atomic(uint_fast16_t)		atomic_uint_fast16_t;
-typedef _Atomic(int_fast32_t)		atomic_int_fast32_t;
-typedef _Atomic(uint_fast32_t)		atomic_uint_fast32_t;
-typedef _Atomic(int_fast64_t)		atomic_int_fast64_t;
-typedef _Atomic(uint_fast64_t)		atomic_uint_fast64_t;
-typedef _Atomic(intptr_t)		atomic_intptr_t;
-typedef _Atomic(uintptr_t)		atomic_uintptr_t;
-typedef _Atomic(size_t)			atomic_size_t;
-typedef _Atomic(ptrdiff_t)		atomic_ptrdiff_t;
-typedef _Atomic(intmax_t)		atomic_intmax_t;
-typedef _Atomic(uintmax_t)		atomic_uintmax_t;
-
-/*
- * 7.17.7 Operations on atomic types.
- */
-
-/*
- * Compiler-specific operations.
- */
-
-#if defined(__CLANG_ATOMICS)
-#define	atomic_compare_exchange_strong_explicit(object, expected,	\
-    desired, success, failure)						\
-	__c11_atomic_compare_exchange_strong(object, expected, desired,	\
-	    success, failure)
-#define	atomic_compare_exchange_weak_explicit(object, expected,		\
-    desired, success, failure)						\
-	__c11_atomic_compare_exchange_weak(object, expected, desired,	\
-	    success, failure)
-#define	atomic_exchange_explicit(object, desired, order)		\
-	__c11_atomic_exchange(object, desired, order)
-#define	atomic_fetch_add_explicit(object, operand, order)		\
-	__c11_atomic_fetch_add(object, operand, order)
-#define	atomic_fetch_and_explicit(object, operand, order)		\
-	__c11_atomic_fetch_and(object, operand, order)
-#define	atomic_fetch_or_explicit(object, operand, order)		\
-	__c11_atomic_fetch_or(object, operand, order)
-#define	atomic_fetch_sub_explicit(object, operand, order)		\
-	__c11_atomic_fetch_sub(object, operand, order)
-#define	atomic_fetch_xor_explicit(object, operand, order)		\
-	__c11_atomic_fetch_xor(object, operand, order)
-#define	atomic_load_explicit(object, order)				\
-	__c11_atomic_load(object, order)
-#define	atomic_store_explicit(object, desired, order)			\
-	__c11_atomic_store(object, desired, order)
-#elif defined(__GNUC_ATOMICS)
-#define	atomic_compare_exchange_strong_explicit(object, expected,	\
-    desired, success, failure)						\
-	__atomic_compare_exchange_n(&(object)->__val, expected,		\
-	    desired, 0, success, failure)
-#define	atomic_compare_exchange_weak_explicit(object, expected,		\
-    desired, success, failure)						\
-	__atomic_compare_exchange_n(&(object)->__val, expected,		\
-	    desired, 1, success, failure)
-#define	atomic_exchange_explicit(object, desired, order)		\
-	__atomic_exchange_n(&(object)->__val, desired, order)
-#define	atomic_fetch_add_explicit(object, operand, order)		\
-	__atomic_fetch_add(&(object)->__val, operand, order)
-#define	atomic_fetch_and_explicit(object, operand, order)		\
-	__atomic_fetch_and(&(object)->__val, operand, order)
-#define	atomic_fetch_or_explicit(object, operand, order)		\
-	__atomic_fetch_or(&(object)->__val, operand, order)
-#define	atomic_fetch_sub_explicit(object, operand, order)		\
-	__atomic_fetch_sub(&(object)->__val, operand, order)
-#define	atomic_fetch_xor_explicit(object, operand, order)		\
-	__atomic_fetch_xor(&(object)->__val, operand, order)
-#define	atomic_load_explicit(object, order)				\
-	__atomic_load_n(&(object)->__val, order)
-#define	atomic_store_explicit(object, desired, order)			\
-	__atomic_store_n(&(object)->__val, desired, order)
-#else
-#define	__atomic_apply_stride(object, operand) \
-	(((__typeof__((object)->__val))0) + (operand))
-#define	atomic_compare_exchange_strong_explicit(object, expected,	\
-    desired, success, failure)	__extension__ ({			\
-	__typeof__(expected) __ep = (expected);				\
-	__typeof__(*__ep) __e = *__ep;					\
-	(void)(success); (void)(failure);				\
-	(_Bool)((*__ep = __sync_val_compare_and_swap(&(object)->__val,	\
-	    __e, desired)) == __e);					\
-})
-#define	atomic_compare_exchange_weak_explicit(object, expected,		\
-    desired, success, failure)						\
-	atomic_compare_exchange_strong_explicit(object, expected,	\
-		desired, success, failure)
-#if __has_builtin(__sync_swap)
-/* Clang provides a full-barrier atomic exchange - use it if available. */
-#define	atomic_exchange_explicit(object, desired, order)		\
-	((void)(order), __sync_swap(&(object)->__val, desired))
-#else
-/*
- * __sync_lock_test_and_set() is only an acquire barrier in theory (although in
- * practice it is usually a full barrier) so we need an explicit barrier before
- * it.
- */
-#define	atomic_exchange_explicit(object, desired, order)		\
-__extension__ ({							\
-	__typeof__(object) __o = (object);				\
-	__typeof__(desired) __d = (desired);				\
-	(void)(order);							\
-	__sync_synchronize();						\
-	__sync_lock_test_and_set(&(__o)->__val, __d);			\
-})
-#endif
-#define	atomic_fetch_add_explicit(object, operand, order)		\
-	((void)(order), __sync_fetch_and_add(&(object)->__val,		\
-	    __atomic_apply_stride(object, operand)))
-#define	atomic_fetch_and_explicit(object, operand, order)		\
-	((void)(order), __sync_fetch_and_and(&(object)->__val, operand))
-#define	atomic_fetch_or_explicit(object, operand, order)		\
-	((void)(order), __sync_fetch_and_or(&(object)->__val, operand))
-#define	atomic_fetch_sub_explicit(object, operand, order)		\
-	((void)(order), __sync_fetch_and_sub(&(object)->__val,		\
-	    __atomic_apply_stride(object, operand)))
-#define	atomic_fetch_xor_explicit(object, operand, order)		\
-	((void)(order), __sync_fetch_and_xor(&(object)->__val, operand))
-#define	atomic_load_explicit(object, order)				\
-	((void)(order), __sync_fetch_and_add(&(object)->__val, 0))
-#define	atomic_store_explicit(object, desired, order)			\
-	((void)atomic_exchange_explicit(object, desired, order))
-#endif
-
-/*
- * Convenience functions.
- *
- * Don't provide these in kernel space. In kernel space, we should be
- * disciplined enough to always provide explicit barriers.
- */
-
-#ifndef _KERNEL
-#define	atomic_compare_exchange_strong(object, expected, desired)	\
-	atomic_compare_exchange_strong_explicit(object, expected,	\
-	    desired, memory_order_seq_cst, memory_order_seq_cst)
-#define	atomic_compare_exchange_weak(object, expected, desired)		\
-	atomic_compare_exchange_weak_explicit(object, expected,		\
-	    desired, memory_order_seq_cst, memory_order_seq_cst)
-#define	atomic_exchange(object, desired)				\
-	atomic_exchange_explicit(object, desired, memory_order_seq_cst)
-#define	atomic_fetch_add(object, operand)				\
-	atomic_fetch_add_explicit(object, operand, memory_order_seq_cst)
-#define	atomic_fetch_and(object, operand)				\
-	atomic_fetch_and_explicit(object, operand, memory_order_seq_cst)
-#define	atomic_fetch_or(object, operand)				\
-	atomic_fetch_or_explicit(object, operand, memory_order_seq_cst)
-#define	atomic_fetch_sub(object, operand)				\
-	atomic_fetch_sub_explicit(object, operand, memory_order_seq_cst)
-#define	atomic_fetch_xor(object, operand)				\
-	atomic_fetch_xor_explicit(object, operand, memory_order_seq_cst)
-#define	atomic_load(object)						\
-	atomic_load_explicit(object, memory_order_seq_cst)
-#define	atomic_store(object, desired)					\
-	atomic_store_explicit(object, desired, memory_order_seq_cst)
-#endif /* !_KERNEL */
-
-/*
- * 7.17.8 Atomic flag type and operations.
- *
- * XXX: Assume atomic_bool can be used as an atomic_flag. Is there some
- * kind of compiler built-in type we could use?
- */
-
-typedef struct {
-	atomic_bool	__flag;
-} atomic_flag;
-
-#define	ATOMIC_FLAG_INIT		{ ATOMIC_VAR_INIT(0) }
-
-static __inline _Bool
-atomic_flag_test_and_set_explicit(volatile atomic_flag *__object,
-    memory_order __order)
-{
-	return (atomic_exchange_explicit(&__object->__flag, 1, __order));
-}
-
-static __inline void
-atomic_flag_clear_explicit(volatile atomic_flag *__object, memory_order __order)
-{
-
-	atomic_store_explicit(&__object->__flag, 0, __order);
-}
-
-#ifndef _KERNEL
-static __inline _Bool
-atomic_flag_test_and_set(volatile atomic_flag *__object)
-{
-
-	return (atomic_flag_test_and_set_explicit(__object,
-	    memory_order_seq_cst));
-}
-
-static __inline void
-atomic_flag_clear(volatile atomic_flag *__object)
-{
-
-	atomic_flag_clear_explicit(__object, memory_order_seq_cst);
-}
-#endif /* !_KERNEL */
-
-#endif /* !_STDATOMIC_H_ */
diff --git a/tools/sdk/include/newlib/stdint.h b/tools/sdk/include/newlib/stdint.h
deleted file mode 100644
index 7386164b9da..00000000000
--- a/tools/sdk/include/newlib/stdint.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/*
- * Copyright (c) 2004, 2005 by
- * Ralf Corsepius, Ulm/Germany. All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software
- * is freely granted, provided that this notice is preserved.
- */
-
-#ifndef _STDINT_H
-#define _STDINT_H
-
-#include <machine/_default_types.h>
-#include <sys/_intsup.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef ___int8_t_defined
-typedef __int8_t int8_t ;
-typedef __uint8_t uint8_t ;
-#define __int8_t_defined 1
-#endif
-
-#ifdef ___int_least8_t_defined
-typedef __int_least8_t int_least8_t;
-typedef __uint_least8_t uint_least8_t;
-#define __int_least8_t_defined 1
-#endif
-
-#ifdef ___int16_t_defined
-typedef __int16_t int16_t ;
-typedef __uint16_t uint16_t ;
-#define __int16_t_defined 1
-#endif
-
-#ifdef ___int_least16_t_defined
-typedef __int_least16_t int_least16_t;
-typedef __uint_least16_t uint_least16_t;
-#define __int_least16_t_defined 1
-#endif
-
-#ifdef ___int32_t_defined
-typedef __int32_t int32_t ;
-typedef __uint32_t uint32_t ;
-#define __int32_t_defined 1
-#endif
-
-#ifdef ___int_least32_t_defined
-typedef __int_least32_t int_least32_t;
-typedef __uint_least32_t uint_least32_t;
-#define __int_least32_t_defined 1
-#endif
-
-#ifdef ___int64_t_defined
-typedef __int64_t int64_t ;
-typedef __uint64_t uint64_t ;
-#define __int64_t_defined 1
-#endif
-
-#ifdef ___int_least64_t_defined
-typedef __int_least64_t int_least64_t;
-typedef __uint_least64_t uint_least64_t;
-#define __int_least64_t_defined 1
-#endif
-
-/*
- * Fastest minimum-width integer types
- *
- * Assume int to be the fastest type for all types with a width 
- * less than __INT_MAX__ rsp. INT_MAX
- */
-#ifdef __INT_FAST8_TYPE__
-  typedef __INT_FAST8_TYPE__ int_fast8_t;
-  typedef __UINT_FAST8_TYPE__ uint_fast8_t;
-#define __int_fast8_t_defined 1
-#elif __STDINT_EXP(INT_MAX) >= 0x7f
-  typedef signed int int_fast8_t;
-  typedef unsigned int uint_fast8_t;
-#define __int_fast8_t_defined 1
-#endif
-
-#ifdef __INT_FAST16_TYPE__
-  typedef __INT_FAST16_TYPE__ int_fast16_t;
-  typedef __UINT_FAST16_TYPE__ uint_fast16_t;
-#define __int_fast16_t_defined 1
-#elif __STDINT_EXP(INT_MAX) >= 0x7fff
-  typedef signed int int_fast16_t;
-  typedef unsigned int uint_fast16_t;
-#define __int_fast16_t_defined 1
-#endif
-
-#ifdef __INT_FAST32_TYPE__
-  typedef __INT_FAST32_TYPE__ int_fast32_t;
-  typedef __UINT_FAST32_TYPE__ uint_fast32_t;
-#define __int_fast32_t_defined 1
-#elif __STDINT_EXP(INT_MAX) >= 0x7fffffff
-  typedef signed int int_fast32_t;
-  typedef unsigned int uint_fast32_t;
-#define __int_fast32_t_defined 1
-#endif
-
-#ifdef __INT_FAST64_TYPE__
-  typedef __INT_FAST64_TYPE__ int_fast64_t;
-  typedef __UINT_FAST64_TYPE__ uint_fast64_t;
-#define __int_fast64_t_defined 1
-#elif __STDINT_EXP(INT_MAX) > 0x7fffffff
-  typedef signed int int_fast64_t;
-  typedef unsigned int uint_fast64_t;
-#define __int_fast64_t_defined 1
-#endif
-
-/*
- * Fall back to [u]int_least<N>_t for [u]int_fast<N>_t types
- * not having been defined, yet.
- * Leave undefined, if [u]int_least<N>_t should not be available.
- */
-#if !__int_fast8_t_defined
-#if __int_least8_t_defined
-  typedef int_least8_t int_fast8_t;
-  typedef uint_least8_t uint_fast8_t;
-#define __int_fast8_t_defined 1
-#endif
-#endif
-
-#if !__int_fast16_t_defined
-#if __int_least16_t_defined
-  typedef int_least16_t int_fast16_t;
-  typedef uint_least16_t uint_fast16_t;
-#define __int_fast16_t_defined 1
-#endif
-#endif
-
-#if !__int_fast32_t_defined
-#if __int_least32_t_defined
-  typedef int_least32_t int_fast32_t;
-  typedef uint_least32_t uint_fast32_t;
-#define __int_fast32_t_defined 1
-#endif
-#endif
-
-#if !__int_fast64_t_defined
-#if __int_least64_t_defined
-  typedef int_least64_t int_fast64_t;
-  typedef uint_least64_t uint_fast64_t;
-#define __int_fast64_t_defined 1
-#endif
-#endif
-
-/* Greatest-width integer types */
-/* Modern GCCs provide __INTMAX_TYPE__ */
-#if defined(__INTMAX_TYPE__)
-  typedef __INTMAX_TYPE__ intmax_t;
-#elif __have_longlong64
-  typedef signed long long intmax_t;
-#else
-  typedef signed long intmax_t;
-#endif
-
-/* Modern GCCs provide __UINTMAX_TYPE__ */
-#if defined(__UINTMAX_TYPE__)
-  typedef __UINTMAX_TYPE__ uintmax_t;
-#elif __have_longlong64
-  typedef unsigned long long uintmax_t;
-#else
-  typedef unsigned long uintmax_t;
-#endif
-
-typedef __intptr_t intptr_t;
-typedef __uintptr_t uintptr_t;
-
-#ifdef __INTPTR_TYPE__
-#define INTPTR_MIN (-__INTPTR_MAX__ - 1)
-#define INTPTR_MAX __INTPTR_MAX__
-#define UINTPTR_MAX __UINTPTR_MAX__
-#elif defined(__PTRDIFF_TYPE__)
-#define INTPTR_MAX PTRDIFF_MAX
-#define INTPTR_MIN PTRDIFF_MIN
-#ifdef __UINTPTR_MAX__
-#define UINTPTR_MAX __UINTPTR_MAX__
-#else
-#define UINTPTR_MAX (2UL * PTRDIFF_MAX + 1)
-#endif
-#else
-/*
- * Fallback to hardcoded values, 
- * should be valid on cpu's with 32bit int/32bit void*
- */
-#define INTPTR_MAX __STDINT_EXP(LONG_MAX)
-#define INTPTR_MIN (-__STDINT_EXP(LONG_MAX) - 1)
-#define UINTPTR_MAX (__STDINT_EXP(LONG_MAX) * 2UL + 1)
-#endif
-
-/* Limits of Specified-Width Integer Types */
-
-#ifdef __INT8_MAX__
-#define INT8_MIN (-__INT8_MAX__ - 1)
-#define INT8_MAX __INT8_MAX__
-#define UINT8_MAX __UINT8_MAX__
-#elif defined(__int8_t_defined)
-#define INT8_MIN 	-128
-#define INT8_MAX 	 127
-#define UINT8_MAX 	 255
-#endif
-
-#ifdef __INT_LEAST8_MAX__
-#define INT_LEAST8_MIN (-__INT_LEAST8_MAX__ - 1)
-#define INT_LEAST8_MAX __INT_LEAST8_MAX__
-#define UINT_LEAST8_MAX __UINT_LEAST8_MAX__
-#elif defined(__int_least8_t_defined)
-#define INT_LEAST8_MIN 	-128
-#define INT_LEAST8_MAX 	 127
-#define UINT_LEAST8_MAX	 255
-#else
-#error required type int_least8_t missing
-#endif
-
-#ifdef __INT16_MAX__
-#define INT16_MIN (-__INT16_MAX__ - 1)
-#define INT16_MAX __INT16_MAX__
-#define UINT16_MAX __UINT16_MAX__
-#elif defined(__int16_t_defined)
-#define INT16_MIN 	-32768
-#define INT16_MAX 	 32767
-#define UINT16_MAX 	 65535
-#endif
-
-#ifdef __INT_LEAST16_MAX__
-#define INT_LEAST16_MIN (-__INT_LEAST16_MAX__ - 1)
-#define INT_LEAST16_MAX __INT_LEAST16_MAX__
-#define UINT_LEAST16_MAX __UINT_LEAST16_MAX__
-#elif defined(__int_least16_t_defined)
-#define INT_LEAST16_MIN	-32768
-#define INT_LEAST16_MAX	 32767
-#define UINT_LEAST16_MAX 65535
-#else
-#error required type int_least16_t missing
-#endif
-
-#ifdef __INT32_MAX__
-#define INT32_MIN (-__INT32_MAX__ - 1)
-#define INT32_MAX __INT32_MAX__
-#define UINT32_MAX __UINT32_MAX__
-#elif defined(__int32_t_defined)
-#if __have_long32
-#define INT32_MIN 	 (-2147483647L-1)
-#define INT32_MAX 	 2147483647L
-#define UINT32_MAX       4294967295UL
-#else
-#define INT32_MIN 	 (-2147483647-1)
-#define INT32_MAX 	 2147483647
-#define UINT32_MAX       4294967295U
-#endif
-#endif
-
-#ifdef __INT_LEAST32_MAX__
-#define INT_LEAST32_MIN (-__INT_LEAST32_MAX__ - 1)
-#define INT_LEAST32_MAX __INT_LEAST32_MAX__
-#define UINT_LEAST32_MAX __UINT_LEAST32_MAX__
-#elif defined(__int_least32_t_defined)
-#if __have_long32
-#define INT_LEAST32_MIN  (-2147483647L-1)
-#define INT_LEAST32_MAX  2147483647L
-#define UINT_LEAST32_MAX 4294967295UL
-#else
-#define INT_LEAST32_MIN  (-2147483647-1)
-#define INT_LEAST32_MAX  2147483647
-#define UINT_LEAST32_MAX 4294967295U
-#endif
-#else
-#error required type int_least32_t missing
-#endif
-
-#ifdef __INT64_MAX__
-#define INT64_MIN (-__INT64_MAX__ - 1)
-#define INT64_MAX __INT64_MAX__
-#define UINT64_MAX __UINT64_MAX__
-#elif defined(__int64_t_defined)
-#if __have_long64
-#define INT64_MIN 	(-9223372036854775807L-1L)
-#define INT64_MAX 	 9223372036854775807L
-#define UINT64_MAX 	18446744073709551615U
-#elif __have_longlong64
-#define INT64_MIN 	(-9223372036854775807LL-1LL)
-#define INT64_MAX 	 9223372036854775807LL
-#define UINT64_MAX 	18446744073709551615ULL
-#endif
-#endif
-
-#ifdef __INT_LEAST64_MAX__
-#define INT_LEAST64_MIN (-__INT_LEAST64_MAX__ - 1)
-#define INT_LEAST64_MAX __INT_LEAST64_MAX__
-#define UINT_LEAST64_MAX __UINT_LEAST64_MAX__
-#elif defined(__int_least64_t_defined)
-#if __have_long64
-#define INT_LEAST64_MIN  (-9223372036854775807L-1L)
-#define INT_LEAST64_MAX  9223372036854775807L
-#define UINT_LEAST64_MAX 18446744073709551615U
-#elif __have_longlong64
-#define INT_LEAST64_MIN  (-9223372036854775807LL-1LL)
-#define INT_LEAST64_MAX  9223372036854775807LL
-#define UINT_LEAST64_MAX 18446744073709551615ULL
-#endif
-#endif
-
-#ifdef __INT_FAST8_MAX__
-#define INT_FAST8_MIN (-__INT_FAST8_MAX__ - 1)
-#define INT_FAST8_MAX __INT_FAST8_MAX__
-#define UINT_FAST8_MAX __UINT_FAST8_MAX__
-#elif defined(__int_fast8_t_defined)
-#if __STDINT_EXP(INT_MAX) >= 0x7f
-#define INT_FAST8_MIN	(-__STDINT_EXP(INT_MAX)-1)
-#define INT_FAST8_MAX	__STDINT_EXP(INT_MAX)
-#define UINT_FAST8_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
-#else
-#define INT_FAST8_MIN	INT_LEAST8_MIN
-#define INT_FAST8_MAX	INT_LEAST8_MAX
-#define UINT_FAST8_MAX	UINT_LEAST8_MAX
-#endif
-#endif
-
-#ifdef __INT_FAST16_MAX__
-#define INT_FAST16_MIN (-__INT_FAST16_MAX__ - 1)
-#define INT_FAST16_MAX __INT_FAST16_MAX__
-#define UINT_FAST16_MAX __UINT_FAST16_MAX__
-#elif defined(__int_fast16_t_defined)
-#if __STDINT_EXP(INT_MAX) >= 0x7fff
-#define INT_FAST16_MIN	(-__STDINT_EXP(INT_MAX)-1)
-#define INT_FAST16_MAX	__STDINT_EXP(INT_MAX)
-#define UINT_FAST16_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
-#else
-#define INT_FAST16_MIN	INT_LEAST16_MIN
-#define INT_FAST16_MAX	INT_LEAST16_MAX
-#define UINT_FAST16_MAX	UINT_LEAST16_MAX
-#endif
-#endif
-
-#ifdef __INT_FAST32_MAX__
-#define INT_FAST32_MIN (-__INT_FAST32_MAX__ - 1)
-#define INT_FAST32_MAX __INT_FAST32_MAX__
-#define UINT_FAST32_MAX __UINT_FAST32_MAX__
-#elif defined(__int_fast32_t_defined)
-#if __STDINT_EXP(INT_MAX) >= 0x7fffffff
-#define INT_FAST32_MIN	(-__STDINT_EXP(INT_MAX)-1)
-#define INT_FAST32_MAX	__STDINT_EXP(INT_MAX)
-#define UINT_FAST32_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
-#else
-#define INT_FAST32_MIN	INT_LEAST32_MIN
-#define INT_FAST32_MAX	INT_LEAST32_MAX
-#define UINT_FAST32_MAX	UINT_LEAST32_MAX
-#endif
-#endif
-
-#ifdef __INT_FAST64_MAX__
-#define INT_FAST64_MIN (-__INT_FAST64_MAX__ - 1)
-#define INT_FAST64_MAX __INT_FAST64_MAX__
-#define UINT_FAST64_MAX __UINT_FAST64_MAX__
-#elif defined(__int_fast64_t_defined)
-#if __STDINT_EXP(INT_MAX) > 0x7fffffff
-#define INT_FAST64_MIN	(-__STDINT_EXP(INT_MAX)-1)
-#define INT_FAST64_MAX	__STDINT_EXP(INT_MAX)
-#define UINT_FAST64_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
-#else
-#define INT_FAST64_MIN	INT_LEAST64_MIN
-#define INT_FAST64_MAX	INT_LEAST64_MAX
-#define UINT_FAST64_MAX	UINT_LEAST64_MAX
-#endif
-#endif
-
-#ifdef __INTMAX_MAX__
-#define INTMAX_MAX __INTMAX_MAX__
-#define INTMAX_MIN (-INTMAX_MAX - 1)
-#elif defined(__INTMAX_TYPE__)
-/* All relevant GCC versions prefer long to long long for intmax_t.  */
-#define INTMAX_MAX INT64_MAX
-#define INTMAX_MIN INT64_MIN
-#endif
-
-#ifdef __UINTMAX_MAX__
-#define UINTMAX_MAX __UINTMAX_MAX__
-#elif defined(__UINTMAX_TYPE__)
-/* All relevant GCC versions prefer long to long long for intmax_t.  */
-#define UINTMAX_MAX UINT64_MAX
-#endif
-
-/* This must match size_t in stddef.h, currently long unsigned int */
-#ifdef __SIZE_MAX__
-#define SIZE_MAX __SIZE_MAX__
-#else
-#define SIZE_MAX (__STDINT_EXP(LONG_MAX) * 2UL + 1)
-#endif
-
-/* This must match sig_atomic_t in <signal.h> (currently int) */
-#define SIG_ATOMIC_MIN (-__STDINT_EXP(INT_MAX) - 1)
-#define SIG_ATOMIC_MAX __STDINT_EXP(INT_MAX)
-
-/* This must match ptrdiff_t  in <stddef.h> (currently long int) */
-#ifdef __PTRDIFF_MAX__
-#define PTRDIFF_MAX __PTRDIFF_MAX__
-#else
-#define PTRDIFF_MAX __STDINT_EXP(LONG_MAX)
-#endif
-#define PTRDIFF_MIN (-PTRDIFF_MAX - 1)
-
-/* This must match definition in <wchar.h> */
-#ifndef WCHAR_MIN
-#ifdef __WCHAR_MIN__
-#define WCHAR_MIN __WCHAR_MIN__
-#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
-#define WCHAR_MIN (0 + L'\0')
-#else
-#define WCHAR_MIN (-0x7fffffff - 1 + L'\0')
-#endif
-#endif
-
-/* This must match definition in <wchar.h> */
-#ifndef WCHAR_MAX
-#ifdef __WCHAR_MAX__
-#define WCHAR_MAX __WCHAR_MAX__
-#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
-#define WCHAR_MAX (0xffffffffu + L'\0')
-#else
-#define WCHAR_MAX (0x7fffffff + L'\0')
-#endif
-#endif
-
-/* wint_t is unsigned int on almost all GCC targets.  */
-#ifdef __WINT_MAX__
-#define WINT_MAX __WINT_MAX__
-#else
-#define WINT_MAX (__STDINT_EXP(INT_MAX) * 2U + 1U)
-#endif
-#ifdef __WINT_MIN__
-#define WINT_MIN __WINT_MIN__
-#else
-#define WINT_MIN 0U
-#endif
-
-/** Macros for minimum-width integer constant expressions */
-#ifdef __INT8_C
-#define INT8_C(x) __INT8_C(x)
-#define UINT8_C(x) __UINT8_C(x)
-#else
-#define INT8_C(x)	x
-#if __STDINT_EXP(INT_MAX) > 0x7f
-#define UINT8_C(x)	x
-#else
-#define UINT8_C(x)	x##U
-#endif
-#endif
-
-#ifdef __INT16_C
-#define INT16_C(x) __INT16_C(x)
-#define UINT16_C(x) __UINT16_C(x)
-#else
-#define INT16_C(x)	x
-#if __STDINT_EXP(INT_MAX) > 0x7fff
-#define UINT16_C(x)	x
-#else
-#define UINT16_C(x)	x##U
-#endif
-#endif
-
-#ifdef __INT32_C
-#define INT32_C(x) __INT32_C(x)
-#define UINT32_C(x) __UINT32_C(x)
-#else
-#if __have_long32
-#define INT32_C(x)	x##L
-#define UINT32_C(x)	x##UL
-#else
-#define INT32_C(x)	x
-#define UINT32_C(x)	x##U
-#endif
-#endif
-
-#ifdef __INT64_C
-#define INT64_C(x) __INT64_C(x)
-#define UINT64_C(x) __UINT64_C(x)
-#else
-#if __int64_t_defined
-#if __have_long64
-#define INT64_C(x)	x##L
-#define UINT64_C(x)	x##UL
-#else
-#define INT64_C(x)	x##LL
-#define UINT64_C(x)	x##ULL
-#endif
-#endif
-#endif
-
-/** Macros for greatest-width integer constant expression */
-#ifdef __INTMAX_C
-#define INTMAX_C(x) __INTMAX_C(x)
-#define UINTMAX_C(x) __UINTMAX_C(x)
-#else
-#if __have_long64
-#define INTMAX_C(x)	x##L
-#define UINTMAX_C(x)	x##UL
-#else
-#define INTMAX_C(x)	x##LL
-#define UINTMAX_C(x)	x##ULL
-#endif
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STDINT_H */
diff --git a/tools/sdk/include/newlib/stdio.h b/tools/sdk/include/newlib/stdio.h
deleted file mode 100644
index 0836ab5637d..00000000000
--- a/tools/sdk/include/newlib/stdio.h
+++ /dev/null
@@ -1,731 +0,0 @@
-/*
- * Copyright (c) 1990 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms are permitted
- * provided that the above copyright notice and this paragraph are
- * duplicated in all such forms and that any documentation,
- * advertising materials, and other materials related to such
- * distribution and use acknowledge that the software was developed
- * by the University of California, Berkeley.  The name of the
- * University may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- *
- *	@(#)stdio.h	5.3 (Berkeley) 3/15/86
- */
-
-/*
- * NB: to fit things in six character monocase externals, the
- * stdio code uses the prefix `__s' for stdio objects, typically
- * followed by a three-character attempt at a mnemonic.
- */
-
-#ifndef _STDIO_H_
-#define	_STDIO_H_
-
-#include "_ansi.h"
-
-#define	_FSTDIO			/* ``function stdio'' */
-
-#define __need_size_t
-#define __need_NULL
-#include <sys/cdefs.h>
-#include <stddef.h>
-
-#define __need___va_list
-#include <stdarg.h>
-
-/*
- * <sys/reent.h> defines __FILE, _fpos_t.
- * They must be defined there because struct _reent needs them (and we don't
- * want reent.h to include this file.
- */
-
-#include <sys/reent.h>
-#include <sys/types.h>
-
-_BEGIN_STD_C
-
-typedef __FILE FILE;
-
-#ifdef __CYGWIN__
-typedef _fpos64_t fpos_t;
-#else
-typedef _fpos_t fpos_t;
-#ifdef __LARGE64_FILES
-typedef _fpos64_t fpos64_t;
-#endif
-#endif /* !__CYGWIN__ */
-
-#include <sys/stdio.h>
-
-#define	__SLBF	0x0001		/* line buffered */
-#define	__SNBF	0x0002		/* unbuffered */
-#define	__SRD	0x0004		/* OK to read */
-#define	__SWR	0x0008		/* OK to write */
-	/* RD and WR are never simultaneously asserted */
-#define	__SRW	0x0010		/* open for reading & writing */
-#define	__SEOF	0x0020		/* found EOF */
-#define	__SERR	0x0040		/* found error */
-#define	__SMBF	0x0080		/* _buf is from malloc */
-#define	__SAPP	0x0100		/* fdopen()ed in append mode - so must  write to end */
-#define	__SSTR	0x0200		/* this is an sprintf/snprintf string */
-#define	__SOPT	0x0400		/* do fseek() optimisation */
-#define	__SNPT	0x0800		/* do not do fseek() optimisation */
-#define	__SOFF	0x1000		/* set iff _offset is in fact correct */
-#define	__SORD	0x2000		/* true => stream orientation (byte/wide) decided */
-#if defined(__CYGWIN__)
-#  define __SCLE  0x4000        /* convert line endings CR/LF <-> NL */
-#endif
-#define	__SL64	0x8000		/* is 64-bit offset large file */
-
-/* _flags2 flags */
-#define	__SNLK  0x0001		/* stdio functions do not lock streams themselves */
-#define	__SWID	0x2000		/* true => stream orientation wide, false => byte, only valid if __SORD in _flags is true */
-
-/*
- * The following three definitions are for ANSI C, which took them
- * from System V, which stupidly took internal interface macros and
- * made them official arguments to setvbuf(), without renaming them.
- * Hence, these ugly _IOxxx names are *supposed* to appear in user code.
- *
- * Although these happen to match their counterparts above, the
- * implementation does not rely on that (so these could be renumbered).
- */
-#define	_IOFBF	0		/* setvbuf should set fully buffered */
-#define	_IOLBF	1		/* setvbuf should set line buffered */
-#define	_IONBF	2		/* setvbuf should set unbuffered */
-
-#define	EOF	(-1)
-
-#ifdef __BUFSIZ__
-#define	BUFSIZ		__BUFSIZ__
-#else
-#define	BUFSIZ		1024
-#endif
-
-#ifdef __FOPEN_MAX__
-#define FOPEN_MAX	__FOPEN_MAX__
-#else
-#define	FOPEN_MAX	20
-#endif
-
-#ifdef __FILENAME_MAX__
-#define FILENAME_MAX    __FILENAME_MAX__
-#else
-#define	FILENAME_MAX	1024
-#endif
-
-#ifdef __L_tmpnam__
-#define L_tmpnam	__L_tmpnam__
-#else
-#define	L_tmpnam	FILENAME_MAX
-#endif
-
-#ifndef __STRICT_ANSI__
-#define P_tmpdir        "/tmp"
-#endif
-
-#ifndef SEEK_SET
-#define	SEEK_SET	0	/* set file offset to offset */
-#endif
-#ifndef SEEK_CUR
-#define	SEEK_CUR	1	/* set file offset to current plus offset */
-#endif
-#ifndef SEEK_END
-#define	SEEK_END	2	/* set file offset to EOF plus offset */
-#endif
-
-#define	TMP_MAX		26
-
-#define	stdin	(_REENT->_stdin)
-#define	stdout	(_REENT->_stdout)
-#define	stderr	(_REENT->_stderr)
-
-#define _stdin_r(x)	((x)->_stdin)
-#define _stdout_r(x)	((x)->_stdout)
-#define _stderr_r(x)	((x)->_stderr)
-
-/*
- * Functions defined in ANSI C standard.
- */
-
-#ifndef __VALIST
-#ifdef __GNUC__
-#define __VALIST __gnuc_va_list
-#else
-#define __VALIST char*
-#endif
-#endif
-
-FILE *	_EXFUN(tmpfile, (void));
-char *	_EXFUN(tmpnam, (char *));
-#if __BSD_VISIBLE || __XSI_VISIBLE || __POSIX_VISIBLE >= 200112
-char *	_EXFUN(tempnam, (const char *, const char *));
-#endif
-int	_EXFUN(fclose, (FILE *));
-int	_EXFUN(fflush, (FILE *));
-FILE *	_EXFUN(freopen, (const char *__restrict, const char *__restrict, FILE *__restrict));
-void	_EXFUN(setbuf, (FILE *__restrict, char *__restrict));
-int	_EXFUN(setvbuf, (FILE *__restrict, char *__restrict, int, size_t));
-int	_EXFUN(fprintf, (FILE *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-int	_EXFUN(fscanf, (FILE *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
-int	_EXFUN(printf, (const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 1, 2))));
-int	_EXFUN(scanf, (const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 1, 2))));
-int	_EXFUN(sscanf, (const char *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
-int	_EXFUN(vfprintf, (FILE *__restrict, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-int	_EXFUN(vprintf, (const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 1, 0))));
-int	_EXFUN(vsprintf, (char *__restrict, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-int	_EXFUN(fgetc, (FILE *));
-char *  _EXFUN(fgets, (char *__restrict, int, FILE *__restrict));
-int	_EXFUN(fputc, (int, FILE *));
-int	_EXFUN(fputs, (const char *__restrict, FILE *__restrict));
-int	_EXFUN(getc, (FILE *));
-int	_EXFUN(getchar, (void));
-char *  _EXFUN(gets, (char *));
-int	_EXFUN(putc, (int, FILE *));
-int	_EXFUN(putchar, (int));
-int	_EXFUN(puts, (const char *));
-int	_EXFUN(ungetc, (int, FILE *));
-size_t	_EXFUN(fread, (_PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
-size_t	_EXFUN(fwrite, (const _PTR __restrict , size_t _size, size_t _n, FILE *));
-#ifdef _COMPILING_NEWLIB
-int	_EXFUN(fgetpos, (FILE *, _fpos_t *));
-#else
-int	_EXFUN(fgetpos, (FILE *__restrict, fpos_t *__restrict));
-#endif
-int	_EXFUN(fseek, (FILE *, long, int));
-#ifdef _COMPILING_NEWLIB
-int	_EXFUN(fsetpos, (FILE *, const _fpos_t *));
-#else
-int	_EXFUN(fsetpos, (FILE *, const fpos_t *));
-#endif
-long	_EXFUN(ftell, ( FILE *));
-void	_EXFUN(rewind, (FILE *));
-void	_EXFUN(clearerr, (FILE *));
-int	_EXFUN(feof, (FILE *));
-int	_EXFUN(ferror, (FILE *));
-void    _EXFUN(perror, (const char *));
-#ifndef _REENT_ONLY
-FILE *	_EXFUN(fopen, (const char *__restrict _name, const char *__restrict _type));
-int	_EXFUN(sprintf, (char *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-int	_EXFUN(remove, (const char *));
-int	_EXFUN(rename, (const char *, const char *));
-#ifdef _COMPILING_NEWLIB
-int	_EXFUN(_rename, (const char *, const char *));
-#endif
-#endif
-#if !defined(__STRICT_ANSI__) || defined(__USE_XOPEN2K)
-#ifdef _COMPILING_NEWLIB
-int	_EXFUN(fseeko, (FILE *, _off_t, int));
-_off_t	_EXFUN(ftello, ( FILE *));
-#else
-int	_EXFUN(fseeko, (FILE *, off_t, int));
-off_t	_EXFUN(ftello, ( FILE *));
-#endif
-#endif
-#if __GNU_VISIBLE
-int	_EXFUN(fcloseall, (_VOID));
-#endif
-#if !defined(__STRICT_ANSI__) || (__STDC_VERSION__ >= 199901L) || (__cplusplus >= 201103L)
-#ifndef _REENT_ONLY
-int	_EXFUN(asiprintf, (char **, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-char *	_EXFUN(asniprintf, (char *, size_t *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-char *	_EXFUN(asnprintf, (char *__restrict, size_t *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(asprintf, (char **__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-#ifndef diprintf
-int	_EXFUN(diprintf, (int, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-#endif
-int	_EXFUN(fiprintf, (FILE *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-int	_EXFUN(fiscanf, (FILE *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
-int	_EXFUN(iprintf, (const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 1, 2))));
-int	_EXFUN(iscanf, (const char *, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 1, 2))));
-int	_EXFUN(siprintf, (char *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-int	_EXFUN(siscanf, (const char *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
-int	_EXFUN(snprintf, (char *__restrict, size_t, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(sniprintf, (char *, size_t, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(vasiprintf, (char **, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-char *	_EXFUN(vasniprintf, (char *, size_t *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-char *	_EXFUN(vasnprintf, (char *, size_t *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(vasprintf, (char **, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-int	_EXFUN(vdiprintf, (int, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-int	_EXFUN(vfiprintf, (FILE *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-int	_EXFUN(vfiscanf, (FILE *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
-int	_EXFUN(vfscanf, (FILE *__restrict, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
-int	_EXFUN(viprintf, (const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 1, 0))));
-int	_EXFUN(viscanf, (const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 1, 0))));
-int	_EXFUN(vscanf, (const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 1, 0))));
-int	_EXFUN(vsiprintf, (char *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-int	_EXFUN(vsiscanf, (const char *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
-int	_EXFUN(vsniprintf, (char *, size_t, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(vsnprintf, (char *__restrict, size_t, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(vsscanf, (const char *__restrict, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
-#endif /* !_REENT_ONLY */
-#endif /* !__STRICT_ANSI__ */
-
-/*
- * Routines in POSIX 1003.1:2001.
- */
-
-#ifndef __STRICT_ANSI__
-#ifndef _REENT_ONLY
-FILE *	_EXFUN(fdopen, (int, const char *));
-#endif
-int	_EXFUN(fileno, (FILE *));
-int	_EXFUN(getw, (FILE *));
-int	_EXFUN(pclose, (FILE *));
-FILE *  _EXFUN(popen, (const char *, const char *));
-int	_EXFUN(putw, (int, FILE *));
-void    _EXFUN(setbuffer, (FILE *, char *, int));
-int	_EXFUN(setlinebuf, (FILE *));
-int	_EXFUN(getc_unlocked, (FILE *));
-int	_EXFUN(getchar_unlocked, (void));
-void	_EXFUN(flockfile, (FILE *));
-int	_EXFUN(ftrylockfile, (FILE *));
-void	_EXFUN(funlockfile, (FILE *));
-int	_EXFUN(putc_unlocked, (int, FILE *));
-int	_EXFUN(putchar_unlocked, (int));
-#endif /* ! __STRICT_ANSI__ */
-
-/*
- * Routines in POSIX 1003.1:200x.
- */
-
-#ifndef __STRICT_ANSI__
-# ifndef _REENT_ONLY
-#  ifndef dprintf
-int	_EXFUN(dprintf, (int, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-#  endif
-FILE *	_EXFUN(fmemopen, (void *__restrict, size_t, const char *__restrict));
-/* getdelim - see __getdelim for now */
-/* getline - see __getline for now */
-FILE *	_EXFUN(open_memstream, (char **, size_t *));
-#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200809
-int	_EXFUN(renameat, (int, const char *, int, const char *));
-#endif
-int	_EXFUN(vdprintf, (int, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-# endif
-#endif
-
-/*
- * Recursive versions of the above.
- */
-
-int	_EXFUN(_asiprintf_r, (struct _reent *, char **, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-char *	_EXFUN(_asniprintf_r, (struct _reent *, char *, size_t *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 4, 5))));
-char *	_EXFUN(_asnprintf_r, (struct _reent *, char *__restrict, size_t *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 4, 5))));
-int	_EXFUN(_asprintf_r, (struct _reent *, char **__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(_diprintf_r, (struct _reent *, int, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(_dprintf_r, (struct _reent *, int, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(_fclose_r, (struct _reent *, FILE *));
-int	_EXFUN(_fcloseall_r, (struct _reent *));
-FILE *	_EXFUN(_fdopen_r, (struct _reent *, int, const char *));
-int	_EXFUN(_fflush_r, (struct _reent *, FILE *));
-int	_EXFUN(_fgetc_r, (struct _reent *, FILE *));
-int	_EXFUN(_fgetc_unlocked_r, (struct _reent *, FILE *));
-char *  _EXFUN(_fgets_r, (struct _reent *, char *__restrict, int, FILE *__restrict));
-char *  _EXFUN(_fgets_unlocked_r, (struct _reent *, char *__restrict, int, FILE *__restrict));
-#ifdef _COMPILING_NEWLIB
-int	_EXFUN(_fgetpos_r, (struct _reent *, FILE *__restrict, _fpos_t *__restrict));
-int	_EXFUN(_fsetpos_r, (struct _reent *, FILE *, const _fpos_t *));
-#else
-int	_EXFUN(_fgetpos_r, (struct _reent *, FILE *, fpos_t *));
-int	_EXFUN(_fsetpos_r, (struct _reent *, FILE *, const fpos_t *));
-#endif
-int	_EXFUN(_fiprintf_r, (struct _reent *, FILE *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(_fiscanf_r, (struct _reent *, FILE *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 3, 4))));
-FILE *	_EXFUN(_fmemopen_r, (struct _reent *, void *__restrict, size_t, const char *__restrict));
-FILE *	_EXFUN(_fopen_r, (struct _reent *, const char *__restrict, const char *__restrict));
-FILE *	_EXFUN(_freopen_r, (struct _reent *, const char *__restrict, const char *__restrict, FILE *__restrict));
-int	_EXFUN(_fprintf_r, (struct _reent *, FILE *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(_fpurge_r, (struct _reent *, FILE *));
-int	_EXFUN(_fputc_r, (struct _reent *, int, FILE *));
-int	_EXFUN(_fputc_unlocked_r, (struct _reent *, int, FILE *));
-int	_EXFUN(_fputs_r, (struct _reent *, const char *__restrict, FILE *__restrict));
-int	_EXFUN(_fputs_unlocked_r, (struct _reent *, const char *__restrict, FILE *__restrict));
-size_t	_EXFUN(_fread_r, (struct _reent *, _PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
-size_t	_EXFUN(_fread_unlocked_r, (struct _reent *, _PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
-int	_EXFUN(_fscanf_r, (struct _reent *, FILE *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 3, 4))));
-int	_EXFUN(_fseek_r, (struct _reent *, FILE *, long, int));
-int	_EXFUN(_fseeko_r,(struct _reent *, FILE *, _off_t, int));
-long	_EXFUN(_ftell_r, (struct _reent *, FILE *));
-_off_t	_EXFUN(_ftello_r,(struct _reent *, FILE *));
-void	_EXFUN(_rewind_r, (struct _reent *, FILE *));
-size_t	_EXFUN(_fwrite_r, (struct _reent *, const _PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
-size_t	_EXFUN(_fwrite_unlocked_r, (struct _reent *, const _PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
-int	_EXFUN(_getc_r, (struct _reent *, FILE *));
-int	_EXFUN(_getc_unlocked_r, (struct _reent *, FILE *));
-int	_EXFUN(_getchar_r, (struct _reent *));
-int	_EXFUN(_getchar_unlocked_r, (struct _reent *));
-char *	_EXFUN(_gets_r, (struct _reent *, char *));
-int	_EXFUN(_iprintf_r, (struct _reent *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-int	_EXFUN(_iscanf_r, (struct _reent *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
-FILE *	_EXFUN(_open_memstream_r, (struct _reent *, char **, size_t *));
-void	_EXFUN(_perror_r, (struct _reent *, const char *));
-int	_EXFUN(_printf_r, (struct _reent *, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 3))));
-int	_EXFUN(_putc_r, (struct _reent *, int, FILE *));
-int	_EXFUN(_putc_unlocked_r, (struct _reent *, int, FILE *));
-int	_EXFUN(_putchar_unlocked_r, (struct _reent *, int));
-int	_EXFUN(_putchar_r, (struct _reent *, int));
-int	_EXFUN(_puts_r, (struct _reent *, const char *));
-int	_EXFUN(_remove_r, (struct _reent *, const char *));
-int	_EXFUN(_rename_r, (struct _reent *,
-			   const char *_old, const char *_new));
-int	_EXFUN(_scanf_r, (struct _reent *, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 3))));
-int	_EXFUN(_siprintf_r, (struct _reent *, char *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(_siscanf_r, (struct _reent *, const char *, const char *, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 3, 4))));
-int	_EXFUN(_sniprintf_r, (struct _reent *, char *, size_t, const char *, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 4, 5))));
-int	_EXFUN(_snprintf_r, (struct _reent *, char *__restrict, size_t, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 4, 5))));
-int	_EXFUN(_sprintf_r, (struct _reent *, char *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 4))));
-int	_EXFUN(_sscanf_r, (struct _reent *, const char *__restrict, const char *__restrict, ...)
-               _ATTRIBUTE ((__format__ (__scanf__, 3, 4))));
-char *	_EXFUN(_tempnam_r, (struct _reent *, const char *, const char *));
-FILE *	_EXFUN(_tmpfile_r, (struct _reent *));
-char *	_EXFUN(_tmpnam_r, (struct _reent *, char *));
-int	_EXFUN(_ungetc_r, (struct _reent *, int, FILE *));
-int	_EXFUN(_vasiprintf_r, (struct _reent *, char **, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-char *	_EXFUN(_vasniprintf_r, (struct _reent*, char *, size_t *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 4, 0))));
-char *	_EXFUN(_vasnprintf_r, (struct _reent*, char *, size_t *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 4, 0))));
-int	_EXFUN(_vasprintf_r, (struct _reent *, char **, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(_vdiprintf_r, (struct _reent *, int, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(_vdprintf_r, (struct _reent *, int, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(_vfiprintf_r, (struct _reent *, FILE *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(_vfiscanf_r, (struct _reent *, FILE *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 3, 0))));
-int	_EXFUN(_vfprintf_r, (struct _reent *, FILE *__restrict, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(_vfscanf_r, (struct _reent *, FILE *__restrict, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 3, 0))));
-int	_EXFUN(_viprintf_r, (struct _reent *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-int	_EXFUN(_viscanf_r, (struct _reent *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
-int	_EXFUN(_vprintf_r, (struct _reent *, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 2, 0))));
-int	_EXFUN(_vscanf_r, (struct _reent *, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 2, 0))));
-int	_EXFUN(_vsiprintf_r, (struct _reent *, char *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(_vsiscanf_r, (struct _reent *, const char *, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 3, 0))));
-int	_EXFUN(_vsniprintf_r, (struct _reent *, char *, size_t, const char *, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 4, 0))));
-int	_EXFUN(_vsnprintf_r, (struct _reent *, char *__restrict, size_t, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 4, 0))));
-int	_EXFUN(_vsprintf_r, (struct _reent *, char *__restrict, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__printf__, 3, 0))));
-int	_EXFUN(_vsscanf_r, (struct _reent *, const char *__restrict, const char *__restrict, __VALIST)
-               _ATTRIBUTE ((__format__ (__scanf__, 3, 0))));
-
-/* Other extensions.  */
-
-int	_EXFUN(fpurge, (FILE *));
-ssize_t _EXFUN(__getdelim, (char **, size_t *, int, FILE *));
-ssize_t _EXFUN(__getline, (char **, size_t *, FILE *));
-
-#if __BSD_VISIBLE
-void	_EXFUN(clearerr_unlocked, (FILE *));
-int	_EXFUN(feof_unlocked, (FILE *));
-int	_EXFUN(ferror_unlocked, (FILE *));
-int	_EXFUN(fileno_unlocked, (FILE *));
-int	_EXFUN(fflush_unlocked, (FILE *));
-int	_EXFUN(fgetc_unlocked, (FILE *));
-int	_EXFUN(fputc_unlocked, (int, FILE *));
-size_t	_EXFUN(fread_unlocked, (_PTR __restrict, size_t _size, size_t _n, FILE *__restrict));
-size_t	_EXFUN(fwrite_unlocked, (const _PTR __restrict , size_t _size, size_t _n, FILE *));
-#endif
-
-#if __GNU_VISIBLE
-char *  _EXFUN(fgets_unlocked, (char *__restrict, int, FILE *__restrict));
-int	_EXFUN(fputs_unlocked, (const char *__restrict, FILE *__restrict));
-#endif
-
-#ifdef __LARGE64_FILES
-#if !defined(__CYGWIN__) || defined(_COMPILING_NEWLIB)
-FILE *	_EXFUN(fdopen64, (int, const char *));
-FILE *  _EXFUN(fopen64, (const char *, const char *));
-FILE *  _EXFUN(freopen64, (_CONST char *, _CONST char *, FILE *));
-_off64_t _EXFUN(ftello64, (FILE *));
-_off64_t _EXFUN(fseeko64, (FILE *, _off64_t, int));
-int     _EXFUN(fgetpos64, (FILE *, _fpos64_t *));
-int     _EXFUN(fsetpos64, (FILE *, const _fpos64_t *));
-FILE *  _EXFUN(tmpfile64, (void));
-
-FILE *	_EXFUN(_fdopen64_r, (struct _reent *, int, const char *));
-FILE *  _EXFUN(_fopen64_r, (struct _reent *,const char *, const char *));
-FILE *  _EXFUN(_freopen64_r, (struct _reent *, _CONST char *, _CONST char *, FILE *));
-_off64_t _EXFUN(_ftello64_r, (struct _reent *, FILE *));
-_off64_t _EXFUN(_fseeko64_r, (struct _reent *, FILE *, _off64_t, int));
-int     _EXFUN(_fgetpos64_r, (struct _reent *, FILE *, _fpos64_t *));
-int     _EXFUN(_fsetpos64_r, (struct _reent *, FILE *, const _fpos64_t *));
-FILE *  _EXFUN(_tmpfile64_r, (struct _reent *));
-#endif /* !__CYGWIN__ */
-#endif /* __LARGE64_FILES */
-
-/*
- * Routines internal to the implementation.
- */
-
-int	_EXFUN(__srget_r, (struct _reent *, FILE *));
-int	_EXFUN(__swbuf_r, (struct _reent *, int, FILE *));
-
-/*
- * Stdio function-access interface.
- */
-
-#ifndef __STRICT_ANSI__
-# ifdef __LARGE64_FILES
-FILE	*_EXFUN(funopen,(const _PTR __cookie,
-		int (*__readfn)(_PTR __c, char *__buf,
-				_READ_WRITE_BUFSIZE_TYPE __n),
-		int (*__writefn)(_PTR __c, const char *__buf,
-				 _READ_WRITE_BUFSIZE_TYPE __n),
-		_fpos64_t (*__seekfn)(_PTR __c, _fpos64_t __off, int __whence),
-		int (*__closefn)(_PTR __c)));
-FILE	*_EXFUN(_funopen_r,(struct _reent *, const _PTR __cookie,
-		int (*__readfn)(_PTR __c, char *__buf,
-				_READ_WRITE_BUFSIZE_TYPE __n),
-		int (*__writefn)(_PTR __c, const char *__buf,
-				 _READ_WRITE_BUFSIZE_TYPE __n),
-		_fpos64_t (*__seekfn)(_PTR __c, _fpos64_t __off, int __whence),
-		int (*__closefn)(_PTR __c)));
-# else
-FILE	*_EXFUN(funopen,(const _PTR __cookie,
-		int (*__readfn)(_PTR __cookie, char *__buf,
-				_READ_WRITE_BUFSIZE_TYPE __n),
-		int (*__writefn)(_PTR __cookie, const char *__buf,
-				 _READ_WRITE_BUFSIZE_TYPE __n),
-		fpos_t (*__seekfn)(_PTR __cookie, fpos_t __off, int __whence),
-		int (*__closefn)(_PTR __cookie)));
-FILE	*_EXFUN(_funopen_r,(struct _reent *, const _PTR __cookie,
-		int (*__readfn)(_PTR __cookie, char *__buf,
-				_READ_WRITE_BUFSIZE_TYPE __n),
-		int (*__writefn)(_PTR __cookie, const char *__buf,
-				 _READ_WRITE_BUFSIZE_TYPE __n),
-		fpos_t (*__seekfn)(_PTR __cookie, fpos_t __off, int __whence),
-		int (*__closefn)(_PTR __cookie)));
-# endif /* !__LARGE64_FILES */
-
-# define	fropen(__cookie, __fn) funopen(__cookie, __fn, (int (*)())0, \
-					       (fpos_t (*)())0, (int (*)())0)
-# define	fwopen(__cookie, __fn) funopen(__cookie, (int (*)())0, __fn, \
-					       (fpos_t (*)())0, (int (*)())0)
-
-typedef ssize_t cookie_read_function_t(void *__cookie, char *__buf, size_t __n);
-typedef ssize_t cookie_write_function_t(void *__cookie, const char *__buf,
-					size_t __n);
-# ifdef __LARGE64_FILES
-typedef int cookie_seek_function_t(void *__cookie, _off64_t *__off,
-				   int __whence);
-# else
-typedef int cookie_seek_function_t(void *__cookie, off_t *__off, int __whence);
-# endif /* !__LARGE64_FILES */
-typedef int cookie_close_function_t(void *__cookie);
-typedef struct
-{
-  /* These four struct member names are dictated by Linux; hopefully,
-     they don't conflict with any macros.  */
-  cookie_read_function_t  *read;
-  cookie_write_function_t *write;
-  cookie_seek_function_t  *seek;
-  cookie_close_function_t *close;
-} cookie_io_functions_t;
-FILE *_EXFUN(fopencookie,(void *__cookie,
-		const char *__mode, cookie_io_functions_t __functions));
-FILE *_EXFUN(_fopencookie_r,(struct _reent *, void *__cookie,
-		const char *__mode, cookie_io_functions_t __functions));
-#endif /* ! __STRICT_ANSI__ */
-
-#ifndef __CUSTOM_FILE_IO__
-/*
- * The __sfoo macros are here so that we can 
- * define function versions in the C library.
- */
-#define       __sgetc_raw_r(__ptr, __f) (--(__f)->_r < 0 ? __srget_r(__ptr, __f) : (int)(*(__f)->_p++))
-
-#ifdef __SCLE
-/*  For a platform with CR/LF, additional logic is required by
-  __sgetc_r which would otherwise simply be a macro; therefore we
-  use an inlined function.  The function is only meant to be inlined
-  in place as used and the function body should never be emitted.  
-
-  There are two possible means to this end when compiling with GCC,
-  one when compiling with a standard C99 compiler, and for other
-  compilers we're just stuck.  At the moment, this issue only
-  affects the Cygwin target, so we'll most likely be using GCC. */
-
-_ELIDABLE_INLINE int __sgetc_r(struct _reent *__ptr, FILE *__p);
-
-_ELIDABLE_INLINE int __sgetc_r(struct _reent *__ptr, FILE *__p)
-  {
-    int __c = __sgetc_raw_r(__ptr, __p);
-    if ((__p->_flags & __SCLE) && (__c == '\r'))
-      {
-      int __c2 = __sgetc_raw_r(__ptr, __p);
-      if (__c2 == '\n')
-        __c = __c2;
-      else
-        ungetc(__c2, __p);
-      }
-    return __c;
-  }
-#else
-#define __sgetc_r(__ptr, __p) __sgetc_raw_r(__ptr, __p)
-#endif
-
-#ifdef _never /* __GNUC__ */
-/* If this inline is actually used, then systems using coff debugging
-   info get hopelessly confused.  21sept93 rich@cygnus.com.  */
-_ELIDABLE_INLINE int __sputc_r(struct _reent *_ptr, int _c, FILE *_p) {
-	if (--_p->_w >= 0 || (_p->_w >= _p->_lbfsize && (char)_c != '\n'))
-		return (*_p->_p++ = _c);
-	else
-		return (__swbuf_r(_ptr, _c, _p));
-}
-#else
-/*
- * This has been tuned to generate reasonable code on the vax using pcc
- */
-#define       __sputc_raw_r(__ptr, __c, __p) \
-	(--(__p)->_w < 0 ? \
-		(__p)->_w >= (__p)->_lbfsize ? \
-			(*(__p)->_p = (__c)), *(__p)->_p != '\n' ? \
-				(int)*(__p)->_p++ : \
-				__swbuf_r(__ptr, '\n', __p) : \
-			__swbuf_r(__ptr, (int)(__c), __p) : \
-		(*(__p)->_p = (__c), (int)*(__p)->_p++))
-#ifdef __SCLE
-#define __sputc_r(__ptr, __c, __p) \
-        ((((__p)->_flags & __SCLE) && ((__c) == '\n')) \
-          ? __sputc_raw_r(__ptr, '\r', (__p)) : 0 , \
-        __sputc_raw_r((__ptr), (__c), (__p)))
-#else
-#define __sputc_r(__ptr, __c, __p) __sputc_raw_r(__ptr, __c, __p)
-#endif
-#endif
-
-#define	__sfeof(p)	((int)(((p)->_flags & __SEOF) != 0))
-#define	__sferror(p)	((int)(((p)->_flags & __SERR) != 0))
-#define	__sclearerr(p)	((void)((p)->_flags &= ~(__SERR|__SEOF)))
-#define	__sfileno(p)	((p)->_file)
-
-#ifndef _REENT_SMALL
-#define	feof(p)		__sfeof(p)
-#define	ferror(p)	__sferror(p)
-#define	clearerr(p)	__sclearerr(p)
-
-#if __BSD_VISIBLE
-#define	feof_unlocked(p)	__sfeof(p)
-#define	ferror_unlocked(p)	__sferror(p)
-#define	clearerr_unlocked(p)	__sclearerr(p)
-#endif /* __BSD_VISIBLE */
-#endif /* _REENT_SMALL */
-
-#if 0 /*ndef __STRICT_ANSI__ - FIXME: must initialize stdio first, use fn */
-#define	fileno(p)	__sfileno(p)
-#endif
-
-#ifndef __CYGWIN__
-#ifndef lint
-#ifdef __SINGLE_THREAD__
-#define	getc(fp)	__sgetc_r(_REENT, fp)
-#define putc(x, fp)	__sputc_r(_REENT, x, fp)
-#endif /* __SINGLE_THREAD__ */
-#endif /* lint */
-#endif /* __CYGWIN__ */
-
-#ifndef __STRICT_ANSI__
-/* fast always-buffered version, true iff error */
-#define	fast_putc(x,p) (--(p)->_w < 0 ? \
-	__swbuf_r(_REENT, (int)(x), p) == EOF : (*(p)->_p = (x), (p)->_p++, 0))
-
-#define	L_cuserid	9		/* posix says it goes in stdio.h :( */
-#ifdef __CYGWIN__
-#define L_ctermid       16
-#endif
-#endif
-
-#endif /* !__CUSTOM_FILE_IO__ */
-
-#ifdef __SINGLE_THREAD__
-#define	getchar()	getc(stdin)
-#define	putchar(x)	putc(x, stdout)
-#endif /* __SINGLE_THREAD__ */
-
-#ifndef __STRICT_ANSI__
-#define	getchar_unlocked()	getc_unlocked(stdin)
-#define	putchar_unlocked(x)	putc_unlocked(x, stdout)
-#endif
-
-_END_STD_C
-
-#endif /* _STDIO_H_ */
diff --git a/tools/sdk/include/newlib/stdio_ext.h b/tools/sdk/include/newlib/stdio_ext.h
deleted file mode 100644
index 029ab025353..00000000000
--- a/tools/sdk/include/newlib/stdio_ext.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * stdio_ext.h
- *
- * Definitions for I/O internal operations, originally from Solaris.
- */
-
-#ifndef _STDIO_EXT_H_
-#define _STDIO_EXT_H_
-
-#ifdef __rtems__
-#error "<stdio_ext.h> not supported"
-#endif
-
-#include <stdio.h>
-
-#define	FSETLOCKING_QUERY	0
-#define	FSETLOCKING_INTERNAL	1
-#define	FSETLOCKING_BYCALLER	2
-
-_BEGIN_STD_C
-
-void	 _EXFUN(__fpurge,(FILE *));
-int	 _EXFUN(__fsetlocking,(FILE *, int));
-
-/* TODO:
-
-   void _flushlbf (void);
-*/
-
-#ifdef  __GNUC__
-
-_ELIDABLE_INLINE size_t
-__fbufsize (FILE *__fp) { return (size_t) __fp->_bf._size; }
-
-_ELIDABLE_INLINE int
-__freading (FILE *__fp) { return (__fp->_flags & __SRD) != 0; }
-
-_ELIDABLE_INLINE int
-__fwriting (FILE *__fp) { return (__fp->_flags & __SWR) != 0; }
-
-_ELIDABLE_INLINE int
-__freadable (FILE *__fp) { return (__fp->_flags & (__SRD | __SRW)) != 0; }
-
-_ELIDABLE_INLINE int
-__fwritable (FILE *__fp) { return (__fp->_flags & (__SWR | __SRW)) != 0; }
-
-_ELIDABLE_INLINE int
-__flbf (FILE *__fp) { return (__fp->_flags & __SLBF) != 0; }
-
-_ELIDABLE_INLINE size_t
-__fpending (FILE *__fp) { return __fp->_p - __fp->_bf._base; }
-
-#else
-
-size_t	 _EXFUN(__fbufsize,(FILE *));
-int	 _EXFUN(__freading,(FILE *));
-int	 _EXFUN(__fwriting,(FILE *));
-int	 _EXFUN(__freadable,(FILE *));
-int	 _EXFUN(__fwritable,(FILE *));
-int	 _EXFUN(__flbf,(FILE *));
-size_t	 _EXFUN(__fpending,(FILE *));
-
-#ifndef __cplusplus
-
-#define __fbufsize(__fp) ((size_t) (__fp)->_bf._size)
-#define __freading(__fp) (((__fp)->_flags & __SRD) != 0)
-#define __fwriting(__fp) (((__fp)->_flags & __SWR) != 0)
-#define __freadable(__fp) (((__fp)->_flags & (__SRD | __SRW)) != 0)
-#define __fwritable(__fp) (((__fp)->_flags & (__SWR | __SRW)) != 0)
-#define __flbf(__fp) (((__fp)->_flags & __SLBF) != 0)
-#define __fpending(__fp) ((size_t) ((__fp)->_p - (__fp)->_bf._base))
-
-#endif /* __cplusplus */
-
-#endif /* __GNUC__ */
-
-_END_STD_C
-
-#endif /* _STDIO_EXT_H_ */
diff --git a/tools/sdk/include/newlib/stdlib.h b/tools/sdk/include/newlib/stdlib.h
deleted file mode 100644
index 254ddd71f7b..00000000000
--- a/tools/sdk/include/newlib/stdlib.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * stdlib.h
- *
- * Definitions for common types, variables, and functions.
- */
-
-#ifndef _STDLIB_H_
-#define _STDLIB_H_
-
-#include <machine/ieeefp.h>
-#include "_ansi.h"
-
-#define __need_size_t
-#define __need_wchar_t
-#define __need_NULL
-#include <stddef.h>
-
-#include <sys/reent.h>
-#include <sys/cdefs.h>
-#include <machine/stdlib.h>
-#ifndef __STRICT_ANSI__
-#include <alloca.h>
-#endif
-
-#ifdef __CYGWIN__
-#include <cygwin/stdlib.h>
-#endif
-
-_BEGIN_STD_C
-
-typedef struct 
-{
-  int quot; /* quotient */
-  int rem; /* remainder */
-} div_t;
-
-typedef struct 
-{
-  long quot; /* quotient */
-  long rem; /* remainder */
-} ldiv_t;
-
-#if !defined(__STRICT_ANSI__) || \
-  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
-  (defined(__cplusplus) && __cplusplus >= 201103L)
-typedef struct
-{
-  long long int quot; /* quotient */
-  long long int rem; /* remainder */
-} lldiv_t;
-#endif
-
-#ifndef __compar_fn_t_defined
-#define __compar_fn_t_defined
-typedef int (*__compar_fn_t) (const _PTR, const _PTR);
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-#define EXIT_FAILURE 1
-#define EXIT_SUCCESS 0
-
-#define RAND_MAX __RAND_MAX
-
-int	_EXFUN(__locale_mb_cur_max,(_VOID));
-
-#define MB_CUR_MAX __locale_mb_cur_max()
-
-_VOID	_EXFUN(abort,(_VOID) _ATTRIBUTE ((__noreturn__)));
-int	_EXFUN(abs,(int));
-int	_EXFUN(atexit,(_VOID (*__func)(_VOID)));
-double	_EXFUN(atof,(const char *__nptr));
-#ifndef __STRICT_ANSI__
-float	_EXFUN(atoff,(const char *__nptr));
-#endif
-int	_EXFUN(atoi,(const char *__nptr));
-int	_EXFUN(_atoi_r,(struct _reent *, const char *__nptr));
-long	_EXFUN(atol,(const char *__nptr));
-long	_EXFUN(_atol_r,(struct _reent *, const char *__nptr));
-_PTR	_EXFUN(bsearch,(const _PTR __key,
-		       const _PTR __base,
-		       size_t __nmemb,
-		       size_t __size,
-		       __compar_fn_t _compar));
-_PTR	_EXFUN_NOTHROW(calloc,(size_t __nmemb, size_t __size));
-div_t	_EXFUN(div,(int __numer, int __denom));
-_VOID	_EXFUN(exit,(int __status) _ATTRIBUTE ((__noreturn__)));
-_VOID	_EXFUN_NOTHROW(free,(_PTR));
-char *  _EXFUN(getenv,(const char *__string));
-char *	_EXFUN(_getenv_r,(struct _reent *, const char *__string));
-char *	_EXFUN(_findenv,(_CONST char *, int *));
-char *	_EXFUN(_findenv_r,(struct _reent *, _CONST char *, int *));
-#ifndef __STRICT_ANSI__
-extern char *suboptarg;			/* getsubopt(3) external variable */
-int	_EXFUN(getsubopt,(char **, char * const *, char **));
-#endif
-long	_EXFUN(labs,(long));
-ldiv_t	_EXFUN(ldiv,(long __numer, long __denom));
-_PTR	_EXFUN_NOTHROW(malloc,(size_t __size));
-int	_EXFUN(mblen,(const char *, size_t));
-int	_EXFUN(_mblen_r,(struct _reent *, const char *, size_t, _mbstate_t *));
-int	_EXFUN(mbtowc,(wchar_t *__restrict, const char *__restrict, size_t));
-int	_EXFUN(_mbtowc_r,(struct _reent *, wchar_t *__restrict, const char *__restrict, size_t, _mbstate_t *));
-int	_EXFUN(wctomb,(char *, wchar_t));
-int	_EXFUN(_wctomb_r,(struct _reent *, char *, wchar_t, _mbstate_t *));
-size_t	_EXFUN(mbstowcs,(wchar_t *__restrict, const char *__restrict, size_t));
-size_t	_EXFUN(_mbstowcs_r,(struct _reent *, wchar_t *__restrict, const char *__restrict, size_t, _mbstate_t *));
-size_t	_EXFUN(wcstombs,(char *__restrict, const wchar_t *__restrict, size_t));
-size_t	_EXFUN(_wcstombs_r,(struct _reent *, char *__restrict, const wchar_t *__restrict, size_t, _mbstate_t *));
-#ifndef __STRICT_ANSI__
-#ifndef _REENT_ONLY
-char *	_EXFUN(mkdtemp,(char *));
-int	_EXFUN(mkostemp,(char *, int));
-int	_EXFUN(mkostemps,(char *, int, int));
-int	_EXFUN(mkstemp,(char *));
-int	_EXFUN(mkstemps,(char *, int));
-#if (__GNUC__ < 4) || defined(__XTENSA__)
-char *	_EXFUN(mktemp,(char *));
-#else
-char *	_EXFUN(mktemp,(char *) _ATTRIBUTE ((__warning__ ("the use of `mktemp' is dangerous; use `mkstemp' instead"))));
-#endif
-#endif
-char *	_EXFUN(_mkdtemp_r, (struct _reent *, char *));
-int	_EXFUN(_mkostemp_r, (struct _reent *, char *, int));
-int	_EXFUN(_mkostemps_r, (struct _reent *, char *, int, int));
-int	_EXFUN(_mkstemp_r, (struct _reent *, char *));
-int	_EXFUN(_mkstemps_r, (struct _reent *, char *, int));
-#if (__GNUC__ < 4) || defined(__XTENSA__)
-char *	_EXFUN(_mktemp_r, (struct _reent *, char *)); 
-#else
-char *	_EXFUN(_mktemp_r, (struct _reent *, char *) _ATTRIBUTE ((__warning__ ("the use of `mktemp' is dangerous; use `mkstemp' instead"))));
-#endif
-#endif
-_VOID	_EXFUN(qsort,(_PTR __base, size_t __nmemb, size_t __size, __compar_fn_t _compar));
-int	_EXFUN(rand,(_VOID));
-_PTR	_EXFUN_NOTHROW(realloc,(_PTR __r, size_t __size));
-#ifndef __STRICT_ANSI__
-_PTR	_EXFUN(reallocf,(_PTR __r, size_t __size));
-char *	_EXFUN(realpath, (const char *__restrict path, char *__restrict resolved_path));
-#endif
-_VOID	_EXFUN(srand,(unsigned __seed));
-double	_EXFUN(strtod,(const char *__restrict __n, char **__restrict __end_PTR));
-double	_EXFUN(_strtod_r,(struct _reent *,const char *__restrict __n, char **__restrict __end_PTR));
-#if !defined(__STRICT_ANSI__) || \
-  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
-  (defined(__cplusplus) && __cplusplus >= 201103L)
-float	_EXFUN(strtof,(const char *__restrict __n, char **__restrict __end_PTR));
-#endif
-#ifndef __STRICT_ANSI__
-/* the following strtodf interface is deprecated...use strtof instead */
-# ifndef strtodf 
-#  define strtodf strtof
-# endif
-#endif
-long	_EXFUN(strtol,(const char *__restrict __n, char **__restrict __end_PTR, int __base));
-long	_EXFUN(_strtol_r,(struct _reent *,const char *__restrict __n, char **__restrict __end_PTR, int __base));
-unsigned long _EXFUN(strtoul,(const char *__restrict __n, char **__restrict __end_PTR, int __base));
-unsigned long _EXFUN(_strtoul_r,(struct _reent *,const char *__restrict __n, char **__restrict __end_PTR, int __base));
-
-int	_EXFUN(system,(const char *__string));
-
-#ifndef __STRICT_ANSI__
-long    _EXFUN(a64l,(const char *__input));
-char *  _EXFUN(l64a,(long __input));
-char *  _EXFUN(_l64a_r,(struct _reent *,long __input));
-int	_EXFUN(on_exit,(_VOID (*__func)(int, _PTR),_PTR __arg));
-#endif /* ! __STRICT_ANSI__ */
-#if !defined(__STRICT_ANSI__) || \
-  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
-  (defined(__cplusplus) && __cplusplus >= 201103L)
-_VOID	_EXFUN(_Exit,(int __status) _ATTRIBUTE ((__noreturn__)));
-#endif
-#ifndef __STRICT_ANSI__
-int	_EXFUN(putenv,(char *__string));
-int	_EXFUN(_putenv_r,(struct _reent *, char *__string));
-_PTR	_EXFUN(_reallocf_r,(struct _reent *, _PTR, size_t));
-int	_EXFUN(setenv,(const char *__string, const char *__value, int __overwrite));
-int	_EXFUN(_setenv_r,(struct _reent *, const char *__string, const char *__value, int __overwrite));
-
-char *	_EXFUN(gcvt,(double,int,char *));
-char *	_EXFUN(gcvtf,(float,int,char *));
-char *	_EXFUN(fcvt,(double,int,int *,int *));
-char *	_EXFUN(fcvtf,(float,int,int *,int *));
-char *	_EXFUN(ecvt,(double,int,int *,int *));
-char *	_EXFUN(ecvtbuf,(double, int, int*, int*, char *));
-char *	_EXFUN(fcvtbuf,(double, int, int*, int*, char *));
-char *	_EXFUN(ecvtf,(float,int,int *,int *));
-char *	_EXFUN(dtoa,(double, int, int, int *, int*, char**));
-#endif
-char *	_EXFUN(__itoa,(int, char *, int));
-char *	_EXFUN(__utoa,(unsigned, char *, int));
-#ifndef __STRICT_ANSI__
-char *	_EXFUN(itoa,(int, char *, int));
-char *	_EXFUN(utoa,(unsigned, char *, int));
-int	_EXFUN(rand_r,(unsigned *__seed));
-
-double _EXFUN(drand48,(_VOID));
-double _EXFUN(_drand48_r,(struct _reent *));
-double _EXFUN(erand48,(unsigned short [3]));
-double _EXFUN(_erand48_r,(struct _reent *, unsigned short [3]));
-long   _EXFUN(jrand48,(unsigned short [3]));
-long   _EXFUN(_jrand48_r,(struct _reent *, unsigned short [3]));
-_VOID  _EXFUN(lcong48,(unsigned short [7]));
-_VOID  _EXFUN(_lcong48_r,(struct _reent *, unsigned short [7]));
-long   _EXFUN(lrand48,(_VOID));
-long   _EXFUN(_lrand48_r,(struct _reent *));
-long   _EXFUN(mrand48,(_VOID));
-long   _EXFUN(_mrand48_r,(struct _reent *));
-long   _EXFUN(nrand48,(unsigned short [3]));
-long   _EXFUN(_nrand48_r,(struct _reent *, unsigned short [3]));
-unsigned short *
-       _EXFUN(seed48,(unsigned short [3]));
-unsigned short *
-       _EXFUN(_seed48_r,(struct _reent *, unsigned short [3]));
-_VOID  _EXFUN(srand48,(long));
-_VOID  _EXFUN(_srand48_r,(struct _reent *, long));
-#endif /* ! __STRICT_ANSI__ */
-#if !defined(__STRICT_ANSI__) || \
-  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
-  (defined(__cplusplus) && __cplusplus >= 201103L)
-long long _EXFUN(atoll,(const char *__nptr));
-#endif
-#ifndef __STRICT_ANSI__
-long long _EXFUN(_atoll_r,(struct _reent *, const char *__nptr));
-#endif /* ! __STRICT_ANSI__ */
-#if !defined(__STRICT_ANSI__) || \
-  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
-  (defined(__cplusplus) && __cplusplus >= 201103L)
-long long _EXFUN(llabs,(long long));
-lldiv_t	_EXFUN(lldiv,(long long __numer, long long __denom));
-long long _EXFUN(strtoll,(const char *__restrict __n, char **__restrict __end_PTR, int __base));
-#endif
-#ifndef __STRICT_ANSI__
-long long _EXFUN(_strtoll_r,(struct _reent *, const char *__restrict __n, char **__restrict __end_PTR, int __base));
-#endif /* ! __STRICT_ANSI__ */
-#if !defined(__STRICT_ANSI__) || \
-  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
-  (defined(__cplusplus) && __cplusplus >= 201103L)
-unsigned long long _EXFUN(strtoull,(const char *__restrict __n, char **__restrict __end_PTR, int __base));
-#endif
-#ifndef __STRICT_ANSI__
-unsigned long long _EXFUN(_strtoull_r,(struct _reent *, const char *__restrict __n, char **__restrict __end_PTR, int __base));
-
-#ifndef __CYGWIN__
-_VOID	_EXFUN(cfree,(_PTR));
-int	_EXFUN(unsetenv,(const char *__string));
-int	_EXFUN(_unsetenv_r,(struct _reent *, const char *__string));
-#endif
-
-#ifdef __rtems__
-int _EXFUN(posix_memalign,(void **, size_t, size_t));
-#endif
-
-#endif /* ! __STRICT_ANSI__ */
-
-char *	_EXFUN(_dtoa_r,(struct _reent *, double, int, int, int *, int*, char**));
-#ifndef __CYGWIN__
-_PTR	_EXFUN_NOTHROW(_malloc_r,(struct _reent *, size_t));
-_PTR	_EXFUN_NOTHROW(_calloc_r,(struct _reent *, size_t, size_t));
-_VOID	_EXFUN_NOTHROW(_free_r,(struct _reent *, _PTR));
-_PTR	_EXFUN_NOTHROW(_realloc_r,(struct _reent *, _PTR, size_t));
-_VOID	_EXFUN(_mstats_r,(struct _reent *, char *));
-#endif
-int	_EXFUN(_system_r,(struct _reent *, const char *));
-
-_VOID	_EXFUN(__eprintf,(const char *, const char *, unsigned int, const char *));
-
-/* There are two common qsort_r variants.  If you request
-   _BSD_SOURCE, you get the BSD version; otherwise you get the GNU
-   version.  We want that #undef qsort_r will still let you
-   invoke the underlying function, but that requires gcc support. */
-#ifdef _BSD_SOURCE
-# ifdef __GNUC__
-_VOID	_EXFUN(qsort_r,(_PTR __base, size_t __nmemb, size_t __size, _PTR __thunk, int (*_compar)(_PTR, const _PTR, const _PTR)))
-             __asm__ (__ASMNAME ("__bsd_qsort_r"));
-# else
-_VOID	_EXFUN(__bsd_qsort_r,(_PTR __base, size_t __nmemb, size_t __size, _PTR __thunk, int (*_compar)(_PTR, const _PTR, const _PTR)));
-#  define qsort_r __bsd_qsort_r
-# endif
-#elif __GNU_VISIBLE
-_VOID	_EXFUN(qsort_r,(_PTR __base, size_t __nmemb, size_t __size, int (*_compar)(const _PTR, const _PTR, _PTR), _PTR __thunk));
-#endif
-
-/* On platforms where long double equals double.  */
-#ifdef _HAVE_LONG_DOUBLE
-#if !defined(__STRICT_ANSI__) || \
-  (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \
-  (defined(__cplusplus) && __cplusplus >= 201103L)
-extern long double strtold (const char *__restrict, char **__restrict);
-#endif
-#endif /* _HAVE_LONG_DOUBLE */
-
-_END_STD_C
-
-#endif /* _STDLIB_H_ */
diff --git a/tools/sdk/include/newlib/string.h b/tools/sdk/include/newlib/string.h
deleted file mode 100644
index af5c9da4d1d..00000000000
--- a/tools/sdk/include/newlib/string.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * string.h
- *
- * Definitions for memory and string functions.
- */
-
-#ifndef _STRING_H_
-#define	_STRING_H_
-
-#include "_ansi.h"
-#include <sys/reent.h>
-#include <sys/cdefs.h>
-#include <sys/features.h>
-
-#define __need_size_t
-#define __need_NULL
-#include <stddef.h>
-
-_BEGIN_STD_C
-
-_PTR 	 _EXFUN(memchr,(const _PTR, int, size_t));
-int 	 _EXFUN(memcmp,(const _PTR, const _PTR, size_t));
-_PTR 	 _EXFUN(memcpy,(_PTR __restrict, const _PTR __restrict, size_t));
-_PTR	 _EXFUN(memmove,(_PTR, const _PTR, size_t));
-_PTR	 _EXFUN(memset,(_PTR, int, size_t));
-char 	*_EXFUN(strcat,(char *__restrict, const char *__restrict));
-char 	*_EXFUN(strchr,(const char *, int));
-int	 _EXFUN(strcmp,(const char *, const char *));
-int	 _EXFUN(strcoll,(const char *, const char *));
-char 	*_EXFUN(strcpy,(char *__restrict, const char *__restrict));
-size_t	 _EXFUN(strcspn,(const char *, const char *));
-char 	*_EXFUN(strerror,(int));
-size_t	 _EXFUN(strlen,(const char *));
-char 	*_EXFUN(strncat,(char *__restrict, const char *__restrict, size_t));
-int	 _EXFUN(strncmp,(const char *, const char *, size_t));
-char 	*_EXFUN(strncpy,(char *__restrict, const char *__restrict, size_t));
-char 	*_EXFUN(strpbrk,(const char *, const char *));
-char 	*_EXFUN(strrchr,(const char *, int));
-size_t	 _EXFUN(strspn,(const char *, const char *));
-char 	*_EXFUN(strstr,(const char *, const char *));
-#ifndef _REENT_ONLY
-char 	*_EXFUN(strtok,(char *__restrict, const char *__restrict));
-#endif
-size_t	 _EXFUN(strxfrm,(char *__restrict, const char *__restrict, size_t));
-
-#if __POSIX_VISIBLE
-char 	*_EXFUN(strtok_r,(char *__restrict, const char *__restrict, char **__restrict));
-#endif
-#if __BSD_VISIBLE
-int	 _EXFUN(bcmp,(const void *, const void *, size_t));
-void	 _EXFUN(bcopy,(const void *, void *, size_t));
-void	 _EXFUN(bzero,(void *, size_t));
-int	 _EXFUN(ffs,(int));
-char 	*_EXFUN(index,(const char *, int));
-#endif
-#if __BSD_VISIBLE || __XSI_VISIBLE
-_PTR	 _EXFUN(memccpy,(_PTR __restrict, const _PTR __restrict, int, size_t));
-#endif
-#if __GNU_VISIBLE
-_PTR	 _EXFUN(mempcpy,(_PTR, const _PTR, size_t));
-_PTR	 _EXFUN(memmem, (const _PTR, size_t, const _PTR, size_t));
-#endif
-_PTR 	 _EXFUN(memrchr,(const _PTR, int, size_t));
-#if __GNU_VISIBLE
-_PTR 	 _EXFUN(rawmemchr,(const _PTR, int));
-#endif
-#if __BSD_VISIBLE
-char 	*_EXFUN(rindex,(const char *, int));
-#endif
-char 	*_EXFUN(stpcpy,(char *__restrict, const char *__restrict));
-char 	*_EXFUN(stpncpy,(char *__restrict, const char *__restrict, size_t));
-#if __BSD_VISIBLE || __POSIX_VISIBLE
-int	 _EXFUN(strcasecmp,(const char *, const char *));
-#endif
-#if __GNU_VISIBLE
-char	*_EXFUN(strcasestr,(const char *, const char *));
-char 	*_EXFUN(strchrnul,(const char *, int));
-#endif
-#if __XSI_VISIBLE >= 500
-char 	*_EXFUN(strdup,(const char *));
-#endif
-#ifndef __STRICT_ANSI__
-char 	*_EXFUN(_strdup_r,(struct _reent *, const char *));
-#endif
-#if __XSI_VISIBLE >= 700
-char 	*_EXFUN(strndup,(const char *, size_t));
-#endif
-
-#ifndef __STRICT_ANSI__
-char 	*_EXFUN(_strndup_r,(struct _reent *, const char *, size_t));
-#endif
-
-#if __GNU_VISIBLE
-int	 _EXFUN(ffsl,(long));
-int	 _EXFUN(ffsll, (long long));
-#endif
-
-/* There are two common strerror_r variants.  If you request
-   _GNU_SOURCE, you get the GNU version; otherwise you get the POSIX
-   version.  POSIX requires that #undef strerror_r will still let you
-   invoke the underlying function, but that requires gcc support.  */
-#if __GNU_VISIBLE
-char	*_EXFUN(strerror_r,(int, char *, size_t));
-#else
-# ifdef __GNUC__
-int	_EXFUN(strerror_r,(int, char *, size_t))
-             __asm__ (__ASMNAME ("__xpg_strerror_r"));
-# else
-int	_EXFUN(__xpg_strerror_r,(int, char *, size_t));
-#  define strerror_r __xpg_strerror_r
-# endif
-#endif
-
-/* Reentrant version of strerror.  */
-char *	_EXFUN(_strerror_r, (struct _reent *, int, int, int *));
-
-#if __BSD_VISIBLE
-size_t	_EXFUN(strlcat,(char *, const char *, size_t));
-size_t	_EXFUN(strlcpy,(char *, const char *, size_t));
-#endif
-#if __BSD_VISIBLE || __POSIX_VISIBLE
-int	_EXFUN(strncasecmp,(const char *, const char *, size_t));
-#endif
-#if !defined(__STRICT_ANSI__) || __POSIX_VISIBLE >= 200809 || \
-    __XSI_VISIBLE >= 700
-size_t	 _EXFUN(strnlen,(const char *, size_t));
-#endif
-#if __BSD_VISIBLE
-char 	*_EXFUN(strsep,(char **, const char *));
-#endif
-
-/*
- * The origin of these is unknown to me so I am conditionalizing them
- * on __STRICT_ANSI__. Finetuning this is definitely needed. --joel
- */
-#if !defined(__STRICT_ANSI__)
-char	*_EXFUN(strlwr,(char *));
-char	*_EXFUN(strupr,(char *));
-#endif
-
-#ifndef DEFS_H	/* Kludge to work around problem compiling in gdb */
-char	*_EXFUN(strsignal, (int __signo));
-#endif
-
-#ifdef __CYGWIN__
-int	_EXFUN(strtosigno, (const char *__name));
-#endif
-
-#if defined _GNU_SOURCE && defined __GNUC__
-#define strdupa(__s) \
-	(__extension__ ({const char *__in = (__s); \
-			 size_t __len = strlen (__in) + 1; \
-			 char * __out = (char *) __builtin_alloca (__len); \
-			 (char *) memcpy (__out, __in, __len);}))
-#define strndupa(__s, __n) \
-	(__extension__ ({const char *__in = (__s); \
-			 size_t __len = strnlen (__in, (__n)) + 1; \
-			 char *__out = (char *) __builtin_alloca (__len); \
-			 __out[__len-1] = '\0'; \
-			 (char *) memcpy (__out, __in, __len-1);}))
-#endif /* _GNU_SOURCE && __GNUC__ */
-
-#include <sys/string.h>
-
-_END_STD_C
-
-#endif /* _STRING_H_ */
diff --git a/tools/sdk/include/newlib/strings.h b/tools/sdk/include/newlib/strings.h
deleted file mode 100644
index 131d81d20c4..00000000000
--- a/tools/sdk/include/newlib/strings.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * strings.h
- *
- * Definitions for string operations.
- */
-
-#ifndef _STRINGS_H_
-#define _STRINGS_H_
-
-#include "_ansi.h"
-#include <sys/reent.h>
-
-#include <sys/types.h> /* for size_t */
-
-_BEGIN_STD_C
-
-#if !defined __STRICT_ANSI__ && _POSIX_VERSION < 200809L
-/* 
- * Marked LEGACY in Open Group Base Specifications Issue 6/IEEE Std 1003.1-2004
- * Removed from Open Group Base Specifications Issue 7/IEEE Std 1003.1-2008
- */
-int	 _EXFUN(bcmp,(const void *, const void *, size_t));
-void	 _EXFUN(bcopy,(const void *, void *, size_t));
-void	 _EXFUN(bzero,(void *, size_t));
-char 	*_EXFUN(index,(const char *, int));
-char 	*_EXFUN(rindex,(const char *, int));
-#endif /* ! __STRICT_ANSI__ */
-
-int	 _EXFUN(ffs,(int));
-int	 _EXFUN(strcasecmp,(const char *, const char *));
-int	 _EXFUN(strncasecmp,(const char *, const char *, size_t));
-
-_END_STD_C
-
-#endif /* _STRINGS_H_ */
diff --git a/tools/sdk/include/newlib/sys/_default_fcntl.h b/tools/sdk/include/newlib/sys/_default_fcntl.h
deleted file mode 100644
index eb674ae7975..00000000000
--- a/tools/sdk/include/newlib/sys/_default_fcntl.h
+++ /dev/null
@@ -1,213 +0,0 @@
-
-#ifndef	_SYS__DEFAULT_FCNTL_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-#define	_SYS__DEFAULT_FCNTL_H_
-#include <_ansi.h>
-#include <sys/cdefs.h>
-#define	_FOPEN		(-1)	/* from sys/file.h, kernel use only */
-#define	_FREAD		0x0001	/* read enabled */
-#define	_FWRITE		0x0002	/* write enabled */
-#define	_FAPPEND	0x0008	/* append (writes guaranteed at the end) */
-#define	_FMARK		0x0010	/* internal; mark during gc() */
-#define	_FDEFER		0x0020	/* internal; defer for next gc pass */
-#define	_FASYNC		0x0040	/* signal pgrp when data ready */
-#define	_FSHLOCK	0x0080	/* BSD flock() shared lock present */
-#define	_FEXLOCK	0x0100	/* BSD flock() exclusive lock present */
-#define	_FCREAT		0x0200	/* open with file create */
-#define	_FTRUNC		0x0400	/* open with truncation */
-#define	_FEXCL		0x0800	/* error on open if file exists */
-#define	_FNBIO		0x1000	/* non blocking I/O (sys5 style) */
-#define	_FSYNC		0x2000	/* do all writes synchronously */
-#define	_FNONBLOCK	0x4000	/* non blocking I/O (POSIX style) */
-#define	_FNDELAY	_FNONBLOCK	/* non blocking I/O (4.2 style) */
-#define	_FNOCTTY	0x8000	/* don't assign a ctty on this open */
-
-#define	O_ACCMODE	(O_RDONLY|O_WRONLY|O_RDWR)
-
-/*
- * Flag values for open(2) and fcntl(2)
- * The kernel adds 1 to the open modes to turn it into some
- * combination of FREAD and FWRITE.
- */
-#define	O_RDONLY	0		/* +1 == FREAD */
-#define	O_WRONLY	1		/* +1 == FWRITE */
-#define	O_RDWR		2		/* +1 == FREAD|FWRITE */
-#define	O_APPEND	_FAPPEND
-#define	O_CREAT		_FCREAT
-#define	O_TRUNC		_FTRUNC
-#define	O_EXCL		_FEXCL
-#define O_SYNC		_FSYNC
-/*	O_NDELAY	_FNDELAY 	set in include/fcntl.h */
-/*	O_NDELAY	_FNBIO 		set in include/fcntl.h */
-#define	O_NONBLOCK	_FNONBLOCK
-#define	O_NOCTTY	_FNOCTTY
-/* For machines which care - */
-#if defined (__CYGWIN__)
-#define _FBINARY        0x10000
-#define _FTEXT          0x20000
-#define _FNOINHERIT	0x40000
-#define _FDIRECT        0x80000
-#define _FNOFOLLOW      0x100000
-#define _FDIRECTORY     0x200000
-#define _FEXECSRCH      0x400000
-
-#define O_BINARY	_FBINARY
-#define O_TEXT		_FTEXT
-#define O_CLOEXEC	_FNOINHERIT
-#define O_DIRECT        _FDIRECT
-#define O_NOFOLLOW      _FNOFOLLOW
-#define O_DSYNC         _FSYNC
-#define O_RSYNC         _FSYNC
-#define O_DIRECTORY     _FDIRECTORY
-#define O_EXEC          _FEXECSRCH
-#define O_SEARCH        _FEXECSRCH
-#endif
-
-#ifndef	_POSIX_SOURCE
-
-/*
- * Flags that work for fcntl(fd, F_SETFL, FXXXX)
- */
-#define	FAPPEND		_FAPPEND
-#define	FSYNC		_FSYNC
-#define	FASYNC		_FASYNC
-#define	FNBIO		_FNBIO
-#define	FNONBIO		_FNONBLOCK	/* XXX fix to be NONBLOCK everywhere */
-#define	FNDELAY		_FNDELAY
-
-/*
- * Flags that are disallowed for fcntl's (FCNTLCANT);
- * used for opens, internal state, or locking.
- */
-#define	FREAD		_FREAD
-#define	FWRITE		_FWRITE
-#define	FMARK		_FMARK
-#define	FDEFER		_FDEFER
-#define	FSHLOCK		_FSHLOCK
-#define	FEXLOCK		_FEXLOCK
-
-/*
- * The rest of the flags, used only for opens
- */
-#define	FOPEN		_FOPEN
-#define	FCREAT		_FCREAT
-#define	FTRUNC		_FTRUNC
-#define	FEXCL		_FEXCL
-#define	FNOCTTY		_FNOCTTY
-
-#endif	/* !_POSIX_SOURCE */
-
-/* XXX close on exec request; must match UF_EXCLOSE in user.h */
-#define	FD_CLOEXEC	1	/* posix */
-
-/* fcntl(2) requests */
-#define	F_DUPFD		0	/* Duplicate fildes */
-#define	F_GETFD		1	/* Get fildes flags (close on exec) */
-#define	F_SETFD		2	/* Set fildes flags (close on exec) */
-#define	F_GETFL		3	/* Get file flags */
-#define	F_SETFL		4	/* Set file flags */
-#ifndef	_POSIX_SOURCE
-#define	F_GETOWN 	5	/* Get owner - for ASYNC */
-#define	F_SETOWN 	6	/* Set owner - for ASYNC */
-#endif	/* !_POSIX_SOURCE */
-#define	F_GETLK  	7	/* Get record-locking information */
-#define	F_SETLK  	8	/* Set or Clear a record-lock (Non-Blocking) */
-#define	F_SETLKW 	9	/* Set or Clear a record-lock (Blocking) */
-#ifndef	_POSIX_SOURCE
-#define	F_RGETLK 	10	/* Test a remote lock to see if it is blocked */
-#define	F_RSETLK 	11	/* Set or unlock a remote lock */
-#define	F_CNVT 		12	/* Convert a fhandle to an open fd */
-#define	F_RSETLKW 	13	/* Set or Clear remote record-lock(Blocking) */
-#endif	/* !_POSIX_SOURCE */
-#ifdef __CYGWIN__
-#define	F_DUPFD_CLOEXEC	14	/* As F_DUPFD, but set close-on-exec flag */
-#endif
-
-/* fcntl(2) flags (l_type field of flock structure) */
-#define	F_RDLCK		1	/* read lock */
-#define	F_WRLCK		2	/* write lock */
-#define	F_UNLCK		3	/* remove lock(s) */
-#ifndef	_POSIX_SOURCE
-#define	F_UNLKSYS	4	/* remove remote locks for a given system */
-#endif	/* !_POSIX_SOURCE */
-
-#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200809 || defined(__CYGWIN__)
-/* Special descriptor value to denote the cwd in calls to openat(2) etc. */
-#define AT_FDCWD -2
-
-/* Flag values for faccessat2) et al. */
-#define AT_EACCESS              1
-#define AT_SYMLINK_NOFOLLOW     2
-#define AT_SYMLINK_FOLLOW       4
-#define AT_REMOVEDIR            8
-#endif
-
-#if __BSD_VISIBLE
-/* lock operations for flock(2) */
-#define	LOCK_SH		0x01		/* shared file lock */
-#define	LOCK_EX		0x02		/* exclusive file lock */
-#define	LOCK_NB		0x04		/* don't block when locking */
-#define	LOCK_UN		0x08		/* unlock file */
-#endif
-
-/*#include <sys/stdtypes.h>*/
-
-#ifndef __CYGWIN__
-/* file segment locking set data type - information passed to system by user */
-struct flock {
-	short	l_type;		/* F_RDLCK, F_WRLCK, or F_UNLCK */
-	short	l_whence;	/* flag to choose starting offset */
-	long	l_start;	/* relative offset, in bytes */
-	long	l_len;		/* length, in bytes; 0 means lock to EOF */
-	short	l_pid;		/* returned with F_GETLK */
-	short	l_xxx;		/* reserved for future use */
-};
-#endif /* __CYGWIN__ */
-
-#ifndef	_POSIX_SOURCE
-/* extended file segment locking set data type */
-struct eflock {
-	short	l_type;		/* F_RDLCK, F_WRLCK, or F_UNLCK */
-	short	l_whence;	/* flag to choose starting offset */
-	long	l_start;	/* relative offset, in bytes */
-	long	l_len;		/* length, in bytes; 0 means lock to EOF */
-	short	l_pid;		/* returned with F_GETLK */
-	short	l_xxx;		/* reserved for future use */
-	long	l_rpid;		/* Remote process id wanting this lock */
-	long	l_rsys;		/* Remote system id wanting this lock */
-};
-#endif	/* !_POSIX_SOURCE */
-
-#include <sys/types.h>
-#include <sys/stat.h>		/* sigh. for the mode bits for open/creat */
-
-extern int open _PARAMS ((const char *, int, ...));
-#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200809 || defined(__CYGWIN__)
-extern int openat _PARAMS ((int, const char *, int, ...));
-#endif
-extern int creat _PARAMS ((const char *, mode_t));
-extern int fcntl _PARAMS ((int, int, ...));
-#if __BSD_VISIBLE
-extern int flock _PARAMS ((int, int));
-#endif
-#ifdef __CYGWIN__
-#include <sys/time.h>
-extern int futimesat _PARAMS ((int, const char *, const struct timeval *));
-#endif
-
-/* Provide _<systemcall> prototypes for functions provided by some versions
-   of newlib.  */
-#ifdef _COMPILING_NEWLIB
-extern int _open _PARAMS ((const char *, int, ...));
-extern int _fcntl _PARAMS ((int, int, ...));
-#ifdef __LARGE64_FILES
-extern int _open64 _PARAMS ((const char *, int, ...));
-#endif
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif	/* !_SYS__DEFAULT_FCNTL_H_ */
diff --git a/tools/sdk/include/newlib/sys/_intsup.h b/tools/sdk/include/newlib/sys/_intsup.h
deleted file mode 100644
index fa78426c520..00000000000
--- a/tools/sdk/include/newlib/sys/_intsup.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2004, 2005 by
- * Ralf Corsepius, Ulm/Germany. All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software
- * is freely granted, provided that this notice is preserved.
- *
- * Modified for xtensa arch & non-long int32_t, removes automatic setting of __have_long32.
- */
-
-#ifndef _SYS__INTSUP_H
-#define _SYS__INTSUP_H
-
-#include <sys/features.h>
-
-#define __STDINT_EXP(x) __##x##__
-
-#define __have_longlong64 1
-
-#endif /* _SYS__INTSUP_H */
diff --git a/tools/sdk/include/newlib/sys/_types.h b/tools/sdk/include/newlib/sys/_types.h
deleted file mode 100644
index 07bc27675af..00000000000
--- a/tools/sdk/include/newlib/sys/_types.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* ANSI C namespace clean utility typedefs */
-
-/* This file defines various typedefs needed by the system calls that support
-   the C library.  Basically, they're just the POSIX versions with an '_'
-   prepended.  This file lives in the `sys' directory so targets can provide
-   their own if desired (or they can put target dependant conditionals here).
-*/
-
-#ifndef	_SYS__TYPES_H
-#define _SYS__TYPES_H
-
-#include <machine/_types.h>
-#include <sys/lock.h>
-
-#ifndef __off_t_defined
-typedef long _off_t;
-#endif
-
-#ifndef __dev_t_defined
-typedef short __dev_t;
-#endif
-
-#ifndef __uid_t_defined
-typedef unsigned short __uid_t;
-#endif
-#ifndef __gid_t_defined
-typedef unsigned short __gid_t;
-#endif
-
-#ifndef __off64_t_defined
-__extension__ typedef long long _off64_t;
-#endif
-
-/*
- * We need fpos_t for the following, but it doesn't have a leading "_",
- * so we use _fpos_t instead.
- */
-#ifndef __fpos_t_defined
-typedef long _fpos_t;		/* XXX must match off_t in <sys/types.h> */
-				/* (and must be `long' for now) */
-#endif
-
-#ifdef __LARGE64_FILES
-#ifndef __fpos64_t_defined
-typedef _off64_t _fpos64_t;
-#endif
-#endif
-
-#ifndef __ssize_t_defined
-#ifdef __SIZE_TYPE__
-/* If __SIZE_TYPE__ is defined (gcc) we define ssize_t based on size_t.
-   We simply change "unsigned" to "signed" for this single definition
-   to make sure ssize_t and size_t only differ by their signedness. */
-#define unsigned signed
-typedef __SIZE_TYPE__ _ssize_t;
-#undef unsigned
-#else
-#if defined(__INT_MAX__) && __INT_MAX__ == 2147483647
-typedef int _ssize_t;
-#else
-typedef long _ssize_t;
-#endif
-#endif
-#endif
-
-#define __need_wint_t
-#include <stddef.h>
-
-#ifndef __mbstate_t_defined
-/* Conversion state information.  */
-typedef struct
-{
-  int __count;
-  union
-  {
-    wint_t __wch;
-    unsigned char __wchb[4];
-  } __value;		/* Value so far.  */
-} _mbstate_t;
-#endif
-
-#ifndef __flock_t_defined
-typedef _LOCK_RECURSIVE_T _flock_t;
-#endif
-
-#ifndef __iconv_t_defined
-/* Iconv descriptor type */
-typedef void *_iconv_t;
-#endif
-
-#endif	/* _SYS__TYPES_H */
diff --git a/tools/sdk/include/newlib/sys/cdefs.h b/tools/sdk/include/newlib/sys/cdefs.h
deleted file mode 100644
index a5e613c63ca..00000000000
--- a/tools/sdk/include/newlib/sys/cdefs.h
+++ /dev/null
@@ -1,710 +0,0 @@
-/* libc/sys/linux/sys/cdefs.h - Helper macros for K&R vs. ANSI C compat. */
-
-/* Written 2000 by Werner Almesberger */
-
-/*-
- * Copyright (c) 1991, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * Berkeley Software Design, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)cdefs.h	8.8 (Berkeley) 1/9/95
- * $FreeBSD$
- */
-
-#ifndef	_SYS_CDEFS_H_
-#define	_SYS_CDEFS_H_
-
-#include <machine/_default_types.h>
-#include <sys/features.h>
-#include <stddef.h>
-
-#define __PMT(args)	args
-#define __DOTS    	, ...
-#define __THROW
-
-#ifdef __GNUC__
-# define __ASMNAME(cname)  __XSTRING (__USER_LABEL_PREFIX__) cname
-#endif
-
-#define __ptr_t void *
-#define __long_double_t  long double
-
-#define __attribute_malloc__
-#define __attribute_pure__
-#define __attribute_format_strfmon__(a,b)
-#define __flexarr      [0]
-
-#ifndef __BOUNDED_POINTERS__
-# define __bounded      /* nothing */
-# define __unbounded    /* nothing */
-# define __ptrvalue     /* nothing */
-#endif
-
-/*
- * Testing against Clang-specific extensions.
- */
-
-#ifndef	__has_extension
-#define	__has_extension		__has_feature
-#endif
-#ifndef	__has_feature
-#define	__has_feature(x)	0
-#endif
-#ifndef	__has_include
-#define	__has_include(x)	0
-#endif
-#ifndef	__has_builtin
-#define	__has_builtin(x)	0
-#endif
-
-#if defined(__cplusplus)
-#define	__BEGIN_DECLS	extern "C" {
-#define	__END_DECLS	}
-#else
-#define	__BEGIN_DECLS
-#define	__END_DECLS
-#endif
-
-/*
- * This code has been put in place to help reduce the addition of
- * compiler specific defines in FreeBSD code.  It helps to aid in
- * having a compiler-agnostic source tree.
- */
-
-#if defined(__GNUC__) || defined(__INTEL_COMPILER)
-
-#if __GNUC__ >= 3 || defined(__INTEL_COMPILER)
-#define __GNUCLIKE_ASM 3
-#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS
-#else
-#define __GNUCLIKE_ASM 2
-#endif
-#define __GNUCLIKE___TYPEOF 1
-#define __GNUCLIKE___OFFSETOF 1
-#define __GNUCLIKE___SECTION 1
-
-#ifndef __INTEL_COMPILER
-# define __GNUCLIKE_CTOR_SECTION_HANDLING 1
-#endif
-
-#define __GNUCLIKE_BUILTIN_CONSTANT_P 1
-# if defined(__INTEL_COMPILER) && defined(__cplusplus) \
-    && __INTEL_COMPILER < 800
-#  undef __GNUCLIKE_BUILTIN_CONSTANT_P
-# endif
-
-#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER)
-# define __GNUCLIKE_BUILTIN_VARARGS 1
-# define __GNUCLIKE_BUILTIN_STDARG 1
-# define __GNUCLIKE_BUILTIN_VAALIST 1
-#endif
-
-#if defined(__GNUC__)
-# define __GNUC_VA_LIST_COMPATIBILITY 1
-#endif
-
-/*
- * Compiler memory barriers, specific to gcc and clang.
- */
-#if defined(__GNUC__)
-#define	__compiler_membar()	__asm __volatile(" " : : : "memory")
-#endif
-
-#ifndef __INTEL_COMPILER
-# define __GNUCLIKE_BUILTIN_NEXT_ARG 1
-# define __GNUCLIKE_MATH_BUILTIN_RELOPS
-#endif
-
-#define __GNUCLIKE_BUILTIN_MEMCPY 1
-
-/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */
-#define __CC_SUPPORTS_INLINE 1
-#define __CC_SUPPORTS___INLINE 1
-#define __CC_SUPPORTS___INLINE__ 1
-
-#define __CC_SUPPORTS___FUNC__ 1
-#define __CC_SUPPORTS_WARNING 1
-
-#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */
-
-#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1
-
-#endif /* __GNUC__ || __INTEL_COMPILER */
-
-/*
- * The __CONCAT macro is used to concatenate parts of symbol names, e.g.
- * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo.
- * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI
- * mode -- there must be no spaces between its arguments, and for nested
- * __CONCAT's, all the __CONCAT's must be at the left.  __CONCAT can also
- * concatenate double-quoted strings produced by the __STRING macro, but
- * this only works with ANSI C.
- *
- * __XSTRING is like __STRING, but it expands any macros in its argument
- * first.  It is only available with ANSI C.
- */
-#if defined(__STDC__) || defined(__cplusplus)
-#define	__P(protos)	protos		/* full-blown ANSI C */
-#define	__CONCAT1(x,y)	x ## y
-#define	__CONCAT(x,y)	__CONCAT1(x,y)
-#define	__STRING(x)	#x		/* stringify without expanding x */
-#define	__XSTRING(x)	__STRING(x)	/* expand x, then stringify */
-
-#define	__const		const		/* define reserved names to standard */
-#define	__signed	signed
-#define	__volatile	volatile
-#if defined(__cplusplus)
-#define	__inline	inline		/* convert to C++ keyword */
-#else
-#if !(defined(__CC_SUPPORTS___INLINE))
-#define	__inline			/* delete GCC keyword */
-#endif /* ! __CC_SUPPORTS___INLINE */
-#endif /* !__cplusplus */
-
-#else	/* !(__STDC__ || __cplusplus) */
-#define	__P(protos)	()		/* traditional C preprocessor */
-#define	__CONCAT(x,y)	x/**/y
-#define	__STRING(x)	"x"
-
-#if !defined(__CC_SUPPORTS___INLINE)
-#define	__const				/* delete pseudo-ANSI C keywords */
-#define	__inline
-#define	__signed
-#define	__volatile
-/*
- * In non-ANSI C environments, new programs will want ANSI-only C keywords
- * deleted from the program and old programs will want them left alone.
- * When using a compiler other than gcc, programs using the ANSI C keywords
- * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS.
- * When using "gcc -traditional", we assume that this is the intent; if
- * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone.
- */
-#ifndef	NO_ANSI_KEYWORDS
-#define	const				/* delete ANSI C keywords */
-#define	inline
-#define	signed
-#define	volatile
-#endif	/* !NO_ANSI_KEYWORDS */
-#endif	/* !__CC_SUPPORTS___INLINE */
-#endif	/* !(__STDC__ || __cplusplus) */
-
-/*
- * Compiler-dependent macros to help declare dead (non-returning) and
- * pure (no side effects) functions, and unused variables.  They are
- * null except for versions of gcc that are known to support the features
- * properly (old versions of gcc-2 supported the dead and pure features
- * in a different (wrong) way).  If we do not provide an implementation
- * for a given compiler, let the compile fail if it is told to use
- * a feature that we cannot live without.
- */
-#ifdef lint
-#define	__dead2
-#define	__pure2
-#define	__unused
-#define	__packed
-#define	__aligned(x)
-#define	__section(x)
-#else
-#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER)
-#define	__dead2
-#define	__pure2
-#define	__unused
-#endif
-#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER)
-#define	__dead2		__attribute__((__noreturn__))
-#define	__pure2		__attribute__((__const__))
-#define	__unused
-/* XXX Find out what to do for __packed, __aligned and __section */
-#endif
-#if __GNUC_PREREQ__(2, 7)
-#define	__dead2		__attribute__((__noreturn__))
-#define	__pure2		__attribute__((__const__))
-#define	__unused	__attribute__((__unused__))
-#define	__used		__attribute__((__used__))
-#define	__packed	__attribute__((__packed__))
-#define	__aligned(x)	__attribute__((__aligned__(x)))
-#define	__section(x)	__attribute__((__section__(x)))
-#endif
-#if defined(__INTEL_COMPILER)
-#define __dead2		__attribute__((__noreturn__))
-#define __pure2		__attribute__((__const__))
-#define __unused	__attribute__((__unused__))
-#define __used		__attribute__((__used__))
-#define __packed	__attribute__((__packed__))
-#define __aligned(x)	__attribute__((__aligned__(x)))
-#define __section(x)	__attribute__((__section__(x)))
-#endif
-#endif
-
-#if !__GNUC_PREREQ__(2, 95)
-#define	__alignof(x)	__offsetof(struct { char __a; x __b; }, __b)
-#endif
-
-/*
- * Keywords added in C11.
- */
-
-#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 201112L
-
-#if !__has_extension(c_alignas)
-#if (defined(__cplusplus) && __cplusplus >= 201103L) || \
-    __has_extension(cxx_alignas)
-#define	_Alignas(x)		alignas(x)
-#else
-/* XXX: Only emulates _Alignas(constant-expression); not _Alignas(type-name). */
-#define	_Alignas(x)		__aligned(x)
-#endif
-#endif
-
-#if defined(__cplusplus) && __cplusplus >= 201103L
-#define	_Alignof(x)		alignof(x)
-#else
-#define	_Alignof(x)		__alignof(x)
-#endif
-
-#if !__has_extension(c_atomic) && !__has_extension(cxx_atomic)
-/*
- * No native support for _Atomic(). Place object in structure to prevent
- * most forms of direct non-atomic access.
- */
-#define	_Atomic(T)		struct { T volatile __val; }
-#endif
-
-#if defined(__cplusplus) && __cplusplus >= 201103L
-#define	_Noreturn		[[noreturn]]
-#else
-#define	_Noreturn		__dead2
-#endif
-
-#if __GNUC_PREREQ__(4, 6) && !defined(__cplusplus)
-/*  Do nothing: _Static_assert() works as per C11 */
-#elif !__has_extension(c_static_assert)
-#if (defined(__cplusplus) && __cplusplus >= 201103L) || \
-    __has_extension(cxx_static_assert)
-#define	_Static_assert(x, y)	static_assert(x, y)
-#elif defined(__COUNTER__)
-#define	_Static_assert(x, y)	__Static_assert(x, __COUNTER__)
-#define	__Static_assert(x, y)	___Static_assert(x, y)
-#define	___Static_assert(x, y)	typedef char __assert_ ## y[(x) ? 1 : -1]
-#else
-#define	_Static_assert(x, y)	struct __hack
-#endif
-#endif
-
-#if !__has_extension(c_thread_local)
-/* XXX: Change this to test against C++11 when clang in base supports it. */
-#if /* (defined(__cplusplus) && __cplusplus >= 201103L) || */ \
-    __has_extension(cxx_thread_local)
-#define	_Thread_local		thread_local
-#else
-#define	_Thread_local		__thread
-#endif
-#endif
-
-#endif /* __STDC_VERSION__ || __STDC_VERSION__ < 201112L */
-
-/*
- * Emulation of C11 _Generic().  Unlike the previously defined C11
- * keywords, it is not possible to implement this using exactly the same
- * syntax.  Therefore implement something similar under the name
- * __generic().  Unlike _Generic(), this macro can only distinguish
- * between a single type, so it requires nested invocations to
- * distinguish multiple cases.
- */
-
-#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
-#define	__generic(expr, t, yes, no)					\
-	_Generic(expr, t: yes, default: no)
-#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus)
-#define	__generic(expr, t, yes, no)					\
-	__builtin_choose_expr(						\
-	    __builtin_types_compatible_p(__typeof(expr), t), yes, no)
-#endif
-
-#if __GNUC_PREREQ__(2, 96)
-#define	__malloc_like	__attribute__((__malloc__))
-#define	__pure		__attribute__((__pure__))
-#else
-#define	__malloc_like
-#define	__pure
-#endif
-
-#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800)
-#define	__always_inline	__attribute__((__always_inline__))
-#else
-#define	__always_inline
-#endif
-
-#if __GNUC_PREREQ__(3, 1)
-#define	__noinline	__attribute__ ((__noinline__))
-#else
-#define	__noinline
-#endif
-
-#if __GNUC_PREREQ__(3, 3)
-#define __nonnull(x)	__attribute__((__nonnull__(x)))
-#else
-#define __nonnull(x)
-#endif
-
-#if __GNUC_PREREQ__(3, 4)
-#define	__fastcall	__attribute__((__fastcall__))
-#else
-#define	__fastcall
-#endif
-
-#if __GNUC_PREREQ__(4, 1)
-#define	__returns_twice	__attribute__((__returns_twice__))
-#else
-#define	__returns_twice
-#endif
-
-/* XXX: should use `#if __STDC_VERSION__ < 199901'. */
-#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
-#define	__func__	NULL
-#endif
-
-/*
- * GCC 2.95 provides `__restrict' as an extension to C90 to support the
- * C99-specific `restrict' type qualifier.  We happen to use `__restrict' as
- * a way to define the `restrict' type qualifier without disturbing older
- * software that is unaware of C99 keywords.
- */
-#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95)
-#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint)
-#define	__restrict
-#else
-#define	__restrict	restrict
-#endif
-#endif
-
-/*
- * GNU C version 2.96 adds explicit branch prediction so that
- * the CPU back-end can hint the processor and also so that
- * code blocks can be reordered such that the predicted path
- * sees a more linear flow, thus improving cache behavior, etc.
- *
- * The following two macros provide us with a way to utilize this
- * compiler feature.  Use __predict_true() if you expect the expression
- * to evaluate to true, and __predict_false() if you expect the
- * expression to evaluate to false.
- *
- * A few notes about usage:
- *
- *	* Generally, __predict_false() error condition checks (unless
- *	  you have some _strong_ reason to do otherwise, in which case
- *	  document it), and/or __predict_true() `no-error' condition
- *	  checks, assuming you want to optimize for the no-error case.
- *
- *	* Other than that, if you don't know the likelihood of a test
- *	  succeeding from empirical or other `hard' evidence, don't
- *	  make predictions.
- *
- *	* These are meant to be used in places that are run `a lot'.
- *	  It is wasteful to make predictions in code that is run
- *	  seldomly (e.g. at subsystem initialization time) as the
- *	  basic block reordering that this affects can often generate
- *	  larger code.
- */
-#if __GNUC_PREREQ__(2, 96)
-#define __predict_true(exp)     __builtin_expect((exp), 1)
-#define __predict_false(exp)    __builtin_expect((exp), 0)
-#else
-#define __predict_true(exp)     (exp)
-#define __predict_false(exp)    (exp)
-#endif
-
-#if __GNUC_PREREQ__(4, 2)
-#define	__hidden	__attribute__((__visibility__("hidden")))
-#define	__exported	__attribute__((__visibility__("default")))
-#else
-#define	__hidden
-#define	__exported
-#endif
-
-#define __offsetof(type, field)	offsetof(type, field)
-#define	__rangeof(type, start, end) \
-	(__offsetof(type, end) - __offsetof(type, start))
-
-/*
- * Given the pointer x to the member m of the struct s, return
- * a pointer to the containing structure.  When using GCC, we first
- * assign pointer x to a local variable, to check that its type is
- * compatible with member m.
- */
-#if __GNUC_PREREQ__(3, 1)
-#define	__containerof(x, s, m) ({					\
-	const volatile __typeof__(((s *)0)->m) *__x = (x);		\
-	__DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\
-})
-#else
-#define	__containerof(x, s, m)						\
-	__DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m))
-#endif
-
-/*
- * Compiler-dependent macros to declare that functions take printf-like
- * or scanf-like arguments.  They are null except for versions of gcc
- * that are known to support the features properly (old versions of gcc-2
- * didn't permit keeping the keywords out of the application namespace).
- */
-#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
-#define	__printflike(fmtarg, firstvararg)
-#define	__scanflike(fmtarg, firstvararg)
-#define	__format_arg(fmtarg)
-#define	__strfmonlike(fmtarg, firstvararg)
-#define	__strftimelike(fmtarg, firstvararg)
-#else
-#define	__printflike(fmtarg, firstvararg) \
-	    __attribute__((__format__ (__printf__, fmtarg, firstvararg)))
-#define	__scanflike(fmtarg, firstvararg) \
-	    __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))
-#define	__format_arg(fmtarg)	__attribute__((__format_arg__ (fmtarg)))
-#define	__strfmonlike(fmtarg, firstvararg) \
-	    __attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))
-#define	__strftimelike(fmtarg, firstvararg) \
-	    __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))
-#endif
-
-/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */
-#if defined(__FreeBSD_cc_version) && __FreeBSD_cc_version >= 300001 && \
-    defined(__GNUC__) && !defined(__INTEL_COMPILER)
-#define	__printf0like(fmtarg, firstvararg) \
-	    __attribute__((__format__ (__printf0__, fmtarg, firstvararg)))
-#else
-#define	__printf0like(fmtarg, firstvararg)
-#endif
-
-#if defined(__GNUC__) || defined(__INTEL_COMPILER)
-#ifndef __INTEL_COMPILER
-#define	__strong_reference(sym,aliassym)	\
-	extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))
-#endif
-#ifdef __ELF__
-#ifdef __STDC__
-#define	__weak_reference(sym,alias)	\
-	__asm__(".weak " #alias);	\
-	__asm__(".equ "  #alias ", " #sym)
-#define	__warn_references(sym,msg)	\
-	__asm__(".section .gnu.warning." #sym);	\
-	__asm__(".asciz \"" msg "\"");	\
-	__asm__(".previous")
-#define	__sym_compat(sym,impl,verid)	\
-	__asm__(".symver " #impl ", " #sym "@" #verid)
-#define	__sym_default(sym,impl,verid)	\
-	__asm__(".symver " #impl ", " #sym "@@" #verid)
-#else
-#define	__weak_reference(sym,alias)	\
-	__asm__(".weak alias");		\
-	__asm__(".equ alias, sym")
-#define	__warn_references(sym,msg)	\
-	__asm__(".section .gnu.warning.sym"); \
-	__asm__(".asciz \"msg\"");	\
-	__asm__(".previous")
-#define	__sym_compat(sym,impl,verid)	\
-	__asm__(".symver impl, sym@verid")
-#define	__sym_default(impl,sym,verid)	\
-	__asm__(".symver impl, sym@@verid")
-#endif	/* __STDC__ */
-#else	/* !__ELF__ */
-#ifdef __STDC__
-#define	__weak_reference(sym,alias)	\
-	__asm__(".stabs \"_" #alias "\",11,0,0,0");	\
-	__asm__(".stabs \"_" #sym "\",1,0,0,0")
-#define	__warn_references(sym,msg)	\
-	__asm__(".stabs \"" msg "\",30,0,0,0");		\
-	__asm__(".stabs \"_" #sym "\",1,0,0,0")
-#else
-#define	__weak_reference(sym,alias)	\
-	__asm__(".stabs \"_/**/alias\",11,0,0,0");	\
-	__asm__(".stabs \"_/**/sym\",1,0,0,0")
-#define	__warn_references(sym,msg)	\
-	__asm__(".stabs msg,30,0,0,0");			\
-	__asm__(".stabs \"_/**/sym\",1,0,0,0")
-#endif	/* __STDC__ */
-#endif	/* __ELF__ */
-#endif	/* __GNUC__ || __INTEL_COMPILER */
-
-#ifndef	__FBSDID
-#define	__FBSDID(s)	struct __hack
-#endif
-
-#ifndef	__RCSID
-#define	__RCSID(s)	struct __hack
-#endif
-
-#ifndef	__RCSID_SOURCE
-#define	__RCSID_SOURCE(s)	struct __hack
-#endif
-
-#ifndef	__SCCSID
-#define	__SCCSID(s)	struct __hack
-#endif
-
-#ifndef	__COPYRIGHT
-#define	__COPYRIGHT(s)	struct __hack
-#endif
-
-#ifndef	__DECONST
-#define	__DECONST(type, var)	((type)(__uintptr_t)(const void *)(var))
-#endif
-
-#ifndef	__DEVOLATILE
-#define	__DEVOLATILE(type, var)	((type)(__uintptr_t)(volatile void *)(var))
-#endif
-
-#ifndef	__DEQUALIFY
-#define	__DEQUALIFY(type, var)	((type)(__uintptr_t)(const volatile void *)(var))
-#endif
-
-/*-
- * The following definitions are an extension of the behavior originally
- * implemented in <sys/_posix.h>, but with a different level of granularity.
- * POSIX.1 requires that the macros we test be defined before any standard
- * header file is included.
- *
- * Here's a quick run-down of the versions:
- *  defined(_POSIX_SOURCE)		1003.1-1988
- *  _POSIX_C_SOURCE == 1		1003.1-1990
- *  _POSIX_C_SOURCE == 2		1003.2-1992 C Language Binding Option
- *  _POSIX_C_SOURCE == 199309		1003.1b-1993
- *  _POSIX_C_SOURCE == 199506		1003.1c-1995, 1003.1i-1995,
- *					and the omnibus ISO/IEC 9945-1: 1996
- *  _POSIX_C_SOURCE == 200112		1003.1-2001
- *  _POSIX_C_SOURCE == 200809		1003.1-2008
- *
- * In addition, the X/Open Portability Guide, which is now the Single UNIX
- * Specification, defines a feature-test macro which indicates the version of
- * that specification, and which subsumes _POSIX_C_SOURCE.
- *
- * Our macros begin with two underscores to avoid namespace screwage.
- */
-
-/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */
-#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1
-#undef _POSIX_C_SOURCE		/* Probably illegal, but beyond caring now. */
-#define	_POSIX_C_SOURCE		199009
-#endif
-
-/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */
-#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2
-#undef _POSIX_C_SOURCE
-#define	_POSIX_C_SOURCE		199209
-#endif
-
-/* Deal with various X/Open Portability Guides and Single UNIX Spec. */
-#ifdef _XOPEN_SOURCE
-#if _XOPEN_SOURCE - 0 >= 700
-#define	__XSI_VISIBLE		700
-#undef _POSIX_C_SOURCE
-#define	_POSIX_C_SOURCE		200809
-#elif _XOPEN_SOURCE - 0 >= 600
-#define	__XSI_VISIBLE		600
-#undef _POSIX_C_SOURCE
-#define	_POSIX_C_SOURCE		200112
-#elif _XOPEN_SOURCE - 0 >= 500
-#define	__XSI_VISIBLE		500
-#undef _POSIX_C_SOURCE
-#define	_POSIX_C_SOURCE		199506
-#endif
-#endif
-
-/*
- * Deal with all versions of POSIX.  The ordering relative to the tests above is
- * important.
- */
-#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE)
-#define	_POSIX_C_SOURCE		198808
-#endif
-#ifdef _POSIX_C_SOURCE
-#if _POSIX_C_SOURCE >= 200809
-#define	__POSIX_VISIBLE		200809
-#define	__ISO_C_VISIBLE		1999
-#elif _POSIX_C_SOURCE >= 200112
-#define	__POSIX_VISIBLE		200112
-#define	__ISO_C_VISIBLE		1999
-#elif _POSIX_C_SOURCE >= 199506
-#define	__POSIX_VISIBLE		199506
-#define	__ISO_C_VISIBLE		1990
-#elif _POSIX_C_SOURCE >= 199309
-#define	__POSIX_VISIBLE		199309
-#define	__ISO_C_VISIBLE		1990
-#elif _POSIX_C_SOURCE >= 199209
-#define	__POSIX_VISIBLE		199209
-#define	__ISO_C_VISIBLE		1990
-#elif _POSIX_C_SOURCE >= 199009
-#define	__POSIX_VISIBLE		199009
-#define	__ISO_C_VISIBLE		1990
-#else
-#define	__POSIX_VISIBLE		198808
-#define	__ISO_C_VISIBLE		0
-#endif /* _POSIX_C_SOURCE */
-#else
-/*-
- * Deal with _ANSI_SOURCE:
- * If it is defined, and no other compilation environment is explicitly
- * requested, then define our internal feature-test macros to zero.  This
- * makes no difference to the preprocessor (undefined symbols in preprocessing
- * expressions are defined to have value zero), but makes it more convenient for
- * a test program to print out the values.
- *
- * If a program mistakenly defines _ANSI_SOURCE and some other macro such as
- * _POSIX_C_SOURCE, we will assume that it wants the broader compilation
- * environment (and in fact we will never get here).
- */
-#if defined(_ANSI_SOURCE)	/* Hide almost everything. */
-#define	__POSIX_VISIBLE		0
-#define	__XSI_VISIBLE		0
-#define	__BSD_VISIBLE		0
-#define	__ISO_C_VISIBLE		1990
-#elif defined(_C99_SOURCE)	/* Localism to specify strict C99 env. */
-#define	__POSIX_VISIBLE		0
-#define	__XSI_VISIBLE		0
-#define	__BSD_VISIBLE		0
-#define	__ISO_C_VISIBLE		1999
-#elif defined(_C11_SOURCE)	/* Localism to specify strict C11 env. */
-#define	__POSIX_VISIBLE		0
-#define	__XSI_VISIBLE		0
-#define	__BSD_VISIBLE		0
-#define	__ISO_C_VISIBLE		2011
-#elif defined(_GNU_SOURCE)	/* Everything and the kitchen sink. */
-#define	__POSIX_VISIBLE		200809
-#define	__XSI_VISIBLE		700
-#define	__BSD_VISIBLE		1
-#define	__ISO_C_VISIBLE		2011
-#define	__GNU_VISIBLE		1
-#else				/* Default: everything except __GNU_VISIBLE. */
-#define	__POSIX_VISIBLE		200809
-#define	__XSI_VISIBLE		700
-#define	__BSD_VISIBLE		1
-#define	__ISO_C_VISIBLE		2011
-#endif
-#endif
-
-#endif /* !_SYS_CDEFS_H_ */
diff --git a/tools/sdk/include/newlib/sys/config.h b/tools/sdk/include/newlib/sys/config.h
deleted file mode 100644
index b5adfe1025a..00000000000
--- a/tools/sdk/include/newlib/sys/config.h
+++ /dev/null
@@ -1,300 +0,0 @@
-#ifndef __SYS_CONFIG_H__
-#define __SYS_CONFIG_H__
-
-#include <machine/ieeefp.h>  /* floating point macros */
-#include <sys/features.h>	/* POSIX defs */
-
-#ifdef __aarch64__
-#define MALLOC_ALIGNMENT 16
-#endif
-
-/* exceptions first */
-#if defined(__H8500__) || defined(__W65__)
-#define __SMALL_BITFIELDS
-/* ???  This conditional is true for the h8500 and the w65, defining H8300
-   in those cases probably isn't the right thing to do.  */
-#define H8300 1
-#endif
-
-/* 16 bit integer machines */
-#if defined(__Z8001__) || defined(__Z8002__) || defined(__H8500__) || defined(__W65__) || defined (__mn10200__) || defined (__AVR__)
-
-#undef INT_MAX
-#undef UINT_MAX
-#define INT_MAX 32767
-#define UINT_MAX 65535
-#endif
-
-#if defined (__H8300__) || defined (__H8300H__) || defined(__H8300S__) || defined (__H8300SX__)
-#define __SMALL_BITFIELDS
-#define H8300 1
-#undef INT_MAX
-#undef UINT_MAX
-#define INT_MAX __INT_MAX__
-#define UINT_MAX (__INT_MAX__ * 2U + 1)
-#endif
-
-#if (defined(__CR16__) || defined(__CR16C__) ||defined(__CR16CP__))
-#ifndef __INT32__
-#define __SMALL_BITFIELDS      
-#undef INT_MAX
-#undef UINT_MAX
-#define INT_MAX 32767
-#define UINT_MAX (__INT_MAX__ * 2U + 1)
-#else /* INT32 */
-#undef INT_MAX
-#undef UINT_MAX
-#define INT_MAX 2147483647
-#define UINT_MAX (__INT_MAX__ * 2U + 1)
-#endif /* INT32 */
-
-#endif /* CR16C */
-
-#if defined (__xc16x__) || defined (__xc16xL__) || defined (__xc16xS__)
-#define __SMALL_BITFIELDS
-#endif
-
-#ifdef __W65__
-#define __SMALL_BITFIELDS
-#endif
-
-#if defined(__D10V__)
-#define __SMALL_BITFIELDS
-#undef INT_MAX
-#undef UINT_MAX
-#define INT_MAX __INT_MAX__
-#define UINT_MAX (__INT_MAX__ * 2U + 1)
-#define _POINTER_INT short
-#endif
-
-#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
-#undef INT_MAX
-#undef UINT_MAX
-#define INT_MAX __INT_MAX__
-#define UINT_MAX (__INT_MAX__ * 2U + 1)
-#define _POINTER_INT short
-#endif
-
-#if defined(__m68k__) || defined(__mc68000__)
-#define _READ_WRITE_RETURN_TYPE _ssize_t
-#endif
-
-#ifdef ___AM29K__
-#define _FLOAT_RET double
-#endif
-
-#ifdef __i386__
-#ifndef __unix__
-/* in other words, go32 */
-#define _FLOAT_RET double
-#endif
-#if defined(__linux__) || defined(__RDOS__)
-/* we want the reentrancy structure to be returned by a function */
-#define __DYNAMIC_REENT__
-#define HAVE_GETDATE
-#define _HAVE_SYSTYPES
-#define _READ_WRITE_RETURN_TYPE _ssize_t
-#define __LARGE64_FILES 1
-/* we use some glibc header files so turn on glibc large file feature */
-#define _LARGEFILE64_SOURCE 1
-#endif
-#endif
-
-#ifdef __mn10200__
-#define __SMALL_BITFIELDS
-#endif
-
-#ifdef __AVR__
-#define __SMALL_BITFIELDS
-#define _POINTER_INT short
-#endif
-
-#ifdef __v850
-#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__sda__))
-#endif
-
-/* For the PowerPC eabi, force the _impure_ptr to be in .sdata */
-#if defined(__PPC__)
-#if defined(_CALL_SYSV)
-#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__section__(".sdata")))
-#endif
-#ifdef __SPE__
-#define _LONG_DOUBLE double
-#endif
-#endif
-
-/* Configure small REENT structure for Xilinx MicroBlaze platforms */
-#if defined (__MICROBLAZE__)
-#ifndef _REENT_SMALL
-#define _REENT_SMALL
-#endif
-/* Xilinx XMK uses Unix98 mutex */
-#ifdef __XMK__
-#define _UNIX98_THREAD_MUTEX_ATTRIBUTES
-#endif
-#endif
-
-#if defined(__mips__) && !defined(__rtems__)
-#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__section__(".sdata")))
-#endif
-
-#ifdef __xstormy16__
-#define __SMALL_BITFIELDS
-#undef INT_MAX
-#undef UINT_MAX
-#define INT_MAX __INT_MAX__
-#define UINT_MAX (__INT_MAX__ * 2U + 1)
-#define MALLOC_ALIGNMENT 8
-#define _POINTER_INT short
-#define __BUFSIZ__ 16
-#define _REENT_SMALL
-#endif
-
-#if defined __MSP430__
-#ifndef _REENT_SMALL
-#define _REENT_SMALL
-#endif
-
-#define __SMALL_BITFIELDS
-
-#ifdef __MSP430X_LARGE__
-#define _POINTER_INT long
-#else
-#define _POINTER_INT int
-#endif
-#endif
-
-#ifdef __m32c__
-#define __SMALL_BITFIELDS
-#undef INT_MAX
-#undef UINT_MAX
-#define INT_MAX __INT_MAX__
-#define UINT_MAX (__INT_MAX__ * 2U + 1)
-#define MALLOC_ALIGNMENT 8
-#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
-#define _POINTER_INT short
-#else
-#define _POINTER_INT long
-#endif
-#define __BUFSIZ__ 16
-#define _REENT_SMALL
-#endif /* __m32c__ */
-
-#ifdef __SPU__
-#define MALLOC_ALIGNMENT 16
-#define __CUSTOM_FILE_IO__
-#endif
-
-#ifdef __XTENSA__
-#include <xtensa/config/core-isa.h>
-#define MALLOC_ALIGNMENT ((XCHAL_DATA_WIDTH) < 16 ? 16 : (XCHAL_DATA_WIDTH))
-/* esp8266-specific: shrink the default fd buffer size */
-#define __BUFSIZ__ 128
-#ifndef __DYNAMIC_REENT__
-#define __DYNAMIC_REENT__
-#endif
-#ifndef _REENT_SMALL
-#define _REENT_SMALL
-#endif
-#define HAVE_GETOPT
-#endif
-
-/* This block should be kept in sync with GCC's limits.h.  The point
-   of having these definitions here is to not include limits.h, which
-   would pollute the user namespace, while still using types of the
-   the correct widths when deciding how to define __int32_t and
-   __int64_t.  */
-#ifndef __INT_MAX__
-# ifdef INT_MAX
-#  define __INT_MAX__ INT_MAX
-# else
-#  define __INT_MAX__ 2147483647
-# endif
-#endif
-
-#ifndef __LONG_MAX__
-# ifdef LONG_MAX
-#  define __LONG_MAX__ LONG_MAX
-# else
-#  if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) \
-      || defined (__sparcv9)
-#   define __LONG_MAX__ 9223372036854775807L
-#  else
-#   define __LONG_MAX__ 2147483647L
-#  endif /* __alpha__ || sparc64 */
-# endif
-#endif
-/* End of block that should be kept in sync with GCC's limits.h.  */
-
-#ifndef _POINTER_INT
-#define _POINTER_INT long
-#endif
-
-#ifdef __frv__
-#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__section__(".sdata")))
-#endif
-#undef __RAND_MAX
-#if __INT_MAX__ == 32767
-#define __RAND_MAX 32767
-#else
-#define __RAND_MAX 0x7fffffff
-#endif
-
-#if defined(__CYGWIN__)
-#include <cygwin/config.h>
-#if !defined (__STRICT_ANSI__) || (__STDC_VERSION__ >= 199901L)
-#define __USE_XOPEN2K 1
-#endif
-#endif
-
-#if defined(__rtems__)
-#define __FILENAME_MAX__ 255
-#define _READ_WRITE_RETURN_TYPE _ssize_t
-#define __DYNAMIC_REENT__
-#define _REENT_GLOBAL_ATEXIT
-#endif
-
-#ifndef __EXPORT
-#define __EXPORT
-#endif
-
-#ifndef __IMPORT
-#define __IMPORT
-#endif
-
-/* Define return type of read/write routines.  In POSIX, the return type
-   for read()/write() is "ssize_t" but legacy newlib code has been using
-   "int" for some time.  If not specified, "int" is defaulted.  */
-#ifndef _READ_WRITE_RETURN_TYPE
-#define _READ_WRITE_RETURN_TYPE int
-#endif
-/* Define `count' parameter of read/write routines.  In POSIX, the `count'
-   parameter is "size_t" but legacy newlib code has been using "int" for some
-   time.  If not specified, "int" is defaulted.  */
-#ifndef _READ_WRITE_BUFSIZE_TYPE
-#define _READ_WRITE_BUFSIZE_TYPE int
-#endif
-
-#ifndef __WCHAR_MAX__
-#if __INT_MAX__ == 32767 || defined (_WIN32)
-#define __WCHAR_MAX__ 0xffffu
-#endif
-#endif
-
-/* See if small reent asked for at configuration time and
-   is not chosen by the platform by default.  */
-#ifdef _WANT_REENT_SMALL
-#ifndef _REENT_SMALL
-#define _REENT_SMALL
-#endif
-#endif
-
-/* If _MB_EXTENDED_CHARSETS_ALL is set, we want all of the extended
-   charsets.  The extended charsets add a few functions and a couple
-   of tables of a few K each. */
-#ifdef _MB_EXTENDED_CHARSETS_ALL
-#define _MB_EXTENDED_CHARSETS_ISO 1
-#define _MB_EXTENDED_CHARSETS_WINDOWS 1
-#endif
-
-#endif /* __SYS_CONFIG_H__ */
diff --git a/tools/sdk/include/newlib/sys/custom_file.h b/tools/sdk/include/newlib/sys/custom_file.h
deleted file mode 100644
index 96314fb9168..00000000000
--- a/tools/sdk/include/newlib/sys/custom_file.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#error System-specific custom_file.h is missing.
-
diff --git a/tools/sdk/include/newlib/sys/dir.h b/tools/sdk/include/newlib/sys/dir.h
deleted file mode 100644
index 220150dc952..00000000000
--- a/tools/sdk/include/newlib/sys/dir.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* BSD predecessor of POSIX.1 <dirent.h> and struct dirent */
-
-#ifndef _SYS_DIR_H_
-#define _SYS_DIR_H_
-
-#include <dirent.h>
-
-#define direct dirent
-
-#endif /*_SYS_DIR_H_*/
diff --git a/tools/sdk/include/newlib/sys/errno.h b/tools/sdk/include/newlib/sys/errno.h
deleted file mode 100644
index a72c37320a7..00000000000
--- a/tools/sdk/include/newlib/sys/errno.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/* errno is not a global variable, because that would make using it
-   non-reentrant.  Instead, its address is returned by the function
-   __errno.  */
-
-#ifndef _SYS_ERRNO_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-#define _SYS_ERRNO_H_
-
-#include <sys/reent.h>
-
-#ifndef _REENT_ONLY
-#define errno (*__errno())
-extern int *__errno _PARAMS ((void));
-#endif
-
-/* Please don't use these variables directly.
-   Use strerror instead. */
-extern __IMPORT _CONST char * _CONST _sys_errlist[];
-extern __IMPORT int _sys_nerr;
-#ifdef __CYGWIN__
-extern __IMPORT const char * const sys_errlist[];
-extern __IMPORT int sys_nerr;
-extern __IMPORT char *program_invocation_name;
-extern __IMPORT char *program_invocation_short_name;
-#endif
-
-#define __errno_r(ptr) ((ptr)->_errno)
-
-#define	EPERM 1		/* Not owner */
-#define	ENOENT 2	/* No such file or directory */
-#define	ESRCH 3		/* No such process */
-#define	EINTR 4		/* Interrupted system call */
-#define	EIO 5		/* I/O error */
-#define	ENXIO 6		/* No such device or address */
-#define	E2BIG 7		/* Arg list too long */
-#define	ENOEXEC 8	/* Exec format error */
-#define	EBADF 9		/* Bad file number */
-#define	ECHILD 10	/* No children */
-#define	EAGAIN 11	/* No more processes */
-#define	ENOMEM 12	/* Not enough space */
-#define	EACCES 13	/* Permission denied */
-#define	EFAULT 14	/* Bad address */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define	ENOTBLK 15	/* Block device required */
-#endif
-#define	EBUSY 16	/* Device or resource busy */
-#define	EEXIST 17	/* File exists */
-#define	EXDEV 18	/* Cross-device link */
-#define	ENODEV 19	/* No such device */
-#define	ENOTDIR 20	/* Not a directory */
-#define	EISDIR 21	/* Is a directory */
-#define	EINVAL 22	/* Invalid argument */
-#define	ENFILE 23	/* Too many open files in system */
-#define	EMFILE 24	/* File descriptor value too large */
-#define	ENOTTY 25	/* Not a character device */
-#define	ETXTBSY 26	/* Text file busy */
-#define	EFBIG 27	/* File too large */
-#define	ENOSPC 28	/* No space left on device */
-#define	ESPIPE 29	/* Illegal seek */
-#define	EROFS 30	/* Read-only file system */
-#define	EMLINK 31	/* Too many links */
-#define	EPIPE 32	/* Broken pipe */
-#define	EDOM 33		/* Mathematics argument out of domain of function */
-#define	ERANGE 34	/* Result too large */
-#define	ENOMSG 35	/* No message of desired type */
-#define	EIDRM 36	/* Identifier removed */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define	ECHRNG 37	/* Channel number out of range */
-#define	EL2NSYNC 38	/* Level 2 not synchronized */
-#define	EL3HLT 39	/* Level 3 halted */
-#define	EL3RST 40	/* Level 3 reset */
-#define	ELNRNG 41	/* Link number out of range */
-#define	EUNATCH 42	/* Protocol driver not attached */
-#define	ENOCSI 43	/* No CSI structure available */
-#define	EL2HLT 44	/* Level 2 halted */
-#endif
-#define	EDEADLK 45	/* Deadlock */
-#define	ENOLCK 46	/* No lock */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define EBADE 50	/* Invalid exchange */
-#define EBADR 51	/* Invalid request descriptor */
-#define EXFULL 52	/* Exchange full */
-#define ENOANO 53	/* No anode */
-#define EBADRQC 54	/* Invalid request code */
-#define EBADSLT 55	/* Invalid slot */
-#define EDEADLOCK 56	/* File locking deadlock error */
-#define EBFONT 57	/* Bad font file fmt */
-#endif
-#define ENOSTR 60	/* Not a stream */
-#define ENODATA 61	/* No data (for no delay io) */
-#define ETIME 62	/* Stream ioctl timeout */
-#define ENOSR 63	/* No stream resources */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define ENONET 64	/* Machine is not on the network */
-#define ENOPKG 65	/* Package not installed */
-#define EREMOTE 66	/* The object is remote */
-#endif
-#define ENOLINK 67	/* Virtual circuit is gone */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define EADV 68		/* Advertise error */
-#define ESRMNT 69	/* Srmount error */
-#define	ECOMM 70	/* Communication error on send */
-#endif
-#define EPROTO 71	/* Protocol error */
-#define	EMULTIHOP 74	/* Multihop attempted */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define	ELBIN 75	/* Inode is remote (not really error) */
-#define	EDOTDOT 76	/* Cross mount point (not really error) */
-#endif
-#define EBADMSG 77	/* Bad message */
-#define EFTYPE 79	/* Inappropriate file type or format */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define ENOTUNIQ 80	/* Given log. name not unique */
-#define EBADFD 81	/* f.d. invalid for this operation */
-#define EREMCHG 82	/* Remote address changed */
-#define ELIBACC 83	/* Can't access a needed shared lib */
-#define ELIBBAD 84	/* Accessing a corrupted shared lib */
-#define ELIBSCN 85	/* .lib section in a.out corrupted */
-#define ELIBMAX 86	/* Attempting to link in too many libs */
-#define ELIBEXEC 87	/* Attempting to exec a shared library */
-#endif
-#define ENOSYS 88	/* Function not implemented */
-#ifdef __CYGWIN__
-#define ENMFILE 89      /* No more files */
-#endif
-#define ENOTEMPTY 90	/* Directory not empty */
-#define ENAMETOOLONG 91	/* File or path name too long */
-#define ELOOP 92	/* Too many symbolic links */
-#define EOPNOTSUPP 95	/* Operation not supported on socket */
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#define ECONNRESET 104  /* Connection reset by peer */
-#define ENOBUFS 105	/* No buffer space available */
-#define EAFNOSUPPORT 106 /* Address family not supported by protocol family */
-#define EPROTOTYPE 107	/* Protocol wrong type for socket */
-#define ENOTSOCK 108	/* Socket operation on non-socket */
-#define ENOPROTOOPT 109	/* Protocol not available */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define ESHUTDOWN 110	/* Can't send after socket shutdown */
-#endif
-#define ECONNREFUSED 111	/* Connection refused */
-#define EADDRINUSE 112		/* Address already in use */
-#define ECONNABORTED 113	/* Software caused connection abort */
-#define ENETUNREACH 114		/* Network is unreachable */
-#define ENETDOWN 115		/* Network interface is not configured */
-#define ETIMEDOUT 116		/* Connection timed out */
-#define EHOSTDOWN 117		/* Host is down */
-#define EHOSTUNREACH 118	/* Host is unreachable */
-#define EINPROGRESS 119		/* Connection already in progress */
-#define EALREADY 120		/* Socket already connected */
-#define EDESTADDRREQ 121	/* Destination address required */
-#define EMSGSIZE 122		/* Message too long */
-#define EPROTONOSUPPORT 123	/* Unknown protocol */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define ESOCKTNOSUPPORT 124	/* Socket type not supported */
-#endif
-#define EADDRNOTAVAIL 125	/* Address not available */
-#define ENETRESET 126		/* Connection aborted by network */
-#define EISCONN 127		/* Socket is already connected */
-#define ENOTCONN 128		/* Socket is not connected */
-#define ETOOMANYREFS 129
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define EPROCLIM 130
-#define EUSERS 131
-#endif
-#define EDQUOT 132
-#define ESTALE 133
-#define ENOTSUP 134		/* Not supported */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define ENOMEDIUM 135   /* No medium (in tape drive) */
-#endif
-#ifdef __CYGWIN__
-#define ENOSHARE 136    /* No such host or network path */
-#define ECASECLASH 137  /* Filename exists with different case */
-#endif
-#define EILSEQ 138		/* Illegal byte sequence */
-#define EOVERFLOW 139	/* Value too large for defined data type */
-#define ECANCELED 140	/* Operation canceled */
-#define ENOTRECOVERABLE 141	/* State not recoverable */
-#define EOWNERDEAD 142	/* Previous owner died */
-#ifdef __LINUX_ERRNO_EXTENSIONS__
-#define ESTRPIPE 143	/* Streams pipe error */
-#endif
-#define EWOULDBLOCK EAGAIN	/* Operation would block */
-
-#define __ELASTERROR 2000	/* Users can add values starting here */
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _SYS_ERRNO_H */
diff --git a/tools/sdk/include/newlib/sys/fcntl.h b/tools/sdk/include/newlib/sys/fcntl.h
deleted file mode 100644
index be85f40c1b8..00000000000
--- a/tools/sdk/include/newlib/sys/fcntl.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _SYS_FCNTL_H_
-#define _SYS_FCNTL_H_
-#include <sys/_default_fcntl.h>
-#endif
diff --git a/tools/sdk/include/newlib/sys/features.h b/tools/sdk/include/newlib/sys/features.h
deleted file mode 100644
index 87f3314fd95..00000000000
--- a/tools/sdk/include/newlib/sys/features.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- *  Written by Joel Sherrill <joel@OARcorp.com>.
- *
- *  COPYRIGHT (c) 1989-2000.
- *
- *  On-Line Applications Research Corporation (OAR).
- *
- *  Permission to use, copy, modify, and distribute this software for any
- *  purpose without fee is hereby granted, provided that this entire notice
- *  is included in all copies of any software which is or includes a copy
- *  or modification of this software.
- *
- *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
- *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
- *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
- *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- *  $Id$
- */
-
-#ifndef _SYS_FEATURES_H
-#define _SYS_FEATURES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Macros to determine that newlib is being used.  Put in this header to 
- * be similar to where glibc stores its version of these macros.
- */
-#define __NEWLIB__  		2
-#define __NEWLIB_MINOR__  	1
-
-/* Macro to test version of GCC.  Returns 0 for non-GCC or too old GCC. */
-#ifndef __GNUC_PREREQ
-# if defined __GNUC__ && defined __GNUC_MINOR__
-#  define __GNUC_PREREQ(maj, min) \
-	((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
-# else
-#  define __GNUC_PREREQ(maj, min) 0
-# endif
-#endif /* __GNUC_PREREQ */
-/* Version with trailing underscores for BSD compatibility. */
-#define	__GNUC_PREREQ__(ma, mi)	__GNUC_PREREQ(ma, mi)
-
-/* RTEMS adheres to POSIX -- 1003.1b with some features from annexes.  */
-
-#ifdef __rtems__
-#define _POSIX_JOB_CONTROL     		1
-#define _POSIX_SAVED_IDS       		1
-#define _POSIX_VERSION			199309L
-#define _POSIX_ASYNCHRONOUS_IO		1
-#define _POSIX_FSYNC			1
-#define _POSIX_MAPPED_FILES		1
-#define _POSIX_MEMLOCK			1
-#define _POSIX_MEMLOCK_RANGE		1
-#define _POSIX_MEMORY_PROTECTION	1
-#define _POSIX_MESSAGE_PASSING		1
-#define _POSIX_MONOTONIC_CLOCK		200112L
-#define _POSIX_PRIORITIZED_IO		1
-#define _POSIX_PRIORITY_SCHEDULING	1
-#define _POSIX_REALTIME_SIGNALS		1
-#define _POSIX_SEMAPHORES		1
-/* #define _POSIX_SHARED_MEMORY_OBJECTS	1 */
-#define _POSIX_SYNCHRONIZED_IO		1
-#define _POSIX_TIMERS			1
-#define _POSIX_BARRIERS                 200112L
-#define _POSIX_READER_WRITER_LOCKS      200112L
-#define _POSIX_SPIN_LOCKS               200112L
-
-
-/* In P1003.1b but defined by drafts at least as early as P1003.1c/D10  */
-#define _POSIX_THREADS				1
-#define _POSIX_THREAD_ATTR_STACKADDR		1
-#define _POSIX_THREAD_ATTR_STACKSIZE		1
-#define _POSIX_THREAD_PRIORITY_SCHEDULING	1
-#define _POSIX_THREAD_PRIO_INHERIT		1
-#define _POSIX_THREAD_PRIO_PROTECT		1
-#define _POSIX_THREAD_PROCESS_SHARED		1
-#define _POSIX_THREAD_SAFE_FUNCTIONS		1
-
-/* P1003.4b/D8 defines the constants below this comment. */
-#define _POSIX_SPAWN				1
-#define _POSIX_TIMEOUTS				1
-#define _POSIX_CPUTIME				1
-#define _POSIX_THREAD_CPUTIME			1
-#define _POSIX_SPORADIC_SERVER			1
-#define _POSIX_THREAD_SPORADIC_SERVER		1
-#define _POSIX_DEVICE_CONTROL			1
-#define _POSIX_DEVCTL_DIRECTION			1
-#define _POSIX_INTERRUPT_CONTROL		1
-#define _POSIX_ADVISORY_INFO			1
-
-/* UNIX98 added some new pthread mutex attributes */
-#define _UNIX98_THREAD_MUTEX_ATTRIBUTES         1
-
-#endif
-
-/* XMK loosely adheres to POSIX -- 1003.1 */
-#ifdef __XMK__
-#define _POSIX_THREADS				1
-#define _POSIX_THREAD_PRIORITY_SCHEDULING	1
-#endif
-
-
-#ifdef __svr4__
-# define _POSIX_JOB_CONTROL     1
-# define _POSIX_SAVED_IDS       1
-# define _POSIX_VERSION 199009L
-#endif
-
-#ifdef __CYGWIN__
-
-#if !defined(__STRICT_ANSI__) || defined(__cplusplus) || __STDC_VERSION__ >= 199901L
-#define _POSIX_VERSION				200112L
-#define _POSIX2_VERSION				200112L
-#define _XOPEN_VERSION				   600
-
-#define _POSIX_ADVISORY_INFO			200112L
-/* #define _POSIX_ASYNCHRONOUS_IO		    -1 */
-/* #define _POSIX_BARRIERS			    -1 */
-#define _POSIX_CHOWN_RESTRICTED			     1
-#define _POSIX_CLOCK_SELECTION			200112L
-#define _POSIX_CPUTIME			    	200112L
-#define _POSIX_FSYNC				200112L
-#define _POSIX_IPV6				200112L
-#define _POSIX_JOB_CONTROL			     1
-#define _POSIX_MAPPED_FILES			200112L
-/* #define _POSIX_MEMLOCK			    -1 */
-#define _POSIX_MEMLOCK_RANGE			200112L
-#define _POSIX_MEMORY_PROTECTION		200112L
-#define _POSIX_MESSAGE_PASSING			200112L
-#define _POSIX_MONOTONIC_CLOCK			200112L
-#define _POSIX_NO_TRUNC				     1
-/* #define _POSIX_PRIORITIZED_IO		    -1 */
-#define _POSIX_PRIORITY_SCHEDULING		200112L
-#define _POSIX_RAW_SOCKETS			200112L
-#define _POSIX_READER_WRITER_LOCKS		200112L
-#define _POSIX_REALTIME_SIGNALS			200112L
-#define _POSIX_REGEXP				     1
-#define _POSIX_SAVED_IDS			     1
-#define _POSIX_SEMAPHORES			200112L
-#define _POSIX_SHARED_MEMORY_OBJECTS		200112L 
-#define _POSIX_SHELL				     1
-/* #define _POSIX_SPAWN				    -1 */
-#define _POSIX_SPIN_LOCKS			    200112L
-/* #define _POSIX_SPORADIC_SERVER		    -1 */
-#define _POSIX_SYNCHRONIZED_IO			200112L
-#define _POSIX_THREAD_ATTR_STACKADDR		200112L
-#define _POSIX_THREAD_ATTR_STACKSIZE		200112L
-#define _POSIX_THREAD_CPUTIME			200112L
-/* #define _POSIX_THREAD_PRIO_INHERIT		    -1 */
-/* #define _POSIX_THREAD_PRIO_PROTECT		    -1 */
-#define _POSIX_THREAD_PRIORITY_SCHEDULING	200112L
-#define _POSIX_THREAD_PROCESS_SHARED		200112L
-#define _POSIX_THREAD_SAFE_FUNCTIONS		200112L
-/* #define _POSIX_THREAD_SPORADIC_SERVER	    -1 */
-#define _POSIX_THREADS				200112L
-/* #define _POSIX_TIMEOUTS			    -1 */
-#define _POSIX_TIMERS				     1
-/* #define _POSIX_TRACE				    -1 */
-/* #define _POSIX_TRACE_EVENT_FILTER		    -1 */
-/* #define _POSIX_TRACE_INHERIT			    -1 */
-/* #define _POSIX_TRACE_LOG			    -1 */
-/* #define _POSIX_TYPED_MEMORY_OBJECTS		    -1 */
-#define _POSIX_VDISABLE				   '\0'
-#define _POSIX2_C_BIND				200112L
-#define _POSIX2_C_DEV				200112L
-#define _POSIX2_CHAR_TERM			200112L
-/* #define _POSIX2_FORT_DEV			    -1 */
-/* #define _POSIX2_FORT_RUN			    -1 */
-/* #define _POSIX2_LOCALEDEF			    -1 */
-/* #define _POSIX2_PBS				    -1 */
-/* #define _POSIX2_PBS_ACCOUNTING		    -1 */
-/* #define _POSIX2_PBS_CHECKPOINT		    -1 */
-/* #define _POSIX2_PBS_LOCATE			    -1 */
-/* #define _POSIX2_PBS_MESSAGE			    -1 */
-/* #define _POSIX2_PBS_TRACK			    -1 */
-#define _POSIX2_SW_DEV				200112L
-#define _POSIX2_UPE				200112L
-#define _POSIX_V6_ILP32_OFF32			    -1
-#ifdef __LP64__
-#define _POSIX_V6_ILP32_OFFBIG			    -1
-#define _POSIX_V6_LP64_OFF64			     1
-#define _POSIX_V6_LPBIG_OFFBIG			     1
-#else
-#define _POSIX_V6_ILP32_OFFBIG			     1
-#define _POSIX_V6_LP64_OFF64			    -1
-#define _POSIX_V6_LPBIG_OFFBIG			    -1
-#endif
-#define _XBS5_ILP32_OFF32			_POSIX_V6_ILP32_OFF32
-#define _XBS5_ILP32_OFFBIG			_POSIX_V6_ILP32_OFFBIG
-#define _XBS5_LP64_OFF64			_POSIX_V6_LP64_OFF64
-#define _XBS5_LPBIG_OFFBIG			_POSIX_V6_LPBIG_OFFBIG
-#define _XOPEN_CRYPT				     1
-#define _XOPEN_ENH_I18N				     1
-/* #define _XOPEN_LEGACY			    -1 */
-/* #define _XOPEN_REALTIME			    -1 */
-/* #define _XOPEN_REALTIME_THREADS		    -1 */
-#define _XOPEN_SHM				     1
-/* #define _XOPEN_STREAMS			    -1 */
-/* #define _XOPEN_UNIX				    -1 */
-
-#endif /* !__STRICT_ANSI__ || __cplusplus || __STDC_VERSION__ >= 199901L */
-
-/* The value corresponds to UNICODE version 4.0, which is the version
-   supported by XP.  Newlib supports 5.2 (2011) but so far Cygwin needs
-   the MS conversions for double-byte charsets. */
-#define __STDC_ISO_10646__ 200305L
-
-#endif /* __CYGWIN__ */
-
-/* ESP-IDF-specific: enable pthreads support */
-#ifdef __XTENSA__
-#define _POSIX_THREADS                          1
-#define _UNIX98_THREAD_MUTEX_ATTRIBUTES         1
-#endif
-
-/* Per the permission given in POSIX.1-2008 section 2.2.1, define
- * _POSIX_C_SOURCE if _XOPEN_SOURCE is defined and _POSIX_C_SOURCE is not.
- * (_XOPEN_SOURCE indicates that XSI extensions are desired by an application.)
- * This permission is first granted in 2008, but use it for older ones, also.
- * Allow for _XOPEN_SOURCE to be empty (from the earliest form of it, before it
- * was required to have specific values).
- */
-#if !defined(_POSIX_C_SOURCE)  &&  defined(_XOPEN_SOURCE) 
-  #if (_XOPEN_SOURCE - 0) == 700	/* POSIX.1-2008 */
-    #define _POSIX_C_SOURCE       200809L
-   #elif (_XOPEN_SOURCE - 0) == 600	/* POSIX.1-2001 or 2004 */
-    #define _POSIX_C_SOURCE       200112L
-   #elif (_XOPEN_SOURCE - 0) == 500	/* POSIX.1-1995 */
-    #define _POSIX_C_SOURCE       199506L
-   #elif (_XOPEN_SOURCE - 0) < 500	/* really old */
-    #define _POSIX_C_SOURCE       2
-  #endif
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _SYS_FEATURES_H */
diff --git a/tools/sdk/include/newlib/sys/file.h b/tools/sdk/include/newlib/sys/file.h
deleted file mode 100644
index be88c6a5ad6..00000000000
--- a/tools/sdk/include/newlib/sys/file.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright (c) 2005-2006 Tensilica Inc.  ALL RIGHTS RESERVED.
-
-   Redistribution and use in source and binary forms, with or without 
-   modification, are permitted provided that the following conditions are met: 
-
-   1. Redistributions of source code must retain the above copyright 
-      notice, this list of conditions and the following disclaimer.
-
-   2. Redistributions in binary form must reproduce the above copyright
-      notice, this list of conditions and the following disclaimer in the
-      documentation and/or other materials provided with the distribution.
-
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-   PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL TENSILICA
-   INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-   EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-   PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  */
-
-#include <sys/fcntl.h>
-
-/* Alternate names for values for the WHENCE argument to `lseek'.
-   These are the same as SEEK_SET, SEEK_CUR, and SEEK_END, respectively. */
-#ifndef L_SET
-#define L_SET   0       /* Seek from beginning of file.  */
-#define L_INCR  1       /* Seek from current position.  */
-#define L_XTND  2       /* Seek from end of file.  */
-#endif
diff --git a/tools/sdk/include/newlib/sys/iconvnls.h b/tools/sdk/include/newlib/sys/iconvnls.h
deleted file mode 100644
index 09ea1831634..00000000000
--- a/tools/sdk/include/newlib/sys/iconvnls.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2003-2004, Artem B. Bityuckiy.
- * Rights transferred to Franklin Electronic Publishers.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Funtions, macros, etc implimented in iconv library but used by other
- * NLS-related subsystems too.
- */
-#ifndef __SYS_ICONVNLS_H__
-#define __SYS_ICONVNLS_H__
-
-#include <_ansi.h>
-#include <reent.h>
-#include <wchar.h>
-#include <iconv.h>
-
-/* Iconv data path environment variable name */
-#define NLS_ENVVAR_NAME  "NLSPATH"
-/* Default NLSPATH value */
-#define ICONV_DEFAULT_NLSPATH "/usr/locale"
-/* Direction markers */
-#define ICONV_NLS_FROM 0
-#define ICONV_NLS_TO   1
-
-_VOID
-_EXFUN(_iconv_nls_get_state, (iconv_t cd, mbstate_t *ps, int direction));
-
-int
-_EXFUN(_iconv_nls_set_state, (iconv_t cd, mbstate_t *ps, int direction));
-
-int
-_EXFUN(_iconv_nls_is_stateful, (iconv_t cd, int direction));
-
-int
-_EXFUN(_iconv_nls_get_mb_cur_max, (iconv_t cd, int direction));
-
-size_t
-_EXFUN(_iconv_nls_conv, (struct _reent *rptr, iconv_t cd,
-                        _CONST char **inbuf, size_t *inbytesleft,
-                        char **outbuf, size_t *outbytesleft));
-
-_CONST char *
-_EXFUN(_iconv_nls_construct_filename, (struct _reent *rptr, _CONST char *file,
-                                      _CONST char *dir, _CONST char *ext));
-
-
-int
-_EXFUN(_iconv_nls_open, (struct _reent *rptr, _CONST char *encoding,
-                        iconv_t *towc, iconv_t *fromwc, int flag));
-
-char *
-_EXFUN(_iconv_resolve_encoding_name, (struct _reent *rptr, _CONST char *ca));
-
-#endif /* __SYS_ICONVNLS_H__ */
-
diff --git a/tools/sdk/include/newlib/sys/lock.h b/tools/sdk/include/newlib/sys/lock.h
deleted file mode 100644
index 0ff3475836f..00000000000
--- a/tools/sdk/include/newlib/sys/lock.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#ifndef _XTENSA_LOCK_H__
-#define _XTENSA_LOCK_H__
-
-/* generic lock implementation.
-
-   Weak linked stub _lock functions in lock.c, can be
-   replaced with a lock implementation at link time.
-
- */
-
-typedef int _lock_t;
-typedef _lock_t _LOCK_RECURSIVE_T;
-typedef _lock_t _LOCK_T;
-
-#include <_ansi.h>
-
-/* NOTE: some parts of newlib statically initialise locks via
-   __LOCK_INIT, some initialise at runtime via __lock_init. So need to
-   support possibility that a _lock_t is null during first call to
-   _lock_acquire or _lock_try_acquire.
-
-   Lock functions all take a pointer to the _lock_t entry, so the
-   value stored there can be manipulated.
-*/
-#define __LOCK_INIT(CLASS,NAME) CLASS _lock_t NAME = 0;
-#define __LOCK_INIT_RECURSIVE(CLASS,NAME) CLASS _lock_t NAME = 0;
-
-void _lock_init(_lock_t *lock);
-void _lock_init_recursive(_lock_t *lock);
-void _lock_close(_lock_t *lock);
-void _lock_close_recursive(_lock_t *lock);
-void _lock_acquire(_lock_t *lock);
-void _lock_acquire_recursive(_lock_t *lock);
-int _lock_try_acquire(_lock_t *lock);
-int _lock_try_acquire_recursive(_lock_t *lock);
-void _lock_release(_lock_t *lock);
-void _lock_release_recursive(_lock_t *lock);
-
-#define __lock_init(lock) _lock_init(&(lock))
-#define __lock_init_recursive(lock) _lock_init_recursive(&(lock))
-#define __lock_close(lock) _lock_close(&(lock))
-#define __lock_close_recursive(lock) _lock_close_recursive(&(lock))
-#define __lock_acquire(lock) _lock_acquire(&(lock))
-#define __lock_acquire_recursive(lock) _lock_acquire_recursive(&(lock))
-#define __lock_try_acquire(lock) _lock_try_acquire(&(lock))
-#define __lock_try_acquire_recursive(lock) _lock_try_acquire_recursive(&(lock))
-#define __lock_release(lock) _lock_release(&(lock))
-#define __lock_release_recursive(lock) _lock_release_recursive(&(lock))
-
-#endif /* _XTENSA_LOCK_H__ */
diff --git a/tools/sdk/include/newlib/sys/param.h b/tools/sdk/include/newlib/sys/param.h
deleted file mode 100644
index ef203d3ecff..00000000000
--- a/tools/sdk/include/newlib/sys/param.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* This is a dummy <sys/param.h> file, not customized for any
-   particular system.  If there is a param.h in libc/sys/SYSDIR/sys,
-   it will override this one.  */
-
-#ifndef _SYS_PARAM_H
-# define _SYS_PARAM_H
-
-#include <sys/config.h>
-#include <sys/syslimits.h>
-#include <machine/endian.h>
-#include <machine/param.h>
-
-#ifndef HZ
-# define HZ (60)
-#endif
-#ifndef NOFILE
-# define NOFILE	(60)
-#endif
-#ifndef PATHSIZE
-# define PATHSIZE (1024)
-#endif
-
-#define MAXPATHLEN PATH_MAX
-
-#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#define MIN(a,b) ((a) < (b) ? (a) : (b))
-
-#endif
diff --git a/tools/sdk/include/newlib/sys/poll.h b/tools/sdk/include/newlib/sys/poll.h
deleted file mode 100644
index 030da6bf480..00000000000
--- a/tools/sdk/include/newlib/sys/poll.h
+++ /dev/null
@@ -1,48 +0,0 @@
-// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_PLATFORM_SYS_POLL_H_
-#define _ESP_PLATFORM_SYS_POLL_H_
-
-#define POLLIN      (1u << 0)      /* data other than high-priority may be read without blocking */
-#define POLLRDNORM  (1u << 1)      /* normal data may be read without blocking */
-#define POLLRDBAND  (1u << 2)      /* priority data may be read without blocking */
-#define POLLPRI     (POLLRDBAND)   /* high-priority data may be read without blocking */
-// Note: POLLPRI is made equivalent to POLLRDBAND in order to fit all these events into one byte
-#define POLLOUT     (1u << 3)      /* normal data may be written without blocking */
-#define POLLWRNORM  (POLLOUT)      /* equivalent to POLLOUT */
-#define POLLWRBAND  (1u << 4)      /* priority data my be written */
-#define POLLERR     (1u << 5)      /* some poll error occurred */
-#define POLLHUP     (1u << 6)      /* file descriptor was "hung up" */
-#define POLLNVAL    (1u << 7)      /* the specified file descriptor is invalid */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct pollfd {
-    int fd;        /* The descriptor. */
-    short events;  /* The event(s) is/are specified here. */
-    short revents; /* Events found are returned here. */
-};
-
-typedef unsigned int nfds_t;
-
-int poll(struct pollfd *fds, nfds_t nfds, int timeout);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif // _ESP_PLATFORM_SYS_POLL_H_
diff --git a/tools/sdk/include/newlib/sys/queue.h b/tools/sdk/include/newlib/sys/queue.h
deleted file mode 100644
index 4bc7dac0efa..00000000000
--- a/tools/sdk/include/newlib/sys/queue.h
+++ /dev/null
@@ -1,691 +0,0 @@
-/*-
- * Copyright (c) 1991, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)queue.h	8.5 (Berkeley) 8/20/94
- * $FreeBSD$
- */
-
-#ifndef _SYS_QUEUE_H_
-#define	_SYS_QUEUE_H_
-
-#include <sys/cdefs.h>
-
-/*
- * This file defines four types of data structures: singly-linked lists,
- * singly-linked tail queues, lists and tail queues.
- *
- * A singly-linked list is headed by a single forward pointer. The elements
- * are singly linked for minimum space and pointer manipulation overhead at
- * the expense of O(n) removal for arbitrary elements. New elements can be
- * added to the list after an existing element or at the head of the list.
- * Elements being removed from the head of the list should use the explicit
- * macro for this purpose for optimum efficiency. A singly-linked list may
- * only be traversed in the forward direction.  Singly-linked lists are ideal
- * for applications with large datasets and few or no removals or for
- * implementing a LIFO queue.
- *
- * A singly-linked tail queue is headed by a pair of pointers, one to the
- * head of the list and the other to the tail of the list. The elements are
- * singly linked for minimum space and pointer manipulation overhead at the
- * expense of O(n) removal for arbitrary elements. New elements can be added
- * to the list after an existing element, at the head of the list, or at the
- * end of the list. Elements being removed from the head of the tail queue
- * should use the explicit macro for this purpose for optimum efficiency.
- * A singly-linked tail queue may only be traversed in the forward direction.
- * Singly-linked tail queues are ideal for applications with large datasets
- * and few or no removals or for implementing a FIFO queue.
- *
- * A list is headed by a single forward pointer (or an array of forward
- * pointers for a hash table header). The elements are doubly linked
- * so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before
- * or after an existing element or at the head of the list. A list
- * may be traversed in either direction.
- *
- * A tail queue is headed by a pair of pointers, one to the head of the
- * list and the other to the tail of the list. The elements are doubly
- * linked so that an arbitrary element can be removed without a need to
- * traverse the list. New elements can be added to the list before or
- * after an existing element, at the head of the list, or at the end of
- * the list. A tail queue may be traversed in either direction.
- *
- * For details on the use of these macros, see the queue(3) manual page.
- *
- *
- *				SLIST	LIST	STAILQ	TAILQ
- * _HEAD			+	+	+	+
- * _HEAD_INITIALIZER		+	+	+	+
- * _ENTRY			+	+	+	+
- * _INIT			+	+	+	+
- * _EMPTY			+	+	+	+
- * _FIRST			+	+	+	+
- * _NEXT			+	+	+	+
- * _PREV			-	+	-	+
- * _LAST			-	-	+	+
- * _FOREACH			+	+	+	+
- * _FOREACH_SAFE		+	+	+	+
- * _FOREACH_REVERSE		-	-	-	+
- * _FOREACH_REVERSE_SAFE	-	-	-	+
- * _INSERT_HEAD			+	+	+	+
- * _INSERT_BEFORE		-	+	-	+
- * _INSERT_AFTER		+	+	+	+
- * _INSERT_TAIL			-	-	+	+
- * _CONCAT			-	-	+	+
- * _REMOVE_AFTER		+	-	+	-
- * _REMOVE_HEAD			+	-	+	-
- * _REMOVE			+	+	+	+
- * _SWAP			+	+	+	+
- *
- */
-#ifdef QUEUE_MACRO_DEBUG
-/* Store the last 2 places the queue element or head was altered */
-struct qm_trace {
-	unsigned long	 lastline;
-	unsigned long	 prevline;
-	const char	*lastfile;
-	const char	*prevfile;
-};
-
-#define	TRACEBUF	struct qm_trace trace;
-#define	TRACEBUF_INITIALIZER	{ __FILE__, __LINE__, NULL, 0 } ,
-#define	TRASHIT(x)	do {(x) = (void *)-1;} while (0)
-#define	QMD_SAVELINK(name, link)	void **name = (void *)&(link)
-
-#define	QMD_TRACE_HEAD(head) do {					\
-	(head)->trace.prevline = (head)->trace.lastline;		\
-	(head)->trace.prevfile = (head)->trace.lastfile;		\
-	(head)->trace.lastline = __LINE__;				\
-	(head)->trace.lastfile = __FILE__;				\
-} while (0)
-
-#define	QMD_TRACE_ELEM(elem) do {					\
-	(elem)->trace.prevline = (elem)->trace.lastline;		\
-	(elem)->trace.prevfile = (elem)->trace.lastfile;		\
-	(elem)->trace.lastline = __LINE__;				\
-	(elem)->trace.lastfile = __FILE__;				\
-} while (0)
-
-#else
-#define	QMD_TRACE_ELEM(elem)
-#define	QMD_TRACE_HEAD(head)
-#define	QMD_SAVELINK(name, link)
-#define	TRACEBUF
-#define	TRACEBUF_INITIALIZER
-#define	TRASHIT(x)
-#endif	/* QUEUE_MACRO_DEBUG */
-
-/*
- * Singly-linked List declarations.
- */
-#define	SLIST_HEAD(name, type)						\
-struct name {								\
-	struct type *slh_first;	/* first element */			\
-}
-
-#define	SLIST_HEAD_INITIALIZER(head)					\
-	{ NULL }
-
-#define	SLIST_ENTRY(type)						\
-struct {								\
-	struct type *sle_next;	/* next element */			\
-}
-
-/*
- * Singly-linked List functions.
- */
-#define	SLIST_EMPTY(head)	((head)->slh_first == NULL)
-
-#define	SLIST_FIRST(head)	((head)->slh_first)
-
-#define	SLIST_FOREACH(var, head, field)					\
-	for ((var) = SLIST_FIRST((head));				\
-	    (var);							\
-	    (var) = SLIST_NEXT((var), field))
-
-#define	SLIST_FOREACH_SAFE(var, head, field, tvar)			\
-	for ((var) = SLIST_FIRST((head));				\
-	    (var) && ((tvar) = SLIST_NEXT((var), field), 1);		\
-	    (var) = (tvar))
-
-#define	SLIST_FOREACH_PREVPTR(var, varp, head, field)			\
-	for ((varp) = &SLIST_FIRST((head));				\
-	    ((var) = *(varp)) != NULL;					\
-	    (varp) = &SLIST_NEXT((var), field))
-
-#define	SLIST_INIT(head) do {						\
-	SLIST_FIRST((head)) = NULL;					\
-} while (0)
-
-#define	SLIST_INSERT_AFTER(slistelm, elm, field) do {			\
-	SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field);	\
-	SLIST_NEXT((slistelm), field) = (elm);				\
-} while (0)
-
-#define	SLIST_INSERT_HEAD(head, elm, field) do {			\
-	SLIST_NEXT((elm), field) = SLIST_FIRST((head));			\
-	SLIST_FIRST((head)) = (elm);					\
-} while (0)
-
-#define	SLIST_NEXT(elm, field)	((elm)->field.sle_next)
-
-#define	SLIST_REMOVE(head, elm, type, field) do {			\
-	QMD_SAVELINK(oldnext, (elm)->field.sle_next);			\
-	if (SLIST_FIRST((head)) == (elm)) {				\
-		SLIST_REMOVE_HEAD((head), field);			\
-	}								\
-	else {								\
-		struct type *curelm = SLIST_FIRST((head));		\
-		while (SLIST_NEXT(curelm, field) != (elm))		\
-			curelm = SLIST_NEXT(curelm, field);		\
-		SLIST_REMOVE_AFTER(curelm, field);			\
-	}								\
-	TRASHIT(*oldnext);						\
-} while (0)
-
-#define SLIST_REMOVE_AFTER(elm, field) do {				\
-	SLIST_NEXT(elm, field) =					\
-	    SLIST_NEXT(SLIST_NEXT(elm, field), field);			\
-} while (0)
-
-#define	SLIST_REMOVE_HEAD(head, field) do {				\
-	SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field);	\
-} while (0)
-
-#define SLIST_SWAP(head1, head2, type) do {				\
-	struct type *swap_first = SLIST_FIRST(head1);			\
-	SLIST_FIRST(head1) = SLIST_FIRST(head2);			\
-	SLIST_FIRST(head2) = swap_first;				\
-} while (0)
-
-/*
- * Singly-linked Tail queue declarations.
- */
-#define	STAILQ_HEAD(name, type)						\
-struct name {								\
-	struct type *stqh_first;/* first element */			\
-	struct type **stqh_last;/* addr of last next element */		\
-}
-
-#define	STAILQ_HEAD_INITIALIZER(head)					\
-	{ NULL, &(head).stqh_first }
-
-#define	STAILQ_ENTRY(type)						\
-struct {								\
-	struct type *stqe_next;	/* next element */			\
-}
-
-/*
- * Singly-linked Tail queue functions.
- */
-#define	STAILQ_CONCAT(head1, head2) do {				\
-	if (!STAILQ_EMPTY((head2))) {					\
-		*(head1)->stqh_last = (head2)->stqh_first;		\
-		(head1)->stqh_last = (head2)->stqh_last;		\
-		STAILQ_INIT((head2));					\
-	}								\
-} while (0)
-
-#define	STAILQ_EMPTY(head)	((head)->stqh_first == NULL)
-
-#define	STAILQ_FIRST(head)	((head)->stqh_first)
-
-#define	STAILQ_FOREACH(var, head, field)				\
-	for((var) = STAILQ_FIRST((head));				\
-	   (var);							\
-	   (var) = STAILQ_NEXT((var), field))
-
-
-#define	STAILQ_FOREACH_SAFE(var, head, field, tvar)			\
-	for ((var) = STAILQ_FIRST((head));				\
-	    (var) && ((tvar) = STAILQ_NEXT((var), field), 1);		\
-	    (var) = (tvar))
-
-#define	STAILQ_INIT(head) do {						\
-	STAILQ_FIRST((head)) = NULL;					\
-	(head)->stqh_last = &STAILQ_FIRST((head));			\
-} while (0)
-
-#define	STAILQ_INSERT_AFTER(head, tqelm, elm, field) do {		\
-	if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
-		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
-	STAILQ_NEXT((tqelm), field) = (elm);				\
-} while (0)
-
-#define	STAILQ_INSERT_HEAD(head, elm, field) do {			\
-	if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL)	\
-		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
-	STAILQ_FIRST((head)) = (elm);					\
-} while (0)
-
-#define	STAILQ_INSERT_TAIL(head, elm, field) do {			\
-	STAILQ_NEXT((elm), field) = NULL;				\
-	*(head)->stqh_last = (elm);					\
-	(head)->stqh_last = &STAILQ_NEXT((elm), field);			\
-} while (0)
-
-#define	STAILQ_LAST(head, type, field)					\
-	(STAILQ_EMPTY((head)) ? NULL :					\
-	    __containerof((head)->stqh_last, struct type, field.stqe_next))
-
-#define	STAILQ_NEXT(elm, field)	((elm)->field.stqe_next)
-
-#define	STAILQ_REMOVE(head, elm, type, field) do {			\
-	QMD_SAVELINK(oldnext, (elm)->field.stqe_next);			\
-	if (STAILQ_FIRST((head)) == (elm)) {				\
-		STAILQ_REMOVE_HEAD((head), field);			\
-	}								\
-	else {								\
-		struct type *curelm = STAILQ_FIRST((head));		\
-		while (STAILQ_NEXT(curelm, field) != (elm))		\
-			curelm = STAILQ_NEXT(curelm, field);		\
-		STAILQ_REMOVE_AFTER(head, curelm, field);		\
-	}								\
-	TRASHIT(*oldnext);						\
-} while (0)
-
-#define STAILQ_REMOVE_AFTER(head, elm, field) do {			\
-	if ((STAILQ_NEXT(elm, field) =					\
-	     STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL)	\
-		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
-} while (0)
-
-#define	STAILQ_REMOVE_HEAD(head, field) do {				\
-	if ((STAILQ_FIRST((head)) =					\
-	     STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL)		\
-		(head)->stqh_last = &STAILQ_FIRST((head));		\
-} while (0)
-
-#define	STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do {			\
-	if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL)	\
-		(head)->stqh_last = &STAILQ_FIRST((head));		\
-} while (0)
-
-#define STAILQ_SWAP(head1, head2, type) do {				\
-	struct type *swap_first = STAILQ_FIRST(head1);			\
-	struct type **swap_last = (head1)->stqh_last;			\
-	STAILQ_FIRST(head1) = STAILQ_FIRST(head2);			\
-	(head1)->stqh_last = (head2)->stqh_last;			\
-	STAILQ_FIRST(head2) = swap_first;				\
-	(head2)->stqh_last = swap_last;					\
-	if (STAILQ_EMPTY(head1))					\
-		(head1)->stqh_last = &STAILQ_FIRST(head1);		\
-	if (STAILQ_EMPTY(head2))					\
-		(head2)->stqh_last = &STAILQ_FIRST(head2);		\
-} while (0)
-
-
-/*
- * List declarations.
- */
-#define	LIST_HEAD(name, type)						\
-struct name {								\
-	struct type *lh_first;	/* first element */			\
-}
-
-#define	LIST_HEAD_INITIALIZER(head)					\
-	{ NULL }
-
-#define	LIST_ENTRY(type)						\
-struct {								\
-	struct type *le_next;	/* next element */			\
-	struct type **le_prev;	/* address of previous next element */	\
-}
-
-/*
- * List functions.
- */
-
-#if (defined(_KERNEL) && defined(INVARIANTS))
-#define	QMD_LIST_CHECK_HEAD(head, field) do {				\
-	if (LIST_FIRST((head)) != NULL &&				\
-	    LIST_FIRST((head))->field.le_prev !=			\
-	     &LIST_FIRST((head)))					\
-		panic("Bad list head %p first->prev != head", (head));	\
-} while (0)
-
-#define	QMD_LIST_CHECK_NEXT(elm, field) do {				\
-	if (LIST_NEXT((elm), field) != NULL &&				\
-	    LIST_NEXT((elm), field)->field.le_prev !=			\
-	     &((elm)->field.le_next))					\
-	     	panic("Bad link elm %p next->prev != elm", (elm));	\
-} while (0)
-
-#define	QMD_LIST_CHECK_PREV(elm, field) do {				\
-	if (*(elm)->field.le_prev != (elm))				\
-		panic("Bad link elm %p prev->next != elm", (elm));	\
-} while (0)
-#else
-#define	QMD_LIST_CHECK_HEAD(head, field)
-#define	QMD_LIST_CHECK_NEXT(elm, field)
-#define	QMD_LIST_CHECK_PREV(elm, field)
-#endif /* (_KERNEL && INVARIANTS) */
-
-#define	LIST_EMPTY(head)	((head)->lh_first == NULL)
-
-#define	LIST_FIRST(head)	((head)->lh_first)
-
-#define	LIST_FOREACH(var, head, field)					\
-	for ((var) = LIST_FIRST((head));				\
-	    (var);							\
-	    (var) = LIST_NEXT((var), field))
-
-#define	LIST_FOREACH_SAFE(var, head, field, tvar)			\
-	for ((var) = LIST_FIRST((head));				\
-	    (var) && ((tvar) = LIST_NEXT((var), field), 1);		\
-	    (var) = (tvar))
-
-#define	LIST_INIT(head) do {						\
-	LIST_FIRST((head)) = NULL;					\
-} while (0)
-
-#define	LIST_INSERT_AFTER(listelm, elm, field) do {			\
-	QMD_LIST_CHECK_NEXT(listelm, field);				\
-	if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
-		LIST_NEXT((listelm), field)->field.le_prev =		\
-		    &LIST_NEXT((elm), field);				\
-	LIST_NEXT((listelm), field) = (elm);				\
-	(elm)->field.le_prev = &LIST_NEXT((listelm), field);		\
-} while (0)
-
-#define	LIST_INSERT_BEFORE(listelm, elm, field) do {			\
-	QMD_LIST_CHECK_PREV(listelm, field);				\
-	(elm)->field.le_prev = (listelm)->field.le_prev;		\
-	LIST_NEXT((elm), field) = (listelm);				\
-	*(listelm)->field.le_prev = (elm);				\
-	(listelm)->field.le_prev = &LIST_NEXT((elm), field);		\
-} while (0)
-
-#define	LIST_INSERT_HEAD(head, elm, field) do {				\
-	QMD_LIST_CHECK_HEAD((head), field);				\
-	if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL)	\
-		LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
-	LIST_FIRST((head)) = (elm);					\
-	(elm)->field.le_prev = &LIST_FIRST((head));			\
-} while (0)
-
-#define	LIST_NEXT(elm, field)	((elm)->field.le_next)
-
-#define	LIST_PREV(elm, head, type, field)				\
-	((elm)->field.le_prev == &LIST_FIRST((head)) ? NULL :		\
-	    __containerof((elm)->field.le_prev, struct type, field.le_next))
-
-#define	LIST_REMOVE(elm, field) do {					\
-	QMD_SAVELINK(oldnext, (elm)->field.le_next);			\
-	QMD_SAVELINK(oldprev, (elm)->field.le_prev);			\
-	QMD_LIST_CHECK_NEXT(elm, field);				\
-	QMD_LIST_CHECK_PREV(elm, field);				\
-	if (LIST_NEXT((elm), field) != NULL)				\
-		LIST_NEXT((elm), field)->field.le_prev = 		\
-		    (elm)->field.le_prev;				\
-	*(elm)->field.le_prev = LIST_NEXT((elm), field);		\
-	TRASHIT(*oldnext);						\
-	TRASHIT(*oldprev);						\
-} while (0)
-
-#define LIST_SWAP(head1, head2, type, field) do {			\
-	struct type *swap_tmp = LIST_FIRST((head1));			\
-	LIST_FIRST((head1)) = LIST_FIRST((head2));			\
-	LIST_FIRST((head2)) = swap_tmp;					\
-	if ((swap_tmp = LIST_FIRST((head1))) != NULL)			\
-		swap_tmp->field.le_prev = &LIST_FIRST((head1));		\
-	if ((swap_tmp = LIST_FIRST((head2))) != NULL)			\
-		swap_tmp->field.le_prev = &LIST_FIRST((head2));		\
-} while (0)
-
-/*
- * Tail queue declarations.
- */
-#define	TAILQ_HEAD(name, type)						\
-struct name {								\
-	struct type *tqh_first;	/* first element */			\
-	struct type **tqh_last;	/* addr of last next element */		\
-	TRACEBUF							\
-}
-
-#define	TAILQ_HEAD_INITIALIZER(head)					\
-	{ NULL, &(head).tqh_first, TRACEBUF_INITIALIZER }
-
-#define	TAILQ_ENTRY(type)						\
-struct {								\
-	struct type *tqe_next;	/* next element */			\
-	struct type **tqe_prev;	/* address of previous next element */	\
-	TRACEBUF							\
-}
-
-/*
- * Tail queue functions.
- */
-#if (defined(_KERNEL) && defined(INVARIANTS))
-#define	QMD_TAILQ_CHECK_HEAD(head, field) do {				\
-	if (!TAILQ_EMPTY(head) &&					\
-	    TAILQ_FIRST((head))->field.tqe_prev !=			\
-	     &TAILQ_FIRST((head)))					\
-		panic("Bad tailq head %p first->prev != head", (head));	\
-} while (0)
-
-#define	QMD_TAILQ_CHECK_TAIL(head, field) do {				\
-	if (*(head)->tqh_last != NULL)					\
-	    	panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); 	\
-} while (0)
-
-#define	QMD_TAILQ_CHECK_NEXT(elm, field) do {				\
-	if (TAILQ_NEXT((elm), field) != NULL &&				\
-	    TAILQ_NEXT((elm), field)->field.tqe_prev !=			\
-	     &((elm)->field.tqe_next))					\
-		panic("Bad link elm %p next->prev != elm", (elm));	\
-} while (0)
-
-#define	QMD_TAILQ_CHECK_PREV(elm, field) do {				\
-	if (*(elm)->field.tqe_prev != (elm))				\
-		panic("Bad link elm %p prev->next != elm", (elm));	\
-} while (0)
-#else
-#define	QMD_TAILQ_CHECK_HEAD(head, field)
-#define	QMD_TAILQ_CHECK_TAIL(head, headname)
-#define	QMD_TAILQ_CHECK_NEXT(elm, field)
-#define	QMD_TAILQ_CHECK_PREV(elm, field)
-#endif /* (_KERNEL && INVARIANTS) */
-
-#define	TAILQ_CONCAT(head1, head2, field) do {				\
-	if (!TAILQ_EMPTY(head2)) {					\
-		*(head1)->tqh_last = (head2)->tqh_first;		\
-		(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last;	\
-		(head1)->tqh_last = (head2)->tqh_last;			\
-		TAILQ_INIT((head2));					\
-		QMD_TRACE_HEAD(head1);					\
-		QMD_TRACE_HEAD(head2);					\
-	}								\
-} while (0)
-
-#define	TAILQ_EMPTY(head)	((head)->tqh_first == NULL)
-
-#define	TAILQ_FIRST(head)	((head)->tqh_first)
-
-#define	TAILQ_FOREACH(var, head, field)					\
-	for ((var) = TAILQ_FIRST((head));				\
-	    (var);							\
-	    (var) = TAILQ_NEXT((var), field))
-
-#define	TAILQ_FOREACH_SAFE(var, head, field, tvar)			\
-	for ((var) = TAILQ_FIRST((head));				\
-	    (var) && ((tvar) = TAILQ_NEXT((var), field), 1);		\
-	    (var) = (tvar))
-
-#define	TAILQ_FOREACH_REVERSE(var, head, headname, field)		\
-	for ((var) = TAILQ_LAST((head), headname);			\
-	    (var);							\
-	    (var) = TAILQ_PREV((var), headname, field))
-
-#define	TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar)	\
-	for ((var) = TAILQ_LAST((head), headname);			\
-	    (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1);	\
-	    (var) = (tvar))
-
-#define	TAILQ_INIT(head) do {						\
-	TAILQ_FIRST((head)) = NULL;					\
-	(head)->tqh_last = &TAILQ_FIRST((head));			\
-	QMD_TRACE_HEAD(head);						\
-} while (0)
-
-#define	TAILQ_INSERT_AFTER(head, listelm, elm, field) do {		\
-	QMD_TAILQ_CHECK_NEXT(listelm, field);				\
-	if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
-		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
-		    &TAILQ_NEXT((elm), field);				\
-	else {								\
-		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
-		QMD_TRACE_HEAD(head);					\
-	}								\
-	TAILQ_NEXT((listelm), field) = (elm);				\
-	(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field);		\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-	QMD_TRACE_ELEM(&listelm->field);				\
-} while (0)
-
-#define	TAILQ_INSERT_BEFORE(listelm, elm, field) do {			\
-	QMD_TAILQ_CHECK_PREV(listelm, field);				\
-	(elm)->field.tqe_prev = (listelm)->field.tqe_prev;		\
-	TAILQ_NEXT((elm), field) = (listelm);				\
-	*(listelm)->field.tqe_prev = (elm);				\
-	(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field);		\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-	QMD_TRACE_ELEM(&listelm->field);				\
-} while (0)
-
-#define	TAILQ_INSERT_HEAD(head, elm, field) do {			\
-	QMD_TAILQ_CHECK_HEAD(head, field);				\
-	if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL)	\
-		TAILQ_FIRST((head))->field.tqe_prev =			\
-		    &TAILQ_NEXT((elm), field);				\
-	else								\
-		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
-	TAILQ_FIRST((head)) = (elm);					\
-	(elm)->field.tqe_prev = &TAILQ_FIRST((head));			\
-	QMD_TRACE_HEAD(head);						\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-} while (0)
-
-#define	TAILQ_INSERT_TAIL(head, elm, field) do {			\
-	QMD_TAILQ_CHECK_TAIL(head, field);				\
-	TAILQ_NEXT((elm), field) = NULL;				\
-	(elm)->field.tqe_prev = (head)->tqh_last;			\
-	*(head)->tqh_last = (elm);					\
-	(head)->tqh_last = &TAILQ_NEXT((elm), field);			\
-	QMD_TRACE_HEAD(head);						\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-} while (0)
-
-#define	TAILQ_LAST(head, headname)					\
-	(*(((struct headname *)((head)->tqh_last))->tqh_last))
-
-#define	TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
-
-#define	TAILQ_PREV(elm, headname, field)				\
-	(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
-
-#define	TAILQ_REMOVE(head, elm, field) do {				\
-	QMD_SAVELINK(oldnext, (elm)->field.tqe_next);			\
-	QMD_SAVELINK(oldprev, (elm)->field.tqe_prev);			\
-	QMD_TAILQ_CHECK_NEXT(elm, field);				\
-	QMD_TAILQ_CHECK_PREV(elm, field);				\
-	if ((TAILQ_NEXT((elm), field)) != NULL)				\
-		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
-		    (elm)->field.tqe_prev;				\
-	else {								\
-		(head)->tqh_last = (elm)->field.tqe_prev;		\
-		QMD_TRACE_HEAD(head);					\
-	}								\
-	*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field);		\
-	TRASHIT(*oldnext);						\
-	TRASHIT(*oldprev);						\
-	QMD_TRACE_ELEM(&(elm)->field);					\
-} while (0)
-
-#define TAILQ_SWAP(head1, head2, type, field) do {			\
-	struct type *swap_first = (head1)->tqh_first;			\
-	struct type **swap_last = (head1)->tqh_last;			\
-	(head1)->tqh_first = (head2)->tqh_first;			\
-	(head1)->tqh_last = (head2)->tqh_last;				\
-	(head2)->tqh_first = swap_first;				\
-	(head2)->tqh_last = swap_last;					\
-	if ((swap_first = (head1)->tqh_first) != NULL)			\
-		swap_first->field.tqe_prev = &(head1)->tqh_first;	\
-	else								\
-		(head1)->tqh_last = &(head1)->tqh_first;		\
-	if ((swap_first = (head2)->tqh_first) != NULL)			\
-		swap_first->field.tqe_prev = &(head2)->tqh_first;	\
-	else								\
-		(head2)->tqh_last = &(head2)->tqh_first;		\
-} while (0)
-
-#ifdef _KERNEL
-
-/*
- * XXX insque() and remque() are an old way of handling certain queues.
- * They bogusly assumes that all queue heads look alike.
- */
-
-struct quehead {
-	struct quehead *qh_link;
-	struct quehead *qh_rlink;
-};
-
-#ifdef	__GNUC__
-
-static __inline void
-insque(void *a, void *b)
-{
-	struct quehead *element = (struct quehead *)a,
-		 *head = (struct quehead *)b;
-
-	element->qh_link = head->qh_link;
-	element->qh_rlink = head;
-	head->qh_link = element;
-	element->qh_link->qh_rlink = element;
-}
-
-static __inline void
-remque(void *a)
-{
-	struct quehead *element = (struct quehead *)a;
-
-	element->qh_link->qh_rlink = element->qh_rlink;
-	element->qh_rlink->qh_link = element->qh_link;
-	element->qh_rlink = 0;
-}
-
-#else /* !__GNUC__ */
-
-void	insque(void *a, void *b);
-void	remque(void *a);
-
-#endif /* __GNUC__ */
-
-#endif /* _KERNEL */
-
-#endif /* !_SYS_QUEUE_H_ */
diff --git a/tools/sdk/include/newlib/sys/random.h b/tools/sdk/include/newlib/sys/random.h
deleted file mode 100644
index afbf4dfd036..00000000000
--- a/tools/sdk/include/newlib/sys/random.h
+++ /dev/null
@@ -1,30 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __SYS_RANDOM__
-#define __SYS_RANDOM__
-
-#include <sys/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-ssize_t getrandom(void *buf, size_t buflen, unsigned int flags);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif //__SYS_RANDOM__
diff --git a/tools/sdk/include/newlib/sys/reent.h b/tools/sdk/include/newlib/sys/reent.h
deleted file mode 100644
index b35595a7d4a..00000000000
--- a/tools/sdk/include/newlib/sys/reent.h
+++ /dev/null
@@ -1,798 +0,0 @@
-/* This header file provides the reentrancy.  */
-
-/* WARNING: All identifiers here must begin with an underscore.  This file is
-   included by stdio.h and others and we therefore must only use identifiers
-   in the namespace allotted to us.  */
-
-#ifndef _SYS_REENT_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-#define _SYS_REENT_H_
-
-#include <_ansi.h>
-#include <stddef.h>
-#include <sys/_types.h>
-
-#define _NULL 0
-
-#ifndef __Long
-#if __LONG_MAX__ == 2147483647L
-#define __Long long
-typedef unsigned __Long __ULong;
-#elif __INT_MAX__ == 2147483647
-#define __Long int
-typedef unsigned __Long __ULong;
-#endif
-#endif
-
-#if !defined( __Long)
-#include <sys/types.h>
-#endif
-
-#ifndef __Long
-#define __Long __int32_t
-typedef __uint32_t __ULong;
-#endif
-
-struct _reent;
-
-/*
- * If _REENT_SMALL is defined, we make struct _reent as small as possible,
- * by having nearly everything possible allocated at first use.
- */
-
-struct _Bigint
-{
-  struct _Bigint *_next;
-  int _k, _maxwds, _sign, _wds;
-  __ULong _x[1];
-};
-
-/* needed by reentrant structure */
-struct __tm
-{
-  int   __tm_sec;
-  int   __tm_min;
-  int   __tm_hour;
-  int   __tm_mday;
-  int   __tm_mon;
-  int   __tm_year;
-  int   __tm_wday;
-  int   __tm_yday;
-  int   __tm_isdst;
-};
-
-/*
- * atexit() support.
- */
-
-#define	_ATEXIT_SIZE 32	/* must be at least 32 to guarantee ANSI conformance */
-
-struct _on_exit_args {
-	void *  _fnargs[_ATEXIT_SIZE];	        /* user fn args */
-	void *	_dso_handle[_ATEXIT_SIZE];
-	/* Bitmask is set if user function takes arguments.  */
-	__ULong _fntypes;           	        /* type of exit routine -
-				   Must have at least _ATEXIT_SIZE bits */
-	/* Bitmask is set if function was registered via __cxa_atexit.  */
-	__ULong _is_cxa;
-};
-
-#ifdef _REENT_SMALL
-struct _atexit {
-	struct	_atexit *_next;			/* next in list */
-	int	_ind;				/* next index in this table */
-	void	(*_fns[_ATEXIT_SIZE])(void);	/* the table itself */
-        struct _on_exit_args * _on_exit_args_ptr;
-};
-# define _ATEXIT_INIT {_NULL, 0, {_NULL}, _NULL}
-#else
-struct _atexit {
-	struct	_atexit *_next;			/* next in list */
-	int	_ind;				/* next index in this table */
-	/* Some entries may already have been called, and will be NULL.  */
-	void	(*_fns[_ATEXIT_SIZE])(void);	/* the table itself */
-        struct _on_exit_args _on_exit_args;
-};
-# define _ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}
-#endif
-
-#ifdef _REENT_GLOBAL_ATEXIT
-# define _REENT_INIT_ATEXIT
-#else
-# define _REENT_INIT_ATEXIT \
-  _NULL, _ATEXIT_INIT,
-#endif
-
-/*
- * Stdio buffers.
- *
- * This and __FILE are defined here because we need them for struct _reent,
- * but we don't want stdio.h included when stdlib.h is.
- */
-
-struct __sbuf {
-	unsigned char *_base;
-	int	_size;
-};
-
-/*
- * Stdio state variables.
- *
- * The following always hold:
- *
- *	if (_flags&(__SLBF|__SWR)) == (__SLBF|__SWR),
- *		_lbfsize is -_bf._size, else _lbfsize is 0
- *	if _flags&__SRD, _w is 0
- *	if _flags&__SWR, _r is 0
- *
- * This ensures that the getc and putc macros (or inline functions) never
- * try to write or read from a file that is in `read' or `write' mode.
- * (Moreover, they can, and do, automatically switch from read mode to
- * write mode, and back, on "r+" and "w+" files.)
- *
- * _lbfsize is used only to make the inline line-buffered output stream
- * code as compact as possible.
- *
- * _ub, _up, and _ur are used when ungetc() pushes back more characters
- * than fit in the current _bf, or when ungetc() pushes back a character
- * that does not match the previous one in _bf.  When this happens,
- * _ub._base becomes non-nil (i.e., a stream has ungetc() data iff
- * _ub._base!=NULL) and _up and _ur save the current values of _p and _r.
- */
-
-#ifdef _REENT_SMALL
-/*
- * struct __sFILE_fake is the start of a struct __sFILE, with only the
- * minimal fields allocated.  In __sinit() we really allocate the 3
- * standard streams, etc., and point away from this fake.
- */
-struct __sFILE_fake {
-  unsigned char *_p;	/* current position in (some) buffer */
-  int	_r;		/* read space left for getc() */
-  int	_w;		/* write space left for putc() */
-  short	_flags;		/* flags, below; this FILE is free if 0 */
-  short	_file;		/* fileno, if Unix descriptor, else -1 */
-  struct __sbuf _bf;	/* the buffer (at least 1 byte, if !NULL) */
-  int	_lbfsize;	/* 0 or -_bf._size, for inline putc */
-
-  struct _reent *_data;
-};
-
-/* Following is needed both in libc/stdio and libc/stdlib so we put it
- * here instead of libc/stdio/local.h where it was previously. */
-
-extern _VOID   _EXFUN(__sinit,(struct _reent *));
-
-# define _REENT_SMALL_CHECK_INIT(ptr)		\
-  do						\
-    {						\
-      if ((ptr) && !(ptr)->__sdidinit)		\
-	__sinit (ptr);				\
-    }						\
-  while (0)
-#else
-# define _REENT_SMALL_CHECK_INIT(ptr) /* nothing */
-#endif
-
-struct __sFILE {
-  unsigned char *_p;	/* current position in (some) buffer */
-  int	_r;		/* read space left for getc() */
-  int	_w;		/* write space left for putc() */
-  short	_flags;		/* flags, below; this FILE is free if 0 */
-  short	_file;		/* fileno, if Unix descriptor, else -1 */
-  struct __sbuf _bf;	/* the buffer (at least 1 byte, if !NULL) */
-  int	_lbfsize;	/* 0 or -_bf._size, for inline putc */
-
-#ifdef _REENT_SMALL
-  struct _reent *_data;
-#endif
-
-  /* operations */
-  _PTR	_cookie;	/* cookie passed to io functions */
-
-  _READ_WRITE_RETURN_TYPE _EXFNPTR(_read, (struct _reent *, _PTR,
-					   char *, _READ_WRITE_BUFSIZE_TYPE));
-  _READ_WRITE_RETURN_TYPE _EXFNPTR(_write, (struct _reent *, _PTR,
-					    const char *,
-					    _READ_WRITE_BUFSIZE_TYPE));
-  _fpos_t _EXFNPTR(_seek, (struct _reent *, _PTR, _fpos_t, int));
-  int _EXFNPTR(_close, (struct _reent *, _PTR));
-
-  /* separate buffer for long sequences of ungetc() */
-  struct __sbuf _ub;	/* ungetc buffer */
-  unsigned char *_up;	/* saved _p when _p is doing ungetc data */
-  int	_ur;		/* saved _r when _r is counting ungetc data */
-
-  /* tricks to meet minimum requirements even when malloc() fails */
-  unsigned char _ubuf[3];	/* guarantee an ungetc() buffer */
-  unsigned char _nbuf[1];	/* guarantee a getc() buffer */
-
-  /* separate buffer for fgetline() when line crosses buffer boundary */
-  struct __sbuf _lb;	/* buffer for fgetline() */
-
-  /* Unix stdio files get aligned to block boundaries on fseek() */
-  int	_blksize;	/* stat.st_blksize (may be != _bf._size) */
-  _off_t _offset;	/* current lseek offset */
-
-#ifndef _REENT_SMALL
-  struct _reent *_data;	/* Here for binary compatibility? Remove? */
-#endif
-
-#ifndef __SINGLE_THREAD__
-  _flock_t _lock;	/* for thread-safety locking */
-#endif
-  _mbstate_t _mbstate;	/* for wide char stdio functions. */
-  int   _flags2;        /* for future use */
-};
-
-#ifdef __CUSTOM_FILE_IO__
-
-/* Get custom _FILE definition.  */
-#include <sys/custom_file.h>
-
-#else /* !__CUSTOM_FILE_IO__ */
-#ifdef __LARGE64_FILES
-struct __sFILE64 {
-  unsigned char *_p;	/* current position in (some) buffer */
-  int	_r;		/* read space left for getc() */
-  int	_w;		/* write space left for putc() */
-  short	_flags;		/* flags, below; this FILE is free if 0 */
-  short	_file;		/* fileno, if Unix descriptor, else -1 */
-  struct __sbuf _bf;	/* the buffer (at least 1 byte, if !NULL) */
-  int	_lbfsize;	/* 0 or -_bf._size, for inline putc */
-
-  struct _reent *_data;
-
-  /* operations */
-  _PTR	_cookie;	/* cookie passed to io functions */
-
-  _READ_WRITE_RETURN_TYPE _EXFNPTR(_read, (struct _reent *, _PTR,
-					   char *, _READ_WRITE_BUFSIZE_TYPE));
-  _READ_WRITE_RETURN_TYPE _EXFNPTR(_write, (struct _reent *, _PTR,
-					    const char *,
-					    _READ_WRITE_BUFSIZE_TYPE));
-  _fpos_t _EXFNPTR(_seek, (struct _reent *, _PTR, _fpos_t, int));
-  int _EXFNPTR(_close, (struct _reent *, _PTR));
-
-  /* separate buffer for long sequences of ungetc() */
-  struct __sbuf _ub;	/* ungetc buffer */
-  unsigned char *_up;	/* saved _p when _p is doing ungetc data */
-  int	_ur;		/* saved _r when _r is counting ungetc data */
-
-  /* tricks to meet minimum requirements even when malloc() fails */
-  unsigned char _ubuf[3];	/* guarantee an ungetc() buffer */
-  unsigned char _nbuf[1];	/* guarantee a getc() buffer */
-
-  /* separate buffer for fgetline() when line crosses buffer boundary */
-  struct __sbuf _lb;	/* buffer for fgetline() */
-
-  /* Unix stdio files get aligned to block boundaries on fseek() */
-  int	_blksize;	/* stat.st_blksize (may be != _bf._size) */
-  int   _flags2;        /* for future use */
-
-  _off64_t _offset;     /* current lseek offset */
-  _fpos64_t _EXFNPTR(_seek64, (struct _reent *, _PTR, _fpos64_t, int));
-
-#ifndef __SINGLE_THREAD__
-  _flock_t _lock;	/* for thread-safety locking */
-#endif
-  _mbstate_t _mbstate;	/* for wide char stdio functions. */
-};
-typedef struct __sFILE64 __FILE;
-#else
-typedef struct __sFILE   __FILE;
-#endif /* __LARGE64_FILES */
-#endif /* !__CUSTOM_FILE_IO__ */
-
-struct _glue
-{
-  struct _glue *_next;
-  int _niobs;
-  __FILE *_iobs;
-};
-
-/*
- * rand48 family support
- *
- * Copyright (c) 1993 Martin Birgmeier
- * All rights reserved.
- *
- * You may redistribute unmodified or modified versions of this source
- * code provided that the above copyright notice and this and the
- * following conditions are retained.
- *
- * This software is provided ``as is'', and comes with no warranties
- * of any kind. I shall in no event be liable for anything that happens
- * to anyone/anything when using this software.
- */
-#define        _RAND48_SEED_0  (0x330e)
-#define        _RAND48_SEED_1  (0xabcd)
-#define        _RAND48_SEED_2  (0x1234)
-#define        _RAND48_MULT_0  (0xe66d)
-#define        _RAND48_MULT_1  (0xdeec)
-#define        _RAND48_MULT_2  (0x0005)
-#define        _RAND48_ADD     (0x000b)
-struct _rand48 {
-  unsigned short _seed[3];
-  unsigned short _mult[3];
-  unsigned short _add;
-#ifdef _REENT_SMALL
-  /* Put this in here as well, for good luck.  */
-  __extension__ unsigned long long _rand_next;
-#endif
-};
-
-/* How big the some arrays are.  */
-#define _REENT_EMERGENCY_SIZE 25
-#define _REENT_ASCTIME_SIZE 26
-#define _REENT_SIGNAL_SIZE 24
-
-/*
- * struct _reent
- *
- * This structure contains *all* globals needed by the library.
- * It's raison d'etre is to facilitate threads by making all library routines
- * reentrant.  IE: All state information is contained here.
- */
-
-#ifdef _REENT_SMALL
-
-struct _mprec
-{
-  /* used by mprec routines */
-  struct _Bigint *_result;
-  int _result_k;
-  struct _Bigint *_p5s;
-  struct _Bigint **_freelist;
-};
-
-
-struct _misc_reent
-{
-  /* miscellaneous reentrant data */
-  char *_strtok_last;
-  _mbstate_t _mblen_state;
-  _mbstate_t _wctomb_state;
-  _mbstate_t _mbtowc_state;
-  char _l64a_buf[8];
-  int _getdate_err;
-  _mbstate_t _mbrlen_state;
-  _mbstate_t _mbrtowc_state;
-  _mbstate_t _mbsrtowcs_state;
-  _mbstate_t _wcrtomb_state;
-  _mbstate_t _wcsrtombs_state;
-};
-
-/* This version of _reent is laid out with "int"s in pairs, to help
- * ports with 16-bit int's but 32-bit pointers, align nicely.  */
-struct _reent
-{
-  /* As an exception to the above put _errno first for binary
-     compatibility with non _REENT_SMALL targets.  */
-  int _errno;			/* local copy of errno */
-
-  /* FILE is a big struct and may change over time.  To try to achieve binary
-     compatibility with future versions, put stdin,stdout,stderr here.
-     These are pointers into member __sf defined below.  */
-  __FILE *_stdin, *_stdout, *_stderr;	/* XXX */
-
-  int  _inc;			/* used by tmpnam */
-
-  char *_emergency;
-
-  int __sdidinit;		/* 1 means stdio has been init'd */
-
-  int _current_category;	/* unused */
-  _CONST char *_current_locale;	/* unused */
-
-  struct _mprec *_mp;
-
-  void _EXFNPTR(__cleanup, (struct _reent *));
-
-  int _gamma_signgam;
-
-  /* used by some fp conversion routines */
-  int _cvtlen;			/* should be size_t */
-  char *_cvtbuf;
-
-  struct _rand48 *_r48;
-  struct __tm *_localtime_buf;
-  char *_asctime_buf;
-
-  /* signal info */
-  void (**_sig_func)(int);
-
-# ifndef _REENT_GLOBAL_ATEXIT
-  /* atexit stuff */
-  struct _atexit *_atexit;
-  struct _atexit _atexit0;
-# endif
-
-  struct _glue __sglue;			/* root of glue chain */
-  __FILE *__sf;			        /* file descriptors */
-  struct _misc_reent *_misc;            /* strtok, multibyte states */
-  char *_signal_buf;                    /* strsignal */
-};
-
-extern const struct __sFILE_fake __sf_fake_stdin;
-extern const struct __sFILE_fake __sf_fake_stdout;
-extern const struct __sFILE_fake __sf_fake_stderr;
-
-# define _REENT_INIT(var) \
-  { 0, \
-    (__FILE *)&__sf_fake_stdin, \
-    (__FILE *)&__sf_fake_stdout, \
-    (__FILE *)&__sf_fake_stderr, \
-    0, \
-    _NULL, \
-    0, \
-    0, \
-    "C", \
-    _NULL, \
-    _NULL, \
-    0, \
-    0, \
-    _NULL, \
-    _NULL, \
-    _NULL, \
-    _NULL, \
-    _NULL, \
-    _REENT_INIT_ATEXIT \
-    {_NULL, 0, _NULL}, \
-    _NULL, \
-    _NULL, \
-    _NULL \
-  }
-
-#ifndef ESP_PLATFORM
-#define _REENT_INIT_PTR(var) \
-  { memset((var), 0, sizeof(*(var))); \
-    (var)->_stdin = (__FILE *)&__sf_fake_stdin; \
-    (var)->_stdout = (__FILE *)&__sf_fake_stdout; \
-    (var)->_stderr = (__FILE *)&__sf_fake_stderr; \
-    (var)->_current_locale = "C"; \
-  }
-#else
-extern void esp_reent_init(struct _reent* reent);
-#define _REENT_INIT_PTR(var) esp_reent_init(var)
-#endif
-
-/* Only built the assert() calls if we are built with debugging.  */
-#if DEBUG
-#include <assert.h>
-#define __reent_assert(x) assert(x)
-#else
-#define __reent_assert(x) ((void)0)
-#endif
-
-#ifdef __CUSTOM_FILE_IO__
-#error Custom FILE I/O and _REENT_SMALL not currently supported.
-#endif
-
-/* Generic _REENT check macro.  */
-#define _REENT_CHECK(var, what, type, size, init) do { \
-  struct _reent *_r = (var); \
-  if (_r->what == NULL) { \
-    _r->what = (type)malloc(size); \
-    __reent_assert(_r->what); \
-    init; \
-  } \
-} while (0)
-
-#define _REENT_CHECK_TM(var) \
-  _REENT_CHECK(var, _localtime_buf, struct __tm *, sizeof *((var)->_localtime_buf), \
-    /* nothing */)
-
-#define _REENT_CHECK_ASCTIME_BUF(var) \
-  _REENT_CHECK(var, _asctime_buf, char *, _REENT_ASCTIME_SIZE, \
-    memset((var)->_asctime_buf, 0, _REENT_ASCTIME_SIZE))
-
-/* Handle the dynamically allocated rand48 structure. */
-#define _REENT_INIT_RAND48(var) do { \
-  struct _reent *_r = (var); \
-  _r->_r48->_seed[0] = _RAND48_SEED_0; \
-  _r->_r48->_seed[1] = _RAND48_SEED_1; \
-  _r->_r48->_seed[2] = _RAND48_SEED_2; \
-  _r->_r48->_mult[0] = _RAND48_MULT_0; \
-  _r->_r48->_mult[1] = _RAND48_MULT_1; \
-  _r->_r48->_mult[2] = _RAND48_MULT_2; \
-  _r->_r48->_add = _RAND48_ADD; \
-  _r->_r48->_rand_next = 1; \
-} while (0)
-#define _REENT_CHECK_RAND48(var) \
-  _REENT_CHECK(var, _r48, struct _rand48 *, sizeof *((var)->_r48), _REENT_INIT_RAND48((var)))
-
-#define _REENT_INIT_MP(var) do { \
-  struct _reent *_r = (var); \
-  _r->_mp->_result_k = 0; \
-  _r->_mp->_result = _r->_mp->_p5s = _NULL; \
-  _r->_mp->_freelist = _NULL; \
-} while (0)
-#define _REENT_CHECK_MP(var) \
-  _REENT_CHECK(var, _mp, struct _mprec *, sizeof *((var)->_mp), _REENT_INIT_MP(var))
-
-#define _REENT_CHECK_EMERGENCY(var) \
-  _REENT_CHECK(var, _emergency, char *, _REENT_EMERGENCY_SIZE, /* nothing */)
-
-#define _REENT_INIT_MISC(var) do { \
-  struct _reent *_r = (var); \
-  _r->_misc->_strtok_last = _NULL; \
-  _r->_misc->_mblen_state.__count = 0; \
-  _r->_misc->_mblen_state.__value.__wch = 0; \
-  _r->_misc->_wctomb_state.__count = 0; \
-  _r->_misc->_wctomb_state.__value.__wch = 0; \
-  _r->_misc->_mbtowc_state.__count = 0; \
-  _r->_misc->_mbtowc_state.__value.__wch = 0; \
-  _r->_misc->_mbrlen_state.__count = 0; \
-  _r->_misc->_mbrlen_state.__value.__wch = 0; \
-  _r->_misc->_mbrtowc_state.__count = 0; \
-  _r->_misc->_mbrtowc_state.__value.__wch = 0; \
-  _r->_misc->_mbsrtowcs_state.__count = 0; \
-  _r->_misc->_mbsrtowcs_state.__value.__wch = 0; \
-  _r->_misc->_wcrtomb_state.__count = 0; \
-  _r->_misc->_wcrtomb_state.__value.__wch = 0; \
-  _r->_misc->_wcsrtombs_state.__count = 0; \
-  _r->_misc->_wcsrtombs_state.__value.__wch = 0; \
-  _r->_misc->_l64a_buf[0] = '\0'; \
-  _r->_misc->_getdate_err = 0; \
-} while (0)
-#define _REENT_CHECK_MISC(var) \
-  _REENT_CHECK(var, _misc, struct _misc_reent *, sizeof *((var)->_misc), _REENT_INIT_MISC(var))
-
-#define _REENT_CHECK_SIGNAL_BUF(var) \
-  _REENT_CHECK(var, _signal_buf, char *, _REENT_SIGNAL_SIZE, /* nothing */)
-
-#define _REENT_SIGNGAM(ptr)	((ptr)->_gamma_signgam)
-#define _REENT_RAND_NEXT(ptr)	((ptr)->_r48->_rand_next)
-#define _REENT_RAND48_SEED(ptr)	((ptr)->_r48->_seed)
-#define _REENT_RAND48_MULT(ptr)	((ptr)->_r48->_mult)
-#define _REENT_RAND48_ADD(ptr)	((ptr)->_r48->_add)
-#define _REENT_MP_RESULT(ptr)	((ptr)->_mp->_result)
-#define _REENT_MP_RESULT_K(ptr)	((ptr)->_mp->_result_k)
-#define _REENT_MP_P5S(ptr)	((ptr)->_mp->_p5s)
-#define _REENT_MP_FREELIST(ptr)	((ptr)->_mp->_freelist)
-#define _REENT_ASCTIME_BUF(ptr)	((ptr)->_asctime_buf)
-#define _REENT_TM(ptr)		((ptr)->_localtime_buf)
-#define _REENT_EMERGENCY(ptr)	((ptr)->_emergency)
-#define _REENT_STRTOK_LAST(ptr)	((ptr)->_misc->_strtok_last)
-#define _REENT_MBLEN_STATE(ptr)	((ptr)->_misc->_mblen_state)
-#define _REENT_MBTOWC_STATE(ptr)((ptr)->_misc->_mbtowc_state)
-#define _REENT_WCTOMB_STATE(ptr)((ptr)->_misc->_wctomb_state)
-#define _REENT_MBRLEN_STATE(ptr) ((ptr)->_misc->_mbrlen_state)
-#define _REENT_MBRTOWC_STATE(ptr) ((ptr)->_misc->_mbrtowc_state)
-#define _REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_misc->_mbsrtowcs_state)
-#define _REENT_WCRTOMB_STATE(ptr) ((ptr)->_misc->_wcrtomb_state)
-#define _REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_misc->_wcsrtombs_state)
-#define _REENT_L64A_BUF(ptr)    ((ptr)->_misc->_l64a_buf)
-#define _REENT_GETDATE_ERR_P(ptr) (&((ptr)->_misc->_getdate_err))
-#define _REENT_SIGNAL_BUF(ptr)  ((ptr)->_signal_buf)
-
-#else /* !_REENT_SMALL */
-
-struct _reent
-{
-  int _errno;			/* local copy of errno */
-
-  /* FILE is a big struct and may change over time.  To try to achieve binary
-     compatibility with future versions, put stdin,stdout,stderr here.
-     These are pointers into member __sf defined below.  */
-  __FILE *_stdin, *_stdout, *_stderr;
-
-  int  _inc;			/* used by tmpnam */
-  char _emergency[_REENT_EMERGENCY_SIZE];
-
-  int _current_category;	/* used by setlocale */
-  _CONST char *_current_locale;
-
-  int __sdidinit;		/* 1 means stdio has been init'd */
-
-  void _EXFNPTR(__cleanup, (struct _reent *));
-
-  /* used by mprec routines */
-  struct _Bigint *_result;
-  int _result_k;
-  struct _Bigint *_p5s;
-  struct _Bigint **_freelist;
-
-  /* used by some fp conversion routines */
-  int _cvtlen;			/* should be size_t */
-  char *_cvtbuf;
-
-  union
-    {
-      struct
-        {
-          unsigned int _unused_rand;
-          char * _strtok_last;
-          char _asctime_buf[_REENT_ASCTIME_SIZE];
-          struct __tm _localtime_buf;
-          int _gamma_signgam;
-          __extension__ unsigned long long _rand_next;
-          struct _rand48 _r48;
-          _mbstate_t _mblen_state;
-          _mbstate_t _mbtowc_state;
-          _mbstate_t _wctomb_state;
-          char _l64a_buf[8];
-          char _signal_buf[_REENT_SIGNAL_SIZE];
-          int _getdate_err;
-          _mbstate_t _mbrlen_state;
-          _mbstate_t _mbrtowc_state;
-          _mbstate_t _mbsrtowcs_state;
-          _mbstate_t _wcrtomb_state;
-          _mbstate_t _wcsrtombs_state;
-	  int _h_errno;
-        } _reent;
-  /* Two next two fields were once used by malloc.  They are no longer
-     used. They are used to preserve the space used before so as to
-     allow addition of new reent fields and keep binary compatibility.   */
-      struct
-        {
-#define _N_LISTS 30
-          unsigned char * _nextf[_N_LISTS];
-          unsigned int _nmalloc[_N_LISTS];
-        } _unused;
-    } _new;
-
-# ifndef _REENT_GLOBAL_ATEXIT
-  /* atexit stuff */
-  struct _atexit *_atexit;	/* points to head of LIFO stack */
-  struct _atexit _atexit0;	/* one guaranteed table, required by ANSI */
-# endif
-
-  /* signal info */
-  void (**(_sig_func))(int);
-
-  /* These are here last so that __FILE can grow without changing the offsets
-     of the above members (on the off chance that future binary compatibility
-     would be broken otherwise).  */
-  struct _glue __sglue;		/* root of glue chain */
-  __FILE __sf[3];  		/* first three file descriptors */
-};
-
-#define _REENT_INIT(var) \
-  { 0, \
-    &(var).__sf[0], \
-    &(var).__sf[1], \
-    &(var).__sf[2], \
-    0, \
-    "", \
-    0, \
-    "C", \
-    0, \
-    _NULL, \
-    _NULL, \
-    0, \
-    _NULL, \
-    _NULL, \
-    0, \
-    _NULL, \
-    { \
-      { \
-        0, \
-        _NULL, \
-        "", \
-        {0, 0, 0, 0, 0, 0, 0, 0, 0}, \
-        0, \
-        1, \
-        { \
-          {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, \
-          {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, \
-          _RAND48_ADD \
-        }, \
-        {0, {0}}, \
-        {0, {0}}, \
-        {0, {0}}, \
-        "", \
-        "", \
-        0, \
-        {0, {0}}, \
-        {0, {0}}, \
-        {0, {0}}, \
-        {0, {0}}, \
-        {0, {0}} \
-      } \
-    }, \
-    _REENT_INIT_ATEXIT \
-    _NULL, \
-    {_NULL, 0, _NULL} \
-  }
-
-#define _REENT_INIT_PTR(var) \
-  { memset((var), 0, sizeof(*(var))); \
-    (var)->_stdin = &(var)->__sf[0]; \
-    (var)->_stdout = &(var)->__sf[1]; \
-    (var)->_stderr = &(var)->__sf[2]; \
-    (var)->_current_locale = "C"; \
-    (var)->_new._reent._rand_next = 1; \
-    (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; \
-    (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; \
-    (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; \
-    (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; \
-    (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; \
-    (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; \
-    (var)->_new._reent._r48._add = _RAND48_ADD; \
-  }
-
-#define _REENT_CHECK_RAND48(ptr)	/* nothing */
-#define _REENT_CHECK_MP(ptr)		/* nothing */
-#define _REENT_CHECK_TM(ptr)		/* nothing */
-#define _REENT_CHECK_ASCTIME_BUF(ptr)	/* nothing */
-#define _REENT_CHECK_EMERGENCY(ptr)	/* nothing */
-#define _REENT_CHECK_MISC(ptr)	        /* nothing */
-#define _REENT_CHECK_SIGNAL_BUF(ptr)	/* nothing */
-
-#define _REENT_SIGNGAM(ptr)	((ptr)->_new._reent._gamma_signgam)
-#define _REENT_RAND_NEXT(ptr)	((ptr)->_new._reent._rand_next)
-#define _REENT_RAND48_SEED(ptr)	((ptr)->_new._reent._r48._seed)
-#define _REENT_RAND48_MULT(ptr)	((ptr)->_new._reent._r48._mult)
-#define _REENT_RAND48_ADD(ptr)	((ptr)->_new._reent._r48._add)
-#define _REENT_MP_RESULT(ptr)	((ptr)->_result)
-#define _REENT_MP_RESULT_K(ptr)	((ptr)->_result_k)
-#define _REENT_MP_P5S(ptr)	((ptr)->_p5s)
-#define _REENT_MP_FREELIST(ptr)	((ptr)->_freelist)
-#define _REENT_ASCTIME_BUF(ptr)	((ptr)->_new._reent._asctime_buf)
-#define _REENT_TM(ptr)		(&(ptr)->_new._reent._localtime_buf)
-#define _REENT_EMERGENCY(ptr)	((ptr)->_emergency)
-#define _REENT_STRTOK_LAST(ptr)	((ptr)->_new._reent._strtok_last)
-#define _REENT_MBLEN_STATE(ptr)	((ptr)->_new._reent._mblen_state)
-#define _REENT_MBTOWC_STATE(ptr)((ptr)->_new._reent._mbtowc_state)
-#define _REENT_WCTOMB_STATE(ptr)((ptr)->_new._reent._wctomb_state)
-#define _REENT_MBRLEN_STATE(ptr)((ptr)->_new._reent._mbrlen_state)
-#define _REENT_MBRTOWC_STATE(ptr)((ptr)->_new._reent._mbrtowc_state)
-#define _REENT_MBSRTOWCS_STATE(ptr)((ptr)->_new._reent._mbsrtowcs_state)
-#define _REENT_WCRTOMB_STATE(ptr)((ptr)->_new._reent._wcrtomb_state)
-#define _REENT_WCSRTOMBS_STATE(ptr)((ptr)->_new._reent._wcsrtombs_state)
-#define _REENT_L64A_BUF(ptr)    ((ptr)->_new._reent._l64a_buf)
-#define _REENT_SIGNAL_BUF(ptr)  ((ptr)->_new._reent._signal_buf)
-#define _REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))
-
-#endif /* !_REENT_SMALL */
-
-/* This value is used in stdlib/misc.c.  reent/reent.c has to know it
-   as well to make sure the freelist is correctly free'd.  Therefore
-   we define it here, rather than in stdlib/misc.c, as before. */
-#define _Kmax (sizeof (size_t) << 3)
-
-/*
- * All references to struct _reent are via this pointer.
- * Internally, newlib routines that need to reference it should use _REENT.
- */
-
-#ifndef __ATTRIBUTE_IMPURE_PTR__
-#define __ATTRIBUTE_IMPURE_PTR__
-#endif
-
-#if !defined(__DYNAMIC_REENT__) || defined(__SINGLE_THREAD__)
-extern struct _reent *_impure_ptr __ATTRIBUTE_IMPURE_PTR__;
-#endif
-
-extern struct _reent *_global_impure_ptr __ATTRIBUTE_IMPURE_PTR__;
-
-void _reclaim_reent _PARAMS ((struct _reent *));
-
-/* #define _REENT_ONLY define this to get only reentrant routines */
-
-#if defined(__DYNAMIC_REENT__) && !defined(__SINGLE_THREAD__)
-#ifndef __getreent
-  struct _reent * _EXFUN(__getreent, (void));
-#endif
-# define _REENT (__getreent())
-#else /* __SINGLE_THREAD__ || !__DYNAMIC_REENT__ */
-# define _REENT _impure_ptr
-#endif /* __SINGLE_THREAD__ || !__DYNAMIC_REENT__ */
-
-#define _GLOBAL_REENT _global_impure_ptr
-
-#ifdef _REENT_GLOBAL_ATEXIT
-extern struct _atexit *_global_atexit; /* points to head of LIFO stack */
-# define _GLOBAL_ATEXIT _global_atexit
-#else
-# define _GLOBAL_ATEXIT (_GLOBAL_REENT->_atexit)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _SYS_REENT_H_ */
diff --git a/tools/sdk/include/newlib/sys/resource.h b/tools/sdk/include/newlib/sys/resource.h
deleted file mode 100644
index c35ac2a465e..00000000000
--- a/tools/sdk/include/newlib/sys/resource.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _SYS_RESOURCE_H_
-#define _SYS_RESOURCE_H_
-
-#include <sys/time.h>
-
-#define	RUSAGE_SELF	0		/* calling process */
-#define	RUSAGE_CHILDREN	-1		/* terminated child processes */
-
-struct rusage {
-  	struct timeval ru_utime;	/* user time used */
-	struct timeval ru_stime;	/* system time used */
-};
-
-int	_EXFUN(getrusage, (int, struct rusage*));
-
-#endif
-
diff --git a/tools/sdk/include/newlib/sys/sched.h b/tools/sdk/include/newlib/sys/sched.h
deleted file mode 100644
index 8554fc2b92e..00000000000
--- a/tools/sdk/include/newlib/sys/sched.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- *  Written by Joel Sherrill <joel@OARcorp.com>.
- *
- *  COPYRIGHT (c) 1989-2010.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  Permission to use, copy, modify, and distribute this software for any
- *  purpose without fee is hereby granted, provided that this entire notice
- *  is included in all copies of any software which is or includes a copy
- *  or modification of this software.
- *
- *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
- *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
- *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
- *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
- *
- *  $Id$
- */
-
-
-#ifndef _SYS_SCHED_H_
-#define _SYS_SCHED_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Scheduling Policies */
-/* Open Group Specifications Issue 6 */
-#if defined(__CYGWIN__)
-#define SCHED_OTHER    3
-#else
-#define SCHED_OTHER    0
-#endif
-
-#define SCHED_FIFO     1
-#define SCHED_RR       2
-
-#if defined(_POSIX_SPORADIC_SERVER)
-#define SCHED_SPORADIC 4
-#endif
-
-/* Scheduling Parameters */
-/* Open Group Specifications Issue 6 */
-
-struct sched_param {
-  int sched_priority;           /* Process execution scheduling priority */
-
-#if defined(_POSIX_SPORADIC_SERVER) || defined(_POSIX_THREAD_SPORADIC_SERVER)
-  int sched_ss_low_priority;    /* Low scheduling priority for sporadic */
-                                /*   server */
-  struct timespec sched_ss_repl_period;
-                                /* Replenishment period for sporadic server */
-  struct timespec sched_ss_init_budget;
-                               /* Initial budget for sporadic server */
-  int sched_ss_max_repl;       /* Maximum pending replenishments for */
-                               /* sporadic server */
-#endif
-};
-
-int sched_yield( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/* end of include file */
-
diff --git a/tools/sdk/include/newlib/sys/select.h b/tools/sdk/include/newlib/sys/select.h
deleted file mode 100644
index 199d48144d3..00000000000
--- a/tools/sdk/include/newlib/sys/select.h
+++ /dev/null
@@ -1,31 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_SYS_SELECT_H__
-#define __ESP_SYS_SELECT_H__
-
-#include <sys/types.h>
-#include <sys/time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds, struct timeval *timeout);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif //__ESP_SYS_SELECT_H__
diff --git a/tools/sdk/include/newlib/sys/signal.h b/tools/sdk/include/newlib/sys/signal.h
deleted file mode 100644
index a29f525c1f6..00000000000
--- a/tools/sdk/include/newlib/sys/signal.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/* sys/signal.h */
-
-#ifndef _SYS_SIGNAL_H
-#define _SYS_SIGNAL_H
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "_ansi.h"
-#include <sys/features.h>
-#include <sys/types.h>
-
-/* #ifndef __STRICT_ANSI__*/
-
-/* Cygwin defines it's own sigset_t in include/cygwin/signal.h */
-#ifndef __CYGWIN__
-typedef unsigned long sigset_t;
-#endif
-
-#if defined(__rtems__)
-
-#if defined(_POSIX_REALTIME_SIGNALS)
-
-/* sigev_notify values
-   NOTE: P1003.1c/D10, p. 34 adds SIGEV_THREAD.  */
-
-#define SIGEV_NONE   1  /* No asynchronous notification shall be delivered */
-                        /*   when the event of interest occurs. */
-#define SIGEV_SIGNAL 2  /* A queued signal, with an application defined */
-                        /*  value, shall be delivered when the event of */
-                        /*  interest occurs. */
-#define SIGEV_THREAD 3  /* A notification function shall be called to */
-                        /*   perform notification. */
-
-/*  Signal Generation and Delivery, P1003.1b-1993, p. 63
-    NOTE: P1003.1c/D10, p. 34 adds sigev_notify_function and
-          sigev_notify_attributes to the sigevent structure.  */
-
-union sigval {
-  int    sival_int;    /* Integer signal value */
-  void  *sival_ptr;    /* Pointer signal value */
-};
-
-struct sigevent {
-  int              sigev_notify;               /* Notification type */
-  int              sigev_signo;                /* Signal number */
-  union sigval     sigev_value;                /* Signal value */
-
-#if defined(_POSIX_THREADS)
-  void           (*sigev_notify_function)( union sigval );
-                                               /* Notification function */
-  pthread_attr_t  *sigev_notify_attributes;    /* Notification Attributes */
-#endif
-};
-
-/* Signal Actions, P1003.1b-1993, p. 64 */
-/* si_code values, p. 66 */
-
-#define SI_USER    1    /* Sent by a user. kill(), abort(), etc */
-#define SI_QUEUE   2    /* Sent by sigqueue() */
-#define SI_TIMER   3    /* Sent by expiration of a timer_settime() timer */
-#define SI_ASYNCIO 4    /* Indicates completion of asycnhronous IO */
-#define SI_MESGQ   5    /* Indicates arrival of a message at an empty queue */
-
-typedef struct {
-  int          si_signo;    /* Signal number */
-  int          si_code;     /* Cause of the signal */
-  union sigval si_value;    /* Signal value */
-} siginfo_t;
-#endif
-
-/*  3.3.8 Synchronously Accept a Signal, P1003.1b-1993, p. 76 */
-
-#define SA_NOCLDSTOP 0x1   /* Do not generate SIGCHLD when children stop */
-#define SA_SIGINFO   0x2   /* Invoke the signal catching function with */
-                           /*   three arguments instead of one. */
-#if __BSD_VISIBLE || __XSI_VISIBLE || __POSIX_VISIBLE >= 200112
-#define SA_ONSTACK   0x4   /* Signal delivery will be on a separate stack. */
-#endif
-
-/* struct sigaction notes from POSIX:
- *
- *  (1) Routines stored in sa_handler should take a single int as
- *      their argument although the POSIX standard does not require this.
- *      This is not longer true since at least POSIX.1-2008
- *  (2) The fields sa_handler and sa_sigaction may overlap, and a conforming
- *      application should not use both simultaneously.
- */
-
-typedef void (*_sig_func_ptr)(int);
-
-struct sigaction {
-  int         sa_flags;       /* Special flags to affect behavior of signal */
-  sigset_t    sa_mask;        /* Additional set of signals to be blocked */
-                              /*   during execution of signal-catching */
-                              /*   function. */
-  union {
-    _sig_func_ptr _handler;  /* SIG_DFL, SIG_IGN, or pointer to a function */
-#if defined(_POSIX_REALTIME_SIGNALS)
-    void      (*_sigaction)( int, siginfo_t *, void * );
-#endif
-  } _signal_handlers;
-};
-
-#define sa_handler    _signal_handlers._handler
-#if defined(_POSIX_REALTIME_SIGNALS)
-#define sa_sigaction  _signal_handlers._sigaction
-#endif
-
-#if __BSD_VISIBLE || __XSI_VISIBLE || __POSIX_VISIBLE >= 200112
-/*
- * Minimum and default signal stack constants. Allow for target overrides
- * from <sys/features.h>.
- */
-#ifndef	MINSIGSTKSZ
-#define	MINSIGSTKSZ	2048
-#endif
-#ifndef	SIGSTKSZ
-#define	SIGSTKSZ	8192
-#endif
-
-/*
- * Possible values for ss_flags in stack_t below.
- */
-#define	SS_ONSTACK	0x1
-#define	SS_DISABLE	0x2
-
-/*
- * Structure used in sigaltstack call.
- */
-typedef struct sigaltstack {
-  void     *ss_sp;    /* Stack base or pointer.  */
-  int       ss_flags; /* Flags.  */
-  size_t    ss_size;  /* Stack size.  */
-} stack_t;
-#endif
-
-#elif defined(__CYGWIN__)
-#include <cygwin/signal.h>
-#else
-#define SA_NOCLDSTOP 1  /* only value supported now for sa_flags */
-
-typedef void (*_sig_func_ptr)(int);
-
-struct sigaction 
-{
-	_sig_func_ptr sa_handler;
-	sigset_t sa_mask;
-	int sa_flags;
-};
-#endif /* defined(__rtems__) */
-
-#define SIG_SETMASK 0	/* set mask with sigprocmask() */
-#define SIG_BLOCK 1	/* set of signals to block */
-#define SIG_UNBLOCK 2	/* set of signals to, well, unblock */
-
-/* These depend upon the type of sigset_t, which right now 
-   is always a long.. They're in the POSIX namespace, but
-   are not ANSI. */
-#define sigaddset(what,sig) (*(what) |= (1<<(sig)), 0)
-#define sigdelset(what,sig) (*(what) &= ~(1<<(sig)), 0)
-#define sigemptyset(what)   (*(what) = 0, 0)
-#define sigfillset(what)    (*(what) = ~(0), 0)
-#define sigismember(what,sig) (((*(what)) & (1<<(sig))) != 0)
-
-int _EXFUN(sigprocmask, (int how, const sigset_t *set, sigset_t *oset));
-
-#if defined(_POSIX_THREADS)
-int _EXFUN(pthread_sigmask, (int how, const sigset_t *set, sigset_t *oset));
-#endif
-
-#if defined(__CYGWIN__) || defined(__rtems__)
-#undef sigaddset
-#undef sigdelset
-#undef sigemptyset
-#undef sigfillset
-#undef sigismember
-
-#ifdef _COMPILING_NEWLIB
-int _EXFUN(_kill, (pid_t, int));
-#endif /* _COMPILING_NEWLIB */
-#endif /* __CYGWIN__ || __rtems__ */
-#if defined(__CYGWIN__) || defined(__rtems__) || defined(__SPU__)
-int _EXFUN(kill, (pid_t, int));
-#endif /* __CYGWIN__ || __rtems__ || __SPU__ */
-#if defined(__CYGWIN__) || defined(__rtems__)
-int _EXFUN(killpg, (pid_t, int));
-int _EXFUN(sigaction, (int, const struct sigaction *, struct sigaction *));
-int _EXFUN(sigaddset, (sigset_t *, const int));
-int _EXFUN(sigdelset, (sigset_t *, const int));
-int _EXFUN(sigismember, (const sigset_t *, int));
-int _EXFUN(sigfillset, (sigset_t *));
-int _EXFUN(sigemptyset, (sigset_t *));
-int _EXFUN(sigpending, (sigset_t *));
-int _EXFUN(sigsuspend, (const sigset_t *));
-int _EXFUN(sigpause, (int));
-
-#ifdef __rtems__
-#if __BSD_VISIBLE || __XSI_VISIBLE || __POSIX_VISIBLE >= 200112
-int _EXFUN(sigaltstack, (const stack_t *__restrict, stack_t *__restrict));
-#endif
-#endif
-
-#if defined(_POSIX_THREADS)
-#ifdef __CYGWIN__
-#  ifndef _CYGWIN_TYPES_H
-#    error You need the winsup sources or a cygwin installation to compile the cygwin version of newlib.
-#  endif
-#endif
-int _EXFUN(pthread_kill, (pthread_t thread, int sig));
-#endif
-
-#if defined(_POSIX_REALTIME_SIGNALS)
-
-/*  3.3.8 Synchronously Accept a Signal, P1003.1b-1993, p. 76
-    NOTE: P1003.1c/D10, p. 39 adds sigwait().  */
-
-int _EXFUN(sigwaitinfo, (const sigset_t *set, siginfo_t *info));
-int _EXFUN(sigtimedwait,
-  (const sigset_t *set, siginfo_t *info, const struct timespec  *timeout)
-);
-int _EXFUN(sigwait, (const sigset_t *set, int *sig));
-
-/*  3.3.9 Queue a Signal to a Process, P1003.1b-1993, p. 78 */
-int _EXFUN(sigqueue, (pid_t pid, int signo, const union sigval value));
-
-#endif /* defined(_POSIX_REALTIME_SIGNALS) */
-
-#endif /* defined(__CYGWIN__) || defined(__rtems__) */
-
-/* #endif __STRICT_ANSI__ */
-
-#if defined(___AM29K__)
-/* These all need to be defined for ANSI C, but I don't think they are
-   meaningful.  */
-#define SIGABRT 1
-#define SIGFPE 1
-#define SIGILL 1
-#define SIGINT 1
-#define SIGSEGV 1
-#define SIGTERM 1
-/* These need to be defined for POSIX, and some others do too.  */
-#define SIGHUP 1
-#define SIGQUIT 1
-#define NSIG 2
-#elif defined(__GO32__)
-#define SIGINT  1
-#define SIGKILL 2
-#define SIGPIPE 3
-#define SIGFPE  4
-#define SIGHUP  5
-#define SIGTERM 6
-#define SIGSEGV 7
-#define SIGTSTP 8
-#define SIGQUIT 9
-#define SIGTRAP 10
-#define SIGILL  11
-#define SIGEMT  12
-#define SIGALRM 13
-#define SIGBUS  14
-#define SIGLOST 15
-#define SIGSTOP 16
-#define SIGABRT 17
-#define SIGUSR1	18
-#define SIGUSR2	19
-#define NSIG    20
-#elif !defined(SIGTRAP)
-#define	SIGHUP	1	/* hangup */
-#define	SIGINT	2	/* interrupt */
-#define	SIGQUIT	3	/* quit */
-#define	SIGILL	4	/* illegal instruction (not reset when caught) */
-#define	SIGTRAP	5	/* trace trap (not reset when caught) */
-#define	SIGIOT	6	/* IOT instruction */
-#define	SIGABRT 6	/* used by abort, replace SIGIOT in the future */
-#define	SIGEMT	7	/* EMT instruction */
-#define	SIGFPE	8	/* floating point exception */
-#define	SIGKILL	9	/* kill (cannot be caught or ignored) */
-#define	SIGBUS	10	/* bus error */
-#define	SIGSEGV	11	/* segmentation violation */
-#define	SIGSYS	12	/* bad argument to system call */
-#define	SIGPIPE	13	/* write on a pipe with no one to read it */
-#define	SIGALRM	14	/* alarm clock */
-#define	SIGTERM	15	/* software termination signal from kill */
-
-#if defined(__rtems__)
-#define	SIGURG	16	/* urgent condition on IO channel */
-#define	SIGSTOP	17	/* sendable stop signal not from tty */
-#define	SIGTSTP	18	/* stop signal from tty */
-#define	SIGCONT	19	/* continue a stopped process */
-#define	SIGCHLD	20	/* to parent on child stop or exit */
-#define	SIGCLD	20	/* System V name for SIGCHLD */
-#define	SIGTTIN	21	/* to readers pgrp upon background tty read */
-#define	SIGTTOU	22	/* like TTIN for output if (tp->t_local&LTOSTOP) */
-#define	SIGIO	23	/* input/output possible signal */
-#define	SIGPOLL	SIGIO	/* System V name for SIGIO */
-#define	SIGWINCH 24	/* window changed */
-#define	SIGUSR1 25	/* user defined signal 1 */
-#define	SIGUSR2 26	/* user defined signal 2 */
-
-/* Real-Time Signals Range, P1003.1b-1993, p. 61
-   NOTE: By P1003.1b-1993, this should be at least RTSIG_MAX
-         (which is a minimum of 8) signals.
- */
-#define SIGRTMIN 27
-#define SIGRTMAX 31
-#define __SIGFIRSTNOTRT SIGHUP
-#define __SIGLASTNOTRT  SIGUSR2
-
-#define NSIG	32      /* signal 0 implied */
-
-#elif defined(__svr4__)
-/* svr4 specifics. different signals above 15, and sigaction. */
-#define	SIGUSR1	16
-#define SIGUSR2	17
-#define SIGCLD	18
-#define	SIGPWR	19
-#define SIGWINCH 20
-#define	SIGPOLL	22	/* 20 for x.out binaries!!!! */
-#define	SIGSTOP	23	/* sendable stop signal not from tty */
-#define	SIGTSTP	24	/* stop signal from tty */
-#define	SIGCONT	25	/* continue a stopped process */
-#define	SIGTTIN	26	/* to readers pgrp upon background tty read */
-#define	SIGTTOU	27	/* like TTIN for output if (tp->t_local&LTOSTOP) */
-#define NSIG	28	
-#else
-#define	SIGURG	16	/* urgent condition on IO channel */
-#define	SIGSTOP	17	/* sendable stop signal not from tty */
-#define	SIGTSTP	18	/* stop signal from tty */
-#define	SIGCONT	19	/* continue a stopped process */
-#define	SIGCHLD	20	/* to parent on child stop or exit */
-#define	SIGCLD	20	/* System V name for SIGCHLD */
-#define	SIGTTIN	21	/* to readers pgrp upon background tty read */
-#define	SIGTTOU	22	/* like TTIN for output if (tp->t_local&LTOSTOP) */
-#define	SIGIO	23	/* input/output possible signal */
-#define	SIGPOLL	SIGIO	/* System V name for SIGIO */
-#define	SIGXCPU	24	/* exceeded CPU time limit */
-#define	SIGXFSZ	25	/* exceeded file size limit */
-#define	SIGVTALRM 26	/* virtual time alarm */
-#define	SIGPROF	27	/* profiling time alarm */
-#define	SIGWINCH 28	/* window changed */
-#define	SIGLOST 29	/* resource lost (eg, record-lock lost) */
-#define	SIGUSR1 30	/* user defined signal 1 */
-#define	SIGUSR2 31	/* user defined signal 2 */
-#define NSIG	32      /* signal 0 implied */
-#endif
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#ifndef _SIGNAL_H_
-/* Some applications take advantage of the fact that <sys/signal.h>
- * and <signal.h> are equivalent in glibc.  Allow for that here.  */
-#include <signal.h>
-#endif
-#endif /* _SYS_SIGNAL_H */
diff --git a/tools/sdk/include/newlib/sys/stat.h b/tools/sdk/include/newlib/sys/stat.h
deleted file mode 100644
index 11b9d8080f4..00000000000
--- a/tools/sdk/include/newlib/sys/stat.h
+++ /dev/null
@@ -1,192 +0,0 @@
-#ifndef	_SYS_STAT_H
-#define	_SYS_STAT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <_ansi.h>
-#include <time.h>
-#include <sys/cdefs.h>
-#include <sys/types.h>
-
-/* dj's stat defines _STAT_H_ */
-#ifndef _STAT_H_
-
-/* It is intended that the layout of this structure not change when the
-   sizes of any of the basic types change (short, int, long) [via a compile
-   time option].  */
-
-#ifdef __CYGWIN__
-#include <cygwin/stat.h>
-#ifdef _COMPILING_NEWLIB
-#define stat64 stat
-#endif
-#else
-struct	stat 
-{
-  dev_t		st_dev;
-  ino_t		st_ino;
-  mode_t	st_mode;
-  nlink_t	st_nlink;
-  uid_t		st_uid;
-  gid_t		st_gid;
-  dev_t		st_rdev;
-  off_t		st_size;
-#if defined(__rtems__)
-  struct timespec st_atim;
-  struct timespec st_mtim;
-  struct timespec st_ctim;
-  blksize_t     st_blksize;
-  blkcnt_t	st_blocks;
-#else
-  /* SysV/sco doesn't have the rest... But Solaris, eabi does.  */
-#if defined(__svr4__) && !defined(__PPC__) && !defined(__sun__)
-  time_t	st_atime;
-  time_t	st_mtime;
-  time_t	st_ctime;
-#else
-  time_t	st_atime;
-  long		st_spare1;
-  time_t	st_mtime;
-  long		st_spare2;
-  time_t	st_ctime;
-  long		st_spare3;
-  long		st_blksize;
-  long		st_blocks;
-  long	st_spare4[2];
-#endif
-#endif
-};
-
-#if defined(__rtems__)
-#define st_atime st_atim.tv_sec
-#define st_ctime st_ctim.tv_sec
-#define st_mtime st_mtim.tv_sec
-#endif
-
-#endif
-
-#define	_IFMT		0170000	/* type of file */
-#define		_IFDIR	0040000	/* directory */
-#define		_IFCHR	0020000	/* character special */
-#define		_IFBLK	0060000	/* block special */
-#define		_IFREG	0100000	/* regular */
-#define		_IFLNK	0120000	/* symbolic link */
-#define		_IFSOCK	0140000	/* socket */
-#define		_IFIFO	0010000	/* fifo */
-
-#define 	S_BLKSIZE  1024 /* size of a block */
-
-#define	S_ISUID		0004000	/* set user id on execution */
-#define	S_ISGID		0002000	/* set group id on execution */
-#define	S_ISVTX		0001000	/* save swapped text even after use */
-#ifndef	_POSIX_SOURCE
-#define	S_IREAD		0000400	/* read permission, owner */
-#define	S_IWRITE 	0000200	/* write permission, owner */
-#define	S_IEXEC		0000100	/* execute/search permission, owner */
-#define	S_ENFMT 	0002000	/* enforcement-mode locking */
-#endif	/* !_POSIX_SOURCE */
-
-#define	S_IFMT		_IFMT
-#define	S_IFDIR		_IFDIR
-#define	S_IFCHR		_IFCHR
-#define	S_IFBLK		_IFBLK
-#define	S_IFREG		_IFREG
-#define	S_IFLNK		_IFLNK
-#define	S_IFSOCK	_IFSOCK
-#define	S_IFIFO		_IFIFO
-
-#ifdef _WIN32
-/* The Windows header files define _S_ forms of these, so we do too
-   for easier portability.  */
-#define _S_IFMT		_IFMT
-#define _S_IFDIR	_IFDIR
-#define _S_IFCHR	_IFCHR
-#define _S_IFIFO	_IFIFO
-#define _S_IFREG	_IFREG
-#define _S_IREAD	0000400
-#define _S_IWRITE	0000200
-#define _S_IEXEC	0000100
-#endif
-
-#define	S_IRWXU 	(S_IRUSR | S_IWUSR | S_IXUSR)
-#define		S_IRUSR	0000400	/* read permission, owner */
-#define		S_IWUSR	0000200	/* write permission, owner */
-#define		S_IXUSR 0000100/* execute/search permission, owner */
-#define	S_IRWXG		(S_IRGRP | S_IWGRP | S_IXGRP)
-#define		S_IRGRP	0000040	/* read permission, group */
-#define		S_IWGRP	0000020	/* write permission, grougroup */
-#define		S_IXGRP 0000010/* execute/search permission, group */
-#define	S_IRWXO		(S_IROTH | S_IWOTH | S_IXOTH)
-#define		S_IROTH	0000004	/* read permission, other */
-#define		S_IWOTH	0000002	/* write permission, other */
-#define		S_IXOTH 0000001/* execute/search permission, other */
-
-#ifndef _POSIX_SOURCE
-#define ACCESSPERMS (S_IRWXU | S_IRWXG | S_IRWXO) /* 0777 */
-#define ALLPERMS (S_ISUID | S_ISGID | S_ISVTX | S_IRWXU | S_IRWXG | S_IRWXO) /* 07777 */
-#define DEFFILEMODE (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH) /* 0666 */
-#endif
-
-#define	S_ISBLK(m)	(((m)&_IFMT) == _IFBLK)
-#define	S_ISCHR(m)	(((m)&_IFMT) == _IFCHR)
-#define	S_ISDIR(m)	(((m)&_IFMT) == _IFDIR)
-#define	S_ISFIFO(m)	(((m)&_IFMT) == _IFIFO)
-#define	S_ISREG(m)	(((m)&_IFMT) == _IFREG)
-#define	S_ISLNK(m)	(((m)&_IFMT) == _IFLNK)
-#define	S_ISSOCK(m)	(((m)&_IFMT) == _IFSOCK)
-
-#if defined(__CYGWIN__)
-/* Special tv_nsec values for futimens(2) and utimensat(2). */
-#define UTIME_NOW	-2L
-#define UTIME_OMIT	-1L
-#endif
-
-int	_EXFUN(chmod,( const char *__path, mode_t __mode ));
-int     _EXFUN(fchmod,(int __fd, mode_t __mode));
-int	_EXFUN(fstat,( int __fd, struct stat *__sbuf ));
-int	_EXFUN(mkdir,( const char *_path, mode_t __mode ));
-int	_EXFUN(mkfifo,( const char *__path, mode_t __mode ));
-int	_EXFUN(stat,( const char *__restrict __path, struct stat *__restrict __sbuf ));
-mode_t	_EXFUN(umask,( mode_t __mask ));
-
-#if defined (__SPU__) || defined(__rtems__) || defined(__CYGWIN__) && !defined(__INSIDE_CYGWIN__)
-int	_EXFUN(lstat,( const char *__restrict __path, struct stat *__restrict __buf ));
-int	_EXFUN(mknod,( const char *__path, mode_t __mode, dev_t __dev ));
-#endif
-
-#if (__POSIX_VISIBLE >= 200809 || defined (__CYGWIN__)) && !defined(__INSIDE_CYGWIN__)
-int	_EXFUN(fchmodat, (int, const char *, mode_t, int));
-#endif
-#if (__BSD_VISIBLE || __POSIX_VISIBLE >= 200809 || defined (__CYGWIN__)) && !defined(__INSIDE_CYGWIN__)
-int	_EXFUN(fstatat, (int, const char *__restrict , struct stat *__restrict, int));
-int	_EXFUN(mkdirat, (int, const char *, mode_t));
-int	_EXFUN(mkfifoat, (int, const char *, mode_t));
-#endif
-#if (__BSD_VISIBLE || __XSI_VISIBLE >= 700 || defined (__CYGWIN__)) && !defined(__INSIDE_CYGWIN__)
-int	_EXFUN(mknodat, (int, const char *, mode_t, dev_t));
-#endif
-#if (__BSD_VISIBLE || __POSIX_VISIBLE >= 200809 || defined (__CYGWIN__)) && !defined(__INSIDE_CYGWIN__)
-int	_EXFUN(utimensat, (int, const char *, const struct timespec *, int));
-int	_EXFUN(futimens, (int, const struct timespec *));
-#endif
-
-/* Provide prototypes for most of the _<systemcall> names that are
-   provided in newlib for some compilers.  */
-#ifdef _COMPILING_NEWLIB
-int	_EXFUN(_fstat,( int __fd, struct stat *__sbuf ));
-int	_EXFUN(_stat,( const char *__restrict __path, struct stat *__restrict __sbuf ));
-int	_EXFUN(_mkdir,( const char *_path, mode_t __mode ));
-#ifdef __LARGE64_FILES
-struct stat64;
-int	_EXFUN(_stat64,( const char *__restrict __path, struct stat64 *__restrict __sbuf ));
-int	_EXFUN(_fstat64,( int __fd, struct stat64 *__sbuf ));
-#endif
-#endif
-
-#endif /* !_STAT_H_ */
-#ifdef __cplusplus
-}
-#endif
-#endif /* _SYS_STAT_H */
diff --git a/tools/sdk/include/newlib/sys/stdio.h b/tools/sdk/include/newlib/sys/stdio.h
deleted file mode 100644
index 0918fe157de..00000000000
--- a/tools/sdk/include/newlib/sys/stdio.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _NEWLIB_STDIO_H
-#define _NEWLIB_STDIO_H
-
-#include <sys/lock.h>
-#include <sys/reent.h>
-
-/* Internal locking macros, used to protect stdio functions.  In the
-   general case, expand to nothing. Use __SSTR flag in FILE _flags to
-   detect if FILE is private to sprintf/sscanf class of functions; if
-   set then do nothing as lock is not initialised. */
-#if !defined(_flockfile)
-#ifndef __SINGLE_THREAD__
-#  define _flockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_acquire_recursive((fp)->_lock))
-#else
-#  define _flockfile(fp)	(_CAST_VOID 0)
-#endif
-#endif
-
-#if !defined(_funlockfile)
-#ifndef __SINGLE_THREAD__
-#  define _funlockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_release_recursive((fp)->_lock))
-#else
-#  define _funlockfile(fp)	(_CAST_VOID 0)
-#endif
-#endif
-
-#endif /* _NEWLIB_STDIO_H */
diff --git a/tools/sdk/include/newlib/sys/string.h b/tools/sdk/include/newlib/sys/string.h
deleted file mode 100644
index ceedf4be10c..00000000000
--- a/tools/sdk/include/newlib/sys/string.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* This is a dummy <sys/string.h> used as a placeholder for
-   systems that need to have a special header file.  */
diff --git a/tools/sdk/include/newlib/sys/syslimits.h b/tools/sdk/include/newlib/sys/syslimits.h
deleted file mode 100644
index c0bb3a2ce09..00000000000
--- a/tools/sdk/include/newlib/sys/syslimits.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 1988, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)syslimits.h	8.1 (Berkeley) 6/2/93
- * $FreeBSD: src/sys/sys/syslimits.h,v 1.10 2001/06/18 20:24:54 wollman Exp $
- */
-
-#ifndef _SYS_SYSLIMITS_H_
-#define _SYS_SYSLIMITS_H_
-
-#define	ARG_MAX			 4096	/* max bytes for an exec function */
-#ifndef CHILD_MAX
-#define	CHILD_MAX		   40	/* max simultaneous processes */
-#endif
-#define	LINK_MAX		32767	/* max file link count */
-#define	MAX_CANON		  255	/* max bytes in term canon input line */
-#define	MAX_INPUT		  255	/* max bytes in terminal input */
-#define	NAME_MAX		  255	/* max bytes in a file name */
-#define	NGROUPS_MAX		   16	/* max supplemental group id's */
-#ifndef OPEN_MAX
-#define	OPEN_MAX		   64	/* max open files per process */
-#endif
-#define	PATH_MAX		 1024	/* max bytes in pathname */
-#define	PIPE_BUF		  512	/* max bytes for atomic pipe writes */
-#define	IOV_MAX			 1024	/* max elements in i/o vector */
-
-#define	BC_BASE_MAX		   99	/* max ibase/obase values in bc(1) */
-#define	BC_DIM_MAX		 2048	/* max array elements in bc(1) */
-#define	BC_SCALE_MAX		   99	/* max scale value in bc(1) */
-#define	BC_STRING_MAX		 1000	/* max const string length in bc(1) */
-#define	COLL_WEIGHTS_MAX	    0	/* max weights for order keyword */
-#define	EXPR_NEST_MAX		   32	/* max expressions nested in expr(1) */
-#define	LINE_MAX		 2048	/* max bytes in an input line */
-#define	RE_DUP_MAX		  255	/* max RE's in interval notation */
-
-#endif
diff --git a/tools/sdk/include/newlib/sys/termios.h b/tools/sdk/include/newlib/sys/termios.h
deleted file mode 100644
index fd0eb5ca884..00000000000
--- a/tools/sdk/include/newlib/sys/termios.h
+++ /dev/null
@@ -1,296 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-// This header file is based on the termios header of
-// "The Single UNIX (r) Specification, Version 2, Copyright (c)  1997 The Open Group".
-
-#ifndef __ESP_SYS_TERMIOS_H__
-#define __ESP_SYS_TERMIOS_H__
-
-// ESP-IDF NOTE: This header provides only a compatibility layer for macros and functions defined in sys/termios.h.
-// Not everything has a defined meaning for ESP-IDF (e.g. process leader IDs) and therefore are likely to be stubbed
-// in actual implementations.
-
-
-#include <stdint.h>
-#include <sys/types.h>
-#include "sdkconfig.h"
-
-#ifdef CONFIG_SUPPORT_TERMIOS
-
-// subscripts for the array c_cc:
-#define VEOF                        0           /** EOF character */
-#define VEOL                        1           /** EOL character */
-#define VERASE                      2           /** ERASE character */
-#define VINTR                       3           /** INTR character */
-#define VKILL                       4           /** KILL character */
-#define VMIN                        5           /** MIN value */
-#define VQUIT                       6           /** QUIT character */
-#define VSTART                      7           /** START character */
-#define VSTOP                       8           /** STOP character */
-#define VSUSP                       9           /** SUSP character */
-#define VTIME                      10           /** TIME value */
-#define NCCS                       (VTIME + 1)  /** Size of the array c_cc for control characters */
-
-// input modes for use as flags in the c_iflag field
-#define BRKINT      (1u << 0)       /** Signal interrupt on break. */
-#define ICRNL       (1u << 1)       /** Map CR to NL on input. */
-#define IGNBRK      (1u << 2)       /** Ignore break condition. */
-#define IGNCR       (1u << 3)       /** Ignore CR. */
-#define IGNPAR      (1u << 4)       /** Ignore characters with parity errors. */
-#define INLCR       (1u << 5)       /** Map NL to CR on input. */
-#define INPCK       (1u << 6)       /** Enable input parity check. */
-#define ISTRIP      (1u << 7)       /** Strip character. */
-#define IUCLC       (1u << 8)       /** Map upper-case to lower-case on input (LEGACY). */
-#define IXANY       (1u << 9)       /** Enable any character to restart output. */
-#define IXOFF       (1u << 10)      /** Enable start/stop input control. */
-#define IXON        (1u << 11)      /** Enable start/stop output control. */
-#define PARMRK      (1u << 12)      /** Mark parity errors. */
-
-// output Modes for use as flags in the c_oflag field
-#define OPOST       (1u <<  0)       /** Post-process output */
-#define OLCUC       (1u <<  1)       /** Map lower-case to upper-case on output (LEGACY). */
-#define ONLCR       (1u <<  2)       /** Map NL to CR-NL on output. */
-#define OCRNL       (1u <<  3)       /** Map CR to NL on output. */
-#define ONOCR       (1u <<  4)       /** No CR output at column 0. */
-#define ONLRET      (1u <<  5)       /** NL performs CR function. */
-#define OFILL       (1u <<  6)       /** Use fill characters for delay. */
-#define NLDLY       (1u <<  7)       /** Select newline delays: */
-#define   NL0       (0u <<  7)       /** Newline character type 0. */
-#define   NL1       (1u <<  7)       /** Newline character type 1. */
-#define CRDLY       (3u <<  8)       /** Select carriage-return delays: */
-#define   CR0       (0u <<  8)       /** Carriage-return delay type 0. */
-#define   CR1       (1u <<  8)       /** Carriage-return delay type 1. */
-#define   CR2       (2u <<  8)       /** Carriage-return delay type 2. */
-#define   CR3       (3u <<  8)       /** Carriage-return delay type 3. */
-#define TABDLY      (3u << 10)       /** Select horizontal-tab delays: */
-#define   TAB0      (0u << 10)       /** Horizontal-tab delay type 0. */
-#define   TAB1      (1u << 10)       /** Horizontal-tab delay type 1. */
-#define   TAB2      (2u << 10)       /** Horizontal-tab delay type 2. */
-#define   TAB3      (3u << 10)       /** Expand tabs to spaces. */
-#define BSDLY       (1u << 12)       /** Select backspace delays: */
-#define   BS0       (0u << 12)       /** Backspace-delay type 0. */
-#define   BS1       (1u << 12)       /** Backspace-delay type 1. */
-#define VTDLY       (1u << 13)       /** Select vertical-tab delays: */
-#define   VT0       (0u << 13)       /** Vertical-tab delay type 0. */
-#define   VT1       (1u << 13)       /** Vertical-tab delay type 1. */
-#define FFDLY       (1u << 14)       /** Select form-feed delays: */
-#define   FF0       (0u << 14)       /** Form-feed delay type 0. */
-#define   FF1       (1u << 14)       /** Form-feed delay type 1. */
-
-// Baud Rate Selection. Valid values for objects of type speed_t:
-// CBAUD range B0 - B38400
-#define B0          0   /** Hang up */
-#define B50         1
-#define B75         2
-#define B110        3
-#define B134        4
-#define B150        5
-#define B200        6
-#define B300        7
-#define B600        8
-#define B1200       9
-#define B1800      10
-#define B2400      11
-#define B4800      12
-#define B9600      13
-#define B19200     14
-#define B38400     15
-// CBAUDEX range B57600 - B4000000
-#define B57600     16
-#define B115200    17
-#define B230400    18
-#define B460800    19
-#define B500000    20
-#define B576000    21
-#define B921600    22
-#define B1000000   23
-#define B1152000   24
-#define B1500000   25
-#define B2000000   26
-#define B2500000   27
-#define B3000000   28
-#define B3500000   29
-#define B4000000   30
-
-// Control Modes for the c_cflag field:
-#define CSIZE      (3u << 0)        /* Character size: */
-#define   CS5      (0u << 0)        /** 5 bits. */
-#define   CS6      (1u << 0)        /** 6 bits. */
-#define   CS7      (2u << 0)        /** 7 bits. */
-#define   CS8      (3u << 0)        /** 8 bits. */
-#define CSTOPB     (1u << 2)        /** Send two stop bits, else one. */
-#define CREAD      (1u << 3)        /** Enable receiver. */
-#define PARENB     (1u << 4)        /** Parity enable. */
-#define PARODD     (1u << 5)        /** Odd parity, else even. */
-#define HUPCL      (1u << 6)        /** Hang up on last close. */
-#define CLOCAL     (1u << 7)        /** Ignore modem status lines. */
-#define CBAUD      (1u << 8)        /** Use baud rates defined by B0-B38400 macros. */
-#define CBAUDEX    (1u << 9)        /** Use baud rates defined by B57600-B4000000 macros. */
-#define BOTHER     (1u << 10)       /** Use custom baud rates */
-
-// Local Modes for c_lflag field:
-#define ECHO       (1u << 0)        /** Enable echo. */
-#define ECHOE      (1u << 1)        /** Echo erase character as error-correcting backspace. */
-#define ECHOK      (1u << 2)        /** Echo KILL. */
-#define ECHONL     (1u << 3)        /** Echo NL. */
-#define ICANON     (1u << 4)        /** Canonical input (erase and kill processing). */
-#define IEXTEN     (1u << 5)        /** Enable extended input character processing. */
-#define ISIG       (1u << 6)        /** Enable signals. */
-#define NOFLSH     (1u << 7)        /** Disable flush after interrupt or quit. */
-#define TOSTOP     (1u << 8)        /** Send SIGTTOU for background output. */
-#define XCASE      (1u << 9)        /** Canonical upper/lower presentation (LEGACY). */
-
-// Attribute Selection constants for use with tcsetattr():
-#define TCSANOW    0                /** Change attributes immediately. */
-#define TCSADRAIN  1                /** Change attributes when output has drained. */
-#define TCSAFLUSH  2                /** Change attributes when output has drained; also flush pending input. */
-
-// Line Control constants for use with tcflush():
-#define TCIFLUSH    0               /** Flush pending input. Flush untransmitted output. */
-#define TCIOFLUSH   1               /** Flush both pending input and untransmitted output. */
-#define TCOFLUSH    2               /** Flush untransmitted output. */
-
-// constants for use with tcflow():
-#define TCIOFF      0               /** Transmit a STOP character, intended to suspend input data. */
-#define TCION       1               /** Transmit a START character, intended to restart input data. */
-#define TCOOFF      2               /** Suspend output. */
-#define TCOON       3               /** Restart output. */
-
-typedef uint8_t cc_t;
-typedef uint32_t speed_t;
-typedef uint16_t tcflag_t;
-
-struct termios
-{
-    tcflag_t c_iflag;    /** Input modes */
-    tcflag_t c_oflag;    /** Output modes */
-    tcflag_t c_cflag;    /** Control modes */
-    tcflag_t c_lflag;    /** Local modes */
-    cc_t     c_cc[NCCS]; /** Control characters */
-    speed_t  c_ispeed;   /** input baud rate */
-    speed_t  c_ospeed;   /** output baud rate */
-};
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Extracts the input baud rate from the input structure exactly (without interpretation).
- *
- * @param p input termios structure
- * @return input baud rate
- */
-speed_t cfgetispeed(const struct termios *p);
-
-/**
- * @brief Extracts the output baud rate from the input structure exactly (without interpretation).
- *
- * @param p input termios structure
- * @return output baud rate
- */
-speed_t cfgetospeed(const struct termios *p);
-
-/**
- * @brief Set input baud rate in the termios structure
- *
- * There is no effect in hardware until a subsequent call of tcsetattr().
- *
- * @param p input termios structure
- * @param sp input baud rate
- * @return 0 when successful, -1 otherwise with errno set
- */
-int cfsetispeed(struct termios *p, speed_t sp);
-
-/**
- * @brief Set output baud rate in the termios structure
- *
- * There is no effect in hardware until a subsequent call of tcsetattr().
- *
- * @param p input termios structure
- * @param sp output baud rate
- * @return 0 when successful, -1 otherwise with errno set
- */
-int cfsetospeed(struct termios *p, speed_t sp);
-
-/**
- * @brief Wait for transmission of output
- *
- * @param fd file descriptor of the terminal
- * @return 0 when successful, -1 otherwise with errno set
- */
-int tcdrain(int fd);
-
-/**
- * @brief Suspend or restart the transmission or reception of data
- *
- * @param fd file descriptor of the terminal
- * @param action selects actions to do
- * @return 0 when successful, -1 otherwise with errno set
- */
-int tcflow(int fd, int action);
-
-/**
- * @brief Flush non-transmitted output data and non-read input data
- *
- * @param fd file descriptor of the terminal
- * @param select selects what should be flushed
- * @return 0 when successful, -1 otherwise with errno set
- */
-int tcflush(int fd, int select);
-
-/**
- * @brief Gets the parameters of the terminal
- *
- * @param fd file descriptor of the terminal
- * @param p output termios structure
- * @return 0 when successful, -1 otherwise with errno set
- */
-int tcgetattr(int fd, struct termios *p);
-
-/**
- * @brief Get process group ID for session leader for controlling terminal
- *
- * @param fd file descriptor of the terminal
- * @return process group ID when successful, -1 otherwise with errno set
- */
-pid_t tcgetsid(int fd);
-
-/**
- * @brief Send a break for a specific duration
- *
- * @param fd file descriptor of the terminal
- * @param duration duration of break
- * @return 0 when successful, -1 otherwise with errno set
- */
-int tcsendbreak(int fd, int duration);
-
-/**
- * @brief Sets the parameters of the terminal
- *
- * @param fd file descriptor of the terminal
- * @param optional_actions optional actions
- * @param p input termios structure
- * @return 0 when successful, -1 otherwise with errno set
- */
-int tcsetattr(int fd, int optional_actions, const struct termios *p);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif // CONFIG_SUPPORT_TERMIOS
-
-#endif //__ESP_SYS_TERMIOS_H__
diff --git a/tools/sdk/include/newlib/sys/time.h b/tools/sdk/include/newlib/sys/time.h
deleted file mode 100644
index 8e3ef80881b..00000000000
--- a/tools/sdk/include/newlib/sys/time.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* time.h -- An implementation of the standard Unix <sys/time.h> file.
-   Written by Geoffrey Noer <noer@cygnus.com>
-   Public domain; no rights reserved. */
-
-#ifndef _SYS_TIME_H_
-#define _SYS_TIME_H_
-
-#include <_ansi.h>
-#include <sys/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef _TIMEVAL_DEFINED
-#define _TIMEVAL_DEFINED
-struct timeval {
-  time_t      tv_sec;
-  suseconds_t tv_usec;
-};
-
-/* BSD time macros used by RTEMS code */
-#if defined (__rtems__) || defined (__CYGWIN__) || defined(__XTENSA__)
-
-/* Convenience macros for operations on timevals.
-   NOTE: `timercmp' does not work for >= or <=.  */
-#define	timerisset(tvp)		((tvp)->tv_sec || (tvp)->tv_usec)
-#define	timerclear(tvp)		((tvp)->tv_sec = (tvp)->tv_usec = 0)
-#define	timercmp(a, b, CMP) 						      \
-  (((a)->tv_sec == (b)->tv_sec) ? 					      \
-   ((a)->tv_usec CMP (b)->tv_usec) : 					      \
-   ((a)->tv_sec CMP (b)->tv_sec))
-#define	timeradd(a, b, result)						      \
-  do {									      \
-    (result)->tv_sec = (a)->tv_sec + (b)->tv_sec;			      \
-    (result)->tv_usec = (a)->tv_usec + (b)->tv_usec;			      \
-    if ((result)->tv_usec >= 1000000)					      \
-      {									      \
-	++(result)->tv_sec;						      \
-	(result)->tv_usec -= 1000000;					      \
-      }									      \
-  } while (0)
-#define	timersub(a, b, result)						      \
-  do {									      \
-    (result)->tv_sec = (a)->tv_sec - (b)->tv_sec;			      \
-    (result)->tv_usec = (a)->tv_usec - (b)->tv_usec;			      \
-    if ((result)->tv_usec < 0) {					      \
-      --(result)->tv_sec;						      \
-      (result)->tv_usec += 1000000;					      \
-    }									      \
-  } while (0)
-#endif /* defined (__rtems__) || defined (__CYGWIN__) */
-#endif /* !_TIMEVAL_DEFINED */
-
-struct timezone {
-  int tz_minuteswest;
-  int tz_dsttime;
-};
-
-#ifdef __CYGWIN__
-#include <cygwin/sys_time.h>
-#endif /* __CYGWIN__ */
-
-#define ITIMER_REAL     0
-#define ITIMER_VIRTUAL  1
-#define ITIMER_PROF     2
-
-struct  itimerval {
-  struct  timeval it_interval;
-  struct  timeval it_value;
-};
-
-#ifdef _COMPILING_NEWLIB
-int _EXFUN(_gettimeofday, (struct timeval *__p, void *__tz));
-#endif
-
-int _EXFUN(gettimeofday, (struct timeval *__restrict __p,
-			  void *__restrict __tz));
-#if __BSD_VISIBLE
-int _EXFUN(settimeofday, (const struct timeval *, const struct timezone *));
-int _EXFUN(adjtime, (const struct timeval *, struct timeval *));
-#endif
-int _EXFUN(utimes, (const char *__path, const struct timeval *__tvp));
-int _EXFUN(getitimer, (int __which, struct itimerval *__value));
-int _EXFUN(setitimer, (int __which, const struct itimerval *__restrict __value,
-					struct itimerval *__restrict __ovalue));
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _SYS_TIME_H_ */
diff --git a/tools/sdk/include/newlib/sys/timeb.h b/tools/sdk/include/newlib/sys/timeb.h
deleted file mode 100644
index 0a2c3de8bdd..00000000000
--- a/tools/sdk/include/newlib/sys/timeb.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* timeb.h -- An implementation of the standard Unix <sys/timeb.h> file.
-   Written by Ian Lance Taylor <ian@cygnus.com>
-   Public domain; no rights reserved.
-
-   <sys/timeb.h> declares the structure used by the ftime function, as
-   well as the ftime function itself.  Newlib does not provide an
-   implementation of ftime.  */
-
-#ifndef _SYS_TIMEB_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define _SYS_TIMEB_H
-
-#include <_ansi.h>
-#include <machine/types.h>
-
-#ifndef __time_t_defined
-typedef _TIME_T_ time_t;
-#define __time_t_defined
-#endif
-
-struct timeb
-{
-  time_t time;
-  unsigned short millitm;
-  short timezone;
-  short dstflag;
-};
-
-extern int ftime _PARAMS ((struct timeb *));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! defined (_SYS_TIMEB_H) */
diff --git a/tools/sdk/include/newlib/sys/times.h b/tools/sdk/include/newlib/sys/times.h
deleted file mode 100644
index 927812cb858..00000000000
--- a/tools/sdk/include/newlib/sys/times.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef	_SYS_TIMES_H
-#ifdef __cplusplus
-extern "C" {
-#endif
-#define	_SYS_TIMES_H
-
-#include <_ansi.h>
-#include <machine/types.h>
-
-#ifndef __clock_t_defined
-typedef _CLOCK_T_ clock_t;
-#define __clock_t_defined
-#endif
-
-/*  Get Process Times, P1003.1b-1993, p. 92 */
-struct tms {
-	clock_t	tms_utime;		/* user time */
-	clock_t	tms_stime;		/* system time */
-	clock_t	tms_cutime;		/* user time, children */
-	clock_t	tms_cstime;		/* system time, children */
-};
-
-clock_t _EXFUN(times,(struct tms *));
-#ifdef _COMPILING_NEWLIB
-clock_t _EXFUN(_times,(struct tms *));
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif	/* !_SYS_TIMES_H */
diff --git a/tools/sdk/include/newlib/sys/types.h b/tools/sdk/include/newlib/sys/types.h
deleted file mode 100644
index ed33e0a617e..00000000000
--- a/tools/sdk/include/newlib/sys/types.h
+++ /dev/null
@@ -1,521 +0,0 @@
-/* unified sys/types.h: 
-   start with sef's sysvi386 version.
-   merge go32 version -- a few ifdefs.
-   h8300hms, h8300xray, and sysvnecv70 disagree on the following types:
-
-   typedef int gid_t;
-   typedef int uid_t;
-   typedef int dev_t;
-   typedef int ino_t;
-   typedef int mode_t;
-   typedef int caddr_t;
-
-   however, these aren't "reasonable" values, the sysvi386 ones make far 
-   more sense, and should work sufficiently well (in particular, h8300 
-   doesn't have a stat, and the necv70 doesn't matter.) -- eichin
- */
-
-#ifndef _SYS_TYPES_H
-
-#include <_ansi.h>
-
-#ifndef __INTTYPES_DEFINED__
-#define __INTTYPES_DEFINED__
-
-#include <machine/_types.h>
-
-#if defined(__rtems__) || defined(__XMK__)
-/*
- *  The following section is RTEMS specific and is needed to more
- *  closely match the types defined in the BSD sys/types.h.
- *  This is needed to let the RTEMS/BSD TCP/IP stack compile.
- */
-
-/* deprecated */
-#if ___int8_t_defined
-typedef __uint8_t	u_int8_t;
-#endif
-#if ___int16_t_defined
-typedef __uint16_t	u_int16_t;
-#endif 
-#if ___int32_t_defined
-typedef __uint32_t	u_int32_t;
-#endif
-
-#if ___int64_t_defined
-typedef __uint64_t	u_int64_t;
-
-/* deprecated */
-typedef	__uint64_t	u_quad_t;
-typedef	__int64_t	quad_t;
-typedef	quad_t *	qaddr_t;
-#endif
-
-#endif
-
-#endif /* ! __INTTYPES_DEFINED */
-
-#ifndef __need_inttypes
-
-#define _SYS_TYPES_H
-#include <sys/_types.h>
-
-#ifdef __i386__
-#if defined (GO32) || defined (__MSDOS__)
-#define __MS_types__
-#endif
-#endif
-
-# include <stddef.h>
-# include <machine/types.h>
-
-/* To ensure the stat struct's layout doesn't change when sizeof(int), etc.
-   changes, we assume sizeof short and long never change and have all types
-   used to define struct stat use them and not int where possible.
-   Where not possible, _ST_INTxx are used.  It would be preferable to not have
-   such assumptions, but until the extra fluff is necessary, it's avoided.
-   No 64 bit targets use stat yet.  What to do about them is postponed
-   until necessary.  */
-#ifdef __GNUC__
-#define _ST_INT32 __attribute__ ((__mode__ (__SI__)))
-#else
-#define _ST_INT32
-#endif
-
-# ifndef	_POSIX_SOURCE
-
-#  define	physadr		physadr_t
-#  define	quad		quad_t
-
-#ifndef _BSDTYPES_DEFINED
-/* also defined in mingw/gmon.h and in w32api/winsock[2].h */
-#ifndef __u_char_defined
-typedef	unsigned char	u_char;
-#define __u_char_defined
-#endif
-#ifndef __u_short_defined
-typedef	unsigned short	u_short;
-#define __u_short_defined
-#endif
-#ifndef __u_int_defined
-typedef	unsigned int	u_int;
-#define __u_int_defined
-#endif
-#ifndef __u_long_defined
-typedef	unsigned long	u_long;
-#define __u_long_defined
-#endif
-#define _BSDTYPES_DEFINED
-#endif
-
-typedef	unsigned short	ushort;		/* System V compatibility */
-typedef	unsigned int	uint;		/* System V compatibility */
-typedef	unsigned long	ulong;		/* System V compatibility */
-# endif	/*!_POSIX_SOURCE */
-
-#ifndef __clock_t_defined
-typedef _CLOCK_T_ clock_t;
-#define __clock_t_defined
-#endif
-
-#ifndef __time_t_defined
-typedef _TIME_T_ time_t;
-#define __time_t_defined
-#endif
-
-#ifndef __timespec_defined
-#define __timespec_defined
-/* Time Value Specification Structures, P1003.1b-1993, p. 261 */
-
-struct timespec {
-  time_t  tv_sec;   /* Seconds */
-  long    tv_nsec;  /* Nanoseconds */
-};
-#endif
-
-struct itimerspec {
-  struct timespec  it_interval;  /* Timer period */
-  struct timespec  it_value;     /* Timer expiration */
-};
-
-#ifndef __daddr_t_defined
-typedef	long	daddr_t;
-#define __daddr_t_defined
-#endif
-#ifndef __caddr_t_defined
-typedef	char *	caddr_t;
-#define __caddr_t_defined
-#endif
-
-#ifndef __CYGWIN__
-#if defined(__MS_types__) || defined(__rtems__) || \
-    defined(__sparc__) || defined(__SPU__)
-typedef	unsigned long	ino_t;
-#else
-typedef	unsigned short	ino_t;
-#endif
-#endif /*__CYGWIN__*/
-
-#ifdef __MS_types__
-typedef unsigned long vm_offset_t;
-typedef unsigned long vm_size_t;
-
-#define __BIT_TYPES_DEFINED__
-
-typedef signed char int8_t;
-typedef unsigned char u_int8_t;
-typedef short int16_t;
-typedef unsigned short u_int16_t;
-typedef int int32_t;
-typedef unsigned int u_int32_t;
-typedef long long int64_t;
-typedef unsigned long long u_int64_t;
-typedef int32_t register_t;
-#endif /* __MS_types__ */
-
-/*
- * All these should be machine specific - right now they are all broken.
- * However, for all of Cygnus' embedded targets, we want them to all be
- * the same.  Otherwise things like sizeof (struct stat) might depend on
- * how the file was compiled (e.g. -mint16 vs -mint32, etc.).
- */
-
-#ifndef __CYGWIN__	/* which defines these types in it's own types.h. */
-typedef _off_t	off_t;
-typedef __dev_t dev_t;
-typedef __uid_t uid_t;
-typedef __gid_t gid_t;
-#endif
-
-#if defined(__XMK__)
-typedef signed char pid_t;
-#else
-typedef int pid_t;
-#endif
-
-#if defined(__rtems__)
-typedef _mode_t mode_t;
-#endif
-
-#ifndef __CYGWIN__
-typedef	long key_t;
-#endif
-typedef _ssize_t ssize_t;
-
-#if !defined(__CYGWIN__) && !defined(__rtems__)
-#ifdef __MS_types__
-typedef	char *	addr_t;
-typedef int mode_t;
-#else
-#if defined (__sparc__) && !defined (__sparc_v9__)
-#ifdef __svr4__
-typedef unsigned long mode_t;
-#else
-typedef unsigned short mode_t;
-#endif
-#else
-typedef unsigned int mode_t _ST_INT32;
-#endif
-#endif /* ! __MS_types__ */
-#endif /*__CYGWIN__*/
-
-typedef unsigned short nlink_t;
-
-/* We don't define fd_set and friends if we are compiling POSIX
-   source, or if we have included (or may include as indicated
-   by __USE_W32_SOCKETS) the W32api winsock[2].h header which
-   defines Windows versions of them.   Note that a program which
-   includes the W32api winsock[2].h header must know what it is doing;
-   it must not call the cygwin32 select function.
-*/
-# if !(defined (_POSIX_SOURCE) || defined (_WINSOCK_H) || defined (_WINSOCKAPI_) || defined (__USE_W32_SOCKETS)) 
-#  define _SYS_TYPES_FD_SET
-#  define	NBBY	8		/* number of bits in a byte */
-/*
- * Select uses bit masks of file descriptors in longs.
- * These macros manipulate such bit fields (the filesystem macros use chars).
- * FD_SETSIZE may be defined by the user, but the default here
- * should be >= NOFILE (param.h).
- */
-#  ifndef	FD_SETSIZE
-#	define	FD_SETSIZE	64
-#  endif
-
-typedef	long	fd_mask;
-#  define	NFDBITS	(sizeof (fd_mask) * NBBY)	/* bits per mask */
-#  ifndef	howmany
-#	define	howmany(x,y)	(((x)+((y)-1))/(y))
-#  endif
-
-/* We use a macro for fd_set so that including Sockets.h afterwards
-   can work.  */
-typedef	struct _types_fd_set {
-	fd_mask	fds_bits[howmany(FD_SETSIZE, NFDBITS)];
-} _types_fd_set;
-
-#define fd_set _types_fd_set
-
-#  define	FD_SET(n, p)	((p)->fds_bits[(n)/NFDBITS] |= (1L << ((n) % NFDBITS)))
-#  define	FD_CLR(n, p)	((p)->fds_bits[(n)/NFDBITS] &= ~(1L << ((n) % NFDBITS)))
-#  define	FD_ISSET(n, p)	((p)->fds_bits[(n)/NFDBITS] & (1L << ((n) % NFDBITS)))
-#  define	FD_ZERO(p)	(__extension__ (void)({ \
-     size_t __i; \
-     char *__tmp = (char *)p; \
-     for (__i = 0; __i < sizeof (*(p)); ++__i) \
-       *__tmp++ = 0; \
-}))
-
-# endif	/* !(defined (_POSIX_SOURCE) || defined (_WINSOCK_H) || defined (_WINSOCKAPI_) || defined (__USE_W32_SOCKETS)) */
-
-#undef __MS_types__
-#undef _ST_INT32
-
-
-#ifndef __clockid_t_defined
-typedef _CLOCKID_T_ clockid_t;
-#define __clockid_t_defined
-#endif
-
-#ifndef __timer_t_defined
-typedef _TIMER_T_ timer_t;
-#define __timer_t_defined
-#endif
-
-typedef unsigned long useconds_t;
-typedef long suseconds_t;
-
-#include <sys/features.h>
-
-
-/* Cygwin will probably never have full posix compliance due to little things
- * like an inability to set the stackaddress. Cygwin is also using void *  
- * pointers rather than structs to ensure maximum binary compatability with
- * previous releases.
- * This means that we don't use the types defined here, but rather in
- * <cygwin/types.h>
- */
-#if defined(_POSIX_THREADS) && !defined(__CYGWIN__)
-
-#include <sys/sched.h>
-
-/*
- *  2.5 Primitive System Data Types,  P1003.1c/D10, p. 19.
- */
-
-#if defined(__XMK__)
-typedef unsigned int pthread_t;          /* identify a thread */
-#else
-typedef __uint32_t pthread_t;            /* identify a thread */
-#endif
-
-/* P1003.1c/D10, p. 118-119 */
-#define PTHREAD_SCOPE_PROCESS 0
-#define PTHREAD_SCOPE_SYSTEM  1
-
-/* P1003.1c/D10, p. 111 */
-#define PTHREAD_INHERIT_SCHED  1      /* scheduling policy and associated */
-                                      /*   attributes are inherited from */
-                                      /*   the calling thread. */
-#define PTHREAD_EXPLICIT_SCHED 2      /* set from provided attribute object */
-
-/* P1003.1c/D10, p. 141 */
-#define PTHREAD_CREATE_DETACHED 0
-#define PTHREAD_CREATE_JOINABLE  1
-
-#if defined(__rtems__)
-  #include <sys/cpuset.h>
-#endif
-
-#if defined(__XMK__)
-typedef struct pthread_attr_s {
-  int contentionscope;
-  struct sched_param schedparam;
-  int  detachstate;
-  void *stackaddr;
-  size_t stacksize;
-} pthread_attr_t;
-
-#define PTHREAD_STACK_MIN       200
-
-#else /* !defined(__XMK__) */
-typedef struct {
-  int is_initialized;
-  void *stackaddr;
-  int stacksize;
-  int contentionscope;
-  int inheritsched;
-  int schedpolicy;
-  struct sched_param schedparam;
-#if defined(__rtems__)
-  size_t guardsize;
-#endif
-
-  /* P1003.4b/D8, p. 54 adds cputime_clock_allowed attribute.  */
-#if defined(_POSIX_THREAD_CPUTIME)
-  int  cputime_clock_allowed;  /* see time.h */
-#endif
-  int  detachstate;
-#if defined(__rtems__)
-  size_t affinitysetsize;
-  cpu_set_t *affinityset;
-  cpu_set_t affinitysetpreallocated;
-#endif
-} pthread_attr_t;
-
-#endif /* !defined(__XMK__) */
-
-#if defined(_POSIX_THREAD_PROCESS_SHARED)
-/* NOTE: P1003.1c/D10, p. 81 defines following values for process_shared.  */
-
-#define PTHREAD_PROCESS_PRIVATE 0 /* visible within only the creating process */
-#define PTHREAD_PROCESS_SHARED  1 /* visible too all processes with access to */
-                                  /*   the memory where the resource is */
-                                  /*   located */
-#endif
-
-#if defined(_POSIX_THREAD_PRIO_PROTECT)
-/* Mutexes */
-
-/* Values for blocking protocol. */
-
-#define PTHREAD_PRIO_NONE    0
-#define PTHREAD_PRIO_INHERIT 1
-#define PTHREAD_PRIO_PROTECT 2
-#endif
-
-#if defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES)
-
-/* Values for mutex type */
-
-/* The following defines are part of the X/Open System Interface (XSI). */
-
-/*
- * This type of mutex does not detect deadlock. A thread attempting to
- * relock this mutex without first unlocking it shall deadlock. Attempting
- * to unlock a mutex locked by a different thread results in undefined
- * behavior.  Attempting to unlock an unlocked mutex results in undefined
- * behavior.
- */
-#define PTHREAD_MUTEX_NORMAL     0
-
-/*
- * A thread attempting to relock this mutex without first unlocking
- * it shall succeed in locking the mutex.  The relocking deadlock which
- * can occur with mutexes of type PTHREAD_MUTEX_NORMAL cannot occur with
- * this type of mutex.  Multiple locks of this mutex shall require the
- * same number of unlocks to release the mutex before another thread can
- * acquire the mutex. A thread attempting to unlock a mutex which another
- * thread has locked shall return with an error.  A thread attempting to
- * unlock an unlocked mutex shall return with an error.
- */
-#define PTHREAD_MUTEX_RECURSIVE  1
-
-/* 
- * This type of mutex provides error checking. A thread attempting
- * to relock this mutex without first unlocking it shall return with an
- * error. A thread attempting to unlock a mutex which another thread has
- * locked shall return with an error. A thread attempting to unlock an
- * unlocked mutex shall return with an error.
- */
-#define PTHREAD_MUTEX_ERRORCHECK 2
-
-/*
- * Attempting to recursively lock a mutex of this type results
- * in undefined behavior. Attempting to unlock a mutex of this type
- * which was not locked by the calling thread results in undefined
- * behavior. Attempting to unlock a mutex of this type which is not locked
- * results in undefined behavior. An implementation may map this mutex to
- * one of the other mutex types.
- */
-#define PTHREAD_MUTEX_DEFAULT    3
-
-#endif /* !defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES) */
-
-#if defined(__XMK__)
-typedef unsigned int pthread_mutex_t;    /* identify a mutex */
-
-typedef struct {
-  int type;
-} pthread_mutexattr_t;
-
-#else /* !defined(__XMK__) */
-typedef __uint32_t pthread_mutex_t;      /* identify a mutex */
-
-typedef struct {
-  int   is_initialized;
-#if defined(_POSIX_THREAD_PROCESS_SHARED)
-  int   process_shared;  /* allow mutex to be shared amongst processes */
-#endif
-#if defined(_POSIX_THREAD_PRIO_PROTECT)
-  int   prio_ceiling;
-  int   protocol;
-#endif
-#if defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES)
-  int type;
-#endif
-  int   recursive;
-} pthread_mutexattr_t;
-#endif /* !defined(__XMK__) */
-
-/* Condition Variables */
-
-typedef __uint32_t pthread_cond_t;       /* identify a condition variable */
-
-typedef struct {
-  int   is_initialized;
-#if defined(_POSIX_THREAD_PROCESS_SHARED)
-  int   process_shared;       /* allow this to be shared amongst processes */
-#endif
-} pthread_condattr_t;         /* a condition attribute object */
-
-/* Keys */
-
-typedef __uint32_t pthread_key_t;        /* thread-specific data keys */
-
-typedef struct {
-  int   is_initialized;  /* is this structure initialized? */
-  int   init_executed;   /* has the initialization routine been run? */
-} pthread_once_t;       /* dynamic package initialization */
-#else
-#if defined (__CYGWIN__)
-#include <cygwin/types.h>
-#endif
-#endif /* defined(_POSIX_THREADS) */
-
-/* POSIX Barrier Types */
-
-#if defined(_POSIX_BARRIERS)
-typedef __uint32_t pthread_barrier_t;        /* POSIX Barrier Object */
-typedef struct {
-  int   is_initialized;  /* is this structure initialized? */
-#if defined(_POSIX_THREAD_PROCESS_SHARED)
-  int   process_shared;       /* allow this to be shared amongst processes */
-#endif
-} pthread_barrierattr_t;
-#endif /* defined(_POSIX_BARRIERS) */
-
-/* POSIX Spin Lock Types */
-
-#if !defined (__CYGWIN__)
-#if defined(_POSIX_SPIN_LOCKS)
-typedef __uint32_t pthread_spinlock_t;        /* POSIX Spin Lock Object */
-#endif /* defined(_POSIX_SPIN_LOCKS) */
-
-/* POSIX Reader/Writer Lock Types */
-
-#if defined(_POSIX_READER_WRITER_LOCKS)
-typedef __uint32_t pthread_rwlock_t;         /* POSIX RWLock Object */
-typedef struct {
-  int   is_initialized;       /* is this structure initialized? */
-#if defined(_POSIX_THREAD_PROCESS_SHARED)
-  int   process_shared;       /* allow this to be shared amongst processes */
-#endif
-} pthread_rwlockattr_t;
-#endif /* defined(_POSIX_READER_WRITER_LOCKS) */
-#endif /* __CYGWIN__ */
-
-#endif  /* !__need_inttypes */
-
-#undef __need_inttypes
-
-#endif	/* _SYS_TYPES_H */
diff --git a/tools/sdk/include/newlib/sys/uio.h b/tools/sdk/include/newlib/sys/uio.h
deleted file mode 100644
index ede27b23513..00000000000
--- a/tools/sdk/include/newlib/sys/uio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_PLATFORM_SYS_UIO_H_
-#define _ESP_PLATFORM_SYS_UIO_H_
-
-int writev(int s, const struct iovec *iov, int iovcnt);
-
-ssize_t readv(int fd, const struct iovec *iov, int iovcnt);
-
-#endif // _ESP_PLATFORM_SYS_UIO_H_
diff --git a/tools/sdk/include/newlib/sys/un.h b/tools/sdk/include/newlib/sys/un.h
deleted file mode 100644
index a99b1832593..00000000000
--- a/tools/sdk/include/newlib/sys/un.h
+++ /dev/null
@@ -1,24 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_PLATFORM_SYS_UN_H_
-#define _ESP_PLATFORM_SYS_UN_H_
-
-#define	AF_UNIX		1		/* local to host (pipes) */
-
-struct sockaddr_un {
-            short                    sun_family;                /*AF_UNIX*/
-            char                     sun_path[108];             /*path name */
-};
-
-#endif // _ESP_PLATFORM_SYS_UN_H_
diff --git a/tools/sdk/include/newlib/sys/unistd.h b/tools/sdk/include/newlib/sys/unistd.h
deleted file mode 100644
index a741383d069..00000000000
--- a/tools/sdk/include/newlib/sys/unistd.h
+++ /dev/null
@@ -1,516 +0,0 @@
-#ifndef _SYS_UNISTD_H
-#define _SYS_UNISTD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <_ansi.h>
-#define __need_size_t
-#define __need_ptrdiff_t
-#include <sys/cdefs.h>
-#include <sys/types.h>
-#include <sys/_types.h>
-#include <stddef.h>
-
-extern char **environ;
-
-void	_EXFUN(_exit, (int __status ) _ATTRIBUTE ((__noreturn__)));
-
-int	_EXFUN(access,(const char *__path, int __amode ));
-unsigned  _EXFUN(alarm, (unsigned __secs ));
-int     _EXFUN(chdir, (const char *__path ));
-int     _EXFUN(chmod, (const char *__path, mode_t __mode ));
-#if !defined(__INSIDE_CYGWIN__)
-int     _EXFUN(chown, (const char *__path, uid_t __owner, gid_t __group ));
-#endif
-#if defined(__CYGWIN__) || defined(__rtems__)
-int     _EXFUN(chroot, (const char *__path ));
-#endif
-int     _EXFUN(close, (int __fildes ));
-#if defined(__CYGWIN__)
-size_t	_EXFUN(confstr, (int __name, char *__buf, size_t __len));
-#endif
-char *  _EXFUN(ctermid, (char *__s ));
-char *  _EXFUN(cuserid, (char *__s ));
-#if defined(__CYGWIN__)
-int	_EXFUN(daemon, (int nochdir, int noclose));
-#endif
-int     _EXFUN(dup, (int __fildes ));
-int     _EXFUN(dup2, (int __fildes, int __fildes2 ));
-#if defined(__CYGWIN__)
-int     _EXFUN(dup3, (int __fildes, int __fildes2, int flags));
-int	_EXFUN(eaccess, (const char *__path, int __mode));
-void	_EXFUN(endusershell, (void));
-int	_EXFUN(euidaccess, (const char *__path, int __mode));
-#endif
-int     _EXFUN(execl, (const char *__path, const char *, ... ));
-int     _EXFUN(execle, (const char *__path, const char *, ... ));
-int     _EXFUN(execlp, (const char *__file, const char *, ... ));
-#if defined(__CYGWIN__)
-int     _EXFUN(execlpe, (const char *__file, const char *, ... ));
-#endif
-int     _EXFUN(execv, (const char *__path, char * const __argv[] ));
-int     _EXFUN(execve, (const char *__path, char * const __argv[], char * const __envp[] ));
-int     _EXFUN(execvp, (const char *__file, char * const __argv[] ));
-#if defined(__CYGWIN__)
-int     _EXFUN(execvpe, (const char *__file, char * const __argv[], char * const __envp[] ));
-#endif
-#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
-int	_EXFUN(faccessat, (int __dirfd, const char *__path, int __mode, int __flags));
-#endif
-#if defined(__CYGWIN__) || defined(__rtems__) || defined(__SPU__)
-int     _EXFUN(fchdir, (int __fildes));
-#endif
-int     _EXFUN(fchmod, (int __fildes, mode_t __mode ));
-#if !defined(__INSIDE_CYGWIN__)
-int     _EXFUN(fchown, (int __fildes, uid_t __owner, gid_t __group ));
-#endif
-#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
-int	_EXFUN(fchownat, (int __dirfd, const char *__path, uid_t __owner, gid_t __group, int __flags));
-#endif
-#if defined(__CYGWIN__)
-int	_EXFUN(fexecve, (int __fd, char * const __argv[], char * const __envp[] ));
-#endif
-pid_t   _EXFUN(fork, (void ));
-long    _EXFUN(fpathconf, (int __fd, int __name ));
-int     _EXFUN(fsync, (int __fd));
-int     _EXFUN(fdatasync, (int __fd));
-#if defined(__CYGWIN__)
-char *  _EXFUN(get_current_dir_name, (void));
-#endif
-char *  _EXFUN(getcwd, (char *__buf, size_t __size ));
-#if defined(__CYGWIN__)
-int	_EXFUN(getdomainname ,(char *__name, size_t __len));
-#endif
-#if !defined(__INSIDE_CYGWIN__)
-gid_t   _EXFUN(getegid, (void ));
-uid_t   _EXFUN(geteuid, (void ));
-gid_t   _EXFUN(getgid, (void ));
-#endif
-int     _EXFUN(getgroups, (int __gidsetsize, gid_t __grouplist[] ));
-#if defined(__CYGWIN__)
-long    _EXFUN(gethostid, (void));
-#endif
-char *  _EXFUN(getlogin, (void ));
-#if defined(_POSIX_THREAD_SAFE_FUNCTIONS)
-int _EXFUN(getlogin_r, (char *name, size_t namesize) );
-#endif
-char *  _EXFUN(getpass, (const char *__prompt));
-int	_EXFUN(getpagesize, (void));
-#if defined(__CYGWIN__)
-int    _EXFUN(getpeereid, (int, uid_t *, gid_t *));
-#endif
-pid_t   _EXFUN(getpgid, (pid_t));
-pid_t   _EXFUN(getpgrp, (void ));
-pid_t   _EXFUN(getpid, (void ));
-pid_t   _EXFUN(getppid, (void ));
-#if defined(__CYGWIN__) || defined(__rtems__)
-pid_t   _EXFUN(getsid, (pid_t));
-#endif
-#if !defined(__INSIDE_CYGWIN__)
-uid_t   _EXFUN(getuid, (void ));
-#endif
-#ifdef __CYGWIN__
-char *	_EXFUN(getusershell, (void));
-char *  _EXFUN(getwd, (char *__buf ));
-int	_EXFUN(iruserok, (unsigned long raddr, int superuser, const char *ruser, const char *luser));
-#endif
-int     _EXFUN(isatty, (int __fildes ));
-#if !defined(__INSIDE_CYGWIN__)
-int     _EXFUN(lchown, (const char *__path, uid_t __owner, gid_t __group ));
-#endif
-int     _EXFUN(link, (const char *__path1, const char *__path2 ));
-#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
-int     _EXFUN(linkat, (int __dirfd1, const char *__path1, int __dirfd2, const char *__path2, int __flags ));
-#endif
-int	_EXFUN(nice, (int __nice_value ));
-#if !defined(__INSIDE_CYGWIN__)
-off_t   _EXFUN(lseek, (int __fildes, off_t __offset, int __whence ));
-#endif
-#if defined(__SPU__) || defined(__CYGWIN__)
-#define F_ULOCK	0
-#define F_LOCK	1
-#define F_TLOCK	2
-#define F_TEST	3
-int     _EXFUN(lockf, (int __fd, int __cmd, off_t __len));
-#endif
-long    _EXFUN(pathconf, (const char *__path, int __name ));
-int     _EXFUN(pause, (void ));
-#ifdef __CYGWIN__
-int	_EXFUN(pthread_atfork, (void (*)(void), void (*)(void), void (*)(void)));
-#endif
-int     _EXFUN(pipe, (int __fildes[2] ));
-#ifdef __CYGWIN__
-int     _EXFUN(pipe2, (int __fildes[2], int flags));
-#endif
-ssize_t _EXFUN(pread, (int __fd, void *__buf, size_t __nbytes, off_t __offset));
-ssize_t _EXFUN(pwrite, (int __fd, const void *__buf, size_t __nbytes, off_t __offset));
-_READ_WRITE_RETURN_TYPE _EXFUN(read, (int __fd, void *__buf, size_t __nbyte ));
-#if defined(__CYGWIN__)
-int	_EXFUN(rresvport, (int *__alport));
-int	_EXFUN(revoke, (char *__path));
-#endif
-int     _EXFUN(rmdir, (const char *__path ));
-#if defined(__CYGWIN__)
-int	_EXFUN(ruserok, (const char *rhost, int superuser, const char *ruser, const char *luser));
-#endif
-void *  _EXFUN(sbrk,  (ptrdiff_t __incr));
-#if !defined(__INSIDE_CYGWIN__)
-#if defined(__CYGWIN__) || defined(__rtems__)
-int     _EXFUN(setegid, (gid_t __gid ));
-int     _EXFUN(seteuid, (uid_t __uid ));
-#endif
-int     _EXFUN(setgid, (gid_t __gid ));
-#endif
-#if defined(__CYGWIN__)
-int	_EXFUN(setgroups, (int ngroups, const gid_t *grouplist ));
-#endif
-#if __BSD_VISIBLE || (defined(_XOPEN_SOURCE) && __XSI_VISIBLE < 500)
-int	_EXFUN(sethostname, (const char *, size_t));
-#endif
-int     _EXFUN(setpgid, (pid_t __pid, pid_t __pgid ));
-int     _EXFUN(setpgrp, (void ));
-#if defined(__CYGWIN__) && !defined(__INSIDE_CYGWIN__)
-int	_EXFUN(setregid, (gid_t __rgid, gid_t __egid));
-int	_EXFUN(setreuid, (uid_t __ruid, uid_t __euid));
-#endif
-pid_t   _EXFUN(setsid, (void ));
-#if !defined(__INSIDE_CYGWIN__)
-int     _EXFUN(setuid, (uid_t __uid ));
-#endif
-#if defined(__CYGWIN__)
-void	_EXFUN(setusershell, (void));
-#endif
-unsigned _EXFUN(sleep, (unsigned int __seconds ));
-void    _EXFUN(swab, (const void *__restrict, void *__restrict, ssize_t));
-long    _EXFUN(sysconf, (int __name ));
-pid_t   _EXFUN(tcgetpgrp, (int __fildes ));
-int     _EXFUN(tcsetpgrp, (int __fildes, pid_t __pgrp_id ));
-char *  _EXFUN(ttyname, (int __fildes ));
-#if defined(__CYGWIN__) || defined(__rtems__)
-int     _EXFUN(ttyname_r, (int, char *, size_t)); 
-#endif
-int     _EXFUN(unlink, (const char *__path ));
-int 	_EXFUN(usleep, (useconds_t __useconds));
-int     _EXFUN(vhangup, (void ));
-_READ_WRITE_RETURN_TYPE _EXFUN(write, (int __fd, const void *__buf, size_t __nbyte ));
-
-#ifdef __CYGWIN__
-# define __UNISTD_GETOPT__
-# include <getopt.h>
-# undef __UNISTD_GETOPT__
-#else
-extern char *optarg;			/* getopt(3) external variables */
-extern int optind, opterr, optopt;
-int	 getopt(int, char * const [], const char *);
-extern int optreset;			/* getopt(3) external variable */
-#endif
-
-#ifndef        _POSIX_SOURCE
-pid_t   _EXFUN(vfork, (void ));
-#endif /* _POSIX_SOURCE */
-
-#ifdef _COMPILING_NEWLIB
-/* Provide prototypes for most of the _<systemcall> names that are
-   provided in newlib for some compilers.  */
-int     _EXFUN(_close, (int __fildes ));
-pid_t   _EXFUN(_fork, (void ));
-pid_t   _EXFUN(_getpid, (void ));
-int	_EXFUN(_isatty, (int __fildes ));
-int     _EXFUN(_link, (const char *__path1, const char *__path2 ));
-_off_t   _EXFUN(_lseek, (int __fildes, _off_t __offset, int __whence ));
-#ifdef __LARGE64_FILES
-_off64_t _EXFUN(_lseek64, (int __filedes, _off64_t __offset, int __whence ));
-#endif
-_READ_WRITE_RETURN_TYPE _EXFUN(_read, (int __fd, void *__buf, size_t __nbyte ));
-void *  _EXFUN(_sbrk,  (ptrdiff_t __incr));
-int     _EXFUN(_unlink, (const char *__path ));
-_READ_WRITE_RETURN_TYPE _EXFUN(_write, (int __fd, const void *__buf, size_t __nbyte ));
-int     _EXFUN(_execve, (const char *__path, char * const __argv[], char * const __envp[] ));
-#endif
-
-#if defined(__CYGWIN__) || defined(__rtems__) || defined(__aarch64__) || defined (__arm__) || defined(__sh__) || defined(__SPU__)
-#if !defined(__INSIDE_CYGWIN__)
-int     _EXFUN(ftruncate, (int __fd, off_t __length));
-int     _EXFUN(truncate, (const char *, off_t __length));
-#endif
-#endif
-
-#if defined(__CYGWIN__) || defined(__rtems__)
-int	_EXFUN(getdtablesize, (void));
-int	_EXFUN(setdtablesize, (int));
-useconds_t _EXFUN(ualarm, (useconds_t __useconds, useconds_t __interval));
-#if !(defined  (_WINSOCK_H) || defined (_WINSOCKAPI_) || defined (__USE_W32_SOCKETS))
-/* winsock[2].h defines as __stdcall, and with int as 2nd arg */
- int	_EXFUN(gethostname, (char *__name, size_t __len));
-#endif
-char *	_EXFUN(mktemp, (char *));
-#endif
-
-#if defined(__CYGWIN__) || defined(__SPU__) || defined(__rtems__)
-void    _EXFUN(sync, (void));
-#endif
-
-ssize_t _EXFUN(readlink, (const char *__restrict __path,
-                          char *__restrict __buf, size_t __buflen));
-#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
-ssize_t        _EXFUN(readlinkat, (int __dirfd1, const char *__restrict __path,
-                            char *__restrict __buf, size_t __buflen));
-#endif
-int     _EXFUN(symlink, (const char *__name1, const char *__name2));
-#if __POSIX_VISIBLE >= 200809 || __BSD_VISIBLE || defined(__CYGWIN__)
-int	_EXFUN(symlinkat, (const char *, int, const char *));
-int	_EXFUN(unlinkat, (int, const char *, int));
-#endif
-
-#define	F_OK	0
-#define	R_OK	4
-#define	W_OK	2
-#define	X_OK	1
-
-# define	SEEK_SET	0
-# define	SEEK_CUR	1
-# define	SEEK_END	2
-
-#include <sys/features.h>
-
-#define STDIN_FILENO    0       /* standard input file descriptor */
-#define STDOUT_FILENO   1       /* standard output file descriptor */
-#define STDERR_FILENO   2       /* standard error file descriptor */
-
-/*
- *  sysconf values per IEEE Std 1003.1, 2008 Edition
- */
-
-#define _SC_ARG_MAX                       0
-#define _SC_CHILD_MAX                     1
-#define _SC_CLK_TCK                       2
-#define _SC_NGROUPS_MAX                   3
-#define _SC_OPEN_MAX                      4
-#define _SC_JOB_CONTROL                   5
-#define _SC_SAVED_IDS                     6
-#define _SC_VERSION                       7
-#define _SC_PAGESIZE                      8
-#define _SC_PAGE_SIZE                     _SC_PAGESIZE
-/* These are non-POSIX values we accidentally introduced in 2000 without
-   guarding them.  Keeping them unguarded for backward compatibility. */
-#define _SC_NPROCESSORS_CONF              9
-#define _SC_NPROCESSORS_ONLN             10
-#define _SC_PHYS_PAGES                   11
-#define _SC_AVPHYS_PAGES                 12
-/* End of non-POSIX values. */
-#define _SC_MQ_OPEN_MAX                  13
-#define _SC_MQ_PRIO_MAX                  14
-#define _SC_RTSIG_MAX                    15
-#define _SC_SEM_NSEMS_MAX                16
-#define _SC_SEM_VALUE_MAX                17
-#define _SC_SIGQUEUE_MAX                 18
-#define _SC_TIMER_MAX                    19
-#define _SC_TZNAME_MAX                   20
-#define _SC_ASYNCHRONOUS_IO              21
-#define _SC_FSYNC                        22
-#define _SC_MAPPED_FILES                 23
-#define _SC_MEMLOCK                      24
-#define _SC_MEMLOCK_RANGE                25
-#define _SC_MEMORY_PROTECTION            26
-#define _SC_MESSAGE_PASSING              27
-#define _SC_PRIORITIZED_IO               28
-#define _SC_REALTIME_SIGNALS             29
-#define _SC_SEMAPHORES                   30
-#define _SC_SHARED_MEMORY_OBJECTS        31
-#define _SC_SYNCHRONIZED_IO              32
-#define _SC_TIMERS                       33
-#define _SC_AIO_LISTIO_MAX               34
-#define _SC_AIO_MAX                      35
-#define _SC_AIO_PRIO_DELTA_MAX           36
-#define _SC_DELAYTIMER_MAX               37
-#define _SC_THREAD_KEYS_MAX              38
-#define _SC_THREAD_STACK_MIN             39
-#define _SC_THREAD_THREADS_MAX           40
-#define _SC_TTY_NAME_MAX                 41
-#define _SC_THREADS                      42
-#define _SC_THREAD_ATTR_STACKADDR        43
-#define _SC_THREAD_ATTR_STACKSIZE        44
-#define _SC_THREAD_PRIORITY_SCHEDULING   45
-#define _SC_THREAD_PRIO_INHERIT          46
-/* _SC_THREAD_PRIO_PROTECT was _SC_THREAD_PRIO_CEILING in early drafts */
-#define _SC_THREAD_PRIO_PROTECT          47
-#define _SC_THREAD_PRIO_CEILING          _SC_THREAD_PRIO_PROTECT
-#define _SC_THREAD_PROCESS_SHARED        48
-#define _SC_THREAD_SAFE_FUNCTIONS        49
-#define _SC_GETGR_R_SIZE_MAX             50
-#define _SC_GETPW_R_SIZE_MAX             51
-#define _SC_LOGIN_NAME_MAX               52
-#define _SC_THREAD_DESTRUCTOR_ITERATIONS 53
-#define _SC_ADVISORY_INFO                54
-#define _SC_ATEXIT_MAX                   55
-#define _SC_BARRIERS                     56
-#define _SC_BC_BASE_MAX                  57
-#define _SC_BC_DIM_MAX                   58
-#define _SC_BC_SCALE_MAX                 59
-#define _SC_BC_STRING_MAX                60
-#define _SC_CLOCK_SELECTION              61
-#define _SC_COLL_WEIGHTS_MAX             62
-#define _SC_CPUTIME                      63
-#define _SC_EXPR_NEST_MAX                64
-#define _SC_HOST_NAME_MAX                65
-#define _SC_IOV_MAX                      66
-#define _SC_IPV6                         67
-#define _SC_LINE_MAX                     68
-#define _SC_MONOTONIC_CLOCK              69
-#define _SC_RAW_SOCKETS                  70
-#define _SC_READER_WRITER_LOCKS          71
-#define _SC_REGEXP                       72
-#define _SC_RE_DUP_MAX                   73
-#define _SC_SHELL                        74
-#define _SC_SPAWN                        75
-#define _SC_SPIN_LOCKS                   76
-#define _SC_SPORADIC_SERVER              77
-#define _SC_SS_REPL_MAX                  78
-#define _SC_SYMLOOP_MAX                  79
-#define _SC_THREAD_CPUTIME               80
-#define _SC_THREAD_SPORADIC_SERVER       81
-#define _SC_TIMEOUTS                     82
-#define _SC_TRACE                        83
-#define _SC_TRACE_EVENT_FILTER           84
-#define _SC_TRACE_EVENT_NAME_MAX         85
-#define _SC_TRACE_INHERIT                86
-#define _SC_TRACE_LOG                    87
-#define _SC_TRACE_NAME_MAX               88
-#define _SC_TRACE_SYS_MAX                89
-#define _SC_TRACE_USER_EVENT_MAX         90
-#define _SC_TYPED_MEMORY_OBJECTS         91
-#define _SC_V7_ILP32_OFF32               92
-#define _SC_V6_ILP32_OFF32               _SC_V7_ILP32_OFF32
-#define _SC_XBS5_ILP32_OFF32             _SC_V7_ILP32_OFF32
-#define _SC_V7_ILP32_OFFBIG              93
-#define _SC_V6_ILP32_OFFBIG              _SC_V7_ILP32_OFFBIG
-#define _SC_XBS5_ILP32_OFFBIG            _SC_V7_ILP32_OFFBIG
-#define _SC_V7_LP64_OFF64                94
-#define _SC_V6_LP64_OFF64                _SC_V7_LP64_OFF64
-#define _SC_XBS5_LP64_OFF64              _SC_V7_LP64_OFF64
-#define _SC_V7_LPBIG_OFFBIG              95
-#define _SC_V6_LPBIG_OFFBIG              _SC_V7_LPBIG_OFFBIG
-#define _SC_XBS5_LPBIG_OFFBIG            _SC_V7_LPBIG_OFFBIG
-#define _SC_XOPEN_CRYPT                  96
-#define _SC_XOPEN_ENH_I18N               97
-#define _SC_XOPEN_LEGACY                 98
-#define _SC_XOPEN_REALTIME               99
-#define _SC_STREAM_MAX                  100
-#define _SC_PRIORITY_SCHEDULING         101
-#define _SC_XOPEN_REALTIME_THREADS      102
-#define _SC_XOPEN_SHM                   103
-#define _SC_XOPEN_STREAMS               104
-#define _SC_XOPEN_UNIX                  105
-#define _SC_XOPEN_VERSION               106
-#define _SC_2_CHAR_TERM                 107
-#define _SC_2_C_BIND                    108
-#define _SC_2_C_DEV                     109
-#define _SC_2_FORT_DEV                  110
-#define _SC_2_FORT_RUN                  111
-#define _SC_2_LOCALEDEF                 112
-#define _SC_2_PBS                       113
-#define _SC_2_PBS_ACCOUNTING            114
-#define _SC_2_PBS_CHECKPOINT            115
-#define _SC_2_PBS_LOCATE                116
-#define _SC_2_PBS_MESSAGE               117
-#define _SC_2_PBS_TRACK                 118
-#define _SC_2_SW_DEV                    119
-#define _SC_2_UPE                       120
-#define _SC_2_VERSION                   121
-#define _SC_THREAD_ROBUST_PRIO_INHERIT  122
-#define _SC_THREAD_ROBUST_PRIO_PROTECT  123
-#define _SC_XOPEN_UUCP                  124
-
-/*
- *  pathconf values per IEEE Std 1003.1, 2008 Edition
- */
-
-#define _PC_LINK_MAX                      0
-#define _PC_MAX_CANON                     1
-#define _PC_MAX_INPUT                     2
-#define _PC_NAME_MAX                      3
-#define _PC_PATH_MAX                      4
-#define _PC_PIPE_BUF                      5
-#define _PC_CHOWN_RESTRICTED              6
-#define _PC_NO_TRUNC                      7
-#define _PC_VDISABLE                      8
-#define _PC_ASYNC_IO                      9
-#define _PC_PRIO_IO                      10
-#define _PC_SYNC_IO                      11
-#define _PC_FILESIZEBITS                 12
-#define _PC_2_SYMLINKS                   13
-#define _PC_SYMLINK_MAX                  14
-#define _PC_ALLOC_SIZE_MIN               15
-#define _PC_REC_INCR_XFER_SIZE           16
-#define _PC_REC_MAX_XFER_SIZE            17
-#define _PC_REC_MIN_XFER_SIZE            18
-#define _PC_REC_XFER_ALIGN               19
-#define _PC_TIMESTAMP_RESOLUTION         20
-#ifdef __CYGWIN__
-/* Ask for POSIX permission bits support. */
-#define _PC_POSIX_PERMISSIONS            90
-/* Ask for full POSIX permission support including uid/gid settings. */
-#define _PC_POSIX_SECURITY               91
-#endif
-
-/*
- *  confstr values per IEEE Std 1003.1, 2004 Edition
- */
-
-#ifdef __CYGWIN__	/* Only defined on Cygwin for now. */
-#define _CS_PATH                               0
-#define _CS_POSIX_V7_ILP32_OFF32_CFLAGS        1
-#define _CS_POSIX_V6_ILP32_OFF32_CFLAGS       _CS_POSIX_V7_ILP32_OFF32_CFLAGS
-#define _CS_XBS5_ILP32_OFF32_CFLAGS           _CS_POSIX_V7_ILP32_OFF32_CFLAGS
-#define _CS_POSIX_V7_ILP32_OFF32_LDFLAGS       2
-#define _CS_POSIX_V6_ILP32_OFF32_LDFLAGS      _CS_POSIX_V7_ILP32_OFF32_LDFLAGS
-#define _CS_XBS5_ILP32_OFF32_LDFLAGS          _CS_POSIX_V7_ILP32_OFF32_LDFLAGS
-#define _CS_POSIX_V7_ILP32_OFF32_LIBS          3
-#define _CS_POSIX_V6_ILP32_OFF32_LIBS         _CS_POSIX_V7_ILP32_OFF32_LIBS
-#define _CS_XBS5_ILP32_OFF32_LIBS             _CS_POSIX_V7_ILP32_OFF32_LIBS
-#define _CS_XBS5_ILP32_OFF32_LINTFLAGS         4
-#define _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS       5
-#define _CS_POSIX_V6_ILP32_OFFBIG_CFLAGS      _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS
-#define _CS_XBS5_ILP32_OFFBIG_CFLAGS          _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS
-#define _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS      6
-#define _CS_POSIX_V6_ILP32_OFFBIG_LDFLAGS     _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS
-#define _CS_XBS5_ILP32_OFFBIG_LDFLAGS         _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS
-#define _CS_POSIX_V7_ILP32_OFFBIG_LIBS         7
-#define _CS_POSIX_V6_ILP32_OFFBIG_LIBS        _CS_POSIX_V7_ILP32_OFFBIG_LIBS
-#define _CS_XBS5_ILP32_OFFBIG_LIBS            _CS_POSIX_V7_ILP32_OFFBIG_LIBS
-#define _CS_XBS5_ILP32_OFFBIG_LINTFLAGS        8
-#define _CS_POSIX_V7_LP64_OFF64_CFLAGS         9
-#define _CS_POSIX_V6_LP64_OFF64_CFLAGS        _CS_POSIX_V7_LP64_OFF64_CFLAGS
-#define _CS_XBS5_LP64_OFF64_CFLAGS            _CS_POSIX_V7_LP64_OFF64_CFLAGS
-#define _CS_POSIX_V7_LP64_OFF64_LDFLAGS       10
-#define _CS_POSIX_V6_LP64_OFF64_LDFLAGS       _CS_POSIX_V7_LP64_OFF64_LDFLAGS
-#define _CS_XBS5_LP64_OFF64_LDFLAGS           _CS_POSIX_V7_LP64_OFF64_LDFLAGS
-#define _CS_POSIX_V7_LP64_OFF64_LIBS          11
-#define _CS_POSIX_V6_LP64_OFF64_LIBS          _CS_POSIX_V7_LP64_OFF64_LIBS
-#define _CS_XBS5_LP64_OFF64_LIBS              _CS_POSIX_V7_LP64_OFF64_LIBS
-#define _CS_XBS5_LP64_OFF64_LINTFLAGS         12
-#define _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS      13
-#define _CS_POSIX_V6_LPBIG_OFFBIG_CFLAGS      _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS
-#define _CS_XBS5_LPBIG_OFFBIG_CFLAGS          _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS
-#define _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS     14
-#define _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS     _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS
-#define _CS_XBS5_LPBIG_OFFBIG_LDFLAGS         _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS
-#define _CS_POSIX_V7_LPBIG_OFFBIG_LIBS        15
-#define _CS_POSIX_V6_LPBIG_OFFBIG_LIBS        _CS_POSIX_V7_LPBIG_OFFBIG_LIBS
-#define _CS_XBS5_LPBIG_OFFBIG_LIBS            _CS_POSIX_V7_LPBIG_OFFBIG_LIBS
-#define _CS_XBS5_LPBIG_OFFBIG_LINTFLAGS       16
-#define _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS    17
-#define _CS_POSIX_V6_WIDTH_RESTRICTED_ENVS    _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS
-#define _CS_XBS5_WIDTH_RESTRICTED_ENVS        _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS
-#define _CS_POSIX_V7_THREADS_CFLAGS           18
-#define _CS_POSIX_V7_THREADS_LDFLAGS          19
-#define _CS_V7_ENV                            20
-#define _CS_V6_ENV                            _CS_V7_ENV
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _SYS_UNISTD_H */
diff --git a/tools/sdk/include/newlib/sys/utime.h b/tools/sdk/include/newlib/sys/utime.h
deleted file mode 100644
index 5e937f10384..00000000000
--- a/tools/sdk/include/newlib/sys/utime.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _SYS_UTIME_H
-#define _SYS_UTIME_H
-
-/* This is a dummy <sys/utime.h> file, not customized for any
-   particular system.  If there is a utime.h in libc/sys/SYSDIR/sys,
-   it will override this one.  */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct utimbuf 
-{
-  time_t actime;
-  time_t modtime; 
-};
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif /* _SYS_UTIME_H */
diff --git a/tools/sdk/include/newlib/sys/wait.h b/tools/sdk/include/newlib/sys/wait.h
deleted file mode 100644
index 73fe372024f..00000000000
--- a/tools/sdk/include/newlib/sys/wait.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef _SYS_WAIT_H
-#define _SYS_WAIT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <sys/types.h>
-
-#define WNOHANG 1
-#define WUNTRACED 2
-
-/* A status looks like:
-      <2 bytes info> <2 bytes code>
-
-      <code> == 0, child has exited, info is the exit value
-      <code> == 1..7e, child has exited, info is the signal number.
-      <code> == 7f, child has stopped, info was the signal number.
-      <code> == 80, there was a core dump.
-*/
-   
-#define WIFEXITED(w)	(((w) & 0xff) == 0)
-#define WIFSIGNALED(w)	(((w) & 0x7f) > 0 && (((w) & 0x7f) < 0x7f))
-#define WIFSTOPPED(w)	(((w) & 0xff) == 0x7f)
-#define WEXITSTATUS(w)	(((w) >> 8) & 0xff)
-#define WTERMSIG(w)	((w) & 0x7f)
-#define WSTOPSIG	WEXITSTATUS
-
-pid_t wait (int *);
-pid_t waitpid (pid_t, int *, int);
-
-#ifdef _COMPILING_NEWLIB
-pid_t _wait (int *);
-#endif
-
-/* Provide prototypes for most of the _<systemcall> names that are
-   provided in newlib for some compilers.  */
-pid_t _wait (int *);
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif
diff --git a/tools/sdk/include/newlib/tar.h b/tools/sdk/include/newlib/tar.h
deleted file mode 100644
index 07b06dd7fba..00000000000
--- a/tools/sdk/include/newlib/tar.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * tar.h
- */
-
-#ifndef _TAR_H
-#define _TAR_H
-
-/* General definitions */
-#define TMAGIC 		"ustar" /* ustar plus null byte. */
-#define TMAGLEN 	6 	/* Length of the above. */
-#define TVERSION 	"00"	/* 00 without a null byte. */
-#define TVERSLEN	2	/* Length of the above. */
-
-/* Typeflag field definitions */
-#define REGTYPE 	'0'	/* Regular file. */
-#define AREGTYPE	'\0'	/* Regular file. */
-#define LNKTYPE		'1'	/* Link. */
-#define SYMTYPE		'2'	/* Symbolic link. */
-#define CHRTYPE		'3'	/* Character special. */
-#define BLKTYPE		'4'	/* Block special. */
-#define DIRTYPE		'5'	/* Directory. */
-#define FIFOTYPE	'6'	/* FIFO special. */
-#define CONTTYPE	'7'	/* Reserved. */
-
-/* Mode field bit definitions (octal) */
-#define	TSUID		04000	/* Set UID on execution. */
-#define	TSGID		02000	/* Set GID on execution. */
-#define	TSVTX		01000	/* On directories, restricted deletion flag. */
-#define	TUREAD		00400	/* Read by owner. */
-#define	TUWRITE		00200	/* Write by owner. */
-#define	TUEXEC		00100	/* Execute/search by owner. */
-#define	TGREAD		00040	/* Read by group. */
-#define	TGWRITE		00020	/* Write by group. */
-#define	TGEXEC		00010	/* Execute/search by group. */
-#define	TOREAD		00004	/* Read by other. */
-#define	TOWRITE		00002	/* Write by other. */
-#define	TOEXEC		00001	/* Execute/search by other. */
-
-#endif
diff --git a/tools/sdk/include/newlib/termios.h b/tools/sdk/include/newlib/termios.h
deleted file mode 100644
index ee1820ce047..00000000000
--- a/tools/sdk/include/newlib/termios.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include <sys/termios.h>
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/newlib/tgmath.h b/tools/sdk/include/newlib/tgmath.h
deleted file mode 100644
index f9c8311cc3d..00000000000
--- a/tools/sdk/include/newlib/tgmath.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/* http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/tgmath.h.html */
-/*-
- * Copyright (c) 2004 Stefan Farfeleder.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _TGMATH_H_
-#define	_TGMATH_H_
-
-#include <complex.h>
-#include <math.h>
-
-#ifdef log2
-#undef log2
-#endif
-
-/*
- * This implementation of <tgmath.h> requires two implementation-dependent
- * macros to be defined:
- * __tg_impl_simple(x, y, z, fn, fnf, fnl, ...)
- *	Invokes fnl() if the corresponding real type of x, y or z is long
- *	double, fn() if it is double or any has an integer type, and fnf()
- *	otherwise.
- * __tg_impl_full(x, y, z, fn, fnf, fnl, cfn, cfnf, cfnl, ...)
- *	Invokes [c]fnl() if the corresponding real type of x, y or z is long
- *	double, [c]fn() if it is double or any has an integer type, and
- *	[c]fnf() otherwise.  The function with the 'c' prefix is called if
- *	any of x, y or z is a complex number.
- * Both macros call the chosen function with all additional arguments passed
- * to them, as given by __VA_ARGS__.
- *
- * Note that these macros cannot be implemented with C's ?: operator,
- * because the return type of the whole expression would incorrectly be long
- * double complex regardless of the argument types.
- */
-
-/* requires GCC >= 3.1 */
-#if !__GNUC_PREREQ (3, 1)
-#error "<tgmath.h> not implemented for this compiler"
-#endif
-
-#define	__tg_type(__e, __t)						\
-	__builtin_types_compatible_p(__typeof__(__e), __t)
-#define	__tg_type3(__e1, __e2, __e3, __t)				\
-	(__tg_type(__e1, __t) || __tg_type(__e2, __t) || 		\
-	 __tg_type(__e3, __t))
-#define	__tg_type_corr(__e1, __e2, __e3, __t)				\
-	(__tg_type3(__e1, __e2, __e3, __t) || 				\
-	 __tg_type3(__e1, __e2, __e3, __t _Complex))
-#define	__tg_integer(__e1, __e2, __e3)					\
-	(((__typeof__(__e1))1.5 == 1) || ((__typeof__(__e2))1.5 == 1) ||	\
-	 ((__typeof__(__e3))1.5 == 1))
-#define	__tg_is_complex(__e1, __e2, __e3)				\
-	(__tg_type3(__e1, __e2, __e3, float _Complex) ||		\
-	 __tg_type3(__e1, __e2, __e3, double _Complex) ||		\
-	 __tg_type3(__e1, __e2, __e3, long double _Complex) ||		\
-	 __tg_type3(__e1, __e2, __e3, __typeof__(_Complex_I)))
-
-#ifdef _LDBL_EQ_DBL
-#define	__tg_impl_simple(x, y, z, fn, fnf, fnl, ...)			\
-	__builtin_choose_expr(__tg_type_corr(x, y, z, long double),	\
-	    fnl(__VA_ARGS__), __builtin_choose_expr(			\
-		__tg_type_corr(x, y, z, double) || __tg_integer(x, y, z),\
-		fn(__VA_ARGS__), fnf(__VA_ARGS__)))
-#else
-#define	__tg_impl_simple(__x, __y, __z, __fn, __fnf, __fnl, ...)	\
-	(__tg_type_corr(__x, __y, __z, double) || __tg_integer(__x, __y, __z)) \
-		? __fn(__VA_ARGS__) : __fnf(__VA_ARGS__)
-#endif
-
-#define	__tg_impl_full(__x, __y, __z, __fn, __fnf, __fnl, __cfn, __cfnf, __cfnl, ...)	\
-	__builtin_choose_expr(__tg_is_complex(__x, __y, __z),		\
-	    __tg_impl_simple(__x, __y, __z, __cfn, __cfnf, __cfnl, __VA_ARGS__),	\
-	    __tg_impl_simple(__x, __y, __z, __fn, __fnf, __fnl, __VA_ARGS__))
-
-/* Macros to save lots of repetition below */
-#define	__tg_simple(__x, __fn)						\
-	__tg_impl_simple(__x, __x, __x, __fn, __fn##f, __fn##l, __x)
-#define	__tg_simple2(__x, __y, __fn)					\
-	__tg_impl_simple(__x, __x, __y, __fn, __fn##f, __fn##l, __x, __y)
-#define	__tg_simplev(__x, __fn, ...)					\
-	__tg_impl_simple(__x, __x, __x, __fn, __fn##f, __fn##l, __VA_ARGS__)
-#define	__tg_full(__x, __fn)						\
-	__tg_impl_full(__x, __x, __x, __fn, __fn##f, __fn##l, c##__fn, c##__fn##f, c##__fn##l, __x)
-
-/* 7.22#4 -- These macros expand to real or complex functions, depending on
- * the type of their arguments. */
-#define	acos(__x)		__tg_full(__x, acos)
-#define	asin(__x)		__tg_full(__x, asin)
-#define	atan(__x)		__tg_full(__x, atan)
-#define	acosh(__x)		__tg_full(__x, acosh)
-#define	asinh(__x)		__tg_full(__x, asinh)
-#define	atanh(__x)		__tg_full(__x, atanh)
-#define	cos(__x)		__tg_full(__x, cos)
-#define	sin(__x)		__tg_full(__x, sin)
-#define	tan(__x)		__tg_full(__x, tan)
-#define	cosh(__x)		__tg_full(__x, cosh)
-#define	sinh(__x)		__tg_full(__x, sinh)
-#define	tanh(__x)		__tg_full(__x, tanh)
-#define	exp(__x)		__tg_full(__x, exp)
-#define	log(__x)		__tg_full(__x, log)
-#define	pow(__x, __y)		__tg_impl_full(__x, __x, __y, pow, powf, powl,	\
-						cpow, cpowf, cpowl, __x, __y)
-#define	sqrt(__x)		__tg_full(__x, sqrt)
-
-/* "The corresponding type-generic macro for fabs and cabs is fabs." */
-#define	fabs(__x)		__tg_impl_full(__x, __x, __x, fabs, fabsf, fabsl,	\
-						cabs, cabsf, cabsl, __x)
-
-/* 7.22#5 -- These macros are only defined for arguments with real type. */
-#define	atan2(__x, __y)		__tg_simple2(__x, __y, atan2)
-#define	cbrt(__x)		__tg_simple(__x, cbrt)
-#define	ceil(__x)		__tg_simple(__x, ceil)
-#define	copysign(__x, __y)	__tg_simple2(__x, __y, copysign)
-#define	erf(__x)		__tg_simple(__x, erf)
-#define	erfc(__x)		__tg_simple(__x, erfc)
-#define	exp2(__x)		__tg_simple(__x, exp2)
-#define	expm1(__x)		__tg_simple(__x, expm1)
-#define	fdim(__x, __y)		__tg_simple2(__x, __y, fdim)
-#define	floor(__x)		__tg_simple(__x, floor)
-#define	fma(__x, __y, __z)	__tg_impl_simple(__x, __y, __z, fma, fmaf, fmal, \
-						 __x, __y, __z)
-#define	fmax(__x, __y)		__tg_simple2(__x, __y, fmax)
-#define	fmin(__x, __y)		__tg_simple2(__x, __y, fmin)
-#define	fmod(__x, __y)		__tg_simple2(__x, __y, fmod)
-#define	frexp(__x, __y)		__tg_simplev(__x, frexp, __x, __y)
-#define	hypot(__x, __y)		__tg_simple2(__x, __y, hypot)
-#define	ilogb(__x)		__tg_simple(__x, ilogb)
-#define	ldexp(__x, __y)		__tg_simplev(__x, ldexp, __x, __y)
-#define	lgamma(__x)		__tg_simple(__x, lgamma)
-#define	llrint(__x)		__tg_simple(__x, llrint)
-#define	llround(__x)		__tg_simple(__x, llround)
-#define	log10(__x)		__tg_simple(__x, log10)
-#define	log1p(__x)		__tg_simple(__x, log1p)
-#define	log2(__x)		__tg_simple(__x, log2)
-#define	logb(__x)		__tg_simple(__x, logb)
-#define	lrint(__x)		__tg_simple(__x, lrint)
-#define	lround(__x)		__tg_simple(__x, lround)
-#define	nearbyint(__x)		__tg_simple(__x, nearbyint)
-#define	nextafter(__x, __y)	__tg_simple2(__x, __y, nextafter)
-/* not yet implemented even for _LDBL_EQ_DBL platforms
-#define	nexttoward(__x, __y)	__tg_simplev(__x, nexttoward, __x, __y)
-*/
-#define	remainder(__x, __y)	__tg_simple2(__x, __y, remainder)
-#define	remquo(__x, __y, __z)	__tg_impl_simple(__x, __x, __y, remquo, remquof,	\
-						 remquol, __x, __y, __z)
-#define	rint(__x)		__tg_simple(__x, rint)
-#define	round(__x)		__tg_simple(__x, round)
-#define	scalbn(__x, __y)	__tg_simplev(__x, scalbn, __x, __y)
-#define	scalbln(__x, __y)	__tg_simplev(__x, scalbln, __x, __y)
-#define	tgamma(__x)		__tg_simple(__x, tgamma)
-#define	trunc(__x)		__tg_simple(__x, trunc)
-
-/* 7.22#6 -- These macros always expand to complex functions. */
-#define	carg(__x)		__tg_simple(__x, carg)
-#define	cimag(__x)		__tg_simple(__x, cimag)
-#define	conj(__x)		__tg_simple(__x, conj)
-#define	cproj(__x)		__tg_simple(__x, cproj)
-#define	creal(__x)		__tg_simple(__x, creal)
-
-#endif /* !_TGMATH_H_ */
diff --git a/tools/sdk/include/newlib/time.h b/tools/sdk/include/newlib/time.h
deleted file mode 100644
index d7b6612db11..00000000000
--- a/tools/sdk/include/newlib/time.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * time.h
- * 
- * Struct and function declarations for dealing with time.
- */
-
-#ifndef _TIME_H_
-#define _TIME_H_
-
-#include "_ansi.h"
-#include <sys/reent.h>
-
-#define __need_size_t
-#define __need_NULL
-#include <stddef.h>
-
-/* Get _CLOCKS_PER_SEC_ */
-#include <machine/time.h>
-
-#ifndef _CLOCKS_PER_SEC_
-#define _CLOCKS_PER_SEC_ 1000
-#endif
-
-#define CLOCKS_PER_SEC _CLOCKS_PER_SEC_
-#define CLK_TCK CLOCKS_PER_SEC
-
-#include <sys/types.h>
-
-_BEGIN_STD_C
-
-struct tm
-{
-  int	tm_sec;
-  int	tm_min;
-  int	tm_hour;
-  int	tm_mday;
-  int	tm_mon;
-  int	tm_year;
-  int	tm_wday;
-  int	tm_yday;
-  int	tm_isdst;
-#ifdef __TM_GMTOFF
-  long	__TM_GMTOFF;
-#endif
-#ifdef __TM_ZONE
-  const char *__TM_ZONE;
-#endif
-};
-
-clock_t	   _EXFUN(clock,    (void));
-double	   _EXFUN(difftime, (time_t _time2, time_t _time1));
-time_t	   _EXFUN(mktime,   (struct tm *_timeptr));
-time_t	   _EXFUN(time,     (time_t *_timer));
-#ifndef _REENT_ONLY
-char	  *_EXFUN(asctime,  (const struct tm *_tblock));
-char	  *_EXFUN(ctime,    (const time_t *_time));
-struct tm *_EXFUN(gmtime,   (const time_t *_timer));
-struct tm *_EXFUN(localtime,(const time_t *_timer));
-#endif
-size_t	   _EXFUN(strftime, (char *__restrict _s,
-			     size_t _maxsize, const char *__restrict _fmt,
-			     const struct tm *__restrict _t));
-
-char	  *_EXFUN(asctime_r,	(const struct tm *__restrict,
-				 char *__restrict));
-char	  *_EXFUN(ctime_r,	(const time_t *, char *));
-struct tm *_EXFUN(gmtime_r,	(const time_t *__restrict,
-				 struct tm *__restrict));
-struct tm *_EXFUN(localtime_r,	(const time_t *__restrict,
-				 struct tm *__restrict));
-
-_END_STD_C
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef __STRICT_ANSI__
-char      *_EXFUN(strptime,     (const char *__restrict,
-				 const char *__restrict,
-				 struct tm *__restrict));
-_VOID      _EXFUN(tzset,	(_VOID));
-_VOID      _EXFUN(_tzset_r,	(struct _reent *));
-
-typedef struct __tzrule_struct
-{
-  char ch;
-  int m;
-  int n;
-  int d;
-  int s;
-  time_t change;
-  long offset; /* Match type of _timezone. */
-} __tzrule_type;
-
-typedef struct __tzinfo_struct
-{
-  int __tznorth;
-  int __tzyear;
-  __tzrule_type __tzrule[2];
-} __tzinfo_type;
-
-__tzinfo_type *_EXFUN (__gettzinfo, (_VOID));
-
-/* getdate functions */
-
-#ifdef HAVE_GETDATE
-#ifndef _REENT_ONLY
-#define getdate_err (*__getdate_err())
-int *_EXFUN(__getdate_err,(_VOID));
-
-struct tm *	_EXFUN(getdate, (const char *));
-/* getdate_err is set to one of the following values to indicate the error.
-     1  the DATEMSK environment variable is null or undefined,
-     2  the template file cannot be opened for reading,
-     3  failed to get file status information,
-     4  the template file is not a regular file,
-     5  an error is encountered while reading the template file,
-     6  memory allication failed (not enough memory available),
-     7  there is no line in the template that matches the input,
-     8  invalid input specification  */
-#endif /* !_REENT_ONLY */
-
-/* getdate_r returns the error code as above */
-int		_EXFUN(getdate_r, (const char *, struct tm *));
-#endif /* HAVE_GETDATE */
-
-/* defines for the opengroup specifications Derived from Issue 1 of the SVID.  */
-extern __IMPORT long _timezone;
-extern __IMPORT int _daylight;
-extern __IMPORT char *_tzname[2];
-
-/* POSIX defines the external tzname being defined in time.h */
-#ifndef tzname
-#define tzname _tzname
-#endif
-#endif /* !__STRICT_ANSI__ */
-
-#ifdef __cplusplus
-}
-#endif
-
-#include <sys/features.h>
-
-#ifdef __CYGWIN__
-#include <cygwin/time.h>
-#endif /*__CYGWIN__*/
-
-#if defined(_POSIX_TIMERS)
-
-#include <signal.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Clocks, P1003.1b-1993, p. 263 */
-
-int _EXFUN(clock_settime, (clockid_t clock_id, const struct timespec *tp));
-int _EXFUN(clock_gettime, (clockid_t clock_id, struct timespec *tp));
-int _EXFUN(clock_getres,  (clockid_t clock_id, struct timespec *res));
-
-/* Create a Per-Process Timer, P1003.1b-1993, p. 264 */
-
-int _EXFUN(timer_create,
-  	(clockid_t clock_id,
- 	struct sigevent *__restrict evp,
-	timer_t *__restrict timerid));
-
-/* Delete a Per_process Timer, P1003.1b-1993, p. 266 */
-
-int _EXFUN(timer_delete, (timer_t timerid));
-
-/* Per-Process Timers, P1003.1b-1993, p. 267 */
-
-int _EXFUN(timer_settime,
-	(timer_t timerid, int flags,
-	const struct itimerspec *__restrict value,
-	struct itimerspec *__restrict ovalue));
-int _EXFUN(timer_gettime, (timer_t timerid, struct itimerspec *value));
-int _EXFUN(timer_getoverrun, (timer_t timerid));
-
-/* High Resolution Sleep, P1003.1b-1993, p. 269 */
-
-int _EXFUN(nanosleep, (const struct timespec  *rqtp, struct timespec *rmtp));
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _POSIX_TIMERS */
-
-#if defined(_POSIX_CLOCK_SELECTION)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int _EXFUN(clock_nanosleep,
-  (clockid_t clock_id, int flags, const struct timespec *rqtp,
-   struct timespec *rmtp));
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _POSIX_CLOCK_SELECTION */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* CPU-time Clock Attributes, P1003.4b/D8, p. 54 */
-
-/* values for the clock enable attribute */
-
-#define CLOCK_ENABLED  1  /* clock is enabled, i.e. counting execution time */
-#define CLOCK_DISABLED 0  /* clock is disabled */
-
-/* values for the pthread cputime_clock_allowed attribute */
-
-#define CLOCK_ALLOWED    1 /* If a thread is created with this value a */
-                           /*   CPU-time clock attached to that thread */
-                           /*   shall be accessible. */
-#define CLOCK_DISALLOWED 0 /* If a thread is created with this value, the */
-                           /*   thread shall not have a CPU-time clock */
-                           /*   accessible. */
-
-/* Manifest Constants, P1003.1b-1993, p. 262 */
-
-#define CLOCK_REALTIME (clockid_t)1
-
-/* Flag indicating time is "absolute" with respect to the clock
-   associated with a time.  */
-
-#define TIMER_ABSTIME	4
-
-/* Manifest Constants, P1003.4b/D8, p. 55 */
-
-#if defined(_POSIX_CPUTIME)
-
-/* When used in a clock or timer function call, this is interpreted as
-   the identifier of the CPU_time clock associated with the PROCESS
-   making the function call.  */
-
-#define CLOCK_PROCESS_CPUTIME_ID (clockid_t)2
-
-#endif
-
-#if defined(_POSIX_THREAD_CPUTIME)
-
-/*  When used in a clock or timer function call, this is interpreted as
-    the identifier of the CPU_time clock associated with the THREAD
-    making the function call.  */
-
-#define CLOCK_THREAD_CPUTIME_ID (clockid_t)3
-
-#endif
-
-#if defined(_POSIX_MONOTONIC_CLOCK)
-
-/*  The identifier for the system-wide monotonic clock, which is defined
- *      as a clock whose value cannot be set via clock_settime() and which 
- *          cannot have backward clock jumps. */
-
-#define CLOCK_MONOTONIC (clockid_t)4
-
-#endif
-
-#if defined(_POSIX_CPUTIME)
-
-/* Accessing a Process CPU-time CLock, P1003.4b/D8, p. 55 */
-
-int _EXFUN(clock_getcpuclockid, (pid_t pid, clockid_t *clock_id));
-
-#endif /* _POSIX_CPUTIME */
-
-#if defined(_POSIX_CPUTIME) || defined(_POSIX_THREAD_CPUTIME)
-
-/* CPU-time Clock Attribute Access, P1003.4b/D8, p. 56 */
-
-int _EXFUN(clock_setenable_attr, (clockid_t clock_id, int attr));
-int _EXFUN(clock_getenable_attr, (clockid_t clock_id, int *attr));
-
-#endif /* _POSIX_CPUTIME or _POSIX_THREAD_CPUTIME */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _TIME_H_ */
-
diff --git a/tools/sdk/include/newlib/unctrl.h b/tools/sdk/include/newlib/unctrl.h
deleted file mode 100644
index 00407523295..00000000000
--- a/tools/sdk/include/newlib/unctrl.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* From curses.h.  */
-/*
- * Copyright (c) 1981, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#ifndef _UNCTRL_H_
-#define _UNCTRL_H_
-
-#include <_ansi.h>
-
-#define unctrl(c)		__unctrl[(c) & 0xff]
-#define unctrllen(ch)		__unctrllen[(ch) & 0xff]
-
-extern __IMPORT _CONST char * _CONST __unctrl[256];	/* Control strings. */
-extern __IMPORT _CONST char __unctrllen[256];	/* Control strings length. */
-
-#endif /* _UNCTRL_H_ */
diff --git a/tools/sdk/include/newlib/unistd.h b/tools/sdk/include/newlib/unistd.h
deleted file mode 100644
index 4f6fd29a4db..00000000000
--- a/tools/sdk/include/newlib/unistd.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _UNISTD_H_
-#define _UNISTD_H_
-
-# include <sys/unistd.h>
-
-#ifndef L_SET
-/* Old BSD names for the same constants; just for compatibility.  */
-#define		L_SET		SEEK_SET
-#define		L_INCR		SEEK_CUR
-#define		L_XTND		SEEK_END
-#endif
-
-#endif /* _UNISTD_H_ */
diff --git a/tools/sdk/include/newlib/utime.h b/tools/sdk/include/newlib/utime.h
deleted file mode 100644
index 652891aab15..00000000000
--- a/tools/sdk/include/newlib/utime.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <_ansi.h>
-
-/* The utime function is defined in libc/sys/<arch>/sys if it exists. */
-#include <sys/utime.h>
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/newlib/utmp.h b/tools/sdk/include/newlib/utmp.h
deleted file mode 100644
index 88cf6f8528f..00000000000
--- a/tools/sdk/include/newlib/utmp.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include <sys/utmp.h>
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/tools/sdk/include/newlib/wchar.h b/tools/sdk/include/newlib/wchar.h
deleted file mode 100644
index 810a6c0e337..00000000000
--- a/tools/sdk/include/newlib/wchar.h
+++ /dev/null
@@ -1,254 +0,0 @@
-#ifndef _WCHAR_H_
-#define _WCHAR_H_
-
-#include <_ansi.h>
-
-#include <sys/reent.h>
-
-#define __need_size_t
-#define __need_wchar_t
-#define __need_wint_t
-#define __need_NULL
-#include <stddef.h>
-
-#define __need___va_list
-#include <stdarg.h>
-
-/* For _mbstate_t definition. */
-#include <sys/_types.h>
-#include <sys/cdefs.h>
-/* For __STDC_ISO_10646__ */
-#include <sys/features.h>
-
-#ifndef WEOF
-# define WEOF ((wint_t)-1)
-#endif
-
-/* This must match definition in <stdint.h> */
-#ifndef WCHAR_MIN
-#ifdef __WCHAR_MIN__
-#define WCHAR_MIN __WCHAR_MIN__
-#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
-#define WCHAR_MIN (0 + L'\0')
-#else
-#define WCHAR_MIN (-0x7fffffff - 1 + L'\0')
-#endif
-#endif
-
-/* This must match definition in <stdint.h> */
-#ifndef WCHAR_MAX
-#ifdef __WCHAR_MAX__
-#define WCHAR_MAX __WCHAR_MAX__
-#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
-#define WCHAR_MAX (0xffffffffu + L'\0')
-#else
-#define WCHAR_MAX (0x7fffffff + L'\0')
-#endif
-#endif
-
-_BEGIN_STD_C
-
-/* As in stdio.h, <sys/reent.h> defines __FILE. */
-typedef __FILE FILE;
-
-/* As required by POSIX.1-2008, declare tm as incomplete type.
-   The actual definition is in time.h. */
-struct tm;
-
-#ifndef _MBSTATE_T
-#define _MBSTATE_T
-typedef _mbstate_t mbstate_t;
-#endif /* _MBSTATE_T */
-
-wint_t	_EXFUN(btowc, (int));
-int	_EXFUN(wctob, (wint_t));
-size_t	_EXFUN(mbrlen, (const char *__restrict, size_t, mbstate_t *__restrict));
-size_t	_EXFUN(mbrtowc, (wchar_t *__restrict, const char *__restrict, size_t,
-						mbstate_t *__restrict));
-size_t	_EXFUN(_mbrtowc_r, (struct _reent *, wchar_t * , const char * , 
-			size_t, mbstate_t *));
-int	_EXFUN(mbsinit, (const mbstate_t *));
-size_t	_EXFUN(mbsnrtowcs, (wchar_t *__restrict, const char **__restrict,
-				size_t, size_t, mbstate_t *__restrict));
-size_t	_EXFUN(_mbsnrtowcs_r, (struct _reent *, wchar_t * , const char ** ,
-			size_t, size_t, mbstate_t *));
-size_t	_EXFUN(mbsrtowcs, (wchar_t *__restrict, const char **__restrict, size_t,
-				mbstate_t *__restrict));
-size_t	_EXFUN(_mbsrtowcs_r, (struct _reent *, wchar_t * , const char ** , size_t, mbstate_t *));
-size_t	_EXFUN(wcrtomb, (char *__restrict, wchar_t, mbstate_t *__restrict));
-size_t	_EXFUN(_wcrtomb_r, (struct _reent *, char * , wchar_t, mbstate_t *));
-size_t	_EXFUN(wcsnrtombs, (char *__restrict, const wchar_t **__restrict,
-				size_t, size_t, mbstate_t *__restrict));
-size_t	_EXFUN(_wcsnrtombs_r, (struct _reent *, char * , const wchar_t ** , 
-			size_t, size_t, mbstate_t *));
-size_t	_EXFUN(wcsrtombs, (char *__restrict, const wchar_t **__restrict,
-				size_t, mbstate_t *__restrict));
-size_t	_EXFUN(_wcsrtombs_r, (struct _reent *, char * , const wchar_t ** , 
-			size_t, mbstate_t *));
-int	_EXFUN(wcscasecmp, (const wchar_t *, const wchar_t *));
-wchar_t	*_EXFUN(wcscat, (wchar_t *__restrict, const wchar_t *__restrict));
-wchar_t	*_EXFUN(wcschr, (const wchar_t *, wchar_t));
-int	_EXFUN(wcscmp, (const wchar_t *, const wchar_t *));
-int	_EXFUN(wcscoll, (const wchar_t *, const wchar_t *));
-wchar_t	*_EXFUN(wcscpy, (wchar_t *__restrict, const wchar_t *__restrict));
-wchar_t	*_EXFUN(wcpcpy, (wchar_t *__restrict,
-				 const wchar_t *__restrict));
-wchar_t	*_EXFUN(wcsdup, (const wchar_t *));
-wchar_t	*_EXFUN(_wcsdup_r, (struct _reent *, const wchar_t * ));
-size_t	_EXFUN(wcscspn, (const wchar_t *, const wchar_t *));
-size_t  _EXFUN(wcsftime, (wchar_t *__restrict, size_t,
-				const wchar_t *__restrict, const struct tm *__restrict));
-size_t	_EXFUN(wcslcat, (wchar_t *, const wchar_t *, size_t));
-size_t	_EXFUN(wcslcpy, (wchar_t *, const wchar_t *, size_t));
-size_t	_EXFUN(wcslen, (const wchar_t *));
-int	_EXFUN(wcsncasecmp, (const wchar_t *, const wchar_t *, size_t));
-wchar_t	*_EXFUN(wcsncat, (wchar_t *__restrict,
-				 const wchar_t *__restrict, size_t));
-int	_EXFUN(wcsncmp, (const wchar_t *, const wchar_t *, size_t));
-wchar_t	*_EXFUN(wcsncpy, (wchar_t *__restrict,
-				 const wchar_t *__restrict, size_t));
-wchar_t	*_EXFUN(wcpncpy, (wchar_t *__restrict,
-				 const wchar_t *__restrict, size_t));
-size_t	_EXFUN(wcsnlen, (const wchar_t *, size_t));
-wchar_t	*_EXFUN(wcspbrk, (const wchar_t *, const wchar_t *));
-wchar_t	*_EXFUN(wcsrchr, (const wchar_t *, wchar_t));
-size_t	_EXFUN(wcsspn, (const wchar_t *, const wchar_t *));
-wchar_t	*_EXFUN(wcsstr, (const wchar_t *__restrict,
-				 const wchar_t *__restrict));
-wchar_t	*_EXFUN(wcstok, (wchar_t *__restrict, const wchar_t *__restrict,
-				 wchar_t **__restrict));
-double _EXFUN(wcstod, (const wchar_t *__restrict, wchar_t **__restrict));
-double _EXFUN(_wcstod_r, (struct _reent *, const wchar_t *, wchar_t **));
-float _EXFUN(wcstof, (const wchar_t *__restrict, wchar_t **__restrict));
-float _EXFUN(_wcstof_r, (struct _reent *, const wchar_t *, wchar_t **));
-#ifdef _LDBL_EQ_DBL
-long double _EXFUN(wcstold, (const wchar_t *, wchar_t **));
-#endif /* _LDBL_EQ_DBL */
-int	_EXFUN(wcswidth, (const wchar_t *, size_t));
-size_t	_EXFUN(wcsxfrm, (wchar_t *__restrict, const wchar_t *__restrict,
-				size_t));
-int	_EXFUN(wcwidth, (const wchar_t));
-wchar_t	*_EXFUN(wmemchr, (const wchar_t *, wchar_t, size_t));
-int	_EXFUN(wmemcmp, (const wchar_t *, const wchar_t *, size_t));
-wchar_t	*_EXFUN(wmemcpy, (wchar_t *__restrict, const wchar_t *__restrict,
-				 size_t));
-wchar_t	*_EXFUN(wmemmove, (wchar_t *, const wchar_t *, size_t));
-wchar_t	*_EXFUN(wmemset, (wchar_t *, wchar_t, size_t));
-
-long    _EXFUN(wcstol, (const wchar_t *__restrict, wchar_t **__restrict, int));
-long long _EXFUN(wcstoll, (const wchar_t *__restrict, wchar_t **__restrict,
-				  int));
-unsigned long _EXFUN(wcstoul, (const wchar_t *__restrict, wchar_t **__restrict,
-					  int));
-unsigned long long _EXFUN(wcstoull, (const wchar_t *__restrict,
-						   wchar_t **__restrict, int));
-long    _EXFUN(_wcstol_r, (struct _reent *, const wchar_t *, wchar_t **, int));
-long long _EXFUN(_wcstoll_r, (struct _reent *, const wchar_t *, wchar_t **, int));
-unsigned long _EXFUN(_wcstoul_r, (struct _reent *, const wchar_t *, wchar_t **, int));
-unsigned long long _EXFUN(_wcstoull_r, (struct _reent *, const wchar_t *, wchar_t **, int));
-/* On platforms where long double equals double.  */
-#ifdef _LDBL_EQ_DBL
-long double _EXFUN(wcstold, (const wchar_t *, wchar_t **));
-#endif /* _LDBL_EQ_DBL */
-
-wint_t _EXFUN(fgetwc, (__FILE *));
-wchar_t *_EXFUN(fgetws, (wchar_t *__restrict, int, __FILE *__restrict));
-wint_t _EXFUN(fputwc, (wchar_t, __FILE *));
-int _EXFUN(fputws, (const wchar_t *__restrict, __FILE *__restrict));
-int _EXFUN (fwide, (__FILE *, int));
-wint_t _EXFUN (getwc, (__FILE *));
-wint_t _EXFUN (getwchar, (void));
-wint_t _EXFUN(putwc, (wchar_t, __FILE *));
-wint_t _EXFUN(putwchar, (wchar_t));
-wint_t _EXFUN (ungetwc, (wint_t wc, __FILE *));
-
-wint_t _EXFUN(_fgetwc_r, (struct _reent *, __FILE *));
-wint_t _EXFUN(_fgetwc_unlocked_r, (struct _reent *, __FILE *));
-wchar_t *_EXFUN(_fgetws_r, (struct _reent *, wchar_t *, int, __FILE *));
-wchar_t *_EXFUN(_fgetws_unlocked_r, (struct _reent *, wchar_t *, int, __FILE *));
-wint_t _EXFUN(_fputwc_r, (struct _reent *, wchar_t, __FILE *));
-wint_t _EXFUN(_fputwc_unlocked_r, (struct _reent *, wchar_t, __FILE *));
-int _EXFUN(_fputws_r, (struct _reent *, const wchar_t *, __FILE *));
-int _EXFUN(_fputws_unlocked_r, (struct _reent *, const wchar_t *, __FILE *));
-int _EXFUN (_fwide_r, (struct _reent *, __FILE *, int));
-wint_t _EXFUN (_getwc_r, (struct _reent *, __FILE *));
-wint_t _EXFUN (_getwc_unlocked_r, (struct _reent *, __FILE *));
-wint_t _EXFUN (_getwchar_r, (struct _reent *ptr));
-wint_t _EXFUN (_getwchar_unlocked_r, (struct _reent *ptr));
-wint_t _EXFUN(_putwc_r, (struct _reent *, wchar_t, __FILE *));
-wint_t _EXFUN(_putwc_unlocked_r, (struct _reent *, wchar_t, __FILE *));
-wint_t _EXFUN(_putwchar_r, (struct _reent *, wchar_t));
-wint_t _EXFUN(_putwchar_unlocked_r, (struct _reent *, wchar_t));
-wint_t _EXFUN (_ungetwc_r, (struct _reent *, wint_t wc, __FILE *));
-
-#if __GNU_VISIBLE
-wint_t _EXFUN(fgetwc_unlocked, (__FILE *));
-wchar_t *_EXFUN(fgetws_unlocked, (wchar_t *__restrict, int, __FILE *__restrict));
-wint_t _EXFUN(fputwc_unlocked, (wchar_t, __FILE *));
-int _EXFUN(fputws_unlocked, (const wchar_t *__restrict, __FILE *__restrict));
-wint_t _EXFUN(getwc_unlocked, (__FILE *));
-wint_t _EXFUN(getwchar_unlocked, (void));
-wint_t _EXFUN(putwc_unlocked, (wchar_t, __FILE *));
-wint_t _EXFUN(putwchar_unlocked, (wchar_t));
-#endif
-
-__FILE *_EXFUN (open_wmemstream, (wchar_t **, size_t *));
-__FILE *_EXFUN (_open_wmemstream_r, (struct _reent *, wchar_t **, size_t *));
-
-#ifndef __VALIST
-#ifdef __GNUC__
-#define __VALIST __gnuc_va_list
-#else
-#define __VALIST char*
-#endif
-#endif
-
-int	_EXFUN(fwprintf, (__FILE *__restrict, const wchar_t *__restrict, ...));
-int	_EXFUN(swprintf, (wchar_t *__restrict, size_t,
-			const wchar_t *__restrict, ...));
-int	_EXFUN(vfwprintf, (__FILE *__restrict, const wchar_t *__restrict,
-			__VALIST));
-int	_EXFUN(vswprintf, (wchar_t *__restrict, size_t,
-			const wchar_t *__restrict, __VALIST));
-int	_EXFUN(vwprintf, (const wchar_t *__restrict, __VALIST));
-int	_EXFUN(wprintf, (const wchar_t *__restrict, ...));
-
-int	_EXFUN(_fwprintf_r, (struct _reent *, __FILE *, const wchar_t *, ...));
-int	_EXFUN(_swprintf_r, (struct _reent *, wchar_t *, size_t, const wchar_t *, ...));
-int	_EXFUN(_vfwprintf_r, (struct _reent *, __FILE *, const wchar_t *, __VALIST));
-int	_EXFUN(_vswprintf_r, (struct _reent *, wchar_t *, size_t, const wchar_t *, __VALIST));
-int	_EXFUN(_vwprintf_r, (struct _reent *, const wchar_t *, __VALIST));
-int	_EXFUN(_wprintf_r, (struct _reent *, const wchar_t *, ...));
-
-int	_EXFUN(fwscanf, (__FILE *__restrict, const wchar_t *__restrict, ...));
-int	_EXFUN(swscanf, (const wchar_t *__restrict,
-			const wchar_t *__restrict, ...));
-int	_EXFUN(vfwscanf, (__FILE *__restrict, const wchar_t *__restrict,
-			__VALIST));
-int	_EXFUN(vswscanf, (const wchar_t *__restrict, const wchar_t *__restrict,
-			__VALIST));
-int	_EXFUN(vwscanf, (const wchar_t *__restrict, __VALIST));
-int	_EXFUN(wscanf, (const wchar_t *__restrict, ...));
-
-int	_EXFUN(_fwscanf_r, (struct _reent *, __FILE *, const wchar_t *, ...));
-int	_EXFUN(_swscanf_r, (struct _reent *, const wchar_t *, const wchar_t *, ...));
-int	_EXFUN(_vfwscanf_r, (struct _reent *, __FILE *, const wchar_t *, __VALIST));
-int	_EXFUN(_vswscanf_r, (struct _reent *, const wchar_t *, const wchar_t *, __VALIST));
-int	_EXFUN(_vwscanf_r, (struct _reent *, const wchar_t *, __VALIST));
-int	_EXFUN(_wscanf_r, (struct _reent *, const wchar_t *, ...));
-
-#define getwc(fp)	fgetwc(fp)
-#define putwc(wc,fp)	fputwc((wc), (fp))
-#define getwchar()	fgetwc(_REENT->_stdin)
-#define putwchar(wc)	fputwc((wc), _REENT->_stdout)
-
-#if __GNU_VISIBLE
-#define getwc_unlocked(fp)	fgetwc_unlocked(fp)
-#define putwc_unlocked(wc,fp)	fputwc_unlocked((wc), (fp))
-#define getwchar_unlocked()	fgetwc_unlocked(_REENT->_stdin)
-#define putwchar_unlocked(wc)	fputwc_unlocked((wc), _REENT->_stdout)
-#endif
-
-_END_STD_C
-
-#endif /* _WCHAR_H_ */
diff --git a/tools/sdk/include/newlib/wctype.h b/tools/sdk/include/newlib/wctype.h
deleted file mode 100644
index c72c9decff0..00000000000
--- a/tools/sdk/include/newlib/wctype.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef _WCTYPE_H_
-#define _WCTYPE_H_
-
-#include <_ansi.h>
-#include <sys/_types.h>
-
-#define __need_wint_t
-#include <stddef.h>
-
-#ifndef WEOF
-# define WEOF ((wint_t)-1)
-#endif
-
-_BEGIN_STD_C
-
-#ifndef _WCTYPE_T
-#define _WCTYPE_T
-typedef int wctype_t;
-#endif
-
-#ifndef _WCTRANS_T
-#define _WCTRANS_T
-typedef int wctrans_t;
-#endif
-
-int	_EXFUN(iswalpha, (wint_t));
-int	_EXFUN(iswalnum, (wint_t));
-int	_EXFUN(iswblank, (wint_t));
-int	_EXFUN(iswcntrl, (wint_t));
-int	_EXFUN(iswctype, (wint_t, wctype_t));
-int	_EXFUN(iswdigit, (wint_t));
-int	_EXFUN(iswgraph, (wint_t));
-int	_EXFUN(iswlower, (wint_t));
-int	_EXFUN(iswprint, (wint_t));
-int	_EXFUN(iswpunct, (wint_t));
-int	_EXFUN(iswspace, (wint_t));
-int	_EXFUN(iswupper, (wint_t));
-int	_EXFUN(iswxdigit, (wint_t));
-wint_t	_EXFUN(towctrans, (wint_t, wctrans_t));
-wint_t	_EXFUN(towupper, (wint_t));
-wint_t	_EXFUN(towlower, (wint_t));
-wctrans_t _EXFUN(wctrans, (const char *));
-wctype_t _EXFUN(wctype, (const char *));
-
-_END_STD_C
-
-#endif /* _WCTYPE_H_ */
diff --git a/tools/sdk/include/newlib/wordexp.h b/tools/sdk/include/newlib/wordexp.h
deleted file mode 100644
index 1f09a64c5ed..00000000000
--- a/tools/sdk/include/newlib/wordexp.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright (C) 2002, 2010 by  Red Hat, Incorporated. All rights reserved.
- *
- * Permission to use, copy, modify, and distribute this software
- * is freely granted, provided that this notice is preserved.
- */
-
-#ifndef _WORDEXP_H_
-#define _WORDEXP_H_
-
-#include <sys/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct _wordexp_t
-{
-  size_t we_wordc;	/* Count of words matched by words. */
-  char **we_wordv;	/* Pointer to list of expanded words. */
-  size_t we_offs;	/* Slots to reserve at the beginning of we_wordv. */
-};
-
-typedef struct _wordexp_t wordexp_t;
-
-#define	WRDE_DOOFFS	0x0001	/* Use we_offs. */
-#define	WRDE_APPEND	0x0002	/* Append to output from previous call. */
-#define	WRDE_NOCMD	0x0004	/* Don't perform command substitution. */
-#define	WRDE_REUSE	0x0008	/* pwordexp points to a wordexp_t struct returned from
-                                   a previous successful call to wordexp. */
-#define	WRDE_SHOWERR	0x0010	/* Print error messages to stderr. */
-#define	WRDE_UNDEF	0x0020	/* Report attempt to expand undefined shell variable. */
-
-enum {
-  WRDE_SUCCESS,
-  WRDE_NOSPACE,
-  WRDE_BADCHAR,
-  WRDE_BADVAL,
-  WRDE_CMDSUB,
-  WRDE_SYNTAX,
-  WRDE_NOSYS
-};
-
-/* Note: This implementation of wordexp requires a version of bash
-   that supports the --wordexp and --protected arguments to be present
-   on the system.  It does not support the WRDE_UNDEF flag. */
-int wordexp(const char *__restrict, wordexp_t *__restrict, int);
-void wordfree(wordexp_t *);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _WORDEXP_H_  */
diff --git a/tools/sdk/include/newlib/xtensa/config/core-isa.h b/tools/sdk/include/newlib/xtensa/config/core-isa.h
deleted file mode 100644
index f3f4e45f001..00000000000
--- a/tools/sdk/include/newlib/xtensa/config/core-isa.h
+++ /dev/null
@@ -1,655 +0,0 @@
-/* 
- * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
- *				processor CORE configuration
- *
- *  See <xtensa/config/core.h>, which includes this file, for more details.
- */
-
-/* Xtensa processor core configuration information.
-
-   Copyright (c) 1999-2016 Tensilica Inc.
-
-   Permission is hereby granted, free of charge, to any person obtaining
-   a copy of this software and associated documentation files (the
-   "Software"), to deal in the Software without restriction, including
-   without limitation the rights to use, copy, modify, merge, publish,
-   distribute, sublicense, and/or sell copies of the Software, and to
-   permit persons to whom the Software is furnished to do so, subject to
-   the following conditions:
-
-   The above copyright notice and this permission notice shall be included
-   in all copies or substantial portions of the Software.
-
-   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
-
-#ifndef _XTENSA_CORE_CONFIGURATION_H
-#define _XTENSA_CORE_CONFIGURATION_H
-
-
-/****************************************************************************
-	    Parameters Useful for Any Code, USER or PRIVILEGED
- ****************************************************************************/
-
-/*
- *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
- *  configured, and a value of 0 otherwise.  These macros are always defined.
- */
-
-
-/*----------------------------------------------------------------------
-				ISA
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
-#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
-#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
-#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
-#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
-#define XCHAL_HAVE_DEBUG		1	/* debug option */
-#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
-#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
-#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
-#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
-#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
-#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
-#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
-#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
-#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
-#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
-#define XCHAL_HAVE_MUL32_HIGH		1	/* MULUH/MULSH instructions */
-#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
-#define XCHAL_HAVE_L32R			1	/* L32R instruction */
-#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
-#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
-#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
-#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
-#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
-#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
-#define XCHAL_HAVE_ABS			1	/* ABS instruction */
-/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
-/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
-#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
-#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
-#define XCHAL_HAVE_SPECULATION		0	/* speculation */
-#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
-#define XCHAL_NUM_CONTEXTS		1	/* */
-#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
-#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
-#define XCHAL_HAVE_PRID			1	/* processor ID register */
-#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
-#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
-#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
-#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
-#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
-#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
-#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
-#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
-#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
-#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
-#define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
-#define XCHAL_HAVE_MAC16		1	/* MAC16 package */
-
-#define XCHAL_HAVE_FUSION		 0	/* Fusion*/
-#define XCHAL_HAVE_FUSION_FP	 0	        /* Fusion FP option */
-#define XCHAL_HAVE_FUSION_LOW_POWER 0	/* Fusion Low Power option */
-#define XCHAL_HAVE_FUSION_AES	 0	        /* Fusion BLE/Wifi AES-128 CCM option */
-#define XCHAL_HAVE_FUSION_CONVENC	 0       /* Fusion Conv Encode option */
-#define XCHAL_HAVE_FUSION_LFSR_CRC	 0	/* Fusion LFSR-CRC option */
-#define XCHAL_HAVE_FUSION_BITOPS	 0	/* Fusion Bit Operations Support option */
-#define XCHAL_HAVE_FUSION_AVS	 0	/* Fusion AVS option */
-#define XCHAL_HAVE_FUSION_16BIT_BASEBAND	 0	/* Fusion 16-bit Baseband option */
-#define XCHAL_HAVE_FUSION_VITERBI        0     /* Fusion Viterbi option */
-#define XCHAL_HAVE_FUSION_SOFTDEMAP      0   /* Fusion Soft Bit Demap option */
-#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI3		0	/* HiFi3 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
-#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
-#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
-#define XCHAL_HAVE_HIFI_MINI		0	
-
-
-#define XCHAL_HAVE_VECTORFPU2005	0	/* vector or user floating-point pkg */
-#define XCHAL_HAVE_USER_DPFPU         0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_USER_SPFPU         0       /* user DP floating-point pkg */
-#define XCHAL_HAVE_FP                 1      /* single prec floating point */
-#define XCHAL_HAVE_FP_DIV             1  /* FP with DIV instructions */
-#define XCHAL_HAVE_FP_RECIP           1        /* FP with RECIP instructions */
-#define XCHAL_HAVE_FP_SQRT            1 /* FP with SQRT instructions */
-#define XCHAL_HAVE_FP_RSQRT           1        /* FP with RSQRT instructions */
-#define XCHAL_HAVE_DFP                        0     /* double precision FP pkg */
-#define XCHAL_HAVE_DFP_DIV            0 /* DFP with DIV instructions */
-#define XCHAL_HAVE_DFP_RECIP          0       /* DFP with RECIP instructions*/
-#define XCHAL_HAVE_DFP_SQRT           0        /* DFP with SQRT instructions */
-#define XCHAL_HAVE_DFP_RSQRT          0       /* DFP with RSQRT instructions*/
-#define XCHAL_HAVE_DFP_ACCEL		1	/* double precision FP acceleration pkg */
-#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL				/* for backward compatibility */
-
-#define XCHAL_HAVE_DFPU_SINGLE_ONLY    1                 	/* DFPU Coprocessor, single precision only */
-#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  0               	/* DFPU Coprocessor, single and double precision */
-#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
-#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
-#define XCHAL_HAVE_PDX4		        0	/* PDX4 */
-#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
-#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
-#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
-#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
-#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
-#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
-#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
-#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
-#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
-#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
-#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
-#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
-#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
-#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
-#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
-#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */
-
-
-/*----------------------------------------------------------------------
-				MISC
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */
-#define XCHAL_NUM_WRITEBUFFER_ENTRIES	4	/* size of write buffer */
-#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
-#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
-#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
-						   (1 = 5-stage, 2 = 7-stage) */
-#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
-#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
-/*  In T1050, applies to selected core load and store instructions (see ISA): */
-#define XCHAL_UNALIGNED_LOAD_EXCEPTION	0	/* unaligned loads cause exc. */
-#define XCHAL_UNALIGNED_STORE_EXCEPTION	0	/* unaligned stores cause exc.*/
-#define XCHAL_UNALIGNED_LOAD_HW		1	/* unaligned loads work in hw */
-#define XCHAL_UNALIGNED_STORE_HW	1	/* unaligned stores work in hw*/
-
-#define XCHAL_SW_VERSION		1100003	/* sw version of this header */
-
-#define XCHAL_CORE_ID			"esp32_v3_49_prod"	/* alphanum core name
-						   (CoreID) set in the Xtensa
-						   Processor Generator */
-
-#define XCHAL_BUILD_UNIQUE_ID		0x0005FE96	/* 22-bit sw build ID */
-
-/*
- *  These definitions describe the hardware targeted by this software.
- */
-#define XCHAL_HW_CONFIGID0		0xC2BCFFFE	/* ConfigID hi 32 bits*/
-#define XCHAL_HW_CONFIGID1		0x1CC5FE96	/* ConfigID lo 32 bits*/
-#define XCHAL_HW_VERSION_NAME		"LX6.0.3"	/* full version name */
-#define XCHAL_HW_VERSION_MAJOR		2600	/* major ver# of targeted hw */
-#define XCHAL_HW_VERSION_MINOR		3	/* minor ver# of targeted hw */
-#define XCHAL_HW_VERSION		260003	/* major*100+minor */
-#define XCHAL_HW_REL_LX6		1
-#define XCHAL_HW_REL_LX6_0		1
-#define XCHAL_HW_REL_LX6_0_3		1
-#define XCHAL_HW_CONFIGID_RELIABLE	1
-/*  If software targets a *range* of hardware versions, these are the bounds: */
-#define XCHAL_HW_MIN_VERSION_MAJOR	2600	/* major v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION_MINOR	3	/* minor v of earliest tgt hw */
-#define XCHAL_HW_MIN_VERSION		260003	/* earliest targeted hw */
-#define XCHAL_HW_MAX_VERSION_MAJOR	2600	/* major v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION_MINOR	3	/* minor v of latest tgt hw */
-#define XCHAL_HW_MAX_VERSION		260003	/* latest targeted hw */
-
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_ICACHE_LINESIZE		4	/* I-cache line size in bytes */
-#define XCHAL_DCACHE_LINESIZE		4	/* D-cache line size in bytes */
-#define XCHAL_ICACHE_LINEWIDTH		2	/* log2(I line size in bytes) */
-#define XCHAL_DCACHE_LINEWIDTH		2	/* log2(D line size in bytes) */
-
-#define XCHAL_ICACHE_SIZE		0	/* I-cache size in bytes or 0 */
-#define XCHAL_DCACHE_SIZE		0	/* D-cache size in bytes or 0 */
-
-#define XCHAL_DCACHE_IS_WRITEBACK	0	/* writeback feature */
-#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
-
-#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
-#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */
-#define XCHAL_PREFETCH_CASTOUT_LINES	0	/* dcache pref. castout bufsz */
-#define XCHAL_PREFETCH_ENTRIES		0	/* cache prefetch entries */
-#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
-#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
-#define XCHAL_HAVE_ICACHE_TEST		0	/* Icache test instructions */
-#define XCHAL_HAVE_DCACHE_TEST		0	/* Dcache test instructions */
-#define XCHAL_HAVE_ICACHE_DYN_WAYS	0	/* Icache dynamic way support */
-#define XCHAL_HAVE_DCACHE_DYN_WAYS	0	/* Dcache dynamic way support */
-
-
-
-
-/****************************************************************************
-    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
- ****************************************************************************/
-
-
-#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
-
-/*----------------------------------------------------------------------
-				CACHE
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
-#define XCHAL_HAVE_AXI			0	/* AXI bus */
-
-#define XCHAL_HAVE_PIF_WR_RESP			0	/* pif write response */
-#define XCHAL_HAVE_PIF_REQ_ATTR			0	/* pif attribute */
-
-/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
-
-/*  Number of cache sets in log2(lines per way):  */
-#define XCHAL_ICACHE_SETWIDTH		0
-#define XCHAL_DCACHE_SETWIDTH		0
-
-/*  Cache set associativity (number of ways):  */
-#define XCHAL_ICACHE_WAYS		1
-#define XCHAL_DCACHE_WAYS		1
-
-/*  Cache features:  */
-#define XCHAL_ICACHE_LINE_LOCKABLE	0
-#define XCHAL_DCACHE_LINE_LOCKABLE	0
-#define XCHAL_ICACHE_ECC_PARITY		0
-#define XCHAL_DCACHE_ECC_PARITY		0
-
-/*  Cache access size in bytes (affects operation of SICW instruction):  */
-#define XCHAL_ICACHE_ACCESS_SIZE	1
-#define XCHAL_DCACHE_ACCESS_SIZE	1
-
-#define XCHAL_DCACHE_BANKS		0	/* number of banks */
-
-/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
-#define XCHAL_CA_BITS			4
-
-
-/*----------------------------------------------------------------------
-			INTERNAL I/D RAM/ROMs and XLMI
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_NUM_INSTROM		1	/* number of core instr. ROMs */
-#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
-#define XCHAL_NUM_DATAROM		1	/* number of core data ROMs */
-#define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
-#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
-#define XCHAL_NUM_XLMI			1	/* number of core XLMI ports */
-
-/*  Instruction ROM 0:  */
-#define XCHAL_INSTROM0_VADDR		0x40800000	/* virtual address */
-#define XCHAL_INSTROM0_PADDR		0x40800000	/* physical address */
-#define XCHAL_INSTROM0_SIZE		4194304	/* size in bytes */
-#define XCHAL_INSTROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-/*  Instruction RAM 0:  */
-#define XCHAL_INSTRAM0_VADDR		0x40000000	/* virtual address */
-#define XCHAL_INSTRAM0_PADDR		0x40000000	/* physical address */
-#define XCHAL_INSTRAM0_SIZE		4194304	/* size in bytes */
-#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-/*  Instruction RAM 1:  */
-#define XCHAL_INSTRAM1_VADDR		0x40400000	/* virtual address */
-#define XCHAL_INSTRAM1_PADDR		0x40400000	/* physical address */
-#define XCHAL_INSTRAM1_SIZE		4194304	/* size in bytes */
-#define XCHAL_INSTRAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-/*  Data ROM 0:  */
-#define XCHAL_DATAROM0_VADDR		0x3F400000	/* virtual address */
-#define XCHAL_DATAROM0_PADDR		0x3F400000	/* physical address */
-#define XCHAL_DATAROM0_SIZE		4194304	/* size in bytes */
-#define XCHAL_DATAROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATAROM0_BANKS		1	/* number of banks */
-
-/*  Data RAM 0:  */
-#define XCHAL_DATARAM0_VADDR		0x3FF80000	/* virtual address */
-#define XCHAL_DATARAM0_PADDR		0x3FF80000	/* physical address */
-#define XCHAL_DATARAM0_SIZE		524288	/* size in bytes */
-#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM0_BANKS		1	/* number of banks */
-
-/*  Data RAM 1:  */
-#define XCHAL_DATARAM1_VADDR		0x3F800000	/* virtual address */
-#define XCHAL_DATARAM1_PADDR		0x3F800000	/* physical address */
-#define XCHAL_DATARAM1_SIZE		4194304	/* size in bytes */
-#define XCHAL_DATARAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
-#define XCHAL_DATARAM1_BANKS		1	/* number of banks */
-
-/*  XLMI Port 0:  */
-#define XCHAL_XLMI0_VADDR		0x3FF00000	/* virtual address */
-#define XCHAL_XLMI0_PADDR		0x3FF00000	/* physical address */
-#define XCHAL_XLMI0_SIZE		524288	/* size in bytes */
-#define XCHAL_XLMI0_ECC_PARITY	0	/* ECC/parity type, 0=none */
-
-#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
-
-
-/*----------------------------------------------------------------------
-			INTERRUPTS and TIMERS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
-#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
-#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
-#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
-#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
-#define XCHAL_NUM_INTERRUPTS		32	/* number of interrupts */
-#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
-#define XCHAL_NUM_EXTINTERRUPTS		26	/* num of external interrupts */
-#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
-						   (not including level zero) */
-#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
-	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
-
-/*  Masks of interrupts at each interrupt level:  */
-#define XCHAL_INTLEVEL1_MASK		0x000637FF
-#define XCHAL_INTLEVEL2_MASK		0x00380000
-#define XCHAL_INTLEVEL3_MASK		0x28C08800
-#define XCHAL_INTLEVEL4_MASK		0x53000000
-#define XCHAL_INTLEVEL5_MASK		0x84010000
-#define XCHAL_INTLEVEL6_MASK		0x00000000
-#define XCHAL_INTLEVEL7_MASK		0x00004000
-
-/*  Masks of interrupts at each range 1..n of interrupt levels:  */
-#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x000637FF
-#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x003E37FF
-#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x28FEBFFF
-#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x7BFEBFFF
-#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0xFFFFBFFF
-#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0xFFFFBFFF
-#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0xFFFFFFFF
-
-/*  Level of each interrupt:  */
-#define XCHAL_INT0_LEVEL		1
-#define XCHAL_INT1_LEVEL		1
-#define XCHAL_INT2_LEVEL		1
-#define XCHAL_INT3_LEVEL		1
-#define XCHAL_INT4_LEVEL		1
-#define XCHAL_INT5_LEVEL		1
-#define XCHAL_INT6_LEVEL		1
-#define XCHAL_INT7_LEVEL		1
-#define XCHAL_INT8_LEVEL		1
-#define XCHAL_INT9_LEVEL		1
-#define XCHAL_INT10_LEVEL		1
-#define XCHAL_INT11_LEVEL		3
-#define XCHAL_INT12_LEVEL		1
-#define XCHAL_INT13_LEVEL		1
-#define XCHAL_INT14_LEVEL		7
-#define XCHAL_INT15_LEVEL		3
-#define XCHAL_INT16_LEVEL		5
-#define XCHAL_INT17_LEVEL		1
-#define XCHAL_INT18_LEVEL		1
-#define XCHAL_INT19_LEVEL		2
-#define XCHAL_INT20_LEVEL		2
-#define XCHAL_INT21_LEVEL		2
-#define XCHAL_INT22_LEVEL		3
-#define XCHAL_INT23_LEVEL		3
-#define XCHAL_INT24_LEVEL		4
-#define XCHAL_INT25_LEVEL		4
-#define XCHAL_INT26_LEVEL		5
-#define XCHAL_INT27_LEVEL		3
-#define XCHAL_INT28_LEVEL		4
-#define XCHAL_INT29_LEVEL		3
-#define XCHAL_INT30_LEVEL		4
-#define XCHAL_INT31_LEVEL		5
-#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
-#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
-#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
-						   EXCSAVE/EPS/EPC_n, RFI n) */
-
-/*  Type of each interrupt:  */
-#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_PROFILING
-#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
-#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_TIMER
-#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT25_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT26_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT27_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-#define XCHAL_INT28_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT29_TYPE 	XTHAL_INTTYPE_SOFTWARE
-#define XCHAL_INT30_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
-#define XCHAL_INT31_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
-
-/*  Masks of interrupts for each type of interrupt:  */
-#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0x00000000
-#define XCHAL_INTTYPE_MASK_SOFTWARE	0x20000080
-#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x50400400
-#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x8FBE333F
-#define XCHAL_INTTYPE_MASK_TIMER	0x00018040
-#define XCHAL_INTTYPE_MASK_NMI		0x00004000
-#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
-#define XCHAL_INTTYPE_MASK_PROFILING	0x00000800
-
-/*  Interrupt numbers assigned to specific interrupt sources:  */
-#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
-#define XCHAL_TIMER1_INTERRUPT		15	/* CCOMPARE1 */
-#define XCHAL_TIMER2_INTERRUPT		16	/* CCOMPARE2 */
-#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
-#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
-#define XCHAL_PROFILING_INTERRUPT	11	/* profiling interrupt */
-
-/*  Interrupt numbers for levels at which only one interrupt is configured:  */
-#define XCHAL_INTLEVEL7_NUM		14
-/*  (There are many interrupts each at level(s) 1, 2, 3, 4, 5.)  */
-
-
-/*
- *  External interrupt mapping.
- *  These macros describe how Xtensa processor interrupt numbers
- *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
- *  map to external BInterrupt<n> pins, for those interrupts
- *  configured as external (level-triggered, edge-triggered, or NMI).
- *  See the Xtensa processor databook for more details.
- */
-
-/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
-#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
-#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
-#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
-#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
-#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
-#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
-#define XCHAL_EXTINT6_NUM		8	/* (intlevel 1) */
-#define XCHAL_EXTINT7_NUM		9	/* (intlevel 1) */
-#define XCHAL_EXTINT8_NUM		10	/* (intlevel 1) */
-#define XCHAL_EXTINT9_NUM		12	/* (intlevel 1) */
-#define XCHAL_EXTINT10_NUM		13	/* (intlevel 1) */
-#define XCHAL_EXTINT11_NUM		14	/* (intlevel 7) */
-#define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
-#define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
-#define XCHAL_EXTINT14_NUM		19	/* (intlevel 2) */
-#define XCHAL_EXTINT15_NUM		20	/* (intlevel 2) */
-#define XCHAL_EXTINT16_NUM		21	/* (intlevel 2) */
-#define XCHAL_EXTINT17_NUM		22	/* (intlevel 3) */
-#define XCHAL_EXTINT18_NUM		23	/* (intlevel 3) */
-#define XCHAL_EXTINT19_NUM		24	/* (intlevel 4) */
-#define XCHAL_EXTINT20_NUM		25	/* (intlevel 4) */
-#define XCHAL_EXTINT21_NUM		26	/* (intlevel 5) */
-#define XCHAL_EXTINT22_NUM		27	/* (intlevel 3) */
-#define XCHAL_EXTINT23_NUM		28	/* (intlevel 4) */
-#define XCHAL_EXTINT24_NUM		30	/* (intlevel 4) */
-#define XCHAL_EXTINT25_NUM		31	/* (intlevel 5) */
-/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
-#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
-#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
-#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
-#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
-#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
-#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
-#define XCHAL_INT8_EXTNUM		6	/* (intlevel 1) */
-#define XCHAL_INT9_EXTNUM		7	/* (intlevel 1) */
-#define XCHAL_INT10_EXTNUM		8	/* (intlevel 1) */
-#define XCHAL_INT12_EXTNUM		9	/* (intlevel 1) */
-#define XCHAL_INT13_EXTNUM		10	/* (intlevel 1) */
-#define XCHAL_INT14_EXTNUM		11	/* (intlevel 7) */
-#define XCHAL_INT17_EXTNUM		12	/* (intlevel 1) */
-#define XCHAL_INT18_EXTNUM		13	/* (intlevel 1) */
-#define XCHAL_INT19_EXTNUM		14	/* (intlevel 2) */
-#define XCHAL_INT20_EXTNUM		15	/* (intlevel 2) */
-#define XCHAL_INT21_EXTNUM		16	/* (intlevel 2) */
-#define XCHAL_INT22_EXTNUM		17	/* (intlevel 3) */
-#define XCHAL_INT23_EXTNUM		18	/* (intlevel 3) */
-#define XCHAL_INT24_EXTNUM		19	/* (intlevel 4) */
-#define XCHAL_INT25_EXTNUM		20	/* (intlevel 4) */
-#define XCHAL_INT26_EXTNUM		21	/* (intlevel 5) */
-#define XCHAL_INT27_EXTNUM		22	/* (intlevel 3) */
-#define XCHAL_INT28_EXTNUM		23	/* (intlevel 4) */
-#define XCHAL_INT30_EXTNUM		24	/* (intlevel 4) */
-#define XCHAL_INT31_EXTNUM		25	/* (intlevel 5) */
-
-
-/*----------------------------------------------------------------------
-			EXCEPTIONS and VECTORS
-  ----------------------------------------------------------------------*/
-
-#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
-						   number: 1 == XEA1 (old)
-							   2 == XEA2 (new)
-							   0 == XEAX (extern) or TX */
-#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
-#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
-#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
-#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
-#define XCHAL_HAVE_HALT			0	/* halt architecture option */
-#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
-#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
-#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
-#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
-#define XCHAL_VECBASE_RESET_VADDR	0x40000000  /* VECBASE reset value */
-#define XCHAL_VECBASE_RESET_PADDR	0x40000000
-#define XCHAL_RESET_VECBASE_OVERLAP	0
-
-#define XCHAL_RESET_VECTOR0_VADDR	0x50000000
-#define XCHAL_RESET_VECTOR0_PADDR	0x50000000
-#define XCHAL_RESET_VECTOR1_VADDR	0x40000400
-#define XCHAL_RESET_VECTOR1_PADDR	0x40000400
-#define XCHAL_RESET_VECTOR_VADDR	0x40000400
-#define XCHAL_RESET_VECTOR_PADDR	0x40000400
-#define XCHAL_USER_VECOFS		0x00000340
-#define XCHAL_USER_VECTOR_VADDR		0x40000340
-#define XCHAL_USER_VECTOR_PADDR		0x40000340
-#define XCHAL_KERNEL_VECOFS		0x00000300
-#define XCHAL_KERNEL_VECTOR_VADDR	0x40000300
-#define XCHAL_KERNEL_VECTOR_PADDR	0x40000300
-#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
-#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x400003C0
-#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x400003C0
-#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
-#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
-#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
-#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
-#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
-#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
-#define XCHAL_WINDOW_VECTORS_VADDR	0x40000000
-#define XCHAL_WINDOW_VECTORS_PADDR	0x40000000
-#define XCHAL_INTLEVEL2_VECOFS		0x00000180
-#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x40000180
-#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x40000180
-#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
-#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x400001C0
-#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x400001C0
-#define XCHAL_INTLEVEL4_VECOFS		0x00000200
-#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x40000200
-#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x40000200
-#define XCHAL_INTLEVEL5_VECOFS		0x00000240
-#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x40000240
-#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x40000240
-#define XCHAL_INTLEVEL6_VECOFS		0x00000280
-#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x40000280
-#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x40000280
-#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
-#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
-#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
-#define XCHAL_NMI_VECOFS		0x000002C0
-#define XCHAL_NMI_VECTOR_VADDR		0x400002C0
-#define XCHAL_NMI_VECTOR_PADDR		0x400002C0
-#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
-#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
-#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
-
-
-/*----------------------------------------------------------------------
-				DEBUG MODULE
-  ----------------------------------------------------------------------*/
-
-/*  Misc  */
-#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
-#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
-#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
-
-/*  On-Chip Debug (OCD)  */
-#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
-#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
-#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
-#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
-
-/*  TRAX (in core)  */
-#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
-#define XCHAL_TRAX_MEM_SIZE		16384	/* TRAX memory size in bytes */
-#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
-#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
-#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
-
-/*  Perf counters  */
-#define XCHAL_NUM_PERF_COUNTERS		2	/* performance counters */
-
-
-/*----------------------------------------------------------------------
-				MMU
-  ----------------------------------------------------------------------*/
-
-/*  See core-matmap.h header file for more details.  */
-
-#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
-#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
-#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
-#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
-#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
-#define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
-#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
-#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
-						   [autorefill] and protection)
-						   usable for an MMU-based OS */
-/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
-
-#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
-#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
-#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
-
-#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
-
-#endif /* _XTENSA_CORE_CONFIGURATION_H */
-
diff --git a/tools/sdk/include/nghttp/config.h b/tools/sdk/include/nghttp/config.h
deleted file mode 100644
index f193b0afcad..00000000000
--- a/tools/sdk/include/nghttp/config.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef __HAVE_CONFIG_H_
-#define __HAVE_CONFIG_H_
-
-#define _U_
-
-#define SIZEOF_INT_P 2
-
-//#define DEBUGBUILD
-#include "stdio.h"
-#include "stdlib.h"
-#include "string.h"
-
-#if (!defined(nghttp_unlikely))
-#define nghttp_unlikely(Expression)	!!(Expression)
-#endif
-
-#define nghttp_ASSERT(Expression) do{if (!(Expression)) printf("%d\n", __LINE__);}while(0)
-
-#define CU_ASSERT(a) nghttp_ASSERT(a)
-#define CU_ASSERT_FATAL(a) nghttp_ASSERT(a)
-
-#if 1
-#define NGHTTP2_DEBUG_INFO() printf("%s %d\n", __FILE__, __LINE__)
-#else
-#define NGHTTP2_DEBUG_INFO()
-#endif
-
-#define NGHTTP_PLATFORM_HTONS(_n)  ((uint16_t)((((_n) & 0xff) << 8) | (((_n) >> 8) & 0xff)))
-#define NGHTTP_PLATFORM_HTONL(_n)  ((uint32_t)( (((_n) & 0xff) << 24) | (((_n) & 0xff00) << 8) | (((_n) >> 8)  & 0xff00) | (((_n) >> 24) & 0xff) ))
-
-#define htons(x) NGHTTP_PLATFORM_HTONS(x)
-#define ntohs(x) NGHTTP_PLATFORM_HTONS(x)
-#define htonl(x) NGHTTP_PLATFORM_HTONL(x)
-#define ntohl(x) NGHTTP_PLATFORM_HTONL(x)
-
-#endif
diff --git a/tools/sdk/include/nghttp/http_parser.h b/tools/sdk/include/nghttp/http_parser.h
deleted file mode 100644
index 105ae510a8a..00000000000
--- a/tools/sdk/include/nghttp/http_parser.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/* Copyright Joyent, Inc. and other Node contributors. All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-#ifndef http_parser_h
-#define http_parser_h
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Also update SONAME in the Makefile whenever you change these. */
-#define HTTP_PARSER_VERSION_MAJOR 2
-#define HTTP_PARSER_VERSION_MINOR 7
-#define HTTP_PARSER_VERSION_PATCH 0
-
-#include <sys/types.h>
-#if defined(_WIN32) && !defined(__MINGW32__) && \
-  (!defined(_MSC_VER) || _MSC_VER<1600) && !defined(__WINE__)
-#include <BaseTsd.h>
-#include <stddef.h>
-typedef __int8 int8_t;
-typedef unsigned __int8 uint8_t;
-typedef __int16 int16_t;
-typedef unsigned __int16 uint16_t;
-typedef __int32 int32_t;
-typedef unsigned __int32 uint32_t;
-typedef __int64 int64_t;
-typedef unsigned __int64 uint64_t;
-#else
-#include <stdint.h>
-#endif
-
-/* Compile with -DHTTP_PARSER_STRICT=0 to make less checks, but run
- * faster
- */
-#ifndef HTTP_PARSER_STRICT
-# define HTTP_PARSER_STRICT 1
-#endif
-
-/* Maximium header size allowed. If the macro is not defined
- * before including this header then the default is used. To
- * change the maximum header size, define the macro in the build
- * environment (e.g. -DHTTP_MAX_HEADER_SIZE=<value>). To remove
- * the effective limit on the size of the header, define the macro
- * to a very large number (e.g. -DHTTP_MAX_HEADER_SIZE=0x7fffffff)
- */
-#ifndef HTTP_MAX_HEADER_SIZE
-# define HTTP_MAX_HEADER_SIZE (80*1024)
-#endif
-
-typedef struct http_parser http_parser;
-typedef struct http_parser_settings http_parser_settings;
-
-
-/* Callbacks should return non-zero to indicate an error. The parser will
- * then halt execution.
- *
- * The one exception is on_headers_complete. In a HTTP_RESPONSE parser
- * returning '1' from on_headers_complete will tell the parser that it
- * should not expect a body. This is used when receiving a response to a
- * HEAD request which may contain 'Content-Length' or 'Transfer-Encoding:
- * chunked' headers that indicate the presence of a body.
- *
- * Returning `2` from on_headers_complete will tell parser that it should not
- * expect neither a body nor any futher responses on this connection. This is
- * useful for handling responses to a CONNECT request which may not contain
- * `Upgrade` or `Connection: upgrade` headers.
- *
- * http_data_cb does not return data chunks. It will be called arbitrarily
- * many times for each string. E.G. you might get 10 callbacks for "on_url"
- * each providing just a few characters more data.
- */
-typedef int (*http_data_cb) (http_parser*, const char *at, size_t length);
-typedef int (*http_cb) (http_parser*);
-
-
-/* Request Methods */
-#define HTTP_METHOD_MAP(XX)         \
-  XX(0,  DELETE,      DELETE)       \
-  XX(1,  GET,         GET)          \
-  XX(2,  HEAD,        HEAD)         \
-  XX(3,  POST,        POST)         \
-  XX(4,  PUT,         PUT)          \
-  /* pathological */                \
-  XX(5,  CONNECT,     CONNECT)      \
-  XX(6,  OPTIONS,     OPTIONS)      \
-  XX(7,  TRACE,       TRACE)        \
-  /* WebDAV */                      \
-  XX(8,  COPY,        COPY)         \
-  XX(9,  LOCK,        LOCK)         \
-  XX(10, MKCOL,       MKCOL)        \
-  XX(11, MOVE,        MOVE)         \
-  XX(12, PROPFIND,    PROPFIND)     \
-  XX(13, PROPPATCH,   PROPPATCH)    \
-  XX(14, SEARCH,      SEARCH)       \
-  XX(15, UNLOCK,      UNLOCK)       \
-  XX(16, BIND,        BIND)         \
-  XX(17, REBIND,      REBIND)       \
-  XX(18, UNBIND,      UNBIND)       \
-  XX(19, ACL,         ACL)          \
-  /* subversion */                  \
-  XX(20, REPORT,      REPORT)       \
-  XX(21, MKACTIVITY,  MKACTIVITY)   \
-  XX(22, CHECKOUT,    CHECKOUT)     \
-  XX(23, MERGE,       MERGE)        \
-  /* upnp */                        \
-  XX(24, MSEARCH,     M-SEARCH)     \
-  XX(25, NOTIFY,      NOTIFY)       \
-  XX(26, SUBSCRIBE,   SUBSCRIBE)    \
-  XX(27, UNSUBSCRIBE, UNSUBSCRIBE)  \
-  /* RFC-5789 */                    \
-  XX(28, PATCH,       PATCH)        \
-  XX(29, PURGE,       PURGE)        \
-  /* CalDAV */                      \
-  XX(30, MKCALENDAR,  MKCALENDAR)   \
-  /* RFC-2068, section 19.6.1.2 */  \
-  XX(31, LINK,        LINK)         \
-  XX(32, UNLINK,      UNLINK)       \
-
-enum http_method
-  {
-#define XX(num, name, string) HTTP_##name = num,
-  HTTP_METHOD_MAP(XX)
-#undef XX
-  };
-
-
-enum http_parser_type { HTTP_REQUEST, HTTP_RESPONSE, HTTP_BOTH };
-
-
-/* Flag values for http_parser.flags field */
-enum flags
-  { F_CHUNKED               = 1 << 0
-  , F_CONNECTION_KEEP_ALIVE = 1 << 1
-  , F_CONNECTION_CLOSE      = 1 << 2
-  , F_CONNECTION_UPGRADE    = 1 << 3
-  , F_TRAILING              = 1 << 4
-  , F_UPGRADE               = 1 << 5
-  , F_SKIPBODY              = 1 << 6
-  , F_CONTENTLENGTH         = 1 << 7
-  };
-
-
-/* Map for errno-related constants
- *
- * The provided argument should be a macro that takes 2 arguments.
- */
-#define HTTP_ERRNO_MAP(XX)                                           \
-  /* No error */                                                     \
-  XX(OK, "success")                                                  \
-                                                                     \
-  /* Callback-related errors */                                      \
-  XX(CB_message_begin, "the on_message_begin callback failed")       \
-  XX(CB_url, "the on_url callback failed")                           \
-  XX(CB_header_field, "the on_header_field callback failed")         \
-  XX(CB_header_value, "the on_header_value callback failed")         \
-  XX(CB_headers_complete, "the on_headers_complete callback failed") \
-  XX(CB_body, "the on_body callback failed")                         \
-  XX(CB_message_complete, "the on_message_complete callback failed") \
-  XX(CB_status, "the on_status callback failed")                     \
-  XX(CB_chunk_header, "the on_chunk_header callback failed")         \
-  XX(CB_chunk_complete, "the on_chunk_complete callback failed")     \
-                                                                     \
-  /* Parsing-related errors */                                       \
-  XX(INVALID_EOF_STATE, "stream ended at an unexpected time")        \
-  XX(HEADER_OVERFLOW,                                                \
-     "too many header bytes seen; overflow detected")                \
-  XX(CLOSED_CONNECTION,                                              \
-     "data received after completed connection: close message")      \
-  XX(INVALID_VERSION, "invalid HTTP version")                        \
-  XX(INVALID_STATUS, "invalid HTTP status code")                     \
-  XX(INVALID_METHOD, "invalid HTTP method")                          \
-  XX(INVALID_URL, "invalid URL")                                     \
-  XX(INVALID_HOST, "invalid host")                                   \
-  XX(INVALID_PORT, "invalid port")                                   \
-  XX(INVALID_PATH, "invalid path")                                   \
-  XX(INVALID_QUERY_STRING, "invalid query string")                   \
-  XX(INVALID_FRAGMENT, "invalid fragment")                           \
-  XX(LF_EXPECTED, "LF character expected")                           \
-  XX(INVALID_HEADER_TOKEN, "invalid character in header")            \
-  XX(INVALID_CONTENT_LENGTH,                                         \
-     "invalid character in content-length header")                   \
-  XX(UNEXPECTED_CONTENT_LENGTH,                                      \
-     "unexpected content-length header")                             \
-  XX(INVALID_CHUNK_SIZE,                                             \
-     "invalid character in chunk size header")                       \
-  XX(INVALID_CONSTANT, "invalid constant string")                    \
-  XX(INVALID_INTERNAL_STATE, "encountered unexpected internal state")\
-  XX(STRICT, "strict mode assertion failed")                         \
-  XX(PAUSED, "parser is paused")                                     \
-  XX(UNKNOWN, "an unknown error occurred")
-
-
-/* Define HPE_* values for each errno value above */
-#define HTTP_ERRNO_GEN(n, s) HPE_##n,
-enum http_errno {
-  HTTP_ERRNO_MAP(HTTP_ERRNO_GEN)
-};
-#undef HTTP_ERRNO_GEN
-
-
-/* Get an http_errno value from an http_parser */
-#define HTTP_PARSER_ERRNO(p)            ((enum http_errno) (p)->http_errno)
-
-
-struct http_parser {
-  /** PRIVATE **/
-  unsigned int type : 2;         /* enum http_parser_type */
-  unsigned int flags : 8;        /* F_* values from 'flags' enum; semi-public */
-  unsigned int state : 7;        /* enum state from http_parser.c */
-  unsigned int header_state : 7; /* enum header_state from http_parser.c */
-  unsigned int index : 7;        /* index into current matcher */
-  unsigned int lenient_http_headers : 1;
-
-  uint32_t nread;          /* # bytes read in various scenarios */
-  uint64_t content_length; /* # bytes in body (0 if no Content-Length header) */
-
-  /** READ-ONLY **/
-  unsigned short http_major;
-  unsigned short http_minor;
-  unsigned int status_code : 16; /* responses only */
-  unsigned int method : 8;       /* requests only */
-  unsigned int http_errno : 7;
-
-  /* 1 = Upgrade header was present and the parser has exited because of that.
-   * 0 = No upgrade header present.
-   * Should be checked when http_parser_execute() returns in addition to
-   * error checking.
-   */
-  unsigned int upgrade : 1;
-
-  /** PUBLIC **/
-  void *data; /* A pointer to get hook to the "connection" or "socket" object */
-};
-
-
-struct http_parser_settings {
-  http_cb      on_message_begin;
-  http_data_cb on_url;
-  http_data_cb on_status;
-  http_data_cb on_header_field;
-  http_data_cb on_header_value;
-  http_cb      on_headers_complete;
-  http_data_cb on_body;
-  http_cb      on_message_complete;
-  /* When on_chunk_header is called, the current chunk length is stored
-   * in parser->content_length.
-   */
-  http_cb      on_chunk_header;
-  http_cb      on_chunk_complete;
-};
-
-
-enum http_parser_url_fields
-  { UF_SCHEMA           = 0
-  , UF_HOST             = 1
-  , UF_PORT             = 2
-  , UF_PATH             = 3
-  , UF_QUERY            = 4
-  , UF_FRAGMENT         = 5
-  , UF_USERINFO         = 6
-  , UF_MAX              = 7
-  };
-
-
-/* Result structure for http_parser_parse_url().
- *
- * Callers should index into field_data[] with UF_* values iff field_set
- * has the relevant (1 << UF_*) bit set. As a courtesy to clients (and
- * because we probably have padding left over), we convert any port to
- * a uint16_t.
- */
-struct http_parser_url {
-  uint16_t field_set;           /* Bitmask of (1 << UF_*) values */
-  uint16_t port;                /* Converted UF_PORT string */
-
-  struct {
-    uint16_t off;               /* Offset into buffer in which field starts */
-    uint16_t len;               /* Length of run in buffer */
-  } field_data[UF_MAX];
-};
-
-
-/* Returns the library version. Bits 16-23 contain the major version number,
- * bits 8-15 the minor version number and bits 0-7 the patch level.
- * Usage example:
- *
- *   unsigned long version = http_parser_version();
- *   unsigned major = (version >> 16) & 255;
- *   unsigned minor = (version >> 8) & 255;
- *   unsigned patch = version & 255;
- *   printf("http_parser v%u.%u.%u\n", major, minor, patch);
- */
-unsigned long http_parser_version(void);
-
-void http_parser_init(http_parser *parser, enum http_parser_type type);
-
-
-/* Initialize http_parser_settings members to 0
- */
-void http_parser_settings_init(http_parser_settings *settings);
-
-
-/* Executes the parser. Returns number of parsed bytes. Sets
- * `parser->http_errno` on error. */
-size_t http_parser_execute(http_parser *parser,
-                           const http_parser_settings *settings,
-                           const char *data,
-                           size_t len);
-
-
-/* If http_should_keep_alive() in the on_headers_complete or
- * on_message_complete callback returns 0, then this should be
- * the last message on the connection.
- * If you are the server, respond with the "Connection: close" header.
- * If you are the client, close the connection.
- */
-int http_should_keep_alive(const http_parser *parser);
-
-/* Returns a string version of the HTTP method. */
-const char *http_method_str(enum http_method m);
-
-/* Return a string name of the given error */
-const char *http_errno_name(enum http_errno err);
-
-/* Return a string description of the given error */
-const char *http_errno_description(enum http_errno err);
-
-/* Initialize all http_parser_url members to 0 */
-void http_parser_url_init(struct http_parser_url *u);
-
-/* Parse a URL; return nonzero on failure */
-int http_parser_parse_url(const char *buf, size_t buflen,
-                          int is_connect,
-                          struct http_parser_url *u);
-
-/* Pause or un-pause the parser; a nonzero value pauses */
-void http_parser_pause(http_parser *parser, int paused);
-
-/* Checks if this is the final chunk of the body. */
-int http_body_is_final(const http_parser *parser);
-
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/tools/sdk/include/nghttp/nghttp2/nghttp2.h b/tools/sdk/include/nghttp/nghttp2/nghttp2.h
deleted file mode 100644
index 1c74b35c667..00000000000
--- a/tools/sdk/include/nghttp/nghttp2/nghttp2.h
+++ /dev/null
@@ -1,5296 +0,0 @@
-/*
- * nghttp2 - HTTP/2 C Library
- *
- * Copyright (c) 2013, 2014 Tatsuhiro Tsujikawa
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef NGHTTP2_H
-#define NGHTTP2_H
-
-/* Define WIN32 when build target is Win32 API (borrowed from
-   libcurl) */
-#if (defined(_WIN32) || defined(__WIN32__)) && !defined(WIN32)
-#define WIN32
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdlib.h>
-#if defined(_MSC_VER) && (_MSC_VER < 1800)
-/* MSVC < 2013 does not have inttypes.h because it is not C99
-   compliant.  See compiler macros and version number in
-   https://sourceforge.net/p/predef/wiki/Compilers/ */
-#include <stdint.h>
-#else /* !defined(_MSC_VER) || (_MSC_VER >= 1800) */
-#include <inttypes.h>
-#endif /* !defined(_MSC_VER) || (_MSC_VER >= 1800) */
-#include <sys/types.h>
-#include <stdarg.h>
-
-#include <nghttp2/nghttp2ver.h>
-
-#ifdef NGHTTP2_STATICLIB
-#define NGHTTP2_EXTERN
-#elif defined(WIN32)
-#ifdef BUILDING_NGHTTP2
-#define NGHTTP2_EXTERN __declspec(dllexport)
-#else /* !BUILDING_NGHTTP2 */
-#define NGHTTP2_EXTERN __declspec(dllimport)
-#endif /* !BUILDING_NGHTTP2 */
-#else  /* !defined(WIN32) */
-#ifdef BUILDING_NGHTTP2
-#define NGHTTP2_EXTERN __attribute__((visibility("default")))
-#else /* !BUILDING_NGHTTP2 */
-#define NGHTTP2_EXTERN
-#endif /* !BUILDING_NGHTTP2 */
-#endif /* !defined(WIN32) */
-
-/**
- * @macro
- *
- * The protocol version identification string of this library
- * supports.  This identifier is used if HTTP/2 is used over TLS.
- */
-#define NGHTTP2_PROTO_VERSION_ID "h2"
-/**
- * @macro
- *
- * The length of :macro:`NGHTTP2_PROTO_VERSION_ID`.
- */
-#define NGHTTP2_PROTO_VERSION_ID_LEN 2
-
-/**
- * @macro
- *
- * The serialized form of ALPN protocol identifier this library
- * supports.  Notice that first byte is the length of following
- * protocol identifier.  This is the same wire format of `TLS ALPN
- * extension <https://tools.ietf.org/html/rfc7301>`_.  This is useful
- * to process incoming ALPN tokens in wire format.
- */
-#define NGHTTP2_PROTO_ALPN "\x2h2"
-
-/**
- * @macro
- *
- * The length of :macro:`NGHTTP2_PROTO_ALPN`.
- */
-#define NGHTTP2_PROTO_ALPN_LEN (sizeof(NGHTTP2_PROTO_ALPN) - 1)
-
-/**
- * @macro
- *
- * The protocol version identification string of this library
- * supports.  This identifier is used if HTTP/2 is used over cleartext
- * TCP.
- */
-#define NGHTTP2_CLEARTEXT_PROTO_VERSION_ID "h2c"
-
-/**
- * @macro
- *
- * The length of :macro:`NGHTTP2_CLEARTEXT_PROTO_VERSION_ID`.
- */
-#define NGHTTP2_CLEARTEXT_PROTO_VERSION_ID_LEN 3
-
-struct nghttp2_session;
-/**
- * @struct
- *
- * The primary structure to hold the resources needed for a HTTP/2
- * session.  The details of this structure are intentionally hidden
- * from the public API.
- */
-typedef struct nghttp2_session nghttp2_session;
-
-/**
- * @macro
- *
- * The age of :type:`nghttp2_info`
- */
-#define NGHTTP2_VERSION_AGE 1
-
-/**
- * @struct
- *
- * This struct is what `nghttp2_version()` returns.  It holds
- * information about the particular nghttp2 version.
- */
-typedef struct {
-  /**
-   * Age of this struct.  This instance of nghttp2 sets it to
-   * :macro:`NGHTTP2_VERSION_AGE` but a future version may bump it and
-   * add more struct fields at the bottom
-   */
-  int age;
-  /**
-   * the :macro:`NGHTTP2_VERSION_NUM` number (since age ==1)
-   */
-  int version_num;
-  /**
-   * points to the :macro:`NGHTTP2_VERSION` string (since age ==1)
-   */
-  const char *version_str;
-  /**
-   * points to the :macro:`NGHTTP2_PROTO_VERSION_ID` string this
-   * instance implements (since age ==1)
-   */
-  const char *proto_str;
-  /* -------- the above fields all exist when age == 1 */
-} nghttp2_info;
-
-/**
- * @macro
- *
- * The default weight of stream dependency.
- */
-#define NGHTTP2_DEFAULT_WEIGHT 16
-
-/**
- * @macro
- *
- * The maximum weight of stream dependency.
- */
-#define NGHTTP2_MAX_WEIGHT 256
-
-/**
- * @macro
- *
- * The minimum weight of stream dependency.
- */
-#define NGHTTP2_MIN_WEIGHT 1
-
-/**
- * @macro
- *
- * The maximum window size
- */
-#define NGHTTP2_MAX_WINDOW_SIZE ((int32_t)((1U << 31) - 1))
-
-/**
- * @macro
- *
- * The initial window size for stream level flow control.
- */
-#define NGHTTP2_INITIAL_WINDOW_SIZE ((1 << 16) - 1)
-/**
- * @macro
- *
- * The initial window size for connection level flow control.
- */
-#define NGHTTP2_INITIAL_CONNECTION_WINDOW_SIZE ((1 << 16) - 1)
-
-/**
- * @macro
- *
- * The default header table size.
- */
-#define NGHTTP2_DEFAULT_HEADER_TABLE_SIZE (1 << 12)
-
-/**
- * @macro
- *
- * The client magic string, which is the first 24 bytes byte string of
- * client connection preface.
- */
-#define NGHTTP2_CLIENT_MAGIC "PRI * HTTP/2.0\r\n\r\nSM\r\n\r\n"
-
-/**
- * @macro
- *
- * The length of :macro:`NGHTTP2_CLIENT_MAGIC`.
- */
-#define NGHTTP2_CLIENT_MAGIC_LEN 24
-
-/**
- * @enum
- *
- * Error codes used in this library.  The code range is [-999, -500],
- * inclusive. The following values are defined:
- */
-typedef enum {
-  /**
-   * Invalid argument passed.
-   */
-  NGHTTP2_ERR_INVALID_ARGUMENT = -501,
-  /**
-   * Out of buffer space.
-   */
-  NGHTTP2_ERR_BUFFER_ERROR = -502,
-  /**
-   * The specified protocol version is not supported.
-   */
-  NGHTTP2_ERR_UNSUPPORTED_VERSION = -503,
-  /**
-   * Used as a return value from :type:`nghttp2_send_callback`,
-   * :type:`nghttp2_recv_callback` and
-   * :type:`nghttp2_send_data_callback` to indicate that the operation
-   * would block.
-   */
-  NGHTTP2_ERR_WOULDBLOCK = -504,
-  /**
-   * General protocol error
-   */
-  NGHTTP2_ERR_PROTO = -505,
-  /**
-   * The frame is invalid.
-   */
-  NGHTTP2_ERR_INVALID_FRAME = -506,
-  /**
-   * The peer performed a shutdown on the connection.
-   */
-  NGHTTP2_ERR_EOF = -507,
-  /**
-   * Used as a return value from
-   * :func:`nghttp2_data_source_read_callback` to indicate that data
-   * transfer is postponed.  See
-   * :func:`nghttp2_data_source_read_callback` for details.
-   */
-  NGHTTP2_ERR_DEFERRED = -508,
-  /**
-   * Stream ID has reached the maximum value.  Therefore no stream ID
-   * is available.
-   */
-  NGHTTP2_ERR_STREAM_ID_NOT_AVAILABLE = -509,
-  /**
-   * The stream is already closed; or the stream ID is invalid.
-   */
-  NGHTTP2_ERR_STREAM_CLOSED = -510,
-  /**
-   * RST_STREAM has been added to the outbound queue.  The stream is
-   * in closing state.
-   */
-  NGHTTP2_ERR_STREAM_CLOSING = -511,
-  /**
-   * The transmission is not allowed for this stream (e.g., a frame
-   * with END_STREAM flag set has already sent).
-   */
-  NGHTTP2_ERR_STREAM_SHUT_WR = -512,
-  /**
-   * The stream ID is invalid.
-   */
-  NGHTTP2_ERR_INVALID_STREAM_ID = -513,
-  /**
-   * The state of the stream is not valid (e.g., DATA cannot be sent
-   * to the stream if response HEADERS has not been sent).
-   */
-  NGHTTP2_ERR_INVALID_STREAM_STATE = -514,
-  /**
-   * Another DATA frame has already been deferred.
-   */
-  NGHTTP2_ERR_DEFERRED_DATA_EXIST = -515,
-  /**
-   * Starting new stream is not allowed (e.g., GOAWAY has been sent
-   * and/or received).
-   */
-  NGHTTP2_ERR_START_STREAM_NOT_ALLOWED = -516,
-  /**
-   * GOAWAY has already been sent.
-   */
-  NGHTTP2_ERR_GOAWAY_ALREADY_SENT = -517,
-  /**
-   * The received frame contains the invalid header block (e.g., There
-   * are duplicate header names; or the header names are not encoded
-   * in US-ASCII character set and not lower cased; or the header name
-   * is zero-length string; or the header value contains multiple
-   * in-sequence NUL bytes).
-   */
-  NGHTTP2_ERR_INVALID_HEADER_BLOCK = -518,
-  /**
-   * Indicates that the context is not suitable to perform the
-   * requested operation.
-   */
-  NGHTTP2_ERR_INVALID_STATE = -519,
-  /**
-   * The user callback function failed due to the temporal error.
-   */
-  NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE = -521,
-  /**
-   * The length of the frame is invalid, either too large or too small.
-   */
-  NGHTTP2_ERR_FRAME_SIZE_ERROR = -522,
-  /**
-   * Header block inflate/deflate error.
-   */
-  NGHTTP2_ERR_HEADER_COMP = -523,
-  /**
-   * Flow control error
-   */
-  NGHTTP2_ERR_FLOW_CONTROL = -524,
-  /**
-   * Insufficient buffer size given to function.
-   */
-  NGHTTP2_ERR_INSUFF_BUFSIZE = -525,
-  /**
-   * Callback was paused by the application
-   */
-  NGHTTP2_ERR_PAUSE = -526,
-  /**
-   * There are too many in-flight SETTING frame and no more
-   * transmission of SETTINGS is allowed.
-   */
-  NGHTTP2_ERR_TOO_MANY_INFLIGHT_SETTINGS = -527,
-  /**
-   * The server push is disabled.
-   */
-  NGHTTP2_ERR_PUSH_DISABLED = -528,
-  /**
-   * DATA or HEADERS frame for a given stream has been already
-   * submitted and has not been fully processed yet.  Application
-   * should wait for the transmission of the previously submitted
-   * frame before submitting another.
-   */
-  NGHTTP2_ERR_DATA_EXIST = -529,
-  /**
-   * The current session is closing due to a connection error or
-   * `nghttp2_session_terminate_session()` is called.
-   */
-  NGHTTP2_ERR_SESSION_CLOSING = -530,
-  /**
-   * Invalid HTTP header field was received and stream is going to be
-   * closed.
-   */
-  NGHTTP2_ERR_HTTP_HEADER = -531,
-  /**
-   * Violation in HTTP messaging rule.
-   */
-  NGHTTP2_ERR_HTTP_MESSAGING = -532,
-  /**
-   * Stream was refused.
-   */
-  NGHTTP2_ERR_REFUSED_STREAM = -533,
-  /**
-   * Unexpected internal error, but recovered.
-   */
-  NGHTTP2_ERR_INTERNAL = -534,
-  /**
-   * Indicates that a processing was canceled.
-   */
-  NGHTTP2_ERR_CANCEL = -535,
-  /**
-   * The errors < :enum:`NGHTTP2_ERR_FATAL` mean that the library is
-   * under unexpected condition and processing was terminated (e.g.,
-   * out of memory).  If application receives this error code, it must
-   * stop using that :type:`nghttp2_session` object and only allowed
-   * operation for that object is deallocate it using
-   * `nghttp2_session_del()`.
-   */
-  NGHTTP2_ERR_FATAL = -900,
-  /**
-   * Out of memory.  This is a fatal error.
-   */
-  NGHTTP2_ERR_NOMEM = -901,
-  /**
-   * The user callback function failed.  This is a fatal error.
-   */
-  NGHTTP2_ERR_CALLBACK_FAILURE = -902,
-  /**
-   * Invalid client magic (see :macro:`NGHTTP2_CLIENT_MAGIC`) was
-   * received and further processing is not possible.
-   */
-  NGHTTP2_ERR_BAD_CLIENT_MAGIC = -903,
-  /**
-   * Possible flooding by peer was detected in this HTTP/2 session.
-   * Flooding is measured by how many PING and SETTINGS frames with
-   * ACK flag set are queued for transmission.  These frames are
-   * response for the peer initiated frames, and peer can cause memory
-   * exhaustion on server side to send these frames forever and does
-   * not read network.
-   */
-  NGHTTP2_ERR_FLOODED = -904
-} nghttp2_error;
-
-/**
- * @struct
- *
- * The object representing single contiguous buffer.
- */
-typedef struct {
-  /**
-   * The pointer to the buffer.
-   */
-  uint8_t *base;
-  /**
-   * The length of the buffer.
-   */
-  size_t len;
-} nghttp2_vec;
-
-struct nghttp2_rcbuf;
-
-/**
- * @struct
- *
- * The object representing reference counted buffer.  The details of
- * this structure are intentionally hidden from the public API.
- */
-typedef struct nghttp2_rcbuf nghttp2_rcbuf;
-
-/**
- * @function
- *
- * Increments the reference count of |rcbuf| by 1.
- */
-NGHTTP2_EXTERN void nghttp2_rcbuf_incref(nghttp2_rcbuf *rcbuf);
-
-/**
- * @function
- *
- * Decrements the reference count of |rcbuf| by 1.  If the reference
- * count becomes zero, the object pointed by |rcbuf| will be freed.
- * In this case, application must not use |rcbuf| again.
- */
-NGHTTP2_EXTERN void nghttp2_rcbuf_decref(nghttp2_rcbuf *rcbuf);
-
-/**
- * @function
- *
- * Returns the underlying buffer managed by |rcbuf|.
- */
-NGHTTP2_EXTERN nghttp2_vec nghttp2_rcbuf_get_buf(nghttp2_rcbuf *rcbuf);
-
-/**
- * @enum
- *
- * The flags for header field name/value pair.
- */
-typedef enum {
-  /**
-   * No flag set.
-   */
-  NGHTTP2_NV_FLAG_NONE = 0,
-  /**
-   * Indicates that this name/value pair must not be indexed ("Literal
-   * Header Field never Indexed" representation must be used in HPACK
-   * encoding).  Other implementation calls this bit as "sensitive".
-   */
-  NGHTTP2_NV_FLAG_NO_INDEX = 0x01,
-  /**
-   * This flag is set solely by application.  If this flag is set, the
-   * library does not make a copy of header field name.  This could
-   * improve performance.
-   */
-  NGHTTP2_NV_FLAG_NO_COPY_NAME = 0x02,
-  /**
-   * This flag is set solely by application.  If this flag is set, the
-   * library does not make a copy of header field value.  This could
-   * improve performance.
-   */
-  NGHTTP2_NV_FLAG_NO_COPY_VALUE = 0x04
-} nghttp2_nv_flag;
-
-/**
- * @struct
- *
- * The name/value pair, which mainly used to represent header fields.
- */
-typedef struct {
-  /**
-   * The |name| byte string.  If this struct is presented from library
-   * (e.g., :type:`nghttp2_on_frame_recv_callback`), |name| is
-   * guaranteed to be NULL-terminated.  For some callbacks
-   * (:type:`nghttp2_before_frame_send_callback`,
-   * :type:`nghttp2_on_frame_send_callback`, and
-   * :type:`nghttp2_on_frame_not_send_callback`), it may not be
-   * NULL-terminated if header field is passed from application with
-   * the flag :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`).  When application
-   * is constructing this struct, |name| is not required to be
-   * NULL-terminated.
-   */
-  uint8_t *name;
-  /**
-   * The |value| byte string.  If this struct is presented from
-   * library (e.g., :type:`nghttp2_on_frame_recv_callback`), |value|
-   * is guaranteed to be NULL-terminated.  For some callbacks
-   * (:type:`nghttp2_before_frame_send_callback`,
-   * :type:`nghttp2_on_frame_send_callback`, and
-   * :type:`nghttp2_on_frame_not_send_callback`), it may not be
-   * NULL-terminated if header field is passed from application with
-   * the flag :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE`).  When
-   * application is constructing this struct, |value| is not required
-   * to be NULL-terminated.
-   */
-  uint8_t *value;
-  /**
-   * The length of the |name|, excluding terminating NULL.
-   */
-  size_t namelen;
-  /**
-   * The length of the |value|, excluding terminating NULL.
-   */
-  size_t valuelen;
-  /**
-   * Bitwise OR of one or more of :type:`nghttp2_nv_flag`.
-   */
-  uint8_t flags;
-} nghttp2_nv;
-
-/**
- * @enum
- *
- * The frame types in HTTP/2 specification.
- */
-typedef enum {
-  /**
-   * The DATA frame.
-   */
-  NGHTTP2_DATA = 0,
-  /**
-   * The HEADERS frame.
-   */
-  NGHTTP2_HEADERS = 0x01,
-  /**
-   * The PRIORITY frame.
-   */
-  NGHTTP2_PRIORITY = 0x02,
-  /**
-   * The RST_STREAM frame.
-   */
-  NGHTTP2_RST_STREAM = 0x03,
-  /**
-   * The SETTINGS frame.
-   */
-  NGHTTP2_SETTINGS = 0x04,
-  /**
-   * The PUSH_PROMISE frame.
-   */
-  NGHTTP2_PUSH_PROMISE = 0x05,
-  /**
-   * The PING frame.
-   */
-  NGHTTP2_PING = 0x06,
-  /**
-   * The GOAWAY frame.
-   */
-  NGHTTP2_GOAWAY = 0x07,
-  /**
-   * The WINDOW_UPDATE frame.
-   */
-  NGHTTP2_WINDOW_UPDATE = 0x08,
-  /**
-   * The CONTINUATION frame.  This frame type won't be passed to any
-   * callbacks because the library processes this frame type and its
-   * preceding HEADERS/PUSH_PROMISE as a single frame.
-   */
-  NGHTTP2_CONTINUATION = 0x09,
-  /**
-   * The ALTSVC frame, which is defined in `RFC 7383
-   * <https://tools.ietf.org/html/rfc7838#section-4>`_.
-   */
-  NGHTTP2_ALTSVC = 0x0a
-} nghttp2_frame_type;
-
-/**
- * @enum
- *
- * The flags for HTTP/2 frames.  This enum defines all flags for all
- * frames.
- */
-typedef enum {
-  /**
-   * No flag set.
-   */
-  NGHTTP2_FLAG_NONE = 0,
-  /**
-   * The END_STREAM flag.
-   */
-  NGHTTP2_FLAG_END_STREAM = 0x01,
-  /**
-   * The END_HEADERS flag.
-   */
-  NGHTTP2_FLAG_END_HEADERS = 0x04,
-  /**
-   * The ACK flag.
-   */
-  NGHTTP2_FLAG_ACK = 0x01,
-  /**
-   * The PADDED flag.
-   */
-  NGHTTP2_FLAG_PADDED = 0x08,
-  /**
-   * The PRIORITY flag.
-   */
-  NGHTTP2_FLAG_PRIORITY = 0x20
-} nghttp2_flag;
-
-/**
- * @enum
- * The SETTINGS ID.
- */
-typedef enum {
-  /**
-   * SETTINGS_HEADER_TABLE_SIZE
-   */
-  NGHTTP2_SETTINGS_HEADER_TABLE_SIZE = 0x01,
-  /**
-   * SETTINGS_ENABLE_PUSH
-   */
-  NGHTTP2_SETTINGS_ENABLE_PUSH = 0x02,
-  /**
-   * SETTINGS_MAX_CONCURRENT_STREAMS
-   */
-  NGHTTP2_SETTINGS_MAX_CONCURRENT_STREAMS = 0x03,
-  /**
-   * SETTINGS_INITIAL_WINDOW_SIZE
-   */
-  NGHTTP2_SETTINGS_INITIAL_WINDOW_SIZE = 0x04,
-  /**
-   * SETTINGS_MAX_FRAME_SIZE
-   */
-  NGHTTP2_SETTINGS_MAX_FRAME_SIZE = 0x05,
-  /**
-   * SETTINGS_MAX_HEADER_LIST_SIZE
-   */
-  NGHTTP2_SETTINGS_MAX_HEADER_LIST_SIZE = 0x06
-} nghttp2_settings_id;
-/* Note: If we add SETTINGS, update the capacity of
-   NGHTTP2_INBOUND_NUM_IV as well */
-
-/**
- * @macro
- *
- * .. warning::
- *
- *   Deprecated.  The initial max concurrent streams is 0xffffffffu.
- *
- * Default maximum number of incoming concurrent streams.  Use
- * `nghttp2_submit_settings()` with
- * :enum:`NGHTTP2_SETTINGS_MAX_CONCURRENT_STREAMS` to change the
- * maximum number of incoming concurrent streams.
- *
- * .. note::
- *
- *   The maximum number of outgoing concurrent streams is 100 by
- *   default.
- */
-#define NGHTTP2_INITIAL_MAX_CONCURRENT_STREAMS ((1U << 31) - 1)
-
-/**
- * @enum
- * The status codes for the RST_STREAM and GOAWAY frames.
- */
-typedef enum {
-  /**
-   * No errors.
-   */
-  NGHTTP2_NO_ERROR = 0x00,
-  /**
-   * PROTOCOL_ERROR
-   */
-  NGHTTP2_PROTOCOL_ERROR = 0x01,
-  /**
-   * INTERNAL_ERROR
-   */
-  NGHTTP2_INTERNAL_ERROR = 0x02,
-  /**
-   * FLOW_CONTROL_ERROR
-   */
-  NGHTTP2_FLOW_CONTROL_ERROR = 0x03,
-  /**
-   * SETTINGS_TIMEOUT
-   */
-  NGHTTP2_SETTINGS_TIMEOUT = 0x04,
-  /**
-   * STREAM_CLOSED
-   */
-  NGHTTP2_STREAM_CLOSED = 0x05,
-  /**
-   * FRAME_SIZE_ERROR
-   */
-  NGHTTP2_FRAME_SIZE_ERROR = 0x06,
-  /**
-   * REFUSED_STREAM
-   */
-  NGHTTP2_REFUSED_STREAM = 0x07,
-  /**
-   * CANCEL
-   */
-  NGHTTP2_CANCEL = 0x08,
-  /**
-   * COMPRESSION_ERROR
-   */
-  NGHTTP2_COMPRESSION_ERROR = 0x09,
-  /**
-   * CONNECT_ERROR
-   */
-  NGHTTP2_CONNECT_ERROR = 0x0a,
-  /**
-   * ENHANCE_YOUR_CALM
-   */
-  NGHTTP2_ENHANCE_YOUR_CALM = 0x0b,
-  /**
-   * INADEQUATE_SECURITY
-   */
-  NGHTTP2_INADEQUATE_SECURITY = 0x0c,
-  /**
-   * HTTP_1_1_REQUIRED
-   */
-  NGHTTP2_HTTP_1_1_REQUIRED = 0x0d
-} nghttp2_error_code;
-
-/**
- * @struct
- * The frame header.
- */
-typedef struct {
-  /**
-   * The length field of this frame, excluding frame header.
-   */
-  size_t length;
-  /**
-   * The stream identifier (aka, stream ID)
-   */
-  int32_t stream_id;
-  /**
-   * The type of this frame.  See `nghttp2_frame_type`.
-   */
-  uint8_t type;
-  /**
-   * The flags.
-   */
-  uint8_t flags;
-  /**
-   * Reserved bit in frame header.  Currently, this is always set to 0
-   * and application should not expect something useful in here.
-   */
-  uint8_t reserved;
-} nghttp2_frame_hd;
-
-/**
- * @union
- *
- * This union represents the some kind of data source passed to
- * :type:`nghttp2_data_source_read_callback`.
- */
-typedef union {
-  /**
-   * The integer field, suitable for a file descriptor.
-   */
-  int fd;
-  /**
-   * The pointer to an arbitrary object.
-   */
-  void *ptr;
-} nghttp2_data_source;
-
-/**
- * @enum
- *
- * The flags used to set in |data_flags| output parameter in
- * :type:`nghttp2_data_source_read_callback`.
- */
-typedef enum {
-  /**
-   * No flag set.
-   */
-  NGHTTP2_DATA_FLAG_NONE = 0,
-  /**
-   * Indicates EOF was sensed.
-   */
-  NGHTTP2_DATA_FLAG_EOF = 0x01,
-  /**
-   * Indicates that END_STREAM flag must not be set even if
-   * NGHTTP2_DATA_FLAG_EOF is set.  Usually this flag is used to send
-   * trailer fields with `nghttp2_submit_request()` or
-   * `nghttp2_submit_response()`.
-   */
-  NGHTTP2_DATA_FLAG_NO_END_STREAM = 0x02,
-  /**
-   * Indicates that application will send complete DATA frame in
-   * :type:`nghttp2_send_data_callback`.
-   */
-  NGHTTP2_DATA_FLAG_NO_COPY = 0x04
-} nghttp2_data_flag;
-
-/**
- * @functypedef
- *
- * Callback function invoked when the library wants to read data from
- * the |source|.  The read data is sent in the stream |stream_id|.
- * The implementation of this function must read at most |length|
- * bytes of data from |source| (or possibly other places) and store
- * them in |buf| and return number of data stored in |buf|.  If EOF is
- * reached, set :enum:`NGHTTP2_DATA_FLAG_EOF` flag in |*data_flags|.
- *
- * Sometime it is desirable to avoid copying data into |buf| and let
- * application to send data directly.  To achieve this, set
- * :enum:`NGHTTP2_DATA_FLAG_NO_COPY` to |*data_flags| (and possibly
- * other flags, just like when we do copy), and return the number of
- * bytes to send without copying data into |buf|.  The library, seeing
- * :enum:`NGHTTP2_DATA_FLAG_NO_COPY`, will invoke
- * :type:`nghttp2_send_data_callback`.  The application must send
- * complete DATA frame in that callback.
- *
- * If this callback is set by `nghttp2_submit_request()`,
- * `nghttp2_submit_response()` or `nghttp2_submit_headers()` and
- * `nghttp2_submit_data()` with flag parameter
- * :enum:`NGHTTP2_FLAG_END_STREAM` set, and
- * :enum:`NGHTTP2_DATA_FLAG_EOF` flag is set to |*data_flags|, DATA
- * frame will have END_STREAM flag set.  Usually, this is expected
- * behaviour and all are fine.  One exception is send trailer fields.
- * You cannot send trailer fields after sending frame with END_STREAM
- * set.  To avoid this problem, one can set
- * :enum:`NGHTTP2_DATA_FLAG_NO_END_STREAM` along with
- * :enum:`NGHTTP2_DATA_FLAG_EOF` to signal the library not to set
- * END_STREAM in DATA frame.  Then application can use
- * `nghttp2_submit_trailer()` to send trailer fields.
- * `nghttp2_submit_trailer()` can be called inside this callback.
- *
- * If the application wants to postpone DATA frames (e.g.,
- * asynchronous I/O, or reading data blocks for long time), it is
- * achieved by returning :enum:`NGHTTP2_ERR_DEFERRED` without reading
- * any data in this invocation.  The library removes DATA frame from
- * the outgoing queue temporarily.  To move back deferred DATA frame
- * to outgoing queue, call `nghttp2_session_resume_data()`.
- *
- * By default, |length| is limited to 16KiB at maximum.  If peer
- * allows larger frames, application can enlarge transmission buffer
- * size.  See :type:`nghttp2_data_source_read_length_callback` for
- * more details.
- *
- * If the application just wants to return from
- * `nghttp2_session_send()` or `nghttp2_session_mem_send()` without
- * sending anything, return :enum:`NGHTTP2_ERR_PAUSE`.
- *
- * In case of error, there are 2 choices. Returning
- * :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE` will close the stream
- * by issuing RST_STREAM with :enum:`NGHTTP2_INTERNAL_ERROR`.  If a
- * different error code is desirable, use
- * `nghttp2_submit_rst_stream()` with a desired error code and then
- * return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  Returning
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` will signal the entire session
- * failure.
- */
-typedef ssize_t (*nghttp2_data_source_read_callback)(
-    nghttp2_session *session, int32_t stream_id, uint8_t *buf, size_t length,
-    uint32_t *data_flags, nghttp2_data_source *source, void *user_data);
-
-/**
- * @struct
- *
- * This struct represents the data source and the way to read a chunk
- * of data from it.
- */
-typedef struct {
-  /**
-   * The data source.
-   */
-  nghttp2_data_source source;
-  /**
-   * The callback function to read a chunk of data from the |source|.
-   */
-  nghttp2_data_source_read_callback read_callback;
-} nghttp2_data_provider;
-
-/**
- * @struct
- *
- * The DATA frame.  The received data is delivered via
- * :type:`nghttp2_on_data_chunk_recv_callback`.
- */
-typedef struct {
-  nghttp2_frame_hd hd;
-  /**
-   * The length of the padding in this frame.  This includes PAD_HIGH
-   * and PAD_LOW.
-   */
-  size_t padlen;
-} nghttp2_data;
-
-/**
- * @enum
- *
- * The category of HEADERS, which indicates the role of the frame.  In
- * HTTP/2 spec, request, response, push response and other arbitrary
- * headers (e.g., trailer fields) are all called just HEADERS.  To
- * give the application the role of incoming HEADERS frame, we define
- * several categories.
- */
-typedef enum {
-  /**
-   * The HEADERS frame is opening new stream, which is analogous to
-   * SYN_STREAM in SPDY.
-   */
-  NGHTTP2_HCAT_REQUEST = 0,
-  /**
-   * The HEADERS frame is the first response headers, which is
-   * analogous to SYN_REPLY in SPDY.
-   */
-  NGHTTP2_HCAT_RESPONSE = 1,
-  /**
-   * The HEADERS frame is the first headers sent against reserved
-   * stream.
-   */
-  NGHTTP2_HCAT_PUSH_RESPONSE = 2,
-  /**
-   * The HEADERS frame which does not apply for the above categories,
-   * which is analogous to HEADERS in SPDY.  If non-final response
-   * (e.g., status 1xx) is used, final response HEADERS frame will be
-   * categorized here.
-   */
-  NGHTTP2_HCAT_HEADERS = 3
-} nghttp2_headers_category;
-
-/**
- * @struct
- *
- * The structure to specify stream dependency.
- */
-typedef struct {
-  /**
-   * The stream ID of the stream to depend on.  Specifying 0 makes
-   * stream not depend any other stream.
-   */
-  int32_t stream_id;
-  /**
-   * The weight of this dependency.
-   */
-  int32_t weight;
-  /**
-   * nonzero means exclusive dependency
-   */
-  uint8_t exclusive;
-} nghttp2_priority_spec;
-
-/**
- * @struct
- *
- * The HEADERS frame.  It has the following members:
- */
-typedef struct {
-  /**
-   * The frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The length of the padding in this frame.  This includes PAD_HIGH
-   * and PAD_LOW.
-   */
-  size_t padlen;
-  /**
-   * The priority specification
-   */
-  nghttp2_priority_spec pri_spec;
-  /**
-   * The name/value pairs.
-   */
-  nghttp2_nv *nva;
-  /**
-   * The number of name/value pairs in |nva|.
-   */
-  size_t nvlen;
-  /**
-   * The category of this HEADERS frame.
-   */
-  nghttp2_headers_category cat;
-} nghttp2_headers;
-
-/**
- * @struct
- *
- * The PRIORITY frame.  It has the following members:
- */
-typedef struct {
-  /**
-   * The frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The priority specification.
-   */
-  nghttp2_priority_spec pri_spec;
-} nghttp2_priority;
-
-/**
- * @struct
- *
- * The RST_STREAM frame.  It has the following members:
- */
-typedef struct {
-  /**
-   * The frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The error code.  See :type:`nghttp2_error_code`.
-   */
-  uint32_t error_code;
-} nghttp2_rst_stream;
-
-/**
- * @struct
- *
- * The SETTINGS ID/Value pair.  It has the following members:
- */
-typedef struct {
-  /**
-   * The SETTINGS ID.  See :type:`nghttp2_settings_id`.
-   */
-  int32_t settings_id;
-  /**
-   * The value of this entry.
-   */
-  uint32_t value;
-} nghttp2_settings_entry;
-
-/**
- * @struct
- *
- * The SETTINGS frame.  It has the following members:
- */
-typedef struct {
-  /**
-   * The frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The number of SETTINGS ID/Value pairs in |iv|.
-   */
-  size_t niv;
-  /**
-   * The pointer to the array of SETTINGS ID/Value pair.
-   */
-  nghttp2_settings_entry *iv;
-} nghttp2_settings;
-
-/**
- * @struct
- *
- * The PUSH_PROMISE frame.  It has the following members:
- */
-typedef struct {
-  /**
-   * The frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The length of the padding in this frame.  This includes PAD_HIGH
-   * and PAD_LOW.
-   */
-  size_t padlen;
-  /**
-   * The name/value pairs.
-   */
-  nghttp2_nv *nva;
-  /**
-   * The number of name/value pairs in |nva|.
-   */
-  size_t nvlen;
-  /**
-   * The promised stream ID
-   */
-  int32_t promised_stream_id;
-  /**
-   * Reserved bit.  Currently this is always set to 0 and application
-   * should not expect something useful in here.
-   */
-  uint8_t reserved;
-} nghttp2_push_promise;
-
-/**
- * @struct
- *
- * The PING frame.  It has the following members:
- */
-typedef struct {
-  /**
-   * The frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The opaque data
-   */
-  uint8_t opaque_data[8];
-} nghttp2_ping;
-
-/**
- * @struct
- *
- * The GOAWAY frame.  It has the following members:
- */
-typedef struct {
-  /**
-   * The frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The last stream stream ID.
-   */
-  int32_t last_stream_id;
-  /**
-   * The error code.  See :type:`nghttp2_error_code`.
-   */
-  uint32_t error_code;
-  /**
-   * The additional debug data
-   */
-  uint8_t *opaque_data;
-  /**
-   * The length of |opaque_data| member.
-   */
-  size_t opaque_data_len;
-  /**
-   * Reserved bit.  Currently this is always set to 0 and application
-   * should not expect something useful in here.
-   */
-  uint8_t reserved;
-} nghttp2_goaway;
-
-/**
- * @struct
- *
- * The WINDOW_UPDATE frame.  It has the following members:
- */
-typedef struct {
-  /**
-   * The frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The window size increment.
-   */
-  int32_t window_size_increment;
-  /**
-   * Reserved bit.  Currently this is always set to 0 and application
-   * should not expect something useful in here.
-   */
-  uint8_t reserved;
-} nghttp2_window_update;
-
-/**
- * @struct
- *
- * The extension frame.  It has following members:
- */
-typedef struct {
-  /**
-   * The frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The pointer to extension payload.  The exact pointer type is
-   * determined by hd.type.
-   *
-   * Currently, no extension is supported.  This is a place holder for
-   * the future extensions.
-   */
-  void *payload;
-} nghttp2_extension;
-
-/**
- * @union
- *
- * This union includes all frames to pass them to various function
- * calls as nghttp2_frame type.  The CONTINUATION frame is omitted
- * from here because the library deals with it internally.
- */
-typedef union {
-  /**
-   * The frame header, which is convenient to inspect frame header.
-   */
-  nghttp2_frame_hd hd;
-  /**
-   * The DATA frame.
-   */
-  nghttp2_data data;
-  /**
-   * The HEADERS frame.
-   */
-  nghttp2_headers headers;
-  /**
-   * The PRIORITY frame.
-   */
-  nghttp2_priority priority;
-  /**
-   * The RST_STREAM frame.
-   */
-  nghttp2_rst_stream rst_stream;
-  /**
-   * The SETTINGS frame.
-   */
-  nghttp2_settings settings;
-  /**
-   * The PUSH_PROMISE frame.
-   */
-  nghttp2_push_promise push_promise;
-  /**
-   * The PING frame.
-   */
-  nghttp2_ping ping;
-  /**
-   * The GOAWAY frame.
-   */
-  nghttp2_goaway goaway;
-  /**
-   * The WINDOW_UPDATE frame.
-   */
-  nghttp2_window_update window_update;
-  /**
-   * The extension frame.
-   */
-  nghttp2_extension ext;
-} nghttp2_frame;
-
-/**
- * @functypedef
- *
- * Callback function invoked when |session| wants to send data to the
- * remote peer.  The implementation of this function must send at most
- * |length| bytes of data stored in |data|.  The |flags| is currently
- * not used and always 0. It must return the number of bytes sent if
- * it succeeds.  If it cannot send any single byte without blocking,
- * it must return :enum:`NGHTTP2_ERR_WOULDBLOCK`.  For other errors,
- * it must return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  The
- * |user_data| pointer is the third argument passed in to the call to
- * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
- *
- * This callback is required if the application uses
- * `nghttp2_session_send()` to send data to the remote endpoint.  If
- * the application uses solely `nghttp2_session_mem_send()` instead,
- * this callback function is unnecessary.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_send_callback()`.
- *
- * .. note::
- *
- *   The |length| may be very small.  If that is the case, and
- *   application disables Nagle algorithm (``TCP_NODELAY``), then just
- *   writing |data| to the network stack leads to very small packet,
- *   and it is very inefficient.  An application should be responsible
- *   to buffer up small chunks of data as necessary to avoid this
- *   situation.
- */
-typedef ssize_t (*nghttp2_send_callback)(nghttp2_session *session,
-                                         const uint8_t *data, size_t length,
-                                         int flags, void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when :enum:`NGHTTP2_DATA_FLAG_NO_COPY` is
- * used in :type:`nghttp2_data_source_read_callback` to send complete
- * DATA frame.
- *
- * The |frame| is a DATA frame to send.  The |framehd| is the
- * serialized frame header (9 bytes). The |length| is the length of
- * application data to send (this does not include padding).  The
- * |source| is the same pointer passed to
- * :type:`nghttp2_data_source_read_callback`.
- *
- * The application first must send frame header |framehd| of length 9
- * bytes.  If ``frame->data.padlen > 0``, send 1 byte of value
- * ``frame->data.padlen - 1``.  Then send exactly |length| bytes of
- * application data.  Finally, if ``frame->data.padlen > 1``, send
- * ``frame->data.padlen - 1`` bytes of zero as padding.
- *
- * The application has to send complete DATA frame in this callback.
- * If all data were written successfully, return 0.
- *
- * If it cannot send any data at all, just return
- * :enum:`NGHTTP2_ERR_WOULDBLOCK`; the library will call this callback
- * with the same parameters later (It is recommended to send complete
- * DATA frame at once in this function to deal with error; if partial
- * frame data has already sent, it is impossible to send another data
- * in that state, and all we can do is tear down connection).  When
- * data is fully processed, but application wants to make
- * `nghttp2_session_mem_send()` or `nghttp2_session_send()` return
- * immediately without processing next frames, return
- * :enum:`NGHTTP2_ERR_PAUSE`.  If application decided to reset this
- * stream, return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`, then
- * the library will send RST_STREAM with INTERNAL_ERROR as error code.
- * The application can also return
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`, which will result in
- * connection closure.  Returning any other value is treated as
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` is returned.
- */
-typedef int (*nghttp2_send_data_callback)(nghttp2_session *session,
-                                          nghttp2_frame *frame,
-                                          const uint8_t *framehd, size_t length,
-                                          nghttp2_data_source *source,
-                                          void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when |session| wants to receive data from
- * the remote peer.  The implementation of this function must read at
- * most |length| bytes of data and store it in |buf|.  The |flags| is
- * currently not used and always 0.  It must return the number of
- * bytes written in |buf| if it succeeds.  If it cannot read any
- * single byte without blocking, it must return
- * :enum:`NGHTTP2_ERR_WOULDBLOCK`.  If it gets EOF before it reads any
- * single byte, it must return :enum:`NGHTTP2_ERR_EOF`.  For other
- * errors, it must return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- * Returning 0 is treated as :enum:`NGHTTP2_ERR_WOULDBLOCK`.  The
- * |user_data| pointer is the third argument passed in to the call to
- * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
- *
- * This callback is required if the application uses
- * `nghttp2_session_recv()` to receive data from the remote endpoint.
- * If the application uses solely `nghttp2_session_mem_recv()`
- * instead, this callback function is unnecessary.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_recv_callback()`.
- */
-typedef ssize_t (*nghttp2_recv_callback)(nghttp2_session *session, uint8_t *buf,
-                                         size_t length, int flags,
-                                         void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked by `nghttp2_session_recv()` and
- * `nghttp2_session_mem_recv()` when a frame is received.  The
- * |user_data| pointer is the third argument passed in to the call to
- * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
- *
- * If frame is HEADERS or PUSH_PROMISE, the ``nva`` and ``nvlen``
- * member of their data structure are always ``NULL`` and 0
- * respectively.  The header name/value pairs are emitted via
- * :type:`nghttp2_on_header_callback`.
- *
- * For HEADERS, PUSH_PROMISE and DATA frames, this callback may be
- * called after stream is closed (see
- * :type:`nghttp2_on_stream_close_callback`).  The application should
- * check that stream is still alive using its own stream management or
- * :func:`nghttp2_session_get_stream_user_data()`.
- *
- * Only HEADERS and DATA frame can signal the end of incoming data.
- * If ``frame->hd.flags & NGHTTP2_FLAG_END_STREAM`` is nonzero, the
- * |frame| is the last frame from the remote peer in this stream.
- *
- * This callback won't be called for CONTINUATION frames.
- * HEADERS/PUSH_PROMISE + CONTINUATIONs are treated as single frame.
- *
- * The implementation of this function must return 0 if it succeeds.
- * If nonzero value is returned, it is treated as fatal error and
- * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_on_frame_recv_callback()`.
- */
-typedef int (*nghttp2_on_frame_recv_callback)(nghttp2_session *session,
-                                              const nghttp2_frame *frame,
-                                              void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked by `nghttp2_session_recv()` and
- * `nghttp2_session_mem_recv()` when an invalid non-DATA frame is
- * received.  The error is indicated by the |lib_error_code|, which is
- * one of the values defined in :type:`nghttp2_error`.  When this
- * callback function is invoked, the library automatically submits
- * either RST_STREAM or GOAWAY frame.  The |user_data| pointer is the
- * third argument passed in to the call to
- * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
- *
- * If frame is HEADERS or PUSH_PROMISE, the ``nva`` and ``nvlen``
- * member of their data structure are always ``NULL`` and 0
- * respectively.
- *
- * The implementation of this function must return 0 if it succeeds.
- * If nonzero is returned, it is treated as fatal error and
- * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_on_invalid_frame_recv_callback()`.
- */
-typedef int (*nghttp2_on_invalid_frame_recv_callback)(
-    nghttp2_session *session, const nghttp2_frame *frame, int lib_error_code,
-    void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when a chunk of data in DATA frame is
- * received.  The |stream_id| is the stream ID this DATA frame belongs
- * to.  The |flags| is the flags of DATA frame which this data chunk
- * is contained.  ``(flags & NGHTTP2_FLAG_END_STREAM) != 0`` does not
- * necessarily mean this chunk of data is the last one in the stream.
- * You should use :type:`nghttp2_on_frame_recv_callback` to know all
- * data frames are received.  The |user_data| pointer is the third
- * argument passed in to the call to `nghttp2_session_client_new()` or
- * `nghttp2_session_server_new()`.
- *
- * If the application uses `nghttp2_session_mem_recv()`, it can return
- * :enum:`NGHTTP2_ERR_PAUSE` to make `nghttp2_session_mem_recv()`
- * return without processing further input bytes.  The memory by
- * pointed by the |data| is retained until
- * `nghttp2_session_mem_recv()` or `nghttp2_session_recv()` is called.
- * The application must retain the input bytes which was used to
- * produce the |data| parameter, because it may refer to the memory
- * region included in the input bytes.
- *
- * The implementation of this function must return 0 if it succeeds.
- * If nonzero is returned, it is treated as fatal error, and
- * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_on_data_chunk_recv_callback()`.
- */
-typedef int (*nghttp2_on_data_chunk_recv_callback)(nghttp2_session *session,
-                                                   uint8_t flags,
-                                                   int32_t stream_id,
-                                                   const uint8_t *data,
-                                                   size_t len, void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked just before the non-DATA frame |frame| is
- * sent.  The |user_data| pointer is the third argument passed in to
- * the call to `nghttp2_session_client_new()` or
- * `nghttp2_session_server_new()`.
- *
- * The implementation of this function must return 0 if it succeeds.
- * It can also return :enum:`NGHTTP2_ERR_CANCEL` to cancel the
- * transmission of the given frame.
- *
- * If there is a fatal error while executing this callback, the
- * implementation should return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`,
- * which makes `nghttp2_session_send()` and
- * `nghttp2_session_mem_send()` functions immediately return
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * If the other value is returned, it is treated as if
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` is returned.  But the
- * implementation should not rely on this since the library may define
- * new return value to extend its capability.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_before_frame_send_callback()`.
- */
-typedef int (*nghttp2_before_frame_send_callback)(nghttp2_session *session,
-                                                  const nghttp2_frame *frame,
-                                                  void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked after the frame |frame| is sent.  The
- * |user_data| pointer is the third argument passed in to the call to
- * `nghttp2_session_client_new()` or `nghttp2_session_server_new()`.
- *
- * The implementation of this function must return 0 if it succeeds.
- * If nonzero is returned, it is treated as fatal error and
- * `nghttp2_session_send()` and `nghttp2_session_mem_send()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_on_frame_send_callback()`.
- */
-typedef int (*nghttp2_on_frame_send_callback)(nghttp2_session *session,
-                                              const nghttp2_frame *frame,
-                                              void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked after the non-DATA frame |frame| is not
- * sent because of the error.  The error is indicated by the
- * |lib_error_code|, which is one of the values defined in
- * :type:`nghttp2_error`.  The |user_data| pointer is the third
- * argument passed in to the call to `nghttp2_session_client_new()` or
- * `nghttp2_session_server_new()`.
- *
- * The implementation of this function must return 0 if it succeeds.
- * If nonzero is returned, it is treated as fatal error and
- * `nghttp2_session_send()` and `nghttp2_session_mem_send()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * `nghttp2_session_get_stream_user_data()` can be used to get
- * associated data.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_on_frame_not_send_callback()`.
- */
-typedef int (*nghttp2_on_frame_not_send_callback)(nghttp2_session *session,
-                                                  const nghttp2_frame *frame,
-                                                  int lib_error_code,
-                                                  void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when the stream |stream_id| is closed.
- * The reason of closure is indicated by the |error_code|.  The
- * |error_code| is usually one of :enum:`nghttp2_error_code`, but that
- * is not guaranteed.  The stream_user_data, which was specified in
- * `nghttp2_submit_request()` or `nghttp2_submit_headers()`, is still
- * available in this function.  The |user_data| pointer is the third
- * argument passed in to the call to `nghttp2_session_client_new()` or
- * `nghttp2_session_server_new()`.
- *
- * This function is also called for a stream in reserved state.
- *
- * The implementation of this function must return 0 if it succeeds.
- * If nonzero is returned, it is treated as fatal error and
- * `nghttp2_session_recv()`, `nghttp2_session_mem_recv()`,
- * `nghttp2_session_send()`, and `nghttp2_session_mem_send()`
- * functions immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_on_stream_close_callback()`.
- */
-typedef int (*nghttp2_on_stream_close_callback)(nghttp2_session *session,
-                                                int32_t stream_id,
-                                                uint32_t error_code,
-                                                void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when the reception of header block in
- * HEADERS or PUSH_PROMISE is started.  Each header name/value pair
- * will be emitted by :type:`nghttp2_on_header_callback`.
- *
- * The ``frame->hd.flags`` may not have
- * :enum:`NGHTTP2_FLAG_END_HEADERS` flag set, which indicates that one
- * or more CONTINUATION frames are involved.  But the application does
- * not need to care about that because the header name/value pairs are
- * emitted transparently regardless of CONTINUATION frames.
- *
- * The server applications probably create an object to store
- * information about new stream if ``frame->hd.type ==
- * NGHTTP2_HEADERS`` and ``frame->headers.cat ==
- * NGHTTP2_HCAT_REQUEST``.  If |session| is configured as server side,
- * ``frame->headers.cat`` is either ``NGHTTP2_HCAT_REQUEST``
- * containing request headers or ``NGHTTP2_HCAT_HEADERS`` containing
- * trailer fields and never get PUSH_PROMISE in this callback.
- *
- * For the client applications, ``frame->hd.type`` is either
- * ``NGHTTP2_HEADERS`` or ``NGHTTP2_PUSH_PROMISE``.  In case of
- * ``NGHTTP2_HEADERS``, ``frame->headers.cat ==
- * NGHTTP2_HCAT_RESPONSE`` means that it is the first response
- * headers, but it may be non-final response which is indicated by 1xx
- * status code.  In this case, there may be zero or more HEADERS frame
- * with ``frame->headers.cat == NGHTTP2_HCAT_HEADERS`` which has
- * non-final response code and finally client gets exactly one HEADERS
- * frame with ``frame->headers.cat == NGHTTP2_HCAT_HEADERS``
- * containing final response headers (non-1xx status code).  The
- * trailer fields also has ``frame->headers.cat ==
- * NGHTTP2_HCAT_HEADERS`` which does not contain any status code.
- *
- * Returning :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE` will close
- * the stream (promised stream if frame is PUSH_PROMISE) by issuing
- * RST_STREAM with :enum:`NGHTTP2_INTERNAL_ERROR`.  In this case,
- * :type:`nghttp2_on_header_callback` and
- * :type:`nghttp2_on_frame_recv_callback` will not be invoked.  If a
- * different error code is desirable, use
- * `nghttp2_submit_rst_stream()` with a desired error code and then
- * return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  Again, use
- * ``frame->push_promise.promised_stream_id`` as stream_id parameter
- * in `nghttp2_submit_rst_stream()` if frame is PUSH_PROMISE.
- *
- * The implementation of this function must return 0 if it succeeds.
- * It can return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE` to
- * reset the stream (promised stream if frame is PUSH_PROMISE).  For
- * critical errors, it must return
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the other value is
- * returned, it is treated as if :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`
- * is returned.  If :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` is returned,
- * `nghttp2_session_mem_recv()` function will immediately return
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_on_begin_headers_callback()`.
- */
-typedef int (*nghttp2_on_begin_headers_callback)(nghttp2_session *session,
-                                                 const nghttp2_frame *frame,
-                                                 void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when a header name/value pair is received
- * for the |frame|.  The |name| of length |namelen| is header name.
- * The |value| of length |valuelen| is header value.  The |flags| is
- * bitwise OR of one or more of :type:`nghttp2_nv_flag`.
- *
- * If :enum:`NGHTTP2_NV_FLAG_NO_INDEX` is set in |flags|, the receiver
- * must not index this name/value pair when forwarding it to the next
- * hop.  More specifically, "Literal Header Field never Indexed"
- * representation must be used in HPACK encoding.
- *
- * When this callback is invoked, ``frame->hd.type`` is either
- * :enum:`NGHTTP2_HEADERS` or :enum:`NGHTTP2_PUSH_PROMISE`.  After all
- * header name/value pairs are processed with this callback, and no
- * error has been detected, :type:`nghttp2_on_frame_recv_callback`
- * will be invoked.  If there is an error in decompression,
- * :type:`nghttp2_on_frame_recv_callback` for the |frame| will not be
- * invoked.
- *
- * Both |name| and |value| are guaranteed to be NULL-terminated.  The
- * |namelen| and |valuelen| do not include terminal NULL.  If
- * `nghttp2_option_set_no_http_messaging()` is used with nonzero
- * value, NULL character may be included in |name| or |value| before
- * terminating NULL.
- *
- * Please note that unless `nghttp2_option_set_no_http_messaging()` is
- * used, nghttp2 library does perform validation against the |name|
- * and the |value| using `nghttp2_check_header_name()` and
- * `nghttp2_check_header_value()`.  In addition to this, nghttp2
- * performs validation based on HTTP Messaging rule, which is briefly
- * explained in :ref:`http-messaging` section.
- *
- * If the application uses `nghttp2_session_mem_recv()`, it can return
- * :enum:`NGHTTP2_ERR_PAUSE` to make `nghttp2_session_mem_recv()`
- * return without processing further input bytes.  The memory pointed
- * by |frame|, |name| and |value| parameters are retained until
- * `nghttp2_session_mem_recv()` or `nghttp2_session_recv()` is called.
- * The application must retain the input bytes which was used to
- * produce these parameters, because it may refer to the memory region
- * included in the input bytes.
- *
- * Returning :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE` will close
- * the stream (promised stream if frame is PUSH_PROMISE) by issuing
- * RST_STREAM with :enum:`NGHTTP2_INTERNAL_ERROR`.  In this case,
- * :type:`nghttp2_on_header_callback` and
- * :type:`nghttp2_on_frame_recv_callback` will not be invoked.  If a
- * different error code is desirable, use
- * `nghttp2_submit_rst_stream()` with a desired error code and then
- * return :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  Again, use
- * ``frame->push_promise.promised_stream_id`` as stream_id parameter
- * in `nghttp2_submit_rst_stream()` if frame is PUSH_PROMISE.
- *
- * The implementation of this function must return 0 if it succeeds.
- * It may return :enum:`NGHTTP2_ERR_PAUSE` or
- * :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  For other critical
- * failures, it must return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If
- * the other nonzero value is returned, it is treated as
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` is returned,
- * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_on_header_callback()`.
- *
- * .. warning::
- *
- *   Application should properly limit the total buffer size to store
- *   incoming header fields.  Without it, peer may send large number
- *   of header fields or large header fields to cause out of memory in
- *   local endpoint.  Due to how HPACK works, peer can do this
- *   effectively without using much memory on their own.
- */
-typedef int (*nghttp2_on_header_callback)(nghttp2_session *session,
-                                          const nghttp2_frame *frame,
-                                          const uint8_t *name, size_t namelen,
-                                          const uint8_t *value, size_t valuelen,
-                                          uint8_t flags, void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when a header name/value pair is received
- * for the |frame|.  The |name| is header name.  The |value| is header
- * value.  The |flags| is bitwise OR of one or more of
- * :type:`nghttp2_nv_flag`.
- *
- * This callback behaves like :type:`nghttp2_on_header_callback`,
- * except that |name| and |value| are stored in reference counted
- * buffer.  If application wishes to keep these references without
- * copying them, use `nghttp2_rcbuf_incref()` to increment their
- * reference count.  It is the application's responsibility to call
- * `nghttp2_rcbuf_decref()` if they called `nghttp2_rcbuf_incref()` so
- * as not to leak memory.  If the |session| is created by
- * `nghttp2_session_server_new3()` or `nghttp2_session_client_new3()`,
- * the function to free memory is the one belongs to the mem
- * parameter.  As long as this free function alives, |name| and
- * |value| can live after |session| was destroyed.
- */
-typedef int (*nghttp2_on_header_callback2)(nghttp2_session *session,
-                                           const nghttp2_frame *frame,
-                                           nghttp2_rcbuf *name,
-                                           nghttp2_rcbuf *value, uint8_t flags,
-                                           void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when a invalid header name/value pair is
- * received for the |frame|.
- *
- * The parameter and behaviour are similar to
- * :type:`nghttp2_on_header_callback`.  The difference is that this
- * callback is only invoked when a invalid header name/value pair is
- * received which is treated as stream error if this callback is not
- * set.  Only invalid regular header field are passed to this
- * callback.  In other words, invalid pseudo header field is not
- * passed to this callback.  Also header fields which includes upper
- * cased latter are also treated as error without passing them to this
- * callback.
- *
- * This callback is only considered if HTTP messaging validation is
- * turned on (which is on by default, see
- * `nghttp2_option_set_no_http_messaging()`).
- *
- * With this callback, application inspects the incoming invalid
- * field, and it also can reset stream from this callback by returning
- * :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  By default, the
- * error code is :enum:`NGHTTP2_PROTOCOL_ERROR`.  To change the error
- * code, call `nghttp2_submit_rst_stream()` with the error code of
- * choice in addition to returning
- * :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.
- *
- * If 0 is returned, the header field is ignored, and the stream is
- * not reset.
- */
-typedef int (*nghttp2_on_invalid_header_callback)(
-    nghttp2_session *session, const nghttp2_frame *frame, const uint8_t *name,
-    size_t namelen, const uint8_t *value, size_t valuelen, uint8_t flags,
-    void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when a invalid header name/value pair is
- * received for the |frame|.
- *
- * The parameter and behaviour are similar to
- * :type:`nghttp2_on_header_callback2`.  The difference is that this
- * callback is only invoked when a invalid header name/value pair is
- * received which is silently ignored if this callback is not set.
- * Only invalid regular header field are passed to this callback.  In
- * other words, invalid pseudo header field is not passed to this
- * callback.  Also header fields which includes upper cased latter are
- * also treated as error without passing them to this callback.
- *
- * This callback is only considered if HTTP messaging validation is
- * turned on (which is on by default, see
- * `nghttp2_option_set_no_http_messaging()`).
- *
- * With this callback, application inspects the incoming invalid
- * field, and it also can reset stream from this callback by returning
- * :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.  By default, the
- * error code is :enum:`NGHTTP2_INTERNAL_ERROR`.  To change the error
- * code, call `nghttp2_submit_rst_stream()` with the error code of
- * choice in addition to returning
- * :enum:`NGHTTP2_ERR_TEMPORAL_CALLBACK_FAILURE`.
- */
-typedef int (*nghttp2_on_invalid_header_callback2)(
-    nghttp2_session *session, const nghttp2_frame *frame, nghttp2_rcbuf *name,
-    nghttp2_rcbuf *value, uint8_t flags, void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when the library asks application how
- * many padding bytes are required for the transmission of the
- * |frame|.  The application must choose the total length of payload
- * including padded bytes in range [frame->hd.length, max_payloadlen],
- * inclusive.  Choosing number not in this range will be treated as
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  Returning
- * ``frame->hd.length`` means no padding is added.  Returning
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` will make
- * `nghttp2_session_send()` and `nghttp2_session_mem_send()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_select_padding_callback()`.
- */
-typedef ssize_t (*nghttp2_select_padding_callback)(nghttp2_session *session,
-                                                   const nghttp2_frame *frame,
-                                                   size_t max_payloadlen,
-                                                   void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when library wants to get max length of
- * data to send data to the remote peer.  The implementation of this
- * function should return a value in the following range.  [1,
- * min(|session_remote_window_size|, |stream_remote_window_size|,
- * |remote_max_frame_size|)].  If a value greater than this range is
- * returned than the max allow value will be used.  Returning a value
- * smaller than this range is treated as
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  The |frame_type| is provided
- * for future extensibility and identifies the type of frame (see
- * :type:`nghttp2_frame_type`) for which to get the length for.
- * Currently supported frame types are: :enum:`NGHTTP2_DATA`.
- *
- * This callback can be used to control the length in bytes for which
- * :type:`nghttp2_data_source_read_callback` is allowed to send to the
- * remote endpoint.  This callback is optional.  Returning
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE` will signal the entire session
- * failure.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_data_source_read_length_callback()`.
- */
-typedef ssize_t (*nghttp2_data_source_read_length_callback)(
-    nghttp2_session *session, uint8_t frame_type, int32_t stream_id,
-    int32_t session_remote_window_size, int32_t stream_remote_window_size,
-    uint32_t remote_max_frame_size, void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when a frame header is received.  The
- * |hd| points to received frame header.
- *
- * Unlike :type:`nghttp2_on_frame_recv_callback`, this callback will
- * also be called when frame header of CONTINUATION frame is received.
- *
- * If both :type:`nghttp2_on_begin_frame_callback` and
- * :type:`nghttp2_on_begin_headers_callback` are set and HEADERS or
- * PUSH_PROMISE is received, :type:`nghttp2_on_begin_frame_callback`
- * will be called first.
- *
- * The implementation of this function must return 0 if it succeeds.
- * If nonzero value is returned, it is treated as fatal error and
- * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- *
- * To set this callback to :type:`nghttp2_session_callbacks`, use
- * `nghttp2_session_callbacks_set_on_begin_frame_callback()`.
- */
-typedef int (*nghttp2_on_begin_frame_callback)(nghttp2_session *session,
-                                               const nghttp2_frame_hd *hd,
-                                               void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when chunk of extension frame payload is
- * received.  The |hd| points to frame header.  The received
- * chunk is |data| of length |len|.
- *
- * The implementation of this function must return 0 if it succeeds.
- *
- * To abort processing this extension frame, return
- * :enum:`NGHTTP2_ERR_CANCEL`.
- *
- * If fatal error occurred, application should return
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  In this case,
- * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the
- * other values are returned, currently they are treated as
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- */
-typedef int (*nghttp2_on_extension_chunk_recv_callback)(
-    nghttp2_session *session, const nghttp2_frame_hd *hd, const uint8_t *data,
-    size_t len, void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when library asks the application to
- * unpack extension payload from its wire format.  The extension
- * payload has been passed to the application using
- * :type:`nghttp2_on_extension_chunk_recv_callback`.  The frame header
- * is already unpacked by the library and provided as |hd|.
- *
- * To receive extension frames, the application must tell desired
- * extension frame type to the library using
- * `nghttp2_option_set_user_recv_extension_type()`.
- *
- * The implementation of this function may store the pointer to the
- * created object as a result of unpacking in |*payload|, and returns
- * 0.  The pointer stored in |*payload| is opaque to the library, and
- * the library does not own its pointer.  |*payload| is initialized as
- * ``NULL``.  The |*payload| is available as ``frame->ext.payload`` in
- * :type:`nghttp2_on_frame_recv_callback`.  Therefore if application
- * can free that memory inside :type:`nghttp2_on_frame_recv_callback`
- * callback.  Of course, application has a liberty not ot use
- * |*payload|, and do its own mechanism to process extension frames.
- *
- * To abort processing this extension frame, return
- * :enum:`NGHTTP2_ERR_CANCEL`.
- *
- * If fatal error occurred, application should return
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  In this case,
- * `nghttp2_session_recv()` and `nghttp2_session_mem_recv()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the
- * other values are returned, currently they are treated as
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- */
-typedef int (*nghttp2_unpack_extension_callback)(nghttp2_session *session,
-                                                 void **payload,
-                                                 const nghttp2_frame_hd *hd,
-                                                 void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when library asks the application to pack
- * extension payload in its wire format.  The frame header will be
- * packed by library.  Application must pack payload only.
- * ``frame->ext.payload`` is the object passed to
- * `nghttp2_submit_extension()` as payload parameter.  Application
- * must pack extension payload to the |buf| of its capacity |len|
- * bytes.  The |len| is at least 16KiB.
- *
- * The implementation of this function should return the number of
- * bytes written into |buf| when it succeeds.
- *
- * To abort processing this extension frame, return
- * :enum:`NGHTTP2_ERR_CANCEL`, and
- * :type:`nghttp2_on_frame_not_send_callback` will be invoked.
- *
- * If fatal error occurred, application should return
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  In this case,
- * `nghttp2_session_send()` and `nghttp2_session_mem_send()` functions
- * immediately return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the
- * other values are returned, currently they are treated as
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  If the return value is
- * strictly larger than |len|, it is treated as
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.
- */
-typedef ssize_t (*nghttp2_pack_extension_callback)(nghttp2_session *session,
-                                                   uint8_t *buf, size_t len,
-                                                   const nghttp2_frame *frame,
-                                                   void *user_data);
-
-/**
- * @functypedef
- *
- * Callback function invoked when library provides the error message
- * intended for human consumption.  This callback is solely for
- * debugging purpose.  The |msg| is typically NULL-terminated string
- * of length |len|.  |len| does not include the sentinel NULL
- * character.
- *
- * The format of error message may change between nghttp2 library
- * versions.  The application should not depend on the particular
- * format.
- *
- * Normally, application should return 0 from this callback.  If fatal
- * error occurred while doing something in this callback, application
- * should return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  In this case,
- * library will return immediately with return value
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`.  Currently, if nonzero value
- * is returned from this callback, they are treated as
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`, but application should not
- * rely on this details.
- */
-typedef int (*nghttp2_error_callback)(nghttp2_session *session, const char *msg,
-                                      size_t len, void *user_data);
-
-struct nghttp2_session_callbacks;
-
-/**
- * @struct
- *
- * Callback functions for :type:`nghttp2_session`.  The details of
- * this structure are intentionally hidden from the public API.
- */
-typedef struct nghttp2_session_callbacks nghttp2_session_callbacks;
-
-/**
- * @function
- *
- * Initializes |*callbacks_ptr| with NULL values.
- *
- * The initialized object can be used when initializing multiple
- * :type:`nghttp2_session` objects.
- *
- * When the application finished using this object, it can use
- * `nghttp2_session_callbacks_del()` to free its memory.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_callbacks_new(nghttp2_session_callbacks **callbacks_ptr);
-
-/**
- * @function
- *
- * Frees any resources allocated for |callbacks|.  If |callbacks| is
- * ``NULL``, this function does nothing.
- */
-NGHTTP2_EXTERN void
-nghttp2_session_callbacks_del(nghttp2_session_callbacks *callbacks);
-
-/**
- * @function
- *
- * Sets callback function invoked when a session wants to send data to
- * the remote peer.  This callback is not necessary if the application
- * uses solely `nghttp2_session_mem_send()` to serialize data to
- * transmit.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_send_callback(
-    nghttp2_session_callbacks *cbs, nghttp2_send_callback send_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when the a session wants to receive
- * data from the remote peer.  This callback is not necessary if the
- * application uses solely `nghttp2_session_mem_recv()` to process
- * received data.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_recv_callback(
-    nghttp2_session_callbacks *cbs, nghttp2_recv_callback recv_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked by `nghttp2_session_recv()` and
- * `nghttp2_session_mem_recv()` when a frame is received.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_frame_recv_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_frame_recv_callback on_frame_recv_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked by `nghttp2_session_recv()` and
- * `nghttp2_session_mem_recv()` when an invalid non-DATA frame is
- * received.
- */
-NGHTTP2_EXTERN void
-nghttp2_session_callbacks_set_on_invalid_frame_recv_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_invalid_frame_recv_callback on_invalid_frame_recv_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when a chunk of data in DATA frame
- * is received.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_data_chunk_recv_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_data_chunk_recv_callback on_data_chunk_recv_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked before a non-DATA frame is sent.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_before_frame_send_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_before_frame_send_callback before_frame_send_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked after a frame is sent.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_frame_send_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_frame_send_callback on_frame_send_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when a non-DATA frame is not sent
- * because of an error.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_frame_not_send_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_frame_not_send_callback on_frame_not_send_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when the stream is closed.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_stream_close_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_stream_close_callback on_stream_close_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when the reception of header block
- * in HEADERS or PUSH_PROMISE is started.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_begin_headers_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_begin_headers_callback on_begin_headers_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when a header name/value pair is
- * received.  If both
- * `nghttp2_session_callbacks_set_on_header_callback()` and
- * `nghttp2_session_callbacks_set_on_header_callback2()` are used to
- * set callbacks, the latter has the precedence.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_header_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_header_callback on_header_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when a header name/value pair is
- * received.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_header_callback2(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_header_callback2 on_header_callback2);
-
-/**
- * @function
- *
- * Sets callback function invoked when a invalid header name/value
- * pair is received.  If both
- * `nghttp2_session_callbacks_set_on_invalid_header_callback()` and
- * `nghttp2_session_callbacks_set_on_invalid_header_callback2()` are
- * used to set callbacks, the latter takes the precedence.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_invalid_header_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_invalid_header_callback on_invalid_header_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when a invalid header name/value
- * pair is received.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_invalid_header_callback2(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_invalid_header_callback2 on_invalid_header_callback2);
-
-/**
- * @function
- *
- * Sets callback function invoked when the library asks application
- * how many padding bytes are required for the transmission of the
- * given frame.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_select_padding_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_select_padding_callback select_padding_callback);
-
-/**
- * @function
- *
- * Sets callback function determine the length allowed in
- * :type:`nghttp2_data_source_read_callback`.
- */
-NGHTTP2_EXTERN void
-nghttp2_session_callbacks_set_data_source_read_length_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_data_source_read_length_callback data_source_read_length_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when a frame header is received.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_on_begin_frame_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_begin_frame_callback on_begin_frame_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when
- * :enum:`NGHTTP2_DATA_FLAG_NO_COPY` is used in
- * :type:`nghttp2_data_source_read_callback` to avoid data copy.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_send_data_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_send_data_callback send_data_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when the library asks the
- * application to pack extension frame payload in wire format.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_pack_extension_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_pack_extension_callback pack_extension_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when the library asks the
- * application to unpack extension frame payload from wire format.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_unpack_extension_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_unpack_extension_callback unpack_extension_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when chunk of extension frame
- * payload is received.
- */
-NGHTTP2_EXTERN void
-nghttp2_session_callbacks_set_on_extension_chunk_recv_callback(
-    nghttp2_session_callbacks *cbs,
-    nghttp2_on_extension_chunk_recv_callback on_extension_chunk_recv_callback);
-
-/**
- * @function
- *
- * Sets callback function invoked when library tells error message to
- * the application.
- */
-NGHTTP2_EXTERN void nghttp2_session_callbacks_set_error_callback(
-    nghttp2_session_callbacks *cbs, nghttp2_error_callback error_callback);
-
-/**
- * @functypedef
- *
- * Custom memory allocator to replace malloc().  The |mem_user_data|
- * is the mem_user_data member of :type:`nghttp2_mem` structure.
- */
-typedef void *(*nghttp2_malloc)(size_t size, void *mem_user_data);
-
-/**
- * @functypedef
- *
- * Custom memory allocator to replace free().  The |mem_user_data| is
- * the mem_user_data member of :type:`nghttp2_mem` structure.
- */
-typedef void (*nghttp2_free)(void *ptr, void *mem_user_data);
-
-/**
- * @functypedef
- *
- * Custom memory allocator to replace calloc().  The |mem_user_data|
- * is the mem_user_data member of :type:`nghttp2_mem` structure.
- */
-typedef void *(*nghttp2_calloc)(size_t nmemb, size_t size, void *mem_user_data);
-
-/**
- * @functypedef
- *
- * Custom memory allocator to replace realloc().  The |mem_user_data|
- * is the mem_user_data member of :type:`nghttp2_mem` structure.
- */
-typedef void *(*nghttp2_realloc)(void *ptr, size_t size, void *mem_user_data);
-
-/**
- * @struct
- *
- * Custom memory allocator functions and user defined pointer.  The
- * |mem_user_data| member is passed to each allocator function.  This
- * can be used, for example, to achieve per-session memory pool.
- *
- * In the following example code, ``my_malloc``, ``my_free``,
- * ``my_calloc`` and ``my_realloc`` are the replacement of the
- * standard allocators ``malloc``, ``free``, ``calloc`` and
- * ``realloc`` respectively::
- *
- *     void *my_malloc_cb(size_t size, void *mem_user_data) {
- *       return my_malloc(size);
- *     }
- *
- *     void my_free_cb(void *ptr, void *mem_user_data) { my_free(ptr); }
- *
- *     void *my_calloc_cb(size_t nmemb, size_t size, void *mem_user_data) {
- *       return my_calloc(nmemb, size);
- *     }
- *
- *     void *my_realloc_cb(void *ptr, size_t size, void *mem_user_data) {
- *       return my_realloc(ptr, size);
- *     }
- *
- *     void session_new() {
- *       nghttp2_session *session;
- *       nghttp2_session_callbacks *callbacks;
- *       nghttp2_mem mem = {NULL, my_malloc_cb, my_free_cb, my_calloc_cb,
- *                          my_realloc_cb};
- *
- *       ...
- *
- *       nghttp2_session_client_new3(&session, callbacks, NULL, NULL, &mem);
- *
- *       ...
- *     }
- */
-typedef struct {
-  /**
-   * An arbitrary user supplied data.  This is passed to each
-   * allocator function.
-   */
-  void *mem_user_data;
-  /**
-   * Custom allocator function to replace malloc().
-   */
-  nghttp2_malloc malloc;
-  /**
-   * Custom allocator function to replace free().
-   */
-  nghttp2_free free;
-  /**
-   * Custom allocator function to replace calloc().
-   */
-  nghttp2_calloc calloc;
-  /**
-   * Custom allocator function to replace realloc().
-   */
-  nghttp2_realloc realloc;
-} nghttp2_mem;
-
-struct nghttp2_option;
-
-/**
- * @struct
- *
- * Configuration options for :type:`nghttp2_session`.  The details of
- * this structure are intentionally hidden from the public API.
- */
-typedef struct nghttp2_option nghttp2_option;
-
-/**
- * @function
- *
- * Initializes |*option_ptr| with default values.
- *
- * When the application finished using this object, it can use
- * `nghttp2_option_del()` to free its memory.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int nghttp2_option_new(nghttp2_option **option_ptr);
-
-/**
- * @function
- *
- * Frees any resources allocated for |option|.  If |option| is
- * ``NULL``, this function does nothing.
- */
-NGHTTP2_EXTERN void nghttp2_option_del(nghttp2_option *option);
-
-/**
- * @function
- *
- * This option prevents the library from sending WINDOW_UPDATE for a
- * connection automatically.  If this option is set to nonzero, the
- * library won't send WINDOW_UPDATE for DATA until application calls
- * `nghttp2_session_consume()` to indicate the consumed amount of
- * data.  Don't use `nghttp2_submit_window_update()` for this purpose.
- * By default, this option is set to zero.
- */
-NGHTTP2_EXTERN void
-nghttp2_option_set_no_auto_window_update(nghttp2_option *option, int val);
-
-/**
- * @function
- *
- * This option sets the SETTINGS_MAX_CONCURRENT_STREAMS value of
- * remote endpoint as if it is received in SETTINGS frame.  Without
- * specifying this option, before the local endpoint receives
- * SETTINGS_MAX_CONCURRENT_STREAMS in SETTINGS frame from remote
- * endpoint, SETTINGS_MAX_CONCURRENT_STREAMS is unlimited.  This may
- * cause problem if local endpoint submits lots of requests initially
- * and sending them at once to the remote peer may lead to the
- * rejection of some requests.  Specifying this option to the sensible
- * value, say 100, may avoid this kind of issue. This value will be
- * overwritten if the local endpoint receives
- * SETTINGS_MAX_CONCURRENT_STREAMS from the remote endpoint.
- */
-NGHTTP2_EXTERN void
-nghttp2_option_set_peer_max_concurrent_streams(nghttp2_option *option,
-                                               uint32_t val);
-
-/**
- * @function
- *
- * By default, nghttp2 library, if configured as server, requires
- * first 24 bytes of client magic byte string (MAGIC).  In most cases,
- * this will simplify the implementation of server.  But sometimes
- * server may want to detect the application protocol based on first
- * few bytes on clear text communication.
- *
- * If this option is used with nonzero |val|, nghttp2 library does not
- * handle MAGIC.  It still checks following SETTINGS frame.  This
- * means that applications should deal with MAGIC by themselves.
- *
- * If this option is not used or used with zero value, if MAGIC does
- * not match :macro:`NGHTTP2_CLIENT_MAGIC`, `nghttp2_session_recv()`
- * and `nghttp2_session_mem_recv()` will return error
- * :enum:`NGHTTP2_ERR_BAD_CLIENT_MAGIC`, which is fatal error.
- */
-NGHTTP2_EXTERN void
-nghttp2_option_set_no_recv_client_magic(nghttp2_option *option, int val);
-
-/**
- * @function
- *
- * By default, nghttp2 library enforces subset of HTTP Messaging rules
- * described in `HTTP/2 specification, section 8
- * <https://tools.ietf.org/html/rfc7540#section-8>`_.  See
- * :ref:`http-messaging` section for details.  For those applications
- * who use nghttp2 library as non-HTTP use, give nonzero to |val| to
- * disable this enforcement.  Please note that disabling this feature
- * does not change the fundamental client and server model of HTTP.
- * That is, even if the validation is disabled, only client can send
- * requests.
- */
-NGHTTP2_EXTERN void nghttp2_option_set_no_http_messaging(nghttp2_option *option,
-                                                         int val);
-
-/**
- * @function
- *
- * RFC 7540 does not enforce any limit on the number of incoming
- * reserved streams (in RFC 7540 terms, streams in reserved (remote)
- * state).  This only affects client side, since only server can push
- * streams.  Malicious server can push arbitrary number of streams,
- * and make client's memory exhausted.  This option can set the
- * maximum number of such incoming streams to avoid possible memory
- * exhaustion.  If this option is set, and pushed streams are
- * automatically closed on reception, without calling user provided
- * callback, if they exceed the given limit.  The default value is
- * 200.  If session is configured as server side, this option has no
- * effect.  Server can control the number of streams to push.
- */
-NGHTTP2_EXTERN void
-nghttp2_option_set_max_reserved_remote_streams(nghttp2_option *option,
-                                               uint32_t val);
-
-/**
- * @function
- *
- * Sets extension frame type the application is willing to handle with
- * user defined callbacks (see
- * :type:`nghttp2_on_extension_chunk_recv_callback` and
- * :type:`nghttp2_unpack_extension_callback`).  The |type| is
- * extension frame type, and must be strictly greater than 0x9.
- * Otherwise, this function does nothing.  The application can call
- * this function multiple times to set more than one frame type to
- * receive.  The application does not have to call this function if it
- * just sends extension frames.
- */
-NGHTTP2_EXTERN void
-nghttp2_option_set_user_recv_extension_type(nghttp2_option *option,
-                                            uint8_t type);
-
-/**
- * @function
- *
- * Sets extension frame type the application is willing to receive
- * using builtin handler.  The |type| is the extension frame type to
- * receive, and must be strictly greater than 0x9.  Otherwise, this
- * function does nothing.  The application can call this function
- * multiple times to set more than one frame type to receive.  The
- * application does not have to call this function if it just sends
- * extension frames.
- *
- * If same frame type is passed to both
- * `nghttp2_option_set_builtin_recv_extension_type()` and
- * `nghttp2_option_set_user_recv_extension_type()`, the latter takes
- * precedence.
- */
-NGHTTP2_EXTERN void
-nghttp2_option_set_builtin_recv_extension_type(nghttp2_option *option,
-                                               uint8_t type);
-
-/**
- * @function
- *
- * This option prevents the library from sending PING frame with ACK
- * flag set automatically when PING frame without ACK flag set is
- * received.  If this option is set to nonzero, the library won't send
- * PING frame with ACK flag set in the response for incoming PING
- * frame.  The application can send PING frame with ACK flag set using
- * `nghttp2_submit_ping()` with :enum:`NGHTTP2_FLAG_ACK` as flags
- * parameter.
- */
-NGHTTP2_EXTERN void nghttp2_option_set_no_auto_ping_ack(nghttp2_option *option,
-                                                        int val);
-
-/**
- * @function
- *
- * This option sets the maximum length of header block (a set of
- * header fields per one HEADERS frame) to send.  The length of a
- * given set of header fields is calculated using
- * `nghttp2_hd_deflate_bound()`.  The default value is 64KiB.  If
- * application attempts to send header fields larger than this limit,
- * the transmission of the frame fails with error code
- * :enum:`NGHTTP2_ERR_FRAME_SIZE_ERROR`.
- */
-NGHTTP2_EXTERN void
-nghttp2_option_set_max_send_header_block_length(nghttp2_option *option,
-                                                size_t val);
-
-/**
- * @function
- *
- * This option sets the maximum dynamic table size for deflating
- * header fields.  The default value is 4KiB.  In HTTP/2, receiver of
- * deflated header block can specify maximum dynamic table size.  The
- * actual maximum size is the minimum of the size receiver specified
- * and this option value.
- */
-NGHTTP2_EXTERN void
-nghttp2_option_set_max_deflate_dynamic_table_size(nghttp2_option *option,
-                                                  size_t val);
-
-/**
- * @function
- *
- * This option prevents the library from retaining closed streams to
- * maintain the priority tree.  If this option is set to nonzero,
- * applications can discard closed stream completely to save memory.
- */
-NGHTTP2_EXTERN void nghttp2_option_set_no_closed_streams(nghttp2_option *option,
-                                                         int val);
-
-/**
- * @function
- *
- * Initializes |*session_ptr| for client use.  The all members of
- * |callbacks| are copied to |*session_ptr|.  Therefore |*session_ptr|
- * does not store |callbacks|.  The |user_data| is an arbitrary user
- * supplied data, which will be passed to the callback functions.
- *
- * The :type:`nghttp2_send_callback` must be specified.  If the
- * application code uses `nghttp2_session_recv()`, the
- * :type:`nghttp2_recv_callback` must be specified.  The other members
- * of |callbacks| can be ``NULL``.
- *
- * If this function fails, |*session_ptr| is left untouched.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_client_new(nghttp2_session **session_ptr,
-                           const nghttp2_session_callbacks *callbacks,
-                           void *user_data);
-
-/**
- * @function
- *
- * Initializes |*session_ptr| for server use.  The all members of
- * |callbacks| are copied to |*session_ptr|. Therefore |*session_ptr|
- * does not store |callbacks|.  The |user_data| is an arbitrary user
- * supplied data, which will be passed to the callback functions.
- *
- * The :type:`nghttp2_send_callback` must be specified.  If the
- * application code uses `nghttp2_session_recv()`, the
- * :type:`nghttp2_recv_callback` must be specified.  The other members
- * of |callbacks| can be ``NULL``.
- *
- * If this function fails, |*session_ptr| is left untouched.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_server_new(nghttp2_session **session_ptr,
-                           const nghttp2_session_callbacks *callbacks,
-                           void *user_data);
-
-/**
- * @function
- *
- * Like `nghttp2_session_client_new()`, but with additional options
- * specified in the |option|.
- *
- * The |option| can be ``NULL`` and the call is equivalent to
- * `nghttp2_session_client_new()`.
- *
- * This function does not take ownership |option|.  The application is
- * responsible for freeing |option| if it finishes using the object.
- *
- * The library code does not refer to |option| after this function
- * returns.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_client_new2(nghttp2_session **session_ptr,
-                            const nghttp2_session_callbacks *callbacks,
-                            void *user_data, const nghttp2_option *option);
-
-/**
- * @function
- *
- * Like `nghttp2_session_server_new()`, but with additional options
- * specified in the |option|.
- *
- * The |option| can be ``NULL`` and the call is equivalent to
- * `nghttp2_session_server_new()`.
- *
- * This function does not take ownership |option|.  The application is
- * responsible for freeing |option| if it finishes using the object.
- *
- * The library code does not refer to |option| after this function
- * returns.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_server_new2(nghttp2_session **session_ptr,
-                            const nghttp2_session_callbacks *callbacks,
-                            void *user_data, const nghttp2_option *option);
-
-/**
- * @function
- *
- * Like `nghttp2_session_client_new2()`, but with additional custom
- * memory allocator specified in the |mem|.
- *
- * The |mem| can be ``NULL`` and the call is equivalent to
- * `nghttp2_session_client_new2()`.
- *
- * This function does not take ownership |mem|.  The application is
- * responsible for freeing |mem|.
- *
- * The library code does not refer to |mem| pointer after this
- * function returns, so the application can safely free it.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int nghttp2_session_client_new3(
-    nghttp2_session **session_ptr, const nghttp2_session_callbacks *callbacks,
-    void *user_data, const nghttp2_option *option, nghttp2_mem *mem);
-
-/**
- * @function
- *
- * Like `nghttp2_session_server_new2()`, but with additional custom
- * memory allocator specified in the |mem|.
- *
- * The |mem| can be ``NULL`` and the call is equivalent to
- * `nghttp2_session_server_new2()`.
- *
- * This function does not take ownership |mem|.  The application is
- * responsible for freeing |mem|.
- *
- * The library code does not refer to |mem| pointer after this
- * function returns, so the application can safely free it.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int nghttp2_session_server_new3(
-    nghttp2_session **session_ptr, const nghttp2_session_callbacks *callbacks,
-    void *user_data, const nghttp2_option *option, nghttp2_mem *mem);
-
-/**
- * @function
- *
- * Frees any resources allocated for |session|.  If |session| is
- * ``NULL``, this function does nothing.
- */
-NGHTTP2_EXTERN void nghttp2_session_del(nghttp2_session *session);
-
-/**
- * @function
- *
- * Sends pending frames to the remote peer.
- *
- * This function retrieves the highest prioritized frame from the
- * outbound queue and sends it to the remote peer.  It does this as
- * many as possible until the user callback
- * :type:`nghttp2_send_callback` returns
- * :enum:`NGHTTP2_ERR_WOULDBLOCK` or the outbound queue becomes empty.
- * This function calls several callback functions which are passed
- * when initializing the |session|.  Here is the simple time chart
- * which tells when each callback is invoked:
- *
- * 1. Get the next frame to send from outbound queue.
- *
- * 2. Prepare transmission of the frame.
- *
- * 3. If the control frame cannot be sent because some preconditions
- *    are not met (e.g., request HEADERS cannot be sent after GOAWAY),
- *    :type:`nghttp2_on_frame_not_send_callback` is invoked.  Abort
- *    the following steps.
- *
- * 4. If the frame is HEADERS, PUSH_PROMISE or DATA,
- *    :type:`nghttp2_select_padding_callback` is invoked.
- *
- * 5. If the frame is request HEADERS, the stream is opened here.
- *
- * 6. :type:`nghttp2_before_frame_send_callback` is invoked.
- *
- * 7. If :enum:`NGHTTP2_ERR_CANCEL` is returned from
- *    :type:`nghttp2_before_frame_send_callback`, the current frame
- *    transmission is canceled, and
- *    :type:`nghttp2_on_frame_not_send_callback` is invoked.  Abort
- *    the following steps.
- *
- * 8. :type:`nghttp2_send_callback` is invoked one or more times to
- *    send the frame.
- *
- * 9. :type:`nghttp2_on_frame_send_callback` is invoked.
- *
- * 10. If the transmission of the frame triggers closure of the
- *     stream, the stream is closed and
- *     :type:`nghttp2_on_stream_close_callback` is invoked.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`
- *     The callback function failed.
- */
-NGHTTP2_EXTERN int nghttp2_session_send(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns the serialized data to send.
- *
- * This function behaves like `nghttp2_session_send()` except that it
- * does not use :type:`nghttp2_send_callback` to transmit data.
- * Instead, it assigns the pointer to the serialized data to the
- * |*data_ptr| and returns its length.  The other callbacks are called
- * in the same way as they are in `nghttp2_session_send()`.
- *
- * If no data is available to send, this function returns 0.
- *
- * This function may not return all serialized data in one invocation.
- * To get all data, call this function repeatedly until it returns 0
- * or one of negative error codes.
- *
- * The assigned |*data_ptr| is valid until the next call of
- * `nghttp2_session_mem_send()` or `nghttp2_session_send()`.
- *
- * The caller must send all data before sending the next chunk of
- * data.
- *
- * This function returns the length of the data pointed by the
- * |*data_ptr| if it succeeds, or one of the following negative error
- * codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- *
- * .. note::
- *
- *   This function may produce very small byte string.  If that is the
- *   case, and application disables Nagle algorithm (``TCP_NODELAY``),
- *   then writing this small chunk leads to very small packet, and it
- *   is very inefficient.  An application should be responsible to
- *   buffer up small chunks of data as necessary to avoid this
- *   situation.
- */
-NGHTTP2_EXTERN ssize_t nghttp2_session_mem_send(nghttp2_session *session,
-                                                const uint8_t **data_ptr);
-
-/**
- * @function
- *
- * Receives frames from the remote peer.
- *
- * This function receives as many frames as possible until the user
- * callback :type:`nghttp2_recv_callback` returns
- * :enum:`NGHTTP2_ERR_WOULDBLOCK`.  This function calls several
- * callback functions which are passed when initializing the
- * |session|.  Here is the simple time chart which tells when each
- * callback is invoked:
- *
- * 1. :type:`nghttp2_recv_callback` is invoked one or more times to
- *    receive frame header.
- *
- * 2. When frame header is received,
- *    :type:`nghttp2_on_begin_frame_callback` is invoked.
- *
- * 3. If the frame is DATA frame:
- *
- *    1. :type:`nghttp2_recv_callback` is invoked to receive DATA
- *       payload. For each chunk of data,
- *       :type:`nghttp2_on_data_chunk_recv_callback` is invoked.
- *
- *    2. If one DATA frame is completely received,
- *       :type:`nghttp2_on_frame_recv_callback` is invoked.  If the
- *       reception of the frame triggers the closure of the stream,
- *       :type:`nghttp2_on_stream_close_callback` is invoked.
- *
- * 4. If the frame is the control frame:
- *
- *    1. :type:`nghttp2_recv_callback` is invoked one or more times to
- *       receive whole frame.
- *
- *    2. If the received frame is valid, then following actions are
- *       taken.  If the frame is either HEADERS or PUSH_PROMISE,
- *       :type:`nghttp2_on_begin_headers_callback` is invoked.  Then
- *       :type:`nghttp2_on_header_callback` is invoked for each header
- *       name/value pair.  For invalid header field,
- *       :type:`nghttp2_on_invalid_header_callback` is called.  After
- *       all name/value pairs are emitted successfully,
- *       :type:`nghttp2_on_frame_recv_callback` is invoked.  For other
- *       frames, :type:`nghttp2_on_frame_recv_callback` is invoked.
- *       If the reception of the frame triggers the closure of the
- *       stream, :type:`nghttp2_on_stream_close_callback` is invoked.
- *
- *    3. If the received frame is unpacked but is interpreted as
- *       invalid, :type:`nghttp2_on_invalid_frame_recv_callback` is
- *       invoked.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_EOF`
- *     The remote peer did shutdown on the connection.
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`
- *     The callback function failed.
- * :enum:`NGHTTP2_ERR_BAD_CLIENT_MAGIC`
- *     Invalid client magic was detected.  This error only returns
- *     when |session| was configured as server and
- *     `nghttp2_option_set_no_recv_client_magic()` is not used with
- *     nonzero value.
- * :enum:`NGHTTP2_ERR_FLOODED`
- *     Flooding was detected in this HTTP/2 session, and it must be
- *     closed.  This is most likely caused by misbehaviour of peer.
- */
-NGHTTP2_EXTERN int nghttp2_session_recv(nghttp2_session *session);
-
-/**
- * @function
- *
- * Processes data |in| as an input from the remote endpoint.  The
- * |inlen| indicates the number of bytes in the |in|.
- *
- * This function behaves like `nghttp2_session_recv()` except that it
- * does not use :type:`nghttp2_recv_callback` to receive data; the
- * |in| is the only data for the invocation of this function.  If all
- * bytes are processed, this function returns.  The other callbacks
- * are called in the same way as they are in `nghttp2_session_recv()`.
- *
- * In the current implementation, this function always tries to
- * processes all input data unless either an error occurs or
- * :enum:`NGHTTP2_ERR_PAUSE` is returned from
- * :type:`nghttp2_on_header_callback` or
- * :type:`nghttp2_on_data_chunk_recv_callback`.  If
- * :enum:`NGHTTP2_ERR_PAUSE` is used, the return value includes the
- * number of bytes which was used to produce the data or frame for the
- * callback.
- *
- * This function returns the number of processed bytes, or one of the
- * following negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`
- *     The callback function failed.
- * :enum:`NGHTTP2_ERR_BAD_CLIENT_MAGIC`
- *     Invalid client magic was detected.  This error only returns
- *     when |session| was configured as server and
- *     `nghttp2_option_set_no_recv_client_magic()` is not used with
- *     nonzero value.
- * :enum:`NGHTTP2_ERR_FLOODED`
- *     Flooding was detected in this HTTP/2 session, and it must be
- *     closed.  This is most likely caused by misbehaviour of peer.
- */
-NGHTTP2_EXTERN ssize_t nghttp2_session_mem_recv(nghttp2_session *session,
-                                                const uint8_t *in,
-                                                size_t inlen);
-
-/**
- * @function
- *
- * Puts back previously deferred DATA frame in the stream |stream_id|
- * to the outbound queue.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The stream does not exist; or no deferred data exist.
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int nghttp2_session_resume_data(nghttp2_session *session,
-                                               int32_t stream_id);
-
-/**
- * @function
- *
- * Returns nonzero value if |session| wants to receive data from the
- * remote peer.
- *
- * If both `nghttp2_session_want_read()` and
- * `nghttp2_session_want_write()` return 0, the application should
- * drop the connection.
- */
-NGHTTP2_EXTERN int nghttp2_session_want_read(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns nonzero value if |session| wants to send data to the remote
- * peer.
- *
- * If both `nghttp2_session_want_read()` and
- * `nghttp2_session_want_write()` return 0, the application should
- * drop the connection.
- */
-NGHTTP2_EXTERN int nghttp2_session_want_write(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns stream_user_data for the stream |stream_id|.  The
- * stream_user_data is provided by `nghttp2_submit_request()`,
- * `nghttp2_submit_headers()` or
- * `nghttp2_session_set_stream_user_data()`.  Unless it is set using
- * `nghttp2_session_set_stream_user_data()`, if the stream is
- * initiated by the remote endpoint, stream_user_data is always
- * ``NULL``.  If the stream does not exist, this function returns
- * ``NULL``.
- */
-NGHTTP2_EXTERN void *
-nghttp2_session_get_stream_user_data(nghttp2_session *session,
-                                     int32_t stream_id);
-
-/**
- * @function
- *
- * Sets the |stream_user_data| to the stream denoted by the
- * |stream_id|.  If a stream user data is already set to the stream,
- * it is replaced with the |stream_user_data|.  It is valid to specify
- * ``NULL`` in the |stream_user_data|, which nullifies the associated
- * data pointer.
- *
- * It is valid to set the |stream_user_data| to the stream reserved by
- * PUSH_PROMISE frame.
- *
- * This function returns 0 if it succeeds, or one of following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The stream does not exist
- */
-NGHTTP2_EXTERN int
-nghttp2_session_set_stream_user_data(nghttp2_session *session,
-                                     int32_t stream_id, void *stream_user_data);
-
-/**
- * @function
- *
- * Returns the number of frames in the outbound queue.  This does not
- * include the deferred DATA frames.
- */
-NGHTTP2_EXTERN size_t
-nghttp2_session_get_outbound_queue_size(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns the number of DATA payload in bytes received without
- * WINDOW_UPDATE transmission for the stream |stream_id|.  The local
- * (receive) window size can be adjusted by
- * `nghttp2_submit_window_update()`.  This function takes into account
- * that and returns effective data length.  In particular, if the
- * local window size is reduced by submitting negative
- * window_size_increment with `nghttp2_submit_window_update()`, this
- * function returns the number of bytes less than actually received.
- *
- * This function returns -1 if it fails.
- */
-NGHTTP2_EXTERN int32_t nghttp2_session_get_stream_effective_recv_data_length(
-    nghttp2_session *session, int32_t stream_id);
-
-/**
- * @function
- *
- * Returns the local (receive) window size for the stream |stream_id|.
- * The local window size can be adjusted by
- * `nghttp2_submit_window_update()`.  This function takes into account
- * that and returns effective window size.
- *
- * This function does not take into account the amount of received
- * data from the remote endpoint.  Use
- * `nghttp2_session_get_stream_local_window_size()` to know the amount
- * of data the remote endpoint can send without receiving stream level
- * WINDOW_UPDATE frame.  Note that each stream is still subject to the
- * connection level flow control.
- *
- * This function returns -1 if it fails.
- */
-NGHTTP2_EXTERN int32_t nghttp2_session_get_stream_effective_local_window_size(
-    nghttp2_session *session, int32_t stream_id);
-
-/**
- * @function
- *
- * Returns the amount of flow-controlled payload (e.g., DATA) that the
- * remote endpoint can send without receiving stream level
- * WINDOW_UPDATE frame.  It is also subject to the connection level
- * flow control.  So the actual amount of data to send is
- * min(`nghttp2_session_get_stream_local_window_size()`,
- * `nghttp2_session_get_local_window_size()`).
- *
- * This function returns -1 if it fails.
- */
-NGHTTP2_EXTERN int32_t nghttp2_session_get_stream_local_window_size(
-    nghttp2_session *session, int32_t stream_id);
-
-/**
- * @function
- *
- * Returns the number of DATA payload in bytes received without
- * WINDOW_UPDATE transmission for a connection.  The local (receive)
- * window size can be adjusted by `nghttp2_submit_window_update()`.
- * This function takes into account that and returns effective data
- * length.  In particular, if the local window size is reduced by
- * submitting negative window_size_increment with
- * `nghttp2_submit_window_update()`, this function returns the number
- * of bytes less than actually received.
- *
- * This function returns -1 if it fails.
- */
-NGHTTP2_EXTERN int32_t
-nghttp2_session_get_effective_recv_data_length(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns the local (receive) window size for a connection.  The
- * local window size can be adjusted by
- * `nghttp2_submit_window_update()`.  This function takes into account
- * that and returns effective window size.
- *
- * This function does not take into account the amount of received
- * data from the remote endpoint.  Use
- * `nghttp2_session_get_local_window_size()` to know the amount of
- * data the remote endpoint can send without receiving
- * connection-level WINDOW_UPDATE frame.  Note that each stream is
- * still subject to the stream level flow control.
- *
- * This function returns -1 if it fails.
- */
-NGHTTP2_EXTERN int32_t
-nghttp2_session_get_effective_local_window_size(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns the amount of flow-controlled payload (e.g., DATA) that the
- * remote endpoint can send without receiving connection level
- * WINDOW_UPDATE frame.  Note that each stream is still subject to the
- * stream level flow control (see
- * `nghttp2_session_get_stream_local_window_size()`).
- *
- * This function returns -1 if it fails.
- */
-NGHTTP2_EXTERN int32_t
-nghttp2_session_get_local_window_size(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns the remote window size for a given stream |stream_id|.
- *
- * This is the amount of flow-controlled payload (e.g., DATA) that the
- * local endpoint can send without stream level WINDOW_UPDATE.  There
- * is also connection level flow control, so the effective size of
- * payload that the local endpoint can actually send is
- * min(`nghttp2_session_get_stream_remote_window_size()`,
- * `nghttp2_session_get_remote_window_size()`).
- *
- * This function returns -1 if it fails.
- */
-NGHTTP2_EXTERN int32_t nghttp2_session_get_stream_remote_window_size(
-    nghttp2_session *session, int32_t stream_id);
-
-/**
- * @function
- *
- * Returns the remote window size for a connection.
- *
- * This function always succeeds.
- */
-NGHTTP2_EXTERN int32_t
-nghttp2_session_get_remote_window_size(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns 1 if local peer half closed the given stream |stream_id|.
- * Returns 0 if it did not.  Returns -1 if no such stream exists.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_get_stream_local_close(nghttp2_session *session,
-                                       int32_t stream_id);
-
-/**
- * @function
- *
- * Returns 1 if remote peer half closed the given stream |stream_id|.
- * Returns 0 if it did not.  Returns -1 if no such stream exists.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_get_stream_remote_close(nghttp2_session *session,
-                                        int32_t stream_id);
-
-/**
- * @function
- *
- * Returns the current dynamic table size of HPACK inflater, including
- * the overhead 32 bytes per entry described in RFC 7541.
- */
-NGHTTP2_EXTERN size_t
-nghttp2_session_get_hd_inflate_dynamic_table_size(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns the current dynamic table size of HPACK deflater including
- * the overhead 32 bytes per entry described in RFC 7541.
- */
-NGHTTP2_EXTERN size_t
-nghttp2_session_get_hd_deflate_dynamic_table_size(nghttp2_session *session);
-
-/**
- * @function
- *
- * Signals the session so that the connection should be terminated.
- *
- * The last stream ID is the minimum value between the stream ID of a
- * stream for which :type:`nghttp2_on_frame_recv_callback` was called
- * most recently and the last stream ID we have sent to the peer
- * previously.
- *
- * The |error_code| is the error code of this GOAWAY frame.  The
- * pre-defined error code is one of :enum:`nghttp2_error_code`.
- *
- * After the transmission, both `nghttp2_session_want_read()` and
- * `nghttp2_session_want_write()` return 0.
- *
- * This function should be called when the connection should be
- * terminated after sending GOAWAY.  If the remaining streams should
- * be processed after GOAWAY, use `nghttp2_submit_goaway()` instead.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int nghttp2_session_terminate_session(nghttp2_session *session,
-                                                     uint32_t error_code);
-
-/**
- * @function
- *
- * Signals the session so that the connection should be terminated.
- *
- * This function behaves like `nghttp2_session_terminate_session()`,
- * but the last stream ID can be specified by the application for fine
- * grained control of stream.  The HTTP/2 specification does not allow
- * last_stream_id to be increased.  So the actual value sent as
- * last_stream_id is the minimum value between the given
- * |last_stream_id| and the last_stream_id we have previously sent to
- * the peer.
- *
- * The |last_stream_id| is peer's stream ID or 0.  So if |session| is
- * initialized as client, |last_stream_id| must be even or 0.  If
- * |session| is initialized as server, |last_stream_id| must be odd or
- * 0.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |last_stream_id| is invalid.
- */
-NGHTTP2_EXTERN int nghttp2_session_terminate_session2(nghttp2_session *session,
-                                                      int32_t last_stream_id,
-                                                      uint32_t error_code);
-
-/**
- * @function
- *
- * Signals to the client that the server started graceful shutdown
- * procedure.
- *
- * This function is only usable for server.  If this function is
- * called with client side session, this function returns
- * :enum:`NGHTTP2_ERR_INVALID_STATE`.
- *
- * To gracefully shutdown HTTP/2 session, server should call this
- * function to send GOAWAY with last_stream_id (1u << 31) - 1.  And
- * after some delay (e.g., 1 RTT), send another GOAWAY with the stream
- * ID that the server has some processing using
- * `nghttp2_submit_goaway()`.  See also
- * `nghttp2_session_get_last_proc_stream_id()`.
- *
- * Unlike `nghttp2_submit_goaway()`, this function just sends GOAWAY
- * and does nothing more.  This is a mere indication to the client
- * that session shutdown is imminent.  The application should call
- * `nghttp2_submit_goaway()` with appropriate last_stream_id after
- * this call.
- *
- * If one or more GOAWAY frame have been already sent by either
- * `nghttp2_submit_goaway()` or `nghttp2_session_terminate_session()`,
- * this function has no effect.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_STATE`
- *     The |session| is initialized as client.
- */
-NGHTTP2_EXTERN int nghttp2_submit_shutdown_notice(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns the value of SETTINGS |id| notified by a remote endpoint.
- * The |id| must be one of values defined in
- * :enum:`nghttp2_settings_id`.
- */
-NGHTTP2_EXTERN uint32_t nghttp2_session_get_remote_settings(
-    nghttp2_session *session, nghttp2_settings_id id);
-
-/**
- * @function
- *
- * Returns the value of SETTINGS |id| of local endpoint acknowledged
- * by the remote endpoint.  The |id| must be one of the values defined
- * in :enum:`nghttp2_settings_id`.
- */
-NGHTTP2_EXTERN uint32_t nghttp2_session_get_local_settings(
-    nghttp2_session *session, nghttp2_settings_id id);
-
-/**
- * @function
- *
- * Tells the |session| that next stream ID is |next_stream_id|.  The
- * |next_stream_id| must be equal or greater than the value returned
- * by `nghttp2_session_get_next_stream_id()`.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |next_stream_id| is strictly less than the value
- *     `nghttp2_session_get_next_stream_id()` returns; or
- *     |next_stream_id| is invalid (e.g., even integer for client, or
- *     odd integer for server).
- */
-NGHTTP2_EXTERN int nghttp2_session_set_next_stream_id(nghttp2_session *session,
-                                                      int32_t next_stream_id);
-
-/**
- * @function
- *
- * Returns the next outgoing stream ID.  Notice that return type is
- * uint32_t.  If we run out of stream ID for this session, this
- * function returns 1 << 31.
- */
-NGHTTP2_EXTERN uint32_t
-nghttp2_session_get_next_stream_id(nghttp2_session *session);
-
-/**
- * @function
- *
- * Tells the |session| that |size| bytes for a stream denoted by
- * |stream_id| were consumed by application and are ready to
- * WINDOW_UPDATE.  The consumed bytes are counted towards both
- * connection and stream level WINDOW_UPDATE (see
- * `nghttp2_session_consume_connection()` and
- * `nghttp2_session_consume_stream()` to update consumption
- * independently).  This function is intended to be used without
- * automatic window update (see
- * `nghttp2_option_set_no_auto_window_update()`).
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is 0.
- * :enum:`NGHTTP2_ERR_INVALID_STATE`
- *     Automatic WINDOW_UPDATE is not disabled.
- */
-NGHTTP2_EXTERN int nghttp2_session_consume(nghttp2_session *session,
-                                           int32_t stream_id, size_t size);
-
-/**
- * @function
- *
- * Like `nghttp2_session_consume()`, but this only tells library that
- * |size| bytes were consumed only for connection level.  Note that
- * HTTP/2 maintains connection and stream level flow control windows
- * independently.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_STATE`
- *     Automatic WINDOW_UPDATE is not disabled.
- */
-NGHTTP2_EXTERN int nghttp2_session_consume_connection(nghttp2_session *session,
-                                                      size_t size);
-
-/**
- * @function
- *
- * Like `nghttp2_session_consume()`, but this only tells library that
- * |size| bytes were consumed only for stream denoted by |stream_id|.
- * Note that HTTP/2 maintains connection and stream level flow control
- * windows independently.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is 0.
- * :enum:`NGHTTP2_ERR_INVALID_STATE`
- *     Automatic WINDOW_UPDATE is not disabled.
- */
-NGHTTP2_EXTERN int nghttp2_session_consume_stream(nghttp2_session *session,
-                                                  int32_t stream_id,
-                                                  size_t size);
-
-/**
- * @function
- *
- * Changes priority of existing stream denoted by |stream_id|.  The
- * new priority specification is |pri_spec|.
- *
- * The priority is changed silently and instantly, and no PRIORITY
- * frame will be sent to notify the peer of this change.  This
- * function may be useful for server to change the priority of pushed
- * stream.
- *
- * If |session| is initialized as server, and ``pri_spec->stream_id``
- * points to the idle stream, the idle stream is created if it does
- * not exist.  The created idle stream will depend on root stream
- * (stream 0) with weight 16.
- *
- * Otherwise, if stream denoted by ``pri_spec->stream_id`` is not
- * found, we use default priority instead of given |pri_spec|.  That
- * is make stream depend on root stream with weight 16.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     Attempted to depend on itself; or no stream exist for the given
- *     |stream_id|; or |stream_id| is 0
- */
-NGHTTP2_EXTERN int
-nghttp2_session_change_stream_priority(nghttp2_session *session,
-                                       int32_t stream_id,
-                                       const nghttp2_priority_spec *pri_spec);
-
-/**
- * @function
- *
- * Creates idle stream with the given |stream_id|, and priority
- * |pri_spec|.
- *
- * The stream creation is done without sending PRIORITY frame, which
- * means that peer does not know about the existence of this idle
- * stream in the local endpoint.
- *
- * RFC 7540 does not disallow the use of creation of idle stream with
- * odd or even stream ID regardless of client or server.  So this
- * function can create odd or even stream ID regardless of client or
- * server.  But probably it is a bit safer to use the stream ID the
- * local endpoint can initiate (in other words, use odd stream ID for
- * client, and even stream ID for server), to avoid potential
- * collision from peer's instruction.  Also we can use
- * `nghttp2_session_set_next_stream_id()` to avoid to open created
- * idle streams accidentally if we follow this recommendation.
- *
- * If |session| is initialized as server, and ``pri_spec->stream_id``
- * points to the idle stream, the idle stream is created if it does
- * not exist.  The created idle stream will depend on root stream
- * (stream 0) with weight 16.
- *
- * Otherwise, if stream denoted by ``pri_spec->stream_id`` is not
- * found, we use default priority instead of given |pri_spec|.  That
- * is make stream depend on root stream with weight 16.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     Attempted to depend on itself; or stream denoted by |stream_id|
- *     already exists; or |stream_id| cannot be used to create idle
- *     stream (in other words, local endpoint has already opened
- *     stream ID greater than or equal to the given stream ID; or
- *     |stream_id| is 0
- */
-NGHTTP2_EXTERN int
-nghttp2_session_create_idle_stream(nghttp2_session *session, int32_t stream_id,
-                                   const nghttp2_priority_spec *pri_spec);
-
-/**
- * @function
- *
- * Performs post-process of HTTP Upgrade request.  This function can
- * be called from both client and server, but the behavior is very
- * different in each other.
- *
- * .. warning::
- *
- *   This function is deprecated in favor of
- *   `nghttp2_session_upgrade2()`, because this function lacks the
- *   parameter to tell the library the request method used in the
- *   original HTTP request.  This information is required for client
- *   to validate actual response body length against content-length
- *   header field (see `nghttp2_option_set_no_http_messaging()`).  If
- *   HEAD is used in request, the length of response body must be 0
- *   regardless of value included in content-length header field.
- *
- * If called from client side, the |settings_payload| must be the
- * value sent in ``HTTP2-Settings`` header field and must be decoded
- * by base64url decoder.  The |settings_payloadlen| is the length of
- * |settings_payload|.  The |settings_payload| is unpacked and its
- * setting values will be submitted using `nghttp2_submit_settings()`.
- * This means that the client application code does not need to submit
- * SETTINGS by itself.  The stream with stream ID=1 is opened and the
- * |stream_user_data| is used for its stream_user_data.  The opened
- * stream becomes half-closed (local) state.
- *
- * If called from server side, the |settings_payload| must be the
- * value received in ``HTTP2-Settings`` header field and must be
- * decoded by base64url decoder.  The |settings_payloadlen| is the
- * length of |settings_payload|.  It is treated as if the SETTINGS
- * frame with that payload is received.  Thus, callback functions for
- * the reception of SETTINGS frame will be invoked.  The stream with
- * stream ID=1 is opened.  The |stream_user_data| is ignored.  The
- * opened stream becomes half-closed (remote).
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |settings_payload| is badly formed.
- * :enum:`NGHTTP2_ERR_PROTO`
- *     The stream ID 1 is already used or closed; or is not available.
- */
-NGHTTP2_EXTERN int nghttp2_session_upgrade(nghttp2_session *session,
-                                           const uint8_t *settings_payload,
-                                           size_t settings_payloadlen,
-                                           void *stream_user_data);
-
-/**
- * @function
- *
- * Performs post-process of HTTP Upgrade request.  This function can
- * be called from both client and server, but the behavior is very
- * different in each other.
- *
- * If called from client side, the |settings_payload| must be the
- * value sent in ``HTTP2-Settings`` header field and must be decoded
- * by base64url decoder.  The |settings_payloadlen| is the length of
- * |settings_payload|.  The |settings_payload| is unpacked and its
- * setting values will be submitted using `nghttp2_submit_settings()`.
- * This means that the client application code does not need to submit
- * SETTINGS by itself.  The stream with stream ID=1 is opened and the
- * |stream_user_data| is used for its stream_user_data.  The opened
- * stream becomes half-closed (local) state.
- *
- * If called from server side, the |settings_payload| must be the
- * value received in ``HTTP2-Settings`` header field and must be
- * decoded by base64url decoder.  The |settings_payloadlen| is the
- * length of |settings_payload|.  It is treated as if the SETTINGS
- * frame with that payload is received.  Thus, callback functions for
- * the reception of SETTINGS frame will be invoked.  The stream with
- * stream ID=1 is opened.  The |stream_user_data| is ignored.  The
- * opened stream becomes half-closed (remote).
- *
- * If the request method is HEAD, pass nonzero value to
- * |head_request|.  Otherwise, pass 0.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |settings_payload| is badly formed.
- * :enum:`NGHTTP2_ERR_PROTO`
- *     The stream ID 1 is already used or closed; or is not available.
- */
-NGHTTP2_EXTERN int nghttp2_session_upgrade2(nghttp2_session *session,
-                                            const uint8_t *settings_payload,
-                                            size_t settings_payloadlen,
-                                            int head_request,
-                                            void *stream_user_data);
-
-/**
- * @function
- *
- * Serializes the SETTINGS values |iv| in the |buf|.  The size of the
- * |buf| is specified by |buflen|.  The number of entries in the |iv|
- * array is given by |niv|.  The required space in |buf| for the |niv|
- * entries is ``6*niv`` bytes and if the given buffer is too small, an
- * error is returned.  This function is used mainly for creating a
- * SETTINGS payload to be sent with the ``HTTP2-Settings`` header
- * field in an HTTP Upgrade request.  The data written in |buf| is NOT
- * base64url encoded and the application is responsible for encoding.
- *
- * This function returns the number of bytes written in |buf|, or one
- * of the following negative error codes:
- *
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |iv| contains duplicate settings ID or invalid value.
- *
- * :enum:`NGHTTP2_ERR_INSUFF_BUFSIZE`
- *     The provided |buflen| size is too small to hold the output.
- */
-NGHTTP2_EXTERN ssize_t nghttp2_pack_settings_payload(
-    uint8_t *buf, size_t buflen, const nghttp2_settings_entry *iv, size_t niv);
-
-/**
- * @function
- *
- * Returns string describing the |lib_error_code|.  The
- * |lib_error_code| must be one of the :enum:`nghttp2_error`.
- */
-NGHTTP2_EXTERN const char *nghttp2_strerror(int lib_error_code);
-
-/**
- * @function
- *
- * Returns string representation of HTTP/2 error code |error_code|
- * (e.g., ``PROTOCOL_ERROR`` is returned if ``error_code ==
- * NGHTTP2_PROTOCOL_ERROR``).  If string representation is unknown for
- * given |error_code|, this function returns string ``unknown``.
- */
-NGHTTP2_EXTERN const char *nghttp2_http2_strerror(uint32_t error_code);
-
-/**
- * @function
- *
- * Initializes |pri_spec| with the |stream_id| of the stream to depend
- * on with |weight| and its exclusive flag.  If |exclusive| is
- * nonzero, exclusive flag is set.
- *
- * The |weight| must be in [:enum:`NGHTTP2_MIN_WEIGHT`,
- * :enum:`NGHTTP2_MAX_WEIGHT`], inclusive.
- */
-NGHTTP2_EXTERN void nghttp2_priority_spec_init(nghttp2_priority_spec *pri_spec,
-                                               int32_t stream_id,
-                                               int32_t weight, int exclusive);
-
-/**
- * @function
- *
- * Initializes |pri_spec| with the default values.  The default values
- * are: stream_id = 0, weight = :macro:`NGHTTP2_DEFAULT_WEIGHT` and
- * exclusive = 0.
- */
-NGHTTP2_EXTERN void
-nghttp2_priority_spec_default_init(nghttp2_priority_spec *pri_spec);
-
-/**
- * @function
- *
- * Returns nonzero if the |pri_spec| is filled with default values.
- */
-NGHTTP2_EXTERN int
-nghttp2_priority_spec_check_default(const nghttp2_priority_spec *pri_spec);
-
-/**
- * @function
- *
- * Submits HEADERS frame and optionally one or more DATA frames.
- *
- * The |pri_spec| is priority specification of this request.  ``NULL``
- * means the default priority (see
- * `nghttp2_priority_spec_default_init()`).  To specify the priority,
- * use `nghttp2_priority_spec_init()`.  If |pri_spec| is not ``NULL``,
- * this function will copy its data members.
- *
- * The ``pri_spec->weight`` must be in [:enum:`NGHTTP2_MIN_WEIGHT`,
- * :enum:`NGHTTP2_MAX_WEIGHT`], inclusive.  If ``pri_spec->weight`` is
- * strictly less than :enum:`NGHTTP2_MIN_WEIGHT`, it becomes
- * :enum:`NGHTTP2_MIN_WEIGHT`.  If it is strictly greater than
- * :enum:`NGHTTP2_MAX_WEIGHT`, it becomes :enum:`NGHTTP2_MAX_WEIGHT`.
- *
- * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
- * |nvlen| elements.  The application is responsible to include
- * required pseudo-header fields (header field whose name starts with
- * ":") in |nva| and must place pseudo-headers before regular header
- * fields.
- *
- * This function creates copies of all name/value pairs in |nva|.  It
- * also lower-cases all names in |nva|.  The order of elements in
- * |nva| is preserved.  For header fields with
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
- * and value are not copied respectively.  With
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
- * pass header field name in lowercase.  The application should
- * maintain the references to them until
- * :type:`nghttp2_on_frame_send_callback` or
- * :type:`nghttp2_on_frame_not_send_callback` is called.
- *
- * HTTP/2 specification has requirement about header fields in the
- * request HEADERS.  See the specification for more details.
- *
- * If |data_prd| is not ``NULL``, it provides data which will be sent
- * in subsequent DATA frames.  In this case, a method that allows
- * request message bodies
- * (https://tools.ietf.org/html/rfc7231#section-4) must be specified
- * with ``:method`` key in |nva| (e.g. ``POST``).  This function does
- * not take ownership of the |data_prd|.  The function copies the
- * members of the |data_prd|.  If |data_prd| is ``NULL``, HEADERS have
- * END_STREAM set.  The |stream_user_data| is data associated to the
- * stream opened by this request and can be an arbitrary pointer,
- * which can be retrieved later by
- * `nghttp2_session_get_stream_user_data()`.
- *
- * This function returns assigned stream ID if it succeeds, or one of
- * the following negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_STREAM_ID_NOT_AVAILABLE`
- *     No stream ID is available because maximum stream ID was
- *     reached.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     Trying to depend on itself (new stream ID equals
- *     ``pri_spec->stream_id``).
- * :enum:`NGHTTP2_ERR_PROTO`
- *     The |session| is server session.
- *
- * .. warning::
- *
- *   This function returns assigned stream ID if it succeeds.  But
- *   that stream is not opened yet.  The application must not submit
- *   frame to that stream ID before
- *   :type:`nghttp2_before_frame_send_callback` is called for this
- *   frame.
- *
- */
-NGHTTP2_EXTERN int32_t nghttp2_submit_request(
-    nghttp2_session *session, const nghttp2_priority_spec *pri_spec,
-    const nghttp2_nv *nva, size_t nvlen, const nghttp2_data_provider *data_prd,
-    void *stream_user_data);
-
-/**
- * @function
- *
- * Submits response HEADERS frame and optionally one or more DATA
- * frames against the stream |stream_id|.
- *
- * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
- * |nvlen| elements.  The application is responsible to include
- * required pseudo-header fields (header field whose name starts with
- * ":") in |nva| and must place pseudo-headers before regular header
- * fields.
- *
- * This function creates copies of all name/value pairs in |nva|.  It
- * also lower-cases all names in |nva|.  The order of elements in
- * |nva| is preserved.  For header fields with
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
- * and value are not copied respectively.  With
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
- * pass header field name in lowercase.  The application should
- * maintain the references to them until
- * :type:`nghttp2_on_frame_send_callback` or
- * :type:`nghttp2_on_frame_not_send_callback` is called.
- *
- * HTTP/2 specification has requirement about header fields in the
- * response HEADERS.  See the specification for more details.
- *
- * If |data_prd| is not ``NULL``, it provides data which will be sent
- * in subsequent DATA frames.  This function does not take ownership
- * of the |data_prd|.  The function copies the members of the
- * |data_prd|.  If |data_prd| is ``NULL``, HEADERS will have
- * END_STREAM flag set.
- *
- * This method can be used as normal HTTP response and push response.
- * When pushing a resource using this function, the |session| must be
- * configured using `nghttp2_session_server_new()` or its variants and
- * the target stream denoted by the |stream_id| must be reserved using
- * `nghttp2_submit_push_promise()`.
- *
- * To send non-final response headers (e.g., HTTP status 101), don't
- * use this function because this function half-closes the outbound
- * stream.  Instead, use `nghttp2_submit_headers()` for this purpose.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is 0.
- * :enum:`NGHTTP2_ERR_DATA_EXIST`
- *     DATA or HEADERS has been already submitted and not fully
- *     processed yet.  Normally, this does not happen, but when
- *     application wrongly calls `nghttp2_submit_response()` twice,
- *     this may happen.
- * :enum:`NGHTTP2_ERR_PROTO`
- *     The |session| is client session.
- *
- * .. warning::
- *
- *   Calling this function twice for the same stream ID may lead to
- *   program crash.  It is generally considered to a programming error
- *   to commit response twice.
- */
-NGHTTP2_EXTERN int
-nghttp2_submit_response(nghttp2_session *session, int32_t stream_id,
-                        const nghttp2_nv *nva, size_t nvlen,
-                        const nghttp2_data_provider *data_prd);
-
-/**
- * @function
- *
- * Submits trailer fields HEADERS against the stream |stream_id|.
- *
- * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
- * |nvlen| elements.  The application must not include pseudo-header
- * fields (headers whose names starts with ":") in |nva|.
- *
- * This function creates copies of all name/value pairs in |nva|.  It
- * also lower-cases all names in |nva|.  The order of elements in
- * |nva| is preserved.  For header fields with
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
- * and value are not copied respectively.  With
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
- * pass header field name in lowercase.  The application should
- * maintain the references to them until
- * :type:`nghttp2_on_frame_send_callback` or
- * :type:`nghttp2_on_frame_not_send_callback` is called.
- *
- * For server, trailer fields must follow response HEADERS or response
- * DATA without END_STREAM flat set.  The library does not enforce
- * this requirement, and applications should do this for themselves.
- * If `nghttp2_submit_trailer()` is called before any response HEADERS
- * submission (usually by `nghttp2_submit_response()`), the content of
- * |nva| will be sent as response headers, which will result in error.
- *
- * This function has the same effect with `nghttp2_submit_headers()`,
- * with flags = :enum:`NGHTTP2_FLAG_END_STREAM` and both pri_spec and
- * stream_user_data to NULL.
- *
- * To submit trailer fields after `nghttp2_submit_response()` is
- * called, the application has to specify
- * :type:`nghttp2_data_provider` to `nghttp2_submit_response()`.
- * Inside of :type:`nghttp2_data_source_read_callback`, when setting
- * :enum:`NGHTTP2_DATA_FLAG_EOF`, also set
- * :enum:`NGHTTP2_DATA_FLAG_NO_END_STREAM`.  After that, the
- * application can send trailer fields using
- * `nghttp2_submit_trailer()`.  `nghttp2_submit_trailer()` can be used
- * inside :type:`nghttp2_data_source_read_callback`.
- *
- * This function returns 0 if it succeeds and |stream_id| is -1.
- * Otherwise, this function returns 0 if it succeeds, or one of the
- * following negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is 0.
- */
-NGHTTP2_EXTERN int nghttp2_submit_trailer(nghttp2_session *session,
-                                          int32_t stream_id,
-                                          const nghttp2_nv *nva, size_t nvlen);
-
-/**
- * @function
- *
- * Submits HEADERS frame. The |flags| is bitwise OR of the
- * following values:
- *
- * * :enum:`NGHTTP2_FLAG_END_STREAM`
- *
- * If |flags| includes :enum:`NGHTTP2_FLAG_END_STREAM`, this frame has
- * END_STREAM flag set.
- *
- * The library handles the CONTINUATION frame internally and it
- * correctly sets END_HEADERS to the last sequence of the PUSH_PROMISE
- * or CONTINUATION frame.
- *
- * If the |stream_id| is -1, this frame is assumed as request (i.e.,
- * request HEADERS frame which opens new stream).  In this case, the
- * assigned stream ID will be returned.  Otherwise, specify stream ID
- * in |stream_id|.
- *
- * The |pri_spec| is priority specification of this request.  ``NULL``
- * means the default priority (see
- * `nghttp2_priority_spec_default_init()`).  To specify the priority,
- * use `nghttp2_priority_spec_init()`.  If |pri_spec| is not ``NULL``,
- * this function will copy its data members.
- *
- * The ``pri_spec->weight`` must be in [:enum:`NGHTTP2_MIN_WEIGHT`,
- * :enum:`NGHTTP2_MAX_WEIGHT`], inclusive.  If ``pri_spec->weight`` is
- * strictly less than :enum:`NGHTTP2_MIN_WEIGHT`, it becomes
- * :enum:`NGHTTP2_MIN_WEIGHT`.  If it is strictly greater than
- * :enum:`NGHTTP2_MAX_WEIGHT`, it becomes :enum:`NGHTTP2_MAX_WEIGHT`.
- *
- * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
- * |nvlen| elements.  The application is responsible to include
- * required pseudo-header fields (header field whose name starts with
- * ":") in |nva| and must place pseudo-headers before regular header
- * fields.
- *
- * This function creates copies of all name/value pairs in |nva|.  It
- * also lower-cases all names in |nva|.  The order of elements in
- * |nva| is preserved.  For header fields with
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
- * and value are not copied respectively.  With
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
- * pass header field name in lowercase.  The application should
- * maintain the references to them until
- * :type:`nghttp2_on_frame_send_callback` or
- * :type:`nghttp2_on_frame_not_send_callback` is called.
- *
- * The |stream_user_data| is a pointer to an arbitrary data which is
- * associated to the stream this frame will open.  Therefore it is
- * only used if this frame opens streams, in other words, it changes
- * stream state from idle or reserved to open.
- *
- * This function is low-level in a sense that the application code can
- * specify flags directly.  For usual HTTP request,
- * `nghttp2_submit_request()` is useful.  Likewise, for HTTP response,
- * prefer `nghttp2_submit_response()`.
- *
- * This function returns newly assigned stream ID if it succeeds and
- * |stream_id| is -1.  Otherwise, this function returns 0 if it
- * succeeds, or one of the following negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_STREAM_ID_NOT_AVAILABLE`
- *     No stream ID is available because maximum stream ID was
- *     reached.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is 0; or trying to depend on itself (stream ID
- *     equals ``pri_spec->stream_id``).
- * :enum:`NGHTTP2_ERR_DATA_EXIST`
- *     DATA or HEADERS has been already submitted and not fully
- *     processed yet.  This happens if stream denoted by |stream_id|
- *     is in reserved state.
- * :enum:`NGHTTP2_ERR_PROTO`
- *     The |stream_id| is -1, and |session| is server session.
- *
- * .. warning::
- *
- *   This function returns assigned stream ID if it succeeds and
- *   |stream_id| is -1.  But that stream is not opened yet.  The
- *   application must not submit frame to that stream ID before
- *   :type:`nghttp2_before_frame_send_callback` is called for this
- *   frame.
- *
- */
-NGHTTP2_EXTERN int32_t nghttp2_submit_headers(
-    nghttp2_session *session, uint8_t flags, int32_t stream_id,
-    const nghttp2_priority_spec *pri_spec, const nghttp2_nv *nva, size_t nvlen,
-    void *stream_user_data);
-
-/**
- * @function
- *
- * Submits one or more DATA frames to the stream |stream_id|.  The
- * data to be sent are provided by |data_prd|.  If |flags| contains
- * :enum:`NGHTTP2_FLAG_END_STREAM`, the last DATA frame has END_STREAM
- * flag set.
- *
- * This function does not take ownership of the |data_prd|.  The
- * function copies the members of the |data_prd|.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_DATA_EXIST`
- *     DATA or HEADERS has been already submitted and not fully
- *     processed yet.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is 0.
- * :enum:`NGHTTP2_ERR_STREAM_CLOSED`
- *     The stream was already closed; or the |stream_id| is invalid.
- *
- * .. note::
- *
- *   Currently, only one DATA or HEADERS is allowed for a stream at a
- *   time.  Submitting these frames more than once before first DATA
- *   or HEADERS is finished results in :enum:`NGHTTP2_ERR_DATA_EXIST`
- *   error code.  The earliest callback which tells that previous
- *   frame is done is :type:`nghttp2_on_frame_send_callback`.  In side
- *   that callback, new data can be submitted using
- *   `nghttp2_submit_data()`.  Of course, all data except for last one
- *   must not have :enum:`NGHTTP2_FLAG_END_STREAM` flag set in
- *   |flags|.  This sounds a bit complicated, and we recommend to use
- *   `nghttp2_submit_request()` and `nghttp2_submit_response()` to
- *   avoid this cascading issue.  The experience shows that for HTTP
- *   use, these two functions are enough to implement both client and
- *   server.
- */
-NGHTTP2_EXTERN int nghttp2_submit_data(nghttp2_session *session, uint8_t flags,
-                                       int32_t stream_id,
-                                       const nghttp2_data_provider *data_prd);
-
-/**
- * @function
- *
- * Submits PRIORITY frame to change the priority of stream |stream_id|
- * to the priority specification |pri_spec|.
- *
- * The |flags| is currently ignored and should be
- * :enum:`NGHTTP2_FLAG_NONE`.
- *
- * The |pri_spec| is priority specification of this request.  ``NULL``
- * is not allowed for this function. To specify the priority, use
- * `nghttp2_priority_spec_init()`.  This function will copy its data
- * members.
- *
- * The ``pri_spec->weight`` must be in [:enum:`NGHTTP2_MIN_WEIGHT`,
- * :enum:`NGHTTP2_MAX_WEIGHT`], inclusive.  If ``pri_spec->weight`` is
- * strictly less than :enum:`NGHTTP2_MIN_WEIGHT`, it becomes
- * :enum:`NGHTTP2_MIN_WEIGHT`.  If it is strictly greater than
- * :enum:`NGHTTP2_MAX_WEIGHT`, it becomes :enum:`NGHTTP2_MAX_WEIGHT`.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is 0; or the |pri_spec| is NULL; or trying to
- *     depend on itself.
- */
-NGHTTP2_EXTERN int
-nghttp2_submit_priority(nghttp2_session *session, uint8_t flags,
-                        int32_t stream_id,
-                        const nghttp2_priority_spec *pri_spec);
-
-/**
- * @function
- *
- * Submits RST_STREAM frame to cancel/reject the stream |stream_id|
- * with the error code |error_code|.
- *
- * The pre-defined error code is one of :enum:`nghttp2_error_code`.
- *
- * The |flags| is currently ignored and should be
- * :enum:`NGHTTP2_FLAG_NONE`.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is 0.
- */
-NGHTTP2_EXTERN int nghttp2_submit_rst_stream(nghttp2_session *session,
-                                             uint8_t flags, int32_t stream_id,
-                                             uint32_t error_code);
-
-/**
- * @function
- *
- * Stores local settings and submits SETTINGS frame.  The |iv| is the
- * pointer to the array of :type:`nghttp2_settings_entry`.  The |niv|
- * indicates the number of :type:`nghttp2_settings_entry`.
- *
- * The |flags| is currently ignored and should be
- * :enum:`NGHTTP2_FLAG_NONE`.
- *
- * This function does not take ownership of the |iv|.  This function
- * copies all the elements in the |iv|.
- *
- * While updating individual stream's local window size, if the window
- * size becomes strictly larger than NGHTTP2_MAX_WINDOW_SIZE,
- * RST_STREAM is issued against such a stream.
- *
- * SETTINGS with :enum:`NGHTTP2_FLAG_ACK` is automatically submitted
- * by the library and application could not send it at its will.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |iv| contains invalid value (e.g., initial window size
- *     strictly greater than (1 << 31) - 1.
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int nghttp2_submit_settings(nghttp2_session *session,
-                                           uint8_t flags,
-                                           const nghttp2_settings_entry *iv,
-                                           size_t niv);
-
-/**
- * @function
- *
- * Submits PUSH_PROMISE frame.
- *
- * The |flags| is currently ignored.  The library handles the
- * CONTINUATION frame internally and it correctly sets END_HEADERS to
- * the last sequence of the PUSH_PROMISE or CONTINUATION frame.
- *
- * The |stream_id| must be client initiated stream ID.
- *
- * The |nva| is an array of name/value pair :type:`nghttp2_nv` with
- * |nvlen| elements.  The application is responsible to include
- * required pseudo-header fields (header field whose name starts with
- * ":") in |nva| and must place pseudo-headers before regular header
- * fields.
- *
- * This function creates copies of all name/value pairs in |nva|.  It
- * also lower-cases all names in |nva|.  The order of elements in
- * |nva| is preserved.  For header fields with
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME` and
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_VALUE` are set, header field name
- * and value are not copied respectively.  With
- * :enum:`NGHTTP2_NV_FLAG_NO_COPY_NAME`, application is responsible to
- * pass header field name in lowercase.  The application should
- * maintain the references to them until
- * :type:`nghttp2_on_frame_send_callback` or
- * :type:`nghttp2_on_frame_not_send_callback` is called.
- *
- * The |promised_stream_user_data| is a pointer to an arbitrary data
- * which is associated to the promised stream this frame will open and
- * make it in reserved state.  It is available using
- * `nghttp2_session_get_stream_user_data()`.  The application can
- * access it in :type:`nghttp2_before_frame_send_callback` and
- * :type:`nghttp2_on_frame_send_callback` of this frame.
- *
- * The client side is not allowed to use this function.
- *
- * To submit response headers and data, use
- * `nghttp2_submit_response()`.
- *
- * This function returns assigned promised stream ID if it succeeds,
- * or one of the following negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_PROTO`
- *     This function was invoked when |session| is initialized as
- *     client.
- * :enum:`NGHTTP2_ERR_STREAM_ID_NOT_AVAILABLE`
- *     No stream ID is available because maximum stream ID was
- *     reached.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is 0; The |stream_id| does not designate stream
- *     that peer initiated.
- * :enum:`NGHTTP2_ERR_STREAM_CLOSED`
- *     The stream was already closed; or the |stream_id| is invalid.
- *
- * .. warning::
- *
- *   This function returns assigned promised stream ID if it succeeds.
- *   As of 1.16.0, stream object for pushed resource is created when
- *   this function succeeds.  In that case, the application can submit
- *   push response for the promised frame.
- *
- *   In 1.15.0 or prior versions, pushed stream is not opened yet when
- *   this function succeeds.  The application must not submit frame to
- *   that stream ID before :type:`nghttp2_before_frame_send_callback`
- *   is called for this frame.
- *
- */
-NGHTTP2_EXTERN int32_t nghttp2_submit_push_promise(
-    nghttp2_session *session, uint8_t flags, int32_t stream_id,
-    const nghttp2_nv *nva, size_t nvlen, void *promised_stream_user_data);
-
-/**
- * @function
- *
- * Submits PING frame.  You don't have to send PING back when you
- * received PING frame.  The library automatically submits PING frame
- * in this case.
- *
- * The |flags| is bitwise OR of 0 or more of the following value.
- *
- * * :enum:`NGHTTP2_FLAG_ACK`
- *
- * Unless `nghttp2_option_set_no_auto_ping_ack()` is used, the |flags|
- * should be :enum:`NGHTTP2_FLAG_NONE`.
- *
- * If the |opaque_data| is non ``NULL``, then it should point to the 8
- * bytes array of memory to specify opaque data to send with PING
- * frame.  If the |opaque_data| is ``NULL``, zero-cleared 8 bytes will
- * be sent as opaque data.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int nghttp2_submit_ping(nghttp2_session *session, uint8_t flags,
-                                       const uint8_t *opaque_data);
-
-/**
- * @function
- *
- * Submits GOAWAY frame with the last stream ID |last_stream_id| and
- * the error code |error_code|.
- *
- * The pre-defined error code is one of :enum:`nghttp2_error_code`.
- *
- * The |flags| is currently ignored and should be
- * :enum:`NGHTTP2_FLAG_NONE`.
- *
- * The |last_stream_id| is peer's stream ID or 0.  So if |session| is
- * initialized as client, |last_stream_id| must be even or 0.  If
- * |session| is initialized as server, |last_stream_id| must be odd or
- * 0.
- *
- * The HTTP/2 specification says last_stream_id must not be increased
- * from the value previously sent.  So the actual value sent as
- * last_stream_id is the minimum value between the given
- * |last_stream_id| and the last_stream_id previously sent to the
- * peer.
- *
- * If the |opaque_data| is not ``NULL`` and |opaque_data_len| is not
- * zero, those data will be sent as additional debug data.  The
- * library makes a copy of the memory region pointed by |opaque_data|
- * with the length |opaque_data_len|, so the caller does not need to
- * keep this memory after the return of this function.  If the
- * |opaque_data_len| is 0, the |opaque_data| could be ``NULL``.
- *
- * After successful transmission of GOAWAY, following things happen.
- * All incoming streams having strictly more than |last_stream_id| are
- * closed.  All incoming HEADERS which starts new stream are simply
- * ignored.  After all active streams are handled, both
- * `nghttp2_session_want_read()` and `nghttp2_session_want_write()`
- * return 0 and the application can close session.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |opaque_data_len| is too large; the |last_stream_id| is
- *     invalid.
- */
-NGHTTP2_EXTERN int nghttp2_submit_goaway(nghttp2_session *session,
-                                         uint8_t flags, int32_t last_stream_id,
-                                         uint32_t error_code,
-                                         const uint8_t *opaque_data,
-                                         size_t opaque_data_len);
-
-/**
- * @function
- *
- * Returns the last stream ID of a stream for which
- * :type:`nghttp2_on_frame_recv_callback` was invoked most recently.
- * The returned value can be used as last_stream_id parameter for
- * `nghttp2_submit_goaway()` and
- * `nghttp2_session_terminate_session2()`.
- *
- * This function always succeeds.
- */
-NGHTTP2_EXTERN int32_t
-nghttp2_session_get_last_proc_stream_id(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns nonzero if new request can be sent from local endpoint.
- *
- * This function return 0 if request is not allowed for this session.
- * There are several reasons why request is not allowed.  Some of the
- * reasons are: session is server; stream ID has been spent; GOAWAY
- * has been sent or received.
- *
- * The application can call `nghttp2_submit_request()` without
- * consulting this function.  In that case, `nghttp2_submit_request()`
- * may return error.  Or, request is failed to sent, and
- * :type:`nghttp2_on_stream_close_callback` is called.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_check_request_allowed(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns nonzero if |session| is initialized as server side session.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_check_server_session(nghttp2_session *session);
-
-/**
- * @function
- *
- * Submits WINDOW_UPDATE frame.
- *
- * The |flags| is currently ignored and should be
- * :enum:`NGHTTP2_FLAG_NONE`.
- *
- * The |stream_id| is the stream ID to send this WINDOW_UPDATE.  To
- * send connection level WINDOW_UPDATE, specify 0 to |stream_id|.
- *
- * If the |window_size_increment| is positive, the WINDOW_UPDATE with
- * that value as window_size_increment is queued.  If the
- * |window_size_increment| is larger than the received bytes from the
- * remote endpoint, the local window size is increased by that
- * difference.  If the sole purpose is to increase the local window
- * size, consider to use `nghttp2_session_set_local_window_size()`.
- *
- * If the |window_size_increment| is negative, the local window size
- * is decreased by -|window_size_increment|.  If automatic
- * WINDOW_UPDATE is enabled
- * (`nghttp2_option_set_no_auto_window_update()`), and the library
- * decided that the WINDOW_UPDATE should be submitted, then
- * WINDOW_UPDATE is queued with the current received bytes count.  If
- * the sole purpose is to decrease the local window size, consider to
- * use `nghttp2_session_set_local_window_size()`.
- *
- * If the |window_size_increment| is 0, the function does nothing and
- * returns 0.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_FLOW_CONTROL`
- *     The local window size overflow or gets negative.
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int nghttp2_submit_window_update(nghttp2_session *session,
-                                                uint8_t flags,
-                                                int32_t stream_id,
-                                                int32_t window_size_increment);
-
-/**
- * @function
- *
- * Set local window size (local endpoints's window size) to the given
- * |window_size| for the given stream denoted by |stream_id|.  To
- * change connection level window size, specify 0 to |stream_id|.  To
- * increase window size, this function may submit WINDOW_UPDATE frame
- * to transmission queue.
- *
- * The |flags| is currently ignored and should be
- * :enum:`NGHTTP2_FLAG_NONE`.
- *
- * This sounds similar to `nghttp2_submit_window_update()`, but there
- * are 2 differences.  The first difference is that this function
- * takes the absolute value of window size to set, rather than the
- * delta.  To change the window size, this may be easier to use since
- * the application just declares the intended window size, rather than
- * calculating delta.  The second difference is that
- * `nghttp2_submit_window_update()` affects the received bytes count
- * which has not acked yet.  By the specification of
- * `nghttp2_submit_window_update()`, to strictly increase the local
- * window size, we have to submit delta including all received bytes
- * count, which might not be desirable in some cases.  On the other
- * hand, this function does not affect the received bytes count.  It
- * just sets the local window size to the given value.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The |stream_id| is negative.
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int
-nghttp2_session_set_local_window_size(nghttp2_session *session, uint8_t flags,
-                                      int32_t stream_id, int32_t window_size);
-
-/**
- * @function
- *
- * Submits extension frame.
- *
- * Application can pass arbitrary frame flags and stream ID in |flags|
- * and |stream_id| respectively.  The |payload| is opaque pointer, and
- * it can be accessible though ``frame->ext.payload`` in
- * :type:`nghttp2_pack_extension_callback`.  The library will not own
- * passed |payload| pointer.
- *
- * The application must set :type:`nghttp2_pack_extension_callback`
- * using `nghttp2_session_callbacks_set_pack_extension_callback()`.
- *
- * The application should retain the memory pointed by |payload| until
- * the transmission of extension frame is done (which is indicated by
- * :type:`nghttp2_on_frame_send_callback`), or transmission fails
- * (which is indicated by :type:`nghttp2_on_frame_not_send_callback`).
- * If application does not touch this memory region after packing it
- * into a wire format, application can free it inside
- * :type:`nghttp2_pack_extension_callback`.
- *
- * The standard HTTP/2 frame cannot be sent with this function, so
- * |type| must be strictly grater than 0x9.  Otherwise, this function
- * will fail with error code :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_INVALID_STATE`
- *     If :type:`nghttp2_pack_extension_callback` is not set.
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     If  |type| specifies  standard  HTTP/2 frame  type.  The  frame
- *     types  in the  rage [0x0,  0x9], both  inclusive, are  standard
- *     HTTP/2 frame type, and cannot be sent using this function.
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory
- */
-NGHTTP2_EXTERN int nghttp2_submit_extension(nghttp2_session *session,
-                                            uint8_t type, uint8_t flags,
-                                            int32_t stream_id, void *payload);
-
-/**
- * @struct
- *
- * The payload of ALTSVC frame.  ALTSVC frame is a non-critical
- * extension to HTTP/2.  If this frame is received, and
- * `nghttp2_option_set_user_recv_extension_type()` is not set, and
- * `nghttp2_option_set_builtin_recv_extension_type()` is set for
- * :enum:`NGHTTP2_ALTSVC`, ``nghttp2_extension.payload`` will point to
- * this struct.
- *
- * It has the following members:
- */
-typedef struct {
-  /**
-   * The pointer to origin which this alternative service is
-   * associated with.  This is not necessarily NULL-terminated.
-   */
-  uint8_t *origin;
-  /**
-   * The length of the |origin|.
-   */
-  size_t origin_len;
-  /**
-   * The pointer to Alt-Svc field value contained in ALTSVC frame.
-   * This is not necessarily NULL-terminated.
-   */
-  uint8_t *field_value;
-  /**
-   * The length of the |field_value|.
-   */
-  size_t field_value_len;
-} nghttp2_ext_altsvc;
-
-/**
- * @function
- *
- * Submits ALTSVC frame.
- *
- * ALTSVC frame is a non-critical extension to HTTP/2, and defined in
- * is defined in `RFC 7383
- * <https://tools.ietf.org/html/rfc7838#section-4>`_.
- *
- * The |flags| is currently ignored and should be
- * :enum:`NGHTTP2_FLAG_NONE`.
- *
- * The |origin| points to the origin this alternative service is
- * associated with.  The |origin_len| is the length of the origin.  If
- * |stream_id| is 0, the origin must be specified.  If |stream_id| is
- * not zero, the origin must be empty (in other words, |origin_len|
- * must be 0).
- *
- * The ALTSVC frame is only usable from server side.  If this function
- * is invoked with client side session, this function returns
- * :enum:`NGHTTP2_ERR_INVALID_STATE`.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory
- * :enum:`NGHTTP2_ERR_INVALID_STATE`
- *     The function is called from client side session
- * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT`
- *     The sum of |origin_len| and |field_value_len| is larger than
- *     16382; or |origin_len| is 0 while |stream_id| is 0; or
- *     |origin_len| is not 0 while |stream_id| is not 0.
- */
-NGHTTP2_EXTERN int nghttp2_submit_altsvc(nghttp2_session *session,
-                                         uint8_t flags, int32_t stream_id,
-                                         const uint8_t *origin,
-                                         size_t origin_len,
-                                         const uint8_t *field_value,
-                                         size_t field_value_len);
-
-/**
- * @function
- *
- * Compares ``lhs->name`` of length ``lhs->namelen`` bytes and
- * ``rhs->name`` of length ``rhs->namelen`` bytes.  Returns negative
- * integer if ``lhs->name`` is found to be less than ``rhs->name``; or
- * returns positive integer if ``lhs->name`` is found to be greater
- * than ``rhs->name``; or returns 0 otherwise.
- */
-NGHTTP2_EXTERN int nghttp2_nv_compare_name(const nghttp2_nv *lhs,
-                                           const nghttp2_nv *rhs);
-
-/**
- * @function
- *
- * A helper function for dealing with NPN in client side or ALPN in
- * server side.  The |in| contains peer's protocol list in preferable
- * order.  The format of |in| is length-prefixed and not
- * null-terminated.  For example, ``h2`` and
- * ``http/1.1`` stored in |in| like this::
- *
- *     in[0] = 2
- *     in[1..2] = "h2"
- *     in[3] = 8
- *     in[4..11] = "http/1.1"
- *     inlen = 12
- *
- * The selection algorithm is as follows:
- *
- * 1. If peer's list contains HTTP/2 protocol the library supports,
- *    it is selected and returns 1. The following step is not taken.
- *
- * 2. If peer's list contains ``http/1.1``, this function selects
- *    ``http/1.1`` and returns 0.  The following step is not taken.
- *
- * 3. This function selects nothing and returns -1 (So called
- *    non-overlap case).  In this case, |out| and |outlen| are left
- *    untouched.
- *
- * Selecting ``h2`` means that ``h2`` is written into |*out| and its
- * length (which is 2) is assigned to |*outlen|.
- *
- * For ALPN, refer to https://tools.ietf.org/html/rfc7301
- *
- * See http://technotes.googlecode.com/git/nextprotoneg.html for more
- * details about NPN.
- *
- * For NPN, to use this method you should do something like::
- *
- *     static int select_next_proto_cb(SSL* ssl,
- *                                     unsigned char **out,
- *                                     unsigned char *outlen,
- *                                     const unsigned char *in,
- *                                     unsigned int inlen,
- *                                     void *arg)
- *     {
- *         int rv;
- *         rv = nghttp2_select_next_protocol(out, outlen, in, inlen);
- *         if (rv == -1) {
- *             return SSL_TLSEXT_ERR_NOACK;
- *         }
- *         if (rv == 1) {
- *             ((MyType*)arg)->http2_selected = 1;
- *         }
- *         return SSL_TLSEXT_ERR_OK;
- *     }
- *     ...
- *     SSL_CTX_set_next_proto_select_cb(ssl_ctx, select_next_proto_cb, my_obj);
- *
- */
-NGHTTP2_EXTERN int nghttp2_select_next_protocol(unsigned char **out,
-                                                unsigned char *outlen,
-                                                const unsigned char *in,
-                                                unsigned int inlen);
-
-/**
- * @function
- *
- * Returns a pointer to a nghttp2_info struct with version information
- * about the run-time library in use.  The |least_version| argument
- * can be set to a 24 bit numerical value for the least accepted
- * version number and if the condition is not met, this function will
- * return a ``NULL``.  Pass in 0 to skip the version checking.
- */
-NGHTTP2_EXTERN nghttp2_info *nghttp2_version(int least_version);
-
-/**
- * @function
- *
- * Returns nonzero if the :type:`nghttp2_error` library error code
- * |lib_error| is fatal.
- */
-NGHTTP2_EXTERN int nghttp2_is_fatal(int lib_error_code);
-
-/**
- * @function
- *
- * Returns nonzero if HTTP header field name |name| of length |len| is
- * valid according to http://tools.ietf.org/html/rfc7230#section-3.2
- *
- * Because this is a header field name in HTTP2, the upper cased alphabet
- * is treated as error.
- */
-NGHTTP2_EXTERN int nghttp2_check_header_name(const uint8_t *name, size_t len);
-
-/**
- * @function
- *
- * Returns nonzero if HTTP header field value |value| of length |len|
- * is valid according to
- * http://tools.ietf.org/html/rfc7230#section-3.2
- */
-NGHTTP2_EXTERN int nghttp2_check_header_value(const uint8_t *value, size_t len);
-
-/* HPACK API */
-
-struct nghttp2_hd_deflater;
-
-/**
- * @struct
- *
- * HPACK deflater object.
- */
-typedef struct nghttp2_hd_deflater nghttp2_hd_deflater;
-
-/**
- * @function
- *
- * Initializes |*deflater_ptr| for deflating name/values pairs.
- *
- * The |max_deflate_dynamic_table_size| is the upper bound of header
- * table size the deflater will use.
- *
- * If this function fails, |*deflater_ptr| is left untouched.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int
-nghttp2_hd_deflate_new(nghttp2_hd_deflater **deflater_ptr,
-                       size_t max_deflate_dynamic_table_size);
-
-/**
- * @function
- *
- * Like `nghttp2_hd_deflate_new()`, but with additional custom memory
- * allocator specified in the |mem|.
- *
- * The |mem| can be ``NULL`` and the call is equivalent to
- * `nghttp2_hd_deflate_new()`.
- *
- * This function does not take ownership |mem|.  The application is
- * responsible for freeing |mem|.
- *
- * The library code does not refer to |mem| pointer after this
- * function returns, so the application can safely free it.
- */
-NGHTTP2_EXTERN int
-nghttp2_hd_deflate_new2(nghttp2_hd_deflater **deflater_ptr,
-                        size_t max_deflate_dynamic_table_size,
-                        nghttp2_mem *mem);
-
-/**
- * @function
- *
- * Deallocates any resources allocated for |deflater|.
- */
-NGHTTP2_EXTERN void nghttp2_hd_deflate_del(nghttp2_hd_deflater *deflater);
-
-/**
- * @function
- *
- * Changes header table size of the |deflater| to
- * |settings_max_dynamic_table_size| bytes.  This may trigger eviction
- * in the dynamic table.
- *
- * The |settings_max_dynamic_table_size| should be the value received
- * in SETTINGS_HEADER_TABLE_SIZE.
- *
- * The deflater never uses more memory than
- * ``max_deflate_dynamic_table_size`` bytes specified in
- * `nghttp2_hd_deflate_new()`.  Therefore, if
- * |settings_max_dynamic_table_size| >
- * ``max_deflate_dynamic_table_size``, resulting maximum table size
- * becomes ``max_deflate_dynamic_table_size``.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int
-nghttp2_hd_deflate_change_table_size(nghttp2_hd_deflater *deflater,
-                                     size_t settings_max_dynamic_table_size);
-
-/**
- * @function
- *
- * Deflates the |nva|, which has the |nvlen| name/value pairs, into
- * the |buf| of length |buflen|.
- *
- * If |buf| is not large enough to store the deflated header block,
- * this function fails with :enum:`NGHTTP2_ERR_INSUFF_BUFSIZE`.  The
- * caller should use `nghttp2_hd_deflate_bound()` to know the upper
- * bound of buffer size required to deflate given header name/value
- * pairs.
- *
- * Once this function fails, subsequent call of this function always
- * returns :enum:`NGHTTP2_ERR_HEADER_COMP`.
- *
- * After this function returns, it is safe to delete the |nva|.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_HEADER_COMP`
- *     Deflation process has failed.
- * :enum:`NGHTTP2_ERR_INSUFF_BUFSIZE`
- *     The provided |buflen| size is too small to hold the output.
- */
-NGHTTP2_EXTERN ssize_t nghttp2_hd_deflate_hd(nghttp2_hd_deflater *deflater,
-                                             uint8_t *buf, size_t buflen,
-                                             const nghttp2_nv *nva,
-                                             size_t nvlen);
-
-/**
- * @function
- *
- * Deflates the |nva|, which has the |nvlen| name/value pairs, into
- * the |veclen| size of buf vector |vec|.  The each size of buffer
- * must be set in len field of :type:`nghttp2_vec`.  If and only if
- * one chunk is filled up completely, next chunk will be used.  If
- * |vec| is not large enough to store the deflated header block, this
- * function fails with :enum:`NGHTTP2_ERR_INSUFF_BUFSIZE`.  The caller
- * should use `nghttp2_hd_deflate_bound()` to know the upper bound of
- * buffer size required to deflate given header name/value pairs.
- *
- * Once this function fails, subsequent call of this function always
- * returns :enum:`NGHTTP2_ERR_HEADER_COMP`.
- *
- * After this function returns, it is safe to delete the |nva|.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_HEADER_COMP`
- *     Deflation process has failed.
- * :enum:`NGHTTP2_ERR_INSUFF_BUFSIZE`
- *     The provided |buflen| size is too small to hold the output.
- */
-NGHTTP2_EXTERN ssize_t nghttp2_hd_deflate_hd_vec(nghttp2_hd_deflater *deflater,
-                                                 const nghttp2_vec *vec,
-                                                 size_t veclen,
-                                                 const nghttp2_nv *nva,
-                                                 size_t nvlen);
-
-/**
- * @function
- *
- * Returns an upper bound on the compressed size after deflation of
- * |nva| of length |nvlen|.
- */
-NGHTTP2_EXTERN size_t nghttp2_hd_deflate_bound(nghttp2_hd_deflater *deflater,
-                                               const nghttp2_nv *nva,
-                                               size_t nvlen);
-
-/**
- * @function
- *
- * Returns the number of entries that header table of |deflater|
- * contains.  This is the sum of the number of static table and
- * dynamic table, so the return value is at least 61.
- */
-NGHTTP2_EXTERN
-size_t nghttp2_hd_deflate_get_num_table_entries(nghttp2_hd_deflater *deflater);
-
-/**
- * @function
- *
- * Returns the table entry denoted by |idx| from header table of
- * |deflater|.  The |idx| is 1-based, and idx=1 returns first entry of
- * static table.  idx=62 returns first entry of dynamic table if it
- * exists.  Specifying idx=0 is error, and this function returns NULL.
- * If |idx| is strictly greater than the number of entries the tables
- * contain, this function returns NULL.
- */
-NGHTTP2_EXTERN
-const nghttp2_nv *
-nghttp2_hd_deflate_get_table_entry(nghttp2_hd_deflater *deflater, size_t idx);
-
-/**
- * @function
- *
- * Returns the used dynamic table size, including the overhead 32
- * bytes per entry described in RFC 7541.
- */
-NGHTTP2_EXTERN
-size_t nghttp2_hd_deflate_get_dynamic_table_size(nghttp2_hd_deflater *deflater);
-
-/**
- * @function
- *
- * Returns the maximum dynamic table size.
- */
-NGHTTP2_EXTERN
-size_t
-nghttp2_hd_deflate_get_max_dynamic_table_size(nghttp2_hd_deflater *deflater);
-
-struct nghttp2_hd_inflater;
-
-/**
- * @struct
- *
- * HPACK inflater object.
- */
-typedef struct nghttp2_hd_inflater nghttp2_hd_inflater;
-
-/**
- * @function
- *
- * Initializes |*inflater_ptr| for inflating name/values pairs.
- *
- * If this function fails, |*inflater_ptr| is left untouched.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- */
-NGHTTP2_EXTERN int nghttp2_hd_inflate_new(nghttp2_hd_inflater **inflater_ptr);
-
-/**
- * @function
- *
- * Like `nghttp2_hd_inflate_new()`, but with additional custom memory
- * allocator specified in the |mem|.
- *
- * The |mem| can be ``NULL`` and the call is equivalent to
- * `nghttp2_hd_inflate_new()`.
- *
- * This function does not take ownership |mem|.  The application is
- * responsible for freeing |mem|.
- *
- * The library code does not refer to |mem| pointer after this
- * function returns, so the application can safely free it.
- */
-NGHTTP2_EXTERN int nghttp2_hd_inflate_new2(nghttp2_hd_inflater **inflater_ptr,
-                                           nghttp2_mem *mem);
-
-/**
- * @function
- *
- * Deallocates any resources allocated for |inflater|.
- */
-NGHTTP2_EXTERN void nghttp2_hd_inflate_del(nghttp2_hd_inflater *inflater);
-
-/**
- * @function
- *
- * Changes header table size in the |inflater|.  This may trigger
- * eviction in the dynamic table.
- *
- * The |settings_max_dynamic_table_size| should be the value
- * transmitted in SETTINGS_HEADER_TABLE_SIZE.
- *
- * This function must not be called while header block is being
- * inflated.  In other words, this function must be called after
- * initialization of |inflater|, but before calling
- * `nghttp2_hd_inflate_hd2()`, or after
- * `nghttp2_hd_inflate_end_headers()`.  Otherwise,
- * `NGHTTP2_ERR_INVALID_STATE` was returned.
- *
- * This function returns 0 if it succeeds, or one of the following
- * negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_INVALID_STATE`
- *     The function is called while header block is being inflated.
- *     Probably, application missed to call
- *     `nghttp2_hd_inflate_end_headers()`.
- */
-NGHTTP2_EXTERN int
-nghttp2_hd_inflate_change_table_size(nghttp2_hd_inflater *inflater,
-                                     size_t settings_max_dynamic_table_size);
-
-/**
- * @enum
- *
- * The flags for header inflation.
- */
-typedef enum {
-  /**
-   * No flag set.
-   */
-  NGHTTP2_HD_INFLATE_NONE = 0,
-  /**
-   * Indicates all headers were inflated.
-   */
-  NGHTTP2_HD_INFLATE_FINAL = 0x01,
-  /**
-   * Indicates a header was emitted.
-   */
-  NGHTTP2_HD_INFLATE_EMIT = 0x02
-} nghttp2_hd_inflate_flag;
-
-/**
- * @function
- *
- * .. warning::
- *
- *   Deprecated.  Use `nghttp2_hd_inflate_hd2()` instead.
- *
- * Inflates name/value block stored in |in| with length |inlen|.  This
- * function performs decompression.  For each successful emission of
- * header name/value pair, :enum:`NGHTTP2_HD_INFLATE_EMIT` is set in
- * |*inflate_flags| and name/value pair is assigned to the |nv_out|
- * and the function returns.  The caller must not free the members of
- * |nv_out|.
- *
- * The |nv_out| may include pointers to the memory region in the |in|.
- * The caller must retain the |in| while the |nv_out| is used.
- *
- * The application should call this function repeatedly until the
- * ``(*inflate_flags) & NGHTTP2_HD_INFLATE_FINAL`` is nonzero and
- * return value is non-negative.  This means the all input values are
- * processed successfully.  Then the application must call
- * `nghttp2_hd_inflate_end_headers()` to prepare for the next header
- * block input.
- *
- * The caller can feed complete compressed header block.  It also can
- * feed it in several chunks.  The caller must set |in_final| to
- * nonzero if the given input is the last block of the compressed
- * header.
- *
- * This function returns the number of bytes processed if it succeeds,
- * or one of the following negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_HEADER_COMP`
- *     Inflation process has failed.
- * :enum:`NGHTTP2_ERR_BUFFER_ERROR`
- *     The header field name or value is too large.
- *
- * Example follows::
- *
- *     int inflate_header_block(nghttp2_hd_inflater *hd_inflater,
- *                              uint8_t *in, size_t inlen, int final)
- *     {
- *         ssize_t rv;
- *
- *         for(;;) {
- *             nghttp2_nv nv;
- *             int inflate_flags = 0;
- *
- *             rv = nghttp2_hd_inflate_hd(hd_inflater, &nv, &inflate_flags,
- *                                        in, inlen, final);
- *
- *             if(rv < 0) {
- *                 fprintf(stderr, "inflate failed with error code %zd", rv);
- *                 return -1;
- *             }
- *
- *             in += rv;
- *             inlen -= rv;
- *
- *             if(inflate_flags & NGHTTP2_HD_INFLATE_EMIT) {
- *                 fwrite(nv.name, nv.namelen, 1, stderr);
- *                 fprintf(stderr, ": ");
- *                 fwrite(nv.value, nv.valuelen, 1, stderr);
- *                 fprintf(stderr, "\n");
- *             }
- *             if(inflate_flags & NGHTTP2_HD_INFLATE_FINAL) {
- *                 nghttp2_hd_inflate_end_headers(hd_inflater);
- *                 break;
- *             }
- *             if((inflate_flags & NGHTTP2_HD_INFLATE_EMIT) == 0 &&
- *                inlen == 0) {
- *                break;
- *             }
- *         }
- *
- *         return 0;
- *     }
- *
- */
-NGHTTP2_EXTERN ssize_t nghttp2_hd_inflate_hd(nghttp2_hd_inflater *inflater,
-                                             nghttp2_nv *nv_out,
-                                             int *inflate_flags, uint8_t *in,
-                                             size_t inlen, int in_final);
-
-/**
- * @function
- *
- * Inflates name/value block stored in |in| with length |inlen|.  This
- * function performs decompression.  For each successful emission of
- * header name/value pair, :enum:`NGHTTP2_HD_INFLATE_EMIT` is set in
- * |*inflate_flags| and name/value pair is assigned to the |nv_out|
- * and the function returns.  The caller must not free the members of
- * |nv_out|.
- *
- * The |nv_out| may include pointers to the memory region in the |in|.
- * The caller must retain the |in| while the |nv_out| is used.
- *
- * The application should call this function repeatedly until the
- * ``(*inflate_flags) & NGHTTP2_HD_INFLATE_FINAL`` is nonzero and
- * return value is non-negative.  If that happens, all given input
- * data (|inlen| bytes) are processed successfully.  Then the
- * application must call `nghttp2_hd_inflate_end_headers()` to prepare
- * for the next header block input.
- *
- * In other words, if |in_final| is nonzero, and this function returns
- * |inlen|, you can assert that :enum:`NGHTTP2_HD_INFLATE_FINAL` is
- * set in |*inflate_flags|.
- *
- * The caller can feed complete compressed header block.  It also can
- * feed it in several chunks.  The caller must set |in_final| to
- * nonzero if the given input is the last block of the compressed
- * header.
- *
- * This function returns the number of bytes processed if it succeeds,
- * or one of the following negative error codes:
- *
- * :enum:`NGHTTP2_ERR_NOMEM`
- *     Out of memory.
- * :enum:`NGHTTP2_ERR_HEADER_COMP`
- *     Inflation process has failed.
- * :enum:`NGHTTP2_ERR_BUFFER_ERROR`
- *     The header field name or value is too large.
- *
- * Example follows::
- *
- *     int inflate_header_block(nghttp2_hd_inflater *hd_inflater,
- *                              uint8_t *in, size_t inlen, int final)
- *     {
- *         ssize_t rv;
- *
- *         for(;;) {
- *             nghttp2_nv nv;
- *             int inflate_flags = 0;
- *
- *             rv = nghttp2_hd_inflate_hd2(hd_inflater, &nv, &inflate_flags,
- *                                         in, inlen, final);
- *
- *             if(rv < 0) {
- *                 fprintf(stderr, "inflate failed with error code %zd", rv);
- *                 return -1;
- *             }
- *
- *             in += rv;
- *             inlen -= rv;
- *
- *             if(inflate_flags & NGHTTP2_HD_INFLATE_EMIT) {
- *                 fwrite(nv.name, nv.namelen, 1, stderr);
- *                 fprintf(stderr, ": ");
- *                 fwrite(nv.value, nv.valuelen, 1, stderr);
- *                 fprintf(stderr, "\n");
- *             }
- *             if(inflate_flags & NGHTTP2_HD_INFLATE_FINAL) {
- *                 nghttp2_hd_inflate_end_headers(hd_inflater);
- *                 break;
- *             }
- *             if((inflate_flags & NGHTTP2_HD_INFLATE_EMIT) == 0 &&
- *                inlen == 0) {
- *                break;
- *             }
- *         }
- *
- *         return 0;
- *     }
- *
- */
-NGHTTP2_EXTERN ssize_t nghttp2_hd_inflate_hd2(nghttp2_hd_inflater *inflater,
-                                              nghttp2_nv *nv_out,
-                                              int *inflate_flags,
-                                              const uint8_t *in, size_t inlen,
-                                              int in_final);
-
-/**
- * @function
- *
- * Signals the end of decompression for one header block.
- *
- * This function returns 0 if it succeeds. Currently this function
- * always succeeds.
- */
-NGHTTP2_EXTERN int
-nghttp2_hd_inflate_end_headers(nghttp2_hd_inflater *inflater);
-
-/**
- * @function
- *
- * Returns the number of entries that header table of |inflater|
- * contains.  This is the sum of the number of static table and
- * dynamic table, so the return value is at least 61.
- */
-NGHTTP2_EXTERN
-size_t nghttp2_hd_inflate_get_num_table_entries(nghttp2_hd_inflater *inflater);
-
-/**
- * @function
- *
- * Returns the table entry denoted by |idx| from header table of
- * |inflater|.  The |idx| is 1-based, and idx=1 returns first entry of
- * static table.  idx=62 returns first entry of dynamic table if it
- * exists.  Specifying idx=0 is error, and this function returns NULL.
- * If |idx| is strictly greater than the number of entries the tables
- * contain, this function returns NULL.
- */
-NGHTTP2_EXTERN
-const nghttp2_nv *
-nghttp2_hd_inflate_get_table_entry(nghttp2_hd_inflater *inflater, size_t idx);
-
-/**
- * @function
- *
- * Returns the used dynamic table size, including the overhead 32
- * bytes per entry described in RFC 7541.
- */
-NGHTTP2_EXTERN
-size_t nghttp2_hd_inflate_get_dynamic_table_size(nghttp2_hd_inflater *inflater);
-
-/**
- * @function
- *
- * Returns the maximum dynamic table size.
- */
-NGHTTP2_EXTERN
-size_t
-nghttp2_hd_inflate_get_max_dynamic_table_size(nghttp2_hd_inflater *inflater);
-
-struct nghttp2_stream;
-
-/**
- * @struct
- *
- * The structure to represent HTTP/2 stream.  The details of this
- * structure are intentionally hidden from the public API.
- */
-typedef struct nghttp2_stream nghttp2_stream;
-
-/**
- * @function
- *
- * Returns pointer to :type:`nghttp2_stream` object denoted by
- * |stream_id|.  If stream was not found, returns NULL.
- *
- * Returns imaginary root stream (see
- * `nghttp2_session_get_root_stream()`) if 0 is given in |stream_id|.
- *
- * Unless |stream_id| == 0, the returned pointer is valid until next
- * call of `nghttp2_session_send()`, `nghttp2_session_mem_send()`,
- * `nghttp2_session_recv()`, and `nghttp2_session_mem_recv()`.
- */
-NGHTTP2_EXTERN nghttp2_stream *
-nghttp2_session_find_stream(nghttp2_session *session, int32_t stream_id);
-
-/**
- * @enum
- *
- * State of stream as described in RFC 7540.
- */
-typedef enum {
-  /**
-   * idle state.
-   */
-  NGHTTP2_STREAM_STATE_IDLE = 1,
-  /**
-   * open state.
-   */
-  NGHTTP2_STREAM_STATE_OPEN,
-  /**
-   * reserved (local) state.
-   */
-  NGHTTP2_STREAM_STATE_RESERVED_LOCAL,
-  /**
-   * reserved (remote) state.
-   */
-  NGHTTP2_STREAM_STATE_RESERVED_REMOTE,
-  /**
-   * half closed (local) state.
-   */
-  NGHTTP2_STREAM_STATE_HALF_CLOSED_LOCAL,
-  /**
-   * half closed (remote) state.
-   */
-  NGHTTP2_STREAM_STATE_HALF_CLOSED_REMOTE,
-  /**
-   * closed state.
-   */
-  NGHTTP2_STREAM_STATE_CLOSED
-} nghttp2_stream_proto_state;
-
-/**
- * @function
- *
- * Returns state of |stream|.  The root stream retrieved by
- * `nghttp2_session_get_root_stream()` will have stream state
- * :enum:`NGHTTP2_STREAM_STATE_IDLE`.
- */
-NGHTTP2_EXTERN nghttp2_stream_proto_state
-nghttp2_stream_get_state(nghttp2_stream *stream);
-
-/**
- * @function
- *
- * Returns root of dependency tree, which is imaginary stream with
- * stream ID 0.  The returned pointer is valid until |session| is
- * freed by `nghttp2_session_del()`.
- */
-NGHTTP2_EXTERN nghttp2_stream *
-nghttp2_session_get_root_stream(nghttp2_session *session);
-
-/**
- * @function
- *
- * Returns the parent stream of |stream| in dependency tree.  Returns
- * NULL if there is no such stream.
- */
-NGHTTP2_EXTERN nghttp2_stream *
-nghttp2_stream_get_parent(nghttp2_stream *stream);
-
-NGHTTP2_EXTERN int32_t nghttp2_stream_get_stream_id(nghttp2_stream *stream);
-
-/**
- * @function
- *
- * Returns the next sibling stream of |stream| in dependency tree.
- * Returns NULL if there is no such stream.
- */
-NGHTTP2_EXTERN nghttp2_stream *
-nghttp2_stream_get_next_sibling(nghttp2_stream *stream);
-
-/**
- * @function
- *
- * Returns the previous sibling stream of |stream| in dependency tree.
- * Returns NULL if there is no such stream.
- */
-NGHTTP2_EXTERN nghttp2_stream *
-nghttp2_stream_get_previous_sibling(nghttp2_stream *stream);
-
-/**
- * @function
- *
- * Returns the first child stream of |stream| in dependency tree.
- * Returns NULL if there is no such stream.
- */
-NGHTTP2_EXTERN nghttp2_stream *
-nghttp2_stream_get_first_child(nghttp2_stream *stream);
-
-/**
- * @function
- *
- * Returns dependency weight to the parent stream of |stream|.
- */
-NGHTTP2_EXTERN int32_t nghttp2_stream_get_weight(nghttp2_stream *stream);
-
-/**
- * @function
- *
- * Returns the sum of the weight for |stream|'s children.
- */
-NGHTTP2_EXTERN int32_t
-nghttp2_stream_get_sum_dependency_weight(nghttp2_stream *stream);
-
-/**
- * @functypedef
- *
- * Callback function invoked when the library outputs debug logging.
- * The function is called with arguments suitable for ``vfprintf(3)``
- *
- * The debug output is only enabled if the library is built with
- * ``DEBUGBUILD`` macro defined.
- */
-typedef void (*nghttp2_debug_vprintf_callback)(const char *format,
-                                               va_list args);
-
-/**
- * @function
- *
- * Sets a debug output callback called by the library when built with
- * ``DEBUGBUILD`` macro defined.  If this option is not used, debug
- * log is written into standard error output.
- *
- * For builds without ``DEBUGBUILD`` macro defined, this function is
- * noop.
- *
- * Note that building with ``DEBUGBUILD`` may cause significant
- * performance penalty to libnghttp2 because of extra processing.  It
- * should be used for debugging purpose only.
- *
- * .. Warning::
- *
- *   Building with ``DEBUGBUILD`` may cause significant performance
- *   penalty to libnghttp2 because of extra processing.  It should be
- *   used for debugging purpose only.  We write this two times because
- *   this is important.
- */
-NGHTTP2_EXTERN void nghttp2_set_debug_vprintf_callback(
-    nghttp2_debug_vprintf_callback debug_vprintf_callback);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* NGHTTP2_H */
diff --git a/tools/sdk/include/nghttp/nghttp2/nghttp2ver.h b/tools/sdk/include/nghttp/nghttp2/nghttp2ver.h
deleted file mode 100644
index ccbbfb3f4af..00000000000
--- a/tools/sdk/include/nghttp/nghttp2/nghttp2ver.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * nghttp2 - HTTP/2 C Library
- *
- * Copyright (c) 2012, 2013 Tatsuhiro Tsujikawa
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef NGHTTP2VER_H
-#define NGHTTP2VER_H
-
-/**
- * @macro
- * Version number of the nghttp2 library release
- */
-#define NGHTTP2_VERSION "v1.22.0"
-
-/**
- * @macro
- * Numerical representation of the version number of the nghttp2 library
- * release. This is a 24 bit number with 8 bits for major number, 8 bits
- * for minor and 8 bits for patch. Version 1.2.3 becomes 0x010203.
- */
-#define NGHTTP2_VERSION_NUM 0x012200
-
-#endif /* NGHTTP2VER_H */
diff --git a/tools/sdk/include/nvs_flash/nvs.h b/tools/sdk/include/nvs_flash/nvs.h
deleted file mode 100644
index 1d88217ee0b..00000000000
--- a/tools/sdk/include/nvs_flash/nvs.h
+++ /dev/null
@@ -1,472 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef ESP_NVS_H
-#define ESP_NVS_H
-
-#include <stdint.h>
-#include <stddef.h>
-#include <stdbool.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Opaque pointer type representing non-volatile storage handle
- */
-typedef uint32_t nvs_handle;
-
-#define ESP_ERR_NVS_BASE                    0x1100                     /*!< Starting number of error codes */
-#define ESP_ERR_NVS_NOT_INITIALIZED         (ESP_ERR_NVS_BASE + 0x01)  /*!< The storage driver is not initialized */
-#define ESP_ERR_NVS_NOT_FOUND               (ESP_ERR_NVS_BASE + 0x02)  /*!< Id namespace doesn’t exist yet and mode is NVS_READONLY */
-#define ESP_ERR_NVS_TYPE_MISMATCH           (ESP_ERR_NVS_BASE + 0x03)  /*!< The type of set or get operation doesn't match the type of value stored in NVS */
-#define ESP_ERR_NVS_READ_ONLY               (ESP_ERR_NVS_BASE + 0x04)  /*!< Storage handle was opened as read only */
-#define ESP_ERR_NVS_NOT_ENOUGH_SPACE        (ESP_ERR_NVS_BASE + 0x05)  /*!< There is not enough space in the underlying storage to save the value */
-#define ESP_ERR_NVS_INVALID_NAME            (ESP_ERR_NVS_BASE + 0x06)  /*!< Namespace name doesn’t satisfy constraints */
-#define ESP_ERR_NVS_INVALID_HANDLE          (ESP_ERR_NVS_BASE + 0x07)  /*!< Handle has been closed or is NULL */
-#define ESP_ERR_NVS_REMOVE_FAILED           (ESP_ERR_NVS_BASE + 0x08)  /*!< The value wasn’t updated because flash write operation has failed. The value was written however, and update will be finished after re-initialization of nvs, provided that flash operation doesn’t fail again. */
-#define ESP_ERR_NVS_KEY_TOO_LONG            (ESP_ERR_NVS_BASE + 0x09)  /*!< Key name is too long */
-#define ESP_ERR_NVS_PAGE_FULL               (ESP_ERR_NVS_BASE + 0x0a)  /*!< Internal error; never returned by nvs API functions */
-#define ESP_ERR_NVS_INVALID_STATE           (ESP_ERR_NVS_BASE + 0x0b)  /*!< NVS is in an inconsistent state due to a previous error. Call nvs_flash_init and nvs_open again, then retry. */
-#define ESP_ERR_NVS_INVALID_LENGTH          (ESP_ERR_NVS_BASE + 0x0c)  /*!< String or blob length is not sufficient to store data */
-#define ESP_ERR_NVS_NO_FREE_PAGES           (ESP_ERR_NVS_BASE + 0x0d)  /*!< NVS partition doesn't contain any empty pages. This may happen if NVS partition was truncated. Erase the whole partition and call nvs_flash_init again. */
-#define ESP_ERR_NVS_VALUE_TOO_LONG          (ESP_ERR_NVS_BASE + 0x0e)  /*!< String or blob length is longer than supported by the implementation */
-#define ESP_ERR_NVS_PART_NOT_FOUND          (ESP_ERR_NVS_BASE + 0x0f)  /*!< Partition with specified name is not found in the partition table */
-
-#define ESP_ERR_NVS_NEW_VERSION_FOUND       (ESP_ERR_NVS_BASE + 0x10)  /*!< NVS partition contains data in new format and cannot be recognized by this version of code */
-#define ESP_ERR_NVS_XTS_ENCR_FAILED         (ESP_ERR_NVS_BASE + 0x11)  /*!< XTS encryption failed while writing NVS entry */
-#define ESP_ERR_NVS_XTS_DECR_FAILED         (ESP_ERR_NVS_BASE + 0x12)  /*!< XTS decryption failed while reading NVS entry */
-#define ESP_ERR_NVS_XTS_CFG_FAILED          (ESP_ERR_NVS_BASE + 0x13)  /*!< XTS configuration setting failed */
-#define ESP_ERR_NVS_XTS_CFG_NOT_FOUND       (ESP_ERR_NVS_BASE + 0x14)  /*!< XTS configuration not found */
-#define ESP_ERR_NVS_ENCR_NOT_SUPPORTED      (ESP_ERR_NVS_BASE + 0x15)  /*!< NVS encryption is not supported in this version */
-#define ESP_ERR_NVS_KEYS_NOT_INITIALIZED    (ESP_ERR_NVS_BASE + 0x16)  /*!< NVS key partition is uninitialized */
-#define ESP_ERR_NVS_CORRUPT_KEY_PART        (ESP_ERR_NVS_BASE + 0x17)  /*!< NVS key partition is corrupt */
-
-
-#define NVS_DEFAULT_PART_NAME           "nvs"   /*!< Default partition name of the NVS partition in the partition table */
-/**
- * @brief Mode of opening the non-volatile storage
- *
- */
-typedef enum {
-	NVS_READONLY,  /*!< Read only */
-	NVS_READWRITE  /*!< Read and write */
-} nvs_open_mode;
-
-typedef enum {
-    NVS_TYPE_U8    = 0x01,
-    NVS_TYPE_I8    = 0x11,
-    NVS_TYPE_U16   = 0x02,
-    NVS_TYPE_I16   = 0x12,
-    NVS_TYPE_U32   = 0x04,
-    NVS_TYPE_I32   = 0x14,
-    NVS_TYPE_U64   = 0x08,
-    NVS_TYPE_I64   = 0x18,
-    NVS_TYPE_STR   = 0x21,
-    NVS_TYPE_BLOB  = 0x42,
-    NVS_TYPE_ANY   = 0xff // Must be last
-} nvs_type_t;
-
-/**
- * @brief      Open non-volatile storage with a given namespace from the default NVS partition
- *
- * Multiple internal ESP-IDF and third party application modules can store
- * their key-value pairs in the NVS module. In order to reduce possible
- * conflicts on key names, each module can use its own namespace.
- * The default NVS partition is the one that is labelled "nvs" in the partition
- * table.
- *
- * @param[in]  name        Namespace name. Maximal length is determined by the
- *                         underlying implementation, but is guaranteed to be
- *                         at least 15 characters. Shouldn't be empty.
- * @param[in]  open_mode   NVS_READWRITE or NVS_READONLY. If NVS_READONLY, will
- *                         open a handle for reading only. All write requests will
- *			   be rejected for this handle.
- * @param[out] out_handle  If successful (return code is zero), handle will be
- *                         returned in this argument.
- *
- * @return
- *             - ESP_OK if storage handle was opened successfully
- *             - ESP_ERR_NVS_NOT_INITIALIZED if the storage driver is not initialized
- *             - ESP_ERR_NVS_PART_NOT_FOUND if the partition with label "nvs" is not found
- *             - ESP_ERR_NVS_NOT_FOUND id namespace doesn't exist yet and
- *               mode is NVS_READONLY
- *             - ESP_ERR_NVS_INVALID_NAME if namespace name doesn't satisfy constraints
- *             - other error codes from the underlying storage driver
- */
-esp_err_t nvs_open(const char* name, nvs_open_mode open_mode, nvs_handle *out_handle);
-
-/**
- * @brief      Open non-volatile storage with a given namespace from specified partition
- *
- * The behaviour is same as nvs_open() API. However this API can operate on a specified NVS
- * partition instead of default NVS partition. Note that the specified partition must be registered
- * with NVS using nvs_flash_init_partition() API.
- *
- * @param[in]  part_name   Label (name) of the partition of interest for object read/write/erase
- * @param[in]  name        Namespace name. Maximal length is determined by the
- *                         underlying implementation, but is guaranteed to be
- *                         at least 15 characters. Shouldn't be empty.
- * @param[in]  open_mode   NVS_READWRITE or NVS_READONLY. If NVS_READONLY, will 
- *                         open a handle for reading only. All write requests will 
- *			   be rejected for this handle.
- * @param[out] out_handle  If successful (return code is zero), handle will be
- *                         returned in this argument.
- *
- * @return
- *             - ESP_OK if storage handle was opened successfully
- *             - ESP_ERR_NVS_NOT_INITIALIZED if the storage driver is not initialized
- *             - ESP_ERR_NVS_PART_NOT_FOUND if the partition with specified name is not found
- *             - ESP_ERR_NVS_NOT_FOUND id namespace doesn't exist yet and
- *               mode is NVS_READONLY
- *             - ESP_ERR_NVS_INVALID_NAME if namespace name doesn't satisfy constraints
- *             - other error codes from the underlying storage driver
- */
-esp_err_t nvs_open_from_partition(const char *part_name, const char* name, nvs_open_mode open_mode, nvs_handle *out_handle);
-
-/**@{*/
-/**
- * @brief      set value for given key
- *
- * This family of functions set value for the key, given its name. Note that
- * actual storage will not be updated until nvs_commit function is called.
- *
- * @param[in]  handle  Handle obtained from nvs_open function.
- *                     Handles that were opened read only cannot be used.
- * @param[in]  key     Key name. Maximal length is determined by the underlying
- *                     implementation, but is guaranteed to be at least
- *                     15 characters. Shouldn't be empty.
- * @param[in]  value   The value to set.
- *                     For strings, the maximum length (including null character) is
- *                     4000 bytes.
- *
- * @return
- *             - ESP_OK if value was set successfully
- *             - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
- *             - ESP_ERR_NVS_READ_ONLY if storage handle was opened as read only
- *             - ESP_ERR_NVS_INVALID_NAME if key name doesn't satisfy constraints
- *             - ESP_ERR_NVS_NOT_ENOUGH_SPACE if there is not enough space in the
- *               underlying storage to save the value
- *             - ESP_ERR_NVS_REMOVE_FAILED if the value wasn't updated because flash
- *               write operation has failed. The value was written however, and
- *               update will be finished after re-initialization of nvs, provided that
- *               flash operation doesn't fail again.
- *             - ESP_ERR_NVS_VALUE_TOO_LONG if the string value is too long
- */
-esp_err_t nvs_set_i8  (nvs_handle handle, const char* key, int8_t value);
-esp_err_t nvs_set_u8  (nvs_handle handle, const char* key, uint8_t value);
-esp_err_t nvs_set_i16 (nvs_handle handle, const char* key, int16_t value);
-esp_err_t nvs_set_u16 (nvs_handle handle, const char* key, uint16_t value);
-esp_err_t nvs_set_i32 (nvs_handle handle, const char* key, int32_t value);
-esp_err_t nvs_set_u32 (nvs_handle handle, const char* key, uint32_t value);
-esp_err_t nvs_set_i64 (nvs_handle handle, const char* key, int64_t value);
-esp_err_t nvs_set_u64 (nvs_handle handle, const char* key, uint64_t value);
-esp_err_t nvs_set_str (nvs_handle handle, const char* key, const char* value);
-/**@}*/ 
-
-/**
- * @brief       set variable length binary value for given key
- *
- * This family of functions set value for the key, given its name. Note that
- * actual storage will not be updated until nvs_commit function is called.
- *
- * @param[in]  handle  Handle obtained from nvs_open function.
- *                     Handles that were opened read only cannot be used.
- * @param[in]  key     Key name. Maximal length is 15 characters. Shouldn't be empty.
- * @param[in]  value   The value to set.
- * @param[in]  length  length of binary value to set, in bytes; Maximum length is
- *                     508000 bytes or (97.6% of the partition size - 4000) bytes
- *                     whichever is lower.
- *
- * @return
- *             - ESP_OK if value was set successfully
- *             - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
- *             - ESP_ERR_NVS_READ_ONLY if storage handle was opened as read only
- *             - ESP_ERR_NVS_INVALID_NAME if key name doesn't satisfy constraints
- *             - ESP_ERR_NVS_NOT_ENOUGH_SPACE if there is not enough space in the
- *               underlying storage to save the value
- *             - ESP_ERR_NVS_REMOVE_FAILED if the value wasn't updated because flash
- *               write operation has failed. The value was written however, and
- *               update will be finished after re-initialization of nvs, provided that
- *               flash operation doesn't fail again.
- *             - ESP_ERR_NVS_VALUE_TOO_LONG if the value is too long
- */
-esp_err_t nvs_set_blob(nvs_handle handle, const char* key, const void* value, size_t length);
-
-/**@{*/
-/**
- * @brief      get value for given key
- *
- * These functions retrieve value for the key, given its name. If key does not
- * exist, or the requested variable type doesn't match the type which was used
- * when setting a value, an error is returned.
- *
- * In case of any error, out_value is not modified.
- *
- * All functions expect out_value to be a pointer to an already allocated variable
- * of the given type.
- *
- * \code{c}
- * // Example of using nvs_get_i32:
- * int32_t max_buffer_size = 4096; // default value
- * esp_err_t err = nvs_get_i32(my_handle, "max_buffer_size", &max_buffer_size);
- * assert(err == ESP_OK || err == ESP_ERR_NVS_NOT_FOUND);
- * // if ESP_ERR_NVS_NOT_FOUND was returned, max_buffer_size will still
- * // have its default value.
- *
- * \endcode
- *
- * @param[in]     handle     Handle obtained from nvs_open function.
- * @param[in]     key        Key name. Maximal length is determined by the underlying
- *                           implementation, but is guaranteed to be at least
- *                           15 characters. Shouldn't be empty.
- * @param         out_value  Pointer to the output value.
- *                           May be NULL for nvs_get_str and nvs_get_blob, in this
- *                           case required length will be returned in length argument.
- *
- * @return
- *             - ESP_OK if the value was retrieved successfully
- *             - ESP_ERR_NVS_NOT_FOUND if the requested key doesn't exist
- *             - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
- *             - ESP_ERR_NVS_INVALID_NAME if key name doesn't satisfy constraints
- *             - ESP_ERR_NVS_INVALID_LENGTH if length is not sufficient to store data
- */
-esp_err_t nvs_get_i8  (nvs_handle handle, const char* key, int8_t* out_value);
-esp_err_t nvs_get_u8  (nvs_handle handle, const char* key, uint8_t* out_value);
-esp_err_t nvs_get_i16 (nvs_handle handle, const char* key, int16_t* out_value);
-esp_err_t nvs_get_u16 (nvs_handle handle, const char* key, uint16_t* out_value);
-esp_err_t nvs_get_i32 (nvs_handle handle, const char* key, int32_t* out_value);
-esp_err_t nvs_get_u32 (nvs_handle handle, const char* key, uint32_t* out_value);
-esp_err_t nvs_get_i64 (nvs_handle handle, const char* key, int64_t* out_value);
-esp_err_t nvs_get_u64 (nvs_handle handle, const char* key, uint64_t* out_value);
-/**@}*/ 
-
-/**
- * @brief      get value for given key
- *
- * These functions retrieve value for the key, given its name. If key does not
- * exist, or the requested variable type doesn't match the type which was used
- * when setting a value, an error is returned.
- *
- * In case of any error, out_value is not modified.
- *
- * All functions expect out_value to be a pointer to an already allocated variable
- * of the given type.
- * 
- * nvs_get_str and nvs_get_blob functions support WinAPI-style length queries.
- * To get the size necessary to store the value, call nvs_get_str or nvs_get_blob
- * with zero out_value and non-zero pointer to length. Variable pointed to
- * by length argument will be set to the required length. For nvs_get_str,
- * this length includes the zero terminator. When calling nvs_get_str and
- * nvs_get_blob with non-zero out_value, length has to be non-zero and has to
- * point to the length available in out_value.
- * It is suggested that nvs_get/set_str is used for zero-terminated C strings, and
- * nvs_get/set_blob used for arbitrary data structures.
- *
- * \code{c}
- * // Example (without error checking) of using nvs_get_str to get a string into dynamic array:
- * size_t required_size;
- * nvs_get_str(my_handle, "server_name", NULL, &required_size);
- * char* server_name = malloc(required_size);
- * nvs_get_str(my_handle, "server_name", server_name, &required_size);
- *
- * // Example (without error checking) of using nvs_get_blob to get a binary data
- * into a static array:
- * uint8_t mac_addr[6];
- * size_t size = sizeof(mac_addr);
- * nvs_get_blob(my_handle, "dst_mac_addr", mac_addr, &size);
- * \endcode
- *
- * @param[in]     handle     Handle obtained from nvs_open function.
- * @param[in]     key        Key name. Maximal length is determined by the underlying
- *                           implementation, but is guaranteed to be at least
- *                           15 characters. Shouldn't be empty.
- * @param         out_value  Pointer to the output value.
- *                           May be NULL for nvs_get_str and nvs_get_blob, in this
- *                           case required length will be returned in length argument.
- * @param[inout]  length     A non-zero pointer to the variable holding the length of out_value.
- *                           In case out_value a zero, will be set to the length
- *                           required to hold the value. In case out_value is not
- *                           zero, will be set to the actual length of the value
- *                           written. For nvs_get_str this includes zero terminator.
- *
- * @return
- *             - ESP_OK if the value was retrieved successfully
- *             - ESP_ERR_NVS_NOT_FOUND if the requested key doesn't exist
- *             - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
- *             - ESP_ERR_NVS_INVALID_NAME if key name doesn't satisfy constraints
- *             - ESP_ERR_NVS_INVALID_LENGTH if length is not sufficient to store data
- */
-/**@{*/
-esp_err_t nvs_get_str (nvs_handle handle, const char* key, char* out_value, size_t* length);
-esp_err_t nvs_get_blob(nvs_handle handle, const char* key, void* out_value, size_t* length);
-/**@}*/
-
-/**
- * @brief      Erase key-value pair with given key name.
- *
- * Note that actual storage may not be updated until nvs_commit function is called.
- *
- * @param[in]  handle  Storage handle obtained with nvs_open.
- *                     Handles that were opened read only cannot be used.
- *
- * @param[in]  key     Key name. Maximal length is determined by the underlying
- *                     implementation, but is guaranteed to be at least
- *                     15 characters. Shouldn't be empty.
- *
- * @return
- *              - ESP_OK if erase operation was successful
- *              - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
- *              - ESP_ERR_NVS_READ_ONLY if handle was opened as read only
- *              - ESP_ERR_NVS_NOT_FOUND if the requested key doesn't exist
- *              - other error codes from the underlying storage driver
- */
-esp_err_t nvs_erase_key(nvs_handle handle, const char* key);
-
-/**
- * @brief      Erase all key-value pairs in a namespace
- *
- * Note that actual storage may not be updated until nvs_commit function is called.
- *
- * @param[in]  handle  Storage handle obtained with nvs_open.
- *                     Handles that were opened read only cannot be used.
- *
- * @return
- *              - ESP_OK if erase operation was successful
- *              - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
- *              - ESP_ERR_NVS_READ_ONLY if handle was opened as read only
- *              - other error codes from the underlying storage driver
- */
-esp_err_t nvs_erase_all(nvs_handle handle);
-
-/**
- * @brief      Write any pending changes to non-volatile storage
- *
- * After setting any values, nvs_commit() must be called to ensure changes are written
- * to non-volatile storage. Individual implementations may write to storage at other times,
- * but this is not guaranteed.
- *
- * @param[in]  handle  Storage handle obtained with nvs_open.
- *                     Handles that were opened read only cannot be used.
- *
- * @return
- *             - ESP_OK if the changes have been written successfully
- *             - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL
- *             - other error codes from the underlying storage driver
- */
-esp_err_t nvs_commit(nvs_handle handle);
-
-/**
- * @brief      Close the storage handle and free any allocated resources
- *
- * This function should be called for each handle opened with nvs_open once
- * the handle is not in use any more. Closing the handle may not automatically
- * write the changes to nonvolatile storage. This has to be done explicitly using
- * nvs_commit function.
- * Once this function is called on a handle, the handle should no longer be used.
- *
- * @param[in]  handle  Storage handle to close
- */
-void nvs_close(nvs_handle handle);
-
-/**
- * @note Info about storage space NVS.
- */
-typedef struct {
-    size_t used_entries;      /**< Amount of used entries. */
-    size_t free_entries;      /**< Amount of free entries. */
-    size_t total_entries;     /**< Amount all available entries. */
-    size_t namespace_count;   /**< Amount name space. */
-} nvs_stats_t;
-
-/**
- * @brief      Fill structure nvs_stats_t. It provides info about used memory the partition.
- *
- * This function calculates to runtime the number of used entries, free entries, total entries,
- * and amount namespace in partition.
- *
- * \code{c}
- * // Example of nvs_get_stats() to get the number of used entries and free entries:
- * nvs_stats_t nvs_stats;
- * nvs_get_stats(NULL, &nvs_stats);
- * printf("Count: UsedEntries = (%d), FreeEntries = (%d), AllEntries = (%d)\n",
-          nvs_stats.used_entries, nvs_stats.free_entries, nvs_stats.total_entries);
- * \endcode
- *
- * @param[in]   part_name   Partition name NVS in the partition table.
- *                          If pass a NULL than will use NVS_DEFAULT_PART_NAME ("nvs").
- *
- * @param[out]  nvs_stats   Returns filled structure nvs_states_t.
- *                          It provides info about used memory the partition.
- *
- *
- * @return
- *             - ESP_OK if the changes have been written successfully.
- *               Return param nvs_stats will be filled.
- *             - ESP_ERR_NVS_PART_NOT_FOUND if the partition with label "name" is not found.
- *               Return param nvs_stats will be filled 0.
- *             - ESP_ERR_NVS_NOT_INITIALIZED if the storage driver is not initialized.
- *               Return param nvs_stats will be filled 0.
- *             - ESP_ERR_INVALID_ARG if nvs_stats equal to NULL.
- *             - ESP_ERR_INVALID_STATE if there is page with the status of INVALID.
- *               Return param nvs_stats will be filled not with correct values because
- *               not all pages will be counted. Counting will be interrupted at the first INVALID page.
- */
-esp_err_t nvs_get_stats(const char* part_name, nvs_stats_t* nvs_stats);
-
-/**
- * @brief      Calculate all entries in a namespace.
- *
- * Note that to find out the total number of records occupied by the namespace,
- * add one to the returned value used_entries (if err is equal to ESP_OK).
- * Because the name space entry takes one entry.
- *
- * \code{c}
- * // Example of nvs_get_used_entry_count() to get amount of all key-value pairs in one namespace:
- * nvs_handle handle;
- * nvs_open("namespace1", NVS_READWRITE, &handle);
- * ...
- * size_t used_entries;
- * size_t total_entries_namespace;
- * if(nvs_get_used_entry_count(handle, &used_entries) == ESP_OK){
- *     // the total number of records occupied by the namespace
- *     total_entries_namespace = used_entries + 1;
- * }
- * \endcode
- *
- * @param[in]   handle              Handle obtained from nvs_open function.
- *
- * @param[out]  used_entries        Returns amount of used entries from a namespace.
- *
- *
- * @return
- *             - ESP_OK if the changes have been written successfully.
- *               Return param used_entries will be filled valid value.
- *             - ESP_ERR_NVS_NOT_INITIALIZED if the storage driver is not initialized.
- *               Return param used_entries will be filled 0.
- *             - ESP_ERR_NVS_INVALID_HANDLE if handle has been closed or is NULL.
- *               Return param used_entries will be filled 0.
- *             - ESP_ERR_INVALID_ARG if nvs_stats equal to NULL.
- *             - Other error codes from the underlying storage driver.
- *               Return param used_entries will be filled 0.
- */
-esp_err_t nvs_get_used_entry_count(nvs_handle handle, size_t* used_entries);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif //ESP_NVS_H
-
diff --git a/tools/sdk/include/nvs_flash/nvs_flash.h b/tools/sdk/include/nvs_flash/nvs_flash.h
deleted file mode 100644
index 55b218ec56e..00000000000
--- a/tools/sdk/include/nvs_flash/nvs_flash.h
+++ /dev/null
@@ -1,194 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef nvs_flash_h
-#define nvs_flash_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "nvs.h"
-#include "esp_partition.h"
-
-
-#define NVS_KEY_SIZE 32 // AES-256
-
-/**
- * @brief Key for encryption and decryption
- */
-typedef struct {
-    uint8_t eky[NVS_KEY_SIZE]; /*!<  XTS encryption and decryption key*/
-    uint8_t tky[NVS_KEY_SIZE]; /*!<  XTS tweak key */
-} nvs_sec_cfg_t;
-
-/**
- * @brief Initialize the default NVS partition.
- *
- * This API initialises the default NVS partition. The default NVS partition
- * is the one that is labeled "nvs" in the partition table.
- *
- * @return
- *      - ESP_OK if storage was successfully initialized.
- *      - ESP_ERR_NVS_NO_FREE_PAGES if the NVS storage contains no empty pages
- *        (which may happen if NVS partition was truncated)
- *      - ESP_ERR_NOT_FOUND if no partition with label "nvs" is found in the partition table
- *      - one of the error codes from the underlying flash storage driver
- */
-esp_err_t nvs_flash_init(void);
-
-/**
- * @brief Initialize NVS flash storage for the specified partition.
- *
- * @param[in]  partition_label   Label of the partition. Note that internally a reference to
- *                               passed value is kept and it should be accessible for future operations
- *
- * @return
- *      - ESP_OK if storage was successfully initialized.
- *      - ESP_ERR_NVS_NO_FREE_PAGES if the NVS storage contains no empty pages
- *        (which may happen if NVS partition was truncated)
- *      - ESP_ERR_NOT_FOUND if specified partition is not found in the partition table
- *      - one of the error codes from the underlying flash storage driver
- */
-esp_err_t nvs_flash_init_partition(const char *partition_label);
-
-/**
- * @brief Deinitialize NVS storage for the default NVS partition
- *
- * Default NVS partition is the partition with "nvs" label in the partition table.
- *
- * @return
- *      - ESP_OK on success (storage was deinitialized)
- *      - ESP_ERR_NVS_NOT_INITIALIZED if the storage was not initialized prior to this call
- */
-esp_err_t nvs_flash_deinit(void);
-
-/**
- * @brief Deinitialize NVS storage for the given NVS partition
- *
- * @param[in]  partition_label   Label of the partition
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NVS_NOT_INITIALIZED if the storage for given partition was not
- *        initialized prior to this call
- */
-esp_err_t nvs_flash_deinit_partition(const char* partition_label);
-
-/**
- * @brief Erase the default NVS partition
- *
- * This function erases all contents of the default NVS partition (one with label "nvs")
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NOT_FOUND if there is no NVS partition labeled "nvs" in the
- *        partition table
- */
-esp_err_t nvs_flash_erase(void);
-
-/**
- * @brief Erase specified NVS partition
- *
- * This function erases all contents of specified NVS partition
- *
- * @param[in]  part_name    Name (label) of the partition to be erased
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NOT_FOUND if there is no NVS partition with the specified name
- *        in the partition table
- */
-esp_err_t nvs_flash_erase_partition(const char *part_name);
-
-
-/**
- * @brief Initialize the default NVS partition.
- *
- * This API initialises the default NVS partition. The default NVS partition
- * is the one that is labeled "nvs" in the partition table.
- *
- * @param[in]  cfg Security configuration (keys) to be used for NVS encryption/decryption. 
- *                              If cfg is NULL, no encryption is used. 
- *
- * @return
- *      - ESP_OK if storage was successfully initialized.
- *      - ESP_ERR_NVS_NO_FREE_PAGES if the NVS storage contains no empty pages
- *        (which may happen if NVS partition was truncated)
- *      - ESP_ERR_NOT_FOUND if no partition with label "nvs" is found in the partition table
- *      - one of the error codes from the underlying flash storage driver
- */
-esp_err_t nvs_flash_secure_init(nvs_sec_cfg_t* cfg);
-
-/**
- * @brief Initialize NVS flash storage for the specified partition.
- *
- * @param[in]  partition_label   Label of the partition. Note that internally a reference to
- *                               passed value is kept and it should be accessible for future operations
- *
- * @param[in]  cfg Security configuration (keys) to be used for NVS encryption/decryption. 
- *                              If cfg is null, no encryption/decryption is used. 
- * @return
- *      - ESP_OK if storage was successfully initialized.
- *      - ESP_ERR_NVS_NO_FREE_PAGES if the NVS storage contains no empty pages
- *        (which may happen if NVS partition was truncated)
- *      - ESP_ERR_NOT_FOUND if specified partition is not found in the partition table
- *      - one of the error codes from the underlying flash storage driver
- */
-esp_err_t nvs_flash_secure_init_partition(const char *partition_label, nvs_sec_cfg_t* cfg);
-
-/**
- * @brief Generate and store NVS keys in the provided esp partition
- * 
- * @param[in]  partition Pointer to partition structure obtained using
- *                       esp_partition_find_first or esp_partition_get.
- *                       Must be non-NULL.
- * @param[out] cfg       Pointer to nvs security configuration structure.
- *                       Pointer must be non-NULL. 
- *                       Generated keys will be populated in this structure.
- *
- *
- * @return 
- *      -ESP_OK, if cfg was read successfully;
- *      -or error codes from esp_partition_write/erase APIs.
- */
-
-esp_err_t nvs_flash_generate_keys(const esp_partition_t* partition, nvs_sec_cfg_t* cfg);
-
-
-/**
- * @brief Read NVS security configuration from a partition. 
- * 
- * @param[in]  partition Pointer to partition structure obtained using
- *                       esp_partition_find_first or esp_partition_get.
- *                       Must be non-NULL.
- * @param[out] cfg       Pointer to nvs security configuration structure.
- *                       Pointer must be non-NULL.
- *
- * @note  Provided parition is assumed to be marked 'encrypted'.
- *
- * @return 
- *      -ESP_OK, if cfg was read successfully;
- *      -ESP_ERR_NVS_KEYS_NOT_INITIALIZED, if the partition is not yet written with keys.
- *      -ESP_ERR_NVS_CORRUPT_KEY_PART, if the partition containing keys is found to be corrupt
- *      -or error codes from esp_partition_read API.
- */
-
-esp_err_t nvs_flash_read_security_cfg(const esp_partition_t* partition, nvs_sec_cfg_t* cfg);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* nvs_flash_h */
diff --git a/tools/sdk/include/openssl/internal/ssl3.h b/tools/sdk/include/openssl/internal/ssl3.h
deleted file mode 100644
index 007b392f3e0..00000000000
--- a/tools/sdk/include/openssl/internal/ssl3.h
+++ /dev/null
@@ -1,44 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL3_H_
-#define _SSL3_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-# define SSL3_AD_CLOSE_NOTIFY             0
-# define SSL3_AD_UNEXPECTED_MESSAGE      10/* fatal */
-# define SSL3_AD_BAD_RECORD_MAC          20/* fatal */
-# define SSL3_AD_DECOMPRESSION_FAILURE   30/* fatal */
-# define SSL3_AD_HANDSHAKE_FAILURE       40/* fatal */
-# define SSL3_AD_NO_CERTIFICATE          41
-# define SSL3_AD_BAD_CERTIFICATE         42
-# define SSL3_AD_UNSUPPORTED_CERTIFICATE 43
-# define SSL3_AD_CERTIFICATE_REVOKED     44
-# define SSL3_AD_CERTIFICATE_EXPIRED     45
-# define SSL3_AD_CERTIFICATE_UNKNOWN     46
-# define SSL3_AD_ILLEGAL_PARAMETER       47/* fatal */
-
-# define SSL3_AL_WARNING                  1
-# define SSL3_AL_FATAL                    2
-
-#define SSL3_VERSION                 0x0300
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/ssl_cert.h b/tools/sdk/include/openssl/internal/ssl_cert.h
deleted file mode 100644
index 86cf31ad513..00000000000
--- a/tools/sdk/include/openssl/internal/ssl_cert.h
+++ /dev/null
@@ -1,55 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_CERT_H_
-#define _SSL_CERT_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ssl_types.h"
-
-/**
- * @brief create a certification object include private key object according to input certification
- *
- * @param ic - input certification point
- *
- * @return certification object point
- */
-CERT *__ssl_cert_new(CERT *ic);
-
-/**
- * @brief create a certification object include private key object
- *
- * @param none
- *
- * @return certification object point
- */
-CERT* ssl_cert_new(void);
-
-/**
- * @brief free a certification object
- *
- * @param cert - certification object point
- *
- * @return none
- */
-void ssl_cert_free(CERT *cert);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/ssl_code.h b/tools/sdk/include/openssl/internal/ssl_code.h
deleted file mode 100644
index 80fdbb20f33..00000000000
--- a/tools/sdk/include/openssl/internal/ssl_code.h
+++ /dev/null
@@ -1,124 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_CODE_H_
-#define _SSL_CODE_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ssl3.h"
-#include "tls1.h"
-#include "x509_vfy.h"
-
-/* Used in SSL_set_shutdown()/SSL_get_shutdown(); */
-# define SSL_SENT_SHUTDOWN       1
-# define SSL_RECEIVED_SHUTDOWN   2
-
-# define SSL_VERIFY_NONE                 0x00
-# define SSL_VERIFY_PEER                 0x01
-# define SSL_VERIFY_FAIL_IF_NO_PEER_CERT 0x02
-# define SSL_VERIFY_CLIENT_ONCE          0x04
-
-/*
- * The following 3 states are kept in ssl->rlayer.rstate when reads fail, you
- * should not need these
- */
-# define SSL_ST_READ_HEADER                      0xF0
-# define SSL_ST_READ_BODY                        0xF1
-# define SSL_ST_READ_DONE                        0xF2
-
-# define SSL_NOTHING            1
-# define SSL_WRITING            2
-# define SSL_READING            3
-# define SSL_X509_LOOKUP        4
-# define SSL_ASYNC_PAUSED       5
-# define SSL_ASYNC_NO_JOBS      6
-
-
-# define SSL_ERROR_NONE                  0
-# define SSL_ERROR_SSL                   1
-# define SSL_ERROR_WANT_READ             2
-# define SSL_ERROR_WANT_WRITE            3
-# define SSL_ERROR_WANT_X509_LOOKUP      4
-# define SSL_ERROR_SYSCALL               5/* look at error stack/return value/errno */
-# define SSL_ERROR_ZERO_RETURN           6
-# define SSL_ERROR_WANT_CONNECT          7
-# define SSL_ERROR_WANT_ACCEPT           8
-# define SSL_ERROR_WANT_ASYNC            9
-# define SSL_ERROR_WANT_ASYNC_JOB       10
-
-/* Message flow states */
-typedef enum {
-    /* No handshake in progress */
-    MSG_FLOW_UNINITED,
-    /* A permanent error with this connection */
-    MSG_FLOW_ERROR,
-    /* We are about to renegotiate */
-    MSG_FLOW_RENEGOTIATE,
-    /* We are reading messages */
-    MSG_FLOW_READING,
-    /* We are writing messages */
-    MSG_FLOW_WRITING,
-    /* Handshake has finished */
-    MSG_FLOW_FINISHED
-} MSG_FLOW_STATE;
-
-/* SSL subsystem states */
-typedef enum {
-    TLS_ST_BEFORE,
-    TLS_ST_OK,
-    DTLS_ST_CR_HELLO_VERIFY_REQUEST,
-    TLS_ST_CR_SRVR_HELLO,
-    TLS_ST_CR_CERT,
-    TLS_ST_CR_CERT_STATUS,
-    TLS_ST_CR_KEY_EXCH,
-    TLS_ST_CR_CERT_REQ,
-    TLS_ST_CR_SRVR_DONE,
-    TLS_ST_CR_SESSION_TICKET,
-    TLS_ST_CR_CHANGE,
-    TLS_ST_CR_FINISHED,
-    TLS_ST_CW_CLNT_HELLO,
-    TLS_ST_CW_CERT,
-    TLS_ST_CW_KEY_EXCH,
-    TLS_ST_CW_CERT_VRFY,
-    TLS_ST_CW_CHANGE,
-    TLS_ST_CW_NEXT_PROTO,
-    TLS_ST_CW_FINISHED,
-    TLS_ST_SW_HELLO_REQ,
-    TLS_ST_SR_CLNT_HELLO,
-    DTLS_ST_SW_HELLO_VERIFY_REQUEST,
-    TLS_ST_SW_SRVR_HELLO,
-    TLS_ST_SW_CERT,
-    TLS_ST_SW_KEY_EXCH,
-    TLS_ST_SW_CERT_REQ,
-    TLS_ST_SW_SRVR_DONE,
-    TLS_ST_SR_CERT,
-    TLS_ST_SR_KEY_EXCH,
-    TLS_ST_SR_CERT_VRFY,
-    TLS_ST_SR_NEXT_PROTO,
-    TLS_ST_SR_CHANGE,
-    TLS_ST_SR_FINISHED,
-    TLS_ST_SW_SESSION_TICKET,
-    TLS_ST_SW_CERT_STATUS,
-    TLS_ST_SW_CHANGE,
-    TLS_ST_SW_FINISHED
-} OSSL_HANDSHAKE_STATE;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/ssl_dbg.h b/tools/sdk/include/openssl/internal/ssl_dbg.h
deleted file mode 100644
index 12ba25f99d8..00000000000
--- a/tools/sdk/include/openssl/internal/ssl_dbg.h
+++ /dev/null
@@ -1,191 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_DEBUG_H_
-#define _SSL_DEBUG_H_
-
-#include "platform/ssl_opt.h"
-#include "platform/ssl_port.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifdef CONFIG_OPENSSL_DEBUG_LEVEL
-    #define SSL_DEBUG_LEVEL CONFIG_OPENSSL_DEBUG_LEVEL
-#else
-    #define SSL_DEBUG_LEVEL 0
-#endif
-
-#define SSL_DEBUG_ON  (SSL_DEBUG_LEVEL + 1)
-#define SSL_DEBUG_OFF (SSL_DEBUG_LEVEL - 1)
-
-#ifdef CONFIG_OPENSSL_DEBUG
-    #ifndef SSL_DEBUG_LOG
-        #error "SSL_DEBUG_LOG is not defined"
-    #endif
-
-    #ifndef SSL_DEBUG_FL
-        #define SSL_DEBUG_FL "\n"
-    #endif
-
-    #define SSL_SHOW_LOCATION()                         \
-        SSL_DEBUG_LOG("SSL assert : %s %d\n",           \
-            __FILE__, __LINE__)
-
-    #define SSL_DEBUG(level, fmt, ...)                  \
-    {                                                   \
-        if (level > SSL_DEBUG_LEVEL) {                  \
-            SSL_DEBUG_LOG(fmt SSL_DEBUG_FL, ##__VA_ARGS__); \
-        }                                               \
-    }
-#else /* CONFIG_OPENSSL_DEBUG */
-    #define SSL_SHOW_LOCATION()
-
-    #define SSL_DEBUG(level, fmt, ...)
-#endif /* CONFIG_OPENSSL_DEBUG */
-
-/**
- * OpenSSL assert function
- *
- * if select "CONFIG_OPENSSL_ASSERT_DEBUG", SSL_ASSERT* will show error file name and line
- * if select "CONFIG_OPENSSL_ASSERT_EXIT", SSL_ASSERT* will just return error code.
- * if select "CONFIG_OPENSSL_ASSERT_DEBUG_EXIT" SSL_ASSERT* will show error file name and line,
- * then return error code.
- * if select "CONFIG_OPENSSL_ASSERT_DEBUG_BLOCK", SSL_ASSERT* will show error file name and line,
- * then block here with "while (1)"
- *
- * SSL_ASSERT1 may will return "-1", so function's return argument is integer.
- * SSL_ASSERT2 may will return "NULL", so function's return argument is a point.
- * SSL_ASSERT2 may will return nothing, so function's return argument is "void".
- */
-#if defined(CONFIG_OPENSSL_ASSERT_DEBUG)
-    #define SSL_ASSERT1(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            SSL_SHOW_LOCATION();                        \
-        }                                               \
-    }
-
-    #define SSL_ASSERT2(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            SSL_SHOW_LOCATION();                        \
-        }                                               \
-    }
-
-    #define SSL_ASSERT3(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            SSL_SHOW_LOCATION();                        \
-        }                                               \
-    }
-#elif defined(CONFIG_OPENSSL_ASSERT_EXIT)
-    #define SSL_ASSERT1(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            return -1;                                  \
-        }                                               \
-    }
-
-    #define SSL_ASSERT2(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            return NULL;                                \
-        }                                               \
-    }
-
-    #define SSL_ASSERT3(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            return ;                                    \
-        }                                               \
-    }
-#elif defined(CONFIG_OPENSSL_ASSERT_DEBUG_EXIT)
-    #define SSL_ASSERT1(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            SSL_SHOW_LOCATION();                        \
-            return -1;                                  \
-        }                                               \
-    }
-
-    #define SSL_ASSERT2(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            SSL_SHOW_LOCATION();                        \
-            return NULL;                                \
-        }                                               \
-    }
-
-    #define SSL_ASSERT3(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            SSL_SHOW_LOCATION();                        \
-            return ;                                    \
-        }                                               \
-    }
-#elif defined(CONFIG_OPENSSL_ASSERT_DEBUG_BLOCK)
-    #define SSL_ASSERT1(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            SSL_SHOW_LOCATION();                        \
-            while (1);                                  \
-        }                                               \
-    }
-
-    #define SSL_ASSERT2(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            SSL_SHOW_LOCATION();                        \
-            while (1);                                  \
-        }                                               \
-    }
-
-    #define SSL_ASSERT3(s)                              \
-    {                                                   \
-        if (!(s)) {                                     \
-            SSL_SHOW_LOCATION();                        \
-            while (1);                                  \
-        }                                               \
-    }
-#else
-    #define SSL_ASSERT1(s)
-    #define SSL_ASSERT2(s)
-    #define SSL_ASSERT3(s)
-#endif
-
-#define SSL_PLATFORM_DEBUG_LEVEL SSL_DEBUG_OFF
-#define SSL_PLATFORM_ERROR_LEVEL SSL_DEBUG_ON
-
-#define SSL_CERT_DEBUG_LEVEL     SSL_DEBUG_OFF
-#define SSL_CERT_ERROR_LEVEL     SSL_DEBUG_ON
-
-#define SSL_PKEY_DEBUG_LEVEL     SSL_DEBUG_OFF
-#define SSL_PKEY_ERROR_LEVEL     SSL_DEBUG_ON
-
-#define SSL_X509_DEBUG_LEVEL     SSL_DEBUG_OFF
-#define SSL_X509_ERROR_LEVEL     SSL_DEBUG_ON
-
-#define SSL_LIB_DEBUG_LEVEL      SSL_DEBUG_OFF
-#define SSL_LIB_ERROR_LEVEL      SSL_DEBUG_ON
-
-#define SSL_STACK_DEBUG_LEVEL    SSL_DEBUG_OFF
-#define SSL_STACK_ERROR_LEVEL    SSL_DEBUG_ON
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/ssl_lib.h b/tools/sdk/include/openssl/internal/ssl_lib.h
deleted file mode 100644
index bf7de22fdf0..00000000000
--- a/tools/sdk/include/openssl/internal/ssl_lib.h
+++ /dev/null
@@ -1,28 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_LIB_H_
-#define _SSL_LIB_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ssl_types.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/ssl_methods.h b/tools/sdk/include/openssl/internal/ssl_methods.h
deleted file mode 100644
index 17cf9bb6974..00000000000
--- a/tools/sdk/include/openssl/internal/ssl_methods.h
+++ /dev/null
@@ -1,122 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_METHODS_H_
-#define _SSL_METHODS_H_
-
-#include "ssl_types.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- * TLS method function implement
- */
-#define IMPLEMENT_TLS_METHOD_FUNC(func_name, \
-                    new, free, \
-                    handshake, shutdown, clear, \
-                    read, send, pending, \
-                    set_fd, set_hostname, get_fd,	\
-                    set_bufflen, \
-                    get_verify_result, \
-                    get_state) \
-        static const SSL_METHOD_FUNC func_name LOCAL_ATRR = { \
-                new, \
-                free, \
-                handshake, \
-                shutdown, \
-                clear, \
-                read, \
-                send, \
-                pending, \
-                set_fd, \
-		set_hostname, \
-                get_fd, \
-                set_bufflen, \
-                get_verify_result, \
-                get_state \
-        };
-
-#define IMPLEMENT_TLS_METHOD(ver, mode, fun, func_name) \
-    const SSL_METHOD* func_name(void) { \
-        static const SSL_METHOD func_name##_data LOCAL_ATRR = { \
-                ver, \
-                mode, \
-                &(fun), \
-        }; \
-        return &func_name##_data; \
-    }
-
-#define IMPLEMENT_SSL_METHOD(ver, mode, fun, func_name) \
-    const SSL_METHOD* func_name(void) { \
-        static const SSL_METHOD func_name##_data LOCAL_ATRR = { \
-                ver, \
-                mode, \
-                &(fun), \
-        }; \
-        return &func_name##_data; \
-    }
-
-#define IMPLEMENT_X509_METHOD(func_name, \
-                new, \
-                free, \
-                load, \
-                show_info) \
-    const X509_METHOD* func_name(void) { \
-        static const X509_METHOD func_name##_data LOCAL_ATRR = { \
-                new, \
-                free, \
-                load, \
-                show_info \
-        }; \
-        return &func_name##_data; \
-    }
-
-#define IMPLEMENT_PKEY_METHOD(func_name, \
-                new, \
-                free, \
-                load) \
-    const PKEY_METHOD* func_name(void) { \
-        static const PKEY_METHOD func_name##_data LOCAL_ATRR = { \
-                new, \
-                free, \
-                load \
-        }; \
-        return &func_name##_data; \
-    }
-
-/**
- * @brief get X509 object method
- *
- * @param none
- *
- * @return X509 object method point
- */
-const X509_METHOD* X509_method(void);
-
-/**
- * @brief get private key object method
- *
- * @param none
- *
- * @return private key object method point
- */
-const PKEY_METHOD* EVP_PKEY_method(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/ssl_pkey.h b/tools/sdk/include/openssl/internal/ssl_pkey.h
deleted file mode 100644
index e790fcc995a..00000000000
--- a/tools/sdk/include/openssl/internal/ssl_pkey.h
+++ /dev/null
@@ -1,86 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_PKEY_H_
-#define _SSL_PKEY_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ssl_types.h"
-
-/**
- * @brief create a private key object according to input private key
- *
- * @param ipk - input private key point
- *
- * @return new private key object point
- */
-EVP_PKEY* __EVP_PKEY_new(EVP_PKEY *ipk);
-
-/**
- * @brief create a private key object
- *
- * @param none
- *
- * @return private key object point
- */
-EVP_PKEY* EVP_PKEY_new(void);
-
-/**
- * @brief load a character key context into system context. If '*a' is pointed to the
- *        private key, then load key into it. Or create a new private key object
- *
- * @param type   - private key type
- * @param a      - a point pointed to a private key point
- * @param pp     - a point pointed to the key context memory point
- * @param length - key bytes
- *
- * @return private key object point
- */
-EVP_PKEY* d2i_PrivateKey(int type,
-                         EVP_PKEY **a,
-                         const unsigned char **pp,
-                         long length);
-
-/**
- * @brief free a private key object
- *
- * @param pkey - private key object point
- *
- * @return none
- */
-void EVP_PKEY_free(EVP_PKEY *x);
-
-/**
- * @brief load private key into the SSL
- *
- * @param type - private key type
- * @param ssl  - SSL point
- * @param len  - data bytes
- * @param d    - data point
- *
- * @return result
- *     0 : failed
- *     1 : OK 
- */
- int SSL_use_PrivateKey_ASN1(int type, SSL *ssl, const unsigned char *d, long len);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/ssl_stack.h b/tools/sdk/include/openssl/internal/ssl_stack.h
deleted file mode 100644
index 7a7051a026b..00000000000
--- a/tools/sdk/include/openssl/internal/ssl_stack.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef _SSL_STACK_H_
-#define _SSL_STACK_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ssl_types.h"
-
-#define STACK_OF(type)  struct stack_st_##type
-
-#define SKM_DEFINE_STACK_OF(t1, t2, t3) \
-    STACK_OF(t1); \
-    static ossl_inline STACK_OF(t1) *sk_##t1##_new_null(void) \
-    { \
-        return (STACK_OF(t1) *)OPENSSL_sk_new_null(); \
-    } \
-
-#define DEFINE_STACK_OF(t) SKM_DEFINE_STACK_OF(t, t, t)
-
-/**
- * @brief create a openssl stack object
- *
- * @param c - stack function
- *
- * @return openssl stack object point
- */
-OPENSSL_STACK* OPENSSL_sk_new(OPENSSL_sk_compfunc c);
-
-/**
- * @brief create a NULL function openssl stack object
- *
- * @param none
- *
- * @return openssl stack object point
- */
-OPENSSL_STACK *OPENSSL_sk_new_null(void);
-
-/**
- * @brief free openssl stack object
- *
- * @param openssl stack object point
- *
- * @return none
- */
-void OPENSSL_sk_free(OPENSSL_STACK *stack);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/ssl_types.h b/tools/sdk/include/openssl/internal/ssl_types.h
deleted file mode 100644
index 21ba69f4c7f..00000000000
--- a/tools/sdk/include/openssl/internal/ssl_types.h
+++ /dev/null
@@ -1,311 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_TYPES_H_
-#define _SSL_TYPES_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ssl_code.h"
-
-typedef void SSL_CIPHER;
-
-typedef void X509_STORE_CTX;
-typedef void X509_STORE;
-
-typedef void RSA;
-
-typedef void STACK;
-
-#define ossl_inline inline
-
-#define SSL_METHOD_CALL(f, s, ...)        s->method->func->ssl_##f(s, ##__VA_ARGS__)
-#define X509_METHOD_CALL(f, x, ...)       x->method->x509_##f(x, ##__VA_ARGS__)
-#define EVP_PKEY_METHOD_CALL(f, k, ...)   k->method->pkey_##f(k, ##__VA_ARGS__)
-
-typedef int (*OPENSSL_sk_compfunc)(const void *, const void *);
-
-struct stack_st;
-typedef struct stack_st OPENSSL_STACK;
-
-struct ssl_method_st;
-typedef struct ssl_method_st SSL_METHOD;
-
-struct ssl_method_func_st;
-typedef struct ssl_method_func_st SSL_METHOD_FUNC;
-
-struct record_layer_st;
-typedef struct record_layer_st RECORD_LAYER;
-
-struct ossl_statem_st;
-typedef struct ossl_statem_st OSSL_STATEM;
-
-struct ssl_session_st;
-typedef struct ssl_session_st SSL_SESSION;
-
-struct ssl_ctx_st;
-typedef struct ssl_ctx_st SSL_CTX;
-
-struct ssl_st;
-typedef struct ssl_st SSL;
-
-struct cert_st;
-typedef struct cert_st CERT;
-
-struct x509_st;
-typedef struct x509_st X509;
-
-struct X509_VERIFY_PARAM_st;
-typedef struct X509_VERIFY_PARAM_st X509_VERIFY_PARAM;
-
-struct evp_pkey_st;
-typedef struct evp_pkey_st EVP_PKEY;
-
-struct x509_method_st;
-typedef struct x509_method_st X509_METHOD;
-
-struct pkey_method_st;
-typedef struct pkey_method_st PKEY_METHOD;
-
-struct ssl_alpn_st;
-typedef struct ssl_alpn_st SSL_ALPN;
-
-struct bio_st;
-typedef struct bio_st BIO;
-
-struct stack_st {
-
-    char **data;
-
-    int num_alloc;
-
-    OPENSSL_sk_compfunc c;
-};
-
-struct evp_pkey_st {
-
-    void *pkey_pm;
-
-    const PKEY_METHOD *method;
-};
-
-struct x509_st {
-
-    /* X509 certification platform private point */
-    void *x509_pm;
-
-    const X509_METHOD *method;
-
-    int ref_counter;
-};
-
-struct cert_st {
-
-    int sec_level;
-
-    X509 *x509;
-
-    EVP_PKEY *pkey;
-
-};
-
-struct ossl_statem_st {
-
-    MSG_FLOW_STATE state;
-
-    int hand_state;
-};
-
-struct record_layer_st {
-
-    int rstate;
-
-    int read_ahead;
-};
-
-struct ssl_session_st {
-
-    long timeout;
-
-    long time;
-
-    X509 *peer;
-};
-
-struct X509_VERIFY_PARAM_st {
-
-    int depth;
-
-};
-
-struct bio_st {
-    const unsigned char * data;
-    int dlen;
-};
-
-typedef enum { ALPN_INIT, ALPN_ENABLE, ALPN_DISABLE, ALPN_ERROR } ALPN_STATUS;
-struct ssl_alpn_st {
-     ALPN_STATUS alpn_status;
-     /* This is dynamically allocated */
-     char *alpn_string;
-     /* This only points to the members in the string */
-#define ALPN_LIST_MAX 10
-     const char *alpn_list[ALPN_LIST_MAX];
-};
-
-struct ssl_ctx_st
-{
-    int version;
-
-    int references;
-
-    unsigned long options;
-
-    SSL_ALPN ssl_alpn;
-
-    const SSL_METHOD *method;
-
-    CERT *cert;
-
-    X509 *client_CA;
-
-    int verify_mode;
-
-    int (*default_verify_callback) (int ok, X509_STORE_CTX *ctx);
-
-    long session_timeout;
-
-    int read_ahead;
-
-    int read_buffer_len;
-
-    X509_VERIFY_PARAM param;
-};
-
-struct ssl_st
-{
-    /* protocol version(one of SSL3.0, TLS1.0, etc.) */
-    int version;
-
-    unsigned long options;
-
-    /* shut things down(0x01 : sent, 0x02 : received) */
-    int shutdown;
-
-    CERT *cert;
-
-    X509 *client_CA;
-
-    SSL_CTX  *ctx;
-
-    const SSL_METHOD *method;
-
-    RECORD_LAYER rlayer;
-
-    /* where we are */
-    OSSL_STATEM statem;
-
-    SSL_SESSION *session;
-
-    int verify_mode;
-
-    int (*verify_callback) (int ok, X509_STORE_CTX *ctx);
-
-    int rwstate;
-
-    long verify_result;
-
-    X509_VERIFY_PARAM param;
-
-    int err;
-
-    void (*info_callback) (const SSL *ssl, int type, int val);
-
-    /* SSL low-level system arch point */
-    void *ssl_pm;
-};
-
-struct ssl_method_st {
-    /* protocol version(one of SSL3.0, TLS1.0, etc.) */
-    int version;
-
-    /* SSL mode(client(0) , server(1), not known(-1)) */
-    int endpoint;
-
-    const SSL_METHOD_FUNC *func;
-};
-
-struct ssl_method_func_st {
-
-    int (*ssl_new)(SSL *ssl);
-
-    void (*ssl_free)(SSL *ssl);
-
-    int (*ssl_handshake)(SSL *ssl);
-
-    int (*ssl_shutdown)(SSL *ssl);
-
-    int (*ssl_clear)(SSL *ssl);
-
-    int (*ssl_read)(SSL *ssl, void *buffer, int len);
-
-    int (*ssl_send)(SSL *ssl, const void *buffer, int len);
-
-    int (*ssl_pending)(const SSL *ssl);
-
-    void (*ssl_set_fd)(SSL *ssl, int fd, int mode);
-
-    void (*ssl_set_hostname)(SSL *ssl, const char *hostname);
-
-    int (*ssl_get_fd)(const SSL *ssl, int mode);
-
-    void (*ssl_set_bufflen)(SSL *ssl, int len);
-
-    long (*ssl_get_verify_result)(const SSL *ssl);
-
-    OSSL_HANDSHAKE_STATE (*ssl_get_state)(const SSL *ssl);
-};
-
-struct x509_method_st {
-
-    int (*x509_new)(X509 *x, X509 *m_x);
-
-    void (*x509_free)(X509 *x);
-
-    int (*x509_load)(X509 *x, const unsigned char *buf, int len);
-
-    int (*x509_show_info)(X509 *x);
-};
-
-struct pkey_method_st {
-
-    int (*pkey_new)(EVP_PKEY *pkey, EVP_PKEY *m_pkey);
-
-    void (*pkey_free)(EVP_PKEY *pkey);
-
-    int (*pkey_load)(EVP_PKEY *pkey, const unsigned char *buf, int len);
-};
-
-
-typedef int (*next_proto_cb)(SSL *ssl, unsigned char **out,
-                             unsigned char *outlen, const unsigned char *in,
-                             unsigned int inlen, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/ssl_x509.h b/tools/sdk/include/openssl/internal/ssl_x509.h
deleted file mode 100644
index 877c4fbb775..00000000000
--- a/tools/sdk/include/openssl/internal/ssl_x509.h
+++ /dev/null
@@ -1,175 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_X509_H_
-#define _SSL_X509_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ssl_types.h"
-#include "ssl_stack.h"
-
-DEFINE_STACK_OF(X509_NAME)
-
-/**
- * @brief create a X509 certification object according to input X509 certification
- *
- * @param ix - input X509 certification point
- *
- * @return new X509 certification object point
- */
-X509* __X509_new(X509 *ix);
-
-/**
- * @brief create a X509 certification object
- *
- * @param none
- *
- * @return X509 certification object point
- */
-X509* X509_new(void);
-
-/**
- * @brief load a character certification context into system context. If '*cert' is pointed to the
- *        certification, then load certification into it. Or create a new X509 certification object
- *
- * @param cert   - a point pointed to X509 certification
- * @param buffer - a point pointed to the certification context memory point
- * @param length - certification bytes
- *
- * @return X509 certification object point
- */
-X509* d2i_X509(X509 **cert, const unsigned char *buffer, long len);
-
-/**
- * @brief free a X509 certification object
- *
- * @param x - X509 certification object point
- *
- * @return none
- */
-void X509_free(X509 *x);
-
-/**
- * @brief set SSL context client CA certification
- *
- * @param ctx - SSL context point
- * @param x   - X509 certification point
- *
- * @return result
- *     0 : failed
- *     1 : OK
- */
-int SSL_CTX_add_client_CA(SSL_CTX *ctx, X509 *x);
-
-/**
- * @brief add CA client certification into the SSL
- *
- * @param ssl - SSL point
- * @param x   - X509 certification point
- *
- * @return result
- *     0 : failed
- *     1 : OK
- */
-int SSL_add_client_CA(SSL *ssl, X509 *x);
-
-/**
- * @brief load certification into the SSL
- *
- * @param ssl - SSL point
- * @param len - data bytes
- * @param d   - data point
- *
- * @return result
- *     0 : failed
- *     1 : OK
- *
- */
-int SSL_use_certificate_ASN1(SSL *ssl, int len, const unsigned char *d);
-
-
-/**
- * @brief set SSL context client CA certification
- *
- * @param store - pointer to X509_STORE
- * @param x     -  pointer to X509 certification point
- *
- * @return result
- *     0 : failed
- *     1 : OK
- */
-int X509_STORE_add_cert(X509_STORE *store, X509 *x);
-
-/**
- * @brief load data in BIO
- *
- * Normally BIO_write should append data but that doesn't happen here, and
- * 'data' cannot be freed after the function is called, it should remain valid 
- * until BIO object is in use.
- *
- * @param b    - pointer to BIO 
- * @param data - pointer to data
- * @param dlen - data bytes
- *
- * @return result
- *      0 : failed
- *      1 : OK
- */
-int BIO_write(BIO *b, const void *data, int dlen);
-
-/**
- * @brief load a character certification context into system context.
- *
- * If '*cert' is pointed to the certification, then load certification 
- * into it, or create a new X509 certification object.
- *
- * @param bp     - pointer to  BIO
- * @param buffer - pointer to the certification context memory
- * @param cb     - pointer to a callback which queries pass phrase used
-                   for encrypted PEM structure
- * @param u      - pointer to arbitary data passed by application to callback
- *
- * @return X509 certification object point
- */
-X509 * PEM_read_bio_X509(BIO *bp, X509 **x, void *cb, void *u);
-
-/**
- * @brief create a BIO object
- * 
- * @param method - pointer to BIO_METHOD
- *
- * @return pointer to BIO object
- */
-BIO *BIO_new(void * method);
-
-/**
- * @brief get the memory BIO method function
- */
-void *BIO_s_mem();
-
-/**
- * @brief free a BIO  object
- *
- * @param x - pointer to BIO object 
- */
-void BIO_free(BIO *b);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/tls1.h b/tools/sdk/include/openssl/internal/tls1.h
deleted file mode 100644
index a9da53e063e..00000000000
--- a/tools/sdk/include/openssl/internal/tls1.h
+++ /dev/null
@@ -1,55 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _TLS1_H_
-#define _TLS1_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-# define TLS1_AD_DECRYPTION_FAILED       21
-# define TLS1_AD_RECORD_OVERFLOW         22
-# define TLS1_AD_UNKNOWN_CA              48/* fatal */
-# define TLS1_AD_ACCESS_DENIED           49/* fatal */
-# define TLS1_AD_DECODE_ERROR            50/* fatal */
-# define TLS1_AD_DECRYPT_ERROR           51
-# define TLS1_AD_EXPORT_RESTRICTION      60/* fatal */
-# define TLS1_AD_PROTOCOL_VERSION        70/* fatal */
-# define TLS1_AD_INSUFFICIENT_SECURITY   71/* fatal */
-# define TLS1_AD_INTERNAL_ERROR          80/* fatal */
-# define TLS1_AD_INAPPROPRIATE_FALLBACK  86/* fatal */
-# define TLS1_AD_USER_CANCELLED          90
-# define TLS1_AD_NO_RENEGOTIATION        100
-/* codes 110-114 are from RFC3546 */
-# define TLS1_AD_UNSUPPORTED_EXTENSION   110
-# define TLS1_AD_CERTIFICATE_UNOBTAINABLE 111
-# define TLS1_AD_UNRECOGNIZED_NAME       112
-# define TLS1_AD_BAD_CERTIFICATE_STATUS_RESPONSE 113
-# define TLS1_AD_BAD_CERTIFICATE_HASH_VALUE 114
-# define TLS1_AD_UNKNOWN_PSK_IDENTITY    115/* fatal */
-# define TLS1_AD_NO_APPLICATION_PROTOCOL 120 /* fatal */
-
-/* Special value for method supporting multiple versions */
-#define TLS_ANY_VERSION                 0x10000
-
-#define TLS1_VERSION                    0x0301
-#define TLS1_1_VERSION                  0x0302
-#define TLS1_2_VERSION                  0x0303
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/internal/x509_vfy.h b/tools/sdk/include/openssl/internal/x509_vfy.h
deleted file mode 100644
index fec367d5fd8..00000000000
--- a/tools/sdk/include/openssl/internal/x509_vfy.h
+++ /dev/null
@@ -1,111 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _X509_VFY_H_
-#define _X509_VFY_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define         X509_V_OK                                       0
-#define         X509_V_ERR_UNSPECIFIED                          1
-#define         X509_V_ERR_UNABLE_TO_GET_ISSUER_CERT            2
-#define         X509_V_ERR_UNABLE_TO_GET_CRL                    3
-#define         X509_V_ERR_UNABLE_TO_DECRYPT_CERT_SIGNATURE     4
-#define         X509_V_ERR_UNABLE_TO_DECRYPT_CRL_SIGNATURE      5
-#define         X509_V_ERR_UNABLE_TO_DECODE_ISSUER_PUBLIC_KEY   6
-#define         X509_V_ERR_CERT_SIGNATURE_FAILURE               7
-#define         X509_V_ERR_CRL_SIGNATURE_FAILURE                8
-#define         X509_V_ERR_CERT_NOT_YET_VALID                   9
-#define         X509_V_ERR_CERT_HAS_EXPIRED                     10
-#define         X509_V_ERR_CRL_NOT_YET_VALID                    11
-#define         X509_V_ERR_CRL_HAS_EXPIRED                      12
-#define         X509_V_ERR_ERROR_IN_CERT_NOT_BEFORE_FIELD       13
-#define         X509_V_ERR_ERROR_IN_CERT_NOT_AFTER_FIELD        14
-#define         X509_V_ERR_ERROR_IN_CRL_LAST_UPDATE_FIELD       15
-#define         X509_V_ERR_ERROR_IN_CRL_NEXT_UPDATE_FIELD       16
-#define         X509_V_ERR_OUT_OF_MEM                           17
-#define         X509_V_ERR_DEPTH_ZERO_SELF_SIGNED_CERT          18
-#define         X509_V_ERR_SELF_SIGNED_CERT_IN_CHAIN            19
-#define         X509_V_ERR_UNABLE_TO_GET_ISSUER_CERT_LOCALLY    20
-#define         X509_V_ERR_UNABLE_TO_VERIFY_LEAF_SIGNATURE      21
-#define         X509_V_ERR_CERT_CHAIN_TOO_LONG                  22
-#define         X509_V_ERR_CERT_REVOKED                         23
-#define         X509_V_ERR_INVALID_CA                           24
-#define         X509_V_ERR_PATH_LENGTH_EXCEEDED                 25
-#define         X509_V_ERR_INVALID_PURPOSE                      26
-#define         X509_V_ERR_CERT_UNTRUSTED                       27
-#define         X509_V_ERR_CERT_REJECTED                        28
-/* These are 'informational' when looking for issuer cert */
-#define         X509_V_ERR_SUBJECT_ISSUER_MISMATCH              29
-#define         X509_V_ERR_AKID_SKID_MISMATCH                   30
-#define         X509_V_ERR_AKID_ISSUER_SERIAL_MISMATCH          31
-#define         X509_V_ERR_KEYUSAGE_NO_CERTSIGN                 32
-#define         X509_V_ERR_UNABLE_TO_GET_CRL_ISSUER             33
-#define         X509_V_ERR_UNHANDLED_CRITICAL_EXTENSION         34
-#define         X509_V_ERR_KEYUSAGE_NO_CRL_SIGN                 35
-#define         X509_V_ERR_UNHANDLED_CRITICAL_CRL_EXTENSION     36
-#define         X509_V_ERR_INVALID_NON_CA                       37
-#define         X509_V_ERR_PROXY_PATH_LENGTH_EXCEEDED           38
-#define         X509_V_ERR_KEYUSAGE_NO_DIGITAL_SIGNATURE        39
-#define         X509_V_ERR_PROXY_CERTIFICATES_NOT_ALLOWED       40
-#define         X509_V_ERR_INVALID_EXTENSION                    41
-#define         X509_V_ERR_INVALID_POLICY_EXTENSION             42
-#define         X509_V_ERR_NO_EXPLICIT_POLICY                   43
-#define         X509_V_ERR_DIFFERENT_CRL_SCOPE                  44
-#define         X509_V_ERR_UNSUPPORTED_EXTENSION_FEATURE        45
-#define         X509_V_ERR_UNNESTED_RESOURCE                    46
-#define         X509_V_ERR_PERMITTED_VIOLATION                  47
-#define         X509_V_ERR_EXCLUDED_VIOLATION                   48
-#define         X509_V_ERR_SUBTREE_MINMAX                       49
-/* The application is not happy */
-#define         X509_V_ERR_APPLICATION_VERIFICATION             50
-#define         X509_V_ERR_UNSUPPORTED_CONSTRAINT_TYPE          51
-#define         X509_V_ERR_UNSUPPORTED_CONSTRAINT_SYNTAX        52
-#define         X509_V_ERR_UNSUPPORTED_NAME_SYNTAX              53
-#define         X509_V_ERR_CRL_PATH_VALIDATION_ERROR            54
-/* Another issuer check debug option */
-#define         X509_V_ERR_PATH_LOOP                            55
-/* Suite B mode algorithm violation */
-#define         X509_V_ERR_SUITE_B_INVALID_VERSION              56
-#define         X509_V_ERR_SUITE_B_INVALID_ALGORITHM            57
-#define         X509_V_ERR_SUITE_B_INVALID_CURVE                58
-#define         X509_V_ERR_SUITE_B_INVALID_SIGNATURE_ALGORITHM  59
-#define         X509_V_ERR_SUITE_B_LOS_NOT_ALLOWED              60
-#define         X509_V_ERR_SUITE_B_CANNOT_SIGN_P_384_WITH_P_256 61
-/* Host, email and IP check errors */
-#define         X509_V_ERR_HOSTNAME_MISMATCH                    62
-#define         X509_V_ERR_EMAIL_MISMATCH                       63
-#define         X509_V_ERR_IP_ADDRESS_MISMATCH                  64
-/* DANE TLSA errors */
-#define         X509_V_ERR_DANE_NO_MATCH                        65
-/* security level errors */
-#define         X509_V_ERR_EE_KEY_TOO_SMALL                     66
-#define         X509_V_ERR_CA_KEY_TOO_SMALL                     67
-#define         X509_V_ERR_CA_MD_TOO_WEAK                       68
-/* Caller error */
-#define         X509_V_ERR_INVALID_CALL                         69
-/* Issuer lookup error */
-#define         X509_V_ERR_STORE_LOOKUP                         70
-/* Certificate transparency */
-#define         X509_V_ERR_NO_VALID_SCTS                        71
-
-#define         X509_V_ERR_PROXY_SUBJECT_NAME_VIOLATION         72
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/openssl/ssl.h b/tools/sdk/include/openssl/openssl/ssl.h
deleted file mode 100644
index 88d7bca69dc..00000000000
--- a/tools/sdk/include/openssl/openssl/ssl.h
+++ /dev/null
@@ -1,1822 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_H_
-#define _SSL_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "internal/ssl_x509.h"
-#include "internal/ssl_pkey.h"
-
-/*
-{
-*/
-
-#define SSL_CB_ALERT 0x4000
-
-#define X509_CHECK_FLAG_ALWAYS_CHECK_SUBJECT		(1 << 0)
-#define X509_CHECK_FLAG_NO_WILDCARDS			(1 << 1)
-#define X509_CHECK_FLAG_NO_PARTIAL_WILDCARDS		(1 << 2)
-#define X509_CHECK_FLAG_MULTI_LABEL_WILDCARDS		(1 << 3)
-#define X509_CHECK_FLAG_SINGLE_LABEL_SUBDOMAINS		(1 << 4)
-
-/**
- * @brief create a SSL context
- *
- * @param method - the SSL context method point
- *
- * @return the context point
- */
-SSL_CTX* SSL_CTX_new(const SSL_METHOD *method);
-
-/**
- * @brief free a SSL context
- *
- * @param method - the SSL context point
- *
- * @return none
- */
-void SSL_CTX_free(SSL_CTX *ctx);
-
-/**
- * @brief create a SSL
- *
- * @param ctx - the SSL context point
- *
- * @return the SSL point
- */
-SSL* SSL_new(SSL_CTX *ctx);
-
-/**
- * @brief free the SSL
- *
- * @param ssl - the SSL point
- *
- * @return none
- */
-void SSL_free(SSL *ssl);
-
-/**
- * @brief connect to the remote SSL server
- *
- * @param ssl - the SSL point
- *
- * @return result
- *     1 : OK
- *    -1 : failed
- */
-int SSL_connect(SSL *ssl);
-
-/**
- * @brief accept the remote connection
- *
- * @param ssl - the SSL point
- *
- * @return result
- *     1 : OK
- *    -1 : failed
- */
-int SSL_accept(SSL *ssl);
-
-/**
- * @brief read data from to remote
- *
- * @param ssl    - the SSL point which has been connected
- * @param buffer - the received data buffer point
- * @param len    - the received data length
- *
- * @return result
- *     > 0 : OK, and return received data bytes
- *     = 0 : connection is closed
- *     < 0 : an error catch
- */
-int SSL_read(SSL *ssl, void *buffer, int len);
-
-/**
- * @brief send the data to remote
- *
- * @param ssl    - the SSL point which has been connected
- * @param buffer - the send data buffer point
- * @param len    - the send data length
- *
- * @return result
- *     > 0 : OK, and return sent data bytes
- *     = 0 : connection is closed
- *     < 0 : an error catch
- */
-int SSL_write(SSL *ssl, const void *buffer, int len);
-
-/**
- * @brief get the verifying result of the SSL certification
- *
- * @param ssl - the SSL point
- *
- * @return the result of verifying
- */
-long SSL_get_verify_result(const SSL *ssl);
-
-/**
- * @brief shutdown the connection
- *
- * @param ssl - the SSL point
- *
- * @return result
- *     1 : OK
- *     0 : shutdown is not finished
- *    -1 : an error catch
- */
-int SSL_shutdown(SSL *ssl);
-
-/**
- * @brief bind the socket file description into the SSL
- *
- * @param ssl - the SSL point
- * @param fd  - socket handle
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_set_fd(SSL *ssl, int fd);
-
-/**
- * @brief Set the hostname for SNI
- *
- * @param ssl - the SSL context point
- * @param hostname  - pointer to the hostname
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_set_tlsext_host_name(SSL* ssl, const char *hostname);
-
-/**
- * @brief These functions load the private key into the SSL_CTX or SSL object
- *
- * @param ctx  - the SSL context point
- * @param pkey - private key object point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_PrivateKey(SSL_CTX *ctx, EVP_PKEY *pkey);
-
-/**
- * @brief These functions load the certification into the SSL_CTX or SSL object
- *
- * @param ctx  - the SSL context point
- * @param pkey - certification object point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_certificate(SSL_CTX *ctx, X509 *x);
-
-/**
- * @brief create the target SSL context client method
- *
- * @param none
- *
- * @return the SSLV2.3 version SSL context client method
- */
-const SSL_METHOD* SSLv23_client_method(void);
-
-/**
- * @brief create the target SSL context client method
- *
- * @param none
- *
- * @return the TLSV1.0 version SSL context client method
- */
-const SSL_METHOD* TLSv1_client_method(void);
-
-/**
- * @brief create the target SSL context client method
- *
- * @param none
- *
- * @return the SSLV1.0 version SSL context client method
- */
-const SSL_METHOD* SSLv3_client_method(void);
-
-/**
- * @brief create the target SSL context client method
- *
- * @param none
- *
- * @return the TLSV1.1 version SSL context client method
- */
-const SSL_METHOD* TLSv1_1_client_method(void);
-
-/**
- * @brief create the target SSL context client method
- *
- * @param none
- *
- * @return the TLSV1.2 version SSL context client method
- */
-const SSL_METHOD* TLSv1_2_client_method(void);
-
-/**
- * @brief create the target SSL context server method
- *
- * @param none
- *
- * @return the TLS any version SSL context client method
- */
-const SSL_METHOD* TLS_client_method(void);
-
-/**
- * @brief create the target SSL context server method
- *
- * @param none
- *
- * @return the SSLV2.3 version SSL context server method
- */
-const SSL_METHOD* SSLv23_server_method(void);
-
-/**
- * @brief create the target SSL context server method
- *
- * @param none
- *
- * @return the TLSV1.1 version SSL context server method
- */
-const SSL_METHOD* TLSv1_1_server_method(void);
-
-/**
- * @brief create the target SSL context server method
- *
- * @param none
- *
- * @return the TLSV1.2 version SSL context server method
- */
-const SSL_METHOD* TLSv1_2_server_method(void);
-
-/**
- * @brief create the target SSL context server method
- *
- * @param none
- *
- * @return the TLSV1.0 version SSL context server method
- */
-const SSL_METHOD* TLSv1_server_method(void);
-
-/**
- * @brief create the target SSL context server method
- *
- * @param none
- *
- * @return the SSLV3.0 version SSL context server method
- */
-const SSL_METHOD* SSLv3_server_method(void);
-
-/**
- * @brief create the target SSL context server method
- *
- * @param none
- *
- * @return the TLS any version SSL context server method
- */
-const SSL_METHOD* TLS_server_method(void);
-
-
-/**
- * @brief set the SSL context ALPN select callback function
- *
- * @param ctx - SSL context point
- * @param cb  - ALPN select callback function
- * @param arg - ALPN select callback function entry private data point
- *
- * @return none
- */
-void SSL_CTX_set_alpn_select_cb(SSL_CTX *ctx,
-                                int (*cb) (SSL *ssl,
-                                           const unsigned char **out,
-                                           unsigned char *outlen,
-                                           const unsigned char *in,
-                                           unsigned int inlen,
-                                           void *arg),
-                                void *arg);
-
-
-/**
- * @brief set the SSL context ALPN select protocol
- *
- * @param ctx        - SSL context point
- * @param protos     - ALPN protocol name
- * @param protos_len - ALPN protocol name bytes
- *
- * @return result
- *     0 : OK
- *     1 : failed
- */
-int SSL_CTX_set_alpn_protos(SSL_CTX *ctx, const unsigned char *protos, unsigned int protos_len);
-
-/**
- * @brief set the SSL context next ALPN select callback function
- *
- * @param ctx - SSL context point
- * @param cb  - ALPN select callback function
- * @param arg - ALPN select callback function entry private data point
- *
- * @return none
- */
-void SSL_CTX_set_next_proto_select_cb(SSL_CTX *ctx,
-                                      int (*cb) (SSL *ssl,
-                                                 unsigned char **out,
-                                                 unsigned char *outlen,
-                                                 const unsigned char *in,
-                                                 unsigned int inlen,
-                                                 void *arg),
-                                      void *arg);
-
-/**
- * @brief get SSL error code
- *
- * @param ssl       - SSL point
- * @param ret_code  - SSL return code
- *
- * @return SSL error number
- */
-int SSL_get_error(const SSL *ssl, int ret_code);
-
-/**
- * @brief clear the SSL error code
- *
- * @param none
- *
- * @return none
- */
-void ERR_clear_error(void);
-
-/**
- * @brief get the current SSL error code
- *
- * @param none
- *
- * @return current SSL error number
- */
-int ERR_get_error(void);
-
-/**
- * @brief register the SSL error strings
- *
- * @param none
- *
- * @return none
- */
-void ERR_load_SSL_strings(void);
-
-/**
- * @brief initialize the SSL library
- *
- * @param none
- *
- * @return none
- */
-void SSL_library_init(void);
-
-/**
- * @brief generates a human-readable string representing the error code e
- *        and store it into the "ret" point memory
- *
- * @param e   - error code
- * @param ret - memory point to store the string
- *
- * @return the result string point
- */
-char *ERR_error_string(unsigned long e, char *ret);
-
-/**
- * @brief add the SSL context option
- *
- * @param ctx - SSL context point
- * @param opt - new SSL context option
- *
- * @return the SSL context option
- */
-unsigned long SSL_CTX_set_options(SSL_CTX *ctx, unsigned long opt);
-
-/**
- * @brief add the SSL context mode
- *
- * @param ctx - SSL context point
- * @param mod - new SSL context mod
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_set_mode(SSL_CTX *ctx, int mod);
-
-/*
-}
-*/
-
-/**
- * @brief perform the SSL handshake
- *
- * @param ssl - SSL point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- *    -1 : a error catch
- */
-int SSL_do_handshake(SSL *ssl);
-
-/**
- * @brief get the SSL current version
- *
- * @param ssl - SSL point
- *
- * @return the version string
- */
-const char *SSL_get_version(const SSL *ssl);
-
-/**
- * @brief set  the SSL context version
- *
- * @param ctx  - SSL context point
- * @param meth - SSL method point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_set_ssl_version(SSL_CTX *ctx, const SSL_METHOD *meth);
-
-/**
- * @brief get the bytes numbers which are to be read
- *
- * @param ssl  - SSL point
- *
- * @return bytes number
- */
-int SSL_pending(const SSL *ssl);
-
-/**
- * @brief check if SSL want nothing
- *
- * @param ssl - SSL point
- *
- * @return result
- *     0 : false
- *     1 : true
- */
-int SSL_want_nothing(const SSL *ssl);
-
-/**
- * @brief check if SSL want to read
- *
- * @param ssl - SSL point
- *
- * @return result
- *     0 : false
- *     1 : true
- */
-int SSL_want_read(const SSL *ssl);
-
-/**
- * @brief check if SSL want to write
- *
- * @param ssl - SSL point
- *
- * @return result
- *     0 : false
- *     1 : true
- */
-int SSL_want_write(const SSL *ssl);
-
-/**
- * @brief get the SSL context current method
- *
- * @param ctx - SSL context point
- *
- * @return the SSL context current method
- */
-const SSL_METHOD *SSL_CTX_get_ssl_method(SSL_CTX *ctx);
-
-/**
- * @brief get the SSL current method
- *
- * @param ssl - SSL point
- *
- * @return the SSL current method
- */
-const SSL_METHOD *SSL_get_ssl_method(SSL *ssl);
-
-/**
- * @brief set the SSL method
- *
- * @param ssl  - SSL point
- * @param meth - SSL method point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_set_ssl_method(SSL *ssl, const SSL_METHOD *method);
-
-/**
- * @brief add CA client certification into the SSL
- *
- * @param ssl - SSL point
- * @param x   - CA certification point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_add_client_CA(SSL *ssl, X509 *x);
-
-/**
- * @brief add CA client certification into the SSL context
- *
- * @param ctx - SSL context point
- * @param x   - CA certification point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_add_client_CA(SSL_CTX *ctx, X509 *x);
-
-/**
- * @brief set the SSL CA certification list
- *
- * @param ssl       - SSL point
- * @param name_list - CA certification list
- *
- * @return none
- */
-void SSL_set_client_CA_list(SSL *ssl, STACK_OF(X509_NAME) *name_list);
-
-/**
- * @brief set the SSL context CA certification list
- *
- * @param ctx       - SSL context point
- * @param name_list - CA certification list
- *
- * @return none
- */
-void SSL_CTX_set_client_CA_list(SSL_CTX *ctx, STACK_OF(X509_NAME) *name_list);
-
-/**
- * @briefget the SSL CA certification list
- *
- * @param ssl - SSL point
- *
- * @return CA certification list
- */
-STACK_OF(X509_NAME) *SSL_get_client_CA_list(const SSL *ssl);
-
-/**
- * @brief get the SSL context CA certification list
- *
- * @param ctx - SSL context point
- *
- * @return CA certification list
- */
-STACK_OF(X509_NAME) *SSL_CTX_get_client_CA_list(const SSL_CTX *ctx);
-
-/**
- * @brief get the SSL certification point
- *
- * @param ssl - SSL point
- *
- * @return SSL certification point
- */
-X509 *SSL_get_certificate(const SSL *ssl);
-
-/**
- * @brief get the SSL private key point
- *
- * @param ssl - SSL point
- *
- * @return SSL private key point
- */
-EVP_PKEY *SSL_get_privatekey(const SSL *ssl);
-
-/**
- * @brief set the SSL information callback function
- *
- * @param ssl - SSL point
- * @param cb  - information callback function
- *
- * @return none
- */
-void SSL_set_info_callback(SSL *ssl, void (*cb) (const SSL *ssl, int type, int val));
-
-/**
- * @brief get the SSL state
- *
- * @param ssl - SSL point
- *
- * @return SSL state
- */
-OSSL_HANDSHAKE_STATE SSL_get_state(const SSL *ssl);
-
-/**
- * @brief set the SSL context read buffer length
- *
- * @param ctx - SSL context point
- * @param len - read buffer length
- *
- * @return none
- */
-void SSL_CTX_set_default_read_buffer_len(SSL_CTX *ctx, size_t len);
-
-/**
- * @brief set the SSL read buffer length
- *
- * @param ssl - SSL point
- * @param len - read buffer length
- *
- * @return none
- */
-void SSL_set_default_read_buffer_len(SSL *ssl, size_t len);
-
-/**
- * @brief set the SSL security level
- *
- * @param ssl   - SSL point
- * @param level - security level
- *
- * @return none
- */
-void SSL_set_security_level(SSL *ssl, int level);
-
-/**
- * @brief get the SSL security level
- *
- * @param ssl - SSL point
- *
- * @return security level
- */
-int SSL_get_security_level(const SSL *ssl);
-
-/**
- * @brief get the SSL verifying mode of the SSL context
- *
- * @param ctx - SSL context point
- *
- * @return verifying mode
- */
-int SSL_CTX_get_verify_mode(const SSL_CTX *ctx);
-
-/**
- * @brief get the SSL verifying depth of the SSL context
- *
- * @param ctx - SSL context point
- *
- * @return verifying depth
- */
-int SSL_CTX_get_verify_depth(const SSL_CTX *ctx);
-
-/**
- * @brief set the SSL context verifying of the SSL context
- *
- * @param ctx             - SSL context point
- * @param mode            - verifying mode
- * @param verify_callback - verifying callback function
- *
- * @return none
- */
-void SSL_CTX_set_verify(SSL_CTX *ctx, int mode, int (*verify_callback)(int, X509_STORE_CTX *));
-
-/**
- * @brief set the SSL verifying of the SSL context
- *
- * @param ctx             - SSL point
- * @param mode            - verifying mode
- * @param verify_callback - verifying callback function
- *
- * @return none
- */
-void SSL_set_verify(SSL *s, int mode, int (*verify_callback)(int, X509_STORE_CTX *));
-
-/**
- * @brief set the SSL verify depth of the SSL context
- *
- * @param ctx   - SSL context point
- * @param depth - verifying depth
- *
- * @return none
- */
-void SSL_CTX_set_verify_depth(SSL_CTX *ctx, int depth);
-
-/**
- * @brief certification verifying callback function
- *
- * @param preverify_ok - verifying result
- * @param x509_ctx     - X509 certification point
- *
- * @return verifying result
- */
-int verify_callback(int preverify_ok, X509_STORE_CTX *x509_ctx);
-
-/**
- * @brief set the session timeout time
- *
- * @param ctx - SSL context point
- * @param t   - new session timeout time
- *
- * @return old session timeout time
- */
-long SSL_CTX_set_timeout(SSL_CTX *ctx, long t);
-
-/**
- * @brief get the session timeout time
- *
- * @param ctx - SSL context point
- *
- * @return current session timeout time
- */
-long SSL_CTX_get_timeout(const SSL_CTX *ctx);
-
-/**
- * @brief set the SSL context cipher through the list string
- *
- * @param ctx - SSL context point
- * @param str - cipher controller list string
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_set_cipher_list(SSL_CTX *ctx, const char *str);
-
-/**
- * @brief set the SSL cipher through the list string
- *
- * @param ssl - SSL point
- * @param str - cipher controller list string
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_set_cipher_list(SSL *ssl, const char *str);
-
-/**
- * @brief get the SSL cipher list string
- *
- * @param ssl - SSL point
- *
- * @return cipher controller list string
- */
-const char *SSL_get_cipher_list(const SSL *ssl, int n);
-
-/**
- * @brief get the SSL cipher
- *
- * @param ssl - SSL point
- *
- * @return current cipher
- */
-const SSL_CIPHER *SSL_get_current_cipher(const SSL *ssl);
-
-/**
- * @brief get the SSL cipher string
- *
- * @param ssl - SSL point
- *
- * @return cipher string
- */
-const char *SSL_get_cipher(const SSL *ssl);
-
-/**
- * @brief get the SSL context object X509 certification storage
- *
- * @param ctx - SSL context point
- *
- * @return x509 certification storage
- */
-X509_STORE *SSL_CTX_get_cert_store(const SSL_CTX *ctx);
-
-/**
- * @brief set the SSL context object X509 certification store
- *
- * @param ctx   - SSL context point
- * @param store - X509 certification store
- *
- * @return none
- */
-void SSL_CTX_set_cert_store(SSL_CTX *ctx, X509_STORE *store);
-
-/**
- * @brief get the SSL specifical statement
- *
- * @param ssl - SSL point
- *
- * @return specifical statement
- */
-int SSL_want(const SSL *ssl);
-
-/**
- * @brief check if the SSL is SSL_X509_LOOKUP state
- *
- * @param ssl - SSL point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_want_x509_lookup(const SSL *ssl);
-
-/**
- * @brief reset the SSL
- *
- * @param ssl - SSL point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_clear(SSL *ssl);
-
-/**
- * @brief get the socket handle of the SSL
- *
- * @param ssl - SSL point
- *
- * @return result
- *     >= 0 : yes, and return socket handle
- *      < 0 : a error catch
- */
-int SSL_get_fd(const SSL *ssl);
-
-/**
- * @brief get the read only socket handle of the SSL
- *
- * @param ssl - SSL point
- *
- * @return result
- *     >= 0 : yes, and return socket handle
- *      < 0 : a error catch
- */
-int SSL_get_rfd(const SSL *ssl);
-
-/**
- * @brief get the write only socket handle of the SSL
- *
- * @param ssl - SSL point
- *
- * @return result
- *     >= 0 : yes, and return socket handle
- *      < 0 : a error catch
- */
-int SSL_get_wfd(const SSL *ssl);
-
-/**
- * @brief set the SSL if we can read as many as data
- *
- * @param ssl - SSL point
- * @param yes - enable the function
- *
- * @return none
- */
-void SSL_set_read_ahead(SSL *s, int yes);
-
-/**
- * @brief set the SSL context if we can read as many as data
- *
- * @param ctx - SSL context point
- * @param yes - enbale the function
- *
- * @return none
- */
-void SSL_CTX_set_read_ahead(SSL_CTX *ctx, int yes);
-
-/**
- * @brief get the SSL ahead signal if we can read as many as data
- *
- * @param ssl - SSL point
- *
- * @return SSL context ahead signal
- */
-int SSL_get_read_ahead(const SSL *ssl);
-
-/**
- * @brief get the SSL context ahead signal if we can read as many as data
- *
- * @param ctx - SSL context point
- *
- * @return SSL context ahead signal
- */
-long SSL_CTX_get_read_ahead(SSL_CTX *ctx);
-
-/**
- * @brief check if some data can be read
- *
- * @param ssl - SSL point
- *
- * @return
- *         1 : there are bytes to be read
- *         0 : no data
- */
-int SSL_has_pending(const SSL *ssl);
-
-/**
- * @brief load the X509 certification into SSL context
- *
- * @param ctx - SSL context point
- * @param x   - X509 certification point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_certificate(SSL_CTX *ctx, X509 *x);//loads the certificate x into ctx
-
-/**
- * @brief load the ASN1 certification into SSL context
- *
- * @param ctx - SSL context point
- * @param len - certification length
- * @param d   - data point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_certificate_ASN1(SSL_CTX *ctx, int len, const unsigned char *d);
-
-/**
- * @brief load the certification file into SSL context
- *
- * @param ctx  - SSL context point
- * @param file - certification file name
- * @param type - certification encoding type
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_certificate_file(SSL_CTX *ctx, const char *file, int type);
-
-/**
- * @brief load the certification chain file into SSL context
- *
- * @param ctx  - SSL context point
- * @param file - certification chain file name
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_certificate_chain_file(SSL_CTX *ctx, const char *file);
-
-
-/**
- * @brief load the ASN1 private key into SSL context
- *
- * @param ctx - SSL context point
- * @param d   - data point
- * @param len - private key length
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_PrivateKey_ASN1(int pk, SSL_CTX *ctx, const unsigned char *d,  long len);//adds the private key of type pk stored at memory location d (length len) to ctx
-
-/**
- * @brief load the private key file into SSL context
- *
- * @param ctx  - SSL context point
- * @param file - private key file name
- * @param type - private key encoding type
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_PrivateKey_file(SSL_CTX *ctx, const char *file, int type);
-
-/**
- * @brief load the RSA private key into SSL context
- *
- * @param ctx - SSL context point
- * @param x   - RSA private key point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_RSAPrivateKey(SSL_CTX *ctx, RSA *rsa);
-
-/**
- * @brief load the RSA ASN1 private key into SSL context
- *
- * @param ctx - SSL context point
- * @param d   - data point
- * @param len - RSA private key length
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_RSAPrivateKey_ASN1(SSL_CTX *ctx, const unsigned char *d, long len);
-
-/**
- * @brief load the RSA private key file into SSL context
- *
- * @param ctx  - SSL context point
- * @param file - RSA private key file name
- * @param type - private key encoding type
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_RSAPrivateKey_file(SSL_CTX *ctx, const char *file, int type);
-
-
-/**
- * @brief check if the private key and certification is matched
- *
- * @param ctx  - SSL context point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_check_private_key(const SSL_CTX *ctx);
-
-/**
- * @brief set the SSL context server information
- *
- * @param ctx               - SSL context point
- * @param serverinfo        - server information string
- * @param serverinfo_length - server information length
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_serverinfo(SSL_CTX *ctx, const unsigned char *serverinfo, size_t serverinfo_length);
-
-/**
- * @brief load  the SSL context server infomation file into SSL context
- *
- * @param ctx  - SSL context point
- * @param file - server information file
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_serverinfo_file(SSL_CTX *ctx, const char *file);
-
-/**
- * @brief SSL select next function
- *
- * @param out        - point of output data point
- * @param outlen     - output data length
- * @param in         - input data
- * @param inlen      - input data length
- * @param client     - client data point
- * @param client_len -client data length
- *
- * @return NPN state
- *         OPENSSL_NPN_UNSUPPORTED : not support
- *         OPENSSL_NPN_NEGOTIATED  : negotiated
- *         OPENSSL_NPN_NO_OVERLAP  : no overlap
- */
-int SSL_select_next_proto(unsigned char **out, unsigned char *outlen,
-                          const unsigned char *in, unsigned int inlen,
-                          const unsigned char *client, unsigned int client_len);
-
-/**
- * @brief load the extra certification chain into the SSL context
- *
- * @param ctx  - SSL context point
- * @param x509 - X509 certification
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-long SSL_CTX_add_extra_chain_cert(SSL_CTX *ctx, X509 *);
-
-/**
- * @brief control the SSL context
- *
- * @param ctx  - SSL context point
- * @param cmd  - command
- * @param larg - parameter length
- * @param parg - parameter point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-long SSL_CTX_ctrl(SSL_CTX *ctx, int cmd, long larg, char *parg);
-
-/**
- * @brief get the SSL context cipher
- *
- * @param ctx - SSL context point
- *
- * @return SSL context cipher
- */
-STACK *SSL_CTX_get_ciphers(const SSL_CTX *ctx);
-
-/**
- * @brief check if the SSL context can read as many as data
- *
- * @param ctx - SSL context point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-long SSL_CTX_get_default_read_ahead(SSL_CTX *ctx);
-
-/**
- * @brief get the SSL context extra data
- *
- * @param ctx - SSL context point
- * @param idx - index
- *
- * @return data point
- */
-char *SSL_CTX_get_ex_data(const SSL_CTX *ctx, int idx);
-
-/**
- * @brief get the SSL context quiet shutdown option
- *
- * @param ctx - SSL context point
- *
- * @return quiet shutdown option
- */
-int SSL_CTX_get_quiet_shutdown(const SSL_CTX *ctx);
-
-/**
- * @brief load the SSL context CA file
- *
- * @param ctx    - SSL context point
- * @param CAfile - CA certification file
- * @param CApath - CA certification file path
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_load_verify_locations(SSL_CTX *ctx, const char *CAfile, const char *CApath);
-
-/**
- * @brief add SSL context reference count by '1'
- *
- * @param ctx - SSL context point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_up_ref(SSL_CTX *ctx);
-
-/**
- * @brief set SSL context application private data
- *
- * @param ctx - SSL context point
- * @param arg - private data
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_set_app_data(SSL_CTX *ctx, void *arg);
-
-/**
- * @brief set SSL context client certification callback function
- *
- * @param ctx - SSL context point
- * @param cb  - callback function
- *
- * @return none
- */
-void SSL_CTX_set_client_cert_cb(SSL_CTX *ctx, int (*cb)(SSL *ssl, X509 **x509, EVP_PKEY **pkey));
-
-/**
- * @brief set the SSL context if we can read as many as data
- *
- * @param ctx - SSL context point
- * @param m   - enable the fuction
- *
- * @return none
- */
-void SSL_CTX_set_default_read_ahead(SSL_CTX *ctx, int m);
-
-/**
- * @brief set SSL context default verifying path
- *
- * @param ctx - SSL context point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_set_default_verify_paths(SSL_CTX *ctx);
-
-/**
- * @brief set SSL context default verifying directory
- *
- * @param ctx - SSL context point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_set_default_verify_dir(SSL_CTX *ctx);
-
-/**
- * @brief set SSL context default verifying file
- *
- * @param ctx - SSL context point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_set_default_verify_file(SSL_CTX *ctx);
-
-/**
- * @brief set SSL context extra data
- *
- * @param ctx - SSL context point
- * @param idx - data index
- * @param arg - data point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_set_ex_data(SSL_CTX *s, int idx, char *arg);
-
-/**
- * @brief clear the SSL context option bit of "op"
- *
- * @param ctx - SSL context point
- * @param op  - option
- *
- * @return SSL context option
- */
-unsigned long SSL_CTX_clear_options(SSL_CTX *ctx, unsigned long op);
-
-/**
- * @brief get the SSL context option
- *
- * @param ctx - SSL context point
- * @param op  - option
- *
- * @return SSL context option
- */
-unsigned long SSL_CTX_get_options(SSL_CTX *ctx);
-
-/**
- * @brief set the SSL context quiet shutdown mode
- *
- * @param ctx  - SSL context point
- * @param mode - mode
- *
- * @return none
- */
-void SSL_CTX_set_quiet_shutdown(SSL_CTX *ctx, int mode);
-
-/**
- * @brief get the SSL context X509 certification
- *
- * @param ctx - SSL context point
- *
- * @return X509 certification
- */
-X509 *SSL_CTX_get0_certificate(const SSL_CTX *ctx);
-
-/**
- * @brief get the SSL context private key
- *
- * @param ctx - SSL context point
- *
- * @return private key
- */
-EVP_PKEY *SSL_CTX_get0_privatekey(const SSL_CTX *ctx);
-
-/**
- * @brief set SSL context PSK identity hint
- *
- * @param ctx  - SSL context point
- * @param hint - PSK identity hint
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_CTX_use_psk_identity_hint(SSL_CTX *ctx, const char *hint);
-
-/**
- * @brief set SSL context PSK server callback function
- *
- * @param ctx      - SSL context point
- * @param callback - callback function
- *
- * @return none
- */
-void SSL_CTX_set_psk_server_callback(SSL_CTX *ctx,
-                                     unsigned int (*callback)(SSL *ssl,
-                                                              const char *identity,
-                                                              unsigned char *psk,
-                                                              int max_psk_len));
-/**
- * @brief get alert description string
- *
- * @param value - alert value
- *
- * @return alert description string
- */
-const char *SSL_alert_desc_string(int value);
-
-/**
- * @brief get alert description long string
- *
- * @param value - alert value
- *
- * @return alert description long string
- */
-const char *SSL_alert_desc_string_long(int value);
-
-/**
- * @brief get alert type string
- *
- * @param value - alert value
- *
- * @return alert type string
- */
-const char *SSL_alert_type_string(int value);
-
-/**
- * @brief get alert type long string
- *
- * @param value - alert value
- *
- * @return alert type long string
- */
-const char *SSL_alert_type_string_long(int value);
-
-/**
- * @brief get SSL context of the SSL
- *
- * @param ssl - SSL point
- *
- * @return SSL context
- */
-SSL_CTX *SSL_get_SSL_CTX(const SSL *ssl);
-
-/**
- * @brief get SSL application data
- *
- * @param ssl - SSL point
- *
- * @return application data
- */
-char *SSL_get_app_data(SSL *ssl);
-
-/**
- * @brief get SSL cipher bits
- *
- * @param ssl - SSL point
- * @param alg_bits - algorithm bits
- *
- * @return strength bits
- */
-int SSL_get_cipher_bits(const SSL *ssl, int *alg_bits);
-
-/**
- * @brief get SSL cipher name
- *
- * @param ssl - SSL point
- *
- * @return SSL cipher name
- */
-char *SSL_get_cipher_name(const SSL *ssl);
-
-/**
- * @brief get SSL cipher version
- *
- * @param ssl - SSL point
- *
- * @return SSL cipher version
- */
-char *SSL_get_cipher_version(const SSL *ssl);
-
-/**
- * @brief get SSL extra data
- *
- * @param ssl - SSL point
- * @param idx - data index
- *
- * @return extra data
- */
-char *SSL_get_ex_data(const SSL *ssl, int idx);
-
-/**
- * @brief get index of the SSL extra data X509 storage context
- *
- * @param none
- *
- * @return data index
- */
-int SSL_get_ex_data_X509_STORE_CTX_idx(void);
-
-/**
- * @brief get peer certification chain
- *
- * @param ssl - SSL point
- *
- * @return certification chain
- */
-STACK *SSL_get_peer_cert_chain(const SSL *ssl);
-
-/**
- * @brief get peer certification
- *
- * @param ssl - SSL point
- *
- * @return certification
- */
-X509 *SSL_get_peer_certificate(const SSL *ssl);
-
-/**
- * @brief get SSL quiet shutdown mode
- *
- * @param ssl - SSL point
- *
- * @return quiet shutdown mode
- */
-int SSL_get_quiet_shutdown(const SSL *ssl);
-
-/**
- * @brief get SSL read only IO handle
- *
- * @param ssl - SSL point
- *
- * @return IO handle
- */
-BIO *SSL_get_rbio(const SSL *ssl);
-
-/**
- * @brief get SSL shared ciphers
- *
- * @param ssl - SSL point
- * @param buf - buffer to store the ciphers
- * @param len - buffer len
- *
- * @return shared ciphers
- */
-char *SSL_get_shared_ciphers(const SSL *ssl, char *buf, int len);
-
-/**
- * @brief get SSL shutdown mode
- *
- * @param ssl - SSL point
- *
- * @return shutdown mode
- */
-int SSL_get_shutdown(const SSL *ssl);
-
-/**
- * @brief get SSL session time
- *
- * @param ssl - SSL point
- *
- * @return session time
- */
-long SSL_get_time(const SSL *ssl);
-
-/**
- * @brief get SSL session timeout time
- *
- * @param ssl - SSL point
- *
- * @return session timeout time
- */
-long SSL_get_timeout(const SSL *ssl);
-
-/**
- * @brief get SSL verifying mode
- *
- * @param ssl - SSL point
- *
- * @return verifying mode
- */
-int SSL_get_verify_mode(const SSL *ssl);
-
-/**
- * @brief get SSL verify parameters
- *
- * @param ssl - SSL point
- *
- * @return verify parameters
- */
-X509_VERIFY_PARAM *SSL_get0_param(SSL *ssl);
-
-/**
- * @brief set expected hostname the peer cert CN should have
- *
- * @param param - verify parameters from SSL_get0_param()
- *
- * @param name - the expected hostname
- *
- * @param namelen - the length of the hostname, or 0 if NUL terminated
- *
- * @return verify parameters
- */
-int X509_VERIFY_PARAM_set1_host(X509_VERIFY_PARAM *param,
-                                const char *name, size_t namelen);
-
-/**
- * @brief set parameters for X509 host verify action
- *
- * @param param -verify parameters from SSL_get0_param()
- *
- * @param flags - bitfield of X509_CHECK_FLAG_... parameters to set
- *
- * @return 1 for success, 0 for failure
- */
-int X509_VERIFY_PARAM_set_hostflags(X509_VERIFY_PARAM *param,
-                    unsigned long flags);
-
-/**
- * @brief clear parameters for X509 host verify action
- *
- * @param param -verify parameters from SSL_get0_param()
- *
- * @param flags - bitfield of X509_CHECK_FLAG_... parameters to clear
- *
- * @return 1 for success, 0 for failure
- */
-int X509_VERIFY_PARAM_clear_hostflags(X509_VERIFY_PARAM *param,
-                      unsigned long flags);
-
-/**
- * @brief get SSL write only IO handle
- *
- * @param ssl - SSL point
- *
- * @return IO handle
- */
-BIO *SSL_get_wbio(const SSL *ssl);
-
-/**
- * @brief load SSL client CA certification file
- *
- * @param file - file name
- *
- * @return certification loading object
- */
-STACK *SSL_load_client_CA_file(const char *file);
-
-/**
- * @brief add SSL reference by '1'
- *
- * @param ssl - SSL point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_up_ref(SSL *ssl);
-
-/**
- * @brief read and put data into buf, but not clear the SSL low-level storage
- *
- * @param ssl - SSL point
- * @param buf - storage buffer point
- * @param num - data bytes
- *
- * @return result
- *     > 0 : OK, and return read bytes
- *     = 0 : connect is closed
- *     < 0 : a error catch
- */
-int SSL_peek(SSL *ssl, void *buf, int num);
-
-/**
- * @brief make SSL renegotiate
- *
- * @param ssl - SSL point
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_renegotiate(SSL *ssl);
-
-/**
- * @brief get the state string where SSL is reading
- *
- * @param ssl - SSL point
- *
- * @return state string
- */
-const char *SSL_rstate_string(SSL *ssl);
-
-/**
- * @brief get the statement long string where SSL is reading
- *
- * @param ssl - SSL point
- *
- * @return statement long string
- */
-const char *SSL_rstate_string_long(SSL *ssl);
-
-/**
- * @brief set SSL accept statement
- *
- * @param ssl - SSL point
- *
- * @return none
- */
-void SSL_set_accept_state(SSL *ssl);
-
-/**
- * @brief set SSL application data
- *
- * @param ssl - SSL point
- * @param arg - SSL application data point
- *
- * @return none
- */
-void SSL_set_app_data(SSL *ssl, char *arg);
-
-/**
- * @brief set SSL BIO
- *
- * @param ssl  - SSL point
- * @param rbio - read only IO
- * @param wbio - write only IO
- *
- * @return none
- */
-void SSL_set_bio(SSL *ssl, BIO *rbio, BIO *wbio);
-
-/**
- * @brief clear SSL option
- *
- * @param ssl - SSL point
- * @param op  - clear option
- *
- * @return SSL option
- */
-unsigned long SSL_clear_options(SSL *ssl, unsigned long op);
-
-/**
- * @brief get SSL option
- *
- * @param ssl - SSL point
- *
- * @return SSL option
- */
-unsigned long SSL_get_options(SSL *ssl);
-
-/**
- * @brief clear SSL option
- *
- * @param ssl - SSL point
- * @param op  - setting option
- *
- * @return SSL option
- */
-unsigned long SSL_set_options(SSL *ssl, unsigned long op);
-
-/**
- * @brief set SSL quiet shutdown mode
- *
- * @param ssl  - SSL point
- * @param mode - quiet shutdown mode
- *
- * @return none
- */
-void SSL_set_quiet_shutdown(SSL *ssl, int mode);
-
-/**
- * @brief set SSL shutdown mode
- *
- * @param ssl  - SSL point
- * @param mode - shutdown mode
- *
- * @return none
- */
-void SSL_set_shutdown(SSL *ssl, int mode);
-
-/**
- * @brief set SSL session time
- *
- * @param ssl - SSL point
- * @param t   - session time
- *
- * @return session time
- */
-void SSL_set_time(SSL *ssl, long t);
-
-/**
- * @brief set SSL session timeout time
- *
- * @param ssl - SSL point
- * @param t   - session timeout time
- *
- * @return session timeout time
- */
-void SSL_set_timeout(SSL *ssl, long t);
-
-/**
- * @brief get SSL statement string
- *
- * @param ssl - SSL point
- *
- * @return SSL statement string
- */
-char *SSL_state_string(const SSL *ssl);
-
-/**
- * @brief get SSL statement long string
- *
- * @param ssl - SSL point
- *
- * @return SSL statement long string
- */
-char *SSL_state_string_long(const SSL *ssl);
-
-/**
- * @brief get SSL renegotiation count
- *
- * @param ssl - SSL point
- *
- * @return renegotiation count
- */
-long SSL_total_renegotiations(SSL *ssl);
-
-/**
- * @brief get SSL version
- *
- * @param ssl - SSL point
- *
- * @return SSL version
- */
-int SSL_version(const SSL *ssl);
-
-/**
- * @brief set SSL PSK identity hint
- *
- * @param ssl  - SSL point
- * @param hint - identity hint
- *
- * @return result
- *     1 : OK
- *     0 : failed
- */
-int SSL_use_psk_identity_hint(SSL *ssl, const char *hint);
-
-/**
- * @brief get SSL PSK identity hint
- *
- * @param ssl - SSL point
- *
- * @return identity hint
- */
-const char *SSL_get_psk_identity_hint(SSL *ssl);
-
-/**
- * @brief get SSL PSK identity
- *
- * @param ssl - SSL point
- *
- * @return identity
- */
-const char *SSL_get_psk_identity(SSL *ssl);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/platform/ssl_opt.h b/tools/sdk/include/openssl/platform/ssl_opt.h
deleted file mode 100644
index a9c55e8c469..00000000000
--- a/tools/sdk/include/openssl/platform/ssl_opt.h
+++ /dev/null
@@ -1,20 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_OPT_H_
-#define _SSL_OPT_H_
-
-#include "sdkconfig.h"
-
-#endif
diff --git a/tools/sdk/include/openssl/platform/ssl_pm.h b/tools/sdk/include/openssl/platform/ssl_pm.h
deleted file mode 100644
index f028a0cee88..00000000000
--- a/tools/sdk/include/openssl/platform/ssl_pm.h
+++ /dev/null
@@ -1,63 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_PM_H_
-#define _SSL_PM_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include <string.h>
-#include "ssl_types.h"
-#include "ssl_port.h"
-
-#define LOCAL_ATRR
-
-int ssl_pm_new(SSL *ssl);
-void ssl_pm_free(SSL *ssl);
-
-int ssl_pm_handshake(SSL *ssl);
-int ssl_pm_shutdown(SSL *ssl);
-int ssl_pm_clear(SSL *ssl);
-
-int ssl_pm_read(SSL *ssl, void *buffer, int len);
-int ssl_pm_send(SSL *ssl, const void *buffer, int len);
-int ssl_pm_pending(const SSL *ssl);
-
-void ssl_pm_set_fd(SSL *ssl, int fd, int mode);
-int ssl_pm_get_fd(const SSL *ssl, int mode);
-
-void ssl_pm_set_hostname(SSL *ssl, const char *hostname);
-
-OSSL_HANDSHAKE_STATE ssl_pm_get_state(const SSL *ssl);
-
-void ssl_pm_set_bufflen(SSL *ssl, int len);
-
-int x509_pm_show_info(X509 *x);
-int x509_pm_new(X509 *x, X509 *m_x);
-void x509_pm_free(X509 *x);
-int x509_pm_load(X509 *x, const unsigned char *buffer, int len);
-
-int pkey_pm_new(EVP_PKEY *pk, EVP_PKEY *m_pk);
-void pkey_pm_free(EVP_PKEY *pk);
-int pkey_pm_load(EVP_PKEY *pk, const unsigned char *buffer, int len);
-
-long ssl_pm_get_verify_result(const SSL *ssl);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tools/sdk/include/openssl/platform/ssl_port.h b/tools/sdk/include/openssl/platform/ssl_port.h
deleted file mode 100644
index 492ea405b2e..00000000000
--- a/tools/sdk/include/openssl/platform/ssl_port.h
+++ /dev/null
@@ -1,45 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SSL_PORT_H_
-#define _SSL_PORT_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "esp_types.h"
-#include "esp_log.h"
-#include "string.h"
-#include "malloc.h"
-
-void *ssl_mem_zalloc(size_t size);
-
-#define ssl_mem_malloc malloc
-#define ssl_mem_free   free
-
-#define ssl_memcpy     memcpy
-#define ssl_strlen     strlen
-
-#define ssl_speed_up_enter()
-#define ssl_speed_up_exit()
-
-#define SSL_DEBUG_FL
-#define SSL_DEBUG_LOG(fmt, ...) ESP_LOGI("openssl", fmt, ##__VA_ARGS__)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/tools/sdk/include/protobuf-c/protobuf-c/protobuf-c.h b/tools/sdk/include/protobuf-c/protobuf-c/protobuf-c.h
deleted file mode 100755
index c8fa4fc2a7c..00000000000
--- a/tools/sdk/include/protobuf-c/protobuf-c/protobuf-c.h
+++ /dev/null
@@ -1,1106 +0,0 @@
-/*
- * Copyright (c) 2008-2017, Dave Benson and the protobuf-c authors.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- *     * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- *     * Redistributions in binary form must reproduce the above
- * copyright notice, this list of conditions and the following disclaimer
- * in the documentation and/or other materials provided with the
- * distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*! \file
- * \mainpage Introduction
- *
- * This is [protobuf-c], a C implementation of [Protocol Buffers].
- *
- * This file defines the public API for the `libprotobuf-c` support library.
- * This API includes interfaces that can be used directly by client code as well
- * as the interfaces used by the code generated by the `protoc-c` compiler.
- *
- * The `libprotobuf-c` support library performs the actual serialization and
- * deserialization of Protocol Buffers messages. It interacts with structures,
- * definitions, and metadata generated by the `protoc-c` compiler from .proto
- * files.
- *
- * \authors Dave Benson and the `protobuf-c` authors.
- *
- * \copyright 2008-2014. Licensed under the terms of the [BSD-2-Clause] license.
- *
- * [protobuf-c]:       https://github.com/protobuf-c/protobuf-c
- * [Protocol Buffers]: https://developers.google.com/protocol-buffers/
- * [BSD-2-Clause]:     http://opensource.org/licenses/BSD-2-Clause
- *
- * \page gencode Generated Code
- *
- * For each enum, we generate a C enum. For each message, we generate a C
- * structure which can be cast to a `ProtobufCMessage`.
- *
- * For each enum and message, we generate a descriptor object that allows us to
- * implement a kind of reflection on the structures.
- *
- * First, some naming conventions:
- *
- * - The name of the type for enums and messages and services is camel case
- *   (meaning WordsAreCrammedTogether) except that double underscores are used
- *   to delimit scopes. For example, the following `.proto` file:
- *
-~~~{.proto}
-        package foo.bar;
-        message BazBah {
-            optional int32 val = 1;
-        }
-~~~
- *
- * would generate a C type `Foo__Bar__BazBah`.
- *
- * - Identifiers for functions and globals are all lowercase, with camel case
- *   words separated by single underscores. For example, one of the function
- *   prototypes generated by `protoc-c` for the above example:
- *
-~~~{.c}
-Foo__Bar__BazBah *
-       foo__bar__baz_bah__unpack
-                     (ProtobufCAllocator  *allocator,
-                      size_t               len,
-                      const uint8_t       *data);
-~~~
- *
- * - Identifiers for enum values contain an uppercase prefix which embeds the
- *   package name and the enum type name.
- *
- * - A double underscore is used to separate further components of identifier
- *   names.
- *
- * For example, in the name of the unpack function above, the package name
- * `foo.bar` has become `foo__bar`, the message name BazBah has become
- * `baz_bah`, and the method name is `unpack`. These are all joined with double
- * underscores to form the C identifier `foo__bar__baz_bah__unpack`.
- *
- * We also generate descriptor objects for messages and enums. These are
- * declared in the `.pb-c.h` files:
- *
-~~~{.c}
-extern const ProtobufCMessageDescriptor foo__bar__baz_bah__descriptor;
-~~~
- *
- * The message structures all begin with `ProtobufCMessageDescriptor *` which is
- * sufficient to allow them to be cast to `ProtobufCMessage`.
- *
- * For each message defined in a `.proto` file, we generate a number of
- * functions and macros. Each function name contains a prefix based on the
- * package name and message name in order to make it a unique C identifier.
- *
- * - `INIT`. Statically initializes a message object, initializing its
- *   descriptor and setting its fields to default values. Uninitialized
- *   messages cannot be processed by the protobuf-c library.
- *
-~~~{.c}
-#define FOO__BAR__BAZ_BAH__INIT \
- { PROTOBUF_C_MESSAGE_INIT (&foo__bar__baz_bah__descriptor), 0 }
-~~~
- * - `init()`. Initializes a message object, initializing its descriptor and
- *   setting its fields to default values. Uninitialized messages cannot be
- *   processed by the protobuf-c library.
- *
-~~~{.c}
-void foo__bar__baz_bah__init
-                     (Foo__Bar__BazBah *message);
-~~~
- * - `unpack()`. Unpacks data for a particular message format. Note that the
- *   `allocator` parameter is usually `NULL` to indicate that the system's
- *   `malloc()` and `free()` functions should be used for dynamically allocating
- *   memory.
- *
-~~~{.c}
-Foo__Bar__BazBah *
-       foo__bar__baz_bah__unpack
-                     (ProtobufCAllocator  *allocator,
-                      size_t               len,
-                      const uint8_t       *data);
-~~~
- *
- * - `free_unpacked()`. Frees a message object obtained with the `unpack()`
- *   method. Freeing `NULL` is allowed (the same as with `free()`).
- *
-~~~{.c}
-void   foo__bar__baz_bah__free_unpacked
-                     (Foo__Bar__BazBah *message,
-                      ProtobufCAllocator *allocator);
-~~~
- *
- * - `get_packed_size()`. Calculates the length in bytes of the serialized
- *   representation of the message object.
- *
-~~~{.c}
-size_t foo__bar__baz_bah__get_packed_size
-                     (const Foo__Bar__BazBah   *message);
-~~~
- *
- * - `pack()`. Pack a message object into a preallocated buffer. Assumes that
- *   the buffer is large enough. (Use `get_packed_size()` first.)
- *
-~~~{.c}
-size_t foo__bar__baz_bah__pack
-                     (const Foo__Bar__BazBah   *message,
-                      uint8_t             *out);
-~~~
- *
- * - `pack_to_buffer()`. Packs a message into a "virtual buffer". This is an
- *   object which defines an "append bytes" callback to consume data as it is
- *   serialized.
- *
-~~~{.c}
-size_t foo__bar__baz_bah__pack_to_buffer
-                     (const Foo__Bar__BazBah   *message,
-                      ProtobufCBuffer     *buffer);
-~~~
- *
- * \page pack Packing and unpacking messages
- *
- * To pack a message, first compute the packed size of the message with
- * protobuf_c_message_get_packed_size(), then allocate a buffer of at least
- * that size, then call protobuf_c_message_pack().
- *
- * Alternatively, a message can be serialized without calculating the final size
- * first. Use the protobuf_c_message_pack_to_buffer() function and provide a
- * ProtobufCBuffer object which implements an "append" method that consumes
- * data.
- *
- * To unpack a message, call the protobuf_c_message_unpack() function. The
- * result can be cast to an object of the type that matches the descriptor for
- * the message.
- *
- * The result of unpacking a message should be freed with
- * protobuf_c_message_free_unpacked().
- */
-
-#ifndef PROTOBUF_C_H
-#define PROTOBUF_C_H
-
-#include <assert.h>
-#include <limits.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-# define PROTOBUF_C__BEGIN_DECLS	extern "C" {
-# define PROTOBUF_C__END_DECLS		}
-#else
-# define PROTOBUF_C__BEGIN_DECLS
-# define PROTOBUF_C__END_DECLS
-#endif
-
-PROTOBUF_C__BEGIN_DECLS
-
-#if defined(_WIN32) && defined(PROTOBUF_C_USE_SHARED_LIB)
-# ifdef PROTOBUF_C_EXPORT
-#  define PROTOBUF_C__API __declspec(dllexport)
-# else
-#  define PROTOBUF_C__API __declspec(dllimport)
-# endif
-#else
-# define PROTOBUF_C__API
-#endif
-
-#if !defined(PROTOBUF_C__NO_DEPRECATED) && \
-	((__GNUC__ > 3) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1))
-# define PROTOBUF_C__DEPRECATED __attribute__((__deprecated__))
-#else
-# define PROTOBUF_C__DEPRECATED
-#endif
-
-#ifndef PROTOBUF_C__FORCE_ENUM_TO_BE_INT_SIZE
- #define PROTOBUF_C__FORCE_ENUM_TO_BE_INT_SIZE(enum_name) \
-  , _##enum_name##_IS_INT_SIZE = INT_MAX
-#endif
-
-#define PROTOBUF_C__SERVICE_DESCRIPTOR_MAGIC    0x14159bc3
-#define PROTOBUF_C__MESSAGE_DESCRIPTOR_MAGIC    0x28aaeef9
-#define PROTOBUF_C__ENUM_DESCRIPTOR_MAGIC       0x114315af
-
-/* Empty string used for initializers */
-extern const char protobuf_c_empty_string[];
-
-/**
- * \defgroup api Public API
- *
- * This is the public API for `libprotobuf-c`. These interfaces are stable and
- * subject to Semantic Versioning guarantees.
- *
- * @{
- */
-
-/**
- * Values for the `flags` word in `ProtobufCFieldDescriptor`.
- */
-typedef enum {
-	/** Set if the field is repeated and marked with the `packed` option. */
-	PROTOBUF_C_FIELD_FLAG_PACKED		= (1 << 0),
-
-	/** Set if the field is marked with the `deprecated` option. */
-	PROTOBUF_C_FIELD_FLAG_DEPRECATED	= (1 << 1),
-
-	/** Set if the field is a member of a oneof (union). */
-	PROTOBUF_C_FIELD_FLAG_ONEOF		= (1 << 2),
-} ProtobufCFieldFlag;
-
-/**
- * Message field rules.
- *
- * \see [Defining A Message Type] in the Protocol Buffers documentation.
- *
- * [Defining A Message Type]:
- *      https://developers.google.com/protocol-buffers/docs/proto#simple
- */
-typedef enum {
-	/** A well-formed message must have exactly one of this field. */
-	PROTOBUF_C_LABEL_REQUIRED,
-
-	/**
-	 * A well-formed message can have zero or one of this field (but not
-	 * more than one).
-	 */
-	PROTOBUF_C_LABEL_OPTIONAL,
-
-	/**
-	 * This field can be repeated any number of times (including zero) in a
-	 * well-formed message. The order of the repeated values will be
-	 * preserved.
-	 */
-	PROTOBUF_C_LABEL_REPEATED,
-
-	/**
-	 * This field has no label. This is valid only in proto3 and is
-	 * equivalent to OPTIONAL but no "has" quantifier will be consulted.
-	 */
-	PROTOBUF_C_LABEL_NONE,
-} ProtobufCLabel;
-
-/**
- * Field value types.
- *
- * \see [Scalar Value Types] in the Protocol Buffers documentation.
- *
- * [Scalar Value Types]:
- *      https://developers.google.com/protocol-buffers/docs/proto#scalar
- */
-typedef enum {
-	PROTOBUF_C_TYPE_INT32,      /**< int32 */
-	PROTOBUF_C_TYPE_SINT32,     /**< signed int32 */
-	PROTOBUF_C_TYPE_SFIXED32,   /**< signed int32 (4 bytes) */
-	PROTOBUF_C_TYPE_INT64,      /**< int64 */
-	PROTOBUF_C_TYPE_SINT64,     /**< signed int64 */
-	PROTOBUF_C_TYPE_SFIXED64,   /**< signed int64 (8 bytes) */
-	PROTOBUF_C_TYPE_UINT32,     /**< unsigned int32 */
-	PROTOBUF_C_TYPE_FIXED32,    /**< unsigned int32 (4 bytes) */
-	PROTOBUF_C_TYPE_UINT64,     /**< unsigned int64 */
-	PROTOBUF_C_TYPE_FIXED64,    /**< unsigned int64 (8 bytes) */
-	PROTOBUF_C_TYPE_FLOAT,      /**< float */
-	PROTOBUF_C_TYPE_DOUBLE,     /**< double */
-	PROTOBUF_C_TYPE_BOOL,       /**< boolean */
-	PROTOBUF_C_TYPE_ENUM,       /**< enumerated type */
-	PROTOBUF_C_TYPE_STRING,     /**< UTF-8 or ASCII string */
-	PROTOBUF_C_TYPE_BYTES,      /**< arbitrary byte sequence */
-	PROTOBUF_C_TYPE_MESSAGE,    /**< nested message */
-} ProtobufCType;
-
-/**
- * Field wire types.
- *
- * \see [Message Structure] in the Protocol Buffers documentation.
- *
- * [Message Structure]:
- *      https://developers.google.com/protocol-buffers/docs/encoding#structure
- */
-typedef enum {
-	PROTOBUF_C_WIRE_TYPE_VARINT = 0,
-	PROTOBUF_C_WIRE_TYPE_64BIT = 1,
-	PROTOBUF_C_WIRE_TYPE_LENGTH_PREFIXED = 2,
-	/* "Start group" and "end group" wire types are unsupported. */
-	PROTOBUF_C_WIRE_TYPE_32BIT = 5,
-} ProtobufCWireType;
-
-struct ProtobufCAllocator;
-struct ProtobufCBinaryData;
-struct ProtobufCBuffer;
-struct ProtobufCBufferSimple;
-struct ProtobufCEnumDescriptor;
-struct ProtobufCEnumValue;
-struct ProtobufCEnumValueIndex;
-struct ProtobufCFieldDescriptor;
-struct ProtobufCIntRange;
-struct ProtobufCMessage;
-struct ProtobufCMessageDescriptor;
-struct ProtobufCMessageUnknownField;
-struct ProtobufCMethodDescriptor;
-struct ProtobufCService;
-struct ProtobufCServiceDescriptor;
-
-typedef struct ProtobufCAllocator ProtobufCAllocator;
-typedef struct ProtobufCBinaryData ProtobufCBinaryData;
-typedef struct ProtobufCBuffer ProtobufCBuffer;
-typedef struct ProtobufCBufferSimple ProtobufCBufferSimple;
-typedef struct ProtobufCEnumDescriptor ProtobufCEnumDescriptor;
-typedef struct ProtobufCEnumValue ProtobufCEnumValue;
-typedef struct ProtobufCEnumValueIndex ProtobufCEnumValueIndex;
-typedef struct ProtobufCFieldDescriptor ProtobufCFieldDescriptor;
-typedef struct ProtobufCIntRange ProtobufCIntRange;
-typedef struct ProtobufCMessage ProtobufCMessage;
-typedef struct ProtobufCMessageDescriptor ProtobufCMessageDescriptor;
-typedef struct ProtobufCMessageUnknownField ProtobufCMessageUnknownField;
-typedef struct ProtobufCMethodDescriptor ProtobufCMethodDescriptor;
-typedef struct ProtobufCService ProtobufCService;
-typedef struct ProtobufCServiceDescriptor ProtobufCServiceDescriptor;
-
-/** Boolean type. */
-typedef int protobuf_c_boolean;
-
-typedef void (*ProtobufCClosure)(const ProtobufCMessage *, void *closure_data);
-typedef void (*ProtobufCMessageInit)(ProtobufCMessage *);
-typedef void (*ProtobufCServiceDestroy)(ProtobufCService *);
-
-/**
- * Structure for defining a custom memory allocator.
- */
-struct ProtobufCAllocator {
-	/** Function to allocate memory. */
-	void		*(*alloc)(void *allocator_data, size_t size);
-
-	/** Function to free memory. */
-	void		(*free)(void *allocator_data, void *pointer);
-
-	/** Opaque pointer passed to `alloc` and `free` functions. */
-	void		*allocator_data;
-};
-
-/**
- * Structure for the protobuf `bytes` scalar type.
- *
- * The data contained in a `ProtobufCBinaryData` is an arbitrary sequence of
- * bytes. It may contain embedded `NUL` characters and is not required to be
- * `NUL`-terminated.
- */
-struct ProtobufCBinaryData {
-	size_t	len;        /**< Number of bytes in the `data` field. */
-	uint8_t	*data;      /**< Data bytes. */
-};
-
-/**
- * Structure for defining a virtual append-only buffer. Used by
- * protobuf_c_message_pack_to_buffer() to abstract the consumption of serialized
- * bytes.
- *
- * `ProtobufCBuffer` "subclasses" may be defined on the stack. For example, to
- * write to a `FILE` object:
- *
-~~~{.c}
-typedef struct {
-        ProtobufCBuffer base;
-        FILE *fp;
-} BufferAppendToFile;
-
-static void
-my_buffer_file_append(ProtobufCBuffer *buffer,
-                      size_t len,
-                      const uint8_t *data)
-{
-        BufferAppendToFile *file_buf = (BufferAppendToFile *) buffer;
-        fwrite(data, len, 1, file_buf->fp); // XXX: No error handling!
-}
-~~~
- *
- * To use this new type of ProtobufCBuffer, it could be called as follows:
- *
-~~~{.c}
-...
-BufferAppendToFile tmp = {0};
-tmp.base.append = my_buffer_file_append;
-tmp.fp = fp;
-protobuf_c_message_pack_to_buffer(&message, &tmp);
-...
-~~~
- */
-struct ProtobufCBuffer {
-	/** Append function. Consumes the `len` bytes stored at `data`. */
-	void		(*append)(ProtobufCBuffer *buffer,
-				  size_t len,
-				  const uint8_t *data);
-};
-
-/**
- * Simple buffer "subclass" of `ProtobufCBuffer`.
- *
- * A `ProtobufCBufferSimple` object is declared on the stack and uses a
- * scratch buffer provided by the user for the initial allocation. It performs
- * exponential resizing, using dynamically allocated memory. A
- * `ProtobufCBufferSimple` object can be created and used as follows:
- *
-~~~{.c}
-uint8_t pad[128];
-ProtobufCBufferSimple simple = PROTOBUF_C_BUFFER_SIMPLE_INIT(pad);
-ProtobufCBuffer *buffer = (ProtobufCBuffer *) &simple;
-~~~
- *
- * `buffer` can now be used with `protobuf_c_message_pack_to_buffer()`. Once a
- * message has been serialized to a `ProtobufCBufferSimple` object, the
- * serialized data bytes can be accessed from the `.data` field.
- *
- * To free the memory allocated by a `ProtobufCBufferSimple` object, if any,
- * call PROTOBUF_C_BUFFER_SIMPLE_CLEAR() on the object, for example:
- *
-~~~{.c}
-PROTOBUF_C_BUFFER_SIMPLE_CLEAR(&simple);
-~~~
- *
- * \see PROTOBUF_C_BUFFER_SIMPLE_INIT
- * \see PROTOBUF_C_BUFFER_SIMPLE_CLEAR
- */
-struct ProtobufCBufferSimple {
-	/** "Base class". */
-	ProtobufCBuffer		base;
-	/** Number of bytes allocated in `data`. */
-	size_t			alloced;
-	/** Number of bytes currently stored in `data`. */
-	size_t			len;
-	/** Data bytes. */
-	uint8_t			*data;
-	/** Whether `data` must be freed. */
-	protobuf_c_boolean	must_free_data;
-	/** Allocator to use. May be NULL to indicate the system allocator. */
-	ProtobufCAllocator	*allocator;
-};
-
-/**
- * Describes an enumeration as a whole, with all of its values.
- */
-struct ProtobufCEnumDescriptor {
-	/** Magic value checked to ensure that the API is used correctly. */
-	uint32_t			magic;
-
-	/** The qualified name (e.g., "namespace.Type"). */
-	const char			*name;
-	/** The unqualified name as given in the .proto file (e.g., "Type"). */
-	const char			*short_name;
-	/** Identifier used in generated C code. */
-	const char			*c_name;
-	/** The dot-separated namespace. */
-	const char			*package_name;
-
-	/** Number elements in `values`. */
-	unsigned			n_values;
-	/** Array of distinct values, sorted by numeric value. */
-	const ProtobufCEnumValue	*values;
-
-	/** Number of elements in `values_by_name`. */
-	unsigned			n_value_names;
-	/** Array of named values, including aliases, sorted by name. */
-	const ProtobufCEnumValueIndex	*values_by_name;
-
-	/** Number of elements in `value_ranges`. */
-	unsigned			n_value_ranges;
-	/** Value ranges, for faster lookups by numeric value. */
-	const ProtobufCIntRange		*value_ranges;
-
-	/** Reserved for future use. */
-	void				*reserved1;
-	/** Reserved for future use. */
-	void				*reserved2;
-	/** Reserved for future use. */
-	void				*reserved3;
-	/** Reserved for future use. */
-	void				*reserved4;
-};
-
-/**
- * Represents a single value of an enumeration.
- */
-struct ProtobufCEnumValue {
-	/** The string identifying this value in the .proto file. */
-	const char	*name;
-
-	/** The string identifying this value in generated C code. */
-	const char	*c_name;
-
-	/** The numeric value assigned in the .proto file. */
-	int		value;
-};
-
-/**
- * Used by `ProtobufCEnumDescriptor` to look up enum values.
- */
-struct ProtobufCEnumValueIndex {
-	/** Name of the enum value. */
-	const char      *name;
-	/** Index into values[] array. */
-	unsigned        index;
-};
-
-/**
- * Describes a single field in a message.
- */
-struct ProtobufCFieldDescriptor {
-	/** Name of the field as given in the .proto file. */
-	const char		*name;
-
-	/** Tag value of the field as given in the .proto file. */
-	uint32_t		id;
-
-	/** Whether the field is `REQUIRED`, `OPTIONAL`, or `REPEATED`. */
-	ProtobufCLabel		label;
-
-	/** The type of the field. */
-	ProtobufCType		type;
-
-	/**
-	 * The offset in bytes of the message's C structure's quantifier field
-	 * (the `has_MEMBER` field for optional members or the `n_MEMBER` field
-	 * for repeated members or the case enum for oneofs).
-	 */
-	unsigned		quantifier_offset;
-
-	/**
-	 * The offset in bytes into the message's C structure for the member
-	 * itself.
-	 */
-	unsigned		offset;
-
-	/**
-	 * A type-specific descriptor.
-	 *
-	 * If `type` is `PROTOBUF_C_TYPE_ENUM`, then `descriptor` points to the
-	 * corresponding `ProtobufCEnumDescriptor`.
-	 *
-	 * If `type` is `PROTOBUF_C_TYPE_MESSAGE`, then `descriptor` points to
-	 * the corresponding `ProtobufCMessageDescriptor`.
-	 *
-	 * Otherwise this field is NULL.
-	 */
-	const void		*descriptor; /* for MESSAGE and ENUM types */
-
-	/** The default value for this field, if defined. May be NULL. */
-	const void		*default_value;
-
-	/**
-	 * A flag word. Zero or more of the bits defined in the
-	 * `ProtobufCFieldFlag` enum may be set.
-	 */
-	uint32_t		flags;
-
-	/** Reserved for future use. */
-	unsigned		reserved_flags;
-	/** Reserved for future use. */
-	void			*reserved2;
-	/** Reserved for future use. */
-	void			*reserved3;
-};
-
-/**
- * Helper structure for optimizing int => index lookups in the case
- * where the keys are mostly consecutive values, as they presumably are for
- * enums and fields.
- *
- * The data structures requires that the values in the original array are
- * sorted.
- */
-struct ProtobufCIntRange {
-	int             start_value;
-	unsigned        orig_index;
-	/*
-	 * NOTE: the number of values in the range can be inferred by looking
-	 * at the next element's orig_index. A dummy element is added to make
-	 * this simple.
-	 */
-};
-
-/**
- * An instance of a message.
- *
- * `ProtobufCMessage` is a light-weight "base class" for all messages.
- *
- * In particular, `ProtobufCMessage` doesn't have any allocation policy
- * associated with it. That's because it's common to create `ProtobufCMessage`
- * objects on the stack. In fact, that's what we recommend for sending messages.
- * If the object is allocated from the stack, you can't really have a memory
- * leak.
- *
- * This means that calls to functions like protobuf_c_message_unpack() which
- * return a `ProtobufCMessage` must be paired with a call to a free function,
- * like protobuf_c_message_free_unpacked().
- */
-struct ProtobufCMessage {
-	/** The descriptor for this message type. */
-	const ProtobufCMessageDescriptor	*descriptor;
-	/** The number of elements in `unknown_fields`. */
-	unsigned				n_unknown_fields;
-	/** The fields that weren't recognized by the parser. */
-	ProtobufCMessageUnknownField		*unknown_fields;
-};
-
-/**
- * Describes a message.
- */
-struct ProtobufCMessageDescriptor {
-	/** Magic value checked to ensure that the API is used correctly. */
-	uint32_t			magic;
-
-	/** The qualified name (e.g., "namespace.Type"). */
-	const char			*name;
-	/** The unqualified name as given in the .proto file (e.g., "Type"). */
-	const char			*short_name;
-	/** Identifier used in generated C code. */
-	const char			*c_name;
-	/** The dot-separated namespace. */
-	const char			*package_name;
-
-	/**
-	 * Size in bytes of the C structure representing an instance of this
-	 * type of message.
-	 */
-	size_t				sizeof_message;
-
-	/** Number of elements in `fields`. */
-	unsigned			n_fields;
-	/** Field descriptors, sorted by tag number. */
-	const ProtobufCFieldDescriptor	*fields;
-	/** Used for looking up fields by name. */
-	const unsigned			*fields_sorted_by_name;
-
-	/** Number of elements in `field_ranges`. */
-	unsigned			n_field_ranges;
-	/** Used for looking up fields by id. */
-	const ProtobufCIntRange		*field_ranges;
-
-	/** Message initialisation function. */
-	ProtobufCMessageInit		message_init;
-
-	/** Reserved for future use. */
-	void				*reserved1;
-	/** Reserved for future use. */
-	void				*reserved2;
-	/** Reserved for future use. */
-	void				*reserved3;
-};
-
-/**
- * An unknown message field.
- */
-struct ProtobufCMessageUnknownField {
-	/** The tag number. */
-	uint32_t		tag;
-	/** The wire type of the field. */
-	ProtobufCWireType	wire_type;
-	/** Number of bytes in `data`. */
-	size_t			len;
-	/** Field data. */
-	uint8_t			*data;
-};
-
-/**
- * Method descriptor.
- */
-struct ProtobufCMethodDescriptor {
-	/** Method name. */
-	const char				*name;
-	/** Input message descriptor. */
-	const ProtobufCMessageDescriptor	*input;
-	/** Output message descriptor. */
-	const ProtobufCMessageDescriptor	*output;
-};
-
-/**
- * Service.
- */
-struct ProtobufCService {
-	/** Service descriptor. */
-	const ProtobufCServiceDescriptor *descriptor;
-	/** Function to invoke the service. */
-	void (*invoke)(ProtobufCService *service,
-		       unsigned method_index,
-		       const ProtobufCMessage *input,
-		       ProtobufCClosure closure,
-		       void *closure_data);
-	/** Function to destroy the service. */
-	void (*destroy)(ProtobufCService *service);
-};
-
-/**
- * Service descriptor.
- */
-struct ProtobufCServiceDescriptor {
-	/** Magic value checked to ensure that the API is used correctly. */
-	uint32_t			magic;
-
-	/** Service name. */
-	const char			*name;
-	/** Short version of service name. */
-	const char			*short_name;
-	/** C identifier for the service name. */
-	const char			*c_name;
-	/** Package name. */
-	const char			*package;
-	/** Number of elements in `methods`. */
-	unsigned			n_methods;
-	/** Method descriptors, in the order defined in the .proto file. */
-	const ProtobufCMethodDescriptor	*methods;
-	/** Sort index of methods. */
-	const unsigned			*method_indices_by_name;
-};
-
-/**
- * Get the version of the protobuf-c library. Note that this is the version of
- * the library linked against, not the version of the headers compiled against.
- *
- * \return A string containing the version number of protobuf-c.
- */
-PROTOBUF_C__API
-const char *
-protobuf_c_version(void);
-
-/**
- * Get the version of the protobuf-c library. Note that this is the version of
- * the library linked against, not the version of the headers compiled against.
- *
- * \return A 32 bit unsigned integer containing the version number of
- *      protobuf-c, represented in base-10 as (MAJOR*1E6) + (MINOR*1E3) + PATCH.
- */
-PROTOBUF_C__API
-uint32_t
-protobuf_c_version_number(void);
-
-/**
- * The version of the protobuf-c headers, represented as a string using the same
- * format as protobuf_c_version().
- */
-#define PROTOBUF_C_VERSION		"1.3.0"
-
-/**
- * The version of the protobuf-c headers, represented as an integer using the
- * same format as protobuf_c_version_number().
- */
-#define PROTOBUF_C_VERSION_NUMBER	1003000
-
-/**
- * The minimum protoc-c version which works with the current version of the
- * protobuf-c headers.
- */
-#define PROTOBUF_C_MIN_COMPILER_VERSION	1000000
-
-/**
- * Look up a `ProtobufCEnumValue` from a `ProtobufCEnumDescriptor` by name.
- *
- * \param desc
- *      The `ProtobufCEnumDescriptor` object.
- * \param name
- *      The `name` field from the corresponding `ProtobufCEnumValue` object to
- *      match.
- * \return
- *      A `ProtobufCEnumValue` object.
- * \retval NULL
- *      If not found or if the optimize_for = CODE_SIZE option was set.
- */
-PROTOBUF_C__API
-const ProtobufCEnumValue *
-protobuf_c_enum_descriptor_get_value_by_name(
-	const ProtobufCEnumDescriptor *desc,
-	const char *name);
-
-/**
- * Look up a `ProtobufCEnumValue` from a `ProtobufCEnumDescriptor` by numeric
- * value.
- *
- * \param desc
- *      The `ProtobufCEnumDescriptor` object.
- * \param value
- *      The `value` field from the corresponding `ProtobufCEnumValue` object to
- *      match.
- *
- * \return
- *      A `ProtobufCEnumValue` object.
- * \retval NULL
- *      If not found.
- */
-PROTOBUF_C__API
-const ProtobufCEnumValue *
-protobuf_c_enum_descriptor_get_value(
-	const ProtobufCEnumDescriptor *desc,
-	int value);
-
-/**
- * Look up a `ProtobufCFieldDescriptor` from a `ProtobufCMessageDescriptor` by
- * the name of the field.
- *
- * \param desc
- *      The `ProtobufCMessageDescriptor` object.
- * \param name
- *      The name of the field.
- * \return
- *      A `ProtobufCFieldDescriptor` object.
- * \retval NULL
- *      If not found or if the optimize_for = CODE_SIZE option was set.
- */
-PROTOBUF_C__API
-const ProtobufCFieldDescriptor *
-protobuf_c_message_descriptor_get_field_by_name(
-	const ProtobufCMessageDescriptor *desc,
-	const char *name);
-
-/**
- * Look up a `ProtobufCFieldDescriptor` from a `ProtobufCMessageDescriptor` by
- * the tag value of the field.
- *
- * \param desc
- *      The `ProtobufCMessageDescriptor` object.
- * \param value
- *      The tag value of the field.
- * \return
- *      A `ProtobufCFieldDescriptor` object.
- * \retval NULL
- *      If not found.
- */
-PROTOBUF_C__API
-const ProtobufCFieldDescriptor *
-protobuf_c_message_descriptor_get_field(
-	const ProtobufCMessageDescriptor *desc,
-	unsigned value);
-
-/**
- * Determine the number of bytes required to store the serialised message.
- *
- * \param message
- *      The message object to serialise.
- * \return
- *      Number of bytes.
- */
-PROTOBUF_C__API
-size_t
-protobuf_c_message_get_packed_size(const ProtobufCMessage *message);
-
-/**
- * Serialise a message from its in-memory representation.
- *
- * This function stores the serialised bytes of the message in a pre-allocated
- * buffer.
- *
- * \param message
- *      The message object to serialise.
- * \param[out] out
- *      Buffer to store the bytes of the serialised message. This buffer must
- *      have enough space to store the packed message. Use
- *      protobuf_c_message_get_packed_size() to determine the number of bytes
- *      required.
- * \return
- *      Number of bytes stored in `out`.
- */
-PROTOBUF_C__API
-size_t
-protobuf_c_message_pack(const ProtobufCMessage *message, uint8_t *out);
-
-/**
- * Serialise a message from its in-memory representation to a virtual buffer.
- *
- * This function calls the `append` method of a `ProtobufCBuffer` object to
- * consume the bytes generated by the serialiser.
- *
- * \param message
- *      The message object to serialise.
- * \param buffer
- *      The virtual buffer object.
- * \return
- *      Number of bytes passed to the virtual buffer.
- */
-PROTOBUF_C__API
-size_t
-protobuf_c_message_pack_to_buffer(
-	const ProtobufCMessage *message,
-	ProtobufCBuffer *buffer);
-
-/**
- * Unpack a serialised message into an in-memory representation.
- *
- * \param descriptor
- *      The message descriptor.
- * \param allocator
- *      `ProtobufCAllocator` to use for memory allocation. May be NULL to
- *      specify the default allocator.
- * \param len
- *      Length in bytes of the serialised message.
- * \param data
- *      Pointer to the serialised message.
- * \return
- *      An unpacked message object.
- * \retval NULL
- *      If an error occurred during unpacking.
- */
-PROTOBUF_C__API
-ProtobufCMessage *
-protobuf_c_message_unpack(
-	const ProtobufCMessageDescriptor *descriptor,
-	ProtobufCAllocator *allocator,
-	size_t len,
-	const uint8_t *data);
-
-/**
- * Free an unpacked message object.
- *
- * This function should be used to deallocate the memory used by a call to
- * protobuf_c_message_unpack().
- *
- * \param message
- *      The message object to free. May be NULL.
- * \param allocator
- *      `ProtobufCAllocator` to use for memory deallocation. May be NULL to
- *      specify the default allocator.
- */
-PROTOBUF_C__API
-void
-protobuf_c_message_free_unpacked(
-	ProtobufCMessage *message,
-	ProtobufCAllocator *allocator);
-
-/**
- * Check the validity of a message object.
- *
- * Makes sure all required fields (`PROTOBUF_C_LABEL_REQUIRED`) are present.
- * Recursively checks nested messages.
- *
- * \retval TRUE
- *      Message is valid.
- * \retval FALSE
- *      Message is invalid.
- */
-PROTOBUF_C__API
-protobuf_c_boolean
-protobuf_c_message_check(const ProtobufCMessage *);
-
-/** Message initialiser. */
-#define PROTOBUF_C_MESSAGE_INIT(descriptor) { descriptor, 0, NULL }
-
-/**
- * Initialise a message object from a message descriptor.
- *
- * \param descriptor
- *      Message descriptor.
- * \param message
- *      Allocated block of memory of size `descriptor->sizeof_message`.
- */
-PROTOBUF_C__API
-void
-protobuf_c_message_init(
-	const ProtobufCMessageDescriptor *descriptor,
-	void *message);
-
-/**
- * Free a service.
- *
- * \param service
- *      The service object to free.
- */
-PROTOBUF_C__API
-void
-protobuf_c_service_destroy(ProtobufCService *service);
-
-/**
- * Look up a `ProtobufCMethodDescriptor` by name.
- *
- * \param desc
- *      Service descriptor.
- * \param name
- *      Name of the method.
- *
- * \return
- *      A `ProtobufCMethodDescriptor` object.
- * \retval NULL
- *      If not found or if the optimize_for = CODE_SIZE option was set.
- */
-PROTOBUF_C__API
-const ProtobufCMethodDescriptor *
-protobuf_c_service_descriptor_get_method_by_name(
-	const ProtobufCServiceDescriptor *desc,
-	const char *name);
-
-/**
- * Initialise a `ProtobufCBufferSimple` object.
- */
-#define PROTOBUF_C_BUFFER_SIMPLE_INIT(array_of_bytes)                   \
-{                                                                       \
-	{ protobuf_c_buffer_simple_append },                            \
-	sizeof(array_of_bytes),                                         \
-	0,                                                              \
-	(array_of_bytes),                                               \
-	0,                                                              \
-	NULL                                                            \
-}
-
-/**
- * Clear a `ProtobufCBufferSimple` object, freeing any allocated memory.
- */
-#define PROTOBUF_C_BUFFER_SIMPLE_CLEAR(simp_buf)                        \
-do {                                                                    \
-	if ((simp_buf)->must_free_data) {                               \
-		if ((simp_buf)->allocator != NULL)                      \
-			(simp_buf)->allocator->free(                    \
-				(simp_buf)->allocator,                  \
-				(simp_buf)->data);			\
-		else                                                    \
-			free((simp_buf)->data);                         \
-	}                                                               \
-} while (0)
-
-/**
- * The `append` method for `ProtobufCBufferSimple`.
- *
- * \param buffer
- *      The buffer object to append to. Must actually be a
- *      `ProtobufCBufferSimple` object.
- * \param len
- *      Number of bytes in `data`.
- * \param data
- *      Data to append.
- */
-PROTOBUF_C__API
-void
-protobuf_c_buffer_simple_append(
-	ProtobufCBuffer *buffer,
-	size_t len,
-	const unsigned char *data);
-
-PROTOBUF_C__API
-void
-protobuf_c_service_generated_init(
-	ProtobufCService *service,
-	const ProtobufCServiceDescriptor *descriptor,
-	ProtobufCServiceDestroy destroy);
-
-PROTOBUF_C__API
-void
-protobuf_c_service_invoke_internal(
-	ProtobufCService *service,
-	unsigned method_index,
-	const ProtobufCMessage *input,
-	ProtobufCClosure closure,
-	void *closure_data);
-
-/**@}*/
-
-PROTOBUF_C__END_DECLS
-
-#endif /* PROTOBUF_C_H */
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_bytes_field.h b/tools/sdk/include/protobuf-c/protoc-c/c_bytes_field.h
deleted file mode 100644
index c4a71e85b47..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_bytes_field.h
+++ /dev/null
@@ -1,100 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_BYTES_FIELD_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_BYTES_FIELD_H__
-
-#include <map>
-#include <string>
-#include <protoc-c/c_field.h>
-
-namespace google {
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class BytesFieldGenerator : public FieldGenerator {
- public:
-  explicit BytesFieldGenerator(const FieldDescriptor* descriptor);
-  ~BytesFieldGenerator();
-
-  // implements FieldGenerator ---------------------------------------
-  void GenerateStructMembers(io::Printer* printer) const;
-  void GenerateDescriptorInitializer(io::Printer* printer) const;
-  void GenerateDefaultValueDeclarations(io::Printer* printer) const;
-  void GenerateDefaultValueImplementations(io::Printer* printer) const;
-  string GetDefaultValue(void) const;
-  void GenerateStaticInit(io::Printer* printer) const;
-
- private:
-  std::map<string, string> variables_;
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(BytesFieldGenerator);
-};
-
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-}  // namespace google
-
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_STRING_FIELD_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_enum.h b/tools/sdk/include/protobuf-c/protoc-c/c_enum.h
deleted file mode 100644
index 9eb9a6679ce..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_enum.h
+++ /dev/null
@@ -1,118 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_ENUM_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_ENUM_H__
-
-#include <string>
-#include <google/protobuf/descriptor.h>
-
-namespace google {
-namespace protobuf {
-  namespace io {
-    class Printer;             // printer.h
-  }
-}
-
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class EnumGenerator {
- public:
-  // See generator.cc for the meaning of dllexport_decl.
-  explicit EnumGenerator(const EnumDescriptor* descriptor,
-                         const string& dllexport_decl);
-  ~EnumGenerator();
-
-  // Header stuff.
-
-  // Generate header code defining the enum.  This code should be placed
-  // within the enum's package namespace, but NOT within any class, even for
-  // nested enums.
-  void GenerateDefinition(io::Printer* printer);
-
-  void GenerateDescriptorDeclarations(io::Printer* printer);
-
-
-  // Source file stuff.
-
-  // Generate the ProtobufCEnumDescriptor for this enum
-  void GenerateEnumDescriptor(io::Printer* printer);
-
-  // Generate static initializer for a ProtobufCEnumValue
-  // given the index of the value in the enum.
-  void GenerateValueInitializer(io::Printer *printer, int index);
-
- private:
-  const EnumDescriptor* descriptor_;
-  string dllexport_decl_;
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(EnumGenerator);
-};
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_ENUM_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_enum_field.h b/tools/sdk/include/protobuf-c/protoc-c/c_enum_field.h
deleted file mode 100644
index 11df6824693..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_enum_field.h
+++ /dev/null
@@ -1,98 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_ENUM_FIELD_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_ENUM_FIELD_H__
-
-#include <map>
-#include <string>
-#include <protoc-c/c_field.h>
-
-namespace google {
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class EnumFieldGenerator : public FieldGenerator {
- public:
-  explicit EnumFieldGenerator(const FieldDescriptor* descriptor);
-  ~EnumFieldGenerator();
-
-  // implements FieldGenerator ---------------------------------------
-  void GenerateStructMembers(io::Printer* printer) const;
-  void GenerateDescriptorInitializer(io::Printer* printer) const;
-  string GetDefaultValue(void) const;
-  void GenerateStaticInit(io::Printer* printer) const;
-
- private:
-  std::map<string, string> variables_;
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(EnumFieldGenerator);
-};
-
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_ENUM_FIELD_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_extension.h b/tools/sdk/include/protobuf-c/protoc-c/c_extension.h
deleted file mode 100644
index ddbf270e5a1..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_extension.h
+++ /dev/null
@@ -1,110 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_EXTENSION_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_EXTENSION_H__
-
-#include <string>
-#include <google/protobuf/stubs/common.h>
-
-namespace google {
-namespace protobuf {
-  class FieldDescriptor;       // descriptor.h
-  namespace io {
-    class Printer;             // printer.h
-  }
-}
-
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-// Generates code for an extension, which may be within the scope of some
-// message or may be at file scope.  This is much simpler than FieldGenerator
-// since extensions are just simple identifiers with interesting types.
-class ExtensionGenerator {
- public:
-  // See generator.cc for the meaning of dllexport_decl.
-  explicit ExtensionGenerator(const FieldDescriptor* descriptor,
-                              const string& dllexport_decl);
-  ~ExtensionGenerator();
-
-  // Header stuff.
-  void GenerateDeclaration(io::Printer* printer);
-
-  // Source file stuff.
-  void GenerateDefinition(io::Printer* printer);
-
- private:
-  const FieldDescriptor* descriptor_;
-  string type_traits_;
-  string dllexport_decl_;
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(ExtensionGenerator);
-};
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_MESSAGE_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_field.h b/tools/sdk/include/protobuf-c/protoc-c/c_field.h
deleted file mode 100644
index 91f1a03dafb..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_field.h
+++ /dev/null
@@ -1,132 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_FIELD_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_FIELD_H__
-
-#include <google/protobuf/stubs/common.h>
-#include <google/protobuf/descriptor.h>
-
-namespace google {
-namespace protobuf {
-  namespace io {
-    class Printer;             // printer.h
-  }
-}
-
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class FieldGenerator {
- public:
-  explicit FieldGenerator(const FieldDescriptor *descriptor) : descriptor_(descriptor) {}
-  virtual ~FieldGenerator();
-
-  // Generate definitions to be included in the structure.
-  virtual void GenerateStructMembers(io::Printer* printer) const = 0;
-
-  // Generate a static initializer for this field.
-  virtual void GenerateDescriptorInitializer(io::Printer* printer) const = 0;
-
-  virtual void GenerateDefaultValueDeclarations(io::Printer* printer) const { }
-  virtual void GenerateDefaultValueImplementations(io::Printer* printer) const { }
-  virtual string GetDefaultValue() const = 0;
-
-  // Generate members to initialize this field from a static initializer
-  virtual void GenerateStaticInit(io::Printer* printer) const = 0;
-
-
- protected:
-  void GenerateDescriptorInitializerGeneric(io::Printer* printer,
-                                            bool optional_uses_has,
-                                            const string &type_macro,
-                                            const string &descriptor_addr) const;
-  const FieldDescriptor *descriptor_;
-
- private:
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(FieldGenerator);
-};
-
-// Convenience class which constructs FieldGenerators for a Descriptor.
-class FieldGeneratorMap {
- public:
-  explicit FieldGeneratorMap(const Descriptor* descriptor);
-  ~FieldGeneratorMap();
-
-  const FieldGenerator& get(const FieldDescriptor* field) const;
-
- private:
-  const Descriptor* descriptor_;
-  scoped_array<scoped_ptr<FieldGenerator> > field_generators_;
-
-  static FieldGenerator* MakeGenerator(const FieldDescriptor* field);
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(FieldGeneratorMap);
-};
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_FIELD_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_file.h b/tools/sdk/include/protobuf-c/protoc-c/c_file.h
deleted file mode 100644
index ed38ce425c3..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_file.h
+++ /dev/null
@@ -1,117 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_FILE_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_FILE_H__
-
-#include <string>
-#include <vector>
-#include <google/protobuf/stubs/common.h>
-#include <protoc-c/c_field.h>
-
-namespace google {
-namespace protobuf {
-  class FileDescriptor;        // descriptor.h
-  namespace io {
-    class Printer;             // printer.h
-  }
-}
-
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class EnumGenerator;           // enum.h
-class MessageGenerator;        // message.h
-class ServiceGenerator;        // service.h
-class ExtensionGenerator;      // extension.h
-
-class FileGenerator {
- public:
-  // See generator.cc for the meaning of dllexport_decl.
-  explicit FileGenerator(const FileDescriptor* file,
-                         const string& dllexport_decl);
-  ~FileGenerator();
-
-  void GenerateHeader(io::Printer* printer);
-  void GenerateSource(io::Printer* printer);
-
- private:
-  const FileDescriptor* file_;
-
-  scoped_array<scoped_ptr<MessageGenerator> > message_generators_;
-  scoped_array<scoped_ptr<EnumGenerator> > enum_generators_;
-  scoped_array<scoped_ptr<ServiceGenerator> > service_generators_;
-  scoped_array<scoped_ptr<ExtensionGenerator> > extension_generators_;
-
-  // E.g. if the package is foo.bar, package_parts_ is {"foo", "bar"}.
-  vector<string> package_parts_;
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(FileGenerator);
-};
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_FILE_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_generator.h b/tools/sdk/include/protobuf-c/protoc-c/c_generator.h
deleted file mode 100644
index f454710b36f..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_generator.h
+++ /dev/null
@@ -1,100 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-// Generates C code for a given .proto file.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_GENERATOR_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_GENERATOR_H__
-
-#include <string>
-#include <google/protobuf/compiler/code_generator.h>
-
-namespace google {
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-// CodeGenerator implementation which generates a C++ source file and
-// header.  If you create your own protocol compiler binary and you want
-// it to support C++ output, you can do so by registering an instance of this
-// CodeGenerator with the CommandLineInterface in your main() function.
-class LIBPROTOC_EXPORT CGenerator : public CodeGenerator {
- public:
-  CGenerator();
-  ~CGenerator();
-
-  // implements CodeGenerator ----------------------------------------
-  bool Generate(const FileDescriptor* file,
-                const string& parameter,
-                OutputDirectory* output_directory,
-                string* error) const;
-
- private:
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(CGenerator);
-};
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_GENERATOR_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_helpers.h b/tools/sdk/include/protobuf-c/protoc-c/c_helpers.h
deleted file mode 100644
index 9dc8c5e859c..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_helpers.h
+++ /dev/null
@@ -1,197 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_HELPERS_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_HELPERS_H__
-
-#include <string>
-#include <vector>
-#include <sstream>
-#include <google/protobuf/descriptor.h>
-#include <google/protobuf/descriptor.pb.h>
-#include <google/protobuf/io/printer.h>
-
-namespace google {
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-// Returns the non-nested type name for the given type.  If "qualified" is
-// true, prefix the type with the full namespace.  For example, if you had:
-//   package foo.bar;
-//   message Baz { message Qux {} }
-// Then the qualified ClassName for Qux would be:
-//   Foo__Bar__Baz_Qux
-// While the non-qualified version would be:
-//   Baz_Qux
-string ClassName(const Descriptor* descriptor, bool qualified);
-string ClassName(const EnumDescriptor* enum_descriptor, bool qualified);
-
-// --- Borrowed from stubs. ---
-template <typename T> string SimpleItoa(T n) {
-  std::stringstream stream;
-  stream << n;
-  return stream.str();
-}
-
-string SimpleFtoa(float f);
-string SimpleDtoa(double f);
-void SplitStringUsing(const string &str, const char *delim, std::vector<string> *out);
-string CEscape(const string& src);
-string StringReplace(const string& s, const string& oldsub, const string& newsub, bool replace_all);
-inline bool HasSuffixString(const string& str, const string& suffix) { return str.size() >= suffix.size() && str.compare(str.size() - suffix.size(), suffix.size(), suffix) == 0; }
-inline string StripSuffixString(const string& str, const string& suffix) { if (HasSuffixString(str, suffix)) { return str.substr(0, str.size() - suffix.size()); } else { return str; } }
-char* FastHexToBuffer(int i, char* buffer);
-
-
-// Get the (unqualified) name that should be used for this field in C code.
-// The name is coerced to lower-case to emulate proto1 behavior.  People
-// should be using lowercase-with-underscores style for proto field names
-// anyway, so normally this just returns field->name().
-string FieldName(const FieldDescriptor* field);
-
-// Get macro string for deprecated field
-string FieldDeprecated(const FieldDescriptor* field);
-
-// Returns the scope where the field was defined (for extensions, this is
-// different from the message type to which the field applies).
-inline const Descriptor* FieldScope(const FieldDescriptor* field) {
-  return field->is_extension() ?
-    field->extension_scope() : field->containing_type();
-}
-
-// convert a CamelCase class name into an all uppercase affair
-// with underscores separating words, e.g. MyClass becomes MY_CLASS.
-string CamelToUpper(const string &class_name);
-string CamelToLower(const string &class_name);
-
-// lowercased, underscored name to camel case
-string ToCamel(const string &name);
-
-// lowercase the string
-string ToLower(const string &class_name);
-string ToUpper(const string &class_name);
-
-// full_name() to lowercase with underscores
-string FullNameToLower(const string &full_name);
-string FullNameToUpper(const string &full_name);
-
-// full_name() to c-typename (with underscores for packages, otherwise camel case)
-string FullNameToC(const string &class_name);
-
-// Splits, indents, formats, and prints comment lines
-void PrintComment (io::Printer* printer, string comment);
-
-// make a string of spaces as long as input
-string ConvertToSpaces(const string &input);
-
-// Strips ".proto" or ".protodevel" from the end of a filename.
-string StripProto(const string& filename);
-
-// Get the C++ type name for a primitive type (e.g. "double", "::google::protobuf::int32", etc.).
-// Note:  non-built-in type names will be qualified, meaning they will start
-// with a ::.  If you are using the type as a template parameter, you will
-// need to insure there is a space between the < and the ::, because the
-// ridiculous C++ standard defines "<:" to be a synonym for "[".
-const char* PrimitiveTypeName(FieldDescriptor::CppType type);
-
-// Get the declared type name in CamelCase format, as is used e.g. for the
-// methods of WireFormat.  For example, TYPE_INT32 becomes "Int32".
-const char* DeclaredTypeMethodName(FieldDescriptor::Type type);
-
-// Convert a file name into a valid identifier.
-string FilenameIdentifier(const string& filename);
-
-// Return the name of the BuildDescriptors() function for a given file.
-string GlobalBuildDescriptorsName(const string& filename);
-
-// return 'required', 'optional', or 'repeated'
-string GetLabelName(FieldDescriptor::Label label);
-
-
-// write IntRanges entries for a bunch of sorted values.
-// returns the number of ranges there are to bsearch.
-unsigned WriteIntRanges(io::Printer* printer, int n_values, const int *values, const string &name);
-
-struct NameIndex
-{
-  unsigned index;
-  const char *name;
-};
-int compare_name_indices_by_name(const void*, const void*);
-
-// Return the syntax version of the file containing the field.
-// This wrapper is needed to be able to compile against protobuf2.
-inline int FieldSyntax(const FieldDescriptor* field) {
-#ifdef HAVE_PROTO3
-  return field->file()->syntax() == FileDescriptor::SYNTAX_PROTO3 ? 3 : 2;
-#else
-  return 2;
-#endif
-}
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_HELPERS_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_message.h b/tools/sdk/include/protobuf-c/protoc-c/c_message.h
deleted file mode 100644
index 8b115d1c8cb..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_message.h
+++ /dev/null
@@ -1,141 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_MESSAGE_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_MESSAGE_H__
-
-#include <string>
-#include <google/protobuf/stubs/common.h>
-#include <protoc-c/c_field.h>
-
-namespace google {
-namespace protobuf {
-  namespace io {
-    class Printer;             // printer.h
-  }
-}
-
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class EnumGenerator;           // enum.h
-class ExtensionGenerator;      // extension.h
-
-class MessageGenerator {
- public:
-  // See generator.cc for the meaning of dllexport_decl.
-  explicit MessageGenerator(const Descriptor* descriptor,
-                            const string& dllexport_decl);
-  ~MessageGenerator();
-
-  // Header stuff.
-
-  // Generate typedef.
-  void GenerateStructTypedef(io::Printer* printer);
-
-  // Generate descriptor prototype
-  void GenerateDescriptorDeclarations(io::Printer* printer);
-
-  // Generate descriptor prototype
-  void GenerateClosureTypedef(io::Printer* printer);
-
-  // Generate definitions of all nested enums (must come before class
-  // definitions because those classes use the enums definitions).
-  void GenerateEnumDefinitions(io::Printer* printer);
-
-  // Generate definitions for this class and all its nested types.
-  void GenerateStructDefinition(io::Printer* printer);
-
-  // Generate __INIT macro for populating this structure
-  void GenerateStructStaticInitMacro(io::Printer* printer);
-
-  // Generate standard helper functions declarations for this message.
-  void GenerateHelperFunctionDeclarations(io::Printer* printer, bool is_submessage);
-
-  // Source file stuff.
-
-  // Generate code that initializes the global variable storing the message's
-  // descriptor.
-  void GenerateMessageDescriptor(io::Printer* printer);
-  void GenerateHelperFunctionDefinitions(io::Printer* printer, bool is_submessage);
-
- private:
-
-  string GetDefaultValueC(const FieldDescriptor *fd);
-
-  const Descriptor* descriptor_;
-  string dllexport_decl_;
-  FieldGeneratorMap field_generators_;
-  scoped_array<scoped_ptr<MessageGenerator> > nested_generators_;
-  scoped_array<scoped_ptr<EnumGenerator> > enum_generators_;
-  scoped_array<scoped_ptr<ExtensionGenerator> > extension_generators_;
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(MessageGenerator);
-};
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_MESSAGE_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_message_field.h b/tools/sdk/include/protobuf-c/protoc-c/c_message_field.h
deleted file mode 100644
index b059fb031b0..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_message_field.h
+++ /dev/null
@@ -1,97 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_MESSAGE_FIELD_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_MESSAGE_FIELD_H__
-
-#include <map>
-#include <string>
-#include <protoc-c/c_field.h>
-
-namespace google {
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class MessageFieldGenerator : public FieldGenerator {
- public:
-  explicit MessageFieldGenerator(const FieldDescriptor* descriptor);
-  ~MessageFieldGenerator();
-
-  // implements FieldGenerator ---------------------------------------
-  void GenerateStructMembers(io::Printer* printer) const;
-  void GenerateDescriptorInitializer(io::Printer* printer) const;
-  string GetDefaultValue(void) const;
-  void GenerateStaticInit(io::Printer* printer) const;
-
- private:
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(MessageFieldGenerator);
-};
-
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_MESSAGE_FIELD_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_primitive_field.h b/tools/sdk/include/protobuf-c/protoc-c/c_primitive_field.h
deleted file mode 100644
index 5ff254c5dd8..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_primitive_field.h
+++ /dev/null
@@ -1,96 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_PRIMITIVE_FIELD_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_PRIMITIVE_FIELD_H__
-
-#include <map>
-#include <string>
-#include <protoc-c/c_field.h>
-
-namespace google {
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class PrimitiveFieldGenerator : public FieldGenerator {
- public:
-  explicit PrimitiveFieldGenerator(const FieldDescriptor* descriptor);
-  ~PrimitiveFieldGenerator();
-
-  // implements FieldGenerator ---------------------------------------
-  void GenerateStructMembers(io::Printer* printer) const;
-  void GenerateDescriptorInitializer(io::Printer* printer) const;
-  string GetDefaultValue(void) const;
-  void GenerateStaticInit(io::Printer* printer) const;
-
- private:
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(PrimitiveFieldGenerator);
-};
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_PRIMITIVE_FIELD_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_service.h b/tools/sdk/include/protobuf-c/protoc-c/c_service.h
deleted file mode 100644
index 6f1798ca724..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_service.h
+++ /dev/null
@@ -1,112 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_SERVICE_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_SERVICE_H__
-
-#include <map>
-#include <string>
-#include <google/protobuf/descriptor.h>
-
-namespace google {
-namespace protobuf {
-  namespace io {
-    class Printer;             // printer.h
-  }
-}
-
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class ServiceGenerator {
- public:
-  // See generator.cc for the meaning of dllexport_decl.
-  explicit ServiceGenerator(const ServiceDescriptor* descriptor,
-                            const string& dllexport_decl);
-  ~ServiceGenerator();
-
-  // Header stuff.
-  void GenerateMainHFile(io::Printer* printer);
-  void GenerateVfuncs(io::Printer* printer);
-  void GenerateInitMacros(io::Printer* printer);
-  void GenerateDescriptorDeclarations(io::Printer* printer);
-  void GenerateCallersDeclarations(io::Printer* printer);
-
-  // Source file stuff.
-  void GenerateCFile(io::Printer* printer);
-  void GenerateServiceDescriptor(io::Printer* printer);
-  void GenerateInit(io::Printer* printer);
-  void GenerateCallersImplementations(io::Printer* printer);
-
-  const ServiceDescriptor* descriptor_;
-  std::map<string, string> vars_;
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(ServiceGenerator);
-};
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_SERVICE_H__
diff --git a/tools/sdk/include/protobuf-c/protoc-c/c_string_field.h b/tools/sdk/include/protobuf-c/protoc-c/c_string_field.h
deleted file mode 100644
index 68f0d25b7dd..00000000000
--- a/tools/sdk/include/protobuf-c/protoc-c/c_string_field.h
+++ /dev/null
@@ -1,100 +0,0 @@
-// Protocol Buffers - Google's data interchange format
-// Copyright 2008 Google Inc.  All rights reserved.
-// http://code.google.com/p/protobuf/
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//     * Neither the name of Google Inc. nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Author: kenton@google.com (Kenton Varda)
-//  Based on original Protocol Buffers design by
-//  Sanjay Ghemawat, Jeff Dean, and others.
-
-// Copyright (c) 2008-2013, Dave Benson.  All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met:
-//
-//     * Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-//     * Redistributions in binary form must reproduce the above
-// copyright notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-// Modified to implement C code by Dave Benson.
-
-#ifndef GOOGLE_PROTOBUF_COMPILER_C_STRING_FIELD_H__
-#define GOOGLE_PROTOBUF_COMPILER_C_STRING_FIELD_H__
-
-#include <map>
-#include <string>
-#include <protoc-c/c_field.h>
-
-namespace google {
-namespace protobuf {
-namespace compiler {
-namespace c {
-
-class StringFieldGenerator : public FieldGenerator {
- public:
-  explicit StringFieldGenerator(const FieldDescriptor* descriptor);
-  ~StringFieldGenerator();
-
-  // implements FieldGenerator ---------------------------------------
-  void GenerateStructMembers(io::Printer* printer) const;
-  void GenerateDescriptorInitializer(io::Printer* printer) const;
-  void GenerateDefaultValueDeclarations(io::Printer* printer) const;
-  void GenerateDefaultValueImplementations(io::Printer* printer) const;
-  string GetDefaultValue(void) const;
-  void GenerateStaticInit(io::Printer* printer) const;
-
- private:
-  std::map<string, string> variables_;
-
-  GOOGLE_DISALLOW_EVIL_CONSTRUCTORS(StringFieldGenerator);
-};
-
-
-}  // namespace c
-}  // namespace compiler
-}  // namespace protobuf
-
-}  // namespace google
-#endif  // GOOGLE_PROTOBUF_COMPILER_C_STRING_FIELD_H__
diff --git a/tools/sdk/include/protobuf-c/t/generated-code2/common-test-arrays.h b/tools/sdk/include/protobuf-c/t/generated-code2/common-test-arrays.h
deleted file mode 100644
index 1535d38e821..00000000000
--- a/tools/sdk/include/protobuf-c/t/generated-code2/common-test-arrays.h
+++ /dev/null
@@ -1,62 +0,0 @@
-
-/* data included from the c++ packed-data generator,
-   and from the c test code. */
-
-#define THOUSAND     1000
-#define MILLION      1000000
-#define BILLION      1000000000LL
-#define TRILLION     1000000000000LL
-#define QUADRILLION  1000000000000000LL
-#define QUINTILLION  1000000000000000000LL
-
-int32_t int32_arr0[2] = { -1, 1 };
-int32_t int32_arr1[5] = { 42, 666, -1123123, 0, 47 };
-int32_t int32_arr_min_max[2] = { INT32_MIN, INT32_MAX };
-
-uint32_t uint32_roundnumbers[4] = { BILLION, MILLION, 1, 0 };
-uint32_t uint32_0_max[2] = { 0, UINT32_MAX };
-
-int64_t int64_roundnumbers[15] = { -QUINTILLION, -QUADRILLION, -TRILLION,
-                                   -BILLION, -MILLION, -THOUSAND,
-                                   1,
-                                   THOUSAND, MILLION, BILLION,
-                                   TRILLION, QUADRILLION, QUINTILLION };
-int64_t int64_min_max[2] = { INT64_MIN, INT64_MAX };
-
-uint64_t uint64_roundnumbers[9] = { 1,
-                                   THOUSAND, MILLION, BILLION,
-                                   TRILLION, QUADRILLION, QUINTILLION };
-uint64_t uint64_0_1_max[3] = { 0, 1, UINT64_MAX };
-uint64_t uint64_random[] = {0,
-                          666,
-                          4200000000ULL,
-                          16ULL * (uint64_t) QUINTILLION + 33 };
-
-#define FLOATING_POINT_RANDOM \
--1000.0, -100.0, -42.0, 0, 666, 131313
-float float_random[] = { FLOATING_POINT_RANDOM };
-double double_random[] = { FLOATING_POINT_RANDOM };
-
-protobuf_c_boolean boolean_0[]  = {0 };
-protobuf_c_boolean boolean_1[]  = {1 };
-protobuf_c_boolean boolean_random[] = {0,1,1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,1,0,1,1,0,1,1,0 };
-
-TEST_ENUM_SMALL_TYPE_NAME enum_small_0[] = { TEST_ENUM_SMALL(VALUE) };
-TEST_ENUM_SMALL_TYPE_NAME enum_small_1[] = { TEST_ENUM_SMALL(OTHER_VALUE) };
-#define T(v) (TEST_ENUM_SMALL_TYPE_NAME)(v)
-TEST_ENUM_SMALL_TYPE_NAME enum_small_random[] = {T(0),T(1),T(1),T(0),T(0),T(1),T(1),T(1),T(0),T(0),T(0),T(0),T(0),T(1),T(1),T(1),T(1),T(1),T(1),T(0),T(1),T(1),T(0),T(1),T(1),T(0) };
-#undef T
-
-#define T(v) (TEST_ENUM_TYPE_NAME)(v)
-TEST_ENUM_TYPE_NAME enum_0[] = { T(0) };
-TEST_ENUM_TYPE_NAME enum_1[] = { T(1) };
-TEST_ENUM_TYPE_NAME enum_random[] = { 
-   T(0), T(268435455), T(127), T(16384), T(16383),
-   T(2097152), T(2097151), T(128), T(268435456),
-   T(0), T(2097152), T(268435455), T(127), T(16383), T(16384) };
-#undef T
-
-char *repeated_strings_0[] = { (char*)"onestring" };
-char *repeated_strings_1[] = { (char*)"two", (char*)"string" };
-char *repeated_strings_2[] = { (char*)"many", (char*)"tiny", (char*)"little", (char*)"strings", (char*)"should", (char*)"be", (char*)"handled" };
-char *repeated_strings_3[] = { (char*)"one very long strings XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" };
diff --git a/tools/sdk/include/protocomm/protocomm.h b/tools/sdk/include/protocomm/protocomm.h
deleted file mode 100644
index 239d71390b2..00000000000
--- a/tools/sdk/include/protocomm/protocomm.h
+++ /dev/null
@@ -1,235 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <protocomm_security.h>
-#include <esp_err.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Function prototype for protocomm endpoint handler
- */
-typedef esp_err_t (*protocomm_req_handler_t)(
-    uint32_t        session_id, /*!< Session ID for identifying protocomm client */
-    const uint8_t  *inbuf,      /*!< Pointer to user provided input data buffer */
-    ssize_t         inlen,      /*!< Length o the input buffer */
-    uint8_t       **outbuf,     /*!< Pointer to output buffer allocated by handler */
-    ssize_t        *outlen,     /*!< Length of the allocated output buffer */
-    void           *priv_data   /*!< Private data passed to the handler (NULL if not used) */
-);
-
-/**
- * @brief   This structure corresponds to a unique instance of protocomm
- *          returned when the API `protocomm_new()` is called. The remaining
- *          Protocomm APIs require this object as the first parameter.
- *
- * @note    Structure of the protocomm object is kept private
- */
-typedef struct protocomm protocomm_t;
-
-/**
- * @brief   Create a new protocomm instance
- *
- * This API will return a new dynamically allocated protocomm instance
- * with all elements of the protocomm_t structure initialized to NULL.
- *
- * @return
- *  - protocomm_t* : On success
- *  - NULL : No memory for allocating new instance
- */
-protocomm_t *protocomm_new();
-
-/**
- * @brief   Delete a protocomm instance
- *
- * This API will deallocate a protocomm instance that was created
- * using `protocomm_new()`.
- *
- * @param[in] pc    Pointer to the protocomm instance to be deleted
- */
-void protocomm_delete(protocomm_t *pc);
-
-/**
- * @brief   Add endpoint request handler for a protocomm instance
- *
- * This API will bind an endpoint handler function to the specified
- * endpoint name, along with any private data that needs to be pass to
- * the handler at the time of call.
- *
- * @note
- *  - An endpoint must be bound to a valid protocomm instance,
- *    created using `protocomm_new()`.
- *  - This function internally calls the registered `add_endpoint()`
- *    function of the selected transport which is a member of the
- *    protocomm_t instance structure.
- *
- * @param[in] pc        Pointer to the protocomm instance
- * @param[in] ep_name   Endpoint identifier(name) string
- * @param[in] h         Endpoint handler function
- * @param[in] priv_data Pointer to private data to be passed as a
- *                      parameter to the handler function on call.
- *                      Pass NULL if not needed.
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_FAIL : Error adding endpoint / Endpoint with this name already exists
- *  - ESP_ERR_NO_MEM : Error allocating endpoint resource
- *  - ESP_ERR_INVALID_ARG : Null instance/name/handler arguments
- */
-esp_err_t protocomm_add_endpoint(protocomm_t *pc, const char *ep_name,
-                                 protocomm_req_handler_t h, void *priv_data);
-
-/**
- * @brief   Remove endpoint request handler for a protocomm instance
- *
- * This API will remove a registered endpoint handler identified by
- * an endpoint name.
- *
- * @note
- *  - This function internally calls the registered `remove_endpoint()`
- *    function which is a member of the protocomm_t instance structure.
- *
- * @param[in] pc        Pointer to the protocomm instance
- * @param[in] ep_name   Endpoint identifier(name) string
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_ERR_NOT_FOUND : Endpoint with specified name doesn't exist
- *  - ESP_ERR_INVALID_ARG : Null instance/name arguments
- */
-esp_err_t protocomm_remove_endpoint(protocomm_t *pc, const char *ep_name);
-
-/**
- * @brief   Calls the registered handler of an endpoint session
- *          for processing incoming data and generating the response
- *
- * @note
- *  - An endpoint must be bound to a valid protocomm instance,
- *    created using `protocomm_new()`.
- *  - Resulting output buffer must be deallocated by the caller.
- *
- * @param[in]  pc         Pointer to the protocomm instance
- * @param[in]  ep_name    Endpoint identifier(name) string
- * @param[in]  session_id Unique ID for a communication session
- * @param[in]  inbuf      Input buffer contains input request data which is to be
- *                        processed by the registered handler
- * @param[in]  inlen      Length of the input buffer
- * @param[out] outbuf     Pointer to internally allocated output buffer,
- *                        where the resulting response data output from
- *                        the registered handler is to be stored
- * @param[out] outlen     Buffer length of the allocated output buffer
- *
- * @return
- *  - ESP_OK : Request handled successfully
- *  - ESP_FAIL : Internal error in execution of registered handler
- *  - ESP_ERR_NO_MEM : Error allocating internal resource
- *  - ESP_ERR_NOT_FOUND : Endpoint with specified name doesn't exist
- *  - ESP_ERR_INVALID_ARG : Null instance/name arguments
- */
-esp_err_t protocomm_req_handle(protocomm_t *pc, const char *ep_name, uint32_t session_id,
-                               const uint8_t *inbuf, ssize_t inlen,
-                               uint8_t **outbuf, ssize_t *outlen);
-
-/**
- * @brief   Add endpoint security for a protocomm instance
- *
- * This API will bind a security session establisher to the specified
- * endpoint name, along with any proof of possession that may be required
- * for authenticating a session client.
- *
- * @note
- *  - An endpoint must be bound to a valid protocomm instance,
- *    created using `protocomm_new()`.
- *  - The choice of security can be any `protocomm_security_t` instance.
- *    Choices `protocomm_security0` and `protocomm_security1` are readily available.
- *
- * @param[in] pc        Pointer to the protocomm instance
- * @param[in] ep_name   Endpoint identifier(name) string
- * @param[in] sec       Pointer to endpoint security instance
- * @param[in] pop       Pointer to proof of possession for authenticating a client
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_FAIL : Error adding endpoint / Endpoint with this name already exists
- *  - ESP_ERR_INVALID_STATE : Security endpoint already set
- *  - ESP_ERR_NO_MEM : Error allocating endpoint resource
- *  - ESP_ERR_INVALID_ARG : Null instance/name/handler arguments
- */
-esp_err_t protocomm_set_security(protocomm_t *pc, const char *ep_name,
-                                 const protocomm_security_t *sec,
-                                 const protocomm_security_pop_t *pop);
-
-/**
- * @brief   Remove endpoint security for a protocomm instance
- *
- * This API will remove a registered security endpoint identified by
- * an endpoint name.
- *
- * @param[in] pc        Pointer to the protocomm instance
- * @param[in] ep_name   Endpoint identifier(name) string
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_ERR_NOT_FOUND : Endpoint with specified name doesn't exist
- *  - ESP_ERR_INVALID_ARG : Null instance/name arguments
- */
-esp_err_t protocomm_unset_security(protocomm_t *pc, const char *ep_name);
-
-/**
- * @brief   Set endpoint for version verification
- *
- * This API can be used for setting an application specific protocol
- * version which can be verified by clients through the endpoint.
- *
- * @note
- *  - An endpoint must be bound to a valid protocomm instance,
- *    created using `protocomm_new()`.
-
- * @param[in] pc        Pointer to the protocomm instance
- * @param[in] ep_name   Endpoint identifier(name) string
- * @param[in] version   Version identifier(name) string
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_FAIL : Error adding endpoint / Endpoint with this name already exists
- *  - ESP_ERR_INVALID_STATE : Version endpoint already set
- *  - ESP_ERR_NO_MEM : Error allocating endpoint resource
- *  - ESP_ERR_INVALID_ARG : Null instance/name/handler arguments
- */
-esp_err_t protocomm_set_version(protocomm_t *pc, const char *ep_name,
-                                const char *version);
-
-/**
- * @brief   Remove version verification endpoint from a protocomm instance
- *
- * This API will remove a registered version endpoint identified by
- * an endpoint name.
- *
- * @param[in] pc        Pointer to the protocomm instance
- * @param[in] ep_name   Endpoint identifier(name) string
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_ERR_NOT_FOUND : Endpoint with specified name doesn't exist
- *  - ESP_ERR_INVALID_ARG : Null instance/name arguments
- */
-esp_err_t protocomm_unset_version(protocomm_t *pc, const char *ep_name);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/protocomm/protocomm_ble.h b/tools/sdk/include/protocomm/protocomm_ble.h
deleted file mode 100644
index 92714444f0e..00000000000
--- a/tools/sdk/include/protocomm/protocomm_ble.h
+++ /dev/null
@@ -1,111 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <esp_gap_ble_api.h>
-
-#include <protocomm.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * BLE device name cannot be larger than this value
- * 31 bytes (max scan response size) - 1 byte (length) - 1 byte (type) = 29 bytes
- */
-#define MAX_BLE_DEVNAME_LEN   (ESP_BLE_SCAN_RSP_DATA_LEN_MAX - 2)
-
-/**
- * @brief   This structure maps handler required by protocomm layer to
- *          UUIDs which are used to uniquely identify BLE characteristics
- *          from a smartphone or a similar client device.
- */
-typedef struct name_uuid {
-    /**
-     * Name of the handler, which is passed to protocomm layer
-     */
-    const char *name;
-
-    /**
-     * UUID to be assigned to the BLE characteristic which is
-     * mapped to the handler
-     */
-    uint16_t uuid;
-} protocomm_ble_name_uuid_t;
-
-/**
- * @brief   Config parameters for protocomm BLE service
- */
-typedef struct {
-    /**
-     * BLE device name being broadcast at the time of provisioning
-     */
-    char         device_name[MAX_BLE_DEVNAME_LEN];
-
-    /**
-     * 128 bit UUID of the provisioning service
-     */
-    uint8_t      service_uuid[ESP_UUID_LEN_128];
-
-    /**
-     * Number of entries in the Name-UUID lookup table
-     */
-    ssize_t      nu_lookup_count;
-
-    /**
-     * Pointer to the Name-UUID lookup table
-     */
-    protocomm_ble_name_uuid_t *nu_lookup;
-} protocomm_ble_config_t;
-
-/**
- * @brief   Start Bluetooth Low Energy based transport layer for provisioning
- *
- * Initialize and start required BLE service for provisioning. This includes
- * the initialization for characteristics/service for BLE.
- *
- * @param[in] pc        Protocomm instance pointer obtained from protocomm_new()
- * @param[in] config    Pointer to config structure for initializing BLE
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_FAIL : Simple BLE start error
- *  - ESP_ERR_NO_MEM : Error allocating memory for internal resources
- *  - ESP_ERR_INVALID_STATE : Error in ble config
- *  - ESP_ERR_INVALID_ARG : Null arguments
- */
-esp_err_t protocomm_ble_start(protocomm_t *pc, const protocomm_ble_config_t *config);
-
-/**
- * @brief   Stop Bluetooth Low Energy based transport layer for provisioning
- *
- * Stops service/task responsible for BLE based interactions for provisioning
- *
- * @note    You might want to optionally reclaim memory from Bluetooth.
- *          Refer to the documentation of `esp_bt_mem_release` in that case.
- *
- * @param[in] pc    Same protocomm instance that was passed to protocomm_ble_start()
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_FAIL : Simple BLE stop error
- *  - ESP_ERR_INVALID_ARG : Null / incorrect protocomm instance
- */
-esp_err_t protocomm_ble_stop(protocomm_t *pc);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/protocomm/protocomm_console.h b/tools/sdk/include/protocomm/protocomm_console.h
deleted file mode 100644
index 767bcd7ca01..00000000000
--- a/tools/sdk/include/protocomm/protocomm_console.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <protocomm.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define PROTOCOMM_CONSOLE_DEFAULT_CONFIG() { \
-    .stack_size     = 4096,                  \
-    .task_priority  = tskIDLE_PRIORITY + 3,  \
-}
-
-/**
- * @brief   Config parameters for protocomm console
- */
-typedef struct {
-    size_t   stack_size;        /*!< Stack size of console task */
-    unsigned task_priority;     /*!< Priority of console task */
-} protocomm_console_config_t;
-
-/**
- * @brief   Start console based protocomm transport
- *
- * @note    This is a singleton. ie. Protocomm can have multiple instances, but only
- *          one instance can be bound to a console based transport layer.
- *
- * @param[in] pc     Protocomm instance pointer obtained from protocomm_new()
- * @param[in] config Config param structure for protocomm console
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_NOT_SUPPORTED : Transport layer bound to another protocomm instance
- *  - ESP_ERR_INVALID_STATE : Transport layer already bound to this protocomm instance
- *  - ESP_FAIL : Failed to start console thread
- */
-esp_err_t protocomm_console_start(protocomm_t *pc, const protocomm_console_config_t *config);
-
-/**
- * @brief   Stop console protocomm transport
- *
- * @param[in] pc    Same protocomm instance that was passed to protocomm_console_start()
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_ERR_INVALID_ARG : Null / incorrect protocomm instance pointer
- */
-esp_err_t protocomm_console_stop(protocomm_t *pc);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/protocomm/protocomm_httpd.h b/tools/sdk/include/protocomm/protocomm_httpd.h
deleted file mode 100644
index 2baf7545512..00000000000
--- a/tools/sdk/include/protocomm/protocomm_httpd.h
+++ /dev/null
@@ -1,107 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <protocomm.h>
-
-#define PROTOCOMM_HTTPD_DEFAULT_CONFIG() {   \
-    .port           = 80,                    \
-    .stack_size     = 4096,                  \
-    .task_priority  = tskIDLE_PRIORITY + 5,  \
-}
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   Config parameters for protocomm HTTP server
- */
-typedef struct {
-
-    uint16_t port;          /*!< Port on which the HTTP server will listen */
-
-    /**
-     * Stack size of server task, adjusted depending
-     * upon stack usage of endpoint handler
-     */
-    size_t   stack_size;
-    unsigned task_priority; /*!< Priority of server task */
-} protocomm_http_server_config_t; /*!< HTTP Server Configuration, if HTTP Server has not been started already */
-
-/** Protocomm HTTPD Configuration Data
- */
-typedef union {
-    /** HTTP Server Handle, if ext_handle_provided is set to true
-     */
-    void *handle;
-
-    /** HTTP Server Configuration, if a server is not already active
-     */
-    protocomm_http_server_config_t config;
-} protocomm_httpd_config_data_t;
-
-/**
- * @brief   Config parameters for protocomm HTTP server
- */
-typedef struct {
-    /** Flag to indicate of an external HTTP Server Handle has been provided.
-     * In such as case, protocomm will use the same HTTP Server and not start
-     * a new one internally.
-     */
-    bool ext_handle_provided;
-    /** Protocomm HTTPD Configuration Data */
-    protocomm_httpd_config_data_t data;
-} protocomm_httpd_config_t;
-
-/**
- * @brief   Start HTTPD protocomm transport
- *
- * This API internally creates a framework to allow endpoint registration and security
- * configuration for the protocomm.
- *
- * @note    This is a singleton. ie. Protocomm can have multiple instances, but only
- *          one instance can be bound to an HTTP transport layer.
- *
- * @param[in] pc        Protocomm instance pointer obtained from protocomm_new()
- * @param[in] config    Pointer to config structure for initializing HTTP server
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_ERR_INVALID_ARG : Null arguments
- *  - ESP_ERR_NOT_SUPPORTED : Transport layer bound to another protocomm instance
- *  - ESP_ERR_INVALID_STATE : Transport layer already bound to this protocomm instance
- *  - ESP_ERR_NO_MEM : Memory allocation for server resource failed
- *  - ESP_ERR_HTTPD_* : HTTP server error on start
- */
-esp_err_t protocomm_httpd_start(protocomm_t *pc, const protocomm_httpd_config_t *config);
-
-/**
- * @brief   Stop HTTPD protocomm transport
- *
- * This API cleans up the HTTPD transport protocomm and frees all the handlers registered
- * with the protocomm.
- *
- * @param[in] pc    Same protocomm instance that was passed to protocomm_httpd_start()
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_ERR_INVALID_ARG : Null / incorrect protocomm instance pointer
- */
-esp_err_t protocomm_httpd_stop(protocomm_t *pc);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/protocomm/protocomm_security.h b/tools/sdk/include/protocomm/protocomm_security.h
deleted file mode 100644
index 28f43a65742..00000000000
--- a/tools/sdk/include/protocomm/protocomm_security.h
+++ /dev/null
@@ -1,101 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <esp_err.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   Proof Of Possession for authenticating a secure session
- */
-typedef struct protocomm_security_pop {
-    /**
-     * Pointer to buffer containing the proof of possession data
-     */
-    const uint8_t *data;
-
-    /**
-     * Length (in bytes) of the proof of possession data
-     */
-    uint16_t len;
-} protocomm_security_pop_t;
-
-/**
- * @brief   Protocomm security object structure.
- *
- * The member functions are used for implementing secure
- * protocomm sessions.
- *
- * @note    This structure should not have any dynamic
- *          members to allow re-entrancy
- */
-typedef struct protocomm_security {
-    /**
-     * Unique version number of security implementation
-     */
-    int ver;
-
-    /**
-     * Function for initializing/allocating security
-     * infrastructure
-     */
-    esp_err_t (*init)();
-
-    /**
-     * Function for deallocating security infrastructure
-     */
-    esp_err_t (*cleanup)();
-
-    /**
-     * Starts new secure transport session with specified ID
-     */
-    esp_err_t (*new_transport_session)(uint32_t session_id);
-
-    /**
-     * Closes a secure transport session with specified ID
-     */
-    esp_err_t (*close_transport_session)(uint32_t session_id);
-
-    /**
-     * Handler function for authenticating connection
-     * request and establishing secure session
-     */
-    esp_err_t (*security_req_handler)(const protocomm_security_pop_t *pop,
-                                      uint32_t session_id,
-                                      const uint8_t *inbuf, ssize_t inlen,
-                                      uint8_t **outbuf, ssize_t *outlen,
-                                      void *priv_data);
-
-    /**
-     * Function which implements the encryption algorithm
-     */
-    esp_err_t (*encrypt)(uint32_t session_id,
-                         const uint8_t *inbuf, ssize_t inlen,
-                         uint8_t *outbuf, ssize_t *outlen);
-
-    /**
-     * Function which implements the decryption algorithm
-     */
-    esp_err_t (*decrypt)(uint32_t session_id,
-                         const uint8_t *inbuf, ssize_t inlen,
-                         uint8_t *outbuf, ssize_t *outlen);
-} protocomm_security_t;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/protocomm/protocomm_security0.h b/tools/sdk/include/protocomm/protocomm_security0.h
deleted file mode 100644
index 9ae8744d470..00000000000
--- a/tools/sdk/include/protocomm/protocomm_security0.h
+++ /dev/null
@@ -1,33 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <protocomm_security.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   Protocomm security version 0 implementation
- *
- * This is a simple implementation to be used when no
- * security is required for the protocomm instance
- */
-extern const protocomm_security_t protocomm_security0;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/protocomm/protocomm_security1.h b/tools/sdk/include/protocomm/protocomm_security1.h
deleted file mode 100644
index 12a05c322aa..00000000000
--- a/tools/sdk/include/protocomm/protocomm_security1.h
+++ /dev/null
@@ -1,33 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <protocomm_security.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   Protocomm security version 1 implementation
- *
- * This is a full fledged security implementation using
- * Curve25519 key exchange and AES-256-CTR encryption
- */
-extern const protocomm_security_t protocomm_security1;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/pthread/esp_pthread.h b/tools/sdk/include/pthread/esp_pthread.h
deleted file mode 100644
index 76f45a32abd..00000000000
--- a/tools/sdk/include/pthread/esp_pthread.h
+++ /dev/null
@@ -1,87 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "esp_err.h"
-#include <freertos/FreeRTOSConfig.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef PTHREAD_STACK_MIN
-#define PTHREAD_STACK_MIN    CONFIG_PTHREAD_STACK_MIN
-#endif
-
-/** pthread configuration structure that influences pthread creation */
-typedef struct {
-    size_t stack_size;  ///< The stack size of the pthread
-    size_t prio;        ///< The thread's priority
-    bool inherit_cfg;   ///< Inherit this configuration further
-    const char* thread_name;  ///< The thread name.
-    int pin_to_core;    ///< The core id to pin the thread to. Has the same value range as xCoreId argument of xTaskCreatePinnedToCore.
-} esp_pthread_cfg_t;
-
-/**
- * @brief Creates a default pthread configuration based
- * on the values set via menuconfig.
- * 
- * @return
- *      A default configuration structure.
- */
-esp_pthread_cfg_t esp_pthread_get_default_config();
-
-/**
- * @brief Configure parameters for creating pthread
- *
- * This API allows you to configure how the subsequent
- * pthread_create() call will behave. This call can be used to setup
- * configuration parameters like stack size, priority, configuration
- * inheritance etc.
- *
- * If the 'inherit' flag in the configuration structure is enabled,
- * then the same configuration is also inherited in the thread
- * subtree.
- *
- * @note Passing non-NULL attributes to pthread_create() will override
- *       the stack_size parameter set using this API
- *
- * @param cfg The pthread config parameters
- *
- * @return
- *      - ESP_OK if configuration was successfully set
- *      - ESP_ERR_NO_MEM if out of memory
- *      - ESP_ERR_INVALID_ARG if stack_size is less than PTHREAD_STACK_MIN
- */
-esp_err_t esp_pthread_set_cfg(const esp_pthread_cfg_t *cfg);
-
-/**
- * @brief Get current pthread creation configuration
- *
- * This will retrieve the current configuration that will be used for
- * creating threads.
- *
- * @param p Pointer to the pthread config structure that will be
- * updated with the currently configured parameters
- *
- * @return
- *      - ESP_OK if the configuration was available
- *      - ESP_ERR_NOT_FOUND if a configuration wasn't previously set
- */
-esp_err_t esp_pthread_get_cfg(esp_pthread_cfg_t *p);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/sdmmc/sdmmc_cmd.h b/tools/sdk/include/sdmmc/sdmmc_cmd.h
deleted file mode 100644
index aa12a4477a4..00000000000
--- a/tools/sdk/include/sdmmc/sdmmc_cmd.h
+++ /dev/null
@@ -1,225 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <stdio.h>
-#include "esp_err.h"
-#include "driver/sdmmc_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Probe and initialize SD/MMC card using given host
- *
- * @note Only SD cards (SDSC and SDHC/SDXC) are supported now.
- *       Support for MMC/eMMC cards will be added later.
- *
- * @param host  pointer to structure defining host controller
- * @param out_card  pointer to structure which will receive information
- *                  about the card when the function completes
- * @return
- *      - ESP_OK on success
- *      - One of the error codes from SDMMC host controller
- */
-esp_err_t sdmmc_card_init(const sdmmc_host_t* host,
-        sdmmc_card_t* out_card);
-
-/**
- * @brief Print information about the card to a stream
- * @param stream  stream obtained using fopen or fdopen
- * @param card  card information structure initialized using sdmmc_card_init
- */
-void sdmmc_card_print_info(FILE* stream, const sdmmc_card_t* card);
-
-/**
- * Write given number of sectors to SD/MMC card
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @param src   pointer to data buffer to read data from; data size must be
- *              equal to sector_count * card->csd.sector_size
- * @param start_sector  sector where to start writing
- * @param sector_count  number of sectors to write
- * @return
- *      - ESP_OK on success
- *      - One of the error codes from SDMMC host controller
- */
-esp_err_t sdmmc_write_sectors(sdmmc_card_t* card, const void* src,
-        size_t start_sector, size_t sector_count);
-
-/**
- * Write given number of sectors to SD/MMC card
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @param dst   pointer to data buffer to write into; buffer size must be
- *              at least sector_count * card->csd.sector_size
- * @param start_sector  sector where to start reading
- * @param sector_count  number of sectors to read
- * @return
- *      - ESP_OK on success
- *      - One of the error codes from SDMMC host controller
- */
-esp_err_t sdmmc_read_sectors(sdmmc_card_t* card, void* dst,
-        size_t start_sector, size_t sector_count);
-
-/**
- * Read one byte from an SDIO card using IO_RW_DIRECT (CMD52)
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @param function  IO function number
- * @param reg  byte address within IO function
- * @param[out] out_byte  output, receives the value read from the card
- * @return
- *      - ESP_OK on success
- *      - One of the error codes from SDMMC host controller
- */
-esp_err_t sdmmc_io_read_byte(sdmmc_card_t* card, uint32_t function,
-        uint32_t reg, uint8_t *out_byte);
-
-/**
- * Write one byte to an SDIO card using IO_RW_DIRECT (CMD52)
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @param function  IO function number
- * @param reg  byte address within IO function
- * @param in_byte  value to be written
- * @param[out] out_byte  if not NULL, receives new byte value read
- *                       from the card (read-after-write).
- * @return
- *      - ESP_OK on success
- *      - One of the error codes from SDMMC host controller
- */
-esp_err_t sdmmc_io_write_byte(sdmmc_card_t* card, uint32_t function,
-        uint32_t reg, uint8_t in_byte, uint8_t* out_byte);
-
-/**
- * Read multiple bytes from an SDIO card using IO_RW_EXTENDED (CMD53)
- *
- * This function performs read operation using CMD53 in byte mode.
- * For block mode, see sdmmc_io_read_blocks.
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @param function  IO function number
- * @param addr  byte address within IO function where reading starts
- * @param dst  buffer which receives the data read from card
- * @param size  number of bytes to read
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_SIZE if size exceeds 512 bytes
- *      - One of the error codes from SDMMC host controller
- */
-esp_err_t sdmmc_io_read_bytes(sdmmc_card_t* card, uint32_t function,
-        uint32_t addr, void* dst, size_t size);
-
-/**
- * Write multiple bytes to an SDIO card using IO_RW_EXTENDED (CMD53)
- *
- * This function performs write operation using CMD53 in byte mode.
- * For block mode, see sdmmc_io_write_blocks.
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @param function  IO function number
- * @param addr  byte address within IO function where writing starts
- * @param src  data to be written
- * @param size  number of bytes to write
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_SIZE if size exceeds 512 bytes
- *      - One of the error codes from SDMMC host controller
- */
-esp_err_t sdmmc_io_write_bytes(sdmmc_card_t* card, uint32_t function,
-        uint32_t addr, const void* src, size_t size);
-
-/**
- * Read blocks of data from an SDIO card using IO_RW_EXTENDED (CMD53)
- *
- * This function performs read operation using CMD53 in block mode.
- * For byte mode, see sdmmc_io_read_bytes.
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @param function  IO function number
- * @param addr  byte address within IO function where writing starts
- * @param dst  buffer which receives the data read from card
- * @param size  number of bytes to read, must be divisible by the card block
- *              size.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_SIZE if size is not divisible by 512 bytes
- *      - One of the error codes from SDMMC host controller
- */
-esp_err_t sdmmc_io_read_blocks(sdmmc_card_t* card, uint32_t function,
-        uint32_t addr, void* dst, size_t size);
-
-/**
- * Write blocks of data to an SDIO card using IO_RW_EXTENDED (CMD53)
- *
- * This function performs write operation using CMD53 in block mode.
- * For byte mode, see sdmmc_io_write_bytes.
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @param function  IO function number
- * @param addr  byte address within IO function where writing starts
- * @param src  data to be written
- * @param size  number of bytes to read, must be divisible by the card block
- *              size.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_SIZE if size is not divisible by 512 bytes
- *      - One of the error codes from SDMMC host controller
- */
-esp_err_t sdmmc_io_write_blocks(sdmmc_card_t* card, uint32_t function,
-        uint32_t addr, const void* src, size_t size);
-
-/**
- * Enable SDIO interrupt in the SDMMC host
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NOT_SUPPORTED if the host controller does not support
- *        IO interrupts
- */
-esp_err_t sdmmc_io_enable_int(sdmmc_card_t* card);
-
-/**
- * Block until an SDIO interrupt is received
- *
- * Slave uses D1 line to signal interrupt condition to the host.
- * This function can be used to wait for the interrupt.
- *
- * @param card  pointer to card information structure previously initialized
- *              using sdmmc_card_init
- * @param timeout_ticks  time to wait for the interrupt, in RTOS ticks
- * @return
- *      - ESP_OK if the interrupt is received
- *      - ESP_ERR_NOT_SUPPORTED if the host controller does not support
- *        IO interrupts
- *      - ESP_ERR_TIMEOUT if the interrupt does not happen in timeout_ticks
- */
-esp_err_t sdmmc_io_wait_int(sdmmc_card_t* card, TickType_t timeout_ticks);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/smartconfig_ack/smartconfig_ack.h b/tools/sdk/include/smartconfig_ack/smartconfig_ack.h
deleted file mode 100644
index 39f7636ebdc..00000000000
--- a/tools/sdk/include/smartconfig_ack/smartconfig_ack.h
+++ /dev/null
@@ -1,76 +0,0 @@
-// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef SMARTCONFIG_ACK_H
-#define SMARTCONFIG_ACK_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SC_ACK_TASK_PRIORITY             2          /*!< Priority of sending smartconfig ACK task */
-#define SC_ACK_TASK_STACK_SIZE           2048       /*!< Stack size of sending smartconfig ACK task */
-
-#define SC_ACK_TOUCH_SERVER_PORT         18266      /*!< ESP touch UDP port of server on cellphone */
-#define SC_ACK_AIRKISS_SERVER_PORT       10000      /*!< Airkiss UDP port of server on cellphone */
-#define SC_ACK_AIRKISS_DEVICE_PORT       10001      /*!< Airkiss UDP port of server on device */
-#define SC_ACK_AIRKISS_TIMEOUT           1500       /*!< Airkiss read data timeout millisecond */
-
-#define SC_ACK_TOUCH_LEN                 11         /*!< Length of ESP touch ACK context */
-#define SC_ACK_AIRKISS_LEN               7          /*!< Length of Airkiss ACK context */
-
-#define SC_ACK_MAX_COUNT                 30         /*!< Maximum count of sending smartconfig ACK */
-
-/**
- * @brief Smartconfig ACK type.
- */
-typedef enum {
-    SC_ACK_TYPE_ESPTOUCH = 0,                       /*!< ESP touch ACK type */
-    SC_ACK_TYPE_AIRKISS,                            /*!< Airkiss ACK type */
-} sc_ack_type_t;
-
-/**
- * @brief Smartconfig parameters passed to sc_ack_send call.
- */
-typedef struct sc_ack {
-    sc_ack_type_t type;           /*!< Smartconfig ACK type */
-    uint8_t *link_flag;           /*!< Smartconfig link flag */
-    sc_callback_t cb;             /*!< Smartconfig callback function */
-    struct {
-        uint8_t token;            /*!< Smartconfig token to be sent */
-        uint8_t mac[6];           /*!< MAC address of station */
-        uint8_t ip[4];            /*!< IP address of cellphone */
-    } ctx;
-} sc_ack_t;
-
-/**
-  * @brief  Send smartconfig ACK to cellphone.
-  *
-  * @attention The API is only used in libsmartconfig.a.
-  *
-  * @param  param: smartconfig parameters;
-  */
-void sc_ack_send(sc_ack_t *param);
-
-/**
-  * @brief  Stop sending smartconfig ACK to cellphone.
-  *
-  * @attention The API is only used in libsmartconfig.a.
-  */
-void sc_ack_send_stop(void);
-
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/tools/sdk/include/soc/soc/adc_channel.h b/tools/sdk/include/soc/soc/adc_channel.h
deleted file mode 100644
index e8835d35f8f..00000000000
--- a/tools/sdk/include/soc/soc/adc_channel.h
+++ /dev/null
@@ -1,72 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_ADC_CHANNEL_H
-#define _SOC_ADC_CHANNEL_H
-
-#define ADC1_GPIO36_CHANNEL     ADC1_CHANNEL_0
-#define ADC1_CHANNEL_0_GPIO_NUM 36
-
-#define ADC1_GPIO37_CHANNEL     ADC1_CHANNEL_1
-#define ADC1_CHANNEL_1_GPIO_NUM 37
-
-#define ADC1_GPIO38_CHANNEL     ADC1_CHANNEL_2
-#define ADC1_CHANNEL_2_GPIO_NUM 38
-
-#define ADC1_GPIO39_CHANNEL     ADC1_CHANNEL_3
-#define ADC1_CHANNEL_3_GPIO_NUM 39
-
-#define ADC1_GPIO32_CHANNEL     ADC1_CHANNEL_4
-#define ADC1_CHANNEL_4_GPIO_NUM 32
-
-#define ADC1_GPIO33_CHANNEL     ADC1_CHANNEL_5
-#define ADC1_CHANNEL_5_GPIO_NUM 33
-
-#define ADC1_GPIO34_CHANNEL     ADC1_CHANNEL_6
-#define ADC1_CHANNEL_6_GPIO_NUM 34
-
-#define ADC1_GPIO35_CHANNEL     ADC1_CHANNEL_7
-#define ADC1_CHANNEL_7_GPIO_NUM 35
-
-#define ADC2_GPIO4_CHANNEL      ADC2_CHANNEL_0
-#define ADC2_CHANNEL_0_GPIO_NUM 4
-
-#define ADC2_GPIO0_CHANNEL      ADC2_CHANNEL_1
-#define ADC2_CHANNEL_1_GPIO_NUM 0
-
-#define ADC2_GPIO2_CHANNEL      ADC2_CHANNEL_2
-#define ADC2_CHANNEL_2_GPIO_NUM 2
-
-#define ADC2_GPIO15_CHANNEL     ADC2_CHANNEL_3
-#define ADC2_CHANNEL_3_GPIO_NUM 15
-
-#define ADC2_GPIO13_CHANNEL     ADC2_CHANNEL_4
-#define ADC2_CHANNEL_4_GPIO_NUM 13
-
-#define ADC2_GPIO12_CHANNEL     ADC2_CHANNEL_5
-#define ADC2_CHANNEL_5_GPIO_NUM 12
-
-#define ADC2_GPIO14_CHANNEL     ADC2_CHANNEL_6
-#define ADC2_CHANNEL_6_GPIO_NUM 14
-
-#define ADC2_GPIO27_CHANNEL     ADC2_CHANNEL_7
-#define ADC2_CHANNEL_7_GPIO_NUM 27
-
-#define ADC2_GPIO25_CHANNEL     ADC2_CHANNEL_8
-#define ADC2_CHANNEL_8_GPIO_NUM 25
-
-#define ADC2_GPIO26_CHANNEL     ADC2_CHANNEL_9
-#define ADC2_CHANNEL_9_GPIO_NUM 26
-
-#endif
diff --git a/tools/sdk/include/soc/soc/apb_ctrl_reg.h b/tools/sdk/include/soc/soc/apb_ctrl_reg.h
deleted file mode 100644
index 2e5ea54c4c7..00000000000
--- a/tools/sdk/include/soc/soc/apb_ctrl_reg.h
+++ /dev/null
@@ -1,294 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_APB_CTRL_REG_H_
-#define _SOC_APB_CTRL_REG_H_
-
-#include "soc.h"
-#define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x0)
-/* APB_CTRL_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_QUICK_CLK_CHNG  (BIT(13))
-#define APB_CTRL_QUICK_CLK_CHNG_M  (BIT(13))
-#define APB_CTRL_QUICK_CLK_CHNG_V  0x1
-#define APB_CTRL_QUICK_CLK_CHNG_S  13
-/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_RST_TICK_CNT  (BIT(12))
-#define APB_CTRL_RST_TICK_CNT_M  (BIT(12))
-#define APB_CTRL_RST_TICK_CNT_V  0x1
-#define APB_CTRL_RST_TICK_CNT_S  12
-/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_CLK_EN  (BIT(11))
-#define APB_CTRL_CLK_EN_M  (BIT(11))
-#define APB_CTRL_CLK_EN_V  0x1
-#define APB_CTRL_CLK_EN_S  11
-/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_CLK_320M_EN  (BIT(10))
-#define APB_CTRL_CLK_320M_EN_M  (BIT(10))
-#define APB_CTRL_CLK_320M_EN_V  0x1
-#define APB_CTRL_CLK_320M_EN_S  10
-/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define APB_CTRL_PRE_DIV_CNT  0x000003FF
-#define APB_CTRL_PRE_DIV_CNT_M  ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
-#define APB_CTRL_PRE_DIV_CNT_V  0x3FF
-#define APB_CTRL_PRE_DIV_CNT_S  0
-
-#define APB_CTRL_XTAL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x4)
-/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
-/*description: */
-#define APB_CTRL_XTAL_TICK_NUM  0x000000FF
-#define APB_CTRL_XTAL_TICK_NUM_M  ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
-#define APB_CTRL_XTAL_TICK_NUM_V  0xFF
-#define APB_CTRL_XTAL_TICK_NUM_S  0
-
-#define APB_CTRL_PLL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x8)
-/* APB_CTRL_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */
-/*description: */
-#define APB_CTRL_PLL_TICK_NUM  0x000000FF
-#define APB_CTRL_PLL_TICK_NUM_M  ((APB_CTRL_PLL_TICK_NUM_V)<<(APB_CTRL_PLL_TICK_NUM_S))
-#define APB_CTRL_PLL_TICK_NUM_V  0xFF
-#define APB_CTRL_PLL_TICK_NUM_S  0
-
-#define APB_CTRL_CK8M_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0xC)
-/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */
-/*description: */
-#define APB_CTRL_CK8M_TICK_NUM  0x000000FF
-#define APB_CTRL_CK8M_TICK_NUM_M  ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
-#define APB_CTRL_CK8M_TICK_NUM_V  0xFF
-#define APB_CTRL_CK8M_TICK_NUM_S  0
-
-#define APB_CTRL_APB_SARADC_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x10)
-/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1: I2S input data is from SAR ADC (for DMA)  0: I2S input data
- is from GPIO matrix*/
-#define APB_CTRL_SARADC_DATA_TO_I2S  (BIT(26))
-#define APB_CTRL_SARADC_DATA_TO_I2S_M  (BIT(26))
-#define APB_CTRL_SARADC_DATA_TO_I2S_V  0x1
-#define APB_CTRL_SARADC_DATA_TO_I2S_S  26
-/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
-  in this case the resolution should not be larger than 11 bits.*/
-#define APB_CTRL_SARADC_DATA_SAR_SEL  (BIT(25))
-#define APB_CTRL_SARADC_DATA_SAR_SEL_M  (BIT(25))
-#define APB_CTRL_SARADC_DATA_SAR_SEL_V  0x1
-#define APB_CTRL_SARADC_DATA_SAR_SEL_S  25
-/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
-#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR  (BIT(24))
-#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M  (BIT(24))
-#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V  0x1
-#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S  24
-/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
-#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR  (BIT(23))
-#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M  (BIT(23))
-#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V  0x1
-#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S  23
-/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
-/*description: 0 ~ 15 means length 1 ~ 16*/
-#define APB_CTRL_SARADC_SAR2_PATT_LEN  0x0000000F
-#define APB_CTRL_SARADC_SAR2_PATT_LEN_M  ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S))
-#define APB_CTRL_SARADC_SAR2_PATT_LEN_V  0xF
-#define APB_CTRL_SARADC_SAR2_PATT_LEN_S  19
-/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
-/*description: 0 ~ 15 means length 1 ~ 16*/
-#define APB_CTRL_SARADC_SAR1_PATT_LEN  0x0000000F
-#define APB_CTRL_SARADC_SAR1_PATT_LEN_M  ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S))
-#define APB_CTRL_SARADC_SAR1_PATT_LEN_V  0xF
-#define APB_CTRL_SARADC_SAR1_PATT_LEN_S  15
-/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
-/*description: SAR clock divider*/
-#define APB_CTRL_SARADC_SAR_CLK_DIV  0x000000FF
-#define APB_CTRL_SARADC_SAR_CLK_DIV_M  ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S))
-#define APB_CTRL_SARADC_SAR_CLK_DIV_V  0xFF
-#define APB_CTRL_SARADC_SAR_CLK_DIV_S  7
-/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_SARADC_SAR_CLK_GATED  (BIT(6))
-#define APB_CTRL_SARADC_SAR_CLK_GATED_M  (BIT(6))
-#define APB_CTRL_SARADC_SAR_CLK_GATED_V  0x1
-#define APB_CTRL_SARADC_SAR_CLK_GATED_S  6
-/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: 0: SAR1  1: SAR2  only work for single SAR mode*/
-#define APB_CTRL_SARADC_SAR_SEL  (BIT(5))
-#define APB_CTRL_SARADC_SAR_SEL_M  (BIT(5))
-#define APB_CTRL_SARADC_SAR_SEL_V  0x1
-#define APB_CTRL_SARADC_SAR_SEL_S  5
-/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
-/*description: 0: single mode  1: double mode  2: alternate mode*/
-#define APB_CTRL_SARADC_WORK_MODE  0x00000003
-#define APB_CTRL_SARADC_WORK_MODE_M  ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S))
-#define APB_CTRL_SARADC_WORK_MODE_V  0x3
-#define APB_CTRL_SARADC_WORK_MODE_S  3
-/* APB_CTRL_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */
-/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL  0: SAR ADC2 is controlled
- by PWDET CTRL*/
-#define APB_CTRL_SARADC_SAR2_MUX  (BIT(2))
-#define APB_CTRL_SARADC_SAR2_MUX_M  (BIT(2))
-#define APB_CTRL_SARADC_SAR2_MUX_V  0x1
-#define APB_CTRL_SARADC_SAR2_MUX_S  2
-/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_SARADC_START  (BIT(1))
-#define APB_CTRL_SARADC_START_M  (BIT(1))
-#define APB_CTRL_SARADC_START_V  0x1
-#define APB_CTRL_SARADC_START_S  1
-/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_SARADC_START_FORCE  (BIT(0))
-#define APB_CTRL_SARADC_START_FORCE_M  (BIT(0))
-#define APB_CTRL_SARADC_START_FORCE_V  0x1
-#define APB_CTRL_SARADC_START_FORCE_S  0
-
-#define APB_CTRL_APB_SARADC_CTRL2_REG          (DR_REG_APB_CTRL_BASE + 0x14)
-/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: 1: data to DIG ADC2 CTRL is inverted  otherwise not*/
-#define APB_CTRL_SARADC_SAR2_INV  (BIT(10))
-#define APB_CTRL_SARADC_SAR2_INV_M  (BIT(10))
-#define APB_CTRL_SARADC_SAR2_INV_V  0x1
-#define APB_CTRL_SARADC_SAR2_INV_S  10
-/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: 1: data to DIG ADC1 CTRL is inverted  otherwise not*/
-#define APB_CTRL_SARADC_SAR1_INV  (BIT(9))
-#define APB_CTRL_SARADC_SAR1_INV_M  (BIT(9))
-#define APB_CTRL_SARADC_SAR1_INV_V  0x1
-#define APB_CTRL_SARADC_SAR1_INV_S  9
-/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
-/*description: max conversion number*/
-#define APB_CTRL_SARADC_MAX_MEAS_NUM  0x000000FF
-#define APB_CTRL_SARADC_MAX_MEAS_NUM_M  ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S))
-#define APB_CTRL_SARADC_MAX_MEAS_NUM_V  0xFF
-#define APB_CTRL_SARADC_MAX_MEAS_NUM_S  1
-/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_SARADC_MEAS_NUM_LIMIT  (BIT(0))
-#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
-#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V  0x1
-#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S  0
-
-#define APB_CTRL_APB_SARADC_FSM_REG          (DR_REG_APB_CTRL_BASE + 0x18)
-/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
-/*description: sample cycles*/
-#define APB_CTRL_SARADC_SAMPLE_CYCLE  0x000000FF
-#define APB_CTRL_SARADC_SAMPLE_CYCLE_M  ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S))
-#define APB_CTRL_SARADC_SAMPLE_CYCLE_V  0xFF
-#define APB_CTRL_SARADC_SAMPLE_CYCLE_S  24
-/* APB_CTRL_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */
-/*description: */
-#define APB_CTRL_SARADC_START_WAIT  0x000000FF
-#define APB_CTRL_SARADC_START_WAIT_M  ((APB_CTRL_SARADC_START_WAIT_V)<<(APB_CTRL_SARADC_START_WAIT_S))
-#define APB_CTRL_SARADC_START_WAIT_V  0xFF
-#define APB_CTRL_SARADC_START_WAIT_S  16
-/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */
-/*description: */
-#define APB_CTRL_SARADC_STANDBY_WAIT  0x000000FF
-#define APB_CTRL_SARADC_STANDBY_WAIT_M  ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S))
-#define APB_CTRL_SARADC_STANDBY_WAIT_V  0xFF
-#define APB_CTRL_SARADC_STANDBY_WAIT_S  8
-/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
-/*description: */
-#define APB_CTRL_SARADC_RSTB_WAIT  0x000000FF
-#define APB_CTRL_SARADC_RSTB_WAIT_M  ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S))
-#define APB_CTRL_SARADC_RSTB_WAIT_V  0xFF
-#define APB_CTRL_SARADC_RSTB_WAIT_S  0
-
-#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG          (DR_REG_APB_CTRL_BASE + 0x1C)
-/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
-#define APB_CTRL_SARADC_SAR1_PATT_TAB1  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S))
-#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S  0
-
-#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG          (DR_REG_APB_CTRL_BASE + 0x20)
-/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
-#define APB_CTRL_SARADC_SAR1_PATT_TAB2  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S))
-#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S  0
-
-#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG          (DR_REG_APB_CTRL_BASE + 0x24)
-/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
-#define APB_CTRL_SARADC_SAR1_PATT_TAB3  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S))
-#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S  0
-
-#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG          (DR_REG_APB_CTRL_BASE + 0x28)
-/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
-#define APB_CTRL_SARADC_SAR1_PATT_TAB4  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S))
-#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S  0
-
-#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG          (DR_REG_APB_CTRL_BASE + 0x2C)
-/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
-#define APB_CTRL_SARADC_SAR2_PATT_TAB1  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S))
-#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S  0
-
-#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG          (DR_REG_APB_CTRL_BASE + 0x30)
-/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
-#define APB_CTRL_SARADC_SAR2_PATT_TAB2  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S))
-#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S  0
-
-#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG          (DR_REG_APB_CTRL_BASE + 0x34)
-/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
-#define APB_CTRL_SARADC_SAR2_PATT_TAB3  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S))
-#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S  0
-
-#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG          (DR_REG_APB_CTRL_BASE + 0x38)
-/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
-#define APB_CTRL_SARADC_SAR2_PATT_TAB4  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S))
-#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V  0xFFFFFFFF
-#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S  0
-
-#define APB_CTRL_APLL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x3C)
-/* APB_CTRL_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */
-/*description: */
-#define APB_CTRL_APLL_TICK_NUM  0x000000FF
-#define APB_CTRL_APLL_TICK_NUM_M  ((APB_CTRL_APLL_TICK_NUM_V)<<(APB_CTRL_APLL_TICK_NUM_S))
-#define APB_CTRL_APLL_TICK_NUM_V  0xFF
-#define APB_CTRL_APLL_TICK_NUM_S  0
-
-#define APB_CTRL_DATE_REG          (DR_REG_APB_CTRL_BASE + 0x7C)
-/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
-/*description: */
-#define APB_CTRL_DATE  0xFFFFFFFF
-#define APB_CTRL_DATE_M  ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
-#define APB_CTRL_DATE_V  0xFFFFFFFF
-#define APB_CTRL_DATE_S  0
-
-
-
-
-#endif /*_SOC_APB_CTRL_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/apb_ctrl_struct.h b/tools/sdk/include/soc/soc/apb_ctrl_struct.h
deleted file mode 100644
index a871af84212..00000000000
--- a/tools/sdk/include/soc/soc/apb_ctrl_struct.h
+++ /dev/null
@@ -1,132 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_APB_CTRL_STRUCT_H_
-#define _SOC_APB_CTRL_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    union {
-        struct {
-            volatile uint32_t pre_div:       10;
-            volatile uint32_t clk_320m_en:    1;
-            volatile uint32_t clk_en:         1;
-            volatile uint32_t rst_tick:       1;
-            volatile uint32_t quick_clk_chng: 1;
-            volatile uint32_t reserved14:    18;
-        };
-        volatile uint32_t val;
-    }clk_conf;
-    union {
-        struct {
-            volatile uint32_t xtal_tick:     8;
-            volatile uint32_t reserved8:    24;
-        };
-        volatile uint32_t val;
-    }xtal_tick_conf;
-    union {
-        struct {
-            volatile uint32_t pll_tick:     8;
-            volatile uint32_t reserved8:   24;
-        };
-        volatile uint32_t val;
-    }pll_tick_conf;
-    union {
-        struct {
-            volatile uint32_t ck8m_tick:     8;
-            volatile uint32_t reserved8:    24;
-        };
-        volatile uint32_t val;
-    }ck8m_tick_conf;
-    union {
-        struct {
-            volatile uint32_t start_force:       1;
-            volatile uint32_t start:             1;
-            volatile uint32_t sar2_mux:          1;       /*1: SAR ADC2 is controlled by DIG ADC2 CTRL  0: SAR ADC2 is controlled by PWDET CTRL*/
-            volatile uint32_t work_mode:         2;       /*0: single mode  1: double mode  2: alternate mode*/
-            volatile uint32_t sar_sel:           1;       /*0: SAR1  1: SAR2  only work for single SAR mode*/
-            volatile uint32_t sar_clk_gated:     1;
-            volatile uint32_t sar_clk_div:       8;       /*SAR clock divider*/
-            volatile uint32_t sar1_patt_len:     4;       /*0 ~ 15 means length 1 ~ 16*/
-            volatile uint32_t sar2_patt_len:     4;       /*0 ~ 15 means length 1 ~ 16*/
-            volatile uint32_t sar1_patt_p_clear: 1;       /*clear the pointer of pattern table for DIG ADC1 CTRL*/
-            volatile uint32_t sar2_patt_p_clear: 1;       /*clear the pointer of pattern table for DIG ADC2 CTRL*/
-            volatile uint32_t data_sar_sel:      1;       /*1: sar_sel will be coded by the MSB of the 16-bit output data  in this case the resolution should not be larger than 11 bits.*/
-            volatile uint32_t data_to_i2s:       1;       /*1: I2S input data is from SAR ADC (for DMA)  0: I2S input data is from GPIO matrix*/
-            volatile uint32_t reserved27:        5;
-        };
-        volatile uint32_t val;
-    }saradc_ctrl;
-    union {
-        struct {
-            volatile uint32_t meas_num_limit: 1;
-            volatile uint32_t max_meas_num:   8;          /*max conversion number*/
-            volatile uint32_t sar1_inv:       1;          /*1: data to DIG ADC1 CTRL is inverted  otherwise not*/
-            volatile uint32_t sar2_inv:       1;          /*1: data to DIG ADC2 CTRL is inverted  otherwise not*/
-            volatile uint32_t reserved11:    21;
-        };
-        volatile uint32_t val;
-    }saradc_ctrl2;
-    union {
-        struct {
-            volatile uint32_t rstb_wait:    8;
-            volatile uint32_t standby_wait: 8;
-            volatile uint32_t start_wait:   8;
-            volatile uint32_t sample_cycle: 8;            /*sample cycles*/
-        };
-        volatile uint32_t val;
-    }saradc_fsm;
-    volatile uint32_t saradc_sar1_patt_tab1;                 /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
-    volatile uint32_t saradc_sar1_patt_tab2;                 /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
-    volatile uint32_t saradc_sar1_patt_tab3;                 /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
-    volatile uint32_t saradc_sar1_patt_tab4;                 /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
-    volatile uint32_t saradc_sar2_patt_tab1;                 /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
-    volatile uint32_t saradc_sar2_patt_tab2;                 /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
-    volatile uint32_t saradc_sar2_patt_tab3;                 /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
-    volatile uint32_t saradc_sar2_patt_tab4;                 /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
-    union {
-        struct {
-            volatile uint32_t apll_tick:     8;
-            volatile uint32_t reserved8:    24;
-        };
-        volatile uint32_t val;
-    }apll_tick_conf;
-    volatile uint32_t reserved_40;
-    volatile uint32_t reserved_44;
-    volatile uint32_t reserved_48;
-    volatile uint32_t reserved_4c;
-    volatile uint32_t reserved_50;
-    volatile uint32_t reserved_54;
-    volatile uint32_t reserved_58;
-    volatile uint32_t reserved_5c;
-    volatile uint32_t reserved_60;
-    volatile uint32_t reserved_64;
-    volatile uint32_t reserved_68;
-    volatile uint32_t reserved_6c;
-    volatile uint32_t reserved_70;
-    volatile uint32_t reserved_74;
-    volatile uint32_t reserved_78;
-    volatile uint32_t date;                                      /**/
-} apb_ctrl_dev_t;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_APB_CTRL_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/bb_reg.h b/tools/sdk/include/soc/soc/bb_reg.h
deleted file mode 100644
index 69d2f43d206..00000000000
--- a/tools/sdk/include/soc/soc/bb_reg.h
+++ /dev/null
@@ -1,42 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_BB_REG_H_
-#define _SOC_BB_REG_H_
-
-/* Some of the baseband control registers.
- * PU/PD fields defined here are used in sleep related functions.
- */
-
-#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
-#define BB_FFT_FORCE_PU (BIT(3))
-#define BB_FFT_FORCE_PU_M (BIT(3))
-#define BB_FFT_FORCE_PU_V 1
-#define BB_FFT_FORCE_PU_S 3
-#define BB_FFT_FORCE_PD (BIT(2))
-#define BB_FFT_FORCE_PD_M (BIT(2))
-#define BB_FFT_FORCE_PD_V 1
-#define BB_FFT_FORCE_PD_S 2
-#define BB_DC_EST_FORCE_PU (BIT(1))
-#define BB_DC_EST_FORCE_PU_M (BIT(1))
-#define BB_DC_EST_FORCE_PU_V 1
-#define BB_DC_EST_FORCE_PU_S 1
-#define BB_DC_EST_FORCE_PD (BIT(0))
-#define BB_DC_EST_FORCE_PD_M (BIT(0))
-#define BB_DC_EST_FORCE_PD_V 1
-#define BB_DC_EST_FORCE_PD_S 0
-
-
-#endif /* _SOC_BB_REG_H_ */
-
diff --git a/tools/sdk/include/soc/soc/boot_mode.h b/tools/sdk/include/soc/soc/boot_mode.h
deleted file mode 100644
index 5106e10cfbd..00000000000
--- a/tools/sdk/include/soc/soc/boot_mode.h
+++ /dev/null
@@ -1,104 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_BOOT_MODE_H_
-#define _SOC_BOOT_MODE_H_
-
-#include "soc.h"
-
-/*SPI Boot*/
-#define IS_1XXXX(v)				(((v)&0x10)==0x10)
-
-/*HSPI Boot*/
-#define IS_010XX(v)				(((v)&0x1c)==0x08)
-
-/*Download Boot, SDIO/UART0/UART1*/
-#define IS_00XXX(v)				(((v)&0x18)==0x00)
-
-/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
-#define IS_00X00(v)				(((v)&0x1b)==0x00)
-
-/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
-#define IS_00X01(v)				(((v)&0x1b)==0x01)
-
-/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
-#define IS_00X10(v)				(((v)&0x1b)==0x02)
-
-/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
-#define IS_00X11(v)				(((v)&0x1b)==0x03)
-
-/*ATE/ANALOG Mode*/
-#define IS_01110(v)				(((v)&0x1f)==0x0e)
-
-/*Diagnostic Mode+UART0 download Mode*/
-#define IS_01111(v)				(((v)&0x1f)==0x0f)
-
-/*legacy SPI Boot*/
-#define IS_01100(v)				(((v)&0x1f)==0x0c)
-
-/*SDIO_Slave download Mode V1.1*/
-#define IS_01101(v)				(((v)&0x1f)==0x0d)
-
-
-
-#define BOOT_MODE_GET()                                 (GPIO_REG_READ(GPIO_STRAP))
-
-/*do not include download mode*/
-#define ETS_IS_UART_BOOT()				IS_01111(BOOT_MODE_GET())
-
-/*all spi boot including spi/hspi/legacy*/
-#define ETS_IS_FLASH_BOOT()				(IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET()))
-
-/*all faster spi boot including spi/hspi*/
-#define ETS_IS_FAST_FLASH_BOOT()				(IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()))
-
-/*all spi boot including spi/legacy*/
-#define ETS_IS_SPI_FLASH_BOOT()				(IS_1XXXX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET()))
-
-/*all spi boot including hspi/legacy*/
-#define ETS_IS_HSPI_FLASH_BOOT()				IS_010XX(BOOT_MODE_GET())
-
-/*all sdio V2 of failing edge input, failing edge output*/
-#define ETS_IS_SDIO_FEI_FEO_V2_BOOT()				IS_00X00(BOOT_MODE_GET())
-
-/*all sdio V2 of failing edge input, raising edge output*/
-#define ETS_IS_SDIO_FEI_REO_V2_BOOT()				IS_00X01(BOOT_MODE_GET())
-
-/*all sdio V2 of raising edge input, failing edge output*/
-#define ETS_IS_SDIO_REI_FEO_V2_BOOT()				IS_00X10(BOOT_MODE_GET())
-
-/*all sdio V2 of raising edge input, raising edge output*/
-#define ETS_IS_SDIO_REI_REO_V2_BOOT()				IS_00X11(BOOT_MODE_GET())
-
-/*all sdio V1 of raising edge input, failing edge output*/
-#define ETS_IS_SDIO_REI_FEO_V1_BOOT()				IS_01101(BOOT_MODE_GET())
-
-/*do not include download mode*/
-#define ETS_IS_SDIO_BOOT()				IS_01101(BOOT_MODE_GET())
-
-/*joint download boot*/
-#define ETS_IS_SDIO_UART_BOOT()				IS_00XXX(BOOT_MODE_GET())
-
-/*ATE mode*/
-#define ETS_IS_ATE_BOOT()				IS_01110(BOOT_MODE_GET())
-
-/*A bit to control flash boot print*/
-#define ETS_IS_PRINT_BOOT()                             (BOOT_MODE_GET() & 0x2)
-
-/*used by  ETS_IS_SDIO_UART_BOOT*/
-#define SEL_NO_BOOT                                    0
-#define SEL_SDIO_BOOT                                 BIT0
-#define SEL_UART_BOOT                                BIT1
-
-#endif /* _SOC_BOOT_MODE_H_ */
diff --git a/tools/sdk/include/soc/soc/can_struct.h b/tools/sdk/include/soc/soc/can_struct.h
deleted file mode 100644
index 81ab02ca075..00000000000
--- a/tools/sdk/include/soc/soc/can_struct.h
+++ /dev/null
@@ -1,213 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_CAN_STRUCT_H_
-#define _SOC_CAN_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* -------------------------- Register Definitions -------------------------- */
-
-/* The CAN peripheral's registers are 8bits, however the ESP32 can only access
- * peripheral registers every 32bits. Therefore each CAN register is mapped to
- * the least significant byte of every 32bits.
- */
-typedef union {
-    struct {
-        uint32_t byte: 8;                                   /* LSB */
-        uint32_t reserved24: 24;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reset: 1;                                  /* MOD.0 Reset Mode */
-        uint32_t listen_only: 1;                            /* MOD.1 Listen Only Mode */
-        uint32_t self_test: 1;                              /* MOD.2 Self Test Mode */
-        uint32_t acceptance_filter: 1;                      /* MOD.3 Acceptance Filter Mode */
-        uint32_t reserved28: 28;                            /* Internal Reserved. MOD.4 Sleep Mode not supported */
-    };
-    uint32_t val;
-} can_mode_reg_t;
-
-typedef union {
-    struct {
-        uint32_t tx_req: 1;                                 /* CMR.0 Transmission Request */
-        uint32_t abort_tx: 1;                               /* CMR.1 Abort Transmission */
-        uint32_t release_rx_buff: 1;                        /* CMR.2 Release Receive Buffer */
-        uint32_t clear_data_overrun: 1;                     /* CMR.3 Clear Data Overrun */
-        uint32_t self_rx_req: 1;                            /* CMR.4 Self Reception Request */
-        uint32_t reserved27: 27;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_cmd_reg_t;
-
-typedef union {
-    struct {
-        uint32_t rx_buff: 1;                                /* SR.0 Receive Buffer Status */
-        uint32_t data_overrun: 1;                           /* SR.1 Data Overrun Status */
-        uint32_t tx_buff: 1;                                /* SR.2 Transmit Buffer Status */
-        uint32_t tx_complete: 1;                            /* SR.3 Transmission Complete Status */
-        uint32_t rx: 1;                                     /* SR.4 Receive Status */
-        uint32_t tx: 1;                                     /* SR.5 Transmit Status */
-        uint32_t error: 1;                                  /* SR.6 Error Status */
-        uint32_t bus: 1;                                    /* SR.7 Bus Status */
-        uint32_t reserved24: 24;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_status_reg_t;
-
-typedef union {
-    struct {
-        uint32_t rx: 1;                                     /* IR.0 Receive Interrupt */
-        uint32_t tx: 1;                                     /* IR.1 Transmit Interrupt */
-        uint32_t err_warn: 1;                               /* IR.2 Error Interrupt */
-        uint32_t data_overrun: 1;                           /* IR.3 Data Overrun Interrupt */
-        uint32_t reserved1: 1;                              /* Internal Reserved (Wake-up not supported) */
-        uint32_t err_passive: 1;                            /* IR.5 Error Passive Interrupt */
-        uint32_t arb_lost: 1;                               /* IR.6 Arbitration Lost Interrupt */
-        uint32_t bus_err: 1;                                /* IR.7 Bus Error Interrupt */
-        uint32_t reserved24: 24;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_intr_reg_t;
-
-typedef union {
-    struct {
-        uint32_t rx: 1;                                     /* IER.0 Receive Interrupt Enable */
-        uint32_t tx: 1;                                     /* IER.1 Transmit Interrupt Enable */
-        uint32_t err_warn: 1;                               /* IER.2 Error Interrupt Enable */
-        uint32_t data_overrun: 1;                           /* IER.3 Data Overrun Interrupt Enable */
-        uint32_t brp_div: 1;                                /* THIS IS NOT AN INTERRUPT. brp_div will prescale BRP by 2. Only available on ESP32 Revision 2 or later. Reserved otherwise */
-        uint32_t err_passive: 1;                            /* IER.5 Error Passive Interrupt Enable */
-        uint32_t arb_lost: 1;                               /* IER.6 Arbitration Lost Interrupt Enable */
-        uint32_t bus_err: 1;                                /* IER.7 Bus Error Interrupt Enable */
-        uint32_t reserved24: 24;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_intr_en_reg_t;
-
-typedef union {
-    struct {
-        uint32_t baud_rate_prescaler: 6;                    /* BTR0[5:0] Baud Rate Prescaler */
-        uint32_t sync_jump_width: 2;                        /* BTR0[7:6] Synchronization Jump Width*/
-        uint32_t reserved24: 24;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_bus_tim_0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t time_seg_1: 4;                             /* BTR1[3:0] Timing Segment 1 */
-        uint32_t time_seg_2: 3;                             /* BTR1[6:4] Timing Segment 2 */
-        uint32_t sampling: 1;                               /* BTR1.7 Sampling*/
-        uint32_t reserved24: 24;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_bus_tim_1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t arbitration_lost_capture: 5;               /* ALC[4:0] Arbitration lost capture */
-        uint32_t reserved27: 27;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_arb_lost_cap_reg_t;
-
-typedef union {
-    struct {
-        uint32_t segment: 5;                                /* ECC[4:0] Error Code Segment 0 to 5 */
-        uint32_t direction: 1;                              /* ECC.5 Error Direction (TX/RX) */
-        uint32_t error_code: 2;                             /* ECC[7:6] Error Code */
-        uint32_t reserved24: 24;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_err_code_cap_reg_t;
-
-typedef struct {
-    can_reg_t code_reg[4];
-    can_reg_t mask_reg[4];
-    uint32_t reserved32[5];
-} can_acc_filter_t;
-
-typedef union {
-    struct {
-        uint32_t rx_message_counter: 5;                     /* RMC[4:0] RX Message Counter */
-        uint32_t reserved27: 27;                            /* Internal Reserved */
-    };
-    uint32_t val;
-} can_rx_msg_cnt_reg_t;
-
-typedef union {
-    struct {
-        uint32_t clock_divider: 3;                          /* CDR[2:0] CLKOUT frequency selector based of fOSC */
-        uint32_t clock_off: 1;                              /* CDR.3 CLKOUT enable/disable */
-        uint32_t reserved3: 3;                              /* Internal Reserved. RXINTEN and CBP not supported */
-        uint32_t can_mode: 1;                               /* CDR.7 BasicCAN:0 PeliCAN:1 */
-        uint32_t reserved24: 24;                            /* Internal Reserved  */
-    };
-    uint32_t val;
-} can_clk_div_reg_t;
-
-/* ---------------------------- Register Layout ------------------------------ */
-
-typedef volatile struct {
-    //Configuration and Control Registers
-    can_mode_reg_t mode_reg;                                /* Address 0 */
-    can_cmd_reg_t command_reg;                              /* Address 1 */
-    can_status_reg_t status_reg;                            /* Address 2 */
-    can_intr_reg_t interrupt_reg;                           /* Address 3 */
-    can_intr_en_reg_t interrupt_enable_reg;                 /* Address 4 */
-    uint32_t reserved_05;                                   /* Address 5 */
-    can_bus_tim_0_reg_t bus_timing_0_reg;                   /* Address 6 */
-    can_bus_tim_1_reg_t bus_timing_1_reg;                   /* Address 7 */
-    uint32_t reserved_08;                                   /* Address 8 (Output control not supported) */
-    uint32_t reserved_09;                                   /* Address 9 (Test Register not supported) */
-    uint32_t reserved_10;                                   /* Address 10 */
-
-    //Capture and Counter Registers
-    can_arb_lost_cap_reg_t arbitration_lost_captue_reg;     /* Address 11 */
-    can_err_code_cap_reg_t error_code_capture_reg;          /* Address 12 */
-    can_reg_t error_warning_limit_reg;                      /* EWLR[7:0] Error Warning Limit: Address 13 */
-    can_reg_t rx_error_counter_reg;                         /* RXERR[7:0] Receive Error Counter: Address 14 */
-    can_reg_t tx_error_counter_reg;                         /* TXERR[7:0] Transmit Error Counter: Address 15 */
-
-    //Shared Registers (TX Buff/RX Buff/Acc Filter)
-    union {
-        can_acc_filter_t acceptance_filter;
-        can_reg_t tx_rx_buffer[13];
-    };                                                      /* Address 16-28 TX/RX Buffer and Acc Filter*/;
-
-    //Misc Registers
-    can_rx_msg_cnt_reg_t rx_message_counter_reg;            /* Address 29 */
-    can_reg_t reserved_30;                                  /* Address 30 (RX Buffer Start Address not supported) */
-    can_clk_div_reg_t clock_divider_reg;                    /* Address 31 */
-
-    //Start of RX FIFO
-} can_dev_t;
-
-_Static_assert(sizeof(can_dev_t) == 128, "CAN registers should be 32 * 4 bytes");
-
-extern can_dev_t CAN;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_CAN_STRUCT_H_ */
-
diff --git a/tools/sdk/include/soc/soc/clkout_channel.h b/tools/sdk/include/soc/soc/clkout_channel.h
deleted file mode 100644
index 5161e3f0b65..00000000000
--- a/tools/sdk/include/soc/soc/clkout_channel.h
+++ /dev/null
@@ -1,26 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_CLKOUT_CHANNEL_H
-#define _SOC_CLKOUT_CHANNEL_H
-
-//CLKOUT channels
-#define CLKOUT_GPIO0_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
-#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM    0
-#define CLKOUT_GPIO3_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
-#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM    3
-#define CLKOUT_GPIO1_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
-#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM    1
-
-#endif
diff --git a/tools/sdk/include/soc/soc/cpu.h b/tools/sdk/include/soc/soc/cpu.h
deleted file mode 100644
index f28feb59fa2..00000000000
--- a/tools/sdk/include/soc/soc/cpu.h
+++ /dev/null
@@ -1,113 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_CPU_H
-#define _SOC_CPU_H
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include "xtensa/corebits.h"
-#include "xtensa/config/core.h"
-
-/* C macros for xtensa special register read/write/exchange */
-
-#define RSR(reg, curval)  asm volatile ("rsr %0, " #reg : "=r" (curval));
-#define WSR(reg, newval)  asm volatile ("wsr %0, " #reg : : "r" (newval));
-#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
-
-/** @brief Read current stack pointer address
- *
- */
-static inline void *get_sp()
-{
-    void *sp;
-    asm volatile ("mov %0, sp;" : "=r" (sp));
-    return sp;
-}
-
-/* Functions to set page attributes for Region Protection option in the CPU.
- * See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
- */
-
-static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
-{
-    asm volatile ("wdtlb  %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
-}
-
-
-static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
-{
-    asm volatile ("witlb  %1, %0; isync\n" :: "r" (vpn), "r" (attr));
-}
-
-static inline void cpu_init_memctl()
-{
-#if XCHAL_ERRATUM_572
-    uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
-    WSR(MEMCTL, memctl);
-#endif // XCHAL_ERRATUM_572
-}
-
-/**
- * @brief Configure memory region protection
- *
- * Make page 0 access raise an exception.
- * Also protect some other unused pages so we can catch weirdness.
- * Useful attribute values:
- * 0 — cached, RW
- * 2 — bypass cache, RWX (default value after CPU reset)
- * 15 — no access, raise exception
- */
-
-static inline void cpu_configure_region_protection()
-{
-    const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
-    for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
-        cpu_write_dtlb(pages_to_protect[i], 0xf);
-        cpu_write_itlb(pages_to_protect[i], 0xf);
-    }
-    cpu_write_dtlb(0x20000000, 0);
-    cpu_write_itlb(0x20000000, 0);
-}
-
-/**
- * @brief Stall CPU using RTC controller
- * @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
- */
-void esp_cpu_stall(int cpu_id);
-
-/**
- * @brief Un-stall CPU using RTC controller
- * @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
- */
-void esp_cpu_unstall(int cpu_id);
-
-/**
- * @brief Reset CPU using RTC controller
- * @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
- */
-void esp_cpu_reset(int cpu_id);
-
-
-/**
- * @brief Returns true if a JTAG debugger is attached to CPU
- * OCD (on chip debug) port.
- *
- * @note If "Make exception and panic handlers JTAG/OCD aware"
- * is disabled, this function always returns false.
- */
-bool esp_cpu_in_ocd_debug_mode();
-
-#endif
diff --git a/tools/sdk/include/soc/soc/dac_channel.h b/tools/sdk/include/soc/soc/dac_channel.h
deleted file mode 100644
index 241a067bb24..00000000000
--- a/tools/sdk/include/soc/soc/dac_channel.h
+++ /dev/null
@@ -1,24 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_DAC_CHANNEL_H
-#define _SOC_DAC_CHANNEL_H
-
-#define DAC_GPIO25_CHANNEL      DAC_CHANNEL_1
-#define DAC_CHANNEL_1_GPIO_NUM  25
-
-#define DAC_GPIO26_CHANNEL      DAC_CHANNEL_2
-#define DAC_CHANNEL_2_GPIO_NUM  26
-
-#endif
diff --git a/tools/sdk/include/soc/soc/dport_access.h b/tools/sdk/include/soc/soc/dport_access.h
deleted file mode 100644
index 2639e46ef14..00000000000
--- a/tools/sdk/include/soc/soc/dport_access.h
+++ /dev/null
@@ -1,202 +0,0 @@
-// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _DPORT_ACCESS_H_
-#define _DPORT_ACCESS_H_
-
-#include <stdint.h>
-#include "esp_attr.h"
-#include "esp_dport_access.h"
-#include "soc.h"
-#include "uart_reg.h"
-#include "xtensa/xtruntime.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//Registers Operation {{
-
-// The _DPORT_xxx register read macros access DPORT memory directly (as opposed to
-// DPORT_REG_READ which applies SMP-safe protections).
-//
-// There are several ways to read the DPORT registers:
-// 1) Use DPORT_REG_READ versions to be SMP-safe in IDF apps.
-//    This method uses the pre-read APB implementation(*) without stall other CPU.
-//    This is beneficial for single readings.
-// 2) If you want to make a sequence of DPORT reads to buffer,
-//    use dport_read_buffer(buff_out, address, num_words),
-//    it is the faster method and it doesn't stop other CPU.
-// 3) If you want to make a sequence of DPORT reads, but you don't want to stop other CPU
-//    and you want to do it faster then you need use DPORT_SEQUENCE_REG_READ().
-//    The difference from the first is that the user himself must disable interrupts while DPORT reading.
-//    Note that disable interrupt need only if the chip has two cores.
-// 4) If you want to make a sequence of DPORT reads,
-//    use DPORT_STALL_OTHER_CPU_START() macro explicitly
-//    and then use _DPORT_REG_READ macro while other CPU is stalled.
-//    After completing read operations, use DPORT_STALL_OTHER_CPU_END().
-//    This method uses stall other CPU while reading DPORT registers.
-//    Useful for compatibility, as well as for large consecutive readings.
-//    This method is slower, but must be used if ROM functions or
-//    other code is called which accesses DPORT without any other workaround.
-// *) The pre-readable APB register before reading the DPORT register
-//    helps synchronize the operation of the two CPUs,
-//    so that reading on different CPUs no longer causes random errors APB register.
-
-// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
-#define _DPORT_REG_READ(_r)        (*(volatile uint32_t *)(_r))
-#define _DPORT_REG_WRITE(_r, _v)   (*(volatile uint32_t *)(_r)) = (_v)
-
-// Write value to DPORT register (does not require protecting)
-#define DPORT_REG_WRITE(_r, _v)   _DPORT_REG_WRITE((_r), (_v))
-
-/**
- * @brief Read value from register, SMP-safe version.
- *
- * This method uses the pre-reading of the APB register before reading the register of the DPORT.
- * This implementation is useful for reading DORT registers for single reading without stall other CPU.
- * There is disable/enable interrupt.
- *
- * @param reg Register address
- * @return Value
- */
-static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
-{
-#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
-    return _DPORT_REG_READ(reg);
-#else
-    return esp_dport_access_reg_read(reg);
-#endif
-}
-
-/**
- * @brief Read value from register, NOT SMP-safe version.
- *
- * This method uses the pre-reading of the APB register before reading the register of the DPORT.
- * There is not disable/enable interrupt.
- * The difference from DPORT_REG_READ() is that the user himself must disable interrupts while DPORT reading.
- * This implementation is useful for reading DORT registers in loop without stall other CPU. Note the usage example.
- * The recommended way to read registers sequentially without stall other CPU
- * is to use the method esp_dport_read_buffer(buff_out, address, num_words). It allows you to read registers in the buffer.
- *
- * \code{c}
- * // This example shows how to use it.
- * { // Use curly brackets to limit the visibility of variables in macros DPORT_INTERRUPT_DISABLE/RESTORE.
- *     DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU.
- *     for (i = 0; i < max; ++i) {
- *        array[i] = DPORT_SEQUENCE_REG_READ(Address + i * 4); // reading DPORT registers
- *     }
- *     DPORT_INTERRUPT_RESTORE(); // restore the previous interrupt level
- * }
- * \endcode
- *
- * @param reg Register address
- * @return Value
- */
-static inline uint32_t IRAM_ATTR DPORT_SEQUENCE_REG_READ(uint32_t reg)
-{
-#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
-    return _DPORT_REG_READ(reg);
-#else
-    return esp_dport_access_sequence_reg_read(reg);
-#endif
-}
-
-//get bit or get bits from register
-#define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
-
-//set bit or set bits to register
-#define DPORT_REG_SET_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
-
-//clear bit or clear bits of register
-#define DPORT_REG_CLR_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
-
-//set bits of register controlled by mask
-#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
-
-//get field from register, uses field _S & _V to determine mask
-#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
-
-//set field to register, used when _f is not left shifted by _f##_S
-#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
-
-//get field value from a variable, used when _f is not left shifted by _f##_S
-#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
-
-//get field value from a variable, used when _f is left shifted by _f##_S
-#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
-
-//set field value to a variable, used when _f is not left shifted by _f##_S
-#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
-
-//set field value to a variable, used when _f is left shifted by _f##_S
-#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
-
-//generate a value from a field value, used when _f is not left shifted by _f##_S
-#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
-
-//generate a value from a field value, used when _f is left shifted by _f##_S
-#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
-
-//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
-#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
-#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
-#define _DPORT_REG_SET_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
-#define _DPORT_REG_CLR_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
-
-/**
- * @brief Read value from register, SMP-safe version.
- *
- * This method uses the pre-reading of the APB register before reading the register of the DPORT.
- * This implementation is useful for reading DORT registers for single reading without stall other CPU.
- *
- * @param reg Register address
- * @return Value
- */
-static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t reg)
-{
-#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM)
-    return _DPORT_REG_READ(reg);
-#else
-    return esp_dport_access_reg_read(reg);
-#endif
-}
-
-//write value to register
-#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
-
-//clear bits of register controlled by mask
-#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
-
-//set bits of register controlled by mask
-#define DPORT_SET_PERI_REG_MASK(reg, mask)   DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
-
-//get bits of register controlled by mask
-#define DPORT_GET_PERI_REG_MASK(reg, mask)   (DPORT_READ_PERI_REG(reg) & (mask))
-
-//get bits of register controlled by highest bit and lowest bit
-#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos)     ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
-
-//set bits of register controlled by mask and shift
-#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
-
-//get field of register
-#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift)      ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
-//}}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _DPORT_ACCESS_H_ */
diff --git a/tools/sdk/include/soc/soc/dport_reg.h b/tools/sdk/include/soc/soc/dport_reg.h
deleted file mode 100644
index 9cc3320b39b..00000000000
--- a/tools/sdk/include/soc/soc/dport_reg.h
+++ /dev/null
@@ -1,4288 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_DPORT_REG_H_
-#define _SOC_DPORT_REG_H_
-
-#include "soc.h"
-
-#ifndef __ASSEMBLER__
-#include "dport_access.h"
-#endif
-   
-/* Registers defined in this header file must be accessed using special macros,
- * prefixed with DPORT_. See soc/dport_access.h file for details.
- */
-
-#define DPORT_PRO_BOOT_REMAP_CTRL_REG          (DR_REG_DPORT_BASE + 0x000)
-/* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_BOOT_REMAP  (BIT(0))
-#define DPORT_PRO_BOOT_REMAP_M  (BIT(0))
-#define DPORT_PRO_BOOT_REMAP_V  0x1
-#define DPORT_PRO_BOOT_REMAP_S  0
-
-#define DPORT_APP_BOOT_REMAP_CTRL_REG          (DR_REG_DPORT_BASE + 0x004)
-/* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_BOOT_REMAP  (BIT(0))
-#define DPORT_APP_BOOT_REMAP_M  (BIT(0))
-#define DPORT_APP_BOOT_REMAP_V  0x1
-#define DPORT_APP_BOOT_REMAP_S  0
-
-#define DPORT_ACCESS_CHECK_REG          (DR_REG_DPORT_BASE + 0x008)
-/* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_ACCESS_CHECK_APP  (BIT(8))
-#define DPORT_ACCESS_CHECK_APP_M  (BIT(8))
-#define DPORT_ACCESS_CHECK_APP_V  0x1
-#define DPORT_ACCESS_CHECK_APP_S  8
-/* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_ACCESS_CHECK_PRO  (BIT(0))
-#define DPORT_ACCESS_CHECK_PRO_M  (BIT(0))
-#define DPORT_ACCESS_CHECK_PRO_V  0x1
-#define DPORT_ACCESS_CHECK_PRO_S  0
-
-#define DPORT_PRO_DPORT_APB_MASK0_REG          (DR_REG_DPORT_BASE + 0x00C)
-/* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_PRODPORT_APB_MASK0  0xFFFFFFFF
-#define DPORT_PRODPORT_APB_MASK0_M  ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S))
-#define DPORT_PRODPORT_APB_MASK0_V  0xFFFFFFFF
-#define DPORT_PRODPORT_APB_MASK0_S  0
-
-#define DPORT_PRO_DPORT_APB_MASK1_REG          (DR_REG_DPORT_BASE + 0x010)
-/* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_PRODPORT_APB_MASK1  0xFFFFFFFF
-#define DPORT_PRODPORT_APB_MASK1_M  ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S))
-#define DPORT_PRODPORT_APB_MASK1_V  0xFFFFFFFF
-#define DPORT_PRODPORT_APB_MASK1_S  0
-
-#define DPORT_APP_DPORT_APB_MASK0_REG          (DR_REG_DPORT_BASE + 0x014)
-/* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_APPDPORT_APB_MASK0  0xFFFFFFFF
-#define DPORT_APPDPORT_APB_MASK0_M  ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S))
-#define DPORT_APPDPORT_APB_MASK0_V  0xFFFFFFFF
-#define DPORT_APPDPORT_APB_MASK0_S  0
-
-#define DPORT_APP_DPORT_APB_MASK1_REG          (DR_REG_DPORT_BASE + 0x018)
-/* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_APPDPORT_APB_MASK1  0xFFFFFFFF
-#define DPORT_APPDPORT_APB_MASK1_M  ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S))
-#define DPORT_APPDPORT_APB_MASK1_V  0xFFFFFFFF
-#define DPORT_APPDPORT_APB_MASK1_S  0
-
-#define DPORT_PERI_CLK_EN_REG          (DR_REG_DPORT_BASE + 0x01C)
-/* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_PERI_CLK_EN  0xFFFFFFFF
-#define DPORT_PERI_CLK_EN_M  ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S))
-#define DPORT_PERI_CLK_EN_V  0xFFFFFFFF
-#define DPORT_PERI_CLK_EN_S  0
-
-#define DPORT_PERI_RST_EN_REG          (DR_REG_DPORT_BASE + 0x020)
-/* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_PERI_RST_EN  0xFFFFFFFF
-#define DPORT_PERI_RST_EN_M  ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S))
-#define DPORT_PERI_RST_EN_V  0xFFFFFFFF
-#define DPORT_PERI_RST_EN_S  0
-
-/* The following bits apply to DPORT_PERI_CLK_EN_REG, DPORT_PERI_RST_EN_REG
- */
-#define DPORT_PERI_EN_AES (1<<0)
-#define DPORT_PERI_EN_SHA (1<<1)
-#define DPORT_PERI_EN_RSA (1<<2)
-/* NB: Secure boot reset will hold SHA & AES in reset */
-#define DPORT_PERI_EN_SECUREBOOT (1<<3)
-/* NB: Digital signature reset will hold AES & RSA in reset */
-#define DPORT_PERI_EN_DIGITAL_SIGNATURE (1<<4)
-
-#define DPORT_WIFI_BB_CFG_REG          (DR_REG_DPORT_BASE + 0x024)
-/* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_WIFI_BB_CFG  0xFFFFFFFF
-#define DPORT_WIFI_BB_CFG_M  ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S))
-#define DPORT_WIFI_BB_CFG_V  0xFFFFFFFF
-#define DPORT_WIFI_BB_CFG_S  0
-
-#define DPORT_WIFI_BB_CFG_2_REG          (DR_REG_DPORT_BASE + 0x028)
-/* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_WIFI_BB_CFG_2  0xFFFFFFFF
-#define DPORT_WIFI_BB_CFG_2_M  ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S))
-#define DPORT_WIFI_BB_CFG_2_V  0xFFFFFFFF
-#define DPORT_WIFI_BB_CFG_2_S  0
-
-#define DPORT_APPCPU_CTRL_A_REG          (DR_REG_DPORT_BASE + 0x02C)
-/* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APPCPU_RESETTING  (BIT(0))
-#define DPORT_APPCPU_RESETTING_M  (BIT(0))
-#define DPORT_APPCPU_RESETTING_V  0x1
-#define DPORT_APPCPU_RESETTING_S  0
-
-#define DPORT_APPCPU_CTRL_B_REG          (DR_REG_DPORT_BASE + 0x030)
-/* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APPCPU_CLKGATE_EN  (BIT(0))
-#define DPORT_APPCPU_CLKGATE_EN_M  (BIT(0))
-#define DPORT_APPCPU_CLKGATE_EN_V  0x1
-#define DPORT_APPCPU_CLKGATE_EN_S  0
-
-#define DPORT_APPCPU_CTRL_C_REG          (DR_REG_DPORT_BASE + 0x034)
-/* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APPCPU_RUNSTALL  (BIT(0))
-#define DPORT_APPCPU_RUNSTALL_M  (BIT(0))
-#define DPORT_APPCPU_RUNSTALL_V  0x1
-#define DPORT_APPCPU_RUNSTALL_S  0
-
-#define DPORT_APPCPU_CTRL_D_REG          (DR_REG_DPORT_BASE + 0x038)
-/* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_APPCPU_BOOT_ADDR  0xFFFFFFFF
-#define DPORT_APPCPU_BOOT_ADDR_M  ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S))
-#define DPORT_APPCPU_BOOT_ADDR_V  0xFFFFFFFF
-#define DPORT_APPCPU_BOOT_ADDR_S  0
-
-#define DPORT_CPU_PER_CONF_REG          (DR_REG_DPORT_BASE + 0x03C)
-/* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_FAST_CLK_RTC_SEL  (BIT(3))
-#define DPORT_FAST_CLK_RTC_SEL_M  (BIT(3))
-#define DPORT_FAST_CLK_RTC_SEL_V  0x1
-#define DPORT_FAST_CLK_RTC_SEL_S  3
-/* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_LOWSPEED_CLK_SEL  (BIT(2))
-#define DPORT_LOWSPEED_CLK_SEL_M  (BIT(2))
-#define DPORT_LOWSPEED_CLK_SEL_V  0x1
-#define DPORT_LOWSPEED_CLK_SEL_S  2
-/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_CPUPERIOD_SEL  0x00000003
-#define DPORT_CPUPERIOD_SEL_M  ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
-#define DPORT_CPUPERIOD_SEL_V  0x3
-#define DPORT_CPUPERIOD_SEL_S  0
-#define DPORT_CPUPERIOD_SEL_80		0
-#define DPORT_CPUPERIOD_SEL_160		1
-#define DPORT_CPUPERIOD_SEL_240		2
-
-#define DPORT_PRO_CACHE_CTRL_REG          (DR_REG_DPORT_BASE + 0x040)
-/* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_DRAM_HL  (BIT(16))
-#define DPORT_PRO_DRAM_HL_M  (BIT(16))
-#define DPORT_PRO_DRAM_HL_V  0x1
-#define DPORT_PRO_DRAM_HL_S  16
-/* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_SLAVE_REQ  (BIT(15))
-#define DPORT_SLAVE_REQ_M  (BIT(15))
-#define DPORT_SLAVE_REQ_V  0x1
-#define DPORT_SLAVE_REQ_S  15
-/* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AHB_SPI_REQ  (BIT(14))
-#define DPORT_AHB_SPI_REQ_M  (BIT(14))
-#define DPORT_AHB_SPI_REQ_V  0x1
-#define DPORT_AHB_SPI_REQ_S  14
-/* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_SLAVE_REQ  (BIT(13))
-#define DPORT_PRO_SLAVE_REQ_M  (BIT(13))
-#define DPORT_PRO_SLAVE_REQ_V  0x1
-#define DPORT_PRO_SLAVE_REQ_S  13
-/* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_AHB_SPI_REQ  (BIT(12))
-#define DPORT_PRO_AHB_SPI_REQ_M  (BIT(12))
-#define DPORT_PRO_AHB_SPI_REQ_V  0x1
-#define DPORT_PRO_AHB_SPI_REQ_S  12
-/* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_DRAM_SPLIT  (BIT(11))
-#define DPORT_PRO_DRAM_SPLIT_M  (BIT(11))
-#define DPORT_PRO_DRAM_SPLIT_V  0x1
-#define DPORT_PRO_DRAM_SPLIT_S  11
-/* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_SINGLE_IRAM_ENA  (BIT(10))
-#define DPORT_PRO_SINGLE_IRAM_ENA_M  (BIT(10))
-#define DPORT_PRO_SINGLE_IRAM_ENA_V  0x1
-#define DPORT_PRO_SINGLE_IRAM_ENA_S  10
-/* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_3_EN  (BIT(9))
-#define DPORT_PRO_CACHE_LOCK_3_EN_M  (BIT(9))
-#define DPORT_PRO_CACHE_LOCK_3_EN_V  0x1
-#define DPORT_PRO_CACHE_LOCK_3_EN_S  9
-/* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_2_EN  (BIT(8))
-#define DPORT_PRO_CACHE_LOCK_2_EN_M  (BIT(8))
-#define DPORT_PRO_CACHE_LOCK_2_EN_V  0x1
-#define DPORT_PRO_CACHE_LOCK_2_EN_S  8
-/* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_1_EN  (BIT(7))
-#define DPORT_PRO_CACHE_LOCK_1_EN_M  (BIT(7))
-#define DPORT_PRO_CACHE_LOCK_1_EN_V  0x1
-#define DPORT_PRO_CACHE_LOCK_1_EN_S  7
-/* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_0_EN  (BIT(6))
-#define DPORT_PRO_CACHE_LOCK_0_EN_M  (BIT(6))
-#define DPORT_PRO_CACHE_LOCK_0_EN_V  0x1
-#define DPORT_PRO_CACHE_LOCK_0_EN_S  6
-/* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_FLUSH_DONE  (BIT(5))
-#define DPORT_PRO_CACHE_FLUSH_DONE_M  (BIT(5))
-#define DPORT_PRO_CACHE_FLUSH_DONE_V  0x1
-#define DPORT_PRO_CACHE_FLUSH_DONE_S  5
-/* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CACHE_FLUSH_ENA  (BIT(4))
-#define DPORT_PRO_CACHE_FLUSH_ENA_M  (BIT(4))
-#define DPORT_PRO_CACHE_FLUSH_ENA_V  0x1
-#define DPORT_PRO_CACHE_FLUSH_ENA_S  4
-/* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_ENABLE  (BIT(3))
-#define DPORT_PRO_CACHE_ENABLE_M  (BIT(3))
-#define DPORT_PRO_CACHE_ENABLE_V  0x1
-#define DPORT_PRO_CACHE_ENABLE_S  3
-/* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_MODE  (BIT(2))
-#define DPORT_PRO_CACHE_MODE_M  (BIT(2))
-#define DPORT_PRO_CACHE_MODE_V  0x1
-#define DPORT_PRO_CACHE_MODE_S  2
-
-#define DPORT_PRO_CACHE_CTRL1_REG          (DR_REG_DPORT_BASE + 0x044)
-/* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_MMU_IA_CLR  (BIT(13))
-#define DPORT_PRO_CACHE_MMU_IA_CLR_M  (BIT(13))
-#define DPORT_PRO_CACHE_MMU_IA_CLR_V  0x1
-#define DPORT_PRO_CACHE_MMU_IA_CLR_S  13
-/* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CMMU_PD  (BIT(12))
-#define DPORT_PRO_CMMU_PD_M  (BIT(12))
-#define DPORT_PRO_CMMU_PD_V  0x1
-#define DPORT_PRO_CMMU_PD_S  12
-/* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CMMU_FORCE_ON  (BIT(11))
-#define DPORT_PRO_CMMU_FORCE_ON_M  (BIT(11))
-#define DPORT_PRO_CMMU_FORCE_ON_V  0x1
-#define DPORT_PRO_CMMU_FORCE_ON_S  11
-/* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_PRO_CMMU_FLASH_PAGE_MODE  0x00000003
-#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M  ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S))
-#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V  0x3
-#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S  9
-/* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */
-/*description: */
-#define DPORT_PRO_CMMU_SRAM_PAGE_MODE  0x00000007
-#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M  ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S))
-#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V  0x7
-#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S  6
-/* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CACHE_MASK_OPSDRAM  (BIT(5))
-#define DPORT_PRO_CACHE_MASK_OPSDRAM_M  (BIT(5))
-#define DPORT_PRO_CACHE_MASK_OPSDRAM_V  0x1
-#define DPORT_PRO_CACHE_MASK_OPSDRAM_S  5
-/* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CACHE_MASK_DROM0  (BIT(4))
-#define DPORT_PRO_CACHE_MASK_DROM0_M  (BIT(4))
-#define DPORT_PRO_CACHE_MASK_DROM0_V  0x1
-#define DPORT_PRO_CACHE_MASK_DROM0_S  4
-/* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CACHE_MASK_DRAM1  (BIT(3))
-#define DPORT_PRO_CACHE_MASK_DRAM1_M  (BIT(3))
-#define DPORT_PRO_CACHE_MASK_DRAM1_V  0x1
-#define DPORT_PRO_CACHE_MASK_DRAM1_S  3
-/* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CACHE_MASK_IROM0  (BIT(2))
-#define DPORT_PRO_CACHE_MASK_IROM0_M  (BIT(2))
-#define DPORT_PRO_CACHE_MASK_IROM0_V  0x1
-#define DPORT_PRO_CACHE_MASK_IROM0_S  2
-/* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CACHE_MASK_IRAM1  (BIT(1))
-#define DPORT_PRO_CACHE_MASK_IRAM1_M  (BIT(1))
-#define DPORT_PRO_CACHE_MASK_IRAM1_V  0x1
-#define DPORT_PRO_CACHE_MASK_IRAM1_S  1
-/* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CACHE_MASK_IRAM0  (BIT(0))
-#define DPORT_PRO_CACHE_MASK_IRAM0_M  (BIT(0))
-#define DPORT_PRO_CACHE_MASK_IRAM0_V  0x1
-#define DPORT_PRO_CACHE_MASK_IRAM0_S  0
-
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_REG          (DR_REG_DPORT_BASE + 0x048)
-/* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX  0x0000000F
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M  ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S))
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V  0xF
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S  18
-/* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN  0x0000000F
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M  ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S))
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V  0xF
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S  14
-/* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE  0x00003FFF
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M  ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S))
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V  0x3FFF
-#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S  0
-
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_REG          (DR_REG_DPORT_BASE + 0x04C)
-/* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX  0x0000000F
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M  ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S))
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V  0xF
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S  18
-/* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN  0x0000000F
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M  ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S))
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V  0xF
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S  14
-/* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE  0x00003FFF
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M  ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S))
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V  0x3FFF
-#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S  0
-
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_REG          (DR_REG_DPORT_BASE + 0x050)
-/* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX  0x0000000F
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M  ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S))
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V  0xF
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S  18
-/* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN  0x0000000F
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M  ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S))
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V  0xF
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S  14
-/* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE  0x00003FFF
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M  ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S))
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V  0x3FFF
-#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S  0
-
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_REG          (DR_REG_DPORT_BASE + 0x054)
-/* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX  0x0000000F
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M  ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S))
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V  0xF
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S  18
-/* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN  0x0000000F
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M  ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S))
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V  0xF
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S  14
-/* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE  0x00003FFF
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M  ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S))
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V  0x3FFF
-#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S  0
-
-#define DPORT_APP_CACHE_CTRL_REG          (DR_REG_DPORT_BASE + 0x058)
-/* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_DRAM_HL  (BIT(14))
-#define DPORT_APP_DRAM_HL_M  (BIT(14))
-#define DPORT_APP_DRAM_HL_V  0x1
-#define DPORT_APP_DRAM_HL_S  14
-/* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_SLAVE_REQ  (BIT(13))
-#define DPORT_APP_SLAVE_REQ_M  (BIT(13))
-#define DPORT_APP_SLAVE_REQ_V  0x1
-#define DPORT_APP_SLAVE_REQ_S  13
-/* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_AHB_SPI_REQ  (BIT(12))
-#define DPORT_APP_AHB_SPI_REQ_M  (BIT(12))
-#define DPORT_APP_AHB_SPI_REQ_V  0x1
-#define DPORT_APP_AHB_SPI_REQ_S  12
-/* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_DRAM_SPLIT  (BIT(11))
-#define DPORT_APP_DRAM_SPLIT_M  (BIT(11))
-#define DPORT_APP_DRAM_SPLIT_V  0x1
-#define DPORT_APP_DRAM_SPLIT_S  11
-/* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_SINGLE_IRAM_ENA  (BIT(10))
-#define DPORT_APP_SINGLE_IRAM_ENA_M  (BIT(10))
-#define DPORT_APP_SINGLE_IRAM_ENA_V  0x1
-#define DPORT_APP_SINGLE_IRAM_ENA_S  10
-/* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_3_EN  (BIT(9))
-#define DPORT_APP_CACHE_LOCK_3_EN_M  (BIT(9))
-#define DPORT_APP_CACHE_LOCK_3_EN_V  0x1
-#define DPORT_APP_CACHE_LOCK_3_EN_S  9
-/* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_2_EN  (BIT(8))
-#define DPORT_APP_CACHE_LOCK_2_EN_M  (BIT(8))
-#define DPORT_APP_CACHE_LOCK_2_EN_V  0x1
-#define DPORT_APP_CACHE_LOCK_2_EN_S  8
-/* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_1_EN  (BIT(7))
-#define DPORT_APP_CACHE_LOCK_1_EN_M  (BIT(7))
-#define DPORT_APP_CACHE_LOCK_1_EN_V  0x1
-#define DPORT_APP_CACHE_LOCK_1_EN_S  7
-/* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_0_EN  (BIT(6))
-#define DPORT_APP_CACHE_LOCK_0_EN_M  (BIT(6))
-#define DPORT_APP_CACHE_LOCK_0_EN_V  0x1
-#define DPORT_APP_CACHE_LOCK_0_EN_S  6
-/* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_FLUSH_DONE  (BIT(5))
-#define DPORT_APP_CACHE_FLUSH_DONE_M  (BIT(5))
-#define DPORT_APP_CACHE_FLUSH_DONE_V  0x1
-#define DPORT_APP_CACHE_FLUSH_DONE_S  5
-/* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CACHE_FLUSH_ENA  (BIT(4))
-#define DPORT_APP_CACHE_FLUSH_ENA_M  (BIT(4))
-#define DPORT_APP_CACHE_FLUSH_ENA_V  0x1
-#define DPORT_APP_CACHE_FLUSH_ENA_S  4
-/* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_ENABLE  (BIT(3))
-#define DPORT_APP_CACHE_ENABLE_M  (BIT(3))
-#define DPORT_APP_CACHE_ENABLE_V  0x1
-#define DPORT_APP_CACHE_ENABLE_S  3
-/* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_MODE  (BIT(2))
-#define DPORT_APP_CACHE_MODE_M  (BIT(2))
-#define DPORT_APP_CACHE_MODE_V  0x1
-#define DPORT_APP_CACHE_MODE_S  2
-
-#define DPORT_APP_CACHE_CTRL1_REG          (DR_REG_DPORT_BASE + 0x05C)
-/* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_MMU_IA_CLR  (BIT(13))
-#define DPORT_APP_CACHE_MMU_IA_CLR_M  (BIT(13))
-#define DPORT_APP_CACHE_MMU_IA_CLR_V  0x1
-#define DPORT_APP_CACHE_MMU_IA_CLR_S  13
-/* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CMMU_PD  (BIT(12))
-#define DPORT_APP_CMMU_PD_M  (BIT(12))
-#define DPORT_APP_CMMU_PD_V  0x1
-#define DPORT_APP_CMMU_PD_S  12
-/* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CMMU_FORCE_ON  (BIT(11))
-#define DPORT_APP_CMMU_FORCE_ON_M  (BIT(11))
-#define DPORT_APP_CMMU_FORCE_ON_V  0x1
-#define DPORT_APP_CMMU_FORCE_ON_S  11
-/* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_APP_CMMU_FLASH_PAGE_MODE  0x00000003
-#define DPORT_APP_CMMU_FLASH_PAGE_MODE_M  ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S))
-#define DPORT_APP_CMMU_FLASH_PAGE_MODE_V  0x3
-#define DPORT_APP_CMMU_FLASH_PAGE_MODE_S  9
-/* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */
-/*description: */
-#define DPORT_APP_CMMU_SRAM_PAGE_MODE  0x00000007
-#define DPORT_APP_CMMU_SRAM_PAGE_MODE_M  ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S))
-#define DPORT_APP_CMMU_SRAM_PAGE_MODE_V  0x7
-#define DPORT_APP_CMMU_SRAM_PAGE_MODE_S  6
-/* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CACHE_MASK_OPSDRAM  (BIT(5))
-#define DPORT_APP_CACHE_MASK_OPSDRAM_M  (BIT(5))
-#define DPORT_APP_CACHE_MASK_OPSDRAM_V  0x1
-#define DPORT_APP_CACHE_MASK_OPSDRAM_S  5
-/* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CACHE_MASK_DROM0  (BIT(4))
-#define DPORT_APP_CACHE_MASK_DROM0_M  (BIT(4))
-#define DPORT_APP_CACHE_MASK_DROM0_V  0x1
-#define DPORT_APP_CACHE_MASK_DROM0_S  4
-/* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CACHE_MASK_DRAM1  (BIT(3))
-#define DPORT_APP_CACHE_MASK_DRAM1_M  (BIT(3))
-#define DPORT_APP_CACHE_MASK_DRAM1_V  0x1
-#define DPORT_APP_CACHE_MASK_DRAM1_S  3
-/* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CACHE_MASK_IROM0  (BIT(2))
-#define DPORT_APP_CACHE_MASK_IROM0_M  (BIT(2))
-#define DPORT_APP_CACHE_MASK_IROM0_V  0x1
-#define DPORT_APP_CACHE_MASK_IROM0_S  2
-/* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CACHE_MASK_IRAM1  (BIT(1))
-#define DPORT_APP_CACHE_MASK_IRAM1_M  (BIT(1))
-#define DPORT_APP_CACHE_MASK_IRAM1_V  0x1
-#define DPORT_APP_CACHE_MASK_IRAM1_S  1
-/* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CACHE_MASK_IRAM0  (BIT(0))
-#define DPORT_APP_CACHE_MASK_IRAM0_M  (BIT(0))
-#define DPORT_APP_CACHE_MASK_IRAM0_V  0x1
-#define DPORT_APP_CACHE_MASK_IRAM0_S  0
-
-#define DPORT_APP_CACHE_LOCK_0_ADDR_REG          (DR_REG_DPORT_BASE + 0x060)
-/* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX  0x0000000F
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M  ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S))
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V  0xF
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S  18
-/* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN  0x0000000F
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M  ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S))
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V  0xF
-#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S  14
-/* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE  0x00003FFF
-#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M  ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S))
-#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V  0x3FFF
-#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S  0
-
-#define DPORT_APP_CACHE_LOCK_1_ADDR_REG          (DR_REG_DPORT_BASE + 0x064)
-/* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX  0x0000000F
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M  ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S))
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V  0xF
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S  18
-/* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN  0x0000000F
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M  ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S))
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V  0xF
-#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S  14
-/* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE  0x00003FFF
-#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M  ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S))
-#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V  0x3FFF
-#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S  0
-
-#define DPORT_APP_CACHE_LOCK_2_ADDR_REG          (DR_REG_DPORT_BASE + 0x068)
-/* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX  0x0000000F
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M  ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S))
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V  0xF
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S  18
-/* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN  0x0000000F
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M  ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S))
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V  0xF
-#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S  14
-/* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE  0x00003FFF
-#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M  ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S))
-#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V  0x3FFF
-#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S  0
-
-#define DPORT_APP_CACHE_LOCK_3_ADDR_REG          (DR_REG_DPORT_BASE + 0x06C)
-/* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX  0x0000000F
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M  ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S))
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V  0xF
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S  18
-/* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN  0x0000000F
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M  ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S))
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V  0xF
-#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S  14
-/* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE  0x00003FFF
-#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M  ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S))
-#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V  0x3FFF
-#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S  0
-
-#define DPORT_TRACEMEM_MUX_MODE_REG          (DR_REG_DPORT_BASE + 0x070)
-/* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_TRACEMEM_MUX_MODE  0x00000003
-#define DPORT_TRACEMEM_MUX_MODE_M  ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S))
-#define DPORT_TRACEMEM_MUX_MODE_V  0x3
-#define DPORT_TRACEMEM_MUX_MODE_S  0
-
-#define DPORT_PRO_TRACEMEM_ENA_REG          (DR_REG_DPORT_BASE + 0x074)
-/* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_TRACEMEM_ENA  (BIT(0))
-#define DPORT_PRO_TRACEMEM_ENA_M  (BIT(0))
-#define DPORT_PRO_TRACEMEM_ENA_V  0x1
-#define DPORT_PRO_TRACEMEM_ENA_S  0
-
-#define DPORT_APP_TRACEMEM_ENA_REG          (DR_REG_DPORT_BASE + 0x078)
-/* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_TRACEMEM_ENA  (BIT(0))
-#define DPORT_APP_TRACEMEM_ENA_M  (BIT(0))
-#define DPORT_APP_TRACEMEM_ENA_V  0x1
-#define DPORT_APP_TRACEMEM_ENA_S  0
-
-#define DPORT_CACHE_MUX_MODE_REG          (DR_REG_DPORT_BASE + 0x07C)
-/* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_CACHE_MUX_MODE  0x00000003
-#define DPORT_CACHE_MUX_MODE_M  ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S))
-#define DPORT_CACHE_MUX_MODE_V  0x3
-#define DPORT_CACHE_MUX_MODE_S  0
-
-#define DPORT_IMMU_PAGE_MODE_REG          (DR_REG_DPORT_BASE + 0x080)
-/* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_IMMU_PAGE_MODE  0x00000003
-#define DPORT_IMMU_PAGE_MODE_M  ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S))
-#define DPORT_IMMU_PAGE_MODE_V  0x3
-#define DPORT_IMMU_PAGE_MODE_S  1
-/* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_INTERNAL_SRAM_IMMU_ENA  (BIT(0))
-#define DPORT_INTERNAL_SRAM_IMMU_ENA_M  (BIT(0))
-#define DPORT_INTERNAL_SRAM_IMMU_ENA_V  0x1
-#define DPORT_INTERNAL_SRAM_IMMU_ENA_S  0
-
-#define DPORT_DMMU_PAGE_MODE_REG          (DR_REG_DPORT_BASE + 0x084)
-/* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_DMMU_PAGE_MODE  0x00000003
-#define DPORT_DMMU_PAGE_MODE_M  ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S))
-#define DPORT_DMMU_PAGE_MODE_V  0x3
-#define DPORT_DMMU_PAGE_MODE_S  1
-/* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_INTERNAL_SRAM_DMMU_ENA  (BIT(0))
-#define DPORT_INTERNAL_SRAM_DMMU_ENA_M  (BIT(0))
-#define DPORT_INTERNAL_SRAM_DMMU_ENA_V  0x1
-#define DPORT_INTERNAL_SRAM_DMMU_ENA_S  0
-
-#define DPORT_ROM_MPU_ENA_REG          (DR_REG_DPORT_BASE + 0x088)
-/* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_ROM_MPU_ENA  (BIT(2))
-#define DPORT_APP_ROM_MPU_ENA_M  (BIT(2))
-#define DPORT_APP_ROM_MPU_ENA_V  0x1
-#define DPORT_APP_ROM_MPU_ENA_S  2
-/* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_ROM_MPU_ENA  (BIT(1))
-#define DPORT_PRO_ROM_MPU_ENA_M  (BIT(1))
-#define DPORT_PRO_ROM_MPU_ENA_V  0x1
-#define DPORT_PRO_ROM_MPU_ENA_S  1
-/* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_SHARE_ROM_MPU_ENA  (BIT(0))
-#define DPORT_SHARE_ROM_MPU_ENA_M  (BIT(0))
-#define DPORT_SHARE_ROM_MPU_ENA_V  0x1
-#define DPORT_SHARE_ROM_MPU_ENA_S  0
-
-#define DPORT_MEM_PD_MASK_REG          (DR_REG_DPORT_BASE + 0x08C)
-/* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_LSLP_MEM_PD_MASK  (BIT(0))
-#define DPORT_LSLP_MEM_PD_MASK_M  (BIT(0))
-#define DPORT_LSLP_MEM_PD_MASK_V  0x1
-#define DPORT_LSLP_MEM_PD_MASK_S  0
-
-#define DPORT_ROM_PD_CTRL_REG          (DR_REG_DPORT_BASE + 0x090)
-/* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */
-/*description: */
-#define DPORT_SHARE_ROM_PD  0x0000003F
-#define DPORT_SHARE_ROM_PD_M  ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S))
-#define DPORT_SHARE_ROM_PD_V  0x3F
-#define DPORT_SHARE_ROM_PD_S  2
-/* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: */
-#define DPORT_APP_ROM_PD  (BIT(1))
-#define DPORT_APP_ROM_PD_M  (BIT(1))
-#define DPORT_APP_ROM_PD_V  0x1
-#define DPORT_APP_ROM_PD_S  1
-/* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define DPORT_PRO_ROM_PD  (BIT(0))
-#define DPORT_PRO_ROM_PD_M  (BIT(0))
-#define DPORT_PRO_ROM_PD_V  0x1
-#define DPORT_PRO_ROM_PD_S  0
-
-#define DPORT_ROM_FO_CTRL_REG          (DR_REG_DPORT_BASE + 0x094)
-/* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */
-/*description: */
-#define DPORT_SHARE_ROM_FO  0x0000003F
-#define DPORT_SHARE_ROM_FO_M  ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S))
-#define DPORT_SHARE_ROM_FO_V  0x3F
-#define DPORT_SHARE_ROM_FO_S  2
-/* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: */
-#define DPORT_APP_ROM_FO  (BIT(1))
-#define DPORT_APP_ROM_FO_M  (BIT(1))
-#define DPORT_APP_ROM_FO_V  0x1
-#define DPORT_APP_ROM_FO_S  1
-/* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: */
-#define DPORT_PRO_ROM_FO  (BIT(0))
-#define DPORT_PRO_ROM_FO_M  (BIT(0))
-#define DPORT_PRO_ROM_FO_V  0x1
-#define DPORT_PRO_ROM_FO_S  0
-
-#define DPORT_SRAM_PD_CTRL_0_REG          (DR_REG_DPORT_BASE + 0x098)
-/* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_SRAM_PD_0  0xFFFFFFFF
-#define DPORT_SRAM_PD_0_M  ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S))
-#define DPORT_SRAM_PD_0_V  0xFFFFFFFF
-#define DPORT_SRAM_PD_0_S  0
-
-#define DPORT_SRAM_PD_CTRL_1_REG          (DR_REG_DPORT_BASE + 0x09C)
-/* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define DPORT_SRAM_PD_1  (BIT(0))
-#define DPORT_SRAM_PD_1_M  (BIT(0))
-#define DPORT_SRAM_PD_1_V  0x1
-#define DPORT_SRAM_PD_1_S  0
-
-#define DPORT_SRAM_FO_CTRL_0_REG          (DR_REG_DPORT_BASE + 0x0A0)
-/* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define DPORT_SRAM_FO_0  0xFFFFFFFF
-#define DPORT_SRAM_FO_0_M  ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S))
-#define DPORT_SRAM_FO_0_V  0xFFFFFFFF
-#define DPORT_SRAM_FO_0_S  0
-
-#define DPORT_SRAM_FO_CTRL_1_REG          (DR_REG_DPORT_BASE + 0x0A4)
-/* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: */
-#define DPORT_SRAM_FO_1  (BIT(0))
-#define DPORT_SRAM_FO_1_M  (BIT(0))
-#define DPORT_SRAM_FO_1_V  0x1
-#define DPORT_SRAM_FO_1_S  0
-
-#define DPORT_IRAM_DRAM_AHB_SEL_REG          (DR_REG_DPORT_BASE + 0x0A8)
-/* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */
-/*description: */
-#define DPORT_MAC_DUMP_MODE  0x00000003
-#define DPORT_MAC_DUMP_MODE_M  ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S))
-#define DPORT_MAC_DUMP_MODE_V  0x3
-#define DPORT_MAC_DUMP_MODE_S  5
-/* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_MASK_AHB  (BIT(4))
-#define DPORT_MASK_AHB_M  (BIT(4))
-#define DPORT_MASK_AHB_V  0x1
-#define DPORT_MASK_AHB_S  4
-/* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_MASK_APP_DRAM  (BIT(3))
-#define DPORT_MASK_APP_DRAM_M  (BIT(3))
-#define DPORT_MASK_APP_DRAM_V  0x1
-#define DPORT_MASK_APP_DRAM_S  3
-/* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_MASK_PRO_DRAM  (BIT(2))
-#define DPORT_MASK_PRO_DRAM_M  (BIT(2))
-#define DPORT_MASK_PRO_DRAM_V  0x1
-#define DPORT_MASK_PRO_DRAM_S  2
-/* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_MASK_APP_IRAM  (BIT(1))
-#define DPORT_MASK_APP_IRAM_M  (BIT(1))
-#define DPORT_MASK_APP_IRAM_V  0x1
-#define DPORT_MASK_APP_IRAM_S  1
-/* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_MASK_PRO_IRAM  (BIT(0))
-#define DPORT_MASK_PRO_IRAM_M  (BIT(0))
-#define DPORT_MASK_PRO_IRAM_V  0x1
-#define DPORT_MASK_PRO_IRAM_S  0
-
-#define DPORT_TAG_FO_CTRL_REG          (DR_REG_DPORT_BASE + 0x0AC)
-/* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_TAG_PD  (BIT(9))
-#define DPORT_APP_CACHE_TAG_PD_M  (BIT(9))
-#define DPORT_APP_CACHE_TAG_PD_V  0x1
-#define DPORT_APP_CACHE_TAG_PD_S  9
-/* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CACHE_TAG_FORCE_ON  (BIT(8))
-#define DPORT_APP_CACHE_TAG_FORCE_ON_M  (BIT(8))
-#define DPORT_APP_CACHE_TAG_FORCE_ON_V  0x1
-#define DPORT_APP_CACHE_TAG_FORCE_ON_S  8
-/* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_TAG_PD  (BIT(1))
-#define DPORT_PRO_CACHE_TAG_PD_M  (BIT(1))
-#define DPORT_PRO_CACHE_TAG_PD_V  0x1
-#define DPORT_PRO_CACHE_TAG_PD_S  1
-/* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CACHE_TAG_FORCE_ON  (BIT(0))
-#define DPORT_PRO_CACHE_TAG_FORCE_ON_M  (BIT(0))
-#define DPORT_PRO_CACHE_TAG_FORCE_ON_V  0x1
-#define DPORT_PRO_CACHE_TAG_FORCE_ON_S  0
-
-#define DPORT_AHB_LITE_MASK_REG          (DR_REG_DPORT_BASE + 0x0B0)
-/* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */
-/*description: */
-#define DPORT_AHB_LITE_SDHOST_PID_REG  0x00000007
-#define DPORT_AHB_LITE_SDHOST_PID_REG_M  ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S))
-#define DPORT_AHB_LITE_SDHOST_PID_REG_V  0x7
-#define DPORT_AHB_LITE_SDHOST_PID_REG_S  11
-/* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AHB_LITE_MASK_APPDPORT  (BIT(10))
-#define DPORT_AHB_LITE_MASK_APPDPORT_M  (BIT(10))
-#define DPORT_AHB_LITE_MASK_APPDPORT_V  0x1
-#define DPORT_AHB_LITE_MASK_APPDPORT_S  10
-/* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AHB_LITE_MASK_PRODPORT  (BIT(9))
-#define DPORT_AHB_LITE_MASK_PRODPORT_M  (BIT(9))
-#define DPORT_AHB_LITE_MASK_PRODPORT_V  0x1
-#define DPORT_AHB_LITE_MASK_PRODPORT_S  9
-/* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AHB_LITE_MASK_SDIO  (BIT(8))
-#define DPORT_AHB_LITE_MASK_SDIO_M  (BIT(8))
-#define DPORT_AHB_LITE_MASK_SDIO_V  0x1
-#define DPORT_AHB_LITE_MASK_SDIO_S  8
-/* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AHB_LITE_MASK_APP  (BIT(4))
-#define DPORT_AHB_LITE_MASK_APP_M  (BIT(4))
-#define DPORT_AHB_LITE_MASK_APP_V  0x1
-#define DPORT_AHB_LITE_MASK_APP_S  4
-/* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AHB_LITE_MASK_PRO  (BIT(0))
-#define DPORT_AHB_LITE_MASK_PRO_M  (BIT(0))
-#define DPORT_AHB_LITE_MASK_PRO_V  0x1
-#define DPORT_AHB_LITE_MASK_PRO_S  0
-
-#define DPORT_AHB_MPU_TABLE_0_REG          (DR_REG_DPORT_BASE + 0x0B4)
-/* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define DPORT_AHB_ACCESS_GRANT_0  0xFFFFFFFF
-#define DPORT_AHB_ACCESS_GRANT_0_M  ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S))
-#define DPORT_AHB_ACCESS_GRANT_0_V  0xFFFFFFFF
-#define DPORT_AHB_ACCESS_GRANT_0_S  0
-
-#define DPORT_AHB_MPU_TABLE_1_REG          (DR_REG_DPORT_BASE + 0x0B8)
-/* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */
-/*description: */
-#define DPORT_AHB_ACCESS_GRANT_1  0x000001FF
-#define DPORT_AHB_ACCESS_GRANT_1_M  ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S))
-#define DPORT_AHB_ACCESS_GRANT_1_V  0x1FF
-#define DPORT_AHB_ACCESS_GRANT_1_S  0
-
-#define DPORT_HOST_INF_SEL_REG          (DR_REG_DPORT_BASE + 0x0BC)
-/* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define DPORT_LINK_DEVICE_SEL  0x000000FF
-#define DPORT_LINK_DEVICE_SEL_M  ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S))
-#define DPORT_LINK_DEVICE_SEL_V  0xFF
-#define DPORT_LINK_DEVICE_SEL_S  8
-/* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define DPORT_PERI_IO_SWAP  0x000000FF
-#define DPORT_PERI_IO_SWAP_M  ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S))
-#define DPORT_PERI_IO_SWAP_V  0xFF
-#define DPORT_PERI_IO_SWAP_S  0
-
-#define DPORT_PERIP_CLK_EN_REG          (DR_REG_DPORT_BASE + 0x0C0)
-/* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */
-/*description: */
-#define DPORT_PERIP_CLK_EN  0xFFFFFFFF
-#define DPORT_PERIP_CLK_EN_M  ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S))
-#define DPORT_PERIP_CLK_EN_V  0xFFFFFFFF
-#define DPORT_PERIP_CLK_EN_S  0
-
-#define DPORT_PWM3_CLK_EN (BIT(26))
-#define DPORT_PWM2_CLK_EN (BIT(25))
-#define DPORT_UART_MEM_CLK_EN   (BIT(24))
-#define DPORT_UART2_CLK_EN   (BIT(23))
-#define DPORT_SPI_DMA_CLK_EN   (BIT(22))
-#define DPORT_I2S1_CLK_EN   (BIT(21))
-#define DPORT_PWM1_CLK_EN   (BIT(20))
-#define DPORT_CAN_CLK_EN   (BIT(19))
-#define DPORT_I2C_EXT1_CLK_EN   (BIT(18))
-#define DPORT_PWM0_CLK_EN   (BIT(17))
-#define DPORT_SPI_CLK_EN_2   (BIT(16)) /** Deprecated, please use DPORT_SPI3_CLK_EN **/
-#define DPORT_SPI3_CLK_EN   (BIT(16))
-#define DPORT_TIMERGROUP1_CLK_EN   (BIT(15))
-#define DPORT_EFUSE_CLK_EN   (BIT(14))
-#define DPORT_TIMERGROUP_CLK_EN   (BIT(13))
-#define DPORT_UHCI1_CLK_EN   (BIT(12))
-#define DPORT_LEDC_CLK_EN   (BIT(11))
-#define DPORT_PCNT_CLK_EN   (BIT(10))
-#define DPORT_RMT_CLK_EN   (BIT(9))
-#define DPORT_UHCI0_CLK_EN   (BIT(8))
-#define DPORT_I2C_EXT0_CLK_EN   (BIT(7))
-#define DPORT_SPI_CLK_EN   (BIT(6)) /** Deprecated, please use DPORT_SPI2_CLK_EN **/
-#define DPORT_SPI2_CLK_EN   (BIT(6))
-#define DPORT_UART1_CLK_EN   (BIT(5))
-#define DPORT_I2S0_CLK_EN   (BIT(4))
-#define DPORT_WDG_CLK_EN   (BIT(3))
-#define DPORT_UART_CLK_EN   (BIT(2))
-#define DPORT_SPI_CLK_EN_1   (BIT(1)) /** Deprecated, please use DPORT_SPI01_CLK_EN **/
-#define DPORT_SPI01_CLK_EN   (BIT(1))
-#define DPORT_TIMERS_CLK_EN   (BIT(0))
-#define DPORT_PERIP_RST_EN_REG          (DR_REG_DPORT_BASE + 0x0C4)
-/* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_PERIP_RST  0xFFFFFFFF
-#define DPORT_PERIP_RST_M  ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S))
-#define DPORT_PERIP_RST_V  0xFFFFFFFF
-#define DPORT_PERIP_RST_S  0
-#define DPORT_PWM3_RST (BIT(26))
-#define DPORT_PWM2_RST (BIT(25))
-#define DPORT_UART_MEM_RST   (BIT(24))
-#define DPORT_UART2_RST   (BIT(23))
-#define DPORT_SPI_DMA_RST   (BIT(22))
-#define DPORT_I2S1_RST   (BIT(21))
-#define DPORT_PWM1_RST   (BIT(20))
-#define DPORT_CAN_RST   (BIT(19))
-#define DPORT_I2C_EXT1_RST   (BIT(18))
-#define DPORT_PWM0_RST   (BIT(17))
-#define DPORT_SPI_RST_2   (BIT(16)) /** Deprecated, please use DPORT_SPI3_RST **/
-#define DPORT_SPI3_RST   (BIT(16))
-#define DPORT_TIMERGROUP1_RST   (BIT(15))
-#define DPORT_EFUSE_RST   (BIT(14))
-#define DPORT_TIMERGROUP_RST   (BIT(13))
-#define DPORT_UHCI1_RST   (BIT(12))
-#define DPORT_LEDC_RST   (BIT(11))
-#define DPORT_PCNT_RST   (BIT(10))
-#define DPORT_RMT_RST   (BIT(9))
-#define DPORT_UHCI0_RST   (BIT(8))
-#define DPORT_I2C_EXT0_RST   (BIT(7))
-#define DPORT_SPI_RST   (BIT(6)) /** Deprecated, please use DPORT_SPI2_RST **/
-#define DPORT_SPI2_RST   (BIT(6))
-#define DPORT_UART1_RST   (BIT(5))
-#define DPORT_I2S0_RST   (BIT(4))
-#define DPORT_WDG_RST   (BIT(3))
-#define DPORT_UART_RST   (BIT(2))
-#define DPORT_SPI_RST_1   (BIT(1)) /** Deprecated, please use DPORT_SPI01_RST **/
-#define DPORT_SPI01_RST   (BIT(1))
-#define DPORT_TIMERS_RST   (BIT(0))
-#define DPORT_SLAVE_SPI_CONFIG_REG          (DR_REG_DPORT_BASE + 0x0C8)
-/* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_SPI_DECRYPT_ENABLE  (BIT(12))
-#define DPORT_SPI_DECRYPT_ENABLE_M  (BIT(12))
-#define DPORT_SPI_DECRYPT_ENABLE_V  0x1
-#define DPORT_SPI_DECRYPT_ENABLE_S  12
-/* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_SPI_ENCRYPT_ENABLE  (BIT(8))
-#define DPORT_SPI_ENCRYPT_ENABLE_M  (BIT(8))
-#define DPORT_SPI_ENCRYPT_ENABLE_V  0x1
-#define DPORT_SPI_ENCRYPT_ENABLE_S  8
-/* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_SLAVE_SPI_MASK_APP  (BIT(4))
-#define DPORT_SLAVE_SPI_MASK_APP_M  (BIT(4))
-#define DPORT_SLAVE_SPI_MASK_APP_V  0x1
-#define DPORT_SLAVE_SPI_MASK_APP_S  4
-/* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_SLAVE_SPI_MASK_PRO  (BIT(0))
-#define DPORT_SLAVE_SPI_MASK_PRO_M  (BIT(0))
-#define DPORT_SLAVE_SPI_MASK_PRO_V  0x1
-#define DPORT_SLAVE_SPI_MASK_PRO_S  0
-
-#define DPORT_WIFI_CLK_EN_REG          (DR_REG_DPORT_BASE + 0x0CC)
-/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
-/*description: */
-#define DPORT_WIFI_CLK_EN  0xFFFFFFFF
-#define DPORT_WIFI_CLK_EN_M  ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S))
-#define DPORT_WIFI_CLK_EN_V  0xFFFFFFFF
-#define DPORT_WIFI_CLK_EN_S  0
-
-/* Mask for all Wifi clock bits - 1, 2, 10 */
-#define DPORT_WIFI_CLK_WIFI_EN  0x00000406
-#define DPORT_WIFI_CLK_WIFI_EN_M  ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
-#define DPORT_WIFI_CLK_WIFI_EN_V  0x406
-#define DPORT_WIFI_CLK_WIFI_EN_S  0
-/* Mask for all Bluetooth clock bits - 11, 16, 17 */
-#define DPORT_WIFI_CLK_BT_EN  0x61
-#define DPORT_WIFI_CLK_BT_EN_M  ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S))
-#define DPORT_WIFI_CLK_BT_EN_V  0x61
-#define DPORT_WIFI_CLK_BT_EN_S  11
-/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
-#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
-//bluetooth baseband bit11
-#define DPORT_BT_BASEBAND_EN  BIT(11)
-//bluetooth LC bit16 and bit17
-#define DPORT_BT_LC_EN  (BIT(16)|BIT(17))
-
-/* Remaining single bit clock masks */
-#define DPORT_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
-#define DPORT_WIFI_CLK_UNUSED_BIT5  BIT(5)
-#define DPORT_WIFI_CLK_UNUSED_BIT12  BIT(12)
-#define DPORT_WIFI_CLK_SDIO_HOST_EN  BIT(13)
-#define DPORT_WIFI_CLK_EMAC_EN  BIT(14)
-#define DPORT_WIFI_CLK_RNG_EN  BIT(15)
-
-#define DPORT_CORE_RST_EN_REG          (DR_REG_DPORT_BASE + 0x0D0)
-/* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_RW_BTLP_RST (BIT(10))
-#define DPORT_RW_BTMAC_RST (BIT(9))
-#define DPORT_MACPWR_RST (BIT(8))
-#define DPORT_EMAC_RST (BIT(7))
-#define DPORT_SDIO_HOST_RST (BIT(6))
-#define DPORT_SDIO_RST (BIT(5))
-#define DPORT_BTMAC_RST (BIT(4))
-#define DPORT_BT_RST (BIT(3))
-#define DPORT_MAC_RST (BIT(2))
-#define DPORT_FE_RST (BIT(1))
-#define DPORT_BB_RST (BIT(0))  
-
-#define DPORT_BT_LPCK_DIV_INT_REG          (DR_REG_DPORT_BASE + 0x0D4)
-/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_BTEXTWAKEUP_REQ  (BIT(12))
-#define DPORT_BTEXTWAKEUP_REQ_M  (BIT(12))
-#define DPORT_BTEXTWAKEUP_REQ_V  0x1
-#define DPORT_BTEXTWAKEUP_REQ_S  12
-/* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
-/*description: */
-#define DPORT_BT_LPCK_DIV_NUM  0x00000FFF
-#define DPORT_BT_LPCK_DIV_NUM_M  ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S))
-#define DPORT_BT_LPCK_DIV_NUM_V  0xFFF
-#define DPORT_BT_LPCK_DIV_NUM_S  0
-
-#define DPORT_BT_LPCK_DIV_FRAC_REG          (DR_REG_DPORT_BASE + 0x0D8)
-/* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_LPCLK_SEL_XTAL32K  (BIT(27))
-#define DPORT_LPCLK_SEL_XTAL32K_M  (BIT(27))
-#define DPORT_LPCLK_SEL_XTAL32K_V  0x1
-#define DPORT_LPCLK_SEL_XTAL32K_S  27
-/* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_LPCLK_SEL_XTAL  (BIT(26))
-#define DPORT_LPCLK_SEL_XTAL_M  (BIT(26))
-#define DPORT_LPCLK_SEL_XTAL_V  0x1
-#define DPORT_LPCLK_SEL_XTAL_S  26
-/* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_LPCLK_SEL_8M  (BIT(25))
-#define DPORT_LPCLK_SEL_8M_M  (BIT(25))
-#define DPORT_LPCLK_SEL_8M_V  0x1
-#define DPORT_LPCLK_SEL_8M_S  25
-/* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_LPCLK_SEL_RTC_SLOW  (BIT(24))
-#define DPORT_LPCLK_SEL_RTC_SLOW_M  (BIT(24))
-#define DPORT_LPCLK_SEL_RTC_SLOW_V  0x1
-#define DPORT_LPCLK_SEL_RTC_SLOW_S  24
-/* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
-/*description: */
-#define DPORT_BT_LPCK_DIV_A  0x00000FFF
-#define DPORT_BT_LPCK_DIV_A_M  ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S))
-#define DPORT_BT_LPCK_DIV_A_V  0xFFF
-#define DPORT_BT_LPCK_DIV_A_S  12
-/* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
-/*description: */
-#define DPORT_BT_LPCK_DIV_B  0x00000FFF
-#define DPORT_BT_LPCK_DIV_B_M  ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S))
-#define DPORT_BT_LPCK_DIV_B_V  0xFFF
-#define DPORT_BT_LPCK_DIV_B_S  0
-
-#define DPORT_CPU_INTR_FROM_CPU_0_REG          (DR_REG_DPORT_BASE + 0x0DC)
-/* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_CPU_INTR_FROM_CPU_0  (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_0_M  (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_0_V  0x1
-#define DPORT_CPU_INTR_FROM_CPU_0_S  0
-
-#define DPORT_CPU_INTR_FROM_CPU_1_REG          (DR_REG_DPORT_BASE + 0x0E0)
-/* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_CPU_INTR_FROM_CPU_1  (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_1_M  (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_1_V  0x1
-#define DPORT_CPU_INTR_FROM_CPU_1_S  0
-
-#define DPORT_CPU_INTR_FROM_CPU_2_REG          (DR_REG_DPORT_BASE + 0x0E4)
-/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_CPU_INTR_FROM_CPU_2  (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_2_M  (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_2_V  0x1
-#define DPORT_CPU_INTR_FROM_CPU_2_S  0
-
-#define DPORT_CPU_INTR_FROM_CPU_3_REG          (DR_REG_DPORT_BASE + 0x0E8)
-/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_CPU_INTR_FROM_CPU_3  (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_3_M  (BIT(0))
-#define DPORT_CPU_INTR_FROM_CPU_3_V  0x1
-#define DPORT_CPU_INTR_FROM_CPU_3_S  0
-
-#define DPORT_PRO_INTR_STATUS_0_REG          (DR_REG_DPORT_BASE + 0x0EC)
-/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_PRO_INTR_STATUS_0  0xFFFFFFFF
-#define DPORT_PRO_INTR_STATUS_0_M  ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S))
-#define DPORT_PRO_INTR_STATUS_0_V  0xFFFFFFFF
-#define DPORT_PRO_INTR_STATUS_0_S  0
-
-#define DPORT_PRO_INTR_STATUS_1_REG          (DR_REG_DPORT_BASE + 0x0F0)
-/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_PRO_INTR_STATUS_1  0xFFFFFFFF
-#define DPORT_PRO_INTR_STATUS_1_M  ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S))
-#define DPORT_PRO_INTR_STATUS_1_V  0xFFFFFFFF
-#define DPORT_PRO_INTR_STATUS_1_S  0
-
-#define DPORT_PRO_INTR_STATUS_2_REG          (DR_REG_DPORT_BASE + 0x0F4)
-/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_PRO_INTR_STATUS_2  0xFFFFFFFF
-#define DPORT_PRO_INTR_STATUS_2_M  ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S))
-#define DPORT_PRO_INTR_STATUS_2_V  0xFFFFFFFF
-#define DPORT_PRO_INTR_STATUS_2_S  0
-
-#define DPORT_APP_INTR_STATUS_0_REG          (DR_REG_DPORT_BASE + 0x0F8)
-/* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_APP_INTR_STATUS_0  0xFFFFFFFF
-#define DPORT_APP_INTR_STATUS_0_M  ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S))
-#define DPORT_APP_INTR_STATUS_0_V  0xFFFFFFFF
-#define DPORT_APP_INTR_STATUS_0_S  0
-
-#define DPORT_APP_INTR_STATUS_1_REG          (DR_REG_DPORT_BASE + 0x0FC)
-/* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_APP_INTR_STATUS_1  0xFFFFFFFF
-#define DPORT_APP_INTR_STATUS_1_M  ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S))
-#define DPORT_APP_INTR_STATUS_1_V  0xFFFFFFFF
-#define DPORT_APP_INTR_STATUS_1_S  0
-
-#define DPORT_APP_INTR_STATUS_2_REG          (DR_REG_DPORT_BASE + 0x100)
-/* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define DPORT_APP_INTR_STATUS_2  0xFFFFFFFF
-#define DPORT_APP_INTR_STATUS_2_M  ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S))
-#define DPORT_APP_INTR_STATUS_2_V  0xFFFFFFFF
-#define DPORT_APP_INTR_STATUS_2_S  0
-
-#define DPORT_PRO_MAC_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x104)
-/* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_MAC_INTR_MAP  0x0000001F
-#define DPORT_PRO_MAC_INTR_MAP_M  ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S))
-#define DPORT_PRO_MAC_INTR_MAP_V  0x1F
-#define DPORT_PRO_MAC_INTR_MAP_S  0
-
-#define DPORT_PRO_MAC_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x108)
-/* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_MAC_NMI_MAP  0x0000001F
-#define DPORT_PRO_MAC_NMI_MAP_M  ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S))
-#define DPORT_PRO_MAC_NMI_MAP_V  0x1F
-#define DPORT_PRO_MAC_NMI_MAP_S  0
-
-#define DPORT_PRO_BB_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x10C)
-/* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_BB_INT_MAP  0x0000001F
-#define DPORT_PRO_BB_INT_MAP_M  ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S))
-#define DPORT_PRO_BB_INT_MAP_V  0x1F
-#define DPORT_PRO_BB_INT_MAP_S  0
-
-#define DPORT_PRO_BT_MAC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x110)
-/* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_BT_MAC_INT_MAP  0x0000001F
-#define DPORT_PRO_BT_MAC_INT_MAP_M  ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S))
-#define DPORT_PRO_BT_MAC_INT_MAP_V  0x1F
-#define DPORT_PRO_BT_MAC_INT_MAP_S  0
-
-#define DPORT_PRO_BT_BB_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x114)
-/* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_BT_BB_INT_MAP  0x0000001F
-#define DPORT_PRO_BT_BB_INT_MAP_M  ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S))
-#define DPORT_PRO_BT_BB_INT_MAP_V  0x1F
-#define DPORT_PRO_BT_BB_INT_MAP_S  0
-
-#define DPORT_PRO_BT_BB_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x118)
-/* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_BT_BB_NMI_MAP  0x0000001F
-#define DPORT_PRO_BT_BB_NMI_MAP_M  ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S))
-#define DPORT_PRO_BT_BB_NMI_MAP_V  0x1F
-#define DPORT_PRO_BT_BB_NMI_MAP_S  0
-
-#define DPORT_PRO_RWBT_IRQ_MAP_REG          (DR_REG_DPORT_BASE + 0x11C)
-/* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_RWBT_IRQ_MAP  0x0000001F
-#define DPORT_PRO_RWBT_IRQ_MAP_M  ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S))
-#define DPORT_PRO_RWBT_IRQ_MAP_V  0x1F
-#define DPORT_PRO_RWBT_IRQ_MAP_S  0
-
-#define DPORT_PRO_RWBLE_IRQ_MAP_REG          (DR_REG_DPORT_BASE + 0x120)
-/* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_RWBLE_IRQ_MAP  0x0000001F
-#define DPORT_PRO_RWBLE_IRQ_MAP_M  ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S))
-#define DPORT_PRO_RWBLE_IRQ_MAP_V  0x1F
-#define DPORT_PRO_RWBLE_IRQ_MAP_S  0
-
-#define DPORT_PRO_RWBT_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x124)
-/* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_RWBT_NMI_MAP  0x0000001F
-#define DPORT_PRO_RWBT_NMI_MAP_M  ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S))
-#define DPORT_PRO_RWBT_NMI_MAP_V  0x1F
-#define DPORT_PRO_RWBT_NMI_MAP_S  0
-
-#define DPORT_PRO_RWBLE_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x128)
-/* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_RWBLE_NMI_MAP  0x0000001F
-#define DPORT_PRO_RWBLE_NMI_MAP_M  ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S))
-#define DPORT_PRO_RWBLE_NMI_MAP_V  0x1F
-#define DPORT_PRO_RWBLE_NMI_MAP_S  0
-
-#define DPORT_PRO_SLC0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x12C)
-/* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SLC0_INTR_MAP  0x0000001F
-#define DPORT_PRO_SLC0_INTR_MAP_M  ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S))
-#define DPORT_PRO_SLC0_INTR_MAP_V  0x1F
-#define DPORT_PRO_SLC0_INTR_MAP_S  0
-
-#define DPORT_PRO_SLC1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x130)
-/* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SLC1_INTR_MAP  0x0000001F
-#define DPORT_PRO_SLC1_INTR_MAP_M  ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S))
-#define DPORT_PRO_SLC1_INTR_MAP_V  0x1F
-#define DPORT_PRO_SLC1_INTR_MAP_S  0
-
-#define DPORT_PRO_UHCI0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x134)
-/* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_UHCI0_INTR_MAP  0x0000001F
-#define DPORT_PRO_UHCI0_INTR_MAP_M  ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S))
-#define DPORT_PRO_UHCI0_INTR_MAP_V  0x1F
-#define DPORT_PRO_UHCI0_INTR_MAP_S  0
-
-#define DPORT_PRO_UHCI1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x138)
-/* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_UHCI1_INTR_MAP  0x0000001F
-#define DPORT_PRO_UHCI1_INTR_MAP_M  ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S))
-#define DPORT_PRO_UHCI1_INTR_MAP_V  0x1F
-#define DPORT_PRO_UHCI1_INTR_MAP_S  0
-
-#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x13C)
-/* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG_T0_LEVEL_INT_MAP  0x0000001F
-#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S))
-#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V  0x1F
-#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S  0
-
-#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x140)
-/* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG_T1_LEVEL_INT_MAP  0x0000001F
-#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S))
-#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V  0x1F
-#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S  0
-
-#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x144)
-/* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP  0x0000001F
-#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S))
-#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V  0x1F
-#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S  0
-
-#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x148)
-/* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP  0x0000001F
-#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S))
-#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V  0x1F
-#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S  0
-
-#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x14C)
-/* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP  0x0000001F
-#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S))
-#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V  0x1F
-#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S  0
-
-#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x150)
-/* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP  0x0000001F
-#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S))
-#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V  0x1F
-#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S  0
-
-#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x154)
-/* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP  0x0000001F
-#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S))
-#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V  0x1F
-#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S  0
-
-#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x158)
-/* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP  0x0000001F
-#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S))
-#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V  0x1F
-#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S  0
-
-#define DPORT_PRO_GPIO_INTERRUPT_MAP_REG          (DR_REG_DPORT_BASE + 0x15C)
-/* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP  0x0000001F
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M  ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S))
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V  0x1F
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S  0
-
-#define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x160)
-/* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP  0x0000001F
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M  ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S))
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x1F
-#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
-
-#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_DPORT_BASE + 0x164)
-/* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S))
-#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S  0
-
-#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_DPORT_BASE + 0x168)
-/* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S))
-#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S  0
-
-#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_DPORT_BASE + 0x16C)
-/* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S))
-#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S  0
-
-#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_DPORT_BASE + 0x170)
-/* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S))
-#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
-#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S  0
-
-#define DPORT_PRO_SPI_INTR_0_MAP_REG          (DR_REG_DPORT_BASE + 0x174)
-/* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SPI_INTR_0_MAP  0x0000001F
-#define DPORT_PRO_SPI_INTR_0_MAP_M  ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S))
-#define DPORT_PRO_SPI_INTR_0_MAP_V  0x1F
-#define DPORT_PRO_SPI_INTR_0_MAP_S  0
-
-#define DPORT_PRO_SPI_INTR_1_MAP_REG          (DR_REG_DPORT_BASE + 0x178)
-/* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SPI_INTR_1_MAP  0x0000001F
-#define DPORT_PRO_SPI_INTR_1_MAP_M  ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S))
-#define DPORT_PRO_SPI_INTR_1_MAP_V  0x1F
-#define DPORT_PRO_SPI_INTR_1_MAP_S  0
-
-#define DPORT_PRO_SPI_INTR_2_MAP_REG          (DR_REG_DPORT_BASE + 0x17C)
-/* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SPI_INTR_2_MAP  0x0000001F
-#define DPORT_PRO_SPI_INTR_2_MAP_M  ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S))
-#define DPORT_PRO_SPI_INTR_2_MAP_V  0x1F
-#define DPORT_PRO_SPI_INTR_2_MAP_S  0
-
-#define DPORT_PRO_SPI_INTR_3_MAP_REG          (DR_REG_DPORT_BASE + 0x180)
-/* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SPI_INTR_3_MAP  0x0000001F
-#define DPORT_PRO_SPI_INTR_3_MAP_M  ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S))
-#define DPORT_PRO_SPI_INTR_3_MAP_V  0x1F
-#define DPORT_PRO_SPI_INTR_3_MAP_S  0
-
-#define DPORT_PRO_I2S0_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x184)
-/* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_I2S0_INT_MAP  0x0000001F
-#define DPORT_PRO_I2S0_INT_MAP_M  ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S))
-#define DPORT_PRO_I2S0_INT_MAP_V  0x1F
-#define DPORT_PRO_I2S0_INT_MAP_S  0
-
-#define DPORT_PRO_I2S1_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x188)
-/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_I2S1_INT_MAP  0x0000001F
-#define DPORT_PRO_I2S1_INT_MAP_M  ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S))
-#define DPORT_PRO_I2S1_INT_MAP_V  0x1F
-#define DPORT_PRO_I2S1_INT_MAP_S  0
-
-#define DPORT_PRO_UART_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x18C)
-/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_UART_INTR_MAP  0x0000001F
-#define DPORT_PRO_UART_INTR_MAP_M  ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S))
-#define DPORT_PRO_UART_INTR_MAP_V  0x1F
-#define DPORT_PRO_UART_INTR_MAP_S  0
-
-#define DPORT_PRO_UART1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x190)
-/* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_UART1_INTR_MAP  0x0000001F
-#define DPORT_PRO_UART1_INTR_MAP_M  ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S))
-#define DPORT_PRO_UART1_INTR_MAP_V  0x1F
-#define DPORT_PRO_UART1_INTR_MAP_S  0
-
-#define DPORT_PRO_UART2_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x194)
-/* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_UART2_INTR_MAP  0x0000001F
-#define DPORT_PRO_UART2_INTR_MAP_M  ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S))
-#define DPORT_PRO_UART2_INTR_MAP_V  0x1F
-#define DPORT_PRO_UART2_INTR_MAP_S  0
-
-#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG          (DR_REG_DPORT_BASE + 0x198)
-/* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP  0x0000001F
-#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M  ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S))
-#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V  0x1F
-#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S  0
-
-#define DPORT_PRO_EMAC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x19C)
-/* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_EMAC_INT_MAP  0x0000001F
-#define DPORT_PRO_EMAC_INT_MAP_M  ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S))
-#define DPORT_PRO_EMAC_INT_MAP_V  0x1F
-#define DPORT_PRO_EMAC_INT_MAP_S  0
-
-#define DPORT_PRO_PWM0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1A0)
-/* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_PWM0_INTR_MAP  0x0000001F
-#define DPORT_PRO_PWM0_INTR_MAP_M  ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S))
-#define DPORT_PRO_PWM0_INTR_MAP_V  0x1F
-#define DPORT_PRO_PWM0_INTR_MAP_S  0
-
-#define DPORT_PRO_PWM1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1A4)
-/* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_PWM1_INTR_MAP  0x0000001F
-#define DPORT_PRO_PWM1_INTR_MAP_M  ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S))
-#define DPORT_PRO_PWM1_INTR_MAP_V  0x1F
-#define DPORT_PRO_PWM1_INTR_MAP_S  0
-
-#define DPORT_PRO_PWM2_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1A8)
-/* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_PWM2_INTR_MAP  0x0000001F
-#define DPORT_PRO_PWM2_INTR_MAP_M  ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S))
-#define DPORT_PRO_PWM2_INTR_MAP_V  0x1F
-#define DPORT_PRO_PWM2_INTR_MAP_S  0
-
-#define DPORT_PRO_PWM3_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1AC)
-/* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_PWM3_INTR_MAP  0x0000001F
-#define DPORT_PRO_PWM3_INTR_MAP_M  ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S))
-#define DPORT_PRO_PWM3_INTR_MAP_V  0x1F
-#define DPORT_PRO_PWM3_INTR_MAP_S  0
-
-#define DPORT_PRO_LEDC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1B0)
-/* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_LEDC_INT_MAP  0x0000001F
-#define DPORT_PRO_LEDC_INT_MAP_M  ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S))
-#define DPORT_PRO_LEDC_INT_MAP_V  0x1F
-#define DPORT_PRO_LEDC_INT_MAP_S  0
-
-#define DPORT_PRO_EFUSE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1B4)
-/* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_EFUSE_INT_MAP  0x0000001F
-#define DPORT_PRO_EFUSE_INT_MAP_M  ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S))
-#define DPORT_PRO_EFUSE_INT_MAP_V  0x1F
-#define DPORT_PRO_EFUSE_INT_MAP_S  0
-
-#define DPORT_PRO_CAN_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1B8)
-/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_CAN_INT_MAP  0x0000001F
-#define DPORT_PRO_CAN_INT_MAP_M  ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S))
-#define DPORT_PRO_CAN_INT_MAP_V  0x1F
-#define DPORT_PRO_CAN_INT_MAP_S  0
-
-#define DPORT_PRO_RTC_CORE_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1BC)
-/* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_RTC_CORE_INTR_MAP  0x0000001F
-#define DPORT_PRO_RTC_CORE_INTR_MAP_M  ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S))
-#define DPORT_PRO_RTC_CORE_INTR_MAP_V  0x1F
-#define DPORT_PRO_RTC_CORE_INTR_MAP_S  0
-
-#define DPORT_PRO_RMT_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1C0)
-/* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_RMT_INTR_MAP  0x0000001F
-#define DPORT_PRO_RMT_INTR_MAP_M  ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S))
-#define DPORT_PRO_RMT_INTR_MAP_V  0x1F
-#define DPORT_PRO_RMT_INTR_MAP_S  0
-
-#define DPORT_PRO_PCNT_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1C4)
-/* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_PCNT_INTR_MAP  0x0000001F
-#define DPORT_PRO_PCNT_INTR_MAP_M  ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S))
-#define DPORT_PRO_PCNT_INTR_MAP_V  0x1F
-#define DPORT_PRO_PCNT_INTR_MAP_S  0
-
-#define DPORT_PRO_I2C_EXT0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1C8)
-/* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_I2C_EXT0_INTR_MAP  0x0000001F
-#define DPORT_PRO_I2C_EXT0_INTR_MAP_M  ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S))
-#define DPORT_PRO_I2C_EXT0_INTR_MAP_V  0x1F
-#define DPORT_PRO_I2C_EXT0_INTR_MAP_S  0
-
-#define DPORT_PRO_I2C_EXT1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1CC)
-/* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_I2C_EXT1_INTR_MAP  0x0000001F
-#define DPORT_PRO_I2C_EXT1_INTR_MAP_M  ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S))
-#define DPORT_PRO_I2C_EXT1_INTR_MAP_V  0x1F
-#define DPORT_PRO_I2C_EXT1_INTR_MAP_S  0
-
-#define DPORT_PRO_RSA_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x1D0)
-/* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_RSA_INTR_MAP  0x0000001F
-#define DPORT_PRO_RSA_INTR_MAP_M  ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S))
-#define DPORT_PRO_RSA_INTR_MAP_V  0x1F
-#define DPORT_PRO_RSA_INTR_MAP_S  0
-
-#define DPORT_PRO_SPI1_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1D4)
-/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SPI1_DMA_INT_MAP  0x0000001F
-#define DPORT_PRO_SPI1_DMA_INT_MAP_M  ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S))
-#define DPORT_PRO_SPI1_DMA_INT_MAP_V  0x1F
-#define DPORT_PRO_SPI1_DMA_INT_MAP_S  0
-
-#define DPORT_PRO_SPI2_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1D8)
-/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SPI2_DMA_INT_MAP  0x0000001F
-#define DPORT_PRO_SPI2_DMA_INT_MAP_M  ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S))
-#define DPORT_PRO_SPI2_DMA_INT_MAP_V  0x1F
-#define DPORT_PRO_SPI2_DMA_INT_MAP_S  0
-
-#define DPORT_PRO_SPI3_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1DC)
-/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_SPI3_DMA_INT_MAP  0x0000001F
-#define DPORT_PRO_SPI3_DMA_INT_MAP_M  ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S))
-#define DPORT_PRO_SPI3_DMA_INT_MAP_V  0x1F
-#define DPORT_PRO_SPI3_DMA_INT_MAP_S  0
-
-#define DPORT_PRO_WDG_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1E0)
-/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_WDG_INT_MAP  0x0000001F
-#define DPORT_PRO_WDG_INT_MAP_M  ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S))
-#define DPORT_PRO_WDG_INT_MAP_V  0x1F
-#define DPORT_PRO_WDG_INT_MAP_S  0
-
-#define DPORT_PRO_TIMER_INT1_MAP_REG          (DR_REG_DPORT_BASE + 0x1E4)
-/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TIMER_INT1_MAP  0x0000001F
-#define DPORT_PRO_TIMER_INT1_MAP_M  ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S))
-#define DPORT_PRO_TIMER_INT1_MAP_V  0x1F
-#define DPORT_PRO_TIMER_INT1_MAP_S  0
-
-#define DPORT_PRO_TIMER_INT2_MAP_REG          (DR_REG_DPORT_BASE + 0x1E8)
-/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TIMER_INT2_MAP  0x0000001F
-#define DPORT_PRO_TIMER_INT2_MAP_M  ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S))
-#define DPORT_PRO_TIMER_INT2_MAP_V  0x1F
-#define DPORT_PRO_TIMER_INT2_MAP_S  0
-
-#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1EC)
-/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG_T0_EDGE_INT_MAP  0x0000001F
-#define DPORT_PRO_TG_T0_EDGE_INT_MAP_M  ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S))
-#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V  0x1F
-#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S  0
-
-#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1F0)
-/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG_T1_EDGE_INT_MAP  0x0000001F
-#define DPORT_PRO_TG_T1_EDGE_INT_MAP_M  ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S))
-#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V  0x1F
-#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S  0
-
-#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1F4)
-/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG_WDT_EDGE_INT_MAP  0x0000001F
-#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M  ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S))
-#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V  0x1F
-#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S  0
-
-#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1F8)
-/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG_LACT_EDGE_INT_MAP  0x0000001F
-#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M  ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S))
-#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V  0x1F
-#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S  0
-
-#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x1FC)
-/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG1_T0_EDGE_INT_MAP  0x0000001F
-#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S))
-#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V  0x1F
-#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S  0
-
-#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x200)
-/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG1_T1_EDGE_INT_MAP  0x0000001F
-#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S))
-#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V  0x1F
-#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S  0
-
-#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x204)
-/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP  0x0000001F
-#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S))
-#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V  0x1F
-#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S  0
-
-#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x208)
-/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP  0x0000001F
-#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S))
-#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V  0x1F
-#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S  0
-
-#define DPORT_PRO_MMU_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x20C)
-/* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_MMU_IA_INT_MAP  0x0000001F
-#define DPORT_PRO_MMU_IA_INT_MAP_M  ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S))
-#define DPORT_PRO_MMU_IA_INT_MAP_V  0x1F
-#define DPORT_PRO_MMU_IA_INT_MAP_S  0
-
-#define DPORT_PRO_MPU_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x210)
-/* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_MPU_IA_INT_MAP  0x0000001F
-#define DPORT_PRO_MPU_IA_INT_MAP_M  ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S))
-#define DPORT_PRO_MPU_IA_INT_MAP_V  0x1F
-#define DPORT_PRO_MPU_IA_INT_MAP_S  0
-
-#define DPORT_PRO_CACHE_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x214)
-/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_CACHE_IA_INT_MAP  0x0000001F
-#define DPORT_PRO_CACHE_IA_INT_MAP_M  ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S))
-#define DPORT_PRO_CACHE_IA_INT_MAP_V  0x1F
-#define DPORT_PRO_CACHE_IA_INT_MAP_S  0
-
-#define DPORT_APP_MAC_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x218)
-/* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_MAC_INTR_MAP  0x0000001F
-#define DPORT_APP_MAC_INTR_MAP_M  ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S))
-#define DPORT_APP_MAC_INTR_MAP_V  0x1F
-#define DPORT_APP_MAC_INTR_MAP_S  0
-
-#define DPORT_APP_MAC_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x21C)
-/* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_MAC_NMI_MAP  0x0000001F
-#define DPORT_APP_MAC_NMI_MAP_M  ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S))
-#define DPORT_APP_MAC_NMI_MAP_V  0x1F
-#define DPORT_APP_MAC_NMI_MAP_S  0
-
-#define DPORT_APP_BB_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x220)
-/* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_BB_INT_MAP  0x0000001F
-#define DPORT_APP_BB_INT_MAP_M  ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S))
-#define DPORT_APP_BB_INT_MAP_V  0x1F
-#define DPORT_APP_BB_INT_MAP_S  0
-
-#define DPORT_APP_BT_MAC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x224)
-/* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_BT_MAC_INT_MAP  0x0000001F
-#define DPORT_APP_BT_MAC_INT_MAP_M  ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S))
-#define DPORT_APP_BT_MAC_INT_MAP_V  0x1F
-#define DPORT_APP_BT_MAC_INT_MAP_S  0
-
-#define DPORT_APP_BT_BB_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x228)
-/* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_BT_BB_INT_MAP  0x0000001F
-#define DPORT_APP_BT_BB_INT_MAP_M  ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S))
-#define DPORT_APP_BT_BB_INT_MAP_V  0x1F
-#define DPORT_APP_BT_BB_INT_MAP_S  0
-
-#define DPORT_APP_BT_BB_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x22C)
-/* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_BT_BB_NMI_MAP  0x0000001F
-#define DPORT_APP_BT_BB_NMI_MAP_M  ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S))
-#define DPORT_APP_BT_BB_NMI_MAP_V  0x1F
-#define DPORT_APP_BT_BB_NMI_MAP_S  0
-
-#define DPORT_APP_RWBT_IRQ_MAP_REG          (DR_REG_DPORT_BASE + 0x230)
-/* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_RWBT_IRQ_MAP  0x0000001F
-#define DPORT_APP_RWBT_IRQ_MAP_M  ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S))
-#define DPORT_APP_RWBT_IRQ_MAP_V  0x1F
-#define DPORT_APP_RWBT_IRQ_MAP_S  0
-
-#define DPORT_APP_RWBLE_IRQ_MAP_REG          (DR_REG_DPORT_BASE + 0x234)
-/* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_RWBLE_IRQ_MAP  0x0000001F
-#define DPORT_APP_RWBLE_IRQ_MAP_M  ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S))
-#define DPORT_APP_RWBLE_IRQ_MAP_V  0x1F
-#define DPORT_APP_RWBLE_IRQ_MAP_S  0
-
-#define DPORT_APP_RWBT_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x238)
-/* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_RWBT_NMI_MAP  0x0000001F
-#define DPORT_APP_RWBT_NMI_MAP_M  ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S))
-#define DPORT_APP_RWBT_NMI_MAP_V  0x1F
-#define DPORT_APP_RWBT_NMI_MAP_S  0
-
-#define DPORT_APP_RWBLE_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x23C)
-/* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_RWBLE_NMI_MAP  0x0000001F
-#define DPORT_APP_RWBLE_NMI_MAP_M  ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S))
-#define DPORT_APP_RWBLE_NMI_MAP_V  0x1F
-#define DPORT_APP_RWBLE_NMI_MAP_S  0
-
-#define DPORT_APP_SLC0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x240)
-/* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SLC0_INTR_MAP  0x0000001F
-#define DPORT_APP_SLC0_INTR_MAP_M  ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S))
-#define DPORT_APP_SLC0_INTR_MAP_V  0x1F
-#define DPORT_APP_SLC0_INTR_MAP_S  0
-
-#define DPORT_APP_SLC1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x244)
-/* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SLC1_INTR_MAP  0x0000001F
-#define DPORT_APP_SLC1_INTR_MAP_M  ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S))
-#define DPORT_APP_SLC1_INTR_MAP_V  0x1F
-#define DPORT_APP_SLC1_INTR_MAP_S  0
-
-#define DPORT_APP_UHCI0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x248)
-/* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_UHCI0_INTR_MAP  0x0000001F
-#define DPORT_APP_UHCI0_INTR_MAP_M  ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S))
-#define DPORT_APP_UHCI0_INTR_MAP_V  0x1F
-#define DPORT_APP_UHCI0_INTR_MAP_S  0
-
-#define DPORT_APP_UHCI1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x24C)
-/* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_UHCI1_INTR_MAP  0x0000001F
-#define DPORT_APP_UHCI1_INTR_MAP_M  ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S))
-#define DPORT_APP_UHCI1_INTR_MAP_V  0x1F
-#define DPORT_APP_UHCI1_INTR_MAP_S  0
-
-#define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x250)
-/* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG_T0_LEVEL_INT_MAP  0x0000001F
-#define DPORT_APP_TG_T0_LEVEL_INT_MAP_M  ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S))
-#define DPORT_APP_TG_T0_LEVEL_INT_MAP_V  0x1F
-#define DPORT_APP_TG_T0_LEVEL_INT_MAP_S  0
-
-#define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x254)
-/* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG_T1_LEVEL_INT_MAP  0x0000001F
-#define DPORT_APP_TG_T1_LEVEL_INT_MAP_M  ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S))
-#define DPORT_APP_TG_T1_LEVEL_INT_MAP_V  0x1F
-#define DPORT_APP_TG_T1_LEVEL_INT_MAP_S  0
-
-#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x258)
-/* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG_WDT_LEVEL_INT_MAP  0x0000001F
-#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M  ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S))
-#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V  0x1F
-#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S  0
-
-#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x25C)
-/* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG_LACT_LEVEL_INT_MAP  0x0000001F
-#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M  ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S))
-#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V  0x1F
-#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S  0
-
-#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x260)
-/* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG1_T0_LEVEL_INT_MAP  0x0000001F
-#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M  ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S))
-#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V  0x1F
-#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S  0
-
-#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x264)
-/* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG1_T1_LEVEL_INT_MAP  0x0000001F
-#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M  ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S))
-#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V  0x1F
-#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S  0
-
-#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x268)
-/* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP  0x0000001F
-#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M  ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S))
-#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V  0x1F
-#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S  0
-
-#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x26C)
-/* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP  0x0000001F
-#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M  ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S))
-#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V  0x1F
-#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S  0
-
-#define DPORT_APP_GPIO_INTERRUPT_MAP_REG          (DR_REG_DPORT_BASE + 0x270)
-/* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_GPIO_INTERRUPT_APP_MAP  0x0000001F
-#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M  ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S))
-#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V  0x1F
-#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S  0
-
-#define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG          (DR_REG_DPORT_BASE + 0x274)
-/* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP  0x0000001F
-#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M  ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S))
-#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V  0x1F
-#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S  0
-
-#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_DPORT_BASE + 0x278)
-/* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
-#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M  ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S))
-#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
-#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S  0
-
-#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_DPORT_BASE + 0x27C)
-/* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
-#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M  ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S))
-#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
-#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S  0
-
-#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_DPORT_BASE + 0x280)
-/* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
-#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M  ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S))
-#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
-#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S  0
-
-#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_DPORT_BASE + 0x284)
-/* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
-#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M  ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S))
-#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
-#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S  0
-
-#define DPORT_APP_SPI_INTR_0_MAP_REG          (DR_REG_DPORT_BASE + 0x288)
-/* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SPI_INTR_0_MAP  0x0000001F
-#define DPORT_APP_SPI_INTR_0_MAP_M  ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S))
-#define DPORT_APP_SPI_INTR_0_MAP_V  0x1F
-#define DPORT_APP_SPI_INTR_0_MAP_S  0
-
-#define DPORT_APP_SPI_INTR_1_MAP_REG          (DR_REG_DPORT_BASE + 0x28C)
-/* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SPI_INTR_1_MAP  0x0000001F
-#define DPORT_APP_SPI_INTR_1_MAP_M  ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S))
-#define DPORT_APP_SPI_INTR_1_MAP_V  0x1F
-#define DPORT_APP_SPI_INTR_1_MAP_S  0
-
-#define DPORT_APP_SPI_INTR_2_MAP_REG          (DR_REG_DPORT_BASE + 0x290)
-/* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SPI_INTR_2_MAP  0x0000001F
-#define DPORT_APP_SPI_INTR_2_MAP_M  ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S))
-#define DPORT_APP_SPI_INTR_2_MAP_V  0x1F
-#define DPORT_APP_SPI_INTR_2_MAP_S  0
-
-#define DPORT_APP_SPI_INTR_3_MAP_REG          (DR_REG_DPORT_BASE + 0x294)
-/* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SPI_INTR_3_MAP  0x0000001F
-#define DPORT_APP_SPI_INTR_3_MAP_M  ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S))
-#define DPORT_APP_SPI_INTR_3_MAP_V  0x1F
-#define DPORT_APP_SPI_INTR_3_MAP_S  0
-
-#define DPORT_APP_I2S0_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x298)
-/* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_I2S0_INT_MAP  0x0000001F
-#define DPORT_APP_I2S0_INT_MAP_M  ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S))
-#define DPORT_APP_I2S0_INT_MAP_V  0x1F
-#define DPORT_APP_I2S0_INT_MAP_S  0
-
-#define DPORT_APP_I2S1_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x29C)
-/* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_I2S1_INT_MAP  0x0000001F
-#define DPORT_APP_I2S1_INT_MAP_M  ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S))
-#define DPORT_APP_I2S1_INT_MAP_V  0x1F
-#define DPORT_APP_I2S1_INT_MAP_S  0
-
-#define DPORT_APP_UART_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2A0)
-/* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_UART_INTR_MAP  0x0000001F
-#define DPORT_APP_UART_INTR_MAP_M  ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S))
-#define DPORT_APP_UART_INTR_MAP_V  0x1F
-#define DPORT_APP_UART_INTR_MAP_S  0
-
-#define DPORT_APP_UART1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2A4)
-/* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_UART1_INTR_MAP  0x0000001F
-#define DPORT_APP_UART1_INTR_MAP_M  ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S))
-#define DPORT_APP_UART1_INTR_MAP_V  0x1F
-#define DPORT_APP_UART1_INTR_MAP_S  0
-
-#define DPORT_APP_UART2_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2A8)
-/* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_UART2_INTR_MAP  0x0000001F
-#define DPORT_APP_UART2_INTR_MAP_M  ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S))
-#define DPORT_APP_UART2_INTR_MAP_V  0x1F
-#define DPORT_APP_UART2_INTR_MAP_S  0
-
-#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG          (DR_REG_DPORT_BASE + 0x2AC)
-/* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP  0x0000001F
-#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M  ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S))
-#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V  0x1F
-#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S  0
-
-#define DPORT_APP_EMAC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2B0)
-/* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_EMAC_INT_MAP  0x0000001F
-#define DPORT_APP_EMAC_INT_MAP_M  ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S))
-#define DPORT_APP_EMAC_INT_MAP_V  0x1F
-#define DPORT_APP_EMAC_INT_MAP_S  0
-
-#define DPORT_APP_PWM0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2B4)
-/* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_PWM0_INTR_MAP  0x0000001F
-#define DPORT_APP_PWM0_INTR_MAP_M  ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S))
-#define DPORT_APP_PWM0_INTR_MAP_V  0x1F
-#define DPORT_APP_PWM0_INTR_MAP_S  0
-
-#define DPORT_APP_PWM1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2B8)
-/* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_PWM1_INTR_MAP  0x0000001F
-#define DPORT_APP_PWM1_INTR_MAP_M  ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S))
-#define DPORT_APP_PWM1_INTR_MAP_V  0x1F
-#define DPORT_APP_PWM1_INTR_MAP_S  0
-
-#define DPORT_APP_PWM2_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2BC)
-/* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_PWM2_INTR_MAP  0x0000001F
-#define DPORT_APP_PWM2_INTR_MAP_M  ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S))
-#define DPORT_APP_PWM2_INTR_MAP_V  0x1F
-#define DPORT_APP_PWM2_INTR_MAP_S  0
-
-#define DPORT_APP_PWM3_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2C0)
-/* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_PWM3_INTR_MAP  0x0000001F
-#define DPORT_APP_PWM3_INTR_MAP_M  ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S))
-#define DPORT_APP_PWM3_INTR_MAP_V  0x1F
-#define DPORT_APP_PWM3_INTR_MAP_S  0
-
-#define DPORT_APP_LEDC_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2C4)
-/* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_LEDC_INT_MAP  0x0000001F
-#define DPORT_APP_LEDC_INT_MAP_M  ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S))
-#define DPORT_APP_LEDC_INT_MAP_V  0x1F
-#define DPORT_APP_LEDC_INT_MAP_S  0
-
-#define DPORT_APP_EFUSE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2C8)
-/* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_EFUSE_INT_MAP  0x0000001F
-#define DPORT_APP_EFUSE_INT_MAP_M  ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S))
-#define DPORT_APP_EFUSE_INT_MAP_V  0x1F
-#define DPORT_APP_EFUSE_INT_MAP_S  0
-
-#define DPORT_APP_CAN_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2CC)
-/* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_CAN_INT_MAP  0x0000001F
-#define DPORT_APP_CAN_INT_MAP_M  ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S))
-#define DPORT_APP_CAN_INT_MAP_V  0x1F
-#define DPORT_APP_CAN_INT_MAP_S  0
-
-#define DPORT_APP_RTC_CORE_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2D0)
-/* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_RTC_CORE_INTR_MAP  0x0000001F
-#define DPORT_APP_RTC_CORE_INTR_MAP_M  ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S))
-#define DPORT_APP_RTC_CORE_INTR_MAP_V  0x1F
-#define DPORT_APP_RTC_CORE_INTR_MAP_S  0
-
-#define DPORT_APP_RMT_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2D4)
-/* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_RMT_INTR_MAP  0x0000001F
-#define DPORT_APP_RMT_INTR_MAP_M  ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S))
-#define DPORT_APP_RMT_INTR_MAP_V  0x1F
-#define DPORT_APP_RMT_INTR_MAP_S  0
-
-#define DPORT_APP_PCNT_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2D8)
-/* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_PCNT_INTR_MAP  0x0000001F
-#define DPORT_APP_PCNT_INTR_MAP_M  ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S))
-#define DPORT_APP_PCNT_INTR_MAP_V  0x1F
-#define DPORT_APP_PCNT_INTR_MAP_S  0
-
-#define DPORT_APP_I2C_EXT0_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2DC)
-/* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_I2C_EXT0_INTR_MAP  0x0000001F
-#define DPORT_APP_I2C_EXT0_INTR_MAP_M  ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S))
-#define DPORT_APP_I2C_EXT0_INTR_MAP_V  0x1F
-#define DPORT_APP_I2C_EXT0_INTR_MAP_S  0
-
-#define DPORT_APP_I2C_EXT1_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2E0)
-/* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_I2C_EXT1_INTR_MAP  0x0000001F
-#define DPORT_APP_I2C_EXT1_INTR_MAP_M  ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S))
-#define DPORT_APP_I2C_EXT1_INTR_MAP_V  0x1F
-#define DPORT_APP_I2C_EXT1_INTR_MAP_S  0
-
-#define DPORT_APP_RSA_INTR_MAP_REG          (DR_REG_DPORT_BASE + 0x2E4)
-/* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_RSA_INTR_MAP  0x0000001F
-#define DPORT_APP_RSA_INTR_MAP_M  ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S))
-#define DPORT_APP_RSA_INTR_MAP_V  0x1F
-#define DPORT_APP_RSA_INTR_MAP_S  0
-
-#define DPORT_APP_SPI1_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2E8)
-/* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SPI1_DMA_INT_MAP  0x0000001F
-#define DPORT_APP_SPI1_DMA_INT_MAP_M  ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S))
-#define DPORT_APP_SPI1_DMA_INT_MAP_V  0x1F
-#define DPORT_APP_SPI1_DMA_INT_MAP_S  0
-
-#define DPORT_APP_SPI2_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2EC)
-/* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SPI2_DMA_INT_MAP  0x0000001F
-#define DPORT_APP_SPI2_DMA_INT_MAP_M  ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S))
-#define DPORT_APP_SPI2_DMA_INT_MAP_V  0x1F
-#define DPORT_APP_SPI2_DMA_INT_MAP_S  0
-
-#define DPORT_APP_SPI3_DMA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2F0)
-/* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_SPI3_DMA_INT_MAP  0x0000001F
-#define DPORT_APP_SPI3_DMA_INT_MAP_M  ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S))
-#define DPORT_APP_SPI3_DMA_INT_MAP_V  0x1F
-#define DPORT_APP_SPI3_DMA_INT_MAP_S  0
-
-#define DPORT_APP_WDG_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x2F4)
-/* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_WDG_INT_MAP  0x0000001F
-#define DPORT_APP_WDG_INT_MAP_M  ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S))
-#define DPORT_APP_WDG_INT_MAP_V  0x1F
-#define DPORT_APP_WDG_INT_MAP_S  0
-
-#define DPORT_APP_TIMER_INT1_MAP_REG          (DR_REG_DPORT_BASE + 0x2F8)
-/* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TIMER_INT1_MAP  0x0000001F
-#define DPORT_APP_TIMER_INT1_MAP_M  ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S))
-#define DPORT_APP_TIMER_INT1_MAP_V  0x1F
-#define DPORT_APP_TIMER_INT1_MAP_S  0
-
-#define DPORT_APP_TIMER_INT2_MAP_REG          (DR_REG_DPORT_BASE + 0x2FC)
-/* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TIMER_INT2_MAP  0x0000001F
-#define DPORT_APP_TIMER_INT2_MAP_M  ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S))
-#define DPORT_APP_TIMER_INT2_MAP_V  0x1F
-#define DPORT_APP_TIMER_INT2_MAP_S  0
-
-#define DPORT_APP_TG_T0_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x300)
-/* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG_T0_EDGE_INT_MAP  0x0000001F
-#define DPORT_APP_TG_T0_EDGE_INT_MAP_M  ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S))
-#define DPORT_APP_TG_T0_EDGE_INT_MAP_V  0x1F
-#define DPORT_APP_TG_T0_EDGE_INT_MAP_S  0
-
-#define DPORT_APP_TG_T1_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x304)
-/* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG_T1_EDGE_INT_MAP  0x0000001F
-#define DPORT_APP_TG_T1_EDGE_INT_MAP_M  ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S))
-#define DPORT_APP_TG_T1_EDGE_INT_MAP_V  0x1F
-#define DPORT_APP_TG_T1_EDGE_INT_MAP_S  0
-
-#define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x308)
-/* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG_WDT_EDGE_INT_MAP  0x0000001F
-#define DPORT_APP_TG_WDT_EDGE_INT_MAP_M  ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S))
-#define DPORT_APP_TG_WDT_EDGE_INT_MAP_V  0x1F
-#define DPORT_APP_TG_WDT_EDGE_INT_MAP_S  0
-
-#define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x30C)
-/* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG_LACT_EDGE_INT_MAP  0x0000001F
-#define DPORT_APP_TG_LACT_EDGE_INT_MAP_M  ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S))
-#define DPORT_APP_TG_LACT_EDGE_INT_MAP_V  0x1F
-#define DPORT_APP_TG_LACT_EDGE_INT_MAP_S  0
-
-#define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x310)
-/* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG1_T0_EDGE_INT_MAP  0x0000001F
-#define DPORT_APP_TG1_T0_EDGE_INT_MAP_M  ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S))
-#define DPORT_APP_TG1_T0_EDGE_INT_MAP_V  0x1F
-#define DPORT_APP_TG1_T0_EDGE_INT_MAP_S  0
-
-#define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x314)
-/* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG1_T1_EDGE_INT_MAP  0x0000001F
-#define DPORT_APP_TG1_T1_EDGE_INT_MAP_M  ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S))
-#define DPORT_APP_TG1_T1_EDGE_INT_MAP_V  0x1F
-#define DPORT_APP_TG1_T1_EDGE_INT_MAP_S  0
-
-#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x318)
-/* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG1_WDT_EDGE_INT_MAP  0x0000001F
-#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M  ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S))
-#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V  0x1F
-#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S  0
-
-#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x31C)
-/* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_TG1_LACT_EDGE_INT_MAP  0x0000001F
-#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M  ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S))
-#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V  0x1F
-#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S  0
-
-#define DPORT_APP_MMU_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x320)
-/* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_MMU_IA_INT_MAP  0x0000001F
-#define DPORT_APP_MMU_IA_INT_MAP_M  ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S))
-#define DPORT_APP_MMU_IA_INT_MAP_V  0x1F
-#define DPORT_APP_MMU_IA_INT_MAP_S  0
-
-#define DPORT_APP_MPU_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x324)
-/* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_MPU_IA_INT_MAP  0x0000001F
-#define DPORT_APP_MPU_IA_INT_MAP_M  ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S))
-#define DPORT_APP_MPU_IA_INT_MAP_V  0x1F
-#define DPORT_APP_MPU_IA_INT_MAP_S  0
-
-#define DPORT_APP_CACHE_IA_INT_MAP_REG          (DR_REG_DPORT_BASE + 0x328)
-/* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_APP_CACHE_IA_INT_MAP  0x0000001F
-#define DPORT_APP_CACHE_IA_INT_MAP_M  ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S))
-#define DPORT_APP_CACHE_IA_INT_MAP_V  0x1F
-#define DPORT_APP_CACHE_IA_INT_MAP_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_UART_REG          (DR_REG_DPORT_BASE + 0x32C)
-/* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_UART_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_UART_ACCESS_GRANT_CONFIG_M  ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S))
-#define DPORT_UART_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_UART_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_SPI1_REG          (DR_REG_DPORT_BASE + 0x330)
-/* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_SPI1_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_SPI1_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S))
-#define DPORT_SPI1_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_SPI1_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_SPI0_REG          (DR_REG_DPORT_BASE + 0x334)
-/* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_SPI0_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_SPI0_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S))
-#define DPORT_SPI0_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_SPI0_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_GPIO_REG          (DR_REG_DPORT_BASE + 0x338)
-/* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_GPIO_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_GPIO_ACCESS_GRANT_CONFIG_M  ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S))
-#define DPORT_GPIO_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_GPIO_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_FE2_REG          (DR_REG_DPORT_BASE + 0x33C)
-/* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_FE2_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_FE2_ACCESS_GRANT_CONFIG_M  ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S))
-#define DPORT_FE2_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_FE2_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_FE_REG          (DR_REG_DPORT_BASE + 0x340)
-/* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_FE_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_FE_ACCESS_GRANT_CONFIG_M  ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S))
-#define DPORT_FE_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_FE_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_TIMER_REG          (DR_REG_DPORT_BASE + 0x344)
-/* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_TIMER_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_TIMER_ACCESS_GRANT_CONFIG_M  ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S))
-#define DPORT_TIMER_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_TIMER_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_RTC_REG          (DR_REG_DPORT_BASE + 0x348)
-/* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_RTC_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_RTC_ACCESS_GRANT_CONFIG_M  ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S))
-#define DPORT_RTC_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_RTC_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG          (DR_REG_DPORT_BASE + 0x34C)
-/* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_IOMUX_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M  ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S))
-#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_WDG_REG          (DR_REG_DPORT_BASE + 0x350)
-/* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_WDG_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_WDG_ACCESS_GRANT_CONFIG_M  ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S))
-#define DPORT_WDG_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_WDG_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_HINF_REG          (DR_REG_DPORT_BASE + 0x354)
-/* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_HINF_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_HINF_ACCESS_GRANT_CONFIG_M  ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S))
-#define DPORT_HINF_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_HINF_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG          (DR_REG_DPORT_BASE + 0x358)
-/* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_UHCI1_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M  ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S))
-#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_MISC_REG          (DR_REG_DPORT_BASE + 0x35C)
-/* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_MISC_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_MISC_ACCESS_GRANT_CONFIG_M  ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S))
-#define DPORT_MISC_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_MISC_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_I2C_REG          (DR_REG_DPORT_BASE + 0x360)
-/* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_I2C_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_I2C_ACCESS_GRANT_CONFIG_M  ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S))
-#define DPORT_I2C_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_I2C_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_I2S0_REG          (DR_REG_DPORT_BASE + 0x364)
-/* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_I2S0_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_I2S0_ACCESS_GRANT_CONFIG_M  ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S))
-#define DPORT_I2S0_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_I2S0_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_UART1_REG          (DR_REG_DPORT_BASE + 0x368)
-/* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_UART1_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_UART1_ACCESS_GRANT_CONFIG_M  ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S))
-#define DPORT_UART1_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_UART1_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_BT_REG          (DR_REG_DPORT_BASE + 0x36C)
-/* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_BT_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_BT_ACCESS_GRANT_CONFIG_M  ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S))
-#define DPORT_BT_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_BT_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG          (DR_REG_DPORT_BASE + 0x370)
-/* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M  ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S))
-#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG          (DR_REG_DPORT_BASE + 0x374)
-/* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M  ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S))
-#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG          (DR_REG_DPORT_BASE + 0x378)
-/* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_UHCI0_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M  ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S))
-#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG          (DR_REG_DPORT_BASE + 0x37C)
-/* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M  ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S))
-#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_RMT_REG          (DR_REG_DPORT_BASE + 0x380)
-/* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_RMT_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_RMT_ACCESS_GRANT_CONFIG_M  ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S))
-#define DPORT_RMT_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_RMT_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_PCNT_REG          (DR_REG_DPORT_BASE + 0x384)
-/* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_PCNT_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_PCNT_ACCESS_GRANT_CONFIG_M  ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S))
-#define DPORT_PCNT_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_PCNT_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_SLC_REG          (DR_REG_DPORT_BASE + 0x388)
-/* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_SLC_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_SLC_ACCESS_GRANT_CONFIG_M  ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S))
-#define DPORT_SLC_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_SLC_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_LEDC_REG          (DR_REG_DPORT_BASE + 0x38C)
-/* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_LEDC_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_LEDC_ACCESS_GRANT_CONFIG_M  ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S))
-#define DPORT_LEDC_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_LEDC_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG          (DR_REG_DPORT_BASE + 0x390)
-/* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_EFUSE_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M  ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S))
-#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG          (DR_REG_DPORT_BASE + 0x394)
-/* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S))
-#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_BB_REG          (DR_REG_DPORT_BASE + 0x398)
-/* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_BB_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_BB_ACCESS_GRANT_CONFIG_M  ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S))
-#define DPORT_BB_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_BB_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_PWM0_REG          (DR_REG_DPORT_BASE + 0x39C)
-/* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_PWM0_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_PWM0_ACCESS_GRANT_CONFIG_M  ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S))
-#define DPORT_PWM0_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_PWM0_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG          (DR_REG_DPORT_BASE + 0x3A0)
-/* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M  ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S))
-#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG          (DR_REG_DPORT_BASE + 0x3A4)
-/* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M  ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S))
-#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_SPI2_REG          (DR_REG_DPORT_BASE + 0x3A8)
-/* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_SPI2_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_SPI2_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S))
-#define DPORT_SPI2_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_SPI2_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_SPI3_REG          (DR_REG_DPORT_BASE + 0x3AC)
-/* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_SPI3_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_SPI3_ACCESS_GRANT_CONFIG_M  ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S))
-#define DPORT_SPI3_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_SPI3_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG          (DR_REG_DPORT_BASE + 0x3B0)
-/* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M  ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S))
-#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG          (DR_REG_DPORT_BASE + 0x3B4)
-/* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M  ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S))
-#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG          (DR_REG_DPORT_BASE + 0x3B8)
-/* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M  ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S))
-#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_EMAC_REG          (DR_REG_DPORT_BASE + 0x3BC)
-/* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_EMAC_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_EMAC_ACCESS_GRANT_CONFIG_M  ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S))
-#define DPORT_EMAC_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_EMAC_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_CAN_REG          (DR_REG_DPORT_BASE + 0x3C0)
-/* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_CAN_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_CAN_ACCESS_GRANT_CONFIG_M  ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S))
-#define DPORT_CAN_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_CAN_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_PWM1_REG          (DR_REG_DPORT_BASE + 0x3C4)
-/* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_PWM1_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_PWM1_ACCESS_GRANT_CONFIG_M  ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S))
-#define DPORT_PWM1_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_PWM1_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_I2S1_REG          (DR_REG_DPORT_BASE + 0x3C8)
-/* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_I2S1_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_I2S1_ACCESS_GRANT_CONFIG_M  ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S))
-#define DPORT_I2S1_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_I2S1_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_UART2_REG          (DR_REG_DPORT_BASE + 0x3CC)
-/* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_UART2_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_UART2_ACCESS_GRANT_CONFIG_M  ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S))
-#define DPORT_UART2_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_UART2_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_PWM2_REG          (DR_REG_DPORT_BASE + 0x3D0)
-/* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_PWM2_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_PWM2_ACCESS_GRANT_CONFIG_M  ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S))
-#define DPORT_PWM2_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_PWM2_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_PWM3_REG          (DR_REG_DPORT_BASE + 0x3D4)
-/* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_PWM3_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_PWM3_ACCESS_GRANT_CONFIG_M  ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S))
-#define DPORT_PWM3_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_PWM3_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_RWBT_REG          (DR_REG_DPORT_BASE + 0x3D8)
-/* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_RWBT_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_RWBT_ACCESS_GRANT_CONFIG_M  ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S))
-#define DPORT_RWBT_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_RWBT_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG          (DR_REG_DPORT_BASE + 0x3DC)
-/* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_BTMAC_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M  ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S))
-#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG          (DR_REG_DPORT_BASE + 0x3E0)
-/* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M  ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S))
-#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_AHBLITE_MPU_TABLE_PWR_REG          (DR_REG_DPORT_BASE + 0x3E4)
-/* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_PWR_ACCESS_GRANT_CONFIG  0x0000003F
-#define DPORT_PWR_ACCESS_GRANT_CONFIG_M  ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S))
-#define DPORT_PWR_ACCESS_GRANT_CONFIG_V  0x3F
-#define DPORT_PWR_ACCESS_GRANT_CONFIG_S  0
-
-#define DPORT_MEM_ACCESS_DBUG0_REG          (DR_REG_DPORT_BASE + 0x3E8)
-/* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */
-/*description: */
-#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT  0x0000000F
-#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M  ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S))
-#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V  0xF
-#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S  26
-/* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */
-/*description: */
-#define DPORT_INTERNAL_SRAM_IA  0x00000FFF
-#define DPORT_INTERNAL_SRAM_IA_M  ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S))
-#define DPORT_INTERNAL_SRAM_IA_V  0xFFF
-#define DPORT_INTERNAL_SRAM_IA_S  14
-/* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */
-/*description: */
-#define DPORT_INTERNAL_SRAM_MMU_AD  0x0000000F
-#define DPORT_INTERNAL_SRAM_MMU_AD_M  ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S))
-#define DPORT_INTERNAL_SRAM_MMU_AD_V  0xF
-#define DPORT_INTERNAL_SRAM_MMU_AD_S  10
-/* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */
-/*description: */
-#define DPORT_SHARE_ROM_IA  0x0000000F
-#define DPORT_SHARE_ROM_IA_M  ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S))
-#define DPORT_SHARE_ROM_IA_V  0xF
-#define DPORT_SHARE_ROM_IA_S  6
-/* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_SHARE_ROM_MPU_AD  0x00000003
-#define DPORT_SHARE_ROM_MPU_AD_M  ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S))
-#define DPORT_SHARE_ROM_MPU_AD_V  0x3
-#define DPORT_SHARE_ROM_MPU_AD_S  4
-/* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_ROM_IA  (BIT(3))
-#define DPORT_APP_ROM_IA_M  (BIT(3))
-#define DPORT_APP_ROM_IA_V  0x1
-#define DPORT_APP_ROM_IA_S  3
-/* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_ROM_MPU_AD  (BIT(2))
-#define DPORT_APP_ROM_MPU_AD_M  (BIT(2))
-#define DPORT_APP_ROM_MPU_AD_V  0x1
-#define DPORT_APP_ROM_MPU_AD_S  2
-/* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_ROM_IA  (BIT(1))
-#define DPORT_PRO_ROM_IA_M  (BIT(1))
-#define DPORT_PRO_ROM_IA_V  0x1
-#define DPORT_PRO_ROM_IA_S  1
-/* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_ROM_MPU_AD  (BIT(0))
-#define DPORT_PRO_ROM_MPU_AD_M  (BIT(0))
-#define DPORT_PRO_ROM_MPU_AD_V  0x1
-#define DPORT_PRO_ROM_MPU_AD_S  0
-
-#define DPORT_MEM_ACCESS_DBUG1_REG          (DR_REG_DPORT_BASE + 0x3EC)
-/* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AHBLITE_IA  (BIT(10))
-#define DPORT_AHBLITE_IA_M  (BIT(10))
-#define DPORT_AHBLITE_IA_V  0x1
-#define DPORT_AHBLITE_IA_S  10
-/* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AHBLITE_ACCESS_DENY  (BIT(9))
-#define DPORT_AHBLITE_ACCESS_DENY_M  (BIT(9))
-#define DPORT_AHBLITE_ACCESS_DENY_V  0x1
-#define DPORT_AHBLITE_ACCESS_DENY_S  9
-/* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AHB_ACCESS_DENY  (BIT(8))
-#define DPORT_AHB_ACCESS_DENY_M  (BIT(8))
-#define DPORT_AHB_ACCESS_DENY_V  0x1
-#define DPORT_AHB_ACCESS_DENY_S  8
-/* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_PIDGEN_IA  0x00000003
-#define DPORT_PIDGEN_IA_M  ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S))
-#define DPORT_PIDGEN_IA_V  0x3
-#define DPORT_PIDGEN_IA_S  6
-/* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_ARB_IA  0x00000003
-#define DPORT_ARB_IA_M  ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S))
-#define DPORT_ARB_IA_V  0x3
-#define DPORT_ARB_IA_S  4
-/* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define DPORT_INTERNAL_SRAM_MMU_MISS  0x0000000F
-#define DPORT_INTERNAL_SRAM_MMU_MISS_M  ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S))
-#define DPORT_INTERNAL_SRAM_MMU_MISS_V  0xF
-#define DPORT_INTERNAL_SRAM_MMU_MISS_S  0
-
-#define DPORT_PRO_DCACHE_DBUG0_REG          (DR_REG_DPORT_BASE + 0x3F0)
-/* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_RX_END  (BIT(23))
-#define DPORT_PRO_RX_END_M  (BIT(23))
-#define DPORT_PRO_RX_END_V  0x1
-#define DPORT_PRO_RX_END_S  23
-/* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_SLAVE_WDATA_V  (BIT(22))
-#define DPORT_PRO_SLAVE_WDATA_V_M  (BIT(22))
-#define DPORT_PRO_SLAVE_WDATA_V_V  0x1
-#define DPORT_PRO_SLAVE_WDATA_V_S  22
-/* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_SLAVE_WR  (BIT(21))
-#define DPORT_PRO_SLAVE_WR_M  (BIT(21))
-#define DPORT_PRO_SLAVE_WR_V  0x1
-#define DPORT_PRO_SLAVE_WR_S  21
-/* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_TX_END  (BIT(20))
-#define DPORT_PRO_TX_END_M  (BIT(20))
-#define DPORT_PRO_TX_END_V  0x1
-#define DPORT_PRO_TX_END_S  20
-/* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_WR_BAK_TO_READ  (BIT(19))
-#define DPORT_PRO_WR_BAK_TO_READ_M  (BIT(19))
-#define DPORT_PRO_WR_BAK_TO_READ_V  0x1
-#define DPORT_PRO_WR_BAK_TO_READ_S  19
-/* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_STATE  0x00000FFF
-#define DPORT_PRO_CACHE_STATE_M  ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S))
-#define DPORT_PRO_CACHE_STATE_V  0xFFF
-#define DPORT_PRO_CACHE_STATE_S  7
-/* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_IA  0x0000003F
-#define DPORT_PRO_CACHE_IA_M  ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S))
-#define DPORT_PRO_CACHE_IA_V  0x3F
-#define DPORT_PRO_CACHE_IA_S  1
-/* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_MMU_IA  (BIT(0))
-#define DPORT_PRO_CACHE_MMU_IA_M  (BIT(0))
-#define DPORT_PRO_CACHE_MMU_IA_V  0x1
-#define DPORT_PRO_CACHE_MMU_IA_S  0
-
-#define DPORT_PRO_DCACHE_DBUG1_REG          (DR_REG_DPORT_BASE + 0x3F4)
-/* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_PRO_CTAG_RAM_RDATA  0xFFFFFFFF
-#define DPORT_PRO_CTAG_RAM_RDATA_M  ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S))
-#define DPORT_PRO_CTAG_RAM_RDATA_V  0xFFFFFFFF
-#define DPORT_PRO_CTAG_RAM_RDATA_S  0
-
-#define DPORT_PRO_DCACHE_DBUG2_REG          (DR_REG_DPORT_BASE + 0x3F8)
-/* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_VADDR  0x07FFFFFF
-#define DPORT_PRO_CACHE_VADDR_M  ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S))
-#define DPORT_PRO_CACHE_VADDR_V  0x7FFFFFF
-#define DPORT_PRO_CACHE_VADDR_S  0
-
-#define DPORT_PRO_DCACHE_DBUG3_REG          (DR_REG_DPORT_BASE + 0x3FC)
-/* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CACHE_IRAM0_PID_ERROR  (BIT(15))
-#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M  (BIT(15))
-#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V  0x1
-#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S  15
-/* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA  0x0000003F
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_M  ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S))
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_V  0x3F
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_S  9
-/* This is the contents of DPORT_PRO_CPU_DISABLED_CACHE_IA field expanded */
-/* The following bits will be set upon invalid access for different memory
- * regions: */
-/* Port of the APP CPU cache when cache is used in high/low or odd/even mode */
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE   BIT(9)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9
-/* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1    BIT(10)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_M  BIT(10)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_V  1
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1_S  10
-/* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0    BIT(11)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_M  BIT(11)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_V  1
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0_S  11
-/* IRAM1:  0x4040_0000 ~ 0x407F_FFFF(RO) */
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1    BIT(12)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_M  BIT(12)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_V  1
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1_S  12
-/* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0    BIT(13)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_M  BIT(13)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_V  1
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0_S  13
-/* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0    BIT(14)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_M  BIT(14)
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_V  1
-#define DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0_S  14
-
-/* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: */
-#define DPORT_PRO_MMU_RDATA  0x000001FF
-#define DPORT_PRO_MMU_RDATA_M  ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S))
-#define DPORT_PRO_MMU_RDATA_V  0x1FF
-#define DPORT_PRO_MMU_RDATA_S  0
-
-#define DPORT_PRO_DCACHE_DBUG4_REG          (DR_REG_DPORT_BASE + 0x400)
-/* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_PRO_DRAM1ADDR0_IA  0x000FFFFF
-#define DPORT_PRO_DRAM1ADDR0_IA_M  ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S))
-#define DPORT_PRO_DRAM1ADDR0_IA_V  0xFFFFF
-#define DPORT_PRO_DRAM1ADDR0_IA_S  0
-
-#define DPORT_PRO_DCACHE_DBUG5_REG          (DR_REG_DPORT_BASE + 0x404)
-/* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_PRO_DROM0ADDR0_IA  0x000FFFFF
-#define DPORT_PRO_DROM0ADDR0_IA_M  ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S))
-#define DPORT_PRO_DROM0ADDR0_IA_V  0xFFFFF
-#define DPORT_PRO_DROM0ADDR0_IA_S  0
-
-#define DPORT_PRO_DCACHE_DBUG6_REG          (DR_REG_DPORT_BASE + 0x408)
-/* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_PRO_IRAM0ADDR_IA  0x000FFFFF
-#define DPORT_PRO_IRAM0ADDR_IA_M  ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S))
-#define DPORT_PRO_IRAM0ADDR_IA_V  0xFFFFF
-#define DPORT_PRO_IRAM0ADDR_IA_S  0
-
-#define DPORT_PRO_DCACHE_DBUG7_REG          (DR_REG_DPORT_BASE + 0x40C)
-/* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_PRO_IRAM1ADDR_IA  0x000FFFFF
-#define DPORT_PRO_IRAM1ADDR_IA_M  ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S))
-#define DPORT_PRO_IRAM1ADDR_IA_V  0xFFFFF
-#define DPORT_PRO_IRAM1ADDR_IA_S  0
-
-#define DPORT_PRO_DCACHE_DBUG8_REG          (DR_REG_DPORT_BASE + 0x410)
-/* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_PRO_IROM0ADDR_IA  0x000FFFFF
-#define DPORT_PRO_IROM0ADDR_IA_M  ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S))
-#define DPORT_PRO_IROM0ADDR_IA_V  0xFFFFF
-#define DPORT_PRO_IROM0ADDR_IA_S  0
-
-#define DPORT_PRO_DCACHE_DBUG9_REG          (DR_REG_DPORT_BASE + 0x414)
-/* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_PRO_OPSDRAMADDR_IA  0x000FFFFF
-#define DPORT_PRO_OPSDRAMADDR_IA_M  ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S))
-#define DPORT_PRO_OPSDRAMADDR_IA_V  0xFFFFF
-#define DPORT_PRO_OPSDRAMADDR_IA_S  0
-
-#define DPORT_APP_DCACHE_DBUG0_REG          (DR_REG_DPORT_BASE + 0x418)
-/* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_RX_END  (BIT(23))
-#define DPORT_APP_RX_END_M  (BIT(23))
-#define DPORT_APP_RX_END_V  0x1
-#define DPORT_APP_RX_END_S  23
-/* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_SLAVE_WDATA_V  (BIT(22))
-#define DPORT_APP_SLAVE_WDATA_V_M  (BIT(22))
-#define DPORT_APP_SLAVE_WDATA_V_V  0x1
-#define DPORT_APP_SLAVE_WDATA_V_S  22
-/* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_SLAVE_WR  (BIT(21))
-#define DPORT_APP_SLAVE_WR_M  (BIT(21))
-#define DPORT_APP_SLAVE_WR_V  0x1
-#define DPORT_APP_SLAVE_WR_S  21
-/* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_TX_END  (BIT(20))
-#define DPORT_APP_TX_END_M  (BIT(20))
-#define DPORT_APP_TX_END_V  0x1
-#define DPORT_APP_TX_END_S  20
-/* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_WR_BAK_TO_READ  (BIT(19))
-#define DPORT_APP_WR_BAK_TO_READ_M  (BIT(19))
-#define DPORT_APP_WR_BAK_TO_READ_V  0x1
-#define DPORT_APP_WR_BAK_TO_READ_S  19
-/* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_STATE  0x00000FFF
-#define DPORT_APP_CACHE_STATE_M  ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S))
-#define DPORT_APP_CACHE_STATE_V  0xFFF
-#define DPORT_APP_CACHE_STATE_S  7
-/* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_IA  0x0000003F
-#define DPORT_APP_CACHE_IA_M  ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S))
-#define DPORT_APP_CACHE_IA_V  0x3F
-#define DPORT_APP_CACHE_IA_S  1
-/* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_MMU_IA  (BIT(0))
-#define DPORT_APP_CACHE_MMU_IA_M  (BIT(0))
-#define DPORT_APP_CACHE_MMU_IA_V  0x1
-#define DPORT_APP_CACHE_MMU_IA_S  0
-
-#define DPORT_APP_DCACHE_DBUG1_REG          (DR_REG_DPORT_BASE + 0x41C)
-/* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_APP_CTAG_RAM_RDATA  0xFFFFFFFF
-#define DPORT_APP_CTAG_RAM_RDATA_M  ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S))
-#define DPORT_APP_CTAG_RAM_RDATA_V  0xFFFFFFFF
-#define DPORT_APP_CTAG_RAM_RDATA_S  0
-
-#define DPORT_APP_DCACHE_DBUG2_REG          (DR_REG_DPORT_BASE + 0x420)
-/* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_VADDR  0x07FFFFFF
-#define DPORT_APP_CACHE_VADDR_M  ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S))
-#define DPORT_APP_CACHE_VADDR_V  0x7FFFFFF
-#define DPORT_APP_CACHE_VADDR_S  0
-
-#define DPORT_APP_DCACHE_DBUG3_REG          (DR_REG_DPORT_BASE + 0x424)
-/* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CACHE_IRAM0_PID_ERROR  (BIT(15))
-#define DPORT_APP_CACHE_IRAM0_PID_ERROR_M  (BIT(15))
-#define DPORT_APP_CACHE_IRAM0_PID_ERROR_V  0x1
-#define DPORT_APP_CACHE_IRAM0_PID_ERROR_S  15
-/* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */
-/*description: */
-#define DPORT_APP_CPU_DISABLED_CACHE_IA  0x0000003F
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_M  ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S))
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_V  0x3F
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_S  9
-/* This is the contents of DPORT_APP_CPU_DISABLED_CACHE_IA field expanded */
-/* The following bits will be set upon invalid access for different memory
- * regions: */
-/* Port of the PRO CPU cache when cache is used in high/low or odd/even mode */
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE   BIT(9)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_M BIT(9)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_V 1
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE_S 9
-/* DRAM1: 0x3F80_0000 ~ 0x3FBF_FFFF(R/W) */
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1    BIT(10)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_M  BIT(10)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_V  1
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1_S  10
-/* IROM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0    BIT(11)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_M  BIT(11)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_V  1
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0_S  11
-/* IRAM1:  0x4040_0000 ~ 0x407F_FFFF(RO) */
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1    BIT(12)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_M  BIT(12)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_V  1
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1_S  12
-/* IRAM0: 0x4080_0000 ~ 0x40BF_FFFF(RO) */
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0    BIT(13)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_M  BIT(13)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_V  1
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0_S  13
-/* DROM0: 0x3F40_0000 ~ 0x3F7F_FFFF (RO) */
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0    BIT(14)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_M  BIT(14)
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_V  1
-#define DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0_S  14
-
-/* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: */
-#define DPORT_APP_MMU_RDATA  0x000001FF
-#define DPORT_APP_MMU_RDATA_M  ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S))
-#define DPORT_APP_MMU_RDATA_V  0x1FF
-#define DPORT_APP_MMU_RDATA_S  0
-
-#define DPORT_APP_DCACHE_DBUG4_REG          (DR_REG_DPORT_BASE + 0x428)
-/* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_APP_DRAM1ADDR0_IA  0x000FFFFF
-#define DPORT_APP_DRAM1ADDR0_IA_M  ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S))
-#define DPORT_APP_DRAM1ADDR0_IA_V  0xFFFFF
-#define DPORT_APP_DRAM1ADDR0_IA_S  0
-
-#define DPORT_APP_DCACHE_DBUG5_REG          (DR_REG_DPORT_BASE + 0x42C)
-/* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_APP_DROM0ADDR0_IA  0x000FFFFF
-#define DPORT_APP_DROM0ADDR0_IA_M  ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S))
-#define DPORT_APP_DROM0ADDR0_IA_V  0xFFFFF
-#define DPORT_APP_DROM0ADDR0_IA_S  0
-
-#define DPORT_APP_DCACHE_DBUG6_REG          (DR_REG_DPORT_BASE + 0x430)
-/* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_APP_IRAM0ADDR_IA  0x000FFFFF
-#define DPORT_APP_IRAM0ADDR_IA_M  ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S))
-#define DPORT_APP_IRAM0ADDR_IA_V  0xFFFFF
-#define DPORT_APP_IRAM0ADDR_IA_S  0
-
-#define DPORT_APP_DCACHE_DBUG7_REG          (DR_REG_DPORT_BASE + 0x434)
-/* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_APP_IRAM1ADDR_IA  0x000FFFFF
-#define DPORT_APP_IRAM1ADDR_IA_M  ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S))
-#define DPORT_APP_IRAM1ADDR_IA_V  0xFFFFF
-#define DPORT_APP_IRAM1ADDR_IA_S  0
-
-#define DPORT_APP_DCACHE_DBUG8_REG          (DR_REG_DPORT_BASE + 0x438)
-/* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_APP_IROM0ADDR_IA  0x000FFFFF
-#define DPORT_APP_IROM0ADDR_IA_M  ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S))
-#define DPORT_APP_IROM0ADDR_IA_V  0xFFFFF
-#define DPORT_APP_IROM0ADDR_IA_S  0
-
-#define DPORT_APP_DCACHE_DBUG9_REG          (DR_REG_DPORT_BASE + 0x43C)
-/* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define DPORT_APP_OPSDRAMADDR_IA  0x000FFFFF
-#define DPORT_APP_OPSDRAMADDR_IA_M  ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S))
-#define DPORT_APP_OPSDRAMADDR_IA_V  0xFFFFF
-#define DPORT_APP_OPSDRAMADDR_IA_S  0
-
-#define DPORT_PRO_CPU_RECORD_CTRL_REG          (DR_REG_DPORT_BASE + 0x440)
-/* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_CPU_PDEBUG_ENABLE  (BIT(8))
-#define DPORT_PRO_CPU_PDEBUG_ENABLE_M  (BIT(8))
-#define DPORT_PRO_CPU_PDEBUG_ENABLE_V  0x1
-#define DPORT_PRO_CPU_PDEBUG_ENABLE_S  8
-/* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CPU_RECORD_DISABLE  (BIT(4))
-#define DPORT_PRO_CPU_RECORD_DISABLE_M  (BIT(4))
-#define DPORT_PRO_CPU_RECORD_DISABLE_V  0x1
-#define DPORT_PRO_CPU_RECORD_DISABLE_S  4
-/* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CPU_RECORD_ENABLE  (BIT(0))
-#define DPORT_PRO_CPU_RECORD_ENABLE_M  (BIT(0))
-#define DPORT_PRO_CPU_RECORD_ENABLE_V  0x1
-#define DPORT_PRO_CPU_RECORD_ENABLE_S  0
-
-#define DPORT_PRO_CPU_RECORD_STATUS_REG          (DR_REG_DPORT_BASE + 0x444)
-/* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PRO_CPU_RECORDING  (BIT(0))
-#define DPORT_PRO_CPU_RECORDING_M  (BIT(0))
-#define DPORT_PRO_CPU_RECORDING_V  0x1
-#define DPORT_PRO_CPU_RECORDING_S  0
-
-#define DPORT_PRO_CPU_RECORD_PID_REG          (DR_REG_DPORT_BASE + 0x448)
-/* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */
-/*description: */
-#define DPORT_RECORD_PRO_PID  0x00000007
-#define DPORT_RECORD_PRO_PID_M  ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S))
-#define DPORT_RECORD_PRO_PID_V  0x7
-#define DPORT_RECORD_PRO_PID_S  0
-
-#define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG          (DR_REG_DPORT_BASE + 0x44C)
-/* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_PRO_PDEBUGINST  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGINST_M  ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S))
-#define DPORT_RECORD_PRO_PDEBUGINST_V  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGINST_S  0
-/* register layout:
- * SIZE [7..0] 		 : Instructions normally complete in the W stage. The size of the instruction in the W is given
- *                	   by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing
- *                	   instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG.
- * ISRC [14..12]	 : Instruction source.
-** LOOP [23..20]	 : Loopback status.
-** CINTLEVEL [27..24]: CINTLEVEL.
-*/
-#define DPORT_RECORD_PDEBUGINST_SZ_M  		((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S))
-#define DPORT_RECORD_PDEBUGINST_SZ_V  		0xFF
-#define DPORT_RECORD_PDEBUGINST_SZ_S  		0
-#define DPORT_RECORD_PDEBUGINST_SZ(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V)
-#define DPORT_RECORD_PDEBUGINST_ISRC_M  	((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S))
-#define DPORT_RECORD_PDEBUGINST_ISRC_V  	0x07
-#define DPORT_RECORD_PDEBUGINST_ISRC_S  	12
-#define DPORT_RECORD_PDEBUGINST_ISRC(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V)
-// #define DPORT_RECORD_PDEBUGINST_LOOP_M  	((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S))
-// #define DPORT_RECORD_PDEBUGINST_LOOP_V  	0x0F
-// #define DPORT_RECORD_PDEBUGINST_LOOP_S  	20
-// #define DPORT_RECORD_PDEBUGINST_LOOP(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V)
-#define DPORT_RECORD_PDEBUGINST_LOOP_REP 	(BIT(20)) /* loopback will occur */
-#define DPORT_RECORD_PDEBUGINST_LOOP		(BIT(21)) /* last inst of loop */
-#define DPORT_RECORD_PDEBUGINST_CINTL_M  	((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S))
-#define DPORT_RECORD_PDEBUGINST_CINTL_V  	0x0F
-#define DPORT_RECORD_PDEBUGINST_CINTL_S  	24
-#define DPORT_RECORD_PDEBUGINST_CINTL(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V)
-
-#define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG          (DR_REG_DPORT_BASE + 0x450)
-/* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define DPORT_RECORD_PRO_PDEBUGSTATUS  0x000000FF
-#define DPORT_RECORD_PRO_PDEBUGSTATUS_M  ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S))
-#define DPORT_RECORD_PRO_PDEBUGSTATUS_V  0xFF
-#define DPORT_RECORD_PRO_PDEBUGSTATUS_S  0
-/* register layout:
- * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
- * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
-*/
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M  		((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V  		0x3F
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S  		0
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO		0x00 /* Power shut off */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP		0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL		0x04 /* Control transfer bubble */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM		0x08 /* I-cache miss (incl uncached miss) */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM		0x0C /* D-cache miss (excl uncached miss) */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0		0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info.
-															The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1		0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL		0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB		0x18 /* HW ITLB refill. The refill address and data are available on
-															DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM		0x1A /* ITLB miss */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB		0x1C /* HW DTLB refill. The refill address and data are available on
-															DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM		0x1E /* DTLB miss */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL		0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC		0x24 /* HW-corrected memory error */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI		0x28 /* WAITI mode */
-#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER		0x3C /* all other bubbles */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M  		((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S))
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V  		0x3F
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S  		0
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX		0x00 /* JX */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX	0x04 /* CALLX */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET		0x08 /* All call returns */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET		0x0C /* All exception returns */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B		0x10 /* Branch taken or loop not taken */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J		0x14 /* J */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL		0x18 /* CALL */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN		0x1C /* Branch not taken */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP		0x20 /* Loop instruction (taken) */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I	0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB	0x28 /* WSR/XSR to LBEGIN */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID	0x2C /* WSR to MMID */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR	0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER		0x34 /* RER or WER */
-#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF		0x3C /* Default */
-
-#define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG          (DR_REG_DPORT_BASE + 0x454)
-/* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_PRO_PDEBUGDATA  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGDATA_M  ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S))
-#define DPORT_RECORD_PRO_PDEBUGDATA_V  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGDATA_S  0
-/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP:
- *
- * HALT [17]: HALT instruction (TX only)
- * MEMW [16]: MEMW, EXTW or EXCW instruction dependency
- * REG  [12]: register dependencies or resource (e.g.TIE ports) conflicts
- * STR  [11]: store release (instruction) dependency
- * LSU  [8] : various LSU dependencies (MHT access, prefetch, cache access insts, s32c1i, etc)
- * OTHER[0] : all other hold dependencies resulting from data or resource dependencies
-*/
-#define DPORT_RECORD_PDEBUGDATA_DEP_HALT  	(BIT(17))
-#define DPORT_RECORD_PDEBUGDATA_DEP_MEMW  	(BIT(16))
-#define DPORT_RECORD_PDEBUGDATA_DEP_REG  	(BIT(12))
-#define DPORT_RECORD_PDEBUGDATA_DEP_STR  	(BIT(11))
-#define DPORT_RECORD_PDEBUGDATA_DEP_LSU  	(BIT(8))
-#define DPORT_RECORD_PDEBUGDATA_DEP_OTHER	(BIT(0))
-/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXCn:
- *
- * EXCCAUSE[21..16]: Processor exception cause
- * EXCVEC  [4..0]  : Encoded Exception Vector
-*/
-#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_M  	((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S))
-#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V  	0x3F
-#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S  	16
-#define DPORT_RECORD_PDEBUGDATA_EXCCAUSE(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_M  		((DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)<<(DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S))
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_V  		0x1F
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_S  		0
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGDATA_EXCCAUSE_S) & DPORT_RECORD_PDEBUGDATA_EXCCAUSE_V)
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_NONE		0x00 /* no vector */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_RST		0x01 /* Reset */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBG		0x02 /* Debug (repl corresp level “n”) */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_NMI		0x03 /* NMI (repl corresp level “n”) */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_USR		0x04 /* User */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_KRNL		0x05 /* Kernel */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_DBL		0x06 /* Double */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_EMEM		0x07 /* Memory Error */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF4		0x0A /* Window Overflow 4 */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF4		0x0B /* Window Underflow 4 */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF8		0x0C /* Window Overflow 8 */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF8		0x0D /* Window Underflow 8 */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_OVF12	0x0E /* Window Overflow 12 */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_UNF12	0x0F /* Window Underflow 12 */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT2		0x10 /* Int Level 2 (n/a if debug/NMI) */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT3		0x11 /* Int Level 3 (n/a if debug/NMI) */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT4		0x12 /* Int Level 4 (n/a if debug/NMI) */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT5		0x13 /* Int Level 5 (n/a if debug/NMI) */
-#define DPORT_RECORD_PDEBUGDATA_EXCVEC_INT6		0x14 /* Int Level 6 (n/a if debug/NMI) */
-/* register layout when bubble cycke cause is DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL:
- *
- * ITERDIV[19]  : Iterative divide stall.
- * ITERMUL[18]  : Iterative multiply stall.
- * BANKCONFL[16]: Bank-conflict stall.
- * BPLOAD[15]  	: Bypass load stall.
- * LSPROC[14]  	: Load/store miss-processing stall.
- * L32R[13]	   	: FastL32R stall.
- * BPIFETCH[12]	: Bypass I fetch stall.
- * RUNSTALL[10]	: RunStall.
- * TIE[9] 	   	: TIE port stall.
- * IPIF[8]	   	: Instruction RAM inbound-PIF stall.
- * IRAMBUSY[7] 	: Instruction RAM/ROM busy stall.
- * ICM[6] 	   	: I-cache-miss stall.
- * LSU[4]      	: The LSU will stall the pipeline under various local memory access conflict situations.
- * DCM[3] 	   	: D-cache-miss stall.
- * BUFFCONFL[2]	: Store buffer conflict stall.
- * BUFF[1] 	   	: Store buffer full stall.
-*/
-#define DPORT_RECORD_PDEBUGDATA_STALL_ITERDIV	(BIT(19))
-#define DPORT_RECORD_PDEBUGDATA_STALL_ITERMUL	(BIT(18))
-#define DPORT_RECORD_PDEBUGDATA_STALL_BANKCONFL	(BIT(16))
-#define DPORT_RECORD_PDEBUGDATA_STALL_BPLOAD	(BIT(15))
-#define DPORT_RECORD_PDEBUGDATA_STALL_LSPROC	(BIT(14))
-#define DPORT_RECORD_PDEBUGDATA_STALL_L32R		(BIT(13))
-#define DPORT_RECORD_PDEBUGDATA_STALL_BPIFETCH	(BIT(12))
-#define DPORT_RECORD_PDEBUGDATA_STALL_RUN		(BIT(10))
-#define DPORT_RECORD_PDEBUGDATA_STALL_TIE		(BIT(9))
-#define DPORT_RECORD_PDEBUGDATA_STALL_IPIF		(BIT(8))
-#define DPORT_RECORD_PDEBUGDATA_STALL_IRAMBUSY	(BIT(7))
-#define DPORT_RECORD_PDEBUGDATA_STALL_ICM		(BIT(6))
-#define DPORT_RECORD_PDEBUGDATA_STALL_LSU		(BIT(4))
-#define DPORT_RECORD_PDEBUGDATA_STALL_DCM		(BIT(3))
-#define DPORT_RECORD_PDEBUGDATA_STALL_BUFFCONFL	(BIT(2))
-#define DPORT_RECORD_PDEBUGDATA_STALL_BUFF		(BIT(1))
-/* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR:
- *
- * XSR[10]		: XSR Instruction
- * WSR[9]		: WSR Instruction
- * RSR[8]		: RSR Instruction
- * SR[7..0] : Special Register Number
-*/
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_XSR		(BIT(10))
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WSR		(BIT(9))
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RSR		(BIT(8))
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_M  		((DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S))
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V  		0xFF
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S  		0
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_SR_V)
-/* register layout for DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER:
- *
- * ER[13..2]: ER Address
- * WER[1]	: WER Instruction
- * RER[0]	: RER Instruction
-*/
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_M  		((DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)<<(DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S))
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V  		0xFFF
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S  		2
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_S) & DPORT_RECORD_PDEBUGDATA_INSNTYPE_ER_V)
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_WER		(BIT(1))
-#define DPORT_RECORD_PDEBUGDATA_INSNTYPE_RER		(BIT(0))
-
-
-#define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG          (DR_REG_DPORT_BASE + 0x458)
-/* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_PRO_PDEBUGPC  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGPC_M  ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S))
-#define DPORT_RECORD_PRO_PDEBUGPC_V  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGPC_S  0
-
-#define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG          (DR_REG_DPORT_BASE + 0x45C)
-/* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_PRO_PDEBUGLS0STAT  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGLS0STAT_M  ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S))
-#define DPORT_RECORD_PRO_PDEBUGLS0STAT_V  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S  0
-/* register layout:
- * TYPE [3..0] 	 : Type of instruction in LS.
- * SZ [7..4]	 : Operand size.
- * DTLBM [8]	 : Data TLB miss.
- * DCM [9]		 : D-cache miss.
- * DCH [10]		 : D-cache hit.
- * UC [12]		 : Uncached.
- * WB [13]		 : Writeback.
- * COH [16]	     : Coherency.
- * STCOH [18..17]: Coherent state.
- * TGT [23..20]  : Local target.
-*/
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_M  		((DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TYPE_S))
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_V  		0x0F
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S  		0
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TYPE_S) & DPORT_RECORD_PDEBUGLS0STAT_TYPE_V)
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_NONE	0x00 /* neither */
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_ITLBR	0x01 /* hw itlb refill */
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_DTLBR	0x02 /* hw dtlb refill */
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_LD		0x05 /* load */
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_STR		0x06 /* store */
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_L32R	0x08 /* l32r */
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_S32CLI1	0x0A /* s32ci1 */
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_CTI		0x0C /* cache test inst */
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWXSR	0x0E /* rsr/wsr/xsr */
-#define DPORT_RECORD_PDEBUGLS0STAT_TYPE_RWER	0x0F /* rer/wer */
-#define DPORT_RECORD_PDEBUGLS0STAT_SZ_M  		((DPORT_RECORD_PDEBUGLS0STAT_SZ_V)<<(DPORT_RECORD_PDEBUGLS0STAT_SZ_S))
-#define DPORT_RECORD_PDEBUGLS0STAT_SZ_V  		0x0F
-#define DPORT_RECORD_PDEBUGLS0STAT_SZ_S  		4
-#define DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_SZ_S) & DPORT_RECORD_PDEBUGLS0STAT_SZ_V)
-#define DPORT_RECORD_PDEBUGLS0STAT_SZB(_r_)		((8<<DPORT_RECORD_PDEBUGLS0STAT_SZ(_r_))/8) // in bytes
-#define DPORT_RECORD_PDEBUGLS0STAT_DTLBM		(BIT(8))
-#define DPORT_RECORD_PDEBUGLS0STAT_DCM			(BIT(9))
-#define DPORT_RECORD_PDEBUGLS0STAT_DCH			(BIT(10))
-#define DPORT_RECORD_PDEBUGLS0STAT_UC			(BIT(12))
-#define DPORT_RECORD_PDEBUGLS0STAT_WB			(BIT(13))
-#define DPORT_RECORD_PDEBUGLS0STAT_COH			(BIT(16))
-#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_M  	((DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)<<(DPORT_RECORD_PDEBUGLS0STAT_STCOH_S))
-#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_V  	0x03
-#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_S  	17
-#define DPORT_RECORD_PDEBUGLS0STAT_STCOH(_r_)	(((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_STCOH_S) & DPORT_RECORD_PDEBUGLS0STAT_STCOH_V)
-#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_NONE  	0x0 /* neither shared nor exclusive nor modified */
-#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_SHARED	0x1 /* shared */
-#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_EXCL  	0x2 /* exclusive */
-#define DPORT_RECORD_PDEBUGLS0STAT_STCOH_MOD  	0x3 /* modified */
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_M  		((DPORT_RECORD_PDEBUGLS0STAT_TGT_V)<<(DPORT_RECORD_PDEBUGLS0STAT_TGT_S))
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_V  		0x0F
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_S  		20
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT(_r_)		(((_r_)>>DPORT_RECORD_PDEBUGLS0STAT_TGT_S) & DPORT_RECORD_PDEBUGLS0STAT_TGT_V)
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_EXT  	0x0 /* not to local memory */
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM0	0x2 /* 001x: InstRAM (0/1) */
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM1	0x3 /* 001x: InstRAM (0/1) */
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM0  	0x4 /* 010x: InstROM (0/1) */
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM1  	0x5 /* 010x: InstROM (0/1) */
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM0  	0x0A /* 101x: DataRAM (0/1) */
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM1  	0x0B /* 101x: DataRAM (0/1) */
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM0  	0xE /* 111x: DataROM (0/1) */
-#define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM1  	0xF /* 111x: DataROM (0/1) */
-// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IRAM(_t_)	(((_t_)&0xE)=0x2) /* 001x: InstRAM (0/1) */
-// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_IROM(_t_)  	(((_t_)&0xE)=0x4) /* 010x: InstROM (0/1) */
-// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DRAM(_t_)  	(((_t_)&0xE)=0x2) /* 101x: DataRAM (0/1) */
-// #define DPORT_RECORD_PDEBUGLS0STAT_TGT_DROM(_t_)  	(((_t_)&0xE)=0x2) /* 111x: DataROM (0/1) */
-
-#define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG          (DR_REG_DPORT_BASE + 0x460)
-/* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_PRO_PDEBUGLS0ADDR  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M  ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S))
-#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S  0
-
-#define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG          (DR_REG_DPORT_BASE + 0x464)
-/* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_PRO_PDEBUGLS0DATA  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGLS0DATA_M  ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S))
-#define DPORT_RECORD_PRO_PDEBUGLS0DATA_V  0xFFFFFFFF
-#define DPORT_RECORD_PRO_PDEBUGLS0DATA_S  0
-
-#define DPORT_APP_CPU_RECORD_CTRL_REG          (DR_REG_DPORT_BASE + 0x468)
-/* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_CPU_PDEBUG_ENABLE  (BIT(8))
-#define DPORT_APP_CPU_PDEBUG_ENABLE_M  (BIT(8))
-#define DPORT_APP_CPU_PDEBUG_ENABLE_V  0x1
-#define DPORT_APP_CPU_PDEBUG_ENABLE_S  8
-/* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CPU_RECORD_DISABLE  (BIT(4))
-#define DPORT_APP_CPU_RECORD_DISABLE_M  (BIT(4))
-#define DPORT_APP_CPU_RECORD_DISABLE_V  0x1
-#define DPORT_APP_CPU_RECORD_DISABLE_S  4
-/* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CPU_RECORD_ENABLE  (BIT(0))
-#define DPORT_APP_CPU_RECORD_ENABLE_M  (BIT(0))
-#define DPORT_APP_CPU_RECORD_ENABLE_V  0x1
-#define DPORT_APP_CPU_RECORD_ENABLE_S  0
-
-#define DPORT_APP_CPU_RECORD_STATUS_REG          (DR_REG_DPORT_BASE + 0x46C)
-/* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_APP_CPU_RECORDING  (BIT(0))
-#define DPORT_APP_CPU_RECORDING_M  (BIT(0))
-#define DPORT_APP_CPU_RECORDING_V  0x1
-#define DPORT_APP_CPU_RECORDING_S  0
-
-#define DPORT_APP_CPU_RECORD_PID_REG          (DR_REG_DPORT_BASE + 0x470)
-/* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */
-/*description: */
-#define DPORT_RECORD_APP_PID  0x00000007
-#define DPORT_RECORD_APP_PID_M  ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S))
-#define DPORT_RECORD_APP_PID_V  0x7
-#define DPORT_RECORD_APP_PID_S  0
-
-#define DPORT_APP_CPU_RECORD_PDEBUGINST_REG          (DR_REG_DPORT_BASE + 0x474)
-/* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_APP_PDEBUGINST  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGINST_M  ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S))
-#define DPORT_RECORD_APP_PDEBUGINST_V  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGINST_S  0
-
-#define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG          (DR_REG_DPORT_BASE + 0x478)
-/* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define DPORT_RECORD_APP_PDEBUGSTATUS  0x000000FF
-#define DPORT_RECORD_APP_PDEBUGSTATUS_M  ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S))
-#define DPORT_RECORD_APP_PDEBUGSTATUS_V  0xFF
-#define DPORT_RECORD_APP_PDEBUGSTATUS_S  0
-
-#define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG          (DR_REG_DPORT_BASE + 0x47C)
-/* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_APP_PDEBUGDATA  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGDATA_M  ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S))
-#define DPORT_RECORD_APP_PDEBUGDATA_V  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGDATA_S  0
-
-#define DPORT_APP_CPU_RECORD_PDEBUGPC_REG          (DR_REG_DPORT_BASE + 0x480)
-/* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_APP_PDEBUGPC  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGPC_M  ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S))
-#define DPORT_RECORD_APP_PDEBUGPC_V  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGPC_S  0
-
-#define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG          (DR_REG_DPORT_BASE + 0x484)
-/* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_APP_PDEBUGLS0STAT  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGLS0STAT_M  ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S))
-#define DPORT_RECORD_APP_PDEBUGLS0STAT_V  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGLS0STAT_S  0
-
-#define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG          (DR_REG_DPORT_BASE + 0x488)
-/* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_APP_PDEBUGLS0ADDR  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGLS0ADDR_M  ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S))
-#define DPORT_RECORD_APP_PDEBUGLS0ADDR_V  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGLS0ADDR_S  0
-
-#define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG          (DR_REG_DPORT_BASE + 0x48C)
-/* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define DPORT_RECORD_APP_PDEBUGLS0DATA  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGLS0DATA_M  ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S))
-#define DPORT_RECORD_APP_PDEBUGLS0DATA_V  0xFFFFFFFF
-#define DPORT_RECORD_APP_PDEBUGLS0DATA_S  0
-
-#define DPORT_RSA_PD_CTRL_REG          (DR_REG_DPORT_BASE + 0x490)
-/* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_RSA_PD  (BIT(0))
-#define DPORT_RSA_PD_M  (BIT(0))
-#define DPORT_RSA_PD_V  0x1
-#define DPORT_RSA_PD_S  0
-
-#define DPORT_ROM_MPU_TABLE0_REG          (DR_REG_DPORT_BASE + 0x494)
-/* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_ROM_MPU_TABLE0  0x00000003
-#define DPORT_ROM_MPU_TABLE0_M  ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S))
-#define DPORT_ROM_MPU_TABLE0_V  0x3
-#define DPORT_ROM_MPU_TABLE0_S  0
-
-#define DPORT_ROM_MPU_TABLE1_REG          (DR_REG_DPORT_BASE + 0x498)
-/* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_ROM_MPU_TABLE1  0x00000003
-#define DPORT_ROM_MPU_TABLE1_M  ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S))
-#define DPORT_ROM_MPU_TABLE1_V  0x3
-#define DPORT_ROM_MPU_TABLE1_S  0
-
-#define DPORT_ROM_MPU_TABLE2_REG          (DR_REG_DPORT_BASE + 0x49C)
-/* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_ROM_MPU_TABLE2  0x00000003
-#define DPORT_ROM_MPU_TABLE2_M  ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S))
-#define DPORT_ROM_MPU_TABLE2_V  0x3
-#define DPORT_ROM_MPU_TABLE2_S  0
-
-#define DPORT_ROM_MPU_TABLE3_REG          (DR_REG_DPORT_BASE + 0x4A0)
-/* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_ROM_MPU_TABLE3  0x00000003
-#define DPORT_ROM_MPU_TABLE3_M  ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S))
-#define DPORT_ROM_MPU_TABLE3_V  0x3
-#define DPORT_ROM_MPU_TABLE3_S  0
-
-#define DPORT_SHROM_MPU_TABLE0_REG          (DR_REG_DPORT_BASE + 0x4A4)
-/* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE0  0x00000003
-#define DPORT_SHROM_MPU_TABLE0_M  ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S))
-#define DPORT_SHROM_MPU_TABLE0_V  0x3
-#define DPORT_SHROM_MPU_TABLE0_S  0
-
-#define DPORT_SHROM_MPU_TABLE1_REG          (DR_REG_DPORT_BASE + 0x4A8)
-/* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE1  0x00000003
-#define DPORT_SHROM_MPU_TABLE1_M  ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S))
-#define DPORT_SHROM_MPU_TABLE1_V  0x3
-#define DPORT_SHROM_MPU_TABLE1_S  0
-
-#define DPORT_SHROM_MPU_TABLE2_REG          (DR_REG_DPORT_BASE + 0x4AC)
-/* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE2  0x00000003
-#define DPORT_SHROM_MPU_TABLE2_M  ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S))
-#define DPORT_SHROM_MPU_TABLE2_V  0x3
-#define DPORT_SHROM_MPU_TABLE2_S  0
-
-#define DPORT_SHROM_MPU_TABLE3_REG          (DR_REG_DPORT_BASE + 0x4B0)
-/* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE3  0x00000003
-#define DPORT_SHROM_MPU_TABLE3_M  ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S))
-#define DPORT_SHROM_MPU_TABLE3_V  0x3
-#define DPORT_SHROM_MPU_TABLE3_S  0
-
-#define DPORT_SHROM_MPU_TABLE4_REG          (DR_REG_DPORT_BASE + 0x4B4)
-/* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE4  0x00000003
-#define DPORT_SHROM_MPU_TABLE4_M  ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S))
-#define DPORT_SHROM_MPU_TABLE4_V  0x3
-#define DPORT_SHROM_MPU_TABLE4_S  0
-
-#define DPORT_SHROM_MPU_TABLE5_REG          (DR_REG_DPORT_BASE + 0x4B8)
-/* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE5  0x00000003
-#define DPORT_SHROM_MPU_TABLE5_M  ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S))
-#define DPORT_SHROM_MPU_TABLE5_V  0x3
-#define DPORT_SHROM_MPU_TABLE5_S  0
-
-#define DPORT_SHROM_MPU_TABLE6_REG          (DR_REG_DPORT_BASE + 0x4BC)
-/* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE6  0x00000003
-#define DPORT_SHROM_MPU_TABLE6_M  ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S))
-#define DPORT_SHROM_MPU_TABLE6_V  0x3
-#define DPORT_SHROM_MPU_TABLE6_S  0
-
-#define DPORT_SHROM_MPU_TABLE7_REG          (DR_REG_DPORT_BASE + 0x4C0)
-/* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE7  0x00000003
-#define DPORT_SHROM_MPU_TABLE7_M  ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S))
-#define DPORT_SHROM_MPU_TABLE7_V  0x3
-#define DPORT_SHROM_MPU_TABLE7_S  0
-
-#define DPORT_SHROM_MPU_TABLE8_REG          (DR_REG_DPORT_BASE + 0x4C4)
-/* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE8  0x00000003
-#define DPORT_SHROM_MPU_TABLE8_M  ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S))
-#define DPORT_SHROM_MPU_TABLE8_V  0x3
-#define DPORT_SHROM_MPU_TABLE8_S  0
-
-#define DPORT_SHROM_MPU_TABLE9_REG          (DR_REG_DPORT_BASE + 0x4C8)
-/* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE9  0x00000003
-#define DPORT_SHROM_MPU_TABLE9_M  ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S))
-#define DPORT_SHROM_MPU_TABLE9_V  0x3
-#define DPORT_SHROM_MPU_TABLE9_S  0
-
-#define DPORT_SHROM_MPU_TABLE10_REG          (DR_REG_DPORT_BASE + 0x4CC)
-/* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE10  0x00000003
-#define DPORT_SHROM_MPU_TABLE10_M  ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S))
-#define DPORT_SHROM_MPU_TABLE10_V  0x3
-#define DPORT_SHROM_MPU_TABLE10_S  0
-
-#define DPORT_SHROM_MPU_TABLE11_REG          (DR_REG_DPORT_BASE + 0x4D0)
-/* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE11  0x00000003
-#define DPORT_SHROM_MPU_TABLE11_M  ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S))
-#define DPORT_SHROM_MPU_TABLE11_V  0x3
-#define DPORT_SHROM_MPU_TABLE11_S  0
-
-#define DPORT_SHROM_MPU_TABLE12_REG          (DR_REG_DPORT_BASE + 0x4D4)
-/* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE12  0x00000003
-#define DPORT_SHROM_MPU_TABLE12_M  ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S))
-#define DPORT_SHROM_MPU_TABLE12_V  0x3
-#define DPORT_SHROM_MPU_TABLE12_S  0
-
-#define DPORT_SHROM_MPU_TABLE13_REG          (DR_REG_DPORT_BASE + 0x4D8)
-/* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE13  0x00000003
-#define DPORT_SHROM_MPU_TABLE13_M  ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S))
-#define DPORT_SHROM_MPU_TABLE13_V  0x3
-#define DPORT_SHROM_MPU_TABLE13_S  0
-
-#define DPORT_SHROM_MPU_TABLE14_REG          (DR_REG_DPORT_BASE + 0x4DC)
-/* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE14  0x00000003
-#define DPORT_SHROM_MPU_TABLE14_M  ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S))
-#define DPORT_SHROM_MPU_TABLE14_V  0x3
-#define DPORT_SHROM_MPU_TABLE14_S  0
-
-#define DPORT_SHROM_MPU_TABLE15_REG          (DR_REG_DPORT_BASE + 0x4E0)
-/* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE15  0x00000003
-#define DPORT_SHROM_MPU_TABLE15_M  ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S))
-#define DPORT_SHROM_MPU_TABLE15_V  0x3
-#define DPORT_SHROM_MPU_TABLE15_S  0
-
-#define DPORT_SHROM_MPU_TABLE16_REG          (DR_REG_DPORT_BASE + 0x4E4)
-/* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE16  0x00000003
-#define DPORT_SHROM_MPU_TABLE16_M  ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S))
-#define DPORT_SHROM_MPU_TABLE16_V  0x3
-#define DPORT_SHROM_MPU_TABLE16_S  0
-
-#define DPORT_SHROM_MPU_TABLE17_REG          (DR_REG_DPORT_BASE + 0x4E8)
-/* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE17  0x00000003
-#define DPORT_SHROM_MPU_TABLE17_M  ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S))
-#define DPORT_SHROM_MPU_TABLE17_V  0x3
-#define DPORT_SHROM_MPU_TABLE17_S  0
-
-#define DPORT_SHROM_MPU_TABLE18_REG          (DR_REG_DPORT_BASE + 0x4EC)
-/* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE18  0x00000003
-#define DPORT_SHROM_MPU_TABLE18_M  ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S))
-#define DPORT_SHROM_MPU_TABLE18_V  0x3
-#define DPORT_SHROM_MPU_TABLE18_S  0
-
-#define DPORT_SHROM_MPU_TABLE19_REG          (DR_REG_DPORT_BASE + 0x4F0)
-/* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE19  0x00000003
-#define DPORT_SHROM_MPU_TABLE19_M  ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S))
-#define DPORT_SHROM_MPU_TABLE19_V  0x3
-#define DPORT_SHROM_MPU_TABLE19_S  0
-
-#define DPORT_SHROM_MPU_TABLE20_REG          (DR_REG_DPORT_BASE + 0x4F4)
-/* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE20  0x00000003
-#define DPORT_SHROM_MPU_TABLE20_M  ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S))
-#define DPORT_SHROM_MPU_TABLE20_V  0x3
-#define DPORT_SHROM_MPU_TABLE20_S  0
-
-#define DPORT_SHROM_MPU_TABLE21_REG          (DR_REG_DPORT_BASE + 0x4F8)
-/* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE21  0x00000003
-#define DPORT_SHROM_MPU_TABLE21_M  ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S))
-#define DPORT_SHROM_MPU_TABLE21_V  0x3
-#define DPORT_SHROM_MPU_TABLE21_S  0
-
-#define DPORT_SHROM_MPU_TABLE22_REG          (DR_REG_DPORT_BASE + 0x4FC)
-/* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE22  0x00000003
-#define DPORT_SHROM_MPU_TABLE22_M  ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S))
-#define DPORT_SHROM_MPU_TABLE22_V  0x3
-#define DPORT_SHROM_MPU_TABLE22_S  0
-
-#define DPORT_SHROM_MPU_TABLE23_REG          (DR_REG_DPORT_BASE + 0x500)
-/* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: */
-#define DPORT_SHROM_MPU_TABLE23  0x00000003
-#define DPORT_SHROM_MPU_TABLE23_M  ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S))
-#define DPORT_SHROM_MPU_TABLE23_V  0x3
-#define DPORT_SHROM_MPU_TABLE23_S  0
-
-#define DPORT_IMMU_TABLE0_REG          (DR_REG_DPORT_BASE + 0x504)
-/* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */
-/*description: */
-#define DPORT_IMMU_TABLE0  0x0000007F
-#define DPORT_IMMU_TABLE0_M  ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S))
-#define DPORT_IMMU_TABLE0_V  0x7F
-#define DPORT_IMMU_TABLE0_S  0
-
-#define DPORT_IMMU_TABLE1_REG          (DR_REG_DPORT_BASE + 0x508)
-/* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
-/*description: */
-#define DPORT_IMMU_TABLE1  0x0000007F
-#define DPORT_IMMU_TABLE1_M  ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S))
-#define DPORT_IMMU_TABLE1_V  0x7F
-#define DPORT_IMMU_TABLE1_S  0
-
-#define DPORT_IMMU_TABLE2_REG          (DR_REG_DPORT_BASE + 0x50C)
-/* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */
-/*description: */
-#define DPORT_IMMU_TABLE2  0x0000007F
-#define DPORT_IMMU_TABLE2_M  ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S))
-#define DPORT_IMMU_TABLE2_V  0x7F
-#define DPORT_IMMU_TABLE2_S  0
-
-#define DPORT_IMMU_TABLE3_REG          (DR_REG_DPORT_BASE + 0x510)
-/* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */
-/*description: */
-#define DPORT_IMMU_TABLE3  0x0000007F
-#define DPORT_IMMU_TABLE3_M  ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S))
-#define DPORT_IMMU_TABLE3_V  0x7F
-#define DPORT_IMMU_TABLE3_S  0
-
-#define DPORT_IMMU_TABLE4_REG          (DR_REG_DPORT_BASE + 0x514)
-/* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */
-/*description: */
-#define DPORT_IMMU_TABLE4  0x0000007F
-#define DPORT_IMMU_TABLE4_M  ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S))
-#define DPORT_IMMU_TABLE4_V  0x7F
-#define DPORT_IMMU_TABLE4_S  0
-
-#define DPORT_IMMU_TABLE5_REG          (DR_REG_DPORT_BASE + 0x518)
-/* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */
-/*description: */
-#define DPORT_IMMU_TABLE5  0x0000007F
-#define DPORT_IMMU_TABLE5_M  ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S))
-#define DPORT_IMMU_TABLE5_V  0x7F
-#define DPORT_IMMU_TABLE5_S  0
-
-#define DPORT_IMMU_TABLE6_REG          (DR_REG_DPORT_BASE + 0x51C)
-/* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */
-/*description: */
-#define DPORT_IMMU_TABLE6  0x0000007F
-#define DPORT_IMMU_TABLE6_M  ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S))
-#define DPORT_IMMU_TABLE6_V  0x7F
-#define DPORT_IMMU_TABLE6_S  0
-
-#define DPORT_IMMU_TABLE7_REG          (DR_REG_DPORT_BASE + 0x520)
-/* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */
-/*description: */
-#define DPORT_IMMU_TABLE7  0x0000007F
-#define DPORT_IMMU_TABLE7_M  ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S))
-#define DPORT_IMMU_TABLE7_V  0x7F
-#define DPORT_IMMU_TABLE7_S  0
-
-#define DPORT_IMMU_TABLE8_REG          (DR_REG_DPORT_BASE + 0x524)
-/* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */
-/*description: */
-#define DPORT_IMMU_TABLE8  0x0000007F
-#define DPORT_IMMU_TABLE8_M  ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S))
-#define DPORT_IMMU_TABLE8_V  0x7F
-#define DPORT_IMMU_TABLE8_S  0
-
-#define DPORT_IMMU_TABLE9_REG          (DR_REG_DPORT_BASE + 0x528)
-/* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */
-/*description: */
-#define DPORT_IMMU_TABLE9  0x0000007F
-#define DPORT_IMMU_TABLE9_M  ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S))
-#define DPORT_IMMU_TABLE9_V  0x7F
-#define DPORT_IMMU_TABLE9_S  0
-
-#define DPORT_IMMU_TABLE10_REG          (DR_REG_DPORT_BASE + 0x52C)
-/* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */
-/*description: */
-#define DPORT_IMMU_TABLE10  0x0000007F
-#define DPORT_IMMU_TABLE10_M  ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S))
-#define DPORT_IMMU_TABLE10_V  0x7F
-#define DPORT_IMMU_TABLE10_S  0
-
-#define DPORT_IMMU_TABLE11_REG          (DR_REG_DPORT_BASE + 0x530)
-/* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */
-/*description: */
-#define DPORT_IMMU_TABLE11  0x0000007F
-#define DPORT_IMMU_TABLE11_M  ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S))
-#define DPORT_IMMU_TABLE11_V  0x7F
-#define DPORT_IMMU_TABLE11_S  0
-
-#define DPORT_IMMU_TABLE12_REG          (DR_REG_DPORT_BASE + 0x534)
-/* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */
-/*description: */
-#define DPORT_IMMU_TABLE12  0x0000007F
-#define DPORT_IMMU_TABLE12_M  ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S))
-#define DPORT_IMMU_TABLE12_V  0x7F
-#define DPORT_IMMU_TABLE12_S  0
-
-#define DPORT_IMMU_TABLE13_REG          (DR_REG_DPORT_BASE + 0x538)
-/* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */
-/*description: */
-#define DPORT_IMMU_TABLE13  0x0000007F
-#define DPORT_IMMU_TABLE13_M  ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S))
-#define DPORT_IMMU_TABLE13_V  0x7F
-#define DPORT_IMMU_TABLE13_S  0
-
-#define DPORT_IMMU_TABLE14_REG          (DR_REG_DPORT_BASE + 0x53C)
-/* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */
-/*description: */
-#define DPORT_IMMU_TABLE14  0x0000007F
-#define DPORT_IMMU_TABLE14_M  ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S))
-#define DPORT_IMMU_TABLE14_V  0x7F
-#define DPORT_IMMU_TABLE14_S  0
-
-#define DPORT_IMMU_TABLE15_REG          (DR_REG_DPORT_BASE + 0x540)
-/* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */
-/*description: */
-#define DPORT_IMMU_TABLE15  0x0000007F
-#define DPORT_IMMU_TABLE15_M  ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S))
-#define DPORT_IMMU_TABLE15_V  0x7F
-#define DPORT_IMMU_TABLE15_S  0
-
-#define DPORT_DMMU_TABLE0_REG          (DR_REG_DPORT_BASE + 0x544)
-/* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */
-/*description: */
-#define DPORT_DMMU_TABLE0  0x0000007F
-#define DPORT_DMMU_TABLE0_M  ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S))
-#define DPORT_DMMU_TABLE0_V  0x7F
-#define DPORT_DMMU_TABLE0_S  0
-
-#define DPORT_DMMU_TABLE1_REG          (DR_REG_DPORT_BASE + 0x548)
-/* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
-/*description: */
-#define DPORT_DMMU_TABLE1  0x0000007F
-#define DPORT_DMMU_TABLE1_M  ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S))
-#define DPORT_DMMU_TABLE1_V  0x7F
-#define DPORT_DMMU_TABLE1_S  0
-
-#define DPORT_DMMU_TABLE2_REG          (DR_REG_DPORT_BASE + 0x54C)
-/* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */
-/*description: */
-#define DPORT_DMMU_TABLE2  0x0000007F
-#define DPORT_DMMU_TABLE2_M  ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S))
-#define DPORT_DMMU_TABLE2_V  0x7F
-#define DPORT_DMMU_TABLE2_S  0
-
-#define DPORT_DMMU_TABLE3_REG          (DR_REG_DPORT_BASE + 0x550)
-/* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */
-/*description: */
-#define DPORT_DMMU_TABLE3  0x0000007F
-#define DPORT_DMMU_TABLE3_M  ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S))
-#define DPORT_DMMU_TABLE3_V  0x7F
-#define DPORT_DMMU_TABLE3_S  0
-
-#define DPORT_DMMU_TABLE4_REG          (DR_REG_DPORT_BASE + 0x554)
-/* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */
-/*description: */
-#define DPORT_DMMU_TABLE4  0x0000007F
-#define DPORT_DMMU_TABLE4_M  ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S))
-#define DPORT_DMMU_TABLE4_V  0x7F
-#define DPORT_DMMU_TABLE4_S  0
-
-#define DPORT_DMMU_TABLE5_REG          (DR_REG_DPORT_BASE + 0x558)
-/* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */
-/*description: */
-#define DPORT_DMMU_TABLE5  0x0000007F
-#define DPORT_DMMU_TABLE5_M  ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S))
-#define DPORT_DMMU_TABLE5_V  0x7F
-#define DPORT_DMMU_TABLE5_S  0
-
-#define DPORT_DMMU_TABLE6_REG          (DR_REG_DPORT_BASE + 0x55C)
-/* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */
-/*description: */
-#define DPORT_DMMU_TABLE6  0x0000007F
-#define DPORT_DMMU_TABLE6_M  ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S))
-#define DPORT_DMMU_TABLE6_V  0x7F
-#define DPORT_DMMU_TABLE6_S  0
-
-#define DPORT_DMMU_TABLE7_REG          (DR_REG_DPORT_BASE + 0x560)
-/* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */
-/*description: */
-#define DPORT_DMMU_TABLE7  0x0000007F
-#define DPORT_DMMU_TABLE7_M  ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S))
-#define DPORT_DMMU_TABLE7_V  0x7F
-#define DPORT_DMMU_TABLE7_S  0
-
-#define DPORT_DMMU_TABLE8_REG          (DR_REG_DPORT_BASE + 0x564)
-/* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */
-/*description: */
-#define DPORT_DMMU_TABLE8  0x0000007F
-#define DPORT_DMMU_TABLE8_M  ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S))
-#define DPORT_DMMU_TABLE8_V  0x7F
-#define DPORT_DMMU_TABLE8_S  0
-
-#define DPORT_DMMU_TABLE9_REG          (DR_REG_DPORT_BASE + 0x568)
-/* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */
-/*description: */
-#define DPORT_DMMU_TABLE9  0x0000007F
-#define DPORT_DMMU_TABLE9_M  ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S))
-#define DPORT_DMMU_TABLE9_V  0x7F
-#define DPORT_DMMU_TABLE9_S  0
-
-#define DPORT_DMMU_TABLE10_REG          (DR_REG_DPORT_BASE + 0x56C)
-/* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */
-/*description: */
-#define DPORT_DMMU_TABLE10  0x0000007F
-#define DPORT_DMMU_TABLE10_M  ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S))
-#define DPORT_DMMU_TABLE10_V  0x7F
-#define DPORT_DMMU_TABLE10_S  0
-
-#define DPORT_DMMU_TABLE11_REG          (DR_REG_DPORT_BASE + 0x570)
-/* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */
-/*description: */
-#define DPORT_DMMU_TABLE11  0x0000007F
-#define DPORT_DMMU_TABLE11_M  ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S))
-#define DPORT_DMMU_TABLE11_V  0x7F
-#define DPORT_DMMU_TABLE11_S  0
-
-#define DPORT_DMMU_TABLE12_REG          (DR_REG_DPORT_BASE + 0x574)
-/* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */
-/*description: */
-#define DPORT_DMMU_TABLE12  0x0000007F
-#define DPORT_DMMU_TABLE12_M  ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S))
-#define DPORT_DMMU_TABLE12_V  0x7F
-#define DPORT_DMMU_TABLE12_S  0
-
-#define DPORT_DMMU_TABLE13_REG          (DR_REG_DPORT_BASE + 0x578)
-/* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */
-/*description: */
-#define DPORT_DMMU_TABLE13  0x0000007F
-#define DPORT_DMMU_TABLE13_M  ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S))
-#define DPORT_DMMU_TABLE13_V  0x7F
-#define DPORT_DMMU_TABLE13_S  0
-
-#define DPORT_DMMU_TABLE14_REG          (DR_REG_DPORT_BASE + 0x57C)
-/* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */
-/*description: */
-#define DPORT_DMMU_TABLE14  0x0000007F
-#define DPORT_DMMU_TABLE14_M  ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S))
-#define DPORT_DMMU_TABLE14_V  0x7F
-#define DPORT_DMMU_TABLE14_S  0
-
-#define DPORT_DMMU_TABLE15_REG          (DR_REG_DPORT_BASE + 0x580)
-/* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */
-/*description: */
-#define DPORT_DMMU_TABLE15  0x0000007F
-#define DPORT_DMMU_TABLE15_M  ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S))
-#define DPORT_DMMU_TABLE15_V  0x7F
-#define DPORT_DMMU_TABLE15_S  0
-
-#define DPORT_PRO_INTRUSION_CTRL_REG          (DR_REG_DPORT_BASE + 0x584)
-/* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PRO_INTRUSION_RECORD_RESET_N  (BIT(0))
-#define DPORT_PRO_INTRUSION_RECORD_RESET_N_M  (BIT(0))
-#define DPORT_PRO_INTRUSION_RECORD_RESET_N_V  0x1
-#define DPORT_PRO_INTRUSION_RECORD_RESET_N_S  0
-
-#define DPORT_PRO_INTRUSION_STATUS_REG          (DR_REG_DPORT_BASE + 0x588)
-/* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define DPORT_PRO_INTRUSION_RECORD  0x0000000F
-#define DPORT_PRO_INTRUSION_RECORD_M  ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S))
-#define DPORT_PRO_INTRUSION_RECORD_V  0xF
-#define DPORT_PRO_INTRUSION_RECORD_S  0
-
-#define DPORT_APP_INTRUSION_CTRL_REG          (DR_REG_DPORT_BASE + 0x58C)
-/* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_APP_INTRUSION_RECORD_RESET_N  (BIT(0))
-#define DPORT_APP_INTRUSION_RECORD_RESET_N_M  (BIT(0))
-#define DPORT_APP_INTRUSION_RECORD_RESET_N_V  0x1
-#define DPORT_APP_INTRUSION_RECORD_RESET_N_S  0
-
-#define DPORT_APP_INTRUSION_STATUS_REG          (DR_REG_DPORT_BASE + 0x590)
-/* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define DPORT_APP_INTRUSION_RECORD  0x0000000F
-#define DPORT_APP_INTRUSION_RECORD_M  ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S))
-#define DPORT_APP_INTRUSION_RECORD_V  0xF
-#define DPORT_APP_INTRUSION_RECORD_S  0
-
-#define DPORT_FRONT_END_MEM_PD_REG          (DR_REG_DPORT_BASE + 0x594)
-/* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_PBUS_MEM_FORCE_PD  (BIT(3))
-#define DPORT_PBUS_MEM_FORCE_PD_M  (BIT(3))
-#define DPORT_PBUS_MEM_FORCE_PD_V  0x1
-#define DPORT_PBUS_MEM_FORCE_PD_S  3
-/* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_PBUS_MEM_FORCE_PU  (BIT(2))
-#define DPORT_PBUS_MEM_FORCE_PU_M  (BIT(2))
-#define DPORT_PBUS_MEM_FORCE_PU_V  0x1
-#define DPORT_PBUS_MEM_FORCE_PU_S  2
-/* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_AGC_MEM_FORCE_PD  (BIT(1))
-#define DPORT_AGC_MEM_FORCE_PD_M  (BIT(1))
-#define DPORT_AGC_MEM_FORCE_PD_V  0x1
-#define DPORT_AGC_MEM_FORCE_PD_S  1
-/* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define DPORT_AGC_MEM_FORCE_PU  (BIT(0))
-#define DPORT_AGC_MEM_FORCE_PU_M  (BIT(0))
-#define DPORT_AGC_MEM_FORCE_PU_V  0x1
-#define DPORT_AGC_MEM_FORCE_PU_S  0
-
-#define DPORT_MMU_IA_INT_EN_REG          (DR_REG_DPORT_BASE + 0x598)
-/* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define DPORT_MMU_IA_INT_EN  0x00FFFFFF
-#define DPORT_MMU_IA_INT_EN_M  ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S))
-#define DPORT_MMU_IA_INT_EN_V  0xFFFFFF
-#define DPORT_MMU_IA_INT_EN_S  0
-
-#define DPORT_MPU_IA_INT_EN_REG          (DR_REG_DPORT_BASE + 0x59C)
-/* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */
-/*description: */
-#define DPORT_MPU_IA_INT_EN  0x0001FFFF
-#define DPORT_MPU_IA_INT_EN_M  ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S))
-#define DPORT_MPU_IA_INT_EN_V  0x1FFFF
-#define DPORT_MPU_IA_INT_EN_S  0
-
-#define DPORT_CACHE_IA_INT_EN_REG          (DR_REG_DPORT_BASE + 0x5A0)
-/* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
-/*description: Interrupt enable bits for various invalid cache access reasons*/
-#define DPORT_CACHE_IA_INT_EN  0x0FFFFFFF
-#define DPORT_CACHE_IA_INT_EN_M  ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S))
-#define DPORT_CACHE_IA_INT_EN_V  0xFFFFFFF
-#define DPORT_CACHE_IA_INT_EN_S  0
-/* Contents of DPORT_CACHE_IA_INT_EN field: */
-/* DPORT_CACHE_IA_INT_PRO_OPPOSITE : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: PRO CPU invalid access to APP CPU cache when cache disabled */
-#define DPORT_CACHE_IA_INT_PRO_OPPOSITE    BIT(19)
-#define DPORT_CACHE_IA_INT_PRO_OPPOSITE_M  BIT(19)
-#define DPORT_CACHE_IA_INT_PRO_OPPOSITE_V  (1)
-#define DPORT_CACHE_IA_INT_PRO_OPPOSITE_S  (19)
-/* DPORT_CACHE_IA_INT_PRO_DRAM1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: PRO CPU invalid access to DRAM1 when cache is disabled */
-#define DPORT_CACHE_IA_INT_PRO_DRAM1    BIT(18)
-#define DPORT_CACHE_IA_INT_PRO_DRAM1_M  BIT(18)
-#define DPORT_CACHE_IA_INT_PRO_DRAM1_V  (1)
-#define DPORT_CACHE_IA_INT_PRO_DRAM1_S  (18)
-/* DPORT_CACHE_IA_INT_PRO_IROM0 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: PRO CPU invalid access to IROM0 when cache is disabled */
-#define DPORT_CACHE_IA_INT_PRO_IROM0    BIT(17)
-#define DPORT_CACHE_IA_INT_PRO_IROM0_M  BIT(17)
-#define DPORT_CACHE_IA_INT_PRO_IROM0_V  (1)
-#define DPORT_CACHE_IA_INT_PRO_IROM0_S  (17)
-/* DPORT_CACHE_IA_INT_PRO_IRAM1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: PRO CPU invalid access to IRAM1 when cache is disabled */
-#define DPORT_CACHE_IA_INT_PRO_IRAM1    BIT(16)
-#define DPORT_CACHE_IA_INT_PRO_IRAM1_M  BIT(16)
-#define DPORT_CACHE_IA_INT_PRO_IRAM1_V  (1)
-#define DPORT_CACHE_IA_INT_PRO_IRAM1_S  (16)
-/* DPORT_CACHE_IA_INT_PRO_IRAM0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: PRO CPU invalid access to IRAM0 when cache is disabled */
-#define DPORT_CACHE_IA_INT_PRO_IRAM0    BIT(15)
-#define DPORT_CACHE_IA_INT_PRO_IRAM0_M  BIT(15)
-#define DPORT_CACHE_IA_INT_PRO_IRAM0_V  (1)
-#define DPORT_CACHE_IA_INT_PRO_IRAM0_S  (15)
-/* DPORT_CACHE_IA_INT_PRO_DROM0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: PRO CPU invalid access to DROM0 when cache is disabled */
-#define DPORT_CACHE_IA_INT_PRO_DROM0    BIT(14)
-#define DPORT_CACHE_IA_INT_PRO_DROM0_M  BIT(14)
-#define DPORT_CACHE_IA_INT_PRO_DROM0_V  (1)
-#define DPORT_CACHE_IA_INT_PRO_DROM0_S  (14)
-/* DPORT_CACHE_IA_INT_APP_OPPOSITE : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: APP CPU invalid access to APP CPU cache when cache disabled */
-#define DPORT_CACHE_IA_INT_APP_OPPOSITE    BIT(5)
-#define DPORT_CACHE_IA_INT_APP_OPPOSITE_M  BIT(5)
-#define DPORT_CACHE_IA_INT_APP_OPPOSITE_V  (1)
-#define DPORT_CACHE_IA_INT_APP_OPPOSITE_S  (5)
-/* DPORT_CACHE_IA_INT_APP_DRAM1 : R/W ;bitpos:43] ;default: 1'b0 ; */
-/*description: APP CPU invalid access to DRAM1 when cache is disabled */
-#define DPORT_CACHE_IA_INT_APP_DRAM1    BIT(4)
-#define DPORT_CACHE_IA_INT_APP_DRAM1_M  BIT(4)
-#define DPORT_CACHE_IA_INT_APP_DRAM1_V  (1)
-#define DPORT_CACHE_IA_INT_APP_DRAM1_S  (4)
-/* DPORT_CACHE_IA_INT_APP_IROM0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: APP CPU invalid access to IROM0 when cache is disabled */
-#define DPORT_CACHE_IA_INT_APP_IROM0    BIT(3)
-#define DPORT_CACHE_IA_INT_APP_IROM0_M  BIT(3)
-#define DPORT_CACHE_IA_INT_APP_IROM0_V  (1)
-#define DPORT_CACHE_IA_INT_APP_IROM0_S  (3)
-/* DPORT_CACHE_IA_INT_APP_IRAM1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: APP CPU invalid access to IRAM1 when cache is disabled */
-#define DPORT_CACHE_IA_INT_APP_IRAM1    BIT(2)
-#define DPORT_CACHE_IA_INT_APP_IRAM1_M  BIT(2)
-#define DPORT_CACHE_IA_INT_APP_IRAM1_V  (1)
-#define DPORT_CACHE_IA_INT_APP_IRAM1_S  (2)
-/* DPORT_CACHE_IA_INT_APP_IRAM0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: APP CPU invalid access to IRAM0 when cache is disabled */
-#define DPORT_CACHE_IA_INT_APP_IRAM0    BIT(1)
-#define DPORT_CACHE_IA_INT_APP_IRAM0_M  BIT(1)
-#define DPORT_CACHE_IA_INT_APP_IRAM0_V  (1)
-#define DPORT_CACHE_IA_INT_APP_IRAM0_S  (1)
-/* DPORT_CACHE_IA_INT_APP_DROM0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: APP CPU invalid access to DROM0 when cache is disabled */
-#define DPORT_CACHE_IA_INT_APP_DROM0    BIT(0)
-#define DPORT_CACHE_IA_INT_APP_DROM0_M  BIT(0)
-#define DPORT_CACHE_IA_INT_APP_DROM0_V  (1)
-#define DPORT_CACHE_IA_INT_APP_DROM0_S  (0)
-
-#define DPORT_SECURE_BOOT_CTRL_REG          (DR_REG_DPORT_BASE + 0x5A4)
-/* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_SW_BOOTLOADER_SEL  (BIT(0))
-#define DPORT_SW_BOOTLOADER_SEL_M  (BIT(0))
-#define DPORT_SW_BOOTLOADER_SEL_V  0x1
-#define DPORT_SW_BOOTLOADER_SEL_S  0
-
-#define DPORT_SPI_DMA_CHAN_SEL_REG          (DR_REG_DPORT_BASE + 0x5A8)
-/* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */
-/*description: */
-#define DPORT_SPI3_DMA_CHAN_SEL  0x00000003
-#define DPORT_SPI3_DMA_CHAN_SEL_M  ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S))
-#define DPORT_SPI3_DMA_CHAN_SEL_V  0x3
-#define DPORT_SPI3_DMA_CHAN_SEL_S  4
-/* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */
-/*description: */
-#define DPORT_SPI2_DMA_CHAN_SEL  0x00000003
-#define DPORT_SPI2_DMA_CHAN_SEL_M  ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S))
-#define DPORT_SPI2_DMA_CHAN_SEL_V  0x3
-#define DPORT_SPI2_DMA_CHAN_SEL_S  2
-/* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */
-/*description: */
-#define DPORT_SPI1_DMA_CHAN_SEL  0x00000003
-#define DPORT_SPI1_DMA_CHAN_SEL_M  ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S))
-#define DPORT_SPI1_DMA_CHAN_SEL_V  0x3
-#define DPORT_SPI1_DMA_CHAN_SEL_S  0
-
-#define DPORT_PRO_VECBASE_CTRL_REG          (DR_REG_DPORT_BASE + 0x5AC)
-/* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_PRO_OUT_VECBASE_SEL  0x00000003
-#define DPORT_PRO_OUT_VECBASE_SEL_M  ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S))
-#define DPORT_PRO_OUT_VECBASE_SEL_V  0x3
-#define DPORT_PRO_OUT_VECBASE_SEL_S  0
-
-#define DPORT_PRO_VECBASE_SET_REG          (DR_REG_DPORT_BASE + 0x5B0)
-/* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
-/*description: */
-#define DPORT_PRO_OUT_VECBASE_REG  0x003FFFFF
-#define DPORT_PRO_OUT_VECBASE_REG_M  ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S))
-#define DPORT_PRO_OUT_VECBASE_REG_V  0x3FFFFF
-#define DPORT_PRO_OUT_VECBASE_REG_S  0
-
-#define DPORT_APP_VECBASE_CTRL_REG          (DR_REG_DPORT_BASE + 0x5B4)
-/* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define DPORT_APP_OUT_VECBASE_SEL  0x00000003
-#define DPORT_APP_OUT_VECBASE_SEL_M  ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S))
-#define DPORT_APP_OUT_VECBASE_SEL_V  0x3
-#define DPORT_APP_OUT_VECBASE_SEL_S  0
-
-#define DPORT_APP_VECBASE_SET_REG          (DR_REG_DPORT_BASE + 0x5B8)
-/* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
-/*description: */
-#define DPORT_APP_OUT_VECBASE_REG  0x003FFFFF
-#define DPORT_APP_OUT_VECBASE_REG_M  ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S))
-#define DPORT_APP_OUT_VECBASE_REG_V  0x3FFFFF
-#define DPORT_APP_OUT_VECBASE_REG_S  0
-
-#define DPORT_DATE_REG          (DR_REG_DPORT_BASE + 0xFFC)
-/* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */
-/*description: */
-#define DPORT_DATE  0x0FFFFFFF
-#define DPORT_DATE_M  ((DPORT_DATE_V)<<(DPORT_DATE_S))
-#define DPORT_DATE_V  0xFFFFFFF
-#define DPORT_DATE_S  0
-#define DPORT_DPORT_DATE_VERSION 0x1605190
-
-/* Flash MMU table for PRO CPU */
-#define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF10000)
-
-/* Flash MMU table for APP CPU */
-#define DPORT_APP_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF12000)
-
-#define DPORT_FLASH_MMU_TABLE_SIZE 0x100
-
-#define DPORT_FLASH_MMU_TABLE_INVALID_VAL 0x100
-
-#endif /*_SOC_DPORT_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/efuse_reg.h b/tools/sdk/include/soc/soc/efuse_reg.h
deleted file mode 100644
index bbe96771370..00000000000
--- a/tools/sdk/include/soc/soc/efuse_reg.h
+++ /dev/null
@@ -1,1188 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_EFUSE_REG_H_
-#define _SOC_EFUSE_REG_H_
-
-
-#include "soc.h"
-#define EFUSE_BLK0_RDATA0_REG          (DR_REG_EFUSE_BASE + 0x000)
-/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; */
-/*description: read for flash_crypt_cnt*/
-#define EFUSE_RD_FLASH_CRYPT_CNT  0x0000007F
-#define EFUSE_RD_FLASH_CRYPT_CNT_M  ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S))
-#define EFUSE_RD_FLASH_CRYPT_CNT_V  0x7F
-#define EFUSE_RD_FLASH_CRYPT_CNT_S  20
-/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */
-/*description: read for efuse_rd_disable*/
-#define EFUSE_RD_EFUSE_RD_DIS  0x0000000F
-#define EFUSE_RD_EFUSE_RD_DIS_M  ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S))
-#define EFUSE_RD_EFUSE_RD_DIS_V  0xF
-#define EFUSE_RD_EFUSE_RD_DIS_S  16
-
-/* Read disable bits for efuse blocks 1-3 */
-#define EFUSE_RD_DIS_BLK1 (1<<16)
-#define EFUSE_RD_DIS_BLK2 (1<<17)
-#define EFUSE_RD_DIS_BLK3 (1<<18)
-/* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS
-   in efuse block 0
-*/
-#define EFUSE_RD_DIS_BLK0_PARTIAL (1<<19)
-
-/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: read for efuse_wr_disable*/
-#define EFUSE_RD_EFUSE_WR_DIS  0x0000FFFF
-#define EFUSE_RD_EFUSE_WR_DIS_M  ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S))
-#define EFUSE_RD_EFUSE_WR_DIS_V  0xFFFF
-#define EFUSE_RD_EFUSE_WR_DIS_S  0
-
-/* Write disable bits */
-#define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */
-#define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */
-#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2)
-#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */
-#define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */
-#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */
-#define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */
-#define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */
-#define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */
-#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */
-#define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */
-#define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */
-#define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */
-#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */
-
-#define EFUSE_BLK0_RDATA1_REG          (DR_REG_EFUSE_BASE + 0x004)
-/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: read for low 32bit WIFI_MAC_Address*/
-#define EFUSE_RD_WIFI_MAC_CRC_LOW  0xFFFFFFFF
-#define EFUSE_RD_WIFI_MAC_CRC_LOW_M  ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S))
-#define EFUSE_RD_WIFI_MAC_CRC_LOW_V  0xFFFFFFFF
-#define EFUSE_RD_WIFI_MAC_CRC_LOW_S  0
-
-#define EFUSE_BLK0_RDATA2_REG          (DR_REG_EFUSE_BASE + 0x008)
-/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: read for high 24bit WIFI_MAC_Address*/
-#define EFUSE_RD_WIFI_MAC_CRC_HIGH  0x00FFFFFF
-#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M  ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S))
-#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V  0xFFFFFF
-#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S  0
-
-#define EFUSE_BLK0_RDATA3_REG          (DR_REG_EFUSE_BASE + 0x00c)
-/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: bit is set to 1 for rev1 silicon*/
-#define EFUSE_RD_CHIP_VER_REV1  (BIT(15))
-#define EFUSE_RD_CHIP_VER_REV1_M  ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S))
-#define EFUSE_RD_CHIP_VER_REV1_V  0x1
-#define EFUSE_RD_CHIP_VER_REV1_S  15
-/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */
-/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/
-#define EFUSE_RD_BLK3_PART_RESERVE  (BIT(14))
-#define EFUSE_RD_BLK3_PART_RESERVE_M  ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S))
-#define EFUSE_RD_BLK3_PART_RESERVE_V  0x1
-#define EFUSE_RD_BLK3_PART_RESERVE_S  14
-/* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: If set, the ESP32's maximum CPU frequency has been rated*/
-#define EFUSE_RD_CHIP_CPU_FREQ_RATED  (BIT(13))
-#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M  ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S))
-#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V  0x1
-#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S  13
-/* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/
-#define EFUSE_RD_CHIP_CPU_FREQ_LOW  (BIT(12))
-#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M  ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S))
-#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V  0x1
-#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S  12
-/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
-/*description: chip package */
-#define EFUSE_RD_CHIP_VER_PKG  0x00000007
-#define EFUSE_RD_CHIP_VER_PKG_M  ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S))
-#define EFUSE_RD_CHIP_VER_PKG_V  0x7
-#define EFUSE_RD_CHIP_VER_PKG_S  9
-#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6  0
-#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5  1
-#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5  2
-#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2  4
-#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4  5
-/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
-/*description: read for SPI_pad_config_hd*/
-#define EFUSE_RD_SPI_PAD_CONFIG_HD  0x0000001F
-#define EFUSE_RD_SPI_PAD_CONFIG_HD_M  ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S))
-#define EFUSE_RD_SPI_PAD_CONFIG_HD_V  0x1F
-#define EFUSE_RD_SPI_PAD_CONFIG_HD_S  4
-/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_RD_CHIP_VER_DIS_CACHE  (BIT(3))
-#define EFUSE_RD_CHIP_VER_DIS_CACHE_M  (BIT(3))
-#define EFUSE_RD_CHIP_VER_DIS_CACHE_V  0x1
-#define EFUSE_RD_CHIP_VER_DIS_CACHE_S  3
-/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_RD_CHIP_VER_32PAD  (BIT(2))
-#define EFUSE_RD_CHIP_VER_32PAD_M  (BIT(2))
-#define EFUSE_RD_CHIP_VER_32PAD_V  0x1
-#define EFUSE_RD_CHIP_VER_32PAD_S  2
-/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_RD_CHIP_VER_DIS_BT  (BIT(1))
-#define EFUSE_RD_CHIP_VER_DIS_BT_M  (BIT(1))
-#define EFUSE_RD_CHIP_VER_DIS_BT_V  0x1
-#define EFUSE_RD_CHIP_VER_DIS_BT_S  1
-/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_RD_CHIP_VER_DIS_APP_CPU  (BIT(0))
-#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M  (BIT(0))
-#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V  0x1
-#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S  0
-
-#define EFUSE_BLK0_RDATA4_REG          (DR_REG_EFUSE_BASE + 0x010)
-/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: read for sdio_force*/
-#define EFUSE_RD_SDIO_FORCE  (BIT(16))
-#define EFUSE_RD_SDIO_FORCE_M  (BIT(16))
-#define EFUSE_RD_SDIO_FORCE_V  0x1
-#define EFUSE_RD_SDIO_FORCE_S  16
-/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: read for SDIO_TIEH*/
-#define EFUSE_RD_SDIO_TIEH  (BIT(15))
-#define EFUSE_RD_SDIO_TIEH_M  (BIT(15))
-#define EFUSE_RD_SDIO_TIEH_V  0x1
-#define EFUSE_RD_SDIO_TIEH_S  15
-/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: read for XPD_SDIO_REG*/
-#define EFUSE_RD_XPD_SDIO_REG  (BIT(14))
-#define EFUSE_RD_XPD_SDIO_REG_M  (BIT(14))
-#define EFUSE_RD_XPD_SDIO_REG_V  0x1
-#define EFUSE_RD_XPD_SDIO_REG_S  14
-/* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */
-/*description: True ADC reference voltage */
-#define EFUSE_RD_ADC_VREF  0x0000001F
-#define EFUSE_RD_ADC_VREF_M  ((EFUSE_RD_ADC_VREF_V)<<(EFUSE_RD_ADC_VREF_S))
-#define EFUSE_RD_ADC_VREF_V  0x1F
-#define EFUSE_RD_ADC_VREF_S  8
-/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer
- * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore
- * SDIO_DREFH/M/L is only available in older versions of ESP32 */
-/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: */
-#define EFUSE_RD_SDIO_DREFL  0x00000003
-#define EFUSE_RD_SDIO_DREFL_M  ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S))
-#define EFUSE_RD_SDIO_DREFL_V  0x3
-#define EFUSE_RD_SDIO_DREFL_S  12
-/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: */
-#define EFUSE_RD_SDIO_DREFM  0x00000003
-#define EFUSE_RD_SDIO_DREFM_M  ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S))
-#define EFUSE_RD_SDIO_DREFM_V  0x3
-#define EFUSE_RD_SDIO_DREFM_S  10
-/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: */
-#define EFUSE_RD_SDIO_DREFH  0x00000003
-#define EFUSE_RD_SDIO_DREFH_M  ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S))
-#define EFUSE_RD_SDIO_DREFH_V  0x3
-#define EFUSE_RD_SDIO_DREFH_S  8
-/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define EFUSE_RD_CK8M_FREQ  0x000000FF
-#define EFUSE_RD_CK8M_FREQ_M  ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S))
-#define EFUSE_RD_CK8M_FREQ_V  0xFF
-#define EFUSE_RD_CK8M_FREQ_S  0
-
-#define EFUSE_BLK0_RDATA5_REG          (DR_REG_EFUSE_BASE + 0x014)
-/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */
-/*description: read for flash_crypt_config*/
-#define EFUSE_RD_FLASH_CRYPT_CONFIG  0x0000000F
-#define EFUSE_RD_FLASH_CRYPT_CONFIG_M  ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S))
-#define EFUSE_RD_FLASH_CRYPT_CONFIG_V  0xF
-#define EFUSE_RD_FLASH_CRYPT_CONFIG_S  28
-/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */
-/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO) 
-  BIT[27] is the sign bit, 0: + , 1: -
-  BIT[26:24] is the difference value, unit: 0.017V 
-  volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017     */
-#define EFUSE_RD_DIG_VOL_L6          0x0F
-#define EFUSE_RD_DIG_VOL_L6_M        ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
-#define EFUSE_RD_DIG_VOL_L6_V        0x0F
-#define EFUSE_RD_DIG_VOL_L6_S        24
-/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */
-/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 
-0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/
-#define EFUSE_RD_VOL_LEVEL_HP_INV    0x03
-#define EFUSE_RD_VOL_LEVEL_HP_INV_M  ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
-#define EFUSE_RD_VOL_LEVEL_HP_INV_V  0x03
-#define EFUSE_RD_VOL_LEVEL_HP_INV_S  22
-/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */
-/* Deprecated */
-#define EFUSE_RD_INST_CONFIG  0x000000FF                                              /** Deprecated **/
-#define EFUSE_RD_INST_CONFIG_M  ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S))  /** Deprecated **/
-#define EFUSE_RD_INST_CONFIG_V  0xFF                                                  /** Deprecated **/
-#define EFUSE_RD_INST_CONFIG_S  20                                                    /** Deprecated **/
-/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */
-/*description: read for SPI_pad_config_cs0*/
-#define EFUSE_RD_SPI_PAD_CONFIG_CS0  0x0000001F
-#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M  ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S))
-#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V  0x1F
-#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S  15
-/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */
-/*description: read for SPI_pad_config_d*/
-#define EFUSE_RD_SPI_PAD_CONFIG_D  0x0000001F
-#define EFUSE_RD_SPI_PAD_CONFIG_D_M  ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S))
-#define EFUSE_RD_SPI_PAD_CONFIG_D_V  0x1F
-#define EFUSE_RD_SPI_PAD_CONFIG_D_S  10
-/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */
-/*description: read for SPI_pad_config_q*/
-#define EFUSE_RD_SPI_PAD_CONFIG_Q  0x0000001F
-#define EFUSE_RD_SPI_PAD_CONFIG_Q_M  ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S))
-#define EFUSE_RD_SPI_PAD_CONFIG_Q_V  0x1F
-#define EFUSE_RD_SPI_PAD_CONFIG_Q_S  5
-/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */
-/*description: read for SPI_pad_config_clk*/
-#define EFUSE_RD_SPI_PAD_CONFIG_CLK  0x0000001F
-#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M  ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S))
-#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V  0x1F
-#define EFUSE_RD_SPI_PAD_CONFIG_CLK_S  0
-
-#define EFUSE_BLK0_RDATA6_REG          (DR_REG_EFUSE_BASE + 0x018)
-/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: read for key_status*/
-#define EFUSE_RD_KEY_STATUS  (BIT(10))
-#define EFUSE_RD_KEY_STATUS_M  (BIT(10))
-#define EFUSE_RD_KEY_STATUS_V  0x1
-#define EFUSE_RD_KEY_STATUS_S  10
-/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: read for download_dis_cache*/
-#define EFUSE_RD_DISABLE_DL_CACHE  (BIT(9))
-#define EFUSE_RD_DISABLE_DL_CACHE_M  (BIT(9))
-#define EFUSE_RD_DISABLE_DL_CACHE_V  0x1
-#define EFUSE_RD_DISABLE_DL_CACHE_S  9
-/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: read for download_dis_decrypt*/
-#define EFUSE_RD_DISABLE_DL_DECRYPT  (BIT(8))
-#define EFUSE_RD_DISABLE_DL_DECRYPT_M  (BIT(8))
-#define EFUSE_RD_DISABLE_DL_DECRYPT_V  0x1
-#define EFUSE_RD_DISABLE_DL_DECRYPT_S  8
-/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: read for download_dis_encrypt*/
-#define EFUSE_RD_DISABLE_DL_ENCRYPT  (BIT(7))
-#define EFUSE_RD_DISABLE_DL_ENCRYPT_M  (BIT(7))
-#define EFUSE_RD_DISABLE_DL_ENCRYPT_V  0x1
-#define EFUSE_RD_DISABLE_DL_ENCRYPT_S  7
-/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: read for JTAG_disable*/
-#define EFUSE_RD_DISABLE_JTAG  (BIT(6))
-#define EFUSE_RD_DISABLE_JTAG_M  (BIT(6))
-#define EFUSE_RD_DISABLE_JTAG_V  0x1
-#define EFUSE_RD_DISABLE_JTAG_S  6
-/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: read for abstract_done_1*/
-#define EFUSE_RD_ABS_DONE_1  (BIT(5))
-#define EFUSE_RD_ABS_DONE_1_M  (BIT(5))
-#define EFUSE_RD_ABS_DONE_1_V  0x1
-#define EFUSE_RD_ABS_DONE_1_S  5
-/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: read for abstract_done_0*/
-#define EFUSE_RD_ABS_DONE_0  (BIT(4))
-#define EFUSE_RD_ABS_DONE_0_M  (BIT(4))
-#define EFUSE_RD_ABS_DONE_0_V  0x1
-#define EFUSE_RD_ABS_DONE_0_S  4
-/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_RD_DISABLE_SDIO_HOST  (BIT(3))
-#define EFUSE_RD_DISABLE_SDIO_HOST_M  (BIT(3))
-#define EFUSE_RD_DISABLE_SDIO_HOST_V  0x1
-#define EFUSE_RD_DISABLE_SDIO_HOST_S  3
-/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: read for console_debug_disable*/
-#define EFUSE_RD_CONSOLE_DEBUG_DISABLE  (BIT(2))
-#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M  (BIT(2))
-#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V  0x1
-#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S  2
-/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: read for coding_scheme*/
-#define EFUSE_RD_CODING_SCHEME  0x00000003
-#define EFUSE_RD_CODING_SCHEME_M  ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S))
-#define EFUSE_RD_CODING_SCHEME_V  0x3
-#define EFUSE_RD_CODING_SCHEME_S  0
-
-#define EFUSE_CODING_SCHEME_VAL_NONE 0x0
-#define EFUSE_CODING_SCHEME_VAL_34   0x1
-#define EFUSE_CODING_SCHEME_VAL_REPEAT   0x2
-
-#define EFUSE_BLK0_WDATA0_REG          (DR_REG_EFUSE_BASE + 0x01c)
-/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; */
-/*description: program for flash_crypt_cnt*/
-#define EFUSE_FLASH_CRYPT_CNT  0x0000007F
-#define EFUSE_FLASH_CRYPT_CNT_M  ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S))
-#define EFUSE_FLASH_CRYPT_CNT_V  0x7F
-#define EFUSE_FLASH_CRYPT_CNT_S  20
-/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */
-/*description: program for efuse_rd_disable*/
-#define EFUSE_RD_DIS  0x0000000F
-#define EFUSE_RD_DIS_M  ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
-#define EFUSE_RD_DIS_V  0xF
-#define EFUSE_RD_DIS_S  16
-/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: program for efuse_wr_disable*/
-#define EFUSE_WR_DIS  0x0000FFFF
-#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
-#define EFUSE_WR_DIS_V  0xFFFF
-#define EFUSE_WR_DIS_S  0
-
-#define EFUSE_BLK0_WDATA1_REG          (DR_REG_EFUSE_BASE + 0x020)
-/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: program for low 32bit WIFI_MAC_Address*/
-#define EFUSE_WIFI_MAC_CRC_LOW  0xFFFFFFFF
-#define EFUSE_WIFI_MAC_CRC_LOW_M  ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S))
-#define EFUSE_WIFI_MAC_CRC_LOW_V  0xFFFFFFFF
-#define EFUSE_WIFI_MAC_CRC_LOW_S  0
-
-#define EFUSE_BLK0_WDATA2_REG          (DR_REG_EFUSE_BASE + 0x024)
-/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: program for high 24bit WIFI_MAC_Address*/
-#define EFUSE_WIFI_MAC_CRC_HIGH  0x00FFFFFF
-#define EFUSE_WIFI_MAC_CRC_HIGH_M  ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S))
-#define EFUSE_WIFI_MAC_CRC_HIGH_V  0xFFFFFF
-#define EFUSE_WIFI_MAC_CRC_HIGH_S  0
-
-#define EFUSE_BLK0_WDATA3_REG          (DR_REG_EFUSE_BASE + 0x028)
-/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_CHIP_VER_REV1  (BIT(15))
-#define EFUSE_CHIP_VER_REV1_M  ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S))
-#define EFUSE_CHIP_VER_REV1_V  0x1
-#define EFUSE_CHIP_VER_REV1_S  15
-/* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */
-/*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/
-#define EFUSE_BLK3_PART_RESERVE  (BIT(14))
-#define EFUSE_BLK3_PART_RESERVE_M  ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S))
-#define EFUSE_BLK3_PART_RESERVE_V  0x1
-#define EFUSE_BLK3_PART_RESERVE_S  14
-/* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: If set, the ESP32's maximum CPU frequency has been rated*/
-#define EFUSE_CHIP_CPU_FREQ_RATED  (BIT(13))
-#define EFUSE_CHIP_CPU_FREQ_RATED_M  ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S))
-#define EFUSE_CHIP_CPU_FREQ_RATED_V  0x1
-#define EFUSE_CHIP_CPU_FREQ_RATED_S  13
-/* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/
-#define EFUSE_CHIP_CPU_FREQ_LOW  (BIT(12))
-#define EFUSE_CHIP_CPU_FREQ_LOW_M  ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S))
-#define EFUSE_CHIP_CPU_FREQ_LOW_V  0x1
-#define EFUSE_CHIP_CPU_FREQ_LOW_S  12
-/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
-/*description: */
-#define EFUSE_CHIP_VER_PKG  0x00000007
-#define EFUSE_CHIP_VER_PKG_M  ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S))
-#define EFUSE_CHIP_VER_PKG_V  0x7
-#define EFUSE_CHIP_VER_PKG_S  9
-#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6  0
-#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5  1
-#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5  2
-#define EFUSE_CHIP_VER_PKG_ESP32PICOD2  4
-#define EFUSE_CHIP_VER_PKG_ESP32PICOD4  5
-/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
-/*description: program for SPI_pad_config_hd*/
-#define EFUSE_SPI_PAD_CONFIG_HD  0x0000001F
-#define EFUSE_SPI_PAD_CONFIG_HD_M  ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S))
-#define EFUSE_SPI_PAD_CONFIG_HD_V  0x1F
-#define EFUSE_SPI_PAD_CONFIG_HD_S  4
-/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_CHIP_VER_DIS_CACHE  (BIT(3))
-#define EFUSE_CHIP_VER_DIS_CACHE_M  (BIT(3))
-#define EFUSE_CHIP_VER_DIS_CACHE_V  0x1
-#define EFUSE_CHIP_VER_DIS_CACHE_S  3
-/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_CHIP_VER_32PAD  (BIT(2))
-#define EFUSE_CHIP_VER_32PAD_M  (BIT(2))
-#define EFUSE_CHIP_VER_32PAD_V  0x1
-#define EFUSE_CHIP_VER_32PAD_S  2
-/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_CHIP_VER_DIS_BT  (BIT(1))
-#define EFUSE_CHIP_VER_DIS_BT_M  (BIT(1))
-#define EFUSE_CHIP_VER_DIS_BT_V  0x1
-#define EFUSE_CHIP_VER_DIS_BT_S  1
-/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_CHIP_VER_DIS_APP_CPU  (BIT(0))
-#define EFUSE_CHIP_VER_DIS_APP_CPU_M  (BIT(0))
-#define EFUSE_CHIP_VER_DIS_APP_CPU_V  0x1
-#define EFUSE_CHIP_VER_DIS_APP_CPU_S  0
-
-#define EFUSE_BLK0_WDATA4_REG          (DR_REG_EFUSE_BASE + 0x02c)
-/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: program for sdio_force*/
-#define EFUSE_SDIO_FORCE  (BIT(16))
-#define EFUSE_SDIO_FORCE_M  (BIT(16))
-#define EFUSE_SDIO_FORCE_V  0x1
-#define EFUSE_SDIO_FORCE_S  16
-/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: program for SDIO_TIEH*/
-#define EFUSE_SDIO_TIEH  (BIT(15))
-#define EFUSE_SDIO_TIEH_M  (BIT(15))
-#define EFUSE_SDIO_TIEH_V  0x1
-#define EFUSE_SDIO_TIEH_S  15
-/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: program for XPD_SDIO_REG*/
-#define EFUSE_XPD_SDIO_REG  (BIT(14))
-#define EFUSE_XPD_SDIO_REG_M  (BIT(14))
-#define EFUSE_XPD_SDIO_REG_V  0x1
-#define EFUSE_XPD_SDIO_REG_S  14
-/* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */
-/*description: True ADC reference voltage */
-#define EFUSE_ADC_VREF  0x0000001F
-#define EFUSE_ADC_VREF_M  ((EFUSE_ADC_VREF_V)<<(EFUSE_ADC_VREF_S))
-#define EFUSE_ADC_VREF_V  0x1F
-#define EFUSE_ADC_VREF_S  8
-/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer
- * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore
- * SDIO_DREFH/M/L is only available in older versions of ESP32 */
-/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: */
-#define EFUSE_SDIO_DREFL  0x00000003
-#define EFUSE_SDIO_DREFL_M  ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S))
-#define EFUSE_SDIO_DREFL_V  0x3
-#define EFUSE_SDIO_DREFL_S  12
-/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: */
-#define EFUSE_SDIO_DREFM  0x00000003
-#define EFUSE_SDIO_DREFM_M  ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S))
-#define EFUSE_SDIO_DREFM_V  0x3
-#define EFUSE_SDIO_DREFM_S  10
-/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: */
-#define EFUSE_SDIO_DREFH  0x00000003
-#define EFUSE_SDIO_DREFH_M  ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S))
-#define EFUSE_SDIO_DREFH_V  0x3
-#define EFUSE_SDIO_DREFH_S  8
-/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define EFUSE_CK8M_FREQ  0x000000FF
-#define EFUSE_CK8M_FREQ_M  ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S))
-#define EFUSE_CK8M_FREQ_V  0xFF
-#define EFUSE_CK8M_FREQ_S  0
-
-#define EFUSE_BLK0_WDATA5_REG          (DR_REG_EFUSE_BASE + 0x030)
-/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */
-/*description: program for flash_crypt_config*/
-#define EFUSE_FLASH_CRYPT_CONFIG  0x0000000F
-#define EFUSE_FLASH_CRYPT_CONFIG_M  ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S))
-#define EFUSE_FLASH_CRYPT_CONFIG_V  0xF
-#define EFUSE_FLASH_CRYPT_CONFIG_S  28
-/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */
-/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W) 
-  BIT[27] is the sign bit, 0: + , 1: -
-  BIT[26:24] is the difference value, unit: 0.017V 
-  volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017     */
-#define EFUSE_DIG_VOL_L6            0x0F
-#define EFUSE_DIG_VOL_L6_M          ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
-#define EFUSE_DIG_VOL_L6_V          0x0F
-#define EFUSE_DIG_VOL_L6_S          24
-/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */
-/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 
-0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/
-#define EFUSE_VOL_LEVEL_HP_INV      0x03
-#define EFUSE_VOL_LEVEL_HP_INV_M    ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
-#define EFUSE_VOL_LEVEL_HP_INV_V    0x03
-#define EFUSE_VOL_LEVEL_HP_INV_S    22
-/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
-/* Deprecated */
-#define EFUSE_INST_CONFIG  0x000000FF                                        /** Deprecated **/
-#define EFUSE_INST_CONFIG_M  ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S))  /** Deprecated **/
-#define EFUSE_INST_CONFIG_V  0xFF                                            /** Deprecated **/
-#define EFUSE_INST_CONFIG_S  20                                              /** Deprecated **/
-/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
-/*description: program for SPI_pad_config_cs0*/
-#define EFUSE_SPI_PAD_CONFIG_CS0  0x0000001F
-#define EFUSE_SPI_PAD_CONFIG_CS0_M  ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S))
-#define EFUSE_SPI_PAD_CONFIG_CS0_V  0x1F
-#define EFUSE_SPI_PAD_CONFIG_CS0_S  15
-/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */
-/*description: program for SPI_pad_config_d*/
-#define EFUSE_SPI_PAD_CONFIG_D  0x0000001F
-#define EFUSE_SPI_PAD_CONFIG_D_M  ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S))
-#define EFUSE_SPI_PAD_CONFIG_D_V  0x1F
-#define EFUSE_SPI_PAD_CONFIG_D_S  10
-/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */
-/*description: program for SPI_pad_config_q*/
-#define EFUSE_SPI_PAD_CONFIG_Q  0x0000001F
-#define EFUSE_SPI_PAD_CONFIG_Q_M  ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S))
-#define EFUSE_SPI_PAD_CONFIG_Q_V  0x1F
-#define EFUSE_SPI_PAD_CONFIG_Q_S  5
-/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */
-/*description: program for SPI_pad_config_clk*/
-#define EFUSE_SPI_PAD_CONFIG_CLK  0x0000001F
-#define EFUSE_SPI_PAD_CONFIG_CLK_M  ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S))
-#define EFUSE_SPI_PAD_CONFIG_CLK_V  0x1F
-#define EFUSE_SPI_PAD_CONFIG_CLK_S  0
-
-#define EFUSE_BLK0_WDATA6_REG          (DR_REG_EFUSE_BASE + 0x034)
-/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: program for key_status*/
-#define EFUSE_KEY_STATUS  (BIT(10))
-#define EFUSE_KEY_STATUS_M  (BIT(10))
-#define EFUSE_KEY_STATUS_V  0x1
-#define EFUSE_KEY_STATUS_S  10
-/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: program for download_dis_cache*/
-#define EFUSE_DISABLE_DL_CACHE  (BIT(9))
-#define EFUSE_DISABLE_DL_CACHE_M  (BIT(9))
-#define EFUSE_DISABLE_DL_CACHE_V  0x1
-#define EFUSE_DISABLE_DL_CACHE_S  9
-/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: program for download_dis_decrypt*/
-#define EFUSE_DISABLE_DL_DECRYPT  (BIT(8))
-#define EFUSE_DISABLE_DL_DECRYPT_M  (BIT(8))
-#define EFUSE_DISABLE_DL_DECRYPT_V  0x1
-#define EFUSE_DISABLE_DL_DECRYPT_S  8
-/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: program for download_dis_encrypt*/
-#define EFUSE_DISABLE_DL_ENCRYPT  (BIT(7))
-#define EFUSE_DISABLE_DL_ENCRYPT_M  (BIT(7))
-#define EFUSE_DISABLE_DL_ENCRYPT_V  0x1
-#define EFUSE_DISABLE_DL_ENCRYPT_S  7
-/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: program for JTAG_disable*/
-#define EFUSE_DISABLE_JTAG  (BIT(6))
-#define EFUSE_DISABLE_JTAG_M  (BIT(6))
-#define EFUSE_DISABLE_JTAG_V  0x1
-#define EFUSE_DISABLE_JTAG_S  6
-/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: program for abstract_done_1*/
-#define EFUSE_ABS_DONE_1  (BIT(5))
-#define EFUSE_ABS_DONE_1_M  (BIT(5))
-#define EFUSE_ABS_DONE_1_V  0x1
-#define EFUSE_ABS_DONE_1_S  5
-/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: program for abstract_done_0*/
-#define EFUSE_ABS_DONE_0  (BIT(4))
-#define EFUSE_ABS_DONE_0_M  (BIT(4))
-#define EFUSE_ABS_DONE_0_V  0x1
-#define EFUSE_ABS_DONE_0_S  4
-/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_DISABLE_SDIO_HOST  (BIT(3))
-#define EFUSE_DISABLE_SDIO_HOST_M  (BIT(3))
-#define EFUSE_DISABLE_SDIO_HOST_V  0x1
-#define EFUSE_DISABLE_SDIO_HOST_S  3
-/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: program for console_debug_disable*/
-#define EFUSE_CONSOLE_DEBUG_DISABLE  (BIT(2))
-#define EFUSE_CONSOLE_DEBUG_DISABLE_M  (BIT(2))
-#define EFUSE_CONSOLE_DEBUG_DISABLE_V  0x1
-#define EFUSE_CONSOLE_DEBUG_DISABLE_S  2
-/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: program for coding_scheme*/
-#define EFUSE_CODING_SCHEME  0x00000003
-#define EFUSE_CODING_SCHEME_M  ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S))
-#define EFUSE_CODING_SCHEME_V  0x3
-#define EFUSE_CODING_SCHEME_S  0
-
-#define EFUSE_BLK1_RDATA0_REG          (DR_REG_EFUSE_BASE + 0x038)
-/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK1*/
-#define EFUSE_BLK1_DOUT0  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT0_M  ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S))
-#define EFUSE_BLK1_DOUT0_V  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT0_S  0
-
-#define EFUSE_BLK1_RDATA1_REG          (DR_REG_EFUSE_BASE + 0x03c)
-/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK1*/
-#define EFUSE_BLK1_DOUT1  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT1_M  ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S))
-#define EFUSE_BLK1_DOUT1_V  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT1_S  0
-
-#define EFUSE_BLK1_RDATA2_REG          (DR_REG_EFUSE_BASE + 0x040)
-/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK1*/
-#define EFUSE_BLK1_DOUT2  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT2_M  ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S))
-#define EFUSE_BLK1_DOUT2_V  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT2_S  0
-
-#define EFUSE_BLK1_RDATA3_REG          (DR_REG_EFUSE_BASE + 0x044)
-/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK1*/
-#define EFUSE_BLK1_DOUT3  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT3_M  ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S))
-#define EFUSE_BLK1_DOUT3_V  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT3_S  0
-
-#define EFUSE_BLK1_RDATA4_REG          (DR_REG_EFUSE_BASE + 0x048)
-/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK1*/
-#define EFUSE_BLK1_DOUT4  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT4_M  ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S))
-#define EFUSE_BLK1_DOUT4_V  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT4_S  0
-
-#define EFUSE_BLK1_RDATA5_REG          (DR_REG_EFUSE_BASE + 0x04c)
-/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK1*/
-#define EFUSE_BLK1_DOUT5  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT5_M  ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S))
-#define EFUSE_BLK1_DOUT5_V  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT5_S  0
-
-#define EFUSE_BLK1_RDATA6_REG          (DR_REG_EFUSE_BASE + 0x050)
-/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK1*/
-#define EFUSE_BLK1_DOUT6  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT6_M  ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S))
-#define EFUSE_BLK1_DOUT6_V  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT6_S  0
-
-#define EFUSE_BLK1_RDATA7_REG          (DR_REG_EFUSE_BASE + 0x054)
-/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK1*/
-#define EFUSE_BLK1_DOUT7  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT7_M  ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S))
-#define EFUSE_BLK1_DOUT7_V  0xFFFFFFFF
-#define EFUSE_BLK1_DOUT7_S  0
-
-#define EFUSE_BLK2_RDATA0_REG          (DR_REG_EFUSE_BASE + 0x058)
-/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK2*/
-#define EFUSE_BLK2_DOUT0  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT0_M  ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S))
-#define EFUSE_BLK2_DOUT0_V  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT0_S  0
-
-#define EFUSE_BLK2_RDATA1_REG          (DR_REG_EFUSE_BASE + 0x05c)
-/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK2*/
-#define EFUSE_BLK2_DOUT1  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT1_M  ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S))
-#define EFUSE_BLK2_DOUT1_V  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT1_S  0
-
-#define EFUSE_BLK2_RDATA2_REG          (DR_REG_EFUSE_BASE + 0x060)
-/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK2*/
-#define EFUSE_BLK2_DOUT2  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT2_M  ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S))
-#define EFUSE_BLK2_DOUT2_V  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT2_S  0
-
-#define EFUSE_BLK2_RDATA3_REG          (DR_REG_EFUSE_BASE + 0x064)
-/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK2*/
-#define EFUSE_BLK2_DOUT3  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT3_M  ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S))
-#define EFUSE_BLK2_DOUT3_V  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT3_S  0
-
-#define EFUSE_BLK2_RDATA4_REG          (DR_REG_EFUSE_BASE + 0x068)
-/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK2*/
-#define EFUSE_BLK2_DOUT4  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT4_M  ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S))
-#define EFUSE_BLK2_DOUT4_V  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT4_S  0
-
-#define EFUSE_BLK2_RDATA5_REG          (DR_REG_EFUSE_BASE + 0x06c)
-/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK2*/
-#define EFUSE_BLK2_DOUT5  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT5_M  ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S))
-#define EFUSE_BLK2_DOUT5_V  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT5_S  0
-
-#define EFUSE_BLK2_RDATA6_REG          (DR_REG_EFUSE_BASE + 0x070)
-/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK2*/
-#define EFUSE_BLK2_DOUT6  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT6_M  ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S))
-#define EFUSE_BLK2_DOUT6_V  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT6_S  0
-
-#define EFUSE_BLK2_RDATA7_REG          (DR_REG_EFUSE_BASE + 0x074)
-/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK2*/
-#define EFUSE_BLK2_DOUT7  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT7_M  ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S))
-#define EFUSE_BLK2_DOUT7_V  0xFFFFFFFF
-#define EFUSE_BLK2_DOUT7_S  0
-
-#define EFUSE_BLK3_RDATA0_REG          (DR_REG_EFUSE_BASE + 0x078)
-/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK3*/
-#define EFUSE_BLK3_DOUT0  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT0_M  ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S))
-#define EFUSE_BLK3_DOUT0_V  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT0_S  0
-
-#define EFUSE_BLK3_RDATA1_REG          (DR_REG_EFUSE_BASE + 0x07c)
-/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK3*/
-#define EFUSE_BLK3_DOUT1  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT1_M  ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S))
-#define EFUSE_BLK3_DOUT1_V  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT1_S  0
-
-#define EFUSE_BLK3_RDATA2_REG          (DR_REG_EFUSE_BASE + 0x080)
-/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK3*/
-#define EFUSE_BLK3_DOUT2  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT2_M  ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S))
-#define EFUSE_BLK3_DOUT2_V  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT2_S  0
-
-/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration
- * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/
-#define EFUSE_BLK3_RDATA3_REG          (DR_REG_EFUSE_BASE + 0x084)
-/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK3*/
-#define EFUSE_BLK3_DOUT3  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT3_M  ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S))
-#define EFUSE_BLK3_DOUT3_V  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT3_S  0
-/* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */
-/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
-#define EFUSE_RD_ADC2_TP_HIGH  0x1FF
-#define EFUSE_RD_ADC2_TP_HIGH_M  ((EFUSE_RD_ADC2_TP_HIGH_V)<<(EFUSE_RD_ADC2_TP_HIGH_S))
-#define EFUSE_RD_ADC2_TP_HIGH_V  0x1FF
-#define EFUSE_RD_ADC2_TP_HIGH_S  23
-/* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */
-/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
-#define EFUSE_RD_ADC2_TP_LOW  0x7F
-#define EFUSE_RD_ADC2_TP_LOW_M  ((EFUSE_RD_ADC2_TP_LOW_V)<<(EFUSE_RD_ADC2_TP_LOW_S))
-#define EFUSE_RD_ADC2_TP_LOW_V  0x7F
-#define EFUSE_RD_ADC2_TP_LOW_S  16
-/* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */
-/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
-#define EFUSE_RD_ADC1_TP_HIGH  0x1FF
-#define EFUSE_RD_ADC1_TP_HIGH_M  ((EFUSE_RD_ADC1_TP_HIGH_V)<<(EFUSE_RD_ADC1_TP_HIGH_S))
-#define EFUSE_RD_ADC1_TP_HIGH_V  0x1FF
-#define EFUSE_RD_ADC1_TP_HIGH_S  7
-/* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
-/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
-#define EFUSE_RD_ADC1_TP_LOW  0x7F
-#define EFUSE_RD_ADC1_TP_LOW_M  ((EFUSE_RD_ADC1_TP_LOW_V)<<(EFUSE_RD_ADC1_TP_LOW_S))
-#define EFUSE_RD_ADC1_TP_LOW_V  0x7F
-#define EFUSE_RD_ADC1_TP_LOW_S  0
-
-#define EFUSE_BLK3_RDATA4_REG          (DR_REG_EFUSE_BASE + 0x088)
-/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK3*/
-#define EFUSE_BLK3_DOUT4  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT4_M  ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S))
-#define EFUSE_BLK3_DOUT4_V  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT4_S  0
-/* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */
-/*description: Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE */
-#define EFUSE_RD_CAL_RESERVED  0x0000FFFF
-#define EFUSE_RD_CAL_RESERVED_M  ((EFUSE_RD_CAL_RESERVED_V)<<(EFUSE_RD_CAL_RESERVED_S))
-#define EFUSE_RD_CAL_RESERVED_V  0xFFFF
-#define EFUSE_RD_CAL_RESERVED_S  0
-
-#define EFUSE_BLK3_RDATA5_REG          (DR_REG_EFUSE_BASE + 0x08c)
-/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK3*/
-#define EFUSE_BLK3_DOUT5  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT5_M  ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S))
-#define EFUSE_BLK3_DOUT5_V  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT5_S  0
-
-#define EFUSE_BLK3_RDATA6_REG          (DR_REG_EFUSE_BASE + 0x090)
-/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK3*/
-#define EFUSE_BLK3_DOUT6  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT6_M  ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S))
-#define EFUSE_BLK3_DOUT6_V  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT6_S  0
-
-#define EFUSE_BLK3_RDATA7_REG          (DR_REG_EFUSE_BASE + 0x094)
-/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: read for BLOCK3*/
-#define EFUSE_BLK3_DOUT7  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT7_M  ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S))
-#define EFUSE_BLK3_DOUT7_V  0xFFFFFFFF
-#define EFUSE_BLK3_DOUT7_S  0
-
-#define EFUSE_BLK1_WDATA0_REG          (DR_REG_EFUSE_BASE + 0x098)
-/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK1*/
-#define EFUSE_BLK1_DIN0  0xFFFFFFFF
-#define EFUSE_BLK1_DIN0_M  ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S))
-#define EFUSE_BLK1_DIN0_V  0xFFFFFFFF
-#define EFUSE_BLK1_DIN0_S  0
-
-#define EFUSE_BLK1_WDATA1_REG          (DR_REG_EFUSE_BASE + 0x09c)
-/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK1*/
-#define EFUSE_BLK1_DIN1  0xFFFFFFFF
-#define EFUSE_BLK1_DIN1_M  ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S))
-#define EFUSE_BLK1_DIN1_V  0xFFFFFFFF
-#define EFUSE_BLK1_DIN1_S  0
-
-#define EFUSE_BLK1_WDATA2_REG          (DR_REG_EFUSE_BASE + 0x0a0)
-/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK1*/
-#define EFUSE_BLK1_DIN2  0xFFFFFFFF
-#define EFUSE_BLK1_DIN2_M  ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S))
-#define EFUSE_BLK1_DIN2_V  0xFFFFFFFF
-#define EFUSE_BLK1_DIN2_S  0
-
-#define EFUSE_BLK1_WDATA3_REG          (DR_REG_EFUSE_BASE + 0x0a4)
-/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK1*/
-#define EFUSE_BLK1_DIN3  0xFFFFFFFF
-#define EFUSE_BLK1_DIN3_M  ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S))
-#define EFUSE_BLK1_DIN3_V  0xFFFFFFFF
-#define EFUSE_BLK1_DIN3_S  0
-
-#define EFUSE_BLK1_WDATA4_REG          (DR_REG_EFUSE_BASE + 0x0a8)
-/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK1*/
-#define EFUSE_BLK1_DIN4  0xFFFFFFFF
-#define EFUSE_BLK1_DIN4_M  ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S))
-#define EFUSE_BLK1_DIN4_V  0xFFFFFFFF
-#define EFUSE_BLK1_DIN4_S  0
-
-#define EFUSE_BLK1_WDATA5_REG          (DR_REG_EFUSE_BASE + 0x0ac)
-/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK1*/
-#define EFUSE_BLK1_DIN5  0xFFFFFFFF
-#define EFUSE_BLK1_DIN5_M  ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S))
-#define EFUSE_BLK1_DIN5_V  0xFFFFFFFF
-#define EFUSE_BLK1_DIN5_S  0
-
-#define EFUSE_BLK1_WDATA6_REG          (DR_REG_EFUSE_BASE + 0x0b0)
-/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK1*/
-#define EFUSE_BLK1_DIN6  0xFFFFFFFF
-#define EFUSE_BLK1_DIN6_M  ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S))
-#define EFUSE_BLK1_DIN6_V  0xFFFFFFFF
-#define EFUSE_BLK1_DIN6_S  0
-
-#define EFUSE_BLK1_WDATA7_REG          (DR_REG_EFUSE_BASE + 0x0b4)
-/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK1*/
-#define EFUSE_BLK1_DIN7  0xFFFFFFFF
-#define EFUSE_BLK1_DIN7_M  ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S))
-#define EFUSE_BLK1_DIN7_V  0xFFFFFFFF
-#define EFUSE_BLK1_DIN7_S  0
-
-#define EFUSE_BLK2_WDATA0_REG          (DR_REG_EFUSE_BASE + 0x0b8)
-/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK2*/
-#define EFUSE_BLK2_DIN0  0xFFFFFFFF
-#define EFUSE_BLK2_DIN0_M  ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S))
-#define EFUSE_BLK2_DIN0_V  0xFFFFFFFF
-#define EFUSE_BLK2_DIN0_S  0
-
-#define EFUSE_BLK2_WDATA1_REG          (DR_REG_EFUSE_BASE + 0x0bc)
-/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK2*/
-#define EFUSE_BLK2_DIN1  0xFFFFFFFF
-#define EFUSE_BLK2_DIN1_M  ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S))
-#define EFUSE_BLK2_DIN1_V  0xFFFFFFFF
-#define EFUSE_BLK2_DIN1_S  0
-
-#define EFUSE_BLK2_WDATA2_REG          (DR_REG_EFUSE_BASE + 0x0c0)
-/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK2*/
-#define EFUSE_BLK2_DIN2  0xFFFFFFFF
-#define EFUSE_BLK2_DIN2_M  ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S))
-#define EFUSE_BLK2_DIN2_V  0xFFFFFFFF
-#define EFUSE_BLK2_DIN2_S  0
-
-#define EFUSE_BLK2_WDATA3_REG          (DR_REG_EFUSE_BASE + 0x0c4)
-/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK2*/
-#define EFUSE_BLK2_DIN3  0xFFFFFFFF
-#define EFUSE_BLK2_DIN3_M  ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S))
-#define EFUSE_BLK2_DIN3_V  0xFFFFFFFF
-#define EFUSE_BLK2_DIN3_S  0
-
-#define EFUSE_BLK2_WDATA4_REG          (DR_REG_EFUSE_BASE + 0x0c8)
-/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK2*/
-#define EFUSE_BLK2_DIN4  0xFFFFFFFF
-#define EFUSE_BLK2_DIN4_M  ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S))
-#define EFUSE_BLK2_DIN4_V  0xFFFFFFFF
-#define EFUSE_BLK2_DIN4_S  0
-
-#define EFUSE_BLK2_WDATA5_REG          (DR_REG_EFUSE_BASE + 0x0cc)
-/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK2*/
-#define EFUSE_BLK2_DIN5  0xFFFFFFFF
-#define EFUSE_BLK2_DIN5_M  ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S))
-#define EFUSE_BLK2_DIN5_V  0xFFFFFFFF
-#define EFUSE_BLK2_DIN5_S  0
-
-#define EFUSE_BLK2_WDATA6_REG          (DR_REG_EFUSE_BASE + 0x0d0)
-/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK2*/
-#define EFUSE_BLK2_DIN6  0xFFFFFFFF
-#define EFUSE_BLK2_DIN6_M  ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S))
-#define EFUSE_BLK2_DIN6_V  0xFFFFFFFF
-#define EFUSE_BLK2_DIN6_S  0
-
-#define EFUSE_BLK2_WDATA7_REG          (DR_REG_EFUSE_BASE + 0x0d4)
-/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK2*/
-#define EFUSE_BLK2_DIN7  0xFFFFFFFF
-#define EFUSE_BLK2_DIN7_M  ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S))
-#define EFUSE_BLK2_DIN7_V  0xFFFFFFFF
-#define EFUSE_BLK2_DIN7_S  0
-
-#define EFUSE_BLK3_WDATA0_REG          (DR_REG_EFUSE_BASE + 0x0d8)
-/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK3*/
-#define EFUSE_BLK3_DIN0  0xFFFFFFFF
-#define EFUSE_BLK3_DIN0_M  ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S))
-#define EFUSE_BLK3_DIN0_V  0xFFFFFFFF
-#define EFUSE_BLK3_DIN0_S  0
-
-#define EFUSE_BLK3_WDATA1_REG          (DR_REG_EFUSE_BASE + 0x0dc)
-/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK3*/
-#define EFUSE_BLK3_DIN1  0xFFFFFFFF
-#define EFUSE_BLK3_DIN1_M  ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S))
-#define EFUSE_BLK3_DIN1_V  0xFFFFFFFF
-#define EFUSE_BLK3_DIN1_S  0
-
-#define EFUSE_BLK3_WDATA2_REG          (DR_REG_EFUSE_BASE + 0x0e0)
-/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK3*/
-#define EFUSE_BLK3_DIN2  0xFFFFFFFF
-#define EFUSE_BLK3_DIN2_M  ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S))
-#define EFUSE_BLK3_DIN2_V  0xFFFFFFFF
-#define EFUSE_BLK3_DIN2_S  0
-
-/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration
- * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/
-#define EFUSE_BLK3_WDATA3_REG          (DR_REG_EFUSE_BASE + 0x0e4)
-/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK3*/
-#define EFUSE_BLK3_DIN3  0xFFFFFFFF
-#define EFUSE_BLK3_DIN3_M  ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S))
-#define EFUSE_BLK3_DIN3_V  0xFFFFFFFF
-#define EFUSE_BLK3_DIN3_S  0
-/* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */
-/*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
-#define EFUSE_ADC2_TP_HIGH  0x1FF
-#define EFUSE_ADC2_TP_HIGH_M  ((EFUSE_ADC2_TP_HIGH_V)<<(EFUSE_ADC2_TP_HIGH_S))
-#define EFUSE_ADC2_TP_HIGH_V  0x1FF
-#define EFUSE_ADC2_TP_HIGH_S  23
-/* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */
-/*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
-#define EFUSE_ADC2_TP_LOW  0x7F
-#define EFUSE_ADC2_TP_LOW_M  ((EFUSE_ADC2_TP_LOW_V)<<(EFUSE_ADC2_TP_LOW_S))
-#define EFUSE_ADC2_TP_LOW_V  0x7F
-#define EFUSE_ADC2_TP_LOW_S  16
-/* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */
-/*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
-#define EFUSE_ADC1_TP_HIGH  0x1FF
-#define EFUSE_ADC1_TP_HIGH_M  ((EFUSE_ADC1_TP_HIGH_V)<<(EFUSE_ADC1_TP_HIGH_S))
-#define EFUSE_ADC1_TP_HIGH_V  0x1FF
-#define EFUSE_ADC1_TP_HIGH_S  7
-/* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
-/*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */
-#define EFUSE_ADC1_TP_LOW  0x7F
-#define EFUSE_ADC1_TP_LOW_M  ((EFUSE_ADC1_TP_LOW_V)<<(EFUSE_ADC1_TP_LOW_S))
-#define EFUSE_ADC1_TP_LOW_V  0x7F
-#define EFUSE_ADC1_TP_LOW_S  0
-
-#define EFUSE_BLK3_WDATA4_REG          (DR_REG_EFUSE_BASE + 0x0e8)
-/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK3*/
-#define EFUSE_BLK3_DIN4  0xFFFFFFFF
-#define EFUSE_BLK3_DIN4_M  ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S))
-#define EFUSE_BLK3_DIN4_V  0xFFFFFFFF
-#define EFUSE_BLK3_DIN4_S  0
-/* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */
-/*description: Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE */
-#define EFUSE_CAL_RESERVED  0x0000FFFF
-#define EFUSE_CAL_RESERVED_M  ((EFUSE_CAL_RESERVED_V)<<(EFUSE_CAL_RESERVED_S))
-#define EFUSE_CAL_RESERVED_V  0xFFFF
-#define EFUSE_CAL_RESERVED_S  0
-
-#define EFUSE_BLK3_WDATA5_REG          (DR_REG_EFUSE_BASE + 0x0ec)
-/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK3*/
-#define EFUSE_BLK3_DIN5  0xFFFFFFFF
-#define EFUSE_BLK3_DIN5_M  ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S))
-#define EFUSE_BLK3_DIN5_V  0xFFFFFFFF
-#define EFUSE_BLK3_DIN5_S  0
-
-#define EFUSE_BLK3_WDATA6_REG          (DR_REG_EFUSE_BASE + 0x0f0)
-/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK3*/
-#define EFUSE_BLK3_DIN6  0xFFFFFFFF
-#define EFUSE_BLK3_DIN6_M  ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S))
-#define EFUSE_BLK3_DIN6_V  0xFFFFFFFF
-#define EFUSE_BLK3_DIN6_S  0
-
-#define EFUSE_BLK3_WDATA7_REG          (DR_REG_EFUSE_BASE + 0x0f4)
-/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: program for BLOCK3*/
-#define EFUSE_BLK3_DIN7  0xFFFFFFFF
-#define EFUSE_BLK3_DIN7_M  ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S))
-#define EFUSE_BLK3_DIN7_V  0xFFFFFFFF
-#define EFUSE_BLK3_DIN7_S  0
-
-#define EFUSE_CLK_REG          (DR_REG_EFUSE_BASE + 0x0f8)
-/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_CLK_EN  (BIT(16))
-#define EFUSE_CLK_EN_M  (BIT(16))
-#define EFUSE_CLK_EN_V  0x1
-#define EFUSE_CLK_EN_S  16
-/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */
-/*description: efuse timing configure*/
-#define EFUSE_CLK_SEL1  0x000000FF
-#define EFUSE_CLK_SEL1_M  ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S))
-#define EFUSE_CLK_SEL1_V  0xFF
-#define EFUSE_CLK_SEL1_S  8
-/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */
-/*description: efuse timing configure*/
-#define EFUSE_CLK_SEL0  0x000000FF
-#define EFUSE_CLK_SEL0_M  ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S))
-#define EFUSE_CLK_SEL0_V  0xFF
-#define EFUSE_CLK_SEL0_S  0
-
-#define EFUSE_CONF_REG          (DR_REG_EFUSE_BASE + 0x0fc)
-/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: */
-#define EFUSE_FORCE_NO_WR_RD_DIS  (BIT(16))
-#define EFUSE_FORCE_NO_WR_RD_DIS_M  (BIT(16))
-#define EFUSE_FORCE_NO_WR_RD_DIS_V  0x1
-#define EFUSE_FORCE_NO_WR_RD_DIS_S  16
-/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: efuse operation code*/
-#define EFUSE_OP_CODE  0x0000FFFF
-#define EFUSE_OP_CODE_M  ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
-#define EFUSE_OP_CODE_V  0xFFFF
-#define EFUSE_OP_CODE_S  0
-
-#define EFUSE_STATUS_REG          (DR_REG_EFUSE_BASE + 0x100)
-/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define EFUSE_DEBUG  0xFFFFFFFF
-#define EFUSE_DEBUG_M  ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S))
-#define EFUSE_DEBUG_V  0xFFFFFFFF
-#define EFUSE_DEBUG_S  0
-
-#define EFUSE_CMD_REG          (DR_REG_EFUSE_BASE + 0x104)
-/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: command for program*/
-#define EFUSE_PGM_CMD  (BIT(1))
-#define EFUSE_PGM_CMD_M  (BIT(1))
-#define EFUSE_PGM_CMD_V  0x1
-#define EFUSE_PGM_CMD_S  1
-/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: command for read*/
-#define EFUSE_READ_CMD  (BIT(0))
-#define EFUSE_READ_CMD_M  (BIT(0))
-#define EFUSE_READ_CMD_V  0x1
-#define EFUSE_READ_CMD_S  0
-
-#define EFUSE_INT_RAW_REG          (DR_REG_EFUSE_BASE + 0x108)
-/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program done interrupt raw status*/
-#define EFUSE_PGM_DONE_INT_RAW  (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_V  0x1
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: read done interrupt raw status*/
-#define EFUSE_READ_DONE_INT_RAW  (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_V  0x1
-#define EFUSE_READ_DONE_INT_RAW_S  0
-
-#define EFUSE_INT_ST_REG          (DR_REG_EFUSE_BASE + 0x10c)
-/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program done interrupt status*/
-#define EFUSE_PGM_DONE_INT_ST  (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_V  0x1
-#define EFUSE_PGM_DONE_INT_ST_S  1
-/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: read done interrupt status*/
-#define EFUSE_READ_DONE_INT_ST  (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_V  0x1
-#define EFUSE_READ_DONE_INT_ST_S  0
-
-#define EFUSE_INT_ENA_REG          (DR_REG_EFUSE_BASE + 0x110)
-/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program done interrupt enable*/
-#define EFUSE_PGM_DONE_INT_ENA  (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_V  0x1
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: read done interrupt enable*/
-#define EFUSE_READ_DONE_INT_ENA  (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_V  0x1
-#define EFUSE_READ_DONE_INT_ENA_S  0
-
-#define EFUSE_INT_CLR_REG          (DR_REG_EFUSE_BASE + 0x114)
-/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program done interrupt clear*/
-#define EFUSE_PGM_DONE_INT_CLR  (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_V  0x1
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: read done interrupt clear*/
-#define EFUSE_READ_DONE_INT_CLR  (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_V  0x1
-#define EFUSE_READ_DONE_INT_CLR_S  0
-
-#define EFUSE_DAC_CONF_REG          (DR_REG_EFUSE_BASE + 0x118)
-/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define EFUSE_DAC_CLK_PAD_SEL  (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x1
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */
-/*description: efuse timing configure*/
-#define EFUSE_DAC_CLK_DIV  0x000000FF
-#define EFUSE_DAC_CLK_DIV_M  ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
-#define EFUSE_DAC_CLK_DIV_V  0xFF
-#define EFUSE_DAC_CLK_DIV_S  0
-
-#define EFUSE_DEC_STATUS_REG          (DR_REG_EFUSE_BASE + 0x11c)
-/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */
-/*description: the decode result of 3/4 coding scheme has warning*/
-#define EFUSE_DEC_WARNINGS  0x00000FFF
-#define EFUSE_DEC_WARNINGS_M  ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S))
-#define EFUSE_DEC_WARNINGS_V  0xFFF
-#define EFUSE_DEC_WARNINGS_S  0
-
-#define EFUSE_DATE_REG          (DR_REG_EFUSE_BASE + 0x1FC)
-/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */
-/*description: */
-#define EFUSE_DATE  0xFFFFFFFF
-#define EFUSE_DATE_M  ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
-#define EFUSE_DATE_V  0xFFFFFFFF
-#define EFUSE_DATE_S  0
-
-
-
-
-#endif /*_SOC_EFUSE_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/emac_ex_reg.h b/tools/sdk/include/soc/soc/emac_ex_reg.h
deleted file mode 100644
index e43217e0833..00000000000
--- a/tools/sdk/include/soc/soc/emac_ex_reg.h
+++ /dev/null
@@ -1,161 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _EMAC_EX_H_
-#define _EMAC_EX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "soc.h"
-#define REG_EMAC_EX_BASE (DR_REG_EMAC_BASE + 0x800)
-
-#define EMAC_EX_CLKOUT_CONF_REG (REG_EMAC_EX_BASE + 0x0000)
-#define EMAC_EX_CLK_OUT_DLY_NUM 0x00000003
-#define EMAC_EX_CLK_OUT_DLY_NUM_M (EMAC_EX_CLK_OUT_DLY_NUM_V << EMAC_EX_CLK_OUT_DLY_NUM_S)
-#define EMAC_EX_CLK_OUT_DLY_NUM_V 0x00000003
-#define EMAC_EX_CLK_OUT_DLY_NUM_S 8
-#define EMAC_EX_CLK_OUT_H_DIV_NUM 0x0000000F
-#define EMAC_EX_CLK_OUT_H_DIV_NUM_M (EMAC_EX_CLK_OUT_H_DIV_NUM_V << EMAC_EX_CLK_OUT_H_DIV_NUM_S)
-#define EMAC_EX_CLK_OUT_H_DIV_NUM_V 0x0000000F
-#define EMAC_EX_CLK_OUT_H_DIV_NUM_S 4
-#define EMAC_EX_CLK_OUT_DIV_NUM 0x0000000F
-#define EMAC_EX_CLK_OUT_DIV_NUM_M (EMAC_EX_CLK_OUT_DIV_NUM_V << EMAC_EX_CLK_OUT_DIV_NUM_S)
-#define EMAC_EX_CLK_OUT_DIV_NUM_V 0x0000000F
-#define EMAC_EX_CLK_OUT_DIV_NUM_S 0
-
-#define EMAC_EX_OSCCLK_CONF_REG (REG_EMAC_EX_BASE + 0x0004)
-#define EMAC_EX_OSC_CLK_SEL (BIT(24))
-#define EMAC_EX_OSC_CLK_SEL_M (BIT(24))
-#define EMAC_EX_OSC_CLK_SEL_V 1
-#define EMAC_EX_OSC_CLK_SEL_S 24
-#define EMAC_EX_OSC_H_DIV_NUM_100M 0x0000003F
-#define EMAC_EX_OSC_H_DIV_NUM_100M_M (EMAC_EX_OSC_H_DIV_NUM_100M_V << EMAC_EX_OSC_H_DIV_NUM_100M_S)
-#define EMAC_EX_OSC_H_DIV_NUM_100M_V 0x0000003F
-#define EMAC_EX_OSC_H_DIV_NUM_100M_S 18
-#define EMAC_EX_OSC_DIV_NUM_100M 0x0000003F
-#define EMAC_EX_OSC_DIV_NUM_100M_M (EMAC_EX_OSC_DIV_NUM_100M_V << EMAC_EX_OSC_DIV_NUM_100M_S)
-#define EMAC_EX_OSC_DIV_NUM_100M_V 0x0000003F
-#define EMAC_EX_OSC_DIV_NUM_100M_S 12
-#define EMAC_EX_OSC_H_DIV_NUM_10M 0x0000003F
-#define EMAC_EX_OSC_H_DIV_NUM_10M_M (EMAC_EX_OSC_H_DIV_NUM_10M_V << EMAC_EX_OSC_H_DIV_NUM_10M_S)
-#define EMAC_EX_OSC_H_DIV_NUM_10M_V 0x0000003F
-#define EMAC_EX_OSC_H_DIV_NUM_10M_S 6
-#define EMAC_EX_OSC_DIV_NUM_10M 0x0000003F
-#define EMAC_EX_OSC_DIV_NUM_10M_M (EMAC_EX_OSC_DIV_NUM_10M_V << EMAC_EX_OSC_DIV_NUM_10M_S)
-#define EMAC_EX_OSC_DIV_NUM_10M_V 0x0000003F
-#define EMAC_EX_OSC_DIV_NUM_10M_S 0
-
-#define EMAC_EX_CLK_CTRL_REG (REG_EMAC_EX_BASE + 0x0008)
-#define EMAC_EX_CLK_EN (BIT(5))
-#define EMAC_EX_CLK_EN_M (BIT(5))
-#define EMAC_EX_CLK_EN_V 1
-#define EMAC_EX_CLK_EN_S 5
-#define EMAC_EX_MII_CLK_RX_EN (BIT(4))
-#define EMAC_EX_MII_CLK_RX_EN_M (BIT(4))
-#define EMAC_EX_MII_CLK_RX_EN_V 1
-#define EMAC_EX_MII_CLK_RX_EN_S 4
-#define EMAC_EX_MII_CLK_TX_EN (BIT(3))
-#define EMAC_EX_MII_CLK_TX_EN_M (BIT(3))
-#define EMAC_EX_MII_CLK_TX_EN_V 1
-#define EMAC_EX_MII_CLK_TX_EN_S 3
-#define EMAC_EX_RX_125_CLK_EN (BIT(2))
-#define EMAC_EX_RX_125_CLK_EN_M (BIT(2))
-#define EMAC_EX_RX_125_CLK_EN_V 1
-#define EMAC_EX_RX_125_CLK_EN_S 2
-#define EMAC_EX_INT_OSC_EN (BIT(1))
-#define EMAC_EX_INT_OSC_EN_M (BIT(1))
-#define EMAC_EX_INT_OSC_EN_V 1
-#define EMAC_EX_INT_OSC_EN_S 1
-#define EMAC_EX_EXT_OSC_EN (BIT(0))
-#define EMAC_EX_EXT_OSC_EN_M (BIT(0))
-#define EMAC_EX_EXT_OSC_EN_V 1
-#define EMAC_EX_EXT_OSC_EN_S 0
-
-#define EMAC_EX_PHYINF_CONF_REG (REG_EMAC_EX_BASE + 0x000c)
-#define EMAC_EX_TX_ERR_OUT_EN (BIT(20))
-#define EMAC_EX_TX_ERR_OUT_EN_M (BIT(20))
-#define EMAC_EX_TX_ERR_OUT_EN_V 1
-#define EMAC_EX_TX_ERR_OUT_EN_S 20
-#define EMAC_EX_SCR_SMI_DLY_RX_SYNC (BIT(19))
-#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_M (BIT(19))
-#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_V 1
-#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_S 19
-#define EMAC_EX_PMT_CTRL_EN (BIT(18))
-#define EMAC_EX_PMT_CTRL_EN_M (BIT(18))
-#define EMAC_EX_PMT_CTRL_EN_V 1
-#define EMAC_EX_PMT_CTRL_EN_S 18
-#define EMAC_EX_SBD_CLK_GATING_EN (BIT(17))
-#define EMAC_EX_SBD_CLK_GATING_EN_M (BIT(17))
-#define EMAC_EX_SBD_CLK_GATING_EN_V 1
-#define EMAC_EX_SBD_CLK_GATING_EN_S 17
-#define EMAC_EX_SS_MODE (BIT(16))
-#define EMAC_EX_SS_MODE_M (BIT(16))
-#define EMAC_EX_SS_MODE_V 1
-#define EMAC_EX_SS_MODE_S 16
-#define EMAC_EX_PHY_INTF_SEL 0x00000007
-#define EMAC_EX_PHY_INTF_SEL_M (EMAC_EX_PHY_INTF_SEL_V << EMAC_EX_PHY_INTF_SEL_S)
-#define EMAC_EX_PHY_INTF_SEL_V 0x00000007
-#define EMAC_EX_PHY_INTF_SEL_S 13
-#define EMAC_EX_REVMII_PHY_ADDR 0x0000001F
-#define EMAC_EX_REVMII_PHY_ADDR_M (EMAC_EX_REVMII_PHY_ADDR_V << EMAC_EX_REVMII_PHY_ADDR_S)
-#define EMAC_EX_REVMII_PHY_ADDR_V 0x0000001F
-#define EMAC_EX_REVMII_PHY_ADDR_S 8
-#define EMAC_EX_CORE_PHY_ADDR 0x0000001F
-#define EMAC_EX_CORE_PHY_ADDR_M (EMAC_EX_CORE_PHY_ADDR_V << EMAC_EX_CORE_PHY_ADDR_S)
-#define EMAC_EX_CORE_PHY_ADDR_V 0x0000001F
-#define EMAC_EX_CORE_PHY_ADDR_S 3
-#define EMAC_EX_SBD_FLOWCTRL (BIT(2))
-#define EMAC_EX_SBD_FLOWCTRL_M (BIT(2))
-#define EMAC_EX_SBD_FLOWCTRL_V 1
-#define EMAC_EX_SBD_FLOWCTRL_S 2
-#define EMAC_EX_EXT_REVMII_RX_CLK_SEL (BIT(1))
-#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_M (BIT(1))
-#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_V 1
-#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_S 1
-#define EMAC_EX_INT_REVMII_RX_CLK_SEL (BIT(0))
-#define EMAC_EX_INT_REVMII_RX_CLK_SEL_M (BIT(0))
-#define EMAC_EX_INT_REVMII_RX_CLK_SEL_V 1
-#define EMAC_EX_INT_REVMII_RX_CLK_SEL_S 0
-
-#define EMAC_EX_PHY_INTF_RMII  4
-
-#define EMAC_EX_EMAC_PD_SEL_REG (REG_EMAC_EX_BASE + 0x0010)
-#define EMAC_EX_RAM_PD_EN 0x00000003
-#define EMAC_EX_RAM_PD_EN_M (EMAC_EX_RAM_PD_EN_V << EMAC_EX_RAM_PD_EN_S)
-#define EMAC_EX_RAM_PD_EN_V 0x00000003
-#define EMAC_EX_RAM_PD_EN_S 0
-
-#define EMAC_EX_DATE_REG (REG_EMAC_EX_BASE + 0x00fc)
-#define EMAC_EX_DATE 0xFFFFFFFF
-#define EMAC_EX_DATE_M (EMAC_EX_DATE_V << EMAC_EX_DATE_S)
-#define EMAC_EX_DATE_V 0xFFFFFFFF
-#define EMAC_EX_DATE_S 0
-#define EMAC_EX_DATE_VERSION 0x16042200
-#define EMAC_EX_DATE_VERSION_M (EMAC_EX_DATE_VERSION_V << EMAC_EX_DATE_VERSION_S)
-#define EMAC_EX_DATE_VERSION_V 0x16042200
-
-#define EMAC_CLK_EN_REG 0x3ff000cc
-#define EMAC_CLK_EN_REG_M (EMAC_CLK_EN_REG_V << EMAC_CLK_EN_REG_S)
-#define EMAC_CLK_EN_REG_V 0x3ff000cc
-#define EMAC_CLK_EN (BIT(14))
-#define EMAC_CLK_EN_M (BIT(14))
-#define EMAC_CLK_EN_V 1
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/tools/sdk/include/soc/soc/emac_reg_v2.h b/tools/sdk/include/soc/soc/emac_reg_v2.h
deleted file mode 100644
index 72af5bfe365..00000000000
--- a/tools/sdk/include/soc/soc/emac_reg_v2.h
+++ /dev/null
@@ -1,1460 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_EMAC_REG_H_
-#define _SOC_EMAC_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define EMAC_DMABUSMODE_REG          (DR_REG_EMAC_BASE + 0x0000)
-/* EMAC_DMAMIXEDBURST : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: When this bit is set high and the FIXED_BURST bit is low  the
- AHB master interface starts all bursts of a length more than 16 with INCR (undefined burst)  whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less.*/
-#define EMAC_DMAMIXEDBURST  (BIT(26))
-#define EMAC_DMAMIXEDBURST_M  (BIT(26))
-#define EMAC_DMAMIXEDBURST_V  0x1
-#define EMAC_DMAMIXEDBURST_S  26
-/* EMAC_DMAADDRALIBEA : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: When this bit is set high and the FIXED_BURST bit is 1  the AHB
- interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0  the first burst (accessing the start address of data buffer) is not aligned  but subsequent bursts are aligned to the address.*/
-#define EMAC_DMAADDRALIBEA  (BIT(25))
-#define EMAC_DMAADDRALIBEA_M  (BIT(25))
-#define EMAC_DMAADDRALIBEA_V  0x1
-#define EMAC_DMAADDRALIBEA_S  25
-/* EMAC_PBLX8_MODE : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: When set high  this bit multiplies the programmed PBL value (Bits[22:17]
- and Bits[13:8]) eight times. Therefore  the DMA transfers the data in 8  16  32  64  128  and 256 beats depending on the PBL value.*/
-#define EMAC_PBLX8_MODE  (BIT(24))
-#define EMAC_PBLX8_MODE_M  (BIT(24))
-#define EMAC_PBLX8_MODE_V  0x1
-#define EMAC_PBLX8_MODE_S  24
-/* EMAC_USE_SEP_PBL : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: When set high  this bit configures the Rx DMA to use the value
- configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When reset to low  the PBL value in Bits[13:8] is applicable for both DMA engines.*/
-#define EMAC_USE_SEP_PBL  (BIT(23))
-#define EMAC_USE_SEP_PBL_M  (BIT(23))
-#define EMAC_USE_SEP_PBL_V  0x1
-#define EMAC_USE_SEP_PBL_S  23
-/* EMAC_RX_DMA_PBL : R/W ;bitpos:[22:17] ;default: 6'h1 ; */
-/*description: This field indicates the maximum number of beats to be transferred
- in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst transfer on the host bus. You can program RPBL with values of 1  2  4  8  16  and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is set high.*/
-#define EMAC_RX_DMA_PBL  0x0000003F
-#define EMAC_RX_DMA_PBL_M  ((EMAC_RX_DMA_PBL_V)<<(EMAC_RX_DMA_PBL_S))
-#define EMAC_RX_DMA_PBL_V  0x3F
-#define EMAC_RX_DMA_PBL_S  17
-/* EMAC_FIXED_BURST : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: This bit controls whether the AHB master interface performs fixed
- burst transfers or not. When set  the AHB interface uses only SINGLE  INCR4  INCR8  or INCR16 during start of the normal burst transfers. When reset  the AHB interface uses SINGLE and INCR burst transfer Operations.*/
-#define EMAC_FIXED_BURST  (BIT(16))
-#define EMAC_FIXED_BURST_M  (BIT(16))
-#define EMAC_FIXED_BURST_V  0x1
-#define EMAC_FIXED_BURST_S  16
-/* EMAC_PRI_RATIO : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: These bits control the priority ratio in the weighted round-robin
- arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit:  2'b00 -- 1: 1    2'b01 -- 2: 0    2'b10 -- 3: 1    2'b11 -- 4: 1*/
-#define EMAC_PRI_RATIO  0x00000003
-#define EMAC_PRI_RATIO_M  ((EMAC_PRI_RATIO_V)<<(EMAC_PRI_RATIO_S))
-#define EMAC_PRI_RATIO_V  0x3
-#define EMAC_PRI_RATIO_S  14
-/* EMAC_PROG_BURST_LEN : R/W ;bitpos:[13:8] ;default: 6'h1 ; */
-/*description: These bits indicate the maximum number of beats to be transferred
- in one DMA transaction. If the number of beats to be transferred is more than 32  then perform the following steps: 1. Set the PBLx8 mode  2. Set the PBL(PROG_BURST_LEN).*/
-#define EMAC_PROG_BURST_LEN  0x0000003F
-#define EMAC_PROG_BURST_LEN_M  ((EMAC_PROG_BURST_LEN_V)<<(EMAC_PROG_BURST_LEN_S))
-#define EMAC_PROG_BURST_LEN_V  0x3F
-#define EMAC_PROG_BURST_LEN_S  8
-/* EMAC_ALT_DESC_SIZE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: When set  the size of the alternate descriptor increases to 32 bytes.*/
-#define EMAC_ALT_DESC_SIZE  (BIT(7))
-#define EMAC_ALT_DESC_SIZE_M  (BIT(7))
-#define EMAC_ALT_DESC_SIZE_V  0x1
-#define EMAC_ALT_DESC_SIZE_S  7
-/* EMAC_DESC_SKIP_LEN : R/W ;bitpos:[6:2] ;default: 5'h0 ; */
-/*description: This bit specifies the number of Word to skip between two unchained
- descriptors.The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_LEN) value is equal to zero  the descriptor table is taken as contiguous by the DMA in Ring mode.*/
-#define EMAC_DESC_SKIP_LEN  0x0000001F
-#define EMAC_DESC_SKIP_LEN_M  ((EMAC_DESC_SKIP_LEN_V)<<(EMAC_DESC_SKIP_LEN_S))
-#define EMAC_DESC_SKIP_LEN_V  0x1F
-#define EMAC_DESC_SKIP_LEN_S  2
-/* EMAC_DMA_ARB_SCH : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: This bit specifies the arbitration scheme between the transmit
- and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX  priority specified in PR (bit[15:14]). 1'b1 Fixed priority (Rx priority to Tx).*/
-#define EMAC_DMA_ARB_SCH  (BIT(1))
-#define EMAC_DMA_ARB_SCH_M  (BIT(1))
-#define EMAC_DMA_ARB_SCH_V  0x1
-#define EMAC_DMA_ARB_SCH_S  1
-/* EMAC_SW_RST : R_WS_SC ;bitpos:[0] ;default: 1'h1 ; */
-/*description: When this bit is set  the MAC DMA Controller resets the logic
- and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC  you should read a zero (0) value in this bit.*/
-#define EMAC_SW_RST  (BIT(0))
-#define EMAC_SW_RST_M  (BIT(0))
-#define EMAC_SW_RST_V  0x1
-#define EMAC_SW_RST_S  0
-
-#define EMAC_DMATXPOLLDEMAND_REG          (DR_REG_EMAC_BASE + 0x0004)
-/* EMAC_TRANS_POLL_DEMAND : RO_WT ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: When these bits are written with any value  the DMA reads the
- current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host)  the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available  the transmission resumes.*/
-#define EMAC_TRANS_POLL_DEMAND  0xFFFFFFFF
-#define EMAC_TRANS_POLL_DEMAND_M  ((EMAC_TRANS_POLL_DEMAND_V)<<(EMAC_TRANS_POLL_DEMAND_S))
-#define EMAC_TRANS_POLL_DEMAND_V  0xFFFFFFFF
-#define EMAC_TRANS_POLL_DEMAND_S  0
-
-#define EMAC_DMARXPOLLDEMAND_REG          (DR_REG_EMAC_BASE + 0x0008)
-/* EMAC_RECV_POLL_DEMAND : RO_WT ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: When these bits are written with any value  the DMA reads the
- current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host)  the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available  the Rx DMA returns to the active state.*/
-#define EMAC_RECV_POLL_DEMAND  0xFFFFFFFF
-#define EMAC_RECV_POLL_DEMAND_M  ((EMAC_RECV_POLL_DEMAND_V)<<(EMAC_RECV_POLL_DEMAND_S))
-#define EMAC_RECV_POLL_DEMAND_V  0xFFFFFFFF
-#define EMAC_RECV_POLL_DEMAND_S  0
-
-#define EMAC_DMARXBASEADDR_REG          (DR_REG_EMAC_BASE + 0x000C)
-/* EMAC_START_RECV_LIST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This field contains the base address of the first descriptor
- in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.*/
-#define EMAC_START_RECV_LIST  0xFFFFFFFF
-#define EMAC_START_RECV_LIST_M  ((EMAC_START_RECV_LIST_V)<<(EMAC_START_RECV_LIST_S))
-#define EMAC_START_RECV_LIST_V  0xFFFFFFFF
-#define EMAC_START_RECV_LIST_S  0
-
-#define EMAC_DMATXBASEADDR_REG          (DR_REG_EMAC_BASE + 0x0010)
-/* EMAC_START_TRANS_LIST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This field contains the base address of the first descriptor
- in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore  these LSB bits are read-only.*/
-#define EMAC_START_TRANS_LIST  0xFFFFFFFF
-#define EMAC_START_TRANS_LIST_M  ((EMAC_START_TRANS_LIST_V)<<(EMAC_START_TRANS_LIST_S))
-#define EMAC_START_TRANS_LIST_V  0xFFFFFFFF
-#define EMAC_START_TRANS_LIST_S  0
-
-#define EMAC_DMASTATUS_REG          (DR_REG_EMAC_BASE + 0x0014)
-/* EMAC_TS_TRI_INT : RO ;bitpos:[29] ;default: 1'h0 ; */
-/*description: This bit indicates an interrupt event in the Timestamp Generator
- block of the ETH_MAC.The software must read the corresponding registers in the ETH_MAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0.*/
-#define EMAC_TS_TRI_INT  (BIT(29))
-#define EMAC_TS_TRI_INT_M  (BIT(29))
-#define EMAC_TS_TRI_INT_V  0x1
-#define EMAC_TS_TRI_INT_S  29
-/* EMAC_PMT_INT : RO ;bitpos:[28] ;default: 1'h0 ; */
-/*description: This bit indicates an interrupt event in the PMT module of the
- ETH_MAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0.*/
-#define EMAC_PMT_INT  (BIT(28))
-#define EMAC_PMT_INT_M  (BIT(28))
-#define EMAC_PMT_INT_V  0x1
-#define EMAC_PMT_INT_S  28
-/* EMAC_ERROR_BITS : RO ;bitpos:[25:23] ;default: 3'h0 ; */
-/*description: This field indicates the type of error that caused a Bus Error
-  for example  error response on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate an interrupt.  3'b000: Error during Rx DMA Write Data Transfer.  3'b011: Error during Tx DMA Read Data Transfer.  3'b100: Error during Rx DMA Descriptor Write Access.  3'b101: Error during Tx DMA Descriptor Write Access.  3'b110: Error during Rx DMA Descriptor Read Access.  3'b111: Error during Tx DMA Descriptor Read Access.*/
-#define EMAC_ERROR_BITS  0x00000007
-#define EMAC_ERROR_BITS_M  ((EMAC_ERROR_BITS_V)<<(EMAC_ERROR_BITS_S))
-#define EMAC_ERROR_BITS_V  0x7
-#define EMAC_ERROR_BITS_S  23
-/* EMAC_TRANS_PROC_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
-/*description: This field indicates the Transmit DMA FSM state. This field does
- not generate an interrupt.  3'b000: Stopped. Reset or Stop Transmit Command issued.  3'b001: Running. Fetching Transmit Transfer Descriptor.  3'b010: Reserved for future use.  3'b011: Running. Waiting for TX packets.  3'b100: Suspended. Receive Descriptor Unavailable.  3'b101: Running. Closing Transmit Descriptor.  3'b110: TIME_STAMP write state.  3'b111: Running. Transferring the TX packets data from transmit buffer to host memory.*/
-#define EMAC_TRANS_PROC_STATE  0x00000007
-#define EMAC_TRANS_PROC_STATE_M  ((EMAC_TRANS_PROC_STATE_V)<<(EMAC_TRANS_PROC_STATE_S))
-#define EMAC_TRANS_PROC_STATE_V  0x7
-#define EMAC_TRANS_PROC_STATE_S  20
-/* EMAC_RECV_PROC_STATE : RO ;bitpos:[19:17] ;default: 3'h0 ; */
-/*description: This field indicates the Receive DMA FSM state. This field does
- not generate an interrupt.  3'b000: Stopped. Reset or Stop Receive Command issued.  3'b001: Running. Fetching Receive Transfer Descriptor.  3'b010: Reserved for future use.  3'b011: Running. Waiting for RX packets.  3'b100: Suspended. Receive Descriptor Unavailable.  3'b101: Running. Closing Receive Descriptor.  3'b110: TIME_STAMP write state.  3'b111: Running. Transferring the TX packets data from receive buffer to host memory.*/
-#define EMAC_RECV_PROC_STATE  0x00000007
-#define EMAC_RECV_PROC_STATE_M  ((EMAC_RECV_PROC_STATE_V)<<(EMAC_RECV_PROC_STATE_S))
-#define EMAC_RECV_PROC_STATE_V  0x7
-#define EMAC_RECV_PROC_STATE_S  17
-/* EMAC_NORM_INT_SUMM : R_SS_WC ;bitpos:[16] ;default: 1'h0 ; */
-/*description: Normal Interrupt Summary bit value is the logical OR of the following
- bits when the corresponding interrupt bits are enabled in Interrupt Enable Register:  Bit[0]: Transmit Interrupt.  Bit[2]: Transmit Buffer Unavailable.  Bit[6]: Receive Interrupt.  Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set  is cleared.*/
-#define EMAC_NORM_INT_SUMM  (BIT(16))
-#define EMAC_NORM_INT_SUMM_M  (BIT(16))
-#define EMAC_NORM_INT_SUMM_V  0x1
-#define EMAC_NORM_INT_SUMM_S  16
-/* EMAC_ABN_INT_SUMM : R_SS_WC ;bitpos:[15] ;default: 1'h0 ; */
-/*description: Abnormal Interrupt Summary bit value is the logical OR of the
- following when the corresponding interrupt bits are enabled in Interrupt Enable Register:   Bit[1]: Transmit Process Stopped.  Bit[3]: Transmit Jabber Timeout.  Bit[4]: Receive FIFO Overflow.  Bit[5]: Transmit Underflow.  Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped.  Bit[9]: Receive Watchdog Timeout.  Bit[10]: Early Transmit Interrupt.  Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes AIS to be set  is cleared.*/
-#define EMAC_ABN_INT_SUMM  (BIT(15))
-#define EMAC_ABN_INT_SUMM_M  (BIT(15))
-#define EMAC_ABN_INT_SUMM_V  0x1
-#define EMAC_ABN_INT_SUMM_S  15
-/* EMAC_EARLY_RECV_INT : R_SS_WC ;bitpos:[14] ;default: 1'h0 ; */
-/*description: This bit indicates that the DMA filled the first data buffer
- of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever occurs earlier).*/
-#define EMAC_EARLY_RECV_INT  (BIT(14))
-#define EMAC_EARLY_RECV_INT_M  (BIT(14))
-#define EMAC_EARLY_RECV_INT_V  0x1
-#define EMAC_EARLY_RECV_INT_S  14
-/* EMAC_FATAL_BUS_ERR_INT : R_SS_WC ;bitpos:[13] ;default: 1'h0 ; */
-/*description: This bit indicates that a bus error occurred  as described in
- Bits [25:23]. When this bit is set  the corresponding DMA engine disables all of its bus accesses.*/
-#define EMAC_FATAL_BUS_ERR_INT  (BIT(13))
-#define EMAC_FATAL_BUS_ERR_INT_M  (BIT(13))
-#define EMAC_FATAL_BUS_ERR_INT_V  0x1
-#define EMAC_FATAL_BUS_ERR_INT_S  13
-/* EMAC_EARLY_TRANS_INT : R_SS_WC ;bitpos:[10] ;default: 1'h0 ; */
-/*description: This bit indicates that the frame to be transmitted is fully
- transferred to the MTL Transmit FIFO.*/
-#define EMAC_EARLY_TRANS_INT  (BIT(10))
-#define EMAC_EARLY_TRANS_INT_M  (BIT(10))
-#define EMAC_EARLY_TRANS_INT_V  0x1
-#define EMAC_EARLY_TRANS_INT_S  10
-/* EMAC_RECV_WDT_TO : R_SS_WC ;bitpos:[9] ;default: 1'h0 ; */
-/*description: When set  this bit indicates that the Receive Watchdog Timer
- expired while receiving the current frame and the current frame is truncated after the watchdog timeout.*/
-#define EMAC_RECV_WDT_TO  (BIT(9))
-#define EMAC_RECV_WDT_TO_M  (BIT(9))
-#define EMAC_RECV_WDT_TO_V  0x1
-#define EMAC_RECV_WDT_TO_S  9
-/* EMAC_RECV_PROC_STOP : R_SS_WC ;bitpos:[8] ;default: 1'h0 ; */
-/*description: This bit is asserted when the Receive Process enters the Stopped state.*/
-#define EMAC_RECV_PROC_STOP  (BIT(8))
-#define EMAC_RECV_PROC_STOP_M  (BIT(8))
-#define EMAC_RECV_PROC_STOP_V  0x1
-#define EMAC_RECV_PROC_STOP_S  8
-/* EMAC_RECV_BUF_UNAVAIL : R_SS_WC ;bitpos:[7] ;default: 1'h0 ; */
-/*description: This bit indicates that the host owns the Next Descriptor in
- the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors  the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued  the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA.*/
-#define EMAC_RECV_BUF_UNAVAIL  (BIT(7))
-#define EMAC_RECV_BUF_UNAVAIL_M  (BIT(7))
-#define EMAC_RECV_BUF_UNAVAIL_V  0x1
-#define EMAC_RECV_BUF_UNAVAIL_S  7
-/* EMAC_RECV_INT : R_SS_WC ;bitpos:[6] ;default: 1'h0 ; */
-/*description: This bit indicates that the frame reception is complete. When
- reception is complete  the Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor  and the specific frame status information is updated in the descriptor. The reception remains in the Running state.*/
-#define EMAC_RECV_INT  (BIT(6))
-#define EMAC_RECV_INT_M  (BIT(6))
-#define EMAC_RECV_INT_V  0x1
-#define EMAC_RECV_INT_S  6
-/* EMAC_TRANS_UNDFLOW : R_SS_WC ;bitpos:[5] ;default: 1'h0 ; */
-/*description: This bit indicates that the Transmit Buffer had an Underflow
- during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.*/
-#define EMAC_TRANS_UNDFLOW  (BIT(5))
-#define EMAC_TRANS_UNDFLOW_M  (BIT(5))
-#define EMAC_TRANS_UNDFLOW_V  0x1
-#define EMAC_TRANS_UNDFLOW_S  5
-/* EMAC_RECV_OVFLOW : R_SS_WC ;bitpos:[4] ;default: 1'h0 ; */
-/*description: This bit indicates that the Receive Buffer had an Overflow during
- frame reception. If the partial frame is transferred to the application  the overflow status is set in RDES0[11].*/
-#define EMAC_RECV_OVFLOW  (BIT(4))
-#define EMAC_RECV_OVFLOW_M  (BIT(4))
-#define EMAC_RECV_OVFLOW_V  0x1
-#define EMAC_RECV_OVFLOW_S  4
-/* EMAC_TRANS_JABBER_TO : R_SS_WC ;bitpos:[3] ;default: 1'h0 ; */
-/*description: This bit indicates that the Transmit Jabber Timer expired  which
- happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs  the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.*/
-#define EMAC_TRANS_JABBER_TO  (BIT(3))
-#define EMAC_TRANS_JABBER_TO_M  (BIT(3))
-#define EMAC_TRANS_JABBER_TO_V  0x1
-#define EMAC_TRANS_JABBER_TO_S  3
-/* EMAC_TRANS_BUF_UNAVAIL : R_SS_WC ;bitpos:[2] ;default: 1'h0 ; */
-/*description: This bit indicates that the host owns the Next Descriptor in
- the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors  the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand Command.*/
-#define EMAC_TRANS_BUF_UNAVAIL  (BIT(2))
-#define EMAC_TRANS_BUF_UNAVAIL_M  (BIT(2))
-#define EMAC_TRANS_BUF_UNAVAIL_V  0x1
-#define EMAC_TRANS_BUF_UNAVAIL_S  2
-/* EMAC_TRANS_PROC_STOP : R_SS_WC ;bitpos:[1] ;default: 1'h0 ; */
-/*description: This bit is set when the transmission is stopped.*/
-#define EMAC_TRANS_PROC_STOP  (BIT(1))
-#define EMAC_TRANS_PROC_STOP_M  (BIT(1))
-#define EMAC_TRANS_PROC_STOP_V  0x1
-#define EMAC_TRANS_PROC_STOP_S  1
-/* EMAC_TRANS_INT : R_SS_WC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: This bit indicates that the frame transmission is complete. When
- transmission is complete  Bit[31] (OWN) of TDES0 is reset  and the specific frame status information is updated in the Descriptor.*/
-#define EMAC_TRANS_INT  (BIT(0))
-#define EMAC_TRANS_INT_M  (BIT(0))
-#define EMAC_TRANS_INT_V  0x1
-#define EMAC_TRANS_INT_S  0
-
-#define EMAC_DMAOPERATION_MODE_REG          (DR_REG_EMAC_BASE + 0x0018)
-/* EMAC_DIS_DROP_TCPIP_ERR_FRAM : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC does not drop the frames which
- only have errors detected by the Receive Checksum engine.When this bit is reset  all error frames are dropped if the Fwd_Err_Frame bit is reset.*/
-#define EMAC_DIS_DROP_TCPIP_ERR_FRAM  (BIT(26))
-#define EMAC_DIS_DROP_TCPIP_ERR_FRAM_M  (BIT(26))
-#define EMAC_DIS_DROP_TCPIP_ERR_FRAM_V  0x1
-#define EMAC_DIS_DROP_TCPIP_ERR_FRAM_S  26
-/* EMAC_RX_STORE_FORWARD : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: When this bit is set  the MTL reads a frame from the Rx FIFO
- only after the complete frame has been written to it.*/
-#define EMAC_RX_STORE_FORWARD  (BIT(25))
-#define EMAC_RX_STORE_FORWARD_M  (BIT(25))
-#define EMAC_RX_STORE_FORWARD_V  0x1
-#define EMAC_RX_STORE_FORWARD_S  25
-/* EMAC_DIS_FLUSH_RECV_FRAMES : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: When this bit is set  the Rx DMA does not flush any frames because
- of the unavailability of receive descriptors or buffers.*/
-#define EMAC_DIS_FLUSH_RECV_FRAMES  (BIT(24))
-#define EMAC_DIS_FLUSH_RECV_FRAMES_M  (BIT(24))
-#define EMAC_DIS_FLUSH_RECV_FRAMES_V  0x1
-#define EMAC_DIS_FLUSH_RECV_FRAMES_S  24
-/* EMAC_TX_STR_FWD : R/W ;bitpos:[21] ;default: 1'h0 ; */
-/*description: When this bit is set  transmission starts when a full frame resides
- in the MTL Transmit FIFO. When this bit is set  the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored.*/
-#define EMAC_TX_STR_FWD  (BIT(21))
-#define EMAC_TX_STR_FWD_M  (BIT(21))
-#define EMAC_TX_STR_FWD_V  0x1
-#define EMAC_TX_STR_FWD_S  21
-/* EMAC_FLUSH_TX_FIFO : R_WS_SC ;bitpos:[20] ;default: 1'h0 ; */
-/*description: When this bit is set  the transmit FIFO controller logic is reset
- to its default values  and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete.*/
-#define EMAC_FLUSH_TX_FIFO  (BIT(20))
-#define EMAC_FLUSH_TX_FIFO_M  (BIT(20))
-#define EMAC_FLUSH_TX_FIFO_V  0x1
-#define EMAC_FLUSH_TX_FIFO_S  20
-/* EMAC_TX_THRESH_CTRL : R/W ;bitpos:[16:14] ;default: 3'h0 ; */
-/*description: These bits control the threshold level of the MTL Transmit FIFO.
- Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition  full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3'b000: 64  3'b001: 128   3'b010: 192   3'b011: 256  3'b100: 40  3'b101: 32  3'b110: 24  3'b111: 16 .*/
-#define EMAC_TX_THRESH_CTRL  0x00000007
-#define EMAC_TX_THRESH_CTRL_M  ((EMAC_TX_THRESH_CTRL_V)<<(EMAC_TX_THRESH_CTRL_S))
-#define EMAC_TX_THRESH_CTRL_V  0x7
-#define EMAC_TX_THRESH_CTRL_S  14
-/* EMAC_START_STOP_TRANSMISSION_COMMAND : R/W ;bitpos:[13] ;default: 1'h0 ; */
-/*description: When this bit is set  transmission is placed in the Running state
-  and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset  the transmission process is placed in the Stopped state after completing the transmission of the current frame.*/
-#define EMAC_START_STOP_TRANSMISSION_COMMAND  (BIT(13))
-#define EMAC_START_STOP_TRANSMISSION_COMMAND_M  (BIT(13))
-#define EMAC_START_STOP_TRANSMISSION_COMMAND_V  0x1
-#define EMAC_START_STOP_TRANSMISSION_COMMAND_S  13
-/* EMAC_FWD_ERR_FRAME : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: When this bit is reset  the Rx FIFO drops frames with error status
- (CRC error collision error   giant frame  watchdog timeout  or overflow).*/
-#define EMAC_FWD_ERR_FRAME  (BIT(7))
-#define EMAC_FWD_ERR_FRAME_M  (BIT(7))
-#define EMAC_FWD_ERR_FRAME_V  0x1
-#define EMAC_FWD_ERR_FRAME_S  7
-/* EMAC_FWD_UNDER_GF : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: When set  the Rx FIFO forwards Undersized frames (that is  frames
- with no Error and length less than 64 bytes) including pad-bytes and CRC.*/
-#define EMAC_FWD_UNDER_GF  (BIT(6))
-#define EMAC_FWD_UNDER_GF_M  (BIT(6))
-#define EMAC_FWD_UNDER_GF_V  0x1
-#define EMAC_FWD_UNDER_GF_S  6
-/* EMAC_DROP_GFRM : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: When set  the MAC drops the received giant frames in the Rx FIFO
-  that is frames that are larger than the computed giant frame limit.*/
-#define EMAC_DROP_GFRM  (BIT(5))
-#define EMAC_DROP_GFRM_M  (BIT(5))
-#define EMAC_DROP_GFRM_V  0x1
-#define EMAC_DROP_GFRM_S  5
-/* EMAC_RX_THRESH_CTRL : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: These two bits control the threshold level of the MTL Receive
- FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2'b00: 64， 2'b01: 32， 2'b10: 96， 2'b11: 128 .*/
-#define EMAC_RX_THRESH_CTRL  0x00000003
-#define EMAC_RX_THRESH_CTRL_M  ((EMAC_RX_THRESH_CTRL_V)<<(EMAC_RX_THRESH_CTRL_S))
-#define EMAC_RX_THRESH_CTRL_V  0x3
-#define EMAC_RX_THRESH_CTRL_S  3
-/* EMAC_OPT_SECOND_FRAME : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: When this bit is set  it instructs the DMA to process the second
- frame of the Transmit data even before the status for the first frame is obtained.*/
-#define EMAC_OPT_SECOND_FRAME  (BIT(2))
-#define EMAC_OPT_SECOND_FRAME_M  (BIT(2))
-#define EMAC_OPT_SECOND_FRAME_V  0x1
-#define EMAC_OPT_SECOND_FRAME_S  2
-/* EMAC_START_STOP_RX : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: When this bit is set  the Receive process is placed in the Running
- state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared  the Rx DMA operation is stopped after the transfer of the current frame.*/
-#define EMAC_START_STOP_RX  (BIT(1))
-#define EMAC_START_STOP_RX_M  (BIT(1))
-#define EMAC_START_STOP_RX_V  0x1
-#define EMAC_START_STOP_RX_S  1
-
-#define EMAC_DMAIN_EN_REG          (DR_REG_EMAC_BASE + 0x001C)
-/* EMAC_DMAIN_NISE : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: When this bit is set  normal interrupt summary is enabled. When
- this bit is reset  normal interrupt summary is disabled. This bit enables the following interrupts in Status Register:  Bit[0]: Transmit Interrupt.  Bit[2]: Transmit Buffer Unavailable.  Bit[6]: Receive Interrupt.  Bit[14]: Early Receive Interrupt.*/
-#define EMAC_DMAIN_NISE  (BIT(16))
-#define EMAC_DMAIN_NISE_M  (BIT(16))
-#define EMAC_DMAIN_NISE_V  0x1
-#define EMAC_DMAIN_NISE_S  16
-/* EMAC_DMAIN_AISE : R/W ;bitpos:[15] ;default: 1'h0 ; */
-/*description: When this bit is set  abnormal interrupt summary is enabled.
- When this bit is reset the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status Register:  Bit[1]: Transmit Process Stopped.  Bit[3]: Transmit Jabber Timeout.  Bit[4]: Receive Overflow.  Bit[5]: Transmit Underflow.  Bit[7]: Receive Buffer Unavailable.  Bit[8]: Receive Process Stopped.  Bit[9]: Receive Watchdog Timeout.  Bit[10]: Early Transmit Interrupt.  Bit[13]: Fatal Bus Error.*/
-#define EMAC_DMAIN_AISE  (BIT(15))
-#define EMAC_DMAIN_AISE_M  (BIT(15))
-#define EMAC_DMAIN_AISE_V  0x1
-#define EMAC_DMAIN_AISE_S  15
-/* EMAC_DMAIN_ERIE : R/W ;bitpos:[14] ;default: 1'h0 ; */
-/*description: When this bit is set with Normal Interrupt Summary Enable (Bit[16])
-  the Early Receive Interrupt is enabled. When this bit is reset  the Early Receive Interrupt is disabled.*/
-#define EMAC_DMAIN_ERIE  (BIT(14))
-#define EMAC_DMAIN_ERIE_M  (BIT(14))
-#define EMAC_DMAIN_ERIE_V  0x1
-#define EMAC_DMAIN_ERIE_S  14
-/* EMAC_DMAIN_FBEE : R/W ;bitpos:[13] ;default: 1'h0 ; */
-/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])
-  the Fatal Bus Error Interrupt is enabled. When this bit is reset  the Fatal Bus Error Enable Interrupt is disabled.*/
-#define EMAC_DMAIN_FBEE  (BIT(13))
-#define EMAC_DMAIN_FBEE_M  (BIT(13))
-#define EMAC_DMAIN_FBEE_V  0x1
-#define EMAC_DMAIN_FBEE_S  13
-/* EMAC_DMAIN_ETIE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: When this bit is set with an Abnormal Interrupt Summary Enable
- (Bit[15])  the Early Transmit Interrupt is enabled. When this bit is reset  the Early Transmit Interrupt is disabled.*/
-#define EMAC_DMAIN_ETIE  (BIT(10))
-#define EMAC_DMAIN_ETIE_M  (BIT(10))
-#define EMAC_DMAIN_ETIE_V  0x1
-#define EMAC_DMAIN_ETIE_S  10
-/* EMAC_DMAIN_RWTE : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])
-  the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset  the Receive Watchdog Timeout Interrupt is disabled.*/
-#define EMAC_DMAIN_RWTE  (BIT(9))
-#define EMAC_DMAIN_RWTE_M  (BIT(9))
-#define EMAC_DMAIN_RWTE_V  0x1
-#define EMAC_DMAIN_RWTE_S  9
-/* EMAC_DMAIN_RSE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])
-  the Receive Stopped Interrupt is enabled. When this bit is reset  the Receive Stopped Interrupt is disabled.*/
-#define EMAC_DMAIN_RSE  (BIT(8))
-#define EMAC_DMAIN_RSE_M  (BIT(8))
-#define EMAC_DMAIN_RSE_V  0x1
-#define EMAC_DMAIN_RSE_S  8
-/* EMAC_DMAIN_RBUE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])
-  the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset  the Receive Buffer Unavailable Interrupt is disabled.*/
-#define EMAC_DMAIN_RBUE  (BIT(7))
-#define EMAC_DMAIN_RBUE_M  (BIT(7))
-#define EMAC_DMAIN_RBUE_V  0x1
-#define EMAC_DMAIN_RBUE_S  7
-/* EMAC_DMAIN_RIE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: When this bit is set with Normal Interrupt Summary Enable (Bit[16])
-  the Receive Interrupt is enabled. When this bit is reset  the Receive Interrupt is disabled.*/
-#define EMAC_DMAIN_RIE  (BIT(6))
-#define EMAC_DMAIN_RIE_M  (BIT(6))
-#define EMAC_DMAIN_RIE_V  0x1
-#define EMAC_DMAIN_RIE_S  6
-/* EMAC_DMAIN_UIE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])
-  the Transmit Underflow Interrupt is enabled. When this bit is reset  the Underflow Interrupt is disabled.*/
-#define EMAC_DMAIN_UIE  (BIT(5))
-#define EMAC_DMAIN_UIE_M  (BIT(5))
-#define EMAC_DMAIN_UIE_V  0x1
-#define EMAC_DMAIN_UIE_S  5
-/* EMAC_DMAIN_OIE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])
-  the Receive Overflow Interrupt is enabled. When this bit is reset  the Overflow Interrupt is disabled.*/
-#define EMAC_DMAIN_OIE  (BIT(4))
-#define EMAC_DMAIN_OIE_M  (BIT(4))
-#define EMAC_DMAIN_OIE_V  0x1
-#define EMAC_DMAIN_OIE_S  4
-/* EMAC_DMAIN_TJTE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])
-  the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset  the Transmit Jabber Timeout Interrupt is disabled.*/
-#define EMAC_DMAIN_TJTE  (BIT(3))
-#define EMAC_DMAIN_TJTE_M  (BIT(3))
-#define EMAC_DMAIN_TJTE_V  0x1
-#define EMAC_DMAIN_TJTE_S  3
-/* EMAC_DMAIN_TBUE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: When this bit is set with Normal Interrupt Summary Enable (Bit
- 16)  the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset  the Transmit Buffer Unavailable Interrupt is Disabled.*/
-#define EMAC_DMAIN_TBUE  (BIT(2))
-#define EMAC_DMAIN_TBUE_M  (BIT(2))
-#define EMAC_DMAIN_TBUE_V  0x1
-#define EMAC_DMAIN_TBUE_S  2
-/* EMAC_DMAIN_TSE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])
-  the Transmission Stopped Interrupt is enabled. When this bit is reset  the Transmission Stopped Interrupt is disabled.*/
-#define EMAC_DMAIN_TSE  (BIT(1))
-#define EMAC_DMAIN_TSE_M  (BIT(1))
-#define EMAC_DMAIN_TSE_V  0x1
-#define EMAC_DMAIN_TSE_S  1
-/* EMAC_DMAIN_TIE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: When this bit is set with Normal Interrupt Summary Enable (Bit[16])
-  the Transmit Interrupt is enabled. When this bit is reset  the Transmit Interrupt is disabled.*/
-#define EMAC_DMAIN_TIE  (BIT(0))
-#define EMAC_DMAIN_TIE_M  (BIT(0))
-#define EMAC_DMAIN_TIE_V  0x1
-#define EMAC_DMAIN_TIE_S  0
-
-#define EMAC_DMAMISSEDFR_REG          (DR_REG_EMAC_BASE + 0x0020)
-/* EMAC_OVERFLOW_BFOC : R_SS_RC ;bitpos:[28] ;default: 1'h0 ; */
-/*description: This bit is set every time the Overflow Frame Counter (Bits[27:17])
- overflows  that is  the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario  the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
-#define EMAC_OVERFLOW_BFOC  (BIT(28))
-#define EMAC_OVERFLOW_BFOC_M  (BIT(28))
-#define EMAC_OVERFLOW_BFOC_V  0x1
-#define EMAC_OVERFLOW_BFOC_S  28
-/* EMAC_OVERFLOW_FC : R_SS_RC ;bitpos:[27:17] ;default: 11'h0 ; */
-/*description: This field indicates the number of frames missed by the application.
- This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read.*/
-#define EMAC_OVERFLOW_FC  0x000007FF
-#define EMAC_OVERFLOW_FC_M  ((EMAC_OVERFLOW_FC_V)<<(EMAC_OVERFLOW_FC_S))
-#define EMAC_OVERFLOW_FC_V  0x7FF
-#define EMAC_OVERFLOW_FC_S  17
-/* EMAC_OVERFLOW_BMFC : R_SS_RC ;bitpos:[16] ;default: 1'h0 ; */
-/*description: This bit is set every time Missed Frame Counter (Bits[15:0])
- overflows that is  the DMA discards an incoming frame because of the Host Receive  Buffer being unavailable with the missed frame counter at maximum value. In such a scenario  the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
-#define EMAC_OVERFLOW_BMFC  (BIT(16))
-#define EMAC_OVERFLOW_BMFC_M  (BIT(16))
-#define EMAC_OVERFLOW_BMFC_V  0x1
-#define EMAC_OVERFLOW_BMFC_S  16
-/* EMAC_MISSED_FC : R_SS_RC ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This field indicates the number of frames missed by the controller
- because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read.*/
-#define EMAC_MISSED_FC  0x0000FFFF
-#define EMAC_MISSED_FC_M  ((EMAC_MISSED_FC_V)<<(EMAC_MISSED_FC_S))
-#define EMAC_MISSED_FC_V  0xFFFF
-#define EMAC_MISSED_FC_S  0
-
-#define EMAC_DMARINTWDTIMER_REG          (DR_REG_EMAC_BASE + 0x0024)
-/* EMAC_RIWTC : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: This bit indicates the number of system clock cycles multiplied
- by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out  the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame.*/
-#define EMAC_RIWTC  0x000000FF
-#define EMAC_RIWTC_M  ((EMAC_RIWTC_V)<<(EMAC_RIWTC_S))
-#define EMAC_RIWTC_V  0xFF
-#define EMAC_RIWTC_S  0
-
-#define EMAC_DMATXCURRDESC_REG          (DR_REG_EMAC_BASE + 0x0048)
-/* EMAC_TRANS_DSCR_ADDR_PTR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The address of the current receive descriptor list. Cleared on
- Reset.Pointer updated by the DMA during operation.*/
-#define EMAC_TRANS_DSCR_ADDR_PTR  0xFFFFFFFF
-#define EMAC_TRANS_DSCR_ADDR_PTR_M  ((EMAC_TRANS_DSCR_ADDR_PTR_V)<<(EMAC_TRANS_DSCR_ADDR_PTR_S))
-#define EMAC_TRANS_DSCR_ADDR_PTR_V  0xFFFFFFFF
-#define EMAC_TRANS_DSCR_ADDR_PTR_S  0
-
-#define EMAC_DMARXCURRDESC_REG          (DR_REG_EMAC_BASE + 0x004C)
-/* EMAC_RECV_DSCR_ADDR_PTR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The address of the current receive descriptor list. Cleared on
- Reset.Pointer updated by the DMA during operation.*/
-#define EMAC_RECV_DSCR_ADDR_PTR  0xFFFFFFFF
-#define EMAC_RECV_DSCR_ADDR_PTR_M  ((EMAC_RECV_DSCR_ADDR_PTR_V)<<(EMAC_RECV_DSCR_ADDR_PTR_S))
-#define EMAC_RECV_DSCR_ADDR_PTR_V  0xFFFFFFFF
-#define EMAC_RECV_DSCR_ADDR_PTR_S  0
-
-#define EMAC_DMATXCURRADDR_BUF_REG          (DR_REG_EMAC_BASE + 0x0050)
-/* EMAC_TRANS_BUFF_ADDR_PTR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The address of the current receive descriptor list. Cleared on
- Reset.Pointer updated by the DMA during operation.*/
-#define EMAC_TRANS_BUFF_ADDR_PTR  0xFFFFFFFF
-#define EMAC_TRANS_BUFF_ADDR_PTR_M  ((EMAC_TRANS_BUFF_ADDR_PTR_V)<<(EMAC_TRANS_BUFF_ADDR_PTR_S))
-#define EMAC_TRANS_BUFF_ADDR_PTR_V  0xFFFFFFFF
-#define EMAC_TRANS_BUFF_ADDR_PTR_S  0
-
-#define EMAC_DMARXCURRADDR_BUF_REG          (DR_REG_EMAC_BASE + 0x0054)
-/* EMAC_RECV_BUFF_ADDR_PTR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The address of the current receive descriptor list. Cleared on
- Reset.Pointer updated by the DMA during operation.*/
-#define EMAC_RECV_BUFF_ADDR_PTR  0xFFFFFFFF
-#define EMAC_RECV_BUFF_ADDR_PTR_M  ((EMAC_RECV_BUFF_ADDR_PTR_V)<<(EMAC_RECV_BUFF_ADDR_PTR_S))
-#define EMAC_RECV_BUFF_ADDR_PTR_V  0xFFFFFFFF
-#define EMAC_RECV_BUFF_ADDR_PTR_S  0
-
-#define EMAC_GMACCONFIG_REG          (DR_REG_EMAC_BASE + 0x1000)
-/* EMAC_SAIRC : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
-/*description: This field controls the source address insertion or replacement
- for all transmitted frames.Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]:  2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation.  2'b10: If Bit[30] is set to 0  the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted frames.  2'b11: If Bit[30] is set to 0  the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1  the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames.*/
-#define EMAC_SAIRC  0x00000007
-#define EMAC_SAIRC_M  ((EMAC_SAIRC_V)<<(EMAC_SAIRC_S))
-#define EMAC_SAIRC_V  0x7
-#define EMAC_SAIRC_S  28
-/* EMAC_ASS2KP : R/W ;bitpos:[27] ;default: 1'h0 ; */
-/*description: When set  the MAC considers all frames  with up to 2 000 bytes
- length  as normal packets.When Bit[20] (JE) is not set  the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set  the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set  setting this bit has no effect on Giant Frame status.*/
-#define EMAC_ASS2KP  (BIT(27))
-#define EMAC_ASS2KP_M  (BIT(27))
-#define EMAC_ASS2KP_V  0x1
-#define EMAC_ASS2KP_S  27
-/* EMAC_EMACWATCHDOG : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC disables the watchdog timer on
- the receiver. The MAC can receive frames of up to 16 383 bytes. When this bit is reset  the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is set high) or the value programmed in Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes.*/
-#define EMAC_EMACWATCHDOG  (BIT(23))
-#define EMAC_EMACWATCHDOG_M  (BIT(23))
-#define EMAC_EMACWATCHDOG_V  0x1
-#define EMAC_EMACWATCHDOG_S  23
-/* EMAC_EMACJABBER : R/W ;bitpos:[22] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC disables the jabber timer on the
- transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset  the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data (10 240 if JE is set high) during Transmission.*/
-#define EMAC_EMACJABBER  (BIT(22))
-#define EMAC_EMACJABBER_M  (BIT(22))
-#define EMAC_EMACJABBER_V  0x1
-#define EMAC_EMACJABBER_S  22
-/* EMAC_EMACJUMBOFRAME : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC allows Jumbo frames of 9 018 bytes
- (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.*/
-#define EMAC_EMACJUMBOFRAME  (BIT(20))
-#define EMAC_EMACJUMBOFRAME_M  (BIT(20))
-#define EMAC_EMACJUMBOFRAME_V  0x1
-#define EMAC_EMACJUMBOFRAME_S  20
-/* EMAC_EMACINTERFRAMEGAP : R/W ;bitpos:[19:17] ;default: 1'h0 ; */
-/*description: These bits control the minimum IFG between frames during transmission.
-  3'b000: 96 bit times.  3'b001: 88 bit times.  3'b010: 80 bit times.  3'b111: 40 bit times. In the half-duplex mode  the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered.*/
-#define EMAC_EMACINTERFRAMEGAP  0x00000007
-#define EMAC_EMACINTERFRAMEGAP_M  ((EMAC_EMACINTERFRAMEGAP_V)<<(EMAC_EMACINTERFRAMEGAP_S))
-#define EMAC_EMACINTERFRAMEGAP_V  0x7
-#define EMAC_EMACINTERFRAMEGAP_S  17
-/* EMAC_EMACDISABLECRS : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: When set high  this bit makes the MAC transmitter ignore the
- MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low  the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions.*/
-#define EMAC_EMACDISABLECRS  (BIT(16))
-#define EMAC_EMACDISABLECRS_M  (BIT(16))
-#define EMAC_EMACDISABLECRS_V  0x1
-#define EMAC_EMACDISABLECRS_S  16
-/* EMAC_EMACMII : R/W ;bitpos:[15] ;default: 1'h0 ; */
-/*description: This bit selects the Ethernet line speed. It should be set to
- 1 for 10 or 100 Mbps operations.In 10 or 100 Mbps operations  this bit  along with FES(EMACFESPEED) bit  it selects the exact linespeed. In the 10/100 Mbps-only operations  the bit is always 1.*/
-#define EMAC_EMACMII  (BIT(15))
-#define EMAC_EMACMII_M  (BIT(15))
-#define EMAC_EMACMII_V  0x1
-#define EMAC_EMACMII_S  15
-/* EMAC_EMACFESPEED : R/W ;bitpos:[14] ;default: 1'h0 ; */
-/*description: This bit selects the speed in the MII  RMII interface. 0: 10 Mbps. 1: 100 Mbps.*/
-#define EMAC_EMACFESPEED  (BIT(14))
-#define EMAC_EMACFESPEED_M  (BIT(14))
-#define EMAC_EMACFESPEED_V  0x1
-#define EMAC_EMACFESPEED_S  14
-/* EMAC_EMACRXOWN : R/W ;bitpos:[13] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC disables the reception of frames
- when the TX_EN is asserted in the half-duplex mode. When this bit is reset  the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full duplex mode.*/
-#define EMAC_EMACRXOWN  (BIT(13))
-#define EMAC_EMACRXOWN_M  (BIT(13))
-#define EMAC_EMACRXOWN_V  0x1
-#define EMAC_EMACRXOWN_S  13
-/* EMAC_EMACLOOPBACK : R/W ;bitpos:[12] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC operates in the loopback mode MII.
- The MII Receive clock input (CLK_RX) is required for the loopback to work properly  because the transmit clock is not looped-back internally.*/
-#define EMAC_EMACLOOPBACK  (BIT(12))
-#define EMAC_EMACLOOPBACK_M  (BIT(12))
-#define EMAC_EMACLOOPBACK_V  0x1
-#define EMAC_EMACLOOPBACK_S  12
-/* EMAC_EMACDUPLEX : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC operates in the full-duplex mode
- where it can transmit and receive simultaneously. This bit is read only with default value of 1'b1 in the full-duplex-mode.*/
-#define EMAC_EMACDUPLEX  (BIT(11))
-#define EMAC_EMACDUPLEX_M  (BIT(11))
-#define EMAC_EMACDUPLEX_V  0x1
-#define EMAC_EMACDUPLEX_S  11
-/* EMAC_EMACRXIPCOFFLOAD : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC calculates the 16-bit one's complement
- of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset  this function is disabled.*/
-#define EMAC_EMACRXIPCOFFLOAD  (BIT(10))
-#define EMAC_EMACRXIPCOFFLOAD_M  (BIT(10))
-#define EMAC_EMACRXIPCOFFLOAD_V  0x1
-#define EMAC_EMACRXIPCOFFLOAD_S  10
-/* EMAC_EMACRETRY : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC attempts only one transmission.
- When a collision occurs on the MII interface  the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset  the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex Mode.*/
-#define EMAC_EMACRETRY  (BIT(9))
-#define EMAC_EMACRETRY_M  (BIT(9))
-#define EMAC_EMACRETRY_V  0x1
-#define EMAC_EMACRETRY_S  9
-/* EMAC_EMACPADCRCSTRIP : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC strips the Pad or FCS field on
- the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset  the MAC passes all incoming frames  without modifying them to the Host.*/
-#define EMAC_EMACPADCRCSTRIP  (BIT(7))
-#define EMAC_EMACPADCRCSTRIP_M  (BIT(7))
-#define EMAC_EMACPADCRCSTRIP_V  0x1
-#define EMAC_EMACPADCRCSTRIP_S  7
-/* EMAC_EMACBACKOFFLIMIT : R/W ;bitpos:[6:5] ;default: 2'h0 ; */
-/*description: The Back-Off limit determines the random integer number (r) of
- slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode.  00: k= min (n  10).  01: k = min (n  8).  10: k = min (n  4).  11: k = min (n  1)  n = retransmission attempt. The random integer r takes the value in the Range 0 ~ 2000.*/
-#define EMAC_EMACBACKOFFLIMIT  0x00000003
-#define EMAC_EMACBACKOFFLIMIT_M  ((EMAC_EMACBACKOFFLIMIT_V)<<(EMAC_EMACBACKOFFLIMIT_S))
-#define EMAC_EMACBACKOFFLIMIT_V  0x3
-#define EMAC_EMACBACKOFFLIMIT_S  5
-/* EMAC_EMACDEFERRALCHECK : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: Deferral Check.*/
-#define EMAC_EMACDEFERRALCHECK  (BIT(4))
-#define EMAC_EMACDEFERRALCHECK_M  (BIT(4))
-#define EMAC_EMACDEFERRALCHECK_V  0x1
-#define EMAC_EMACDEFERRALCHECK_S  4
-/* EMAC_EMACTX : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: When this bit is set  the transmit state machine of the MAC is
- enabled for transmission on the MII. When this bit is reset  the MAC transmit state machine is disabled after the completion of the transmission of the current frame  and does not transmit any further frames.*/
-#define EMAC_EMACTX  (BIT(3))
-#define EMAC_EMACTX_M  (BIT(3))
-#define EMAC_EMACTX_V  0x1
-#define EMAC_EMACTX_S  3
-/* EMAC_EMACRX : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: When this bit is set  the receiver state machine of the MAC is
- enabled for receiving frames from the MII. When this bit is reset  the MAC receive state machine is disabled after the completion of the reception of the current frame  and does not receive any further frames from the MII.*/
-#define EMAC_EMACRX  (BIT(2))
-#define EMAC_EMACRX_M  (BIT(2))
-#define EMAC_EMACRX_V  0x1
-#define EMAC_EMACRX_S  2
-/* EMAC_PLTF : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: These bits control the number of preamble bytes that are added
- to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/
-#define EMAC_PLTF  0x00000003
-#define EMAC_PLTF_M  ((EMAC_PLTF_V)<<(EMAC_PLTF_S))
-#define EMAC_PLTF_V  0x3
-#define EMAC_PLTF_S  0
-
-#define EMAC_GMACFF_REG          (DR_REG_EMAC_BASE + 0x1004)
-/* EMAC_RECEIVE_ALL : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC Receiver module passes all received
- frames  irrespective of whether they pass the address filter or not  to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter.*/
-#define EMAC_RECEIVE_ALL  (BIT(31))
-#define EMAC_RECEIVE_ALL_M  (BIT(31))
-#define EMAC_RECEIVE_ALL_V  0x1
-#define EMAC_RECEIVE_ALL_S  31
-/* EMAC_SAFE : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC compares the SA field of the received
- frames with the values programmed in the enabled SA registers. If the comparison fails  the MAC drops the frame. When this bit is reset  the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison.*/
-#define EMAC_SAFE  (BIT(9))
-#define EMAC_SAFE_M  (BIT(9))
-#define EMAC_SAFE_V  0x1
-#define EMAC_SAFE_S  9
-/* EMAC_SAIF : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: When this bit is set  the Address Check block operates in inverse
- filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset  frames whose SA does not match the SA registers are marked as failing the SA Address filter.*/
-#define EMAC_SAIF  (BIT(8))
-#define EMAC_SAIF_M  (BIT(8))
-#define EMAC_SAIF_V  0x1
-#define EMAC_SAIF_S  8
-/* EMAC_PCF : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: These bits control the forwarding of all control frames (including
- unicast and multicast Pause frames).   2'b00: MAC filters all control frames from reaching the application.  2'b01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter.  2'b10: MAC forwards all control frames to application even if they fail the Address Filter.  2'b11: MAC forwards control frames that pass the Address Filter.The following conditions should be true for the Pause frames processing:  Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register (Flow Control Register) to 1.  Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set.  Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.*/
-#define EMAC_PCF  0x00000003
-#define EMAC_PCF_M  ((EMAC_PCF_V)<<(EMAC_PCF_S))
-#define EMAC_PCF_V  0x3
-#define EMAC_PCF_S  6
-/* EMAC_DBF : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: When this bit is set  the AFM(Address Filtering Module) module
- blocks all incoming broadcast frames. In addition  it overrides all other filter settings. When this bit is reset  the AFM module passes all received broadcast Frames.*/
-#define EMAC_DBF  (BIT(5))
-#define EMAC_DBF_M  (BIT(5))
-#define EMAC_DBF_V  0x1
-#define EMAC_DBF_S  5
-/* EMAC_PAM : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: When set  this bit indicates that all received frames with a
- multicast destination address (first bit in the destination address field is '1') are passed.*/
-#define EMAC_PAM  (BIT(4))
-#define EMAC_PAM_M  (BIT(4))
-#define EMAC_PAM_V  0x1
-#define EMAC_PAM_S  4
-/* EMAC_DAIF : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: When this bit is set  the Address Check block operates in inverse
- filtering mode for the DA address comparison for both unicast and multicast frames. When reset  normal filtering of frames is performed.*/
-#define EMAC_DAIF  (BIT(3))
-#define EMAC_DAIF_M  (BIT(3))
-#define EMAC_DAIF_V  0x1
-#define EMAC_DAIF_S  3
-/* EMAC_PMODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: When this bit is set  the Address Filter module passes all incoming
- frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set.*/
-#define EMAC_PMODE  (BIT(0))
-#define EMAC_PMODE_M  (BIT(0))
-#define EMAC_PMODE_V  0x1
-#define EMAC_PMODE_S  0
-
-#define EMAC_GMIIADDR_REG          (DR_REG_EMAC_BASE + 0x1010)
-/* EMAC_MIIDEV : R/W ;bitpos:[15:11] ;default: 6'h0 ; */
-/*description: This field indicates which of the 32 possible PHY devices are being accessed.*/
-#define EMAC_MIIDEV  0x0000001F
-#define EMAC_MIIDEV_M  ((EMAC_MIIDEV_V)<<(EMAC_MIIDEV_S))
-#define EMAC_MIIDEV_V  0x1F
-#define EMAC_MIIDEV_S  11
-/* EMAC_MIIREG : R/W ;bitpos:[10:6] ;default: 5'h0 ; */
-/*description: These bits select the desired MII register in the selected PHY device.*/
-#define EMAC_MIIREG  0x0000001F
-#define EMAC_MIIREG_M  ((EMAC_MIIREG_V)<<(EMAC_MIIREG_S))
-#define EMAC_MIIREG_V  0x1F
-#define EMAC_MIIREG_S  6
-/* EMAC_MIICSRCLK : R/W ;bitpos:[5:2] ;default: 5'h0 ; */
-/*description: CSR clock range: 1.0 MHz ~ 2.5 MHz.  4'b0000: When the APB clock
- frequency is 80 MHz  the MDC clock frequency is APB CLK/42  4'b0000: When the APB clock frequency is 40 MHz  the MDC clock frequency is APB CLK/26.*/
-#define EMAC_MIICSRCLK  0x0000000F
-#define EMAC_MIICSRCLK_M  ((EMAC_MIICSRCLK_V)<<(EMAC_MIICSRCLK_S))
-#define EMAC_MIICSRCLK_V  0xF
-#define EMAC_MIICSRCLK_S  2
-/* EMAC_MIIWRITE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: When set  this bit indicates to the PHY that this is a Write
- operation using the MII Data register. If this bit is not set  it indicates that this is a Read operation  that is  placing the data in the MII Data register.*/
-#define EMAC_MIIWRITE  (BIT(1))
-#define EMAC_MIIWRITE_M  (BIT(1))
-#define EMAC_MIIWRITE_V  0x1
-#define EMAC_MIIWRITE_S  1
-/* EMAC_MIIBUSY : R_WS_SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: This bit should read logic 0 before writing to PHY Addr Register
- and PHY data Register.During a PHY register access  the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation  the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed  there is no change in the functionality of this bit even when the PHY is not Present.*/
-#define EMAC_MIIBUSY  (BIT(0))
-#define EMAC_MIIBUSY_M  (BIT(0))
-#define EMAC_MIIBUSY_V  0x1
-#define EMAC_MIIBUSY_S  0
-
-#define EMAC_MIIDATA_REG          (DR_REG_EMAC_BASE + 0x1014)
-/* EMAC_MII_DATA : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This field contains the 16-bit data value read from the PHY after
- a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation.*/
-#define EMAC_MII_DATA  0x0000FFFF
-#define EMAC_MII_DATA_M  ((EMAC_MII_DATA_V)<<(EMAC_MII_DATA_S))
-#define EMAC_MII_DATA_V  0xFFFF
-#define EMAC_MII_DATA_S  0
-
-#define EMAC_GMACFC_REG          (DR_REG_EMAC_BASE + 0x1018)
-/* EMAC_PAUSE_TIME : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: This field holds the value to be used in the Pause Time field
- in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.*/
-#define EMAC_PAUSE_TIME  0x0000FFFF
-#define EMAC_PAUSE_TIME_M  ((EMAC_PAUSE_TIME_V)<<(EMAC_PAUSE_TIME_S))
-#define EMAC_PAUSE_TIME_V  0xFFFF
-#define EMAC_PAUSE_TIME_S  16
-/* EMAC_DZPQ : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: When this bit is set  it disables the automatic generation of
- the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset  normal operation with automatic Zero-Quanta Pause frame generation is enabled.*/
-#define EMAC_DZPQ  (BIT(7))
-#define EMAC_DZPQ_M  (BIT(7))
-#define EMAC_DZPQ_V  0x1
-#define EMAC_DZPQ_S  7
-/* EMAC_PLT : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: This field configures the threshold of the Pause timer automatic
- retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example  if PT = 100H (256 slot-times)  and PLT = 01  then a second Pause frame is automatically transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values:   2'b00: The threshold is Pause time minus 4 slot times (PT-4 slot times).  2'b01: The threshold is Pause time minus 28 slot times (PT-28 slot times).  2'b10: The threshold is Pause time minus 144 slot times (PT-144 slot times).  2'b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface.*/
-#define EMAC_PLT  0x00000003
-#define EMAC_PLT_M  ((EMAC_PLT_V)<<(EMAC_PLT_S))
-#define EMAC_PLT_V  0x3
-#define EMAC_PLT_S  4
-/* EMAC_UPFD : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: A pause frame is processed when it has the unique multicast address
- specified in the IEEE Std 802.3. When this bit is set  the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the EMACADDR0 High Register and EMACADDR0 Low Register. When this bit is reset  the MAC only detects Pause frames with unique multicast address.*/
-#define EMAC_UPFD  (BIT(3))
-#define EMAC_UPFD_M  (BIT(3))
-#define EMAC_UPFD_V  0x1
-#define EMAC_UPFD_S  3
-/* EMAC_RFCE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: When this bit is set  the MAC decodes the received Pause frame
- and disables its transmitter for a specified (Pause) time. When this bit is reset  the decode function of the Pause frame is disabled.*/
-#define EMAC_RFCE  (BIT(2))
-#define EMAC_RFCE_M  (BIT(2))
-#define EMAC_RFCE_V  0x1
-#define EMAC_RFCE_S  2
-/* EMAC_TFCE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: In the full-duplex mode  when this bit is set  the MAC enables
- the flow control operation to transmit Pause frames. When this bit is reset  the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode  when this bit is set the MAC enables the backpressure operation. When this bit is reset  the backpressure feature is Disabled.*/
-#define EMAC_TFCE  (BIT(1))
-#define EMAC_TFCE_M  (BIT(1))
-#define EMAC_TFCE_V  0x1
-#define EMAC_TFCE_S  1
-/* EMAC_FCBBA : R_WS_SC(FCB)/R_W(BPA) ;bitpos:[0] ;default: 1'h0 ; */
-/*description: This bit initiates a Pause frame in the full-duplex mode and
- activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode  this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame  the Application must set this bit to 1'b1. During a transfer of the Control Frame  this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission  the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode  when this bit is set (and TFCE is set)  then backpressure is asserted by the MAC. During backpressure  when the MAC receives a new frame  the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode  the BPA(backpressure activate) is automatically disabled.*/
-#define EMAC_FCBBA  (BIT(0))
-#define EMAC_FCBBA_M  (BIT(0))
-#define EMAC_FCBBA_V  0x1
-#define EMAC_FCBBA_S  0
-
-#define EMAC_DEBUG_REG          (DR_REG_EMAC_BASE + 0x1024)
-/* EMAC_MTLTSFFS : RO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: When high  this bit indicates that the MTL TxStatus FIFO is full.
- Therefore  the MTL cannot accept any more frames for transmission.*/
-#define EMAC_MTLTSFFS  (BIT(25))
-#define EMAC_MTLTSFFS_M  (BIT(25))
-#define EMAC_MTLTSFFS_V  0x1
-#define EMAC_MTLTSFFS_S  25
-/* EMAC_MTLTFNES : RO ;bitpos:[24] ;default: 1'h0 ; */
-/*description: When high  this bit indicates that the MTL Tx FIFO is not empty
- and some data is left for Transmission.*/
-#define EMAC_MTLTFNES  (BIT(24))
-#define EMAC_MTLTFNES_M  (BIT(24))
-#define EMAC_MTLTFNES_V  0x1
-#define EMAC_MTLTFNES_S  24
-/* EMAC_MTLTFWCS : RO ;bitpos:[22] ;default: 1'h0 ; */
-/*description: When high  this bit indicates that the MTL Tx FIFO Write Controller
- is active and is transferring data to the Tx FIFO.*/
-#define EMAC_MTLTFWCS  (BIT(22))
-#define EMAC_MTLTFWCS_M  (BIT(22))
-#define EMAC_MTLTFWCS_V  0x1
-#define EMAC_MTLTFWCS_S  22
-/* EMAC_MTLTFRCS : RO ;bitpos:[21:20] ;default: 2'h0 ; */
-/*description: This field indicates the state of the Tx FIFO Read Controller:
-   2'b00: IDLE state.  2'b01: READ state (transferring data to the MAC transmitter).  2'b10: Waiting for TxStatus from the MAC transmitter.  2'b11: Writing the received TxStatus or flushing the Tx FIFO.*/
-#define EMAC_MTLTFRCS  0x00000003
-#define EMAC_MTLTFRCS_M  ((EMAC_MTLTFRCS_V)<<(EMAC_MTLTFRCS_S))
-#define EMAC_MTLTFRCS_V  0x3
-#define EMAC_MTLTFRCS_S  20
-/* EMAC_MACTP : RO ;bitpos:[19] ;default: 1'h0 ; */
-/*description: When high  this bit indicates that the MAC transmitter is in
- the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission.*/
-#define EMAC_MACTP  (BIT(19))
-#define EMAC_MACTP_M  (BIT(19))
-#define EMAC_MACTP_V  0x1
-#define EMAC_MACTP_S  19
-/* EMAC_MACTFCS : RO ;bitpos:[18:17] ;default: 2'h0 ; */
-/*description: This field indicates the state of the MAC Transmit Frame Controller
- module:   2'b00: IDLE state.  2'b01: Waiting for status of previous frame or IFG or backoff period to be over.  2'b10: Generating and transmitting a Pause frame (in the full-duplex mode).  2'b11: Transferring input frame for transmission.*/
-#define EMAC_MACTFCS  0x00000003
-#define EMAC_MACTFCS_M  ((EMAC_MACTFCS_V)<<(EMAC_MACTFCS_S))
-#define EMAC_MACTFCS_V  0x3
-#define EMAC_MACTFCS_S  17
-/* EMAC_MACTPES : RO ;bitpos:[16] ;default: 1'h0 ; */
-/*description: When high  this bit indicates that the MAC MII transmit protocol
- engine is actively transmitting data and is not in the IDLE state.*/
-#define EMAC_MACTPES  (BIT(16))
-#define EMAC_MACTPES_M  (BIT(16))
-#define EMAC_MACTPES_V  0x1
-#define EMAC_MACTPES_S  16
-/* EMAC_MTLRFFLS : RO ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: This field gives the status of the fill-level of the Rx FIFO:
-   2'b00: Rx FIFO Empty.  2'b01: Rx FIFO fill-level below flow-control deactivate threshold.  2'b10: Rx FIFO fill-level above flow-control activate threshold.  2'b11: Rx FIFO Full.*/
-#define EMAC_MTLRFFLS  0x00000003
-#define EMAC_MTLRFFLS_M  ((EMAC_MTLRFFLS_V)<<(EMAC_MTLRFFLS_S))
-#define EMAC_MTLRFFLS_V  0x3
-#define EMAC_MTLRFFLS_S  8
-/* EMAC_MTLRFRCS : RO ;bitpos:[6:5] ;default: 2'h0 ; */
-/*description: This field gives the state of the Rx FIFO read Controller: 2'b00:
- IDLE state.2'b01: Reading frame data.2'b10: Reading frame status (or timestamp).2'b11: Flushing the frame data and status.*/
-#define EMAC_MTLRFRCS  0x00000003
-#define EMAC_MTLRFRCS_M  ((EMAC_MTLRFRCS_V)<<(EMAC_MTLRFRCS_S))
-#define EMAC_MTLRFRCS_V  0x3
-#define EMAC_MTLRFRCS_S  5
-/* EMAC_MTLRFWCAS : RO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: When high  this bit indicates that the MTL Rx FIFO Write Controller
- is active and is transferring a received frame to the FIFO.*/
-#define EMAC_MTLRFWCAS  (BIT(4))
-#define EMAC_MTLRFWCAS_M  (BIT(4))
-#define EMAC_MTLRFWCAS_V  0x1
-#define EMAC_MTLRFWCAS_S  4
-/* EMAC_MACRFFCS : RO ;bitpos:[2:1] ;default: 2'h0 ; */
-/*description: When high  this field indicates the active state of the FIFO
- Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller.*/
-#define EMAC_MACRFFCS  0x00000003
-#define EMAC_MACRFFCS_M  ((EMAC_MACRFFCS_V)<<(EMAC_MACRFFCS_S))
-#define EMAC_MACRFFCS_V  0x3
-#define EMAC_MACRFFCS_S  1
-/* EMAC_MACRPES : RO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: When high  this bit indicates that the MAC MII receive protocol
- engine is actively receiving data and not in IDLE state.*/
-#define EMAC_MACRPES  (BIT(0))
-#define EMAC_MACRPES_M  (BIT(0))
-#define EMAC_MACRPES_V  0x1
-#define EMAC_MACRPES_S  0
-
-#define EMAC_PMT_RWUFFR_REG          (DR_REG_EMAC_BASE + 0x1028)
-/* EMAC_WKUPPKTFILTER : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The MSB (31st bit) must be zero.Bit j[30:0] is the byte mask.
- If Bit 1/2/3/4 (byte number) of the byte mask is set  the CRC block processes the Filter 0/1/2/3 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type  defining the destination address type of the pattern.When the bit is set  the pattern applies to only multicast packets*/
-#define EMAC_WKUPPKTFILTER  0xFFFFFFFF
-#define EMAC_WKUPPKTFILTER_M  ((EMAC_WKUPPKTFILTER_V)<<(EMAC_WKUPPKTFILTER_S))
-#define EMAC_WKUPPKTFILTER_V  0xFFFFFFFF
-#define EMAC_WKUPPKTFILTER_S  0
-
-#define EMAC_PMT_CSR_REG          (DR_REG_EMAC_BASE + 0x102C)
-/* EMAC_RWKFILTRST : R_WS_SC ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When this bit is set  it resets the RWKPTR register to 3’b000.*/
-#define EMAC_RWKFILTRST  (BIT(31))
-#define EMAC_RWKFILTRST_M  (BIT(31))
-#define EMAC_RWKFILTRST_V  0x1
-#define EMAC_RWKFILTRST_S  31
-/* EMAC_RWKPTR : RO ;bitpos:[28:24] ;default: 6'h0 ; */
-/*description: The maximum value of the pointer is 7  the detail information
- please refer to PMT_RWUFFR.*/
-#define EMAC_RWKPTR  0x0000001F
-#define EMAC_RWKPTR_M  ((EMAC_RWKPTR_V)<<(EMAC_RWKPTR_S))
-#define EMAC_RWKPTR_V  0x1F
-#define EMAC_RWKPTR_S  24
-/* EMAC_GLBLUCAST : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: When set  enables any unicast packet filtered by the MAC (DAFilter)
- address recognition to be a remote wake-up frame.*/
-#define EMAC_GLBLUCAST  (BIT(9))
-#define EMAC_GLBLUCAST_M  (BIT(9))
-#define EMAC_GLBLUCAST_V  0x1
-#define EMAC_GLBLUCAST_S  9
-/* EMAC_RWKPRCVD : R_SS_RC ;bitpos:[6] ;default: 1'h0 ; */
-/*description: When set  this bit indicates the power management event is generated
- because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register.*/
-#define EMAC_RWKPRCVD  (BIT(6))
-#define EMAC_RWKPRCVD_M  (BIT(6))
-#define EMAC_RWKPRCVD_V  0x1
-#define EMAC_RWKPRCVD_S  6
-/* EMAC_MGKPRCVD : R_SS_RC ;bitpos:[5] ;default: 1'h0 ; */
-/*description: When set  this bit indicates that the power management event
- is generated because of the reception of a magic packet. This bit is cleared by a Read into this register.*/
-#define EMAC_MGKPRCVD  (BIT(5))
-#define EMAC_MGKPRCVD_M  (BIT(5))
-#define EMAC_MGKPRCVD_V  0x1
-#define EMAC_MGKPRCVD_S  5
-/* EMAC_RWKPKTEN : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: When set  enables generation of a power management event because
- of remote wake-up frame reception*/
-#define EMAC_RWKPKTEN  (BIT(2))
-#define EMAC_RWKPKTEN_M  (BIT(2))
-#define EMAC_RWKPKTEN_V  0x1
-#define EMAC_RWKPKTEN_S  2
-/* EMAC_MGKPKTEN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: When set  enables generation of a power management event because
- of magic packet reception.*/
-#define EMAC_MGKPKTEN  (BIT(1))
-#define EMAC_MGKPKTEN_M  (BIT(1))
-#define EMAC_MGKPKTEN_V  0x1
-#define EMAC_MGKPKTEN_S  1
-/* EMAC_PWRDWN : R_WS_SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: When set  the MAC receiver drops all received frames until it
- receives the expected magic packet or remote wake-up frame.This bit must only be set when MGKPKTEN  GLBLUCAST  or RWKPKTEN bit is set high.*/
-#define EMAC_PWRDWN  (BIT(0))
-#define EMAC_PWRDWN_M  (BIT(0))
-#define EMAC_PWRDWN_V  0x1
-#define EMAC_PWRDWN_S  0
-
-#define EMAC_GMACLPI_CRS_REG          (DR_REG_EMAC_BASE + 0x1030)
-/* EMAC_LPITXA : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: This bit controls the behavior of the MAC when it is entering
- or coming out of the LPI mode on the transmit side.If the LPITXA and LPIEN bits are set to 1  the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0  the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.*/
-#define EMAC_LPITXA  (BIT(19))
-#define EMAC_LPITXA_M  (BIT(19))
-#define EMAC_LPITXA_V  0x1
-#define EMAC_LPITXA_S  19
-/* EMAC_PLS : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: This bit indicates the link status of the PHY.When set  the link
- is considered to be okay (up) and when reset  the link is considered to be down.*/
-#define EMAC_PLS  (BIT(17))
-#define EMAC_PLS_M  (BIT(17))
-#define EMAC_PLS_V  0x1
-#define EMAC_PLS_S  17
-/* EMAC_LPIEN : R_W_SC ;bitpos:[16] ;default: 1'h0 ; */
-/*description: When set  this bit instructs the MAC Transmitter to enter the
- LPI state. When reset  this bit instructs the MAC to exit the LPI state and resume normal transmission.This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.*/
-#define EMAC_LPIEN  (BIT(16))
-#define EMAC_LPIEN_M  (BIT(16))
-#define EMAC_LPIEN_V  0x1
-#define EMAC_LPIEN_S  16
-/* EMAC_RLPIST : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: When set  this bit indicates that the MAC is receiving the LPI
- pattern on the MII interface.*/
-#define EMAC_RLPIST  (BIT(9))
-#define EMAC_RLPIST_M  (BIT(9))
-#define EMAC_RLPIST_V  0x1
-#define EMAC_RLPIST_S  9
-/* EMAC_TLPIST : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: When set  this bit indicates that the MAC is transmitting the
- LPI pattern on the MII interface.*/
-#define EMAC_TLPIST  (BIT(8))
-#define EMAC_TLPIST_M  (BIT(8))
-#define EMAC_TLPIST_V  0x1
-#define EMAC_TLPIST_S  8
-/* EMAC_RLPIEX : R_SS_RC ;bitpos:[3] ;default: 1'h0 ; */
-/*description: When set  this bit indicates that the MAC Receiver has stopped
- receiving the LPI pattern on the MII interface  exited the LPI state  and resumed the normal reception. This bit is cleared by a read into this register.*/
-#define EMAC_RLPIEX  (BIT(3))
-#define EMAC_RLPIEX_M  (BIT(3))
-#define EMAC_RLPIEX_V  0x1
-#define EMAC_RLPIEX_S  3
-/* EMAC_RLPIEN : R_SS_RC ;bitpos:[2] ;default: 1'h0 ; */
-/*description: When set  this bit indicates that the MAC Receiver has received
- an LPI pattern and entered the LPI state. This bit is cleared by a read into this register.*/
-#define EMAC_RLPIEN  (BIT(2))
-#define EMAC_RLPIEN_M  (BIT(2))
-#define EMAC_RLPIEN_V  0x1
-#define EMAC_RLPIEN_S  2
-/* EMAC_TLPIEX : R_SS_RC ;bitpos:[1] ;default: 1'h0 ; */
-/*description: When set  this bit indicates that the MAC transmitter has exited
- the LPI state after the user has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this register.*/
-#define EMAC_TLPIEX  (BIT(1))
-#define EMAC_TLPIEX_M  (BIT(1))
-#define EMAC_TLPIEX_V  0x1
-#define EMAC_TLPIEX_S  1
-/* EMAC_TLPIEN : R_SS_RC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: When set  this bit indicates that the MAC Transmitter has entered
- the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.*/
-#define EMAC_TLPIEN  (BIT(0))
-#define EMAC_TLPIEN_M  (BIT(0))
-#define EMAC_TLPIEN_V  0x1
-#define EMAC_TLPIEN_S  0
-
-#define EMAC_GMACLPITIMERSCONTROL_REG          (DR_REG_EMAC_BASE + 0x1034)
-/* EMAC_LPI_LS_TIMER : R/W ;bitpos:[25:16] ;default: 10'h3E8 ; */
-/*description: This field specifies the minimum time (in milliseconds) for which
- the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard.*/
-#define EMAC_LPI_LS_TIMER  0x000003FF
-#define EMAC_LPI_LS_TIMER_M  ((EMAC_LPI_LS_TIMER_V)<<(EMAC_LPI_LS_TIMER_S))
-#define EMAC_LPI_LS_TIMER_V  0x3FF
-#define EMAC_LPI_LS_TIMER_S  16
-/* EMAC_LPI_TW_TIMER : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This field specifies the minimum time (in microseconds) for which
- the MAC waits  after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.*/
-#define EMAC_LPI_TW_TIMER  0x0000FFFF
-#define EMAC_LPI_TW_TIMER_M  ((EMAC_LPI_TW_TIMER_V)<<(EMAC_LPI_TW_TIMER_S))
-#define EMAC_LPI_TW_TIMER_V  0xFFFF
-#define EMAC_LPI_TW_TIMER_S  0
-
-#define EMAC_INTS_REG          (DR_REG_EMAC_BASE + 0x1038)
-/* EMAC_LPIIS : RO ;bitpos:[10] ;default: 1'h0 ; */
-/*description: When the Energy Efficient Ethernet feature is enabled  this bit
- is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register).*/
-#define EMAC_LPIIS  (BIT(10))
-#define EMAC_LPIIS_M  (BIT(10))
-#define EMAC_LPIIS_V  0x1
-#define EMAC_LPIIS_S  10
-/* EMAC_PMTINTS : RO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: This bit is set when a magic packet or remote wake-up frame is
- received in the power-down mode (see Bit[5] and Bit[6] in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit is valid only when you select the optional PMT module during core configuration.*/
-#define EMAC_PMTINTS  (BIT(3))
-#define EMAC_PMTINTS_M  (BIT(3))
-#define EMAC_PMTINTS_V  0x1
-#define EMAC_PMTINTS_S  3
-
-#define EMAC_INTMASK_REG          (DR_REG_EMAC_BASE + 0x103C)
-/* EMAC_LPIINTMASK : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: When set  this bit disables the assertion of the interrupt signal
- because of the setting of the LPI Interrupt Status bit in Register (Interrupt Status Register).*/
-#define EMAC_LPIINTMASK  (BIT(10))
-#define EMAC_LPIINTMASK_M  (BIT(10))
-#define EMAC_LPIINTMASK_V  0x1
-#define EMAC_LPIINTMASK_S  10
-/* EMAC_PMTINTMASK : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: When set  this bit disables the assertion of the interrupt signal
- because of the setting of PMT Interrupt Status bit in Register (Interrupt Status Register).*/
-#define EMAC_PMTINTMASK  (BIT(3))
-#define EMAC_PMTINTMASK_M  (BIT(3))
-#define EMAC_PMTINTMASK_V  0x1
-#define EMAC_PMTINTMASK_S  3
-
-#define EMAC_ADDR0HIGH_REG          (DR_REG_EMAC_BASE + 0x1040)
-/* EMAC_ADDRESS_ENABLE0 : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: This bit is always set to 1.*/
-#define EMAC_ADDRESS_ENABLE0  (BIT(31))
-#define EMAC_ADDRESS_ENABLE0_M  (BIT(31))
-#define EMAC_ADDRESS_ENABLE0_V  0x1
-#define EMAC_ADDRESS_ENABLE0_S  31
-/* EMAC_ADDRESS0_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */
-/*description: This field contains the upper 16 bits (47:32) of the first 6-byte
- MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
-#define EMAC_ADDRESS0_HI  0x0000FFFF
-#define EMAC_ADDRESS0_HI_M  ((EMAC_ADDRESS0_HI_V)<<(EMAC_ADDRESS0_HI_S))
-#define EMAC_ADDRESS0_HI_V  0xFFFF
-#define EMAC_ADDRESS0_HI_S  0
-
-#define EMAC_ADDR0LOW_REG          (DR_REG_EMAC_BASE + 0x1044)
-/* EMAC_MAC_ADDRESS0_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */
-/*description: This field contains the lower 32 bits of the first 6-byte MAC
- address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
-#define EMAC_MAC_ADDRESS0_LOW  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS0_LOW_M  ((EMAC_MAC_ADDRESS0_LOW_V)<<(EMAC_MAC_ADDRESS0_LOW_S))
-#define EMAC_MAC_ADDRESS0_LOW_V  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS0_LOW_S  0
-
-#define EMAC_ADDR1HIGH_REG          (DR_REG_EMAC_BASE + 0x1048)
-/* EMAC_ADDRESS_ENABLE1 : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When this bit is set  the address filter module uses the second
- MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering.*/
-#define EMAC_ADDRESS_ENABLE1  (BIT(31))
-#define EMAC_ADDRESS_ENABLE1_M  (BIT(31))
-#define EMAC_ADDRESS_ENABLE1_V  0x1
-#define EMAC_ADDRESS_ENABLE1_S  31
-/* EMAC_SOURCE_ADDRESS : R/W ;bitpos:[30] ;default: 1'h0 ; */
-/*description: When this bit is set  the EMACADDR1[47:0] is used to compare
- with the SA fields of the received frame. When this bit is reset  the EMACADDR1[47:0] is used to compare with the DA fields of the received frame.*/
-#define EMAC_SOURCE_ADDRESS  (BIT(30))
-#define EMAC_SOURCE_ADDRESS_M  (BIT(30))
-#define EMAC_SOURCE_ADDRESS_V  0x1
-#define EMAC_SOURCE_ADDRESS_S  30
-/* EMAC_MASK_BYTE_CONTROL : R/W ;bitpos:[29:24] ;default: 6'h0 ; */
-/*description: These bits are mask control bits for comparison of each of the
- EMACADDR1 bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR1 registers. Each bit controls the masking of the bytes as follows:  Bit[29]: EMACADDR1 High [15:8].  Bit[28]: EMACADDR1 High [7:0].  Bit[27]: EMACADDR1 Low [31:24].  Bit[24]: EMACADDR1 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
-#define EMAC_MASK_BYTE_CONTROL  0x0000003F
-#define EMAC_MASK_BYTE_CONTROL_M  ((EMAC_MASK_BYTE_CONTROL_V)<<(EMAC_MASK_BYTE_CONTROL_S))
-#define EMAC_MASK_BYTE_CONTROL_V  0x3F
-#define EMAC_MASK_BYTE_CONTROL_S  24
-/* EMAC_MAC_ADDRESS1_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */
-/*description: This field contains the upper 16 bits  Bits[47:32] of the second
- 6-byte MAC Address.*/
-#define EMAC_MAC_ADDRESS1_HI  0x0000FFFF
-#define EMAC_MAC_ADDRESS1_HI_M  ((EMAC_MAC_ADDRESS1_HI_V)<<(EMAC_MAC_ADDRESS1_HI_S))
-#define EMAC_MAC_ADDRESS1_HI_V  0xFFFF
-#define EMAC_MAC_ADDRESS1_HI_S  0
-
-#define EMAC_ADDR1LOW_REG          (DR_REG_EMAC_BASE + 0x104C)
-/* EMAC_MAC_ADDRESS1_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */
-/*description: This field contains the lower 32 bits of the second 6-byte MAC
- address.The content of this field is undefined  so the register needs to be configured after the initialization Process.*/
-#define EMAC_MAC_ADDRESS1_LOW  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS1_LOW_M  ((EMAC_MAC_ADDRESS1_LOW_V)<<(EMAC_MAC_ADDRESS1_LOW_S))
-#define EMAC_MAC_ADDRESS1_LOW_V  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS1_LOW_S  0
-
-#define EMAC_ADDR2HIGH_REG          (DR_REG_EMAC_BASE + 0x1050)
-/* EMAC_ADDRESS_ENABLE2 : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When this bit is set  the address filter module uses the third
- MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering.*/
-#define EMAC_ADDRESS_ENABLE2  (BIT(31))
-#define EMAC_ADDRESS_ENABLE2_M  (BIT(31))
-#define EMAC_ADDRESS_ENABLE2_V  0x1
-#define EMAC_ADDRESS_ENABLE2_S  31
-/* EMAC_SOURCE_ADDRESS2 : R/W ;bitpos:[30] ;default: 1'h0 ; */
-/*description: When this bit is set  the EMACADDR2[47:0] is used to compare
- with the SA fields of the received frame. When this bit is reset  the EMACADDR2[47:0] is used to compare with the DA fields of the received frame.*/
-#define EMAC_SOURCE_ADDRESS2  (BIT(30))
-#define EMAC_SOURCE_ADDRESS2_M  (BIT(30))
-#define EMAC_SOURCE_ADDRESS2_V  0x1
-#define EMAC_SOURCE_ADDRESS2_S  30
-/* EMAC_MASK_BYTE_CONTROL2 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */
-/*description: These bits are mask control bits for comparison of each of the
- EMACADDR2 bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR2 registers. Each bit controls the masking of the bytes as follows:  Bit[29]: EMACADDR2 High [15:8].  Bit[28]: EMACADDR2 High [7:0].  Bit[27]: EMACADDR2 Low [31:24].  Bit[24]: EMACADDR2 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
-#define EMAC_MASK_BYTE_CONTROL2  0x0000003F
-#define EMAC_MASK_BYTE_CONTROL2_M  ((EMAC_MASK_BYTE_CONTROL2_V)<<(EMAC_MASK_BYTE_CONTROL2_S))
-#define EMAC_MASK_BYTE_CONTROL2_V  0x3F
-#define EMAC_MASK_BYTE_CONTROL2_S  24
-/* EMAC_MAC_ADDRESS2_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */
-/*description: This field contains the upper 16 bits  Bits[47:32] of the third
- 6-byte MAC address.*/
-#define EMAC_MAC_ADDRESS2_HI  0x0000FFFF
-#define EMAC_MAC_ADDRESS2_HI_M  ((EMAC_MAC_ADDRESS2_HI_V)<<(EMAC_MAC_ADDRESS2_HI_S))
-#define EMAC_MAC_ADDRESS2_HI_V  0xFFFF
-#define EMAC_MAC_ADDRESS2_HI_S  0
-
-#define EMAC_ADDR2LOW_REG          (DR_REG_EMAC_BASE + 0x1054)
-/* EMAC_MAC_ADDRESS2_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */
-/*description: This field contains the lower 32 bits of the third 6-byte MAC
- address. The content of this field is undefined  so the register needs to be configured after the initialization process.*/
-#define EMAC_MAC_ADDRESS2_LOW  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS2_LOW_M  ((EMAC_MAC_ADDRESS2_LOW_V)<<(EMAC_MAC_ADDRESS2_LOW_S))
-#define EMAC_MAC_ADDRESS2_LOW_V  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS2_LOW_S  0
-
-#define EMAC_ADDR3HIGH_REG          (DR_REG_EMAC_BASE + 0x1058)
-/* EMAC_ADDRESS_ENABLE3 : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When this bit is set  the address filter module uses the fourth
- MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering.*/
-#define EMAC_ADDRESS_ENABLE3  (BIT(31))
-#define EMAC_ADDRESS_ENABLE3_M  (BIT(31))
-#define EMAC_ADDRESS_ENABLE3_V  0x1
-#define EMAC_ADDRESS_ENABLE3_S  31
-/* EMAC_SOURCE_ADDRESS3 : R/W ;bitpos:[30] ;default: 1'h0 ; */
-/*description: When this bit is set  the EMACADDR3[47:0] is used to compare
- with the SA fields of the received frame. When this bit is reset  the EMACADDR3[47:0] is used to compare with the DA fields of the received frame.*/
-#define EMAC_SOURCE_ADDRESS3  (BIT(30))
-#define EMAC_SOURCE_ADDRESS3_M  (BIT(30))
-#define EMAC_SOURCE_ADDRESS3_V  0x1
-#define EMAC_SOURCE_ADDRESS3_S  30
-/* EMAC_MASK_BYTE_CONTROL3 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */
-/*description: These bits are mask control bits for comparison of each of the
- EMACADDR3 bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR3 registers. Each bit controls the masking of the bytes as follows:  Bit[29]: EMACADDR3 High [15:8].  Bit[28]: EMACADDR3 High [7:0].  Bit[27]: EMACADDR3 Low [31:24].  Bit[24]: EMACADDR3 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
-#define EMAC_MASK_BYTE_CONTROL3  0x0000003F
-#define EMAC_MASK_BYTE_CONTROL3_M  ((EMAC_MASK_BYTE_CONTROL3_V)<<(EMAC_MASK_BYTE_CONTROL3_S))
-#define EMAC_MASK_BYTE_CONTROL3_V  0x3F
-#define EMAC_MASK_BYTE_CONTROL3_S  24
-/* EMAC_MAC_ADDRESS3_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */
-/*description: This field contains the upper 16 bits  Bits[47:32] of the fourth
- 6-byte MAC address.*/
-#define EMAC_MAC_ADDRESS3_HI  0x0000FFFF
-#define EMAC_MAC_ADDRESS3_HI_M  ((EMAC_MAC_ADDRESS3_HI_V)<<(EMAC_MAC_ADDRESS3_HI_S))
-#define EMAC_MAC_ADDRESS3_HI_V  0xFFFF
-#define EMAC_MAC_ADDRESS3_HI_S  0
-
-#define EMAC_ADDR3LOW_REG          (DR_REG_EMAC_BASE + 0x105C)
-/* EMAC_MAC_ADDRESS3_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */
-/*description: This field contains the lower 32 bits of the fourth 6-byte MAC
- address.The content of this field is undefined  so the register needs to be configured after the initialization Process.*/
-#define EMAC_MAC_ADDRESS3_LOW  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS3_LOW_M  ((EMAC_MAC_ADDRESS3_LOW_V)<<(EMAC_MAC_ADDRESS3_LOW_S))
-#define EMAC_MAC_ADDRESS3_LOW_V  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS3_LOW_S  0
-
-#define EMAC_ADDR4HIGH_REG          (DR_REG_EMAC_BASE + 0x1060)
-/* EMAC_ADDRESS_ENABLE4 : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When this bit is set  the address filter module uses the fifth
- MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering.*/
-#define EMAC_ADDRESS_ENABLE4  (BIT(31))
-#define EMAC_ADDRESS_ENABLE4_M  (BIT(31))
-#define EMAC_ADDRESS_ENABLE4_V  0x1
-#define EMAC_ADDRESS_ENABLE4_S  31
-/* EMAC_SOURCE_ADDRESS4 : R/W ;bitpos:[30] ;default: 1'h0 ; */
-/*description: When this bit is set  the EMACADDR4[47:0] is used to compare
- with the SA fields of the received frame. When this bit is reset  the EMACADDR4[47:0] is used to compare with the DA fields of the received frame.*/
-#define EMAC_SOURCE_ADDRESS4  (BIT(30))
-#define EMAC_SOURCE_ADDRESS4_M  (BIT(30))
-#define EMAC_SOURCE_ADDRESS4_V  0x1
-#define EMAC_SOURCE_ADDRESS4_S  30
-/* EMAC_MASK_BYTE_CONTROL4 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */
-/*description: These bits are mask control bits for comparison of each of the
- EMACADDR4 bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR4 registers. Each bit controls the masking of the bytes as follows:  Bit[29]: EMACADDR4 High [15:8].  Bit[28]: EMACADDR4 High [7:0].  Bit[27]: EMACADDR4 Low [31:24].  Bit[24]: EMACADDR4 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
-#define EMAC_MASK_BYTE_CONTROL4  0x0000003F
-#define EMAC_MASK_BYTE_CONTROL4_M  ((EMAC_MASK_BYTE_CONTROL4_V)<<(EMAC_MASK_BYTE_CONTROL4_S))
-#define EMAC_MASK_BYTE_CONTROL4_V  0x3F
-#define EMAC_MASK_BYTE_CONTROL4_S  24
-/* EMAC_MAC_ADDRESS4_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */
-/*description: This field contains the upper 16 bits  Bits[47:32] of the fifth
- 6-byte MAC address.*/
-#define EMAC_MAC_ADDRESS4_HI  0x0000FFFF
-#define EMAC_MAC_ADDRESS4_HI_M  ((EMAC_MAC_ADDRESS4_HI_V)<<(EMAC_MAC_ADDRESS4_HI_S))
-#define EMAC_MAC_ADDRESS4_HI_V  0xFFFF
-#define EMAC_MAC_ADDRESS4_HI_S  0
-
-#define EMAC_ADDR4LOW_REG          (DR_REG_EMAC_BASE + 0x1064)
-/* EMAC_MAC_ADDRESS4_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */
-/*description: This field contains the lower 32 bits of the fifth 6-byte MAC
- address. The content of this field is undefined  so the register needs to be configured after the initialization process.*/
-#define EMAC_MAC_ADDRESS4_LOW  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS4_LOW_M  ((EMAC_MAC_ADDRESS4_LOW_V)<<(EMAC_MAC_ADDRESS4_LOW_S))
-#define EMAC_MAC_ADDRESS4_LOW_V  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS4_LOW_S  0
-
-#define EMAC_ADDR5HIGH_REG          (DR_REG_EMAC_BASE + 0x1068)
-/* EMAC_ADDRESS_ENABLE5 : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When this bit is set  the address filter module uses the sixth
- MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering.*/
-#define EMAC_ADDRESS_ENABLE5  (BIT(31))
-#define EMAC_ADDRESS_ENABLE5_M  (BIT(31))
-#define EMAC_ADDRESS_ENABLE5_V  0x1
-#define EMAC_ADDRESS_ENABLE5_S  31
-/* EMAC_SOURCE_ADDRESS5 : R/W ;bitpos:[30] ;default: 1'h0 ; */
-/*description: When this bit is set  the EMACADDR5[47:0] is used to compare
- with the SA fields of the received frame. When this bit is reset  the EMACADDR5[47:0] is used to compare with the DA fields of the received frame.*/
-#define EMAC_SOURCE_ADDRESS5  (BIT(30))
-#define EMAC_SOURCE_ADDRESS5_M  (BIT(30))
-#define EMAC_SOURCE_ADDRESS5_V  0x1
-#define EMAC_SOURCE_ADDRESS5_S  30
-/* EMAC_MASK_BYTE_CONTROL5 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */
-/*description: These bits are mask control bits for comparison of each of the
- EMACADDR5 bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR5 registers. Each bit controls the masking of the bytes as follows:  Bit[29]: EMACADDR5 High [15:8].  Bit[28]: EMACADDR5 High [7:0].  Bit[27]: EMACADDR5 Low [31:24].  Bit[24]: EMACADDR5 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
-#define EMAC_MASK_BYTE_CONTROL5  0x0000003F
-#define EMAC_MASK_BYTE_CONTROL5_M  ((EMAC_MASK_BYTE_CONTROL5_V)<<(EMAC_MASK_BYTE_CONTROL5_S))
-#define EMAC_MASK_BYTE_CONTROL5_V  0x3F
-#define EMAC_MASK_BYTE_CONTROL5_S  24
-/* EMAC_MAC_ADDRESS5_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */
-/*description: This field contains the upper 16 bits  Bits[47:32] of the sixth
- 6-byte MAC address.*/
-#define EMAC_MAC_ADDRESS5_HI  0x0000FFFF
-#define EMAC_MAC_ADDRESS5_HI_M  ((EMAC_MAC_ADDRESS5_HI_V)<<(EMAC_MAC_ADDRESS5_HI_S))
-#define EMAC_MAC_ADDRESS5_HI_V  0xFFFF
-#define EMAC_MAC_ADDRESS5_HI_S  0
-
-#define EMAC_ADDR5LOW_REG          (DR_REG_EMAC_BASE + 0x106C)
-/* EMAC_MAC_ADDRESS5_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */
-/*description: This field contains the lower 32 bits of the sixth 6-byte MAC
- address. The content of this field is undefined  so the register needs to be configured after the initialization process.*/
-#define EMAC_MAC_ADDRESS5_LOW  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS5_LOW_M  ((EMAC_MAC_ADDRESS5_LOW_V)<<(EMAC_MAC_ADDRESS5_LOW_S))
-#define EMAC_MAC_ADDRESS5_LOW_V  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS5_LOW_S  0
-
-#define EMAC_ADDR6HIGH_REG          (DR_REG_EMAC_BASE + 0x1070)
-/* EMAC_ADDRESS_ENABLE6 : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When this bit is set  the address filter module uses the seventh
- MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering.*/
-#define EMAC_ADDRESS_ENABLE6  (BIT(31))
-#define EMAC_ADDRESS_ENABLE6_M  (BIT(31))
-#define EMAC_ADDRESS_ENABLE6_V  0x1
-#define EMAC_ADDRESS_ENABLE6_S  31
-/* EMAC_SOURCE_ADDRESS6 : R/W ;bitpos:[30] ;default: 1'h0 ; */
-/*description: When this bit is set  the EMACADDR6[47:0] is used to compare
- with the SA fields of the received frame. When this bit is reset  the EMACADDR6[47:0] is used to compare with the DA fields of the received frame.*/
-#define EMAC_SOURCE_ADDRESS6  (BIT(30))
-#define EMAC_SOURCE_ADDRESS6_M  (BIT(30))
-#define EMAC_SOURCE_ADDRESS6_V  0x1
-#define EMAC_SOURCE_ADDRESS6_S  30
-/* EMAC_MASK_BYTE_CONTROL6 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */
-/*description: These bits are mask control bits for comparison of each of the
- EMACADDR6 bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR6 registers. Each bit controls the masking of the bytes as follows:  Bit[29]: EMACADDR6 High [15:8].  Bit[28]: EMACADDR6 High [7:0].  Bit[27]: EMACADDR6 Low [31:24].  Bit[24]: EMACADDR6 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
-#define EMAC_MASK_BYTE_CONTROL6  0x0000003F
-#define EMAC_MASK_BYTE_CONTROL6_M  ((EMAC_MASK_BYTE_CONTROL6_V)<<(EMAC_MASK_BYTE_CONTROL6_S))
-#define EMAC_MASK_BYTE_CONTROL6_V  0x3F
-#define EMAC_MASK_BYTE_CONTROL6_S  24
-/* EMAC_MAC_ADDRESS6_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */
-/*description: This field contains the upper 16 bits  Bits[47:32] of the seventh
- 6-byte MAC Address.*/
-#define EMAC_MAC_ADDRESS6_HI  0x0000FFFF
-#define EMAC_MAC_ADDRESS6_HI_M  ((EMAC_MAC_ADDRESS6_HI_V)<<(EMAC_MAC_ADDRESS6_HI_S))
-#define EMAC_MAC_ADDRESS6_HI_V  0xFFFF
-#define EMAC_MAC_ADDRESS6_HI_S  0
-
-#define EMAC_ADDR6LOW_REG          (DR_REG_EMAC_BASE + 0x1074)
-/* EMAC_MAC_ADDRESS6_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */
-/*description: This field contains the lower 32 bits of the seventh 6-byte MAC
- address.The content of this field is undefined  so the register needs to be configured after the initialization Process.*/
-#define EMAC_MAC_ADDRESS6_LOW  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS6_LOW_M  ((EMAC_MAC_ADDRESS6_LOW_V)<<(EMAC_MAC_ADDRESS6_LOW_S))
-#define EMAC_MAC_ADDRESS6_LOW_V  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS6_LOW_S  0
-
-#define EMAC_ADDR7HIGH_REG          (DR_REG_EMAC_BASE + 0x1078)
-/* EMAC_ADDRESS_ENABLE7 : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When this bit is set  the address filter module uses the eighth
- MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering.*/
-#define EMAC_ADDRESS_ENABLE7  (BIT(31))
-#define EMAC_ADDRESS_ENABLE7_M  (BIT(31))
-#define EMAC_ADDRESS_ENABLE7_V  0x1
-#define EMAC_ADDRESS_ENABLE7_S  31
-/* EMAC_SOURCE_ADDRESS7 : R/W ;bitpos:[30] ;default: 1'h0 ; */
-/*description: When this bit is set  the EMACADDR7[47:0] is used to compare
- with the SA fields of the received frame. When this bit is reset  the EMACADDR7[47:0] is used to compare with the DA fields of the received frame.*/
-#define EMAC_SOURCE_ADDRESS7  (BIT(30))
-#define EMAC_SOURCE_ADDRESS7_M  (BIT(30))
-#define EMAC_SOURCE_ADDRESS7_V  0x1
-#define EMAC_SOURCE_ADDRESS7_S  30
-/* EMAC_MASK_BYTE_CONTROL7 : R/W ;bitpos:[29:24] ;default: 6'h0 ; */
-/*description: These bits are mask control bits for comparison of each of the
- EMACADDR7 bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR7 registers. Each bit controls the masking of the bytes as follows:  Bit[29]: EMACADDR7 High [15:8].  Bit[28]: EMACADDR7 High [7:0].  Bit[27]: EMACADDR7 Low [31:24].  Bit[24]: EMACADDR7 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
-#define EMAC_MASK_BYTE_CONTROL7  0x0000003F
-#define EMAC_MASK_BYTE_CONTROL7_M  ((EMAC_MASK_BYTE_CONTROL7_V)<<(EMAC_MASK_BYTE_CONTROL7_S))
-#define EMAC_MASK_BYTE_CONTROL7_V  0x3F
-#define EMAC_MASK_BYTE_CONTROL7_S  24
-/* EMAC_MAC_ADDRESS7_HI : R/W ;bitpos:[15:0] ;default: 16'hFFFF ; */
-/*description: This field contains the upper 16 bits  Bits[47:32] of the eighth
- 6-byte MAC Address.*/
-#define EMAC_MAC_ADDRESS7_HI  0x0000FFFF
-#define EMAC_MAC_ADDRESS7_HI_M  ((EMAC_MAC_ADDRESS7_HI_V)<<(EMAC_MAC_ADDRESS7_HI_S))
-#define EMAC_MAC_ADDRESS7_HI_V  0xFFFF
-#define EMAC_MAC_ADDRESS7_HI_S  0
-
-#define EMAC_ADDR7LOW_REG          (DR_REG_EMAC_BASE + 0x107C)
-/* EMAC_MAC_ADDRESS7_LOW : R/W ;bitpos:[31:0] ;default: 32'hFFFFFFFF ; */
-/*description: This field contains the lower 32 bits of the eighth 6-byte MAC
- address.The content of this field is undefined  so the register needs to be configured after the initialization Process.*/
-#define EMAC_MAC_ADDRESS7_LOW  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS7_LOW_M  ((EMAC_MAC_ADDRESS7_LOW_V)<<(EMAC_MAC_ADDRESS7_LOW_S))
-#define EMAC_MAC_ADDRESS7_LOW_V  0xFFFFFFFF
-#define EMAC_MAC_ADDRESS7_LOW_S  0
-
-#define EMAC_CSTATUS_REG          (DR_REG_EMAC_BASE + 0x10D8)
-/* EMAC_JABBER_TIMEOUT : RO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: This bit indicates whether there is jabber timeout error (1'b1)
- in the received Frame.*/
-#define EMAC_JABBER_TIMEOUT  (BIT(4))
-#define EMAC_JABBER_TIMEOUT_M  (BIT(4))
-#define EMAC_JABBER_TIMEOUT_V  0x1
-#define EMAC_JABBER_TIMEOUT_S  4
-/* EMAC_LINK_SPEED : RO ;bitpos:[2:1] ;default: 1'h0 ; */
-/*description: This bit indicates the current speed of the link:   2'b00: 2.5
- MHz.  2'b01: 25 MHz.  2'b10: 125 MHz.*/
-#define EMAC_LINK_SPEED  0x00000003
-#define EMAC_LINK_SPEED_M  ((EMAC_LINK_SPEED_V)<<(EMAC_LINK_SPEED_S))
-#define EMAC_LINK_SPEED_V  0x3
-#define EMAC_LINK_SPEED_S  1
-/* EMAC_LINK_MODE : RO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: This bit indicates the current mode of operation of the link:
-   1'b0: Half-duplex mode.  1'b1: Full-duplex mode.*/
-#define EMAC_LINK_MODE  (BIT(0))
-#define EMAC_LINK_MODE_M  (BIT(0))
-#define EMAC_LINK_MODE_V  0x1
-#define EMAC_LINK_MODE_S  0
-
-#define EMAC_WDOGTO_REG          (DR_REG_EMAC_BASE + 0x10DC)
-/* EMAC_PWDOGEN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset
-  the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared  the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG.*/
-#define EMAC_PWDOGEN  (BIT(16))
-#define EMAC_PWDOGEN_M  (BIT(16))
-#define EMAC_PWDOGEN_V  0x1
-#define EMAC_PWDOGEN_S  16
-/* EMAC_WDOGTO : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG
- is reset  this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field  such frame is terminated and declared as an error frame.*/
-#define EMAC_WDOGTO  0x00003FFF
-#define EMAC_WDOGTO_M  ((EMAC_WDOGTO_V)<<(EMAC_WDOGTO_S))
-#define EMAC_WDOGTO_V  0x3FFF
-#define EMAC_WDOGTO_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_EMAC_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/fe_reg.h b/tools/sdk/include/soc/soc/fe_reg.h
deleted file mode 100644
index 7705586d7c3..00000000000
--- a/tools/sdk/include/soc/soc/fe_reg.h
+++ /dev/null
@@ -1,41 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "soc/soc.h"
-
-/* Some of the RF frontend control registers.
- * PU/PD fields defined here are used in sleep related functions.
- */
-
-#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
-#define FE_IQ_EST_FORCE_PU (BIT(5))
-#define FE_IQ_EST_FORCE_PU_M (BIT(5))
-#define FE_IQ_EST_FORCE_PU_V 1
-#define FE_IQ_EST_FORCE_PU_S 5
-#define FE_IQ_EST_FORCE_PD (BIT(4))
-#define FE_IQ_EST_FORCE_PD_M (BIT(4))
-#define FE_IQ_EST_FORCE_PD_V 1
-#define FE_IQ_EST_FORCE_PD_S 4
-
-#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
-#define FE2_TX_INF_FORCE_PU (BIT(10))
-#define FE2_TX_INF_FORCE_PU_M (BIT(10))
-#define FE2_TX_INF_FORCE_PU_V 1
-#define FE2_TX_INF_FORCE_PU_S 10
-#define FE2_TX_INF_FORCE_PD (BIT(9))
-#define FE2_TX_INF_FORCE_PD_M (BIT(9))
-#define FE2_TX_INF_FORCE_PD_V 1
-#define FE2_TX_INF_FORCE_PD_S 9
diff --git a/tools/sdk/include/soc/soc/frc_timer_reg.h b/tools/sdk/include/soc/soc/frc_timer_reg.h
deleted file mode 100644
index a2152c5c91a..00000000000
--- a/tools/sdk/include/soc/soc/frc_timer_reg.h
+++ /dev/null
@@ -1,52 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_FRC_TIMER_REG_H_
-#define _SOC_FRC_TIMER_REG_H_
-
-#include "soc.h"
-
-/**
- * These are the register definitions for "legacy" timers
- */
-
-#define REG_FRC_TIMER_BASE(i)           (DR_REG_FRC_TIMER_BASE + i*0x20)
-
-#define FRC_TIMER_LOAD_REG(i)           (REG_FRC_TIMER_BASE(i) + 0x0)   // timer load value (23 bit for i==0, 32 bit for i==1)
-#define FRC_TIMER_LOAD_VALUE(i)         ((i == 0)?0x007FFFFF:0xffffffff)
-#define FRC_TIMER_LOAD_VALUE_S          0
-
-#define FRC_TIMER_COUNT_REG(i)          (REG_FRC_TIMER_BASE(i) + 0x4)   // timer count value (23 bit for i==0, 32 bit for i==1)
-#define FRC_TIMER_COUNT                 ((i == 0)?0x007FFFFF:0xffffffff)
-#define FRC_TIMER_COUNT_S               0
-
-#define FRC_TIMER_CTRL_REG(i)           (REG_FRC_TIMER_BASE(i) + 0x8)
-#define FRC_TIMER_INT_STATUS            (BIT(8))        // interrupt status (RO)
-#define FRC_TIMER_ENABLE                (BIT(7))        // enable timer
-#define FRC_TIMER_AUTOLOAD              (BIT(6))        // enable autoload
-#define FRC_TIMER_PRESCALER             0x00000007
-#define FRC_TIMER_PRESCALER_S           1
-#define FRC_TIMER_PRESCALER_1           (0 << FRC_TIMER_PRESCALER_S)
-#define FRC_TIMER_PRESCALER_16          (2 << FRC_TIMER_PRESCALER_S)
-#define FRC_TIMER_PRESCALER_256         (4 << FRC_TIMER_PRESCALER_S)
-#define FRC_TIMER_LEVEL_INT             (BIT(0))        // 1: level, 0: edge
-
-#define FRC_TIMER_INT_REG(i)            (REG_FRC_TIMER_BASE(i) + 0xC)
-#define FRC_TIMER_INT_CLR               (BIT(0))        // clear interrupt
-
-#define FRC_TIMER_ALARM_REG(i)          (REG_FRC_TIMER_BASE(i) + 0x10)  // timer alarm value; register only present for i == 1
-#define FRC_TIMER_ALARM                 0xFFFFFFFF
-#define FRC_TIMER_ALARM_S               0
-
-#endif //_SOC_FRC_TIMER_REG_H_
diff --git a/tools/sdk/include/soc/soc/gpio_periph.h b/tools/sdk/include/soc/soc/gpio_periph.h
deleted file mode 100644
index 93b23f42772..00000000000
--- a/tools/sdk/include/soc/soc/gpio_periph.h
+++ /dev/null
@@ -1,35 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_GPIO_PERIPH_H
-#define _SOC_GPIO_PERIPH_H
-#include "stdint.h"
-#include "soc/gpio_pins.h"
-#include "soc/io_mux_reg.h"
-#include "soc/gpio_struct.h"
-#include "soc/gpio_reg.h"
-#include "soc/gpio_sig_map.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _SOC_GPIO_PERIPH_H
diff --git a/tools/sdk/include/soc/soc/gpio_pins.h b/tools/sdk/include/soc/soc/gpio_pins.h
deleted file mode 100644
index 6c2bfb7418f..00000000000
--- a/tools/sdk/include/soc/soc/gpio_pins.h
+++ /dev/null
@@ -1,28 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _GPIO_PINS_H
-#define _GPIO_PINS_H
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#define GPIO_PIN_COUNT                  40
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _GPIO_PINS_H
diff --git a/tools/sdk/include/soc/soc/gpio_reg.h b/tools/sdk/include/soc/soc/gpio_reg.h
deleted file mode 100644
index 8168f4ba12b..00000000000
--- a/tools/sdk/include/soc/soc/gpio_reg.h
+++ /dev/null
@@ -1,8238 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_GPIO_REG_H_
-#define _SOC_GPIO_REG_H_
-
-#include "soc.h"
-#define GPIO_BT_SELECT_REG          (DR_REG_GPIO_BASE + 0x0000)
-/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: NA*/
-#define GPIO_BT_SEL  0xFFFFFFFF
-#define GPIO_BT_SEL_M  ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
-#define GPIO_BT_SEL_V  0xFFFFFFFF
-#define GPIO_BT_SEL_S  0
-
-#define GPIO_OUT_REG          (DR_REG_GPIO_BASE + 0x0004)
-/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 output value*/
-#define GPIO_OUT_DATA  0xFFFFFFFF
-#define GPIO_OUT_DATA_M  ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
-#define GPIO_OUT_DATA_V  0xFFFFFFFF
-#define GPIO_OUT_DATA_S  0
-
-#define GPIO_OUT_W1TS_REG          (DR_REG_GPIO_BASE + 0x0008)
-/* GPIO_OUT_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 output value write 1 to set*/
-#define GPIO_OUT_DATA_W1TS  0xFFFFFFFF
-#define GPIO_OUT_DATA_W1TS_M  ((GPIO_OUT_DATA_W1TS_V)<<(GPIO_OUT_DATA_W1TS_S))
-#define GPIO_OUT_DATA_W1TS_V  0xFFFFFFFF
-#define GPIO_OUT_DATA_W1TS_S  0
-
-#define GPIO_OUT_W1TC_REG          (DR_REG_GPIO_BASE + 0x000c)
-/* GPIO_OUT_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 output value write 1 to clear*/
-#define GPIO_OUT_DATA_W1TC  0xFFFFFFFF
-#define GPIO_OUT_DATA_W1TC_M  ((GPIO_OUT_DATA_W1TC_V)<<(GPIO_OUT_DATA_W1TC_S))
-#define GPIO_OUT_DATA_W1TC_V  0xFFFFFFFF
-#define GPIO_OUT_DATA_W1TC_S  0
-
-#define GPIO_OUT1_REG          (DR_REG_GPIO_BASE + 0x0010)
-/* GPIO_OUT1_DATA : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 output value*/
-#define GPIO_OUT1_DATA  0x000000FF
-#define GPIO_OUT1_DATA_M  ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S))
-#define GPIO_OUT1_DATA_V  0xFF
-#define GPIO_OUT1_DATA_S  0
-
-#define GPIO_OUT1_W1TS_REG          (DR_REG_GPIO_BASE + 0x0014)
-/* GPIO_OUT1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 output value write 1 to set*/
-#define GPIO_OUT1_DATA_W1TS  0x000000FF
-#define GPIO_OUT1_DATA_W1TS_M  ((GPIO_OUT1_DATA_W1TS_V)<<(GPIO_OUT1_DATA_W1TS_S))
-#define GPIO_OUT1_DATA_W1TS_V  0xFF
-#define GPIO_OUT1_DATA_W1TS_S  0
-
-#define GPIO_OUT1_W1TC_REG          (DR_REG_GPIO_BASE + 0x0018)
-/* GPIO_OUT1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 output value write 1 to clear*/
-#define GPIO_OUT1_DATA_W1TC  0x000000FF
-#define GPIO_OUT1_DATA_W1TC_M  ((GPIO_OUT1_DATA_W1TC_V)<<(GPIO_OUT1_DATA_W1TC_S))
-#define GPIO_OUT1_DATA_W1TC_V  0xFF
-#define GPIO_OUT1_DATA_W1TC_S  0
-
-#define GPIO_SDIO_SELECT_REG          (DR_REG_GPIO_BASE + 0x001c)
-/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: SDIO PADS on/off control from outside*/
-#define GPIO_SDIO_SEL  0x000000FF
-#define GPIO_SDIO_SEL_M  ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S))
-#define GPIO_SDIO_SEL_V  0xFF
-#define GPIO_SDIO_SEL_S  0
-
-#define GPIO_ENABLE_REG          (DR_REG_GPIO_BASE + 0x0020)
-/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 output enable*/
-#define GPIO_ENABLE_DATA  0xFFFFFFFF
-#define GPIO_ENABLE_DATA_M  ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
-#define GPIO_ENABLE_DATA_V  0xFFFFFFFF
-#define GPIO_ENABLE_DATA_S  0
-
-#define GPIO_ENABLE_W1TS_REG          (DR_REG_GPIO_BASE + 0x0024)
-/* GPIO_ENABLE_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 output enable write 1 to set*/
-#define GPIO_ENABLE_DATA_W1TS  0xFFFFFFFF
-#define GPIO_ENABLE_DATA_W1TS_M  ((GPIO_ENABLE_DATA_W1TS_V)<<(GPIO_ENABLE_DATA_W1TS_S))
-#define GPIO_ENABLE_DATA_W1TS_V  0xFFFFFFFF
-#define GPIO_ENABLE_DATA_W1TS_S  0
-
-#define GPIO_ENABLE_W1TC_REG          (DR_REG_GPIO_BASE + 0x0028)
-/* GPIO_ENABLE_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 output enable write 1 to clear*/
-#define GPIO_ENABLE_DATA_W1TC  0xFFFFFFFF
-#define GPIO_ENABLE_DATA_W1TC_M  ((GPIO_ENABLE_DATA_W1TC_V)<<(GPIO_ENABLE_DATA_W1TC_S))
-#define GPIO_ENABLE_DATA_W1TC_V  0xFFFFFFFF
-#define GPIO_ENABLE_DATA_W1TC_S  0
-
-#define GPIO_ENABLE1_REG          (DR_REG_GPIO_BASE + 0x002c)
-/* GPIO_ENABLE1_DATA : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 output enable*/
-#define GPIO_ENABLE1_DATA  0x000000FF
-#define GPIO_ENABLE1_DATA_M  ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S))
-#define GPIO_ENABLE1_DATA_V  0xFF
-#define GPIO_ENABLE1_DATA_S  0
-
-#define GPIO_ENABLE1_W1TS_REG          (DR_REG_GPIO_BASE + 0x0030)
-/* GPIO_ENABLE1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 output enable write 1 to set*/
-#define GPIO_ENABLE1_DATA_W1TS  0x000000FF
-#define GPIO_ENABLE1_DATA_W1TS_M  ((GPIO_ENABLE1_DATA_W1TS_V)<<(GPIO_ENABLE1_DATA_W1TS_S))
-#define GPIO_ENABLE1_DATA_W1TS_V  0xFF
-#define GPIO_ENABLE1_DATA_W1TS_S  0
-
-#define GPIO_ENABLE1_W1TC_REG          (DR_REG_GPIO_BASE + 0x0034)
-/* GPIO_ENABLE1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 output enable write 1 to clear*/
-#define GPIO_ENABLE1_DATA_W1TC  0x000000FF
-#define GPIO_ENABLE1_DATA_W1TC_M  ((GPIO_ENABLE1_DATA_W1TC_V)<<(GPIO_ENABLE1_DATA_W1TC_S))
-#define GPIO_ENABLE1_DATA_W1TC_V  0xFF
-#define GPIO_ENABLE1_DATA_W1TC_S  0
-
-#define GPIO_STRAP_REG          (DR_REG_GPIO_BASE + 0x0038)
-/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default:  ; */
-/*description: {10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5} */
-#define GPIO_STRAPPING  0x0000FFFF
-#define GPIO_STRAPPING_M  ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
-#define GPIO_STRAPPING_V  0xFFFF
-#define GPIO_STRAPPING_S  0
-
-#define GPIO_IN_REG          (DR_REG_GPIO_BASE + 0x003c)
-/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default:  ; */
-/*description: GPIO0~31 input value*/
-#define GPIO_IN_DATA  0xFFFFFFFF
-#define GPIO_IN_DATA_M  ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S))
-#define GPIO_IN_DATA_V  0xFFFFFFFF
-#define GPIO_IN_DATA_S  0
-
-#define GPIO_IN1_REG          (DR_REG_GPIO_BASE + 0x0040)
-/* GPIO_IN1_DATA : RO ;bitpos:[7:0] ;default:  ; */
-/*description: GPIO32~39 input value*/
-#define GPIO_IN1_DATA  0x000000FF
-#define GPIO_IN1_DATA_M  ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S))
-#define GPIO_IN1_DATA_V  0xFF
-#define GPIO_IN1_DATA_S  0
-
-#define GPIO_STATUS_REG          (DR_REG_GPIO_BASE + 0x0044)
-/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 interrupt status*/
-#define GPIO_STATUS_INT  0xFFFFFFFF
-#define GPIO_STATUS_INT_M  ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S))
-#define GPIO_STATUS_INT_V  0xFFFFFFFF
-#define GPIO_STATUS_INT_S  0
-
-#define GPIO_STATUS_W1TS_REG          (DR_REG_GPIO_BASE + 0x0048)
-/* GPIO_STATUS_INT_W1TS : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 interrupt status write 1 to set*/
-#define GPIO_STATUS_INT_W1TS  0xFFFFFFFF
-#define GPIO_STATUS_INT_W1TS_M  ((GPIO_STATUS_INT_W1TS_V)<<(GPIO_STATUS_INT_W1TS_S))
-#define GPIO_STATUS_INT_W1TS_V  0xFFFFFFFF
-#define GPIO_STATUS_INT_W1TS_S  0
-
-#define GPIO_STATUS_W1TC_REG          (DR_REG_GPIO_BASE + 0x004c)
-/* GPIO_STATUS_INT_W1TC : R/W ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 interrupt status write 1 to clear*/
-#define GPIO_STATUS_INT_W1TC  0xFFFFFFFF
-#define GPIO_STATUS_INT_W1TC_M  ((GPIO_STATUS_INT_W1TC_V)<<(GPIO_STATUS_INT_W1TC_S))
-#define GPIO_STATUS_INT_W1TC_V  0xFFFFFFFF
-#define GPIO_STATUS_INT_W1TC_S  0
-
-#define GPIO_STATUS1_REG          (DR_REG_GPIO_BASE + 0x0050)
-/* GPIO_STATUS1_INT : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 interrupt status*/
-#define GPIO_STATUS1_INT  0x000000FF
-#define GPIO_STATUS1_INT_M  ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S))
-#define GPIO_STATUS1_INT_V  0xFF
-#define GPIO_STATUS1_INT_S  0
-
-#define GPIO_STATUS1_W1TS_REG          (DR_REG_GPIO_BASE + 0x0054)
-/* GPIO_STATUS1_INT_W1TS : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 interrupt status write 1 to set*/
-#define GPIO_STATUS1_INT_W1TS  0x000000FF
-#define GPIO_STATUS1_INT_W1TS_M  ((GPIO_STATUS1_INT_W1TS_V)<<(GPIO_STATUS1_INT_W1TS_S))
-#define GPIO_STATUS1_INT_W1TS_V  0xFF
-#define GPIO_STATUS1_INT_W1TS_S  0
-
-#define GPIO_STATUS1_W1TC_REG          (DR_REG_GPIO_BASE + 0x0058)
-/* GPIO_STATUS1_INT_W1TC : R/W ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 interrupt status write 1 to clear*/
-#define GPIO_STATUS1_INT_W1TC  0x000000FF
-#define GPIO_STATUS1_INT_W1TC_M  ((GPIO_STATUS1_INT_W1TC_V)<<(GPIO_STATUS1_INT_W1TC_S))
-#define GPIO_STATUS1_INT_W1TC_V  0xFF
-#define GPIO_STATUS1_INT_W1TC_S  0
-
-#define GPIO_ACPU_INT_REG          (DR_REG_GPIO_BASE + 0x0060)
-/* GPIO_APPCPU_INT : RO ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 APP CPU interrupt status*/
-#define GPIO_APPCPU_INT  0xFFFFFFFF
-#define GPIO_APPCPU_INT_M  ((GPIO_APPCPU_INT_V)<<(GPIO_APPCPU_INT_S))
-#define GPIO_APPCPU_INT_V  0xFFFFFFFF
-#define GPIO_APPCPU_INT_S  0
-
-#define GPIO_ACPU_NMI_INT_REG          (DR_REG_GPIO_BASE + 0x0064)
-/* GPIO_APPCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 APP CPU non-maskable interrupt status*/
-#define GPIO_APPCPU_NMI_INT  0xFFFFFFFF
-#define GPIO_APPCPU_NMI_INT_M  ((GPIO_APPCPU_NMI_INT_V)<<(GPIO_APPCPU_NMI_INT_S))
-#define GPIO_APPCPU_NMI_INT_V  0xFFFFFFFF
-#define GPIO_APPCPU_NMI_INT_S  0
-
-#define GPIO_PCPU_INT_REG          (DR_REG_GPIO_BASE + 0x0068)
-/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 PRO CPU interrupt status*/
-#define GPIO_PROCPU_INT  0xFFFFFFFF
-#define GPIO_PROCPU_INT_M  ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S))
-#define GPIO_PROCPU_INT_V  0xFFFFFFFF
-#define GPIO_PROCPU_INT_S  0
-
-#define GPIO_PCPU_NMI_INT_REG          (DR_REG_GPIO_BASE + 0x006c)
-/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */
-/*description: GPIO0~31 PRO CPU non-maskable interrupt status*/
-#define GPIO_PROCPU_NMI_INT  0xFFFFFFFF
-#define GPIO_PROCPU_NMI_INT_M  ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
-#define GPIO_PROCPU_NMI_INT_V  0xFFFFFFFF
-#define GPIO_PROCPU_NMI_INT_S  0
-
-#define GPIO_CPUSDIO_INT_REG          (DR_REG_GPIO_BASE + 0x0070)
-/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: x ; */
-/*description: SDIO's extent GPIO0~31 interrupt*/
-#define GPIO_SDIO_INT  0xFFFFFFFF
-#define GPIO_SDIO_INT_M  ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S))
-#define GPIO_SDIO_INT_V  0xFFFFFFFF
-#define GPIO_SDIO_INT_S  0
-
-#define GPIO_ACPU_INT1_REG          (DR_REG_GPIO_BASE + 0x0074)
-/* GPIO_APPCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 APP CPU interrupt status*/
-#define GPIO_APPCPU_INT_H  0x000000FF
-#define GPIO_APPCPU_INT_H_M  ((GPIO_APPCPU_INT_H_V)<<(GPIO_APPCPU_INT_H_S))
-#define GPIO_APPCPU_INT_H_V  0xFF
-#define GPIO_APPCPU_INT_H_S  0
-
-#define GPIO_ACPU_NMI_INT1_REG          (DR_REG_GPIO_BASE + 0x0078)
-/* GPIO_APPCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 APP CPU non-maskable interrupt status*/
-#define GPIO_APPCPU_NMI_INT_H  0x000000FF
-#define GPIO_APPCPU_NMI_INT_H_M  ((GPIO_APPCPU_NMI_INT_H_V)<<(GPIO_APPCPU_NMI_INT_H_S))
-#define GPIO_APPCPU_NMI_INT_H_V  0xFF
-#define GPIO_APPCPU_NMI_INT_H_S  0
-
-#define GPIO_PCPU_INT1_REG          (DR_REG_GPIO_BASE + 0x007c)
-/* GPIO_PROCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 PRO CPU interrupt status*/
-#define GPIO_PROCPU_INT_H  0x000000FF
-#define GPIO_PROCPU_INT_H_M  ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S))
-#define GPIO_PROCPU_INT_H_V  0xFF
-#define GPIO_PROCPU_INT_H_S  0
-
-#define GPIO_PCPU_NMI_INT1_REG          (DR_REG_GPIO_BASE + 0x0080)
-/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */
-/*description: GPIO32~39 PRO CPU non-maskable interrupt status*/
-#define GPIO_PROCPU_NMI_INT_H  0x000000FF
-#define GPIO_PROCPU_NMI_INT_H_M  ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S))
-#define GPIO_PROCPU_NMI_INT_H_V  0xFF
-#define GPIO_PROCPU_NMI_INT_H_S  0
-
-#define GPIO_CPUSDIO_INT1_REG          (DR_REG_GPIO_BASE + 0x0084)
-/* GPIO_SDIO_INT_H : RO ;bitpos:[7:0] ;default: x ; */
-/*description: SDIO's extent GPIO32~39 interrupt*/
-#define GPIO_SDIO_INT_H  0x000000FF
-#define GPIO_SDIO_INT_H_M  ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S))
-#define GPIO_SDIO_INT_H_V  0xFF
-#define GPIO_SDIO_INT_H_S  0
-
-#define GPIO_REG(io_num)      (GPIO_PIN0_REG + (io_num)*0x4)
-#define GPIO_PIN_INT_ENA 0x0000001F
-#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S))
-#define GPIO_PIN_INT_ENA_V 0x0000001F
-#define GPIO_PIN_INT_ENA_S 13
-#define GPIO_PIN_CONFIG 0x00000003
-#define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S))
-#define GPIO_PIN_CONFIG_V 0x00000003
-#define GPIO_PIN_CONFIG_S 11
-#define GPIO_PIN_WAKEUP_ENABLE (BIT(10))
-#define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10))
-#define GPIO_PIN_WAKEUP_ENABLE_V 0x1
-#define GPIO_PIN_WAKEUP_ENABLE_S 10
-#define GPIO_PIN_INT_TYPE 0x00000007
-#define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S))
-#define GPIO_PIN_INT_TYPE_V 0x00000007
-#define GPIO_PIN_INT_TYPE_S 7
-#define GPIO_PIN_PAD_DRIVER (BIT(2))
-#define GPIO_PIN_PAD_DRIVER_M (BIT(2))
-#define GPIO_PIN_PAD_DRIVER_V 0x1
-#define GPIO_PIN_PAD_DRIVER_S 2
-
-#define GPIO_PIN0_REG          (DR_REG_GPIO_BASE + 0x0088)
-/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN0_INT_ENA  0x0000001F
-#define GPIO_PIN0_INT_ENA_M  ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
-#define GPIO_PIN0_INT_ENA_V  0x1F
-#define GPIO_PIN0_INT_ENA_S  13
-/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN0_CONFIG  0x00000003
-#define GPIO_PIN0_CONFIG_M  ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S))
-#define GPIO_PIN0_CONFIG_V  0x3
-#define GPIO_PIN0_CONFIG_S  11
-/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN0_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN0_WAKEUP_ENABLE_S  10
-/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN0_INT_TYPE  0x00000007
-#define GPIO_PIN0_INT_TYPE_M  ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S))
-#define GPIO_PIN0_INT_TYPE_V  0x7
-#define GPIO_PIN0_INT_TYPE_S  7
-/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN0_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN0_PAD_DRIVER_V  0x1
-#define GPIO_PIN0_PAD_DRIVER_S  2
-
-#define GPIO_PIN1_REG          (DR_REG_GPIO_BASE + 0x008c)
-/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN1_INT_ENA  0x0000001F
-#define GPIO_PIN1_INT_ENA_M  ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S))
-#define GPIO_PIN1_INT_ENA_V  0x1F
-#define GPIO_PIN1_INT_ENA_S  13
-/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN1_CONFIG  0x00000003
-#define GPIO_PIN1_CONFIG_M  ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
-#define GPIO_PIN1_CONFIG_V  0x3
-#define GPIO_PIN1_CONFIG_S  11
-/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN1_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN1_WAKEUP_ENABLE_S  10
-/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN1_INT_TYPE  0x00000007
-#define GPIO_PIN1_INT_TYPE_M  ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S))
-#define GPIO_PIN1_INT_TYPE_V  0x7
-#define GPIO_PIN1_INT_TYPE_S  7
-/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN1_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN1_PAD_DRIVER_V  0x1
-#define GPIO_PIN1_PAD_DRIVER_S  2
-
-#define GPIO_PIN2_REG          (DR_REG_GPIO_BASE + 0x0090)
-/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN2_INT_ENA  0x0000001F
-#define GPIO_PIN2_INT_ENA_M  ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S))
-#define GPIO_PIN2_INT_ENA_V  0x1F
-#define GPIO_PIN2_INT_ENA_S  13
-/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN2_CONFIG  0x00000003
-#define GPIO_PIN2_CONFIG_M  ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S))
-#define GPIO_PIN2_CONFIG_V  0x3
-#define GPIO_PIN2_CONFIG_S  11
-/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN2_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN2_WAKEUP_ENABLE_S  10
-/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN2_INT_TYPE  0x00000007
-#define GPIO_PIN2_INT_TYPE_M  ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S))
-#define GPIO_PIN2_INT_TYPE_V  0x7
-#define GPIO_PIN2_INT_TYPE_S  7
-/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN2_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN2_PAD_DRIVER_V  0x1
-#define GPIO_PIN2_PAD_DRIVER_S  2
-
-#define GPIO_PIN3_REG          (DR_REG_GPIO_BASE + 0x0094)
-/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN3_INT_ENA  0x0000001F
-#define GPIO_PIN3_INT_ENA_M  ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S))
-#define GPIO_PIN3_INT_ENA_V  0x1F
-#define GPIO_PIN3_INT_ENA_S  13
-/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN3_CONFIG  0x00000003
-#define GPIO_PIN3_CONFIG_M  ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S))
-#define GPIO_PIN3_CONFIG_V  0x3
-#define GPIO_PIN3_CONFIG_S  11
-/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN3_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN3_WAKEUP_ENABLE_S  10
-/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN3_INT_TYPE  0x00000007
-#define GPIO_PIN3_INT_TYPE_M  ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
-#define GPIO_PIN3_INT_TYPE_V  0x7
-#define GPIO_PIN3_INT_TYPE_S  7
-/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN3_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN3_PAD_DRIVER_V  0x1
-#define GPIO_PIN3_PAD_DRIVER_S  2
-
-#define GPIO_PIN4_REG          (DR_REG_GPIO_BASE + 0x0098)
-/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN4_INT_ENA  0x0000001F
-#define GPIO_PIN4_INT_ENA_M  ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
-#define GPIO_PIN4_INT_ENA_V  0x1F
-#define GPIO_PIN4_INT_ENA_S  13
-/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN4_CONFIG  0x00000003
-#define GPIO_PIN4_CONFIG_M  ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S))
-#define GPIO_PIN4_CONFIG_V  0x3
-#define GPIO_PIN4_CONFIG_S  11
-/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN4_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN4_WAKEUP_ENABLE_S  10
-/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN4_INT_TYPE  0x00000007
-#define GPIO_PIN4_INT_TYPE_M  ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S))
-#define GPIO_PIN4_INT_TYPE_V  0x7
-#define GPIO_PIN4_INT_TYPE_S  7
-/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN4_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN4_PAD_DRIVER_V  0x1
-#define GPIO_PIN4_PAD_DRIVER_S  2
-
-#define GPIO_PIN5_REG          (DR_REG_GPIO_BASE + 0x009c)
-/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN5_INT_ENA  0x0000001F
-#define GPIO_PIN5_INT_ENA_M  ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S))
-#define GPIO_PIN5_INT_ENA_V  0x1F
-#define GPIO_PIN5_INT_ENA_S  13
-/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN5_CONFIG  0x00000003
-#define GPIO_PIN5_CONFIG_M  ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
-#define GPIO_PIN5_CONFIG_V  0x3
-#define GPIO_PIN5_CONFIG_S  11
-/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN5_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN5_WAKEUP_ENABLE_S  10
-/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN5_INT_TYPE  0x00000007
-#define GPIO_PIN5_INT_TYPE_M  ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S))
-#define GPIO_PIN5_INT_TYPE_V  0x7
-#define GPIO_PIN5_INT_TYPE_S  7
-/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN5_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN5_PAD_DRIVER_V  0x1
-#define GPIO_PIN5_PAD_DRIVER_S  2
-
-#define GPIO_PIN6_REG          (DR_REG_GPIO_BASE + 0x00a0)
-/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN6_INT_ENA  0x0000001F
-#define GPIO_PIN6_INT_ENA_M  ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S))
-#define GPIO_PIN6_INT_ENA_V  0x1F
-#define GPIO_PIN6_INT_ENA_S  13
-/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN6_CONFIG  0x00000003
-#define GPIO_PIN6_CONFIG_M  ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S))
-#define GPIO_PIN6_CONFIG_V  0x3
-#define GPIO_PIN6_CONFIG_S  11
-/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN6_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN6_WAKEUP_ENABLE_S  10
-/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN6_INT_TYPE  0x00000007
-#define GPIO_PIN6_INT_TYPE_M  ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S))
-#define GPIO_PIN6_INT_TYPE_V  0x7
-#define GPIO_PIN6_INT_TYPE_S  7
-/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN6_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN6_PAD_DRIVER_V  0x1
-#define GPIO_PIN6_PAD_DRIVER_S  2
-
-#define GPIO_PIN7_REG          (DR_REG_GPIO_BASE + 0x00a4)
-/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN7_INT_ENA  0x0000001F
-#define GPIO_PIN7_INT_ENA_M  ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S))
-#define GPIO_PIN7_INT_ENA_V  0x1F
-#define GPIO_PIN7_INT_ENA_S  13
-/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN7_CONFIG  0x00000003
-#define GPIO_PIN7_CONFIG_M  ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S))
-#define GPIO_PIN7_CONFIG_V  0x3
-#define GPIO_PIN7_CONFIG_S  11
-/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN7_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN7_WAKEUP_ENABLE_S  10
-/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN7_INT_TYPE  0x00000007
-#define GPIO_PIN7_INT_TYPE_M  ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
-#define GPIO_PIN7_INT_TYPE_V  0x7
-#define GPIO_PIN7_INT_TYPE_S  7
-/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN7_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN7_PAD_DRIVER_V  0x1
-#define GPIO_PIN7_PAD_DRIVER_S  2
-
-#define GPIO_PIN8_REG          (DR_REG_GPIO_BASE + 0x00a8)
-/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN8_INT_ENA  0x0000001F
-#define GPIO_PIN8_INT_ENA_M  ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
-#define GPIO_PIN8_INT_ENA_V  0x1F
-#define GPIO_PIN8_INT_ENA_S  13
-/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN8_CONFIG  0x00000003
-#define GPIO_PIN8_CONFIG_M  ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S))
-#define GPIO_PIN8_CONFIG_V  0x3
-#define GPIO_PIN8_CONFIG_S  11
-/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN8_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN8_WAKEUP_ENABLE_S  10
-/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN8_INT_TYPE  0x00000007
-#define GPIO_PIN8_INT_TYPE_M  ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S))
-#define GPIO_PIN8_INT_TYPE_V  0x7
-#define GPIO_PIN8_INT_TYPE_S  7
-/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN8_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN8_PAD_DRIVER_V  0x1
-#define GPIO_PIN8_PAD_DRIVER_S  2
-
-#define GPIO_PIN9_REG          (DR_REG_GPIO_BASE + 0x00ac)
-/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN9_INT_ENA  0x0000001F
-#define GPIO_PIN9_INT_ENA_M  ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S))
-#define GPIO_PIN9_INT_ENA_V  0x1F
-#define GPIO_PIN9_INT_ENA_S  13
-/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN9_CONFIG  0x00000003
-#define GPIO_PIN9_CONFIG_M  ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
-#define GPIO_PIN9_CONFIG_V  0x3
-#define GPIO_PIN9_CONFIG_S  11
-/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN9_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN9_WAKEUP_ENABLE_S  10
-/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN9_INT_TYPE  0x00000007
-#define GPIO_PIN9_INT_TYPE_M  ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S))
-#define GPIO_PIN9_INT_TYPE_V  0x7
-#define GPIO_PIN9_INT_TYPE_S  7
-/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN9_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN9_PAD_DRIVER_V  0x1
-#define GPIO_PIN9_PAD_DRIVER_S  2
-
-#define GPIO_PIN10_REG          (DR_REG_GPIO_BASE + 0x00b0)
-/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN10_INT_ENA  0x0000001F
-#define GPIO_PIN10_INT_ENA_M  ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S))
-#define GPIO_PIN10_INT_ENA_V  0x1F
-#define GPIO_PIN10_INT_ENA_S  13
-/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN10_CONFIG  0x00000003
-#define GPIO_PIN10_CONFIG_M  ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S))
-#define GPIO_PIN10_CONFIG_V  0x3
-#define GPIO_PIN10_CONFIG_S  11
-/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN10_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN10_WAKEUP_ENABLE_S  10
-/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN10_INT_TYPE  0x00000007
-#define GPIO_PIN10_INT_TYPE_M  ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S))
-#define GPIO_PIN10_INT_TYPE_V  0x7
-#define GPIO_PIN10_INT_TYPE_S  7
-/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN10_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN10_PAD_DRIVER_V  0x1
-#define GPIO_PIN10_PAD_DRIVER_S  2
-
-#define GPIO_PIN11_REG          (DR_REG_GPIO_BASE + 0x00b4)
-/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN11_INT_ENA  0x0000001F
-#define GPIO_PIN11_INT_ENA_M  ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S))
-#define GPIO_PIN11_INT_ENA_V  0x1F
-#define GPIO_PIN11_INT_ENA_S  13
-/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN11_CONFIG  0x00000003
-#define GPIO_PIN11_CONFIG_M  ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S))
-#define GPIO_PIN11_CONFIG_V  0x3
-#define GPIO_PIN11_CONFIG_S  11
-/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN11_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN11_WAKEUP_ENABLE_S  10
-/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN11_INT_TYPE  0x00000007
-#define GPIO_PIN11_INT_TYPE_M  ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
-#define GPIO_PIN11_INT_TYPE_V  0x7
-#define GPIO_PIN11_INT_TYPE_S  7
-/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN11_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN11_PAD_DRIVER_V  0x1
-#define GPIO_PIN11_PAD_DRIVER_S  2
-
-#define GPIO_PIN12_REG          (DR_REG_GPIO_BASE + 0x00b8)
-/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN12_INT_ENA  0x0000001F
-#define GPIO_PIN12_INT_ENA_M  ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
-#define GPIO_PIN12_INT_ENA_V  0x1F
-#define GPIO_PIN12_INT_ENA_S  13
-/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN12_CONFIG  0x00000003
-#define GPIO_PIN12_CONFIG_M  ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S))
-#define GPIO_PIN12_CONFIG_V  0x3
-#define GPIO_PIN12_CONFIG_S  11
-/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN12_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN12_WAKEUP_ENABLE_S  10
-/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN12_INT_TYPE  0x00000007
-#define GPIO_PIN12_INT_TYPE_M  ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S))
-#define GPIO_PIN12_INT_TYPE_V  0x7
-#define GPIO_PIN12_INT_TYPE_S  7
-/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN12_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN12_PAD_DRIVER_V  0x1
-#define GPIO_PIN12_PAD_DRIVER_S  2
-
-#define GPIO_PIN13_REG          (DR_REG_GPIO_BASE + 0x00bc)
-/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN13_INT_ENA  0x0000001F
-#define GPIO_PIN13_INT_ENA_M  ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S))
-#define GPIO_PIN13_INT_ENA_V  0x1F
-#define GPIO_PIN13_INT_ENA_S  13
-/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN13_CONFIG  0x00000003
-#define GPIO_PIN13_CONFIG_M  ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
-#define GPIO_PIN13_CONFIG_V  0x3
-#define GPIO_PIN13_CONFIG_S  11
-/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN13_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN13_WAKEUP_ENABLE_S  10
-/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN13_INT_TYPE  0x00000007
-#define GPIO_PIN13_INT_TYPE_M  ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S))
-#define GPIO_PIN13_INT_TYPE_V  0x7
-#define GPIO_PIN13_INT_TYPE_S  7
-/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN13_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN13_PAD_DRIVER_V  0x1
-#define GPIO_PIN13_PAD_DRIVER_S  2
-
-#define GPIO_PIN14_REG          (DR_REG_GPIO_BASE + 0x00c0)
-/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN14_INT_ENA  0x0000001F
-#define GPIO_PIN14_INT_ENA_M  ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S))
-#define GPIO_PIN14_INT_ENA_V  0x1F
-#define GPIO_PIN14_INT_ENA_S  13
-/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN14_CONFIG  0x00000003
-#define GPIO_PIN14_CONFIG_M  ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S))
-#define GPIO_PIN14_CONFIG_V  0x3
-#define GPIO_PIN14_CONFIG_S  11
-/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN14_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN14_WAKEUP_ENABLE_S  10
-/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN14_INT_TYPE  0x00000007
-#define GPIO_PIN14_INT_TYPE_M  ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S))
-#define GPIO_PIN14_INT_TYPE_V  0x7
-#define GPIO_PIN14_INT_TYPE_S  7
-/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN14_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN14_PAD_DRIVER_V  0x1
-#define GPIO_PIN14_PAD_DRIVER_S  2
-
-#define GPIO_PIN15_REG          (DR_REG_GPIO_BASE + 0x00c4)
-/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN15_INT_ENA  0x0000001F
-#define GPIO_PIN15_INT_ENA_M  ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S))
-#define GPIO_PIN15_INT_ENA_V  0x1F
-#define GPIO_PIN15_INT_ENA_S  13
-/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN15_CONFIG  0x00000003
-#define GPIO_PIN15_CONFIG_M  ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S))
-#define GPIO_PIN15_CONFIG_V  0x3
-#define GPIO_PIN15_CONFIG_S  11
-/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN15_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN15_WAKEUP_ENABLE_S  10
-/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN15_INT_TYPE  0x00000007
-#define GPIO_PIN15_INT_TYPE_M  ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
-#define GPIO_PIN15_INT_TYPE_V  0x7
-#define GPIO_PIN15_INT_TYPE_S  7
-/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN15_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN15_PAD_DRIVER_V  0x1
-#define GPIO_PIN15_PAD_DRIVER_S  2
-
-#define GPIO_PIN16_REG          (DR_REG_GPIO_BASE + 0x00c8)
-/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN16_INT_ENA  0x0000001F
-#define GPIO_PIN16_INT_ENA_M  ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
-#define GPIO_PIN16_INT_ENA_V  0x1F
-#define GPIO_PIN16_INT_ENA_S  13
-/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN16_CONFIG  0x00000003
-#define GPIO_PIN16_CONFIG_M  ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S))
-#define GPIO_PIN16_CONFIG_V  0x3
-#define GPIO_PIN16_CONFIG_S  11
-/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN16_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN16_WAKEUP_ENABLE_S  10
-/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN16_INT_TYPE  0x00000007
-#define GPIO_PIN16_INT_TYPE_M  ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S))
-#define GPIO_PIN16_INT_TYPE_V  0x7
-#define GPIO_PIN16_INT_TYPE_S  7
-/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN16_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN16_PAD_DRIVER_V  0x1
-#define GPIO_PIN16_PAD_DRIVER_S  2
-
-#define GPIO_PIN17_REG          (DR_REG_GPIO_BASE + 0x00cc)
-/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN17_INT_ENA  0x0000001F
-#define GPIO_PIN17_INT_ENA_M  ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S))
-#define GPIO_PIN17_INT_ENA_V  0x1F
-#define GPIO_PIN17_INT_ENA_S  13
-/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN17_CONFIG  0x00000003
-#define GPIO_PIN17_CONFIG_M  ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
-#define GPIO_PIN17_CONFIG_V  0x3
-#define GPIO_PIN17_CONFIG_S  11
-/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN17_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN17_WAKEUP_ENABLE_S  10
-/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN17_INT_TYPE  0x00000007
-#define GPIO_PIN17_INT_TYPE_M  ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S))
-#define GPIO_PIN17_INT_TYPE_V  0x7
-#define GPIO_PIN17_INT_TYPE_S  7
-/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN17_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN17_PAD_DRIVER_V  0x1
-#define GPIO_PIN17_PAD_DRIVER_S  2
-
-#define GPIO_PIN18_REG          (DR_REG_GPIO_BASE + 0x00d0)
-/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN18_INT_ENA  0x0000001F
-#define GPIO_PIN18_INT_ENA_M  ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S))
-#define GPIO_PIN18_INT_ENA_V  0x1F
-#define GPIO_PIN18_INT_ENA_S  13
-/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN18_CONFIG  0x00000003
-#define GPIO_PIN18_CONFIG_M  ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S))
-#define GPIO_PIN18_CONFIG_V  0x3
-#define GPIO_PIN18_CONFIG_S  11
-/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN18_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN18_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN18_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN18_WAKEUP_ENABLE_S  10
-/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN18_INT_TYPE  0x00000007
-#define GPIO_PIN18_INT_TYPE_M  ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S))
-#define GPIO_PIN18_INT_TYPE_V  0x7
-#define GPIO_PIN18_INT_TYPE_S  7
-/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN18_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN18_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN18_PAD_DRIVER_V  0x1
-#define GPIO_PIN18_PAD_DRIVER_S  2
-
-#define GPIO_PIN19_REG          (DR_REG_GPIO_BASE + 0x00d4)
-/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN19_INT_ENA  0x0000001F
-#define GPIO_PIN19_INT_ENA_M  ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S))
-#define GPIO_PIN19_INT_ENA_V  0x1F
-#define GPIO_PIN19_INT_ENA_S  13
-/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN19_CONFIG  0x00000003
-#define GPIO_PIN19_CONFIG_M  ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S))
-#define GPIO_PIN19_CONFIG_V  0x3
-#define GPIO_PIN19_CONFIG_S  11
-/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN19_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN19_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN19_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN19_WAKEUP_ENABLE_S  10
-/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN19_INT_TYPE  0x00000007
-#define GPIO_PIN19_INT_TYPE_M  ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
-#define GPIO_PIN19_INT_TYPE_V  0x7
-#define GPIO_PIN19_INT_TYPE_S  7
-/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN19_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN19_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN19_PAD_DRIVER_V  0x1
-#define GPIO_PIN19_PAD_DRIVER_S  2
-
-#define GPIO_PIN20_REG          (DR_REG_GPIO_BASE + 0x00d8)
-/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-mask interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-mask interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN20_INT_ENA  0x0000001F
-#define GPIO_PIN20_INT_ENA_M  ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
-#define GPIO_PIN20_INT_ENA_V  0x1F
-#define GPIO_PIN20_INT_ENA_S  13
-/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN20_CONFIG  0x00000003
-#define GPIO_PIN20_CONFIG_M  ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S))
-#define GPIO_PIN20_CONFIG_V  0x3
-#define GPIO_PIN20_CONFIG_S  11
-/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN20_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN20_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN20_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN20_WAKEUP_ENABLE_S  10
-/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN20_INT_TYPE  0x00000007
-#define GPIO_PIN20_INT_TYPE_M  ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S))
-#define GPIO_PIN20_INT_TYPE_V  0x7
-#define GPIO_PIN20_INT_TYPE_S  7
-/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN20_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN20_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN20_PAD_DRIVER_V  0x1
-#define GPIO_PIN20_PAD_DRIVER_S  2
-
-#define GPIO_PIN21_REG          (DR_REG_GPIO_BASE + 0x00dc)
-/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN21_INT_ENA  0x0000001F
-#define GPIO_PIN21_INT_ENA_M  ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S))
-#define GPIO_PIN21_INT_ENA_V  0x1F
-#define GPIO_PIN21_INT_ENA_S  13
-/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN21_CONFIG  0x00000003
-#define GPIO_PIN21_CONFIG_M  ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
-#define GPIO_PIN21_CONFIG_V  0x3
-#define GPIO_PIN21_CONFIG_S  11
-/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN21_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN21_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN21_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN21_WAKEUP_ENABLE_S  10
-/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN21_INT_TYPE  0x00000007
-#define GPIO_PIN21_INT_TYPE_M  ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S))
-#define GPIO_PIN21_INT_TYPE_V  0x7
-#define GPIO_PIN21_INT_TYPE_S  7
-/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN21_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN21_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN21_PAD_DRIVER_V  0x1
-#define GPIO_PIN21_PAD_DRIVER_S  2
-
-#define GPIO_PIN22_REG          (DR_REG_GPIO_BASE + 0x00e0)
-/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: */
-#define GPIO_PIN22_INT_ENA  0x0000001F
-#define GPIO_PIN22_INT_ENA_M  ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S))
-#define GPIO_PIN22_INT_ENA_V  0x1F
-#define GPIO_PIN22_INT_ENA_S  13
-/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN22_CONFIG  0x00000003
-#define GPIO_PIN22_CONFIG_M  ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S))
-#define GPIO_PIN22_CONFIG_V  0x3
-#define GPIO_PIN22_CONFIG_S  11
-/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN22_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN22_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN22_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN22_WAKEUP_ENABLE_S  10
-/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN22_INT_TYPE  0x00000007
-#define GPIO_PIN22_INT_TYPE_M  ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S))
-#define GPIO_PIN22_INT_TYPE_V  0x7
-#define GPIO_PIN22_INT_TYPE_S  7
-/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: */
-#define GPIO_PIN22_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN22_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN22_PAD_DRIVER_V  0x1
-#define GPIO_PIN22_PAD_DRIVER_S  2
-
-#define GPIO_PIN23_REG          (DR_REG_GPIO_BASE + 0x00e4)
-/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN23_INT_ENA  0x0000001F
-#define GPIO_PIN23_INT_ENA_M  ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S))
-#define GPIO_PIN23_INT_ENA_V  0x1F
-#define GPIO_PIN23_INT_ENA_S  13
-/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN23_CONFIG  0x00000003
-#define GPIO_PIN23_CONFIG_M  ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S))
-#define GPIO_PIN23_CONFIG_V  0x3
-#define GPIO_PIN23_CONFIG_S  11
-/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN23_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN23_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN23_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN23_WAKEUP_ENABLE_S  10
-/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN23_INT_TYPE  0x00000007
-#define GPIO_PIN23_INT_TYPE_M  ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
-#define GPIO_PIN23_INT_TYPE_V  0x7
-#define GPIO_PIN23_INT_TYPE_S  7
-/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN23_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN23_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN23_PAD_DRIVER_V  0x1
-#define GPIO_PIN23_PAD_DRIVER_S  2
-
-#define GPIO_PIN24_REG          (DR_REG_GPIO_BASE + 0x00e8)
-/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN24_INT_ENA  0x0000001F
-#define GPIO_PIN24_INT_ENA_M  ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
-#define GPIO_PIN24_INT_ENA_V  0x1F
-#define GPIO_PIN24_INT_ENA_S  13
-/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN24_CONFIG  0x00000003
-#define GPIO_PIN24_CONFIG_M  ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S))
-#define GPIO_PIN24_CONFIG_V  0x3
-#define GPIO_PIN24_CONFIG_S  11
-/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN24_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN24_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN24_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN24_WAKEUP_ENABLE_S  10
-/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN24_INT_TYPE  0x00000007
-#define GPIO_PIN24_INT_TYPE_M  ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S))
-#define GPIO_PIN24_INT_TYPE_V  0x7
-#define GPIO_PIN24_INT_TYPE_S  7
-/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN24_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN24_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN24_PAD_DRIVER_V  0x1
-#define GPIO_PIN24_PAD_DRIVER_S  2
-
-#define GPIO_PIN25_REG          (DR_REG_GPIO_BASE + 0x00ec)
-/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN25_INT_ENA  0x0000001F
-#define GPIO_PIN25_INT_ENA_M  ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S))
-#define GPIO_PIN25_INT_ENA_V  0x1F
-#define GPIO_PIN25_INT_ENA_S  13
-/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN25_CONFIG  0x00000003
-#define GPIO_PIN25_CONFIG_M  ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
-#define GPIO_PIN25_CONFIG_V  0x3
-#define GPIO_PIN25_CONFIG_S  11
-/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN25_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN25_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN25_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN25_WAKEUP_ENABLE_S  10
-/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN25_INT_TYPE  0x00000007
-#define GPIO_PIN25_INT_TYPE_M  ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S))
-#define GPIO_PIN25_INT_TYPE_V  0x7
-#define GPIO_PIN25_INT_TYPE_S  7
-/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN25_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN25_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN25_PAD_DRIVER_V  0x1
-#define GPIO_PIN25_PAD_DRIVER_S  2
-
-#define GPIO_PIN26_REG          (DR_REG_GPIO_BASE + 0x00f0)
-/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN26_INT_ENA  0x0000001F
-#define GPIO_PIN26_INT_ENA_M  ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S))
-#define GPIO_PIN26_INT_ENA_V  0x1F
-#define GPIO_PIN26_INT_ENA_S  13
-/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN26_CONFIG  0x00000003
-#define GPIO_PIN26_CONFIG_M  ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S))
-#define GPIO_PIN26_CONFIG_V  0x3
-#define GPIO_PIN26_CONFIG_S  11
-/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN26_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN26_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN26_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN26_WAKEUP_ENABLE_S  10
-/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN26_INT_TYPE  0x00000007
-#define GPIO_PIN26_INT_TYPE_M  ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S))
-#define GPIO_PIN26_INT_TYPE_V  0x7
-#define GPIO_PIN26_INT_TYPE_S  7
-/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN26_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN26_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN26_PAD_DRIVER_V  0x1
-#define GPIO_PIN26_PAD_DRIVER_S  2
-
-#define GPIO_PIN27_REG          (DR_REG_GPIO_BASE + 0x00f4)
-/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN27_INT_ENA  0x0000001F
-#define GPIO_PIN27_INT_ENA_M  ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S))
-#define GPIO_PIN27_INT_ENA_V  0x1F
-#define GPIO_PIN27_INT_ENA_S  13
-/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN27_CONFIG  0x00000003
-#define GPIO_PIN27_CONFIG_M  ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S))
-#define GPIO_PIN27_CONFIG_V  0x3
-#define GPIO_PIN27_CONFIG_S  11
-/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN27_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN27_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN27_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN27_WAKEUP_ENABLE_S  10
-/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN27_INT_TYPE  0x00000007
-#define GPIO_PIN27_INT_TYPE_M  ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S))
-#define GPIO_PIN27_INT_TYPE_V  0x7
-#define GPIO_PIN27_INT_TYPE_S  7
-/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN27_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN27_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN27_PAD_DRIVER_V  0x1
-#define GPIO_PIN27_PAD_DRIVER_S  2
-
-#define GPIO_PIN28_REG          (DR_REG_GPIO_BASE + 0x00f8)
-/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN28_INT_ENA  0x0000001F
-#define GPIO_PIN28_INT_ENA_M  ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S))
-#define GPIO_PIN28_INT_ENA_V  0x1F
-#define GPIO_PIN28_INT_ENA_S  13
-/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN28_CONFIG  0x00000003
-#define GPIO_PIN28_CONFIG_M  ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S))
-#define GPIO_PIN28_CONFIG_V  0x3
-#define GPIO_PIN28_CONFIG_S  11
-/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN28_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN28_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN28_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN28_WAKEUP_ENABLE_S  10
-/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN28_INT_TYPE  0x00000007
-#define GPIO_PIN28_INT_TYPE_M  ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S))
-#define GPIO_PIN28_INT_TYPE_V  0x7
-#define GPIO_PIN28_INT_TYPE_S  7
-/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN28_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN28_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN28_PAD_DRIVER_V  0x1
-#define GPIO_PIN28_PAD_DRIVER_S  2
-
-#define GPIO_PIN29_REG          (DR_REG_GPIO_BASE + 0x00fc)
-/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN29_INT_ENA  0x0000001F
-#define GPIO_PIN29_INT_ENA_M  ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S))
-#define GPIO_PIN29_INT_ENA_V  0x1F
-#define GPIO_PIN29_INT_ENA_S  13
-/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN29_CONFIG  0x00000003
-#define GPIO_PIN29_CONFIG_M  ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S))
-#define GPIO_PIN29_CONFIG_V  0x3
-#define GPIO_PIN29_CONFIG_S  11
-/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN29_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN29_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN29_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN29_WAKEUP_ENABLE_S  10
-/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN29_INT_TYPE  0x00000007
-#define GPIO_PIN29_INT_TYPE_M  ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S))
-#define GPIO_PIN29_INT_TYPE_V  0x7
-#define GPIO_PIN29_INT_TYPE_S  7
-/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN29_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN29_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN29_PAD_DRIVER_V  0x1
-#define GPIO_PIN29_PAD_DRIVER_S  2
-
-#define GPIO_PIN30_REG          (DR_REG_GPIO_BASE + 0x0100)
-/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN30_INT_ENA  0x0000001F
-#define GPIO_PIN30_INT_ENA_M  ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S))
-#define GPIO_PIN30_INT_ENA_V  0x1F
-#define GPIO_PIN30_INT_ENA_S  13
-/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN30_CONFIG  0x00000003
-#define GPIO_PIN30_CONFIG_M  ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S))
-#define GPIO_PIN30_CONFIG_V  0x3
-#define GPIO_PIN30_CONFIG_S  11
-/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN30_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN30_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN30_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN30_WAKEUP_ENABLE_S  10
-/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN30_INT_TYPE  0x00000007
-#define GPIO_PIN30_INT_TYPE_M  ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S))
-#define GPIO_PIN30_INT_TYPE_V  0x7
-#define GPIO_PIN30_INT_TYPE_S  7
-/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN30_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN30_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN30_PAD_DRIVER_V  0x1
-#define GPIO_PIN30_PAD_DRIVER_S  2
-
-#define GPIO_PIN31_REG          (DR_REG_GPIO_BASE + 0x0104)
-/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN31_INT_ENA  0x0000001F
-#define GPIO_PIN31_INT_ENA_M  ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S))
-#define GPIO_PIN31_INT_ENA_V  0x1F
-#define GPIO_PIN31_INT_ENA_S  13
-/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN31_CONFIG  0x00000003
-#define GPIO_PIN31_CONFIG_M  ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S))
-#define GPIO_PIN31_CONFIG_V  0x3
-#define GPIO_PIN31_CONFIG_S  11
-/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN31_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN31_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN31_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN31_WAKEUP_ENABLE_S  10
-/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN31_INT_TYPE  0x00000007
-#define GPIO_PIN31_INT_TYPE_M  ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S))
-#define GPIO_PIN31_INT_TYPE_V  0x7
-#define GPIO_PIN31_INT_TYPE_S  7
-/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN31_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN31_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN31_PAD_DRIVER_V  0x1
-#define GPIO_PIN31_PAD_DRIVER_S  2
-
-#define GPIO_PIN32_REG          (DR_REG_GPIO_BASE + 0x0108)
-/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN32_INT_ENA  0x0000001F
-#define GPIO_PIN32_INT_ENA_M  ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S))
-#define GPIO_PIN32_INT_ENA_V  0x1F
-#define GPIO_PIN32_INT_ENA_S  13
-/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN32_CONFIG  0x00000003
-#define GPIO_PIN32_CONFIG_M  ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S))
-#define GPIO_PIN32_CONFIG_V  0x3
-#define GPIO_PIN32_CONFIG_S  11
-/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN32_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN32_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN32_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN32_WAKEUP_ENABLE_S  10
-/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN32_INT_TYPE  0x00000007
-#define GPIO_PIN32_INT_TYPE_M  ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S))
-#define GPIO_PIN32_INT_TYPE_V  0x7
-#define GPIO_PIN32_INT_TYPE_S  7
-/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN32_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN32_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN32_PAD_DRIVER_V  0x1
-#define GPIO_PIN32_PAD_DRIVER_S  2
-
-#define GPIO_PIN33_REG          (DR_REG_GPIO_BASE + 0x010c)
-/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN33_INT_ENA  0x0000001F
-#define GPIO_PIN33_INT_ENA_M  ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S))
-#define GPIO_PIN33_INT_ENA_V  0x1F
-#define GPIO_PIN33_INT_ENA_S  13
-/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN33_CONFIG  0x00000003
-#define GPIO_PIN33_CONFIG_M  ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S))
-#define GPIO_PIN33_CONFIG_V  0x3
-#define GPIO_PIN33_CONFIG_S  11
-/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN33_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN33_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN33_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN33_WAKEUP_ENABLE_S  10
-/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN33_INT_TYPE  0x00000007
-#define GPIO_PIN33_INT_TYPE_M  ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S))
-#define GPIO_PIN33_INT_TYPE_V  0x7
-#define GPIO_PIN33_INT_TYPE_S  7
-/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN33_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN33_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN33_PAD_DRIVER_V  0x1
-#define GPIO_PIN33_PAD_DRIVER_S  2
-
-#define GPIO_PIN34_REG          (DR_REG_GPIO_BASE + 0x0110)
-/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN34_INT_ENA  0x0000001F
-#define GPIO_PIN34_INT_ENA_M  ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S))
-#define GPIO_PIN34_INT_ENA_V  0x1F
-#define GPIO_PIN34_INT_ENA_S  13
-/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN34_CONFIG  0x00000003
-#define GPIO_PIN34_CONFIG_M  ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S))
-#define GPIO_PIN34_CONFIG_V  0x3
-#define GPIO_PIN34_CONFIG_S  11
-/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN34_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN34_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN34_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN34_WAKEUP_ENABLE_S  10
-/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN34_INT_TYPE  0x00000007
-#define GPIO_PIN34_INT_TYPE_M  ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S))
-#define GPIO_PIN34_INT_TYPE_V  0x7
-#define GPIO_PIN34_INT_TYPE_S  7
-/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN34_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN34_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN34_PAD_DRIVER_V  0x1
-#define GPIO_PIN34_PAD_DRIVER_S  2
-
-#define GPIO_PIN35_REG          (DR_REG_GPIO_BASE + 0x0114)
-/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN35_INT_ENA  0x0000001F
-#define GPIO_PIN35_INT_ENA_M  ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S))
-#define GPIO_PIN35_INT_ENA_V  0x1F
-#define GPIO_PIN35_INT_ENA_S  13
-/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN35_CONFIG  0x00000003
-#define GPIO_PIN35_CONFIG_M  ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S))
-#define GPIO_PIN35_CONFIG_V  0x3
-#define GPIO_PIN35_CONFIG_S  11
-/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN35_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN35_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN35_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN35_WAKEUP_ENABLE_S  10
-/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN35_INT_TYPE  0x00000007
-#define GPIO_PIN35_INT_TYPE_M  ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S))
-#define GPIO_PIN35_INT_TYPE_V  0x7
-#define GPIO_PIN35_INT_TYPE_S  7
-/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN35_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN35_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN35_PAD_DRIVER_V  0x1
-#define GPIO_PIN35_PAD_DRIVER_S  2
-
-#define GPIO_PIN36_REG          (DR_REG_GPIO_BASE + 0x0118)
-/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN36_INT_ENA  0x0000001F
-#define GPIO_PIN36_INT_ENA_M  ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S))
-#define GPIO_PIN36_INT_ENA_V  0x1F
-#define GPIO_PIN36_INT_ENA_S  13
-/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN36_CONFIG  0x00000003
-#define GPIO_PIN36_CONFIG_M  ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S))
-#define GPIO_PIN36_CONFIG_V  0x3
-#define GPIO_PIN36_CONFIG_S  11
-/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN36_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN36_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN36_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN36_WAKEUP_ENABLE_S  10
-/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN36_INT_TYPE  0x00000007
-#define GPIO_PIN36_INT_TYPE_M  ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S))
-#define GPIO_PIN36_INT_TYPE_V  0x7
-#define GPIO_PIN36_INT_TYPE_S  7
-/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN36_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN36_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN36_PAD_DRIVER_V  0x1
-#define GPIO_PIN36_PAD_DRIVER_S  2
-
-#define GPIO_PIN37_REG          (DR_REG_GPIO_BASE + 0x011c)
-/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN37_INT_ENA  0x0000001F
-#define GPIO_PIN37_INT_ENA_M  ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S))
-#define GPIO_PIN37_INT_ENA_V  0x1F
-#define GPIO_PIN37_INT_ENA_S  13
-/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN37_CONFIG  0x00000003
-#define GPIO_PIN37_CONFIG_M  ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S))
-#define GPIO_PIN37_CONFIG_V  0x3
-#define GPIO_PIN37_CONFIG_S  11
-/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN37_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN37_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN37_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN37_WAKEUP_ENABLE_S  10
-/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN37_INT_TYPE  0x00000007
-#define GPIO_PIN37_INT_TYPE_M  ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S))
-#define GPIO_PIN37_INT_TYPE_V  0x7
-#define GPIO_PIN37_INT_TYPE_S  7
-/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN37_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN37_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN37_PAD_DRIVER_V  0x1
-#define GPIO_PIN37_PAD_DRIVER_S  2
-
-#define GPIO_PIN38_REG          (DR_REG_GPIO_BASE + 0x0120)
-/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN38_INT_ENA  0x0000001F
-#define GPIO_PIN38_INT_ENA_M  ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S))
-#define GPIO_PIN38_INT_ENA_V  0x1F
-#define GPIO_PIN38_INT_ENA_S  13
-/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN38_CONFIG  0x00000003
-#define GPIO_PIN38_CONFIG_M  ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S))
-#define GPIO_PIN38_CONFIG_V  0x3
-#define GPIO_PIN38_CONFIG_S  11
-/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN38_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN38_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN38_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN38_WAKEUP_ENABLE_S  10
-/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN38_INT_TYPE  0x00000007
-#define GPIO_PIN38_INT_TYPE_M  ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S))
-#define GPIO_PIN38_INT_TYPE_V  0x7
-#define GPIO_PIN38_INT_TYPE_S  7
-/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN38_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN38_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN38_PAD_DRIVER_V  0x1
-#define GPIO_PIN38_PAD_DRIVER_S  2
-
-#define GPIO_PIN39_REG          (DR_REG_GPIO_BASE + 0x0124)
-/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */
-/*description: bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt
- enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-#define GPIO_PIN39_INT_ENA  0x0000001F
-#define GPIO_PIN39_INT_ENA_M  ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S))
-#define GPIO_PIN39_INT_ENA_V  0x1F
-#define GPIO_PIN39_INT_ENA_S  13
-/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */
-/*description: NA*/
-#define GPIO_PIN39_CONFIG  0x00000003
-#define GPIO_PIN39_CONFIG_M  ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S))
-#define GPIO_PIN39_CONFIG_V  0x3
-#define GPIO_PIN39_CONFIG_S  11
-/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define GPIO_PIN39_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN39_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN39_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN39_WAKEUP_ENABLE_S  10
-/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define GPIO_PIN39_INT_TYPE  0x00000007
-#define GPIO_PIN39_INT_TYPE_M  ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S))
-#define GPIO_PIN39_INT_TYPE_V  0x7
-#define GPIO_PIN39_INT_TYPE_S  7
-/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define GPIO_PIN39_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN39_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN39_PAD_DRIVER_V  0x1
-#define GPIO_PIN39_PAD_DRIVER_S  2
-
-#define GPIO_cali_conf_REG          (DR_REG_GPIO_BASE + 0x0128)
-/* GPIO_CALI_START : R/W ;bitpos:[31] ;default: x ; */
-/*description: */
-#define GPIO_CALI_START  (BIT(31))
-#define GPIO_CALI_START_M  (BIT(31))
-#define GPIO_CALI_START_V  0x1
-#define GPIO_CALI_START_S  31
-/* GPIO_CALI_RTC_MAX : R/W ;bitpos:[9:0] ;default: x ; */
-/*description: */
-#define GPIO_CALI_RTC_MAX  0x000003FF
-#define GPIO_CALI_RTC_MAX_M  ((GPIO_CALI_RTC_MAX_V)<<(GPIO_CALI_RTC_MAX_S))
-#define GPIO_CALI_RTC_MAX_V  0x3FF
-#define GPIO_CALI_RTC_MAX_S  0
-
-#define GPIO_cali_data_REG          (DR_REG_GPIO_BASE + 0x012c)
-/* GPIO_CALI_RDY_SYNC2 : RO ;bitpos:[31] ;default:  ; */
-/*description: */
-#define GPIO_CALI_RDY_SYNC2  (BIT(31))
-#define GPIO_CALI_RDY_SYNC2_M  (BIT(31))
-#define GPIO_CALI_RDY_SYNC2_V  0x1
-#define GPIO_CALI_RDY_SYNC2_S  31
-/* GPIO_CALI_RDY_REAL : RO ;bitpos:[30] ;default:  ; */
-/*description: */
-#define GPIO_CALI_RDY_REAL  (BIT(30))
-#define GPIO_CALI_RDY_REAL_M  (BIT(30))
-#define GPIO_CALI_RDY_REAL_V  0x1
-#define GPIO_CALI_RDY_REAL_S  30
-/* GPIO_CALI_VALUE_SYNC2 : RO ;bitpos:[19:0] ;default:  ; */
-/*description: */
-#define GPIO_CALI_VALUE_SYNC2  0x000FFFFF
-#define GPIO_CALI_VALUE_SYNC2_M  ((GPIO_CALI_VALUE_SYNC2_V)<<(GPIO_CALI_VALUE_SYNC2_S))
-#define GPIO_CALI_VALUE_SYNC2_V  0xFFFFF
-#define GPIO_CALI_VALUE_SYNC2_S  0
-
-#define GPIO_FUNC0_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0130)
-/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG0_IN_SEL  (BIT(7))
-#define GPIO_SIG0_IN_SEL_M  (BIT(7))
-#define GPIO_SIG0_IN_SEL_V  0x1
-#define GPIO_SIG0_IN_SEL_S  7
-/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC0_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC0_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC0_IN_INV_SEL_V  0x1
-#define GPIO_FUNC0_IN_INV_SEL_S  6
-/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC0_IN_SEL  0x0000003F
-#define GPIO_FUNC0_IN_SEL_M  ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S))
-#define GPIO_FUNC0_IN_SEL_V  0x3F
-#define GPIO_FUNC0_IN_SEL_S  0
-
-#define GPIO_FUNC1_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0134)
-/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG1_IN_SEL  (BIT(7))
-#define GPIO_SIG1_IN_SEL_M  (BIT(7))
-#define GPIO_SIG1_IN_SEL_V  0x1
-#define GPIO_SIG1_IN_SEL_S  7
-/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC1_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC1_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC1_IN_INV_SEL_V  0x1
-#define GPIO_FUNC1_IN_INV_SEL_S  6
-/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC1_IN_SEL  0x0000003F
-#define GPIO_FUNC1_IN_SEL_M  ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S))
-#define GPIO_FUNC1_IN_SEL_V  0x3F
-#define GPIO_FUNC1_IN_SEL_S  0
-
-#define GPIO_FUNC2_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0138)
-/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG2_IN_SEL  (BIT(7))
-#define GPIO_SIG2_IN_SEL_M  (BIT(7))
-#define GPIO_SIG2_IN_SEL_V  0x1
-#define GPIO_SIG2_IN_SEL_S  7
-/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC2_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC2_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC2_IN_INV_SEL_V  0x1
-#define GPIO_FUNC2_IN_INV_SEL_S  6
-/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC2_IN_SEL  0x0000003F
-#define GPIO_FUNC2_IN_SEL_M  ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S))
-#define GPIO_FUNC2_IN_SEL_V  0x3F
-#define GPIO_FUNC2_IN_SEL_S  0
-
-#define GPIO_FUNC3_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x013c)
-/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG3_IN_SEL  (BIT(7))
-#define GPIO_SIG3_IN_SEL_M  (BIT(7))
-#define GPIO_SIG3_IN_SEL_V  0x1
-#define GPIO_SIG3_IN_SEL_S  7
-/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC3_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC3_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC3_IN_INV_SEL_V  0x1
-#define GPIO_FUNC3_IN_INV_SEL_S  6
-/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC3_IN_SEL  0x0000003F
-#define GPIO_FUNC3_IN_SEL_M  ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S))
-#define GPIO_FUNC3_IN_SEL_V  0x3F
-#define GPIO_FUNC3_IN_SEL_S  0
-
-#define GPIO_FUNC4_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0140)
-/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG4_IN_SEL  (BIT(7))
-#define GPIO_SIG4_IN_SEL_M  (BIT(7))
-#define GPIO_SIG4_IN_SEL_V  0x1
-#define GPIO_SIG4_IN_SEL_S  7
-/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC4_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC4_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC4_IN_INV_SEL_V  0x1
-#define GPIO_FUNC4_IN_INV_SEL_S  6
-/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC4_IN_SEL  0x0000003F
-#define GPIO_FUNC4_IN_SEL_M  ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S))
-#define GPIO_FUNC4_IN_SEL_V  0x3F
-#define GPIO_FUNC4_IN_SEL_S  0
-
-#define GPIO_FUNC5_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0144)
-/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG5_IN_SEL  (BIT(7))
-#define GPIO_SIG5_IN_SEL_M  (BIT(7))
-#define GPIO_SIG5_IN_SEL_V  0x1
-#define GPIO_SIG5_IN_SEL_S  7
-/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC5_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC5_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC5_IN_INV_SEL_V  0x1
-#define GPIO_FUNC5_IN_INV_SEL_S  6
-/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC5_IN_SEL  0x0000003F
-#define GPIO_FUNC5_IN_SEL_M  ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S))
-#define GPIO_FUNC5_IN_SEL_V  0x3F
-#define GPIO_FUNC5_IN_SEL_S  0
-
-#define GPIO_FUNC6_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0148)
-/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG6_IN_SEL  (BIT(7))
-#define GPIO_SIG6_IN_SEL_M  (BIT(7))
-#define GPIO_SIG6_IN_SEL_V  0x1
-#define GPIO_SIG6_IN_SEL_S  7
-/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC6_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC6_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC6_IN_INV_SEL_V  0x1
-#define GPIO_FUNC6_IN_INV_SEL_S  6
-/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC6_IN_SEL  0x0000003F
-#define GPIO_FUNC6_IN_SEL_M  ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S))
-#define GPIO_FUNC6_IN_SEL_V  0x3F
-#define GPIO_FUNC6_IN_SEL_S  0
-
-#define GPIO_FUNC7_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x014c)
-/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG7_IN_SEL  (BIT(7))
-#define GPIO_SIG7_IN_SEL_M  (BIT(7))
-#define GPIO_SIG7_IN_SEL_V  0x1
-#define GPIO_SIG7_IN_SEL_S  7
-/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC7_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC7_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC7_IN_INV_SEL_V  0x1
-#define GPIO_FUNC7_IN_INV_SEL_S  6
-/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC7_IN_SEL  0x0000003F
-#define GPIO_FUNC7_IN_SEL_M  ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S))
-#define GPIO_FUNC7_IN_SEL_V  0x3F
-#define GPIO_FUNC7_IN_SEL_S  0
-
-#define GPIO_FUNC8_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0150)
-/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG8_IN_SEL  (BIT(7))
-#define GPIO_SIG8_IN_SEL_M  (BIT(7))
-#define GPIO_SIG8_IN_SEL_V  0x1
-#define GPIO_SIG8_IN_SEL_S  7
-/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC8_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC8_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC8_IN_INV_SEL_V  0x1
-#define GPIO_FUNC8_IN_INV_SEL_S  6
-/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC8_IN_SEL  0x0000003F
-#define GPIO_FUNC8_IN_SEL_M  ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S))
-#define GPIO_FUNC8_IN_SEL_V  0x3F
-#define GPIO_FUNC8_IN_SEL_S  0
-
-#define GPIO_FUNC9_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0154)
-/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG9_IN_SEL  (BIT(7))
-#define GPIO_SIG9_IN_SEL_M  (BIT(7))
-#define GPIO_SIG9_IN_SEL_V  0x1
-#define GPIO_SIG9_IN_SEL_S  7
-/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC9_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC9_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC9_IN_INV_SEL_V  0x1
-#define GPIO_FUNC9_IN_INV_SEL_S  6
-/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC9_IN_SEL  0x0000003F
-#define GPIO_FUNC9_IN_SEL_M  ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S))
-#define GPIO_FUNC9_IN_SEL_V  0x3F
-#define GPIO_FUNC9_IN_SEL_S  0
-
-#define GPIO_FUNC10_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0158)
-/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG10_IN_SEL  (BIT(7))
-#define GPIO_SIG10_IN_SEL_M  (BIT(7))
-#define GPIO_SIG10_IN_SEL_V  0x1
-#define GPIO_SIG10_IN_SEL_S  7
-/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC10_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC10_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC10_IN_INV_SEL_V  0x1
-#define GPIO_FUNC10_IN_INV_SEL_S  6
-/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC10_IN_SEL  0x0000003F
-#define GPIO_FUNC10_IN_SEL_M  ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S))
-#define GPIO_FUNC10_IN_SEL_V  0x3F
-#define GPIO_FUNC10_IN_SEL_S  0
-
-#define GPIO_FUNC11_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x015c)
-/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG11_IN_SEL  (BIT(7))
-#define GPIO_SIG11_IN_SEL_M  (BIT(7))
-#define GPIO_SIG11_IN_SEL_V  0x1
-#define GPIO_SIG11_IN_SEL_S  7
-/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC11_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC11_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC11_IN_INV_SEL_V  0x1
-#define GPIO_FUNC11_IN_INV_SEL_S  6
-/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC11_IN_SEL  0x0000003F
-#define GPIO_FUNC11_IN_SEL_M  ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S))
-#define GPIO_FUNC11_IN_SEL_V  0x3F
-#define GPIO_FUNC11_IN_SEL_S  0
-
-#define GPIO_FUNC12_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0160)
-/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG12_IN_SEL  (BIT(7))
-#define GPIO_SIG12_IN_SEL_M  (BIT(7))
-#define GPIO_SIG12_IN_SEL_V  0x1
-#define GPIO_SIG12_IN_SEL_S  7
-/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC12_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC12_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC12_IN_INV_SEL_V  0x1
-#define GPIO_FUNC12_IN_INV_SEL_S  6
-/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC12_IN_SEL  0x0000003F
-#define GPIO_FUNC12_IN_SEL_M  ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S))
-#define GPIO_FUNC12_IN_SEL_V  0x3F
-#define GPIO_FUNC12_IN_SEL_S  0
-
-#define GPIO_FUNC13_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0164)
-/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG13_IN_SEL  (BIT(7))
-#define GPIO_SIG13_IN_SEL_M  (BIT(7))
-#define GPIO_SIG13_IN_SEL_V  0x1
-#define GPIO_SIG13_IN_SEL_S  7
-/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC13_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC13_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC13_IN_INV_SEL_V  0x1
-#define GPIO_FUNC13_IN_INV_SEL_S  6
-/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC13_IN_SEL  0x0000003F
-#define GPIO_FUNC13_IN_SEL_M  ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S))
-#define GPIO_FUNC13_IN_SEL_V  0x3F
-#define GPIO_FUNC13_IN_SEL_S  0
-
-#define GPIO_FUNC14_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0168)
-/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG14_IN_SEL  (BIT(7))
-#define GPIO_SIG14_IN_SEL_M  (BIT(7))
-#define GPIO_SIG14_IN_SEL_V  0x1
-#define GPIO_SIG14_IN_SEL_S  7
-/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC14_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC14_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC14_IN_INV_SEL_V  0x1
-#define GPIO_FUNC14_IN_INV_SEL_S  6
-/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC14_IN_SEL  0x0000003F
-#define GPIO_FUNC14_IN_SEL_M  ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S))
-#define GPIO_FUNC14_IN_SEL_V  0x3F
-#define GPIO_FUNC14_IN_SEL_S  0
-
-#define GPIO_FUNC15_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x016c)
-/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG15_IN_SEL  (BIT(7))
-#define GPIO_SIG15_IN_SEL_M  (BIT(7))
-#define GPIO_SIG15_IN_SEL_V  0x1
-#define GPIO_SIG15_IN_SEL_S  7
-/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC15_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC15_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC15_IN_INV_SEL_V  0x1
-#define GPIO_FUNC15_IN_INV_SEL_S  6
-/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC15_IN_SEL  0x0000003F
-#define GPIO_FUNC15_IN_SEL_M  ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S))
-#define GPIO_FUNC15_IN_SEL_V  0x3F
-#define GPIO_FUNC15_IN_SEL_S  0
-
-#define GPIO_FUNC16_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0170)
-/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG16_IN_SEL  (BIT(7))
-#define GPIO_SIG16_IN_SEL_M  (BIT(7))
-#define GPIO_SIG16_IN_SEL_V  0x1
-#define GPIO_SIG16_IN_SEL_S  7
-/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC16_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC16_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC16_IN_INV_SEL_V  0x1
-#define GPIO_FUNC16_IN_INV_SEL_S  6
-/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC16_IN_SEL  0x0000003F
-#define GPIO_FUNC16_IN_SEL_M  ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S))
-#define GPIO_FUNC16_IN_SEL_V  0x3F
-#define GPIO_FUNC16_IN_SEL_S  0
-
-#define GPIO_FUNC17_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0174)
-/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG17_IN_SEL  (BIT(7))
-#define GPIO_SIG17_IN_SEL_M  (BIT(7))
-#define GPIO_SIG17_IN_SEL_V  0x1
-#define GPIO_SIG17_IN_SEL_S  7
-/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC17_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC17_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC17_IN_INV_SEL_V  0x1
-#define GPIO_FUNC17_IN_INV_SEL_S  6
-/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC17_IN_SEL  0x0000003F
-#define GPIO_FUNC17_IN_SEL_M  ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S))
-#define GPIO_FUNC17_IN_SEL_V  0x3F
-#define GPIO_FUNC17_IN_SEL_S  0
-
-#define GPIO_FUNC18_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0178)
-/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG18_IN_SEL  (BIT(7))
-#define GPIO_SIG18_IN_SEL_M  (BIT(7))
-#define GPIO_SIG18_IN_SEL_V  0x1
-#define GPIO_SIG18_IN_SEL_S  7
-/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC18_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC18_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC18_IN_INV_SEL_V  0x1
-#define GPIO_FUNC18_IN_INV_SEL_S  6
-/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC18_IN_SEL  0x0000003F
-#define GPIO_FUNC18_IN_SEL_M  ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S))
-#define GPIO_FUNC18_IN_SEL_V  0x3F
-#define GPIO_FUNC18_IN_SEL_S  0
-
-#define GPIO_FUNC19_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x017c)
-/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG19_IN_SEL  (BIT(7))
-#define GPIO_SIG19_IN_SEL_M  (BIT(7))
-#define GPIO_SIG19_IN_SEL_V  0x1
-#define GPIO_SIG19_IN_SEL_S  7
-/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC19_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC19_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC19_IN_INV_SEL_V  0x1
-#define GPIO_FUNC19_IN_INV_SEL_S  6
-/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC19_IN_SEL  0x0000003F
-#define GPIO_FUNC19_IN_SEL_M  ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S))
-#define GPIO_FUNC19_IN_SEL_V  0x3F
-#define GPIO_FUNC19_IN_SEL_S  0
-
-#define GPIO_FUNC20_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0180)
-/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG20_IN_SEL  (BIT(7))
-#define GPIO_SIG20_IN_SEL_M  (BIT(7))
-#define GPIO_SIG20_IN_SEL_V  0x1
-#define GPIO_SIG20_IN_SEL_S  7
-/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC20_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC20_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC20_IN_INV_SEL_V  0x1
-#define GPIO_FUNC20_IN_INV_SEL_S  6
-/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC20_IN_SEL  0x0000003F
-#define GPIO_FUNC20_IN_SEL_M  ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S))
-#define GPIO_FUNC20_IN_SEL_V  0x3F
-#define GPIO_FUNC20_IN_SEL_S  0
-
-#define GPIO_FUNC21_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0184)
-/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG21_IN_SEL  (BIT(7))
-#define GPIO_SIG21_IN_SEL_M  (BIT(7))
-#define GPIO_SIG21_IN_SEL_V  0x1
-#define GPIO_SIG21_IN_SEL_S  7
-/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC21_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC21_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC21_IN_INV_SEL_V  0x1
-#define GPIO_FUNC21_IN_INV_SEL_S  6
-/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC21_IN_SEL  0x0000003F
-#define GPIO_FUNC21_IN_SEL_M  ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S))
-#define GPIO_FUNC21_IN_SEL_V  0x3F
-#define GPIO_FUNC21_IN_SEL_S  0
-
-#define GPIO_FUNC22_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0188)
-/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG22_IN_SEL  (BIT(7))
-#define GPIO_SIG22_IN_SEL_M  (BIT(7))
-#define GPIO_SIG22_IN_SEL_V  0x1
-#define GPIO_SIG22_IN_SEL_S  7
-/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC22_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC22_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC22_IN_INV_SEL_V  0x1
-#define GPIO_FUNC22_IN_INV_SEL_S  6
-/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC22_IN_SEL  0x0000003F
-#define GPIO_FUNC22_IN_SEL_M  ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S))
-#define GPIO_FUNC22_IN_SEL_V  0x3F
-#define GPIO_FUNC22_IN_SEL_S  0
-
-#define GPIO_FUNC23_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x018c)
-/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG23_IN_SEL  (BIT(7))
-#define GPIO_SIG23_IN_SEL_M  (BIT(7))
-#define GPIO_SIG23_IN_SEL_V  0x1
-#define GPIO_SIG23_IN_SEL_S  7
-/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC23_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC23_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC23_IN_INV_SEL_V  0x1
-#define GPIO_FUNC23_IN_INV_SEL_S  6
-/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC23_IN_SEL  0x0000003F
-#define GPIO_FUNC23_IN_SEL_M  ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S))
-#define GPIO_FUNC23_IN_SEL_V  0x3F
-#define GPIO_FUNC23_IN_SEL_S  0
-
-#define GPIO_FUNC24_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0190)
-/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG24_IN_SEL  (BIT(7))
-#define GPIO_SIG24_IN_SEL_M  (BIT(7))
-#define GPIO_SIG24_IN_SEL_V  0x1
-#define GPIO_SIG24_IN_SEL_S  7
-/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC24_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC24_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC24_IN_INV_SEL_V  0x1
-#define GPIO_FUNC24_IN_INV_SEL_S  6
-/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC24_IN_SEL  0x0000003F
-#define GPIO_FUNC24_IN_SEL_M  ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S))
-#define GPIO_FUNC24_IN_SEL_V  0x3F
-#define GPIO_FUNC24_IN_SEL_S  0
-
-#define GPIO_FUNC25_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0194)
-/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG25_IN_SEL  (BIT(7))
-#define GPIO_SIG25_IN_SEL_M  (BIT(7))
-#define GPIO_SIG25_IN_SEL_V  0x1
-#define GPIO_SIG25_IN_SEL_S  7
-/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC25_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC25_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC25_IN_INV_SEL_V  0x1
-#define GPIO_FUNC25_IN_INV_SEL_S  6
-/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC25_IN_SEL  0x0000003F
-#define GPIO_FUNC25_IN_SEL_M  ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S))
-#define GPIO_FUNC25_IN_SEL_V  0x3F
-#define GPIO_FUNC25_IN_SEL_S  0
-
-#define GPIO_FUNC26_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0198)
-/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG26_IN_SEL  (BIT(7))
-#define GPIO_SIG26_IN_SEL_M  (BIT(7))
-#define GPIO_SIG26_IN_SEL_V  0x1
-#define GPIO_SIG26_IN_SEL_S  7
-/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC26_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC26_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC26_IN_INV_SEL_V  0x1
-#define GPIO_FUNC26_IN_INV_SEL_S  6
-/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC26_IN_SEL  0x0000003F
-#define GPIO_FUNC26_IN_SEL_M  ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S))
-#define GPIO_FUNC26_IN_SEL_V  0x3F
-#define GPIO_FUNC26_IN_SEL_S  0
-
-#define GPIO_FUNC27_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x019c)
-/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG27_IN_SEL  (BIT(7))
-#define GPIO_SIG27_IN_SEL_M  (BIT(7))
-#define GPIO_SIG27_IN_SEL_V  0x1
-#define GPIO_SIG27_IN_SEL_S  7
-/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC27_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC27_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC27_IN_INV_SEL_V  0x1
-#define GPIO_FUNC27_IN_INV_SEL_S  6
-/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC27_IN_SEL  0x0000003F
-#define GPIO_FUNC27_IN_SEL_M  ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S))
-#define GPIO_FUNC27_IN_SEL_V  0x3F
-#define GPIO_FUNC27_IN_SEL_S  0
-
-#define GPIO_FUNC28_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01a0)
-/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG28_IN_SEL  (BIT(7))
-#define GPIO_SIG28_IN_SEL_M  (BIT(7))
-#define GPIO_SIG28_IN_SEL_V  0x1
-#define GPIO_SIG28_IN_SEL_S  7
-/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC28_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC28_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC28_IN_INV_SEL_V  0x1
-#define GPIO_FUNC28_IN_INV_SEL_S  6
-/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC28_IN_SEL  0x0000003F
-#define GPIO_FUNC28_IN_SEL_M  ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S))
-#define GPIO_FUNC28_IN_SEL_V  0x3F
-#define GPIO_FUNC28_IN_SEL_S  0
-
-#define GPIO_FUNC29_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01a4)
-/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG29_IN_SEL  (BIT(7))
-#define GPIO_SIG29_IN_SEL_M  (BIT(7))
-#define GPIO_SIG29_IN_SEL_V  0x1
-#define GPIO_SIG29_IN_SEL_S  7
-/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC29_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC29_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC29_IN_INV_SEL_V  0x1
-#define GPIO_FUNC29_IN_INV_SEL_S  6
-/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC29_IN_SEL  0x0000003F
-#define GPIO_FUNC29_IN_SEL_M  ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S))
-#define GPIO_FUNC29_IN_SEL_V  0x3F
-#define GPIO_FUNC29_IN_SEL_S  0
-
-#define GPIO_FUNC30_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01a8)
-/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG30_IN_SEL  (BIT(7))
-#define GPIO_SIG30_IN_SEL_M  (BIT(7))
-#define GPIO_SIG30_IN_SEL_V  0x1
-#define GPIO_SIG30_IN_SEL_S  7
-/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC30_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC30_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC30_IN_INV_SEL_V  0x1
-#define GPIO_FUNC30_IN_INV_SEL_S  6
-/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC30_IN_SEL  0x0000003F
-#define GPIO_FUNC30_IN_SEL_M  ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S))
-#define GPIO_FUNC30_IN_SEL_V  0x3F
-#define GPIO_FUNC30_IN_SEL_S  0
-
-#define GPIO_FUNC31_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01ac)
-/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG31_IN_SEL  (BIT(7))
-#define GPIO_SIG31_IN_SEL_M  (BIT(7))
-#define GPIO_SIG31_IN_SEL_V  0x1
-#define GPIO_SIG31_IN_SEL_S  7
-/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC31_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC31_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC31_IN_INV_SEL_V  0x1
-#define GPIO_FUNC31_IN_INV_SEL_S  6
-/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC31_IN_SEL  0x0000003F
-#define GPIO_FUNC31_IN_SEL_M  ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S))
-#define GPIO_FUNC31_IN_SEL_V  0x3F
-#define GPIO_FUNC31_IN_SEL_S  0
-
-#define GPIO_FUNC32_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01b0)
-/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG32_IN_SEL  (BIT(7))
-#define GPIO_SIG32_IN_SEL_M  (BIT(7))
-#define GPIO_SIG32_IN_SEL_V  0x1
-#define GPIO_SIG32_IN_SEL_S  7
-/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC32_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC32_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC32_IN_INV_SEL_V  0x1
-#define GPIO_FUNC32_IN_INV_SEL_S  6
-/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC32_IN_SEL  0x0000003F
-#define GPIO_FUNC32_IN_SEL_M  ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S))
-#define GPIO_FUNC32_IN_SEL_V  0x3F
-#define GPIO_FUNC32_IN_SEL_S  0
-
-#define GPIO_FUNC33_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01b4)
-/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG33_IN_SEL  (BIT(7))
-#define GPIO_SIG33_IN_SEL_M  (BIT(7))
-#define GPIO_SIG33_IN_SEL_V  0x1
-#define GPIO_SIG33_IN_SEL_S  7
-/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC33_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC33_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC33_IN_INV_SEL_V  0x1
-#define GPIO_FUNC33_IN_INV_SEL_S  6
-/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC33_IN_SEL  0x0000003F
-#define GPIO_FUNC33_IN_SEL_M  ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S))
-#define GPIO_FUNC33_IN_SEL_V  0x3F
-#define GPIO_FUNC33_IN_SEL_S  0
-
-#define GPIO_FUNC34_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01b8)
-/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG34_IN_SEL  (BIT(7))
-#define GPIO_SIG34_IN_SEL_M  (BIT(7))
-#define GPIO_SIG34_IN_SEL_V  0x1
-#define GPIO_SIG34_IN_SEL_S  7
-/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC34_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC34_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC34_IN_INV_SEL_V  0x1
-#define GPIO_FUNC34_IN_INV_SEL_S  6
-/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC34_IN_SEL  0x0000003F
-#define GPIO_FUNC34_IN_SEL_M  ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S))
-#define GPIO_FUNC34_IN_SEL_V  0x3F
-#define GPIO_FUNC34_IN_SEL_S  0
-
-#define GPIO_FUNC35_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01bc)
-/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG35_IN_SEL  (BIT(7))
-#define GPIO_SIG35_IN_SEL_M  (BIT(7))
-#define GPIO_SIG35_IN_SEL_V  0x1
-#define GPIO_SIG35_IN_SEL_S  7
-/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC35_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC35_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC35_IN_INV_SEL_V  0x1
-#define GPIO_FUNC35_IN_INV_SEL_S  6
-/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC35_IN_SEL  0x0000003F
-#define GPIO_FUNC35_IN_SEL_M  ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S))
-#define GPIO_FUNC35_IN_SEL_V  0x3F
-#define GPIO_FUNC35_IN_SEL_S  0
-
-#define GPIO_FUNC36_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01c0)
-/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG36_IN_SEL  (BIT(7))
-#define GPIO_SIG36_IN_SEL_M  (BIT(7))
-#define GPIO_SIG36_IN_SEL_V  0x1
-#define GPIO_SIG36_IN_SEL_S  7
-/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC36_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC36_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC36_IN_INV_SEL_V  0x1
-#define GPIO_FUNC36_IN_INV_SEL_S  6
-/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC36_IN_SEL  0x0000003F
-#define GPIO_FUNC36_IN_SEL_M  ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S))
-#define GPIO_FUNC36_IN_SEL_V  0x3F
-#define GPIO_FUNC36_IN_SEL_S  0
-
-#define GPIO_FUNC37_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01c4)
-/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG37_IN_SEL  (BIT(7))
-#define GPIO_SIG37_IN_SEL_M  (BIT(7))
-#define GPIO_SIG37_IN_SEL_V  0x1
-#define GPIO_SIG37_IN_SEL_S  7
-/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC37_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC37_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC37_IN_INV_SEL_V  0x1
-#define GPIO_FUNC37_IN_INV_SEL_S  6
-/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC37_IN_SEL  0x0000003F
-#define GPIO_FUNC37_IN_SEL_M  ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S))
-#define GPIO_FUNC37_IN_SEL_V  0x3F
-#define GPIO_FUNC37_IN_SEL_S  0
-
-#define GPIO_FUNC38_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01c8)
-/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG38_IN_SEL  (BIT(7))
-#define GPIO_SIG38_IN_SEL_M  (BIT(7))
-#define GPIO_SIG38_IN_SEL_V  0x1
-#define GPIO_SIG38_IN_SEL_S  7
-/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC38_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC38_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC38_IN_INV_SEL_V  0x1
-#define GPIO_FUNC38_IN_INV_SEL_S  6
-/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC38_IN_SEL  0x0000003F
-#define GPIO_FUNC38_IN_SEL_M  ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S))
-#define GPIO_FUNC38_IN_SEL_V  0x3F
-#define GPIO_FUNC38_IN_SEL_S  0
-
-#define GPIO_FUNC39_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01cc)
-/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG39_IN_SEL  (BIT(7))
-#define GPIO_SIG39_IN_SEL_M  (BIT(7))
-#define GPIO_SIG39_IN_SEL_V  0x1
-#define GPIO_SIG39_IN_SEL_S  7
-/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC39_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC39_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC39_IN_INV_SEL_V  0x1
-#define GPIO_FUNC39_IN_INV_SEL_S  6
-/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC39_IN_SEL  0x0000003F
-#define GPIO_FUNC39_IN_SEL_M  ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S))
-#define GPIO_FUNC39_IN_SEL_V  0x3F
-#define GPIO_FUNC39_IN_SEL_S  0
-
-#define GPIO_FUNC40_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01d0)
-/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG40_IN_SEL  (BIT(7))
-#define GPIO_SIG40_IN_SEL_M  (BIT(7))
-#define GPIO_SIG40_IN_SEL_V  0x1
-#define GPIO_SIG40_IN_SEL_S  7
-/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC40_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC40_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC40_IN_INV_SEL_V  0x1
-#define GPIO_FUNC40_IN_INV_SEL_S  6
-/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC40_IN_SEL  0x0000003F
-#define GPIO_FUNC40_IN_SEL_M  ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S))
-#define GPIO_FUNC40_IN_SEL_V  0x3F
-#define GPIO_FUNC40_IN_SEL_S  0
-
-#define GPIO_FUNC41_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01d4)
-/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG41_IN_SEL  (BIT(7))
-#define GPIO_SIG41_IN_SEL_M  (BIT(7))
-#define GPIO_SIG41_IN_SEL_V  0x1
-#define GPIO_SIG41_IN_SEL_S  7
-/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC41_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC41_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC41_IN_INV_SEL_V  0x1
-#define GPIO_FUNC41_IN_INV_SEL_S  6
-/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC41_IN_SEL  0x0000003F
-#define GPIO_FUNC41_IN_SEL_M  ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S))
-#define GPIO_FUNC41_IN_SEL_V  0x3F
-#define GPIO_FUNC41_IN_SEL_S  0
-
-#define GPIO_FUNC42_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01d8)
-/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG42_IN_SEL  (BIT(7))
-#define GPIO_SIG42_IN_SEL_M  (BIT(7))
-#define GPIO_SIG42_IN_SEL_V  0x1
-#define GPIO_SIG42_IN_SEL_S  7
-/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC42_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC42_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC42_IN_INV_SEL_V  0x1
-#define GPIO_FUNC42_IN_INV_SEL_S  6
-/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC42_IN_SEL  0x0000003F
-#define GPIO_FUNC42_IN_SEL_M  ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S))
-#define GPIO_FUNC42_IN_SEL_V  0x3F
-#define GPIO_FUNC42_IN_SEL_S  0
-
-#define GPIO_FUNC43_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01dc)
-/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG43_IN_SEL  (BIT(7))
-#define GPIO_SIG43_IN_SEL_M  (BIT(7))
-#define GPIO_SIG43_IN_SEL_V  0x1
-#define GPIO_SIG43_IN_SEL_S  7
-/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC43_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC43_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC43_IN_INV_SEL_V  0x1
-#define GPIO_FUNC43_IN_INV_SEL_S  6
-/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC43_IN_SEL  0x0000003F
-#define GPIO_FUNC43_IN_SEL_M  ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S))
-#define GPIO_FUNC43_IN_SEL_V  0x3F
-#define GPIO_FUNC43_IN_SEL_S  0
-
-#define GPIO_FUNC44_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01e0)
-/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG44_IN_SEL  (BIT(7))
-#define GPIO_SIG44_IN_SEL_M  (BIT(7))
-#define GPIO_SIG44_IN_SEL_V  0x1
-#define GPIO_SIG44_IN_SEL_S  7
-/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC44_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC44_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC44_IN_INV_SEL_V  0x1
-#define GPIO_FUNC44_IN_INV_SEL_S  6
-/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC44_IN_SEL  0x0000003F
-#define GPIO_FUNC44_IN_SEL_M  ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S))
-#define GPIO_FUNC44_IN_SEL_V  0x3F
-#define GPIO_FUNC44_IN_SEL_S  0
-
-#define GPIO_FUNC45_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01e4)
-/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG45_IN_SEL  (BIT(7))
-#define GPIO_SIG45_IN_SEL_M  (BIT(7))
-#define GPIO_SIG45_IN_SEL_V  0x1
-#define GPIO_SIG45_IN_SEL_S  7
-/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC45_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC45_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC45_IN_INV_SEL_V  0x1
-#define GPIO_FUNC45_IN_INV_SEL_S  6
-/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC45_IN_SEL  0x0000003F
-#define GPIO_FUNC45_IN_SEL_M  ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S))
-#define GPIO_FUNC45_IN_SEL_V  0x3F
-#define GPIO_FUNC45_IN_SEL_S  0
-
-#define GPIO_FUNC46_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01e8)
-/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG46_IN_SEL  (BIT(7))
-#define GPIO_SIG46_IN_SEL_M  (BIT(7))
-#define GPIO_SIG46_IN_SEL_V  0x1
-#define GPIO_SIG46_IN_SEL_S  7
-/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC46_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC46_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC46_IN_INV_SEL_V  0x1
-#define GPIO_FUNC46_IN_INV_SEL_S  6
-/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC46_IN_SEL  0x0000003F
-#define GPIO_FUNC46_IN_SEL_M  ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S))
-#define GPIO_FUNC46_IN_SEL_V  0x3F
-#define GPIO_FUNC46_IN_SEL_S  0
-
-#define GPIO_FUNC47_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01ec)
-/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG47_IN_SEL  (BIT(7))
-#define GPIO_SIG47_IN_SEL_M  (BIT(7))
-#define GPIO_SIG47_IN_SEL_V  0x1
-#define GPIO_SIG47_IN_SEL_S  7
-/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC47_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC47_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC47_IN_INV_SEL_V  0x1
-#define GPIO_FUNC47_IN_INV_SEL_S  6
-/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC47_IN_SEL  0x0000003F
-#define GPIO_FUNC47_IN_SEL_M  ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S))
-#define GPIO_FUNC47_IN_SEL_V  0x3F
-#define GPIO_FUNC47_IN_SEL_S  0
-
-#define GPIO_FUNC48_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01f0)
-/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG48_IN_SEL  (BIT(7))
-#define GPIO_SIG48_IN_SEL_M  (BIT(7))
-#define GPIO_SIG48_IN_SEL_V  0x1
-#define GPIO_SIG48_IN_SEL_S  7
-/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC48_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC48_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC48_IN_INV_SEL_V  0x1
-#define GPIO_FUNC48_IN_INV_SEL_S  6
-/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC48_IN_SEL  0x0000003F
-#define GPIO_FUNC48_IN_SEL_M  ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S))
-#define GPIO_FUNC48_IN_SEL_V  0x3F
-#define GPIO_FUNC48_IN_SEL_S  0
-
-#define GPIO_FUNC49_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01f4)
-/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG49_IN_SEL  (BIT(7))
-#define GPIO_SIG49_IN_SEL_M  (BIT(7))
-#define GPIO_SIG49_IN_SEL_V  0x1
-#define GPIO_SIG49_IN_SEL_S  7
-/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC49_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC49_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC49_IN_INV_SEL_V  0x1
-#define GPIO_FUNC49_IN_INV_SEL_S  6
-/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC49_IN_SEL  0x0000003F
-#define GPIO_FUNC49_IN_SEL_M  ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S))
-#define GPIO_FUNC49_IN_SEL_V  0x3F
-#define GPIO_FUNC49_IN_SEL_S  0
-
-#define GPIO_FUNC50_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01f8)
-/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG50_IN_SEL  (BIT(7))
-#define GPIO_SIG50_IN_SEL_M  (BIT(7))
-#define GPIO_SIG50_IN_SEL_V  0x1
-#define GPIO_SIG50_IN_SEL_S  7
-/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC50_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC50_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC50_IN_INV_SEL_V  0x1
-#define GPIO_FUNC50_IN_INV_SEL_S  6
-/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC50_IN_SEL  0x0000003F
-#define GPIO_FUNC50_IN_SEL_M  ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S))
-#define GPIO_FUNC50_IN_SEL_V  0x3F
-#define GPIO_FUNC50_IN_SEL_S  0
-
-#define GPIO_FUNC51_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x01fc)
-/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG51_IN_SEL  (BIT(7))
-#define GPIO_SIG51_IN_SEL_M  (BIT(7))
-#define GPIO_SIG51_IN_SEL_V  0x1
-#define GPIO_SIG51_IN_SEL_S  7
-/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC51_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC51_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC51_IN_INV_SEL_V  0x1
-#define GPIO_FUNC51_IN_INV_SEL_S  6
-/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC51_IN_SEL  0x0000003F
-#define GPIO_FUNC51_IN_SEL_M  ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S))
-#define GPIO_FUNC51_IN_SEL_V  0x3F
-#define GPIO_FUNC51_IN_SEL_S  0
-
-#define GPIO_FUNC52_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0200)
-/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG52_IN_SEL  (BIT(7))
-#define GPIO_SIG52_IN_SEL_M  (BIT(7))
-#define GPIO_SIG52_IN_SEL_V  0x1
-#define GPIO_SIG52_IN_SEL_S  7
-/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC52_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC52_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC52_IN_INV_SEL_V  0x1
-#define GPIO_FUNC52_IN_INV_SEL_S  6
-/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC52_IN_SEL  0x0000003F
-#define GPIO_FUNC52_IN_SEL_M  ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S))
-#define GPIO_FUNC52_IN_SEL_V  0x3F
-#define GPIO_FUNC52_IN_SEL_S  0
-
-#define GPIO_FUNC53_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0204)
-/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG53_IN_SEL  (BIT(7))
-#define GPIO_SIG53_IN_SEL_M  (BIT(7))
-#define GPIO_SIG53_IN_SEL_V  0x1
-#define GPIO_SIG53_IN_SEL_S  7
-/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC53_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC53_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC53_IN_INV_SEL_V  0x1
-#define GPIO_FUNC53_IN_INV_SEL_S  6
-/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC53_IN_SEL  0x0000003F
-#define GPIO_FUNC53_IN_SEL_M  ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S))
-#define GPIO_FUNC53_IN_SEL_V  0x3F
-#define GPIO_FUNC53_IN_SEL_S  0
-
-#define GPIO_FUNC54_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0208)
-/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG54_IN_SEL  (BIT(7))
-#define GPIO_SIG54_IN_SEL_M  (BIT(7))
-#define GPIO_SIG54_IN_SEL_V  0x1
-#define GPIO_SIG54_IN_SEL_S  7
-/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC54_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC54_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC54_IN_INV_SEL_V  0x1
-#define GPIO_FUNC54_IN_INV_SEL_S  6
-/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC54_IN_SEL  0x0000003F
-#define GPIO_FUNC54_IN_SEL_M  ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S))
-#define GPIO_FUNC54_IN_SEL_V  0x3F
-#define GPIO_FUNC54_IN_SEL_S  0
-
-#define GPIO_FUNC55_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x020c)
-/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG55_IN_SEL  (BIT(7))
-#define GPIO_SIG55_IN_SEL_M  (BIT(7))
-#define GPIO_SIG55_IN_SEL_V  0x1
-#define GPIO_SIG55_IN_SEL_S  7
-/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC55_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC55_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC55_IN_INV_SEL_V  0x1
-#define GPIO_FUNC55_IN_INV_SEL_S  6
-/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC55_IN_SEL  0x0000003F
-#define GPIO_FUNC55_IN_SEL_M  ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S))
-#define GPIO_FUNC55_IN_SEL_V  0x3F
-#define GPIO_FUNC55_IN_SEL_S  0
-
-#define GPIO_FUNC56_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0210)
-/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG56_IN_SEL  (BIT(7))
-#define GPIO_SIG56_IN_SEL_M  (BIT(7))
-#define GPIO_SIG56_IN_SEL_V  0x1
-#define GPIO_SIG56_IN_SEL_S  7
-/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC56_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC56_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC56_IN_INV_SEL_V  0x1
-#define GPIO_FUNC56_IN_INV_SEL_S  6
-/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC56_IN_SEL  0x0000003F
-#define GPIO_FUNC56_IN_SEL_M  ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S))
-#define GPIO_FUNC56_IN_SEL_V  0x3F
-#define GPIO_FUNC56_IN_SEL_S  0
-
-#define GPIO_FUNC57_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0214)
-/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG57_IN_SEL  (BIT(7))
-#define GPIO_SIG57_IN_SEL_M  (BIT(7))
-#define GPIO_SIG57_IN_SEL_V  0x1
-#define GPIO_SIG57_IN_SEL_S  7
-/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC57_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC57_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC57_IN_INV_SEL_V  0x1
-#define GPIO_FUNC57_IN_INV_SEL_S  6
-/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC57_IN_SEL  0x0000003F
-#define GPIO_FUNC57_IN_SEL_M  ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S))
-#define GPIO_FUNC57_IN_SEL_V  0x3F
-#define GPIO_FUNC57_IN_SEL_S  0
-
-#define GPIO_FUNC58_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0218)
-/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG58_IN_SEL  (BIT(7))
-#define GPIO_SIG58_IN_SEL_M  (BIT(7))
-#define GPIO_SIG58_IN_SEL_V  0x1
-#define GPIO_SIG58_IN_SEL_S  7
-/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC58_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC58_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC58_IN_INV_SEL_V  0x1
-#define GPIO_FUNC58_IN_INV_SEL_S  6
-/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC58_IN_SEL  0x0000003F
-#define GPIO_FUNC58_IN_SEL_M  ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S))
-#define GPIO_FUNC58_IN_SEL_V  0x3F
-#define GPIO_FUNC58_IN_SEL_S  0
-
-#define GPIO_FUNC59_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x021c)
-/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG59_IN_SEL  (BIT(7))
-#define GPIO_SIG59_IN_SEL_M  (BIT(7))
-#define GPIO_SIG59_IN_SEL_V  0x1
-#define GPIO_SIG59_IN_SEL_S  7
-/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC59_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC59_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC59_IN_INV_SEL_V  0x1
-#define GPIO_FUNC59_IN_INV_SEL_S  6
-/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC59_IN_SEL  0x0000003F
-#define GPIO_FUNC59_IN_SEL_M  ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S))
-#define GPIO_FUNC59_IN_SEL_V  0x3F
-#define GPIO_FUNC59_IN_SEL_S  0
-
-#define GPIO_FUNC60_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0220)
-/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG60_IN_SEL  (BIT(7))
-#define GPIO_SIG60_IN_SEL_M  (BIT(7))
-#define GPIO_SIG60_IN_SEL_V  0x1
-#define GPIO_SIG60_IN_SEL_S  7
-/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC60_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC60_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC60_IN_INV_SEL_V  0x1
-#define GPIO_FUNC60_IN_INV_SEL_S  6
-/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC60_IN_SEL  0x0000003F
-#define GPIO_FUNC60_IN_SEL_M  ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S))
-#define GPIO_FUNC60_IN_SEL_V  0x3F
-#define GPIO_FUNC60_IN_SEL_S  0
-
-#define GPIO_FUNC61_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0224)
-/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG61_IN_SEL  (BIT(7))
-#define GPIO_SIG61_IN_SEL_M  (BIT(7))
-#define GPIO_SIG61_IN_SEL_V  0x1
-#define GPIO_SIG61_IN_SEL_S  7
-/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC61_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC61_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC61_IN_INV_SEL_V  0x1
-#define GPIO_FUNC61_IN_INV_SEL_S  6
-/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC61_IN_SEL  0x0000003F
-#define GPIO_FUNC61_IN_SEL_M  ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S))
-#define GPIO_FUNC61_IN_SEL_V  0x3F
-#define GPIO_FUNC61_IN_SEL_S  0
-
-#define GPIO_FUNC62_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0228)
-/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG62_IN_SEL  (BIT(7))
-#define GPIO_SIG62_IN_SEL_M  (BIT(7))
-#define GPIO_SIG62_IN_SEL_V  0x1
-#define GPIO_SIG62_IN_SEL_S  7
-/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC62_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC62_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC62_IN_INV_SEL_V  0x1
-#define GPIO_FUNC62_IN_INV_SEL_S  6
-/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC62_IN_SEL  0x0000003F
-#define GPIO_FUNC62_IN_SEL_M  ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S))
-#define GPIO_FUNC62_IN_SEL_V  0x3F
-#define GPIO_FUNC62_IN_SEL_S  0
-
-#define GPIO_FUNC63_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x022c)
-/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG63_IN_SEL  (BIT(7))
-#define GPIO_SIG63_IN_SEL_M  (BIT(7))
-#define GPIO_SIG63_IN_SEL_V  0x1
-#define GPIO_SIG63_IN_SEL_S  7
-/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC63_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC63_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC63_IN_INV_SEL_V  0x1
-#define GPIO_FUNC63_IN_INV_SEL_S  6
-/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC63_IN_SEL  0x0000003F
-#define GPIO_FUNC63_IN_SEL_M  ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S))
-#define GPIO_FUNC63_IN_SEL_V  0x3F
-#define GPIO_FUNC63_IN_SEL_S  0
-
-#define GPIO_FUNC64_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0230)
-/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG64_IN_SEL  (BIT(7))
-#define GPIO_SIG64_IN_SEL_M  (BIT(7))
-#define GPIO_SIG64_IN_SEL_V  0x1
-#define GPIO_SIG64_IN_SEL_S  7
-/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC64_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC64_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC64_IN_INV_SEL_V  0x1
-#define GPIO_FUNC64_IN_INV_SEL_S  6
-/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC64_IN_SEL  0x0000003F
-#define GPIO_FUNC64_IN_SEL_M  ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S))
-#define GPIO_FUNC64_IN_SEL_V  0x3F
-#define GPIO_FUNC64_IN_SEL_S  0
-
-#define GPIO_FUNC65_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0234)
-/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG65_IN_SEL  (BIT(7))
-#define GPIO_SIG65_IN_SEL_M  (BIT(7))
-#define GPIO_SIG65_IN_SEL_V  0x1
-#define GPIO_SIG65_IN_SEL_S  7
-/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC65_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC65_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC65_IN_INV_SEL_V  0x1
-#define GPIO_FUNC65_IN_INV_SEL_S  6
-/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC65_IN_SEL  0x0000003F
-#define GPIO_FUNC65_IN_SEL_M  ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S))
-#define GPIO_FUNC65_IN_SEL_V  0x3F
-#define GPIO_FUNC65_IN_SEL_S  0
-
-#define GPIO_FUNC66_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0238)
-/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG66_IN_SEL  (BIT(7))
-#define GPIO_SIG66_IN_SEL_M  (BIT(7))
-#define GPIO_SIG66_IN_SEL_V  0x1
-#define GPIO_SIG66_IN_SEL_S  7
-/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC66_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC66_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC66_IN_INV_SEL_V  0x1
-#define GPIO_FUNC66_IN_INV_SEL_S  6
-/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC66_IN_SEL  0x0000003F
-#define GPIO_FUNC66_IN_SEL_M  ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S))
-#define GPIO_FUNC66_IN_SEL_V  0x3F
-#define GPIO_FUNC66_IN_SEL_S  0
-
-#define GPIO_FUNC67_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x023c)
-/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG67_IN_SEL  (BIT(7))
-#define GPIO_SIG67_IN_SEL_M  (BIT(7))
-#define GPIO_SIG67_IN_SEL_V  0x1
-#define GPIO_SIG67_IN_SEL_S  7
-/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC67_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC67_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC67_IN_INV_SEL_V  0x1
-#define GPIO_FUNC67_IN_INV_SEL_S  6
-/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC67_IN_SEL  0x0000003F
-#define GPIO_FUNC67_IN_SEL_M  ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S))
-#define GPIO_FUNC67_IN_SEL_V  0x3F
-#define GPIO_FUNC67_IN_SEL_S  0
-
-#define GPIO_FUNC68_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0240)
-/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG68_IN_SEL  (BIT(7))
-#define GPIO_SIG68_IN_SEL_M  (BIT(7))
-#define GPIO_SIG68_IN_SEL_V  0x1
-#define GPIO_SIG68_IN_SEL_S  7
-/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC68_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC68_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC68_IN_INV_SEL_V  0x1
-#define GPIO_FUNC68_IN_INV_SEL_S  6
-/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC68_IN_SEL  0x0000003F
-#define GPIO_FUNC68_IN_SEL_M  ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S))
-#define GPIO_FUNC68_IN_SEL_V  0x3F
-#define GPIO_FUNC68_IN_SEL_S  0
-
-#define GPIO_FUNC69_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0244)
-/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG69_IN_SEL  (BIT(7))
-#define GPIO_SIG69_IN_SEL_M  (BIT(7))
-#define GPIO_SIG69_IN_SEL_V  0x1
-#define GPIO_SIG69_IN_SEL_S  7
-/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC69_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC69_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC69_IN_INV_SEL_V  0x1
-#define GPIO_FUNC69_IN_INV_SEL_S  6
-/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC69_IN_SEL  0x0000003F
-#define GPIO_FUNC69_IN_SEL_M  ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S))
-#define GPIO_FUNC69_IN_SEL_V  0x3F
-#define GPIO_FUNC69_IN_SEL_S  0
-
-#define GPIO_FUNC70_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0248)
-/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG70_IN_SEL  (BIT(7))
-#define GPIO_SIG70_IN_SEL_M  (BIT(7))
-#define GPIO_SIG70_IN_SEL_V  0x1
-#define GPIO_SIG70_IN_SEL_S  7
-/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC70_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC70_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC70_IN_INV_SEL_V  0x1
-#define GPIO_FUNC70_IN_INV_SEL_S  6
-/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC70_IN_SEL  0x0000003F
-#define GPIO_FUNC70_IN_SEL_M  ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S))
-#define GPIO_FUNC70_IN_SEL_V  0x3F
-#define GPIO_FUNC70_IN_SEL_S  0
-
-#define GPIO_FUNC71_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x024c)
-/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG71_IN_SEL  (BIT(7))
-#define GPIO_SIG71_IN_SEL_M  (BIT(7))
-#define GPIO_SIG71_IN_SEL_V  0x1
-#define GPIO_SIG71_IN_SEL_S  7
-/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC71_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC71_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC71_IN_INV_SEL_V  0x1
-#define GPIO_FUNC71_IN_INV_SEL_S  6
-/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC71_IN_SEL  0x0000003F
-#define GPIO_FUNC71_IN_SEL_M  ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S))
-#define GPIO_FUNC71_IN_SEL_V  0x3F
-#define GPIO_FUNC71_IN_SEL_S  0
-
-#define GPIO_FUNC72_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0250)
-/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG72_IN_SEL  (BIT(7))
-#define GPIO_SIG72_IN_SEL_M  (BIT(7))
-#define GPIO_SIG72_IN_SEL_V  0x1
-#define GPIO_SIG72_IN_SEL_S  7
-/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC72_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC72_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC72_IN_INV_SEL_V  0x1
-#define GPIO_FUNC72_IN_INV_SEL_S  6
-/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC72_IN_SEL  0x0000003F
-#define GPIO_FUNC72_IN_SEL_M  ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S))
-#define GPIO_FUNC72_IN_SEL_V  0x3F
-#define GPIO_FUNC72_IN_SEL_S  0
-
-#define GPIO_FUNC73_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0254)
-/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG73_IN_SEL  (BIT(7))
-#define GPIO_SIG73_IN_SEL_M  (BIT(7))
-#define GPIO_SIG73_IN_SEL_V  0x1
-#define GPIO_SIG73_IN_SEL_S  7
-/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC73_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC73_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC73_IN_INV_SEL_V  0x1
-#define GPIO_FUNC73_IN_INV_SEL_S  6
-/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC73_IN_SEL  0x0000003F
-#define GPIO_FUNC73_IN_SEL_M  ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S))
-#define GPIO_FUNC73_IN_SEL_V  0x3F
-#define GPIO_FUNC73_IN_SEL_S  0
-
-#define GPIO_FUNC74_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0258)
-/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG74_IN_SEL  (BIT(7))
-#define GPIO_SIG74_IN_SEL_M  (BIT(7))
-#define GPIO_SIG74_IN_SEL_V  0x1
-#define GPIO_SIG74_IN_SEL_S  7
-/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC74_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC74_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC74_IN_INV_SEL_V  0x1
-#define GPIO_FUNC74_IN_INV_SEL_S  6
-/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC74_IN_SEL  0x0000003F
-#define GPIO_FUNC74_IN_SEL_M  ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S))
-#define GPIO_FUNC74_IN_SEL_V  0x3F
-#define GPIO_FUNC74_IN_SEL_S  0
-
-#define GPIO_FUNC75_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x025c)
-/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG75_IN_SEL  (BIT(7))
-#define GPIO_SIG75_IN_SEL_M  (BIT(7))
-#define GPIO_SIG75_IN_SEL_V  0x1
-#define GPIO_SIG75_IN_SEL_S  7
-/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC75_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC75_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC75_IN_INV_SEL_V  0x1
-#define GPIO_FUNC75_IN_INV_SEL_S  6
-/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC75_IN_SEL  0x0000003F
-#define GPIO_FUNC75_IN_SEL_M  ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S))
-#define GPIO_FUNC75_IN_SEL_V  0x3F
-#define GPIO_FUNC75_IN_SEL_S  0
-
-#define GPIO_FUNC76_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0260)
-/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG76_IN_SEL  (BIT(7))
-#define GPIO_SIG76_IN_SEL_M  (BIT(7))
-#define GPIO_SIG76_IN_SEL_V  0x1
-#define GPIO_SIG76_IN_SEL_S  7
-/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC76_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC76_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC76_IN_INV_SEL_V  0x1
-#define GPIO_FUNC76_IN_INV_SEL_S  6
-/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC76_IN_SEL  0x0000003F
-#define GPIO_FUNC76_IN_SEL_M  ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S))
-#define GPIO_FUNC76_IN_SEL_V  0x3F
-#define GPIO_FUNC76_IN_SEL_S  0
-
-#define GPIO_FUNC77_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0264)
-/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG77_IN_SEL  (BIT(7))
-#define GPIO_SIG77_IN_SEL_M  (BIT(7))
-#define GPIO_SIG77_IN_SEL_V  0x1
-#define GPIO_SIG77_IN_SEL_S  7
-/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC77_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC77_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC77_IN_INV_SEL_V  0x1
-#define GPIO_FUNC77_IN_INV_SEL_S  6
-/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC77_IN_SEL  0x0000003F
-#define GPIO_FUNC77_IN_SEL_M  ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S))
-#define GPIO_FUNC77_IN_SEL_V  0x3F
-#define GPIO_FUNC77_IN_SEL_S  0
-
-#define GPIO_FUNC78_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0268)
-/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG78_IN_SEL  (BIT(7))
-#define GPIO_SIG78_IN_SEL_M  (BIT(7))
-#define GPIO_SIG78_IN_SEL_V  0x1
-#define GPIO_SIG78_IN_SEL_S  7
-/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC78_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC78_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC78_IN_INV_SEL_V  0x1
-#define GPIO_FUNC78_IN_INV_SEL_S  6
-/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC78_IN_SEL  0x0000003F
-#define GPIO_FUNC78_IN_SEL_M  ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S))
-#define GPIO_FUNC78_IN_SEL_V  0x3F
-#define GPIO_FUNC78_IN_SEL_S  0
-
-#define GPIO_FUNC79_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x026c)
-/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG79_IN_SEL  (BIT(7))
-#define GPIO_SIG79_IN_SEL_M  (BIT(7))
-#define GPIO_SIG79_IN_SEL_V  0x1
-#define GPIO_SIG79_IN_SEL_S  7
-/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC79_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC79_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC79_IN_INV_SEL_V  0x1
-#define GPIO_FUNC79_IN_INV_SEL_S  6
-/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC79_IN_SEL  0x0000003F
-#define GPIO_FUNC79_IN_SEL_M  ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S))
-#define GPIO_FUNC79_IN_SEL_V  0x3F
-#define GPIO_FUNC79_IN_SEL_S  0
-
-#define GPIO_FUNC80_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0270)
-/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG80_IN_SEL  (BIT(7))
-#define GPIO_SIG80_IN_SEL_M  (BIT(7))
-#define GPIO_SIG80_IN_SEL_V  0x1
-#define GPIO_SIG80_IN_SEL_S  7
-/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC80_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC80_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC80_IN_INV_SEL_V  0x1
-#define GPIO_FUNC80_IN_INV_SEL_S  6
-/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC80_IN_SEL  0x0000003F
-#define GPIO_FUNC80_IN_SEL_M  ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S))
-#define GPIO_FUNC80_IN_SEL_V  0x3F
-#define GPIO_FUNC80_IN_SEL_S  0
-
-#define GPIO_FUNC81_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0274)
-/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG81_IN_SEL  (BIT(7))
-#define GPIO_SIG81_IN_SEL_M  (BIT(7))
-#define GPIO_SIG81_IN_SEL_V  0x1
-#define GPIO_SIG81_IN_SEL_S  7
-/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC81_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC81_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC81_IN_INV_SEL_V  0x1
-#define GPIO_FUNC81_IN_INV_SEL_S  6
-/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC81_IN_SEL  0x0000003F
-#define GPIO_FUNC81_IN_SEL_M  ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S))
-#define GPIO_FUNC81_IN_SEL_V  0x3F
-#define GPIO_FUNC81_IN_SEL_S  0
-
-#define GPIO_FUNC82_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0278)
-/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG82_IN_SEL  (BIT(7))
-#define GPIO_SIG82_IN_SEL_M  (BIT(7))
-#define GPIO_SIG82_IN_SEL_V  0x1
-#define GPIO_SIG82_IN_SEL_S  7
-/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC82_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC82_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC82_IN_INV_SEL_V  0x1
-#define GPIO_FUNC82_IN_INV_SEL_S  6
-/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC82_IN_SEL  0x0000003F
-#define GPIO_FUNC82_IN_SEL_M  ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S))
-#define GPIO_FUNC82_IN_SEL_V  0x3F
-#define GPIO_FUNC82_IN_SEL_S  0
-
-#define GPIO_FUNC83_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x027c)
-/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG83_IN_SEL  (BIT(7))
-#define GPIO_SIG83_IN_SEL_M  (BIT(7))
-#define GPIO_SIG83_IN_SEL_V  0x1
-#define GPIO_SIG83_IN_SEL_S  7
-/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC83_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC83_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC83_IN_INV_SEL_V  0x1
-#define GPIO_FUNC83_IN_INV_SEL_S  6
-/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC83_IN_SEL  0x0000003F
-#define GPIO_FUNC83_IN_SEL_M  ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S))
-#define GPIO_FUNC83_IN_SEL_V  0x3F
-#define GPIO_FUNC83_IN_SEL_S  0
-
-#define GPIO_FUNC84_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0280)
-/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG84_IN_SEL  (BIT(7))
-#define GPIO_SIG84_IN_SEL_M  (BIT(7))
-#define GPIO_SIG84_IN_SEL_V  0x1
-#define GPIO_SIG84_IN_SEL_S  7
-/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC84_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC84_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC84_IN_INV_SEL_V  0x1
-#define GPIO_FUNC84_IN_INV_SEL_S  6
-/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC84_IN_SEL  0x0000003F
-#define GPIO_FUNC84_IN_SEL_M  ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S))
-#define GPIO_FUNC84_IN_SEL_V  0x3F
-#define GPIO_FUNC84_IN_SEL_S  0
-
-#define GPIO_FUNC85_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0284)
-/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG85_IN_SEL  (BIT(7))
-#define GPIO_SIG85_IN_SEL_M  (BIT(7))
-#define GPIO_SIG85_IN_SEL_V  0x1
-#define GPIO_SIG85_IN_SEL_S  7
-/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC85_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC85_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC85_IN_INV_SEL_V  0x1
-#define GPIO_FUNC85_IN_INV_SEL_S  6
-/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC85_IN_SEL  0x0000003F
-#define GPIO_FUNC85_IN_SEL_M  ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S))
-#define GPIO_FUNC85_IN_SEL_V  0x3F
-#define GPIO_FUNC85_IN_SEL_S  0
-
-#define GPIO_FUNC86_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0288)
-/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG86_IN_SEL  (BIT(7))
-#define GPIO_SIG86_IN_SEL_M  (BIT(7))
-#define GPIO_SIG86_IN_SEL_V  0x1
-#define GPIO_SIG86_IN_SEL_S  7
-/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC86_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC86_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC86_IN_INV_SEL_V  0x1
-#define GPIO_FUNC86_IN_INV_SEL_S  6
-/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC86_IN_SEL  0x0000003F
-#define GPIO_FUNC86_IN_SEL_M  ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S))
-#define GPIO_FUNC86_IN_SEL_V  0x3F
-#define GPIO_FUNC86_IN_SEL_S  0
-
-#define GPIO_FUNC87_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x028c)
-/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG87_IN_SEL  (BIT(7))
-#define GPIO_SIG87_IN_SEL_M  (BIT(7))
-#define GPIO_SIG87_IN_SEL_V  0x1
-#define GPIO_SIG87_IN_SEL_S  7
-/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC87_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC87_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC87_IN_INV_SEL_V  0x1
-#define GPIO_FUNC87_IN_INV_SEL_S  6
-/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC87_IN_SEL  0x0000003F
-#define GPIO_FUNC87_IN_SEL_M  ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S))
-#define GPIO_FUNC87_IN_SEL_V  0x3F
-#define GPIO_FUNC87_IN_SEL_S  0
-
-#define GPIO_FUNC88_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0290)
-/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG88_IN_SEL  (BIT(7))
-#define GPIO_SIG88_IN_SEL_M  (BIT(7))
-#define GPIO_SIG88_IN_SEL_V  0x1
-#define GPIO_SIG88_IN_SEL_S  7
-/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC88_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC88_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC88_IN_INV_SEL_V  0x1
-#define GPIO_FUNC88_IN_INV_SEL_S  6
-/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC88_IN_SEL  0x0000003F
-#define GPIO_FUNC88_IN_SEL_M  ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S))
-#define GPIO_FUNC88_IN_SEL_V  0x3F
-#define GPIO_FUNC88_IN_SEL_S  0
-
-#define GPIO_FUNC89_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0294)
-/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG89_IN_SEL  (BIT(7))
-#define GPIO_SIG89_IN_SEL_M  (BIT(7))
-#define GPIO_SIG89_IN_SEL_V  0x1
-#define GPIO_SIG89_IN_SEL_S  7
-/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC89_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC89_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC89_IN_INV_SEL_V  0x1
-#define GPIO_FUNC89_IN_INV_SEL_S  6
-/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC89_IN_SEL  0x0000003F
-#define GPIO_FUNC89_IN_SEL_M  ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S))
-#define GPIO_FUNC89_IN_SEL_V  0x3F
-#define GPIO_FUNC89_IN_SEL_S  0
-
-#define GPIO_FUNC90_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0298)
-/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG90_IN_SEL  (BIT(7))
-#define GPIO_SIG90_IN_SEL_M  (BIT(7))
-#define GPIO_SIG90_IN_SEL_V  0x1
-#define GPIO_SIG90_IN_SEL_S  7
-/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC90_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC90_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC90_IN_INV_SEL_V  0x1
-#define GPIO_FUNC90_IN_INV_SEL_S  6
-/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC90_IN_SEL  0x0000003F
-#define GPIO_FUNC90_IN_SEL_M  ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S))
-#define GPIO_FUNC90_IN_SEL_V  0x3F
-#define GPIO_FUNC90_IN_SEL_S  0
-
-#define GPIO_FUNC91_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x029c)
-/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG91_IN_SEL  (BIT(7))
-#define GPIO_SIG91_IN_SEL_M  (BIT(7))
-#define GPIO_SIG91_IN_SEL_V  0x1
-#define GPIO_SIG91_IN_SEL_S  7
-/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC91_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC91_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC91_IN_INV_SEL_V  0x1
-#define GPIO_FUNC91_IN_INV_SEL_S  6
-/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC91_IN_SEL  0x0000003F
-#define GPIO_FUNC91_IN_SEL_M  ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S))
-#define GPIO_FUNC91_IN_SEL_V  0x3F
-#define GPIO_FUNC91_IN_SEL_S  0
-
-#define GPIO_FUNC92_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02a0)
-/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG92_IN_SEL  (BIT(7))
-#define GPIO_SIG92_IN_SEL_M  (BIT(7))
-#define GPIO_SIG92_IN_SEL_V  0x1
-#define GPIO_SIG92_IN_SEL_S  7
-/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC92_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC92_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC92_IN_INV_SEL_V  0x1
-#define GPIO_FUNC92_IN_INV_SEL_S  6
-/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC92_IN_SEL  0x0000003F
-#define GPIO_FUNC92_IN_SEL_M  ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S))
-#define GPIO_FUNC92_IN_SEL_V  0x3F
-#define GPIO_FUNC92_IN_SEL_S  0
-
-#define GPIO_FUNC93_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02a4)
-/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG93_IN_SEL  (BIT(7))
-#define GPIO_SIG93_IN_SEL_M  (BIT(7))
-#define GPIO_SIG93_IN_SEL_V  0x1
-#define GPIO_SIG93_IN_SEL_S  7
-/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC93_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC93_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC93_IN_INV_SEL_V  0x1
-#define GPIO_FUNC93_IN_INV_SEL_S  6
-/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC93_IN_SEL  0x0000003F
-#define GPIO_FUNC93_IN_SEL_M  ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S))
-#define GPIO_FUNC93_IN_SEL_V  0x3F
-#define GPIO_FUNC93_IN_SEL_S  0
-
-#define GPIO_FUNC94_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02a8)
-/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG94_IN_SEL  (BIT(7))
-#define GPIO_SIG94_IN_SEL_M  (BIT(7))
-#define GPIO_SIG94_IN_SEL_V  0x1
-#define GPIO_SIG94_IN_SEL_S  7
-/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC94_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC94_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC94_IN_INV_SEL_V  0x1
-#define GPIO_FUNC94_IN_INV_SEL_S  6
-/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC94_IN_SEL  0x0000003F
-#define GPIO_FUNC94_IN_SEL_M  ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S))
-#define GPIO_FUNC94_IN_SEL_V  0x3F
-#define GPIO_FUNC94_IN_SEL_S  0
-
-#define GPIO_FUNC95_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02ac)
-/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG95_IN_SEL  (BIT(7))
-#define GPIO_SIG95_IN_SEL_M  (BIT(7))
-#define GPIO_SIG95_IN_SEL_V  0x1
-#define GPIO_SIG95_IN_SEL_S  7
-/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC95_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC95_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC95_IN_INV_SEL_V  0x1
-#define GPIO_FUNC95_IN_INV_SEL_S  6
-/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC95_IN_SEL  0x0000003F
-#define GPIO_FUNC95_IN_SEL_M  ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S))
-#define GPIO_FUNC95_IN_SEL_V  0x3F
-#define GPIO_FUNC95_IN_SEL_S  0
-
-#define GPIO_FUNC96_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02b0)
-/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG96_IN_SEL  (BIT(7))
-#define GPIO_SIG96_IN_SEL_M  (BIT(7))
-#define GPIO_SIG96_IN_SEL_V  0x1
-#define GPIO_SIG96_IN_SEL_S  7
-/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC96_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC96_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC96_IN_INV_SEL_V  0x1
-#define GPIO_FUNC96_IN_INV_SEL_S  6
-/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC96_IN_SEL  0x0000003F
-#define GPIO_FUNC96_IN_SEL_M  ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S))
-#define GPIO_FUNC96_IN_SEL_V  0x3F
-#define GPIO_FUNC96_IN_SEL_S  0
-
-#define GPIO_FUNC97_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02b4)
-/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG97_IN_SEL  (BIT(7))
-#define GPIO_SIG97_IN_SEL_M  (BIT(7))
-#define GPIO_SIG97_IN_SEL_V  0x1
-#define GPIO_SIG97_IN_SEL_S  7
-/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC97_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC97_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC97_IN_INV_SEL_V  0x1
-#define GPIO_FUNC97_IN_INV_SEL_S  6
-/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC97_IN_SEL  0x0000003F
-#define GPIO_FUNC97_IN_SEL_M  ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S))
-#define GPIO_FUNC97_IN_SEL_V  0x3F
-#define GPIO_FUNC97_IN_SEL_S  0
-
-#define GPIO_FUNC98_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02b8)
-/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG98_IN_SEL  (BIT(7))
-#define GPIO_SIG98_IN_SEL_M  (BIT(7))
-#define GPIO_SIG98_IN_SEL_V  0x1
-#define GPIO_SIG98_IN_SEL_S  7
-/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC98_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC98_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC98_IN_INV_SEL_V  0x1
-#define GPIO_FUNC98_IN_INV_SEL_S  6
-/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC98_IN_SEL  0x0000003F
-#define GPIO_FUNC98_IN_SEL_M  ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S))
-#define GPIO_FUNC98_IN_SEL_V  0x3F
-#define GPIO_FUNC98_IN_SEL_S  0
-
-#define GPIO_FUNC99_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02bc)
-/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG99_IN_SEL  (BIT(7))
-#define GPIO_SIG99_IN_SEL_M  (BIT(7))
-#define GPIO_SIG99_IN_SEL_V  0x1
-#define GPIO_SIG99_IN_SEL_S  7
-/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC99_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC99_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC99_IN_INV_SEL_V  0x1
-#define GPIO_FUNC99_IN_INV_SEL_S  6
-/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC99_IN_SEL  0x0000003F
-#define GPIO_FUNC99_IN_SEL_M  ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S))
-#define GPIO_FUNC99_IN_SEL_V  0x3F
-#define GPIO_FUNC99_IN_SEL_S  0
-
-#define GPIO_FUNC100_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02c0)
-/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG100_IN_SEL  (BIT(7))
-#define GPIO_SIG100_IN_SEL_M  (BIT(7))
-#define GPIO_SIG100_IN_SEL_V  0x1
-#define GPIO_SIG100_IN_SEL_S  7
-/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC100_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC100_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC100_IN_INV_SEL_V  0x1
-#define GPIO_FUNC100_IN_INV_SEL_S  6
-/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC100_IN_SEL  0x0000003F
-#define GPIO_FUNC100_IN_SEL_M  ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S))
-#define GPIO_FUNC100_IN_SEL_V  0x3F
-#define GPIO_FUNC100_IN_SEL_S  0
-
-#define GPIO_FUNC101_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02c4)
-/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG101_IN_SEL  (BIT(7))
-#define GPIO_SIG101_IN_SEL_M  (BIT(7))
-#define GPIO_SIG101_IN_SEL_V  0x1
-#define GPIO_SIG101_IN_SEL_S  7
-/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC101_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC101_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC101_IN_INV_SEL_V  0x1
-#define GPIO_FUNC101_IN_INV_SEL_S  6
-/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC101_IN_SEL  0x0000003F
-#define GPIO_FUNC101_IN_SEL_M  ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S))
-#define GPIO_FUNC101_IN_SEL_V  0x3F
-#define GPIO_FUNC101_IN_SEL_S  0
-
-#define GPIO_FUNC102_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02c8)
-/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG102_IN_SEL  (BIT(7))
-#define GPIO_SIG102_IN_SEL_M  (BIT(7))
-#define GPIO_SIG102_IN_SEL_V  0x1
-#define GPIO_SIG102_IN_SEL_S  7
-/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC102_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC102_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC102_IN_INV_SEL_V  0x1
-#define GPIO_FUNC102_IN_INV_SEL_S  6
-/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC102_IN_SEL  0x0000003F
-#define GPIO_FUNC102_IN_SEL_M  ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S))
-#define GPIO_FUNC102_IN_SEL_V  0x3F
-#define GPIO_FUNC102_IN_SEL_S  0
-
-#define GPIO_FUNC103_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02cc)
-/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG103_IN_SEL  (BIT(7))
-#define GPIO_SIG103_IN_SEL_M  (BIT(7))
-#define GPIO_SIG103_IN_SEL_V  0x1
-#define GPIO_SIG103_IN_SEL_S  7
-/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC103_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC103_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC103_IN_INV_SEL_V  0x1
-#define GPIO_FUNC103_IN_INV_SEL_S  6
-/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC103_IN_SEL  0x0000003F
-#define GPIO_FUNC103_IN_SEL_M  ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S))
-#define GPIO_FUNC103_IN_SEL_V  0x3F
-#define GPIO_FUNC103_IN_SEL_S  0
-
-#define GPIO_FUNC104_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02d0)
-/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG104_IN_SEL  (BIT(7))
-#define GPIO_SIG104_IN_SEL_M  (BIT(7))
-#define GPIO_SIG104_IN_SEL_V  0x1
-#define GPIO_SIG104_IN_SEL_S  7
-/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC104_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC104_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC104_IN_INV_SEL_V  0x1
-#define GPIO_FUNC104_IN_INV_SEL_S  6
-/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC104_IN_SEL  0x0000003F
-#define GPIO_FUNC104_IN_SEL_M  ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S))
-#define GPIO_FUNC104_IN_SEL_V  0x3F
-#define GPIO_FUNC104_IN_SEL_S  0
-
-#define GPIO_FUNC105_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02d4)
-/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG105_IN_SEL  (BIT(7))
-#define GPIO_SIG105_IN_SEL_M  (BIT(7))
-#define GPIO_SIG105_IN_SEL_V  0x1
-#define GPIO_SIG105_IN_SEL_S  7
-/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC105_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC105_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC105_IN_INV_SEL_V  0x1
-#define GPIO_FUNC105_IN_INV_SEL_S  6
-/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC105_IN_SEL  0x0000003F
-#define GPIO_FUNC105_IN_SEL_M  ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S))
-#define GPIO_FUNC105_IN_SEL_V  0x3F
-#define GPIO_FUNC105_IN_SEL_S  0
-
-#define GPIO_FUNC106_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02d8)
-/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG106_IN_SEL  (BIT(7))
-#define GPIO_SIG106_IN_SEL_M  (BIT(7))
-#define GPIO_SIG106_IN_SEL_V  0x1
-#define GPIO_SIG106_IN_SEL_S  7
-/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC106_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC106_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC106_IN_INV_SEL_V  0x1
-#define GPIO_FUNC106_IN_INV_SEL_S  6
-/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC106_IN_SEL  0x0000003F
-#define GPIO_FUNC106_IN_SEL_M  ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S))
-#define GPIO_FUNC106_IN_SEL_V  0x3F
-#define GPIO_FUNC106_IN_SEL_S  0
-
-#define GPIO_FUNC107_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02dc)
-/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG107_IN_SEL  (BIT(7))
-#define GPIO_SIG107_IN_SEL_M  (BIT(7))
-#define GPIO_SIG107_IN_SEL_V  0x1
-#define GPIO_SIG107_IN_SEL_S  7
-/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC107_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC107_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC107_IN_INV_SEL_V  0x1
-#define GPIO_FUNC107_IN_INV_SEL_S  6
-/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC107_IN_SEL  0x0000003F
-#define GPIO_FUNC107_IN_SEL_M  ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S))
-#define GPIO_FUNC107_IN_SEL_V  0x3F
-#define GPIO_FUNC107_IN_SEL_S  0
-
-#define GPIO_FUNC108_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02e0)
-/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG108_IN_SEL  (BIT(7))
-#define GPIO_SIG108_IN_SEL_M  (BIT(7))
-#define GPIO_SIG108_IN_SEL_V  0x1
-#define GPIO_SIG108_IN_SEL_S  7
-/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC108_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC108_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC108_IN_INV_SEL_V  0x1
-#define GPIO_FUNC108_IN_INV_SEL_S  6
-/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC108_IN_SEL  0x0000003F
-#define GPIO_FUNC108_IN_SEL_M  ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S))
-#define GPIO_FUNC108_IN_SEL_V  0x3F
-#define GPIO_FUNC108_IN_SEL_S  0
-
-#define GPIO_FUNC109_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02e4)
-/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG109_IN_SEL  (BIT(7))
-#define GPIO_SIG109_IN_SEL_M  (BIT(7))
-#define GPIO_SIG109_IN_SEL_V  0x1
-#define GPIO_SIG109_IN_SEL_S  7
-/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC109_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC109_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC109_IN_INV_SEL_V  0x1
-#define GPIO_FUNC109_IN_INV_SEL_S  6
-/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC109_IN_SEL  0x0000003F
-#define GPIO_FUNC109_IN_SEL_M  ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S))
-#define GPIO_FUNC109_IN_SEL_V  0x3F
-#define GPIO_FUNC109_IN_SEL_S  0
-
-#define GPIO_FUNC110_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02e8)
-/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG110_IN_SEL  (BIT(7))
-#define GPIO_SIG110_IN_SEL_M  (BIT(7))
-#define GPIO_SIG110_IN_SEL_V  0x1
-#define GPIO_SIG110_IN_SEL_S  7
-/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC110_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC110_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC110_IN_INV_SEL_V  0x1
-#define GPIO_FUNC110_IN_INV_SEL_S  6
-/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC110_IN_SEL  0x0000003F
-#define GPIO_FUNC110_IN_SEL_M  ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S))
-#define GPIO_FUNC110_IN_SEL_V  0x3F
-#define GPIO_FUNC110_IN_SEL_S  0
-
-#define GPIO_FUNC111_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02ec)
-/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG111_IN_SEL  (BIT(7))
-#define GPIO_SIG111_IN_SEL_M  (BIT(7))
-#define GPIO_SIG111_IN_SEL_V  0x1
-#define GPIO_SIG111_IN_SEL_S  7
-/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC111_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC111_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC111_IN_INV_SEL_V  0x1
-#define GPIO_FUNC111_IN_INV_SEL_S  6
-/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC111_IN_SEL  0x0000003F
-#define GPIO_FUNC111_IN_SEL_M  ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S))
-#define GPIO_FUNC111_IN_SEL_V  0x3F
-#define GPIO_FUNC111_IN_SEL_S  0
-
-#define GPIO_FUNC112_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02f0)
-/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG112_IN_SEL  (BIT(7))
-#define GPIO_SIG112_IN_SEL_M  (BIT(7))
-#define GPIO_SIG112_IN_SEL_V  0x1
-#define GPIO_SIG112_IN_SEL_S  7
-/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC112_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC112_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC112_IN_INV_SEL_V  0x1
-#define GPIO_FUNC112_IN_INV_SEL_S  6
-/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC112_IN_SEL  0x0000003F
-#define GPIO_FUNC112_IN_SEL_M  ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S))
-#define GPIO_FUNC112_IN_SEL_V  0x3F
-#define GPIO_FUNC112_IN_SEL_S  0
-
-#define GPIO_FUNC113_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02f4)
-/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG113_IN_SEL  (BIT(7))
-#define GPIO_SIG113_IN_SEL_M  (BIT(7))
-#define GPIO_SIG113_IN_SEL_V  0x1
-#define GPIO_SIG113_IN_SEL_S  7
-/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC113_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC113_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC113_IN_INV_SEL_V  0x1
-#define GPIO_FUNC113_IN_INV_SEL_S  6
-/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC113_IN_SEL  0x0000003F
-#define GPIO_FUNC113_IN_SEL_M  ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S))
-#define GPIO_FUNC113_IN_SEL_V  0x3F
-#define GPIO_FUNC113_IN_SEL_S  0
-
-#define GPIO_FUNC114_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02f8)
-/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG114_IN_SEL  (BIT(7))
-#define GPIO_SIG114_IN_SEL_M  (BIT(7))
-#define GPIO_SIG114_IN_SEL_V  0x1
-#define GPIO_SIG114_IN_SEL_S  7
-/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC114_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC114_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC114_IN_INV_SEL_V  0x1
-#define GPIO_FUNC114_IN_INV_SEL_S  6
-/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC114_IN_SEL  0x0000003F
-#define GPIO_FUNC114_IN_SEL_M  ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S))
-#define GPIO_FUNC114_IN_SEL_V  0x3F
-#define GPIO_FUNC114_IN_SEL_S  0
-
-#define GPIO_FUNC115_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x02fc)
-/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG115_IN_SEL  (BIT(7))
-#define GPIO_SIG115_IN_SEL_M  (BIT(7))
-#define GPIO_SIG115_IN_SEL_V  0x1
-#define GPIO_SIG115_IN_SEL_S  7
-/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC115_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC115_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC115_IN_INV_SEL_V  0x1
-#define GPIO_FUNC115_IN_INV_SEL_S  6
-/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC115_IN_SEL  0x0000003F
-#define GPIO_FUNC115_IN_SEL_M  ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S))
-#define GPIO_FUNC115_IN_SEL_V  0x3F
-#define GPIO_FUNC115_IN_SEL_S  0
-
-#define GPIO_FUNC116_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0300)
-/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG116_IN_SEL  (BIT(7))
-#define GPIO_SIG116_IN_SEL_M  (BIT(7))
-#define GPIO_SIG116_IN_SEL_V  0x1
-#define GPIO_SIG116_IN_SEL_S  7
-/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC116_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC116_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC116_IN_INV_SEL_V  0x1
-#define GPIO_FUNC116_IN_INV_SEL_S  6
-/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC116_IN_SEL  0x0000003F
-#define GPIO_FUNC116_IN_SEL_M  ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S))
-#define GPIO_FUNC116_IN_SEL_V  0x3F
-#define GPIO_FUNC116_IN_SEL_S  0
-
-#define GPIO_FUNC117_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0304)
-/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG117_IN_SEL  (BIT(7))
-#define GPIO_SIG117_IN_SEL_M  (BIT(7))
-#define GPIO_SIG117_IN_SEL_V  0x1
-#define GPIO_SIG117_IN_SEL_S  7
-/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC117_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC117_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC117_IN_INV_SEL_V  0x1
-#define GPIO_FUNC117_IN_INV_SEL_S  6
-/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC117_IN_SEL  0x0000003F
-#define GPIO_FUNC117_IN_SEL_M  ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S))
-#define GPIO_FUNC117_IN_SEL_V  0x3F
-#define GPIO_FUNC117_IN_SEL_S  0
-
-#define GPIO_FUNC118_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0308)
-/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG118_IN_SEL  (BIT(7))
-#define GPIO_SIG118_IN_SEL_M  (BIT(7))
-#define GPIO_SIG118_IN_SEL_V  0x1
-#define GPIO_SIG118_IN_SEL_S  7
-/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC118_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC118_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC118_IN_INV_SEL_V  0x1
-#define GPIO_FUNC118_IN_INV_SEL_S  6
-/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC118_IN_SEL  0x0000003F
-#define GPIO_FUNC118_IN_SEL_M  ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S))
-#define GPIO_FUNC118_IN_SEL_V  0x3F
-#define GPIO_FUNC118_IN_SEL_S  0
-
-#define GPIO_FUNC119_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x030c)
-/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG119_IN_SEL  (BIT(7))
-#define GPIO_SIG119_IN_SEL_M  (BIT(7))
-#define GPIO_SIG119_IN_SEL_V  0x1
-#define GPIO_SIG119_IN_SEL_S  7
-/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC119_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC119_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC119_IN_INV_SEL_V  0x1
-#define GPIO_FUNC119_IN_INV_SEL_S  6
-/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC119_IN_SEL  0x0000003F
-#define GPIO_FUNC119_IN_SEL_M  ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S))
-#define GPIO_FUNC119_IN_SEL_V  0x3F
-#define GPIO_FUNC119_IN_SEL_S  0
-
-#define GPIO_FUNC120_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0310)
-/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG120_IN_SEL  (BIT(7))
-#define GPIO_SIG120_IN_SEL_M  (BIT(7))
-#define GPIO_SIG120_IN_SEL_V  0x1
-#define GPIO_SIG120_IN_SEL_S  7
-/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC120_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC120_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC120_IN_INV_SEL_V  0x1
-#define GPIO_FUNC120_IN_INV_SEL_S  6
-/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC120_IN_SEL  0x0000003F
-#define GPIO_FUNC120_IN_SEL_M  ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S))
-#define GPIO_FUNC120_IN_SEL_V  0x3F
-#define GPIO_FUNC120_IN_SEL_S  0
-
-#define GPIO_FUNC121_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0314)
-/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG121_IN_SEL  (BIT(7))
-#define GPIO_SIG121_IN_SEL_M  (BIT(7))
-#define GPIO_SIG121_IN_SEL_V  0x1
-#define GPIO_SIG121_IN_SEL_S  7
-/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC121_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC121_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC121_IN_INV_SEL_V  0x1
-#define GPIO_FUNC121_IN_INV_SEL_S  6
-/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC121_IN_SEL  0x0000003F
-#define GPIO_FUNC121_IN_SEL_M  ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S))
-#define GPIO_FUNC121_IN_SEL_V  0x3F
-#define GPIO_FUNC121_IN_SEL_S  0
-
-#define GPIO_FUNC122_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0318)
-/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG122_IN_SEL  (BIT(7))
-#define GPIO_SIG122_IN_SEL_M  (BIT(7))
-#define GPIO_SIG122_IN_SEL_V  0x1
-#define GPIO_SIG122_IN_SEL_S  7
-/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC122_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC122_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC122_IN_INV_SEL_V  0x1
-#define GPIO_FUNC122_IN_INV_SEL_S  6
-/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC122_IN_SEL  0x0000003F
-#define GPIO_FUNC122_IN_SEL_M  ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S))
-#define GPIO_FUNC122_IN_SEL_V  0x3F
-#define GPIO_FUNC122_IN_SEL_S  0
-
-#define GPIO_FUNC123_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x031c)
-/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG123_IN_SEL  (BIT(7))
-#define GPIO_SIG123_IN_SEL_M  (BIT(7))
-#define GPIO_SIG123_IN_SEL_V  0x1
-#define GPIO_SIG123_IN_SEL_S  7
-/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC123_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC123_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC123_IN_INV_SEL_V  0x1
-#define GPIO_FUNC123_IN_INV_SEL_S  6
-/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC123_IN_SEL  0x0000003F
-#define GPIO_FUNC123_IN_SEL_M  ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S))
-#define GPIO_FUNC123_IN_SEL_V  0x3F
-#define GPIO_FUNC123_IN_SEL_S  0
-
-#define GPIO_FUNC124_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0320)
-/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG124_IN_SEL  (BIT(7))
-#define GPIO_SIG124_IN_SEL_M  (BIT(7))
-#define GPIO_SIG124_IN_SEL_V  0x1
-#define GPIO_SIG124_IN_SEL_S  7
-/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC124_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC124_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC124_IN_INV_SEL_V  0x1
-#define GPIO_FUNC124_IN_INV_SEL_S  6
-/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC124_IN_SEL  0x0000003F
-#define GPIO_FUNC124_IN_SEL_M  ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S))
-#define GPIO_FUNC124_IN_SEL_V  0x3F
-#define GPIO_FUNC124_IN_SEL_S  0
-
-#define GPIO_FUNC125_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0324)
-/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG125_IN_SEL  (BIT(7))
-#define GPIO_SIG125_IN_SEL_M  (BIT(7))
-#define GPIO_SIG125_IN_SEL_V  0x1
-#define GPIO_SIG125_IN_SEL_S  7
-/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC125_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC125_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC125_IN_INV_SEL_V  0x1
-#define GPIO_FUNC125_IN_INV_SEL_S  6
-/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC125_IN_SEL  0x0000003F
-#define GPIO_FUNC125_IN_SEL_M  ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S))
-#define GPIO_FUNC125_IN_SEL_V  0x3F
-#define GPIO_FUNC125_IN_SEL_S  0
-
-#define GPIO_FUNC126_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0328)
-/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG126_IN_SEL  (BIT(7))
-#define GPIO_SIG126_IN_SEL_M  (BIT(7))
-#define GPIO_SIG126_IN_SEL_V  0x1
-#define GPIO_SIG126_IN_SEL_S  7
-/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC126_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC126_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC126_IN_INV_SEL_V  0x1
-#define GPIO_FUNC126_IN_INV_SEL_S  6
-/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC126_IN_SEL  0x0000003F
-#define GPIO_FUNC126_IN_SEL_M  ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S))
-#define GPIO_FUNC126_IN_SEL_V  0x3F
-#define GPIO_FUNC126_IN_SEL_S  0
-
-#define GPIO_FUNC127_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x032c)
-/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG127_IN_SEL  (BIT(7))
-#define GPIO_SIG127_IN_SEL_M  (BIT(7))
-#define GPIO_SIG127_IN_SEL_V  0x1
-#define GPIO_SIG127_IN_SEL_S  7
-/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC127_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC127_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC127_IN_INV_SEL_V  0x1
-#define GPIO_FUNC127_IN_INV_SEL_S  6
-/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC127_IN_SEL  0x0000003F
-#define GPIO_FUNC127_IN_SEL_M  ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S))
-#define GPIO_FUNC127_IN_SEL_V  0x3F
-#define GPIO_FUNC127_IN_SEL_S  0
-
-#define GPIO_FUNC128_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0330)
-/* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG128_IN_SEL  (BIT(7))
-#define GPIO_SIG128_IN_SEL_M  (BIT(7))
-#define GPIO_SIG128_IN_SEL_V  0x1
-#define GPIO_SIG128_IN_SEL_S  7
-/* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC128_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC128_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC128_IN_INV_SEL_V  0x1
-#define GPIO_FUNC128_IN_INV_SEL_S  6
-/* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC128_IN_SEL  0x0000003F
-#define GPIO_FUNC128_IN_SEL_M  ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S))
-#define GPIO_FUNC128_IN_SEL_V  0x3F
-#define GPIO_FUNC128_IN_SEL_S  0
-
-#define GPIO_FUNC129_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0334)
-/* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG129_IN_SEL  (BIT(7))
-#define GPIO_SIG129_IN_SEL_M  (BIT(7))
-#define GPIO_SIG129_IN_SEL_V  0x1
-#define GPIO_SIG129_IN_SEL_S  7
-/* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC129_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC129_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC129_IN_INV_SEL_V  0x1
-#define GPIO_FUNC129_IN_INV_SEL_S  6
-/* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC129_IN_SEL  0x0000003F
-#define GPIO_FUNC129_IN_SEL_M  ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S))
-#define GPIO_FUNC129_IN_SEL_V  0x3F
-#define GPIO_FUNC129_IN_SEL_S  0
-
-#define GPIO_FUNC130_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0338)
-/* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG130_IN_SEL  (BIT(7))
-#define GPIO_SIG130_IN_SEL_M  (BIT(7))
-#define GPIO_SIG130_IN_SEL_V  0x1
-#define GPIO_SIG130_IN_SEL_S  7
-/* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC130_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC130_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC130_IN_INV_SEL_V  0x1
-#define GPIO_FUNC130_IN_INV_SEL_S  6
-/* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC130_IN_SEL  0x0000003F
-#define GPIO_FUNC130_IN_SEL_M  ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S))
-#define GPIO_FUNC130_IN_SEL_V  0x3F
-#define GPIO_FUNC130_IN_SEL_S  0
-
-#define GPIO_FUNC131_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x033c)
-/* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG131_IN_SEL  (BIT(7))
-#define GPIO_SIG131_IN_SEL_M  (BIT(7))
-#define GPIO_SIG131_IN_SEL_V  0x1
-#define GPIO_SIG131_IN_SEL_S  7
-/* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC131_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC131_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC131_IN_INV_SEL_V  0x1
-#define GPIO_FUNC131_IN_INV_SEL_S  6
-/* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC131_IN_SEL  0x0000003F
-#define GPIO_FUNC131_IN_SEL_M  ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S))
-#define GPIO_FUNC131_IN_SEL_V  0x3F
-#define GPIO_FUNC131_IN_SEL_S  0
-
-#define GPIO_FUNC132_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0340)
-/* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG132_IN_SEL  (BIT(7))
-#define GPIO_SIG132_IN_SEL_M  (BIT(7))
-#define GPIO_SIG132_IN_SEL_V  0x1
-#define GPIO_SIG132_IN_SEL_S  7
-/* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC132_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC132_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC132_IN_INV_SEL_V  0x1
-#define GPIO_FUNC132_IN_INV_SEL_S  6
-/* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC132_IN_SEL  0x0000003F
-#define GPIO_FUNC132_IN_SEL_M  ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S))
-#define GPIO_FUNC132_IN_SEL_V  0x3F
-#define GPIO_FUNC132_IN_SEL_S  0
-
-#define GPIO_FUNC133_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0344)
-/* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG133_IN_SEL  (BIT(7))
-#define GPIO_SIG133_IN_SEL_M  (BIT(7))
-#define GPIO_SIG133_IN_SEL_V  0x1
-#define GPIO_SIG133_IN_SEL_S  7
-/* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC133_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC133_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC133_IN_INV_SEL_V  0x1
-#define GPIO_FUNC133_IN_INV_SEL_S  6
-/* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC133_IN_SEL  0x0000003F
-#define GPIO_FUNC133_IN_SEL_M  ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S))
-#define GPIO_FUNC133_IN_SEL_V  0x3F
-#define GPIO_FUNC133_IN_SEL_S  0
-
-#define GPIO_FUNC134_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0348)
-/* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG134_IN_SEL  (BIT(7))
-#define GPIO_SIG134_IN_SEL_M  (BIT(7))
-#define GPIO_SIG134_IN_SEL_V  0x1
-#define GPIO_SIG134_IN_SEL_S  7
-/* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC134_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC134_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC134_IN_INV_SEL_V  0x1
-#define GPIO_FUNC134_IN_INV_SEL_S  6
-/* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC134_IN_SEL  0x0000003F
-#define GPIO_FUNC134_IN_SEL_M  ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S))
-#define GPIO_FUNC134_IN_SEL_V  0x3F
-#define GPIO_FUNC134_IN_SEL_S  0
-
-#define GPIO_FUNC135_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x034c)
-/* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG135_IN_SEL  (BIT(7))
-#define GPIO_SIG135_IN_SEL_M  (BIT(7))
-#define GPIO_SIG135_IN_SEL_V  0x1
-#define GPIO_SIG135_IN_SEL_S  7
-/* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC135_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC135_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC135_IN_INV_SEL_V  0x1
-#define GPIO_FUNC135_IN_INV_SEL_S  6
-/* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC135_IN_SEL  0x0000003F
-#define GPIO_FUNC135_IN_SEL_M  ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S))
-#define GPIO_FUNC135_IN_SEL_V  0x3F
-#define GPIO_FUNC135_IN_SEL_S  0
-
-#define GPIO_FUNC136_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0350)
-/* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG136_IN_SEL  (BIT(7))
-#define GPIO_SIG136_IN_SEL_M  (BIT(7))
-#define GPIO_SIG136_IN_SEL_V  0x1
-#define GPIO_SIG136_IN_SEL_S  7
-/* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC136_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC136_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC136_IN_INV_SEL_V  0x1
-#define GPIO_FUNC136_IN_INV_SEL_S  6
-/* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC136_IN_SEL  0x0000003F
-#define GPIO_FUNC136_IN_SEL_M  ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S))
-#define GPIO_FUNC136_IN_SEL_V  0x3F
-#define GPIO_FUNC136_IN_SEL_S  0
-
-#define GPIO_FUNC137_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0354)
-/* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG137_IN_SEL  (BIT(7))
-#define GPIO_SIG137_IN_SEL_M  (BIT(7))
-#define GPIO_SIG137_IN_SEL_V  0x1
-#define GPIO_SIG137_IN_SEL_S  7
-/* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC137_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC137_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC137_IN_INV_SEL_V  0x1
-#define GPIO_FUNC137_IN_INV_SEL_S  6
-/* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC137_IN_SEL  0x0000003F
-#define GPIO_FUNC137_IN_SEL_M  ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S))
-#define GPIO_FUNC137_IN_SEL_V  0x3F
-#define GPIO_FUNC137_IN_SEL_S  0
-
-#define GPIO_FUNC138_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0358)
-/* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG138_IN_SEL  (BIT(7))
-#define GPIO_SIG138_IN_SEL_M  (BIT(7))
-#define GPIO_SIG138_IN_SEL_V  0x1
-#define GPIO_SIG138_IN_SEL_S  7
-/* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC138_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC138_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC138_IN_INV_SEL_V  0x1
-#define GPIO_FUNC138_IN_INV_SEL_S  6
-/* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC138_IN_SEL  0x0000003F
-#define GPIO_FUNC138_IN_SEL_M  ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S))
-#define GPIO_FUNC138_IN_SEL_V  0x3F
-#define GPIO_FUNC138_IN_SEL_S  0
-
-#define GPIO_FUNC139_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x035c)
-/* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG139_IN_SEL  (BIT(7))
-#define GPIO_SIG139_IN_SEL_M  (BIT(7))
-#define GPIO_SIG139_IN_SEL_V  0x1
-#define GPIO_SIG139_IN_SEL_S  7
-/* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC139_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC139_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC139_IN_INV_SEL_V  0x1
-#define GPIO_FUNC139_IN_INV_SEL_S  6
-/* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC139_IN_SEL  0x0000003F
-#define GPIO_FUNC139_IN_SEL_M  ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S))
-#define GPIO_FUNC139_IN_SEL_V  0x3F
-#define GPIO_FUNC139_IN_SEL_S  0
-
-#define GPIO_FUNC140_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0360)
-/* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG140_IN_SEL  (BIT(7))
-#define GPIO_SIG140_IN_SEL_M  (BIT(7))
-#define GPIO_SIG140_IN_SEL_V  0x1
-#define GPIO_SIG140_IN_SEL_S  7
-/* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC140_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC140_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC140_IN_INV_SEL_V  0x1
-#define GPIO_FUNC140_IN_INV_SEL_S  6
-/* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC140_IN_SEL  0x0000003F
-#define GPIO_FUNC140_IN_SEL_M  ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S))
-#define GPIO_FUNC140_IN_SEL_V  0x3F
-#define GPIO_FUNC140_IN_SEL_S  0
-
-#define GPIO_FUNC141_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0364)
-/* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG141_IN_SEL  (BIT(7))
-#define GPIO_SIG141_IN_SEL_M  (BIT(7))
-#define GPIO_SIG141_IN_SEL_V  0x1
-#define GPIO_SIG141_IN_SEL_S  7
-/* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC141_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC141_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC141_IN_INV_SEL_V  0x1
-#define GPIO_FUNC141_IN_INV_SEL_S  6
-/* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC141_IN_SEL  0x0000003F
-#define GPIO_FUNC141_IN_SEL_M  ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S))
-#define GPIO_FUNC141_IN_SEL_V  0x3F
-#define GPIO_FUNC141_IN_SEL_S  0
-
-#define GPIO_FUNC142_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0368)
-/* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG142_IN_SEL  (BIT(7))
-#define GPIO_SIG142_IN_SEL_M  (BIT(7))
-#define GPIO_SIG142_IN_SEL_V  0x1
-#define GPIO_SIG142_IN_SEL_S  7
-/* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC142_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC142_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC142_IN_INV_SEL_V  0x1
-#define GPIO_FUNC142_IN_INV_SEL_S  6
-/* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC142_IN_SEL  0x0000003F
-#define GPIO_FUNC142_IN_SEL_M  ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S))
-#define GPIO_FUNC142_IN_SEL_V  0x3F
-#define GPIO_FUNC142_IN_SEL_S  0
-
-#define GPIO_FUNC143_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x036c)
-/* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG143_IN_SEL  (BIT(7))
-#define GPIO_SIG143_IN_SEL_M  (BIT(7))
-#define GPIO_SIG143_IN_SEL_V  0x1
-#define GPIO_SIG143_IN_SEL_S  7
-/* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC143_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC143_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC143_IN_INV_SEL_V  0x1
-#define GPIO_FUNC143_IN_INV_SEL_S  6
-/* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC143_IN_SEL  0x0000003F
-#define GPIO_FUNC143_IN_SEL_M  ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S))
-#define GPIO_FUNC143_IN_SEL_V  0x3F
-#define GPIO_FUNC143_IN_SEL_S  0
-
-#define GPIO_FUNC144_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0370)
-/* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG144_IN_SEL  (BIT(7))
-#define GPIO_SIG144_IN_SEL_M  (BIT(7))
-#define GPIO_SIG144_IN_SEL_V  0x1
-#define GPIO_SIG144_IN_SEL_S  7
-/* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC144_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC144_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC144_IN_INV_SEL_V  0x1
-#define GPIO_FUNC144_IN_INV_SEL_S  6
-/* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC144_IN_SEL  0x0000003F
-#define GPIO_FUNC144_IN_SEL_M  ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S))
-#define GPIO_FUNC144_IN_SEL_V  0x3F
-#define GPIO_FUNC144_IN_SEL_S  0
-
-#define GPIO_FUNC145_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0374)
-/* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG145_IN_SEL  (BIT(7))
-#define GPIO_SIG145_IN_SEL_M  (BIT(7))
-#define GPIO_SIG145_IN_SEL_V  0x1
-#define GPIO_SIG145_IN_SEL_S  7
-/* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC145_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC145_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC145_IN_INV_SEL_V  0x1
-#define GPIO_FUNC145_IN_INV_SEL_S  6
-/* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC145_IN_SEL  0x0000003F
-#define GPIO_FUNC145_IN_SEL_M  ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S))
-#define GPIO_FUNC145_IN_SEL_V  0x3F
-#define GPIO_FUNC145_IN_SEL_S  0
-
-#define GPIO_FUNC146_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0378)
-/* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG146_IN_SEL  (BIT(7))
-#define GPIO_SIG146_IN_SEL_M  (BIT(7))
-#define GPIO_SIG146_IN_SEL_V  0x1
-#define GPIO_SIG146_IN_SEL_S  7
-/* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC146_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC146_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC146_IN_INV_SEL_V  0x1
-#define GPIO_FUNC146_IN_INV_SEL_S  6
-/* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC146_IN_SEL  0x0000003F
-#define GPIO_FUNC146_IN_SEL_M  ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S))
-#define GPIO_FUNC146_IN_SEL_V  0x3F
-#define GPIO_FUNC146_IN_SEL_S  0
-
-#define GPIO_FUNC147_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x037c)
-/* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG147_IN_SEL  (BIT(7))
-#define GPIO_SIG147_IN_SEL_M  (BIT(7))
-#define GPIO_SIG147_IN_SEL_V  0x1
-#define GPIO_SIG147_IN_SEL_S  7
-/* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC147_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC147_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC147_IN_INV_SEL_V  0x1
-#define GPIO_FUNC147_IN_INV_SEL_S  6
-/* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC147_IN_SEL  0x0000003F
-#define GPIO_FUNC147_IN_SEL_M  ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S))
-#define GPIO_FUNC147_IN_SEL_V  0x3F
-#define GPIO_FUNC147_IN_SEL_S  0
-
-#define GPIO_FUNC148_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0380)
-/* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG148_IN_SEL  (BIT(7))
-#define GPIO_SIG148_IN_SEL_M  (BIT(7))
-#define GPIO_SIG148_IN_SEL_V  0x1
-#define GPIO_SIG148_IN_SEL_S  7
-/* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC148_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC148_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC148_IN_INV_SEL_V  0x1
-#define GPIO_FUNC148_IN_INV_SEL_S  6
-/* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC148_IN_SEL  0x0000003F
-#define GPIO_FUNC148_IN_SEL_M  ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S))
-#define GPIO_FUNC148_IN_SEL_V  0x3F
-#define GPIO_FUNC148_IN_SEL_S  0
-
-#define GPIO_FUNC149_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0384)
-/* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG149_IN_SEL  (BIT(7))
-#define GPIO_SIG149_IN_SEL_M  (BIT(7))
-#define GPIO_SIG149_IN_SEL_V  0x1
-#define GPIO_SIG149_IN_SEL_S  7
-/* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC149_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC149_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC149_IN_INV_SEL_V  0x1
-#define GPIO_FUNC149_IN_INV_SEL_S  6
-/* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC149_IN_SEL  0x0000003F
-#define GPIO_FUNC149_IN_SEL_M  ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S))
-#define GPIO_FUNC149_IN_SEL_V  0x3F
-#define GPIO_FUNC149_IN_SEL_S  0
-
-#define GPIO_FUNC150_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0388)
-/* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG150_IN_SEL  (BIT(7))
-#define GPIO_SIG150_IN_SEL_M  (BIT(7))
-#define GPIO_SIG150_IN_SEL_V  0x1
-#define GPIO_SIG150_IN_SEL_S  7
-/* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC150_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC150_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC150_IN_INV_SEL_V  0x1
-#define GPIO_FUNC150_IN_INV_SEL_S  6
-/* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC150_IN_SEL  0x0000003F
-#define GPIO_FUNC150_IN_SEL_M  ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S))
-#define GPIO_FUNC150_IN_SEL_V  0x3F
-#define GPIO_FUNC150_IN_SEL_S  0
-
-#define GPIO_FUNC151_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x038c)
-/* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG151_IN_SEL  (BIT(7))
-#define GPIO_SIG151_IN_SEL_M  (BIT(7))
-#define GPIO_SIG151_IN_SEL_V  0x1
-#define GPIO_SIG151_IN_SEL_S  7
-/* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC151_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC151_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC151_IN_INV_SEL_V  0x1
-#define GPIO_FUNC151_IN_INV_SEL_S  6
-/* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC151_IN_SEL  0x0000003F
-#define GPIO_FUNC151_IN_SEL_M  ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S))
-#define GPIO_FUNC151_IN_SEL_V  0x3F
-#define GPIO_FUNC151_IN_SEL_S  0
-
-#define GPIO_FUNC152_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0390)
-/* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG152_IN_SEL  (BIT(7))
-#define GPIO_SIG152_IN_SEL_M  (BIT(7))
-#define GPIO_SIG152_IN_SEL_V  0x1
-#define GPIO_SIG152_IN_SEL_S  7
-/* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC152_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC152_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC152_IN_INV_SEL_V  0x1
-#define GPIO_FUNC152_IN_INV_SEL_S  6
-/* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC152_IN_SEL  0x0000003F
-#define GPIO_FUNC152_IN_SEL_M  ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S))
-#define GPIO_FUNC152_IN_SEL_V  0x3F
-#define GPIO_FUNC152_IN_SEL_S  0
-
-#define GPIO_FUNC153_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0394)
-/* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG153_IN_SEL  (BIT(7))
-#define GPIO_SIG153_IN_SEL_M  (BIT(7))
-#define GPIO_SIG153_IN_SEL_V  0x1
-#define GPIO_SIG153_IN_SEL_S  7
-/* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC153_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC153_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC153_IN_INV_SEL_V  0x1
-#define GPIO_FUNC153_IN_INV_SEL_S  6
-/* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC153_IN_SEL  0x0000003F
-#define GPIO_FUNC153_IN_SEL_M  ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S))
-#define GPIO_FUNC153_IN_SEL_V  0x3F
-#define GPIO_FUNC153_IN_SEL_S  0
-
-#define GPIO_FUNC154_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0398)
-/* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG154_IN_SEL  (BIT(7))
-#define GPIO_SIG154_IN_SEL_M  (BIT(7))
-#define GPIO_SIG154_IN_SEL_V  0x1
-#define GPIO_SIG154_IN_SEL_S  7
-/* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC154_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC154_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC154_IN_INV_SEL_V  0x1
-#define GPIO_FUNC154_IN_INV_SEL_S  6
-/* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC154_IN_SEL  0x0000003F
-#define GPIO_FUNC154_IN_SEL_M  ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S))
-#define GPIO_FUNC154_IN_SEL_V  0x3F
-#define GPIO_FUNC154_IN_SEL_S  0
-
-#define GPIO_FUNC155_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x039c)
-/* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG155_IN_SEL  (BIT(7))
-#define GPIO_SIG155_IN_SEL_M  (BIT(7))
-#define GPIO_SIG155_IN_SEL_V  0x1
-#define GPIO_SIG155_IN_SEL_S  7
-/* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC155_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC155_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC155_IN_INV_SEL_V  0x1
-#define GPIO_FUNC155_IN_INV_SEL_S  6
-/* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC155_IN_SEL  0x0000003F
-#define GPIO_FUNC155_IN_SEL_M  ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S))
-#define GPIO_FUNC155_IN_SEL_V  0x3F
-#define GPIO_FUNC155_IN_SEL_S  0
-
-#define GPIO_FUNC156_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03a0)
-/* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG156_IN_SEL  (BIT(7))
-#define GPIO_SIG156_IN_SEL_M  (BIT(7))
-#define GPIO_SIG156_IN_SEL_V  0x1
-#define GPIO_SIG156_IN_SEL_S  7
-/* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC156_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC156_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC156_IN_INV_SEL_V  0x1
-#define GPIO_FUNC156_IN_INV_SEL_S  6
-/* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC156_IN_SEL  0x0000003F
-#define GPIO_FUNC156_IN_SEL_M  ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S))
-#define GPIO_FUNC156_IN_SEL_V  0x3F
-#define GPIO_FUNC156_IN_SEL_S  0
-
-#define GPIO_FUNC157_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03a4)
-/* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG157_IN_SEL  (BIT(7))
-#define GPIO_SIG157_IN_SEL_M  (BIT(7))
-#define GPIO_SIG157_IN_SEL_V  0x1
-#define GPIO_SIG157_IN_SEL_S  7
-/* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC157_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC157_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC157_IN_INV_SEL_V  0x1
-#define GPIO_FUNC157_IN_INV_SEL_S  6
-/* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC157_IN_SEL  0x0000003F
-#define GPIO_FUNC157_IN_SEL_M  ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S))
-#define GPIO_FUNC157_IN_SEL_V  0x3F
-#define GPIO_FUNC157_IN_SEL_S  0
-
-#define GPIO_FUNC158_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03a8)
-/* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG158_IN_SEL  (BIT(7))
-#define GPIO_SIG158_IN_SEL_M  (BIT(7))
-#define GPIO_SIG158_IN_SEL_V  0x1
-#define GPIO_SIG158_IN_SEL_S  7
-/* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC158_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC158_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC158_IN_INV_SEL_V  0x1
-#define GPIO_FUNC158_IN_INV_SEL_S  6
-/* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC158_IN_SEL  0x0000003F
-#define GPIO_FUNC158_IN_SEL_M  ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S))
-#define GPIO_FUNC158_IN_SEL_V  0x3F
-#define GPIO_FUNC158_IN_SEL_S  0
-
-#define GPIO_FUNC159_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03ac)
-/* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG159_IN_SEL  (BIT(7))
-#define GPIO_SIG159_IN_SEL_M  (BIT(7))
-#define GPIO_SIG159_IN_SEL_V  0x1
-#define GPIO_SIG159_IN_SEL_S  7
-/* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC159_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC159_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC159_IN_INV_SEL_V  0x1
-#define GPIO_FUNC159_IN_INV_SEL_S  6
-/* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC159_IN_SEL  0x0000003F
-#define GPIO_FUNC159_IN_SEL_M  ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S))
-#define GPIO_FUNC159_IN_SEL_V  0x3F
-#define GPIO_FUNC159_IN_SEL_S  0
-
-#define GPIO_FUNC160_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03b0)
-/* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG160_IN_SEL  (BIT(7))
-#define GPIO_SIG160_IN_SEL_M  (BIT(7))
-#define GPIO_SIG160_IN_SEL_V  0x1
-#define GPIO_SIG160_IN_SEL_S  7
-/* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC160_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC160_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC160_IN_INV_SEL_V  0x1
-#define GPIO_FUNC160_IN_INV_SEL_S  6
-/* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC160_IN_SEL  0x0000003F
-#define GPIO_FUNC160_IN_SEL_M  ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S))
-#define GPIO_FUNC160_IN_SEL_V  0x3F
-#define GPIO_FUNC160_IN_SEL_S  0
-
-#define GPIO_FUNC161_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03b4)
-/* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG161_IN_SEL  (BIT(7))
-#define GPIO_SIG161_IN_SEL_M  (BIT(7))
-#define GPIO_SIG161_IN_SEL_V  0x1
-#define GPIO_SIG161_IN_SEL_S  7
-/* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC161_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC161_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC161_IN_INV_SEL_V  0x1
-#define GPIO_FUNC161_IN_INV_SEL_S  6
-/* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC161_IN_SEL  0x0000003F
-#define GPIO_FUNC161_IN_SEL_M  ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S))
-#define GPIO_FUNC161_IN_SEL_V  0x3F
-#define GPIO_FUNC161_IN_SEL_S  0
-
-#define GPIO_FUNC162_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03b8)
-/* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG162_IN_SEL  (BIT(7))
-#define GPIO_SIG162_IN_SEL_M  (BIT(7))
-#define GPIO_SIG162_IN_SEL_V  0x1
-#define GPIO_SIG162_IN_SEL_S  7
-/* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC162_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC162_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC162_IN_INV_SEL_V  0x1
-#define GPIO_FUNC162_IN_INV_SEL_S  6
-/* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC162_IN_SEL  0x0000003F
-#define GPIO_FUNC162_IN_SEL_M  ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S))
-#define GPIO_FUNC162_IN_SEL_V  0x3F
-#define GPIO_FUNC162_IN_SEL_S  0
-
-#define GPIO_FUNC163_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03bc)
-/* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG163_IN_SEL  (BIT(7))
-#define GPIO_SIG163_IN_SEL_M  (BIT(7))
-#define GPIO_SIG163_IN_SEL_V  0x1
-#define GPIO_SIG163_IN_SEL_S  7
-/* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC163_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC163_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC163_IN_INV_SEL_V  0x1
-#define GPIO_FUNC163_IN_INV_SEL_S  6
-/* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC163_IN_SEL  0x0000003F
-#define GPIO_FUNC163_IN_SEL_M  ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S))
-#define GPIO_FUNC163_IN_SEL_V  0x3F
-#define GPIO_FUNC163_IN_SEL_S  0
-
-#define GPIO_FUNC164_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03c0)
-/* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG164_IN_SEL  (BIT(7))
-#define GPIO_SIG164_IN_SEL_M  (BIT(7))
-#define GPIO_SIG164_IN_SEL_V  0x1
-#define GPIO_SIG164_IN_SEL_S  7
-/* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC164_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC164_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC164_IN_INV_SEL_V  0x1
-#define GPIO_FUNC164_IN_INV_SEL_S  6
-/* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC164_IN_SEL  0x0000003F
-#define GPIO_FUNC164_IN_SEL_M  ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S))
-#define GPIO_FUNC164_IN_SEL_V  0x3F
-#define GPIO_FUNC164_IN_SEL_S  0
-
-#define GPIO_FUNC165_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03c4)
-/* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG165_IN_SEL  (BIT(7))
-#define GPIO_SIG165_IN_SEL_M  (BIT(7))
-#define GPIO_SIG165_IN_SEL_V  0x1
-#define GPIO_SIG165_IN_SEL_S  7
-/* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC165_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC165_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC165_IN_INV_SEL_V  0x1
-#define GPIO_FUNC165_IN_INV_SEL_S  6
-/* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC165_IN_SEL  0x0000003F
-#define GPIO_FUNC165_IN_SEL_M  ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S))
-#define GPIO_FUNC165_IN_SEL_V  0x3F
-#define GPIO_FUNC165_IN_SEL_S  0
-
-#define GPIO_FUNC166_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03c8)
-/* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG166_IN_SEL  (BIT(7))
-#define GPIO_SIG166_IN_SEL_M  (BIT(7))
-#define GPIO_SIG166_IN_SEL_V  0x1
-#define GPIO_SIG166_IN_SEL_S  7
-/* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC166_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC166_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC166_IN_INV_SEL_V  0x1
-#define GPIO_FUNC166_IN_INV_SEL_S  6
-/* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC166_IN_SEL  0x0000003F
-#define GPIO_FUNC166_IN_SEL_M  ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S))
-#define GPIO_FUNC166_IN_SEL_V  0x3F
-#define GPIO_FUNC166_IN_SEL_S  0
-
-#define GPIO_FUNC167_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03cc)
-/* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG167_IN_SEL  (BIT(7))
-#define GPIO_SIG167_IN_SEL_M  (BIT(7))
-#define GPIO_SIG167_IN_SEL_V  0x1
-#define GPIO_SIG167_IN_SEL_S  7
-/* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC167_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC167_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC167_IN_INV_SEL_V  0x1
-#define GPIO_FUNC167_IN_INV_SEL_S  6
-/* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC167_IN_SEL  0x0000003F
-#define GPIO_FUNC167_IN_SEL_M  ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S))
-#define GPIO_FUNC167_IN_SEL_V  0x3F
-#define GPIO_FUNC167_IN_SEL_S  0
-
-#define GPIO_FUNC168_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03d0)
-/* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG168_IN_SEL  (BIT(7))
-#define GPIO_SIG168_IN_SEL_M  (BIT(7))
-#define GPIO_SIG168_IN_SEL_V  0x1
-#define GPIO_SIG168_IN_SEL_S  7
-/* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC168_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC168_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC168_IN_INV_SEL_V  0x1
-#define GPIO_FUNC168_IN_INV_SEL_S  6
-/* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC168_IN_SEL  0x0000003F
-#define GPIO_FUNC168_IN_SEL_M  ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S))
-#define GPIO_FUNC168_IN_SEL_V  0x3F
-#define GPIO_FUNC168_IN_SEL_S  0
-
-#define GPIO_FUNC169_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03d4)
-/* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG169_IN_SEL  (BIT(7))
-#define GPIO_SIG169_IN_SEL_M  (BIT(7))
-#define GPIO_SIG169_IN_SEL_V  0x1
-#define GPIO_SIG169_IN_SEL_S  7
-/* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC169_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC169_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC169_IN_INV_SEL_V  0x1
-#define GPIO_FUNC169_IN_INV_SEL_S  6
-/* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC169_IN_SEL  0x0000003F
-#define GPIO_FUNC169_IN_SEL_M  ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S))
-#define GPIO_FUNC169_IN_SEL_V  0x3F
-#define GPIO_FUNC169_IN_SEL_S  0
-
-#define GPIO_FUNC170_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03d8)
-/* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG170_IN_SEL  (BIT(7))
-#define GPIO_SIG170_IN_SEL_M  (BIT(7))
-#define GPIO_SIG170_IN_SEL_V  0x1
-#define GPIO_SIG170_IN_SEL_S  7
-/* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC170_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC170_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC170_IN_INV_SEL_V  0x1
-#define GPIO_FUNC170_IN_INV_SEL_S  6
-/* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC170_IN_SEL  0x0000003F
-#define GPIO_FUNC170_IN_SEL_M  ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S))
-#define GPIO_FUNC170_IN_SEL_V  0x3F
-#define GPIO_FUNC170_IN_SEL_S  0
-
-#define GPIO_FUNC171_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03dc)
-/* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG171_IN_SEL  (BIT(7))
-#define GPIO_SIG171_IN_SEL_M  (BIT(7))
-#define GPIO_SIG171_IN_SEL_V  0x1
-#define GPIO_SIG171_IN_SEL_S  7
-/* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC171_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC171_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC171_IN_INV_SEL_V  0x1
-#define GPIO_FUNC171_IN_INV_SEL_S  6
-/* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC171_IN_SEL  0x0000003F
-#define GPIO_FUNC171_IN_SEL_M  ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S))
-#define GPIO_FUNC171_IN_SEL_V  0x3F
-#define GPIO_FUNC171_IN_SEL_S  0
-
-#define GPIO_FUNC172_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03e0)
-/* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG172_IN_SEL  (BIT(7))
-#define GPIO_SIG172_IN_SEL_M  (BIT(7))
-#define GPIO_SIG172_IN_SEL_V  0x1
-#define GPIO_SIG172_IN_SEL_S  7
-/* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC172_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC172_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC172_IN_INV_SEL_V  0x1
-#define GPIO_FUNC172_IN_INV_SEL_S  6
-/* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC172_IN_SEL  0x0000003F
-#define GPIO_FUNC172_IN_SEL_M  ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S))
-#define GPIO_FUNC172_IN_SEL_V  0x3F
-#define GPIO_FUNC172_IN_SEL_S  0
-
-#define GPIO_FUNC173_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03e4)
-/* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG173_IN_SEL  (BIT(7))
-#define GPIO_SIG173_IN_SEL_M  (BIT(7))
-#define GPIO_SIG173_IN_SEL_V  0x1
-#define GPIO_SIG173_IN_SEL_S  7
-/* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC173_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC173_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC173_IN_INV_SEL_V  0x1
-#define GPIO_FUNC173_IN_INV_SEL_S  6
-/* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC173_IN_SEL  0x0000003F
-#define GPIO_FUNC173_IN_SEL_M  ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S))
-#define GPIO_FUNC173_IN_SEL_V  0x3F
-#define GPIO_FUNC173_IN_SEL_S  0
-
-#define GPIO_FUNC174_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03e8)
-/* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG174_IN_SEL  (BIT(7))
-#define GPIO_SIG174_IN_SEL_M  (BIT(7))
-#define GPIO_SIG174_IN_SEL_V  0x1
-#define GPIO_SIG174_IN_SEL_S  7
-/* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC174_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC174_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC174_IN_INV_SEL_V  0x1
-#define GPIO_FUNC174_IN_INV_SEL_S  6
-/* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC174_IN_SEL  0x0000003F
-#define GPIO_FUNC174_IN_SEL_M  ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S))
-#define GPIO_FUNC174_IN_SEL_V  0x3F
-#define GPIO_FUNC174_IN_SEL_S  0
-
-#define GPIO_FUNC175_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03ec)
-/* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG175_IN_SEL  (BIT(7))
-#define GPIO_SIG175_IN_SEL_M  (BIT(7))
-#define GPIO_SIG175_IN_SEL_V  0x1
-#define GPIO_SIG175_IN_SEL_S  7
-/* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC175_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC175_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC175_IN_INV_SEL_V  0x1
-#define GPIO_FUNC175_IN_INV_SEL_S  6
-/* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC175_IN_SEL  0x0000003F
-#define GPIO_FUNC175_IN_SEL_M  ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S))
-#define GPIO_FUNC175_IN_SEL_V  0x3F
-#define GPIO_FUNC175_IN_SEL_S  0
-
-#define GPIO_FUNC176_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03f0)
-/* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG176_IN_SEL  (BIT(7))
-#define GPIO_SIG176_IN_SEL_M  (BIT(7))
-#define GPIO_SIG176_IN_SEL_V  0x1
-#define GPIO_SIG176_IN_SEL_S  7
-/* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC176_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC176_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC176_IN_INV_SEL_V  0x1
-#define GPIO_FUNC176_IN_INV_SEL_S  6
-/* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC176_IN_SEL  0x0000003F
-#define GPIO_FUNC176_IN_SEL_M  ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S))
-#define GPIO_FUNC176_IN_SEL_V  0x3F
-#define GPIO_FUNC176_IN_SEL_S  0
-
-#define GPIO_FUNC177_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03f4)
-/* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG177_IN_SEL  (BIT(7))
-#define GPIO_SIG177_IN_SEL_M  (BIT(7))
-#define GPIO_SIG177_IN_SEL_V  0x1
-#define GPIO_SIG177_IN_SEL_S  7
-/* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC177_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC177_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC177_IN_INV_SEL_V  0x1
-#define GPIO_FUNC177_IN_INV_SEL_S  6
-/* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC177_IN_SEL  0x0000003F
-#define GPIO_FUNC177_IN_SEL_M  ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S))
-#define GPIO_FUNC177_IN_SEL_V  0x3F
-#define GPIO_FUNC177_IN_SEL_S  0
-
-#define GPIO_FUNC178_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03f8)
-/* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG178_IN_SEL  (BIT(7))
-#define GPIO_SIG178_IN_SEL_M  (BIT(7))
-#define GPIO_SIG178_IN_SEL_V  0x1
-#define GPIO_SIG178_IN_SEL_S  7
-/* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC178_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC178_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC178_IN_INV_SEL_V  0x1
-#define GPIO_FUNC178_IN_INV_SEL_S  6
-/* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC178_IN_SEL  0x0000003F
-#define GPIO_FUNC178_IN_SEL_M  ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S))
-#define GPIO_FUNC178_IN_SEL_V  0x3F
-#define GPIO_FUNC178_IN_SEL_S  0
-
-#define GPIO_FUNC179_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x03fc)
-/* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG179_IN_SEL  (BIT(7))
-#define GPIO_SIG179_IN_SEL_M  (BIT(7))
-#define GPIO_SIG179_IN_SEL_V  0x1
-#define GPIO_SIG179_IN_SEL_S  7
-/* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC179_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC179_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC179_IN_INV_SEL_V  0x1
-#define GPIO_FUNC179_IN_INV_SEL_S  6
-/* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC179_IN_SEL  0x0000003F
-#define GPIO_FUNC179_IN_SEL_M  ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S))
-#define GPIO_FUNC179_IN_SEL_V  0x3F
-#define GPIO_FUNC179_IN_SEL_S  0
-
-#define GPIO_FUNC180_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0400)
-/* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG180_IN_SEL  (BIT(7))
-#define GPIO_SIG180_IN_SEL_M  (BIT(7))
-#define GPIO_SIG180_IN_SEL_V  0x1
-#define GPIO_SIG180_IN_SEL_S  7
-/* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC180_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC180_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC180_IN_INV_SEL_V  0x1
-#define GPIO_FUNC180_IN_INV_SEL_S  6
-/* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC180_IN_SEL  0x0000003F
-#define GPIO_FUNC180_IN_SEL_M  ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S))
-#define GPIO_FUNC180_IN_SEL_V  0x3F
-#define GPIO_FUNC180_IN_SEL_S  0
-
-#define GPIO_FUNC181_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0404)
-/* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG181_IN_SEL  (BIT(7))
-#define GPIO_SIG181_IN_SEL_M  (BIT(7))
-#define GPIO_SIG181_IN_SEL_V  0x1
-#define GPIO_SIG181_IN_SEL_S  7
-/* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC181_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC181_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC181_IN_INV_SEL_V  0x1
-#define GPIO_FUNC181_IN_INV_SEL_S  6
-/* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC181_IN_SEL  0x0000003F
-#define GPIO_FUNC181_IN_SEL_M  ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S))
-#define GPIO_FUNC181_IN_SEL_V  0x3F
-#define GPIO_FUNC181_IN_SEL_S  0
-
-#define GPIO_FUNC182_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0408)
-/* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG182_IN_SEL  (BIT(7))
-#define GPIO_SIG182_IN_SEL_M  (BIT(7))
-#define GPIO_SIG182_IN_SEL_V  0x1
-#define GPIO_SIG182_IN_SEL_S  7
-/* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC182_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC182_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC182_IN_INV_SEL_V  0x1
-#define GPIO_FUNC182_IN_INV_SEL_S  6
-/* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC182_IN_SEL  0x0000003F
-#define GPIO_FUNC182_IN_SEL_M  ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S))
-#define GPIO_FUNC182_IN_SEL_V  0x3F
-#define GPIO_FUNC182_IN_SEL_S  0
-
-#define GPIO_FUNC183_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x040c)
-/* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG183_IN_SEL  (BIT(7))
-#define GPIO_SIG183_IN_SEL_M  (BIT(7))
-#define GPIO_SIG183_IN_SEL_V  0x1
-#define GPIO_SIG183_IN_SEL_S  7
-/* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC183_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC183_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC183_IN_INV_SEL_V  0x1
-#define GPIO_FUNC183_IN_INV_SEL_S  6
-/* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC183_IN_SEL  0x0000003F
-#define GPIO_FUNC183_IN_SEL_M  ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S))
-#define GPIO_FUNC183_IN_SEL_V  0x3F
-#define GPIO_FUNC183_IN_SEL_S  0
-
-#define GPIO_FUNC184_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0410)
-/* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG184_IN_SEL  (BIT(7))
-#define GPIO_SIG184_IN_SEL_M  (BIT(7))
-#define GPIO_SIG184_IN_SEL_V  0x1
-#define GPIO_SIG184_IN_SEL_S  7
-/* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC184_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC184_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC184_IN_INV_SEL_V  0x1
-#define GPIO_FUNC184_IN_INV_SEL_S  6
-/* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC184_IN_SEL  0x0000003F
-#define GPIO_FUNC184_IN_SEL_M  ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S))
-#define GPIO_FUNC184_IN_SEL_V  0x3F
-#define GPIO_FUNC184_IN_SEL_S  0
-
-#define GPIO_FUNC185_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0414)
-/* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG185_IN_SEL  (BIT(7))
-#define GPIO_SIG185_IN_SEL_M  (BIT(7))
-#define GPIO_SIG185_IN_SEL_V  0x1
-#define GPIO_SIG185_IN_SEL_S  7
-/* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC185_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC185_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC185_IN_INV_SEL_V  0x1
-#define GPIO_FUNC185_IN_INV_SEL_S  6
-/* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC185_IN_SEL  0x0000003F
-#define GPIO_FUNC185_IN_SEL_M  ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S))
-#define GPIO_FUNC185_IN_SEL_V  0x3F
-#define GPIO_FUNC185_IN_SEL_S  0
-
-#define GPIO_FUNC186_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0418)
-/* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG186_IN_SEL  (BIT(7))
-#define GPIO_SIG186_IN_SEL_M  (BIT(7))
-#define GPIO_SIG186_IN_SEL_V  0x1
-#define GPIO_SIG186_IN_SEL_S  7
-/* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC186_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC186_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC186_IN_INV_SEL_V  0x1
-#define GPIO_FUNC186_IN_INV_SEL_S  6
-/* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC186_IN_SEL  0x0000003F
-#define GPIO_FUNC186_IN_SEL_M  ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S))
-#define GPIO_FUNC186_IN_SEL_V  0x3F
-#define GPIO_FUNC186_IN_SEL_S  0
-
-#define GPIO_FUNC187_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x041c)
-/* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG187_IN_SEL  (BIT(7))
-#define GPIO_SIG187_IN_SEL_M  (BIT(7))
-#define GPIO_SIG187_IN_SEL_V  0x1
-#define GPIO_SIG187_IN_SEL_S  7
-/* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC187_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC187_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC187_IN_INV_SEL_V  0x1
-#define GPIO_FUNC187_IN_INV_SEL_S  6
-/* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC187_IN_SEL  0x0000003F
-#define GPIO_FUNC187_IN_SEL_M  ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S))
-#define GPIO_FUNC187_IN_SEL_V  0x3F
-#define GPIO_FUNC187_IN_SEL_S  0
-
-#define GPIO_FUNC188_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0420)
-/* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG188_IN_SEL  (BIT(7))
-#define GPIO_SIG188_IN_SEL_M  (BIT(7))
-#define GPIO_SIG188_IN_SEL_V  0x1
-#define GPIO_SIG188_IN_SEL_S  7
-/* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC188_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC188_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC188_IN_INV_SEL_V  0x1
-#define GPIO_FUNC188_IN_INV_SEL_S  6
-/* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC188_IN_SEL  0x0000003F
-#define GPIO_FUNC188_IN_SEL_M  ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S))
-#define GPIO_FUNC188_IN_SEL_V  0x3F
-#define GPIO_FUNC188_IN_SEL_S  0
-
-#define GPIO_FUNC189_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0424)
-/* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG189_IN_SEL  (BIT(7))
-#define GPIO_SIG189_IN_SEL_M  (BIT(7))
-#define GPIO_SIG189_IN_SEL_V  0x1
-#define GPIO_SIG189_IN_SEL_S  7
-/* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC189_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC189_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC189_IN_INV_SEL_V  0x1
-#define GPIO_FUNC189_IN_INV_SEL_S  6
-/* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC189_IN_SEL  0x0000003F
-#define GPIO_FUNC189_IN_SEL_M  ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S))
-#define GPIO_FUNC189_IN_SEL_V  0x3F
-#define GPIO_FUNC189_IN_SEL_S  0
-
-#define GPIO_FUNC190_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0428)
-/* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG190_IN_SEL  (BIT(7))
-#define GPIO_SIG190_IN_SEL_M  (BIT(7))
-#define GPIO_SIG190_IN_SEL_V  0x1
-#define GPIO_SIG190_IN_SEL_S  7
-/* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC190_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC190_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC190_IN_INV_SEL_V  0x1
-#define GPIO_FUNC190_IN_INV_SEL_S  6
-/* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC190_IN_SEL  0x0000003F
-#define GPIO_FUNC190_IN_SEL_M  ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S))
-#define GPIO_FUNC190_IN_SEL_V  0x3F
-#define GPIO_FUNC190_IN_SEL_S  0
-
-#define GPIO_FUNC191_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x042c)
-/* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG191_IN_SEL  (BIT(7))
-#define GPIO_SIG191_IN_SEL_M  (BIT(7))
-#define GPIO_SIG191_IN_SEL_V  0x1
-#define GPIO_SIG191_IN_SEL_S  7
-/* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC191_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC191_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC191_IN_INV_SEL_V  0x1
-#define GPIO_FUNC191_IN_INV_SEL_S  6
-/* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC191_IN_SEL  0x0000003F
-#define GPIO_FUNC191_IN_SEL_M  ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S))
-#define GPIO_FUNC191_IN_SEL_V  0x3F
-#define GPIO_FUNC191_IN_SEL_S  0
-
-#define GPIO_FUNC192_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0430)
-/* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG192_IN_SEL  (BIT(7))
-#define GPIO_SIG192_IN_SEL_M  (BIT(7))
-#define GPIO_SIG192_IN_SEL_V  0x1
-#define GPIO_SIG192_IN_SEL_S  7
-/* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC192_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC192_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC192_IN_INV_SEL_V  0x1
-#define GPIO_FUNC192_IN_INV_SEL_S  6
-/* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC192_IN_SEL  0x0000003F
-#define GPIO_FUNC192_IN_SEL_M  ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S))
-#define GPIO_FUNC192_IN_SEL_V  0x3F
-#define GPIO_FUNC192_IN_SEL_S  0
-
-#define GPIO_FUNC193_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0434)
-/* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG193_IN_SEL  (BIT(7))
-#define GPIO_SIG193_IN_SEL_M  (BIT(7))
-#define GPIO_SIG193_IN_SEL_V  0x1
-#define GPIO_SIG193_IN_SEL_S  7
-/* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC193_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC193_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC193_IN_INV_SEL_V  0x1
-#define GPIO_FUNC193_IN_INV_SEL_S  6
-/* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC193_IN_SEL  0x0000003F
-#define GPIO_FUNC193_IN_SEL_M  ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S))
-#define GPIO_FUNC193_IN_SEL_V  0x3F
-#define GPIO_FUNC193_IN_SEL_S  0
-
-#define GPIO_FUNC194_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0438)
-/* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG194_IN_SEL  (BIT(7))
-#define GPIO_SIG194_IN_SEL_M  (BIT(7))
-#define GPIO_SIG194_IN_SEL_V  0x1
-#define GPIO_SIG194_IN_SEL_S  7
-/* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC194_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC194_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC194_IN_INV_SEL_V  0x1
-#define GPIO_FUNC194_IN_INV_SEL_S  6
-/* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC194_IN_SEL  0x0000003F
-#define GPIO_FUNC194_IN_SEL_M  ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S))
-#define GPIO_FUNC194_IN_SEL_V  0x3F
-#define GPIO_FUNC194_IN_SEL_S  0
-
-#define GPIO_FUNC195_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x043c)
-/* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG195_IN_SEL  (BIT(7))
-#define GPIO_SIG195_IN_SEL_M  (BIT(7))
-#define GPIO_SIG195_IN_SEL_V  0x1
-#define GPIO_SIG195_IN_SEL_S  7
-/* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC195_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC195_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC195_IN_INV_SEL_V  0x1
-#define GPIO_FUNC195_IN_INV_SEL_S  6
-/* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC195_IN_SEL  0x0000003F
-#define GPIO_FUNC195_IN_SEL_M  ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S))
-#define GPIO_FUNC195_IN_SEL_V  0x3F
-#define GPIO_FUNC195_IN_SEL_S  0
-
-#define GPIO_FUNC196_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0440)
-/* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG196_IN_SEL  (BIT(7))
-#define GPIO_SIG196_IN_SEL_M  (BIT(7))
-#define GPIO_SIG196_IN_SEL_V  0x1
-#define GPIO_SIG196_IN_SEL_S  7
-/* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC196_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC196_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC196_IN_INV_SEL_V  0x1
-#define GPIO_FUNC196_IN_INV_SEL_S  6
-/* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC196_IN_SEL  0x0000003F
-#define GPIO_FUNC196_IN_SEL_M  ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S))
-#define GPIO_FUNC196_IN_SEL_V  0x3F
-#define GPIO_FUNC196_IN_SEL_S  0
-
-#define GPIO_FUNC197_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0444)
-/* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG197_IN_SEL  (BIT(7))
-#define GPIO_SIG197_IN_SEL_M  (BIT(7))
-#define GPIO_SIG197_IN_SEL_V  0x1
-#define GPIO_SIG197_IN_SEL_S  7
-/* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC197_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC197_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC197_IN_INV_SEL_V  0x1
-#define GPIO_FUNC197_IN_INV_SEL_S  6
-/* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC197_IN_SEL  0x0000003F
-#define GPIO_FUNC197_IN_SEL_M  ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S))
-#define GPIO_FUNC197_IN_SEL_V  0x3F
-#define GPIO_FUNC197_IN_SEL_S  0
-
-#define GPIO_FUNC198_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0448)
-/* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG198_IN_SEL  (BIT(7))
-#define GPIO_SIG198_IN_SEL_M  (BIT(7))
-#define GPIO_SIG198_IN_SEL_V  0x1
-#define GPIO_SIG198_IN_SEL_S  7
-/* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC198_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC198_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC198_IN_INV_SEL_V  0x1
-#define GPIO_FUNC198_IN_INV_SEL_S  6
-/* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC198_IN_SEL  0x0000003F
-#define GPIO_FUNC198_IN_SEL_M  ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S))
-#define GPIO_FUNC198_IN_SEL_V  0x3F
-#define GPIO_FUNC198_IN_SEL_S  0
-
-#define GPIO_FUNC199_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x044c)
-/* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG199_IN_SEL  (BIT(7))
-#define GPIO_SIG199_IN_SEL_M  (BIT(7))
-#define GPIO_SIG199_IN_SEL_V  0x1
-#define GPIO_SIG199_IN_SEL_S  7
-/* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC199_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC199_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC199_IN_INV_SEL_V  0x1
-#define GPIO_FUNC199_IN_INV_SEL_S  6
-/* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC199_IN_SEL  0x0000003F
-#define GPIO_FUNC199_IN_SEL_M  ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S))
-#define GPIO_FUNC199_IN_SEL_V  0x3F
-#define GPIO_FUNC199_IN_SEL_S  0
-
-#define GPIO_FUNC200_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0450)
-/* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG200_IN_SEL  (BIT(7))
-#define GPIO_SIG200_IN_SEL_M  (BIT(7))
-#define GPIO_SIG200_IN_SEL_V  0x1
-#define GPIO_SIG200_IN_SEL_S  7
-/* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC200_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC200_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC200_IN_INV_SEL_V  0x1
-#define GPIO_FUNC200_IN_INV_SEL_S  6
-/* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC200_IN_SEL  0x0000003F
-#define GPIO_FUNC200_IN_SEL_M  ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S))
-#define GPIO_FUNC200_IN_SEL_V  0x3F
-#define GPIO_FUNC200_IN_SEL_S  0
-
-#define GPIO_FUNC201_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0454)
-/* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG201_IN_SEL  (BIT(7))
-#define GPIO_SIG201_IN_SEL_M  (BIT(7))
-#define GPIO_SIG201_IN_SEL_V  0x1
-#define GPIO_SIG201_IN_SEL_S  7
-/* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC201_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC201_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC201_IN_INV_SEL_V  0x1
-#define GPIO_FUNC201_IN_INV_SEL_S  6
-/* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC201_IN_SEL  0x0000003F
-#define GPIO_FUNC201_IN_SEL_M  ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S))
-#define GPIO_FUNC201_IN_SEL_V  0x3F
-#define GPIO_FUNC201_IN_SEL_S  0
-
-#define GPIO_FUNC202_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0458)
-/* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG202_IN_SEL  (BIT(7))
-#define GPIO_SIG202_IN_SEL_M  (BIT(7))
-#define GPIO_SIG202_IN_SEL_V  0x1
-#define GPIO_SIG202_IN_SEL_S  7
-/* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC202_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC202_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC202_IN_INV_SEL_V  0x1
-#define GPIO_FUNC202_IN_INV_SEL_S  6
-/* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC202_IN_SEL  0x0000003F
-#define GPIO_FUNC202_IN_SEL_M  ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S))
-#define GPIO_FUNC202_IN_SEL_V  0x3F
-#define GPIO_FUNC202_IN_SEL_S  0
-
-#define GPIO_FUNC203_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x045c)
-/* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG203_IN_SEL  (BIT(7))
-#define GPIO_SIG203_IN_SEL_M  (BIT(7))
-#define GPIO_SIG203_IN_SEL_V  0x1
-#define GPIO_SIG203_IN_SEL_S  7
-/* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC203_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC203_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC203_IN_INV_SEL_V  0x1
-#define GPIO_FUNC203_IN_INV_SEL_S  6
-/* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC203_IN_SEL  0x0000003F
-#define GPIO_FUNC203_IN_SEL_M  ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S))
-#define GPIO_FUNC203_IN_SEL_V  0x3F
-#define GPIO_FUNC203_IN_SEL_S  0
-
-#define GPIO_FUNC204_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0460)
-/* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG204_IN_SEL  (BIT(7))
-#define GPIO_SIG204_IN_SEL_M  (BIT(7))
-#define GPIO_SIG204_IN_SEL_V  0x1
-#define GPIO_SIG204_IN_SEL_S  7
-/* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC204_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC204_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC204_IN_INV_SEL_V  0x1
-#define GPIO_FUNC204_IN_INV_SEL_S  6
-/* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC204_IN_SEL  0x0000003F
-#define GPIO_FUNC204_IN_SEL_M  ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S))
-#define GPIO_FUNC204_IN_SEL_V  0x3F
-#define GPIO_FUNC204_IN_SEL_S  0
-
-#define GPIO_FUNC205_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0464)
-/* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG205_IN_SEL  (BIT(7))
-#define GPIO_SIG205_IN_SEL_M  (BIT(7))
-#define GPIO_SIG205_IN_SEL_V  0x1
-#define GPIO_SIG205_IN_SEL_S  7
-/* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC205_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC205_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC205_IN_INV_SEL_V  0x1
-#define GPIO_FUNC205_IN_INV_SEL_S  6
-/* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC205_IN_SEL  0x0000003F
-#define GPIO_FUNC205_IN_SEL_M  ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S))
-#define GPIO_FUNC205_IN_SEL_V  0x3F
-#define GPIO_FUNC205_IN_SEL_S  0
-
-#define GPIO_FUNC206_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0468)
-/* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG206_IN_SEL  (BIT(7))
-#define GPIO_SIG206_IN_SEL_M  (BIT(7))
-#define GPIO_SIG206_IN_SEL_V  0x1
-#define GPIO_SIG206_IN_SEL_S  7
-/* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC206_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC206_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC206_IN_INV_SEL_V  0x1
-#define GPIO_FUNC206_IN_INV_SEL_S  6
-/* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC206_IN_SEL  0x0000003F
-#define GPIO_FUNC206_IN_SEL_M  ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S))
-#define GPIO_FUNC206_IN_SEL_V  0x3F
-#define GPIO_FUNC206_IN_SEL_S  0
-
-#define GPIO_FUNC207_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x046c)
-/* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG207_IN_SEL  (BIT(7))
-#define GPIO_SIG207_IN_SEL_M  (BIT(7))
-#define GPIO_SIG207_IN_SEL_V  0x1
-#define GPIO_SIG207_IN_SEL_S  7
-/* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC207_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC207_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC207_IN_INV_SEL_V  0x1
-#define GPIO_FUNC207_IN_INV_SEL_S  6
-/* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC207_IN_SEL  0x0000003F
-#define GPIO_FUNC207_IN_SEL_M  ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S))
-#define GPIO_FUNC207_IN_SEL_V  0x3F
-#define GPIO_FUNC207_IN_SEL_S  0
-
-#define GPIO_FUNC208_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0470)
-/* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG208_IN_SEL  (BIT(7))
-#define GPIO_SIG208_IN_SEL_M  (BIT(7))
-#define GPIO_SIG208_IN_SEL_V  0x1
-#define GPIO_SIG208_IN_SEL_S  7
-/* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC208_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC208_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC208_IN_INV_SEL_V  0x1
-#define GPIO_FUNC208_IN_INV_SEL_S  6
-/* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC208_IN_SEL  0x0000003F
-#define GPIO_FUNC208_IN_SEL_M  ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S))
-#define GPIO_FUNC208_IN_SEL_V  0x3F
-#define GPIO_FUNC208_IN_SEL_S  0
-
-#define GPIO_FUNC209_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0474)
-/* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG209_IN_SEL  (BIT(7))
-#define GPIO_SIG209_IN_SEL_M  (BIT(7))
-#define GPIO_SIG209_IN_SEL_V  0x1
-#define GPIO_SIG209_IN_SEL_S  7
-/* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC209_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC209_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC209_IN_INV_SEL_V  0x1
-#define GPIO_FUNC209_IN_INV_SEL_S  6
-/* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC209_IN_SEL  0x0000003F
-#define GPIO_FUNC209_IN_SEL_M  ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S))
-#define GPIO_FUNC209_IN_SEL_V  0x3F
-#define GPIO_FUNC209_IN_SEL_S  0
-
-#define GPIO_FUNC210_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0478)
-/* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG210_IN_SEL  (BIT(7))
-#define GPIO_SIG210_IN_SEL_M  (BIT(7))
-#define GPIO_SIG210_IN_SEL_V  0x1
-#define GPIO_SIG210_IN_SEL_S  7
-/* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC210_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC210_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC210_IN_INV_SEL_V  0x1
-#define GPIO_FUNC210_IN_INV_SEL_S  6
-/* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC210_IN_SEL  0x0000003F
-#define GPIO_FUNC210_IN_SEL_M  ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S))
-#define GPIO_FUNC210_IN_SEL_V  0x3F
-#define GPIO_FUNC210_IN_SEL_S  0
-
-#define GPIO_FUNC211_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x047c)
-/* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG211_IN_SEL  (BIT(7))
-#define GPIO_SIG211_IN_SEL_M  (BIT(7))
-#define GPIO_SIG211_IN_SEL_V  0x1
-#define GPIO_SIG211_IN_SEL_S  7
-/* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC211_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC211_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC211_IN_INV_SEL_V  0x1
-#define GPIO_FUNC211_IN_INV_SEL_S  6
-/* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC211_IN_SEL  0x0000003F
-#define GPIO_FUNC211_IN_SEL_M  ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S))
-#define GPIO_FUNC211_IN_SEL_V  0x3F
-#define GPIO_FUNC211_IN_SEL_S  0
-
-#define GPIO_FUNC212_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0480)
-/* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG212_IN_SEL  (BIT(7))
-#define GPIO_SIG212_IN_SEL_M  (BIT(7))
-#define GPIO_SIG212_IN_SEL_V  0x1
-#define GPIO_SIG212_IN_SEL_S  7
-/* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC212_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC212_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC212_IN_INV_SEL_V  0x1
-#define GPIO_FUNC212_IN_INV_SEL_S  6
-/* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC212_IN_SEL  0x0000003F
-#define GPIO_FUNC212_IN_SEL_M  ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S))
-#define GPIO_FUNC212_IN_SEL_V  0x3F
-#define GPIO_FUNC212_IN_SEL_S  0
-
-#define GPIO_FUNC213_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0484)
-/* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG213_IN_SEL  (BIT(7))
-#define GPIO_SIG213_IN_SEL_M  (BIT(7))
-#define GPIO_SIG213_IN_SEL_V  0x1
-#define GPIO_SIG213_IN_SEL_S  7
-/* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC213_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC213_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC213_IN_INV_SEL_V  0x1
-#define GPIO_FUNC213_IN_INV_SEL_S  6
-/* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC213_IN_SEL  0x0000003F
-#define GPIO_FUNC213_IN_SEL_M  ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S))
-#define GPIO_FUNC213_IN_SEL_V  0x3F
-#define GPIO_FUNC213_IN_SEL_S  0
-
-#define GPIO_FUNC214_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0488)
-/* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG214_IN_SEL  (BIT(7))
-#define GPIO_SIG214_IN_SEL_M  (BIT(7))
-#define GPIO_SIG214_IN_SEL_V  0x1
-#define GPIO_SIG214_IN_SEL_S  7
-/* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC214_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC214_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC214_IN_INV_SEL_V  0x1
-#define GPIO_FUNC214_IN_INV_SEL_S  6
-/* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC214_IN_SEL  0x0000003F
-#define GPIO_FUNC214_IN_SEL_M  ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S))
-#define GPIO_FUNC214_IN_SEL_V  0x3F
-#define GPIO_FUNC214_IN_SEL_S  0
-
-#define GPIO_FUNC215_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x048c)
-/* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG215_IN_SEL  (BIT(7))
-#define GPIO_SIG215_IN_SEL_M  (BIT(7))
-#define GPIO_SIG215_IN_SEL_V  0x1
-#define GPIO_SIG215_IN_SEL_S  7
-/* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC215_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC215_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC215_IN_INV_SEL_V  0x1
-#define GPIO_FUNC215_IN_INV_SEL_S  6
-/* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC215_IN_SEL  0x0000003F
-#define GPIO_FUNC215_IN_SEL_M  ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S))
-#define GPIO_FUNC215_IN_SEL_V  0x3F
-#define GPIO_FUNC215_IN_SEL_S  0
-
-#define GPIO_FUNC216_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0490)
-/* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG216_IN_SEL  (BIT(7))
-#define GPIO_SIG216_IN_SEL_M  (BIT(7))
-#define GPIO_SIG216_IN_SEL_V  0x1
-#define GPIO_SIG216_IN_SEL_S  7
-/* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC216_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC216_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC216_IN_INV_SEL_V  0x1
-#define GPIO_FUNC216_IN_INV_SEL_S  6
-/* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC216_IN_SEL  0x0000003F
-#define GPIO_FUNC216_IN_SEL_M  ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S))
-#define GPIO_FUNC216_IN_SEL_V  0x3F
-#define GPIO_FUNC216_IN_SEL_S  0
-
-#define GPIO_FUNC217_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0494)
-/* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG217_IN_SEL  (BIT(7))
-#define GPIO_SIG217_IN_SEL_M  (BIT(7))
-#define GPIO_SIG217_IN_SEL_V  0x1
-#define GPIO_SIG217_IN_SEL_S  7
-/* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC217_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC217_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC217_IN_INV_SEL_V  0x1
-#define GPIO_FUNC217_IN_INV_SEL_S  6
-/* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC217_IN_SEL  0x0000003F
-#define GPIO_FUNC217_IN_SEL_M  ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S))
-#define GPIO_FUNC217_IN_SEL_V  0x3F
-#define GPIO_FUNC217_IN_SEL_S  0
-
-#define GPIO_FUNC218_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0498)
-/* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG218_IN_SEL  (BIT(7))
-#define GPIO_SIG218_IN_SEL_M  (BIT(7))
-#define GPIO_SIG218_IN_SEL_V  0x1
-#define GPIO_SIG218_IN_SEL_S  7
-/* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC218_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC218_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC218_IN_INV_SEL_V  0x1
-#define GPIO_FUNC218_IN_INV_SEL_S  6
-/* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC218_IN_SEL  0x0000003F
-#define GPIO_FUNC218_IN_SEL_M  ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S))
-#define GPIO_FUNC218_IN_SEL_V  0x3F
-#define GPIO_FUNC218_IN_SEL_S  0
-
-#define GPIO_FUNC219_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x049c)
-/* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG219_IN_SEL  (BIT(7))
-#define GPIO_SIG219_IN_SEL_M  (BIT(7))
-#define GPIO_SIG219_IN_SEL_V  0x1
-#define GPIO_SIG219_IN_SEL_S  7
-/* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC219_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC219_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC219_IN_INV_SEL_V  0x1
-#define GPIO_FUNC219_IN_INV_SEL_S  6
-/* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC219_IN_SEL  0x0000003F
-#define GPIO_FUNC219_IN_SEL_M  ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S))
-#define GPIO_FUNC219_IN_SEL_V  0x3F
-#define GPIO_FUNC219_IN_SEL_S  0
-
-#define GPIO_FUNC220_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04a0)
-/* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG220_IN_SEL  (BIT(7))
-#define GPIO_SIG220_IN_SEL_M  (BIT(7))
-#define GPIO_SIG220_IN_SEL_V  0x1
-#define GPIO_SIG220_IN_SEL_S  7
-/* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC220_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC220_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC220_IN_INV_SEL_V  0x1
-#define GPIO_FUNC220_IN_INV_SEL_S  6
-/* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC220_IN_SEL  0x0000003F
-#define GPIO_FUNC220_IN_SEL_M  ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S))
-#define GPIO_FUNC220_IN_SEL_V  0x3F
-#define GPIO_FUNC220_IN_SEL_S  0
-
-#define GPIO_FUNC221_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04a4)
-/* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG221_IN_SEL  (BIT(7))
-#define GPIO_SIG221_IN_SEL_M  (BIT(7))
-#define GPIO_SIG221_IN_SEL_V  0x1
-#define GPIO_SIG221_IN_SEL_S  7
-/* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC221_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC221_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC221_IN_INV_SEL_V  0x1
-#define GPIO_FUNC221_IN_INV_SEL_S  6
-/* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC221_IN_SEL  0x0000003F
-#define GPIO_FUNC221_IN_SEL_M  ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S))
-#define GPIO_FUNC221_IN_SEL_V  0x3F
-#define GPIO_FUNC221_IN_SEL_S  0
-
-#define GPIO_FUNC222_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04a8)
-/* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG222_IN_SEL  (BIT(7))
-#define GPIO_SIG222_IN_SEL_M  (BIT(7))
-#define GPIO_SIG222_IN_SEL_V  0x1
-#define GPIO_SIG222_IN_SEL_S  7
-/* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC222_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC222_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC222_IN_INV_SEL_V  0x1
-#define GPIO_FUNC222_IN_INV_SEL_S  6
-/* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC222_IN_SEL  0x0000003F
-#define GPIO_FUNC222_IN_SEL_M  ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S))
-#define GPIO_FUNC222_IN_SEL_V  0x3F
-#define GPIO_FUNC222_IN_SEL_S  0
-
-#define GPIO_FUNC223_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04ac)
-/* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG223_IN_SEL  (BIT(7))
-#define GPIO_SIG223_IN_SEL_M  (BIT(7))
-#define GPIO_SIG223_IN_SEL_V  0x1
-#define GPIO_SIG223_IN_SEL_S  7
-/* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC223_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC223_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC223_IN_INV_SEL_V  0x1
-#define GPIO_FUNC223_IN_INV_SEL_S  6
-/* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC223_IN_SEL  0x0000003F
-#define GPIO_FUNC223_IN_SEL_M  ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S))
-#define GPIO_FUNC223_IN_SEL_V  0x3F
-#define GPIO_FUNC223_IN_SEL_S  0
-
-#define GPIO_FUNC224_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04b0)
-/* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG224_IN_SEL  (BIT(7))
-#define GPIO_SIG224_IN_SEL_M  (BIT(7))
-#define GPIO_SIG224_IN_SEL_V  0x1
-#define GPIO_SIG224_IN_SEL_S  7
-/* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC224_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC224_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC224_IN_INV_SEL_V  0x1
-#define GPIO_FUNC224_IN_INV_SEL_S  6
-/* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC224_IN_SEL  0x0000003F
-#define GPIO_FUNC224_IN_SEL_M  ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S))
-#define GPIO_FUNC224_IN_SEL_V  0x3F
-#define GPIO_FUNC224_IN_SEL_S  0
-
-#define GPIO_FUNC225_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04b4)
-/* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG225_IN_SEL  (BIT(7))
-#define GPIO_SIG225_IN_SEL_M  (BIT(7))
-#define GPIO_SIG225_IN_SEL_V  0x1
-#define GPIO_SIG225_IN_SEL_S  7
-/* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC225_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC225_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC225_IN_INV_SEL_V  0x1
-#define GPIO_FUNC225_IN_INV_SEL_S  6
-/* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC225_IN_SEL  0x0000003F
-#define GPIO_FUNC225_IN_SEL_M  ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S))
-#define GPIO_FUNC225_IN_SEL_V  0x3F
-#define GPIO_FUNC225_IN_SEL_S  0
-
-#define GPIO_FUNC226_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04b8)
-/* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG226_IN_SEL  (BIT(7))
-#define GPIO_SIG226_IN_SEL_M  (BIT(7))
-#define GPIO_SIG226_IN_SEL_V  0x1
-#define GPIO_SIG226_IN_SEL_S  7
-/* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC226_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC226_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC226_IN_INV_SEL_V  0x1
-#define GPIO_FUNC226_IN_INV_SEL_S  6
-/* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC226_IN_SEL  0x0000003F
-#define GPIO_FUNC226_IN_SEL_M  ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S))
-#define GPIO_FUNC226_IN_SEL_V  0x3F
-#define GPIO_FUNC226_IN_SEL_S  0
-
-#define GPIO_FUNC227_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04bc)
-/* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG227_IN_SEL  (BIT(7))
-#define GPIO_SIG227_IN_SEL_M  (BIT(7))
-#define GPIO_SIG227_IN_SEL_V  0x1
-#define GPIO_SIG227_IN_SEL_S  7
-/* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC227_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC227_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC227_IN_INV_SEL_V  0x1
-#define GPIO_FUNC227_IN_INV_SEL_S  6
-/* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC227_IN_SEL  0x0000003F
-#define GPIO_FUNC227_IN_SEL_M  ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S))
-#define GPIO_FUNC227_IN_SEL_V  0x3F
-#define GPIO_FUNC227_IN_SEL_S  0
-
-#define GPIO_FUNC228_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04c0)
-/* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG228_IN_SEL  (BIT(7))
-#define GPIO_SIG228_IN_SEL_M  (BIT(7))
-#define GPIO_SIG228_IN_SEL_V  0x1
-#define GPIO_SIG228_IN_SEL_S  7
-/* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC228_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC228_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC228_IN_INV_SEL_V  0x1
-#define GPIO_FUNC228_IN_INV_SEL_S  6
-/* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC228_IN_SEL  0x0000003F
-#define GPIO_FUNC228_IN_SEL_M  ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S))
-#define GPIO_FUNC228_IN_SEL_V  0x3F
-#define GPIO_FUNC228_IN_SEL_S  0
-
-#define GPIO_FUNC229_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04c4)
-/* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG229_IN_SEL  (BIT(7))
-#define GPIO_SIG229_IN_SEL_M  (BIT(7))
-#define GPIO_SIG229_IN_SEL_V  0x1
-#define GPIO_SIG229_IN_SEL_S  7
-/* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC229_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC229_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC229_IN_INV_SEL_V  0x1
-#define GPIO_FUNC229_IN_INV_SEL_S  6
-/* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC229_IN_SEL  0x0000003F
-#define GPIO_FUNC229_IN_SEL_M  ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S))
-#define GPIO_FUNC229_IN_SEL_V  0x3F
-#define GPIO_FUNC229_IN_SEL_S  0
-
-#define GPIO_FUNC230_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04c8)
-/* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG230_IN_SEL  (BIT(7))
-#define GPIO_SIG230_IN_SEL_M  (BIT(7))
-#define GPIO_SIG230_IN_SEL_V  0x1
-#define GPIO_SIG230_IN_SEL_S  7
-/* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC230_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC230_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC230_IN_INV_SEL_V  0x1
-#define GPIO_FUNC230_IN_INV_SEL_S  6
-/* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC230_IN_SEL  0x0000003F
-#define GPIO_FUNC230_IN_SEL_M  ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S))
-#define GPIO_FUNC230_IN_SEL_V  0x3F
-#define GPIO_FUNC230_IN_SEL_S  0
-
-#define GPIO_FUNC231_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04cc)
-/* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG231_IN_SEL  (BIT(7))
-#define GPIO_SIG231_IN_SEL_M  (BIT(7))
-#define GPIO_SIG231_IN_SEL_V  0x1
-#define GPIO_SIG231_IN_SEL_S  7
-/* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC231_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC231_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC231_IN_INV_SEL_V  0x1
-#define GPIO_FUNC231_IN_INV_SEL_S  6
-/* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC231_IN_SEL  0x0000003F
-#define GPIO_FUNC231_IN_SEL_M  ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S))
-#define GPIO_FUNC231_IN_SEL_V  0x3F
-#define GPIO_FUNC231_IN_SEL_S  0
-
-#define GPIO_FUNC232_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04d0)
-/* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG232_IN_SEL  (BIT(7))
-#define GPIO_SIG232_IN_SEL_M  (BIT(7))
-#define GPIO_SIG232_IN_SEL_V  0x1
-#define GPIO_SIG232_IN_SEL_S  7
-/* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC232_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC232_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC232_IN_INV_SEL_V  0x1
-#define GPIO_FUNC232_IN_INV_SEL_S  6
-/* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC232_IN_SEL  0x0000003F
-#define GPIO_FUNC232_IN_SEL_M  ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S))
-#define GPIO_FUNC232_IN_SEL_V  0x3F
-#define GPIO_FUNC232_IN_SEL_S  0
-
-#define GPIO_FUNC233_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04d4)
-/* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG233_IN_SEL  (BIT(7))
-#define GPIO_SIG233_IN_SEL_M  (BIT(7))
-#define GPIO_SIG233_IN_SEL_V  0x1
-#define GPIO_SIG233_IN_SEL_S  7
-/* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC233_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC233_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC233_IN_INV_SEL_V  0x1
-#define GPIO_FUNC233_IN_INV_SEL_S  6
-/* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC233_IN_SEL  0x0000003F
-#define GPIO_FUNC233_IN_SEL_M  ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S))
-#define GPIO_FUNC233_IN_SEL_V  0x3F
-#define GPIO_FUNC233_IN_SEL_S  0
-
-#define GPIO_FUNC234_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04d8)
-/* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG234_IN_SEL  (BIT(7))
-#define GPIO_SIG234_IN_SEL_M  (BIT(7))
-#define GPIO_SIG234_IN_SEL_V  0x1
-#define GPIO_SIG234_IN_SEL_S  7
-/* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC234_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC234_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC234_IN_INV_SEL_V  0x1
-#define GPIO_FUNC234_IN_INV_SEL_S  6
-/* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC234_IN_SEL  0x0000003F
-#define GPIO_FUNC234_IN_SEL_M  ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S))
-#define GPIO_FUNC234_IN_SEL_V  0x3F
-#define GPIO_FUNC234_IN_SEL_S  0
-
-#define GPIO_FUNC235_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04dc)
-/* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG235_IN_SEL  (BIT(7))
-#define GPIO_SIG235_IN_SEL_M  (BIT(7))
-#define GPIO_SIG235_IN_SEL_V  0x1
-#define GPIO_SIG235_IN_SEL_S  7
-/* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC235_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC235_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC235_IN_INV_SEL_V  0x1
-#define GPIO_FUNC235_IN_INV_SEL_S  6
-/* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC235_IN_SEL  0x0000003F
-#define GPIO_FUNC235_IN_SEL_M  ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S))
-#define GPIO_FUNC235_IN_SEL_V  0x3F
-#define GPIO_FUNC235_IN_SEL_S  0
-
-#define GPIO_FUNC236_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04e0)
-/* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG236_IN_SEL  (BIT(7))
-#define GPIO_SIG236_IN_SEL_M  (BIT(7))
-#define GPIO_SIG236_IN_SEL_V  0x1
-#define GPIO_SIG236_IN_SEL_S  7
-/* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC236_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC236_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC236_IN_INV_SEL_V  0x1
-#define GPIO_FUNC236_IN_INV_SEL_S  6
-/* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC236_IN_SEL  0x0000003F
-#define GPIO_FUNC236_IN_SEL_M  ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S))
-#define GPIO_FUNC236_IN_SEL_V  0x3F
-#define GPIO_FUNC236_IN_SEL_S  0
-
-#define GPIO_FUNC237_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04e4)
-/* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG237_IN_SEL  (BIT(7))
-#define GPIO_SIG237_IN_SEL_M  (BIT(7))
-#define GPIO_SIG237_IN_SEL_V  0x1
-#define GPIO_SIG237_IN_SEL_S  7
-/* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC237_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC237_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC237_IN_INV_SEL_V  0x1
-#define GPIO_FUNC237_IN_INV_SEL_S  6
-/* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC237_IN_SEL  0x0000003F
-#define GPIO_FUNC237_IN_SEL_M  ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S))
-#define GPIO_FUNC237_IN_SEL_V  0x3F
-#define GPIO_FUNC237_IN_SEL_S  0
-
-#define GPIO_FUNC238_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04e8)
-/* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG238_IN_SEL  (BIT(7))
-#define GPIO_SIG238_IN_SEL_M  (BIT(7))
-#define GPIO_SIG238_IN_SEL_V  0x1
-#define GPIO_SIG238_IN_SEL_S  7
-/* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC238_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC238_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC238_IN_INV_SEL_V  0x1
-#define GPIO_FUNC238_IN_INV_SEL_S  6
-/* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC238_IN_SEL  0x0000003F
-#define GPIO_FUNC238_IN_SEL_M  ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S))
-#define GPIO_FUNC238_IN_SEL_V  0x3F
-#define GPIO_FUNC238_IN_SEL_S  0
-
-#define GPIO_FUNC239_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04ec)
-/* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG239_IN_SEL  (BIT(7))
-#define GPIO_SIG239_IN_SEL_M  (BIT(7))
-#define GPIO_SIG239_IN_SEL_V  0x1
-#define GPIO_SIG239_IN_SEL_S  7
-/* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC239_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC239_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC239_IN_INV_SEL_V  0x1
-#define GPIO_FUNC239_IN_INV_SEL_S  6
-/* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC239_IN_SEL  0x0000003F
-#define GPIO_FUNC239_IN_SEL_M  ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S))
-#define GPIO_FUNC239_IN_SEL_V  0x3F
-#define GPIO_FUNC239_IN_SEL_S  0
-
-#define GPIO_FUNC240_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04f0)
-/* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG240_IN_SEL  (BIT(7))
-#define GPIO_SIG240_IN_SEL_M  (BIT(7))
-#define GPIO_SIG240_IN_SEL_V  0x1
-#define GPIO_SIG240_IN_SEL_S  7
-/* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC240_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC240_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC240_IN_INV_SEL_V  0x1
-#define GPIO_FUNC240_IN_INV_SEL_S  6
-/* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC240_IN_SEL  0x0000003F
-#define GPIO_FUNC240_IN_SEL_M  ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S))
-#define GPIO_FUNC240_IN_SEL_V  0x3F
-#define GPIO_FUNC240_IN_SEL_S  0
-
-#define GPIO_FUNC241_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04f4)
-/* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG241_IN_SEL  (BIT(7))
-#define GPIO_SIG241_IN_SEL_M  (BIT(7))
-#define GPIO_SIG241_IN_SEL_V  0x1
-#define GPIO_SIG241_IN_SEL_S  7
-/* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC241_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC241_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC241_IN_INV_SEL_V  0x1
-#define GPIO_FUNC241_IN_INV_SEL_S  6
-/* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC241_IN_SEL  0x0000003F
-#define GPIO_FUNC241_IN_SEL_M  ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S))
-#define GPIO_FUNC241_IN_SEL_V  0x3F
-#define GPIO_FUNC241_IN_SEL_S  0
-
-#define GPIO_FUNC242_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04f8)
-/* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG242_IN_SEL  (BIT(7))
-#define GPIO_SIG242_IN_SEL_M  (BIT(7))
-#define GPIO_SIG242_IN_SEL_V  0x1
-#define GPIO_SIG242_IN_SEL_S  7
-/* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC242_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC242_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC242_IN_INV_SEL_V  0x1
-#define GPIO_FUNC242_IN_INV_SEL_S  6
-/* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC242_IN_SEL  0x0000003F
-#define GPIO_FUNC242_IN_SEL_M  ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S))
-#define GPIO_FUNC242_IN_SEL_V  0x3F
-#define GPIO_FUNC242_IN_SEL_S  0
-
-#define GPIO_FUNC243_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x04fc)
-/* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG243_IN_SEL  (BIT(7))
-#define GPIO_SIG243_IN_SEL_M  (BIT(7))
-#define GPIO_SIG243_IN_SEL_V  0x1
-#define GPIO_SIG243_IN_SEL_S  7
-/* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC243_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC243_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC243_IN_INV_SEL_V  0x1
-#define GPIO_FUNC243_IN_INV_SEL_S  6
-/* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC243_IN_SEL  0x0000003F
-#define GPIO_FUNC243_IN_SEL_M  ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S))
-#define GPIO_FUNC243_IN_SEL_V  0x3F
-#define GPIO_FUNC243_IN_SEL_S  0
-
-#define GPIO_FUNC244_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0500)
-/* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG244_IN_SEL  (BIT(7))
-#define GPIO_SIG244_IN_SEL_M  (BIT(7))
-#define GPIO_SIG244_IN_SEL_V  0x1
-#define GPIO_SIG244_IN_SEL_S  7
-/* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC244_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC244_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC244_IN_INV_SEL_V  0x1
-#define GPIO_FUNC244_IN_INV_SEL_S  6
-/* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC244_IN_SEL  0x0000003F
-#define GPIO_FUNC244_IN_SEL_M  ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S))
-#define GPIO_FUNC244_IN_SEL_V  0x3F
-#define GPIO_FUNC244_IN_SEL_S  0
-
-#define GPIO_FUNC245_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0504)
-/* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG245_IN_SEL  (BIT(7))
-#define GPIO_SIG245_IN_SEL_M  (BIT(7))
-#define GPIO_SIG245_IN_SEL_V  0x1
-#define GPIO_SIG245_IN_SEL_S  7
-/* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC245_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC245_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC245_IN_INV_SEL_V  0x1
-#define GPIO_FUNC245_IN_INV_SEL_S  6
-/* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC245_IN_SEL  0x0000003F
-#define GPIO_FUNC245_IN_SEL_M  ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S))
-#define GPIO_FUNC245_IN_SEL_V  0x3F
-#define GPIO_FUNC245_IN_SEL_S  0
-
-#define GPIO_FUNC246_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0508)
-/* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG246_IN_SEL  (BIT(7))
-#define GPIO_SIG246_IN_SEL_M  (BIT(7))
-#define GPIO_SIG246_IN_SEL_V  0x1
-#define GPIO_SIG246_IN_SEL_S  7
-/* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC246_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC246_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC246_IN_INV_SEL_V  0x1
-#define GPIO_FUNC246_IN_INV_SEL_S  6
-/* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC246_IN_SEL  0x0000003F
-#define GPIO_FUNC246_IN_SEL_M  ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S))
-#define GPIO_FUNC246_IN_SEL_V  0x3F
-#define GPIO_FUNC246_IN_SEL_S  0
-
-#define GPIO_FUNC247_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x050c)
-/* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG247_IN_SEL  (BIT(7))
-#define GPIO_SIG247_IN_SEL_M  (BIT(7))
-#define GPIO_SIG247_IN_SEL_V  0x1
-#define GPIO_SIG247_IN_SEL_S  7
-/* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC247_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC247_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC247_IN_INV_SEL_V  0x1
-#define GPIO_FUNC247_IN_INV_SEL_S  6
-/* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC247_IN_SEL  0x0000003F
-#define GPIO_FUNC247_IN_SEL_M  ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S))
-#define GPIO_FUNC247_IN_SEL_V  0x3F
-#define GPIO_FUNC247_IN_SEL_S  0
-
-#define GPIO_FUNC248_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0510)
-/* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG248_IN_SEL  (BIT(7))
-#define GPIO_SIG248_IN_SEL_M  (BIT(7))
-#define GPIO_SIG248_IN_SEL_V  0x1
-#define GPIO_SIG248_IN_SEL_S  7
-/* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC248_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC248_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC248_IN_INV_SEL_V  0x1
-#define GPIO_FUNC248_IN_INV_SEL_S  6
-/* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC248_IN_SEL  0x0000003F
-#define GPIO_FUNC248_IN_SEL_M  ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S))
-#define GPIO_FUNC248_IN_SEL_V  0x3F
-#define GPIO_FUNC248_IN_SEL_S  0
-
-#define GPIO_FUNC249_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0514)
-/* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG249_IN_SEL  (BIT(7))
-#define GPIO_SIG249_IN_SEL_M  (BIT(7))
-#define GPIO_SIG249_IN_SEL_V  0x1
-#define GPIO_SIG249_IN_SEL_S  7
-/* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC249_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC249_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC249_IN_INV_SEL_V  0x1
-#define GPIO_FUNC249_IN_INV_SEL_S  6
-/* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC249_IN_SEL  0x0000003F
-#define GPIO_FUNC249_IN_SEL_M  ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S))
-#define GPIO_FUNC249_IN_SEL_V  0x3F
-#define GPIO_FUNC249_IN_SEL_S  0
-
-#define GPIO_FUNC250_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0518)
-/* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG250_IN_SEL  (BIT(7))
-#define GPIO_SIG250_IN_SEL_M  (BIT(7))
-#define GPIO_SIG250_IN_SEL_V  0x1
-#define GPIO_SIG250_IN_SEL_S  7
-/* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC250_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC250_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC250_IN_INV_SEL_V  0x1
-#define GPIO_FUNC250_IN_INV_SEL_S  6
-/* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC250_IN_SEL  0x0000003F
-#define GPIO_FUNC250_IN_SEL_M  ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S))
-#define GPIO_FUNC250_IN_SEL_V  0x3F
-#define GPIO_FUNC250_IN_SEL_S  0
-
-#define GPIO_FUNC251_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x051c)
-/* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG251_IN_SEL  (BIT(7))
-#define GPIO_SIG251_IN_SEL_M  (BIT(7))
-#define GPIO_SIG251_IN_SEL_V  0x1
-#define GPIO_SIG251_IN_SEL_S  7
-/* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC251_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC251_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC251_IN_INV_SEL_V  0x1
-#define GPIO_FUNC251_IN_INV_SEL_S  6
-/* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC251_IN_SEL  0x0000003F
-#define GPIO_FUNC251_IN_SEL_M  ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S))
-#define GPIO_FUNC251_IN_SEL_V  0x3F
-#define GPIO_FUNC251_IN_SEL_S  0
-
-#define GPIO_FUNC252_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0520)
-/* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG252_IN_SEL  (BIT(7))
-#define GPIO_SIG252_IN_SEL_M  (BIT(7))
-#define GPIO_SIG252_IN_SEL_V  0x1
-#define GPIO_SIG252_IN_SEL_S  7
-/* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC252_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC252_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC252_IN_INV_SEL_V  0x1
-#define GPIO_FUNC252_IN_INV_SEL_S  6
-/* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC252_IN_SEL  0x0000003F
-#define GPIO_FUNC252_IN_SEL_M  ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S))
-#define GPIO_FUNC252_IN_SEL_V  0x3F
-#define GPIO_FUNC252_IN_SEL_S  0
-
-#define GPIO_FUNC253_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0524)
-/* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG253_IN_SEL  (BIT(7))
-#define GPIO_SIG253_IN_SEL_M  (BIT(7))
-#define GPIO_SIG253_IN_SEL_V  0x1
-#define GPIO_SIG253_IN_SEL_S  7
-/* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC253_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC253_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC253_IN_INV_SEL_V  0x1
-#define GPIO_FUNC253_IN_INV_SEL_S  6
-/* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC253_IN_SEL  0x0000003F
-#define GPIO_FUNC253_IN_SEL_M  ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S))
-#define GPIO_FUNC253_IN_SEL_V  0x3F
-#define GPIO_FUNC253_IN_SEL_S  0
-
-#define GPIO_FUNC254_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0528)
-/* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG254_IN_SEL  (BIT(7))
-#define GPIO_SIG254_IN_SEL_M  (BIT(7))
-#define GPIO_SIG254_IN_SEL_V  0x1
-#define GPIO_SIG254_IN_SEL_S  7
-/* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC254_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC254_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC254_IN_INV_SEL_V  0x1
-#define GPIO_FUNC254_IN_INV_SEL_S  6
-/* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC254_IN_SEL  0x0000003F
-#define GPIO_FUNC254_IN_SEL_M  ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S))
-#define GPIO_FUNC254_IN_SEL_V  0x3F
-#define GPIO_FUNC254_IN_SEL_S  0
-
-#define GPIO_FUNC255_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x052c)
-/* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: x ; */
-/*description: if the slow signal bypass the io matrix or not if you want  setting
- the value to 1*/
-#define GPIO_SIG255_IN_SEL  (BIT(7))
-#define GPIO_SIG255_IN_SEL_M  (BIT(7))
-#define GPIO_SIG255_IN_SEL_V  0x1
-#define GPIO_SIG255_IN_SEL_S  7
-/* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */
-/*description: revert the value of the input if you want to revert  please set the value to 1*/
-#define GPIO_FUNC255_IN_INV_SEL  (BIT(6))
-#define GPIO_FUNC255_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC255_IN_INV_SEL_V  0x1
-#define GPIO_FUNC255_IN_INV_SEL_S  6
-/* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */
-/*description: select one of the 256 inputs*/
-#define GPIO_FUNC255_IN_SEL  0x0000003F
-#define GPIO_FUNC255_IN_SEL_M  ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S))
-#define GPIO_FUNC255_IN_SEL_V  0x3F
-#define GPIO_FUNC255_IN_SEL_S  0
-
-#define GPIO_FUNC0_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0530)
-/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC0_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC0_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC0_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC0_OEN_INV_SEL_S  11
-/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC0_OEN_SEL  (BIT(10))
-#define GPIO_FUNC0_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC0_OEN_SEL_V  0x1
-#define GPIO_FUNC0_OEN_SEL_S  10
-/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC0_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC0_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC0_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC0_OUT_INV_SEL_S  9
-/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC0_OUT_SEL  0x000001FF
-#define GPIO_FUNC0_OUT_SEL_M  ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S))
-#define GPIO_FUNC0_OUT_SEL_V  0x1FF
-#define GPIO_FUNC0_OUT_SEL_S  0
-
-#define GPIO_FUNC1_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0534)
-/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC1_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC1_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC1_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC1_OEN_INV_SEL_S  11
-/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC1_OEN_SEL  (BIT(10))
-#define GPIO_FUNC1_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC1_OEN_SEL_V  0x1
-#define GPIO_FUNC1_OEN_SEL_S  10
-/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC1_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC1_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC1_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC1_OUT_INV_SEL_S  9
-/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC1_OUT_SEL  0x000001FF
-#define GPIO_FUNC1_OUT_SEL_M  ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S))
-#define GPIO_FUNC1_OUT_SEL_V  0x1FF
-#define GPIO_FUNC1_OUT_SEL_S  0
-
-#define GPIO_FUNC2_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0538)
-/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC2_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC2_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC2_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC2_OEN_INV_SEL_S  11
-/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC2_OEN_SEL  (BIT(10))
-#define GPIO_FUNC2_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC2_OEN_SEL_V  0x1
-#define GPIO_FUNC2_OEN_SEL_S  10
-/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC2_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC2_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC2_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC2_OUT_INV_SEL_S  9
-/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC2_OUT_SEL  0x000001FF
-#define GPIO_FUNC2_OUT_SEL_M  ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S))
-#define GPIO_FUNC2_OUT_SEL_V  0x1FF
-#define GPIO_FUNC2_OUT_SEL_S  0
-
-#define GPIO_FUNC3_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x053c)
-/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC3_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC3_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC3_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC3_OEN_INV_SEL_S  11
-/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC3_OEN_SEL  (BIT(10))
-#define GPIO_FUNC3_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC3_OEN_SEL_V  0x1
-#define GPIO_FUNC3_OEN_SEL_S  10
-/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC3_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC3_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC3_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC3_OUT_INV_SEL_S  9
-/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC3_OUT_SEL  0x000001FF
-#define GPIO_FUNC3_OUT_SEL_M  ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S))
-#define GPIO_FUNC3_OUT_SEL_V  0x1FF
-#define GPIO_FUNC3_OUT_SEL_S  0
-
-#define GPIO_FUNC4_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0540)
-/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC4_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC4_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC4_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC4_OEN_INV_SEL_S  11
-/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC4_OEN_SEL  (BIT(10))
-#define GPIO_FUNC4_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC4_OEN_SEL_V  0x1
-#define GPIO_FUNC4_OEN_SEL_S  10
-/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC4_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC4_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC4_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC4_OUT_INV_SEL_S  9
-/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC4_OUT_SEL  0x000001FF
-#define GPIO_FUNC4_OUT_SEL_M  ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S))
-#define GPIO_FUNC4_OUT_SEL_V  0x1FF
-#define GPIO_FUNC4_OUT_SEL_S  0
-
-#define GPIO_FUNC5_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0544)
-/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC5_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC5_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC5_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC5_OEN_INV_SEL_S  11
-/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC5_OEN_SEL  (BIT(10))
-#define GPIO_FUNC5_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC5_OEN_SEL_V  0x1
-#define GPIO_FUNC5_OEN_SEL_S  10
-/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC5_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC5_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC5_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC5_OUT_INV_SEL_S  9
-/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC5_OUT_SEL  0x000001FF
-#define GPIO_FUNC5_OUT_SEL_M  ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S))
-#define GPIO_FUNC5_OUT_SEL_V  0x1FF
-#define GPIO_FUNC5_OUT_SEL_S  0
-
-#define GPIO_FUNC6_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0548)
-/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC6_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC6_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC6_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC6_OEN_INV_SEL_S  11
-/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC6_OEN_SEL  (BIT(10))
-#define GPIO_FUNC6_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC6_OEN_SEL_V  0x1
-#define GPIO_FUNC6_OEN_SEL_S  10
-/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC6_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC6_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC6_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC6_OUT_INV_SEL_S  9
-/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC6_OUT_SEL  0x000001FF
-#define GPIO_FUNC6_OUT_SEL_M  ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S))
-#define GPIO_FUNC6_OUT_SEL_V  0x1FF
-#define GPIO_FUNC6_OUT_SEL_S  0
-
-#define GPIO_FUNC7_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x054c)
-/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC7_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC7_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC7_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC7_OEN_INV_SEL_S  11
-/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC7_OEN_SEL  (BIT(10))
-#define GPIO_FUNC7_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC7_OEN_SEL_V  0x1
-#define GPIO_FUNC7_OEN_SEL_S  10
-/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC7_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC7_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC7_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC7_OUT_INV_SEL_S  9
-/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC7_OUT_SEL  0x000001FF
-#define GPIO_FUNC7_OUT_SEL_M  ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S))
-#define GPIO_FUNC7_OUT_SEL_V  0x1FF
-#define GPIO_FUNC7_OUT_SEL_S  0
-
-#define GPIO_FUNC8_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0550)
-/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC8_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC8_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC8_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC8_OEN_INV_SEL_S  11
-/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC8_OEN_SEL  (BIT(10))
-#define GPIO_FUNC8_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC8_OEN_SEL_V  0x1
-#define GPIO_FUNC8_OEN_SEL_S  10
-/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC8_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC8_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC8_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC8_OUT_INV_SEL_S  9
-/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC8_OUT_SEL  0x000001FF
-#define GPIO_FUNC8_OUT_SEL_M  ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S))
-#define GPIO_FUNC8_OUT_SEL_V  0x1FF
-#define GPIO_FUNC8_OUT_SEL_S  0
-
-#define GPIO_FUNC9_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0554)
-/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC9_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC9_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC9_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC9_OEN_INV_SEL_S  11
-/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC9_OEN_SEL  (BIT(10))
-#define GPIO_FUNC9_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC9_OEN_SEL_V  0x1
-#define GPIO_FUNC9_OEN_SEL_S  10
-/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC9_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC9_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC9_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC9_OUT_INV_SEL_S  9
-/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC9_OUT_SEL  0x000001FF
-#define GPIO_FUNC9_OUT_SEL_M  ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S))
-#define GPIO_FUNC9_OUT_SEL_V  0x1FF
-#define GPIO_FUNC9_OUT_SEL_S  0
-
-#define GPIO_FUNC10_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0558)
-/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC10_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC10_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC10_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC10_OEN_INV_SEL_S  11
-/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC10_OEN_SEL  (BIT(10))
-#define GPIO_FUNC10_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC10_OEN_SEL_V  0x1
-#define GPIO_FUNC10_OEN_SEL_S  10
-/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC10_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC10_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC10_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC10_OUT_INV_SEL_S  9
-/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC10_OUT_SEL  0x000001FF
-#define GPIO_FUNC10_OUT_SEL_M  ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S))
-#define GPIO_FUNC10_OUT_SEL_V  0x1FF
-#define GPIO_FUNC10_OUT_SEL_S  0
-
-#define GPIO_FUNC11_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x055c)
-/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC11_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC11_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC11_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC11_OEN_INV_SEL_S  11
-/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC11_OEN_SEL  (BIT(10))
-#define GPIO_FUNC11_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC11_OEN_SEL_V  0x1
-#define GPIO_FUNC11_OEN_SEL_S  10
-/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC11_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC11_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC11_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC11_OUT_INV_SEL_S  9
-/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC11_OUT_SEL  0x000001FF
-#define GPIO_FUNC11_OUT_SEL_M  ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S))
-#define GPIO_FUNC11_OUT_SEL_V  0x1FF
-#define GPIO_FUNC11_OUT_SEL_S  0
-
-#define GPIO_FUNC12_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0560)
-/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC12_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC12_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC12_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC12_OEN_INV_SEL_S  11
-/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC12_OEN_SEL  (BIT(10))
-#define GPIO_FUNC12_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC12_OEN_SEL_V  0x1
-#define GPIO_FUNC12_OEN_SEL_S  10
-/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC12_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC12_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC12_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC12_OUT_INV_SEL_S  9
-/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC12_OUT_SEL  0x000001FF
-#define GPIO_FUNC12_OUT_SEL_M  ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S))
-#define GPIO_FUNC12_OUT_SEL_V  0x1FF
-#define GPIO_FUNC12_OUT_SEL_S  0
-
-#define GPIO_FUNC13_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0564)
-/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC13_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC13_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC13_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC13_OEN_INV_SEL_S  11
-/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC13_OEN_SEL  (BIT(10))
-#define GPIO_FUNC13_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC13_OEN_SEL_V  0x1
-#define GPIO_FUNC13_OEN_SEL_S  10
-/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC13_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC13_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC13_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC13_OUT_INV_SEL_S  9
-/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC13_OUT_SEL  0x000001FF
-#define GPIO_FUNC13_OUT_SEL_M  ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S))
-#define GPIO_FUNC13_OUT_SEL_V  0x1FF
-#define GPIO_FUNC13_OUT_SEL_S  0
-
-#define GPIO_FUNC14_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0568)
-/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC14_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC14_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC14_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC14_OEN_INV_SEL_S  11
-/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC14_OEN_SEL  (BIT(10))
-#define GPIO_FUNC14_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC14_OEN_SEL_V  0x1
-#define GPIO_FUNC14_OEN_SEL_S  10
-/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC14_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC14_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC14_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC14_OUT_INV_SEL_S  9
-/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC14_OUT_SEL  0x000001FF
-#define GPIO_FUNC14_OUT_SEL_M  ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S))
-#define GPIO_FUNC14_OUT_SEL_V  0x1FF
-#define GPIO_FUNC14_OUT_SEL_S  0
-
-#define GPIO_FUNC15_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x056c)
-/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC15_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC15_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC15_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC15_OEN_INV_SEL_S  11
-/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC15_OEN_SEL  (BIT(10))
-#define GPIO_FUNC15_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC15_OEN_SEL_V  0x1
-#define GPIO_FUNC15_OEN_SEL_S  10
-/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC15_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC15_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC15_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC15_OUT_INV_SEL_S  9
-/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC15_OUT_SEL  0x000001FF
-#define GPIO_FUNC15_OUT_SEL_M  ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S))
-#define GPIO_FUNC15_OUT_SEL_V  0x1FF
-#define GPIO_FUNC15_OUT_SEL_S  0
-
-#define GPIO_FUNC16_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0570)
-/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC16_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC16_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC16_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC16_OEN_INV_SEL_S  11
-/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC16_OEN_SEL  (BIT(10))
-#define GPIO_FUNC16_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC16_OEN_SEL_V  0x1
-#define GPIO_FUNC16_OEN_SEL_S  10
-/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC16_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC16_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC16_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC16_OUT_INV_SEL_S  9
-/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC16_OUT_SEL  0x000001FF
-#define GPIO_FUNC16_OUT_SEL_M  ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S))
-#define GPIO_FUNC16_OUT_SEL_V  0x1FF
-#define GPIO_FUNC16_OUT_SEL_S  0
-
-#define GPIO_FUNC17_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0574)
-/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC17_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC17_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC17_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC17_OEN_INV_SEL_S  11
-/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC17_OEN_SEL  (BIT(10))
-#define GPIO_FUNC17_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC17_OEN_SEL_V  0x1
-#define GPIO_FUNC17_OEN_SEL_S  10
-/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC17_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC17_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC17_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC17_OUT_INV_SEL_S  9
-/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC17_OUT_SEL  0x000001FF
-#define GPIO_FUNC17_OUT_SEL_M  ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S))
-#define GPIO_FUNC17_OUT_SEL_V  0x1FF
-#define GPIO_FUNC17_OUT_SEL_S  0
-
-#define GPIO_FUNC18_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0578)
-/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC18_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC18_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC18_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC18_OEN_INV_SEL_S  11
-/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC18_OEN_SEL  (BIT(10))
-#define GPIO_FUNC18_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC18_OEN_SEL_V  0x1
-#define GPIO_FUNC18_OEN_SEL_S  10
-/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC18_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC18_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC18_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC18_OUT_INV_SEL_S  9
-/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC18_OUT_SEL  0x000001FF
-#define GPIO_FUNC18_OUT_SEL_M  ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S))
-#define GPIO_FUNC18_OUT_SEL_V  0x1FF
-#define GPIO_FUNC18_OUT_SEL_S  0
-
-#define GPIO_FUNC19_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x057c)
-/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC19_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC19_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC19_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC19_OEN_INV_SEL_S  11
-/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC19_OEN_SEL  (BIT(10))
-#define GPIO_FUNC19_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC19_OEN_SEL_V  0x1
-#define GPIO_FUNC19_OEN_SEL_S  10
-/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC19_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC19_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC19_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC19_OUT_INV_SEL_S  9
-/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC19_OUT_SEL  0x000001FF
-#define GPIO_FUNC19_OUT_SEL_M  ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S))
-#define GPIO_FUNC19_OUT_SEL_V  0x1FF
-#define GPIO_FUNC19_OUT_SEL_S  0
-
-#define GPIO_FUNC20_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0580)
-/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC20_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC20_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC20_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC20_OEN_INV_SEL_S  11
-/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC20_OEN_SEL  (BIT(10))
-#define GPIO_FUNC20_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC20_OEN_SEL_V  0x1
-#define GPIO_FUNC20_OEN_SEL_S  10
-/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC20_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC20_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC20_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC20_OUT_INV_SEL_S  9
-/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC20_OUT_SEL  0x000001FF
-#define GPIO_FUNC20_OUT_SEL_M  ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S))
-#define GPIO_FUNC20_OUT_SEL_V  0x1FF
-#define GPIO_FUNC20_OUT_SEL_S  0
-
-#define GPIO_FUNC21_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0584)
-/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC21_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC21_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC21_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC21_OEN_INV_SEL_S  11
-/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC21_OEN_SEL  (BIT(10))
-#define GPIO_FUNC21_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC21_OEN_SEL_V  0x1
-#define GPIO_FUNC21_OEN_SEL_S  10
-/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC21_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC21_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC21_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC21_OUT_INV_SEL_S  9
-/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC21_OUT_SEL  0x000001FF
-#define GPIO_FUNC21_OUT_SEL_M  ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S))
-#define GPIO_FUNC21_OUT_SEL_V  0x1FF
-#define GPIO_FUNC21_OUT_SEL_S  0
-
-#define GPIO_FUNC22_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0588)
-/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC22_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC22_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC22_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC22_OEN_INV_SEL_S  11
-/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC22_OEN_SEL  (BIT(10))
-#define GPIO_FUNC22_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC22_OEN_SEL_V  0x1
-#define GPIO_FUNC22_OEN_SEL_S  10
-/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC22_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC22_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC22_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC22_OUT_INV_SEL_S  9
-/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC22_OUT_SEL  0x000001FF
-#define GPIO_FUNC22_OUT_SEL_M  ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S))
-#define GPIO_FUNC22_OUT_SEL_V  0x1FF
-#define GPIO_FUNC22_OUT_SEL_S  0
-
-#define GPIO_FUNC23_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x058c)
-/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC23_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC23_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC23_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC23_OEN_INV_SEL_S  11
-/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC23_OEN_SEL  (BIT(10))
-#define GPIO_FUNC23_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC23_OEN_SEL_V  0x1
-#define GPIO_FUNC23_OEN_SEL_S  10
-/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC23_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC23_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC23_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC23_OUT_INV_SEL_S  9
-/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC23_OUT_SEL  0x000001FF
-#define GPIO_FUNC23_OUT_SEL_M  ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S))
-#define GPIO_FUNC23_OUT_SEL_V  0x1FF
-#define GPIO_FUNC23_OUT_SEL_S  0
-
-#define GPIO_FUNC24_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0590)
-/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC24_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC24_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC24_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC24_OEN_INV_SEL_S  11
-/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC24_OEN_SEL  (BIT(10))
-#define GPIO_FUNC24_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC24_OEN_SEL_V  0x1
-#define GPIO_FUNC24_OEN_SEL_S  10
-/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC24_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC24_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC24_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC24_OUT_INV_SEL_S  9
-/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC24_OUT_SEL  0x000001FF
-#define GPIO_FUNC24_OUT_SEL_M  ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S))
-#define GPIO_FUNC24_OUT_SEL_V  0x1FF
-#define GPIO_FUNC24_OUT_SEL_S  0
-
-#define GPIO_FUNC25_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0594)
-/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC25_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC25_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC25_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC25_OEN_INV_SEL_S  11
-/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC25_OEN_SEL  (BIT(10))
-#define GPIO_FUNC25_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC25_OEN_SEL_V  0x1
-#define GPIO_FUNC25_OEN_SEL_S  10
-/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC25_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC25_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC25_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC25_OUT_INV_SEL_S  9
-/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC25_OUT_SEL  0x000001FF
-#define GPIO_FUNC25_OUT_SEL_M  ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S))
-#define GPIO_FUNC25_OUT_SEL_V  0x1FF
-#define GPIO_FUNC25_OUT_SEL_S  0
-
-#define GPIO_FUNC26_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x0598)
-/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC26_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC26_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC26_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC26_OEN_INV_SEL_S  11
-/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC26_OEN_SEL  (BIT(10))
-#define GPIO_FUNC26_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC26_OEN_SEL_V  0x1
-#define GPIO_FUNC26_OEN_SEL_S  10
-/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC26_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC26_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC26_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC26_OUT_INV_SEL_S  9
-/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC26_OUT_SEL  0x000001FF
-#define GPIO_FUNC26_OUT_SEL_M  ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S))
-#define GPIO_FUNC26_OUT_SEL_V  0x1FF
-#define GPIO_FUNC26_OUT_SEL_S  0
-
-#define GPIO_FUNC27_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x059c)
-/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC27_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC27_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC27_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC27_OEN_INV_SEL_S  11
-/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC27_OEN_SEL  (BIT(10))
-#define GPIO_FUNC27_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC27_OEN_SEL_V  0x1
-#define GPIO_FUNC27_OEN_SEL_S  10
-/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC27_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC27_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC27_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC27_OUT_INV_SEL_S  9
-/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC27_OUT_SEL  0x000001FF
-#define GPIO_FUNC27_OUT_SEL_M  ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S))
-#define GPIO_FUNC27_OUT_SEL_V  0x1FF
-#define GPIO_FUNC27_OUT_SEL_S  0
-
-#define GPIO_FUNC28_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05a0)
-/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC28_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC28_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC28_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC28_OEN_INV_SEL_S  11
-/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC28_OEN_SEL  (BIT(10))
-#define GPIO_FUNC28_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC28_OEN_SEL_V  0x1
-#define GPIO_FUNC28_OEN_SEL_S  10
-/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC28_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC28_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC28_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC28_OUT_INV_SEL_S  9
-/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC28_OUT_SEL  0x000001FF
-#define GPIO_FUNC28_OUT_SEL_M  ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S))
-#define GPIO_FUNC28_OUT_SEL_V  0x1FF
-#define GPIO_FUNC28_OUT_SEL_S  0
-
-#define GPIO_FUNC29_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05a4)
-/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC29_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC29_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC29_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC29_OEN_INV_SEL_S  11
-/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC29_OEN_SEL  (BIT(10))
-#define GPIO_FUNC29_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC29_OEN_SEL_V  0x1
-#define GPIO_FUNC29_OEN_SEL_S  10
-/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC29_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC29_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC29_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC29_OUT_INV_SEL_S  9
-/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC29_OUT_SEL  0x000001FF
-#define GPIO_FUNC29_OUT_SEL_M  ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S))
-#define GPIO_FUNC29_OUT_SEL_V  0x1FF
-#define GPIO_FUNC29_OUT_SEL_S  0
-
-#define GPIO_FUNC30_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05a8)
-/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC30_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC30_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC30_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC30_OEN_INV_SEL_S  11
-/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC30_OEN_SEL  (BIT(10))
-#define GPIO_FUNC30_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC30_OEN_SEL_V  0x1
-#define GPIO_FUNC30_OEN_SEL_S  10
-/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC30_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC30_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC30_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC30_OUT_INV_SEL_S  9
-/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC30_OUT_SEL  0x000001FF
-#define GPIO_FUNC30_OUT_SEL_M  ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S))
-#define GPIO_FUNC30_OUT_SEL_V  0x1FF
-#define GPIO_FUNC30_OUT_SEL_S  0
-
-#define GPIO_FUNC31_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05ac)
-/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC31_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC31_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC31_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC31_OEN_INV_SEL_S  11
-/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC31_OEN_SEL  (BIT(10))
-#define GPIO_FUNC31_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC31_OEN_SEL_V  0x1
-#define GPIO_FUNC31_OEN_SEL_S  10
-/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC31_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC31_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC31_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC31_OUT_INV_SEL_S  9
-/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC31_OUT_SEL  0x000001FF
-#define GPIO_FUNC31_OUT_SEL_M  ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S))
-#define GPIO_FUNC31_OUT_SEL_V  0x1FF
-#define GPIO_FUNC31_OUT_SEL_S  0
-
-#define GPIO_FUNC32_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05b0)
-/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC32_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC32_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC32_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC32_OEN_INV_SEL_S  11
-/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC32_OEN_SEL  (BIT(10))
-#define GPIO_FUNC32_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC32_OEN_SEL_V  0x1
-#define GPIO_FUNC32_OEN_SEL_S  10
-/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC32_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC32_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC32_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC32_OUT_INV_SEL_S  9
-/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC32_OUT_SEL  0x000001FF
-#define GPIO_FUNC32_OUT_SEL_M  ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S))
-#define GPIO_FUNC32_OUT_SEL_V  0x1FF
-#define GPIO_FUNC32_OUT_SEL_S  0
-
-#define GPIO_FUNC33_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05b4)
-/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC33_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC33_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC33_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC33_OEN_INV_SEL_S  11
-/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC33_OEN_SEL  (BIT(10))
-#define GPIO_FUNC33_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC33_OEN_SEL_V  0x1
-#define GPIO_FUNC33_OEN_SEL_S  10
-/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC33_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC33_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC33_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC33_OUT_INV_SEL_S  9
-/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC33_OUT_SEL  0x000001FF
-#define GPIO_FUNC33_OUT_SEL_M  ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S))
-#define GPIO_FUNC33_OUT_SEL_V  0x1FF
-#define GPIO_FUNC33_OUT_SEL_S  0
-
-#define GPIO_FUNC34_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05b8)
-/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC34_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC34_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC34_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC34_OEN_INV_SEL_S  11
-/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC34_OEN_SEL  (BIT(10))
-#define GPIO_FUNC34_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC34_OEN_SEL_V  0x1
-#define GPIO_FUNC34_OEN_SEL_S  10
-/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC34_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC34_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC34_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC34_OUT_INV_SEL_S  9
-/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC34_OUT_SEL  0x000001FF
-#define GPIO_FUNC34_OUT_SEL_M  ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S))
-#define GPIO_FUNC34_OUT_SEL_V  0x1FF
-#define GPIO_FUNC34_OUT_SEL_S  0
-
-#define GPIO_FUNC35_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05bc)
-/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC35_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC35_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC35_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC35_OEN_INV_SEL_S  11
-/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC35_OEN_SEL  (BIT(10))
-#define GPIO_FUNC35_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC35_OEN_SEL_V  0x1
-#define GPIO_FUNC35_OEN_SEL_S  10
-/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC35_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC35_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC35_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC35_OUT_INV_SEL_S  9
-/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC35_OUT_SEL  0x000001FF
-#define GPIO_FUNC35_OUT_SEL_M  ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S))
-#define GPIO_FUNC35_OUT_SEL_V  0x1FF
-#define GPIO_FUNC35_OUT_SEL_S  0
-
-#define GPIO_FUNC36_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05c0)
-/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC36_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC36_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC36_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC36_OEN_INV_SEL_S  11
-/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC36_OEN_SEL  (BIT(10))
-#define GPIO_FUNC36_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC36_OEN_SEL_V  0x1
-#define GPIO_FUNC36_OEN_SEL_S  10
-/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC36_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC36_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC36_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC36_OUT_INV_SEL_S  9
-/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC36_OUT_SEL  0x000001FF
-#define GPIO_FUNC36_OUT_SEL_M  ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S))
-#define GPIO_FUNC36_OUT_SEL_V  0x1FF
-#define GPIO_FUNC36_OUT_SEL_S  0
-
-#define GPIO_FUNC37_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05c4)
-/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC37_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC37_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC37_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC37_OEN_INV_SEL_S  11
-/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC37_OEN_SEL  (BIT(10))
-#define GPIO_FUNC37_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC37_OEN_SEL_V  0x1
-#define GPIO_FUNC37_OEN_SEL_S  10
-/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC37_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC37_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC37_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC37_OUT_INV_SEL_S  9
-/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC37_OUT_SEL  0x000001FF
-#define GPIO_FUNC37_OUT_SEL_M  ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S))
-#define GPIO_FUNC37_OUT_SEL_V  0x1FF
-#define GPIO_FUNC37_OUT_SEL_S  0
-
-#define GPIO_FUNC38_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05c8)
-/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC38_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC38_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC38_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC38_OEN_INV_SEL_S  11
-/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC38_OEN_SEL  (BIT(10))
-#define GPIO_FUNC38_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC38_OEN_SEL_V  0x1
-#define GPIO_FUNC38_OEN_SEL_S  10
-/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC38_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC38_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC38_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC38_OUT_INV_SEL_S  9
-/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC38_OUT_SEL  0x000001FF
-#define GPIO_FUNC38_OUT_SEL_M  ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S))
-#define GPIO_FUNC38_OUT_SEL_V  0x1FF
-#define GPIO_FUNC38_OUT_SEL_S  0
-
-#define GPIO_FUNC39_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x05cc)
-/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */
-/*description: invert the output enable value  if you want to revert the output
- enable value  setting the value to 1*/
-#define GPIO_FUNC39_OEN_INV_SEL  (BIT(11))
-#define GPIO_FUNC39_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC39_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC39_OEN_INV_SEL_S  11
-/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */
-/*description: weather using the logical oen signal or not using the value setting
- by the register*/
-#define GPIO_FUNC39_OEN_SEL  (BIT(10))
-#define GPIO_FUNC39_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC39_OEN_SEL_V  0x1
-#define GPIO_FUNC39_OEN_SEL_S  10
-/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */
-/*description: invert the output value  if you want to revert the output value
-  setting the value to 1*/
-#define GPIO_FUNC39_OUT_INV_SEL  (BIT(9))
-#define GPIO_FUNC39_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC39_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC39_OUT_INV_SEL_S  9
-/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */
-/*description: select one of the 256 output to 40 GPIO*/
-#define GPIO_FUNC39_OUT_SEL  0x000001FF
-#define GPIO_FUNC39_OUT_SEL_M  ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S))
-#define GPIO_FUNC39_OUT_SEL_V  0x1FF
-#define GPIO_FUNC39_OUT_SEL_S  0
-
-
-
-
-#endif /*_SOC_GPIO_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/gpio_sd_reg.h b/tools/sdk/include/soc/soc/gpio_sd_reg.h
deleted file mode 100644
index be39fcf2c20..00000000000
--- a/tools/sdk/include/soc/soc/gpio_sd_reg.h
+++ /dev/null
@@ -1,160 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_GPIO_SD_REG_H_
-#define _SOC_GPIO_SD_REG_H_
-
-#include "soc.h"
-#define GPIO_SIGMADELTA0_REG          (DR_REG_GPIO_SD_BASE + 0x0000)
-/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD0_PRESCALE  0x000000FF
-#define GPIO_SD0_PRESCALE_M  ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
-#define GPIO_SD0_PRESCALE_V  0xFF
-#define GPIO_SD0_PRESCALE_S  8
-/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD0_IN  0x000000FF
-#define GPIO_SD0_IN_M  ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
-#define GPIO_SD0_IN_V  0xFF
-#define GPIO_SD0_IN_S  0
-
-#define GPIO_SIGMADELTA1_REG          (DR_REG_GPIO_SD_BASE + 0x0004)
-/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD1_PRESCALE  0x000000FF
-#define GPIO_SD1_PRESCALE_M  ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
-#define GPIO_SD1_PRESCALE_V  0xFF
-#define GPIO_SD1_PRESCALE_S  8
-/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD1_IN  0x000000FF
-#define GPIO_SD1_IN_M  ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
-#define GPIO_SD1_IN_V  0xFF
-#define GPIO_SD1_IN_S  0
-
-#define GPIO_SIGMADELTA2_REG          (DR_REG_GPIO_SD_BASE + 0x0008)
-/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD2_PRESCALE  0x000000FF
-#define GPIO_SD2_PRESCALE_M  ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
-#define GPIO_SD2_PRESCALE_V  0xFF
-#define GPIO_SD2_PRESCALE_S  8
-/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD2_IN  0x000000FF
-#define GPIO_SD2_IN_M  ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
-#define GPIO_SD2_IN_V  0xFF
-#define GPIO_SD2_IN_S  0
-
-#define GPIO_SIGMADELTA3_REG          (DR_REG_GPIO_SD_BASE + 0x000c)
-/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD3_PRESCALE  0x000000FF
-#define GPIO_SD3_PRESCALE_M  ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
-#define GPIO_SD3_PRESCALE_V  0xFF
-#define GPIO_SD3_PRESCALE_S  8
-/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD3_IN  0x000000FF
-#define GPIO_SD3_IN_M  ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
-#define GPIO_SD3_IN_V  0xFF
-#define GPIO_SD3_IN_S  0
-
-#define GPIO_SIGMADELTA4_REG          (DR_REG_GPIO_SD_BASE + 0x0010)
-/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD4_PRESCALE  0x000000FF
-#define GPIO_SD4_PRESCALE_M  ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
-#define GPIO_SD4_PRESCALE_V  0xFF
-#define GPIO_SD4_PRESCALE_S  8
-/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD4_IN  0x000000FF
-#define GPIO_SD4_IN_M  ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
-#define GPIO_SD4_IN_V  0xFF
-#define GPIO_SD4_IN_S  0
-
-#define GPIO_SIGMADELTA5_REG          (DR_REG_GPIO_SD_BASE + 0x0014)
-/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD5_PRESCALE  0x000000FF
-#define GPIO_SD5_PRESCALE_M  ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
-#define GPIO_SD5_PRESCALE_V  0xFF
-#define GPIO_SD5_PRESCALE_S  8
-/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD5_IN  0x000000FF
-#define GPIO_SD5_IN_M  ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
-#define GPIO_SD5_IN_V  0xFF
-#define GPIO_SD5_IN_S  0
-
-#define GPIO_SIGMADELTA6_REG          (DR_REG_GPIO_SD_BASE + 0x0018)
-/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD6_PRESCALE  0x000000FF
-#define GPIO_SD6_PRESCALE_M  ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
-#define GPIO_SD6_PRESCALE_V  0xFF
-#define GPIO_SD6_PRESCALE_S  8
-/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD6_IN  0x000000FF
-#define GPIO_SD6_IN_M  ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
-#define GPIO_SD6_IN_V  0xFF
-#define GPIO_SD6_IN_S  0
-
-#define GPIO_SIGMADELTA7_REG          (DR_REG_GPIO_SD_BASE + 0x001c)
-/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD7_PRESCALE  0x000000FF
-#define GPIO_SD7_PRESCALE_M  ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
-#define GPIO_SD7_PRESCALE_V  0xFF
-#define GPIO_SD7_PRESCALE_S  8
-/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD7_IN  0x000000FF
-#define GPIO_SD7_IN_M  ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
-#define GPIO_SD7_IN_V  0xFF
-#define GPIO_SD7_IN_S  0
-
-#define GPIO_SIGMADELTA_CG_REG          (DR_REG_GPIO_SD_BASE + 0x0020)
-/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SD_CLK_EN  (BIT(31))
-#define GPIO_SD_CLK_EN_M  (BIT(31))
-#define GPIO_SD_CLK_EN_V  0x1
-#define GPIO_SD_CLK_EN_S  31
-
-#define GPIO_SIGMADELTA_MISC_REG          (DR_REG_GPIO_SD_BASE + 0x0024)
-/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SPI_SWAP  (BIT(31))
-#define GPIO_SPI_SWAP_M  (BIT(31))
-#define GPIO_SPI_SWAP_V  0x1
-#define GPIO_SPI_SWAP_S  31
-
-#define GPIO_SIGMADELTA_VERSION_REG          (DR_REG_GPIO_SD_BASE + 0x0028)
-/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1506190 ; */
-/*description: */
-#define GPIO_SD_DATE  0x0FFFFFFF
-#define GPIO_SD_DATE_M  ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
-#define GPIO_SD_DATE_V  0xFFFFFFF
-#define GPIO_SD_DATE_S  0
-#define SIGMADELTA_GPIO_SD_DATE_VERSION 0x1506190
-
-
-
-
-#endif /*_SOC_GPIO_SD_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/gpio_sd_struct.h b/tools/sdk/include/soc/soc/gpio_sd_struct.h
deleted file mode 100644
index 4b82be052ca..00000000000
--- a/tools/sdk/include/soc/soc/gpio_sd_struct.h
+++ /dev/null
@@ -1,60 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_GPIO_SD_STRUCT_H_
-#define _SOC_GPIO_SD_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t duty:        8;
-            uint32_t prescale:    8;
-            uint32_t reserved16: 16;
-        };
-        uint32_t val;
-    } channel[8];
-    union {
-        struct {
-            uint32_t reserved0: 31;
-            uint32_t clk_en:     1;
-        };
-        uint32_t val;
-    } cg;
-    union {
-        struct {
-            uint32_t reserved0: 31;
-            uint32_t spi_swap:   1;
-        };
-        uint32_t val;
-    } misc;
-    union {
-        struct {
-            uint32_t date:      28;
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    } version;
-} gpio_sd_dev_t;
-extern gpio_sd_dev_t SIGMADELTA;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_GPIO_SD_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/gpio_sig_map.h b/tools/sdk/include/soc/soc/gpio_sig_map.h
deleted file mode 100644
index 1d3dc5b04ce..00000000000
--- a/tools/sdk/include/soc/soc/gpio_sig_map.h
+++ /dev/null
@@ -1,422 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_GPIO_SIG_MAP_H_
-#define _SOC_GPIO_SIG_MAP_H_
-
-#define SPICLK_IN_IDX			0
-#define SPICLK_OUT_IDX			0
-#define SPIQ_IN_IDX			1
-#define SPIQ_OUT_IDX			1
-#define SPID_IN_IDX			2
-#define SPID_OUT_IDX			2
-#define SPIHD_IN_IDX			3
-#define SPIHD_OUT_IDX			3
-#define SPIWP_IN_IDX			4
-#define SPIWP_OUT_IDX			4
-#define SPICS0_IN_IDX			5
-#define SPICS0_OUT_IDX			5
-#define SPICS1_IN_IDX			6
-#define SPICS1_OUT_IDX			6
-#define SPICS2_IN_IDX			7
-#define SPICS2_OUT_IDX			7
-#define HSPICLK_IN_IDX			8
-#define HSPICLK_OUT_IDX			8
-#define HSPIQ_IN_IDX			9
-#define HSPIQ_OUT_IDX			9
-#define HSPID_IN_IDX			10
-#define HSPID_OUT_IDX			10
-#define HSPICS0_IN_IDX			11
-#define HSPICS0_OUT_IDX			11
-#define HSPIHD_IN_IDX			12
-#define HSPIHD_OUT_IDX			12
-#define HSPIWP_IN_IDX			13
-#define HSPIWP_OUT_IDX			13
-#define U0RXD_IN_IDX			14
-#define U0TXD_OUT_IDX			14
-#define U0CTS_IN_IDX			15
-#define U0RTS_OUT_IDX			15
-#define U0DSR_IN_IDX			16
-#define U0DTR_OUT_IDX			16
-#define U1RXD_IN_IDX			17
-#define U1TXD_OUT_IDX			17
-#define U1CTS_IN_IDX			18
-#define U1RTS_OUT_IDX			18
-#define I2CM_SCL_O_IDX			19
-#define I2CM_SDA_I_IDX			20
-#define I2CM_SDA_O_IDX			20
-#define EXT_I2C_SCL_O_IDX			21
-#define EXT_I2C_SDA_O_IDX			22
-#define EXT_I2C_SDA_I_IDX			22
-#define I2S0O_BCK_IN_IDX			23
-#define I2S0O_BCK_OUT_IDX			23
-#define I2S1O_BCK_IN_IDX			24
-#define I2S1O_BCK_OUT_IDX			24
-#define I2S0O_WS_IN_IDX			25
-#define I2S0O_WS_OUT_IDX			25
-#define I2S1O_WS_IN_IDX			26
-#define I2S1O_WS_OUT_IDX			26
-#define I2S0I_BCK_IN_IDX			27
-#define I2S0I_BCK_OUT_IDX			27
-#define I2S0I_WS_IN_IDX			28
-#define I2S0I_WS_OUT_IDX			28
-#define I2CEXT0_SCL_IN_IDX			29
-#define I2CEXT0_SCL_OUT_IDX			29
-#define I2CEXT0_SDA_IN_IDX			30
-#define I2CEXT0_SDA_OUT_IDX			30
-#define PWM0_SYNC0_IN_IDX			31
-#define SDIO_TOHOST_INT_OUT_IDX			31
-#define PWM0_SYNC1_IN_IDX			32
-#define PWM0_OUT0A_IDX			32
-#define PWM0_SYNC2_IN_IDX			33
-#define PWM0_OUT0B_IDX			33
-#define PWM0_F0_IN_IDX			34
-#define PWM0_OUT1A_IDX			34
-#define PWM0_F1_IN_IDX			35
-#define PWM0_OUT1B_IDX			35
-#define PWM0_F2_IN_IDX			36
-#define PWM0_OUT2A_IDX			36
-#define GPIO_BT_ACTIVE_IDX			37
-#define PWM0_OUT2B_IDX			37
-#define GPIO_BT_PRIORITY_IDX			38
-#define PCNT_SIG_CH0_IN0_IDX			39
-#define PCNT_SIG_CH1_IN0_IDX			40
-#define GPIO_WLAN_ACTIVE_IDX			40
-#define PCNT_CTRL_CH0_IN0_IDX			41
-#define BB_DIAG0_IDX			41
-#define PCNT_CTRL_CH1_IN0_IDX			42
-#define BB_DIAG1_IDX			42
-#define PCNT_SIG_CH0_IN1_IDX			43
-#define BB_DIAG2_IDX			43
-#define PCNT_SIG_CH1_IN1_IDX			44
-#define BB_DIAG3_IDX			44
-#define PCNT_CTRL_CH0_IN1_IDX			45
-#define BB_DIAG4_IDX			45
-#define PCNT_CTRL_CH1_IN1_IDX			46
-#define BB_DIAG5_IDX			46
-#define PCNT_SIG_CH0_IN2_IDX			47
-#define BB_DIAG6_IDX			47
-#define PCNT_SIG_CH1_IN2_IDX			48
-#define BB_DIAG7_IDX			48
-#define PCNT_CTRL_CH0_IN2_IDX			49
-#define BB_DIAG8_IDX			49
-#define PCNT_CTRL_CH1_IN2_IDX			50
-#define BB_DIAG9_IDX			50
-#define PCNT_SIG_CH0_IN3_IDX			51
-#define BB_DIAG10_IDX			51
-#define PCNT_SIG_CH1_IN3_IDX			52
-#define BB_DIAG11_IDX			52
-#define PCNT_CTRL_CH0_IN3_IDX			53
-#define BB_DIAG12_IDX			53
-#define PCNT_CTRL_CH1_IN3_IDX			54
-#define BB_DIAG13_IDX			54
-#define PCNT_SIG_CH0_IN4_IDX			55
-#define BB_DIAG14_IDX			55
-#define PCNT_SIG_CH1_IN4_IDX			56
-#define BB_DIAG15_IDX			56
-#define PCNT_CTRL_CH0_IN4_IDX			57
-#define BB_DIAG16_IDX			57
-#define PCNT_CTRL_CH1_IN4_IDX			58
-#define BB_DIAG17_IDX			58
-#define BB_DIAG18_IDX			59
-#define BB_DIAG19_IDX			60
-#define HSPICS1_IN_IDX			61
-#define HSPICS1_OUT_IDX			61
-#define HSPICS2_IN_IDX			62
-#define HSPICS2_OUT_IDX			62
-#define VSPICLK_IN_IDX			63
-#define VSPICLK_OUT_IDX			63
-#define VSPIQ_IN_IDX			64
-#define VSPIQ_OUT_IDX			64
-#define VSPID_IN_IDX			65
-#define VSPID_OUT_IDX			65
-#define VSPIHD_IN_IDX			66
-#define VSPIHD_OUT_IDX			66
-#define VSPIWP_IN_IDX			67
-#define VSPIWP_OUT_IDX			67
-#define VSPICS0_IN_IDX			68
-#define VSPICS0_OUT_IDX			68
-#define VSPICS1_IN_IDX			69
-#define VSPICS1_OUT_IDX			69
-#define VSPICS2_IN_IDX			70
-#define VSPICS2_OUT_IDX			70
-#define PCNT_SIG_CH0_IN5_IDX			71
-#define LEDC_HS_SIG_OUT0_IDX			71
-#define PCNT_SIG_CH1_IN5_IDX			72
-#define LEDC_HS_SIG_OUT1_IDX			72
-#define PCNT_CTRL_CH0_IN5_IDX			73
-#define LEDC_HS_SIG_OUT2_IDX			73
-#define PCNT_CTRL_CH1_IN5_IDX			74
-#define LEDC_HS_SIG_OUT3_IDX			74
-#define PCNT_SIG_CH0_IN6_IDX			75
-#define LEDC_HS_SIG_OUT4_IDX			75
-#define PCNT_SIG_CH1_IN6_IDX			76
-#define LEDC_HS_SIG_OUT5_IDX			76
-#define PCNT_CTRL_CH0_IN6_IDX			77
-#define LEDC_HS_SIG_OUT6_IDX			77
-#define PCNT_CTRL_CH1_IN6_IDX			78
-#define LEDC_HS_SIG_OUT7_IDX			78
-#define PCNT_SIG_CH0_IN7_IDX			79
-#define LEDC_LS_SIG_OUT0_IDX			79
-#define PCNT_SIG_CH1_IN7_IDX			80
-#define LEDC_LS_SIG_OUT1_IDX			80
-#define PCNT_CTRL_CH0_IN7_IDX			81
-#define LEDC_LS_SIG_OUT2_IDX			81
-#define PCNT_CTRL_CH1_IN7_IDX			82
-#define LEDC_LS_SIG_OUT3_IDX			82
-#define RMT_SIG_IN0_IDX			83
-#define LEDC_LS_SIG_OUT4_IDX			83
-#define RMT_SIG_IN1_IDX			84
-#define LEDC_LS_SIG_OUT5_IDX			84
-#define RMT_SIG_IN2_IDX			85
-#define LEDC_LS_SIG_OUT6_IDX			85
-#define RMT_SIG_IN3_IDX			86
-#define LEDC_LS_SIG_OUT7_IDX			86
-#define RMT_SIG_IN4_IDX			87
-#define RMT_SIG_OUT0_IDX			87
-#define RMT_SIG_IN5_IDX			88
-#define RMT_SIG_OUT1_IDX			88
-#define RMT_SIG_IN6_IDX			89
-#define RMT_SIG_OUT2_IDX			89
-#define RMT_SIG_IN7_IDX			90
-#define RMT_SIG_OUT3_IDX			90
-#define RMT_SIG_OUT4_IDX			91
-#define RMT_SIG_OUT5_IDX			92
-#define EXT_ADC_START_IDX			93
-#define RMT_SIG_OUT6_IDX			93
-#define CAN_RX_IDX			94
-#define RMT_SIG_OUT7_IDX			94
-#define I2CEXT1_SCL_IN_IDX			95
-#define I2CEXT1_SCL_OUT_IDX			95
-#define I2CEXT1_SDA_IN_IDX			96
-#define I2CEXT1_SDA_OUT_IDX			96
-#define HOST_CARD_DETECT_N_1_IDX			97
-#define HOST_CCMD_OD_PULLUP_EN_N_IDX			97
-#define HOST_CARD_DETECT_N_2_IDX			98
-#define HOST_RST_N_1_IDX			98
-#define HOST_CARD_WRITE_PRT_1_IDX			99
-#define HOST_RST_N_2_IDX			99
-#define HOST_CARD_WRITE_PRT_2_IDX			100
-#define GPIO_SD0_OUT_IDX			100
-#define HOST_CARD_INT_N_1_IDX			101
-#define GPIO_SD1_OUT_IDX			101
-#define HOST_CARD_INT_N_2_IDX			102
-#define GPIO_SD2_OUT_IDX			102
-#define PWM1_SYNC0_IN_IDX			103
-#define GPIO_SD3_OUT_IDX			103
-#define PWM1_SYNC1_IN_IDX			104
-#define GPIO_SD4_OUT_IDX			104
-#define PWM1_SYNC2_IN_IDX			105
-#define GPIO_SD5_OUT_IDX			105
-#define PWM1_F0_IN_IDX			106
-#define GPIO_SD6_OUT_IDX			106
-#define PWM1_F1_IN_IDX			107
-#define GPIO_SD7_OUT_IDX			107
-#define PWM1_F2_IN_IDX			108
-#define PWM1_OUT0A_IDX			108
-#define PWM0_CAP0_IN_IDX			109
-#define PWM1_OUT0B_IDX			109
-#define PWM0_CAP1_IN_IDX			110
-#define PWM1_OUT1A_IDX			110
-#define PWM0_CAP2_IN_IDX			111
-#define PWM1_OUT1B_IDX			111
-#define PWM1_CAP0_IN_IDX			112
-#define PWM1_OUT2A_IDX			112
-#define PWM1_CAP1_IN_IDX			113
-#define PWM1_OUT2B_IDX			113
-#define PWM1_CAP2_IN_IDX			114
-#define PWM2_OUT1H_IDX			114
-#define PWM2_FLTA_IDX			115
-#define PWM2_OUT1L_IDX			115
-#define PWM2_FLTB_IDX			116
-#define PWM2_OUT2H_IDX			116
-#define PWM2_CAP1_IN_IDX			117
-#define PWM2_OUT2L_IDX			117
-#define PWM2_CAP2_IN_IDX			118
-#define PWM2_OUT3H_IDX			118
-#define PWM2_CAP3_IN_IDX			119
-#define PWM2_OUT3L_IDX			119
-#define PWM3_FLTA_IDX			120
-#define PWM2_OUT4H_IDX			120
-#define PWM3_FLTB_IDX			121
-#define PWM2_OUT4L_IDX			121
-#define PWM3_CAP1_IN_IDX			122
-#define PWM3_CAP2_IN_IDX			123
-#define CAN_TX_IDX			123
-#define PWM3_CAP3_IN_IDX			124
-#define CAN_BUS_OFF_ON_IDX			124
-#define CAN_CLKOUT_IDX			125
-#define SPID4_IN_IDX			128
-#define SPID4_OUT_IDX			128
-#define SPID5_IN_IDX			129
-#define SPID5_OUT_IDX			129
-#define SPID6_IN_IDX			130
-#define SPID6_OUT_IDX			130
-#define SPID7_IN_IDX			131
-#define SPID7_OUT_IDX			131
-#define HSPID4_IN_IDX			132
-#define HSPID4_OUT_IDX			132
-#define HSPID5_IN_IDX			133
-#define HSPID5_OUT_IDX			133
-#define HSPID6_IN_IDX			134
-#define HSPID6_OUT_IDX			134
-#define HSPID7_IN_IDX			135
-#define HSPID7_OUT_IDX			135
-#define VSPID4_IN_IDX			136
-#define VSPID4_OUT_IDX			136
-#define VSPID5_IN_IDX			137
-#define VSPID5_OUT_IDX			137
-#define VSPID6_IN_IDX			138
-#define VSPID6_OUT_IDX			138
-#define VSPID7_IN_IDX			139
-#define VSPID7_OUT_IDX			139
-#define I2S0I_DATA_IN0_IDX			140
-#define I2S0O_DATA_OUT0_IDX			140
-#define I2S0I_DATA_IN1_IDX			141
-#define I2S0O_DATA_OUT1_IDX			141
-#define I2S0I_DATA_IN2_IDX			142
-#define I2S0O_DATA_OUT2_IDX			142
-#define I2S0I_DATA_IN3_IDX			143
-#define I2S0O_DATA_OUT3_IDX			143
-#define I2S0I_DATA_IN4_IDX			144
-#define I2S0O_DATA_OUT4_IDX			144
-#define I2S0I_DATA_IN5_IDX			145
-#define I2S0O_DATA_OUT5_IDX			145
-#define I2S0I_DATA_IN6_IDX			146
-#define I2S0O_DATA_OUT6_IDX			146
-#define I2S0I_DATA_IN7_IDX			147
-#define I2S0O_DATA_OUT7_IDX			147
-#define I2S0I_DATA_IN8_IDX			148
-#define I2S0O_DATA_OUT8_IDX			148
-#define I2S0I_DATA_IN9_IDX			149
-#define I2S0O_DATA_OUT9_IDX			149
-#define I2S0I_DATA_IN10_IDX			150
-#define I2S0O_DATA_OUT10_IDX			150
-#define I2S0I_DATA_IN11_IDX			151
-#define I2S0O_DATA_OUT11_IDX			151
-#define I2S0I_DATA_IN12_IDX			152
-#define I2S0O_DATA_OUT12_IDX			152
-#define I2S0I_DATA_IN13_IDX			153
-#define I2S0O_DATA_OUT13_IDX			153
-#define I2S0I_DATA_IN14_IDX			154
-#define I2S0O_DATA_OUT14_IDX			154
-#define I2S0I_DATA_IN15_IDX			155
-#define I2S0O_DATA_OUT15_IDX			155
-#define I2S0O_DATA_OUT16_IDX			156
-#define I2S0O_DATA_OUT17_IDX			157
-#define I2S0O_DATA_OUT18_IDX			158
-#define I2S0O_DATA_OUT19_IDX			159
-#define I2S0O_DATA_OUT20_IDX			160
-#define I2S0O_DATA_OUT21_IDX			161
-#define I2S0O_DATA_OUT22_IDX			162
-#define I2S0O_DATA_OUT23_IDX			163
-#define I2S1I_BCK_IN_IDX			164
-#define I2S1I_BCK_OUT_IDX			164
-#define I2S1I_WS_IN_IDX			165
-#define I2S1I_WS_OUT_IDX			165
-#define I2S1I_DATA_IN0_IDX			166
-#define I2S1O_DATA_OUT0_IDX			166
-#define I2S1I_DATA_IN1_IDX			167
-#define I2S1O_DATA_OUT1_IDX			167
-#define I2S1I_DATA_IN2_IDX			168
-#define I2S1O_DATA_OUT2_IDX			168
-#define I2S1I_DATA_IN3_IDX			169
-#define I2S1O_DATA_OUT3_IDX			169
-#define I2S1I_DATA_IN4_IDX			170
-#define I2S1O_DATA_OUT4_IDX			170
-#define I2S1I_DATA_IN5_IDX			171
-#define I2S1O_DATA_OUT5_IDX			171
-#define I2S1I_DATA_IN6_IDX			172
-#define I2S1O_DATA_OUT6_IDX			172
-#define I2S1I_DATA_IN7_IDX			173
-#define I2S1O_DATA_OUT7_IDX			173
-#define I2S1I_DATA_IN8_IDX			174
-#define I2S1O_DATA_OUT8_IDX			174
-#define I2S1I_DATA_IN9_IDX			175
-#define I2S1O_DATA_OUT9_IDX			175
-#define I2S1I_DATA_IN10_IDX			176
-#define I2S1O_DATA_OUT10_IDX			176
-#define I2S1I_DATA_IN11_IDX			177
-#define I2S1O_DATA_OUT11_IDX			177
-#define I2S1I_DATA_IN12_IDX			178
-#define I2S1O_DATA_OUT12_IDX			178
-#define I2S1I_DATA_IN13_IDX			179
-#define I2S1O_DATA_OUT13_IDX			179
-#define I2S1I_DATA_IN14_IDX			180
-#define I2S1O_DATA_OUT14_IDX			180
-#define I2S1I_DATA_IN15_IDX			181
-#define I2S1O_DATA_OUT15_IDX			181
-#define I2S1O_DATA_OUT16_IDX			182
-#define I2S1O_DATA_OUT17_IDX			183
-#define I2S1O_DATA_OUT18_IDX			184
-#define I2S1O_DATA_OUT19_IDX			185
-#define I2S1O_DATA_OUT20_IDX			186
-#define I2S1O_DATA_OUT21_IDX			187
-#define I2S1O_DATA_OUT22_IDX			188
-#define I2S1O_DATA_OUT23_IDX			189
-#define I2S0I_H_SYNC_IDX			190
-#define PWM3_OUT1H_IDX			190
-#define I2S0I_V_SYNC_IDX			191
-#define PWM3_OUT1L_IDX			191
-#define I2S0I_H_ENABLE_IDX			192
-#define PWM3_OUT2H_IDX			192
-#define I2S1I_H_SYNC_IDX			193
-#define PWM3_OUT2L_IDX			193
-#define I2S1I_V_SYNC_IDX			194
-#define PWM3_OUT3H_IDX			194
-#define I2S1I_H_ENABLE_IDX			195
-#define PWM3_OUT3L_IDX			195
-#define PWM3_OUT4H_IDX			196
-#define PWM3_OUT4L_IDX			197
-#define U2RXD_IN_IDX			198
-#define U2TXD_OUT_IDX			198
-#define U2CTS_IN_IDX			199
-#define U2RTS_OUT_IDX			199
-#define EMAC_MDC_I_IDX			200
-#define EMAC_MDC_O_IDX			200
-#define EMAC_MDI_I_IDX			201
-#define EMAC_MDO_O_IDX			201
-#define EMAC_CRS_I_IDX			202
-#define EMAC_CRS_O_IDX			202
-#define EMAC_COL_I_IDX			203
-#define EMAC_COL_O_IDX			203
-#define PCMFSYNC_IN_IDX			204
-#define BT_AUDIO0_IRQ_IDX			204
-#define PCMCLK_IN_IDX			205
-#define BT_AUDIO1_IRQ_IDX			205
-#define PCMDIN_IDX			206
-#define BT_AUDIO2_IRQ_IDX			206
-#define BLE_AUDIO0_IRQ_IDX			207
-#define BLE_AUDIO1_IRQ_IDX			208
-#define BLE_AUDIO2_IRQ_IDX			209
-#define PCMFSYNC_OUT_IDX			210
-#define PCMCLK_OUT_IDX			211
-#define PCMDOUT_IDX			212
-#define BLE_AUDIO_SYNC0_P_IDX			213
-#define BLE_AUDIO_SYNC1_P_IDX			214
-#define BLE_AUDIO_SYNC2_P_IDX			215
-#define ANT_SEL0_IDX			216
-#define ANT_SEL1_IDX			217
-#define ANT_SEL2_IDX			218
-#define ANT_SEL3_IDX			219
-#define ANT_SEL4_IDX			220
-#define ANT_SEL5_IDX			221
-#define ANT_SEL6_IDX			222
-#define ANT_SEL7_IDX			223
-#define SIG_IN_FUNC224_IDX			224
-#define SIG_IN_FUNC225_IDX			225
-#define SIG_IN_FUNC226_IDX			226
-#define SIG_IN_FUNC227_IDX			227
-#define SIG_IN_FUNC228_IDX			228
-#define SIG_GPIO_OUT_IDX            256
-#endif /* _SOC_GPIO_SIG_MAP_H_ */
diff --git a/tools/sdk/include/soc/soc/gpio_struct.h b/tools/sdk/include/soc/soc/gpio_struct.h
deleted file mode 100644
index 15038fed3ff..00000000000
--- a/tools/sdk/include/soc/soc/gpio_struct.h
+++ /dev/null
@@ -1,216 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_GPIO_STRUCT_H_
-#define _SOC_GPIO_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    uint32_t bt_select;                             /*NA*/
-    uint32_t out;                                   /*GPIO0~31 output value*/
-    uint32_t out_w1ts;                              /*GPIO0~31 output value write 1 to set*/
-    uint32_t out_w1tc;                              /*GPIO0~31 output value write 1 to clear*/
-    union {
-        struct {
-            uint32_t data:       8;                 /*GPIO32~39 output value*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } out1;
-    union {
-        struct {
-            uint32_t data:       8;                 /*GPIO32~39 output value write 1 to set*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } out1_w1ts;
-    union {
-        struct {
-            uint32_t data:       8;                 /*GPIO32~39 output value write 1 to clear*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } out1_w1tc;
-    union {
-        struct {
-            uint32_t sel:        8;                 /*SDIO PADS on/off control from outside*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } sdio_select;
-    uint32_t enable;                                /*GPIO0~31 output enable*/
-    uint32_t enable_w1ts;                           /*GPIO0~31 output enable write 1 to set*/
-    uint32_t enable_w1tc;                           /*GPIO0~31 output enable write 1 to clear*/
-    union {
-        struct {
-            uint32_t data:        8;                /*GPIO32~39 output enable*/
-            uint32_t reserved8:  24;
-        };
-        uint32_t val;
-    } enable1;
-    union {
-        struct {
-            uint32_t data:        8;                /*GPIO32~39 output enable write 1 to set*/
-            uint32_t reserved8:  24;
-        };
-        uint32_t val;
-    } enable1_w1ts;
-    union {
-        struct {
-            uint32_t data:        8;                /*GPIO32~39 output enable write 1 to clear*/
-            uint32_t reserved8:  24;
-        };
-        uint32_t val;
-    } enable1_w1tc;
-    union {
-        struct {
-            uint32_t strapping: 16;                 /*GPIO strapping results: {2'd0  boot_sel_dig[7:1]  vsdio_boot_sel  boot_sel_chip[5:0]} .   Boot_sel_dig[7:1]: {U0RXD  SD_CLK  SD_CMD  SD_DATA0  SD_DATA1  SD_DATA2  SD_DATA3} .  vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0  U0TXD  GPIO2  GPIO4  MTDO  GPIO5} */
-            uint32_t reserved16:16;
-        };
-        uint32_t val;
-    } strap;
-    uint32_t in;                                    /*GPIO0~31 input value*/
-    union {
-        struct {
-            uint32_t data:       8;                 /*GPIO32~39 input value*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } in1;
-    uint32_t status;                                /*GPIO0~31 interrupt status*/
-    uint32_t status_w1ts;                           /*GPIO0~31 interrupt status write 1 to set*/
-    uint32_t status_w1tc;                           /*GPIO0~31 interrupt status write 1 to clear*/
-    union {
-        struct {
-            uint32_t intr_st:    8;                 /*GPIO32~39 interrupt status*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } status1;
-    union {
-        struct {
-            uint32_t intr_st:    8;                 /*GPIO32~39 interrupt status write 1 to set*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } status1_w1ts;
-    union {
-        struct {
-            uint32_t intr_st:    8;                 /*GPIO32~39 interrupt status write 1 to clear*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } status1_w1tc;
-    uint32_t reserved_5c;
-    uint32_t acpu_int;                              /*GPIO0~31 APP CPU interrupt status*/
-    uint32_t acpu_nmi_int;                          /*GPIO0~31 APP CPU non-maskable interrupt status*/
-    uint32_t pcpu_int;                              /*GPIO0~31 PRO CPU interrupt status*/
-    uint32_t pcpu_nmi_int;                          /*GPIO0~31 PRO CPU non-maskable interrupt status*/
-    uint32_t cpusdio_int;                           /*SDIO's extent GPIO0~31 interrupt*/
-    union {
-        struct {
-            uint32_t intr:       8;                 /*GPIO32~39 APP CPU interrupt status*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } acpu_int1;
-    union {
-        struct {
-            uint32_t intr:       8;                 /*GPIO32~39 APP CPU non-maskable interrupt status*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } acpu_nmi_int1;
-    union {
-        struct {
-            uint32_t intr:       8;                 /*GPIO32~39 PRO CPU interrupt status*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } pcpu_int1;
-    union {
-        struct {
-            uint32_t intr:       8;                 /*GPIO32~39 PRO CPU non-maskable interrupt status*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } pcpu_nmi_int1;
-    union {
-        struct {
-            uint32_t intr:       8;                 /*SDIO's extent GPIO32~39 interrupt*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } cpusdio_int1;
-    union {
-        struct {
-            uint32_t reserved0:     2;
-            uint32_t pad_driver:    1;              /*if set to 0: normal output  if set to 1: open drain*/
-            uint32_t reserved3:     4;
-            uint32_t int_type:      3;              /*if set to 0: GPIO interrupt disable  if set to 1: rising edge trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-            uint32_t wakeup_enable: 1;              /*GPIO wake up enable  only available in light sleep*/
-            uint32_t config:        2;              /*NA*/
-            uint32_t int_ena:       5;              /*bit0: APP CPU interrupt enable  bit1: APP CPU non-maskable interrupt enable  bit3: PRO CPU interrupt enable  bit4:  PRO CPU non-maskable interrupt enable  bit5: SDIO's extent interrupt enable*/
-            uint32_t reserved18:   14;
-        };
-        uint32_t val;
-    } pin[40];
-    union {
-        struct {
-            uint32_t rtc_max:     10;
-            uint32_t reserved10:  21;
-            uint32_t start:        1;
-        };
-        uint32_t val;
-    } cali_conf;
-    union {
-        struct {
-            uint32_t value_sync2: 20;
-            uint32_t reserved20:  10;
-            uint32_t rdy_real:     1;
-            uint32_t rdy_sync2:    1;
-        };
-        uint32_t val;
-    } cali_data;
-    union {
-        struct {
-            uint32_t func_sel:    6;                /*select one of the 256 inputs*/
-            uint32_t sig_in_inv:  1;                /*revert the value of the input if you want to revert  please set the value to 1*/
-            uint32_t sig_in_sel:  1;                /*if the slow signal bypass the io matrix or not if you want  setting the value to 1*/
-            uint32_t reserved8:  24;                /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input  if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x  if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1   if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/
-        };
-        uint32_t val;
-    } func_in_sel_cfg[256];
-    union {
-        struct {
-            uint32_t func_sel:     9;               /*select one of the 256 output to 40 GPIO*/
-            uint32_t inv_sel:      1;               /*invert the output value  if you want to revert the output value  setting the value to 1*/
-            uint32_t oen_sel:      1;               /*weather using the logical oen signal or not using the value setting by the register*/
-            uint32_t oen_inv_sel:  1;               /*invert the output enable value  if you want to revert the output enable value  setting the value to 1*/
-            uint32_t reserved12:  20;               /*The 40 registers below are selection control for 40 GPIO output  if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x  if GPIO_FUNCx_OUT_INV_SEL is set to 1  the output signal x is set to ~value.  if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/
-        };
-        uint32_t val;
-    } func_out_sel_cfg[40];
-} gpio_dev_t;
-extern gpio_dev_t GPIO;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_GPIO_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/hinf_reg.h b/tools/sdk/include/soc/soc/hinf_reg.h
deleted file mode 100644
index aad357864eb..00000000000
--- a/tools/sdk/include/soc/soc/hinf_reg.h
+++ /dev/null
@@ -1,248 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_HINF_REG_H_
-#define _SOC_HINF_REG_H_
-
-
-#include "soc.h"
-#define HINF_CFG_DATA0_REG          (DR_REG_HINF_BASE + 0x0)
-/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
-/*description: */
-#define HINF_DEVICE_ID_FN1  0x0000FFFF
-#define HINF_DEVICE_ID_FN1_M  ((HINF_DEVICE_ID_FN1_V)<<(HINF_DEVICE_ID_FN1_S))
-#define HINF_DEVICE_ID_FN1_V  0xFFFF
-#define HINF_DEVICE_ID_FN1_S  16
-/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
-/*description: */
-#define HINF_USER_ID_FN1  0x0000FFFF
-#define HINF_USER_ID_FN1_M  ((HINF_USER_ID_FN1_V)<<(HINF_USER_ID_FN1_S))
-#define HINF_USER_ID_FN1_V  0xFFFF
-#define HINF_USER_ID_FN1_S  0
-
-#define HINF_CFG_DATA1_REG          (DR_REG_HINF_BASE + 0x4)
-/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */
-/*description: */
-#define HINF_SDIO20_CONF1  0x00000007
-#define HINF_SDIO20_CONF1_M  ((HINF_SDIO20_CONF1_V)<<(HINF_SDIO20_CONF1_S))
-#define HINF_SDIO20_CONF1_V  0x7
-#define HINF_SDIO20_CONF1_S  29
-/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define HINF_FUNC2_EPS  (BIT(28))
-#define HINF_FUNC2_EPS_M  (BIT(28))
-#define HINF_FUNC2_EPS_V  0x1
-#define HINF_FUNC2_EPS_S  28
-/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */
-/*description: */
-#define HINF_SDIO_VER  0x00000FFF
-#define HINF_SDIO_VER_M  ((HINF_SDIO_VER_V)<<(HINF_SDIO_VER_S))
-#define HINF_SDIO_VER_V  0xFFF
-#define HINF_SDIO_VER_S  16
-/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
-/*description: */
-#define HINF_SDIO20_CONF0  0x0000000F
-#define HINF_SDIO20_CONF0_M  ((HINF_SDIO20_CONF0_V)<<(HINF_SDIO20_CONF0_S))
-#define HINF_SDIO20_CONF0_V  0xF
-#define HINF_SDIO20_CONF0_S  12
-/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HINF_IOENABLE1  (BIT(11))
-#define HINF_IOENABLE1_M  (BIT(11))
-#define HINF_IOENABLE1_V  0x1
-#define HINF_IOENABLE1_S  11
-/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HINF_EMP  (BIT(10))
-#define HINF_EMP_M  (BIT(10))
-#define HINF_EMP_V  0x1
-#define HINF_EMP_S  10
-/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HINF_FUNC1_EPS  (BIT(9))
-#define HINF_FUNC1_EPS_M  (BIT(9))
-#define HINF_FUNC1_EPS_V  0x1
-#define HINF_FUNC1_EPS_S  9
-/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HINF_CD_DISABLE  (BIT(8))
-#define HINF_CD_DISABLE_M  (BIT(8))
-#define HINF_CD_DISABLE_V  0x1
-#define HINF_CD_DISABLE_S  8
-/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HINF_IOENABLE2  (BIT(7))
-#define HINF_IOENABLE2_M  (BIT(7))
-#define HINF_IOENABLE2_V  0x1
-#define HINF_IOENABLE2_S  7
-/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HINF_SDIO_INT_MASK  (BIT(6))
-#define HINF_SDIO_INT_MASK_M  (BIT(6))
-#define HINF_SDIO_INT_MASK_V  0x1
-#define HINF_SDIO_INT_MASK_S  6
-/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HINF_SDIO_IOREADY2  (BIT(5))
-#define HINF_SDIO_IOREADY2_M  (BIT(5))
-#define HINF_SDIO_IOREADY2_V  0x1
-#define HINF_SDIO_IOREADY2_S  5
-/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define HINF_SDIO_CD_ENABLE  (BIT(4))
-#define HINF_SDIO_CD_ENABLE_M  (BIT(4))
-#define HINF_SDIO_CD_ENABLE_V  0x1
-#define HINF_SDIO_CD_ENABLE_S  4
-/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HINF_HIGHSPEED_MODE  (BIT(3))
-#define HINF_HIGHSPEED_MODE_M  (BIT(3))
-#define HINF_HIGHSPEED_MODE_V  0x1
-#define HINF_HIGHSPEED_MODE_S  3
-/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HINF_HIGHSPEED_ENABLE  (BIT(2))
-#define HINF_HIGHSPEED_ENABLE_M  (BIT(2))
-#define HINF_HIGHSPEED_ENABLE_V  0x1
-#define HINF_HIGHSPEED_ENABLE_S  2
-/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HINF_SDIO_IOREADY1  (BIT(1))
-#define HINF_SDIO_IOREADY1_M  (BIT(1))
-#define HINF_SDIO_IOREADY1_V  0x1
-#define HINF_SDIO_IOREADY1_S  1
-/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define HINF_SDIO_ENABLE  (BIT(0))
-#define HINF_SDIO_ENABLE_M  (BIT(0))
-#define HINF_SDIO_ENABLE_V  0x1
-#define HINF_SDIO_ENABLE_S  0
-
-#define HINF_CFG_DATA7_REG          (DR_REG_HINF_BASE + 0x1C)
-/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */
-/*description: */
-#define HINF_SDIO_IOREADY0  (BIT(17))
-#define HINF_SDIO_IOREADY0_M  (BIT(17))
-#define HINF_SDIO_IOREADY0_V  0x1
-#define HINF_SDIO_IOREADY0_S  17
-/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HINF_SDIO_RST  (BIT(16))
-#define HINF_SDIO_RST_M  (BIT(16))
-#define HINF_SDIO_RST_V  0x1
-#define HINF_SDIO_RST_S  16
-/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
-/*description: */
-#define HINF_CHIP_STATE  0x000000FF
-#define HINF_CHIP_STATE_M  ((HINF_CHIP_STATE_V)<<(HINF_CHIP_STATE_S))
-#define HINF_CHIP_STATE_V  0xFF
-#define HINF_CHIP_STATE_S  8
-/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define HINF_PIN_STATE  0x000000FF
-#define HINF_PIN_STATE_M  ((HINF_PIN_STATE_V)<<(HINF_PIN_STATE_S))
-#define HINF_PIN_STATE_V  0xFF
-#define HINF_PIN_STATE_S  0
-
-#define HINF_CIS_CONF0_REG          (DR_REG_HINF_BASE + 0x20)
-/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define HINF_CIS_CONF_W0  0xFFFFFFFF
-#define HINF_CIS_CONF_W0_M  ((HINF_CIS_CONF_W0_V)<<(HINF_CIS_CONF_W0_S))
-#define HINF_CIS_CONF_W0_V  0xFFFFFFFF
-#define HINF_CIS_CONF_W0_S  0
-
-#define HINF_CIS_CONF1_REG          (DR_REG_HINF_BASE + 0x24)
-/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define HINF_CIS_CONF_W1  0xFFFFFFFF
-#define HINF_CIS_CONF_W1_M  ((HINF_CIS_CONF_W1_V)<<(HINF_CIS_CONF_W1_S))
-#define HINF_CIS_CONF_W1_V  0xFFFFFFFF
-#define HINF_CIS_CONF_W1_S  0
-
-#define HINF_CIS_CONF2_REG          (DR_REG_HINF_BASE + 0x28)
-/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define HINF_CIS_CONF_W2  0xFFFFFFFF
-#define HINF_CIS_CONF_W2_M  ((HINF_CIS_CONF_W2_V)<<(HINF_CIS_CONF_W2_S))
-#define HINF_CIS_CONF_W2_V  0xFFFFFFFF
-#define HINF_CIS_CONF_W2_S  0
-
-#define HINF_CIS_CONF3_REG          (DR_REG_HINF_BASE + 0x2C)
-/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define HINF_CIS_CONF_W3  0xFFFFFFFF
-#define HINF_CIS_CONF_W3_M  ((HINF_CIS_CONF_W3_V)<<(HINF_CIS_CONF_W3_S))
-#define HINF_CIS_CONF_W3_V  0xFFFFFFFF
-#define HINF_CIS_CONF_W3_S  0
-
-#define HINF_CIS_CONF4_REG          (DR_REG_HINF_BASE + 0x30)
-/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define HINF_CIS_CONF_W4  0xFFFFFFFF
-#define HINF_CIS_CONF_W4_M  ((HINF_CIS_CONF_W4_V)<<(HINF_CIS_CONF_W4_S))
-#define HINF_CIS_CONF_W4_V  0xFFFFFFFF
-#define HINF_CIS_CONF_W4_S  0
-
-#define HINF_CIS_CONF5_REG          (DR_REG_HINF_BASE + 0x34)
-/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define HINF_CIS_CONF_W5  0xFFFFFFFF
-#define HINF_CIS_CONF_W5_M  ((HINF_CIS_CONF_W5_V)<<(HINF_CIS_CONF_W5_S))
-#define HINF_CIS_CONF_W5_V  0xFFFFFFFF
-#define HINF_CIS_CONF_W5_S  0
-
-#define HINF_CIS_CONF6_REG          (DR_REG_HINF_BASE + 0x38)
-/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define HINF_CIS_CONF_W6  0xFFFFFFFF
-#define HINF_CIS_CONF_W6_M  ((HINF_CIS_CONF_W6_V)<<(HINF_CIS_CONF_W6_S))
-#define HINF_CIS_CONF_W6_V  0xFFFFFFFF
-#define HINF_CIS_CONF_W6_S  0
-
-#define HINF_CIS_CONF7_REG          (DR_REG_HINF_BASE + 0x3C)
-/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: */
-#define HINF_CIS_CONF_W7  0xFFFFFFFF
-#define HINF_CIS_CONF_W7_M  ((HINF_CIS_CONF_W7_V)<<(HINF_CIS_CONF_W7_S))
-#define HINF_CIS_CONF_W7_V  0xFFFFFFFF
-#define HINF_CIS_CONF_W7_S  0
-
-#define HINF_CFG_DATA16_REG          (DR_REG_HINF_BASE + 0x40)
-/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */
-/*description: */
-#define HINF_DEVICE_ID_FN2  0x0000FFFF
-#define HINF_DEVICE_ID_FN2_M  ((HINF_DEVICE_ID_FN2_V)<<(HINF_DEVICE_ID_FN2_S))
-#define HINF_DEVICE_ID_FN2_V  0xFFFF
-#define HINF_DEVICE_ID_FN2_S  16
-/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
-/*description: */
-#define HINF_USER_ID_FN2  0x0000FFFF
-#define HINF_USER_ID_FN2_M  ((HINF_USER_ID_FN2_V)<<(HINF_USER_ID_FN2_S))
-#define HINF_USER_ID_FN2_V  0xFFFF
-#define HINF_USER_ID_FN2_S  0
-
-#define HINF_DATE_REG          (DR_REG_HINF_BASE + 0xFC)
-/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */
-/*description: */
-#define HINF_SDIO_DATE  0xFFFFFFFF
-#define HINF_SDIO_DATE_M  ((HINF_SDIO_DATE_V)<<(HINF_SDIO_DATE_S))
-#define HINF_SDIO_DATE_V  0xFFFFFFFF
-#define HINF_SDIO_DATE_S  0
-
-
-
-
-#endif /*_SOC_HINF_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/hinf_struct.h b/tools/sdk/include/soc/soc/hinf_struct.h
deleted file mode 100644
index 8e46f5397d0..00000000000
--- a/tools/sdk/include/soc/soc/hinf_struct.h
+++ /dev/null
@@ -1,136 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_HINF_STRUCT_H_
-#define _SOC_HINF_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t user_id_fn1:  16;
-            uint32_t device_id_fn1:16;
-        };
-        uint32_t val;
-    } cfg_data0;
-    union {
-        struct {
-            uint32_t sdio_enable:      1;
-            uint32_t sdio_ioready1:    1;
-            uint32_t highspeed_enable: 1;
-            uint32_t highspeed_mode:   1;
-            uint32_t sdio_cd_enable:   1;
-            uint32_t sdio_ioready2:    1;
-            uint32_t sdio_int_mask:    1;
-            uint32_t ioenable2:        1;
-            uint32_t cd_disable:       1;
-            uint32_t func1_eps:        1;
-            uint32_t emp:              1;
-            uint32_t ioenable1:        1;
-            uint32_t sdio20_conf0:     4;
-            uint32_t sdio_ver:        12;
-            uint32_t func2_eps:        1;
-            uint32_t sdio20_conf1:     3;
-        };
-        uint32_t val;
-    } cfg_data1;
-    uint32_t reserved_8;
-    uint32_t reserved_c;
-    uint32_t reserved_10;
-    uint32_t reserved_14;
-    uint32_t reserved_18;
-    union {
-        struct {
-            uint32_t pin_state:     8;
-            uint32_t chip_state:    8;
-            uint32_t sdio_rst:      1;
-            uint32_t sdio_ioready0: 1;
-            uint32_t reserved18:   14;
-        };
-        uint32_t val;
-    } cfg_data7;
-    uint32_t cis_conf0;                     /**/
-    uint32_t cis_conf1;                     /**/
-    uint32_t cis_conf2;                     /**/
-    uint32_t cis_conf3;                     /**/
-    uint32_t cis_conf4;                     /**/
-    uint32_t cis_conf5;                     /**/
-    uint32_t cis_conf6;                     /**/
-    uint32_t cis_conf7;                     /**/
-    union {
-        struct {
-            uint32_t user_id_fn2:  16;
-            uint32_t device_id_fn2:16;
-        };
-        uint32_t val;
-    } cfg_data16;
-    uint32_t reserved_44;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t date;                          /**/
-} hinf_dev_t;
-extern hinf_dev_t HINF;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_HINF_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/host_reg.h b/tools/sdk/include/soc/soc/host_reg.h
deleted file mode 100644
index ef556e21cdc..00000000000
--- a/tools/sdk/include/soc/soc/host_reg.h
+++ /dev/null
@@ -1,3144 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_HOST_REG_H_
-#define _SOC_HOST_REG_H_
-
-
-#include "soc.h"
-#define HOST_SLCHOST_FUNC2_0_REG          (DR_REG_SLCHOST_BASE + 0x10)
-/* HOST_SLC_FUNC2_INT : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC_FUNC2_INT  (BIT(24))
-#define HOST_SLC_FUNC2_INT_M  (BIT(24))
-#define HOST_SLC_FUNC2_INT_V  0x1
-#define HOST_SLC_FUNC2_INT_S  24
-
-#define HOST_SLCHOST_FUNC2_1_REG          (DR_REG_SLCHOST_BASE + 0x14)
-/* HOST_SLC_FUNC2_INT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC_FUNC2_INT_EN  (BIT(0))
-#define HOST_SLC_FUNC2_INT_EN_M  (BIT(0))
-#define HOST_SLC_FUNC2_INT_EN_V  0x1
-#define HOST_SLC_FUNC2_INT_EN_S  0
-
-#define HOST_SLCHOST_FUNC2_2_REG          (DR_REG_SLCHOST_BASE + 0x20)
-/* HOST_SLC_FUNC1_MDSTAT : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define HOST_SLC_FUNC1_MDSTAT  (BIT(0))
-#define HOST_SLC_FUNC1_MDSTAT_M  (BIT(0))
-#define HOST_SLC_FUNC1_MDSTAT_V  0x1
-#define HOST_SLC_FUNC1_MDSTAT_S  0
-
-#define HOST_SLCHOST_GPIO_STATUS0_REG          (DR_REG_SLCHOST_BASE + 0x34)
-/* HOST_GPIO_SDIO_INT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT0  0xFFFFFFFF
-#define HOST_GPIO_SDIO_INT0_M  ((HOST_GPIO_SDIO_INT0_V)<<(HOST_GPIO_SDIO_INT0_S))
-#define HOST_GPIO_SDIO_INT0_V  0xFFFFFFFF
-#define HOST_GPIO_SDIO_INT0_S  0
-
-#define HOST_SLCHOST_GPIO_STATUS1_REG          (DR_REG_SLCHOST_BASE + 0x38)
-/* HOST_GPIO_SDIO_INT1 : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT1  0x000000FF
-#define HOST_GPIO_SDIO_INT1_M  ((HOST_GPIO_SDIO_INT1_V)<<(HOST_GPIO_SDIO_INT1_S))
-#define HOST_GPIO_SDIO_INT1_V  0xFF
-#define HOST_GPIO_SDIO_INT1_S  0
-
-#define HOST_SLCHOST_GPIO_IN0_REG          (DR_REG_SLCHOST_BASE + 0x3C)
-/* HOST_GPIO_SDIO_IN0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_IN0  0xFFFFFFFF
-#define HOST_GPIO_SDIO_IN0_M  ((HOST_GPIO_SDIO_IN0_V)<<(HOST_GPIO_SDIO_IN0_S))
-#define HOST_GPIO_SDIO_IN0_V  0xFFFFFFFF
-#define HOST_GPIO_SDIO_IN0_S  0
-
-#define HOST_SLCHOST_GPIO_IN1_REG          (DR_REG_SLCHOST_BASE + 0x40)
-/* HOST_GPIO_SDIO_IN1 : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_IN1  0x000000FF
-#define HOST_GPIO_SDIO_IN1_M  ((HOST_GPIO_SDIO_IN1_V)<<(HOST_GPIO_SDIO_IN1_S))
-#define HOST_GPIO_SDIO_IN1_V  0xFF
-#define HOST_GPIO_SDIO_IN1_S  0
-
-#define HOST_SLC0HOST_TOKEN_RDATA_REG          (DR_REG_SLCHOST_BASE + 0x44)
-/* HOST_SLC0_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_EOF  0x0000000F
-#define HOST_SLC0_RX_PF_EOF_M  ((HOST_SLC0_RX_PF_EOF_V)<<(HOST_SLC0_RX_PF_EOF_S))
-#define HOST_SLC0_RX_PF_EOF_V  0xF
-#define HOST_SLC0_RX_PF_EOF_S  28
-/* HOST_HOSTSLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_TOKEN1  0x00000FFF
-#define HOST_HOSTSLC0_TOKEN1_M  ((HOST_HOSTSLC0_TOKEN1_V)<<(HOST_HOSTSLC0_TOKEN1_S))
-#define HOST_HOSTSLC0_TOKEN1_V  0xFFF
-#define HOST_HOSTSLC0_TOKEN1_S  16
-/* HOST_SLC0_RX_PF_VALID : RO ;bitpos:[12] ;default: 4'h0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID  (BIT(12))
-#define HOST_SLC0_RX_PF_VALID_M  (BIT(12))
-#define HOST_SLC0_RX_PF_VALID_V  0x1
-#define HOST_SLC0_RX_PF_VALID_S  12
-/* HOST_SLC0_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0  0x00000FFF
-#define HOST_SLC0_TOKEN0_M  ((HOST_SLC0_TOKEN0_V)<<(HOST_SLC0_TOKEN0_S))
-#define HOST_SLC0_TOKEN0_V  0xFFF
-#define HOST_SLC0_TOKEN0_S  0
-
-#define HOST_SLC0_HOST_PF_REG          (DR_REG_SLCHOST_BASE + 0x48)
-/* HOST_SLC0_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define HOST_SLC0_PF_DATA  0xFFFFFFFF
-#define HOST_SLC0_PF_DATA_M  ((HOST_SLC0_PF_DATA_V)<<(HOST_SLC0_PF_DATA_S))
-#define HOST_SLC0_PF_DATA_V  0xFFFFFFFF
-#define HOST_SLC0_PF_DATA_S  0
-
-#define HOST_SLC1_HOST_PF_REG          (DR_REG_SLCHOST_BASE + 0x4C)
-/* HOST_SLC1_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define HOST_SLC1_PF_DATA  0xFFFFFFFF
-#define HOST_SLC1_PF_DATA_M  ((HOST_SLC1_PF_DATA_V)<<(HOST_SLC1_PF_DATA_S))
-#define HOST_SLC1_PF_DATA_V  0xFFFFFFFF
-#define HOST_SLC1_PF_DATA_S  0
-
-#define HOST_SLC0HOST_INT_RAW_REG          (DR_REG_SLCHOST_BASE + 0x50)
-/* HOST_GPIO_SDIO_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_RAW  (BIT(25))
-#define HOST_GPIO_SDIO_INT_RAW_M  (BIT(25))
-#define HOST_GPIO_SDIO_INT_RAW_V  0x1
-#define HOST_GPIO_SDIO_INT_RAW_S  25
-/* HOST_SLC0_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_RAW  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_M  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_V  0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_S  24
-/* HOST_SLC0_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_RAW  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_M  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_V  0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_S  23
-/* HOST_SLC0_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_RAW  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_RAW_M  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_RAW_V  0x1
-#define HOST_SLC0_EXT_BIT3_INT_RAW_S  22
-/* HOST_SLC0_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_RAW  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_RAW_M  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_RAW_V  0x1
-#define HOST_SLC0_EXT_BIT2_INT_RAW_S  21
-/* HOST_SLC0_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_RAW  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_RAW_M  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_RAW_V  0x1
-#define HOST_SLC0_EXT_BIT1_INT_RAW_S  20
-/* HOST_SLC0_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_RAW  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_RAW_M  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_RAW_V  0x1
-#define HOST_SLC0_EXT_BIT0_INT_RAW_S  19
-/* HOST_SLC0_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_RAW  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_RAW_M  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_RAW_V  0x1
-#define HOST_SLC0_RX_PF_VALID_INT_RAW_S  18
-/* HOST_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_RAW  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_RAW_M  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_RAW_V  0x1
-#define HOST_SLC0_TX_OVF_INT_RAW_S  17
-/* HOST_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_RAW  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_RAW_M  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_RAW_V  0x1
-#define HOST_SLC0_RX_UDF_INT_RAW_S  16
-/* HOST_SLC0HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_RAW  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_RAW_M  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_RAW_V  0x1
-#define HOST_SLC0HOST_TX_START_INT_RAW_S  15
-/* HOST_SLC0HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_RAW  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_RAW_M  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_RAW_V  0x1
-#define HOST_SLC0HOST_RX_START_INT_RAW_S  14
-/* HOST_SLC0HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_RAW  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_RAW_M  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_RAW_V  0x1
-#define HOST_SLC0HOST_RX_EOF_INT_RAW_S  13
-/* HOST_SLC0HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_RAW  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_RAW_M  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_RAW_V  0x1
-#define HOST_SLC0HOST_RX_SOF_INT_RAW_S  12
-/* HOST_SLC0_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_RAW  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_M  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_V  0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_S  11
-/* HOST_SLC0_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_RAW  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_M  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_V  0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_S  10
-/* HOST_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_RAW  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_M  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_V  0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_S  9
-/* HOST_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_RAW  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_M  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_V  0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_S  8
-/* HOST_SLC0_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_RAW  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_RAW_M  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_RAW_V  0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_RAW_S  7
-/* HOST_SLC0_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_RAW  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_RAW_M  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_RAW_V  0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_RAW_S  6
-/* HOST_SLC0_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_RAW  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_RAW_M  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_RAW_V  0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_RAW_S  5
-/* HOST_SLC0_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_RAW  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_RAW_M  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_RAW_V  0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_RAW_S  4
-/* HOST_SLC0_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_RAW  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_RAW_M  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_RAW_V  0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_RAW_S  3
-/* HOST_SLC0_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_RAW  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_RAW_M  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_RAW_V  0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_RAW_S  2
-/* HOST_SLC0_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_RAW  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_RAW_M  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_RAW_V  0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_RAW_S  1
-/* HOST_SLC0_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_RAW  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_RAW_M  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_RAW_V  0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_RAW_S  0
-
-#define HOST_SLC1HOST_INT_RAW_REG          (DR_REG_SLCHOST_BASE + 0x54)
-/* HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V  0x1
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S  25
-/* HOST_SLC1_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_HOST_RD_RETRY_INT_RAW  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_RAW_M  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_RAW_V  0x1
-#define HOST_SLC1_HOST_RD_RETRY_INT_RAW_S  24
-/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V  0x1
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S  23
-/* HOST_SLC1_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT3_INT_RAW  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_RAW_M  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_RAW_V  0x1
-#define HOST_SLC1_EXT_BIT3_INT_RAW_S  22
-/* HOST_SLC1_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT2_INT_RAW  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_RAW_M  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_RAW_V  0x1
-#define HOST_SLC1_EXT_BIT2_INT_RAW_S  21
-/* HOST_SLC1_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT1_INT_RAW  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_RAW_M  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_RAW_V  0x1
-#define HOST_SLC1_EXT_BIT1_INT_RAW_S  20
-/* HOST_SLC1_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT0_INT_RAW  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_RAW_M  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_RAW_V  0x1
-#define HOST_SLC1_EXT_BIT0_INT_RAW_S  19
-/* HOST_SLC1_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_PF_VALID_INT_RAW  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_RAW_M  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_RAW_V  0x1
-#define HOST_SLC1_RX_PF_VALID_INT_RAW_S  18
-/* HOST_SLC1_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TX_OVF_INT_RAW  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_RAW_M  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_RAW_V  0x1
-#define HOST_SLC1_TX_OVF_INT_RAW_S  17
-/* HOST_SLC1_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_UDF_INT_RAW  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_RAW_M  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_RAW_V  0x1
-#define HOST_SLC1_RX_UDF_INT_RAW_S  16
-/* HOST_SLC1HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_TX_START_INT_RAW  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_RAW_M  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_RAW_V  0x1
-#define HOST_SLC1HOST_TX_START_INT_RAW_S  15
-/* HOST_SLC1HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_START_INT_RAW  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_RAW_M  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_RAW_V  0x1
-#define HOST_SLC1HOST_RX_START_INT_RAW_S  14
-/* HOST_SLC1HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_EOF_INT_RAW  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_RAW_M  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_RAW_V  0x1
-#define HOST_SLC1HOST_RX_EOF_INT_RAW_S  13
-/* HOST_SLC1HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_SOF_INT_RAW  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_RAW_M  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_RAW_V  0x1
-#define HOST_SLC1HOST_RX_SOF_INT_RAW_S  12
-/* HOST_SLC1_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_0TO1_INT_RAW  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_RAW_M  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_RAW_V  0x1
-#define HOST_SLC1_TOKEN1_0TO1_INT_RAW_S  11
-/* HOST_SLC1_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_0TO1_INT_RAW  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_RAW_M  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_RAW_V  0x1
-#define HOST_SLC1_TOKEN0_0TO1_INT_RAW_S  10
-/* HOST_SLC1_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_1TO0_INT_RAW  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_RAW_M  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_RAW_V  0x1
-#define HOST_SLC1_TOKEN1_1TO0_INT_RAW_S  9
-/* HOST_SLC1_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_1TO0_INT_RAW  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_RAW_M  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_RAW_V  0x1
-#define HOST_SLC1_TOKEN0_1TO0_INT_RAW_S  8
-/* HOST_SLC1_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT7_INT_RAW  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_RAW_M  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_RAW_V  0x1
-#define HOST_SLC1_TOHOST_BIT7_INT_RAW_S  7
-/* HOST_SLC1_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT6_INT_RAW  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_RAW_M  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_RAW_V  0x1
-#define HOST_SLC1_TOHOST_BIT6_INT_RAW_S  6
-/* HOST_SLC1_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT5_INT_RAW  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_RAW_M  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_RAW_V  0x1
-#define HOST_SLC1_TOHOST_BIT5_INT_RAW_S  5
-/* HOST_SLC1_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT4_INT_RAW  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_RAW_M  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_RAW_V  0x1
-#define HOST_SLC1_TOHOST_BIT4_INT_RAW_S  4
-/* HOST_SLC1_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT3_INT_RAW  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_RAW_M  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_RAW_V  0x1
-#define HOST_SLC1_TOHOST_BIT3_INT_RAW_S  3
-/* HOST_SLC1_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT2_INT_RAW  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_RAW_M  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_RAW_V  0x1
-#define HOST_SLC1_TOHOST_BIT2_INT_RAW_S  2
-/* HOST_SLC1_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT1_INT_RAW  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_RAW_M  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_RAW_V  0x1
-#define HOST_SLC1_TOHOST_BIT1_INT_RAW_S  1
-/* HOST_SLC1_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT0_INT_RAW  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_RAW_M  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_RAW_V  0x1
-#define HOST_SLC1_TOHOST_BIT0_INT_RAW_S  0
-
-#define HOST_SLC0HOST_INT_ST_REG          (DR_REG_SLCHOST_BASE + 0x58)
-/* HOST_GPIO_SDIO_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_ST  (BIT(25))
-#define HOST_GPIO_SDIO_INT_ST_M  (BIT(25))
-#define HOST_GPIO_SDIO_INT_ST_V  0x1
-#define HOST_GPIO_SDIO_INT_ST_S  25
-/* HOST_SLC0_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_ST  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ST_M  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ST_V  0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_ST_S  24
-/* HOST_SLC0_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_ST  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ST_M  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ST_V  0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_ST_S  23
-/* HOST_SLC0_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_ST  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ST_M  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ST_V  0x1
-#define HOST_SLC0_EXT_BIT3_INT_ST_S  22
-/* HOST_SLC0_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_ST  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ST_M  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ST_V  0x1
-#define HOST_SLC0_EXT_BIT2_INT_ST_S  21
-/* HOST_SLC0_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_ST  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ST_M  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ST_V  0x1
-#define HOST_SLC0_EXT_BIT1_INT_ST_S  20
-/* HOST_SLC0_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_ST  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ST_M  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ST_V  0x1
-#define HOST_SLC0_EXT_BIT0_INT_ST_S  19
-/* HOST_SLC0_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_ST  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ST_M  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ST_V  0x1
-#define HOST_SLC0_RX_PF_VALID_INT_ST_S  18
-/* HOST_SLC0_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_ST  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ST_M  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ST_V  0x1
-#define HOST_SLC0_TX_OVF_INT_ST_S  17
-/* HOST_SLC0_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_ST  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ST_M  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ST_V  0x1
-#define HOST_SLC0_RX_UDF_INT_ST_S  16
-/* HOST_SLC0HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_ST  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ST_M  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ST_V  0x1
-#define HOST_SLC0HOST_TX_START_INT_ST_S  15
-/* HOST_SLC0HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_ST  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ST_M  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ST_V  0x1
-#define HOST_SLC0HOST_RX_START_INT_ST_S  14
-/* HOST_SLC0HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_ST  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ST_M  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ST_V  0x1
-#define HOST_SLC0HOST_RX_EOF_INT_ST_S  13
-/* HOST_SLC0HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_ST  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ST_M  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ST_V  0x1
-#define HOST_SLC0HOST_RX_SOF_INT_ST_S  12
-/* HOST_SLC0_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_ST  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ST_M  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ST_V  0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_ST_S  11
-/* HOST_SLC0_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_ST  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ST_M  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ST_V  0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_ST_S  10
-/* HOST_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_ST  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ST_M  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ST_V  0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_ST_S  9
-/* HOST_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_ST  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ST_M  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ST_V  0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_ST_S  8
-/* HOST_SLC0_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_ST  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ST_M  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ST_V  0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_ST_S  7
-/* HOST_SLC0_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_ST  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ST_M  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ST_V  0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_ST_S  6
-/* HOST_SLC0_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_ST  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ST_M  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ST_V  0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_ST_S  5
-/* HOST_SLC0_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_ST  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ST_M  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ST_V  0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_ST_S  4
-/* HOST_SLC0_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_ST  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ST_M  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ST_V  0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_ST_S  3
-/* HOST_SLC0_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_ST  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ST_M  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ST_V  0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_ST_S  2
-/* HOST_SLC0_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_ST  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ST_M  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ST_V  0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_ST_S  1
-/* HOST_SLC0_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_ST  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ST_M  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ST_V  0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_ST_S  0
-
-#define HOST_SLC1HOST_INT_ST_REG          (DR_REG_SLCHOST_BASE + 0x5C)
-/* HOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V  0x1
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S  25
-/* HOST_SLC1_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_HOST_RD_RETRY_INT_ST  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_ST_M  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_ST_V  0x1
-#define HOST_SLC1_HOST_RD_RETRY_INT_ST_S  24
-/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V  0x1
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S  23
-/* HOST_SLC1_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT3_INT_ST  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_ST_M  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_ST_V  0x1
-#define HOST_SLC1_EXT_BIT3_INT_ST_S  22
-/* HOST_SLC1_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT2_INT_ST  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_ST_M  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_ST_V  0x1
-#define HOST_SLC1_EXT_BIT2_INT_ST_S  21
-/* HOST_SLC1_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT1_INT_ST  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_ST_M  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_ST_V  0x1
-#define HOST_SLC1_EXT_BIT1_INT_ST_S  20
-/* HOST_SLC1_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT0_INT_ST  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_ST_M  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_ST_V  0x1
-#define HOST_SLC1_EXT_BIT0_INT_ST_S  19
-/* HOST_SLC1_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_PF_VALID_INT_ST  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_ST_M  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_ST_V  0x1
-#define HOST_SLC1_RX_PF_VALID_INT_ST_S  18
-/* HOST_SLC1_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TX_OVF_INT_ST  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_ST_M  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_ST_V  0x1
-#define HOST_SLC1_TX_OVF_INT_ST_S  17
-/* HOST_SLC1_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_UDF_INT_ST  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_ST_M  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_ST_V  0x1
-#define HOST_SLC1_RX_UDF_INT_ST_S  16
-/* HOST_SLC1HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_TX_START_INT_ST  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_ST_M  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_ST_V  0x1
-#define HOST_SLC1HOST_TX_START_INT_ST_S  15
-/* HOST_SLC1HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_START_INT_ST  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_ST_M  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_ST_V  0x1
-#define HOST_SLC1HOST_RX_START_INT_ST_S  14
-/* HOST_SLC1HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_EOF_INT_ST  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_ST_M  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_ST_V  0x1
-#define HOST_SLC1HOST_RX_EOF_INT_ST_S  13
-/* HOST_SLC1HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_SOF_INT_ST  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_ST_M  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_ST_V  0x1
-#define HOST_SLC1HOST_RX_SOF_INT_ST_S  12
-/* HOST_SLC1_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_0TO1_INT_ST  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_ST_M  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_ST_V  0x1
-#define HOST_SLC1_TOKEN1_0TO1_INT_ST_S  11
-/* HOST_SLC1_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_0TO1_INT_ST  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_ST_M  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_ST_V  0x1
-#define HOST_SLC1_TOKEN0_0TO1_INT_ST_S  10
-/* HOST_SLC1_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_1TO0_INT_ST  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_ST_M  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_ST_V  0x1
-#define HOST_SLC1_TOKEN1_1TO0_INT_ST_S  9
-/* HOST_SLC1_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_1TO0_INT_ST  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_ST_M  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_ST_V  0x1
-#define HOST_SLC1_TOKEN0_1TO0_INT_ST_S  8
-/* HOST_SLC1_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT7_INT_ST  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_ST_M  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_ST_V  0x1
-#define HOST_SLC1_TOHOST_BIT7_INT_ST_S  7
-/* HOST_SLC1_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT6_INT_ST  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_ST_M  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_ST_V  0x1
-#define HOST_SLC1_TOHOST_BIT6_INT_ST_S  6
-/* HOST_SLC1_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT5_INT_ST  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_ST_M  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_ST_V  0x1
-#define HOST_SLC1_TOHOST_BIT5_INT_ST_S  5
-/* HOST_SLC1_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT4_INT_ST  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_ST_M  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_ST_V  0x1
-#define HOST_SLC1_TOHOST_BIT4_INT_ST_S  4
-/* HOST_SLC1_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT3_INT_ST  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_ST_M  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_ST_V  0x1
-#define HOST_SLC1_TOHOST_BIT3_INT_ST_S  3
-/* HOST_SLC1_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT2_INT_ST  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_ST_M  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_ST_V  0x1
-#define HOST_SLC1_TOHOST_BIT2_INT_ST_S  2
-/* HOST_SLC1_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT1_INT_ST  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_ST_M  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_ST_V  0x1
-#define HOST_SLC1_TOHOST_BIT1_INT_ST_S  1
-/* HOST_SLC1_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT0_INT_ST  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_ST_M  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_ST_V  0x1
-#define HOST_SLC1_TOHOST_BIT0_INT_ST_S  0
-
-#define HOST_SLCHOST_PKT_LEN_REG          (DR_REG_SLCHOST_BASE + 0x60)
-/* HOST_HOSTSLC0_LEN_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN_CHECK  0x00000FFF
-#define HOST_HOSTSLC0_LEN_CHECK_M  ((HOST_HOSTSLC0_LEN_CHECK_V)<<(HOST_HOSTSLC0_LEN_CHECK_S))
-#define HOST_HOSTSLC0_LEN_CHECK_V  0xFFF
-#define HOST_HOSTSLC0_LEN_CHECK_S  20
-/* HOST_HOSTSLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN  0x000FFFFF
-#define HOST_HOSTSLC0_LEN_M  ((HOST_HOSTSLC0_LEN_V)<<(HOST_HOSTSLC0_LEN_S))
-#define HOST_HOSTSLC0_LEN_V  0xFFFFF
-#define HOST_HOSTSLC0_LEN_S  0
-
-#define HOST_SLCHOST_STATE_W0_REG          (DR_REG_SLCHOST_BASE + 0x64)
-/* HOST_SLCHOST_STATE3 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE3  0x000000FF
-#define HOST_SLCHOST_STATE3_M  ((HOST_SLCHOST_STATE3_V)<<(HOST_SLCHOST_STATE3_S))
-#define HOST_SLCHOST_STATE3_V  0xFF
-#define HOST_SLCHOST_STATE3_S  24
-/* HOST_SLCHOST_STATE2 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE2  0x000000FF
-#define HOST_SLCHOST_STATE2_M  ((HOST_SLCHOST_STATE2_V)<<(HOST_SLCHOST_STATE2_S))
-#define HOST_SLCHOST_STATE2_V  0xFF
-#define HOST_SLCHOST_STATE2_S  16
-/* HOST_SLCHOST_STATE1 : RO ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE1  0x000000FF
-#define HOST_SLCHOST_STATE1_M  ((HOST_SLCHOST_STATE1_V)<<(HOST_SLCHOST_STATE1_S))
-#define HOST_SLCHOST_STATE1_V  0xFF
-#define HOST_SLCHOST_STATE1_S  8
-/* HOST_SLCHOST_STATE0 : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE0  0x000000FF
-#define HOST_SLCHOST_STATE0_M  ((HOST_SLCHOST_STATE0_V)<<(HOST_SLCHOST_STATE0_S))
-#define HOST_SLCHOST_STATE0_V  0xFF
-#define HOST_SLCHOST_STATE0_S  0
-
-#define HOST_SLCHOST_STATE_W1_REG          (DR_REG_SLCHOST_BASE + 0x68)
-/* HOST_SLCHOST_STATE7 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE7  0x000000FF
-#define HOST_SLCHOST_STATE7_M  ((HOST_SLCHOST_STATE7_V)<<(HOST_SLCHOST_STATE7_S))
-#define HOST_SLCHOST_STATE7_V  0xFF
-#define HOST_SLCHOST_STATE7_S  24
-/* HOST_SLCHOST_STATE6 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE6  0x000000FF
-#define HOST_SLCHOST_STATE6_M  ((HOST_SLCHOST_STATE6_V)<<(HOST_SLCHOST_STATE6_S))
-#define HOST_SLCHOST_STATE6_V  0xFF
-#define HOST_SLCHOST_STATE6_S  16
-/* HOST_SLCHOST_STATE5 : RO ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE5  0x000000FF
-#define HOST_SLCHOST_STATE5_M  ((HOST_SLCHOST_STATE5_V)<<(HOST_SLCHOST_STATE5_S))
-#define HOST_SLCHOST_STATE5_V  0xFF
-#define HOST_SLCHOST_STATE5_S  8
-/* HOST_SLCHOST_STATE4 : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_STATE4  0x000000FF
-#define HOST_SLCHOST_STATE4_M  ((HOST_SLCHOST_STATE4_V)<<(HOST_SLCHOST_STATE4_S))
-#define HOST_SLCHOST_STATE4_V  0xFF
-#define HOST_SLCHOST_STATE4_S  0
-
-#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0))
-
-#define HOST_SLCHOST_CONF_W0_REG          (DR_REG_SLCHOST_BASE + 0x6C)
-/* HOST_SLCHOST_CONF3 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF3  0x000000FF
-#define HOST_SLCHOST_CONF3_M  ((HOST_SLCHOST_CONF3_V)<<(HOST_SLCHOST_CONF3_S))
-#define HOST_SLCHOST_CONF3_V  0xFF
-#define HOST_SLCHOST_CONF3_S  24
-/* HOST_SLCHOST_CONF2 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF2  0x000000FF
-#define HOST_SLCHOST_CONF2_M  ((HOST_SLCHOST_CONF2_V)<<(HOST_SLCHOST_CONF2_S))
-#define HOST_SLCHOST_CONF2_V  0xFF
-#define HOST_SLCHOST_CONF2_S  16
-/* HOST_SLCHOST_CONF1 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF1  0x000000FF
-#define HOST_SLCHOST_CONF1_M  ((HOST_SLCHOST_CONF1_V)<<(HOST_SLCHOST_CONF1_S))
-#define HOST_SLCHOST_CONF1_V  0xFF
-#define HOST_SLCHOST_CONF1_S  8
-/* HOST_SLCHOST_CONF0 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF0  0x000000FF
-#define HOST_SLCHOST_CONF0_M  ((HOST_SLCHOST_CONF0_V)<<(HOST_SLCHOST_CONF0_S))
-#define HOST_SLCHOST_CONF0_V  0xFF
-#define HOST_SLCHOST_CONF0_S  0
-
-#define HOST_SLCHOST_CONF_W1_REG          (DR_REG_SLCHOST_BASE + 0x70)
-/* HOST_SLCHOST_CONF7 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF7  0x000000FF
-#define HOST_SLCHOST_CONF7_M  ((HOST_SLCHOST_CONF7_V)<<(HOST_SLCHOST_CONF7_S))
-#define HOST_SLCHOST_CONF7_V  0xFF
-#define HOST_SLCHOST_CONF7_S  24
-/* HOST_SLCHOST_CONF6 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF6  0x000000FF
-#define HOST_SLCHOST_CONF6_M  ((HOST_SLCHOST_CONF6_V)<<(HOST_SLCHOST_CONF6_S))
-#define HOST_SLCHOST_CONF6_V  0xFF
-#define HOST_SLCHOST_CONF6_S  16
-/* HOST_SLCHOST_CONF5 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF5  0x000000FF
-#define HOST_SLCHOST_CONF5_M  ((HOST_SLCHOST_CONF5_V)<<(HOST_SLCHOST_CONF5_S))
-#define HOST_SLCHOST_CONF5_V  0xFF
-#define HOST_SLCHOST_CONF5_S  8
-/* HOST_SLCHOST_CONF4 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF4  0x000000FF
-#define HOST_SLCHOST_CONF4_M  ((HOST_SLCHOST_CONF4_V)<<(HOST_SLCHOST_CONF4_S))
-#define HOST_SLCHOST_CONF4_V  0xFF
-#define HOST_SLCHOST_CONF4_S  0
-
-#define HOST_SLCHOST_CONF_W2_REG          (DR_REG_SLCHOST_BASE + 0x74)
-/* HOST_SLCHOST_CONF11 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF11  0x000000FF
-#define HOST_SLCHOST_CONF11_M  ((HOST_SLCHOST_CONF11_V)<<(HOST_SLCHOST_CONF11_S))
-#define HOST_SLCHOST_CONF11_V  0xFF
-#define HOST_SLCHOST_CONF11_S  24
-/* HOST_SLCHOST_CONF10 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF10  0x000000FF
-#define HOST_SLCHOST_CONF10_M  ((HOST_SLCHOST_CONF10_V)<<(HOST_SLCHOST_CONF10_S))
-#define HOST_SLCHOST_CONF10_V  0xFF
-#define HOST_SLCHOST_CONF10_S  16
-/* HOST_SLCHOST_CONF9 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF9  0x000000FF
-#define HOST_SLCHOST_CONF9_M  ((HOST_SLCHOST_CONF9_V)<<(HOST_SLCHOST_CONF9_S))
-#define HOST_SLCHOST_CONF9_V  0xFF
-#define HOST_SLCHOST_CONF9_S  8
-/* HOST_SLCHOST_CONF8 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF8  0x000000FF
-#define HOST_SLCHOST_CONF8_M  ((HOST_SLCHOST_CONF8_V)<<(HOST_SLCHOST_CONF8_S))
-#define HOST_SLCHOST_CONF8_V  0xFF
-#define HOST_SLCHOST_CONF8_S  0
-
-#define HOST_SLCHOST_CONF_W3_REG          (DR_REG_SLCHOST_BASE + 0x78)
-/* HOST_SLCHOST_CONF15 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF15  0x000000FF
-#define HOST_SLCHOST_CONF15_M  ((HOST_SLCHOST_CONF15_V)<<(HOST_SLCHOST_CONF15_S))
-#define HOST_SLCHOST_CONF15_V  0xFF
-#define HOST_SLCHOST_CONF15_S  24
-/* HOST_SLCHOST_CONF14 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF14  0x000000FF
-#define HOST_SLCHOST_CONF14_M  ((HOST_SLCHOST_CONF14_V)<<(HOST_SLCHOST_CONF14_S))
-#define HOST_SLCHOST_CONF14_V  0xFF
-#define HOST_SLCHOST_CONF14_S  16
-/* HOST_SLCHOST_CONF13 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF13  0x000000FF
-#define HOST_SLCHOST_CONF13_M  ((HOST_SLCHOST_CONF13_V)<<(HOST_SLCHOST_CONF13_S))
-#define HOST_SLCHOST_CONF13_V  0xFF
-#define HOST_SLCHOST_CONF13_S  8
-/* HOST_SLCHOST_CONF12 : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF12  0x000000FF
-#define HOST_SLCHOST_CONF12_M  ((HOST_SLCHOST_CONF12_V)<<(HOST_SLCHOST_CONF12_S))
-#define HOST_SLCHOST_CONF12_V  0xFF
-#define HOST_SLCHOST_CONF12_S  0
-
-#define HOST_SLCHOST_CONF_W4_REG          (DR_REG_SLCHOST_BASE + 0x7C)
-/* HOST_SLCHOST_CONF19 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: Interrupt to target CPU*/
-#define HOST_SLCHOST_CONF19  0x000000FF
-#define HOST_SLCHOST_CONF19_M  ((HOST_SLCHOST_CONF19_V)<<(HOST_SLCHOST_CONF19_S))
-#define HOST_SLCHOST_CONF19_V  0xFF
-#define HOST_SLCHOST_CONF19_S  24
-/* HOST_SLCHOST_CONF18 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF18  0x000000FF
-#define HOST_SLCHOST_CONF18_M  ((HOST_SLCHOST_CONF18_V)<<(HOST_SLCHOST_CONF18_S))
-#define HOST_SLCHOST_CONF18_V  0xFF
-#define HOST_SLCHOST_CONF18_S  16
-/* HOST_SLCHOST_CONF17 : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: SLC timeout enable*/
-#define HOST_SLCHOST_CONF17  0x000000FF
-#define HOST_SLCHOST_CONF17_M  ((HOST_SLCHOST_CONF17_V)<<(HOST_SLCHOST_CONF17_S))
-#define HOST_SLCHOST_CONF17_V  0xFF
-#define HOST_SLCHOST_CONF17_S  8
-/* HOST_SLCHOST_CONF16 : R/W ;bitpos:[7:0] ;default: 8'hFF ; */
-/*description: SLC timeout value*/
-#define HOST_SLCHOST_CONF16  0x000000FF
-#define HOST_SLCHOST_CONF16_M  ((HOST_SLCHOST_CONF16_V)<<(HOST_SLCHOST_CONF16_S))
-#define HOST_SLCHOST_CONF16_V  0xFF
-#define HOST_SLCHOST_CONF16_S  0
-
-#define HOST_SLCHOST_CONF_W5_REG          (DR_REG_SLCHOST_BASE + 0x80)
-/* HOST_SLCHOST_CONF23 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF23  0x000000FF
-#define HOST_SLCHOST_CONF23_M  ((HOST_SLCHOST_CONF23_V)<<(HOST_SLCHOST_CONF23_S))
-#define HOST_SLCHOST_CONF23_V  0xFF
-#define HOST_SLCHOST_CONF23_S  24
-/* HOST_SLCHOST_CONF22 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF22  0x000000FF
-#define HOST_SLCHOST_CONF22_M  ((HOST_SLCHOST_CONF22_V)<<(HOST_SLCHOST_CONF22_S))
-#define HOST_SLCHOST_CONF22_V  0xFF
-#define HOST_SLCHOST_CONF22_S  16
-/* HOST_SLCHOST_CONF21 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF21  0x000000FF
-#define HOST_SLCHOST_CONF21_M  ((HOST_SLCHOST_CONF21_V)<<(HOST_SLCHOST_CONF21_S))
-#define HOST_SLCHOST_CONF21_V  0xFF
-#define HOST_SLCHOST_CONF21_S  8
-/* HOST_SLCHOST_CONF20 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF20  0x000000FF
-#define HOST_SLCHOST_CONF20_M  ((HOST_SLCHOST_CONF20_V)<<(HOST_SLCHOST_CONF20_S))
-#define HOST_SLCHOST_CONF20_V  0xFF
-#define HOST_SLCHOST_CONF20_S  0
-
-#define HOST_SLCHOST_WIN_CMD_REG          (DR_REG_SLCHOST_BASE + 0x84)
-
-#define HOST_SLCHOST_CONF_W6_REG          (DR_REG_SLCHOST_BASE + 0x88)
-/* HOST_SLCHOST_CONF27 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF27  0x000000FF
-#define HOST_SLCHOST_CONF27_M  ((HOST_SLCHOST_CONF27_V)<<(HOST_SLCHOST_CONF27_S))
-#define HOST_SLCHOST_CONF27_V  0xFF
-#define HOST_SLCHOST_CONF27_S  24
-/* HOST_SLCHOST_CONF26 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF26  0x000000FF
-#define HOST_SLCHOST_CONF26_M  ((HOST_SLCHOST_CONF26_V)<<(HOST_SLCHOST_CONF26_S))
-#define HOST_SLCHOST_CONF26_V  0xFF
-#define HOST_SLCHOST_CONF26_S  16
-/* HOST_SLCHOST_CONF25 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF25  0x000000FF
-#define HOST_SLCHOST_CONF25_M  ((HOST_SLCHOST_CONF25_V)<<(HOST_SLCHOST_CONF25_S))
-#define HOST_SLCHOST_CONF25_V  0xFF
-#define HOST_SLCHOST_CONF25_S  8
-/* HOST_SLCHOST_CONF24 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF24  0x000000FF
-#define HOST_SLCHOST_CONF24_M  ((HOST_SLCHOST_CONF24_V)<<(HOST_SLCHOST_CONF24_S))
-#define HOST_SLCHOST_CONF24_V  0xFF
-#define HOST_SLCHOST_CONF24_S  0
-
-#define HOST_SLCHOST_CONF_W7_REG          (DR_REG_SLCHOST_BASE + 0x8C)
-/* HOST_SLCHOST_CONF31 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF31  0x000000FF
-#define HOST_SLCHOST_CONF31_M  ((HOST_SLCHOST_CONF31_V)<<(HOST_SLCHOST_CONF31_S))
-#define HOST_SLCHOST_CONF31_V  0xFF
-#define HOST_SLCHOST_CONF31_S  24
-/* HOST_SLCHOST_CONF30 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF30  0x000000FF
-#define HOST_SLCHOST_CONF30_M  ((HOST_SLCHOST_CONF30_V)<<(HOST_SLCHOST_CONF30_S))
-#define HOST_SLCHOST_CONF30_V  0xFF
-#define HOST_SLCHOST_CONF30_S  16
-/* HOST_SLCHOST_CONF29 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF29  0x000000FF
-#define HOST_SLCHOST_CONF29_M  ((HOST_SLCHOST_CONF29_V)<<(HOST_SLCHOST_CONF29_S))
-#define HOST_SLCHOST_CONF29_V  0xFF
-#define HOST_SLCHOST_CONF29_S  8
-/* HOST_SLCHOST_CONF28 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF28  0x000000FF
-#define HOST_SLCHOST_CONF28_M  ((HOST_SLCHOST_CONF28_V)<<(HOST_SLCHOST_CONF28_S))
-#define HOST_SLCHOST_CONF28_V  0xFF
-#define HOST_SLCHOST_CONF28_S  0
-
-#define HOST_SLCHOST_PKT_LEN0_REG          (DR_REG_SLCHOST_BASE + 0x90)
-/* HOST_HOSTSLC0_LEN0 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN0  0x000FFFFF
-#define HOST_HOSTSLC0_LEN0_M  ((HOST_HOSTSLC0_LEN0_V)<<(HOST_HOSTSLC0_LEN0_S))
-#define HOST_HOSTSLC0_LEN0_V  0xFFFFF
-#define HOST_HOSTSLC0_LEN0_S  0
-
-#define HOST_SLCHOST_PKT_LEN1_REG          (DR_REG_SLCHOST_BASE + 0x94)
-/* HOST_HOSTSLC0_LEN1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN1  0x000FFFFF
-#define HOST_HOSTSLC0_LEN1_M  ((HOST_HOSTSLC0_LEN1_V)<<(HOST_HOSTSLC0_LEN1_S))
-#define HOST_HOSTSLC0_LEN1_V  0xFFFFF
-#define HOST_HOSTSLC0_LEN1_S  0
-
-#define HOST_SLCHOST_PKT_LEN2_REG          (DR_REG_SLCHOST_BASE + 0x98)
-/* HOST_HOSTSLC0_LEN2 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define HOST_HOSTSLC0_LEN2  0x000FFFFF
-#define HOST_HOSTSLC0_LEN2_M  ((HOST_HOSTSLC0_LEN2_V)<<(HOST_HOSTSLC0_LEN2_S))
-#define HOST_HOSTSLC0_LEN2_V  0xFFFFF
-#define HOST_HOSTSLC0_LEN2_S  0
-
-#define HOST_SLCHOST_CONF_W8_REG          (DR_REG_SLCHOST_BASE + 0x9C)
-/* HOST_SLCHOST_CONF35 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF35  0x000000FF
-#define HOST_SLCHOST_CONF35_M  ((HOST_SLCHOST_CONF35_V)<<(HOST_SLCHOST_CONF35_S))
-#define HOST_SLCHOST_CONF35_V  0xFF
-#define HOST_SLCHOST_CONF35_S  24
-/* HOST_SLCHOST_CONF34 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF34  0x000000FF
-#define HOST_SLCHOST_CONF34_M  ((HOST_SLCHOST_CONF34_V)<<(HOST_SLCHOST_CONF34_S))
-#define HOST_SLCHOST_CONF34_V  0xFF
-#define HOST_SLCHOST_CONF34_S  16
-/* HOST_SLCHOST_CONF33 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF33  0x000000FF
-#define HOST_SLCHOST_CONF33_M  ((HOST_SLCHOST_CONF33_V)<<(HOST_SLCHOST_CONF33_S))
-#define HOST_SLCHOST_CONF33_V  0xFF
-#define HOST_SLCHOST_CONF33_S  8
-/* HOST_SLCHOST_CONF32 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF32  0x000000FF
-#define HOST_SLCHOST_CONF32_M  ((HOST_SLCHOST_CONF32_V)<<(HOST_SLCHOST_CONF32_S))
-#define HOST_SLCHOST_CONF32_V  0xFF
-#define HOST_SLCHOST_CONF32_S  0
-
-#define HOST_SLCHOST_CONF_W9_REG          (DR_REG_SLCHOST_BASE + 0xA0)
-/* HOST_SLCHOST_CONF39 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF39  0x000000FF
-#define HOST_SLCHOST_CONF39_M  ((HOST_SLCHOST_CONF39_V)<<(HOST_SLCHOST_CONF39_S))
-#define HOST_SLCHOST_CONF39_V  0xFF
-#define HOST_SLCHOST_CONF39_S  24
-/* HOST_SLCHOST_CONF38 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF38  0x000000FF
-#define HOST_SLCHOST_CONF38_M  ((HOST_SLCHOST_CONF38_V)<<(HOST_SLCHOST_CONF38_S))
-#define HOST_SLCHOST_CONF38_V  0xFF
-#define HOST_SLCHOST_CONF38_S  16
-/* HOST_SLCHOST_CONF37 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF37  0x000000FF
-#define HOST_SLCHOST_CONF37_M  ((HOST_SLCHOST_CONF37_V)<<(HOST_SLCHOST_CONF37_S))
-#define HOST_SLCHOST_CONF37_V  0xFF
-#define HOST_SLCHOST_CONF37_S  8
-/* HOST_SLCHOST_CONF36 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF36  0x000000FF
-#define HOST_SLCHOST_CONF36_M  ((HOST_SLCHOST_CONF36_V)<<(HOST_SLCHOST_CONF36_S))
-#define HOST_SLCHOST_CONF36_V  0xFF
-#define HOST_SLCHOST_CONF36_S  0
-
-#define HOST_SLCHOST_CONF_W10_REG          (DR_REG_SLCHOST_BASE + 0xA4)
-/* HOST_SLCHOST_CONF43 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF43  0x000000FF
-#define HOST_SLCHOST_CONF43_M  ((HOST_SLCHOST_CONF43_V)<<(HOST_SLCHOST_CONF43_S))
-#define HOST_SLCHOST_CONF43_V  0xFF
-#define HOST_SLCHOST_CONF43_S  24
-/* HOST_SLCHOST_CONF42 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF42  0x000000FF
-#define HOST_SLCHOST_CONF42_M  ((HOST_SLCHOST_CONF42_V)<<(HOST_SLCHOST_CONF42_S))
-#define HOST_SLCHOST_CONF42_V  0xFF
-#define HOST_SLCHOST_CONF42_S  16
-/* HOST_SLCHOST_CONF41 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF41  0x000000FF
-#define HOST_SLCHOST_CONF41_M  ((HOST_SLCHOST_CONF41_V)<<(HOST_SLCHOST_CONF41_S))
-#define HOST_SLCHOST_CONF41_V  0xFF
-#define HOST_SLCHOST_CONF41_S  8
-/* HOST_SLCHOST_CONF40 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF40  0x000000FF
-#define HOST_SLCHOST_CONF40_M  ((HOST_SLCHOST_CONF40_V)<<(HOST_SLCHOST_CONF40_S))
-#define HOST_SLCHOST_CONF40_V  0xFF
-#define HOST_SLCHOST_CONF40_S  0
-
-#define HOST_SLCHOST_CONF_W11_REG          (DR_REG_SLCHOST_BASE + 0xA8)
-/* HOST_SLCHOST_CONF47 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF47  0x000000FF
-#define HOST_SLCHOST_CONF47_M  ((HOST_SLCHOST_CONF47_V)<<(HOST_SLCHOST_CONF47_S))
-#define HOST_SLCHOST_CONF47_V  0xFF
-#define HOST_SLCHOST_CONF47_S  24
-/* HOST_SLCHOST_CONF46 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF46  0x000000FF
-#define HOST_SLCHOST_CONF46_M  ((HOST_SLCHOST_CONF46_V)<<(HOST_SLCHOST_CONF46_S))
-#define HOST_SLCHOST_CONF46_V  0xFF
-#define HOST_SLCHOST_CONF46_S  16
-/* HOST_SLCHOST_CONF45 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF45  0x000000FF
-#define HOST_SLCHOST_CONF45_M  ((HOST_SLCHOST_CONF45_V)<<(HOST_SLCHOST_CONF45_S))
-#define HOST_SLCHOST_CONF45_V  0xFF
-#define HOST_SLCHOST_CONF45_S  8
-/* HOST_SLCHOST_CONF44 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF44  0x000000FF
-#define HOST_SLCHOST_CONF44_M  ((HOST_SLCHOST_CONF44_V)<<(HOST_SLCHOST_CONF44_S))
-#define HOST_SLCHOST_CONF44_V  0xFF
-#define HOST_SLCHOST_CONF44_S  0
-
-#define HOST_SLCHOST_CONF_W12_REG          (DR_REG_SLCHOST_BASE + 0xAC)
-/* HOST_SLCHOST_CONF51 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF51  0x000000FF
-#define HOST_SLCHOST_CONF51_M  ((HOST_SLCHOST_CONF51_V)<<(HOST_SLCHOST_CONF51_S))
-#define HOST_SLCHOST_CONF51_V  0xFF
-#define HOST_SLCHOST_CONF51_S  24
-/* HOST_SLCHOST_CONF50 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF50  0x000000FF
-#define HOST_SLCHOST_CONF50_M  ((HOST_SLCHOST_CONF50_V)<<(HOST_SLCHOST_CONF50_S))
-#define HOST_SLCHOST_CONF50_V  0xFF
-#define HOST_SLCHOST_CONF50_S  16
-/* HOST_SLCHOST_CONF49 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF49  0x000000FF
-#define HOST_SLCHOST_CONF49_M  ((HOST_SLCHOST_CONF49_V)<<(HOST_SLCHOST_CONF49_S))
-#define HOST_SLCHOST_CONF49_V  0xFF
-#define HOST_SLCHOST_CONF49_S  8
-/* HOST_SLCHOST_CONF48 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF48  0x000000FF
-#define HOST_SLCHOST_CONF48_M  ((HOST_SLCHOST_CONF48_V)<<(HOST_SLCHOST_CONF48_S))
-#define HOST_SLCHOST_CONF48_V  0xFF
-#define HOST_SLCHOST_CONF48_S  0
-
-#define HOST_SLCHOST_CONF_W13_REG          (DR_REG_SLCHOST_BASE + 0xB0)
-/* HOST_SLCHOST_CONF55 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF55  0x000000FF
-#define HOST_SLCHOST_CONF55_M  ((HOST_SLCHOST_CONF55_V)<<(HOST_SLCHOST_CONF55_S))
-#define HOST_SLCHOST_CONF55_V  0xFF
-#define HOST_SLCHOST_CONF55_S  24
-/* HOST_SLCHOST_CONF54 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF54  0x000000FF
-#define HOST_SLCHOST_CONF54_M  ((HOST_SLCHOST_CONF54_V)<<(HOST_SLCHOST_CONF54_S))
-#define HOST_SLCHOST_CONF54_V  0xFF
-#define HOST_SLCHOST_CONF54_S  16
-/* HOST_SLCHOST_CONF53 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF53  0x000000FF
-#define HOST_SLCHOST_CONF53_M  ((HOST_SLCHOST_CONF53_V)<<(HOST_SLCHOST_CONF53_S))
-#define HOST_SLCHOST_CONF53_V  0xFF
-#define HOST_SLCHOST_CONF53_S  8
-/* HOST_SLCHOST_CONF52 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF52  0x000000FF
-#define HOST_SLCHOST_CONF52_M  ((HOST_SLCHOST_CONF52_V)<<(HOST_SLCHOST_CONF52_S))
-#define HOST_SLCHOST_CONF52_V  0xFF
-#define HOST_SLCHOST_CONF52_S  0
-
-#define HOST_SLCHOST_CONF_W14_REG          (DR_REG_SLCHOST_BASE + 0xB4)
-/* HOST_SLCHOST_CONF59 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF59  0x000000FF
-#define HOST_SLCHOST_CONF59_M  ((HOST_SLCHOST_CONF59_V)<<(HOST_SLCHOST_CONF59_S))
-#define HOST_SLCHOST_CONF59_V  0xFF
-#define HOST_SLCHOST_CONF59_S  24
-/* HOST_SLCHOST_CONF58 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF58  0x000000FF
-#define HOST_SLCHOST_CONF58_M  ((HOST_SLCHOST_CONF58_V)<<(HOST_SLCHOST_CONF58_S))
-#define HOST_SLCHOST_CONF58_V  0xFF
-#define HOST_SLCHOST_CONF58_S  16
-/* HOST_SLCHOST_CONF57 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF57  0x000000FF
-#define HOST_SLCHOST_CONF57_M  ((HOST_SLCHOST_CONF57_V)<<(HOST_SLCHOST_CONF57_S))
-#define HOST_SLCHOST_CONF57_V  0xFF
-#define HOST_SLCHOST_CONF57_S  8
-/* HOST_SLCHOST_CONF56 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF56  0x000000FF
-#define HOST_SLCHOST_CONF56_M  ((HOST_SLCHOST_CONF56_V)<<(HOST_SLCHOST_CONF56_S))
-#define HOST_SLCHOST_CONF56_V  0xFF
-#define HOST_SLCHOST_CONF56_S  0
-
-#define HOST_SLCHOST_CONF_W15_REG          (DR_REG_SLCHOST_BASE + 0xB8)
-/* HOST_SLCHOST_CONF63 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF63  0x000000FF
-#define HOST_SLCHOST_CONF63_M  ((HOST_SLCHOST_CONF63_V)<<(HOST_SLCHOST_CONF63_S))
-#define HOST_SLCHOST_CONF63_V  0xFF
-#define HOST_SLCHOST_CONF63_S  24
-/* HOST_SLCHOST_CONF62 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF62  0x000000FF
-#define HOST_SLCHOST_CONF62_M  ((HOST_SLCHOST_CONF62_V)<<(HOST_SLCHOST_CONF62_S))
-#define HOST_SLCHOST_CONF62_V  0xFF
-#define HOST_SLCHOST_CONF62_S  16
-/* HOST_SLCHOST_CONF61 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF61  0x000000FF
-#define HOST_SLCHOST_CONF61_M  ((HOST_SLCHOST_CONF61_V)<<(HOST_SLCHOST_CONF61_S))
-#define HOST_SLCHOST_CONF61_V  0xFF
-#define HOST_SLCHOST_CONF61_S  8
-/* HOST_SLCHOST_CONF60 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define HOST_SLCHOST_CONF60  0x000000FF
-#define HOST_SLCHOST_CONF60_M  ((HOST_SLCHOST_CONF60_V)<<(HOST_SLCHOST_CONF60_S))
-#define HOST_SLCHOST_CONF60_V  0xFF
-#define HOST_SLCHOST_CONF60_S  0
-
-#define HOST_SLCHOST_CHECK_SUM0_REG          (DR_REG_SLCHOST_BASE + 0xBC)
-/* HOST_SLCHOST_CHECK_SUM0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLCHOST_CHECK_SUM0  0xFFFFFFFF
-#define HOST_SLCHOST_CHECK_SUM0_M  ((HOST_SLCHOST_CHECK_SUM0_V)<<(HOST_SLCHOST_CHECK_SUM0_S))
-#define HOST_SLCHOST_CHECK_SUM0_V  0xFFFFFFFF
-#define HOST_SLCHOST_CHECK_SUM0_S  0
-
-#define HOST_SLCHOST_CHECK_SUM1_REG          (DR_REG_SLCHOST_BASE + 0xC0)
-/* HOST_SLCHOST_CHECK_SUM1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLCHOST_CHECK_SUM1  0xFFFFFFFF
-#define HOST_SLCHOST_CHECK_SUM1_M  ((HOST_SLCHOST_CHECK_SUM1_V)<<(HOST_SLCHOST_CHECK_SUM1_S))
-#define HOST_SLCHOST_CHECK_SUM1_V  0xFFFFFFFF
-#define HOST_SLCHOST_CHECK_SUM1_S  0
-
-#define HOST_SLC1HOST_TOKEN_RDATA_REG          (DR_REG_SLCHOST_BASE + 0xC4)
-/* HOST_SLC1_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: */
-#define HOST_SLC1_RX_PF_EOF  0x0000000F
-#define HOST_SLC1_RX_PF_EOF_M  ((HOST_SLC1_RX_PF_EOF_V)<<(HOST_SLC1_RX_PF_EOF_S))
-#define HOST_SLC1_RX_PF_EOF_V  0xF
-#define HOST_SLC1_RX_PF_EOF_S  28
-/* HOST_HOSTSLC1_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define HOST_HOSTSLC1_TOKEN1  0x00000FFF
-#define HOST_HOSTSLC1_TOKEN1_M  ((HOST_HOSTSLC1_TOKEN1_V)<<(HOST_HOSTSLC1_TOKEN1_S))
-#define HOST_HOSTSLC1_TOKEN1_V  0xFFF
-#define HOST_HOSTSLC1_TOKEN1_S  16
-/* HOST_SLC1_RX_PF_VALID : RO ;bitpos:[12] ;default: 1'h0 ; */
-/*description: */
-#define HOST_SLC1_RX_PF_VALID  (BIT(12))
-#define HOST_SLC1_RX_PF_VALID_M  (BIT(12))
-#define HOST_SLC1_RX_PF_VALID_V  0x1
-#define HOST_SLC1_RX_PF_VALID_S  12
-/* HOST_SLC1_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0  0x00000FFF
-#define HOST_SLC1_TOKEN0_M  ((HOST_SLC1_TOKEN0_V)<<(HOST_SLC1_TOKEN0_S))
-#define HOST_SLC1_TOKEN0_V  0xFFF
-#define HOST_SLC1_TOKEN0_S  0
-
-#define HOST_SLC0HOST_TOKEN_WDATA_REG          (DR_REG_SLCHOST_BASE + 0xC8)
-/* HOST_SLC0HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN1_WD  0x00000FFF
-#define HOST_SLC0HOST_TOKEN1_WD_M  ((HOST_SLC0HOST_TOKEN1_WD_V)<<(HOST_SLC0HOST_TOKEN1_WD_S))
-#define HOST_SLC0HOST_TOKEN1_WD_V  0xFFF
-#define HOST_SLC0HOST_TOKEN1_WD_S  16
-/* HOST_SLC0HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN0_WD  0x00000FFF
-#define HOST_SLC0HOST_TOKEN0_WD_M  ((HOST_SLC0HOST_TOKEN0_WD_V)<<(HOST_SLC0HOST_TOKEN0_WD_S))
-#define HOST_SLC0HOST_TOKEN0_WD_V  0xFFF
-#define HOST_SLC0HOST_TOKEN0_WD_S  0
-
-#define HOST_SLC1HOST_TOKEN_WDATA_REG          (DR_REG_SLCHOST_BASE + 0xCC)
-/* HOST_SLC1HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define HOST_SLC1HOST_TOKEN1_WD  0x00000FFF
-#define HOST_SLC1HOST_TOKEN1_WD_M  ((HOST_SLC1HOST_TOKEN1_WD_V)<<(HOST_SLC1HOST_TOKEN1_WD_S))
-#define HOST_SLC1HOST_TOKEN1_WD_V  0xFFF
-#define HOST_SLC1HOST_TOKEN1_WD_S  16
-/* HOST_SLC1HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define HOST_SLC1HOST_TOKEN0_WD  0x00000FFF
-#define HOST_SLC1HOST_TOKEN0_WD_M  ((HOST_SLC1HOST_TOKEN0_WD_V)<<(HOST_SLC1HOST_TOKEN0_WD_S))
-#define HOST_SLC1HOST_TOKEN0_WD_V  0xFFF
-#define HOST_SLC1HOST_TOKEN0_WD_S  0
-
-#define HOST_SLCHOST_TOKEN_CON_REG          (DR_REG_SLCHOST_BASE + 0xD0)
-/* HOST_SLC0HOST_LEN_WR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_LEN_WR  (BIT(8))
-#define HOST_SLC0HOST_LEN_WR_M  (BIT(8))
-#define HOST_SLC0HOST_LEN_WR_V  0x1
-#define HOST_SLC0HOST_LEN_WR_S  8
-/* HOST_SLC1HOST_TOKEN1_WR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_TOKEN1_WR  (BIT(7))
-#define HOST_SLC1HOST_TOKEN1_WR_M  (BIT(7))
-#define HOST_SLC1HOST_TOKEN1_WR_V  0x1
-#define HOST_SLC1HOST_TOKEN1_WR_S  7
-/* HOST_SLC1HOST_TOKEN0_WR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_TOKEN0_WR  (BIT(6))
-#define HOST_SLC1HOST_TOKEN0_WR_M  (BIT(6))
-#define HOST_SLC1HOST_TOKEN0_WR_V  0x1
-#define HOST_SLC1HOST_TOKEN0_WR_S  6
-/* HOST_SLC1HOST_TOKEN1_DEC : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_TOKEN1_DEC  (BIT(5))
-#define HOST_SLC1HOST_TOKEN1_DEC_M  (BIT(5))
-#define HOST_SLC1HOST_TOKEN1_DEC_V  0x1
-#define HOST_SLC1HOST_TOKEN1_DEC_S  5
-/* HOST_SLC1HOST_TOKEN0_DEC : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_TOKEN0_DEC  (BIT(4))
-#define HOST_SLC1HOST_TOKEN0_DEC_M  (BIT(4))
-#define HOST_SLC1HOST_TOKEN0_DEC_V  0x1
-#define HOST_SLC1HOST_TOKEN0_DEC_S  4
-/* HOST_SLC0HOST_TOKEN1_WR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN1_WR  (BIT(3))
-#define HOST_SLC0HOST_TOKEN1_WR_M  (BIT(3))
-#define HOST_SLC0HOST_TOKEN1_WR_V  0x1
-#define HOST_SLC0HOST_TOKEN1_WR_S  3
-/* HOST_SLC0HOST_TOKEN0_WR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN0_WR  (BIT(2))
-#define HOST_SLC0HOST_TOKEN0_WR_M  (BIT(2))
-#define HOST_SLC0HOST_TOKEN0_WR_V  0x1
-#define HOST_SLC0HOST_TOKEN0_WR_S  2
-/* HOST_SLC0HOST_TOKEN1_DEC : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN1_DEC  (BIT(1))
-#define HOST_SLC0HOST_TOKEN1_DEC_M  (BIT(1))
-#define HOST_SLC0HOST_TOKEN1_DEC_V  0x1
-#define HOST_SLC0HOST_TOKEN1_DEC_S  1
-/* HOST_SLC0HOST_TOKEN0_DEC : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TOKEN0_DEC  (BIT(0))
-#define HOST_SLC0HOST_TOKEN0_DEC_M  (BIT(0))
-#define HOST_SLC0HOST_TOKEN0_DEC_V  0x1
-#define HOST_SLC0HOST_TOKEN0_DEC_S  0
-
-#define HOST_SLC0HOST_INT_CLR_REG          (DR_REG_SLCHOST_BASE + 0xD4)
-/* HOST_GPIO_SDIO_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_CLR  (BIT(25))
-#define HOST_GPIO_SDIO_INT_CLR_M  (BIT(25))
-#define HOST_GPIO_SDIO_INT_CLR_V  0x1
-#define HOST_GPIO_SDIO_INT_CLR_S  25
-/* HOST_SLC0_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_CLR  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_M  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_V  0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_S  24
-/* HOST_SLC0_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_CLR  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_M  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_V  0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_S  23
-/* HOST_SLC0_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_CLR  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_CLR_M  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_CLR_V  0x1
-#define HOST_SLC0_EXT_BIT3_INT_CLR_S  22
-/* HOST_SLC0_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_CLR  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_CLR_M  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_CLR_V  0x1
-#define HOST_SLC0_EXT_BIT2_INT_CLR_S  21
-/* HOST_SLC0_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_CLR  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_CLR_M  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_CLR_V  0x1
-#define HOST_SLC0_EXT_BIT1_INT_CLR_S  20
-/* HOST_SLC0_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_CLR  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_CLR_M  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_CLR_V  0x1
-#define HOST_SLC0_EXT_BIT0_INT_CLR_S  19
-/* HOST_SLC0_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_CLR  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_CLR_M  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_CLR_V  0x1
-#define HOST_SLC0_RX_PF_VALID_INT_CLR_S  18
-/* HOST_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_CLR  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_CLR_M  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_CLR_V  0x1
-#define HOST_SLC0_TX_OVF_INT_CLR_S  17
-/* HOST_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_CLR  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_CLR_M  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_CLR_V  0x1
-#define HOST_SLC0_RX_UDF_INT_CLR_S  16
-/* HOST_SLC0HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_CLR  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_CLR_M  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_CLR_V  0x1
-#define HOST_SLC0HOST_TX_START_INT_CLR_S  15
-/* HOST_SLC0HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_CLR  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_CLR_M  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_CLR_V  0x1
-#define HOST_SLC0HOST_RX_START_INT_CLR_S  14
-/* HOST_SLC0HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_CLR  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_CLR_M  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_CLR_V  0x1
-#define HOST_SLC0HOST_RX_EOF_INT_CLR_S  13
-/* HOST_SLC0HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_CLR  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_CLR_M  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_CLR_V  0x1
-#define HOST_SLC0HOST_RX_SOF_INT_CLR_S  12
-/* HOST_SLC0_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_CLR  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_M  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_V  0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_S  11
-/* HOST_SLC0_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_CLR  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_M  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_V  0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_S  10
-/* HOST_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_CLR  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_M  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_V  0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_S  9
-/* HOST_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_CLR  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_M  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_V  0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_S  8
-/* HOST_SLC0_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_CLR  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_CLR_M  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_CLR_V  0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_CLR_S  7
-/* HOST_SLC0_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_CLR  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_CLR_M  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_CLR_V  0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_CLR_S  6
-/* HOST_SLC0_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_CLR  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_CLR_M  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_CLR_V  0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_CLR_S  5
-/* HOST_SLC0_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_CLR  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_CLR_M  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_CLR_V  0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_CLR_S  4
-/* HOST_SLC0_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_CLR  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_CLR_M  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_CLR_V  0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_CLR_S  3
-/* HOST_SLC0_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_CLR  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_CLR_M  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_CLR_V  0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_CLR_S  2
-/* HOST_SLC0_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_CLR  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_CLR_M  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_CLR_V  0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_CLR_S  1
-/* HOST_SLC0_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_CLR  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_CLR_M  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_CLR_V  0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_CLR_S  0
-
-#define HOST_SLC1HOST_INT_CLR_REG          (DR_REG_SLCHOST_BASE + 0xD8)
-/* HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V  0x1
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S  25
-/* HOST_SLC1_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_HOST_RD_RETRY_INT_CLR  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_CLR_M  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_CLR_V  0x1
-#define HOST_SLC1_HOST_RD_RETRY_INT_CLR_S  24
-/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V  0x1
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S  23
-/* HOST_SLC1_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT3_INT_CLR  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_CLR_M  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_CLR_V  0x1
-#define HOST_SLC1_EXT_BIT3_INT_CLR_S  22
-/* HOST_SLC1_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT2_INT_CLR  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_CLR_M  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_CLR_V  0x1
-#define HOST_SLC1_EXT_BIT2_INT_CLR_S  21
-/* HOST_SLC1_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT1_INT_CLR  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_CLR_M  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_CLR_V  0x1
-#define HOST_SLC1_EXT_BIT1_INT_CLR_S  20
-/* HOST_SLC1_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT0_INT_CLR  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_CLR_M  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_CLR_V  0x1
-#define HOST_SLC1_EXT_BIT0_INT_CLR_S  19
-/* HOST_SLC1_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_PF_VALID_INT_CLR  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_CLR_M  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_CLR_V  0x1
-#define HOST_SLC1_RX_PF_VALID_INT_CLR_S  18
-/* HOST_SLC1_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TX_OVF_INT_CLR  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_CLR_M  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_CLR_V  0x1
-#define HOST_SLC1_TX_OVF_INT_CLR_S  17
-/* HOST_SLC1_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_UDF_INT_CLR  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_CLR_M  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_CLR_V  0x1
-#define HOST_SLC1_RX_UDF_INT_CLR_S  16
-/* HOST_SLC1HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_TX_START_INT_CLR  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_CLR_M  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_CLR_V  0x1
-#define HOST_SLC1HOST_TX_START_INT_CLR_S  15
-/* HOST_SLC1HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_START_INT_CLR  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_CLR_M  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_CLR_V  0x1
-#define HOST_SLC1HOST_RX_START_INT_CLR_S  14
-/* HOST_SLC1HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_EOF_INT_CLR  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_CLR_M  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_CLR_V  0x1
-#define HOST_SLC1HOST_RX_EOF_INT_CLR_S  13
-/* HOST_SLC1HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_SOF_INT_CLR  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_CLR_M  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_CLR_V  0x1
-#define HOST_SLC1HOST_RX_SOF_INT_CLR_S  12
-/* HOST_SLC1_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_0TO1_INT_CLR  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_CLR_M  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_CLR_V  0x1
-#define HOST_SLC1_TOKEN1_0TO1_INT_CLR_S  11
-/* HOST_SLC1_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_0TO1_INT_CLR  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_CLR_M  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_CLR_V  0x1
-#define HOST_SLC1_TOKEN0_0TO1_INT_CLR_S  10
-/* HOST_SLC1_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_1TO0_INT_CLR  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_CLR_M  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_CLR_V  0x1
-#define HOST_SLC1_TOKEN1_1TO0_INT_CLR_S  9
-/* HOST_SLC1_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_1TO0_INT_CLR  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_CLR_M  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_CLR_V  0x1
-#define HOST_SLC1_TOKEN0_1TO0_INT_CLR_S  8
-/* HOST_SLC1_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT7_INT_CLR  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_CLR_M  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_CLR_V  0x1
-#define HOST_SLC1_TOHOST_BIT7_INT_CLR_S  7
-/* HOST_SLC1_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT6_INT_CLR  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_CLR_M  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_CLR_V  0x1
-#define HOST_SLC1_TOHOST_BIT6_INT_CLR_S  6
-/* HOST_SLC1_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT5_INT_CLR  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_CLR_M  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_CLR_V  0x1
-#define HOST_SLC1_TOHOST_BIT5_INT_CLR_S  5
-/* HOST_SLC1_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT4_INT_CLR  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_CLR_M  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_CLR_V  0x1
-#define HOST_SLC1_TOHOST_BIT4_INT_CLR_S  4
-/* HOST_SLC1_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT3_INT_CLR  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_CLR_M  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_CLR_V  0x1
-#define HOST_SLC1_TOHOST_BIT3_INT_CLR_S  3
-/* HOST_SLC1_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT2_INT_CLR  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_CLR_M  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_CLR_V  0x1
-#define HOST_SLC1_TOHOST_BIT2_INT_CLR_S  2
-/* HOST_SLC1_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT1_INT_CLR  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_CLR_M  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_CLR_V  0x1
-#define HOST_SLC1_TOHOST_BIT1_INT_CLR_S  1
-/* HOST_SLC1_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT0_INT_CLR  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_CLR_M  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_CLR_V  0x1
-#define HOST_SLC1_TOHOST_BIT0_INT_CLR_S  0
-
-#define HOST_SLC0HOST_FUNC1_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xDC)
-/* HOST_FN1_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_GPIO_SDIO_INT_ENA  (BIT(25))
-#define HOST_FN1_GPIO_SDIO_INT_ENA_M  (BIT(25))
-#define HOST_FN1_GPIO_SDIO_INT_ENA_V  0x1
-#define HOST_FN1_GPIO_SDIO_INT_ENA_S  25
-/* HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA  (BIT(24))
-#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
-#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S  24
-/* HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA  (BIT(23))
-#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
-#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S  23
-/* HOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA  (BIT(22))
-#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_M  (BIT(22))
-#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S  22
-/* HOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA  (BIT(21))
-#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M  (BIT(21))
-#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S  21
-/* HOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA  (BIT(20))
-#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_M  (BIT(20))
-#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S  20
-/* HOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA  (BIT(19))
-#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_M  (BIT(19))
-#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S  19
-/* HOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA  (BIT(18))
-#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M  (BIT(18))
-#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S  18
-/* HOST_FN1_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TX_OVF_INT_ENA  (BIT(17))
-#define HOST_FN1_SLC0_TX_OVF_INT_ENA_M  (BIT(17))
-#define HOST_FN1_SLC0_TX_OVF_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TX_OVF_INT_ENA_S  17
-/* HOST_FN1_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_RX_UDF_INT_ENA  (BIT(16))
-#define HOST_FN1_SLC0_RX_UDF_INT_ENA_M  (BIT(16))
-#define HOST_FN1_SLC0_RX_UDF_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_RX_UDF_INT_ENA_S  16
-/* HOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0HOST_TX_START_INT_ENA  (BIT(15))
-#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_M  (BIT(15))
-#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_V  0x1
-#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_S  15
-/* HOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0HOST_RX_START_INT_ENA  (BIT(14))
-#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_M  (BIT(14))
-#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_V  0x1
-#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_S  14
-/* HOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA  (BIT(13))
-#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M  (BIT(13))
-#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V  0x1
-#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S  13
-/* HOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA  (BIT(12))
-#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M  (BIT(12))
-#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V  0x1
-#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S  12
-/* HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA  (BIT(11))
-#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
-#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S  11
-/* HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA  (BIT(10))
-#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
-#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S  10
-/* HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA  (BIT(9))
-#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
-#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S  9
-/* HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA  (BIT(8))
-#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
-#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S  8
-/* HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA  (BIT(7))
-#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M  (BIT(7))
-#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S  7
-/* HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA  (BIT(6))
-#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M  (BIT(6))
-#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S  6
-/* HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA  (BIT(5))
-#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M  (BIT(5))
-#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S  5
-/* HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA  (BIT(4))
-#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M  (BIT(4))
-#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S  4
-/* HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA  (BIT(3))
-#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M  (BIT(3))
-#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S  3
-/* HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA  (BIT(2))
-#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M  (BIT(2))
-#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S  2
-/* HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA  (BIT(1))
-#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M  (BIT(1))
-#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S  1
-/* HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA  (BIT(0))
-#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M  (BIT(0))
-#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V  0x1
-#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S  0
-
-#define HOST_SLC1HOST_FUNC1_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xE0)
-/* HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA  (BIT(25))
-#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (BIT(25))
-#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
-/* HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA  (BIT(24))
-#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
-#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S  24
-/* HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA  (BIT(23))
-#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
-#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
-/* HOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA  (BIT(22))
-#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA_M  (BIT(22))
-#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA_S  22
-/* HOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA  (BIT(21))
-#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA_M  (BIT(21))
-#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA_S  21
-/* HOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA  (BIT(20))
-#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA_M  (BIT(20))
-#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA_S  20
-/* HOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA  (BIT(19))
-#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA_M  (BIT(19))
-#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA_S  19
-/* HOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA  (BIT(18))
-#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M  (BIT(18))
-#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S  18
-/* HOST_FN1_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TX_OVF_INT_ENA  (BIT(17))
-#define HOST_FN1_SLC1_TX_OVF_INT_ENA_M  (BIT(17))
-#define HOST_FN1_SLC1_TX_OVF_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TX_OVF_INT_ENA_S  17
-/* HOST_FN1_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_RX_UDF_INT_ENA  (BIT(16))
-#define HOST_FN1_SLC1_RX_UDF_INT_ENA_M  (BIT(16))
-#define HOST_FN1_SLC1_RX_UDF_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_RX_UDF_INT_ENA_S  16
-/* HOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1HOST_TX_START_INT_ENA  (BIT(15))
-#define HOST_FN1_SLC1HOST_TX_START_INT_ENA_M  (BIT(15))
-#define HOST_FN1_SLC1HOST_TX_START_INT_ENA_V  0x1
-#define HOST_FN1_SLC1HOST_TX_START_INT_ENA_S  15
-/* HOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1HOST_RX_START_INT_ENA  (BIT(14))
-#define HOST_FN1_SLC1HOST_RX_START_INT_ENA_M  (BIT(14))
-#define HOST_FN1_SLC1HOST_RX_START_INT_ENA_V  0x1
-#define HOST_FN1_SLC1HOST_RX_START_INT_ENA_S  14
-/* HOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA  (BIT(13))
-#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M  (BIT(13))
-#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V  0x1
-#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S  13
-/* HOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA  (BIT(12))
-#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M  (BIT(12))
-#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V  0x1
-#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S  12
-/* HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA  (BIT(11))
-#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
-#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S  11
-/* HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA  (BIT(10))
-#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
-#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S  10
-/* HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA  (BIT(9))
-#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
-#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S  9
-/* HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA  (BIT(8))
-#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
-#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S  8
-/* HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA  (BIT(7))
-#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M  (BIT(7))
-#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S  7
-/* HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA  (BIT(6))
-#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M  (BIT(6))
-#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S  6
-/* HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA  (BIT(5))
-#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M  (BIT(5))
-#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S  5
-/* HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA  (BIT(4))
-#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M  (BIT(4))
-#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S  4
-/* HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA  (BIT(3))
-#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M  (BIT(3))
-#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S  3
-/* HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA  (BIT(2))
-#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M  (BIT(2))
-#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S  2
-/* HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA  (BIT(1))
-#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M  (BIT(1))
-#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S  1
-/* HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA  (BIT(0))
-#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M  (BIT(0))
-#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V  0x1
-#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S  0
-
-#define HOST_SLC0HOST_FUNC2_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xE4)
-/* HOST_FN2_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_GPIO_SDIO_INT_ENA  (BIT(25))
-#define HOST_FN2_GPIO_SDIO_INT_ENA_M  (BIT(25))
-#define HOST_FN2_GPIO_SDIO_INT_ENA_V  0x1
-#define HOST_FN2_GPIO_SDIO_INT_ENA_S  25
-/* HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA  (BIT(24))
-#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
-#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S  24
-/* HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA  (BIT(23))
-#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
-#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S  23
-/* HOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA  (BIT(22))
-#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA_M  (BIT(22))
-#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA_S  22
-/* HOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA  (BIT(21))
-#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA_M  (BIT(21))
-#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA_S  21
-/* HOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA  (BIT(20))
-#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA_M  (BIT(20))
-#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA_S  20
-/* HOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA  (BIT(19))
-#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA_M  (BIT(19))
-#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA_S  19
-/* HOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA  (BIT(18))
-#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M  (BIT(18))
-#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S  18
-/* HOST_FN2_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TX_OVF_INT_ENA  (BIT(17))
-#define HOST_FN2_SLC0_TX_OVF_INT_ENA_M  (BIT(17))
-#define HOST_FN2_SLC0_TX_OVF_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TX_OVF_INT_ENA_S  17
-/* HOST_FN2_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_RX_UDF_INT_ENA  (BIT(16))
-#define HOST_FN2_SLC0_RX_UDF_INT_ENA_M  (BIT(16))
-#define HOST_FN2_SLC0_RX_UDF_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_RX_UDF_INT_ENA_S  16
-/* HOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0HOST_TX_START_INT_ENA  (BIT(15))
-#define HOST_FN2_SLC0HOST_TX_START_INT_ENA_M  (BIT(15))
-#define HOST_FN2_SLC0HOST_TX_START_INT_ENA_V  0x1
-#define HOST_FN2_SLC0HOST_TX_START_INT_ENA_S  15
-/* HOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0HOST_RX_START_INT_ENA  (BIT(14))
-#define HOST_FN2_SLC0HOST_RX_START_INT_ENA_M  (BIT(14))
-#define HOST_FN2_SLC0HOST_RX_START_INT_ENA_V  0x1
-#define HOST_FN2_SLC0HOST_RX_START_INT_ENA_S  14
-/* HOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA  (BIT(13))
-#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M  (BIT(13))
-#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V  0x1
-#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S  13
-/* HOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA  (BIT(12))
-#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M  (BIT(12))
-#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V  0x1
-#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S  12
-/* HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA  (BIT(11))
-#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
-#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S  11
-/* HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA  (BIT(10))
-#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
-#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S  10
-/* HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA  (BIT(9))
-#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
-#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S  9
-/* HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA  (BIT(8))
-#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
-#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S  8
-/* HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA  (BIT(7))
-#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M  (BIT(7))
-#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S  7
-/* HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA  (BIT(6))
-#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M  (BIT(6))
-#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S  6
-/* HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA  (BIT(5))
-#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M  (BIT(5))
-#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S  5
-/* HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA  (BIT(4))
-#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M  (BIT(4))
-#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S  4
-/* HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA  (BIT(3))
-#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M  (BIT(3))
-#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S  3
-/* HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA  (BIT(2))
-#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M  (BIT(2))
-#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S  2
-/* HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA  (BIT(1))
-#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M  (BIT(1))
-#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S  1
-/* HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA  (BIT(0))
-#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M  (BIT(0))
-#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V  0x1
-#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S  0
-
-#define HOST_SLC1HOST_FUNC2_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xE8)
-/* HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA  (BIT(25))
-#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (BIT(25))
-#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
-/* HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA  (BIT(24))
-#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
-#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S  24
-/* HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA  (BIT(23))
-#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
-#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
-/* HOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA  (BIT(22))
-#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA_M  (BIT(22))
-#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA_S  22
-/* HOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA  (BIT(21))
-#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA_M  (BIT(21))
-#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA_S  21
-/* HOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA  (BIT(20))
-#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA_M  (BIT(20))
-#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA_S  20
-/* HOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA  (BIT(19))
-#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA_M  (BIT(19))
-#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA_S  19
-/* HOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA  (BIT(18))
-#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M  (BIT(18))
-#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S  18
-/* HOST_FN2_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TX_OVF_INT_ENA  (BIT(17))
-#define HOST_FN2_SLC1_TX_OVF_INT_ENA_M  (BIT(17))
-#define HOST_FN2_SLC1_TX_OVF_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TX_OVF_INT_ENA_S  17
-/* HOST_FN2_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_RX_UDF_INT_ENA  (BIT(16))
-#define HOST_FN2_SLC1_RX_UDF_INT_ENA_M  (BIT(16))
-#define HOST_FN2_SLC1_RX_UDF_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_RX_UDF_INT_ENA_S  16
-/* HOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1HOST_TX_START_INT_ENA  (BIT(15))
-#define HOST_FN2_SLC1HOST_TX_START_INT_ENA_M  (BIT(15))
-#define HOST_FN2_SLC1HOST_TX_START_INT_ENA_V  0x1
-#define HOST_FN2_SLC1HOST_TX_START_INT_ENA_S  15
-/* HOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1HOST_RX_START_INT_ENA  (BIT(14))
-#define HOST_FN2_SLC1HOST_RX_START_INT_ENA_M  (BIT(14))
-#define HOST_FN2_SLC1HOST_RX_START_INT_ENA_V  0x1
-#define HOST_FN2_SLC1HOST_RX_START_INT_ENA_S  14
-/* HOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA  (BIT(13))
-#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M  (BIT(13))
-#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V  0x1
-#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S  13
-/* HOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA  (BIT(12))
-#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M  (BIT(12))
-#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V  0x1
-#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S  12
-/* HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA  (BIT(11))
-#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
-#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S  11
-/* HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA  (BIT(10))
-#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
-#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S  10
-/* HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA  (BIT(9))
-#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
-#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S  9
-/* HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA  (BIT(8))
-#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
-#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S  8
-/* HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA  (BIT(7))
-#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M  (BIT(7))
-#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S  7
-/* HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA  (BIT(6))
-#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M  (BIT(6))
-#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S  6
-/* HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA  (BIT(5))
-#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M  (BIT(5))
-#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S  5
-/* HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA  (BIT(4))
-#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M  (BIT(4))
-#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S  4
-/* HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA  (BIT(3))
-#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M  (BIT(3))
-#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S  3
-/* HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA  (BIT(2))
-#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M  (BIT(2))
-#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S  2
-/* HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA  (BIT(1))
-#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M  (BIT(1))
-#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S  1
-/* HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA  (BIT(0))
-#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M  (BIT(0))
-#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V  0x1
-#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S  0
-
-#define HOST_SLC0HOST_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xEC)
-/* HOST_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_ENA  (BIT(25))
-#define HOST_GPIO_SDIO_INT_ENA_M  (BIT(25))
-#define HOST_GPIO_SDIO_INT_ENA_V  0x1
-#define HOST_GPIO_SDIO_INT_ENA_S  25
-/* HOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_V  0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_S  24
-/* HOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_V  0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_S  23
-/* HOST_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_ENA  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ENA_M  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ENA_V  0x1
-#define HOST_SLC0_EXT_BIT3_INT_ENA_S  22
-/* HOST_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_ENA  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ENA_M  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ENA_V  0x1
-#define HOST_SLC0_EXT_BIT2_INT_ENA_S  21
-/* HOST_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_ENA  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ENA_M  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ENA_V  0x1
-#define HOST_SLC0_EXT_BIT1_INT_ENA_S  20
-/* HOST_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_ENA  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ENA_M  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ENA_V  0x1
-#define HOST_SLC0_EXT_BIT0_INT_ENA_S  19
-/* HOST_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_ENA  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ENA_M  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ENA_V  0x1
-#define HOST_SLC0_RX_PF_VALID_INT_ENA_S  18
-/* HOST_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_ENA  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ENA_M  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ENA_V  0x1
-#define HOST_SLC0_TX_OVF_INT_ENA_S  17
-/* HOST_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_ENA  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ENA_M  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ENA_V  0x1
-#define HOST_SLC0_RX_UDF_INT_ENA_S  16
-/* HOST_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_ENA  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ENA_M  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ENA_V  0x1
-#define HOST_SLC0HOST_TX_START_INT_ENA_S  15
-/* HOST_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_ENA  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ENA_M  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ENA_V  0x1
-#define HOST_SLC0HOST_RX_START_INT_ENA_S  14
-/* HOST_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_ENA  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ENA_M  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ENA_V  0x1
-#define HOST_SLC0HOST_RX_EOF_INT_ENA_S  13
-/* HOST_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_ENA  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ENA_M  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ENA_V  0x1
-#define HOST_SLC0HOST_RX_SOF_INT_ENA_S  12
-/* HOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_V  0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_S  11
-/* HOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_V  0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_S  10
-/* HOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_S  9
-/* HOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_S  8
-/* HOST_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA_M  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA_V  0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA_S  7
-/* HOST_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA_M  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA_V  0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA_S  6
-/* HOST_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA_M  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA_V  0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA_S  5
-/* HOST_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA_M  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA_V  0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA_S  4
-/* HOST_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA_M  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA_V  0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA_S  3
-/* HOST_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA_M  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA_V  0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA_S  2
-/* HOST_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA_M  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA_V  0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA_S  1
-/* HOST_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA_M  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA_V  0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA_S  0
-
-#define HOST_SLC1HOST_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xF0)
-/* HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V  0x1
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S  25
-/* HOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_HOST_RD_RETRY_INT_ENA  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_ENA_V  0x1
-#define HOST_SLC1_HOST_RD_RETRY_INT_ENA_S  24
-/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V  0x1
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S  23
-/* HOST_SLC1_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT3_INT_ENA  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_ENA_M  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_ENA_V  0x1
-#define HOST_SLC1_EXT_BIT3_INT_ENA_S  22
-/* HOST_SLC1_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT2_INT_ENA  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_ENA_M  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_ENA_V  0x1
-#define HOST_SLC1_EXT_BIT2_INT_ENA_S  21
-/* HOST_SLC1_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT1_INT_ENA  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_ENA_M  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_ENA_V  0x1
-#define HOST_SLC1_EXT_BIT1_INT_ENA_S  20
-/* HOST_SLC1_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT0_INT_ENA  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_ENA_M  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_ENA_V  0x1
-#define HOST_SLC1_EXT_BIT0_INT_ENA_S  19
-/* HOST_SLC1_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_PF_VALID_INT_ENA  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_ENA_M  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_ENA_V  0x1
-#define HOST_SLC1_RX_PF_VALID_INT_ENA_S  18
-/* HOST_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TX_OVF_INT_ENA  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_ENA_M  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_ENA_V  0x1
-#define HOST_SLC1_TX_OVF_INT_ENA_S  17
-/* HOST_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_UDF_INT_ENA  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_ENA_M  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_ENA_V  0x1
-#define HOST_SLC1_RX_UDF_INT_ENA_S  16
-/* HOST_SLC1HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_TX_START_INT_ENA  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_ENA_M  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_ENA_V  0x1
-#define HOST_SLC1HOST_TX_START_INT_ENA_S  15
-/* HOST_SLC1HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_START_INT_ENA  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_ENA_M  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_ENA_V  0x1
-#define HOST_SLC1HOST_RX_START_INT_ENA_S  14
-/* HOST_SLC1HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_EOF_INT_ENA  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_ENA_M  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_ENA_V  0x1
-#define HOST_SLC1HOST_RX_EOF_INT_ENA_S  13
-/* HOST_SLC1HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_SOF_INT_ENA  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_ENA_M  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_ENA_V  0x1
-#define HOST_SLC1HOST_RX_SOF_INT_ENA_S  12
-/* HOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_0TO1_INT_ENA  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_ENA_V  0x1
-#define HOST_SLC1_TOKEN1_0TO1_INT_ENA_S  11
-/* HOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_0TO1_INT_ENA  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_ENA_V  0x1
-#define HOST_SLC1_TOKEN0_0TO1_INT_ENA_S  10
-/* HOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_1TO0_INT_ENA  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_ENA_V  0x1
-#define HOST_SLC1_TOKEN1_1TO0_INT_ENA_S  9
-/* HOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_1TO0_INT_ENA  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_ENA_V  0x1
-#define HOST_SLC1_TOKEN0_1TO0_INT_ENA_S  8
-/* HOST_SLC1_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT7_INT_ENA  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_ENA_M  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_ENA_V  0x1
-#define HOST_SLC1_TOHOST_BIT7_INT_ENA_S  7
-/* HOST_SLC1_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT6_INT_ENA  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_ENA_M  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_ENA_V  0x1
-#define HOST_SLC1_TOHOST_BIT6_INT_ENA_S  6
-/* HOST_SLC1_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT5_INT_ENA  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_ENA_M  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_ENA_V  0x1
-#define HOST_SLC1_TOHOST_BIT5_INT_ENA_S  5
-/* HOST_SLC1_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT4_INT_ENA  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_ENA_M  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_ENA_V  0x1
-#define HOST_SLC1_TOHOST_BIT4_INT_ENA_S  4
-/* HOST_SLC1_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT3_INT_ENA  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_ENA_M  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_ENA_V  0x1
-#define HOST_SLC1_TOHOST_BIT3_INT_ENA_S  3
-/* HOST_SLC1_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT2_INT_ENA  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_ENA_M  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_ENA_V  0x1
-#define HOST_SLC1_TOHOST_BIT2_INT_ENA_S  2
-/* HOST_SLC1_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT1_INT_ENA  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_ENA_M  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_ENA_V  0x1
-#define HOST_SLC1_TOHOST_BIT1_INT_ENA_S  1
-/* HOST_SLC1_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT0_INT_ENA  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_ENA_M  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_ENA_V  0x1
-#define HOST_SLC1_TOHOST_BIT0_INT_ENA_S  0
-
-#define HOST_SLC0HOST_RX_INFOR_REG          (DR_REG_SLCHOST_BASE + 0xF4)
-/* HOST_SLC0HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_INFOR  0x000FFFFF
-#define HOST_SLC0HOST_RX_INFOR_M  ((HOST_SLC0HOST_RX_INFOR_V)<<(HOST_SLC0HOST_RX_INFOR_S))
-#define HOST_SLC0HOST_RX_INFOR_V  0xFFFFF
-#define HOST_SLC0HOST_RX_INFOR_S  0
-
-#define HOST_SLC1HOST_RX_INFOR_REG          (DR_REG_SLCHOST_BASE + 0xF8)
-/* HOST_SLC1HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_INFOR  0x000FFFFF
-#define HOST_SLC1HOST_RX_INFOR_M  ((HOST_SLC1HOST_RX_INFOR_V)<<(HOST_SLC1HOST_RX_INFOR_S))
-#define HOST_SLC1HOST_RX_INFOR_V  0xFFFFF
-#define HOST_SLC1HOST_RX_INFOR_S  0
-
-#define HOST_SLC0HOST_LEN_WD_REG          (DR_REG_SLCHOST_BASE + 0xFC)
-/* HOST_SLC0HOST_LEN_WD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_LEN_WD  0xFFFFFFFF
-#define HOST_SLC0HOST_LEN_WD_M  ((HOST_SLC0HOST_LEN_WD_V)<<(HOST_SLC0HOST_LEN_WD_S))
-#define HOST_SLC0HOST_LEN_WD_V  0xFFFFFFFF
-#define HOST_SLC0HOST_LEN_WD_S  0
-
-#define HOST_SLC_APBWIN_WDATA_REG          (DR_REG_SLCHOST_BASE + 0x100)
-/* HOST_SLC_APBWIN_WDATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_WDATA  0xFFFFFFFF
-#define HOST_SLC_APBWIN_WDATA_M  ((HOST_SLC_APBWIN_WDATA_V)<<(HOST_SLC_APBWIN_WDATA_S))
-#define HOST_SLC_APBWIN_WDATA_V  0xFFFFFFFF
-#define HOST_SLC_APBWIN_WDATA_S  0
-
-#define HOST_SLC_APBWIN_CONF_REG          (DR_REG_SLCHOST_BASE + 0x104)
-/* HOST_SLC_APBWIN_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_START  (BIT(29))
-#define HOST_SLC_APBWIN_START_M  (BIT(29))
-#define HOST_SLC_APBWIN_START_V  0x1
-#define HOST_SLC_APBWIN_START_S  29
-/* HOST_SLC_APBWIN_WR : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_WR  (BIT(28))
-#define HOST_SLC_APBWIN_WR_M  (BIT(28))
-#define HOST_SLC_APBWIN_WR_V  0x1
-#define HOST_SLC_APBWIN_WR_S  28
-/* HOST_SLC_APBWIN_ADDR : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_ADDR  0x0FFFFFFF
-#define HOST_SLC_APBWIN_ADDR_M  ((HOST_SLC_APBWIN_ADDR_V)<<(HOST_SLC_APBWIN_ADDR_S))
-#define HOST_SLC_APBWIN_ADDR_V  0xFFFFFFF
-#define HOST_SLC_APBWIN_ADDR_S  0
-
-#define HOST_SLC_APBWIN_RDATA_REG          (DR_REG_SLCHOST_BASE + 0x108)
-/* HOST_SLC_APBWIN_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define HOST_SLC_APBWIN_RDATA  0xFFFFFFFF
-#define HOST_SLC_APBWIN_RDATA_M  ((HOST_SLC_APBWIN_RDATA_V)<<(HOST_SLC_APBWIN_RDATA_S))
-#define HOST_SLC_APBWIN_RDATA_V  0xFFFFFFFF
-#define HOST_SLC_APBWIN_RDATA_S  0
-
-#define HOST_SLCHOST_RDCLR0_REG          (DR_REG_SLCHOST_BASE + 0x10C)
-/* HOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */
-/*description: */
-#define HOST_SLCHOST_SLC0_BIT6_CLRADDR  0x000001FF
-#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_M  ((HOST_SLCHOST_SLC0_BIT6_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT6_CLRADDR_S))
-#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_V  0x1FF
-#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_S  9
-/* HOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h44 ; */
-/*description: */
-#define HOST_SLCHOST_SLC0_BIT7_CLRADDR  0x000001FF
-#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_M  ((HOST_SLCHOST_SLC0_BIT7_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT7_CLRADDR_S))
-#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_V  0x1FF
-#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_S  0
-
-#define HOST_SLCHOST_RDCLR1_REG          (DR_REG_SLCHOST_BASE + 0x110)
-/* HOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */
-/*description: */
-#define HOST_SLCHOST_SLC1_BIT6_CLRADDR  0x000001FF
-#define HOST_SLCHOST_SLC1_BIT6_CLRADDR_M  ((HOST_SLCHOST_SLC1_BIT6_CLRADDR_V)<<(HOST_SLCHOST_SLC1_BIT6_CLRADDR_S))
-#define HOST_SLCHOST_SLC1_BIT6_CLRADDR_V  0x1FF
-#define HOST_SLCHOST_SLC1_BIT6_CLRADDR_S  9
-/* HOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h1e0 ; */
-/*description: */
-#define HOST_SLCHOST_SLC1_BIT7_CLRADDR  0x000001FF
-#define HOST_SLCHOST_SLC1_BIT7_CLRADDR_M  ((HOST_SLCHOST_SLC1_BIT7_CLRADDR_V)<<(HOST_SLCHOST_SLC1_BIT7_CLRADDR_S))
-#define HOST_SLCHOST_SLC1_BIT7_CLRADDR_V  0x1FF
-#define HOST_SLCHOST_SLC1_BIT7_CLRADDR_S  0
-
-#define HOST_SLC0HOST_INT_ENA1_REG          (DR_REG_SLCHOST_BASE + 0x114)
-/* HOST_GPIO_SDIO_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_GPIO_SDIO_INT_ENA1  (BIT(25))
-#define HOST_GPIO_SDIO_INT_ENA1_M  (BIT(25))
-#define HOST_GPIO_SDIO_INT_ENA1_V  0x1
-#define HOST_GPIO_SDIO_INT_ENA1_S  25
-/* HOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_M  (BIT(24))
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V  0x1
-#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S  24
-/* HOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_M  (BIT(23))
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V  0x1
-#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S  23
-/* HOST_SLC0_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT3_INT_ENA1  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ENA1_M  (BIT(22))
-#define HOST_SLC0_EXT_BIT3_INT_ENA1_V  0x1
-#define HOST_SLC0_EXT_BIT3_INT_ENA1_S  22
-/* HOST_SLC0_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT2_INT_ENA1  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ENA1_M  (BIT(21))
-#define HOST_SLC0_EXT_BIT2_INT_ENA1_V  0x1
-#define HOST_SLC0_EXT_BIT2_INT_ENA1_S  21
-/* HOST_SLC0_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT1_INT_ENA1  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ENA1_M  (BIT(20))
-#define HOST_SLC0_EXT_BIT1_INT_ENA1_V  0x1
-#define HOST_SLC0_EXT_BIT1_INT_ENA1_S  20
-/* HOST_SLC0_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_EXT_BIT0_INT_ENA1  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ENA1_M  (BIT(19))
-#define HOST_SLC0_EXT_BIT0_INT_ENA1_V  0x1
-#define HOST_SLC0_EXT_BIT0_INT_ENA1_S  19
-/* HOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_PF_VALID_INT_ENA1  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ENA1_M  (BIT(18))
-#define HOST_SLC0_RX_PF_VALID_INT_ENA1_V  0x1
-#define HOST_SLC0_RX_PF_VALID_INT_ENA1_S  18
-/* HOST_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TX_OVF_INT_ENA1  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ENA1_M  (BIT(17))
-#define HOST_SLC0_TX_OVF_INT_ENA1_V  0x1
-#define HOST_SLC0_TX_OVF_INT_ENA1_S  17
-/* HOST_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_RX_UDF_INT_ENA1  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ENA1_M  (BIT(16))
-#define HOST_SLC0_RX_UDF_INT_ENA1_V  0x1
-#define HOST_SLC0_RX_UDF_INT_ENA1_S  16
-/* HOST_SLC0HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_TX_START_INT_ENA1  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ENA1_M  (BIT(15))
-#define HOST_SLC0HOST_TX_START_INT_ENA1_V  0x1
-#define HOST_SLC0HOST_TX_START_INT_ENA1_S  15
-/* HOST_SLC0HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_START_INT_ENA1  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ENA1_M  (BIT(14))
-#define HOST_SLC0HOST_RX_START_INT_ENA1_V  0x1
-#define HOST_SLC0HOST_RX_START_INT_ENA1_S  14
-/* HOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_EOF_INT_ENA1  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ENA1_M  (BIT(13))
-#define HOST_SLC0HOST_RX_EOF_INT_ENA1_V  0x1
-#define HOST_SLC0HOST_RX_EOF_INT_ENA1_S  13
-/* HOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0HOST_RX_SOF_INT_ENA1  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ENA1_M  (BIT(12))
-#define HOST_SLC0HOST_RX_SOF_INT_ENA1_V  0x1
-#define HOST_SLC0HOST_RX_SOF_INT_ENA1_S  12
-/* HOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_M  (BIT(11))
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V  0x1
-#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S  11
-/* HOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_M  (BIT(10))
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V  0x1
-#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S  10
-/* HOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M  (BIT(9))
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x1
-#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S  9
-/* HOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_M  (BIT(8))
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x1
-#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S  8
-/* HOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA1  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_M  (BIT(7))
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_V  0x1
-#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_S  7
-/* HOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA1  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_M  (BIT(6))
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_V  0x1
-#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_S  6
-/* HOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA1  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_M  (BIT(5))
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_V  0x1
-#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_S  5
-/* HOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA1  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_M  (BIT(4))
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_V  0x1
-#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_S  4
-/* HOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA1  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_M  (BIT(3))
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_V  0x1
-#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_S  3
-/* HOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA1  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_M  (BIT(2))
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_V  0x1
-#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_S  2
-/* HOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA1  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_M  (BIT(1))
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_V  0x1
-#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_S  1
-/* HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA1  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_M  (BIT(0))
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_V  0x1
-#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_S  0
-
-#define HOST_SLC1HOST_INT_ENA1_REG          (DR_REG_SLCHOST_BASE + 0x118)
-/* HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M  (BIT(25))
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V  0x1
-#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S  25
-/* HOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1_M  (BIT(24))
-#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1_V  0x1
-#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1_S  24
-/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M  (BIT(23))
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V  0x1
-#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S  23
-/* HOST_SLC1_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT3_INT_ENA1  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_ENA1_M  (BIT(22))
-#define HOST_SLC1_EXT_BIT3_INT_ENA1_V  0x1
-#define HOST_SLC1_EXT_BIT3_INT_ENA1_S  22
-/* HOST_SLC1_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT2_INT_ENA1  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_ENA1_M  (BIT(21))
-#define HOST_SLC1_EXT_BIT2_INT_ENA1_V  0x1
-#define HOST_SLC1_EXT_BIT2_INT_ENA1_S  21
-/* HOST_SLC1_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT1_INT_ENA1  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_ENA1_M  (BIT(20))
-#define HOST_SLC1_EXT_BIT1_INT_ENA1_V  0x1
-#define HOST_SLC1_EXT_BIT1_INT_ENA1_S  20
-/* HOST_SLC1_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_EXT_BIT0_INT_ENA1  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_ENA1_M  (BIT(19))
-#define HOST_SLC1_EXT_BIT0_INT_ENA1_V  0x1
-#define HOST_SLC1_EXT_BIT0_INT_ENA1_S  19
-/* HOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_PF_VALID_INT_ENA1  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_ENA1_M  (BIT(18))
-#define HOST_SLC1_RX_PF_VALID_INT_ENA1_V  0x1
-#define HOST_SLC1_RX_PF_VALID_INT_ENA1_S  18
-/* HOST_SLC1_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TX_OVF_INT_ENA1  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_ENA1_M  (BIT(17))
-#define HOST_SLC1_TX_OVF_INT_ENA1_V  0x1
-#define HOST_SLC1_TX_OVF_INT_ENA1_S  17
-/* HOST_SLC1_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_RX_UDF_INT_ENA1  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_ENA1_M  (BIT(16))
-#define HOST_SLC1_RX_UDF_INT_ENA1_V  0x1
-#define HOST_SLC1_RX_UDF_INT_ENA1_S  16
-/* HOST_SLC1HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_TX_START_INT_ENA1  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_ENA1_M  (BIT(15))
-#define HOST_SLC1HOST_TX_START_INT_ENA1_V  0x1
-#define HOST_SLC1HOST_TX_START_INT_ENA1_S  15
-/* HOST_SLC1HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_START_INT_ENA1  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_ENA1_M  (BIT(14))
-#define HOST_SLC1HOST_RX_START_INT_ENA1_V  0x1
-#define HOST_SLC1HOST_RX_START_INT_ENA1_S  14
-/* HOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_EOF_INT_ENA1  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_ENA1_M  (BIT(13))
-#define HOST_SLC1HOST_RX_EOF_INT_ENA1_V  0x1
-#define HOST_SLC1HOST_RX_EOF_INT_ENA1_S  13
-/* HOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1HOST_RX_SOF_INT_ENA1  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_ENA1_M  (BIT(12))
-#define HOST_SLC1HOST_RX_SOF_INT_ENA1_V  0x1
-#define HOST_SLC1HOST_RX_SOF_INT_ENA1_S  12
-/* HOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1_M  (BIT(11))
-#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1_V  0x1
-#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1_S  11
-/* HOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1_M  (BIT(10))
-#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1_V  0x1
-#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1_S  10
-/* HOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1_M  (BIT(9))
-#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1_V  0x1
-#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1_S  9
-/* HOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1_M  (BIT(8))
-#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1_V  0x1
-#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1_S  8
-/* HOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT7_INT_ENA1  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_ENA1_M  (BIT(7))
-#define HOST_SLC1_TOHOST_BIT7_INT_ENA1_V  0x1
-#define HOST_SLC1_TOHOST_BIT7_INT_ENA1_S  7
-/* HOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT6_INT_ENA1  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_ENA1_M  (BIT(6))
-#define HOST_SLC1_TOHOST_BIT6_INT_ENA1_V  0x1
-#define HOST_SLC1_TOHOST_BIT6_INT_ENA1_S  6
-/* HOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT5_INT_ENA1  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_ENA1_M  (BIT(5))
-#define HOST_SLC1_TOHOST_BIT5_INT_ENA1_V  0x1
-#define HOST_SLC1_TOHOST_BIT5_INT_ENA1_S  5
-/* HOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT4_INT_ENA1  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_ENA1_M  (BIT(4))
-#define HOST_SLC1_TOHOST_BIT4_INT_ENA1_V  0x1
-#define HOST_SLC1_TOHOST_BIT4_INT_ENA1_S  4
-/* HOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT3_INT_ENA1  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_ENA1_M  (BIT(3))
-#define HOST_SLC1_TOHOST_BIT3_INT_ENA1_V  0x1
-#define HOST_SLC1_TOHOST_BIT3_INT_ENA1_S  3
-/* HOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT2_INT_ENA1  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_ENA1_M  (BIT(2))
-#define HOST_SLC1_TOHOST_BIT2_INT_ENA1_V  0x1
-#define HOST_SLC1_TOHOST_BIT2_INT_ENA1_S  2
-/* HOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT1_INT_ENA1  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_ENA1_M  (BIT(1))
-#define HOST_SLC1_TOHOST_BIT1_INT_ENA1_V  0x1
-#define HOST_SLC1_TOHOST_BIT1_INT_ENA1_S  1
-/* HOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SLC1_TOHOST_BIT0_INT_ENA1  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_ENA1_M  (BIT(0))
-#define HOST_SLC1_TOHOST_BIT0_INT_ENA1_V  0x1
-#define HOST_SLC1_TOHOST_BIT0_INT_ENA1_S  0
-
-#define HOST_SLCHOSTDATE_REG          (DR_REG_SLCHOST_BASE + 0x178)
-/* HOST_SLCHOST_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022500 ; */
-/*description: */
-#define HOST_SLCHOST_DATE  0xFFFFFFFF
-#define HOST_SLCHOST_DATE_M  ((HOST_SLCHOST_DATE_V)<<(HOST_SLCHOST_DATE_S))
-#define HOST_SLCHOST_DATE_V  0xFFFFFFFF
-#define HOST_SLCHOST_DATE_S  0
-
-#define HOST_SLCHOSTID_REG          (DR_REG_SLCHOST_BASE + 0x17C)
-/* HOST_SLCHOST_ID : R/W ;bitpos:[31:0] ;default: 32'h0600 ; */
-/*description: */
-#define HOST_SLCHOST_ID  0xFFFFFFFF
-#define HOST_SLCHOST_ID_M  ((HOST_SLCHOST_ID_V)<<(HOST_SLCHOST_ID_S))
-#define HOST_SLCHOST_ID_V  0xFFFFFFFF
-#define HOST_SLCHOST_ID_S  0
-
-#define HOST_SLCHOST_CONF_REG          (DR_REG_SLCHOST_BASE + 0x1F0)
-/* HOST_HSPEED_CON_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define HOST_HSPEED_CON_EN  (BIT(27))
-#define HOST_HSPEED_CON_EN_M  (BIT(27))
-#define HOST_HSPEED_CON_EN_V  0x1
-#define HOST_HSPEED_CON_EN_S  27
-/* HOST_SDIO_PAD_PULLUP : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SDIO_PAD_PULLUP  (BIT(26))
-#define HOST_SDIO_PAD_PULLUP_M  (BIT(26))
-#define HOST_SDIO_PAD_PULLUP_V  0x1
-#define HOST_SDIO_PAD_PULLUP_S  26
-/* HOST_SDIO20_INT_DELAY : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define HOST_SDIO20_INT_DELAY  (BIT(25))
-#define HOST_SDIO20_INT_DELAY_M  (BIT(25))
-#define HOST_SDIO20_INT_DELAY_V  0x1
-#define HOST_SDIO20_INT_DELAY_S  25
-/* HOST_FRC_QUICK_IN : R/W ;bitpos:[24:20] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_QUICK_IN  0x0000001F
-#define HOST_FRC_QUICK_IN_M  ((HOST_FRC_QUICK_IN_V)<<(HOST_FRC_QUICK_IN_S))
-#define HOST_FRC_QUICK_IN_V  0x1F
-#define HOST_FRC_QUICK_IN_S  20
-/* HOST_FRC_POS_SAMP : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_POS_SAMP  0x0000001F
-#define HOST_FRC_POS_SAMP_M  ((HOST_FRC_POS_SAMP_V)<<(HOST_FRC_POS_SAMP_S))
-#define HOST_FRC_POS_SAMP_V  0x1F
-#define HOST_FRC_POS_SAMP_S  15
-/* HOST_FRC_NEG_SAMP : R/W ;bitpos:[14:10] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_NEG_SAMP  0x0000001F
-#define HOST_FRC_NEG_SAMP_M  ((HOST_FRC_NEG_SAMP_V)<<(HOST_FRC_NEG_SAMP_S))
-#define HOST_FRC_NEG_SAMP_V  0x1F
-#define HOST_FRC_NEG_SAMP_S  10
-/* HOST_FRC_SDIO20 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_SDIO20  0x0000001F
-#define HOST_FRC_SDIO20_M  ((HOST_FRC_SDIO20_V)<<(HOST_FRC_SDIO20_S))
-#define HOST_FRC_SDIO20_V  0x1F
-#define HOST_FRC_SDIO20_S  5
-/* HOST_FRC_SDIO11 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */
-/*description: */
-#define HOST_FRC_SDIO11  0x0000001F
-#define HOST_FRC_SDIO11_M  ((HOST_FRC_SDIO11_V)<<(HOST_FRC_SDIO11_S))
-#define HOST_FRC_SDIO11_V  0x1F
-#define HOST_FRC_SDIO11_S  0
-
-#define HOST_SLCHOST_INF_ST_REG          (DR_REG_SLCHOST_BASE + 0x1F4)
-/* HOST_SDIO_QUICK_IN : RO ;bitpos:[14:10] ;default: 5'b0 ; */
-/*description: */
-#define HOST_SDIO_QUICK_IN  0x0000001F
-#define HOST_SDIO_QUICK_IN_M  ((HOST_SDIO_QUICK_IN_V)<<(HOST_SDIO_QUICK_IN_S))
-#define HOST_SDIO_QUICK_IN_V  0x1F
-#define HOST_SDIO_QUICK_IN_S  10
-/* HOST_SDIO_NEG_SAMP : RO ;bitpos:[9:5] ;default: 5'b0 ; */
-/*description: */
-#define HOST_SDIO_NEG_SAMP  0x0000001F
-#define HOST_SDIO_NEG_SAMP_M  ((HOST_SDIO_NEG_SAMP_V)<<(HOST_SDIO_NEG_SAMP_S))
-#define HOST_SDIO_NEG_SAMP_V  0x1F
-#define HOST_SDIO_NEG_SAMP_S  5
-/* HOST_SDIO20_MODE : RO ;bitpos:[4:0] ;default: 5'b0 ; */
-/*description: */
-#define HOST_SDIO20_MODE  0x0000001F
-#define HOST_SDIO20_MODE_M  ((HOST_SDIO20_MODE_V)<<(HOST_SDIO20_MODE_S))
-#define HOST_SDIO20_MODE_V  0x1F
-#define HOST_SDIO20_MODE_S  0
-
-
-
-
-#endif /*_SOC_HOST_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/host_struct.h b/tools/sdk/include/soc/soc/host_struct.h
deleted file mode 100644
index 6c350abfc3a..00000000000
--- a/tools/sdk/include/soc/soc/host_struct.h
+++ /dev/null
@@ -1,893 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_HOST_STRUCT_H_
-#define _SOC_HOST_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    uint32_t reserved_0;
-    uint32_t reserved_4;
-    uint32_t reserved_8;
-    uint32_t reserved_c;
-    union {
-        struct {
-            uint32_t reserved0:    24;
-            uint32_t func2_int:     1;
-            uint32_t reserved25:    7;
-        };
-        uint32_t val;
-    } func2_0;
-    union {
-        struct {
-            uint32_t func2_int_en:     1;
-            uint32_t reserved1:       31;
-        };
-        uint32_t val;
-    } func2_1;
-    uint32_t reserved_18;
-    uint32_t reserved_1c;
-    union {
-        struct {
-            uint32_t func1_mdstat:     1;
-            uint32_t reserved1:       31;
-        };
-        uint32_t val;
-    } func2_2;
-    uint32_t reserved_24;
-    uint32_t reserved_28;
-    uint32_t reserved_2c;
-    uint32_t reserved_30;
-    uint32_t gpio_status0;                                  /**/
-    union {
-        struct {
-            uint32_t sdio_int1:      8;
-            uint32_t reserved8:     24;
-        };
-        uint32_t val;
-    } gpio_status1;
-    uint32_t gpio_in0;                                      /**/
-    union {
-        struct {
-            uint32_t sdio_in1:      8;
-            uint32_t reserved8:    24;
-        };
-        uint32_t val;
-    } gpio_in1;
-    union {
-        struct {
-            uint32_t token0:          12;
-            uint32_t rx_pf_valid:      1;
-            uint32_t reserved13:       3;
-            uint32_t reg_token1:      12;
-            uint32_t rx_pf_eof:        4;
-        };
-        uint32_t val;
-    } slc0_token_rdata;
-    uint32_t slc0_pf;                                          /**/
-    uint32_t slc1_pf;                                          /**/
-    union {
-        struct {
-            uint32_t tohost_bit0:                1;
-            uint32_t tohost_bit1:                1;
-            uint32_t tohost_bit2:                1;
-            uint32_t tohost_bit3:                1;
-            uint32_t tohost_bit4:                1;
-            uint32_t tohost_bit5:                1;
-            uint32_t tohost_bit6:                1;
-            uint32_t tohost_bit7:                1;
-            uint32_t token0_1to0:                1;
-            uint32_t token1_1to0:                1;
-            uint32_t token0_0to1:                1;
-            uint32_t token1_0to1:                1;
-            uint32_t rx_sof:                     1;
-            uint32_t rx_eof:                     1;
-            uint32_t rx_start:                   1;
-            uint32_t tx_start:                   1;
-            uint32_t rx_udf:                     1;
-            uint32_t tx_ovf:                     1;
-            uint32_t rx_pf_valid:                1;
-            uint32_t ext_bit0:                   1;
-            uint32_t ext_bit1:                   1;
-            uint32_t ext_bit2:                   1;
-            uint32_t ext_bit3:                   1;
-            uint32_t rx_new_packet:              1;
-            uint32_t rd_retry:                   1;
-            uint32_t gpio_sdio:                  1;
-            uint32_t reserved26:                 6;
-        };
-        uint32_t val;
-    } slc0_int_raw;
-    union {
-        struct {
-            uint32_t tohost_bit0:                     1;
-            uint32_t tohost_bit1:                     1;
-            uint32_t tohost_bit2:                     1;
-            uint32_t tohost_bit3:                     1;
-            uint32_t tohost_bit4:                     1;
-            uint32_t tohost_bit5:                     1;
-            uint32_t tohost_bit6:                     1;
-            uint32_t tohost_bit7:                     1;
-            uint32_t token0_1to0:                     1;
-            uint32_t token1_1to0:                     1;
-            uint32_t token0_0to1:                     1;
-            uint32_t token1_0to1:                     1;
-            uint32_t rx_sof:                          1;
-            uint32_t rx_eof:                          1;
-            uint32_t rx_start:                        1;
-            uint32_t tx_start:                        1;
-            uint32_t rx_udf:                          1;
-            uint32_t tx_ovf:                          1;
-            uint32_t rx_pf_valid:                     1;
-            uint32_t ext_bit0:                        1;
-            uint32_t ext_bit1:                        1;
-            uint32_t ext_bit2:                        1;
-            uint32_t ext_bit3:                        1;
-            uint32_t wifi_rx_new_packet:              1;
-            uint32_t rd_retry:                        1;
-            uint32_t bt_rx_new_packet:                1;
-            uint32_t reserved26:                      6;
-        };
-        uint32_t val;
-    } slc1_int_raw;
-    union {
-        struct {
-            uint32_t tohost_bit0:               1;
-            uint32_t tohost_bit1:               1;
-            uint32_t tohost_bit2:               1;
-            uint32_t tohost_bit3:               1;
-            uint32_t tohost_bit4:               1;
-            uint32_t tohost_bit5:               1;
-            uint32_t tohost_bit6:               1;
-            uint32_t tohost_bit7:               1;
-            uint32_t token0_1to0:               1;
-            uint32_t token1_1to0:               1;
-            uint32_t token0_0to1:               1;
-            uint32_t token1_0to1:               1;
-            uint32_t rx_sof:                    1;
-            uint32_t rx_eof:                    1;
-            uint32_t rx_start:                  1;
-            uint32_t tx_start:                  1;
-            uint32_t rx_udf:                    1;
-            uint32_t tx_ovf:                    1;
-            uint32_t rx_pf_valid:               1;
-            uint32_t ext_bit0:                  1;
-            uint32_t ext_bit1:                  1;
-            uint32_t ext_bit2:                  1;
-            uint32_t ext_bit3:                  1;
-            uint32_t rx_new_packet:             1;
-            uint32_t rd_retry:                  1;
-            uint32_t gpio_sdio:                 1;
-            uint32_t reserved26:                6;
-        };
-        uint32_t val;
-    } slc0_int_st;
-    union {
-        struct {
-            uint32_t tohost_bit0:                    1;
-            uint32_t tohost_bit1:                    1;
-            uint32_t tohost_bit2:                    1;
-            uint32_t tohost_bit3:                    1;
-            uint32_t tohost_bit4:                    1;
-            uint32_t tohost_bit5:                    1;
-            uint32_t tohost_bit6:                    1;
-            uint32_t tohost_bit7:                    1;
-            uint32_t token0_1to0:                    1;
-            uint32_t token1_1to0:                    1;
-            uint32_t token0_0to1:                    1;
-            uint32_t token1_0to1:                    1;
-            uint32_t rx_sof:                         1;
-            uint32_t rx_eof:                         1;
-            uint32_t rx_start:                       1;
-            uint32_t tx_start:                       1;
-            uint32_t rx_udf:                         1;
-            uint32_t tx_ovf:                         1;
-            uint32_t rx_pf_valid:                    1;
-            uint32_t ext_bit0:                       1;
-            uint32_t ext_bit1:                       1;
-            uint32_t ext_bit2:                       1;
-            uint32_t ext_bit3:                       1;
-            uint32_t wifi_rx_new_packet:             1;
-            uint32_t rd_retry:                       1;
-            uint32_t bt_rx_new_packet:               1;
-            uint32_t reserved26:                     6;
-        };
-        uint32_t val;
-    } slc1_int_st;
-    union {
-        struct {
-            uint32_t reg_slc0_len:      20;
-            uint32_t reg_slc0_len_check:12;
-        };
-        uint32_t val;
-    } pkt_len;
-    union {
-        struct {
-            uint32_t state0:         8;
-            uint32_t state1:         8;
-            uint32_t state2:         8;
-            uint32_t state3:         8;
-        };
-        uint32_t val;
-    } state_w0;
-    union {
-        struct {
-            uint32_t state4:         8;
-            uint32_t state5:         8;
-            uint32_t state6:         8;
-            uint32_t state7:         8;
-        };
-        uint32_t val;
-    } state_w1;
-    union {
-        struct {
-            uint32_t conf0:         8;
-            uint32_t conf1:         8;
-            uint32_t conf2:         8;
-            uint32_t conf3:         8;
-        };
-        uint32_t val;
-    } conf_w0;
-    union {
-        struct {
-            uint32_t conf4:         8;
-            uint32_t conf5:         8;
-            uint32_t conf6:         8;
-            uint32_t conf7:         8;
-        };
-        uint32_t val;
-    } conf_w1;
-    union {
-        struct {
-            uint32_t conf8:          8;
-            uint32_t conf9:          8;
-            uint32_t conf10:         8;
-            uint32_t conf11:         8;
-        };
-        uint32_t val;
-    } conf_w2;
-    union {
-        struct {
-            uint32_t conf12:         8;
-            uint32_t conf13:         8;
-            uint32_t conf14:         8;
-            uint32_t conf15:         8;
-        };
-        uint32_t val;
-    } conf_w3;
-    union {
-        struct {
-            uint32_t conf16:         8;                        /*SLC timeout value*/
-            uint32_t conf17:         8;                        /*SLC timeout enable*/
-            uint32_t conf18:         8;
-            uint32_t conf19:         8;                        /*Interrupt to target CPU*/
-        };
-        uint32_t val;
-    } conf_w4;
-    union {
-        struct {
-            uint32_t conf20:         8;
-            uint32_t conf21:         8;
-            uint32_t conf22:         8;
-            uint32_t conf23:         8;
-        };
-        uint32_t val;
-    } conf_w5;
-    uint32_t win_cmd;                                       /**/
-    union {
-        struct {
-            uint32_t conf24:         8;
-            uint32_t conf25:         8;
-            uint32_t conf26:         8;
-            uint32_t conf27:         8;
-        };
-        uint32_t val;
-    } conf_w6;
-    union {
-        struct {
-            uint32_t conf28:         8;
-            uint32_t conf29:         8;
-            uint32_t conf30:         8;
-            uint32_t conf31:         8;
-        };
-        uint32_t val;
-    } conf_w7;
-    union {
-        struct {
-            uint32_t reg_slc0_len0:20;
-            uint32_t reserved20:   12;
-        };
-        uint32_t val;
-    } pkt_len0;
-    union {
-        struct {
-            uint32_t reg_slc0_len1:20;
-            uint32_t reserved20:   12;
-        };
-        uint32_t val;
-    } pkt_len1;
-    union {
-        struct {
-            uint32_t reg_slc0_len2:20;
-            uint32_t reserved20:   12;
-        };
-        uint32_t val;
-    } pkt_len2;
-    union {
-        struct {
-            uint32_t conf32:         8;
-            uint32_t conf33:         8;
-            uint32_t conf34:         8;
-            uint32_t conf35:         8;
-        };
-        uint32_t val;
-    } conf_w8;
-    union {
-        struct {
-            uint32_t conf36:         8;
-            uint32_t conf37:         8;
-            uint32_t conf38:         8;
-            uint32_t conf39:         8;
-        };
-        uint32_t val;
-    } conf_w9;
-    union {
-        struct {
-            uint32_t conf40:         8;
-            uint32_t conf41:         8;
-            uint32_t conf42:         8;
-            uint32_t conf43:         8;
-        };
-        uint32_t val;
-    } conf_w10;
-    union {
-        struct {
-            uint32_t conf44:         8;
-            uint32_t conf45:         8;
-            uint32_t conf46:         8;
-            uint32_t conf47:         8;
-        };
-        uint32_t val;
-    } conf_w11;
-    union {
-        struct {
-            uint32_t conf48:         8;
-            uint32_t conf49:         8;
-            uint32_t conf50:         8;
-            uint32_t conf51:         8;
-        };
-        uint32_t val;
-    } conf_w12;
-    union {
-        struct {
-            uint32_t conf52:         8;
-            uint32_t conf53:         8;
-            uint32_t conf54:         8;
-            uint32_t conf55:         8;
-        };
-        uint32_t val;
-    } conf_w13;
-    union {
-        struct {
-            uint32_t conf56:         8;
-            uint32_t conf57:         8;
-            uint32_t conf58:         8;
-            uint32_t conf59:         8;
-        };
-        uint32_t val;
-    } conf_w14;
-    union {
-        struct {
-            uint32_t conf60:         8;
-            uint32_t conf61:         8;
-            uint32_t conf62:         8;
-            uint32_t conf63:         8;
-        };
-        uint32_t val;
-    } conf_w15;
-    uint32_t check_sum0;                                    /**/
-    uint32_t check_sum1;                                    /**/
-    union {
-        struct {
-            uint32_t token0:          12;
-            uint32_t rx_pf_valid:      1;
-            uint32_t reserved13:       3;
-            uint32_t reg_token1:      12;
-            uint32_t rx_pf_eof:        4;
-        };
-        uint32_t val;
-    } slc1_token_rdata;
-    union {
-        struct {
-            uint32_t token0_wd:         12;
-            uint32_t reserved12:         4;
-            uint32_t token1_wd:         12;
-            uint32_t reserved28:         4;
-        };
-        uint32_t val;
-    } slc0_token_wdata;
-    union {
-        struct {
-            uint32_t token0_wd:         12;
-            uint32_t reserved12:         4;
-            uint32_t token1_wd:         12;
-            uint32_t reserved28:         4;
-        };
-        uint32_t val;
-    } slc1_token_wdata;
-    union {
-        struct {
-            uint32_t slc0_token0_dec:     1;
-            uint32_t slc0_token1_dec:     1;
-            uint32_t slc0_token0_wr:      1;
-            uint32_t slc0_token1_wr:      1;
-            uint32_t slc1_token0_dec:     1;
-            uint32_t slc1_token1_dec:     1;
-            uint32_t slc1_token0_wr:      1;
-            uint32_t slc1_token1_wr:      1;
-            uint32_t slc0_len_wr:         1;
-            uint32_t reserved9:          23;
-        };
-        uint32_t val;
-    } token_con;
-    union {
-        struct {
-            uint32_t tohost_bit0:                1;
-            uint32_t tohost_bit1:                1;
-            uint32_t tohost_bit2:                1;
-            uint32_t tohost_bit3:                1;
-            uint32_t tohost_bit4:                1;
-            uint32_t tohost_bit5:                1;
-            uint32_t tohost_bit6:                1;
-            uint32_t tohost_bit7:                1;
-            uint32_t token0_1to0:                1;
-            uint32_t token1_1to0:                1;
-            uint32_t token0_0to1:                1;
-            uint32_t token1_0to1:                1;
-            uint32_t rx_sof:                     1;
-            uint32_t rx_eof:                     1;
-            uint32_t rx_start:                   1;
-            uint32_t tx_start:                   1;
-            uint32_t rx_udf:                     1;
-            uint32_t tx_ovf:                     1;
-            uint32_t rx_pf_valid:                1;
-            uint32_t ext_bit0:                   1;
-            uint32_t ext_bit1:                   1;
-            uint32_t ext_bit2:                   1;
-            uint32_t ext_bit3:                   1;
-            uint32_t rx_new_packet:              1;
-            uint32_t rd_retry:                   1;
-            uint32_t gpio_sdio:                  1;
-            uint32_t reserved26:                 6;
-        };
-        uint32_t val;
-    } slc0_int_clr;
-    union {
-        struct {
-            uint32_t tohost_bit0:                     1;
-            uint32_t tohost_bit1:                     1;
-            uint32_t tohost_bit2:                     1;
-            uint32_t tohost_bit3:                     1;
-            uint32_t tohost_bit4:                     1;
-            uint32_t tohost_bit5:                     1;
-            uint32_t tohost_bit6:                     1;
-            uint32_t tohost_bit7:                     1;
-            uint32_t token0_1to0:                     1;
-            uint32_t token1_1to0:                     1;
-            uint32_t token0_0to1:                     1;
-            uint32_t token1_0to1:                     1;
-            uint32_t rx_sof:                          1;
-            uint32_t rx_eof:                          1;
-            uint32_t rx_start:                        1;
-            uint32_t tx_start:                        1;
-            uint32_t rx_udf:                          1;
-            uint32_t tx_ovf:                          1;
-            uint32_t rx_pf_valid:                     1;
-            uint32_t ext_bit0:                        1;
-            uint32_t ext_bit1:                        1;
-            uint32_t ext_bit2:                        1;
-            uint32_t ext_bit3:                        1;
-            uint32_t wifi_rx_new_packet:              1;
-            uint32_t rd_retry:                        1;
-            uint32_t bt_rx_new_packet:                1;
-            uint32_t reserved26:                      6;
-        };
-        uint32_t val;
-    } slc1_int_clr;
-    union {
-        struct {
-            uint32_t tohost_bit0:                    1;
-            uint32_t tohost_bit1:                    1;
-            uint32_t tohost_bit2:                    1;
-            uint32_t tohost_bit3:                    1;
-            uint32_t tohost_bit4:                    1;
-            uint32_t tohost_bit5:                    1;
-            uint32_t tohost_bit6:                    1;
-            uint32_t tohost_bit7:                    1;
-            uint32_t token0_1to0:                    1;
-            uint32_t token1_1to0:                    1;
-            uint32_t token0_0to1:                    1;
-            uint32_t token1_0to1:                    1;
-            uint32_t rx_sof:                         1;
-            uint32_t rx_eof:                         1;
-            uint32_t rx_start:                       1;
-            uint32_t tx_start:                       1;
-            uint32_t rx_udf:                         1;
-            uint32_t tx_ovf:                         1;
-            uint32_t rx_pf_valid:                    1;
-            uint32_t ext_bit0:                       1;
-            uint32_t ext_bit1:                       1;
-            uint32_t ext_bit2:                       1;
-            uint32_t ext_bit3:                       1;
-            uint32_t rx_new_packet:                  1;
-            uint32_t rd_retry:                       1;
-            uint32_t gpio_sdio:                      1;
-            uint32_t reserved26:                     6;
-        };
-        uint32_t val;
-    } slc0_func1_int_ena;
-    union {
-        struct {
-            uint32_t tohost_bit0:                         1;
-            uint32_t tohost_bit1:                         1;
-            uint32_t tohost_bit2:                         1;
-            uint32_t tohost_bit3:                         1;
-            uint32_t tohost_bit4:                         1;
-            uint32_t tohost_bit5:                         1;
-            uint32_t tohost_bit6:                         1;
-            uint32_t tohost_bit7:                         1;
-            uint32_t token0_1to0:                         1;
-            uint32_t token1_1to0:                         1;
-            uint32_t token0_0to1:                         1;
-            uint32_t token1_0to1:                         1;
-            uint32_t rx_sof:                              1;
-            uint32_t rx_eof:                              1;
-            uint32_t rx_start:                            1;
-            uint32_t tx_start:                            1;
-            uint32_t rx_udf:                              1;
-            uint32_t tx_ovf:                              1;
-            uint32_t rx_pf_valid:                         1;
-            uint32_t ext_bit0:                            1;
-            uint32_t ext_bit1:                            1;
-            uint32_t ext_bit2:                            1;
-            uint32_t ext_bit3:                            1;
-            uint32_t wifi_rx_new_packet:                  1;
-            uint32_t rd_retry:                            1;
-            uint32_t bt_rx_new_packet:                    1;
-            uint32_t reserved26:                          6;
-        };
-        uint32_t val;
-    } slc1_func1_int_ena;
-    union {
-        struct {
-            uint32_t tohost_bit0:                    1;
-            uint32_t tohost_bit1:                    1;
-            uint32_t tohost_bit2:                    1;
-            uint32_t tohost_bit3:                    1;
-            uint32_t tohost_bit4:                    1;
-            uint32_t tohost_bit5:                    1;
-            uint32_t tohost_bit6:                    1;
-            uint32_t tohost_bit7:                    1;
-            uint32_t token0_1to0:                    1;
-            uint32_t token1_1to0:                    1;
-            uint32_t token0_0to1:                    1;
-            uint32_t token1_0to1:                    1;
-            uint32_t rx_sof:                         1;
-            uint32_t rx_eof:                         1;
-            uint32_t rx_start:                       1;
-            uint32_t tx_start:                       1;
-            uint32_t rx_udf:                         1;
-            uint32_t tx_ovf:                         1;
-            uint32_t rx_pf_valid:                    1;
-            uint32_t ext_bit0:                       1;
-            uint32_t ext_bit1:                       1;
-            uint32_t ext_bit2:                       1;
-            uint32_t ext_bit3:                       1;
-            uint32_t rx_new_packet:                  1;
-            uint32_t rd_retry:                       1;
-            uint32_t gpio_sdio:                      1;
-            uint32_t reserved26:                     6;
-        };
-        uint32_t val;
-    } slc0_func2_int_ena;
-    union {
-        struct {
-            uint32_t tohost_bit0:                         1;
-            uint32_t tohost_bit1:                         1;
-            uint32_t tohost_bit2:                         1;
-            uint32_t tohost_bit3:                         1;
-            uint32_t tohost_bit4:                         1;
-            uint32_t tohost_bit5:                         1;
-            uint32_t tohost_bit6:                         1;
-            uint32_t tohost_bit7:                         1;
-            uint32_t token0_1to0:                         1;
-            uint32_t token1_1to0:                         1;
-            uint32_t token0_0to1:                         1;
-            uint32_t token1_0to1:                         1;
-            uint32_t rx_sof:                              1;
-            uint32_t rx_eof:                              1;
-            uint32_t rx_start:                            1;
-            uint32_t tx_start:                            1;
-            uint32_t rx_udf:                              1;
-            uint32_t tx_ovf:                              1;
-            uint32_t rx_pf_valid:                         1;
-            uint32_t ext_bit0:                            1;
-            uint32_t ext_bit1:                            1;
-            uint32_t ext_bit2:                            1;
-            uint32_t ext_bit3:                            1;
-            uint32_t wifi_rx_new_packet:                  1;
-            uint32_t rd_retry:                            1;
-            uint32_t bt_rx_new_packet:                    1;
-            uint32_t reserved26:                          6;
-        };
-        uint32_t val;
-    } slc1_func2_int_ena;
-    union {
-        struct {
-            uint32_t tohost_bit0:                1;
-            uint32_t tohost_bit1:                1;
-            uint32_t tohost_bit2:                1;
-            uint32_t tohost_bit3:                1;
-            uint32_t tohost_bit4:                1;
-            uint32_t tohost_bit5:                1;
-            uint32_t tohost_bit6:                1;
-            uint32_t tohost_bit7:                1;
-            uint32_t token0_1to0:                1;
-            uint32_t token1_1to0:                1;
-            uint32_t token0_0to1:                1;
-            uint32_t token1_0to1:                1;
-            uint32_t rx_sof:                     1;
-            uint32_t rx_eof:                     1;
-            uint32_t rx_start:                   1;
-            uint32_t tx_start:                   1;
-            uint32_t rx_udf:                     1;
-            uint32_t tx_ovf:                     1;
-            uint32_t rx_pf_valid:                1;
-            uint32_t ext_bit0:                   1;
-            uint32_t ext_bit1:                   1;
-            uint32_t ext_bit2:                   1;
-            uint32_t ext_bit3:                   1;
-            uint32_t rx_new_packet:              1;
-            uint32_t rd_retry:                   1;
-            uint32_t gpio_sdio:                  1;
-            uint32_t reserved26:                 6;
-        };
-        uint32_t val;
-    } slc0_int_ena;
-    union {
-        struct {
-            uint32_t tohost_bit0:                     1;
-            uint32_t tohost_bit1:                     1;
-            uint32_t tohost_bit2:                     1;
-            uint32_t tohost_bit3:                     1;
-            uint32_t tohost_bit4:                     1;
-            uint32_t tohost_bit5:                     1;
-            uint32_t tohost_bit6:                     1;
-            uint32_t tohost_bit7:                     1;
-            uint32_t token0_1to0:                     1;
-            uint32_t token1_1to0:                     1;
-            uint32_t token0_0to1:                     1;
-            uint32_t token1_0to1:                     1;
-            uint32_t rx_sof:                          1;
-            uint32_t rx_eof:                          1;
-            uint32_t rx_start:                        1;
-            uint32_t tx_start:                        1;
-            uint32_t rx_udf:                          1;
-            uint32_t tx_ovf:                          1;
-            uint32_t rx_pf_valid:                     1;
-            uint32_t ext_bit0:                        1;
-            uint32_t ext_bit1:                        1;
-            uint32_t ext_bit2:                        1;
-            uint32_t ext_bit3:                        1;
-            uint32_t wifi_rx_new_packet:              1;
-            uint32_t rd_retry:                        1;
-            uint32_t bt_rx_new_packet:                1;
-            uint32_t reserved26:                      6;
-        };
-        uint32_t val;
-    } slc1_int_ena;
-    union {
-        struct {
-            uint32_t infor:            20;
-            uint32_t reserved20:       12;
-        };
-        uint32_t val;
-    } slc0_rx_infor;
-    union {
-        struct {
-            uint32_t infor:            20;
-            uint32_t reserved20:       12;
-        };
-        uint32_t val;
-    } slc1_rx_infor;
-    uint32_t slc0_len_wd;                                       /**/
-    uint32_t apbwin_wdata;                                 /**/
-    union {
-        struct {
-            uint32_t addr:            28;
-            uint32_t wr:               1;
-            uint32_t start:            1;
-            uint32_t reserved30:       2;
-        };
-        uint32_t val;
-    } apbwin_conf;
-    uint32_t apbwin_rdata;                                 /**/
-    union {
-        struct {
-            uint32_t bit7_clraddr:              9;
-            uint32_t bit6_clraddr:              9;
-            uint32_t reserved18:               14;
-        };
-        uint32_t val;
-    } slc0_rdclr;
-    union {
-        struct {
-            uint32_t bit7_clraddr:              9;
-            uint32_t bit6_clraddr:              9;
-            uint32_t reserved18:               14;
-        };
-        uint32_t val;
-    } slc1_rdclr;
-    union {
-        struct {
-            uint32_t tohost_bit01:                1;
-            uint32_t tohost_bit11:                1;
-            uint32_t tohost_bit21:                1;
-            uint32_t tohost_bit31:                1;
-            uint32_t tohost_bit41:                1;
-            uint32_t tohost_bit51:                1;
-            uint32_t tohost_bit61:                1;
-            uint32_t tohost_bit71:                1;
-            uint32_t token0_1to01:                1;
-            uint32_t token1_1to01:                1;
-            uint32_t token0_0to11:                1;
-            uint32_t token1_0to11:                1;
-            uint32_t rx_sof1:                     1;
-            uint32_t rx_eof1:                     1;
-            uint32_t rx_start1:                   1;
-            uint32_t tx_start1:                   1;
-            uint32_t rx_udf1:                     1;
-            uint32_t tx_ovf1:                     1;
-            uint32_t rx_pf_valid1:                1;
-            uint32_t ext_bit01:                   1;
-            uint32_t ext_bit11:                   1;
-            uint32_t ext_bit21:                   1;
-            uint32_t ext_bit31:                   1;
-            uint32_t rx_new_packet1:              1;
-            uint32_t rd_retry1:                   1;
-            uint32_t gpio_sdio1:                  1;
-            uint32_t reserved26:                  6;
-        };
-        uint32_t val;
-    } slc0_int_ena1;
-    union {
-        struct {
-            uint32_t tohost_bit01:                     1;
-            uint32_t tohost_bit11:                     1;
-            uint32_t tohost_bit21:                     1;
-            uint32_t tohost_bit31:                     1;
-            uint32_t tohost_bit41:                     1;
-            uint32_t tohost_bit51:                     1;
-            uint32_t tohost_bit61:                     1;
-            uint32_t tohost_bit71:                     1;
-            uint32_t token0_1to01:                     1;
-            uint32_t token1_1to01:                     1;
-            uint32_t token0_0to11:                     1;
-            uint32_t token1_0to11:                     1;
-            uint32_t rx_sof1:                          1;
-            uint32_t rx_eof1:                          1;
-            uint32_t rx_start1:                        1;
-            uint32_t tx_start1:                        1;
-            uint32_t rx_udf1:                          1;
-            uint32_t tx_ovf1:                          1;
-            uint32_t rx_pf_valid1:                     1;
-            uint32_t ext_bit01:                        1;
-            uint32_t ext_bit11:                        1;
-            uint32_t ext_bit21:                        1;
-            uint32_t ext_bit31:                        1;
-            uint32_t wifi_rx_new_packet1:              1;
-            uint32_t rd_retry1:                        1;
-            uint32_t bt_rx_new_packet1:                1;
-            uint32_t reserved26:                       6;
-        };
-        uint32_t val;
-    } slc1_int_ena1;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t date;                                          /**/
-    uint32_t id;                                            /**/
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    union {
-        struct {
-            uint32_t frc_sdio11:       5;
-            uint32_t frc_sdio20:       5;
-            uint32_t frc_neg_samp:     5;
-            uint32_t frc_pos_samp:     5;
-            uint32_t frc_quick_in:     5;
-            uint32_t sdio20_int_delay: 1;
-            uint32_t sdio_pad_pullup:  1;
-            uint32_t hspeed_con_en:    1;
-            uint32_t reserved28:       4;
-        };
-        uint32_t val;
-    } conf;
-    union {
-        struct {
-            uint32_t sdio20_mode:   5;
-            uint32_t sdio_neg_samp: 5;
-            uint32_t sdio_quick_in: 5;
-            uint32_t reserved15:   17;
-        };
-        uint32_t val;
-    } inf_st;
-} host_dev_t;
-extern host_dev_t HOST;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_HOST_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/hwcrypto_reg.h b/tools/sdk/include/soc/soc/hwcrypto_reg.h
deleted file mode 100644
index d0dfa748589..00000000000
--- a/tools/sdk/include/soc/soc/hwcrypto_reg.h
+++ /dev/null
@@ -1,68 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __HWCRYPTO_REG_H__
-#define __HWCRYPTO_REG_H__
-
-#include "soc.h"
-
-/* registers for RSA acceleration via Multiple Precision Integer ops */
-#define RSA_MEM_M_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x000)
-/* RB & Z use the same memory block, depending on phase of operation */
-#define RSA_MEM_RB_BLOCK_BASE         ((DR_REG_RSA_BASE)+0x200)
-#define RSA_MEM_Z_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x200)
-#define RSA_MEM_Y_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x400)
-#define RSA_MEM_X_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x600)
-
-#define RSA_M_DASH_REG                (DR_REG_RSA_BASE + 0x800)
-#define RSA_MODEXP_MODE_REG           (DR_REG_RSA_BASE + 0x804)
-#define RSA_START_MODEXP_REG          (DR_REG_RSA_BASE + 0x808)
-#define RSA_MULT_MODE_REG             (DR_REG_RSA_BASE + 0x80c)
-#define RSA_MULT_START_REG            (DR_REG_RSA_BASE + 0x810)
-
-#define RSA_INTERRUPT_REG             (DR_REG_RSA_BASE + 0x814)
-
-#define RSA_CLEAN_REG                 (DR_REG_RSA_BASE + 0x818)
-
-/* SHA acceleration registers */
-#define SHA_TEXT_BASE          ((DR_REG_SHA_BASE) + 0x00)
-
-#define SHA_1_START_REG         ((DR_REG_SHA_BASE) + 0x80)
-#define SHA_1_CONTINUE_REG      ((DR_REG_SHA_BASE) + 0x84)
-#define SHA_1_LOAD_REG          ((DR_REG_SHA_BASE) + 0x88)
-#define SHA_1_BUSY_REG          ((DR_REG_SHA_BASE) + 0x8c)
-
-#define SHA_256_START_REG       ((DR_REG_SHA_BASE) + 0x90)
-#define SHA_256_CONTINUE_REG    ((DR_REG_SHA_BASE) + 0x94)
-#define SHA_256_LOAD_REG        ((DR_REG_SHA_BASE) + 0x98)
-#define SHA_256_BUSY_REG        ((DR_REG_SHA_BASE) + 0x9c)
-
-#define SHA_384_START_REG       ((DR_REG_SHA_BASE) + 0xa0)
-#define SHA_384_CONTINUE_REG    ((DR_REG_SHA_BASE) + 0xa4)
-#define SHA_384_LOAD_REG        ((DR_REG_SHA_BASE) + 0xa8)
-#define SHA_384_BUSY_REG        ((DR_REG_SHA_BASE) + 0xac)
-
-#define SHA_512_START_REG       ((DR_REG_SHA_BASE) + 0xb0)
-#define SHA_512_CONTINUE_REG    ((DR_REG_SHA_BASE) + 0xb4)
-#define SHA_512_LOAD_REG        ((DR_REG_SHA_BASE) + 0xb8)
-#define SHA_512_BUSY_REG        ((DR_REG_SHA_BASE) + 0xbc)
-
-/* AES acceleration registers */
-#define AES_START_REG           ((DR_REG_AES_BASE) + 0x00)
-#define AES_IDLE_REG            ((DR_REG_AES_BASE) + 0x04)
-#define AES_MODE_REG            ((DR_REG_AES_BASE) + 0x08)
-#define AES_KEY_BASE            ((DR_REG_AES_BASE) + 0x10)
-#define AES_TEXT_BASE           ((DR_REG_AES_BASE) + 0x30)
-#define AES_ENDIAN              ((DR_REG_AES_BASE) + 0x40)
-
-#endif
diff --git a/tools/sdk/include/soc/soc/i2c_reg.h b/tools/sdk/include/soc/soc/i2c_reg.h
deleted file mode 100644
index 292695eb7f3..00000000000
--- a/tools/sdk/include/soc/soc/i2c_reg.h
+++ /dev/null
@@ -1,951 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_I2C_REG_H_
-#define _SOC_I2C_REG_H_
-
-
-#include "soc.h"
-
-#define REG_I2C_BASE(i)    (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
-
-#define I2C_SCL_LOW_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0000)
-/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This register is used to configure the  low level width of SCL clock.*/
-#define I2C_SCL_LOW_PERIOD  0x00003FFF
-#define I2C_SCL_LOW_PERIOD_M  ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
-#define I2C_SCL_LOW_PERIOD_V  0x3FFF
-#define I2C_SCL_LOW_PERIOD_S  0
-
-#define I2C_CTR_REG(i)          (REG_I2C_BASE(i) + 0x0004)
-/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This is the clock gating control bit for reading or writing registers.*/
-#define I2C_CLK_EN  (BIT(8))
-#define I2C_CLK_EN_M  (BIT(8))
-#define I2C_CLK_EN_V  0x1
-#define I2C_CLK_EN_S  8
-/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: This bit is used to control the storage mode for received datas.
- 1: receive data from most significant bit    0: receive data from least significant bit*/
-#define I2C_RX_LSB_FIRST  (BIT(7))
-#define I2C_RX_LSB_FIRST_M  (BIT(7))
-#define I2C_RX_LSB_FIRST_V  0x1
-#define I2C_RX_LSB_FIRST_S  7
-/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This bit is used to control the sending mode for  data need to
- be send. 1: receive data from most significant bit    0: receive data from least significant bit*/
-#define I2C_TX_LSB_FIRST  (BIT(6))
-#define I2C_TX_LSB_FIRST_M  (BIT(6))
-#define I2C_TX_LSB_FIRST_V  0x1
-#define I2C_TX_LSB_FIRST_S  6
-/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to start sending data in txfifo.*/
-#define I2C_TRANS_START  (BIT(5))
-#define I2C_TRANS_START_M  (BIT(5))
-#define I2C_TRANS_START_V  0x1
-#define I2C_TRANS_START_S  5
-/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to configure the module as i2c master  clear this
- bit to configure the module as i2c slave.*/
-#define I2C_MS_MODE  (BIT(4))
-#define I2C_MS_MODE_M  (BIT(4))
-#define I2C_MS_MODE_V  0x1
-#define I2C_MS_MODE_S  4
-/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to sample data in SCL low level. clear this bit
- to sample data in SCL high level.*/
-#define I2C_SAMPLE_SCL_LEVEL  (BIT(2))
-#define I2C_SAMPLE_SCL_LEVEL_M  (BIT(2))
-#define I2C_SAMPLE_SCL_LEVEL_V  0x1
-#define I2C_SAMPLE_SCL_LEVEL_S  2
-/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: 1: normally ouput scl clock  0: exchange the function of scl_o
- and scl_oe (scl_o is the original internal output scl signal  scl_oe is the enable bit for the internal output scl signal)*/
-#define I2C_SCL_FORCE_OUT  (BIT(1))
-#define I2C_SCL_FORCE_OUT_M  (BIT(1))
-#define I2C_SCL_FORCE_OUT_V  0x1
-#define I2C_SCL_FORCE_OUT_S  1
-/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: 1: normally ouput sda data   0: exchange the function of sda_o
- and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
-#define I2C_SDA_FORCE_OUT  (BIT(0))
-#define I2C_SDA_FORCE_OUT_M  (BIT(0))
-#define I2C_SDA_FORCE_OUT_V  0x1
-#define I2C_SDA_FORCE_OUT_S  0
-
-#define I2C_SR_REG(i)          (REG_I2C_BASE(i) + 0x0008)
-/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
-/*description: This register stores the value of state machine to produce SCL.
- 3'h0: SCL_IDLE  3'h1:SCL_START   3'h2:SCL_LOW_EDGE  3'h3: SCL_LOW   3'h4:SCL_HIGH_EDGE   3'h5:SCL_HIGH  3'h6:SCL_STOP*/
-#define I2C_SCL_STATE_LAST  0x00000007
-#define I2C_SCL_STATE_LAST_M  ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
-#define I2C_SCL_STATE_LAST_V  0x7
-#define I2C_SCL_STATE_LAST_S  28
-/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
-/*description: This register stores the value of state machine for i2c module.
-  3'h0: SCL_MAIN_IDLE  3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS  3'h3: SCL_RX_DATA  3'h4 SCL_TX_DATA  3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
-#define I2C_SCL_MAIN_STATE_LAST  0x00000007
-#define I2C_SCL_MAIN_STATE_LAST_M  ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
-#define I2C_SCL_MAIN_STATE_LAST_V  0x7
-#define I2C_SCL_MAIN_STATE_LAST_S  24
-/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
-/*description: This register stores the amount of received data  in ram.*/
-#define I2C_TXFIFO_CNT  0x0000003F
-#define I2C_TXFIFO_CNT_M  ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
-#define I2C_TXFIFO_CNT_V  0x3F
-#define I2C_TXFIFO_CNT_S  18
-/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
-/*description: This register represent the amount of data need to send.*/
-#define I2C_RXFIFO_CNT  0x0000003F
-#define I2C_RXFIFO_CNT_M  ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
-#define I2C_RXFIFO_CNT_V  0x3F
-#define I2C_RXFIFO_CNT_S  8
-/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This register changes to high level when one byte is transferred.*/
-#define I2C_BYTE_TRANS  (BIT(6))
-#define I2C_BYTE_TRANS_M  (BIT(6))
-#define I2C_BYTE_TRANS_V  0x1
-#define I2C_BYTE_TRANS_S  6
-/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: when configured as i2c slave  and the address send by master
- is equal to slave's address  then this bit will be high level.*/
-#define I2C_SLAVE_ADDRESSED  (BIT(5))
-#define I2C_SLAVE_ADDRESSED_M  (BIT(5))
-#define I2C_SLAVE_ADDRESSED_V  0x1
-#define I2C_SLAVE_ADDRESSED_S  5
-/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
-#define I2C_BUS_BUSY  (BIT(4))
-#define I2C_BUS_BUSY_M  (BIT(4))
-#define I2C_BUS_BUSY_V  0x1
-#define I2C_BUS_BUSY_S  4
-/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: when I2C lost control of SDA line  this register changes to high level.*/
-#define I2C_ARB_LOST  (BIT(3))
-#define I2C_ARB_LOST_M  (BIT(3))
-#define I2C_ARB_LOST_V  0x1
-#define I2C_ARB_LOST_S  3
-/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: when I2C takes more than time_out_reg clocks to receive a data
- then this register changes to high level.*/
-#define I2C_TIME_OUT  (BIT(2))
-#define I2C_TIME_OUT_M  (BIT(2))
-#define I2C_TIME_OUT_V  0x1
-#define I2C_TIME_OUT_S  2
-/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: when in slave mode  1: master read slave  0: master write slave.*/
-#define I2C_SLAVE_RW  (BIT(1))
-#define I2C_SLAVE_RW_M  (BIT(1))
-#define I2C_SLAVE_RW_V  0x1
-#define I2C_SLAVE_RW_S  1
-/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This register stores the value of ACK bit.*/
-#define I2C_ACK_REC  (BIT(0))
-#define I2C_ACK_REC_M  (BIT(0))
-#define I2C_ACK_REC_V  0x1
-#define I2C_ACK_REC_S  0
-
-#define I2C_TO_REG(i)          (REG_I2C_BASE(i) + 0x000c)
-/* I2C_TIME_OUT_REG : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: This register is used to configure the max clock number of receiving  a data.*/
-#define I2C_TIME_OUT_REG  0x000FFFFF
-#define I2C_TIME_OUT_REG_M  ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S))
-#define I2C_TIME_OUT_REG_V  0xFFFFF
-#define I2C_TIME_OUT_REG_S  0
-
-#define I2C_SLAVE_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x0010)
-/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: This register is used to enable slave 10bit address mode.*/
-#define I2C_ADDR_10BIT_EN  (BIT(31))
-#define I2C_ADDR_10BIT_EN_M  (BIT(31))
-#define I2C_ADDR_10BIT_EN_V  0x1
-#define I2C_ADDR_10BIT_EN_S  31
-/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
-/*description: when configured as i2c slave  this register is used to configure
- slave's address.*/
-#define I2C_SLAVE_ADDR  0x00007FFF
-#define I2C_SLAVE_ADDR_M  ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
-#define I2C_SLAVE_ADDR_V  0x7FFF
-#define I2C_SLAVE_ADDR_S  0
-
-#define I2C_RXFIFO_ST_REG(i)          (REG_I2C_BASE(i) + 0x0014)
-/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
-/*description: This is the offset address of the last  sending data as described
- in nonfifo_tx_thres register.*/
-#define I2C_TXFIFO_END_ADDR  0x0000001F
-#define I2C_TXFIFO_END_ADDR_M  ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S))
-#define I2C_TXFIFO_END_ADDR_V  0x1F
-#define I2C_TXFIFO_END_ADDR_S  15
-/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
-/*description: This is the offset address of the first  sending data as described
- in nonfifo_tx_thres register.*/
-#define I2C_TXFIFO_START_ADDR  0x0000001F
-#define I2C_TXFIFO_START_ADDR_M  ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S))
-#define I2C_TXFIFO_START_ADDR_V  0x1F
-#define I2C_TXFIFO_START_ADDR_S  10
-/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
-/*description: This is the offset address of the first receiving data as described
- in nonfifo_rx_thres_register.*/
-#define I2C_RXFIFO_END_ADDR  0x0000001F
-#define I2C_RXFIFO_END_ADDR_M  ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S))
-#define I2C_RXFIFO_END_ADDR_V  0x1F
-#define I2C_RXFIFO_END_ADDR_S  5
-/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
-/*description: This is the offset address of the last receiving data as described
- in nonfifo_rx_thres_register.*/
-#define I2C_RXFIFO_START_ADDR  0x0000001F
-#define I2C_RXFIFO_START_ADDR_M  ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S))
-#define I2C_RXFIFO_START_ADDR_V  0x1F
-#define I2C_RXFIFO_START_ADDR_S  0
-
-#define I2C_FIFO_CONF_REG(i)          (REG_I2C_BASE(i) + 0x0018)
-/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */
-/*description: when I2C sends more than nonfifo_tx_thres data  it will produce
- tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
-#define I2C_NONFIFO_TX_THRES  0x0000003F
-#define I2C_NONFIFO_TX_THRES_M  ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S))
-#define I2C_NONFIFO_TX_THRES_V  0x3F
-#define I2C_NONFIFO_TX_THRES_S  20
-/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */
-/*description: when I2C receives more than nonfifo_rx_thres data  it will produce
- rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
-#define I2C_NONFIFO_RX_THRES  0x0000003F
-#define I2C_NONFIFO_RX_THRES_M  ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S))
-#define I2C_NONFIFO_RX_THRES_V  0x3F
-#define I2C_NONFIFO_RX_THRES_S  14
-/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to reset tx fifo when using apb fifo access.*/
-#define I2C_TX_FIFO_RST  (BIT(13))
-#define I2C_TX_FIFO_RST_M  (BIT(13))
-#define I2C_TX_FIFO_RST_V  0x1
-#define I2C_TX_FIFO_RST_S  13
-/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to reset rx fifo when using apb fifo access.*/
-#define I2C_RX_FIFO_RST  (BIT(12))
-#define I2C_RX_FIFO_RST_M  (BIT(12))
-#define I2C_RX_FIFO_RST_V  0x1
-#define I2C_RX_FIFO_RST_S  12
-/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: When this bit is set to 1 then the byte after address represent
- the offset address of I2C Slave's ram.*/
-#define I2C_FIFO_ADDR_CFG_EN  (BIT(11))
-#define I2C_FIFO_ADDR_CFG_EN_M  (BIT(11))
-#define I2C_FIFO_ADDR_CFG_EN_V  0x1
-#define I2C_FIFO_ADDR_CFG_EN_S  11
-/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to enble apb nonfifo access.*/
-#define I2C_NONFIFO_EN  (BIT(10))
-#define I2C_NONFIFO_EN_M  (BIT(10))
-#define I2C_NONFIFO_EN_V  0x1
-#define I2C_NONFIFO_EN_S  10
-/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
-/*description: Config txfifo empty threhd value when using apb fifo access*/
-#define I2C_TXFIFO_EMPTY_THRHD  0x0000001F
-#define I2C_TXFIFO_EMPTY_THRHD_M  ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S))
-#define I2C_TXFIFO_EMPTY_THRHD_V  0x1F
-#define I2C_TXFIFO_EMPTY_THRHD_S  5
-/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
-/*description: */
-#define I2C_RXFIFO_FULL_THRHD  0x0000001F
-#define I2C_RXFIFO_FULL_THRHD_M  ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S))
-#define I2C_RXFIFO_FULL_THRHD_V  0x1F
-#define I2C_RXFIFO_FULL_THRHD_S  0
-
-#define I2C_DATA_APB_REG(i)      (0x60013000 + (i) * 0x14000 + 0x001c)
-
-#define I2C_DATA_REG(i)          (REG_I2C_BASE(i) + 0x001c)
-/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: The register represent the byte  data read from rxfifo when use apb fifo access*/
-#define I2C_FIFO_RDATA  0x000000FF
-#define I2C_FIFO_RDATA_M  ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
-#define I2C_FIFO_RDATA_V  0xFF
-#define I2C_FIFO_RDATA_S  0
-
-#define I2C_INT_RAW_REG(i)          (REG_I2C_BASE(i) + 0x0020)
-/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when
- I2C sends more data than nonfifo_tx_thres  it will produce tx_send_empty_int interrupt..*/
-#define I2C_TX_SEND_EMPTY_INT_RAW  (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_RAW_M  (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_RAW_V  0x1
-#define I2C_TX_SEND_EMPTY_INT_RAW_S  12
-/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when
- I2C receives more data  than nonfifo_rx_thres  it will produce rx_rec_full_int interrupt.*/
-#define I2C_RX_REC_FULL_INT_RAW  (BIT(11))
-#define I2C_RX_REC_FULL_INT_RAW_M  (BIT(11))
-#define I2C_RX_REC_FULL_INT_RAW_V  0x1
-#define I2C_RX_REC_FULL_INT_RAW_S  11
-/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for ack_err_int interrupt. when
- I2C receives a wrong ACK bit  it will produce ack_err_int interrupt..*/
-#define I2C_ACK_ERR_INT_RAW  (BIT(10))
-#define I2C_ACK_ERR_INT_RAW_M  (BIT(10))
-#define I2C_ACK_ERR_INT_RAW_V  0x1
-#define I2C_ACK_ERR_INT_RAW_S  10
-/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for trans_start_int interrupt. when
- I2C sends the START bit it will produce trans_start_int interrupt.*/
-#define I2C_TRANS_START_INT_RAW  (BIT(9))
-#define I2C_TRANS_START_INT_RAW_M  (BIT(9))
-#define I2C_TRANS_START_INT_RAW_V  0x1
-#define I2C_TRANS_START_INT_RAW_S  9
-/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for time_out_int interrupt. when
- I2C takes a lot of time to receive a data  it will produce  time_out_int interrupt.*/
-#define I2C_TIME_OUT_INT_RAW  (BIT(8))
-#define I2C_TIME_OUT_INT_RAW_M  (BIT(8))
-#define I2C_TIME_OUT_INT_RAW_V  0x1
-#define I2C_TIME_OUT_INT_RAW_S  8
-/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for trans_complete_int interrupt.
- when I2C Master finished STOP command  it will produce trans_complete_int interrupt.*/
-#define I2C_TRANS_COMPLETE_INT_RAW  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_RAW_V  0x1
-#define I2C_TRANS_COMPLETE_INT_RAW_S  7
-/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for master_tra_comp_int interrupt.
- when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
-#define I2C_MASTER_TRAN_COMP_INT_RAW  (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_RAW_M  (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_RAW_V  0x1
-#define I2C_MASTER_TRAN_COMP_INT_RAW_S  6
-/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when
- I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
-#define I2C_ARBITRATION_LOST_INT_RAW  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_RAW_V  0x1
-#define I2C_ARBITRATION_LOST_INT_RAW_S  5
-/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for slave_tran_comp_int interrupt.
- when I2C Slave detectsthe STOP bit  it will produce slave_tran_comp_int interrupt.*/
-#define I2C_SLAVE_TRAN_COMP_INT_RAW  (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_RAW_M  (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_RAW_V  0x1
-#define I2C_SLAVE_TRAN_COMP_INT_RAW_S  4
-/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for end_detect_int interrupt. when
- I2C deals with  the END command  it will produce end_detect_int interrupt.*/
-#define I2C_END_DETECT_INT_RAW  (BIT(3))
-#define I2C_END_DETECT_INT_RAW_M  (BIT(3))
-#define I2C_END_DETECT_INT_RAW_V  0x1
-#define I2C_END_DETECT_INT_RAW_S  3
-/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for receiving data overflow when
- use apb fifo access.*/
-#define I2C_RXFIFO_OVF_INT_RAW  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_RAW_M  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_RAW_V  0x1
-#define I2C_RXFIFO_OVF_INT_RAW_S  2
-/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/
-#define I2C_TXFIFO_EMPTY_INT_RAW  (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_RAW_V  0x1
-#define I2C_TXFIFO_EMPTY_INT_RAW_S  1
-/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/
-#define I2C_RXFIFO_FULL_INT_RAW  (BIT(0))
-#define I2C_RXFIFO_FULL_INT_RAW_M  (BIT(0))
-#define I2C_RXFIFO_FULL_INT_RAW_V  0x1
-#define I2C_RXFIFO_FULL_INT_RAW_S  0
-
-#define I2C_INT_CLR_REG(i)          (REG_I2C_BASE(i) + 0x0024)
-/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_send_empty_int interrupt.*/
-#define I2C_TX_SEND_EMPTY_INT_CLR  (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_CLR_M  (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_CLR_V  0x1
-#define I2C_TX_SEND_EMPTY_INT_CLR_S  12
-/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rx_rec_full_int interrupt.*/
-#define I2C_RX_REC_FULL_INT_CLR  (BIT(11))
-#define I2C_RX_REC_FULL_INT_CLR_M  (BIT(11))
-#define I2C_RX_REC_FULL_INT_CLR_V  0x1
-#define I2C_RX_REC_FULL_INT_CLR_S  11
-/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to clear the ack_err_int interrupt.*/
-#define I2C_ACK_ERR_INT_CLR  (BIT(10))
-#define I2C_ACK_ERR_INT_CLR_M  (BIT(10))
-#define I2C_ACK_ERR_INT_CLR_V  0x1
-#define I2C_ACK_ERR_INT_CLR_S  10
-/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to clear the trans_start_int interrupt.*/
-#define I2C_TRANS_START_INT_CLR  (BIT(9))
-#define I2C_TRANS_START_INT_CLR_M  (BIT(9))
-#define I2C_TRANS_START_INT_CLR_V  0x1
-#define I2C_TRANS_START_INT_CLR_S  9
-/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to clear the time_out_int interrupt.*/
-#define I2C_TIME_OUT_INT_CLR  (BIT(8))
-#define I2C_TIME_OUT_INT_CLR_M  (BIT(8))
-#define I2C_TIME_OUT_INT_CLR_V  0x1
-#define I2C_TIME_OUT_INT_CLR_S  8
-/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to clear the trans_complete_int interrupt.*/
-#define I2C_TRANS_COMPLETE_INT_CLR  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_CLR_V  0x1
-#define I2C_TRANS_COMPLETE_INT_CLR_S  7
-/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to clear the master_tran_comp interrupt.*/
-#define I2C_MASTER_TRAN_COMP_INT_CLR  (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_CLR_M  (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_CLR_V  0x1
-#define I2C_MASTER_TRAN_COMP_INT_CLR_S  6
-/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to clear the arbitration_lost_int interrupt.*/
-#define I2C_ARBITRATION_LOST_INT_CLR  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_CLR_V  0x1
-#define I2C_ARBITRATION_LOST_INT_CLR_S  5
-/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/
-#define I2C_SLAVE_TRAN_COMP_INT_CLR  (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_CLR_M  (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_CLR_V  0x1
-#define I2C_SLAVE_TRAN_COMP_INT_CLR_S  4
-/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear the end_detect_int interrupt.*/
-#define I2C_END_DETECT_INT_CLR  (BIT(3))
-#define I2C_END_DETECT_INT_CLR_M  (BIT(3))
-#define I2C_END_DETECT_INT_CLR_V  0x1
-#define I2C_END_DETECT_INT_CLR_S  3
-/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/
-#define I2C_RXFIFO_OVF_INT_CLR  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_CLR_M  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_CLR_V  0x1
-#define I2C_RXFIFO_OVF_INT_CLR_S  2
-/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear the txfifo_empty_int interrupt.*/
-#define I2C_TXFIFO_EMPTY_INT_CLR  (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_CLR_V  0x1
-#define I2C_TXFIFO_EMPTY_INT_CLR_S  1
-/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_full_int interrupt.*/
-#define I2C_RXFIFO_FULL_INT_CLR  (BIT(0))
-#define I2C_RXFIFO_FULL_INT_CLR_M  (BIT(0))
-#define I2C_RXFIFO_FULL_INT_CLR_V  0x1
-#define I2C_RXFIFO_FULL_INT_CLR_S  0
-
-#define I2C_INT_ENA_REG(i)          (REG_I2C_BASE(i) + 0x0028)
-/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The enable bit for tx_send_empty_int interrupt.*/
-#define I2C_TX_SEND_EMPTY_INT_ENA  (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_ENA_M  (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_ENA_V  0x1
-#define I2C_TX_SEND_EMPTY_INT_ENA_S  12
-/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The enable bit for rx_rec_full_int interrupt.*/
-#define I2C_RX_REC_FULL_INT_ENA  (BIT(11))
-#define I2C_RX_REC_FULL_INT_ENA_M  (BIT(11))
-#define I2C_RX_REC_FULL_INT_ENA_V  0x1
-#define I2C_RX_REC_FULL_INT_ENA_S  11
-/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The enable bit for ack_err_int interrupt.*/
-#define I2C_ACK_ERR_INT_ENA  (BIT(10))
-#define I2C_ACK_ERR_INT_ENA_M  (BIT(10))
-#define I2C_ACK_ERR_INT_ENA_V  0x1
-#define I2C_ACK_ERR_INT_ENA_S  10
-/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for trans_start_int interrupt.*/
-#define I2C_TRANS_START_INT_ENA  (BIT(9))
-#define I2C_TRANS_START_INT_ENA_M  (BIT(9))
-#define I2C_TRANS_START_INT_ENA_V  0x1
-#define I2C_TRANS_START_INT_ENA_S  9
-/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for time_out_int interrupt.*/
-#define I2C_TIME_OUT_INT_ENA  (BIT(8))
-#define I2C_TIME_OUT_INT_ENA_M  (BIT(8))
-#define I2C_TIME_OUT_INT_ENA_V  0x1
-#define I2C_TIME_OUT_INT_ENA_S  8
-/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for trans_complete_int interrupt.*/
-#define I2C_TRANS_COMPLETE_INT_ENA  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ENA_V  0x1
-#define I2C_TRANS_COMPLETE_INT_ENA_S  7
-/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for master_tran_comp_int interrupt.*/
-#define I2C_MASTER_TRAN_COMP_INT_ENA  (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_ENA_M  (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_ENA_V  0x1
-#define I2C_MASTER_TRAN_COMP_INT_ENA_S  6
-/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for arbitration_lost_int interrupt.*/
-#define I2C_ARBITRATION_LOST_INT_ENA  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ENA_V  0x1
-#define I2C_ARBITRATION_LOST_INT_ENA_S  5
-/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for slave_tran_comp_int interrupt.*/
-#define I2C_SLAVE_TRAN_COMP_INT_ENA  (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_ENA_M  (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_ENA_V  0x1
-#define I2C_SLAVE_TRAN_COMP_INT_ENA_S  4
-/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for end_detect_int interrupt.*/
-#define I2C_END_DETECT_INT_ENA  (BIT(3))
-#define I2C_END_DETECT_INT_ENA_M  (BIT(3))
-#define I2C_END_DETECT_INT_ENA_V  0x1
-#define I2C_END_DETECT_INT_ENA_S  3
-/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for rxfifo_ovf_int interrupt.*/
-#define I2C_RXFIFO_OVF_INT_ENA  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ENA_M  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ENA_V  0x1
-#define I2C_RXFIFO_OVF_INT_ENA_S  2
-/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for txfifo_empty_int interrupt.*/
-#define I2C_TXFIFO_EMPTY_INT_ENA  (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_ENA_V  0x1
-#define I2C_TXFIFO_EMPTY_INT_ENA_S  1
-/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for rxfifo_full_int interrupt.*/
-#define I2C_RXFIFO_FULL_INT_ENA  (BIT(0))
-#define I2C_RXFIFO_FULL_INT_ENA_M  (BIT(0))
-#define I2C_RXFIFO_FULL_INT_ENA_V  0x1
-#define I2C_RXFIFO_FULL_INT_ENA_S  0
-
-#define I2C_INT_STATUS_REG(i)          (REG_I2C_BASE(i) + 0x002c)
-/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The masked interrupt status for tx_send_empty_int interrupt.*/
-#define I2C_TX_SEND_EMPTY_INT_ST  (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_ST_M  (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_ST_V  0x1
-#define I2C_TX_SEND_EMPTY_INT_ST_S  12
-/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The masked interrupt status for rx_rec_full_int interrupt.*/
-#define I2C_RX_REC_FULL_INT_ST  (BIT(11))
-#define I2C_RX_REC_FULL_INT_ST_M  (BIT(11))
-#define I2C_RX_REC_FULL_INT_ST_V  0x1
-#define I2C_RX_REC_FULL_INT_ST_S  11
-/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The masked interrupt status for ack_err_int interrupt.*/
-#define I2C_ACK_ERR_INT_ST  (BIT(10))
-#define I2C_ACK_ERR_INT_ST_M  (BIT(10))
-#define I2C_ACK_ERR_INT_ST_V  0x1
-#define I2C_ACK_ERR_INT_ST_S  10
-/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The masked interrupt status for trans_start_int interrupt.*/
-#define I2C_TRANS_START_INT_ST  (BIT(9))
-#define I2C_TRANS_START_INT_ST_M  (BIT(9))
-#define I2C_TRANS_START_INT_ST_V  0x1
-#define I2C_TRANS_START_INT_ST_S  9
-/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The masked interrupt status for time_out_int interrupt.*/
-#define I2C_TIME_OUT_INT_ST  (BIT(8))
-#define I2C_TIME_OUT_INT_ST_M  (BIT(8))
-#define I2C_TIME_OUT_INT_ST_V  0x1
-#define I2C_TIME_OUT_INT_ST_S  8
-/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The masked interrupt status for trans_complete_int interrupt.*/
-#define I2C_TRANS_COMPLETE_INT_ST  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ST_M  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ST_V  0x1
-#define I2C_TRANS_COMPLETE_INT_ST_S  7
-/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The masked interrupt status for master_tran_comp_int interrupt.*/
-#define I2C_MASTER_TRAN_COMP_INT_ST  (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_ST_M  (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_ST_V  0x1
-#define I2C_MASTER_TRAN_COMP_INT_ST_S  6
-/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The masked interrupt status for arbitration_lost_int interrupt.*/
-#define I2C_ARBITRATION_LOST_INT_ST  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ST_M  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ST_V  0x1
-#define I2C_ARBITRATION_LOST_INT_ST_S  5
-/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/
-#define I2C_SLAVE_TRAN_COMP_INT_ST  (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_ST_M  (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_ST_V  0x1
-#define I2C_SLAVE_TRAN_COMP_INT_ST_S  4
-/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The masked interrupt status for end_detect_int interrupt.*/
-#define I2C_END_DETECT_INT_ST  (BIT(3))
-#define I2C_END_DETECT_INT_ST_M  (BIT(3))
-#define I2C_END_DETECT_INT_ST_V  0x1
-#define I2C_END_DETECT_INT_ST_S  3
-/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/
-#define I2C_RXFIFO_OVF_INT_ST  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ST_M  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ST_V  0x1
-#define I2C_RXFIFO_OVF_INT_ST_S  2
-/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The masked interrupt status for txfifo_empty_int interrupt.*/
-#define I2C_TXFIFO_EMPTY_INT_ST  (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_ST_V  0x1
-#define I2C_TXFIFO_EMPTY_INT_ST_S  1
-/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The masked interrupt status for rxfifo_full_int interrupt.*/
-#define I2C_RXFIFO_FULL_INT_ST  (BIT(0))
-#define I2C_RXFIFO_FULL_INT_ST_M  (BIT(0))
-#define I2C_RXFIFO_FULL_INT_ST_V  0x1
-#define I2C_RXFIFO_FULL_INT_ST_S  0
-
-#define I2C_SDA_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x0030)
-/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: This register is used to configure the clock num I2C used to
- hold the data after the negedge of SCL.*/
-#define I2C_SDA_HOLD_TIME  0x000003FF
-#define I2C_SDA_HOLD_TIME_M  ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
-#define I2C_SDA_HOLD_TIME_V  0x3FF
-#define I2C_SDA_HOLD_TIME_S  0
-
-#define I2C_SDA_SAMPLE_REG(i)          (REG_I2C_BASE(i) + 0x0034)
-/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: This register is used to configure the clock num I2C used to
- sample data on SDA after the posedge of SCL*/
-#define I2C_SDA_SAMPLE_TIME  0x000003FF
-#define I2C_SDA_SAMPLE_TIME_M  ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
-#define I2C_SDA_SAMPLE_TIME_V  0x3FF
-#define I2C_SDA_SAMPLE_TIME_S  0
-
-#define I2C_SCL_HIGH_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0038)
-/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This register is used to configure the clock num during SCL is low level.*/
-#define I2C_SCL_HIGH_PERIOD  0x00003FFF
-#define I2C_SCL_HIGH_PERIOD_M  ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
-#define I2C_SCL_HIGH_PERIOD_V  0x3FFF
-#define I2C_SCL_HIGH_PERIOD_S  0
-
-#define I2C_SCL_START_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x0040)
-/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
-/*description: This register is used to configure the clock num between the
- negedge of SDA and negedge of SCL for start mark.*/
-#define I2C_SCL_START_HOLD_TIME  0x000003FF
-#define I2C_SCL_START_HOLD_TIME_M  ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
-#define I2C_SCL_START_HOLD_TIME_V  0x3FF
-#define I2C_SCL_START_HOLD_TIME_S  0
-
-#define I2C_SCL_RSTART_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x0044)
-/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
-/*description: This register is used to configure the clock num between the
- posedge of SCL and the negedge of SDA for restart mark.*/
-#define I2C_SCL_RSTART_SETUP_TIME  0x000003FF
-#define I2C_SCL_RSTART_SETUP_TIME_M  ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
-#define I2C_SCL_RSTART_SETUP_TIME_V  0x3FF
-#define I2C_SCL_RSTART_SETUP_TIME_S  0
-
-#define I2C_SCL_STOP_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x0048)
-/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This register is used to configure the clock num after the STOP bit's posedge.*/
-#define I2C_SCL_STOP_HOLD_TIME  0x00003FFF
-#define I2C_SCL_STOP_HOLD_TIME_M  ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
-#define I2C_SCL_STOP_HOLD_TIME_V  0x3FFF
-#define I2C_SCL_STOP_HOLD_TIME_S  0
-
-#define I2C_SCL_STOP_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x004C)
-/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: This register is used to configure the clock num between the
- posedge of SCL and the posedge of SDA.*/
-#define I2C_SCL_STOP_SETUP_TIME  0x000003FF
-#define I2C_SCL_STOP_SETUP_TIME_M  ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
-#define I2C_SCL_STOP_SETUP_TIME_V  0x3FF
-#define I2C_SCL_STOP_SETUP_TIME_S  0
-
-#define I2C_SCL_FILTER_CFG_REG(i)          (REG_I2C_BASE(i) + 0x0050)
-/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: This is the filter enable bit for SCL.*/
-#define I2C_SCL_FILTER_EN  (BIT(3))
-#define I2C_SCL_FILTER_EN_M  (BIT(3))
-#define I2C_SCL_FILTER_EN_V  0x1
-#define I2C_SCL_FILTER_EN_S  3
-/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: When input SCL's pulse width is smaller than this register value
-  I2C ignores this pulse.*/
-#define I2C_SCL_FILTER_THRES  0x00000007
-#define I2C_SCL_FILTER_THRES_M  ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))
-#define I2C_SCL_FILTER_THRES_V  0x7
-#define I2C_SCL_FILTER_THRES_S  0
-
-#define I2C_SDA_FILTER_CFG_REG(i)          (REG_I2C_BASE(i) + 0x0054)
-/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: This is the filter enable bit for SDA.*/
-#define I2C_SDA_FILTER_EN  (BIT(3))
-#define I2C_SDA_FILTER_EN_M  (BIT(3))
-#define I2C_SDA_FILTER_EN_V  0x1
-#define I2C_SDA_FILTER_EN_S  3
-/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: When input SCL's pulse width is smaller than this register value
-  I2C ignores this pulse.*/
-#define I2C_SDA_FILTER_THRES  0x00000007
-#define I2C_SDA_FILTER_THRES_M  ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
-#define I2C_SDA_FILTER_THRES_V  0x7
-#define I2C_SDA_FILTER_THRES_S  0
-
-#define I2C_COMD0_REG(i)          (REG_I2C_BASE(i) + 0x0058)
-/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command0 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND0_DONE  (BIT(31))
-#define I2C_COMMAND0_DONE_M  (BIT(31))
-#define I2C_COMMAND0_DONE_V  0x1
-#define I2C_COMMAND0_DONE_S  31
-/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command0. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND0  0x00003FFF
-#define I2C_COMMAND0_M  ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
-#define I2C_COMMAND0_V  0x3FFF
-#define I2C_COMMAND0_S  0
-
-#define I2C_COMD1_REG(i)          (REG_I2C_BASE(i) + 0x005C)
-/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command1 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND1_DONE  (BIT(31))
-#define I2C_COMMAND1_DONE_M  (BIT(31))
-#define I2C_COMMAND1_DONE_V  0x1
-#define I2C_COMMAND1_DONE_S  31
-/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command1. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND1  0x00003FFF
-#define I2C_COMMAND1_M  ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
-#define I2C_COMMAND1_V  0x3FFF
-#define I2C_COMMAND1_S  0
-
-#define I2C_COMD2_REG(i)          (REG_I2C_BASE(i) + 0x0060)
-/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command2 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND2_DONE  (BIT(31))
-#define I2C_COMMAND2_DONE_M  (BIT(31))
-#define I2C_COMMAND2_DONE_V  0x1
-#define I2C_COMMAND2_DONE_S  31
-/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command2. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND2  0x00003FFF
-#define I2C_COMMAND2_M  ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
-#define I2C_COMMAND2_V  0x3FFF
-#define I2C_COMMAND2_S  0
-
-#define I2C_COMD3_REG(i)          (REG_I2C_BASE(i) + 0x0064)
-/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command3 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND3_DONE  (BIT(31))
-#define I2C_COMMAND3_DONE_M  (BIT(31))
-#define I2C_COMMAND3_DONE_V  0x1
-#define I2C_COMMAND3_DONE_S  31
-/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command3. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND3  0x00003FFF
-#define I2C_COMMAND3_M  ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
-#define I2C_COMMAND3_V  0x3FFF
-#define I2C_COMMAND3_S  0
-
-#define I2C_COMD4_REG(i)          (REG_I2C_BASE(i) + 0x0068)
-/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command4 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND4_DONE  (BIT(31))
-#define I2C_COMMAND4_DONE_M  (BIT(31))
-#define I2C_COMMAND4_DONE_V  0x1
-#define I2C_COMMAND4_DONE_S  31
-/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command4. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND4  0x00003FFF
-#define I2C_COMMAND4_M  ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
-#define I2C_COMMAND4_V  0x3FFF
-#define I2C_COMMAND4_S  0
-
-#define I2C_COMD5_REG(i)          (REG_I2C_BASE(i) + 0x006C)
-/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command5 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND5_DONE  (BIT(31))
-#define I2C_COMMAND5_DONE_M  (BIT(31))
-#define I2C_COMMAND5_DONE_V  0x1
-#define I2C_COMMAND5_DONE_S  31
-/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command5. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND5  0x00003FFF
-#define I2C_COMMAND5_M  ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
-#define I2C_COMMAND5_V  0x3FFF
-#define I2C_COMMAND5_S  0
-
-#define I2C_COMD6_REG(i)          (REG_I2C_BASE(i) + 0x0070)
-/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command6 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND6_DONE  (BIT(31))
-#define I2C_COMMAND6_DONE_M  (BIT(31))
-#define I2C_COMMAND6_DONE_V  0x1
-#define I2C_COMMAND6_DONE_S  31
-/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command6. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND6  0x00003FFF
-#define I2C_COMMAND6_M  ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
-#define I2C_COMMAND6_V  0x3FFF
-#define I2C_COMMAND6_S  0
-
-#define I2C_COMD7_REG(i)          (REG_I2C_BASE(i) + 0x0074)
-/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command7 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND7_DONE  (BIT(31))
-#define I2C_COMMAND7_DONE_M  (BIT(31))
-#define I2C_COMMAND7_DONE_V  0x1
-#define I2C_COMMAND7_DONE_S  31
-/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command7. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND7  0x00003FFF
-#define I2C_COMMAND7_M  ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
-#define I2C_COMMAND7_V  0x3FFF
-#define I2C_COMMAND7_S  0
-
-#define I2C_COMD8_REG(i)          (REG_I2C_BASE(i) + 0x0078)
-/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command8 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND8_DONE  (BIT(31))
-#define I2C_COMMAND8_DONE_M  (BIT(31))
-#define I2C_COMMAND8_DONE_V  0x1
-#define I2C_COMMAND8_DONE_S  31
-/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command8. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND8  0x00003FFF
-#define I2C_COMMAND8_M  ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S))
-#define I2C_COMMAND8_V  0x3FFF
-#define I2C_COMMAND8_S  0
-
-#define I2C_COMD9_REG(i)          (REG_I2C_BASE(i) + 0x007C)
-/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command9 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND9_DONE  (BIT(31))
-#define I2C_COMMAND9_DONE_M  (BIT(31))
-#define I2C_COMMAND9_DONE_V  0x1
-#define I2C_COMMAND9_DONE_S  31
-/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command9. It consists of three part. op_code
- is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND9  0x00003FFF
-#define I2C_COMMAND9_M  ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S))
-#define I2C_COMMAND9_V  0x3FFF
-#define I2C_COMMAND9_S  0
-
-#define I2C_COMD10_REG(i)          (REG_I2C_BASE(i) + 0x0080)
-/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command10 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND10_DONE  (BIT(31))
-#define I2C_COMMAND10_DONE_M  (BIT(31))
-#define I2C_COMMAND10_DONE_V  0x1
-#define I2C_COMMAND10_DONE_S  31
-/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command10. It consists of three part.
- op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND10  0x00003FFF
-#define I2C_COMMAND10_M  ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S))
-#define I2C_COMMAND10_V  0x3FFF
-#define I2C_COMMAND10_S  0
-
-#define I2C_COMD11_REG(i)          (REG_I2C_BASE(i) + 0x0084)
-/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command11 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND11_DONE  (BIT(31))
-#define I2C_COMMAND11_DONE_M  (BIT(31))
-#define I2C_COMMAND11_DONE_V  0x1
-#define I2C_COMMAND11_DONE_S  31
-/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command11. It consists of three part.
- op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND11  0x00003FFF
-#define I2C_COMMAND11_M  ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S))
-#define I2C_COMMAND11_V  0x3FFF
-#define I2C_COMMAND11_S  0
-
-#define I2C_COMD12_REG(i)          (REG_I2C_BASE(i) + 0x0088)
-/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command12 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND12_DONE  (BIT(31))
-#define I2C_COMMAND12_DONE_M  (BIT(31))
-#define I2C_COMMAND12_DONE_V  0x1
-#define I2C_COMMAND12_DONE_S  31
-/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command12. It consists of three part.
- op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND12  0x00003FFF
-#define I2C_COMMAND12_M  ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S))
-#define I2C_COMMAND12_V  0x3FFF
-#define I2C_COMMAND12_S  0
-
-#define I2C_COMD13_REG(i)          (REG_I2C_BASE(i) + 0x008C)
-/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command13 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND13_DONE  (BIT(31))
-#define I2C_COMMAND13_DONE_M  (BIT(31))
-#define I2C_COMMAND13_DONE_V  0x1
-#define I2C_COMMAND13_DONE_S  31
-/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command13. It consists of three part.
- op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND13  0x00003FFF
-#define I2C_COMMAND13_M  ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S))
-#define I2C_COMMAND13_V  0x3FFF
-#define I2C_COMMAND13_S  0
-
-#define I2C_COMD14_REG(i)          (REG_I2C_BASE(i) + 0x0090)
-/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command14 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND14_DONE  (BIT(31))
-#define I2C_COMMAND14_DONE_M  (BIT(31))
-#define I2C_COMMAND14_DONE_V  0x1
-#define I2C_COMMAND14_DONE_S  31
-/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command14. It consists of three part.
- op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND14  0x00003FFF
-#define I2C_COMMAND14_M  ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S))
-#define I2C_COMMAND14_V  0x3FFF
-#define I2C_COMMAND14_S  0
-
-#define I2C_COMD15_REG(i)          (REG_I2C_BASE(i) + 0x0094)
-/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When command15 is done in I2C Master mode  this bit changes to high level.*/
-#define I2C_COMMAND15_DONE  (BIT(31))
-#define I2C_COMMAND15_DONE_M  (BIT(31))
-#define I2C_COMMAND15_DONE_V  0x1
-#define I2C_COMMAND15_DONE_S  31
-/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: This is the content of command15. It consists of three part.
- op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-#define I2C_COMMAND15  0x00003FFF
-#define I2C_COMMAND15_M  ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S))
-#define I2C_COMMAND15_V  0x3FFF
-#define I2C_COMMAND15_S  0
-
-#define I2C_DATE_REG(i)          (REG_I2C_BASE(i) + 0x00F8)
-/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
-/*description: */
-#define I2C_DATE  0xFFFFFFFF
-#define I2C_DATE_M  ((I2C_DATE_V)<<(I2C_DATE_S))
-#define I2C_DATE_V  0xFFFFFFFF
-#define I2C_DATE_S  0
-
-#define I2C_FIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x0100)
-
-
-
-
-#endif /*_SOC_I2C_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/i2c_struct.h b/tools/sdk/include/soc/soc/i2c_struct.h
deleted file mode 100644
index c60bb1e7c18..00000000000
--- a/tools/sdk/include/soc/soc/i2c_struct.h
+++ /dev/null
@@ -1,301 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_I2C_STRUCT_H_
-#define _SOC_I2C_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t period:14;             /*This register is used to configure the  low level width of SCL clock.*/
-            uint32_t reserved14:    18;
-        };
-        uint32_t val;
-    } scl_low_period;
-    union {
-        struct {
-            uint32_t sda_force_out:    1;           /*1：normally output sda data   0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
-            uint32_t scl_force_out:    1;           /*1：normally output scl clock  0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal  scl_oe is the enable bit for the internal output scl signal)*/
-            uint32_t sample_scl_level: 1;           /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/
-            uint32_t reserved3:        1;
-            uint32_t ms_mode:          1;           /*Set this bit to configure the module as i2c master  clear this bit to configure the module as i2c slave.*/
-            uint32_t trans_start:      1;           /*Set this bit to start sending data in tx_fifo.*/
-            uint32_t tx_lsb_first:     1;           /*This bit is used to control the sending mode for  data need to be send. 1：receive data from most significant bit    0：receive data from least significant bit*/
-            uint32_t rx_lsb_first:     1;           /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit    0：receive data from least significant bit*/
-            uint32_t clk_en:           1;           /*This is the clock gating control bit for reading or writing registers.*/
-            uint32_t reserved9:       23;
-        };
-        uint32_t val;
-    } ctr;
-    union {
-        struct {
-            uint32_t ack_rec:             1;        /*This register stores the value of ACK bit.*/
-            uint32_t slave_rw:            1;        /*when in slave mode  1：master read slave  0: master write slave.*/
-            uint32_t time_out:            1;        /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/
-            uint32_t arb_lost:            1;        /*when I2C lost control of SDA line  this register changes to high level.*/
-            uint32_t bus_busy:            1;        /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
-            uint32_t slave_addressed:     1;        /*when configured as i2c slave  and the address send by master is equal to slave's address  then this bit will be high level.*/
-            uint32_t byte_trans:          1;        /*This register changes to high level when one byte is transferred.*/
-            uint32_t reserved7:           1;
-            uint32_t rx_fifo_cnt:         6;        /*This register represent the amount of data need to send.*/
-            uint32_t reserved14:          4;
-            uint32_t tx_fifo_cnt:         6;        /*This register stores the amount of received data  in ram.*/
-            uint32_t scl_main_state_last: 3;        /*This register stores the value of state machine for i2c module.  3'h0: SCL_MAIN_IDLE  3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS  3'h3: SCL_RX_DATA  3'h4 SCL_TX_DATA  3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
-            uint32_t reserved27:          1;
-            uint32_t scl_state_last:      3;        /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE  3'h1:SCL_START   3'h2:SCL_LOW_EDGE  3'h3: SCL_LOW   3'h4:SCL_HIGH_EDGE   3'h5:SCL_HIGH  3'h6:SCL_STOP*/
-            uint32_t reserved31:          1;
-        };
-        uint32_t val;
-    } status_reg;
-    union {
-        struct {
-            uint32_t tout:      20;                 /*This register is used to configure the max clock number of receiving a data, unit: APB clock cycle.*/
-            uint32_t reserved20:12;
-        };
-        uint32_t val;
-    } timeout;
-    union {
-        struct {
-            uint32_t addr:       15;                /*when configured as i2c slave  this register is used to configure slave's address.*/
-            uint32_t reserved15: 16;
-            uint32_t en_10bit:    1;                /*This register is used to enable slave 10bit address mode.*/
-        };
-        uint32_t val;
-    } slave_addr;
-    union {
-        struct {
-            uint32_t rx_fifo_start_addr: 5;         /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
-            uint32_t rx_fifo_end_addr:   5;         /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
-            uint32_t tx_fifo_start_addr: 5;         /*This is the offset address of the first  sending data as described in nonfifo_tx_thres register.*/
-            uint32_t tx_fifo_end_addr:   5;         /*This is the offset address of the last  sending data as described in nonfifo_tx_thres register.*/
-            uint32_t reserved20:        12;
-        };
-        uint32_t val;
-    } fifo_st;
-    union {
-        struct {
-            uint32_t rx_fifo_full_thrhd: 5;
-            uint32_t tx_fifo_empty_thrhd:5;         /*Config tx_fifo empty threhd value when using apb fifo access*/
-            uint32_t nonfifo_en:         1;         /*Set this bit to enble apb nonfifo access.*/
-            uint32_t fifo_addr_cfg_en:   1;         /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/
-            uint32_t rx_fifo_rst:        1;         /*Set this bit to reset rx fifo when using apb fifo access.*/
-            uint32_t tx_fifo_rst:        1;         /*Set this bit to reset tx fifo when using apb fifo access.*/
-            uint32_t nonfifo_rx_thres:   6;         /*when I2C receives more than nonfifo_rx_thres data  it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
-            uint32_t nonfifo_tx_thres:   6;         /*when I2C sends more than nonfifo_tx_thres data  it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
-            uint32_t reserved26:         6;
-        };
-        uint32_t val;
-    } fifo_conf;
-    union {
-        struct {
-            uint8_t data;                           /*The register represent the byte  data read from rx_fifo when use apb fifo access*/
-            uint8_t reserved[3];
-        };
-        uint32_t val;
-    } fifo_data;
-    union {
-        struct {
-            uint32_t rx_fifo_full:     1;           /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
-            uint32_t tx_fifo_empty:    1;           /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
-            uint32_t rx_fifo_ovf:      1;           /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
-            uint32_t end_detect:       1;           /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with  the END command  it will produce end_detect_int interrupt.*/
-            uint32_t slave_tran_comp:  1;           /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit  it will produce slave_tran_comp_int interrupt.*/
-            uint32_t arbitration_lost: 1;           /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
-            uint32_t master_tran_comp: 1;           /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
-            uint32_t trans_complete:   1;           /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command  it will produce trans_complete_int interrupt.*/
-            uint32_t time_out:         1;           /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data  it will produce  time_out_int interrupt.*/
-            uint32_t trans_start:      1;           /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/
-            uint32_t ack_err:          1;           /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit  it will produce ack_err_int interrupt..*/
-            uint32_t rx_rec_full:      1;           /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data  than nonfifo_rx_thres  it will produce rx_rec_full_int interrupt.*/
-            uint32_t tx_send_empty:    1;           /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres  it will produce tx_send_empty_int interrupt..*/
-            uint32_t reserved13:      19;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rx_fifo_full:     1;           /*Set this bit to clear the rx_fifo_full_int interrupt.*/
-            uint32_t tx_fifo_empty:    1;           /*Set this bit to clear the tx_fifo_empty_int interrupt.*/
-            uint32_t rx_fifo_ovf:      1;           /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/
-            uint32_t end_detect:       1;           /*Set this bit to clear the end_detect_int interrupt.*/
-            uint32_t slave_tran_comp:  1;           /*Set this bit to clear the slave_tran_comp_int interrupt.*/
-            uint32_t arbitration_lost: 1;           /*Set this bit to clear the arbitration_lost_int interrupt.*/
-            uint32_t master_tran_comp: 1;           /*Set this bit to clear the master_tran_comp interrupt.*/
-            uint32_t trans_complete:   1;           /*Set this bit to clear the trans_complete_int interrupt.*/
-            uint32_t time_out:         1;           /*Set this bit to clear the time_out_int interrupt.*/
-            uint32_t trans_start:      1;           /*Set this bit to clear the trans_start_int interrupt.*/
-            uint32_t ack_err:          1;           /*Set this bit to clear the ack_err_int interrupt.*/
-            uint32_t rx_rec_full:      1;           /*Set this bit to clear the rx_rec_full_int interrupt.*/
-            uint32_t tx_send_empty:    1;           /*Set this bit to clear the tx_send_empty_int interrupt.*/
-            uint32_t reserved13:      19;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t rx_fifo_full:     1;           /*The enable bit for rx_fifo_full_int interrupt.*/
-            uint32_t tx_fifo_empty:    1;           /*The enable bit for tx_fifo_empty_int interrupt.*/
-            uint32_t rx_fifo_ovf:      1;           /*The enable bit for rx_fifo_ovf_int interrupt.*/
-            uint32_t end_detect:       1;           /*The enable bit for end_detect_int interrupt.*/
-            uint32_t slave_tran_comp:  1;           /*The enable bit for slave_tran_comp_int interrupt.*/
-            uint32_t arbitration_lost: 1;           /*The enable bit for arbitration_lost_int interrupt.*/
-            uint32_t master_tran_comp: 1;           /*The enable bit for master_tran_comp_int interrupt.*/
-            uint32_t trans_complete:   1;           /*The enable bit for trans_complete_int interrupt.*/
-            uint32_t time_out:         1;           /*The enable bit for time_out_int interrupt.*/
-            uint32_t trans_start:      1;           /*The enable bit for trans_start_int interrupt.*/
-            uint32_t ack_err:          1;           /*The enable bit for ack_err_int interrupt.*/
-            uint32_t rx_rec_full:      1;           /*The enable bit for rx_rec_full_int interrupt.*/
-            uint32_t tx_send_empty:    1;           /*The enable bit for tx_send_empty_int interrupt.*/
-            uint32_t reserved13:      19;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t rx_fifo_full:     1;            /*The masked interrupt status for rx_fifo_full_int interrupt.*/
-            uint32_t tx_fifo_empty:    1;            /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
-            uint32_t rx_fifo_ovf:      1;            /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
-            uint32_t end_detect:       1;            /*The masked interrupt status for end_detect_int interrupt.*/
-            uint32_t slave_tran_comp:  1;            /*The masked interrupt status for slave_tran_comp_int interrupt.*/
-            uint32_t arbitration_lost: 1;            /*The masked interrupt status for arbitration_lost_int interrupt.*/
-            uint32_t master_tran_comp: 1;            /*The masked interrupt status for master_tran_comp_int interrupt.*/
-            uint32_t trans_complete:   1;            /*The masked interrupt status for trans_complete_int interrupt.*/
-            uint32_t time_out:         1;            /*The masked interrupt status for time_out_int interrupt.*/
-            uint32_t trans_start:      1;            /*The masked interrupt status for trans_start_int interrupt.*/
-            uint32_t ack_err:          1;            /*The masked interrupt status for ack_err_int interrupt.*/
-            uint32_t rx_rec_full:      1;            /*The masked interrupt status for rx_rec_full_int interrupt.*/
-            uint32_t tx_send_empty:    1;            /*The masked interrupt status for tx_send_empty_int interrupt.*/
-            uint32_t reserved13:      19;
-        };
-        uint32_t val;
-    } int_status;
-    union {
-        struct {
-            uint32_t time:        10;                /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
-            uint32_t reserved10:  22;
-        };
-        uint32_t val;
-    } sda_hold;
-    union {
-        struct {
-            uint32_t time:       10;                 /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
-            uint32_t reserved10: 22;
-        };
-        uint32_t val;
-    } sda_sample;
-    union {
-        struct {
-            uint32_t period:     14;                 /*This register is used to configure the clock num during SCL is low level.*/
-            uint32_t reserved14: 18;
-        };
-        uint32_t val;
-    } scl_high_period;
-    uint32_t reserved_3c;
-    union {
-        struct {
-            uint32_t time:       10;                /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
-            uint32_t reserved10: 22;
-        };
-        uint32_t val;
-    } scl_start_hold;
-    union {
-        struct {
-            uint32_t time:       10;                /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
-            uint32_t reserved10: 22;
-        };
-        uint32_t val;
-    } scl_rstart_setup;
-    union {
-        struct {
-            uint32_t time:       14;                /*This register is used to configure the clock num after the STOP bit's posedge.*/
-            uint32_t reserved14: 18;
-        };
-        uint32_t val;
-    } scl_stop_hold;
-    union {
-        struct {
-            uint32_t time:       10;                /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
-            uint32_t reserved10: 22;
-        };
-        uint32_t val;
-    } scl_stop_setup;
-    union {
-        struct {
-            uint32_t thres:      3;                 /*When input SCL's pulse width is smaller than this register value  I2C ignores this pulse.*/
-            uint32_t en:         1;                 /*This is the filter enable bit for SCL.*/
-            uint32_t reserved4: 28;
-        };
-        uint32_t val;
-    } scl_filter_cfg;
-    union {
-        struct {
-            uint32_t thres:      3;                 /*When input SCL's pulse width is smaller than this register value  I2C ignores this pulse.*/
-            uint32_t en:         1;                 /*This is the filter enable bit for SDA.*/
-            uint32_t reserved4: 28;
-        };
-        uint32_t val;
-    } sda_filter_cfg;
-    union {
-        struct {
-            uint32_t byte_num:      8;              /*Byte_num represent the number of data need to be send or data need to be received.*/
-            uint32_t ack_en:        1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-            uint32_t ack_exp:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-            uint32_t ack_val:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-            uint32_t op_code:       3;              /*op_code is the command  0：RSTART   1：WRITE  2：READ  3：STOP . 4:END.*/
-            uint32_t reserved14:   17;
-            uint32_t done:  1;                      /*When command0 is done in I2C Master mode  this bit changes to high level.*/
-        };
-        uint32_t val;
-    } command[16];
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t date;                                  /**/
-    uint32_t reserved_fc;
-    uint32_t ram_data[32];                          /*This the start address for ram when use apb nonfifo access.*/
-} i2c_dev_t;
-extern i2c_dev_t I2C0;
-extern i2c_dev_t I2C1;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_I2C_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/i2s_reg.h b/tools/sdk/include/soc/soc/i2s_reg.h
deleted file mode 100644
index 3473c087cae..00000000000
--- a/tools/sdk/include/soc/soc/i2s_reg.h
+++ /dev/null
@@ -1,1527 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_I2S_REG_H_
-#define _SOC_I2S_REG_H_
-
-#include "soc.h"
-
-#define REG_I2S_BASE( i ) ( DR_REG_I2S_BASE + ((i)*0x1E000))
-
-
-#define I2S_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0008)
-/* I2S_SIG_LOOPBACK : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define I2S_SIG_LOOPBACK  (BIT(18))
-#define I2S_SIG_LOOPBACK_M  (BIT(18))
-#define I2S_SIG_LOOPBACK_V  0x1
-#define I2S_SIG_LOOPBACK_S  18
-/* I2S_RX_MSB_RIGHT : R/W ;bitpos:[17] ;default: 1'b1 ; */
-/*description: */
-#define I2S_RX_MSB_RIGHT  (BIT(17))
-#define I2S_RX_MSB_RIGHT_M  (BIT(17))
-#define I2S_RX_MSB_RIGHT_V  0x1
-#define I2S_RX_MSB_RIGHT_S  17
-/* I2S_TX_MSB_RIGHT : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: */
-#define I2S_TX_MSB_RIGHT  (BIT(16))
-#define I2S_TX_MSB_RIGHT_M  (BIT(16))
-#define I2S_TX_MSB_RIGHT_V  0x1
-#define I2S_TX_MSB_RIGHT_S  16
-/* I2S_RX_MONO : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_MONO  (BIT(15))
-#define I2S_RX_MONO_M  (BIT(15))
-#define I2S_RX_MONO_V  0x1
-#define I2S_RX_MONO_S  15
-/* I2S_TX_MONO : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_MONO  (BIT(14))
-#define I2S_TX_MONO_M  (BIT(14))
-#define I2S_TX_MONO_V  0x1
-#define I2S_TX_MONO_S  14
-/* I2S_RX_SHORT_SYNC : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_SHORT_SYNC  (BIT(13))
-#define I2S_RX_SHORT_SYNC_M  (BIT(13))
-#define I2S_RX_SHORT_SYNC_V  0x1
-#define I2S_RX_SHORT_SYNC_S  13
-/* I2S_TX_SHORT_SYNC : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_SHORT_SYNC  (BIT(12))
-#define I2S_TX_SHORT_SYNC_M  (BIT(12))
-#define I2S_TX_SHORT_SYNC_V  0x1
-#define I2S_TX_SHORT_SYNC_S  12
-/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_MSB_SHIFT  (BIT(11))
-#define I2S_RX_MSB_SHIFT_M  (BIT(11))
-#define I2S_RX_MSB_SHIFT_V  0x1
-#define I2S_RX_MSB_SHIFT_S  11
-/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_MSB_SHIFT  (BIT(10))
-#define I2S_TX_MSB_SHIFT_M  (BIT(10))
-#define I2S_TX_MSB_SHIFT_V  0x1
-#define I2S_TX_MSB_SHIFT_S  10
-/* I2S_RX_RIGHT_FIRST : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: */
-#define I2S_RX_RIGHT_FIRST  (BIT(9))
-#define I2S_RX_RIGHT_FIRST_M  (BIT(9))
-#define I2S_RX_RIGHT_FIRST_V  0x1
-#define I2S_RX_RIGHT_FIRST_S  9
-/* I2S_TX_RIGHT_FIRST : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define I2S_TX_RIGHT_FIRST  (BIT(8))
-#define I2S_TX_RIGHT_FIRST_M  (BIT(8))
-#define I2S_TX_RIGHT_FIRST_V  0x1
-#define I2S_TX_RIGHT_FIRST_S  8
-/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_SLAVE_MOD  (BIT(7))
-#define I2S_RX_SLAVE_MOD_M  (BIT(7))
-#define I2S_RX_SLAVE_MOD_V  0x1
-#define I2S_RX_SLAVE_MOD_S  7
-/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_SLAVE_MOD  (BIT(6))
-#define I2S_TX_SLAVE_MOD_M  (BIT(6))
-#define I2S_TX_SLAVE_MOD_V  0x1
-#define I2S_TX_SLAVE_MOD_S  6
-/* I2S_RX_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_START  (BIT(5))
-#define I2S_RX_START_M  (BIT(5))
-#define I2S_RX_START_V  0x1
-#define I2S_RX_START_S  5
-/* I2S_TX_START : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_START  (BIT(4))
-#define I2S_TX_START_M  (BIT(4))
-#define I2S_TX_START_V  0x1
-#define I2S_TX_START_S  4
-/* I2S_RX_FIFO_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_FIFO_RESET  (BIT(3))
-#define I2S_RX_FIFO_RESET_M  (BIT(3))
-#define I2S_RX_FIFO_RESET_V  0x1
-#define I2S_RX_FIFO_RESET_S  3
-/* I2S_TX_FIFO_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_FIFO_RESET  (BIT(2))
-#define I2S_TX_FIFO_RESET_M  (BIT(2))
-#define I2S_TX_FIFO_RESET_V  0x1
-#define I2S_TX_FIFO_RESET_S  2
-/* I2S_RX_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_RESET  (BIT(1))
-#define I2S_RX_RESET_M  (BIT(1))
-#define I2S_RX_RESET_V  0x1
-#define I2S_RX_RESET_S  1
-/* I2S_TX_RESET : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_RESET  (BIT(0))
-#define I2S_TX_RESET_M  (BIT(0))
-#define I2S_TX_RESET_V  0x1
-#define I2S_TX_RESET_S  0
-
-#define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0x000c)
-/* I2S_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_TOTAL_EOF_INT_RAW  (BIT(16))
-#define I2S_OUT_TOTAL_EOF_INT_RAW_M  (BIT(16))
-#define I2S_OUT_TOTAL_EOF_INT_RAW_V  0x1
-#define I2S_OUT_TOTAL_EOF_INT_RAW_S  16
-/* I2S_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DSCR_EMPTY_INT_RAW  (BIT(15))
-#define I2S_IN_DSCR_EMPTY_INT_RAW_M  (BIT(15))
-#define I2S_IN_DSCR_EMPTY_INT_RAW_V  0x1
-#define I2S_IN_DSCR_EMPTY_INT_RAW_S  15
-/* I2S_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_DSCR_ERR_INT_RAW  (BIT(14))
-#define I2S_OUT_DSCR_ERR_INT_RAW_M  (BIT(14))
-#define I2S_OUT_DSCR_ERR_INT_RAW_V  0x1
-#define I2S_OUT_DSCR_ERR_INT_RAW_S  14
-/* I2S_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DSCR_ERR_INT_RAW  (BIT(13))
-#define I2S_IN_DSCR_ERR_INT_RAW_M  (BIT(13))
-#define I2S_IN_DSCR_ERR_INT_RAW_V  0x1
-#define I2S_IN_DSCR_ERR_INT_RAW_S  13
-/* I2S_OUT_EOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_EOF_INT_RAW  (BIT(12))
-#define I2S_OUT_EOF_INT_RAW_M  (BIT(12))
-#define I2S_OUT_EOF_INT_RAW_V  0x1
-#define I2S_OUT_EOF_INT_RAW_S  12
-/* I2S_OUT_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_DONE_INT_RAW  (BIT(11))
-#define I2S_OUT_DONE_INT_RAW_M  (BIT(11))
-#define I2S_OUT_DONE_INT_RAW_V  0x1
-#define I2S_OUT_DONE_INT_RAW_S  11
-/* I2S_IN_ERR_EOF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_ERR_EOF_INT_RAW  (BIT(10))
-#define I2S_IN_ERR_EOF_INT_RAW_M  (BIT(10))
-#define I2S_IN_ERR_EOF_INT_RAW_V  0x1
-#define I2S_IN_ERR_EOF_INT_RAW_S  10
-/* I2S_IN_SUC_EOF_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_SUC_EOF_INT_RAW  (BIT(9))
-#define I2S_IN_SUC_EOF_INT_RAW_M  (BIT(9))
-#define I2S_IN_SUC_EOF_INT_RAW_V  0x1
-#define I2S_IN_SUC_EOF_INT_RAW_S  9
-/* I2S_IN_DONE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DONE_INT_RAW  (BIT(8))
-#define I2S_IN_DONE_INT_RAW_M  (BIT(8))
-#define I2S_IN_DONE_INT_RAW_V  0x1
-#define I2S_IN_DONE_INT_RAW_S  8
-/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_HUNG_INT_RAW  (BIT(7))
-#define I2S_TX_HUNG_INT_RAW_M  (BIT(7))
-#define I2S_TX_HUNG_INT_RAW_V  0x1
-#define I2S_TX_HUNG_INT_RAW_S  7
-/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_HUNG_INT_RAW  (BIT(6))
-#define I2S_RX_HUNG_INT_RAW_M  (BIT(6))
-#define I2S_RX_HUNG_INT_RAW_V  0x1
-#define I2S_RX_HUNG_INT_RAW_S  6
-/* I2S_TX_REMPTY_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_REMPTY_INT_RAW  (BIT(5))
-#define I2S_TX_REMPTY_INT_RAW_M  (BIT(5))
-#define I2S_TX_REMPTY_INT_RAW_V  0x1
-#define I2S_TX_REMPTY_INT_RAW_S  5
-/* I2S_TX_WFULL_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_WFULL_INT_RAW  (BIT(4))
-#define I2S_TX_WFULL_INT_RAW_M  (BIT(4))
-#define I2S_TX_WFULL_INT_RAW_V  0x1
-#define I2S_TX_WFULL_INT_RAW_S  4
-/* I2S_RX_REMPTY_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_REMPTY_INT_RAW  (BIT(3))
-#define I2S_RX_REMPTY_INT_RAW_M  (BIT(3))
-#define I2S_RX_REMPTY_INT_RAW_V  0x1
-#define I2S_RX_REMPTY_INT_RAW_S  3
-/* I2S_RX_WFULL_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_WFULL_INT_RAW  (BIT(2))
-#define I2S_RX_WFULL_INT_RAW_M  (BIT(2))
-#define I2S_RX_WFULL_INT_RAW_V  0x1
-#define I2S_RX_WFULL_INT_RAW_S  2
-/* I2S_TX_PUT_DATA_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_PUT_DATA_INT_RAW  (BIT(1))
-#define I2S_TX_PUT_DATA_INT_RAW_M  (BIT(1))
-#define I2S_TX_PUT_DATA_INT_RAW_V  0x1
-#define I2S_TX_PUT_DATA_INT_RAW_S  1
-/* I2S_RX_TAKE_DATA_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_TAKE_DATA_INT_RAW  (BIT(0))
-#define I2S_RX_TAKE_DATA_INT_RAW_M  (BIT(0))
-#define I2S_RX_TAKE_DATA_INT_RAW_V  0x1
-#define I2S_RX_TAKE_DATA_INT_RAW_S  0
-
-#define I2S_INT_ST_REG(i)          (REG_I2S_BASE(i) + 0x0010)
-/* I2S_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_TOTAL_EOF_INT_ST  (BIT(16))
-#define I2S_OUT_TOTAL_EOF_INT_ST_M  (BIT(16))
-#define I2S_OUT_TOTAL_EOF_INT_ST_V  0x1
-#define I2S_OUT_TOTAL_EOF_INT_ST_S  16
-/* I2S_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DSCR_EMPTY_INT_ST  (BIT(15))
-#define I2S_IN_DSCR_EMPTY_INT_ST_M  (BIT(15))
-#define I2S_IN_DSCR_EMPTY_INT_ST_V  0x1
-#define I2S_IN_DSCR_EMPTY_INT_ST_S  15
-/* I2S_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_DSCR_ERR_INT_ST  (BIT(14))
-#define I2S_OUT_DSCR_ERR_INT_ST_M  (BIT(14))
-#define I2S_OUT_DSCR_ERR_INT_ST_V  0x1
-#define I2S_OUT_DSCR_ERR_INT_ST_S  14
-/* I2S_IN_DSCR_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DSCR_ERR_INT_ST  (BIT(13))
-#define I2S_IN_DSCR_ERR_INT_ST_M  (BIT(13))
-#define I2S_IN_DSCR_ERR_INT_ST_V  0x1
-#define I2S_IN_DSCR_ERR_INT_ST_S  13
-/* I2S_OUT_EOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_EOF_INT_ST  (BIT(12))
-#define I2S_OUT_EOF_INT_ST_M  (BIT(12))
-#define I2S_OUT_EOF_INT_ST_V  0x1
-#define I2S_OUT_EOF_INT_ST_S  12
-/* I2S_OUT_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_DONE_INT_ST  (BIT(11))
-#define I2S_OUT_DONE_INT_ST_M  (BIT(11))
-#define I2S_OUT_DONE_INT_ST_V  0x1
-#define I2S_OUT_DONE_INT_ST_S  11
-/* I2S_IN_ERR_EOF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_ERR_EOF_INT_ST  (BIT(10))
-#define I2S_IN_ERR_EOF_INT_ST_M  (BIT(10))
-#define I2S_IN_ERR_EOF_INT_ST_V  0x1
-#define I2S_IN_ERR_EOF_INT_ST_S  10
-/* I2S_IN_SUC_EOF_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_SUC_EOF_INT_ST  (BIT(9))
-#define I2S_IN_SUC_EOF_INT_ST_M  (BIT(9))
-#define I2S_IN_SUC_EOF_INT_ST_V  0x1
-#define I2S_IN_SUC_EOF_INT_ST_S  9
-/* I2S_IN_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DONE_INT_ST  (BIT(8))
-#define I2S_IN_DONE_INT_ST_M  (BIT(8))
-#define I2S_IN_DONE_INT_ST_V  0x1
-#define I2S_IN_DONE_INT_ST_S  8
-/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_HUNG_INT_ST  (BIT(7))
-#define I2S_TX_HUNG_INT_ST_M  (BIT(7))
-#define I2S_TX_HUNG_INT_ST_V  0x1
-#define I2S_TX_HUNG_INT_ST_S  7
-/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_HUNG_INT_ST  (BIT(6))
-#define I2S_RX_HUNG_INT_ST_M  (BIT(6))
-#define I2S_RX_HUNG_INT_ST_V  0x1
-#define I2S_RX_HUNG_INT_ST_S  6
-/* I2S_TX_REMPTY_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_REMPTY_INT_ST  (BIT(5))
-#define I2S_TX_REMPTY_INT_ST_M  (BIT(5))
-#define I2S_TX_REMPTY_INT_ST_V  0x1
-#define I2S_TX_REMPTY_INT_ST_S  5
-/* I2S_TX_WFULL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_WFULL_INT_ST  (BIT(4))
-#define I2S_TX_WFULL_INT_ST_M  (BIT(4))
-#define I2S_TX_WFULL_INT_ST_V  0x1
-#define I2S_TX_WFULL_INT_ST_S  4
-/* I2S_RX_REMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_REMPTY_INT_ST  (BIT(3))
-#define I2S_RX_REMPTY_INT_ST_M  (BIT(3))
-#define I2S_RX_REMPTY_INT_ST_V  0x1
-#define I2S_RX_REMPTY_INT_ST_S  3
-/* I2S_RX_WFULL_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_WFULL_INT_ST  (BIT(2))
-#define I2S_RX_WFULL_INT_ST_M  (BIT(2))
-#define I2S_RX_WFULL_INT_ST_V  0x1
-#define I2S_RX_WFULL_INT_ST_S  2
-/* I2S_TX_PUT_DATA_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_PUT_DATA_INT_ST  (BIT(1))
-#define I2S_TX_PUT_DATA_INT_ST_M  (BIT(1))
-#define I2S_TX_PUT_DATA_INT_ST_V  0x1
-#define I2S_TX_PUT_DATA_INT_ST_S  1
-/* I2S_RX_TAKE_DATA_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_TAKE_DATA_INT_ST  (BIT(0))
-#define I2S_RX_TAKE_DATA_INT_ST_M  (BIT(0))
-#define I2S_RX_TAKE_DATA_INT_ST_V  0x1
-#define I2S_RX_TAKE_DATA_INT_ST_S  0
-
-#define I2S_INT_ENA_REG(i)          (REG_I2S_BASE(i) + 0x0014)
-/* I2S_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_TOTAL_EOF_INT_ENA  (BIT(16))
-#define I2S_OUT_TOTAL_EOF_INT_ENA_M  (BIT(16))
-#define I2S_OUT_TOTAL_EOF_INT_ENA_V  0x1
-#define I2S_OUT_TOTAL_EOF_INT_ENA_S  16
-/* I2S_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DSCR_EMPTY_INT_ENA  (BIT(15))
-#define I2S_IN_DSCR_EMPTY_INT_ENA_M  (BIT(15))
-#define I2S_IN_DSCR_EMPTY_INT_ENA_V  0x1
-#define I2S_IN_DSCR_EMPTY_INT_ENA_S  15
-/* I2S_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_DSCR_ERR_INT_ENA  (BIT(14))
-#define I2S_OUT_DSCR_ERR_INT_ENA_M  (BIT(14))
-#define I2S_OUT_DSCR_ERR_INT_ENA_V  0x1
-#define I2S_OUT_DSCR_ERR_INT_ENA_S  14
-/* I2S_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DSCR_ERR_INT_ENA  (BIT(13))
-#define I2S_IN_DSCR_ERR_INT_ENA_M  (BIT(13))
-#define I2S_IN_DSCR_ERR_INT_ENA_V  0x1
-#define I2S_IN_DSCR_ERR_INT_ENA_S  13
-/* I2S_OUT_EOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_EOF_INT_ENA  (BIT(12))
-#define I2S_OUT_EOF_INT_ENA_M  (BIT(12))
-#define I2S_OUT_EOF_INT_ENA_V  0x1
-#define I2S_OUT_EOF_INT_ENA_S  12
-/* I2S_OUT_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_DONE_INT_ENA  (BIT(11))
-#define I2S_OUT_DONE_INT_ENA_M  (BIT(11))
-#define I2S_OUT_DONE_INT_ENA_V  0x1
-#define I2S_OUT_DONE_INT_ENA_S  11
-/* I2S_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_ERR_EOF_INT_ENA  (BIT(10))
-#define I2S_IN_ERR_EOF_INT_ENA_M  (BIT(10))
-#define I2S_IN_ERR_EOF_INT_ENA_V  0x1
-#define I2S_IN_ERR_EOF_INT_ENA_S  10
-/* I2S_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_SUC_EOF_INT_ENA  (BIT(9))
-#define I2S_IN_SUC_EOF_INT_ENA_M  (BIT(9))
-#define I2S_IN_SUC_EOF_INT_ENA_V  0x1
-#define I2S_IN_SUC_EOF_INT_ENA_S  9
-/* I2S_IN_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DONE_INT_ENA  (BIT(8))
-#define I2S_IN_DONE_INT_ENA_M  (BIT(8))
-#define I2S_IN_DONE_INT_ENA_V  0x1
-#define I2S_IN_DONE_INT_ENA_S  8
-/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_HUNG_INT_ENA  (BIT(7))
-#define I2S_TX_HUNG_INT_ENA_M  (BIT(7))
-#define I2S_TX_HUNG_INT_ENA_V  0x1
-#define I2S_TX_HUNG_INT_ENA_S  7
-/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_HUNG_INT_ENA  (BIT(6))
-#define I2S_RX_HUNG_INT_ENA_M  (BIT(6))
-#define I2S_RX_HUNG_INT_ENA_V  0x1
-#define I2S_RX_HUNG_INT_ENA_S  6
-/* I2S_TX_REMPTY_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_REMPTY_INT_ENA  (BIT(5))
-#define I2S_TX_REMPTY_INT_ENA_M  (BIT(5))
-#define I2S_TX_REMPTY_INT_ENA_V  0x1
-#define I2S_TX_REMPTY_INT_ENA_S  5
-/* I2S_TX_WFULL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_WFULL_INT_ENA  (BIT(4))
-#define I2S_TX_WFULL_INT_ENA_M  (BIT(4))
-#define I2S_TX_WFULL_INT_ENA_V  0x1
-#define I2S_TX_WFULL_INT_ENA_S  4
-/* I2S_RX_REMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_REMPTY_INT_ENA  (BIT(3))
-#define I2S_RX_REMPTY_INT_ENA_M  (BIT(3))
-#define I2S_RX_REMPTY_INT_ENA_V  0x1
-#define I2S_RX_REMPTY_INT_ENA_S  3
-/* I2S_RX_WFULL_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_WFULL_INT_ENA  (BIT(2))
-#define I2S_RX_WFULL_INT_ENA_M  (BIT(2))
-#define I2S_RX_WFULL_INT_ENA_V  0x1
-#define I2S_RX_WFULL_INT_ENA_S  2
-/* I2S_TX_PUT_DATA_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_PUT_DATA_INT_ENA  (BIT(1))
-#define I2S_TX_PUT_DATA_INT_ENA_M  (BIT(1))
-#define I2S_TX_PUT_DATA_INT_ENA_V  0x1
-#define I2S_TX_PUT_DATA_INT_ENA_S  1
-/* I2S_RX_TAKE_DATA_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_TAKE_DATA_INT_ENA  (BIT(0))
-#define I2S_RX_TAKE_DATA_INT_ENA_M  (BIT(0))
-#define I2S_RX_TAKE_DATA_INT_ENA_V  0x1
-#define I2S_RX_TAKE_DATA_INT_ENA_S  0
-
-#define I2S_INT_CLR_REG(i)          (REG_I2S_BASE(i) + 0x0018)
-/* I2S_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_TOTAL_EOF_INT_CLR  (BIT(16))
-#define I2S_OUT_TOTAL_EOF_INT_CLR_M  (BIT(16))
-#define I2S_OUT_TOTAL_EOF_INT_CLR_V  0x1
-#define I2S_OUT_TOTAL_EOF_INT_CLR_S  16
-/* I2S_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DSCR_EMPTY_INT_CLR  (BIT(15))
-#define I2S_IN_DSCR_EMPTY_INT_CLR_M  (BIT(15))
-#define I2S_IN_DSCR_EMPTY_INT_CLR_V  0x1
-#define I2S_IN_DSCR_EMPTY_INT_CLR_S  15
-/* I2S_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_DSCR_ERR_INT_CLR  (BIT(14))
-#define I2S_OUT_DSCR_ERR_INT_CLR_M  (BIT(14))
-#define I2S_OUT_DSCR_ERR_INT_CLR_V  0x1
-#define I2S_OUT_DSCR_ERR_INT_CLR_S  14
-/* I2S_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DSCR_ERR_INT_CLR  (BIT(13))
-#define I2S_IN_DSCR_ERR_INT_CLR_M  (BIT(13))
-#define I2S_IN_DSCR_ERR_INT_CLR_V  0x1
-#define I2S_IN_DSCR_ERR_INT_CLR_S  13
-/* I2S_OUT_EOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_EOF_INT_CLR  (BIT(12))
-#define I2S_OUT_EOF_INT_CLR_M  (BIT(12))
-#define I2S_OUT_EOF_INT_CLR_V  0x1
-#define I2S_OUT_EOF_INT_CLR_S  12
-/* I2S_OUT_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_DONE_INT_CLR  (BIT(11))
-#define I2S_OUT_DONE_INT_CLR_M  (BIT(11))
-#define I2S_OUT_DONE_INT_CLR_V  0x1
-#define I2S_OUT_DONE_INT_CLR_S  11
-/* I2S_IN_ERR_EOF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_ERR_EOF_INT_CLR  (BIT(10))
-#define I2S_IN_ERR_EOF_INT_CLR_M  (BIT(10))
-#define I2S_IN_ERR_EOF_INT_CLR_V  0x1
-#define I2S_IN_ERR_EOF_INT_CLR_S  10
-/* I2S_IN_SUC_EOF_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_SUC_EOF_INT_CLR  (BIT(9))
-#define I2S_IN_SUC_EOF_INT_CLR_M  (BIT(9))
-#define I2S_IN_SUC_EOF_INT_CLR_V  0x1
-#define I2S_IN_SUC_EOF_INT_CLR_S  9
-/* I2S_IN_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_DONE_INT_CLR  (BIT(8))
-#define I2S_IN_DONE_INT_CLR_M  (BIT(8))
-#define I2S_IN_DONE_INT_CLR_V  0x1
-#define I2S_IN_DONE_INT_CLR_S  8
-/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_HUNG_INT_CLR  (BIT(7))
-#define I2S_TX_HUNG_INT_CLR_M  (BIT(7))
-#define I2S_TX_HUNG_INT_CLR_V  0x1
-#define I2S_TX_HUNG_INT_CLR_S  7
-/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_HUNG_INT_CLR  (BIT(6))
-#define I2S_RX_HUNG_INT_CLR_M  (BIT(6))
-#define I2S_RX_HUNG_INT_CLR_V  0x1
-#define I2S_RX_HUNG_INT_CLR_S  6
-/* I2S_TX_REMPTY_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_REMPTY_INT_CLR  (BIT(5))
-#define I2S_TX_REMPTY_INT_CLR_M  (BIT(5))
-#define I2S_TX_REMPTY_INT_CLR_V  0x1
-#define I2S_TX_REMPTY_INT_CLR_S  5
-/* I2S_TX_WFULL_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_WFULL_INT_CLR  (BIT(4))
-#define I2S_TX_WFULL_INT_CLR_M  (BIT(4))
-#define I2S_TX_WFULL_INT_CLR_V  0x1
-#define I2S_TX_WFULL_INT_CLR_S  4
-/* I2S_RX_REMPTY_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_REMPTY_INT_CLR  (BIT(3))
-#define I2S_RX_REMPTY_INT_CLR_M  (BIT(3))
-#define I2S_RX_REMPTY_INT_CLR_V  0x1
-#define I2S_RX_REMPTY_INT_CLR_S  3
-/* I2S_RX_WFULL_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_WFULL_INT_CLR  (BIT(2))
-#define I2S_RX_WFULL_INT_CLR_M  (BIT(2))
-#define I2S_RX_WFULL_INT_CLR_V  0x1
-#define I2S_RX_WFULL_INT_CLR_S  2
-/* I2S_PUT_DATA_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2S_PUT_DATA_INT_CLR  (BIT(1))
-#define I2S_PUT_DATA_INT_CLR_M  (BIT(1))
-#define I2S_PUT_DATA_INT_CLR_V  0x1
-#define I2S_PUT_DATA_INT_CLR_S  1
-/* I2S_TAKE_DATA_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TAKE_DATA_INT_CLR  (BIT(0))
-#define I2S_TAKE_DATA_INT_CLR_M  (BIT(0))
-#define I2S_TAKE_DATA_INT_CLR_V  0x1
-#define I2S_TAKE_DATA_INT_CLR_S  0
-
-#define I2S_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x001c)
-/* I2S_TX_BCK_IN_INV : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_BCK_IN_INV  (BIT(24))
-#define I2S_TX_BCK_IN_INV_M  (BIT(24))
-#define I2S_TX_BCK_IN_INV_V  0x1
-#define I2S_TX_BCK_IN_INV_S  24
-/* I2S_DATA_ENABLE_DELAY : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
-/*description: */
-#define I2S_DATA_ENABLE_DELAY  0x00000003
-#define I2S_DATA_ENABLE_DELAY_M  ((I2S_DATA_ENABLE_DELAY_V)<<(I2S_DATA_ENABLE_DELAY_S))
-#define I2S_DATA_ENABLE_DELAY_V  0x3
-#define I2S_DATA_ENABLE_DELAY_S  22
-/* I2S_RX_DSYNC_SW : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_DSYNC_SW  (BIT(21))
-#define I2S_RX_DSYNC_SW_M  (BIT(21))
-#define I2S_RX_DSYNC_SW_V  0x1
-#define I2S_RX_DSYNC_SW_S  21
-/* I2S_TX_DSYNC_SW : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_DSYNC_SW  (BIT(20))
-#define I2S_TX_DSYNC_SW_M  (BIT(20))
-#define I2S_TX_DSYNC_SW_V  0x1
-#define I2S_TX_DSYNC_SW_S  20
-/* I2S_RX_BCK_OUT_DELAY : R/W ;bitpos:[19:18] ;default: 2'b0 ; */
-/*description: */
-#define I2S_RX_BCK_OUT_DELAY  0x00000003
-#define I2S_RX_BCK_OUT_DELAY_M  ((I2S_RX_BCK_OUT_DELAY_V)<<(I2S_RX_BCK_OUT_DELAY_S))
-#define I2S_RX_BCK_OUT_DELAY_V  0x3
-#define I2S_RX_BCK_OUT_DELAY_S  18
-/* I2S_RX_WS_OUT_DELAY : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
-/*description: */
-#define I2S_RX_WS_OUT_DELAY  0x00000003
-#define I2S_RX_WS_OUT_DELAY_M  ((I2S_RX_WS_OUT_DELAY_V)<<(I2S_RX_WS_OUT_DELAY_S))
-#define I2S_RX_WS_OUT_DELAY_V  0x3
-#define I2S_RX_WS_OUT_DELAY_S  16
-/* I2S_TX_SD_OUT_DELAY : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
-/*description: */
-#define I2S_TX_SD_OUT_DELAY  0x00000003
-#define I2S_TX_SD_OUT_DELAY_M  ((I2S_TX_SD_OUT_DELAY_V)<<(I2S_TX_SD_OUT_DELAY_S))
-#define I2S_TX_SD_OUT_DELAY_V  0x3
-#define I2S_TX_SD_OUT_DELAY_S  14
-/* I2S_TX_WS_OUT_DELAY : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: */
-#define I2S_TX_WS_OUT_DELAY  0x00000003
-#define I2S_TX_WS_OUT_DELAY_M  ((I2S_TX_WS_OUT_DELAY_V)<<(I2S_TX_WS_OUT_DELAY_S))
-#define I2S_TX_WS_OUT_DELAY_V  0x3
-#define I2S_TX_WS_OUT_DELAY_S  12
-/* I2S_TX_BCK_OUT_DELAY : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: */
-#define I2S_TX_BCK_OUT_DELAY  0x00000003
-#define I2S_TX_BCK_OUT_DELAY_M  ((I2S_TX_BCK_OUT_DELAY_V)<<(I2S_TX_BCK_OUT_DELAY_S))
-#define I2S_TX_BCK_OUT_DELAY_V  0x3
-#define I2S_TX_BCK_OUT_DELAY_S  10
-/* I2S_RX_SD_IN_DELAY : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: */
-#define I2S_RX_SD_IN_DELAY  0x00000003
-#define I2S_RX_SD_IN_DELAY_M  ((I2S_RX_SD_IN_DELAY_V)<<(I2S_RX_SD_IN_DELAY_S))
-#define I2S_RX_SD_IN_DELAY_V  0x3
-#define I2S_RX_SD_IN_DELAY_S  8
-/* I2S_RX_WS_IN_DELAY : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: */
-#define I2S_RX_WS_IN_DELAY  0x00000003
-#define I2S_RX_WS_IN_DELAY_M  ((I2S_RX_WS_IN_DELAY_V)<<(I2S_RX_WS_IN_DELAY_S))
-#define I2S_RX_WS_IN_DELAY_V  0x3
-#define I2S_RX_WS_IN_DELAY_S  6
-/* I2S_RX_BCK_IN_DELAY : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define I2S_RX_BCK_IN_DELAY  0x00000003
-#define I2S_RX_BCK_IN_DELAY_M  ((I2S_RX_BCK_IN_DELAY_V)<<(I2S_RX_BCK_IN_DELAY_S))
-#define I2S_RX_BCK_IN_DELAY_V  0x3
-#define I2S_RX_BCK_IN_DELAY_S  4
-/* I2S_TX_WS_IN_DELAY : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: */
-#define I2S_TX_WS_IN_DELAY  0x00000003
-#define I2S_TX_WS_IN_DELAY_M  ((I2S_TX_WS_IN_DELAY_V)<<(I2S_TX_WS_IN_DELAY_S))
-#define I2S_TX_WS_IN_DELAY_V  0x3
-#define I2S_TX_WS_IN_DELAY_S  2
-/* I2S_TX_BCK_IN_DELAY : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define I2S_TX_BCK_IN_DELAY  0x00000003
-#define I2S_TX_BCK_IN_DELAY_M  ((I2S_TX_BCK_IN_DELAY_V)<<(I2S_TX_BCK_IN_DELAY_S))
-#define I2S_TX_BCK_IN_DELAY_V  0x3
-#define I2S_TX_BCK_IN_DELAY_S  0
-
-#define I2S_FIFO_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0020)
-/* I2S_RX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define I2S_RX_FIFO_MOD_FORCE_EN  (BIT(20))
-#define I2S_RX_FIFO_MOD_FORCE_EN_M  (BIT(20))
-#define I2S_RX_FIFO_MOD_FORCE_EN_V  0x1
-#define I2S_RX_FIFO_MOD_FORCE_EN_S  20
-/* I2S_TX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define I2S_TX_FIFO_MOD_FORCE_EN  (BIT(19))
-#define I2S_TX_FIFO_MOD_FORCE_EN_M  (BIT(19))
-#define I2S_TX_FIFO_MOD_FORCE_EN_V  0x1
-#define I2S_TX_FIFO_MOD_FORCE_EN_S  19
-/* I2S_RX_FIFO_MOD : R/W ;bitpos:[18:16] ;default: 3'b0 ; */
-/*description: */
-#define I2S_RX_FIFO_MOD  0x00000007
-#define I2S_RX_FIFO_MOD_M  ((I2S_RX_FIFO_MOD_V)<<(I2S_RX_FIFO_MOD_S))
-#define I2S_RX_FIFO_MOD_V  0x7
-#define I2S_RX_FIFO_MOD_S  16
-/* I2S_TX_FIFO_MOD : R/W ;bitpos:[15:13] ;default: 3'b0 ; */
-/*description: */
-#define I2S_TX_FIFO_MOD  0x00000007
-#define I2S_TX_FIFO_MOD_M  ((I2S_TX_FIFO_MOD_V)<<(I2S_TX_FIFO_MOD_S))
-#define I2S_TX_FIFO_MOD_V  0x7
-#define I2S_TX_FIFO_MOD_S  13
-/* I2S_DSCR_EN : R/W ;bitpos:[12] ;default: 1'd1 ; */
-/*description: */
-#define I2S_DSCR_EN  (BIT(12))
-#define I2S_DSCR_EN_M  (BIT(12))
-#define I2S_DSCR_EN_V  0x1
-#define I2S_DSCR_EN_S  12
-/* I2S_TX_DATA_NUM : R/W ;bitpos:[11:6] ;default: 6'd32 ; */
-/*description: */
-#define I2S_TX_DATA_NUM  0x0000003F
-#define I2S_TX_DATA_NUM_M  ((I2S_TX_DATA_NUM_V)<<(I2S_TX_DATA_NUM_S))
-#define I2S_TX_DATA_NUM_V  0x3F
-#define I2S_TX_DATA_NUM_S  6
-/* I2S_RX_DATA_NUM : R/W ;bitpos:[5:0] ;default: 6'd32 ; */
-/*description: */
-#define I2S_RX_DATA_NUM  0x0000003F
-#define I2S_RX_DATA_NUM_M  ((I2S_RX_DATA_NUM_V)<<(I2S_RX_DATA_NUM_S))
-#define I2S_RX_DATA_NUM_V  0x3F
-#define I2S_RX_DATA_NUM_S  0
-
-#define I2S_RXEOF_NUM_REG(i)          (REG_I2S_BASE(i) + 0x0024)
-/* I2S_RX_EOF_NUM : R/W ;bitpos:[31:0] ;default: 32'd64 ; */
-/*description: */
-#define I2S_RX_EOF_NUM  0xFFFFFFFF
-#define I2S_RX_EOF_NUM_M  ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
-#define I2S_RX_EOF_NUM_V  0xFFFFFFFF
-#define I2S_RX_EOF_NUM_S  0
-
-#define I2S_CONF_SIGLE_DATA_REG(i)          (REG_I2S_BASE(i) + 0x0028)
-/* I2S_SIGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: */
-#define I2S_SIGLE_DATA  0xFFFFFFFF
-#define I2S_SIGLE_DATA_M  ((I2S_SIGLE_DATA_V)<<(I2S_SIGLE_DATA_S))
-#define I2S_SIGLE_DATA_V  0xFFFFFFFF
-#define I2S_SIGLE_DATA_S  0
-
-#define I2S_CONF_CHAN_REG(i)          (REG_I2S_BASE(i) + 0x002c)
-/* I2S_RX_CHAN_MOD : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: */
-#define I2S_RX_CHAN_MOD  0x00000003
-#define I2S_RX_CHAN_MOD_M  ((I2S_RX_CHAN_MOD_V)<<(I2S_RX_CHAN_MOD_S))
-#define I2S_RX_CHAN_MOD_V  0x3
-#define I2S_RX_CHAN_MOD_S  3
-/* I2S_TX_CHAN_MOD : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define I2S_TX_CHAN_MOD  0x00000007
-#define I2S_TX_CHAN_MOD_M  ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S))
-#define I2S_TX_CHAN_MOD_V  0x7
-#define I2S_TX_CHAN_MOD_S  0
-
-#define I2S_OUT_LINK_REG(i)          (REG_I2S_BASE(i) + 0x0030)
-/* I2S_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define I2S_OUTLINK_PARK  (BIT(31))
-#define I2S_OUTLINK_PARK_M  (BIT(31))
-#define I2S_OUTLINK_PARK_V  0x1
-#define I2S_OUTLINK_PARK_S  31
-/* I2S_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUTLINK_RESTART  (BIT(30))
-#define I2S_OUTLINK_RESTART_M  (BIT(30))
-#define I2S_OUTLINK_RESTART_V  0x1
-#define I2S_OUTLINK_RESTART_S  30
-/* I2S_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUTLINK_START  (BIT(29))
-#define I2S_OUTLINK_START_M  (BIT(29))
-#define I2S_OUTLINK_START_V  0x1
-#define I2S_OUTLINK_START_S  29
-/* I2S_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUTLINK_STOP  (BIT(28))
-#define I2S_OUTLINK_STOP_M  (BIT(28))
-#define I2S_OUTLINK_STOP_V  0x1
-#define I2S_OUTLINK_STOP_S  28
-/* I2S_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define I2S_OUTLINK_ADDR  0x000FFFFF
-#define I2S_OUTLINK_ADDR_M  ((I2S_OUTLINK_ADDR_V)<<(I2S_OUTLINK_ADDR_S))
-#define I2S_OUTLINK_ADDR_V  0xFFFFF
-#define I2S_OUTLINK_ADDR_S  0
-
-#define I2S_IN_LINK_REG(i)          (REG_I2S_BASE(i) + 0x0034)
-/* I2S_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define I2S_INLINK_PARK  (BIT(31))
-#define I2S_INLINK_PARK_M  (BIT(31))
-#define I2S_INLINK_PARK_V  0x1
-#define I2S_INLINK_PARK_S  31
-/* I2S_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define I2S_INLINK_RESTART  (BIT(30))
-#define I2S_INLINK_RESTART_M  (BIT(30))
-#define I2S_INLINK_RESTART_V  0x1
-#define I2S_INLINK_RESTART_S  30
-/* I2S_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define I2S_INLINK_START  (BIT(29))
-#define I2S_INLINK_START_M  (BIT(29))
-#define I2S_INLINK_START_V  0x1
-#define I2S_INLINK_START_S  29
-/* I2S_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define I2S_INLINK_STOP  (BIT(28))
-#define I2S_INLINK_STOP_M  (BIT(28))
-#define I2S_INLINK_STOP_V  0x1
-#define I2S_INLINK_STOP_S  28
-/* I2S_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define I2S_INLINK_ADDR  0x000FFFFF
-#define I2S_INLINK_ADDR_M  ((I2S_INLINK_ADDR_V)<<(I2S_INLINK_ADDR_S))
-#define I2S_INLINK_ADDR_V  0xFFFFF
-#define I2S_INLINK_ADDR_S  0
-
-#define I2S_OUT_EOF_DES_ADDR_REG(i)          (REG_I2S_BASE(i) + 0x0038)
-/* I2S_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define I2S_OUT_EOF_DES_ADDR  0xFFFFFFFF
-#define I2S_OUT_EOF_DES_ADDR_M  ((I2S_OUT_EOF_DES_ADDR_V)<<(I2S_OUT_EOF_DES_ADDR_S))
-#define I2S_OUT_EOF_DES_ADDR_V  0xFFFFFFFF
-#define I2S_OUT_EOF_DES_ADDR_S  0
-
-#define I2S_IN_EOF_DES_ADDR_REG(i)          (REG_I2S_BASE(i) + 0x003c)
-/* I2S_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define I2S_IN_SUC_EOF_DES_ADDR  0xFFFFFFFF
-#define I2S_IN_SUC_EOF_DES_ADDR_M  ((I2S_IN_SUC_EOF_DES_ADDR_V)<<(I2S_IN_SUC_EOF_DES_ADDR_S))
-#define I2S_IN_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
-#define I2S_IN_SUC_EOF_DES_ADDR_S  0
-
-#define I2S_OUT_EOF_BFR_DES_ADDR_REG(i)          (REG_I2S_BASE(i) + 0x0040)
-/* I2S_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define I2S_OUT_EOF_BFR_DES_ADDR  0xFFFFFFFF
-#define I2S_OUT_EOF_BFR_DES_ADDR_M  ((I2S_OUT_EOF_BFR_DES_ADDR_V)<<(I2S_OUT_EOF_BFR_DES_ADDR_S))
-#define I2S_OUT_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
-#define I2S_OUT_EOF_BFR_DES_ADDR_S  0
-
-#define I2S_AHB_TEST_REG(i)          (REG_I2S_BASE(i) + 0x0044)
-/* I2S_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define I2S_AHB_TESTADDR  0x00000003
-#define I2S_AHB_TESTADDR_M  ((I2S_AHB_TESTADDR_V)<<(I2S_AHB_TESTADDR_S))
-#define I2S_AHB_TESTADDR_V  0x3
-#define I2S_AHB_TESTADDR_S  4
-/* I2S_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define I2S_AHB_TESTMODE  0x00000007
-#define I2S_AHB_TESTMODE_M  ((I2S_AHB_TESTMODE_V)<<(I2S_AHB_TESTMODE_S))
-#define I2S_AHB_TESTMODE_V  0x7
-#define I2S_AHB_TESTMODE_S  0
-
-#define I2S_INLINK_DSCR_REG(i)          (REG_I2S_BASE(i) + 0x0048)
-/* I2S_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define I2S_INLINK_DSCR  0xFFFFFFFF
-#define I2S_INLINK_DSCR_M  ((I2S_INLINK_DSCR_V)<<(I2S_INLINK_DSCR_S))
-#define I2S_INLINK_DSCR_V  0xFFFFFFFF
-#define I2S_INLINK_DSCR_S  0
-
-#define I2S_INLINK_DSCR_BF0_REG(i)          (REG_I2S_BASE(i) + 0x004C)
-/* I2S_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define I2S_INLINK_DSCR_BF0  0xFFFFFFFF
-#define I2S_INLINK_DSCR_BF0_M  ((I2S_INLINK_DSCR_BF0_V)<<(I2S_INLINK_DSCR_BF0_S))
-#define I2S_INLINK_DSCR_BF0_V  0xFFFFFFFF
-#define I2S_INLINK_DSCR_BF0_S  0
-
-#define I2S_INLINK_DSCR_BF1_REG(i)          (REG_I2S_BASE(i) + 0x0050)
-/* I2S_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define I2S_INLINK_DSCR_BF1  0xFFFFFFFF
-#define I2S_INLINK_DSCR_BF1_M  ((I2S_INLINK_DSCR_BF1_V)<<(I2S_INLINK_DSCR_BF1_S))
-#define I2S_INLINK_DSCR_BF1_V  0xFFFFFFFF
-#define I2S_INLINK_DSCR_BF1_S  0
-
-#define I2S_OUTLINK_DSCR_REG(i)          (REG_I2S_BASE(i) + 0x0054)
-/* I2S_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define I2S_OUTLINK_DSCR  0xFFFFFFFF
-#define I2S_OUTLINK_DSCR_M  ((I2S_OUTLINK_DSCR_V)<<(I2S_OUTLINK_DSCR_S))
-#define I2S_OUTLINK_DSCR_V  0xFFFFFFFF
-#define I2S_OUTLINK_DSCR_S  0
-
-#define I2S_OUTLINK_DSCR_BF0_REG(i)          (REG_I2S_BASE(i) + 0x0058)
-/* I2S_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define I2S_OUTLINK_DSCR_BF0  0xFFFFFFFF
-#define I2S_OUTLINK_DSCR_BF0_M  ((I2S_OUTLINK_DSCR_BF0_V)<<(I2S_OUTLINK_DSCR_BF0_S))
-#define I2S_OUTLINK_DSCR_BF0_V  0xFFFFFFFF
-#define I2S_OUTLINK_DSCR_BF0_S  0
-
-#define I2S_OUTLINK_DSCR_BF1_REG(i)          (REG_I2S_BASE(i) + 0x005C)
-/* I2S_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define I2S_OUTLINK_DSCR_BF1  0xFFFFFFFF
-#define I2S_OUTLINK_DSCR_BF1_M  ((I2S_OUTLINK_DSCR_BF1_V)<<(I2S_OUTLINK_DSCR_BF1_S))
-#define I2S_OUTLINK_DSCR_BF1_V  0xFFFFFFFF
-#define I2S_OUTLINK_DSCR_BF1_S  0
-
-#define I2S_LC_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0060)
-/* I2S_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2S_MEM_TRANS_EN  (BIT(13))
-#define I2S_MEM_TRANS_EN_M  (BIT(13))
-#define I2S_MEM_TRANS_EN_V  0x1
-#define I2S_MEM_TRANS_EN_S  13
-/* I2S_CHECK_OWNER : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2S_CHECK_OWNER  (BIT(12))
-#define I2S_CHECK_OWNER_M  (BIT(12))
-#define I2S_CHECK_OWNER_V  0x1
-#define I2S_CHECK_OWNER_S  12
-/* I2S_OUT_DATA_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_DATA_BURST_EN  (BIT(11))
-#define I2S_OUT_DATA_BURST_EN_M  (BIT(11))
-#define I2S_OUT_DATA_BURST_EN_V  0x1
-#define I2S_OUT_DATA_BURST_EN_S  11
-/* I2S_INDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2S_INDSCR_BURST_EN  (BIT(10))
-#define I2S_INDSCR_BURST_EN_M  (BIT(10))
-#define I2S_INDSCR_BURST_EN_V  0x1
-#define I2S_INDSCR_BURST_EN_S  10
-/* I2S_OUTDSCR_BURST_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUTDSCR_BURST_EN  (BIT(9))
-#define I2S_OUTDSCR_BURST_EN_M  (BIT(9))
-#define I2S_OUTDSCR_BURST_EN_V  0x1
-#define I2S_OUTDSCR_BURST_EN_S  9
-/* I2S_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define I2S_OUT_EOF_MODE  (BIT(8))
-#define I2S_OUT_EOF_MODE_M  (BIT(8))
-#define I2S_OUT_EOF_MODE_V  0x1
-#define I2S_OUT_EOF_MODE_S  8
-/* I2S_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_NO_RESTART_CLR  (BIT(7))
-#define I2S_OUT_NO_RESTART_CLR_M  (BIT(7))
-#define I2S_OUT_NO_RESTART_CLR_V  0x1
-#define I2S_OUT_NO_RESTART_CLR_S  7
-/* I2S_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_AUTO_WRBACK  (BIT(6))
-#define I2S_OUT_AUTO_WRBACK_M  (BIT(6))
-#define I2S_OUT_AUTO_WRBACK_V  0x1
-#define I2S_OUT_AUTO_WRBACK_S  6
-/* I2S_IN_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2S_IN_LOOP_TEST  (BIT(5))
-#define I2S_IN_LOOP_TEST_M  (BIT(5))
-#define I2S_IN_LOOP_TEST_V  0x1
-#define I2S_IN_LOOP_TEST_S  5
-/* I2S_OUT_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_LOOP_TEST  (BIT(4))
-#define I2S_OUT_LOOP_TEST_M  (BIT(4))
-#define I2S_OUT_LOOP_TEST_V  0x1
-#define I2S_OUT_LOOP_TEST_S  4
-/* I2S_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2S_AHBM_RST  (BIT(3))
-#define I2S_AHBM_RST_M  (BIT(3))
-#define I2S_AHBM_RST_V  0x1
-#define I2S_AHBM_RST_S  3
-/* I2S_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2S_AHBM_FIFO_RST  (BIT(2))
-#define I2S_AHBM_FIFO_RST_M  (BIT(2))
-#define I2S_AHBM_FIFO_RST_V  0x1
-#define I2S_AHBM_FIFO_RST_S  2
-/* I2S_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2S_OUT_RST  (BIT(1))
-#define I2S_OUT_RST_M  (BIT(1))
-#define I2S_OUT_RST_V  0x1
-#define I2S_OUT_RST_S  1
-/* I2S_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define I2S_IN_RST  (BIT(0))
-#define I2S_IN_RST_M  (BIT(0))
-#define I2S_IN_RST_V  0x1
-#define I2S_IN_RST_S  0
-
-#define I2S_OUTFIFO_PUSH_REG(i)          (REG_I2S_BASE(i) + 0x0064)
-/* I2S_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: */
-#define I2S_OUTFIFO_PUSH  (BIT(16))
-#define I2S_OUTFIFO_PUSH_M  (BIT(16))
-#define I2S_OUTFIFO_PUSH_V  0x1
-#define I2S_OUTFIFO_PUSH_S  16
-/* I2S_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: */
-#define I2S_OUTFIFO_WDATA  0x000001FF
-#define I2S_OUTFIFO_WDATA_M  ((I2S_OUTFIFO_WDATA_V)<<(I2S_OUTFIFO_WDATA_S))
-#define I2S_OUTFIFO_WDATA_V  0x1FF
-#define I2S_OUTFIFO_WDATA_S  0
-
-#define I2S_INFIFO_POP_REG(i)          (REG_I2S_BASE(i) + 0x0068)
-/* I2S_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: */
-#define I2S_INFIFO_POP  (BIT(16))
-#define I2S_INFIFO_POP_M  (BIT(16))
-#define I2S_INFIFO_POP_V  0x1
-#define I2S_INFIFO_POP_S  16
-/* I2S_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define I2S_INFIFO_RDATA  0x00000FFF
-#define I2S_INFIFO_RDATA_M  ((I2S_INFIFO_RDATA_V)<<(I2S_INFIFO_RDATA_S))
-#define I2S_INFIFO_RDATA_V  0xFFF
-#define I2S_INFIFO_RDATA_S  0
-
-#define I2S_LC_STATE0_REG(i)          (REG_I2S_BASE(i) + 0x006C)
-/* I2S_LC_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define I2S_LC_STATE0  0xFFFFFFFF
-#define I2S_LC_STATE0_M  ((I2S_LC_STATE0_V)<<(I2S_LC_STATE0_S))
-#define I2S_LC_STATE0_V  0xFFFFFFFF
-#define I2S_LC_STATE0_S  0
-
-#define I2S_LC_STATE1_REG(i)          (REG_I2S_BASE(i) + 0x0070)
-/* I2S_LC_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define I2S_LC_STATE1  0xFFFFFFFF
-#define I2S_LC_STATE1_M  ((I2S_LC_STATE1_V)<<(I2S_LC_STATE1_S))
-#define I2S_LC_STATE1_V  0xFFFFFFFF
-#define I2S_LC_STATE1_S  0
-
-#define I2S_LC_HUNG_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0074)
-/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: */
-#define I2S_LC_FIFO_TIMEOUT_ENA  (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_M  (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x1
-#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
-/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
-/*description: */
-#define I2S_LC_FIFO_TIMEOUT_SHIFT  0x00000007
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x7
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
-/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
-/*description: */
-#define I2S_LC_FIFO_TIMEOUT  0x000000FF
-#define I2S_LC_FIFO_TIMEOUT_M  ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S))
-#define I2S_LC_FIFO_TIMEOUT_V  0xFF
-#define I2S_LC_FIFO_TIMEOUT_S  0
-
-#define I2S_CVSD_CONF0_REG(i)          (REG_I2S_BASE(i) + 0x0080)
-/* I2S_CVSD_Y_MIN : R/W ;bitpos:[31:16] ;default: 16'h8000 ; */
-/*description: */
-#define I2S_CVSD_Y_MIN  0x0000FFFF
-#define I2S_CVSD_Y_MIN_M  ((I2S_CVSD_Y_MIN_V)<<(I2S_CVSD_Y_MIN_S))
-#define I2S_CVSD_Y_MIN_V  0xFFFF
-#define I2S_CVSD_Y_MIN_S  16
-/* I2S_CVSD_Y_MAX : R/W ;bitpos:[15:0] ;default: 16'h7fff ; */
-/*description: */
-#define I2S_CVSD_Y_MAX  0x0000FFFF
-#define I2S_CVSD_Y_MAX_M  ((I2S_CVSD_Y_MAX_V)<<(I2S_CVSD_Y_MAX_S))
-#define I2S_CVSD_Y_MAX_V  0xFFFF
-#define I2S_CVSD_Y_MAX_S  0
-
-#define I2S_CVSD_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x0084)
-/* I2S_CVSD_SIGMA_MIN : R/W ;bitpos:[31:16] ;default: 16'd10 ; */
-/*description: */
-#define I2S_CVSD_SIGMA_MIN  0x0000FFFF
-#define I2S_CVSD_SIGMA_MIN_M  ((I2S_CVSD_SIGMA_MIN_V)<<(I2S_CVSD_SIGMA_MIN_S))
-#define I2S_CVSD_SIGMA_MIN_V  0xFFFF
-#define I2S_CVSD_SIGMA_MIN_S  16
-/* I2S_CVSD_SIGMA_MAX : R/W ;bitpos:[15:0] ;default: 16'd1280 ; */
-/*description: */
-#define I2S_CVSD_SIGMA_MAX  0x0000FFFF
-#define I2S_CVSD_SIGMA_MAX_M  ((I2S_CVSD_SIGMA_MAX_V)<<(I2S_CVSD_SIGMA_MAX_S))
-#define I2S_CVSD_SIGMA_MAX_V  0xFFFF
-#define I2S_CVSD_SIGMA_MAX_S  0
-
-#define I2S_CVSD_CONF2_REG(i)          (REG_I2S_BASE(i) + 0x0088)
-/* I2S_CVSD_H : R/W ;bitpos:[18:16] ;default: 3'd5 ; */
-/*description: */
-#define I2S_CVSD_H  0x00000007
-#define I2S_CVSD_H_M  ((I2S_CVSD_H_V)<<(I2S_CVSD_H_S))
-#define I2S_CVSD_H_V  0x7
-#define I2S_CVSD_H_S  16
-/* I2S_CVSD_BETA : R/W ;bitpos:[15:6] ;default: 10'd10 ; */
-/*description: */
-#define I2S_CVSD_BETA  0x000003FF
-#define I2S_CVSD_BETA_M  ((I2S_CVSD_BETA_V)<<(I2S_CVSD_BETA_S))
-#define I2S_CVSD_BETA_V  0x3FF
-#define I2S_CVSD_BETA_S  6
-/* I2S_CVSD_J : R/W ;bitpos:[5:3] ;default: 3'h4 ; */
-/*description: */
-#define I2S_CVSD_J  0x00000007
-#define I2S_CVSD_J_M  ((I2S_CVSD_J_V)<<(I2S_CVSD_J_S))
-#define I2S_CVSD_J_V  0x7
-#define I2S_CVSD_J_S  3
-/* I2S_CVSD_K : R/W ;bitpos:[2:0] ;default: 3'h4 ; */
-/*description: */
-#define I2S_CVSD_K  0x00000007
-#define I2S_CVSD_K_M  ((I2S_CVSD_K_V)<<(I2S_CVSD_K_S))
-#define I2S_CVSD_K_V  0x7
-#define I2S_CVSD_K_S  0
-
-#define I2S_PLC_CONF0_REG(i)          (REG_I2S_BASE(i) + 0x008C)
-/* I2S_N_MIN_ERR : R/W ;bitpos:[27:25] ;default: 3'd4 ; */
-/*description: */
-#define I2S_N_MIN_ERR  0x00000007
-#define I2S_N_MIN_ERR_M  ((I2S_N_MIN_ERR_V)<<(I2S_N_MIN_ERR_S))
-#define I2S_N_MIN_ERR_V  0x7
-#define I2S_N_MIN_ERR_S  25
-/* I2S_PACK_LEN_8K : R/W ;bitpos:[24:20] ;default: 5'd10 ; */
-/*description: */
-#define I2S_PACK_LEN_8K  0x0000001F
-#define I2S_PACK_LEN_8K_M  ((I2S_PACK_LEN_8K_V)<<(I2S_PACK_LEN_8K_S))
-#define I2S_PACK_LEN_8K_V  0x1F
-#define I2S_PACK_LEN_8K_S  20
-/* I2S_MAX_SLIDE_SAMPLE : R/W ;bitpos:[19:12] ;default: 8'd128 ; */
-/*description: */
-#define I2S_MAX_SLIDE_SAMPLE  0x000000FF
-#define I2S_MAX_SLIDE_SAMPLE_M  ((I2S_MAX_SLIDE_SAMPLE_V)<<(I2S_MAX_SLIDE_SAMPLE_S))
-#define I2S_MAX_SLIDE_SAMPLE_V  0xFF
-#define I2S_MAX_SLIDE_SAMPLE_S  12
-/* I2S_SHIFT_RATE : R/W ;bitpos:[11:9] ;default: 3'h1 ; */
-/*description: */
-#define I2S_SHIFT_RATE  0x00000007
-#define I2S_SHIFT_RATE_M  ((I2S_SHIFT_RATE_V)<<(I2S_SHIFT_RATE_S))
-#define I2S_SHIFT_RATE_V  0x7
-#define I2S_SHIFT_RATE_S  9
-/* I2S_N_ERR_SEG : R/W ;bitpos:[8:6] ;default: 3'h4 ; */
-/*description: */
-#define I2S_N_ERR_SEG  0x00000007
-#define I2S_N_ERR_SEG_M  ((I2S_N_ERR_SEG_V)<<(I2S_N_ERR_SEG_S))
-#define I2S_N_ERR_SEG_V  0x7
-#define I2S_N_ERR_SEG_S  6
-/* I2S_GOOD_PACK_MAX : R/W ;bitpos:[5:0] ;default: 6'h39 ; */
-/*description: */
-#define I2S_GOOD_PACK_MAX  0x0000003F
-#define I2S_GOOD_PACK_MAX_M  ((I2S_GOOD_PACK_MAX_V)<<(I2S_GOOD_PACK_MAX_S))
-#define I2S_GOOD_PACK_MAX_V  0x3F
-#define I2S_GOOD_PACK_MAX_S  0
-
-#define I2S_PLC_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x0090)
-/* I2S_SLIDE_WIN_LEN : R/W ;bitpos:[31:24] ;default: 8'd160 ; */
-/*description: */
-#define I2S_SLIDE_WIN_LEN  0x000000FF
-#define I2S_SLIDE_WIN_LEN_M  ((I2S_SLIDE_WIN_LEN_V)<<(I2S_SLIDE_WIN_LEN_S))
-#define I2S_SLIDE_WIN_LEN_V  0xFF
-#define I2S_SLIDE_WIN_LEN_S  24
-/* I2S_BAD_OLA_WIN2_PARA : R/W ;bitpos:[23:16] ;default: 8'd23 ; */
-/*description: */
-#define I2S_BAD_OLA_WIN2_PARA  0x000000FF
-#define I2S_BAD_OLA_WIN2_PARA_M  ((I2S_BAD_OLA_WIN2_PARA_V)<<(I2S_BAD_OLA_WIN2_PARA_S))
-#define I2S_BAD_OLA_WIN2_PARA_V  0xFF
-#define I2S_BAD_OLA_WIN2_PARA_S  16
-/* I2S_BAD_OLA_WIN2_PARA_SHIFT : R/W ;bitpos:[15:12] ;default: 4'd8 ; */
-/*description: */
-#define I2S_BAD_OLA_WIN2_PARA_SHIFT  0x0000000F
-#define I2S_BAD_OLA_WIN2_PARA_SHIFT_M  ((I2S_BAD_OLA_WIN2_PARA_SHIFT_V)<<(I2S_BAD_OLA_WIN2_PARA_SHIFT_S))
-#define I2S_BAD_OLA_WIN2_PARA_SHIFT_V  0xF
-#define I2S_BAD_OLA_WIN2_PARA_SHIFT_S  12
-/* I2S_BAD_CEF_ATTEN_PARA_SHIFT : R/W ;bitpos:[11:8] ;default: 4'd10 ; */
-/*description: */
-#define I2S_BAD_CEF_ATTEN_PARA_SHIFT  0x0000000F
-#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_M  ((I2S_BAD_CEF_ATTEN_PARA_SHIFT_V)<<(I2S_BAD_CEF_ATTEN_PARA_SHIFT_S))
-#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_V  0xF
-#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_S  8
-/* I2S_BAD_CEF_ATTEN_PARA : R/W ;bitpos:[7:0] ;default: 8'd5 ; */
-/*description: */
-#define I2S_BAD_CEF_ATTEN_PARA  0x000000FF
-#define I2S_BAD_CEF_ATTEN_PARA_M  ((I2S_BAD_CEF_ATTEN_PARA_V)<<(I2S_BAD_CEF_ATTEN_PARA_S))
-#define I2S_BAD_CEF_ATTEN_PARA_V  0xFF
-#define I2S_BAD_CEF_ATTEN_PARA_S  0
-
-#define I2S_PLC_CONF2_REG(i)          (REG_I2S_BASE(i) + 0x0094)
-/* I2S_MIN_PERIOD : R/W ;bitpos:[6:2] ;default: 5'd10 ; */
-/*description: */
-#define I2S_MIN_PERIOD  0x0000001F
-#define I2S_MIN_PERIOD_M  ((I2S_MIN_PERIOD_V)<<(I2S_MIN_PERIOD_S))
-#define I2S_MIN_PERIOD_V  0x1F
-#define I2S_MIN_PERIOD_S  2
-/* I2S_CVSD_SEG_MOD : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define I2S_CVSD_SEG_MOD  0x00000003
-#define I2S_CVSD_SEG_MOD_M  ((I2S_CVSD_SEG_MOD_V)<<(I2S_CVSD_SEG_MOD_S))
-#define I2S_CVSD_SEG_MOD_V  0x3
-#define I2S_CVSD_SEG_MOD_S  0
-
-#define I2S_ESCO_CONF0_REG(i)          (REG_I2S_BASE(i) + 0x0098)
-/* I2S_PLC2DMA_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2S_PLC2DMA_EN  (BIT(12))
-#define I2S_PLC2DMA_EN_M  (BIT(12))
-#define I2S_PLC2DMA_EN_V  0x1
-#define I2S_PLC2DMA_EN_S  12
-/* I2S_PLC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2S_PLC_EN  (BIT(11))
-#define I2S_PLC_EN_M  (BIT(11))
-#define I2S_PLC_EN_V  0x1
-#define I2S_PLC_EN_S  11
-/* I2S_CVSD_DEC_RESET : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2S_CVSD_DEC_RESET  (BIT(10))
-#define I2S_CVSD_DEC_RESET_M  (BIT(10))
-#define I2S_CVSD_DEC_RESET_V  0x1
-#define I2S_CVSD_DEC_RESET_S  10
-/* I2S_CVSD_DEC_START : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2S_CVSD_DEC_START  (BIT(9))
-#define I2S_CVSD_DEC_START_M  (BIT(9))
-#define I2S_CVSD_DEC_START_V  0x1
-#define I2S_CVSD_DEC_START_S  9
-/* I2S_ESCO_CVSD_INF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2S_ESCO_CVSD_INF_EN  (BIT(8))
-#define I2S_ESCO_CVSD_INF_EN_M  (BIT(8))
-#define I2S_ESCO_CVSD_INF_EN_V  0x1
-#define I2S_ESCO_CVSD_INF_EN_S  8
-/* I2S_ESCO_CVSD_PACK_LEN_8K : R/W ;bitpos:[7:3] ;default: 5'b0 ; */
-/*description: */
-#define I2S_ESCO_CVSD_PACK_LEN_8K  0x0000001F
-#define I2S_ESCO_CVSD_PACK_LEN_8K_M  ((I2S_ESCO_CVSD_PACK_LEN_8K_V)<<(I2S_ESCO_CVSD_PACK_LEN_8K_S))
-#define I2S_ESCO_CVSD_PACK_LEN_8K_V  0x1F
-#define I2S_ESCO_CVSD_PACK_LEN_8K_S  3
-/* I2S_ESCO_CVSD_DEC_PACK_ERR : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2S_ESCO_CVSD_DEC_PACK_ERR  (BIT(2))
-#define I2S_ESCO_CVSD_DEC_PACK_ERR_M  (BIT(2))
-#define I2S_ESCO_CVSD_DEC_PACK_ERR_V  0x1
-#define I2S_ESCO_CVSD_DEC_PACK_ERR_S  2
-/* I2S_ESCO_CHAN_MOD : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define I2S_ESCO_CHAN_MOD  (BIT(1))
-#define I2S_ESCO_CHAN_MOD_M  (BIT(1))
-#define I2S_ESCO_CHAN_MOD_V  0x1
-#define I2S_ESCO_CHAN_MOD_S  1
-/* I2S_ESCO_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define I2S_ESCO_EN  (BIT(0))
-#define I2S_ESCO_EN_M  (BIT(0))
-#define I2S_ESCO_EN_V  0x1
-#define I2S_ESCO_EN_S  0
-
-#define I2S_SCO_CONF0_REG(i)          (REG_I2S_BASE(i) + 0x009c)
-/* I2S_CVSD_ENC_RESET : R/W ;bitpos:[3] ;default: 1'd0 ; */
-/*description: */
-#define I2S_CVSD_ENC_RESET  (BIT(3))
-#define I2S_CVSD_ENC_RESET_M  (BIT(3))
-#define I2S_CVSD_ENC_RESET_V  0x1
-#define I2S_CVSD_ENC_RESET_S  3
-/* I2S_CVSD_ENC_START : R/W ;bitpos:[2] ;default: 1'd0 ; */
-/*description: */
-#define I2S_CVSD_ENC_START  (BIT(2))
-#define I2S_CVSD_ENC_START_M  (BIT(2))
-#define I2S_CVSD_ENC_START_V  0x1
-#define I2S_CVSD_ENC_START_S  2
-/* I2S_SCO_NO_I2S_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define I2S_SCO_NO_I2S_EN  (BIT(1))
-#define I2S_SCO_NO_I2S_EN_M  (BIT(1))
-#define I2S_SCO_NO_I2S_EN_V  0x1
-#define I2S_SCO_NO_I2S_EN_S  1
-/* I2S_SCO_WITH_I2S_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define I2S_SCO_WITH_I2S_EN  (BIT(0))
-#define I2S_SCO_WITH_I2S_EN_M  (BIT(0))
-#define I2S_SCO_WITH_I2S_EN_V  0x1
-#define I2S_SCO_WITH_I2S_EN_S  0
-
-#define I2S_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x00a0)
-/* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: */
-#define I2S_TX_ZEROS_RM_EN  (BIT(9))
-#define I2S_TX_ZEROS_RM_EN_M  (BIT(9))
-#define I2S_TX_ZEROS_RM_EN_V  0x1
-#define I2S_TX_ZEROS_RM_EN_S  9
-/* I2S_TX_STOP_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: */
-#define I2S_TX_STOP_EN  (BIT(8))
-#define I2S_TX_STOP_EN_M  (BIT(8))
-#define I2S_TX_STOP_EN_V  0x1
-#define I2S_TX_STOP_EN_S  8
-/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[7] ;default: 1'h1 ; */
-/*description: */
-#define I2S_RX_PCM_BYPASS  (BIT(7))
-#define I2S_RX_PCM_BYPASS_M  (BIT(7))
-#define I2S_RX_PCM_BYPASS_V  0x1
-#define I2S_RX_PCM_BYPASS_S  7
-/* I2S_RX_PCM_CONF : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
-/*description: */
-#define I2S_RX_PCM_CONF  0x00000007
-#define I2S_RX_PCM_CONF_M  ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S))
-#define I2S_RX_PCM_CONF_V  0x7
-#define I2S_RX_PCM_CONF_S  4
-/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[3] ;default: 1'h1 ; */
-/*description: */
-#define I2S_TX_PCM_BYPASS  (BIT(3))
-#define I2S_TX_PCM_BYPASS_M  (BIT(3))
-#define I2S_TX_PCM_BYPASS_V  0x1
-#define I2S_TX_PCM_BYPASS_S  3
-/* I2S_TX_PCM_CONF : R/W ;bitpos:[2:0] ;default: 3'h1 ; */
-/*description: */
-#define I2S_TX_PCM_CONF  0x00000007
-#define I2S_TX_PCM_CONF_M  ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S))
-#define I2S_TX_PCM_CONF_V  0x7
-#define I2S_TX_PCM_CONF_S  0
-
-#define I2S_PD_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00a4)
-/* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */
-/*description: */
-#define I2S_PLC_MEM_FORCE_PU  (BIT(3))
-#define I2S_PLC_MEM_FORCE_PU_M  (BIT(3))
-#define I2S_PLC_MEM_FORCE_PU_V  0x1
-#define I2S_PLC_MEM_FORCE_PU_S  3
-/* I2S_PLC_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define I2S_PLC_MEM_FORCE_PD  (BIT(2))
-#define I2S_PLC_MEM_FORCE_PD_M  (BIT(2))
-#define I2S_PLC_MEM_FORCE_PD_V  0x1
-#define I2S_PLC_MEM_FORCE_PD_S  2
-/* I2S_FIFO_FORCE_PU : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: */
-#define I2S_FIFO_FORCE_PU  (BIT(1))
-#define I2S_FIFO_FORCE_PU_M  (BIT(1))
-#define I2S_FIFO_FORCE_PU_V  0x1
-#define I2S_FIFO_FORCE_PU_S  1
-/* I2S_FIFO_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define I2S_FIFO_FORCE_PD  (BIT(0))
-#define I2S_FIFO_FORCE_PD_M  (BIT(0))
-#define I2S_FIFO_FORCE_PD_V  0x1
-#define I2S_FIFO_FORCE_PD_S  0
-
-#define I2S_CONF2_REG(i)          (REG_I2S_BASE(i) + 0x00a8)
-/* I2S_INTER_VALID_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2S_INTER_VALID_EN  (BIT(7))
-#define I2S_INTER_VALID_EN_M  (BIT(7))
-#define I2S_INTER_VALID_EN_V  0x1
-#define I2S_INTER_VALID_EN_S  7
-/* I2S_EXT_ADC_START_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2S_EXT_ADC_START_EN  (BIT(6))
-#define I2S_EXT_ADC_START_EN_M  (BIT(6))
-#define I2S_EXT_ADC_START_EN_V  0x1
-#define I2S_EXT_ADC_START_EN_S  6
-/* I2S_LCD_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2S_LCD_EN  (BIT(5))
-#define I2S_LCD_EN_M  (BIT(5))
-#define I2S_LCD_EN_V  0x1
-#define I2S_LCD_EN_S  5
-/* I2S_DATA_ENABLE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: */
-#define I2S_DATA_ENABLE  (BIT(4))
-#define I2S_DATA_ENABLE_M  (BIT(4))
-#define I2S_DATA_ENABLE_V  0x1
-#define I2S_DATA_ENABLE_S  4
-/* I2S_DATA_ENABLE_TEST_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: */
-#define I2S_DATA_ENABLE_TEST_EN  (BIT(3))
-#define I2S_DATA_ENABLE_TEST_EN_M  (BIT(3))
-#define I2S_DATA_ENABLE_TEST_EN_V  0x1
-#define I2S_DATA_ENABLE_TEST_EN_S  3
-/* I2S_LCD_TX_SDX2_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define I2S_LCD_TX_SDX2_EN  (BIT(2))
-#define I2S_LCD_TX_SDX2_EN_M  (BIT(2))
-#define I2S_LCD_TX_SDX2_EN_V  0x1
-#define I2S_LCD_TX_SDX2_EN_S  2
-/* I2S_LCD_TX_WRX2_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: */
-#define I2S_LCD_TX_WRX2_EN  (BIT(1))
-#define I2S_LCD_TX_WRX2_EN_M  (BIT(1))
-#define I2S_LCD_TX_WRX2_EN_V  0x1
-#define I2S_LCD_TX_WRX2_EN_S  1
-/* I2S_CAMERA_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define I2S_CAMERA_EN  (BIT(0))
-#define I2S_CAMERA_EN_M  (BIT(0))
-#define I2S_CAMERA_EN_V  0x1
-#define I2S_CAMERA_EN_S  0
-
-#define I2S_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00ac)
-/* I2S_CLKA_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define I2S_CLKA_ENA  (BIT(21))
-#define I2S_CLKA_ENA_M  (BIT(21))
-#define I2S_CLKA_ENA_V  0x1
-#define I2S_CLKA_ENA_S  21
-/* I2S_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define I2S_CLK_EN  (BIT(20))
-#define I2S_CLK_EN_M  (BIT(20))
-#define I2S_CLK_EN_V  0x1
-#define I2S_CLK_EN_S  20
-/* I2S_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
-/*description: */
-#define I2S_CLKM_DIV_A  0x0000003F
-#define I2S_CLKM_DIV_A_M  ((I2S_CLKM_DIV_A_V)<<(I2S_CLKM_DIV_A_S))
-#define I2S_CLKM_DIV_A_V  0x3F
-#define I2S_CLKM_DIV_A_S  14
-/* I2S_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
-/*description: */
-#define I2S_CLKM_DIV_B  0x0000003F
-#define I2S_CLKM_DIV_B_M  ((I2S_CLKM_DIV_B_V)<<(I2S_CLKM_DIV_B_S))
-#define I2S_CLKM_DIV_B_V  0x3F
-#define I2S_CLKM_DIV_B_S  8
-/* I2S_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
-/*description: */
-#define I2S_CLKM_DIV_NUM  0x000000FF
-#define I2S_CLKM_DIV_NUM_M  ((I2S_CLKM_DIV_NUM_V)<<(I2S_CLKM_DIV_NUM_S))
-#define I2S_CLKM_DIV_NUM_V  0xFF
-#define I2S_CLKM_DIV_NUM_S  0
-
-#define I2S_SAMPLE_RATE_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00b0)
-/* I2S_RX_BITS_MOD : R/W ;bitpos:[23:18] ;default: 6'd16 ; */
-/*description: */
-#define I2S_RX_BITS_MOD  0x0000003F
-#define I2S_RX_BITS_MOD_M  ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S))
-#define I2S_RX_BITS_MOD_V  0x3F
-#define I2S_RX_BITS_MOD_S  18
-/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:12] ;default: 6'd16 ; */
-/*description: */
-#define I2S_TX_BITS_MOD  0x0000003F
-#define I2S_TX_BITS_MOD_M  ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S))
-#define I2S_TX_BITS_MOD_V  0x3F
-#define I2S_TX_BITS_MOD_S  12
-/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[11:6] ;default: 6'd6 ; */
-/*description: */
-#define I2S_RX_BCK_DIV_NUM  0x0000003F
-#define I2S_RX_BCK_DIV_NUM_M  ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S))
-#define I2S_RX_BCK_DIV_NUM_V  0x3F
-#define I2S_RX_BCK_DIV_NUM_S  6
-/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[5:0] ;default: 6'd6 ; */
-/*description: */
-#define I2S_TX_BCK_DIV_NUM  0x0000003F
-#define I2S_TX_BCK_DIV_NUM_M  ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S))
-#define I2S_TX_BCK_DIV_NUM_V  0x3F
-#define I2S_TX_BCK_DIV_NUM_S  0
-
-#define I2S_PDM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00b4)
-/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define I2S_TX_PDM_HP_BYPASS  (BIT(25))
-#define I2S_TX_PDM_HP_BYPASS_M  (BIT(25))
-#define I2S_TX_PDM_HP_BYPASS_V  0x1
-#define I2S_TX_PDM_HP_BYPASS_S  25
-/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[24] ;default: 1'h1 ; */
-/*description: */
-#define I2S_RX_PDM_SINC_DSR_16_EN  (BIT(24))
-#define I2S_RX_PDM_SINC_DSR_16_EN_M  (BIT(24))
-#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x1
-#define I2S_RX_PDM_SINC_DSR_16_EN_S  24
-/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[23:22] ;default: 2'h1 ; */
-/*description: */
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT  0x00000003
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S))
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  22
-/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[21:20] ;default: 2'h1 ; */
-/*description: */
-#define I2S_TX_PDM_SINC_IN_SHIFT  0x00000003
-#define I2S_TX_PDM_SINC_IN_SHIFT_M  ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S))
-#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_SINC_IN_SHIFT_S  20
-/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[19:18] ;default: 2'h1 ; */
-/*description: */
-#define I2S_TX_PDM_LP_IN_SHIFT  0x00000003
-#define I2S_TX_PDM_LP_IN_SHIFT_M  ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S))
-#define I2S_TX_PDM_LP_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_LP_IN_SHIFT_S  18
-/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[17:16] ;default: 2'h1 ; */
-/*description: */
-#define I2S_TX_PDM_HP_IN_SHIFT  0x00000003
-#define I2S_TX_PDM_HP_IN_SHIFT_M  ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S))
-#define I2S_TX_PDM_HP_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_HP_IN_SHIFT_S  16
-/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define I2S_TX_PDM_PRESCALE  0x000000FF
-#define I2S_TX_PDM_PRESCALE_M  ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S))
-#define I2S_TX_PDM_PRESCALE_V  0xFF
-#define I2S_TX_PDM_PRESCALE_S  8
-/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[7:4] ;default: 4'h2 ; */
-/*description: */
-#define I2S_TX_PDM_SINC_OSR2  0x0000000F
-#define I2S_TX_PDM_SINC_OSR2_M  ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S))
-#define I2S_TX_PDM_SINC_OSR2_V  0xF
-#define I2S_TX_PDM_SINC_OSR2_S  4
-/* I2S_PDM2PCM_CONV_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: */
-#define I2S_PDM2PCM_CONV_EN  (BIT(3))
-#define I2S_PDM2PCM_CONV_EN_M  (BIT(3))
-#define I2S_PDM2PCM_CONV_EN_V  0x1
-#define I2S_PDM2PCM_CONV_EN_S  3
-/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define I2S_PCM2PDM_CONV_EN  (BIT(2))
-#define I2S_PCM2PDM_CONV_EN_M  (BIT(2))
-#define I2S_PCM2PDM_CONV_EN_V  0x1
-#define I2S_PCM2PDM_CONV_EN_S  2
-/* I2S_RX_PDM_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: */
-#define I2S_RX_PDM_EN  (BIT(1))
-#define I2S_RX_PDM_EN_M  (BIT(1))
-#define I2S_RX_PDM_EN_V  0x1
-#define I2S_RX_PDM_EN_S  1
-/* I2S_TX_PDM_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define I2S_TX_PDM_EN  (BIT(0))
-#define I2S_TX_PDM_EN_M  (BIT(0))
-#define I2S_TX_PDM_EN_V  0x1
-#define I2S_TX_PDM_EN_S  0
-
-#define I2S_PDM_FREQ_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00b8)
-/* I2S_TX_PDM_FP : R/W ;bitpos:[19:10] ;default: 10'd960 ; */
-/*description: */
-#define I2S_TX_PDM_FP  0x000003FF
-#define I2S_TX_PDM_FP_M  ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S))
-#define I2S_TX_PDM_FP_V  0x3FF
-#define I2S_TX_PDM_FP_S  10
-/* I2S_TX_PDM_FS : R/W ;bitpos:[9:0] ;default: 10'd480 ; */
-/*description: */
-#define I2S_TX_PDM_FS  0x000003FF
-#define I2S_TX_PDM_FS_M  ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S))
-#define I2S_TX_PDM_FS_V  0x3FF
-#define I2S_TX_PDM_FS_S  0
-
-#define I2S_STATE_REG(i)          (REG_I2S_BASE(i) + 0x00bc)
-/* I2S_RX_FIFO_RESET_BACK : RO ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define I2S_RX_FIFO_RESET_BACK  (BIT(2))
-#define I2S_RX_FIFO_RESET_BACK_M  (BIT(2))
-#define I2S_RX_FIFO_RESET_BACK_V  0x1
-#define I2S_RX_FIFO_RESET_BACK_S  2
-/* I2S_TX_FIFO_RESET_BACK : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define I2S_TX_FIFO_RESET_BACK  (BIT(1))
-#define I2S_TX_FIFO_RESET_BACK_M  (BIT(1))
-#define I2S_TX_FIFO_RESET_BACK_V  0x1
-#define I2S_TX_FIFO_RESET_BACK_S  1
-/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define I2S_TX_IDLE  (BIT(0))
-#define I2S_TX_IDLE_M  (BIT(0))
-#define I2S_TX_IDLE_V  0x1
-#define I2S_TX_IDLE_S  0
-
-#define I2S_DATE_REG(i)          (REG_I2S_BASE(i) + 0x00fc)
-/* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h1604201 ; */
-/*description: */
-#define I2S_I2SDATE  0xFFFFFFFF
-#define I2S_I2SDATE_M  ((I2S_I2SDATE_V)<<(I2S_I2SDATE_S))
-#define I2S_I2SDATE_V  0xFFFFFFFF
-#define I2S_I2SDATE_S  0
-
-
-
-
-#endif /*_SOC_I2S_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/i2s_struct.h b/tools/sdk/include/soc/soc/i2s_struct.h
deleted file mode 100644
index aa92bb75fea..00000000000
--- a/tools/sdk/include/soc/soc/i2s_struct.h
+++ /dev/null
@@ -1,472 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_I2S_STRUCT_H_
-#define _SOC_I2S_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    uint32_t reserved_0;
-    uint32_t reserved_4;
-    union {
-        struct {
-            uint32_t tx_reset:       1;
-            uint32_t rx_reset:       1;
-            uint32_t tx_fifo_reset:  1;
-            uint32_t rx_fifo_reset:  1;
-            uint32_t tx_start:       1;
-            uint32_t rx_start:       1;
-            uint32_t tx_slave_mod:   1;
-            uint32_t rx_slave_mod:   1;
-            uint32_t tx_right_first: 1;
-            uint32_t rx_right_first: 1;
-            uint32_t tx_msb_shift:   1;
-            uint32_t rx_msb_shift:   1;
-            uint32_t tx_short_sync:  1;
-            uint32_t rx_short_sync:  1;
-            uint32_t tx_mono:        1;
-            uint32_t rx_mono:        1;
-            uint32_t tx_msb_right:   1;
-            uint32_t rx_msb_right:   1;
-            uint32_t sig_loopback:   1;
-            uint32_t reserved19:    13;
-        };
-        uint32_t val;
-    } conf;
-    union {
-        struct {
-            uint32_t rx_take_data:  1;
-            uint32_t tx_put_data:   1;
-            uint32_t rx_wfull:      1;
-            uint32_t rx_rempty:     1;
-            uint32_t tx_wfull:      1;
-            uint32_t tx_rempty:     1;
-            uint32_t rx_hung:       1;
-            uint32_t tx_hung:       1;
-            uint32_t in_done:       1;
-            uint32_t in_suc_eof:    1;
-            uint32_t in_err_eof:    1;
-            uint32_t out_done:      1;
-            uint32_t out_eof:       1;
-            uint32_t in_dscr_err:   1;
-            uint32_t out_dscr_err:  1;
-            uint32_t in_dscr_empty: 1;
-            uint32_t out_total_eof: 1;
-            uint32_t reserved17:   15;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rx_take_data:  1;
-            uint32_t tx_put_data:   1;
-            uint32_t rx_wfull:      1;
-            uint32_t rx_rempty:     1;
-            uint32_t tx_wfull:      1;
-            uint32_t tx_rempty:     1;
-            uint32_t rx_hung:       1;
-            uint32_t tx_hung:       1;
-            uint32_t in_done:       1;
-            uint32_t in_suc_eof:    1;
-            uint32_t in_err_eof:    1;
-            uint32_t out_done:      1;
-            uint32_t out_eof:       1;
-            uint32_t in_dscr_err:   1;
-            uint32_t out_dscr_err:  1;
-            uint32_t in_dscr_empty: 1;
-            uint32_t out_total_eof: 1;
-            uint32_t reserved17:   15;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t rx_take_data:  1;
-            uint32_t tx_put_data:   1;
-            uint32_t rx_wfull:      1;
-            uint32_t rx_rempty:     1;
-            uint32_t tx_wfull:      1;
-            uint32_t tx_rempty:     1;
-            uint32_t rx_hung:       1;
-            uint32_t tx_hung:       1;
-            uint32_t in_done:       1;
-            uint32_t in_suc_eof:    1;
-            uint32_t in_err_eof:    1;
-            uint32_t out_done:      1;
-            uint32_t out_eof:       1;
-            uint32_t in_dscr_err:   1;
-            uint32_t out_dscr_err:  1;
-            uint32_t in_dscr_empty: 1;
-            uint32_t out_total_eof: 1;
-            uint32_t reserved17:   15;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t take_data:     1;
-            uint32_t put_data:      1;
-            uint32_t rx_wfull:      1;
-            uint32_t rx_rempty:     1;
-            uint32_t tx_wfull:      1;
-            uint32_t tx_rempty:     1;
-            uint32_t rx_hung:       1;
-            uint32_t tx_hung:       1;
-            uint32_t in_done:       1;
-            uint32_t in_suc_eof:    1;
-            uint32_t in_err_eof:    1;
-            uint32_t out_done:      1;
-            uint32_t out_eof:       1;
-            uint32_t in_dscr_err:   1;
-            uint32_t out_dscr_err:  1;
-            uint32_t in_dscr_empty: 1;
-            uint32_t out_total_eof: 1;
-            uint32_t reserved17:   15;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t tx_bck_in_delay:   2;
-            uint32_t tx_ws_in_delay:    2;
-            uint32_t rx_bck_in_delay:   2;
-            uint32_t rx_ws_in_delay:    2;
-            uint32_t rx_sd_in_delay:    2;
-            uint32_t tx_bck_out_delay:  2;
-            uint32_t tx_ws_out_delay:   2;
-            uint32_t tx_sd_out_delay:   2;
-            uint32_t rx_ws_out_delay:   2;
-            uint32_t rx_bck_out_delay:  2;
-            uint32_t tx_dsync_sw:       1;
-            uint32_t rx_dsync_sw:       1;
-            uint32_t data_enable_delay: 2;
-            uint32_t tx_bck_in_inv:     1;
-            uint32_t reserved25:        7;
-        };
-        uint32_t val;
-    } timing;
-    union {
-        struct {
-            uint32_t rx_data_num:          6;
-            uint32_t tx_data_num:          6;
-            uint32_t dscr_en:              1;
-            uint32_t tx_fifo_mod:          3;
-            uint32_t rx_fifo_mod:          3;
-            uint32_t tx_fifo_mod_force_en: 1;
-            uint32_t rx_fifo_mod_force_en: 1;
-            uint32_t reserved21:          11;
-        };
-        uint32_t val;
-    } fifo_conf;
-    uint32_t rx_eof_num;
-    uint32_t conf_single_data;
-    union {
-        struct {
-            uint32_t tx_chan_mod: 3;
-            uint32_t rx_chan_mod: 2;
-            uint32_t reserved5:  27;
-        };
-        uint32_t val;
-    } conf_chan;
-    union {
-        struct {
-            uint32_t addr:       20;
-            uint32_t reserved20:  8;
-            uint32_t stop:        1;
-            uint32_t start:       1;
-            uint32_t restart:     1;
-            uint32_t park:        1;
-        };
-        uint32_t val;
-    } out_link;
-    union {
-        struct {
-            uint32_t addr:       20;
-            uint32_t reserved20:  8;
-            uint32_t stop:        1;
-            uint32_t start:       1;
-            uint32_t restart:     1;
-            uint32_t park:        1;
-        };
-        uint32_t val;
-    } in_link;
-    uint32_t out_eof_des_addr;
-    uint32_t in_eof_des_addr;
-    uint32_t out_eof_bfr_des_addr;
-    union {
-        struct {
-            uint32_t mode:       3;
-            uint32_t reserved3:  1;
-            uint32_t addr:       2;
-            uint32_t reserved6: 26;
-        };
-        uint32_t val;
-    } ahb_test;
-    uint32_t in_link_dscr;
-    uint32_t in_link_dscr_bf0;
-    uint32_t in_link_dscr_bf1;
-    uint32_t out_link_dscr;
-    uint32_t out_link_dscr_bf0;
-    uint32_t out_link_dscr_bf1;
-    union {
-        struct {
-            uint32_t in_rst:             1;
-            uint32_t out_rst:            1;
-            uint32_t ahbm_fifo_rst:      1;
-            uint32_t ahbm_rst:           1;
-            uint32_t out_loop_test:      1;
-            uint32_t in_loop_test:       1;
-            uint32_t out_auto_wrback:    1;
-            uint32_t out_no_restart_clr: 1;
-            uint32_t out_eof_mode:       1;
-            uint32_t outdscr_burst_en:   1;
-            uint32_t indscr_burst_en:    1;
-            uint32_t out_data_burst_en:  1;
-            uint32_t check_owner:        1;
-            uint32_t mem_trans_en:       1;
-            uint32_t reserved14:        18;
-        };
-        uint32_t val;
-    } lc_conf;
-    union {
-        struct {
-            uint32_t wdata:      9;
-            uint32_t reserved9:  7;
-            uint32_t push:       1;
-            uint32_t reserved17: 15;
-        };
-        uint32_t val;
-    } out_fifo_push;
-    union {
-        struct {
-            uint32_t rdata:      12;
-            uint32_t reserved12:  4;
-            uint32_t pop:         1;
-            uint32_t reserved17: 15;
-        };
-        uint32_t val;
-    } in_fifo_pop;
-    uint32_t lc_state0;
-    uint32_t lc_state1;
-    union {
-        struct {
-            uint32_t fifo_timeout:       8;
-            uint32_t fifo_timeout_shift: 3;
-            uint32_t fifo_timeout_ena:   1;
-            uint32_t reserved12:        20;
-        };
-        uint32_t val;
-    } lc_hung_conf;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    union {
-        struct {
-            uint32_t y_max:16;
-            uint32_t y_min:16;
-        };
-        uint32_t val;
-    } cvsd_conf0;
-    union {
-        struct {
-            uint32_t sigma_max:16;
-            uint32_t sigma_min:16;
-        };
-        uint32_t val;
-    } cvsd_conf1;
-    union {
-        struct {
-            uint32_t cvsd_k:     3;
-            uint32_t cvsd_j:     3;
-            uint32_t cvsd_beta: 10;
-            uint32_t cvsd_h:     3;
-            uint32_t reserved19:13;
-        };
-        uint32_t val;
-    } cvsd_conf2;
-    union {
-        struct {
-            uint32_t good_pack_max:    6;
-            uint32_t n_err_seg:        3;
-            uint32_t shift_rate:       3;
-            uint32_t max_slide_sample: 8;
-            uint32_t pack_len_8k:      5;
-            uint32_t n_min_err:        3;
-            uint32_t reserved28:       4;
-        };
-        uint32_t val;
-    } plc_conf0;
-    union {
-        struct {
-            uint32_t bad_cef_atten_para:       8;
-            uint32_t bad_cef_atten_para_shift: 4;
-            uint32_t bad_ola_win2_para_shift:  4;
-            uint32_t bad_ola_win2_para:        8;
-            uint32_t slide_win_len:            8;
-        };
-        uint32_t val;
-    } plc_conf1;
-    union {
-        struct {
-            uint32_t cvsd_seg_mod: 2;
-            uint32_t min_period:   5;
-            uint32_t reserved7:   25;
-        };
-        uint32_t val;
-    } plc_conf2;
-    union {
-        struct {
-            uint32_t en:                1;
-            uint32_t chan_mod:          1;
-            uint32_t cvsd_dec_pack_err: 1;
-            uint32_t cvsd_pack_len_8k:  5;
-            uint32_t cvsd_inf_en:       1;
-            uint32_t cvsd_dec_start:    1;
-            uint32_t cvsd_dec_reset:    1;
-            uint32_t plc_en:            1;
-            uint32_t plc2dma_en:        1;
-            uint32_t reserved13:       19;
-        };
-        uint32_t val;
-    } esco_conf0;
-    union {
-        struct {
-            uint32_t with_en:        1;
-            uint32_t no_en:          1;
-            uint32_t cvsd_enc_start: 1;
-            uint32_t cvsd_enc_reset: 1;
-            uint32_t reserved4:     28;
-        };
-        uint32_t val;
-    } sco_conf0;
-    union {
-        struct {
-            uint32_t tx_pcm_conf:    3;
-            uint32_t tx_pcm_bypass:  1;
-            uint32_t rx_pcm_conf:    3;
-            uint32_t rx_pcm_bypass:  1;
-            uint32_t tx_stop_en:     1;
-            uint32_t tx_zeros_rm_en: 1;
-            uint32_t reserved10:    22;
-        };
-        uint32_t val;
-    } conf1;
-    union {
-        struct {
-            uint32_t fifo_force_pd:    1;
-            uint32_t fifo_force_pu:    1;
-            uint32_t plc_mem_force_pd: 1;
-            uint32_t plc_mem_force_pu: 1;
-            uint32_t reserved4:       28;
-        };
-        uint32_t val;
-    } pd_conf;
-    union {
-        struct {
-            uint32_t camera_en:           1;
-            uint32_t lcd_tx_wrx2_en:      1;
-            uint32_t lcd_tx_sdx2_en:      1;
-            uint32_t data_enable_test_en: 1;
-            uint32_t data_enable:         1;
-            uint32_t lcd_en:              1;
-            uint32_t ext_adc_start_en:    1;
-            uint32_t inter_valid_en:      1;
-            uint32_t reserved8:          24;
-        };
-        uint32_t val;
-    } conf2;
-    union {
-        struct {
-            uint32_t clkm_div_num: 8;
-            uint32_t clkm_div_b:   6;
-            uint32_t clkm_div_a:   6;
-            uint32_t clk_en:       1;
-            uint32_t clka_en:      1;
-            uint32_t reserved22:  10;
-        };
-        uint32_t val;
-    } clkm_conf;
-    union {
-        struct {
-            uint32_t tx_bck_div_num: 6;
-            uint32_t rx_bck_div_num: 6;
-            uint32_t tx_bits_mod:    6;
-            uint32_t rx_bits_mod:    6;
-            uint32_t reserved24:     8;
-        };
-        uint32_t val;
-    } sample_rate_conf;
-    union {
-        struct {
-            uint32_t tx_pdm_en:              1;
-            uint32_t rx_pdm_en:              1;
-            uint32_t pcm2pdm_conv_en:        1;
-            uint32_t pdm2pcm_conv_en:        1;
-            uint32_t tx_sinc_osr2:           4;
-            uint32_t tx_prescale:            8;
-            uint32_t tx_hp_in_shift:         2;
-            uint32_t tx_lp_in_shift:         2;
-            uint32_t tx_sinc_in_shift:       2;
-            uint32_t tx_sigmadelta_in_shift: 2;
-            uint32_t rx_sinc_dsr_16_en:      1;
-            uint32_t txhp_bypass:            1;
-            uint32_t reserved26:             6;
-        };
-        uint32_t val;
-    } pdm_conf;
-    union {
-        struct {
-            uint32_t tx_pdm_fs: 10;
-            uint32_t tx_pdm_fp: 10;
-            uint32_t reserved20:12;
-        };
-        uint32_t val;
-    } pdm_freq_conf;
-    union {
-        struct {
-            uint32_t tx_idle:            1;
-            uint32_t tx_fifo_reset_back: 1;
-            uint32_t rx_fifo_reset_back: 1;
-            uint32_t reserved3:         29;
-        };
-        uint32_t val;
-    } state;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t date;                                        /**/
-} i2s_dev_t;
-extern i2s_dev_t I2S0;
-extern i2s_dev_t I2S1;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_I2S_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/io_mux_reg.h b/tools/sdk/include/soc/soc/io_mux_reg.h
deleted file mode 100644
index 25978b326ff..00000000000
--- a/tools/sdk/include/soc/soc/io_mux_reg.h
+++ /dev/null
@@ -1,382 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_IO_MUX_REG_H_
-#define _SOC_IO_MUX_REG_H_
-
-#include "soc.h"
-
-/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
-/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
-/* Pin used for wakeup from sleep */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
-/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
-/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
-/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
-/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
-/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
-/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
-/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
-/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
-/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
-
-#define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-
-/*
- * @attention
- *     The PIN_PULL[UP|DWN]_[EN|DIS]() functions used to exist as macros in previous SDK versions. 
- *     Unfortunately, however, they do not work for some GPIOs on the ESP32 chip, which needs pullups 
- *     and -downs turned on and off through RTC registers. The functions still exist for compatibility 
- *     with older code, but are marked as deprecated in order to generate a warning.
- *     Please replace them in this fashion: (make sure to include driver/gpio.h as well)
- *     PIN_PULLUP_EN(GPIO_PIN_MUX_REG[x])   ->  gpio_pullup_en(x)
- *     PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[x])  ->  gpio_pullup_dis(x)
- *     PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[x])  ->  gpio_pulldown_en(x)
- *     PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[x]) ->  gpio_pulldown_dis(x)
- *
-*/
-static inline void __attribute__ ((deprecated)) PIN_PULLUP_DIS(uint32_t PIN_NAME) 
-{
-    REG_CLR_BIT(PIN_NAME, FUN_PU);
-}
-
-static inline void __attribute__ ((deprecated)) PIN_PULLUP_EN(uint32_t PIN_NAME)
-{
-    REG_SET_BIT(PIN_NAME, FUN_PU);
-}
-
-static inline void __attribute__ ((deprecated)) PIN_PULLDWN_DIS(uint32_t PIN_NAME)
-{
-    REG_CLR_BIT(PIN_NAME, FUN_PD);
-}
-
-static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME)
-{
-    REG_SET_BIT(PIN_NAME, FUN_PD);
-}
-
-
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-
-#define PIN_FUNC_GPIO                               2
-
-#define PIN_CTRL                          (DR_REG_IO_MUX_BASE +0x00)
-#define CLK_OUT3                                    0xf
-#define CLK_OUT3_V                                  CLK_OUT3
-#define CLK_OUT3_S                                  8
-#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
-#define CLK_OUT2                                    0xf
-#define CLK_OUT2_V                                  CLK_OUT2
-#define CLK_OUT2_S                                  4
-#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
-#define CLK_OUT1                                    0xf
-#define CLK_OUT1_V                                  CLK_OUT1
-#define CLK_OUT1_S                                  0
-#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
-
-#define PERIPHS_IO_MUX_GPIO0_U            (DR_REG_IO_MUX_BASE +0x44)
-#define IO_MUX_GPIO0_REG                  PERIPHS_IO_MUX_GPIO0_U
-#define FUNC_GPIO0_EMAC_TX_CLK                      5
-#define FUNC_GPIO0_GPIO0                            2
-#define FUNC_GPIO0_CLK_OUT1                         1
-#define FUNC_GPIO0_GPIO0_0                          0
-
-#define PERIPHS_IO_MUX_U0TXD_U            (DR_REG_IO_MUX_BASE +0x88)
-#define IO_MUX_GPIO1_REG                  PERIPHS_IO_MUX_U0TXD_U
-#define FUNC_U0TXD_EMAC_RXD2                        5
-#define FUNC_U0TXD_GPIO1                            2
-#define FUNC_U0TXD_CLK_OUT3                         1
-#define FUNC_U0TXD_U0TXD                            0
-
-#define PERIPHS_IO_MUX_GPIO2_U            (DR_REG_IO_MUX_BASE +0x40)
-#define IO_MUX_GPIO2_REG                  PERIPHS_IO_MUX_GPIO2_U
-#define FUNC_GPIO2_SD_DATA0                         4
-#define FUNC_GPIO2_HS2_DATA0                        3
-#define FUNC_GPIO2_GPIO2                            2
-#define FUNC_GPIO2_HSPIWP                           1
-#define FUNC_GPIO2_GPIO2_0                          0
-
-#define PERIPHS_IO_MUX_U0RXD_U            (DR_REG_IO_MUX_BASE +0x84)
-#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U0RXD_U
-#define FUNC_U0RXD_GPIO3                            2
-#define FUNC_U0RXD_CLK_OUT2                         1
-#define FUNC_U0RXD_U0RXD                            0
-
-#define PERIPHS_IO_MUX_GPIO4_U            (DR_REG_IO_MUX_BASE +0x48)
-#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_GPIO4_U
-#define FUNC_GPIO4_EMAC_TX_ER                       5
-#define FUNC_GPIO4_SD_DATA1                         4
-#define FUNC_GPIO4_HS2_DATA1                        3
-#define FUNC_GPIO4_GPIO4                            2
-#define FUNC_GPIO4_HSPIHD                           1
-#define FUNC_GPIO4_GPIO4_0                          0
-
-#define PERIPHS_IO_MUX_GPIO5_U            (DR_REG_IO_MUX_BASE +0x6c)
-#define IO_MUX_GPIO5_REG                   PERIPHS_IO_MUX_GPIO5_U
-#define FUNC_GPIO5_EMAC_RX_CLK                      5
-#define FUNC_GPIO5_HS1_DATA6                        3
-#define FUNC_GPIO5_GPIO5                            2
-#define FUNC_GPIO5_VSPICS0                          1
-#define FUNC_GPIO5_GPIO5_0                          0
-
-#define PERIPHS_IO_MUX_SD_CLK_U           (DR_REG_IO_MUX_BASE +0x60)
-#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_SD_CLK_U
-#define FUNC_SD_CLK_U1CTS                           4
-#define FUNC_SD_CLK_HS1_CLK                         3
-#define FUNC_SD_CLK_GPIO6                           2
-#define FUNC_SD_CLK_SPICLK                          1
-#define FUNC_SD_CLK_SD_CLK                          0
-
-#define PERIPHS_IO_MUX_SD_DATA0_U         (DR_REG_IO_MUX_BASE +0x64)
-#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_SD_DATA0_U
-#define FUNC_SD_DATA0_U2RTS                         4
-#define FUNC_SD_DATA0_HS1_DATA0                     3
-#define FUNC_SD_DATA0_GPIO7                         2
-#define FUNC_SD_DATA0_SPIQ                          1
-#define FUNC_SD_DATA0_SD_DATA0                      0
-
-#define PERIPHS_IO_MUX_SD_DATA1_U         (DR_REG_IO_MUX_BASE +0x68)
-#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_SD_DATA1_U
-#define FUNC_SD_DATA1_U2CTS                         4
-#define FUNC_SD_DATA1_HS1_DATA1                     3
-#define FUNC_SD_DATA1_GPIO8                         2
-#define FUNC_SD_DATA1_SPID                          1
-#define FUNC_SD_DATA1_SD_DATA1                      0
-
-#define PERIPHS_IO_MUX_SD_DATA2_U         (DR_REG_IO_MUX_BASE +0x54)
-#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_SD_DATA2_U
-#define FUNC_SD_DATA2_U1RXD                         4
-#define FUNC_SD_DATA2_HS1_DATA2                     3
-#define FUNC_SD_DATA2_GPIO9                         2
-#define FUNC_SD_DATA2_SPIHD                         1
-#define FUNC_SD_DATA2_SD_DATA2                      0
-
-#define PERIPHS_IO_MUX_SD_DATA3_U         (DR_REG_IO_MUX_BASE +0x58)
-#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_SD_DATA3_U
-#define FUNC_SD_DATA3_U1TXD                         4
-#define FUNC_SD_DATA3_HS1_DATA3                     3
-#define FUNC_SD_DATA3_GPIO10                        2
-#define FUNC_SD_DATA3_SPIWP                         1
-#define FUNC_SD_DATA3_SD_DATA3                      0
-
-#define PERIPHS_IO_MUX_SD_CMD_U           (DR_REG_IO_MUX_BASE +0x5c)
-#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_SD_CMD_U
-#define FUNC_SD_CMD_U1RTS                           4
-#define FUNC_SD_CMD_HS1_CMD                         3
-#define FUNC_SD_CMD_GPIO11                          2
-#define FUNC_SD_CMD_SPICS0                          1
-#define FUNC_SD_CMD_SD_CMD                          0
-
-#define PERIPHS_IO_MUX_MTDI_U             (DR_REG_IO_MUX_BASE +0x34)
-#define IO_MUX_GPIO12_REG                    PERIPHS_IO_MUX_MTDI_U
-#define FUNC_MTDI_EMAC_TXD3                         5
-#define FUNC_MTDI_SD_DATA2                          4
-#define FUNC_MTDI_HS2_DATA2                         3
-#define FUNC_MTDI_GPIO12                            2
-#define FUNC_MTDI_HSPIQ                             1
-#define FUNC_MTDI_MTDI                              0
-
-#define PERIPHS_IO_MUX_MTCK_U             (DR_REG_IO_MUX_BASE +0x38)
-#define IO_MUX_GPIO13_REG                    PERIPHS_IO_MUX_MTCK_U
-#define FUNC_MTCK_EMAC_RX_ER                        5
-#define FUNC_MTCK_SD_DATA3                          4
-#define FUNC_MTCK_HS2_DATA3                         3
-#define FUNC_MTCK_GPIO13                            2
-#define FUNC_MTCK_HSPID                             1
-#define FUNC_MTCK_MTCK                              0
-
-#define PERIPHS_IO_MUX_MTMS_U             (DR_REG_IO_MUX_BASE +0x30)
-#define IO_MUX_GPIO14_REG                    PERIPHS_IO_MUX_MTMS_U
-#define FUNC_MTMS_EMAC_TXD2                         5
-#define FUNC_MTMS_SD_CLK                            4
-#define FUNC_MTMS_HS2_CLK                           3
-#define FUNC_MTMS_GPIO14                            2
-#define FUNC_MTMS_HSPICLK                           1
-#define FUNC_MTMS_MTMS                              0
-
-#define PERIPHS_IO_MUX_MTDO_U             (DR_REG_IO_MUX_BASE +0x3c)
-#define IO_MUX_GPIO15_REG                    PERIPHS_IO_MUX_MTDO_U
-#define FUNC_MTDO_EMAC_RXD3                         5
-#define FUNC_MTDO_SD_CMD                            4
-#define FUNC_MTDO_HS2_CMD                           3
-#define FUNC_MTDO_GPIO15                            2
-#define FUNC_MTDO_HSPICS0                           1
-#define FUNC_MTDO_MTDO                              0
-
-#define PERIPHS_IO_MUX_GPIO16_U           (DR_REG_IO_MUX_BASE +0x4c)
-#define IO_MUX_GPIO16_REG                    PERIPHS_IO_MUX_GPIO16_U
-#define FUNC_GPIO16_EMAC_CLK_OUT                    5
-#define FUNC_GPIO16_U2RXD                           4
-#define FUNC_GPIO16_HS1_DATA4                       3
-#define FUNC_GPIO16_GPIO16                          2
-#define FUNC_GPIO16_GPIO16_0                        0
-
-#define PERIPHS_IO_MUX_GPIO17_U           (DR_REG_IO_MUX_BASE +0x50)
-#define IO_MUX_GPIO17_REG                    PERIPHS_IO_MUX_GPIO17_U
-#define FUNC_GPIO17_EMAC_CLK_OUT_180                5
-#define FUNC_GPIO17_U2TXD                           4
-#define FUNC_GPIO17_HS1_DATA5                       3
-#define FUNC_GPIO17_GPIO17                          2
-#define FUNC_GPIO17_GPIO17_0                        0
-
-#define PERIPHS_IO_MUX_GPIO18_U           (DR_REG_IO_MUX_BASE +0x70)
-#define IO_MUX_GPIO18_REG                    PERIPHS_IO_MUX_GPIO18_U
-#define FUNC_GPIO18_HS1_DATA7                       3
-#define FUNC_GPIO18_GPIO18                          2
-#define FUNC_GPIO18_VSPICLK                         1
-#define FUNC_GPIO18_GPIO18_0                        0
-
-#define PERIPHS_IO_MUX_GPIO19_U           (DR_REG_IO_MUX_BASE +0x74)
-#define IO_MUX_GPIO19_REG                    PERIPHS_IO_MUX_GPIO19_U
-#define FUNC_GPIO19_EMAC_TXD0                       5
-#define FUNC_GPIO19_U0CTS                           3
-#define FUNC_GPIO19_GPIO19                          2
-#define FUNC_GPIO19_VSPIQ                           1
-#define FUNC_GPIO19_GPIO19_0                        0
-
-#define PERIPHS_IO_MUX_GPIO20_U           (DR_REG_IO_MUX_BASE +0x78)
-#define IO_MUX_GPIO20_REG                    PERIPHS_IO_MUX_GPIO20_U
-#define FUNC_GPIO20_GPIO20                          2
-#define FUNC_GPIO20_GPIO20_0                        0
-
-#define PERIPHS_IO_MUX_GPIO21_U           (DR_REG_IO_MUX_BASE +0x7c)
-#define IO_MUX_GPIO21_REG                    PERIPHS_IO_MUX_GPIO21_U
-#define FUNC_GPIO21_EMAC_TX_EN                      5
-#define FUNC_GPIO21_GPIO21                          2
-#define FUNC_GPIO21_VSPIHD                          1
-#define FUNC_GPIO21_GPIO21_0                        0
-
-#define PERIPHS_IO_MUX_GPIO22_U           (DR_REG_IO_MUX_BASE +0x80)
-#define IO_MUX_GPIO22_REG                    PERIPHS_IO_MUX_GPIO22_U
-#define FUNC_GPIO22_EMAC_TXD1                       5
-#define FUNC_GPIO22_U0RTS                           3
-#define FUNC_GPIO22_GPIO22                          2
-#define FUNC_GPIO22_VSPIWP                          1
-#define FUNC_GPIO22_GPIO22_0                        0
-
-#define PERIPHS_IO_MUX_GPIO23_U           (DR_REG_IO_MUX_BASE +0x8c)
-#define IO_MUX_GPIO23_REG                    PERIPHS_IO_MUX_GPIO23_U
-#define FUNC_GPIO23_HS1_STROBE                      3
-#define FUNC_GPIO23_GPIO23                          2
-#define FUNC_GPIO23_VSPID                           1
-#define FUNC_GPIO23_GPIO23_0                        0
-
-#define PERIPHS_IO_MUX_GPIO24_U           (DR_REG_IO_MUX_BASE +0x90)
-#define IO_MUX_GPIO24_REG                    PERIPHS_IO_MUX_GPIO24_U
-#define FUNC_GPIO24_GPIO24                          2
-#define FUNC_GPIO24_GPIO24_0                        0
-
-#define PERIPHS_IO_MUX_GPIO25_U           (DR_REG_IO_MUX_BASE +0x24)
-#define IO_MUX_GPIO25_REG                    PERIPHS_IO_MUX_GPIO25_U
-#define FUNC_GPIO25_EMAC_RXD0                       5
-#define FUNC_GPIO25_GPIO25                          2
-#define FUNC_GPIO25_GPIO25_0                        0
-
-#define PERIPHS_IO_MUX_GPIO26_U           (DR_REG_IO_MUX_BASE +0x28)
-#define IO_MUX_GPIO26_REG                    PERIPHS_IO_MUX_GPIO26_U
-#define FUNC_GPIO26_EMAC_RXD1                       5
-#define FUNC_GPIO26_GPIO26                          2
-#define FUNC_GPIO26_GPIO26_0                        0
-
-#define PERIPHS_IO_MUX_GPIO27_U           (DR_REG_IO_MUX_BASE +0x2c)
-#define IO_MUX_GPIO27_REG                    PERIPHS_IO_MUX_GPIO27_U
-#define FUNC_GPIO27_EMAC_RX_DV                      5
-#define FUNC_GPIO27_GPIO27                          2
-#define FUNC_GPIO27_GPIO27_0                        0
-
-#define PERIPHS_IO_MUX_GPIO32_U           (DR_REG_IO_MUX_BASE +0x1c)
-#define IO_MUX_GPIO32_REG                    PERIPHS_IO_MUX_GPIO32_U
-#define FUNC_GPIO32_GPIO32                          2
-#define FUNC_GPIO32_GPIO32_0                        0
-
-#define PERIPHS_IO_MUX_GPIO33_U           (DR_REG_IO_MUX_BASE +0x20)
-#define IO_MUX_GPIO33_REG                    PERIPHS_IO_MUX_GPIO33_U
-#define FUNC_GPIO33_GPIO33                          2
-#define FUNC_GPIO33_GPIO33_0                        0
-
-#define PERIPHS_IO_MUX_GPIO34_U           (DR_REG_IO_MUX_BASE +0x14)
-#define IO_MUX_GPIO34_REG                    PERIPHS_IO_MUX_GPIO34_U
-#define FUNC_GPIO34_GPIO34                          2
-#define FUNC_GPIO34_GPIO34_0                        0
-
-#define PERIPHS_IO_MUX_GPIO35_U           (DR_REG_IO_MUX_BASE +0x18)
-#define IO_MUX_GPIO35_REG                    PERIPHS_IO_MUX_GPIO35_U
-#define FUNC_GPIO35_GPIO35                          2
-#define FUNC_GPIO35_GPIO35_0                        0
-
-#define PERIPHS_IO_MUX_GPIO36_U           (DR_REG_IO_MUX_BASE +0x04)
-#define IO_MUX_GPIO36_REG                    PERIPHS_IO_MUX_GPIO36_U
-#define FUNC_GPIO36_GPIO36                          2
-#define FUNC_GPIO36_GPIO36_0                        0
-
-#define PERIPHS_IO_MUX_GPIO37_U           (DR_REG_IO_MUX_BASE +0x08)
-#define IO_MUX_GPIO37_REG                    PERIPHS_IO_MUX_GPIO37_U
-#define FUNC_GPIO37_GPIO37                          2
-#define FUNC_GPIO37_GPIO37_0                        0
-
-#define PERIPHS_IO_MUX_GPIO38_U           (DR_REG_IO_MUX_BASE +0x0c)
-#define IO_MUX_GPIO38_REG                    PERIPHS_IO_MUX_GPIO38_U
-#define FUNC_GPIO38_GPIO38                          2
-#define FUNC_GPIO38_GPIO38_0                        0
-
-#define PERIPHS_IO_MUX_GPIO39_U           (DR_REG_IO_MUX_BASE +0x10)
-#define IO_MUX_GPIO39_REG                    PERIPHS_IO_MUX_GPIO39_U
-#define FUNC_GPIO39_GPIO39                          2
-#define FUNC_GPIO39_GPIO39_0                        0
-
-#endif /* _SOC_IO_MUX_REG_H_ */
diff --git a/tools/sdk/include/soc/soc/ledc_reg.h b/tools/sdk/include/soc/soc/ledc_reg.h
deleted file mode 100644
index 559be87361e..00000000000
--- a/tools/sdk/include/soc/soc/ledc_reg.h
+++ /dev/null
@@ -1,2463 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_LEDC_REG_H_
-#define _SOC_LEDC_REG_H_
-
-
-#include "soc.h"
-#define LEDC_HSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x0000)
-/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: This bit is clock gating control signal. when software config
- LED_PWM internal registers  it controls the register clock.*/
-#define LEDC_CLK_EN  (BIT(31))
-#define LEDC_CLK_EN_M  (BIT(31))
-#define LEDC_CLK_EN_V  0x1
-#define LEDC_CLK_EN_S  31
-/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when high speed channel0 is off.*/
-#define LEDC_IDLE_LV_HSCH0  (BIT(3))
-#define LEDC_IDLE_LV_HSCH0_M  (BIT(3))
-#define LEDC_IDLE_LV_HSCH0_V  0x1
-#define LEDC_IDLE_LV_HSCH0_S  3
-/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for high speed channel0*/
-#define LEDC_SIG_OUT_EN_HSCH0  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH0_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH0_V  0x1
-#define LEDC_SIG_OUT_EN_HSCH0_S  2
-/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four high speed timers  the two bits are used to select
- one of them for high speed channel0.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
-#define LEDC_TIMER_SEL_HSCH0  0x00000003
-#define LEDC_TIMER_SEL_HSCH0_M  ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S))
-#define LEDC_TIMER_SEL_HSCH0_V  0x3
-#define LEDC_TIMER_SEL_HSCH0_S  0
-
-#define LEDC_HSCH0_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0004)
-/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when htimerx(x=[0 3]) selected
- by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/
-#define LEDC_HPOINT_HSCH0  0x000FFFFF
-#define LEDC_HPOINT_HSCH0_M  ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S))
-#define LEDC_HPOINT_HSCH0_V  0xFFFFF
-#define LEDC_HPOINT_HSCH0_S  0
-
-#define LEDC_HSCH0_DUTY_REG          (DR_REG_LEDC_BASE + 0x0008)
-/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When hstimerx(x=[0
- 3]) choosed by high speed channel0  has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4])          (1)  reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_HSCH0  0x01FFFFFF
-#define LEDC_DUTY_HSCH0_M  ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))
-#define LEDC_DUTY_HSCH0_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH0_S  0
-
-#define LEDC_HSCH0_CONF1_REG          (DR_REG_LEDC_BASE + 0x000C)
-/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0
- has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_HSCH0  (BIT(31))
-#define LEDC_DUTY_START_HSCH0_M  (BIT(31))
-#define LEDC_DUTY_START_HSCH0_V  0x1
-#define LEDC_DUTY_START_HSCH0_S  31
-/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for high speed channel0.*/
-#define LEDC_DUTY_INC_HSCH0  (BIT(30))
-#define LEDC_DUTY_INC_HSCH0_M  (BIT(30))
-#define LEDC_DUTY_INC_HSCH0_V  0x1
-#define LEDC_DUTY_INC_HSCH0_S  30
-/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for high speed channel0.*/
-#define LEDC_DUTY_NUM_HSCH0  0x000003FF
-#define LEDC_DUTY_NUM_HSCH0_M  ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S))
-#define LEDC_DUTY_NUM_HSCH0_V  0x3FF
-#define LEDC_DUTY_NUM_HSCH0_S  20
-/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_hsch0 cycles for high speed channel0.*/
-#define LEDC_DUTY_CYCLE_HSCH0  0x000003FF
-#define LEDC_DUTY_CYCLE_HSCH0_M  ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S))
-#define LEDC_DUTY_CYCLE_HSCH0_V  0x3FF
-#define LEDC_DUTY_CYCLE_HSCH0_S  10
-/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- high speed channel0.*/
-#define LEDC_DUTY_SCALE_HSCH0  0x000003FF
-#define LEDC_DUTY_SCALE_HSCH0_M  ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S))
-#define LEDC_DUTY_SCALE_HSCH0_V  0x3FF
-#define LEDC_DUTY_SCALE_HSCH0_S  0
-
-#define LEDC_HSCH0_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0010)
-/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for high speed channel0.*/
-#define LEDC_DUTY_HSCH0  0x01FFFFFF
-#define LEDC_DUTY_HSCH0_M  ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))
-#define LEDC_DUTY_HSCH0_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH0_S  0
-
-#define LEDC_HSCH1_CONF0_REG          (DR_REG_LEDC_BASE + 0x0014)
-/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when high speed channel1 is off.*/
-#define LEDC_IDLE_LV_HSCH1  (BIT(3))
-#define LEDC_IDLE_LV_HSCH1_M  (BIT(3))
-#define LEDC_IDLE_LV_HSCH1_V  0x1
-#define LEDC_IDLE_LV_HSCH1_S  3
-/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for high speed channel1*/
-#define LEDC_SIG_OUT_EN_HSCH1  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH1_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH1_V  0x1
-#define LEDC_SIG_OUT_EN_HSCH1_S  2
-/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four high speed timers  the two bits are used to select
- one of them for high speed channel1.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
-#define LEDC_TIMER_SEL_HSCH1  0x00000003
-#define LEDC_TIMER_SEL_HSCH1_M  ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S))
-#define LEDC_TIMER_SEL_HSCH1_V  0x3
-#define LEDC_TIMER_SEL_HSCH1_S  0
-
-#define LEDC_HSCH1_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0018)
-/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when htimerx(x=[0 3]) selected
- by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/
-#define LEDC_HPOINT_HSCH1  0x000FFFFF
-#define LEDC_HPOINT_HSCH1_M  ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S))
-#define LEDC_HPOINT_HSCH1_V  0xFFFFF
-#define LEDC_HPOINT_HSCH1_S  0
-
-#define LEDC_HSCH1_DUTY_REG          (DR_REG_LEDC_BASE + 0x001C)
-/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When hstimerx(x=[0
- 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4])          (1)  reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_HSCH1  0x01FFFFFF
-#define LEDC_DUTY_HSCH1_M  ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))
-#define LEDC_DUTY_HSCH1_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH1_S  0
-
-#define LEDC_HSCH1_CONF1_REG          (DR_REG_LEDC_BASE + 0x0020)
-/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_HSCH1  (BIT(31))
-#define LEDC_DUTY_START_HSCH1_M  (BIT(31))
-#define LEDC_DUTY_START_HSCH1_V  0x1
-#define LEDC_DUTY_START_HSCH1_S  31
-/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for high speed channel1.*/
-#define LEDC_DUTY_INC_HSCH1  (BIT(30))
-#define LEDC_DUTY_INC_HSCH1_M  (BIT(30))
-#define LEDC_DUTY_INC_HSCH1_V  0x1
-#define LEDC_DUTY_INC_HSCH1_S  30
-/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for high speed channel1.*/
-#define LEDC_DUTY_NUM_HSCH1  0x000003FF
-#define LEDC_DUTY_NUM_HSCH1_M  ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S))
-#define LEDC_DUTY_NUM_HSCH1_V  0x3FF
-#define LEDC_DUTY_NUM_HSCH1_S  20
-/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_hsch1 cycles for high speed channel1.*/
-#define LEDC_DUTY_CYCLE_HSCH1  0x000003FF
-#define LEDC_DUTY_CYCLE_HSCH1_M  ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S))
-#define LEDC_DUTY_CYCLE_HSCH1_V  0x3FF
-#define LEDC_DUTY_CYCLE_HSCH1_S  10
-/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- high speed channel1.*/
-#define LEDC_DUTY_SCALE_HSCH1  0x000003FF
-#define LEDC_DUTY_SCALE_HSCH1_M  ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S))
-#define LEDC_DUTY_SCALE_HSCH1_V  0x3FF
-#define LEDC_DUTY_SCALE_HSCH1_S  0
-
-#define LEDC_HSCH1_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0024)
-/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for high speed channel1.*/
-#define LEDC_DUTY_HSCH1  0x01FFFFFF
-#define LEDC_DUTY_HSCH1_M  ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))
-#define LEDC_DUTY_HSCH1_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH1_S  0
-
-#define LEDC_HSCH2_CONF0_REG          (DR_REG_LEDC_BASE + 0x0028)
-/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when high speed channel2 is off.*/
-#define LEDC_IDLE_LV_HSCH2  (BIT(3))
-#define LEDC_IDLE_LV_HSCH2_M  (BIT(3))
-#define LEDC_IDLE_LV_HSCH2_V  0x1
-#define LEDC_IDLE_LV_HSCH2_S  3
-/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for high speed channel2*/
-#define LEDC_SIG_OUT_EN_HSCH2  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH2_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH2_V  0x1
-#define LEDC_SIG_OUT_EN_HSCH2_S  2
-/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four high speed timers  the two bits are used to select
- one of them for high speed channel2.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
-#define LEDC_TIMER_SEL_HSCH2  0x00000003
-#define LEDC_TIMER_SEL_HSCH2_M  ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S))
-#define LEDC_TIMER_SEL_HSCH2_V  0x3
-#define LEDC_TIMER_SEL_HSCH2_S  0
-
-#define LEDC_HSCH2_HPOINT_REG          (DR_REG_LEDC_BASE + 0x002C)
-/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when htimerx(x=[0 3]) selected
- by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/
-#define LEDC_HPOINT_HSCH2  0x000FFFFF
-#define LEDC_HPOINT_HSCH2_M  ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S))
-#define LEDC_HPOINT_HSCH2_V  0xFFFFF
-#define LEDC_HPOINT_HSCH2_S  0
-
-#define LEDC_HSCH2_DUTY_REG          (DR_REG_LEDC_BASE + 0x0030)
-/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When hstimerx(x=[0
- 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4])          (1)  reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_HSCH2  0x01FFFFFF
-#define LEDC_DUTY_HSCH2_M  ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))
-#define LEDC_DUTY_HSCH2_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH2_S  0
-
-#define LEDC_HSCH2_CONF1_REG          (DR_REG_LEDC_BASE + 0x0034)
-/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2
- has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_HSCH2  (BIT(31))
-#define LEDC_DUTY_START_HSCH2_M  (BIT(31))
-#define LEDC_DUTY_START_HSCH2_V  0x1
-#define LEDC_DUTY_START_HSCH2_S  31
-/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for high speed channel2.*/
-#define LEDC_DUTY_INC_HSCH2  (BIT(30))
-#define LEDC_DUTY_INC_HSCH2_M  (BIT(30))
-#define LEDC_DUTY_INC_HSCH2_V  0x1
-#define LEDC_DUTY_INC_HSCH2_S  30
-/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for high speed channel2.*/
-#define LEDC_DUTY_NUM_HSCH2  0x000003FF
-#define LEDC_DUTY_NUM_HSCH2_M  ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S))
-#define LEDC_DUTY_NUM_HSCH2_V  0x3FF
-#define LEDC_DUTY_NUM_HSCH2_S  20
-/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_hsch2 cycles for high speed channel2.*/
-#define LEDC_DUTY_CYCLE_HSCH2  0x000003FF
-#define LEDC_DUTY_CYCLE_HSCH2_M  ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S))
-#define LEDC_DUTY_CYCLE_HSCH2_V  0x3FF
-#define LEDC_DUTY_CYCLE_HSCH2_S  10
-/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- high speed channel2.*/
-#define LEDC_DUTY_SCALE_HSCH2  0x000003FF
-#define LEDC_DUTY_SCALE_HSCH2_M  ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S))
-#define LEDC_DUTY_SCALE_HSCH2_V  0x3FF
-#define LEDC_DUTY_SCALE_HSCH2_S  0
-
-#define LEDC_HSCH2_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0038)
-/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for high speed channel2.*/
-#define LEDC_DUTY_HSCH2  0x01FFFFFF
-#define LEDC_DUTY_HSCH2_M  ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))
-#define LEDC_DUTY_HSCH2_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH2_S  0
-
-#define LEDC_HSCH3_CONF0_REG          (DR_REG_LEDC_BASE + 0x003C)
-/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when high speed channel3 is off.*/
-#define LEDC_IDLE_LV_HSCH3  (BIT(3))
-#define LEDC_IDLE_LV_HSCH3_M  (BIT(3))
-#define LEDC_IDLE_LV_HSCH3_V  0x1
-#define LEDC_IDLE_LV_HSCH3_S  3
-/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for high speed channel3*/
-#define LEDC_SIG_OUT_EN_HSCH3  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH3_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH3_V  0x1
-#define LEDC_SIG_OUT_EN_HSCH3_S  2
-/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four high speed timers  the two bits are used to select
- one of them for high speed channel3.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
-#define LEDC_TIMER_SEL_HSCH3  0x00000003
-#define LEDC_TIMER_SEL_HSCH3_M  ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S))
-#define LEDC_TIMER_SEL_HSCH3_V  0x3
-#define LEDC_TIMER_SEL_HSCH3_S  0
-
-#define LEDC_HSCH3_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0040)
-/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when htimerx(x=[0 3]) selected
- by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/
-#define LEDC_HPOINT_HSCH3  0x000FFFFF
-#define LEDC_HPOINT_HSCH3_M  ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S))
-#define LEDC_HPOINT_HSCH3_V  0xFFFFF
-#define LEDC_HPOINT_HSCH3_S  0
-
-#define LEDC_HSCH3_DUTY_REG          (DR_REG_LEDC_BASE + 0x0044)
-/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When hstimerx(x=[0
- 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4])          (1)  reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_HSCH3  0x01FFFFFF
-#define LEDC_DUTY_HSCH3_M  ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))
-#define LEDC_DUTY_HSCH3_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH3_S  0
-
-#define LEDC_HSCH3_CONF1_REG          (DR_REG_LEDC_BASE + 0x0048)
-/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3
- has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_HSCH3  (BIT(31))
-#define LEDC_DUTY_START_HSCH3_M  (BIT(31))
-#define LEDC_DUTY_START_HSCH3_V  0x1
-#define LEDC_DUTY_START_HSCH3_S  31
-/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for high speed channel3.*/
-#define LEDC_DUTY_INC_HSCH3  (BIT(30))
-#define LEDC_DUTY_INC_HSCH3_M  (BIT(30))
-#define LEDC_DUTY_INC_HSCH3_V  0x1
-#define LEDC_DUTY_INC_HSCH3_S  30
-/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for high speed channel3.*/
-#define LEDC_DUTY_NUM_HSCH3  0x000003FF
-#define LEDC_DUTY_NUM_HSCH3_M  ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S))
-#define LEDC_DUTY_NUM_HSCH3_V  0x3FF
-#define LEDC_DUTY_NUM_HSCH3_S  20
-/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_hsch3 cycles for high speed channel3.*/
-#define LEDC_DUTY_CYCLE_HSCH3  0x000003FF
-#define LEDC_DUTY_CYCLE_HSCH3_M  ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S))
-#define LEDC_DUTY_CYCLE_HSCH3_V  0x3FF
-#define LEDC_DUTY_CYCLE_HSCH3_S  10
-/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- high speed channel3.*/
-#define LEDC_DUTY_SCALE_HSCH3  0x000003FF
-#define LEDC_DUTY_SCALE_HSCH3_M  ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S))
-#define LEDC_DUTY_SCALE_HSCH3_V  0x3FF
-#define LEDC_DUTY_SCALE_HSCH3_S  0
-
-#define LEDC_HSCH3_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x004C)
-/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for high speed channel3.*/
-#define LEDC_DUTY_HSCH3  0x01FFFFFF
-#define LEDC_DUTY_HSCH3_M  ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))
-#define LEDC_DUTY_HSCH3_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH3_S  0
-
-#define LEDC_HSCH4_CONF0_REG          (DR_REG_LEDC_BASE + 0x0050)
-/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when high speed channel4 is off.*/
-#define LEDC_IDLE_LV_HSCH4  (BIT(3))
-#define LEDC_IDLE_LV_HSCH4_M  (BIT(3))
-#define LEDC_IDLE_LV_HSCH4_V  0x1
-#define LEDC_IDLE_LV_HSCH4_S  3
-/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for high speed channel4*/
-#define LEDC_SIG_OUT_EN_HSCH4  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH4_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH4_V  0x1
-#define LEDC_SIG_OUT_EN_HSCH4_S  2
-/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four high speed timers  the two bits are used to select
- one of them for high speed channel4.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
-#define LEDC_TIMER_SEL_HSCH4  0x00000003
-#define LEDC_TIMER_SEL_HSCH4_M  ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S))
-#define LEDC_TIMER_SEL_HSCH4_V  0x3
-#define LEDC_TIMER_SEL_HSCH4_S  0
-
-#define LEDC_HSCH4_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0054)
-/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when htimerx(x=[0 3]) selected
- by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/
-#define LEDC_HPOINT_HSCH4  0x000FFFFF
-#define LEDC_HPOINT_HSCH4_M  ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S))
-#define LEDC_HPOINT_HSCH4_V  0xFFFFF
-#define LEDC_HPOINT_HSCH4_S  0
-
-#define LEDC_HSCH4_DUTY_REG          (DR_REG_LEDC_BASE + 0x0058)
-/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When hstimerx(x=[0
- 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4])          (1)  reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_HSCH4  0x01FFFFFF
-#define LEDC_DUTY_HSCH4_M  ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))
-#define LEDC_DUTY_HSCH4_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH4_S  0
-
-#define LEDC_HSCH4_CONF1_REG          (DR_REG_LEDC_BASE + 0x005C)
-/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_HSCH4  (BIT(31))
-#define LEDC_DUTY_START_HSCH4_M  (BIT(31))
-#define LEDC_DUTY_START_HSCH4_V  0x1
-#define LEDC_DUTY_START_HSCH4_S  31
-/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for high speed channel4.*/
-#define LEDC_DUTY_INC_HSCH4  (BIT(30))
-#define LEDC_DUTY_INC_HSCH4_M  (BIT(30))
-#define LEDC_DUTY_INC_HSCH4_V  0x1
-#define LEDC_DUTY_INC_HSCH4_S  30
-/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for high speed channel1.*/
-#define LEDC_DUTY_NUM_HSCH4  0x000003FF
-#define LEDC_DUTY_NUM_HSCH4_M  ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S))
-#define LEDC_DUTY_NUM_HSCH4_V  0x3FF
-#define LEDC_DUTY_NUM_HSCH4_S  20
-/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_hsch4 cycles for high speed channel4.*/
-#define LEDC_DUTY_CYCLE_HSCH4  0x000003FF
-#define LEDC_DUTY_CYCLE_HSCH4_M  ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S))
-#define LEDC_DUTY_CYCLE_HSCH4_V  0x3FF
-#define LEDC_DUTY_CYCLE_HSCH4_S  10
-/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- high speed channel4.*/
-#define LEDC_DUTY_SCALE_HSCH4  0x000003FF
-#define LEDC_DUTY_SCALE_HSCH4_M  ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S))
-#define LEDC_DUTY_SCALE_HSCH4_V  0x3FF
-#define LEDC_DUTY_SCALE_HSCH4_S  0
-
-#define LEDC_HSCH4_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0060)
-/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for high speed channel4.*/
-#define LEDC_DUTY_HSCH4  0x01FFFFFF
-#define LEDC_DUTY_HSCH4_M  ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))
-#define LEDC_DUTY_HSCH4_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH4_S  0
-
-#define LEDC_HSCH5_CONF0_REG          (DR_REG_LEDC_BASE + 0x0064)
-/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when high speed channel5 is off.*/
-#define LEDC_IDLE_LV_HSCH5  (BIT(3))
-#define LEDC_IDLE_LV_HSCH5_M  (BIT(3))
-#define LEDC_IDLE_LV_HSCH5_V  0x1
-#define LEDC_IDLE_LV_HSCH5_S  3
-/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for high speed channel5.*/
-#define LEDC_SIG_OUT_EN_HSCH5  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH5_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH5_V  0x1
-#define LEDC_SIG_OUT_EN_HSCH5_S  2
-/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four high speed timers  the two bits are used to select
- one of them for high speed channel5.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
-#define LEDC_TIMER_SEL_HSCH5  0x00000003
-#define LEDC_TIMER_SEL_HSCH5_M  ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S))
-#define LEDC_TIMER_SEL_HSCH5_V  0x3
-#define LEDC_TIMER_SEL_HSCH5_S  0
-
-#define LEDC_HSCH5_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0068)
-/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when htimerx(x=[0 3]) selected
- by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/
-#define LEDC_HPOINT_HSCH5  0x000FFFFF
-#define LEDC_HPOINT_HSCH5_M  ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S))
-#define LEDC_HPOINT_HSCH5_V  0xFFFFF
-#define LEDC_HPOINT_HSCH5_S  0
-
-#define LEDC_HSCH5_DUTY_REG          (DR_REG_LEDC_BASE + 0x006C)
-/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When hstimerx(x=[0
- 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4])          (1)  reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_HSCH5  0x01FFFFFF
-#define LEDC_DUTY_HSCH5_M  ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))
-#define LEDC_DUTY_HSCH5_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH5_S  0
-
-#define LEDC_HSCH5_CONF1_REG          (DR_REG_LEDC_BASE + 0x0070)
-/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5
- has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_HSCH5  (BIT(31))
-#define LEDC_DUTY_START_HSCH5_M  (BIT(31))
-#define LEDC_DUTY_START_HSCH5_V  0x1
-#define LEDC_DUTY_START_HSCH5_S  31
-/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for high speed channel5.*/
-#define LEDC_DUTY_INC_HSCH5  (BIT(30))
-#define LEDC_DUTY_INC_HSCH5_M  (BIT(30))
-#define LEDC_DUTY_INC_HSCH5_V  0x1
-#define LEDC_DUTY_INC_HSCH5_S  30
-/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for high speed channel5.*/
-#define LEDC_DUTY_NUM_HSCH5  0x000003FF
-#define LEDC_DUTY_NUM_HSCH5_M  ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S))
-#define LEDC_DUTY_NUM_HSCH5_V  0x3FF
-#define LEDC_DUTY_NUM_HSCH5_S  20
-/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_hsch5 cycles for high speed channel5.*/
-#define LEDC_DUTY_CYCLE_HSCH5  0x000003FF
-#define LEDC_DUTY_CYCLE_HSCH5_M  ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S))
-#define LEDC_DUTY_CYCLE_HSCH5_V  0x3FF
-#define LEDC_DUTY_CYCLE_HSCH5_S  10
-/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- high speed channel5.*/
-#define LEDC_DUTY_SCALE_HSCH5  0x000003FF
-#define LEDC_DUTY_SCALE_HSCH5_M  ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S))
-#define LEDC_DUTY_SCALE_HSCH5_V  0x3FF
-#define LEDC_DUTY_SCALE_HSCH5_S  0
-
-#define LEDC_HSCH5_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0074)
-/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for high speed channel5.*/
-#define LEDC_DUTY_HSCH5  0x01FFFFFF
-#define LEDC_DUTY_HSCH5_M  ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))
-#define LEDC_DUTY_HSCH5_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH5_S  0
-
-#define LEDC_HSCH6_CONF0_REG          (DR_REG_LEDC_BASE + 0x0078)
-/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when high speed channel6 is off.*/
-#define LEDC_IDLE_LV_HSCH6  (BIT(3))
-#define LEDC_IDLE_LV_HSCH6_M  (BIT(3))
-#define LEDC_IDLE_LV_HSCH6_V  0x1
-#define LEDC_IDLE_LV_HSCH6_S  3
-/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for high speed channel6*/
-#define LEDC_SIG_OUT_EN_HSCH6  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH6_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH6_V  0x1
-#define LEDC_SIG_OUT_EN_HSCH6_S  2
-/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four high speed timers  the two bits are used to select
- one of them for high speed channel6.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
-#define LEDC_TIMER_SEL_HSCH6  0x00000003
-#define LEDC_TIMER_SEL_HSCH6_M  ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S))
-#define LEDC_TIMER_SEL_HSCH6_V  0x3
-#define LEDC_TIMER_SEL_HSCH6_S  0
-
-#define LEDC_HSCH6_HPOINT_REG          (DR_REG_LEDC_BASE + 0x007C)
-/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when htimerx(x=[0 3]) selected
- by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/
-#define LEDC_HPOINT_HSCH6  0x000FFFFF
-#define LEDC_HPOINT_HSCH6_M  ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S))
-#define LEDC_HPOINT_HSCH6_V  0xFFFFF
-#define LEDC_HPOINT_HSCH6_S  0
-
-#define LEDC_HSCH6_DUTY_REG          (DR_REG_LEDC_BASE + 0x0080)
-/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When hstimerx(x=[0
- 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4])          (1)  reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_HSCH6  0x01FFFFFF
-#define LEDC_DUTY_HSCH6_M  ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))
-#define LEDC_DUTY_HSCH6_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH6_S  0
-
-#define LEDC_HSCH6_CONF1_REG          (DR_REG_LEDC_BASE + 0x0084)
-/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_HSCH6  (BIT(31))
-#define LEDC_DUTY_START_HSCH6_M  (BIT(31))
-#define LEDC_DUTY_START_HSCH6_V  0x1
-#define LEDC_DUTY_START_HSCH6_S  31
-/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for high speed channel6.*/
-#define LEDC_DUTY_INC_HSCH6  (BIT(30))
-#define LEDC_DUTY_INC_HSCH6_M  (BIT(30))
-#define LEDC_DUTY_INC_HSCH6_V  0x1
-#define LEDC_DUTY_INC_HSCH6_S  30
-/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for high speed channel6.*/
-#define LEDC_DUTY_NUM_HSCH6  0x000003FF
-#define LEDC_DUTY_NUM_HSCH6_M  ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S))
-#define LEDC_DUTY_NUM_HSCH6_V  0x3FF
-#define LEDC_DUTY_NUM_HSCH6_S  20
-/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_hsch6 cycles for high speed channel6.*/
-#define LEDC_DUTY_CYCLE_HSCH6  0x000003FF
-#define LEDC_DUTY_CYCLE_HSCH6_M  ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S))
-#define LEDC_DUTY_CYCLE_HSCH6_V  0x3FF
-#define LEDC_DUTY_CYCLE_HSCH6_S  10
-/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- high speed channel6.*/
-#define LEDC_DUTY_SCALE_HSCH6  0x000003FF
-#define LEDC_DUTY_SCALE_HSCH6_M  ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S))
-#define LEDC_DUTY_SCALE_HSCH6_V  0x3FF
-#define LEDC_DUTY_SCALE_HSCH6_S  0
-
-#define LEDC_HSCH6_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0088)
-/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for high speed channel6.*/
-#define LEDC_DUTY_HSCH6  0x01FFFFFF
-#define LEDC_DUTY_HSCH6_M  ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))
-#define LEDC_DUTY_HSCH6_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH6_S  0
-
-#define LEDC_HSCH7_CONF0_REG          (DR_REG_LEDC_BASE + 0x008C)
-/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when high speed channel7 is off.*/
-#define LEDC_IDLE_LV_HSCH7  (BIT(3))
-#define LEDC_IDLE_LV_HSCH7_M  (BIT(3))
-#define LEDC_IDLE_LV_HSCH7_V  0x1
-#define LEDC_IDLE_LV_HSCH7_S  3
-/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for high speed channel7.*/
-#define LEDC_SIG_OUT_EN_HSCH7  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH7_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_HSCH7_V  0x1
-#define LEDC_SIG_OUT_EN_HSCH7_S  2
-/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four high speed timers  the two bits are used to select
- one of them for high speed channel7.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
-#define LEDC_TIMER_SEL_HSCH7  0x00000003
-#define LEDC_TIMER_SEL_HSCH7_M  ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S))
-#define LEDC_TIMER_SEL_HSCH7_V  0x3
-#define LEDC_TIMER_SEL_HSCH7_S  0
-
-#define LEDC_HSCH7_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0090)
-/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when htimerx(x=[0 3]) selected
- by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/
-#define LEDC_HPOINT_HSCH7  0x000FFFFF
-#define LEDC_HPOINT_HSCH7_M  ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S))
-#define LEDC_HPOINT_HSCH7_V  0xFFFFF
-#define LEDC_HPOINT_HSCH7_S  0
-
-#define LEDC_HSCH7_DUTY_REG          (DR_REG_LEDC_BASE + 0x0094)
-/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When hstimerx(x=[0
- 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4])          (1)  reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_HSCH7  0x01FFFFFF
-#define LEDC_DUTY_HSCH7_M  ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))
-#define LEDC_DUTY_HSCH7_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH7_S  0
-
-#define LEDC_HSCH7_CONF1_REG          (DR_REG_LEDC_BASE + 0x0098)
-/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_HSCH7  (BIT(31))
-#define LEDC_DUTY_START_HSCH7_M  (BIT(31))
-#define LEDC_DUTY_START_HSCH7_V  0x1
-#define LEDC_DUTY_START_HSCH7_S  31
-/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for high speed channel6.*/
-#define LEDC_DUTY_INC_HSCH7  (BIT(30))
-#define LEDC_DUTY_INC_HSCH7_M  (BIT(30))
-#define LEDC_DUTY_INC_HSCH7_V  0x1
-#define LEDC_DUTY_INC_HSCH7_S  30
-/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for high speed channel6.*/
-#define LEDC_DUTY_NUM_HSCH7  0x000003FF
-#define LEDC_DUTY_NUM_HSCH7_M  ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S))
-#define LEDC_DUTY_NUM_HSCH7_V  0x3FF
-#define LEDC_DUTY_NUM_HSCH7_S  20
-/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_hsch7 cycles for high speed channel7.*/
-#define LEDC_DUTY_CYCLE_HSCH7  0x000003FF
-#define LEDC_DUTY_CYCLE_HSCH7_M  ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S))
-#define LEDC_DUTY_CYCLE_HSCH7_V  0x3FF
-#define LEDC_DUTY_CYCLE_HSCH7_S  10
-/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- high speed channel7.*/
-#define LEDC_DUTY_SCALE_HSCH7  0x000003FF
-#define LEDC_DUTY_SCALE_HSCH7_M  ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S))
-#define LEDC_DUTY_SCALE_HSCH7_V  0x3FF
-#define LEDC_DUTY_SCALE_HSCH7_S  0
-
-#define LEDC_HSCH7_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x009C)
-/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for high speed channel7.*/
-#define LEDC_DUTY_HSCH7  0x01FFFFFF
-#define LEDC_DUTY_HSCH7_M  ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))
-#define LEDC_DUTY_HSCH7_V  0x1FFFFFF
-#define LEDC_DUTY_HSCH7_S  0
-
-#define LEDC_LSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x00A0)
-/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY
- for low speed channel0.*/
-#define LEDC_PARA_UP_LSCH0  (BIT(4))
-#define LEDC_PARA_UP_LSCH0_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH0_V  0x1
-#define LEDC_PARA_UP_LSCH0_S  4
-/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when low speed channel0 is off.*/
-#define LEDC_IDLE_LV_LSCH0  (BIT(3))
-#define LEDC_IDLE_LV_LSCH0_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH0_V  0x1
-#define LEDC_IDLE_LV_LSCH0_S  3
-/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for low speed channel0.*/
-#define LEDC_SIG_OUT_EN_LSCH0  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH0_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH0_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH0_S  2
-/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four low speed timers  the two bits are used to select
- one of them for low speed channel0.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
-#define LEDC_TIMER_SEL_LSCH0  0x00000003
-#define LEDC_TIMER_SEL_LSCH0_M  ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))
-#define LEDC_TIMER_SEL_LSCH0_V  0x3
-#define LEDC_TIMER_SEL_LSCH0_S  0
-
-#define LEDC_LSCH0_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00A4)
-/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected
- by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/
-#define LEDC_HPOINT_LSCH0  0x000FFFFF
-#define LEDC_HPOINT_LSCH0_M  ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))
-#define LEDC_HPOINT_LSCH0_V  0xFFFFF
-#define LEDC_HPOINT_LSCH0_S  0
-
-#define LEDC_LSCH0_DUTY_REG          (DR_REG_LEDC_BASE + 0x00A8)
-/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When lstimerx(x=[0
- 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4])          (1)  reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_LSCH0  0x01FFFFFF
-#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
-#define LEDC_DUTY_LSCH0_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH0_S  0
-
-#define LEDC_LSCH0_CONF1_REG          (DR_REG_LEDC_BASE + 0x00AC)
-/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_LSCH0  (BIT(31))
-#define LEDC_DUTY_START_LSCH0_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH0_V  0x1
-#define LEDC_DUTY_START_LSCH0_S  31
-/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for low speed channel6.*/
-#define LEDC_DUTY_INC_LSCH0  (BIT(30))
-#define LEDC_DUTY_INC_LSCH0_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH0_V  0x1
-#define LEDC_DUTY_INC_LSCH0_S  30
-/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for low speed channel6.*/
-#define LEDC_DUTY_NUM_LSCH0  0x000003FF
-#define LEDC_DUTY_NUM_LSCH0_M  ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))
-#define LEDC_DUTY_NUM_LSCH0_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH0_S  20
-/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_lsch0 cycles for low speed channel0.*/
-#define LEDC_DUTY_CYCLE_LSCH0  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH0_M  ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))
-#define LEDC_DUTY_CYCLE_LSCH0_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH0_S  10
-/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- low speed channel0.*/
-#define LEDC_DUTY_SCALE_LSCH0  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH0_M  ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
-#define LEDC_DUTY_SCALE_LSCH0_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH0_S  0
-
-#define LEDC_LSCH0_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x00B0)
-/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for low speed channel0.*/
-#define LEDC_DUTY_LSCH0  0x01FFFFFF
-#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
-#define LEDC_DUTY_LSCH0_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH0_S  0
-
-#define LEDC_LSCH1_CONF0_REG          (DR_REG_LEDC_BASE + 0x00B4)
-/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY
- for low speed channel1.*/
-#define LEDC_PARA_UP_LSCH1  (BIT(4))
-#define LEDC_PARA_UP_LSCH1_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH1_V  0x1
-#define LEDC_PARA_UP_LSCH1_S  4
-/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when low speed channel1 is off.*/
-#define LEDC_IDLE_LV_LSCH1  (BIT(3))
-#define LEDC_IDLE_LV_LSCH1_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH1_V  0x1
-#define LEDC_IDLE_LV_LSCH1_S  3
-/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for low speed channel1.*/
-#define LEDC_SIG_OUT_EN_LSCH1  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH1_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH1_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH1_S  2
-/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four low speed timers  the two bits are used to select
- one of them for low speed channel1.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
-#define LEDC_TIMER_SEL_LSCH1  0x00000003
-#define LEDC_TIMER_SEL_LSCH1_M  ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))
-#define LEDC_TIMER_SEL_LSCH1_V  0x3
-#define LEDC_TIMER_SEL_LSCH1_S  0
-
-#define LEDC_LSCH1_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00B8)
-/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected
- by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/
-#define LEDC_HPOINT_LSCH1  0x000FFFFF
-#define LEDC_HPOINT_LSCH1_M  ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))
-#define LEDC_HPOINT_LSCH1_V  0xFFFFF
-#define LEDC_HPOINT_LSCH1_S  0
-
-#define LEDC_LSCH1_DUTY_REG          (DR_REG_LEDC_BASE + 0x00BC)
-/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When lstimerx(x=[0
- 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4])          (1)  reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_LSCH1  0x01FFFFFF
-#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
-#define LEDC_DUTY_LSCH1_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH1_S  0
-
-#define LEDC_LSCH1_CONF1_REG          (DR_REG_LEDC_BASE + 0x00C0)
-/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
- has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_LSCH1  (BIT(31))
-#define LEDC_DUTY_START_LSCH1_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH1_V  0x1
-#define LEDC_DUTY_START_LSCH1_S  31
-/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for low speed channel1.*/
-#define LEDC_DUTY_INC_LSCH1  (BIT(30))
-#define LEDC_DUTY_INC_LSCH1_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH1_V  0x1
-#define LEDC_DUTY_INC_LSCH1_S  30
-/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for low speed channel1.*/
-#define LEDC_DUTY_NUM_LSCH1  0x000003FF
-#define LEDC_DUTY_NUM_LSCH1_M  ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))
-#define LEDC_DUTY_NUM_LSCH1_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH1_S  20
-/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_lsch1 cycles for low speed channel1.*/
-#define LEDC_DUTY_CYCLE_LSCH1  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH1_M  ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))
-#define LEDC_DUTY_CYCLE_LSCH1_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH1_S  10
-/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- low speed channel1.*/
-#define LEDC_DUTY_SCALE_LSCH1  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH1_M  ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
-#define LEDC_DUTY_SCALE_LSCH1_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH1_S  0
-
-#define LEDC_LSCH1_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x00C4)
-/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for low speed channel1.*/
-#define LEDC_DUTY_LSCH1  0x01FFFFFF
-#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
-#define LEDC_DUTY_LSCH1_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH1_S  0
-
-#define LEDC_LSCH2_CONF0_REG          (DR_REG_LEDC_BASE + 0x00C8)
-/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY
- for low speed channel2.*/
-#define LEDC_PARA_UP_LSCH2  (BIT(4))
-#define LEDC_PARA_UP_LSCH2_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH2_V  0x1
-#define LEDC_PARA_UP_LSCH2_S  4
-/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when low speed channel2 is off.*/
-#define LEDC_IDLE_LV_LSCH2  (BIT(3))
-#define LEDC_IDLE_LV_LSCH2_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH2_V  0x1
-#define LEDC_IDLE_LV_LSCH2_S  3
-/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for low speed channel2.*/
-#define LEDC_SIG_OUT_EN_LSCH2  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH2_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH2_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH2_S  2
-/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four low speed timers  the two bits are used to select
- one of them for low speed channel2.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
-#define LEDC_TIMER_SEL_LSCH2  0x00000003
-#define LEDC_TIMER_SEL_LSCH2_M  ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))
-#define LEDC_TIMER_SEL_LSCH2_V  0x3
-#define LEDC_TIMER_SEL_LSCH2_S  0
-
-#define LEDC_LSCH2_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00CC)
-/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected
- by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/
-#define LEDC_HPOINT_LSCH2  0x000FFFFF
-#define LEDC_HPOINT_LSCH2_M  ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))
-#define LEDC_HPOINT_LSCH2_V  0xFFFFF
-#define LEDC_HPOINT_LSCH2_S  0
-
-#define LEDC_LSCH2_DUTY_REG          (DR_REG_LEDC_BASE + 0x00D0)
-/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When lstimerx(x=[0
- 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4])          (1)  reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_LSCH2  0x01FFFFFF
-#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
-#define LEDC_DUTY_LSCH2_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH2_S  0
-
-#define LEDC_LSCH2_CONF1_REG          (DR_REG_LEDC_BASE + 0x00D4)
-/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2
- has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_LSCH2  (BIT(31))
-#define LEDC_DUTY_START_LSCH2_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH2_V  0x1
-#define LEDC_DUTY_START_LSCH2_S  31
-/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for low speed channel2.*/
-#define LEDC_DUTY_INC_LSCH2  (BIT(30))
-#define LEDC_DUTY_INC_LSCH2_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH2_V  0x1
-#define LEDC_DUTY_INC_LSCH2_S  30
-/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for low speed channel2.*/
-#define LEDC_DUTY_NUM_LSCH2  0x000003FF
-#define LEDC_DUTY_NUM_LSCH2_M  ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))
-#define LEDC_DUTY_NUM_LSCH2_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH2_S  20
-/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_lsch2 cycles for low speed channel2.*/
-#define LEDC_DUTY_CYCLE_LSCH2  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH2_M  ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))
-#define LEDC_DUTY_CYCLE_LSCH2_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH2_S  10
-/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- low speed channel2.*/
-#define LEDC_DUTY_SCALE_LSCH2  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH2_M  ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
-#define LEDC_DUTY_SCALE_LSCH2_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH2_S  0
-
-#define LEDC_LSCH2_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x00D8)
-/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for low speed channel2.*/
-#define LEDC_DUTY_LSCH2  0x01FFFFFF
-#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
-#define LEDC_DUTY_LSCH2_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH2_S  0
-
-#define LEDC_LSCH3_CONF0_REG          (DR_REG_LEDC_BASE + 0x00DC)
-/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY
- for low speed channel3.*/
-#define LEDC_PARA_UP_LSCH3  (BIT(4))
-#define LEDC_PARA_UP_LSCH3_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH3_V  0x1
-#define LEDC_PARA_UP_LSCH3_S  4
-/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when low speed channel3 is off.*/
-#define LEDC_IDLE_LV_LSCH3  (BIT(3))
-#define LEDC_IDLE_LV_LSCH3_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH3_V  0x1
-#define LEDC_IDLE_LV_LSCH3_S  3
-/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for low speed channel3.*/
-#define LEDC_SIG_OUT_EN_LSCH3  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH3_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH3_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH3_S  2
-/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four low speed timers  the two bits are used to select
- one of them for low speed channel3.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
-#define LEDC_TIMER_SEL_LSCH3  0x00000003
-#define LEDC_TIMER_SEL_LSCH3_M  ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))
-#define LEDC_TIMER_SEL_LSCH3_V  0x3
-#define LEDC_TIMER_SEL_LSCH3_S  0
-
-#define LEDC_LSCH3_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00E0)
-/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected
- by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/
-#define LEDC_HPOINT_LSCH3  0x000FFFFF
-#define LEDC_HPOINT_LSCH3_M  ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))
-#define LEDC_HPOINT_LSCH3_V  0xFFFFF
-#define LEDC_HPOINT_LSCH3_S  0
-
-#define LEDC_LSCH3_DUTY_REG          (DR_REG_LEDC_BASE + 0x00E4)
-/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When lstimerx(x=[0
- 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4])          (1)  reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_LSCH3  0x01FFFFFF
-#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
-#define LEDC_DUTY_LSCH3_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH3_S  0
-
-#define LEDC_LSCH3_CONF1_REG          (DR_REG_LEDC_BASE + 0x00E8)
-/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3
- has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_LSCH3  (BIT(31))
-#define LEDC_DUTY_START_LSCH3_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH3_V  0x1
-#define LEDC_DUTY_START_LSCH3_S  31
-/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for low speed channel3.*/
-#define LEDC_DUTY_INC_LSCH3  (BIT(30))
-#define LEDC_DUTY_INC_LSCH3_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH3_V  0x1
-#define LEDC_DUTY_INC_LSCH3_S  30
-/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for low speed channel3.*/
-#define LEDC_DUTY_NUM_LSCH3  0x000003FF
-#define LEDC_DUTY_NUM_LSCH3_M  ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))
-#define LEDC_DUTY_NUM_LSCH3_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH3_S  20
-/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_lsch3 cycles for low speed channel3.*/
-#define LEDC_DUTY_CYCLE_LSCH3  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH3_M  ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))
-#define LEDC_DUTY_CYCLE_LSCH3_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH3_S  10
-/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- low speed channel3.*/
-#define LEDC_DUTY_SCALE_LSCH3  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH3_M  ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
-#define LEDC_DUTY_SCALE_LSCH3_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH3_S  0
-
-#define LEDC_LSCH3_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x00EC)
-/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for low speed channel3.*/
-#define LEDC_DUTY_LSCH3  0x01FFFFFF
-#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
-#define LEDC_DUTY_LSCH3_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH3_S  0
-
-#define LEDC_LSCH4_CONF0_REG          (DR_REG_LEDC_BASE + 0x00F0)
-/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY
- for low speed channel4.*/
-#define LEDC_PARA_UP_LSCH4  (BIT(4))
-#define LEDC_PARA_UP_LSCH4_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH4_V  0x1
-#define LEDC_PARA_UP_LSCH4_S  4
-/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when low speed channel4 is off.*/
-#define LEDC_IDLE_LV_LSCH4  (BIT(3))
-#define LEDC_IDLE_LV_LSCH4_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH4_V  0x1
-#define LEDC_IDLE_LV_LSCH4_S  3
-/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for low speed channel4.*/
-#define LEDC_SIG_OUT_EN_LSCH4  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH4_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH4_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH4_S  2
-/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four low speed timers  the two bits are used to select
- one of them for low speed channel4.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
-#define LEDC_TIMER_SEL_LSCH4  0x00000003
-#define LEDC_TIMER_SEL_LSCH4_M  ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))
-#define LEDC_TIMER_SEL_LSCH4_V  0x3
-#define LEDC_TIMER_SEL_LSCH4_S  0
-
-#define LEDC_LSCH4_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00F4)
-/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected
- by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/
-#define LEDC_HPOINT_LSCH4  0x000FFFFF
-#define LEDC_HPOINT_LSCH4_M  ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))
-#define LEDC_HPOINT_LSCH4_V  0xFFFFF
-#define LEDC_HPOINT_LSCH4_S  0
-
-#define LEDC_LSCH4_DUTY_REG          (DR_REG_LEDC_BASE + 0x00F8)
-/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When lstimerx(x=[0
- 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4])          (1)  reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_LSCH4  0x01FFFFFF
-#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
-#define LEDC_DUTY_LSCH4_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH4_S  0
-
-#define LEDC_LSCH4_CONF1_REG          (DR_REG_LEDC_BASE + 0x00FC)
-/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch4  reg_duty_cycle_hsch4 and reg_duty_scale_hsch4
- has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_LSCH4  (BIT(31))
-#define LEDC_DUTY_START_LSCH4_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH4_V  0x1
-#define LEDC_DUTY_START_LSCH4_S  31
-/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for low speed channel4.*/
-#define LEDC_DUTY_INC_LSCH4  (BIT(30))
-#define LEDC_DUTY_INC_LSCH4_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH4_V  0x1
-#define LEDC_DUTY_INC_LSCH4_S  30
-/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for low speed channel4.*/
-#define LEDC_DUTY_NUM_LSCH4  0x000003FF
-#define LEDC_DUTY_NUM_LSCH4_M  ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))
-#define LEDC_DUTY_NUM_LSCH4_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH4_S  20
-/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_lsch4 cycles for low speed channel4.*/
-#define LEDC_DUTY_CYCLE_LSCH4  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH4_M  ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))
-#define LEDC_DUTY_CYCLE_LSCH4_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH4_S  10
-/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- low speed channel4.*/
-#define LEDC_DUTY_SCALE_LSCH4  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH4_M  ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
-#define LEDC_DUTY_SCALE_LSCH4_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH4_S  0
-
-#define LEDC_LSCH4_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0100)
-/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for low speed channel4.*/
-#define LEDC_DUTY_LSCH4  0x01FFFFFF
-#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
-#define LEDC_DUTY_LSCH4_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH4_S  0
-
-#define LEDC_LSCH5_CONF0_REG          (DR_REG_LEDC_BASE + 0x0104)
-/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY
- for low speed channel5.*/
-#define LEDC_PARA_UP_LSCH5  (BIT(4))
-#define LEDC_PARA_UP_LSCH5_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH5_V  0x1
-#define LEDC_PARA_UP_LSCH5_S  4
-/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when low speed channel5 is off.*/
-#define LEDC_IDLE_LV_LSCH5  (BIT(3))
-#define LEDC_IDLE_LV_LSCH5_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH5_V  0x1
-#define LEDC_IDLE_LV_LSCH5_S  3
-/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for low speed channel5.*/
-#define LEDC_SIG_OUT_EN_LSCH5  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH5_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH5_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH5_S  2
-/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four low speed timers  the two bits are used to select
- one of them for low speed channel5.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
-#define LEDC_TIMER_SEL_LSCH5  0x00000003
-#define LEDC_TIMER_SEL_LSCH5_M  ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))
-#define LEDC_TIMER_SEL_LSCH5_V  0x3
-#define LEDC_TIMER_SEL_LSCH5_S  0
-
-#define LEDC_LSCH5_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0108)
-/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected
- by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/
-#define LEDC_HPOINT_LSCH5  0x000FFFFF
-#define LEDC_HPOINT_LSCH5_M  ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))
-#define LEDC_HPOINT_LSCH5_V  0xFFFFF
-#define LEDC_HPOINT_LSCH5_S  0
-
-#define LEDC_LSCH5_DUTY_REG          (DR_REG_LEDC_BASE + 0x010C)
-/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When lstimerx(x=[0
- 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4])          (1)  reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_LSCH5  0x01FFFFFF
-#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
-#define LEDC_DUTY_LSCH5_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH5_S  0
-
-#define LEDC_LSCH5_CONF1_REG          (DR_REG_LEDC_BASE + 0x0110)
-/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch4  reg_duty_cycle_hsch4 and reg_duty_scale_hsch4
- has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_LSCH5  (BIT(31))
-#define LEDC_DUTY_START_LSCH5_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH5_V  0x1
-#define LEDC_DUTY_START_LSCH5_S  31
-/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for low speed channel5.*/
-#define LEDC_DUTY_INC_LSCH5  (BIT(30))
-#define LEDC_DUTY_INC_LSCH5_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH5_V  0x1
-#define LEDC_DUTY_INC_LSCH5_S  30
-/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for low speed channel5.*/
-#define LEDC_DUTY_NUM_LSCH5  0x000003FF
-#define LEDC_DUTY_NUM_LSCH5_M  ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))
-#define LEDC_DUTY_NUM_LSCH5_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH5_S  20
-/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_lsch5 cycles for low speed channel4.*/
-#define LEDC_DUTY_CYCLE_LSCH5  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH5_M  ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))
-#define LEDC_DUTY_CYCLE_LSCH5_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH5_S  10
-/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- low speed channel5.*/
-#define LEDC_DUTY_SCALE_LSCH5  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH5_M  ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
-#define LEDC_DUTY_SCALE_LSCH5_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH5_S  0
-
-#define LEDC_LSCH5_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0114)
-/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for low speed channel5.*/
-#define LEDC_DUTY_LSCH5  0x01FFFFFF
-#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
-#define LEDC_DUTY_LSCH5_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH5_S  0
-
-#define LEDC_LSCH6_CONF0_REG          (DR_REG_LEDC_BASE + 0x0118)
-/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY
- for low speed channel6.*/
-#define LEDC_PARA_UP_LSCH6  (BIT(4))
-#define LEDC_PARA_UP_LSCH6_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH6_V  0x1
-#define LEDC_PARA_UP_LSCH6_S  4
-/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when low speed channel6 is off.*/
-#define LEDC_IDLE_LV_LSCH6  (BIT(3))
-#define LEDC_IDLE_LV_LSCH6_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH6_V  0x1
-#define LEDC_IDLE_LV_LSCH6_S  3
-/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for low speed channel6.*/
-#define LEDC_SIG_OUT_EN_LSCH6  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH6_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH6_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH6_S  2
-/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four low speed timers  the two bits are used to select
- one of them for low speed channel6.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
-#define LEDC_TIMER_SEL_LSCH6  0x00000003
-#define LEDC_TIMER_SEL_LSCH6_M  ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S))
-#define LEDC_TIMER_SEL_LSCH6_V  0x3
-#define LEDC_TIMER_SEL_LSCH6_S  0
-
-#define LEDC_LSCH6_HPOINT_REG          (DR_REG_LEDC_BASE + 0x011C)
-/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected
- by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/
-#define LEDC_HPOINT_LSCH6  0x000FFFFF
-#define LEDC_HPOINT_LSCH6_M  ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S))
-#define LEDC_HPOINT_LSCH6_V  0xFFFFF
-#define LEDC_HPOINT_LSCH6_S  0
-
-#define LEDC_LSCH6_DUTY_REG          (DR_REG_LEDC_BASE + 0x0120)
-/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When lstimerx(x=[0
- 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4])          (1)  reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_LSCH6  0x01FFFFFF
-#define LEDC_DUTY_LSCH6_M  ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))
-#define LEDC_DUTY_LSCH6_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH6_S  0
-
-#define LEDC_LSCH6_CONF1_REG          (DR_REG_LEDC_BASE + 0x0124)
-/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch6  reg_duty_cycle_hsch6 and reg_duty_scale_hsch6
- has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_LSCH6  (BIT(31))
-#define LEDC_DUTY_START_LSCH6_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH6_V  0x1
-#define LEDC_DUTY_START_LSCH6_S  31
-/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for low speed channel6.*/
-#define LEDC_DUTY_INC_LSCH6  (BIT(30))
-#define LEDC_DUTY_INC_LSCH6_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH6_V  0x1
-#define LEDC_DUTY_INC_LSCH6_S  30
-/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for low speed channel6.*/
-#define LEDC_DUTY_NUM_LSCH6  0x000003FF
-#define LEDC_DUTY_NUM_LSCH6_M  ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S))
-#define LEDC_DUTY_NUM_LSCH6_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH6_S  20
-/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_lsch6 cycles for low speed channel6.*/
-#define LEDC_DUTY_CYCLE_LSCH6  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH6_M  ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S))
-#define LEDC_DUTY_CYCLE_LSCH6_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH6_S  10
-/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- low speed channel6.*/
-#define LEDC_DUTY_SCALE_LSCH6  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH6_M  ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S))
-#define LEDC_DUTY_SCALE_LSCH6_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH6_S  0
-
-#define LEDC_LSCH6_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0128)
-/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for low speed channel6.*/
-#define LEDC_DUTY_LSCH6  0x01FFFFFF
-#define LEDC_DUTY_LSCH6_M  ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))
-#define LEDC_DUTY_LSCH6_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH6_S  0
-
-#define LEDC_LSCH7_CONF0_REG          (DR_REG_LEDC_BASE + 0x012C)
-/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY
- for low speed channel7.*/
-#define LEDC_PARA_UP_LSCH7  (BIT(4))
-#define LEDC_PARA_UP_LSCH7_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH7_V  0x1
-#define LEDC_PARA_UP_LSCH7_S  4
-/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This bit is used to control the output value when low speed channel7 is off.*/
-#define LEDC_IDLE_LV_LSCH7  (BIT(3))
-#define LEDC_IDLE_LV_LSCH7_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH7_V  0x1
-#define LEDC_IDLE_LV_LSCH7_S  3
-/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for low speed channel7.*/
-#define LEDC_SIG_OUT_EN_LSCH7  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH7_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH7_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH7_S  2
-/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: There are four low speed timers  the two bits are used to select
- one of them for low speed channel7.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
-#define LEDC_TIMER_SEL_LSCH7  0x00000003
-#define LEDC_TIMER_SEL_LSCH7_M  ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S))
-#define LEDC_TIMER_SEL_LSCH7_V  0x3
-#define LEDC_TIMER_SEL_LSCH7_S  0
-
-#define LEDC_LSCH7_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0130)
-/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The output value changes to high when lstimerx(x=[0 3]) selected
- by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/
-#define LEDC_HPOINT_LSCH7  0x000FFFFF
-#define LEDC_HPOINT_LSCH7_M  ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S))
-#define LEDC_HPOINT_LSCH7_V  0xFFFFF
-#define LEDC_HPOINT_LSCH7_S  0
-
-#define LEDC_LSCH7_DUTY_REG          (DR_REG_LEDC_BASE + 0x0134)
-/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: The register is used to control output duty. When lstimerx(x=[0
- 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4])          (1)  reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-#define LEDC_DUTY_LSCH7  0x01FFFFFF
-#define LEDC_DUTY_LSCH7_M  ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))
-#define LEDC_DUTY_LSCH7_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH7_S  0
-
-#define LEDC_LSCH7_CONF1_REG          (DR_REG_LEDC_BASE + 0x0138)
-/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When reg_duty_num_hsch4  reg_duty_cycle_hsch4 and reg_duty_scale_hsch4
- has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/
-#define LEDC_DUTY_START_LSCH7  (BIT(31))
-#define LEDC_DUTY_START_LSCH7_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH7_V  0x1
-#define LEDC_DUTY_START_LSCH7_S  31
-/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This register is used to increase the duty of output signal or
- decrease the duty of output signal for low speed channel4.*/
-#define LEDC_DUTY_INC_LSCH7  (BIT(30))
-#define LEDC_DUTY_INC_LSCH7_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH7_V  0x1
-#define LEDC_DUTY_INC_LSCH7_S  30
-/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: This register is used to control the num of increased or decreased
- times for low speed channel4.*/
-#define LEDC_DUTY_NUM_LSCH7  0x000003FF
-#define LEDC_DUTY_NUM_LSCH7_M  ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S))
-#define LEDC_DUTY_NUM_LSCH7_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH7_S  20
-/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: This register is used to increase or decrease the duty every
- reg_duty_cycle_lsch7 cycles for low speed channel7.*/
-#define LEDC_DUTY_CYCLE_LSCH7  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH7_M  ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S))
-#define LEDC_DUTY_CYCLE_LSCH7_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH7_S  10
-/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register controls the increase or decrease step scale for
- low speed channel7.*/
-#define LEDC_DUTY_SCALE_LSCH7  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH7_M  ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S))
-#define LEDC_DUTY_SCALE_LSCH7_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH7_S  0
-
-#define LEDC_LSCH7_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x013C)
-/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
-/*description: This register represents the current duty of the output signal
- for low speed channel7.*/
-#define LEDC_DUTY_LSCH7  0x01FFFFFF
-#define LEDC_DUTY_LSCH7_M  ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))
-#define LEDC_DUTY_LSCH7_V  0x1FFFFFF
-#define LEDC_DUTY_LSCH7_S  0
-
-#define LEDC_HSTIMER0_CONF_REG          (DR_REG_LEDC_BASE + 0x0140)
-/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: This bit is used to choose apb_clk or ref_tick for high speed
- timer0. 1'b1:apb_clk  0:ref_tick*/
-#define LEDC_TICK_SEL_HSTIMER0  (BIT(25))
-#define LEDC_TICK_SEL_HSTIMER0_M  (BIT(25))
-#define LEDC_TICK_SEL_HSTIMER0_V  0x1
-#define LEDC_TICK_SEL_HSTIMER0_S  25
-/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/
-#define LEDC_HSTIMER0_RST  (BIT(24))
-#define LEDC_HSTIMER0_RST_M  (BIT(24))
-#define LEDC_HSTIMER0_RST_V  0x1
-#define LEDC_HSTIMER0_RST_S  24
-/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This bit is used to pause the counter in high speed timer0*/
-#define LEDC_HSTIMER0_PAUSE  (BIT(23))
-#define LEDC_HSTIMER0_PAUSE_M  (BIT(23))
-#define LEDC_HSTIMER0_PAUSE_V  0x1
-#define LEDC_HSTIMER0_PAUSE_S  23
-/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
-/*description: This register is used to configure parameter for divider in high
- speed timer0 the least significant eight bits represent the decimal part.*/
-#define LEDC_DIV_NUM_HSTIMER0  0x0003FFFF
-#define LEDC_DIV_NUM_HSTIMER0_M  ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S))
-#define LEDC_DIV_NUM_HSTIMER0_V  0x3FFFF
-#define LEDC_DIV_NUM_HSTIMER0_S  5
-/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: This register controls the range of the counter in high speed
- timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/
-#define LEDC_HSTIMER0_DUTY_RES  0x0000001F
-#define LEDC_HSTIMER0_DUTY_RES_M  ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S))
-#define LEDC_HSTIMER0_DUTY_RES_V  0x1F
-#define LEDC_HSTIMER0_DUTY_RES_S  0
-// Keep the definitions below to be compatible with previous version
-#define LEDC_HSTIMER0_LIM         LEDC_HSTIMER0_DUTY_RES
-#define LEDC_HSTIMER0_LIM_M       LEDC_HSTIMER0_DUTY_RES_M
-#define LEDC_HSTIMER0_LIM_V       LEDC_HSTIMER0_DUTY_RES_V
-#define LEDC_HSTIMER0_LIM_S       LEDC_HSTIMER0_DUTY_RES_S
-
-#define LEDC_HSTIMER0_VALUE_REG          (DR_REG_LEDC_BASE + 0x0144)
-/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: software can read this register to get the current counter value
- in high speed timer0*/
-#define LEDC_HSTIMER0_CNT  0x000FFFFF
-#define LEDC_HSTIMER0_CNT_M  ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S))
-#define LEDC_HSTIMER0_CNT_V  0xFFFFF
-#define LEDC_HSTIMER0_CNT_S  0
-
-#define LEDC_HSTIMER1_CONF_REG          (DR_REG_LEDC_BASE + 0x0148)
-/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: This bit is used to choose apb_clk or ref_tick for high speed
- timer1. 1'b1:apb_clk  0:ref_tick*/
-#define LEDC_TICK_SEL_HSTIMER1  (BIT(25))
-#define LEDC_TICK_SEL_HSTIMER1_M  (BIT(25))
-#define LEDC_TICK_SEL_HSTIMER1_V  0x1
-#define LEDC_TICK_SEL_HSTIMER1_S  25
-/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/
-#define LEDC_HSTIMER1_RST  (BIT(24))
-#define LEDC_HSTIMER1_RST_M  (BIT(24))
-#define LEDC_HSTIMER1_RST_V  0x1
-#define LEDC_HSTIMER1_RST_S  24
-/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This bit is used to pause the counter in high speed timer1*/
-#define LEDC_HSTIMER1_PAUSE  (BIT(23))
-#define LEDC_HSTIMER1_PAUSE_M  (BIT(23))
-#define LEDC_HSTIMER1_PAUSE_V  0x1
-#define LEDC_HSTIMER1_PAUSE_S  23
-/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
-/*description: This register is used to configure parameter for divider in high
- speed timer1 the least significant eight bits represent the decimal part.*/
-#define LEDC_DIV_NUM_HSTIMER1  0x0003FFFF
-#define LEDC_DIV_NUM_HSTIMER1_M  ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S))
-#define LEDC_DIV_NUM_HSTIMER1_V  0x3FFFF
-#define LEDC_DIV_NUM_HSTIMER1_S  5
-/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: This register controls the range of the counter in high speed
- timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/
-#define LEDC_HSTIMER1_DUTY_RES  0x0000001F
-#define LEDC_HSTIMER1_DUTY_RES_M  ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S))
-#define LEDC_HSTIMER1_DUTY_RES_V  0x1F
-#define LEDC_HSTIMER1_DUTY_RES_S  0
-// Keep the definitions below to be compatible with previous version
-#define LEDC_HSTIMER1_LIM       LEDC_HSTIMER1_DUTY_RES
-#define LEDC_HSTIMER1_LIM_M     LEDC_HSTIMER1_DUTY_RES_M
-#define LEDC_HSTIMER1_LIM_V     LEDC_HSTIMER1_DUTY_RES_V
-#define LEDC_HSTIMER1_LIM_S     LEDC_HSTIMER1_DUTY_RES_S
-
-#define LEDC_HSTIMER1_VALUE_REG          (DR_REG_LEDC_BASE + 0x014C)
-/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: software can read this register to get the current counter value
- in high speed timer1.*/
-#define LEDC_HSTIMER1_CNT  0x000FFFFF
-#define LEDC_HSTIMER1_CNT_M  ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S))
-#define LEDC_HSTIMER1_CNT_V  0xFFFFF
-#define LEDC_HSTIMER1_CNT_S  0
-
-#define LEDC_HSTIMER2_CONF_REG          (DR_REG_LEDC_BASE + 0x0150)
-/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: This bit is used to choose apb_clk or ref_tick for high speed
- timer2. 1'b1:apb_clk  0:ref_tick*/
-#define LEDC_TICK_SEL_HSTIMER2  (BIT(25))
-#define LEDC_TICK_SEL_HSTIMER2_M  (BIT(25))
-#define LEDC_TICK_SEL_HSTIMER2_V  0x1
-#define LEDC_TICK_SEL_HSTIMER2_S  25
-/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/
-#define LEDC_HSTIMER2_RST  (BIT(24))
-#define LEDC_HSTIMER2_RST_M  (BIT(24))
-#define LEDC_HSTIMER2_RST_V  0x1
-#define LEDC_HSTIMER2_RST_S  24
-/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This bit is used to pause the counter in high speed timer2*/
-#define LEDC_HSTIMER2_PAUSE  (BIT(23))
-#define LEDC_HSTIMER2_PAUSE_M  (BIT(23))
-#define LEDC_HSTIMER2_PAUSE_V  0x1
-#define LEDC_HSTIMER2_PAUSE_S  23
-/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
-/*description: This register is used to configure parameter for divider in high
- speed timer2 the least significant eight bits represent the decimal part.*/
-#define LEDC_DIV_NUM_HSTIMER2  0x0003FFFF
-#define LEDC_DIV_NUM_HSTIMER2_M  ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S))
-#define LEDC_DIV_NUM_HSTIMER2_V  0x3FFFF
-#define LEDC_DIV_NUM_HSTIMER2_S  5
-/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: This register controls the range of the counter in high speed
- timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/
-#define LEDC_HSTIMER2_DUTY_RES  0x0000001F
-#define LEDC_HSTIMER2_DUTY_RES_M  ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S))
-#define LEDC_HSTIMER2_DUTY_RES_V  0x1F
-#define LEDC_HSTIMER2_DUTY_RES_S  0
-// Keep the definitions below to be compatible with previous version
-#define LEDC_HSTIMER2_LIM       LEDC_HSTIMER2_DUTY_RES
-#define LEDC_HSTIMER2_LIM_M     LEDC_HSTIMER2_DUTY_RES_M
-#define LEDC_HSTIMER2_LIM_V     LEDC_HSTIMER2_DUTY_RES_V
-#define LEDC_HSTIMER2_LIM_S     LEDC_HSTIMER2_DUTY_RES_S
-
-#define LEDC_HSTIMER2_VALUE_REG          (DR_REG_LEDC_BASE + 0x0154)
-/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: software can read this register to get the current counter value
- in high speed timer2*/
-#define LEDC_HSTIMER2_CNT  0x000FFFFF
-#define LEDC_HSTIMER2_CNT_M  ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S))
-#define LEDC_HSTIMER2_CNT_V  0xFFFFF
-#define LEDC_HSTIMER2_CNT_S  0
-
-#define LEDC_HSTIMER3_CONF_REG          (DR_REG_LEDC_BASE + 0x0158)
-/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: This bit is used to choose apb_clk or ref_tick for high speed
- timer3. 1'b1:apb_clk  0:ref_tick*/
-#define LEDC_TICK_SEL_HSTIMER3  (BIT(25))
-#define LEDC_TICK_SEL_HSTIMER3_M  (BIT(25))
-#define LEDC_TICK_SEL_HSTIMER3_V  0x1
-#define LEDC_TICK_SEL_HSTIMER3_S  25
-/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/
-#define LEDC_HSTIMER3_RST  (BIT(24))
-#define LEDC_HSTIMER3_RST_M  (BIT(24))
-#define LEDC_HSTIMER3_RST_V  0x1
-#define LEDC_HSTIMER3_RST_S  24
-/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This bit is used to pause the counter in high speed timer3*/
-#define LEDC_HSTIMER3_PAUSE  (BIT(23))
-#define LEDC_HSTIMER3_PAUSE_M  (BIT(23))
-#define LEDC_HSTIMER3_PAUSE_V  0x1
-#define LEDC_HSTIMER3_PAUSE_S  23
-/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
-/*description: This register is used to configure parameter for divider in high
- speed timer3 the least significant eight bits represent the decimal part.*/
-#define LEDC_DIV_NUM_HSTIMER3  0x0003FFFF
-#define LEDC_DIV_NUM_HSTIMER3_M  ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S))
-#define LEDC_DIV_NUM_HSTIMER3_V  0x3FFFF
-#define LEDC_DIV_NUM_HSTIMER3_S  5
-/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: This register controls the range of the counter in high speed
- timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/
-#define LEDC_HSTIMER3_DUTY_RES  0x0000001F
-#define LEDC_HSTIMER3_DUTY_RES_M  ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S))
-#define LEDC_HSTIMER3_DUTY_RES_V  0x1F
-#define LEDC_HSTIMER3_DUTY_RES_S  0
-// Keep the definitions below to be compatible with previous version
-#define LEDC_HSTIMER3_LIM       LEDC_HSTIMER3_DUTY_RES
-#define LEDC_HSTIMER3_LIM_M     LEDC_HSTIMER3_DUTY_RES_M
-#define LEDC_HSTIMER3_LIM_V     LEDC_HSTIMER3_DUTY_RES_V
-#define LEDC_HSTIMER3_LIM_S     LEDC_HSTIMER3_DUTY_RES_S
-
-#define LEDC_HSTIMER3_VALUE_REG          (DR_REG_LEDC_BASE + 0x015C)
-/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: software can read this register to get the current counter value
- in high speed timer3*/
-#define LEDC_HSTIMER3_CNT  0x000FFFFF
-#define LEDC_HSTIMER3_CNT_M  ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S))
-#define LEDC_HSTIMER3_CNT_V  0xFFFFF
-#define LEDC_HSTIMER3_CNT_S  0
-
-#define LEDC_LSTIMER0_CONF_REG          (DR_REG_LEDC_BASE + 0x0160)
-/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: Set this bit  to update  reg_div_num_lstime0 and  reg_lstimer0_lim.*/
-#define LEDC_LSTIMER0_PARA_UP  (BIT(26))
-#define LEDC_LSTIMER0_PARA_UP_M  (BIT(26))
-#define LEDC_LSTIMER0_PARA_UP_V  0x1
-#define LEDC_LSTIMER0_PARA_UP_S  26
-/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: This bit is used to choose slow_clk or ref_tick for low speed
- timer0. 1'b1:slow_clk  0:ref_tick*/
-#define LEDC_TICK_SEL_LSTIMER0  (BIT(25))
-#define LEDC_TICK_SEL_LSTIMER0_M  (BIT(25))
-#define LEDC_TICK_SEL_LSTIMER0_V  0x1
-#define LEDC_TICK_SEL_LSTIMER0_S  25
-/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/
-#define LEDC_LSTIMER0_RST  (BIT(24))
-#define LEDC_LSTIMER0_RST_M  (BIT(24))
-#define LEDC_LSTIMER0_RST_V  0x1
-#define LEDC_LSTIMER0_RST_S  24
-/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This bit is used to pause the counter in low speed timer0.*/
-#define LEDC_LSTIMER0_PAUSE  (BIT(23))
-#define LEDC_LSTIMER0_PAUSE_M  (BIT(23))
-#define LEDC_LSTIMER0_PAUSE_V  0x1
-#define LEDC_LSTIMER0_PAUSE_S  23
-/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
-/*description: This register is used to configure parameter for divider in low
- speed timer0 the least significant eight bits represent the decimal part.*/
-#define LEDC_DIV_NUM_LSTIMER0  0x0003FFFF
-#define LEDC_DIV_NUM_LSTIMER0_M  ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S))
-#define LEDC_DIV_NUM_LSTIMER0_V  0x3FFFF
-#define LEDC_DIV_NUM_LSTIMER0_S  5
-/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: This register controls the range of the counter in low speed
- timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/
-#define LEDC_LSTIMER0_DUTY_RES  0x0000001F
-#define LEDC_LSTIMER0_DUTY_RES_M  ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
-#define LEDC_LSTIMER0_DUTY_RES_V  0x1F
-#define LEDC_LSTIMER0_DUTY_RES_S  0
-// Keep the definitions below to be compatible with previous version
-#define LEDC_LSTIMER0_LIM       LEDC_LSTIMER0_DUTY_RES
-#define LEDC_LSTIMER0_LIM_M     LEDC_LSTIMER0_DUTY_RES_M
-#define LEDC_LSTIMER0_LIM_V     LEDC_LSTIMER0_DUTY_RES_V
-#define LEDC_LSTIMER0_LIM_S     LEDC_LSTIMER0_DUTY_RES_S
-
-#define LEDC_LSTIMER0_VALUE_REG          (DR_REG_LEDC_BASE + 0x0164)
-/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: software can read this register to get the current counter value
- in low speed timer0.*/
-#define LEDC_LSTIMER0_CNT  0x000FFFFF
-#define LEDC_LSTIMER0_CNT_M  ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
-#define LEDC_LSTIMER0_CNT_V  0xFFFFF
-#define LEDC_LSTIMER0_CNT_S  0
-
-#define LEDC_LSTIMER1_CONF_REG          (DR_REG_LEDC_BASE + 0x0168)
-/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: Set this bit  to update  reg_div_num_lstime1 and  reg_lstimer1_lim.*/
-#define LEDC_LSTIMER1_PARA_UP  (BIT(26))
-#define LEDC_LSTIMER1_PARA_UP_M  (BIT(26))
-#define LEDC_LSTIMER1_PARA_UP_V  0x1
-#define LEDC_LSTIMER1_PARA_UP_S  26
-/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: This bit is used to choose slow_clk or ref_tick for low speed
- timer1. 1'b1:slow_clk  0:ref_tick*/
-#define LEDC_TICK_SEL_LSTIMER1  (BIT(25))
-#define LEDC_TICK_SEL_LSTIMER1_M  (BIT(25))
-#define LEDC_TICK_SEL_LSTIMER1_V  0x1
-#define LEDC_TICK_SEL_LSTIMER1_S  25
-/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/
-#define LEDC_LSTIMER1_RST  (BIT(24))
-#define LEDC_LSTIMER1_RST_M  (BIT(24))
-#define LEDC_LSTIMER1_RST_V  0x1
-#define LEDC_LSTIMER1_RST_S  24
-/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This bit is used to pause the counter in low speed timer1.*/
-#define LEDC_LSTIMER1_PAUSE  (BIT(23))
-#define LEDC_LSTIMER1_PAUSE_M  (BIT(23))
-#define LEDC_LSTIMER1_PAUSE_V  0x1
-#define LEDC_LSTIMER1_PAUSE_S  23
-/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
-/*description: This register is used to configure parameter for divider in low
- speed timer1 the least significant eight bits represent the decimal part.*/
-#define LEDC_DIV_NUM_LSTIMER1  0x0003FFFF
-#define LEDC_DIV_NUM_LSTIMER1_M  ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S))
-#define LEDC_DIV_NUM_LSTIMER1_V  0x3FFFF
-#define LEDC_DIV_NUM_LSTIMER1_S  5
-/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: This register controls the range of the counter in low speed
- timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/
-#define LEDC_LSTIMER1_DUTY_RES  0x0000001F
-#define LEDC_LSTIMER1_DUTY_RES_M  ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
-#define LEDC_LSTIMER1_DUTY_RES_V  0x1F
-#define LEDC_LSTIMER1_DUTY_RES_S  0
-// Keep the definitions below to be compatible with previous version
-#define LEDC_LSTIMER1_LIM       LEDC_LSTIMER1_DUTY_RES
-#define LEDC_LSTIMER1_LIM_M     LEDC_LSTIMER1_DUTY_RES_M
-#define LEDC_LSTIMER1_LIM_V     LEDC_LSTIMER1_DUTY_RES_V
-#define LEDC_LSTIMER1_LIM_S     LEDC_LSTIMER1_DUTY_RES_S
-
-#define LEDC_LSTIMER1_VALUE_REG          (DR_REG_LEDC_BASE + 0x016C)
-/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: software can read this register to get the current counter value
- in low speed timer1.*/
-#define LEDC_LSTIMER1_CNT  0x000FFFFF
-#define LEDC_LSTIMER1_CNT_M  ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))
-#define LEDC_LSTIMER1_CNT_V  0xFFFFF
-#define LEDC_LSTIMER1_CNT_S  0
-
-#define LEDC_LSTIMER2_CONF_REG          (DR_REG_LEDC_BASE + 0x0170)
-/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: Set this bit  to update  reg_div_num_lstime2 and  reg_lstimer2_lim.*/
-#define LEDC_LSTIMER2_PARA_UP  (BIT(26))
-#define LEDC_LSTIMER2_PARA_UP_M  (BIT(26))
-#define LEDC_LSTIMER2_PARA_UP_V  0x1
-#define LEDC_LSTIMER2_PARA_UP_S  26
-/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: This bit is used to choose slow_clk or ref_tick for low speed
- timer2. 1'b1:slow_clk  0:ref_tick*/
-#define LEDC_TICK_SEL_LSTIMER2  (BIT(25))
-#define LEDC_TICK_SEL_LSTIMER2_M  (BIT(25))
-#define LEDC_TICK_SEL_LSTIMER2_V  0x1
-#define LEDC_TICK_SEL_LSTIMER2_S  25
-/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/
-#define LEDC_LSTIMER2_RST  (BIT(24))
-#define LEDC_LSTIMER2_RST_M  (BIT(24))
-#define LEDC_LSTIMER2_RST_V  0x1
-#define LEDC_LSTIMER2_RST_S  24
-/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This bit is used to pause the counter in low speed timer2.*/
-#define LEDC_LSTIMER2_PAUSE  (BIT(23))
-#define LEDC_LSTIMER2_PAUSE_M  (BIT(23))
-#define LEDC_LSTIMER2_PAUSE_V  0x1
-#define LEDC_LSTIMER2_PAUSE_S  23
-/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
-/*description: This register is used to configure parameter for divider in low
- speed timer2 the least significant eight bits represent the decimal part.*/
-#define LEDC_DIV_NUM_LSTIMER2  0x0003FFFF
-#define LEDC_DIV_NUM_LSTIMER2_M  ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S))
-#define LEDC_DIV_NUM_LSTIMER2_V  0x3FFFF
-#define LEDC_DIV_NUM_LSTIMER2_S  5
-/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: This register controls the range of the counter in low speed
- timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/
-#define LEDC_LSTIMER2_DUTY_RES  0x0000001F
-#define LEDC_LSTIMER2_DUTY_RES_M  ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
-#define LEDC_LSTIMER2_DUTY_RES_V  0x1F
-#define LEDC_LSTIMER2_DUTY_RES_S  0
-// Keep the definitions below to be compatible with previous version
-#define LEDC_LSTIMER2_LIM       LEDC_LSTIMER2_DUTY_RES
-#define LEDC_LSTIMER2_LIM_M     LEDC_LSTIMER2_DUTY_RES_M
-#define LEDC_LSTIMER2_LIM_V     LEDC_LSTIMER2_DUTY_RES_V
-#define LEDC_LSTIMER2_LIM_S     LEDC_LSTIMER2_DUTY_RES_S
-
-#define LEDC_LSTIMER2_VALUE_REG          (DR_REG_LEDC_BASE + 0x0174)
-/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: software can read this register to get the current counter value
- in low speed timer2.*/
-#define LEDC_LSTIMER2_CNT  0x000FFFFF
-#define LEDC_LSTIMER2_CNT_M  ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
-#define LEDC_LSTIMER2_CNT_V  0xFFFFF
-#define LEDC_LSTIMER2_CNT_S  0
-
-#define LEDC_LSTIMER3_CONF_REG          (DR_REG_LEDC_BASE + 0x0178)
-/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
-/*description: Set this bit  to update  reg_div_num_lstime3 and  reg_lstimer3_lim.*/
-#define LEDC_LSTIMER3_PARA_UP  (BIT(26))
-#define LEDC_LSTIMER3_PARA_UP_M  (BIT(26))
-#define LEDC_LSTIMER3_PARA_UP_V  0x1
-#define LEDC_LSTIMER3_PARA_UP_S  26
-/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: This bit is used to choose slow_clk or ref_tick for low speed
- timer3. 1'b1:slow_clk  0:ref_tick*/
-#define LEDC_TICK_SEL_LSTIMER3  (BIT(25))
-#define LEDC_TICK_SEL_LSTIMER3_M  (BIT(25))
-#define LEDC_TICK_SEL_LSTIMER3_V  0x1
-#define LEDC_TICK_SEL_LSTIMER3_S  25
-/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/
-#define LEDC_LSTIMER3_RST  (BIT(24))
-#define LEDC_LSTIMER3_RST_M  (BIT(24))
-#define LEDC_LSTIMER3_RST_V  0x1
-#define LEDC_LSTIMER3_RST_S  24
-/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This bit is used to pause the counter in low speed timer3.*/
-#define LEDC_LSTIMER3_PAUSE  (BIT(23))
-#define LEDC_LSTIMER3_PAUSE_M  (BIT(23))
-#define LEDC_LSTIMER3_PAUSE_V  0x1
-#define LEDC_LSTIMER3_PAUSE_S  23
-/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
-/*description: This register is used to configure parameter for divider in low
- speed timer3 the least significant eight bits represent the decimal part.*/
-#define LEDC_DIV_NUM_LSTIMER3  0x0003FFFF
-#define LEDC_DIV_NUM_LSTIMER3_M  ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S))
-#define LEDC_DIV_NUM_LSTIMER3_V  0x3FFFF
-#define LEDC_DIV_NUM_LSTIMER3_S  5
-/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: This register controls the range of the counter in low speed
- timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/
-#define LEDC_LSTIMER3_DUTY_RES  0x0000001F
-#define LEDC_LSTIMER3_DUTY_RES_M  ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
-#define LEDC_LSTIMER3_DUTY_RES_V  0x1F
-#define LEDC_LSTIMER3_DUTY_RES_S  0
-// Keep the definitions below to be compatible with previous version
-#define LEDC_LSTIMER3_LIM       LEDC_LSTIMER3_DUTY_RES
-#define LEDC_LSTIMER3_LIM_M     LEDC_LSTIMER3_DUTY_RES_M
-#define LEDC_LSTIMER3_LIM_V     LEDC_LSTIMER3_DUTY_RES_V
-#define LEDC_LSTIMER3_LIM_S     LEDC_LSTIMER3_DUTY_RES_S
-
-#define LEDC_LSTIMER3_VALUE_REG          (DR_REG_LEDC_BASE + 0x017C)
-/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: software can read this register to get the current counter value
- in low speed timer3.*/
-#define LEDC_LSTIMER3_CNT  0x000FFFFF
-#define LEDC_LSTIMER3_CNT_M  ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))
-#define LEDC_LSTIMER3_CNT_V  0xFFFFF
-#define LEDC_LSTIMER3_CNT_S  0
-
-#define LEDC_INT_RAW_REG          (DR_REG_LEDC_BASE + 0x0180)
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel 7 duty change done.*/
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW  (BIT(23))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M  (BIT(23))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S  23
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel 6 duty change done.*/
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW  (BIT(22))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M  (BIT(22))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S  22
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel 5 duty change done.*/
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW  (BIT(21))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M  (BIT(21))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S  21
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel 4 duty change done.*/
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW  (BIT(20))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M  (BIT(20))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S  20
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel 3 duty change done.*/
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW  (BIT(19))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M  (BIT(19))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S  19
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel 2 duty change done.*/
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW  (BIT(18))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M  (BIT(18))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S  18
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel 1 duty change done.*/
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW  (BIT(17))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M  (BIT(17))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S  17
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel 0 duty change done.*/
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW  (BIT(16))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M  (BIT(16))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S  16
-/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel 7 duty change done.*/
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW  (BIT(15))
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M  (BIT(15))
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S  15
-/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel 6 duty change done.*/
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW  (BIT(14))
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M  (BIT(14))
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S  14
-/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel 5 duty change done.*/
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW  (BIT(13))
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M  (BIT(13))
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S  13
-/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel 4 duty change done.*/
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW  (BIT(12))
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M  (BIT(12))
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S  12
-/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel 3 duty change done.*/
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW  (BIT(11))
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M  (BIT(11))
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S  11
-/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel 2 duty change done.*/
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW  (BIT(10))
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M  (BIT(10))
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S  10
-/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel 1 duty change done.*/
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW  (BIT(9))
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S  9
-/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel 0 duty change done.*/
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW  (BIT(8))
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S  8
-/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel3  counter overflow.*/
-#define LEDC_LSTIMER3_OVF_INT_RAW  (BIT(7))
-#define LEDC_LSTIMER3_OVF_INT_RAW_M  (BIT(7))
-#define LEDC_LSTIMER3_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_RAW_S  7
-/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel2  counter overflow.*/
-#define LEDC_LSTIMER2_OVF_INT_RAW  (BIT(6))
-#define LEDC_LSTIMER2_OVF_INT_RAW_M  (BIT(6))
-#define LEDC_LSTIMER2_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_RAW_S  6
-/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel1  counter overflow.*/
-#define LEDC_LSTIMER1_OVF_INT_RAW  (BIT(5))
-#define LEDC_LSTIMER1_OVF_INT_RAW_M  (BIT(5))
-#define LEDC_LSTIMER1_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_RAW_S  5
-/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for low speed channel0  counter overflow.*/
-#define LEDC_LSTIMER0_OVF_INT_RAW  (BIT(4))
-#define LEDC_LSTIMER0_OVF_INT_RAW_M  (BIT(4))
-#define LEDC_LSTIMER0_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_RAW_S  4
-/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel3  counter overflow.*/
-#define LEDC_HSTIMER3_OVF_INT_RAW  (BIT(3))
-#define LEDC_HSTIMER3_OVF_INT_RAW_M  (BIT(3))
-#define LEDC_HSTIMER3_OVF_INT_RAW_V  0x1
-#define LEDC_HSTIMER3_OVF_INT_RAW_S  3
-/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel2  counter overflow.*/
-#define LEDC_HSTIMER2_OVF_INT_RAW  (BIT(2))
-#define LEDC_HSTIMER2_OVF_INT_RAW_M  (BIT(2))
-#define LEDC_HSTIMER2_OVF_INT_RAW_V  0x1
-#define LEDC_HSTIMER2_OVF_INT_RAW_S  2
-/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel1  counter overflow.*/
-#define LEDC_HSTIMER1_OVF_INT_RAW  (BIT(1))
-#define LEDC_HSTIMER1_OVF_INT_RAW_M  (BIT(1))
-#define LEDC_HSTIMER1_OVF_INT_RAW_V  0x1
-#define LEDC_HSTIMER1_OVF_INT_RAW_S  1
-/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for high speed channel0  counter overflow.*/
-#define LEDC_HSTIMER0_OVF_INT_RAW  (BIT(0))
-#define LEDC_HSTIMER0_OVF_INT_RAW_M  (BIT(0))
-#define LEDC_HSTIMER0_OVF_INT_RAW_V  0x1
-#define LEDC_HSTIMER0_OVF_INT_RAW_S  0
-
-#define LEDC_INT_ST_REG          (DR_REG_LEDC_BASE + 0x0184)
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */
-/*description: The interrupt status bit for low speed channel 7 duty change done event*/
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST  (BIT(23))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M  (BIT(23))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S  23
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel 6 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST  (BIT(22))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M  (BIT(22))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S  22
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel 5 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST  (BIT(21))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M  (BIT(21))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S  21
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel 4 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST  (BIT(20))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M  (BIT(20))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S  20
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel 3 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST  (BIT(19))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M  (BIT(19))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S  19
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel 2 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST  (BIT(18))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M  (BIT(18))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S  18
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel 1 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST  (BIT(17))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M  (BIT(17))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S  17
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel 0 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST  (BIT(16))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M  (BIT(16))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S  16
-/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel 7 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST  (BIT(15))
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M  (BIT(15))
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S  15
-/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel 6 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST  (BIT(14))
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M  (BIT(14))
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S  14
-/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel 5 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST  (BIT(13))
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M  (BIT(13))
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S  13
-/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel 4 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST  (BIT(12))
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M  (BIT(12))
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S  12
-/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel 3 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST  (BIT(11))
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M  (BIT(11))
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S  11
-/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel 2 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST  (BIT(10))
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M  (BIT(10))
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S  10
-/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel 1 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST  (BIT(9))
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S  9
-/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel 0 duty change done event.*/
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST  (BIT(8))
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S  8
-/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel3  counter overflow event.*/
-#define LEDC_LSTIMER3_OVF_INT_ST  (BIT(7))
-#define LEDC_LSTIMER3_OVF_INT_ST_M  (BIT(7))
-#define LEDC_LSTIMER3_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_ST_S  7
-/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel2  counter overflow event.*/
-#define LEDC_LSTIMER2_OVF_INT_ST  (BIT(6))
-#define LEDC_LSTIMER2_OVF_INT_ST_M  (BIT(6))
-#define LEDC_LSTIMER2_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_ST_S  6
-/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel1  counter overflow event.*/
-#define LEDC_LSTIMER1_OVF_INT_ST  (BIT(5))
-#define LEDC_LSTIMER1_OVF_INT_ST_M  (BIT(5))
-#define LEDC_LSTIMER1_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_ST_S  5
-/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The interrupt status bit for low speed channel0  counter overflow event.*/
-#define LEDC_LSTIMER0_OVF_INT_ST  (BIT(4))
-#define LEDC_LSTIMER0_OVF_INT_ST_M  (BIT(4))
-#define LEDC_LSTIMER0_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_ST_S  4
-/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel3  counter overflow event.*/
-#define LEDC_HSTIMER3_OVF_INT_ST  (BIT(3))
-#define LEDC_HSTIMER3_OVF_INT_ST_M  (BIT(3))
-#define LEDC_HSTIMER3_OVF_INT_ST_V  0x1
-#define LEDC_HSTIMER3_OVF_INT_ST_S  3
-/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel2  counter overflow event.*/
-#define LEDC_HSTIMER2_OVF_INT_ST  (BIT(2))
-#define LEDC_HSTIMER2_OVF_INT_ST_M  (BIT(2))
-#define LEDC_HSTIMER2_OVF_INT_ST_V  0x1
-#define LEDC_HSTIMER2_OVF_INT_ST_S  2
-/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel1  counter overflow event.*/
-#define LEDC_HSTIMER1_OVF_INT_ST  (BIT(1))
-#define LEDC_HSTIMER1_OVF_INT_ST_M  (BIT(1))
-#define LEDC_HSTIMER1_OVF_INT_ST_V  0x1
-#define LEDC_HSTIMER1_OVF_INT_ST_S  1
-/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt status bit for high speed channel0  counter overflow event.*/
-#define LEDC_HSTIMER0_OVF_INT_ST  (BIT(0))
-#define LEDC_HSTIMER0_OVF_INT_ST_M  (BIT(0))
-#define LEDC_HSTIMER0_OVF_INT_ST_V  0x1
-#define LEDC_HSTIMER0_OVF_INT_ST_S  0
-
-#define LEDC_INT_ENA_REG          (DR_REG_LEDC_BASE + 0x0188)
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA  (BIT(23))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M  (BIT(23))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S  23
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA  (BIT(22))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M  (BIT(22))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S  22
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA  (BIT(21))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M  (BIT(21))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S  21
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA  (BIT(20))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M  (BIT(20))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S  20
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA  (BIT(19))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M  (BIT(19))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S  19
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA  (BIT(18))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M  (BIT(18))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S  18
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA  (BIT(17))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M  (BIT(17))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S  17
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA  (BIT(16))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M  (BIT(16))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S  16
-/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA  (BIT(15))
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M  (BIT(15))
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S  15
-/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA  (BIT(14))
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M  (BIT(14))
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S  14
-/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA  (BIT(13))
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M  (BIT(13))
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S  13
-/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA  (BIT(12))
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M  (BIT(12))
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S  12
-/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA  (BIT(11))
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M  (BIT(11))
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S  11
-/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA  (BIT(10))
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M  (BIT(10))
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S  10
-/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA  (BIT(9))
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S  9
-/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA  (BIT(8))
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S  8
-/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel3  counter overflow interrupt.*/
-#define LEDC_LSTIMER3_OVF_INT_ENA  (BIT(7))
-#define LEDC_LSTIMER3_OVF_INT_ENA_M  (BIT(7))
-#define LEDC_LSTIMER3_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_ENA_S  7
-/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel2  counter overflow interrupt.*/
-#define LEDC_LSTIMER2_OVF_INT_ENA  (BIT(6))
-#define LEDC_LSTIMER2_OVF_INT_ENA_M  (BIT(6))
-#define LEDC_LSTIMER2_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_ENA_S  6
-/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel1  counter overflow interrupt.*/
-#define LEDC_LSTIMER1_OVF_INT_ENA  (BIT(5))
-#define LEDC_LSTIMER1_OVF_INT_ENA_M  (BIT(5))
-#define LEDC_LSTIMER1_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_ENA_S  5
-/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for low speed channel0  counter overflow interrupt.*/
-#define LEDC_LSTIMER0_OVF_INT_ENA  (BIT(4))
-#define LEDC_LSTIMER0_OVF_INT_ENA_M  (BIT(4))
-#define LEDC_LSTIMER0_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_ENA_S  4
-/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel3  counter overflow interrupt.*/
-#define LEDC_HSTIMER3_OVF_INT_ENA  (BIT(3))
-#define LEDC_HSTIMER3_OVF_INT_ENA_M  (BIT(3))
-#define LEDC_HSTIMER3_OVF_INT_ENA_V  0x1
-#define LEDC_HSTIMER3_OVF_INT_ENA_S  3
-/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel2  counter overflow interrupt.*/
-#define LEDC_HSTIMER2_OVF_INT_ENA  (BIT(2))
-#define LEDC_HSTIMER2_OVF_INT_ENA_M  (BIT(2))
-#define LEDC_HSTIMER2_OVF_INT_ENA_V  0x1
-#define LEDC_HSTIMER2_OVF_INT_ENA_S  2
-/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel1  counter overflow interrupt.*/
-#define LEDC_HSTIMER1_OVF_INT_ENA  (BIT(1))
-#define LEDC_HSTIMER1_OVF_INT_ENA_M  (BIT(1))
-#define LEDC_HSTIMER1_OVF_INT_ENA_V  0x1
-#define LEDC_HSTIMER1_OVF_INT_ENA_S  1
-/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for high speed channel0  counter overflow interrupt.*/
-#define LEDC_HSTIMER0_OVF_INT_ENA  (BIT(0))
-#define LEDC_HSTIMER0_OVF_INT_ENA_M  (BIT(0))
-#define LEDC_HSTIMER0_OVF_INT_ENA_V  0x1
-#define LEDC_HSTIMER0_OVF_INT_ENA_S  0
-
-#define LEDC_INT_CLR_REG          (DR_REG_LEDC_BASE + 0x018C)
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */
-/*description: Set this  bit to clear  low speed channel 7 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR  (BIT(23))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M  (BIT(23))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S  23
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel 6 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR  (BIT(22))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M  (BIT(22))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S  22
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel 5 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR  (BIT(21))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M  (BIT(21))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S  21
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel 4 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR  (BIT(20))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M  (BIT(20))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S  20
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel 3 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR  (BIT(19))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M  (BIT(19))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S  19
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel 2 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR  (BIT(18))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M  (BIT(18))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S  18
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel 1 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR  (BIT(17))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M  (BIT(17))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S  17
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel 0 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR  (BIT(16))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M  (BIT(16))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S  16
-/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel 7 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR  (BIT(15))
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M  (BIT(15))
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S  15
-/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel 6 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR  (BIT(14))
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M  (BIT(14))
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S  14
-/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel 5 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR  (BIT(13))
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M  (BIT(13))
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S  13
-/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel 4 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR  (BIT(12))
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M  (BIT(12))
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S  12
-/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel 3 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR  (BIT(11))
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M  (BIT(11))
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S  11
-/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel 2 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR  (BIT(10))
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M  (BIT(10))
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S  10
-/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel 1 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR  (BIT(9))
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S  9
-/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel 0 duty change done interrupt.*/
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR  (BIT(8))
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S  8
-/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel3  counter overflow interrupt.*/
-#define LEDC_LSTIMER3_OVF_INT_CLR  (BIT(7))
-#define LEDC_LSTIMER3_OVF_INT_CLR_M  (BIT(7))
-#define LEDC_LSTIMER3_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_CLR_S  7
-/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel2  counter overflow interrupt.*/
-#define LEDC_LSTIMER2_OVF_INT_CLR  (BIT(6))
-#define LEDC_LSTIMER2_OVF_INT_CLR_M  (BIT(6))
-#define LEDC_LSTIMER2_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_CLR_S  6
-/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel1  counter overflow interrupt.*/
-#define LEDC_LSTIMER1_OVF_INT_CLR  (BIT(5))
-#define LEDC_LSTIMER1_OVF_INT_CLR_M  (BIT(5))
-#define LEDC_LSTIMER1_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_CLR_S  5
-/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  low speed channel0  counter overflow interrupt.*/
-#define LEDC_LSTIMER0_OVF_INT_CLR  (BIT(4))
-#define LEDC_LSTIMER0_OVF_INT_CLR_M  (BIT(4))
-#define LEDC_LSTIMER0_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_CLR_S  4
-/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel3  counter overflow interrupt.*/
-#define LEDC_HSTIMER3_OVF_INT_CLR  (BIT(3))
-#define LEDC_HSTIMER3_OVF_INT_CLR_M  (BIT(3))
-#define LEDC_HSTIMER3_OVF_INT_CLR_V  0x1
-#define LEDC_HSTIMER3_OVF_INT_CLR_S  3
-/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel2  counter overflow interrupt.*/
-#define LEDC_HSTIMER2_OVF_INT_CLR  (BIT(2))
-#define LEDC_HSTIMER2_OVF_INT_CLR_M  (BIT(2))
-#define LEDC_HSTIMER2_OVF_INT_CLR_V  0x1
-#define LEDC_HSTIMER2_OVF_INT_CLR_S  2
-/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel1  counter overflow interrupt.*/
-#define LEDC_HSTIMER1_OVF_INT_CLR  (BIT(1))
-#define LEDC_HSTIMER1_OVF_INT_CLR_M  (BIT(1))
-#define LEDC_HSTIMER1_OVF_INT_CLR_V  0x1
-#define LEDC_HSTIMER1_OVF_INT_CLR_S  1
-/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this  bit to clear  high speed channel0  counter overflow interrupt.*/
-#define LEDC_HSTIMER0_OVF_INT_CLR  (BIT(0))
-#define LEDC_HSTIMER0_OVF_INT_CLR_M  (BIT(0))
-#define LEDC_HSTIMER0_OVF_INT_CLR_V  0x1
-#define LEDC_HSTIMER0_OVF_INT_CLR_S  0
-
-#define LEDC_CONF_REG          (DR_REG_LEDC_BASE + 0x0190)
-/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit is used to set the frequency of slow_clk. 1'b1:80mhz  1'b0:8mhz*/
-#define LEDC_APB_CLK_SEL  (BIT(0))
-#define LEDC_APB_CLK_SEL_M  (BIT(0))
-#define LEDC_APB_CLK_SEL_V  0x1
-#define LEDC_APB_CLK_SEL_S  0
-
-#define LEDC_DATE_REG          (DR_REG_LEDC_BASE + 0x01FC)
-/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */
-/*description: This register represents the version .*/
-#define LEDC_DATE  0xFFFFFFFF
-#define LEDC_DATE_M  ((LEDC_DATE_V)<<(LEDC_DATE_S))
-#define LEDC_DATE_V  0xFFFFFFFF
-#define LEDC_DATE_S  0
-
-
-
-
-#endif /*_SOC_LEDC_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/ledc_struct.h b/tools/sdk/include/soc/soc/ledc_struct.h
deleted file mode 100644
index d07e059f209..00000000000
--- a/tools/sdk/include/soc/soc/ledc_struct.h
+++ /dev/null
@@ -1,263 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_LEDC_STRUCT_H_
-#define _SOC_LEDC_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    struct {
-        struct {
-            union {
-                struct {
-                    uint32_t timer_sel:  2;              /*There are four high speed timers  the two bits are used to select one of them for high speed channel.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
-                    uint32_t sig_out_en: 1;              /*This is the output enable control bit for high speed channel*/
-                    uint32_t idle_lv:    1;              /*This bit is used to control the output value when high speed channel is off.*/
-                    uint32_t low_speed_update: 1;        /*This bit is only useful for low speed timer channels, reserved for high speed timers*/
-                    uint32_t reserved4: 26;
-                    uint32_t clk_en:     1;              /*This bit is clock gating control signal. when software configure LED_PWM internal registers  it controls the register clock.*/
-                };
-                uint32_t val;
-            } conf0;
-            union {
-                struct {
-                    uint32_t hpoint:     20;             /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/
-                    uint32_t reserved20: 12;
-                };
-                uint32_t val;
-            } hpoint;
-            union {
-                struct {
-                    uint32_t duty:      25;              /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel  has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4])          (1)  reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
-                    uint32_t reserved25: 7;
-                };
-                uint32_t val;
-            } duty;
-            union {
-                struct {
-                    uint32_t duty_scale:10;              /*This register controls the increase or decrease step scale for high speed channel.*/
-                    uint32_t duty_cycle:10;              /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/
-                    uint32_t duty_num:  10;              /*This register is used to control the number of increased or decreased times for high speed channel.*/
-                    uint32_t duty_inc:   1;              /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/
-                    uint32_t duty_start: 1;              /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
-                };
-                uint32_t val;
-            } conf1;
-            union {
-                struct {
-                    uint32_t duty_read: 25;              /*This register represents the current duty of the output signal for high speed channel.*/
-                    uint32_t reserved25: 7;
-                };
-                uint32_t val;
-            } duty_rd;
-        } channel[8];
-    } channel_group[2];                                /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
-    struct {
-        struct {
-            union {
-                struct {
-                    uint32_t duty_resolution:   5;     /*This register controls resolution of PWN duty by defining the bit width of timer's counter. The max bit width of the counter is 20.*/
-                    uint32_t clock_divider:    18;     /*This register is used to configure the divider of clock at the entry of timer. The least significant eight bits represent the decimal part.*/
-                    uint32_t pause:             1;     /*This bit is used to pause the counter in high speed timer*/
-                    uint32_t rst:               1;     /*This bit is used to reset high speed timer the counter will be 0 after reset.*/
-                    uint32_t tick_sel:          1;     /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk  0:ref_tick*/
-                    uint32_t low_speed_update:  1;     /*This bit is only useful for low speed timer channels, reserved for high speed timers*/
-                    uint32_t reserved26:        5;
-                };
-                struct {
-                    uint32_t bit_num:           5 __attribute__((deprecated));  /*Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1.*/
-                    uint32_t div_num:          18 __attribute__((deprecated));  /*Deprecated in ESP-IDF 3.0. This is an alias to 'clock_divider' for backward compatibility with ESP-IDF 2.1.*/
-                    uint32_t place_holder:      9 __attribute__((deprecated));  /*A place holder to accommodate deprecated members*/
-                };
-                uint32_t val;
-            } conf;
-            union {
-                struct {
-                    uint32_t timer_cnt:  20;               /*software can read this register to get the current counter value in high speed timer*/
-                    uint32_t reserved20: 12;
-                };
-                uint32_t val;
-            } value;
-        } timer[4];
-    } timer_group[2];                                    /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
-    union {
-        struct {
-            uint32_t hstimer0_ovf:        1;           /*The interrupt raw bit for high speed channel0  counter overflow.*/
-            uint32_t hstimer1_ovf:        1;           /*The interrupt raw bit for high speed channel1  counter overflow.*/
-            uint32_t hstimer2_ovf:        1;           /*The interrupt raw bit for high speed channel2  counter overflow.*/
-            uint32_t hstimer3_ovf:        1;           /*The interrupt raw bit for high speed channel3  counter overflow.*/
-            uint32_t lstimer0_ovf:        1;           /*The interrupt raw bit for low speed channel0  counter overflow.*/
-            uint32_t lstimer1_ovf:        1;           /*The interrupt raw bit for low speed channel1  counter overflow.*/
-            uint32_t lstimer2_ovf:        1;           /*The interrupt raw bit for low speed channel2  counter overflow.*/
-            uint32_t lstimer3_ovf:        1;           /*The interrupt raw bit for low speed channel3  counter overflow.*/
-            uint32_t duty_chng_end_hsch0: 1;           /*The interrupt raw bit for high speed channel 0 duty change done.*/
-            uint32_t duty_chng_end_hsch1: 1;           /*The interrupt raw bit for high speed channel 1 duty change done.*/
-            uint32_t duty_chng_end_hsch2: 1;           /*The interrupt raw bit for high speed channel 2 duty change done.*/
-            uint32_t duty_chng_end_hsch3: 1;           /*The interrupt raw bit for high speed channel 3 duty change done.*/
-            uint32_t duty_chng_end_hsch4: 1;           /*The interrupt raw bit for high speed channel 4 duty change done.*/
-            uint32_t duty_chng_end_hsch5: 1;           /*The interrupt raw bit for high speed channel 5 duty change done.*/
-            uint32_t duty_chng_end_hsch6: 1;           /*The interrupt raw bit for high speed channel 6 duty change done.*/
-            uint32_t duty_chng_end_hsch7: 1;           /*The interrupt raw bit for high speed channel 7 duty change done.*/
-            uint32_t duty_chng_end_lsch0: 1;           /*The interrupt raw bit for low speed channel 0 duty change done.*/
-            uint32_t duty_chng_end_lsch1: 1;           /*The interrupt raw bit for low speed channel 1 duty change done.*/
-            uint32_t duty_chng_end_lsch2: 1;           /*The interrupt raw bit for low speed channel 2 duty change done.*/
-            uint32_t duty_chng_end_lsch3: 1;           /*The interrupt raw bit for low speed channel 3 duty change done.*/
-            uint32_t duty_chng_end_lsch4: 1;           /*The interrupt raw bit for low speed channel 4 duty change done.*/
-            uint32_t duty_chng_end_lsch5: 1;           /*The interrupt raw bit for low speed channel 5 duty change done.*/
-            uint32_t duty_chng_end_lsch6: 1;           /*The interrupt raw bit for low speed channel 6 duty change done.*/
-            uint32_t duty_chng_end_lsch7: 1;           /*The interrupt raw bit for low speed channel 7 duty change done.*/
-            uint32_t reserved24:          8;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t hstimer0_ovf:        1;            /*The interrupt status bit for high speed channel0  counter overflow event.*/
-            uint32_t hstimer1_ovf:        1;            /*The interrupt status bit for high speed channel1  counter overflow event.*/
-            uint32_t hstimer2_ovf:        1;            /*The interrupt status bit for high speed channel2  counter overflow event.*/
-            uint32_t hstimer3_ovf:        1;            /*The interrupt status bit for high speed channel3  counter overflow event.*/
-            uint32_t lstimer0_ovf:        1;            /*The interrupt status bit for low speed channel0  counter overflow event.*/
-            uint32_t lstimer1_ovf:        1;            /*The interrupt status bit for low speed channel1  counter overflow event.*/
-            uint32_t lstimer2_ovf:        1;            /*The interrupt status bit for low speed channel2  counter overflow event.*/
-            uint32_t lstimer3_ovf:        1;            /*The interrupt status bit for low speed channel3  counter overflow event.*/
-            uint32_t duty_chng_end_hsch0: 1;            /*The interrupt enable bit for high speed channel 0 duty change done event.*/
-            uint32_t duty_chng_end_hsch1: 1;            /*The interrupt status bit for high speed channel 1 duty change done event.*/
-            uint32_t duty_chng_end_hsch2: 1;            /*The interrupt status bit for high speed channel 2 duty change done event.*/
-            uint32_t duty_chng_end_hsch3: 1;            /*The interrupt status bit for high speed channel 3 duty change done event.*/
-            uint32_t duty_chng_end_hsch4: 1;            /*The interrupt status bit for high speed channel 4 duty change done event.*/
-            uint32_t duty_chng_end_hsch5: 1;            /*The interrupt status bit for high speed channel 5 duty change done event.*/
-            uint32_t duty_chng_end_hsch6: 1;            /*The interrupt status bit for high speed channel 6 duty change done event.*/
-            uint32_t duty_chng_end_hsch7: 1;            /*The interrupt status bit for high speed channel 7 duty change done event.*/
-            uint32_t duty_chng_end_lsch0: 1;            /*The interrupt status bit for low speed channel 0 duty change done event.*/
-            uint32_t duty_chng_end_lsch1: 1;            /*The interrupt status bit for low speed channel 1 duty change done event.*/
-            uint32_t duty_chng_end_lsch2: 1;            /*The interrupt status bit for low speed channel 2 duty change done event.*/
-            uint32_t duty_chng_end_lsch3: 1;            /*The interrupt status bit for low speed channel 3 duty change done event.*/
-            uint32_t duty_chng_end_lsch4: 1;            /*The interrupt status bit for low speed channel 4 duty change done event.*/
-            uint32_t duty_chng_end_lsch5: 1;            /*The interrupt status bit for low speed channel 5 duty change done event.*/
-            uint32_t duty_chng_end_lsch6: 1;            /*The interrupt status bit for low speed channel 6 duty change done event.*/
-            uint32_t duty_chng_end_lsch7: 1;            /*The interrupt status bit for low speed channel 7 duty change done event*/
-            uint32_t reserved24:          8;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t hstimer0_ovf:        1;           /*The interrupt enable bit for high speed channel0  counter overflow interrupt.*/
-            uint32_t hstimer1_ovf:        1;           /*The interrupt enable bit for high speed channel1  counter overflow interrupt.*/
-            uint32_t hstimer2_ovf:        1;           /*The interrupt enable bit for high speed channel2  counter overflow interrupt.*/
-            uint32_t hstimer3_ovf:        1;           /*The interrupt enable bit for high speed channel3  counter overflow interrupt.*/
-            uint32_t lstimer0_ovf:        1;           /*The interrupt enable bit for low speed channel0  counter overflow interrupt.*/
-            uint32_t lstimer1_ovf:        1;           /*The interrupt enable bit for low speed channel1  counter overflow interrupt.*/
-            uint32_t lstimer2_ovf:        1;           /*The interrupt enable bit for low speed channel2  counter overflow interrupt.*/
-            uint32_t lstimer3_ovf:        1;           /*The interrupt enable bit for low speed channel3  counter overflow interrupt.*/
-            uint32_t duty_chng_end_hsch0: 1;           /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch1: 1;           /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch2: 1;           /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch3: 1;           /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch4: 1;           /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch5: 1;           /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch6: 1;           /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch7: 1;           /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch0: 1;           /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch1: 1;           /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch2: 1;           /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch3: 1;           /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch4: 1;           /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch5: 1;           /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch6: 1;           /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch7: 1;           /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
-            uint32_t reserved24:          8;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t hstimer0_ovf:        1;           /*Set this  bit to clear  high speed channel0  counter overflow interrupt.*/
-            uint32_t hstimer1_ovf:        1;           /*Set this  bit to clear  high speed channel1  counter overflow interrupt.*/
-            uint32_t hstimer2_ovf:        1;           /*Set this  bit to clear  high speed channel2  counter overflow interrupt.*/
-            uint32_t hstimer3_ovf:        1;           /*Set this  bit to clear  high speed channel3  counter overflow interrupt.*/
-            uint32_t lstimer0_ovf:        1;           /*Set this  bit to clear  low speed channel0  counter overflow interrupt.*/
-            uint32_t lstimer1_ovf:        1;           /*Set this  bit to clear  low speed channel1  counter overflow interrupt.*/
-            uint32_t lstimer2_ovf:        1;           /*Set this  bit to clear  low speed channel2  counter overflow interrupt.*/
-            uint32_t lstimer3_ovf:        1;           /*Set this  bit to clear  low speed channel3  counter overflow interrupt.*/
-            uint32_t duty_chng_end_hsch0: 1;           /*Set this  bit to clear  high speed channel 0 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch1: 1;           /*Set this  bit to clear  high speed channel 1 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch2: 1;           /*Set this  bit to clear  high speed channel 2 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch3: 1;           /*Set this  bit to clear  high speed channel 3 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch4: 1;           /*Set this  bit to clear  high speed channel 4 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch5: 1;           /*Set this  bit to clear  high speed channel 5 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch6: 1;           /*Set this  bit to clear  high speed channel 6 duty change done interrupt.*/
-            uint32_t duty_chng_end_hsch7: 1;           /*Set this  bit to clear  high speed channel 7 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch0: 1;           /*Set this  bit to clear  low speed channel 0 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch1: 1;           /*Set this  bit to clear  low speed channel 1 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch2: 1;           /*Set this  bit to clear  low speed channel 2 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch3: 1;           /*Set this  bit to clear  low speed channel 3 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch4: 1;           /*Set this  bit to clear  low speed channel 4 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch5: 1;           /*Set this  bit to clear  low speed channel 5 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch6: 1;           /*Set this  bit to clear  low speed channel 6 duty change done interrupt.*/
-            uint32_t duty_chng_end_lsch7: 1;           /*Set this  bit to clear  low speed channel 7 duty change done interrupt.*/
-            uint32_t reserved24:          8;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t apb_clk_sel: 1;                   /*This bit decides the slow clock for LEDC low speed channels, so we want to replace the field name with slow_clk_sel*/
-            uint32_t reserved1:  31;
-        };
-        struct {
-            uint32_t slow_clk_sel: 1;                  /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz  1'b0:8mhz, (only used by LEDC low speed channels/timers)*/
-            uint32_t reserved:  31;
-        };
-        uint32_t val;
-    } conf;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t date;                                     /*This register represents the version .*/
-} ledc_dev_t;
-extern ledc_dev_t LEDC;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_LEDC_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/mcpwm_reg.h b/tools/sdk/include/soc/soc/mcpwm_reg.h
deleted file mode 100644
index 1dce94d4694..00000000000
--- a/tools/sdk/include/soc/soc/mcpwm_reg.h
+++ /dev/null
@@ -1,3028 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_MCPWM_REG_H_
-#define _SOC_MCPWM_REG_H_
-#include "soc.h"
-
-#define REG_MCPWM_BASE(i)               (DR_REG_PWM_BASE + i * (0xE000))
-#define MCPWM_CLK_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0000)
-/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
-#define MCPWM_CLK_PRESCALE  0x000000FF
-#define MCPWM_CLK_PRESCALE_M  ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S))
-#define MCPWM_CLK_PRESCALE_V  0xFF
-#define MCPWM_CLK_PRESCALE_S  0
-
-#define MCPWM_TIMER0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0004)
-/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: Update method for active reg of PWM timer0 period  0: immediate
-  1: TEZ  2: sync  3: TEZ or sync. TEZ here and below means timer equal zero event*/
-#define MCPWM_TIMER0_PERIOD_UPMETHOD  0x00000003
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S))
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x3
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
-/*description: Period shadow reg of PWM timer0*/
-#define MCPWM_TIMER0_PERIOD  0x0000FFFF
-#define MCPWM_TIMER0_PERIOD_M  ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S))
-#define MCPWM_TIMER0_PERIOD_V  0xFFFF
-#define MCPWM_TIMER0_PERIOD_S  8
-/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
-#define MCPWM_TIMER0_PRESCALE  0x000000FF
-#define MCPWM_TIMER0_PRESCALE_M  ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S))
-#define MCPWM_TIMER0_PRESCALE_V  0xFF
-#define MCPWM_TIMER0_PRESCALE_S  0
-
-#define MCPWM_TIMER0_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0008)
-/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: PWM timer0 working mode  0: freeze  1: increase mod  2: decrease
- mod  3: up-down mod*/
-#define MCPWM_TIMER0_MOD  0x00000003
-#define MCPWM_TIMER0_MOD_M  ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S))
-#define MCPWM_TIMER0_MOD_V  0x3
-#define MCPWM_TIMER0_MOD_S  3
-/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: PWM timer0 start and stop control. 0: stop @ TEZ  1: stop @ TEP
-  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP. TEP here and below means timer equal period event*/
-#define MCPWM_TIMER0_START  0x00000007
-#define MCPWM_TIMER0_START_M  ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S))
-#define MCPWM_TIMER0_START_V  0x7
-#define MCPWM_TIMER0_START_S  0
-
-#define MCPWM_TIMER0_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x000c)
-/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
-/*description: Phase for timer reload on sync event*/
-#define MCPWM_TIMER0_PHASE  0x0001FFFF
-#define MCPWM_TIMER0_PHASE_M  ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S))
-#define MCPWM_TIMER0_PHASE_V  0x1FFFF
-#define MCPWM_TIMER0_PHASE_S  4
-/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: PWM timer0 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
-#define MCPWM_TIMER0_SYNCO_SEL  0x00000003
-#define MCPWM_TIMER0_SYNCO_SEL_M  ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S))
-#define MCPWM_TIMER0_SYNCO_SEL_V  0x3
-#define MCPWM_TIMER0_SYNCO_SEL_S  2
-/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Toggling this bit will trigger a software sync*/
-#define MCPWM_TIMER0_SYNC_SW  (BIT(1))
-#define MCPWM_TIMER0_SYNC_SW_M  (BIT(1))
-#define MCPWM_TIMER0_SYNC_SW_V  0x1
-#define MCPWM_TIMER0_SYNC_SW_S  1
-/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: When set   timer reload with phase on sync input event is enabled*/
-#define MCPWM_TIMER0_SYNCI_EN  (BIT(0))
-#define MCPWM_TIMER0_SYNCI_EN_M  (BIT(0))
-#define MCPWM_TIMER0_SYNCI_EN_V  0x1
-#define MCPWM_TIMER0_SYNCI_EN_S  0
-
-#define MCPWM_TIMER0_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0010)
-/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
-/*description: Current PWM timer0 counter direction  0: increment 1: decrement*/
-#define MCPWM_TIMER0_DIRECTION  (BIT(16))
-#define MCPWM_TIMER0_DIRECTION_M  (BIT(16))
-#define MCPWM_TIMER0_DIRECTION_V  0x1
-#define MCPWM_TIMER0_DIRECTION_S  16
-/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: Current PWM timer0 counter value*/
-#define MCPWM_TIMER0_VALUE  0x0000FFFF
-#define MCPWM_TIMER0_VALUE_M  ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S))
-#define MCPWM_TIMER0_VALUE_V  0xFFFF
-#define MCPWM_TIMER0_VALUE_S  0
-
-#define MCPWM_TIMER1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0014)
-/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: Update method for active reg of PWM timer1 period  0: immediate
-  1: TEZ  2: sync  3: TEZ or sync*/
-#define MCPWM_TIMER1_PERIOD_UPMETHOD  0x00000003
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S))
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x3
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
-/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
-/*description: Period shadow reg of PWM timer1*/
-#define MCPWM_TIMER1_PERIOD  0x0000FFFF
-#define MCPWM_TIMER1_PERIOD_M  ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S))
-#define MCPWM_TIMER1_PERIOD_V  0xFFFF
-#define MCPWM_TIMER1_PERIOD_S  8
-/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)*/
-#define MCPWM_TIMER1_PRESCALE  0x000000FF
-#define MCPWM_TIMER1_PRESCALE_M  ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S))
-#define MCPWM_TIMER1_PRESCALE_V  0xFF
-#define MCPWM_TIMER1_PRESCALE_S  0
-
-#define MCPWM_TIMER1_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0018)
-/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: PWM timer1 working mode  0: freeze  1: increase mod  2: decrease
- mod  3: up-down mod*/
-#define MCPWM_TIMER1_MOD  0x00000003
-#define MCPWM_TIMER1_MOD_M  ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S))
-#define MCPWM_TIMER1_MOD_V  0x3
-#define MCPWM_TIMER1_MOD_S  3
-/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: PWM timer1 start and stop control. 0: stop @ TEZ  1: stop @ TEP
-  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP.*/
-#define MCPWM_TIMER1_START  0x00000007
-#define MCPWM_TIMER1_START_M  ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S))
-#define MCPWM_TIMER1_START_V  0x7
-#define MCPWM_TIMER1_START_S  0
-
-#define MCPWM_TIMER1_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x001c)
-/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
-/*description: Phase for timer reload on sync event*/
-#define MCPWM_TIMER1_PHASE  0x0001FFFF
-#define MCPWM_TIMER1_PHASE_M  ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S))
-#define MCPWM_TIMER1_PHASE_V  0x1FFFF
-#define MCPWM_TIMER1_PHASE_S  4
-/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: PWM timer1 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
-#define MCPWM_TIMER1_SYNCO_SEL  0x00000003
-#define MCPWM_TIMER1_SYNCO_SEL_M  ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S))
-#define MCPWM_TIMER1_SYNCO_SEL_V  0x3
-#define MCPWM_TIMER1_SYNCO_SEL_S  2
-/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Toggling this bit will trigger a software sync*/
-#define MCPWM_TIMER1_SYNC_SW  (BIT(1))
-#define MCPWM_TIMER1_SYNC_SW_M  (BIT(1))
-#define MCPWM_TIMER1_SYNC_SW_V  0x1
-#define MCPWM_TIMER1_SYNC_SW_S  1
-/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: When set   timer reload with phase on sync input event is enabled*/
-#define MCPWM_TIMER1_SYNCI_EN  (BIT(0))
-#define MCPWM_TIMER1_SYNCI_EN_M  (BIT(0))
-#define MCPWM_TIMER1_SYNCI_EN_V  0x1
-#define MCPWM_TIMER1_SYNCI_EN_S  0
-
-#define MCPWM_TIMER1_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0020)
-/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
-/*description: Current PWM timer1 counter direction  0: increment 1: decrement*/
-#define MCPWM_TIMER1_DIRECTION  (BIT(16))
-#define MCPWM_TIMER1_DIRECTION_M  (BIT(16))
-#define MCPWM_TIMER1_DIRECTION_V  0x1
-#define MCPWM_TIMER1_DIRECTION_S  16
-/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: Current PWM timer1 counter value*/
-#define MCPWM_TIMER1_VALUE  0x0000FFFF
-#define MCPWM_TIMER1_VALUE_M  ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S))
-#define MCPWM_TIMER1_VALUE_V  0xFFFF
-#define MCPWM_TIMER1_VALUE_S  0
-
-#define MCPWM_TIMER2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0024)
-/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: Update method for active reg of PWM timer2 period  0: immediate
-  1: TEZ  2: sync  3: TEZ or sync*/
-#define MCPWM_TIMER2_PERIOD_UPMETHOD  0x00000003
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S))
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x3
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
-/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
-/*description: Period shadow reg of PWM timer2*/
-#define MCPWM_TIMER2_PERIOD  0x0000FFFF
-#define MCPWM_TIMER2_PERIOD_M  ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S))
-#define MCPWM_TIMER2_PERIOD_V  0xFFFF
-#define MCPWM_TIMER2_PERIOD_S  8
-/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)*/
-#define MCPWM_TIMER2_PRESCALE  0x000000FF
-#define MCPWM_TIMER2_PRESCALE_M  ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S))
-#define MCPWM_TIMER2_PRESCALE_V  0xFF
-#define MCPWM_TIMER2_PRESCALE_S  0
-
-#define MCPWM_TIMER2_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0028)
-/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: PWM timer2 working mode  0: freeze  1: increase mod  2: decrease
- mod  3: up-down mod*/
-#define MCPWM_TIMER2_MOD  0x00000003
-#define MCPWM_TIMER2_MOD_M  ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S))
-#define MCPWM_TIMER2_MOD_V  0x3
-#define MCPWM_TIMER2_MOD_S  3
-/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: PWM timer2 start and stop control. 0: stop @ TEZ  1: stop @ TEP
-  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP.*/
-#define MCPWM_TIMER2_START  0x00000007
-#define MCPWM_TIMER2_START_M  ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S))
-#define MCPWM_TIMER2_START_V  0x7
-#define MCPWM_TIMER2_START_S  0
-
-#define MCPWM_TIMER2_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x002c)
-/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
-/*description: Phase for timer reload on sync event*/
-#define MCPWM_TIMER2_PHASE  0x0001FFFF
-#define MCPWM_TIMER2_PHASE_M  ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S))
-#define MCPWM_TIMER2_PHASE_V  0x1FFFF
-#define MCPWM_TIMER2_PHASE_S  4
-/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: PWM timer2 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
-#define MCPWM_TIMER2_SYNCO_SEL  0x00000003
-#define MCPWM_TIMER2_SYNCO_SEL_M  ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S))
-#define MCPWM_TIMER2_SYNCO_SEL_V  0x3
-#define MCPWM_TIMER2_SYNCO_SEL_S  2
-/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Toggling this bit will trigger a software sync*/
-#define MCPWM_TIMER2_SYNC_SW  (BIT(1))
-#define MCPWM_TIMER2_SYNC_SW_M  (BIT(1))
-#define MCPWM_TIMER2_SYNC_SW_V  0x1
-#define MCPWM_TIMER2_SYNC_SW_S  1
-/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: When set   timer reload with phase on sync input event is enabled*/
-#define MCPWM_TIMER2_SYNCI_EN  (BIT(0))
-#define MCPWM_TIMER2_SYNCI_EN_M  (BIT(0))
-#define MCPWM_TIMER2_SYNCI_EN_V  0x1
-#define MCPWM_TIMER2_SYNCI_EN_S  0
-
-#define MCPWM_TIMER2_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0030)
-/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
-/*description: Current PWM timer2 counter direction  0: increment 1: decrement*/
-#define MCPWM_TIMER2_DIRECTION  (BIT(16))
-#define MCPWM_TIMER2_DIRECTION_M  (BIT(16))
-#define MCPWM_TIMER2_DIRECTION_V  0x1
-#define MCPWM_TIMER2_DIRECTION_S  16
-/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: Current PWM timer2 counter value*/
-#define MCPWM_TIMER2_VALUE  0x0000FFFF
-#define MCPWM_TIMER2_VALUE_M  ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S))
-#define MCPWM_TIMER2_VALUE_V  0xFFFF
-#define MCPWM_TIMER2_VALUE_S  0
-
-#define MCPWM_TIMER_SYNCI_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0034)
-/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: Onvert SYNC2 from GPIO matrix*/
-#define MCPWM_EXTERNAL_SYNCI2_INVERT  (BIT(11))
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (BIT(11))
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x1
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
-/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: Invert SYNC1 from GPIO matrix*/
-#define MCPWM_EXTERNAL_SYNCI1_INVERT  (BIT(10))
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (BIT(10))
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x1
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
-/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: Invert SYNC0 from GPIO matrix*/
-#define MCPWM_EXTERNAL_SYNCI0_INVERT  (BIT(9))
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (BIT(9))
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x1
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
-/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */
-/*description: Select sync input for PWM timer2  1: PWM timer0 synco  2: PWM
- timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
-#define MCPWM_TIMER2_SYNCISEL  0x00000007
-#define MCPWM_TIMER2_SYNCISEL_M  ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S))
-#define MCPWM_TIMER2_SYNCISEL_V  0x7
-#define MCPWM_TIMER2_SYNCISEL_S  6
-/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */
-/*description: Select sync input for PWM timer1  1: PWM timer0 synco  2: PWM
- timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
-#define MCPWM_TIMER1_SYNCISEL  0x00000007
-#define MCPWM_TIMER1_SYNCISEL_M  ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S))
-#define MCPWM_TIMER1_SYNCISEL_V  0x7
-#define MCPWM_TIMER1_SYNCISEL_S  3
-/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */
-/*description: Select sync input for PWM timer0  1: PWM timer0 synco  2: PWM
- timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
-#define MCPWM_TIMER0_SYNCISEL  0x00000007
-#define MCPWM_TIMER0_SYNCISEL_M  ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S))
-#define MCPWM_TIMER0_SYNCISEL_V  0x7
-#define MCPWM_TIMER0_SYNCISEL_S  0
-
-#define MCPWM_OPERATOR_TIMERSEL_REG(i)          (REG_MCPWM_BASE(i) + 0x0038)
-/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
-/*description: Select which PWM timer's is the timing reference for PWM operator2
-  0: timer0  1: timer1  2: timer2*/
-#define MCPWM_OPERATOR2_TIMERSEL  0x00000003
-#define MCPWM_OPERATOR2_TIMERSEL_M  ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S))
-#define MCPWM_OPERATOR2_TIMERSEL_V  0x3
-#define MCPWM_OPERATOR2_TIMERSEL_S  4
-/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: Select which PWM timer's is the timing reference for PWM operator1
-  0: timer0  1: timer1  2: timer2*/
-#define MCPWM_OPERATOR1_TIMERSEL  0x00000003
-#define MCPWM_OPERATOR1_TIMERSEL_M  ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S))
-#define MCPWM_OPERATOR1_TIMERSEL_V  0x3
-#define MCPWM_OPERATOR1_TIMERSEL_S  2
-/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: Select which PWM timer's is the timing reference for PWM operator0
-  0: timer0  1: timer1  2: timer2*/
-#define MCPWM_OPERATOR0_TIMERSEL  0x00000003
-#define MCPWM_OPERATOR0_TIMERSEL_M  ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S))
-#define MCPWM_OPERATOR0_TIMERSEL_V  0x3
-#define MCPWM_OPERATOR0_TIMERSEL_S  0
-
-#define MCPWM_GEN0_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x003c)
-/* MCPWM_GEN0_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  PWM generator 0 time stamp
- B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
-#define MCPWM_GEN0_B_SHDW_FULL  (BIT(9))
-#define MCPWM_GEN0_B_SHDW_FULL_M  (BIT(9))
-#define MCPWM_GEN0_B_SHDW_FULL_V  0x1
-#define MCPWM_GEN0_B_SHDW_FULL_S  9
-/* MCPWM_GEN0_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  PWM generator 0 time stamp
- A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
-#define MCPWM_GEN0_A_SHDW_FULL  (BIT(8))
-#define MCPWM_GEN0_A_SHDW_FULL_M  (BIT(8))
-#define MCPWM_GEN0_A_SHDW_FULL_V  0x1
-#define MCPWM_GEN0_A_SHDW_FULL_S  8
-/* MCPWM_GEN0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
-/*description: Update method for PWM generator 0 time stamp B's active reg.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_GEN0_B_UPMETHOD  0x0000000F
-#define MCPWM_GEN0_B_UPMETHOD_M  ((MCPWM_GEN0_B_UPMETHOD_V)<<(MCPWM_GEN0_B_UPMETHOD_S))
-#define MCPWM_GEN0_B_UPMETHOD_V  0xF
-#define MCPWM_GEN0_B_UPMETHOD_S  4
-/* MCPWM_GEN0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: Update method for PWM generator 0 time stamp A's active reg.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_GEN0_A_UPMETHOD  0x0000000F
-#define MCPWM_GEN0_A_UPMETHOD_M  ((MCPWM_GEN0_A_UPMETHOD_V)<<(MCPWM_GEN0_A_UPMETHOD_S))
-#define MCPWM_GEN0_A_UPMETHOD_V  0xF
-#define MCPWM_GEN0_A_UPMETHOD_S  0
-
-#define MCPWM_GEN0_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0040)
-/* MCPWM_GEN0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: PWM generator 0 time stamp A's shadow reg*/
-#define MCPWM_GEN0_A  0x0000FFFF
-#define MCPWM_GEN0_A_M  ((MCPWM_GEN0_A_V)<<(MCPWM_GEN0_A_S))
-#define MCPWM_GEN0_A_V  0xFFFF
-#define MCPWM_GEN0_A_S  0
-
-#define MCPWM_GEN0_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x0044)
-/* MCPWM_GEN0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: PWM generator 0 time stamp B's shadow reg*/
-#define MCPWM_GEN0_B  0x0000FFFF
-#define MCPWM_GEN0_B_M  ((MCPWM_GEN0_B_V)<<(MCPWM_GEN0_B_S))
-#define MCPWM_GEN0_B_V  0xFFFF
-#define MCPWM_GEN0_B_S  0
-
-#define MCPWM_GEN0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0048)
-/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
-/*description: Source selection for PWM generator 0 event_t1  take effect immediately
-  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
-#define MCPWM_GEN0_T1_SEL  0x00000007
-#define MCPWM_GEN0_T1_SEL_M  ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S))
-#define MCPWM_GEN0_T1_SEL_V  0x7
-#define MCPWM_GEN0_T1_SEL_S  7
-/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
-/*description: Source selection for PWM generator 0 event_t0  take effect immediately
-  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
-#define MCPWM_GEN0_T0_SEL  0x00000007
-#define MCPWM_GEN0_T0_SEL_M  ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S))
-#define MCPWM_GEN0_T0_SEL_V  0x7
-#define MCPWM_GEN0_T0_SEL_S  4
-/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: Update method for PWM generator 0's active reg of configuration.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
-#define MCPWM_GEN0_CFG_UPMETHOD  0x0000000F
-#define MCPWM_GEN0_CFG_UPMETHOD_M  ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S))
-#define MCPWM_GEN0_CFG_UPMETHOD_V  0xF
-#define MCPWM_GEN0_CFG_UPMETHOD_S  0
-
-#define MCPWM_GEN0_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x004c)
-/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: Non-continuous immediate software force mode for PWM0B  0: disabled
-  1: low  2: high  3: disabled*/
-#define MCPWM_GEN0_B_NCIFORCE_MODE  0x00000003
-#define MCPWM_GEN0_B_NCIFORCE_MODE_M  ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S))
-#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x3
-#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
-/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: Non-continuous immediate software force trigger for PWM0B  a
- toggle will trigger a force event*/
-#define MCPWM_GEN0_B_NCIFORCE  (BIT(13))
-#define MCPWM_GEN0_B_NCIFORCE_M  (BIT(13))
-#define MCPWM_GEN0_B_NCIFORCE_V  0x1
-#define MCPWM_GEN0_B_NCIFORCE_S  13
-/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
-/*description: Non-continuous immediate software force mode for PWM0A  0: disabled
-  1: low  2: high  3: disabled*/
-#define MCPWM_GEN0_A_NCIFORCE_MODE  0x00000003
-#define MCPWM_GEN0_A_NCIFORCE_MODE_M  ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S))
-#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x3
-#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
-/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: Non-continuous immediate software force trigger for PWM0A  a
- toggle will trigger a force event*/
-#define MCPWM_GEN0_A_NCIFORCE  (BIT(10))
-#define MCPWM_GEN0_A_NCIFORCE_M  (BIT(10))
-#define MCPWM_GEN0_A_NCIFORCE_V  0x1
-#define MCPWM_GEN0_A_NCIFORCE_S  10
-/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Continuous software force mode for PWM0B. 0: disabled  1: low
-  2: high  3: disabled*/
-#define MCPWM_GEN0_B_CNTUFORCE_MODE  0x00000003
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S))
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x3
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
-/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Continuous software force mode for PWM0A. 0: disabled  1: low
-  2: high  3: disabled*/
-#define MCPWM_GEN0_A_CNTUFORCE_MODE  0x00000003
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S))
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x3
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
-/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
-/*description: Update method for continuous software force of PWM generator0.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD  0x0000003F
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S))
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x3F
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
-
-#define MCPWM_GEN0_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0050)
-/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event_t1 when timer decreasing.
- 0: no change  1: low  2: high  3: toggle*/
-#define MCPWM_GEN0_A_DT1  0x00000003
-#define MCPWM_GEN0_A_DT1_M  ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S))
-#define MCPWM_GEN0_A_DT1_V  0x3
-#define MCPWM_GEN0_A_DT1_S  22
-/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event_t0 when timer decreasing*/
-#define MCPWM_GEN0_A_DT0  0x00000003
-#define MCPWM_GEN0_A_DT0_M  ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S))
-#define MCPWM_GEN0_A_DT0_V  0x3
-#define MCPWM_GEN0_A_DT0_S  20
-/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event TEB when timer decreasing*/
-#define MCPWM_GEN0_A_DTEB  0x00000003
-#define MCPWM_GEN0_A_DTEB_M  ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S))
-#define MCPWM_GEN0_A_DTEB_V  0x3
-#define MCPWM_GEN0_A_DTEB_S  18
-/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event TEA when timer decreasing*/
-#define MCPWM_GEN0_A_DTEA  0x00000003
-#define MCPWM_GEN0_A_DTEA_M  ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S))
-#define MCPWM_GEN0_A_DTEA_V  0x3
-#define MCPWM_GEN0_A_DTEA_S  16
-/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event TEP when timer decreasing*/
-#define MCPWM_GEN0_A_DTEP  0x00000003
-#define MCPWM_GEN0_A_DTEP_M  ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S))
-#define MCPWM_GEN0_A_DTEP_V  0x3
-#define MCPWM_GEN0_A_DTEP_S  14
-/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event TEZ when timer decreasing*/
-#define MCPWM_GEN0_A_DTEZ  0x00000003
-#define MCPWM_GEN0_A_DTEZ_M  ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S))
-#define MCPWM_GEN0_A_DTEZ_V  0x3
-#define MCPWM_GEN0_A_DTEZ_S  12
-/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event_t1 when timer increasing*/
-#define MCPWM_GEN0_A_UT1  0x00000003
-#define MCPWM_GEN0_A_UT1_M  ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S))
-#define MCPWM_GEN0_A_UT1_V  0x3
-#define MCPWM_GEN0_A_UT1_S  10
-/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event_t0 when timer increasing*/
-#define MCPWM_GEN0_A_UT0  0x00000003
-#define MCPWM_GEN0_A_UT0_M  ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S))
-#define MCPWM_GEN0_A_UT0_V  0x3
-#define MCPWM_GEN0_A_UT0_S  8
-/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event TEB when timer increasing*/
-#define MCPWM_GEN0_A_UTEB  0x00000003
-#define MCPWM_GEN0_A_UTEB_M  ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S))
-#define MCPWM_GEN0_A_UTEB_V  0x3
-#define MCPWM_GEN0_A_UTEB_S  6
-/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event TEA when timer increasing*/
-#define MCPWM_GEN0_A_UTEA  0x00000003
-#define MCPWM_GEN0_A_UTEA_M  ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S))
-#define MCPWM_GEN0_A_UTEA_V  0x3
-#define MCPWM_GEN0_A_UTEA_S  4
-/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event TEP when timer increasing*/
-#define MCPWM_GEN0_A_UTEP  0x00000003
-#define MCPWM_GEN0_A_UTEP_M  ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S))
-#define MCPWM_GEN0_A_UTEP_V  0x3
-#define MCPWM_GEN0_A_UTEP_S  2
-/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: Action on PWM0A triggered by event TEZ when timer increasing*/
-#define MCPWM_GEN0_A_UTEZ  0x00000003
-#define MCPWM_GEN0_A_UTEZ_M  ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S))
-#define MCPWM_GEN0_A_UTEZ_V  0x3
-#define MCPWM_GEN0_A_UTEZ_S  0
-
-#define MCPWM_GEN0_B_REG(i)          (REG_MCPWM_BASE(i) + 0x0054)
-/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event_t1 when timer decreasing.
- 0: no change  1: low  2: high  3: toggle*/
-#define MCPWM_GEN0_B_DT1  0x00000003
-#define MCPWM_GEN0_B_DT1_M  ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S))
-#define MCPWM_GEN0_B_DT1_V  0x3
-#define MCPWM_GEN0_B_DT1_S  22
-/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event_t0 when timer decreasing*/
-#define MCPWM_GEN0_B_DT0  0x00000003
-#define MCPWM_GEN0_B_DT0_M  ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S))
-#define MCPWM_GEN0_B_DT0_V  0x3
-#define MCPWM_GEN0_B_DT0_S  20
-/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event TEB when timer decreasing*/
-#define MCPWM_GEN0_B_DTEB  0x00000003
-#define MCPWM_GEN0_B_DTEB_M  ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S))
-#define MCPWM_GEN0_B_DTEB_V  0x3
-#define MCPWM_GEN0_B_DTEB_S  18
-/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event TEA when timer decreasing*/
-#define MCPWM_GEN0_B_DTEA  0x00000003
-#define MCPWM_GEN0_B_DTEA_M  ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S))
-#define MCPWM_GEN0_B_DTEA_V  0x3
-#define MCPWM_GEN0_B_DTEA_S  16
-/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event TEP when timer decreasing*/
-#define MCPWM_GEN0_B_DTEP  0x00000003
-#define MCPWM_GEN0_B_DTEP_M  ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S))
-#define MCPWM_GEN0_B_DTEP_V  0x3
-#define MCPWM_GEN0_B_DTEP_S  14
-/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event TEZ when timer decreasing*/
-#define MCPWM_GEN0_B_DTEZ  0x00000003
-#define MCPWM_GEN0_B_DTEZ_M  ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S))
-#define MCPWM_GEN0_B_DTEZ_V  0x3
-#define MCPWM_GEN0_B_DTEZ_S  12
-/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event_t1 when timer increasing*/
-#define MCPWM_GEN0_B_UT1  0x00000003
-#define MCPWM_GEN0_B_UT1_M  ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S))
-#define MCPWM_GEN0_B_UT1_V  0x3
-#define MCPWM_GEN0_B_UT1_S  10
-/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event_t0 when timer increasing*/
-#define MCPWM_GEN0_B_UT0  0x00000003
-#define MCPWM_GEN0_B_UT0_M  ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S))
-#define MCPWM_GEN0_B_UT0_V  0x3
-#define MCPWM_GEN0_B_UT0_S  8
-/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event TEB when timer increasing*/
-#define MCPWM_GEN0_B_UTEB  0x00000003
-#define MCPWM_GEN0_B_UTEB_M  ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S))
-#define MCPWM_GEN0_B_UTEB_V  0x3
-#define MCPWM_GEN0_B_UTEB_S  6
-/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event TEA when timer increasing*/
-#define MCPWM_GEN0_B_UTEA  0x00000003
-#define MCPWM_GEN0_B_UTEA_M  ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S))
-#define MCPWM_GEN0_B_UTEA_V  0x3
-#define MCPWM_GEN0_B_UTEA_S  4
-/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event TEP when timer increasing*/
-#define MCPWM_GEN0_B_UTEP  0x00000003
-#define MCPWM_GEN0_B_UTEP_M  ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S))
-#define MCPWM_GEN0_B_UTEP_V  0x3
-#define MCPWM_GEN0_B_UTEP_S  2
-/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: Action on PWM0B triggered by event TEZ when timer increasing*/
-#define MCPWM_GEN0_B_UTEZ  0x00000003
-#define MCPWM_GEN0_B_UTEZ_M  ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S))
-#define MCPWM_GEN0_B_UTEZ_V  0x3
-#define MCPWM_GEN0_B_UTEZ_S  0
-
-#define MCPWM_DT0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0058)
-/* MCPWM_DT0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Dead time generator 0 clock selection. 0: PWM_clk  1: PT_clk*/
-#define MCPWM_DT0_CLK_SEL  (BIT(17))
-#define MCPWM_DT0_CLK_SEL_M  (BIT(17))
-#define MCPWM_DT0_CLK_SEL_V  0x1
-#define MCPWM_DT0_CLK_SEL_S  17
-/* MCPWM_DT0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: S0 in documentation*/
-#define MCPWM_DT0_B_OUTBYPASS  (BIT(16))
-#define MCPWM_DT0_B_OUTBYPASS_M  (BIT(16))
-#define MCPWM_DT0_B_OUTBYPASS_V  0x1
-#define MCPWM_DT0_B_OUTBYPASS_S  16
-/* MCPWM_DT0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
-/*description: S1 in documentation*/
-#define MCPWM_DT0_A_OUTBYPASS  (BIT(15))
-#define MCPWM_DT0_A_OUTBYPASS_M  (BIT(15))
-#define MCPWM_DT0_A_OUTBYPASS_V  0x1
-#define MCPWM_DT0_A_OUTBYPASS_S  15
-/* MCPWM_DT0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: S3 in documentation*/
-#define MCPWM_DT0_FED_OUTINVERT  (BIT(14))
-#define MCPWM_DT0_FED_OUTINVERT_M  (BIT(14))
-#define MCPWM_DT0_FED_OUTINVERT_V  0x1
-#define MCPWM_DT0_FED_OUTINVERT_S  14
-/* MCPWM_DT0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: S2 in documentation*/
-#define MCPWM_DT0_RED_OUTINVERT  (BIT(13))
-#define MCPWM_DT0_RED_OUTINVERT_M  (BIT(13))
-#define MCPWM_DT0_RED_OUTINVERT_V  0x1
-#define MCPWM_DT0_RED_OUTINVERT_S  13
-/* MCPWM_DT0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: S5 in documentation*/
-#define MCPWM_DT0_FED_INSEL  (BIT(12))
-#define MCPWM_DT0_FED_INSEL_M  (BIT(12))
-#define MCPWM_DT0_FED_INSEL_V  0x1
-#define MCPWM_DT0_FED_INSEL_S  12
-/* MCPWM_DT0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: S4 in documentation*/
-#define MCPWM_DT0_RED_INSEL  (BIT(11))
-#define MCPWM_DT0_RED_INSEL_M  (BIT(11))
-#define MCPWM_DT0_RED_INSEL_V  0x1
-#define MCPWM_DT0_RED_INSEL_S  11
-/* MCPWM_DT0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: S7 in documentation*/
-#define MCPWM_DT0_B_OUTSWAP  (BIT(10))
-#define MCPWM_DT0_B_OUTSWAP_M  (BIT(10))
-#define MCPWM_DT0_B_OUTSWAP_V  0x1
-#define MCPWM_DT0_B_OUTSWAP_S  10
-/* MCPWM_DT0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: S6 in documentation*/
-#define MCPWM_DT0_A_OUTSWAP  (BIT(9))
-#define MCPWM_DT0_A_OUTSWAP_M  (BIT(9))
-#define MCPWM_DT0_A_OUTSWAP_V  0x1
-#define MCPWM_DT0_A_OUTSWAP_S  9
-/* MCPWM_DT0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
- on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
-#define MCPWM_DT0_DEB_MODE  (BIT(8))
-#define MCPWM_DT0_DEB_MODE_M  (BIT(8))
-#define MCPWM_DT0_DEB_MODE_V  0x1
-#define MCPWM_DT0_DEB_MODE_S  8
-/* MCPWM_DT0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
-/*description: Update method for RED (rising edge delay) active reg. 0: immediate
-  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_DT0_RED_UPMETHOD  0x0000000F
-#define MCPWM_DT0_RED_UPMETHOD_M  ((MCPWM_DT0_RED_UPMETHOD_V)<<(MCPWM_DT0_RED_UPMETHOD_S))
-#define MCPWM_DT0_RED_UPMETHOD_V  0xF
-#define MCPWM_DT0_RED_UPMETHOD_S  4
-/* MCPWM_DT0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: Update method for FED (falling edge delay) active reg. 0: immediate
-  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_DT0_FED_UPMETHOD  0x0000000F
-#define MCPWM_DT0_FED_UPMETHOD_M  ((MCPWM_DT0_FED_UPMETHOD_V)<<(MCPWM_DT0_FED_UPMETHOD_S))
-#define MCPWM_DT0_FED_UPMETHOD_V  0xF
-#define MCPWM_DT0_FED_UPMETHOD_S  0
-
-#define MCPWM_DT0_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x005c)
-/* MCPWM_DT0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: Shadow reg for FED*/
-#define MCPWM_DT0_FED  0x0000FFFF
-#define MCPWM_DT0_FED_M  ((MCPWM_DT0_FED_V)<<(MCPWM_DT0_FED_S))
-#define MCPWM_DT0_FED_V  0xFFFF
-#define MCPWM_DT0_FED_S  0
-
-#define MCPWM_DT0_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0060)
-/* MCPWM_DT0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: Shadow reg for RED*/
-#define MCPWM_DT0_RED  0x0000FFFF
-#define MCPWM_DT0_RED_M  ((MCPWM_DT0_RED_V)<<(MCPWM_DT0_RED_S))
-#define MCPWM_DT0_RED_V  0xFFFF
-#define MCPWM_DT0_RED_S  0
-
-#define MCPWM_CARRIER0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0064)
-/* MCPWM_CARRIER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: When set  invert the input of PWM0A and PWM0B for this submodule*/
-#define MCPWM_CARRIER0_IN_INVERT  (BIT(13))
-#define MCPWM_CARRIER0_IN_INVERT_M  (BIT(13))
-#define MCPWM_CARRIER0_IN_INVERT_V  0x1
-#define MCPWM_CARRIER0_IN_INVERT_S  13
-/* MCPWM_CARRIER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: When set  invert the output of PWM0A and PWM0B for this submodule*/
-#define MCPWM_CARRIER0_OUT_INVERT  (BIT(12))
-#define MCPWM_CARRIER0_OUT_INVERT_M  (BIT(12))
-#define MCPWM_CARRIER0_OUT_INVERT_V  0x1
-#define MCPWM_CARRIER0_OUT_INVERT_S  12
-/* MCPWM_CARRIER0_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
-/*description: Width of the fist pulse in number of periods of the carrier*/
-#define MCPWM_CARRIER0_OSHWTH  0x0000000F
-#define MCPWM_CARRIER0_OSHWTH_M  ((MCPWM_CARRIER0_OSHWTH_V)<<(MCPWM_CARRIER0_OSHWTH_S))
-#define MCPWM_CARRIER0_OSHWTH_V  0xF
-#define MCPWM_CARRIER0_OSHWTH_S  8
-/* MCPWM_CARRIER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
-/*description: Carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
-#define MCPWM_CARRIER0_DUTY  0x00000007
-#define MCPWM_CARRIER0_DUTY_M  ((MCPWM_CARRIER0_DUTY_V)<<(MCPWM_CARRIER0_DUTY_S))
-#define MCPWM_CARRIER0_DUTY_V  0x7
-#define MCPWM_CARRIER0_DUTY_S  5
-/* MCPWM_CARRIER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
-/*description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk
- = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
-#define MCPWM_CARRIER0_PRESCALE  0x0000000F
-#define MCPWM_CARRIER0_PRESCALE_M  ((MCPWM_CARRIER0_PRESCALE_V)<<(MCPWM_CARRIER0_PRESCALE_S))
-#define MCPWM_CARRIER0_PRESCALE_V  0xF
-#define MCPWM_CARRIER0_PRESCALE_S  1
-/* MCPWM_CARRIER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: When set  carrier0 function is enabled. When cleared  carrier0 is bypassed*/
-#define MCPWM_CARRIER0_EN  (BIT(0))
-#define MCPWM_CARRIER0_EN_M  (BIT(0))
-#define MCPWM_CARRIER0_EN_V  0x1
-#define MCPWM_CARRIER0_EN_S  0
-
-#define MCPWM_FH0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0068)
-/* MCPWM_FH0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM0B when fault event occurs and timer
- is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH0_B_OST_U  0x00000003
-#define MCPWM_FH0_B_OST_U_M  ((MCPWM_FH0_B_OST_U_V)<<(MCPWM_FH0_B_OST_U_S))
-#define MCPWM_FH0_B_OST_U_V  0x3
-#define MCPWM_FH0_B_OST_U_S  22
-/* MCPWM_FH0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM0B when fault event occurs and timer
- is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH0_B_OST_D  0x00000003
-#define MCPWM_FH0_B_OST_D_M  ((MCPWM_FH0_B_OST_D_V)<<(MCPWM_FH0_B_OST_D_S))
-#define MCPWM_FH0_B_OST_D_V  0x3
-#define MCPWM_FH0_B_OST_D_S  20
-/* MCPWM_FH0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and
- timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH0_B_CBC_U  0x00000003
-#define MCPWM_FH0_B_CBC_U_M  ((MCPWM_FH0_B_CBC_U_V)<<(MCPWM_FH0_B_CBC_U_S))
-#define MCPWM_FH0_B_CBC_U_V  0x3
-#define MCPWM_FH0_B_CBC_U_S  18
-/* MCPWM_FH0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and
- timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH0_B_CBC_D  0x00000003
-#define MCPWM_FH0_B_CBC_D_M  ((MCPWM_FH0_B_CBC_D_V)<<(MCPWM_FH0_B_CBC_D_S))
-#define MCPWM_FH0_B_CBC_D_V  0x3
-#define MCPWM_FH0_B_CBC_D_S  16
-/* MCPWM_FH0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM0A when fault event occurs and timer
- is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH0_A_OST_U  0x00000003
-#define MCPWM_FH0_A_OST_U_M  ((MCPWM_FH0_A_OST_U_V)<<(MCPWM_FH0_A_OST_U_S))
-#define MCPWM_FH0_A_OST_U_V  0x3
-#define MCPWM_FH0_A_OST_U_S  14
-/* MCPWM_FH0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM0A when fault event occurs and timer
- is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH0_A_OST_D  0x00000003
-#define MCPWM_FH0_A_OST_D_M  ((MCPWM_FH0_A_OST_D_V)<<(MCPWM_FH0_A_OST_D_S))
-#define MCPWM_FH0_A_OST_D_V  0x3
-#define MCPWM_FH0_A_OST_D_S  12
-/* MCPWM_FH0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and
- timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH0_A_CBC_U  0x00000003
-#define MCPWM_FH0_A_CBC_U_M  ((MCPWM_FH0_A_CBC_U_V)<<(MCPWM_FH0_A_CBC_U_S))
-#define MCPWM_FH0_A_CBC_U_V  0x3
-#define MCPWM_FH0_A_CBC_U_S  10
-/* MCPWM_FH0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and
- timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH0_A_CBC_D  0x00000003
-#define MCPWM_FH0_A_CBC_D_M  ((MCPWM_FH0_A_CBC_D_V)<<(MCPWM_FH0_A_CBC_D_S))
-#define MCPWM_FH0_A_CBC_D_V  0x3
-#define MCPWM_FH0_A_CBC_D_S  8
-/* MCPWM_FH0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH0_F0_OST  (BIT(7))
-#define MCPWM_FH0_F0_OST_M  (BIT(7))
-#define MCPWM_FH0_F0_OST_V  0x1
-#define MCPWM_FH0_F0_OST_S  7
-/* MCPWM_FH0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH0_F1_OST  (BIT(6))
-#define MCPWM_FH0_F1_OST_M  (BIT(6))
-#define MCPWM_FH0_F1_OST_V  0x1
-#define MCPWM_FH0_F1_OST_S  6
-/* MCPWM_FH0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH0_F2_OST  (BIT(5))
-#define MCPWM_FH0_F2_OST_M  (BIT(5))
-#define MCPWM_FH0_F2_OST_V  0x1
-#define MCPWM_FH0_F2_OST_S  5
-/* MCPWM_FH0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH0_SW_OST  (BIT(4))
-#define MCPWM_FH0_SW_OST_M  (BIT(4))
-#define MCPWM_FH0_SW_OST_V  0x1
-#define MCPWM_FH0_SW_OST_S  4
-/* MCPWM_FH0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
-/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
-#define MCPWM_FH0_F0_CBC  (BIT(3))
-#define MCPWM_FH0_F0_CBC_M  (BIT(3))
-#define MCPWM_FH0_F0_CBC_V  0x1
-#define MCPWM_FH0_F0_CBC_S  3
-/* MCPWM_FH0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
-/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
-#define MCPWM_FH0_F1_CBC  (BIT(2))
-#define MCPWM_FH0_F1_CBC_M  (BIT(2))
-#define MCPWM_FH0_F1_CBC_V  0x1
-#define MCPWM_FH0_F1_CBC_S  2
-/* MCPWM_FH0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
-#define MCPWM_FH0_F2_CBC  (BIT(1))
-#define MCPWM_FH0_F2_CBC_M  (BIT(1))
-#define MCPWM_FH0_F2_CBC_V  0x1
-#define MCPWM_FH0_F2_CBC_S  1
-/* MCPWM_FH0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Enable register for software force cycle-by-cycle mode action.
- 0: disable  1: enable*/
-#define MCPWM_FH0_SW_CBC  (BIT(0))
-#define MCPWM_FH0_SW_CBC_M  (BIT(0))
-#define MCPWM_FH0_SW_CBC_V  0x1
-#define MCPWM_FH0_SW_CBC_S  0
-
-#define MCPWM_FH0_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x006c)
-/* MCPWM_FH0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: A toggle (software negation of value of this bit) triggers a
- one-shot mode action*/
-#define MCPWM_FH0_FORCE_OST  (BIT(4))
-#define MCPWM_FH0_FORCE_OST_M  (BIT(4))
-#define MCPWM_FH0_FORCE_OST_V  0x1
-#define MCPWM_FH0_FORCE_OST_S  4
-/* MCPWM_FH0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
-/*description: A toggle triggers a cycle-by-cycle mode action*/
-#define MCPWM_FH0_FORCE_CBC  (BIT(3))
-#define MCPWM_FH0_FORCE_CBC_M  (BIT(3))
-#define MCPWM_FH0_FORCE_CBC_V  0x1
-#define MCPWM_FH0_FORCE_CBC_S  3
-/* MCPWM_FH0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
-/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
-#define MCPWM_FH0_CBCPULSE  0x00000003
-#define MCPWM_FH0_CBCPULSE_M  ((MCPWM_FH0_CBCPULSE_V)<<(MCPWM_FH0_CBCPULSE_S))
-#define MCPWM_FH0_CBCPULSE_V  0x3
-#define MCPWM_FH0_CBCPULSE_S  1
-/* MCPWM_FH0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: A toggle will clear on going one-shot mode action*/
-#define MCPWM_FH0_CLR_OST  (BIT(0))
-#define MCPWM_FH0_CLR_OST_M  (BIT(0))
-#define MCPWM_FH0_CLR_OST_V  0x1
-#define MCPWM_FH0_CLR_OST_S  0
-
-#define MCPWM_FH0_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0070)
-/* MCPWM_FH0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
-#define MCPWM_FH0_OST_ON  (BIT(1))
-#define MCPWM_FH0_OST_ON_M  (BIT(1))
-#define MCPWM_FH0_OST_ON_V  0x1
-#define MCPWM_FH0_OST_ON_S  1
-/* MCPWM_FH0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
-#define MCPWM_FH0_CBC_ON  (BIT(0))
-#define MCPWM_FH0_CBC_ON_M  (BIT(0))
-#define MCPWM_FH0_CBC_ON_V  0x1
-#define MCPWM_FH0_CBC_ON_S  0
-
-#define MCPWM_GEN1_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0074)
-/* MCPWM_GEN1_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  PWM generator 1 time stamp
- B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
-#define MCPWM_GEN1_B_SHDW_FULL  (BIT(9))
-#define MCPWM_GEN1_B_SHDW_FULL_M  (BIT(9))
-#define MCPWM_GEN1_B_SHDW_FULL_V  0x1
-#define MCPWM_GEN1_B_SHDW_FULL_S  9
-/* MCPWM_GEN1_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  PWM generator 1 time stamp
- A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
-#define MCPWM_GEN1_A_SHDW_FULL  (BIT(8))
-#define MCPWM_GEN1_A_SHDW_FULL_M  (BIT(8))
-#define MCPWM_GEN1_A_SHDW_FULL_V  0x1
-#define MCPWM_GEN1_A_SHDW_FULL_S  8
-/* MCPWM_GEN1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
-/*description: Update method for PWM generator 1 time stamp B's active reg.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_GEN1_B_UPMETHOD  0x0000000F
-#define MCPWM_GEN1_B_UPMETHOD_M  ((MCPWM_GEN1_B_UPMETHOD_V)<<(MCPWM_GEN1_B_UPMETHOD_S))
-#define MCPWM_GEN1_B_UPMETHOD_V  0xF
-#define MCPWM_GEN1_B_UPMETHOD_S  4
-/* MCPWM_GEN1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: Update method for PWM generator 1 time stamp A's active reg.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_GEN1_A_UPMETHOD  0x0000000F
-#define MCPWM_GEN1_A_UPMETHOD_M  ((MCPWM_GEN1_A_UPMETHOD_V)<<(MCPWM_GEN1_A_UPMETHOD_S))
-#define MCPWM_GEN1_A_UPMETHOD_V  0xF
-#define MCPWM_GEN1_A_UPMETHOD_S  0
-
-#define MCPWM_GEN1_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0078)
-/* MCPWM_GEN1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: PWM generator 1 time stamp A's shadow reg*/
-#define MCPWM_GEN1_A  0x0000FFFF
-#define MCPWM_GEN1_A_M  ((MCPWM_GEN1_A_V)<<(MCPWM_GEN1_A_S))
-#define MCPWM_GEN1_A_V  0xFFFF
-#define MCPWM_GEN1_A_S  0
-
-#define MCPWM_GEN1_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x007c)
-/* MCPWM_GEN1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: PWM generator 1 time stamp B's shadow reg*/
-#define MCPWM_GEN1_B  0x0000FFFF
-#define MCPWM_GEN1_B_M  ((MCPWM_GEN1_B_V)<<(MCPWM_GEN1_B_S))
-#define MCPWM_GEN1_B_V  0xFFFF
-#define MCPWM_GEN1_B_S  0
-
-#define MCPWM_GEN1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0080)
-/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
-/*description: Source selection for PWM generate1 event_t1  take effect immediately
-  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
-#define MCPWM_GEN1_T1_SEL  0x00000007
-#define MCPWM_GEN1_T1_SEL_M  ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S))
-#define MCPWM_GEN1_T1_SEL_V  0x7
-#define MCPWM_GEN1_T1_SEL_S  7
-/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
-/*description: Source selection for PWM generate1 event_t0  take effect immediately
-  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
-#define MCPWM_GEN1_T0_SEL  0x00000007
-#define MCPWM_GEN1_T0_SEL_M  ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S))
-#define MCPWM_GEN1_T0_SEL_V  0x7
-#define MCPWM_GEN1_T0_SEL_S  4
-/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: Update method for PWM generate1's active reg of configuration.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
-#define MCPWM_GEN1_CFG_UPMETHOD  0x0000000F
-#define MCPWM_GEN1_CFG_UPMETHOD_M  ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S))
-#define MCPWM_GEN1_CFG_UPMETHOD_V  0xF
-#define MCPWM_GEN1_CFG_UPMETHOD_S  0
-
-#define MCPWM_GEN1_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x0084)
-/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: Non-continuous immediate software force mode for PWM1B  0: disabled
-  1: low  2: high  3: disabled*/
-#define MCPWM_GEN1_B_NCIFORCE_MODE  0x00000003
-#define MCPWM_GEN1_B_NCIFORCE_MODE_M  ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S))
-#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x3
-#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
-/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: Non-continuous immediate software force trigger for PWM1B  a
- toggle will trigger a force event*/
-#define MCPWM_GEN1_B_NCIFORCE  (BIT(13))
-#define MCPWM_GEN1_B_NCIFORCE_M  (BIT(13))
-#define MCPWM_GEN1_B_NCIFORCE_V  0x1
-#define MCPWM_GEN1_B_NCIFORCE_S  13
-/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
-/*description: Non-continuous immediate software force mode for PWM1A  0: disabled
-  1: low  2: high  3: disabled*/
-#define MCPWM_GEN1_A_NCIFORCE_MODE  0x00000003
-#define MCPWM_GEN1_A_NCIFORCE_MODE_M  ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S))
-#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x3
-#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
-/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: Non-continuous immediate software force trigger for PWM1A  a
- toggle will trigger a force event*/
-#define MCPWM_GEN1_A_NCIFORCE  (BIT(10))
-#define MCPWM_GEN1_A_NCIFORCE_M  (BIT(10))
-#define MCPWM_GEN1_A_NCIFORCE_V  0x1
-#define MCPWM_GEN1_A_NCIFORCE_S  10
-/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Continuous software force mode for PWM1B. 0: disabled  1: low
-  2: high  3: disabled*/
-#define MCPWM_GEN1_B_CNTUFORCE_MODE  0x00000003
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S))
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x3
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
-/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Continuous software force mode for PWM1A. 0: disabled  1: low
-  2: high  3: disabled*/
-#define MCPWM_GEN1_A_CNTUFORCE_MODE  0x00000003
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S))
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x3
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
-/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
-/*description: Update method for continuous software force of PWM generator1.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD  0x0000003F
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S))
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x3F
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
-
-#define MCPWM_GEN1_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0088)
-/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event_t1 when timer decreasing.
- 0: no change  1: low  2: high  3: toggle*/
-#define MCPWM_GEN1_A_DT1  0x00000003
-#define MCPWM_GEN1_A_DT1_M  ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S))
-#define MCPWM_GEN1_A_DT1_V  0x3
-#define MCPWM_GEN1_A_DT1_S  22
-/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event_t0 when timer decreasing*/
-#define MCPWM_GEN1_A_DT0  0x00000003
-#define MCPWM_GEN1_A_DT0_M  ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S))
-#define MCPWM_GEN1_A_DT0_V  0x3
-#define MCPWM_GEN1_A_DT0_S  20
-/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event TEB when timer decreasing*/
-#define MCPWM_GEN1_A_DTEB  0x00000003
-#define MCPWM_GEN1_A_DTEB_M  ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S))
-#define MCPWM_GEN1_A_DTEB_V  0x3
-#define MCPWM_GEN1_A_DTEB_S  18
-/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event TEA when timer decreasing*/
-#define MCPWM_GEN1_A_DTEA  0x00000003
-#define MCPWM_GEN1_A_DTEA_M  ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S))
-#define MCPWM_GEN1_A_DTEA_V  0x3
-#define MCPWM_GEN1_A_DTEA_S  16
-/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event TEP when timer decreasing*/
-#define MCPWM_GEN1_A_DTEP  0x00000003
-#define MCPWM_GEN1_A_DTEP_M  ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S))
-#define MCPWM_GEN1_A_DTEP_V  0x3
-#define MCPWM_GEN1_A_DTEP_S  14
-/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event TEZ when timer decreasing*/
-#define MCPWM_GEN1_A_DTEZ  0x00000003
-#define MCPWM_GEN1_A_DTEZ_M  ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S))
-#define MCPWM_GEN1_A_DTEZ_V  0x3
-#define MCPWM_GEN1_A_DTEZ_S  12
-/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event_t1 when timer increasing*/
-#define MCPWM_GEN1_A_UT1  0x00000003
-#define MCPWM_GEN1_A_UT1_M  ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S))
-#define MCPWM_GEN1_A_UT1_V  0x3
-#define MCPWM_GEN1_A_UT1_S  10
-/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event_t0 when timer increasing*/
-#define MCPWM_GEN1_A_UT0  0x00000003
-#define MCPWM_GEN1_A_UT0_M  ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S))
-#define MCPWM_GEN1_A_UT0_V  0x3
-#define MCPWM_GEN1_A_UT0_S  8
-/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event TEB when timer increasing*/
-#define MCPWM_GEN1_A_UTEB  0x00000003
-#define MCPWM_GEN1_A_UTEB_M  ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S))
-#define MCPWM_GEN1_A_UTEB_V  0x3
-#define MCPWM_GEN1_A_UTEB_S  6
-/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event TEA when timer increasing*/
-#define MCPWM_GEN1_A_UTEA  0x00000003
-#define MCPWM_GEN1_A_UTEA_M  ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S))
-#define MCPWM_GEN1_A_UTEA_V  0x3
-#define MCPWM_GEN1_A_UTEA_S  4
-/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event TEP when timer increasing*/
-#define MCPWM_GEN1_A_UTEP  0x00000003
-#define MCPWM_GEN1_A_UTEP_M  ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S))
-#define MCPWM_GEN1_A_UTEP_V  0x3
-#define MCPWM_GEN1_A_UTEP_S  2
-/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: Action on PWM1A triggered by event TEZ when timer increasing*/
-#define MCPWM_GEN1_A_UTEZ  0x00000003
-#define MCPWM_GEN1_A_UTEZ_M  ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S))
-#define MCPWM_GEN1_A_UTEZ_V  0x3
-#define MCPWM_GEN1_A_UTEZ_S  0
-
-#define MCPWM_GEN1_B_REG(i)          (REG_MCPWM_BASE(i) + 0x008c)
-/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event_t1 when timer decreasing.
- 0: no change  1: low  2: high  3: toggle*/
-#define MCPWM_GEN1_B_DT1  0x00000003
-#define MCPWM_GEN1_B_DT1_M  ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S))
-#define MCPWM_GEN1_B_DT1_V  0x3
-#define MCPWM_GEN1_B_DT1_S  22
-/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event_t0 when timer decreasing*/
-#define MCPWM_GEN1_B_DT0  0x00000003
-#define MCPWM_GEN1_B_DT0_M  ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S))
-#define MCPWM_GEN1_B_DT0_V  0x3
-#define MCPWM_GEN1_B_DT0_S  20
-/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event TEB when timer decreasing*/
-#define MCPWM_GEN1_B_DTEB  0x00000003
-#define MCPWM_GEN1_B_DTEB_M  ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S))
-#define MCPWM_GEN1_B_DTEB_V  0x3
-#define MCPWM_GEN1_B_DTEB_S  18
-/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event TEA when timer decreasing*/
-#define MCPWM_GEN1_B_DTEA  0x00000003
-#define MCPWM_GEN1_B_DTEA_M  ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S))
-#define MCPWM_GEN1_B_DTEA_V  0x3
-#define MCPWM_GEN1_B_DTEA_S  16
-/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event TEP when timer decreasing*/
-#define MCPWM_GEN1_B_DTEP  0x00000003
-#define MCPWM_GEN1_B_DTEP_M  ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S))
-#define MCPWM_GEN1_B_DTEP_V  0x3
-#define MCPWM_GEN1_B_DTEP_S  14
-/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event TEZ when timer decreasing*/
-#define MCPWM_GEN1_B_DTEZ  0x00000003
-#define MCPWM_GEN1_B_DTEZ_M  ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S))
-#define MCPWM_GEN1_B_DTEZ_V  0x3
-#define MCPWM_GEN1_B_DTEZ_S  12
-/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event_t1 when timer increasing*/
-#define MCPWM_GEN1_B_UT1  0x00000003
-#define MCPWM_GEN1_B_UT1_M  ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S))
-#define MCPWM_GEN1_B_UT1_V  0x3
-#define MCPWM_GEN1_B_UT1_S  10
-/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event_t0 when timer increasing*/
-#define MCPWM_GEN1_B_UT0  0x00000003
-#define MCPWM_GEN1_B_UT0_M  ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S))
-#define MCPWM_GEN1_B_UT0_V  0x3
-#define MCPWM_GEN1_B_UT0_S  8
-/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event TEB when timer increasing*/
-#define MCPWM_GEN1_B_UTEB  0x00000003
-#define MCPWM_GEN1_B_UTEB_M  ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S))
-#define MCPWM_GEN1_B_UTEB_V  0x3
-#define MCPWM_GEN1_B_UTEB_S  6
-/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event TEA when timer increasing*/
-#define MCPWM_GEN1_B_UTEA  0x00000003
-#define MCPWM_GEN1_B_UTEA_M  ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S))
-#define MCPWM_GEN1_B_UTEA_V  0x3
-#define MCPWM_GEN1_B_UTEA_S  4
-/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event TEP when timer increasing*/
-#define MCPWM_GEN1_B_UTEP  0x00000003
-#define MCPWM_GEN1_B_UTEP_M  ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S))
-#define MCPWM_GEN1_B_UTEP_V  0x3
-#define MCPWM_GEN1_B_UTEP_S  2
-/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: Action on PWM1B triggered by event TEZ when timer increasing*/
-#define MCPWM_GEN1_B_UTEZ  0x00000003
-#define MCPWM_GEN1_B_UTEZ_M  ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S))
-#define MCPWM_GEN1_B_UTEZ_V  0x3
-#define MCPWM_GEN1_B_UTEZ_S  0
-
-#define MCPWM_DT1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0090)
-/* MCPWM_DT1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Dead time generator 1 clock selection. 0: PWM_clk  1: PT_clk*/
-#define MCPWM_DT1_CLK_SEL  (BIT(17))
-#define MCPWM_DT1_CLK_SEL_M  (BIT(17))
-#define MCPWM_DT1_CLK_SEL_V  0x1
-#define MCPWM_DT1_CLK_SEL_S  17
-/* MCPWM_DT1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: S0 in documentation*/
-#define MCPWM_DT1_B_OUTBYPASS  (BIT(16))
-#define MCPWM_DT1_B_OUTBYPASS_M  (BIT(16))
-#define MCPWM_DT1_B_OUTBYPASS_V  0x1
-#define MCPWM_DT1_B_OUTBYPASS_S  16
-/* MCPWM_DT1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
-/*description: S1 in documentation*/
-#define MCPWM_DT1_A_OUTBYPASS  (BIT(15))
-#define MCPWM_DT1_A_OUTBYPASS_M  (BIT(15))
-#define MCPWM_DT1_A_OUTBYPASS_V  0x1
-#define MCPWM_DT1_A_OUTBYPASS_S  15
-/* MCPWM_DT1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: S3 in documentation*/
-#define MCPWM_DT1_FED_OUTINVERT  (BIT(14))
-#define MCPWM_DT1_FED_OUTINVERT_M  (BIT(14))
-#define MCPWM_DT1_FED_OUTINVERT_V  0x1
-#define MCPWM_DT1_FED_OUTINVERT_S  14
-/* MCPWM_DT1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: S2 in documentation*/
-#define MCPWM_DT1_RED_OUTINVERT  (BIT(13))
-#define MCPWM_DT1_RED_OUTINVERT_M  (BIT(13))
-#define MCPWM_DT1_RED_OUTINVERT_V  0x1
-#define MCPWM_DT1_RED_OUTINVERT_S  13
-/* MCPWM_DT1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: S5 in documentation*/
-#define MCPWM_DT1_FED_INSEL  (BIT(12))
-#define MCPWM_DT1_FED_INSEL_M  (BIT(12))
-#define MCPWM_DT1_FED_INSEL_V  0x1
-#define MCPWM_DT1_FED_INSEL_S  12
-/* MCPWM_DT1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: S4 in documentation*/
-#define MCPWM_DT1_RED_INSEL  (BIT(11))
-#define MCPWM_DT1_RED_INSEL_M  (BIT(11))
-#define MCPWM_DT1_RED_INSEL_V  0x1
-#define MCPWM_DT1_RED_INSEL_S  11
-/* MCPWM_DT1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: S7 in documentation*/
-#define MCPWM_DT1_B_OUTSWAP  (BIT(10))
-#define MCPWM_DT1_B_OUTSWAP_M  (BIT(10))
-#define MCPWM_DT1_B_OUTSWAP_V  0x1
-#define MCPWM_DT1_B_OUTSWAP_S  10
-/* MCPWM_DT1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: S6 in documentation*/
-#define MCPWM_DT1_A_OUTSWAP  (BIT(9))
-#define MCPWM_DT1_A_OUTSWAP_M  (BIT(9))
-#define MCPWM_DT1_A_OUTSWAP_V  0x1
-#define MCPWM_DT1_A_OUTSWAP_S  9
-/* MCPWM_DT1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
- on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
-#define MCPWM_DT1_DEB_MODE  (BIT(8))
-#define MCPWM_DT1_DEB_MODE_M  (BIT(8))
-#define MCPWM_DT1_DEB_MODE_V  0x1
-#define MCPWM_DT1_DEB_MODE_S  8
-/* MCPWM_DT1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
-/*description: Update method for RED (rising edge delay) active reg. 0: immediate
-  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_DT1_RED_UPMETHOD  0x0000000F
-#define MCPWM_DT1_RED_UPMETHOD_M  ((MCPWM_DT1_RED_UPMETHOD_V)<<(MCPWM_DT1_RED_UPMETHOD_S))
-#define MCPWM_DT1_RED_UPMETHOD_V  0xF
-#define MCPWM_DT1_RED_UPMETHOD_S  4
-/* MCPWM_DT1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: Update method for FED (falling edge delay) active reg. 0: immediate
-  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_DT1_FED_UPMETHOD  0x0000000F
-#define MCPWM_DT1_FED_UPMETHOD_M  ((MCPWM_DT1_FED_UPMETHOD_V)<<(MCPWM_DT1_FED_UPMETHOD_S))
-#define MCPWM_DT1_FED_UPMETHOD_V  0xF
-#define MCPWM_DT1_FED_UPMETHOD_S  0
-
-#define MCPWM_DT1_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0094)
-/* MCPWM_DT1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: Shadow reg for FED*/
-#define MCPWM_DT1_FED  0x0000FFFF
-#define MCPWM_DT1_FED_M  ((MCPWM_DT1_FED_V)<<(MCPWM_DT1_FED_S))
-#define MCPWM_DT1_FED_V  0xFFFF
-#define MCPWM_DT1_FED_S  0
-
-#define MCPWM_DT1_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0098)
-/* MCPWM_DT1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: Shadow reg for RED*/
-#define MCPWM_DT1_RED  0x0000FFFF
-#define MCPWM_DT1_RED_M  ((MCPWM_DT1_RED_V)<<(MCPWM_DT1_RED_S))
-#define MCPWM_DT1_RED_V  0xFFFF
-#define MCPWM_DT1_RED_S  0
-
-#define MCPWM_CARRIER1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x009c)
-/* MCPWM_CARRIER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: When set  invert the input of PWM1A and PWM1B for this submodule*/
-#define MCPWM_CARRIER1_IN_INVERT  (BIT(13))
-#define MCPWM_CARRIER1_IN_INVERT_M  (BIT(13))
-#define MCPWM_CARRIER1_IN_INVERT_V  0x1
-#define MCPWM_CARRIER1_IN_INVERT_S  13
-/* MCPWM_CARRIER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: When set  invert the output of PWM1A and PWM1B for this submodule*/
-#define MCPWM_CARRIER1_OUT_INVERT  (BIT(12))
-#define MCPWM_CARRIER1_OUT_INVERT_M  (BIT(12))
-#define MCPWM_CARRIER1_OUT_INVERT_V  0x1
-#define MCPWM_CARRIER1_OUT_INVERT_S  12
-/* MCPWM_CARRIER1_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
-/*description: Width of the fist pulse in number of periods of the carrier*/
-#define MCPWM_CARRIER1_OSHWTH  0x0000000F
-#define MCPWM_CARRIER1_OSHWTH_M  ((MCPWM_CARRIER1_OSHWTH_V)<<(MCPWM_CARRIER1_OSHWTH_S))
-#define MCPWM_CARRIER1_OSHWTH_V  0xF
-#define MCPWM_CARRIER1_OSHWTH_S  8
-/* MCPWM_CARRIER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
-/*description: Carrier duty selection. Duty = PWM_CARRIER1_DUTY / 8*/
-#define MCPWM_CARRIER1_DUTY  0x00000007
-#define MCPWM_CARRIER1_DUTY_M  ((MCPWM_CARRIER1_DUTY_V)<<(MCPWM_CARRIER1_DUTY_S))
-#define MCPWM_CARRIER1_DUTY_V  0x7
-#define MCPWM_CARRIER1_DUTY_S  5
-/* MCPWM_CARRIER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
-/*description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk
- = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)*/
-#define MCPWM_CARRIER1_PRESCALE  0x0000000F
-#define MCPWM_CARRIER1_PRESCALE_M  ((MCPWM_CARRIER1_PRESCALE_V)<<(MCPWM_CARRIER1_PRESCALE_S))
-#define MCPWM_CARRIER1_PRESCALE_V  0xF
-#define MCPWM_CARRIER1_PRESCALE_S  1
-/* MCPWM_CARRIER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: When set  carrier1 function is enabled. When cleared  carrier1 is bypassed*/
-#define MCPWM_CARRIER1_EN  (BIT(0))
-#define MCPWM_CARRIER1_EN_M  (BIT(0))
-#define MCPWM_CARRIER1_EN_V  0x1
-#define MCPWM_CARRIER1_EN_S  0
-
-#define MCPWM_FH1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00a0)
-/* MCPWM_FH1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM1B when fault event occurs and timer
- is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH1_B_OST_U  0x00000003
-#define MCPWM_FH1_B_OST_U_M  ((MCPWM_FH1_B_OST_U_V)<<(MCPWM_FH1_B_OST_U_S))
-#define MCPWM_FH1_B_OST_U_V  0x3
-#define MCPWM_FH1_B_OST_U_S  22
-/* MCPWM_FH1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM1B when fault event occurs and timer
- is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH1_B_OST_D  0x00000003
-#define MCPWM_FH1_B_OST_D_M  ((MCPWM_FH1_B_OST_D_V)<<(MCPWM_FH1_B_OST_D_S))
-#define MCPWM_FH1_B_OST_D_V  0x3
-#define MCPWM_FH1_B_OST_D_S  20
-/* MCPWM_FH1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and
- timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH1_B_CBC_U  0x00000003
-#define MCPWM_FH1_B_CBC_U_M  ((MCPWM_FH1_B_CBC_U_V)<<(MCPWM_FH1_B_CBC_U_S))
-#define MCPWM_FH1_B_CBC_U_V  0x3
-#define MCPWM_FH1_B_CBC_U_S  18
-/* MCPWM_FH1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and
- timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH1_B_CBC_D  0x00000003
-#define MCPWM_FH1_B_CBC_D_M  ((MCPWM_FH1_B_CBC_D_V)<<(MCPWM_FH1_B_CBC_D_S))
-#define MCPWM_FH1_B_CBC_D_V  0x3
-#define MCPWM_FH1_B_CBC_D_S  16
-/* MCPWM_FH1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM1A when fault event occurs and timer
- is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH1_A_OST_U  0x00000003
-#define MCPWM_FH1_A_OST_U_M  ((MCPWM_FH1_A_OST_U_V)<<(MCPWM_FH1_A_OST_U_S))
-#define MCPWM_FH1_A_OST_U_V  0x3
-#define MCPWM_FH1_A_OST_U_S  14
-/* MCPWM_FH1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM1A when fault event occurs and timer
- is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH1_A_OST_D  0x00000003
-#define MCPWM_FH1_A_OST_D_M  ((MCPWM_FH1_A_OST_D_V)<<(MCPWM_FH1_A_OST_D_S))
-#define MCPWM_FH1_A_OST_D_V  0x3
-#define MCPWM_FH1_A_OST_D_S  12
-/* MCPWM_FH1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and
- timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH1_A_CBC_U  0x00000003
-#define MCPWM_FH1_A_CBC_U_M  ((MCPWM_FH1_A_CBC_U_V)<<(MCPWM_FH1_A_CBC_U_S))
-#define MCPWM_FH1_A_CBC_U_V  0x3
-#define MCPWM_FH1_A_CBC_U_S  10
-/* MCPWM_FH1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and
- timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH1_A_CBC_D  0x00000003
-#define MCPWM_FH1_A_CBC_D_M  ((MCPWM_FH1_A_CBC_D_V)<<(MCPWM_FH1_A_CBC_D_S))
-#define MCPWM_FH1_A_CBC_D_V  0x3
-#define MCPWM_FH1_A_CBC_D_S  8
-/* MCPWM_FH1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH1_F0_OST  (BIT(7))
-#define MCPWM_FH1_F0_OST_M  (BIT(7))
-#define MCPWM_FH1_F0_OST_V  0x1
-#define MCPWM_FH1_F0_OST_S  7
-/* MCPWM_FH1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH1_F1_OST  (BIT(6))
-#define MCPWM_FH1_F1_OST_M  (BIT(6))
-#define MCPWM_FH1_F1_OST_V  0x1
-#define MCPWM_FH1_F1_OST_S  6
-/* MCPWM_FH1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH1_F2_OST  (BIT(5))
-#define MCPWM_FH1_F2_OST_M  (BIT(5))
-#define MCPWM_FH1_F2_OST_V  0x1
-#define MCPWM_FH1_F2_OST_S  5
-/* MCPWM_FH1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH1_SW_OST  (BIT(4))
-#define MCPWM_FH1_SW_OST_M  (BIT(4))
-#define MCPWM_FH1_SW_OST_V  0x1
-#define MCPWM_FH1_SW_OST_S  4
-/* MCPWM_FH1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
-/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
-#define MCPWM_FH1_F0_CBC  (BIT(3))
-#define MCPWM_FH1_F0_CBC_M  (BIT(3))
-#define MCPWM_FH1_F0_CBC_V  0x1
-#define MCPWM_FH1_F0_CBC_S  3
-/* MCPWM_FH1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
-/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
-#define MCPWM_FH1_F1_CBC  (BIT(2))
-#define MCPWM_FH1_F1_CBC_M  (BIT(2))
-#define MCPWM_FH1_F1_CBC_V  0x1
-#define MCPWM_FH1_F1_CBC_S  2
-/* MCPWM_FH1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
-#define MCPWM_FH1_F2_CBC  (BIT(1))
-#define MCPWM_FH1_F2_CBC_M  (BIT(1))
-#define MCPWM_FH1_F2_CBC_V  0x1
-#define MCPWM_FH1_F2_CBC_S  1
-/* MCPWM_FH1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Enable register for software force cycle-by-cycle mode action.
- 0: disable  1: enable*/
-#define MCPWM_FH1_SW_CBC  (BIT(0))
-#define MCPWM_FH1_SW_CBC_M  (BIT(0))
-#define MCPWM_FH1_SW_CBC_V  0x1
-#define MCPWM_FH1_SW_CBC_S  0
-
-#define MCPWM_FH1_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x00a4)
-/* MCPWM_FH1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: A toggle (software negation of value of this bit) triggers a
- one-shot mode action*/
-#define MCPWM_FH1_FORCE_OST  (BIT(4))
-#define MCPWM_FH1_FORCE_OST_M  (BIT(4))
-#define MCPWM_FH1_FORCE_OST_V  0x1
-#define MCPWM_FH1_FORCE_OST_S  4
-/* MCPWM_FH1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
-/*description: A toggle triggers a cycle-by-cycle mode action*/
-#define MCPWM_FH1_FORCE_CBC  (BIT(3))
-#define MCPWM_FH1_FORCE_CBC_M  (BIT(3))
-#define MCPWM_FH1_FORCE_CBC_V  0x1
-#define MCPWM_FH1_FORCE_CBC_S  3
-/* MCPWM_FH1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
-/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
-#define MCPWM_FH1_CBCPULSE  0x00000003
-#define MCPWM_FH1_CBCPULSE_M  ((MCPWM_FH1_CBCPULSE_V)<<(MCPWM_FH1_CBCPULSE_S))
-#define MCPWM_FH1_CBCPULSE_V  0x3
-#define MCPWM_FH1_CBCPULSE_S  1
-/* MCPWM_FH1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: A toggle will clear on going one-shot mode action*/
-#define MCPWM_FH1_CLR_OST  (BIT(0))
-#define MCPWM_FH1_CLR_OST_M  (BIT(0))
-#define MCPWM_FH1_CLR_OST_V  0x1
-#define MCPWM_FH1_CLR_OST_S  0
-
-#define MCPWM_FH1_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x00a8)
-/* MCPWM_FH1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
-#define MCPWM_FH1_OST_ON  (BIT(1))
-#define MCPWM_FH1_OST_ON_M  (BIT(1))
-#define MCPWM_FH1_OST_ON_V  0x1
-#define MCPWM_FH1_OST_ON_S  1
-/* MCPWM_FH1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
-#define MCPWM_FH1_CBC_ON  (BIT(0))
-#define MCPWM_FH1_CBC_ON_M  (BIT(0))
-#define MCPWM_FH1_CBC_ON_V  0x1
-#define MCPWM_FH1_CBC_ON_S  0
-
-#define MCPWM_GEN2_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00ac)
-/* MCPWM_GEN2_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  PWM generator 2 time stamp
- B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
-#define MCPWM_GEN2_B_SHDW_FULL  (BIT(9))
-#define MCPWM_GEN2_B_SHDW_FULL_M  (BIT(9))
-#define MCPWM_GEN2_B_SHDW_FULL_V  0x1
-#define MCPWM_GEN2_B_SHDW_FULL_S  9
-/* MCPWM_GEN2_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  PWM generator 2 time stamp
- A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
-#define MCPWM_GEN2_A_SHDW_FULL  (BIT(8))
-#define MCPWM_GEN2_A_SHDW_FULL_M  (BIT(8))
-#define MCPWM_GEN2_A_SHDW_FULL_V  0x1
-#define MCPWM_GEN2_A_SHDW_FULL_S  8
-/* MCPWM_GEN2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
-/*description: Update method for PWM generator 2 time stamp B's active reg.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_GEN2_B_UPMETHOD  0x0000000F
-#define MCPWM_GEN2_B_UPMETHOD_M  ((MCPWM_GEN2_B_UPMETHOD_V)<<(MCPWM_GEN2_B_UPMETHOD_S))
-#define MCPWM_GEN2_B_UPMETHOD_V  0xF
-#define MCPWM_GEN2_B_UPMETHOD_S  4
-/* MCPWM_GEN2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: Update method for PWM generator 2 time stamp A's active reg.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_GEN2_A_UPMETHOD  0x0000000F
-#define MCPWM_GEN2_A_UPMETHOD_M  ((MCPWM_GEN2_A_UPMETHOD_V)<<(MCPWM_GEN2_A_UPMETHOD_S))
-#define MCPWM_GEN2_A_UPMETHOD_V  0xF
-#define MCPWM_GEN2_A_UPMETHOD_S  0
-
-#define MCPWM_GEN2_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x00b0)
-/* MCPWM_GEN2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: PWM generator 2 time stamp A's shadow reg*/
-#define MCPWM_GEN2_A  0x0000FFFF
-#define MCPWM_GEN2_A_M  ((MCPWM_GEN2_A_V)<<(MCPWM_GEN2_A_S))
-#define MCPWM_GEN2_A_V  0xFFFF
-#define MCPWM_GEN2_A_S  0
-
-#define MCPWM_GEN2_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x00b4)
-/* MCPWM_GEN2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: PWM generator 2 time stamp B's shadow reg*/
-#define MCPWM_GEN2_B  0x0000FFFF
-#define MCPWM_GEN2_B_M  ((MCPWM_GEN2_B_V)<<(MCPWM_GEN2_B_S))
-#define MCPWM_GEN2_B_V  0xFFFF
-#define MCPWM_GEN2_B_S  0
-
-#define MCPWM_GEN2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00b8)
-/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
-/*description: Source selection for PWM generate2 event_t1  take effect immediately
-  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
-#define MCPWM_GEN2_T1_SEL  0x00000007
-#define MCPWM_GEN2_T1_SEL_M  ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S))
-#define MCPWM_GEN2_T1_SEL_V  0x7
-#define MCPWM_GEN2_T1_SEL_S  7
-/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
-/*description: Source selection for PWM generate2 event_t0  take effect immediately
-  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
-#define MCPWM_GEN2_T0_SEL  0x00000007
-#define MCPWM_GEN2_T0_SEL_M  ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S))
-#define MCPWM_GEN2_T0_SEL_V  0x7
-#define MCPWM_GEN2_T0_SEL_S  4
-/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: Update method for PWM generate2's active reg of configuration.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
-#define MCPWM_GEN2_CFG_UPMETHOD  0x0000000F
-#define MCPWM_GEN2_CFG_UPMETHOD_M  ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S))
-#define MCPWM_GEN2_CFG_UPMETHOD_V  0xF
-#define MCPWM_GEN2_CFG_UPMETHOD_S  0
-
-#define MCPWM_GEN2_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x00bc)
-/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: Non-continuous immediate software force mode for PWM2B  0: disabled
-  1: low  2: high  3: disabled*/
-#define MCPWM_GEN2_B_NCIFORCE_MODE  0x00000003
-#define MCPWM_GEN2_B_NCIFORCE_MODE_M  ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S))
-#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x3
-#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
-/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: Non-continuous immediate software force trigger for PWM2B  a
- toggle will trigger a force event*/
-#define MCPWM_GEN2_B_NCIFORCE  (BIT(13))
-#define MCPWM_GEN2_B_NCIFORCE_M  (BIT(13))
-#define MCPWM_GEN2_B_NCIFORCE_V  0x1
-#define MCPWM_GEN2_B_NCIFORCE_S  13
-/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
-/*description: Non-continuous immediate software force mode for PWM2A  0: disabled
-  1: low  2: high  3: disabled*/
-#define MCPWM_GEN2_A_NCIFORCE_MODE  0x00000003
-#define MCPWM_GEN2_A_NCIFORCE_MODE_M  ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S))
-#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x3
-#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
-/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: Non-continuous immediate software force trigger for PWM2A  a
- toggle will trigger a force event*/
-#define MCPWM_GEN2_A_NCIFORCE  (BIT(10))
-#define MCPWM_GEN2_A_NCIFORCE_M  (BIT(10))
-#define MCPWM_GEN2_A_NCIFORCE_V  0x1
-#define MCPWM_GEN2_A_NCIFORCE_S  10
-/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Continuous software force mode for PWM2B. 0: disabled  1: low
-  2: high  3: disabled*/
-#define MCPWM_GEN2_B_CNTUFORCE_MODE  0x00000003
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S))
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x3
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
-/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Continuous software force mode for PWM2A. 0: disabled  1: low
-  2: high  3: disabled*/
-#define MCPWM_GEN2_A_CNTUFORCE_MODE  0x00000003
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S))
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x3
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
-/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
-/*description: Update method for continuous software force of PWM generator2.
- 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD  0x0000003F
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S))
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x3F
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
-
-#define MCPWM_GEN2_A_REG(i)          (REG_MCPWM_BASE(i) + 0x00c0)
-/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event_t1 when timer decreasing.
- 0: no change  1: low  2: high  3: toggle*/
-#define MCPWM_GEN2_A_DT1  0x00000003
-#define MCPWM_GEN2_A_DT1_M  ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S))
-#define MCPWM_GEN2_A_DT1_V  0x3
-#define MCPWM_GEN2_A_DT1_S  22
-/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event_t0 when timer decreasing*/
-#define MCPWM_GEN2_A_DT0  0x00000003
-#define MCPWM_GEN2_A_DT0_M  ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S))
-#define MCPWM_GEN2_A_DT0_V  0x3
-#define MCPWM_GEN2_A_DT0_S  20
-/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event TEB when timer decreasing*/
-#define MCPWM_GEN2_A_DTEB  0x00000003
-#define MCPWM_GEN2_A_DTEB_M  ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S))
-#define MCPWM_GEN2_A_DTEB_V  0x3
-#define MCPWM_GEN2_A_DTEB_S  18
-/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event TEA when timer decreasing*/
-#define MCPWM_GEN2_A_DTEA  0x00000003
-#define MCPWM_GEN2_A_DTEA_M  ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S))
-#define MCPWM_GEN2_A_DTEA_V  0x3
-#define MCPWM_GEN2_A_DTEA_S  16
-/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event TEP when timer decreasing*/
-#define MCPWM_GEN2_A_DTEP  0x00000003
-#define MCPWM_GEN2_A_DTEP_M  ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S))
-#define MCPWM_GEN2_A_DTEP_V  0x3
-#define MCPWM_GEN2_A_DTEP_S  14
-/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event TEZ when timer decreasing*/
-#define MCPWM_GEN2_A_DTEZ  0x00000003
-#define MCPWM_GEN2_A_DTEZ_M  ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S))
-#define MCPWM_GEN2_A_DTEZ_V  0x3
-#define MCPWM_GEN2_A_DTEZ_S  12
-/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event_t1 when timer increasing*/
-#define MCPWM_GEN2_A_UT1  0x00000003
-#define MCPWM_GEN2_A_UT1_M  ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S))
-#define MCPWM_GEN2_A_UT1_V  0x3
-#define MCPWM_GEN2_A_UT1_S  10
-/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event_t0 when timer increasing*/
-#define MCPWM_GEN2_A_UT0  0x00000003
-#define MCPWM_GEN2_A_UT0_M  ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S))
-#define MCPWM_GEN2_A_UT0_V  0x3
-#define MCPWM_GEN2_A_UT0_S  8
-/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event TEB when timer increasing*/
-#define MCPWM_GEN2_A_UTEB  0x00000003
-#define MCPWM_GEN2_A_UTEB_M  ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S))
-#define MCPWM_GEN2_A_UTEB_V  0x3
-#define MCPWM_GEN2_A_UTEB_S  6
-/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event TEA when timer increasing*/
-#define MCPWM_GEN2_A_UTEA  0x00000003
-#define MCPWM_GEN2_A_UTEA_M  ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S))
-#define MCPWM_GEN2_A_UTEA_V  0x3
-#define MCPWM_GEN2_A_UTEA_S  4
-/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event TEP when timer increasing*/
-#define MCPWM_GEN2_A_UTEP  0x00000003
-#define MCPWM_GEN2_A_UTEP_M  ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S))
-#define MCPWM_GEN2_A_UTEP_V  0x3
-#define MCPWM_GEN2_A_UTEP_S  2
-/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: Action on PWM2A triggered by event TEZ when timer increasing*/
-#define MCPWM_GEN2_A_UTEZ  0x00000003
-#define MCPWM_GEN2_A_UTEZ_M  ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S))
-#define MCPWM_GEN2_A_UTEZ_V  0x3
-#define MCPWM_GEN2_A_UTEZ_S  0
-
-#define MCPWM_GEN2_B_REG(i)          (REG_MCPWM_BASE(i) + 0x00c4)
-/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event_t1 when timer decreasing.
- 0: no change  1: low  2: high  3: toggle*/
-#define MCPWM_GEN2_B_DT1  0x00000003
-#define MCPWM_GEN2_B_DT1_M  ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S))
-#define MCPWM_GEN2_B_DT1_V  0x3
-#define MCPWM_GEN2_B_DT1_S  22
-/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event_t0 when timer decreasing*/
-#define MCPWM_GEN2_B_DT0  0x00000003
-#define MCPWM_GEN2_B_DT0_M  ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S))
-#define MCPWM_GEN2_B_DT0_V  0x3
-#define MCPWM_GEN2_B_DT0_S  20
-/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event TEB when timer decreasing*/
-#define MCPWM_GEN2_B_DTEB  0x00000003
-#define MCPWM_GEN2_B_DTEB_M  ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S))
-#define MCPWM_GEN2_B_DTEB_V  0x3
-#define MCPWM_GEN2_B_DTEB_S  18
-/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event TEA when timer decreasing*/
-#define MCPWM_GEN2_B_DTEA  0x00000003
-#define MCPWM_GEN2_B_DTEA_M  ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S))
-#define MCPWM_GEN2_B_DTEA_V  0x3
-#define MCPWM_GEN2_B_DTEA_S  16
-/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event TEP when timer decreasing*/
-#define MCPWM_GEN2_B_DTEP  0x00000003
-#define MCPWM_GEN2_B_DTEP_M  ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S))
-#define MCPWM_GEN2_B_DTEP_V  0x3
-#define MCPWM_GEN2_B_DTEP_S  14
-/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event TEZ when timer decreasing*/
-#define MCPWM_GEN2_B_DTEZ  0x00000003
-#define MCPWM_GEN2_B_DTEZ_M  ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S))
-#define MCPWM_GEN2_B_DTEZ_V  0x3
-#define MCPWM_GEN2_B_DTEZ_S  12
-/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event_t1 when timer increasing*/
-#define MCPWM_GEN2_B_UT1  0x00000003
-#define MCPWM_GEN2_B_UT1_M  ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S))
-#define MCPWM_GEN2_B_UT1_V  0x3
-#define MCPWM_GEN2_B_UT1_S  10
-/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event_t0 when timer increasing*/
-#define MCPWM_GEN2_B_UT0  0x00000003
-#define MCPWM_GEN2_B_UT0_M  ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S))
-#define MCPWM_GEN2_B_UT0_V  0x3
-#define MCPWM_GEN2_B_UT0_S  8
-/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event TEB when timer increasing*/
-#define MCPWM_GEN2_B_UTEB  0x00000003
-#define MCPWM_GEN2_B_UTEB_M  ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S))
-#define MCPWM_GEN2_B_UTEB_V  0x3
-#define MCPWM_GEN2_B_UTEB_S  6
-/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event TEA when timer increasing*/
-#define MCPWM_GEN2_B_UTEA  0x00000003
-#define MCPWM_GEN2_B_UTEA_M  ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S))
-#define MCPWM_GEN2_B_UTEA_V  0x3
-#define MCPWM_GEN2_B_UTEA_S  4
-/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event TEP when timer increasing*/
-#define MCPWM_GEN2_B_UTEP  0x00000003
-#define MCPWM_GEN2_B_UTEP_M  ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S))
-#define MCPWM_GEN2_B_UTEP_V  0x3
-#define MCPWM_GEN2_B_UTEP_S  2
-/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: Action on PWM2B triggered by event TEZ when timer increasing*/
-#define MCPWM_GEN2_B_UTEZ  0x00000003
-#define MCPWM_GEN2_B_UTEZ_M  ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S))
-#define MCPWM_GEN2_B_UTEZ_V  0x3
-#define MCPWM_GEN2_B_UTEZ_S  0
-
-#define MCPWM_DT2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00c8)
-/* MCPWM_DT2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Dead time generator 1 clock selection. 0: PWM_clk  1: PT_clk*/
-#define MCPWM_DT2_CLK_SEL  (BIT(17))
-#define MCPWM_DT2_CLK_SEL_M  (BIT(17))
-#define MCPWM_DT2_CLK_SEL_V  0x1
-#define MCPWM_DT2_CLK_SEL_S  17
-/* MCPWM_DT2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: S0 in documentation*/
-#define MCPWM_DT2_B_OUTBYPASS  (BIT(16))
-#define MCPWM_DT2_B_OUTBYPASS_M  (BIT(16))
-#define MCPWM_DT2_B_OUTBYPASS_V  0x1
-#define MCPWM_DT2_B_OUTBYPASS_S  16
-/* MCPWM_DT2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
-/*description: S1 in documentation*/
-#define MCPWM_DT2_A_OUTBYPASS  (BIT(15))
-#define MCPWM_DT2_A_OUTBYPASS_M  (BIT(15))
-#define MCPWM_DT2_A_OUTBYPASS_V  0x1
-#define MCPWM_DT2_A_OUTBYPASS_S  15
-/* MCPWM_DT2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: S3 in documentation*/
-#define MCPWM_DT2_FED_OUTINVERT  (BIT(14))
-#define MCPWM_DT2_FED_OUTINVERT_M  (BIT(14))
-#define MCPWM_DT2_FED_OUTINVERT_V  0x1
-#define MCPWM_DT2_FED_OUTINVERT_S  14
-/* MCPWM_DT2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: S2 in documentation*/
-#define MCPWM_DT2_RED_OUTINVERT  (BIT(13))
-#define MCPWM_DT2_RED_OUTINVERT_M  (BIT(13))
-#define MCPWM_DT2_RED_OUTINVERT_V  0x1
-#define MCPWM_DT2_RED_OUTINVERT_S  13
-/* MCPWM_DT2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: S5 in documentation*/
-#define MCPWM_DT2_FED_INSEL  (BIT(12))
-#define MCPWM_DT2_FED_INSEL_M  (BIT(12))
-#define MCPWM_DT2_FED_INSEL_V  0x1
-#define MCPWM_DT2_FED_INSEL_S  12
-/* MCPWM_DT2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: S4 in documentation*/
-#define MCPWM_DT2_RED_INSEL  (BIT(11))
-#define MCPWM_DT2_RED_INSEL_M  (BIT(11))
-#define MCPWM_DT2_RED_INSEL_V  0x1
-#define MCPWM_DT2_RED_INSEL_S  11
-/* MCPWM_DT2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: S7 in documentation*/
-#define MCPWM_DT2_B_OUTSWAP  (BIT(10))
-#define MCPWM_DT2_B_OUTSWAP_M  (BIT(10))
-#define MCPWM_DT2_B_OUTSWAP_V  0x1
-#define MCPWM_DT2_B_OUTSWAP_S  10
-/* MCPWM_DT2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: S6 in documentation*/
-#define MCPWM_DT2_A_OUTSWAP  (BIT(9))
-#define MCPWM_DT2_A_OUTSWAP_M  (BIT(9))
-#define MCPWM_DT2_A_OUTSWAP_V  0x1
-#define MCPWM_DT2_A_OUTSWAP_S  9
-/* MCPWM_DT2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
- on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
-#define MCPWM_DT2_DEB_MODE  (BIT(8))
-#define MCPWM_DT2_DEB_MODE_M  (BIT(8))
-#define MCPWM_DT2_DEB_MODE_V  0x1
-#define MCPWM_DT2_DEB_MODE_S  8
-/* MCPWM_DT2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
-/*description: Update method for RED (rising edge delay) active reg. 0: immediate
-  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_DT2_RED_UPMETHOD  0x0000000F
-#define MCPWM_DT2_RED_UPMETHOD_M  ((MCPWM_DT2_RED_UPMETHOD_V)<<(MCPWM_DT2_RED_UPMETHOD_S))
-#define MCPWM_DT2_RED_UPMETHOD_V  0xF
-#define MCPWM_DT2_RED_UPMETHOD_S  4
-/* MCPWM_DT2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
-/*description: Update method for FED (falling edge delay) active reg. 0: immediate
-  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
-#define MCPWM_DT2_FED_UPMETHOD  0x0000000F
-#define MCPWM_DT2_FED_UPMETHOD_M  ((MCPWM_DT2_FED_UPMETHOD_V)<<(MCPWM_DT2_FED_UPMETHOD_S))
-#define MCPWM_DT2_FED_UPMETHOD_V  0xF
-#define MCPWM_DT2_FED_UPMETHOD_S  0
-
-#define MCPWM_DT2_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00cc)
-/* MCPWM_DT2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: Shadow reg for FED*/
-#define MCPWM_DT2_FED  0x0000FFFF
-#define MCPWM_DT2_FED_M  ((MCPWM_DT2_FED_V)<<(MCPWM_DT2_FED_S))
-#define MCPWM_DT2_FED_V  0xFFFF
-#define MCPWM_DT2_FED_S  0
-
-#define MCPWM_DT2_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00d0)
-/* MCPWM_DT2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
-/*description: Shadow reg for RED*/
-#define MCPWM_DT2_RED  0x0000FFFF
-#define MCPWM_DT2_RED_M  ((MCPWM_DT2_RED_V)<<(MCPWM_DT2_RED_S))
-#define MCPWM_DT2_RED_V  0xFFFF
-#define MCPWM_DT2_RED_S  0
-
-#define MCPWM_CARRIER2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00d4)
-/* MCPWM_CARRIER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: When set  invert the input of PWM2A and PWM2B for this submodule*/
-#define MCPWM_CARRIER2_IN_INVERT  (BIT(13))
-#define MCPWM_CARRIER2_IN_INVERT_M  (BIT(13))
-#define MCPWM_CARRIER2_IN_INVERT_V  0x1
-#define MCPWM_CARRIER2_IN_INVERT_S  13
-/* MCPWM_CARRIER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: When set  invert the output of PWM2A and PWM2B for this submodule*/
-#define MCPWM_CARRIER2_OUT_INVERT  (BIT(12))
-#define MCPWM_CARRIER2_OUT_INVERT_M  (BIT(12))
-#define MCPWM_CARRIER2_OUT_INVERT_V  0x1
-#define MCPWM_CARRIER2_OUT_INVERT_S  12
-/* MCPWM_CARRIER2_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
-/*description: Width of the fist pulse in number of periods of the carrier*/
-#define MCPWM_CARRIER2_OSHWTH  0x0000000F
-#define MCPWM_CARRIER2_OSHWTH_M  ((MCPWM_CARRIER2_OSHWTH_V)<<(MCPWM_CARRIER2_OSHWTH_S))
-#define MCPWM_CARRIER2_OSHWTH_V  0xF
-#define MCPWM_CARRIER2_OSHWTH_S  8
-/* MCPWM_CARRIER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
-/*description: Carrier duty selection. Duty = PWM_CARRIER2_DUTY / 8*/
-#define MCPWM_CARRIER2_DUTY  0x00000007
-#define MCPWM_CARRIER2_DUTY_M  ((MCPWM_CARRIER2_DUTY_V)<<(MCPWM_CARRIER2_DUTY_S))
-#define MCPWM_CARRIER2_DUTY_V  0x7
-#define MCPWM_CARRIER2_DUTY_S  5
-/* MCPWM_CARRIER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
-/*description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk
- = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)*/
-#define MCPWM_CARRIER2_PRESCALE  0x0000000F
-#define MCPWM_CARRIER2_PRESCALE_M  ((MCPWM_CARRIER2_PRESCALE_V)<<(MCPWM_CARRIER2_PRESCALE_S))
-#define MCPWM_CARRIER2_PRESCALE_V  0xF
-#define MCPWM_CARRIER2_PRESCALE_S  1
-/* MCPWM_CARRIER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: When set  carrier2 function is enabled. When cleared  carrier2 is bypassed*/
-#define MCPWM_CARRIER2_EN  (BIT(0))
-#define MCPWM_CARRIER2_EN_M  (BIT(0))
-#define MCPWM_CARRIER2_EN_V  0x1
-#define MCPWM_CARRIER2_EN_S  0
-
-#define MCPWM_FH2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00d8)
-/* MCPWM_FH2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM2B when fault event occurs and timer
- is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH2_B_OST_U  0x00000003
-#define MCPWM_FH2_B_OST_U_M  ((MCPWM_FH2_B_OST_U_V)<<(MCPWM_FH2_B_OST_U_S))
-#define MCPWM_FH2_B_OST_U_V  0x3
-#define MCPWM_FH2_B_OST_U_S  22
-/* MCPWM_FH2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM2B when fault event occurs and timer
- is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH2_B_OST_D  0x00000003
-#define MCPWM_FH2_B_OST_D_M  ((MCPWM_FH2_B_OST_D_V)<<(MCPWM_FH2_B_OST_D_S))
-#define MCPWM_FH2_B_OST_D_V  0x3
-#define MCPWM_FH2_B_OST_D_S  20
-/* MCPWM_FH2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and
- timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH2_B_CBC_U  0x00000003
-#define MCPWM_FH2_B_CBC_U_M  ((MCPWM_FH2_B_CBC_U_V)<<(MCPWM_FH2_B_CBC_U_S))
-#define MCPWM_FH2_B_CBC_U_V  0x3
-#define MCPWM_FH2_B_CBC_U_S  18
-/* MCPWM_FH2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and
- timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH2_B_CBC_D  0x00000003
-#define MCPWM_FH2_B_CBC_D_M  ((MCPWM_FH2_B_CBC_D_V)<<(MCPWM_FH2_B_CBC_D_S))
-#define MCPWM_FH2_B_CBC_D_V  0x3
-#define MCPWM_FH2_B_CBC_D_S  16
-/* MCPWM_FH2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM2A when fault event occurs and timer
- is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH2_A_OST_U  0x00000003
-#define MCPWM_FH2_A_OST_U_M  ((MCPWM_FH2_A_OST_U_V)<<(MCPWM_FH2_A_OST_U_S))
-#define MCPWM_FH2_A_OST_U_V  0x3
-#define MCPWM_FH2_A_OST_U_S  14
-/* MCPWM_FH2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: One-shot mode action on PWM2A when fault event occurs and timer
- is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH2_A_OST_D  0x00000003
-#define MCPWM_FH2_A_OST_D_M  ((MCPWM_FH2_A_OST_D_V)<<(MCPWM_FH2_A_OST_D_S))
-#define MCPWM_FH2_A_OST_D_V  0x3
-#define MCPWM_FH2_A_OST_D_S  12
-/* MCPWM_FH2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and
- timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH2_A_CBC_U  0x00000003
-#define MCPWM_FH2_A_CBC_U_M  ((MCPWM_FH2_A_CBC_U_V)<<(MCPWM_FH2_A_CBC_U_S))
-#define MCPWM_FH2_A_CBC_U_V  0x3
-#define MCPWM_FH2_A_CBC_U_S  10
-/* MCPWM_FH2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
-/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and
- timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-#define MCPWM_FH2_A_CBC_D  0x00000003
-#define MCPWM_FH2_A_CBC_D_M  ((MCPWM_FH2_A_CBC_D_V)<<(MCPWM_FH2_A_CBC_D_S))
-#define MCPWM_FH2_A_CBC_D_V  0x3
-#define MCPWM_FH2_A_CBC_D_S  8
-/* MCPWM_FH2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH2_F0_OST  (BIT(7))
-#define MCPWM_FH2_F0_OST_M  (BIT(7))
-#define MCPWM_FH2_F0_OST_V  0x1
-#define MCPWM_FH2_F0_OST_S  7
-/* MCPWM_FH2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH2_F1_OST  (BIT(6))
-#define MCPWM_FH2_F1_OST_M  (BIT(6))
-#define MCPWM_FH2_F1_OST_V  0x1
-#define MCPWM_FH2_F1_OST_S  6
-/* MCPWM_FH2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH2_F2_OST  (BIT(5))
-#define MCPWM_FH2_F2_OST_M  (BIT(5))
-#define MCPWM_FH2_F2_OST_V  0x1
-#define MCPWM_FH2_F2_OST_S  5
-/* MCPWM_FH2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
-#define MCPWM_FH2_SW_OST  (BIT(4))
-#define MCPWM_FH2_SW_OST_M  (BIT(4))
-#define MCPWM_FH2_SW_OST_V  0x1
-#define MCPWM_FH2_SW_OST_S  4
-/* MCPWM_FH2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
-/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
-#define MCPWM_FH2_F0_CBC  (BIT(3))
-#define MCPWM_FH2_F0_CBC_M  (BIT(3))
-#define MCPWM_FH2_F0_CBC_V  0x1
-#define MCPWM_FH2_F0_CBC_S  3
-/* MCPWM_FH2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
-/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
-#define MCPWM_FH2_F1_CBC  (BIT(2))
-#define MCPWM_FH2_F1_CBC_M  (BIT(2))
-#define MCPWM_FH2_F1_CBC_V  0x1
-#define MCPWM_FH2_F1_CBC_S  2
-/* MCPWM_FH2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
-#define MCPWM_FH2_F2_CBC  (BIT(1))
-#define MCPWM_FH2_F2_CBC_M  (BIT(1))
-#define MCPWM_FH2_F2_CBC_V  0x1
-#define MCPWM_FH2_F2_CBC_S  1
-/* MCPWM_FH2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Enable register for software force cycle-by-cycle mode action.
- 0: disable  1: enable*/
-#define MCPWM_FH2_SW_CBC  (BIT(0))
-#define MCPWM_FH2_SW_CBC_M  (BIT(0))
-#define MCPWM_FH2_SW_CBC_V  0x1
-#define MCPWM_FH2_SW_CBC_S  0
-
-#define MCPWM_FH2_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x00dc)
-/* MCPWM_FH2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: A toggle (software negation of value of this bit) triggers a
- one-shot mode action*/
-#define MCPWM_FH2_FORCE_OST  (BIT(4))
-#define MCPWM_FH2_FORCE_OST_M  (BIT(4))
-#define MCPWM_FH2_FORCE_OST_V  0x1
-#define MCPWM_FH2_FORCE_OST_S  4
-/* MCPWM_FH2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
-/*description: A toggle triggers a cycle-by-cycle mode action*/
-#define MCPWM_FH2_FORCE_CBC  (BIT(3))
-#define MCPWM_FH2_FORCE_CBC_M  (BIT(3))
-#define MCPWM_FH2_FORCE_CBC_V  0x1
-#define MCPWM_FH2_FORCE_CBC_S  3
-/* MCPWM_FH2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
-/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
-#define MCPWM_FH2_CBCPULSE  0x00000003
-#define MCPWM_FH2_CBCPULSE_M  ((MCPWM_FH2_CBCPULSE_V)<<(MCPWM_FH2_CBCPULSE_S))
-#define MCPWM_FH2_CBCPULSE_V  0x3
-#define MCPWM_FH2_CBCPULSE_S  1
-/* MCPWM_FH2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: A toggle will clear on going one-shot mode action*/
-#define MCPWM_FH2_CLR_OST  (BIT(0))
-#define MCPWM_FH2_CLR_OST_M  (BIT(0))
-#define MCPWM_FH2_CLR_OST_V  0x1
-#define MCPWM_FH2_CLR_OST_S  0
-
-#define MCPWM_FH2_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x00e0)
-/* MCPWM_FH2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
-#define MCPWM_FH2_OST_ON  (BIT(1))
-#define MCPWM_FH2_OST_ON_M  (BIT(1))
-#define MCPWM_FH2_OST_ON_V  0x1
-#define MCPWM_FH2_OST_ON_S  1
-/* MCPWM_FH2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
-#define MCPWM_FH2_CBC_ON  (BIT(0))
-#define MCPWM_FH2_CBC_ON_M  (BIT(0))
-#define MCPWM_FH2_CBC_ON_V  0x1
-#define MCPWM_FH2_CBC_ON_S  0
-
-#define MCPWM_FAULT_DETECT_REG(i)          (REG_MCPWM_BASE(i) + 0x00e4)
-/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  event_f2 is on going*/
-#define MCPWM_EVENT_F2  (BIT(8))
-#define MCPWM_EVENT_F2_M  (BIT(8))
-#define MCPWM_EVENT_F2_V  0x1
-#define MCPWM_EVENT_F2_S  8
-/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  event_f1 is on going*/
-#define MCPWM_EVENT_F1  (BIT(7))
-#define MCPWM_EVENT_F1_M  (BIT(7))
-#define MCPWM_EVENT_F1_V  0x1
-#define MCPWM_EVENT_F1_S  7
-/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */
-/*description: Set and reset by hardware. If set  event_f0 is on going*/
-#define MCPWM_EVENT_F0  (BIT(6))
-#define MCPWM_EVENT_F0_M  (BIT(6))
-#define MCPWM_EVENT_F0_V  0x1
-#define MCPWM_EVENT_F0_S  6
-/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: Set event_f2 trigger polarity on FAULT2 source from GPIO matrix.
- 0: level low  1: level high*/
-#define MCPWM_F2_POLE  (BIT(5))
-#define MCPWM_F2_POLE_M  (BIT(5))
-#define MCPWM_F2_POLE_V  0x1
-#define MCPWM_F2_POLE_S  5
-/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: Set event_f1 trigger polarity on FAULT2 source from GPIO matrix.
- 0: level low  1: level high*/
-#define MCPWM_F1_POLE  (BIT(4))
-#define MCPWM_F1_POLE_M  (BIT(4))
-#define MCPWM_F1_POLE_V  0x1
-#define MCPWM_F1_POLE_S  4
-/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */
-/*description: Set event_f0 trigger polarity on FAULT2 source from GPIO matrix.
- 0: level low  1: level high*/
-#define MCPWM_F0_POLE  (BIT(3))
-#define MCPWM_F0_POLE_M  (BIT(3))
-#define MCPWM_F0_POLE_V  0x1
-#define MCPWM_F0_POLE_S  3
-/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */
-/*description: Set to enable generation of event_f2*/
-#define MCPWM_F2_EN  (BIT(2))
-#define MCPWM_F2_EN_M  (BIT(2))
-#define MCPWM_F2_EN_V  0x1
-#define MCPWM_F2_EN_S  2
-/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: Set to enable generation of event_f1*/
-#define MCPWM_F1_EN  (BIT(1))
-#define MCPWM_F1_EN_M  (BIT(1))
-#define MCPWM_F1_EN_V  0x1
-#define MCPWM_F1_EN_S  1
-/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Set to enable generation of event_f0*/
-#define MCPWM_F0_EN  (BIT(0))
-#define MCPWM_F0_EN_M  (BIT(0))
-#define MCPWM_F0_EN_V  0x1
-#define MCPWM_F0_EN_S  0
-
-#define MCPWM_CAP_TIMER_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00e8)
-/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */
-/*description: Set this bit to force a capture timer sync  capture timer is
- loaded with value in phase register.*/
-#define MCPWM_CAP_SYNC_SW  (BIT(5))
-#define MCPWM_CAP_SYNC_SW_M  (BIT(5))
-#define MCPWM_CAP_SYNC_SW_V  0x1
-#define MCPWM_CAP_SYNC_SW_S  5
-/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: Capture module sync input selection. 0: none  1: timer0 synco
-  2: timer1 synco  3: timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix*/
-#define MCPWM_CAP_SYNCI_SEL  0x00000007
-#define MCPWM_CAP_SYNCI_SEL_M  ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S))
-#define MCPWM_CAP_SYNCI_SEL_V  0x7
-#define MCPWM_CAP_SYNCI_SEL_S  2
-/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: When set  capture timer sync is enabled.*/
-#define MCPWM_CAP_SYNCI_EN  (BIT(1))
-#define MCPWM_CAP_SYNCI_EN_M  (BIT(1))
-#define MCPWM_CAP_SYNCI_EN_V  0x1
-#define MCPWM_CAP_SYNCI_EN_S  1
-/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: When set  capture timer incrementing under APB_clk is enabled.*/
-#define MCPWM_CAP_TIMER_EN  (BIT(0))
-#define MCPWM_CAP_TIMER_EN_M  (BIT(0))
-#define MCPWM_CAP_TIMER_EN_V  0x1
-#define MCPWM_CAP_TIMER_EN_S  0
-
-#define MCPWM_CAP_TIMER_PHASE_REG(i)          (REG_MCPWM_BASE(i) + 0x00ec)
-/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: Phase value for capture timer sync operation.*/
-#define MCPWM_CAP_PHASE  0xFFFFFFFF
-#define MCPWM_CAP_PHASE_M  ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S))
-#define MCPWM_CAP_PHASE_V  0xFFFFFFFF
-#define MCPWM_CAP_PHASE_S  0
-
-#define MCPWM_CAP_CH0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f0)
-/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
-/*description: Write 1 will trigger a software forced capture on channel 0*/
-#define MCPWM_CAP0_SW  (BIT(12))
-#define MCPWM_CAP0_SW_M  (BIT(12))
-#define MCPWM_CAP0_SW_V  0x1
-#define MCPWM_CAP0_SW_S  12
-/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: When set  CAP0 form GPIO matrix is inverted before prescale*/
-#define MCPWM_CAP0_IN_INVERT  (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_V  0x1
-#define MCPWM_CAP0_IN_INVERT_S  11
-/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
-/*description: Value of prescale on possitive edge of CAP0. Prescale value =
- PWM_CAP0_PRESCALE + 1*/
-#define MCPWM_CAP0_PRESCALE  0x000000FF
-#define MCPWM_CAP0_PRESCALE_M  ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S))
-#define MCPWM_CAP0_PRESCALE_V  0xFF
-#define MCPWM_CAP0_PRESCALE_S  3
-/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
-/*description: Edge of capture on channel 0 after prescale.  bit0: negedge cap
- en  bit1: posedge cap en*/
-#define MCPWM_CAP0_MODE  0x00000003
-#define MCPWM_CAP0_MODE_M  ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S))
-#define MCPWM_CAP0_MODE_V  0x3
-#define MCPWM_CAP0_MODE_S  1
-/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: When set  capture on channel 0 is enabled*/
-#define MCPWM_CAP0_EN  (BIT(0))
-#define MCPWM_CAP0_EN_M  (BIT(0))
-#define MCPWM_CAP0_EN_V  0x1
-#define MCPWM_CAP0_EN_S  0
-
-#define MCPWM_CAP_CH1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f4)
-/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
-/*description: Write 1 will trigger a software forced capture on channel 1*/
-#define MCPWM_CAP1_SW  (BIT(12))
-#define MCPWM_CAP1_SW_M  (BIT(12))
-#define MCPWM_CAP1_SW_V  0x1
-#define MCPWM_CAP1_SW_S  12
-/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: When set  CAP1 form GPIO matrix is inverted before prescale*/
-#define MCPWM_CAP1_IN_INVERT  (BIT(11))
-#define MCPWM_CAP1_IN_INVERT_M  (BIT(11))
-#define MCPWM_CAP1_IN_INVERT_V  0x1
-#define MCPWM_CAP1_IN_INVERT_S  11
-/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
-/*description: Value of prescale on possitive edge of CAP1. Prescale value =
- PWM_CAP1_PRESCALE + 1*/
-#define MCPWM_CAP1_PRESCALE  0x000000FF
-#define MCPWM_CAP1_PRESCALE_M  ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S))
-#define MCPWM_CAP1_PRESCALE_V  0xFF
-#define MCPWM_CAP1_PRESCALE_S  3
-/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
-/*description: Edge of capture on channel 1 after prescale.  bit0: negedge cap
- en  bit1: posedge cap en*/
-#define MCPWM_CAP1_MODE  0x00000003
-#define MCPWM_CAP1_MODE_M  ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S))
-#define MCPWM_CAP1_MODE_V  0x3
-#define MCPWM_CAP1_MODE_S  1
-/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: When set  capture on channel 1 is enabled*/
-#define MCPWM_CAP1_EN  (BIT(0))
-#define MCPWM_CAP1_EN_M  (BIT(0))
-#define MCPWM_CAP1_EN_V  0x1
-#define MCPWM_CAP1_EN_S  0
-
-#define MCPWM_CAP_CH2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f8)
-/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
-/*description: Write 1 will trigger a software forced capture on channel 2*/
-#define MCPWM_CAP2_SW  (BIT(12))
-#define MCPWM_CAP2_SW_M  (BIT(12))
-#define MCPWM_CAP2_SW_V  0x1
-#define MCPWM_CAP2_SW_S  12
-/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: When set  CAP2 form GPIO matrix is inverted before prescale*/
-#define MCPWM_CAP2_IN_INVERT  (BIT(11))
-#define MCPWM_CAP2_IN_INVERT_M  (BIT(11))
-#define MCPWM_CAP2_IN_INVERT_V  0x1
-#define MCPWM_CAP2_IN_INVERT_S  11
-/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
-/*description: Value of prescale on possitive edge of CAP2. Prescale value =
- PWM_CAP2_PRESCALE + 1*/
-#define MCPWM_CAP2_PRESCALE  0x000000FF
-#define MCPWM_CAP2_PRESCALE_M  ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S))
-#define MCPWM_CAP2_PRESCALE_V  0xFF
-#define MCPWM_CAP2_PRESCALE_S  3
-/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
-/*description: Edge of capture on channel 2 after prescale.  bit0: negedge cap
- en  bit1: posedge cap en*/
-#define MCPWM_CAP2_MODE  0x00000003
-#define MCPWM_CAP2_MODE_M  ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S))
-#define MCPWM_CAP2_MODE_V  0x3
-#define MCPWM_CAP2_MODE_S  1
-/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: When set  capture on channel 2 is enabled*/
-#define MCPWM_CAP2_EN  (BIT(0))
-#define MCPWM_CAP2_EN_M  (BIT(0))
-#define MCPWM_CAP2_EN_V  0x1
-#define MCPWM_CAP2_EN_S  0
-
-#define MCPWM_CAP_CH0_REG(i)          (REG_MCPWM_BASE(i) + 0x00fc)
-/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: Value of last capture on channel 0*/
-#define MCPWM_CAP0_VALUE  0xFFFFFFFF
-#define MCPWM_CAP0_VALUE_M  ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S))
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFF
-#define MCPWM_CAP0_VALUE_S  0
-
-#define MCPWM_CAP_CH1_REG(i)          (REG_MCPWM_BASE(i) + 0x0100)
-/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: Value of last capture on channel 1*/
-#define MCPWM_CAP1_VALUE  0xFFFFFFFF
-#define MCPWM_CAP1_VALUE_M  ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S))
-#define MCPWM_CAP1_VALUE_V  0xFFFFFFFF
-#define MCPWM_CAP1_VALUE_S  0
-
-#define MCPWM_CAP_CH2_REG(i)          (REG_MCPWM_BASE(i) + 0x0104)
-/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: Value of last capture on channel 2*/
-#define MCPWM_CAP2_VALUE  0xFFFFFFFF
-#define MCPWM_CAP2_VALUE_M  ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S))
-#define MCPWM_CAP2_VALUE_V  0xFFFFFFFF
-#define MCPWM_CAP2_VALUE_S  0
-
-#define MCPWM_CAP_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0108)
-/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */
-/*description: Edge of last capture trigger on channel 2  0: posedge  1: negedge*/
-#define MCPWM_CAP2_EDGE  (BIT(2))
-#define MCPWM_CAP2_EDGE_M  (BIT(2))
-#define MCPWM_CAP2_EDGE_V  0x1
-#define MCPWM_CAP2_EDGE_S  2
-/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: Edge of last capture trigger on channel 1  0: posedge  1: negedge*/
-#define MCPWM_CAP1_EDGE  (BIT(1))
-#define MCPWM_CAP1_EDGE_M  (BIT(1))
-#define MCPWM_CAP1_EDGE_V  0x1
-#define MCPWM_CAP1_EDGE_S  1
-/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Edge of last capture trigger on channel 0  0: posedge  1: negedge*/
-#define MCPWM_CAP0_EDGE  (BIT(0))
-#define MCPWM_CAP0_EDGE_M  (BIT(0))
-#define MCPWM_CAP0_EDGE_V  0x1
-#define MCPWM_CAP0_EDGE_S  0
-
-#define MCPWM_UPDATE_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x010c)
-/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: A toggle (software negation of value of this bit) will trigger
- a forced update of active registers in PWM operator 2*/
-#define MCPWM_OP2_FORCE_UP  (BIT(7))
-#define MCPWM_OP2_FORCE_UP_M  (BIT(7))
-#define MCPWM_OP2_FORCE_UP_V  0x1
-#define MCPWM_OP2_FORCE_UP_S  7
-/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */
-/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
- in PWM operator 2 are enabled*/
-#define MCPWM_OP2_UP_EN  (BIT(6))
-#define MCPWM_OP2_UP_EN_M  (BIT(6))
-#define MCPWM_OP2_UP_EN_V  0x1
-#define MCPWM_OP2_UP_EN_S  6
-/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: A toggle (software negation of value of this bit) will trigger
- a forced update of active registers in PWM operator 1*/
-#define MCPWM_OP1_FORCE_UP  (BIT(5))
-#define MCPWM_OP1_FORCE_UP_M  (BIT(5))
-#define MCPWM_OP1_FORCE_UP_V  0x1
-#define MCPWM_OP1_FORCE_UP_S  5
-/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */
-/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
- in PWM operator 1 are enabled*/
-#define MCPWM_OP1_UP_EN  (BIT(4))
-#define MCPWM_OP1_UP_EN_M  (BIT(4))
-#define MCPWM_OP1_UP_EN_V  0x1
-#define MCPWM_OP1_UP_EN_S  4
-/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */
-/*description: A toggle (software negation of value of this bit) will trigger
- a forced update of active registers in PWM operator 0*/
-#define MCPWM_OP0_FORCE_UP  (BIT(3))
-#define MCPWM_OP0_FORCE_UP_M  (BIT(3))
-#define MCPWM_OP0_FORCE_UP_V  0x1
-#define MCPWM_OP0_FORCE_UP_S  3
-/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */
-/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
- in PWM operator 0 are enabled*/
-#define MCPWM_OP0_UP_EN  (BIT(2))
-#define MCPWM_OP0_UP_EN_M  (BIT(2))
-#define MCPWM_OP0_UP_EN_V  0x1
-#define MCPWM_OP0_UP_EN_S  2
-/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: A toggle (software negation of value of this bit) will trigger
- a forced update of all active registers in MCPWM module*/
-#define MCPWM_GLOBAL_FORCE_UP  (BIT(1))
-#define MCPWM_GLOBAL_FORCE_UP_M  (BIT(1))
-#define MCPWM_GLOBAL_FORCE_UP_V  0x1
-#define MCPWM_GLOBAL_FORCE_UP_S  1
-/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
-/*description: The global enable of update of all active registers in MCPWM module*/
-#define MCPWM_GLOBAL_UP_EN  (BIT(0))
-#define MCPWM_GLOBAL_UP_EN_M  (BIT(0))
-#define MCPWM_GLOBAL_UP_EN_V  0x1
-#define MCPWM_GLOBAL_UP_EN_S  0
-
-#define MCMCPWM_INT_ENA_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0110)
-/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by captureon channel 2*/
-#define MCPWM_CAP2_INT_ENA  (BIT(29))
-#define MCPWM_CAP2_INT_ENA_M  (BIT(29))
-#define MCPWM_CAP2_INT_ENA_V  0x1
-#define MCPWM_CAP2_INT_ENA_S  29
-/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by captureon channel 1*/
-#define MCPWM_CAP1_INT_ENA  (BIT(28))
-#define MCPWM_CAP1_INT_ENA_M  (BIT(28))
-#define MCPWM_CAP1_INT_ENA_V  0x1
-#define MCPWM_CAP1_INT_ENA_S  28
-/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by captureon channel 0*/
-#define MCPWM_CAP0_INT_ENA  (BIT(27))
-#define MCPWM_CAP0_INT_ENA_M  (BIT(27))
-#define MCPWM_CAP0_INT_ENA_V  0x1
-#define MCPWM_CAP0_INT_ENA_S  27
-/* MCPWM_FH2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM2*/
-#define MCPWM_FH2_OST_INT_ENA  (BIT(26))
-#define MCPWM_FH2_OST_INT_ENA_M  (BIT(26))
-#define MCPWM_FH2_OST_INT_ENA_V  0x1
-#define MCPWM_FH2_OST_INT_ENA_S  26
-/* MCPWM_FH1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/
-#define MCPWM_FH1_OST_INT_ENA  (BIT(25))
-#define MCPWM_FH1_OST_INT_ENA_M  (BIT(25))
-#define MCPWM_FH1_OST_INT_ENA_V  0x1
-#define MCPWM_FH1_OST_INT_ENA_S  25
-/* MCPWM_FH0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/
-#define MCPWM_FH0_OST_INT_ENA  (BIT(24))
-#define MCPWM_FH0_OST_INT_ENA_M  (BIT(24))
-#define MCPWM_FH0_OST_INT_ENA_V  0x1
-#define MCPWM_FH0_OST_INT_ENA_S  24
-/* MCPWM_FH2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM2*/
-#define MCPWM_FH2_CBC_INT_ENA  (BIT(23))
-#define MCPWM_FH2_CBC_INT_ENA_M  (BIT(23))
-#define MCPWM_FH2_CBC_INT_ENA_V  0x1
-#define MCPWM_FH2_CBC_INT_ENA_S  23
-/* MCPWM_FH1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM1*/
-#define MCPWM_FH1_CBC_INT_ENA  (BIT(22))
-#define MCPWM_FH1_CBC_INT_ENA_M  (BIT(22))
-#define MCPWM_FH1_CBC_INT_ENA_V  0x1
-#define MCPWM_FH1_CBC_INT_ENA_S  22
-/* MCPWM_FH0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM0*/
-#define MCPWM_FH0_CBC_INT_ENA  (BIT(21))
-#define MCPWM_FH0_CBC_INT_ENA_M  (BIT(21))
-#define MCPWM_FH0_CBC_INT_ENA_V  0x1
-#define MCPWM_FH0_CBC_INT_ENA_S  21
-/* MCPWM_OP2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by a PWM operator 2 TEB event*/
-#define MCPWM_OP2_TEB_INT_ENA  (BIT(20))
-#define MCPWM_OP2_TEB_INT_ENA_M  (BIT(20))
-#define MCPWM_OP2_TEB_INT_ENA_V  0x1
-#define MCPWM_OP2_TEB_INT_ENA_S  20
-/* MCPWM_OP1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by a PWM operator 1 TEB event*/
-#define MCPWM_OP1_TEB_INT_ENA  (BIT(19))
-#define MCPWM_OP1_TEB_INT_ENA_M  (BIT(19))
-#define MCPWM_OP1_TEB_INT_ENA_V  0x1
-#define MCPWM_OP1_TEB_INT_ENA_S  19
-/* MCPWM_OP0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by a PWM operator 0 TEB event*/
-#define MCPWM_OP0_TEB_INT_ENA  (BIT(18))
-#define MCPWM_OP0_TEB_INT_ENA_M  (BIT(18))
-#define MCPWM_OP0_TEB_INT_ENA_V  0x1
-#define MCPWM_OP0_TEB_INT_ENA_S  18
-/* MCPWM_OP2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by a PWM operator 2 TEA event*/
-#define MCPWM_OP2_TEA_INT_ENA  (BIT(17))
-#define MCPWM_OP2_TEA_INT_ENA_M  (BIT(17))
-#define MCPWM_OP2_TEA_INT_ENA_V  0x1
-#define MCPWM_OP2_TEA_INT_ENA_S  17
-/* MCPWM_OP1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by a PWM operator 1 TEA event*/
-#define MCPWM_OP1_TEA_INT_ENA  (BIT(16))
-#define MCPWM_OP1_TEA_INT_ENA_M  (BIT(16))
-#define MCPWM_OP1_TEA_INT_ENA_V  0x1
-#define MCPWM_OP1_TEA_INT_ENA_S  16
-/* MCPWM_OP0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered by a PWM operator 0 TEA event*/
-#define MCPWM_OP0_TEA_INT_ENA  (BIT(15))
-#define MCPWM_OP0_TEA_INT_ENA_M  (BIT(15))
-#define MCPWM_OP0_TEA_INT_ENA_V  0x1
-#define MCPWM_OP0_TEA_INT_ENA_S  15
-/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered when event_f2 ends*/
-#define MCPWM_FAULT2_CLR_INT_ENA  (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ENA_M  (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ENA_V  0x1
-#define MCPWM_FAULT2_CLR_INT_ENA_S  14
-/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered when event_f1 ends*/
-#define MCPWM_FAULT1_CLR_INT_ENA  (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ENA_M  (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ENA_V  0x1
-#define MCPWM_FAULT1_CLR_INT_ENA_S  13
-/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered when event_f0 ends*/
-#define MCPWM_FAULT0_CLR_INT_ENA  (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ENA_M  (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ENA_V  0x1
-#define MCPWM_FAULT0_CLR_INT_ENA_S  12
-/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered when event_f2 starts*/
-#define MCPWM_FAULT2_INT_ENA  (BIT(11))
-#define MCPWM_FAULT2_INT_ENA_M  (BIT(11))
-#define MCPWM_FAULT2_INT_ENA_V  0x1
-#define MCPWM_FAULT2_INT_ENA_S  11
-/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered when event_f1 starts*/
-#define MCPWM_FAULT1_INT_ENA  (BIT(10))
-#define MCPWM_FAULT1_INT_ENA_M  (BIT(10))
-#define MCPWM_FAULT1_INT_ENA_V  0x1
-#define MCPWM_FAULT1_INT_ENA_S  10
-/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: The enable bit for interrupt triggered when event_f0 starts*/
-#define MCPWM_FAULT0_INT_ENA  (BIT(9))
-#define MCPWM_FAULT0_INT_ENA_M  (BIT(9))
-#define MCPWM_FAULT0_INT_ENA_V  0x1
-#define MCPWM_FAULT0_INT_ENA_S  9
-/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: The enable bit for interrupt triggered by a PWM timer 2 TEP event*/
-#define MCPWM_TIMER2_TEP_INT_ENA  (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ENA_M  (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ENA_V  0x1
-#define MCPWM_TIMER2_TEP_INT_ENA_S  8
-/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: The enable bit for interrupt triggered by a PWM timer 1 TEP event*/
-#define MCPWM_TIMER1_TEP_INT_ENA  (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ENA_M  (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ENA_V  0x1
-#define MCPWM_TIMER1_TEP_INT_ENA_S  7
-/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: The enable bit for interrupt triggered by a PWM timer 0 TEP event*/
-#define MCPWM_TIMER0_TEP_INT_ENA  (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ENA_M  (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ENA_V  0x1
-#define MCPWM_TIMER0_TEP_INT_ENA_S  6
-/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: The enable bit for interrupt triggered by a PWM timer 2 TEZ event*/
-#define MCPWM_TIMER2_TEZ_INT_ENA  (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ENA_M  (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x1
-#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
-/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: The enable bit for interrupt triggered by a PWM timer 1 TEZ event*/
-#define MCPWM_TIMER1_TEZ_INT_ENA  (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ENA_M  (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x1
-#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
-/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: The enable bit for interrupt triggered by a PWM timer 0 TEZ event*/
-#define MCPWM_TIMER0_TEZ_INT_ENA  (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ENA_M  (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x1
-#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
-/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The enable bit for interrupt triggered when timer 2 stops*/
-#define MCPWM_TIMER2_STOP_INT_ENA  (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ENA_M  (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ENA_V  0x1
-#define MCPWM_TIMER2_STOP_INT_ENA_S  2
-/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The enable bit for interrupt triggered when timer 1 stops*/
-#define MCPWM_TIMER1_STOP_INT_ENA  (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ENA_M  (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ENA_V  0x1
-#define MCPWM_TIMER1_STOP_INT_ENA_S  1
-/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The enable bit for interrupt triggered when timer 0 stops*/
-#define MCPWM_TIMER0_STOP_INT_ENA  (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ENA_M  (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ENA_V  0x1
-#define MCPWM_TIMER0_STOP_INT_ENA_S  0
-
-#define MCMCPWM_INT_RAW_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0114)
-/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by captureon channel 2*/
-#define MCPWM_CAP2_INT_RAW  (BIT(29))
-#define MCPWM_CAP2_INT_RAW_M  (BIT(29))
-#define MCPWM_CAP2_INT_RAW_V  0x1
-#define MCPWM_CAP2_INT_RAW_S  29
-/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by captureon channel 1*/
-#define MCPWM_CAP1_INT_RAW  (BIT(28))
-#define MCPWM_CAP1_INT_RAW_M  (BIT(28))
-#define MCPWM_CAP1_INT_RAW_V  0x1
-#define MCPWM_CAP1_INT_RAW_S  28
-/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by captureon channel 0*/
-#define MCPWM_CAP0_INT_RAW  (BIT(27))
-#define MCPWM_CAP0_INT_RAW_M  (BIT(27))
-#define MCPWM_CAP0_INT_RAW_V  0x1
-#define MCPWM_CAP0_INT_RAW_S  27
-/* MCPWM_FH2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM2*/
-#define MCPWM_FH2_OST_INT_RAW  (BIT(26))
-#define MCPWM_FH2_OST_INT_RAW_M  (BIT(26))
-#define MCPWM_FH2_OST_INT_RAW_V  0x1
-#define MCPWM_FH2_OST_INT_RAW_S  26
-/* MCPWM_FH1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/
-#define MCPWM_FH1_OST_INT_RAW  (BIT(25))
-#define MCPWM_FH1_OST_INT_RAW_M  (BIT(25))
-#define MCPWM_FH1_OST_INT_RAW_V  0x1
-#define MCPWM_FH1_OST_INT_RAW_S  25
-/* MCPWM_FH0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/
-#define MCPWM_FH0_OST_INT_RAW  (BIT(24))
-#define MCPWM_FH0_OST_INT_RAW_M  (BIT(24))
-#define MCPWM_FH0_OST_INT_RAW_V  0x1
-#define MCPWM_FH0_OST_INT_RAW_S  24
-/* MCPWM_FH2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
- mode action on PWM2*/
-#define MCPWM_FH2_CBC_INT_RAW  (BIT(23))
-#define MCPWM_FH2_CBC_INT_RAW_M  (BIT(23))
-#define MCPWM_FH2_CBC_INT_RAW_V  0x1
-#define MCPWM_FH2_CBC_INT_RAW_S  23
-/* MCPWM_FH1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
- mode action on PWM1*/
-#define MCPWM_FH1_CBC_INT_RAW  (BIT(22))
-#define MCPWM_FH1_CBC_INT_RAW_M  (BIT(22))
-#define MCPWM_FH1_CBC_INT_RAW_V  0x1
-#define MCPWM_FH1_CBC_INT_RAW_S  22
-/* MCPWM_FH0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
- mode action on PWM0*/
-#define MCPWM_FH0_CBC_INT_RAW  (BIT(21))
-#define MCPWM_FH0_CBC_INT_RAW_M  (BIT(21))
-#define MCPWM_FH0_CBC_INT_RAW_V  0x1
-#define MCPWM_FH0_CBC_INT_RAW_S  21
-/* MCPWM_OP2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEB event*/
-#define MCPWM_OP2_TEB_INT_RAW  (BIT(20))
-#define MCPWM_OP2_TEB_INT_RAW_M  (BIT(20))
-#define MCPWM_OP2_TEB_INT_RAW_V  0x1
-#define MCPWM_OP2_TEB_INT_RAW_S  20
-/* MCPWM_OP1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEB event*/
-#define MCPWM_OP1_TEB_INT_RAW  (BIT(19))
-#define MCPWM_OP1_TEB_INT_RAW_M  (BIT(19))
-#define MCPWM_OP1_TEB_INT_RAW_V  0x1
-#define MCPWM_OP1_TEB_INT_RAW_S  19
-/* MCPWM_OP0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEB event*/
-#define MCPWM_OP0_TEB_INT_RAW  (BIT(18))
-#define MCPWM_OP0_TEB_INT_RAW_M  (BIT(18))
-#define MCPWM_OP0_TEB_INT_RAW_V  0x1
-#define MCPWM_OP0_TEB_INT_RAW_S  18
-/* MCPWM_OP2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEA event*/
-#define MCPWM_OP2_TEA_INT_RAW  (BIT(17))
-#define MCPWM_OP2_TEA_INT_RAW_M  (BIT(17))
-#define MCPWM_OP2_TEA_INT_RAW_V  0x1
-#define MCPWM_OP2_TEA_INT_RAW_S  17
-/* MCPWM_OP1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEA event*/
-#define MCPWM_OP1_TEA_INT_RAW  (BIT(16))
-#define MCPWM_OP1_TEA_INT_RAW_M  (BIT(16))
-#define MCPWM_OP1_TEA_INT_RAW_V  0x1
-#define MCPWM_OP1_TEA_INT_RAW_S  16
-/* MCPWM_OP0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEA event*/
-#define MCPWM_OP0_TEA_INT_RAW  (BIT(15))
-#define MCPWM_OP0_TEA_INT_RAW_M  (BIT(15))
-#define MCPWM_OP0_TEA_INT_RAW_V  0x1
-#define MCPWM_OP0_TEA_INT_RAW_S  15
-/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered when event_f2 ends*/
-#define MCPWM_FAULT2_CLR_INT_RAW  (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_RAW_M  (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_RAW_V  0x1
-#define MCPWM_FAULT2_CLR_INT_RAW_S  14
-/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered when event_f1 ends*/
-#define MCPWM_FAULT1_CLR_INT_RAW  (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_RAW_M  (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_RAW_V  0x1
-#define MCPWM_FAULT1_CLR_INT_RAW_S  13
-/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered when event_f0 ends*/
-#define MCPWM_FAULT0_CLR_INT_RAW  (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_RAW_M  (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_RAW_V  0x1
-#define MCPWM_FAULT0_CLR_INT_RAW_S  12
-/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered when event_f2 starts*/
-#define MCPWM_FAULT2_INT_RAW  (BIT(11))
-#define MCPWM_FAULT2_INT_RAW_M  (BIT(11))
-#define MCPWM_FAULT2_INT_RAW_V  0x1
-#define MCPWM_FAULT2_INT_RAW_S  11
-/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered when event_f1 starts*/
-#define MCPWM_FAULT1_INT_RAW  (BIT(10))
-#define MCPWM_FAULT1_INT_RAW_M  (BIT(10))
-#define MCPWM_FAULT1_INT_RAW_V  0x1
-#define MCPWM_FAULT1_INT_RAW_S  10
-/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */
-/*description: The raw status bit for interrupt triggered when event_f0 starts*/
-#define MCPWM_FAULT0_INT_RAW  (BIT(9))
-#define MCPWM_FAULT0_INT_RAW_M  (BIT(9))
-#define MCPWM_FAULT0_INT_RAW_V  0x1
-#define MCPWM_FAULT0_INT_RAW_S  9
-/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEP event*/
-#define MCPWM_TIMER2_TEP_INT_RAW  (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_RAW_M  (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_RAW_V  0x1
-#define MCPWM_TIMER2_TEP_INT_RAW_S  8
-/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEP event*/
-#define MCPWM_TIMER1_TEP_INT_RAW  (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_RAW_M  (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_RAW_V  0x1
-#define MCPWM_TIMER1_TEP_INT_RAW_S  7
-/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEP event*/
-#define MCPWM_TIMER0_TEP_INT_RAW  (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_RAW_M  (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_RAW_V  0x1
-#define MCPWM_TIMER0_TEP_INT_RAW_S  6
-/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEZ event*/
-#define MCPWM_TIMER2_TEZ_INT_RAW  (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_RAW_M  (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x1
-#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
-/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEZ event*/
-#define MCPWM_TIMER1_TEZ_INT_RAW  (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_RAW_M  (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x1
-#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
-/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEZ event*/
-#define MCPWM_TIMER0_TEZ_INT_RAW  (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_RAW_M  (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x1
-#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
-/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The raw status bit for interrupt triggered when timer 2 stops*/
-#define MCPWM_TIMER2_STOP_INT_RAW  (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_RAW_M  (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_RAW_V  0x1
-#define MCPWM_TIMER2_STOP_INT_RAW_S  2
-/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The raw status bit for interrupt triggered when timer 1 stops*/
-#define MCPWM_TIMER1_STOP_INT_RAW  (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_RAW_M  (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_RAW_V  0x1
-#define MCPWM_TIMER1_STOP_INT_RAW_S  1
-/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The raw status bit for interrupt triggered when timer 0 stops*/
-#define MCPWM_TIMER0_STOP_INT_RAW  (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_RAW_M  (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_RAW_V  0x1
-#define MCPWM_TIMER0_STOP_INT_RAW_S  0
-
-#define MCMCPWM_INT_ST_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0118)
-/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by captureon channel 2*/
-#define MCPWM_CAP2_INT_ST  (BIT(29))
-#define MCPWM_CAP2_INT_ST_M  (BIT(29))
-#define MCPWM_CAP2_INT_ST_V  0x1
-#define MCPWM_CAP2_INT_ST_S  29
-/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by captureon channel 1*/
-#define MCPWM_CAP1_INT_ST  (BIT(28))
-#define MCPWM_CAP1_INT_ST_M  (BIT(28))
-#define MCPWM_CAP1_INT_ST_V  0x1
-#define MCPWM_CAP1_INT_ST_S  28
-/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by captureon channel 0*/
-#define MCPWM_CAP0_INT_ST  (BIT(27))
-#define MCPWM_CAP0_INT_ST_M  (BIT(27))
-#define MCPWM_CAP0_INT_ST_V  0x1
-#define MCPWM_CAP0_INT_ST_S  27
-/* MCPWM_FH2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM2*/
-#define MCPWM_FH2_OST_INT_ST  (BIT(26))
-#define MCPWM_FH2_OST_INT_ST_M  (BIT(26))
-#define MCPWM_FH2_OST_INT_ST_V  0x1
-#define MCPWM_FH2_OST_INT_ST_S  26
-/* MCPWM_FH1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/
-#define MCPWM_FH1_OST_INT_ST  (BIT(25))
-#define MCPWM_FH1_OST_INT_ST_M  (BIT(25))
-#define MCPWM_FH1_OST_INT_ST_V  0x1
-#define MCPWM_FH1_OST_INT_ST_S  25
-/* MCPWM_FH0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/
-#define MCPWM_FH0_OST_INT_ST  (BIT(24))
-#define MCPWM_FH0_OST_INT_ST_M  (BIT(24))
-#define MCPWM_FH0_OST_INT_ST_V  0x1
-#define MCPWM_FH0_OST_INT_ST_S  24
-/* MCPWM_FH2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
- mode action on PWM2*/
-#define MCPWM_FH2_CBC_INT_ST  (BIT(23))
-#define MCPWM_FH2_CBC_INT_ST_M  (BIT(23))
-#define MCPWM_FH2_CBC_INT_ST_V  0x1
-#define MCPWM_FH2_CBC_INT_ST_S  23
-/* MCPWM_FH1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
- mode action on PWM1*/
-#define MCPWM_FH1_CBC_INT_ST  (BIT(22))
-#define MCPWM_FH1_CBC_INT_ST_M  (BIT(22))
-#define MCPWM_FH1_CBC_INT_ST_V  0x1
-#define MCPWM_FH1_CBC_INT_ST_S  22
-/* MCPWM_FH0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
- mode action on PWM0*/
-#define MCPWM_FH0_CBC_INT_ST  (BIT(21))
-#define MCPWM_FH0_CBC_INT_ST_M  (BIT(21))
-#define MCPWM_FH0_CBC_INT_ST_V  0x1
-#define MCPWM_FH0_CBC_INT_ST_S  21
-/* MCPWM_OP2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEB event*/
-#define MCPWM_OP2_TEB_INT_ST  (BIT(20))
-#define MCPWM_OP2_TEB_INT_ST_M  (BIT(20))
-#define MCPWM_OP2_TEB_INT_ST_V  0x1
-#define MCPWM_OP2_TEB_INT_ST_S  20
-/* MCPWM_OP1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEB event*/
-#define MCPWM_OP1_TEB_INT_ST  (BIT(19))
-#define MCPWM_OP1_TEB_INT_ST_M  (BIT(19))
-#define MCPWM_OP1_TEB_INT_ST_V  0x1
-#define MCPWM_OP1_TEB_INT_ST_S  19
-/* MCPWM_OP0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEB event*/
-#define MCPWM_OP0_TEB_INT_ST  (BIT(18))
-#define MCPWM_OP0_TEB_INT_ST_M  (BIT(18))
-#define MCPWM_OP0_TEB_INT_ST_V  0x1
-#define MCPWM_OP0_TEB_INT_ST_S  18
-/* MCPWM_OP2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEA event*/
-#define MCPWM_OP2_TEA_INT_ST  (BIT(17))
-#define MCPWM_OP2_TEA_INT_ST_M  (BIT(17))
-#define MCPWM_OP2_TEA_INT_ST_V  0x1
-#define MCPWM_OP2_TEA_INT_ST_S  17
-/* MCPWM_OP1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEA event*/
-#define MCPWM_OP1_TEA_INT_ST  (BIT(16))
-#define MCPWM_OP1_TEA_INT_ST_M  (BIT(16))
-#define MCPWM_OP1_TEA_INT_ST_V  0x1
-#define MCPWM_OP1_TEA_INT_ST_S  16
-/* MCPWM_OP0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEA event*/
-#define MCPWM_OP0_TEA_INT_ST  (BIT(15))
-#define MCPWM_OP0_TEA_INT_ST_M  (BIT(15))
-#define MCPWM_OP0_TEA_INT_ST_V  0x1
-#define MCPWM_OP0_TEA_INT_ST_S  15
-/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered when event_f2 ends*/
-#define MCPWM_FAULT2_CLR_INT_ST  (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ST_M  (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ST_V  0x1
-#define MCPWM_FAULT2_CLR_INT_ST_S  14
-/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered when event_f1 ends*/
-#define MCPWM_FAULT1_CLR_INT_ST  (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ST_M  (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ST_V  0x1
-#define MCPWM_FAULT1_CLR_INT_ST_S  13
-/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered when event_f0 ends*/
-#define MCPWM_FAULT0_CLR_INT_ST  (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ST_M  (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ST_V  0x1
-#define MCPWM_FAULT0_CLR_INT_ST_S  12
-/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered when event_f2 starts*/
-#define MCPWM_FAULT2_INT_ST  (BIT(11))
-#define MCPWM_FAULT2_INT_ST_M  (BIT(11))
-#define MCPWM_FAULT2_INT_ST_V  0x1
-#define MCPWM_FAULT2_INT_ST_S  11
-/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered when event_f1 starts*/
-#define MCPWM_FAULT1_INT_ST  (BIT(10))
-#define MCPWM_FAULT1_INT_ST_M  (BIT(10))
-#define MCPWM_FAULT1_INT_ST_V  0x1
-#define MCPWM_FAULT1_INT_ST_S  10
-/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */
-/*description: The masked status bit for interrupt triggered when event_f0 starts*/
-#define MCPWM_FAULT0_INT_ST  (BIT(9))
-#define MCPWM_FAULT0_INT_ST_M  (BIT(9))
-#define MCPWM_FAULT0_INT_ST_V  0x1
-#define MCPWM_FAULT0_INT_ST_S  9
-/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEP event*/
-#define MCPWM_TIMER2_TEP_INT_ST  (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ST_M  (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ST_V  0x1
-#define MCPWM_TIMER2_TEP_INT_ST_S  8
-/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEP event*/
-#define MCPWM_TIMER1_TEP_INT_ST  (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ST_M  (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ST_V  0x1
-#define MCPWM_TIMER1_TEP_INT_ST_S  7
-/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEP event*/
-#define MCPWM_TIMER0_TEP_INT_ST  (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ST_M  (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ST_V  0x1
-#define MCPWM_TIMER0_TEP_INT_ST_S  6
-/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEZ event*/
-#define MCPWM_TIMER2_TEZ_INT_ST  (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ST_M  (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ST_V  0x1
-#define MCPWM_TIMER2_TEZ_INT_ST_S  5
-/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEZ event*/
-#define MCPWM_TIMER1_TEZ_INT_ST  (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ST_M  (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ST_V  0x1
-#define MCPWM_TIMER1_TEZ_INT_ST_S  4
-/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEZ event*/
-#define MCPWM_TIMER0_TEZ_INT_ST  (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ST_M  (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ST_V  0x1
-#define MCPWM_TIMER0_TEZ_INT_ST_S  3
-/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The masked status bit for interrupt triggered when timer 2 stops*/
-#define MCPWM_TIMER2_STOP_INT_ST  (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ST_M  (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ST_V  0x1
-#define MCPWM_TIMER2_STOP_INT_ST_S  2
-/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The masked status bit for interrupt triggered when timer 1 stops*/
-#define MCPWM_TIMER1_STOP_INT_ST  (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ST_M  (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ST_V  0x1
-#define MCPWM_TIMER1_STOP_INT_ST_S  1
-/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The masked status bit for interrupt triggered when timer 0 stops*/
-#define MCPWM_TIMER0_STOP_INT_ST  (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ST_M  (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ST_V  0x1
-#define MCPWM_TIMER0_STOP_INT_ST_S  0
-
-#define MCMCPWM_INT_CLR_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x011c)
-/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by captureon channel 2*/
-#define MCPWM_CAP2_INT_CLR  (BIT(29))
-#define MCPWM_CAP2_INT_CLR_M  (BIT(29))
-#define MCPWM_CAP2_INT_CLR_V  0x1
-#define MCPWM_CAP2_INT_CLR_S  29
-/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by captureon channel 1*/
-#define MCPWM_CAP1_INT_CLR  (BIT(28))
-#define MCPWM_CAP1_INT_CLR_M  (BIT(28))
-#define MCPWM_CAP1_INT_CLR_V  0x1
-#define MCPWM_CAP1_INT_CLR_S  28
-/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by captureon channel 0*/
-#define MCPWM_CAP0_INT_CLR  (BIT(27))
-#define MCPWM_CAP0_INT_CLR_M  (BIT(27))
-#define MCPWM_CAP0_INT_CLR_V  0x1
-#define MCPWM_CAP0_INT_CLR_S  27
-/* MCPWM_FH2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM2*/
-#define MCPWM_FH2_OST_INT_CLR  (BIT(26))
-#define MCPWM_FH2_OST_INT_CLR_M  (BIT(26))
-#define MCPWM_FH2_OST_INT_CLR_V  0x1
-#define MCPWM_FH2_OST_INT_CLR_S  26
-/* MCPWM_FH1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/
-#define MCPWM_FH1_OST_INT_CLR  (BIT(25))
-#define MCPWM_FH1_OST_INT_CLR_M  (BIT(25))
-#define MCPWM_FH1_OST_INT_CLR_V  0x1
-#define MCPWM_FH1_OST_INT_CLR_S  25
-/* MCPWM_FH0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/
-#define MCPWM_FH0_OST_INT_CLR  (BIT(24))
-#define MCPWM_FH0_OST_INT_CLR_M  (BIT(24))
-#define MCPWM_FH0_OST_INT_CLR_V  0x1
-#define MCPWM_FH0_OST_INT_CLR_S  24
-/* MCPWM_FH2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
- mode action on PWM2*/
-#define MCPWM_FH2_CBC_INT_CLR  (BIT(23))
-#define MCPWM_FH2_CBC_INT_CLR_M  (BIT(23))
-#define MCPWM_FH2_CBC_INT_CLR_V  0x1
-#define MCPWM_FH2_CBC_INT_CLR_S  23
-/* MCPWM_FH1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
- mode action on PWM1*/
-#define MCPWM_FH1_CBC_INT_CLR  (BIT(22))
-#define MCPWM_FH1_CBC_INT_CLR_M  (BIT(22))
-#define MCPWM_FH1_CBC_INT_CLR_V  0x1
-#define MCPWM_FH1_CBC_INT_CLR_S  22
-/* MCPWM_FH0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
- mode action on PWM0*/
-#define MCPWM_FH0_CBC_INT_CLR  (BIT(21))
-#define MCPWM_FH0_CBC_INT_CLR_M  (BIT(21))
-#define MCPWM_FH0_CBC_INT_CLR_V  0x1
-#define MCPWM_FH0_CBC_INT_CLR_S  21
-/* MCPWM_OP2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEB event*/
-#define MCPWM_OP2_TEB_INT_CLR  (BIT(20))
-#define MCPWM_OP2_TEB_INT_CLR_M  (BIT(20))
-#define MCPWM_OP2_TEB_INT_CLR_V  0x1
-#define MCPWM_OP2_TEB_INT_CLR_S  20
-/* MCPWM_OP1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEB event*/
-#define MCPWM_OP1_TEB_INT_CLR  (BIT(19))
-#define MCPWM_OP1_TEB_INT_CLR_M  (BIT(19))
-#define MCPWM_OP1_TEB_INT_CLR_V  0x1
-#define MCPWM_OP1_TEB_INT_CLR_S  19
-/* MCPWM_OP0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEB event*/
-#define MCPWM_OP0_TEB_INT_CLR  (BIT(18))
-#define MCPWM_OP0_TEB_INT_CLR_M  (BIT(18))
-#define MCPWM_OP0_TEB_INT_CLR_V  0x1
-#define MCPWM_OP0_TEB_INT_CLR_S  18
-/* MCPWM_OP2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEA event*/
-#define MCPWM_OP2_TEA_INT_CLR  (BIT(17))
-#define MCPWM_OP2_TEA_INT_CLR_M  (BIT(17))
-#define MCPWM_OP2_TEA_INT_CLR_V  0x1
-#define MCPWM_OP2_TEA_INT_CLR_S  17
-/* MCPWM_OP1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEA event*/
-#define MCPWM_OP1_TEA_INT_CLR  (BIT(16))
-#define MCPWM_OP1_TEA_INT_CLR_M  (BIT(16))
-#define MCPWM_OP1_TEA_INT_CLR_V  0x1
-#define MCPWM_OP1_TEA_INT_CLR_S  16
-/* MCPWM_OP0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEA event*/
-#define MCPWM_OP0_TEA_INT_CLR  (BIT(15))
-#define MCPWM_OP0_TEA_INT_CLR_M  (BIT(15))
-#define MCPWM_OP0_TEA_INT_CLR_V  0x1
-#define MCPWM_OP0_TEA_INT_CLR_S  15
-/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered when event_f2 ends*/
-#define MCPWM_FAULT2_CLR_INT_CLR  (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_CLR_M  (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_CLR_V  0x1
-#define MCPWM_FAULT2_CLR_INT_CLR_S  14
-/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered when event_f1 ends*/
-#define MCPWM_FAULT1_CLR_INT_CLR  (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_CLR_M  (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_CLR_V  0x1
-#define MCPWM_FAULT1_CLR_INT_CLR_S  13
-/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered when event_f0 ends*/
-#define MCPWM_FAULT0_CLR_INT_CLR  (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_CLR_M  (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_CLR_V  0x1
-#define MCPWM_FAULT0_CLR_INT_CLR_S  12
-/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered when event_f2 starts*/
-#define MCPWM_FAULT2_INT_CLR  (BIT(11))
-#define MCPWM_FAULT2_INT_CLR_M  (BIT(11))
-#define MCPWM_FAULT2_INT_CLR_V  0x1
-#define MCPWM_FAULT2_INT_CLR_S  11
-/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered when event_f1 starts*/
-#define MCPWM_FAULT1_INT_CLR  (BIT(10))
-#define MCPWM_FAULT1_INT_CLR_M  (BIT(10))
-#define MCPWM_FAULT1_INT_CLR_V  0x1
-#define MCPWM_FAULT1_INT_CLR_S  10
-/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */
-/*description: Set this bit to clear interrupt triggered when event_f0 starts*/
-#define MCPWM_FAULT0_INT_CLR  (BIT(9))
-#define MCPWM_FAULT0_INT_CLR_M  (BIT(9))
-#define MCPWM_FAULT0_INT_CLR_V  0x1
-#define MCPWM_FAULT0_INT_CLR_S  9
-/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEP event*/
-#define MCPWM_TIMER2_TEP_INT_CLR  (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_CLR_M  (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_CLR_V  0x1
-#define MCPWM_TIMER2_TEP_INT_CLR_S  8
-/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEP event*/
-#define MCPWM_TIMER1_TEP_INT_CLR  (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_CLR_M  (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_CLR_V  0x1
-#define MCPWM_TIMER1_TEP_INT_CLR_S  7
-/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEP event*/
-#define MCPWM_TIMER0_TEP_INT_CLR  (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_CLR_M  (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_CLR_V  0x1
-#define MCPWM_TIMER0_TEP_INT_CLR_S  6
-/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event*/
-#define MCPWM_TIMER2_TEZ_INT_CLR  (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_CLR_M  (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x1
-#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
-/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event*/
-#define MCPWM_TIMER1_TEZ_INT_CLR  (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_CLR_M  (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x1
-#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
-/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event*/
-#define MCPWM_TIMER0_TEZ_INT_CLR  (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_CLR_M  (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x1
-#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
-/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to clear interrupt triggered when timer 2 stops*/
-#define MCPWM_TIMER2_STOP_INT_CLR  (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_CLR_M  (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_CLR_V  0x1
-#define MCPWM_TIMER2_STOP_INT_CLR_S  2
-/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Set this bit to clear interrupt triggered when timer 1 stops*/
-#define MCPWM_TIMER1_STOP_INT_CLR  (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_CLR_M  (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_CLR_V  0x1
-#define MCPWM_TIMER1_STOP_INT_CLR_S  1
-/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to clear interrupt triggered when timer 0 stops*/
-#define MCPWM_TIMER0_STOP_INT_CLR  (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_CLR_M  (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_CLR_V  0x1
-#define MCPWM_TIMER0_STOP_INT_CLR_S  0
-
-#define MCPWM_CLK_REG(i)          (REG_MCPWM_BASE(i) + 0x0120)
-/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Force clock on for this reg file*/
-#define MCPWM_CLK_EN  (BIT(0))
-#define MCPWM_CLK_EN_M  (BIT(0))
-#define MCPWM_CLK_EN_V  0x1
-#define MCPWM_CLK_EN_S  0
-
-#define MCPWM_VERSION_REG(i)          (REG_MCPWM_BASE(i) + 0x0124)
-/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */
-/*description: Version of this reg file*/
-#define MCPWM_DATE  0x0FFFFFFF
-#define MCPWM_DATE_M  ((MCPWM_DATE_V)<<(MCPWM_DATE_S))
-#define MCPWM_DATE_V  0xFFFFFFF
-#define MCPWM_DATE_S  0
-
-
-
-
-#endif /*_SOC_MCPWM_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/mcpwm_struct.h b/tools/sdk/include/soc/soc/mcpwm_struct.h
deleted file mode 100644
index 1d5110bf8c9..00000000000
--- a/tools/sdk/include/soc/soc/mcpwm_struct.h
+++ /dev/null
@@ -1,464 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_MCPWM_STRUCT_H__
-#define _SOC_MCPWM_STRUCT_H__
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t prescale: 8;                  /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
-            uint32_t reserved8:   24;
-        };
-        uint32_t val;
-    }clk_cfg;
-    struct {
-        union {
-            struct {
-                uint32_t prescale:        8;        /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
-                uint32_t period:         16;        /*period shadow reg of PWM timer0*/
-                uint32_t upmethod: 2;        /*Update method for active reg of PWM timer0 period  0: immediate  1: TEZ  2: sync  3: TEZ | sync. TEZ here and below means timer equal zero event*/
-                uint32_t reserved26:      6;
-            };
-            uint32_t val;
-        }period;
-        union {
-            struct {
-                uint32_t start: 3;                  /*PWM timer0 start and stop control. 0: stop @ TEZ  1: stop @ TEP  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP. TEP here and below means timer equal period event*/
-                uint32_t mode:   2;                  /*PWM timer0 working mode  0: freeze  1: increase mod  2: decrease mod  3: up-down mod*/
-                uint32_t reserved5:   27;
-            };
-            uint32_t val;
-        }mode;
-        union {
-            struct {
-                uint32_t in_en:     1;              /*when set   timer reload with phase on sync input event is enabled*/
-                uint32_t sync_sw:   1;              /*write the negate value will trigger a software sync*/
-                uint32_t out_sel: 2;              /*PWM timer0 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
-                uint32_t timer_phase:    17;              /*phase for timer reload on sync event*/
-                uint32_t reserved21:      11;
-            };
-            uint32_t val;
-        }sync;
-        union {
-            struct {
-                uint32_t value:    16;              /*current PWM timer0 counter value*/
-                uint32_t direction: 1;              /*current PWM timer0 counter direction  0: increment 1: decrement*/
-                uint32_t reserved17:      15;
-            };
-            uint32_t val;
-        }status;
-    }timer[3];
-
-
-    union {
-        struct {
-            uint32_t t0_in_sel:   3;        /*select sync input for PWM timer0  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
-            uint32_t t1_in_sel:   3;        /*select sync input for PWM timer1  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
-            uint32_t t2_in_sel:   3;        /*select sync input for PWM timer2  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
-            uint32_t ext_in0_inv: 1;        /*invert SYNC0 from GPIO matrix*/
-            uint32_t ext_in1_inv: 1;        /*invert SYNC1 from GPIO matrix*/
-            uint32_t ext_in2_inv: 1;        /*invert SYNC2 from GPIO matrix*/
-            uint32_t reserved12:            20;
-        };
-        uint32_t val;
-    }timer_synci_cfg;
-    union {
-        struct {
-            uint32_t operator0_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator0  0: timer0  1: timer1  2: timer2*/
-            uint32_t operator1_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator1  0: timer0  1: timer1  2: timer2*/
-            uint32_t operator2_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator2  0: timer0  1: timer1  2: timer2*/
-            uint32_t reserved6:         26;
-        };
-        uint32_t val;
-    }timer_sel;
-
-
-    struct {
-        union {
-            struct {
-                uint32_t a_upmethod:  4;             /*Update method for PWM compare0 A's active reg. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: freeze*/
-                uint32_t b_upmethod:  4;             /*Update method for PWM compare0 B's active reg. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: freeze*/
-                uint32_t a_shdw_full: 1;             /*Set and reset by hardware. If set  PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
-                uint32_t b_shdw_full: 1;             /*Set and reset by hardware. If set  PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
-                uint32_t reserved10:       22;
-            };
-            uint32_t val;
-        }cmpr_cfg;
-        union {
-            struct {
-                uint32_t cmpr_val:       16;                    /*PWM compare0 A's shadow reg*/
-                uint32_t reserved16:16;
-            };
-            uint32_t val;
-        }cmpr_value[2];
-        union {
-            struct {
-                uint32_t upmethod: 4;             /*Update method for PWM generate0's active reg of configuration. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: freeze*/
-                uint32_t t0_sel:       3;             /*Source selection for PWM generate0 event_t0  take effect immediately  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
-                uint32_t t1_sel:       3;             /*Source selection for PWM generate0 event_t1  take effect immediately  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
-                uint32_t reserved10:       22;
-            };
-            uint32_t val;
-        }gen_cfg0;
-        union {
-            struct {
-                uint32_t cntu_force_upmethod: 6;       /*Update method for continuous software force of PWM generate0. 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: freeze. (TEA/B here and below means timer equals A/B event)*/
-                uint32_t a_cntuforce_mode:   2;       /*Continuous software force mode for PWM0A. 0: disabled  1: low  2: high  3: disabled*/
-                uint32_t b_cntuforce_mode:   2;       /*Continuous software force mode for PWM0B. 0: disabled  1: low  2: high  3: disabled*/
-                uint32_t a_nciforce:         1;       /*non-continuous immediate software force trigger for PWM0A  a toggle will trigger a force event*/
-                uint32_t a_nciforce_mode:    2;       /*non-continuous immediate software force mode for PWM0A  0: disabled  1: low  2: high  3: disabled*/
-                uint32_t b_nciforce:         1;       /*non-continuous immediate software force trigger for PWM0B  a toggle will trigger a force event*/
-                uint32_t b_nciforce_mode:    2;       /*non-continuous immediate software force mode for PWM0B  0: disabled  1: low  2: high  3: disabled*/
-                uint32_t reserved16:             16;
-            };
-            uint32_t val;
-        }gen_force;
-        union {
-            struct {
-                uint32_t utez: 2;                   /*Action on PWM0A triggered by event TEZ when timer increasing*/
-                uint32_t utep: 2;                   /*Action on PWM0A triggered by event TEP when timer increasing*/
-                uint32_t utea: 2;                   /*Action on PWM0A triggered by event TEA when timer increasing*/
-                uint32_t uteb: 2;                   /*Action on PWM0A triggered by event TEB when timer increasing*/
-                uint32_t ut0:  2;                   /*Action on PWM0A triggered by event_t0 when timer increasing*/
-                uint32_t ut1:  2;                   /*Action on PWM0A triggered by event_t1 when timer increasing*/
-                uint32_t dtez: 2;                   /*Action on PWM0A triggered by event TEZ when timer decreasing*/
-                uint32_t dtep: 2;                   /*Action on PWM0A triggered by event TEP when timer decreasing*/
-                uint32_t dtea: 2;                   /*Action on PWM0A triggered by event TEA when timer decreasing*/
-                uint32_t dteb: 2;                   /*Action on PWM0A triggered by event TEB when timer decreasing*/
-                uint32_t dt0:  2;                   /*Action on PWM0A triggered by event_t0 when timer decreasing*/
-                uint32_t dt1:  2;                   /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change  1: low  2: high  3: toggle*/
-                uint32_t reserved24:  8;
-            };
-            uint32_t val;
-        }generator[2];
-        union {
-            struct {
-                uint32_t fed_upmethod:  4;             /*Update method for FED (falling edge delay) active reg. 0: immediate  bit0: tez  bit1: tep  bit2: sync  bit3: freeze*/
-                uint32_t red_upmethod:  4;             /*Update method for RED (rising edge delay) active reg. 0: immediate  bit0: tez  bit1: tep  bit2: sync  bit3: freeze*/
-                uint32_t deb_mode:      1;             /*S8 in documentation  dual-edge B mode  0: fed/red take effect on different path separately  1: fed/red take effect on B path  A out is in bypass or dulpB mode*/
-                uint32_t a_outswap:     1;             /*S6 in documentation*/
-                uint32_t b_outswap:     1;             /*S7 in documentation*/
-                uint32_t red_insel:     1;             /*S4 in documentation*/
-                uint32_t fed_insel:     1;             /*S5 in documentation*/
-                uint32_t red_outinvert: 1;             /*S2 in documentation*/
-                uint32_t fed_outinvert: 1;             /*S3 in documentation*/
-                uint32_t a_outbypass:   1;             /*S1 in documentation*/
-                uint32_t b_outbypass:   1;             /*S0 in documentation*/
-                uint32_t clk_sel:       1;             /*Dead band0 clock selection. 0: PWM_clk  1: PT_clk*/
-                uint32_t reserved18:   14;
-            };
-            uint32_t val;
-        }db_cfg;
-        union {
-            struct {
-                uint32_t fed:   16;                    /*Shadow reg for FED*/
-                uint32_t reserved16:16;
-            };
-            uint32_t val;
-        }db_fed_cfg;
-        union {
-            struct {
-                uint32_t red:   16;                    /*Shadow reg for RED*/
-                uint32_t reserved16:16;
-            };
-            uint32_t val;
-        }db_red_cfg;
-        union {
-            struct {
-                uint32_t en:         1;           /*When set  carrier0 function is enabled. When reset  carrier0 is bypassed*/
-                uint32_t prescale:   4;           /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
-                uint32_t duty:       3;           /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
-                uint32_t oshtwth:    4;           /*width of the fist pulse in number of periods of the carrier*/
-                uint32_t out_invert: 1;           /*when set  invert the output of PWM0A and PWM0B for this submodule*/
-                uint32_t in_invert:  1;           /*when set  invert the input of PWM0A and PWM0B for this submodule*/
-                uint32_t reserved14:         18;
-            };
-            uint32_t val;
-        }carrier_cfg;
-        union {
-            struct {
-                uint32_t sw_cbc:  1;                   /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
-                uint32_t f2_cbc:  1;                   /*event_f2 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
-                uint32_t f1_cbc:  1;                   /*event_f1 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
-                uint32_t f0_cbc:  1;                   /*event_f0 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
-                uint32_t sw_ost:  1;                   /*one-shot tripping software force event will trigger one-shot trip event. 0: disable  1: enable*/
-                uint32_t f2_ost:  1;                   /*event_f2 will trigger one-shot trip event. 0: disable  1: enable*/
-                uint32_t f1_ost:  1;                   /*event_f1 will trigger one-shot trip event. 0: disable  1: enable*/
-                uint32_t f0_ost:  1;                   /*event_f0 will trigger one-shot trip event. 0: disable  1: enable*/
-                uint32_t a_cbc_d: 2;                   /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-                uint32_t a_cbc_u: 2;                   /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-                uint32_t a_ost_d: 2;                   /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-                uint32_t a_ost_u: 2;                   /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-                uint32_t b_cbc_d: 2;                   /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-                uint32_t b_cbc_u: 2;                   /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-                uint32_t b_ost_d: 2;                   /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-                uint32_t b_ost_u: 2;                   /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
-                uint32_t reserved24:  8;
-            };
-            uint32_t val;
-        }tz_cfg0;
-        union {
-            struct {
-                uint32_t clr_ost:   1;                 /*a toggle will clear on going one-shot tripping*/
-                uint32_t cbcpulse:  2;                 /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ  bit1:TEP*/
-                uint32_t force_cbc: 1;                 /*a toggle trigger a cycle-by-cycle tripping software force event*/
-                uint32_t force_ost: 1;                 /*a toggle (software negate its value) trigger a one-shot tripping software force event*/
-                uint32_t reserved5:    27;
-            };
-            uint32_t val;
-        }tz_cfg1;
-        union {
-            struct {
-                uint32_t cbc_on: 1;                    /*Set and reset by hardware. If set  an cycle-by-cycle trip event is on going*/
-                uint32_t ost_on: 1;                    /*Set and reset by hardware. If set  an one-shot trip event is on going*/
-                uint32_t reserved2: 30;
-            };
-            uint32_t val;
-        }tz_status;
-    }channel[3];
-
-    union {
-        struct {
-            uint32_t f0_en:      1;                    /*When set  event_f0 generation is enabled*/
-            uint32_t f1_en:      1;                    /*When set  event_f1 generation is enabled*/
-            uint32_t f2_en:      1;                    /*When set  event_f2 generation is enabled*/
-            uint32_t f0_pole:    1;                    /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
-            uint32_t f1_pole:    1;                    /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
-            uint32_t f2_pole:    1;                    /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
-            uint32_t event_f0:   1;                    /*Set and reset by hardware. If set  event_f0 is on going*/
-            uint32_t event_f1:   1;                    /*Set and reset by hardware. If set  event_f1 is on going*/
-            uint32_t event_f2:   1;                    /*Set and reset by hardware. If set  event_f2 is on going*/
-            uint32_t reserved9: 23;
-        };
-        uint32_t val;
-    }fault_detect;
-    union {
-        struct {
-            uint32_t timer_en:  1;                 /*When set  capture timer incrementing under APB_clk is enabled.*/
-            uint32_t synci_en:  1;                 /*When set  capture timer sync is enabled.*/
-            uint32_t synci_sel: 3;                 /*capture module sync input selection. 0: none  1: timer0 synco  2: timer1 synco  3: timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix*/
-            uint32_t sync_sw:   1;                 /*Write 1 will force a capture timer sync  capture timer is loaded with value in phase register.*/
-            uint32_t reserved6:    26;
-        };
-        uint32_t val;
-    }cap_timer_cfg;
-    uint32_t cap_timer_phase;                      /*Phase value for capture timer sync operation.*/
-    union {
-        struct {
-            uint32_t en:        1;                /*When set  capture on channel 0 is enabled*/
-            uint32_t mode:      2;                /*Edge of capture on channel 0 after prescale.  bit0: negedge cap en  bit1: posedge cap en*/
-            uint32_t prescale:  8;                /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/
-            uint32_t in_invert: 1;                /*when set  CAP0 form GPIO matrix is inverted before prescale*/
-            uint32_t sw:        1;                /*Write 1 will trigger a software forced capture on channel 0*/
-            uint32_t reserved13:    19;
-        };
-        uint32_t val;
-    }cap_cfg_ch[3];
-    uint32_t cap_val_ch[3];                              /*Value of last capture on channel 0*/
-    union {
-        struct {
-            uint32_t cap0_edge:  1;                    /*Edge of last capture trigger on channel 0  0: posedge  1: negedge*/
-            uint32_t cap1_edge:  1;                    /*Edge of last capture trigger on channel 1  0: posedge  1: negedge*/
-            uint32_t cap2_edge:  1;                    /*Edge of last capture trigger on channel 2  0: posedge  1: negedge*/
-            uint32_t reserved3: 29;
-        };
-        uint32_t val;
-    }cap_status;
-    union {
-        struct {
-            uint32_t global_up_en:    1;               /*The global enable of update of all active registers in MCPWM module*/
-            uint32_t global_force_up: 1;               /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/
-            uint32_t op0_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 0 are enabled*/
-            uint32_t op0_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/
-            uint32_t op1_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 1 are enabled*/
-            uint32_t op1_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/
-            uint32_t op2_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 2 are enabled*/
-            uint32_t op2_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/
-            uint32_t reserved8:      24;
-        };
-        uint32_t val;
-    }update_cfg;
-    union {
-        struct {
-            uint32_t timer0_stop_int_ena: 1;           /*Interrupt when timer 0 stops*/
-            uint32_t timer1_stop_int_ena: 1;           /*Interrupt when timer 1 stops*/
-            uint32_t timer2_stop_int_ena: 1;           /*Interrupt when timer 2 stops*/
-            uint32_t timer0_tez_int_ena:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
-            uint32_t timer1_tez_int_ena:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
-            uint32_t timer2_tez_int_ena:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
-            uint32_t timer0_tep_int_ena:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
-            uint32_t timer1_tep_int_ena:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
-            uint32_t timer2_tep_int_ena:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
-            uint32_t fault0_int_ena:      1;           /*Interrupt when event_f0 starts*/
-            uint32_t fault1_int_ena:      1;           /*Interrupt when event_f1 starts*/
-            uint32_t fault2_int_ena:      1;           /*Interrupt when event_f2 starts*/
-            uint32_t fault0_clr_int_ena:  1;           /*Interrupt when event_f0 ends*/
-            uint32_t fault1_clr_int_ena:  1;           /*Interrupt when event_f1 ends*/
-            uint32_t fault2_clr_int_ena:  1;           /*Interrupt when event_f2 ends*/
-            uint32_t cmpr0_tea_int_ena:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
-            uint32_t cmpr1_tea_int_ena:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
-            uint32_t cmpr2_tea_int_ena:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
-            uint32_t cmpr0_teb_int_ena:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
-            uint32_t cmpr1_teb_int_ena:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
-            uint32_t cmpr2_teb_int_ena:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
-            uint32_t tz0_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
-            uint32_t tz1_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
-            uint32_t tz2_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
-            uint32_t tz0_ost_int_ena:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
-            uint32_t tz1_ost_int_ena:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
-            uint32_t tz2_ost_int_ena:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
-            uint32_t cap0_int_ena:        1;           /*A capture on channel 0 will trigger this interrupt*/
-            uint32_t cap1_int_ena:        1;           /*A capture on channel 1 will trigger this interrupt*/
-            uint32_t cap2_int_ena:        1;           /*A capture on channel 2 will trigger this interrupt*/
-            uint32_t reserved30:          2;
-        };
-        uint32_t val;
-    }int_ena;
-    union {
-        struct {
-            uint32_t timer0_stop_int_raw: 1;           /*Interrupt when timer 0 stops*/
-            uint32_t timer1_stop_int_raw: 1;           /*Interrupt when timer 1 stops*/
-            uint32_t timer2_stop_int_raw: 1;           /*Interrupt when timer 2 stops*/
-            uint32_t timer0_tez_int_raw:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
-            uint32_t timer1_tez_int_raw:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
-            uint32_t timer2_tez_int_raw:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
-            uint32_t timer0_tep_int_raw:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
-            uint32_t timer1_tep_int_raw:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
-            uint32_t timer2_tep_int_raw:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
-            uint32_t fault0_int_raw:      1;           /*Interrupt when event_f0 starts*/
-            uint32_t fault1_int_raw:      1;           /*Interrupt when event_f1 starts*/
-            uint32_t fault2_int_raw:      1;           /*Interrupt when event_f2 starts*/
-            uint32_t fault0_clr_int_raw:  1;           /*Interrupt when event_f0 ends*/
-            uint32_t fault1_clr_int_raw:  1;           /*Interrupt when event_f1 ends*/
-            uint32_t fault2_clr_int_raw:  1;           /*Interrupt when event_f2 ends*/
-            uint32_t cmpr0_tea_int_raw:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
-            uint32_t cmpr1_tea_int_raw:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
-            uint32_t cmpr2_tea_int_raw:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
-            uint32_t cmpr0_teb_int_raw:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
-            uint32_t cmpr1_teb_int_raw:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
-            uint32_t cmpr2_teb_int_raw:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
-            uint32_t tz0_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
-            uint32_t tz1_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
-            uint32_t tz2_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
-            uint32_t tz0_ost_int_raw:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
-            uint32_t tz1_ost_int_raw:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
-            uint32_t tz2_ost_int_raw:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
-            uint32_t cap0_int_raw:        1;           /*A capture on channel 0 will trigger this interrupt*/
-            uint32_t cap1_int_raw:        1;           /*A capture on channel 1 will trigger this interrupt*/
-            uint32_t cap2_int_raw:        1;           /*A capture on channel 2 will trigger this interrupt*/
-            uint32_t reserved30:          2;
-        };
-        uint32_t val;
-    }int_raw;
-    union {
-        struct {
-            uint32_t timer0_stop_int_st: 1;            /*Interrupt when timer 0 stops*/
-            uint32_t timer1_stop_int_st: 1;            /*Interrupt when timer 1 stops*/
-            uint32_t timer2_stop_int_st: 1;            /*Interrupt when timer 2 stops*/
-            uint32_t timer0_tez_int_st:  1;            /*A PWM timer 0 TEZ event will trigger this interrupt*/
-            uint32_t timer1_tez_int_st:  1;            /*A PWM timer 1 TEZ event will trigger this interrupt*/
-            uint32_t timer2_tez_int_st:  1;            /*A PWM timer 2 TEZ event will trigger this interrupt*/
-            uint32_t timer0_tep_int_st:  1;            /*A PWM timer 0 TEP event will trigger this interrupt*/
-            uint32_t timer1_tep_int_st:  1;            /*A PWM timer 1 TEP event will trigger this interrupt*/
-            uint32_t timer2_tep_int_st:  1;            /*A PWM timer 2 TEP event will trigger this interrupt*/
-            uint32_t fault0_int_st:      1;            /*Interrupt when event_f0 starts*/
-            uint32_t fault1_int_st:      1;            /*Interrupt when event_f1 starts*/
-            uint32_t fault2_int_st:      1;            /*Interrupt when event_f2 starts*/
-            uint32_t fault0_clr_int_st:  1;            /*Interrupt when event_f0 ends*/
-            uint32_t fault1_clr_int_st:  1;            /*Interrupt when event_f1 ends*/
-            uint32_t fault2_clr_int_st:  1;            /*Interrupt when event_f2 ends*/
-            uint32_t cmpr0_tea_int_st:   1;            /*A PWM operator 0 TEA event will trigger this interrupt*/
-            uint32_t cmpr1_tea_int_st:   1;            /*A PWM operator 1 TEA event will trigger this interrupt*/
-            uint32_t cmpr2_tea_int_st:   1;            /*A PWM operator 2 TEA event will trigger this interrupt*/
-            uint32_t cmpr0_teb_int_st:   1;            /*A PWM operator 0 TEB event will trigger this interrupt*/
-            uint32_t cmpr1_teb_int_st:   1;            /*A PWM operator 1 TEB event will trigger this interrupt*/
-            uint32_t cmpr2_teb_int_st:   1;            /*A PWM operator 2 TEB event will trigger this interrupt*/
-            uint32_t tz0_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
-            uint32_t tz1_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
-            uint32_t tz2_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
-            uint32_t tz0_ost_int_st:     1;            /*An one-shot trip event on PWM0 will trigger this interrupt*/
-            uint32_t tz1_ost_int_st:     1;            /*An one-shot trip event on PWM1 will trigger this interrupt*/
-            uint32_t tz2_ost_int_st:     1;            /*An one-shot trip event on PWM2 will trigger this interrupt*/
-            uint32_t cap0_int_st:        1;            /*A capture on channel 0 will trigger this interrupt*/
-            uint32_t cap1_int_st:        1;            /*A capture on channel 1 will trigger this interrupt*/
-            uint32_t cap2_int_st:        1;            /*A capture on channel 2 will trigger this interrupt*/
-            uint32_t reserved30:         2;
-        };
-        uint32_t val;
-    }int_st;
-    union {
-        struct {
-            uint32_t timer0_stop_int_clr: 1;           /*Interrupt when timer 0 stops*/
-            uint32_t timer1_stop_int_clr: 1;           /*Interrupt when timer 1 stops*/
-            uint32_t timer2_stop_int_clr: 1;           /*Interrupt when timer 2 stops*/
-            uint32_t timer0_tez_int_clr:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
-            uint32_t timer1_tez_int_clr:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
-            uint32_t timer2_tez_int_clr:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
-            uint32_t timer0_tep_int_clr:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
-            uint32_t timer1_tep_int_clr:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
-            uint32_t timer2_tep_int_clr:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
-            uint32_t fault0_int_clr:      1;           /*Interrupt when event_f0 starts*/
-            uint32_t fault1_int_clr:      1;           /*Interrupt when event_f1 starts*/
-            uint32_t fault2_int_clr:      1;           /*Interrupt when event_f2 starts*/
-            uint32_t fault0_clr_int_clr:  1;           /*Interrupt when event_f0 ends*/
-            uint32_t fault1_clr_int_clr:  1;           /*Interrupt when event_f1 ends*/
-            uint32_t fault2_clr_int_clr:  1;           /*Interrupt when event_f2 ends*/
-            uint32_t cmpr0_tea_int_clr:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
-            uint32_t cmpr1_tea_int_clr:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
-            uint32_t cmpr2_tea_int_clr:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
-            uint32_t cmpr0_teb_int_clr:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
-            uint32_t cmpr1_teb_int_clr:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
-            uint32_t cmpr2_teb_int_clr:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
-            uint32_t tz0_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
-            uint32_t tz1_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
-            uint32_t tz2_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
-            uint32_t tz0_ost_int_clr:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
-            uint32_t tz1_ost_int_clr:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
-            uint32_t tz2_ost_int_clr:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
-            uint32_t cap0_int_clr:        1;           /*A capture on channel 0 will trigger this interrupt*/
-            uint32_t cap1_int_clr:        1;           /*A capture on channel 1 will trigger this interrupt*/
-            uint32_t cap2_int_clr:        1;           /*A capture on channel 2 will trigger this interrupt*/
-            uint32_t reserved30:          2;
-        };
-        uint32_t val;
-    }int_clr;
-    union {
-        struct {
-            uint32_t clk_en:     1;                    /*Force clock on for this reg file*/
-            uint32_t reserved1: 31;
-        };
-        uint32_t val;
-    }reg_clk;
-    union {
-        struct {
-            uint32_t date:      28;                    /*Version of this reg file*/
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    }version;
-} mcpwm_dev_t;
-extern mcpwm_dev_t MCPWM0;
-extern mcpwm_dev_t MCPWM1;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_MCPWM_STRUCT_H__ */
diff --git a/tools/sdk/include/soc/soc/nrx_reg.h b/tools/sdk/include/soc/soc/nrx_reg.h
deleted file mode 100644
index ca338b89ab3..00000000000
--- a/tools/sdk/include/soc/soc/nrx_reg.h
+++ /dev/null
@@ -1,55 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "soc/soc.h"
-
-/* Some of the WiFi RX control registers.
- * PU/PD fields defined here are used in sleep related functions.
- */
-
-#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
-#define NRX_CHAN_EST_FORCE_PU (BIT(7))
-#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
-#define NRX_CHAN_EST_FORCE_PU_V 1
-#define NRX_CHAN_EST_FORCE_PU_S 7
-#define NRX_CHAN_EST_FORCE_PD (BIT(6))
-#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
-#define NRX_CHAN_EST_FORCE_PD_V 1
-#define NRX_CHAN_EST_FORCE_PD_S 6
-#define NRX_RX_ROT_FORCE_PU (BIT(5))
-#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
-#define NRX_RX_ROT_FORCE_PU_V 1
-#define NRX_RX_ROT_FORCE_PU_S 5
-#define NRX_RX_ROT_FORCE_PD (BIT(4))
-#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
-#define NRX_RX_ROT_FORCE_PD_V 1
-#define NRX_RX_ROT_FORCE_PD_S 4
-#define NRX_VIT_FORCE_PU (BIT(3))
-#define NRX_VIT_FORCE_PU_M (BIT(3))
-#define NRX_VIT_FORCE_PU_V 1
-#define NRX_VIT_FORCE_PU_S 3
-#define NRX_VIT_FORCE_PD (BIT(2))
-#define NRX_VIT_FORCE_PD_M (BIT(2))
-#define NRX_VIT_FORCE_PD_V 1
-#define NRX_VIT_FORCE_PD_S 2
-#define NRX_DEMAP_FORCE_PU (BIT(1))
-#define NRX_DEMAP_FORCE_PU_M (BIT(1))
-#define NRX_DEMAP_FORCE_PU_V 1
-#define NRX_DEMAP_FORCE_PU_S 1
-#define NRX_DEMAP_FORCE_PD (BIT(0))
-#define NRX_DEMAP_FORCE_PD_M (BIT(0))
-#define NRX_DEMAP_FORCE_PD_V 1
-#define NRX_DEMAP_FORCE_PD_S 0
diff --git a/tools/sdk/include/soc/soc/pcnt_reg.h b/tools/sdk/include/soc/soc/pcnt_reg.h
deleted file mode 100644
index fa7dedc2528..00000000000
--- a/tools/sdk/include/soc/soc/pcnt_reg.h
+++ /dev/null
@@ -1,1526 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_PCNT_REG_H_
-#define _SOC_PCNT_REG_H_
-
-
-#include "soc.h"
-#define PCNT_U0_CONF0_REG          (DR_REG_PCNT_BASE + 0x0000)
-/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's low control
- signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_LCTRL_MODE_U0  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U0_M  ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S))
-#define PCNT_CH1_LCTRL_MODE_U0_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U0_S  30
-/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's high
- control signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_HCTRL_MODE_U0  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U0_M  ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S))
-#define PCNT_CH1_HCTRL_MODE_U0_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U0_S  28
-/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- posedge signal for unit0. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH1_POS_MODE_U0  0x00000003
-#define PCNT_CH1_POS_MODE_U0_M  ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S))
-#define PCNT_CH1_POS_MODE_U0_V  0x3
-#define PCNT_CH1_POS_MODE_U0_S  26
-/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- negedge signal for unit0. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH1_NEG_MODE_U0  0x00000003
-#define PCNT_CH1_NEG_MODE_U0_M  ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S))
-#define PCNT_CH1_NEG_MODE_U0_V  0x3
-#define PCNT_CH1_NEG_MODE_U0_S  24
-/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's low control
- signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_LCTRL_MODE_U0  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U0_M  ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S))
-#define PCNT_CH0_LCTRL_MODE_U0_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U0_S  22
-/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's high
- control signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_HCTRL_MODE_U0  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U0_M  ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S))
-#define PCNT_CH0_HCTRL_MODE_U0_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U0_S  20
-/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- posedge signal for unit0. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH0_POS_MODE_U0  0x00000003
-#define PCNT_CH0_POS_MODE_U0_M  ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S))
-#define PCNT_CH0_POS_MODE_U0_V  0x3
-#define PCNT_CH0_POS_MODE_U0_S  18
-/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- negedge signal for unit0. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH0_NEG_MODE_U0  0x00000003
-#define PCNT_CH0_NEG_MODE_U0_M  ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S))
-#define PCNT_CH0_NEG_MODE_U0_V  0x3
-#define PCNT_CH0_NEG_MODE_U0_S  16
-/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for  comparing  unit0's count with thres1 value .*/
-#define PCNT_THR_THRES1_EN_U0  (BIT(15))
-#define PCNT_THR_THRES1_EN_U0_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U0_V  0x1
-#define PCNT_THR_THRES1_EN_U0_S  15
-/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for comparing unit0's count with  thres0 value.*/
-#define PCNT_THR_THRES0_EN_U0  (BIT(14))
-#define PCNT_THR_THRES0_EN_U0_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U0_V  0x1
-#define PCNT_THR_THRES0_EN_U0_S  14
-/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit0's count with thr_l_lim  value.*/
-#define PCNT_THR_L_LIM_EN_U0  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U0_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U0_V  0x1
-#define PCNT_THR_L_LIM_EN_U0_S  13
-/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: This is the enable bit for  comparing unit0's count with thr_h_lim value.*/
-#define PCNT_THR_H_LIM_EN_U0  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U0_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U0_V  0x1
-#define PCNT_THR_H_LIM_EN_U0_S  12
-/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit0's count with 0 value.*/
-#define PCNT_THR_ZERO_EN_U0  (BIT(11))
-#define PCNT_THR_ZERO_EN_U0_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U0_V  0x1
-#define PCNT_THR_ZERO_EN_U0_S  11
-/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: This is the enable bit for filtering input signals for unit0.*/
-#define PCNT_FILTER_EN_U0  (BIT(10))
-#define PCNT_FILTER_EN_U0_M  (BIT(10))
-#define PCNT_FILTER_EN_U0_V  0x1
-#define PCNT_FILTER_EN_U0_S  10
-/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: This register is used to filter pluse whose width is smaller
- than this value for unit0.*/
-#define PCNT_FILTER_THRES_U0  0x000003FF
-#define PCNT_FILTER_THRES_U0_M  ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S))
-#define PCNT_FILTER_THRES_U0_V  0x3FF
-#define PCNT_FILTER_THRES_U0_S  0
-
-#define PCNT_U0_CONF1_REG          (DR_REG_PCNT_BASE + 0x0004)
-/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to configure  thres1 value for unit0.*/
-#define PCNT_CNT_THRES1_U0  0x0000FFFF
-#define PCNT_CNT_THRES1_U0_M  ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S))
-#define PCNT_CNT_THRES1_U0_V  0xFFFF
-#define PCNT_CNT_THRES1_U0_S  16
-/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thres0 value for unit0.*/
-#define PCNT_CNT_THRES0_U0  0x0000FFFF
-#define PCNT_CNT_THRES0_U0_M  ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S))
-#define PCNT_CNT_THRES0_U0_V  0xFFFF
-#define PCNT_CNT_THRES0_U0_S  0
-
-#define PCNT_U0_CONF2_REG          (DR_REG_PCNT_BASE + 0x0008)
-/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to confiugre thr_l_lim value for unit0.*/
-#define PCNT_CNT_L_LIM_U0  0x0000FFFF
-#define PCNT_CNT_L_LIM_U0_M  ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S))
-#define PCNT_CNT_L_LIM_U0_V  0xFFFF
-#define PCNT_CNT_L_LIM_U0_S  16
-/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thr_h_lim value for unit0.*/
-#define PCNT_CNT_H_LIM_U0  0x0000FFFF
-#define PCNT_CNT_H_LIM_U0_M  ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S))
-#define PCNT_CNT_H_LIM_U0_V  0xFFFF
-#define PCNT_CNT_H_LIM_U0_S  0
-
-#define PCNT_U1_CONF0_REG          (DR_REG_PCNT_BASE + 0x000c)
-/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's low control
- signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_LCTRL_MODE_U1  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U1_M  ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S))
-#define PCNT_CH1_LCTRL_MODE_U1_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U1_S  30
-/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's high
- control signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_HCTRL_MODE_U1  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U1_M  ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S))
-#define PCNT_CH1_HCTRL_MODE_U1_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U1_S  28
-/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- posedge signal for unit1. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH1_POS_MODE_U1  0x00000003
-#define PCNT_CH1_POS_MODE_U1_M  ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S))
-#define PCNT_CH1_POS_MODE_U1_V  0x3
-#define PCNT_CH1_POS_MODE_U1_S  26
-/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- negedge signal for unit1. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH1_NEG_MODE_U1  0x00000003
-#define PCNT_CH1_NEG_MODE_U1_M  ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S))
-#define PCNT_CH1_NEG_MODE_U1_V  0x3
-#define PCNT_CH1_NEG_MODE_U1_S  24
-/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's low control
- signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_LCTRL_MODE_U1  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U1_M  ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S))
-#define PCNT_CH0_LCTRL_MODE_U1_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U1_S  22
-/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's high
- control signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_HCTRL_MODE_U1  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U1_M  ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S))
-#define PCNT_CH0_HCTRL_MODE_U1_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U1_S  20
-/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- posedge signal for unit1. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH0_POS_MODE_U1  0x00000003
-#define PCNT_CH0_POS_MODE_U1_M  ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S))
-#define PCNT_CH0_POS_MODE_U1_V  0x3
-#define PCNT_CH0_POS_MODE_U1_S  18
-/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- negedge signal for unit1. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH0_NEG_MODE_U1  0x00000003
-#define PCNT_CH0_NEG_MODE_U1_M  ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S))
-#define PCNT_CH0_NEG_MODE_U1_V  0x3
-#define PCNT_CH0_NEG_MODE_U1_S  16
-/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for  comparing  unit1's count with thres1 value .*/
-#define PCNT_THR_THRES1_EN_U1  (BIT(15))
-#define PCNT_THR_THRES1_EN_U1_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U1_V  0x1
-#define PCNT_THR_THRES1_EN_U1_S  15
-/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for comparing unit1's count with  thres0 value.*/
-#define PCNT_THR_THRES0_EN_U1  (BIT(14))
-#define PCNT_THR_THRES0_EN_U1_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U1_V  0x1
-#define PCNT_THR_THRES0_EN_U1_S  14
-/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit1's count with thr_l_lim  value.*/
-#define PCNT_THR_L_LIM_EN_U1  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U1_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U1_V  0x1
-#define PCNT_THR_L_LIM_EN_U1_S  13
-/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: This is the enable bit for  comparing unit1's count with thr_h_lim value.*/
-#define PCNT_THR_H_LIM_EN_U1  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U1_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U1_V  0x1
-#define PCNT_THR_H_LIM_EN_U1_S  12
-/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit1's count with 0 value.*/
-#define PCNT_THR_ZERO_EN_U1  (BIT(11))
-#define PCNT_THR_ZERO_EN_U1_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U1_V  0x1
-#define PCNT_THR_ZERO_EN_U1_S  11
-/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: This is the enable bit for filtering input signals for unit1.*/
-#define PCNT_FILTER_EN_U1  (BIT(10))
-#define PCNT_FILTER_EN_U1_M  (BIT(10))
-#define PCNT_FILTER_EN_U1_V  0x1
-#define PCNT_FILTER_EN_U1_S  10
-/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: This register is used to filter pluse whose width is smaller
- than this value for unit1.*/
-#define PCNT_FILTER_THRES_U1  0x000003FF
-#define PCNT_FILTER_THRES_U1_M  ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S))
-#define PCNT_FILTER_THRES_U1_V  0x3FF
-#define PCNT_FILTER_THRES_U1_S  0
-
-#define PCNT_U1_CONF1_REG          (DR_REG_PCNT_BASE + 0x0010)
-/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to configure  thres1 value for unit1.*/
-#define PCNT_CNT_THRES1_U1  0x0000FFFF
-#define PCNT_CNT_THRES1_U1_M  ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S))
-#define PCNT_CNT_THRES1_U1_V  0xFFFF
-#define PCNT_CNT_THRES1_U1_S  16
-/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thres0 value for unit1.*/
-#define PCNT_CNT_THRES0_U1  0x0000FFFF
-#define PCNT_CNT_THRES0_U1_M  ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S))
-#define PCNT_CNT_THRES0_U1_V  0xFFFF
-#define PCNT_CNT_THRES0_U1_S  0
-
-#define PCNT_U1_CONF2_REG          (DR_REG_PCNT_BASE + 0x0014)
-/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to confiugre thr_l_lim value for unit1.*/
-#define PCNT_CNT_L_LIM_U1  0x0000FFFF
-#define PCNT_CNT_L_LIM_U1_M  ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S))
-#define PCNT_CNT_L_LIM_U1_V  0xFFFF
-#define PCNT_CNT_L_LIM_U1_S  16
-/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thr_h_lim value for unit1.*/
-#define PCNT_CNT_H_LIM_U1  0x0000FFFF
-#define PCNT_CNT_H_LIM_U1_M  ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S))
-#define PCNT_CNT_H_LIM_U1_V  0xFFFF
-#define PCNT_CNT_H_LIM_U1_S  0
-
-#define PCNT_U2_CONF0_REG          (DR_REG_PCNT_BASE + 0x0018)
-/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's low control
- signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_LCTRL_MODE_U2  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U2_M  ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S))
-#define PCNT_CH1_LCTRL_MODE_U2_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U2_S  30
-/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's high
- control signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_HCTRL_MODE_U2  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U2_M  ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S))
-#define PCNT_CH1_HCTRL_MODE_U2_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U2_S  28
-/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- posedge signal for unit2. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH1_POS_MODE_U2  0x00000003
-#define PCNT_CH1_POS_MODE_U2_M  ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S))
-#define PCNT_CH1_POS_MODE_U2_V  0x3
-#define PCNT_CH1_POS_MODE_U2_S  26
-/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- negedge signal for unit2. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH1_NEG_MODE_U2  0x00000003
-#define PCNT_CH1_NEG_MODE_U2_M  ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S))
-#define PCNT_CH1_NEG_MODE_U2_V  0x3
-#define PCNT_CH1_NEG_MODE_U2_S  24
-/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's low control
- signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_LCTRL_MODE_U2  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U2_M  ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S))
-#define PCNT_CH0_LCTRL_MODE_U2_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U2_S  22
-/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's high
- control signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_HCTRL_MODE_U2  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U2_M  ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S))
-#define PCNT_CH0_HCTRL_MODE_U2_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U2_S  20
-/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- posedge signal for unit2. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH0_POS_MODE_U2  0x00000003
-#define PCNT_CH0_POS_MODE_U2_M  ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S))
-#define PCNT_CH0_POS_MODE_U2_V  0x3
-#define PCNT_CH0_POS_MODE_U2_S  18
-/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- negedge signal for unit2. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH0_NEG_MODE_U2  0x00000003
-#define PCNT_CH0_NEG_MODE_U2_M  ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S))
-#define PCNT_CH0_NEG_MODE_U2_V  0x3
-#define PCNT_CH0_NEG_MODE_U2_S  16
-/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for  comparing  unit2's count with thres1 value .*/
-#define PCNT_THR_THRES1_EN_U2  (BIT(15))
-#define PCNT_THR_THRES1_EN_U2_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U2_V  0x1
-#define PCNT_THR_THRES1_EN_U2_S  15
-/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for comparing unit2's count with  thres0 value.*/
-#define PCNT_THR_THRES0_EN_U2  (BIT(14))
-#define PCNT_THR_THRES0_EN_U2_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U2_V  0x1
-#define PCNT_THR_THRES0_EN_U2_S  14
-/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit2's count with thr_l_lim  value.*/
-#define PCNT_THR_L_LIM_EN_U2  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U2_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U2_V  0x1
-#define PCNT_THR_L_LIM_EN_U2_S  13
-/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: This is the enable bit for  comparing unit2's count with thr_h_lim value.*/
-#define PCNT_THR_H_LIM_EN_U2  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U2_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U2_V  0x1
-#define PCNT_THR_H_LIM_EN_U2_S  12
-/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit2's count with 0 value.*/
-#define PCNT_THR_ZERO_EN_U2  (BIT(11))
-#define PCNT_THR_ZERO_EN_U2_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U2_V  0x1
-#define PCNT_THR_ZERO_EN_U2_S  11
-/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: This is the enable bit for filtering input signals for unit2.*/
-#define PCNT_FILTER_EN_U2  (BIT(10))
-#define PCNT_FILTER_EN_U2_M  (BIT(10))
-#define PCNT_FILTER_EN_U2_V  0x1
-#define PCNT_FILTER_EN_U2_S  10
-/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: This register is used to filter pluse whose width is smaller
- than this value for unit2.*/
-#define PCNT_FILTER_THRES_U2  0x000003FF
-#define PCNT_FILTER_THRES_U2_M  ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S))
-#define PCNT_FILTER_THRES_U2_V  0x3FF
-#define PCNT_FILTER_THRES_U2_S  0
-
-#define PCNT_U2_CONF1_REG          (DR_REG_PCNT_BASE + 0x001c)
-/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to configure  thres1 value for unit2.*/
-#define PCNT_CNT_THRES1_U2  0x0000FFFF
-#define PCNT_CNT_THRES1_U2_M  ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S))
-#define PCNT_CNT_THRES1_U2_V  0xFFFF
-#define PCNT_CNT_THRES1_U2_S  16
-/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thres0 value for unit2.*/
-#define PCNT_CNT_THRES0_U2  0x0000FFFF
-#define PCNT_CNT_THRES0_U2_M  ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S))
-#define PCNT_CNT_THRES0_U2_V  0xFFFF
-#define PCNT_CNT_THRES0_U2_S  0
-
-#define PCNT_U2_CONF2_REG          (DR_REG_PCNT_BASE + 0x0020)
-/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to confiugre thr_l_lim value for unit2.*/
-#define PCNT_CNT_L_LIM_U2  0x0000FFFF
-#define PCNT_CNT_L_LIM_U2_M  ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S))
-#define PCNT_CNT_L_LIM_U2_V  0xFFFF
-#define PCNT_CNT_L_LIM_U2_S  16
-/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thr_h_lim value for unit2.*/
-#define PCNT_CNT_H_LIM_U2  0x0000FFFF
-#define PCNT_CNT_H_LIM_U2_M  ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S))
-#define PCNT_CNT_H_LIM_U2_V  0xFFFF
-#define PCNT_CNT_H_LIM_U2_S  0
-
-#define PCNT_U3_CONF0_REG          (DR_REG_PCNT_BASE + 0x0024)
-/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's low control
- signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_LCTRL_MODE_U3  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U3_M  ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S))
-#define PCNT_CH1_LCTRL_MODE_U3_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U3_S  30
-/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's high
- control signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_HCTRL_MODE_U3  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U3_M  ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S))
-#define PCNT_CH1_HCTRL_MODE_U3_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U3_S  28
-/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- posedge signal for unit3. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH1_POS_MODE_U3  0x00000003
-#define PCNT_CH1_POS_MODE_U3_M  ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S))
-#define PCNT_CH1_POS_MODE_U3_V  0x3
-#define PCNT_CH1_POS_MODE_U3_S  26
-/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- negedge signal for unit3. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH1_NEG_MODE_U3  0x00000003
-#define PCNT_CH1_NEG_MODE_U3_M  ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S))
-#define PCNT_CH1_NEG_MODE_U3_V  0x3
-#define PCNT_CH1_NEG_MODE_U3_S  24
-/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's low control
- signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_LCTRL_MODE_U3  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U3_M  ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S))
-#define PCNT_CH0_LCTRL_MODE_U3_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U3_S  22
-/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's high
- control signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_HCTRL_MODE_U3  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U3_M  ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S))
-#define PCNT_CH0_HCTRL_MODE_U3_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U3_S  20
-/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- posedge signal for unit3. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH0_POS_MODE_U3  0x00000003
-#define PCNT_CH0_POS_MODE_U3_M  ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S))
-#define PCNT_CH0_POS_MODE_U3_V  0x3
-#define PCNT_CH0_POS_MODE_U3_S  18
-/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- negedge signal for unit3. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH0_NEG_MODE_U3  0x00000003
-#define PCNT_CH0_NEG_MODE_U3_M  ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S))
-#define PCNT_CH0_NEG_MODE_U3_V  0x3
-#define PCNT_CH0_NEG_MODE_U3_S  16
-/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for  comparing  unit3's count with thres1 value .*/
-#define PCNT_THR_THRES1_EN_U3  (BIT(15))
-#define PCNT_THR_THRES1_EN_U3_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U3_V  0x1
-#define PCNT_THR_THRES1_EN_U3_S  15
-/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for comparing unit3's count with  thres0 value.*/
-#define PCNT_THR_THRES0_EN_U3  (BIT(14))
-#define PCNT_THR_THRES0_EN_U3_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U3_V  0x1
-#define PCNT_THR_THRES0_EN_U3_S  14
-/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit3's count with thr_l_lim  value.*/
-#define PCNT_THR_L_LIM_EN_U3  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U3_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U3_V  0x1
-#define PCNT_THR_L_LIM_EN_U3_S  13
-/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: This is the enable bit for  comparing unit3's count with thr_h_lim value.*/
-#define PCNT_THR_H_LIM_EN_U3  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U3_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U3_V  0x1
-#define PCNT_THR_H_LIM_EN_U3_S  12
-/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit3's count with 0 value.*/
-#define PCNT_THR_ZERO_EN_U3  (BIT(11))
-#define PCNT_THR_ZERO_EN_U3_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U3_V  0x1
-#define PCNT_THR_ZERO_EN_U3_S  11
-/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: This is the enable bit for filtering input signals for unit3.*/
-#define PCNT_FILTER_EN_U3  (BIT(10))
-#define PCNT_FILTER_EN_U3_M  (BIT(10))
-#define PCNT_FILTER_EN_U3_V  0x1
-#define PCNT_FILTER_EN_U3_S  10
-/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: This register is used to filter pluse whose width is smaller
- than this value for unit3.*/
-#define PCNT_FILTER_THRES_U3  0x000003FF
-#define PCNT_FILTER_THRES_U3_M  ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S))
-#define PCNT_FILTER_THRES_U3_V  0x3FF
-#define PCNT_FILTER_THRES_U3_S  0
-
-#define PCNT_U3_CONF1_REG          (DR_REG_PCNT_BASE + 0x0028)
-/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to configure  thres1 value for unit3.*/
-#define PCNT_CNT_THRES1_U3  0x0000FFFF
-#define PCNT_CNT_THRES1_U3_M  ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S))
-#define PCNT_CNT_THRES1_U3_V  0xFFFF
-#define PCNT_CNT_THRES1_U3_S  16
-/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thres0 value for unit3.*/
-#define PCNT_CNT_THRES0_U3  0x0000FFFF
-#define PCNT_CNT_THRES0_U3_M  ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S))
-#define PCNT_CNT_THRES0_U3_V  0xFFFF
-#define PCNT_CNT_THRES0_U3_S  0
-
-#define PCNT_U3_CONF2_REG          (DR_REG_PCNT_BASE + 0x002c)
-/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to confiugre thr_l_lim value for unit3.*/
-#define PCNT_CNT_L_LIM_U3  0x0000FFFF
-#define PCNT_CNT_L_LIM_U3_M  ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S))
-#define PCNT_CNT_L_LIM_U3_V  0xFFFF
-#define PCNT_CNT_L_LIM_U3_S  16
-/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thr_h_lim value for unit3.*/
-#define PCNT_CNT_H_LIM_U3  0x0000FFFF
-#define PCNT_CNT_H_LIM_U3_M  ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S))
-#define PCNT_CNT_H_LIM_U3_V  0xFFFF
-#define PCNT_CNT_H_LIM_U3_S  0
-
-#define PCNT_U4_CONF0_REG          (DR_REG_PCNT_BASE + 0x0030)
-/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's low control
- signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_LCTRL_MODE_U4  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U4_M  ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S))
-#define PCNT_CH1_LCTRL_MODE_U4_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U4_S  30
-/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's high
- control signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_HCTRL_MODE_U4  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U4_M  ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S))
-#define PCNT_CH1_HCTRL_MODE_U4_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U4_S  28
-/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- posedge signal for unit4. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH1_POS_MODE_U4  0x00000003
-#define PCNT_CH1_POS_MODE_U4_M  ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S))
-#define PCNT_CH1_POS_MODE_U4_V  0x3
-#define PCNT_CH1_POS_MODE_U4_S  26
-/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- negedge signal for unit4. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH1_NEG_MODE_U4  0x00000003
-#define PCNT_CH1_NEG_MODE_U4_M  ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S))
-#define PCNT_CH1_NEG_MODE_U4_V  0x3
-#define PCNT_CH1_NEG_MODE_U4_S  24
-/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's low control
- signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_LCTRL_MODE_U4  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U4_M  ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S))
-#define PCNT_CH0_LCTRL_MODE_U4_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U4_S  22
-/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's high
- control signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_HCTRL_MODE_U4  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U4_M  ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S))
-#define PCNT_CH0_HCTRL_MODE_U4_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U4_S  20
-/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- posedge signal for unit4. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH0_POS_MODE_U4  0x00000003
-#define PCNT_CH0_POS_MODE_U4_M  ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S))
-#define PCNT_CH0_POS_MODE_U4_V  0x3
-#define PCNT_CH0_POS_MODE_U4_S  18
-/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- negedge signal for unit4. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH0_NEG_MODE_U4  0x00000003
-#define PCNT_CH0_NEG_MODE_U4_M  ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S))
-#define PCNT_CH0_NEG_MODE_U4_V  0x3
-#define PCNT_CH0_NEG_MODE_U4_S  16
-/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for  comparing  unit4's count with thres1 value .*/
-#define PCNT_THR_THRES1_EN_U4  (BIT(15))
-#define PCNT_THR_THRES1_EN_U4_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U4_V  0x1
-#define PCNT_THR_THRES1_EN_U4_S  15
-/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for comparing unit4's count with  thres0 value.*/
-#define PCNT_THR_THRES0_EN_U4  (BIT(14))
-#define PCNT_THR_THRES0_EN_U4_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U4_V  0x1
-#define PCNT_THR_THRES0_EN_U4_S  14
-/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit4's count with thr_l_lim  value.*/
-#define PCNT_THR_L_LIM_EN_U4  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U4_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U4_V  0x1
-#define PCNT_THR_L_LIM_EN_U4_S  13
-/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: This is the enable bit for  comparing unit4's count with thr_h_lim value.*/
-#define PCNT_THR_H_LIM_EN_U4  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U4_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U4_V  0x1
-#define PCNT_THR_H_LIM_EN_U4_S  12
-/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit4's count with 0 value.*/
-#define PCNT_THR_ZERO_EN_U4  (BIT(11))
-#define PCNT_THR_ZERO_EN_U4_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U4_V  0x1
-#define PCNT_THR_ZERO_EN_U4_S  11
-/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: This is the enable bit for filtering input signals for unit4.*/
-#define PCNT_FILTER_EN_U4  (BIT(10))
-#define PCNT_FILTER_EN_U4_M  (BIT(10))
-#define PCNT_FILTER_EN_U4_V  0x1
-#define PCNT_FILTER_EN_U4_S  10
-/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: This register is used to filter pluse whose width is smaller
- than this value for unit4.*/
-#define PCNT_FILTER_THRES_U4  0x000003FF
-#define PCNT_FILTER_THRES_U4_M  ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S))
-#define PCNT_FILTER_THRES_U4_V  0x3FF
-#define PCNT_FILTER_THRES_U4_S  0
-
-#define PCNT_U4_CONF1_REG          (DR_REG_PCNT_BASE + 0x0034)
-/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to configure  thres1 value for unit4.*/
-#define PCNT_CNT_THRES1_U4  0x0000FFFF
-#define PCNT_CNT_THRES1_U4_M  ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S))
-#define PCNT_CNT_THRES1_U4_V  0xFFFF
-#define PCNT_CNT_THRES1_U4_S  16
-/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thres0 value for unit4.*/
-#define PCNT_CNT_THRES0_U4  0x0000FFFF
-#define PCNT_CNT_THRES0_U4_M  ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S))
-#define PCNT_CNT_THRES0_U4_V  0xFFFF
-#define PCNT_CNT_THRES0_U4_S  0
-
-#define PCNT_U4_CONF2_REG          (DR_REG_PCNT_BASE + 0x0038)
-/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to confiugre thr_l_lim value for unit4.*/
-#define PCNT_CNT_L_LIM_U4  0x0000FFFF
-#define PCNT_CNT_L_LIM_U4_M  ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S))
-#define PCNT_CNT_L_LIM_U4_V  0xFFFF
-#define PCNT_CNT_L_LIM_U4_S  16
-/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thr_h_lim value for unit4.*/
-#define PCNT_CNT_H_LIM_U4  0x0000FFFF
-#define PCNT_CNT_H_LIM_U4_M  ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S))
-#define PCNT_CNT_H_LIM_U4_V  0xFFFF
-#define PCNT_CNT_H_LIM_U4_S  0
-
-#define PCNT_U5_CONF0_REG          (DR_REG_PCNT_BASE + 0x003c)
-/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's low control
- signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_LCTRL_MODE_U5  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U5_M  ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S))
-#define PCNT_CH1_LCTRL_MODE_U5_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U5_S  30
-/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's high
- control signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_HCTRL_MODE_U5  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U5_M  ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S))
-#define PCNT_CH1_HCTRL_MODE_U5_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U5_S  28
-/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- posedge signal for unit5. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH1_POS_MODE_U5  0x00000003
-#define PCNT_CH1_POS_MODE_U5_M  ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S))
-#define PCNT_CH1_POS_MODE_U5_V  0x3
-#define PCNT_CH1_POS_MODE_U5_S  26
-/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- negedge signal for unit5. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH1_NEG_MODE_U5  0x00000003
-#define PCNT_CH1_NEG_MODE_U5_M  ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S))
-#define PCNT_CH1_NEG_MODE_U5_V  0x3
-#define PCNT_CH1_NEG_MODE_U5_S  24
-/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's low control
- signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_LCTRL_MODE_U5  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U5_M  ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S))
-#define PCNT_CH0_LCTRL_MODE_U5_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U5_S  22
-/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's high
- control signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_HCTRL_MODE_U5  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U5_M  ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S))
-#define PCNT_CH0_HCTRL_MODE_U5_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U5_S  20
-/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- posedge signal for unit5. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH0_POS_MODE_U5  0x00000003
-#define PCNT_CH0_POS_MODE_U5_M  ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S))
-#define PCNT_CH0_POS_MODE_U5_V  0x3
-#define PCNT_CH0_POS_MODE_U5_S  18
-/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- negedge signal for unit5. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH0_NEG_MODE_U5  0x00000003
-#define PCNT_CH0_NEG_MODE_U5_M  ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S))
-#define PCNT_CH0_NEG_MODE_U5_V  0x3
-#define PCNT_CH0_NEG_MODE_U5_S  16
-/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for  comparing  unit5's count with thres1 value .*/
-#define PCNT_THR_THRES1_EN_U5  (BIT(15))
-#define PCNT_THR_THRES1_EN_U5_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U5_V  0x1
-#define PCNT_THR_THRES1_EN_U5_S  15
-/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for comparing unit5's count with  thres0 value.*/
-#define PCNT_THR_THRES0_EN_U5  (BIT(14))
-#define PCNT_THR_THRES0_EN_U5_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U5_V  0x1
-#define PCNT_THR_THRES0_EN_U5_S  14
-/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit5's count with thr_l_lim  value.*/
-#define PCNT_THR_L_LIM_EN_U5  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U5_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U5_V  0x1
-#define PCNT_THR_L_LIM_EN_U5_S  13
-/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: This is the enable bit for  comparing unit5's count with thr_h_lim value.*/
-#define PCNT_THR_H_LIM_EN_U5  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U5_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U5_V  0x1
-#define PCNT_THR_H_LIM_EN_U5_S  12
-/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit5's count with 0 value.*/
-#define PCNT_THR_ZERO_EN_U5  (BIT(11))
-#define PCNT_THR_ZERO_EN_U5_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U5_V  0x1
-#define PCNT_THR_ZERO_EN_U5_S  11
-/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: This is the enable bit for filtering input signals for unit5.*/
-#define PCNT_FILTER_EN_U5  (BIT(10))
-#define PCNT_FILTER_EN_U5_M  (BIT(10))
-#define PCNT_FILTER_EN_U5_V  0x1
-#define PCNT_FILTER_EN_U5_S  10
-/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: This register is used to filter pluse whose width is smaller
- than this value for unit5.*/
-#define PCNT_FILTER_THRES_U5  0x000003FF
-#define PCNT_FILTER_THRES_U5_M  ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S))
-#define PCNT_FILTER_THRES_U5_V  0x3FF
-#define PCNT_FILTER_THRES_U5_S  0
-
-#define PCNT_U5_CONF1_REG          (DR_REG_PCNT_BASE + 0x0040)
-/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to configure  thres1 value for unit5.*/
-#define PCNT_CNT_THRES1_U5  0x0000FFFF
-#define PCNT_CNT_THRES1_U5_M  ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S))
-#define PCNT_CNT_THRES1_U5_V  0xFFFF
-#define PCNT_CNT_THRES1_U5_S  16
-/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thres0 value for unit5.*/
-#define PCNT_CNT_THRES0_U5  0x0000FFFF
-#define PCNT_CNT_THRES0_U5_M  ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S))
-#define PCNT_CNT_THRES0_U5_V  0xFFFF
-#define PCNT_CNT_THRES0_U5_S  0
-
-#define PCNT_U5_CONF2_REG          (DR_REG_PCNT_BASE + 0x0044)
-/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to confiugre thr_l_lim value for unit5.*/
-#define PCNT_CNT_L_LIM_U5  0x0000FFFF
-#define PCNT_CNT_L_LIM_U5_M  ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S))
-#define PCNT_CNT_L_LIM_U5_V  0xFFFF
-#define PCNT_CNT_L_LIM_U5_S  16
-/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thr_h_lim value for unit5.*/
-#define PCNT_CNT_H_LIM_U5  0x0000FFFF
-#define PCNT_CNT_H_LIM_U5_M  ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S))
-#define PCNT_CNT_H_LIM_U5_V  0xFFFF
-#define PCNT_CNT_H_LIM_U5_S  0
-
-#define PCNT_U6_CONF0_REG          (DR_REG_PCNT_BASE + 0x0048)
-/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's low control
- signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_LCTRL_MODE_U6  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U6_M  ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S))
-#define PCNT_CH1_LCTRL_MODE_U6_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U6_S  30
-/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's high
- control signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_HCTRL_MODE_U6  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U6_M  ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S))
-#define PCNT_CH1_HCTRL_MODE_U6_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U6_S  28
-/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- posedge signal for unit6. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH1_POS_MODE_U6  0x00000003
-#define PCNT_CH1_POS_MODE_U6_M  ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S))
-#define PCNT_CH1_POS_MODE_U6_V  0x3
-#define PCNT_CH1_POS_MODE_U6_S  26
-/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- negedge signal for unit6. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH1_NEG_MODE_U6  0x00000003
-#define PCNT_CH1_NEG_MODE_U6_M  ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S))
-#define PCNT_CH1_NEG_MODE_U6_V  0x3
-#define PCNT_CH1_NEG_MODE_U6_S  24
-/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's low control
- signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_LCTRL_MODE_U6  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U6_M  ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S))
-#define PCNT_CH0_LCTRL_MODE_U6_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U6_S  22
-/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's high
- control signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_HCTRL_MODE_U6  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U6_M  ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S))
-#define PCNT_CH0_HCTRL_MODE_U6_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U6_S  20
-/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- posedge signal for unit6. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH0_POS_MODE_U6  0x00000003
-#define PCNT_CH0_POS_MODE_U6_M  ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S))
-#define PCNT_CH0_POS_MODE_U6_V  0x3
-#define PCNT_CH0_POS_MODE_U6_S  18
-/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- negedge signal for unit6. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH0_NEG_MODE_U6  0x00000003
-#define PCNT_CH0_NEG_MODE_U6_M  ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S))
-#define PCNT_CH0_NEG_MODE_U6_V  0x3
-#define PCNT_CH0_NEG_MODE_U6_S  16
-/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for  comparing  unit6's count with thres1 value .*/
-#define PCNT_THR_THRES1_EN_U6  (BIT(15))
-#define PCNT_THR_THRES1_EN_U6_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U6_V  0x1
-#define PCNT_THR_THRES1_EN_U6_S  15
-/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for comparing unit6's count with  thres0 value.*/
-#define PCNT_THR_THRES0_EN_U6  (BIT(14))
-#define PCNT_THR_THRES0_EN_U6_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U6_V  0x1
-#define PCNT_THR_THRES0_EN_U6_S  14
-/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit6's count with thr_l_lim  value.*/
-#define PCNT_THR_L_LIM_EN_U6  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U6_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U6_V  0x1
-#define PCNT_THR_L_LIM_EN_U6_S  13
-/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: This is the enable bit for  comparing unit6's count with thr_h_lim value.*/
-#define PCNT_THR_H_LIM_EN_U6  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U6_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U6_V  0x1
-#define PCNT_THR_H_LIM_EN_U6_S  12
-/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit6's count with 0 value.*/
-#define PCNT_THR_ZERO_EN_U6  (BIT(11))
-#define PCNT_THR_ZERO_EN_U6_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U6_V  0x1
-#define PCNT_THR_ZERO_EN_U6_S  11
-/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: This is the enable bit for filtering input signals for unit6.*/
-#define PCNT_FILTER_EN_U6  (BIT(10))
-#define PCNT_FILTER_EN_U6_M  (BIT(10))
-#define PCNT_FILTER_EN_U6_V  0x1
-#define PCNT_FILTER_EN_U6_S  10
-/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: This register is used to filter pluse whose width is smaller
- than this value for unit6.*/
-#define PCNT_FILTER_THRES_U6  0x000003FF
-#define PCNT_FILTER_THRES_U6_M  ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S))
-#define PCNT_FILTER_THRES_U6_V  0x3FF
-#define PCNT_FILTER_THRES_U6_S  0
-
-#define PCNT_U6_CONF1_REG          (DR_REG_PCNT_BASE + 0x004c)
-/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to configure  thres1 value for unit6.*/
-#define PCNT_CNT_THRES1_U6  0x0000FFFF
-#define PCNT_CNT_THRES1_U6_M  ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S))
-#define PCNT_CNT_THRES1_U6_V  0xFFFF
-#define PCNT_CNT_THRES1_U6_S  16
-/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thres0 value for unit6.*/
-#define PCNT_CNT_THRES0_U6  0x0000FFFF
-#define PCNT_CNT_THRES0_U6_M  ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S))
-#define PCNT_CNT_THRES0_U6_V  0xFFFF
-#define PCNT_CNT_THRES0_U6_S  0
-
-#define PCNT_U6_CONF2_REG          (DR_REG_PCNT_BASE + 0x0050)
-/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to confiugre thr_l_lim value for unit6.*/
-#define PCNT_CNT_L_LIM_U6  0x0000FFFF
-#define PCNT_CNT_L_LIM_U6_M  ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S))
-#define PCNT_CNT_L_LIM_U6_V  0xFFFF
-#define PCNT_CNT_L_LIM_U6_S  16
-/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thr_h_lim value for unit6.*/
-#define PCNT_CNT_H_LIM_U6  0x0000FFFF
-#define PCNT_CNT_H_LIM_U6_M  ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S))
-#define PCNT_CNT_H_LIM_U6_V  0xFFFF
-#define PCNT_CNT_H_LIM_U6_S  0
-
-#define PCNT_U7_CONF0_REG          (DR_REG_PCNT_BASE + 0x0054)
-/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's low control
- signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_LCTRL_MODE_U7  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U7_M  ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S))
-#define PCNT_CH1_LCTRL_MODE_U7_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U7_S  30
-/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's high
- control signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH1_HCTRL_MODE_U7  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U7_M  ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S))
-#define PCNT_CH1_HCTRL_MODE_U7_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U7_S  28
-/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- posedge signal for unit7. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH1_POS_MODE_U7  0x00000003
-#define PCNT_CH1_POS_MODE_U7_M  ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S))
-#define PCNT_CH1_POS_MODE_U7_V  0x3
-#define PCNT_CH1_POS_MODE_U7_S  26
-/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel1's input
- negedge signal for unit7. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH1_NEG_MODE_U7  0x00000003
-#define PCNT_CH1_NEG_MODE_U7_M  ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S))
-#define PCNT_CH1_NEG_MODE_U7_V  0x3
-#define PCNT_CH1_NEG_MODE_U7_S  24
-/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's low control
- signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_LCTRL_MODE_U7  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U7_M  ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S))
-#define PCNT_CH0_LCTRL_MODE_U7_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U7_S  22
-/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's high
- control signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
-#define PCNT_CH0_HCTRL_MODE_U7  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U7_M  ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S))
-#define PCNT_CH0_HCTRL_MODE_U7_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U7_S  20
-/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- posedge signal for unit7. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-#define PCNT_CH0_POS_MODE_U7  0x00000003
-#define PCNT_CH0_POS_MODE_U7_M  ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S))
-#define PCNT_CH0_POS_MODE_U7_V  0x3
-#define PCNT_CH0_POS_MODE_U7_S  18
-/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: This register is used to control the mode of channel0's input
- negedge signal for unit7. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-#define PCNT_CH0_NEG_MODE_U7  0x00000003
-#define PCNT_CH0_NEG_MODE_U7_M  ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S))
-#define PCNT_CH0_NEG_MODE_U7_V  0x3
-#define PCNT_CH0_NEG_MODE_U7_S  16
-/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for  comparing  unit7's count with thres1 value .*/
-#define PCNT_THR_THRES1_EN_U7  (BIT(15))
-#define PCNT_THR_THRES1_EN_U7_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U7_V  0x1
-#define PCNT_THR_THRES1_EN_U7_S  15
-/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for comparing unit7's count with  thres0 value.*/
-#define PCNT_THR_THRES0_EN_U7  (BIT(14))
-#define PCNT_THR_THRES0_EN_U7_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U7_V  0x1
-#define PCNT_THR_THRES0_EN_U7_S  14
-/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit7's count with thr_l_lim  value.*/
-#define PCNT_THR_L_LIM_EN_U7  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U7_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U7_V  0x1
-#define PCNT_THR_L_LIM_EN_U7_S  13
-/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: This is the enable bit for  comparing unit7's count with thr_h_lim value.*/
-#define PCNT_THR_H_LIM_EN_U7  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U7_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U7_V  0x1
-#define PCNT_THR_H_LIM_EN_U7_S  12
-/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: This is the enable bit for comparing unit7's count with 0 value.*/
-#define PCNT_THR_ZERO_EN_U7  (BIT(11))
-#define PCNT_THR_ZERO_EN_U7_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U7_V  0x1
-#define PCNT_THR_ZERO_EN_U7_S  11
-/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: This is the enable bit for filtering input signals for unit7.*/
-#define PCNT_FILTER_EN_U7  (BIT(10))
-#define PCNT_FILTER_EN_U7_M  (BIT(10))
-#define PCNT_FILTER_EN_U7_V  0x1
-#define PCNT_FILTER_EN_U7_S  10
-/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: This register is used to filter pluse whose width is smaller
- than this value for unit7.*/
-#define PCNT_FILTER_THRES_U7  0x000003FF
-#define PCNT_FILTER_THRES_U7_M  ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S))
-#define PCNT_FILTER_THRES_U7_V  0x3FF
-#define PCNT_FILTER_THRES_U7_S  0
-
-#define PCNT_U7_CONF1_REG          (DR_REG_PCNT_BASE + 0x0058)
-/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to configure  thres1 value for unit7.*/
-#define PCNT_CNT_THRES1_U7  0x0000FFFF
-#define PCNT_CNT_THRES1_U7_M  ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S))
-#define PCNT_CNT_THRES1_U7_V  0xFFFF
-#define PCNT_CNT_THRES1_U7_S  16
-/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thres0 value for unit7.*/
-#define PCNT_CNT_THRES0_U7  0x0000FFFF
-#define PCNT_CNT_THRES0_U7_M  ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S))
-#define PCNT_CNT_THRES0_U7_V  0xFFFF
-#define PCNT_CNT_THRES0_U7_S  0
-
-#define PCNT_U7_CONF2_REG          (DR_REG_PCNT_BASE + 0x005c)
-/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: This register is used to confiugre thr_l_lim value for unit7.*/
-#define PCNT_CNT_L_LIM_U7  0x0000FFFF
-#define PCNT_CNT_L_LIM_U7_M  ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S))
-#define PCNT_CNT_L_LIM_U7_V  0xFFFF
-#define PCNT_CNT_L_LIM_U7_S  16
-/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: This register is used to configure thr_h_lim value for unit7.*/
-#define PCNT_CNT_H_LIM_U7  0x0000FFFF
-#define PCNT_CNT_H_LIM_U7_M  ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S))
-#define PCNT_CNT_H_LIM_U7_V  0xFFFF
-#define PCNT_CNT_H_LIM_U7_S  0
-
-#define PCNT_U0_CNT_REG          (DR_REG_PCNT_BASE + 0x0060)
-/* PCNT_PLUS_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This register stores the current pulse count value for unit0.*/
-#define PCNT_PLUS_CNT_U0  0x0000FFFF
-#define PCNT_PLUS_CNT_U0_M  ((PCNT_PLUS_CNT_U0_V)<<(PCNT_PLUS_CNT_U0_S))
-#define PCNT_PLUS_CNT_U0_V  0xFFFF
-#define PCNT_PLUS_CNT_U0_S  0
-
-#define PCNT_U1_CNT_REG          (DR_REG_PCNT_BASE + 0x0064)
-/* PCNT_PLUS_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This register stores the current pulse count value for unit1.*/
-#define PCNT_PLUS_CNT_U1  0x0000FFFF
-#define PCNT_PLUS_CNT_U1_M  ((PCNT_PLUS_CNT_U1_V)<<(PCNT_PLUS_CNT_U1_S))
-#define PCNT_PLUS_CNT_U1_V  0xFFFF
-#define PCNT_PLUS_CNT_U1_S  0
-
-#define PCNT_U2_CNT_REG          (DR_REG_PCNT_BASE + 0x0068)
-/* PCNT_PLUS_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This register stores the current pulse count value for unit2.*/
-#define PCNT_PLUS_CNT_U2  0x0000FFFF
-#define PCNT_PLUS_CNT_U2_M  ((PCNT_PLUS_CNT_U2_V)<<(PCNT_PLUS_CNT_U2_S))
-#define PCNT_PLUS_CNT_U2_V  0xFFFF
-#define PCNT_PLUS_CNT_U2_S  0
-
-#define PCNT_U3_CNT_REG          (DR_REG_PCNT_BASE + 0x006c)
-/* PCNT_PLUS_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This register stores the current pulse count value for unit3.*/
-#define PCNT_PLUS_CNT_U3  0x0000FFFF
-#define PCNT_PLUS_CNT_U3_M  ((PCNT_PLUS_CNT_U3_V)<<(PCNT_PLUS_CNT_U3_S))
-#define PCNT_PLUS_CNT_U3_V  0xFFFF
-#define PCNT_PLUS_CNT_U3_S  0
-
-#define PCNT_U4_CNT_REG          (DR_REG_PCNT_BASE + 0x0070)
-/* PCNT_PLUS_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This register stores the current pulse count value for unit4.*/
-#define PCNT_PLUS_CNT_U4  0x0000FFFF
-#define PCNT_PLUS_CNT_U4_M  ((PCNT_PLUS_CNT_U4_V)<<(PCNT_PLUS_CNT_U4_S))
-#define PCNT_PLUS_CNT_U4_V  0xFFFF
-#define PCNT_PLUS_CNT_U4_S  0
-
-#define PCNT_U5_CNT_REG          (DR_REG_PCNT_BASE + 0x0074)
-/* PCNT_PLUS_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This register stores the current pulse count value for unit5.*/
-#define PCNT_PLUS_CNT_U5  0x0000FFFF
-#define PCNT_PLUS_CNT_U5_M  ((PCNT_PLUS_CNT_U5_V)<<(PCNT_PLUS_CNT_U5_S))
-#define PCNT_PLUS_CNT_U5_V  0xFFFF
-#define PCNT_PLUS_CNT_U5_S  0
-
-#define PCNT_U6_CNT_REG          (DR_REG_PCNT_BASE + 0x0078)
-/* PCNT_PLUS_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This register stores the current pulse count value for unit6.*/
-#define PCNT_PLUS_CNT_U6  0x0000FFFF
-#define PCNT_PLUS_CNT_U6_M  ((PCNT_PLUS_CNT_U6_V)<<(PCNT_PLUS_CNT_U6_S))
-#define PCNT_PLUS_CNT_U6_V  0xFFFF
-#define PCNT_PLUS_CNT_U6_S  0
-
-#define PCNT_U7_CNT_REG          (DR_REG_PCNT_BASE + 0x007c)
-/* PCNT_PLUS_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: This register stores the current pulse count value for unit7.*/
-#define PCNT_PLUS_CNT_U7  0x0000FFFF
-#define PCNT_PLUS_CNT_U7_M  ((PCNT_PLUS_CNT_U7_V)<<(PCNT_PLUS_CNT_U7_S))
-#define PCNT_PLUS_CNT_U7_V  0xFFFF
-#define PCNT_PLUS_CNT_U7_S  0
-
-#define PCNT_INT_RAW_REG          (DR_REG_PCNT_BASE + 0x0080)
-/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the interrupt raw bit for channel7 event.*/
-#define PCNT_CNT_THR_EVENT_U7_INT_RAW  (BIT(7))
-#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M  (BIT(7))
-#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S  7
-/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the interrupt raw bit for channel6 event.*/
-#define PCNT_CNT_THR_EVENT_U6_INT_RAW  (BIT(6))
-#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M  (BIT(6))
-#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S  6
-/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the interrupt raw bit for channel5 event.*/
-#define PCNT_CNT_THR_EVENT_U5_INT_RAW  (BIT(5))
-#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M  (BIT(5))
-#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S  5
-/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the interrupt raw bit for channel4 event.*/
-#define PCNT_CNT_THR_EVENT_U4_INT_RAW  (BIT(4))
-#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M  (BIT(4))
-#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S  4
-/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the interrupt raw bit for channel3 event.*/
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the interrupt raw bit for channel2 event.*/
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the interrupt raw bit for channel1 event.*/
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the interrupt raw bit for channel0 event.*/
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S  0
-
-#define PCNT_INT_ST_REG          (DR_REG_PCNT_BASE + 0x0084)
-/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the  interrupt status bit for channel7 event.*/
-#define PCNT_CNT_THR_EVENT_U7_INT_ST  (BIT(7))
-#define PCNT_CNT_THR_EVENT_U7_INT_ST_M  (BIT(7))
-#define PCNT_CNT_THR_EVENT_U7_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U7_INT_ST_S  7
-/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the  interrupt status bit for channel6 event.*/
-#define PCNT_CNT_THR_EVENT_U6_INT_ST  (BIT(6))
-#define PCNT_CNT_THR_EVENT_U6_INT_ST_M  (BIT(6))
-#define PCNT_CNT_THR_EVENT_U6_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U6_INT_ST_S  6
-/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the  interrupt status bit for channel5 event.*/
-#define PCNT_CNT_THR_EVENT_U5_INT_ST  (BIT(5))
-#define PCNT_CNT_THR_EVENT_U5_INT_ST_M  (BIT(5))
-#define PCNT_CNT_THR_EVENT_U5_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U5_INT_ST_S  5
-/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the  interrupt status bit for channel4 event.*/
-#define PCNT_CNT_THR_EVENT_U4_INT_ST  (BIT(4))
-#define PCNT_CNT_THR_EVENT_U4_INT_ST_M  (BIT(4))
-#define PCNT_CNT_THR_EVENT_U4_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U4_INT_ST_S  4
-/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the  interrupt status bit for channel3 event.*/
-#define PCNT_CNT_THR_EVENT_U3_INT_ST  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the  interrupt status bit for channel2 event.*/
-#define PCNT_CNT_THR_EVENT_U2_INT_ST  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the  interrupt status bit for channel1 event.*/
-#define PCNT_CNT_THR_EVENT_U1_INT_ST  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the  interrupt status bit for channel0 event.*/
-#define PCNT_CNT_THR_EVENT_U0_INT_ST  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_S  0
-
-#define PCNT_INT_ENA_REG          (DR_REG_PCNT_BASE + 0x0088)
-/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the  interrupt enable bit for channel7 event.*/
-#define PCNT_CNT_THR_EVENT_U7_INT_ENA  (BIT(7))
-#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M  (BIT(7))
-#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S  7
-/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the  interrupt enable bit for channel6 event.*/
-#define PCNT_CNT_THR_EVENT_U6_INT_ENA  (BIT(6))
-#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M  (BIT(6))
-#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S  6
-/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the  interrupt enable bit for channel5 event.*/
-#define PCNT_CNT_THR_EVENT_U5_INT_ENA  (BIT(5))
-#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M  (BIT(5))
-#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S  5
-/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the  interrupt enable bit for channel4 event.*/
-#define PCNT_CNT_THR_EVENT_U4_INT_ENA  (BIT(4))
-#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M  (BIT(4))
-#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S  4
-/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the  interrupt enable bit for channel3 event.*/
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the  interrupt enable bit for channel2 event.*/
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the  interrupt enable bit for channel1 event.*/
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the  interrupt enable bit for channel0 event.*/
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S  0
-
-#define PCNT_INT_CLR_REG          (DR_REG_PCNT_BASE + 0x008c)
-/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to clear channel7 event interrupt.*/
-#define PCNT_CNT_THR_EVENT_U7_INT_CLR  (BIT(7))
-#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M  (BIT(7))
-#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S  7
-/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to clear channel6 event interrupt.*/
-#define PCNT_CNT_THR_EVENT_U6_INT_CLR  (BIT(6))
-#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M  (BIT(6))
-#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S  6
-/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to clear channel5 event interrupt.*/
-#define PCNT_CNT_THR_EVENT_U5_INT_CLR  (BIT(5))
-#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M  (BIT(5))
-#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S  5
-/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to clear channel4 event interrupt.*/
-#define PCNT_CNT_THR_EVENT_U4_INT_CLR  (BIT(4))
-#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M  (BIT(4))
-#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S  4
-/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear channel3 event interrupt.*/
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear channel2 event interrupt.*/
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear channel1 event interrupt.*/
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear channel0 event interrupt.*/
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S  0
-
-#define PCNT_U0_STATUS_REG          (DR_REG_PCNT_BASE + 0x0090)
-/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define PCNT_CORE_STATUS_U0  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U0_M  ((PCNT_CORE_STATUS_U0_V)<<(PCNT_CORE_STATUS_U0_S))
-#define PCNT_CORE_STATUS_U0_V  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U0_S  0
-/*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/
-#define PCNT_STATUS_CNT_MODE    0x3
-#define PCNT_STATUS_CNT_MODE_M  ((PCNT_STATUS_CNT_MODE_V)<<(PCNT_STATUS_CNT_MODE_S))
-#define PCNT_STATUS_CNT_MODE_V  0x3
-#define PCNT_STATUS_CNT_MODE_S  0
-/* counter value equals to thresh1*/
-#define PCNT_STATUS_THRES1    BIT(2)
-#define PCNT_STATUS_THRES1_M  BIT(2)
-#define PCNT_STATUS_THRES1_V  0x1
-#define PCNT_STATUS_THRES1_S  2
-/* counter value equals to thresh0*/
-#define PCNT_STATUS_THRES0    BIT(3)
-#define PCNT_STATUS_THRES0_M  BIT(3)
-#define PCNT_STATUS_THRES0_V  0x1
-#define PCNT_STATUS_THRES0_S  3
-/* counter value reaches h_lim*/
-#define PCNT_STATUS_L_LIM    BIT(4)
-#define PCNT_STATUS_L_LIM_M  BIT(4)
-#define PCNT_STATUS_L_LIM_V  0x1
-#define PCNT_STATUS_L_LIM_S  4
-/* counter value reaches l_lim*/
-#define PCNT_STATUS_H_LIM    BIT(5)
-#define PCNT_STATUS_H_LIM_M  BIT(5)
-#define PCNT_STATUS_H_LIM_V  0x1
-#define PCNT_STATUS_H_LIM_S  5
-/* counter value equals to zero*/
-#define PCNT_STATUS_ZERO    BIT(6)
-#define PCNT_STATUS_ZERO_M  BIT(6)
-#define PCNT_STATUS_ZERO_V  0x1
-#define PCNT_STATUS_ZERO_S  6
-
-#define PCNT_U1_STATUS_REG          (DR_REG_PCNT_BASE + 0x0094)
-/* PCNT_CORE_STATUS_U1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define PCNT_CORE_STATUS_U1  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U1_M  ((PCNT_CORE_STATUS_U1_V)<<(PCNT_CORE_STATUS_U1_S))
-#define PCNT_CORE_STATUS_U1_V  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U1_S  0
-
-#define PCNT_U2_STATUS_REG          (DR_REG_PCNT_BASE + 0x0098)
-/* PCNT_CORE_STATUS_U2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define PCNT_CORE_STATUS_U2  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U2_M  ((PCNT_CORE_STATUS_U2_V)<<(PCNT_CORE_STATUS_U2_S))
-#define PCNT_CORE_STATUS_U2_V  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U2_S  0
-
-#define PCNT_U3_STATUS_REG          (DR_REG_PCNT_BASE + 0x009c)
-/* PCNT_CORE_STATUS_U3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define PCNT_CORE_STATUS_U3  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U3_M  ((PCNT_CORE_STATUS_U3_V)<<(PCNT_CORE_STATUS_U3_S))
-#define PCNT_CORE_STATUS_U3_V  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U3_S  0
-
-#define PCNT_U4_STATUS_REG          (DR_REG_PCNT_BASE + 0x00a0)
-/* PCNT_CORE_STATUS_U4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define PCNT_CORE_STATUS_U4  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U4_M  ((PCNT_CORE_STATUS_U4_V)<<(PCNT_CORE_STATUS_U4_S))
-#define PCNT_CORE_STATUS_U4_V  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U4_S  0
-
-#define PCNT_U5_STATUS_REG          (DR_REG_PCNT_BASE + 0x00a4)
-/* PCNT_CORE_STATUS_U5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define PCNT_CORE_STATUS_U5  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U5_M  ((PCNT_CORE_STATUS_U5_V)<<(PCNT_CORE_STATUS_U5_S))
-#define PCNT_CORE_STATUS_U5_V  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U5_S  0
-
-#define PCNT_U6_STATUS_REG          (DR_REG_PCNT_BASE + 0x00a8)
-/* PCNT_CORE_STATUS_U6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define PCNT_CORE_STATUS_U6  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U6_M  ((PCNT_CORE_STATUS_U6_V)<<(PCNT_CORE_STATUS_U6_S))
-#define PCNT_CORE_STATUS_U6_V  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U6_S  0
-
-#define PCNT_U7_STATUS_REG          (DR_REG_PCNT_BASE + 0x00ac)
-/* PCNT_CORE_STATUS_U7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define PCNT_CORE_STATUS_U7  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U7_M  ((PCNT_CORE_STATUS_U7_V)<<(PCNT_CORE_STATUS_U7_S))
-#define PCNT_CORE_STATUS_U7_V  0xFFFFFFFF
-#define PCNT_CORE_STATUS_U7_S  0
-
-#define PCNT_CTRL_REG          (DR_REG_PCNT_BASE + 0x00b0)
-/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CLK_EN  (BIT(16))
-#define PCNT_CLK_EN_M  (BIT(16))
-#define PCNT_CLK_EN_V  0x1
-#define PCNT_CLK_EN_S  16
-/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to pause unit7's counter.*/
-#define PCNT_CNT_PAUSE_U7  (BIT(15))
-#define PCNT_CNT_PAUSE_U7_M  (BIT(15))
-#define PCNT_CNT_PAUSE_U7_V  0x1
-#define PCNT_CNT_PAUSE_U7_S  15
-/* PCNT_PLUS_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: Set this bit to clear unit7's counter.*/
-#define PCNT_PLUS_CNT_RST_U7  (BIT(14))
-#define PCNT_PLUS_CNT_RST_U7_M  (BIT(14))
-#define PCNT_PLUS_CNT_RST_U7_V  0x1
-#define PCNT_PLUS_CNT_RST_U7_S  14
-/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to pause unit6's counter.*/
-#define PCNT_CNT_PAUSE_U6  (BIT(13))
-#define PCNT_CNT_PAUSE_U6_M  (BIT(13))
-#define PCNT_CNT_PAUSE_U6_V  0x1
-#define PCNT_CNT_PAUSE_U6_S  13
-/* PCNT_PLUS_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: Set this bit to clear unit6's counter.*/
-#define PCNT_PLUS_CNT_RST_U6  (BIT(12))
-#define PCNT_PLUS_CNT_RST_U6_M  (BIT(12))
-#define PCNT_PLUS_CNT_RST_U6_V  0x1
-#define PCNT_PLUS_CNT_RST_U6_S  12
-/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to pause unit5's counter.*/
-#define PCNT_CNT_PAUSE_U5  (BIT(11))
-#define PCNT_CNT_PAUSE_U5_M  (BIT(11))
-#define PCNT_CNT_PAUSE_U5_V  0x1
-#define PCNT_CNT_PAUSE_U5_S  11
-/* PCNT_PLUS_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: Set this bit to clear unit5's counter.*/
-#define PCNT_PLUS_CNT_RST_U5  (BIT(10))
-#define PCNT_PLUS_CNT_RST_U5_M  (BIT(10))
-#define PCNT_PLUS_CNT_RST_U5_V  0x1
-#define PCNT_PLUS_CNT_RST_U5_S  10
-/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to pause unit4's counter.*/
-#define PCNT_CNT_PAUSE_U4  (BIT(9))
-#define PCNT_CNT_PAUSE_U4_M  (BIT(9))
-#define PCNT_CNT_PAUSE_U4_V  0x1
-#define PCNT_CNT_PAUSE_U4_S  9
-/* PCNT_PLUS_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: Set this bit to clear unit4's counter.*/
-#define PCNT_PLUS_CNT_RST_U4  (BIT(8))
-#define PCNT_PLUS_CNT_RST_U4_M  (BIT(8))
-#define PCNT_PLUS_CNT_RST_U4_V  0x1
-#define PCNT_PLUS_CNT_RST_U4_S  8
-/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to pause unit3's counter.*/
-#define PCNT_CNT_PAUSE_U3  (BIT(7))
-#define PCNT_CNT_PAUSE_U3_M  (BIT(7))
-#define PCNT_CNT_PAUSE_U3_V  0x1
-#define PCNT_CNT_PAUSE_U3_S  7
-/* PCNT_PLUS_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: Set this bit to clear unit3's counter.*/
-#define PCNT_PLUS_CNT_RST_U3  (BIT(6))
-#define PCNT_PLUS_CNT_RST_U3_M  (BIT(6))
-#define PCNT_PLUS_CNT_RST_U3_V  0x1
-#define PCNT_PLUS_CNT_RST_U3_S  6
-/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to pause unit2's counter.*/
-#define PCNT_CNT_PAUSE_U2  (BIT(5))
-#define PCNT_CNT_PAUSE_U2_M  (BIT(5))
-#define PCNT_CNT_PAUSE_U2_V  0x1
-#define PCNT_CNT_PAUSE_U2_S  5
-/* PCNT_PLUS_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: Set this bit to clear unit2's counter.*/
-#define PCNT_PLUS_CNT_RST_U2  (BIT(4))
-#define PCNT_PLUS_CNT_RST_U2_M  (BIT(4))
-#define PCNT_PLUS_CNT_RST_U2_V  0x1
-#define PCNT_PLUS_CNT_RST_U2_S  4
-/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to pause unit1's counter.*/
-#define PCNT_CNT_PAUSE_U1  (BIT(3))
-#define PCNT_CNT_PAUSE_U1_M  (BIT(3))
-#define PCNT_CNT_PAUSE_U1_V  0x1
-#define PCNT_CNT_PAUSE_U1_S  3
-/* PCNT_PLUS_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: Set this bit to clear unit1's counter.*/
-#define PCNT_PLUS_CNT_RST_U1  (BIT(2))
-#define PCNT_PLUS_CNT_RST_U1_M  (BIT(2))
-#define PCNT_PLUS_CNT_RST_U1_V  0x1
-#define PCNT_PLUS_CNT_RST_U1_S  2
-/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to pause unit0's counter.*/
-#define PCNT_CNT_PAUSE_U0  (BIT(1))
-#define PCNT_CNT_PAUSE_U0_M  (BIT(1))
-#define PCNT_CNT_PAUSE_U0_V  0x1
-#define PCNT_CNT_PAUSE_U0_S  1
-/* PCNT_PLUS_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Set this bit to clear unit0's counter.*/
-#define PCNT_PLUS_CNT_RST_U0  (BIT(0))
-#define PCNT_PLUS_CNT_RST_U0_M  (BIT(0))
-#define PCNT_PLUS_CNT_RST_U0_V  0x1
-#define PCNT_PLUS_CNT_RST_U0_S  0
-
-#define PCNT_DATE_REG          (DR_REG_PCNT_BASE + 0x00fc)
-/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */
-/*description: */
-#define PCNT_DATE  0xFFFFFFFF
-#define PCNT_DATE_M  ((PCNT_DATE_V)<<(PCNT_DATE_S))
-#define PCNT_DATE_V  0xFFFFFFFF
-#define PCNT_DATE_S  0
-
-
-
-
-#endif /*_SOC_PCNT_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/pcnt_struct.h b/tools/sdk/include/soc/soc/pcnt_struct.h
deleted file mode 100644
index a551835bb8f..00000000000
--- a/tools/sdk/include/soc/soc/pcnt_struct.h
+++ /dev/null
@@ -1,184 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_PCNT_STRUCT_H_
-#define _SOC_PCNT_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    struct{
-        union {
-            struct {
-                uint32_t filter_thres:  10;         /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
-                uint32_t filter_en:      1;         /*This is the enable bit for filtering input signals for unit0.*/
-                uint32_t thr_zero_en:    1;         /*This is the enable bit for comparing unit0's count with 0 value.*/
-                uint32_t thr_h_lim_en:   1;         /*This is the enable bit for  comparing unit0's count with thr_h_lim value.*/
-                uint32_t thr_l_lim_en:   1;         /*This is the enable bit for comparing unit0's count with thr_l_lim  value.*/
-                uint32_t thr_thres0_en:  1;         /*This is the enable bit for comparing unit0's count with  thres0 value.*/
-                uint32_t thr_thres1_en:  1;         /*This is the enable bit for  comparing  unit0's count with thres1 value .*/
-                uint32_t ch0_neg_mode:   2;         /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-                uint32_t ch0_pos_mode:   2;         /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-                uint32_t ch0_hctrl_mode: 2;         /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low   2'd1：decrease when control signal is high   others:forbidden*/
-                uint32_t ch0_lctrl_mode: 2;         /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low   2'd1：decrease when control signal is high   others:forbidden*/
-                uint32_t ch1_neg_mode:   2;         /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
-                uint32_t ch1_pos_mode:   2;         /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
-                uint32_t ch1_hctrl_mode: 2;         /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low   2'd1：decrease when control signal is high   others:forbidden*/
-                uint32_t ch1_lctrl_mode: 2;         /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low   2'd1：decrease when control signal is high   others:forbidden*/
-            };
-            uint32_t val;
-        } conf0;
-        union {
-            struct {
-                uint32_t cnt_thres0:16;             /*This register is used to configure thres0 value for unit0.*/
-                uint32_t cnt_thres1:16;             /*This register is used to configure thres1 value for unit0.*/
-            };
-            uint32_t val;
-        } conf1;
-        union {
-            struct {
-                uint32_t cnt_h_lim:16;              /*This register is used to configure thr_h_lim value for unit0.*/
-                uint32_t cnt_l_lim:16;              /*This register is used to configure thr_l_lim value for unit0.*/
-            };
-            uint32_t val;
-        } conf2;
-    } conf_unit[8];
-    union {
-        struct {
-            uint32_t cnt_val   : 16;                /*This register stores the current pulse count value for unit0.*/
-            uint32_t reserved16: 16;
-        };
-        uint32_t val;
-    } cnt_unit[8];
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0: 1;           /*This is the interrupt raw bit for channel0 event.*/
-            uint32_t cnt_thr_event_u1: 1;           /*This is the interrupt raw bit for channel1 event.*/
-            uint32_t cnt_thr_event_u2: 1;           /*This is the interrupt raw bit for channel2 event.*/
-            uint32_t cnt_thr_event_u3: 1;           /*This is the interrupt raw bit for channel3 event.*/
-            uint32_t cnt_thr_event_u4: 1;           /*This is the interrupt raw bit for channel4 event.*/
-            uint32_t cnt_thr_event_u5: 1;           /*This is the interrupt raw bit for channel5 event.*/
-            uint32_t cnt_thr_event_u6: 1;           /*This is the interrupt raw bit for channel6 event.*/
-            uint32_t cnt_thr_event_u7: 1;           /*This is the interrupt raw bit for channel7 event.*/
-            uint32_t reserved8:       24;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0: 1;            /*This is the  interrupt status bit for channel0 event.*/
-            uint32_t cnt_thr_event_u1: 1;            /*This is the  interrupt status bit for channel1 event.*/
-            uint32_t cnt_thr_event_u2: 1;            /*This is the  interrupt status bit for channel2 event.*/
-            uint32_t cnt_thr_event_u3: 1;            /*This is the  interrupt status bit for channel3 event.*/
-            uint32_t cnt_thr_event_u4: 1;            /*This is the  interrupt status bit for channel4 event.*/
-            uint32_t cnt_thr_event_u5: 1;            /*This is the  interrupt status bit for channel5 event.*/
-            uint32_t cnt_thr_event_u6: 1;            /*This is the  interrupt status bit for channel6 event.*/
-            uint32_t cnt_thr_event_u7: 1;            /*This is the  interrupt status bit for channel7 event.*/
-            uint32_t reserved8:       24;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0: 1;           /*This is the  interrupt enable bit for channel0 event.*/
-            uint32_t cnt_thr_event_u1: 1;           /*This is the  interrupt enable bit for channel1 event.*/
-            uint32_t cnt_thr_event_u2: 1;           /*This is the  interrupt enable bit for channel2 event.*/
-            uint32_t cnt_thr_event_u3: 1;           /*This is the  interrupt enable bit for channel3 event.*/
-            uint32_t cnt_thr_event_u4: 1;           /*This is the  interrupt enable bit for channel4 event.*/
-            uint32_t cnt_thr_event_u5: 1;           /*This is the  interrupt enable bit for channel5 event.*/
-            uint32_t cnt_thr_event_u6: 1;           /*This is the  interrupt enable bit for channel6 event.*/
-            uint32_t cnt_thr_event_u7: 1;           /*This is the  interrupt enable bit for channel7 event.*/
-            uint32_t reserved8:       24;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0: 1;           /*Set this bit to clear channel0 event interrupt.*/
-            uint32_t cnt_thr_event_u1: 1;           /*Set this bit to clear channel1 event interrupt.*/
-            uint32_t cnt_thr_event_u2: 1;           /*Set this bit to clear channel2 event interrupt.*/
-            uint32_t cnt_thr_event_u3: 1;           /*Set this bit to clear channel3 event interrupt.*/
-            uint32_t cnt_thr_event_u4: 1;           /*Set this bit to clear channel4 event interrupt.*/
-            uint32_t cnt_thr_event_u5: 1;           /*Set this bit to clear channel5 event interrupt.*/
-            uint32_t cnt_thr_event_u6: 1;           /*Set this bit to clear channel6 event interrupt.*/
-            uint32_t cnt_thr_event_u7: 1;           /*Set this bit to clear channel7 event interrupt.*/
-            uint32_t reserved8:       24;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t cnt_mode:2;                    /*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/
-            uint32_t thres1_lat:1;                  /* counter value equals to thresh1*/
-            uint32_t thres0_lat:1;                  /* counter value equals to thresh0*/
-            uint32_t l_lim_lat:1;                   /* counter value reaches h_lim*/
-            uint32_t h_lim_lat:1;                   /* counter value reaches l_lim*/
-            uint32_t zero_lat:1;                    /* counter value equals zero*/
-            uint32_t reserved7:25;
-        };
-        uint32_t val;
-    } status_unit[8];
-    union {
-        struct {
-            uint32_t cnt_rst_u0:   1;               /*Set this bit to clear unit0's counter.*/
-            uint32_t cnt_pause_u0: 1;               /*Set this bit to pause unit0's counter.*/
-            uint32_t cnt_rst_u1:   1;               /*Set this bit to clear unit1's counter.*/
-            uint32_t cnt_pause_u1: 1;               /*Set this bit to pause unit1's counter.*/
-            uint32_t cnt_rst_u2:   1;               /*Set this bit to clear unit2's counter.*/
-            uint32_t cnt_pause_u2: 1;               /*Set this bit to pause unit2's counter.*/
-            uint32_t cnt_rst_u3:   1;               /*Set this bit to clear unit3's counter.*/
-            uint32_t cnt_pause_u3: 1;               /*Set this bit to pause unit3's counter.*/
-            uint32_t cnt_rst_u4:   1;               /*Set this bit to clear unit4's counter.*/
-            uint32_t cnt_pause_u4: 1;               /*Set this bit to pause unit4's counter.*/
-            uint32_t cnt_rst_u5:   1;               /*Set this bit to clear unit5's counter.*/
-            uint32_t cnt_pause_u5: 1;               /*Set this bit to pause unit5's counter.*/
-            uint32_t cnt_rst_u6:   1;               /*Set this bit to clear unit6's counter.*/
-            uint32_t cnt_pause_u6: 1;               /*Set this bit to pause unit6's counter.*/
-            uint32_t cnt_rst_u7:   1;               /*Set this bit to clear unit7's counter.*/
-            uint32_t cnt_pause_u7: 1;               /*Set this bit to pause unit7's counter.*/
-            uint32_t clk_en:       1;
-            uint32_t reserved17:  15;
-        };
-        uint32_t val;
-    } ctrl;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t date;                                  /**/
-} pcnt_dev_t;
-extern pcnt_dev_t PCNT;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_PCNT_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/periph_defs.h b/tools/sdk/include/soc/soc/periph_defs.h
deleted file mode 100644
index c4ad589c9dd..00000000000
--- a/tools/sdk/include/soc/soc/periph_defs.h
+++ /dev/null
@@ -1,64 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_PERIPH_DEFS_H_
-#define _SOC_PERIPH_DEFS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PERIPH_LEDC_MODULE = 0,
-    PERIPH_UART0_MODULE,
-    PERIPH_UART1_MODULE,
-    PERIPH_UART2_MODULE,
-    PERIPH_I2C0_MODULE,
-    PERIPH_I2C1_MODULE,
-    PERIPH_I2S0_MODULE,
-    PERIPH_I2S1_MODULE,
-    PERIPH_TIMG0_MODULE,
-    PERIPH_TIMG1_MODULE,
-    PERIPH_PWM0_MODULE,
-    PERIPH_PWM1_MODULE,
-    PERIPH_PWM2_MODULE,
-    PERIPH_PWM3_MODULE,
-    PERIPH_UHCI0_MODULE,
-    PERIPH_UHCI1_MODULE,
-    PERIPH_RMT_MODULE,
-    PERIPH_PCNT_MODULE,
-    PERIPH_SPI_MODULE,
-    PERIPH_HSPI_MODULE,
-    PERIPH_VSPI_MODULE,
-    PERIPH_SPI_DMA_MODULE,
-    PERIPH_SDMMC_MODULE,
-    PERIPH_SDIO_SLAVE_MODULE,
-    PERIPH_CAN_MODULE,
-    PERIPH_EMAC_MODULE,
-    PERIPH_RNG_MODULE,
-    PERIPH_WIFI_MODULE,
-    PERIPH_BT_MODULE,
-    PERIPH_WIFI_BT_COMMON_MODULE,
-    PERIPH_BT_BASEBAND_MODULE,
-    PERIPH_BT_LC_MODULE,
-    PERIPH_AES_MODULE,
-    PERIPH_SHA_MODULE,
-    PERIPH_RSA_MODULE,
-} periph_module_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SOC_PERIPH_DEFS_H_ */
diff --git a/tools/sdk/include/soc/soc/pid.h b/tools/sdk/include/soc/soc/pid.h
deleted file mode 100644
index bd4e9f26d24..00000000000
--- a/tools/sdk/include/soc/soc/pid.h
+++ /dev/null
@@ -1,65 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_PID_H_
-#define _SOC_PID_H_
-
-#define PROPID_GEN_BASE 0x3FF1F000
-//Bits 1..7: 1 if interrupt will be triggering PID change
-#define PROPID_CONFIG_INTERRUPT_ENABLE	((PROPID_GEN_BASE)+0x000)
-//Vectors for the various interrupt handlers
-#define PROPID_CONFIG_INTERRUPT_ADDR_1	((PROPID_GEN_BASE)+0x004)
-#define PROPID_CONFIG_INTERRUPT_ADDR_2	((PROPID_GEN_BASE)+0x008)
-#define PROPID_CONFIG_INTERRUPT_ADDR_3	((PROPID_GEN_BASE)+0x00C)
-#define PROPID_CONFIG_INTERRUPT_ADDR_4	((PROPID_GEN_BASE)+0x010)
-#define PROPID_CONFIG_INTERRUPT_ADDR_5	((PROPID_GEN_BASE)+0x014)
-#define PROPID_CONFIG_INTERRUPT_ADDR_6	((PROPID_GEN_BASE)+0x018)
-#define PROPID_CONFIG_INTERRUPT_ADDR_7	((PROPID_GEN_BASE)+0x01C)
-
-//Delay, in CPU cycles, before switching to new PID
-#define PROPID_CONFIG_PID_DELAY			((PROPID_GEN_BASE)+0x020)
-#define PROPID_CONFIG_NMI_DELAY			((PROPID_GEN_BASE)+0x024)
-
-//Last detected interrupt. Set by hw on int.
-#define PROPID_TABLE_LEVEL				((PROPID_GEN_BASE)+0x028)
-//PID/prev int data for each int
-#define PROPID_FROM_1					((PROPID_GEN_BASE)+0x02C)
-#define PROPID_FROM_2					((PROPID_GEN_BASE)+0x030)
-#define PROPID_FROM_3					((PROPID_GEN_BASE)+0x034)
-#define PROPID_FROM_4					((PROPID_GEN_BASE)+0x038)
-#define PROPID_FROM_5					((PROPID_GEN_BASE)+0x03C)
-#define PROPID_FROM_6					((PROPID_GEN_BASE)+0x040)
-#define PROPID_FROM_7					((PROPID_GEN_BASE)+0x044)
-#define PROPID_FROM_PID_MASK	0x7
-#define PROPID_FROM_PID_S		0
-#define PROPID_FROM_INT_MASK	0xF
-#define PROPID_FROM_INT_S		3
-
-//PID to be set after confirm routine
-#define PROPID_PID_NEW					((PROPID_GEN_BASE)+0x048)
-//Write to kick off PID change
-#define PROPID_PID_CONFIRM				((PROPID_GEN_BASE)+0x04c)
-//current PID?
-#define PROPID_PID_REG					((PROPID_GEN_BASE)+0x050)
-
-//Write to mask NMI
-#define PROPID_PID_NMI_MASK_HW_ENABLE	((PROPID_GEN_BASE)+0x054)
-//Write to unmask NMI
-#define PROPID_PID_NMI_MASK_HW_DISABLE	((PROPID_GEN_BASE)+0x058)
-#define PROPID_PID_NMI_MASK_HW_REG		((PROPID_GEN_BASE)+0x05c)
-
-//Debug regs
-#define PROPID_PID						((PROPID_GEN_BASE)+0x060)
-#define PROPID_NMI_MASK_HW				((PROPID_GEN_BASE)+0x064)
-
-#endif /* _SOC_PID_H_ */
diff --git a/tools/sdk/include/soc/soc/rmt_reg.h b/tools/sdk/include/soc/soc/rmt_reg.h
deleted file mode 100644
index 15c2f9a2dc6..00000000000
--- a/tools/sdk/include/soc/soc/rmt_reg.h
+++ /dev/null
@@ -1,2604 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_RMT_REG_H_
-#define _SOC_RMT_REG_H_
-
-#include "soc.h"
-#define RMT_CH0DATA_REG          (DR_REG_RMT_BASE + 0x0000)
-
-#define RMT_CH1DATA_REG          (DR_REG_RMT_BASE + 0x0004)
-
-#define RMT_CH2DATA_REG          (DR_REG_RMT_BASE + 0x0008)
-
-#define RMT_CH3DATA_REG          (DR_REG_RMT_BASE + 0x000c)
-
-#define RMT_CH4DATA_REG          (DR_REG_RMT_BASE + 0x0010)
-
-#define RMT_CH5DATA_REG          (DR_REG_RMT_BASE + 0x0014)
-
-#define RMT_CH6DATA_REG          (DR_REG_RMT_BASE + 0x0018)
-
-#define RMT_CH7DATA_REG          (DR_REG_RMT_BASE + 0x001c)
-
-#define RMT_CH0CONF0_REG          (DR_REG_RMT_BASE + 0x0020)
-/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: This bit  is used  to control clock.when software config RMT
- internal registers  it controls the register clock.*/
-#define RMT_CLK_EN  (BIT(31))
-#define RMT_CLK_EN_M  (BIT(31))
-#define RMT_CLK_EN_V  0x1
-#define RMT_CLK_EN_S  31
-/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/
-#define RMT_MEM_PD  (BIT(30))
-#define RMT_MEM_PD_M  (BIT(30))
-#define RMT_MEM_PD_V  0x1
-#define RMT_MEM_PD_S  30
-/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit is used to configure the way carrier wave is modulated
- for  channel0.1'b1:transmit on low output level  1'b0:transmit  on high output level.*/
-#define RMT_CARRIER_OUT_LV_CH0  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH0_M  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH0_V  0x1
-#define RMT_CARRIER_OUT_LV_CH0_S  29
-/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: This is the carrier modulation enable control bit for channel0.*/
-#define RMT_CARRIER_EN_CH0  (BIT(28))
-#define RMT_CARRIER_EN_CH0_M  (BIT(28))
-#define RMT_CARRIER_EN_CH0_V  0x1
-#define RMT_CARRIER_EN_CH0_S  28
-/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
-/*description: This register is used to configure the the amount of memory blocks
- allocated to channel0.*/
-#define RMT_MEM_SIZE_CH0  0x0000000F
-#define RMT_MEM_SIZE_CH0_M  ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S))
-#define RMT_MEM_SIZE_CH0_V  0xF
-#define RMT_MEM_SIZE_CH0_S  24
-/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
-/*description: In receive mode when no edge is detected on the input signal
- for longer than reg_idle_thres_ch0 then the receive process is done.*/
-#define RMT_IDLE_THRES_CH0  0x0000FFFF
-#define RMT_IDLE_THRES_CH0_M  ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S))
-#define RMT_IDLE_THRES_CH0_V  0xFFFF
-#define RMT_IDLE_THRES_CH0_S  8
-/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
-/*description: This register is used to configure the  frequency divider's factor in channel0.*/
-#define RMT_DIV_CNT_CH0  0x000000FF
-#define RMT_DIV_CNT_CH0_M  ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S))
-#define RMT_DIV_CNT_CH0_V  0xFF
-#define RMT_DIV_CNT_CH0_S  0
-
-#define RMT_CH0CONF1_REG          (DR_REG_RMT_BASE + 0x0024)
-/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for channel0 in IDLE state.*/
-#define RMT_IDLE_OUT_EN_CH0  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH0_M  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH0_V  0x1
-#define RMT_IDLE_OUT_EN_CH0_S  19
-/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This bit configures the output signal's level for channel0 in IDLE state.*/
-#define RMT_IDLE_OUT_LV_CH0  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH0_M  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH0_V  0x1
-#define RMT_IDLE_OUT_LV_CH0_S  18
-/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
-#define RMT_REF_ALWAYS_ON_CH0  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH0_M  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH0_V  0x1
-#define RMT_REF_ALWAYS_ON_CH0_S  17
-/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This bit is used to reset divider in channel0.*/
-#define RMT_REF_CNT_RST_CH0  (BIT(16))
-#define RMT_REF_CNT_RST_CH0_M  (BIT(16))
-#define RMT_REF_CNT_RST_CH0_V  0x1
-#define RMT_REF_CNT_RST_CH0_S  16
-/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
-/*description: in receive mode  channel0 ignore input pulse when the pulse width
- is smaller then this value.*/
-#define RMT_RX_FILTER_THRES_CH0  0x000000FF
-#define RMT_RX_FILTER_THRES_CH0_M  ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S))
-#define RMT_RX_FILTER_THRES_CH0_V  0xFF
-#define RMT_RX_FILTER_THRES_CH0_S  8
-/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the receive filter enable bit for channel0.*/
-#define RMT_RX_FILTER_EN_CH0  (BIT(7))
-#define RMT_RX_FILTER_EN_CH0_M  (BIT(7))
-#define RMT_RX_FILTER_EN_CH0_V  0x1
-#define RMT_RX_FILTER_EN_CH0_S  7
-/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to continue sending  from the first data to the
- last data in channel0 again and again.*/
-#define RMT_TX_CONTI_MODE_CH0  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH0_M  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH0_V  0x1
-#define RMT_TX_CONTI_MODE_CH0_S  6
-/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: This is the mark of channel0's ram usage right.1'b1：receiver
- uses the ram  0：transmitter uses the ram*/
-#define RMT_MEM_OWNER_CH0  (BIT(5))
-#define RMT_MEM_OWNER_CH0_M  (BIT(5))
-#define RMT_MEM_OWNER_CH0_V  0x1
-#define RMT_MEM_OWNER_CH0_S  5
-/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/
-#define RMT_APB_MEM_RST_CH0  (BIT(4))
-#define RMT_APB_MEM_RST_CH0_M  (BIT(4))
-#define RMT_APB_MEM_RST_CH0_V  0x1
-#define RMT_APB_MEM_RST_CH0_S  4
-/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/
-#define RMT_MEM_RD_RST_CH0  (BIT(3))
-#define RMT_MEM_RD_RST_CH0_M  (BIT(3))
-#define RMT_MEM_RD_RST_CH0_V  0x1
-#define RMT_MEM_RD_RST_CH0_S  3
-/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to reset write ram address for channel0 by receiver access.*/
-#define RMT_MEM_WR_RST_CH0  (BIT(2))
-#define RMT_MEM_WR_RST_CH0_M  (BIT(2))
-#define RMT_MEM_WR_RST_CH0_V  0x1
-#define RMT_MEM_WR_RST_CH0_S  2
-/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Set this bit to enbale receving data for channel0.*/
-#define RMT_RX_EN_CH0  (BIT(1))
-#define RMT_RX_EN_CH0_M  (BIT(1))
-#define RMT_RX_EN_CH0_V  0x1
-#define RMT_RX_EN_CH0_S  1
-/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to start sending data for channel0.*/
-#define RMT_TX_START_CH0  (BIT(0))
-#define RMT_TX_START_CH0_M  (BIT(0))
-#define RMT_TX_START_CH0_V  0x1
-#define RMT_TX_START_CH0_S  0
-
-#define RMT_CH1CONF0_REG          (DR_REG_RMT_BASE + 0x0028)
-/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit is used to configure the way carrier wave is modulated
- for  channel1.1'b1:transmit on low output level  1'b0:transmit  on high output level.*/
-#define RMT_CARRIER_OUT_LV_CH1  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH1_M  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH1_V  0x1
-#define RMT_CARRIER_OUT_LV_CH1_S  29
-/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: This is the carrier modulation enable control bit for channel1.*/
-#define RMT_CARRIER_EN_CH1  (BIT(28))
-#define RMT_CARRIER_EN_CH1_M  (BIT(28))
-#define RMT_CARRIER_EN_CH1_V  0x1
-#define RMT_CARRIER_EN_CH1_S  28
-/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
-/*description: This register is used to configure the the amount of memory blocks
- allocated to channel1.*/
-#define RMT_MEM_SIZE_CH1  0x0000000F
-#define RMT_MEM_SIZE_CH1_M  ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S))
-#define RMT_MEM_SIZE_CH1_V  0xF
-#define RMT_MEM_SIZE_CH1_S  24
-/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
-/*description: This register is used to configure the the amount of memory blocks
- allocated to channel1.*/
-#define RMT_IDLE_THRES_CH1  0x0000FFFF
-#define RMT_IDLE_THRES_CH1_M  ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S))
-#define RMT_IDLE_THRES_CH1_V  0xFFFF
-#define RMT_IDLE_THRES_CH1_S  8
-/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
-/*description: This register is used to configure the  frequency divider's factor in channel1.*/
-#define RMT_DIV_CNT_CH1  0x000000FF
-#define RMT_DIV_CNT_CH1_M  ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S))
-#define RMT_DIV_CNT_CH1_V  0xFF
-#define RMT_DIV_CNT_CH1_S  0
-
-#define RMT_CH1CONF1_REG          (DR_REG_RMT_BASE + 0x002c)
-/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for channel1 in IDLE state.*/
-#define RMT_IDLE_OUT_EN_CH1  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH1_M  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH1_V  0x1
-#define RMT_IDLE_OUT_EN_CH1_S  19
-/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This bit configures the output signal's level for channel1 in IDLE state.*/
-#define RMT_IDLE_OUT_LV_CH1  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH1_M  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH1_V  0x1
-#define RMT_IDLE_OUT_LV_CH1_S  18
-/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
-#define RMT_REF_ALWAYS_ON_CH1  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH1_M  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH1_V  0x1
-#define RMT_REF_ALWAYS_ON_CH1_S  17
-/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This bit is used to reset divider in channel1.*/
-#define RMT_REF_CNT_RST_CH1  (BIT(16))
-#define RMT_REF_CNT_RST_CH1_M  (BIT(16))
-#define RMT_REF_CNT_RST_CH1_V  0x1
-#define RMT_REF_CNT_RST_CH1_S  16
-/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
-/*description: in receive mode  channel1 ignore input pulse when the pulse width
- is smaller then this value.*/
-#define RMT_RX_FILTER_THRES_CH1  0x000000FF
-#define RMT_RX_FILTER_THRES_CH1_M  ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S))
-#define RMT_RX_FILTER_THRES_CH1_V  0xFF
-#define RMT_RX_FILTER_THRES_CH1_S  8
-/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the receive filter enable bit for channel1.*/
-#define RMT_RX_FILTER_EN_CH1  (BIT(7))
-#define RMT_RX_FILTER_EN_CH1_M  (BIT(7))
-#define RMT_RX_FILTER_EN_CH1_V  0x1
-#define RMT_RX_FILTER_EN_CH1_S  7
-/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to continue sending  from the first data to the
- last data in channel1 again and again.*/
-#define RMT_TX_CONTI_MODE_CH1  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH1_M  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH1_V  0x1
-#define RMT_TX_CONTI_MODE_CH1_S  6
-/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: This is the mark of channel1's ram usage right.1'b1：receiver
- uses the ram  0：transmitter uses the ram*/
-#define RMT_MEM_OWNER_CH1  (BIT(5))
-#define RMT_MEM_OWNER_CH1_M  (BIT(5))
-#define RMT_MEM_OWNER_CH1_V  0x1
-#define RMT_MEM_OWNER_CH1_S  5
-/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/
-#define RMT_APB_MEM_RST_CH1  (BIT(4))
-#define RMT_APB_MEM_RST_CH1_M  (BIT(4))
-#define RMT_APB_MEM_RST_CH1_V  0x1
-#define RMT_APB_MEM_RST_CH1_S  4
-/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/
-#define RMT_MEM_RD_RST_CH1  (BIT(3))
-#define RMT_MEM_RD_RST_CH1_M  (BIT(3))
-#define RMT_MEM_RD_RST_CH1_V  0x1
-#define RMT_MEM_RD_RST_CH1_S  3
-/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to reset write ram address for channel1 by receiver access.*/
-#define RMT_MEM_WR_RST_CH1  (BIT(2))
-#define RMT_MEM_WR_RST_CH1_M  (BIT(2))
-#define RMT_MEM_WR_RST_CH1_V  0x1
-#define RMT_MEM_WR_RST_CH1_S  2
-/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Set this bit to enbale receving data for channel1.*/
-#define RMT_RX_EN_CH1  (BIT(1))
-#define RMT_RX_EN_CH1_M  (BIT(1))
-#define RMT_RX_EN_CH1_V  0x1
-#define RMT_RX_EN_CH1_S  1
-/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to start sending data for channel1.*/
-#define RMT_TX_START_CH1  (BIT(0))
-#define RMT_TX_START_CH1_M  (BIT(0))
-#define RMT_TX_START_CH1_V  0x1
-#define RMT_TX_START_CH1_S  0
-
-#define RMT_CH2CONF0_REG          (DR_REG_RMT_BASE + 0x0030)
-/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add
- on low level  1'b0:add  on high level.*/
-#define RMT_CARRIER_OUT_LV_CH2  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH2_M  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH2_V  0x1
-#define RMT_CARRIER_OUT_LV_CH2_S  29
-/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: This is the carrier modulation enable control bit for channel2.*/
-#define RMT_CARRIER_EN_CH2  (BIT(28))
-#define RMT_CARRIER_EN_CH2_M  (BIT(28))
-#define RMT_CARRIER_EN_CH2_V  0x1
-#define RMT_CARRIER_EN_CH2_S  28
-/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
-/*description: This register is used to configure the the amount of memory blocks
- allocated to channel2.*/
-#define RMT_MEM_SIZE_CH2  0x0000000F
-#define RMT_MEM_SIZE_CH2_M  ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S))
-#define RMT_MEM_SIZE_CH2_V  0xF
-#define RMT_MEM_SIZE_CH2_S  24
-/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2
- then the receive process is done.*/
-#define RMT_IDLE_THRES_CH2  0x0000FFFF
-#define RMT_IDLE_THRES_CH2_M  ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S))
-#define RMT_IDLE_THRES_CH2_V  0xFFFF
-#define RMT_IDLE_THRES_CH2_S  8
-/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
-/*description: This register is used to configure the  frequency divider's factor in channel2.*/
-#define RMT_DIV_CNT_CH2  0x000000FF
-#define RMT_DIV_CNT_CH2_M  ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S))
-#define RMT_DIV_CNT_CH2_V  0xFF
-#define RMT_DIV_CNT_CH2_S  0
-
-#define RMT_CH2CONF1_REG          (DR_REG_RMT_BASE + 0x0034)
-/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for channel2 in IDLE state.*/
-#define RMT_IDLE_OUT_EN_CH2  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH2_M  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH2_V  0x1
-#define RMT_IDLE_OUT_EN_CH2_S  19
-/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This bit configures the output signal's level for channel2 in IDLE state.*/
-#define RMT_IDLE_OUT_LV_CH2  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH2_M  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH2_V  0x1
-#define RMT_IDLE_OUT_LV_CH2_S  18
-/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
-#define RMT_REF_ALWAYS_ON_CH2  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH2_M  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH2_V  0x1
-#define RMT_REF_ALWAYS_ON_CH2_S  17
-/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This bit is used to reset divider in channel2.*/
-#define RMT_REF_CNT_RST_CH2  (BIT(16))
-#define RMT_REF_CNT_RST_CH2_M  (BIT(16))
-#define RMT_REF_CNT_RST_CH2_V  0x1
-#define RMT_REF_CNT_RST_CH2_S  16
-/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
-/*description: in receive mode  channel2 ignore input pulse when the pulse width
- is smaller then this value.*/
-#define RMT_RX_FILTER_THRES_CH2  0x000000FF
-#define RMT_RX_FILTER_THRES_CH2_M  ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S))
-#define RMT_RX_FILTER_THRES_CH2_V  0xFF
-#define RMT_RX_FILTER_THRES_CH2_S  8
-/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the receive filter enable bit for channel2.*/
-#define RMT_RX_FILTER_EN_CH2  (BIT(7))
-#define RMT_RX_FILTER_EN_CH2_M  (BIT(7))
-#define RMT_RX_FILTER_EN_CH2_V  0x1
-#define RMT_RX_FILTER_EN_CH2_S  7
-/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to continue sending  from the first data to the
- last data in channel2.*/
-#define RMT_TX_CONTI_MODE_CH2  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH2_M  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH2_V  0x1
-#define RMT_TX_CONTI_MODE_CH2_S  6
-/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: This is the mark of channel2's ram usage right.1'b1：receiver
- uses the ram  0：transmitter uses the ram*/
-#define RMT_MEM_OWNER_CH2  (BIT(5))
-#define RMT_MEM_OWNER_CH2_M  (BIT(5))
-#define RMT_MEM_OWNER_CH2_V  0x1
-#define RMT_MEM_OWNER_CH2_S  5
-/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/
-#define RMT_APB_MEM_RST_CH2  (BIT(4))
-#define RMT_APB_MEM_RST_CH2_M  (BIT(4))
-#define RMT_APB_MEM_RST_CH2_V  0x1
-#define RMT_APB_MEM_RST_CH2_S  4
-/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/
-#define RMT_MEM_RD_RST_CH2  (BIT(3))
-#define RMT_MEM_RD_RST_CH2_M  (BIT(3))
-#define RMT_MEM_RD_RST_CH2_V  0x1
-#define RMT_MEM_RD_RST_CH2_S  3
-/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to reset write ram address for channel2 by receiver access.*/
-#define RMT_MEM_WR_RST_CH2  (BIT(2))
-#define RMT_MEM_WR_RST_CH2_M  (BIT(2))
-#define RMT_MEM_WR_RST_CH2_V  0x1
-#define RMT_MEM_WR_RST_CH2_S  2
-/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Set this bit to enbale receving data for channel2.*/
-#define RMT_RX_EN_CH2  (BIT(1))
-#define RMT_RX_EN_CH2_M  (BIT(1))
-#define RMT_RX_EN_CH2_V  0x1
-#define RMT_RX_EN_CH2_S  1
-/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to start sending data for channel2.*/
-#define RMT_TX_START_CH2  (BIT(0))
-#define RMT_TX_START_CH2_M  (BIT(0))
-#define RMT_TX_START_CH2_V  0x1
-#define RMT_TX_START_CH2_S  0
-
-#define RMT_CH3CONF0_REG          (DR_REG_RMT_BASE + 0x0038)
-/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add
- on low level  1'b0:add  on high level.*/
-#define RMT_CARRIER_OUT_LV_CH3  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH3_M  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH3_V  0x1
-#define RMT_CARRIER_OUT_LV_CH3_S  29
-/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: This is the carrier modulation enable control bit for channel3.*/
-#define RMT_CARRIER_EN_CH3  (BIT(28))
-#define RMT_CARRIER_EN_CH3_M  (BIT(28))
-#define RMT_CARRIER_EN_CH3_V  0x1
-#define RMT_CARRIER_EN_CH3_S  28
-/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
-/*description: This register is used to configure the the amount of memory blocks
- allocated to channel3.*/
-#define RMT_MEM_SIZE_CH3  0x0000000F
-#define RMT_MEM_SIZE_CH3_M  ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S))
-#define RMT_MEM_SIZE_CH3_V  0xF
-#define RMT_MEM_SIZE_CH3_S  24
-/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3
- then the receive process is done.*/
-#define RMT_IDLE_THRES_CH3  0x0000FFFF
-#define RMT_IDLE_THRES_CH3_M  ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S))
-#define RMT_IDLE_THRES_CH3_V  0xFFFF
-#define RMT_IDLE_THRES_CH3_S  8
-/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
-/*description: This register is used to configure the  frequency divider's factor in channel3.*/
-#define RMT_DIV_CNT_CH3  0x000000FF
-#define RMT_DIV_CNT_CH3_M  ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S))
-#define RMT_DIV_CNT_CH3_V  0xFF
-#define RMT_DIV_CNT_CH3_S  0
-
-#define RMT_CH3CONF1_REG          (DR_REG_RMT_BASE + 0x003c)
-/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for channel3 in IDLE state.*/
-#define RMT_IDLE_OUT_EN_CH3  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH3_M  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH3_V  0x1
-#define RMT_IDLE_OUT_EN_CH3_S  19
-/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This bit configures the output signal's level for channel3 in IDLE state.*/
-#define RMT_IDLE_OUT_LV_CH3  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH3_M  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH3_V  0x1
-#define RMT_IDLE_OUT_LV_CH3_S  18
-/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
-#define RMT_REF_ALWAYS_ON_CH3  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH3_M  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH3_V  0x1
-#define RMT_REF_ALWAYS_ON_CH3_S  17
-/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This bit is used to reset divider in channel3.*/
-#define RMT_REF_CNT_RST_CH3  (BIT(16))
-#define RMT_REF_CNT_RST_CH3_M  (BIT(16))
-#define RMT_REF_CNT_RST_CH3_V  0x1
-#define RMT_REF_CNT_RST_CH3_S  16
-/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
-/*description: in receive mode  channel3 ignore input pulse when the pulse width
- is smaller then this value.*/
-#define RMT_RX_FILTER_THRES_CH3  0x000000FF
-#define RMT_RX_FILTER_THRES_CH3_M  ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S))
-#define RMT_RX_FILTER_THRES_CH3_V  0xFF
-#define RMT_RX_FILTER_THRES_CH3_S  8
-/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the receive filter enable bit for channel3.*/
-#define RMT_RX_FILTER_EN_CH3  (BIT(7))
-#define RMT_RX_FILTER_EN_CH3_M  (BIT(7))
-#define RMT_RX_FILTER_EN_CH3_V  0x1
-#define RMT_RX_FILTER_EN_CH3_S  7
-/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to continue sending  from the first data to the
- last data in channel3.*/
-#define RMT_TX_CONTI_MODE_CH3  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH3_M  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH3_V  0x1
-#define RMT_TX_CONTI_MODE_CH3_S  6
-/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: This is the mark of channel3's ram usage right.1'b1：receiver
- uses the ram  0：transmitter uses the ram*/
-#define RMT_MEM_OWNER_CH3  (BIT(5))
-#define RMT_MEM_OWNER_CH3_M  (BIT(5))
-#define RMT_MEM_OWNER_CH3_V  0x1
-#define RMT_MEM_OWNER_CH3_S  5
-/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/
-#define RMT_APB_MEM_RST_CH3  (BIT(4))
-#define RMT_APB_MEM_RST_CH3_M  (BIT(4))
-#define RMT_APB_MEM_RST_CH3_V  0x1
-#define RMT_APB_MEM_RST_CH3_S  4
-/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/
-#define RMT_MEM_RD_RST_CH3  (BIT(3))
-#define RMT_MEM_RD_RST_CH3_M  (BIT(3))
-#define RMT_MEM_RD_RST_CH3_V  0x1
-#define RMT_MEM_RD_RST_CH3_S  3
-/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to reset write ram address for channel3 by receiver access.*/
-#define RMT_MEM_WR_RST_CH3  (BIT(2))
-#define RMT_MEM_WR_RST_CH3_M  (BIT(2))
-#define RMT_MEM_WR_RST_CH3_V  0x1
-#define RMT_MEM_WR_RST_CH3_S  2
-/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Set this bit to enbale receving data for channel3.*/
-#define RMT_RX_EN_CH3  (BIT(1))
-#define RMT_RX_EN_CH3_M  (BIT(1))
-#define RMT_RX_EN_CH3_V  0x1
-#define RMT_RX_EN_CH3_S  1
-/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to start sending data for channel3.*/
-#define RMT_TX_START_CH3  (BIT(0))
-#define RMT_TX_START_CH3_M  (BIT(0))
-#define RMT_TX_START_CH3_V  0x1
-#define RMT_TX_START_CH3_S  0
-
-#define RMT_CH4CONF0_REG          (DR_REG_RMT_BASE + 0x0040)
-/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add
- on low level  1'b0:add  on high level.*/
-#define RMT_CARRIER_OUT_LV_CH4  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH4_M  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH4_V  0x1
-#define RMT_CARRIER_OUT_LV_CH4_S  29
-/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: This is the carrier modulation enable control bit for channel4.*/
-#define RMT_CARRIER_EN_CH4  (BIT(28))
-#define RMT_CARRIER_EN_CH4_M  (BIT(28))
-#define RMT_CARRIER_EN_CH4_V  0x1
-#define RMT_CARRIER_EN_CH4_S  28
-/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
-/*description: This register is used to configure the the amount of memory blocks
- allocated to channel4.*/
-#define RMT_MEM_SIZE_CH4  0x0000000F
-#define RMT_MEM_SIZE_CH4_M  ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S))
-#define RMT_MEM_SIZE_CH4_V  0xF
-#define RMT_MEM_SIZE_CH4_S  24
-/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4
- then the receive process is done.*/
-#define RMT_IDLE_THRES_CH4  0x0000FFFF
-#define RMT_IDLE_THRES_CH4_M  ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S))
-#define RMT_IDLE_THRES_CH4_V  0xFFFF
-#define RMT_IDLE_THRES_CH4_S  8
-/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
-/*description: This register is used to configure the  frequency divider's factor in channel4.*/
-#define RMT_DIV_CNT_CH4  0x000000FF
-#define RMT_DIV_CNT_CH4_M  ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S))
-#define RMT_DIV_CNT_CH4_V  0xFF
-#define RMT_DIV_CNT_CH4_S  0
-
-#define RMT_CH4CONF1_REG          (DR_REG_RMT_BASE + 0x0044)
-/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for channel4 in IDLE state.*/
-#define RMT_IDLE_OUT_EN_CH4  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH4_M  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH4_V  0x1
-#define RMT_IDLE_OUT_EN_CH4_S  19
-/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This bit configures the output signal's level for channel4 in IDLE state.*/
-#define RMT_IDLE_OUT_LV_CH4  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH4_M  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH4_V  0x1
-#define RMT_IDLE_OUT_LV_CH4_S  18
-/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
-#define RMT_REF_ALWAYS_ON_CH4  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH4_M  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH4_V  0x1
-#define RMT_REF_ALWAYS_ON_CH4_S  17
-/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This bit is used to reset divider in channel4.*/
-#define RMT_REF_CNT_RST_CH4  (BIT(16))
-#define RMT_REF_CNT_RST_CH4_M  (BIT(16))
-#define RMT_REF_CNT_RST_CH4_V  0x1
-#define RMT_REF_CNT_RST_CH4_S  16
-/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
-/*description: in receive mode  channel4 ignore input pulse when the pulse width
- is smaller then this value.*/
-#define RMT_RX_FILTER_THRES_CH4  0x000000FF
-#define RMT_RX_FILTER_THRES_CH4_M  ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S))
-#define RMT_RX_FILTER_THRES_CH4_V  0xFF
-#define RMT_RX_FILTER_THRES_CH4_S  8
-/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the receive filter enable bit for channel4.*/
-#define RMT_RX_FILTER_EN_CH4  (BIT(7))
-#define RMT_RX_FILTER_EN_CH4_M  (BIT(7))
-#define RMT_RX_FILTER_EN_CH4_V  0x1
-#define RMT_RX_FILTER_EN_CH4_S  7
-/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to continue sending  from the first data to the
- last data in channel4.*/
-#define RMT_TX_CONTI_MODE_CH4  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH4_M  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH4_V  0x1
-#define RMT_TX_CONTI_MODE_CH4_S  6
-/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: This is the mark of channel4's ram usage right.1'b1：receiver
- uses the ram  0：transmitter uses the ram*/
-#define RMT_MEM_OWNER_CH4  (BIT(5))
-#define RMT_MEM_OWNER_CH4_M  (BIT(5))
-#define RMT_MEM_OWNER_CH4_V  0x1
-#define RMT_MEM_OWNER_CH4_S  5
-/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/
-#define RMT_APB_MEM_RST_CH4  (BIT(4))
-#define RMT_APB_MEM_RST_CH4_M  (BIT(4))
-#define RMT_APB_MEM_RST_CH4_V  0x1
-#define RMT_APB_MEM_RST_CH4_S  4
-/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/
-#define RMT_MEM_RD_RST_CH4  (BIT(3))
-#define RMT_MEM_RD_RST_CH4_M  (BIT(3))
-#define RMT_MEM_RD_RST_CH4_V  0x1
-#define RMT_MEM_RD_RST_CH4_S  3
-/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to reset write ram address for channel4 by receiver access.*/
-#define RMT_MEM_WR_RST_CH4  (BIT(2))
-#define RMT_MEM_WR_RST_CH4_M  (BIT(2))
-#define RMT_MEM_WR_RST_CH4_V  0x1
-#define RMT_MEM_WR_RST_CH4_S  2
-/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Set this bit to enbale receving data for channel4.*/
-#define RMT_RX_EN_CH4  (BIT(1))
-#define RMT_RX_EN_CH4_M  (BIT(1))
-#define RMT_RX_EN_CH4_V  0x1
-#define RMT_RX_EN_CH4_S  1
-/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to start sending data for channel4.*/
-#define RMT_TX_START_CH4  (BIT(0))
-#define RMT_TX_START_CH4_M  (BIT(0))
-#define RMT_TX_START_CH4_V  0x1
-#define RMT_TX_START_CH4_S  0
-
-#define RMT_CH5CONF0_REG          (DR_REG_RMT_BASE + 0x0048)
-/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add
- on low level  1'b0:add  on high level.*/
-#define RMT_CARRIER_OUT_LV_CH5  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH5_M  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH5_V  0x1
-#define RMT_CARRIER_OUT_LV_CH5_S  29
-/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: This is the carrier modulation enable control bit for channel5.*/
-#define RMT_CARRIER_EN_CH5  (BIT(28))
-#define RMT_CARRIER_EN_CH5_M  (BIT(28))
-#define RMT_CARRIER_EN_CH5_V  0x1
-#define RMT_CARRIER_EN_CH5_S  28
-/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
-/*description: This register is used to configure the the amount of memory blocks
- allocated to channel5.*/
-#define RMT_MEM_SIZE_CH5  0x0000000F
-#define RMT_MEM_SIZE_CH5_M  ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S))
-#define RMT_MEM_SIZE_CH5_V  0xF
-#define RMT_MEM_SIZE_CH5_S  24
-/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5
- then the receive process is done.*/
-#define RMT_IDLE_THRES_CH5  0x0000FFFF
-#define RMT_IDLE_THRES_CH5_M  ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S))
-#define RMT_IDLE_THRES_CH5_V  0xFFFF
-#define RMT_IDLE_THRES_CH5_S  8
-/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
-/*description: This register is used to configure the  frequency divider's factor in channel5.*/
-#define RMT_DIV_CNT_CH5  0x000000FF
-#define RMT_DIV_CNT_CH5_M  ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S))
-#define RMT_DIV_CNT_CH5_V  0xFF
-#define RMT_DIV_CNT_CH5_S  0
-
-#define RMT_CH5CONF1_REG          (DR_REG_RMT_BASE + 0x004c)
-/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for channel5 in IDLE state.*/
-#define RMT_IDLE_OUT_EN_CH5  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH5_M  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH5_V  0x1
-#define RMT_IDLE_OUT_EN_CH5_S  19
-/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This bit configures the output signal's level for channel5 in IDLE state.*/
-#define RMT_IDLE_OUT_LV_CH5  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH5_M  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH5_V  0x1
-#define RMT_IDLE_OUT_LV_CH5_S  18
-/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
-#define RMT_REF_ALWAYS_ON_CH5  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH5_M  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH5_V  0x1
-#define RMT_REF_ALWAYS_ON_CH5_S  17
-/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This bit is used to reset divider in channel5.*/
-#define RMT_REF_CNT_RST_CH5  (BIT(16))
-#define RMT_REF_CNT_RST_CH5_M  (BIT(16))
-#define RMT_REF_CNT_RST_CH5_V  0x1
-#define RMT_REF_CNT_RST_CH5_S  16
-/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
-/*description: in receive mode  channel5 ignore input pulse when the pulse width
- is smaller then this value.*/
-#define RMT_RX_FILTER_THRES_CH5  0x000000FF
-#define RMT_RX_FILTER_THRES_CH5_M  ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S))
-#define RMT_RX_FILTER_THRES_CH5_V  0xFF
-#define RMT_RX_FILTER_THRES_CH5_S  8
-/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the receive filter enable bit for channel5.*/
-#define RMT_RX_FILTER_EN_CH5  (BIT(7))
-#define RMT_RX_FILTER_EN_CH5_M  (BIT(7))
-#define RMT_RX_FILTER_EN_CH5_V  0x1
-#define RMT_RX_FILTER_EN_CH5_S  7
-/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to continue sending  from the first data to the
- last data in channel5.*/
-#define RMT_TX_CONTI_MODE_CH5  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH5_M  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH5_V  0x1
-#define RMT_TX_CONTI_MODE_CH5_S  6
-/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: This is the mark of channel5's ram usage right.1'b1：receiver
- uses the ram  0：transmitter uses the ram*/
-#define RMT_MEM_OWNER_CH5  (BIT(5))
-#define RMT_MEM_OWNER_CH5_M  (BIT(5))
-#define RMT_MEM_OWNER_CH5_V  0x1
-#define RMT_MEM_OWNER_CH5_S  5
-/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/
-#define RMT_APB_MEM_RST_CH5  (BIT(4))
-#define RMT_APB_MEM_RST_CH5_M  (BIT(4))
-#define RMT_APB_MEM_RST_CH5_V  0x1
-#define RMT_APB_MEM_RST_CH5_S  4
-/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/
-#define RMT_MEM_RD_RST_CH5  (BIT(3))
-#define RMT_MEM_RD_RST_CH5_M  (BIT(3))
-#define RMT_MEM_RD_RST_CH5_V  0x1
-#define RMT_MEM_RD_RST_CH5_S  3
-/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to reset write ram address for channel5 by receiver access.*/
-#define RMT_MEM_WR_RST_CH5  (BIT(2))
-#define RMT_MEM_WR_RST_CH5_M  (BIT(2))
-#define RMT_MEM_WR_RST_CH5_V  0x1
-#define RMT_MEM_WR_RST_CH5_S  2
-/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Set this bit to enbale receving data for channel5.*/
-#define RMT_RX_EN_CH5  (BIT(1))
-#define RMT_RX_EN_CH5_M  (BIT(1))
-#define RMT_RX_EN_CH5_V  0x1
-#define RMT_RX_EN_CH5_S  1
-/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to start sending data for channel5.*/
-#define RMT_TX_START_CH5  (BIT(0))
-#define RMT_TX_START_CH5_M  (BIT(0))
-#define RMT_TX_START_CH5_V  0x1
-#define RMT_TX_START_CH5_S  0
-
-#define RMT_CH6CONF0_REG          (DR_REG_RMT_BASE + 0x0050)
-/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add
- on low level  1'b0:add  on high level.*/
-#define RMT_CARRIER_OUT_LV_CH6  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH6_M  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH6_V  0x1
-#define RMT_CARRIER_OUT_LV_CH6_S  29
-/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: This is the carrier modulation enable control bit for channel6.*/
-#define RMT_CARRIER_EN_CH6  (BIT(28))
-#define RMT_CARRIER_EN_CH6_M  (BIT(28))
-#define RMT_CARRIER_EN_CH6_V  0x1
-#define RMT_CARRIER_EN_CH6_S  28
-/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
-/*description: This register is used to configure the the amount of memory blocks
- allocated to channel6.*/
-#define RMT_MEM_SIZE_CH6  0x0000000F
-#define RMT_MEM_SIZE_CH6_M  ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S))
-#define RMT_MEM_SIZE_CH6_V  0xF
-#define RMT_MEM_SIZE_CH6_S  24
-/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6
- then the receive process is done.*/
-#define RMT_IDLE_THRES_CH6  0x0000FFFF
-#define RMT_IDLE_THRES_CH6_M  ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S))
-#define RMT_IDLE_THRES_CH6_V  0xFFFF
-#define RMT_IDLE_THRES_CH6_S  8
-/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
-/*description: This register is used to configure the  frequency divider's factor in channel6.*/
-#define RMT_DIV_CNT_CH6  0x000000FF
-#define RMT_DIV_CNT_CH6_M  ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S))
-#define RMT_DIV_CNT_CH6_V  0xFF
-#define RMT_DIV_CNT_CH6_S  0
-
-#define RMT_CH6CONF1_REG          (DR_REG_RMT_BASE + 0x0054)
-/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for channel6 in IDLE state.*/
-#define RMT_IDLE_OUT_EN_CH6  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH6_M  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH6_V  0x1
-#define RMT_IDLE_OUT_EN_CH6_S  19
-/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This bit configures the output signal's level for channel6 in IDLE state.*/
-#define RMT_IDLE_OUT_LV_CH6  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH6_M  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH6_V  0x1
-#define RMT_IDLE_OUT_LV_CH6_S  18
-/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
-#define RMT_REF_ALWAYS_ON_CH6  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH6_M  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH6_V  0x1
-#define RMT_REF_ALWAYS_ON_CH6_S  17
-/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This bit is used to reset divider in channel6.*/
-#define RMT_REF_CNT_RST_CH6  (BIT(16))
-#define RMT_REF_CNT_RST_CH6_M  (BIT(16))
-#define RMT_REF_CNT_RST_CH6_V  0x1
-#define RMT_REF_CNT_RST_CH6_S  16
-/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
-/*description: in receive mode  channel6 ignore input pulse when the pulse width
- is smaller then this value.*/
-#define RMT_RX_FILTER_THRES_CH6  0x000000FF
-#define RMT_RX_FILTER_THRES_CH6_M  ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S))
-#define RMT_RX_FILTER_THRES_CH6_V  0xFF
-#define RMT_RX_FILTER_THRES_CH6_S  8
-/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the receive filter enable bit for channel6.*/
-#define RMT_RX_FILTER_EN_CH6  (BIT(7))
-#define RMT_RX_FILTER_EN_CH6_M  (BIT(7))
-#define RMT_RX_FILTER_EN_CH6_V  0x1
-#define RMT_RX_FILTER_EN_CH6_S  7
-/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to continue sending  from the first data to the
- last data in channel6.*/
-#define RMT_TX_CONTI_MODE_CH6  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH6_M  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH6_V  0x1
-#define RMT_TX_CONTI_MODE_CH6_S  6
-/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: This is the mark of channel6's ram usage right.1'b1：receiver
- uses the ram  0：transmitter uses the ram*/
-#define RMT_MEM_OWNER_CH6  (BIT(5))
-#define RMT_MEM_OWNER_CH6_M  (BIT(5))
-#define RMT_MEM_OWNER_CH6_V  0x1
-#define RMT_MEM_OWNER_CH6_S  5
-/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/
-#define RMT_APB_MEM_RST_CH6  (BIT(4))
-#define RMT_APB_MEM_RST_CH6_M  (BIT(4))
-#define RMT_APB_MEM_RST_CH6_V  0x1
-#define RMT_APB_MEM_RST_CH6_S  4
-/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/
-#define RMT_MEM_RD_RST_CH6  (BIT(3))
-#define RMT_MEM_RD_RST_CH6_M  (BIT(3))
-#define RMT_MEM_RD_RST_CH6_V  0x1
-#define RMT_MEM_RD_RST_CH6_S  3
-/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to reset write ram address for channel6 by receiver access.*/
-#define RMT_MEM_WR_RST_CH6  (BIT(2))
-#define RMT_MEM_WR_RST_CH6_M  (BIT(2))
-#define RMT_MEM_WR_RST_CH6_V  0x1
-#define RMT_MEM_WR_RST_CH6_S  2
-/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Set this bit to enbale receving data for channel6.*/
-#define RMT_RX_EN_CH6  (BIT(1))
-#define RMT_RX_EN_CH6_M  (BIT(1))
-#define RMT_RX_EN_CH6_V  0x1
-#define RMT_RX_EN_CH6_S  1
-/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to start sending data for channel6.*/
-#define RMT_TX_START_CH6  (BIT(0))
-#define RMT_TX_START_CH6_M  (BIT(0))
-#define RMT_TX_START_CH6_V  0x1
-#define RMT_TX_START_CH6_S  0
-
-#define RMT_CH7CONF0_REG          (DR_REG_RMT_BASE + 0x0058)
-/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add
- on low level  1'b0:add  on high level.*/
-#define RMT_CARRIER_OUT_LV_CH7  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH7_M  (BIT(29))
-#define RMT_CARRIER_OUT_LV_CH7_V  0x1
-#define RMT_CARRIER_OUT_LV_CH7_S  29
-/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: This is the carrier modulation enable control bit for channel7.*/
-#define RMT_CARRIER_EN_CH7  (BIT(28))
-#define RMT_CARRIER_EN_CH7_M  (BIT(28))
-#define RMT_CARRIER_EN_CH7_V  0x1
-#define RMT_CARRIER_EN_CH7_S  28
-/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
-/*description: This register is used to configure the the amount of memory blocks
- allocated to channel7.*/
-#define RMT_MEM_SIZE_CH7  0x0000000F
-#define RMT_MEM_SIZE_CH7_M  ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S))
-#define RMT_MEM_SIZE_CH7_V  0xF
-#define RMT_MEM_SIZE_CH7_S  24
-/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
-/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7
- then the receive process is done.*/
-#define RMT_IDLE_THRES_CH7  0x0000FFFF
-#define RMT_IDLE_THRES_CH7_M  ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S))
-#define RMT_IDLE_THRES_CH7_V  0xFFFF
-#define RMT_IDLE_THRES_CH7_S  8
-/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
-/*description: This register is used to configure the  frequency divider's factor in channel7.*/
-#define RMT_DIV_CNT_CH7  0x000000FF
-#define RMT_DIV_CNT_CH7_M  ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S))
-#define RMT_DIV_CNT_CH7_V  0xFF
-#define RMT_DIV_CNT_CH7_S  0
-
-#define RMT_CH7CONF1_REG          (DR_REG_RMT_BASE + 0x005c)
-/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the output enable control bit for channel6 in IDLE state.*/
-#define RMT_IDLE_OUT_EN_CH7  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH7_M  (BIT(19))
-#define RMT_IDLE_OUT_EN_CH7_V  0x1
-#define RMT_IDLE_OUT_EN_CH7_S  19
-/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This bit configures the output signal's level for channel7 in IDLE state.*/
-#define RMT_IDLE_OUT_LV_CH7  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH7_M  (BIT(18))
-#define RMT_IDLE_OUT_LV_CH7_V  0x1
-#define RMT_IDLE_OUT_LV_CH7_S  18
-/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
-#define RMT_REF_ALWAYS_ON_CH7  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH7_M  (BIT(17))
-#define RMT_REF_ALWAYS_ON_CH7_V  0x1
-#define RMT_REF_ALWAYS_ON_CH7_S  17
-/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This bit is used to reset divider in channel7.*/
-#define RMT_REF_CNT_RST_CH7  (BIT(16))
-#define RMT_REF_CNT_RST_CH7_M  (BIT(16))
-#define RMT_REF_CNT_RST_CH7_V  0x1
-#define RMT_REF_CNT_RST_CH7_S  16
-/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
-/*description: in receive mode  channel7 ignore input pulse when the pulse width
- is smaller then this value.*/
-#define RMT_RX_FILTER_THRES_CH7  0x000000FF
-#define RMT_RX_FILTER_THRES_CH7_M  ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S))
-#define RMT_RX_FILTER_THRES_CH7_V  0xFF
-#define RMT_RX_FILTER_THRES_CH7_S  8
-/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the receive filter enable bit for channel7.*/
-#define RMT_RX_FILTER_EN_CH7  (BIT(7))
-#define RMT_RX_FILTER_EN_CH7_M  (BIT(7))
-#define RMT_RX_FILTER_EN_CH7_V  0x1
-#define RMT_RX_FILTER_EN_CH7_S  7
-/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to continue sending  from the first data to the
- last data in channel7.*/
-#define RMT_TX_CONTI_MODE_CH7  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH7_M  (BIT(6))
-#define RMT_TX_CONTI_MODE_CH7_V  0x1
-#define RMT_TX_CONTI_MODE_CH7_S  6
-/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: This is the mark of channel7's ram usage right.1'b1：receiver
- uses the ram  0：transmitter uses the ram*/
-#define RMT_MEM_OWNER_CH7  (BIT(5))
-#define RMT_MEM_OWNER_CH7_M  (BIT(5))
-#define RMT_MEM_OWNER_CH7_V  0x1
-#define RMT_MEM_OWNER_CH7_S  5
-/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/
-#define RMT_APB_MEM_RST_CH7  (BIT(4))
-#define RMT_APB_MEM_RST_CH7_M  (BIT(4))
-#define RMT_APB_MEM_RST_CH7_V  0x1
-#define RMT_APB_MEM_RST_CH7_S  4
-/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/
-#define RMT_MEM_RD_RST_CH7  (BIT(3))
-#define RMT_MEM_RD_RST_CH7_M  (BIT(3))
-#define RMT_MEM_RD_RST_CH7_V  0x1
-#define RMT_MEM_RD_RST_CH7_S  3
-/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to reset write ram address for channel7 by receiver access.*/
-#define RMT_MEM_WR_RST_CH7  (BIT(2))
-#define RMT_MEM_WR_RST_CH7_M  (BIT(2))
-#define RMT_MEM_WR_RST_CH7_V  0x1
-#define RMT_MEM_WR_RST_CH7_S  2
-/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: Set this bit to enbale receving data for channel7.*/
-#define RMT_RX_EN_CH7  (BIT(1))
-#define RMT_RX_EN_CH7_M  (BIT(1))
-#define RMT_RX_EN_CH7_V  0x1
-#define RMT_RX_EN_CH7_S  1
-/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to start sending data for channel7.*/
-#define RMT_TX_START_CH7  (BIT(0))
-#define RMT_TX_START_CH7_M  (BIT(0))
-#define RMT_TX_START_CH7_V  0x1
-#define RMT_TX_START_CH7_S  0
-
-#define RMT_CH0STATUS_REG          (DR_REG_RMT_BASE + 0x0060)
-/* RMT_STATUS_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The status for channel0*/
-#define RMT_STATUS_CH0  0xFFFFFFFF
-#define RMT_STATUS_CH0_M  ((RMT_STATUS_CH0_V)<<(RMT_STATUS_CH0_S))
-#define RMT_STATUS_CH0_V  0xFFFFFFFF
-#define RMT_STATUS_CH0_S  0
-/* RMT_APB_MEM_RD_ERR_CH0 : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The apb read memory status bit for channel0 turns to
- high level when the apb read address exceeds the configuration range.*/
-#define RMT_APB_MEM_RD_ERR_CH0 (BIT(31))
-#define RMT_APB_MEM_RD_ERR_CH0_M  ((RMT_APB_MEM_RD_ERR_CH0_V)<<(RMT_APB_MEM_RD_ERR_CH0_S))
-#define RMT_APB_MEM_RD_ERR_CH0_V  0x1
-#define RMT_APB_MEM_RD_ERR_CH0_S  31
-/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The apb write memory status bit for channel0 turns to
- high level when the apb write address exceeds the configuration range.*/
-#define RMT_APB_MEM_WR_ERR_CH0 (BIT(30))
-#define RMT_APB_MEM_WR_ERR_CH0_M  ((RMT_APB_MEM_WR_ERR_CH0_V)<<(RMT_APB_MEM_WR_ERR_CH0_S))
-#define RMT_APB_MEM_WR_ERR_CH0_V  0x1
-#define RMT_APB_MEM_WR_ERR_CH0_S  30
-/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The memory empty status bit for channel0. in acyclic mode,
- this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
-#define RMT_MEM_EMPTY_CH0 (BIT(29))
-#define RMT_MEM_EMPTY_CH0_M  ((RMT_MEM_EMPTY_CH0_V)<<(RMT_MEM_EMPTY_CH0_S))
-#define RMT_MEM_EMPTY_CH0_V  0x1
-#define RMT_MEM_EMPTY_CH0_S  29
-/* RMT_MEM_FULL_CH0 : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The memory full status bit for channel0 turns to high level
- when mem_waddr_ex is greater than or equal to the configuration range.*/
-#define RMT_MEM_FULL_CH0 (BIT(28))
-#define RMT_MEM_FULL_CH0_M  ((RMT_MEM_FULL_CH0_V)<<(RMT_MEM_FULL_CH0_S))
-#define RMT_MEM_FULL_CH0_V  0x1
-#define RMT_MEM_FULL_CH0_S  28
-/* RMT_MEM_OWNER_ERR_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: When channel0 is configured for receive mode, this bit will turn to high level
- if rmt_mem_owner register is not set to 1.*/
-#define RMT_MEM_OWNER_ERR_CH0 (BIT(27))
-#define RMT_MEM_OWNER_ERR_CH0_M  ((RMT_MEM_OWNER_ERR_CH0_V)<<(RMT_MEM_OWNER_ERR_CH0_S))
-#define RMT_MEM_OWNER_ERR_CH0_V  0x1
-#define RMT_MEM_OWNER_ERR_CH0_S  27
-/* RMT_STATE_CH0 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: The channel0 state machine status register.
-3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
-#define RMT_STATE_CH0 0x07000000
-#define RMT_STATE_CH0_M  ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S))
-#define RMT_STATE_CH0_V  0x7
-#define RMT_STATE_CH0_S  24
-/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
-/*description: The current memory write address of channel0.*/
-#define RMT_MEM_RADDR_EX_CH0 0x003ff000
-#define RMT_MEM_RADDR_EX_CH0_M  ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S))
-#define RMT_MEM_RADDR_EX_CH0_V  0x3ff
-#define RMT_MEM_RADDR_EX_CH0_S  12
-/* RMT_MEM_WADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The current memory read address of channel0.*/
-#define RMT_MEM_WADDR_EX_CH0 0x000003ff
-#define RMT_MEM_WADDR_EX_CH0_M  ((RMT_MEM_WADDR_EX_CH0_V)<<(RMT_MEM_WADDR_EX_CH0_S))
-#define RMT_MEM_WADDR_EX_CH0_V  0x3ff
-#define RMT_MEM_WADDR_EX_CH0_S  0
-
-#define RMT_CH1STATUS_REG          (DR_REG_RMT_BASE + 0x0064)
-/* RMT_STATUS_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The status for channel1*/
-#define RMT_STATUS_CH1  0xFFFFFFFF
-#define RMT_STATUS_CH1_M  ((RMT_STATUS_CH1_V)<<(RMT_STATUS_CH1_S))
-#define RMT_STATUS_CH1_V  0xFFFFFFFF
-#define RMT_STATUS_CH1_S  0
-/* RMT_APB_MEM_RD_ERR_CH1 : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The apb read memory status bit for channel1 turns to
- high level when the apb read address exceeds the configuration range.*/
-#define RMT_APB_MEM_RD_ERR_CH1 (BIT(31))
-#define RMT_APB_MEM_RD_ERR_CH1_M  ((RMT_APB_MEM_RD_ERR_CH1_V)<<(RMT_APB_MEM_RD_ERR_CH1_S))
-#define RMT_APB_MEM_RD_ERR_CH1_V  0x1
-#define RMT_APB_MEM_RD_ERR_CH1_S  31
-/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The apb write memory status bit for channel1 turns to
- high level when the apb write address exceeds the configuration range.*/
-#define RMT_APB_MEM_WR_ERR_CH1 (BIT(30))
-#define RMT_APB_MEM_WR_ERR_CH1_M  ((RMT_APB_MEM_WR_ERR_CH1_V)<<(RMT_APB_MEM_WR_ERR_CH1_S))
-#define RMT_APB_MEM_WR_ERR_CH1_V  0x1
-#define RMT_APB_MEM_WR_ERR_CH1_S  30
-/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The memory empty status bit for channel1. in acyclic mode,
- this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
-#define RMT_MEM_EMPTY_CH1 (BIT(29))
-#define RMT_MEM_EMPTY_CH1_M  ((RMT_MEM_EMPTY_CH1_V)<<(RMT_MEM_EMPTY_CH1_S))
-#define RMT_MEM_EMPTY_CH1_V  0x1
-#define RMT_MEM_EMPTY_CH1_S  29
-/* RMT_MEM_FULL_CH1 : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The memory full status bit for channel1 turns to high level
- when mem_waddr_ex is greater than or equal to the configuration range.*/
-#define RMT_MEM_FULL_CH1 (BIT(28))
-#define RMT_MEM_FULL_CH1_M  ((RMT_MEM_FULL_CH1_V)<<(RMT_MEM_FULL_CH1_S))
-#define RMT_MEM_FULL_CH1_V  0x1
-#define RMT_MEM_FULL_CH1_S  28
-/* RMT_MEM_OWNER_ERR_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: When channel1 is configured for receive mode, this bit will turn to high level
- if rmt_mem_owner register is not set to 1.*/
-#define RMT_MEM_OWNER_ERR_CH1 (BIT(27))
-#define RMT_MEM_OWNER_ERR_CH1_M  ((RMT_MEM_OWNER_ERR_CH1_V)<<(RMT_MEM_OWNER_ERR_CH1_S))
-#define RMT_MEM_OWNER_ERR_CH1_V  0x1
-#define RMT_MEM_OWNER_ERR_CH1_S  27
-/* RMT_STATE_CH1 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: The channel1 state machine status register.
-3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
-#define RMT_STATE_CH1 0x07000000
-#define RMT_STATE_CH1_M  ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S))
-#define RMT_STATE_CH1_V  0x7
-#define RMT_STATE_CH1_S  24
-/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
-/*description: The current memory write address of channel1.*/
-#define RMT_MEM_RADDR_EX_CH1 0x003ff000
-#define RMT_MEM_RADDR_EX_CH1_M  ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S))
-#define RMT_MEM_RADDR_EX_CH1_V  0x3ff
-#define RMT_MEM_RADDR_EX_CH1_S  12
-/* RMT_MEM_WADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The current memory read address of channel1.*/
-#define RMT_MEM_WADDR_EX_CH1 0x000003ff
-#define RMT_MEM_WADDR_EX_CH1_M  ((RMT_MEM_WADDR_EX_CH1_V)<<(RMT_MEM_WADDR_EX_CH1_S))
-#define RMT_MEM_WADDR_EX_CH1_V  0x3ff
-#define RMT_MEM_WADDR_EX_CH1_S  0
-
-#define RMT_CH2STATUS_REG          (DR_REG_RMT_BASE + 0x0068)
-/* RMT_STATUS_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The status for channel2*/
-#define RMT_STATUS_CH2  0xFFFFFFFF
-#define RMT_STATUS_CH2_M  ((RMT_STATUS_CH2_V)<<(RMT_STATUS_CH2_S))
-#define RMT_STATUS_CH2_V  0xFFFFFFFF
-#define RMT_STATUS_CH2_S  0
-/* RMT_APB_MEM_RD_ERR_CH2 : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The apb read memory status bit for channel2 turns to
- high level when the apb read address exceeds the configuration range.*/
-#define RMT_APB_MEM_RD_ERR_CH2 (BIT(31))
-#define RMT_APB_MEM_RD_ERR_CH2_M  ((RMT_APB_MEM_RD_ERR_CH2_V)<<(RMT_APB_MEM_RD_ERR_CH2_S))
-#define RMT_APB_MEM_RD_ERR_CH2_V  0x1
-#define RMT_APB_MEM_RD_ERR_CH2_S  31
-/* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The apb write memory status bit for channel2 turns to
- high level when the apb write address exceeds the configuration range.*/
-#define RMT_APB_MEM_WR_ERR_CH2 (BIT(30))
-#define RMT_APB_MEM_WR_ERR_CH2_M  ((RMT_APB_MEM_WR_ERR_CH2_V)<<(RMT_APB_MEM_WR_ERR_CH2_S))
-#define RMT_APB_MEM_WR_ERR_CH2_V  0x1
-#define RMT_APB_MEM_WR_ERR_CH2_S  30
-/* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The memory empty status bit for channel2. in acyclic mode,
- this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
-#define RMT_MEM_EMPTY_CH2 (BIT(29))
-#define RMT_MEM_EMPTY_CH2_M  ((RMT_MEM_EMPTY_CH2_V)<<(RMT_MEM_EMPTY_CH2_S))
-#define RMT_MEM_EMPTY_CH2_V  0x1
-#define RMT_MEM_EMPTY_CH2_S  29
-/* RMT_MEM_FULL_CH2 : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The memory full status bit for channel2 turns to high level
- when mem_waddr_ex is greater than or equal to the configuration range.*/
-#define RMT_MEM_FULL_CH2 (BIT(28))
-#define RMT_MEM_FULL_CH2_M  ((RMT_MEM_FULL_CH2_V)<<(RMT_MEM_FULL_CH2_S))
-#define RMT_MEM_FULL_CH2_V  0x1
-#define RMT_MEM_FULL_CH2_S  28
-/* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: When channel2 is configured for receive mode, this bit will turn to high level
- if rmt_mem_owner register is not set to 1.*/
-#define RMT_MEM_OWNER_ERR_CH2 (BIT(27))
-#define RMT_MEM_OWNER_ERR_CH2_M  ((RMT_MEM_OWNER_ERR_CH2_V)<<(RMT_MEM_OWNER_ERR_CH2_S))
-#define RMT_MEM_OWNER_ERR_CH2_V  0x1
-#define RMT_MEM_OWNER_ERR_CH2_S  27
-/* RMT_STATE_CH2 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: The channel2 state machine status register.
-3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
-#define RMT_STATE_CH2 0x07000000
-#define RMT_STATE_CH2_M  ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S))
-#define RMT_STATE_CH2_V  0x7
-#define RMT_STATE_CH2_S  24
-/* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
-/*description: The current memory write address of channel2.*/
-#define RMT_MEM_RADDR_EX_CH2 0x003ff000
-#define RMT_MEM_RADDR_EX_CH2_M  ((RMT_MEM_RADDR_EX_CH2_V)<<(RMT_MEM_RADDR_EX_CH2_S))
-#define RMT_MEM_RADDR_EX_CH2_V  0x3ff
-#define RMT_MEM_RADDR_EX_CH2_S  12
-/* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The current memory read address of channel2.*/
-#define RMT_MEM_WADDR_EX_CH2 0x000003ff
-#define RMT_MEM_WADDR_EX_CH2_M  ((RMT_MEM_WADDR_EX_CH2_V)<<(RMT_MEM_WADDR_EX_CH2_S))
-#define RMT_MEM_WADDR_EX_CH2_V  0x3ff
-#define RMT_MEM_WADDR_EX_CH2_S  0
-
-#define RMT_CH3STATUS_REG          (DR_REG_RMT_BASE + 0x006c)
-/* RMT_STATUS_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The status for channel3*/
-#define RMT_STATUS_CH3  0xFFFFFFFF
-#define RMT_STATUS_CH3_M  ((RMT_STATUS_CH3_V)<<(RMT_STATUS_CH3_S))
-#define RMT_STATUS_CH3_V  0xFFFFFFFF
-#define RMT_STATUS_CH3_S  0
-/* RMT_APB_MEM_RD_ERR_CH3 : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The apb read memory status bit for channel3 turns to
- high level when the apb read address exceeds the configuration range.*/
-#define RMT_APB_MEM_RD_ERR_CH3 (BIT(31))
-#define RMT_APB_MEM_RD_ERR_CH3_M  ((RMT_APB_MEM_RD_ERR_CH3_V)<<(RMT_APB_MEM_RD_ERR_CH3_S))
-#define RMT_APB_MEM_RD_ERR_CH3_V  0x1
-#define RMT_APB_MEM_RD_ERR_CH3_S  31
-/* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The apb write memory status bit for channel3 turns to
- high level when the apb write address exceeds the configuration range.*/
-#define RMT_APB_MEM_WR_ERR_CH3 (BIT(30))
-#define RMT_APB_MEM_WR_ERR_CH3_M  ((RMT_APB_MEM_WR_ERR_CH3_V)<<(RMT_APB_MEM_WR_ERR_CH3_S))
-#define RMT_APB_MEM_WR_ERR_CH3_V  0x1
-#define RMT_APB_MEM_WR_ERR_CH3_S  30
-/* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The memory empty status bit for channel3. in acyclic mode,
- this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
-#define RMT_MEM_EMPTY_CH3 (BIT(29))
-#define RMT_MEM_EMPTY_CH3_M  ((RMT_MEM_EMPTY_CH3_V)<<(RMT_MEM_EMPTY_CH3_S))
-#define RMT_MEM_EMPTY_CH3_V  0x1
-#define RMT_MEM_EMPTY_CH3_S  29
-/* RMT_MEM_FULL_CH3 : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The memory full status bit for channel3 turns to high level
- when mem_waddr_ex is greater than or equal to the configuration range.*/
-#define RMT_MEM_FULL_CH3 (BIT(28))
-#define RMT_MEM_FULL_CH3_M  ((RMT_MEM_FULL_CH3_V)<<(RMT_MEM_FULL_CH3_S))
-#define RMT_MEM_FULL_CH3_V  0x1
-#define RMT_MEM_FULL_CH3_S  28
-/* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: When channel3 is configured for receive mode, this bit will turn to high level
- if rmt_mem_owner register is not set to 1.*/
-#define RMT_MEM_OWNER_ERR_CH3 (BIT(27))
-#define RMT_MEM_OWNER_ERR_CH3_M  ((RMT_MEM_OWNER_ERR_CH3_V)<<(RMT_MEM_OWNER_ERR_CH3_S))
-#define RMT_MEM_OWNER_ERR_CH3_V  0x1
-#define RMT_MEM_OWNER_ERR_CH3_S  27
-/* RMT_STATE_CH3 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: The channel3 state machine status register.
-3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
-#define RMT_STATE_CH3 0x07000000
-#define RMT_STATE_CH3_M  ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S))
-#define RMT_STATE_CH3_V  0x7
-#define RMT_STATE_CH3_S  24
-/* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
-/*description: The current memory write address of channel3.*/
-#define RMT_MEM_RADDR_EX_CH3 0x003ff000
-#define RMT_MEM_RADDR_EX_CH3_M  ((RMT_MEM_RADDR_EX_CH3_V)<<(RMT_MEM_RADDR_EX_CH3_S))
-#define RMT_MEM_RADDR_EX_CH3_V  0x3ff
-#define RMT_MEM_RADDR_EX_CH3_S  12
-/* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The current memory read address of channel3.*/
-#define RMT_MEM_WADDR_EX_CH3 0x000003ff
-#define RMT_MEM_WADDR_EX_CH3_M  ((RMT_MEM_WADDR_EX_CH3_V)<<(RMT_MEM_WADDR_EX_CH3_S))
-#define RMT_MEM_WADDR_EX_CH3_V  0x3ff
-#define RMT_MEM_WADDR_EX_CH3_S  0
-
-#define RMT_CH4STATUS_REG          (DR_REG_RMT_BASE + 0x0070)
-/* RMT_STATUS_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The status for channel4*/
-#define RMT_STATUS_CH4  0xFFFFFFFF
-#define RMT_STATUS_CH4_M  ((RMT_STATUS_CH4_V)<<(RMT_STATUS_CH4_S))
-#define RMT_STATUS_CH4_V  0xFFFFFFFF
-#define RMT_STATUS_CH4_S  0
-/* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The apb read memory status bit for channel4 turns to
- high level when the apb read address exceeds the configuration range.*/
-#define RMT_APB_MEM_RD_ERR_CH4 (BIT(31))
-#define RMT_APB_MEM_RD_ERR_CH4_M  ((RMT_APB_MEM_RD_ERR_CH4_V)<<(RMT_APB_MEM_RD_ERR_CH4_S))
-#define RMT_APB_MEM_RD_ERR_CH4_V  0x1
-#define RMT_APB_MEM_RD_ERR_CH4_S  31
-/* RMT_APB_MEM_WR_ERR_CH4 : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The apb write memory status bit for channel4 turns to
- high level when the apb write address exceeds the configuration range.*/
-#define RMT_APB_MEM_WR_ERR_CH4 (BIT(30))
-#define RMT_APB_MEM_WR_ERR_CH4_M  ((RMT_APB_MEM_WR_ERR_CH4_V)<<(RMT_APB_MEM_WR_ERR_CH4_S))
-#define RMT_APB_MEM_WR_ERR_CH4_V  0x1
-#define RMT_APB_MEM_WR_ERR_CH4_S  30
-/* RMT_MEM_EMPTY_CH4 : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The memory empty status bit for channel4. in acyclic mode,
- this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
-#define RMT_MEM_EMPTY_CH4 (BIT(29))
-#define RMT_MEM_EMPTY_CH4_M  ((RMT_MEM_EMPTY_CH4_V)<<(RMT_MEM_EMPTY_CH4_S))
-#define RMT_MEM_EMPTY_CH4_V  0x1
-#define RMT_MEM_EMPTY_CH4_S  29
-/* RMT_MEM_FULL_CH4 : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The memory full status bit for channel4 turns to high level
- when mem_waddr_ex is greater than or equal to the configuration range.*/
-#define RMT_MEM_FULL_CH4 (BIT(28))
-#define RMT_MEM_FULL_CH4_M  ((RMT_MEM_FULL_CH4_V)<<(RMT_MEM_FULL_CH4_S))
-#define RMT_MEM_FULL_CH4_V  0x1
-#define RMT_MEM_FULL_CH4_S  28
-/* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: When channel4 is configured for receive mode, this bit will turn to high level
- if rmt_mem_owner register is not set to 1.*/
-#define RMT_MEM_OWNER_ERR_CH4 (BIT(27))
-#define RMT_MEM_OWNER_ERR_CH4_M  ((RMT_MEM_OWNER_ERR_CH4_V)<<(RMT_MEM_OWNER_ERR_CH4_S))
-#define RMT_MEM_OWNER_ERR_CH4_V  0x1
-#define RMT_MEM_OWNER_ERR_CH4_S  27
-/* RMT_STATE_CH4 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: The channel4 state machine status register.
-3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
-#define RMT_STATE_CH4 0x07000000
-#define RMT_STATE_CH4_M  ((RMT_STATE_CH4_V)<<(RMT_STATE_CH4_S))
-#define RMT_STATE_CH4_V  0x7
-#define RMT_STATE_CH4_S  24
-/* RMT_MEM_RADDR_EX_CH4 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
-/*description: The current memory write address of channel4.*/
-#define RMT_MEM_RADDR_EX_CH4 0x003ff000
-#define RMT_MEM_RADDR_EX_CH4_M  ((RMT_MEM_RADDR_EX_CH4_V)<<(RMT_MEM_RADDR_EX_CH4_S))
-#define RMT_MEM_RADDR_EX_CH4_V  0x3ff
-#define RMT_MEM_RADDR_EX_CH4_S  12
-/* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The current memory read address of channel4.*/
-#define RMT_MEM_WADDR_EX_CH4 0x000003ff
-#define RMT_MEM_WADDR_EX_CH4_M  ((RMT_MEM_WADDR_EX_CH4_V)<<(RMT_MEM_WADDR_EX_CH4_S))
-#define RMT_MEM_WADDR_EX_CH4_V  0x3ff
-#define RMT_MEM_WADDR_EX_CH4_S  0
-
-#define RMT_CH5STATUS_REG          (DR_REG_RMT_BASE + 0x0074)
-/* RMT_STATUS_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The status for channel5*/
-#define RMT_STATUS_CH5  0xFFFFFFFF
-#define RMT_STATUS_CH5_M  ((RMT_STATUS_CH5_V)<<(RMT_STATUS_CH5_S))
-#define RMT_STATUS_CH5_V  0xFFFFFFFF
-#define RMT_STATUS_CH5_S  0
-/* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The apb read memory status bit for channel5 turns to
- high level when the apb read address exceeds the configuration range.*/
-#define RMT_APB_MEM_RD_ERR_CH5 (BIT(31))
-#define RMT_APB_MEM_RD_ERR_CH5_M  ((RMT_APB_MEM_RD_ERR_CH5_V)<<(RMT_APB_MEM_RD_ERR_CH5_S))
-#define RMT_APB_MEM_RD_ERR_CH5_V  0x1
-#define RMT_APB_MEM_RD_ERR_CH5_S  31
-/* RMT_APB_MEM_WR_ERR_CH5 : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The apb write memory status bit for channel5 turns to
- high level when the apb write address exceeds the configuration range.*/
-#define RMT_APB_MEM_WR_ERR_CH5 (BIT(30))
-#define RMT_APB_MEM_WR_ERR_CH5_M  ((RMT_APB_MEM_WR_ERR_CH5_V)<<(RMT_APB_MEM_WR_ERR_CH5_S))
-#define RMT_APB_MEM_WR_ERR_CH5_V  0x1
-#define RMT_APB_MEM_WR_ERR_CH5_S  30
-/* RMT_MEM_EMPTY_CH5 : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The memory empty status bit for channel5. in acyclic mode,
- this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
-#define RMT_MEM_EMPTY_CH5 (BIT(29))
-#define RMT_MEM_EMPTY_CH5_M  ((RMT_MEM_EMPTY_CH5_V)<<(RMT_MEM_EMPTY_CH5_S))
-#define RMT_MEM_EMPTY_CH5_V  0x1
-#define RMT_MEM_EMPTY_CH5_S  29
-/* RMT_MEM_FULL_CH5 : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The memory full status bit for channel5 turns to high level
- when mem_waddr_ex is greater than or equal to the configuration range.*/
-#define RMT_MEM_FULL_CH5 (BIT(28))
-#define RMT_MEM_FULL_CH5_M  ((RMT_MEM_FULL_CH5_V)<<(RMT_MEM_FULL_CH5_S))
-#define RMT_MEM_FULL_CH5_V  0x1
-#define RMT_MEM_FULL_CH5_S  28
-/* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: When channel5 is configured for receive mode, this bit will turn to high level
- if rmt_mem_owner register is not set to 1.*/
-#define RMT_MEM_OWNER_ERR_CH5 (BIT(27))
-#define RMT_MEM_OWNER_ERR_CH5_M  ((RMT_MEM_OWNER_ERR_CH5_V)<<(RMT_MEM_OWNER_ERR_CH5_S))
-#define RMT_MEM_OWNER_ERR_CH5_V  0x1
-#define RMT_MEM_OWNER_ERR_CH5_S  27
-/* RMT_STATE_CH5 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: The channel5 state machine status register.
-3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
-#define RMT_STATE_CH5 0x07000000
-#define RMT_STATE_CH5_M  ((RMT_STATE_CH5_V)<<(RMT_STATE_CH5_S))
-#define RMT_STATE_CH5_V  0x7
-#define RMT_STATE_CH5_S  24
-/* RMT_MEM_RADDR_EX_CH5 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
-/*description: The current memory write address of channel5.*/
-#define RMT_MEM_RADDR_EX_CH5 0x003ff000
-#define RMT_MEM_RADDR_EX_CH5_M  ((RMT_MEM_RADDR_EX_CH5_V)<<(RMT_MEM_RADDR_EX_CH5_S))
-#define RMT_MEM_RADDR_EX_CH5_V  0x3ff
-#define RMT_MEM_RADDR_EX_CH5_S  12
-/* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The current memory read address of channel5.*/
-#define RMT_MEM_WADDR_EX_CH5 0x000003ff
-#define RMT_MEM_WADDR_EX_CH5_M  ((RMT_MEM_WADDR_EX_CH5_V)<<(RMT_MEM_WADDR_EX_CH5_S))
-#define RMT_MEM_WADDR_EX_CH5_V  0x3ff
-#define RMT_MEM_WADDR_EX_CH5_S  0
-
-#define RMT_CH6STATUS_REG          (DR_REG_RMT_BASE + 0x0078)
-/* RMT_STATUS_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The status for channel6*/
-#define RMT_STATUS_CH6  0xFFFFFFFF
-#define RMT_STATUS_CH6_M  ((RMT_STATUS_CH6_V)<<(RMT_STATUS_CH6_S))
-#define RMT_STATUS_CH6_V  0xFFFFFFFF
-#define RMT_STATUS_CH6_S  0
-/* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The apb read memory status bit for channel6 turns to
- high level when the apb read address exceeds the configuration range.*/
-#define RMT_APB_MEM_RD_ERR_CH6 (BIT(31))
-#define RMT_APB_MEM_RD_ERR_CH6_M  ((RMT_APB_MEM_RD_ERR_CH6_V)<<(RMT_APB_MEM_RD_ERR_CH6_S))
-#define RMT_APB_MEM_RD_ERR_CH6_V  0x1
-#define RMT_APB_MEM_RD_ERR_CH6_S  31
-/* RMT_APB_MEM_WR_ERR_CH6 : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The apb write memory status bit for channel6 turns to
- high level when the apb write address exceeds the configuration range.*/
-#define RMT_APB_MEM_WR_ERR_CH6 (BIT(30))
-#define RMT_APB_MEM_WR_ERR_CH6_M  ((RMT_APB_MEM_WR_ERR_CH6_V)<<(RMT_APB_MEM_WR_ERR_CH6_S))
-#define RMT_APB_MEM_WR_ERR_CH6_V  0x1
-#define RMT_APB_MEM_WR_ERR_CH6_S  30
-/* RMT_MEM_EMPTY_CH6 : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The memory empty status bit for channel6. in acyclic mode,
- this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
-#define RMT_MEM_EMPTY_CH6 (BIT(29))
-#define RMT_MEM_EMPTY_CH6_M  ((RMT_MEM_EMPTY_CH6_V)<<(RMT_MEM_EMPTY_CH6_S))
-#define RMT_MEM_EMPTY_CH6_V  0x1
-#define RMT_MEM_EMPTY_CH6_S  29
-/* RMT_MEM_FULL_CH6 : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The memory full status bit for channel6 turns to high level
- when mem_waddr_ex is greater than or equal to the configuration range.*/
-#define RMT_MEM_FULL_CH6 (BIT(28))
-#define RMT_MEM_FULL_CH6_M  ((RMT_MEM_FULL_CH6_V)<<(RMT_MEM_FULL_CH6_S))
-#define RMT_MEM_FULL_CH6_V  0x1
-#define RMT_MEM_FULL_CH6_S  28
-/* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: When channel6 is configured for receive mode, this bit will turn to high level
- if rmt_mem_owner register is not set to 1.*/
-#define RMT_MEM_OWNER_ERR_CH6 (BIT(27))
-#define RMT_MEM_OWNER_ERR_CH6_M  ((RMT_MEM_OWNER_ERR_CH6_V)<<(RMT_MEM_OWNER_ERR_CH6_S))
-#define RMT_MEM_OWNER_ERR_CH6_V  0x1
-#define RMT_MEM_OWNER_ERR_CH6_S  27
-/* RMT_STATE_CH6 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: The channel6 state machine status register.
-3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
-#define RMT_STATE_CH6 0x07000000
-#define RMT_STATE_CH6_M  ((RMT_STATE_CH6_V)<<(RMT_STATE_CH6_S))
-#define RMT_STATE_CH6_V  0x7
-#define RMT_STATE_CH6_S  24
-/* RMT_MEM_RADDR_EX_CH6 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
-/*description: The current memory write address of channel6.*/
-#define RMT_MEM_RADDR_EX_CH6 0x003ff000
-#define RMT_MEM_RADDR_EX_CH6_M  ((RMT_MEM_RADDR_EX_CH6_V)<<(RMT_MEM_RADDR_EX_CH6_S))
-#define RMT_MEM_RADDR_EX_CH6_V  0x3ff
-#define RMT_MEM_RADDR_EX_CH6_S  12
-/* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The current memory read address of channel6.*/
-#define RMT_MEM_WADDR_EX_CH6 0x000003ff
-#define RMT_MEM_WADDR_EX_CH6_M  ((RMT_MEM_WADDR_EX_CH6_V)<<(RMT_MEM_WADDR_EX_CH6_S))
-#define RMT_MEM_WADDR_EX_CH6_V  0x3ff
-#define RMT_MEM_WADDR_EX_CH6_S  0
-
-#define RMT_CH7STATUS_REG          (DR_REG_RMT_BASE + 0x007c)
-/* RMT_STATUS_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The status for channel7*/
-#define RMT_STATUS_CH7  0xFFFFFFFF
-#define RMT_STATUS_CH7_M  ((RMT_STATUS_CH7_V)<<(RMT_STATUS_CH7_S))
-#define RMT_STATUS_CH7_V  0xFFFFFFFF
-#define RMT_STATUS_CH7_S  0
-/* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The apb read memory status bit for channel7 turns to
- high level when the apb read address exceeds the configuration range.*/
-#define RMT_APB_MEM_RD_ERR_CH7 (BIT(31))
-#define RMT_APB_MEM_RD_ERR_CH7_M  ((RMT_APB_MEM_RD_ERR_CH7_V)<<(RMT_APB_MEM_RD_ERR_CH7_S))
-#define RMT_APB_MEM_RD_ERR_CH7_V  0x1
-#define RMT_APB_MEM_RD_ERR_CH7_S  31
-/* RMT_APB_MEM_WR_ERR_CH7 : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The apb write memory status bit for channel7 turns to
- high level when the apb write address exceeds the configuration range.*/
-#define RMT_APB_MEM_WR_ERR_CH7 (BIT(30))
-#define RMT_APB_MEM_WR_ERR_CH7_M  ((RMT_APB_MEM_WR_ERR_CH7_V)<<(RMT_APB_MEM_WR_ERR_CH7_S))
-#define RMT_APB_MEM_WR_ERR_CH7_V  0x1
-#define RMT_APB_MEM_WR_ERR_CH7_S  30
-/* RMT_MEM_EMPTY_CH7 : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The memory empty status bit for channel7. in acyclic mode,
- this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.*/
-#define RMT_MEM_EMPTY_CH7 (BIT(29))
-#define RMT_MEM_EMPTY_CH7_M  ((RMT_MEM_EMPTY_CH7_V)<<(RMT_MEM_EMPTY_CH7_S))
-#define RMT_MEM_EMPTY_CH7_V  0x1
-#define RMT_MEM_EMPTY_CH7_S  29
-/* RMT_MEM_FULL_CH7 : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The memory full status bit for channel7 turns to high level
- when mem_waddr_ex is greater than or equal to the configuration range.*/
-#define RMT_MEM_FULL_CH7 (BIT(28))
-#define RMT_MEM_FULL_CH7_M  ((RMT_MEM_FULL_CH7_V)<<(RMT_MEM_FULL_CH7_S))
-#define RMT_MEM_FULL_CH7_V  0x1
-#define RMT_MEM_FULL_CH7_S  28
-/* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: When channel7 is configured for receive mode, this bit will turn to high level
- if rmt_mem_owner register is not set to 1.*/
-#define RMT_MEM_OWNER_ERR_CH7 (BIT(27))
-#define RMT_MEM_OWNER_ERR_CH7_M  ((RMT_MEM_OWNER_ERR_CH7_V)<<(RMT_MEM_OWNER_ERR_CH7_S))
-#define RMT_MEM_OWNER_ERR_CH7_V  0x1
-#define RMT_MEM_OWNER_ERR_CH7_S  27
-/* RMT_STATE_CH7 : RO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: The channel7 state machine status register.
-3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait.*/
-#define RMT_STATE_CH7 0x07000000
-#define RMT_STATE_CH7_M  ((RMT_STATE_CH7_V)<<(RMT_STATE_CH7_S))
-#define RMT_STATE_CH7_V  0x7
-#define RMT_STATE_CH7_S  24
-/* RMT_MEM_RADDR_EX_CH7 : RO ;bitpos:[21:12] ;default: 10'h0 ; */
-/*description: The current memory write address of channel7.*/
-#define RMT_MEM_RADDR_EX_CH7 0x003ff000
-#define RMT_MEM_RADDR_EX_CH7_M  ((RMT_MEM_RADDR_EX_CH7_V)<<(RMT_MEM_RADDR_EX_CH7_S))
-#define RMT_MEM_RADDR_EX_CH7_V  0x3ff
-#define RMT_MEM_RADDR_EX_CH7_S  12
-/* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The current memory read address of channel7.*/
-#define RMT_MEM_WADDR_EX_CH7 0x000003ff
-#define RMT_MEM_WADDR_EX_CH7_M  ((RMT_MEM_WADDR_EX_CH7_V)<<(RMT_MEM_WADDR_EX_CH7_S))
-#define RMT_MEM_WADDR_EX_CH7_V  0x3ff
-#define RMT_MEM_WADDR_EX_CH7_S  0
-
-#define RMT_CH0ADDR_REG          (DR_REG_RMT_BASE + 0x0080)
-/* RMT_APB_MEM_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The ram relative address in channel0 by apb fifo access*/
-#define RMT_APB_MEM_ADDR_CH0  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH0_M  ((RMT_APB_MEM_ADDR_CH0_V)<<(RMT_APB_MEM_ADDR_CH0_S))
-#define RMT_APB_MEM_ADDR_CH0_V  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH0_S  0
-
-#define RMT_CH1ADDR_REG          (DR_REG_RMT_BASE + 0x0084)
-/* RMT_APB_MEM_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The ram relative address in channel1 by apb fifo access*/
-#define RMT_APB_MEM_ADDR_CH1  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH1_M  ((RMT_APB_MEM_ADDR_CH1_V)<<(RMT_APB_MEM_ADDR_CH1_S))
-#define RMT_APB_MEM_ADDR_CH1_V  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH1_S  0
-
-#define RMT_CH2ADDR_REG          (DR_REG_RMT_BASE + 0x0088)
-/* RMT_APB_MEM_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The ram relative address in channel2 by apb fifo access*/
-#define RMT_APB_MEM_ADDR_CH2  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH2_M  ((RMT_APB_MEM_ADDR_CH2_V)<<(RMT_APB_MEM_ADDR_CH2_S))
-#define RMT_APB_MEM_ADDR_CH2_V  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH2_S  0
-
-#define RMT_CH3ADDR_REG          (DR_REG_RMT_BASE + 0x008c)
-/* RMT_APB_MEM_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The ram relative address in channel3 by apb fifo access*/
-#define RMT_APB_MEM_ADDR_CH3  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH3_M  ((RMT_APB_MEM_ADDR_CH3_V)<<(RMT_APB_MEM_ADDR_CH3_S))
-#define RMT_APB_MEM_ADDR_CH3_V  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH3_S  0
-
-#define RMT_CH4ADDR_REG          (DR_REG_RMT_BASE + 0x0090)
-/* RMT_APB_MEM_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The ram relative address in channel4 by apb fifo access*/
-#define RMT_APB_MEM_ADDR_CH4  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH4_M  ((RMT_APB_MEM_ADDR_CH4_V)<<(RMT_APB_MEM_ADDR_CH4_S))
-#define RMT_APB_MEM_ADDR_CH4_V  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH4_S  0
-
-#define RMT_CH5ADDR_REG          (DR_REG_RMT_BASE + 0x0094)
-/* RMT_APB_MEM_ADDR_CH5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The ram relative address in channel5 by apb fifo access*/
-#define RMT_APB_MEM_ADDR_CH5  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH5_M  ((RMT_APB_MEM_ADDR_CH5_V)<<(RMT_APB_MEM_ADDR_CH5_S))
-#define RMT_APB_MEM_ADDR_CH5_V  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH5_S  0
-
-#define RMT_CH6ADDR_REG          (DR_REG_RMT_BASE + 0x0098)
-/* RMT_APB_MEM_ADDR_CH6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The ram relative address in channel6 by apb fifo access*/
-#define RMT_APB_MEM_ADDR_CH6  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH6_M  ((RMT_APB_MEM_ADDR_CH6_V)<<(RMT_APB_MEM_ADDR_CH6_S))
-#define RMT_APB_MEM_ADDR_CH6_V  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH6_S  0
-
-#define RMT_CH7ADDR_REG          (DR_REG_RMT_BASE + 0x009c)
-/* RMT_APB_MEM_ADDR_CH7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The ram relative address in channel7 by apb fifo access*/
-#define RMT_APB_MEM_ADDR_CH7  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH7_M  ((RMT_APB_MEM_ADDR_CH7_V)<<(RMT_APB_MEM_ADDR_CH7_S))
-#define RMT_APB_MEM_ADDR_CH7_V  0xFFFFFFFF
-#define RMT_APB_MEM_ADDR_CH7_S  0
-
-#define RMT_INT_RAW_REG          (DR_REG_RMT_BASE + 0x00a0)
-/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel7 turns to high level when
- transmitter in channle 7  have send datas more than  reg_rmt_tx_lim_ch7  after detecting this interrupt  software can updata the old datas with new datas.*/
-#define RMT_CH7_TX_THR_EVENT_INT_RAW  (BIT(31))
-#define RMT_CH7_TX_THR_EVENT_INT_RAW_M  (BIT(31))
-#define RMT_CH7_TX_THR_EVENT_INT_RAW_V  0x1
-#define RMT_CH7_TX_THR_EVENT_INT_RAW_S  31
-/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 6 turns to high level when
- transmitter in channle6  have send datas more than  reg_rmt_tx_lim_ch6  after detecting this interrupt  software can updata the old datas with new datas.*/
-#define RMT_CH6_TX_THR_EVENT_INT_RAW  (BIT(30))
-#define RMT_CH6_TX_THR_EVENT_INT_RAW_M  (BIT(30))
-#define RMT_CH6_TX_THR_EVENT_INT_RAW_V  0x1
-#define RMT_CH6_TX_THR_EVENT_INT_RAW_S  30
-/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 5 turns to high level when
- transmitter in channle5  have send datas more than  reg_rmt_tx_lim_ch5  after detecting this interrupt  software can updata the old datas with new datas.*/
-#define RMT_CH5_TX_THR_EVENT_INT_RAW  (BIT(29))
-#define RMT_CH5_TX_THR_EVENT_INT_RAW_M  (BIT(29))
-#define RMT_CH5_TX_THR_EVENT_INT_RAW_V  0x1
-#define RMT_CH5_TX_THR_EVENT_INT_RAW_S  29
-/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 4 turns to high level when
- transmitter in channle4  have send datas more than  reg_rmt_tx_lim_ch4  after detecting this interrupt  software can updata the old datas with new datas.*/
-#define RMT_CH4_TX_THR_EVENT_INT_RAW  (BIT(28))
-#define RMT_CH4_TX_THR_EVENT_INT_RAW_M  (BIT(28))
-#define RMT_CH4_TX_THR_EVENT_INT_RAW_V  0x1
-#define RMT_CH4_TX_THR_EVENT_INT_RAW_S  28
-/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 3 turns to high level when
- transmitter in channle3  have send datas more than  reg_rmt_tx_lim_ch3  after detecting this interrupt  software can updata the old datas with new datas.*/
-#define RMT_CH3_TX_THR_EVENT_INT_RAW  (BIT(27))
-#define RMT_CH3_TX_THR_EVENT_INT_RAW_M  (BIT(27))
-#define RMT_CH3_TX_THR_EVENT_INT_RAW_V  0x1
-#define RMT_CH3_TX_THR_EVENT_INT_RAW_S  27
-/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 2 turns to high level when
- transmitter in channle2  have send datas more than  reg_rmt_tx_lim_ch2  after detecting this interrupt  software can updata the old datas with new datas.*/
-#define RMT_CH2_TX_THR_EVENT_INT_RAW  (BIT(26))
-#define RMT_CH2_TX_THR_EVENT_INT_RAW_M  (BIT(26))
-#define RMT_CH2_TX_THR_EVENT_INT_RAW_V  0x1
-#define RMT_CH2_TX_THR_EVENT_INT_RAW_S  26
-/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 1 turns to high level when
- transmitter in channle1  have send datas more than  reg_rmt_tx_lim_ch1  after detecting this interrupt  software can updata the old datas with new datas.*/
-#define RMT_CH1_TX_THR_EVENT_INT_RAW  (BIT(25))
-#define RMT_CH1_TX_THR_EVENT_INT_RAW_M  (BIT(25))
-#define RMT_CH1_TX_THR_EVENT_INT_RAW_V  0x1
-#define RMT_CH1_TX_THR_EVENT_INT_RAW_S  25
-/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 0 turns to high level when
- transmitter in channle0  have send datas more than  reg_rmt_tx_lim_ch0  after detecting this interrupt  software can updata the old datas with new datas.*/
-#define RMT_CH0_TX_THR_EVENT_INT_RAW  (BIT(24))
-#define RMT_CH0_TX_THR_EVENT_INT_RAW_M  (BIT(24))
-#define RMT_CH0_TX_THR_EVENT_INT_RAW_V  0x1
-#define RMT_CH0_TX_THR_EVENT_INT_RAW_S  24
-/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 7 turns to high level when
- channle 7 detects some errors.*/
-#define RMT_CH7_ERR_INT_RAW  (BIT(23))
-#define RMT_CH7_ERR_INT_RAW_M  (BIT(23))
-#define RMT_CH7_ERR_INT_RAW_V  0x1
-#define RMT_CH7_ERR_INT_RAW_S  23
-/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 7 turns to high level when
- the receive process is done.*/
-#define RMT_CH7_RX_END_INT_RAW  (BIT(22))
-#define RMT_CH7_RX_END_INT_RAW_M  (BIT(22))
-#define RMT_CH7_RX_END_INT_RAW_V  0x1
-#define RMT_CH7_RX_END_INT_RAW_S  22
-/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 7 turns to high level when
- the transmit process is done.*/
-#define RMT_CH7_TX_END_INT_RAW  (BIT(21))
-#define RMT_CH7_TX_END_INT_RAW_M  (BIT(21))
-#define RMT_CH7_TX_END_INT_RAW_V  0x1
-#define RMT_CH7_TX_END_INT_RAW_S  21
-/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 6 turns to high level when
- channle 6 detects some errors.*/
-#define RMT_CH6_ERR_INT_RAW  (BIT(20))
-#define RMT_CH6_ERR_INT_RAW_M  (BIT(20))
-#define RMT_CH6_ERR_INT_RAW_V  0x1
-#define RMT_CH6_ERR_INT_RAW_S  20
-/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 6 turns to high level when
- the receive process is done.*/
-#define RMT_CH6_RX_END_INT_RAW  (BIT(19))
-#define RMT_CH6_RX_END_INT_RAW_M  (BIT(19))
-#define RMT_CH6_RX_END_INT_RAW_V  0x1
-#define RMT_CH6_RX_END_INT_RAW_S  19
-/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 6 turns to high level when
- the transmit process is done.*/
-#define RMT_CH6_TX_END_INT_RAW  (BIT(18))
-#define RMT_CH6_TX_END_INT_RAW_M  (BIT(18))
-#define RMT_CH6_TX_END_INT_RAW_V  0x1
-#define RMT_CH6_TX_END_INT_RAW_S  18
-/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 5 turns to high level when
- channle 5 detects some errors.*/
-#define RMT_CH5_ERR_INT_RAW  (BIT(17))
-#define RMT_CH5_ERR_INT_RAW_M  (BIT(17))
-#define RMT_CH5_ERR_INT_RAW_V  0x1
-#define RMT_CH5_ERR_INT_RAW_S  17
-/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 5 turns to high level when
- the receive process is done.*/
-#define RMT_CH5_RX_END_INT_RAW  (BIT(16))
-#define RMT_CH5_RX_END_INT_RAW_M  (BIT(16))
-#define RMT_CH5_RX_END_INT_RAW_V  0x1
-#define RMT_CH5_RX_END_INT_RAW_S  16
-/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 5 turns to high level when
- the transmit process is done.*/
-#define RMT_CH5_TX_END_INT_RAW  (BIT(15))
-#define RMT_CH5_TX_END_INT_RAW_M  (BIT(15))
-#define RMT_CH5_TX_END_INT_RAW_V  0x1
-#define RMT_CH5_TX_END_INT_RAW_S  15
-/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 4 turns to high level when
- channle 4 detects some errors.*/
-#define RMT_CH4_ERR_INT_RAW  (BIT(14))
-#define RMT_CH4_ERR_INT_RAW_M  (BIT(14))
-#define RMT_CH4_ERR_INT_RAW_V  0x1
-#define RMT_CH4_ERR_INT_RAW_S  14
-/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 4 turns to high level when
- the receive process is done.*/
-#define RMT_CH4_RX_END_INT_RAW  (BIT(13))
-#define RMT_CH4_RX_END_INT_RAW_M  (BIT(13))
-#define RMT_CH4_RX_END_INT_RAW_V  0x1
-#define RMT_CH4_RX_END_INT_RAW_S  13
-/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 4 turns to high level when
- the transmit process is done.*/
-#define RMT_CH4_TX_END_INT_RAW  (BIT(12))
-#define RMT_CH4_TX_END_INT_RAW_M  (BIT(12))
-#define RMT_CH4_TX_END_INT_RAW_V  0x1
-#define RMT_CH4_TX_END_INT_RAW_S  12
-/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 3 turns to high level when
- channle 3 detects some errors.*/
-#define RMT_CH3_ERR_INT_RAW  (BIT(11))
-#define RMT_CH3_ERR_INT_RAW_M  (BIT(11))
-#define RMT_CH3_ERR_INT_RAW_V  0x1
-#define RMT_CH3_ERR_INT_RAW_S  11
-/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 3 turns to high level when
- the receive process is done.*/
-#define RMT_CH3_RX_END_INT_RAW  (BIT(10))
-#define RMT_CH3_RX_END_INT_RAW_M  (BIT(10))
-#define RMT_CH3_RX_END_INT_RAW_V  0x1
-#define RMT_CH3_RX_END_INT_RAW_S  10
-/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 3 turns to high level when
- the transmit process is done.*/
-#define RMT_CH3_TX_END_INT_RAW  (BIT(9))
-#define RMT_CH3_TX_END_INT_RAW_M  (BIT(9))
-#define RMT_CH3_TX_END_INT_RAW_V  0x1
-#define RMT_CH3_TX_END_INT_RAW_S  9
-/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 2 turns to high level when
- channle 2 detects some errors.*/
-#define RMT_CH2_ERR_INT_RAW  (BIT(8))
-#define RMT_CH2_ERR_INT_RAW_M  (BIT(8))
-#define RMT_CH2_ERR_INT_RAW_V  0x1
-#define RMT_CH2_ERR_INT_RAW_S  8
-/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 2 turns to high level when
- the receive process is done.*/
-#define RMT_CH2_RX_END_INT_RAW  (BIT(7))
-#define RMT_CH2_RX_END_INT_RAW_M  (BIT(7))
-#define RMT_CH2_RX_END_INT_RAW_V  0x1
-#define RMT_CH2_RX_END_INT_RAW_S  7
-/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 2 turns to high level when
- the transmit process is done.*/
-#define RMT_CH2_TX_END_INT_RAW  (BIT(6))
-#define RMT_CH2_TX_END_INT_RAW_M  (BIT(6))
-#define RMT_CH2_TX_END_INT_RAW_V  0x1
-#define RMT_CH2_TX_END_INT_RAW_S  6
-/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 1 turns to high level when
- channle 1 detects some errors.*/
-#define RMT_CH1_ERR_INT_RAW  (BIT(5))
-#define RMT_CH1_ERR_INT_RAW_M  (BIT(5))
-#define RMT_CH1_ERR_INT_RAW_V  0x1
-#define RMT_CH1_ERR_INT_RAW_S  5
-/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 1 turns to high level when
- the receive process is done.*/
-#define RMT_CH1_RX_END_INT_RAW  (BIT(4))
-#define RMT_CH1_RX_END_INT_RAW_M  (BIT(4))
-#define RMT_CH1_RX_END_INT_RAW_V  0x1
-#define RMT_CH1_RX_END_INT_RAW_S  4
-/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 1 turns to high level when
- the transmit process is done.*/
-#define RMT_CH1_TX_END_INT_RAW  (BIT(3))
-#define RMT_CH1_TX_END_INT_RAW_M  (BIT(3))
-#define RMT_CH1_TX_END_INT_RAW_V  0x1
-#define RMT_CH1_TX_END_INT_RAW_S  3
-/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 0 turns to high level when
- channle 0 detects some errors.*/
-#define RMT_CH0_ERR_INT_RAW  (BIT(2))
-#define RMT_CH0_ERR_INT_RAW_M  (BIT(2))
-#define RMT_CH0_ERR_INT_RAW_V  0x1
-#define RMT_CH0_ERR_INT_RAW_S  2
-/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 0 turns to high level when
- the receive process is done.*/
-#define RMT_CH0_RX_END_INT_RAW  (BIT(1))
-#define RMT_CH0_RX_END_INT_RAW_M  (BIT(1))
-#define RMT_CH0_RX_END_INT_RAW_V  0x1
-#define RMT_CH0_RX_END_INT_RAW_S  1
-/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for channel 0 turns to high level when
- the transmit process is done.*/
-#define RMT_CH0_TX_END_INT_RAW  (BIT(0))
-#define RMT_CH0_TX_END_INT_RAW_M  (BIT(0))
-#define RMT_CH0_TX_END_INT_RAW_V  0x1
-#define RMT_CH0_TX_END_INT_RAW_S  0
-
-#define RMT_INT_ST_REG          (DR_REG_RMT_BASE + 0x00a4)
-/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The interrupt state bit  for channel 7's rmt_ch7_tx_thr_event_int_raw
- when mt_ch7_tx_thr_event_int_ena is set to 1.*/
-#define RMT_CH7_TX_THR_EVENT_INT_ST  (BIT(31))
-#define RMT_CH7_TX_THR_EVENT_INT_ST_M  (BIT(31))
-#define RMT_CH7_TX_THR_EVENT_INT_ST_V  0x1
-#define RMT_CH7_TX_THR_EVENT_INT_ST_S  31
-/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The interrupt state bit  for channel 6's rmt_ch6_tx_thr_event_int_raw
- when mt_ch6_tx_thr_event_int_ena is set to 1.*/
-#define RMT_CH6_TX_THR_EVENT_INT_ST  (BIT(30))
-#define RMT_CH6_TX_THR_EVENT_INT_ST_M  (BIT(30))
-#define RMT_CH6_TX_THR_EVENT_INT_ST_V  0x1
-#define RMT_CH6_TX_THR_EVENT_INT_ST_S  30
-/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The interrupt state bit  for channel 5's rmt_ch5_tx_thr_event_int_raw
- when mt_ch5_tx_thr_event_int_ena is set to 1.*/
-#define RMT_CH5_TX_THR_EVENT_INT_ST  (BIT(29))
-#define RMT_CH5_TX_THR_EVENT_INT_ST_M  (BIT(29))
-#define RMT_CH5_TX_THR_EVENT_INT_ST_V  0x1
-#define RMT_CH5_TX_THR_EVENT_INT_ST_S  29
-/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: The interrupt state bit  for channel 4's rmt_ch4_tx_thr_event_int_raw
- when mt_ch4_tx_thr_event_int_ena is set to 1.*/
-#define RMT_CH4_TX_THR_EVENT_INT_ST  (BIT(28))
-#define RMT_CH4_TX_THR_EVENT_INT_ST_M  (BIT(28))
-#define RMT_CH4_TX_THR_EVENT_INT_ST_V  0x1
-#define RMT_CH4_TX_THR_EVENT_INT_ST_S  28
-/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: The interrupt state bit  for channel 3's rmt_ch3_tx_thr_event_int_raw
- when mt_ch3_tx_thr_event_int_ena is set to 1.*/
-#define RMT_CH3_TX_THR_EVENT_INT_ST  (BIT(27))
-#define RMT_CH3_TX_THR_EVENT_INT_ST_M  (BIT(27))
-#define RMT_CH3_TX_THR_EVENT_INT_ST_V  0x1
-#define RMT_CH3_TX_THR_EVENT_INT_ST_S  27
-/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: The interrupt state bit  for channel 2's rmt_ch2_tx_thr_event_int_raw
- when mt_ch2_tx_thr_event_int_ena is set to 1.*/
-#define RMT_CH2_TX_THR_EVENT_INT_ST  (BIT(26))
-#define RMT_CH2_TX_THR_EVENT_INT_ST_M  (BIT(26))
-#define RMT_CH2_TX_THR_EVENT_INT_ST_V  0x1
-#define RMT_CH2_TX_THR_EVENT_INT_ST_S  26
-/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: The interrupt state bit  for channel 1's rmt_ch1_tx_thr_event_int_raw
- when mt_ch1_tx_thr_event_int_ena is set to 1.*/
-#define RMT_CH1_TX_THR_EVENT_INT_ST  (BIT(25))
-#define RMT_CH1_TX_THR_EVENT_INT_ST_M  (BIT(25))
-#define RMT_CH1_TX_THR_EVENT_INT_ST_V  0x1
-#define RMT_CH1_TX_THR_EVENT_INT_ST_S  25
-/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: The interrupt state bit  for channel 0's rmt_ch0_tx_thr_event_int_raw
- when mt_ch0_tx_thr_event_int_ena is set to 1.*/
-#define RMT_CH0_TX_THR_EVENT_INT_ST  (BIT(24))
-#define RMT_CH0_TX_THR_EVENT_INT_ST_M  (BIT(24))
-#define RMT_CH0_TX_THR_EVENT_INT_ST_V  0x1
-#define RMT_CH0_TX_THR_EVENT_INT_ST_S  24
-/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 7's rmt_ch7_err_int_raw
- when  rmt_ch7_err_int_ena is set to 1.*/
-#define RMT_CH7_ERR_INT_ST  (BIT(23))
-#define RMT_CH7_ERR_INT_ST_M  (BIT(23))
-#define RMT_CH7_ERR_INT_ST_V  0x1
-#define RMT_CH7_ERR_INT_ST_S  23
-/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 7's rmt_ch7_rx_end_int_raw
- when  rmt_ch7_rx_end_int_ena is set to 1.*/
-#define RMT_CH7_RX_END_INT_ST  (BIT(22))
-#define RMT_CH7_RX_END_INT_ST_M  (BIT(22))
-#define RMT_CH7_RX_END_INT_ST_V  0x1
-#define RMT_CH7_RX_END_INT_ST_S  22
-/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 7's mt_ch7_tx_end_int_raw
- when mt_ch7_tx_end_int_ena is set to 1.*/
-#define RMT_CH7_TX_END_INT_ST  (BIT(21))
-#define RMT_CH7_TX_END_INT_ST_M  (BIT(21))
-#define RMT_CH7_TX_END_INT_ST_V  0x1
-#define RMT_CH7_TX_END_INT_ST_S  21
-/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 6's rmt_ch6_err_int_raw
- when  rmt_ch6_err_int_ena is set to 1.*/
-#define RMT_CH6_ERR_INT_ST  (BIT(20))
-#define RMT_CH6_ERR_INT_ST_M  (BIT(20))
-#define RMT_CH6_ERR_INT_ST_V  0x1
-#define RMT_CH6_ERR_INT_ST_S  20
-/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 6's rmt_ch6_rx_end_int_raw
- when  rmt_ch6_rx_end_int_ena is set to 1.*/
-#define RMT_CH6_RX_END_INT_ST  (BIT(19))
-#define RMT_CH6_RX_END_INT_ST_M  (BIT(19))
-#define RMT_CH6_RX_END_INT_ST_V  0x1
-#define RMT_CH6_RX_END_INT_ST_S  19
-/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 6's mt_ch6_tx_end_int_raw
- when mt_ch6_tx_end_int_ena is set to 1.*/
-#define RMT_CH6_TX_END_INT_ST  (BIT(18))
-#define RMT_CH6_TX_END_INT_ST_M  (BIT(18))
-#define RMT_CH6_TX_END_INT_ST_V  0x1
-#define RMT_CH6_TX_END_INT_ST_S  18
-/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 5's rmt_ch5_err_int_raw
- when  rmt_ch5_err_int_ena is set to 1.*/
-#define RMT_CH5_ERR_INT_ST  (BIT(17))
-#define RMT_CH5_ERR_INT_ST_M  (BIT(17))
-#define RMT_CH5_ERR_INT_ST_V  0x1
-#define RMT_CH5_ERR_INT_ST_S  17
-/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 5's rmt_ch5_rx_end_int_raw
- when  rmt_ch5_rx_end_int_ena is set to 1.*/
-#define RMT_CH5_RX_END_INT_ST  (BIT(16))
-#define RMT_CH5_RX_END_INT_ST_M  (BIT(16))
-#define RMT_CH5_RX_END_INT_ST_V  0x1
-#define RMT_CH5_RX_END_INT_ST_S  16
-/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 5's mt_ch5_tx_end_int_raw
- when mt_ch5_tx_end_int_ena is set to 1.*/
-#define RMT_CH5_TX_END_INT_ST  (BIT(15))
-#define RMT_CH5_TX_END_INT_ST_M  (BIT(15))
-#define RMT_CH5_TX_END_INT_ST_V  0x1
-#define RMT_CH5_TX_END_INT_ST_S  15
-/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 4's rmt_ch4_err_int_raw
- when  rmt_ch4_err_int_ena is set to 1.*/
-#define RMT_CH4_ERR_INT_ST  (BIT(14))
-#define RMT_CH4_ERR_INT_ST_M  (BIT(14))
-#define RMT_CH4_ERR_INT_ST_V  0x1
-#define RMT_CH4_ERR_INT_ST_S  14
-/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 4's rmt_ch4_rx_end_int_raw
- when  rmt_ch4_rx_end_int_ena is set to 1.*/
-#define RMT_CH4_RX_END_INT_ST  (BIT(13))
-#define RMT_CH4_RX_END_INT_ST_M  (BIT(13))
-#define RMT_CH4_RX_END_INT_ST_V  0x1
-#define RMT_CH4_RX_END_INT_ST_S  13
-/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 4's mt_ch4_tx_end_int_raw
- when mt_ch4_tx_end_int_ena is set to 1.*/
-#define RMT_CH4_TX_END_INT_ST  (BIT(12))
-#define RMT_CH4_TX_END_INT_ST_M  (BIT(12))
-#define RMT_CH4_TX_END_INT_ST_V  0x1
-#define RMT_CH4_TX_END_INT_ST_S  12
-/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 3's rmt_ch3_err_int_raw
- when  rmt_ch3_err_int_ena is set to 1.*/
-#define RMT_CH3_ERR_INT_ST  (BIT(11))
-#define RMT_CH3_ERR_INT_ST_M  (BIT(11))
-#define RMT_CH3_ERR_INT_ST_V  0x1
-#define RMT_CH3_ERR_INT_ST_S  11
-/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 3's rmt_ch3_rx_end_int_raw
- when  rmt_ch3_rx_end_int_ena is set to 1.*/
-#define RMT_CH3_RX_END_INT_ST  (BIT(10))
-#define RMT_CH3_RX_END_INT_ST_M  (BIT(10))
-#define RMT_CH3_RX_END_INT_ST_V  0x1
-#define RMT_CH3_RX_END_INT_ST_S  10
-/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 3's mt_ch3_tx_end_int_raw
- when mt_ch3_tx_end_int_ena is set to 1.*/
-#define RMT_CH3_TX_END_INT_ST  (BIT(9))
-#define RMT_CH3_TX_END_INT_ST_M  (BIT(9))
-#define RMT_CH3_TX_END_INT_ST_V  0x1
-#define RMT_CH3_TX_END_INT_ST_S  9
-/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 2's rmt_ch2_err_int_raw
- when  rmt_ch2_err_int_ena is set to 1.*/
-#define RMT_CH2_ERR_INT_ST  (BIT(8))
-#define RMT_CH2_ERR_INT_ST_M  (BIT(8))
-#define RMT_CH2_ERR_INT_ST_V  0x1
-#define RMT_CH2_ERR_INT_ST_S  8
-/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 2's rmt_ch2_rx_end_int_raw
- when  rmt_ch2_rx_end_int_ena is set to 1.*/
-#define RMT_CH2_RX_END_INT_ST  (BIT(7))
-#define RMT_CH2_RX_END_INT_ST_M  (BIT(7))
-#define RMT_CH2_RX_END_INT_ST_V  0x1
-#define RMT_CH2_RX_END_INT_ST_S  7
-/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 2's mt_ch2_tx_end_int_raw
- when mt_ch2_tx_end_int_ena is set to 1.*/
-#define RMT_CH2_TX_END_INT_ST  (BIT(6))
-#define RMT_CH2_TX_END_INT_ST_M  (BIT(6))
-#define RMT_CH2_TX_END_INT_ST_V  0x1
-#define RMT_CH2_TX_END_INT_ST_S  6
-/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 1's rmt_ch1_err_int_raw
- when  rmt_ch1_err_int_ena is set to 1.*/
-#define RMT_CH1_ERR_INT_ST  (BIT(5))
-#define RMT_CH1_ERR_INT_ST_M  (BIT(5))
-#define RMT_CH1_ERR_INT_ST_V  0x1
-#define RMT_CH1_ERR_INT_ST_S  5
-/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 1's rmt_ch1_rx_end_int_raw
- when  rmt_ch1_rx_end_int_ena is set to 1.*/
-#define RMT_CH1_RX_END_INT_ST  (BIT(4))
-#define RMT_CH1_RX_END_INT_ST_M  (BIT(4))
-#define RMT_CH1_RX_END_INT_ST_V  0x1
-#define RMT_CH1_RX_END_INT_ST_S  4
-/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 1's mt_ch1_tx_end_int_raw
- when mt_ch1_tx_end_int_ena is set to 1.*/
-#define RMT_CH1_TX_END_INT_ST  (BIT(3))
-#define RMT_CH1_TX_END_INT_ST_M  (BIT(3))
-#define RMT_CH1_TX_END_INT_ST_V  0x1
-#define RMT_CH1_TX_END_INT_ST_S  3
-/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 0's rmt_ch0_err_int_raw
- when  rmt_ch0_err_int_ena is set to 0.*/
-#define RMT_CH0_ERR_INT_ST  (BIT(2))
-#define RMT_CH0_ERR_INT_ST_M  (BIT(2))
-#define RMT_CH0_ERR_INT_ST_V  0x1
-#define RMT_CH0_ERR_INT_ST_S  2
-/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 0's rmt_ch0_rx_end_int_raw
- when  rmt_ch0_rx_end_int_ena is set to 0.*/
-#define RMT_CH0_RX_END_INT_ST  (BIT(1))
-#define RMT_CH0_RX_END_INT_ST_M  (BIT(1))
-#define RMT_CH0_RX_END_INT_ST_V  0x1
-#define RMT_CH0_RX_END_INT_ST_S  1
-/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt  state bit for channel 0's mt_ch0_tx_end_int_raw
- when mt_ch0_tx_end_int_ena is set to 0.*/
-#define RMT_CH0_TX_END_INT_ST  (BIT(0))
-#define RMT_CH0_TX_END_INT_ST_M  (BIT(0))
-#define RMT_CH0_TX_END_INT_ST_V  0x1
-#define RMT_CH0_TX_END_INT_ST_S  0
-
-#define RMT_INT_ENA_REG          (DR_REG_RMT_BASE + 0x00a8)
-/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
-#define RMT_CH7_TX_THR_EVENT_INT_ENA  (BIT(31))
-#define RMT_CH7_TX_THR_EVENT_INT_ENA_M  (BIT(31))
-#define RMT_CH7_TX_THR_EVENT_INT_ENA_V  0x1
-#define RMT_CH7_TX_THR_EVENT_INT_ENA_S  31
-/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
-#define RMT_CH6_TX_THR_EVENT_INT_ENA  (BIT(30))
-#define RMT_CH6_TX_THR_EVENT_INT_ENA_M  (BIT(30))
-#define RMT_CH6_TX_THR_EVENT_INT_ENA_V  0x1
-#define RMT_CH6_TX_THR_EVENT_INT_ENA_S  30
-/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
-#define RMT_CH5_TX_THR_EVENT_INT_ENA  (BIT(29))
-#define RMT_CH5_TX_THR_EVENT_INT_ENA_M  (BIT(29))
-#define RMT_CH5_TX_THR_EVENT_INT_ENA_V  0x1
-#define RMT_CH5_TX_THR_EVENT_INT_ENA_S  29
-/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
-#define RMT_CH4_TX_THR_EVENT_INT_ENA  (BIT(28))
-#define RMT_CH4_TX_THR_EVENT_INT_ENA_M  (BIT(28))
-#define RMT_CH4_TX_THR_EVENT_INT_ENA_V  0x1
-#define RMT_CH4_TX_THR_EVENT_INT_ENA_S  28
-/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
-#define RMT_CH3_TX_THR_EVENT_INT_ENA  (BIT(27))
-#define RMT_CH3_TX_THR_EVENT_INT_ENA_M  (BIT(27))
-#define RMT_CH3_TX_THR_EVENT_INT_ENA_V  0x1
-#define RMT_CH3_TX_THR_EVENT_INT_ENA_S  27
-/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
-#define RMT_CH2_TX_THR_EVENT_INT_ENA  (BIT(26))
-#define RMT_CH2_TX_THR_EVENT_INT_ENA_M  (BIT(26))
-#define RMT_CH2_TX_THR_EVENT_INT_ENA_V  0x1
-#define RMT_CH2_TX_THR_EVENT_INT_ENA_S  26
-/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
-#define RMT_CH1_TX_THR_EVENT_INT_ENA  (BIT(25))
-#define RMT_CH1_TX_THR_EVENT_INT_ENA_M  (BIT(25))
-#define RMT_CH1_TX_THR_EVENT_INT_ENA_V  0x1
-#define RMT_CH1_TX_THR_EVENT_INT_ENA_S  25
-/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
-#define RMT_CH0_TX_THR_EVENT_INT_ENA  (BIT(24))
-#define RMT_CH0_TX_THR_EVENT_INT_ENA_M  (BIT(24))
-#define RMT_CH0_TX_THR_EVENT_INT_ENA_V  0x1
-#define RMT_CH0_TX_THR_EVENT_INT_ENA_S  24
-/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch7_err_int_st.*/
-#define RMT_CH7_ERR_INT_ENA  (BIT(23))
-#define RMT_CH7_ERR_INT_ENA_M  (BIT(23))
-#define RMT_CH7_ERR_INT_ENA_V  0x1
-#define RMT_CH7_ERR_INT_ENA_S  23
-/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/
-#define RMT_CH7_RX_END_INT_ENA  (BIT(22))
-#define RMT_CH7_RX_END_INT_ENA_M  (BIT(22))
-#define RMT_CH7_RX_END_INT_ENA_V  0x1
-#define RMT_CH7_RX_END_INT_ENA_S  22
-/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/
-#define RMT_CH7_TX_END_INT_ENA  (BIT(21))
-#define RMT_CH7_TX_END_INT_ENA_M  (BIT(21))
-#define RMT_CH7_TX_END_INT_ENA_V  0x1
-#define RMT_CH7_TX_END_INT_ENA_S  21
-/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch6_err_int_st.*/
-#define RMT_CH6_ERR_INT_ENA  (BIT(20))
-#define RMT_CH6_ERR_INT_ENA_M  (BIT(20))
-#define RMT_CH6_ERR_INT_ENA_V  0x1
-#define RMT_CH6_ERR_INT_ENA_S  20
-/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/
-#define RMT_CH6_RX_END_INT_ENA  (BIT(19))
-#define RMT_CH6_RX_END_INT_ENA_M  (BIT(19))
-#define RMT_CH6_RX_END_INT_ENA_V  0x1
-#define RMT_CH6_RX_END_INT_ENA_S  19
-/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/
-#define RMT_CH6_TX_END_INT_ENA  (BIT(18))
-#define RMT_CH6_TX_END_INT_ENA_M  (BIT(18))
-#define RMT_CH6_TX_END_INT_ENA_V  0x1
-#define RMT_CH6_TX_END_INT_ENA_S  18
-/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch5_err_int_st.*/
-#define RMT_CH5_ERR_INT_ENA  (BIT(17))
-#define RMT_CH5_ERR_INT_ENA_M  (BIT(17))
-#define RMT_CH5_ERR_INT_ENA_V  0x1
-#define RMT_CH5_ERR_INT_ENA_S  17
-/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/
-#define RMT_CH5_RX_END_INT_ENA  (BIT(16))
-#define RMT_CH5_RX_END_INT_ENA_M  (BIT(16))
-#define RMT_CH5_RX_END_INT_ENA_V  0x1
-#define RMT_CH5_RX_END_INT_ENA_S  16
-/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/
-#define RMT_CH5_TX_END_INT_ENA  (BIT(15))
-#define RMT_CH5_TX_END_INT_ENA_M  (BIT(15))
-#define RMT_CH5_TX_END_INT_ENA_V  0x1
-#define RMT_CH5_TX_END_INT_ENA_S  15
-/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch4_err_int_st.*/
-#define RMT_CH4_ERR_INT_ENA  (BIT(14))
-#define RMT_CH4_ERR_INT_ENA_M  (BIT(14))
-#define RMT_CH4_ERR_INT_ENA_V  0x1
-#define RMT_CH4_ERR_INT_ENA_S  14
-/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/
-#define RMT_CH4_RX_END_INT_ENA  (BIT(13))
-#define RMT_CH4_RX_END_INT_ENA_M  (BIT(13))
-#define RMT_CH4_RX_END_INT_ENA_V  0x1
-#define RMT_CH4_RX_END_INT_ENA_S  13
-/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/
-#define RMT_CH4_TX_END_INT_ENA  (BIT(12))
-#define RMT_CH4_TX_END_INT_ENA_M  (BIT(12))
-#define RMT_CH4_TX_END_INT_ENA_V  0x1
-#define RMT_CH4_TX_END_INT_ENA_S  12
-/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch3_err_int_st.*/
-#define RMT_CH3_ERR_INT_ENA  (BIT(11))
-#define RMT_CH3_ERR_INT_ENA_M  (BIT(11))
-#define RMT_CH3_ERR_INT_ENA_V  0x1
-#define RMT_CH3_ERR_INT_ENA_S  11
-/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/
-#define RMT_CH3_RX_END_INT_ENA  (BIT(10))
-#define RMT_CH3_RX_END_INT_ENA_M  (BIT(10))
-#define RMT_CH3_RX_END_INT_ENA_V  0x1
-#define RMT_CH3_RX_END_INT_ENA_S  10
-/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/
-#define RMT_CH3_TX_END_INT_ENA  (BIT(9))
-#define RMT_CH3_TX_END_INT_ENA_M  (BIT(9))
-#define RMT_CH3_TX_END_INT_ENA_V  0x1
-#define RMT_CH3_TX_END_INT_ENA_S  9
-/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch2_err_int_st.*/
-#define RMT_CH2_ERR_INT_ENA  (BIT(8))
-#define RMT_CH2_ERR_INT_ENA_M  (BIT(8))
-#define RMT_CH2_ERR_INT_ENA_V  0x1
-#define RMT_CH2_ERR_INT_ENA_S  8
-/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/
-#define RMT_CH2_RX_END_INT_ENA  (BIT(7))
-#define RMT_CH2_RX_END_INT_ENA_M  (BIT(7))
-#define RMT_CH2_RX_END_INT_ENA_V  0x1
-#define RMT_CH2_RX_END_INT_ENA_S  7
-/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/
-#define RMT_CH2_TX_END_INT_ENA  (BIT(6))
-#define RMT_CH2_TX_END_INT_ENA_M  (BIT(6))
-#define RMT_CH2_TX_END_INT_ENA_V  0x1
-#define RMT_CH2_TX_END_INT_ENA_S  6
-/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch1_err_int_st.*/
-#define RMT_CH1_ERR_INT_ENA  (BIT(5))
-#define RMT_CH1_ERR_INT_ENA_M  (BIT(5))
-#define RMT_CH1_ERR_INT_ENA_V  0x1
-#define RMT_CH1_ERR_INT_ENA_S  5
-/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/
-#define RMT_CH1_RX_END_INT_ENA  (BIT(4))
-#define RMT_CH1_RX_END_INT_ENA_M  (BIT(4))
-#define RMT_CH1_RX_END_INT_ENA_V  0x1
-#define RMT_CH1_RX_END_INT_ENA_S  4
-/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/
-#define RMT_CH1_TX_END_INT_ENA  (BIT(3))
-#define RMT_CH1_TX_END_INT_ENA_M  (BIT(3))
-#define RMT_CH1_TX_END_INT_ENA_V  0x1
-#define RMT_CH1_TX_END_INT_ENA_S  3
-/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch0_err_int_st.*/
-#define RMT_CH0_ERR_INT_ENA  (BIT(2))
-#define RMT_CH0_ERR_INT_ENA_M  (BIT(2))
-#define RMT_CH0_ERR_INT_ENA_V  0x1
-#define RMT_CH0_ERR_INT_ENA_S  2
-/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/
-#define RMT_CH0_RX_END_INT_ENA  (BIT(1))
-#define RMT_CH0_RX_END_INT_ENA_M  (BIT(1))
-#define RMT_CH0_RX_END_INT_ENA_V  0x1
-#define RMT_CH0_RX_END_INT_ENA_S  1
-/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/
-#define RMT_CH0_TX_END_INT_ENA  (BIT(0))
-#define RMT_CH0_TX_END_INT_ENA_M  (BIT(0))
-#define RMT_CH0_TX_END_INT_ENA_V  0x1
-#define RMT_CH0_TX_END_INT_ENA_S  0
-
-#define RMT_INT_CLR_REG          (DR_REG_RMT_BASE + 0x00ac)
-/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch7_tx_thr_event_int_raw interrupt.*/
-#define RMT_CH7_TX_THR_EVENT_INT_CLR  (BIT(31))
-#define RMT_CH7_TX_THR_EVENT_INT_CLR_M  (BIT(31))
-#define RMT_CH7_TX_THR_EVENT_INT_CLR_V  0x1
-#define RMT_CH7_TX_THR_EVENT_INT_CLR_S  31
-/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch6_tx_thr_event_int_raw interrupt.*/
-#define RMT_CH6_TX_THR_EVENT_INT_CLR  (BIT(30))
-#define RMT_CH6_TX_THR_EVENT_INT_CLR_M  (BIT(30))
-#define RMT_CH6_TX_THR_EVENT_INT_CLR_V  0x1
-#define RMT_CH6_TX_THR_EVENT_INT_CLR_S  30
-/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch5_tx_thr_event_int_raw interrupt.*/
-#define RMT_CH5_TX_THR_EVENT_INT_CLR  (BIT(29))
-#define RMT_CH5_TX_THR_EVENT_INT_CLR_M  (BIT(29))
-#define RMT_CH5_TX_THR_EVENT_INT_CLR_V  0x1
-#define RMT_CH5_TX_THR_EVENT_INT_CLR_S  29
-/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch4_tx_thr_event_int_raw interrupt.*/
-#define RMT_CH4_TX_THR_EVENT_INT_CLR  (BIT(28))
-#define RMT_CH4_TX_THR_EVENT_INT_CLR_M  (BIT(28))
-#define RMT_CH4_TX_THR_EVENT_INT_CLR_V  0x1
-#define RMT_CH4_TX_THR_EVENT_INT_CLR_S  28
-/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch3_tx_thr_event_int_raw interrupt.*/
-#define RMT_CH3_TX_THR_EVENT_INT_CLR  (BIT(27))
-#define RMT_CH3_TX_THR_EVENT_INT_CLR_M  (BIT(27))
-#define RMT_CH3_TX_THR_EVENT_INT_CLR_V  0x1
-#define RMT_CH3_TX_THR_EVENT_INT_CLR_S  27
-/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch2_tx_thr_event_int_raw interrupt.*/
-#define RMT_CH2_TX_THR_EVENT_INT_CLR  (BIT(26))
-#define RMT_CH2_TX_THR_EVENT_INT_CLR_M  (BIT(26))
-#define RMT_CH2_TX_THR_EVENT_INT_CLR_V  0x1
-#define RMT_CH2_TX_THR_EVENT_INT_CLR_S  26
-/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch1_tx_thr_event_int_raw interrupt.*/
-#define RMT_CH1_TX_THR_EVENT_INT_CLR  (BIT(25))
-#define RMT_CH1_TX_THR_EVENT_INT_CLR_M  (BIT(25))
-#define RMT_CH1_TX_THR_EVENT_INT_CLR_V  0x1
-#define RMT_CH1_TX_THR_EVENT_INT_CLR_S  25
-/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch0_tx_thr_event_int_raw interrupt.*/
-#define RMT_CH0_TX_THR_EVENT_INT_CLR  (BIT(24))
-#define RMT_CH0_TX_THR_EVENT_INT_CLR_M  (BIT(24))
-#define RMT_CH0_TX_THR_EVENT_INT_CLR_V  0x1
-#define RMT_CH0_TX_THR_EVENT_INT_CLR_S  24
-/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch7_err_int_raw.*/
-#define RMT_CH7_ERR_INT_CLR  (BIT(23))
-#define RMT_CH7_ERR_INT_CLR_M  (BIT(23))
-#define RMT_CH7_ERR_INT_CLR_V  0x1
-#define RMT_CH7_ERR_INT_CLR_S  23
-/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
-#define RMT_CH7_RX_END_INT_CLR  (BIT(22))
-#define RMT_CH7_RX_END_INT_CLR_M  (BIT(22))
-#define RMT_CH7_RX_END_INT_CLR_V  0x1
-#define RMT_CH7_RX_END_INT_CLR_S  22
-/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
-#define RMT_CH7_TX_END_INT_CLR  (BIT(21))
-#define RMT_CH7_TX_END_INT_CLR_M  (BIT(21))
-#define RMT_CH7_TX_END_INT_CLR_V  0x1
-#define RMT_CH7_TX_END_INT_CLR_S  21
-/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch6_err_int_raw.*/
-#define RMT_CH6_ERR_INT_CLR  (BIT(20))
-#define RMT_CH6_ERR_INT_CLR_M  (BIT(20))
-#define RMT_CH6_ERR_INT_CLR_V  0x1
-#define RMT_CH6_ERR_INT_CLR_S  20
-/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
-#define RMT_CH6_RX_END_INT_CLR  (BIT(19))
-#define RMT_CH6_RX_END_INT_CLR_M  (BIT(19))
-#define RMT_CH6_RX_END_INT_CLR_V  0x1
-#define RMT_CH6_RX_END_INT_CLR_S  19
-/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
-#define RMT_CH6_TX_END_INT_CLR  (BIT(18))
-#define RMT_CH6_TX_END_INT_CLR_M  (BIT(18))
-#define RMT_CH6_TX_END_INT_CLR_V  0x1
-#define RMT_CH6_TX_END_INT_CLR_S  18
-/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch5_err_int_raw.*/
-#define RMT_CH5_ERR_INT_CLR  (BIT(17))
-#define RMT_CH5_ERR_INT_CLR_M  (BIT(17))
-#define RMT_CH5_ERR_INT_CLR_V  0x1
-#define RMT_CH5_ERR_INT_CLR_S  17
-/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
-#define RMT_CH5_RX_END_INT_CLR  (BIT(16))
-#define RMT_CH5_RX_END_INT_CLR_M  (BIT(16))
-#define RMT_CH5_RX_END_INT_CLR_V  0x1
-#define RMT_CH5_RX_END_INT_CLR_S  16
-/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
-#define RMT_CH5_TX_END_INT_CLR  (BIT(15))
-#define RMT_CH5_TX_END_INT_CLR_M  (BIT(15))
-#define RMT_CH5_TX_END_INT_CLR_V  0x1
-#define RMT_CH5_TX_END_INT_CLR_S  15
-/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch4_err_int_raw.*/
-#define RMT_CH4_ERR_INT_CLR  (BIT(14))
-#define RMT_CH4_ERR_INT_CLR_M  (BIT(14))
-#define RMT_CH4_ERR_INT_CLR_V  0x1
-#define RMT_CH4_ERR_INT_CLR_S  14
-/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
-#define RMT_CH4_RX_END_INT_CLR  (BIT(13))
-#define RMT_CH4_RX_END_INT_CLR_M  (BIT(13))
-#define RMT_CH4_RX_END_INT_CLR_V  0x1
-#define RMT_CH4_RX_END_INT_CLR_S  13
-/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
-#define RMT_CH4_TX_END_INT_CLR  (BIT(12))
-#define RMT_CH4_TX_END_INT_CLR_M  (BIT(12))
-#define RMT_CH4_TX_END_INT_CLR_V  0x1
-#define RMT_CH4_TX_END_INT_CLR_S  12
-/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch3_err_int_raw.*/
-#define RMT_CH3_ERR_INT_CLR  (BIT(11))
-#define RMT_CH3_ERR_INT_CLR_M  (BIT(11))
-#define RMT_CH3_ERR_INT_CLR_V  0x1
-#define RMT_CH3_ERR_INT_CLR_S  11
-/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
-#define RMT_CH3_RX_END_INT_CLR  (BIT(10))
-#define RMT_CH3_RX_END_INT_CLR_M  (BIT(10))
-#define RMT_CH3_RX_END_INT_CLR_V  0x1
-#define RMT_CH3_RX_END_INT_CLR_S  10
-/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
-#define RMT_CH3_TX_END_INT_CLR  (BIT(9))
-#define RMT_CH3_TX_END_INT_CLR_M  (BIT(9))
-#define RMT_CH3_TX_END_INT_CLR_V  0x1
-#define RMT_CH3_TX_END_INT_CLR_S  9
-/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch2_err_int_raw.*/
-#define RMT_CH2_ERR_INT_CLR  (BIT(8))
-#define RMT_CH2_ERR_INT_CLR_M  (BIT(8))
-#define RMT_CH2_ERR_INT_CLR_V  0x1
-#define RMT_CH2_ERR_INT_CLR_S  8
-/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
-#define RMT_CH2_RX_END_INT_CLR  (BIT(7))
-#define RMT_CH2_RX_END_INT_CLR_M  (BIT(7))
-#define RMT_CH2_RX_END_INT_CLR_V  0x1
-#define RMT_CH2_RX_END_INT_CLR_S  7
-/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
-#define RMT_CH2_TX_END_INT_CLR  (BIT(6))
-#define RMT_CH2_TX_END_INT_CLR_M  (BIT(6))
-#define RMT_CH2_TX_END_INT_CLR_V  0x1
-#define RMT_CH2_TX_END_INT_CLR_S  6
-/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch1_err_int_raw.*/
-#define RMT_CH1_ERR_INT_CLR  (BIT(5))
-#define RMT_CH1_ERR_INT_CLR_M  (BIT(5))
-#define RMT_CH1_ERR_INT_CLR_V  0x1
-#define RMT_CH1_ERR_INT_CLR_S  5
-/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
-#define RMT_CH1_RX_END_INT_CLR  (BIT(4))
-#define RMT_CH1_RX_END_INT_CLR_M  (BIT(4))
-#define RMT_CH1_RX_END_INT_CLR_V  0x1
-#define RMT_CH1_RX_END_INT_CLR_S  4
-/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
-#define RMT_CH1_TX_END_INT_CLR  (BIT(3))
-#define RMT_CH1_TX_END_INT_CLR_M  (BIT(3))
-#define RMT_CH1_TX_END_INT_CLR_V  0x1
-#define RMT_CH1_TX_END_INT_CLR_S  3
-/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear the  rmt_ch0_err_int_raw.*/
-#define RMT_CH0_ERR_INT_CLR  (BIT(2))
-#define RMT_CH0_ERR_INT_CLR_M  (BIT(2))
-#define RMT_CH0_ERR_INT_CLR_V  0x1
-#define RMT_CH0_ERR_INT_CLR_S  2
-/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
-#define RMT_CH0_RX_END_INT_CLR  (BIT(1))
-#define RMT_CH0_RX_END_INT_CLR_M  (BIT(1))
-#define RMT_CH0_RX_END_INT_CLR_V  0x1
-#define RMT_CH0_RX_END_INT_CLR_S  1
-/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
-#define RMT_CH0_TX_END_INT_CLR  (BIT(0))
-#define RMT_CH0_TX_END_INT_CLR_M  (BIT(0))
-#define RMT_CH0_TX_END_INT_CLR_V  0x1
-#define RMT_CH0_TX_END_INT_CLR_S  0
-
-#define RMT_CH0CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00b0)
-/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's high level value for channel0.*/
-#define RMT_CARRIER_HIGH_CH0  0x0000FFFF
-#define RMT_CARRIER_HIGH_CH0_M  ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S))
-#define RMT_CARRIER_HIGH_CH0_V  0xFFFF
-#define RMT_CARRIER_HIGH_CH0_S  16
-/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's low level value for channel0.*/
-#define RMT_CARRIER_LOW_CH0  0x0000FFFF
-#define RMT_CARRIER_LOW_CH0_M  ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S))
-#define RMT_CARRIER_LOW_CH0_V  0xFFFF
-#define RMT_CARRIER_LOW_CH0_S  0
-
-#define RMT_CH1CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00b4)
-/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's high level value for channel1.*/
-#define RMT_CARRIER_HIGH_CH1  0x0000FFFF
-#define RMT_CARRIER_HIGH_CH1_M  ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S))
-#define RMT_CARRIER_HIGH_CH1_V  0xFFFF
-#define RMT_CARRIER_HIGH_CH1_S  16
-/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's low level value for channel1.*/
-#define RMT_CARRIER_LOW_CH1  0x0000FFFF
-#define RMT_CARRIER_LOW_CH1_M  ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S))
-#define RMT_CARRIER_LOW_CH1_V  0xFFFF
-#define RMT_CARRIER_LOW_CH1_S  0
-
-#define RMT_CH2CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00b8)
-/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's high level value for channel2.*/
-#define RMT_CARRIER_HIGH_CH2  0x0000FFFF
-#define RMT_CARRIER_HIGH_CH2_M  ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S))
-#define RMT_CARRIER_HIGH_CH2_V  0xFFFF
-#define RMT_CARRIER_HIGH_CH2_S  16
-/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's low level value for channel2.*/
-#define RMT_CARRIER_LOW_CH2  0x0000FFFF
-#define RMT_CARRIER_LOW_CH2_M  ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S))
-#define RMT_CARRIER_LOW_CH2_V  0xFFFF
-#define RMT_CARRIER_LOW_CH2_S  0
-
-#define RMT_CH3CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00bc)
-/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's high level value for channel3.*/
-#define RMT_CARRIER_HIGH_CH3  0x0000FFFF
-#define RMT_CARRIER_HIGH_CH3_M  ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S))
-#define RMT_CARRIER_HIGH_CH3_V  0xFFFF
-#define RMT_CARRIER_HIGH_CH3_S  16
-/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's low level value for channel3.*/
-#define RMT_CARRIER_LOW_CH3  0x0000FFFF
-#define RMT_CARRIER_LOW_CH3_M  ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S))
-#define RMT_CARRIER_LOW_CH3_V  0xFFFF
-#define RMT_CARRIER_LOW_CH3_S  0
-
-#define RMT_CH4CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00c0)
-/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's high level value for channel4.*/
-#define RMT_CARRIER_HIGH_CH4  0x0000FFFF
-#define RMT_CARRIER_HIGH_CH4_M  ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S))
-#define RMT_CARRIER_HIGH_CH4_V  0xFFFF
-#define RMT_CARRIER_HIGH_CH4_S  16
-/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's low level value for channel4.*/
-#define RMT_CARRIER_LOW_CH4  0x0000FFFF
-#define RMT_CARRIER_LOW_CH4_M  ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S))
-#define RMT_CARRIER_LOW_CH4_V  0xFFFF
-#define RMT_CARRIER_LOW_CH4_S  0
-
-#define RMT_CH5CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00c4)
-/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's high level value for channel5.*/
-#define RMT_CARRIER_HIGH_CH5  0x0000FFFF
-#define RMT_CARRIER_HIGH_CH5_M  ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S))
-#define RMT_CARRIER_HIGH_CH5_V  0xFFFF
-#define RMT_CARRIER_HIGH_CH5_S  16
-/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's low level value for channel5.*/
-#define RMT_CARRIER_LOW_CH5  0x0000FFFF
-#define RMT_CARRIER_LOW_CH5_M  ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S))
-#define RMT_CARRIER_LOW_CH5_V  0xFFFF
-#define RMT_CARRIER_LOW_CH5_S  0
-
-#define RMT_CH6CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00c8)
-/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's high level value for channel6.*/
-#define RMT_CARRIER_HIGH_CH6  0x0000FFFF
-#define RMT_CARRIER_HIGH_CH6_M  ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S))
-#define RMT_CARRIER_HIGH_CH6_V  0xFFFF
-#define RMT_CARRIER_HIGH_CH6_S  16
-/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's low level value for channel6.*/
-#define RMT_CARRIER_LOW_CH6  0x0000FFFF
-#define RMT_CARRIER_LOW_CH6_M  ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S))
-#define RMT_CARRIER_LOW_CH6_V  0xFFFF
-#define RMT_CARRIER_LOW_CH6_S  0
-
-#define RMT_CH7CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00cc)
-/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's high level value for channel7.*/
-#define RMT_CARRIER_HIGH_CH7  0x0000FFFF
-#define RMT_CARRIER_HIGH_CH7_M  ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S))
-#define RMT_CARRIER_HIGH_CH7_V  0xFFFF
-#define RMT_CARRIER_HIGH_CH7_S  16
-/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
-/*description: This register is used to configure carrier wave's low level value for channel7.*/
-#define RMT_CARRIER_LOW_CH7  0x0000FFFF
-#define RMT_CARRIER_LOW_CH7_M  ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S))
-#define RMT_CARRIER_LOW_CH7_V  0xFFFF
-#define RMT_CARRIER_LOW_CH7_S  0
-
-#define RMT_CH0_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00d0)
-/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
-/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0
- produce the relative interrupt.*/
-#define RMT_TX_LIM_CH0  0x000001FF
-#define RMT_TX_LIM_CH0_M  ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S))
-#define RMT_TX_LIM_CH0_V  0x1FF
-#define RMT_TX_LIM_CH0_S  0
-
-#define RMT_CH1_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00d4)
-/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
-/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1
- produce the relative interrupt.*/
-#define RMT_TX_LIM_CH1  0x000001FF
-#define RMT_TX_LIM_CH1_M  ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S))
-#define RMT_TX_LIM_CH1_V  0x1FF
-#define RMT_TX_LIM_CH1_S  0
-
-#define RMT_CH2_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00d8)
-/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
-/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2
- produce the relative interrupt.*/
-#define RMT_TX_LIM_CH2  0x000001FF
-#define RMT_TX_LIM_CH2_M  ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S))
-#define RMT_TX_LIM_CH2_V  0x1FF
-#define RMT_TX_LIM_CH2_S  0
-
-#define RMT_CH3_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00dc)
-/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
-/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3
- produce the relative interrupt.*/
-#define RMT_TX_LIM_CH3  0x000001FF
-#define RMT_TX_LIM_CH3_M  ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S))
-#define RMT_TX_LIM_CH3_V  0x1FF
-#define RMT_TX_LIM_CH3_S  0
-
-#define RMT_CH4_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00e0)
-/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
-/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4
- produce the relative interrupt.*/
-#define RMT_TX_LIM_CH4  0x000001FF
-#define RMT_TX_LIM_CH4_M  ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S))
-#define RMT_TX_LIM_CH4_V  0x1FF
-#define RMT_TX_LIM_CH4_S  0
-
-#define RMT_CH5_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00e4)
-/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
-/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5
- produce the relative interrupt.*/
-#define RMT_TX_LIM_CH5  0x000001FF
-#define RMT_TX_LIM_CH5_M  ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S))
-#define RMT_TX_LIM_CH5_V  0x1FF
-#define RMT_TX_LIM_CH5_S  0
-
-#define RMT_CH6_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00e8)
-/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
-/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6
- produce the relative interrupt.*/
-#define RMT_TX_LIM_CH6  0x000001FF
-#define RMT_TX_LIM_CH6_M  ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S))
-#define RMT_TX_LIM_CH6_V  0x1FF
-#define RMT_TX_LIM_CH6_S  0
-
-#define RMT_CH7_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00ec)
-/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
-/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7
- produce the relative interrupt.*/
-#define RMT_TX_LIM_CH7  0x000001FF
-#define RMT_TX_LIM_CH7_M  ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S))
-#define RMT_TX_LIM_CH7_V  0x1FF
-#define RMT_TX_LIM_CH7_S  0
-
-#define RMT_APB_CONF_REG          (DR_REG_RMT_BASE + 0x00f0)
-/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: when datas need to be send is more than channel's mem can store
-  then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/
-#define RMT_MEM_TX_WRAP_EN  (BIT(1))
-#define RMT_MEM_TX_WRAP_EN_M  (BIT(1))
-#define RMT_MEM_TX_WRAP_EN_V  0x1
-#define RMT_MEM_TX_WRAP_EN_S  1
-/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to disable apb fifo access*/
-#define RMT_APB_FIFO_MASK  (BIT(0))
-#define RMT_APB_FIFO_MASK_M  (BIT(0))
-#define RMT_APB_FIFO_MASK_V  0x1
-#define RMT_APB_FIFO_MASK_S  0
-
-#define RMT_DATE_REG          (DR_REG_RMT_BASE + 0x00fc)
-/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022600 ; */
-/*description: This is the version register.*/
-#define RMT_DATE  0xFFFFFFFF
-#define RMT_DATE_M  ((RMT_DATE_V)<<(RMT_DATE_S))
-#define RMT_DATE_V  0xFFFFFFFF
-#define RMT_DATE_S  0
-
-/* RMT memory block address */
-#define RMT_CHANNEL_MEM(i)  (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i))
-
-
-#endif /*_SOC_RMT_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/rmt_struct.h b/tools/sdk/include/soc/soc/rmt_struct.h
deleted file mode 100644
index bc4cd7a2ec5..00000000000
--- a/tools/sdk/include/soc/soc/rmt_struct.h
+++ /dev/null
@@ -1,264 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_RMT_STRUCT_H_
-#define _SOC_RMT_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    uint32_t data_ch[8];                                /*The R/W ram address for channel0-7 by apb fifo access.
-                                                        Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
-                                                        and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
-    struct{
-        union {
-            struct {
-                uint32_t div_cnt:        8;             /*This register is used to configure the  frequency divider's factor in channel0-7.*/
-                uint32_t idle_thres:    16;             /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/
-                uint32_t mem_size:       4;             /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/
-                uint32_t carrier_en:     1;             /*This is the carrier modulation enable control bit for channel0-7.*/
-                uint32_t carrier_out_lv: 1;             /*This bit is used to configure the way carrier wave is modulated for  channel0-7.1'b1:transmit on low output level  1'b0:transmit  on high output level.*/
-                uint32_t mem_pd:         1;             /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/
-                uint32_t clk_en:         1;             /*This bit  is used  to control clock.when software configure RMT internal registers  it controls the register clock.*/
-            };
-            uint32_t val;
-        } conf0;
-        union {
-            struct {
-                uint32_t tx_start:        1;            /*Set this bit to start sending data for channel0-7.*/
-                uint32_t rx_en:           1;            /*Set this bit to enable receiving data for channel0-7.*/
-                uint32_t mem_wr_rst:      1;            /*Set this bit to reset write ram address for channel0-7 by receiver access.*/
-                uint32_t mem_rd_rst:      1;            /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/
-                uint32_t apb_mem_rst:     1;            /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/
-                uint32_t mem_owner:       1;            /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram  0：transmitter uses the ram*/
-                uint32_t tx_conti_mode:   1;            /*Set this bit to continue sending  from the first data to the last data in channel0-7 again and again.*/
-                uint32_t rx_filter_en:    1;            /*This is the receive filter enable bit for channel0-7.*/
-                uint32_t rx_filter_thres: 8;            /*in receive mode  channel0-7 ignore input pulse when the pulse width is smaller then this value.*/
-                uint32_t ref_cnt_rst:     1;            /*This bit is used to reset divider in channel0-7.*/
-                uint32_t ref_always_on:   1;            /*This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
-                uint32_t idle_out_lv:     1;            /*This bit configures the output signal's level for channel0-7 in IDLE state.*/
-                uint32_t idle_out_en:     1;            /*This is the output enable control bit for channel0-7 in IDLE state.*/
-                uint32_t reserved20:     12;
-            };
-            uint32_t val;
-        } conf1;
-    } conf_ch[8];
-    uint32_t status_ch[8];                              /*The status for channel0-7*/
-    uint32_t apb_mem_addr_ch[8];                        /*The ram relative address in channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/
-    union {
-        struct {
-            uint32_t ch0_tx_end:       1;               /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
-            uint32_t ch0_rx_end:       1;               /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/
-            uint32_t ch0_err:          1;               /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/
-            uint32_t ch1_tx_end:       1;               /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/
-            uint32_t ch1_rx_end:       1;               /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/
-            uint32_t ch1_err:          1;               /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/
-            uint32_t ch2_tx_end:       1;               /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/
-            uint32_t ch2_rx_end:       1;               /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/
-            uint32_t ch2_err:          1;               /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/
-            uint32_t ch3_tx_end:       1;               /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/
-            uint32_t ch3_rx_end:       1;               /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/
-            uint32_t ch3_err:          1;               /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/
-            uint32_t ch4_tx_end:       1;               /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/
-            uint32_t ch4_rx_end:       1;               /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/
-            uint32_t ch4_err:          1;               /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/
-            uint32_t ch5_tx_end:       1;               /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/
-            uint32_t ch5_rx_end:       1;               /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/
-            uint32_t ch5_err:          1;               /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/
-            uint32_t ch6_tx_end:       1;               /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/
-            uint32_t ch6_rx_end:       1;               /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/
-            uint32_t ch6_err:          1;               /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/
-            uint32_t ch7_tx_end:       1;               /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/
-            uint32_t ch7_rx_end:       1;               /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/
-            uint32_t ch7_err:          1;               /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/
-            uint32_t ch0_tx_thr_event: 1;               /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0  have send data more than  reg_rmt_tx_lim_ch0  after detecting this interrupt  software can updata the old data with new data.*/
-            uint32_t ch1_tx_thr_event: 1;               /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1  have send data more than  reg_rmt_tx_lim_ch1  after detecting this interrupt  software can updata the old data with new data.*/
-            uint32_t ch2_tx_thr_event: 1;               /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2  have send data more than  reg_rmt_tx_lim_ch2  after detecting this interrupt  software can updata the old data with new data.*/
-            uint32_t ch3_tx_thr_event: 1;               /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3  have send data more than  reg_rmt_tx_lim_ch3  after detecting this interrupt  software can updata the old data with new data.*/
-            uint32_t ch4_tx_thr_event: 1;               /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4  have send data more than  reg_rmt_tx_lim_ch4  after detecting this interrupt  software can updata the old data with new data.*/
-            uint32_t ch5_tx_thr_event: 1;               /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5  have send data more than  reg_rmt_tx_lim_ch5  after detecting this interrupt  software can updata the old data with new data.*/
-            uint32_t ch6_tx_thr_event: 1;               /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6  have send data more than  reg_rmt_tx_lim_ch6  after detecting this interrupt  software can updata the old data with new data.*/
-            uint32_t ch7_tx_thr_event: 1;               /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7  have send data more than  reg_rmt_tx_lim_ch7  after detecting this interrupt  software can updata the old data with new data.*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t ch0_tx_end:       1;                /*The interrupt  state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
-            uint32_t ch0_rx_end:       1;                /*The interrupt  state bit for channel 0's rmt_ch0_rx_end_int_raw when  rmt_ch0_rx_end_int_ena is set to 0.*/
-            uint32_t ch0_err:          1;                /*The interrupt  state bit for channel 0's rmt_ch0_err_int_raw when  rmt_ch0_err_int_ena is set to 0.*/
-            uint32_t ch1_tx_end:       1;                /*The interrupt  state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/
-            uint32_t ch1_rx_end:       1;                /*The interrupt  state bit for channel 1's rmt_ch1_rx_end_int_raw when  rmt_ch1_rx_end_int_ena is set to 1.*/
-            uint32_t ch1_err:          1;                /*The interrupt  state bit for channel 1's rmt_ch1_err_int_raw when  rmt_ch1_err_int_ena is set to 1.*/
-            uint32_t ch2_tx_end:       1;                /*The interrupt  state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/
-            uint32_t ch2_rx_end:       1;                /*The interrupt  state bit for channel 2's rmt_ch2_rx_end_int_raw when  rmt_ch2_rx_end_int_ena is set to 1.*/
-            uint32_t ch2_err:          1;                /*The interrupt  state bit for channel 2's rmt_ch2_err_int_raw when  rmt_ch2_err_int_ena is set to 1.*/
-            uint32_t ch3_tx_end:       1;                /*The interrupt  state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/
-            uint32_t ch3_rx_end:       1;                /*The interrupt  state bit for channel 3's rmt_ch3_rx_end_int_raw when  rmt_ch3_rx_end_int_ena is set to 1.*/
-            uint32_t ch3_err:          1;                /*The interrupt  state bit for channel 3's rmt_ch3_err_int_raw when  rmt_ch3_err_int_ena is set to 1.*/
-            uint32_t ch4_tx_end:       1;                /*The interrupt  state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/
-            uint32_t ch4_rx_end:       1;                /*The interrupt  state bit for channel 4's rmt_ch4_rx_end_int_raw when  rmt_ch4_rx_end_int_ena is set to 1.*/
-            uint32_t ch4_err:          1;                /*The interrupt  state bit for channel 4's rmt_ch4_err_int_raw when  rmt_ch4_err_int_ena is set to 1.*/
-            uint32_t ch5_tx_end:       1;                /*The interrupt  state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/
-            uint32_t ch5_rx_end:       1;                /*The interrupt  state bit for channel 5's rmt_ch5_rx_end_int_raw when  rmt_ch5_rx_end_int_ena is set to 1.*/
-            uint32_t ch5_err:          1;                /*The interrupt  state bit for channel 5's rmt_ch5_err_int_raw when  rmt_ch5_err_int_ena is set to 1.*/
-            uint32_t ch6_tx_end:       1;                /*The interrupt  state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/
-            uint32_t ch6_rx_end:       1;                /*The interrupt  state bit for channel 6's rmt_ch6_rx_end_int_raw when  rmt_ch6_rx_end_int_ena is set to 1.*/
-            uint32_t ch6_err:          1;                /*The interrupt  state bit for channel 6's rmt_ch6_err_int_raw when  rmt_ch6_err_int_ena is set to 1.*/
-            uint32_t ch7_tx_end:       1;                /*The interrupt  state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/
-            uint32_t ch7_rx_end:       1;                /*The interrupt  state bit for channel 7's rmt_ch7_rx_end_int_raw when  rmt_ch7_rx_end_int_ena is set to 1.*/
-            uint32_t ch7_err:          1;                /*The interrupt  state bit for channel 7's rmt_ch7_err_int_raw when  rmt_ch7_err_int_ena is set to 1.*/
-            uint32_t ch0_tx_thr_event: 1;                /*The interrupt state bit  for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/
-            uint32_t ch1_tx_thr_event: 1;                /*The interrupt state bit  for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/
-            uint32_t ch2_tx_thr_event: 1;                /*The interrupt state bit  for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/
-            uint32_t ch3_tx_thr_event: 1;                /*The interrupt state bit  for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/
-            uint32_t ch4_tx_thr_event: 1;                /*The interrupt state bit  for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/
-            uint32_t ch5_tx_thr_event: 1;                /*The interrupt state bit  for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/
-            uint32_t ch6_tx_thr_event: 1;                /*The interrupt state bit  for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/
-            uint32_t ch7_tx_thr_event: 1;                /*The interrupt state bit  for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t ch0_tx_end:       1;               /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
-            uint32_t ch0_rx_end:       1;               /*Set this bit to enable rmt_ch0_rx_end_int_st.*/
-            uint32_t ch0_err:          1;               /*Set this bit to enable rmt_ch0_err_int_st.*/
-            uint32_t ch1_tx_end:       1;               /*Set this bit to enable rmt_ch1_tx_end_int_st.*/
-            uint32_t ch1_rx_end:       1;               /*Set this bit to enable rmt_ch1_rx_end_int_st.*/
-            uint32_t ch1_err:          1;               /*Set this bit to enable rmt_ch1_err_int_st.*/
-            uint32_t ch2_tx_end:       1;               /*Set this bit to enable rmt_ch2_tx_end_int_st.*/
-            uint32_t ch2_rx_end:       1;               /*Set this bit to enable rmt_ch2_rx_end_int_st.*/
-            uint32_t ch2_err:          1;               /*Set this bit to enable rmt_ch2_err_int_st.*/
-            uint32_t ch3_tx_end:       1;               /*Set this bit to enable rmt_ch3_tx_end_int_st.*/
-            uint32_t ch3_rx_end:       1;               /*Set this bit to enable rmt_ch3_rx_end_int_st.*/
-            uint32_t ch3_err:          1;               /*Set this bit to enable rmt_ch3_err_int_st.*/
-            uint32_t ch4_tx_end:       1;               /*Set this bit to enable rmt_ch4_tx_end_int_st.*/
-            uint32_t ch4_rx_end:       1;               /*Set this bit to enable rmt_ch4_rx_end_int_st.*/
-            uint32_t ch4_err:          1;               /*Set this bit to enable rmt_ch4_err_int_st.*/
-            uint32_t ch5_tx_end:       1;               /*Set this bit to enable rmt_ch5_tx_end_int_st.*/
-            uint32_t ch5_rx_end:       1;               /*Set this bit to enable rmt_ch5_rx_end_int_st.*/
-            uint32_t ch5_err:          1;               /*Set this bit to enable rmt_ch5_err_int_st.*/
-            uint32_t ch6_tx_end:       1;               /*Set this bit to enable rmt_ch6_tx_end_int_st.*/
-            uint32_t ch6_rx_end:       1;               /*Set this bit to enable rmt_ch6_rx_end_int_st.*/
-            uint32_t ch6_err:          1;               /*Set this bit to enable rmt_ch6_err_int_st.*/
-            uint32_t ch7_tx_end:       1;               /*Set this bit to enable rmt_ch7_tx_end_int_st.*/
-            uint32_t ch7_rx_end:       1;               /*Set this bit to enable rmt_ch7_rx_end_int_st.*/
-            uint32_t ch7_err:          1;               /*Set this bit to enable rmt_ch7_err_int_st.*/
-            uint32_t ch0_tx_thr_event: 1;               /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
-            uint32_t ch1_tx_thr_event: 1;               /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
-            uint32_t ch2_tx_thr_event: 1;               /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
-            uint32_t ch3_tx_thr_event: 1;               /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
-            uint32_t ch4_tx_thr_event: 1;               /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
-            uint32_t ch5_tx_thr_event: 1;               /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
-            uint32_t ch6_tx_thr_event: 1;               /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
-            uint32_t ch7_tx_thr_event: 1;               /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t ch0_tx_end:       1;               /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
-            uint32_t ch0_rx_end:       1;               /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
-            uint32_t ch0_err:          1;               /*Set this bit to clear the  rmt_ch0_err_int_raw.*/
-            uint32_t ch1_tx_end:       1;               /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
-            uint32_t ch1_rx_end:       1;               /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
-            uint32_t ch1_err:          1;               /*Set this bit to clear the  rmt_ch1_err_int_raw.*/
-            uint32_t ch2_tx_end:       1;               /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
-            uint32_t ch2_rx_end:       1;               /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
-            uint32_t ch2_err:          1;               /*Set this bit to clear the  rmt_ch2_err_int_raw.*/
-            uint32_t ch3_tx_end:       1;               /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
-            uint32_t ch3_rx_end:       1;               /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
-            uint32_t ch3_err:          1;               /*Set this bit to clear the  rmt_ch3_err_int_raw.*/
-            uint32_t ch4_tx_end:       1;               /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
-            uint32_t ch4_rx_end:       1;               /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
-            uint32_t ch4_err:          1;               /*Set this bit to clear the  rmt_ch4_err_int_raw.*/
-            uint32_t ch5_tx_end:       1;               /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
-            uint32_t ch5_rx_end:       1;               /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
-            uint32_t ch5_err:          1;               /*Set this bit to clear the  rmt_ch5_err_int_raw.*/
-            uint32_t ch6_tx_end:       1;               /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
-            uint32_t ch6_rx_end:       1;               /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
-            uint32_t ch6_err:          1;               /*Set this bit to clear the  rmt_ch6_err_int_raw.*/
-            uint32_t ch7_tx_end:       1;               /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
-            uint32_t ch7_rx_end:       1;               /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
-            uint32_t ch7_err:          1;               /*Set this bit to clear the  rmt_ch7_err_int_raw.*/
-            uint32_t ch0_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch0_tx_thr_event_int_raw interrupt.*/
-            uint32_t ch1_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch1_tx_thr_event_int_raw interrupt.*/
-            uint32_t ch2_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch2_tx_thr_event_int_raw interrupt.*/
-            uint32_t ch3_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch3_tx_thr_event_int_raw interrupt.*/
-            uint32_t ch4_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch4_tx_thr_event_int_raw interrupt.*/
-            uint32_t ch5_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch5_tx_thr_event_int_raw interrupt.*/
-            uint32_t ch6_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch6_tx_thr_event_int_raw interrupt.*/
-            uint32_t ch7_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch7_tx_thr_event_int_raw interrupt.*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t low: 16;                           /*This register is used to configure carrier wave's low level value for channel0-7.*/
-            uint32_t high:16;                           /*This register is used to configure carrier wave's high level value for channel0-7.*/
-        };
-        uint32_t val;
-    } carrier_duty_ch[8];
-    union {
-        struct {
-            uint32_t limit: 9;                          /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/
-            uint32_t reserved9: 23;
-        };
-        uint32_t val;
-    } tx_lim_ch[8];
-    union {
-        struct {
-            uint32_t fifo_mask:  1;                     /*Set this bit to enable RMTMEM and disable apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/
-            uint32_t mem_tx_wrap_en: 1;                 /*when data need to be send is more than channel's mem can store  then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/
-            uint32_t reserved2:     30;
-        };
-        uint32_t val;
-    } apb_conf;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t date;                                      /*This is the version register.*/
-} rmt_dev_t;
-extern rmt_dev_t RMT;
-
-typedef struct {
-    union {
-        struct {
-            uint32_t duration0 :15;
-            uint32_t level0 :1;
-            uint32_t duration1 :15;
-            uint32_t level1 :1;
-        };
-        uint32_t val;
-    };
-} rmt_item32_t;
-
-//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
-typedef volatile struct {
-    struct {
-        union {
-            rmt_item32_t data32[64];
-        };
-    } chan[8];
-} rmt_mem_t;
-extern rmt_mem_t RMTMEM;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_RMT_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/rtc.h b/tools/sdk/include/soc/soc/rtc.h
deleted file mode 100644
index a528bdd15de..00000000000
--- a/tools/sdk/include/soc/soc/rtc.h
+++ /dev/null
@@ -1,726 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @file rtc.h
- * @brief Low-level RTC power, clock, and sleep functions.
- *
- * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
- * RTC_CNTL peripheral handles many functions:
- * - enables/disables clocks and power to various parts of the chip; this is
- *   done using direct register access (forcing power up or power down) or by
- *   allowing state machines to control power and clocks automatically
- * - handles sleep and wakeup functions
- * - maintains a 48-bit counter which can be used for timekeeping
- *
- * These functions are not thread safe, and should not be viewed as high level
- * APIs. For example, while this file provides a function which can switch
- * CPU frequency, this function is on its own is not sufficient to implement
- * frequency switching in ESP-IDF context: some coordination with RTOS,
- * peripheral drivers, and WiFi/BT stacks is also required.
- *
- * These functions will normally not be used in applications directly.
- * ESP-IDF provides, or will provide, drivers and other facilities to use
- * RTC subsystem functionality.
- *
- * The functions are loosely split into the following groups:
- * - rtc_clk: clock switching, calibration
- * - rtc_time: reading RTC counter, conversion between counter values and time
- * - rtc_sleep: entry into sleep modes
- * - rtc_init: initialization
- */
-
-
-/**
- * @brief Possible main XTAL frequency values.
- *
- * Enum values should be equal to frequency in MHz.
- */
-typedef enum {
-    RTC_XTAL_FREQ_AUTO = 0,     //!< Automatic XTAL frequency detection
-    RTC_XTAL_FREQ_40M = 40,     //!< 40 MHz XTAL
-    RTC_XTAL_FREQ_26M = 26,     //!< 26 MHz XTAL
-    RTC_XTAL_FREQ_24M = 24,     //!< 24 MHz XTAL
-} rtc_xtal_freq_t;
-
-/**
- * @brief CPU frequency values
- */
-typedef enum {
-    RTC_CPU_FREQ_XTAL = 0,      //!< Main XTAL frequency
-    RTC_CPU_FREQ_80M = 1,       //!< 80 MHz
-    RTC_CPU_FREQ_160M = 2,      //!< 160 MHz
-    RTC_CPU_FREQ_240M = 3,      //!< 240 MHz
-    RTC_CPU_FREQ_2M = 4,        //!< 2 MHz
-} rtc_cpu_freq_t;
-
-/**
- * @brief CPU clock source
- */
-typedef enum {
-    RTC_CPU_FREQ_SRC_XTAL,  //!< XTAL
-    RTC_CPU_FREQ_SRC_PLL,   //!< PLL (480M or 320M)
-    RTC_CPU_FREQ_SRC_8M,    //!< Internal 8M RTC oscillator
-    RTC_CPU_FREQ_SRC_APLL   //!< APLL
-} rtc_cpu_freq_src_t;
-
-/**
- * @brief CPU clock configuration structure
- */
-typedef struct {
-    rtc_cpu_freq_src_t source;      //!< The clock from which CPU clock is derived
-    uint32_t source_freq_mhz;       //!< Source clock frequency
-    uint32_t div;                   //!< Divider, freq_mhz = source_freq_mhz / div
-    uint32_t freq_mhz;              //!< CPU clock frequency
-} rtc_cpu_freq_config_t;
-
-/**
- * @brief RTC SLOW_CLK frequency values
- */
-typedef enum {
-    RTC_SLOW_FREQ_RTC = 0,      //!< Internal 150 kHz RC oscillator
-    RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
-    RTC_SLOW_FREQ_8MD256 = 2,   //!< Internal 8 MHz RC oscillator, divided by 256
-} rtc_slow_freq_t;
-
-/**
- * @brief RTC FAST_CLK frequency values
- */
-typedef enum {
-    RTC_FAST_FREQ_XTALD4 = 0,   //!< Main XTAL, divided by 4
-    RTC_FAST_FREQ_8M = 1,       //!< Internal 8 MHz RC oscillator
-} rtc_fast_freq_t;
-
-/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
-#define RTC_FAST_CLK_FREQ_APPROX 8500000
-
-/**
- * @brief Clock source to be calibrated using rtc_clk_cal function
- */
-typedef enum {
-    RTC_CAL_RTC_MUX = 0,       //!< Currently selected RTC SLOW_CLK
-    RTC_CAL_8MD256 = 1,        //!< Internal 8 MHz RC oscillator, divided by 256
-    RTC_CAL_32K_XTAL = 2       //!< External 32 kHz XTAL
-} rtc_cal_sel_t;
-
-/**
- * Initialization parameters for rtc_clk_init
- */
-typedef struct {
-    rtc_xtal_freq_t xtal_freq : 8;      //!< Main XTAL frequency
-    rtc_cpu_freq_t cpu_freq_mhz : 10;   //!< CPU frequency to set, in MHz
-    rtc_fast_freq_t fast_freq : 1;      //!< RTC_FAST_CLK frequency to set
-    rtc_slow_freq_t slow_freq : 2;      //!< RTC_SLOW_CLK frequency to set
-    uint32_t clk_8m_div : 3;            //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
-    uint32_t slow_clk_dcap : 8;         //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
-    uint32_t clk_8m_dfreq : 8;          //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
-} rtc_clk_config_t;
-
-/**
- * Default initializer for rtc_clk_config_t
- */
-#define RTC_CLK_CONFIG_DEFAULT() { \
-    .xtal_freq = RTC_XTAL_FREQ_AUTO, \
-    .cpu_freq_mhz = 80, \
-    .fast_freq = RTC_FAST_FREQ_8M, \
-    .slow_freq = RTC_SLOW_FREQ_RTC, \
-    .clk_8m_div = 0, \
-    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
-    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
-}
-
-/**
- * Initialize clocks and set CPU frequency
- *
- * If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt
- * to auto detect XTAL frequency. Auto detection is performed by comparing
- * XTAL frequency with the frequency of internal 8MHz oscillator. Note that at
- * high temperatures the frequency of the internal 8MHz oscillator may drift
- * enough for auto detection to be unreliable.
- * Auto detection code will attempt to distinguish between 26MHz and 40MHz
- * crystals. 24 MHz crystals are not supported by auto detection code.
- * If XTAL frequency can not be auto detected, this 26MHz frequency will be used.
- *
- * @param cfg clock configuration as rtc_clk_config_t
- */
-void rtc_clk_init(rtc_clk_config_t cfg);
-
-/**
- * @brief Get main XTAL frequency
- *
- * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
- * rtc_clk_init function, or if the value was RTC_XTAL_FREQ_AUTO, the detected
- * XTAL frequency.
- *
- * @return XTAL frequency, one of rtc_xtal_freq_t
- */
-rtc_xtal_freq_t rtc_clk_xtal_freq_get();
-
-/**
- * @brief Update XTAL frequency
- *
- * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
- * after startup.
- *
- * @param xtal_freq New frequency value
- */
-void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
-
-/**
- * @brief Enable or disable 32 kHz XTAL oscillator
- * @param en  true to enable, false to disable
- */
-void rtc_clk_32k_enable(bool en);
-
-/**
- * @brief Configure 32 kHz XTAL oscillator to accept external clock signal
- */
-void rtc_clk_32k_enable_external();
-
-/**
- * @brief Get the state of 32k XTAL oscillator
- * @return true if 32k XTAL oscillator has been enabled
- */
-bool rtc_clk_32k_enabled();
-
-/**
- * @brief Enable 32k oscillator, configuring it for fast startup time.
- * Note: to achieve higher frequency stability, rtc_clk_32k_enable function
- * must be called one the 32k XTAL oscillator has started up. This function
- * will initially disable the 32k XTAL oscillator, so it should not be called
- * when the system is using 32k XTAL as RTC_SLOW_CLK.
- *
- * @param cycle Number of 32kHz cycles to bootstrap external crystal.
- *              If 0, no square wave will be used to bootstrap crystal oscillation.
- */
-void rtc_clk_32k_bootstrap(uint32_t cycle);
-
-/**
- * @brief Enable or disable 8 MHz internal oscillator
- *
- * Output from 8 MHz internal oscillator is passed into a configurable
- * divider, which by default divides the input clock frequency by 256.
- * Output of the divider may be used as RTC_SLOW_CLK source.
- * Output of the divider is referred to in register descriptions and code as
- * 8md256 or simply d256. Divider values other than 256 may be configured, but
- * this facility is not currently needed, so is not exposed in the code.
- *
- * When 8MHz/256 divided output is not needed, the divider should be disabled
- * to reduce power consumption.
- *
- * @param clk_8m_en true to enable 8MHz generator
- * @param d256_en true to enable /256 divider
- */
-void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
-
-/**
- * @brief Get the state of 8 MHz internal oscillator
- * @return true if the oscillator is enabled
- */
-bool rtc_clk_8m_enabled();
-
-/**
- * @brief Get the state of /256 divider which is applied to 8MHz clock
- * @return true if the divided output is enabled
- */
-bool rtc_clk_8md256_enabled();
-
-/**
- * @brief Enable or disable APLL
- *
- * Output frequency is given by the formula:
- * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
- *
- * The dividend in this expression should be in the range of 240 - 600 MHz.
- *
- * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
- *
- * @param enable  true to enable, false to disable
- * @param sdm0  frequency adjustment parameter, 0..255
- * @param sdm1  frequency adjustment parameter, 0..255
- * @param sdm2  frequency adjustment parameter, 0..63
- * @param o_div  frequency divider, 0..31
- */
-void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1,
-        uint32_t sdm2, uint32_t o_div);
-
-/**
- * @brief Select source for RTC_SLOW_CLK
- * @param slow_freq clock source (one of rtc_slow_freq_t values)
- */
-void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
-
-/**
- * @brief Get the RTC_SLOW_CLK source
- * @return currently selected clock source (one of rtc_slow_freq_t values)
- */
-rtc_slow_freq_t rtc_clk_slow_freq_get();
-
-/**
- * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
- *
- * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
- * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
- * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
- *
- * rtc_clk_cal function can be used to get more precise value by comparing
- * RTC_SLOW_CLK frequency to the frequency of main XTAL.
- *
- * @return RTC_SLOW_CLK frequency, in Hz
- */
-uint32_t rtc_clk_slow_freq_get_hz();
-
-/**
- * @brief Select source for RTC_FAST_CLK
- * @param fast_freq clock source (one of rtc_fast_freq_t values)
- */
-void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
-
-/**
- * @brief Get the RTC_FAST_CLK source
- * @return currently selected clock source (one of rtc_fast_freq_t values)
- */
-rtc_fast_freq_t rtc_clk_fast_freq_get();
-
-/**
- * @brief Switch CPU frequency
- *
- * @note This function is deprecated and will be removed.
- *       See rtc_clk_cpu_freq_config_set instead.
- *
- * If a PLL-derived frequency is requested (80, 160, 240 MHz), this function
- * will enable the PLL. Otherwise, PLL will be disabled.
- * Note: this function is not optimized for switching speed. It may take several
- * hundred microseconds to perform frequency switch.
- *
- * @param cpu_freq  new CPU frequency
- */
-void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated));
-
-/**
- * @brief Switch CPU frequency
- *
- * @note This function is deprecated and will be removed.
- *       See rtc_clk_cpu_freq_set_config_fast instead.
- *
- * This is a faster version of rtc_clk_cpu_freq_set, which can handle some of
- * the frequency switch paths (XTAL -> PLL, PLL -> XTAL).
- * When switching from PLL to XTAL, PLL is not disabled (unlike rtc_clk_cpu_freq_set).
- * When switching back from XTAL to PLL, only the same PLL can be used.
- * Therefore it is not possible to switch 240 -> XTAL -> (80 or 160) using this
- * function.
- *
- * For unsupported cases, this function falls back to rtc_clk_cpu_freq_set.
- *
- * Unlike rtc_clk_cpu_freq_set, this function relies on static data, so it is
- * less safe to use it e.g. from a panic handler (when memory might be corrupted).
- *
- * @param cpu_freq  new CPU frequency
- */
-void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq) __attribute__((deprecated));
-
-/**
- * @brief Get the currently selected CPU frequency
- *
- * @note This function is deprecated and will be removed.
- *       See rtc_clk_cpu_freq_get_config instead.
- *
- * Although CPU can be clocked by APLL and RTC 8M sources, such support is not
- * exposed through this library. As such, this function will not return
- * meaningful values when these clock sources are configured (e.g. using direct
- * access to clock selection registers). In debug builds, it will assert; in
- * release builds, it will return RTC_CPU_FREQ_XTAL.
- *
- * @return CPU frequency (one of rtc_cpu_freq_t values)
- */
-rtc_cpu_freq_t rtc_clk_cpu_freq_get()  __attribute__((deprecated));
-
-/**
- * @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
- *
- * @note This function is deprecated and will be removed.
- *       See rtc_clk_cpu_freq_get/set_config instead.
- *
- * @param cpu_freq  CPU frequency, on of rtc_cpu_freq_t values
- * @return CPU frequency, in HZ
- */
-uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq)  __attribute__((deprecated));
-
-/**
- * @brief Get rtc_cpu_freq_t enum value for given CPU frequency
- *
- * @note This function is deprecated and will be removed.
- *       See rtc_clk_cpu_freq_mhz_to_config instead.
- *
- * @param cpu_freq_mhz  CPU frequency, one of 80, 160, 240, 2, and XTAL frequency
- * @param[out] out_val output, rtc_cpu_freq_t value corresponding to the frequency
- * @return true if the given frequency value matches one of enum values
- */
- bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t* out_val) __attribute__((deprecated));
-
-/**
- * @brief Get CPU frequency config corresponding to a rtc_cpu_freq_t value
- * @param cpu_freq CPU frequency enumeration value
- * @param[out] out_config  Output, CPU frequency configuration structure
- */
- void rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq, rtc_cpu_freq_config_t* out_config);
-
- /**
-  * @brief Get CPU frequency config for a given frequency
-  * @param freq_mhz  Frequency in MHz
-  * @param[out] out_config Output, CPU frequency configuration structure
-  * @return true if frequency can be obtained, false otherwise
-  */
- bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config);
-
- /**
-  * @brief Switch CPU frequency
-  *
-  * This function sets CPU frequency according to the given configuration
-  * structure. It enables PLLs, if necessary.
-  *
-  * @note This function in not intended to be called by applications in FreeRTOS
-  * environment. This is because it does not adjust various timers based on the
-  * new CPU frequency.
-  *
-  * @param config  CPU frequency configuration structure
-  */
- void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config);
-
- /**
-  * @brief Switch CPU frequency (optimized for speed)
-  *
-  * This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
-  * It works faster because it does not disable PLLs when switching from PLL to
-  * XTAL and does not enabled them when switching back. If PLL is not already
-  * enabled when this function is called to switch from XTAL to PLL frequency,
-  * or the PLL which is enabled is the wrong one, this function will fall back
-  * to calling rtc_clk_cpu_freq_set_config.
-  *
-  * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
-  * so it is less safe to use it e.g. from a panic handler (when memory might
-  * be corrupted).
-  *
-  * @note This function in not intended to be called by applications in FreeRTOS
-  * environment. This is because it does not adjust various timers based on the
-  * new CPU frequency.
-  *
-  * @param config  CPU frequency configuration structure
-  */
- void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config);
-
- /**
-  * @brief Get the currently used CPU frequency configuration
-  * @param[out] out_config  Output, CPU frequency configuration structure
-  */
- void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config);
-
- /**
-  * @brief Switch CPU clock source to XTAL
-  *
-  * Short form for filling in rtc_cpu_freq_config_t structure and calling
-  * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
-  * Assumes that XTAL frequency has been determined — don't call in startup code.
-  */
- void rtc_clk_cpu_freq_set_xtal();
-
-
-/**
- * @brief Store new APB frequency value into RTC_APB_FREQ_REG
- *
- * This function doesn't change any hardware clocks.
- *
- * Functions which perform frequency switching and change APB frequency call
- * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
- * (one of RTC general purpose retention registers). This should not normally
- * be called from application code.
- *
- * @param apb_freq  new APB frequency, in Hz
- */
-void rtc_clk_apb_freq_update(uint32_t apb_freq);
-
-/**
- * @brief Get the current stored APB frequency.
- * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
- */
-uint32_t rtc_clk_apb_freq_get();
-
-#define RTC_CLK_CAL_FRACT  19  //!< Number of fractional bits in values returned by rtc_clk_cal
-
-/**
- * @brief Measure RTC slow clock's period, based on main XTAL frequency
- *
- * This function will time out and return 0 if the time for the given number
- * of cycles to be counted exceeds the expected time twice. This may happen if
- * 32k XTAL is being calibrated, but the oscillator has not started up (due to
- * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
- *
- * @param cal_clk  clock to be measured
- * @param slow_clk_cycles  number of slow clock cycles to average
- * @return average slow clock period in microseconds, Q13.19 fixed point format,
- *         or 0 if calibration has timed out
- */
-uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
-
-/**
- * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
- * @param cal_clk slow clock to be measured
- * @param slow_clk_cycles number of slow clock cycles to average
- * @return average ratio between XTAL frequency and slow clock frequency,
- *         Q13.19 fixed point format, or 0 if calibration has timed out.
- */
-uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
-
-/**
- * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
- * @param time_in_us Time interval in microseconds
- * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
- *                         fixed point format (as returned by rtc_slowck_cali).
- * @return number of slow clock cycles
- */
-uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
-
-/**
- * @brief Convert time interval from RTC_SLOW_CLK to microseconds
- * @param time_in_us Time interval in RTC_SLOW_CLK cycles
- * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
- *                         fixed point format (as returned by rtc_slowck_cali).
- * @return time interval in microseconds
- */
-uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
-
-/**
- * @brief Get current value of RTC counter
- *
- * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
- * cycles. Counter value is not writable by software. The value is not adjusted
- * when switching to a different RTC_SLOW_CLK source.
- *
- * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
- *
- * @return current value of RTC counter
- */
-uint64_t rtc_time_get();
-
-/**
- * @brief Busy loop until next RTC_SLOW_CLK cycle
- *
- * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
- * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
- * one RTC_SLOW_CLK cycle later.
- */
-void rtc_clk_wait_for_slow_cycle();
-
-/**
- * @brief sleep configuration for rtc_sleep_init function
- */
-typedef struct {
-    uint32_t lslp_mem_inf_fpu : 1;      //!< force normal voltage in sleep mode (digital domain memory)
-    uint32_t rtc_mem_inf_fpu : 1;       //!< force normal voltage in sleep mode (RTC memory)
-    uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
-    uint32_t rtc_fastmem_pd_en : 1;     //!< power down RTC fast memory
-    uint32_t rtc_slowmem_pd_en : 1;     //!< power down RTC slow memory
-    uint32_t rtc_peri_pd_en : 1;        //!< power down RTC peripherals
-    uint32_t wifi_pd_en : 1;            //!< power down WiFi
-    uint32_t rom_mem_pd_en : 1;         //!< power down main RAM and ROM
-    uint32_t deep_slp : 1;              //!< power down digital domain
-    uint32_t wdt_flashboot_mod_en : 1;  //!< enable WDT flashboot mode
-    uint32_t dig_dbias_wak : 3;         //!< set bias for digital domain, in active mode
-    uint32_t dig_dbias_slp : 3;         //!< set bias for digital domain, in sleep mode
-    uint32_t rtc_dbias_wak : 3;         //!< set bias for RTC domain, in active mode
-    uint32_t rtc_dbias_slp : 3;         //!< set bias for RTC domain, in sleep mode
-    uint32_t lslp_meminf_pd : 1;        //!< remove all peripheral force power up flags
-    uint32_t vddsdio_pd_en : 1;         //!< power down VDDSDIO regulator
-    uint32_t xtal_fpu : 1;              //!< keep main XTAL powered up in sleep
-} rtc_sleep_config_t;
-
-/**
- * Default initializer for rtc_sleep_config_t
- *
- * This initializer sets all fields to "reasonable" values (e.g. suggested for
- * production use) based on a combination of RTC_SLEEP_PD_x flags.
- *
- * @param RTC_SLEEP_PD_x flags combined using bitwise OR
- */
-#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
-    .lslp_mem_inf_fpu = 0, \
-    .rtc_mem_inf_fpu = 0, \
-    .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
-    .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
-    .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
-    .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
-    .wifi_pd_en = 0, \
-    .rom_mem_pd_en = 0, \
-    .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
-    .wdt_flashboot_mod_en = 0, \
-    .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
-    .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \
-    .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
-    .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \
-    .lslp_meminf_pd = 1, \
-    .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
-    .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \
-};
-
-#define RTC_SLEEP_PD_DIG                BIT(0)  //!< Deep sleep (power down digital domain)
-#define RTC_SLEEP_PD_RTC_PERIPH         BIT(1)  //!< Power down RTC peripherals
-#define RTC_SLEEP_PD_RTC_SLOW_MEM       BIT(2)  //!< Power down RTC SLOW memory
-#define RTC_SLEEP_PD_RTC_FAST_MEM       BIT(3)  //!< Power down RTC FAST memory
-#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)  //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
-#define RTC_SLEEP_PD_VDDSDIO            BIT(5)  //!< Power down VDDSDIO regulator
-#define RTC_SLEEP_PD_XTAL               BIT(6)  //!< Power down main XTAL
-
-/**
- * @brief Prepare the chip to enter sleep mode
- *
- * This function configures various power control state machines to handle
- * entry into light sleep or deep sleep mode, switches APB and CPU clock source
- * (usually to XTAL), and sets bias voltages for digital and RTC power domains.
- *
- * This function does not actually enter sleep mode; this is done using
- * rtc_sleep_start function. Software may do some other actions between
- * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
- * wakeup sources.
- * @param cfg sleep mode configuration
- */
-void rtc_sleep_init(rtc_sleep_config_t cfg);
-
-
-/**
- * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
- * @param t value of RTC counter at which wakeup from sleep will happen;
- *          only the lower 48 bits are used
- */
-void rtc_sleep_set_wakeup_time(uint64_t t);
-
-
-#define RTC_EXT0_TRIG_EN    BIT(0)  //!< EXT0 GPIO wakeup
-#define RTC_EXT1_TRIG_EN    BIT(1)  //!< EXT1 GPIO wakeup
-#define RTC_GPIO_TRIG_EN    BIT(2)  //!< GPIO wakeup (light sleep only)
-#define RTC_TIMER_TRIG_EN   BIT(3)  //!< Timer wakeup
-#define RTC_SDIO_TRIG_EN    BIT(4)  //!< SDIO wakeup (light sleep only)
-#define RTC_MAC_TRIG_EN     BIT(5)  //!< MAC wakeup (light sleep only)
-#define RTC_UART0_TRIG_EN   BIT(6)  //!< UART0 wakeup (light sleep only)
-#define RTC_UART1_TRIG_EN   BIT(7)  //!< UART1 wakeup (light sleep only)
-#define RTC_TOUCH_TRIG_EN   BIT(8)  //!< Touch wakeup
-#define RTC_ULP_TRIG_EN     BIT(9)  //!< ULP wakeup
-#define RTC_BT_TRIG_EN      BIT(10) //!< BT wakeup (light sleep only)
-
-/**
- * @brief Enter deep or light sleep mode
- *
- * This function enters the sleep mode previously configured using rtc_sleep_init
- * function. Before entering sleep, software should configure wake up sources
- * appropriately (set up GPIO wakeup registers, timer wakeup registers,
- * and so on).
- *
- * If deep sleep mode was configured using rtc_sleep_init, and sleep is not
- * rejected by hardware (based on reject_opt flags), this function never returns.
- * When the chip wakes up from deep sleep, CPU is reset and execution starts
- * from ROM bootloader.
- *
- * If light sleep mode was configured using rtc_sleep_init, this function
- * returns on wakeup, or if sleep is rejected by hardware.
- *
- * @param wakeup_opt  bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
- *                    combined with OR)
- * @param reject_opt  bit mask of sleep reject reasons:
- *                      - RTC_CNTL_GPIO_REJECT_EN
- *                      - RTC_CNTL_SDIO_REJECT_EN
- *                    These flags are used to prevent entering sleep when e.g.
- *                    an external host is communicating via SDIO slave
- * @return non-zero if sleep was rejected by hardware
- */
-uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
-
-/**
- * RTC power and clock control initialization settings
- */
-typedef struct {
-    uint32_t ck8m_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
-    uint32_t xtal_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
-    uint32_t pll_wait : 8;          //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
-    uint32_t clkctl_init : 1;       //!< Perform clock control related initialization
-    uint32_t pwrctl_init : 1;       //!< Perform power control related initialization
-    uint32_t rtc_dboost_fpd : 1;    //!< Force power down RTC_DBOOST
-} rtc_config_t;
-
-/**
- * Default initializer of rtc_config_t.
- *
- * This initializer sets all fields to "reasonable" values (e.g. suggested for
- * production use).
- */
-#define RTC_CONFIG_DEFAULT() {\
-    .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
-    .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
-    .pll_wait  = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
-    .clkctl_init = 1, \
-    .pwrctl_init = 1, \
-    .rtc_dboost_fpd = 1 \
-}
-
-/**
- * Initialize RTC clock and power control related functions
- * @param cfg configuration options as rtc_config_t
- */
-void rtc_init(rtc_config_t cfg);
-
-#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
-#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
-
-/**
- * Structure describing vddsdio configuration
- */
-typedef struct {
-    uint32_t force : 1;     //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
-    uint32_t enable : 1;    //!< Enable VDDSDIO regulator
-    uint32_t tieh  : 1;     //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
-    uint32_t drefh : 2;     //!< Tuning parameter for VDDSDIO regulator
-    uint32_t drefm : 2;     //!< Tuning parameter for VDDSDIO regulator
-    uint32_t drefl : 2;     //!< Tuning parameter for VDDSDIO regulator
-} rtc_vddsdio_config_t;
-
-/**
- * Get current VDDSDIO configuration
- * If VDDSDIO configuration is overridden by RTC, get values from RTC
- * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
- * Otherwise, use default values and the level of MTDI bootstrapping pin.
- * @return currently used VDDSDIO configuration
- */
-rtc_vddsdio_config_t rtc_vddsdio_get_config();
-
-/**
- * Set new VDDSDIO configuration using RTC registers.
- * If config.force == 1, this overrides configuration done using bootstrapping
- * pins and EFUSE.
- *
- * @param config new VDDSDIO configuration
- */
-void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/tools/sdk/include/soc/soc/rtc_cntl_reg.h b/tools/sdk/include/soc/soc/rtc_cntl_reg.h
deleted file mode 100644
index 090b3f7072c..00000000000
--- a/tools/sdk/include/soc/soc/rtc_cntl_reg.h
+++ /dev/null
@@ -1,2072 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_RTC_CNTL_REG_H_
-#define _SOC_RTC_CNTL_REG_H_
-
-/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
-#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
-
-
-#include "soc.h"
-#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)
-/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
-/*description: SW system reset*/
-#define RTC_CNTL_SW_SYS_RST  (BIT(31))
-#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
-#define RTC_CNTL_SW_SYS_RST_V  0x1
-#define RTC_CNTL_SW_SYS_RST_S  31
-/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: digital core force no reset in deep sleep*/
-#define RTC_CNTL_DG_WRAP_FORCE_NORST  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
-/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: digital wrap force reset in deep sleep*/
-#define RTC_CNTL_DG_WRAP_FORCE_RST  (BIT(29))
-#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
-#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
-/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_ANALOG_FORCE_NOISO  (BIT(28))
-#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
-#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
-#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
-/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_PLL_FORCE_NOISO  (BIT(27))
-#define RTC_CNTL_PLL_FORCE_NOISO_M  (BIT(27))
-#define RTC_CNTL_PLL_FORCE_NOISO_V  0x1
-#define RTC_CNTL_PLL_FORCE_NOISO_S  27
-/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_XTL_FORCE_NOISO  (BIT(26))
-#define RTC_CNTL_XTL_FORCE_NOISO_M  (BIT(26))
-#define RTC_CNTL_XTL_FORCE_NOISO_V  0x1
-#define RTC_CNTL_XTL_FORCE_NOISO_S  26
-/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_ANALOG_FORCE_ISO  (BIT(25))
-#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
-#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
-#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
-/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_PLL_FORCE_ISO  (BIT(24))
-#define RTC_CNTL_PLL_FORCE_ISO_M  (BIT(24))
-#define RTC_CNTL_PLL_FORCE_ISO_V  0x1
-#define RTC_CNTL_PLL_FORCE_ISO_S  24
-/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_XTL_FORCE_ISO  (BIT(23))
-#define RTC_CNTL_XTL_FORCE_ISO_M  (BIT(23))
-#define RTC_CNTL_XTL_FORCE_ISO_V  0x1
-#define RTC_CNTL_XTL_FORCE_ISO_S  23
-/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */
-/*description: BIAS_CORE force power up*/
-#define RTC_CNTL_BIAS_CORE_FORCE_PU  (BIT(22))
-#define RTC_CNTL_BIAS_CORE_FORCE_PU_M  (BIT(22))
-#define RTC_CNTL_BIAS_CORE_FORCE_PU_V  0x1
-#define RTC_CNTL_BIAS_CORE_FORCE_PU_S  22
-/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: BIAS_CORE force power down*/
-#define RTC_CNTL_BIAS_CORE_FORCE_PD  (BIT(21))
-#define RTC_CNTL_BIAS_CORE_FORCE_PD_M  (BIT(21))
-#define RTC_CNTL_BIAS_CORE_FORCE_PD_V  0x1
-#define RTC_CNTL_BIAS_CORE_FORCE_PD_S  21
-/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: BIAS_CORE follow CK8M*/
-#define RTC_CNTL_BIAS_CORE_FOLW_8M  (BIT(20))
-#define RTC_CNTL_BIAS_CORE_FOLW_8M_M  (BIT(20))
-#define RTC_CNTL_BIAS_CORE_FOLW_8M_V  0x1
-#define RTC_CNTL_BIAS_CORE_FOLW_8M_S  20
-/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */
-/*description: BIAS_I2C force power up*/
-#define RTC_CNTL_BIAS_I2C_FORCE_PU  (BIT(19))
-#define RTC_CNTL_BIAS_I2C_FORCE_PU_M  (BIT(19))
-#define RTC_CNTL_BIAS_I2C_FORCE_PU_V  0x1
-#define RTC_CNTL_BIAS_I2C_FORCE_PU_S  19
-/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: BIAS_I2C force power down*/
-#define RTC_CNTL_BIAS_I2C_FORCE_PD  (BIT(18))
-#define RTC_CNTL_BIAS_I2C_FORCE_PD_M  (BIT(18))
-#define RTC_CNTL_BIAS_I2C_FORCE_PD_V  0x1
-#define RTC_CNTL_BIAS_I2C_FORCE_PD_S  18
-/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: BIAS_I2C follow CK8M*/
-#define RTC_CNTL_BIAS_I2C_FOLW_8M  (BIT(17))
-#define RTC_CNTL_BIAS_I2C_FOLW_8M_M  (BIT(17))
-#define RTC_CNTL_BIAS_I2C_FOLW_8M_V  0x1
-#define RTC_CNTL_BIAS_I2C_FOLW_8M_S  17
-/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: BIAS_SLEEP force no sleep*/
-#define RTC_CNTL_BIAS_FORCE_NOSLEEP  (BIT(16))
-#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M  (BIT(16))
-#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V  0x1
-#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S  16
-/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: BIAS_SLEEP force sleep*/
-#define RTC_CNTL_BIAS_FORCE_SLEEP  (BIT(15))
-#define RTC_CNTL_BIAS_FORCE_SLEEP_M  (BIT(15))
-#define RTC_CNTL_BIAS_FORCE_SLEEP_V  0x1
-#define RTC_CNTL_BIAS_FORCE_SLEEP_S  15
-/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: BIAS_SLEEP follow CK8M*/
-#define RTC_CNTL_BIAS_SLEEP_FOLW_8M  (BIT(14))
-#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M  (BIT(14))
-#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V  0x1
-#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S  14
-/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */
-/*description: crystall force power up*/
-#define RTC_CNTL_XTL_FORCE_PU  (BIT(13))
-#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
-#define RTC_CNTL_XTL_FORCE_PU_V  0x1
-#define RTC_CNTL_XTL_FORCE_PU_S  13
-/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: crystall force power down*/
-#define RTC_CNTL_XTL_FORCE_PD  (BIT(12))
-#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
-#define RTC_CNTL_XTL_FORCE_PD_V  0x1
-#define RTC_CNTL_XTL_FORCE_PD_S  12
-/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: BB_PLL force power up*/
-#define RTC_CNTL_BBPLL_FORCE_PU  (BIT(11))
-#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
-#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
-#define RTC_CNTL_BBPLL_FORCE_PU_S  11
-/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: BB_PLL force power down*/
-#define RTC_CNTL_BBPLL_FORCE_PD  (BIT(10))
-#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
-#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
-#define RTC_CNTL_BBPLL_FORCE_PD_S  10
-/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: BB_PLL_I2C force power up*/
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU  (BIT(9))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
-/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: BB_PLL _I2C force power down*/
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD  (BIT(8))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
-/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: BB_I2C force power up*/
-#define RTC_CNTL_BB_I2C_FORCE_PU  (BIT(7))
-#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
-#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
-#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
-/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: BB_I2C force power down*/
-#define RTC_CNTL_BB_I2C_FORCE_PD  (BIT(6))
-#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
-#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
-#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
-/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: PRO CPU SW reset*/
-#define RTC_CNTL_SW_PROCPU_RST  (BIT(5))
-#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
-#define RTC_CNTL_SW_PROCPU_RST_V  0x1
-#define RTC_CNTL_SW_PROCPU_RST_S  5
-/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: APP CPU SW reset*/
-#define RTC_CNTL_SW_APPCPU_RST  (BIT(4))
-#define RTC_CNTL_SW_APPCPU_RST_M  (BIT(4))
-#define RTC_CNTL_SW_APPCPU_RST_V  0x1
-#define RTC_CNTL_SW_APPCPU_RST_S  4
-/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: {reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} ==
- 0x86 will stall PRO CPU*/
-#define RTC_CNTL_SW_STALL_PROCPU_C0  0x00000003
-#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
-#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
-#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
-/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: {reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} ==
- 0x86 will stall APP CPU*/
-#define RTC_CNTL_SW_STALL_APPCPU_C0  0x00000003
-#define RTC_CNTL_SW_STALL_APPCPU_C0_M  ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
-#define RTC_CNTL_SW_STALL_APPCPU_C0_V  0x3
-#define RTC_CNTL_SW_STALL_APPCPU_C0_S  0
-
-#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x4)
-/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: RTC sleep timer low 32 bits*/
-#define RTC_CNTL_SLP_VAL_LO  0xFFFFFFFF
-#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
-#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
-#define RTC_CNTL_SLP_VAL_LO_S  0
-
-#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x8)
-/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: timer alarm enable bit*/
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN  (BIT(16))
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
-/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC sleep timer high 16 bits*/
-#define RTC_CNTL_SLP_VAL_HI  0x0000FFFF
-#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
-#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
-#define RTC_CNTL_SLP_VAL_HI_S  0
-
-#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0xc)
-/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Set 1: to update register with RTC timer*/
-#define RTC_CNTL_TIME_UPDATE  (BIT(31))
-#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
-#define RTC_CNTL_TIME_UPDATE_V  0x1
-#define RTC_CNTL_TIME_UPDATE_S  31
-/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: To indicate the register is updated*/
-#define RTC_CNTL_TIME_VALID  (BIT(30))
-#define RTC_CNTL_TIME_VALID_M  (BIT(30))
-#define RTC_CNTL_TIME_VALID_V  0x1
-#define RTC_CNTL_TIME_VALID_S  30
-
-#define RTC_CNTL_TIME0_REG          (DR_REG_RTCCNTL_BASE + 0x10)
-/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: RTC timer low 32 bits*/
-#define RTC_CNTL_TIME_LO  0xFFFFFFFF
-#define RTC_CNTL_TIME_LO_M  ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S))
-#define RTC_CNTL_TIME_LO_V  0xFFFFFFFF
-#define RTC_CNTL_TIME_LO_S  0
-
-#define RTC_CNTL_TIME1_REG          (DR_REG_RTCCNTL_BASE + 0x14)
-/* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC timer high 16 bits*/
-#define RTC_CNTL_TIME_HI  0x0000FFFF
-#define RTC_CNTL_TIME_HI_M  ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S))
-#define RTC_CNTL_TIME_HI_V  0xFFFF
-#define RTC_CNTL_TIME_HI_S  0
-
-#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x18)
-/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: sleep enable bit*/
-#define RTC_CNTL_SLEEP_EN  (BIT(31))
-#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
-#define RTC_CNTL_SLEEP_EN_V  0x1
-#define RTC_CNTL_SLEEP_EN_S  31
-/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: sleep reject bit*/
-#define RTC_CNTL_SLP_REJECT  (BIT(30))
-#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
-#define RTC_CNTL_SLP_REJECT_V  0x1
-#define RTC_CNTL_SLP_REJECT_S  30
-/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: sleep wakeup bit*/
-#define RTC_CNTL_SLP_WAKEUP  (BIT(29))
-#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
-#define RTC_CNTL_SLP_WAKEUP_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_S  29
-/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */
-/*description: SDIO active indication*/
-#define RTC_CNTL_SDIO_ACTIVE_IND  (BIT(28))
-#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
-#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
-#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
-/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: ULP-coprocessor timer enable bit*/
-#define RTC_CNTL_ULP_CP_SLP_TIMER_EN  (BIT(24))
-#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M  (BIT(24))
-#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V  0x1
-#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S  24
-/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: touch timer enable bit*/
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN  (BIT(23))
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M  (BIT(23))
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V  0x1
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S  23
-/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: 1: APB to RTC using bridge   0: APB to RTC using sync*/
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL  (BIT(22))
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
-/* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
-/*description: ULP-coprocessor force wake up*/
-#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN  (BIT(21))
-#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M  (BIT(21))
-#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V  0x1
-#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S  21
-/* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */
-/*description: touch controller force wake up*/
-#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN  (BIT(20))
-#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M  (BIT(20))
-#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V  0x1
-#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S  20
-
-#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x1c)
-/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */
-/*description: PLL wait cycles in slow_clk_rtc*/
-#define RTC_CNTL_PLL_BUF_WAIT  0x000000FF
-#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
-#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
-#define RTC_CNTL_PLL_BUF_WAIT_S  24
-#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
-/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
-/*description: XTAL wait cycles in slow_clk_rtc*/
-#define RTC_CNTL_XTL_BUF_WAIT  0x000003FF
-#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
-#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
-#define RTC_CNTL_XTL_BUF_WAIT_S  14
-#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  20
-/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
-/*description: CK8M wait cycles in slow_clk_rtc*/
-#define RTC_CNTL_CK8M_WAIT  0x000000FF
-#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
-#define RTC_CNTL_CK8M_WAIT_V  0xFF
-#define RTC_CNTL_CK8M_WAIT_S  6
-#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
-/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
-/*description: CPU stall wait cycles in fast_clk_rtc*/
-#define RTC_CNTL_CPU_STALL_WAIT  0x0000001F
-#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
-#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
-#define RTC_CNTL_CPU_STALL_WAIT_S  1
-/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
-/*description: CPU stall enable bit*/
-#define RTC_CNTL_CPU_STALL_EN  (BIT(0))
-#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
-#define RTC_CNTL_CPU_STALL_EN_V  0x1
-#define RTC_CNTL_CPU_STALL_EN_S  0
-
-#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x20)
-/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
-/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/
-#define RTC_CNTL_MIN_TIME_CK8M_OFF  0x000000FF
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
-/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */
-/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller
- start to work*/
-#define RTC_CNTL_ULPCP_TOUCH_START_WAIT  0x000001FF
-#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M  ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S))
-#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V  0x1FF
-#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S  15
-
-#define RTC_CNTL_TIMER3_REG          (DR_REG_RTCCNTL_BASE + 0x24)
-/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */
-/*description: */
-#define RTC_CNTL_ROM_RAM_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M  ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S))
-#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S  25
-/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */
-/*description: */
-#define RTC_CNTL_ROM_RAM_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M  ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S))
-#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S  16
-/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
-/*description: */
-#define RTC_CNTL_WIFI_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_WIFI_POWERUP_TIMER_M  ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S))
-#define RTC_CNTL_WIFI_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_WIFI_POWERUP_TIMER_S  9
-/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
-/*description: */
-#define RTC_CNTL_WIFI_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_WIFI_WAIT_TIMER_M  ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S))
-#define RTC_CNTL_WIFI_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_WIFI_WAIT_TIMER_S  0
-
-#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x28)
-/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
-/*description: */
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
-/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
-/*description: */
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
-/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
-/*description: */
-#define RTC_CNTL_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_POWERUP_TIMER_M  ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S))
-#define RTC_CNTL_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_POWERUP_TIMER_S  9
-/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
-/*description: */
-#define RTC_CNTL_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_WAIT_TIMER_M  ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S))
-#define RTC_CNTL_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_WAIT_TIMER_S  0
-
-#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x2c)
-/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */
-/*description: */
-#define RTC_CNTL_RTCMEM_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M  ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S))
-#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S  25
-/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */
-/*description: */
-#define RTC_CNTL_RTCMEM_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_RTCMEM_WAIT_TIMER_M  ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S))
-#define RTC_CNTL_RTCMEM_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_RTCMEM_WAIT_TIMER_S  16
-/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
-/*description: minimal sleep cycles in slow_clk_rtc*/
-#define RTC_CNTL_MIN_SLP_VAL  0x000000FF
-#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
-#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
-#define RTC_CNTL_MIN_SLP_VAL_S  8
-#define RTC_CNTL_MIN_SLP_VAL_MIN 2
-/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */
-/*description: */
-#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV  0x000000FF
-#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M  ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S))
-#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V  0xFF
-#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S  0
-
-#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x30)
-/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: 1: PLL_I2C power up   otherwise power down*/
-#define RTC_CNTL_PLL_I2C_PU  (BIT(31))
-#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
-#define RTC_CNTL_PLL_I2C_PU_V  0x1
-#define RTC_CNTL_PLL_I2C_PU_S  31
-/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: 1: CKGEN_I2C power up   otherwise power down*/
-#define RTC_CNTL_CKGEN_I2C_PU  (BIT(30))
-#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
-#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
-#define RTC_CNTL_CKGEN_I2C_PU_S  30
-/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: 1: RFRX_PBUS power up   otherwise power down*/
-#define RTC_CNTL_RFRX_PBUS_PU  (BIT(28))
-#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
-#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
-#define RTC_CNTL_RFRX_PBUS_PU_S  28
-/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: 1: TXRF_I2C power up   otherwise power down*/
-#define RTC_CNTL_TXRF_I2C_PU  (BIT(27))
-#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
-#define RTC_CNTL_TXRF_I2C_PU_V  0x1
-#define RTC_CNTL_TXRF_I2C_PU_S  27
-/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1: PVTMON power up   otherwise power down*/
-#define RTC_CNTL_PVTMON_PU  (BIT(26))
-#define RTC_CNTL_PVTMON_PU_M  (BIT(26))
-#define RTC_CNTL_PVTMON_PU_V  0x1
-#define RTC_CNTL_PVTMON_PU_S  26
-/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: start BBPLL calibration during sleep*/
-#define RTC_CNTL_BBPLL_CAL_SLP_START  (BIT(25))
-#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
-#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
-#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
-/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: PLLA force power up*/
-#define RTC_CNTL_PLLA_FORCE_PU  (BIT(24))
-#define RTC_CNTL_PLLA_FORCE_PU_M  (BIT(24))
-#define RTC_CNTL_PLLA_FORCE_PU_V  0x1
-#define RTC_CNTL_PLLA_FORCE_PU_S  24
-/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: PLLA force power down*/
-#define RTC_CNTL_PLLA_FORCE_PD  (BIT(23))
-#define RTC_CNTL_PLLA_FORCE_PD_M  (BIT(23))
-#define RTC_CNTL_PLLA_FORCE_PD_V  0x1
-#define RTC_CNTL_PLLA_FORCE_PD_S  23
-
-#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x34)
-/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: PRO CPU state vector sel*/
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL  (BIT(13))
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M  (BIT(13))
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V  0x1
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S  13
-/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: APP CPU state vector sel*/
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL  (BIT(12))
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M  (BIT(12))
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V  0x1
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S  12
-/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */
-/*description: reset cause of APP CPU*/
-#define RTC_CNTL_RESET_CAUSE_APPCPU  0x0000003F
-#define RTC_CNTL_RESET_CAUSE_APPCPU_M  ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
-#define RTC_CNTL_RESET_CAUSE_APPCPU_V  0x3F
-#define RTC_CNTL_RESET_CAUSE_APPCPU_S  6
-/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
-/*description: reset cause of PRO CPU*/
-#define RTC_CNTL_RESET_CAUSE_PROCPU  0x0000003F
-#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
-#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
-#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
-
-#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x38)
-/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: enable filter for gpio wakeup event*/
-#define RTC_CNTL_GPIO_WAKEUP_FILTER  (BIT(22))
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(22))
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  22
-/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */
-/*description: wakeup enable bitmap*/
-#define RTC_CNTL_WAKEUP_ENA  0x000007FF
-#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
-#define RTC_CNTL_WAKEUP_ENA_V  0x7FF
-#define RTC_CNTL_WAKEUP_ENA_S  11
-/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */
-/*description: wakeup cause*/
-#define RTC_CNTL_WAKEUP_CAUSE  0x000007FF
-#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
-#define RTC_CNTL_WAKEUP_CAUSE_V  0x7FF
-#define RTC_CNTL_WAKEUP_CAUSE_S  0
-
-#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x3c)
-/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA  (BIT(8))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(8))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  8
-/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: enable brown out interrupt*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA  (BIT(7))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(7))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_S  7
-/* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: enable touch interrupt*/
-#define RTC_CNTL_TOUCH_INT_ENA  (BIT(6))
-#define RTC_CNTL_TOUCH_INT_ENA_M  (BIT(6))
-#define RTC_CNTL_TOUCH_INT_ENA_V  0x1
-#define RTC_CNTL_TOUCH_INT_ENA_S  6
-/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: enable ULP-coprocessor interrupt*/
-#define RTC_CNTL_ULP_CP_INT_ENA  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ENA_M  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ENA_V  0x1
-#define RTC_CNTL_ULP_CP_INT_ENA_S  5
-/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: enable RTC time valid interrupt*/
-#define RTC_CNTL_TIME_VALID_INT_ENA  (BIT(4))
-#define RTC_CNTL_TIME_VALID_INT_ENA_M  (BIT(4))
-#define RTC_CNTL_TIME_VALID_INT_ENA_V  0x1
-#define RTC_CNTL_TIME_VALID_INT_ENA_S  4
-/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt*/
-#define RTC_CNTL_WDT_INT_ENA  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: enable SDIO idle interrupt*/
-#define RTC_CNTL_SDIO_IDLE_INT_ENA  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_S  2
-/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
-
-#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x40)
-/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: RTC main timer interrupt raw*/
-#define RTC_CNTL_MAIN_TIMER_INT_RAW  (BIT(8))
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(8))
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  8
-/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: brown out interrupt raw*/
-#define RTC_CNTL_BROWN_OUT_INT_RAW  (BIT(7))
-#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(7))
-#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_RAW_S  7
-/* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: touch interrupt raw*/
-#define RTC_CNTL_TOUCH_INT_RAW  (BIT(6))
-#define RTC_CNTL_TOUCH_INT_RAW_M  (BIT(6))
-#define RTC_CNTL_TOUCH_INT_RAW_V  0x1
-#define RTC_CNTL_TOUCH_INT_RAW_S  6
-/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: ULP-coprocessor interrupt raw*/
-#define RTC_CNTL_ULP_CP_INT_RAW  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_RAW_M  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_RAW_V  0x1
-#define RTC_CNTL_ULP_CP_INT_RAW_S  5
-/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: RTC time valid interrupt raw*/
-#define RTC_CNTL_TIME_VALID_INT_RAW  (BIT(4))
-#define RTC_CNTL_TIME_VALID_INT_RAW_M  (BIT(4))
-#define RTC_CNTL_TIME_VALID_INT_RAW_V  0x1
-#define RTC_CNTL_TIME_VALID_INT_RAW_S  4
-/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC WDT interrupt raw*/
-#define RTC_CNTL_WDT_INT_RAW  (BIT(3))
-#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_RAW_V  0x1
-#define RTC_CNTL_WDT_INT_RAW_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SDIO idle interrupt raw*/
-#define RTC_CNTL_SDIO_IDLE_INT_RAW  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_RAW_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_RAW_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_RAW_S  2
-/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: sleep reject interrupt raw*/
-#define RTC_CNTL_SLP_REJECT_INT_RAW  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: sleep wakeup interrupt raw*/
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
-
-#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x44)
-/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: RTC main timer interrupt state*/
-#define RTC_CNTL_MAIN_TIMER_INT_ST  (BIT(8))
-#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(8))
-#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ST_S  8
-/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: brown out interrupt state*/
-#define RTC_CNTL_BROWN_OUT_INT_ST  (BIT(7))
-#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(7))
-#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ST_S  7
-/* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: touch interrupt state*/
-#define RTC_CNTL_TOUCH_INT_ST  (BIT(6))
-#define RTC_CNTL_TOUCH_INT_ST_M  (BIT(6))
-#define RTC_CNTL_TOUCH_INT_ST_V  0x1
-#define RTC_CNTL_TOUCH_INT_ST_S  6
-/* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: ULP-coprocessor interrupt state*/
-#define RTC_CNTL_SAR_INT_ST  (BIT(5))
-#define RTC_CNTL_SAR_INT_ST_M  (BIT(5))
-#define RTC_CNTL_SAR_INT_ST_V  0x1
-#define RTC_CNTL_SAR_INT_ST_S  5
-/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: RTC time valid interrupt state*/
-#define RTC_CNTL_TIME_VALID_INT_ST  (BIT(4))
-#define RTC_CNTL_TIME_VALID_INT_ST_M  (BIT(4))
-#define RTC_CNTL_TIME_VALID_INT_ST_V  0x1
-#define RTC_CNTL_TIME_VALID_INT_ST_S  4
-/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC WDT interrupt state*/
-#define RTC_CNTL_WDT_INT_ST  (BIT(3))
-#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ST_V  0x1
-#define RTC_CNTL_WDT_INT_ST_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SDIO idle interrupt state*/
-#define RTC_CNTL_SDIO_IDLE_INT_ST  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ST_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ST_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_ST_S  2
-/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: sleep reject interrupt state*/
-#define RTC_CNTL_SLP_REJECT_INT_ST  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: sleep wakeup interrupt state*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ST  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
-
-#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x48)
-/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Clear RTC main timer interrupt state*/
-#define RTC_CNTL_MAIN_TIMER_INT_CLR  (BIT(8))
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(8))
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  8
-/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Clear brown out interrupt state*/
-#define RTC_CNTL_BROWN_OUT_INT_CLR  (BIT(7))
-#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(7))
-#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_CLR_S  7
-/* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Clear touch interrupt state*/
-#define RTC_CNTL_TOUCH_INT_CLR  (BIT(6))
-#define RTC_CNTL_TOUCH_INT_CLR_M  (BIT(6))
-#define RTC_CNTL_TOUCH_INT_CLR_V  0x1
-#define RTC_CNTL_TOUCH_INT_CLR_S  6
-/* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Clear ULP-coprocessor interrupt state*/
-#define RTC_CNTL_SAR_INT_CLR  (BIT(5))
-#define RTC_CNTL_SAR_INT_CLR_M  (BIT(5))
-#define RTC_CNTL_SAR_INT_CLR_V  0x1
-#define RTC_CNTL_SAR_INT_CLR_S  5
-/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Clear RTC time valid interrupt state*/
-#define RTC_CNTL_TIME_VALID_INT_CLR  (BIT(4))
-#define RTC_CNTL_TIME_VALID_INT_CLR_M  (BIT(4))
-#define RTC_CNTL_TIME_VALID_INT_CLR_V  0x1
-#define RTC_CNTL_TIME_VALID_INT_CLR_S  4
-/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Clear RTC WDT interrupt state*/
-#define RTC_CNTL_WDT_INT_CLR  (BIT(3))
-#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_CLR_V  0x1
-#define RTC_CNTL_WDT_INT_CLR_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Clear SDIO idle interrupt state*/
-#define RTC_CNTL_SDIO_IDLE_INT_CLR  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_CLR_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_CLR_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_CLR_S  2
-/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Clear sleep reject interrupt state*/
-#define RTC_CNTL_SLP_REJECT_INT_CLR  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Clear sleep wakeup interrupt state*/
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
-
-#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x4c)
-/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: 32-bit general purpose retention register*/
-#define RTC_CNTL_SCRATCH0  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
-#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH0_S  0
-
-#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x50)
-/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: 32-bit general purpose retention register*/
-#define RTC_CNTL_SCRATCH1  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
-#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH1_S  0
-
-#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x54)
-/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: 32-bit general purpose retention register*/
-#define RTC_CNTL_SCRATCH2  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
-#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH2_S  0
-
-#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x58)
-/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: 32-bit general purpose retention register*/
-#define RTC_CNTL_SCRATCH3  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
-#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH3_S  0
-
-#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x5c)
-/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: enable control XTAL by external pads*/
-#define RTC_CNTL_XTL_EXT_CTR_EN  (BIT(31))
-#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
-#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
-#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
-/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: power down XTAL at high level  1: power down XTAL at low level*/
-#define RTC_CNTL_XTL_EXT_CTR_LV  (BIT(30))
-#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
-#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
-#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
-
-#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x60)
-/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 0: external wakeup at low level  1: external wakeup at high level*/
-#define RTC_CNTL_EXT_WAKEUP1_LV  (BIT(31))
-#define RTC_CNTL_EXT_WAKEUP1_LV_M  (BIT(31))
-#define RTC_CNTL_EXT_WAKEUP1_LV_V  0x1
-#define RTC_CNTL_EXT_WAKEUP1_LV_S  31
-/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: external wakeup at low level  1: external wakeup at high level*/
-#define RTC_CNTL_EXT_WAKEUP0_LV  (BIT(30))
-#define RTC_CNTL_EXT_WAKEUP0_LV_M  (BIT(30))
-#define RTC_CNTL_EXT_WAKEUP0_LV_V  0x1
-#define RTC_CNTL_EXT_WAKEUP0_LV_S  30
-
-#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x64)
-/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */
-/*description: sleep reject cause*/
-#define RTC_CNTL_REJECT_CAUSE  0x0000000F
-#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
-#define RTC_CNTL_REJECT_CAUSE_V  0xF
-#define RTC_CNTL_REJECT_CAUSE_S  28
-/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: enable reject for deep sleep*/
-#define RTC_CNTL_DEEP_SLP_REJECT_EN  (BIT(27))
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(27))
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  27
-/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: enable reject for light sleep*/
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN  (BIT(26))
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(26))
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  26
-/* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: enable SDIO reject*/
-#define RTC_CNTL_SDIO_REJECT_EN  (BIT(25))
-#define RTC_CNTL_SDIO_REJECT_EN_M  (BIT(25))
-#define RTC_CNTL_SDIO_REJECT_EN_V  0x1
-#define RTC_CNTL_SDIO_REJECT_EN_S  25
-/* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: enable GPIO reject*/
-#define RTC_CNTL_GPIO_REJECT_EN  (BIT(24))
-#define RTC_CNTL_GPIO_REJECT_EN_M  (BIT(24))
-#define RTC_CNTL_GPIO_REJECT_EN_V  0x1
-#define RTC_CNTL_GPIO_REJECT_EN_S  24
-
-#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x68)
-/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */
-/*description: CPU period sel*/
-#define RTC_CNTL_CPUPERIOD_SEL  0x00000003
-#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
-#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
-#define RTC_CNTL_CPUPERIOD_SEL_S  30
-/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: CPU sel option*/
-#define RTC_CNTL_CPUSEL_CONF  (BIT(29))
-#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
-#define RTC_CNTL_CPUSEL_CONF_V  0x1
-#define RTC_CNTL_CPUSEL_CONF_S  29
-
-#define RTC_CNTL_SDIO_ACT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x6c)
-/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */
-/*description: */
-#define RTC_CNTL_SDIO_ACT_DNUM  0x000003FF
-#define RTC_CNTL_SDIO_ACT_DNUM_M  ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S))
-#define RTC_CNTL_SDIO_ACT_DNUM_V  0x3FF
-#define RTC_CNTL_SDIO_ACT_DNUM_S  22
-
-#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x70)
-/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: slow_clk_rtc sel. 0: SLOW_CK  1: CK_XTAL_32K  2: CK8M_D256_OUT*/
-#define RTC_CNTL_ANA_CLK_RTC_SEL  0x00000003
-#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
-#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
-#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
-/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: fast_clk_rtc sel. 0: XTAL div 4  1: CK8M*/
-#define RTC_CNTL_FAST_CLK_RTC_SEL  (BIT(29))
-#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
-#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
-#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
-/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
-/*description: SOC clock sel. 0: XTAL  1: PLL  2: CK8M  3: APLL*/
-#define RTC_CNTL_SOC_CLK_SEL  0x00000003
-#define RTC_CNTL_SOC_CLK_SEL_M  ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S))
-#define RTC_CNTL_SOC_CLK_SEL_V  0x3
-#define RTC_CNTL_SOC_CLK_SEL_S  27
-#define RTC_CNTL_SOC_CLK_SEL_XTL    0
-#define RTC_CNTL_SOC_CLK_SEL_PLL    1
-#define RTC_CNTL_SOC_CLK_SEL_8M     2
-#define RTC_CNTL_SOC_CLK_SEL_APLL   3
-/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: CK8M force power up*/
-#define RTC_CNTL_CK8M_FORCE_PU  (BIT(26))
-#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
-#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
-#define RTC_CNTL_CK8M_FORCE_PU_S  26
-/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: CK8M force power down*/
-#define RTC_CNTL_CK8M_FORCE_PD  (BIT(25))
-#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
-#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
-#define RTC_CNTL_CK8M_FORCE_PD_S  25
-/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */
-/*description: CK8M_DFREQ*/
-#define RTC_CNTL_CK8M_DFREQ  0x000000FF
-#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
-#define RTC_CNTL_CK8M_DFREQ_V  0xFF
-#define RTC_CNTL_CK8M_DFREQ_S  17
-#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
-/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: CK8M force no gating during sleep*/
-#define RTC_CNTL_CK8M_FORCE_NOGATING  (BIT(16))
-#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
-#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
-/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: XTAL force no gating during sleep*/
-#define RTC_CNTL_XTAL_FORCE_NOGATING  (BIT(15))
-#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
-#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
-/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */
-/*description: divider = reg_ck8m_div_sel + 1*/
-#define RTC_CNTL_CK8M_DIV_SEL  0x00000007
-#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
-#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
-#define RTC_CNTL_CK8M_DIV_SEL_S  12
-/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_CK8M_DFREQ_FORCE  (BIT(11))
-#define RTC_CNTL_CK8M_DFREQ_FORCE_M  (BIT(11))
-#define RTC_CNTL_CK8M_DFREQ_FORCE_V  0x1
-#define RTC_CNTL_CK8M_DFREQ_FORCE_S  11
-/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: enable CK8M for digital core (no relationship with RTC core)*/
-#define RTC_CNTL_DIG_CLK8M_EN  (BIT(10))
-#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
-#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
-#define RTC_CNTL_DIG_CLK8M_EN_S  10
-/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
-/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
-#define RTC_CNTL_DIG_CLK8M_D256_EN  (BIT(9))
-#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
-#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
-#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
-/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
-#define RTC_CNTL_DIG_XTAL32K_EN  (BIT(8))
-#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
-#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
-#define RTC_CNTL_DIG_XTAL32K_EN_S  8
-/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: 1: CK8M_D256_OUT is actually CK8M  0: CK8M_D256_OUT is CK8M divided by 256*/
-#define RTC_CNTL_ENB_CK8M_DIV  (BIT(7))
-#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
-#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
-#define RTC_CNTL_ENB_CK8M_DIV_S  7
-/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: disable CK8M and CK8M_D256_OUT*/
-#define RTC_CNTL_ENB_CK8M  (BIT(6))
-#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
-#define RTC_CNTL_ENB_CK8M_V  0x1
-#define RTC_CNTL_ENB_CK8M_S  6
-/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
-/*description: CK8M_D256_OUT divider. 00: div128  01: div256  10: div512  11: div1024.*/
-#define RTC_CNTL_CK8M_DIV  0x00000003
-#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
-#define RTC_CNTL_CK8M_DIV_V  0x3
-#define RTC_CNTL_CK8M_DIV_S  4
-
-#define RTC_CNTL_SDIO_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x74)
-/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/
-#define RTC_CNTL_XPD_SDIO_REG  (BIT(31))
-#define RTC_CNTL_XPD_SDIO_REG_M  (BIT(31))
-#define RTC_CNTL_XPD_SDIO_REG_V  0x1
-#define RTC_CNTL_XPD_SDIO_REG_S  31
-/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */
-/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
-#define RTC_CNTL_DREFH_SDIO  0x00000003
-#define RTC_CNTL_DREFH_SDIO_M  ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
-#define RTC_CNTL_DREFH_SDIO_V  0x3
-#define RTC_CNTL_DREFH_SDIO_S  29
-/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
-/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
-#define RTC_CNTL_DREFM_SDIO  0x00000003
-#define RTC_CNTL_DREFM_SDIO_M  ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
-#define RTC_CNTL_DREFM_SDIO_V  0x3
-#define RTC_CNTL_DREFM_SDIO_S  27
-/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
-/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
-#define RTC_CNTL_DREFL_SDIO  0x00000003
-#define RTC_CNTL_DREFL_SDIO_M  ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
-#define RTC_CNTL_DREFL_SDIO_V  0x3
-#define RTC_CNTL_DREFL_SDIO_S  25
-/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
-/*description: read only register for REG1P8_READY*/
-#define RTC_CNTL_REG1P8_READY  (BIT(24))
-#define RTC_CNTL_REG1P8_READY_M  (BIT(24))
-#define RTC_CNTL_REG1P8_READY_V  0x1
-#define RTC_CNTL_REG1P8_READY_S  24
-/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
-/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
-#define RTC_CNTL_SDIO_TIEH  (BIT(23))
-#define RTC_CNTL_SDIO_TIEH_M  (BIT(23))
-#define RTC_CNTL_SDIO_TIEH_V  0x1
-#define RTC_CNTL_SDIO_TIEH_S  23
-/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: 1: use SW option to control SDIO_REG  0: use state machine*/
-#define RTC_CNTL_SDIO_FORCE  (BIT(22))
-#define RTC_CNTL_SDIO_FORCE_M  (BIT(22))
-#define RTC_CNTL_SDIO_FORCE_V  0x1
-#define RTC_CNTL_SDIO_FORCE_S  22
-/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
-/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
-#define RTC_CNTL_SDIO_PD_EN  (BIT(21))
-#define RTC_CNTL_SDIO_PD_EN_M  (BIT(21))
-#define RTC_CNTL_SDIO_PD_EN_V  0x1
-#define RTC_CNTL_SDIO_PD_EN_S  21
-
-#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x78)
-/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: RST_BIAS_I2C*/
-#define RTC_CNTL_RST_BIAS_I2C  (BIT(31))
-#define RTC_CNTL_RST_BIAS_I2C_M  (BIT(31))
-#define RTC_CNTL_RST_BIAS_I2C_V  0x1
-#define RTC_CNTL_RST_BIAS_I2C_S  31
-/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: DEC_HEARTBEAT_WIDTH*/
-#define RTC_CNTL_DEC_HEARTBEAT_WIDTH  (BIT(30))
-#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M  (BIT(30))
-#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V  0x1
-#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S  30
-/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: INC_HEARTBEAT_PERIOD*/
-#define RTC_CNTL_INC_HEARTBEAT_PERIOD  (BIT(29))
-#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M  (BIT(29))
-#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V  0x1
-#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S  29
-/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: DEC_HEARTBEAT_PERIOD*/
-#define RTC_CNTL_DEC_HEARTBEAT_PERIOD  (BIT(28))
-#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M  (BIT(28))
-#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V  0x1
-#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S  28
-/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: INC_HEARTBEAT_REFRESH*/
-#define RTC_CNTL_INC_HEARTBEAT_REFRESH  (BIT(27))
-#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M  (BIT(27))
-#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V  0x1
-#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S  27
-/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: ENB_SCK_XTAL*/
-#define RTC_CNTL_ENB_SCK_XTAL  (BIT(26))
-#define RTC_CNTL_ENB_SCK_XTAL_M  (BIT(26))
-#define RTC_CNTL_ENB_SCK_XTAL_V  0x1
-#define RTC_CNTL_ENB_SCK_XTAL_S  26
-/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */
-/*description: DBG_ATTEN*/
-#define RTC_CNTL_DBG_ATTEN  0x00000003
-#define RTC_CNTL_DBG_ATTEN_M  ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S))
-#define RTC_CNTL_DBG_ATTEN_V  0x3
-#define RTC_CNTL_DBG_ATTEN_S  24
-#define RTC_CNTL_DBG_ATTEN_DEFAULT  3
-#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x7c)
-/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
-/*description: RTC_REG force power up*/
-#define RTC_CNTL_FORCE_PU  (BIT(31))
-#define RTC_CNTL_FORCE_PU_M  (BIT(31))
-#define RTC_CNTL_FORCE_PU_V  0x1
-#define RTC_CNTL_FORCE_PU_S  31
-/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: RTC_REG force power down (for RTC_REG power down means decrease
- the voltage to 0.8v or lower )*/
-#define RTC_CNTL_FORCE_PD  (BIT(30))
-#define RTC_CNTL_FORCE_PD_M  (BIT(30))
-#define RTC_CNTL_FORCE_PD_V  0x1
-#define RTC_CNTL_FORCE_PD_S  30
-/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */
-/*description: RTC_DBOOST force power up*/
-#define RTC_CNTL_DBOOST_FORCE_PU  (BIT(29))
-#define RTC_CNTL_DBOOST_FORCE_PU_M  (BIT(29))
-#define RTC_CNTL_DBOOST_FORCE_PU_V  0x1
-#define RTC_CNTL_DBOOST_FORCE_PU_S  29
-/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: RTC_DBOOST force power down*/
-#define RTC_CNTL_DBOOST_FORCE_PD  (BIT(28))
-#define RTC_CNTL_DBOOST_FORCE_PD_M  (BIT(28))
-#define RTC_CNTL_DBOOST_FORCE_PD_V  0x1
-#define RTC_CNTL_DBOOST_FORCE_PD_S  28
-/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */
-/*description: RTC_DBIAS during wakeup*/
-#define RTC_CNTL_DBIAS_WAK  0x00000007
-#define RTC_CNTL_DBIAS_WAK_M  ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S))
-#define RTC_CNTL_DBIAS_WAK_V  0x7
-#define RTC_CNTL_DBIAS_WAK_S  25
-/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */
-/*description: RTC_DBIAS during sleep*/
-#define RTC_CNTL_DBIAS_SLP  0x00000007
-#define RTC_CNTL_DBIAS_SLP_M  ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S))
-#define RTC_CNTL_DBIAS_SLP_V  0x7
-#define RTC_CNTL_DBIAS_SLP_S  22
-/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
-/*description: SCK_DCAP*/
-#define RTC_CNTL_SCK_DCAP  0x000000FF
-#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
-#define RTC_CNTL_SCK_DCAP_V  0xFF
-#define RTC_CNTL_SCK_DCAP_S  14
-#define RTC_CNTL_SCK_DCAP_DEFAULT   255
-/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */
-/*description: DIG_REG_DBIAS during wakeup*/
-#define RTC_CNTL_DIG_DBIAS_WAK  0x00000007
-#define RTC_CNTL_DIG_DBIAS_WAK_M  ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S))
-#define RTC_CNTL_DIG_DBIAS_WAK_V  0x7
-#define RTC_CNTL_DIG_DBIAS_WAK_S  11
-/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */
-/*description: DIG_REG_DBIAS during sleep*/
-#define RTC_CNTL_DIG_DBIAS_SLP  0x00000007
-#define RTC_CNTL_DIG_DBIAS_SLP_M  ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S))
-#define RTC_CNTL_DIG_DBIAS_SLP_V  0x7
-#define RTC_CNTL_DIG_DBIAS_SLP_S  8
-/* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: N/A*/
-#define RTC_CNTL_SCK_DCAP_FORCE  (BIT(7))
-#define RTC_CNTL_SCK_DCAP_FORCE_M  (BIT(7))
-#define RTC_CNTL_SCK_DCAP_FORCE_V  0x1
-#define RTC_CNTL_SCK_DCAP_FORCE_S  7
-
-/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
- * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
- * Valid if RTC_CNTL_DBG_ATTEN is 0.
- */
-#define RTC_CNTL_DBIAS_0V90 0
-#define RTC_CNTL_DBIAS_0V95 1
-#define RTC_CNTL_DBIAS_1V00 2
-#define RTC_CNTL_DBIAS_1V05 3
-#define RTC_CNTL_DBIAS_1V10 4
-#define RTC_CNTL_DBIAS_1V15 5
-#define RTC_CNTL_DBIAS_1V20 6
-#define RTC_CNTL_DBIAS_1V25 7
-
-#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x80)
-/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: enable power down rtc_peri in sleep*/
-#define RTC_CNTL_PD_EN  (BIT(20))
-#define RTC_CNTL_PD_EN_M  (BIT(20))
-#define RTC_CNTL_PD_EN_V  0x1
-#define RTC_CNTL_PD_EN_S  20
-/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: rtc_peri force power up*/
-#define RTC_CNTL_PWC_FORCE_PU  (BIT(19))
-#define RTC_CNTL_PWC_FORCE_PU_M  (BIT(19))
-#define RTC_CNTL_PWC_FORCE_PU_V  0x1
-#define RTC_CNTL_PWC_FORCE_PU_S  19
-/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: rtc_peri force power down*/
-#define RTC_CNTL_PWC_FORCE_PD  (BIT(18))
-#define RTC_CNTL_PWC_FORCE_PD_M  (BIT(18))
-#define RTC_CNTL_PWC_FORCE_PD_V  0x1
-#define RTC_CNTL_PWC_FORCE_PD_S  18
-/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: enable power down RTC memory in sleep*/
-#define RTC_CNTL_SLOWMEM_PD_EN  (BIT(17))
-#define RTC_CNTL_SLOWMEM_PD_EN_M  (BIT(17))
-#define RTC_CNTL_SLOWMEM_PD_EN_V  0x1
-#define RTC_CNTL_SLOWMEM_PD_EN_S  17
-/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: RTC memory force power up*/
-#define RTC_CNTL_SLOWMEM_FORCE_PU  (BIT(16))
-#define RTC_CNTL_SLOWMEM_FORCE_PU_M  (BIT(16))
-#define RTC_CNTL_SLOWMEM_FORCE_PU_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_PU_S  16
-/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: RTC memory force power down*/
-#define RTC_CNTL_SLOWMEM_FORCE_PD  (BIT(15))
-#define RTC_CNTL_SLOWMEM_FORCE_PD_M  (BIT(15))
-#define RTC_CNTL_SLOWMEM_FORCE_PD_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_PD_S  15
-/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: enable power down fast RTC memory in sleep*/
-#define RTC_CNTL_FASTMEM_PD_EN  (BIT(14))
-#define RTC_CNTL_FASTMEM_PD_EN_M  (BIT(14))
-#define RTC_CNTL_FASTMEM_PD_EN_V  0x1
-#define RTC_CNTL_FASTMEM_PD_EN_S  14
-/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: Fast RTC memory force power up*/
-#define RTC_CNTL_FASTMEM_FORCE_PU  (BIT(13))
-#define RTC_CNTL_FASTMEM_FORCE_PU_M  (BIT(13))
-#define RTC_CNTL_FASTMEM_FORCE_PU_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_PU_S  13
-/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Fast RTC memory force power down*/
-#define RTC_CNTL_FASTMEM_FORCE_PD  (BIT(12))
-#define RTC_CNTL_FASTMEM_FORCE_PD_M  (BIT(12))
-#define RTC_CNTL_FASTMEM_FORCE_PD_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_PD_S  12
-/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: RTC memory force no PD*/
-#define RTC_CNTL_SLOWMEM_FORCE_LPU  (BIT(11))
-#define RTC_CNTL_SLOWMEM_FORCE_LPU_M  (BIT(11))
-#define RTC_CNTL_SLOWMEM_FORCE_LPU_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_LPU_S  11
-/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: RTC memory force PD*/
-#define RTC_CNTL_SLOWMEM_FORCE_LPD  (BIT(10))
-#define RTC_CNTL_SLOWMEM_FORCE_LPD_M  (BIT(10))
-#define RTC_CNTL_SLOWMEM_FORCE_LPD_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_LPD_S  10
-/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: RTC memory  PD following CPU  0: RTC memory PD following RTC state machine*/
-#define RTC_CNTL_SLOWMEM_FOLW_CPU  (BIT(9))
-#define RTC_CNTL_SLOWMEM_FOLW_CPU_M  (BIT(9))
-#define RTC_CNTL_SLOWMEM_FOLW_CPU_V  0x1
-#define RTC_CNTL_SLOWMEM_FOLW_CPU_S  9
-/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: Fast RTC memory force no PD*/
-#define RTC_CNTL_FASTMEM_FORCE_LPU  (BIT(8))
-#define RTC_CNTL_FASTMEM_FORCE_LPU_M  (BIT(8))
-#define RTC_CNTL_FASTMEM_FORCE_LPU_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_LPU_S  8
-/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Fast RTC memory force PD*/
-#define RTC_CNTL_FASTMEM_FORCE_LPD  (BIT(7))
-#define RTC_CNTL_FASTMEM_FORCE_LPD_M  (BIT(7))
-#define RTC_CNTL_FASTMEM_FORCE_LPD_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_LPD_S  7
-/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: 1: Fast RTC memory PD following CPU  0: fast RTC memory PD following
- RTC state machine*/
-#define RTC_CNTL_FASTMEM_FOLW_CPU  (BIT(6))
-#define RTC_CNTL_FASTMEM_FOLW_CPU_M  (BIT(6))
-#define RTC_CNTL_FASTMEM_FOLW_CPU_V  0x1
-#define RTC_CNTL_FASTMEM_FOLW_CPU_S  6
-/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */
-/*description: rtc_peri force no ISO*/
-#define RTC_CNTL_FORCE_NOISO  (BIT(5))
-#define RTC_CNTL_FORCE_NOISO_M  (BIT(5))
-#define RTC_CNTL_FORCE_NOISO_V  0x1
-#define RTC_CNTL_FORCE_NOISO_S  5
-/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: rtc_peri force ISO*/
-#define RTC_CNTL_FORCE_ISO  (BIT(4))
-#define RTC_CNTL_FORCE_ISO_M  (BIT(4))
-#define RTC_CNTL_FORCE_ISO_V  0x1
-#define RTC_CNTL_FORCE_ISO_S  4
-/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC memory force ISO*/
-#define RTC_CNTL_SLOWMEM_FORCE_ISO  (BIT(3))
-#define RTC_CNTL_SLOWMEM_FORCE_ISO_M  (BIT(3))
-#define RTC_CNTL_SLOWMEM_FORCE_ISO_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_ISO_S  3
-/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: RTC memory force no ISO*/
-#define RTC_CNTL_SLOWMEM_FORCE_NOISO  (BIT(2))
-#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M  (BIT(2))
-#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S  2
-/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Fast RTC memory force ISO*/
-#define RTC_CNTL_FASTMEM_FORCE_ISO  (BIT(1))
-#define RTC_CNTL_FASTMEM_FORCE_ISO_M  (BIT(1))
-#define RTC_CNTL_FASTMEM_FORCE_ISO_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_ISO_S  1
-/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Fast RTC memory force no ISO*/
-#define RTC_CNTL_FASTMEM_FORCE_NOISO  (BIT(0))
-#define RTC_CNTL_FASTMEM_FORCE_NOISO_M  (BIT(0))
-#define RTC_CNTL_FASTMEM_FORCE_NOISO_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_NOISO_S  0
-
-/* Useful groups of RTC_CNTL_PWC_REG bits */
-#define RTC_CNTL_MEM_FORCE_ISO    \
-    (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO)
-#define RTC_CNTL_MEM_FORCE_NOISO  \
-    (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
-#define RTC_CNTL_MEM_PD_EN        \
-    (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN)
-#define RTC_CNTL_MEM_FORCE_PU     \
-    (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
-#define RTC_CNTL_MEM_FORCE_PD     \
-    (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD)
-#define RTC_CNTL_MEM_FOLW_CPU     \
-    (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
-#define RTC_CNTL_MEM_FORCE_LPU    \
-    (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU)
-#define RTC_CNTL_MEM_FORCE_LPD    \
-    (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD)
-
-#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x84)
-/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */
-/*description: enable power down digital core in sleep*/
-#define RTC_CNTL_DG_WRAP_PD_EN  (BIT(31))
-#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
-#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
-#define RTC_CNTL_DG_WRAP_PD_EN_S  31
-/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */
-/*description: enable power down wifi in sleep*/
-#define RTC_CNTL_WIFI_PD_EN  (BIT(30))
-#define RTC_CNTL_WIFI_PD_EN_M  (BIT(30))
-#define RTC_CNTL_WIFI_PD_EN_V  0x1
-#define RTC_CNTL_WIFI_PD_EN_S  30
-/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */
-/*description: enable power down internal SRAM 4 in sleep*/
-#define RTC_CNTL_INTER_RAM4_PD_EN  (BIT(29))
-#define RTC_CNTL_INTER_RAM4_PD_EN_M  (BIT(29))
-#define RTC_CNTL_INTER_RAM4_PD_EN_V  0x1
-#define RTC_CNTL_INTER_RAM4_PD_EN_S  29
-/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */
-/*description: enable power down internal SRAM 3 in sleep*/
-#define RTC_CNTL_INTER_RAM3_PD_EN  (BIT(28))
-#define RTC_CNTL_INTER_RAM3_PD_EN_M  (BIT(28))
-#define RTC_CNTL_INTER_RAM3_PD_EN_V  0x1
-#define RTC_CNTL_INTER_RAM3_PD_EN_S  28
-/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */
-/*description: enable power down internal SRAM 2 in sleep*/
-#define RTC_CNTL_INTER_RAM2_PD_EN  (BIT(27))
-#define RTC_CNTL_INTER_RAM2_PD_EN_M  (BIT(27))
-#define RTC_CNTL_INTER_RAM2_PD_EN_V  0x1
-#define RTC_CNTL_INTER_RAM2_PD_EN_S  27
-/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */
-/*description: enable power down internal SRAM 1 in sleep*/
-#define RTC_CNTL_INTER_RAM1_PD_EN  (BIT(26))
-#define RTC_CNTL_INTER_RAM1_PD_EN_M  (BIT(26))
-#define RTC_CNTL_INTER_RAM1_PD_EN_V  0x1
-#define RTC_CNTL_INTER_RAM1_PD_EN_S  26
-/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */
-/*description: enable power down internal SRAM 0 in sleep*/
-#define RTC_CNTL_INTER_RAM0_PD_EN  (BIT(25))
-#define RTC_CNTL_INTER_RAM0_PD_EN_M  (BIT(25))
-#define RTC_CNTL_INTER_RAM0_PD_EN_V  0x1
-#define RTC_CNTL_INTER_RAM0_PD_EN_S  25
-/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */
-/*description: enable power down ROM in sleep*/
-#define RTC_CNTL_ROM0_PD_EN  (BIT(24))
-#define RTC_CNTL_ROM0_PD_EN_M  (BIT(24))
-#define RTC_CNTL_ROM0_PD_EN_V  0x1
-#define RTC_CNTL_ROM0_PD_EN_S  24
-/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */
-/*description: digital core force power up*/
-#define RTC_CNTL_DG_WRAP_FORCE_PU  (BIT(20))
-#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
-#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
-/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: digital core force power down*/
-#define RTC_CNTL_DG_WRAP_FORCE_PD  (BIT(19))
-#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
-#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
-/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
-/*description: wifi force power up*/
-#define RTC_CNTL_WIFI_FORCE_PU  (BIT(18))
-#define RTC_CNTL_WIFI_FORCE_PU_M  (BIT(18))
-#define RTC_CNTL_WIFI_FORCE_PU_V  0x1
-#define RTC_CNTL_WIFI_FORCE_PU_S  18
-/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: wifi force power down*/
-#define RTC_CNTL_WIFI_FORCE_PD  (BIT(17))
-#define RTC_CNTL_WIFI_FORCE_PD_M  (BIT(17))
-#define RTC_CNTL_WIFI_FORCE_PD_V  0x1
-#define RTC_CNTL_WIFI_FORCE_PD_S  17
-/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: internal SRAM 4 force power up*/
-#define RTC_CNTL_INTER_RAM4_FORCE_PU  (BIT(16))
-#define RTC_CNTL_INTER_RAM4_FORCE_PU_M  (BIT(16))
-#define RTC_CNTL_INTER_RAM4_FORCE_PU_V  0x1
-#define RTC_CNTL_INTER_RAM4_FORCE_PU_S  16
-/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: internal SRAM 4 force power down*/
-#define RTC_CNTL_INTER_RAM4_FORCE_PD  (BIT(15))
-#define RTC_CNTL_INTER_RAM4_FORCE_PD_M  (BIT(15))
-#define RTC_CNTL_INTER_RAM4_FORCE_PD_V  0x1
-#define RTC_CNTL_INTER_RAM4_FORCE_PD_S  15
-/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */
-/*description: internal SRAM 3 force power up*/
-#define RTC_CNTL_INTER_RAM3_FORCE_PU  (BIT(14))
-#define RTC_CNTL_INTER_RAM3_FORCE_PU_M  (BIT(14))
-#define RTC_CNTL_INTER_RAM3_FORCE_PU_V  0x1
-#define RTC_CNTL_INTER_RAM3_FORCE_PU_S  14
-/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: internal SRAM 3 force power down*/
-#define RTC_CNTL_INTER_RAM3_FORCE_PD  (BIT(13))
-#define RTC_CNTL_INTER_RAM3_FORCE_PD_M  (BIT(13))
-#define RTC_CNTL_INTER_RAM3_FORCE_PD_V  0x1
-#define RTC_CNTL_INTER_RAM3_FORCE_PD_S  13
-/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
-/*description: internal SRAM 2 force power up*/
-#define RTC_CNTL_INTER_RAM2_FORCE_PU  (BIT(12))
-#define RTC_CNTL_INTER_RAM2_FORCE_PU_M  (BIT(12))
-#define RTC_CNTL_INTER_RAM2_FORCE_PU_V  0x1
-#define RTC_CNTL_INTER_RAM2_FORCE_PU_S  12
-/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: internal SRAM 2 force power down*/
-#define RTC_CNTL_INTER_RAM2_FORCE_PD  (BIT(11))
-#define RTC_CNTL_INTER_RAM2_FORCE_PD_M  (BIT(11))
-#define RTC_CNTL_INTER_RAM2_FORCE_PD_V  0x1
-#define RTC_CNTL_INTER_RAM2_FORCE_PD_S  11
-/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */
-/*description: internal SRAM 1 force power up*/
-#define RTC_CNTL_INTER_RAM1_FORCE_PU  (BIT(10))
-#define RTC_CNTL_INTER_RAM1_FORCE_PU_M  (BIT(10))
-#define RTC_CNTL_INTER_RAM1_FORCE_PU_V  0x1
-#define RTC_CNTL_INTER_RAM1_FORCE_PU_S  10
-/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: internal SRAM 1 force power down*/
-#define RTC_CNTL_INTER_RAM1_FORCE_PD  (BIT(9))
-#define RTC_CNTL_INTER_RAM1_FORCE_PD_M  (BIT(9))
-#define RTC_CNTL_INTER_RAM1_FORCE_PD_V  0x1
-#define RTC_CNTL_INTER_RAM1_FORCE_PD_S  9
-/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */
-/*description: internal SRAM 0 force power up*/
-#define RTC_CNTL_INTER_RAM0_FORCE_PU  (BIT(8))
-#define RTC_CNTL_INTER_RAM0_FORCE_PU_M  (BIT(8))
-#define RTC_CNTL_INTER_RAM0_FORCE_PU_V  0x1
-#define RTC_CNTL_INTER_RAM0_FORCE_PU_S  8
-/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: internal SRAM 0 force power down*/
-#define RTC_CNTL_INTER_RAM0_FORCE_PD  (BIT(7))
-#define RTC_CNTL_INTER_RAM0_FORCE_PD_M  (BIT(7))
-#define RTC_CNTL_INTER_RAM0_FORCE_PD_V  0x1
-#define RTC_CNTL_INTER_RAM0_FORCE_PD_S  7
-/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */
-/*description: ROM force power up*/
-#define RTC_CNTL_ROM0_FORCE_PU  (BIT(6))
-#define RTC_CNTL_ROM0_FORCE_PU_M  (BIT(6))
-#define RTC_CNTL_ROM0_FORCE_PU_V  0x1
-#define RTC_CNTL_ROM0_FORCE_PU_S  6
-/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: ROM force power down*/
-#define RTC_CNTL_ROM0_FORCE_PD  (BIT(5))
-#define RTC_CNTL_ROM0_FORCE_PD_M  (BIT(5))
-#define RTC_CNTL_ROM0_FORCE_PD_V  0x1
-#define RTC_CNTL_ROM0_FORCE_PD_S  5
-/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: memories in digital core force no PD in sleep*/
-#define RTC_CNTL_LSLP_MEM_FORCE_PU  (BIT(4))
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(4))
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  4
-/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: memories in digital core force PD in sleep*/
-#define RTC_CNTL_LSLP_MEM_FORCE_PD  (BIT(3))
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(3))
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  3
-
-/* Useful groups of RTC_CNTL_DIG_PWC_REG bits */
-#define RTC_CNTL_CPU_ROM_RAM_PD_EN \
-    (RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\
-     RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\
-     RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN)
-#define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \
-    (RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\
-     RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\
-     RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU)
-#define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \
-    (RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\
-     RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\
-     RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD
-
-#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x88)
-/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
-/*description: digital core force no ISO*/
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO  (BIT(31))
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
-/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: digital core force ISO*/
-#define RTC_CNTL_DG_WRAP_FORCE_ISO  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
-/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */
-/*description: wifi force no ISO*/
-#define RTC_CNTL_WIFI_FORCE_NOISO  (BIT(29))
-#define RTC_CNTL_WIFI_FORCE_NOISO_M  (BIT(29))
-#define RTC_CNTL_WIFI_FORCE_NOISO_V  0x1
-#define RTC_CNTL_WIFI_FORCE_NOISO_S  29
-/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: wifi force ISO*/
-#define RTC_CNTL_WIFI_FORCE_ISO  (BIT(28))
-#define RTC_CNTL_WIFI_FORCE_ISO_M  (BIT(28))
-#define RTC_CNTL_WIFI_FORCE_ISO_V  0x1
-#define RTC_CNTL_WIFI_FORCE_ISO_S  28
-/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: internal SRAM 4 force no ISO*/
-#define RTC_CNTL_INTER_RAM4_FORCE_NOISO  (BIT(27))
-#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M  (BIT(27))
-#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V  0x1
-#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S  27
-/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: internal SRAM 4 force ISO*/
-#define RTC_CNTL_INTER_RAM4_FORCE_ISO  (BIT(26))
-#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M  (BIT(26))
-#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V  0x1
-#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S  26
-/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */
-/*description: internal SRAM 3 force no ISO*/
-#define RTC_CNTL_INTER_RAM3_FORCE_NOISO  (BIT(25))
-#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M  (BIT(25))
-#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V  0x1
-#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S  25
-/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: internal SRAM 3 force ISO*/
-#define RTC_CNTL_INTER_RAM3_FORCE_ISO  (BIT(24))
-#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M  (BIT(24))
-#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V  0x1
-#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S  24
-/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
-/*description: internal SRAM 2 force no ISO*/
-#define RTC_CNTL_INTER_RAM2_FORCE_NOISO  (BIT(23))
-#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M  (BIT(23))
-#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V  0x1
-#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S  23
-/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: internal SRAM 2 force ISO*/
-#define RTC_CNTL_INTER_RAM2_FORCE_ISO  (BIT(22))
-#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M  (BIT(22))
-#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V  0x1
-#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S  22
-/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */
-/*description: internal SRAM 1 force no ISO*/
-#define RTC_CNTL_INTER_RAM1_FORCE_NOISO  (BIT(21))
-#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M  (BIT(21))
-#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V  0x1
-#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S  21
-/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: internal SRAM 1 force ISO*/
-#define RTC_CNTL_INTER_RAM1_FORCE_ISO  (BIT(20))
-#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M  (BIT(20))
-#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V  0x1
-#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S  20
-/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */
-/*description: internal SRAM 0 force no ISO*/
-#define RTC_CNTL_INTER_RAM0_FORCE_NOISO  (BIT(19))
-#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M  (BIT(19))
-#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V  0x1
-#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S  19
-/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: internal SRAM 0 force ISO*/
-#define RTC_CNTL_INTER_RAM0_FORCE_ISO  (BIT(18))
-#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M  (BIT(18))
-#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V  0x1
-#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S  18
-/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */
-/*description: ROM force no ISO*/
-#define RTC_CNTL_ROM0_FORCE_NOISO  (BIT(17))
-#define RTC_CNTL_ROM0_FORCE_NOISO_M  (BIT(17))
-#define RTC_CNTL_ROM0_FORCE_NOISO_V  0x1
-#define RTC_CNTL_ROM0_FORCE_NOISO_S  17
-/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: ROM force ISO*/
-#define RTC_CNTL_ROM0_FORCE_ISO  (BIT(16))
-#define RTC_CNTL_ROM0_FORCE_ISO_M  (BIT(16))
-#define RTC_CNTL_ROM0_FORCE_ISO_V  0x1
-#define RTC_CNTL_ROM0_FORCE_ISO_S  16
-/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: digital pad force hold*/
-#define RTC_CNTL_DG_PAD_FORCE_HOLD  (BIT(15))
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
-/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */
-/*description: digital pad force un-hold*/
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD  (BIT(14))
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
-/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: digital pad force ISO*/
-#define RTC_CNTL_DG_PAD_FORCE_ISO  (BIT(13))
-#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
-#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
-/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */
-/*description: digital pad force no ISO*/
-#define RTC_CNTL_DG_PAD_FORCE_NOISO  (BIT(12))
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
-/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: digital pad enable auto-hold*/
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN  (BIT(11))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
-/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */
-/*description: wtite only register to clear digital pad auto-hold*/
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD  (BIT(10))
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
-/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
-/*description: read only register to indicate digital pad auto-hold status*/
-#define RTC_CNTL_DG_PAD_AUTOHOLD  (BIT(9))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
-#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
-/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_DIG_ISO_FORCE_ON  (BIT(8))
-#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
-#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
-#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
-/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_DIG_ISO_FORCE_OFF  (BIT(7))
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
-
-/* Useful groups of RTC_CNTL_DIG_ISO_REG bits */
-#define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO   \
-    (RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\
-     RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\
-     RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO)
-#define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \
-    (RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\
-     RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\
-     RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO)
-
-#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x8c)
-/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: enable RTC WDT*/
-#define RTC_CNTL_WDT_EN  (BIT(31))
-#define RTC_CNTL_WDT_EN_M  (BIT(31))
-#define RTC_CNTL_WDT_EN_V  0x1
-#define RTC_CNTL_WDT_EN_S  31
-/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
- stage en  4: RTC reset stage en*/
-#define RTC_CNTL_WDT_STG0  0x00000007
-#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
-#define RTC_CNTL_WDT_STG0_V  0x7
-#define RTC_CNTL_WDT_STG0_S  28
-/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
- stage en  4: RTC reset stage en*/
-#define RTC_CNTL_WDT_STG1  0x00000007
-#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
-#define RTC_CNTL_WDT_STG1_V  0x7
-#define RTC_CNTL_WDT_STG1_S  25
-/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
- stage en  4: RTC reset stage en*/
-#define RTC_CNTL_WDT_STG2  0x00000007
-#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
-#define RTC_CNTL_WDT_STG2_V  0x7
-#define RTC_CNTL_WDT_STG2_S  22
-/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
- stage en  4: RTC reset stage en*/
-#define RTC_CNTL_WDT_STG3  0x00000007
-#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
-#define RTC_CNTL_WDT_STG3_V  0x7
-#define RTC_CNTL_WDT_STG3_S  19
-/* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: N/A*/
-#define RTC_CNTL_WDT_EDGE_INT_EN  (BIT(18))
-#define RTC_CNTL_WDT_EDGE_INT_EN_M  (BIT(18))
-#define RTC_CNTL_WDT_EDGE_INT_EN_V  0x1
-#define RTC_CNTL_WDT_EDGE_INT_EN_S  18
-/* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: N/A*/
-#define RTC_CNTL_WDT_LEVEL_INT_EN  (BIT(17))
-#define RTC_CNTL_WDT_LEVEL_INT_EN_M  (BIT(17))
-#define RTC_CNTL_WDT_LEVEL_INT_EN_V  0x1
-#define RTC_CNTL_WDT_LEVEL_INT_EN_S  17
-/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */
-/*description: CPU reset counter length*/
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH  0x00000007
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  14
-/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */
-/*description: system reset counter length*/
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH  0x00000007
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  11
-/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
-/*description: enable WDT in flash boot*/
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN  (BIT(10))
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(10))
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  10
-/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: enable WDT reset PRO CPU*/
-#define RTC_CNTL_WDT_PROCPU_RESET_EN  (BIT(9))
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(9))
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  9
-/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: enable WDT reset APP CPU*/
-#define RTC_CNTL_WDT_APPCPU_RESET_EN  (BIT(8))
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_M  (BIT(8))
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_S  8
-/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */
-/*description: pause WDT in sleep*/
-#define RTC_CNTL_WDT_PAUSE_IN_SLP  (BIT(7))
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(7))
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  7
-/* RTC_CNTL_WDT_STGX : */
-/*description: stage action selection values */
-#define RTC_WDT_STG_SEL_OFF             0
-#define RTC_WDT_STG_SEL_INT             1
-#define RTC_WDT_STG_SEL_RESET_CPU       2
-#define RTC_WDT_STG_SEL_RESET_SYSTEM    3
-#define RTC_WDT_STG_SEL_RESET_RTC       4
-
-#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x90)
-/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */
-/*description: */
-#define RTC_CNTL_WDT_STG0_HOLD  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
-#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG0_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x94)
-/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
-/*description: */
-#define RTC_CNTL_WDT_STG1_HOLD  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
-#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG1_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x98)
-/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: */
-#define RTC_CNTL_WDT_STG2_HOLD  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
-#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG2_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x9c)
-/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: */
-#define RTC_CNTL_WDT_STG3_HOLD  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
-#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG3_HOLD_S  0
-
-#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0xa0)
-/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_WDT_FEED  (BIT(31))
-#define RTC_CNTL_WDT_FEED_M  (BIT(31))
-#define RTC_CNTL_WDT_FEED_V  0x1
-#define RTC_CNTL_WDT_FEED_S  31
-
-#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xa4)
-/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
-/*description: */
-#define RTC_CNTL_WDT_WKEY  0xFFFFFFFF
-#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
-#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_WKEY_S  0
-
-#define RTC_CNTL_TEST_MUX_REG          (DR_REG_RTCCNTL_BASE + 0xa8)
-/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: DTEST_RTC*/
-#define RTC_CNTL_DTEST_RTC  0x00000003
-#define RTC_CNTL_DTEST_RTC_M  ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S))
-#define RTC_CNTL_DTEST_RTC_V  0x3
-#define RTC_CNTL_DTEST_RTC_S  30
-/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: ENT_RTC*/
-#define RTC_CNTL_ENT_RTC  (BIT(29))
-#define RTC_CNTL_ENT_RTC_M  (BIT(29))
-#define RTC_CNTL_ENT_RTC_V  0x1
-#define RTC_CNTL_ENT_RTC_S  29
-
-#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0xac)
-/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */
-/*description: {reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} ==
- 0x86 will stall PRO CPU*/
-#define RTC_CNTL_SW_STALL_PROCPU_C1  0x0000003F
-#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
-#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
-#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
-/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */
-/*description: {reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} ==
- 0x86 will stall APP CPU*/
-#define RTC_CNTL_SW_STALL_APPCPU_C1  0x0000003F
-#define RTC_CNTL_SW_STALL_APPCPU_C1_M  ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
-#define RTC_CNTL_SW_STALL_APPCPU_C1_V  0x3F
-#define RTC_CNTL_SW_STALL_APPCPU_C1_S  20
-
-#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0xb0)
-/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: 32-bit general purpose retention register*/
-#define RTC_CNTL_SCRATCH4  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
-#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH4_S  0
-
-#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0xb4)
-/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: 32-bit general purpose retention register*/
-#define RTC_CNTL_SCRATCH5  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
-#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH5_S  0
-
-#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0xb8)
-/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: 32-bit general purpose retention register*/
-#define RTC_CNTL_SCRATCH6  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
-#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH6_S  0
-
-#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0xbc)
-/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: 32-bit general purpose retention register*/
-#define RTC_CNTL_SCRATCH7  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
-#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH7_S  0
-
-#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0xc0)
-/* RTC_CNTL_RDY_FOR_WAKEUP : R/0; bitpos:[19]; default: 0 */
-/*description: 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise */
-#define RTC_CNTL_RDY_FOR_WAKEUP  (BIT(19))
-#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
-#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
-#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
-
-/* Compatibility definition */
-#define RTC_CNTL_DIAG0_REG RTC_CNTL_LOW_POWER_ST_REG
-/* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_LOW_POWER_DIAG0  0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG0_M  ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S))
-#define RTC_CNTL_LOW_POWER_DIAG0_V  0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG0_S  0
-
-#define RTC_CNTL_DIAG1_REG          (DR_REG_RTCCNTL_BASE + 0xc4)
-/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_LOW_POWER_DIAG1  0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
-#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG1_S  0
-
-#define RTC_CNTL_HOLD_FORCE_REG          (DR_REG_RTCCNTL_BASE + 0xc8)
-/* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_X32N_HOLD_FORCE  (BIT(17))
-#define RTC_CNTL_X32N_HOLD_FORCE_M  (BIT(17))
-#define RTC_CNTL_X32N_HOLD_FORCE_V  0x1
-#define RTC_CNTL_X32N_HOLD_FORCE_S  17
-/* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_X32P_HOLD_FORCE  (BIT(16))
-#define RTC_CNTL_X32P_HOLD_FORCE_M  (BIT(16))
-#define RTC_CNTL_X32P_HOLD_FORCE_V  0x1
-#define RTC_CNTL_X32P_HOLD_FORCE_S  16
-/* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE  (BIT(15))
-#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M  (BIT(15))
-#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V  0x1
-#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S  15
-/* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE  (BIT(14))
-#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M  (BIT(14))
-#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V  0x1
-#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S  14
-/* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE  (BIT(13))
-#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M  (BIT(13))
-#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V  0x1
-#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S  13
-/* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE  (BIT(12))
-#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M  (BIT(12))
-#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V  0x1
-#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S  12
-/* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE  (BIT(11))
-#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M  (BIT(11))
-#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V  0x1
-#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S  11
-/* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE  (BIT(10))
-#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M  (BIT(10))
-#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V  0x1
-#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S  10
-/* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE  (BIT(9))
-#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M  (BIT(9))
-#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V  0x1
-#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S  9
-/* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE  (BIT(8))
-#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M  (BIT(8))
-#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V  0x1
-#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S  8
-/* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_SENSE4_HOLD_FORCE  (BIT(7))
-#define RTC_CNTL_SENSE4_HOLD_FORCE_M  (BIT(7))
-#define RTC_CNTL_SENSE4_HOLD_FORCE_V  0x1
-#define RTC_CNTL_SENSE4_HOLD_FORCE_S  7
-/* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_SENSE3_HOLD_FORCE  (BIT(6))
-#define RTC_CNTL_SENSE3_HOLD_FORCE_M  (BIT(6))
-#define RTC_CNTL_SENSE3_HOLD_FORCE_V  0x1
-#define RTC_CNTL_SENSE3_HOLD_FORCE_S  6
-/* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_SENSE2_HOLD_FORCE  (BIT(5))
-#define RTC_CNTL_SENSE2_HOLD_FORCE_M  (BIT(5))
-#define RTC_CNTL_SENSE2_HOLD_FORCE_V  0x1
-#define RTC_CNTL_SENSE2_HOLD_FORCE_S  5
-/* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_SENSE1_HOLD_FORCE  (BIT(4))
-#define RTC_CNTL_SENSE1_HOLD_FORCE_M  (BIT(4))
-#define RTC_CNTL_SENSE1_HOLD_FORCE_V  0x1
-#define RTC_CNTL_SENSE1_HOLD_FORCE_S  4
-/* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_PDAC2_HOLD_FORCE  (BIT(3))
-#define RTC_CNTL_PDAC2_HOLD_FORCE_M  (BIT(3))
-#define RTC_CNTL_PDAC2_HOLD_FORCE_V  0x1
-#define RTC_CNTL_PDAC2_HOLD_FORCE_S  3
-/* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_PDAC1_HOLD_FORCE  (BIT(2))
-#define RTC_CNTL_PDAC1_HOLD_FORCE_M  (BIT(2))
-#define RTC_CNTL_PDAC1_HOLD_FORCE_V  0x1
-#define RTC_CNTL_PDAC1_HOLD_FORCE_S  2
-/* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_ADC2_HOLD_FORCE  (BIT(1))
-#define RTC_CNTL_ADC2_HOLD_FORCE_M  (BIT(1))
-#define RTC_CNTL_ADC2_HOLD_FORCE_V  0x1
-#define RTC_CNTL_ADC2_HOLD_FORCE_S  1
-/* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_ADC1_HOLD_FORCE  (BIT(0))
-#define RTC_CNTL_ADC1_HOLD_FORCE_M  (BIT(0))
-#define RTC_CNTL_ADC1_HOLD_FORCE_V  0x1
-#define RTC_CNTL_ADC1_HOLD_FORCE_S  0
-
-#define RTC_CNTL_EXT_WAKEUP1_REG          (DR_REG_RTCCNTL_BASE + 0xcc)
-/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */
-/*description: clear ext wakeup1 status*/
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR  (BIT(18))
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M  (BIT(18))
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V  0x1
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S  18
-/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: Bitmap to select RTC pads for ext wakeup1*/
-#define RTC_CNTL_EXT_WAKEUP1_SEL  0x0003FFFF
-#define RTC_CNTL_EXT_WAKEUP1_SEL_M  ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S))
-#define RTC_CNTL_EXT_WAKEUP1_SEL_V  0x3FFFF
-#define RTC_CNTL_EXT_WAKEUP1_SEL_S  0
-
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG          (DR_REG_RTCCNTL_BASE + 0xd0)
-/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: ext wakeup1 status*/
-#define RTC_CNTL_EXT_WAKEUP1_STATUS  0x0003FFFF
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_M  ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S))
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_V  0x3FFFF
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_S  0
-
-#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0xd4)
-/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: brown out detect*/
-#define RTC_CNTL_BROWN_OUT_DET  (BIT(31))
-#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
-#define RTC_CNTL_BROWN_OUT_DET_V  0x1
-#define RTC_CNTL_BROWN_OUT_DET_S  31
-/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: enable brown out*/
-#define RTC_CNTL_BROWN_OUT_ENA  (BIT(30))
-#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
-#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_ENA_S  30
-/* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */
-/*description: brown out threshold*/
-#define RTC_CNTL_DBROWN_OUT_THRES  0x00000007
-#define RTC_CNTL_DBROWN_OUT_THRES_M  ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S))
-#define RTC_CNTL_DBROWN_OUT_THRES_V  0x7
-#define RTC_CNTL_DBROWN_OUT_THRES_S  27
-/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: enable brown out reset*/
-#define RTC_CNTL_BROWN_OUT_RST_ENA  (BIT(26))
-#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
-#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
-/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */
-/*description: brown out reset wait cycles*/
-#define RTC_CNTL_BROWN_OUT_RST_WAIT  0x000003FF
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
-/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable power down RF when brown out happens*/
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA  (BIT(15))
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
-/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: enable close flash when brown out happens*/
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA  (BIT(14))
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
-
-#define RTC_MEM_CONF            (DR_REG_RTCCNTL_BASE + 0x40 * 4)
-#define RTC_MEM_CRC_FINISH      (BIT(31))
-#define RTC_MEM_CRC_FINISH_M    (BIT(31))
-#define RTC_MEM_CRC_FINISH_V    0x1
-#define RTC_MEM_CRC_FINISH_S    (31)
-#define RTC_MEM_CRC_LEN         (0x7ff)
-#define RTC_MEM_CRC_LEN_M       ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S))
-#define RTC_MEM_CRC_LEN_V       (0x7ff)
-#define RTC_MEM_CRC_LEN_S       (20)
-#define RTC_MEM_CRC_ADDR        (0x7ff)
-#define RTC_MEM_CRC_ADDR_M      ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S))
-#define RTC_MEM_CRC_ADDR_V      (0x7ff)
-#define RTC_MEM_CRC_ADDR_S      (9)
-#define RTC_MEM_CRC_START       (BIT(8))
-#define RTC_MEM_CRC_START_M     (BIT(8))
-#define RTC_MEM_CRC_START_V     0x1
-#define RTC_MEM_CRC_START_S     (8)
-#define RTC_MEM_PID_CONF        (0xff)
-#define RTC_MEM_PID_CONF_M      (0xff)
-#define RTC_MEM_PID_CONF_V      (0xff)
-#define RTC_MEM_PID_CONF_S      (0)
-
-#define RTC_MEM_CRC_RES         (DR_REG_RTCCNTL_BASE + 0x41 * 4)
-
-#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x13c)
-/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */
-/*description: */
-#define RTC_CNTL_CNTL_DATE  0x0FFFFFFF
-#define RTC_CNTL_CNTL_DATE_M  ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S))
-#define RTC_CNTL_CNTL_DATE_V  0xFFFFFFF
-#define RTC_CNTL_CNTL_DATE_S  0
-#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280
-
-
-
-
-#endif /*_SOC_RTC_CNTL_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/rtc_cntl_struct.h b/tools/sdk/include/soc/soc/rtc_cntl_struct.h
deleted file mode 100644
index 17a2d180382..00000000000
--- a/tools/sdk/include/soc/soc/rtc_cntl_struct.h
+++ /dev/null
@@ -1,566 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_RTC_CNTL_STRUCT_H_
-#define _SOC_RTC_CNTL_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t sw_stall_appcpu_c0:  2;             /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]}  == 0x86 will stall APP CPU*/
-            uint32_t sw_stall_procpu_c0:  2;             /*{reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]}  == 0x86 will stall PRO CPU*/
-            uint32_t sw_appcpu_rst:       1;             /*APP CPU SW reset*/
-            uint32_t sw_procpu_rst:       1;             /*PRO CPU SW reset*/
-            uint32_t bb_i2c_force_pd:     1;             /*BB_I2C force power down*/
-            uint32_t bb_i2c_force_pu:     1;             /*BB_I2C force power up*/
-            uint32_t bbpll_i2c_force_pd:  1;             /*BB_PLL _I2C force power down*/
-            uint32_t bbpll_i2c_force_pu:  1;             /*BB_PLL_I2C force power up*/
-            uint32_t bbpll_force_pd:      1;             /*BB_PLL force power down*/
-            uint32_t bbpll_force_pu:      1;             /*BB_PLL force power up*/
-            uint32_t xtl_force_pd:        1;             /*crystall force power down*/
-            uint32_t xtl_force_pu:        1;             /*crystall force power up*/
-            uint32_t bias_sleep_folw_8m:  1;             /*BIAS_SLEEP follow CK8M*/
-            uint32_t bias_force_sleep:    1;             /*BIAS_SLEEP force sleep*/
-            uint32_t bias_force_nosleep:  1;             /*BIAS_SLEEP force no sleep*/
-            uint32_t bias_i2c_folw_8m:    1;             /*BIAS_I2C follow CK8M*/
-            uint32_t bias_i2c_force_pd:   1;             /*BIAS_I2C force power down*/
-            uint32_t bias_i2c_force_pu:   1;             /*BIAS_I2C force power up*/
-            uint32_t bias_core_folw_8m:   1;             /*BIAS_CORE follow CK8M*/
-            uint32_t bias_core_force_pd:  1;             /*BIAS_CORE force power down*/
-            uint32_t bias_core_force_pu:  1;             /*BIAS_CORE force power up*/
-            uint32_t xtl_force_iso:       1;
-            uint32_t pll_force_iso:       1;
-            uint32_t analog_force_iso:    1;
-            uint32_t xtl_force_noiso:     1;
-            uint32_t pll_force_noiso:     1;
-            uint32_t analog_force_noiso:  1;
-            uint32_t dg_wrap_force_rst:   1;             /*digital wrap force reset in deep sleep*/
-            uint32_t dg_wrap_force_norst: 1;             /*digital core force no reset in deep sleep*/
-            uint32_t sw_sys_rst:          1;             /*SW system reset*/
-        };
-        uint32_t val;
-    } options0;
-    uint32_t slp_timer0;                             /*RTC sleep timer low 32 bits*/
-    union {
-        struct {
-            uint32_t slp_val_hi:             16;         /*RTC sleep timer high 16 bits*/
-            uint32_t main_timer_alarm_en: 1;         /*timer alarm enable bit*/
-            uint32_t reserved17:             15;
-        };
-        uint32_t val;
-    } slp_timer1;
-    union {
-        struct {
-            uint32_t reserved0:      30;
-            uint32_t valid:  1;                 /*To indicate the register is updated*/
-            uint32_t update: 1;                 /*Set 1: to update register with RTC timer*/
-        };
-        uint32_t val;
-    } time_update;
-    uint32_t time0;                                  /*RTC timer low 32 bits*/
-    union {
-        struct {
-            uint32_t time_hi:16;                     /*RTC timer high 16 bits*/
-            uint32_t reserved16: 16;
-        };
-        uint32_t val;
-    } time1;
-    union {
-        struct {
-            uint32_t reserved0:             20;
-            uint32_t touch_wakeup_force_en:  1;          /*touch controller force wake up*/
-            uint32_t ulp_cp_wakeup_force_en: 1;          /*ULP-coprocessor force wake up*/
-            uint32_t apb2rtc_bridge_sel:     1;          /*1: APB to RTC using bridge   0: APB to RTC using sync*/
-            uint32_t touch_slp_timer_en:     1;          /*touch timer enable bit*/
-            uint32_t ulp_cp_slp_timer_en:    1;          /*ULP-coprocessor timer enable bit*/
-            uint32_t reserved25:             3;
-            uint32_t sdio_active_ind:        1;          /*SDIO active indication*/
-            uint32_t slp_wakeup:             1;          /*sleep wakeup bit*/
-            uint32_t slp_reject:             1;          /*sleep reject bit*/
-            uint32_t sleep_en:               1;          /*sleep enable bit*/
-        };
-        uint32_t val;
-    } state0;
-    union {
-        struct {
-            uint32_t cpu_stall_en:   1;                  /*CPU stall enable bit*/
-            uint32_t cpu_stall_wait: 5;                  /*CPU stall wait cycles in fast_clk_rtc*/
-            uint32_t ck8m_wait:      8;                  /*CK8M wait cycles in slow_clk_rtc*/
-            uint32_t xtl_buf_wait:  10;                  /*XTAL wait cycles in slow_clk_rtc*/
-            uint32_t pll_buf_wait:   8;                  /*PLL wait cycles in slow_clk_rtc*/
-        };
-        uint32_t val;
-    } timer1;
-    union {
-        struct {
-            uint32_t reserved0:             15;
-            uint32_t ulpcp_touch_start_wait: 9;          /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/
-            uint32_t min_time_ck8m_off:      8;          /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
-        };
-        uint32_t val;
-    } timer2;
-    union {
-        struct {
-            uint32_t wifi_wait_timer:       9;
-            uint32_t wifi_powerup_timer:    7;
-            uint32_t rom_ram_wait_timer:    9;
-            uint32_t rom_ram_powerup_timer: 7;
-        };
-        uint32_t val;
-    } timer3;
-    union {
-        struct {
-            uint32_t rtc_wait_timer:        9;
-            uint32_t rtc_powerup_timer:     7;
-            uint32_t dg_wrap_wait_timer:    9;
-            uint32_t dg_wrap_powerup_timer: 7;
-        };
-        uint32_t val;
-    } timer4;
-    union {
-        struct {
-            uint32_t ulp_cp_subtimer_prediv: 8;
-            uint32_t min_slp_val:            8;          /*minimal sleep cycles in slow_clk_rtc*/
-            uint32_t rtcmem_wait_timer:      9;
-            uint32_t rtcmem_powerup_timer:   7;
-        };
-        uint32_t val;
-    } timer5;
-    union {
-        struct {
-            uint32_t reserved0:          23;
-            uint32_t plla_force_pd:       1;             /*PLLA force power down*/
-            uint32_t plla_force_pu:       1;             /*PLLA force power up*/
-            uint32_t bbpll_cal_slp_start: 1;             /*start BBPLL calibration during sleep*/
-            uint32_t pvtmon_pu:           1;             /*1: PVTMON power up   otherwise power down*/
-            uint32_t txrf_i2c_pu:         1;             /*1: TXRF_I2C power up   otherwise power down*/
-            uint32_t rfrx_pbus_pu:        1;             /*1: RFRX_PBUS power up   otherwise power down*/
-            uint32_t reserved29:          1;
-            uint32_t ckgen_i2c_pu:        1;             /*1: CKGEN_I2C power up   otherwise power down*/
-            uint32_t pll_i2c_pu:          1;             /*1: PLL_I2C power up   otherwise power down*/
-        };
-        uint32_t val;
-    } ana_conf;
-    union {
-        struct {
-            uint32_t reset_cause_procpu:     6;          /*reset cause of PRO CPU*/
-            uint32_t reset_cause_appcpu:     6;          /*reset cause of APP CPU*/
-            uint32_t appcpu_stat_vector_sel: 1;          /*APP CPU state vector sel*/
-            uint32_t procpu_stat_vector_sel: 1;          /*PRO CPU state vector sel*/
-            uint32_t reserved14:            18;
-        };
-        uint32_t val;
-    } reset_state;
-    union {
-        struct {
-            uint32_t wakeup_cause:      11;              /*wakeup cause*/
-            uint32_t rtc_wakeup_ena:    11;              /*wakeup enable bitmap*/
-            uint32_t gpio_wakeup_filter: 1;              /*enable filter for gpio wakeup event*/
-            uint32_t reserved23:         9;
-        };
-        uint32_t val;
-    } wakeup_state;
-    union {
-        struct {
-            uint32_t slp_wakeup:     1;          /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject:     1;          /*enable sleep reject interrupt*/
-            uint32_t sdio_idle:      1;          /*enable SDIO idle interrupt*/
-            uint32_t rtc_wdt:        1;          /*enable RTC WDT interrupt*/
-            uint32_t rtc_time_valid: 1;          /*enable RTC time valid interrupt*/
-            uint32_t rtc_ulp_cp:     1;          /*enable ULP-coprocessor interrupt*/
-            uint32_t rtc_touch:      1;          /*enable touch interrupt*/
-            uint32_t rtc_brown_out:  1;          /*enable brown out interrupt*/
-            uint32_t rtc_main_timer: 1;          /*enable RTC main timer interrupt*/
-            uint32_t reserved9:             23;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t slp_wakeup:     1;          /*sleep wakeup interrupt raw*/
-            uint32_t slp_reject:     1;          /*sleep reject interrupt raw*/
-            uint32_t sdio_idle:      1;          /*SDIO idle interrupt raw*/
-            uint32_t rtc_wdt:        1;          /*RTC WDT interrupt raw*/
-            uint32_t rtc_time_valid: 1;          /*RTC time valid interrupt raw*/
-            uint32_t rtc_ulp_cp:     1;          /*ULP-coprocessor interrupt raw*/
-            uint32_t rtc_touch:      1;          /*touch interrupt raw*/
-            uint32_t rtc_brown_out:  1;          /*brown out interrupt raw*/
-            uint32_t rtc_main_timer: 1;          /*RTC main timer interrupt raw*/
-            uint32_t reserved9:             23;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t slp_wakeup:     1;           /*sleep wakeup interrupt state*/
-            uint32_t slp_reject:     1;           /*sleep reject interrupt state*/
-            uint32_t sdio_idle:      1;           /*SDIO idle interrupt state*/
-            uint32_t rtc_wdt:        1;           /*RTC WDT interrupt state*/
-            uint32_t rtc_time_valid: 1;           /*RTC time valid interrupt state*/
-            uint32_t rtc_sar:        1;           /*ULP-coprocessor interrupt state*/
-            uint32_t rtc_touch:      1;           /*touch interrupt state*/
-            uint32_t rtc_brown_out:  1;           /*brown out interrupt state*/
-            uint32_t rtc_main_timer: 1;           /*RTC main timer interrupt state*/
-            uint32_t reserved9:            23;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t slp_wakeup:     1;          /*Clear sleep wakeup interrupt state*/
-            uint32_t slp_reject:     1;          /*Clear sleep reject interrupt state*/
-            uint32_t sdio_idle:      1;          /*Clear SDIO idle interrupt state*/
-            uint32_t rtc_wdt:        1;          /*Clear RTC WDT interrupt state*/
-            uint32_t rtc_time_valid: 1;          /*Clear RTC time valid interrupt state*/
-            uint32_t rtc_sar:        1;          /*Clear ULP-coprocessor interrupt state*/
-            uint32_t rtc_touch:      1;          /*Clear touch interrupt state*/
-            uint32_t rtc_brown_out:  1;          /*Clear brown out interrupt state*/
-            uint32_t rtc_main_timer: 1;          /*Clear RTC main timer interrupt state*/
-            uint32_t reserved9:             23;
-        };
-        uint32_t val;
-    } int_clr;
-    uint32_t rtc_store0;                                 /*32-bit general purpose retention register*/
-    uint32_t rtc_store1;                                 /*32-bit general purpose retention register*/
-    uint32_t rtc_store2;                                 /*32-bit general purpose retention register*/
-    uint32_t rtc_store3;                                 /*32-bit general purpose retention register*/
-    union {
-        struct {
-            uint32_t reserved0:     30;
-            uint32_t ctr_lv: 1;                  /*0: power down XTAL at high level  1: power down XTAL at low level*/
-            uint32_t ctr_en: 1;                  /*enable control XTAL by external pads*/
-        };
-        uint32_t val;
-    } ext_xtl_conf;
-    union {
-        struct {
-            uint32_t reserved0:     30;
-            uint32_t wakeup0_lv: 1;                  /*0: external wakeup at low level  1: external wakeup at high level*/
-            uint32_t wakeup1_lv: 1;                  /*0: external wakeup at low level  1: external wakeup at high level*/
-        };
-        uint32_t val;
-    } ext_wakeup_conf;
-    union {
-        struct {
-            uint32_t reserved0:          24;
-            uint32_t gpio_reject_en:      1;             /*enable GPIO reject*/
-            uint32_t sdio_reject_en:      1;             /*enable SDIO reject*/
-            uint32_t light_slp_reject_en: 1;             /*enable reject for light sleep*/
-            uint32_t deep_slp_reject_en:  1;             /*enable reject for deep sleep*/
-            uint32_t reject_cause:        4;             /*sleep reject cause*/
-        };
-        uint32_t val;
-    } slp_reject_conf;
-    union {
-        struct {
-            uint32_t reserved0:        29;
-            uint32_t cpusel_conf:   1;               /*CPU sel option*/
-            uint32_t cpuperiod_sel: 2;               /*CPU period sel*/
-        };
-        uint32_t val;
-    } cpu_period_conf;
-    union {
-        struct {
-            uint32_t reserved0:    22;
-            uint32_t sdio_act_dnum:10;
-        };
-        uint32_t val;
-    } sdio_act_conf;
-    union {
-        struct {
-            uint32_t reserved0:           4;
-            uint32_t ck8m_div:            2;             /*CK8M_D256_OUT divider. 00: div128  01: div256  10: div512  11: div1024.*/
-            uint32_t enb_ck8m:            1;             /*disable CK8M and CK8M_D256_OUT*/
-            uint32_t enb_ck8m_div:        1;             /*1: CK8M_D256_OUT is actually CK8M  0: CK8M_D256_OUT is CK8M divided by 256*/
-            uint32_t dig_xtal32k_en:      1;             /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
-            uint32_t dig_clk8m_d256_en:   1;             /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
-            uint32_t dig_clk8m_en:        1;             /*enable CK8M for digital core (no relationship with RTC core)*/
-            uint32_t ck8m_dfreq_force:    1;
-            uint32_t ck8m_div_sel:        3;             /*divider = reg_ck8m_div_sel + 1*/
-            uint32_t xtal_force_nogating: 1;             /*XTAL force no gating during sleep*/
-            uint32_t ck8m_force_nogating: 1;             /*CK8M force no gating during sleep*/
-            uint32_t ck8m_dfreq:          8;             /*CK8M_DFREQ*/
-            uint32_t ck8m_force_pd:       1;             /*CK8M force power down*/
-            uint32_t ck8m_force_pu:       1;             /*CK8M force power up*/
-            uint32_t soc_clk_sel:         2;             /*SOC clock sel. 0: XTAL  1: PLL  2: CK8M  3: APLL*/
-            uint32_t fast_clk_rtc_sel:    1;             /*fast_clk_rtc sel. 0: XTAL div 4  1: CK8M*/
-            uint32_t ana_clk_rtc_sel:     2;             /*slow_clk_rtc sel. 0: SLOW_CK  1: CK_XTAL_32K  2: CK8M_D256_OUT*/
-        };
-        uint32_t val;
-    } clk_conf;
-    union {
-        struct {
-            uint32_t reserved0:   21;
-            uint32_t sdio_pd_en:   1;                    /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
-            uint32_t sdio_force:   1;                    /*1: use SW option to control SDIO_REG  0: use state machine*/
-            uint32_t sdio_tieh:    1;                    /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
-            uint32_t reg1p8_ready: 1;                    /*read only register for REG1P8_READY*/
-            uint32_t drefl_sdio:   2;                    /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t drefm_sdio:   2;                    /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t drefh_sdio:   2;                    /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t xpd_sdio:     1;                    /*SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/
-        };
-        uint32_t val;
-    } sdio_conf;
-    union {
-        struct {
-            uint32_t reserved0:            24;
-            uint32_t dbg_atten:             2;           /*DBG_ATTEN*/
-            uint32_t enb_sck_xtal:          1;           /*ENB_SCK_XTAL*/
-            uint32_t inc_heartbeat_refresh: 1;           /*INC_HEARTBEAT_REFRESH*/
-            uint32_t dec_heartbeat_period:  1;           /*DEC_HEARTBEAT_PERIOD*/
-            uint32_t inc_heartbeat_period:  1;           /*INC_HEARTBEAT_PERIOD*/
-            uint32_t dec_heartbeat_width:   1;           /*DEC_HEARTBEAT_WIDTH*/
-            uint32_t rst_bias_i2c:          1;           /*RST_BIAS_I2C*/
-        };
-        uint32_t val;
-    } bias_conf;
-    union {
-        struct {
-            uint32_t reserved0:           7;
-            uint32_t sck_dcap_force:      1;             /*N/A*/
-            uint32_t dig_dbias_slp:       3;             /*DIG_REG_DBIAS during sleep*/
-            uint32_t dig_dbias_wak:       3;             /*DIG_REG_DBIAS during wakeup*/
-            uint32_t sck_dcap:            8;             /*SCK_DCAP*/
-            uint32_t rtc_dbias_slp:       3;             /*RTC_DBIAS during sleep*/
-            uint32_t rtc_dbias_wak:       3;             /*RTC_DBIAS during wakeup*/
-            uint32_t rtc_dboost_force_pd: 1;             /*RTC_DBOOST force power down*/
-            uint32_t rtc_dboost_force_pu: 1;             /*RTC_DBOOST force power up*/
-            uint32_t rtc_force_pd:        1;             /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
-            uint32_t rtc_force_pu:        1;             /*RTC_REG force power up*/
-        };
-        uint32_t val;
-    } rtc;
-    union {
-        struct {
-            uint32_t fastmem_force_noiso: 1;         /*Fast RTC memory force no ISO*/
-            uint32_t fastmem_force_iso:   1;         /*Fast RTC memory force ISO*/
-            uint32_t slowmem_force_noiso: 1;         /*RTC memory force no ISO*/
-            uint32_t slowmem_force_iso:   1;         /*RTC memory force ISO*/
-            uint32_t rtc_force_iso:           1;         /*rtc_peri force ISO*/
-            uint32_t force_noiso:         1;         /*rtc_peri force no ISO*/
-            uint32_t fastmem_folw_cpu:    1;         /*1: Fast RTC memory PD following CPU  0: fast RTC memory PD following RTC state machine*/
-            uint32_t fastmem_force_lpd:   1;         /*Fast RTC memory force PD*/
-            uint32_t fastmem_force_lpu:   1;         /*Fast RTC memory force no PD*/
-            uint32_t slowmem_folw_cpu:    1;         /*1: RTC memory  PD following CPU  0: RTC memory PD following RTC state machine*/
-            uint32_t slowmem_force_lpd:   1;         /*RTC memory force PD*/
-            uint32_t slowmem_force_lpu:   1;         /*RTC memory force no PD*/
-            uint32_t fastmem_force_pd:    1;         /*Fast RTC memory force power down*/
-            uint32_t fastmem_force_pu:    1;         /*Fast RTC memory force power up*/
-            uint32_t fastmem_pd_en:       1;         /*enable power down fast RTC memory in sleep*/
-            uint32_t slowmem_force_pd:    1;         /*RTC memory force power down*/
-            uint32_t slowmem_force_pu:    1;         /*RTC memory force power up*/
-            uint32_t slowmem_pd_en:       1;         /*enable power down RTC memory in sleep*/
-            uint32_t pwc_force_pd:        1;         /*rtc_peri force power down*/
-            uint32_t pwc_force_pu:        1;         /*rtc_peri force power up*/
-            uint32_t pd_en:               1;         /*enable power down rtc_peri in sleep*/
-            uint32_t reserved21:             11;
-        };
-        uint32_t val;
-    } rtc_pwc;
-    union {
-        struct {
-            uint32_t reserved0:           3;
-            uint32_t lslp_mem_force_pd:   1;             /*memories in digital core force PD in sleep*/
-            uint32_t lslp_mem_force_pu:   1;             /*memories in digital core force no PD in sleep*/
-            uint32_t rom0_force_pd:       1;             /*ROM force power down*/
-            uint32_t rom0_force_pu:       1;             /*ROM force power up*/
-            uint32_t inter_ram0_force_pd: 1;             /*internal SRAM 0 force power down*/
-            uint32_t inter_ram0_force_pu: 1;             /*internal SRAM 0 force power up*/
-            uint32_t inter_ram1_force_pd: 1;             /*internal SRAM 1 force power down*/
-            uint32_t inter_ram1_force_pu: 1;             /*internal SRAM 1 force power up*/
-            uint32_t inter_ram2_force_pd: 1;             /*internal SRAM 2 force power down*/
-            uint32_t inter_ram2_force_pu: 1;             /*internal SRAM 2 force power up*/
-            uint32_t inter_ram3_force_pd: 1;             /*internal SRAM 3 force power down*/
-            uint32_t inter_ram3_force_pu: 1;             /*internal SRAM 3 force power up*/
-            uint32_t inter_ram4_force_pd: 1;             /*internal SRAM 4 force power down*/
-            uint32_t inter_ram4_force_pu: 1;             /*internal SRAM 4 force power up*/
-            uint32_t wifi_force_pd:       1;             /*wifi force power down*/
-            uint32_t wifi_force_pu:       1;             /*wifi force power up*/
-            uint32_t dg_wrap_force_pd:    1;             /*digital core force power down*/
-            uint32_t dg_wrap_force_pu:    1;             /*digital core force power up*/
-            uint32_t reserved21:          3;
-            uint32_t rom0_pd_en:          1;             /*enable power down ROM in sleep*/
-            uint32_t inter_ram0_pd_en:    1;             /*enable power down internal SRAM 0 in sleep*/
-            uint32_t inter_ram1_pd_en:    1;             /*enable power down internal SRAM 1 in sleep*/
-            uint32_t inter_ram2_pd_en:    1;             /*enable power down internal SRAM 2 in sleep*/
-            uint32_t inter_ram3_pd_en:    1;             /*enable power down internal SRAM 3 in sleep*/
-            uint32_t inter_ram4_pd_en:    1;             /*enable power down internal SRAM 4 in sleep*/
-            uint32_t wifi_pd_en:          1;             /*enable power down wifi in sleep*/
-            uint32_t dg_wrap_pd_en:       1;             /*enable power down digital core in sleep*/
-        };
-        uint32_t val;
-    } dig_pwc;
-    union {
-        struct {
-            uint32_t reserved0:              7;
-            uint32_t dig_iso_force_off:      1;
-            uint32_t dig_iso_force_on:       1;
-            uint32_t dg_pad_autohold:        1;          /*read only register to indicate digital pad auto-hold status*/
-            uint32_t clr_dg_pad_autohold:    1;          /*wtite only register to clear digital pad auto-hold*/
-            uint32_t dg_pad_autohold_en:     1;          /*digital pad enable auto-hold*/
-            uint32_t dg_pad_force_noiso:     1;          /*digital pad force no ISO*/
-            uint32_t dg_pad_force_iso:       1;          /*digital pad force ISO*/
-            uint32_t dg_pad_force_unhold:    1;          /*digital pad force un-hold*/
-            uint32_t dg_pad_force_hold:      1;          /*digital pad force hold*/
-            uint32_t rom0_force_iso:         1;          /*ROM force ISO*/
-            uint32_t rom0_force_noiso:       1;          /*ROM force no ISO*/
-            uint32_t inter_ram0_force_iso:   1;          /*internal SRAM 0 force ISO*/
-            uint32_t inter_ram0_force_noiso: 1;          /*internal SRAM 0 force no ISO*/
-            uint32_t inter_ram1_force_iso:   1;          /*internal SRAM 1 force ISO*/
-            uint32_t inter_ram1_force_noiso: 1;          /*internal SRAM 1 force no ISO*/
-            uint32_t inter_ram2_force_iso:   1;          /*internal SRAM 2 force ISO*/
-            uint32_t inter_ram2_force_noiso: 1;          /*internal SRAM 2 force no ISO*/
-            uint32_t inter_ram3_force_iso:   1;          /*internal SRAM 3 force ISO*/
-            uint32_t inter_ram3_force_noiso: 1;          /*internal SRAM 3 force no ISO*/
-            uint32_t inter_ram4_force_iso:   1;          /*internal SRAM 4 force ISO*/
-            uint32_t inter_ram4_force_noiso: 1;          /*internal SRAM 4 force no ISO*/
-            uint32_t wifi_force_iso:         1;          /*wifi force ISO*/
-            uint32_t wifi_force_noiso:       1;          /*wifi force no ISO*/
-            uint32_t dg_wrap_force_iso:      1;          /*digital core force ISO*/
-            uint32_t dg_wrap_force_noiso:    1;          /*digital core force no ISO*/
-        };
-        uint32_t val;
-    } dig_iso;
-    union {
-        struct {
-            uint32_t reserved0:            7;
-            uint32_t pause_in_slp:     1;            /*pause WDT in sleep*/
-            uint32_t appcpu_reset_en:  1;            /*enable WDT reset APP CPU*/
-            uint32_t procpu_reset_en:  1;            /*enable WDT reset PRO CPU*/
-            uint32_t flashboot_mod_en: 1;            /*enable WDT in flash boot*/
-            uint32_t sys_reset_length: 3;            /*system reset counter length*/
-            uint32_t cpu_reset_length: 3;            /*CPU reset counter length*/
-            uint32_t level_int_en:     1;            /*N/A*/
-            uint32_t edge_int_en:      1;            /*N/A*/
-            uint32_t stg3:             3;            /*1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en*/
-            uint32_t stg2:             3;            /*1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en*/
-            uint32_t stg1:             3;            /*1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en*/
-            uint32_t stg0:             3;            /*1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en*/
-            uint32_t en:               1;            /*enable RTC WDT*/
-        };
-        uint32_t val;
-    } wdt_config0;
-    uint32_t wdt_config1;                             /**/
-    uint32_t wdt_config2;                             /**/
-    uint32_t wdt_config3;                             /**/
-    uint32_t wdt_config4;                             /**/
-    union {
-        struct {
-            uint32_t reserved0:   31;
-            uint32_t feed: 1;
-        };
-        uint32_t val;
-    } wdt_feed;
-    uint32_t wdt_wprotect;                            /**/
-    union {
-        struct {
-            uint32_t reserved0: 29;
-            uint32_t ent_rtc:    1;                      /*ENT_RTC*/
-            uint32_t dtest_rtc:  2;                      /*DTEST_RTC*/
-        };
-        uint32_t val;
-    } test_mux;
-    union {
-        struct {
-            uint32_t reserved0:         20;
-            uint32_t appcpu_c1: 6;              /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]}  == 0x86 will stall APP CPU*/
-            uint32_t procpu_c1: 6;              /*{reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]}  == 0x86 will stall PRO CPU*/
-        };
-        uint32_t val;
-    } sw_cpu_stall;
-    uint32_t store4;                                 /*32-bit general purpose retention register*/
-    uint32_t store5;                                 /*32-bit general purpose retention register*/
-    uint32_t store6;                                 /*32-bit general purpose retention register*/
-    uint32_t store7;                                 /*32-bit general purpose retention register*/
-    uint32_t diag0;                                  /**/
-    uint32_t diag1;                                  /**/
-    union {
-        struct {
-            uint32_t adc1_hold_force:       1;
-            uint32_t adc2_hold_force:       1;
-            uint32_t pdac1_hold_force:      1;
-            uint32_t pdac2_hold_force:      1;
-            uint32_t sense1_hold_force:     1;
-            uint32_t sense2_hold_force:     1;
-            uint32_t sense3_hold_force:     1;
-            uint32_t sense4_hold_force:     1;
-            uint32_t touch_pad0_hold_force: 1;
-            uint32_t touch_pad1_hold_force: 1;
-            uint32_t touch_pad2_hold_force: 1;
-            uint32_t touch_pad3_hold_force: 1;
-            uint32_t touch_pad4_hold_force: 1;
-            uint32_t touch_pad5_hold_force: 1;
-            uint32_t touch_pad6_hold_force: 1;
-            uint32_t touch_pad7_hold_force: 1;
-            uint32_t x32p_hold_force:       1;
-            uint32_t x32n_hold_force:       1;
-            uint32_t reserved18:           14;
-        };
-        uint32_t val;
-    } hold_force;
-    union {
-        struct {
-            uint32_t ext_wakeup1_sel:       18;          /*Bitmap to select RTC pads for ext wakeup1*/
-            uint32_t ext_wakeup1_status_clr: 1;          /*clear ext wakeup1 status*/
-            uint32_t reserved19:            13;
-        };
-        uint32_t val;
-    } ext_wakeup1;
-    union {
-        struct {
-            uint32_t ext_wakeup1_status:18;              /*ext wakeup1 status*/
-            uint32_t reserved18:        14;
-        };
-        uint32_t val;
-    } ext_wakeup1_status;
-    union {
-        struct {
-            uint32_t reserved0:                14;
-            uint32_t close_flash_ena: 1;       /*enable close flash when brown out happens*/
-            uint32_t pd_rf_ena:       1;       /*enable power down RF when brown out happens*/
-            uint32_t rst_wait:       10;       /*brown out reset wait cycles*/
-            uint32_t rst_ena:         1;       /*enable brown out reset*/
-            uint32_t thres:          3;       /*brown out threshold*/
-            uint32_t ena:             1;       /*enable brown out*/
-            uint32_t det:         1;       /*brown out detect*/
-        };
-        uint32_t val;
-    } brown_out;
-    uint32_t reserved_39;
-    uint32_t reserved_3d;
-    uint32_t reserved_41;
-    uint32_t reserved_45;
-    uint32_t reserved_49;
-    uint32_t reserved_4d;
-    union {
-        struct {
-            uint32_t date:      28;
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    } date;
-} rtc_cntl_dev_t;
-extern rtc_cntl_dev_t RTCCNTL;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_RTC_CNTL_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/rtc_gpio_channel.h b/tools/sdk/include/soc/soc/rtc_gpio_channel.h
deleted file mode 100644
index c5107a0fb1d..00000000000
--- a/tools/sdk/include/soc/soc/rtc_gpio_channel.h
+++ /dev/null
@@ -1,73 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_RTC_GPIO_CHANNEL_H
-#define _SOC_RTC_GPIO_CHANNEL_H
-
-//RTC GPIO channels
-#define RTCIO_GPIO36_CHANNEL        0   //RTCIO_CHANNEL_0
-#define RTCIO_CHANNEL_0_GPIO_NUM    36
-
-#define RTCIO_GPIO37_CHANNEL        1   //RTCIO_CHANNEL_1
-#define RTCIO_CHANNEL_1_GPIO_NUM    37
-
-#define RTCIO_GPIO38_CHANNEL        2   //RTCIO_CHANNEL_2
-#define RTCIO_CHANNEL_2_GPIO_NUM    38
-
-#define RTCIO_GPIO39_CHANNEL        3   //RTCIO_CHANNEL_3
-#define RTCIO_CHANNEL_3_GPIO_NUM    39
-
-#define RTCIO_GPIO34_CHANNEL        4   //RTCIO_CHANNEL_4
-#define RTCIO_CHANNEL_4_GPIO_NUM    34
-
-#define RTCIO_GPIO35_CHANNEL        5   //RTCIO_CHANNEL_5
-#define RTCIO_CHANNEL_5_GPIO_NUM    35
-
-#define RTCIO_GPIO25_CHANNEL        6   //RTCIO_CHANNEL_6
-#define RTCIO_CHANNEL_6_GPIO_NUM    25
-
-#define RTCIO_GPIO26_CHANNEL        7   //RTCIO_CHANNEL_7
-#define RTCIO_CHANNEL_7_GPIO_NUM    26
-
-#define RTCIO_GPIO33_CHANNEL        8   //RTCIO_CHANNEL_8
-#define RTCIO_CHANNEL_8_GPIO_NUM    33
-
-#define RTCIO_GPIO32_CHANNEL        9   //RTCIO_CHANNEL_9
-#define RTCIO_CHANNEL_9_GPIO_NUM    32
-
-#define RTCIO_GPIO4_CHANNEL         10   //RTCIO_CHANNEL_10
-#define RTCIO_CHANNEL_10_GPIO_NUM   4
-
-#define RTCIO_GPIO0_CHANNEL         11   //RTCIO_CHANNEL_11
-#define RTCIO_CHANNEL_11_GPIO_NUM   0
-
-#define RTCIO_GPIO2_CHANNEL         12   //RTCIO_CHANNEL_12
-#define RTCIO_CHANNEL_12_GPIO_NUM   2
-
-#define RTCIO_GPIO15_CHANNEL        13   //RTCIO_CHANNEL_13
-#define RTCIO_CHANNEL_13_GPIO_NUM   15
-
-#define RTCIO_GPIO13_CHANNEL        14   //RTCIO_CHANNEL_14
-#define RTCIO_CHANNEL_14_GPIO_NUM   13
-
-#define RTCIO_GPIO12_CHANNEL        15   //RTCIO_CHANNEL_15
-#define RTCIO_CHANNEL_15_GPIO_NUM   12
-
-#define RTCIO_GPIO14_CHANNEL        16   //RTCIO_CHANNEL_16
-#define RTCIO_CHANNEL_16_GPIO_NUM   14
-
-#define RTCIO_GPIO27_CHANNEL        17   //RTCIO_CHANNEL_17
-#define RTCIO_CHANNEL_17_GPIO_NUM   27
-
-#endif
diff --git a/tools/sdk/include/soc/soc/rtc_i2c_reg.h b/tools/sdk/include/soc/soc/rtc_i2c_reg.h
deleted file mode 100644
index be7b64c6b1c..00000000000
--- a/tools/sdk/include/soc/soc/rtc_i2c_reg.h
+++ /dev/null
@@ -1,288 +0,0 @@
-// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "soc.h"
-
-/**
- * This file lists peripheral registers of an I2C controller which is part of the RTC.
- * ULP coprocessor uses this controller to implement I2C_RD and I2C_WR instructions.
- *
- * Part of the functionality of this controller (such as slave mode, and multi-byte
- * transfers) is not wired to the ULP, and is such, is not available to the
- * ULP programs.
- */
-
-#define RTC_I2C_SCL_LOW_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x000)
-/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[18:0] ;default: 19'b0 ; */
-/*description: number of cycles that scl == 0 */
-#define RTC_I2C_SCL_LOW_PERIOD    0x1FFFFFF
-#define RTC_I2C_SCL_LOW_PERIOD_M  ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
-#define RTC_I2C_SCL_LOW_PERIOD_V  0x1FFFFFF
-#define RTC_I2C_SCL_LOW_PERIOD_S  0
-
-#define RTC_I2C_CTRL_REG          (DR_REG_RTC_I2C_BASE + 0x004)
-/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Send LSB first */
-#define RTC_I2C_RX_LSB_FIRST	BIT(7)
-#define RTC_I2C_RX_LSB_FIRST_M  BIT(7)
-#define RTC_I2C_RX_LSB_FIRST_V  (1)
-#define RTC_I2C_RX_LSB_FIRST_S  (7)
-/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Receive LSB first */
-#define RTC_I2C_TX_LSB_FIRST	BIT(6)
-#define RTC_I2C_TX_LSB_FIRST_M  BIT(6)
-#define RTC_I2C_TX_LSB_FIRST_V  (1)
-#define RTC_I2C_TX_LSB_FIRST_S  (6)
-/* RTC_I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Force to generate start condition */
-#define RTC_I2C_TRANS_START	   BIT(5)
-#define RTC_I2C_TRANS_START_M  BIT(5)
-#define RTC_I2C_TRANS_START_V  (1)
-#define RTC_I2C_TRANS_START_S  (5)
-/* RTC_I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Master (1) or slave (0) */
-#define RTC_I2C_MS_MODE	   BIT(4)
-#define RTC_I2C_MS_MODE_M  BIT(4)
-#define RTC_I2C_MS_MODE_V  (1)
-#define RTC_I2C_MS_MODE_S  (4)
-/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: SCL is push-pull (1) or open-drain (0) */
-#define RTC_I2C_SCL_FORCE_OUT	 BIT(1)
-#define RTC_I2C_SCL_FORCE_OUT_M  BIT(1)
-#define RTC_I2C_SCL_FORCE_OUT_V  (1)
-#define RTC_I2C_SCL_FORCE_OUT_S  (1)
-/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SDA is push-pull (1) or open-drain (0) */
-#define RTC_I2C_SDA_FORCE_OUT	 BIT(0)
-#define RTC_I2C_SDA_FORCE_OUT_M  BIT(0)
-#define RTC_I2C_SDA_FORCE_OUT_V  (1)
-#define RTC_I2C_SDA_FORCE_OUT_S  (0)
-
-#define RTC_I2C_DEBUG_STATUS_REG          (DR_REG_RTC_I2C_BASE + 0x008)
-/* RTC_I2C_SCL_STATE : R/W ;bitpos:[30:28] ;default: 3'b0 ; */
-/*description: state of SCL state machine */
-#define RTC_I2C_SCL_STATE	 0x7
-#define RTC_I2C_SCL_STATE_M  ((RTC_I2C_SCL_STATE_V)<<(RTC_I2C_SCL_STATE_S))
-#define RTC_I2C_SCL_STATE_V  0x7
-#define RTC_I2C_SCL_STATE_S  28
-/* RTC_I2C_MAIN_STATE : R/W ;bitpos:[27:25] ;default: 3'b0 ; */
-/*description: state of the main state machine */
-#define RTC_I2C_MAIN_STATE    0x7
-#define RTC_I2C_MAIN_STATE_M  ((RTC_I2C_MAIN_STATE_V)<<(RTC_I2C_MAIN_STATE_S))
-#define RTC_I2C_MAIN_STATE_V  0x7
-#define RTC_I2C_MAIN_STATE_S  25
-/* RTC_I2C_BYTE_TRANS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: 8 bit transmit done */
-#define RTC_I2C_BYTE_TRANS	   BIT(6)
-#define RTC_I2C_BYTE_TRANS_M  BIT(6)
-#define RTC_I2C_BYTE_TRANS_V  (1)
-#define RTC_I2C_BYTE_TRANS_S  (6)
-/* RTC_I2C_SLAVE_ADDR_MATCH : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: When working as a slave, whether address was matched */
-#define RTC_I2C_SLAVE_ADDR_MATCH	   BIT(5)
-#define RTC_I2C_SLAVE_ADDR_MATCH_M  BIT(5)
-#define RTC_I2C_SLAVE_ADDR_MATCH_V  (1)
-#define RTC_I2C_SLAVE_ADDR_MATCH_S  (5)
-/* RTC_I2C_BUS_BUSY : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: operation is in progress */
-#define RTC_I2C_BUS_BUSY	   BIT(4)
-#define RTC_I2C_BUS_BUSY_M  BIT(4)
-#define RTC_I2C_BUS_BUSY_V  (1)
-#define RTC_I2C_BUS_BUSY_S  (4)
-/* RTC_I2C_ARB_LOST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: When working as a master, lost control of I2C bus */
-#define RTC_I2C_ARB_LOST	   BIT(3)
-#define RTC_I2C_ARB_LOST_M  BIT(3)
-#define RTC_I2C_ARB_LOST_V  (1)
-#define RTC_I2C_ARB_LOST_S  (3)
-/* RTC_I2C_TIMED_OUT : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Transfer has timed out */
-#define RTC_I2C_TIMED_OUT	   BIT(2)
-#define RTC_I2C_TIMED_OUT_M  BIT(2)
-#define RTC_I2C_TIMED_OUT_V  (1)
-#define RTC_I2C_TIMED_OUT_S  (2)
-/* RTC_I2C_SLAVE_RW : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: When working as a slave, the value of R/W bit received */
-#define RTC_I2C_SLAVE_RW	   BIT(1)
-#define RTC_I2C_SLAVE_RW_M  BIT(1)
-#define RTC_I2C_SLAVE_RW_V  (1)
-#define RTC_I2C_SLAVE_RW_S  (1)
-/* RTC_I2C_ACK_VAL : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The value of an acknowledge signal on the bus */
-#define RTC_I2C_ACK_VAL	   BIT(0)
-#define RTC_I2C_ACK_VAL_M  BIT(0)
-#define RTC_I2C_ACK_VAL_V  (1)
-#define RTC_I2C_ACK_VAL_S  (0)
-
-#define RTC_I2C_TIMEOUT_REG          (DR_REG_RTC_I2C_BASE + 0x00c)
-/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: Maximum number of FAST_CLK cycles that the transmission can take */
-#define RTC_I2C_TIMEOUT	   0xFFFFF
-#define RTC_I2C_TIMEOUT_M  ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
-#define RTC_I2C_TIMEOUT_V  0xFFFFF
-#define RTC_I2C_TIMEOUT_S  0
-
-#define RTC_I2C_SLAVE_ADDR_REG          (DR_REG_RTC_I2C_BASE + 0x010)
-/* RTC_I2C_SLAVE_ADDR_10BIT : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set if local slave address is 10-bit */
-#define RTC_I2C_SLAVE_ADDR_10BIT	BIT(31)
-#define RTC_I2C_SLAVE_ADDR_10BIT_M  BIT(31)
-#define RTC_I2C_SLAVE_ADDR_10BIT_V  (1)
-#define RTC_I2C_SLAVE_ADDR_10BIT_S  (31)
-/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
-/*description: local slave address */
-#define RTC_I2C_SLAVE_ADDR	  0x7FFF
-#define RTC_I2C_SLAVE_ADDR_M  ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
-#define RTC_I2C_SLAVE_ADDR_V  0x7FFF
-#define RTC_I2C_SLAVE_ADDR_S  0
-
-/* Result of last read operation. Not used directly as the data will be
- * returned to the ULP. Listed for debugging purposes.
- */
-#define RTC_I2C_DATA_REG         (DR_REG_RTC_I2C_BASE + 0x01c)
-
-/* Interrupt registers; since the interrupt from RTC_I2C is not connected,
- * these registers are only listed for debugging purposes.
- */
-
-/* Interrupt raw status register */
-#define RTC_I2C_INT_RAW_REG         (DR_REG_RTC_I2C_BASE + 0x020)
-/* RTC_I2C_TIME_OUT_INT_RAW : R/O ;bitpos:[7] ;default: 1'b0 ; */
-/*description: time out interrupt raw status */
-#define RTC_I2C_TIME_OUT_INT_RAW	   BIT(7)
-#define RTC_I2C_TIME_OUT_INT_RAW_M  BIT(7)
-#define RTC_I2C_TIME_OUT_INT_RAW_V  (1)
-#define RTC_I2C_TIME_OUT_INT_RAW_S  (7)
-/* RTC_I2C_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Stop condition has been detected interrupt raw status */
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW	   BIT(6)
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M  BIT(6)
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V  (1)
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S  (6)
-/* RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description:  */
-#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW	   BIT(5)
-#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_M  BIT(5)
-#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_V  (1)
-#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_RAW_S  (5)
-/* RTC_I2C_ARBITRATION_LOST_INT_RAW : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Master lost arbitration */
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW	   BIT(4)
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M  BIT(4)
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V  (1)
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S  (4)
-/* RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Slave accepted 1 byte and address matched */
-#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW	   BIT(3)
-#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_M  BIT(3)
-#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_V  (1)
-#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_RAW_S  (3)
-
-/* Interrupt clear register */
-#define RTC_I2C_INT_CLR_REG         (DR_REG_RTC_I2C_BASE + 0x024)
-/* RTC_I2C_TIME_OUT_INT_CLR : W/O ;bitpos:[8] ;default: 1'b0 ; */
-/*description:  */
-#define RTC_I2C_TIME_OUT_INT_CLR	   BIT(8)
-#define RTC_I2C_TIME_OUT_INT_CLR_M  BIT(8)
-#define RTC_I2C_TIME_OUT_INT_CLR_V  (1)
-#define RTC_I2C_TIME_OUT_INT_CLR_S  (8)
-/* RTC_I2C_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description:  */
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR	   BIT(7)
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M  BIT(7)
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V  (1)
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S  (7)
-/* RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description:  */
-#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR	   BIT(6)
-#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_M  BIT(6)
-#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_V  (1)
-#define RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR_S  (6)
-/* RTC_I2C_ARBITRATION_LOST_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description:  */
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR	   BIT(5)
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M  BIT(5)
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V  (1)
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S  (5)
-/* RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description:  */
-#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR	   BIT(4)
-#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_M  BIT(4)
-#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_V  (1)
-#define RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR_S  (4)
-
-/* Interrupt enable register.
- * Bit definitions are not given here, because interrupt functionality
- * of RTC_I2C is not used.
- */
-#define RTC_I2C_INT_EN_REG          (DR_REG_RTC_I2C_BASE + 0x028)
-
-/* Masked interrupt status register.
- * Bit definitions are not given here, because interrupt functionality
- * of RTC_I2C is not used.
- */
-#define RTC_I2C_INT_ST_REG          (DR_REG_RTC_I2C_BASE + 0x02c)
-
-#define RTC_I2C_SDA_DUTY_REG          (DR_REG_RTC_I2C_BASE + 0x030)
-/* RTC_I2C_SDA_DUTY : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: Number of FAST_CLK cycles SDA will switch after falling edge of SCL */
-#define RTC_I2C_SDA_DUTY	0xFFFFF
-#define RTC_I2C_SDA_DUTY_M  ((RTC_I2C_SDA_DUTY_V)<<(RTC_I2C_SDA_DUTY_S))
-#define RTC_I2C_SDA_DUTY_V  0xFFFFF
-#define RTC_I2C_SDA_DUTY_S  0
-
-#define RTC_I2C_SCL_HIGH_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x038)
-/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: Number of FAST_CLK cycles for SCL to be high */
-#define RTC_I2C_SCL_HIGH_PERIOD	   0xFFFFF
-#define RTC_I2C_SCL_HIGH_PERIOD_M  ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
-#define RTC_I2C_SCL_HIGH_PERIOD_V  0xFFFFF
-#define RTC_I2C_SCL_HIGH_PERIOD_S  0
-
-#define RTC_I2C_SCL_START_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x040)
-/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: Number of FAST_CLK cycles to wait before generating start condition */
-#define RTC_I2C_SCL_START_PERIOD	0xFFFFF
-#define RTC_I2C_SCL_START_PERIOD_M  ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
-#define RTC_I2C_SCL_START_PERIOD_V  0xFFFFF
-#define RTC_I2C_SCL_START_PERIOD_S  0
-
-#define RTC_I2C_SCL_STOP_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x044)
-/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: Number of FAST_CLK cycles to wait before generating stop condition */
-#define RTC_I2C_SCL_STOP_PERIOD	   0xFFFFF
-#define RTC_I2C_SCL_STOP_PERIOD_M  ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
-#define RTC_I2C_SCL_STOP_PERIOD_V  0xFFFFF
-#define RTC_I2C_SCL_STOP_PERIOD_S  0
-
-/* A block of 16 RTC_I2C_CMD registers which describe I2C operation to be
- * performed. Unused when ULP is controlling RTC_I2C.
- */
-#define RTC_I2C_CMD_REG_COUNT   16
-#define RTC_I2C_CMD_REG(i)          (DR_REG_RTC_I2C_BASE + 0x048 + (i) * 4)
-/* RTC_I2C_CMD_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Bit is set by HW when command is done */
-#define RTC_I2C_CMD_DONE	   BIT(31)
-#define RTC_I2C_CMD_DONE_M  BIT(31)
-#define RTC_I2C_CMD_DONE_V  (1)
-#define RTC_I2C_CMD_DONE_S  (31)
-/* RTC_I2C_VAL : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: Command content */
-#define RTC_I2C_VAL	   0
-#define RTC_I2C_VAL_M  ((RTC_I2C_VAL_V)<<(RTC_I2C_VAL_S))
-#define RTC_I2C_VAL_V  0x3FFF
-#define RTC_I2C_VAL_S  0
-
diff --git a/tools/sdk/include/soc/soc/rtc_io_reg.h b/tools/sdk/include/soc/soc/rtc_io_reg.h
deleted file mode 100644
index 5a3ce10d422..00000000000
--- a/tools/sdk/include/soc/soc/rtc_io_reg.h
+++ /dev/null
@@ -1,1954 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_RTC_IO_REG_H_
-#define _SOC_RTC_IO_REG_H_
-
-
-#include "soc.h"
-#define RTC_GPIO_OUT_REG          (DR_REG_RTCIO_BASE + 0x0)
-/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output value*/
-#define RTC_GPIO_OUT_DATA  0x0003FFFF
-#define RTC_GPIO_OUT_DATA_M  ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S))
-#define RTC_GPIO_OUT_DATA_V  0x3FFFF
-#define RTC_GPIO_OUT_DATA_S  14
-
-#define RTC_GPIO_OUT_W1TS_REG          (DR_REG_RTCIO_BASE + 0x4)
-/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output value write 1 to set*/
-#define RTC_GPIO_OUT_DATA_W1TS  0x0003FFFF
-#define RTC_GPIO_OUT_DATA_W1TS_M  ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S))
-#define RTC_GPIO_OUT_DATA_W1TS_V  0x3FFFF
-#define RTC_GPIO_OUT_DATA_W1TS_S  14
-
-#define RTC_GPIO_OUT_W1TC_REG          (DR_REG_RTCIO_BASE + 0x8)
-/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output value write 1 to clear*/
-#define RTC_GPIO_OUT_DATA_W1TC  0x0003FFFF
-#define RTC_GPIO_OUT_DATA_W1TC_M  ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S))
-#define RTC_GPIO_OUT_DATA_W1TC_V  0x3FFFF
-#define RTC_GPIO_OUT_DATA_W1TC_S  14
-
-#define RTC_GPIO_ENABLE_REG          (DR_REG_RTCIO_BASE + 0xc)
-/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output enable*/
-#define RTC_GPIO_ENABLE  0x0003FFFF
-#define RTC_GPIO_ENABLE_M  ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S))
-#define RTC_GPIO_ENABLE_V  0x3FFFF
-#define RTC_GPIO_ENABLE_S  14
-
-#define RTC_GPIO_ENABLE_W1TS_REG          (DR_REG_RTCIO_BASE + 0x10)
-/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output enable write 1 to set*/
-#define RTC_GPIO_ENABLE_W1TS  0x0003FFFF
-#define RTC_GPIO_ENABLE_W1TS_M  ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S))
-#define RTC_GPIO_ENABLE_W1TS_V  0x3FFFF
-#define RTC_GPIO_ENABLE_W1TS_S  14
-
-#define RTC_GPIO_ENABLE_W1TC_REG          (DR_REG_RTCIO_BASE + 0x14)
-/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output enable write 1 to clear*/
-#define RTC_GPIO_ENABLE_W1TC  0x0003FFFF
-#define RTC_GPIO_ENABLE_W1TC_M  ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S))
-#define RTC_GPIO_ENABLE_W1TC_V  0x3FFFF
-#define RTC_GPIO_ENABLE_W1TC_S  14
-
-#define RTC_GPIO_STATUS_REG          (DR_REG_RTCIO_BASE + 0x18)
-/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 interrupt status*/
-#define RTC_GPIO_STATUS_INT  0x0003FFFF
-#define RTC_GPIO_STATUS_INT_M  ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S))
-#define RTC_GPIO_STATUS_INT_V  0x3FFFF
-#define RTC_GPIO_STATUS_INT_S  14
-
-#define RTC_GPIO_STATUS_W1TS_REG          (DR_REG_RTCIO_BASE + 0x1c)
-/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 interrupt status write 1 to set*/
-#define RTC_GPIO_STATUS_INT_W1TS  0x0003FFFF
-#define RTC_GPIO_STATUS_INT_W1TS_M  ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S))
-#define RTC_GPIO_STATUS_INT_W1TS_V  0x3FFFF
-#define RTC_GPIO_STATUS_INT_W1TS_S  14
-
-#define RTC_GPIO_STATUS_W1TC_REG          (DR_REG_RTCIO_BASE + 0x20)
-/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 interrupt status write 1 to clear*/
-#define RTC_GPIO_STATUS_INT_W1TC  0x0003FFFF
-#define RTC_GPIO_STATUS_INT_W1TC_M  ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S))
-#define RTC_GPIO_STATUS_INT_W1TC_V  0x3FFFF
-#define RTC_GPIO_STATUS_INT_W1TC_S  14
-
-#define RTC_GPIO_IN_REG          (DR_REG_RTCIO_BASE + 0x24)
-/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default:  ; */
-/*description: GPIO0~17 input value*/
-#define RTC_GPIO_IN_NEXT  0x0003FFFF
-#define RTC_GPIO_IN_NEXT_M  ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S))
-#define RTC_GPIO_IN_NEXT_V  0x3FFFF
-#define RTC_GPIO_IN_NEXT_S  14
-
-#define RTC_GPIO_PIN0_REG          (DR_REG_RTCIO_BASE + 0x28)
-/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN0_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN0_INT_TYPE_M  ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))
-#define RTC_GPIO_PIN0_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN0_INT_TYPE_S  7
-/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN0_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN0_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN0_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN1_REG          (DR_REG_RTCIO_BASE + 0x2c)
-/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN1_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN1_INT_TYPE_M  ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))
-#define RTC_GPIO_PIN1_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN1_INT_TYPE_S  7
-/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN1_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN1_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN1_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN2_REG          (DR_REG_RTCIO_BASE + 0x30)
-/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN2_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN2_INT_TYPE_M  ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))
-#define RTC_GPIO_PIN2_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN2_INT_TYPE_S  7
-/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN2_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN2_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN2_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN3_REG          (DR_REG_RTCIO_BASE + 0x34)
-/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN3_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN3_INT_TYPE_M  ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))
-#define RTC_GPIO_PIN3_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN3_INT_TYPE_S  7
-/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN3_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN3_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN3_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN4_REG          (DR_REG_RTCIO_BASE + 0x38)
-/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN4_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN4_INT_TYPE_M  ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))
-#define RTC_GPIO_PIN4_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN4_INT_TYPE_S  7
-/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN4_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN4_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN4_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN5_REG          (DR_REG_RTCIO_BASE + 0x3c)
-/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN5_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN5_INT_TYPE_M  ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))
-#define RTC_GPIO_PIN5_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN5_INT_TYPE_S  7
-/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN5_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN5_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN5_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN6_REG          (DR_REG_RTCIO_BASE + 0x40)
-/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN6_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN6_INT_TYPE_M  ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))
-#define RTC_GPIO_PIN6_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN6_INT_TYPE_S  7
-/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN6_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN6_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN6_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN7_REG          (DR_REG_RTCIO_BASE + 0x44)
-/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN7_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN7_INT_TYPE_M  ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))
-#define RTC_GPIO_PIN7_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN7_INT_TYPE_S  7
-/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN7_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN7_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN7_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN8_REG          (DR_REG_RTCIO_BASE + 0x48)
-/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN8_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN8_INT_TYPE_M  ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))
-#define RTC_GPIO_PIN8_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN8_INT_TYPE_S  7
-/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN8_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN8_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN8_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN9_REG          (DR_REG_RTCIO_BASE + 0x4c)
-/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN9_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN9_INT_TYPE_M  ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))
-#define RTC_GPIO_PIN9_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN9_INT_TYPE_S  7
-/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN9_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN9_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN9_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN10_REG          (DR_REG_RTCIO_BASE + 0x50)
-/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN10_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN10_INT_TYPE_M  ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))
-#define RTC_GPIO_PIN10_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN10_INT_TYPE_S  7
-/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN10_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN10_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN10_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN11_REG          (DR_REG_RTCIO_BASE + 0x54)
-/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN11_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN11_INT_TYPE_M  ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))
-#define RTC_GPIO_PIN11_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN11_INT_TYPE_S  7
-/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN11_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN11_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN11_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN12_REG          (DR_REG_RTCIO_BASE + 0x58)
-/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN12_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN12_INT_TYPE_M  ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))
-#define RTC_GPIO_PIN12_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN12_INT_TYPE_S  7
-/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN12_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN12_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN12_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN13_REG          (DR_REG_RTCIO_BASE + 0x5c)
-/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN13_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN13_INT_TYPE_M  ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))
-#define RTC_GPIO_PIN13_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN13_INT_TYPE_S  7
-/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN13_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN13_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN13_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN14_REG          (DR_REG_RTCIO_BASE + 0x60)
-/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN14_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN14_INT_TYPE_M  ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))
-#define RTC_GPIO_PIN14_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN14_INT_TYPE_S  7
-/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN14_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN14_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN14_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN15_REG          (DR_REG_RTCIO_BASE + 0x64)
-/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN15_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN15_INT_TYPE_M  ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))
-#define RTC_GPIO_PIN15_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN15_INT_TYPE_S  7
-/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN15_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN15_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN15_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN16_REG          (DR_REG_RTCIO_BASE + 0x68)
-/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN16_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN16_INT_TYPE_M  ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))
-#define RTC_GPIO_PIN16_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN16_INT_TYPE_S  7
-/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN16_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN16_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN16_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN17_REG          (DR_REG_RTCIO_BASE + 0x6c)
-/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN17_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN17_INT_TYPE_M  ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))
-#define RTC_GPIO_PIN17_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN17_INT_TYPE_S  7
-/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN17_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN17_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN17_PAD_DRIVER_S  2
-
-#define RTC_IO_RTC_DEBUG_SEL_REG          (DR_REG_RTCIO_BASE + 0x70)
-/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_12M_NO_GATING  (BIT(25))
-#define RTC_IO_DEBUG_12M_NO_GATING_M  (BIT(25))
-#define RTC_IO_DEBUG_12M_NO_GATING_V  0x1
-#define RTC_IO_DEBUG_12M_NO_GATING_S  25
-/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL4  0x0000001F
-#define RTC_IO_DEBUG_SEL4_M  ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S))
-#define RTC_IO_DEBUG_SEL4_V  0x1F
-#define RTC_IO_DEBUG_SEL4_S  20
-/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL3  0x0000001F
-#define RTC_IO_DEBUG_SEL3_M  ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S))
-#define RTC_IO_DEBUG_SEL3_V  0x1F
-#define RTC_IO_DEBUG_SEL3_S  15
-/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL2  0x0000001F
-#define RTC_IO_DEBUG_SEL2_M  ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S))
-#define RTC_IO_DEBUG_SEL2_V  0x1F
-#define RTC_IO_DEBUG_SEL2_S  10
-/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL1  0x0000001F
-#define RTC_IO_DEBUG_SEL1_M  ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S))
-#define RTC_IO_DEBUG_SEL1_V  0x1F
-#define RTC_IO_DEBUG_SEL1_S  5
-/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL0  0x0000001F
-#define RTC_IO_DEBUG_SEL0_M  ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S))
-#define RTC_IO_DEBUG_SEL0_V  0x1F
-#define RTC_IO_DEBUG_SEL0_S  0
-#define RTC_IO_DEBUG_SEL0_8M       1
-#define RTC_IO_DEBUG_SEL0_32K_XTAL 4
-#define RTC_IO_DEBUG_SEL0_150K_OSC 5
-
-#define RTC_IO_DIG_PAD_HOLD_REG          (DR_REG_RTCIO_BASE + 0x74)
-/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */
-/*description: select the digital pad hold value.*/
-#define RTC_IO_DIG_PAD_HOLD  0xFFFFFFFF
-#define RTC_IO_DIG_PAD_HOLD_M  ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S))
-#define RTC_IO_DIG_PAD_HOLD_V  0xFFFFFFFF
-#define RTC_IO_DIG_PAD_HOLD_S  0
-
-#define RTC_IO_HALL_SENS_REG          (DR_REG_RTCIO_BASE + 0x78)
-/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: Power on hall sensor and connect to VP and VN*/
-#define RTC_IO_XPD_HALL  (BIT(31))
-#define RTC_IO_XPD_HALL_M  (BIT(31))
-#define RTC_IO_XPD_HALL_V  0x1
-#define RTC_IO_XPD_HALL_S  31
-/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: Reverse phase of hall sensor*/
-#define RTC_IO_HALL_PHASE  (BIT(30))
-#define RTC_IO_HALL_PHASE_M  (BIT(30))
-#define RTC_IO_HALL_PHASE_V  0x1
-#define RTC_IO_HALL_PHASE_S  30
-
-#define RTC_IO_SENSOR_PADS_REG          (DR_REG_RTCIO_BASE + 0x7c)
-/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_SENSE1_HOLD  (BIT(31))
-#define RTC_IO_SENSE1_HOLD_M  (BIT(31))
-#define RTC_IO_SENSE1_HOLD_V  0x1
-#define RTC_IO_SENSE1_HOLD_S  31
-/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_SENSE2_HOLD  (BIT(30))
-#define RTC_IO_SENSE2_HOLD_M  (BIT(30))
-#define RTC_IO_SENSE2_HOLD_V  0x1
-#define RTC_IO_SENSE2_HOLD_S  30
-/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_SENSE3_HOLD  (BIT(29))
-#define RTC_IO_SENSE3_HOLD_M  (BIT(29))
-#define RTC_IO_SENSE3_HOLD_V  0x1
-#define RTC_IO_SENSE3_HOLD_S  29
-/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_SENSE4_HOLD  (BIT(28))
-#define RTC_IO_SENSE4_HOLD_M  (BIT(28))
-#define RTC_IO_SENSE4_HOLD_V  0x1
-#define RTC_IO_SENSE4_HOLD_S  28
-/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_SENSE1_MUX_SEL  (BIT(27))
-#define RTC_IO_SENSE1_MUX_SEL_M  (BIT(27))
-#define RTC_IO_SENSE1_MUX_SEL_V  0x1
-#define RTC_IO_SENSE1_MUX_SEL_S  27
-/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_SENSE2_MUX_SEL  (BIT(26))
-#define RTC_IO_SENSE2_MUX_SEL_M  (BIT(26))
-#define RTC_IO_SENSE2_MUX_SEL_V  0x1
-#define RTC_IO_SENSE2_MUX_SEL_S  26
-/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_SENSE3_MUX_SEL  (BIT(25))
-#define RTC_IO_SENSE3_MUX_SEL_M  (BIT(25))
-#define RTC_IO_SENSE3_MUX_SEL_V  0x1
-#define RTC_IO_SENSE3_MUX_SEL_S  25
-/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_SENSE4_MUX_SEL  (BIT(24))
-#define RTC_IO_SENSE4_MUX_SEL_M  (BIT(24))
-#define RTC_IO_SENSE4_MUX_SEL_V  0x1
-#define RTC_IO_SENSE4_MUX_SEL_S  24
-/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_SENSE1_FUN_SEL  0x00000003
-#define RTC_IO_SENSE1_FUN_SEL_M  ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S))
-#define RTC_IO_SENSE1_FUN_SEL_V  0x3
-#define RTC_IO_SENSE1_FUN_SEL_S  22
-/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_SENSE1_SLP_SEL  (BIT(21))
-#define RTC_IO_SENSE1_SLP_SEL_M  (BIT(21))
-#define RTC_IO_SENSE1_SLP_SEL_V  0x1
-#define RTC_IO_SENSE1_SLP_SEL_S  21
-/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_SENSE1_SLP_IE  (BIT(20))
-#define RTC_IO_SENSE1_SLP_IE_M  (BIT(20))
-#define RTC_IO_SENSE1_SLP_IE_V  0x1
-#define RTC_IO_SENSE1_SLP_IE_S  20
-/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_SENSE1_FUN_IE  (BIT(19))
-#define RTC_IO_SENSE1_FUN_IE_M  (BIT(19))
-#define RTC_IO_SENSE1_FUN_IE_V  0x1
-#define RTC_IO_SENSE1_FUN_IE_S  19
-/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_SENSE2_FUN_SEL  0x00000003
-#define RTC_IO_SENSE2_FUN_SEL_M  ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S))
-#define RTC_IO_SENSE2_FUN_SEL_V  0x3
-#define RTC_IO_SENSE2_FUN_SEL_S  17
-/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_SENSE2_SLP_SEL  (BIT(16))
-#define RTC_IO_SENSE2_SLP_SEL_M  (BIT(16))
-#define RTC_IO_SENSE2_SLP_SEL_V  0x1
-#define RTC_IO_SENSE2_SLP_SEL_S  16
-/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_SENSE2_SLP_IE  (BIT(15))
-#define RTC_IO_SENSE2_SLP_IE_M  (BIT(15))
-#define RTC_IO_SENSE2_SLP_IE_V  0x1
-#define RTC_IO_SENSE2_SLP_IE_S  15
-/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_SENSE2_FUN_IE  (BIT(14))
-#define RTC_IO_SENSE2_FUN_IE_M  (BIT(14))
-#define RTC_IO_SENSE2_FUN_IE_V  0x1
-#define RTC_IO_SENSE2_FUN_IE_S  14
-/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_SENSE3_FUN_SEL  0x00000003
-#define RTC_IO_SENSE3_FUN_SEL_M  ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S))
-#define RTC_IO_SENSE3_FUN_SEL_V  0x3
-#define RTC_IO_SENSE3_FUN_SEL_S  12
-/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_SENSE3_SLP_SEL  (BIT(11))
-#define RTC_IO_SENSE3_SLP_SEL_M  (BIT(11))
-#define RTC_IO_SENSE3_SLP_SEL_V  0x1
-#define RTC_IO_SENSE3_SLP_SEL_S  11
-/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_SENSE3_SLP_IE  (BIT(10))
-#define RTC_IO_SENSE3_SLP_IE_M  (BIT(10))
-#define RTC_IO_SENSE3_SLP_IE_V  0x1
-#define RTC_IO_SENSE3_SLP_IE_S  10
-/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_SENSE3_FUN_IE  (BIT(9))
-#define RTC_IO_SENSE3_FUN_IE_M  (BIT(9))
-#define RTC_IO_SENSE3_FUN_IE_V  0x1
-#define RTC_IO_SENSE3_FUN_IE_S  9
-/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_SENSE4_FUN_SEL  0x00000003
-#define RTC_IO_SENSE4_FUN_SEL_M  ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S))
-#define RTC_IO_SENSE4_FUN_SEL_V  0x3
-#define RTC_IO_SENSE4_FUN_SEL_S  7
-/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_SENSE4_SLP_SEL  (BIT(6))
-#define RTC_IO_SENSE4_SLP_SEL_M  (BIT(6))
-#define RTC_IO_SENSE4_SLP_SEL_V  0x1
-#define RTC_IO_SENSE4_SLP_SEL_S  6
-/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_SENSE4_SLP_IE  (BIT(5))
-#define RTC_IO_SENSE4_SLP_IE_M  (BIT(5))
-#define RTC_IO_SENSE4_SLP_IE_V  0x1
-#define RTC_IO_SENSE4_SLP_IE_S  5
-/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_SENSE4_FUN_IE  (BIT(4))
-#define RTC_IO_SENSE4_FUN_IE_M  (BIT(4))
-#define RTC_IO_SENSE4_FUN_IE_V  0x1
-#define RTC_IO_SENSE4_FUN_IE_S  4
-
-#define RTC_IO_ADC_PAD_REG          (DR_REG_RTCIO_BASE + 0x80)
-/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_ADC1_HOLD  (BIT(31))
-#define RTC_IO_ADC1_HOLD_M  (BIT(31))
-#define RTC_IO_ADC1_HOLD_V  0x1
-#define RTC_IO_ADC1_HOLD_S  31
-/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_ADC2_HOLD  (BIT(30))
-#define RTC_IO_ADC2_HOLD_M  (BIT(30))
-#define RTC_IO_ADC2_HOLD_V  0x1
-#define RTC_IO_ADC2_HOLD_S  30
-/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_ADC1_MUX_SEL  (BIT(29))
-#define RTC_IO_ADC1_MUX_SEL_M  (BIT(29))
-#define RTC_IO_ADC1_MUX_SEL_V  0x1
-#define RTC_IO_ADC1_MUX_SEL_S  29
-/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_ADC2_MUX_SEL  (BIT(28))
-#define RTC_IO_ADC2_MUX_SEL_M  (BIT(28))
-#define RTC_IO_ADC2_MUX_SEL_V  0x1
-#define RTC_IO_ADC2_MUX_SEL_S  28
-/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_ADC1_FUN_SEL  0x00000003
-#define RTC_IO_ADC1_FUN_SEL_M  ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S))
-#define RTC_IO_ADC1_FUN_SEL_V  0x3
-#define RTC_IO_ADC1_FUN_SEL_S  26
-/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_ADC1_SLP_SEL  (BIT(25))
-#define RTC_IO_ADC1_SLP_SEL_M  (BIT(25))
-#define RTC_IO_ADC1_SLP_SEL_V  0x1
-#define RTC_IO_ADC1_SLP_SEL_S  25
-/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_ADC1_SLP_IE  (BIT(24))
-#define RTC_IO_ADC1_SLP_IE_M  (BIT(24))
-#define RTC_IO_ADC1_SLP_IE_V  0x1
-#define RTC_IO_ADC1_SLP_IE_S  24
-/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_ADC1_FUN_IE  (BIT(23))
-#define RTC_IO_ADC1_FUN_IE_M  (BIT(23))
-#define RTC_IO_ADC1_FUN_IE_V  0x1
-#define RTC_IO_ADC1_FUN_IE_S  23
-/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_ADC2_FUN_SEL  0x00000003
-#define RTC_IO_ADC2_FUN_SEL_M  ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S))
-#define RTC_IO_ADC2_FUN_SEL_V  0x3
-#define RTC_IO_ADC2_FUN_SEL_S  21
-/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_ADC2_SLP_SEL  (BIT(20))
-#define RTC_IO_ADC2_SLP_SEL_M  (BIT(20))
-#define RTC_IO_ADC2_SLP_SEL_V  0x1
-#define RTC_IO_ADC2_SLP_SEL_S  20
-/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_ADC2_SLP_IE  (BIT(19))
-#define RTC_IO_ADC2_SLP_IE_M  (BIT(19))
-#define RTC_IO_ADC2_SLP_IE_V  0x1
-#define RTC_IO_ADC2_SLP_IE_S  19
-/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_ADC2_FUN_IE  (BIT(18))
-#define RTC_IO_ADC2_FUN_IE_M  (BIT(18))
-#define RTC_IO_ADC2_FUN_IE_V  0x1
-#define RTC_IO_ADC2_FUN_IE_S  18
-
-#define RTC_IO_PAD_DAC1_REG          (DR_REG_RTCIO_BASE + 0x84)
-/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_PDAC1_DRV  0x00000003
-#define RTC_IO_PDAC1_DRV_M  ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S))
-#define RTC_IO_PDAC1_DRV_V  0x3
-#define RTC_IO_PDAC1_DRV_S  30
-/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_PDAC1_HOLD  (BIT(29))
-#define RTC_IO_PDAC1_HOLD_M  (BIT(29))
-#define RTC_IO_PDAC1_HOLD_V  0x1
-#define RTC_IO_PDAC1_HOLD_S  29
-/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_PDAC1_RDE  (BIT(28))
-#define RTC_IO_PDAC1_RDE_M  (BIT(28))
-#define RTC_IO_PDAC1_RDE_V  0x1
-#define RTC_IO_PDAC1_RDE_S  28
-/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_PDAC1_RUE  (BIT(27))
-#define RTC_IO_PDAC1_RUE_M  (BIT(27))
-#define RTC_IO_PDAC1_RUE_V  0x1
-#define RTC_IO_PDAC1_RUE_S  27
-/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
-/*description: PAD DAC1 control code.*/
-#define RTC_IO_PDAC1_DAC  0x000000FF
-#define RTC_IO_PDAC1_DAC_M  ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S))
-#define RTC_IO_PDAC1_DAC_V  0xFF
-#define RTC_IO_PDAC1_DAC_S  19
-/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: Power on DAC1. Usually  we need to tristate PDAC1 if we power
- on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-#define RTC_IO_PDAC1_XPD_DAC  (BIT(18))
-#define RTC_IO_PDAC1_XPD_DAC_M  (BIT(18))
-#define RTC_IO_PDAC1_XPD_DAC_V  0x1
-#define RTC_IO_PDAC1_XPD_DAC_S  18
-/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_PDAC1_MUX_SEL  (BIT(17))
-#define RTC_IO_PDAC1_MUX_SEL_M  (BIT(17))
-#define RTC_IO_PDAC1_MUX_SEL_V  0x1
-#define RTC_IO_PDAC1_MUX_SEL_S  17
-/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_PDAC1_FUN_SEL  0x00000003
-#define RTC_IO_PDAC1_FUN_SEL_M  ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S))
-#define RTC_IO_PDAC1_FUN_SEL_V  0x3
-#define RTC_IO_PDAC1_FUN_SEL_S  15
-/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_PDAC1_SLP_SEL  (BIT(14))
-#define RTC_IO_PDAC1_SLP_SEL_M  (BIT(14))
-#define RTC_IO_PDAC1_SLP_SEL_V  0x1
-#define RTC_IO_PDAC1_SLP_SEL_S  14
-/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_PDAC1_SLP_IE  (BIT(13))
-#define RTC_IO_PDAC1_SLP_IE_M  (BIT(13))
-#define RTC_IO_PDAC1_SLP_IE_V  0x1
-#define RTC_IO_PDAC1_SLP_IE_S  13
-/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_PDAC1_SLP_OE  (BIT(12))
-#define RTC_IO_PDAC1_SLP_OE_M  (BIT(12))
-#define RTC_IO_PDAC1_SLP_OE_V  0x1
-#define RTC_IO_PDAC1_SLP_OE_S  12
-/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_PDAC1_FUN_IE  (BIT(11))
-#define RTC_IO_PDAC1_FUN_IE_M  (BIT(11))
-#define RTC_IO_PDAC1_FUN_IE_V  0x1
-#define RTC_IO_PDAC1_FUN_IE_S  11
-/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: Power on DAC1. Usually  we need to tristate PDAC1 if we power
- on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-#define RTC_IO_PDAC1_DAC_XPD_FORCE  (BIT(10))
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_M  (BIT(10))
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_V  0x1
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_S  10
-
-#define RTC_IO_PAD_DAC2_REG          (DR_REG_RTCIO_BASE + 0x88)
-/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_PDAC2_DRV  0x00000003
-#define RTC_IO_PDAC2_DRV_M  ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S))
-#define RTC_IO_PDAC2_DRV_V  0x3
-#define RTC_IO_PDAC2_DRV_S  30
-/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_PDAC2_HOLD  (BIT(29))
-#define RTC_IO_PDAC2_HOLD_M  (BIT(29))
-#define RTC_IO_PDAC2_HOLD_V  0x1
-#define RTC_IO_PDAC2_HOLD_S  29
-/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_PDAC2_RDE  (BIT(28))
-#define RTC_IO_PDAC2_RDE_M  (BIT(28))
-#define RTC_IO_PDAC2_RDE_V  0x1
-#define RTC_IO_PDAC2_RDE_S  28
-/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_PDAC2_RUE  (BIT(27))
-#define RTC_IO_PDAC2_RUE_M  (BIT(27))
-#define RTC_IO_PDAC2_RUE_V  0x1
-#define RTC_IO_PDAC2_RUE_S  27
-/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
-/*description: PAD DAC2 control code.*/
-#define RTC_IO_PDAC2_DAC  0x000000FF
-#define RTC_IO_PDAC2_DAC_M  ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S))
-#define RTC_IO_PDAC2_DAC_V  0xFF
-#define RTC_IO_PDAC2_DAC_S  19
-/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: Power on DAC2. Usually  we need to tristate PDAC1 if we power
- on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-#define RTC_IO_PDAC2_XPD_DAC  (BIT(18))
-#define RTC_IO_PDAC2_XPD_DAC_M  (BIT(18))
-#define RTC_IO_PDAC2_XPD_DAC_V  0x1
-#define RTC_IO_PDAC2_XPD_DAC_S  18
-/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_PDAC2_MUX_SEL  (BIT(17))
-#define RTC_IO_PDAC2_MUX_SEL_M  (BIT(17))
-#define RTC_IO_PDAC2_MUX_SEL_V  0x1
-#define RTC_IO_PDAC2_MUX_SEL_S  17
-/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_PDAC2_FUN_SEL  0x00000003
-#define RTC_IO_PDAC2_FUN_SEL_M  ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S))
-#define RTC_IO_PDAC2_FUN_SEL_V  0x3
-#define RTC_IO_PDAC2_FUN_SEL_S  15
-/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_PDAC2_SLP_SEL  (BIT(14))
-#define RTC_IO_PDAC2_SLP_SEL_M  (BIT(14))
-#define RTC_IO_PDAC2_SLP_SEL_V  0x1
-#define RTC_IO_PDAC2_SLP_SEL_S  14
-/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_PDAC2_SLP_IE  (BIT(13))
-#define RTC_IO_PDAC2_SLP_IE_M  (BIT(13))
-#define RTC_IO_PDAC2_SLP_IE_V  0x1
-#define RTC_IO_PDAC2_SLP_IE_S  13
-/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_PDAC2_SLP_OE  (BIT(12))
-#define RTC_IO_PDAC2_SLP_OE_M  (BIT(12))
-#define RTC_IO_PDAC2_SLP_OE_V  0x1
-#define RTC_IO_PDAC2_SLP_OE_S  12
-/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_PDAC2_FUN_IE  (BIT(11))
-#define RTC_IO_PDAC2_FUN_IE_M  (BIT(11))
-#define RTC_IO_PDAC2_FUN_IE_V  0x1
-#define RTC_IO_PDAC2_FUN_IE_S  11
-/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: Power on DAC2. Usually  we need to tristate PDAC2 if we power
- on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-#define RTC_IO_PDAC2_DAC_XPD_FORCE  (BIT(10))
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_M  (BIT(10))
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_V  0x1
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_S  10
-
-#define RTC_IO_XTAL_32K_PAD_REG          (DR_REG_RTCIO_BASE + 0x8c)
-/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_X32N_DRV  0x00000003
-#define RTC_IO_X32N_DRV_M  ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S))
-#define RTC_IO_X32N_DRV_V  0x3
-#define RTC_IO_X32N_DRV_S  30
-/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_X32N_HOLD  (BIT(29))
-#define RTC_IO_X32N_HOLD_M  (BIT(29))
-#define RTC_IO_X32N_HOLD_V  0x1
-#define RTC_IO_X32N_HOLD_S  29
-/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_X32N_RDE  (BIT(28))
-#define RTC_IO_X32N_RDE_M  (BIT(28))
-#define RTC_IO_X32N_RDE_V  0x1
-#define RTC_IO_X32N_RDE_S  28
-/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_X32N_RUE  (BIT(27))
-#define RTC_IO_X32N_RUE_M  (BIT(27))
-#define RTC_IO_X32N_RUE_V  0x1
-#define RTC_IO_X32N_RUE_S  27
-/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_X32P_DRV  0x00000003
-#define RTC_IO_X32P_DRV_M  ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S))
-#define RTC_IO_X32P_DRV_V  0x3
-#define RTC_IO_X32P_DRV_S  25
-/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_X32P_HOLD  (BIT(24))
-#define RTC_IO_X32P_HOLD_M  (BIT(24))
-#define RTC_IO_X32P_HOLD_V  0x1
-#define RTC_IO_X32P_HOLD_S  24
-/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_X32P_RDE  (BIT(23))
-#define RTC_IO_X32P_RDE_M  (BIT(23))
-#define RTC_IO_X32P_RDE_V  0x1
-#define RTC_IO_X32P_RDE_S  23
-/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_X32P_RUE  (BIT(22))
-#define RTC_IO_X32P_RUE_M  (BIT(22))
-#define RTC_IO_X32P_RUE_V  0x1
-#define RTC_IO_X32P_RUE_S  22
-/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */
-/*description: 32K XTAL bias current DAC.*/
-#define RTC_IO_DAC_XTAL_32K  0x00000003
-#define RTC_IO_DAC_XTAL_32K_M  ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S))
-#define RTC_IO_DAC_XTAL_32K_V  0x3
-#define RTC_IO_DAC_XTAL_32K_S  20
-/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Power up 32kHz crystal oscillator*/
-#define RTC_IO_XPD_XTAL_32K  (BIT(19))
-#define RTC_IO_XPD_XTAL_32K_M  (BIT(19))
-#define RTC_IO_XPD_XTAL_32K_V  0x1
-#define RTC_IO_XPD_XTAL_32K_S  19
-/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_X32N_MUX_SEL  (BIT(18))
-#define RTC_IO_X32N_MUX_SEL_M  (BIT(18))
-#define RTC_IO_X32N_MUX_SEL_V  0x1
-#define RTC_IO_X32N_MUX_SEL_S  18
-/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_X32P_MUX_SEL  (BIT(17))
-#define RTC_IO_X32P_MUX_SEL_M  (BIT(17))
-#define RTC_IO_X32P_MUX_SEL_V  0x1
-#define RTC_IO_X32P_MUX_SEL_S  17
-/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_X32N_FUN_SEL  0x00000003
-#define RTC_IO_X32N_FUN_SEL_M  ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S))
-#define RTC_IO_X32N_FUN_SEL_V  0x3
-#define RTC_IO_X32N_FUN_SEL_S  15
-/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_X32N_SLP_SEL  (BIT(14))
-#define RTC_IO_X32N_SLP_SEL_M  (BIT(14))
-#define RTC_IO_X32N_SLP_SEL_V  0x1
-#define RTC_IO_X32N_SLP_SEL_S  14
-/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_X32N_SLP_IE  (BIT(13))
-#define RTC_IO_X32N_SLP_IE_M  (BIT(13))
-#define RTC_IO_X32N_SLP_IE_V  0x1
-#define RTC_IO_X32N_SLP_IE_S  13
-/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_X32N_SLP_OE  (BIT(12))
-#define RTC_IO_X32N_SLP_OE_M  (BIT(12))
-#define RTC_IO_X32N_SLP_OE_V  0x1
-#define RTC_IO_X32N_SLP_OE_S  12
-/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_X32N_FUN_IE  (BIT(11))
-#define RTC_IO_X32N_FUN_IE_M  (BIT(11))
-#define RTC_IO_X32N_FUN_IE_V  0x1
-#define RTC_IO_X32N_FUN_IE_S  11
-/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_X32P_FUN_SEL  0x00000003
-#define RTC_IO_X32P_FUN_SEL_M  ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S))
-#define RTC_IO_X32P_FUN_SEL_V  0x3
-#define RTC_IO_X32P_FUN_SEL_S  9
-/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_X32P_SLP_SEL  (BIT(8))
-#define RTC_IO_X32P_SLP_SEL_M  (BIT(8))
-#define RTC_IO_X32P_SLP_SEL_V  0x1
-#define RTC_IO_X32P_SLP_SEL_S  8
-/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_X32P_SLP_IE  (BIT(7))
-#define RTC_IO_X32P_SLP_IE_M  (BIT(7))
-#define RTC_IO_X32P_SLP_IE_V  0x1
-#define RTC_IO_X32P_SLP_IE_S  7
-/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_X32P_SLP_OE  (BIT(6))
-#define RTC_IO_X32P_SLP_OE_M  (BIT(6))
-#define RTC_IO_X32P_SLP_OE_V  0x1
-#define RTC_IO_X32P_SLP_OE_S  6
-/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_X32P_FUN_IE  (BIT(5))
-#define RTC_IO_X32P_FUN_IE_M  (BIT(5))
-#define RTC_IO_X32P_FUN_IE_V  0x1
-#define RTC_IO_X32P_FUN_IE_S  5
-/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */
-/*description: 32K XTAL resistor bias control.*/
-#define RTC_IO_DRES_XTAL_32K  0x00000003
-#define RTC_IO_DRES_XTAL_32K_M  ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S))
-#define RTC_IO_DRES_XTAL_32K_V  0x3
-#define RTC_IO_DRES_XTAL_32K_S  3
-/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */
-/*description: 32K XTAL self-bias reference control.*/
-#define RTC_IO_DBIAS_XTAL_32K  0x00000003
-#define RTC_IO_DBIAS_XTAL_32K_M  ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S))
-#define RTC_IO_DBIAS_XTAL_32K_V  0x3
-#define RTC_IO_DBIAS_XTAL_32K_S  1
-
-#define RTC_IO_TOUCH_CFG_REG          (DR_REG_RTCIO_BASE + 0x90)
-/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: touch sensor bias power on.*/
-#define RTC_IO_TOUCH_XPD_BIAS  (BIT(31))
-#define RTC_IO_TOUCH_XPD_BIAS_M  (BIT(31))
-#define RTC_IO_TOUCH_XPD_BIAS_V  0x1
-#define RTC_IO_TOUCH_XPD_BIAS_S  31
-/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */
-/*description: touch sensor saw wave top voltage.*/
-#define RTC_IO_TOUCH_DREFH  0x00000003
-#define RTC_IO_TOUCH_DREFH_M  ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S))
-#define RTC_IO_TOUCH_DREFH_V  0x3
-#define RTC_IO_TOUCH_DREFH_S  29
-/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
-/*description: touch sensor saw wave bottom voltage.*/
-#define RTC_IO_TOUCH_DREFL  0x00000003
-#define RTC_IO_TOUCH_DREFL_M  ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S))
-#define RTC_IO_TOUCH_DREFL_V  0x3
-#define RTC_IO_TOUCH_DREFL_S  27
-/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */
-/*description: touch sensor saw wave voltage range.*/
-#define RTC_IO_TOUCH_DRANGE  0x00000003
-#define RTC_IO_TOUCH_DRANGE_M  ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S))
-#define RTC_IO_TOUCH_DRANGE_V  0x3
-#define RTC_IO_TOUCH_DRANGE_S  25
-/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */
-/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When
- BIAS_SLEEP  this setting is available*/
-#define RTC_IO_TOUCH_DCUR  0x00000003
-#define RTC_IO_TOUCH_DCUR_M  ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S))
-#define RTC_IO_TOUCH_DCUR_V  0x3
-#define RTC_IO_TOUCH_DCUR_S  23
-
-#define RTC_IO_TOUCH_PAD0_REG          (DR_REG_RTCIO_BASE + 0x94)
-/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD0_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD0_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD0_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD0_HOLD_S  31
-/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD0_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD0_DRV_M  ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S))
-#define RTC_IO_TOUCH_PAD0_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD0_DRV_S  29
-/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD0_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD0_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD0_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD0_RDE_S  28
-/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD0_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD0_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD0_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD0_RUE_S  27
-/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD0_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD0_DAC_M  ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S))
-#define RTC_IO_TOUCH_PAD0_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD0_DAC_S  23
-/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD0_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD0_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD0_START_V  0x1
-#define RTC_IO_TOUCH_PAD0_START_S  22
-/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD0_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD0_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD0_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD0_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD0_XPD_S  20
-/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD0_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD0_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_M  ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD0_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD0_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD0_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD0_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD0_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD0_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD0_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD0_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD0_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD0_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD0_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD0_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD0_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/
-#define RTC_IO_TOUCH_PAD0_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD1_REG          (DR_REG_RTCIO_BASE + 0x98)
-/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: */
-#define RTC_IO_TOUCH_PAD1_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD1_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD1_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD1_HOLD_S  31
-/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD1_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD1_DRV_M  ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S))
-#define RTC_IO_TOUCH_PAD1_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD1_DRV_S  29
-/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD1_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD1_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD1_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD1_RDE_S  28
-/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD1_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD1_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD1_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD1_RUE_S  27
-/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD1_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD1_DAC_M  ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S))
-#define RTC_IO_TOUCH_PAD1_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD1_DAC_S  23
-/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD1_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD1_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD1_START_V  0x1
-#define RTC_IO_TOUCH_PAD1_START_S  22
-/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD1_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD1_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD1_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD1_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD1_XPD_S  20
-/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD1_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD1_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_M  ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD1_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD1_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD1_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD1_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD1_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD1_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD1_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD1_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD1_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD1_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD1_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD1_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD1_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/
-#define RTC_IO_TOUCH_PAD1_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD2_REG          (DR_REG_RTCIO_BASE + 0x9c)
-/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD2_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD2_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD2_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD2_HOLD_S  31
-/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD2_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD2_DRV_M  ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S))
-#define RTC_IO_TOUCH_PAD2_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD2_DRV_S  29
-/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD2_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD2_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD2_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD2_RDE_S  28
-/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD2_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD2_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD2_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD2_RUE_S  27
-/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD2_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD2_DAC_M  ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S))
-#define RTC_IO_TOUCH_PAD2_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD2_DAC_S  23
-/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD2_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD2_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD2_START_V  0x1
-#define RTC_IO_TOUCH_PAD2_START_S  22
-/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD2_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD2_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD2_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD2_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD2_XPD_S  20
-/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD2_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD2_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_M  ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD2_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD2_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD2_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD2_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD2_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD2_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD2_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD2_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD2_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD2_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD2_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD2_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD2_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/
-#define RTC_IO_TOUCH_PAD2_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD3_REG          (DR_REG_RTCIO_BASE + 0xa0)
-/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD3_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD3_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD3_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD3_HOLD_S  31
-/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD3_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD3_DRV_M  ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S))
-#define RTC_IO_TOUCH_PAD3_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD3_DRV_S  29
-/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD3_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD3_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD3_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD3_RDE_S  28
-/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD3_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD3_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD3_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD3_RUE_S  27
-/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD3_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD3_DAC_M  ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S))
-#define RTC_IO_TOUCH_PAD3_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD3_DAC_S  23
-/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD3_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD3_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD3_START_V  0x1
-#define RTC_IO_TOUCH_PAD3_START_S  22
-/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD3_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD3_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD3_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD3_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD3_XPD_S  20
-/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD3_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD3_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_M  ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD3_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD3_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD3_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD3_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD3_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD3_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD3_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD3_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD3_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD3_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD3_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD3_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD3_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/
-#define RTC_IO_TOUCH_PAD3_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD4_REG          (DR_REG_RTCIO_BASE + 0xa4)
-/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD4_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD4_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD4_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD4_HOLD_S  31
-/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD4_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD4_DRV_M  ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S))
-#define RTC_IO_TOUCH_PAD4_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD4_DRV_S  29
-/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD4_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD4_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD4_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD4_RDE_S  28
-/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD4_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD4_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD4_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD4_RUE_S  27
-/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD4_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD4_DAC_M  ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S))
-#define RTC_IO_TOUCH_PAD4_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD4_DAC_S  23
-/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD4_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD4_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD4_START_V  0x1
-#define RTC_IO_TOUCH_PAD4_START_S  22
-/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD4_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD4_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD4_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD4_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD4_XPD_S  20
-/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD4_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD4_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_M  ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD4_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD4_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD4_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD4_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD4_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD4_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD4_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD4_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD4_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD4_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD4_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD4_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD4_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/
-#define RTC_IO_TOUCH_PAD4_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD5_REG          (DR_REG_RTCIO_BASE + 0xa8)
-/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD5_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD5_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD5_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD5_HOLD_S  31
-/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD5_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD5_DRV_M  ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S))
-#define RTC_IO_TOUCH_PAD5_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD5_DRV_S  29
-/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD5_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD5_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD5_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD5_RDE_S  28
-/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD5_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD5_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD5_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD5_RUE_S  27
-/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD5_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD5_DAC_M  ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S))
-#define RTC_IO_TOUCH_PAD5_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD5_DAC_S  23
-/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD5_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD5_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD5_START_V  0x1
-#define RTC_IO_TOUCH_PAD5_START_S  22
-/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD5_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD5_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD5_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD5_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD5_XPD_S  20
-/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD5_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD5_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_M  ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD5_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD5_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD5_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD5_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD5_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD5_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD5_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD5_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD5_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD5_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD5_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD5_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD5_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/
-#define RTC_IO_TOUCH_PAD5_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD6_REG          (DR_REG_RTCIO_BASE + 0xac)
-/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD6_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD6_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD6_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD6_HOLD_S  31
-/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD6_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD6_DRV_M  ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S))
-#define RTC_IO_TOUCH_PAD6_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD6_DRV_S  29
-/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD6_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD6_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD6_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD6_RDE_S  28
-/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD6_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD6_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD6_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD6_RUE_S  27
-/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD6_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD6_DAC_M  ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S))
-#define RTC_IO_TOUCH_PAD6_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD6_DAC_S  23
-/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD6_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD6_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD6_START_V  0x1
-#define RTC_IO_TOUCH_PAD6_START_S  22
-/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD6_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD6_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD6_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD6_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD6_XPD_S  20
-/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD6_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD6_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_M  ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD6_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD6_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD6_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD6_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD6_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD6_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD6_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD6_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD6_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD6_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD6_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD6_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD6_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/
-#define RTC_IO_TOUCH_PAD6_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD7_REG          (DR_REG_RTCIO_BASE + 0xb0)
-/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD7_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD7_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD7_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD7_HOLD_S  31
-/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD7_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD7_DRV_M  ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S))
-#define RTC_IO_TOUCH_PAD7_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD7_DRV_S  29
-/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD7_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD7_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD7_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD7_RDE_S  28
-/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD7_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD7_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD7_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD7_RUE_S  27
-/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD7_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD7_DAC_M  ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S))
-#define RTC_IO_TOUCH_PAD7_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD7_DAC_S  23
-/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD7_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD7_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD7_START_V  0x1
-#define RTC_IO_TOUCH_PAD7_START_S  22
-/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD7_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD7_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD7_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD7_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD7_XPD_S  20
-/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD7_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD7_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_M  ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD7_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD7_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD7_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD7_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD7_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD7_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD7_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD7_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD7_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD7_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD7_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD7_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD7_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/
-#define RTC_IO_TOUCH_PAD7_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD8_REG          (DR_REG_RTCIO_BASE + 0xb4)
-/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD8_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD8_DAC_M  ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S))
-#define RTC_IO_TOUCH_PAD8_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD8_DAC_S  23
-/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD8_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD8_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD8_START_V  0x1
-#define RTC_IO_TOUCH_PAD8_START_S  22
-/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD8_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD8_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD8_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD8_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD8_XPD_S  20
-/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
-#define RTC_IO_TOUCH_PAD8_TO_GPIO  (BIT(19))
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_S  19
-
-#define RTC_IO_TOUCH_PAD9_REG          (DR_REG_RTCIO_BASE + 0xb8)
-/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD9_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD9_DAC_M  ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S))
-#define RTC_IO_TOUCH_PAD9_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD9_DAC_S  23
-/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD9_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD9_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD9_START_V  0x1
-#define RTC_IO_TOUCH_PAD9_START_S  22
-/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD9_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD9_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD9_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD9_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD9_XPD_S  20
-/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
-#define RTC_IO_TOUCH_PAD9_TO_GPIO  (BIT(19))
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_S  19
-
-#define RTC_IO_EXT_WAKEUP0_REG          (DR_REG_RTCIO_BASE + 0xbc)
-/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
-/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/
-#define RTC_IO_EXT_WAKEUP0_SEL  0x0000001F
-#define RTC_IO_EXT_WAKEUP0_SEL_M  ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
-#define RTC_IO_EXT_WAKEUP0_SEL_V  0x1F
-#define RTC_IO_EXT_WAKEUP0_SEL_S  27
-
-#define RTC_IO_XTL_EXT_CTR_REG          (DR_REG_RTCIO_BASE + 0xc0)
-/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
-/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select
- GPIO2 ...Ò17Ó select GPIO17*/
-#define RTC_IO_XTL_EXT_CTR_SEL  0x0000001F
-#define RTC_IO_XTL_EXT_CTR_SEL_M  ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S))
-#define RTC_IO_XTL_EXT_CTR_SEL_V  0x1F
-#define RTC_IO_XTL_EXT_CTR_SEL_S  27
-
-#define RTC_IO_SAR_I2C_IO_REG          (DR_REG_RTCIO_BASE + 0xc4)
-/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/
-#define RTC_IO_SAR_I2C_SDA_SEL  0x00000003
-#define RTC_IO_SAR_I2C_SDA_SEL_M  ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S))
-#define RTC_IO_SAR_I2C_SDA_SEL_V  0x3
-#define RTC_IO_SAR_I2C_SDA_SEL_S  30
-/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/
-#define RTC_IO_SAR_I2C_SCL_SEL  0x00000003
-#define RTC_IO_SAR_I2C_SCL_SEL_M  ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S))
-#define RTC_IO_SAR_I2C_SCL_SEL_V  0x3
-#define RTC_IO_SAR_I2C_SCL_SEL_S  28
-/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */
-/*description: */
-#define RTC_IO_SAR_DEBUG_BIT_SEL  0x0000001F
-#define RTC_IO_SAR_DEBUG_BIT_SEL_M  ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S))
-#define RTC_IO_SAR_DEBUG_BIT_SEL_V  0x1F
-#define RTC_IO_SAR_DEBUG_BIT_SEL_S  23
-
-#define RTC_IO_DATE_REG          (DR_REG_RTCIO_BASE + 0xc8)
-/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */
-/*description: date*/
-#define RTC_IO_IO_DATE  0x0FFFFFFF
-#define RTC_IO_IO_DATE_M  ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))
-#define RTC_IO_IO_DATE_V  0xFFFFFFF
-#define RTC_IO_IO_DATE_S  0
-#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160
-
-
-
-
-#endif /*_SOC_RTC_IO_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/rtc_io_struct.h b/tools/sdk/include/soc/soc/rtc_io_struct.h
deleted file mode 100644
index d82f1bd8c04..00000000000
--- a/tools/sdk/include/soc/soc/rtc_io_struct.h
+++ /dev/null
@@ -1,293 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_RTC_IO_STRUCT_H_
-#define _SOC_RTC_IO_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t reserved0:        14;
-            uint32_t data:18;              /*GPIO0~17 output value*/
-        };
-        uint32_t val;
-    } out;
-    union {
-        struct {
-            uint32_t reserved0:             14;
-            uint32_t w1ts:18;         /*GPIO0~17 output value write 1 to set*/
-        };
-        uint32_t val;
-    } out_w1ts;
-    union {
-        struct {
-            uint32_t reserved0:             14;
-            uint32_t w1tc:18;         /*GPIO0~17 output value write 1 to clear*/
-        };
-        uint32_t val;
-    } out_w1tc;
-    union {
-        struct {
-            uint32_t reserved0:      14;
-            uint32_t enable:18;                /*GPIO0~17 output enable*/
-        };
-        uint32_t val;
-    } enable;
-    union {
-        struct {
-            uint32_t reserved0:           14;
-            uint32_t w1ts:18;           /*GPIO0~17 output enable write 1 to set*/
-        };
-        uint32_t val;
-    } enable_w1ts;
-    union {
-        struct {
-            uint32_t reserved0:           14;
-            uint32_t w1tc:18;           /*GPIO0~17 output enable write 1 to clear*/
-        };
-        uint32_t val;
-    } enable_w1tc;
-    union {
-        struct {
-            uint32_t reserved0:          14;
-            uint32_t status:18;            /*GPIO0~17 interrupt status*/
-        };
-        uint32_t val;
-    } status;
-    union {
-        struct {
-            uint32_t reserved0:               14;
-            uint32_t w1ts:18;       /*GPIO0~17 interrupt status write 1 to set*/
-        };
-        uint32_t val;
-    } status_w1ts;
-    union {
-        struct {
-            uint32_t reserved0:               14;
-            uint32_t w1tc:18;       /*GPIO0~17 interrupt status write 1 to clear*/
-        };
-        uint32_t val;
-    } status_w1tc;
-    union {
-        struct {
-            uint32_t reserved0:       14;
-            uint32_t in:18;               /*GPIO0~17 input value*/
-        };
-        uint32_t val;
-    } in_val;
-    union {
-        struct {
-            uint32_t reserved0:                   2;
-            uint32_t pad_driver:    1;    /*if set to 0: normal output  if set to 1: open drain*/
-            uint32_t reserved3:                   4;
-            uint32_t int_type:      3;    /*if set to 0: GPIO interrupt disable  if set to 1: rising edge trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-            uint32_t wakeup_enable: 1;    /*GPIO wake up enable  only available in light sleep*/
-            uint32_t reserved11:                 21;
-        };
-        uint32_t val;
-    } pin[18];
-    union {
-        struct {
-            uint32_t sel0:          5;
-            uint32_t sel1:          5;
-            uint32_t sel2:          5;
-            uint32_t sel3:          5;
-            uint32_t sel4:          5;
-            uint32_t no_gating_12m: 1;
-            uint32_t reserved26:              6;
-        };
-        uint32_t val;
-    } debug_sel;
-    uint32_t dig_pad_hold;                              /*select the digital pad hold value.*/
-    union {
-        struct {
-            uint32_t reserved0: 30;
-            uint32_t hall_phase: 1;                     /*Reverse phase of hall sensor*/
-            uint32_t xpd_hall:   1;                     /*Power on hall sensor and connect to VP and VN*/
-        };
-        uint32_t val;
-    } hall_sens;
-    union {
-        struct {
-            uint32_t reserved0:      4;
-            uint32_t sense4_fun_ie:  1;                 /*the input enable of the pad*/
-            uint32_t sense4_slp_ie:  1;                 /*the input enable of the pad in sleep status*/
-            uint32_t sense4_slp_sel: 1;                 /*the sleep status selection signal of the pad*/
-            uint32_t sense4_fun_sel: 2;                 /*the functional selection signal of the pad*/
-            uint32_t sense3_fun_ie:  1;                 /*the input enable of the pad*/
-            uint32_t sense3_slp_ie:  1;                 /*the input enable of the pad in sleep status*/
-            uint32_t sense3_slp_sel: 1;                 /*the sleep status selection signal of the pad*/
-            uint32_t sense3_fun_sel: 2;                 /*the functional selection signal of the pad*/
-            uint32_t sense2_fun_ie:  1;                 /*the input enable of the pad*/
-            uint32_t sense2_slp_ie:  1;                 /*the input enable of the pad in sleep status*/
-            uint32_t sense2_slp_sel: 1;                 /*the sleep status selection signal of the pad*/
-            uint32_t sense2_fun_sel: 2;                 /*the functional selection signal of the pad*/
-            uint32_t sense1_fun_ie:  1;                 /*the input enable of the pad*/
-            uint32_t sense1_slp_ie:  1;                 /*the input enable of the pad in sleep status*/
-            uint32_t sense1_slp_sel: 1;                 /*the sleep status selection signal of the pad*/
-            uint32_t sense1_fun_sel: 2;                 /*the functional selection signal of the pad*/
-            uint32_t sense4_mux_sel: 1;                 /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t sense3_mux_sel: 1;                 /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t sense2_mux_sel: 1;                 /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t sense1_mux_sel: 1;                 /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t sense4_hold:    1;                 /*hold the current value of the output when setting the hold to �1�*/
-            uint32_t sense3_hold:    1;                 /*hold the current value of the output when setting the hold to �1�*/
-            uint32_t sense2_hold:    1;                 /*hold the current value of the output when setting the hold to �1�*/
-            uint32_t sense1_hold:    1;                 /*hold the current value of the output when setting the hold to �1�*/
-        };
-        uint32_t val;
-    } sensor_pads;
-    union {
-        struct {
-            uint32_t reserved0:   18;
-            uint32_t adc2_fun_ie:  1;                   /*the input enable of the pad*/
-            uint32_t adc2_slp_ie:  1;                   /*the input enable of the pad in sleep status*/
-            uint32_t adc2_slp_sel: 1;                   /*the sleep status selection signal of the pad*/
-            uint32_t adc2_fun_sel: 2;                   /*the functional selection signal of the pad*/
-            uint32_t adc1_fun_ie:  1;                   /*the input enable of the pad*/
-            uint32_t adc1_slp_ie:  1;                   /*the input enable of the pad in sleep status*/
-            uint32_t adc1_slp_sel: 1;                   /*the sleep status selection signal of the pad*/
-            uint32_t adc1_fun_sel: 2;                   /*the functional selection signal of the pad*/
-            uint32_t adc2_mux_sel: 1;                   /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t adc1_mux_sel: 1;                   /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t adc2_hold:    1;                   /*hold the current value of the output when setting the hold to �1�*/
-            uint32_t adc1_hold:    1;                   /*hold the current value of the output when setting the hold to �1�*/
-        };
-        uint32_t val;
-    } adc_pad;
-    union {
-        struct {
-            uint32_t reserved0:          10;
-            uint32_t dac_xpd_force: 1;            /*Power on DAC1. Usually  we need to tristate PDAC1 if we power on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-            uint32_t fun_ie:        1;            /*the input enable of the pad*/
-            uint32_t slp_oe:        1;            /*the output enable of the pad in sleep status*/
-            uint32_t slp_ie:        1;            /*the input enable of the pad in sleep status*/
-            uint32_t slp_sel:       1;            /*the sleep status selection signal of the pad*/
-            uint32_t fun_sel:       2;            /*the functional selection signal of the pad*/
-            uint32_t mux_sel:       1;            /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t xpd_dac:       1;            /*Power on DAC1. Usually  we need to tristate PDAC1 if we power on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-            uint32_t dac:           8;            /*PAD DAC1 control code.*/
-            uint32_t rue:           1;            /*the pull up enable of the pad*/
-            uint32_t rde:           1;            /*the pull down enable of the pad*/
-            uint32_t hold:          1;            /*hold the current value of the output when setting the hold to �1�*/
-            uint32_t drv:           2;            /*the driver strength of the pad*/
-        };
-        uint32_t val;
-    } pad_dac[2];
-    union {
-        struct {
-            uint32_t reserved0:      1;
-            uint32_t dbias_xtal_32k: 2;                 /*32K XTAL self-bias reference control.*/
-            uint32_t dres_xtal_32k:  2;                 /*32K XTAL resistor bias control.*/
-            uint32_t x32p_fun_ie:    1;                 /*the input enable of the pad*/
-            uint32_t x32p_slp_oe:    1;                 /*the output enable of the pad in sleep status*/
-            uint32_t x32p_slp_ie:    1;                 /*the input enable of the pad in sleep status*/
-            uint32_t x32p_slp_sel:   1;                 /*the sleep status selection signal of the pad*/
-            uint32_t x32p_fun_sel:   2;                 /*the functional selection signal of the pad*/
-            uint32_t x32n_fun_ie:    1;                 /*the input enable of the pad*/
-            uint32_t x32n_slp_oe:    1;                 /*the output enable of the pad in sleep status*/
-            uint32_t x32n_slp_ie:    1;                 /*the input enable of the pad in sleep status*/
-            uint32_t x32n_slp_sel:   1;                 /*the sleep status selection signal of the pad*/
-            uint32_t x32n_fun_sel:   2;                 /*the functional selection signal of the pad*/
-            uint32_t x32p_mux_sel:   1;                 /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t x32n_mux_sel:   1;                 /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t xpd_xtal_32k:   1;                 /*Power up 32kHz crystal oscillator*/
-            uint32_t dac_xtal_32k:   2;                 /*32K XTAL bias current DAC.*/
-            uint32_t x32p_rue:       1;                 /*the pull up enable of the pad*/
-            uint32_t x32p_rde:       1;                 /*the pull down enable of the pad*/
-            uint32_t x32p_hold:      1;                 /*hold the current value of the output when setting the hold to �1�*/
-            uint32_t x32p_drv:       2;                 /*the driver strength of the pad*/
-            uint32_t x32n_rue:       1;                 /*the pull up enable of the pad*/
-            uint32_t x32n_rde:       1;                 /*the pull down enable of the pad*/
-            uint32_t x32n_hold:      1;                 /*hold the current value of the output when setting the hold to �1�*/
-            uint32_t x32n_drv:       2;                 /*the driver strength of the pad*/
-        };
-        uint32_t val;
-    } xtal_32k_pad;
-    union {
-        struct {
-            uint32_t reserved0:     23;
-            uint32_t dcur:     2;                 /*touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP  this setting is available*/
-            uint32_t drange:   2;                 /*touch sensor saw wave voltage range.*/
-            uint32_t drefl:    2;                 /*touch sensor saw wave bottom voltage.*/
-            uint32_t drefh:    2;                 /*touch sensor saw wave top voltage.*/
-            uint32_t xpd_bias: 1;                 /*touch sensor bias power on.*/
-        };
-        uint32_t val;
-    } touch_cfg;
-    union {
-        struct {
-            uint32_t reserved0:         12;
-            uint32_t to_gpio: 1;             /*connect the rtc pad input to digital pad input �0� is availbale GPIO4*/
-            uint32_t fun_ie:  1;             /*the input enable of the pad*/
-            uint32_t slp_oe:  1;             /*the output enable of the pad in sleep status*/
-            uint32_t slp_ie:  1;             /*the input enable of the pad in sleep status*/
-            uint32_t slp_sel: 1;             /*the sleep status selection signal of the pad*/
-            uint32_t fun_sel: 2;             /*the functional selection signal of the pad*/
-            uint32_t mux_sel: 1;             /*�1� select the digital function  �0�slection the rtc function*/
-            uint32_t xpd:     1;             /*touch sensor power on.*/
-            uint32_t tie_opt: 1;             /*default touch sensor tie option. 0: tie low  1: tie high.*/
-            uint32_t start:   1;             /*start touch sensor.*/
-            uint32_t dac:     3;             /*touch sensor slope control. 3-bit for each touch panel  default 100.*/
-            uint32_t reserved26:         1;
-            uint32_t rue:     1;             /*the pull up enable of the pad*/
-            uint32_t rde:     1;             /*the pull down enable of the pad*/
-            uint32_t drv:     2;             /*the driver strength of the pad*/
-            uint32_t hold:    1;             /*hold the current value of the output when setting the hold to �1�*/
-        };
-        uint32_t val;
-    } touch_pad[10];
-    union {
-        struct {
-            uint32_t reserved0:      27;
-            uint32_t sel: 5;                /*select the wakeup source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/
-        };
-        uint32_t val;
-    } ext_wakeup0;
-    union {
-        struct {
-            uint32_t reserved0:      27;
-            uint32_t sel: 5;                /*select the external xtl power source �0� select GPIO0 �1� select GPIO2 ...�17� select GPIO17*/
-        };
-        uint32_t val;
-    } xtl_ext_ctr;
-    union {
-        struct {
-            uint32_t reserved0:        23;
-            uint32_t debug_bit_sel: 5;
-            uint32_t scl_sel:   2;              /*�0� using TOUCH_PAD[0] as i2c clk �1� using TOUCH_PAD[2] as i2c clk*/
-            uint32_t sda_sel:   2;              /*�0� using TOUCH_PAD[1] as i2c sda �1� using TOUCH_PAD[3] as i2c sda*/
-        };
-        uint32_t val;
-    } sar_i2c_io;
-    union {
-        struct {
-            uint32_t date:      28;                     /*date*/
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    } date;
-} rtc_io_dev_t;
-extern rtc_io_dev_t RTCIO;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_RTC_IO_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/rtc_periph.h b/tools/sdk/include/soc/soc/rtc_periph.h
deleted file mode 100644
index 832186c3d8f..00000000000
--- a/tools/sdk/include/soc/soc/rtc_periph.h
+++ /dev/null
@@ -1,62 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_RTC_PERIPH_H
-#define _SOC_RTC_PERIPH_H
-#include <stdint.h>
-#include "soc/rtc_io_reg.h"
-#include "soc/rtc_cntl_reg.h"
-#include "soc/rtc_gpio_channel.h"
-#include "soc/gpio_pins.h"
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @brief Pin function information for a single GPIO pad's RTC functions.
- *
- * This is an internal function of the driver, and is not usually useful
- * for external use.
- */
-typedef struct {
-    uint32_t reg;       /*!< Register of RTC pad, or 0 if not an RTC GPIO */
-    uint32_t mux;       /*!< Bit mask for selecting digital pad or RTC pad */
-    uint32_t func;      /*!< Shift of pad function (FUN_SEL) field */
-    uint32_t ie;        /*!< Mask of input enable */
-    uint32_t pullup;    /*!< Mask of pullup enable */
-    uint32_t pulldown;  /*!< Mask of pulldown enable */
-    uint32_t slpsel;    /*!< If slpsel bit is set, slpie will be used as pad input enabled signal in sleep mode */
-    uint32_t slpie;     /*!< Mask of input enable in sleep mode */
-    uint32_t hold;      /*!< Mask of hold enable */
-    uint32_t hold_force;/*!< Mask of hold_force bit for RTC IO in RTC_CNTL_HOLD_FORCE_REG */
-    uint32_t drv_v;     /*!< Mask of drive capability */
-    uint32_t drv_s;     /*!< Offset of drive capability */
-    int rtc_num;        /*!< RTC IO number, or -1 if not an RTC GPIO */
-} rtc_gpio_desc_t;
-
-/**
- * @brief Provides access to a constant table of RTC I/O pin
- * function information.
- *
- * This is an internal function of the driver, and is not usually useful
- * for external use.
- */
-extern const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _SOC_RTC_PERIPH_H
diff --git a/tools/sdk/include/soc/soc/rtc_wdt.h b/tools/sdk/include/soc/soc/rtc_wdt.h
deleted file mode 100644
index bdaea942b4d..00000000000
--- a/tools/sdk/include/soc/soc/rtc_wdt.h
+++ /dev/null
@@ -1,202 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-/* Recommendation of using API RTC_WDT.
-1) Setting and enabling rtc_wdt:
-@code
-    rtc_wdt_protect_off();
-    rtc_wdt_disable();
-    rtc_wdt_set_length_of_reset_signal(RTC_WDT_SYS_RESET_SIG, RTC_WDT_LENGTH_3_2us);
-    rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_RESET_SYSTEM); //RTC_WDT_STAGE_ACTION_RESET_SYSTEM or RTC_WDT_STAGE_ACTION_RESET_RTC
-    rtc_wdt_set_time(RTC_WDT_STAGE0, 7000);     // timeout rtd_wdt 7000ms.
-    rtc_wdt_enable();
-    rtc_wdt_protect_on();
- @endcode
-
-* If you use this option RTC_WDT_STAGE_ACTION_RESET_SYSTEM then after reset you can see these messages.
-They can help to understand where the CPUs were when the WDT was triggered.
-    W (30) boot: PRO CPU has been reset by WDT.
-	W (30) boot: WDT reset info: PRO CPU PC=0x400xxxxx
-	... function where it happened
-
-	W (31) boot: WDT reset info: APP CPU PC=0x400xxxxx
-	... function where it happened
-
-* If you use this option RTC_WDT_STAGE_ACTION_RESET_RTC then you will see message (rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)) 
-without description where were CPUs when it happened.
-
-2) Reset counter of rtc_wdt:
-@code
-    rtc_wdt_feed();
-@endcode
-
-3) Disable rtc_wdt:
-@code
-    rtc_wdt_disable();
-@endcode
- */
-
-#ifndef _SOC_RTC_WDT_H
-#define _SOC_RTC_WDT_H
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "soc/rtc_cntl_reg.h"
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/// List of stage of rtc watchdog. WDT has 4 stage.
-typedef enum {
-    RTC_WDT_STAGE0 = 0,     /*!< Stage 0 */
-    RTC_WDT_STAGE1 = 1,     /*!< Stage 1 */
-    RTC_WDT_STAGE2 = 2,     /*!< Stage 2 */
-    RTC_WDT_STAGE3 = 3      /*!< Stage 3 */
-} rtc_wdt_stage_t;
-
-/// List of action. When the time of stage expires this action will be triggered.
-typedef enum {
-    RTC_WDT_STAGE_ACTION_OFF            = RTC_WDT_STG_SEL_OFF,          /*!< Disabled. This stage will have no effects on the system. */
-    RTC_WDT_STAGE_ACTION_INTERRUPT      = RTC_WDT_STG_SEL_INT,          /*!< Trigger an interrupt. When the stage expires an interrupt is triggered. */
-    RTC_WDT_STAGE_ACTION_RESET_CPU      = RTC_WDT_STG_SEL_RESET_CPU,    /*!< Reset a CPU core. */
-    RTC_WDT_STAGE_ACTION_RESET_SYSTEM   = RTC_WDT_STG_SEL_RESET_SYSTEM, /*!< Reset the main system includes the CPU and all peripherals. The RTC is an exception to this, and it will not be reset. */
-    RTC_WDT_STAGE_ACTION_RESET_RTC      = RTC_WDT_STG_SEL_RESET_RTC     /*!< Reset the main system and the RTC. */
-} rtc_wdt_stage_action_t;
-
-/// Type of reset signal
-typedef enum {
-    RTC_WDT_SYS_RESET_SIG = 0,     /*!< System reset signal length selection */
-    RTC_WDT_CPU_RESET_SIG = 1      /*!< CPU reset signal length selection */
-} rtc_wdt_reset_sig_t;
-
-/// Length of reset signal
-typedef enum {
-    RTC_WDT_LENGTH_100ns = 0,     /*!< 100 ns */
-    RTC_WDT_LENGTH_200ns = 1,     /*!< 200 ns */
-    RTC_WDT_LENGTH_300ns = 2,     /*!< 300 ns */
-    RTC_WDT_LENGTH_400ns = 3,     /*!< 400 ns */
-    RTC_WDT_LENGTH_500ns = 4,     /*!< 500 ns */
-    RTC_WDT_LENGTH_800ns = 5,     /*!< 800 ns */
-    RTC_WDT_LENGTH_1_6us = 6,     /*!< 1.6 us */
-    RTC_WDT_LENGTH_3_2us = 7      /*!< 3.2 us */
-} rtc_wdt_length_sig_t;
-
-/**
- * @brief Get status of protect of rtc_wdt.
- *
- * @return
- *         - True if the protect of RTC_WDT is set
- */
-bool rtc_wdt_get_protect_status();
-
-/**
- * @brief Set protect of rtc_wdt.
- */
-void rtc_wdt_protect_on();
-
-/**
- * @brief Reset protect of rtc_wdt.
- */
-void rtc_wdt_protect_off();
-
-/**
- * @brief Enable rtc_wdt.
- */
-void rtc_wdt_enable();
-
-/**
- * @brief Enable the flash boot protection procedure for WDT.
- *
- * Do not recommend to use it in the app.
- * This function was added to be compatibility with the old bootloaders.
- * This mode is disabled in bootloader or using rtc_wdt_disable() function.
- */
-void rtc_wdt_flashboot_mode_enable();
-
-/**
- * @brief Disable rtc_wdt.
- */
-void rtc_wdt_disable();
-
-/**
- * @brief Reset counter rtc_wdt.
- *
- * It returns to stage 0 and its expiry counter restarts from 0.
- */
-void rtc_wdt_feed();
-
-/**
- * @brief Set time for required stage.
- *
- * @param[in] stage Stage of rtc_wdt.
- * @param[in] timeout_ms Timeout for this stage.
- *
- * @return
- *         - ESP_OK In case of success
- *         - ESP_ERR_INVALID_ARG If stage has invalid value
- */
-esp_err_t rtc_wdt_set_time(rtc_wdt_stage_t stage, unsigned int timeout_ms);
-
-/**
- * @brief Get the timeout set for the required stage.
- *
- * @param[in]  stage Stage of rtc_wdt.
- * @param[out] timeout_ms Timeout set for this stage. (not elapsed time).
- *
- * @return
- *         - ESP_OK In case of success
- *         - ESP_ERR_INVALID_ARG If stage has invalid value
- */
-esp_err_t rtc_wdt_get_timeout(rtc_wdt_stage_t stage, unsigned int* timeout_ms);
-
-/**
- * @brief Set an action for required stage.
- *
- * @param[in] stage Stage of rtc_wdt.
- * @param[in] stage_sel Action for this stage. When the time of stage expires this action will be triggered.
- *
- * @return
- *         - ESP_OK In case of success
- *         - ESP_ERR_INVALID_ARG If stage or stage_sel have invalid value
- */
-esp_err_t rtc_wdt_set_stage(rtc_wdt_stage_t stage, rtc_wdt_stage_action_t stage_sel);
-
-/**
- * @brief Set a length of reset signal.
- *
- * @param[in] reset_src Type of reset signal.
- * @param[in] reset_signal_length A length of reset signal.
- *
- * @return
- *         - ESP_OK In case of success
- *         - ESP_ERR_INVALID_ARG If reset_src  or reset_signal_length have invalid value
- */
-esp_err_t rtc_wdt_set_length_of_reset_signal(rtc_wdt_reset_sig_t reset_src, rtc_wdt_length_sig_t reset_signal_length);
-
-/**
- * @brief Return true if rtc_wdt is enabled.
- *
- * @return
- *         - True rtc_wdt is enabled
- */
-bool rtc_wdt_is_on();
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // _SOC_RTC_WDT_H
diff --git a/tools/sdk/include/soc/soc/sdio_slave_periph.h b/tools/sdk/include/soc/soc/sdio_slave_periph.h
deleted file mode 100644
index 467104dcf4a..00000000000
--- a/tools/sdk/include/soc/soc/sdio_slave_periph.h
+++ /dev/null
@@ -1,49 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_SDIO_SLAVE_PERIPH_H_
-#define _SOC_SDIO_SLAVE_PERIPH_H_
-
-#include <stdint.h>
-//include soc related (generated) definitions
-#include "soc/sdio_slave_pins.h"
-#include "soc/slc_reg.h"
-#include "soc/slc_struct.h"
-#include "soc/host_reg.h"
-#include "soc/host_struct.h"
-#include "soc/hinf_reg.h"
-#include "soc/hinf_struct.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** pin and signal information of each slot */
-typedef struct {
-    uint32_t clk_gpio;
-    uint32_t cmd_gpio;
-    uint32_t d0_gpio;
-    uint32_t d1_gpio;
-    uint32_t d2_gpio;
-    uint32_t d3_gpio;
-    int      func;
-} sdio_slave_slot_info_t;
-
-extern const sdio_slave_slot_info_t sdio_slave_slot_info[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SOC_SDIO_SLAVE_PERIPH_H_ */
\ No newline at end of file
diff --git a/tools/sdk/include/soc/soc/sdio_slave_pins.h b/tools/sdk/include/soc/soc/sdio_slave_pins.h
deleted file mode 100644
index 97c8bec07fd..00000000000
--- a/tools/sdk/include/soc/soc/sdio_slave_pins.h
+++ /dev/null
@@ -1,34 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_SDIO_SLAVE_PINS_H_
-#define _SOC_SDIO_SLAVE_PINS_H_
-
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK  6
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD  11
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0   7
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1   8
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2   9
-#define SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3   10
-#define SDIO_SLAVE_SLOT0_FUNC               0
-
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK  14
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD  15
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0   2
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1   4
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2   12
-#define SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3   13
-#define SDIO_SLAVE_SLOT1_FUNC               4
-
-#endif /* _SOC_SDIO_SLAVE_PINS_H_ */
\ No newline at end of file
diff --git a/tools/sdk/include/soc/soc/sdmmc_periph.h b/tools/sdk/include/soc/soc/sdmmc_periph.h
deleted file mode 100644
index 79dfaf34abd..00000000000
--- a/tools/sdk/include/soc/soc/sdmmc_periph.h
+++ /dev/null
@@ -1,53 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_SDMMC_PERIPH_H_
-#define _SOC_SDMMC_PERIPH_H_
-
-#include <stdint.h>
-//include soc related (generated) definitions
-#include "soc/sdmmc_pins.h"
-#include "soc/sdmmc_reg.h"
-#include "soc/sdmmc_struct.h"
-#include "soc/gpio_sig_map.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    uint8_t clk_gpio;
-    uint8_t cmd_gpio;
-    uint8_t d0_gpio;
-    uint8_t d1_gpio;
-    uint8_t d2_gpio;
-    uint8_t d3_gpio;
-    uint8_t d4_gpio;
-    uint8_t d5_gpio;
-    uint8_t d6_gpio;
-    uint8_t d7_gpio;
-    uint8_t card_detect;
-    uint8_t write_protect;
-    uint8_t card_int;
-    uint8_t width;
-} sdmmc_slot_info_t;
-
-/** pin and signal information of each slot */
-extern const sdmmc_slot_info_t sdmmc_slot_info[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SOC_SDMMC_PERIPH_H_ */
\ No newline at end of file
diff --git a/tools/sdk/include/soc/soc/sdmmc_pins.h b/tools/sdk/include/soc/soc/sdmmc_pins.h
deleted file mode 100644
index c0b328239ad..00000000000
--- a/tools/sdk/include/soc/soc/sdmmc_pins.h
+++ /dev/null
@@ -1,38 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_SDMMC_PINS_H_
-#define _SOC_SDMMC_PINS_H_
-
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_CLK  6
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_CMD  11
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D0   7
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D1   8
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D2   9
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D3   10
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D4   16
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D5   17
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D6   5
-#define SDMMC_SLOT0_IOMUX_PIN_NUM_D7   18
-#define SDMMC_SLOT0_FUNC               0
-
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_CLK  14
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_CMD  15
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D0   2
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D1   4
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D2   12
-#define SDMMC_SLOT1_IOMUX_PIN_NUM_D3   13
-#define SDMMC_SLOT1_FUNC               4
-
-#endif /* _SOC_SDMMC_PINS_H_ */
\ No newline at end of file
diff --git a/tools/sdk/include/soc/soc/sdmmc_reg.h b/tools/sdk/include/soc/soc/sdmmc_reg.h
deleted file mode 100644
index 0e92f682244..00000000000
--- a/tools/sdk/include/soc/soc/sdmmc_reg.h
+++ /dev/null
@@ -1,97 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SDMMC_REG_H_
-#define _SOC_SDMMC_REG_H_
-#include "soc.h"
-
-#define SDMMC_CTRL_REG          (DR_REG_SDMMC_BASE + 0x00)
-#define SDMMC_PWREN_REG         (DR_REG_SDMMC_BASE + 0x04)
-#define SDMMC_CLKDIV_REG        (DR_REG_SDMMC_BASE + 0x08)
-#define SDMMC_CLKSRC_REG        (DR_REG_SDMMC_BASE + 0x0c)
-#define SDMMC_CLKENA_REG        (DR_REG_SDMMC_BASE + 0x10)
-#define SDMMC_TMOUT_REG         (DR_REG_SDMMC_BASE + 0x14)
-#define SDMMC_CTYPE_REG         (DR_REG_SDMMC_BASE + 0x18)
-#define SDMMC_BLKSIZ_REG        (DR_REG_SDMMC_BASE + 0x1c)
-#define SDMMC_BYTCNT_REG        (DR_REG_SDMMC_BASE + 0x20)
-#define SDMMC_INTMASK_REG       (DR_REG_SDMMC_BASE + 0x24)
-#define SDMMC_CMDARG_REG        (DR_REG_SDMMC_BASE + 0x28)
-#define SDMMC_CMD_REG           (DR_REG_SDMMC_BASE + 0x2c)
-#define SDMMC_RESP0_REG         (DR_REG_SDMMC_BASE + 0x30)
-#define SDMMC_RESP1_REG         (DR_REG_SDMMC_BASE + 0x34)
-#define SDMMC_RESP2_REG         (DR_REG_SDMMC_BASE + 0x38)
-#define SDMMC_RESP3_REG         (DR_REG_SDMMC_BASE + 0x3c)
-
-#define SDMMC_MINTSTS_REG       (DR_REG_SDMMC_BASE + 0x40)
-#define SDMMC_RINTSTS_REG       (DR_REG_SDMMC_BASE + 0x44)
-#define SDMMC_STATUS_REG        (DR_REG_SDMMC_BASE + 0x48)
-#define SDMMC_FIFOTH_REG        (DR_REG_SDMMC_BASE + 0x4c)
-#define SDMMC_CDETECT_REG       (DR_REG_SDMMC_BASE + 0x50)
-#define SDMMC_WRTPRT_REG        (DR_REG_SDMMC_BASE + 0x54)
-#define SDMMC_GPIO_REG          (DR_REG_SDMMC_BASE + 0x58)
-#define SDMMC_TCBCNT_REG        (DR_REG_SDMMC_BASE + 0x5c)
-#define SDMMC_TBBCNT_REG        (DR_REG_SDMMC_BASE + 0x60)
-#define SDMMC_DEBNCE_REG        (DR_REG_SDMMC_BASE + 0x64)
-#define SDMMC_USRID_REG         (DR_REG_SDMMC_BASE + 0x68)
-#define SDMMC_VERID_REG         (DR_REG_SDMMC_BASE + 0x6c)
-#define SDMMC_HCON_REG          (DR_REG_SDMMC_BASE + 0x70)
-#define SDMMC_UHS_REG_REG       (DR_REG_SDMMC_BASE + 0x74)
-#define SDMMC_RST_N_REG         (DR_REG_SDMMC_BASE + 0x78)
-#define SDMMC_BMOD_REG          (DR_REG_SDMMC_BASE + 0x80)
-#define SDMMC_PLDMND_REG        (DR_REG_SDMMC_BASE + 0x84)
-#define SDMMC_DBADDR_REG        (DR_REG_SDMMC_BASE + 0x88)
-#define SDMMC_DBADDRU_REG       (DR_REG_SDMMC_BASE + 0x8c)
-#define SDMMC_IDSTS_REG         (DR_REG_SDMMC_BASE + 0x8c)
-#define SDMMC_IDINTEN_REG       (DR_REG_SDMMC_BASE + 0x90)
-#define SDMMC_DSCADDR_REG       (DR_REG_SDMMC_BASE + 0x94)
-#define SDMMC_DSCADDRL_REG      (DR_REG_SDMMC_BASE + 0x98)
-#define SDMMC_DSCADDRU_REG      (DR_REG_SDMMC_BASE + 0x9c)
-#define SDMMC_BUFADDRL_REG      (DR_REG_SDMMC_BASE + 0xa0)
-#define SDMMC_BUFADDRU_REG      (DR_REG_SDMMC_BASE + 0xa4)
-#define SDMMC_CARDTHRCTL_REG    (DR_REG_SDMMC_BASE + 0x100)
-#define SDMMC_BACK_END_POWER_REG    (DR_REG_SDMMC_BASE + 0x104)
-#define SDMMC_UHS_REG_EXT_REG   (DR_REG_SDMMC_BASE + 0x108)
-#define SDMMC_EMMC_DDR_REG_REG  (DR_REG_SDMMC_BASE + 0x10c)
-#define SDMMC_ENABLE_SHIFT_REG  (DR_REG_SDMMC_BASE + 0x110)
-
-#define SDMMC_CLOCK_REG         (DR_REG_SDMMC_BASE + 0x800)
-
-#define SDMMC_INTMASK_IO_SLOT1  BIT(17)
-#define SDMMC_INTMASK_IO_SLOT0  BIT(16)
-#define SDMMC_INTMASK_EBE       BIT(15)
-#define SDMMC_INTMASK_ACD       BIT(14)
-#define SDMMC_INTMASK_SBE       BIT(13)
-#define SDMMC_INTMASK_BCI       BIT(13)
-#define SDMMC_INTMASK_HLE       BIT(12)
-#define SDMMC_INTMASK_FRUN      BIT(11)
-#define SDMMC_INTMASK_HTO       BIT(10)
-#define SDMMC_INTMASK_DTO       BIT(9)
-#define SDMMC_INTMASK_RTO       BIT(8)
-#define SDMMC_INTMASK_DCRC      BIT(7)
-#define SDMMC_INTMASK_RCRC      BIT(6)
-#define SDMMC_INTMASK_RXDR      BIT(5)
-#define SDMMC_INTMASK_TXDR      BIT(4)
-#define SDMMC_INTMASK_DATA_OVER BIT(3)
-#define SDMMC_INTMASK_CMD_DONE  BIT(2)
-#define SDMMC_INTMASK_RESP_ERR  BIT(1)
-#define SDMMC_INTMASK_CD        BIT(0)
-
-#define SDMMC_IDMAC_INTMASK_AI  BIT(9)
-#define SDMMC_IDMAC_INTMASK_NI  BIT(8)
-#define SDMMC_IDMAC_INTMASK_CES BIT(5)
-#define SDMMC_IDMAC_INTMASK_DU  BIT(4)
-#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
-#define SDMMC_IDMAC_INTMASK_RI  BIT(1)
-#define SDMMC_IDMAC_INTMASK_TI  BIT(0)
-
-#endif /* _SOC_SDMMC_REG_H_  */
diff --git a/tools/sdk/include/soc/soc/sdmmc_struct.h b/tools/sdk/include/soc/soc/sdmmc_struct.h
deleted file mode 100644
index 17b8b3f24f7..00000000000
--- a/tools/sdk/include/soc/soc/sdmmc_struct.h
+++ /dev/null
@@ -1,393 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SDMMC_STRUCT_H_
-#define _SOC_SDMMC_STRUCT_H_
-
-#include <stdint.h>
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    uint32_t reserved1: 1;
-    uint32_t disable_int_on_completion: 1;
-    uint32_t last_descriptor: 1;
-    uint32_t first_descriptor: 1;
-    uint32_t second_address_chained: 1;
-    uint32_t end_of_ring: 1;
-    uint32_t reserved2: 24;
-    uint32_t card_error_summary: 1;
-    uint32_t owned_by_idmac: 1;
-    uint32_t buffer1_size: 13;
-    uint32_t buffer2_size: 13;
-    uint32_t reserved3: 6;
-    void* buffer1_ptr;
-    union {
-        void* buffer2_ptr;
-        void* next_desc_ptr;
-    };
-} sdmmc_desc_t;
-
-#define SDMMC_DMA_MAX_BUF_LEN 4096
-
-_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
-
-
-typedef struct {
-    uint32_t cmd_index: 6;          ///< Command index
-    uint32_t response_expect: 1;    ///< set if response is expected
-    uint32_t response_long: 1;      ///< 0: short response expected, 1: long response expected
-    uint32_t check_response_crc: 1; ///< set if controller should check response CRC
-    uint32_t data_expected: 1;      ///< 0: no data expected, 1: data expected
-    uint32_t rw: 1;                 ///< 0: read from card, 1: write to card (don't care if no data expected)
-    uint32_t stream_mode: 1;        ///< 0: block transfer, 1: stream transfer (don't care if no data expected)
-    uint32_t send_auto_stop: 1;     ///< set to send stop at the end of the transfer
-    uint32_t wait_complete: 1;      ///< 0: send command at once, 1: wait for previous command to complete
-    uint32_t stop_abort_cmd: 1;     ///< set if this is a stop or abort command intended to stop current transfer
-    uint32_t send_init: 1;          ///< set to send init sequence (80 clocks of 1)
-    uint32_t card_num: 5;           ///< card number
-    uint32_t update_clk_reg: 1;     ///< 0: normal command, 1: don't send command, just update clock registers
-    uint32_t read_ceata: 1;         ///< set if performing read from CE-ATA device
-    uint32_t ccs_expected: 1;       ///< set if CCS is expected from CE-ATA device
-    uint32_t enable_boot: 1;        ///< set for mandatory boot mode
-    uint32_t expect_boot_ack: 1;    ///< when set along with enable_boot, controller expects boot ack pattern
-    uint32_t disable_boot: 1;       ///< set to terminate boot operation (don't set along with enable_boot)
-    uint32_t boot_mode: 1;          ///< 0: mandatory boot operation, 1: alternate boot operation
-    uint32_t volt_switch: 1;        ///< set to enable voltage switching (for CMD11 only)
-    uint32_t use_hold_reg: 1;       ///< clear to bypass HOLD register
-    uint32_t reserved: 1;
-    uint32_t start_command: 1;      ///< Start command; once command is sent to the card, bit is cleared.
-} sdmmc_hw_cmd_t;  ///< command format used in cmd register; this structure is defined to make it easier to build command values
-
-_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
-
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t controller_reset: 1;
-            uint32_t fifo_reset: 1;
-            uint32_t dma_reset: 1;
-            uint32_t reserved1: 1;
-            uint32_t int_enable: 1;
-            uint32_t dma_enable: 1;
-            uint32_t read_wait: 1;
-            uint32_t send_irq_response: 1;
-            uint32_t abort_read_data: 1;
-            uint32_t send_ccsd: 1;
-            uint32_t send_auto_stop_ccsd: 1;
-            uint32_t ceata_device_interrupt_status: 1;
-            uint32_t reserved2: 4;
-            uint32_t card_voltage_a: 4;
-            uint32_t card_voltage_b: 4;
-            uint32_t enable_od_pullup: 1;
-            uint32_t use_internal_dma: 1;
-            uint32_t reserved3: 6;
-        };
-        uint32_t val;
-    } ctrl;
-
-    uint32_t pwren;             ///< 1: enable power to card, 0: disable power to card
-
-    union {
-        struct {
-            uint32_t div0: 8;   ///< 0: bypass, 1-255: divide clock by (2*div0).
-            uint32_t div1: 8;   ///< 0: bypass, 1-255: divide clock by (2*div0).
-            uint32_t div2: 8;   ///< 0: bypass, 1-255: divide clock by (2*div0).
-            uint32_t div3: 8;   ///< 0: bypass, 1-255: divide clock by (2*div0).
-        };
-        uint32_t val;
-    } clkdiv;
-
-    union {
-        struct {
-            uint32_t card0: 2;            ///< 0-3: select clock divider for card 0 among div0-div3
-            uint32_t card1: 2;            ///< 0-3: select clock divider for card 1 among div0-div3
-            uint32_t reserved: 28;
-        };
-        uint32_t val;
-    } clksrc;
-
-    union {
-        struct {
-            uint32_t cclk_enable: 16;       ///< 1: enable clock to card, 0: disable clock
-            uint32_t cclk_low_power: 16;    ///< 1: enable clock gating when card is idle, 0: disable clock gating
-        };
-        uint32_t val;
-    } clkena;
-
-    union {
-        struct {
-            uint32_t response: 8;       ///< response timeout, in card output clock cycles
-            uint32_t data: 24;          ///< data read timeout, in card output clock cycles
-        };
-        uint32_t val;
-    } tmout;
-
-    union {
-        struct {
-            uint32_t card_width: 16;    ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode
-            uint32_t card_width_8: 16;  ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored)
-        };
-        uint32_t val;
-    } ctype;
-
-    uint32_t blksiz: 16;        ///< block size, default 0x200
-    uint32_t : 16;
-
-    uint32_t bytcnt;            ///< number of bytes to be transferred
-
-    union {
-        struct {
-            uint32_t cd: 1;             ///< Card detect interrupt enable
-            uint32_t re: 1;             ///< Response error interrupt enable
-            uint32_t cmd_done: 1;       ///< Command done interrupt enable
-            uint32_t dto: 1;            ///< Data transfer over interrupt enable
-            uint32_t txdr: 1;           ///< Transmit FIFO data request interrupt enable
-            uint32_t rxdr: 1;           ///< Receive FIFO data request interrupt enable
-            uint32_t rcrc: 1;           ///< Response CRC error interrupt enable
-            uint32_t dcrc: 1;           ///< Data CRC error interrupt enable
-            uint32_t rto: 1;            ///< Response timeout interrupt enable
-            uint32_t drto: 1;           ///< Data read timeout interrupt enable
-            uint32_t hto: 1;            ///< Data starvation-by-host timeout interrupt enable
-            uint32_t frun: 1;           ///< FIFO underrun/overrun error interrupt enable
-            uint32_t hle: 1;            ///< Hardware locked write error interrupt enable
-            uint32_t sbi_bci: 1;        ///< Start bit error / busy clear interrupt enable
-            uint32_t acd: 1;            ///< Auto command done interrupt enable
-            uint32_t ebe: 1;            ///< End bit error / write no CRC interrupt enable
-            uint32_t sdio: 16;          ///< SDIO interrupt enable
-        };
-        uint32_t val;
-    } intmask;
-
-    uint32_t cmdarg;        ///< Command argument to be passed to card
-
-    sdmmc_hw_cmd_t cmd;
-
-    uint32_t resp[4];           ///< Response from card
-
-    union {
-        struct {
-            uint32_t cd: 1;             ///< Card detect interrupt masked status
-            uint32_t re: 1;             ///< Response error interrupt masked status
-            uint32_t cmd_done: 1;       ///< Command done interrupt masked status
-            uint32_t dto: 1;            ///< Data transfer over interrupt masked status
-            uint32_t txdr: 1;           ///< Transmit FIFO data request interrupt masked status
-            uint32_t rxdr: 1;           ///< Receive FIFO data request interrupt masked status
-            uint32_t rcrc: 1;           ///< Response CRC error interrupt masked status
-            uint32_t dcrc: 1;           ///< Data CRC error interrupt masked status
-            uint32_t rto: 1;            ///< Response timeout interrupt masked status
-            uint32_t drto: 1;           ///< Data read timeout interrupt masked status
-            uint32_t hto: 1;            ///< Data starvation-by-host timeout interrupt masked status
-            uint32_t frun: 1;           ///< FIFO underrun/overrun error interrupt masked status
-            uint32_t hle: 1;            ///< Hardware locked write error interrupt masked status
-            uint32_t sbi_bci: 1;        ///< Start bit error / busy clear interrupt masked status
-            uint32_t acd: 1;            ///< Auto command done interrupt masked status
-            uint32_t ebe: 1;            ///< End bit error / write no CRC interrupt masked status
-            uint32_t sdio: 16;          ///< SDIO interrupt masked status
-        };
-        uint32_t val;
-    } mintsts;
-
-    union {
-        struct {
-            uint32_t cd: 1;             ///< Card detect raw interrupt status
-            uint32_t re: 1;             ///< Response error raw interrupt status
-            uint32_t cmd_done: 1;       ///< Command done raw interrupt status
-            uint32_t dto: 1;            ///< Data transfer over raw interrupt status
-            uint32_t txdr: 1;           ///< Transmit FIFO data request raw interrupt status
-            uint32_t rxdr: 1;           ///< Receive FIFO data request raw interrupt status
-            uint32_t rcrc: 1;           ///< Response CRC error raw interrupt status
-            uint32_t dcrc: 1;           ///< Data CRC error raw interrupt status
-            uint32_t rto: 1;            ///< Response timeout raw interrupt status
-            uint32_t drto: 1;           ///< Data read timeout raw interrupt status
-            uint32_t hto: 1;            ///< Data starvation-by-host timeout raw interrupt status
-            uint32_t frun: 1;           ///< FIFO underrun/overrun error raw interrupt status
-            uint32_t hle: 1;            ///< Hardware locked write error raw interrupt status
-            uint32_t sbi_bci: 1;        ///< Start bit error / busy clear raw interrupt status
-            uint32_t acd: 1;            ///< Auto command done raw interrupt status
-            uint32_t ebe: 1;            ///< End bit error / write no CRC raw interrupt status
-            uint32_t sdio: 16;          ///< SDIO raw interrupt status
-        };
-        uint32_t val;
-    } rintsts;                          ///< interrupts can be cleared by writing this register
-
-    union {
-        struct {
-            uint32_t fifo_rx_watermark: 1;  ///< FIFO reached receive watermark level
-            uint32_t fifo_tx_watermark: 1;  ///< FIFO reached transmit watermark level
-            uint32_t fifo_empty: 1;         ///< FIFO is empty
-            uint32_t fifo_full: 1;          ///< FIFO is full
-            uint32_t cmd_fsm_state: 4;      ///< command FSM state
-            uint32_t data3_status: 1;       ///< this bit reads 1 if card is present
-            uint32_t data_busy: 1;          ///< this bit reads 1 if card is busy
-            uint32_t data_fsm_busy: 1;      ///< this bit reads 1 if transmit/receive FSM is busy
-            uint32_t response_index: 6;     ///< index of the previous response
-            uint32_t fifo_count: 13;        ///< number of filled locations in the FIFO
-            uint32_t dma_ack: 1;            ///< DMA acknowledge signal
-            uint32_t dma_req: 1;            ///< DMA request signal
-        };
-        uint32_t val;
-    } status;
-
-    union {
-        struct {
-            uint32_t tx_watermark: 12;      ///< FIFO TX watermark level
-            uint32_t reserved1: 4;
-            uint32_t rx_watermark: 12;      ///< FIFO RX watermark level
-            uint32_t dw_dma_mts: 3;
-            uint32_t reserved2: 1;
-        };
-        uint32_t val;
-    } fifoth;
-
-    union {
-        struct {
-            uint32_t cards: 2;              ///< bit N reads 0 if card N is present
-            uint32_t reserved: 30;
-        };
-        uint32_t val;
-    } cdetect;
-
-    union {
-        struct {
-            uint32_t cards: 2;              ///< bit N reads 1 if card N is write protected
-            uint32_t reserved: 30;
-        };
-        uint32_t val;
-    } wrtprt;
-
-    uint32_t gpio;      ///< unused
-    uint32_t tcbcnt;    ///< transferred (to card) byte count
-    uint32_t tbbcnt;    ///< transferred from host to FIFO byte count
-
-    union {
-        struct {
-            uint32_t debounce_count: 24;    ///< number of host cycles used by debounce filter, typical time should be 5-25ms
-            uint32_t reserved: 8;
-        };
-    } debnce;
-
-    uint32_t usrid;     ///< user ID
-    uint32_t verid;     ///< IP block version
-    uint32_t hcon;      ///< compile-time IP configuration
-    union {
-        struct {
-            uint32_t voltage: 16;           ///< voltage control for slots; no-op on ESP32.
-            uint32_t ddr: 16;                ///< bit N enables DDR mode for card N
-        };
-    } uhs;              ///< UHS related settings
-
-    union {
-        struct {
-            uint32_t cards: 2;          ///< bit N resets card N, active low
-            uint32_t reserved: 30;
-        };
-    } rst_n;
-
-    uint32_t reserved_7c;
-
-    union {
-        struct {
-            uint32_t sw_reset: 1;       ///< set to reset DMA controller
-            uint32_t fb: 1;             ///< set if AHB master performs fixed burst transfers
-            uint32_t dsl: 5;            ///< descriptor skip length: number of words to skip between two unchained descriptors
-            uint32_t enable: 1;         ///< set to enable IDMAC
-            uint32_t pbl: 3;            ///< programmable burst length
-            uint32_t reserved: 21;
-        };
-        uint32_t val;
-    } bmod;
-
-    uint32_t pldmnd;                    ///< set any bit to resume IDMAC FSM from suspended state
-    sdmmc_desc_t* dbaddr;        ///< descriptor list base
-
-    union {
-        struct {
-            uint32_t ti: 1;         ///< transmit interrupt status
-            uint32_t ri: 1;         ///< receive interrupt status
-            uint32_t fbe: 1;        ///< fatal bus error
-            uint32_t reserved1: 1;
-            uint32_t du: 1;         ///< descriptor unavailable
-            uint32_t ces: 1;        ///< card error summary
-            uint32_t reserved2: 2;
-            uint32_t nis: 1;        ///< normal interrupt summary
-            uint32_t fbe_code: 3;   ///< code of fatal bus error
-            uint32_t fsm: 4;        ///< DMAC FSM state
-            uint32_t reserved3: 15;
-        };
-        uint32_t val;
-    } idsts;
-
-    union {
-        struct {
-            uint32_t ti: 1;         ///< transmit interrupt enable
-            uint32_t ri: 1;         ///< receive interrupt enable
-            uint32_t fbe: 1;        ///< fatal bus error interrupt enable
-            uint32_t reserved1: 1;
-            uint32_t du: 1;         ///< descriptor unavailable interrupt enable
-            uint32_t ces: 1;        ///< card error interrupt enable
-            uint32_t reserved2: 2;
-            uint32_t ni: 1;         ///< normal interrupt interrupt enable
-            uint32_t ai: 1;         ///< abnormal interrupt enable
-            uint32_t reserved3: 22;
-        };
-        uint32_t val;
-    } idinten;
-
-    uint32_t dscaddr;       ///< current host descriptor address
-    uint32_t dscaddrl;      ///< unused
-    uint32_t dscaddru;      ///< unused
-    uint32_t bufaddrl;      ///< unused
-    uint32_t bufaddru;      ///< unused
-    uint32_t reserved_a8[22];
-    union {
-        struct {
-            uint32_t read_thr_en : 1;       ///< initiate transfer only if FIFO has more space than the read threshold
-            uint32_t busy_clr_int_en : 1;   ///< enable generation of busy clear interrupts
-            uint32_t write_thr_en : 1;      ///< equivalent of read_thr_en for writes
-            uint32_t reserved1 : 13;
-            uint32_t card_threshold : 12;   ///< threshold value for reads/writes, in bytes
-        };
-        uint32_t val;
-    } cardthrctl;
-    uint32_t back_end_power;
-    uint32_t uhs_reg_ext;
-    uint32_t emmc_ddr_reg;
-    uint32_t enable_shift;
-    uint32_t reserved_114[443];
-    union {
-        struct {
-            uint32_t phase_dout: 3;         ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
-            uint32_t phase_din: 3;          ///< phase of data input clock
-            uint32_t phase_core: 3;         ///< phase of the clock to SDMMC peripheral
-            uint32_t div_factor_p: 4;       ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
-            uint32_t div_factor_h: 4;       ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
-            uint32_t div_factor_m: 4;       ///< should be equal to div_factor_p
-        };
-        uint32_t val;
-    } clock;
-} sdmmc_dev_t;
-extern sdmmc_dev_t SDMMC;
-
-_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //_SOC_SDMMC_STRUCT_H_
diff --git a/tools/sdk/include/soc/soc/sens_reg.h b/tools/sdk/include/soc/soc/sens_reg.h
deleted file mode 100644
index 34834376e89..00000000000
--- a/tools/sdk/include/soc/soc/sens_reg.h
+++ /dev/null
@@ -1,1068 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SENS_REG_H_
-#define _SOC_SENS_REG_H_
-
-
-#include "soc.h"
-#define SENS_SAR_READ_CTRL_REG          (DR_REG_SENS_BASE + 0x0000)
-/* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: Invert SAR ADC1 data*/
-#define SENS_SAR1_DATA_INV  (BIT(28))
-#define SENS_SAR1_DATA_INV_M  (BIT(28))
-#define SENS_SAR1_DATA_INV_V  0x1
-#define SENS_SAR1_DATA_INV_S  28
-/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL  0: SAR ADC1 controlled by RTC ADC1 CTRL*/
-#define SENS_SAR1_DIG_FORCE  (BIT(27))
-#define SENS_SAR1_DIG_FORCE_M  (BIT(27))
-#define SENS_SAR1_DIG_FORCE_V  0x1
-#define SENS_SAR1_DIG_FORCE_S  27
-/* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
-/*description: */
-#define SENS_SAR1_SAMPLE_NUM  0x000000FF
-#define SENS_SAR1_SAMPLE_NUM_M  ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S))
-#define SENS_SAR1_SAMPLE_NUM_V  0xFF
-#define SENS_SAR1_SAMPLE_NUM_S  19
-/* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: */
-#define SENS_SAR1_CLK_GATED  (BIT(18))
-#define SENS_SAR1_CLK_GATED_M  (BIT(18))
-#define SENS_SAR1_CLK_GATED_V  0x1
-#define SENS_SAR1_CLK_GATED_S  18
-/* SENS_SAR1_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */
-/*description: 00: for 9-bit width  01: for 10-bit width  10: for 11-bit width
-  11: for 12-bit width*/
-#define SENS_SAR1_SAMPLE_BIT  0x00000003
-#define SENS_SAR1_SAMPLE_BIT_M  ((SENS_SAR1_SAMPLE_BIT_V)<<(SENS_SAR1_SAMPLE_BIT_S))
-#define SENS_SAR1_SAMPLE_BIT_V  0x3
-#define SENS_SAR1_SAMPLE_BIT_S  16
-/* SENS_SAR1_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */
-/*description: sample cycles for SAR ADC1*/
-#define SENS_SAR1_SAMPLE_CYCLE  0x000000FF
-#define SENS_SAR1_SAMPLE_CYCLE_M  ((SENS_SAR1_SAMPLE_CYCLE_V)<<(SENS_SAR1_SAMPLE_CYCLE_S))
-#define SENS_SAR1_SAMPLE_CYCLE_V  0xFF
-#define SENS_SAR1_SAMPLE_CYCLE_S  8
-/* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
-/*description: clock divider*/
-#define SENS_SAR1_CLK_DIV  0x000000FF
-#define SENS_SAR1_CLK_DIV_M  ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S))
-#define SENS_SAR1_CLK_DIV_V  0xFF
-#define SENS_SAR1_CLK_DIV_S  0
-
-#define SENS_SAR_READ_STATUS1_REG          (DR_REG_SENS_BASE + 0x0004)
-/* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SENS_SAR1_READER_STATUS  0xFFFFFFFF
-#define SENS_SAR1_READER_STATUS_M  ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S))
-#define SENS_SAR1_READER_STATUS_V  0xFFFFFFFF
-#define SENS_SAR1_READER_STATUS_S  0
-
-#define SENS_SAR_MEAS_WAIT1_REG          (DR_REG_SENS_BASE + 0x0008)
-/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */
-/*description: */
-#define SENS_SAR_AMP_WAIT2  0x0000FFFF
-#define SENS_SAR_AMP_WAIT2_M  ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S))
-#define SENS_SAR_AMP_WAIT2_V  0xFFFF
-#define SENS_SAR_AMP_WAIT2_S  16
-/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */
-/*description: */
-#define SENS_SAR_AMP_WAIT1  0x0000FFFF
-#define SENS_SAR_AMP_WAIT1_M  ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S))
-#define SENS_SAR_AMP_WAIT1_V  0xFFFF
-#define SENS_SAR_AMP_WAIT1_S  0
-
-#define SENS_SAR_MEAS_WAIT2_REG          (DR_REG_SENS_BASE + 0x000c)
-/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */
-/*description: */
-#define SENS_SAR2_RSTB_WAIT  0x000000FF
-#define SENS_SAR2_RSTB_WAIT_M  ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S))
-#define SENS_SAR2_RSTB_WAIT_V  0xFF
-#define SENS_SAR2_RSTB_WAIT_S  20
-/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: */
-#define SENS_FORCE_XPD_SAR  0x00000003
-#define SENS_FORCE_XPD_SAR_M  ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S))
-#define SENS_FORCE_XPD_SAR_V  0x3
-#define SENS_FORCE_XPD_SAR_S  18
-#define SENS_FORCE_XPD_SAR_SW_M (BIT1)
-#define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down
-#define SENS_FORCE_XPD_SAR_PD  2 // Force power down
-#define SENS_FORCE_XPD_SAR_PU  3 // Force power up
-/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: */
-#define SENS_FORCE_XPD_AMP  0x00000003
-#define SENS_FORCE_XPD_AMP_M  ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S))
-#define SENS_FORCE_XPD_AMP_V  0x3
-#define SENS_FORCE_XPD_AMP_S  16
-#define SENS_FORCE_XPD_AMP_FSM 0 // Use FSM to control power down
-#define SENS_FORCE_XPD_AMP_PD  2 // Force power down
-#define SENS_FORCE_XPD_AMP_PU  3 // Force power up
-/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */
-/*description: */
-#define SENS_SAR_AMP_WAIT3  0x0000FFFF
-#define SENS_SAR_AMP_WAIT3_M  ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S))
-#define SENS_SAR_AMP_WAIT3_V  0xFFFF
-#define SENS_SAR_AMP_WAIT3_S  0
-
-#define SENS_SAR_MEAS_CTRL_REG          (DR_REG_SENS_BASE + 0x0010)
-/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */
-/*description: */
-#define SENS_SAR2_XPD_WAIT  0x000000FF
-#define SENS_SAR2_XPD_WAIT_M  ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S))
-#define SENS_SAR2_XPD_WAIT_V  0xFF
-#define SENS_SAR2_XPD_WAIT_S  24
-/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[23:20] ;default: 4'b0000 ; */
-/*description: */
-#define SENS_SAR_RSTB_FSM  0x0000000F
-#define SENS_SAR_RSTB_FSM_M  ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S))
-#define SENS_SAR_RSTB_FSM_V  0xF
-#define SENS_SAR_RSTB_FSM_S  20
-/* SENS_XPD_SAR_FSM : R/W ;bitpos:[19:16] ;default: 4'b0111 ; */
-/*description: */
-#define SENS_XPD_SAR_FSM  0x0000000F
-#define SENS_XPD_SAR_FSM_M  ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S))
-#define SENS_XPD_SAR_FSM_V  0xF
-#define SENS_XPD_SAR_FSM_S  16
-/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */
-/*description: */
-#define SENS_AMP_SHORT_REF_GND_FSM  0x0000000F
-#define SENS_AMP_SHORT_REF_GND_FSM_M  ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S))
-#define SENS_AMP_SHORT_REF_GND_FSM_V  0xF
-#define SENS_AMP_SHORT_REF_GND_FSM_S  12
-/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[11:8] ;default: 4'b0011 ; */
-/*description: */
-#define SENS_AMP_SHORT_REF_FSM  0x0000000F
-#define SENS_AMP_SHORT_REF_FSM_M  ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S))
-#define SENS_AMP_SHORT_REF_FSM_V  0xF
-#define SENS_AMP_SHORT_REF_FSM_S  8
-/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[7:4] ;default: 4'b1000 ; */
-/*description: */
-#define SENS_AMP_RST_FB_FSM  0x0000000F
-#define SENS_AMP_RST_FB_FSM_M  ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S))
-#define SENS_AMP_RST_FB_FSM_V  0xF
-#define SENS_AMP_RST_FB_FSM_S  4
-/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[3:0] ;default: 4'b1111 ; */
-/*description: */
-#define SENS_XPD_SAR_AMP_FSM  0x0000000F
-#define SENS_XPD_SAR_AMP_FSM_M  ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S))
-#define SENS_XPD_SAR_AMP_FSM_V  0xF
-#define SENS_XPD_SAR_AMP_FSM_S  0
-
-#define SENS_SAR_READ_STATUS2_REG          (DR_REG_SENS_BASE + 0x0014)
-/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SENS_SAR2_READER_STATUS  0xFFFFFFFF
-#define SENS_SAR2_READER_STATUS_M  ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S))
-#define SENS_SAR2_READER_STATUS_V  0xFFFFFFFF
-#define SENS_SAR2_READER_STATUS_S  0
-
-#define SENS_ULP_CP_SLEEP_CYC0_REG          (DR_REG_SENS_BASE + 0x0018)
-/* SENS_SLEEP_CYCLES_S0 : R/W ;bitpos:[31:0] ;default: 32'd200 ; */
-/*description: sleep cycles for ULP-coprocessor timer*/
-#define SENS_SLEEP_CYCLES_S0  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S0_M  ((SENS_SLEEP_CYCLES_S0_V)<<(SENS_SLEEP_CYCLES_S0_S))
-#define SENS_SLEEP_CYCLES_S0_V  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S0_S  0
-
-#define SENS_ULP_CP_SLEEP_CYC1_REG          (DR_REG_SENS_BASE + 0x001c)
-/* SENS_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */
-/*description: */
-#define SENS_SLEEP_CYCLES_S1  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S1_M  ((SENS_SLEEP_CYCLES_S1_V)<<(SENS_SLEEP_CYCLES_S1_S))
-#define SENS_SLEEP_CYCLES_S1_V  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S1_S  0
-
-#define SENS_ULP_CP_SLEEP_CYC2_REG          (DR_REG_SENS_BASE + 0x0020)
-/* SENS_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */
-/*description: */
-#define SENS_SLEEP_CYCLES_S2  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S2_M  ((SENS_SLEEP_CYCLES_S2_V)<<(SENS_SLEEP_CYCLES_S2_S))
-#define SENS_SLEEP_CYCLES_S2_V  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S2_S  0
-
-#define SENS_ULP_CP_SLEEP_CYC3_REG          (DR_REG_SENS_BASE + 0x0024)
-/* SENS_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */
-/*description: */
-#define SENS_SLEEP_CYCLES_S3  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S3_M  ((SENS_SLEEP_CYCLES_S3_V)<<(SENS_SLEEP_CYCLES_S3_S))
-#define SENS_SLEEP_CYCLES_S3_V  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S3_S  0
-
-#define SENS_ULP_CP_SLEEP_CYC4_REG          (DR_REG_SENS_BASE + 0x0028)
-/* SENS_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */
-/*description: */
-#define SENS_SLEEP_CYCLES_S4  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S4_M  ((SENS_SLEEP_CYCLES_S4_V)<<(SENS_SLEEP_CYCLES_S4_S))
-#define SENS_SLEEP_CYCLES_S4_V  0xFFFFFFFF
-#define SENS_SLEEP_CYCLES_S4_S  0
-
-#define SENS_SAR_START_FORCE_REG          (DR_REG_SENS_BASE + 0x002c)
-/* SENS_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: N/A*/
-#define SENS_SAR2_PWDET_EN  (BIT(24))
-#define SENS_SAR2_PWDET_EN_M  (BIT(24))
-#define SENS_SAR2_PWDET_EN_V  0x1
-#define SENS_SAR2_PWDET_EN_S  24
-/* SENS_SAR1_STOP : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: stop SAR ADC1 conversion*/
-#define SENS_SAR1_STOP  (BIT(23))
-#define SENS_SAR1_STOP_M  (BIT(23))
-#define SENS_SAR1_STOP_V  0x1
-#define SENS_SAR1_STOP_S  23
-/* SENS_SAR2_STOP : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: stop SAR ADC2 conversion*/
-#define SENS_SAR2_STOP  (BIT(22))
-#define SENS_SAR2_STOP_M  (BIT(22))
-#define SENS_SAR2_STOP_V  0x1
-#define SENS_SAR2_STOP_S  22
-/* SENS_PC_INIT : R/W ;bitpos:[21:11] ;default: 11'b0 ; */
-/*description: initialized PC for ULP-coprocessor*/
-#define SENS_PC_INIT  0x000007FF
-#define SENS_PC_INIT_M  ((SENS_PC_INIT_V)<<(SENS_PC_INIT_S))
-#define SENS_PC_INIT_V  0x7FF
-#define SENS_PC_INIT_S  11
-/* SENS_SARCLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SENS_SARCLK_EN  (BIT(10))
-#define SENS_SARCLK_EN_M  (BIT(10))
-#define SENS_SARCLK_EN_V  0x1
-#define SENS_SARCLK_EN_S  10
-/* SENS_ULP_CP_START_TOP : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Write 1 to start ULP-coprocessor  only active when reg_ulp_cp_force_start_top
- = 1*/
-#define SENS_ULP_CP_START_TOP  (BIT(9))
-#define SENS_ULP_CP_START_TOP_M  (BIT(9))
-#define SENS_ULP_CP_START_TOP_V  0x1
-#define SENS_ULP_CP_START_TOP_S  9
-/* SENS_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: 1: ULP-coprocessor is started by SW  0: ULP-coprocessor is started by timer*/
-#define SENS_ULP_CP_FORCE_START_TOP  (BIT(8))
-#define SENS_ULP_CP_FORCE_START_TOP_M  (BIT(8))
-#define SENS_ULP_CP_FORCE_START_TOP_V  0x1
-#define SENS_ULP_CP_FORCE_START_TOP_S  8
-/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[7:5] ;default: 3'b0 ; */
-/*description: SAR2_PWDET_CCT  PA power detector capacitance tuning.*/
-#define SENS_SAR2_PWDET_CCT  0x00000007
-#define SENS_SAR2_PWDET_CCT_M  ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S))
-#define SENS_SAR2_PWDET_CCT_V  0x7
-#define SENS_SAR2_PWDET_CCT_S  5
-/* SENS_SAR2_EN_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: SAR2_EN_TEST  only active when reg_sar2_dig_force = 0*/
-#define SENS_SAR2_EN_TEST  (BIT(4))
-#define SENS_SAR2_EN_TEST_M  (BIT(4))
-#define SENS_SAR2_EN_TEST_V  0x1
-#define SENS_SAR2_EN_TEST_S  4
-/* SENS_SAR2_BIT_WIDTH : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: 00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/
-#define SENS_SAR2_BIT_WIDTH  0x00000003
-#define SENS_SAR2_BIT_WIDTH_M  ((SENS_SAR2_BIT_WIDTH_V)<<(SENS_SAR2_BIT_WIDTH_S))
-#define SENS_SAR2_BIT_WIDTH_V  0x3
-#define SENS_SAR2_BIT_WIDTH_S  2
-/* SENS_SAR1_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: 00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/
-#define SENS_SAR1_BIT_WIDTH  0x00000003
-#define SENS_SAR1_BIT_WIDTH_M  ((SENS_SAR1_BIT_WIDTH_V)<<(SENS_SAR1_BIT_WIDTH_S))
-#define SENS_SAR1_BIT_WIDTH_V  0x3
-#define SENS_SAR1_BIT_WIDTH_S  0
-
-#define SENS_SAR_MEM_WR_CTRL_REG          (DR_REG_SENS_BASE + 0x0030)
-/* SENS_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
-/*description: */
-#define SENS_RTC_MEM_WR_OFFST_CLR  (BIT(22))
-#define SENS_RTC_MEM_WR_OFFST_CLR_M  (BIT(22))
-#define SENS_RTC_MEM_WR_OFFST_CLR_V  0x1
-#define SENS_RTC_MEM_WR_OFFST_CLR_S  22
-/* SENS_MEM_WR_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */
-/*description: */
-#define SENS_MEM_WR_ADDR_SIZE  0x000007FF
-#define SENS_MEM_WR_ADDR_SIZE_M  ((SENS_MEM_WR_ADDR_SIZE_V)<<(SENS_MEM_WR_ADDR_SIZE_S))
-#define SENS_MEM_WR_ADDR_SIZE_V  0x7FF
-#define SENS_MEM_WR_ADDR_SIZE_S  11
-/* SENS_MEM_WR_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */
-/*description: */
-#define SENS_MEM_WR_ADDR_INIT  0x000007FF
-#define SENS_MEM_WR_ADDR_INIT_M  ((SENS_MEM_WR_ADDR_INIT_V)<<(SENS_MEM_WR_ADDR_INIT_S))
-#define SENS_MEM_WR_ADDR_INIT_V  0x7FF
-#define SENS_MEM_WR_ADDR_INIT_S  0
-
-#define SENS_SAR_ATTEN1_REG          (DR_REG_SENS_BASE + 0x0034)
-/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: 2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/
-#define SENS_SAR1_ATTEN  0xFFFFFFFF
-#define SENS_SAR1_ATTEN_M  ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S))
-#define SENS_SAR1_ATTEN_V  0xFFFFFFFF
-#define SENS_SAR1_ATTEN_S  0
-#define SENS_SAR1_ATTEN_VAL_MASK   0x3
-#define SENS_SAR2_ATTEN_VAL_MASK   0x3
-
-#define SENS_SAR_ATTEN2_REG          (DR_REG_SENS_BASE + 0x0038)
-/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: 2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/
-#define SENS_SAR2_ATTEN  0xFFFFFFFF
-#define SENS_SAR2_ATTEN_M  ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S))
-#define SENS_SAR2_ATTEN_V  0xFFFFFFFF
-#define SENS_SAR2_ATTEN_S  0
-
-#define SENS_SAR_SLAVE_ADDR1_REG          (DR_REG_SENS_BASE + 0x003c)
-/* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */
-/*description: */
-#define SENS_MEAS_STATUS  0x000000FF
-#define SENS_MEAS_STATUS_M  ((SENS_MEAS_STATUS_V)<<(SENS_MEAS_STATUS_S))
-#define SENS_MEAS_STATUS_V  0xFF
-#define SENS_MEAS_STATUS_S  22
-/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
-/*description: */
-#define SENS_I2C_SLAVE_ADDR0  0x000007FF
-#define SENS_I2C_SLAVE_ADDR0_M  ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S))
-#define SENS_I2C_SLAVE_ADDR0_V  0x7FF
-#define SENS_I2C_SLAVE_ADDR0_S  11
-/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
-/*description: */
-#define SENS_I2C_SLAVE_ADDR1  0x000007FF
-#define SENS_I2C_SLAVE_ADDR1_M  ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S))
-#define SENS_I2C_SLAVE_ADDR1_V  0x7FF
-#define SENS_I2C_SLAVE_ADDR1_S  0
-
-#define SENS_SAR_SLAVE_ADDR2_REG          (DR_REG_SENS_BASE + 0x0040)
-/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
-/*description: */
-#define SENS_I2C_SLAVE_ADDR2  0x000007FF
-#define SENS_I2C_SLAVE_ADDR2_M  ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S))
-#define SENS_I2C_SLAVE_ADDR2_V  0x7FF
-#define SENS_I2C_SLAVE_ADDR2_S  11
-/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
-/*description: */
-#define SENS_I2C_SLAVE_ADDR3  0x000007FF
-#define SENS_I2C_SLAVE_ADDR3_M  ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S))
-#define SENS_I2C_SLAVE_ADDR3_V  0x7FF
-#define SENS_I2C_SLAVE_ADDR3_S  0
-
-#define SENS_SAR_SLAVE_ADDR3_REG          (DR_REG_SENS_BASE + 0x0044)
-/* SENS_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */
-/*description: indicate temperature sensor out ready*/
-#define SENS_TSENS_RDY_OUT  (BIT(30))
-#define SENS_TSENS_RDY_OUT_M  (BIT(30))
-#define SENS_TSENS_RDY_OUT_V  0x1
-#define SENS_TSENS_RDY_OUT_S  30
-/* SENS_TSENS_OUT : RO ;bitpos:[29:22] ;default: 8'h0 ; */
-/*description: temperature sensor data out*/
-#define SENS_TSENS_OUT  0x000000FF
-#define SENS_TSENS_OUT_M  ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S))
-#define SENS_TSENS_OUT_V  0xFF
-#define SENS_TSENS_OUT_S  22
-/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
-/*description: */
-#define SENS_I2C_SLAVE_ADDR4  0x000007FF
-#define SENS_I2C_SLAVE_ADDR4_M  ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S))
-#define SENS_I2C_SLAVE_ADDR4_V  0x7FF
-#define SENS_I2C_SLAVE_ADDR4_S  11
-/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
-/*description: */
-#define SENS_I2C_SLAVE_ADDR5  0x000007FF
-#define SENS_I2C_SLAVE_ADDR5_M  ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S))
-#define SENS_I2C_SLAVE_ADDR5_V  0x7FF
-#define SENS_I2C_SLAVE_ADDR5_S  0
-
-#define SENS_SAR_SLAVE_ADDR4_REG          (DR_REG_SENS_BASE + 0x0048)
-/* SENS_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */
-/*description: indicate I2C done*/
-#define SENS_I2C_DONE  (BIT(30))
-#define SENS_I2C_DONE_M  (BIT(30))
-#define SENS_I2C_DONE_V  0x1
-#define SENS_I2C_DONE_S  30
-/* SENS_I2C_RDATA : RO ;bitpos:[29:22] ;default: 8'h0 ; */
-/*description: I2C read data*/
-#define SENS_I2C_RDATA  0x000000FF
-#define SENS_I2C_RDATA_M  ((SENS_I2C_RDATA_V)<<(SENS_I2C_RDATA_S))
-#define SENS_I2C_RDATA_V  0xFF
-#define SENS_I2C_RDATA_S  22
-/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
-/*description: */
-#define SENS_I2C_SLAVE_ADDR6  0x000007FF
-#define SENS_I2C_SLAVE_ADDR6_M  ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S))
-#define SENS_I2C_SLAVE_ADDR6_V  0x7FF
-#define SENS_I2C_SLAVE_ADDR6_S  11
-/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
-/*description: */
-#define SENS_I2C_SLAVE_ADDR7  0x000007FF
-#define SENS_I2C_SLAVE_ADDR7_M  ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S))
-#define SENS_I2C_SLAVE_ADDR7_V  0x7FF
-#define SENS_I2C_SLAVE_ADDR7_S  0
-
-#define SENS_SAR_TSENS_CTRL_REG          (DR_REG_SENS_BASE + 0x004c)
-/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: temperature sensor dump out  only active when reg_tsens_power_up_force = 1*/
-#define SENS_TSENS_DUMP_OUT  (BIT(26))
-#define SENS_TSENS_DUMP_OUT_M  (BIT(26))
-#define SENS_TSENS_DUMP_OUT_V  0x1
-#define SENS_TSENS_DUMP_OUT_S  26
-/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: 1: dump out & power up controlled by SW  0: by FSM*/
-#define SENS_TSENS_POWER_UP_FORCE  (BIT(25))
-#define SENS_TSENS_POWER_UP_FORCE_M  (BIT(25))
-#define SENS_TSENS_POWER_UP_FORCE_V  0x1
-#define SENS_TSENS_POWER_UP_FORCE_S  25
-/* SENS_TSENS_POWER_UP : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: temperature sensor power up*/
-#define SENS_TSENS_POWER_UP  (BIT(24))
-#define SENS_TSENS_POWER_UP_M  (BIT(24))
-#define SENS_TSENS_POWER_UP_V  0x1
-#define SENS_TSENS_POWER_UP_S  24
-/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[23:16] ;default: 8'd6 ; */
-/*description: temperature sensor clock divider*/
-#define SENS_TSENS_CLK_DIV  0x000000FF
-#define SENS_TSENS_CLK_DIV_M  ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S))
-#define SENS_TSENS_CLK_DIV_V  0xFF
-#define SENS_TSENS_CLK_DIV_S  16
-/* SENS_TSENS_IN_INV : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: invert temperature sensor data*/
-#define SENS_TSENS_IN_INV  (BIT(15))
-#define SENS_TSENS_IN_INV_M  (BIT(15))
-#define SENS_TSENS_IN_INV_V  0x1
-#define SENS_TSENS_IN_INV_S  15
-/* SENS_TSENS_CLK_GATED : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: */
-#define SENS_TSENS_CLK_GATED  (BIT(14))
-#define SENS_TSENS_CLK_GATED_M  (BIT(14))
-#define SENS_TSENS_CLK_GATED_V  0x1
-#define SENS_TSENS_CLK_GATED_S  14
-/* SENS_TSENS_CLK_INV : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define SENS_TSENS_CLK_INV  (BIT(13))
-#define SENS_TSENS_CLK_INV_M  (BIT(13))
-#define SENS_TSENS_CLK_INV_V  0x1
-#define SENS_TSENS_CLK_INV_S  13
-/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SENS_TSENS_XPD_FORCE  (BIT(12))
-#define SENS_TSENS_XPD_FORCE_M  (BIT(12))
-#define SENS_TSENS_XPD_FORCE_V  0x1
-#define SENS_TSENS_XPD_FORCE_S  12
-/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
-/*description: */
-#define SENS_TSENS_XPD_WAIT  0x00000FFF
-#define SENS_TSENS_XPD_WAIT_M  ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S))
-#define SENS_TSENS_XPD_WAIT_V  0xFFF
-#define SENS_TSENS_XPD_WAIT_S  0
-
-#define SENS_SAR_I2C_CTRL_REG          (DR_REG_SENS_BASE + 0x0050)
-/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: I2C started by SW  0: I2C started by FSM*/
-#define SENS_SAR_I2C_START_FORCE  (BIT(29))
-#define SENS_SAR_I2C_START_FORCE_M  (BIT(29))
-#define SENS_SAR_I2C_START_FORCE_V  0x1
-#define SENS_SAR_I2C_START_FORCE_S  29
-/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: start I2C  only active when reg_sar_i2c_start_force = 1*/
-#define SENS_SAR_I2C_START  (BIT(28))
-#define SENS_SAR_I2C_START_M  (BIT(28))
-#define SENS_SAR_I2C_START_V  0x1
-#define SENS_SAR_I2C_START_S  28
-/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
-/*description: I2C control data  only active when reg_sar_i2c_start_force = 1*/
-#define SENS_SAR_I2C_CTRL  0x0FFFFFFF
-#define SENS_SAR_I2C_CTRL_M  ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S))
-#define SENS_SAR_I2C_CTRL_V  0xFFFFFFF
-#define SENS_SAR_I2C_CTRL_S  0
-
-#define SENS_SAR_MEAS_START1_REG          (DR_REG_SENS_BASE + 0x0054)
-/* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW  0: SAR ADC1
- pad enable bitmap is controlled by ULP-coprocessor*/
-#define SENS_SAR1_EN_PAD_FORCE  (BIT(31))
-#define SENS_SAR1_EN_PAD_FORCE_M  (BIT(31))
-#define SENS_SAR1_EN_PAD_FORCE_V  0x1
-#define SENS_SAR1_EN_PAD_FORCE_S  31
-/* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */
-/*description: SAR ADC1 pad enable bitmap  only active when reg_sar1_en_pad_force = 1*/
-#define SENS_SAR1_EN_PAD  0x00000FFF
-#define SENS_SAR1_EN_PAD_M  ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S))
-#define SENS_SAR1_EN_PAD_V  0xFFF
-#define SENS_SAR1_EN_PAD_S  19
-/* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: 1: SAR ADC1 controller (in RTC) is started by SW  0: SAR ADC1
- controller is started by ULP-coprocessor*/
-#define SENS_MEAS1_START_FORCE  (BIT(18))
-#define SENS_MEAS1_START_FORCE_M  (BIT(18))
-#define SENS_MEAS1_START_FORCE_V  0x1
-#define SENS_MEAS1_START_FORCE_S  18
-/* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: SAR ADC1 controller (in RTC) starts conversion  only active when
- reg_meas1_start_force = 1*/
-#define SENS_MEAS1_START_SAR  (BIT(17))
-#define SENS_MEAS1_START_SAR_M  (BIT(17))
-#define SENS_MEAS1_START_SAR_V  0x1
-#define SENS_MEAS1_START_SAR_S  17
-/* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: SAR ADC1 conversion done indication*/
-#define SENS_MEAS1_DONE_SAR  (BIT(16))
-#define SENS_MEAS1_DONE_SAR_M  (BIT(16))
-#define SENS_MEAS1_DONE_SAR_V  0x1
-#define SENS_MEAS1_DONE_SAR_S  16
-/* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: SAR ADC1 data*/
-#define SENS_MEAS1_DATA_SAR  0x0000FFFF
-#define SENS_MEAS1_DATA_SAR_M  ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S))
-#define SENS_MEAS1_DATA_SAR_V  0xFFFF
-#define SENS_MEAS1_DATA_SAR_S  0
-
-#define SENS_SAR_TOUCH_CTRL1_REG          (DR_REG_SENS_BASE + 0x0058)
-/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: 1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled
- by FSM in ULP-coprocessor*/
-#define SENS_HALL_PHASE_FORCE  (BIT(27))
-#define SENS_HALL_PHASE_FORCE_M  (BIT(27))
-#define SENS_HALL_PHASE_FORCE_V  0x1
-#define SENS_HALL_PHASE_FORCE_S  27
-/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by
- FSM in ULP-coprocessor*/
-#define SENS_XPD_HALL_FORCE  (BIT(26))
-#define SENS_XPD_HALL_FORCE_M  (BIT(26))
-#define SENS_XPD_HALL_FORCE_V  0x1
-#define SENS_XPD_HALL_FORCE_S  26
-/* SENS_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: 1: wakeup interrupt is generated if SET1 is "touched"  0:
- wakeup interrupt is generated only if SET1 & SET2 is both "touched"*/
-#define SENS_TOUCH_OUT_1EN  (BIT(25))
-#define SENS_TOUCH_OUT_1EN_M  (BIT(25))
-#define SENS_TOUCH_OUT_1EN_V  0x1
-#define SENS_TOUCH_OUT_1EN_S  25
-/* SENS_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: when the counter is greater then the threshold  the touch
- pad is considered as "touched"  0: when the counter is less than the threshold  the touch pad is considered as "touched"*/
-#define SENS_TOUCH_OUT_SEL  (BIT(24))
-#define SENS_TOUCH_OUT_SEL_M  (BIT(24))
-#define SENS_TOUCH_OUT_SEL_V  0x1
-#define SENS_TOUCH_OUT_SEL_S  24
-/* SENS_TOUCH_XPD_WAIT : R/W ;bitpos:[23:16] ;default: 8'h4 ; */
-/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
-#define SENS_TOUCH_XPD_WAIT  0x000000FF
-#define SENS_TOUCH_XPD_WAIT_M  ((SENS_TOUCH_XPD_WAIT_V)<<(SENS_TOUCH_XPD_WAIT_S))
-#define SENS_TOUCH_XPD_WAIT_V  0xFF
-#define SENS_TOUCH_XPD_WAIT_S  16
-/* SENS_TOUCH_MEAS_DELAY : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: the meas length (in 8MHz)*/
-#define SENS_TOUCH_MEAS_DELAY  0x0000FFFF
-#define SENS_TOUCH_MEAS_DELAY_M  ((SENS_TOUCH_MEAS_DELAY_V)<<(SENS_TOUCH_MEAS_DELAY_S))
-#define SENS_TOUCH_MEAS_DELAY_V  0xFFFF
-#define SENS_TOUCH_MEAS_DELAY_S  0
-
-#define SENS_SAR_TOUCH_THRES1_REG          (DR_REG_SENS_BASE + 0x005c)
-/* SENS_TOUCH_OUT_TH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 0*/
-#define SENS_TOUCH_OUT_TH0  0x0000FFFF
-#define SENS_TOUCH_OUT_TH0_M  ((SENS_TOUCH_OUT_TH0_V)<<(SENS_TOUCH_OUT_TH0_S))
-#define SENS_TOUCH_OUT_TH0_V  0xFFFF
-#define SENS_TOUCH_OUT_TH0_S  16
-/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 1*/
-#define SENS_TOUCH_OUT_TH1  0x0000FFFF
-#define SENS_TOUCH_OUT_TH1_M  ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S))
-#define SENS_TOUCH_OUT_TH1_V  0xFFFF
-#define SENS_TOUCH_OUT_TH1_S  0
-
-#define SENS_SAR_TOUCH_THRES2_REG          (DR_REG_SENS_BASE + 0x0060)
-/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 2*/
-#define SENS_TOUCH_OUT_TH2  0x0000FFFF
-#define SENS_TOUCH_OUT_TH2_M  ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S))
-#define SENS_TOUCH_OUT_TH2_V  0xFFFF
-#define SENS_TOUCH_OUT_TH2_S  16
-/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 3*/
-#define SENS_TOUCH_OUT_TH3  0x0000FFFF
-#define SENS_TOUCH_OUT_TH3_M  ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S))
-#define SENS_TOUCH_OUT_TH3_V  0xFFFF
-#define SENS_TOUCH_OUT_TH3_S  0
-
-#define SENS_SAR_TOUCH_THRES3_REG          (DR_REG_SENS_BASE + 0x0064)
-/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 4*/
-#define SENS_TOUCH_OUT_TH4  0x0000FFFF
-#define SENS_TOUCH_OUT_TH4_M  ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S))
-#define SENS_TOUCH_OUT_TH4_V  0xFFFF
-#define SENS_TOUCH_OUT_TH4_S  16
-/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 5*/
-#define SENS_TOUCH_OUT_TH5  0x0000FFFF
-#define SENS_TOUCH_OUT_TH5_M  ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S))
-#define SENS_TOUCH_OUT_TH5_V  0xFFFF
-#define SENS_TOUCH_OUT_TH5_S  0
-
-#define SENS_SAR_TOUCH_THRES4_REG          (DR_REG_SENS_BASE + 0x0068)
-/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 6*/
-#define SENS_TOUCH_OUT_TH6  0x0000FFFF
-#define SENS_TOUCH_OUT_TH6_M  ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S))
-#define SENS_TOUCH_OUT_TH6_V  0xFFFF
-#define SENS_TOUCH_OUT_TH6_S  16
-/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 7*/
-#define SENS_TOUCH_OUT_TH7  0x0000FFFF
-#define SENS_TOUCH_OUT_TH7_M  ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S))
-#define SENS_TOUCH_OUT_TH7_V  0xFFFF
-#define SENS_TOUCH_OUT_TH7_S  0
-
-#define SENS_SAR_TOUCH_THRES5_REG          (DR_REG_SENS_BASE + 0x006c)
-/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 8*/
-#define SENS_TOUCH_OUT_TH8  0x0000FFFF
-#define SENS_TOUCH_OUT_TH8_M  ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S))
-#define SENS_TOUCH_OUT_TH8_V  0xFFFF
-#define SENS_TOUCH_OUT_TH8_S  16
-/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the threshold for touch pad 9*/
-#define SENS_TOUCH_OUT_TH9  0x0000FFFF
-#define SENS_TOUCH_OUT_TH9_M  ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S))
-#define SENS_TOUCH_OUT_TH9_V  0xFFFF
-#define SENS_TOUCH_OUT_TH9_S  0
-
-#define SENS_SAR_TOUCH_OUT1_REG          (DR_REG_SENS_BASE + 0x0070)
-/* SENS_TOUCH_MEAS_OUT0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the counter for touch pad 0*/
-#define SENS_TOUCH_MEAS_OUT0  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT0_M  ((SENS_TOUCH_MEAS_OUT0_V)<<(SENS_TOUCH_MEAS_OUT0_S))
-#define SENS_TOUCH_MEAS_OUT0_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT0_S  16
-/* SENS_TOUCH_MEAS_OUT1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the counter for touch pad 1*/
-#define SENS_TOUCH_MEAS_OUT1  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT1_M  ((SENS_TOUCH_MEAS_OUT1_V)<<(SENS_TOUCH_MEAS_OUT1_S))
-#define SENS_TOUCH_MEAS_OUT1_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT1_S  0
-
-#define SENS_SAR_TOUCH_OUT2_REG          (DR_REG_SENS_BASE + 0x0074)
-/* SENS_TOUCH_MEAS_OUT2 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the counter for touch pad 2*/
-#define SENS_TOUCH_MEAS_OUT2  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT2_M  ((SENS_TOUCH_MEAS_OUT2_V)<<(SENS_TOUCH_MEAS_OUT2_S))
-#define SENS_TOUCH_MEAS_OUT2_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT2_S  16
-/* SENS_TOUCH_MEAS_OUT3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the counter for touch pad 3*/
-#define SENS_TOUCH_MEAS_OUT3  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT3_M  ((SENS_TOUCH_MEAS_OUT3_V)<<(SENS_TOUCH_MEAS_OUT3_S))
-#define SENS_TOUCH_MEAS_OUT3_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT3_S  0
-
-#define SENS_SAR_TOUCH_OUT3_REG          (DR_REG_SENS_BASE + 0x0078)
-/* SENS_TOUCH_MEAS_OUT4 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the counter for touch pad 4*/
-#define SENS_TOUCH_MEAS_OUT4  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT4_M  ((SENS_TOUCH_MEAS_OUT4_V)<<(SENS_TOUCH_MEAS_OUT4_S))
-#define SENS_TOUCH_MEAS_OUT4_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT4_S  16
-/* SENS_TOUCH_MEAS_OUT5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the counter for touch pad 5*/
-#define SENS_TOUCH_MEAS_OUT5  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT5_M  ((SENS_TOUCH_MEAS_OUT5_V)<<(SENS_TOUCH_MEAS_OUT5_S))
-#define SENS_TOUCH_MEAS_OUT5_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT5_S  0
-
-#define SENS_SAR_TOUCH_OUT4_REG          (DR_REG_SENS_BASE + 0x007c)
-/* SENS_TOUCH_MEAS_OUT6 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the counter for touch pad 6*/
-#define SENS_TOUCH_MEAS_OUT6  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT6_M  ((SENS_TOUCH_MEAS_OUT6_V)<<(SENS_TOUCH_MEAS_OUT6_S))
-#define SENS_TOUCH_MEAS_OUT6_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT6_S  16
-/* SENS_TOUCH_MEAS_OUT7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the counter for touch pad 7*/
-#define SENS_TOUCH_MEAS_OUT7  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT7_M  ((SENS_TOUCH_MEAS_OUT7_V)<<(SENS_TOUCH_MEAS_OUT7_S))
-#define SENS_TOUCH_MEAS_OUT7_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT7_S  0
-
-#define SENS_SAR_TOUCH_OUT5_REG          (DR_REG_SENS_BASE + 0x0080)
-/* SENS_TOUCH_MEAS_OUT8 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: the counter for touch pad 8*/
-#define SENS_TOUCH_MEAS_OUT8  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT8_M  ((SENS_TOUCH_MEAS_OUT8_V)<<(SENS_TOUCH_MEAS_OUT8_S))
-#define SENS_TOUCH_MEAS_OUT8_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT8_S  16
-/* SENS_TOUCH_MEAS_OUT9 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: the counter for touch pad 9*/
-#define SENS_TOUCH_MEAS_OUT9  0x0000FFFF
-#define SENS_TOUCH_MEAS_OUT9_M  ((SENS_TOUCH_MEAS_OUT9_V)<<(SENS_TOUCH_MEAS_OUT9_S))
-#define SENS_TOUCH_MEAS_OUT9_V  0xFFFF
-#define SENS_TOUCH_MEAS_OUT9_S  0
-
-#define SENS_SAR_TOUCH_CTRL2_REG          (DR_REG_SENS_BASE + 0x0084)
-/* SENS_TOUCH_MEAS_EN_CLR : WO ;bitpos:[30] ;default: 1'h0 ; */
-/*description: to clear reg_touch_meas_en*/
-#define SENS_TOUCH_MEAS_EN_CLR  (BIT(30))
-#define SENS_TOUCH_MEAS_EN_CLR_M  (BIT(30))
-#define SENS_TOUCH_MEAS_EN_CLR_V  0x1
-#define SENS_TOUCH_MEAS_EN_CLR_S  30
-/* SENS_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[29:14] ;default: 16'h100 ; */
-/*description: sleep cycles for timer*/
-#define SENS_TOUCH_SLEEP_CYCLES  0x0000FFFF
-#define SENS_TOUCH_SLEEP_CYCLES_M  ((SENS_TOUCH_SLEEP_CYCLES_V)<<(SENS_TOUCH_SLEEP_CYCLES_S))
-#define SENS_TOUCH_SLEEP_CYCLES_V  0xFFFF
-#define SENS_TOUCH_SLEEP_CYCLES_S  14
-/* SENS_TOUCH_START_FORCE : R/W ;bitpos:[13] ;default: 1'h0 ; */
-/*description: 1: to start touch fsm by SW  0: to start touch fsm by timer*/
-#define SENS_TOUCH_START_FORCE  (BIT(13))
-#define SENS_TOUCH_START_FORCE_M  (BIT(13))
-#define SENS_TOUCH_START_FORCE_V  0x1
-#define SENS_TOUCH_START_FORCE_S  13
-/* SENS_TOUCH_START_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
-/*description: 1: start touch fsm  valid when reg_touch_start_force is set*/
-#define SENS_TOUCH_START_EN  (BIT(12))
-#define SENS_TOUCH_START_EN_M  (BIT(12))
-#define SENS_TOUCH_START_EN_V  0x1
-#define SENS_TOUCH_START_EN_S  12
-/* SENS_TOUCH_START_FSM_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
-/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm  0: TOUCH_START
- & TOUCH_XPD is controlled by registers*/
-#define SENS_TOUCH_START_FSM_EN  (BIT(11))
-#define SENS_TOUCH_START_FSM_EN_M  (BIT(11))
-#define SENS_TOUCH_START_FSM_EN_V  0x1
-#define SENS_TOUCH_START_FSM_EN_S  11
-/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[10] ;default: 1'h0 ; */
-/*description: fsm set 1 to indicate touch touch meas is done*/
-#define SENS_TOUCH_MEAS_DONE  (BIT(10))
-#define SENS_TOUCH_MEAS_DONE_M  (BIT(10))
-#define SENS_TOUCH_MEAS_DONE_V  0x1
-#define SENS_TOUCH_MEAS_DONE_S  10
-/* SENS_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: 10-bit register to indicate which pads are "touched"*/
-#define SENS_TOUCH_MEAS_EN  0x000003FF
-#define SENS_TOUCH_MEAS_EN_M  ((SENS_TOUCH_MEAS_EN_V)<<(SENS_TOUCH_MEAS_EN_S))
-#define SENS_TOUCH_MEAS_EN_V  0x3FF
-#define SENS_TOUCH_MEAS_EN_S  0
-
-#define SENS_SAR_TOUCH_ENABLE_REG          (DR_REG_SENS_BASE + 0x008c)
-/* SENS_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */
-/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is
- "touched" only if at least one of touch pad in SET1 is "touched".*/
-#define SENS_TOUCH_PAD_OUTEN1  0x000003FF
-#define SENS_TOUCH_PAD_OUTEN1_M  ((SENS_TOUCH_PAD_OUTEN1_V)<<(SENS_TOUCH_PAD_OUTEN1_S))
-#define SENS_TOUCH_PAD_OUTEN1_V  0x3FF
-#define SENS_TOUCH_PAD_OUTEN1_S  20
-/* SENS_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */
-/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is
- "touched" only if at least one of touch pad in SET2 is "touched".*/
-#define SENS_TOUCH_PAD_OUTEN2  0x000003FF
-#define SENS_TOUCH_PAD_OUTEN2_M  ((SENS_TOUCH_PAD_OUTEN2_V)<<(SENS_TOUCH_PAD_OUTEN2_S))
-#define SENS_TOUCH_PAD_OUTEN2_V  0x3FF
-#define SENS_TOUCH_PAD_OUTEN2_S  10
-/* SENS_TOUCH_PAD_WORKEN : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */
-/*description: Bitmap defining the working set during the measurement.*/
-#define SENS_TOUCH_PAD_WORKEN  0x000003FF
-#define SENS_TOUCH_PAD_WORKEN_M  ((SENS_TOUCH_PAD_WORKEN_V)<<(SENS_TOUCH_PAD_WORKEN_S))
-#define SENS_TOUCH_PAD_WORKEN_V  0x3FF
-#define SENS_TOUCH_PAD_WORKEN_S  0
-
-#define SENS_SAR_READ_CTRL2_REG          (DR_REG_SENS_BASE + 0x0090)
-/* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Invert SAR ADC2 data*/
-#define SENS_SAR2_DATA_INV  (BIT(29))
-#define SENS_SAR2_DATA_INV_M  (BIT(29))
-#define SENS_SAR2_DATA_INV_V  0x1
-#define SENS_SAR2_DATA_INV_S  29
-/* SENS_SAR2_DIG_FORCE : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL  0: SAR
- ADC2 controlled by RTC ADC2 CTRL*/
-#define SENS_SAR2_DIG_FORCE  (BIT(28))
-#define SENS_SAR2_DIG_FORCE_M  (BIT(28))
-#define SENS_SAR2_DIG_FORCE_V  0x1
-#define SENS_SAR2_DIG_FORCE_S  28
-/* SENS_SAR2_PWDET_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SENS_SAR2_PWDET_FORCE  (BIT(27))
-#define SENS_SAR2_PWDET_FORCE_M  (BIT(27))
-#define SENS_SAR2_PWDET_FORCE_V  0x1
-#define SENS_SAR2_PWDET_FORCE_S  27
-/* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
-/*description: */
-#define SENS_SAR2_SAMPLE_NUM  0x000000FF
-#define SENS_SAR2_SAMPLE_NUM_M  ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S))
-#define SENS_SAR2_SAMPLE_NUM_V  0xFF
-#define SENS_SAR2_SAMPLE_NUM_S  19
-/* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: */
-#define SENS_SAR2_CLK_GATED  (BIT(18))
-#define SENS_SAR2_CLK_GATED_M  (BIT(18))
-#define SENS_SAR2_CLK_GATED_V  0x1
-#define SENS_SAR2_CLK_GATED_S  18
-/* SENS_SAR2_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */
-/*description: 00: for 9-bit width  01: for 10-bit width  10: for 11-bit width
-  11: for 12-bit width*/
-#define SENS_SAR2_SAMPLE_BIT  0x00000003
-#define SENS_SAR2_SAMPLE_BIT_M  ((SENS_SAR2_SAMPLE_BIT_V)<<(SENS_SAR2_SAMPLE_BIT_S))
-#define SENS_SAR2_SAMPLE_BIT_V  0x3
-#define SENS_SAR2_SAMPLE_BIT_S  16
-/* SENS_SAR2_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */
-/*description: sample cycles for SAR ADC2*/
-#define SENS_SAR2_SAMPLE_CYCLE  0x000000FF
-#define SENS_SAR2_SAMPLE_CYCLE_M  ((SENS_SAR2_SAMPLE_CYCLE_V)<<(SENS_SAR2_SAMPLE_CYCLE_S))
-#define SENS_SAR2_SAMPLE_CYCLE_V  0xFF
-#define SENS_SAR2_SAMPLE_CYCLE_S  8
-/* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
-/*description: clock divider*/
-#define SENS_SAR2_CLK_DIV  0x000000FF
-#define SENS_SAR2_CLK_DIV_M  ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S))
-#define SENS_SAR2_CLK_DIV_V  0xFF
-#define SENS_SAR2_CLK_DIV_S  0
-
-#define SENS_SAR_MEAS_START2_REG          (DR_REG_SENS_BASE + 0x0094)
-/* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW  0: SAR ADC2
- pad enable bitmap is controlled by ULP-coprocessor*/
-#define SENS_SAR2_EN_PAD_FORCE  (BIT(31))
-#define SENS_SAR2_EN_PAD_FORCE_M  (BIT(31))
-#define SENS_SAR2_EN_PAD_FORCE_V  0x1
-#define SENS_SAR2_EN_PAD_FORCE_S  31
-/* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */
-/*description: SAR ADC2 pad enable bitmap  only active when reg_sar2_en_pad_force = 1*/
-#define SENS_SAR2_EN_PAD  0x00000FFF
-#define SENS_SAR2_EN_PAD_M  ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S))
-#define SENS_SAR2_EN_PAD_V  0xFFF
-#define SENS_SAR2_EN_PAD_S  19
-/* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: 1: SAR ADC2 controller (in RTC) is started by SW  0: SAR ADC2
- controller is started by ULP-coprocessor*/
-#define SENS_MEAS2_START_FORCE  (BIT(18))
-#define SENS_MEAS2_START_FORCE_M  (BIT(18))
-#define SENS_MEAS2_START_FORCE_V  0x1
-#define SENS_MEAS2_START_FORCE_S  18
-/* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: SAR ADC2 controller (in RTC) starts conversion  only active when
- reg_meas2_start_force = 1*/
-#define SENS_MEAS2_START_SAR  (BIT(17))
-#define SENS_MEAS2_START_SAR_M  (BIT(17))
-#define SENS_MEAS2_START_SAR_V  0x1
-#define SENS_MEAS2_START_SAR_S  17
-/* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: SAR ADC2 conversion done indication*/
-#define SENS_MEAS2_DONE_SAR  (BIT(16))
-#define SENS_MEAS2_DONE_SAR_M  (BIT(16))
-#define SENS_MEAS2_DONE_SAR_V  0x1
-#define SENS_MEAS2_DONE_SAR_S  16
-/* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: SAR ADC2 data*/
-#define SENS_MEAS2_DATA_SAR  0x0000FFFF
-#define SENS_MEAS2_DATA_SAR_M  ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S))
-#define SENS_MEAS2_DATA_SAR_V  0xFFFF
-#define SENS_MEAS2_DATA_SAR_S  0
-
-#define SENS_SAR_DAC_CTRL1_REG          (DR_REG_SENS_BASE + 0x0098)
-/* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: 1: invert PDAC_CLK*/
-#define SENS_DAC_CLK_INV  (BIT(25))
-#define SENS_DAC_CLK_INV_M  (BIT(25))
-#define SENS_DAC_CLK_INV_V  0x1
-#define SENS_DAC_CLK_INV_S  25
-/* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: force PDAC_CLK to high*/
-#define SENS_DAC_CLK_FORCE_HIGH  (BIT(24))
-#define SENS_DAC_CLK_FORCE_HIGH_M  (BIT(24))
-#define SENS_DAC_CLK_FORCE_HIGH_V  0x1
-#define SENS_DAC_CLK_FORCE_HIGH_S  24
-/* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: 1: force PDAC_CLK to low*/
-#define SENS_DAC_CLK_FORCE_LOW  (BIT(23))
-#define SENS_DAC_CLK_FORCE_LOW_M  (BIT(23))
-#define SENS_DAC_CLK_FORCE_LOW_V  0x1
-#define SENS_DAC_CLK_FORCE_LOW_S  23
-/* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: 1: DAC1 & DAC2 use DMA  0: DAC1 & DAC2 do not use DMA*/
-#define SENS_DAC_DIG_FORCE  (BIT(22))
-#define SENS_DAC_DIG_FORCE_M  (BIT(22))
-#define SENS_DAC_DIG_FORCE_V  0x1
-#define SENS_DAC_DIG_FORCE_S  22
-/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
-/*description: */
-#define SENS_DEBUG_BIT_SEL  0x0000001F
-#define SENS_DEBUG_BIT_SEL_M  ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S))
-#define SENS_DEBUG_BIT_SEL_V  0x1F
-#define SENS_DEBUG_BIT_SEL_S  17
-/* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: 1: enable CW generator  0: disable CW generator*/
-#define SENS_SW_TONE_EN  (BIT(16))
-#define SENS_SW_TONE_EN_M  (BIT(16))
-#define SENS_SW_TONE_EN_V  0x1
-#define SENS_SW_TONE_EN_S  16
-/* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: frequency step for CW generator  can be used to adjust the frequency*/
-#define SENS_SW_FSTEP  0x0000FFFF
-#define SENS_SW_FSTEP_M  ((SENS_SW_FSTEP_V)<<(SENS_SW_FSTEP_S))
-#define SENS_SW_FSTEP_V  0xFFFF
-#define SENS_SW_FSTEP_S  0
-
-#define SENS_SAR_DAC_CTRL2_REG          (DR_REG_SENS_BASE + 0x009c)
-/* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: 1: to select CW generator as source to PDAC2_DAC[7:0]  0: to
- select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/
-#define SENS_DAC_CW_EN2  (BIT(25))
-#define SENS_DAC_CW_EN2_M  (BIT(25))
-#define SENS_DAC_CW_EN2_V  0x1
-#define SENS_DAC_CW_EN2_S  25
-/* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: 1: to select CW generator as source to PDAC1_DAC[7:0]  0: to
- select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/
-#define SENS_DAC_CW_EN1  (BIT(24))
-#define SENS_DAC_CW_EN1_M  (BIT(24))
-#define SENS_DAC_CW_EN1_V  0x1
-#define SENS_DAC_CW_EN1_S  24
-/* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
-/*description: 00: do not invert any bits  01: invert all bits  10: invert MSB
-  11: invert all bits except MSB*/
-#define SENS_DAC_INV2  0x00000003
-#define SENS_DAC_INV2_M  ((SENS_DAC_INV2_V)<<(SENS_DAC_INV2_S))
-#define SENS_DAC_INV2_V  0x3
-#define SENS_DAC_INV2_S  22
-/* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */
-/*description: 00: do not invert any bits  01: invert all bits  10: invert MSB
-  11: invert all bits except MSB*/
-#define SENS_DAC_INV1  0x00000003
-#define SENS_DAC_INV1_M  ((SENS_DAC_INV1_V)<<(SENS_DAC_INV1_S))
-#define SENS_DAC_INV1_V  0x3
-#define SENS_DAC_INV1_S  20
-/* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */
-/*description: 00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/
-#define SENS_DAC_SCALE2  0x00000003
-#define SENS_DAC_SCALE2_M  ((SENS_DAC_SCALE2_V)<<(SENS_DAC_SCALE2_S))
-#define SENS_DAC_SCALE2_V  0x3
-#define SENS_DAC_SCALE2_S  18
-/* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
-/*description: 00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/
-#define SENS_DAC_SCALE1  0x00000003
-#define SENS_DAC_SCALE1_M  ((SENS_DAC_SCALE1_V)<<(SENS_DAC_SCALE1_S))
-#define SENS_DAC_SCALE1_V  0x3
-#define SENS_DAC_SCALE1_S  16
-/* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
-/*description: DC offset for DAC2 CW generator*/
-#define SENS_DAC_DC2  0x000000FF
-#define SENS_DAC_DC2_M  ((SENS_DAC_DC2_V)<<(SENS_DAC_DC2_S))
-#define SENS_DAC_DC2_V  0xFF
-#define SENS_DAC_DC2_S  8
-/* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: DC offset for DAC1 CW generator*/
-#define SENS_DAC_DC1  0x000000FF
-#define SENS_DAC_DC1_M  ((SENS_DAC_DC1_V)<<(SENS_DAC_DC1_S))
-#define SENS_DAC_DC1_V  0xFF
-#define SENS_DAC_DC1_S  0
-
-#define SENS_SAR_MEAS_CTRL2_REG          (DR_REG_SENS_BASE + 0x0a0)
-/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[18:17] ;default: 2'b0 ; */
-/*description: */
-#define SENS_AMP_SHORT_REF_GND_FORCE  0x00000003
-#define SENS_AMP_SHORT_REF_GND_FORCE_M  ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S))
-#define SENS_AMP_SHORT_REF_GND_FORCE_V  0x3
-#define SENS_AMP_SHORT_REF_GND_FORCE_S  17
-#define SENS_AMP_SHORT_REF_GND_FORCE_FSM 0 // Use FSM to control power down
-#define SENS_AMP_SHORT_REF_GND_FORCE_PD  2 // Force power down
-#define SENS_AMP_SHORT_REF_GND_FORCE_PU  3 // Force power up
-/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */
-/*description: */
-#define SENS_AMP_SHORT_REF_FORCE  0x00000003
-#define SENS_AMP_SHORT_REF_FORCE_M  ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S))
-#define SENS_AMP_SHORT_REF_FORCE_V  0x3
-#define SENS_AMP_SHORT_REF_FORCE_S  15
-#define SENS_AMP_SHORT_REF_FORCE_FSM 0 // Use FSM to control power down
-#define SENS_AMP_SHORT_REF_FORCE_PD  2 // Force power down
-#define SENS_AMP_SHORT_REF_FORCE_PU  3 // Force power up
-/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */
-/*description: */
-#define SENS_AMP_RST_FB_FORCE  0x00000003
-#define SENS_AMP_RST_FB_FORCE_M  ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S))
-#define SENS_AMP_RST_FB_FORCE_V  0x3
-#define SENS_AMP_RST_FB_FORCE_S  13
-#define SENS_AMP_RST_FB_FORCE_FSM 0 // Use FSM to control power down
-#define SENS_AMP_RST_FB_FORCE_PD  2 // Force power down
-#define SENS_AMP_RST_FB_FORCE_PU  3 // Force power up
-/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */
-/*description: */
-#define SENS_SAR2_RSTB_FORCE  0x00000003
-#define SENS_SAR2_RSTB_FORCE_M  ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S))
-#define SENS_SAR2_RSTB_FORCE_V  0x3
-#define SENS_SAR2_RSTB_FORCE_S  11
-#define SENS_SAR2_RSTB_FORCE_FSM 0 // Use FSM to control power down
-#define SENS_SAR2_RSTB_FORCE_PD  2 // Force power down
-#define SENS_SAR2_RSTB_FORCE_PU  3 // Force power up
-/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SENS_SAR_RSTB_FSM_IDLE  (BIT(10))
-#define SENS_SAR_RSTB_FSM_IDLE_M  (BIT(10))
-#define SENS_SAR_RSTB_FSM_IDLE_V  0x1
-#define SENS_SAR_RSTB_FSM_IDLE_S  10
-/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SENS_XPD_SAR_FSM_IDLE  (BIT(9))
-#define SENS_XPD_SAR_FSM_IDLE_M  (BIT(9))
-#define SENS_XPD_SAR_FSM_IDLE_V  0x1
-#define SENS_XPD_SAR_FSM_IDLE_S  9
-/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SENS_AMP_SHORT_REF_GND_FSM_IDLE  (BIT(8))
-#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M  (BIT(8))
-#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V  0x1
-#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S  8
-/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SENS_AMP_SHORT_REF_FSM_IDLE  (BIT(7))
-#define SENS_AMP_SHORT_REF_FSM_IDLE_M  (BIT(7))
-#define SENS_AMP_SHORT_REF_FSM_IDLE_V  0x1
-#define SENS_AMP_SHORT_REF_FSM_IDLE_S  7
-/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SENS_AMP_RST_FB_FSM_IDLE  (BIT(6))
-#define SENS_AMP_RST_FB_FSM_IDLE_M  (BIT(6))
-#define SENS_AMP_RST_FB_FSM_IDLE_V  0x1
-#define SENS_AMP_RST_FB_FSM_IDLE_S  6
-/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SENS_XPD_SAR_AMP_FSM_IDLE  (BIT(5))
-#define SENS_XPD_SAR_AMP_FSM_IDLE_M  (BIT(5))
-#define SENS_XPD_SAR_AMP_FSM_IDLE_V  0x1
-#define SENS_XPD_SAR_AMP_FSM_IDLE_S  5
-/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SENS_SAR1_DAC_XPD_FSM_IDLE  (BIT(4))
-#define SENS_SAR1_DAC_XPD_FSM_IDLE_M  (BIT(4))
-#define SENS_SAR1_DAC_XPD_FSM_IDLE_V  0x1
-#define SENS_SAR1_DAC_XPD_FSM_IDLE_S  4
-/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */
-/*description: */
-#define SENS_SAR1_DAC_XPD_FSM  0x0000000F
-#define SENS_SAR1_DAC_XPD_FSM_M  ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S))
-#define SENS_SAR1_DAC_XPD_FSM_V  0xF
-#define SENS_SAR1_DAC_XPD_FSM_S  0
-
-#define SENS_SAR_NOUSE_REG          (DR_REG_SENS_BASE + 0x00F8)
-/* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SENS_SAR_NOUSE  0xFFFFFFFF
-#define SENS_SAR_NOUSE_M  ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S))
-#define SENS_SAR_NOUSE_V  0xFFFFFFFF
-#define SENS_SAR_NOUSE_S  0
-
-#define SENS_SARDATE_REG          (DR_REG_SENS_BASE + 0x00FC)
-/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605180 ; */
-/*description: */
-#define SENS_SAR_DATE  0x0FFFFFFF
-#define SENS_SAR_DATE_M  ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S))
-#define SENS_SAR_DATE_V  0xFFFFFFF
-#define SENS_SAR_DATE_S  0
-
-
-
-
-#endif /*_SOC_SENS_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/sens_struct.h b/tools/sdk/include/soc/soc/sens_struct.h
deleted file mode 100644
index f572148cd1d..00000000000
--- a/tools/sdk/include/soc/soc/sens_struct.h
+++ /dev/null
@@ -1,328 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SENS_STRUCT_H_
-#define _SOC_SENS_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t sar1_clk_div:      8;
-            uint32_t sar1_sample_cycle: 8;
-            uint32_t sar1_sample_bit:   2;
-            uint32_t sar1_clk_gated:    1;
-            uint32_t sar1_sample_num:   8;
-            uint32_t sar1_dig_force:    1;                /*1: ADC1 is controlled by the digital controller  0: RTC controller*/
-            uint32_t sar1_data_inv:     1;
-            uint32_t reserved29:        3;
-        };
-        uint32_t val;
-    } sar_read_ctrl;
-    uint32_t sar_read_status1;                            /**/
-    union {
-        struct {
-            uint32_t sar_amp_wait1:16;
-            uint32_t sar_amp_wait2:16;
-        };
-        uint32_t val;
-    } sar_meas_wait1;
-    union {
-        struct {
-            uint32_t sar_amp_wait3: 16;
-            uint32_t force_xpd_amp:  2;
-            uint32_t force_xpd_sar:  2;
-            uint32_t sar2_rstb_wait: 8;
-            uint32_t reserved28:     4;
-        };
-        uint32_t val;
-    } sar_meas_wait2;
-    union {
-        struct {
-            uint32_t xpd_sar_amp_fsm:       4;
-            uint32_t amp_rst_fb_fsm:        4;
-            uint32_t amp_short_ref_fsm:     4;
-            uint32_t amp_short_ref_gnd_fsm: 4;
-            uint32_t xpd_sar_fsm:           4;
-            uint32_t sar_rstb_fsm:          4;
-            uint32_t sar2_xpd_wait:         8;
-        };
-        uint32_t val;
-    } sar_meas_ctrl;
-    uint32_t sar_read_status2;                            /**/
-    uint32_t ulp_cp_sleep_cyc0;                          /**/
-    uint32_t ulp_cp_sleep_cyc1;                          /**/
-    uint32_t ulp_cp_sleep_cyc2;                          /**/
-    uint32_t ulp_cp_sleep_cyc3;                          /**/
-    uint32_t ulp_cp_sleep_cyc4;                          /**/
-    union {
-        struct {
-            uint32_t sar1_bit_width:         2;
-            uint32_t sar2_bit_width:         2;
-            uint32_t sar2_en_test:           1;
-            uint32_t sar2_pwdet_cct:         3;
-            uint32_t ulp_cp_force_start_top: 1;
-            uint32_t ulp_cp_start_top:       1;
-            uint32_t sarclk_en:              1;
-            uint32_t pc_init:               11;
-            uint32_t sar2_stop:              1;
-            uint32_t sar1_stop:              1;
-            uint32_t sar2_pwdet_en:          1;
-            uint32_t reserved25:             7;
-        };
-        uint32_t val;
-    } sar_start_force;
-    union {
-        struct {
-            uint32_t mem_wr_addr_init:    11;
-            uint32_t mem_wr_addr_size:    11;
-            uint32_t rtc_mem_wr_offst_clr: 1;
-            uint32_t reserved23:           9;
-        };
-        uint32_t val;
-    } sar_mem_wr_ctrl;
-    uint32_t sar_atten1;                                  /**/
-    uint32_t sar_atten2;                                  /**/
-    union {
-        struct {
-            uint32_t i2c_slave_addr1:   11;
-            uint32_t i2c_slave_addr0:   11;
-            uint32_t meas_status:        8;
-            uint32_t reserved30:         2;
-        };
-        uint32_t val;
-    } sar_slave_addr1;
-    union {
-        struct {
-            uint32_t i2c_slave_addr3:11;
-            uint32_t i2c_slave_addr2:11;
-            uint32_t reserved22:     10;
-        };
-        uint32_t val;
-    } sar_slave_addr2;
-    union {
-        struct {
-            uint32_t i2c_slave_addr5:11;
-            uint32_t i2c_slave_addr4:11;
-            uint32_t tsens_out:       8;
-            uint32_t tsens_rdy_out:   1;
-            uint32_t reserved31:      1;
-        };
-        uint32_t val;
-    } sar_slave_addr3;
-    union {
-        struct {
-            uint32_t i2c_slave_addr7:11;
-            uint32_t i2c_slave_addr6:11;
-            uint32_t i2c_rdata:       8;
-            uint32_t i2c_done:        1;
-            uint32_t reserved31:      1;
-        };
-        uint32_t val;
-    } sar_slave_addr4;
-    union {
-        struct {
-            uint32_t tsens_xpd_wait:      12;
-            uint32_t tsens_xpd_force:      1;
-            uint32_t tsens_clk_inv:        1;
-            uint32_t tsens_clk_gated:      1;
-            uint32_t tsens_in_inv:         1;
-            uint32_t tsens_clk_div:        8;
-            uint32_t tsens_power_up:       1;
-            uint32_t tsens_power_up_force: 1;
-            uint32_t tsens_dump_out:       1;
-            uint32_t reserved27:           5;
-        };
-        uint32_t val;
-    } sar_tctrl;
-    union {
-        struct {
-            uint32_t sar_i2c_ctrl:       28;
-            uint32_t sar_i2c_start:       1;
-            uint32_t sar_i2c_start_force: 1;
-            uint32_t reserved30:          2;
-        };
-        uint32_t val;
-    } sar_i2c_ctrl;
-    union {
-        struct {
-            uint32_t meas1_data_sar:   16;
-            uint32_t meas1_done_sar:    1;
-            uint32_t meas1_start_sar:   1;
-            uint32_t meas1_start_force: 1;                /*1: ADC1 is controlled by the digital or RTC controller  0: Ulp coprocessor*/
-            uint32_t sar1_en_pad:      12;
-            uint32_t sar1_en_pad_force: 1;                /*1: Data ports are controlled by the digital or RTC controller  0: Ulp coprocessor*/
-        };
-        uint32_t val;
-    } sar_meas_start1;
-    union {
-        struct {
-            uint32_t touch_meas_delay:16;
-            uint32_t touch_xpd_wait:   8;
-            uint32_t touch_out_sel:    1;
-            uint32_t touch_out_1en:    1;
-            uint32_t xpd_hall_force:   1;                 /*1: Power of hall sensor is controlled by the digital or RTC controller  0: Ulp coprocessor*/
-            uint32_t hall_phase_force: 1;                 /*1: Phase of hall sensor is controlled by the digital or RTC controller  0: Ulp coprocessor*/
-            uint32_t reserved28:       4;
-        };
-        uint32_t val;
-    } sar_touch_ctrl1;
-    union {
-        struct {
-            uint32_t l_thresh: 16;
-            uint32_t h_thresh: 16;
-        };
-        uint32_t val;
-    } touch_thresh[5];
-    union {
-        struct {
-            uint32_t l_val: 16;
-            uint32_t h_val: 16;
-        };
-        uint32_t val;
-    } touch_meas[5];
-    union {
-        struct {
-            uint32_t touch_meas_en:     10;
-            uint32_t touch_meas_done:    1;
-            uint32_t touch_start_fsm_en: 1;
-            uint32_t touch_start_en:     1;
-            uint32_t touch_start_force:  1;
-            uint32_t touch_sleep_cycles:16;
-            uint32_t touch_meas_en_clr:  1;
-            uint32_t reserved31:         1;
-        };
-        uint32_t val;
-    } sar_touch_ctrl2;
-    uint32_t reserved_88;
-    union {
-        struct {
-            uint32_t touch_pad_worken:10;
-            uint32_t touch_pad_outen2:10;
-            uint32_t touch_pad_outen1:10;
-            uint32_t reserved30:       2;
-        };
-        uint32_t val;
-    } sar_touch_enable;
-    union {
-        struct {
-            uint32_t sar2_clk_div:      8;
-            uint32_t sar2_sample_cycle: 8;
-            uint32_t sar2_sample_bit:   2;
-            uint32_t sar2_clk_gated:    1;
-            uint32_t sar2_sample_num:   8;
-            uint32_t sar2_pwdet_force:  1;                /*1: ADC2 is controlled by PWDET  0: digital or RTC controller*/
-            uint32_t sar2_dig_force:    1;                /*1: ADC2 is controlled by the digital controller  0: RTC controller*/
-            uint32_t sar2_data_inv:     1;
-            uint32_t reserved30:        2;
-        };
-        uint32_t val;
-    } sar_read_ctrl2;
-    union {
-        struct {
-            uint32_t meas2_data_sar:   16;
-            uint32_t meas2_done_sar:    1;
-            uint32_t meas2_start_sar:   1;
-            uint32_t meas2_start_force: 1;                /*1: ADC2 is controlled by the digital or RTC controller  0: Ulp coprocessor*/
-            uint32_t sar2_en_pad:      12;
-            uint32_t sar2_en_pad_force: 1;                /*1: Data ports are controlled by the digital or RTC controller  0: Ulp coprocessor*/
-        };
-        uint32_t val;
-    } sar_meas_start2;
-    union {
-        struct {
-            uint32_t sw_fstep:          16;
-            uint32_t sw_tone_en:         1;
-            uint32_t debug_bit_sel:      5;
-            uint32_t dac_dig_force:      1;
-            uint32_t dac_clk_force_low:  1;
-            uint32_t dac_clk_force_high: 1;
-            uint32_t dac_clk_inv:        1;
-            uint32_t reserved26:         6;
-        };
-        uint32_t val;
-    } sar_dac_ctrl1;
-    union {
-        struct {
-            uint32_t dac_dc1:    8;
-            uint32_t dac_dc2:    8;
-            uint32_t dac_scale1: 2;
-            uint32_t dac_scale2: 2;
-            uint32_t dac_inv1:   2;
-            uint32_t dac_inv2:   2;
-            uint32_t dac_cw_en1: 1;
-            uint32_t dac_cw_en2: 1;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } sar_dac_ctrl2;
-    union {
-        struct {
-            uint32_t sar1_dac_xpd_fsm:           4;
-            uint32_t sar1_dac_xpd_fsm_idle:      1;
-            uint32_t xpd_sar_amp_fsm_idle:       1;
-            uint32_t amp_rst_fb_fsm_idle:        1;
-            uint32_t amp_short_ref_fsm_idle:     1;
-            uint32_t amp_short_ref_gnd_fsm_idle: 1;
-            uint32_t xpd_sar_fsm_idle:           1;
-            uint32_t sar_rstb_fsm_idle:          1;
-            uint32_t sar2_rstb_force:            2;
-            uint32_t amp_rst_fb_force:           2;
-            uint32_t amp_short_ref_force:        2;
-            uint32_t amp_short_ref_gnd_force:    2;
-            uint32_t reserved19:                13;
-        };
-        uint32_t val;
-    } sar_meas_ctrl2;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t sar_nouse;                                   /**/
-    union {
-        struct {
-            uint32_t sar_date:  28;
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    } sardate;
-} sens_dev_t;
-extern sens_dev_t SENS;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_SENS_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/slc_reg.h b/tools/sdk/include/soc/soc/slc_reg.h
deleted file mode 100644
index 3d4541cccbc..00000000000
--- a/tools/sdk/include/soc/soc/slc_reg.h
+++ /dev/null
@@ -1,3244 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SLC_REG_H_
-#define _SOC_SLC_REG_H_
-
-
-#include "soc.h"
-#define SLC_CONF0_REG          (DR_REG_SLC_BASE + 0x0)
-/* SLC_SLC1_TOKEN_SEL : R/W ;bitpos:[31] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC1_TOKEN_SEL  (BIT(31))
-#define SLC_SLC1_TOKEN_SEL_M  (BIT(31))
-#define SLC_SLC1_TOKEN_SEL_V  0x1
-#define SLC_SLC1_TOKEN_SEL_S  31
-/* SLC_SLC1_TOKEN_AUTO_CLR : R/W ;bitpos:[30] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC1_TOKEN_AUTO_CLR  (BIT(30))
-#define SLC_SLC1_TOKEN_AUTO_CLR_M  (BIT(30))
-#define SLC_SLC1_TOKEN_AUTO_CLR_V  0x1
-#define SLC_SLC1_TOKEN_AUTO_CLR_S  30
-/* SLC_SLC1_TXDATA_BURST_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_TXDATA_BURST_EN  (BIT(29))
-#define SLC_SLC1_TXDATA_BURST_EN_M  (BIT(29))
-#define SLC_SLC1_TXDATA_BURST_EN_V  0x1
-#define SLC_SLC1_TXDATA_BURST_EN_S  29
-/* SLC_SLC1_TXDSCR_BURST_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_TXDSCR_BURST_EN  (BIT(28))
-#define SLC_SLC1_TXDSCR_BURST_EN_M  (BIT(28))
-#define SLC_SLC1_TXDSCR_BURST_EN_V  0x1
-#define SLC_SLC1_TXDSCR_BURST_EN_S  28
-/* SLC_SLC1_TXLINK_AUTO_RET : R/W ;bitpos:[27] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_TXLINK_AUTO_RET  (BIT(27))
-#define SLC_SLC1_TXLINK_AUTO_RET_M  (BIT(27))
-#define SLC_SLC1_TXLINK_AUTO_RET_V  0x1
-#define SLC_SLC1_TXLINK_AUTO_RET_S  27
-/* SLC_SLC1_RXLINK_AUTO_RET : R/W ;bitpos:[26] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_RXLINK_AUTO_RET  (BIT(26))
-#define SLC_SLC1_RXLINK_AUTO_RET_M  (BIT(26))
-#define SLC_SLC1_RXLINK_AUTO_RET_V  0x1
-#define SLC_SLC1_RXLINK_AUTO_RET_S  26
-/* SLC_SLC1_RXDATA_BURST_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_RXDATA_BURST_EN  (BIT(25))
-#define SLC_SLC1_RXDATA_BURST_EN_M  (BIT(25))
-#define SLC_SLC1_RXDATA_BURST_EN_V  0x1
-#define SLC_SLC1_RXDATA_BURST_EN_S  25
-/* SLC_SLC1_RXDSCR_BURST_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_RXDSCR_BURST_EN  (BIT(24))
-#define SLC_SLC1_RXDSCR_BURST_EN_M  (BIT(24))
-#define SLC_SLC1_RXDSCR_BURST_EN_V  0x1
-#define SLC_SLC1_RXDSCR_BURST_EN_S  24
-/* SLC_SLC1_RX_NO_RESTART_CLR : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_NO_RESTART_CLR  (BIT(23))
-#define SLC_SLC1_RX_NO_RESTART_CLR_M  (BIT(23))
-#define SLC_SLC1_RX_NO_RESTART_CLR_V  0x1
-#define SLC_SLC1_RX_NO_RESTART_CLR_S  23
-/* SLC_SLC1_RX_AUTO_WRBACK : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_AUTO_WRBACK  (BIT(22))
-#define SLC_SLC1_RX_AUTO_WRBACK_M  (BIT(22))
-#define SLC_SLC1_RX_AUTO_WRBACK_V  0x1
-#define SLC_SLC1_RX_AUTO_WRBACK_S  22
-/* SLC_SLC1_RX_LOOP_TEST : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_RX_LOOP_TEST  (BIT(21))
-#define SLC_SLC1_RX_LOOP_TEST_M  (BIT(21))
-#define SLC_SLC1_RX_LOOP_TEST_V  0x1
-#define SLC_SLC1_RX_LOOP_TEST_S  21
-/* SLC_SLC1_TX_LOOP_TEST : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_TX_LOOP_TEST  (BIT(20))
-#define SLC_SLC1_TX_LOOP_TEST_M  (BIT(20))
-#define SLC_SLC1_TX_LOOP_TEST_V  0x1
-#define SLC_SLC1_TX_LOOP_TEST_S  20
-/* SLC_SLC1_WR_RETRY_MASK_EN : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_WR_RETRY_MASK_EN  (BIT(19))
-#define SLC_SLC1_WR_RETRY_MASK_EN_M  (BIT(19))
-#define SLC_SLC1_WR_RETRY_MASK_EN_V  0x1
-#define SLC_SLC1_WR_RETRY_MASK_EN_S  19
-/* SLC_SLC0_WR_RETRY_MASK_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_MASK_EN  (BIT(18))
-#define SLC_SLC0_WR_RETRY_MASK_EN_M  (BIT(18))
-#define SLC_SLC0_WR_RETRY_MASK_EN_V  0x1
-#define SLC_SLC0_WR_RETRY_MASK_EN_S  18
-/* SLC_SLC1_RX_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_RST  (BIT(17))
-#define SLC_SLC1_RX_RST_M  (BIT(17))
-#define SLC_SLC1_RX_RST_V  0x1
-#define SLC_SLC1_RX_RST_S  17
-/* SLC_SLC1_TX_RST : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC1_TX_RST  (BIT(16))
-#define SLC_SLC1_TX_RST_M  (BIT(16))
-#define SLC_SLC1_TX_RST_V  0x1
-#define SLC_SLC1_TX_RST_S  16
-/* SLC_SLC0_TOKEN_SEL : R/W ;bitpos:[15] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_TOKEN_SEL  (BIT(15))
-#define SLC_SLC0_TOKEN_SEL_M  (BIT(15))
-#define SLC_SLC0_TOKEN_SEL_V  0x1
-#define SLC_SLC0_TOKEN_SEL_S  15
-/* SLC_SLC0_TOKEN_AUTO_CLR : R/W ;bitpos:[14] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_TOKEN_AUTO_CLR  (BIT(14))
-#define SLC_SLC0_TOKEN_AUTO_CLR_M  (BIT(14))
-#define SLC_SLC0_TOKEN_AUTO_CLR_V  0x1
-#define SLC_SLC0_TOKEN_AUTO_CLR_S  14
-/* SLC_SLC0_TXDATA_BURST_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TXDATA_BURST_EN  (BIT(13))
-#define SLC_SLC0_TXDATA_BURST_EN_M  (BIT(13))
-#define SLC_SLC0_TXDATA_BURST_EN_V  0x1
-#define SLC_SLC0_TXDATA_BURST_EN_S  13
-/* SLC_SLC0_TXDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TXDSCR_BURST_EN  (BIT(12))
-#define SLC_SLC0_TXDSCR_BURST_EN_M  (BIT(12))
-#define SLC_SLC0_TXDSCR_BURST_EN_V  0x1
-#define SLC_SLC0_TXDSCR_BURST_EN_S  12
-/* SLC_SLC0_TXLINK_AUTO_RET : R/W ;bitpos:[11] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_AUTO_RET  (BIT(11))
-#define SLC_SLC0_TXLINK_AUTO_RET_M  (BIT(11))
-#define SLC_SLC0_TXLINK_AUTO_RET_V  0x1
-#define SLC_SLC0_TXLINK_AUTO_RET_S  11
-/* SLC_SLC0_RXLINK_AUTO_RET : R/W ;bitpos:[10] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_AUTO_RET  (BIT(10))
-#define SLC_SLC0_RXLINK_AUTO_RET_M  (BIT(10))
-#define SLC_SLC0_RXLINK_AUTO_RET_V  0x1
-#define SLC_SLC0_RXLINK_AUTO_RET_S  10
-/* SLC_SLC0_RXDATA_BURST_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RXDATA_BURST_EN  (BIT(9))
-#define SLC_SLC0_RXDATA_BURST_EN_M  (BIT(9))
-#define SLC_SLC0_RXDATA_BURST_EN_V  0x1
-#define SLC_SLC0_RXDATA_BURST_EN_S  9
-/* SLC_SLC0_RXDSCR_BURST_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RXDSCR_BURST_EN  (BIT(8))
-#define SLC_SLC0_RXDSCR_BURST_EN_M  (BIT(8))
-#define SLC_SLC0_RXDSCR_BURST_EN_V  0x1
-#define SLC_SLC0_RXDSCR_BURST_EN_S  8
-/* SLC_SLC0_RX_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_NO_RESTART_CLR  (BIT(7))
-#define SLC_SLC0_RX_NO_RESTART_CLR_M  (BIT(7))
-#define SLC_SLC0_RX_NO_RESTART_CLR_V  0x1
-#define SLC_SLC0_RX_NO_RESTART_CLR_S  7
-/* SLC_SLC0_RX_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_AUTO_WRBACK  (BIT(6))
-#define SLC_SLC0_RX_AUTO_WRBACK_M  (BIT(6))
-#define SLC_SLC0_RX_AUTO_WRBACK_V  0x1
-#define SLC_SLC0_RX_AUTO_WRBACK_S  6
-/* SLC_SLC0_RX_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_LOOP_TEST  (BIT(5))
-#define SLC_SLC0_RX_LOOP_TEST_M  (BIT(5))
-#define SLC_SLC0_RX_LOOP_TEST_V  0x1
-#define SLC_SLC0_RX_LOOP_TEST_S  5
-/* SLC_SLC0_TX_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TX_LOOP_TEST  (BIT(4))
-#define SLC_SLC0_TX_LOOP_TEST_M  (BIT(4))
-#define SLC_SLC0_TX_LOOP_TEST_V  0x1
-#define SLC_SLC0_TX_LOOP_TEST_S  4
-/* SLC_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_AHBM_RST  (BIT(3))
-#define SLC_AHBM_RST_M  (BIT(3))
-#define SLC_AHBM_RST_V  0x1
-#define SLC_AHBM_RST_S  3
-/* SLC_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_AHBM_FIFO_RST  (BIT(2))
-#define SLC_AHBM_FIFO_RST_M  (BIT(2))
-#define SLC_AHBM_FIFO_RST_V  0x1
-#define SLC_AHBM_FIFO_RST_S  2
-/* SLC_SLC0_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_RST  (BIT(1))
-#define SLC_SLC0_RX_RST_M  (BIT(1))
-#define SLC_SLC0_RX_RST_V  0x1
-#define SLC_SLC0_RX_RST_S  1
-/* SLC_SLC0_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_RST  (BIT(0))
-#define SLC_SLC0_TX_RST_M  (BIT(0))
-#define SLC_SLC0_TX_RST_V  0x1
-#define SLC_SLC0_TX_RST_S  0
-
-#define SLC_0INT_RAW_REG          (DR_REG_SLC_BASE + 0x4)
-/* SLC_SLC0_RX_QUICK_EOF_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S  26
-/* SLC_CMD_DTC_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_RAW  (BIT(25))
-#define SLC_CMD_DTC_INT_RAW_M  (BIT(25))
-#define SLC_CMD_DTC_INT_RAW_V  0x1
-#define SLC_CMD_DTC_INT_RAW_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_RAW_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_RAW_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S  19
-/* SLC_SLC0_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_RAW  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_RAW_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_RAW_V  0x1
-#define SLC_SLC0_TOHOST_INT_RAW_S  18
-/* SLC_SLC0_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_RAW  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_RAW_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_RAW_V  0x1
-#define SLC_SLC0_RX_EOF_INT_RAW_S  17
-/* SLC_SLC0_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_RAW  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_RAW_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_RAW_V  0x1
-#define SLC_SLC0_RX_DONE_INT_RAW_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_RAW_S  15
-/* SLC_SLC0_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_RAW  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_RAW_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_RAW_V  0x1
-#define SLC_SLC0_TX_DONE_INT_RAW_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S  12
-/* SLC_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_RAW  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_RAW_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_RAW_V  0x1
-#define SLC_SLC0_TX_OVF_INT_RAW_S  11
-/* SLC_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_RAW  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_RAW_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_RAW_V  0x1
-#define SLC_SLC0_RX_UDF_INT_RAW_S  10
-/* SLC_SLC0_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_RAW  (BIT(9))
-#define SLC_SLC0_TX_START_INT_RAW_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_RAW_V  0x1
-#define SLC_SLC0_TX_START_INT_RAW_S  9
-/* SLC_SLC0_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_RAW  (BIT(8))
-#define SLC_SLC0_RX_START_INT_RAW_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_RAW_V  0x1
-#define SLC_SLC0_RX_START_INT_RAW_S  8
-/* SLC_FRHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_RAW  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_RAW_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT7_INT_RAW_S  7
-/* SLC_FRHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_RAW  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_RAW_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT6_INT_RAW_S  6
-/* SLC_FRHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_RAW  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_RAW_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT5_INT_RAW_S  5
-/* SLC_FRHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_RAW  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_RAW_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT4_INT_RAW_S  4
-/* SLC_FRHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_RAW  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_RAW_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT3_INT_RAW_S  3
-/* SLC_FRHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_RAW  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_RAW_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT2_INT_RAW_S  2
-/* SLC_FRHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_RAW  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_RAW_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT1_INT_RAW_S  1
-/* SLC_FRHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_RAW  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_RAW_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT0_INT_RAW_S  0
-
-#define SLC_0INT_ST_REG          (DR_REG_SLC_BASE + 0x8)
-/* SLC_SLC0_RX_QUICK_EOF_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST_S  26
-/* SLC_CMD_DTC_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_ST  (BIT(25))
-#define SLC_CMD_DTC_INT_ST_M  (BIT(25))
-#define SLC_CMD_DTC_INT_ST_V  0x1
-#define SLC_CMD_DTC_INT_ST_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_ST  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ST_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_ST  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ST_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST_S  19
-/* SLC_SLC0_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_ST  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST_V  0x1
-#define SLC_SLC0_TOHOST_INT_ST_S  18
-/* SLC_SLC0_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_ST  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST_V  0x1
-#define SLC_SLC0_RX_EOF_INT_ST_S  17
-/* SLC_SLC0_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_ST  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST_V  0x1
-#define SLC_SLC0_RX_DONE_INT_ST_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_ST  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ST_S  15
-/* SLC_SLC0_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_ST  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST_V  0x1
-#define SLC_SLC0_TX_DONE_INT_ST_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST_S  12
-/* SLC_SLC0_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_ST  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST_V  0x1
-#define SLC_SLC0_TX_OVF_INT_ST_S  11
-/* SLC_SLC0_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_ST  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST_V  0x1
-#define SLC_SLC0_RX_UDF_INT_ST_S  10
-/* SLC_SLC0_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_ST  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST_V  0x1
-#define SLC_SLC0_TX_START_INT_ST_S  9
-/* SLC_SLC0_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_ST  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST_V  0x1
-#define SLC_SLC0_RX_START_INT_ST_S  8
-/* SLC_FRHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_ST  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST_V  0x1
-#define SLC_FRHOST_BIT7_INT_ST_S  7
-/* SLC_FRHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_ST  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST_V  0x1
-#define SLC_FRHOST_BIT6_INT_ST_S  6
-/* SLC_FRHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_ST  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST_V  0x1
-#define SLC_FRHOST_BIT5_INT_ST_S  5
-/* SLC_FRHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_ST  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST_V  0x1
-#define SLC_FRHOST_BIT4_INT_ST_S  4
-/* SLC_FRHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_ST  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST_V  0x1
-#define SLC_FRHOST_BIT3_INT_ST_S  3
-/* SLC_FRHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_ST  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST_V  0x1
-#define SLC_FRHOST_BIT2_INT_ST_S  2
-/* SLC_FRHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_ST  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST_V  0x1
-#define SLC_FRHOST_BIT1_INT_ST_S  1
-/* SLC_FRHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_ST  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST_V  0x1
-#define SLC_FRHOST_BIT0_INT_ST_S  0
-
-#define SLC_0INT_ENA_REG          (DR_REG_SLC_BASE + 0xC)
-/* SLC_SLC0_RX_QUICK_EOF_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S  26
-/* SLC_CMD_DTC_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_ENA  (BIT(25))
-#define SLC_CMD_DTC_INT_ENA_M  (BIT(25))
-#define SLC_CMD_DTC_INT_ENA_V  0x1
-#define SLC_CMD_DTC_INT_ENA_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S  19
-/* SLC_SLC0_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_ENA  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA_V  0x1
-#define SLC_SLC0_TOHOST_INT_ENA_S  18
-/* SLC_SLC0_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_ENA  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA_V  0x1
-#define SLC_SLC0_RX_EOF_INT_ENA_S  17
-/* SLC_SLC0_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_ENA  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA_V  0x1
-#define SLC_SLC0_RX_DONE_INT_ENA_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA_S  15
-/* SLC_SLC0_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_ENA  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA_V  0x1
-#define SLC_SLC0_TX_DONE_INT_ENA_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S  12
-/* SLC_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_ENA  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA_V  0x1
-#define SLC_SLC0_TX_OVF_INT_ENA_S  11
-/* SLC_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_ENA  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA_V  0x1
-#define SLC_SLC0_RX_UDF_INT_ENA_S  10
-/* SLC_SLC0_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_ENA  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA_V  0x1
-#define SLC_SLC0_TX_START_INT_ENA_S  9
-/* SLC_SLC0_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_ENA  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA_V  0x1
-#define SLC_SLC0_RX_START_INT_ENA_S  8
-/* SLC_FRHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_ENA  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT7_INT_ENA_S  7
-/* SLC_FRHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_ENA  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT6_INT_ENA_S  6
-/* SLC_FRHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_ENA  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT5_INT_ENA_S  5
-/* SLC_FRHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_ENA  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT4_INT_ENA_S  4
-/* SLC_FRHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_ENA  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT3_INT_ENA_S  3
-/* SLC_FRHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_ENA  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT2_INT_ENA_S  2
-/* SLC_FRHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_ENA  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT1_INT_ENA_S  1
-/* SLC_FRHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_ENA  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT0_INT_ENA_S  0
-
-#define SLC_0INT_CLR_REG          (DR_REG_SLC_BASE + 0x10)
-/* SLC_SLC0_RX_QUICK_EOF_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S  26
-/* SLC_CMD_DTC_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_CLR  (BIT(25))
-#define SLC_CMD_DTC_INT_CLR_M  (BIT(25))
-#define SLC_CMD_DTC_INT_CLR_V  0x1
-#define SLC_CMD_DTC_INT_CLR_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_CLR_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_CLR_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S  19
-/* SLC_SLC0_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_CLR  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_CLR_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_CLR_V  0x1
-#define SLC_SLC0_TOHOST_INT_CLR_S  18
-/* SLC_SLC0_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_CLR  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_CLR_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_CLR_V  0x1
-#define SLC_SLC0_RX_EOF_INT_CLR_S  17
-/* SLC_SLC0_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_CLR  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_CLR_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_CLR_V  0x1
-#define SLC_SLC0_RX_DONE_INT_CLR_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_CLR_S  15
-/* SLC_SLC0_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_CLR  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_CLR_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_CLR_V  0x1
-#define SLC_SLC0_TX_DONE_INT_CLR_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S  12
-/* SLC_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_CLR  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_CLR_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_CLR_V  0x1
-#define SLC_SLC0_TX_OVF_INT_CLR_S  11
-/* SLC_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_CLR  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_CLR_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_CLR_V  0x1
-#define SLC_SLC0_RX_UDF_INT_CLR_S  10
-/* SLC_SLC0_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_CLR  (BIT(9))
-#define SLC_SLC0_TX_START_INT_CLR_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_CLR_V  0x1
-#define SLC_SLC0_TX_START_INT_CLR_S  9
-/* SLC_SLC0_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_CLR  (BIT(8))
-#define SLC_SLC0_RX_START_INT_CLR_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_CLR_V  0x1
-#define SLC_SLC0_RX_START_INT_CLR_S  8
-/* SLC_FRHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_CLR  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_CLR_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT7_INT_CLR_S  7
-/* SLC_FRHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_CLR  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_CLR_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT6_INT_CLR_S  6
-/* SLC_FRHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_CLR  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_CLR_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT5_INT_CLR_S  5
-/* SLC_FRHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_CLR  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_CLR_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT4_INT_CLR_S  4
-/* SLC_FRHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_CLR  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_CLR_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT3_INT_CLR_S  3
-/* SLC_FRHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_CLR  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_CLR_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT2_INT_CLR_S  2
-/* SLC_FRHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_CLR  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_CLR_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT1_INT_CLR_S  1
-/* SLC_FRHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_CLR  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_CLR_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT0_INT_CLR_S  0
-
-#define SLC_1INT_RAW_REG          (DR_REG_SLC_BASE + 0x14)
-/* SLC_SLC1_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_ERR_EOF_INT_RAW  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_RAW_M  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_RAW_V  0x1
-#define SLC_SLC1_TX_ERR_EOF_INT_RAW_S  24
-/* SLC_SLC1_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_WR_RETRY_DONE_INT_RAW  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_RAW_M  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_RAW_V  0x1
-#define SLC_SLC1_WR_RETRY_DONE_INT_RAW_S  23
-/* SLC_SLC1_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_HOST_RD_ACK_INT_RAW  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_RAW_M  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_RAW_V  0x1
-#define SLC_SLC1_HOST_RD_ACK_INT_RAW_S  22
-/* SLC_SLC1_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_M  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_V  0x1
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_S  21
-/* SLC_SLC1_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DSCR_ERR_INT_RAW  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_RAW_M  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_RAW_V  0x1
-#define SLC_SLC1_RX_DSCR_ERR_INT_RAW_S  20
-/* SLC_SLC1_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_ERR_INT_RAW  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_RAW_M  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_RAW_V  0x1
-#define SLC_SLC1_TX_DSCR_ERR_INT_RAW_S  19
-/* SLC_SLC1_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOHOST_INT_RAW  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_RAW_M  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_RAW_V  0x1
-#define SLC_SLC1_TOHOST_INT_RAW_S  18
-/* SLC_SLC1_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_EOF_INT_RAW  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_RAW_M  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_RAW_V  0x1
-#define SLC_SLC1_RX_EOF_INT_RAW_S  17
-/* SLC_SLC1_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DONE_INT_RAW  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_RAW_M  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_RAW_V  0x1
-#define SLC_SLC1_RX_DONE_INT_RAW_S  16
-/* SLC_SLC1_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_SUC_EOF_INT_RAW  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_RAW_M  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_RAW_V  0x1
-#define SLC_SLC1_TX_SUC_EOF_INT_RAW_S  15
-/* SLC_SLC1_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DONE_INT_RAW  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_RAW_M  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_RAW_V  0x1
-#define SLC_SLC1_TX_DONE_INT_RAW_S  14
-/* SLC_SLC1_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_1TO0_INT_RAW  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_RAW_M  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_RAW_V  0x1
-#define SLC_SLC1_TOKEN1_1TO0_INT_RAW_S  13
-/* SLC_SLC1_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_1TO0_INT_RAW  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_RAW_M  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_RAW_V  0x1
-#define SLC_SLC1_TOKEN0_1TO0_INT_RAW_S  12
-/* SLC_SLC1_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_OVF_INT_RAW  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_RAW_M  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_RAW_V  0x1
-#define SLC_SLC1_TX_OVF_INT_RAW_S  11
-/* SLC_SLC1_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_UDF_INT_RAW  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_RAW_M  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_RAW_V  0x1
-#define SLC_SLC1_RX_UDF_INT_RAW_S  10
-/* SLC_SLC1_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_START_INT_RAW  (BIT(9))
-#define SLC_SLC1_TX_START_INT_RAW_M  (BIT(9))
-#define SLC_SLC1_TX_START_INT_RAW_V  0x1
-#define SLC_SLC1_TX_START_INT_RAW_S  9
-/* SLC_SLC1_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_START_INT_RAW  (BIT(8))
-#define SLC_SLC1_RX_START_INT_RAW_M  (BIT(8))
-#define SLC_SLC1_RX_START_INT_RAW_V  0x1
-#define SLC_SLC1_RX_START_INT_RAW_S  8
-/* SLC_FRHOST_BIT15_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT15_INT_RAW  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_RAW_M  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT15_INT_RAW_S  7
-/* SLC_FRHOST_BIT14_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT14_INT_RAW  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_RAW_M  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT14_INT_RAW_S  6
-/* SLC_FRHOST_BIT13_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT13_INT_RAW  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_RAW_M  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT13_INT_RAW_S  5
-/* SLC_FRHOST_BIT12_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT12_INT_RAW  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_RAW_M  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT12_INT_RAW_S  4
-/* SLC_FRHOST_BIT11_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT11_INT_RAW  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_RAW_M  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT11_INT_RAW_S  3
-/* SLC_FRHOST_BIT10_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT10_INT_RAW  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_RAW_M  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT10_INT_RAW_S  2
-/* SLC_FRHOST_BIT9_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT9_INT_RAW  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_RAW_M  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT9_INT_RAW_S  1
-/* SLC_FRHOST_BIT8_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT8_INT_RAW  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_RAW_M  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_RAW_V  0x1
-#define SLC_FRHOST_BIT8_INT_RAW_S  0
-
-#define SLC_1INT_ST_REG          (DR_REG_SLC_BASE + 0x18)
-/* SLC_SLC1_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_ERR_EOF_INT_ST  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_ST_M  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_ST_V  0x1
-#define SLC_SLC1_TX_ERR_EOF_INT_ST_S  24
-/* SLC_SLC1_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_WR_RETRY_DONE_INT_ST  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_ST_M  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_ST_V  0x1
-#define SLC_SLC1_WR_RETRY_DONE_INT_ST_S  23
-/* SLC_SLC1_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_HOST_RD_ACK_INT_ST  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_ST_M  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_ST_V  0x1
-#define SLC_SLC1_HOST_RD_ACK_INT_ST_S  22
-/* SLC_SLC1_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_M  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_V  0x1
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_S  21
-/* SLC_SLC1_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DSCR_ERR_INT_ST  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_ST_M  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_ST_V  0x1
-#define SLC_SLC1_RX_DSCR_ERR_INT_ST_S  20
-/* SLC_SLC1_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_ERR_INT_ST  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_ST_M  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_ST_V  0x1
-#define SLC_SLC1_TX_DSCR_ERR_INT_ST_S  19
-/* SLC_SLC1_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOHOST_INT_ST  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_ST_M  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_ST_V  0x1
-#define SLC_SLC1_TOHOST_INT_ST_S  18
-/* SLC_SLC1_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_EOF_INT_ST  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_ST_M  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_ST_V  0x1
-#define SLC_SLC1_RX_EOF_INT_ST_S  17
-/* SLC_SLC1_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DONE_INT_ST  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_ST_M  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_ST_V  0x1
-#define SLC_SLC1_RX_DONE_INT_ST_S  16
-/* SLC_SLC1_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_SUC_EOF_INT_ST  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_ST_M  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_ST_V  0x1
-#define SLC_SLC1_TX_SUC_EOF_INT_ST_S  15
-/* SLC_SLC1_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DONE_INT_ST  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_ST_M  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_ST_V  0x1
-#define SLC_SLC1_TX_DONE_INT_ST_S  14
-/* SLC_SLC1_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_1TO0_INT_ST  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_ST_M  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_ST_V  0x1
-#define SLC_SLC1_TOKEN1_1TO0_INT_ST_S  13
-/* SLC_SLC1_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_1TO0_INT_ST  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_ST_M  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_ST_V  0x1
-#define SLC_SLC1_TOKEN0_1TO0_INT_ST_S  12
-/* SLC_SLC1_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_OVF_INT_ST  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_ST_M  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_ST_V  0x1
-#define SLC_SLC1_TX_OVF_INT_ST_S  11
-/* SLC_SLC1_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_UDF_INT_ST  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_ST_M  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_ST_V  0x1
-#define SLC_SLC1_RX_UDF_INT_ST_S  10
-/* SLC_SLC1_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_START_INT_ST  (BIT(9))
-#define SLC_SLC1_TX_START_INT_ST_M  (BIT(9))
-#define SLC_SLC1_TX_START_INT_ST_V  0x1
-#define SLC_SLC1_TX_START_INT_ST_S  9
-/* SLC_SLC1_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_START_INT_ST  (BIT(8))
-#define SLC_SLC1_RX_START_INT_ST_M  (BIT(8))
-#define SLC_SLC1_RX_START_INT_ST_V  0x1
-#define SLC_SLC1_RX_START_INT_ST_S  8
-/* SLC_FRHOST_BIT15_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT15_INT_ST  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_ST_M  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_ST_V  0x1
-#define SLC_FRHOST_BIT15_INT_ST_S  7
-/* SLC_FRHOST_BIT14_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT14_INT_ST  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_ST_M  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_ST_V  0x1
-#define SLC_FRHOST_BIT14_INT_ST_S  6
-/* SLC_FRHOST_BIT13_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT13_INT_ST  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_ST_M  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_ST_V  0x1
-#define SLC_FRHOST_BIT13_INT_ST_S  5
-/* SLC_FRHOST_BIT12_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT12_INT_ST  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_ST_M  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_ST_V  0x1
-#define SLC_FRHOST_BIT12_INT_ST_S  4
-/* SLC_FRHOST_BIT11_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT11_INT_ST  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_ST_M  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_ST_V  0x1
-#define SLC_FRHOST_BIT11_INT_ST_S  3
-/* SLC_FRHOST_BIT10_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT10_INT_ST  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_ST_M  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_ST_V  0x1
-#define SLC_FRHOST_BIT10_INT_ST_S  2
-/* SLC_FRHOST_BIT9_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT9_INT_ST  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_ST_M  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_ST_V  0x1
-#define SLC_FRHOST_BIT9_INT_ST_S  1
-/* SLC_FRHOST_BIT8_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT8_INT_ST  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_ST_M  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_ST_V  0x1
-#define SLC_FRHOST_BIT8_INT_ST_S  0
-
-#define SLC_1INT_ENA_REG          (DR_REG_SLC_BASE + 0x1C)
-/* SLC_SLC1_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_ERR_EOF_INT_ENA  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_ENA_M  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_ENA_V  0x1
-#define SLC_SLC1_TX_ERR_EOF_INT_ENA_S  24
-/* SLC_SLC1_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_WR_RETRY_DONE_INT_ENA  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_ENA_M  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_ENA_V  0x1
-#define SLC_SLC1_WR_RETRY_DONE_INT_ENA_S  23
-/* SLC_SLC1_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_HOST_RD_ACK_INT_ENA  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_ENA_M  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_ENA_V  0x1
-#define SLC_SLC1_HOST_RD_ACK_INT_ENA_S  22
-/* SLC_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_M  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_V  0x1
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_S  21
-/* SLC_SLC1_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DSCR_ERR_INT_ENA  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_ENA_M  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_ENA_V  0x1
-#define SLC_SLC1_RX_DSCR_ERR_INT_ENA_S  20
-/* SLC_SLC1_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_ERR_INT_ENA  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_ENA_M  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_ENA_V  0x1
-#define SLC_SLC1_TX_DSCR_ERR_INT_ENA_S  19
-/* SLC_SLC1_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOHOST_INT_ENA  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_ENA_M  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_ENA_V  0x1
-#define SLC_SLC1_TOHOST_INT_ENA_S  18
-/* SLC_SLC1_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_EOF_INT_ENA  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_ENA_M  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_ENA_V  0x1
-#define SLC_SLC1_RX_EOF_INT_ENA_S  17
-/* SLC_SLC1_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DONE_INT_ENA  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_ENA_M  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_ENA_V  0x1
-#define SLC_SLC1_RX_DONE_INT_ENA_S  16
-/* SLC_SLC1_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_SUC_EOF_INT_ENA  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_ENA_M  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_ENA_V  0x1
-#define SLC_SLC1_TX_SUC_EOF_INT_ENA_S  15
-/* SLC_SLC1_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DONE_INT_ENA  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_ENA_M  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_ENA_V  0x1
-#define SLC_SLC1_TX_DONE_INT_ENA_S  14
-/* SLC_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_1TO0_INT_ENA  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_ENA_M  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_ENA_V  0x1
-#define SLC_SLC1_TOKEN1_1TO0_INT_ENA_S  13
-/* SLC_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_1TO0_INT_ENA  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_ENA_M  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_ENA_V  0x1
-#define SLC_SLC1_TOKEN0_1TO0_INT_ENA_S  12
-/* SLC_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_OVF_INT_ENA  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_ENA_M  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_ENA_V  0x1
-#define SLC_SLC1_TX_OVF_INT_ENA_S  11
-/* SLC_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_UDF_INT_ENA  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_ENA_M  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_ENA_V  0x1
-#define SLC_SLC1_RX_UDF_INT_ENA_S  10
-/* SLC_SLC1_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_START_INT_ENA  (BIT(9))
-#define SLC_SLC1_TX_START_INT_ENA_M  (BIT(9))
-#define SLC_SLC1_TX_START_INT_ENA_V  0x1
-#define SLC_SLC1_TX_START_INT_ENA_S  9
-/* SLC_SLC1_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_START_INT_ENA  (BIT(8))
-#define SLC_SLC1_RX_START_INT_ENA_M  (BIT(8))
-#define SLC_SLC1_RX_START_INT_ENA_V  0x1
-#define SLC_SLC1_RX_START_INT_ENA_S  8
-/* SLC_FRHOST_BIT15_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT15_INT_ENA  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_ENA_M  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT15_INT_ENA_S  7
-/* SLC_FRHOST_BIT14_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT14_INT_ENA  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_ENA_M  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT14_INT_ENA_S  6
-/* SLC_FRHOST_BIT13_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT13_INT_ENA  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_ENA_M  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT13_INT_ENA_S  5
-/* SLC_FRHOST_BIT12_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT12_INT_ENA  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_ENA_M  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT12_INT_ENA_S  4
-/* SLC_FRHOST_BIT11_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT11_INT_ENA  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_ENA_M  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT11_INT_ENA_S  3
-/* SLC_FRHOST_BIT10_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT10_INT_ENA  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_ENA_M  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT10_INT_ENA_S  2
-/* SLC_FRHOST_BIT9_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT9_INT_ENA  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_ENA_M  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT9_INT_ENA_S  1
-/* SLC_FRHOST_BIT8_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT8_INT_ENA  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_ENA_M  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_ENA_V  0x1
-#define SLC_FRHOST_BIT8_INT_ENA_S  0
-
-#define SLC_1INT_CLR_REG          (DR_REG_SLC_BASE + 0x20)
-/* SLC_SLC1_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_ERR_EOF_INT_CLR  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_CLR_M  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_CLR_V  0x1
-#define SLC_SLC1_TX_ERR_EOF_INT_CLR_S  24
-/* SLC_SLC1_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_WR_RETRY_DONE_INT_CLR  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_CLR_M  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_CLR_V  0x1
-#define SLC_SLC1_WR_RETRY_DONE_INT_CLR_S  23
-/* SLC_SLC1_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_HOST_RD_ACK_INT_CLR  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_CLR_M  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_CLR_V  0x1
-#define SLC_SLC1_HOST_RD_ACK_INT_CLR_S  22
-/* SLC_SLC1_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_M  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_V  0x1
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_S  21
-/* SLC_SLC1_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DSCR_ERR_INT_CLR  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_CLR_M  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_CLR_V  0x1
-#define SLC_SLC1_RX_DSCR_ERR_INT_CLR_S  20
-/* SLC_SLC1_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_ERR_INT_CLR  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_CLR_M  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_CLR_V  0x1
-#define SLC_SLC1_TX_DSCR_ERR_INT_CLR_S  19
-/* SLC_SLC1_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOHOST_INT_CLR  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_CLR_M  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_CLR_V  0x1
-#define SLC_SLC1_TOHOST_INT_CLR_S  18
-/* SLC_SLC1_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_EOF_INT_CLR  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_CLR_M  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_CLR_V  0x1
-#define SLC_SLC1_RX_EOF_INT_CLR_S  17
-/* SLC_SLC1_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DONE_INT_CLR  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_CLR_M  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_CLR_V  0x1
-#define SLC_SLC1_RX_DONE_INT_CLR_S  16
-/* SLC_SLC1_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_SUC_EOF_INT_CLR  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_CLR_M  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_CLR_V  0x1
-#define SLC_SLC1_TX_SUC_EOF_INT_CLR_S  15
-/* SLC_SLC1_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DONE_INT_CLR  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_CLR_M  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_CLR_V  0x1
-#define SLC_SLC1_TX_DONE_INT_CLR_S  14
-/* SLC_SLC1_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_1TO0_INT_CLR  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_CLR_M  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_CLR_V  0x1
-#define SLC_SLC1_TOKEN1_1TO0_INT_CLR_S  13
-/* SLC_SLC1_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_1TO0_INT_CLR  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_CLR_M  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_CLR_V  0x1
-#define SLC_SLC1_TOKEN0_1TO0_INT_CLR_S  12
-/* SLC_SLC1_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_OVF_INT_CLR  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_CLR_M  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_CLR_V  0x1
-#define SLC_SLC1_TX_OVF_INT_CLR_S  11
-/* SLC_SLC1_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_UDF_INT_CLR  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_CLR_M  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_CLR_V  0x1
-#define SLC_SLC1_RX_UDF_INT_CLR_S  10
-/* SLC_SLC1_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_START_INT_CLR  (BIT(9))
-#define SLC_SLC1_TX_START_INT_CLR_M  (BIT(9))
-#define SLC_SLC1_TX_START_INT_CLR_V  0x1
-#define SLC_SLC1_TX_START_INT_CLR_S  9
-/* SLC_SLC1_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_START_INT_CLR  (BIT(8))
-#define SLC_SLC1_RX_START_INT_CLR_M  (BIT(8))
-#define SLC_SLC1_RX_START_INT_CLR_V  0x1
-#define SLC_SLC1_RX_START_INT_CLR_S  8
-/* SLC_FRHOST_BIT15_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT15_INT_CLR  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_CLR_M  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT15_INT_CLR_S  7
-/* SLC_FRHOST_BIT14_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT14_INT_CLR  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_CLR_M  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT14_INT_CLR_S  6
-/* SLC_FRHOST_BIT13_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT13_INT_CLR  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_CLR_M  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT13_INT_CLR_S  5
-/* SLC_FRHOST_BIT12_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT12_INT_CLR  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_CLR_M  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT12_INT_CLR_S  4
-/* SLC_FRHOST_BIT11_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT11_INT_CLR  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_CLR_M  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT11_INT_CLR_S  3
-/* SLC_FRHOST_BIT10_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT10_INT_CLR  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_CLR_M  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT10_INT_CLR_S  2
-/* SLC_FRHOST_BIT9_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT9_INT_CLR  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_CLR_M  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT9_INT_CLR_S  1
-/* SLC_FRHOST_BIT8_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT8_INT_CLR  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_CLR_M  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_CLR_V  0x1
-#define SLC_FRHOST_BIT8_INT_CLR_S  0
-
-#define SLC_RX_STATUS_REG          (DR_REG_SLC_BASE + 0x24)
-/* SLC_SLC1_RX_EMPTY : RO ;bitpos:[17] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_RX_EMPTY  (BIT(17))
-#define SLC_SLC1_RX_EMPTY_M  (BIT(17))
-#define SLC_SLC1_RX_EMPTY_V  0x1
-#define SLC_SLC1_RX_EMPTY_S  17
-/* SLC_SLC1_RX_FULL : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_FULL  (BIT(16))
-#define SLC_SLC1_RX_FULL_M  (BIT(16))
-#define SLC_SLC1_RX_FULL_V  0x1
-#define SLC_SLC1_RX_FULL_S  16
-/* SLC_SLC0_RX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_EMPTY  (BIT(1))
-#define SLC_SLC0_RX_EMPTY_M  (BIT(1))
-#define SLC_SLC0_RX_EMPTY_V  0x1
-#define SLC_SLC0_RX_EMPTY_S  1
-/* SLC_SLC0_RX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_FULL  (BIT(0))
-#define SLC_SLC0_RX_FULL_M  (BIT(0))
-#define SLC_SLC0_RX_FULL_V  0x1
-#define SLC_SLC0_RX_FULL_S  0
-
-#define SLC_0RXFIFO_PUSH_REG          (DR_REG_SLC_BASE + 0x28)
-/* SLC_SLC0_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_RXFIFO_PUSH  (BIT(16))
-#define SLC_SLC0_RXFIFO_PUSH_M  (BIT(16))
-#define SLC_SLC0_RXFIFO_PUSH_V  0x1
-#define SLC_SLC0_RXFIFO_PUSH_S  16
-/* SLC_SLC0_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: */
-#define SLC_SLC0_RXFIFO_WDATA  0x000001FF
-#define SLC_SLC0_RXFIFO_WDATA_M  ((SLC_SLC0_RXFIFO_WDATA_V)<<(SLC_SLC0_RXFIFO_WDATA_S))
-#define SLC_SLC0_RXFIFO_WDATA_V  0x1FF
-#define SLC_SLC0_RXFIFO_WDATA_S  0
-
-#define SLC_1RXFIFO_PUSH_REG          (DR_REG_SLC_BASE + 0x2C)
-/* SLC_SLC1_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC1_RXFIFO_PUSH  (BIT(16))
-#define SLC_SLC1_RXFIFO_PUSH_M  (BIT(16))
-#define SLC_SLC1_RXFIFO_PUSH_V  0x1
-#define SLC_SLC1_RXFIFO_PUSH_S  16
-/* SLC_SLC1_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: */
-#define SLC_SLC1_RXFIFO_WDATA  0x000001FF
-#define SLC_SLC1_RXFIFO_WDATA_M  ((SLC_SLC1_RXFIFO_WDATA_V)<<(SLC_SLC1_RXFIFO_WDATA_S))
-#define SLC_SLC1_RXFIFO_WDATA_V  0x1FF
-#define SLC_SLC1_RXFIFO_WDATA_S  0
-
-#define SLC_TX_STATUS_REG          (DR_REG_SLC_BASE + 0x30)
-/* SLC_SLC1_TX_EMPTY : RO ;bitpos:[17] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_TX_EMPTY  (BIT(17))
-#define SLC_SLC1_TX_EMPTY_M  (BIT(17))
-#define SLC_SLC1_TX_EMPTY_V  0x1
-#define SLC_SLC1_TX_EMPTY_S  17
-/* SLC_SLC1_TX_FULL : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_FULL  (BIT(16))
-#define SLC_SLC1_TX_FULL_M  (BIT(16))
-#define SLC_SLC1_TX_FULL_V  0x1
-#define SLC_SLC1_TX_FULL_S  16
-/* SLC_SLC0_TX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TX_EMPTY  (BIT(1))
-#define SLC_SLC0_TX_EMPTY_M  (BIT(1))
-#define SLC_SLC0_TX_EMPTY_V  0x1
-#define SLC_SLC0_TX_EMPTY_S  1
-/* SLC_SLC0_TX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_FULL  (BIT(0))
-#define SLC_SLC0_TX_FULL_M  (BIT(0))
-#define SLC_SLC0_TX_FULL_V  0x1
-#define SLC_SLC0_TX_FULL_S  0
-
-#define SLC_0TXFIFO_POP_REG          (DR_REG_SLC_BASE + 0x34)
-/* SLC_SLC0_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_TXFIFO_POP  (BIT(16))
-#define SLC_SLC0_TXFIFO_POP_M  (BIT(16))
-#define SLC_SLC0_TXFIFO_POP_V  0x1
-#define SLC_SLC0_TXFIFO_POP_S  16
-/* SLC_SLC0_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */
-/*description: */
-#define SLC_SLC0_TXFIFO_RDATA  0x000007FF
-#define SLC_SLC0_TXFIFO_RDATA_M  ((SLC_SLC0_TXFIFO_RDATA_V)<<(SLC_SLC0_TXFIFO_RDATA_S))
-#define SLC_SLC0_TXFIFO_RDATA_V  0x7FF
-#define SLC_SLC0_TXFIFO_RDATA_S  0
-
-#define SLC_1TXFIFO_POP_REG          (DR_REG_SLC_BASE + 0x38)
-/* SLC_SLC1_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC1_TXFIFO_POP  (BIT(16))
-#define SLC_SLC1_TXFIFO_POP_M  (BIT(16))
-#define SLC_SLC1_TXFIFO_POP_V  0x1
-#define SLC_SLC1_TXFIFO_POP_S  16
-/* SLC_SLC1_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */
-/*description: */
-#define SLC_SLC1_TXFIFO_RDATA  0x000007FF
-#define SLC_SLC1_TXFIFO_RDATA_M  ((SLC_SLC1_TXFIFO_RDATA_V)<<(SLC_SLC1_TXFIFO_RDATA_S))
-#define SLC_SLC1_TXFIFO_RDATA_V  0x7FF
-#define SLC_SLC1_TXFIFO_RDATA_S  0
-
-#define SLC_0RX_LINK_REG          (DR_REG_SLC_BASE + 0x3C)
-/* SLC_SLC0_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_PARK  (BIT(31))
-#define SLC_SLC0_RXLINK_PARK_M  (BIT(31))
-#define SLC_SLC0_RXLINK_PARK_V  0x1
-#define SLC_SLC0_RXLINK_PARK_S  31
-/* SLC_SLC0_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_RESTART  (BIT(30))
-#define SLC_SLC0_RXLINK_RESTART_M  (BIT(30))
-#define SLC_SLC0_RXLINK_RESTART_V  0x1
-#define SLC_SLC0_RXLINK_RESTART_S  30
-/* SLC_SLC0_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_START  (BIT(29))
-#define SLC_SLC0_RXLINK_START_M  (BIT(29))
-#define SLC_SLC0_RXLINK_START_V  0x1
-#define SLC_SLC0_RXLINK_START_S  29
-/* SLC_SLC0_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_STOP  (BIT(28))
-#define SLC_SLC0_RXLINK_STOP_M  (BIT(28))
-#define SLC_SLC0_RXLINK_STOP_V  0x1
-#define SLC_SLC0_RXLINK_STOP_S  28
-/* SLC_SLC0_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_ADDR  0x000FFFFF
-#define SLC_SLC0_RXLINK_ADDR_M  ((SLC_SLC0_RXLINK_ADDR_V)<<(SLC_SLC0_RXLINK_ADDR_S))
-#define SLC_SLC0_RXLINK_ADDR_V  0xFFFFF
-#define SLC_SLC0_RXLINK_ADDR_S  0
-
-#define SLC_0TX_LINK_REG          (DR_REG_SLC_BASE + 0x40)
-/* SLC_SLC0_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_PARK  (BIT(31))
-#define SLC_SLC0_TXLINK_PARK_M  (BIT(31))
-#define SLC_SLC0_TXLINK_PARK_V  0x1
-#define SLC_SLC0_TXLINK_PARK_S  31
-/* SLC_SLC0_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_RESTART  (BIT(30))
-#define SLC_SLC0_TXLINK_RESTART_M  (BIT(30))
-#define SLC_SLC0_TXLINK_RESTART_V  0x1
-#define SLC_SLC0_TXLINK_RESTART_S  30
-/* SLC_SLC0_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_START  (BIT(29))
-#define SLC_SLC0_TXLINK_START_M  (BIT(29))
-#define SLC_SLC0_TXLINK_START_V  0x1
-#define SLC_SLC0_TXLINK_START_S  29
-/* SLC_SLC0_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_STOP  (BIT(28))
-#define SLC_SLC0_TXLINK_STOP_M  (BIT(28))
-#define SLC_SLC0_TXLINK_STOP_V  0x1
-#define SLC_SLC0_TXLINK_STOP_S  28
-/* SLC_SLC0_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_ADDR  0x000FFFFF
-#define SLC_SLC0_TXLINK_ADDR_M  ((SLC_SLC0_TXLINK_ADDR_V)<<(SLC_SLC0_TXLINK_ADDR_S))
-#define SLC_SLC0_TXLINK_ADDR_V  0xFFFFF
-#define SLC_SLC0_TXLINK_ADDR_S  0
-
-#define SLC_1RX_LINK_REG          (DR_REG_SLC_BASE + 0x44)
-/* SLC_SLC1_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC1_RXLINK_PARK  (BIT(31))
-#define SLC_SLC1_RXLINK_PARK_M  (BIT(31))
-#define SLC_SLC1_RXLINK_PARK_V  0x1
-#define SLC_SLC1_RXLINK_PARK_S  31
-/* SLC_SLC1_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RXLINK_RESTART  (BIT(30))
-#define SLC_SLC1_RXLINK_RESTART_M  (BIT(30))
-#define SLC_SLC1_RXLINK_RESTART_V  0x1
-#define SLC_SLC1_RXLINK_RESTART_S  30
-/* SLC_SLC1_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RXLINK_START  (BIT(29))
-#define SLC_SLC1_RXLINK_START_M  (BIT(29))
-#define SLC_SLC1_RXLINK_START_V  0x1
-#define SLC_SLC1_RXLINK_START_S  29
-/* SLC_SLC1_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RXLINK_STOP  (BIT(28))
-#define SLC_SLC1_RXLINK_STOP_M  (BIT(28))
-#define SLC_SLC1_RXLINK_STOP_V  0x1
-#define SLC_SLC1_RXLINK_STOP_S  28
-/* SLC_SLC1_BT_PACKET : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_BT_PACKET  (BIT(20))
-#define SLC_SLC1_BT_PACKET_M  (BIT(20))
-#define SLC_SLC1_BT_PACKET_V  0x1
-#define SLC_SLC1_BT_PACKET_S  20
-/* SLC_SLC1_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC1_RXLINK_ADDR  0x000FFFFF
-#define SLC_SLC1_RXLINK_ADDR_M  ((SLC_SLC1_RXLINK_ADDR_V)<<(SLC_SLC1_RXLINK_ADDR_S))
-#define SLC_SLC1_RXLINK_ADDR_V  0xFFFFF
-#define SLC_SLC1_RXLINK_ADDR_S  0
-
-#define SLC_1TX_LINK_REG          (DR_REG_SLC_BASE + 0x48)
-/* SLC_SLC1_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC1_TXLINK_PARK  (BIT(31))
-#define SLC_SLC1_TXLINK_PARK_M  (BIT(31))
-#define SLC_SLC1_TXLINK_PARK_V  0x1
-#define SLC_SLC1_TXLINK_PARK_S  31
-/* SLC_SLC1_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TXLINK_RESTART  (BIT(30))
-#define SLC_SLC1_TXLINK_RESTART_M  (BIT(30))
-#define SLC_SLC1_TXLINK_RESTART_V  0x1
-#define SLC_SLC1_TXLINK_RESTART_S  30
-/* SLC_SLC1_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TXLINK_START  (BIT(29))
-#define SLC_SLC1_TXLINK_START_M  (BIT(29))
-#define SLC_SLC1_TXLINK_START_V  0x1
-#define SLC_SLC1_TXLINK_START_S  29
-/* SLC_SLC1_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TXLINK_STOP  (BIT(28))
-#define SLC_SLC1_TXLINK_STOP_M  (BIT(28))
-#define SLC_SLC1_TXLINK_STOP_V  0x1
-#define SLC_SLC1_TXLINK_STOP_S  28
-/* SLC_SLC1_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC1_TXLINK_ADDR  0x000FFFFF
-#define SLC_SLC1_TXLINK_ADDR_M  ((SLC_SLC1_TXLINK_ADDR_V)<<(SLC_SLC1_TXLINK_ADDR_S))
-#define SLC_SLC1_TXLINK_ADDR_V  0xFFFFF
-#define SLC_SLC1_TXLINK_ADDR_S  0
-
-#define SLC_INTVEC_TOHOST_REG          (DR_REG_SLC_BASE + 0x4C)
-/* SLC_SLC1_TOHOST_INTVEC : WO ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define SLC_SLC1_TOHOST_INTVEC  0x000000FF
-#define SLC_SLC1_TOHOST_INTVEC_M  ((SLC_SLC1_TOHOST_INTVEC_V)<<(SLC_SLC1_TOHOST_INTVEC_S))
-#define SLC_SLC1_TOHOST_INTVEC_V  0xFF
-#define SLC_SLC1_TOHOST_INTVEC_S  16
-/* SLC_SLC0_TOHOST_INTVEC : WO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INTVEC  0x000000FF
-#define SLC_SLC0_TOHOST_INTVEC_M  ((SLC_SLC0_TOHOST_INTVEC_V)<<(SLC_SLC0_TOHOST_INTVEC_S))
-#define SLC_SLC0_TOHOST_INTVEC_V  0xFF
-#define SLC_SLC0_TOHOST_INTVEC_S  0
-
-#define SLC_0TOKEN0_REG          (DR_REG_SLC_BASE + 0x50)
-/* SLC_SLC0_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0  0x00000FFF
-#define SLC_SLC0_TOKEN0_M  ((SLC_SLC0_TOKEN0_V)<<(SLC_SLC0_TOKEN0_S))
-#define SLC_SLC0_TOKEN0_V  0xFFF
-#define SLC_SLC0_TOKEN0_S  16
-/* SLC_SLC0_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_INC_MORE  (BIT(14))
-#define SLC_SLC0_TOKEN0_INC_MORE_M  (BIT(14))
-#define SLC_SLC0_TOKEN0_INC_MORE_V  0x1
-#define SLC_SLC0_TOKEN0_INC_MORE_S  14
-/* SLC_SLC0_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_INC  (BIT(13))
-#define SLC_SLC0_TOKEN0_INC_M  (BIT(13))
-#define SLC_SLC0_TOKEN0_INC_V  0x1
-#define SLC_SLC0_TOKEN0_INC_S  13
-/* SLC_SLC0_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_WR  (BIT(12))
-#define SLC_SLC0_TOKEN0_WR_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_WR_V  0x1
-#define SLC_SLC0_TOKEN0_WR_S  12
-/* SLC_SLC0_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_WDATA  0x00000FFF
-#define SLC_SLC0_TOKEN0_WDATA_M  ((SLC_SLC0_TOKEN0_WDATA_V)<<(SLC_SLC0_TOKEN0_WDATA_S))
-#define SLC_SLC0_TOKEN0_WDATA_V  0xFFF
-#define SLC_SLC0_TOKEN0_WDATA_S  0
-
-#define SLC_0TOKEN1_REG          (DR_REG_SLC_BASE + 0x54)
-/* SLC_SLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1  0x00000FFF
-#define SLC_SLC0_TOKEN1_M  ((SLC_SLC0_TOKEN1_V)<<(SLC_SLC0_TOKEN1_S))
-#define SLC_SLC0_TOKEN1_V  0xFFF
-#define SLC_SLC0_TOKEN1_S  16
-/* SLC_SLC0_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_INC_MORE  (BIT(14))
-#define SLC_SLC0_TOKEN1_INC_MORE_M  (BIT(14))
-#define SLC_SLC0_TOKEN1_INC_MORE_V  0x1
-#define SLC_SLC0_TOKEN1_INC_MORE_S  14
-/* SLC_SLC0_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_INC  (BIT(13))
-#define SLC_SLC0_TOKEN1_INC_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_INC_V  0x1
-#define SLC_SLC0_TOKEN1_INC_S  13
-/* SLC_SLC0_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_WR  (BIT(12))
-#define SLC_SLC0_TOKEN1_WR_M  (BIT(12))
-#define SLC_SLC0_TOKEN1_WR_V  0x1
-#define SLC_SLC0_TOKEN1_WR_S  12
-/* SLC_SLC0_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_WDATA  0x00000FFF
-#define SLC_SLC0_TOKEN1_WDATA_M  ((SLC_SLC0_TOKEN1_WDATA_V)<<(SLC_SLC0_TOKEN1_WDATA_S))
-#define SLC_SLC0_TOKEN1_WDATA_V  0xFFF
-#define SLC_SLC0_TOKEN1_WDATA_S  0
-
-#define SLC_1TOKEN0_REG          (DR_REG_SLC_BASE + 0x58)
-/* SLC_SLC1_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0  0x00000FFF
-#define SLC_SLC1_TOKEN0_M  ((SLC_SLC1_TOKEN0_V)<<(SLC_SLC1_TOKEN0_S))
-#define SLC_SLC1_TOKEN0_V  0xFFF
-#define SLC_SLC1_TOKEN0_S  16
-/* SLC_SLC1_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_INC_MORE  (BIT(14))
-#define SLC_SLC1_TOKEN0_INC_MORE_M  (BIT(14))
-#define SLC_SLC1_TOKEN0_INC_MORE_V  0x1
-#define SLC_SLC1_TOKEN0_INC_MORE_S  14
-/* SLC_SLC1_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_INC  (BIT(13))
-#define SLC_SLC1_TOKEN0_INC_M  (BIT(13))
-#define SLC_SLC1_TOKEN0_INC_V  0x1
-#define SLC_SLC1_TOKEN0_INC_S  13
-/* SLC_SLC1_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_WR  (BIT(12))
-#define SLC_SLC1_TOKEN0_WR_M  (BIT(12))
-#define SLC_SLC1_TOKEN0_WR_V  0x1
-#define SLC_SLC1_TOKEN0_WR_S  12
-/* SLC_SLC1_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_WDATA  0x00000FFF
-#define SLC_SLC1_TOKEN0_WDATA_M  ((SLC_SLC1_TOKEN0_WDATA_V)<<(SLC_SLC1_TOKEN0_WDATA_S))
-#define SLC_SLC1_TOKEN0_WDATA_V  0xFFF
-#define SLC_SLC1_TOKEN0_WDATA_S  0
-
-#define SLC_1TOKEN1_REG          (DR_REG_SLC_BASE + 0x5C)
-/* SLC_SLC1_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1  0x00000FFF
-#define SLC_SLC1_TOKEN1_M  ((SLC_SLC1_TOKEN1_V)<<(SLC_SLC1_TOKEN1_S))
-#define SLC_SLC1_TOKEN1_V  0xFFF
-#define SLC_SLC1_TOKEN1_S  16
-/* SLC_SLC1_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_INC_MORE  (BIT(14))
-#define SLC_SLC1_TOKEN1_INC_MORE_M  (BIT(14))
-#define SLC_SLC1_TOKEN1_INC_MORE_V  0x1
-#define SLC_SLC1_TOKEN1_INC_MORE_S  14
-/* SLC_SLC1_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_INC  (BIT(13))
-#define SLC_SLC1_TOKEN1_INC_M  (BIT(13))
-#define SLC_SLC1_TOKEN1_INC_V  0x1
-#define SLC_SLC1_TOKEN1_INC_S  13
-/* SLC_SLC1_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_WR  (BIT(12))
-#define SLC_SLC1_TOKEN1_WR_M  (BIT(12))
-#define SLC_SLC1_TOKEN1_WR_V  0x1
-#define SLC_SLC1_TOKEN1_WR_S  12
-/* SLC_SLC1_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_WDATA  0x00000FFF
-#define SLC_SLC1_TOKEN1_WDATA_M  ((SLC_SLC1_TOKEN1_WDATA_V)<<(SLC_SLC1_TOKEN1_WDATA_S))
-#define SLC_SLC1_TOKEN1_WDATA_V  0xFFF
-#define SLC_SLC1_TOKEN1_WDATA_S  0
-
-#define SLC_CONF1_REG          (DR_REG_SLC_BASE + 0x60)
-/* SLC_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CLK_EN  (BIT(22))
-#define SLC_CLK_EN_M  (BIT(22))
-#define SLC_CLK_EN_V  0x1
-#define SLC_CLK_EN_S  22
-/* SLC_SLC1_RX_STITCH_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_RX_STITCH_EN  (BIT(21))
-#define SLC_SLC1_RX_STITCH_EN_M  (BIT(21))
-#define SLC_SLC1_RX_STITCH_EN_V  0x1
-#define SLC_SLC1_RX_STITCH_EN_S  21
-/* SLC_SLC1_TX_STITCH_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_TX_STITCH_EN  (BIT(20))
-#define SLC_SLC1_TX_STITCH_EN_M  (BIT(20))
-#define SLC_SLC1_TX_STITCH_EN_V  0x1
-#define SLC_SLC1_TX_STITCH_EN_S  20
-/* SLC_HOST_INT_LEVEL_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_HOST_INT_LEVEL_SEL  (BIT(19))
-#define SLC_HOST_INT_LEVEL_SEL_M  (BIT(19))
-#define SLC_HOST_INT_LEVEL_SEL_V  0x1
-#define SLC_HOST_INT_LEVEL_SEL_S  19
-/* SLC_SLC1_RX_CHECK_SUM_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_CHECK_SUM_EN  (BIT(18))
-#define SLC_SLC1_RX_CHECK_SUM_EN_M  (BIT(18))
-#define SLC_SLC1_RX_CHECK_SUM_EN_V  0x1
-#define SLC_SLC1_RX_CHECK_SUM_EN_S  18
-/* SLC_SLC1_TX_CHECK_SUM_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_CHECK_SUM_EN  (BIT(17))
-#define SLC_SLC1_TX_CHECK_SUM_EN_M  (BIT(17))
-#define SLC_SLC1_TX_CHECK_SUM_EN_V  0x1
-#define SLC_SLC1_TX_CHECK_SUM_EN_S  17
-/* SLC_SLC1_CHECK_OWNER : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_CHECK_OWNER  (BIT(16))
-#define SLC_SLC1_CHECK_OWNER_M  (BIT(16))
-#define SLC_SLC1_CHECK_OWNER_V  0x1
-#define SLC_SLC1_CHECK_OWNER_S  16
-/* SLC_SLC0_RX_STITCH_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_STITCH_EN  (BIT(6))
-#define SLC_SLC0_RX_STITCH_EN_M  (BIT(6))
-#define SLC_SLC0_RX_STITCH_EN_V  0x1
-#define SLC_SLC0_RX_STITCH_EN_S  6
-/* SLC_SLC0_TX_STITCH_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_TX_STITCH_EN  (BIT(5))
-#define SLC_SLC0_TX_STITCH_EN_M  (BIT(5))
-#define SLC_SLC0_TX_STITCH_EN_V  0x1
-#define SLC_SLC0_TX_STITCH_EN_S  5
-/* SLC_SLC0_LEN_AUTO_CLR : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_LEN_AUTO_CLR  (BIT(4))
-#define SLC_SLC0_LEN_AUTO_CLR_M  (BIT(4))
-#define SLC_SLC0_LEN_AUTO_CLR_V  0x1
-#define SLC_SLC0_LEN_AUTO_CLR_S  4
-/* SLC_CMD_HOLD_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define SLC_CMD_HOLD_EN  (BIT(3))
-#define SLC_CMD_HOLD_EN_M  (BIT(3))
-#define SLC_CMD_HOLD_EN_V  0x1
-#define SLC_CMD_HOLD_EN_S  3
-/* SLC_SLC0_RX_CHECK_SUM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_CHECK_SUM_EN  (BIT(2))
-#define SLC_SLC0_RX_CHECK_SUM_EN_M  (BIT(2))
-#define SLC_SLC0_RX_CHECK_SUM_EN_V  0x1
-#define SLC_SLC0_RX_CHECK_SUM_EN_S  2
-/* SLC_SLC0_TX_CHECK_SUM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_CHECK_SUM_EN  (BIT(1))
-#define SLC_SLC0_TX_CHECK_SUM_EN_M  (BIT(1))
-#define SLC_SLC0_TX_CHECK_SUM_EN_V  0x1
-#define SLC_SLC0_TX_CHECK_SUM_EN_S  1
-/* SLC_SLC0_CHECK_OWNER : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_CHECK_OWNER  (BIT(0))
-#define SLC_SLC0_CHECK_OWNER_M  (BIT(0))
-#define SLC_SLC0_CHECK_OWNER_V  0x1
-#define SLC_SLC0_CHECK_OWNER_S  0
-
-#define SLC_0_STATE0_REG          (DR_REG_SLC_BASE + 0x64)
-/* SLC_SLC0_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_STATE0  0xFFFFFFFF
-#define SLC_SLC0_STATE0_M  ((SLC_SLC0_STATE0_V)<<(SLC_SLC0_STATE0_S))
-#define SLC_SLC0_STATE0_V  0xFFFFFFFF
-#define SLC_SLC0_STATE0_S  0
-
-#define SLC_0_STATE1_REG          (DR_REG_SLC_BASE + 0x68)
-/* SLC_SLC0_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_STATE1  0xFFFFFFFF
-#define SLC_SLC0_STATE1_M  ((SLC_SLC0_STATE1_V)<<(SLC_SLC0_STATE1_S))
-#define SLC_SLC0_STATE1_V  0xFFFFFFFF
-#define SLC_SLC0_STATE1_S  0
-
-#define SLC_1_STATE0_REG          (DR_REG_SLC_BASE + 0x6C)
-/* SLC_SLC1_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC1_STATE0  0xFFFFFFFF
-#define SLC_SLC1_STATE0_M  ((SLC_SLC1_STATE0_V)<<(SLC_SLC1_STATE0_S))
-#define SLC_SLC1_STATE0_V  0xFFFFFFFF
-#define SLC_SLC1_STATE0_S  0
-
-#define SLC_1_STATE1_REG          (DR_REG_SLC_BASE + 0x70)
-/* SLC_SLC1_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC1_STATE1  0xFFFFFFFF
-#define SLC_SLC1_STATE1_M  ((SLC_SLC1_STATE1_V)<<(SLC_SLC1_STATE1_S))
-#define SLC_SLC1_STATE1_V  0xFFFFFFFF
-#define SLC_SLC1_STATE1_S  0
-
-#define SLC_BRIDGE_CONF_REG          (DR_REG_SLC_BASE + 0x74)
-/* SLC_TX_PUSH_IDLE_NUM : R/W ;bitpos:[31:16] ;default: 16'ha ; */
-/*description: */
-#define SLC_TX_PUSH_IDLE_NUM  0x0000FFFF
-#define SLC_TX_PUSH_IDLE_NUM_M  ((SLC_TX_PUSH_IDLE_NUM_V)<<(SLC_TX_PUSH_IDLE_NUM_S))
-#define SLC_TX_PUSH_IDLE_NUM_V  0xFFFF
-#define SLC_TX_PUSH_IDLE_NUM_S  16
-/* SLC_SLC1_TX_DUMMY_MODE : R/W ;bitpos:[14] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC1_TX_DUMMY_MODE  (BIT(14))
-#define SLC_SLC1_TX_DUMMY_MODE_M  (BIT(14))
-#define SLC_SLC1_TX_DUMMY_MODE_V  0x1
-#define SLC_SLC1_TX_DUMMY_MODE_S  14
-/* SLC_HDA_MAP_128K : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: */
-#define SLC_HDA_MAP_128K  (BIT(13))
-#define SLC_HDA_MAP_128K_M  (BIT(13))
-#define SLC_HDA_MAP_128K_V  0x1
-#define SLC_HDA_MAP_128K_S  13
-/* SLC_SLC0_TX_DUMMY_MODE : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: */
-#define SLC_SLC0_TX_DUMMY_MODE  (BIT(12))
-#define SLC_SLC0_TX_DUMMY_MODE_M  (BIT(12))
-#define SLC_SLC0_TX_DUMMY_MODE_V  0x1
-#define SLC_SLC0_TX_DUMMY_MODE_S  12
-/* SLC_FIFO_MAP_ENA : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
-/*description: */
-#define SLC_FIFO_MAP_ENA  0x0000000F
-#define SLC_FIFO_MAP_ENA_M  ((SLC_FIFO_MAP_ENA_V)<<(SLC_FIFO_MAP_ENA_S))
-#define SLC_FIFO_MAP_ENA_V  0xF
-#define SLC_FIFO_MAP_ENA_S  8
-/* SLC_TXEOF_ENA : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
-/*description: */
-#define SLC_TXEOF_ENA  0x0000003F
-#define SLC_TXEOF_ENA_M  ((SLC_TXEOF_ENA_V)<<(SLC_TXEOF_ENA_S))
-#define SLC_TXEOF_ENA_V  0x3F
-#define SLC_TXEOF_ENA_S  0
-
-#define SLC_0_TO_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x78)
-/* SLC_SLC0_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TO_EOF_DES_ADDR  0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_DES_ADDR_M  ((SLC_SLC0_TO_EOF_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_DES_ADDR_S))
-#define SLC_SLC0_TO_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_DES_ADDR_S  0
-
-#define SLC_0_TX_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x7C)
-/* SLC_SLC0_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR  0xFFFFFFFF
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M  ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_SUC_EOF_DES_ADDR_S))
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S  0
-
-#define SLC_0_TO_EOF_BFR_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x80)
-/* SLC_SLC0_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR  0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M  ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_BFR_DES_ADDR_S))
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S  0
-
-#define SLC_1_TO_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x84)
-/* SLC_SLC1_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC1_TO_EOF_DES_ADDR  0xFFFFFFFF
-#define SLC_SLC1_TO_EOF_DES_ADDR_M  ((SLC_SLC1_TO_EOF_DES_ADDR_V)<<(SLC_SLC1_TO_EOF_DES_ADDR_S))
-#define SLC_SLC1_TO_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC1_TO_EOF_DES_ADDR_S  0
-
-#define SLC_1_TX_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x88)
-/* SLC_SLC1_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC1_TX_SUC_EOF_DES_ADDR  0xFFFFFFFF
-#define SLC_SLC1_TX_SUC_EOF_DES_ADDR_M  ((SLC_SLC1_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC1_TX_SUC_EOF_DES_ADDR_S))
-#define SLC_SLC1_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC1_TX_SUC_EOF_DES_ADDR_S  0
-
-#define SLC_1_TO_EOF_BFR_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x8C)
-/* SLC_SLC1_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC1_TO_EOF_BFR_DES_ADDR  0xFFFFFFFF
-#define SLC_SLC1_TO_EOF_BFR_DES_ADDR_M  ((SLC_SLC1_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC1_TO_EOF_BFR_DES_ADDR_S))
-#define SLC_SLC1_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC1_TO_EOF_BFR_DES_ADDR_S  0
-
-#define SLC_AHB_TEST_REG          (DR_REG_SLC_BASE + 0x90)
-/* SLC_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define SLC_AHB_TESTADDR  0x00000003
-#define SLC_AHB_TESTADDR_M  ((SLC_AHB_TESTADDR_V)<<(SLC_AHB_TESTADDR_S))
-#define SLC_AHB_TESTADDR_V  0x3
-#define SLC_AHB_TESTADDR_S  4
-/* SLC_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define SLC_AHB_TESTMODE  0x00000007
-#define SLC_AHB_TESTMODE_M  ((SLC_AHB_TESTMODE_V)<<(SLC_AHB_TESTMODE_S))
-#define SLC_AHB_TESTMODE_V  0x7
-#define SLC_AHB_TESTMODE_S  0
-
-#define SLC_SDIO_ST_REG          (DR_REG_SLC_BASE + 0x94)
-/* SLC_FUNC2_ACC_STATE : RO ;bitpos:[28:24] ;default: 5'b0 ; */
-/*description: */
-#define SLC_FUNC2_ACC_STATE  0x0000001F
-#define SLC_FUNC2_ACC_STATE_M  ((SLC_FUNC2_ACC_STATE_V)<<(SLC_FUNC2_ACC_STATE_S))
-#define SLC_FUNC2_ACC_STATE_V  0x1F
-#define SLC_FUNC2_ACC_STATE_S  24
-/* SLC_FUNC1_ACC_STATE : RO ;bitpos:[20:16] ;default: 5'b0 ; */
-/*description: */
-#define SLC_FUNC1_ACC_STATE  0x0000001F
-#define SLC_FUNC1_ACC_STATE_M  ((SLC_FUNC1_ACC_STATE_V)<<(SLC_FUNC1_ACC_STATE_S))
-#define SLC_FUNC1_ACC_STATE_V  0x1F
-#define SLC_FUNC1_ACC_STATE_S  16
-/* SLC_BUS_ST : RO ;bitpos:[14:12] ;default: 3'b0 ; */
-/*description: */
-#define SLC_BUS_ST  0x00000007
-#define SLC_BUS_ST_M  ((SLC_BUS_ST_V)<<(SLC_BUS_ST_S))
-#define SLC_BUS_ST_V  0x7
-#define SLC_BUS_ST_S  12
-/* SLC_SDIO_WAKEUP : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SDIO_WAKEUP  (BIT(8))
-#define SLC_SDIO_WAKEUP_M  (BIT(8))
-#define SLC_SDIO_WAKEUP_V  0x1
-#define SLC_SDIO_WAKEUP_S  8
-/* SLC_FUNC_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: */
-#define SLC_FUNC_ST  0x0000000F
-#define SLC_FUNC_ST_M  ((SLC_FUNC_ST_V)<<(SLC_FUNC_ST_S))
-#define SLC_FUNC_ST_V  0xF
-#define SLC_FUNC_ST_S  4
-/* SLC_CMD_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define SLC_CMD_ST  0x00000007
-#define SLC_CMD_ST_M  ((SLC_CMD_ST_V)<<(SLC_CMD_ST_S))
-#define SLC_CMD_ST_V  0x7
-#define SLC_CMD_ST_S  0
-
-#define SLC_RX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0x98)
-/* SLC_SLC1_RD_RETRY_THRESHOLD : R/W ;bitpos:[31:21] ;default: 11'h80 ; */
-/*description: */
-#define SLC_SLC1_RD_RETRY_THRESHOLD  0x000007FF
-#define SLC_SLC1_RD_RETRY_THRESHOLD_M  ((SLC_SLC1_RD_RETRY_THRESHOLD_V)<<(SLC_SLC1_RD_RETRY_THRESHOLD_S))
-#define SLC_SLC1_RD_RETRY_THRESHOLD_V  0x7FF
-#define SLC_SLC1_RD_RETRY_THRESHOLD_S  21
-/* SLC_SLC1_RX_FILL_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_RX_FILL_EN  (BIT(20))
-#define SLC_SLC1_RX_FILL_EN_M  (BIT(20))
-#define SLC_SLC1_RX_FILL_EN_V  0x1
-#define SLC_SLC1_RX_FILL_EN_S  20
-/* SLC_SLC1_RX_EOF_MODE : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_RX_EOF_MODE  (BIT(19))
-#define SLC_SLC1_RX_EOF_MODE_M  (BIT(19))
-#define SLC_SLC1_RX_EOF_MODE_V  0x1
-#define SLC_SLC1_RX_EOF_MODE_S  19
-/* SLC_SLC1_RX_FILL_MODE : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_FILL_MODE  (BIT(18))
-#define SLC_SLC1_RX_FILL_MODE_M  (BIT(18))
-#define SLC_SLC1_RX_FILL_MODE_V  0x1
-#define SLC_SLC1_RX_FILL_MODE_S  18
-/* SLC_SLC1_INFOR_NO_REPLACE : R/W ;bitpos:[17] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_INFOR_NO_REPLACE  (BIT(17))
-#define SLC_SLC1_INFOR_NO_REPLACE_M  (BIT(17))
-#define SLC_SLC1_INFOR_NO_REPLACE_V  0x1
-#define SLC_SLC1_INFOR_NO_REPLACE_S  17
-/* SLC_SLC1_TOKEN_NO_REPLACE : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC1_TOKEN_NO_REPLACE  (BIT(16))
-#define SLC_SLC1_TOKEN_NO_REPLACE_M  (BIT(16))
-#define SLC_SLC1_TOKEN_NO_REPLACE_V  0x1
-#define SLC_SLC1_TOKEN_NO_REPLACE_S  16
-/* SLC_SLC0_RD_RETRY_THRESHOLD : R/W ;bitpos:[15:5] ;default: 11'h80 ; */
-/*description: */
-#define SLC_SLC0_RD_RETRY_THRESHOLD  0x000007FF
-#define SLC_SLC0_RD_RETRY_THRESHOLD_M  ((SLC_SLC0_RD_RETRY_THRESHOLD_V)<<(SLC_SLC0_RD_RETRY_THRESHOLD_S))
-#define SLC_SLC0_RD_RETRY_THRESHOLD_V  0x7FF
-#define SLC_SLC0_RD_RETRY_THRESHOLD_S  5
-/* SLC_SLC0_RX_FILL_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_FILL_EN  (BIT(4))
-#define SLC_SLC0_RX_FILL_EN_M  (BIT(4))
-#define SLC_SLC0_RX_FILL_EN_V  0x1
-#define SLC_SLC0_RX_FILL_EN_S  4
-/* SLC_SLC0_RX_EOF_MODE : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_MODE  (BIT(3))
-#define SLC_SLC0_RX_EOF_MODE_M  (BIT(3))
-#define SLC_SLC0_RX_EOF_MODE_V  0x1
-#define SLC_SLC0_RX_EOF_MODE_S  3
-/* SLC_SLC0_RX_FILL_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_FILL_MODE  (BIT(2))
-#define SLC_SLC0_RX_FILL_MODE_M  (BIT(2))
-#define SLC_SLC0_RX_FILL_MODE_V  0x1
-#define SLC_SLC0_RX_FILL_MODE_S  2
-/* SLC_SLC0_INFOR_NO_REPLACE : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SLC_SLC0_INFOR_NO_REPLACE  (BIT(1))
-#define SLC_SLC0_INFOR_NO_REPLACE_M  (BIT(1))
-#define SLC_SLC0_INFOR_NO_REPLACE_V  0x1
-#define SLC_SLC0_INFOR_NO_REPLACE_S  1
-/* SLC_SLC0_TOKEN_NO_REPLACE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN_NO_REPLACE  (BIT(0))
-#define SLC_SLC0_TOKEN_NO_REPLACE_M  (BIT(0))
-#define SLC_SLC0_TOKEN_NO_REPLACE_V  0x1
-#define SLC_SLC0_TOKEN_NO_REPLACE_S  0
-
-#define SLC_0_TXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0x9C)
-/* SLC_SLC0_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_DSCR  0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_M  ((SLC_SLC0_TXLINK_DSCR_V)<<(SLC_SLC0_TXLINK_DSCR_S))
-#define SLC_SLC0_TXLINK_DSCR_V  0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_S  0
-
-#define SLC_0_TXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xA0)
-/* SLC_SLC0_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_DSCR_BF0  0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF0_M  ((SLC_SLC0_TXLINK_DSCR_BF0_V)<<(SLC_SLC0_TXLINK_DSCR_BF0_S))
-#define SLC_SLC0_TXLINK_DSCR_BF0_V  0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF0_S  0
-
-#define SLC_0_TXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xA4)
-/* SLC_SLC0_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_TXLINK_DSCR_BF1  0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF1_M  ((SLC_SLC0_TXLINK_DSCR_BF1_V)<<(SLC_SLC0_TXLINK_DSCR_BF1_S))
-#define SLC_SLC0_TXLINK_DSCR_BF1_V  0xFFFFFFFF
-#define SLC_SLC0_TXLINK_DSCR_BF1_S  0
-
-#define SLC_0_RXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0xA8)
-/* SLC_SLC0_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_DSCR  0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_M  ((SLC_SLC0_RXLINK_DSCR_V)<<(SLC_SLC0_RXLINK_DSCR_S))
-#define SLC_SLC0_RXLINK_DSCR_V  0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_S  0
-
-#define SLC_0_RXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xAC)
-/* SLC_SLC0_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_DSCR_BF0  0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF0_M  ((SLC_SLC0_RXLINK_DSCR_BF0_V)<<(SLC_SLC0_RXLINK_DSCR_BF0_S))
-#define SLC_SLC0_RXLINK_DSCR_BF0_V  0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF0_S  0
-
-#define SLC_0_RXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xB0)
-/* SLC_SLC0_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RXLINK_DSCR_BF1  0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF1_M  ((SLC_SLC0_RXLINK_DSCR_BF1_V)<<(SLC_SLC0_RXLINK_DSCR_BF1_S))
-#define SLC_SLC0_RXLINK_DSCR_BF1_V  0xFFFFFFFF
-#define SLC_SLC0_RXLINK_DSCR_BF1_S  0
-
-#define SLC_1_TXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0xB4)
-/* SLC_SLC1_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC1_TXLINK_DSCR  0xFFFFFFFF
-#define SLC_SLC1_TXLINK_DSCR_M  ((SLC_SLC1_TXLINK_DSCR_V)<<(SLC_SLC1_TXLINK_DSCR_S))
-#define SLC_SLC1_TXLINK_DSCR_V  0xFFFFFFFF
-#define SLC_SLC1_TXLINK_DSCR_S  0
-
-#define SLC_1_TXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xB8)
-/* SLC_SLC1_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC1_TXLINK_DSCR_BF0  0xFFFFFFFF
-#define SLC_SLC1_TXLINK_DSCR_BF0_M  ((SLC_SLC1_TXLINK_DSCR_BF0_V)<<(SLC_SLC1_TXLINK_DSCR_BF0_S))
-#define SLC_SLC1_TXLINK_DSCR_BF0_V  0xFFFFFFFF
-#define SLC_SLC1_TXLINK_DSCR_BF0_S  0
-
-#define SLC_1_TXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xBC)
-/* SLC_SLC1_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC1_TXLINK_DSCR_BF1  0xFFFFFFFF
-#define SLC_SLC1_TXLINK_DSCR_BF1_M  ((SLC_SLC1_TXLINK_DSCR_BF1_V)<<(SLC_SLC1_TXLINK_DSCR_BF1_S))
-#define SLC_SLC1_TXLINK_DSCR_BF1_V  0xFFFFFFFF
-#define SLC_SLC1_TXLINK_DSCR_BF1_S  0
-
-#define SLC_1_RXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0xC0)
-/* SLC_SLC1_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC1_RXLINK_DSCR  0xFFFFFFFF
-#define SLC_SLC1_RXLINK_DSCR_M  ((SLC_SLC1_RXLINK_DSCR_V)<<(SLC_SLC1_RXLINK_DSCR_S))
-#define SLC_SLC1_RXLINK_DSCR_V  0xFFFFFFFF
-#define SLC_SLC1_RXLINK_DSCR_S  0
-
-#define SLC_1_RXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xC4)
-/* SLC_SLC1_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC1_RXLINK_DSCR_BF0  0xFFFFFFFF
-#define SLC_SLC1_RXLINK_DSCR_BF0_M  ((SLC_SLC1_RXLINK_DSCR_BF0_V)<<(SLC_SLC1_RXLINK_DSCR_BF0_S))
-#define SLC_SLC1_RXLINK_DSCR_BF0_V  0xFFFFFFFF
-#define SLC_SLC1_RXLINK_DSCR_BF0_S  0
-
-#define SLC_1_RXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xC8)
-/* SLC_SLC1_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC1_RXLINK_DSCR_BF1  0xFFFFFFFF
-#define SLC_SLC1_RXLINK_DSCR_BF1_M  ((SLC_SLC1_RXLINK_DSCR_BF1_V)<<(SLC_SLC1_RXLINK_DSCR_BF1_S))
-#define SLC_SLC1_RXLINK_DSCR_BF1_V  0xFFFFFFFF
-#define SLC_SLC1_RXLINK_DSCR_BF1_S  0
-
-#define SLC_0_TX_ERREOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0xCC)
-/* SLC_SLC0_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR  0xFFFFFFFF
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M  ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_ERR_EOF_DES_ADDR_S))
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S  0
-
-#define SLC_1_TX_ERREOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0xD0)
-/* SLC_SLC1_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC1_TX_ERR_EOF_DES_ADDR  0xFFFFFFFF
-#define SLC_SLC1_TX_ERR_EOF_DES_ADDR_M  ((SLC_SLC1_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC1_TX_ERR_EOF_DES_ADDR_S))
-#define SLC_SLC1_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC1_TX_ERR_EOF_DES_ADDR_S  0
-
-#define SLC_TOKEN_LAT_REG          (DR_REG_SLC_BASE + 0xD4)
-/* SLC_SLC1_TOKEN : RO ;bitpos:[27:16] ;default: 12'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN  0x00000FFF
-#define SLC_SLC1_TOKEN_M  ((SLC_SLC1_TOKEN_V)<<(SLC_SLC1_TOKEN_S))
-#define SLC_SLC1_TOKEN_V  0xFFF
-#define SLC_SLC1_TOKEN_S  16
-/* SLC_SLC0_TOKEN : RO ;bitpos:[11:0] ;default: 12'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN  0x00000FFF
-#define SLC_SLC0_TOKEN_M  ((SLC_SLC0_TOKEN_V)<<(SLC_SLC0_TOKEN_S))
-#define SLC_SLC0_TOKEN_V  0xFFF
-#define SLC_SLC0_TOKEN_S  0
-
-#define SLC_TX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0xD8)
-/* SLC_WR_RETRY_THRESHOLD : R/W ;bitpos:[10:0] ;default: 11'h80 ; */
-/*description: */
-#define SLC_WR_RETRY_THRESHOLD  0x000007FF
-#define SLC_WR_RETRY_THRESHOLD_M  ((SLC_WR_RETRY_THRESHOLD_V)<<(SLC_WR_RETRY_THRESHOLD_S))
-#define SLC_WR_RETRY_THRESHOLD_V  0x7FF
-#define SLC_WR_RETRY_THRESHOLD_S  0
-
-#define SLC_CMD_INFOR0_REG          (DR_REG_SLC_BASE + 0xDC)
-/* SLC_CMD_CONTENT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_CMD_CONTENT0  0xFFFFFFFF
-#define SLC_CMD_CONTENT0_M  ((SLC_CMD_CONTENT0_V)<<(SLC_CMD_CONTENT0_S))
-#define SLC_CMD_CONTENT0_V  0xFFFFFFFF
-#define SLC_CMD_CONTENT0_S  0
-
-#define SLC_CMD_INFOR1_REG          (DR_REG_SLC_BASE + 0xE0)
-/* SLC_CMD_CONTENT1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_CMD_CONTENT1  0xFFFFFFFF
-#define SLC_CMD_CONTENT1_M  ((SLC_CMD_CONTENT1_V)<<(SLC_CMD_CONTENT1_S))
-#define SLC_CMD_CONTENT1_V  0xFFFFFFFF
-#define SLC_CMD_CONTENT1_S  0
-
-#define SLC_0_LEN_CONF_REG          (DR_REG_SLC_BASE + 0xE4)
-/* SLC_SLC0_TX_NEW_PKT_IND : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_NEW_PKT_IND  (BIT(28))
-#define SLC_SLC0_TX_NEW_PKT_IND_M  (BIT(28))
-#define SLC_SLC0_TX_NEW_PKT_IND_V  0x1
-#define SLC_SLC0_TX_NEW_PKT_IND_S  28
-/* SLC_SLC0_RX_NEW_PKT_IND : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_NEW_PKT_IND  (BIT(27))
-#define SLC_SLC0_RX_NEW_PKT_IND_M  (BIT(27))
-#define SLC_SLC0_RX_NEW_PKT_IND_V  0x1
-#define SLC_SLC0_RX_NEW_PKT_IND_S  27
-/* SLC_SLC0_TX_GET_USED_DSCR : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_GET_USED_DSCR  (BIT(26))
-#define SLC_SLC0_TX_GET_USED_DSCR_M  (BIT(26))
-#define SLC_SLC0_TX_GET_USED_DSCR_V  0x1
-#define SLC_SLC0_TX_GET_USED_DSCR_S  26
-/* SLC_SLC0_RX_GET_USED_DSCR : WO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_GET_USED_DSCR  (BIT(25))
-#define SLC_SLC0_RX_GET_USED_DSCR_M  (BIT(25))
-#define SLC_SLC0_RX_GET_USED_DSCR_V  0x1
-#define SLC_SLC0_RX_GET_USED_DSCR_S  25
-/* SLC_SLC0_TX_PACKET_LOAD_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_PACKET_LOAD_EN  (BIT(24))
-#define SLC_SLC0_TX_PACKET_LOAD_EN_M  (BIT(24))
-#define SLC_SLC0_TX_PACKET_LOAD_EN_V  0x1
-#define SLC_SLC0_TX_PACKET_LOAD_EN_S  24
-/* SLC_SLC0_RX_PACKET_LOAD_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_PACKET_LOAD_EN  (BIT(23))
-#define SLC_SLC0_RX_PACKET_LOAD_EN_M  (BIT(23))
-#define SLC_SLC0_RX_PACKET_LOAD_EN_V  0x1
-#define SLC_SLC0_RX_PACKET_LOAD_EN_S  23
-/* SLC_SLC0_LEN_INC_MORE : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_LEN_INC_MORE  (BIT(22))
-#define SLC_SLC0_LEN_INC_MORE_M  (BIT(22))
-#define SLC_SLC0_LEN_INC_MORE_V  0x1
-#define SLC_SLC0_LEN_INC_MORE_S  22
-/* SLC_SLC0_LEN_INC : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_LEN_INC  (BIT(21))
-#define SLC_SLC0_LEN_INC_M  (BIT(21))
-#define SLC_SLC0_LEN_INC_V  0x1
-#define SLC_SLC0_LEN_INC_S  21
-/* SLC_SLC0_LEN_WR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_LEN_WR  (BIT(20))
-#define SLC_SLC0_LEN_WR_M  (BIT(20))
-#define SLC_SLC0_LEN_WR_V  0x1
-#define SLC_SLC0_LEN_WR_S  20
-/* SLC_SLC0_LEN_WDATA : WO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC0_LEN_WDATA  0x000FFFFF
-#define SLC_SLC0_LEN_WDATA_M  ((SLC_SLC0_LEN_WDATA_V)<<(SLC_SLC0_LEN_WDATA_S))
-#define SLC_SLC0_LEN_WDATA_V  0xFFFFF
-#define SLC_SLC0_LEN_WDATA_S  0
-
-#define SLC_0_LENGTH_REG          (DR_REG_SLC_BASE + 0xE8)
-/* SLC_SLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: */
-#define SLC_SLC0_LEN  0x000FFFFF
-#define SLC_SLC0_LEN_M  ((SLC_SLC0_LEN_V)<<(SLC_SLC0_LEN_S))
-#define SLC_SLC0_LEN_V  0xFFFFF
-#define SLC_SLC0_LEN_S  0
-
-#define SLC_0_TXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xEC)
-/* SLC_SLC0_TX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_H_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S  0
-
-#define SLC_0_TXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF0)
-/* SLC_SLC0_TX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_E_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S  0
-
-#define SLC_0_RXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xF4)
-/* SLC_SLC0_RX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_H_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S  0
-
-#define SLC_0_RXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF8)
-/* SLC_SLC0_RX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_E_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S  0
-
-#define SLC_0_TXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0xFC)
-/* SLC_SLC0_TX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_START_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S  0
-
-#define SLC_0_TXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x100)
-/* SLC_SLC0_TX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_END_DSCR_ADDR_S))
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S  0
-
-#define SLC_0_RXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0x104)
-/* SLC_SLC0_RX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_START_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S  0
-
-#define SLC_0_RXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x108)
-/* SLC_SLC0_RX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_END_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S  0
-
-#define SLC_SEQ_POSITION_REG          (DR_REG_SLC_BASE + 0x114)
-/* SLC_SLC1_SEQ_POSITION : R/W ;bitpos:[15:8] ;default: 8'h5 ; */
-/*description: */
-#define SLC_SLC1_SEQ_POSITION  0x000000FF
-#define SLC_SLC1_SEQ_POSITION_M  ((SLC_SLC1_SEQ_POSITION_V)<<(SLC_SLC1_SEQ_POSITION_S))
-#define SLC_SLC1_SEQ_POSITION_V  0xFF
-#define SLC_SLC1_SEQ_POSITION_S  8
-/* SLC_SLC0_SEQ_POSITION : R/W ;bitpos:[7:0] ;default: 8'h9 ; */
-/*description: */
-#define SLC_SLC0_SEQ_POSITION  0x000000FF
-#define SLC_SLC0_SEQ_POSITION_M  ((SLC_SLC0_SEQ_POSITION_V)<<(SLC_SLC0_SEQ_POSITION_S))
-#define SLC_SLC0_SEQ_POSITION_V  0xFF
-#define SLC_SLC0_SEQ_POSITION_S  0
-
-#define SLC_0_DSCR_REC_CONF_REG          (DR_REG_SLC_BASE + 0x118)
-/* SLC_SLC0_RX_DSCR_REC_LIM : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_REC_LIM  0x000003FF
-#define SLC_SLC0_RX_DSCR_REC_LIM_M  ((SLC_SLC0_RX_DSCR_REC_LIM_V)<<(SLC_SLC0_RX_DSCR_REC_LIM_S))
-#define SLC_SLC0_RX_DSCR_REC_LIM_V  0x3FF
-#define SLC_SLC0_RX_DSCR_REC_LIM_S  0
-
-#define SLC_SDIO_CRC_ST0_REG          (DR_REG_SLC_BASE + 0x11C)
-/* SLC_DAT3_CRC_ERR_CNT : RO ;bitpos:[31:24] ;default: 8'h0 ; */
-/*description: */
-#define SLC_DAT3_CRC_ERR_CNT  0x000000FF
-#define SLC_DAT3_CRC_ERR_CNT_M  ((SLC_DAT3_CRC_ERR_CNT_V)<<(SLC_DAT3_CRC_ERR_CNT_S))
-#define SLC_DAT3_CRC_ERR_CNT_V  0xFF
-#define SLC_DAT3_CRC_ERR_CNT_S  24
-/* SLC_DAT2_CRC_ERR_CNT : RO ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: */
-#define SLC_DAT2_CRC_ERR_CNT  0x000000FF
-#define SLC_DAT2_CRC_ERR_CNT_M  ((SLC_DAT2_CRC_ERR_CNT_V)<<(SLC_DAT2_CRC_ERR_CNT_S))
-#define SLC_DAT2_CRC_ERR_CNT_V  0xFF
-#define SLC_DAT2_CRC_ERR_CNT_S  16
-/* SLC_DAT1_CRC_ERR_CNT : RO ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: */
-#define SLC_DAT1_CRC_ERR_CNT  0x000000FF
-#define SLC_DAT1_CRC_ERR_CNT_M  ((SLC_DAT1_CRC_ERR_CNT_V)<<(SLC_DAT1_CRC_ERR_CNT_S))
-#define SLC_DAT1_CRC_ERR_CNT_V  0xFF
-#define SLC_DAT1_CRC_ERR_CNT_S  8
-/* SLC_DAT0_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define SLC_DAT0_CRC_ERR_CNT  0x000000FF
-#define SLC_DAT0_CRC_ERR_CNT_M  ((SLC_DAT0_CRC_ERR_CNT_V)<<(SLC_DAT0_CRC_ERR_CNT_S))
-#define SLC_DAT0_CRC_ERR_CNT_V  0xFF
-#define SLC_DAT0_CRC_ERR_CNT_S  0
-
-#define SLC_SDIO_CRC_ST1_REG          (DR_REG_SLC_BASE + 0x120)
-/* SLC_ERR_CNT_CLR : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define SLC_ERR_CNT_CLR  (BIT(31))
-#define SLC_ERR_CNT_CLR_M  (BIT(31))
-#define SLC_ERR_CNT_CLR_V  0x1
-#define SLC_ERR_CNT_CLR_S  31
-/* SLC_CMD_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define SLC_CMD_CRC_ERR_CNT  0x000000FF
-#define SLC_CMD_CRC_ERR_CNT_M  ((SLC_CMD_CRC_ERR_CNT_V)<<(SLC_CMD_CRC_ERR_CNT_S))
-#define SLC_CMD_CRC_ERR_CNT_V  0xFF
-#define SLC_CMD_CRC_ERR_CNT_S  0
-
-#define SLC_0_EOF_START_DES_REG          (DR_REG_SLC_BASE + 0x124)
-/* SLC_SLC0_EOF_START_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_EOF_START_DES_ADDR  0xFFFFFFFF
-#define SLC_SLC0_EOF_START_DES_ADDR_M  ((SLC_SLC0_EOF_START_DES_ADDR_V)<<(SLC_SLC0_EOF_START_DES_ADDR_S))
-#define SLC_SLC0_EOF_START_DES_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_EOF_START_DES_ADDR_S  0
-
-#define SLC_0_PUSH_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x128)
-/* SLC_SLC0_RX_PUSH_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR_M  ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V)<<(SLC_SLC0_RX_PUSH_DSCR_ADDR_S))
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_PUSH_DSCR_ADDR_S  0
-
-#define SLC_0_DONE_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x12C)
-/* SLC_SLC0_RX_DONE_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_RX_DONE_DSCR_ADDR_M  ((SLC_SLC0_RX_DONE_DSCR_ADDR_V)<<(SLC_SLC0_RX_DONE_DSCR_ADDR_S))
-#define SLC_SLC0_RX_DONE_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_RX_DONE_DSCR_ADDR_S  0
-
-#define SLC_0_SUB_START_DES_REG          (DR_REG_SLC_BASE + 0x130)
-/* SLC_SLC0_SUB_PAC_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR  0xFFFFFFFF
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M  ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V)<<(SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S))
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V  0xFFFFFFFF
-#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S  0
-
-#define SLC_0_DSCR_CNT_REG          (DR_REG_SLC_BASE + 0x134)
-/* SLC_SLC0_RX_GET_EOF_OCC : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_GET_EOF_OCC  (BIT(16))
-#define SLC_SLC0_RX_GET_EOF_OCC_M  (BIT(16))
-#define SLC_SLC0_RX_GET_EOF_OCC_V  0x1
-#define SLC_SLC0_RX_GET_EOF_OCC_S  16
-/* SLC_SLC0_RX_DSCR_CNT_LAT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_CNT_LAT  0x000003FF
-#define SLC_SLC0_RX_DSCR_CNT_LAT_M  ((SLC_SLC0_RX_DSCR_CNT_LAT_V)<<(SLC_SLC0_RX_DSCR_CNT_LAT_S))
-#define SLC_SLC0_RX_DSCR_CNT_LAT_V  0x3FF
-#define SLC_SLC0_RX_DSCR_CNT_LAT_S  0
-
-#define SLC_0_LEN_LIM_CONF_REG          (DR_REG_SLC_BASE + 0x138)
-/* SLC_SLC0_LEN_LIM : R/W ;bitpos:[19:0] ;default: 20'h5400 ; */
-/*description: */
-#define SLC_SLC0_LEN_LIM  0x000FFFFF
-#define SLC_SLC0_LEN_LIM_M  ((SLC_SLC0_LEN_LIM_V)<<(SLC_SLC0_LEN_LIM_S))
-#define SLC_SLC0_LEN_LIM_V  0xFFFFF
-#define SLC_SLC0_LEN_LIM_S  0
-
-#define SLC_0INT_ST1_REG          (DR_REG_SLC_BASE + 0x13C)
-/* SLC_SLC0_RX_QUICK_EOF_INT_ST1 : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S  26
-/* SLC_CMD_DTC_INT_ST1 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_ST1  (BIT(25))
-#define SLC_CMD_DTC_INT_ST1_M  (BIT(25))
-#define SLC_CMD_DTC_INT_ST1_V  0x1
-#define SLC_CMD_DTC_INT_ST1_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ST1_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ST1_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S  19
-/* SLC_SLC0_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_ST1  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST1_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ST1_V  0x1
-#define SLC_SLC0_TOHOST_INT_ST1_S  18
-/* SLC_SLC0_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_ST1  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST1_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ST1_V  0x1
-#define SLC_SLC0_RX_EOF_INT_ST1_S  17
-/* SLC_SLC0_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_ST1  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST1_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ST1_V  0x1
-#define SLC_SLC0_RX_DONE_INT_ST1_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ST1_S  15
-/* SLC_SLC0_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_ST1  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST1_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ST1_V  0x1
-#define SLC_SLC0_TX_DONE_INT_ST1_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S  12
-/* SLC_SLC0_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_ST1  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST1_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ST1_V  0x1
-#define SLC_SLC0_TX_OVF_INT_ST1_S  11
-/* SLC_SLC0_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_ST1  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST1_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ST1_V  0x1
-#define SLC_SLC0_RX_UDF_INT_ST1_S  10
-/* SLC_SLC0_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_ST1  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST1_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ST1_V  0x1
-#define SLC_SLC0_TX_START_INT_ST1_S  9
-/* SLC_SLC0_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_ST1  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST1_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ST1_V  0x1
-#define SLC_SLC0_RX_START_INT_ST1_S  8
-/* SLC_FRHOST_BIT7_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_ST1  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST1_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT7_INT_ST1_S  7
-/* SLC_FRHOST_BIT6_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_ST1  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST1_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT6_INT_ST1_S  6
-/* SLC_FRHOST_BIT5_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_ST1  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST1_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT5_INT_ST1_S  5
-/* SLC_FRHOST_BIT4_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_ST1  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST1_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT4_INT_ST1_S  4
-/* SLC_FRHOST_BIT3_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_ST1  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST1_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT3_INT_ST1_S  3
-/* SLC_FRHOST_BIT2_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_ST1  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST1_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT2_INT_ST1_S  2
-/* SLC_FRHOST_BIT1_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_ST1  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST1_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT1_INT_ST1_S  1
-/* SLC_FRHOST_BIT0_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_ST1  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST1_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT0_INT_ST1_S  0
-
-#define SLC_0INT_ENA1_REG          (DR_REG_SLC_BASE + 0x140)
-/* SLC_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M  (BIT(26))
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S  26
-/* SLC_CMD_DTC_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SLC_CMD_DTC_INT_ENA1  (BIT(25))
-#define SLC_CMD_DTC_INT_ENA1_M  (BIT(25))
-#define SLC_CMD_DTC_INT_ENA1_V  0x1
-#define SLC_CMD_DTC_INT_ENA1_S  25
-/* SLC_SLC0_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M  (BIT(24))
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S  24
-/* SLC_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M  (BIT(23))
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V  0x1
-#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S  23
-/* SLC_SLC0_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M  (BIT(22))
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V  0x1
-#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S  22
-/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M  (BIT(21))
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S  21
-/* SLC_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M  (BIT(20))
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S  20
-/* SLC_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M  (BIT(19))
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S  19
-/* SLC_SLC0_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOHOST_INT_ENA1  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA1_M  (BIT(18))
-#define SLC_SLC0_TOHOST_INT_ENA1_V  0x1
-#define SLC_SLC0_TOHOST_INT_ENA1_S  18
-/* SLC_SLC0_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_EOF_INT_ENA1  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA1_M  (BIT(17))
-#define SLC_SLC0_RX_EOF_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_EOF_INT_ENA1_S  17
-/* SLC_SLC0_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_DONE_INT_ENA1  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA1_M  (BIT(16))
-#define SLC_SLC0_RX_DONE_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_DONE_INT_ENA1_S  16
-/* SLC_SLC0_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M  (BIT(15))
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S  15
-/* SLC_SLC0_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_DONE_INT_ENA1  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA1_M  (BIT(14))
-#define SLC_SLC0_TX_DONE_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_DONE_INT_ENA1_S  14
-/* SLC_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M  (BIT(13))
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x1
-#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S  13
-/* SLC_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M  (BIT(12))
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x1
-#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S  12
-/* SLC_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_OVF_INT_ENA1  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA1_M  (BIT(11))
-#define SLC_SLC0_TX_OVF_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_OVF_INT_ENA1_S  11
-/* SLC_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_UDF_INT_ENA1  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA1_M  (BIT(10))
-#define SLC_SLC0_RX_UDF_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_UDF_INT_ENA1_S  10
-/* SLC_SLC0_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_TX_START_INT_ENA1  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA1_M  (BIT(9))
-#define SLC_SLC0_TX_START_INT_ENA1_V  0x1
-#define SLC_SLC0_TX_START_INT_ENA1_S  9
-/* SLC_SLC0_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC0_RX_START_INT_ENA1  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA1_M  (BIT(8))
-#define SLC_SLC0_RX_START_INT_ENA1_V  0x1
-#define SLC_SLC0_RX_START_INT_ENA1_S  8
-/* SLC_FRHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT7_INT_ENA1  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA1_M  (BIT(7))
-#define SLC_FRHOST_BIT7_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT7_INT_ENA1_S  7
-/* SLC_FRHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT6_INT_ENA1  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA1_M  (BIT(6))
-#define SLC_FRHOST_BIT6_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT6_INT_ENA1_S  6
-/* SLC_FRHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT5_INT_ENA1  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA1_M  (BIT(5))
-#define SLC_FRHOST_BIT5_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT5_INT_ENA1_S  5
-/* SLC_FRHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT4_INT_ENA1  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA1_M  (BIT(4))
-#define SLC_FRHOST_BIT4_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT4_INT_ENA1_S  4
-/* SLC_FRHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT3_INT_ENA1  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA1_M  (BIT(3))
-#define SLC_FRHOST_BIT3_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT3_INT_ENA1_S  3
-/* SLC_FRHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT2_INT_ENA1  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA1_M  (BIT(2))
-#define SLC_FRHOST_BIT2_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT2_INT_ENA1_S  2
-/* SLC_FRHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT1_INT_ENA1  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA1_M  (BIT(1))
-#define SLC_FRHOST_BIT1_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT1_INT_ENA1_S  1
-/* SLC_FRHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT0_INT_ENA1  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA1_M  (BIT(0))
-#define SLC_FRHOST_BIT0_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT0_INT_ENA1_S  0
-
-#define SLC_1INT_ST1_REG          (DR_REG_SLC_BASE + 0x144)
-/* SLC_SLC1_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_ERR_EOF_INT_ST1  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_ST1_M  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_ST1_V  0x1
-#define SLC_SLC1_TX_ERR_EOF_INT_ST1_S  24
-/* SLC_SLC1_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_WR_RETRY_DONE_INT_ST1  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_ST1_M  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_ST1_V  0x1
-#define SLC_SLC1_WR_RETRY_DONE_INT_ST1_S  23
-/* SLC_SLC1_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_HOST_RD_ACK_INT_ST1  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_ST1_M  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_ST1_V  0x1
-#define SLC_SLC1_HOST_RD_ACK_INT_ST1_S  22
-/* SLC_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_M  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_V  0x1
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_S  21
-/* SLC_SLC1_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DSCR_ERR_INT_ST1  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_ST1_M  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_ST1_V  0x1
-#define SLC_SLC1_RX_DSCR_ERR_INT_ST1_S  20
-/* SLC_SLC1_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_ERR_INT_ST1  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_ST1_M  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_ST1_V  0x1
-#define SLC_SLC1_TX_DSCR_ERR_INT_ST1_S  19
-/* SLC_SLC1_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOHOST_INT_ST1  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_ST1_M  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_ST1_V  0x1
-#define SLC_SLC1_TOHOST_INT_ST1_S  18
-/* SLC_SLC1_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_EOF_INT_ST1  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_ST1_M  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_ST1_V  0x1
-#define SLC_SLC1_RX_EOF_INT_ST1_S  17
-/* SLC_SLC1_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DONE_INT_ST1  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_ST1_M  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_ST1_V  0x1
-#define SLC_SLC1_RX_DONE_INT_ST1_S  16
-/* SLC_SLC1_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_SUC_EOF_INT_ST1  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_ST1_M  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_ST1_V  0x1
-#define SLC_SLC1_TX_SUC_EOF_INT_ST1_S  15
-/* SLC_SLC1_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DONE_INT_ST1  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_ST1_M  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_ST1_V  0x1
-#define SLC_SLC1_TX_DONE_INT_ST1_S  14
-/* SLC_SLC1_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_1TO0_INT_ST1  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_ST1_M  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_ST1_V  0x1
-#define SLC_SLC1_TOKEN1_1TO0_INT_ST1_S  13
-/* SLC_SLC1_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_1TO0_INT_ST1  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_ST1_M  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_ST1_V  0x1
-#define SLC_SLC1_TOKEN0_1TO0_INT_ST1_S  12
-/* SLC_SLC1_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_OVF_INT_ST1  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_ST1_M  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_ST1_V  0x1
-#define SLC_SLC1_TX_OVF_INT_ST1_S  11
-/* SLC_SLC1_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_UDF_INT_ST1  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_ST1_M  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_ST1_V  0x1
-#define SLC_SLC1_RX_UDF_INT_ST1_S  10
-/* SLC_SLC1_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_START_INT_ST1  (BIT(9))
-#define SLC_SLC1_TX_START_INT_ST1_M  (BIT(9))
-#define SLC_SLC1_TX_START_INT_ST1_V  0x1
-#define SLC_SLC1_TX_START_INT_ST1_S  9
-/* SLC_SLC1_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_START_INT_ST1  (BIT(8))
-#define SLC_SLC1_RX_START_INT_ST1_M  (BIT(8))
-#define SLC_SLC1_RX_START_INT_ST1_V  0x1
-#define SLC_SLC1_RX_START_INT_ST1_S  8
-/* SLC_FRHOST_BIT15_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT15_INT_ST1  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_ST1_M  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT15_INT_ST1_S  7
-/* SLC_FRHOST_BIT14_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT14_INT_ST1  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_ST1_M  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT14_INT_ST1_S  6
-/* SLC_FRHOST_BIT13_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT13_INT_ST1  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_ST1_M  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT13_INT_ST1_S  5
-/* SLC_FRHOST_BIT12_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT12_INT_ST1  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_ST1_M  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT12_INT_ST1_S  4
-/* SLC_FRHOST_BIT11_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT11_INT_ST1  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_ST1_M  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT11_INT_ST1_S  3
-/* SLC_FRHOST_BIT10_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT10_INT_ST1  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_ST1_M  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT10_INT_ST1_S  2
-/* SLC_FRHOST_BIT9_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT9_INT_ST1  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_ST1_M  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT9_INT_ST1_S  1
-/* SLC_FRHOST_BIT8_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT8_INT_ST1  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_ST1_M  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_ST1_V  0x1
-#define SLC_FRHOST_BIT8_INT_ST1_S  0
-
-#define SLC_1INT_ENA1_REG          (DR_REG_SLC_BASE + 0x148)
-/* SLC_SLC1_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_ERR_EOF_INT_ENA1  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_ENA1_M  (BIT(24))
-#define SLC_SLC1_TX_ERR_EOF_INT_ENA1_V  0x1
-#define SLC_SLC1_TX_ERR_EOF_INT_ENA1_S  24
-/* SLC_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_M  (BIT(23))
-#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_V  0x1
-#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_S  23
-/* SLC_SLC1_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_HOST_RD_ACK_INT_ENA1  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_ENA1_M  (BIT(22))
-#define SLC_SLC1_HOST_RD_ACK_INT_ENA1_V  0x1
-#define SLC_SLC1_HOST_RD_ACK_INT_ENA1_S  22
-/* SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_M  (BIT(21))
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_V  0x1
-#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_S  21
-/* SLC_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_M  (BIT(20))
-#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_V  0x1
-#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_S  20
-/* SLC_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_M  (BIT(19))
-#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_V  0x1
-#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_S  19
-/* SLC_SLC1_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOHOST_INT_ENA1  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_ENA1_M  (BIT(18))
-#define SLC_SLC1_TOHOST_INT_ENA1_V  0x1
-#define SLC_SLC1_TOHOST_INT_ENA1_S  18
-/* SLC_SLC1_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_EOF_INT_ENA1  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_ENA1_M  (BIT(17))
-#define SLC_SLC1_RX_EOF_INT_ENA1_V  0x1
-#define SLC_SLC1_RX_EOF_INT_ENA1_S  17
-/* SLC_SLC1_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_DONE_INT_ENA1  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_ENA1_M  (BIT(16))
-#define SLC_SLC1_RX_DONE_INT_ENA1_V  0x1
-#define SLC_SLC1_RX_DONE_INT_ENA1_S  16
-/* SLC_SLC1_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_SUC_EOF_INT_ENA1  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_ENA1_M  (BIT(15))
-#define SLC_SLC1_TX_SUC_EOF_INT_ENA1_V  0x1
-#define SLC_SLC1_TX_SUC_EOF_INT_ENA1_S  15
-/* SLC_SLC1_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_DONE_INT_ENA1  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_ENA1_M  (BIT(14))
-#define SLC_SLC1_TX_DONE_INT_ENA1_V  0x1
-#define SLC_SLC1_TX_DONE_INT_ENA1_S  14
-/* SLC_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_M  (BIT(13))
-#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_V  0x1
-#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_S  13
-/* SLC_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_M  (BIT(12))
-#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_V  0x1
-#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_S  12
-/* SLC_SLC1_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_OVF_INT_ENA1  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_ENA1_M  (BIT(11))
-#define SLC_SLC1_TX_OVF_INT_ENA1_V  0x1
-#define SLC_SLC1_TX_OVF_INT_ENA1_S  11
-/* SLC_SLC1_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_UDF_INT_ENA1  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_ENA1_M  (BIT(10))
-#define SLC_SLC1_RX_UDF_INT_ENA1_V  0x1
-#define SLC_SLC1_RX_UDF_INT_ENA1_S  10
-/* SLC_SLC1_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_TX_START_INT_ENA1  (BIT(9))
-#define SLC_SLC1_TX_START_INT_ENA1_M  (BIT(9))
-#define SLC_SLC1_TX_START_INT_ENA1_V  0x1
-#define SLC_SLC1_TX_START_INT_ENA1_S  9
-/* SLC_SLC1_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SLC_SLC1_RX_START_INT_ENA1  (BIT(8))
-#define SLC_SLC1_RX_START_INT_ENA1_M  (BIT(8))
-#define SLC_SLC1_RX_START_INT_ENA1_V  0x1
-#define SLC_SLC1_RX_START_INT_ENA1_S  8
-/* SLC_FRHOST_BIT15_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT15_INT_ENA1  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_ENA1_M  (BIT(7))
-#define SLC_FRHOST_BIT15_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT15_INT_ENA1_S  7
-/* SLC_FRHOST_BIT14_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT14_INT_ENA1  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_ENA1_M  (BIT(6))
-#define SLC_FRHOST_BIT14_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT14_INT_ENA1_S  6
-/* SLC_FRHOST_BIT13_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT13_INT_ENA1  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_ENA1_M  (BIT(5))
-#define SLC_FRHOST_BIT13_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT13_INT_ENA1_S  5
-/* SLC_FRHOST_BIT12_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT12_INT_ENA1  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_ENA1_M  (BIT(4))
-#define SLC_FRHOST_BIT12_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT12_INT_ENA1_S  4
-/* SLC_FRHOST_BIT11_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT11_INT_ENA1  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_ENA1_M  (BIT(3))
-#define SLC_FRHOST_BIT11_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT11_INT_ENA1_S  3
-/* SLC_FRHOST_BIT10_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT10_INT_ENA1  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_ENA1_M  (BIT(2))
-#define SLC_FRHOST_BIT10_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT10_INT_ENA1_S  2
-/* SLC_FRHOST_BIT9_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT9_INT_ENA1  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_ENA1_M  (BIT(1))
-#define SLC_FRHOST_BIT9_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT9_INT_ENA1_S  1
-/* SLC_FRHOST_BIT8_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SLC_FRHOST_BIT8_INT_ENA1  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_ENA1_M  (BIT(0))
-#define SLC_FRHOST_BIT8_INT_ENA1_V  0x1
-#define SLC_FRHOST_BIT8_INT_ENA1_S  0
-
-#define SLC_DATE_REG          (DR_REG_SLC_BASE + 0x1F8)
-/* SLC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022500 ; */
-/*description: */
-#define SLC_DATE  0xFFFFFFFF
-#define SLC_DATE_M  ((SLC_DATE_V)<<(SLC_DATE_S))
-#define SLC_DATE_V  0xFFFFFFFF
-#define SLC_DATE_S  0
-
-#define SLC_ID_REG          (DR_REG_SLC_BASE + 0x1FC)
-/* SLC_ID : R/W ;bitpos:[31:0] ;default: 32'h0100 ; */
-/*description: */
-#define SLC_ID  0xFFFFFFFF
-#define SLC_ID_M  ((SLC_ID_V)<<(SLC_ID_S))
-#define SLC_ID_V  0xFFFFFFFF
-#define SLC_ID_S  0
-
-
-
-
-#endif /*_SOC_SLC_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/slc_struct.h b/tools/sdk/include/soc/soc/slc_struct.h
deleted file mode 100644
index 55506a5b436..00000000000
--- a/tools/sdk/include/soc/soc/slc_struct.h
+++ /dev/null
@@ -1,860 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SLC_STRUCT_H_
-#define _SOC_SLC_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t slc0_tx_rst:         1;
-            uint32_t slc0_rx_rst:         1;
-            uint32_t ahbm_fifo_rst:       1;
-            uint32_t ahbm_rst:            1;
-            uint32_t slc0_tx_loop_test:   1;
-            uint32_t slc0_rx_loop_test:   1;
-            uint32_t slc0_rx_auto_wrback: 1;
-            uint32_t slc0_rx_no_restart_clr: 1;
-            uint32_t slc0_rxdscr_burst_en: 1;
-            uint32_t slc0_rxdata_burst_en: 1;
-            uint32_t slc0_rxlink_auto_ret: 1;
-            uint32_t slc0_txlink_auto_ret: 1;
-            uint32_t slc0_txdscr_burst_en: 1;
-            uint32_t slc0_txdata_burst_en: 1;
-            uint32_t slc0_token_auto_clr: 1;
-            uint32_t slc0_token_sel:      1;
-            uint32_t slc1_tx_rst:         1;
-            uint32_t slc1_rx_rst:         1;
-            uint32_t slc0_wr_retry_mask_en: 1;
-            uint32_t slc1_wr_retry_mask_en: 1;
-            uint32_t slc1_tx_loop_test:   1;
-            uint32_t slc1_rx_loop_test:   1;
-            uint32_t slc1_rx_auto_wrback: 1;
-            uint32_t slc1_rx_no_restart_clr: 1;
-            uint32_t slc1_rxdscr_burst_en: 1;
-            uint32_t slc1_rxdata_burst_en: 1;
-            uint32_t slc1_rxlink_auto_ret: 1;
-            uint32_t slc1_txlink_auto_ret: 1;
-            uint32_t slc1_txdscr_burst_en: 1;
-            uint32_t slc1_txdata_burst_en: 1;
-            uint32_t slc1_token_auto_clr: 1;
-            uint32_t slc1_token_sel:      1;
-        };
-        uint32_t val;
-    } conf0;
-    union {
-        struct {
-            uint32_t frhost_bit0:             1;
-            uint32_t frhost_bit1:             1;
-            uint32_t frhost_bit2:             1;
-            uint32_t frhost_bit3:             1;
-            uint32_t frhost_bit4:             1;
-            uint32_t frhost_bit5:             1;
-            uint32_t frhost_bit6:             1;
-            uint32_t frhost_bit7:             1;
-            uint32_t rx_start:                1;
-            uint32_t tx_start:                1;
-            uint32_t rx_udf:                  1;
-            uint32_t tx_ovf:                  1;
-            uint32_t token0_1to0:             1;
-            uint32_t token1_1to0:             1;
-            uint32_t tx_done:                 1;
-            uint32_t tx_suc_eof:              1;
-            uint32_t rx_done:                 1;
-            uint32_t rx_eof:                  1;
-            uint32_t tohost:                  1;
-            uint32_t tx_dscr_err:             1;
-            uint32_t rx_dscr_err:             1;
-            uint32_t tx_dscr_empty:           1;
-            uint32_t host_rd_ack:             1;
-            uint32_t wr_retry_done:           1;
-            uint32_t tx_err_eof:              1;
-            uint32_t cmd_dtc:                 1;
-            uint32_t rx_quick_eof:            1;
-            uint32_t reserved27:              5;
-        };
-        uint32_t val;
-    } slc0_int_raw;
-    union {
-        struct {
-            uint32_t frhost_bit0:            1;
-            uint32_t frhost_bit1:            1;
-            uint32_t frhost_bit2:            1;
-            uint32_t frhost_bit3:            1;
-            uint32_t frhost_bit4:            1;
-            uint32_t frhost_bit5:            1;
-            uint32_t frhost_bit6:            1;
-            uint32_t frhost_bit7:            1;
-            uint32_t rx_start:               1;
-            uint32_t tx_start:               1;
-            uint32_t rx_udf:                 1;
-            uint32_t tx_ovf:                 1;
-            uint32_t token0_1to0:            1;
-            uint32_t token1_1to0:            1;
-            uint32_t tx_done:                1;
-            uint32_t tx_suc_eof:             1;
-            uint32_t rx_done:                1;
-            uint32_t rx_eof:                 1;
-            uint32_t tohost:                 1;
-            uint32_t tx_dscr_err:            1;
-            uint32_t rx_dscr_err:            1;
-            uint32_t tx_dscr_empty:          1;
-            uint32_t host_rd_ack:            1;
-            uint32_t wr_retry_done:          1;
-            uint32_t tx_err_eof:             1;
-            uint32_t cmd_dtc:                1;
-            uint32_t rx_quick_eof:           1;
-            uint32_t reserved27:             5;
-        };
-        uint32_t val;
-    } slc0_int_st;
-    union {
-        struct {
-            uint32_t frhost_bit0:             1;
-            uint32_t frhost_bit1:             1;
-            uint32_t frhost_bit2:             1;
-            uint32_t frhost_bit3:             1;
-            uint32_t frhost_bit4:             1;
-            uint32_t frhost_bit5:             1;
-            uint32_t frhost_bit6:             1;
-            uint32_t frhost_bit7:             1;
-            uint32_t rx_start:                1;
-            uint32_t tx_start:                1;
-            uint32_t rx_udf:                  1;
-            uint32_t tx_ovf:                  1;
-            uint32_t token0_1to0:             1;
-            uint32_t token1_1to0:             1;
-            uint32_t tx_done:                 1;
-            uint32_t tx_suc_eof:              1;
-            uint32_t rx_done:                 1;
-            uint32_t rx_eof:                  1;
-            uint32_t tohost:                  1;
-            uint32_t tx_dscr_err:             1;
-            uint32_t rx_dscr_err:             1;
-            uint32_t tx_dscr_empty:           1;
-            uint32_t host_rd_ack:             1;
-            uint32_t wr_retry_done:           1;
-            uint32_t tx_err_eof:              1;
-            uint32_t cmd_dtc:                 1;
-            uint32_t rx_quick_eof:            1;
-            uint32_t reserved27:              5;
-        };
-        uint32_t val;
-    } slc0_int_ena;
-    union {
-        struct {
-            uint32_t frhost_bit0:             1;
-            uint32_t frhost_bit1:             1;
-            uint32_t frhost_bit2:             1;
-            uint32_t frhost_bit3:             1;
-            uint32_t frhost_bit4:             1;
-            uint32_t frhost_bit5:             1;
-            uint32_t frhost_bit6:             1;
-            uint32_t frhost_bit7:             1;
-            uint32_t rx_start:                1;
-            uint32_t tx_start:                1;
-            uint32_t rx_udf:                  1;
-            uint32_t tx_ovf:                  1;
-            uint32_t token0_1to0:             1;
-            uint32_t token1_1to0:             1;
-            uint32_t tx_done:                 1;
-            uint32_t tx_suc_eof:              1;
-            uint32_t rx_done:                 1;
-            uint32_t rx_eof:                  1;
-            uint32_t tohost:                  1;
-            uint32_t tx_dscr_err:             1;
-            uint32_t rx_dscr_err:             1;
-            uint32_t tx_dscr_empty:           1;
-            uint32_t host_rd_ack:             1;
-            uint32_t wr_retry_done:           1;
-            uint32_t tx_err_eof:              1;
-            uint32_t cmd_dtc:                 1;
-            uint32_t rx_quick_eof:            1;
-            uint32_t reserved27:              5;
-        };
-        uint32_t val;
-    } slc0_int_clr;
-    union {
-        struct {
-            uint32_t frhost_bit8:             1;
-            uint32_t frhost_bit9:             1;
-            uint32_t frhost_bit10:            1;
-            uint32_t frhost_bit11:            1;
-            uint32_t frhost_bit12:            1;
-            uint32_t frhost_bit13:            1;
-            uint32_t frhost_bit14:            1;
-            uint32_t frhost_bit15:            1;
-            uint32_t rx_start:                1;
-            uint32_t tx_start:                1;
-            uint32_t rx_udf:                  1;
-            uint32_t tx_ovf:                  1;
-            uint32_t token0_1to0:             1;
-            uint32_t token1_1to0:             1;
-            uint32_t tx_done:                 1;
-            uint32_t tx_suc_eof:              1;
-            uint32_t rx_done:                 1;
-            uint32_t rx_eof:                  1;
-            uint32_t tohost:                  1;
-            uint32_t tx_dscr_err:             1;
-            uint32_t rx_dscr_err:             1;
-            uint32_t tx_dscr_empty:           1;
-            uint32_t host_rd_ack:             1;
-            uint32_t wr_retry_done:           1;
-            uint32_t tx_err_eof:              1;
-            uint32_t reserved25:              7;
-        };
-        uint32_t val;
-    } slc1_int_raw;
-    union {
-        struct {
-            uint32_t frhost_bit8:            1;
-            uint32_t frhost_bit9:            1;
-            uint32_t frhost_bit10:           1;
-            uint32_t frhost_bit11:           1;
-            uint32_t frhost_bit12:           1;
-            uint32_t frhost_bit13:           1;
-            uint32_t frhost_bit14:           1;
-            uint32_t frhost_bit15:           1;
-            uint32_t rx_start:               1;
-            uint32_t tx_start:               1;
-            uint32_t rx_udf:                 1;
-            uint32_t tx_ovf:                 1;
-            uint32_t token0_1to0:            1;
-            uint32_t token1_1to0:            1;
-            uint32_t tx_done:                1;
-            uint32_t tx_suc_eof:             1;
-            uint32_t rx_done:                1;
-            uint32_t rx_eof:                 1;
-            uint32_t tohost:                 1;
-            uint32_t tx_dscr_err:            1;
-            uint32_t rx_dscr_err:            1;
-            uint32_t tx_dscr_empty:          1;
-            uint32_t host_rd_ack:            1;
-            uint32_t wr_retry_done:          1;
-            uint32_t tx_err_eof:             1;
-            uint32_t reserved25:             7;
-        };
-        uint32_t val;
-    } slc1_int_st;
-    union {
-        struct {
-            uint32_t frhost_bit8:             1;
-            uint32_t frhost_bit9:             1;
-            uint32_t frhost_bit10:            1;
-            uint32_t frhost_bit11:            1;
-            uint32_t frhost_bit12:            1;
-            uint32_t frhost_bit13:            1;
-            uint32_t frhost_bit14:            1;
-            uint32_t frhost_bit15:            1;
-            uint32_t rx_start:                1;
-            uint32_t tx_start:                1;
-            uint32_t rx_udf:                  1;
-            uint32_t tx_ovf:                  1;
-            uint32_t token0_1to0:             1;
-            uint32_t token1_1to0:             1;
-            uint32_t tx_done:                 1;
-            uint32_t tx_suc_eof:              1;
-            uint32_t rx_done:                 1;
-            uint32_t rx_eof:                  1;
-            uint32_t tohost:                  1;
-            uint32_t tx_dscr_err:             1;
-            uint32_t rx_dscr_err:             1;
-            uint32_t tx_dscr_empty:           1;
-            uint32_t host_rd_ack:             1;
-            uint32_t wr_retry_done:           1;
-            uint32_t tx_err_eof:              1;
-            uint32_t reserved25:              7;
-        };
-        uint32_t val;
-    } slc1_int_ena;
-    union {
-        struct {
-            uint32_t frhost_bit8:             1;
-            uint32_t frhost_bit9:             1;
-            uint32_t frhost_bit10:            1;
-            uint32_t frhost_bit11:            1;
-            uint32_t frhost_bit12:            1;
-            uint32_t frhost_bit13:            1;
-            uint32_t frhost_bit14:            1;
-            uint32_t frhost_bit15:            1;
-            uint32_t rx_start:                1;
-            uint32_t tx_start:                1;
-            uint32_t rx_udf:                  1;
-            uint32_t tx_ovf:                  1;
-            uint32_t token0_1to0:             1;
-            uint32_t token1_1to0:             1;
-            uint32_t tx_done:                 1;
-            uint32_t tx_suc_eof:              1;
-            uint32_t rx_done:                 1;
-            uint32_t rx_eof:                  1;
-            uint32_t tohost:                  1;
-            uint32_t tx_dscr_err:             1;
-            uint32_t rx_dscr_err:             1;
-            uint32_t tx_dscr_empty:           1;
-            uint32_t host_rd_ack:             1;
-            uint32_t wr_retry_done:           1;
-            uint32_t tx_err_eof:              1;
-            uint32_t reserved25:              7;
-        };
-        uint32_t val;
-    } slc1_int_clr;
-    union {
-        struct {
-            uint32_t slc0_rx_full: 1;
-            uint32_t slc0_rx_empty: 1;
-            uint32_t reserved2: 14;
-            uint32_t slc1_rx_full: 1;
-            uint32_t slc1_rx_empty: 1;
-            uint32_t reserved18:14;
-        };
-        uint32_t val;
-    } rx_status;
-    union {
-        struct {
-            uint32_t rxfifo_wdata:   9;
-            uint32_t reserved9:      7;
-            uint32_t rxfifo_push:    1;
-            uint32_t reserved17:    15;
-        };
-        uint32_t val;
-    } slc0_rxfifo_push;
-    union {
-        struct {
-            uint32_t rxfifo_wdata:   9;
-            uint32_t reserved9:      7;
-            uint32_t rxfifo_push:    1;
-            uint32_t reserved17:    15;
-        };
-        uint32_t val;
-    } slc1_rxfifo_push;
-    union {
-        struct {
-            uint32_t slc0_tx_full: 1;
-            uint32_t slc0_tx_empty: 1;
-            uint32_t reserved2: 14;
-            uint32_t slc1_tx_full: 1;
-            uint32_t slc1_tx_empty: 1;
-            uint32_t reserved18:14;
-        };
-        uint32_t val;
-    } tx_status;
-    union {
-        struct {
-            uint32_t txfifo_rdata:  11;
-            uint32_t reserved11:     5;
-            uint32_t txfifo_pop:     1;
-            uint32_t reserved17:    15;
-        };
-        uint32_t val;
-    } slc0_txfifo_pop;
-    union {
-        struct {
-            uint32_t txfifo_rdata:  11;
-            uint32_t reserved11:     5;
-            uint32_t txfifo_pop:     1;
-            uint32_t reserved17:    15;
-        };
-        uint32_t val;
-    } slc1_txfifo_pop;
-    union {
-        struct {
-            uint32_t addr:            20;
-            uint32_t reserved20:       8;
-            uint32_t stop:             1;
-            uint32_t start:            1;
-            uint32_t restart:          1;
-            uint32_t park:             1;
-        };
-        uint32_t val;
-    } slc0_rx_link;
-    union {
-        struct {
-            uint32_t addr:            20;
-            uint32_t reserved20:       8;
-            uint32_t stop:             1;
-            uint32_t start:            1;
-            uint32_t restart:          1;
-            uint32_t park:             1;
-        };
-        uint32_t val;
-    } slc0_tx_link;
-    union {
-        struct {
-            uint32_t addr:            20;
-            uint32_t bt_packet:        1;
-            uint32_t reserved21:       7;
-            uint32_t stop:             1;
-            uint32_t start:            1;
-            uint32_t restart:          1;
-            uint32_t park:             1;
-        };
-        uint32_t val;
-    } slc1_rx_link;
-    union {
-        struct {
-            uint32_t addr:            20;
-            uint32_t reserved20:       8;
-            uint32_t stop:             1;
-            uint32_t start:            1;
-            uint32_t restart:          1;
-            uint32_t park:             1;
-        };
-        uint32_t val;
-    } slc1_tx_link;
-    union {
-        struct {
-            uint32_t slc0_intvec:     8;
-            uint32_t reserved8:       8;
-            uint32_t slc1_intvec:     8;
-            uint32_t reserved24:      8;
-        };
-        uint32_t val;
-    } intvec_tohost;
-    union {
-        struct {
-            uint32_t wdata:            12;
-            uint32_t wr:                1;
-            uint32_t inc:               1;
-            uint32_t inc_more:          1;
-            uint32_t reserved15:        1;
-            uint32_t token0:           12;
-            uint32_t reserved28:        4;
-        };
-        uint32_t val;
-    } slc0_token0;
-    union {
-        struct {
-            uint32_t wdata:            12;
-            uint32_t wr:                1;
-            uint32_t inc:               1;
-            uint32_t inc_more:          1;
-            uint32_t reserved15:        1;
-            uint32_t token1:           12;
-            uint32_t reserved28:        4;
-        };
-        uint32_t val;
-    } slc0_token1;
-    union {
-        struct {
-            uint32_t wdata:            12;
-            uint32_t wr:                1;
-            uint32_t inc:               1;
-            uint32_t inc_more:          1;
-            uint32_t reserved15:        1;
-            uint32_t token0:           12;
-            uint32_t reserved28:        4;
-        };
-        uint32_t val;
-    } slc1_token0;
-    union {
-        struct {
-            uint32_t wdata:            12;
-            uint32_t wr:                1;
-            uint32_t inc:               1;
-            uint32_t inc_more:          1;
-            uint32_t reserved15:        1;
-            uint32_t token1:           12;
-            uint32_t reserved28:        4;
-        };
-        uint32_t val;
-    } slc1_token1;
-    union {
-        struct {
-            uint32_t slc0_check_owner:   1;
-            uint32_t slc0_tx_check_sum_en: 1;
-            uint32_t slc0_rx_check_sum_en: 1;
-            uint32_t cmd_hold_en:        1;
-            uint32_t slc0_len_auto_clr:  1;
-            uint32_t slc0_tx_stitch_en:  1;
-            uint32_t slc0_rx_stitch_en:  1;
-            uint32_t reserved7:          9;
-            uint32_t slc1_check_owner:   1;
-            uint32_t slc1_tx_check_sum_en: 1;
-            uint32_t slc1_rx_check_sum_en: 1;
-            uint32_t host_int_level_sel: 1;
-            uint32_t slc1_tx_stitch_en:  1;
-            uint32_t slc1_rx_stitch_en:  1;
-            uint32_t clk_en:             1;
-            uint32_t reserved23:         9;
-        };
-        uint32_t val;
-    } conf1;
-    uint32_t slc0_state0;                                  /**/
-    uint32_t slc0_state1;                                  /**/
-    uint32_t slc1_state0;                                  /**/
-    uint32_t slc1_state1;                                  /**/
-    union {
-        struct {
-            uint32_t txeof_ena:        6;
-            uint32_t reserved6:        2;
-            uint32_t fifo_map_ena:     4;
-            uint32_t slc0_tx_dummy_mode: 1;
-            uint32_t hda_map_128k:     1;
-            uint32_t slc1_tx_dummy_mode: 1;
-            uint32_t reserved15:       1;
-            uint32_t tx_push_idle_num:16;
-        };
-        uint32_t val;
-    } bridge_conf;
-    uint32_t slc0_to_eof_des_addr;                         /**/
-    uint32_t slc0_tx_eof_des_addr;                         /**/
-    uint32_t slc0_to_eof_bfr_des_addr;                     /**/
-    uint32_t slc1_to_eof_des_addr;                         /**/
-    uint32_t slc1_tx_eof_des_addr;                         /**/
-    uint32_t slc1_to_eof_bfr_des_addr;                     /**/
-    union {
-        struct {
-            uint32_t mode:         3;
-            uint32_t reserved3:    1;
-            uint32_t addr:         2;
-            uint32_t reserved6:   26;
-        };
-        uint32_t val;
-    } ahb_test;
-    union {
-        struct {
-            uint32_t cmd_st:          3;
-            uint32_t reserved3:       1;
-            uint32_t func_st:         4;
-            uint32_t sdio_wakeup:     1;
-            uint32_t reserved9:       3;
-            uint32_t bus_st:          3;
-            uint32_t reserved15:      1;
-            uint32_t func1_acc_state: 5;
-            uint32_t reserved21:      3;
-            uint32_t func2_acc_state: 5;
-            uint32_t reserved29:      3;
-        };
-        uint32_t val;
-    } sdio_st;
-    union {
-        struct {
-            uint32_t slc0_token_no_replace: 1;
-            uint32_t slc0_infor_no_replace: 1;
-            uint32_t slc0_rx_fill_mode:    1;
-            uint32_t slc0_rx_eof_mode:     1;
-            uint32_t slc0_rx_fill_en:      1;
-            uint32_t slc0_rd_retry_threshold:11;
-            uint32_t slc1_token_no_replace: 1;
-            uint32_t slc1_infor_no_replace: 1;
-            uint32_t slc1_rx_fill_mode:    1;
-            uint32_t slc1_rx_eof_mode:     1;
-            uint32_t slc1_rx_fill_en:      1;
-            uint32_t slc1_rd_retry_threshold:11;
-        };
-        uint32_t val;
-    } rx_dscr_conf;
-    uint32_t slc0_txlink_dscr;                             /**/
-    uint32_t slc0_txlink_dscr_bf0;                         /**/
-    uint32_t slc0_txlink_dscr_bf1;                         /**/
-    uint32_t slc0_rxlink_dscr;                             /**/
-    uint32_t slc0_rxlink_dscr_bf0;                         /**/
-    uint32_t slc0_rxlink_dscr_bf1;                         /**/
-    uint32_t slc1_txlink_dscr;                             /**/
-    uint32_t slc1_txlink_dscr_bf0;                         /**/
-    uint32_t slc1_txlink_dscr_bf1;                         /**/
-    uint32_t slc1_rxlink_dscr;                             /**/
-    uint32_t slc1_rxlink_dscr_bf0;                         /**/
-    uint32_t slc1_rxlink_dscr_bf1;                         /**/
-    uint32_t slc0_tx_erreof_des_addr;                      /**/
-    uint32_t slc1_tx_erreof_des_addr;                      /**/
-    union {
-        struct {
-            uint32_t slc0_token:12;
-            uint32_t reserved12: 4;
-            uint32_t slc1_token:12;
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    } token_lat;
-    union {
-        struct {
-            uint32_t wr_retry_threshold:11;
-            uint32_t reserved11:        21;
-        };
-        uint32_t val;
-    } tx_dscr_conf;
-    uint32_t cmd_infor0;                                /**/
-    uint32_t cmd_infor1;                                /**/
-    union {
-        struct {
-            uint32_t len_wdata:          20;
-            uint32_t len_wr:              1;
-            uint32_t len_inc:             1;
-            uint32_t len_inc_more:        1;
-            uint32_t rx_packet_load_en:   1;
-            uint32_t tx_packet_load_en:   1;
-            uint32_t rx_get_used_dscr:    1;
-            uint32_t tx_get_used_dscr:    1;
-            uint32_t rx_new_pkt_ind:      1;
-            uint32_t tx_new_pkt_ind:      1;
-            uint32_t reserved29:          3;
-        };
-        uint32_t val;
-    } slc0_len_conf;
-    union {
-        struct {
-            uint32_t len:       20;
-            uint32_t reserved20:12;
-        };
-        uint32_t val;
-    } slc0_length;
-    uint32_t slc0_txpkt_h_dscr;                            /**/
-    uint32_t slc0_txpkt_e_dscr;                            /**/
-    uint32_t slc0_rxpkt_h_dscr;                            /**/
-    uint32_t slc0_rxpkt_e_dscr;                            /**/
-    uint32_t slc0_txpktu_h_dscr;                           /**/
-    uint32_t slc0_txpktu_e_dscr;                           /**/
-    uint32_t slc0_rxpktu_h_dscr;                           /**/
-    uint32_t slc0_rxpktu_e_dscr;                           /**/
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    union {
-        struct {
-            uint32_t slc0_position:  8;
-            uint32_t slc1_position:  8;
-            uint32_t reserved16:    16;
-        };
-        uint32_t val;
-    } seq_position;
-    union {
-        struct {
-            uint32_t rx_dscr_rec_lim:  10;
-            uint32_t reserved10:       22;
-        };
-        uint32_t val;
-    } slc0_dscr_rec_conf;
-    union {
-        struct {
-            uint32_t dat0_crc_err_cnt: 8;
-            uint32_t dat1_crc_err_cnt: 8;
-            uint32_t dat2_crc_err_cnt: 8;
-            uint32_t dat3_crc_err_cnt: 8;
-        };
-        uint32_t val;
-    } sdio_crc_st0;
-    union {
-        struct {
-            uint32_t cmd_crc_err_cnt: 8;
-            uint32_t reserved8:      23;
-            uint32_t err_cnt_clr:     1;
-        };
-        uint32_t val;
-    } sdio_crc_st1;
-    uint32_t slc0_eof_start_des;                           /**/
-    uint32_t slc0_push_dscr_addr;                          /**/
-    uint32_t slc0_done_dscr_addr;                          /**/
-    uint32_t slc0_sub_start_des;                           /**/
-    union {
-        struct {
-            uint32_t rx_dscr_cnt_lat:  10;
-            uint32_t reserved10:        6;
-            uint32_t rx_get_eof_occ:    1;
-            uint32_t reserved17:       15;
-        };
-        uint32_t val;
-    } slc0_dscr_cnt;
-    union {
-        struct {
-            uint32_t len_lim:   20;
-            uint32_t reserved20:12;
-        };
-        uint32_t val;
-    } slc0_len_lim_conf;
-    union {
-        struct {
-            uint32_t frhost_bit01:            1;
-            uint32_t frhost_bit11:            1;
-            uint32_t frhost_bit21:            1;
-            uint32_t frhost_bit31:            1;
-            uint32_t frhost_bit41:            1;
-            uint32_t frhost_bit51:            1;
-            uint32_t frhost_bit61:            1;
-            uint32_t frhost_bit71:            1;
-            uint32_t rx_start1:               1;
-            uint32_t tx_start1:               1;
-            uint32_t rx_udf1:                 1;
-            uint32_t tx_ovf1:                 1;
-            uint32_t token0_1to01:            1;
-            uint32_t token1_1to01:            1;
-            uint32_t tx_done1:                1;
-            uint32_t tx_suc_eof1:             1;
-            uint32_t rx_done1:                1;
-            uint32_t rx_eof1:                 1;
-            uint32_t tohost1:                 1;
-            uint32_t tx_dscr_err1:            1;
-            uint32_t rx_dscr_err1:            1;
-            uint32_t tx_dscr_empty1:          1;
-            uint32_t host_rd_ack1:            1;
-            uint32_t wr_retry_done1:          1;
-            uint32_t tx_err_eof1:             1;
-            uint32_t cmd_dtc1:                1;
-            uint32_t rx_quick_eof1:           1;
-            uint32_t reserved27:              5;
-        };
-        uint32_t val;
-    } slc0_int_st1;
-    union {
-        struct {
-            uint32_t frhost_bit01:             1;
-            uint32_t frhost_bit11:             1;
-            uint32_t frhost_bit21:             1;
-            uint32_t frhost_bit31:             1;
-            uint32_t frhost_bit41:             1;
-            uint32_t frhost_bit51:             1;
-            uint32_t frhost_bit61:             1;
-            uint32_t frhost_bit71:             1;
-            uint32_t rx_start1:                1;
-            uint32_t tx_start1:                1;
-            uint32_t rx_udf1:                  1;
-            uint32_t tx_ovf1:                  1;
-            uint32_t token0_1to01:             1;
-            uint32_t token1_1to01:             1;
-            uint32_t tx_done1:                 1;
-            uint32_t tx_suc_eof1:              1;
-            uint32_t rx_done1:                 1;
-            uint32_t rx_eof1:                  1;
-            uint32_t tohost1:                  1;
-            uint32_t tx_dscr_err1:             1;
-            uint32_t rx_dscr_err1:             1;
-            uint32_t tx_dscr_empty1:           1;
-            uint32_t host_rd_ack1:             1;
-            uint32_t wr_retry_done1:           1;
-            uint32_t tx_err_eof1:              1;
-            uint32_t cmd_dtc1:                 1;
-            uint32_t rx_quick_eof1:            1;
-            uint32_t reserved27:               5;
-        };
-        uint32_t val;
-    } slc0_int_ena1;
-    union {
-        struct {
-            uint32_t frhost_bit81:            1;
-            uint32_t frhost_bit91:            1;
-            uint32_t frhost_bit101:           1;
-            uint32_t frhost_bit111:           1;
-            uint32_t frhost_bit121:           1;
-            uint32_t frhost_bit131:           1;
-            uint32_t frhost_bit141:           1;
-            uint32_t frhost_bit151:           1;
-            uint32_t rx_start1:               1;
-            uint32_t tx_start1:               1;
-            uint32_t rx_udf1:                 1;
-            uint32_t tx_ovf1:                 1;
-            uint32_t token0_1to01:            1;
-            uint32_t token1_1to01:            1;
-            uint32_t tx_done1:                1;
-            uint32_t tx_suc_eof1:             1;
-            uint32_t rx_done1:                1;
-            uint32_t rx_eof1:                 1;
-            uint32_t tohost1:                 1;
-            uint32_t tx_dscr_err1:            1;
-            uint32_t rx_dscr_err1:            1;
-            uint32_t tx_dscr_empty1:          1;
-            uint32_t host_rd_ack1:            1;
-            uint32_t wr_retry_done1:          1;
-            uint32_t tx_err_eof1:             1;
-            uint32_t reserved25:              7;
-        };
-        uint32_t val;
-    } slc1_int_st1;
-    union {
-        struct {
-            uint32_t frhost_bit81:             1;
-            uint32_t frhost_bit91:             1;
-            uint32_t frhost_bit101:            1;
-            uint32_t frhost_bit111:            1;
-            uint32_t frhost_bit121:            1;
-            uint32_t frhost_bit131:            1;
-            uint32_t frhost_bit141:            1;
-            uint32_t frhost_bit151:            1;
-            uint32_t rx_start1:                1;
-            uint32_t tx_start1:                1;
-            uint32_t rx_udf1:                  1;
-            uint32_t tx_ovf1:                  1;
-            uint32_t token0_1to01:             1;
-            uint32_t token1_1to01:             1;
-            uint32_t tx_done1:                 1;
-            uint32_t tx_suc_eof1:              1;
-            uint32_t rx_done1:                 1;
-            uint32_t rx_eof1:                  1;
-            uint32_t tohost1:                  1;
-            uint32_t tx_dscr_err1:             1;
-            uint32_t rx_dscr_err1:             1;
-            uint32_t tx_dscr_empty1:           1;
-            uint32_t host_rd_ack1:             1;
-            uint32_t wr_retry_done1:           1;
-            uint32_t tx_err_eof1:              1;
-            uint32_t reserved25:               7;
-        };
-        uint32_t val;
-    } slc1_int_ena1;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t date;                                      /**/
-    uint32_t id;                                        /**/
-} slc_dev_t;
-extern slc_dev_t SLC;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_SLC_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/soc.h b/tools/sdk/include/soc/soc/soc.h
deleted file mode 100644
index d1d468303cc..00000000000
--- a/tools/sdk/include/soc/soc/soc.h
+++ /dev/null
@@ -1,454 +0,0 @@
-// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP32_SOC_H_
-#define _ESP32_SOC_H_
-
-#ifndef __ASSEMBLER__
-#include <stdint.h>
-#include "esp_assert.h"
-#endif
-
-//Register Bits{{
-#define BIT31   0x80000000
-#define BIT30   0x40000000
-#define BIT29   0x20000000
-#define BIT28   0x10000000
-#define BIT27   0x08000000
-#define BIT26   0x04000000
-#define BIT25   0x02000000
-#define BIT24   0x01000000
-#define BIT23   0x00800000
-#define BIT22   0x00400000
-#define BIT21   0x00200000
-#define BIT20   0x00100000
-#define BIT19   0x00080000
-#define BIT18   0x00040000
-#define BIT17   0x00020000
-#define BIT16   0x00010000
-#define BIT15   0x00008000
-#define BIT14   0x00004000
-#define BIT13   0x00002000
-#define BIT12   0x00001000
-#define BIT11   0x00000800
-#define BIT10   0x00000400
-#define BIT9     0x00000200
-#define BIT8     0x00000100
-#define BIT7     0x00000080
-#define BIT6     0x00000040
-#define BIT5     0x00000020
-#define BIT4     0x00000010
-#define BIT3     0x00000008
-#define BIT2     0x00000004
-#define BIT1     0x00000002
-#define BIT0     0x00000001
-//}}
-
-#define PRO_CPU_NUM (0)
-#define APP_CPU_NUM (1)
-
-/* Overall memory map */
-#define SOC_IROM_LOW            0x400D0000
-#define SOC_IROM_HIGH           0x40400000
-#define SOC_DROM_LOW            0x3F400000
-#define SOC_DROM_HIGH           0x3F800000
-#define SOC_DRAM_LOW            0x3FAE0000
-#define SOC_DRAM_HIGH           0x40000000
-#define SOC_RTC_IRAM_LOW        0x400C0000
-#define SOC_RTC_IRAM_HIGH       0x400C2000
-#define SOC_RTC_DATA_LOW        0x50000000
-#define SOC_RTC_DATA_HIGH       0x50002000
-#define SOC_EXTRAM_DATA_LOW     0x3F800000
-#define SOC_EXTRAM_DATA_HIGH    0x3FC00000
-
-#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
-
-
-#define DR_REG_DPORT_BASE                       0x3ff00000
-#define DR_REG_AES_BASE                         0x3ff01000
-#define DR_REG_RSA_BASE                         0x3ff02000
-#define DR_REG_SHA_BASE                         0x3ff03000
-#define DR_REG_FLASH_MMU_TABLE_PRO              0x3ff10000
-#define DR_REG_FLASH_MMU_TABLE_APP              0x3ff12000
-#define DR_REG_DPORT_END                        0x3ff13FFC
-#define DR_REG_UART_BASE                        0x3ff40000
-#define DR_REG_SPI1_BASE                        0x3ff42000
-#define DR_REG_SPI0_BASE                        0x3ff43000
-#define DR_REG_GPIO_BASE                        0x3ff44000
-#define DR_REG_GPIO_SD_BASE                     0x3ff44f00
-#define DR_REG_FE2_BASE                         0x3ff45000
-#define DR_REG_FE_BASE                          0x3ff46000
-#define DR_REG_FRC_TIMER_BASE                   0x3ff47000
-#define DR_REG_RTCCNTL_BASE                     0x3ff48000
-#define DR_REG_RTCIO_BASE                       0x3ff48400
-#define DR_REG_SENS_BASE                        0x3ff48800
-#define DR_REG_RTC_I2C_BASE                     0x3ff48C00
-#define DR_REG_IO_MUX_BASE                      0x3ff49000
-#define DR_REG_HINF_BASE                        0x3ff4B000
-#define DR_REG_UHCI1_BASE                       0x3ff4C000
-#define DR_REG_I2S_BASE                         0x3ff4F000
-#define DR_REG_UART1_BASE                       0x3ff50000
-#define DR_REG_BT_BASE                          0x3ff51000
-#define DR_REG_I2C_EXT_BASE                     0x3ff53000
-#define DR_REG_UHCI0_BASE                       0x3ff54000
-#define DR_REG_SLCHOST_BASE                     0x3ff55000
-#define DR_REG_RMT_BASE                         0x3ff56000
-#define DR_REG_PCNT_BASE                        0x3ff57000
-#define DR_REG_SLC_BASE                         0x3ff58000
-#define DR_REG_LEDC_BASE                        0x3ff59000
-#define DR_REG_EFUSE_BASE                       0x3ff5A000
-#define DR_REG_SPI_ENCRYPT_BASE                 0x3ff5B000
-#define DR_REG_NRX_BASE                         0x3ff5CC00
-#define DR_REG_BB_BASE                          0x3ff5D000
-#define DR_REG_PWM_BASE                         0x3ff5E000
-#define DR_REG_TIMERGROUP0_BASE                 0x3ff5F000
-#define DR_REG_TIMERGROUP1_BASE                 0x3ff60000
-#define DR_REG_RTCMEM0_BASE                     0x3ff61000
-#define DR_REG_RTCMEM1_BASE                     0x3ff62000
-#define DR_REG_RTCMEM2_BASE                     0x3ff63000
-#define DR_REG_SPI2_BASE                        0x3ff64000
-#define DR_REG_SPI3_BASE                        0x3ff65000
-#define DR_REG_SYSCON_BASE                      0x3ff66000
-#define DR_REG_APB_CTRL_BASE                    0x3ff66000    /* Old name for SYSCON, to be removed */
-#define DR_REG_I2C1_EXT_BASE                    0x3ff67000
-#define DR_REG_SDMMC_BASE                       0x3ff68000
-#define DR_REG_EMAC_BASE                        0x3ff69000
-#define DR_REG_CAN_BASE                         0x3ff6B000
-#define DR_REG_PWM1_BASE                        0x3ff6C000
-#define DR_REG_I2S1_BASE                        0x3ff6D000
-#define DR_REG_UART2_BASE                       0x3ff6E000
-#define DR_REG_PWM2_BASE                        0x3ff6F000
-#define DR_REG_PWM3_BASE                        0x3ff70000
-#define PERIPHS_SPI_ENCRYPT_BASEADDR            DR_REG_SPI_ENCRYPT_BASE
-
-//Registers Operation {{
-#define ETS_UNCACHED_ADDR(addr) (addr)
-#define ETS_CACHED_ADDR(addr) (addr)
-
-#ifndef __ASSEMBLER__
-#define BIT(nr)                 (1UL << (nr))
-#define BIT64(nr)               (1ULL << (nr))
-#else
-#define BIT(nr)                 (1 << (nr))
-#endif
-
-#ifndef __ASSEMBLER__
-
-#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
-
-#if !defined( BOOTLOADER_BUILD ) && defined( CONFIG_ESP32_DPORT_WORKAROUND ) && defined( ESP_PLATFORM )
-#define ASSERT_IF_DPORT_REG(_r, OP)  TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
-#else
-#define ASSERT_IF_DPORT_REG(_r, OP)
-#endif
-
-//write value to register
-#define REG_WRITE(_r, _v) ({                                                                                           \
-            ASSERT_IF_DPORT_REG((_r), REG_WRITE);                                                                      \
-            (*(volatile uint32_t *)(_r)) = (_v);                                                                       \
-        })
-
-//read value from register
-#define REG_READ(_r) ({                                                                                                \
-            ASSERT_IF_DPORT_REG((_r), REG_READ);                                                                       \
-            (*(volatile uint32_t *)(_r));                                                                              \
-        })
-
-//get bit or get bits from register
-#define REG_GET_BIT(_r, _b)  ({                                                                                        \
-            ASSERT_IF_DPORT_REG((_r), REG_GET_BIT);                                                                    \
-            (*(volatile uint32_t*)(_r) & (_b));                                                                        \
-        })
-
-//set bit or set bits to register
-#define REG_SET_BIT(_r, _b)  ({                                                                                        \
-            ASSERT_IF_DPORT_REG((_r), REG_SET_BIT);                                                                    \
-            (*(volatile uint32_t*)(_r) |= (_b));                                                                       \
-        })
-
-//clear bit or clear bits of register
-#define REG_CLR_BIT(_r, _b)  ({                                                                                        \
-            ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT);                                                                    \
-            (*(volatile uint32_t*)(_r) &= ~(_b));                                                                      \
-        })
-
-//set bits of register controlled by mask
-#define REG_SET_BITS(_r, _b, _m) ({                                                                                    \
-            ASSERT_IF_DPORT_REG((_r), REG_SET_BITS);                                                                   \
-            (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)));                         \
-        })
-
-//get field from register, uses field _S & _V to determine mask
-#define REG_GET_FIELD(_r, _f) ({                                                                                       \
-            ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD);                                                                  \
-            ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
-        })
-
-//set field of a register from variable, uses field _S & _V to determine mask
-#define REG_SET_FIELD(_r, _f, _v) ({                                                                                   \
-            ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD);                                                                  \
-            (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))));                \
-        })
-
-//get field value from a variable, used when _f is not left shifted by _f##_S
-#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
-
-//get field value from a variable, used when _f is left shifted by _f##_S
-#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
-
-//set field value to a variable, used when _f is not left shifted by _f##_S
-#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
-
-//set field value to a variable, used when _f is left shifted by _f##_S
-#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
-
-//generate a value from a field value, used when _f is not left shifted by _f##_S
-#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
-
-//generate a value from a field value, used when _f is left shifted by _f##_S
-#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
-
-//read value from register
-#define READ_PERI_REG(addr) ({                                                                                         \
-            ASSERT_IF_DPORT_REG((addr), READ_PERI_REG);                                                                \
-            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)));                                                         \
-        })
-
-//write value to register
-#define WRITE_PERI_REG(addr, val) ({                                                                                   \
-            ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG);                                                               \
-            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val);                                       \
-        })
-
-//clear bits of register controlled by mask
-#define CLEAR_PERI_REG_MASK(reg, mask) ({                                                                              \
-            ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK);                                                           \
-            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))));                                                     \
-        })
-
-//set bits of register controlled by mask
-#define SET_PERI_REG_MASK(reg, mask) ({                                                                                \
-            ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK);                                                             \
-            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)));                                                        \
-        })
-
-//get bits of register controlled by mask
-#define GET_PERI_REG_MASK(reg, mask) ({                                                                                \
-            ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK);                                                             \
-            (READ_PERI_REG(reg) & (mask));                                                                             \
-        })
-
-//get bits of register controlled by highest bit and lowest bit
-#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({                                                                        \
-            ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS);                                                             \
-            ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1));                                            \
-        })
-
-//set bits of register controlled by mask and shift
-#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({                                                                  \
-            ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS);                                                             \
-            (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ));      \
-        })
-
-//get field of register
-#define GET_PERI_REG_BITS2(reg, mask,shift) ({                                                                         \
-            ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2);                                                            \
-            ((READ_PERI_REG(reg)>>(shift))&(mask));                                                                    \
-        })
-
-#endif /* !__ASSEMBLER__ */
-//}}
-
-//Periheral Clock {{
-#define  APB_CLK_FREQ_ROM                            ( 26*1000000 )
-#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
-#define  CPU_CLK_FREQ                                APB_CLK_FREQ
-#define  APB_CLK_FREQ                                ( 80*1000000 )       //unit: Hz
-#define  REF_CLK_FREQ                                ( 1000000 )
-#define  UART_CLK_FREQ                               APB_CLK_FREQ
-#define  WDT_CLK_FREQ                                APB_CLK_FREQ
-#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
-#define  SPI_CLK_DIV                                 4
-#define  TICKS_PER_US_ROM                            26              // CPU is 80MHz
-//}}
-
-/* Overall memory map */
-#define SOC_DROM_LOW    0x3F400000
-#define SOC_DROM_HIGH   0x3F800000
-#define SOC_IROM_LOW    0x400D0000
-#define SOC_IROM_HIGH   0x40400000
-#define SOC_IROM_MASK_LOW   0x40000000
-#define SOC_IROM_MASK_HIGH  0x40070000
-#define SOC_CACHE_PRO_LOW   0x40070000
-#define SOC_CACHE_PRO_HIGH  0x40078000
-#define SOC_CACHE_APP_LOW   0x40078000
-#define SOC_CACHE_APP_HIGH  0x40080000
-#define SOC_IRAM_LOW    0x40080000
-#define SOC_IRAM_HIGH   0x400A0000
-#define SOC_RTC_IRAM_LOW  0x400C0000
-#define SOC_RTC_IRAM_HIGH 0x400C2000
-#define SOC_RTC_DRAM_LOW  0x3FF80000
-#define SOC_RTC_DRAM_HIGH 0x3FF82000
-#define SOC_RTC_DATA_LOW  0x50000000
-#define SOC_RTC_DATA_HIGH 0x50002000
-
-//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
-#define SOC_DIRAM_IRAM_LOW    0x400A0000
-#define SOC_DIRAM_IRAM_HIGH   0x400BFFFC
-#define SOC_DIRAM_DRAM_LOW    0x3FFE0000
-#define SOC_DIRAM_DRAM_HIGH   0x3FFFFFFC
-
-// Region of memory accessible via DMA. See esp_ptr_dma_capable().
-#define SOC_DMA_LOW  0x3FFAE000
-#define SOC_DMA_HIGH 0x40000000
-
-// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
-#define SOC_BYTE_ACCESSIBLE_LOW     0x3FF90000
-#define SOC_BYTE_ACCESSIBLE_HIGH    0x40000000
-
-//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
-//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
-#define SOC_MEM_INTERNAL_LOW        0x3FF90000
-#define SOC_MEM_INTERNAL_HIGH       0x400C2000
-
-//Interrupt hardware source table
-//This table is decided by hardware, don't touch this.
-#define ETS_WIFI_MAC_INTR_SOURCE                0/**< interrupt of WiFi MAC, level*/
-#define ETS_WIFI_MAC_NMI_SOURCE                 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
-#define ETS_WIFI_BB_INTR_SOURCE                 2/**< interrupt of WiFi BB, level, we can do some calibartion*/
-#define ETS_BT_MAC_INTR_SOURCE                  3/**< will be cancelled*/
-#define ETS_BT_BB_INTR_SOURCE                   4/**< interrupt of BT BB, level*/
-#define ETS_BT_BB_NMI_SOURCE                    5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
-#define ETS_RWBT_INTR_SOURCE                    6/**< interrupt of RWBT, level*/
-#define ETS_RWBLE_INTR_SOURCE                   7/**< interrupt of RWBLE, level*/
-#define ETS_RWBT_NMI_SOURCE                     8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
-#define ETS_RWBLE_NMI_SOURCE                    9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
-#define ETS_SLC0_INTR_SOURCE                    10/**< interrupt of SLC0, level*/
-#define ETS_SLC1_INTR_SOURCE                    11/**< interrupt of SLC1, level*/
-#define ETS_UHCI0_INTR_SOURCE                   12/**< interrupt of UHCI0, level*/
-#define ETS_UHCI1_INTR_SOURCE                   13/**< interrupt of UHCI1, level*/
-#define ETS_TG0_T0_LEVEL_INTR_SOURCE            14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
-#define ETS_TG0_T1_LEVEL_INTR_SOURCE            15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
-#define ETS_TG0_WDT_LEVEL_INTR_SOURCE           16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
-#define ETS_TG0_LACT_LEVEL_INTR_SOURCE          17/**< interrupt of TIMER_GROUP0, LACT, level*/
-#define ETS_TG1_T0_LEVEL_INTR_SOURCE            18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
-#define ETS_TG1_T1_LEVEL_INTR_SOURCE            19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
-#define ETS_TG1_WDT_LEVEL_INTR_SOURCE           20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
-#define ETS_TG1_LACT_LEVEL_INTR_SOURCE          21/**< interrupt of TIMER_GROUP1, LACT, level*/
-#define ETS_GPIO_INTR_SOURCE                    22/**< interrupt of GPIO, level*/
-#define ETS_GPIO_NMI_SOURCE                     23/**< interrupt of GPIO, NMI*/
-#define ETS_FROM_CPU_INTR0_SOURCE               24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
-#define ETS_FROM_CPU_INTR1_SOURCE               25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
-#define ETS_FROM_CPU_INTR2_SOURCE               26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
-#define ETS_FROM_CPU_INTR3_SOURCE               27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
-#define ETS_SPI0_INTR_SOURCE                    28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
-#define ETS_SPI1_INTR_SOURCE                    29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
-#define ETS_SPI2_INTR_SOURCE                    30/**< interrupt of SPI2, level*/
-#define ETS_SPI3_INTR_SOURCE                    31/**< interrupt of SPI3, level*/
-#define ETS_I2S0_INTR_SOURCE                    32/**< interrupt of I2S0, level*/
-#define ETS_I2S1_INTR_SOURCE                    33/**< interrupt of I2S1, level*/
-#define ETS_UART0_INTR_SOURCE                   34/**< interrupt of UART0, level*/
-#define ETS_UART1_INTR_SOURCE                   35/**< interrupt of UART1, level*/
-#define ETS_UART2_INTR_SOURCE                   36/**< interrupt of UART2, level*/
-#define ETS_SDIO_HOST_INTR_SOURCE               37/**< interrupt of SD/SDIO/MMC HOST, level*/
-#define ETS_ETH_MAC_INTR_SOURCE                 38/**< interrupt of ethernet mac, level*/
-#define ETS_PWM0_INTR_SOURCE                    39/**< interrupt of PWM0, level, Reserved*/
-#define ETS_PWM1_INTR_SOURCE                    40/**< interrupt of PWM1, level, Reserved*/
-#define ETS_PWM2_INTR_SOURCE                    41/**< interrupt of PWM2, level*/
-#define ETS_PWM3_INTR_SOURCE                    42/**< interruot of PWM3, level*/
-#define ETS_LEDC_INTR_SOURCE                    43/**< interrupt of LED PWM, level*/
-#define ETS_EFUSE_INTR_SOURCE                   44/**< interrupt of efuse, level, not likely to use*/
-#define ETS_CAN_INTR_SOURCE                     45/**< interrupt of can, level*/
-#define ETS_RTC_CORE_INTR_SOURCE                46/**< interrupt of rtc core, level, include rtc watchdog*/
-#define ETS_RMT_INTR_SOURCE                     47/**< interrupt of remote controller, level*/
-#define ETS_PCNT_INTR_SOURCE                    48/**< interrupt of pluse count, level*/
-#define ETS_I2C_EXT0_INTR_SOURCE                49/**< interrupt of I2C controller1, level*/
-#define ETS_I2C_EXT1_INTR_SOURCE                50/**< interrupt of I2C controller0, level*/
-#define ETS_RSA_INTR_SOURCE                     51/**< interrupt of RSA accelerator, level*/
-#define ETS_SPI1_DMA_INTR_SOURCE                52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
-#define ETS_SPI2_DMA_INTR_SOURCE                53/**< interrupt of SPI2 DMA, level*/
-#define ETS_SPI3_DMA_INTR_SOURCE                54/**< interrupt of SPI3 DMA, level*/
-#define ETS_WDT_INTR_SOURCE                     55/**< will be cancelled*/
-#define ETS_TIMER1_INTR_SOURCE                  56/**< will be cancelled*/
-#define ETS_TIMER2_INTR_SOURCE                  57/**< will be cancelled*/
-#define ETS_TG0_T0_EDGE_INTR_SOURCE             58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
-#define ETS_TG0_T1_EDGE_INTR_SOURCE             59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
-#define ETS_TG0_WDT_EDGE_INTR_SOURCE            60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
-#define ETS_TG0_LACT_EDGE_INTR_SOURCE           61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
-#define ETS_TG1_T0_EDGE_INTR_SOURCE             62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
-#define ETS_TG1_T1_EDGE_INTR_SOURCE             63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
-#define ETS_TG1_WDT_EDGE_INTR_SOURCE            64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
-#define ETS_TG1_LACT_EDGE_INTR_SOURCE           65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
-#define ETS_MMU_IA_INTR_SOURCE                  66/**< interrupt of MMU Invalid Access, LEVEL*/
-#define ETS_MPU_IA_INTR_SOURCE                  67/**< interrupt of MPU Invalid Access, LEVEL*/
-#define ETS_CACHE_IA_INTR_SOURCE                68/**< interrupt of Cache Invalied Access, LEVEL*/
-
-//interrupt cpu using table, Please see the core-isa.h
-/*************************************************************************************************************
- *      Intr num                Level           Type                    PRO CPU usage           APP CPU uasge
- *      0                       1               extern level            WMAC                    Reserved
- *      1                       1               extern level            BT/BLE Host HCI DMA     BT/BLE Host HCI DMA
- *      2                       1               extern level
- *      3                       1               extern level
- *      4                       1               extern level            WBB
- *      5                       1               extern level            BT/BLE Controller       BT/BLE Controller
- *      6                       1               timer                   FreeRTOS Tick(L1)       FreeRTOS Tick(L1)
- *      7                       1               software                BT/BLE VHCI             BT/BLE VHCI
- *      8                       1               extern level            BT/BLE BB(RX/TX)        BT/BLE BB(RX/TX)
- *      9                       1               extern level
- *      10                      1               extern edge
- *      11                      3               profiling
- *      12                      1               extern level
- *      13                      1               extern level
- *      14                      7               nmi                     Reserved                Reserved
- *      15                      3               timer                   FreeRTOS Tick(L3)       FreeRTOS Tick(L3)
- *      16                      5               timer
- *      17                      1               extern level
- *      18                      1               extern level
- *      19                      2               extern level
- *      20                      2               extern level
- *      21                      2               extern level
- *      22                      3               extern edge
- *      23                      3               extern level
- *      24                      4               extern level            TG1_WDT
- *      25                      4               extern level            CACHEERR
- *      26                      5               extern level
- *      27                      3               extern level            Reserved                Reserved
- *      28                      4               extern edge             DPORT ACCESS            DPORT ACCESS
- *      29                      3               software                Reserved                Reserved
- *      30                      4               extern edge             Reserved                Reserved
- *      31                      5               extern level
- *************************************************************************************************************
- */
-
-//CPU0 Interrupt number reserved, not touch this.
-#define ETS_WMAC_INUM                           0
-#define ETS_BT_HOST_INUM                        1
-#define ETS_WBB_INUM                            4
-#define ETS_TG0_T1_INUM                         10 /**< use edge interrupt*/
-#define ETS_FRC1_INUM                           22
-#define ETS_T1_WDT_INUM                         24
-#define ETS_CACHEERR_INUM                       25
-#define ETS_DPORT_INUM                          28
-
-//CPU0 Interrupt number used in ROM, should be cancelled in SDK
-#define ETS_SLC_INUM                            1
-#define ETS_UART0_INUM                          5
-#define ETS_UART1_INUM                          5
-//Other interrupt number should be managed by the user
-
-//Invalid interrupt for number interrupt matrix
-#define ETS_INVALID_INUM                        6
-
-#endif /* _ESP32_SOC_H_ */
diff --git a/tools/sdk/include/soc/soc/soc_memory_layout.h b/tools/sdk/include/soc/soc/soc_memory_layout.h
deleted file mode 100644
index 9bca1120ab3..00000000000
--- a/tools/sdk/include/soc/soc/soc_memory_layout.h
+++ /dev/null
@@ -1,208 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-#include <stdlib.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "soc/soc.h"
-#include "sdkconfig.h"
-#include "esp_attr.h"
-
-#ifdef CONFIG_BT_ENABLED
-
-#define SOC_MEM_BT_DATA_START               0x3ffae6e0
-#define SOC_MEM_BT_DATA_END                 0x3ffaff10
-#define SOC_MEM_BT_EM_START                 0x3ffb0000
-#define SOC_MEM_BT_EM_END                   0x3ffb7cd8
-#define SOC_MEM_BT_EM_BTDM0_START           0x3ffb0000
-#define SOC_MEM_BT_EM_BTDM0_END             0x3ffb09a8
-#define SOC_MEM_BT_EM_BLE_START             0x3ffb09a8
-#define SOC_MEM_BT_EM_BLE_END               0x3ffb1ddc
-#define SOC_MEM_BT_EM_BTDM1_START           0x3ffb1ddc
-#define SOC_MEM_BT_EM_BTDM1_END             0x3ffb2730
-#define SOC_MEM_BT_EM_BREDR_START           0x3ffb2730
-#define SOC_MEM_BT_EM_BREDR_NO_SYNC_END     0x3ffb6388  //Not calculate with synchronize connection support
-#define SOC_MEM_BT_EM_BREDR_END             0x3ffb7cd8  //Calculate with synchronize connection support
-#define SOC_MEM_BT_EM_SYNC0_START           0x3ffb6388
-#define SOC_MEM_BT_EM_SYNC0_END             0x3ffb6bf8
-#define SOC_MEM_BT_EM_SYNC1_START           0x3ffb6bf8
-#define SOC_MEM_BT_EM_SYNC1_END             0x3ffb7468
-#define SOC_MEM_BT_EM_SYNC2_START           0x3ffb7468
-#define SOC_MEM_BT_EM_SYNC2_END             0x3ffb7cd8
-#define SOC_MEM_BT_BSS_START                0x3ffb8000
-#define SOC_MEM_BT_BSS_END                  0x3ffb9a20
-#define SOC_MEM_BT_MISC_START               0x3ffbdb28
-#define SOC_MEM_BT_MISC_END                 0x3ffbdb5c
-
-#define SOC_MEM_BT_EM_PER_SYNC_SIZE         0x870
-
-#define SOC_MEM_BT_EM_BREDR_REAL_END        (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE)
-
-#endif //CONFIG_BT_ENABLED
-
-#define SOC_MEMORY_TYPE_NO_PRIOS 3
-
-/* Type descriptor holds a description for a particular type of memory on a particular SoC.
- */
-typedef struct {
-    const char *name;  ///< Name of this memory type
-    uint32_t caps[SOC_MEMORY_TYPE_NO_PRIOS]; ///< Capabilities for this memory type (as a prioritised set)
-    bool aliased_iram;   ///< If true, this is data memory that is is also mapped in IRAM
-    bool startup_stack; ///< If true, memory of this type is used for ROM stack during startup
-} soc_memory_type_desc_t;
-
-/* Constant table of tag descriptors for all this SoC's tags */
-extern const soc_memory_type_desc_t soc_memory_types[];
-extern const size_t soc_memory_type_count;
-
-/* Region descriptor holds a description for a particular region of memory on a particular SoC.
- */
-typedef struct
-{
-    intptr_t start;  ///< Start address of the region
-    size_t size;            ///< Size of the region in bytes
-    size_t type;             ///< Type of the region (index into soc_memory_types array)
-    intptr_t iram_address; ///< If non-zero, is equivalent address in IRAM
-} soc_memory_region_t;
-
-extern const soc_memory_region_t soc_memory_regions[];
-extern const size_t soc_memory_region_count;
-
-/* Region descriptor holds a description for a particular region of
-   memory reserved on this SoC for a particular use (ie not available
-   for stack/heap usage.) */
-typedef struct
-{
-    intptr_t start;
-    intptr_t end;
-} soc_reserved_region_t;
-
-/* Use this macro to reserved a fixed region of RAM (hardcoded addresses)
- * for a particular purpose.
- *
- * Usually used to mark out memory addresses needed for hardware or ROM code
- * purposes.
- *
- * Don't call this macro from user code which can use normal C static allocation
- * instead.
- *
- * @param START Start address to be reserved.
- * @param END One after the address of the last byte to be reserved. (ie length of
- * the reserved region is (END - START) in bytes.
- * @param NAME Name for the reserved region. Must be a valid variable name,
- * unique to this source file.
- */
-#define SOC_RESERVE_MEMORY_REGION(START, END, NAME)     \
-    __attribute__((section(".reserved_memory_address"))) __attribute__((used)) \
-    static soc_reserved_region_t reserved_region_##NAME = { START, END };
-
-/* Return available memory regions for this SoC. Each available memory
- * region is a contiguous piece of memory which is not being used by
- * static data, used by ROM code, or reserved by a component using
- * the SOC_RESERVE_MEMORY_REGION() macro.
- *
- * This result is soc_memory_regions[] minus all regions reserved
- * via the SOC_RESERVE_MEMORY_REGION() macro (which may also split
- * some regions up.)
- *
- * At startup, all available memory returned by this function is
- * registered as heap space.
- *
- * @note OS-level startup function only, not recommended to call from
- * app code.
- *
- * @param regions Pointer to an array for reading available regions into.
- * Size of the array should be at least the result of
- * soc_get_available_memory_region_max_count(). Entries in the array
- * will be ordered by memory address.
- *
- * @return Number of entries copied to 'regions'. Will be no greater than
- * the result of soc_get_available_memory_region_max_count().
- */
-size_t soc_get_available_memory_regions(soc_memory_region_t *regions);
-
-/* Return the maximum number of available memory regions which could be
- * returned by soc_get_available_memory_regions(). Used to size the
- * array passed to that function.
- */
-size_t soc_get_available_memory_region_max_count();
-
-inline static bool IRAM_ATTR esp_ptr_dma_capable(const void *p)
-{
-    return (intptr_t)p >= SOC_DMA_LOW && (intptr_t)p < SOC_DMA_HIGH;
-}
-
-inline static bool IRAM_ATTR esp_ptr_word_aligned(const void *p)
-{
-    return ((intptr_t)p) % 4 == 0;
-}
-
-inline static bool IRAM_ATTR esp_ptr_executable(const void *p)
-{
-    intptr_t ip = (intptr_t) p;
-    return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
-        || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
-        || (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH)
-#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE)
-        || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
-#endif
-        || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
-}
-
-inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
-{
-    bool r;
-    r = ((intptr_t)p >= SOC_BYTE_ACCESSIBLE_LOW && (intptr_t)p < SOC_BYTE_ACCESSIBLE_HIGH);
-#if CONFIG_SPIRAM_SUPPORT
-    r |= ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
-#endif
-    return r;
-}
-
-inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
-    bool r;
-    r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
-    r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
-    return r;
-}
-
-
-inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
-    return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
-}
-
-inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) {
-#ifndef CONFIG_FREERTOS_UNICORE
-    return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
-#else
-    return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
-#endif
-}
-
-inline static bool IRAM_ATTR esp_ptr_in_drom(const void *p) {
-    return ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < SOC_DROM_HIGH);
-}
-
-inline static bool IRAM_ATTR esp_ptr_in_dram(const void *p) {
-    return ((intptr_t)p >= SOC_DRAM_LOW && (intptr_t)p < SOC_DRAM_HIGH);
-}
-
-inline static bool IRAM_ATTR esp_ptr_in_diram_dram(const void *p) {
-    return ((intptr_t)p >= SOC_DIRAM_DRAM_LOW && (intptr_t)p < SOC_DIRAM_DRAM_HIGH);
-}
-
-inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) {
-    return ((intptr_t)p >= SOC_DIRAM_IRAM_LOW && (intptr_t)p < SOC_DIRAM_IRAM_HIGH);
-}
diff --git a/tools/sdk/include/soc/soc/soc_ulp.h b/tools/sdk/include/soc/soc/soc_ulp.h
deleted file mode 100644
index e8c20d2b565..00000000000
--- a/tools/sdk/include/soc/soc/soc_ulp.h
+++ /dev/null
@@ -1,46 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-// This file contains various convenience macros to be used in ULP programs.
-
-// Helper macros to calculate bit field width from mask, using the preprocessor.
-// Used later in READ_RTC_FIELD and WRITE_RTC_FIELD.
-#define IS_BIT_SET(m, i) (((m) >> (i)) & 1)
-#define MASK_TO_WIDTH_HELPER1(m, i)  IS_BIT_SET(m, i)
-#define MASK_TO_WIDTH_HELPER2(m, i)  (MASK_TO_WIDTH_HELPER1(m, i)  + MASK_TO_WIDTH_HELPER1(m, i + 1))
-#define MASK_TO_WIDTH_HELPER4(m, i)  (MASK_TO_WIDTH_HELPER2(m, i)  + MASK_TO_WIDTH_HELPER2(m, i + 2))
-#define MASK_TO_WIDTH_HELPER8(m, i)  (MASK_TO_WIDTH_HELPER4(m, i)  + MASK_TO_WIDTH_HELPER4(m, i + 4))
-#define MASK_TO_WIDTH_HELPER16(m, i) (MASK_TO_WIDTH_HELPER8(m, i)  + MASK_TO_WIDTH_HELPER8(m, i + 8))
-#define MASK_TO_WIDTH_HELPER32(m, i) (MASK_TO_WIDTH_HELPER16(m, i) + MASK_TO_WIDTH_HELPER16(m, i + 16))
-
-// Peripheral register access macros, build around REG_RD and REG_WR instructions.
-// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros.
-
-// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16
-#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \
-    REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit)
-
-// Write immediate value into rtc_reg[low_bit + bit_width - 1 : low_bit], bit_width <= 8
-#define WRITE_RTC_REG(rtc_reg, low_bit, bit_width, value) \
-    REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value) & 0xff)
-
-// Read from a field in rtc_reg into R0, up to 16 bits
-#define READ_RTC_FIELD(rtc_reg, field) \
-    READ_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER16(field ## _V, 0))
-
-// Write immediate value into a field in rtc_reg, up to 8 bits
-#define WRITE_RTC_FIELD(rtc_reg, field, value) \
-    WRITE_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER8(field ## _V, 0), ((value) & field ## _V))
-
diff --git a/tools/sdk/include/soc/soc/spi_periph.h b/tools/sdk/include/soc/soc/spi_periph.h
deleted file mode 100644
index 19b3f745125..00000000000
--- a/tools/sdk/include/soc/soc/spi_periph.h
+++ /dev/null
@@ -1,66 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_SPI_PERIPH_H_
-#define _SOC_SPI_PERIPH_H_
-
-#include <stdint.h>
-#include "soc/soc.h"
-#include "soc/periph_defs.h"
-//include soc related (generated) definitions
-#include "soc/spi_pins.h"
-#include "soc/spi_reg.h"
-#include "soc/spi_struct.h"
-#include "soc/gpio_sig_map.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*
- Stores a bunch of per-spi-peripheral data.
-*/
-typedef struct {
-    const uint8_t spiclk_out;       //GPIO mux output signals
-    const uint8_t spiclk_in;
-    const uint8_t spid_out;
-    const uint8_t spiq_out;
-    const uint8_t spiwp_out;
-    const uint8_t spihd_out;
-    const uint8_t spid_in;          //GPIO mux input signals
-    const uint8_t spiq_in;
-    const uint8_t spiwp_in;
-    const uint8_t spihd_in;
-    const uint8_t spics_out[3];     // /CS GPIO output mux signals
-    const uint8_t spics_in;
-    const uint8_t spiclk_iomux_pin;    //IO pins of IO_MUX muxed signals
-    const uint8_t spid_iomux_pin;
-    const uint8_t spiq_iomux_pin;
-    const uint8_t spiwp_iomux_pin;
-    const uint8_t spihd_iomux_pin;
-    const uint8_t spics0_iomux_pin;
-    const uint8_t irq;              //irq source for interrupt mux
-    const uint8_t irq_dma;          //dma irq source for interrupt mux
-    const periph_module_t module;   //peripheral module, for enabling clock etc
-    spi_dev_t *hw;              //Pointer to the hardware registers
-} spi_signal_conn_t;
-
-extern const spi_signal_conn_t spi_periph_signal[3];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SOC_SPI_PERIPH_H_ */
\ No newline at end of file
diff --git a/tools/sdk/include/soc/soc/spi_pins.h b/tools/sdk/include/soc/soc/spi_pins.h
deleted file mode 100644
index eb7af858273..00000000000
--- a/tools/sdk/include/soc/soc/spi_pins.h
+++ /dev/null
@@ -1,39 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_SPI_PINS_H_
-#define _SOC_SPI_PINS_H_
-
-#define SPI_IOMUX_PIN_NUM_MISO  7
-#define SPI_IOMUX_PIN_NUM_MOSI  8
-#define SPI_IOMUX_PIN_NUM_CLK   6
-#define SPI_IOMUX_PIN_NUM_CS    11
-#define SPI_IOMUX_PIN_NUM_WP    10
-#define SPI_IOMUX_PIN_NUM_HD    9
-
-#define HSPI_IOMUX_PIN_NUM_MISO 12
-#define HSPI_IOMUX_PIN_NUM_MOSI 13
-#define HSPI_IOMUX_PIN_NUM_CLK  14
-#define HSPI_IOMUX_PIN_NUM_CS   15
-#define HSPI_IOMUX_PIN_NUM_WP   2
-#define HSPI_IOMUX_PIN_NUM_HD   4
-
-#define VSPI_IOMUX_PIN_NUM_MISO 19
-#define VSPI_IOMUX_PIN_NUM_MOSI 23
-#define VSPI_IOMUX_PIN_NUM_CLK  18
-#define VSPI_IOMUX_PIN_NUM_CS   5
-#define VSPI_IOMUX_PIN_NUM_WP   22
-#define VSPI_IOMUX_PIN_NUM_HD   21
-
-#endif /* _SOC_SPI_PINS_H_ */
\ No newline at end of file
diff --git a/tools/sdk/include/soc/soc/spi_reg.h b/tools/sdk/include/soc/soc/spi_reg.h
deleted file mode 100644
index fac2965c786..00000000000
--- a/tools/sdk/include/soc/soc/spi_reg.h
+++ /dev/null
@@ -1,1713 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __SPI_REG_H__
-#define __SPI_REG_H__
-
-
-#include "soc.h"
-#define REG_SPI_BASE(i)     (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 )))
-
-#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
-/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Read flash enable. Read flash operation will be triggered when
- the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-#define SPI_FLASH_READ  (BIT(31))
-#define SPI_FLASH_READ_M  (BIT(31))
-#define SPI_FLASH_READ_V  0x1
-#define SPI_FLASH_READ_S  31
-/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Write flash enable.  Write enable command will be sent when the
- bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-#define SPI_FLASH_WREN  (BIT(30))
-#define SPI_FLASH_WREN_M  (BIT(30))
-#define SPI_FLASH_WREN_V  0x1
-#define SPI_FLASH_WREN_S  30
-/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Write flash disable. Write disable command will be sent when
- the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-#define SPI_FLASH_WRDI  (BIT(29))
-#define SPI_FLASH_WRDI_M  (BIT(29))
-#define SPI_FLASH_WRDI_V  0x1
-#define SPI_FLASH_WRDI_S  29
-/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Read JEDEC ID . Read ID command will be sent when the bit is
- set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-#define SPI_FLASH_RDID  (BIT(28))
-#define SPI_FLASH_RDID_M  (BIT(28))
-#define SPI_FLASH_RDID_V  0x1
-#define SPI_FLASH_RDID_S  28
-/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Read status register-1.  Read status operation will be triggered
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_RDSR  (BIT(27))
-#define SPI_FLASH_RDSR_M  (BIT(27))
-#define SPI_FLASH_RDSR_V  0x1
-#define SPI_FLASH_RDSR_S  27
-/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write status register enable.   Write status operation  will
- be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_WRSR  (BIT(26))
-#define SPI_FLASH_WRSR_M  (BIT(26))
-#define SPI_FLASH_WRSR_V  0x1
-#define SPI_FLASH_WRSR_S  26
-/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Page program enable(1 byte ~256 bytes data to be programmed).
- Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
-#define SPI_FLASH_PP  (BIT(25))
-#define SPI_FLASH_PP_M  (BIT(25))
-#define SPI_FLASH_PP_V  0x1
-#define SPI_FLASH_PP_S  25
-/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_SE  (BIT(24))
-#define SPI_FLASH_SE_M  (BIT(24))
-#define SPI_FLASH_SE_V  0x1
-#define SPI_FLASH_SE_S  24
-/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Block erase enable. A 64KB block is erased via SPI command D8H.  Block erase operation will be triggered
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_BE  (BIT(23))
-#define SPI_FLASH_BE_M  (BIT(23))
-#define SPI_FLASH_BE_V  0x1
-#define SPI_FLASH_BE_S  23
-/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Chip erase enable. Chip erase operation will be triggered when
- the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_CE  (BIT(22))
-#define SPI_FLASH_CE_M  (BIT(22))
-#define SPI_FLASH_CE_V  0x1
-#define SPI_FLASH_CE_S  22
-/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Drive Flash into power down.  An operation will be triggered
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_DP  (BIT(21))
-#define SPI_FLASH_DP_M  (BIT(21))
-#define SPI_FLASH_DP_V  0x1
-#define SPI_FLASH_DP_S  21
-/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: This bit combined with reg_resandres bit releases Flash from
- the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_RES  (BIT(20))
-#define SPI_FLASH_RES_M  (BIT(20))
-#define SPI_FLASH_RES_V  0x1
-#define SPI_FLASH_RES_S  20
-/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Drive Flash into high performance mode.  The bit will be cleared
- once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_HPM  (BIT(19))
-#define SPI_FLASH_HPM_M  (BIT(19))
-#define SPI_FLASH_HPM_V  0x1
-#define SPI_FLASH_HPM_S  19
-/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: User define command enable.  An operation will be triggered when
- the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_USR  (BIT(18))
-#define SPI_USR_M  (BIT(18))
-#define SPI_USR_V  0x1
-#define SPI_USR_S  18
-/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: program erase suspend bit  program erase suspend operation will
- be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_PES  (BIT(17))
-#define SPI_FLASH_PES_M  (BIT(17))
-#define SPI_FLASH_PES_V  0x1
-#define SPI_FLASH_PES_S  17
-/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: program erase resume bit  program erase suspend operation will
- be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_FLASH_PER  (BIT(16))
-#define SPI_FLASH_PER_M  (BIT(16))
-#define SPI_FLASH_PER_V  0x1
-#define SPI_FLASH_PER_S  16
-
-#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x4)
-//The CSV actually is wrong here. It indicates that the lower 8 bits of this register are reserved. This is not true,
-//all 32 bits of SPI_ADDR_REG are usable/used.
-
-#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
-/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
-#define SPI_WR_BIT_ORDER  (BIT(26))
-#define SPI_WR_BIT_ORDER_M  (BIT(26))
-#define SPI_WR_BIT_ORDER_V  0x1
-#define SPI_WR_BIT_ORDER_S  26
-/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/
-#define SPI_RD_BIT_ORDER  (BIT(25))
-#define SPI_RD_BIT_ORDER_M  (BIT(25))
-#define SPI_RD_BIT_ORDER_V  0x1
-#define SPI_RD_BIT_ORDER_S  25
-/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply
- 4 signals. 1: enable 0: disable.*/
-#define SPI_FREAD_QIO  (BIT(24))
-#define SPI_FREAD_QIO_M  (BIT(24))
-#define SPI_FREAD_QIO_V  0x1
-#define SPI_FREAD_QIO_S  24
-/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply
- 2 signals. 1: enable 0: disable.*/
-#define SPI_FREAD_DIO  (BIT(23))
-#define SPI_FREAD_DIO_M  (BIT(23))
-#define SPI_FREAD_DIO_V  0x1
-#define SPI_FREAD_DIO_S  23
-/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: two bytes data will be written to status register when it is
- set. 1: enable 0: disable.*/
-#define SPI_WRSR_2B  (BIT(22))
-#define SPI_WRSR_2B_M  (BIT(22))
-#define SPI_WRSR_2B_V  0x1
-#define SPI_WRSR_2B_S  22
-/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high  0: output low.*/
-#define SPI_WP_REG  (BIT(21))
-#define SPI_WP_REG_M  (BIT(21))
-#define SPI_WP_REG_V  0x1
-#define SPI_WP_REG_S  21
-/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
-#define SPI_FREAD_QUAD  (BIT(20))
-#define SPI_FREAD_QUAD_M  (BIT(20))
-#define SPI_FREAD_QUAD_V  0x1
-#define SPI_FREAD_QUAD_S  20
-/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: The Device ID is read out to SPI_RD_STATUS register, this bit
- combine with spi_flash_res bit. 1: enable 0: disable.*/
-#define SPI_RESANDRES  (BIT(15))
-#define SPI_RESANDRES_M  (BIT(15))
-#define SPI_RESANDRES_V  0x1
-#define SPI_RESANDRES_S  15
-/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
-#define SPI_FREAD_DUAL  (BIT(14))
-#define SPI_FREAD_DUAL_M  (BIT(14))
-#define SPI_FREAD_DUAL_V  0x1
-#define SPI_FREAD_DUAL_S  14
-/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This bit enable the bits: spi_fread_qio  spi_fread_dio  spi_fread_qout
- and spi_fread_dout. 1: enable 0: disable.*/
-#define SPI_FASTRD_MODE  (BIT(13))
-#define SPI_FASTRD_MODE_M  (BIT(13))
-#define SPI_FASTRD_MODE_V  0x1
-#define SPI_FASTRD_MODE_S  13
-/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: wait flash idle when program flash or erase flash. 1: enable 0: disable.*/
-#define SPI_WAIT_FLASH_IDLE_EN  (BIT(12))
-#define SPI_WAIT_FLASH_IDLE_EN_M  (BIT(12))
-#define SPI_WAIT_FLASH_IDLE_EN_V  0x1
-#define SPI_WAIT_FLASH_IDLE_EN_S  12
-/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI1  enable crc32 when writing encrypted data to flash.
- 1: enable  0:disable*/
-#define SPI_TX_CRC_EN  (BIT(11))
-#define SPI_TX_CRC_EN_M  (BIT(11))
-#define SPI_TX_CRC_EN_V  0x1
-#define SPI_TX_CRC_EN_S  11
-/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: For SPI1  initialize crc32 module before writing encrypted data
- to flash. Active low.*/
-#define SPI_FCS_CRC_EN  (BIT(10))
-#define SPI_FCS_CRC_EN_M  (BIT(10))
-#define SPI_FCS_CRC_EN_V  0x1
-#define SPI_FCS_CRC_EN_S  10
-
-#define SPI_CTRL1_REG(i)          (REG_SPI_BASE(i) + 0xC)
-/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */
-/*description: SPI cs signal is delayed by spi clock cycles*/
-#define SPI_CS_HOLD_DELAY  0x0000000F
-#define SPI_CS_HOLD_DELAY_M  ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S))
-#define SPI_CS_HOLD_DELAY_V  0xF
-#define SPI_CS_HOLD_DELAY_S  28
-/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */
-/*description: Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
-#define SPI_CS_HOLD_DELAY_RES  0x00000FFF
-#define SPI_CS_HOLD_DELAY_RES_M  ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S))
-#define SPI_CS_HOLD_DELAY_RES_V  0xFFF
-#define SPI_CS_HOLD_DELAY_RES_S  16
-
-#define SPI_RD_STATUS_REG(i)          (REG_SPI_BASE(i) + 0x10)
-/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */
-/*description: In the slave mode,it is the status for master to read out.*/
-#define SPI_STATUS_EXT  0x000000FF
-#define SPI_STATUS_EXT_M  ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S))
-#define SPI_STATUS_EXT_V  0xFF
-#define SPI_STATUS_EXT_S  24
-/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
-/*description: Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/
-#define SPI_WB_MODE  0x000000FF
-#define SPI_WB_MODE_M  ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S))
-#define SPI_WB_MODE_V  0xFF
-#define SPI_WB_MODE_S  16
-/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: In the slave mode, it is the status for master to read out.*/
-#define SPI_STATUS  0x0000FFFF
-#define SPI_STATUS_M  ((SPI_STATUS_V)<<(SPI_STATUS_S))
-#define SPI_STATUS_V  0xFFFF
-#define SPI_STATUS_S  0
-
-#define SPI_CTRL2_REG(i)          (REG_SPI_BASE(i) + 0x14)
-/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: spi_cs signal is delayed by system clock cycles*/
-#define SPI_CS_DELAY_NUM  0x0000000F
-#define SPI_CS_DELAY_NUM_M  ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S))
-#define SPI_CS_DELAY_NUM_V  0xF
-#define SPI_CS_DELAY_NUM_S  28
-/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
-/*description: spi_cs signal is delayed by spi_clk . 0: zero  1: if spi_ck_out_edge
- or spi_ck_i_edge is set 1  delayed by half cycle    else delayed by one cycle  2: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by one cycle   else delayed by half cycle  3: delayed one cycle*/
-#define SPI_CS_DELAY_MODE  0x00000003
-#define SPI_CS_DELAY_MODE_M  ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S))
-#define SPI_CS_DELAY_MODE_V  0x3
-#define SPI_CS_DELAY_MODE_S  26
-/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */
-/*description: MOSI signals are delayed by system clock cycles*/
-#define SPI_MOSI_DELAY_NUM  0x00000007
-#define SPI_MOSI_DELAY_NUM_M  ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S))
-#define SPI_MOSI_DELAY_NUM_V  0x7
-#define SPI_MOSI_DELAY_NUM_S  23
-/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */
-/*description: MOSI signals are delayed by spi_clk. 0: zero  1: if spi_ck_out_edge
- or spi_ck_i_edge is set 1  delayed by half cycle    else delayed by one cycle  2: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by one cycle  else delayed by half cycle  3: delayed one cycle*/
-#define SPI_MOSI_DELAY_MODE  0x00000003
-#define SPI_MOSI_DELAY_MODE_M  ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S))
-#define SPI_MOSI_DELAY_MODE_V  0x3
-#define SPI_MOSI_DELAY_MODE_S  21
-/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: MISO signals are delayed by system clock cycles*/
-#define SPI_MISO_DELAY_NUM  0x00000007
-#define SPI_MISO_DELAY_NUM_M  ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S))
-#define SPI_MISO_DELAY_NUM_V  0x7
-#define SPI_MISO_DELAY_NUM_S  18
-/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: MISO signals are delayed by spi_clk. 0: zero  1: if spi_ck_out_edge
- or spi_ck_i_edge is set 1  delayed by half cycle    else delayed by one cycle  2: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by one cycle  else delayed by half cycle  3: delayed one cycle*/
-#define SPI_MISO_DELAY_MODE  0x00000003
-#define SPI_MISO_DELAY_MODE_M  ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S))
-#define SPI_MISO_DELAY_MODE_V  0x3
-#define SPI_MISO_DELAY_MODE_S  16
-/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */
-/*description: modify spi clock duty ratio when the value is lager than 8,
- the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/
-#define SPI_CK_OUT_HIGH_MODE  0x0000000F
-#define SPI_CK_OUT_HIGH_MODE_M  ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S))
-#define SPI_CK_OUT_HIGH_MODE_V  0xF
-#define SPI_CK_OUT_HIGH_MODE_S  12
-/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
-/*description: modify spi clock duty ratio when the value is lager than 8,
- the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/
-#define SPI_CK_OUT_LOW_MODE  0x0000000F
-#define SPI_CK_OUT_LOW_MODE_M  ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S))
-#define SPI_CK_OUT_LOW_MODE_V  0xF
-#define SPI_CK_OUT_LOW_MODE_S  8
-/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */
-/*description: delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/
-#define SPI_HOLD_TIME  0x0000000F
-#define SPI_HOLD_TIME_M  ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S))
-#define SPI_HOLD_TIME_V  0xF
-#define SPI_HOLD_TIME_S  4
-/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */
-/*description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined
- with spi_cs_setup bit.*/
-#define SPI_SETUP_TIME  0x0000000F
-#define SPI_SETUP_TIME_M  ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S))
-#define SPI_SETUP_TIME_V  0xF
-#define SPI_SETUP_TIME_S  0
-
-#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0x18)
-/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is
- divided from system clock.*/
-#define SPI_CLK_EQU_SYSCLK  (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_V  0x1
-#define SPI_CLK_EQU_SYSCLK_S  31
-/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */
-/*description: In the master mode it is pre-divider of spi_clk.*/
-#define SPI_CLKDIV_PRE  0x00001FFF
-#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
-#define SPI_CLKDIV_PRE_V  0x1FFF
-#define SPI_CLKDIV_PRE_S  18
-/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
-/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency
- is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
-#define SPI_CLKCNT_N  0x0000003F
-#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
-#define SPI_CLKCNT_N_V  0x3F
-#define SPI_CLKCNT_N_S  12
-/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
-/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In
- the slave mode it must be 0.*/
-#define SPI_CLKCNT_H  0x0000003F
-#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
-#define SPI_CLKCNT_H_V  0x3F
-#define SPI_CLKCNT_H_S  6
-/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
-/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave
- mode it must be 0.*/
-#define SPI_CLKCNT_L  0x0000003F
-#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
-#define SPI_CLKCNT_L_V  0x3F
-#define SPI_CLKCNT_L_S  0
-
-#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x1C)
-/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the command phase of an operation.*/
-#define SPI_USR_COMMAND  (BIT(31))
-#define SPI_USR_COMMAND_M  (BIT(31))
-#define SPI_USR_COMMAND_V  0x1
-#define SPI_USR_COMMAND_S  31
-/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the address phase of an operation.*/
-#define SPI_USR_ADDR  (BIT(30))
-#define SPI_USR_ADDR_M  (BIT(30))
-#define SPI_USR_ADDR_V  0x1
-#define SPI_USR_ADDR_S  30
-/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation.*/
-#define SPI_USR_DUMMY  (BIT(29))
-#define SPI_USR_DUMMY_M  (BIT(29))
-#define SPI_USR_DUMMY_V  0x1
-#define SPI_USR_DUMMY_S  29
-/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the read-data phase of an operation.*/
-#define SPI_USR_MISO  (BIT(28))
-#define SPI_USR_MISO_M  (BIT(28))
-#define SPI_USR_MISO_V  0x1
-#define SPI_USR_MISO_S  28
-/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the write-data phase of an operation.*/
-#define SPI_USR_MOSI  (BIT(27))
-#define SPI_USR_MOSI_M  (BIT(27))
-#define SPI_USR_MOSI_V  0x1
-#define SPI_USR_MOSI_S  27
-/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable.*/
-#define SPI_USR_DUMMY_IDLE  (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_USR_DUMMY_IDLE_V  0x1
-#define SPI_USR_DUMMY_IDLE_S  26
-/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15.
- 1: enable 0: disable.*/
-#define SPI_USR_MOSI_HIGHPART  (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_V  0x1
-#define SPI_USR_MOSI_HIGHPART_S  25
-/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15.
- 1: enable 0: disable.*/
-#define SPI_USR_MISO_HIGHPART  (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_USR_MISO_HIGHPART_V  0x1
-#define SPI_USR_MISO_HIGHPART_S  24
-/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: spi is hold at prepare state  the bit combined with spi_usr_hold_pol bit.*/
-#define SPI_USR_PREP_HOLD  (BIT(23))
-#define SPI_USR_PREP_HOLD_M  (BIT(23))
-#define SPI_USR_PREP_HOLD_V  0x1
-#define SPI_USR_PREP_HOLD_S  23
-/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: spi is hold at command state  the bit combined with spi_usr_hold_pol bit.*/
-#define SPI_USR_CMD_HOLD  (BIT(22))
-#define SPI_USR_CMD_HOLD_M  (BIT(22))
-#define SPI_USR_CMD_HOLD_V  0x1
-#define SPI_USR_CMD_HOLD_S  22
-/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: spi is hold at address state  the bit combined with spi_usr_hold_pol bit.*/
-#define SPI_USR_ADDR_HOLD  (BIT(21))
-#define SPI_USR_ADDR_HOLD_M  (BIT(21))
-#define SPI_USR_ADDR_HOLD_V  0x1
-#define SPI_USR_ADDR_HOLD_S  21
-/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: spi is hold at dummy state  the bit combined with spi_usr_hold_pol bit.*/
-#define SPI_USR_DUMMY_HOLD  (BIT(20))
-#define SPI_USR_DUMMY_HOLD_M  (BIT(20))
-#define SPI_USR_DUMMY_HOLD_V  0x1
-#define SPI_USR_DUMMY_HOLD_S  20
-/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: spi is hold at data in state  the bit combined with spi_usr_hold_pol bit.*/
-#define SPI_USR_DIN_HOLD  (BIT(19))
-#define SPI_USR_DIN_HOLD_M  (BIT(19))
-#define SPI_USR_DIN_HOLD_V  0x1
-#define SPI_USR_DIN_HOLD_S  19
-/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: spi is hold at data out state  the bit combined with spi_usr_hold_pol bit.*/
-#define SPI_USR_DOUT_HOLD  (BIT(18))
-#define SPI_USR_DOUT_HOLD_M  (BIT(18))
-#define SPI_USR_DOUT_HOLD_V  0x1
-#define SPI_USR_DOUT_HOLD_S  18
-/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: It is combined with hold bits to set the polarity of spi hold
- line  1: spi will be held when spi hold line is high  0: spi will be held when spi hold line is low*/
-#define SPI_USR_HOLD_POL  (BIT(17))
-#define SPI_USR_HOLD_POL_M  (BIT(17))
-#define SPI_USR_HOLD_POL_V  0x1
-#define SPI_USR_HOLD_POL_S  17
-/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set the bit to enable 3-line half duplex communication  mosi
- and miso signals share the same pin. 1: enable 0: disable.*/
-#define SPI_SIO  (BIT(16))
-#define SPI_SIO_M  (BIT(16))
-#define SPI_SIO_V  0x1
-#define SPI_SIO_S  16
-/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 4 signals.*/
-#define SPI_FWRITE_QIO  (BIT(15))
-#define SPI_FWRITE_QIO_M  (BIT(15))
-#define SPI_FWRITE_QIO_V  0x1
-#define SPI_FWRITE_QIO_S  15
-/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 2 signals.*/
-#define SPI_FWRITE_DIO  (BIT(14))
-#define SPI_FWRITE_DIO_M  (BIT(14))
-#define SPI_FWRITE_DIO_V  0x1
-#define SPI_FWRITE_DIO_S  14
-/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 4 signals*/
-#define SPI_FWRITE_QUAD  (BIT(13))
-#define SPI_FWRITE_QUAD_M  (BIT(13))
-#define SPI_FWRITE_QUAD_V  0x1
-#define SPI_FWRITE_QUAD_S  13
-/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 2 signals*/
-#define SPI_FWRITE_DUAL  (BIT(12))
-#define SPI_FWRITE_DUAL_M  (BIT(12))
-#define SPI_FWRITE_DUAL_V  0x1
-#define SPI_FWRITE_DUAL_S  12
-/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
-#define SPI_WR_BYTE_ORDER  (BIT(11))
-#define SPI_WR_BYTE_ORDER_M  (BIT(11))
-#define SPI_WR_BYTE_ORDER_V  0x1
-#define SPI_WR_BYTE_ORDER_S  11
-/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/
-#define SPI_RD_BYTE_ORDER  (BIT(10))
-#define SPI_RD_BYTE_ORDER_M  (BIT(10))
-#define SPI_RD_BYTE_ORDER_V  0x1
-#define SPI_RD_BYTE_ORDER_S  10
-/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
-#define SPI_CK_OUT_EDGE  (BIT(7))
-#define SPI_CK_OUT_EDGE_M  (BIT(7))
-#define SPI_CK_OUT_EDGE_V  0x1
-#define SPI_CK_OUT_EDGE_S  7
-/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: In the slave mode  the bit is same as spi_ck_out_edge in master
- mode. It is combined with  spi_miso_delay_mode bits.*/
-#define SPI_CK_I_EDGE  (BIT(6))
-#define SPI_CK_I_EDGE_M  (BIT(6))
-#define SPI_CK_I_EDGE_V  0x1
-#define SPI_CK_I_EDGE_S  6
-/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable.*/
-#define SPI_CS_SETUP  (BIT(5))
-#define SPI_CS_SETUP_M  (BIT(5))
-#define SPI_CS_SETUP_V  0x1
-#define SPI_CS_SETUP_S  5
-/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable.*/
-#define SPI_CS_HOLD  (BIT(4))
-#define SPI_CS_HOLD_M  (BIT(4))
-#define SPI_CS_HOLD_V  0x1
-#define SPI_CS_HOLD_S  4
-/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/
-#define SPI_DOUTDIN  (BIT(0))
-#define SPI_DOUTDIN_M  (BIT(0))
-#define SPI_DOUTDIN_V  0x1
-#define SPI_DOUTDIN_S  0
-
-#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x20)
-/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/
-#define SPI_USR_ADDR_BITLEN  0x0000003F
-#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
-#define SPI_USR_ADDR_BITLEN_V  0x3F
-#define SPI_USR_ADDR_BITLEN_S  26
-/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
-/*description: The length in spi_clk cycles of dummy phase. The register value
- shall be (cycle_num-1).*/
-#define SPI_USR_DUMMY_CYCLELEN  0x000000FF
-#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
-#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
-#define SPI_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x24)
-/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/
-#define SPI_USR_COMMAND_BITLEN  0x0000000F
-#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
-#define SPI_USR_COMMAND_BITLEN_V  0xF
-#define SPI_USR_COMMAND_BITLEN_S  28
-/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command.*/
-#define SPI_USR_COMMAND_VALUE  0x0000FFFF
-#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
-#define SPI_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_USR_COMMAND_VALUE_S  0
-
-#define SPI_MOSI_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x28)
-/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/
-#define SPI_USR_MOSI_DBITLEN  0x00FFFFFF
-#define SPI_USR_MOSI_DBITLEN_M  ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S))
-#define SPI_USR_MOSI_DBITLEN_V  0xFFFFFF
-#define SPI_USR_MOSI_DBITLEN_S  0
-
-#define SPI_MISO_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x2C)
-/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: The length in bits of  read-data. The register value shall be (bit_num-1).*/
-#define SPI_USR_MISO_DBITLEN  0x00FFFFFF
-#define SPI_USR_MISO_DBITLEN_M  ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S))
-#define SPI_USR_MISO_DBITLEN_V  0xFFFFFF
-#define SPI_USR_MISO_DBITLEN_S  0
-
-#define SPI_SLV_WR_STATUS_REG(i)          (REG_SPI_BASE(i) + 0x30)
-/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: In the slave mode this register are the status register for the
- master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/
-#define SPI_SLV_WR_ST  0xFFFFFFFF
-#define SPI_SLV_WR_ST_M  ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S))
-#define SPI_SLV_WR_ST_V  0xFFFFFFFF
-#define SPI_SLV_WR_ST_S  0
-
-#define SPI_PIN_REG(i)          (REG_SPI_BASE(i) + 0x34)
-/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: spi cs line keep low when the bit is set.*/
-#define SPI_CS_KEEP_ACTIVE  (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_V  0x1
-#define SPI_CS_KEEP_ACTIVE_S  30
-/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle*/
-#define SPI_CK_IDLE_EDGE  (BIT(29))
-#define SPI_CK_IDLE_EDGE_M  (BIT(29))
-#define SPI_CK_IDLE_EDGE_V  0x1
-#define SPI_CK_IDLE_EDGE_S  29
-/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */
-/*description: In the master mode  spi cs line is enable as spi clk  it is combined
- with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/
-#define SPI_MASTER_CK_SEL  0x00000007
-#define SPI_MASTER_CK_SEL_M  ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S))
-#define SPI_MASTER_CK_SEL_V  0x07
-#define SPI_MASTER_CK_SEL_S  11
-/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */
-/*description: In the master mode  the bits are the polarity of spi cs line
-  the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
-#define SPI_MASTER_CS_POL  0x00000007
-#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
-#define SPI_MASTER_CS_POL_V  0x7
-#define SPI_MASTER_CS_POL_S  6
-/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: 1: spi clk out disable  0: spi clk out enable*/
-#define SPI_CK_DIS  (BIT(5))
-#define SPI_CK_DIS_M  (BIT(5))
-#define SPI_CK_DIS_V  0x1
-#define SPI_CK_DIS_S  5
-/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/
-#define SPI_CS2_DIS  (BIT(2))
-#define SPI_CS2_DIS_M  (BIT(2))
-#define SPI_CS2_DIS_V  0x1
-#define SPI_CS2_DIS_S  2
-/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/
-#define SPI_CS1_DIS  (BIT(1))
-#define SPI_CS1_DIS_M  (BIT(1))
-#define SPI_CS1_DIS_V  0x1
-#define SPI_CS1_DIS_S  1
-/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/
-#define SPI_CS0_DIS  (BIT(0))
-#define SPI_CS0_DIS_M  (BIT(0))
-#define SPI_CS0_DIS_V  0x1
-#define SPI_CS0_DIS_S  0
-
-#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0x38)
-/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Software reset enable, reset the spi clock line cs line and data lines.*/
-#define SPI_SYNC_RESET  (BIT(31))
-#define SPI_SYNC_RESET_M  (BIT(31))
-#define SPI_SYNC_RESET_V  0x1
-#define SPI_SYNC_RESET_S  31
-/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 1: slave mode 0: master mode.*/
-#define SPI_SLAVE_MODE  (BIT(30))
-#define SPI_SLAVE_MODE_M  (BIT(30))
-#define SPI_SLAVE_MODE_V  0x1
-#define SPI_SLAVE_MODE_S  30
-/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: write and read buffer enable in the slave mode*/
-#define SPI_SLV_WR_RD_BUF_EN  (BIT(29))
-#define SPI_SLV_WR_RD_BUF_EN_M  (BIT(29))
-#define SPI_SLV_WR_RD_BUF_EN_V  0x1
-#define SPI_SLV_WR_RD_BUF_EN_S  29
-/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: write and read status enable  in the slave mode*/
-#define SPI_SLV_WR_RD_STA_EN  (BIT(28))
-#define SPI_SLV_WR_RD_STA_EN_M  (BIT(28))
-#define SPI_SLV_WR_RD_STA_EN_V  0x1
-#define SPI_SLV_WR_RD_STA_EN_S  28
-/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: 1: slave mode commands are defined in SPI_SLAVE3.  0: slave mode
- commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/
-#define SPI_SLV_CMD_DEFINE  (BIT(27))
-#define SPI_SLV_CMD_DEFINE_M  (BIT(27))
-#define SPI_SLV_CMD_DEFINE_V  0x1
-#define SPI_SLV_CMD_DEFINE_S  27
-/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */
-/*description: The operations counter in both the master mode and the slave
- mode. 4: read-status*/
-#define SPI_TRANS_CNT  0x0000000F
-#define SPI_TRANS_CNT_M  ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S))
-#define SPI_TRANS_CNT_V  0xF
-#define SPI_TRANS_CNT_S  23
-/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
-/*description: In the slave mode it is the state of spi state machine.*/
-#define SPI_SLV_LAST_STATE  0x00000007
-#define SPI_SLV_LAST_STATE_M  ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S))
-#define SPI_SLV_LAST_STATE_V  0x7
-#define SPI_SLV_LAST_STATE_S  20
-/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */
-/*description: In the slave mode it is the value of command.*/
-#define SPI_SLV_LAST_COMMAND  0x00000007
-#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
-#define SPI_SLV_LAST_COMMAND_V  0x7
-#define SPI_SLV_LAST_COMMAND_S  17
-/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: In the slave mode  this bits used to synchronize the input spi
- cs signal and eliminate spi cs  jitter.*/
-#define SPI_CS_I_MODE  0x00000003
-#define SPI_CS_I_MODE_M  ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S))
-#define SPI_CS_I_MODE_V  0x3
-#define SPI_CS_I_MODE_S  10
-/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */
-/*description: Interrupt enable bits for the below 5 sources*/
-#define SPI_INT_EN  0x0000001F
-#define SPI_INT_EN_M  ((SPI_INT_EN_V)<<(SPI_INT_EN_S))
-#define SPI_INT_EN_V  0x1F
-#define SPI_INT_EN_S  5
-/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for the completion of any operation in
- both the master mode and the slave mode.*/
-#define SPI_TRANS_DONE  (BIT(4))
-#define SPI_TRANS_DONE_M  (BIT(4))
-#define SPI_TRANS_DONE_V  0x1
-#define SPI_TRANS_DONE_S  4
-/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for the completion of write-status operation
- in the slave mode.*/
-#define SPI_SLV_WR_STA_DONE  (BIT(3))
-#define SPI_SLV_WR_STA_DONE_M  (BIT(3))
-#define SPI_SLV_WR_STA_DONE_V  0x1
-#define SPI_SLV_WR_STA_DONE_S  3
-/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for the completion of read-status operation
- in the slave mode.*/
-#define SPI_SLV_RD_STA_DONE  (BIT(2))
-#define SPI_SLV_RD_STA_DONE_M  (BIT(2))
-#define SPI_SLV_RD_STA_DONE_V  0x1
-#define SPI_SLV_RD_STA_DONE_S  2
-/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for the completion of write-buffer operation
- in the slave mode.*/
-#define SPI_SLV_WR_BUF_DONE  (BIT(1))
-#define SPI_SLV_WR_BUF_DONE_M  (BIT(1))
-#define SPI_SLV_WR_BUF_DONE_V  0x1
-#define SPI_SLV_WR_BUF_DONE_S  1
-/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt raw bit for the completion of read-buffer operation
- in the slave mode.*/
-#define SPI_SLV_RD_BUF_DONE  (BIT(0))
-#define SPI_SLV_RD_BUF_DONE_M  (BIT(0))
-#define SPI_SLV_RD_BUF_DONE_V  0x1
-#define SPI_SLV_RD_BUF_DONE_S  0
-
-#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0x3C)
-/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */
-/*description: In the slave mode it is the length of status bit.*/
-#define SPI_SLV_STATUS_BITLEN  0x0000001F
-#define SPI_SLV_STATUS_BITLEN_M  ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S))
-#define SPI_SLV_STATUS_BITLEN_V  0x1F
-#define SPI_SLV_STATUS_BITLEN_S  27
-/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: In the slave mode enable fast read status.*/
-#define SPI_SLV_STATUS_FAST_EN  (BIT(26))
-#define SPI_SLV_STATUS_FAST_EN_M  (BIT(26))
-#define SPI_SLV_STATUS_FAST_EN_V  0x1
-#define SPI_SLV_STATUS_FAST_EN_S  26
-/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: In the slave mode  1:read register of SPI_SLV_WR_STATUS  0: read
- register of SPI_RD_STATUS.*/
-#define SPI_SLV_STATUS_READBACK  (BIT(25))
-#define SPI_SLV_STATUS_READBACK_M  (BIT(25))
-#define SPI_SLV_STATUS_READBACK_V  0x1
-#define SPI_SLV_STATUS_READBACK_S  25
-/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
-/*description: In the slave mode it is the address length in bits for read-buffer
- operation. The register value shall be (bit_num-1).*/
-#define SPI_SLV_RD_ADDR_BITLEN  0x0000003F
-#define SPI_SLV_RD_ADDR_BITLEN_M  ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S))
-#define SPI_SLV_RD_ADDR_BITLEN_V  0x3F
-#define SPI_SLV_RD_ADDR_BITLEN_S  10
-/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */
-/*description: In the slave mode it is the address length in bits for write-buffer
- operation. The register value shall be (bit_num-1).*/
-#define SPI_SLV_WR_ADDR_BITLEN  0x0000003F
-#define SPI_SLV_WR_ADDR_BITLEN_M  ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S))
-#define SPI_SLV_WR_ADDR_BITLEN_V  0x3F
-#define SPI_SLV_WR_ADDR_BITLEN_S  4
-/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: In the slave mode it is the enable bit of dummy phase for write-status
- operations.*/
-#define SPI_SLV_WRSTA_DUMMY_EN  (BIT(3))
-#define SPI_SLV_WRSTA_DUMMY_EN_M  (BIT(3))
-#define SPI_SLV_WRSTA_DUMMY_EN_V  0x1
-#define SPI_SLV_WRSTA_DUMMY_EN_S  3
-/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: In the slave mode it is the enable bit of dummy phase for read-status
- operations.*/
-#define SPI_SLV_RDSTA_DUMMY_EN  (BIT(2))
-#define SPI_SLV_RDSTA_DUMMY_EN_M  (BIT(2))
-#define SPI_SLV_RDSTA_DUMMY_EN_V  0x1
-#define SPI_SLV_RDSTA_DUMMY_EN_S  2
-/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: In the slave mode it is the enable bit of dummy phase for write-buffer
- operations.*/
-#define SPI_SLV_WRBUF_DUMMY_EN  (BIT(1))
-#define SPI_SLV_WRBUF_DUMMY_EN_M  (BIT(1))
-#define SPI_SLV_WRBUF_DUMMY_EN_V  0x1
-#define SPI_SLV_WRBUF_DUMMY_EN_S  1
-/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: In the slave mode it is the enable bit of dummy phase for read-buffer
- operations.*/
-#define SPI_SLV_RDBUF_DUMMY_EN  (BIT(0))
-#define SPI_SLV_RDBUF_DUMMY_EN_M  (BIT(0))
-#define SPI_SLV_RDBUF_DUMMY_EN_V  0x1
-#define SPI_SLV_RDBUF_DUMMY_EN_S  0
-
-#define SPI_SLAVE2_REG(i)          (REG_SPI_BASE(i) + 0x40)
-/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */
-/*description: In the slave mode it is the length in spi_clk cycles of dummy
- phase for write-buffer operations. The register value shall be (cycle_num-1).*/
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN  0x000000FF
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M  ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S))
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V  0xFF
-#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S  24
-/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
-/*description: In the slave mode it is the length in spi_clk cycles of dummy
- phase for read-buffer operations. The register value shall be (cycle_num-1).*/
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN  0x000000FF
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M  ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S))
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V  0xFF
-#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S  16
-/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: In the slave mode it is the length in spi_clk cycles of dummy
- phase for write-status operations. The register value shall be (cycle_num-1).*/
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN  0x000000FF
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M  ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S))
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V  0xFF
-#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S  8
-/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: In the slave mode it is the length in spi_clk cycles of dummy
- phase for read-status operations. The register value shall be (cycle_num-1).*/
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN  0x000000FF
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M  ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S))
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V  0xFF
-#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S  0
-
-#define SPI_SLAVE3_REG(i)          (REG_SPI_BASE(i) + 0x44)
-/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */
-/*description: In the slave mode it is the value of write-status command.*/
-#define SPI_SLV_WRSTA_CMD_VALUE  0x000000FF
-#define SPI_SLV_WRSTA_CMD_VALUE_M  ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S))
-#define SPI_SLV_WRSTA_CMD_VALUE_V  0xFF
-#define SPI_SLV_WRSTA_CMD_VALUE_S  24
-/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */
-/*description: In the slave mode it is the value of read-status command.*/
-#define SPI_SLV_RDSTA_CMD_VALUE  0x000000FF
-#define SPI_SLV_RDSTA_CMD_VALUE_M  ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S))
-#define SPI_SLV_RDSTA_CMD_VALUE_V  0xFF
-#define SPI_SLV_RDSTA_CMD_VALUE_S  16
-/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
-/*description: In the slave mode it is the value of write-buffer command.*/
-#define SPI_SLV_WRBUF_CMD_VALUE  0x000000FF
-#define SPI_SLV_WRBUF_CMD_VALUE_M  ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S))
-#define SPI_SLV_WRBUF_CMD_VALUE_V  0xFF
-#define SPI_SLV_WRBUF_CMD_VALUE_S  8
-/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: In the slave mode it is the value of read-buffer command.*/
-#define SPI_SLV_RDBUF_CMD_VALUE  0x000000FF
-#define SPI_SLV_RDBUF_CMD_VALUE_M  ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S))
-#define SPI_SLV_RDBUF_CMD_VALUE_V  0xFF
-#define SPI_SLV_RDBUF_CMD_VALUE_S  0
-
-#define SPI_SLV_WRBUF_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x48)
-/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: In the slave mode it is the length in bits for write-buffer operations.
- The register value shall be (bit_num-1).*/
-#define SPI_SLV_WRBUF_DBITLEN  0x00FFFFFF
-#define SPI_SLV_WRBUF_DBITLEN_M  ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S))
-#define SPI_SLV_WRBUF_DBITLEN_V  0xFFFFFF
-#define SPI_SLV_WRBUF_DBITLEN_S  0
-
-#define SPI_SLV_RDBUF_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x4C)
-/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: In the slave mode it is the length in bits for read-buffer operations.
- The register value shall be (bit_num-1).*/
-#define SPI_SLV_RDBUF_DBITLEN  0x00FFFFFF
-#define SPI_SLV_RDBUF_DBITLEN_M  ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S))
-#define SPI_SLV_RDBUF_DBITLEN_V  0xFFFFFF
-#define SPI_SLV_RDBUF_DBITLEN_S  0
-
-#define SPI_CACHE_FCTRL_REG(i)          (REG_SPI_BASE(i) + 0x50)
-/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0  spi1 send suspend command before cache read flash 
- 1: enable  0:disable.*/
-#define SPI_CACHE_FLASH_PES_EN  (BIT(3))
-#define SPI_CACHE_FLASH_PES_EN_M  (BIT(3))
-#define SPI_CACHE_FLASH_PES_EN_V  0x1
-#define SPI_CACHE_FLASH_PES_EN_S  3
-/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0  cache  read flash for user define command  1: enable  0:disable.*/
-#define SPI_CACHE_FLASH_USR_CMD  (BIT(2))
-#define SPI_CACHE_FLASH_USR_CMD_M  (BIT(2))
-#define SPI_CACHE_FLASH_USR_CMD_V  0x1
-#define SPI_CACHE_FLASH_USR_CMD_S  2
-/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0  cache  read flash with 4 bytes command  1: enable  0:disable.*/
-#define SPI_CACHE_USR_CMD_4BYTE  (BIT(1))
-#define SPI_CACHE_USR_CMD_4BYTE_M  (BIT(1))
-#define SPI_CACHE_USR_CMD_4BYTE_V  0x1
-#define SPI_CACHE_USR_CMD_4BYTE_S  1
-/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0  Cache access enable  1: enable  0:disable.*/
-#define SPI_CACHE_REQ_EN  (BIT(0))
-#define SPI_CACHE_REQ_EN_M  (BIT(0))
-#define SPI_CACHE_REQ_EN_V  0x1
-#define SPI_CACHE_REQ_EN_S  0
-
-#define SPI_CACHE_SCTRL_REG(i)          (REG_SPI_BASE(i) + 0x54)
-/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: For SPI0  In the spi sram mode cache write sram for user define command*/
-#define SPI_CACHE_SRAM_USR_WCMD  (BIT(28))
-#define SPI_CACHE_SRAM_USR_WCMD_M  (BIT(28))
-#define SPI_CACHE_SRAM_USR_WCMD_V  0x1
-#define SPI_CACHE_SRAM_USR_WCMD_S  28
-/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */
-/*description: For SPI0  In the sram mode  it is the length in bits of address
- phase. The register value shall be (bit_num-1).*/
-#define SPI_SRAM_ADDR_BITLEN  0x0000003F
-#define SPI_SRAM_ADDR_BITLEN_M  ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S))
-#define SPI_SRAM_ADDR_BITLEN_V  0x3F
-#define SPI_SRAM_ADDR_BITLEN_S  22
-/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */
-/*description: For SPI0  In the sram mode  it is the length in bits of address
- phase. The register value shall be (bit_num-1).*/
-#define SPI_SRAM_DUMMY_CYCLELEN  0x000000FF
-#define SPI_SRAM_DUMMY_CYCLELEN_M  ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S))
-#define SPI_SRAM_DUMMY_CYCLELEN_V  0xFF
-#define SPI_SRAM_DUMMY_CYCLELEN_S  14
-/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */
-/*description: For SPI0  In the sram mode  it is the byte length of spi read sram data.*/
-#define SPI_SRAM_BYTES_LEN  0x000000FF
-#define SPI_SRAM_BYTES_LEN_M  ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S))
-#define SPI_SRAM_BYTES_LEN_V  0xFF
-#define SPI_SRAM_BYTES_LEN_S  6
-/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: For SPI0  In the spi sram mode cache read sram for user define command.*/
-#define SPI_CACHE_SRAM_USR_RCMD  (BIT(5))
-#define SPI_CACHE_SRAM_USR_RCMD_M  (BIT(5))
-#define SPI_CACHE_SRAM_USR_RCMD_V  0x1
-#define SPI_CACHE_SRAM_USR_RCMD_S  5
-/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: For SPI0  In the spi sram mode  it is the enable bit of dummy
- phase for read operations.*/
-#define SPI_USR_RD_SRAM_DUMMY  (BIT(4))
-#define SPI_USR_RD_SRAM_DUMMY_M  (BIT(4))
-#define SPI_USR_RD_SRAM_DUMMY_V  0x1
-#define SPI_USR_RD_SRAM_DUMMY_S  4
-/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0  In the spi sram mode  it is the enable bit of dummy
- phase for write operations.*/
-#define SPI_USR_WR_SRAM_DUMMY  (BIT(3))
-#define SPI_USR_WR_SRAM_DUMMY_M  (BIT(3))
-#define SPI_USR_WR_SRAM_DUMMY_V  0x1
-#define SPI_USR_WR_SRAM_DUMMY_S  3
-/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0  In the spi sram mode  spi quad I/O mode enable  1: enable  0:disable*/
-#define SPI_USR_SRAM_QIO  (BIT(2))
-#define SPI_USR_SRAM_QIO_M  (BIT(2))
-#define SPI_USR_SRAM_QIO_V  0x1
-#define SPI_USR_SRAM_QIO_S  2
-/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0  In the spi sram mode  spi dual I/O mode enable  1: enable  0:disable*/
-#define SPI_USR_SRAM_DIO  (BIT(1))
-#define SPI_USR_SRAM_DIO_M  (BIT(1))
-#define SPI_USR_SRAM_DIO_V  0x1
-#define SPI_USR_SRAM_DIO_S  1
-
-#define SPI_SRAM_CMD_REG(i)          (REG_SPI_BASE(i) + 0x58)
-/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation
- will be triggered when the bit is set. The bit will be cleared once the operation done*/
-#define SPI_SRAM_RSTIO  (BIT(4))
-#define SPI_SRAM_RSTIO_M  (BIT(4))
-#define SPI_SRAM_RSTIO_V  0x1
-#define SPI_SRAM_RSTIO_S  4
-/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0 SRAM QIO mode enable .  SRAM QIO enable command will
- be send when the bit is set. The bit will be cleared once the operation done.*/
-#define SPI_SRAM_QIO  (BIT(1))
-#define SPI_SRAM_QIO_M  (BIT(1))
-#define SPI_SRAM_QIO_V  0x1
-#define SPI_SRAM_QIO_S  1
-/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0 SRAM DIO mode enable .  SRAM DIO enable command will
- be send when the bit is set. The bit will be cleared once the operation done.*/
-#define SPI_SRAM_DIO  (BIT(0))
-#define SPI_SRAM_DIO_M  (BIT(0))
-#define SPI_SRAM_DIO_V  0x1
-#define SPI_SRAM_DIO_S  0
-
-#define SPI_SRAM_DRD_CMD_REG(i)          (REG_SPI_BASE(i) + 0x5C)
-/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0 When cache mode is enable it is the length in bits of
- command phase for SRAM. The register value shall be (bit_num-1).*/
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN  0x0000000F
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
-#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
-/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0 When cache mode is enable it is the read command value
- of command phase for SRAM.*/
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE  0x0000FFFF
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S))
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
-#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
-
-#define SPI_SRAM_DWR_CMD_REG(i)          (REG_SPI_BASE(i) + 0x60)
-/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0 When cache mode is enable it is the in bits of command
- phase  for SRAM. The register value shall be (bit_num-1).*/
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN  0x0000000F
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
-#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
-/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0 When cache mode is enable it is the write command value
- of command phase for SRAM.*/
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE  0x0000FFFF
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S))
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
-#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
-
-#define SPI_SLV_RD_BIT_REG(i)          (REG_SPI_BASE(i) + 0x64)
-/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: In the slave mode it is the bit length of read data. The value
- is the length - 1.*/
-#define SPI_SLV_RDATA_BIT  0x00FFFFFF
-#define SPI_SLV_RDATA_BIT_M  ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S))
-#define SPI_SLV_RDATA_BIT_V  0xFFFFFF
-#define SPI_SLV_RDATA_BIT_S  0
-
-#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x80)
-/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF0  0xFFFFFFFF
-#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
-#define SPI_BUF0_V  0xFFFFFFFF
-#define SPI_BUF0_S  0
-
-#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x84)
-/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF1  0xFFFFFFFF
-#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
-#define SPI_BUF1_V  0xFFFFFFFF
-#define SPI_BUF1_S  0
-
-#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0x88)
-/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF2  0xFFFFFFFF
-#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
-#define SPI_BUF2_V  0xFFFFFFFF
-#define SPI_BUF2_S  0
-
-#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0x8C)
-/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF3  0xFFFFFFFF
-#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
-#define SPI_BUF3_V  0xFFFFFFFF
-#define SPI_BUF3_S  0
-
-#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0x90)
-/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF4  0xFFFFFFFF
-#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
-#define SPI_BUF4_V  0xFFFFFFFF
-#define SPI_BUF4_S  0
-
-#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0x94)
-/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF5  0xFFFFFFFF
-#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
-#define SPI_BUF5_V  0xFFFFFFFF
-#define SPI_BUF5_S  0
-
-#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0x98)
-/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF6  0xFFFFFFFF
-#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
-#define SPI_BUF6_V  0xFFFFFFFF
-#define SPI_BUF6_S  0
-
-#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0x9C)
-/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF7  0xFFFFFFFF
-#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
-#define SPI_BUF7_V  0xFFFFFFFF
-#define SPI_BUF7_S  0
-
-#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0xA0)
-/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF8  0xFFFFFFFF
-#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
-#define SPI_BUF8_V  0xFFFFFFFF
-#define SPI_BUF8_S  0
-
-#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0xA4)
-/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF9  0xFFFFFFFF
-#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
-#define SPI_BUF9_V  0xFFFFFFFF
-#define SPI_BUF9_S  0
-
-#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0xA8)
-/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF10  0xFFFFFFFF
-#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
-#define SPI_BUF10_V  0xFFFFFFFF
-#define SPI_BUF10_S  0
-
-#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0xAC)
-/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF11  0xFFFFFFFF
-#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
-#define SPI_BUF11_V  0xFFFFFFFF
-#define SPI_BUF11_S  0
-
-#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0xB0)
-/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF12  0xFFFFFFFF
-#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
-#define SPI_BUF12_V  0xFFFFFFFF
-#define SPI_BUF12_S  0
-
-#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0xB4)
-/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF13  0xFFFFFFFF
-#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
-#define SPI_BUF13_V  0xFFFFFFFF
-#define SPI_BUF13_S  0
-
-#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0xB8)
-/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF14  0xFFFFFFFF
-#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
-#define SPI_BUF14_V  0xFFFFFFFF
-#define SPI_BUF14_S  0
-
-#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0xBC)
-/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_BUF15  0xFFFFFFFF
-#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
-#define SPI_BUF15_V  0xFFFFFFFF
-#define SPI_BUF15_S  0
-
-#define SPI_TX_CRC_REG(i)          (REG_SPI_BASE(i) + 0xC0)
-/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: For SPI1  the value of crc32 for 256 bits data.*/
-#define SPI_TX_CRC_DATA  0xFFFFFFFF
-#define SPI_TX_CRC_DATA_M  ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S))
-#define SPI_TX_CRC_DATA_V  0xFFFFFFFF
-#define SPI_TX_CRC_DATA_S  0
-
-#define SPI_EXT0_REG(i)          (REG_SPI_BASE(i) + 0xF0)
-/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: page program delay enable.*/
-#define SPI_T_PP_ENA  (BIT(31))
-#define SPI_T_PP_ENA_M  (BIT(31))
-#define SPI_T_PP_ENA_V  0x1
-#define SPI_T_PP_ENA_S  31
-/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */
-/*description: page program delay time shift .*/
-#define SPI_T_PP_SHIFT  0x0000000F
-#define SPI_T_PP_SHIFT_M  ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S))
-#define SPI_T_PP_SHIFT_V  0xF
-#define SPI_T_PP_SHIFT_S  16
-/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */
-/*description: page program delay time  by system clock.*/
-#define SPI_T_PP_TIME  0x00000FFF
-#define SPI_T_PP_TIME_M  ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S))
-#define SPI_T_PP_TIME_V  0xFFF
-#define SPI_T_PP_TIME_S  0
-
-#define SPI_EXT1_REG(i)          (REG_SPI_BASE(i) + 0xF4)
-/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: erase flash delay enable.*/
-#define SPI_T_ERASE_ENA  (BIT(31))
-#define SPI_T_ERASE_ENA_M  (BIT(31))
-#define SPI_T_ERASE_ENA_V  0x1
-#define SPI_T_ERASE_ENA_S  31
-/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */
-/*description: erase flash delay time shift.*/
-#define SPI_T_ERASE_SHIFT  0x0000000F
-#define SPI_T_ERASE_SHIFT_M  ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S))
-#define SPI_T_ERASE_SHIFT_V  0xF
-#define SPI_T_ERASE_SHIFT_S  16
-/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */
-/*description: erase flash delay time by system clock.*/
-#define SPI_T_ERASE_TIME  0x00000FFF
-#define SPI_T_ERASE_TIME_M  ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S))
-#define SPI_T_ERASE_TIME_V  0xFFF
-#define SPI_T_ERASE_TIME_S  0
-
-#define SPI_EXT2_REG(i)          (REG_SPI_BASE(i) + 0xF8)
-/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: The status of spi state machine .*/
-#define SPI_ST  0x00000007
-#define SPI_ST_M  ((SPI_ST_V)<<(SPI_ST_S))
-#define SPI_ST_V  0x7
-#define SPI_ST_S  0
-
-#define SPI_EXT3_REG(i)          (REG_SPI_BASE(i) + 0xFC)
-/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: This register is for two SPI masters to share the same cs clock
- and data signals. The bits of one SPI are set  if the other SPI is busy  the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase.*/
-#define SPI_INT_HOLD_ENA  0x00000003
-#define SPI_INT_HOLD_ENA_M  ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S))
-#define SPI_INT_HOLD_ENA_V  0x3
-#define SPI_INT_HOLD_ENA_S  0
-
-#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x100)
-/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: spi dma continue tx/rx data.*/
-#define SPI_DMA_CONTINUE  (BIT(16))
-#define SPI_DMA_CONTINUE_M  (BIT(16))
-#define SPI_DMA_CONTINUE_V  0x1
-#define SPI_DMA_CONTINUE_S  16
-/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: spi dma write data stop when in continue tx/rx mode.*/
-#define SPI_DMA_TX_STOP  (BIT(15))
-#define SPI_DMA_TX_STOP_M  (BIT(15))
-#define SPI_DMA_TX_STOP_V  0x1
-#define SPI_DMA_TX_STOP_S  15
-/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: spi dma read data stop  when in continue tx/rx mode.*/
-#define SPI_DMA_RX_STOP  (BIT(14))
-#define SPI_DMA_RX_STOP_M  (BIT(14))
-#define SPI_DMA_RX_STOP_V  0x1
-#define SPI_DMA_RX_STOP_S  14
-/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: spi dma read data from memory in burst mode.*/
-#define SPI_OUT_DATA_BURST_EN  (BIT(12))
-#define SPI_OUT_DATA_BURST_EN_M  (BIT(12))
-#define SPI_OUT_DATA_BURST_EN_V  0x1
-#define SPI_OUT_DATA_BURST_EN_S  12
-/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: read descriptor use burst mode when write data to memory.*/
-#define SPI_INDSCR_BURST_EN  (BIT(11))
-#define SPI_INDSCR_BURST_EN_M  (BIT(11))
-#define SPI_INDSCR_BURST_EN_V  0x1
-#define SPI_INDSCR_BURST_EN_S  11
-/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: read descriptor use burst mode when read data for memory.*/
-#define SPI_OUTDSCR_BURST_EN  (BIT(10))
-#define SPI_OUTDSCR_BURST_EN_M  (BIT(10))
-#define SPI_OUTDSCR_BURST_EN_V  0x1
-#define SPI_OUTDSCR_BURST_EN_S  10
-/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: out eof flag generation mode . 1: when dma pop all data from
- fifo  0:when ahb push all data to fifo.*/
-#define SPI_OUT_EOF_MODE  (BIT(9))
-#define SPI_OUT_EOF_MODE_M  (BIT(9))
-#define SPI_OUT_EOF_MODE_V  0x1
-#define SPI_OUT_EOF_MODE_S  9
-/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: when the link is empty   jump to next automatically.*/
-#define SPI_OUT_AUTO_WRBACK  (BIT(8))
-#define SPI_OUT_AUTO_WRBACK_M  (BIT(8))
-#define SPI_OUT_AUTO_WRBACK_V  0x1
-#define SPI_OUT_AUTO_WRBACK_S  8
-/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set bit to test out link.*/
-#define SPI_OUT_LOOP_TEST  (BIT(7))
-#define SPI_OUT_LOOP_TEST_M  (BIT(7))
-#define SPI_OUT_LOOP_TEST_V  0x1
-#define SPI_OUT_LOOP_TEST_S  7
-/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set bit to test in link.*/
-#define SPI_IN_LOOP_TEST  (BIT(6))
-#define SPI_IN_LOOP_TEST_M  (BIT(6))
-#define SPI_IN_LOOP_TEST_V  0x1
-#define SPI_IN_LOOP_TEST_S  6
-/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: reset spi dma ahb master.*/
-#define SPI_AHBM_RST  (BIT(5))
-#define SPI_AHBM_RST_M  (BIT(5))
-#define SPI_AHBM_RST_V  0x1
-#define SPI_AHBM_RST_S  5
-/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: reset spi dma ahb master fifo pointer.*/
-#define SPI_AHBM_FIFO_RST  (BIT(4))
-#define SPI_AHBM_FIFO_RST_M  (BIT(4))
-#define SPI_AHBM_FIFO_RST_V  0x1
-#define SPI_AHBM_FIFO_RST_S  4
-/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/
-#define SPI_OUT_RST  (BIT(3))
-#define SPI_OUT_RST_M  (BIT(3))
-#define SPI_OUT_RST_V  0x1
-#define SPI_OUT_RST_S  3
-/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/
-#define SPI_IN_RST  (BIT(2))
-#define SPI_IN_RST_M  (BIT(2))
-#define SPI_IN_RST_V  0x1
-#define SPI_IN_RST_S  2
-
-#define SPI_DMA_OUT_LINK_REG(i)          (REG_SPI_BASE(i) + 0x104)
-/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set the bit to mount on new outlink descriptors.*/
-#define SPI_OUTLINK_RESTART  (BIT(30))
-#define SPI_OUTLINK_RESTART_M  (BIT(30))
-#define SPI_OUTLINK_RESTART_V  0x1
-#define SPI_OUTLINK_RESTART_S  30
-/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set the bit to start to use outlink descriptor.*/
-#define SPI_OUTLINK_START  (BIT(29))
-#define SPI_OUTLINK_START_M  (BIT(29))
-#define SPI_OUTLINK_START_V  0x1
-#define SPI_OUTLINK_START_S  29
-/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set the bit to stop to use outlink descriptor.*/
-#define SPI_OUTLINK_STOP  (BIT(28))
-#define SPI_OUTLINK_STOP_M  (BIT(28))
-#define SPI_OUTLINK_STOP_V  0x1
-#define SPI_OUTLINK_STOP_S  28
-/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The address of the first outlink descriptor.*/
-#define SPI_OUTLINK_ADDR  0x000FFFFF
-#define SPI_OUTLINK_ADDR_M  ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S))
-#define SPI_OUTLINK_ADDR_V  0xFFFFF
-#define SPI_OUTLINK_ADDR_S  0
-
-#define SPI_DMA_IN_LINK_REG(i)          (REG_SPI_BASE(i) + 0x108)
-/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set the bit to mount on new inlink descriptors.*/
-#define SPI_INLINK_RESTART  (BIT(30))
-#define SPI_INLINK_RESTART_M  (BIT(30))
-#define SPI_INLINK_RESTART_V  0x1
-#define SPI_INLINK_RESTART_S  30
-/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set the bit to start to use inlink descriptor.*/
-#define SPI_INLINK_START  (BIT(29))
-#define SPI_INLINK_START_M  (BIT(29))
-#define SPI_INLINK_START_V  0x1
-#define SPI_INLINK_START_S  29
-/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set the bit to stop to use inlink descriptor.*/
-#define SPI_INLINK_STOP  (BIT(28))
-#define SPI_INLINK_STOP_M  (BIT(28))
-#define SPI_INLINK_STOP_V  0x1
-#define SPI_INLINK_STOP_S  28
-/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: when the bit is set  inlink descriptor returns to the next descriptor
- while a packet is wrong*/
-#define SPI_INLINK_AUTO_RET  (BIT(20))
-#define SPI_INLINK_AUTO_RET_M  (BIT(20))
-#define SPI_INLINK_AUTO_RET_V  0x1
-#define SPI_INLINK_AUTO_RET_S  20
-/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: The address of the first inlink descriptor.*/
-#define SPI_INLINK_ADDR  0x000FFFFF
-#define SPI_INLINK_ADDR_M  ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S))
-#define SPI_INLINK_ADDR_V  0xFFFFF
-#define SPI_INLINK_ADDR_S  0
-
-#define SPI_DMA_STATUS_REG(i)          (REG_SPI_BASE(i) + 0x10C)
-/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: spi dma write data status bit.*/
-#define SPI_DMA_TX_EN  (BIT(1))
-#define SPI_DMA_TX_EN_M  (BIT(1))
-#define SPI_DMA_TX_EN_V  0x1
-#define SPI_DMA_TX_EN_S  1
-/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: spi dma read data status bit.*/
-#define SPI_DMA_RX_EN  (BIT(0))
-#define SPI_DMA_RX_EN_M  (BIT(0))
-#define SPI_DMA_RX_EN_V  0x1
-#define SPI_DMA_RX_EN_S  0
-
-#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x110)
-/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for sending all the packets to host done.*/
-#define SPI_OUT_TOTAL_EOF_INT_ENA  (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_ENA_M  (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_ENA_V  0x1
-#define SPI_OUT_TOTAL_EOF_INT_ENA_S  8
-/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for sending a packet to host done.*/
-#define SPI_OUT_EOF_INT_ENA  (BIT(7))
-#define SPI_OUT_EOF_INT_ENA_M  (BIT(7))
-#define SPI_OUT_EOF_INT_ENA_V  0x1
-#define SPI_OUT_EOF_INT_ENA_S  7
-/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for completing usage of a outlink descriptor .*/
-#define SPI_OUT_DONE_INT_ENA  (BIT(6))
-#define SPI_OUT_DONE_INT_ENA_M  (BIT(6))
-#define SPI_OUT_DONE_INT_ENA_V  0x1
-#define SPI_OUT_DONE_INT_ENA_S  6
-/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for completing receiving all the packets from host.*/
-#define SPI_IN_SUC_EOF_INT_ENA  (BIT(5))
-#define SPI_IN_SUC_EOF_INT_ENA_M  (BIT(5))
-#define SPI_IN_SUC_EOF_INT_ENA_V  0x1
-#define SPI_IN_SUC_EOF_INT_ENA_S  5
-/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for receiving error.*/
-#define SPI_IN_ERR_EOF_INT_ENA  (BIT(4))
-#define SPI_IN_ERR_EOF_INT_ENA_M  (BIT(4))
-#define SPI_IN_ERR_EOF_INT_ENA_V  0x1
-#define SPI_IN_ERR_EOF_INT_ENA_S  4
-/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for completing usage of a inlink descriptor.*/
-#define SPI_IN_DONE_INT_ENA  (BIT(3))
-#define SPI_IN_DONE_INT_ENA_M  (BIT(3))
-#define SPI_IN_DONE_INT_ENA_V  0x1
-#define SPI_IN_DONE_INT_ENA_S  3
-/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for inlink descriptor error.*/
-#define SPI_INLINK_DSCR_ERROR_INT_ENA  (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_ENA_M  (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_ENA_V  0x1
-#define SPI_INLINK_DSCR_ERROR_INT_ENA_S  2
-/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for outlink descriptor error.*/
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA  (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M  (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V  0x1
-#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S  1
-/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for lack of enough inlink descriptors.*/
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA  (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M  (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V  0x1
-#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S  0
-
-#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x114)
-/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw bit for sending all the packets to host done.*/
-#define SPI_OUT_TOTAL_EOF_INT_RAW  (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_RAW_M  (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_RAW_V  0x1
-#define SPI_OUT_TOTAL_EOF_INT_RAW_S  8
-/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw bit for sending a packet to host done.*/
-#define SPI_OUT_EOF_INT_RAW  (BIT(7))
-#define SPI_OUT_EOF_INT_RAW_M  (BIT(7))
-#define SPI_OUT_EOF_INT_RAW_V  0x1
-#define SPI_OUT_EOF_INT_RAW_S  7
-/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit for completing usage of a outlink descriptor.*/
-#define SPI_OUT_DONE_INT_RAW  (BIT(6))
-#define SPI_OUT_DONE_INT_RAW_M  (BIT(6))
-#define SPI_OUT_DONE_INT_RAW_V  0x1
-#define SPI_OUT_DONE_INT_RAW_S  6
-/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for completing receiving all the packets from host.*/
-#define SPI_IN_SUC_EOF_INT_RAW  (BIT(5))
-#define SPI_IN_SUC_EOF_INT_RAW_M  (BIT(5))
-#define SPI_IN_SUC_EOF_INT_RAW_V  0x1
-#define SPI_IN_SUC_EOF_INT_RAW_S  5
-/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for receiving error.*/
-#define SPI_IN_ERR_EOF_INT_RAW  (BIT(4))
-#define SPI_IN_ERR_EOF_INT_RAW_M  (BIT(4))
-#define SPI_IN_ERR_EOF_INT_RAW_V  0x1
-#define SPI_IN_ERR_EOF_INT_RAW_S  4
-/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for completing usage of a inlink descriptor.*/
-#define SPI_IN_DONE_INT_RAW  (BIT(3))
-#define SPI_IN_DONE_INT_RAW_M  (BIT(3))
-#define SPI_IN_DONE_INT_RAW_V  0x1
-#define SPI_IN_DONE_INT_RAW_S  3
-/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for inlink descriptor error.*/
-#define SPI_INLINK_DSCR_ERROR_INT_RAW  (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_RAW_M  (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_RAW_V  0x1
-#define SPI_INLINK_DSCR_ERROR_INT_RAW_S  2
-/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit for outlink descriptor error.*/
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW  (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M  (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V  0x1
-#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S  1
-/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit for lack of enough inlink descriptors.*/
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW  (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M  (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V  0x1
-#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S  0
-
-#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x118)
-/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The status bit for sending all the packets to host done.*/
-#define SPI_OUT_TOTAL_EOF_INT_ST  (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_ST_M  (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_ST_V  0x1
-#define SPI_OUT_TOTAL_EOF_INT_ST_S  8
-/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The status bit for sending a packet to host done.*/
-#define SPI_OUT_EOF_INT_ST  (BIT(7))
-#define SPI_OUT_EOF_INT_ST_M  (BIT(7))
-#define SPI_OUT_EOF_INT_ST_V  0x1
-#define SPI_OUT_EOF_INT_ST_S  7
-/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The status bit for completing usage of a outlink descriptor.*/
-#define SPI_OUT_DONE_INT_ST  (BIT(6))
-#define SPI_OUT_DONE_INT_ST_M  (BIT(6))
-#define SPI_OUT_DONE_INT_ST_V  0x1
-#define SPI_OUT_DONE_INT_ST_S  6
-/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for completing receiving all the packets from host.*/
-#define SPI_IN_SUC_EOF_INT_ST  (BIT(5))
-#define SPI_IN_SUC_EOF_INT_ST_M  (BIT(5))
-#define SPI_IN_SUC_EOF_INT_ST_V  0x1
-#define SPI_IN_SUC_EOF_INT_ST_S  5
-/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for receiving error.*/
-#define SPI_IN_ERR_EOF_INT_ST  (BIT(4))
-#define SPI_IN_ERR_EOF_INT_ST_M  (BIT(4))
-#define SPI_IN_ERR_EOF_INT_ST_V  0x1
-#define SPI_IN_ERR_EOF_INT_ST_S  4
-/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for completing usage of a inlink descriptor.*/
-#define SPI_IN_DONE_INT_ST  (BIT(3))
-#define SPI_IN_DONE_INT_ST_M  (BIT(3))
-#define SPI_IN_DONE_INT_ST_V  0x1
-#define SPI_IN_DONE_INT_ST_S  3
-/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for inlink descriptor error.*/
-#define SPI_INLINK_DSCR_ERROR_INT_ST  (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_ST_M  (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_ST_V  0x1
-#define SPI_INLINK_DSCR_ERROR_INT_ST_S  2
-/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for outlink descriptor error.*/
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST  (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M  (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V  0x1
-#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S  1
-/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for lack of enough inlink descriptors.*/
-#define SPI_INLINK_DSCR_EMPTY_INT_ST  (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_ST_M  (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_ST_V  0x1
-#define SPI_INLINK_DSCR_EMPTY_INT_ST_S  0
-
-#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x11C)
-/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The clear bit for sending all the packets to host done.*/
-#define SPI_OUT_TOTAL_EOF_INT_CLR  (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_CLR_M  (BIT(8))
-#define SPI_OUT_TOTAL_EOF_INT_CLR_V  0x1
-#define SPI_OUT_TOTAL_EOF_INT_CLR_S  8
-/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The clear bit for sending a packet to host done.*/
-#define SPI_OUT_EOF_INT_CLR  (BIT(7))
-#define SPI_OUT_EOF_INT_CLR_M  (BIT(7))
-#define SPI_OUT_EOF_INT_CLR_V  0x1
-#define SPI_OUT_EOF_INT_CLR_S  7
-/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The clear bit for completing usage of a outlink descriptor.*/
-#define SPI_OUT_DONE_INT_CLR  (BIT(6))
-#define SPI_OUT_DONE_INT_CLR_M  (BIT(6))
-#define SPI_OUT_DONE_INT_CLR_V  0x1
-#define SPI_OUT_DONE_INT_CLR_S  6
-/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The clear bit for completing receiving all the packets from host.*/
-#define SPI_IN_SUC_EOF_INT_CLR  (BIT(5))
-#define SPI_IN_SUC_EOF_INT_CLR_M  (BIT(5))
-#define SPI_IN_SUC_EOF_INT_CLR_V  0x1
-#define SPI_IN_SUC_EOF_INT_CLR_S  5
-/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for receiving error.*/
-#define SPI_IN_ERR_EOF_INT_CLR  (BIT(4))
-#define SPI_IN_ERR_EOF_INT_CLR_M  (BIT(4))
-#define SPI_IN_ERR_EOF_INT_CLR_V  0x1
-#define SPI_IN_ERR_EOF_INT_CLR_S  4
-/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for completing usage of a inlink descriptor.*/
-#define SPI_IN_DONE_INT_CLR  (BIT(3))
-#define SPI_IN_DONE_INT_CLR_M  (BIT(3))
-#define SPI_IN_DONE_INT_CLR_V  0x1
-#define SPI_IN_DONE_INT_CLR_S  3
-/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for inlink descriptor error.*/
-#define SPI_INLINK_DSCR_ERROR_INT_CLR  (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_CLR_M  (BIT(2))
-#define SPI_INLINK_DSCR_ERROR_INT_CLR_V  0x1
-#define SPI_INLINK_DSCR_ERROR_INT_CLR_S  2
-/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for outlink descriptor error.*/
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR  (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M  (BIT(1))
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V  0x1
-#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S  1
-/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for lack of enough inlink descriptors.*/
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR  (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M  (BIT(0))
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V  0x1
-#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S  0
-
-#define SPI_IN_ERR_EOF_DES_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x120)
-/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The inlink descriptor address when spi dma produce receiving error.*/
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR  0xFFFFFFFF
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M  ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S))
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S  0
-
-#define SPI_IN_SUC_EOF_DES_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x124)
-/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR  0xFFFFFFFF
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M  ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S))
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S  0
-
-#define SPI_INLINK_DSCR_REG(i)          (REG_SPI_BASE(i) + 0x128)
-/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current in descriptor pointer.*/
-#define SPI_DMA_INLINK_DSCR  0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_M  ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S))
-#define SPI_DMA_INLINK_DSCR_V  0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_S  0
-
-#define SPI_INLINK_DSCR_BF0_REG(i)          (REG_SPI_BASE(i) + 0x12C)
-/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of next in descriptor pointer.*/
-#define SPI_DMA_INLINK_DSCR_BF0  0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_BF0_M  ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S))
-#define SPI_DMA_INLINK_DSCR_BF0_V  0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_BF0_S  0
-
-#define SPI_INLINK_DSCR_BF1_REG(i)          (REG_SPI_BASE(i) + 0x130)
-/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current in descriptor data buffer pointer.*/
-#define SPI_DMA_INLINK_DSCR_BF1  0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_BF1_M  ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S))
-#define SPI_DMA_INLINK_DSCR_BF1_V  0xFFFFFFFF
-#define SPI_DMA_INLINK_DSCR_BF1_S  0
-
-#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x134)
-/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The address of buffer relative to the outlink descriptor that produce eof.*/
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR  0xFFFFFFFF
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M  ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S))
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
-#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S  0
-
-#define SPI_OUT_EOF_DES_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x138)
-/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The last outlink descriptor address when spi dma produce to_eof.*/
-#define SPI_DMA_OUT_EOF_DES_ADDR  0xFFFFFFFF
-#define SPI_DMA_OUT_EOF_DES_ADDR_M  ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S))
-#define SPI_DMA_OUT_EOF_DES_ADDR_V  0xFFFFFFFF
-#define SPI_DMA_OUT_EOF_DES_ADDR_S  0
-
-#define SPI_OUTLINK_DSCR_REG(i)          (REG_SPI_BASE(i) + 0x13C)
-/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current out descriptor pointer.*/
-#define SPI_DMA_OUTLINK_DSCR  0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_M  ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S))
-#define SPI_DMA_OUTLINK_DSCR_V  0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_S  0
-
-#define SPI_OUTLINK_DSCR_BF0_REG(i)          (REG_SPI_BASE(i) + 0x140)
-/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of next out descriptor pointer.*/
-#define SPI_DMA_OUTLINK_DSCR_BF0  0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_BF0_M  ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S))
-#define SPI_DMA_OUTLINK_DSCR_BF0_V  0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_BF0_S  0
-
-#define SPI_OUTLINK_DSCR_BF1_REG(i)          (REG_SPI_BASE(i) + 0x144)
-/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current out descriptor data buffer pointer.*/
-#define SPI_DMA_OUTLINK_DSCR_BF1  0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_BF1_M  ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S))
-#define SPI_DMA_OUTLINK_DSCR_BF1_V  0xFFFFFFFF
-#define SPI_DMA_OUTLINK_DSCR_BF1_S  0
-
-#define SPI_DMA_RSTATUS_REG(i)          (REG_SPI_BASE(i) + 0x148)
-/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: spi dma read data from memory status.*/
-#define SPI_DMA_OUT_STATUS  0xFFFFFFFF
-#define SPI_DMA_OUT_STATUS_M  ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S))
-#define SPI_DMA_OUT_STATUS_V  0xFFFFFFFF
-#define SPI_DMA_OUT_STATUS_S  0
-
-#define SPI_DMA_TSTATUS_REG(i)          (REG_SPI_BASE(i) + 0x14C)
-/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: spi dma write data to memory status.*/
-#define SPI_DMA_IN_STATUS  0xFFFFFFFF
-#define SPI_DMA_IN_STATUS_M  ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S))
-#define SPI_DMA_IN_STATUS_V  0xFFFFFFFF
-#define SPI_DMA_IN_STATUS_S  0
-
-#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0x3FC)
-/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */
-/*description: SPI register version.*/
-#define SPI_DATE  0x0FFFFFFF
-#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
-#define SPI_DATE_V  0xFFFFFFF
-#define SPI_DATE_S  0
-
-
-
-
-#endif /*__SPI_REG_H__ */
-
-
diff --git a/tools/sdk/include/soc/soc/spi_struct.h b/tools/sdk/include/soc/soc/spi_struct.h
deleted file mode 100644
index 3e36c81c905..00000000000
--- a/tools/sdk/include/soc/soc/spi_struct.h
+++ /dev/null
@@ -1,688 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SPI_STRUCT_H_
-#define _SOC_SPI_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t reserved0: 16;                         /*reserved*/
-            uint32_t flash_per:  1;                         /*program erase resume bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_pes:  1;                         /*program erase suspend bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t usr:        1;                         /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_hpm:  1;                         /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_res:  1;                         /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_dp:   1;                         /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_ce:   1;                         /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_be:   1;                         /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_se:   1;                         /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_pp:   1;                         /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
-            uint32_t flash_wrsr: 1;                         /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_rdsr: 1;                         /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_rdid: 1;                         /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-            uint32_t flash_wrdi: 1;                         /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-            uint32_t flash_wren: 1;                         /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-            uint32_t flash_read: 1;                         /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;                                          /*addr to slave / from master. SPI transfer from the MSB to the LSB. If length > 32 bits, then address continues from MSB of slv_wr_status.*/
-    union {
-        struct {
-            uint32_t reserved0:         10;                 /*reserved*/
-            uint32_t fcs_crc_en:         1;                 /*For SPI1  initialize crc32 module before writing encrypted data to flash. Active low.*/
-            uint32_t tx_crc_en:          1;                 /*For SPI1  enable crc32 when writing encrypted data to flash. 1: enable  0:disable*/
-            uint32_t wait_flash_idle_en: 1;                 /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/
-            uint32_t fastrd_mode:        1;                 /*This bit enable the bits: spi_fread_qio  spi_fread_dio  spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/
-            uint32_t fread_dual:         1;                 /*In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
-            uint32_t resandres:          1;                 /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/
-            uint32_t reserved16:         4;                 /*reserved*/
-            uint32_t fread_quad:         1;                 /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
-            uint32_t wp:                 1;                 /*Write protect signal output when SPI is idle.  1: output high  0: output low.*/
-            uint32_t wrsr_2b:            1;                 /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
-            uint32_t fread_dio:          1;                 /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
-            uint32_t fread_qio:          1;                 /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
-            uint32_t rd_bit_order:       1;                 /*In read-data (MISO) phase 1: LSB first 0: MSB first*/
-            uint32_t wr_bit_order:       1;                 /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
-            uint32_t reserved27:         5;                 /*reserved*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t reserved0:        16;                  /*reserved*/
-            uint32_t cs_hold_delay_res:12;                  /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
-            uint32_t cs_hold_delay:     4;                  /*SPI cs signal is delayed by spi clock cycles*/
-        };
-        uint32_t val;
-    } ctrl1;
-    union {
-        struct {
-            uint32_t status:    16;                         /*In the slave mode, it is the status for master to read out.*/
-            uint32_t wb_mode:    8;                         /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/
-            uint32_t status_ext: 8;                         /*In the slave mode,it is the status for master to read out.*/
-        };
-        uint32_t val;
-    } rd_status;
-    union {
-        struct {
-            uint32_t setup_time:       4;                   /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/
-            uint32_t hold_time:        4;                   /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/
-            uint32_t ck_out_low_mode:  4;                   /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/
-            uint32_t ck_out_high_mode: 4;                   /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/
-            uint32_t miso_delay_mode:  2;                   /*MISO signals are delayed by spi_clk. 0: zero  1: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by half cycle    else delayed by one cycle  2: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by one cycle  else delayed by half cycle  3: delayed one cycle*/
-            uint32_t miso_delay_num:   3;                   /*MISO signals are delayed by system clock cycles*/
-            uint32_t mosi_delay_mode:  2;                   /*MOSI signals are delayed by spi_clk. 0: zero  1: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by half cycle    else delayed by one cycle  2: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by one cycle  else delayed by half cycle  3: delayed one cycle*/
-            uint32_t mosi_delay_num:   3;                   /*MOSI signals are delayed by system clock cycles*/
-            uint32_t cs_delay_mode:    2;                   /*spi_cs signal is delayed by spi_clk . 0: zero  1: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by half cycle    else delayed by one cycle  2: if spi_ck_out_edge or spi_ck_i_edge is set 1  delayed by one cycle   else delayed by half cycle  3: delayed one cycle*/
-            uint32_t cs_delay_num:     4;                   /*spi_cs signal is delayed by system clock cycles*/
-        };
-        uint32_t val;
-    } ctrl2;
-    union {
-        struct {
-            uint32_t clkcnt_l:       6;                     /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/
-            uint32_t clkcnt_h:       6;                     /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
-            uint32_t clkcnt_n:       6;                     /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
-            uint32_t clkdiv_pre:    13;                     /*In the master mode it is pre-divider of spi_clk.*/
-            uint32_t clk_equ_sysclk: 1;                     /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t doutdin:           1;                  /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/
-            uint32_t reserved1:         3;                  /*reserved*/
-            uint32_t cs_hold:           1;                  /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/
-            uint32_t cs_setup:          1;                  /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/
-            uint32_t ck_i_edge:         1;                  /*In the slave mode  the bit is same as spi_ck_out_edge in master mode. It is combined with  spi_miso_delay_mode bits.*/
-            uint32_t ck_out_edge:       1;                  /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
-            uint32_t reserved8:         2;                  /*reserved*/
-            uint32_t rd_byte_order:     1;                  /*In read-data (MISO) phase 1: big-endian 0: little_endian*/
-            uint32_t wr_byte_order:     1;                  /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
-            uint32_t fwrite_dual:       1;                  /*In the write operations read-data phase apply 2 signals*/
-            uint32_t fwrite_quad:       1;                  /*In the write operations read-data phase apply 4 signals*/
-            uint32_t fwrite_dio:        1;                  /*In the write operations address phase and read-data phase apply 2 signals.*/
-            uint32_t fwrite_qio:        1;                  /*In the write operations address phase and read-data phase apply 4 signals.*/
-            uint32_t sio:               1;                  /*Set the bit to enable 3-line half duplex communication  mosi and miso signals share the same pin. 1: enable 0: disable.*/
-            uint32_t usr_hold_pol:      1;                  /*It is combined with hold bits to set the polarity of spi hold line  1: spi will be held when spi hold line is high  0: spi will be held when spi hold line is low*/
-            uint32_t usr_dout_hold:     1;                  /*spi is hold at data out state  the bit combined with spi_usr_hold_pol bit.*/
-            uint32_t usr_din_hold:      1;                  /*spi is hold at data in state  the bit combined with spi_usr_hold_pol bit.*/
-            uint32_t usr_dummy_hold:    1;                  /*spi is hold at dummy state  the bit combined with spi_usr_hold_pol bit.*/
-            uint32_t usr_addr_hold:     1;                  /*spi is hold at address state  the bit combined with spi_usr_hold_pol bit.*/
-            uint32_t usr_cmd_hold:      1;                  /*spi is hold at command state  the bit combined with spi_usr_hold_pol bit.*/
-            uint32_t usr_prep_hold:     1;                  /*spi is hold at prepare state  the bit combined with spi_usr_hold_pol bit.*/
-            uint32_t usr_miso_highpart: 1;                  /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
-            uint32_t usr_mosi_highpart: 1;                  /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
-            uint32_t usr_dummy_idle:    1;                  /*spi clock is disable in dummy phase when the bit is enable.*/
-            uint32_t usr_mosi:          1;                  /*This bit enable the write-data phase of an operation.*/
-            uint32_t usr_miso:          1;                  /*This bit enable the read-data phase of an operation.*/
-            uint32_t usr_dummy:         1;                  /*This bit enable the dummy phase of an operation.*/
-            uint32_t usr_addr:          1;                  /*This bit enable the address phase of an operation.*/
-            uint32_t usr_command:       1;                  /*This bit enable the command phase of an operation.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen: 8;                 /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
-            uint32_t reserved8:         18;                 /*reserved*/
-            uint32_t usr_addr_bitlen:    6;                 /*The length in bits of address phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value: 16;                 /*The value of  command. Output sequence: bit 7-0 and then 15-8.*/
-            uint32_t reserved16:        12;                 /*reserved*/
-            uint32_t usr_command_bitlen: 4;                 /*The length in bits of command phase. The register value shall be (bit_num-1)*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t usr_mosi_dbitlen:24;                   /*The length in bits of write-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved24:       8;                   /*reserved*/
-        };
-        uint32_t val;
-    } mosi_dlen;
-    union {
-        struct {
-            uint32_t usr_miso_dbitlen:24;                   /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved24:       8;                   /*reserved*/
-        };
-        uint32_t val;
-    } miso_dlen;
-    uint32_t slv_wr_status;                                 /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/
-    union {
-        struct {
-            uint32_t cs0_dis:        1;                     /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/
-            uint32_t cs1_dis:        1;                     /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/
-            uint32_t cs2_dis:        1;                     /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/
-            uint32_t reserved3:      2;                     /*reserved*/
-            uint32_t ck_dis:         1;                     /*1: spi clk out disable  0: spi clk out enable*/
-            uint32_t master_cs_pol:  3;                     /*In the master mode  the bits are the polarity of spi cs line  the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
-            uint32_t reserved9:      2;                     /*reserved*/
-            uint32_t master_ck_sel:  3;                     /*In the master mode  spi cs line is enable as spi clk  it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/
-            uint32_t reserved14:    15;                     /*reserved*/
-            uint32_t ck_idle_edge:   1;                     /*1: spi clk line is high when idle     0: spi clk line is low when idle*/
-            uint32_t cs_keep_active: 1;                     /*spi cs line keep low when the bit is set.*/
-            uint32_t reserved31:     1;                     /*reserved*/
-        };
-        uint32_t val;
-    } pin;
-    union {
-        struct {
-            uint32_t rd_buf_done:  1;                       /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
-            uint32_t wr_buf_done:  1;                       /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/
-            uint32_t rd_sta_done:  1;                       /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/
-            uint32_t wr_sta_done:  1;                       /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/
-            uint32_t trans_done:   1;                       /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
-            uint32_t rd_buf_inten: 1;                       /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/
-            uint32_t wr_buf_inten: 1;                       /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/
-            uint32_t rd_sta_inten: 1;                       /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/
-            uint32_t wr_sta_inten: 1;                       /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/
-            uint32_t trans_inten:  1;                       /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/
-            uint32_t cs_i_mode:    2;                       /*In the slave mode  this bits used to synchronize the input spi cs signal and eliminate spi cs  jitter.*/
-            uint32_t reserved12:   5;                       /*reserved*/
-            uint32_t last_command: 3;                       /*In the slave mode it is the value of command.*/
-            uint32_t last_state:   3;                       /*In the slave mode it is the state of spi state machine.*/
-            uint32_t trans_cnt:    4;                       /*The operations counter in both the master mode and the slave mode. 4: read-status*/
-            uint32_t cmd_define:   1;                       /*1: slave mode commands are defined in SPI_SLAVE3.  0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/
-            uint32_t wr_rd_sta_en: 1;                       /*write and read status enable  in the slave mode*/
-            uint32_t wr_rd_buf_en: 1;                       /*write and read buffer enable in the slave mode*/
-            uint32_t slave_mode:   1;                       /*1: slave mode 0: master mode.*/
-            uint32_t sync_reset:   1;                       /*Software reset enable, reset the spi clock line cs line and data lines.*/
-        };
-        uint32_t val;
-    } slave;
-    union {
-        struct {
-            uint32_t rdbuf_dummy_en:  1;                    /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/
-            uint32_t wrbuf_dummy_en:  1;                    /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/
-            uint32_t rdsta_dummy_en:  1;                    /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/
-            uint32_t wrsta_dummy_en:  1;                    /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/
-            uint32_t wr_addr_bitlen:  6;                    /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/
-            uint32_t rd_addr_bitlen:  6;                    /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/
-            uint32_t reserved16:      9;                    /*reserved*/
-            uint32_t status_readback: 1;                    /*In the slave mode  1:read register of SPI_SLV_WR_STATUS  0: read register of SPI_RD_STATUS.*/
-            uint32_t status_fast_en:  1;                    /*In the slave mode enable fast read status.*/
-            uint32_t status_bitlen:   5;                    /*In the slave mode it is the length of status bit.*/
-        };
-        uint32_t val;
-    } slave1;
-    union {
-        struct {
-            uint32_t rdsta_dummy_cyclelen: 8;               /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/
-            uint32_t wrsta_dummy_cyclelen: 8;               /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/
-            uint32_t rdbuf_dummy_cyclelen: 8;               /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/
-            uint32_t wrbuf_dummy_cyclelen: 8;               /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/
-        };
-        uint32_t val;
-    } slave2;
-    union {
-        struct {
-            uint32_t rdbuf_cmd_value: 8;                    /*In the slave mode it is the value of read-buffer command.*/
-            uint32_t wrbuf_cmd_value: 8;                    /*In the slave mode it is the value of write-buffer command.*/
-            uint32_t rdsta_cmd_value: 8;                    /*In the slave mode it is the value of read-status command.*/
-            uint32_t wrsta_cmd_value: 8;                    /*In the slave mode it is the value of write-status command.*/
-        };
-        uint32_t val;
-    } slave3;
-    union {
-        struct {
-            uint32_t bit_len:    24;                        /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
-            uint32_t reserved24:  8;                        /*reserved*/
-        };
-        uint32_t val;
-    } slv_wrbuf_dlen;
-    union {
-        struct {
-            uint32_t bit_len:    24;                        /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
-            uint32_t reserved24:  8;                        /*reserved*/
-        };
-        uint32_t val;
-    } slv_rdbuf_dlen;
-    union {
-        struct {
-            uint32_t req_en:        1;                      /*For SPI0  Cache access enable  1: enable  0:disable.*/
-            uint32_t usr_cmd_4byte: 1;                      /*For SPI0  cache  read flash with 4 bytes command  1: enable  0:disable.*/
-            uint32_t flash_usr_cmd: 1;                      /*For SPI0  cache  read flash for user define command  1: enable  0:disable.*/
-            uint32_t flash_pes_en:  1;                      /*For SPI0  spi1 send suspend command before cache read flash  1: enable  0:disable.*/
-            uint32_t reserved4:    28;                      /*reserved*/
-        };
-        uint32_t val;
-    } cache_fctrl;
-    union {
-        struct {
-            uint32_t reserved0:           1;                /*reserved*/
-            uint32_t usr_sram_dio:        1;                /*For SPI0  In the spi sram mode  spi dual I/O mode enable  1: enable  0:disable*/
-            uint32_t usr_sram_qio:        1;                /*For SPI0  In the spi sram mode  spi quad I/O mode enable  1: enable  0:disable*/
-            uint32_t usr_wr_sram_dummy:   1;                /*For SPI0  In the spi sram mode  it is the enable bit of dummy phase for write operations.*/
-            uint32_t usr_rd_sram_dummy:   1;                /*For SPI0  In the spi sram mode  it is the enable bit of dummy phase for read operations.*/
-            uint32_t cache_sram_usr_rcmd: 1;                /*For SPI0  In the spi sram mode cache read sram for user define command.*/
-            uint32_t sram_bytes_len:      8;                /*For SPI0  In the sram mode  it is the byte length of spi read sram data.*/
-            uint32_t sram_dummy_cyclelen: 8;                /*For SPI0  In the sram mode  it is the length in bits of address phase. The register value shall be (bit_num-1).*/
-            uint32_t sram_addr_bitlen:    6;                /*For SPI0  In the sram mode  it is the length in bits of address phase. The register value shall be (bit_num-1).*/
-            uint32_t cache_sram_usr_wcmd: 1;                /*For SPI0  In the spi sram mode cache write sram for user define command*/
-            uint32_t reserved29:          3;                /*reserved*/
-        };
-        uint32_t val;
-    } cache_sctrl;
-    union {
-        struct {
-            uint32_t dio:       1;                          /*For SPI0 SRAM DIO mode enable .  SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
-            uint32_t qio:       1;                          /*For SPI0 SRAM QIO mode enable .  SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/
-            uint32_t reserved2: 2;                          /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/
-            uint32_t rst_io:    1;                          /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/
-            uint32_t reserved5:27;                          /*reserved*/
-        };
-        uint32_t val;
-    } sram_cmd;
-    union {
-        struct {
-            uint32_t usr_rd_cmd_value:   16;                /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/
-            uint32_t reserved16:         12;                /*reserved*/
-            uint32_t usr_rd_cmd_bitlen:   4;                /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_drd_cmd;
-    union {
-        struct {
-            uint32_t usr_wr_cmd_value: 16;                  /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/
-            uint32_t reserved16:       12;                  /*reserved*/
-            uint32_t usr_wr_cmd_bitlen: 4;                  /*For SPI0 When cache mode is enable it is the in bits of command phase  for SRAM. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_dwr_cmd;
-    union {
-        struct {
-            uint32_t slv_rdata_bit:24;                      /*In the slave mode it is the bit length of read data. The value is the length - 1.*/
-            uint32_t reserved24:    8;                      /*reserved*/
-        };
-        uint32_t val;
-    } slv_rd_bit;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t data_buf[16];                                  /*data buffer*/
-    uint32_t tx_crc;                                        /*For SPI1  the value of crc32 for 256 bits data.*/
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    union {
-        struct {
-            uint32_t t_pp_time: 12;                         /*page program delay time  by system clock.*/
-            uint32_t reserved12: 4;                         /*reserved*/
-            uint32_t t_pp_shift: 4;                         /*page program delay time shift .*/
-            uint32_t reserved20:11;                         /*reserved*/
-            uint32_t t_pp_ena:   1;                         /*page program delay enable.*/
-        };
-        uint32_t val;
-    } ext0;
-    union {
-        struct {
-            uint32_t t_erase_time: 12;                      /*erase flash delay time by system clock.*/
-            uint32_t reserved12:    4;                      /*reserved*/
-            uint32_t t_erase_shift: 4;                      /*erase flash delay time shift.*/
-            uint32_t reserved20:   11;                      /*reserved*/
-            uint32_t t_erase_ena:   1;                      /*erase flash delay enable.*/
-        };
-        uint32_t val;
-    } ext1;
-    union {
-        struct {
-            uint32_t st:         3;                         /*The status of spi state machine .*/
-            uint32_t reserved3: 29;                         /*reserved*/
-        };
-        uint32_t val;
-    } ext2;
-    union {
-        struct {
-            uint32_t int_hold_ena: 2;                       /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set  if the other SPI is busy  the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/
-            uint32_t reserved2:   30;                       /*reserved*/
-        };
-        uint32_t val;
-    } ext3;
-    union {
-        struct {
-            uint32_t reserved0:         2;                  /*reserved*/
-            uint32_t in_rst:            1;                  /*The bit is used to reset in dma fsm and in data fifo pointer.*/
-            uint32_t out_rst:           1;                  /*The bit is used to reset out dma fsm and out data fifo pointer.*/
-            uint32_t ahbm_fifo_rst:     1;                  /*reset spi dma ahb master fifo pointer.*/
-            uint32_t ahbm_rst:          1;                  /*reset spi dma ahb master.*/
-            uint32_t in_loop_test:      1;                  /*Set bit to test in link.*/
-            uint32_t out_loop_test:     1;                  /*Set bit to test out link.*/
-            uint32_t out_auto_wrback:   1;                  /*when the link is empty   jump to next automatically.*/
-            uint32_t out_eof_mode:      1;                  /*out eof flag generation mode . 1: when dma pop all data from fifo  0:when ahb push all data to fifo.*/
-            uint32_t outdscr_burst_en:  1;                  /*read descriptor use burst mode when read data for memory.*/
-            uint32_t indscr_burst_en:   1;                  /*read descriptor use burst mode when write data to memory.*/
-            uint32_t out_data_burst_en: 1;                  /*spi dma read data from memory in burst mode.*/
-            uint32_t reserved13:        1;                  /*reserved*/
-            uint32_t dma_rx_stop:       1;                  /*spi dma read data stop  when in continue tx/rx mode.*/
-            uint32_t dma_tx_stop:       1;                  /*spi dma write data stop when in continue tx/rx mode.*/
-            uint32_t dma_continue:      1;                  /*spi dma continue tx/rx data.*/
-            uint32_t reserved17:       15;                  /*reserved*/
-        };
-        uint32_t val;
-    } dma_conf;
-    union {
-        struct {
-            uint32_t addr:        20;                       /*The address of the first outlink descriptor.*/
-            uint32_t reserved20:   8;                       /*reserved*/
-            uint32_t stop:         1;                       /*Set the bit to stop to use outlink descriptor.*/
-            uint32_t start:        1;                       /*Set the bit to start to use outlink descriptor.*/
-            uint32_t restart:      1;                       /*Set the bit to mount on new outlink descriptors.*/
-            uint32_t reserved31:   1;                       /*reserved*/
-        };
-        uint32_t val;
-    } dma_out_link;
-    union {
-        struct {
-            uint32_t addr:       20;                        /*The address of the first inlink descriptor.*/
-            uint32_t auto_ret:    1;                        /*when the bit is set  inlink descriptor returns to the next descriptor while a packet is wrong*/
-            uint32_t reserved21:  7;                        /*reserved*/
-            uint32_t stop:        1;                        /*Set the bit to stop to use inlink descriptor.*/
-            uint32_t start:       1;                        /*Set the bit to start to use inlink descriptor.*/
-            uint32_t restart:     1;                        /*Set the bit to mount on new inlink descriptors.*/
-            uint32_t reserved31:  1;                        /*reserved*/
-        };
-        uint32_t val;
-    } dma_in_link;
-    union {
-        struct {
-            uint32_t rx_en:      1;                         /*spi dma read data status bit.*/
-            uint32_t tx_en:      1;                         /*spi dma write data status bit.*/
-            uint32_t reserved2: 30;                         /*spi dma read data from memory count.*/
-        };
-        uint32_t val;
-    } dma_status;
-    union {
-        struct {
-            uint32_t inlink_dscr_empty:  1;                 /*The enable bit for lack of enough inlink descriptors.*/
-            uint32_t outlink_dscr_error: 1;                 /*The enable bit for outlink descriptor error.*/
-            uint32_t inlink_dscr_error:  1;                 /*The enable bit for inlink descriptor error.*/
-            uint32_t in_done:            1;                 /*The enable bit for completing usage of a inlink descriptor.*/
-            uint32_t in_err_eof:         1;                 /*The enable bit for receiving error.*/
-            uint32_t in_suc_eof:         1;                 /*The enable bit for completing receiving all the packets from host.*/
-            uint32_t out_done:           1;                 /*The enable bit for completing usage of a outlink descriptor .*/
-            uint32_t out_eof:            1;                 /*The enable bit for sending a packet to host done.*/
-            uint32_t out_total_eof:      1;                 /*The enable bit for sending all the packets to host done.*/
-            uint32_t reserved9:         23;                 /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_ena;
-    union {
-        struct {
-            uint32_t inlink_dscr_empty:  1;                 /*The raw bit for lack of enough inlink descriptors.*/
-            uint32_t outlink_dscr_error: 1;                 /*The raw bit for outlink descriptor error.*/
-            uint32_t inlink_dscr_error:  1;                 /*The raw bit for inlink descriptor error.*/
-            uint32_t in_done:            1;                 /*The raw bit for completing usage of a inlink descriptor.*/
-            uint32_t in_err_eof:         1;                 /*The raw bit for receiving error.*/
-            uint32_t in_suc_eof:         1;                 /*The raw bit for completing receiving all the packets from host.*/
-            uint32_t out_done:           1;                 /*The raw bit for completing usage of a outlink descriptor.*/
-            uint32_t out_eof:            1;                 /*The raw bit for sending a packet to host done.*/
-            uint32_t out_total_eof:      1;                 /*The raw bit for sending all the packets to host done.*/
-            uint32_t reserved9:         23;                 /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_raw;
-    union {
-        struct {
-            uint32_t inlink_dscr_empty:  1;                  /*The status bit for lack of enough inlink descriptors.*/
-            uint32_t outlink_dscr_error: 1;                  /*The status bit for outlink descriptor error.*/
-            uint32_t inlink_dscr_error:  1;                  /*The status bit for inlink descriptor error.*/
-            uint32_t in_done:            1;                  /*The status bit for completing usage of a inlink descriptor.*/
-            uint32_t in_err_eof:         1;                  /*The status bit for receiving error.*/
-            uint32_t in_suc_eof:         1;                  /*The status bit for completing receiving all the packets from host.*/
-            uint32_t out_done:           1;                  /*The status bit for completing usage of a outlink descriptor.*/
-            uint32_t out_eof:            1;                  /*The status bit for sending a packet to host done.*/
-            uint32_t out_total_eof:      1;                  /*The status bit for sending all the packets to host done.*/
-            uint32_t reserved9:         23;                  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_st;
-    union {
-        struct {
-            uint32_t inlink_dscr_empty:  1;                 /*The clear bit for lack of enough inlink descriptors.*/
-            uint32_t outlink_dscr_error: 1;                 /*The clear bit for outlink descriptor error.*/
-            uint32_t inlink_dscr_error:  1;                 /*The clear bit for inlink descriptor error.*/
-            uint32_t in_done:            1;                 /*The clear bit for completing usage of a inlink descriptor.*/
-            uint32_t in_err_eof:         1;                 /*The clear bit for receiving error.*/
-            uint32_t in_suc_eof:         1;                 /*The clear bit for completing receiving all the packets from host.*/
-            uint32_t out_done:           1;                 /*The clear bit for completing usage of a outlink descriptor.*/
-            uint32_t out_eof:            1;                 /*The clear bit for sending a packet to host done.*/
-            uint32_t out_total_eof:      1;                 /*The clear bit for sending all the packets to host done.*/
-            uint32_t reserved9:         23;                 /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_clr;
-    uint32_t dma_in_err_eof_des_addr;                       /*The inlink descriptor address when spi dma produce receiving error.*/
-    uint32_t dma_in_suc_eof_des_addr;                       /*The last inlink descriptor address when spi dma produce from_suc_eof.*/
-    uint32_t dma_inlink_dscr;                               /*The content of current in descriptor pointer.*/
-    uint32_t dma_inlink_dscr_bf0;                           /*The content of next in descriptor pointer.*/
-    uint32_t dma_inlink_dscr_bf1;                           /*The content of current in descriptor data buffer pointer.*/
-    uint32_t dma_out_eof_bfr_des_addr;                      /*The address of buffer relative to the outlink descriptor that produce eof.*/
-    uint32_t dma_out_eof_des_addr;                          /*The last outlink descriptor address when spi dma produce to_eof.*/
-    uint32_t dma_outlink_dscr;                              /*The content of current out descriptor pointer.*/
-    uint32_t dma_outlink_dscr_bf0;                          /*The content of next out descriptor pointer.*/
-    uint32_t dma_outlink_dscr_bf1;                          /*The content of current out descriptor data buffer pointer.*/
-    uint32_t dma_rx_status;                                 /*spi dma read data from memory status.*/
-    uint32_t dma_tx_status;                                 /*spi dma write data to memory status.*/
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t date:      28;                         /*SPI register version.*/
-            uint32_t reserved28: 4;                         /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_dev_t;
-extern spi_dev_t SPI0;                                      /* SPI0 IS FOR INTERNAL USE*/
-extern spi_dev_t SPI1;
-extern spi_dev_t SPI2;
-extern spi_dev_t SPI3;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_SPI_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/syscon_reg.h b/tools/sdk/include/soc/soc/syscon_reg.h
deleted file mode 100644
index 5012b27e573..00000000000
--- a/tools/sdk/include/soc/soc/syscon_reg.h
+++ /dev/null
@@ -1,294 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SYSCON_REG_H_
-#define _SOC_SYSCON_REG_H_
-
-#include "soc.h"
-#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x0)
-/* SYSCON_QUICK_CLK_CHNG : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_QUICK_CLK_CHNG  (BIT(13))
-#define SYSCON_QUICK_CLK_CHNG_M  (BIT(13))
-#define SYSCON_QUICK_CLK_CHNG_V  0x1
-#define SYSCON_QUICK_CLK_CHNG_S  13
-/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_RST_TICK_CNT  (BIT(12))
-#define SYSCON_RST_TICK_CNT_M  (BIT(12))
-#define SYSCON_RST_TICK_CNT_V  0x1
-#define SYSCON_RST_TICK_CNT_S  12
-/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_CLK_EN  (BIT(11))
-#define SYSCON_CLK_EN_M  (BIT(11))
-#define SYSCON_CLK_EN_V  0x1
-#define SYSCON_CLK_EN_S  11
-/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_CLK_320M_EN  (BIT(10))
-#define SYSCON_CLK_320M_EN_M  (BIT(10))
-#define SYSCON_CLK_320M_EN_V  0x1
-#define SYSCON_CLK_320M_EN_S  10
-/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define SYSCON_PRE_DIV_CNT  0x000003FF
-#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
-#define SYSCON_PRE_DIV_CNT_V  0x3FF
-#define SYSCON_PRE_DIV_CNT_S  0
-
-#define SYSCON_XTAL_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x4)
-/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
-/*description: */
-#define SYSCON_XTAL_TICK_NUM  0x000000FF
-#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
-#define SYSCON_XTAL_TICK_NUM_V  0xFF
-#define SYSCON_XTAL_TICK_NUM_S  0
-
-#define SYSCON_PLL_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x8)
-/* SYSCON_PLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd79 ; */
-/*description: */
-#define SYSCON_PLL_TICK_NUM  0x000000FF
-#define SYSCON_PLL_TICK_NUM_M  ((SYSCON_PLL_TICK_NUM_V)<<(SYSCON_PLL_TICK_NUM_S))
-#define SYSCON_PLL_TICK_NUM_V  0xFF
-#define SYSCON_PLL_TICK_NUM_S  0
-
-#define SYSCON_CK8M_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0xC)
-/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd11 ; */
-/*description: */
-#define SYSCON_CK8M_TICK_NUM  0x000000FF
-#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
-#define SYSCON_CK8M_TICK_NUM_V  0xFF
-#define SYSCON_CK8M_TICK_NUM_S  0
-
-#define SYSCON_SARADC_CTRL_REG          (DR_REG_SYSCON_BASE + 0x10)
-/* SYSCON_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1: I2S input data is from SAR ADC (for DMA)  0: I2S input data
- is from GPIO matrix*/
-#define SYSCON_SARADC_DATA_TO_I2S  (BIT(26))
-#define SYSCON_SARADC_DATA_TO_I2S_M  (BIT(26))
-#define SYSCON_SARADC_DATA_TO_I2S_V  0x1
-#define SYSCON_SARADC_DATA_TO_I2S_S  26
-/* SYSCON_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
-  in this case the resolution should not be larger than 11 bits.*/
-#define SYSCON_SARADC_DATA_SAR_SEL  (BIT(25))
-#define SYSCON_SARADC_DATA_SAR_SEL_M  (BIT(25))
-#define SYSCON_SARADC_DATA_SAR_SEL_V  0x1
-#define SYSCON_SARADC_DATA_SAR_SEL_S  25
-/* SYSCON_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
-#define SYSCON_SARADC_SAR2_PATT_P_CLEAR  (BIT(24))
-#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_M  (BIT(24))
-#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_V  0x1
-#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_S  24
-/* SYSCON_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
-#define SYSCON_SARADC_SAR1_PATT_P_CLEAR  (BIT(23))
-#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_M  (BIT(23))
-#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_V  0x1
-#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_S  23
-/* SYSCON_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
-/*description: 0 ~ 15 means length 1 ~ 16*/
-#define SYSCON_SARADC_SAR2_PATT_LEN  0x0000000F
-#define SYSCON_SARADC_SAR2_PATT_LEN_M  ((SYSCON_SARADC_SAR2_PATT_LEN_V)<<(SYSCON_SARADC_SAR2_PATT_LEN_S))
-#define SYSCON_SARADC_SAR2_PATT_LEN_V  0xF
-#define SYSCON_SARADC_SAR2_PATT_LEN_S  19
-/* SYSCON_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
-/*description: 0 ~ 15 means length 1 ~ 16*/
-#define SYSCON_SARADC_SAR1_PATT_LEN  0x0000000F
-#define SYSCON_SARADC_SAR1_PATT_LEN_M  ((SYSCON_SARADC_SAR1_PATT_LEN_V)<<(SYSCON_SARADC_SAR1_PATT_LEN_S))
-#define SYSCON_SARADC_SAR1_PATT_LEN_V  0xF
-#define SYSCON_SARADC_SAR1_PATT_LEN_S  15
-/* SYSCON_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
-/*description: SAR clock divider*/
-#define SYSCON_SARADC_SAR_CLK_DIV  0x000000FF
-#define SYSCON_SARADC_SAR_CLK_DIV_M  ((SYSCON_SARADC_SAR_CLK_DIV_V)<<(SYSCON_SARADC_SAR_CLK_DIV_S))
-#define SYSCON_SARADC_SAR_CLK_DIV_V  0xFF
-#define SYSCON_SARADC_SAR_CLK_DIV_S  7
-/* SYSCON_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_SARADC_SAR_CLK_GATED  (BIT(6))
-#define SYSCON_SARADC_SAR_CLK_GATED_M  (BIT(6))
-#define SYSCON_SARADC_SAR_CLK_GATED_V  0x1
-#define SYSCON_SARADC_SAR_CLK_GATED_S  6
-/* SYSCON_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: 0: SAR1  1: SAR2  only work for single SAR mode*/
-#define SYSCON_SARADC_SAR_SEL  (BIT(5))
-#define SYSCON_SARADC_SAR_SEL_M  (BIT(5))
-#define SYSCON_SARADC_SAR_SEL_V  0x1
-#define SYSCON_SARADC_SAR_SEL_S  5
-/* SYSCON_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
-/*description: 0: single mode  1: double mode  2: alternate mode*/
-#define SYSCON_SARADC_WORK_MODE  0x00000003
-#define SYSCON_SARADC_WORK_MODE_M  ((SYSCON_SARADC_WORK_MODE_V)<<(SYSCON_SARADC_WORK_MODE_S))
-#define SYSCON_SARADC_WORK_MODE_V  0x3
-#define SYSCON_SARADC_WORK_MODE_S  3
-/* SYSCON_SARADC_SAR2_MUX : R/W ;bitpos:[2] ;default: 1'd0 ; */
-/*description: 1: SAR ADC2 is controlled by DIG ADC2 CTRL  0: SAR ADC2 is controlled
- by PWDET CTRL*/
-#define SYSCON_SARADC_SAR2_MUX  (BIT(2))
-#define SYSCON_SARADC_SAR2_MUX_M  (BIT(2))
-#define SYSCON_SARADC_SAR2_MUX_V  0x1
-#define SYSCON_SARADC_SAR2_MUX_S  2
-/* SYSCON_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_SARADC_START  (BIT(1))
-#define SYSCON_SARADC_START_M  (BIT(1))
-#define SYSCON_SARADC_START_V  0x1
-#define SYSCON_SARADC_START_S  1
-/* SYSCON_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_SARADC_START_FORCE  (BIT(0))
-#define SYSCON_SARADC_START_FORCE_M  (BIT(0))
-#define SYSCON_SARADC_START_FORCE_V  0x1
-#define SYSCON_SARADC_START_FORCE_S  0
-
-#define SYSCON_SARADC_CTRL2_REG          (DR_REG_SYSCON_BASE + 0x14)
-/* SYSCON_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: 1: data to DIG ADC2 CTRL is inverted  otherwise not*/
-#define SYSCON_SARADC_SAR2_INV  (BIT(10))
-#define SYSCON_SARADC_SAR2_INV_M  (BIT(10))
-#define SYSCON_SARADC_SAR2_INV_V  0x1
-#define SYSCON_SARADC_SAR2_INV_S  10
-/* SYSCON_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: 1: data to DIG ADC1 CTRL is inverted  otherwise not*/
-#define SYSCON_SARADC_SAR1_INV  (BIT(9))
-#define SYSCON_SARADC_SAR1_INV_M  (BIT(9))
-#define SYSCON_SARADC_SAR1_INV_V  0x1
-#define SYSCON_SARADC_SAR1_INV_S  9
-/* SYSCON_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
-/*description: max conversion number*/
-#define SYSCON_SARADC_MAX_MEAS_NUM  0x000000FF
-#define SYSCON_SARADC_MAX_MEAS_NUM_M  ((SYSCON_SARADC_MAX_MEAS_NUM_V)<<(SYSCON_SARADC_MAX_MEAS_NUM_S))
-#define SYSCON_SARADC_MAX_MEAS_NUM_V  0xFF
-#define SYSCON_SARADC_MAX_MEAS_NUM_S  1
-/* SYSCON_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_SARADC_MEAS_NUM_LIMIT  (BIT(0))
-#define SYSCON_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
-#define SYSCON_SARADC_MEAS_NUM_LIMIT_V  0x1
-#define SYSCON_SARADC_MEAS_NUM_LIMIT_S  0
-
-#define SYSCON_SARADC_FSM_REG          (DR_REG_SYSCON_BASE + 0x18)
-/* SYSCON_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
-/*description: sample cycles*/
-#define SYSCON_SARADC_SAMPLE_CYCLE  0x000000FF
-#define SYSCON_SARADC_SAMPLE_CYCLE_M  ((SYSCON_SARADC_SAMPLE_CYCLE_V)<<(SYSCON_SARADC_SAMPLE_CYCLE_S))
-#define SYSCON_SARADC_SAMPLE_CYCLE_V  0xFF
-#define SYSCON_SARADC_SAMPLE_CYCLE_S  24
-/* SYSCON_SARADC_START_WAIT : R/W ;bitpos:[23:16] ;default: 8'd8 ; */
-/*description: */
-#define SYSCON_SARADC_START_WAIT  0x000000FF
-#define SYSCON_SARADC_START_WAIT_M  ((SYSCON_SARADC_START_WAIT_V)<<(SYSCON_SARADC_START_WAIT_S))
-#define SYSCON_SARADC_START_WAIT_V  0xFF
-#define SYSCON_SARADC_START_WAIT_S  16
-/* SYSCON_SARADC_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd255 ; */
-/*description: */
-#define SYSCON_SARADC_STANDBY_WAIT  0x000000FF
-#define SYSCON_SARADC_STANDBY_WAIT_M  ((SYSCON_SARADC_STANDBY_WAIT_V)<<(SYSCON_SARADC_STANDBY_WAIT_S))
-#define SYSCON_SARADC_STANDBY_WAIT_V  0xFF
-#define SYSCON_SARADC_STANDBY_WAIT_S  8
-/* SYSCON_SARADC_RSTB_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
-/*description: */
-#define SYSCON_SARADC_RSTB_WAIT  0x000000FF
-#define SYSCON_SARADC_RSTB_WAIT_M  ((SYSCON_SARADC_RSTB_WAIT_V)<<(SYSCON_SARADC_RSTB_WAIT_S))
-#define SYSCON_SARADC_RSTB_WAIT_V  0xFF
-#define SYSCON_SARADC_RSTB_WAIT_S  0
-
-#define SYSCON_SARADC_SAR1_PATT_TAB1_REG          (DR_REG_SYSCON_BASE + 0x1C)
-/* SYSCON_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
-#define SYSCON_SARADC_SAR1_PATT_TAB1  0xFFFFFFFF
-#define SYSCON_SARADC_SAR1_PATT_TAB1_M  ((SYSCON_SARADC_SAR1_PATT_TAB1_V)<<(SYSCON_SARADC_SAR1_PATT_TAB1_S))
-#define SYSCON_SARADC_SAR1_PATT_TAB1_V  0xFFFFFFFF
-#define SYSCON_SARADC_SAR1_PATT_TAB1_S  0
-
-#define SYSCON_SARADC_SAR1_PATT_TAB2_REG          (DR_REG_SYSCON_BASE + 0x20)
-/* SYSCON_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
-#define SYSCON_SARADC_SAR1_PATT_TAB2  0xFFFFFFFF
-#define SYSCON_SARADC_SAR1_PATT_TAB2_M  ((SYSCON_SARADC_SAR1_PATT_TAB2_V)<<(SYSCON_SARADC_SAR1_PATT_TAB2_S))
-#define SYSCON_SARADC_SAR1_PATT_TAB2_V  0xFFFFFFFF
-#define SYSCON_SARADC_SAR1_PATT_TAB2_S  0
-
-#define SYSCON_SARADC_SAR1_PATT_TAB3_REG          (DR_REG_SYSCON_BASE + 0x24)
-/* SYSCON_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
-#define SYSCON_SARADC_SAR1_PATT_TAB3  0xFFFFFFFF
-#define SYSCON_SARADC_SAR1_PATT_TAB3_M  ((SYSCON_SARADC_SAR1_PATT_TAB3_V)<<(SYSCON_SARADC_SAR1_PATT_TAB3_S))
-#define SYSCON_SARADC_SAR1_PATT_TAB3_V  0xFFFFFFFF
-#define SYSCON_SARADC_SAR1_PATT_TAB3_S  0
-
-#define SYSCON_SARADC_SAR1_PATT_TAB4_REG          (DR_REG_SYSCON_BASE + 0x28)
-/* SYSCON_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
-#define SYSCON_SARADC_SAR1_PATT_TAB4  0xFFFFFFFF
-#define SYSCON_SARADC_SAR1_PATT_TAB4_M  ((SYSCON_SARADC_SAR1_PATT_TAB4_V)<<(SYSCON_SARADC_SAR1_PATT_TAB4_S))
-#define SYSCON_SARADC_SAR1_PATT_TAB4_V  0xFFFFFFFF
-#define SYSCON_SARADC_SAR1_PATT_TAB4_S  0
-
-#define SYSCON_SARADC_SAR2_PATT_TAB1_REG          (DR_REG_SYSCON_BASE + 0x2C)
-/* SYSCON_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
-#define SYSCON_SARADC_SAR2_PATT_TAB1  0xFFFFFFFF
-#define SYSCON_SARADC_SAR2_PATT_TAB1_M  ((SYSCON_SARADC_SAR2_PATT_TAB1_V)<<(SYSCON_SARADC_SAR2_PATT_TAB1_S))
-#define SYSCON_SARADC_SAR2_PATT_TAB1_V  0xFFFFFFFF
-#define SYSCON_SARADC_SAR2_PATT_TAB1_S  0
-
-#define SYSCON_SARADC_SAR2_PATT_TAB2_REG          (DR_REG_SYSCON_BASE + 0x30)
-/* SYSCON_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
-#define SYSCON_SARADC_SAR2_PATT_TAB2  0xFFFFFFFF
-#define SYSCON_SARADC_SAR2_PATT_TAB2_M  ((SYSCON_SARADC_SAR2_PATT_TAB2_V)<<(SYSCON_SARADC_SAR2_PATT_TAB2_S))
-#define SYSCON_SARADC_SAR2_PATT_TAB2_V  0xFFFFFFFF
-#define SYSCON_SARADC_SAR2_PATT_TAB2_S  0
-
-#define SYSCON_SARADC_SAR2_PATT_TAB3_REG          (DR_REG_SYSCON_BASE + 0x34)
-/* SYSCON_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
-#define SYSCON_SARADC_SAR2_PATT_TAB3  0xFFFFFFFF
-#define SYSCON_SARADC_SAR2_PATT_TAB3_M  ((SYSCON_SARADC_SAR2_PATT_TAB3_V)<<(SYSCON_SARADC_SAR2_PATT_TAB3_S))
-#define SYSCON_SARADC_SAR2_PATT_TAB3_V  0xFFFFFFFF
-#define SYSCON_SARADC_SAR2_PATT_TAB3_S  0
-
-#define SYSCON_SARADC_SAR2_PATT_TAB4_REG          (DR_REG_SYSCON_BASE + 0x38)
-/* SYSCON_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
-/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
-#define SYSCON_SARADC_SAR2_PATT_TAB4  0xFFFFFFFF
-#define SYSCON_SARADC_SAR2_PATT_TAB4_M  ((SYSCON_SARADC_SAR2_PATT_TAB4_V)<<(SYSCON_SARADC_SAR2_PATT_TAB4_S))
-#define SYSCON_SARADC_SAR2_PATT_TAB4_V  0xFFFFFFFF
-#define SYSCON_SARADC_SAR2_PATT_TAB4_S  0
-
-#define SYSCON_APLL_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x3C)
-/* SYSCON_APLL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd99 ; */
-/*description: */
-#define SYSCON_APLL_TICK_NUM  0x000000FF
-#define SYSCON_APLL_TICK_NUM_M  ((SYSCON_APLL_TICK_NUM_V)<<(SYSCON_APLL_TICK_NUM_S))
-#define SYSCON_APLL_TICK_NUM_V  0xFF
-#define SYSCON_APLL_TICK_NUM_S  0
-
-#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x7C)
-/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042000 ; */
-/*description: */
-#define SYSCON_DATE  0xFFFFFFFF
-#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
-#define SYSCON_DATE_V  0xFFFFFFFF
-#define SYSCON_DATE_S  0
-
-
-
-
-#endif /*_SOC_SYSCON_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/syscon_struct.h b/tools/sdk/include/soc/soc/syscon_struct.h
deleted file mode 100644
index 4fb86f42b99..00000000000
--- a/tools/sdk/include/soc/soc/syscon_struct.h
+++ /dev/null
@@ -1,125 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SYSCON_STRUCT_H_
-#define _SOC_SYSCON_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t pre_div:       10;
-            uint32_t clk_320m_en:    1;
-            uint32_t clk_en:         1;
-            uint32_t rst_tick:       1;
-            uint32_t quick_clk_chng: 1;
-            uint32_t reserved14:    18;
-        };
-        uint32_t val;
-    }clk_conf;
-    union {
-        struct {
-            uint32_t xtal_tick:     8;
-            uint32_t reserved8:    24;
-        };
-        uint32_t val;
-    }xtal_tick_conf;
-    union {
-        struct {
-            uint32_t pll_tick:     8;
-            uint32_t reserved8:   24;
-        };
-        uint32_t val;
-    }pll_tick_conf;
-    union {
-        struct {
-            uint32_t ck8m_tick:     8;
-            uint32_t reserved8:    24;
-        };
-        uint32_t val;
-    }ck8m_tick_conf;
-    union {
-        struct {
-            uint32_t start_force:       1;
-            uint32_t start:             1;
-            uint32_t sar2_mux:          1;       /*1: SAR ADC2 is controlled by DIG ADC2 CTRL  0: SAR ADC2 is controlled by PWDET CTRL*/
-            uint32_t work_mode:         2;       /*0: single mode  1: double mode  2: alternate mode*/
-            uint32_t sar_sel:           1;       /*0: SAR1  1: SAR2  only work for single SAR mode*/
-            uint32_t sar_clk_gated:     1;
-            uint32_t sar_clk_div:       8;       /*SAR clock divider*/
-            uint32_t sar1_patt_len:     4;       /*0 ~ 15 means length 1 ~ 16*/
-            uint32_t sar2_patt_len:     4;       /*0 ~ 15 means length 1 ~ 16*/
-            uint32_t sar1_patt_p_clear: 1;       /*clear the pointer of pattern table for DIG ADC1 CTRL*/
-            uint32_t sar2_patt_p_clear: 1;       /*clear the pointer of pattern table for DIG ADC2 CTRL*/
-            uint32_t data_sar_sel:      1;       /*1: sar_sel will be coded by the MSB of the 16-bit output data  in this case the resolution should not be larger than 11 bits.*/
-            uint32_t data_to_i2s:       1;       /*1: I2S input data is from SAR ADC (for DMA)  0: I2S input data is from GPIO matrix*/
-            uint32_t reserved27:        5;
-        };
-        uint32_t val;
-    }saradc_ctrl;
-    union {
-        struct {
-            uint32_t meas_num_limit: 1;
-            uint32_t max_meas_num:   8;          /*max conversion number*/
-            uint32_t sar1_inv:       1;          /*1: data to DIG ADC1 CTRL is inverted  otherwise not*/
-            uint32_t sar2_inv:       1;          /*1: data to DIG ADC2 CTRL is inverted  otherwise not*/
-            uint32_t reserved11:    21;
-        };
-        uint32_t val;
-    }saradc_ctrl2;
-    union {
-        struct {
-            uint32_t rstb_wait:    8;
-            uint32_t standby_wait: 8;
-            uint32_t start_wait:   8;
-            uint32_t sample_cycle: 8;            /*sample cycles*/
-        };
-        uint32_t val;
-    }saradc_fsm;
-    uint32_t saradc_sar1_patt_tab[4];                 /*item 0 ~ 3 for ADC1 pattern table*/
-    uint32_t saradc_sar2_patt_tab[4];                 /*item 0 ~ 3 for ADC2 pattern table*/
-    union {
-        struct {
-            uint32_t apll_tick:     8;
-            uint32_t reserved8:    24;
-        };
-        uint32_t val;
-    }apll_tick_conf;
-    uint32_t reserved_40;
-    uint32_t reserved_44;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t date;                                      /**/
-} syscon_dev_t;
-
-#ifdef __cplusplus
-}
-#endif
-extern syscon_dev_t SYSCON;
-#endif  /* _SOC_SYSCON_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/timer_group_reg.h b/tools/sdk/include/soc/soc/timer_group_reg.h
deleted file mode 100644
index 2db2a7e3f1b..00000000000
--- a/tools/sdk/include/soc/soc/timer_group_reg.h
+++ /dev/null
@@ -1,668 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __TIMG_REG_H__
-#define __TIMG_REG_H__
-#include "soc.h"
-
-/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
-#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for TIMG_WDT_STGx */
-#define TIMG_WDT_STG_SEL_OFF 0
-#define TIMG_WDT_STG_SEL_INT 1
-#define TIMG_WDT_STG_SEL_RESET_CPU 2
-#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
-
-
-#define REG_TIMG_BASE(i)       (DR_REG_TIMERGROUP0_BASE + i*0x1000)
-#define TIMG_T0CONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0000)
-/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When set  timer 0 time-base counter is enabled*/
-#define TIMG_T0_EN  (BIT(31))
-#define TIMG_T0_EN_M  (BIT(31))
-#define TIMG_T0_EN_V  0x1
-#define TIMG_T0_EN_S  31
-/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
-/*description: When set  timer 0 time-base counter increment. When cleared timer
- 0 time-base counter decrement.*/
-#define TIMG_T0_INCREASE  (BIT(30))
-#define TIMG_T0_INCREASE_M  (BIT(30))
-#define TIMG_T0_INCREASE_V  0x1
-#define TIMG_T0_INCREASE_S  30
-/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
-/*description: When set  timer 0 auto-reload at alarming is enabled*/
-#define TIMG_T0_AUTORELOAD  (BIT(29))
-#define TIMG_T0_AUTORELOAD_M  (BIT(29))
-#define TIMG_T0_AUTORELOAD_V  0x1
-#define TIMG_T0_AUTORELOAD_S  29
-/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
-/*description: Timer 0 clock (T0_clk) prescale value.*/
-#define TIMG_T0_DIVIDER  0x0000FFFF
-#define TIMG_T0_DIVIDER_M  ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
-#define TIMG_T0_DIVIDER_V  0xFFFF
-#define TIMG_T0_DIVIDER_S  13
-/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
-/*description: When set  edge type interrupt will be generated during alarm*/
-#define TIMG_T0_EDGE_INT_EN  (BIT(12))
-#define TIMG_T0_EDGE_INT_EN_M  (BIT(12))
-#define TIMG_T0_EDGE_INT_EN_V  0x1
-#define TIMG_T0_EDGE_INT_EN_S  12
-/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: When set  level type interrupt will be generated during alarm*/
-#define TIMG_T0_LEVEL_INT_EN  (BIT(11))
-#define TIMG_T0_LEVEL_INT_EN_M  (BIT(11))
-#define TIMG_T0_LEVEL_INT_EN_V  0x1
-#define TIMG_T0_LEVEL_INT_EN_S  11
-/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: When set  alarm is enabled*/
-#define TIMG_T0_ALARM_EN  (BIT(10))
-#define TIMG_T0_ALARM_EN_M  (BIT(10))
-#define TIMG_T0_ALARM_EN_V  0x1
-#define TIMG_T0_ALARM_EN_S  10
-
-#define TIMG_T0LO_REG(i)          (REG_TIMG_BASE(i) + 0x0004)
-/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Register to store timer 0 time-base counter current value lower 32 bits.*/
-#define TIMG_T0_LO  0xFFFFFFFF
-#define TIMG_T0_LO_M  ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
-#define TIMG_T0_LO_V  0xFFFFFFFF
-#define TIMG_T0_LO_S  0
-
-#define TIMG_T0HI_REG(i)          (REG_TIMG_BASE(i) + 0x0008)
-/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Register to store timer 0 time-base counter current value higher 32 bits.*/
-#define TIMG_T0_HI  0xFFFFFFFF
-#define TIMG_T0_HI_M  ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
-#define TIMG_T0_HI_V  0xFFFFFFFF
-#define TIMG_T0_HI_S  0
-
-#define TIMG_T0UPDATE_REG(i)          (REG_TIMG_BASE(i) + 0x000c)
-/* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Write any value will trigger a timer 0 time-base counter value
- update (timer 0 current value will be stored in registers above)*/
-#define TIMG_T0_UPDATE  0xFFFFFFFF
-#define TIMG_T0_UPDATE_M  ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S))
-#define TIMG_T0_UPDATE_V  0xFFFFFFFF
-#define TIMG_T0_UPDATE_S  0
-
-#define TIMG_T0ALARMLO_REG(i)          (REG_TIMG_BASE(i) + 0x0010)
-/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
-#define TIMG_T0_ALARM_LO  0xFFFFFFFF
-#define TIMG_T0_ALARM_LO_M  ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
-#define TIMG_T0_ALARM_LO_V  0xFFFFFFFF
-#define TIMG_T0_ALARM_LO_S  0
-
-#define TIMG_T0ALARMHI_REG(i)          (REG_TIMG_BASE(i) + 0x0014)
-/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
-#define TIMG_T0_ALARM_HI  0xFFFFFFFF
-#define TIMG_T0_ALARM_HI_M  ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
-#define TIMG_T0_ALARM_HI_V  0xFFFFFFFF
-#define TIMG_T0_ALARM_HI_S  0
-
-#define TIMG_T0LOADLO_REG(i)          (REG_TIMG_BASE(i) + 0x0018)
-/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Lower 32 bits of the value that will load into timer 0 time-base counter*/
-#define TIMG_T0_LOAD_LO  0xFFFFFFFF
-#define TIMG_T0_LOAD_LO_M  ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
-#define TIMG_T0_LOAD_LO_V  0xFFFFFFFF
-#define TIMG_T0_LOAD_LO_S  0
-
-#define TIMG_T0LOADHI_REG(i)          (REG_TIMG_BASE(i) + 0x001c)
-/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: higher 32 bits of the value that will load into timer 0 time-base counter*/
-#define TIMG_T0_LOAD_HI  0xFFFFFFFF
-#define TIMG_T0_LOAD_HI_M  ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
-#define TIMG_T0_LOAD_HI_V  0xFFFFFFFF
-#define TIMG_T0_LOAD_HI_S  0
-
-#define TIMG_T0LOAD_REG(i)          (REG_TIMG_BASE(i) + 0x0020)
-/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Write any value will trigger timer 0 time-base counter reload*/
-#define TIMG_T0_LOAD  0xFFFFFFFF
-#define TIMG_T0_LOAD_M  ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
-#define TIMG_T0_LOAD_V  0xFFFFFFFF
-#define TIMG_T0_LOAD_S  0
-
-#define TIMG_T1CONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0024)
-/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When set  timer 1 time-base counter is enabled*/
-#define TIMG_T1_EN  (BIT(31))
-#define TIMG_T1_EN_M  (BIT(31))
-#define TIMG_T1_EN_V  0x1
-#define TIMG_T1_EN_S  31
-/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
-/*description: When set  timer 1 time-base counter increment. When cleared timer
- 1 time-base counter decrement.*/
-#define TIMG_T1_INCREASE  (BIT(30))
-#define TIMG_T1_INCREASE_M  (BIT(30))
-#define TIMG_T1_INCREASE_V  0x1
-#define TIMG_T1_INCREASE_S  30
-/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
-/*description: When set  timer 1 auto-reload at alarming is enabled*/
-#define TIMG_T1_AUTORELOAD  (BIT(29))
-#define TIMG_T1_AUTORELOAD_M  (BIT(29))
-#define TIMG_T1_AUTORELOAD_V  0x1
-#define TIMG_T1_AUTORELOAD_S  29
-/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
-/*description: Timer 1 clock (T1_clk) prescale value.*/
-#define TIMG_T1_DIVIDER  0x0000FFFF
-#define TIMG_T1_DIVIDER_M  ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S))
-#define TIMG_T1_DIVIDER_V  0xFFFF
-#define TIMG_T1_DIVIDER_S  13
-/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
-/*description: When set  edge type interrupt will be generated during alarm*/
-#define TIMG_T1_EDGE_INT_EN  (BIT(12))
-#define TIMG_T1_EDGE_INT_EN_M  (BIT(12))
-#define TIMG_T1_EDGE_INT_EN_V  0x1
-#define TIMG_T1_EDGE_INT_EN_S  12
-/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: When set  level type interrupt will be generated during alarm*/
-#define TIMG_T1_LEVEL_INT_EN  (BIT(11))
-#define TIMG_T1_LEVEL_INT_EN_M  (BIT(11))
-#define TIMG_T1_LEVEL_INT_EN_V  0x1
-#define TIMG_T1_LEVEL_INT_EN_S  11
-/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: When set  alarm is enabled*/
-#define TIMG_T1_ALARM_EN  (BIT(10))
-#define TIMG_T1_ALARM_EN_M  (BIT(10))
-#define TIMG_T1_ALARM_EN_V  0x1
-#define TIMG_T1_ALARM_EN_S  10
-
-#define TIMG_T1LO_REG(i)          (REG_TIMG_BASE(i) + 0x0028)
-/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Register to store timer 1 time-base counter current value lower 32 bits.*/
-#define TIMG_T1_LO  0xFFFFFFFF
-#define TIMG_T1_LO_M  ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S))
-#define TIMG_T1_LO_V  0xFFFFFFFF
-#define TIMG_T1_LO_S  0
-
-#define TIMG_T1HI_REG(i)          (REG_TIMG_BASE(i) + 0x002c)
-/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Register to store timer 1 time-base counter current value higher 32 bits.*/
-#define TIMG_T1_HI  0xFFFFFFFF
-#define TIMG_T1_HI_M  ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S))
-#define TIMG_T1_HI_V  0xFFFFFFFF
-#define TIMG_T1_HI_S  0
-
-#define TIMG_T1UPDATE_REG(i)          (REG_TIMG_BASE(i) + 0x0030)
-/* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Write any value will trigger a timer 1 time-base counter value
- update (timer 1 current value will be stored in registers above)*/
-#define TIMG_T1_UPDATE  0xFFFFFFFF
-#define TIMG_T1_UPDATE_M  ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S))
-#define TIMG_T1_UPDATE_V  0xFFFFFFFF
-#define TIMG_T1_UPDATE_S  0
-
-#define TIMG_T1ALARMLO_REG(i)          (REG_TIMG_BASE(i) + 0x0034)
-/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Timer 1 time-base counter value lower 32 bits that will trigger the alarm*/
-#define TIMG_T1_ALARM_LO  0xFFFFFFFF
-#define TIMG_T1_ALARM_LO_M  ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S))
-#define TIMG_T1_ALARM_LO_V  0xFFFFFFFF
-#define TIMG_T1_ALARM_LO_S  0
-
-#define TIMG_T1ALARMHI_REG(i)          (REG_TIMG_BASE(i) + 0x0038)
-/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Timer 1 time-base counter value higher 32 bits that will trigger the alarm*/
-#define TIMG_T1_ALARM_HI  0xFFFFFFFF
-#define TIMG_T1_ALARM_HI_M  ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S))
-#define TIMG_T1_ALARM_HI_V  0xFFFFFFFF
-#define TIMG_T1_ALARM_HI_S  0
-
-#define TIMG_T1LOADLO_REG(i)          (REG_TIMG_BASE(i) + 0x003c)
-/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Lower 32 bits of the value that will load into timer 1 time-base counter*/
-#define TIMG_T1_LOAD_LO  0xFFFFFFFF
-#define TIMG_T1_LOAD_LO_M  ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S))
-#define TIMG_T1_LOAD_LO_V  0xFFFFFFFF
-#define TIMG_T1_LOAD_LO_S  0
-
-#define TIMG_T1LOADHI_REG(i)          (REG_TIMG_BASE(i) + 0x0040)
-/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: higher 32 bits of the value that will load into timer 1 time-base counter*/
-#define TIMG_T1_LOAD_HI  0xFFFFFFFF
-#define TIMG_T1_LOAD_HI_M  ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S))
-#define TIMG_T1_LOAD_HI_V  0xFFFFFFFF
-#define TIMG_T1_LOAD_HI_S  0
-
-#define TIMG_T1LOAD_REG(i)          (REG_TIMG_BASE(i) + 0x0044)
-/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Write any value will trigger timer 1 time-base counter reload*/
-#define TIMG_T1_LOAD  0xFFFFFFFF
-#define TIMG_T1_LOAD_M  ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S))
-#define TIMG_T1_LOAD_V  0xFFFFFFFF
-#define TIMG_T1_LOAD_S  0
-
-#define TIMG_WDTCONFIG0_REG(i)          (REG_TIMG_BASE(i) + 0x0048)
-/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: When set  SWDT is enabled*/
-#define TIMG_WDT_EN  (BIT(31))
-#define TIMG_WDT_EN_M  (BIT(31))
-#define TIMG_WDT_EN_V  0x1
-#define TIMG_WDT_EN_S  31
-/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */
-/*description: Stage 0 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system*/
-#define TIMG_WDT_STG0  0x00000003
-#define TIMG_WDT_STG0_M  ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
-#define TIMG_WDT_STG0_V  0x3
-#define TIMG_WDT_STG0_S  29
-/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */
-/*description: Stage 1 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system*/
-#define TIMG_WDT_STG1  0x00000003
-#define TIMG_WDT_STG1_M  ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
-#define TIMG_WDT_STG1_V  0x3
-#define TIMG_WDT_STG1_S  27
-/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */
-/*description: Stage 2 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system*/
-#define TIMG_WDT_STG2  0x00000003
-#define TIMG_WDT_STG2_M  ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
-#define TIMG_WDT_STG2_V  0x3
-#define TIMG_WDT_STG2_S  25
-/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */
-/*description: Stage 3 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system*/
-#define TIMG_WDT_STG3  0x00000003
-#define TIMG_WDT_STG3_M  ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
-#define TIMG_WDT_STG3_V  0x3
-#define TIMG_WDT_STG3_S  23
-/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
-/*description: When set  edge type interrupt generation is enabled*/
-#define TIMG_WDT_EDGE_INT_EN  (BIT(22))
-#define TIMG_WDT_EDGE_INT_EN_M  (BIT(22))
-#define TIMG_WDT_EDGE_INT_EN_V  0x1
-#define TIMG_WDT_EDGE_INT_EN_S  22
-/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
-/*description: When set  level type interrupt generation is enabled*/
-#define TIMG_WDT_LEVEL_INT_EN  (BIT(21))
-#define TIMG_WDT_LEVEL_INT_EN_M  (BIT(21))
-#define TIMG_WDT_LEVEL_INT_EN_V  0x1
-#define TIMG_WDT_LEVEL_INT_EN_S  21
-/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
-/*description: length of CPU reset selection. 0: 100ns  1: 200ns  2: 300ns 
- 3: 400ns  4: 500ns  5: 800ns  6: 1.6us  7: 3.2us*/
-#define TIMG_WDT_CPU_RESET_LENGTH  0x00000007
-#define TIMG_WDT_CPU_RESET_LENGTH_M  ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
-#define TIMG_WDT_CPU_RESET_LENGTH_V  0x7
-#define TIMG_WDT_CPU_RESET_LENGTH_S  18
-/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
-/*description: length of system reset selection. 0: 100ns  1: 200ns  2: 300ns
-  3: 400ns  4: 500ns  5: 800ns  6: 1.6us  7: 3.2us*/
-#define TIMG_WDT_SYS_RESET_LENGTH  0x00000007
-#define TIMG_WDT_SYS_RESET_LENGTH_M  ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
-#define TIMG_WDT_SYS_RESET_LENGTH_V  0x7
-#define TIMG_WDT_SYS_RESET_LENGTH_S  15
-/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
-/*description: When set  flash boot protection is enabled*/
-#define TIMG_WDT_FLASHBOOT_MOD_EN  (BIT(14))
-#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (BIT(14))
-#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x1
-#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
-
-#define TIMG_WDTCONFIG1_REG(i)          (REG_TIMG_BASE(i) + 0x004c)
-/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
-/*description: SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
-#define TIMG_WDT_CLK_PRESCALE  0x0000FFFF
-#define TIMG_WDT_CLK_PRESCALE_M  ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
-#define TIMG_WDT_CLK_PRESCALE_V  0xFFFF
-#define TIMG_WDT_CLK_PRESCALE_S  16
-
-#define TIMG_WDTCONFIG2_REG(i)          (REG_TIMG_BASE(i) + 0x0050)
-/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
-/*description: Stage 0 timeout value in SWDT clock cycles*/
-#define TIMG_WDT_STG0_HOLD  0xFFFFFFFF
-#define TIMG_WDT_STG0_HOLD_M  ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
-#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFF
-#define TIMG_WDT_STG0_HOLD_S  0
-
-#define TIMG_WDTCONFIG3_REG(i)          (REG_TIMG_BASE(i) + 0x0054)
-/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
-/*description: Stage 1 timeout value in SWDT clock cycles*/
-#define TIMG_WDT_STG1_HOLD  0xFFFFFFFF
-#define TIMG_WDT_STG1_HOLD_M  ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
-#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFF
-#define TIMG_WDT_STG1_HOLD_S  0
-
-#define TIMG_WDTCONFIG4_REG(i)          (REG_TIMG_BASE(i) + 0x0058)
-/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
-/*description: Stage 2 timeout value in SWDT clock cycles*/
-#define TIMG_WDT_STG2_HOLD  0xFFFFFFFF
-#define TIMG_WDT_STG2_HOLD_M  ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
-#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFF
-#define TIMG_WDT_STG2_HOLD_S  0
-
-#define TIMG_WDTCONFIG5_REG(i)          (REG_TIMG_BASE(i) + 0x005c)
-/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
-/*description: Stage 3 timeout value in SWDT clock cycles*/
-#define TIMG_WDT_STG3_HOLD  0xFFFFFFFF
-#define TIMG_WDT_STG3_HOLD_M  ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
-#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFF
-#define TIMG_WDT_STG3_HOLD_S  0
-
-#define TIMG_WDTFEED_REG(i)          (REG_TIMG_BASE(i) + 0x0060)
-/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Write any value will feed SWDT*/
-#define TIMG_WDT_FEED  0xFFFFFFFF
-#define TIMG_WDT_FEED_M  ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
-#define TIMG_WDT_FEED_V  0xFFFFFFFF
-#define TIMG_WDT_FEED_S  0
-
-#define TIMG_WDTWPROTECT_REG(i)          (REG_TIMG_BASE(i) + 0x0064)
-/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
-/*description: If change its value from default  then write protection is on.*/
-#define TIMG_WDT_WKEY  0xFFFFFFFF
-#define TIMG_WDT_WKEY_M  ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
-#define TIMG_WDT_WKEY_V  0xFFFFFFFF
-#define TIMG_WDT_WKEY_S  0
-
-#define TIMG_RTCCALICFG_REG(i)          (REG_TIMG_BASE(i) + 0x0068)
-/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_RTC_CALI_START  (BIT(31))
-#define TIMG_RTC_CALI_START_M  (BIT(31))
-#define TIMG_RTC_CALI_START_V  0x1
-#define TIMG_RTC_CALI_START_S  31
-/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
-/*description: */
-#define TIMG_RTC_CALI_MAX  0x00007FFF
-#define TIMG_RTC_CALI_MAX_M  ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
-#define TIMG_RTC_CALI_MAX_V  0x7FFF
-#define TIMG_RTC_CALI_MAX_S  16
-/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_RTC_CALI_RDY  (BIT(15))
-#define TIMG_RTC_CALI_RDY_M  (BIT(15))
-#define TIMG_RTC_CALI_RDY_V  0x1
-#define TIMG_RTC_CALI_RDY_S  15
-/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
-/*description: */
-#define TIMG_RTC_CALI_CLK_SEL  0x00000003
-#define TIMG_RTC_CALI_CLK_SEL_M  ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
-#define TIMG_RTC_CALI_CLK_SEL_V  0x3
-#define TIMG_RTC_CALI_CLK_SEL_S  13
-/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
-/*description: */
-#define TIMG_RTC_CALI_START_CYCLING  (BIT(12))
-#define TIMG_RTC_CALI_START_CYCLING_M  (BIT(12))
-#define TIMG_RTC_CALI_START_CYCLING_V  0x1
-#define TIMG_RTC_CALI_START_CYCLING_S  12
-
-#define TIMG_RTCCALICFG1_REG(i)          (REG_TIMG_BASE(i) + 0x006c)
-/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
-/*description: */
-#define TIMG_RTC_CALI_VALUE  0x01FFFFFF
-#define TIMG_RTC_CALI_VALUE_M  ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
-#define TIMG_RTC_CALI_VALUE_V  0x1FFFFFF
-#define TIMG_RTC_CALI_VALUE_S  7
-
-#define TIMG_LACTCONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0070)
-/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_LACT_EN  (BIT(31))
-#define TIMG_LACT_EN_M  (BIT(31))
-#define TIMG_LACT_EN_V  0x1
-#define TIMG_LACT_EN_S  31
-/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
-/*description: */
-#define TIMG_LACT_INCREASE  (BIT(30))
-#define TIMG_LACT_INCREASE_M  (BIT(30))
-#define TIMG_LACT_INCREASE_V  0x1
-#define TIMG_LACT_INCREASE_S  30
-/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
-/*description: */
-#define TIMG_LACT_AUTORELOAD  (BIT(29))
-#define TIMG_LACT_AUTORELOAD_M  (BIT(29))
-#define TIMG_LACT_AUTORELOAD_V  0x1
-#define TIMG_LACT_AUTORELOAD_S  29
-/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
-/*description: */
-#define TIMG_LACT_DIVIDER  0x0000FFFF
-#define TIMG_LACT_DIVIDER_M  ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S))
-#define TIMG_LACT_DIVIDER_V  0xFFFF
-#define TIMG_LACT_DIVIDER_S  13
-/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_LACT_EDGE_INT_EN  (BIT(12))
-#define TIMG_LACT_EDGE_INT_EN_M  (BIT(12))
-#define TIMG_LACT_EDGE_INT_EN_V  0x1
-#define TIMG_LACT_EDGE_INT_EN_S  12
-/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_LACT_LEVEL_INT_EN  (BIT(11))
-#define TIMG_LACT_LEVEL_INT_EN_M  (BIT(11))
-#define TIMG_LACT_LEVEL_INT_EN_V  0x1
-#define TIMG_LACT_LEVEL_INT_EN_S  11
-/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_LACT_ALARM_EN  (BIT(10))
-#define TIMG_LACT_ALARM_EN_M  (BIT(10))
-#define TIMG_LACT_ALARM_EN_V  0x1
-#define TIMG_LACT_ALARM_EN_S  10
-/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
-/*description: */
-#define TIMG_LACT_LAC_EN  (BIT(9))
-#define TIMG_LACT_LAC_EN_M  (BIT(9))
-#define TIMG_LACT_LAC_EN_V  0x1
-#define TIMG_LACT_LAC_EN_S  9
-/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
-/*description: */
-#define TIMG_LACT_CPST_EN  (BIT(8))
-#define TIMG_LACT_CPST_EN_M  (BIT(8))
-#define TIMG_LACT_CPST_EN_V  0x1
-#define TIMG_LACT_CPST_EN_S  8
-/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_LACT_RTC_ONLY  (BIT(7))
-#define TIMG_LACT_RTC_ONLY_M  (BIT(7))
-#define TIMG_LACT_RTC_ONLY_V  0x1
-#define TIMG_LACT_RTC_ONLY_S  7
-
-#define TIMG_LACTRTC_REG(i)          (REG_TIMG_BASE(i) + 0x0074)
-/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */
-/*description: */
-#define TIMG_LACT_RTC_STEP_LEN  0x03FFFFFF
-#define TIMG_LACT_RTC_STEP_LEN_M  ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S))
-#define TIMG_LACT_RTC_STEP_LEN_V  0x3FFFFFF
-#define TIMG_LACT_RTC_STEP_LEN_S  6
-
-#define TIMG_LACTLO_REG(i)          (REG_TIMG_BASE(i) + 0x0078)
-/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define TIMG_LACT_LO  0xFFFFFFFF
-#define TIMG_LACT_LO_M  ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S))
-#define TIMG_LACT_LO_V  0xFFFFFFFF
-#define TIMG_LACT_LO_S  0
-
-#define TIMG_LACTHI_REG(i)          (REG_TIMG_BASE(i) + 0x007c)
-/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define TIMG_LACT_HI  0xFFFFFFFF
-#define TIMG_LACT_HI_M  ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S))
-#define TIMG_LACT_HI_V  0xFFFFFFFF
-#define TIMG_LACT_HI_S  0
-
-#define TIMG_LACTUPDATE_REG(i)          (REG_TIMG_BASE(i) + 0x0080)
-/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define TIMG_LACT_UPDATE  0xFFFFFFFF
-#define TIMG_LACT_UPDATE_M  ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S))
-#define TIMG_LACT_UPDATE_V  0xFFFFFFFF
-#define TIMG_LACT_UPDATE_S  0
-
-#define TIMG_LACTALARMLO_REG(i)          (REG_TIMG_BASE(i) + 0x0084)
-/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define TIMG_LACT_ALARM_LO  0xFFFFFFFF
-#define TIMG_LACT_ALARM_LO_M  ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S))
-#define TIMG_LACT_ALARM_LO_V  0xFFFFFFFF
-#define TIMG_LACT_ALARM_LO_S  0
-
-#define TIMG_LACTALARMHI_REG(i)          (REG_TIMG_BASE(i) + 0x0088)
-/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define TIMG_LACT_ALARM_HI  0xFFFFFFFF
-#define TIMG_LACT_ALARM_HI_M  ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S))
-#define TIMG_LACT_ALARM_HI_V  0xFFFFFFFF
-#define TIMG_LACT_ALARM_HI_S  0
-
-#define TIMG_LACTLOADLO_REG(i)          (REG_TIMG_BASE(i) + 0x008c)
-/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define TIMG_LACT_LOAD_LO  0xFFFFFFFF
-#define TIMG_LACT_LOAD_LO_M  ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S))
-#define TIMG_LACT_LOAD_LO_V  0xFFFFFFFF
-#define TIMG_LACT_LOAD_LO_S  0
-
-#define TIMG_LACTLOADHI_REG(i)          (REG_TIMG_BASE(i) + 0x0090)
-/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define TIMG_LACT_LOAD_HI  0xFFFFFFFF
-#define TIMG_LACT_LOAD_HI_M  ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S))
-#define TIMG_LACT_LOAD_HI_V  0xFFFFFFFF
-#define TIMG_LACT_LOAD_HI_S  0
-
-#define TIMG_LACTLOAD_REG(i)          (REG_TIMG_BASE(i) + 0x0094)
-/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define TIMG_LACT_LOAD  0xFFFFFFFF
-#define TIMG_LACT_LOAD_M  ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S))
-#define TIMG_LACT_LOAD_V  0xFFFFFFFF
-#define TIMG_LACT_LOAD_S  0
-
-#define TIMG_INT_ENA_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x0098)
-/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_LACT_INT_ENA  (BIT(3))
-#define TIMG_LACT_INT_ENA_M  (BIT(3))
-#define TIMG_LACT_INT_ENA_V  0x1
-#define TIMG_LACT_INT_ENA_S  3
-/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Interrupt when an interrupt stage timeout*/
-#define TIMG_WDT_INT_ENA  (BIT(2))
-#define TIMG_WDT_INT_ENA_M  (BIT(2))
-#define TIMG_WDT_INT_ENA_V  0x1
-#define TIMG_WDT_INT_ENA_S  2
-/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: interrupt when timer1 alarm*/
-#define TIMG_T1_INT_ENA  (BIT(1))
-#define TIMG_T1_INT_ENA_M  (BIT(1))
-#define TIMG_T1_INT_ENA_V  0x1
-#define TIMG_T1_INT_ENA_S  1
-/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: interrupt when timer0 alarm*/
-#define TIMG_T0_INT_ENA  (BIT(0))
-#define TIMG_T0_INT_ENA_M  (BIT(0))
-#define TIMG_T0_INT_ENA_V  0x1
-#define TIMG_T0_INT_ENA_S  0
-
-#define TIMG_INT_RAW_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x009c)
-/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_LACT_INT_RAW  (BIT(3))
-#define TIMG_LACT_INT_RAW_M  (BIT(3))
-#define TIMG_LACT_INT_RAW_V  0x1
-#define TIMG_LACT_INT_RAW_S  3
-/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Interrupt when an interrupt stage timeout*/
-#define TIMG_WDT_INT_RAW  (BIT(2))
-#define TIMG_WDT_INT_RAW_M  (BIT(2))
-#define TIMG_WDT_INT_RAW_V  0x1
-#define TIMG_WDT_INT_RAW_S  2
-/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: interrupt when timer1 alarm*/
-#define TIMG_T1_INT_RAW  (BIT(1))
-#define TIMG_T1_INT_RAW_M  (BIT(1))
-#define TIMG_T1_INT_RAW_V  0x1
-#define TIMG_T1_INT_RAW_S  1
-/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: interrupt when timer0 alarm*/
-#define TIMG_T0_INT_RAW  (BIT(0))
-#define TIMG_T0_INT_RAW_M  (BIT(0))
-#define TIMG_T0_INT_RAW_V  0x1
-#define TIMG_T0_INT_RAW_S  0
-
-#define TIMG_INT_ST_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x00a0)
-/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_LACT_INT_ST  (BIT(3))
-#define TIMG_LACT_INT_ST_M  (BIT(3))
-#define TIMG_LACT_INT_ST_V  0x1
-#define TIMG_LACT_INT_ST_S  3
-/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Interrupt when an interrupt stage timeout*/
-#define TIMG_WDT_INT_ST  (BIT(2))
-#define TIMG_WDT_INT_ST_M  (BIT(2))
-#define TIMG_WDT_INT_ST_V  0x1
-#define TIMG_WDT_INT_ST_S  2
-/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: interrupt when timer1 alarm*/
-#define TIMG_T1_INT_ST  (BIT(1))
-#define TIMG_T1_INT_ST_M  (BIT(1))
-#define TIMG_T1_INT_ST_V  0x1
-#define TIMG_T1_INT_ST_S  1
-/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: interrupt when timer0 alarm*/
-#define TIMG_T0_INT_ST  (BIT(0))
-#define TIMG_T0_INT_ST_M  (BIT(0))
-#define TIMG_T0_INT_ST_V  0x1
-#define TIMG_T0_INT_ST_S  0
-
-#define TIMG_INT_CLR_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x00a4)
-/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: */
-#define TIMG_LACT_INT_CLR  (BIT(3))
-#define TIMG_LACT_INT_CLR_M  (BIT(3))
-#define TIMG_LACT_INT_CLR_V  0x1
-#define TIMG_LACT_INT_CLR_S  3
-/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Interrupt when an interrupt stage timeout*/
-#define TIMG_WDT_INT_CLR  (BIT(2))
-#define TIMG_WDT_INT_CLR_M  (BIT(2))
-#define TIMG_WDT_INT_CLR_V  0x1
-#define TIMG_WDT_INT_CLR_S  2
-/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: interrupt when timer1 alarm*/
-#define TIMG_T1_INT_CLR  (BIT(1))
-#define TIMG_T1_INT_CLR_M  (BIT(1))
-#define TIMG_T1_INT_CLR_V  0x1
-#define TIMG_T1_INT_CLR_S  1
-/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: interrupt when timer0 alarm*/
-#define TIMG_T0_INT_CLR  (BIT(0))
-#define TIMG_T0_INT_CLR_M  (BIT(0))
-#define TIMG_T0_INT_CLR_V  0x1
-#define TIMG_T0_INT_CLR_S  0
-
-#define TIMG_NTIMERS_DATE_REG(i)          (REG_TIMG_BASE(i) + 0x00f8)
-/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; */
-/*description: Version of this regfile*/
-#define TIMG_NTIMERS_DATE  0x0FFFFFFF
-#define TIMG_NTIMERS_DATE_M  ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
-#define TIMG_NTIMERS_DATE_V  0xFFFFFFF
-#define TIMG_NTIMERS_DATE_S  0
-
-#define TIMGCLK_REG(i)          (REG_TIMG_BASE(i) + 0x00fc)
-/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Force clock enable for this regfile*/
-#define TIMG_CLK_EN  (BIT(31))
-#define TIMG_CLK_EN_M  (BIT(31))
-#define TIMG_CLK_EN_V  0x1
-#define TIMG_CLK_EN_S  31
-
-
-
-
-#endif /*__TIMG_REG_H__ */
-
-
diff --git a/tools/sdk/include/soc/soc/timer_group_struct.h b/tools/sdk/include/soc/soc/timer_group_struct.h
deleted file mode 100644
index 6d312969d49..00000000000
--- a/tools/sdk/include/soc/soc/timer_group_struct.h
+++ /dev/null
@@ -1,207 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_TIMG_STRUCT_H_
-#define _SOC_TIMG_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    struct{
-        union {
-            struct {
-                uint32_t reserved0:   10;
-                uint32_t alarm_en:     1;             /*When set  alarm is enabled*/
-                uint32_t level_int_en: 1;             /*When set  level type interrupt will be generated during alarm*/
-                uint32_t edge_int_en:  1;             /*When set  edge type interrupt will be generated during alarm*/
-                uint32_t divider:     16;             /*Timer clock (T0/1_clk) pre-scale value.*/
-                uint32_t autoreload:   1;             /*When set  timer 0/1 auto-reload at alarming is enabled*/
-                uint32_t increase:     1;             /*When set  timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/
-                uint32_t enable:       1;             /*When set  timer 0/1 time-base counter is enabled*/
-            };
-            uint32_t val;
-        } config;
-        uint32_t cnt_low;                             /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
-        uint32_t cnt_high;                            /*Register to store timer 0 time-base counter current value higher 32 bits.*/
-        uint32_t update;                              /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
-        uint32_t alarm_low;                           /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
-        uint32_t alarm_high;                          /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
-        uint32_t load_low;                            /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
-        uint32_t load_high;                           /*higher 32 bits of the value that will load into timer 0 time-base counter*/
-        uint32_t reload;                              /*Write any value will trigger timer 0 time-base counter reload*/
-    } hw_timer[2];
-    union {
-        struct {
-            uint32_t reserved0:       14;
-            uint32_t flashboot_mod_en: 1;             /*When set  flash boot protection is enabled*/
-            uint32_t sys_reset_length: 3;             /*length of system reset selection. 0: 100ns  1: 200ns  2: 300ns  3: 400ns  4: 500ns  5: 800ns  6: 1.6us  7: 3.2us*/
-            uint32_t cpu_reset_length: 3;             /*length of CPU reset selection. 0: 100ns  1: 200ns  2: 300ns  3: 400ns  4: 500ns  5: 800ns  6: 1.6us  7: 3.2us*/
-            uint32_t level_int_en:     1;             /*When set  level type interrupt generation is enabled*/
-            uint32_t edge_int_en:      1;             /*When set  edge type interrupt generation is enabled*/
-            uint32_t stg3:             2;             /*Stage 3 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system*/
-            uint32_t stg2:             2;             /*Stage 2 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system*/
-            uint32_t stg1:             2;             /*Stage 1 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system*/
-            uint32_t stg0:             2;             /*Stage 0 configuration. 0: off  1: interrupt  2: reset CPU  3: reset system*/
-            uint32_t en:               1;             /*When set  SWDT is enabled*/
-        };
-        uint32_t val;
-    } wdt_config0;
-    union {
-        struct {
-            uint32_t reserved0:       16;
-            uint32_t clk_prescale:16;             /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
-        };
-        uint32_t val;
-    } wdt_config1;
-    uint32_t wdt_config2;                             /*Stage 0 timeout value in SWDT clock cycles*/
-    uint32_t wdt_config3;                             /*Stage 1 timeout value in SWDT clock cycles*/
-    uint32_t wdt_config4;                             /*Stage 2 timeout value in SWDT clock cycles*/
-    uint32_t wdt_config5;                             /*Stage 3 timeout value in SWDT clock cycles*/
-    uint32_t wdt_feed;                                /*Write any value will feed SWDT*/
-    uint32_t wdt_wprotect;                            /*If change its value from default  then write protection is on.*/
-    union {
-        struct {
-            uint32_t reserved0:             12;
-            uint32_t start_cycling: 1;
-            uint32_t clk_sel:       2;
-            uint32_t rdy:           1;
-            uint32_t max:          15;
-            uint32_t start:         1;
-        };
-        uint32_t val;
-    } rtc_cali_cfg;
-    union {
-        struct {
-            uint32_t reserved0:      7;
-            uint32_t value:25;
-        };
-        uint32_t val;
-    } rtc_cali_cfg1;
-    union {
-        struct {
-            uint32_t reserved0:         7;
-            uint32_t rtc_only:     1;
-            uint32_t cpst_en:      1;
-            uint32_t lac_en:       1;
-            uint32_t alarm_en:     1;
-            uint32_t level_int_en: 1;
-            uint32_t edge_int_en:  1;
-            uint32_t divider:     16;
-            uint32_t autoreload:   1;
-            uint32_t increase:     1;
-            uint32_t en:           1;
-        };
-        uint32_t val;
-    } lactconfig;
-    union {
-        struct {
-            uint32_t reserved0:         6;
-            uint32_t step_len:26;
-        };
-        uint32_t val;
-    } lactrtc;
-    uint32_t lactlo;                                  /**/
-    uint32_t lacthi;                                  /**/
-    uint32_t lactupdate;                              /**/
-    uint32_t lactalarmlo;                             /**/
-    uint32_t lactalarmhi;                             /**/
-    uint32_t lactloadlo;                              /**/
-    uint32_t lactloadhi;                              /**/
-    uint32_t lactload;                                /**/
-    union {
-        struct {
-            uint32_t t0:         1;                   /*interrupt when timer0 alarm*/
-            uint32_t t1:         1;                   /*interrupt when timer1 alarm*/
-            uint32_t wdt:        1;                   /*Interrupt when an interrupt stage timeout*/
-            uint32_t lact:       1;
-            uint32_t reserved4: 28;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t t0:        1;                    /*interrupt when timer0 alarm*/
-            uint32_t t1:        1;                    /*interrupt when timer1 alarm*/
-            uint32_t wdt:       1;                    /*Interrupt when an interrupt stage timeout*/
-            uint32_t lact:      1;
-            uint32_t reserved4:28;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t t0:         1;                   /*interrupt when timer0 alarm*/
-            uint32_t t1:         1;                   /*interrupt when timer1 alarm*/
-            uint32_t wdt:        1;                   /*Interrupt when an interrupt stage timeout*/
-            uint32_t lact:       1;
-            uint32_t reserved4: 28;
-        };
-        uint32_t val;
-    } int_st_timers;
-    union {
-        struct {
-            uint32_t t0:         1;                   /*interrupt when timer0 alarm*/
-            uint32_t t1:         1;                   /*interrupt when timer1 alarm*/
-            uint32_t wdt:        1;                   /*Interrupt when an interrupt stage timeout*/
-            uint32_t lact:       1;
-            uint32_t reserved4: 28;
-        };
-        uint32_t val;
-    } int_clr_timers;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    union {
-        struct {
-            uint32_t date:28;                         /*Version of this regfile*/
-            uint32_t reserved28:   4;
-        };
-        uint32_t val;
-    } timg_date;
-    union {
-        struct {
-            uint32_t reserved0: 31;
-            uint32_t en:     1;                   /*Force clock enable for this regfile*/
-        };
-        uint32_t val;
-    } clk;
-} timg_dev_t;
-extern timg_dev_t TIMERG0;
-extern timg_dev_t TIMERG1;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_TIMG_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/touch_channel.h b/tools/sdk/include/soc/soc/touch_channel.h
deleted file mode 100644
index a9aa838b4e0..00000000000
--- a/tools/sdk/include/soc/soc/touch_channel.h
+++ /dev/null
@@ -1,49 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_TOUCH_CHANNEL_H
-#define _SOC_TOUCH_CHANNEL_H
-
-//Touch channels
-#define TOUCH_PAD_GPIO4_CHANNEL     TOUCH_PAD_NUM0
-#define TOUCH_PAD_NUM0_GPIO_NUM     4
-
-#define TOUCH_PAD_GPIO0_CHANNEL     TOUCH_PAD_NUM1
-#define TOUCH_PAD_NUM1_GPIO_NUM     0
-
-#define TOUCH_PAD_GPIO2_CHANNEL     TOUCH_PAD_NUM2
-#define TOUCH_PAD_NUM2_GPIO_NUM     2
-
-#define TOUCH_PAD_GPIO15_CHANNEL    TOUCH_PAD_NUM3
-#define TOUCH_PAD_NUM3_GPIO_NUM     15
-
-#define TOUCH_PAD_GPIO13_CHANNEL    TOUCH_PAD_NUM4
-#define TOUCH_PAD_NUM4_GPIO_NUM     13
-
-#define TOUCH_PAD_GPIO12_CHANNEL    TOUCH_PAD_NUM5
-#define TOUCH_PAD_NUM5_GPIO_NUM     12
-
-#define TOUCH_PAD_GPIO14_CHANNEL    TOUCH_PAD_NUM6
-#define TOUCH_PAD_NUM6_GPIO_NUM     14
-
-#define TOUCH_PAD_GPIO27_CHANNEL    TOUCH_PAD_NUM7
-#define TOUCH_PAD_NUM7_GPIO_NUM     27
-
-#define TOUCH_PAD_GPIO33_CHANNEL    TOUCH_PAD_NUM8
-#define TOUCH_PAD_NUM8_GPIO_NUM     33
-
-#define TOUCH_PAD_GPIO32_CHANNEL    TOUCH_PAD_NUM9
-#define TOUCH_PAD_NUM9_GPIO_NUM     32
-
-#endif
diff --git a/tools/sdk/include/soc/soc/uart_channel.h b/tools/sdk/include/soc/soc/uart_channel.h
deleted file mode 100644
index 5b8dc56d5ae..00000000000
--- a/tools/sdk/include/soc/soc/uart_channel.h
+++ /dev/null
@@ -1,61 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _SOC_UART_CHANNEL_H
-#define _SOC_UART_CHANNEL_H
-
-//UART channels
-#define UART_GPIO1_DIRECT_CHANNEL       UART_NUM_0
-#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  1
-#define UART_GPIO3_DIRECT_CHANNEL       UART_NUM_0
-#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  3
-#define UART_GPIO19_DIRECT_CHANNEL      UART_NUM_0
-#define UART_NUM_0_CTS_DIRECT_GPIO_NUM  19
-#define UART_GPIO22_DIRECT_CHANNEL      UART_NUM_0
-#define UART_NUM_0_RTS_DIRECT_GPIO_NUM  22
-
-#define UART_TXD_GPIO1_DIRECT_CHANNEL   UART_GPIO1_DIRECT_CHANNEL
-#define UART_RXD_GPIO3_DIRECT_CHANNEL   UART_GPIO3_DIRECT_CHANNEL
-#define UART_CTS_GPIO19_DIRECT_CHANNEL  UART_GPIO19_DIRECT_CHANNEL
-#define UART_RTS_GPIO22_DIRECT_CHANNEL  UART_GPIO22_DIRECT_CHANNEL
-
-#define UART_GPIO10_DIRECT_CHANNEL      UART_NUM_1
-#define UART_NUM_1_TXD_DIRECT_GPIO_NUM  10
-#define UART_GPIO9_DIRECT_CHANNEL       UART_NUM_1
-#define UART_NUM_1_RXD_DIRECT_GPIO_NUM  9
-#define UART_GPIO6_DIRECT_CHANNEL       UART_NUM_1
-#define UART_NUM_1_CTS_DIRECT_GPIO_NUM  6
-#define UART_GPIO11_DIRECT_CHANNEL      UART_NUM_1
-#define UART_NUM_1_RTS_DIRECT_GPIO_NUM  11
-
-#define UART_TXD_GPIO10_DIRECT_CHANNEL  UART_GPIO10_DIRECT_CHANNEL
-#define UART_RXD_GPIO9_DIRECT_CHANNEL   UART_GPIO9_DIRECT_CHANNEL
-#define UART_CTS_GPIO6_DIRECT_CHANNEL   UART_GPIO6_DIRECT_CHANNEL
-#define UART_RTS_GPIO11_DIRECT_CHANNEL  UART_GPIO11_DIRECT_CHANNEL
-
-#define UART_GPIO17_DIRECT_CHANNEL      UART_NUM_2
-#define UART_NUM_2_TXD_DIRECT_GPIO_NUM  17
-#define UART_GPIO16_DIRECT_CHANNEL      UART_NUM_2
-#define UART_NUM_2_RXD_DIRECT_GPIO_NUM  16
-#define UART_GPIO8_DIRECT_CHANNEL       UART_NUM_2
-#define UART_NUM_2_CTS_DIRECT_GPIO_NUM  8
-#define UART_GPIO7_DIRECT_CHANNEL       UART_NUM_2
-#define UART_NUM_2_RTS_DIRECT_GPIO_NUM  7
-
-#define UART_TXD_GPIO17_DIRECT_CHANNEL  UART_GPIO17_DIRECT_CHANNEL
-#define UART_RXD_GPIO16_DIRECT_CHANNEL  UART_GPIO16_DIRECT_CHANNEL
-#define UART_CTS_GPIO8_DIRECT_CHANNEL   UART_GPIO8_DIRECT_CHANNEL
-#define UART_RTS_GPIO7_DIRECT_CHANNEL   UART_GPIO7_DIRECT_CHANNEL
-
-#endif
diff --git a/tools/sdk/include/soc/soc/uart_reg.h b/tools/sdk/include/soc/soc/uart_reg.h
deleted file mode 100644
index 33b6e998edf..00000000000
--- a/tools/sdk/include/soc/soc/uart_reg.h
+++ /dev/null
@@ -1,1180 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef __UART_REG_H__
-#define __UART_REG_H__
-
-
-#include "soc.h"
-
-#define REG_UART_BASE( i )  (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
-#define REG_UART_AHB_BASE(i)  (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
-#define UART_FIFO_AHB_REG(i)  (REG_UART_AHB_BASE(i) + 0x0)
-#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
-
-/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: This register stores one byte data  read by rx fifo.*/
-#define UART_RXFIFO_RD_BYTE  0x000000FF
-#define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
-#define UART_RXFIFO_RD_BYTE_V  0xFF
-#define UART_RXFIFO_RD_BYTE_S  0
-
-#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
-/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- the configured at_cmd chars.*/
-#define UART_AT_CMD_CHAR_DET_INT_RAW  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when rs485 detects
- the clash between transmitter and receiver.*/
-#define UART_RS485_CLASH_INT_RAW  (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_V  0x1
-#define UART_RS485_CLASH_INT_RAW_S  17
-/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when rs485 detects
- the data frame error.*/
-#define UART_RS485_FRM_ERR_INT_RAW  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_V  0x1
-#define UART_RS485_FRM_ERR_INT_RAW_S  16
-/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/
-#define UART_RS485_PARITY_ERR_INT_RAW  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
-#define UART_RS485_PARITY_ERR_INT_RAW_S  15
-/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter has
- send all the data in fifo.*/
-#define UART_TX_DONE_INT_RAW  (BIT(14))
-#define UART_TX_DONE_INT_RAW_M  (BIT(14))
-#define UART_TX_DONE_INT_RAW_V  0x1
-#define UART_TX_DONE_INT_RAW_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter has
- kept the shortest duration after the  last data has been send.*/
-#define UART_TX_BRK_IDLE_DONE_INT_RAW  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter completes
-  sendding  0 after all the datas in transmitter's fifo are send.*/
-#define UART_TX_BRK_DONE_INT_RAW  (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_V  0x1
-#define UART_TX_BRK_DONE_INT_RAW_S  12
-/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/
-#define UART_GLITCH_DET_INT_RAW  (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_V  0x1
-#define UART_GLITCH_DET_INT_RAW_S  11
-/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives
- xon char with uart_sw_flow_con_en is set to 1.*/
-#define UART_SW_XOFF_INT_RAW  (BIT(10))
-#define UART_SW_XOFF_INT_RAW_M  (BIT(10))
-#define UART_SW_XOFF_INT_RAW_V  0x1
-#define UART_SW_XOFF_INT_RAW_S  10
-/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives
- xoff char with uart_sw_flow_con_en is set to 1.*/
-#define UART_SW_XON_INT_RAW  (BIT(9))
-#define UART_SW_XON_INT_RAW_M  (BIT(9))
-#define UART_SW_XON_INT_RAW_V  0x1
-#define UART_SW_XON_INT_RAW_S  9
-/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver takes
- more time than rx_tout_thrhd to receive a byte.*/
-#define UART_RXFIFO_TOUT_INT_RAW  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_V  0x1
-#define UART_RXFIFO_TOUT_INT_RAW_S  8
-/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- the 0 after the stop bit.*/
-#define UART_BRK_DET_INT_RAW  (BIT(7))
-#define UART_BRK_DET_INT_RAW_M  (BIT(7))
-#define UART_BRK_DET_INT_RAW_V  0x1
-#define UART_BRK_DET_INT_RAW_S  7
-/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- the edge change of ctsn signal.*/
-#define UART_CTS_CHG_INT_RAW  (BIT(6))
-#define UART_CTS_CHG_INT_RAW_M  (BIT(6))
-#define UART_CTS_CHG_INT_RAW_V  0x1
-#define UART_CTS_CHG_INT_RAW_S  6
-/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- the edge change of dsrn signal.*/
-#define UART_DSR_CHG_INT_RAW  (BIT(5))
-#define UART_DSR_CHG_INT_RAW_M  (BIT(5))
-#define UART_DSR_CHG_INT_RAW_V  0x1
-#define UART_DSR_CHG_INT_RAW_S  5
-/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives
- more data than the fifo can store.*/
-#define UART_RXFIFO_OVF_INT_RAW  (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_V  0x1
-#define UART_RXFIFO_OVF_INT_RAW_S  4
-/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- data's frame error .*/
-#define UART_FRM_ERR_INT_RAW  (BIT(3))
-#define UART_FRM_ERR_INT_RAW_M  (BIT(3))
-#define UART_FRM_ERR_INT_RAW_V  0x1
-#define UART_FRM_ERR_INT_RAW_S  3
-/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- the parity error of data.*/
-#define UART_PARITY_ERR_INT_RAW  (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_V  0x1
-#define UART_PARITY_ERR_INT_RAW_S  2
-/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when the amount of
- data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
-#define UART_TXFIFO_EMPTY_INT_RAW  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
-#define UART_TXFIFO_EMPTY_INT_RAW_S  1
-/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives
- more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
-#define UART_RXFIFO_FULL_INT_RAW  (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_V  0x1
-#define UART_RXFIFO_FULL_INT_RAW_S  0
-
-#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
-/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena
- is set to 1.*/
-#define UART_AT_CMD_CHAR_DET_INT_ST  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena
- is set to 1.*/
-#define UART_RS485_CLASH_INT_ST  (BIT(17))
-#define UART_RS485_CLASH_INT_ST_M  (BIT(17))
-#define UART_RS485_CLASH_INT_ST_V  0x1
-#define UART_RS485_CLASH_INT_ST_S  17
-/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena
- is set to 1.*/
-#define UART_RS485_FRM_ERR_INT_ST  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_V  0x1
-#define UART_RS485_FRM_ERR_INT_ST_S  16
-/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena
- is set to 1.*/
-#define UART_RS485_PARITY_ERR_INT_ST  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_V  0x1
-#define UART_RS485_PARITY_ERR_INT_ST_S  15
-/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
-#define UART_TX_DONE_INT_ST  (BIT(14))
-#define UART_TX_DONE_INT_ST_M  (BIT(14))
-#define UART_TX_DONE_INT_ST_V  0x1
-#define UART_TX_DONE_INT_ST_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- is set to 1.*/
-#define UART_TX_BRK_IDLE_DONE_INT_ST  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena
- is set to 1.*/
-#define UART_TX_BRK_DONE_INT_ST  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_V  0x1
-#define UART_TX_BRK_DONE_INT_ST_S  12
-/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena
- is set to 1.*/
-#define UART_GLITCH_DET_INT_ST  (BIT(11))
-#define UART_GLITCH_DET_INT_ST_M  (BIT(11))
-#define UART_GLITCH_DET_INT_ST_V  0x1
-#define UART_GLITCH_DET_INT_ST_S  11
-/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
-#define UART_SW_XOFF_INT_ST  (BIT(10))
-#define UART_SW_XOFF_INT_ST_M  (BIT(10))
-#define UART_SW_XOFF_INT_ST_V  0x1
-#define UART_SW_XOFF_INT_ST_S  10
-/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
-#define UART_SW_XON_INT_ST  (BIT(9))
-#define UART_SW_XON_INT_ST_M  (BIT(9))
-#define UART_SW_XON_INT_ST_V  0x1
-#define UART_SW_XON_INT_ST_S  9
-/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena
- is set to 1.*/
-#define UART_RXFIFO_TOUT_INT_ST  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_V  0x1
-#define UART_RXFIFO_TOUT_INT_ST_S  8
-/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
-#define UART_BRK_DET_INT_ST  (BIT(7))
-#define UART_BRK_DET_INT_ST_M  (BIT(7))
-#define UART_BRK_DET_INT_ST_V  0x1
-#define UART_BRK_DET_INT_ST_S  7
-/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
-#define UART_CTS_CHG_INT_ST  (BIT(6))
-#define UART_CTS_CHG_INT_ST_M  (BIT(6))
-#define UART_CTS_CHG_INT_ST_V  0x1
-#define UART_CTS_CHG_INT_ST_S  6
-/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
-#define UART_DSR_CHG_INT_ST  (BIT(5))
-#define UART_DSR_CHG_INT_ST_M  (BIT(5))
-#define UART_DSR_CHG_INT_ST_V  0x1
-#define UART_DSR_CHG_INT_ST_S  5
-/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena
- is set to 1.*/
-#define UART_RXFIFO_OVF_INT_ST  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_V  0x1
-#define UART_RXFIFO_OVF_INT_ST_S  4
-/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
-#define UART_FRM_ERR_INT_ST  (BIT(3))
-#define UART_FRM_ERR_INT_ST_M  (BIT(3))
-#define UART_FRM_ERR_INT_ST_V  0x1
-#define UART_FRM_ERR_INT_ST_S  3
-/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena
- is set to 1.*/
-#define UART_PARITY_ERR_INT_ST  (BIT(2))
-#define UART_PARITY_ERR_INT_ST_M  (BIT(2))
-#define UART_PARITY_ERR_INT_ST_V  0x1
-#define UART_PARITY_ERR_INT_ST_S  2
-/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena
- is set to 1.*/
-#define UART_TXFIFO_EMPTY_INT_ST  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_V  0x1
-#define UART_TXFIFO_EMPTY_INT_ST_S  1
-/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena
- is set to 1.*/
-#define UART_RXFIFO_FULL_INT_ST  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_V  0x1
-#define UART_RXFIFO_FULL_INT_ST_S  0
-
-#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
-/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This is the enable bit for at_cmd_char_det_int_st register.*/
-#define UART_AT_CMD_CHAR_DET_INT_ENA  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_clash_int_st register.*/
-#define UART_RS485_CLASH_INT_ENA  (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_V  0x1
-#define UART_RS485_CLASH_INT_ENA_S  17
-/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_parity_err_int_st register.*/
-#define UART_RS485_FRM_ERR_INT_ENA  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_V  0x1
-#define UART_RS485_FRM_ERR_INT_ENA_S  16
-/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_parity_err_int_st register.*/
-#define UART_RS485_PARITY_ERR_INT_ENA  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
-#define UART_RS485_PARITY_ERR_INT_ENA_S  15
-/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_done_int_st register.*/
-#define UART_TX_DONE_INT_ENA  (BIT(14))
-#define UART_TX_DONE_INT_ENA_M  (BIT(14))
-#define UART_TX_DONE_INT_ENA_V  0x1
-#define UART_TX_DONE_INT_ENA_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/
-#define UART_TX_BRK_IDLE_DONE_INT_ENA  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_brk_done_int_st register.*/
-#define UART_TX_BRK_DONE_INT_ENA  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_V  0x1
-#define UART_TX_BRK_DONE_INT_ENA_S  12
-/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This is the enable bit for glitch_det_int_st register.*/
-#define UART_GLITCH_DET_INT_ENA  (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_V  0x1
-#define UART_GLITCH_DET_INT_ENA_S  11
-/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the enable bit for sw_xoff_int_st register.*/
-#define UART_SW_XOFF_INT_ENA  (BIT(10))
-#define UART_SW_XOFF_INT_ENA_M  (BIT(10))
-#define UART_SW_XOFF_INT_ENA_V  0x1
-#define UART_SW_XOFF_INT_ENA_S  10
-/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This is the enable bit for sw_xon_int_st register.*/
-#define UART_SW_XON_INT_ENA  (BIT(9))
-#define UART_SW_XON_INT_ENA_M  (BIT(9))
-#define UART_SW_XON_INT_ENA_V  0x1
-#define UART_SW_XON_INT_ENA_S  9
-/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_tout_int_st register.*/
-#define UART_RXFIFO_TOUT_INT_ENA  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_V  0x1
-#define UART_RXFIFO_TOUT_INT_ENA_S  8
-/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the enable bit for brk_det_int_st register.*/
-#define UART_BRK_DET_INT_ENA  (BIT(7))
-#define UART_BRK_DET_INT_ENA_M  (BIT(7))
-#define UART_BRK_DET_INT_ENA_V  0x1
-#define UART_BRK_DET_INT_ENA_S  7
-/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the enable bit for cts_chg_int_st register.*/
-#define UART_CTS_CHG_INT_ENA  (BIT(6))
-#define UART_CTS_CHG_INT_ENA_M  (BIT(6))
-#define UART_CTS_CHG_INT_ENA_V  0x1
-#define UART_CTS_CHG_INT_ENA_S  6
-/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the enable bit for dsr_chg_int_st register.*/
-#define UART_DSR_CHG_INT_ENA  (BIT(5))
-#define UART_DSR_CHG_INT_ENA_M  (BIT(5))
-#define UART_DSR_CHG_INT_ENA_V  0x1
-#define UART_DSR_CHG_INT_ENA_S  5
-/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_ovf_int_st register.*/
-#define UART_RXFIFO_OVF_INT_ENA  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_V  0x1
-#define UART_RXFIFO_OVF_INT_ENA_S  4
-/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the enable bit for frm_err_int_st register.*/
-#define UART_FRM_ERR_INT_ENA  (BIT(3))
-#define UART_FRM_ERR_INT_ENA_M  (BIT(3))
-#define UART_FRM_ERR_INT_ENA_V  0x1
-#define UART_FRM_ERR_INT_ENA_S  3
-/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the enable bit for parity_err_int_st register.*/
-#define UART_PARITY_ERR_INT_ENA  (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_V  0x1
-#define UART_PARITY_ERR_INT_ENA_S  2
-/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_full_int_st register.*/
-#define UART_TXFIFO_EMPTY_INT_ENA  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
-#define UART_TXFIFO_EMPTY_INT_ENA_S  1
-/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_full_int_st register.*/
-#define UART_RXFIFO_FULL_INT_ENA  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_V  0x1
-#define UART_RXFIFO_FULL_INT_ENA_S  0
-
-#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
-/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
-#define UART_AT_CMD_CHAR_DET_INT_CLR  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/
-#define UART_RS485_CLASH_INT_CLR  (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_V  0x1
-#define UART_RS485_CLASH_INT_CLR_S  17
-/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
-#define UART_RS485_FRM_ERR_INT_CLR  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_V  0x1
-#define UART_RS485_FRM_ERR_INT_CLR_S  16
-/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
-#define UART_RS485_PARITY_ERR_INT_CLR  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
-#define UART_RS485_PARITY_ERR_INT_CLR_S  15
-/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_done_int_raw interrupt.*/
-#define UART_TX_DONE_INT_CLR  (BIT(14))
-#define UART_TX_DONE_INT_CLR_M  (BIT(14))
-#define UART_TX_DONE_INT_CLR_V  0x1
-#define UART_TX_DONE_INT_CLR_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
-#define UART_TX_BRK_IDLE_DONE_INT_CLR  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/
-#define UART_TX_BRK_DONE_INT_CLR  (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_V  0x1
-#define UART_TX_BRK_DONE_INT_CLR_S  12
-/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/
-#define UART_GLITCH_DET_INT_CLR  (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_V  0x1
-#define UART_GLITCH_DET_INT_CLR_S  11
-/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/
-#define UART_SW_XOFF_INT_CLR  (BIT(10))
-#define UART_SW_XOFF_INT_CLR_M  (BIT(10))
-#define UART_SW_XOFF_INT_CLR_V  0x1
-#define UART_SW_XOFF_INT_CLR_S  10
-/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/
-#define UART_SW_XON_INT_CLR  (BIT(9))
-#define UART_SW_XON_INT_CLR_M  (BIT(9))
-#define UART_SW_XON_INT_CLR_V  0x1
-#define UART_SW_XON_INT_CLR_S  9
-/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
-#define UART_RXFIFO_TOUT_INT_CLR  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_V  0x1
-#define UART_RXFIFO_TOUT_INT_CLR_S  8
-/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to clear the brk_det_int_raw interrupt.*/
-#define UART_BRK_DET_INT_CLR  (BIT(7))
-#define UART_BRK_DET_INT_CLR_M  (BIT(7))
-#define UART_BRK_DET_INT_CLR_V  0x1
-#define UART_BRK_DET_INT_CLR_S  7
-/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/
-#define UART_CTS_CHG_INT_CLR  (BIT(6))
-#define UART_CTS_CHG_INT_CLR_M  (BIT(6))
-#define UART_CTS_CHG_INT_CLR_V  0x1
-#define UART_CTS_CHG_INT_CLR_S  6
-/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/
-#define UART_DSR_CHG_INT_CLR  (BIT(5))
-#define UART_DSR_CHG_INT_CLR_M  (BIT(5))
-#define UART_DSR_CHG_INT_CLR_V  0x1
-#define UART_DSR_CHG_INT_CLR_S  5
-/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
-#define UART_RXFIFO_OVF_INT_CLR  (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_V  0x1
-#define UART_RXFIFO_OVF_INT_CLR_S  4
-/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear frm_err_int_raw interrupt.*/
-#define UART_FRM_ERR_INT_CLR  (BIT(3))
-#define UART_FRM_ERR_INT_CLR_M  (BIT(3))
-#define UART_FRM_ERR_INT_CLR_V  0x1
-#define UART_FRM_ERR_INT_CLR_S  3
-/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear parity_err_int_raw interrupt.*/
-#define UART_PARITY_ERR_INT_CLR  (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_V  0x1
-#define UART_PARITY_ERR_INT_CLR_S  2
-/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/
-#define UART_TXFIFO_EMPTY_INT_CLR  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
-#define UART_TXFIFO_EMPTY_INT_CLR_S  1
-/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/
-#define UART_RXFIFO_FULL_INT_CLR  (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_V  0x1
-#define UART_RXFIFO_FULL_INT_CLR_S  0
-
-#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
-/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
-/*description: The register  value is the decimal part of the frequency divider's factor.*/
-#define UART_CLKDIV_FRAG  0x0000000F
-#define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
-#define UART_CLKDIV_FRAG_V  0xF
-#define UART_CLKDIV_FRAG_S  20
-/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */
-/*description: The register value is  the  integer part of the frequency divider's factor.*/
-#define UART_CLKDIV  0x000FFFFF
-#define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
-#define UART_CLKDIV_V  0xFFFFF
-#define UART_CLKDIV_S  0
-
-#define UART_AUTOBAUD_REG(i)          (REG_UART_BASE(i) + 0x18)
-/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */
-/*description: when input pulse width is lower then this value igore this pulse.this
- register is used in autobaud detect process.*/
-#define UART_GLITCH_FILT  0x000000FF
-#define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
-#define UART_GLITCH_FILT_V  0xFF
-#define UART_GLITCH_FILT_S  8
-/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the enable bit for detecting baudrate.*/
-#define UART_AUTOBAUD_EN  (BIT(0))
-#define UART_AUTOBAUD_EN_M  (BIT(0))
-#define UART_AUTOBAUD_EN_V  0x1
-#define UART_AUTOBAUD_EN_S  0
-
-#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
-/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */
-/*description: This register represent the  level value of the internal uart rxd signal.*/
-#define UART_TXD  (BIT(31))
-#define UART_TXD_M  (BIT(31))
-#define UART_TXD_V  0x1
-#define UART_TXD_S  31
-/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This register represent the level value of the internal uart cts signal.*/
-#define UART_RTSN  (BIT(30))
-#define UART_RTSN_M  (BIT(30))
-#define UART_RTSN_V  0x1
-#define UART_RTSN_S  30
-/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: The register represent the level value of the internal uart dsr signal.*/
-#define UART_DTRN  (BIT(29))
-#define UART_DTRN_M  (BIT(29))
-#define UART_DTRN_V  0x1
-#define UART_DTRN_S  29
-/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */
-/*description: This register stores the value of transmitter's finite state
- machine. 0:TX_IDLE  1:TX_STRT  2:TX_DAT0  3:TX_DAT1  4:TX_DAT2   5:TX_DAT3 6:TX_DAT4  7:TX_DAT5  8:TX_DAT6 9:TX_DAT7  10:TX_PRTY   11:TX_STP1  12:TX_STP2  13:TX_DL0   14:TX_DL1*/
-#define UART_ST_UTX_OUT  0x0000000F
-#define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
-#define UART_ST_UTX_OUT_V  0xF
-#define UART_ST_UTX_OUT_S  24
-/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
-/*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in
- transmitter's fifo.tx_mem_cnt stores the 3 most significant bits  txfifo_cnt stores the 8 least significant bits.*/
-#define UART_TXFIFO_CNT  0x000000FF
-#define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
-#define UART_TXFIFO_CNT_V  0xFF
-#define UART_TXFIFO_CNT_S  16
-/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This register stores the level value of the internal uart rxd signal.*/
-#define UART_RXD  (BIT(15))
-#define UART_RXD_M  (BIT(15))
-#define UART_RXD_V  0x1
-#define UART_RXD_S  15
-/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This register stores the level value of the internal uart cts signal.*/
-#define UART_CTSN  (BIT(14))
-#define UART_CTSN_M  (BIT(14))
-#define UART_CTSN_V  0x1
-#define UART_CTSN_S  14
-/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This register stores the level value of the internal uart dsr signal.*/
-#define UART_DSRN  (BIT(13))
-#define UART_DSRN_M  (BIT(13))
-#define UART_DSRN_V  0x1
-#define UART_DSRN_S  13
-/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */
-/*description: This register stores the value of receiver's finite state machine.
- 0:RX_IDLE  1:RX_STRT  2:RX_DAT0  3:RX_DAT1  4:RX_DAT2  5:RX_DAT3  6:RX_DAT4  7:RX_DAT5  8:RX_DAT6  9:RX_DAT7   10:RX_PRTY   11:RX_STP1  12:RX_STP2 13:RX_DL1*/
-#define UART_ST_URX_OUT  0x0000000F
-#define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
-#define UART_ST_URX_OUT_V  0xF
-#define UART_ST_URX_OUT_S  8
-/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in
- receiver's fifo. rx_mem_cnt register stores the 3 most significant bits  rxfifo_cnt stores the 8 least significant bits.*/
-#define UART_RXFIFO_CNT  0x000000FF
-#define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
-#define UART_RXFIFO_CNT_V  0xFF
-#define UART_RXFIFO_CNT_S  0
-
-#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
-/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */
-/*description: This register is used to select the clock.1.apb clock 0:ref_tick*/
-#define UART_TICK_REF_ALWAYS_ON  (BIT(27))
-#define UART_TICK_REF_ALWAYS_ON_M  (BIT(27))
-#define UART_TICK_REF_ALWAYS_ON_V  0x1
-#define UART_TICK_REF_ALWAYS_ON_S  27
-/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1.receiver stops storing data int fifo when data is wrong.
- 0.receiver stores the data even if the  received data is wrong.*/
-#define UART_ERR_WR_MASK  (BIT(26))
-#define UART_ERR_WR_MASK_M  (BIT(26))
-#define UART_ERR_WR_MASK_V  0x1
-#define UART_ERR_WR_MASK_S  26
-/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: 1.force clock on for registers.support clock only when write registers*/
-#define UART_CLK_EN  (BIT(25))
-#define UART_CLK_EN_M  (BIT(25))
-#define UART_CLK_EN_V  0x1
-#define UART_CLK_EN_S  25
-/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart dtr signal.*/
-#define UART_DTR_INV  (BIT(24))
-#define UART_DTR_INV_M  (BIT(24))
-#define UART_DTR_INV_V  0x1
-#define UART_DTR_INV_S  24
-/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart rts signal.*/
-#define UART_RTS_INV  (BIT(23))
-#define UART_RTS_INV_M  (BIT(23))
-#define UART_RTS_INV_V  0x1
-#define UART_RTS_INV_S  23
-/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart txd signal.*/
-#define UART_TXD_INV  (BIT(22))
-#define UART_TXD_INV_M  (BIT(22))
-#define UART_TXD_INV_V  0x1
-#define UART_TXD_INV_S  22
-/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart dsr signal.*/
-#define UART_DSR_INV  (BIT(21))
-#define UART_DSR_INV_M  (BIT(21))
-#define UART_DSR_INV_V  0x1
-#define UART_DSR_INV_S  21
-/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart cts signal.*/
-#define UART_CTS_INV  (BIT(20))
-#define UART_CTS_INV_M  (BIT(20))
-#define UART_CTS_INV_V  0x1
-#define UART_CTS_INV_S  20
-/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart rxd signal.*/
-#define UART_RXD_INV  (BIT(19))
-#define UART_RXD_INV_M  (BIT(19))
-#define UART_RXD_INV_V  0x1
-#define UART_RXD_INV_S  19
-/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: Set this bit to reset uart transmitter's fifo.*/
-#define UART_TXFIFO_RST  (BIT(18))
-#define UART_TXFIFO_RST_M  (BIT(18))
-#define UART_TXFIFO_RST_V  0x1
-#define UART_TXFIFO_RST_S  18
-/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: Set this bit to reset uart receiver's fifo.*/
-#define UART_RXFIFO_RST  (BIT(17))
-#define UART_RXFIFO_RST_M  (BIT(17))
-#define UART_RXFIFO_RST_V  0x1
-#define UART_RXFIFO_RST_S  17
-/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: Set this bit to enable irda protocol.*/
-#define UART_IRDA_EN  (BIT(16))
-#define UART_IRDA_EN_M  (BIT(16))
-#define UART_IRDA_EN_V  0x1
-#define UART_IRDA_EN_S  16
-/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to enable transmitter's flow control function.*/
-#define UART_TX_FLOW_EN  (BIT(15))
-#define UART_TX_FLOW_EN_M  (BIT(15))
-#define UART_TX_FLOW_EN_V  0x1
-#define UART_TX_FLOW_EN_S  15
-/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable uart loopback test mode.*/
-#define UART_LOOPBACK  (BIT(14))
-#define UART_LOOPBACK_M  (BIT(14))
-#define UART_LOOPBACK_V  0x1
-#define UART_LOOPBACK_S  14
-/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to inverse the level value of irda receiver's level.*/
-#define UART_IRDA_RX_INV  (BIT(13))
-#define UART_IRDA_RX_INV_M  (BIT(13))
-#define UART_IRDA_RX_INV_V  0x1
-#define UART_IRDA_RX_INV_S  13
-/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to inverse the level value of  irda transmitter's level.*/
-#define UART_IRDA_TX_INV  (BIT(12))
-#define UART_IRDA_TX_INV_M  (BIT(12))
-#define UART_IRDA_TX_INV_V  0x1
-#define UART_IRDA_TX_INV_S  12
-/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: 1.the irda transmitter's 11th bit is the same to the 10th bit.
- 0.set irda transmitter's 11th bit to 0.*/
-#define UART_IRDA_WCTL  (BIT(11))
-#define UART_IRDA_WCTL_M  (BIT(11))
-#define UART_IRDA_WCTL_V  0x1
-#define UART_IRDA_WCTL_S  11
-/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the start enable bit for irda transmitter.*/
-#define UART_IRDA_TX_EN  (BIT(10))
-#define UART_IRDA_TX_EN_M  (BIT(10))
-#define UART_IRDA_TX_EN_V  0x1
-#define UART_IRDA_TX_EN_S  10
-/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to enable irda loopback mode.*/
-#define UART_IRDA_DPLX  (BIT(9))
-#define UART_IRDA_DPLX_M  (BIT(9))
-#define UART_IRDA_DPLX_V  0x1
-#define UART_IRDA_DPLX_S  9
-/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to enbale transmitter to  send 0 when the process
- of sending data is done.*/
-#define UART_TXD_BRK  (BIT(8))
-#define UART_TXD_BRK_M  (BIT(8))
-#define UART_TXD_BRK_V  0x1
-#define UART_TXD_BRK_S  8
-/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This register is used to configure the software dtr signal which
- is used in software flow control..*/
-#define UART_SW_DTR  (BIT(7))
-#define UART_SW_DTR_M  (BIT(7))
-#define UART_SW_DTR_V  0x1
-#define UART_SW_DTR_S  7
-/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This register is used to configure the software rts signal which
- is used in software flow control.*/
-#define UART_SW_RTS  (BIT(6))
-#define UART_SW_RTS_M  (BIT(6))
-#define UART_SW_RTS_V  0x1
-#define UART_SW_RTS_S  6
-/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
-/*description: This register is used to set the length of  stop bit. 1:1bit  2:1.5bits  3:2bits*/
-#define UART_STOP_BIT_NUM  0x00000003
-#define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
-#define UART_STOP_BIT_NUM_V  0x3
-#define UART_STOP_BIT_NUM_S  4
-/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
-/*description: This registe is used to set the length of data:  0:5bits 1:6bits 2:7bits 3:8bits*/
-#define UART_BIT_NUM  0x00000003
-#define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
-#define UART_BIT_NUM_V  0x3
-#define UART_BIT_NUM_S  2
-/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to enable uart parity check.*/
-#define UART_PARITY_EN  (BIT(1))
-#define UART_PARITY_EN_M  (BIT(1))
-#define UART_PARITY_EN_V  0x1
-#define UART_PARITY_EN_S  1
-/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This register is used to configure the parity check mode.  0:even 1:odd*/
-#define UART_PARITY  (BIT(0))
-#define UART_PARITY_M  (BIT(0))
-#define UART_PARITY_V  0x1
-#define UART_PARITY_S  0
-
-#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
-/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: This is the enble bit for uart receiver's timeout function.*/
-#define UART_RX_TOUT_EN  (BIT(31))
-#define UART_RX_TOUT_EN_M  (BIT(31))
-#define UART_RX_TOUT_EN_V  0x1
-#define UART_RX_TOUT_EN_S  31
-/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */
-/*description: This register is used to configure the timeout value for uart
- receiver receiving a byte.*/
-#define UART_RX_TOUT_THRHD  0x0000007F
-#define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
-#define UART_RX_TOUT_THRHD_V  0x7F
-#define UART_RX_TOUT_THRHD_S  24
-/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: This is the flow enable bit for uart receiver. 1:choose software
- flow control with configuring sw_rts signal*/
-#define UART_RX_FLOW_EN  (BIT(23))
-#define UART_RX_FLOW_EN_M  (BIT(23))
-#define UART_RX_FLOW_EN_V  0x1
-#define UART_RX_FLOW_EN_S  23
-/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */
-/*description: when receiver receives more data than its threshold value.
- receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/
-#define UART_RX_FLOW_THRHD  0x0000007F
-#define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
-#define UART_RX_FLOW_THRHD_V  0x7F
-#define UART_RX_FLOW_THRHD_S  16
-/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */
-/*description: when the data amount in transmitter fifo is less than its threshold
- value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/
-#define UART_TXFIFO_EMPTY_THRHD  0x0000007F
-#define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
-#define UART_TXFIFO_EMPTY_THRHD_V  0x7F
-#define UART_TXFIFO_EMPTY_THRHD_S  8
-/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */
-/*description: When receiver receives more data than its threshold value.receiver
- will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/
-#define UART_RXFIFO_FULL_THRHD  0x0000007F
-#define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
-#define UART_RXFIFO_FULL_THRHD_V  0x7F
-#define UART_RXFIFO_FULL_THRHD_S  0
-
-#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
-/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
-/*description: This register stores the value of the minimum duration time for
- the low level pulse. it is used in baudrate-detect process.*/
-#define UART_LOWPULSE_MIN_CNT  0x000FFFFF
-#define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
-#define UART_LOWPULSE_MIN_CNT_V  0xFFFFF
-#define UART_LOWPULSE_MIN_CNT_S  0
-
-#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
-/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
-/*description: This register stores  the value of the maxinum duration time
- for the high level pulse. it is used in baudrate-detect process.*/
-#define UART_HIGHPULSE_MIN_CNT  0x000FFFFF
-#define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
-#define UART_HIGHPULSE_MIN_CNT_V  0xFFFFF
-#define UART_HIGHPULSE_MIN_CNT_S  0
-
-#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
-/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register stores the count of rxd edge change. it is used
- in baudrate-detect process.*/
-#define UART_RXD_EDGE_CNT  0x000003FF
-#define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
-#define UART_RXD_EDGE_CNT_V  0x3FF
-#define UART_RXD_EDGE_CNT_S  0
-
-#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
-/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/
-#define UART_SEND_XOFF  (BIT(5))
-#define UART_SEND_XOFF_M  (BIT(5))
-#define UART_SEND_XOFF_V  0x1
-#define UART_SEND_XOFF_S  5
-/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to send xon char. it is cleared by hardware automatically.*/
-#define UART_SEND_XON  (BIT(4))
-#define UART_SEND_XON_M  (BIT(4))
-#define UART_SEND_XON_V  0x1
-#define UART_SEND_XON_S  4
-/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/
-#define UART_FORCE_XOFF  (BIT(3))
-#define UART_FORCE_XOFF_M  (BIT(3))
-#define UART_FORCE_XOFF_V  0x1
-#define UART_FORCE_XOFF_S  3
-/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear ctsn to stop the  transmitter from sending data.*/
-#define UART_FORCE_XON  (BIT(2))
-#define UART_FORCE_XON_M  (BIT(2))
-#define UART_FORCE_XON_V  0x1
-#define UART_FORCE_XON_S  2
-/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to remove flow control char from the received data.*/
-#define UART_XONOFF_DEL  (BIT(1))
-#define UART_XONOFF_DEL_M  (BIT(1))
-#define UART_XONOFF_DEL_V  0x1
-#define UART_XONOFF_DEL_S  1
-/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable software  flow control. it is used with
- register sw_xon or sw_xoff .*/
-#define UART_SW_FLOW_CON_EN  (BIT(0))
-#define UART_SW_FLOW_CON_EN_M  (BIT(0))
-#define UART_SW_FLOW_CON_EN_V  0x1
-#define UART_SW_FLOW_CON_EN_S  0
-
-#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
-/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
-/*description: When the input rxd edge changes more than this register value.
- the uart is active from light sleeping mode.*/
-#define UART_ACTIVE_THRESHOLD  0x000003FF
-#define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
-#define UART_ACTIVE_THRESHOLD_V  0x3FF
-#define UART_ACTIVE_THRESHOLD_S  0
-
-#define UART_SWFC_CONF_REG(i)          (REG_UART_BASE(i) + 0x3C)
-/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */
-/*description: This register stores the xoff flow control char.*/
-#define UART_XOFF_CHAR  0x000000FF
-#define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
-#define UART_XOFF_CHAR_V  0xFF
-#define UART_XOFF_CHAR_S  24
-/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */
-/*description: This register stores the xon flow control char.*/
-#define UART_XON_CHAR  0x000000FF
-#define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
-#define UART_XON_CHAR_V  0xFF
-#define UART_XON_CHAR_S  16
-/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */
-/*description: When the data amount in receiver's fifo is less than this register
- value. it will send a xon char with uart_sw_flow_con_en set to 1.*/
-#define UART_XOFF_THRESHOLD  0x000000FF
-#define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
-#define UART_XOFF_THRESHOLD_V  0xFF
-#define UART_XOFF_THRESHOLD_S  8
-/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: when the data amount in receiver's fifo is more than this register
- value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/
-#define UART_XON_THRESHOLD  0x000000FF
-#define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
-#define UART_XON_THRESHOLD_V  0xFF
-#define UART_XON_THRESHOLD_S  0
-
-#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x40)
-/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */
-/*description: This register is used to configure the num of 0 send after the
- process of sending data is done. it is active when txd_brk is set to 1.*/
-#define UART_TX_BRK_NUM  0x000000FF
-#define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
-#define UART_TX_BRK_NUM_V  0xFF
-#define UART_TX_BRK_NUM_S  20
-/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
-/*description: This register is used to configure the duration time between transfers.*/
-#define UART_TX_IDLE_NUM  0x000003FF
-#define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
-#define UART_TX_IDLE_NUM_V  0x3FF
-#define UART_TX_IDLE_NUM_S  10
-/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
-/*description: when receiver takes more time than this register value to receive
- a byte data. it will produce frame end signal for uhci to stop receiving data.*/
-#define UART_RX_IDLE_THRHD  0x000003FF
-#define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
-#define UART_RX_IDLE_THRHD_V  0x3FF
-#define UART_RX_IDLE_THRHD_S  0
-
-#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
-/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
-/*description: This register is used to delay the transmitter's internal data signal.*/
-#define UART_RS485_TX_DLY_NUM  0x0000000F
-#define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
-#define UART_RS485_TX_DLY_NUM_V  0xF
-#define UART_RS485_TX_DLY_NUM_S  6
-/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This register is used to delay the receiver's internal data signal.*/
-#define UART_RS485_RX_DLY_NUM  (BIT(5))
-#define UART_RS485_RX_DLY_NUM_M  (BIT(5))
-#define UART_RS485_RX_DLY_NUM_V  0x1
-#define UART_RS485_RX_DLY_NUM_S  5
-/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: enable rs485's transmitter to send data when rs485's receiver
- is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
-#define UART_RS485RXBY_TX_EN  (BIT(4))
-#define UART_RS485RXBY_TX_EN_M  (BIT(4))
-#define UART_RS485RXBY_TX_EN_V  0x1
-#define UART_RS485RXBY_TX_EN_S  4
-/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable loopback transmitter's output data signal
- to receiver's input data signal.*/
-#define UART_RS485TX_RX_EN  (BIT(3))
-#define UART_RS485TX_RX_EN_M  (BIT(3))
-#define UART_RS485TX_RX_EN_V  0x1
-#define UART_RS485TX_RX_EN_S  3
-/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to delay the stop bit by 1 bit.*/
-#define UART_DL1_EN  (BIT(2))
-#define UART_DL1_EN_M  (BIT(2))
-#define UART_DL1_EN_V  0x1
-#define UART_DL1_EN_S  2
-/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to delay the stop bit by 1 bit.*/
-#define UART_DL0_EN  (BIT(1))
-#define UART_DL0_EN_M  (BIT(1))
-#define UART_DL0_EN_V  0x1
-#define UART_DL0_EN_S  1
-/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to choose rs485 mode.*/
-#define UART_RS485_EN  (BIT(0))
-#define UART_RS485_EN_M  (BIT(0))
-#define UART_RS485_EN_V  0x1
-#define UART_RS485_EN_S  0
-
-#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x48)
-/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
-/*description: This register is used to configure the idle duration time before
- the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
-#define UART_PRE_IDLE_NUM  0x00FFFFFF
-#define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
-#define UART_PRE_IDLE_NUM_V  0xFFFFFF
-#define UART_PRE_IDLE_NUM_S  0
-
-#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x4c)
-/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
-/*description: This register is used to configure the duration time between
- the last at_cmd and the next data. when the duration is less than this register value  it will not take the previous data as at_cmd char.*/
-#define UART_POST_IDLE_NUM  0x00FFFFFF
-#define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
-#define UART_POST_IDLE_NUM_V  0xFFFFFF
-#define UART_POST_IDLE_NUM_S  0
-
-#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x50)
-/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */
-/*description: This register is used to configure the duration time between
- the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/
-#define UART_RX_GAP_TOUT  0x00FFFFFF
-#define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
-#define UART_RX_GAP_TOUT_V  0xFFFFFF
-#define UART_RX_GAP_TOUT_S  0
-
-#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x54)
-/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
-/*description: This register is used to configure the num of continous at_cmd
- chars received by receiver.*/
-#define UART_CHAR_NUM  0x000000FF
-#define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
-#define UART_CHAR_NUM_V  0xFF
-#define UART_CHAR_NUM_S  8
-/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
-/*description: This register is used to configure the content of at_cmd char.*/
-#define UART_AT_CMD_CHAR  0x000000FF
-#define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
-#define UART_AT_CMD_CHAR_V  0xFF
-#define UART_AT_CMD_CHAR_S  0
-
-#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x58)
-/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
-/*description: refer to txfifo_empty_thrhd 's describtion.*/
-#define UART_TX_MEM_EMPTY_THRHD  0x00000007
-#define UART_TX_MEM_EMPTY_THRHD_M  ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S))
-#define UART_TX_MEM_EMPTY_THRHD_V  0x7
-#define UART_TX_MEM_EMPTY_THRHD_S  28
-/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
-/*description: refer to the rxfifo_full_thrhd's describtion.*/
-#define UART_RX_MEM_FULL_THRHD  0x00000007
-#define UART_RX_MEM_FULL_THRHD_M  ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S))
-#define UART_RX_MEM_FULL_THRHD_V  0x7
-#define UART_RX_MEM_FULL_THRHD_S  25
-/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */
-/*description: refer to the uart_xoff_threshold's describtion.*/
-#define UART_XOFF_THRESHOLD_H2  0x00000003
-#define UART_XOFF_THRESHOLD_H2_M  ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S))
-#define UART_XOFF_THRESHOLD_H2_V  0x3
-#define UART_XOFF_THRESHOLD_H2_S  23
-/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */
-/*description: refer to the uart_xon_threshold's describtion.*/
-#define UART_XON_THRESHOLD_H2  0x00000003
-#define UART_XON_THRESHOLD_H2_M  ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S))
-#define UART_XON_THRESHOLD_H2_V  0x3
-#define UART_XON_THRESHOLD_H2_S  21
-/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: refer to the rx_tout_thrhd's describtion.*/
-#define UART_RX_TOUT_THRHD_H3  0x00000007
-#define UART_RX_TOUT_THRHD_H3_M  ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S))
-#define UART_RX_TOUT_THRHD_H3_V  0x7
-#define UART_RX_TOUT_THRHD_H3_S  18
-/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: refer to the rx_flow_thrhd's describtion.*/
-#define UART_RX_FLOW_THRHD_H3  0x00000007
-#define UART_RX_FLOW_THRHD_H3_M  ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S))
-#define UART_RX_FLOW_THRHD_H3_V  0x7
-#define UART_RX_FLOW_THRHD_H3_S  15
-/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */
-/*description: This register is used to configure the amount of mem allocated
- to transmitter's fifo.the default byte num is 128.*/
-#define UART_TX_SIZE  0x0000000F
-#define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
-#define UART_TX_SIZE_V  0xF
-#define UART_TX_SIZE_S  7
-/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */
-/*description: This register is used to configure the amount of mem allocated
- to receiver's fifo. the default byte num is 128.*/
-#define UART_RX_SIZE  0x0000000F
-#define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
-#define UART_RX_SIZE_V  0xF
-#define UART_RX_SIZE_S  3
-/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to power down mem.when reg_mem_pd registers in
- the 3 uarts are all set to 1  mem will enter low power mode.*/
-#define UART_MEM_PD  (BIT(0))
-#define UART_MEM_PD_M  (BIT(0))
-#define UART_MEM_PD_V  0x1
-#define UART_MEM_PD_S  0
-
-#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x5c)
-/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: */
-#define UART_MEM_TX_STATUS  0x00FFFFFF
-#define UART_MEM_TX_STATUS_M  ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S))
-#define UART_MEM_TX_STATUS_V  0xFFFFFF
-#define UART_MEM_TX_STATUS_S  0
-
-#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x60)
-/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: This register stores the current uart rx mem read address
-  and rx mem write address */
-#define UART_MEM_RX_STATUS  0x00FFFFFF
-#define UART_MEM_RX_STATUS_M  ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S))
-#define UART_MEM_RX_STATUS_V  0xFFFFFF
-#define UART_MEM_RX_STATUS_S  0
-/* UART_MEM_RX_RD_ADDR : RO ;bitpos:[12:2] ;default: 11'h0 ; */
-/*description: This register stores the rx mem read address */
-#define UART_MEM_RX_RD_ADDR  0x000007FF
-#define UART_MEM_RX_RD_ADDR_M ((UART_MEM_RX_RD_ADDR_V)<<(UART_MEM_RX_RD_ADDR_S))
-#define UART_MEM_RX_RD_ADDR_V (0x7FF)
-#define UART_MEM_RX_RD_ADDR_S (2)
-/* UART_MEM_RX_WR_ADDR : RO ;bitpos:[23:13] ;default: 11'h0 ; */
-/*description: This register stores the rx mem write address */
-#define UART_MEM_RX_WR_ADDR   0x000007FF
-#define UART_MEM_RX_WR_ADDR_M ((UART_MEM_RX_WR_ADDR_V)<<(UART_MEM_RX_WR_ADDR_S))
-#define UART_MEM_RX_WR_ADDR_V (0x7FF)
-#define UART_MEM_RX_WR_ADDR_S (13)
-
-#define UART_MEM_CNT_STATUS_REG(i)          (REG_UART_BASE(i) + 0x64)
-/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: refer to the txfifo_cnt's describtion.*/
-#define UART_TX_MEM_CNT  0x00000007
-#define UART_TX_MEM_CNT_M  ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S))
-#define UART_TX_MEM_CNT_V  0x7
-#define UART_TX_MEM_CNT_S  3
-/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: refer to the rxfifo_cnt's describtion.*/
-#define UART_RX_MEM_CNT  0x00000007
-#define UART_RX_MEM_CNT_M  ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S))
-#define UART_RX_MEM_CNT_V  0x7
-#define UART_RX_MEM_CNT_S  0
-
-#define UART_POSPULSE_REG(i)          (REG_UART_BASE(i) + 0x68)
-/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
-/*description: This register stores the count of rxd posedge edge. it is used
- in boudrate-detect process.*/
-#define UART_POSEDGE_MIN_CNT  0x000FFFFF
-#define UART_POSEDGE_MIN_CNT_M  ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
-#define UART_POSEDGE_MIN_CNT_V  0xFFFFF
-#define UART_POSEDGE_MIN_CNT_S  0
-
-#define UART_NEGPULSE_REG(i)          (REG_UART_BASE(i) + 0x6c)
-/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
-/*description: This register stores the count of rxd negedge edge. it is used
- in boudrate-detect process.*/
-#define UART_NEGEDGE_MIN_CNT  0x000FFFFF
-#define UART_NEGEDGE_MIN_CNT_M  ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
-#define UART_NEGEDGE_MIN_CNT_V  0xFFFFF
-#define UART_NEGEDGE_MIN_CNT_S  0
-
-#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x78)
-/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */
-/*description: */
-#define UART_DATE  0xFFFFFFFF
-#define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
-#define UART_DATE_V  0xFFFFFFFF
-#define UART_DATE_S  0
-
-#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x7C)
-/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */
-/*description: */
-#define UART_ID  0xFFFFFFFF
-#define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
-#define UART_ID_V  0xFFFFFFFF
-#define UART_ID_S  0
-
-
-
-
-#endif /*__UART_REG_H__ */
-
-
diff --git a/tools/sdk/include/soc/soc/uart_struct.h b/tools/sdk/include/soc/soc/uart_struct.h
deleted file mode 100644
index 4efd6cf9011..00000000000
--- a/tools/sdk/include/soc/soc/uart_struct.h
+++ /dev/null
@@ -1,383 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UART_STRUCT_H_
-#define _SOC_UART_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint8_t rw_byte;                 /*This register stores one byte data  read by rx fifo.*/
-            uint8_t reserved[3];
-        };
-        uint32_t val;
-    } fifo;
-    union {
-        struct {
-            uint32_t rxfifo_full:      1;           /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
-            uint32_t txfifo_empty:     1;           /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
-            uint32_t parity_err:       1;           /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/
-            uint32_t frm_err:          1;           /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/
-            uint32_t rxfifo_ovf:       1;           /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/
-            uint32_t dsr_chg:          1;           /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/
-            uint32_t cts_chg:          1;           /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/
-            uint32_t brk_det:          1;           /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/
-            uint32_t rxfifo_tout:      1;           /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
-            uint32_t sw_xon:           1;           /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/
-            uint32_t sw_xoff:          1;           /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/
-            uint32_t glitch_det:       1;           /*This interrupt raw bit turns to high level when receiver detects the start bit.*/
-            uint32_t tx_brk_done:      1;           /*This interrupt raw bit turns to high level when transmitter completes  sending  0 after all the data in transmitter's fifo are send.*/
-            uint32_t tx_brk_idle_done: 1;           /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the  last data has been send.*/
-            uint32_t tx_done:          1;           /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/
-            uint32_t rs485_parity_err: 1;           /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/
-            uint32_t rs485_frm_err:    1;           /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/
-            uint32_t rs485_clash:      1;           /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/
-            uint32_t at_cmd_char_det:  1;           /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/
-            uint32_t reserved19:      13;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rxfifo_full:      1;            /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
-            uint32_t txfifo_empty:     1;            /*This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.*/
-            uint32_t parity_err:       1;            /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
-            uint32_t frm_err:          1;            /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
-            uint32_t rxfifo_ovf:       1;            /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
-            uint32_t dsr_chg:          1;            /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
-            uint32_t cts_chg:          1;            /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
-            uint32_t brk_det:          1;            /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
-            uint32_t rxfifo_tout:      1;            /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
-            uint32_t sw_xon:           1;            /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
-            uint32_t sw_xoff:          1;            /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
-            uint32_t glitch_det:       1;            /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
-            uint32_t tx_brk_done:      1;            /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
-            uint32_t tx_brk_idle_done: 1;            /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
-            uint32_t tx_done:          1;            /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
-            uint32_t rs485_parity_err: 1;            /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
-            uint32_t rs485_frm_err:    1;            /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
-            uint32_t rs485_clash:      1;            /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
-            uint32_t at_cmd_char_det:  1;            /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
-            uint32_t reserved19:      13;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t rxfifo_full:      1;           /*This is the enable bit for rxfifo_full_int_st register.*/
-            uint32_t txfifo_empty:     1;           /*This is the enable bit for rxfifo_full_int_st register.*/
-            uint32_t parity_err:       1;           /*This is the enable bit for parity_err_int_st register.*/
-            uint32_t frm_err:          1;           /*This is the enable bit for frm_err_int_st register.*/
-            uint32_t rxfifo_ovf:       1;           /*This is the enable bit for rxfifo_ovf_int_st register.*/
-            uint32_t dsr_chg:          1;           /*This is the enable bit for dsr_chg_int_st register.*/
-            uint32_t cts_chg:          1;           /*This is the enable bit for cts_chg_int_st register.*/
-            uint32_t brk_det:          1;           /*This is the enable bit for brk_det_int_st register.*/
-            uint32_t rxfifo_tout:      1;           /*This is the enable bit for rxfifo_tout_int_st register.*/
-            uint32_t sw_xon:           1;           /*This is the enable bit for sw_xon_int_st register.*/
-            uint32_t sw_xoff:          1;           /*This is the enable bit for sw_xoff_int_st register.*/
-            uint32_t glitch_det:       1;           /*This is the enable bit for glitch_det_int_st register.*/
-            uint32_t tx_brk_done:      1;           /*This is the enable bit for tx_brk_done_int_st register.*/
-            uint32_t tx_brk_idle_done: 1;           /*This is the enable bit for tx_brk_idle_done_int_st register.*/
-            uint32_t tx_done:          1;           /*This is the enable bit for tx_done_int_st register.*/
-            uint32_t rs485_parity_err: 1;           /*This is the enable bit for rs485_parity_err_int_st register.*/
-            uint32_t rs485_frm_err:    1;           /*This is the enable bit for rs485_parity_err_int_st register.*/
-            uint32_t rs485_clash:      1;           /*This is the enable bit for rs485_clash_int_st register.*/
-            uint32_t at_cmd_char_det:  1;           /*This is the enable bit for at_cmd_char_det_int_st register.*/
-            uint32_t reserved19:      13;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t rxfifo_full:      1;           /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
-            uint32_t txfifo_empty:     1;           /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
-            uint32_t parity_err:       1;           /*Set this bit to clear parity_err_int_raw interrupt.*/
-            uint32_t frm_err:          1;           /*Set this bit to clear frm_err_int_raw interrupt.*/
-            uint32_t rxfifo_ovf:       1;           /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
-            uint32_t dsr_chg:          1;           /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
-            uint32_t cts_chg:          1;           /*Set this bit to clear the cts_chg_int_raw interrupt.*/
-            uint32_t brk_det:          1;           /*Set this bit to clear the brk_det_int_raw interrupt.*/
-            uint32_t rxfifo_tout:      1;           /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
-            uint32_t sw_xon:           1;           /*Set this bit to clear the sw_xon_int_raw interrupt.*/
-            uint32_t sw_xoff:          1;           /*Set this bit to clear the sw_xon_int_raw interrupt.*/
-            uint32_t glitch_det:       1;           /*Set this bit to clear the glitch_det_int_raw interrupt.*/
-            uint32_t tx_brk_done:      1;           /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
-            uint32_t tx_brk_idle_done: 1;           /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
-            uint32_t tx_done:          1;           /*Set this bit to clear the tx_done_int_raw interrupt.*/
-            uint32_t rs485_parity_err: 1;           /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
-            uint32_t rs485_frm_err:    1;           /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
-            uint32_t rs485_clash:      1;           /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
-            uint32_t at_cmd_char_det:  1;           /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
-            uint32_t reserved19:      13;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t div_int:    20;                /*The register value is  the  integer part of the frequency divider's factor.*/
-            uint32_t div_frag:    4;                /*The register  value is the decimal part of the frequency divider's factor.*/
-            uint32_t reserved24:  8;
-        };
-        uint32_t val;
-    } clk_div;
-    union {
-        struct {
-            uint32_t en: 1;                         /*This is the enable bit for detecting baudrate.*/
-            uint32_t reserved1:   7;
-            uint32_t glitch_filt: 8;                /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/
-            uint32_t reserved16: 16;
-        };
-        uint32_t val;
-    } auto_baud;
-    union {
-        struct {
-            uint32_t rxfifo_cnt: 8;                 /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits  rxfifo_cnt stores the 8 least significant bits.*/
-            uint32_t st_urx_out: 4;                 /*This register stores the value of receiver's finite state machine. 0:RX_IDLE  1:RX_STRT  2:RX_DAT0  3:RX_DAT1  4:RX_DAT2  5:RX_DAT3  6:RX_DAT4  7:RX_DAT5  8:RX_DAT6  9:RX_DAT7   10:RX_PRTY   11:RX_STP1  12:RX_STP2 13:RX_DL1*/
-            uint32_t reserved12: 1;
-            uint32_t dsrn:       1;                 /*This register stores the level value of the internal uart dsr signal.*/
-            uint32_t ctsn:       1;                 /*This register stores the level value of the internal uart cts signal.*/
-            uint32_t rxd:        1;                 /*This register stores the level value of the internal uart rxd signal.*/
-            uint32_t txfifo_cnt: 8;                 /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits  txfifo_cnt stores the 8 least significant bits.*/
-            uint32_t st_utx_out: 4;                 /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE  1:TX_STRT  2:TX_DAT0  3:TX_DAT1  4:TX_DAT2   5:TX_DAT3 6:TX_DAT4  7:TX_DAT5  8:TX_DAT6 9:TX_DAT7  10:TX_PRTY   11:TX_STP1  12:TX_STP2  13:TX_DL0   14:TX_DL1*/
-            uint32_t reserved28: 1;
-            uint32_t dtrn:       1;                 /*The register represent the level value of the internal uart dsr signal.*/
-            uint32_t rtsn:       1;                 /*This register represent the level value of the internal uart cts signal.*/
-            uint32_t txd:        1;                 /*This register represent the  level value of the internal uart rxd signal.*/
-        };
-        uint32_t val;
-    } status;
-    union {
-        struct {
-            uint32_t parity:             1;         /*This register is used to configure the parity check mode.  0:even 1:odd*/
-            uint32_t parity_en:          1;         /*Set this bit to enable uart parity check.*/
-            uint32_t bit_num:            2;         /*This register is used to set the length of data:  0:5bits 1:6bits 2:7bits 3:8bits*/
-            uint32_t stop_bit_num:       2;         /*This register is used to set the length of  stop bit. 1:1bit  2:1.5bits  3:2bits*/
-            uint32_t sw_rts:             1;         /*This register is used to configure the software rts signal which is used in software flow control.*/
-            uint32_t sw_dtr:             1;         /*This register is used to configure the software dtr signal which is used in software flow control..*/
-            uint32_t txd_brk:            1;         /*Set this bit to enable transmitter to  send 0 when the process of sending data is done.*/
-            uint32_t irda_dplx:          1;         /*Set this bit to enable irda loop-back mode.*/
-            uint32_t irda_tx_en:         1;         /*This is the start enable bit for irda transmitter.*/
-            uint32_t irda_wctl:          1;         /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/
-            uint32_t irda_tx_inv:        1;         /*Set this bit to inverse the level value of  irda transmitter's level.*/
-            uint32_t irda_rx_inv:        1;         /*Set this bit to inverse the level value of irda receiver's level.*/
-            uint32_t loopback:           1;         /*Set this bit to enable uart loop-back test mode.*/
-            uint32_t tx_flow_en:         1;         /*Set this bit to enable transmitter's flow control function.*/
-            uint32_t irda_en:            1;         /*Set this bit to enable irda protocol.*/
-            uint32_t rxfifo_rst:         1;         /*Set this bit to reset uart receiver's fifo.*/
-            uint32_t txfifo_rst:         1;         /*Set this bit to reset uart transmitter's fifo.*/
-            uint32_t rxd_inv:            1;         /*Set this bit to inverse the level value of uart rxd signal.*/
-            uint32_t cts_inv:            1;         /*Set this bit to inverse the level value of uart cts signal.*/
-            uint32_t dsr_inv:            1;         /*Set this bit to inverse the level value of uart dsr signal.*/
-            uint32_t txd_inv:            1;         /*Set this bit to inverse the level value of uart txd signal.*/
-            uint32_t rts_inv:            1;         /*Set this bit to inverse the level value of uart rts signal.*/
-            uint32_t dtr_inv:            1;         /*Set this bit to inverse the level value of uart dtr signal.*/
-            uint32_t clk_en:             1;         /*1：force clock on for registers：support clock only when write registers*/
-            uint32_t err_wr_mask:        1;         /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the  received data is wrong.*/
-            uint32_t tick_ref_always_on: 1;         /*This register is used to select the clock.1：apb clock：ref_tick*/
-            uint32_t reserved28:         4;
-        };
-        uint32_t val;
-    } conf0;
-    union {
-        struct {
-            uint32_t rxfifo_full_thrhd:  7;         /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/
-            uint32_t reserved7:          1;
-            uint32_t txfifo_empty_thrhd: 7;         /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/
-            uint32_t reserved15:         1;
-            uint32_t rx_flow_thrhd:      7;         /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/
-            uint32_t rx_flow_en:         1;         /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/
-            uint32_t rx_tout_thrhd:      7;         /*This register is used to configure the timeout value for uart receiver receiving a byte.*/
-            uint32_t rx_tout_en:         1;         /*This is the enable bit for uart receiver's timeout function.*/
-        };
-        uint32_t val;
-    } conf1;
-    union {
-        struct {
-            uint32_t min_cnt:     20;               /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/
-            uint32_t reserved20:  12;
-        };
-        uint32_t val;
-    } lowpulse;
-    union {
-        struct {
-            uint32_t min_cnt:     20;               /*This register stores  the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/
-            uint32_t reserved20:  12;
-        };
-        uint32_t val;
-    } highpulse;
-    union {
-        struct {
-            uint32_t edge_cnt:    10;               /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
-            uint32_t reserved10:  22;
-        };
-        uint32_t val;
-    } rxd_cnt;
-    union {
-        struct {
-            uint32_t sw_flow_con_en: 1;             /*Set this bit to enable software  flow control. it is used with register sw_xon or sw_xoff .*/
-            uint32_t xonoff_del:     1;             /*Set this bit to remove flow control char from the received data.*/
-            uint32_t force_xon:      1;             /*Set this bit to clear ctsn to stop the  transmitter from sending data.*/
-            uint32_t force_xoff:     1;             /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/
-            uint32_t send_xon:       1;             /*Set this bit to send xon char， it is cleared by hardware automatically.*/
-            uint32_t send_xoff:      1;             /*Set this bit to send xoff char， it is cleared by hardware automatically.*/
-            uint32_t reserved6:     26;
-        };
-        uint32_t val;
-    } flow_conf;
-    union {
-        struct {
-            uint32_t active_threshold:10;           /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/
-            uint32_t reserved10:      22;
-        };
-        uint32_t val;
-    } sleep_conf;
-    union {
-        struct {
-            uint32_t xon_threshold:  8;             /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/
-            uint32_t xoff_threshold: 8;             /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/
-            uint32_t xon_char:       8;             /*This register stores the xon flow control char.*/
-            uint32_t xoff_char:      8;             /*This register stores the xoff flow control char.*/
-        };
-        uint32_t val;
-    } swfc_conf;
-    union {
-        struct {
-            uint32_t rx_idle_thrhd:10;              /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/
-            uint32_t tx_idle_num:  10;              /*This register is used to configure the duration time between transfers.*/
-            uint32_t tx_brk_num:    8;              /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/
-            uint32_t reserved28:    4;
-        };
-        uint32_t val;
-    } idle_conf;
-    union {
-        struct {
-            uint32_t en:               1;           /*Set this bit to choose rs485 mode.*/
-            uint32_t dl0_en:           1;           /*Set this bit to delay the stop bit by 1 bit.*/
-            uint32_t dl1_en:           1;           /*Set this bit to delay the stop bit by 1 bit.*/
-            uint32_t tx_rx_en:         1;           /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/
-            uint32_t rx_busy_tx_en:    1;           /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
-            uint32_t rx_dly_num:       1;           /*This register is used to delay the receiver's internal data signal.*/
-            uint32_t tx_dly_num:       4;           /*This register is used to delay the transmitter's internal data signal.*/
-            uint32_t reserved10:      22;
-        };
-        uint32_t val;
-    } rs485_conf;
-    union {
-        struct {
-            uint32_t pre_idle_num:24;               /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
-            uint32_t reserved24:   8;
-        };
-        uint32_t val;
-    } at_cmd_precnt;
-    union {
-        struct {
-            uint32_t post_idle_num:24;              /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value  it will not take the previous data as at_cmd char.*/
-            uint32_t reserved24:    8;
-        };
-        uint32_t val;
-    } at_cmd_postcnt;
-    union {
-        struct {
-            uint32_t rx_gap_tout:24;                /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/
-            uint32_t reserved24:  8;
-        };
-        uint32_t val;
-    } at_cmd_gaptout;
-    union {
-        struct {
-            uint32_t data:        8;                /*This register is used to configure the content of at_cmd char.*/
-            uint32_t char_num:    8;                /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/
-            uint32_t reserved16: 16;
-        };
-        uint32_t val;
-    } at_cmd_char;
-    union {
-        struct {
-            uint32_t mem_pd:             1;         /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1  memory will enter low power mode.*/
-            uint32_t reserved1:          1;
-            uint32_t reserved2:          1;
-            uint32_t rx_size:            4;         /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/
-            uint32_t tx_size:            4;         /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/
-            uint32_t reserved11:         4;
-            uint32_t rx_flow_thrhd_h3:   3;         /*refer to the rx_flow_thrhd's description.*/
-            uint32_t rx_tout_thrhd_h3:   3;         /*refer to the rx_tout_thrhd's description.*/
-            uint32_t xon_threshold_h2:   2;         /*refer to the uart_xon_threshold's description.*/
-            uint32_t xoff_threshold_h2:  2;         /*refer to the uart_xoff_threshold's description.*/
-            uint32_t rx_mem_full_thrhd:  3;         /*refer to the rxfifo_full_thrhd's description.*/
-            uint32_t tx_mem_empty_thrhd: 3;         /*refer to txfifo_empty_thrhd 's description.*/
-            uint32_t reserved31:         1;
-        };
-        uint32_t val;
-    } mem_conf;
-    union {
-        struct {
-            uint32_t status:24;
-            uint32_t reserved24:    8;
-        };
-        uint32_t val;
-    } mem_tx_status;
-    union {
-        struct {
-            uint32_t status:      24;
-            uint32_t reserved24:   8;
-        };
-        struct {
-            uint32_t reserved0:     2;
-            uint32_t rd_addr:      11;              /*This register stores the rx mem read address.*/
-            uint32_t wr_addr:      11;              /*This register stores the rx mem write address.*/
-            uint32_t reserved:      8;
-        };
-        uint32_t val;
-    } mem_rx_status;
-    union {
-        struct {
-            uint32_t rx_cnt: 3;                      /*refer to the rxfifo_cnt's description.*/
-            uint32_t tx_cnt: 3;                      /*refer to the txfifo_cnt's description.*/
-            uint32_t reserved6: 26;
-        };
-        uint32_t val;
-    } mem_cnt_status;
-    union {
-        struct {
-            uint32_t min_cnt:     20;                 /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/
-            uint32_t reserved20:  12;
-        };
-        uint32_t val;
-    } pospulse;
-    union {
-        struct {
-            uint32_t min_cnt:     20;                 /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/
-            uint32_t reserved20:  12;
-        };
-        uint32_t val;
-    } negpulse;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t date;                                    /**/
-    uint32_t id;                                      /**/
-} uart_dev_t;
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-extern uart_dev_t UART2;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_UART_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/uhci_reg.h b/tools/sdk/include/soc/soc/uhci_reg.h
deleted file mode 100644
index 973c6b58929..00000000000
--- a/tools/sdk/include/soc/soc/uhci_reg.h
+++ /dev/null
@@ -1,1260 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UHCI_REG_H_
-#define _SOC_UHCI_REG_H_
-
-
-#include "soc.h"
-#define REG_UHCI_BASE(i)         (DR_REG_UHCI0_BASE - (i) * 0x8000)
-#define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
-/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Set this bit to enable to use brk char as the end of a data frame.*/
-#define UHCI_UART_RX_BRK_EOF_EN  (BIT(23))
-#define UHCI_UART_RX_BRK_EOF_EN_M  (BIT(23))
-#define UHCI_UART_RX_BRK_EOF_EN_V  0x1
-#define UHCI_UART_RX_BRK_EOF_EN_S  23
-/* UHCI_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Set this bit to enable clock-gating for read or write registers.*/
-#define UHCI_CLK_EN  (BIT(22))
-#define UHCI_CLK_EN_M  (BIT(22))
-#define UHCI_CLK_EN_V  0x1
-#define UHCI_CLK_EN_S  22
-/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Set this bit to enable crc calculation for data frame when bit6
- in the head packet is 1.*/
-#define UHCI_ENCODE_CRC_EN  (BIT(21))
-#define UHCI_ENCODE_CRC_EN_M  (BIT(21))
-#define UHCI_ENCODE_CRC_EN_V  0x1
-#define UHCI_ENCODE_CRC_EN_S  21
-/* UHCI_LEN_EOF_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: Set this bit to enable to use packet_len in packet head  when
- the received data is equal to packet_len  this means the end of a data frame.*/
-#define UHCI_LEN_EOF_EN  (BIT(20))
-#define UHCI_LEN_EOF_EN_M  (BIT(20))
-#define UHCI_LEN_EOF_EN_V  0x1
-#define UHCI_LEN_EOF_EN_S  20
-/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Set this bit to enable to use idle time  when the idle time after
- data frame is satisfied  this means the end of a data frame.*/
-#define UHCI_UART_IDLE_EOF_EN  (BIT(19))
-#define UHCI_UART_IDLE_EOF_EN_M  (BIT(19))
-#define UHCI_UART_IDLE_EOF_EN_V  0x1
-#define UHCI_UART_IDLE_EOF_EN_S  19
-/* UHCI_CRC_REC_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: Set this bit to enable receiver''s ability of crc calculation
-  when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/
-#define UHCI_CRC_REC_EN  (BIT(18))
-#define UHCI_CRC_REC_EN_M  (BIT(18))
-#define UHCI_CRC_REC_EN_V  0x1
-#define UHCI_CRC_REC_EN_S  18
-/* UHCI_HEAD_EN : R/W ;bitpos:[17] ;default: 1'b1 ; */
-/*description: Set this bit to enable to use head packet  before the data frame.*/
-#define UHCI_HEAD_EN  (BIT(17))
-#define UHCI_HEAD_EN_M  (BIT(17))
-#define UHCI_HEAD_EN_V  0x1
-#define UHCI_HEAD_EN_S  17
-/* UHCI_SEPER_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: Set this bit to use special char to separate the data frame.*/
-#define UHCI_SEPER_EN  (BIT(16))
-#define UHCI_SEPER_EN_M  (BIT(16))
-#define UHCI_SEPER_EN_V  0x1
-#define UHCI_SEPER_EN_S  16
-/* UHCI_MEM_TRANS_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_MEM_TRANS_EN  (BIT(15))
-#define UHCI_MEM_TRANS_EN_M  (BIT(15))
-#define UHCI_MEM_TRANS_EN_V  0x1
-#define UHCI_MEM_TRANS_EN_S  15
-/* UHCI_OUT_DATA_BURST_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable DMA burst MODE*/
-#define UHCI_OUT_DATA_BURST_EN  (BIT(14))
-#define UHCI_OUT_DATA_BURST_EN_M  (BIT(14))
-#define UHCI_OUT_DATA_BURST_EN_V  0x1
-#define UHCI_OUT_DATA_BURST_EN_S  14
-/* UHCI_INDSCR_BURST_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to enable DMA out links to use burst mode.*/
-#define UHCI_INDSCR_BURST_EN  (BIT(13))
-#define UHCI_INDSCR_BURST_EN_M  (BIT(13))
-#define UHCI_INDSCR_BURST_EN_V  0x1
-#define UHCI_INDSCR_BURST_EN_S  13
-/* UHCI_OUTDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to enable DMA in links to use burst mode.*/
-#define UHCI_OUTDSCR_BURST_EN  (BIT(12))
-#define UHCI_OUTDSCR_BURST_EN_M  (BIT(12))
-#define UHCI_OUTDSCR_BURST_EN_V  0x1
-#define UHCI_OUTDSCR_BURST_EN_S  12
-/* UHCI_UART2_CE : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to use UART2 to transmit or receive data.*/
-#define UHCI_UART2_CE  (BIT(11))
-#define UHCI_UART2_CE_M  (BIT(11))
-#define UHCI_UART2_CE_V  0x1
-#define UHCI_UART2_CE_S  11
-/* UHCI_UART1_CE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to use UART1 to transmit or receive data.*/
-#define UHCI_UART1_CE  (BIT(10))
-#define UHCI_UART1_CE_M  (BIT(10))
-#define UHCI_UART1_CE_V  0x1
-#define UHCI_UART1_CE_S  10
-/* UHCI_UART0_CE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to use UART to transmit or receive data.*/
-#define UHCI_UART0_CE  (BIT(9))
-#define UHCI_UART0_CE_M  (BIT(9))
-#define UHCI_UART0_CE_V  0x1
-#define UHCI_UART0_CE_S  9
-/* UHCI_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: Set this bit to produce eof after DMA pops all data  clear this
- bit to produce eof after DMA pushes all data*/
-#define UHCI_OUT_EOF_MODE  (BIT(8))
-#define UHCI_OUT_EOF_MODE_M  (BIT(8))
-#define UHCI_OUT_EOF_MODE_V  0x1
-#define UHCI_OUT_EOF_MODE_S  8
-/* UHCI_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: don't use*/
-#define UHCI_OUT_NO_RESTART_CLR  (BIT(7))
-#define UHCI_OUT_NO_RESTART_CLR_M  (BIT(7))
-#define UHCI_OUT_NO_RESTART_CLR_V  0x1
-#define UHCI_OUT_NO_RESTART_CLR_S  7
-/* UHCI_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: when in link's length is 0  go on to use the next in link automatically.*/
-#define UHCI_OUT_AUTO_WRBACK  (BIT(6))
-#define UHCI_OUT_AUTO_WRBACK_M  (BIT(6))
-#define UHCI_OUT_AUTO_WRBACK_V  0x1
-#define UHCI_OUT_AUTO_WRBACK_S  6
-/* UHCI_OUT_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable loop test for out links.*/
-#define UHCI_OUT_LOOP_TEST  (BIT(5))
-#define UHCI_OUT_LOOP_TEST_M  (BIT(5))
-#define UHCI_OUT_LOOP_TEST_V  0x1
-#define UHCI_OUT_LOOP_TEST_S  5
-/* UHCI_IN_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to enable loop test for in links.*/
-#define UHCI_IN_LOOP_TEST  (BIT(4))
-#define UHCI_IN_LOOP_TEST_M  (BIT(4))
-#define UHCI_IN_LOOP_TEST_V  0x1
-#define UHCI_IN_LOOP_TEST_S  4
-/* UHCI_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to reset dma  ahb interface.*/
-#define UHCI_AHBM_RST  (BIT(3))
-#define UHCI_AHBM_RST_M  (BIT(3))
-#define UHCI_AHBM_RST_V  0x1
-#define UHCI_AHBM_RST_S  3
-/* UHCI_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to reset dma ahb fifo.*/
-#define UHCI_AHBM_FIFO_RST  (BIT(2))
-#define UHCI_AHBM_FIFO_RST_M  (BIT(2))
-#define UHCI_AHBM_FIFO_RST_V  0x1
-#define UHCI_AHBM_FIFO_RST_S  2
-/* UHCI_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to reset out link operations.*/
-#define UHCI_OUT_RST  (BIT(1))
-#define UHCI_OUT_RST_M  (BIT(1))
-#define UHCI_OUT_RST_V  0x1
-#define UHCI_OUT_RST_S  1
-/* UHCI_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Set this bit to reset in link operations.*/
-#define UHCI_IN_RST  (BIT(0))
-#define UHCI_IN_RST_M  (BIT(0))
-#define UHCI_IN_RST_V  0x1
-#define UHCI_IN_RST_S  0
-
-#define UHCI_INT_RAW_REG(i)          (REG_UHCI_BASE(i) + 0x4)
-/* UHCI_DMA_INFIFO_FULL_WM_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW  (BIT(16))
-#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_M  (BIT(16))
-#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_V  0x1
-#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_S  16
-/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: When use always_send registers to send a series of short packets
- it will produce this interrupt when dma has send the short packet.*/
-#define UHCI_SEND_A_Q_INT_RAW  (BIT(15))
-#define UHCI_SEND_A_Q_INT_RAW_M  (BIT(15))
-#define UHCI_SEND_A_Q_INT_RAW_V  0x1
-#define UHCI_SEND_A_Q_INT_RAW_S  15
-/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: When use single send registers to send a short packets it will
- produce this interrupt when dma has send the short packet.*/
-#define UHCI_SEND_S_Q_INT_RAW  (BIT(14))
-#define UHCI_SEND_S_Q_INT_RAW_M  (BIT(14))
-#define UHCI_SEND_S_Q_INT_RAW_V  0x1
-#define UHCI_SEND_S_Q_INT_RAW_S  14
-/* UHCI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: When all data have been send  it will produce uhci_out_total_eof_int interrupt.*/
-#define UHCI_OUT_TOTAL_EOF_INT_RAW  (BIT(13))
-#define UHCI_OUT_TOTAL_EOF_INT_RAW_M  (BIT(13))
-#define UHCI_OUT_TOTAL_EOF_INT_RAW_V  0x1
-#define UHCI_OUT_TOTAL_EOF_INT_RAW_S  13
-/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: when there are some errors about eof in outlink descriptor  it
- will produce uhci_outlink_eof_err_int interrupt.*/
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW  (BIT(12))
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M  (BIT(12))
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S  12
-/* UHCI_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: when there are not enough in links for DMA it will produce uhci_in_dscr_err_int
- interrupt.*/
-#define UHCI_IN_DSCR_EMPTY_INT_RAW  (BIT(11))
-#define UHCI_IN_DSCR_EMPTY_INT_RAW_M  (BIT(11))
-#define UHCI_IN_DSCR_EMPTY_INT_RAW_V  0x1
-#define UHCI_IN_DSCR_EMPTY_INT_RAW_S  11
-/* UHCI_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: when there are some errors about the in link descriptor  it will
- produce uhci_out_dscr_err_int interrupt.*/
-#define UHCI_OUT_DSCR_ERR_INT_RAW  (BIT(10))
-#define UHCI_OUT_DSCR_ERR_INT_RAW_M  (BIT(10))
-#define UHCI_OUT_DSCR_ERR_INT_RAW_V  0x1
-#define UHCI_OUT_DSCR_ERR_INT_RAW_S  10
-/* UHCI_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: when there are some errors about the out link descriptor  it
- will produce uhci_in_dscr_err_int interrupt.*/
-#define UHCI_IN_DSCR_ERR_INT_RAW  (BIT(9))
-#define UHCI_IN_DSCR_ERR_INT_RAW_M  (BIT(9))
-#define UHCI_IN_DSCR_ERR_INT_RAW_V  0x1
-#define UHCI_IN_DSCR_ERR_INT_RAW_S  9
-/* UHCI_OUT_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: when the current descriptor's eof bit is 1  it will produce uhci_out_eof_int
- interrupt.*/
-#define UHCI_OUT_EOF_INT_RAW  (BIT(8))
-#define UHCI_OUT_EOF_INT_RAW_M  (BIT(8))
-#define UHCI_OUT_EOF_INT_RAW_V  0x1
-#define UHCI_OUT_EOF_INT_RAW_S  8
-/* UHCI_OUT_DONE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: when a out link descriptor is completed  it will produce uhci_out_done_int
- interrupt.*/
-#define UHCI_OUT_DONE_INT_RAW  (BIT(7))
-#define UHCI_OUT_DONE_INT_RAW_M  (BIT(7))
-#define UHCI_OUT_DONE_INT_RAW_V  0x1
-#define UHCI_OUT_DONE_INT_RAW_S  7
-/* UHCI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: when there are some errors about eof in in link descriptor  it
- will produce uhci_in_err_eof_int interrupt.*/
-#define UHCI_IN_ERR_EOF_INT_RAW  (BIT(6))
-#define UHCI_IN_ERR_EOF_INT_RAW_M  (BIT(6))
-#define UHCI_IN_ERR_EOF_INT_RAW_V  0x1
-#define UHCI_IN_ERR_EOF_INT_RAW_S  6
-/* UHCI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: when a data packet has been received  it will produce uhci_in_suc_eof_int
- interrupt.*/
-#define UHCI_IN_SUC_EOF_INT_RAW  (BIT(5))
-#define UHCI_IN_SUC_EOF_INT_RAW_M  (BIT(5))
-#define UHCI_IN_SUC_EOF_INT_RAW_V  0x1
-#define UHCI_IN_SUC_EOF_INT_RAW_S  5
-/* UHCI_IN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: when a in link descriptor has been completed it will produce
- uhci_in_done_int interrupt.*/
-#define UHCI_IN_DONE_INT_RAW  (BIT(4))
-#define UHCI_IN_DONE_INT_RAW_M  (BIT(4))
-#define UHCI_IN_DONE_INT_RAW_V  0x1
-#define UHCI_IN_DONE_INT_RAW_S  4
-/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: when DMA takes a lot of time to read a data from RAM  it will
- produce uhci_tx_hung_int interrupt.*/
-#define UHCI_TX_HUNG_INT_RAW  (BIT(3))
-#define UHCI_TX_HUNG_INT_RAW_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_RAW_V  0x1
-#define UHCI_TX_HUNG_INT_RAW_S  3
-/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: when DMA takes a lot of time to receive a data   it will produce
- uhci_rx_hung_int interrupt.*/
-#define UHCI_RX_HUNG_INT_RAW  (BIT(2))
-#define UHCI_RX_HUNG_INT_RAW_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_RAW_V  0x1
-#define UHCI_RX_HUNG_INT_RAW_S  2
-/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/
-#define UHCI_TX_START_INT_RAW  (BIT(1))
-#define UHCI_TX_START_INT_RAW_M  (BIT(1))
-#define UHCI_TX_START_INT_RAW_V  0x1
-#define UHCI_TX_START_INT_RAW_S  1
-/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: when a separator char has been send  it will produce uhci_rx_start_int
- interrupt.*/
-#define UHCI_RX_START_INT_RAW  (BIT(0))
-#define UHCI_RX_START_INT_RAW_M  (BIT(0))
-#define UHCI_RX_START_INT_RAW_V  0x1
-#define UHCI_RX_START_INT_RAW_S  0
-
-#define UHCI_INT_ST_REG(i)          (REG_UHCI_BASE(i) + 0x8)
-/* UHCI_DMA_INFIFO_FULL_WM_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_DMA_INFIFO_FULL_WM_INT_ST  (BIT(16))
-#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_M  (BIT(16))
-#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_V  0x1
-#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_S  16
-/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_SEND_A_Q_INT_ST  (BIT(15))
-#define UHCI_SEND_A_Q_INT_ST_M  (BIT(15))
-#define UHCI_SEND_A_Q_INT_ST_V  0x1
-#define UHCI_SEND_A_Q_INT_ST_S  15
-/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_SEND_S_Q_INT_ST  (BIT(14))
-#define UHCI_SEND_S_Q_INT_ST_M  (BIT(14))
-#define UHCI_SEND_S_Q_INT_ST_V  0x1
-#define UHCI_SEND_S_Q_INT_ST_S  14
-/* UHCI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_TOTAL_EOF_INT_ST  (BIT(13))
-#define UHCI_OUT_TOTAL_EOF_INT_ST_M  (BIT(13))
-#define UHCI_OUT_TOTAL_EOF_INT_ST_V  0x1
-#define UHCI_OUT_TOTAL_EOF_INT_ST_S  13
-/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUTLINK_EOF_ERR_INT_ST  (BIT(12))
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (BIT(12))
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  12
-/* UHCI_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_DSCR_EMPTY_INT_ST  (BIT(11))
-#define UHCI_IN_DSCR_EMPTY_INT_ST_M  (BIT(11))
-#define UHCI_IN_DSCR_EMPTY_INT_ST_V  0x1
-#define UHCI_IN_DSCR_EMPTY_INT_ST_S  11
-/* UHCI_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_DSCR_ERR_INT_ST  (BIT(10))
-#define UHCI_OUT_DSCR_ERR_INT_ST_M  (BIT(10))
-#define UHCI_OUT_DSCR_ERR_INT_ST_V  0x1
-#define UHCI_OUT_DSCR_ERR_INT_ST_S  10
-/* UHCI_IN_DSCR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_DSCR_ERR_INT_ST  (BIT(9))
-#define UHCI_IN_DSCR_ERR_INT_ST_M  (BIT(9))
-#define UHCI_IN_DSCR_ERR_INT_ST_V  0x1
-#define UHCI_IN_DSCR_ERR_INT_ST_S  9
-/* UHCI_OUT_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_EOF_INT_ST  (BIT(8))
-#define UHCI_OUT_EOF_INT_ST_M  (BIT(8))
-#define UHCI_OUT_EOF_INT_ST_V  0x1
-#define UHCI_OUT_EOF_INT_ST_S  8
-/* UHCI_OUT_DONE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_DONE_INT_ST  (BIT(7))
-#define UHCI_OUT_DONE_INT_ST_M  (BIT(7))
-#define UHCI_OUT_DONE_INT_ST_V  0x1
-#define UHCI_OUT_DONE_INT_ST_S  7
-/* UHCI_IN_ERR_EOF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_ERR_EOF_INT_ST  (BIT(6))
-#define UHCI_IN_ERR_EOF_INT_ST_M  (BIT(6))
-#define UHCI_IN_ERR_EOF_INT_ST_V  0x1
-#define UHCI_IN_ERR_EOF_INT_ST_S  6
-/* UHCI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_SUC_EOF_INT_ST  (BIT(5))
-#define UHCI_IN_SUC_EOF_INT_ST_M  (BIT(5))
-#define UHCI_IN_SUC_EOF_INT_ST_V  0x1
-#define UHCI_IN_SUC_EOF_INT_ST_S  5
-/* UHCI_IN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_DONE_INT_ST  (BIT(4))
-#define UHCI_IN_DONE_INT_ST_M  (BIT(4))
-#define UHCI_IN_DONE_INT_ST_V  0x1
-#define UHCI_IN_DONE_INT_ST_S  4
-/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_TX_HUNG_INT_ST  (BIT(3))
-#define UHCI_TX_HUNG_INT_ST_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_ST_V  0x1
-#define UHCI_TX_HUNG_INT_ST_S  3
-/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_RX_HUNG_INT_ST  (BIT(2))
-#define UHCI_RX_HUNG_INT_ST_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_ST_V  0x1
-#define UHCI_RX_HUNG_INT_ST_S  2
-/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_TX_START_INT_ST  (BIT(1))
-#define UHCI_TX_START_INT_ST_M  (BIT(1))
-#define UHCI_TX_START_INT_ST_V  0x1
-#define UHCI_TX_START_INT_ST_S  1
-/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_RX_START_INT_ST  (BIT(0))
-#define UHCI_RX_START_INT_ST_M  (BIT(0))
-#define UHCI_RX_START_INT_ST_V  0x1
-#define UHCI_RX_START_INT_ST_S  0
-
-#define UHCI_INT_ENA_REG(i)          (REG_UHCI_BASE(i) + 0xC)
-/* UHCI_DMA_INFIFO_FULL_WM_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA  (BIT(16))
-#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_M  (BIT(16))
-#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_V  0x1
-#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_S  16
-/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_SEND_A_Q_INT_ENA  (BIT(15))
-#define UHCI_SEND_A_Q_INT_ENA_M  (BIT(15))
-#define UHCI_SEND_A_Q_INT_ENA_V  0x1
-#define UHCI_SEND_A_Q_INT_ENA_S  15
-/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_SEND_S_Q_INT_ENA  (BIT(14))
-#define UHCI_SEND_S_Q_INT_ENA_M  (BIT(14))
-#define UHCI_SEND_S_Q_INT_ENA_V  0x1
-#define UHCI_SEND_S_Q_INT_ENA_S  14
-/* UHCI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_TOTAL_EOF_INT_ENA  (BIT(13))
-#define UHCI_OUT_TOTAL_EOF_INT_ENA_M  (BIT(13))
-#define UHCI_OUT_TOTAL_EOF_INT_ENA_V  0x1
-#define UHCI_OUT_TOTAL_EOF_INT_ENA_S  13
-/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA  (BIT(12))
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (BIT(12))
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  12
-/* UHCI_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_DSCR_EMPTY_INT_ENA  (BIT(11))
-#define UHCI_IN_DSCR_EMPTY_INT_ENA_M  (BIT(11))
-#define UHCI_IN_DSCR_EMPTY_INT_ENA_V  0x1
-#define UHCI_IN_DSCR_EMPTY_INT_ENA_S  11
-/* UHCI_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_DSCR_ERR_INT_ENA  (BIT(10))
-#define UHCI_OUT_DSCR_ERR_INT_ENA_M  (BIT(10))
-#define UHCI_OUT_DSCR_ERR_INT_ENA_V  0x1
-#define UHCI_OUT_DSCR_ERR_INT_ENA_S  10
-/* UHCI_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_DSCR_ERR_INT_ENA  (BIT(9))
-#define UHCI_IN_DSCR_ERR_INT_ENA_M  (BIT(9))
-#define UHCI_IN_DSCR_ERR_INT_ENA_V  0x1
-#define UHCI_IN_DSCR_ERR_INT_ENA_S  9
-/* UHCI_OUT_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_EOF_INT_ENA  (BIT(8))
-#define UHCI_OUT_EOF_INT_ENA_M  (BIT(8))
-#define UHCI_OUT_EOF_INT_ENA_V  0x1
-#define UHCI_OUT_EOF_INT_ENA_S  8
-/* UHCI_OUT_DONE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_DONE_INT_ENA  (BIT(7))
-#define UHCI_OUT_DONE_INT_ENA_M  (BIT(7))
-#define UHCI_OUT_DONE_INT_ENA_V  0x1
-#define UHCI_OUT_DONE_INT_ENA_S  7
-/* UHCI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_ERR_EOF_INT_ENA  (BIT(6))
-#define UHCI_IN_ERR_EOF_INT_ENA_M  (BIT(6))
-#define UHCI_IN_ERR_EOF_INT_ENA_V  0x1
-#define UHCI_IN_ERR_EOF_INT_ENA_S  6
-/* UHCI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_SUC_EOF_INT_ENA  (BIT(5))
-#define UHCI_IN_SUC_EOF_INT_ENA_M  (BIT(5))
-#define UHCI_IN_SUC_EOF_INT_ENA_V  0x1
-#define UHCI_IN_SUC_EOF_INT_ENA_S  5
-/* UHCI_IN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_DONE_INT_ENA  (BIT(4))
-#define UHCI_IN_DONE_INT_ENA_M  (BIT(4))
-#define UHCI_IN_DONE_INT_ENA_V  0x1
-#define UHCI_IN_DONE_INT_ENA_S  4
-/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_TX_HUNG_INT_ENA  (BIT(3))
-#define UHCI_TX_HUNG_INT_ENA_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_ENA_V  0x1
-#define UHCI_TX_HUNG_INT_ENA_S  3
-/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_RX_HUNG_INT_ENA  (BIT(2))
-#define UHCI_RX_HUNG_INT_ENA_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_ENA_V  0x1
-#define UHCI_RX_HUNG_INT_ENA_S  2
-/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_TX_START_INT_ENA  (BIT(1))
-#define UHCI_TX_START_INT_ENA_M  (BIT(1))
-#define UHCI_TX_START_INT_ENA_V  0x1
-#define UHCI_TX_START_INT_ENA_S  1
-/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_RX_START_INT_ENA  (BIT(0))
-#define UHCI_RX_START_INT_ENA_M  (BIT(0))
-#define UHCI_RX_START_INT_ENA_V  0x1
-#define UHCI_RX_START_INT_ENA_S  0
-
-#define UHCI_INT_CLR_REG(i)          (REG_UHCI_BASE(i) + 0x10)
-/* UHCI_DMA_INFIFO_FULL_WM_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR  (BIT(16))
-#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_M  (BIT(16))
-#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_V  0x1
-#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_S  16
-/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_SEND_A_Q_INT_CLR  (BIT(15))
-#define UHCI_SEND_A_Q_INT_CLR_M  (BIT(15))
-#define UHCI_SEND_A_Q_INT_CLR_V  0x1
-#define UHCI_SEND_A_Q_INT_CLR_S  15
-/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_SEND_S_Q_INT_CLR  (BIT(14))
-#define UHCI_SEND_S_Q_INT_CLR_M  (BIT(14))
-#define UHCI_SEND_S_Q_INT_CLR_V  0x1
-#define UHCI_SEND_S_Q_INT_CLR_S  14
-/* UHCI_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_TOTAL_EOF_INT_CLR  (BIT(13))
-#define UHCI_OUT_TOTAL_EOF_INT_CLR_M  (BIT(13))
-#define UHCI_OUT_TOTAL_EOF_INT_CLR_V  0x1
-#define UHCI_OUT_TOTAL_EOF_INT_CLR_S  13
-/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR  (BIT(12))
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (BIT(12))
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  12
-/* UHCI_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_DSCR_EMPTY_INT_CLR  (BIT(11))
-#define UHCI_IN_DSCR_EMPTY_INT_CLR_M  (BIT(11))
-#define UHCI_IN_DSCR_EMPTY_INT_CLR_V  0x1
-#define UHCI_IN_DSCR_EMPTY_INT_CLR_S  11
-/* UHCI_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_DSCR_ERR_INT_CLR  (BIT(10))
-#define UHCI_OUT_DSCR_ERR_INT_CLR_M  (BIT(10))
-#define UHCI_OUT_DSCR_ERR_INT_CLR_V  0x1
-#define UHCI_OUT_DSCR_ERR_INT_CLR_S  10
-/* UHCI_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_DSCR_ERR_INT_CLR  (BIT(9))
-#define UHCI_IN_DSCR_ERR_INT_CLR_M  (BIT(9))
-#define UHCI_IN_DSCR_ERR_INT_CLR_V  0x1
-#define UHCI_IN_DSCR_ERR_INT_CLR_S  9
-/* UHCI_OUT_EOF_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_EOF_INT_CLR  (BIT(8))
-#define UHCI_OUT_EOF_INT_CLR_M  (BIT(8))
-#define UHCI_OUT_EOF_INT_CLR_V  0x1
-#define UHCI_OUT_EOF_INT_CLR_S  8
-/* UHCI_OUT_DONE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_OUT_DONE_INT_CLR  (BIT(7))
-#define UHCI_OUT_DONE_INT_CLR_M  (BIT(7))
-#define UHCI_OUT_DONE_INT_CLR_V  0x1
-#define UHCI_OUT_DONE_INT_CLR_S  7
-/* UHCI_IN_ERR_EOF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_ERR_EOF_INT_CLR  (BIT(6))
-#define UHCI_IN_ERR_EOF_INT_CLR_M  (BIT(6))
-#define UHCI_IN_ERR_EOF_INT_CLR_V  0x1
-#define UHCI_IN_ERR_EOF_INT_CLR_S  6
-/* UHCI_IN_SUC_EOF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_SUC_EOF_INT_CLR  (BIT(5))
-#define UHCI_IN_SUC_EOF_INT_CLR_M  (BIT(5))
-#define UHCI_IN_SUC_EOF_INT_CLR_V  0x1
-#define UHCI_IN_SUC_EOF_INT_CLR_S  5
-/* UHCI_IN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_DONE_INT_CLR  (BIT(4))
-#define UHCI_IN_DONE_INT_CLR_M  (BIT(4))
-#define UHCI_IN_DONE_INT_CLR_V  0x1
-#define UHCI_IN_DONE_INT_CLR_S  4
-/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_TX_HUNG_INT_CLR  (BIT(3))
-#define UHCI_TX_HUNG_INT_CLR_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_CLR_V  0x1
-#define UHCI_TX_HUNG_INT_CLR_S  3
-/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_RX_HUNG_INT_CLR  (BIT(2))
-#define UHCI_RX_HUNG_INT_CLR_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_CLR_V  0x1
-#define UHCI_RX_HUNG_INT_CLR_S  2
-/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_TX_START_INT_CLR  (BIT(1))
-#define UHCI_TX_START_INT_CLR_M  (BIT(1))
-#define UHCI_TX_START_INT_CLR_V  0x1
-#define UHCI_TX_START_INT_CLR_S  1
-/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_RX_START_INT_CLR  (BIT(0))
-#define UHCI_RX_START_INT_CLR_M  (BIT(0))
-#define UHCI_RX_START_INT_CLR_V  0x1
-#define UHCI_RX_START_INT_CLR_S  0
-
-#define UHCI_DMA_OUT_STATUS_REG(i)          (REG_UHCI_BASE(i) + 0x14)
-/* UHCI_OUT_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: 1:DMA in link descriptor's fifo is empty.*/
-#define UHCI_OUT_EMPTY  (BIT(1))
-#define UHCI_OUT_EMPTY_M  (BIT(1))
-#define UHCI_OUT_EMPTY_V  0x1
-#define UHCI_OUT_EMPTY_S  1
-/* UHCI_OUT_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1:DMA out link descriptor's fifo is full.*/
-#define UHCI_OUT_FULL  (BIT(0))
-#define UHCI_OUT_FULL_M  (BIT(0))
-#define UHCI_OUT_FULL_V  0x1
-#define UHCI_OUT_FULL_S  0
-
-#define UHCI_DMA_OUT_PUSH_REG(i)          (REG_UHCI_BASE(i) + 0x18)
-/* UHCI_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: Set this bit to push data in out link descriptor's fifo.*/
-#define UHCI_OUTFIFO_PUSH  (BIT(16))
-#define UHCI_OUTFIFO_PUSH_M  (BIT(16))
-#define UHCI_OUTFIFO_PUSH_V  0x1
-#define UHCI_OUTFIFO_PUSH_S  16
-/* UHCI_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: This is the data need to be pushed into out link descriptor's fifo.*/
-#define UHCI_OUTFIFO_WDATA  0x000001FF
-#define UHCI_OUTFIFO_WDATA_M  ((UHCI_OUTFIFO_WDATA_V)<<(UHCI_OUTFIFO_WDATA_S))
-#define UHCI_OUTFIFO_WDATA_V  0x1FF
-#define UHCI_OUTFIFO_WDATA_S  0
-
-#define UHCI_DMA_IN_STATUS_REG(i)          (REG_UHCI_BASE(i) + 0x1C)
-/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[6:4] ;default: 3'h0 ; */
-/*description: This register stores the errors caused in out link descriptor's data packet.*/
-#define UHCI_RX_ERR_CAUSE  0x00000007
-#define UHCI_RX_ERR_CAUSE_M  ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
-#define UHCI_RX_ERR_CAUSE_V  0x7
-#define UHCI_RX_ERR_CAUSE_S  4
-/* UHCI_IN_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define UHCI_IN_EMPTY  (BIT(1))
-#define UHCI_IN_EMPTY_M  (BIT(1))
-#define UHCI_IN_EMPTY_V  0x1
-#define UHCI_IN_EMPTY_S  1
-/* UHCI_IN_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define UHCI_IN_FULL  (BIT(0))
-#define UHCI_IN_FULL_M  (BIT(0))
-#define UHCI_IN_FULL_V  0x1
-#define UHCI_IN_FULL_S  0
-
-#define UHCI_DMA_IN_POP_REG(i)          (REG_UHCI_BASE(i) + 0x20)
-/* UHCI_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: Set this bit to pop data in in link descriptor's fifo.*/
-#define UHCI_INFIFO_POP  (BIT(16))
-#define UHCI_INFIFO_POP_M  (BIT(16))
-#define UHCI_INFIFO_POP_V  0x1
-#define UHCI_INFIFO_POP_S  16
-/* UHCI_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: This register stores the data pop from in link descriptor's fifo.*/
-#define UHCI_INFIFO_RDATA  0x00000FFF
-#define UHCI_INFIFO_RDATA_M  ((UHCI_INFIFO_RDATA_V)<<(UHCI_INFIFO_RDATA_S))
-#define UHCI_INFIFO_RDATA_V  0xFFF
-#define UHCI_INFIFO_RDATA_S  0
-
-#define UHCI_DMA_OUT_LINK_REG(i)          (REG_UHCI_BASE(i) + 0x24)
-/* UHCI_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: 1£º the out link descriptor's fsm is in idle state. 0:the out
- link descriptor's fsm is working.*/
-#define UHCI_OUTLINK_PARK  (BIT(31))
-#define UHCI_OUTLINK_PARK_M  (BIT(31))
-#define UHCI_OUTLINK_PARK_V  0x1
-#define UHCI_OUTLINK_PARK_S  31
-/* UHCI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to mount on new out link descriptors*/
-#define UHCI_OUTLINK_RESTART  (BIT(30))
-#define UHCI_OUTLINK_RESTART_M  (BIT(30))
-#define UHCI_OUTLINK_RESTART_V  0x1
-#define UHCI_OUTLINK_RESTART_S  30
-/* UHCI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to start dealing with the out link descriptors.*/
-#define UHCI_OUTLINK_START  (BIT(29))
-#define UHCI_OUTLINK_START_M  (BIT(29))
-#define UHCI_OUTLINK_START_V  0x1
-#define UHCI_OUTLINK_START_S  29
-/* UHCI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to stop dealing with the out link descriptors.*/
-#define UHCI_OUTLINK_STOP  (BIT(28))
-#define UHCI_OUTLINK_STOP_M  (BIT(28))
-#define UHCI_OUTLINK_STOP_V  0x1
-#define UHCI_OUTLINK_STOP_S  28
-/* UHCI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: This register stores the least 20 bits of the first out link
- descriptor's address.*/
-#define UHCI_OUTLINK_ADDR  0x000FFFFF
-#define UHCI_OUTLINK_ADDR_M  ((UHCI_OUTLINK_ADDR_V)<<(UHCI_OUTLINK_ADDR_S))
-#define UHCI_OUTLINK_ADDR_V  0xFFFFF
-#define UHCI_OUTLINK_ADDR_S  0
-
-#define UHCI_DMA_IN_LINK_REG(i)          (REG_UHCI_BASE(i) + 0x28)
-/* UHCI_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: 1:the in link descriptor's fsm is in idle state.   0:the in link
- descriptor's fsm is working*/
-#define UHCI_INLINK_PARK  (BIT(31))
-#define UHCI_INLINK_PARK_M  (BIT(31))
-#define UHCI_INLINK_PARK_V  0x1
-#define UHCI_INLINK_PARK_S  31
-/* UHCI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to mount on new in link descriptors*/
-#define UHCI_INLINK_RESTART  (BIT(30))
-#define UHCI_INLINK_RESTART_M  (BIT(30))
-#define UHCI_INLINK_RESTART_V  0x1
-#define UHCI_INLINK_RESTART_S  30
-/* UHCI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to start dealing with the in link descriptors.*/
-#define UHCI_INLINK_START  (BIT(29))
-#define UHCI_INLINK_START_M  (BIT(29))
-#define UHCI_INLINK_START_V  0x1
-#define UHCI_INLINK_START_S  29
-/* UHCI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to stop dealing with the in link descriptors.*/
-#define UHCI_INLINK_STOP  (BIT(28))
-#define UHCI_INLINK_STOP_M  (BIT(28))
-#define UHCI_INLINK_STOP_V  0x1
-#define UHCI_INLINK_STOP_S  28
-/* UHCI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: 1:when a packet is wrong in link descriptor returns to the descriptor
- which is lately used.*/
-#define UHCI_INLINK_AUTO_RET  (BIT(20))
-#define UHCI_INLINK_AUTO_RET_M  (BIT(20))
-#define UHCI_INLINK_AUTO_RET_V  0x1
-#define UHCI_INLINK_AUTO_RET_S  20
-/* UHCI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
-/*description: This register stores the least 20 bits of the first in link descriptor's
- address.*/
-#define UHCI_INLINK_ADDR  0x000FFFFF
-#define UHCI_INLINK_ADDR_M  ((UHCI_INLINK_ADDR_V)<<(UHCI_INLINK_ADDR_S))
-#define UHCI_INLINK_ADDR_V  0xFFFFF
-#define UHCI_INLINK_ADDR_S  0
-
-#define UHCI_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x2C)
-/* UHCI_DMA_INFIFO_FULL_THRS : R/W ;bitpos:[20:9] ;default: 12'b0 ; */
-/*description: when data amount in link descriptor's fifo is more than this
- register value  it will produce uhci_dma_infifo_full_wm_int interrupt.*/
-#define UHCI_DMA_INFIFO_FULL_THRS  0x00000FFF
-#define UHCI_DMA_INFIFO_FULL_THRS_M  ((UHCI_DMA_INFIFO_FULL_THRS_V)<<(UHCI_DMA_INFIFO_FULL_THRS_S))
-#define UHCI_DMA_INFIFO_FULL_THRS_V  0xFFF
-#define UHCI_DMA_INFIFO_FULL_THRS_S  9
-/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to start inserting the packet header.*/
-#define UHCI_SW_START  (BIT(8))
-#define UHCI_SW_START_M  (BIT(8))
-#define UHCI_SW_START_V  0x1
-#define UHCI_SW_START_S  8
-/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to enable software way to add packet header.*/
-#define UHCI_WAIT_SW_START  (BIT(7))
-#define UHCI_WAIT_SW_START_M  (BIT(7))
-#define UHCI_WAIT_SW_START_V  0x1
-#define UHCI_WAIT_SW_START_S  7
-/* UHCI_CHECK_OWNER : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to check the owner bit in link descriptor.*/
-#define UHCI_CHECK_OWNER  (BIT(6))
-#define UHCI_CHECK_OWNER_M  (BIT(6))
-#define UHCI_CHECK_OWNER_V  0x1
-#define UHCI_CHECK_OWNER_S  6
-/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: Set this bit to enable hardware replace ack num in packet header automatically.*/
-#define UHCI_TX_ACK_NUM_RE  (BIT(5))
-#define UHCI_TX_ACK_NUM_RE_M  (BIT(5))
-#define UHCI_TX_ACK_NUM_RE_V  0x1
-#define UHCI_TX_ACK_NUM_RE_S  5
-/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: Set this bit to enable hardware replace check_sum in packet header
- automatically.*/
-#define UHCI_TX_CHECK_SUM_RE  (BIT(4))
-#define UHCI_TX_CHECK_SUM_RE_M  (BIT(4))
-#define UHCI_TX_CHECK_SUM_RE_V  0x1
-#define UHCI_TX_CHECK_SUM_RE_S  4
-/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to save packet header .*/
-#define UHCI_SAVE_HEAD  (BIT(3))
-#define UHCI_SAVE_HEAD_M  (BIT(3))
-#define UHCI_SAVE_HEAD_V  0x1
-#define UHCI_SAVE_HEAD_S  3
-/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to disable crc calculation.*/
-#define UHCI_CRC_DISABLE  (BIT(2))
-#define UHCI_CRC_DISABLE_M  (BIT(2))
-#define UHCI_CRC_DISABLE_V  0x1
-#define UHCI_CRC_DISABLE_S  2
-/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Set this bit to enable decoder to check seq num in packet header.*/
-#define UHCI_CHECK_SEQ_EN  (BIT(1))
-#define UHCI_CHECK_SEQ_EN_M  (BIT(1))
-#define UHCI_CHECK_SEQ_EN_V  0x1
-#define UHCI_CHECK_SEQ_EN_S  1
-/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Set this bit to enable decoder to check  check_sum in packet header.*/
-#define UHCI_CHECK_SUM_EN  (BIT(0))
-#define UHCI_CHECK_SUM_EN_M  (BIT(0))
-#define UHCI_CHECK_SUM_EN_V  0x1
-#define UHCI_CHECK_SUM_EN_S  0
-
-#define UHCI_STATE0_REG(i)          (REG_UHCI_BASE(i) + 0x30)
-/* UHCI_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define UHCI_STATE0  0xFFFFFFFF
-#define UHCI_STATE0_M  ((UHCI_STATE0_V)<<(UHCI_STATE0_S))
-#define UHCI_STATE0_V  0xFFFFFFFF
-#define UHCI_STATE0_S  0
-
-#define UHCI_STATE1_REG(i)          (REG_UHCI_BASE(i) + 0x34)
-/* UHCI_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define UHCI_STATE1  0xFFFFFFFF
-#define UHCI_STATE1_M  ((UHCI_STATE1_V)<<(UHCI_STATE1_S))
-#define UHCI_STATE1_V  0xFFFFFFFF
-#define UHCI_STATE1_S  0
-
-#define UHCI_DMA_OUT_EOF_DES_ADDR_REG(i)          (REG_UHCI_BASE(i) + 0x38)
-/* UHCI_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the address of out link descriptoir when
- eof bit in this descriptor is 1.*/
-#define UHCI_OUT_EOF_DES_ADDR  0xFFFFFFFF
-#define UHCI_OUT_EOF_DES_ADDR_M  ((UHCI_OUT_EOF_DES_ADDR_V)<<(UHCI_OUT_EOF_DES_ADDR_S))
-#define UHCI_OUT_EOF_DES_ADDR_V  0xFFFFFFFF
-#define UHCI_OUT_EOF_DES_ADDR_S  0
-
-#define UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG(i)          (REG_UHCI_BASE(i) + 0x3C)
-/* UHCI_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the address of in link descriptor when eof
- bit in this descriptor is 1.*/
-#define UHCI_IN_SUC_EOF_DES_ADDR  0xFFFFFFFF
-#define UHCI_IN_SUC_EOF_DES_ADDR_M  ((UHCI_IN_SUC_EOF_DES_ADDR_V)<<(UHCI_IN_SUC_EOF_DES_ADDR_S))
-#define UHCI_IN_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
-#define UHCI_IN_SUC_EOF_DES_ADDR_S  0
-
-#define UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG(i)          (REG_UHCI_BASE(i) + 0x40)
-/* UHCI_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the address of in link descriptor when there
- are some errors in this descriptor.*/
-#define UHCI_IN_ERR_EOF_DES_ADDR  0xFFFFFFFF
-#define UHCI_IN_ERR_EOF_DES_ADDR_M  ((UHCI_IN_ERR_EOF_DES_ADDR_V)<<(UHCI_IN_ERR_EOF_DES_ADDR_S))
-#define UHCI_IN_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
-#define UHCI_IN_ERR_EOF_DES_ADDR_S  0
-
-#define UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG(i)          (REG_UHCI_BASE(i) + 0x44)
-/* UHCI_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the address of out link descriptor when
- there are some errors in this descriptor.*/
-#define UHCI_OUT_EOF_BFR_DES_ADDR  0xFFFFFFFF
-#define UHCI_OUT_EOF_BFR_DES_ADDR_M  ((UHCI_OUT_EOF_BFR_DES_ADDR_V)<<(UHCI_OUT_EOF_BFR_DES_ADDR_S))
-#define UHCI_OUT_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
-#define UHCI_OUT_EOF_BFR_DES_ADDR_S  0
-
-#define UHCI_AHB_TEST_REG(i)          (REG_UHCI_BASE(i) + 0x48)
-/* UHCI_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: The two bits represent ahb bus address bit[20:19]*/
-#define UHCI_AHB_TESTADDR  0x00000003
-#define UHCI_AHB_TESTADDR_M  ((UHCI_AHB_TESTADDR_V)<<(UHCI_AHB_TESTADDR_S))
-#define UHCI_AHB_TESTADDR_V  0x3
-#define UHCI_AHB_TESTADDR_S  4
-/* UHCI_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1)
- or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
-#define UHCI_AHB_TESTMODE  0x00000007
-#define UHCI_AHB_TESTMODE_M  ((UHCI_AHB_TESTMODE_V)<<(UHCI_AHB_TESTMODE_S))
-#define UHCI_AHB_TESTMODE_V  0x7
-#define UHCI_AHB_TESTMODE_S  0
-
-#define UHCI_DMA_IN_DSCR_REG(i)          (REG_UHCI_BASE(i) + 0x4C)
-/* UHCI_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current in link descriptor's third dword*/
-#define UHCI_INLINK_DSCR  0xFFFFFFFF
-#define UHCI_INLINK_DSCR_M  ((UHCI_INLINK_DSCR_V)<<(UHCI_INLINK_DSCR_S))
-#define UHCI_INLINK_DSCR_V  0xFFFFFFFF
-#define UHCI_INLINK_DSCR_S  0
-
-#define UHCI_DMA_IN_DSCR_BF0_REG(i)          (REG_UHCI_BASE(i) + 0x50)
-/* UHCI_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current in link descriptor's first dword*/
-#define UHCI_INLINK_DSCR_BF0  0xFFFFFFFF
-#define UHCI_INLINK_DSCR_BF0_M  ((UHCI_INLINK_DSCR_BF0_V)<<(UHCI_INLINK_DSCR_BF0_S))
-#define UHCI_INLINK_DSCR_BF0_V  0xFFFFFFFF
-#define UHCI_INLINK_DSCR_BF0_S  0
-
-#define UHCI_DMA_IN_DSCR_BF1_REG(i)          (REG_UHCI_BASE(i) + 0x54)
-/* UHCI_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current in link descriptor's second dword*/
-#define UHCI_INLINK_DSCR_BF1  0xFFFFFFFF
-#define UHCI_INLINK_DSCR_BF1_M  ((UHCI_INLINK_DSCR_BF1_V)<<(UHCI_INLINK_DSCR_BF1_S))
-#define UHCI_INLINK_DSCR_BF1_V  0xFFFFFFFF
-#define UHCI_INLINK_DSCR_BF1_S  0
-
-#define UHCI_DMA_OUT_DSCR_REG(i)          (REG_UHCI_BASE(i) + 0x58)
-/* UHCI_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current out link descriptor's third dword*/
-#define UHCI_OUTLINK_DSCR  0xFFFFFFFF
-#define UHCI_OUTLINK_DSCR_M  ((UHCI_OUTLINK_DSCR_V)<<(UHCI_OUTLINK_DSCR_S))
-#define UHCI_OUTLINK_DSCR_V  0xFFFFFFFF
-#define UHCI_OUTLINK_DSCR_S  0
-
-#define UHCI_DMA_OUT_DSCR_BF0_REG(i)          (REG_UHCI_BASE(i) + 0x5C)
-/* UHCI_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current out link descriptor's first dword*/
-#define UHCI_OUTLINK_DSCR_BF0  0xFFFFFFFF
-#define UHCI_OUTLINK_DSCR_BF0_M  ((UHCI_OUTLINK_DSCR_BF0_V)<<(UHCI_OUTLINK_DSCR_BF0_S))
-#define UHCI_OUTLINK_DSCR_BF0_V  0xFFFFFFFF
-#define UHCI_OUTLINK_DSCR_BF0_S  0
-
-#define UHCI_DMA_OUT_DSCR_BF1_REG(i)          (REG_UHCI_BASE(i) + 0x60)
-/* UHCI_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The content of current out link descriptor's second dword*/
-#define UHCI_OUTLINK_DSCR_BF1  0xFFFFFFFF
-#define UHCI_OUTLINK_DSCR_BF1_M  ((UHCI_OUTLINK_DSCR_BF1_V)<<(UHCI_OUTLINK_DSCR_BF1_S))
-#define UHCI_OUTLINK_DSCR_BF1_V  0xFFFFFFFF
-#define UHCI_OUTLINK_DSCR_BF1_S  0
-
-#define UHCI_ESCAPE_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x64)
-/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to enable  flow control char 0x13 replace when DMA sends data.*/
-#define UHCI_RX_13_ESC_EN  (BIT(7))
-#define UHCI_RX_13_ESC_EN_M  (BIT(7))
-#define UHCI_RX_13_ESC_EN_V  0x1
-#define UHCI_RX_13_ESC_EN_S  7
-/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to enable  flow control char 0x11 replace when DMA sends data.*/
-#define UHCI_RX_11_ESC_EN  (BIT(6))
-#define UHCI_RX_11_ESC_EN_M  (BIT(6))
-#define UHCI_RX_11_ESC_EN_V  0x1
-#define UHCI_RX_11_ESC_EN_S  6
-/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: Set this bit to enable  0xdb char replace when DMA sends data.*/
-#define UHCI_RX_DB_ESC_EN  (BIT(5))
-#define UHCI_RX_DB_ESC_EN_M  (BIT(5))
-#define UHCI_RX_DB_ESC_EN_V  0x1
-#define UHCI_RX_DB_ESC_EN_S  5
-/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: Set this bit to enable  0xc0 char replace when DMA sends data.*/
-#define UHCI_RX_C0_ESC_EN  (BIT(4))
-#define UHCI_RX_C0_ESC_EN_M  (BIT(4))
-#define UHCI_RX_C0_ESC_EN_V  0x1
-#define UHCI_RX_C0_ESC_EN_S  4
-/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable flow control char 0x13 decode when DMA receives data.*/
-#define UHCI_TX_13_ESC_EN  (BIT(3))
-#define UHCI_TX_13_ESC_EN_M  (BIT(3))
-#define UHCI_TX_13_ESC_EN_V  0x1
-#define UHCI_TX_13_ESC_EN_S  3
-/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to enable  flow control char 0x11 decode when DMA receives data.*/
-#define UHCI_TX_11_ESC_EN  (BIT(2))
-#define UHCI_TX_11_ESC_EN_M  (BIT(2))
-#define UHCI_TX_11_ESC_EN_V  0x1
-#define UHCI_TX_11_ESC_EN_S  2
-/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Set this bit to enable  0xdb char decode when DMA receives data.*/
-#define UHCI_TX_DB_ESC_EN  (BIT(1))
-#define UHCI_TX_DB_ESC_EN_M  (BIT(1))
-#define UHCI_TX_DB_ESC_EN_V  0x1
-#define UHCI_TX_DB_ESC_EN_S  1
-/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Set this bit to enable  0xc0 char decode when DMA receives data.*/
-#define UHCI_TX_C0_ESC_EN  (BIT(0))
-#define UHCI_TX_C0_ESC_EN_M  (BIT(0))
-#define UHCI_TX_C0_ESC_EN_V  0x1
-#define UHCI_TX_C0_ESC_EN_S  0
-
-#define UHCI_HUNG_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x68)
-/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: This is the enable bit for DMA  send data timeout*/
-#define UHCI_RXFIFO_TIMEOUT_ENA  (BIT(23))
-#define UHCI_RXFIFO_TIMEOUT_ENA_M  (BIT(23))
-#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x1
-#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
-/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
-/*description: The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/
-#define UHCI_RXFIFO_TIMEOUT_SHIFT  0x00000007
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x7
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
-/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
-/*description: This register stores the timeout value.when DMA takes more time
- than this register value to read a data from RAM  it will produce  uhci_rx_hung_int interrupt.*/
-#define UHCI_RXFIFO_TIMEOUT  0x000000FF
-#define UHCI_RXFIFO_TIMEOUT_M  ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
-#define UHCI_RXFIFO_TIMEOUT_V  0xFF
-#define UHCI_RXFIFO_TIMEOUT_S  12
-/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: The enable bit for txfifo receive data  timeout*/
-#define UHCI_TXFIFO_TIMEOUT_ENA  (BIT(11))
-#define UHCI_TXFIFO_TIMEOUT_ENA_M  (BIT(11))
-#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x1
-#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
-/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
-/*description: The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/
-#define UHCI_TXFIFO_TIMEOUT_SHIFT  0x00000007
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x7
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
-/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
-/*description: This register stores the timeout value.when DMA takes more time
- than this register value to receive a data  it will produce  uhci_tx_hung_int interrupt.*/
-#define UHCI_TXFIFO_TIMEOUT  0x000000FF
-#define UHCI_TXFIFO_TIMEOUT_M  ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
-#define UHCI_TXFIFO_TIMEOUT_V  0xFF
-#define UHCI_TXFIFO_TIMEOUT_S  0
-
-#define UHCI_ACK_NUM_REG(i)          (REG_UHCI_BASE(i) + 0x6C)
-
-#define UHCI_RX_HEAD_REG(i)          (REG_UHCI_BASE(i) + 0x70)
-/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the packet header received by DMA*/
-#define UHCI_RX_HEAD  0xFFFFFFFF
-#define UHCI_RX_HEAD_M  ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
-#define UHCI_RX_HEAD_V  0xFFFFFFFF
-#define UHCI_RX_HEAD_S  0
-
-#define UHCI_QUICK_SENT_REG(i)          (REG_UHCI_BASE(i) + 0x74)
-/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to enable continuously send the same short packet*/
-#define UHCI_ALWAYS_SEND_EN  (BIT(7))
-#define UHCI_ALWAYS_SEND_EN_M  (BIT(7))
-#define UHCI_ALWAYS_SEND_EN_V  0x1
-#define UHCI_ALWAYS_SEND_EN_S  7
-/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
-/*description: The bits are used to choose which short packet*/
-#define UHCI_ALWAYS_SEND_NUM  0x00000007
-#define UHCI_ALWAYS_SEND_NUM_M  ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
-#define UHCI_ALWAYS_SEND_NUM_V  0x7
-#define UHCI_ALWAYS_SEND_NUM_S  4
-/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable  send a short packet*/
-#define UHCI_SINGLE_SEND_EN  (BIT(3))
-#define UHCI_SINGLE_SEND_EN_M  (BIT(3))
-#define UHCI_SINGLE_SEND_EN_V  0x1
-#define UHCI_SINGLE_SEND_EN_S  3
-/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: The bits are used to choose which short packet*/
-#define UHCI_SINGLE_SEND_NUM  0x00000007
-#define UHCI_SINGLE_SEND_NUM_M  ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
-#define UHCI_SINGLE_SEND_NUM_V  0x7
-#define UHCI_SINGLE_SEND_NUM_S  0
-
-#define UHCI_Q0_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x78)
-/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's first dword*/
-#define UHCI_SEND_Q0_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD0_M  ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
-#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD0_S  0
-
-#define UHCI_Q0_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x7C)
-/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's second dword*/
-#define UHCI_SEND_Q0_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD1_M  ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
-#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD1_S  0
-
-#define UHCI_Q1_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x80)
-/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's first dword*/
-#define UHCI_SEND_Q1_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD0_M  ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
-#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD0_S  0
-
-#define UHCI_Q1_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x84)
-/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's second dword*/
-#define UHCI_SEND_Q1_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD1_M  ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
-#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD1_S  0
-
-#define UHCI_Q2_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x88)
-/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's first dword*/
-#define UHCI_SEND_Q2_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD0_M  ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
-#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD0_S  0
-
-#define UHCI_Q2_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x8C)
-/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's second dword*/
-#define UHCI_SEND_Q2_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD1_M  ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
-#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD1_S  0
-
-#define UHCI_Q3_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x90)
-/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's first dword*/
-#define UHCI_SEND_Q3_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD0_M  ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
-#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD0_S  0
-
-#define UHCI_Q3_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x94)
-/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's second dword*/
-#define UHCI_SEND_Q3_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD1_M  ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
-#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD1_S  0
-
-#define UHCI_Q4_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x98)
-/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's first dword*/
-#define UHCI_SEND_Q4_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD0_M  ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
-#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD0_S  0
-
-#define UHCI_Q4_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x9C)
-/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's second dword*/
-#define UHCI_SEND_Q4_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD1_M  ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
-#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD1_S  0
-
-#define UHCI_Q5_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0xA0)
-/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's first dword*/
-#define UHCI_SEND_Q5_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD0_M  ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
-#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD0_S  0
-
-#define UHCI_Q5_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0xA4)
-/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's second dword*/
-#define UHCI_SEND_Q5_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD1_M  ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
-#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD1_S  0
-
-#define UHCI_Q6_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0xA8)
-/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's first dword*/
-#define UHCI_SEND_Q6_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD0_M  ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
-#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD0_S  0
-
-#define UHCI_Q6_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0xAC)
-/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This register stores the content of short packet's second dword*/
-#define UHCI_SEND_Q6_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD1_M  ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
-#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD1_S  0
-
-#define UHCI_ESC_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0xB0)
-/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
-/*description: This register stores the second char used to replace seperator
- char in data . 0xdc 0xdb replace 0xc0 by default.*/
-#define UHCI_SEPER_ESC_CHAR1  0x000000FF
-#define UHCI_SEPER_ESC_CHAR1_M  ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
-#define UHCI_SEPER_ESC_CHAR1_V  0xFF
-#define UHCI_SEPER_ESC_CHAR1_S  16
-/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: This register stores thee first char used to replace seperator char in data.*/
-#define UHCI_SEPER_ESC_CHAR0  0x000000FF
-#define UHCI_SEPER_ESC_CHAR0_M  ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
-#define UHCI_SEPER_ESC_CHAR0_V  0xFF
-#define UHCI_SEPER_ESC_CHAR0_S  8
-/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
-/*description: This register stores the seperator char  seperator char is used
- to seperate the data frame.*/
-#define UHCI_SEPER_CHAR  0x000000FF
-#define UHCI_SEPER_CHAR_M  ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
-#define UHCI_SEPER_CHAR_V  0xFF
-#define UHCI_SEPER_CHAR_S  0
-
-#define UHCI_ESC_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0xB4)
-/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
-/*description: This register stores the second char used to replace the reg_esc_seq0 in data*/
-#define UHCI_ESC_SEQ0_CHAR1  0x000000FF
-#define UHCI_ESC_SEQ0_CHAR1_M  ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
-#define UHCI_ESC_SEQ0_CHAR1_V  0xFF
-#define UHCI_ESC_SEQ0_CHAR1_S  16
-/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: This register stores the first char used to replace reg_esc_seq0 in data.*/
-#define UHCI_ESC_SEQ0_CHAR0  0x000000FF
-#define UHCI_ESC_SEQ0_CHAR0_M  ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
-#define UHCI_ESC_SEQ0_CHAR0_V  0xFF
-#define UHCI_ESC_SEQ0_CHAR0_S  8
-/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
-/*description: This register stores the first substitute char used to replace
- the seperator char.*/
-#define UHCI_ESC_SEQ0  0x000000FF
-#define UHCI_ESC_SEQ0_M  ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
-#define UHCI_ESC_SEQ0_V  0xFF
-#define UHCI_ESC_SEQ0_S  0
-
-#define UHCI_ESC_CONF2_REG(i)          (REG_UHCI_BASE(i) + 0xB8)
-/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
-/*description: This register stores the second char used to replace the reg_esc_seq1 in data.*/
-#define UHCI_ESC_SEQ1_CHAR1  0x000000FF
-#define UHCI_ESC_SEQ1_CHAR1_M  ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
-#define UHCI_ESC_SEQ1_CHAR1_V  0xFF
-#define UHCI_ESC_SEQ1_CHAR1_S  16
-/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: This register stores the first char used to replace the reg_esc_seq1 in data.*/
-#define UHCI_ESC_SEQ1_CHAR0  0x000000FF
-#define UHCI_ESC_SEQ1_CHAR0_M  ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
-#define UHCI_ESC_SEQ1_CHAR0_V  0xFF
-#define UHCI_ESC_SEQ1_CHAR0_S  8
-/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
-/*description: This register stores the flow control char to turn on the flow_control*/
-#define UHCI_ESC_SEQ1  0x000000FF
-#define UHCI_ESC_SEQ1_M  ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
-#define UHCI_ESC_SEQ1_V  0xFF
-#define UHCI_ESC_SEQ1_S  0
-
-#define UHCI_ESC_CONF3_REG(i)          (REG_UHCI_BASE(i) + 0xBC)
-/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
-/*description: This register stores  the second char used to replace the reg_esc_seq2 in data.*/
-#define UHCI_ESC_SEQ2_CHAR1  0x000000FF
-#define UHCI_ESC_SEQ2_CHAR1_M  ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
-#define UHCI_ESC_SEQ2_CHAR1_V  0xFF
-#define UHCI_ESC_SEQ2_CHAR1_S  16
-/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: This register stores the first char used to replace the reg_esc_seq2 in data.*/
-#define UHCI_ESC_SEQ2_CHAR0  0x000000FF
-#define UHCI_ESC_SEQ2_CHAR0_M  ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
-#define UHCI_ESC_SEQ2_CHAR0_V  0xFF
-#define UHCI_ESC_SEQ2_CHAR0_S  8
-/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
-/*description: This register stores the flow_control char to turn off the flow_control*/
-#define UHCI_ESC_SEQ2  0x000000FF
-#define UHCI_ESC_SEQ2_M  ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
-#define UHCI_ESC_SEQ2_V  0xFF
-#define UHCI_ESC_SEQ2_S  0
-
-#define UHCI_PKT_THRES_REG(i)          (REG_UHCI_BASE(i) + 0xC0)
-/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
-/*description: when the amount of packet payload is greater than this value
- the process of receiving data is done.*/
-#define UHCI_PKT_THRS  0x00001FFF
-#define UHCI_PKT_THRS_M  ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
-#define UHCI_PKT_THRS_V  0x1FFF
-#define UHCI_PKT_THRS_S  0
-
-#define UHCI_DATE_REG(i)          (REG_UHCI_BASE(i) + 0xFC)
-/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h16041001 ; */
-/*description: version information*/
-#define UHCI_DATE  0xFFFFFFFF
-#define UHCI_DATE_M  ((UHCI_DATE_V)<<(UHCI_DATE_S))
-#define UHCI_DATE_V  0xFFFFFFFF
-#define UHCI_DATE_S  0
-
-
-
-
-#endif /*_SOC_UHCI_REG_H_ */
-
-
diff --git a/tools/sdk/include/soc/soc/uhci_struct.h b/tools/sdk/include/soc/soc/uhci_struct.h
deleted file mode 100644
index 543af215c44..00000000000
--- a/tools/sdk/include/soc/soc/uhci_struct.h
+++ /dev/null
@@ -1,349 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UHCI_STRUCT_H_
-#define _SOC_UHCI_STRUCT_H_
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct {
-    union {
-        struct {
-            uint32_t in_rst:             1;                /*Set this bit to reset in link operations.*/
-            uint32_t out_rst:            1;                /*Set this bit to reset out link operations.*/
-            uint32_t ahbm_fifo_rst:      1;                /*Set this bit to reset dma ahb fifo.*/
-            uint32_t ahbm_rst:           1;                /*Set this bit to reset dma  ahb interface.*/
-            uint32_t in_loop_test:       1;                /*Set this bit to enable loop test for in links.*/
-            uint32_t out_loop_test:      1;                /*Set this bit to enable loop test for out links.*/
-            uint32_t out_auto_wrback:    1;                /*when in link's length is 0  go on to use the next in link automatically.*/
-            uint32_t out_no_restart_clr: 1;                /*don't use*/
-            uint32_t out_eof_mode:       1;                /*Set this bit to produce eof after DMA pops all data  clear this bit to produce eof after DMA pushes all data*/
-            uint32_t uart0_ce:           1;                /*Set this bit to use UART to transmit or receive data.*/
-            uint32_t uart1_ce:           1;                /*Set this bit to use UART1 to transmit or receive data.*/
-            uint32_t uart2_ce:           1;                /*Set this bit to use UART2 to transmit or receive data.*/
-            uint32_t outdscr_burst_en:   1;                /*Set this bit to enable DMA in links to use burst mode.*/
-            uint32_t indscr_burst_en:    1;                /*Set this bit to enable DMA out links to use burst mode.*/
-            uint32_t out_data_burst_en:  1;                /*Set this bit to enable DMA burst MODE*/
-            uint32_t mem_trans_en:       1;
-            uint32_t seper_en:           1;                /*Set this bit to use special char to separate the data frame.*/
-            uint32_t head_en:            1;                /*Set this bit to enable to use head packet  before the data frame.*/
-            uint32_t crc_rec_en:         1;                /*Set this bit to enable receiver''s ability of crc calculation  when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/
-            uint32_t uart_idle_eof_en:   1;                /*Set this bit to enable to use idle time  when the idle time after data frame is satisfied  this means the end of a data frame.*/
-            uint32_t len_eof_en:         1;                /*Set this bit to enable to use packet_len in packet head  when the received data is equal to packet_len  this means the end of a data frame.*/
-            uint32_t encode_crc_en:      1;                /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/
-            uint32_t clk_en:             1;                /*Set this bit to enable clock-gating for read or write registers.*/
-            uint32_t uart_rx_brk_eof_en: 1;                /*Set this bit to enable to use brk char as the end of a data frame.*/
-            uint32_t reserved24:         8;
-        };
-        uint32_t val;
-    } conf0;
-    union {
-        struct {
-            uint32_t rx_start:            1;               /*when a separator char has been send  it will produce uhci_rx_start_int interrupt.*/
-            uint32_t tx_start:            1;               /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/
-            uint32_t rx_hung:             1;               /*when DMA takes a lot of time to receive a data   it will produce uhci_rx_hung_int interrupt.*/
-            uint32_t tx_hung:             1;               /*when DMA takes a lot of time to read a data from RAM  it will produce uhci_tx_hung_int interrupt.*/
-            uint32_t in_done:             1;               /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/
-            uint32_t in_suc_eof:          1;               /*when a data packet has been received  it will produce uhci_in_suc_eof_int interrupt.*/
-            uint32_t in_err_eof:          1;               /*when there are some errors about eof in in link descriptor  it will produce uhci_in_err_eof_int interrupt.*/
-            uint32_t out_done:            1;               /*when a out link descriptor is completed  it will produce uhci_out_done_int interrupt.*/
-            uint32_t out_eof:             1;               /*when the current descriptor's eof bit is 1  it will produce uhci_out_eof_int interrupt.*/
-            uint32_t in_dscr_err:         1;               /*when there are some errors about the out link descriptor  it will produce uhci_in_dscr_err_int interrupt.*/
-            uint32_t out_dscr_err:        1;               /*when there are some errors about the in link descriptor  it will produce uhci_out_dscr_err_int interrupt.*/
-            uint32_t in_dscr_empty:       1;               /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/
-            uint32_t outlink_eof_err:     1;               /*when there are some errors about eof in outlink descriptor  it will produce uhci_outlink_eof_err_int interrupt.*/
-            uint32_t out_total_eof:       1;               /*When all data have been send  it will produce uhci_out_total_eof_int interrupt.*/
-            uint32_t send_s_q:            1;               /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/
-            uint32_t send_a_q:            1;               /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/
-            uint32_t dma_in_fifo_full_wm: 1;
-            uint32_t reserved17:         15;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rx_start:            1;
-            uint32_t tx_start:            1;
-            uint32_t rx_hung:             1;
-            uint32_t tx_hung:             1;
-            uint32_t in_done:             1;
-            uint32_t in_suc_eof:          1;
-            uint32_t in_err_eof:          1;
-            uint32_t out_done:            1;
-            uint32_t out_eof:             1;
-            uint32_t in_dscr_err:         1;
-            uint32_t out_dscr_err:        1;
-            uint32_t in_dscr_empty:       1;
-            uint32_t outlink_eof_err:     1;
-            uint32_t out_total_eof:       1;
-            uint32_t send_s_q:            1;
-            uint32_t send_a_q:            1;
-            uint32_t dma_in_fifo_full_wm: 1;
-            uint32_t reserved17:         15;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t rx_start:            1;
-            uint32_t tx_start:            1;
-            uint32_t rx_hung:             1;
-            uint32_t tx_hung:             1;
-            uint32_t in_done:             1;
-            uint32_t in_suc_eof:          1;
-            uint32_t in_err_eof:          1;
-            uint32_t out_done:            1;
-            uint32_t out_eof:             1;
-            uint32_t in_dscr_err:         1;
-            uint32_t out_dscr_err:        1;
-            uint32_t in_dscr_empty:       1;
-            uint32_t outlink_eof_err:     1;
-            uint32_t out_total_eof:       1;
-            uint32_t send_s_q:            1;
-            uint32_t send_a_q:            1;
-            uint32_t dma_in_fifo_full_wm: 1;
-            uint32_t reserved17:         15;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t rx_start:            1;
-            uint32_t tx_start:            1;
-            uint32_t rx_hung:             1;
-            uint32_t tx_hung:             1;
-            uint32_t in_done:             1;
-            uint32_t in_suc_eof:          1;
-            uint32_t in_err_eof:          1;
-            uint32_t out_done:            1;
-            uint32_t out_eof:             1;
-            uint32_t in_dscr_err:         1;
-            uint32_t out_dscr_err:        1;
-            uint32_t in_dscr_empty:       1;
-            uint32_t outlink_eof_err:     1;
-            uint32_t out_total_eof:       1;
-            uint32_t send_s_q:            1;
-            uint32_t send_a_q:            1;
-            uint32_t dma_in_fifo_full_wm: 1;
-            uint32_t reserved17:         15;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t full:       1;                      /*1:DMA out link descriptor's fifo is full.*/
-            uint32_t empty:      1;                      /*1:DMA in link descriptor's fifo is empty.*/
-            uint32_t reserved2: 30;
-        };
-        uint32_t val;
-    } dma_out_status;
-    union {
-        struct {
-            uint32_t fifo_wdata: 9;                      /*This is the data need to be pushed into out link descriptor's fifo.*/
-            uint32_t reserved9:  7;
-            uint32_t fifo_push:  1;                      /*Set this bit to push data in out link descriptor's fifo.*/
-            uint32_t reserved17:15;
-        };
-        uint32_t val;
-    } dma_out_push;
-    union {
-        struct {
-            uint32_t full:         1;
-            uint32_t empty:        1;
-            uint32_t reserved2:    2;
-            uint32_t rx_err_cause: 3;                    /*This register stores the errors caused in out link descriptor's data packet.*/
-            uint32_t reserved7:   25;
-        };
-        uint32_t val;
-    } dma_in_status;
-    union {
-        struct {
-            uint32_t fifo_rdata:  12;                    /*This register stores the data pop from in link descriptor's fifo.*/
-            uint32_t reserved12:   4;
-            uint32_t fifo_pop:     1;                    /*Set this bit to pop data in in link descriptor's fifo.*/
-            uint32_t reserved17:  15;
-        };
-        uint32_t val;
-    } dma_in_pop;
-    union {
-        struct {
-            uint32_t addr:         20;                   /*This register stores the least 20 bits of the first out link descriptor's address.*/
-            uint32_t reserved20:    8;
-            uint32_t stop:          1;                   /*Set this bit to stop dealing with the out link descriptors.*/
-            uint32_t start:         1;                   /*Set this bit to start dealing with the out link descriptors.*/
-            uint32_t restart:       1;                   /*Set this bit to mount on new out link descriptors*/
-            uint32_t park:          1;                   /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/
-        };
-        uint32_t val;
-    } dma_out_link;
-    union {
-        struct {
-            uint32_t addr:       20;                     /*This register stores the least 20 bits of the first in link descriptor's address.*/
-            uint32_t auto_ret:    1;                     /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/
-            uint32_t reserved21:  7;
-            uint32_t stop:        1;                     /*Set this bit to stop dealing with the in link descriptors.*/
-            uint32_t start:       1;                     /*Set this bit to start dealing with the in link descriptors.*/
-            uint32_t restart:     1;                     /*Set this bit to mount on new in link descriptors*/
-            uint32_t park:        1;                     /*1:the in link descriptor's fsm is in idle state.   0:the in link descriptor's fsm is working*/
-        };
-        uint32_t val;
-    } dma_in_link;
-    union {
-        struct {
-            uint32_t check_sum_en:          1;            /*Set this bit to enable decoder to check  check_sum in packet header.*/
-            uint32_t check_seq_en:          1;            /*Set this bit to enable decoder to check seq num in packet header.*/
-            uint32_t crc_disable:           1;            /*Set this bit to disable crc calculation.*/
-            uint32_t save_head:             1;            /*Set this bit to save packet header .*/
-            uint32_t tx_check_sum_re:       1;            /*Set this bit to enable hardware replace check_sum in packet header automatically.*/
-            uint32_t tx_ack_num_re:         1;            /*Set this bit to enable hardware replace ack num in packet header automatically.*/
-            uint32_t check_owner:           1;            /*Set this bit to check the owner bit in link descriptor.*/
-            uint32_t wait_sw_start:         1;            /*Set this bit to enable software way to add packet header.*/
-            uint32_t sw_start:              1;            /*Set this bit to start inserting the packet header.*/
-            uint32_t dma_in_fifo_full_thrs:12;            /*when data amount in link descriptor's fifo is more than this register value  it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/
-            uint32_t reserved21:           11;
-        };
-        uint32_t val;
-    } conf1;
-    uint32_t state0;                                       /**/
-    uint32_t state1;                                       /**/
-    uint32_t dma_out_eof_des_addr;                         /*This register stores the address of out link description when eof bit in this descriptor is 1.*/
-    uint32_t dma_in_suc_eof_des_addr;                      /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/
-    uint32_t dma_in_err_eof_des_addr;                      /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/
-    uint32_t dma_out_eof_bfr_des_addr;                     /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/
-    union {
-        struct {
-            uint32_t test_mode:   3;                       /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
-            uint32_t reserved3:   1;
-            uint32_t test_addr:   2;                       /*The two bits represent ahb bus address bit[20:19]*/
-            uint32_t reserved6:  26;
-        };
-        uint32_t val;
-    } ahb_test;
-    uint32_t dma_in_dscr;                                  /*The content of current in link descriptor's third dword*/
-    uint32_t dma_in_dscr_bf0;                              /*The content of current in link descriptor's first dword*/
-    uint32_t dma_in_dscr_bf1;                              /*The content of current in link descriptor's second dword*/
-    uint32_t dma_out_dscr;                                 /*The content of current out link descriptor's third dword*/
-    uint32_t dma_out_dscr_bf0;                             /*The content of current out link descriptor's first dword*/
-    uint32_t dma_out_dscr_bf1;                             /*The content of current out link descriptor's second dword*/
-    union {
-        struct {
-            uint32_t tx_c0_esc_en: 1;                      /*Set this bit to enable  0xc0 char decode when DMA receives data.*/
-            uint32_t tx_db_esc_en: 1;                      /*Set this bit to enable  0xdb char decode when DMA receives data.*/
-            uint32_t tx_11_esc_en: 1;                      /*Set this bit to enable  flow control char 0x11 decode when DMA receives data.*/
-            uint32_t tx_13_esc_en: 1;                      /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/
-            uint32_t rx_c0_esc_en: 1;                      /*Set this bit to enable  0xc0 char replace when DMA sends data.*/
-            uint32_t rx_db_esc_en: 1;                      /*Set this bit to enable  0xdb char replace when DMA sends data.*/
-            uint32_t rx_11_esc_en: 1;                      /*Set this bit to enable  flow control char 0x11 replace when DMA sends data.*/
-            uint32_t rx_13_esc_en: 1;                      /*Set this bit to enable  flow control char 0x13 replace when DMA sends data.*/
-            uint32_t reserved8:   24;
-        };
-        uint32_t val;
-    } escape_conf;
-    union {
-        struct {
-            uint32_t txfifo_timeout:       8;              /*This register stores the timeout value.when DMA takes more time than this register value to receive a data  it will produce  uhci_tx_hung_int interrupt.*/
-            uint32_t txfifo_timeout_shift: 3;              /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/
-            uint32_t txfifo_timeout_ena:   1;              /*The enable bit for tx fifo receive data  timeout*/
-            uint32_t rxfifo_timeout:       8;              /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM  it will produce  uhci_rx_hung_int interrupt.*/
-            uint32_t rxfifo_timeout_shift: 3;              /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/
-            uint32_t rxfifo_timeout_ena:   1;              /*This is the enable bit for DMA  send data timeout*/
-            uint32_t reserved24:           8;
-        };
-        uint32_t val;
-    } hung_conf;
-    uint32_t ack_num;                                      /**/
-    uint32_t rx_head;                                      /*This register stores the packet header received by DMA*/
-    union {
-        struct {
-            uint32_t single_send_num: 3;                   /*The bits are used to choose which short packet*/
-            uint32_t single_send_en:  1;                   /*Set this bit to enable  send a short packet*/
-            uint32_t always_send_num: 3;                   /*The bits are used to choose which short packet*/
-            uint32_t always_send_en:  1;                   /*Set this bit to enable continuously send the same short packet*/
-            uint32_t reserved8:      24;
-        };
-        uint32_t val;
-    } quick_sent;
-    struct{
-        uint32_t w_data[2];                                /*This register stores the content of short packet's dword*/
-    } q_data[7];
-    union {
-        struct {
-            uint32_t seper_char:      8;                   /*This register stores the separator char  separator char is used to separate the data frame.*/
-            uint32_t seper_esc_char0: 8;                   /*This register stores the first char used to replace separator char in data.*/
-            uint32_t seper_esc_char1: 8;                   /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/
-            uint32_t reserved24:      8;
-        };
-        uint32_t val;
-    } esc_conf0;
-    union {
-        struct {
-            uint32_t seq0:       8;                        /*This register stores the first substitute char used to replace the separate char.*/
-            uint32_t seq0_char0: 8;                        /*This register stores the first char used to replace reg_esc_seq0 in data.*/
-            uint32_t seq0_char1: 8;                        /*This register stores the second char used to replace the reg_esc_seq0 in data*/
-            uint32_t reserved24: 8;
-        };
-        uint32_t val;
-    } esc_conf1;
-    union {
-        struct {
-            uint32_t seq1:       8;                        /*This register stores the flow control char to turn on the flow_control*/
-            uint32_t seq1_char0: 8;                        /*This register stores the first char used to replace the reg_esc_seq1 in data.*/
-            uint32_t seq1_char1: 8;                        /*This register stores the second char used to replace the reg_esc_seq1 in data.*/
-            uint32_t reserved24: 8;
-        };
-        uint32_t val;
-    } esc_conf2;
-    union {
-        struct {
-            uint32_t seq2:       8;                        /*This register stores the flow_control char to turn off the flow_control*/
-            uint32_t seq2_char0: 8;                        /*This register stores the first char used to replace the reg_esc_seq2 in data.*/
-            uint32_t seq2_char1: 8;                        /*This register stores  the second char used to replace the reg_esc_seq2 in data.*/
-            uint32_t reserved24: 8;
-        };
-        uint32_t val;
-    } esc_conf3;
-    union {
-        struct {
-            uint32_t thrs:      13;                        /*when the amount of packet payload is larger than this value the process of receiving data is done.*/
-            uint32_t reserved13:19;
-        };
-        uint32_t val;
-    } pkt_thres;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t date;                                         /*version information*/
-} uhci_dev_t;
-extern uhci_dev_t UHCI0;
-extern uhci_dev_t UHCI1;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_UHCI_STRUCT_H_ */
diff --git a/tools/sdk/include/soc/soc/wdev_reg.h b/tools/sdk/include/soc/soc/wdev_reg.h
deleted file mode 100644
index f3217cb0d6f..00000000000
--- a/tools/sdk/include/soc/soc/wdev_reg.h
+++ /dev/null
@@ -1,20 +0,0 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "soc.h"
-
-/* Hardware random number generator register */ 
-#define WDEV_RND_REG 0x60035144
diff --git a/tools/sdk/include/spi_flash/esp_partition.h b/tools/sdk/include/spi_flash/esp_partition.h
deleted file mode 100644
index 6537967eb7e..00000000000
--- a/tools/sdk/include/spi_flash/esp_partition.h
+++ /dev/null
@@ -1,328 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_PARTITION_H__
-#define __ESP_PARTITION_H__
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include "esp_err.h"
-#include "esp_spi_flash.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @file esp_partition.h
- * @brief Partition APIs
- */
-
-
-/**
- * @brief Partition type
- * @note Keep this enum in sync with PartitionDefinition class gen_esp32part.py
- */
-typedef enum {
-    ESP_PARTITION_TYPE_APP = 0x00,       //!< Application partition type
-    ESP_PARTITION_TYPE_DATA = 0x01,      //!< Data partition type
-} esp_partition_type_t;
-
-/**
- * @brief Partition subtype
- * @note Keep this enum in sync with PartitionDefinition class gen_esp32part.py
- */
-typedef enum {
-    ESP_PARTITION_SUBTYPE_APP_FACTORY = 0x00,                                 //!< Factory application partition
-    ESP_PARTITION_SUBTYPE_APP_OTA_MIN = 0x10,                                 //!< Base for OTA partition subtypes
-    ESP_PARTITION_SUBTYPE_APP_OTA_0 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 0,  //!< OTA partition 0
-    ESP_PARTITION_SUBTYPE_APP_OTA_1 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 1,  //!< OTA partition 1
-    ESP_PARTITION_SUBTYPE_APP_OTA_2 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 2,  //!< OTA partition 2
-    ESP_PARTITION_SUBTYPE_APP_OTA_3 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 3,  //!< OTA partition 3
-    ESP_PARTITION_SUBTYPE_APP_OTA_4 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 4,  //!< OTA partition 4
-    ESP_PARTITION_SUBTYPE_APP_OTA_5 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 5,  //!< OTA partition 5
-    ESP_PARTITION_SUBTYPE_APP_OTA_6 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 6,  //!< OTA partition 6
-    ESP_PARTITION_SUBTYPE_APP_OTA_7 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 7,  //!< OTA partition 7
-    ESP_PARTITION_SUBTYPE_APP_OTA_8 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 8,  //!< OTA partition 8
-    ESP_PARTITION_SUBTYPE_APP_OTA_9 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 9,  //!< OTA partition 9
-    ESP_PARTITION_SUBTYPE_APP_OTA_10 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 10,//!< OTA partition 10
-    ESP_PARTITION_SUBTYPE_APP_OTA_11 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 11,//!< OTA partition 11
-    ESP_PARTITION_SUBTYPE_APP_OTA_12 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 12,//!< OTA partition 12
-    ESP_PARTITION_SUBTYPE_APP_OTA_13 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 13,//!< OTA partition 13
-    ESP_PARTITION_SUBTYPE_APP_OTA_14 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 14,//!< OTA partition 14
-    ESP_PARTITION_SUBTYPE_APP_OTA_15 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 15,//!< OTA partition 15
-    ESP_PARTITION_SUBTYPE_APP_OTA_MAX = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 16,//!< Max subtype of OTA partition
-    ESP_PARTITION_SUBTYPE_APP_TEST = 0x20,                                    //!< Test application partition
-
-    ESP_PARTITION_SUBTYPE_DATA_OTA = 0x00,                                    //!< OTA selection partition
-    ESP_PARTITION_SUBTYPE_DATA_PHY = 0x01,                                    //!< PHY init data partition
-    ESP_PARTITION_SUBTYPE_DATA_NVS = 0x02,                                    //!< NVS partition
-    ESP_PARTITION_SUBTYPE_DATA_COREDUMP = 0x03,                               //!< COREDUMP partition
-    ESP_PARTITION_SUBTYPE_DATA_NVS_KEYS = 0x04,                               //!< Partition for NVS keys
-    ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM = 0x05,                               //!< Partition for emulate eFuse bits
-
-    ESP_PARTITION_SUBTYPE_DATA_ESPHTTPD = 0x80,                               //!< ESPHTTPD partition
-    ESP_PARTITION_SUBTYPE_DATA_FAT = 0x81,                                    //!< FAT partition
-    ESP_PARTITION_SUBTYPE_DATA_SPIFFS = 0x82,                                 //!< SPIFFS partition
-
-    ESP_PARTITION_SUBTYPE_ANY = 0xff,                                         //!< Used to search for partitions with any subtype
-} esp_partition_subtype_t;
-
-/**
- * @brief Convenience macro to get esp_partition_subtype_t value for the i-th OTA partition
- */
-#define ESP_PARTITION_SUBTYPE_OTA(i) ((esp_partition_subtype_t)(ESP_PARTITION_SUBTYPE_APP_OTA_MIN + ((i) & 0xf)))
-
-/**
- * @brief Opaque partition iterator type
- */
-typedef struct esp_partition_iterator_opaque_* esp_partition_iterator_t;
-
-/**
- * @brief partition information structure
- *
- * This is not the format in flash, that format is esp_partition_info_t.
- *
- * However, this is the format used by this API.
- */
-typedef struct {
-    esp_partition_type_t type;          /*!< partition type (app/data) */
-    esp_partition_subtype_t subtype;    /*!< partition subtype */
-    uint32_t address;                   /*!< starting address of the partition in flash */
-    uint32_t size;                      /*!< size of the partition, in bytes */
-    char label[17];                     /*!< partition label, zero-terminated ASCII string */
-    bool encrypted;                     /*!< flag is set to true if partition is encrypted */
-} esp_partition_t;
-
-/**
- * @brief Find partition based on one or more parameters
- *
- * @param type Partition type, one of esp_partition_type_t values
- * @param subtype Partition subtype, one of esp_partition_subtype_t values.
- *                To find all partitions of given type, use
- *                ESP_PARTITION_SUBTYPE_ANY.
- * @param label (optional) Partition label. Set this value if looking
- *             for partition with a specific name. Pass NULL otherwise.
- *
- * @return iterator which can be used to enumerate all the partitions found,
- *         or NULL if no partitions were found.
- *         Iterator obtained through this function has to be released
- *         using esp_partition_iterator_release when not used any more.
- */
-esp_partition_iterator_t esp_partition_find(esp_partition_type_t type, esp_partition_subtype_t subtype, const char* label);
-
-/**
- * @brief Find first partition based on one or more parameters
- *
- * @param type Partition type, one of esp_partition_type_t values
- * @param subtype Partition subtype, one of esp_partition_subtype_t values.
- *                To find all partitions of given type, use
- *                ESP_PARTITION_SUBTYPE_ANY.
- * @param label (optional) Partition label. Set this value if looking
- *             for partition with a specific name. Pass NULL otherwise.
- *
- * @return pointer to esp_partition_t structure, or NULL if no partition is found.
- *         This pointer is valid for the lifetime of the application.
- */
-const esp_partition_t* esp_partition_find_first(esp_partition_type_t type, esp_partition_subtype_t subtype, const char* label);
-
-/**
- * @brief Get esp_partition_t structure for given partition
- *
- * @param iterator  Iterator obtained using esp_partition_find. Must be non-NULL.
- *
- * @return pointer to esp_partition_t structure. This pointer is valid for the lifetime
- *         of the application.
- */
-const esp_partition_t* esp_partition_get(esp_partition_iterator_t iterator);
-
-/**
- * @brief Move partition iterator to the next partition found
- *
- * Any copies of the iterator will be invalid after this call.
- *
- * @param iterator Iterator obtained using esp_partition_find. Must be non-NULL.
- *
- * @return NULL if no partition was found, valid esp_partition_iterator_t otherwise.
- */
-esp_partition_iterator_t esp_partition_next(esp_partition_iterator_t iterator);
-
-/**
- * @brief Release partition iterator
- *
- * @param iterator Iterator obtained using esp_partition_find. Must be non-NULL.
- *
- */
-void esp_partition_iterator_release(esp_partition_iterator_t iterator);
-
-/**
- * @brief Verify partition data
- *
- * Given a pointer to partition data, verify this partition exists in the partition table (all fields match.)
- *
- * This function is also useful to take partition data which may be in a RAM buffer and convert it to a pointer to the
- * permanent partition data stored in flash.
- *
- * Pointers returned from this function can be compared directly to the address of any pointer returned from
- * esp_partition_get(), as a test for equality.
- *
- * @param partition Pointer to partition data to verify. Must be non-NULL. All fields of this structure must match the
- * partition table entry in flash for this function to return a successful match.
- *
- * @return
- * - If partition not found, returns NULL.
- * - If found, returns a pointer to the esp_partition_t structure in flash. This pointer is always valid for the lifetime of the application.
- */
-const esp_partition_t *esp_partition_verify(const esp_partition_t *partition);
-
-/**
- * @brief Read data from the partition
- *
- * @param partition Pointer to partition structure obtained using
- *                  esp_partition_find_first or esp_partition_get.
- *                  Must be non-NULL.
- * @param dst Pointer to the buffer where data should be stored.
- *            Pointer must be non-NULL and buffer must be at least 'size' bytes long.
- * @param src_offset Address of the data to be read, relative to the
- *                   beginning of the partition.
- * @param size Size of data to be read, in bytes.
- *
- * @return ESP_OK, if data was read successfully;
- *         ESP_ERR_INVALID_ARG, if src_offset exceeds partition size;
- *         ESP_ERR_INVALID_SIZE, if read would go out of bounds of the partition;
- *         or one of error codes from lower-level flash driver.
- */
-esp_err_t esp_partition_read(const esp_partition_t* partition,
-                             size_t src_offset, void* dst, size_t size);
-
-/**
- * @brief Write data to the partition
- *
- * Before writing data to flash, corresponding region of flash needs to be erased.
- * This can be done using esp_partition_erase_range function.
- *
- * Partitions marked with an encryption flag will automatically be
- * written via the spi_flash_write_encrypted() function. If writing to
- * an encrypted partition, all write offsets and lengths must be
- * multiples of 16 bytes. See the spi_flash_write_encrypted() function
- * for more details. Unencrypted partitions do not have this
- * restriction.
- *
- * @param partition Pointer to partition structure obtained using
- *                  esp_partition_find_first or esp_partition_get.
- *                  Must be non-NULL.
- * @param dst_offset Address where the data should be written, relative to the
- *                   beginning of the partition.
- * @param src Pointer to the source buffer.  Pointer must be non-NULL and
- *            buffer must be at least 'size' bytes long.
- * @param size Size of data to be written, in bytes.
- *
- * @note Prior to writing to flash memory, make sure it has been erased with
- *       esp_partition_erase_range call.
- *
- * @return ESP_OK, if data was written successfully;
- *         ESP_ERR_INVALID_ARG, if dst_offset exceeds partition size;
- *         ESP_ERR_INVALID_SIZE, if write would go out of bounds of the partition;
- *         or one of error codes from lower-level flash driver.
- */
-esp_err_t esp_partition_write(const esp_partition_t* partition,
-                             size_t dst_offset, const void* src, size_t size);
-
-/**
- * @brief Erase part of the partition
- *
- * @param partition Pointer to partition structure obtained using
- *                  esp_partition_find_first or esp_partition_get.
- *                  Must be non-NULL.
- * @param start_addr Address where erase operation should start. Must be aligned
- *                   to 4 kilobytes.
- * @param size Size of the range which should be erased, in bytes.
- *                   Must be divisible by 4 kilobytes.
- *
- * @return ESP_OK, if the range was erased successfully;
- *         ESP_ERR_INVALID_ARG, if iterator or dst are NULL;
- *         ESP_ERR_INVALID_SIZE, if erase would go out of bounds of the partition;
- *         or one of error codes from lower-level flash driver.
- */
-esp_err_t esp_partition_erase_range(const esp_partition_t* partition,
-                                    uint32_t start_addr, uint32_t size);
-
-/**
- * @brief Configure MMU to map partition into data memory
- *
- * Unlike spi_flash_mmap function, which requires a 64kB aligned base address,
- * this function doesn't impose such a requirement.
- * If offset results in a flash address which is not aligned to 64kB boundary,
- * address will be rounded to the lower 64kB boundary, so that mapped region
- * includes requested range.
- * Pointer returned via out_ptr argument will be adjusted to point to the
- * requested offset (not necessarily to the beginning of mmap-ed region).
- *
- * To release mapped memory, pass handle returned via out_handle argument to
- * spi_flash_munmap function.
- *
- * @param partition Pointer to partition structure obtained using
- *                  esp_partition_find_first or esp_partition_get.
- *                  Must be non-NULL.
- * @param offset Offset from the beginning of partition where mapping should start.
- * @param size Size of the area to be mapped.
- * @param memory  Memory space where the region should be mapped
- * @param out_ptr  Output, pointer to the mapped memory region
- * @param out_handle  Output, handle which should be used for spi_flash_munmap call
- *
- * @return ESP_OK, if successful
- */
-esp_err_t esp_partition_mmap(const esp_partition_t* partition, uint32_t offset, uint32_t size,
-                             spi_flash_mmap_memory_t memory,
-                             const void** out_ptr, spi_flash_mmap_handle_t* out_handle);
-
-/**
- * @brief Get SHA-256 digest for required partition.
- *
- * For apps with SHA-256 appended to the app image, the result is the appended SHA-256 value for the app image content.
- * The hash is verified before returning, if app content is invalid then the function returns ESP_ERR_IMAGE_INVALID.
- * For apps without SHA-256 appended to the image, the result is the SHA-256 of all bytes in the app image.
- * For other partition types, the result is the SHA-256 of the entire partition.
- *
- * @param[in]  partition    Pointer to info for partition containing app or data. (fields: address, size and type, are required to be filled).
- * @param[out] sha_256      Returned SHA-256 digest for a given partition.
- *
- * @return
- *          - ESP_OK: In case of successful operation.
- *          - ESP_ERR_INVALID_ARG: The size was 0 or the sha_256 was NULL.
- *          - ESP_ERR_NO_MEM: Cannot allocate memory for sha256 operation.
- *          - ESP_ERR_IMAGE_INVALID: App partition doesn't contain a valid app image.
- *          - ESP_FAIL: An allocation error occurred.
- */
-esp_err_t esp_partition_get_sha256(const esp_partition_t *partition, uint8_t *sha_256);
-
-/**
- * @brief Check for the identity of two partitions by SHA-256 digest.
- *
- * @param[in] partition_1 Pointer to info for partition 1 containing app or data. (fields: address, size and type, are required to be filled).
- * @param[in] partition_2 Pointer to info for partition 2 containing app or data. (fields: address, size and type, are required to be filled).
- *
- * @return
- *         - True:  In case of the two firmware is equal.
- *         - False: Otherwise
- */
-bool esp_partition_check_identity(const esp_partition_t *partition_1, const esp_partition_t *partition_2);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __ESP_PARTITION_H__ */
diff --git a/tools/sdk/include/spi_flash/esp_spi_flash.h b/tools/sdk/include/spi_flash/esp_spi_flash.h
deleted file mode 100644
index ddcbbf62014..00000000000
--- a/tools/sdk/include/spi_flash/esp_spi_flash.h
+++ /dev/null
@@ -1,441 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef ESP_SPI_FLASH_H
-#define ESP_SPI_FLASH_H
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-#include "esp_err.h"
-#include "sdkconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ESP_ERR_FLASH_BASE       0x10010
-#define ESP_ERR_FLASH_OP_FAIL    (ESP_ERR_FLASH_BASE + 1)
-#define ESP_ERR_FLASH_OP_TIMEOUT (ESP_ERR_FLASH_BASE + 2)
-
-#define SPI_FLASH_SEC_SIZE  4096    /**< SPI Flash sector size */
-
-#define SPI_FLASH_MMU_PAGE_SIZE 0x10000 /**< Flash cache MMU mapping page size */
-
-/**
- * @brief  Initialize SPI flash access driver
- *
- *  This function must be called exactly once, before any other 
- *  spi_flash_* functions are called.
- *  Currently this function is called from startup code. There is
- *  no need to call it from application code.
- *
- */
-void spi_flash_init();
-
-/**
- * @brief  Get flash chip size, as set in binary image header
- *
- * @note This value does not necessarily match real flash size.
- *
- * @return size of flash chip, in bytes
- */
-size_t spi_flash_get_chip_size();
-
-/**
- * @brief  Erase the Flash sector.
- *
- * @param  sector  Sector number, the count starts at sector 0, 4KB per sector.
- *
- * @return esp_err_t
- */
-esp_err_t spi_flash_erase_sector(size_t sector);
-
-/**
- * @brief  Erase a range of flash sectors
- *
- * @param  start_address  Address where erase operation has to start.
- *                                  Must be 4kB-aligned
- * @param  size  Size of erased range, in bytes. Must be divisible by 4kB.
- *
- * @return esp_err_t
- */
-esp_err_t spi_flash_erase_range(size_t start_address, size_t size);
-
-
-/**
- * @brief  Write data to Flash.
- *
- * @note For fastest write performance, write a 4 byte aligned size at a
- * 4 byte aligned offset in flash from a source buffer in DRAM. Varying any of
- * these parameters will still work, but will be slower due to buffering.
- *
- * @note Writing more than 8KB at a time will be split into multiple
- * write operations to avoid disrupting other tasks in the system.
- *
- * @param  dest_addr Destination address in Flash.
- * @param  src       Pointer to the source buffer.
- * @param  size      Length of data, in bytes.
- *
- * @return esp_err_t
- */
-esp_err_t spi_flash_write(size_t dest_addr, const void *src, size_t size);
-
-
-/**
- * @brief  Write data encrypted to Flash.
- *
- * @note Flash encryption must be enabled for this function to work.
- *
- * @note Flash encryption must be enabled when calling this function.
- * If flash encryption is disabled, the function returns
- * ESP_ERR_INVALID_STATE.  Use esp_flash_encryption_enabled()
- * function to determine if flash encryption is enabled.
- *
- * @note Both dest_addr and size must be multiples of 16 bytes. For
- * absolute best performance, both dest_addr and size arguments should
- * be multiples of 32 bytes.
- *
- * @param  dest_addr Destination address in Flash. Must be a multiple of 16 bytes.
- * @param  src       Pointer to the source buffer.
- * @param  size      Length of data, in bytes. Must be a multiple of 16 bytes.
- *
- * @return esp_err_t
- */
-esp_err_t spi_flash_write_encrypted(size_t dest_addr, const void *src, size_t size);
-
-/**
- * @brief  Read data from Flash.
- *
- * @note For fastest read performance, all parameters should be
- * 4 byte aligned. If source address and read size are not 4 byte
- * aligned, read may be split into multiple flash operations. If
- * destination buffer is not 4 byte aligned, a temporary buffer will
- * be allocated on the stack.
- *
- * @note Reading more than 16KB of data at a time will be split
- * into multiple reads to avoid disruption to other tasks in the
- * system. Consider using spi_flash_mmap() to read large amounts
- * of data.
- *
- * @param  src_addr source address of the data in Flash.
- * @param  dest     pointer to the destination buffer
- * @param  size     length of data
- *
- *
- * @return esp_err_t
- */
-esp_err_t spi_flash_read(size_t src_addr, void *dest, size_t size);
-
-
-/**
- * @brief  Read data from Encrypted Flash.
- *
- * If flash encryption is enabled, this function will transparently decrypt data as it is read.
- * If flash encryption is not enabled, this function behaves the same as spi_flash_read().
- *
- * See esp_flash_encryption_enabled() for a function to check if flash encryption is enabled.
- *
- * @param  src   source address of the data in Flash.
- * @param  dest  pointer to the destination buffer
- * @param  size  length of data
- *
- * @return esp_err_t
- */
-esp_err_t spi_flash_read_encrypted(size_t src, void *dest, size_t size);
-
-/**
- * @brief Enumeration which specifies memory space requested in an mmap call
- */
-typedef enum {
-    SPI_FLASH_MMAP_DATA,    /**< map to data memory (Vaddr0), allows byte-aligned access, 4 MB total */
-    SPI_FLASH_MMAP_INST,    /**< map to instruction memory (Vaddr1-3), allows only 4-byte-aligned access, 11 MB total */
-} spi_flash_mmap_memory_t;
-
-/**
- * @brief Opaque handle for memory region obtained from spi_flash_mmap.
- */
-typedef uint32_t spi_flash_mmap_handle_t;
-
-/**
- * @brief Map region of flash memory into data or instruction address space
- *
- * This function allocates sufficient number of 64kB MMU pages and configures
- * them to map the requested region of flash memory into the address space.
- * It may reuse MMU pages which already provide the required mapping.
- *
- * As with any allocator, if mmap/munmap are heavily used then the address space
- * may become fragmented. To troubleshoot issues with page allocation, use
- * spi_flash_mmap_dump() function.
- *
- * @param src_addr  Physical address in flash where requested region starts.
- *                  This address *must* be aligned to 64kB boundary
- *                  (SPI_FLASH_MMU_PAGE_SIZE)
- * @param size  Size of region to be mapped. This size will be rounded
- *              up to a 64kB boundary
- * @param memory  Address space where the region should be mapped (data or instruction)
- * @param[out] out_ptr  Output, pointer to the mapped memory region
- * @param[out] out_handle  Output, handle which should be used for spi_flash_munmap call
- *
- * @return  ESP_OK on success, ESP_ERR_NO_MEM if pages can not be allocated
- */
-esp_err_t spi_flash_mmap(size_t src_addr, size_t size, spi_flash_mmap_memory_t memory,
-                         const void** out_ptr, spi_flash_mmap_handle_t* out_handle);
-
-/**
- * @brief Map sequences of pages of flash memory into data or instruction address space
- *
- * This function allocates sufficient number of 64kB MMU pages and configures
- * them to map the indicated pages of flash memory contiguously into address space.
- * In this respect, it works in a similar way as spi_flash_mmap() but it allows mapping
- * a (maybe non-contiguous) set of pages into a contiguous region of memory.
- *
- * @param pages An array of numbers indicating the 64kB pages in flash to be mapped
- *              contiguously into memory. These indicate the indexes of the 64kB pages,
- *              not the byte-size addresses as used in other functions.
- *              Array must be located in internal memory.
- * @param page_count  Number of entries in the pages array
- * @param memory  Address space where the region should be mapped (instruction or data)
- * @param[out] out_ptr  Output, pointer to the mapped memory region
- * @param[out] out_handle  Output, handle which should be used for spi_flash_munmap call
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NO_MEM if pages can not be allocated
- *      - ESP_ERR_INVALID_ARG if pagecount is zero or pages array is not in
- *        internal memory
- */
-esp_err_t spi_flash_mmap_pages(const int *pages, size_t page_count, spi_flash_mmap_memory_t memory,
-                         const void** out_ptr, spi_flash_mmap_handle_t* out_handle);
-
-
-/**
- * @brief Release region previously obtained using spi_flash_mmap
- *
- * @note Calling this function will not necessarily unmap memory region.
- *       Region will only be unmapped when there are no other handles which
- *       reference this region. In case of partially overlapping regions
- *       it is possible that memory will be unmapped partially.
- *
- * @param handle  Handle obtained from spi_flash_mmap
- */
-void spi_flash_munmap(spi_flash_mmap_handle_t handle);
-
-/**
- * @brief Display information about mapped regions
- *
- * This function lists handles obtained using spi_flash_mmap, along with range
- * of pages allocated to each handle. It also lists all non-zero entries of
- * MMU table and corresponding reference counts.
- */
-void spi_flash_mmap_dump();
-
-/**
- * @brief get free pages number which can be mmap
- *
- * This function will return number of free pages available in mmu table. This could be useful
- * before calling actual spi_flash_mmap (maps flash range to DCache or ICache memory) to check
- * if there is sufficient space available for mapping.
- *
- * @param memory memory type of MMU table free page
- *
- * @return number of free pages which can be mmaped
- */
-uint32_t spi_flash_mmap_get_free_pages(spi_flash_mmap_memory_t memory);
-
-
-#define SPI_FLASH_CACHE2PHYS_FAIL UINT32_MAX /*<! Result from spi_flash_cache2phys() if flash cache address is invalid */
-
-/**
- * @brief Given a memory address where flash is mapped, return the corresponding physical flash offset.
- *
- * Cache address does not have have been assigned via spi_flash_mmap(), any address in memory mapped flash space can be looked up.
- *
- * @param cached Pointer to flashed cached memory.
- *
- * @return
- * - SPI_FLASH_CACHE2PHYS_FAIL If cache address is outside flash cache region, or the address is not mapped.
- * - Otherwise, returns physical offset in flash
- */
-size_t spi_flash_cache2phys(const void *cached);
-
-/** @brief Given a physical offset in flash, return the address where it is mapped in the memory space.
- *
- * Physical address does not have to have been assigned via spi_flash_mmap(), any address in flash can be looked up.
- *
- * @note Only the first matching cache address is returned. If MMU flash cache table is configured so multiple entries
- * point to the same physical address, there may be more than one cache address corresponding to that physical
- * address. It is also possible for a single physical address to be mapped to both the IROM and DROM regions.
- *
- * @note This function doesn't impose any alignment constraints, but if memory argument is SPI_FLASH_MMAP_INST and
- * phys_offs is not 4-byte aligned, then reading from the returned pointer will result in a crash.
- *
- * @param phys_offs Physical offset in flash memory to look up.
- * @param memory Address space type to look up a flash cache address mapping for (instruction or data)
- *
- * @return
- * - NULL if the physical address is invalid or not mapped to flash cache of the specified memory type.
- * - Cached memory address (in IROM or DROM space) corresponding to phys_offs.
- */
-const void *spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memory_t memory);
-
-/** @brief Check at runtime if flash cache is enabled on both CPUs
- *
- * @return true if both CPUs have flash cache enabled, false otherwise.
- */
-bool spi_flash_cache_enabled();
-
-/**
- * @brief SPI flash critical section enter function.
- *
- */
-typedef void (*spi_flash_guard_start_func_t)(void);
-/**
- * @brief SPI flash critical section exit function.
- */
-typedef void (*spi_flash_guard_end_func_t)(void);
-/**
- * @brief SPI flash operation lock function.
- */
-typedef void (*spi_flash_op_lock_func_t)(void);
-/**
- * @brief SPI flash operation unlock function.
- */
-typedef void (*spi_flash_op_unlock_func_t)(void);
-/**
- * @brief Function to protect SPI flash critical regions corruption.
- */
-typedef bool (*spi_flash_is_safe_write_address_t)(size_t addr, size_t size);
-/**
- * @brief Function to yield to the OS during erase operation.
- */
-typedef void (*spi_flash_os_yield_t)(void);
-
-/**
- * Structure holding SPI flash access critical sections management functions.
- *
- * Flash API uses two types of flash access management functions:
- * 1) Functions which prepare/restore flash cache and interrupts before calling
- *    appropriate ROM functions (SPIWrite, SPIRead and SPIEraseBlock):
- *   - 'start' function should disables flash cache and non-IRAM interrupts and
- *      is invoked before the call to one of ROM function above.
- *   - 'end' function should restore state of flash cache and non-IRAM interrupts and
- *      is invoked after the call to one of ROM function above.
- *    These two functions are not recursive.
- * 2) Functions which synchronizes access to internal data used by flash API.
- *    This functions are mostly intended to synchronize access to flash API internal data
- *    in multithreaded environment and use OS primitives:
- *   - 'op_lock' locks access to flash API internal data.
- *   - 'op_unlock' unlocks access to flash API internal data.
- *   These two functions are recursive and can be used around the outside of multiple calls to
- *   'start' & 'end', in order to create atomic multi-part flash operations.
- * 3) When CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is disabled, flash writing/erasing
- *    API checks for addresses provided by user to avoid corruption of critical flash regions
- *    (bootloader, partition table, running application etc.).
- *
- * Different versions of the guarding functions should be used depending on the context of
- * execution (with or without functional OS). In normal conditions when flash API is called
- * from task the functions use OS primitives. When there is no OS at all or when
- * it is not guaranteed that OS is functional (accessing flash from exception handler) these
- * functions cannot use OS primitives or even does not need them (multithreaded access is not possible).
- *
- * @note Structure and corresponding guard functions should not reside in flash.
- *       For example structure can be placed in DRAM and functions in IRAM sections.
- */
-typedef struct {
-    spi_flash_guard_start_func_t        start;      /**< critical section start function. */
-    spi_flash_guard_end_func_t          end;        /**< critical section end function. */
-    spi_flash_op_lock_func_t            op_lock;    /**< flash access API lock function.*/
-    spi_flash_op_unlock_func_t          op_unlock;  /**< flash access API unlock function.*/
-#if !CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED
-    spi_flash_is_safe_write_address_t   is_safe_write_address; /**< checks flash write addresses.*/
-#endif
-    spi_flash_os_yield_t                yield;      /**< yield to the OS during flash erase */
-} spi_flash_guard_funcs_t;
-
-/**
- * @brief  Sets guard functions to access flash.
- *
- * @note Pointed structure and corresponding guard functions should not reside in flash.
- *       For example structure can be placed in DRAM and functions in IRAM sections.
- *
- * @param funcs pointer to structure holding flash access guard functions.
- */
-void spi_flash_guard_set(const spi_flash_guard_funcs_t* funcs);
-
-/**
- * @brief Get the guard functions used for flash access
- *
- * @return The guard functions that were set via spi_flash_guard_set(). These functions
- * can be called if implementing custom low-level SPI flash operations.
- */
-const spi_flash_guard_funcs_t *spi_flash_guard_get();
-
-/**
- * @brief Default OS-aware flash access guard functions
- */
-extern const spi_flash_guard_funcs_t g_flash_guard_default_ops;
-
-/**
- * @brief Non-OS flash access guard functions
- *
- * @note This version of flash guard functions is to be used when no OS is present or from panic handler.
- *       It does not use any OS primitives and IPC and implies that only calling CPU is active.
- */
-extern const spi_flash_guard_funcs_t g_flash_guard_no_os_ops;
-
-#if CONFIG_SPI_FLASH_ENABLE_COUNTERS
-
-/**
- * Structure holding statistics for one type of operation
- */
-typedef struct {
-    uint32_t count;     // number of times operation was executed
-    uint32_t time;      // total time taken, in microseconds
-    uint32_t bytes;     // total number of bytes
-} spi_flash_counter_t;
-
-typedef struct {
-    spi_flash_counter_t read;
-    spi_flash_counter_t write;
-    spi_flash_counter_t erase;
-} spi_flash_counters_t;
-
-/**
- * @brief  Reset SPI flash operation counters
- */
-void spi_flash_reset_counters();
-
-/**
- * @brief  Print SPI flash operation counters
- */
-void spi_flash_dump_counters();
-
-/**
- * @brief  Return current SPI flash operation counters
- *
- * @return  pointer to the spi_flash_counters_t structure holding values
- *          of the operation counters
- */
-const spi_flash_counters_t* spi_flash_get_counters();
-
-#endif //CONFIG_SPI_FLASH_ENABLE_COUNTERS
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ESP_SPI_FLASH_H */
-
diff --git a/tools/sdk/include/spiffs/esp_spiffs.h b/tools/sdk/include/spiffs/esp_spiffs.h
deleted file mode 100644
index ae1b9ad4306..00000000000
--- a/tools/sdk/include/spiffs/esp_spiffs.h
+++ /dev/null
@@ -1,102 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_SPIFFS_H_
-#define _ESP_SPIFFS_H_
-
-#include <stdbool.h>
-#include "esp_err.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Configuration structure for esp_vfs_spiffs_register
- */
-typedef struct {
-        const char* base_path;          /*!< File path prefix associated with the filesystem. */
-        const char* partition_label;    /*!< Optional, label of SPIFFS partition to use. If set to NULL, first partition with subtype=spiffs will be used. */
-        size_t max_files;               /*!< Maximum files that could be open at the same time. */
-        bool format_if_mount_failed;    /*!< If true, it will format the file system if it fails to mount. */
-} esp_vfs_spiffs_conf_t;
-
-/**
- * Register and mount SPIFFS to VFS with given path prefix.
- *
- * @param   conf                      Pointer to esp_vfs_spiffs_conf_t configuration structure
- *
- * @return  
- *          - ESP_OK                  if success
- *          - ESP_ERR_NO_MEM          if objects could not be allocated
- *          - ESP_ERR_INVALID_STATE   if already mounted or partition is encrypted
- *          - ESP_ERR_NOT_FOUND       if partition for SPIFFS was not found
- *          - ESP_FAIL                if mount or format fails
- */
-esp_err_t esp_vfs_spiffs_register(const esp_vfs_spiffs_conf_t * conf);
-
-/**
- * Unregister and unmount SPIFFS from VFS
- *
- * @param partition_label  Optional, label of the partition to unregister.
- *                         If not specified, first partition with subtype=spiffs is used.
- *
- * @return  
- *          - ESP_OK if successful
- *          - ESP_ERR_INVALID_STATE already unregistered
- */
-esp_err_t esp_vfs_spiffs_unregister(const char* partition_label);
-
-/**
- * Check if SPIFFS is mounted
- *
- * @param partition_label  Optional, label of the partition to check.
- *                         If not specified, first partition with subtype=spiffs is used.
- *
- * @return  
- *          - true    if mounted
- *          - false   if not mounted
- */
-bool esp_spiffs_mounted(const char* partition_label);
-
-/**
- * Format the SPIFFS partition
- *
- * @param partition_label  Optional, label of the partition to format.
- *                         If not specified, first partition with subtype=spiffs is used.
- * @return  
- *          - ESP_OK      if successful
- *          - ESP_FAIL    on error
- */
-esp_err_t esp_spiffs_format(const char* partition_label);
-
-/**
- * Get information for SPIFFS
- *
- * @param partition_label           Optional, label of the partition to get info for.
- *                                  If not specified, first partition with subtype=spiffs is used.
- * @param[out] total_bytes          Size of the file system
- * @param[out] used_bytes           Current used bytes in the file system
- *
- * @return  
- *          - ESP_OK                  if success
- *          - ESP_ERR_INVALID_STATE   if not mounted
- */
-esp_err_t esp_spiffs_info(const char* partition_label, size_t *total_bytes, size_t *used_bytes);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ESP_SPIFFS_H_ */
diff --git a/tools/sdk/include/spiffs/spiffs_config.h b/tools/sdk/include/spiffs/spiffs_config.h
deleted file mode 100644
index a382ba6f956..00000000000
--- a/tools/sdk/include/spiffs/spiffs_config.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * spiffs_config.h
- *
- *  Created on: Jul 3, 2013
- *      Author: petera
- */
-
-#ifndef SPIFFS_CONFIG_H_
-#define SPIFFS_CONFIG_H_
-
-// ----------- 8< ------------
-// Following includes are for the linux test build of spiffs
-// These may/should/must be removed/altered/replaced in your target
-#include <stdio.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include <stddef.h>
-#include <unistd.h>
-#include <sdkconfig.h>
-#include <esp_log.h>
-
-// compile time switches
-#define SPIFFS_TAG "SPIFFS"
-
-// Set generic spiffs debug output call.
-#if CONFIG_SPIFFS_DBG
-#define SPIFFS_DBG(...)             ESP_LOGD(SPIFFS_TAG, __VA_ARGS__)
-#else
-#define SPIFFS_DBG(...)
-#endif
-#if CONFIG_SPIFFS_API_DBG
-#define SPIFFS_API_DBG(...)         ESP_LOGD(SPIFFS_TAG, __VA_ARGS__)
-#else
-#define SPIFFS_API_DBG(...)
-#endif
-#if CONFIG_SPIFFS_DBG
-#define SPIFFS_GC_DBG(...)          ESP_LOGD(SPIFFS_TAG, __VA_ARGS__)
-#else
-#define SPIFFS_GC_DBG(...)
-#endif
-#if CONFIG_SPIFFS_CACHE_DBG
-#define SPIFFS_CACHE_DBG(...)       ESP_LOGD(SPIFFS_TAG, __VA_ARGS__)
-#else
-#define SPIFFS_CACHE_DBG(...)
-#endif
-#if CONFIG_SPIFFS_CHECK_DBG
-#define SPIFFS_CHECK_DBG(...)       ESP_LOGD(SPIFFS_TAG, __VA_ARGS__)
-#else
-#define SPIFFS_CHECK_DBG(...)
-#endif
-
-// needed types
-typedef signed int s32_t;
-typedef unsigned int u32_t;
-typedef signed short s16_t;
-typedef unsigned short u16_t;
-typedef signed char s8_t;
-typedef unsigned char u8_t;
-
-struct spiffs_t;
-extern void spiffs_api_lock(struct spiffs_t *fs);
-extern void spiffs_api_unlock(struct spiffs_t *fs);
-
-// Defines spiffs debug print formatters
-// some general signed number
-#define _SPIPRIi   "%d"
-// address
-#define _SPIPRIad  "%08x"
-// block
-#define _SPIPRIbl  "%04x"
-// page
-#define _SPIPRIpg  "%04x"
-// span index
-#define _SPIPRIsp  "%04x"
-// file descriptor
-#define _SPIPRIfd  "%d"
-// file object id
-#define _SPIPRIid  "%04x"
-// file flags
-#define _SPIPRIfl  "%02x"
-
-
-// Enable/disable API functions to determine exact number of bytes
-// for filedescriptor and cache buffers. Once decided for a configuration,
-// this can be disabled to reduce flash.
-#define SPIFFS_BUFFER_HELP              0
-
-// Enables/disable memory read caching of nucleus file system operations.
-// If enabled, memory area must be provided for cache in SPIFFS_mount.
-#ifdef CONFIG_SPIFFS_CACHE
-#define SPIFFS_CACHE                (1)
-#else
-#define SPIFFS_CACHE                (0)
-#endif
-#if SPIFFS_CACHE
-// Enables memory write caching for file descriptors in hydrogen
-#ifdef CONFIG_SPIFFS_CACHE_WR
-#define SPIFFS_CACHE_WR             (1)
-#else
-#define SPIFFS_CACHE_WR             (0)
-#endif
-
-// Enable/disable statistics on caching. Debug/test purpose only.
-#ifdef CONFIG_SPIFFS_CACHE_STATS
-#define SPIFFS_CACHE_STATS          (1)
-#else
-#define SPIFFS_CACHE_STATS          (0)
-#endif
-#endif
-
-// Always check header of each accessed page to ensure consistent state.
-// If enabled it will increase number of reads, will increase flash.
-#ifdef CONFIG_SPIFFS_PAGE_CHECK
-#define SPIFFS_PAGE_CHECK           (1)
-#else
-#define SPIFFS_PAGE_CHECK           (0)
-#endif
-
-// Define maximum number of gc runs to perform to reach desired free pages.
-#define SPIFFS_GC_MAX_RUNS              CONFIG_SPIFFS_GC_MAX_RUNS
-
-// Enable/disable statistics on gc. Debug/test purpose only.
-#ifdef CONFIG_SPIFFS_GC_STATS
-#define SPIFFS_GC_STATS             (1)
-#else
-#define SPIFFS_GC_STATS             (0)
-#endif
-
-// Garbage collecting examines all pages in a block which and sums up
-// to a block score. Deleted pages normally gives positive score and
-// used pages normally gives a negative score (as these must be moved).
-// To have a fair wear-leveling, the erase age is also included in score,
-// whose factor normally is the most positive.
-// The larger the score, the more likely it is that the block will
-// picked for garbage collection.
-
-// Garbage collecting heuristics - weight used for deleted pages.
-#define SPIFFS_GC_HEUR_W_DELET          (5)
-// Garbage collecting heuristics - weight used for used pages.
-#define SPIFFS_GC_HEUR_W_USED           (-1)
-// Garbage collecting heuristics - weight used for time between
-// last erased and erase of this block.
-#define SPIFFS_GC_HEUR_W_ERASE_AGE      (50)
-
-// Object name maximum length. Note that this length include the
-// zero-termination character, meaning maximum string of characters
-// can at most be SPIFFS_OBJ_NAME_LEN - 1.
-#define SPIFFS_OBJ_NAME_LEN             (CONFIG_SPIFFS_OBJ_NAME_LEN)
-
-// Maximum length of the metadata associated with an object.
-// Setting to non-zero value enables metadata-related API but also
-// changes the on-disk format, so the change is not backward-compatible.
-//
-// Do note: the meta length must never exceed
-// logical_page_size - (SPIFFS_OBJ_NAME_LEN + SPIFFS_PAGE_EXTRA_SIZE)
-//
-// This is derived from following:
-// logical_page_size - (SPIFFS_OBJ_NAME_LEN + sizeof(spiffs_page_header) +
-// spiffs_object_ix_header fields + at least some LUT entries)
-#define SPIFFS_OBJ_META_LEN             (CONFIG_SPIFFS_META_LENGTH)
-#define SPIFFS_PAGE_EXTRA_SIZE          (64)
-_Static_assert(SPIFFS_OBJ_META_LEN + SPIFFS_OBJ_NAME_LEN + SPIFFS_PAGE_EXTRA_SIZE
-        <= CONFIG_SPIFFS_PAGE_SIZE, "SPIFFS_OBJ_META_LEN or SPIFFS_OBJ_NAME_LEN too long");
-
-// Size of buffer allocated on stack used when copying data.
-// Lower value generates more read/writes. No meaning having it bigger
-// than logical page size.
-#define SPIFFS_COPY_BUFFER_STACK        (256)
-
-// Enable this to have an identifiable spiffs filesystem. This will look for
-// a magic in all sectors to determine if this is a valid spiffs system or
-// not on mount point. If not, SPIFFS_format must be called prior to mounting
-// again.
-#ifdef CONFIG_SPIFFS_USE_MAGIC
-#define SPIFFS_USE_MAGIC                (1)
-#else
-#define SPIFFS_USE_MAGIC                (0)
-#endif
-
-#if SPIFFS_USE_MAGIC
-// Only valid when SPIFFS_USE_MAGIC is enabled. If SPIFFS_USE_MAGIC_LENGTH is
-// enabled, the magic will also be dependent on the length of the filesystem.
-// For example, a filesystem configured and formatted for 4 megabytes will not
-// be accepted for mounting with a configuration defining the filesystem as 2
-// megabytes.
-#ifdef CONFIG_SPIFFS_USE_MAGIC_LENGTH
-#define SPIFFS_USE_MAGIC_LENGTH         (1)
-#else
-#define SPIFFS_USE_MAGIC_LENGTH         (0)
-#endif
-#endif
-
-// SPIFFS_LOCK and SPIFFS_UNLOCK protects spiffs from reentrancy on api level
-// These should be defined on a multithreaded system
-
-// define this to enter a mutex if you're running on a multithreaded system
-#define SPIFFS_LOCK(fs)   spiffs_api_lock(fs)
-// define this to exit a mutex if you're running on a multithreaded system
-#define SPIFFS_UNLOCK(fs) spiffs_api_unlock(fs)
-
-// Enable if only one spiffs instance with constant configuration will exist
-// on the target. This will reduce calculations, flash and memory accesses.
-// Parts of configuration must be defined below instead of at time of mount.
-#define SPIFFS_SINGLETON 0
-
-// Enable this if your target needs aligned data for index tables
-#define SPIFFS_ALIGNED_OBJECT_INDEX_TABLES      0
-
-// Enable this if you want the HAL callbacks to be called with the spiffs struct
-#define SPIFFS_HAL_CALLBACK_EXTRA               1
-
-// Enable this if you want to add an integer offset to all file handles
-// (spiffs_file). This is useful if running multiple instances of spiffs on
-// same target, in order to recognise to what spiffs instance a file handle
-// belongs.
-// NB: This adds config field fh_ix_offset in the configuration struct when
-// mounting, which must be defined.
-#define SPIFFS_FILEHDL_OFFSET                   0
-
-// Enable this to compile a read only version of spiffs.
-// This will reduce binary size of spiffs. All code comprising modification
-// of the file system will not be compiled. Some config will be ignored.
-// HAL functions for erasing and writing to spi-flash may be null. Cache
-// can be disabled for even further binary size reduction (and ram savings).
-// Functions modifying the fs will return SPIFFS_ERR_RO_NOT_IMPL.
-// If the file system cannot be mounted due to aborted erase operation and
-// SPIFFS_USE_MAGIC is enabled, SPIFFS_ERR_RO_ABORTED_OPERATION will be
-// returned.
-// Might be useful for e.g. bootloaders and such.
-#define SPIFFS_READ_ONLY                        0
-
-// Enable this to add a temporal file cache using the fd buffer.
-// The effects of the cache is that SPIFFS_open will find the file faster in
-// certain cases. It will make it a lot easier for spiffs to find files
-// opened frequently, reducing number of readings from the spi flash for
-// finding those files.
-// This will grow each fd by 6 bytes. If your files are opened in patterns
-// with a degree of temporal locality, the system is optimized.
-// Examples can be letting spiffs serve web content, where one file is the css.
-// The css is accessed for each html file that is opened, meaning it is
-// accessed almost every second time a file is opened. Another example could be
-// a log file that is often opened, written, and closed.
-// The size of the cache is number of given file descriptors, as it piggybacks
-// on the fd update mechanism. The cache lives in the closed file descriptors.
-// When closed, the fd know the whereabouts of the file. Instead of forgetting
-// this, the temporal cache will keep handling updates to that file even if the
-// fd is closed. If the file is opened again, the location of the file is found
-// directly. If all available descriptors become opened, all cache memory is
-// lost.
-#define SPIFFS_TEMPORAL_FD_CACHE                1
-
-// Temporal file cache hit score. Each time a file is opened, all cached files
-// will lose one point. If the opened file is found in cache, that entry will
-// gain SPIFFS_TEMPORAL_CACHE_HIT_SCORE points. One can experiment with this
-// value for the specific access patterns of the application. However, it must
-// be between 1 (no gain for hitting a cached entry often) and 255.
-#define SPIFFS_TEMPORAL_CACHE_HIT_SCORE         4
-
-// Enable to be able to map object indices to memory.
-// This allows for faster and more deterministic reading if cases of reading
-// large files and when changing file offset by seeking around a lot.
-// When mapping a file's index, the file system will be scanned for index pages
-// and the info will be put in memory provided by user. When reading, the
-// memory map can be looked up instead of searching for index pages on the
-// medium. This way, user can trade memory against performance.
-// Whole, parts of, or future parts not being written yet can be mapped. The
-// memory array will be owned by spiffs and updated accordingly during garbage
-// collecting or when modifying the indices. The latter is invoked by when the
-// file is modified in some way. The index buffer is tied to the file
-// descriptor.
-#define SPIFFS_IX_MAP                           1
-
-// Set SPIFFS_TEST_VISUALISATION to non-zero to enable SPIFFS_vis function
-// in the api. This function will visualize all filesystem using given printf
-// function.
-#ifdef CONFIG_SPIFFS_TEST_VISUALISATION
-#define SPIFFS_TEST_VISUALISATION               1
-#else
-#define SPIFFS_TEST_VISUALISATION               0
-#endif
-#if SPIFFS_TEST_VISUALISATION
-#ifndef spiffs_printf
-#define spiffs_printf(...)                ESP_LOGD(SPIFFS_TAG, __VA_ARGS__)
-#endif
-// spiffs_printf argument for a free page
-#define SPIFFS_TEST_VIS_FREE_STR          "_"
-// spiffs_printf argument for a deleted page
-#define SPIFFS_TEST_VIS_DELE_STR          "/"
-// spiffs_printf argument for an index page for given object id
-#define SPIFFS_TEST_VIS_INDX_STR(id)      "i"
-// spiffs_printf argument for a data page for given object id
-#define SPIFFS_TEST_VIS_DATA_STR(id)      "d"
-#endif
-
-// Types depending on configuration such as the amount of flash bytes
-// given to spiffs file system in total (spiffs_file_system_size),
-// the logical block size (log_block_size), and the logical page size
-// (log_page_size)
-
-// Block index type. Make sure the size of this type can hold
-// the highest number of all blocks - i.e. spiffs_file_system_size / log_block_size
-typedef u16_t spiffs_block_ix;
-// Page index type. Make sure the size of this type can hold
-// the highest page number of all pages - i.e. spiffs_file_system_size / log_page_size
-typedef u16_t spiffs_page_ix;
-// Object id type - most significant bit is reserved for index flag. Make sure the
-// size of this type can hold the highest object id on a full system,
-// i.e. 2 + (spiffs_file_system_size / (2*log_page_size))*2
-typedef u16_t spiffs_obj_id;
-// Object span index type. Make sure the size of this type can
-// hold the largest possible span index on the system -
-// i.e. (spiffs_file_system_size / log_page_size) - 1
-typedef u16_t spiffs_span_ix;
-
-#endif /* SPIFFS_CONFIG_H_ */
diff --git a/tools/sdk/include/tcp_transport/esp_transport.h b/tools/sdk/include/tcp_transport/esp_transport.h
deleted file mode 100644
index e163a010cd9..00000000000
--- a/tools/sdk/include/tcp_transport/esp_transport.h
+++ /dev/null
@@ -1,304 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_TRANSPORT_H_
-#define _ESP_TRANSPORT_H_
-
-#include <esp_err.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-typedef struct esp_transport_list_t* esp_transport_list_handle_t;
-typedef struct esp_transport_item_t* esp_transport_handle_t;
-
-typedef int (*connect_func)(esp_transport_handle_t t, const char *host, int port, int timeout_ms);
-typedef int (*io_func)(esp_transport_handle_t t, const char *buffer, int len, int timeout_ms);
-typedef int (*io_read_func)(esp_transport_handle_t t, char *buffer, int len, int timeout_ms);
-typedef int (*trans_func)(esp_transport_handle_t t);
-typedef int (*poll_func)(esp_transport_handle_t t, int timeout_ms);
-typedef int (*connect_async_func)(esp_transport_handle_t t, const char *host, int port, int timeout_ms);
-typedef esp_transport_handle_t (*payload_transfer_func)(esp_transport_handle_t);
-
-/**
- * @brief      Create transport list
- *
- * @return     A handle can hold all transports
- */
-esp_transport_list_handle_t esp_transport_list_init();
-
-/**
- * @brief      Cleanup and free all transports, include itself,
- *             this function will invoke esp_transport_destroy of every transport have added this the list
- *
- * @param[in]  list  The list
- *
- * @return
- *     - ESP_OK
- *     - ESP_FAIL
- */
-esp_err_t esp_transport_list_destroy(esp_transport_list_handle_t list);
-
-/**
- * @brief      Add a transport to the list, and define a scheme to indentify this transport in the list
- *
- * @param[in]  list    The list
- * @param[in]  t       The Transport
- * @param[in]  scheme  The scheme
- *
- * @return
- *     - ESP_OK
- */
-esp_err_t esp_transport_list_add(esp_transport_list_handle_t list, esp_transport_handle_t t, const char *scheme);
-
-/**
- * @brief      This function will remove all transport from the list,
- *             invoke esp_transport_destroy of every transport have added this the list
- *
- * @param[in]  list  The list
- *
- * @return
- *     - ESP_OK
- *     - ESP_ERR_INVALID_ARG
- */
-esp_err_t esp_transport_list_clean(esp_transport_list_handle_t list);
-
-/**
- * @brief      Get the transport by scheme, which has been defined when calling function `esp_transport_list_add`
- *
- * @param[in]  list  The list
- * @param[in]  tag   The tag
- *
- * @return     The transport handle
- */
-esp_transport_handle_t esp_transport_list_get_transport(esp_transport_list_handle_t list, const char *scheme);
-
-/**
- * @brief      Initialize a transport handle object
- *
- * @return     The transport handle
- */
-esp_transport_handle_t esp_transport_init();
-
-/**
- * @brief      Cleanup and free memory the transport
- *
- * @param[in]  t     The transport handle
- *
- * @return
- *     - ESP_OK
- *     - ESP_FAIL
- */
-esp_err_t esp_transport_destroy(esp_transport_handle_t t);
-
-/**
- * @brief      Get default port number used by this transport
- *
- * @param[in]  t     The transport handle
- *
- * @return     the port number
- */
-int esp_transport_get_default_port(esp_transport_handle_t t);
-
-/**
- * @brief      Set default port number that can be used by this transport
- *
- * @param[in]  t     The transport handle
- * @param[in]  port  The port number
- *
- * @return
- *     - ESP_OK
- *     - ESP_FAIL
- */
-esp_err_t esp_transport_set_default_port(esp_transport_handle_t t, int port);
-
-/**
- * @brief      Transport connection function, to make a connection to server
- *
- * @param      t           The transport handle
- * @param[in]  host        Hostname
- * @param[in]  port        Port
- * @param[in]  timeout_ms  The timeout milliseconds
- *
- * @return
- * - socket for will use by this transport
- * - (-1) if there are any errors, should check errno
- */
-int esp_transport_connect(esp_transport_handle_t t, const char *host, int port, int timeout_ms);
-
-/**
- * @brief      Non-blocking transport connection function, to make a connection to server
- *
- * @param      t           The transport handle
- * @param[in]  host        Hostname
- * @param[in]  port        Port
- * @param[in]  timeout_ms  The timeout milliseconds
- *
- * @return
- * - socket for will use by this transport
- * - (-1) if there are any errors, should check errno
- */
-int esp_transport_connect_async(esp_transport_handle_t t, const char *host, int port, int timeout_ms);
-
-/**
- * @brief      Transport read function
- *
- * @param      t           The transport handle
- * @param      buffer      The buffer
- * @param[in]  len         The length
- * @param[in]  timeout_ms  The timeout milliseconds
- *
- * @return
- *  - Number of bytes was read
- *  - (-1) if there are any errors, should check errno
- */
-int esp_transport_read(esp_transport_handle_t t, char *buffer, int len, int timeout_ms);
-
-/**
- * @brief      Poll the transport until readable or timeout
- *
- * @param[in]  t           The transport handle
- * @param[in]  timeout_ms  The timeout milliseconds
- *
- * @return
- *     - 0      Timeout
- *     - (-1)   If there are any errors, should check errno
- *     - other  The transport can read
- */
-int esp_transport_poll_read(esp_transport_handle_t t, int timeout_ms);
-
-/**
- * @brief      Transport write function
- *
- * @param      t           The transport handle
- * @param      buffer      The buffer
- * @param[in]  len         The length
- * @param[in]  timeout_ms  The timeout milliseconds
- *
- * @return
- *  - Number of bytes was written
- *  - (-1) if there are any errors, should check errno
- */
-int esp_transport_write(esp_transport_handle_t t, const char *buffer, int len, int timeout_ms);
-
-/**
- * @brief      Poll the transport until writeable or timeout
- *
- * @param[in]  t           The transport handle
- * @param[in]  timeout_ms  The timeout milliseconds
- *
- * @return
- *     - 0      Timeout
- *     - (-1)   If there are any errors, should check errno
- *     - other  The transport can write
- */
-int esp_transport_poll_write(esp_transport_handle_t t, int timeout_ms);
-
-/**
- * @brief      Transport close
- *
- * @param      t     The transport handle
- *
- * @return
- * - 0 if ok
- * - (-1) if there are any errors, should check errno
- */
-int esp_transport_close(esp_transport_handle_t t);
-
-/**
- * @brief      Get user data context of this transport
- *
- * @param[in]  t        The transport handle
- *
- * @return     The user data context
- */
-void *esp_transport_get_context_data(esp_transport_handle_t t);
-
-/**
- * @brief      Get transport handle of underlying protocol
- *             which can access this protocol payload directly
- *             (used for receiving longer msg multiple times)
- *
- * @param[in]  t        The transport handle
- *
- * @return     Payload transport handle
- */
-esp_transport_handle_t esp_transport_get_payload_transport_handle(esp_transport_handle_t t);
-
-/**
- * @brief      Set the user context data for this transport
- *
- * @param[in]  t        The transport handle
- * @param      data     The user data context
- *
- * @return
- *     - ESP_OK
- */
-esp_err_t esp_transport_set_context_data(esp_transport_handle_t t, void *data);
-
-/**
- * @brief      Set transport functions for the transport handle
- *
- * @param[in]  t            The transport handle
- * @param[in]  _connect     The connect function pointer
- * @param[in]  _read        The read function pointer
- * @param[in]  _write       The write function pointer
- * @param[in]  _close       The close function pointer
- * @param[in]  _poll_read   The poll read function pointer
- * @param[in]  _poll_write  The poll write function pointer
- * @param[in]  _destroy     The destroy function pointer
- *
- * @return
- *     - ESP_OK
- */
-esp_err_t esp_transport_set_func(esp_transport_handle_t t,
-                             connect_func _connect,
-                             io_read_func _read,
-                             io_func _write,
-                             trans_func _close,
-                             poll_func _poll_read,
-                             poll_func _poll_write,
-                             trans_func _destroy);
-
-
-/**
- * @brief      Set transport functions for the transport handle
- *
- * @param[in]  t                    The transport handle
- * @param[in]  _connect_async_func  The connect_async function pointer
- *
- * @return
- *     - ESP_OK
- *     - ESP_FAIL
- */
-esp_err_t esp_transport_set_async_connect_func(esp_transport_handle_t t, connect_async_func _connect_async_func);
-
-/**
- * @brief      Set parent transport function to the handle
- *
- * @param[in]  t                    The transport handle
- * @param[in]  _parent_transport    The underlying transport getter pointer
- *
- * @return
- *     - ESP_OK
- *     - ESP_FAIL
- */
-esp_err_t esp_transport_set_parent_transport_func(esp_transport_handle_t t, payload_transfer_func _parent_transport);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _ESP_TRANSPORT_ */
diff --git a/tools/sdk/include/tcp_transport/esp_transport_ssl.h b/tools/sdk/include/tcp_transport/esp_transport_ssl.h
deleted file mode 100644
index 0f83c1d6e49..00000000000
--- a/tools/sdk/include/tcp_transport/esp_transport_ssl.h
+++ /dev/null
@@ -1,85 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_TRANSPORT_SSL_H_
-#define _ESP_TRANSPORT_SSL_H_
-
-#include "esp_transport.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**
- * @brief       Create new SSL transport, the transport handle must be release esp_transport_destroy callback
- *
- * @return      the allocated esp_transport_handle_t, or NULL if the handle can not be allocated
- */
-esp_transport_handle_t esp_transport_ssl_init();
-
-/**
- * @brief      Set SSL certificate data (as PEM format).
- *             Note that, this function stores the pointer to data, rather than making a copy.
- *             So this data must remain valid until after the connection is cleaned up
- *
- * @param      t     ssl transport
- * @param[in]  data  The pem data
- * @param[in]  len   The length
- */
-void esp_transport_ssl_set_cert_data(esp_transport_handle_t t, const char *data, int len);
-
-/**
- * @brief      Enable global CA store for SSL connection
- *
- * @param      t    ssl transport
- */
-void esp_transport_ssl_enable_global_ca_store(esp_transport_handle_t t);
-
-/**
- * @brief      Set SSL client certificate data for mutual authentication (as PEM format).
- *             Note that, this function stores the pointer to data, rather than making a copy.
- *             So this data must remain valid until after the connection is cleaned up
- *
- * @param      t     ssl transport
- * @param[in]  data  The pem data
- * @param[in]  len   The length
- */
-void esp_transport_ssl_set_client_cert_data(esp_transport_handle_t t, const char *data, int len);
-
-/**
- * @brief      Set SSL client key data for mutual authentication (as PEM format).
- *             Note that, this function stores the pointer to data, rather than making a copy.
- *             So this data must remain valid until after the connection is cleaned up
- *
- * @param      t     ssl transport
- * @param[in]  data  The pem data
- * @param[in]  len   The length
- */
-void esp_transport_ssl_set_client_key_data(esp_transport_handle_t t, const char *data, int len);
-
-/**
- * @brief      Skip validation of certificate's common name field
- *
- * @note       Skipping CN validation is not recommended
- *
- * @param      t     ssl transport
- */
-void esp_transport_ssl_skip_common_name_check(esp_transport_handle_t t);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _ESP_TRANSPORT_SSL_H_ */
-
diff --git a/tools/sdk/include/tcp_transport/esp_transport_tcp.h b/tools/sdk/include/tcp_transport/esp_transport_tcp.h
deleted file mode 100644
index 57ad453309f..00000000000
--- a/tools/sdk/include/tcp_transport/esp_transport_tcp.h
+++ /dev/null
@@ -1,36 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_TRANSPORT_TCP_H_
-#define _ESP_TRANSPORT_TCP_H_
-
-#include "esp_transport.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief      Create TCP transport, the transport handle must be release esp_transport_destroy callback
- *
- * @return  the allocated esp_transport_handle_t, or NULL if the handle can not be allocated
- */
-esp_transport_handle_t esp_transport_tcp_init();
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ESP_TRANSPORT_TCP_H_ */
diff --git a/tools/sdk/include/tcp_transport/esp_transport_utils.h b/tools/sdk/include/tcp_transport/esp_transport_utils.h
deleted file mode 100644
index 405b4f6b46e..00000000000
--- a/tools/sdk/include/tcp_transport/esp_transport_utils.h
+++ /dev/null
@@ -1,40 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _ESP_TRANSPORT_UTILS_H_
-#define _ESP_TRANSPORT_UTILS_H_
-#include <sys/time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief      Convert milliseconds to timeval struct
- *
- * @param[in]  timeout_ms  The timeout milliseconds
- * @param[out] tv          Timeval struct
- */
-void esp_transport_utils_ms_to_timeval(int timeout_ms, struct timeval *tv);
-
-
-#define ESP_TRANSPORT_MEM_CHECK(TAG, a, action) if (!(a)) {                                                      \
-        ESP_LOGE(TAG,"%s:%d (%s): %s", __FILE__, __LINE__, __FUNCTION__, "Memory exhausted");       \
-        action;                                                                                         \
-        }
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _ESP_TRANSPORT_UTILS_H_ */
\ No newline at end of file
diff --git a/tools/sdk/include/tcp_transport/esp_transport_ws.h b/tools/sdk/include/tcp_transport/esp_transport_ws.h
deleted file mode 100644
index 08ed2ef27e1..00000000000
--- a/tools/sdk/include/tcp_transport/esp_transport_ws.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is subject to the terms and conditions defined in
- * file 'LICENSE', which is part of this source code package.
- * Tuan PM <tuanpm at live dot com>
- */
-
-#ifndef _ESP_TRANSPORT_WS_H_
-#define _ESP_TRANSPORT_WS_H_
-
-#include "esp_transport.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum ws_transport_opcodes {
-    WS_TRANSPORT_OPCODES_CONT =  0x00,
-    WS_TRANSPORT_OPCODES_TEXT =  0x01,
-    WS_TRANSPORT_OPCODES_BINARY = 0x02,
-    WS_TRANSPORT_OPCODES_CLOSE = 0x08,
-    WS_TRANSPORT_OPCODES_PING = 0x09,
-    WS_TRANSPORT_OPCODES_PONG = 0x0a,
-    WS_TRANSPORT_OPCODES_FIN = 0x80,
-} ws_transport_opcodes_t;
-
-/**
- * @brief      Create web socket transport
- *
- * @return
- *  - transport
- *  - NULL
- */
-esp_transport_handle_t esp_transport_ws_init(esp_transport_handle_t parent_handle);
-
-/**
- * @brief       Set HTTP path to update protocol to websocket
- *
- * @param t     websocket transport handle
- * @param path  The HTTP Path
- */
-void esp_transport_ws_set_path(esp_transport_handle_t t, const char *path);
-
-/**
- * @brief               Set websocket sub protocol header
- *
- * @param t             websocket transport handle
- * @param sub_protocol  Sub protocol string
- *
- * @return
- *      - ESP_OK on success
- *      - One of the error codes
- */
-esp_err_t esp_transport_ws_set_subprotocol(esp_transport_handle_t t, const char *sub_protocol);
-
-/**
- * @brief               Set websocket user-agent header
- *
- * @param t             websocket transport handle
- * @param sub_protocol  user-agent string
- *
- * @return
- *      - ESP_OK on success
- *      - One of the error codes
- */
-esp_err_t esp_transport_ws_set_user_agent(esp_transport_handle_t t, const char *user_agent);
-
-/**
- * @brief               Set websocket additional headers
- *
- * @param t             websocket transport handle
- * @param sub_protocol  additional header strings each terminated with \r\n
- *
- * @return
- *      - ESP_OK on success
- *      - One of the error codes
- */
-esp_err_t esp_transport_ws_set_headers(esp_transport_handle_t t, const char *headers);
-
-/**
- * @brief               Sends websocket raw message with custom opcode and payload
- *
- * Note that generic esp_transport_write for ws handle sends
- * binary massages by default if size is > 0 and
- * ping message if message size is set to 0.
- * This API is provided to support explicit messages with arbitrary opcode,
- * should it be PING, PONG or TEXT message with arbitrary data.
- *
- * @param[in]  t           Websocket transport handle
- * @param[in]  opcode      ws operation code
- * @param[in]  buffer      The buffer
- * @param[in]  len         The length
- * @param[in]  timeout_ms  The timeout milliseconds (-1 indicates block forever)
- *
- * @return
- *  - Number of bytes was written
- *  - (-1) if there are any errors, should check errno
- */
-int esp_transport_ws_send_raw(esp_transport_handle_t t, ws_transport_opcodes_t opcode, const char *b, int len, int timeout_ms);
-
-/**
- * @brief               Returns websocket op-code for last received data
- *
- * @param t             websocket transport handle
- *
- * @return
- *      - Received op-code as enum
- */
-ws_transport_opcodes_t esp_transport_ws_get_read_opcode(esp_transport_handle_t t);
-
-/**
- * @brief               Returns payload length of the last received data
- *
- * @param t             websocket transport handle
- *
- * @return
- *      - Number of bytes in the payload
- */
-int esp_transport_ws_get_read_payload_len(esp_transport_handle_t t);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ESP_TRANSPORT_WS_H_ */
diff --git a/tools/sdk/include/tcpip_adapter/tcpip_adapter.h b/tools/sdk/include/tcpip_adapter/tcpip_adapter.h
deleted file mode 100644
index 848bf16adca..00000000000
--- a/tools/sdk/include/tcpip_adapter/tcpip_adapter.h
+++ /dev/null
@@ -1,683 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _TCPIP_ADAPTER_H_
-#define _TCPIP_ADAPTER_H_
-
-#include <stdint.h>
-#include "rom/queue.h"
-#include "esp_wifi_types.h"
-#include "sdkconfig.h"
-
-#if CONFIG_TCPIP_LWIP
-#include "lwip/ip_addr.h"
-#include "dhcpserver/dhcpserver.h"
-
-typedef dhcps_lease_t tcpip_adapter_dhcps_lease_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define IP2STR(ipaddr) ip4_addr1_16(ipaddr), \
-    ip4_addr2_16(ipaddr), \
-    ip4_addr3_16(ipaddr), \
-    ip4_addr4_16(ipaddr)
-
-#define IPSTR "%d.%d.%d.%d"
-
-#define IPV62STR(ipaddr) IP6_ADDR_BLOCK1(&(ipaddr)),     \
-    IP6_ADDR_BLOCK2(&(ipaddr)),     \
-    IP6_ADDR_BLOCK3(&(ipaddr)),     \
-    IP6_ADDR_BLOCK4(&(ipaddr)),     \
-    IP6_ADDR_BLOCK5(&(ipaddr)),     \
-    IP6_ADDR_BLOCK6(&(ipaddr)),     \
-    IP6_ADDR_BLOCK7(&(ipaddr)),     \
-    IP6_ADDR_BLOCK8(&(ipaddr))
-
-#define IPV6STR "%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x"
-
-/** @brief IPV4 IP address information
- */
-typedef struct {
-    ip4_addr_t ip;      /**< Interface IPV4 address */
-    ip4_addr_t netmask; /**< Interface IPV4 netmask */
-    ip4_addr_t gw;      /**< Interface IPV4 gateway address */
-} tcpip_adapter_ip_info_t;
-
-/** @brief IPV6 IP address information
- */
-typedef struct {
-    ip6_addr_t ip; /**< Interface IPV6 address */
-} tcpip_adapter_ip6_info_t;
-
-/** @brief IP address info of station connected to WLAN AP
- *
- * @note See also wifi_sta_info_t (MAC layer information only)
- */
-typedef struct {
-    uint8_t mac[6]; /**< Station MAC address */
-    ip4_addr_t ip;  /**< Station assigned IP address */
-} tcpip_adapter_sta_info_t;
-
-/** @brief WLAN AP: Connected stations list
- *
- * Used to retrieve IP address information about connected stations.
- */
-typedef struct {
-    tcpip_adapter_sta_info_t sta[ESP_WIFI_MAX_CONN_NUM]; /**< Connected stations */
-    int num; /**< Number of connected stations */
-} tcpip_adapter_sta_list_t;
-
-#endif
-
-#define ESP_ERR_TCPIP_ADAPTER_BASE                  0x5000
-#define ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS        ESP_ERR_TCPIP_ADAPTER_BASE + 0x01
-#define ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY          ESP_ERR_TCPIP_ADAPTER_BASE + 0x02
-#define ESP_ERR_TCPIP_ADAPTER_DHCPC_START_FAILED    ESP_ERR_TCPIP_ADAPTER_BASE + 0x03
-#define ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED  ESP_ERR_TCPIP_ADAPTER_BASE + 0x04
-#define ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPPED  ESP_ERR_TCPIP_ADAPTER_BASE + 0x05
-#define ESP_ERR_TCPIP_ADAPTER_NO_MEM                ESP_ERR_TCPIP_ADAPTER_BASE + 0x06
-#define ESP_ERR_TCPIP_ADAPTER_DHCP_NOT_STOPPED      ESP_ERR_TCPIP_ADAPTER_BASE + 0x07
-
-/* @brief On-chip network interfaces */
-typedef enum {
-    TCPIP_ADAPTER_IF_STA = 0,     /**< Wi-Fi STA (station) interface */
-    TCPIP_ADAPTER_IF_AP,          /**< Wi-Fi soft-AP interface */
-    TCPIP_ADAPTER_IF_ETH,         /**< Ethernet interface */
-    TCPIP_ADAPTER_IF_MAX
-} tcpip_adapter_if_t;
-
-/** @brief Type of DNS server */
-typedef enum {
-    TCPIP_ADAPTER_DNS_MAIN= 0,       /**< DNS main server address*/
-    TCPIP_ADAPTER_DNS_BACKUP,        /**< DNS backup server address (Wi-Fi STA and Ethernet only) */
-    TCPIP_ADAPTER_DNS_FALLBACK,      /**< DNS fallback server address (Wi-Fi STA and Ethernet only) */
-    TCPIP_ADAPTER_DNS_MAX
-} tcpip_adapter_dns_type_t;
-
-/** @brief DNS server info */
-typedef struct {
-    ip_addr_t ip; /**< IPV4 address of DNS server */
-} tcpip_adapter_dns_info_t;
-
-/** @brief Status of DHCP client or DHCP server */
-typedef enum {
-    TCPIP_ADAPTER_DHCP_INIT = 0,    /**< DHCP client/server is in initial state (not yet started) */
-    TCPIP_ADAPTER_DHCP_STARTED,     /**< DHCP client/server has been started */
-    TCPIP_ADAPTER_DHCP_STOPPED,     /**< DHCP client/server has been stopped */
-    TCPIP_ADAPTER_DHCP_STATUS_MAX
-} tcpip_adapter_dhcp_status_t;
-
-/** @brief Mode for DHCP client or DHCP server option functions */
-typedef enum{
-    TCPIP_ADAPTER_OP_START = 0,
-    TCPIP_ADAPTER_OP_SET,           /**< Set option */
-    TCPIP_ADAPTER_OP_GET,           /**< Get option */
-    TCPIP_ADAPTER_OP_MAX
-} tcpip_adapter_dhcp_option_mode_t;
-
-/* Deprecated name for tcpip_adapter_dhcp_option_mode_t, to remove after ESP-IDF V4.0 */
-typedef tcpip_adapter_dhcp_option_mode_t tcpip_adapter_option_mode_t;
-
-/** @brief Supported options for DHCP client or DHCP server */
-typedef enum{
-    TCPIP_ADAPTER_DOMAIN_NAME_SERVER            = 6,    /**< Domain name server */
-    TCPIP_ADAPTER_ROUTER_SOLICITATION_ADDRESS   = 32,   /**< Solicitation router address */
-    TCPIP_ADAPTER_REQUESTED_IP_ADDRESS          = 50,   /**< Request specific IP address */
-    TCPIP_ADAPTER_IP_ADDRESS_LEASE_TIME         = 51,   /**< Request IP address lease time */
-    TCPIP_ADAPTER_IP_REQUEST_RETRY_TIME         = 52,   /**< Request IP address retry counter */
-} tcpip_adapter_dhcp_option_id_t;
-
-/* Deprecated name for tcpip_adapter_dhcp_option_id_t, to remove after ESP-IDF V4.0 */
-typedef tcpip_adapter_dhcp_option_id_t tcpip_adapter_option_id_t;
-
-/**
- * @brief  Initialize the underlying TCP/IP stack
- *
- * @note This function should be called exactly once from application code, when the application starts up.
- */
-void tcpip_adapter_init(void);
-
-/**
- * @brief  Cause the TCP/IP stack to start the Ethernet interface with specified MAC and IP
- *
- * @note This function should be called after the Ethernet MAC hardware is initialized. In the default configuration, application code does not need to call this function - it is called automatically by the default handler for the SYSTEM_EVENT_ETH_START event.
- *
- * @param[in]  mac Set MAC address of this interface
- * @param[in]  ip_info Set IP address of this interface
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *         - ESP_ERR_NO_MEM
- */
-esp_err_t tcpip_adapter_eth_start(uint8_t *mac, tcpip_adapter_ip_info_t *ip_info);
-
-/**
- * @brief  Cause the TCP/IP stack to start the Wi-Fi station interface with specified MAC and IP
- *
- *
- * @note This function should be called after the Wi-Fi Station hardware is initialized. In the default configuration, application code does not need to call this function - it is called automatically by the default handler for the SYSTEM_EVENT_STA_START event.
- *
- * @param[in]  mac Set MAC address of this interface
- * @param[in]  ip_info Set IP address of this interface
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *         - ESP_ERR_NO_MEM
- */
-esp_err_t tcpip_adapter_sta_start(uint8_t *mac, tcpip_adapter_ip_info_t *ip_info);
-
-/**
- * @brief  Cause the TCP/IP stack to start the Wi-Fi AP interface with specified MAC and IP
- *
- * @note This function should be called after the Wi-Fi AP hardware is initialized. In the default configuration, application code does not need to call this function - it is called automatically by the default handler for the SYSTEM_EVENT_AP_START event.
- *
- * DHCP server will be started automatically when this function is called.
- *
- * @param[in]  mac Set MAC address of this interface
- * @param[in]  ip_info Set IP address of this interface
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *         - ESP_ERR_NO_MEM
- */
-esp_err_t tcpip_adapter_ap_start(uint8_t *mac, tcpip_adapter_ip_info_t *ip_info);
-
-/**
- * @brief  Cause the TCP/IP stack to stop a network interface
- *
- * Causes TCP/IP stack to clean up this interface. This includes stopping the DHCP server or client, if they are started.
- *
- * @note This API is called by the default Wi-Fi and Ethernet event handlers if the underlying network driver reports that the
- * interface has stopped.
- *
- * @note To stop an interface from application code, call the network-specific API (esp_wifi_stop() or esp_eth_stop()).
- * The driver layer will then send a stop event and the event handler should call this API.
- * Otherwise, the driver and MAC layer will remain started.
- *
- * @param[in]  tcpip_if Interface which will be stopped
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *         - ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
- */
-esp_err_t tcpip_adapter_stop(tcpip_adapter_if_t tcpip_if);
-
-/**
- * @brief  Cause the TCP/IP stack to bring up an interface
- *
- * @note This function is called automatically by the default event handlers for the Wi-Fi Station and Ethernet interfaces,
- * in response to the SYSTEM_EVENT_STA_CONNECTED and SYSTEM_EVENT_ETH_CONNECTED events, respectively.
- *
- * @note This function is not normally used with Wi-Fi AP interface. If the AP interface is started, it is up.
- *
- * @param[in]  tcpip_if Interface to bring up
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
- */
-esp_err_t tcpip_adapter_up(tcpip_adapter_if_t tcpip_if);
-
-/**
- * @brief Cause the TCP/IP stack to shutdown an interface
- *
- * @note This function is called automatically by the default event handlers for the Wi-Fi Station and Ethernet interfaces,
- * in response to the SYSTEM_EVENT_STA_DISCONNECTED and SYSTEM_EVENT_ETH_DISCONNECTED events, respectively.
- *
- * @note This function is not normally used with Wi-Fi AP interface. If the AP interface is stopped, it is down.
- *
- * @param[in]  tcpip_if Interface to shutdown
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
- */
-esp_err_t tcpip_adapter_down(tcpip_adapter_if_t tcpip_if);
-
-/**
- * @brief  Get interface's IP address information
- *
- * If the interface is up, IP information is read directly from the TCP/IP stack.
- *
- * If the interface is down, IP information is read from a copy kept in the TCP/IP adapter
- * library itself.
- *
- * @param[in]   tcpip_if Interface to get IP information
- * @param[out]  ip_info If successful, IP information will be returned in this argument.
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- */
-esp_err_t tcpip_adapter_get_ip_info(tcpip_adapter_if_t tcpip_if, tcpip_adapter_ip_info_t *ip_info);
-
-/**
- * @brief  Set interface's IP address information
- *
- * This function is mainly used to set a static IP on an interface.
- *
- * If the interface is up, the new IP information is set directly in the TCP/IP stack.
- *
- * The copy of IP information kept in the TCP/IP adapter library is also updated (this
- * copy is returned if the IP is queried while the interface is still down.)
- *
- * @note DHCP client/server must be stopped before setting new IP information.
- *
- * @note Calling this interface for the Wi-Fi STA or Ethernet interfaces may generate a
- * SYSTEM_EVENT_STA_GOT_IP or SYSTEM_EVENT_ETH_GOT_IP event.
- *
- * @param[in] tcpip_if Interface to set IP information
- * @param[in] ip_info IP information to set on the specified interface
- *
- * @return
- *      - ESP_OK
- *      - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *      - ESP_ERR_TCPIP_ADAPTER_DHCP_NOT_STOPPED If DHCP server or client is still running
- */
-esp_err_t tcpip_adapter_set_ip_info(tcpip_adapter_if_t tcpip_if, const tcpip_adapter_ip_info_t *ip_info);
-
-/**
- * @brief  Set DNS Server information
- *
- * This function behaves differently for different interfaces:
- *
- * - For Wi-Fi Station interface and Ethernet interface, up to three types of DNS server can be set (in order of priority):
- *   - Main DNS Server (TCPIP_ADAPTER_DNS_MAIN)
- *   - Backup DNS Server (TCPIP_ADAPTER_DNS_BACKUP)
- *   - Fallback DNS Server (TCPIP_ADAPTER_DNS_FALLBACK)
- *
- *   If DHCP client is enabled, main and backup DNS servers will be updated automatically from the DHCP lease if the relevant DHCP options are set. Fallback DNS Server is never updated from the DHCP lease and is designed to be set via this API.
- *
- *   If DHCP client is disabled, all DNS server types can be set via this API only.
- *
- * - For Wi-Fi AP interface, the Main DNS Server setting is used by the DHCP server to provide a DNS Server option to DHCP clients (Wi-Fi stations).
- *   - The default Main DNS server is the IP of the Wi-Fi AP interface itself.
- *   - This function can override it by setting server type TCPIP_ADAPTER_DNS_MAIN.
- *   - Other DNS Server types are not supported for the Wi-Fi AP interface.
- *
- * @param[in]  tcpip_if Interface to set DNS Server information
- * @param[in]  type Type of DNS Server to set: TCPIP_ADAPTER_DNS_MAIN, TCPIP_ADAPTER_DNS_BACKUP, TCPIP_ADAPTER_DNS_FALLBACK
- * @param[in]  dns  DNS Server address to set
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS invalid params
- */
-esp_err_t tcpip_adapter_set_dns_info(tcpip_adapter_if_t tcpip_if, tcpip_adapter_dns_type_t type, tcpip_adapter_dns_info_t *dns);
-
-/**
- * @brief  Get DNS Server information
- *
- * Return the currently configured DNS Server address for the specified interface and Server type.
- *
- * This may be result of a previous call to tcpip_adapter_set_dns_info(). If the interface's DHCP client is enabled,
- * the Main or Backup DNS Server may be set by the current DHCP lease.
- *
- * @param[in]  tcpip_if Interface to get DNS Server information
- * @param[in]  type Type of DNS Server to get: TCPIP_ADAPTER_DNS_MAIN, TCPIP_ADAPTER_DNS_BACKUP, TCPIP_ADAPTER_DNS_FALLBACK
- * @param[out] dns  DNS Server result is written here on success
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS invalid params
- */
-esp_err_t tcpip_adapter_get_dns_info(tcpip_adapter_if_t tcpip_if, tcpip_adapter_dns_type_t type, tcpip_adapter_dns_info_t *dns);
-
-/**
- * @brief  Get interface's old IP information
- *
- * Returns an "old" IP address previously stored for the interface when the valid IP changed.
- *
- * If the IP lost timer has expired (meaning the interface was down for longer than the configured interval)
- * then the old IP information will be zero.
- *
- * @param[in]   tcpip_if Interface to get old IP information
- * @param[out]  ip_info If successful, IP information will be returned in this argument.
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- */
-esp_err_t tcpip_adapter_get_old_ip_info(tcpip_adapter_if_t tcpip_if, tcpip_adapter_ip_info_t *ip_info);
-
-/**
- * @brief  Set interface old IP information
- *
- * This function is called from the DHCP client for the Wi-Fi STA and Ethernet interfaces, before a new IP is set. It is also called from the default handlers for the SYSTEM_EVENT_STA_CONNECTED and SYSTEM_EVENT_ETH_CONNECTED events.
- *
- * Calling this function stores the previously configured IP, which can be used to determine if the IP changes in the future.
- *
- * If the interface is disconnected or down for too long, the "IP lost timer" will expire (after the configured interval) and set the old IP information to zero.
- *
- * @param[in]  tcpip_if Interface to set old IP information
- * @param[in]  ip_info Store the old IP information for the specified interface
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- */
-esp_err_t tcpip_adapter_set_old_ip_info(tcpip_adapter_if_t tcpip_if, const tcpip_adapter_ip_info_t *ip_info);
-
-
-/**
- * @brief  Create interface link-local IPv6 address
- *
- * Cause the TCP/IP stack to create a link-local IPv6 address for the specified interface.
- *
- * This function also registers a callback for the specified interface, so that if the link-local address becomes verified as the preferred address then a SYSTEM_EVENT_GOT_IP6 event will be sent.
- *
- * @param[in]  tcpip_if Interface to create a link-local IPv6 address
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- */
-esp_err_t tcpip_adapter_create_ip6_linklocal(tcpip_adapter_if_t tcpip_if);
-
-/**
- * @brief  Get interface link-local IPv6 address
- *
- * If the specified interface is up and a preferred link-local IPv6 address
- * has been created for the interface, return a copy of it.
- *
- * @param[in]  tcpip_if Interface to get link-local IPv6 address
- * @param[out] if_ip6 IPv6 information will be returned in this argument if successful.
- *
- * @return
- *      - ESP_OK
- *      - ESP_FAIL If interface is down, does not have a link-local IPv6 address, or the link-local IPv6 address is not a preferred address.
- */
-esp_err_t tcpip_adapter_get_ip6_linklocal(tcpip_adapter_if_t tcpip_if, ip6_addr_t *if_ip6);
-
-/**
- * @brief  Get interface global IPv6 address
- *
- * If the specified interface is up and a preferred global IPv6 address
- * has been created for the interface, return a copy of it.
- *
- * @param[in]  tcpip_if Interface to get global IPv6 address
- * @param[out] if_ip6 IPv6 information will be returned in this argument if successful.
- *
- * @return
- *      - ESP_OK
- *      - ESP_FAIL If interface is down, does not have a global IPv6 address.
- */
-esp_err_t tcpip_adapter_get_ip6_global(tcpip_adapter_if_t tcpip_if, ip6_addr_t *if_ip6);
-
-#if 0
-esp_err_t tcpip_adapter_get_mac(tcpip_adapter_if_t tcpip_if, uint8_t *mac);
-
-esp_err_t tcpip_adapter_set_mac(tcpip_adapter_if_t tcpip_if, uint8_t *mac);
-#endif
-
-/**
- * @brief  Get DHCP Server status
- *
- * @param[in]   tcpip_if Interface to get status of DHCP server.
- * @param[out]  status If successful, the status of the DHCP server will be returned in this argument.
- *
- * @return
- *         - ESP_OK
- */
-esp_err_t tcpip_adapter_dhcps_get_status(tcpip_adapter_if_t tcpip_if, tcpip_adapter_dhcp_status_t *status);
-
-/**
- * @brief  Set or Get DHCP server option
- *
- * @param[in] opt_op TCPIP_ADAPTER_OP_SET to set an option, TCPIP_ADAPTER_OP_GET to get an option.
- * @param[in] opt_id Option index to get or set, must be one of the supported enum values.
- * @param[inout] opt_val Pointer to the option parameter.
- * @param[in] opt_len Length of the option parameter.
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *         - ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPPED
- *         - ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED
- */
-esp_err_t tcpip_adapter_dhcps_option(tcpip_adapter_dhcp_option_mode_t opt_op, tcpip_adapter_dhcp_option_id_t opt_id, void *opt_val, uint32_t opt_len);
-
-/**
- * @brief  Start DHCP server
- *
- * @note   Currently DHCP server is only supported on the Wi-Fi AP interface.
- *
- * @param[in]  tcpip_if Interface to start DHCP server. Must be TCPIP_ADAPTER_IF_AP.
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *         - ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED
- */
-esp_err_t tcpip_adapter_dhcps_start(tcpip_adapter_if_t tcpip_if);
-
-/**
- * @brief  Stop DHCP server
- *
- * @note   Currently DHCP server is only supported on the Wi-Fi AP interface.
- *
- * @param[in]  tcpip_if Interface to stop DHCP server. Must be TCPIP_ADAPTER_IF_AP.
- *
- * @return
- *      - ESP_OK
- *      - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *      - ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPPED
- *      - ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
- */
-esp_err_t tcpip_adapter_dhcps_stop(tcpip_adapter_if_t tcpip_if);
-
-/**
- * @brief  Get DHCP client status
- *
- * @param[in]  tcpip_if Interface to get status of DHCP client
- * @param[out] status If successful, the status of DHCP client will be returned in this argument.
- *
- * @return
- *         - ESP_OK
- */
-esp_err_t tcpip_adapter_dhcpc_get_status(tcpip_adapter_if_t tcpip_if, tcpip_adapter_dhcp_status_t *status);
-
-/**
- * @brief  Set or Get DHCP client's option
- *
- * @note This function is not yet implemented
- *
- * @param[in] opt_op TCPIP_ADAPTER_OP_SET to set an option, TCPIP_ADAPTER_OP_GET to get an option.
- * @param[in] opt_id Option index to get or set, must be one of the supported enum values.
- * @param[inout] opt_val Pointer to the option parameter.
- * @param[in] opt_len Length of the option parameter.
- *
- * @return
- *         - ESP_ERR_NOT_SUPPORTED (not implemented)
- */
-esp_err_t tcpip_adapter_dhcpc_option(tcpip_adapter_dhcp_option_mode_t opt_op, tcpip_adapter_dhcp_option_id_t opt_id, void *opt_val, uint32_t opt_len);
-
-/**
- * @brief Start DHCP client
- *
- * @note DHCP Client is only supported for the Wi-Fi station and Ethernet interfaces.
- *
- * @note The default event handlers for the SYSTEM_EVENT_STA_CONNECTED and SYSTEM_EVENT_ETH_CONNECTED events call this function.
- *
- * @param[in]  tcpip_if Interface to start the DHCP client
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *         - ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STARTED
- *         - ESP_ERR_TCPIP_ADAPTER_DHCPC_START_FAILED
- */
-esp_err_t tcpip_adapter_dhcpc_start(tcpip_adapter_if_t tcpip_if);
-
-/**
- * @brief  Stop DHCP client
- *
- * @note DHCP Client is only supported for the Wi-Fi station and Ethernet interfaces.
- *
- * @note Calling tcpip_adapter_stop() or tcpip_adapter_down() will also stop the DHCP Client if it is running.
- *
- * @param[in] tcpip_if Interface to stop the DHCP client
- *
- * @return
- *      - ESP_OK
- *      - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- *      - ESP_ERR_TCPIP_ADAPTER_DHCP_ALREADY_STOPPED
- *      - ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY
- */
-esp_err_t tcpip_adapter_dhcpc_stop(tcpip_adapter_if_t tcpip_if);
-
-/**
- * @brief  Receive an Ethernet frame from the Ethernet interface
- *
- * This function will automatically be installed by esp_eth_init(). The Ethernet driver layer will then call this function to forward frames to the TCP/IP stack.
- *
- * @note Application code does not usually need to use this function directly.
- *
- * @param[in]  buffer Received data
- * @param[in]  len Length of the data frame
- * @param[in]  eb Pointer to internal Wi-Fi buffer (ignored for Ethernet)
- *
- * @return
- *         - ESP_OK
- */
-esp_err_t tcpip_adapter_eth_input(void *buffer, uint16_t len, void *eb);
-
-/**
- * @brief  Receive an 802.11 data frame from the Wi-Fi Station interface
- *
- * This function should be installed by calling esp_wifi_reg_rxcb(). The Wi-Fi driver layer will then call this function to forward frames to the TCP/IP stack.
- *
- * @note Installation happens automatically in the default handler for the SYSTEM_EVENT_STA_CONNECTED event.
- *
- * @note Application code does not usually need to call this function directly.
- *
- * @param[in]  buffer Received data
- * @param[in]  len Length of the data frame
- * @param[in]  eb Pointer to internal Wi-Fi buffer
- *
- * @return
- *         - ESP_OK
- */
-esp_err_t tcpip_adapter_sta_input(void *buffer, uint16_t len, void *eb);
-
-/**
- * @brief  Receive an 802.11 data frame from the Wi-Fi AP interface
- *
- * This function should be installed by calling esp_wifi_reg_rxcb(). The Wi-Fi driver layer will then call this function to forward frames to the TCP/IP stack.
- *
- * @note Installation happens automatically in the default handler for the SYSTEM_EVENT_AP_START event.
- *
- * @note Application code does not usually need to call this function directly.
- *
- * @param[in]  buffer Received data
- * @param[in]  len Length of the data frame
- * @param[in]  eb Pointer to internal Wi-Fi buffer
- *
- * @return
- *         - ESP_OK
- */
-esp_err_t tcpip_adapter_ap_input(void *buffer, uint16_t len, void *eb);
-
-/**
- * @brief  Get network interface index
- *
- * Get network interface from TCP/IP implementation-specific interface pointer.
- *
- * @param[in]  dev Implementation-specific TCP/IP stack interface pointer.
- *
- * @return
- *         - ESP_IF_WIFI_STA
- *         - ESP_IF_WIFI_AP
- *         - ESP_IF_ETH
- *         - ESP_IF_MAX - invalid parameter
- */
-esp_interface_t tcpip_adapter_get_esp_if(void *dev);
-
-/**
- * @brief  Get IP information for stations connected to the Wi-Fi AP interface
- *
- * @param[in]   wifi_sta_list Wi-Fi station info list, returned from esp_wifi_ap_get_sta_list()
- * @param[out]  tcpip_sta_list IP layer station info list, corresponding to MAC addresses provided in wifi_sta_list
- *
- * @return
- *         - ESP_OK
- *         - ESP_ERR_TCPIP_ADAPTER_NO_MEM
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS
- */
-esp_err_t tcpip_adapter_get_sta_list(const wifi_sta_list_t *wifi_sta_list, tcpip_adapter_sta_list_t *tcpip_sta_list);
-
-#define TCPIP_HOSTNAME_MAX_SIZE    32
-/**
- * @brief  Set the hostname of an interface
- *
- * @param[in]   tcpip_if Interface to set the hostname
- * @param[in]   hostname New hostname for the interface. Maximum length 32 bytes.
- *
- * @return
- *         - ESP_OK - success
- *         - ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY - interface status error
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS - parameter error
- */
-esp_err_t tcpip_adapter_set_hostname(tcpip_adapter_if_t tcpip_if, const char *hostname);
-
-/**
- * @brief  Get interface hostname.
- *
- * @param[in]   tcpip_if Interface to get the hostname
- * @param[out]   hostname Returns a pointer to the hostname. May be NULL if no hostname is set. If set non-NULL, pointer remains valid (and string may change if the hostname changes).
- *
- * @return
- *         - ESP_OK - success
- *         - ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY - interface status error
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS - parameter error
- */
-esp_err_t tcpip_adapter_get_hostname(tcpip_adapter_if_t tcpip_if, const char **hostname);
-
-/**
- * @brief  Get the TCP/IP stack-specific interface that is assigned to a given interface
- *
- * @note For lwIP, this returns a pointer to a netif structure.
- *
- * @param[in]  tcpip_if Interface to get the implementation-specific interface
- * @param[out] netif Pointer to the implementation-specific interface
- *
- * @return
- *         - ESP_OK - success
- *         - ESP_ERR_TCPIP_ADAPTER_IF_NOT_READY - interface status error
- *         - ESP_ERR_TCPIP_ADAPTER_INVALID_PARAMS - parameter error
- */
-esp_err_t tcpip_adapter_get_netif(tcpip_adapter_if_t tcpip_if, void ** netif);
-
-/**
- * @brief  Test if supplied interface is up or down
- *
- * @param[in]   tcpip_if Interface to test up/down status
- *
- * @return
- *         - true - Interface is up
- *         - false - Interface is down
- */
-bool tcpip_adapter_is_netif_up(tcpip_adapter_if_t tcpip_if);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*  _TCPIP_ADAPTER_H_ */
diff --git a/tools/sdk/include/tcpip_adapter/tcpip_adapter_internal.h b/tools/sdk/include/tcpip_adapter/tcpip_adapter_internal.h
deleted file mode 100644
index 93dfdeedcea..00000000000
--- a/tools/sdk/include/tcpip_adapter/tcpip_adapter_internal.h
+++ /dev/null
@@ -1,66 +0,0 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "tcpip_adapter.h"
-#include "rom/queue.h"
-
-struct tcpip_adapter_api_msg_s;
-
-typedef int (*tcpip_adapter_api_fn)(struct tcpip_adapter_api_msg_s *msg);
-
-typedef struct tcpip_adapter_api_msg_s {
-    int type;  /**< The first field MUST be int */
-    int ret;
-    tcpip_adapter_api_fn api_fn;
-    tcpip_adapter_if_t tcpip_if;
-    tcpip_adapter_ip_info_t *ip_info;
-    uint8_t *mac;
-    void    *data;
-} tcpip_adapter_api_msg_t;
-
-typedef struct tcpip_adapter_dns_param_s {
-    tcpip_adapter_dns_type_t dns_type;
-    tcpip_adapter_dns_info_t *dns_info;
-} tcpip_adapter_dns_param_t;
-
-typedef struct tcpip_adapter_ip_lost_timer_s {
-    bool timer_running;
-} tcpip_adapter_ip_lost_timer_t;
-
-
-#define TCPIP_ADAPTER_TRHEAD_SAFE 1
-#define TCPIP_ADAPTER_IPC_LOCAL   0
-#define TCPIP_ADAPTER_IPC_REMOTE  1
-
-#define TCPIP_ADAPTER_IPC_CALL(_if, _mac, _ip, _data, _fn) do {\
-    tcpip_adapter_api_msg_t msg;\
-    if (tcpip_inited == false) {\
-        ESP_LOGE(TAG, "tcpip_adapter is not initialized!");\
-        abort();\
-    }\
-    memset(&msg, 0, sizeof(msg));\
-    msg.tcpip_if = (_if);\
-    msg.mac      = (uint8_t*)(_mac);\
-    msg.ip_info  = (tcpip_adapter_ip_info_t*)(_ip);\
-    msg.data     = (void*)(_data);\
-    msg.api_fn   = (_fn);\
-    if (TCPIP_ADAPTER_IPC_REMOTE == tcpip_adapter_ipc_check(&msg)) {\
-        ESP_LOGV(TAG, "check: remote, if=%d fn=%p\n", (_if), (_fn));\
-        return msg.ret;\
-    } else {\
-        ESP_LOGV(TAG, "check: local, if=%d fn=%p\n", (_if), (_fn));\
-    }\
-} while(0)
diff --git a/tools/sdk/include/ulp/esp32/ulp.h b/tools/sdk/include/ulp/esp32/ulp.h
deleted file mode 100644
index c9ca5110179..00000000000
--- a/tools/sdk/include/ulp/esp32/ulp.h
+++ /dev/null
@@ -1,920 +0,0 @@
-// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-#include <stdint.h>
-#include <stddef.h>
-#include <stdlib.h>
-#include "esp_err.h"
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ULP_FSM_PREPARE_SLEEP_CYCLES 2    /*!< Cycles spent by FSM preparing ULP for sleep */
-#define ULP_FSM_WAKEUP_SLEEP_CYCLES  2    /*!< Cycles spent by FSM waking up ULP from sleep */
-
-/**
- * @defgroup ulp_registers ULP coprocessor registers
- * @{
- */
-
-
-#define R0 0    /*!< general purpose register 0 */
-#define R1 1    /*!< general purpose register 1 */
-#define R2 2    /*!< general purpose register 2 */
-#define R3 3    /*!< general purpose register 3 */
-/**@}*/
-
-/** @defgroup ulp_opcodes ULP coprocessor opcodes, sub opcodes, and various modifiers/flags
- *
- * These definitions are not intended to be used directly.
- * They are used in definitions of instructions later on.
- *
- * @{
- */
-
-#define OPCODE_WR_REG 1         /*!< Instruction: write peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */
-
-#define OPCODE_RD_REG 2         /*!< Instruction: read peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */
-
-#define RD_REG_PERIPH_RTC_CNTL 0    /*!< Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions */
-#define RD_REG_PERIPH_RTC_IO   1    /*!< Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions */
-#define RD_REG_PERIPH_SENS     2    /*!< Identifier of SARADC peripheral for RD_REG and WR_REG instructions */
-#define RD_REG_PERIPH_RTC_I2C  3    /*!< Identifier of RTC_I2C peripheral for RD_REG and WR_REG instructions */
-
-#define OPCODE_I2C 3            /*!< Instruction: read/write I2C (not implemented yet) */
-
-#define OPCODE_DELAY 4          /*!< Instruction: delay (nop) for a given number of cycles */
-
-#define OPCODE_ADC 5            /*!< Instruction: SAR ADC measurement (not implemented yet) */
-
-#define OPCODE_ST 6             /*!< Instruction: store indirect to RTC memory */
-#define SUB_OPCODE_ST 4         /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */
-
-#define OPCODE_ALU 7            /*!< Arithmetic instructions */
-#define SUB_OPCODE_ALU_REG 0    /*!< Arithmetic instruction, both source values are in register */
-#define SUB_OPCODE_ALU_IMM 1    /*!< Arithmetic instruction, one source value is an immediate */
-#define SUB_OPCODE_ALU_CNT 2    /*!< Arithmetic instruction between counter register and an immediate (not implemented yet)*/
-#define ALU_SEL_ADD 0           /*!< Addition */
-#define ALU_SEL_SUB 1           /*!< Subtraction */
-#define ALU_SEL_AND 2           /*!< Logical AND */
-#define ALU_SEL_OR  3           /*!< Logical OR */
-#define ALU_SEL_MOV 4           /*!< Copy value (immediate to destination register or source register to destination register */
-#define ALU_SEL_LSH 5           /*!< Shift left by given number of bits */
-#define ALU_SEL_RSH 6           /*!< Shift right by given number of bits */
-
-#define OPCODE_BRANCH 8         /*!< Branch instructions */
-#define SUB_OPCODE_BX  0        /*!< Branch to absolute PC (immediate or in register) */
-#define BX_JUMP_TYPE_DIRECT 0   /*!< Unconditional jump */
-#define BX_JUMP_TYPE_ZERO 1     /*!< Branch if last ALU result is zero */
-#define BX_JUMP_TYPE_OVF 2      /*!< Branch if last ALU operation caused and overflow */
-#define SUB_OPCODE_B  1         /*!< Branch to a relative offset */
-#define B_CMP_L 0               /*!< Branch if R0 is less than an immediate */
-#define B_CMP_GE 1              /*!< Branch if R0 is greater than or equal to an immediate */
-
-#define OPCODE_END 9            /*!< Stop executing the program */
-#define SUB_OPCODE_END 0        /*!< Stop executing the program and optionally wake up the chip */
-#define SUB_OPCODE_SLEEP 1      /*!< Stop executing the program and run it again after selected interval */
-
-#define OPCODE_TSENS 10         /*!< Instruction: temperature sensor measurement (not implemented yet) */
-
-#define OPCODE_HALT 11          /*!< Halt the coprocessor */
-
-#define OPCODE_LD 13            /*!< Indirect load lower 16 bits from RTC memory */
-
-#define OPCODE_MACRO 15         /*!< Not a real opcode. Used to identify labels and branches in the program */
-#define SUB_OPCODE_MACRO_LABEL 0    /*!< Label macro */
-#define SUB_OPCODE_MACRO_BRANCH 1   /*!< Branch macro */
-/**@}*/
-
-/**@{*/
-#define ESP_ERR_ULP_BASE                0x1200                  /*!< Offset for ULP-related error codes */
-#define ESP_ERR_ULP_SIZE_TOO_BIG        (ESP_ERR_ULP_BASE + 1)  /*!< Program doesn't fit into RTC memory reserved for the ULP */
-#define ESP_ERR_ULP_INVALID_LOAD_ADDR   (ESP_ERR_ULP_BASE + 2)  /*!< Load address is outside of RTC memory reserved for the ULP */
-#define ESP_ERR_ULP_DUPLICATE_LABEL     (ESP_ERR_ULP_BASE + 3)  /*!< More than one label with the same number was defined */
-#define ESP_ERR_ULP_UNDEFINED_LABEL     (ESP_ERR_ULP_BASE + 4)  /*!< Branch instructions references an undefined label */
-#define ESP_ERR_ULP_BRANCH_OUT_OF_RANGE (ESP_ERR_ULP_BASE + 5)  /*!< Branch target is out of range of B instruction (try replacing with BX) */
-/**@}*/
-
-
-/**
- * @brief Instruction format structure
- *
- * All ULP instructions are 32 bit long.
- * This union contains field layouts used by all of the supported instructions.
- * This union also includes a special "macro" instruction layout.
- * This is not a real instruction which can be executed by the CPU. It acts
- * as a token which is removed from the program by the
- * ulp_process_macros_and_load function.
- *
- * These structures are not intended to be used directly.
- * Preprocessor definitions provided below fill the fields of these structure with
- * the right arguments.
- */
-typedef union {
-
-    struct {
-        uint32_t cycles : 16;       /*!< Number of cycles to sleep */
-        uint32_t unused : 12;       /*!< Unused */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_DELAY) */
-    } delay;                        /*!< Format of DELAY instruction */
-
-    struct {
-        uint32_t dreg : 2;          /*!< Register which contains data to store */
-        uint32_t sreg : 2;          /*!< Register which contains address in RTC memory (expressed in words) */
-        uint32_t unused1 : 6;       /*!< Unused */
-        uint32_t offset : 11;       /*!< Offset to add to sreg */
-        uint32_t unused2 : 4;       /*!< Unused */
-        uint32_t sub_opcode : 3;    /*!< Sub opcode (SUB_OPCODE_ST) */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_ST) */
-    } st;                           /*!< Format of ST instruction */
-
-    struct {
-        uint32_t dreg : 2;          /*!< Register where the data should be loaded to */
-        uint32_t sreg : 2;          /*!< Register which contains address in RTC memory (expressed in words) */
-        uint32_t unused1 : 6;       /*!< Unused */
-        uint32_t offset : 11;       /*!< Offset to add to sreg */
-        uint32_t unused2 : 7;       /*!< Unused */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_LD) */
-    } ld;                           /*!< Format of LD instruction */
-
-    struct {
-        uint32_t unused : 28;       /*!< Unused */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_HALT) */
-    } halt;                         /*!< Format of HALT instruction */
-
-    struct {
-        uint32_t dreg : 2;          /*!< Register which contains target PC, expressed in words (used if .reg == 1) */
-        uint32_t addr : 11;         /*!< Target PC, expressed in words (used if .reg == 0) */
-        uint32_t unused : 8;        /*!< Unused */
-        uint32_t reg : 1;           /*!< Target PC in register (1) or immediate (0) */
-        uint32_t type : 3;          /*!< Jump condition (BX_JUMP_TYPE_xxx) */
-        uint32_t sub_opcode : 3;    /*!< Sub opcode (SUB_OPCODE_BX) */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_BRANCH) */
-    } bx;                           /*!< Format of BRANCH instruction (absolute address) */
-
-    struct {
-        uint32_t imm : 16;          /*!< Immediate value to compare against */
-        uint32_t cmp : 1;           /*!< Comparison to perform: B_CMP_L or B_CMP_GE */
-        uint32_t offset : 7;        /*!< Absolute value of target PC offset w.r.t. current PC, expressed in words */
-        uint32_t sign : 1;          /*!< Sign of target PC offset: 0: positive, 1: negative */
-        uint32_t sub_opcode : 3;    /*!< Sub opcode (SUB_OPCODE_B) */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_BRANCH) */
-    } b;                            /*!< Format of BRANCH instruction (relative address) */
-
-    struct {
-        uint32_t dreg : 2;          /*!< Destination register */
-        uint32_t sreg : 2;          /*!< Register with operand A */
-        uint32_t treg : 2;          /*!< Register with operand B */
-        uint32_t unused : 15;       /*!< Unused */
-        uint32_t sel : 4;           /*!< Operation to perform, one of ALU_SEL_xxx */
-        uint32_t sub_opcode : 3;    /*!< Sub opcode (SUB_OPCODE_ALU_REG) */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_ALU) */
-    } alu_reg;                      /*!< Format of ALU instruction (both sources are registers) */
-
-    struct {
-        uint32_t dreg : 2;          /*!< Destination register */
-        uint32_t sreg : 2;          /*!< Register with operand A */
-        uint32_t imm : 16;          /*!< Immediate value of operand B */
-        uint32_t unused : 1;        /*!< Unused */
-        uint32_t sel : 4;           /*!< Operation to perform, one of ALU_SEL_xxx */
-        uint32_t sub_opcode : 3;    /*!< Sub opcode (SUB_OPCODE_ALU_IMM) */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_ALU) */
-    } alu_imm;                      /*!< Format of ALU instruction (one source is an immediate) */
-
-    struct {
-        uint32_t addr : 8;          /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */
-        uint32_t periph_sel : 2;    /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */
-        uint32_t data : 8;          /*!< 8 bits of data to write */
-        uint32_t low : 5;           /*!< Low bit */
-        uint32_t high : 5;          /*!< High bit */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_WR_REG) */
-    } wr_reg;                       /*!< Format of WR_REG instruction */
-
-    struct {
-        uint32_t addr : 8;          /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */
-        uint32_t periph_sel : 2;    /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */
-        uint32_t unused : 8;        /*!< Unused */
-        uint32_t low : 5;           /*!< Low bit */
-        uint32_t high : 5;          /*!< High bit */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_WR_REG) */
-    } rd_reg;                       /*!< Format of RD_REG instruction */
-
-    struct {
-        uint32_t dreg : 2;          /*!< Register where to store ADC result */
-        uint32_t mux : 4;           /*!< Select SARADC pad (mux + 1) */
-        uint32_t sar_sel : 1;       /*!< Select SARADC0 (0) or SARADC1 (1) */
-        uint32_t unused1 : 1;       /*!< Unused */
-        uint32_t cycles : 16;       /*!< TBD, cycles used for measurement */
-        uint32_t unused2 : 4;       /*!< Unused */
-        uint32_t opcode: 4;         /*!< Opcode (OPCODE_ADC) */
-    } adc;                          /*!< Format of ADC instruction */
-
-    struct {
-        uint32_t dreg : 2;          /*!< Register where to store temperature measurement result */
-        uint32_t wait_delay: 14;    /*!< Cycles to wait after measurement is done */
-        uint32_t reserved: 12;      /*!< Reserved, set to 0 */
-        uint32_t opcode: 4;         /*!< Opcode (OPCODE_TSENS) */
-    } tsens;                        /*!< Format of TSENS instruction */
-
-    struct {
-        uint32_t i2c_addr : 8;      /*!< I2C slave address */
-        uint32_t data : 8;          /*!< Data to read or write */
-        uint32_t low_bits : 3;      /*!< TBD */
-        uint32_t high_bits : 3;     /*!< TBD */
-        uint32_t i2c_sel : 4;       /*!< TBD, select reg_i2c_slave_address[7:0] */
-        uint32_t unused : 1;        /*!< Unused */
-        uint32_t rw : 1;            /*!< Write (1) or read (0) */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_I2C) */
-    } i2c;                          /*!< Format of I2C instruction */
-
-    struct {
-        uint32_t wakeup : 1;        /*!< Set to 1 to wake up chip */
-        uint32_t unused : 24;       /*!< Unused */
-        uint32_t sub_opcode : 3;    /*!< Sub opcode (SUB_OPCODE_WAKEUP) */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_END) */
-    } end;                          /*!< Format of END instruction with wakeup */
-
-    struct {
-        uint32_t cycle_sel : 4;     /*!< Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from */
-        uint32_t unused : 21;       /*!< Unused */
-        uint32_t sub_opcode : 3;    /*!< Sub opcode (SUB_OPCODE_SLEEP) */
-        uint32_t opcode : 4;        /*!< Opcode (OPCODE_END) */
-    } sleep;                        /*!< Format of END instruction with sleep */
-
-    struct {
-        uint32_t label : 16;        /*!< Label number */
-        uint32_t unused : 8;        /*!< Unused */
-        uint32_t sub_opcode : 4;    /*!< SUB_OPCODE_MACRO_LABEL or SUB_OPCODE_MACRO_BRANCH */
-        uint32_t opcode: 4;         /*!< Opcode (OPCODE_MACRO) */
-    } macro;                        /*!< Format of tokens used by LABEL and BRANCH macros */
-
-} ulp_insn_t;
-
-_Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should be 4 bytes");
-
-/**
- * Delay (nop) for a given number of cycles
- */
-#define I_DELAY(cycles_) { .delay = {\
-    .cycles = cycles_, \
-    .unused = 0, \
-    .opcode = OPCODE_DELAY } }
-
-/**
- * Halt the coprocessor.
- *
- * This instruction halts the coprocessor, but keeps ULP timer active.
- * As such, ULP program will be restarted again by timer.
- * To stop the program and prevent the timer from restarting the program,
- * use I_END(0) instruction.
- */
-#define I_HALT() { .halt = {\
-    .unused = 0, \
-    .opcode = OPCODE_HALT } }
-
-/**
- * Map SoC peripheral register to periph_sel field of RD_REG and WR_REG
- * instructions.
- *
- * @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals.
- * @return periph_sel value for the peripheral to which this register belongs.
- */
-static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
-    uint32_t ret = 3;
-    if (reg < DR_REG_RTCCNTL_BASE) {
-        assert(0 && "invalid register base");
-    } else if (reg < DR_REG_RTCIO_BASE) {
-        ret = RD_REG_PERIPH_RTC_CNTL;
-    } else if (reg < DR_REG_SENS_BASE) {
-        ret = RD_REG_PERIPH_RTC_IO;
-    } else if (reg < DR_REG_RTC_I2C_BASE){
-        ret = RD_REG_PERIPH_SENS;
-    } else if (reg < DR_REG_IO_MUX_BASE){
-        ret = RD_REG_PERIPH_RTC_I2C;
-    } else {
-        assert(0 && "invalid register base");
-    }
-    return ret;
-}
-
-/**
- * Write literal value to a peripheral register
- *
- * reg[high_bit : low_bit] = val
- * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
- */
-#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
-    .addr = (reg & 0xff) / sizeof(uint32_t), \
-    .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
-    .data = val, \
-    .low = low_bit, \
-    .high = high_bit, \
-    .opcode = OPCODE_WR_REG } }
-
-/**
- * Read from peripheral register into R0
- *
- * R0 = reg[high_bit : low_bit]
- * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
- */
-#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
-    .addr = (reg & 0xff) / sizeof(uint32_t), \
-    .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
-    .unused = 0, \
-    .low = low_bit, \
-    .high = high_bit, \
-    .opcode = OPCODE_RD_REG } }
-
-/**
- * Set or clear a bit in the peripheral register.
- *
- * Sets bit (1 << shift) of register reg to value val.
- * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
- */
-#define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val)
-
-/**
- * Wake the SoC from deep sleep.
- *
- * This instruction initiates wake up from deep sleep.
- * Use esp_deep_sleep_enable_ulp_wakeup to enable deep sleep wakeup
- * triggered by the ULP before going into deep sleep.
- * Note that ULP program will still keep running until the I_HALT
- * instruction, and it will still be restarted by timer at regular
- * intervals, even when the SoC is woken up.
- *
- * To stop the ULP program, use I_HALT instruction.
- *
- * To disable the timer which start ULP program, use I_END()
- * instruction. I_END instruction clears the
- * RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG
- * register, which controls the ULP timer.
- */
-#define I_WAKE() { .end = { \
-        .wakeup = 1, \
-        .unused = 0, \
-        .sub_opcode = SUB_OPCODE_END, \
-        .opcode = OPCODE_END } }
-
-/**
- * Stop ULP program timer.
- *
- * This is a convenience macro which disables the ULP program timer.
- * Once this instruction is used, ULP program will not be restarted
- * anymore until ulp_run function is called.
- *
- * ULP program will continue running after this instruction. To stop
- * the currently running program, use I_HALT().
- */
-#define I_END() \
-    I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
-/**
- * Select the time interval used to run ULP program.
- *
- * This instructions selects which of the SENS_SLEEP_CYCLES_Sx
- * registers' value is used by the ULP program timer.
- * When the ULP program stops at I_HALT instruction, ULP program
- * timer start counting. When the counter reaches the value of
- * the selected SENS_SLEEP_CYCLES_Sx register, ULP program
- * start running again from the start address (passed to the ulp_run
- * function).
- * There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5.
- *
- * By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP
- * program timer.
- */
-#define I_SLEEP_CYCLE_SEL(timer_idx) { .sleep = { \
-        .cycle_sel = timer_idx, \
-        .unused = 0, \
-        .sub_opcode = SUB_OPCODE_SLEEP, \
-        .opcode = OPCODE_END } }
-
-/**
- * Perform temperature sensor measurement and store it into reg_dest.
- *
- * Delay can be set between 1 and ((1 << 14) - 1). Higher values give
- * higher measurement resolution.
- */
-#define I_TSENS(reg_dest, delay) { .tsens = { \
-        .dreg = reg_dest, \
-        .wait_delay = delay, \
-        .reserved = 0, \
-        .opcode = OPCODE_TSENS } }
-
-/**
- * Perform ADC measurement and store result in reg_dest.
- *
- * adc_idx selects ADC (0 or 1).
- * pad_idx selects ADC pad (0 - 7).
- */
-#define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\
-        .dreg = reg_dest, \
-        .mux = pad_idx + 1, \
-        .sar_sel = adc_idx, \
-        .unused1 = 0, \
-        .cycles = 0, \
-        .unused2 = 0, \
-        .opcode = OPCODE_ADC } }
-
-/**
- * Store value from register reg_val into RTC memory.
- *
- * The value is written to an offset calculated by adding value of
- * reg_addr register and offset_ field (this offset is expressed in 32-bit words).
- * 32 bits written to RTC memory are built as follows:
- * - bits [31:21] hold the PC of current instruction, expressed in 32-bit words
- * - bits [20:16] = 5'b1
- * - bits [15:0] are assigned the contents of reg_val
- *
- * RTC_SLOW_MEM[addr + offset_] = { 5'b0, insn_PC[10:0], val[15:0] }
- */
-#define I_ST(reg_val, reg_addr, offset_) { .st = { \
-    .dreg = reg_val, \
-    .sreg = reg_addr, \
-    .unused1 = 0, \
-    .offset = offset_, \
-    .unused2 = 0, \
-    .sub_opcode = SUB_OPCODE_ST, \
-    .opcode = OPCODE_ST } }
-
-
-/**
- * Load value from RTC memory into reg_dest register.
- *
- * Loads 16 LSBs from RTC memory word given by the sum of value in reg_addr and
- * value of offset_.
- */
-#define I_LD(reg_dest, reg_addr, offset_) { .ld = { \
-    .dreg = reg_dest, \
-    .sreg = reg_addr, \
-    .unused1 = 0, \
-    .offset = offset_, \
-    .unused2 = 0, \
-    .opcode = OPCODE_LD } }
-
-
-/**
- *  Branch relative if R0 less than immediate value.
- *
- *  pc_offset is expressed in words, and can be from -127 to 127
- *  imm_value is a 16-bit value to compare R0 against
- */
-#define I_BL(pc_offset, imm_value) { .b = { \
-    .imm = imm_value, \
-    .cmp = B_CMP_L, \
-    .offset = abs(pc_offset), \
-    .sign = (pc_offset >= 0) ? 0 : 1, \
-    .sub_opcode = SUB_OPCODE_B, \
-    .opcode = OPCODE_BRANCH } }
-
-/**
- *  Branch relative if R0 greater or equal than immediate value.
- *
- *  pc_offset is expressed in words, and can be from -127 to 127
- *  imm_value is a 16-bit value to compare R0 against
- */
-#define I_BGE(pc_offset, imm_value) { .b = { \
-    .imm = imm_value, \
-    .cmp = B_CMP_GE, \
-    .offset = abs(pc_offset), \
-    .sign = (pc_offset >= 0) ? 0 : 1, \
-    .sub_opcode = SUB_OPCODE_B, \
-    .opcode = OPCODE_BRANCH } }
-
-/**
- * Unconditional branch to absolute PC, address in register.
- *
- * reg_pc is the register which contains address to jump to.
- * Address is expressed in 32-bit words.
- */
-#define I_BXR(reg_pc) { .bx = { \
-    .dreg = reg_pc, \
-    .addr = 0, \
-    .unused = 0, \
-    .reg = 1, \
-    .type = BX_JUMP_TYPE_DIRECT, \
-    .sub_opcode = SUB_OPCODE_BX, \
-    .opcode = OPCODE_BRANCH } }
-
-/**
- *  Unconditional branch to absolute PC, immediate address.
- *
- *  Address imm_pc is expressed in 32-bit words.
- */
-#define I_BXI(imm_pc) { .bx = { \
-    .dreg = 0, \
-    .addr = imm_pc, \
-    .unused = 0, \
-    .reg = 0, \
-    .type = BX_JUMP_TYPE_DIRECT, \
-    .sub_opcode = SUB_OPCODE_BX, \
-    .opcode = OPCODE_BRANCH } }
-
-/**
- * Branch to absolute PC if ALU result is zero, address in register.
- *
- * reg_pc is the register which contains address to jump to.
- * Address is expressed in 32-bit words.
- */
-#define I_BXZR(reg_pc) { .bx = { \
-    .dreg = reg_pc, \
-    .addr = 0, \
-    .unused = 0, \
-    .reg = 1, \
-    .type = BX_JUMP_TYPE_ZERO, \
-    .sub_opcode = SUB_OPCODE_BX, \
-    .opcode = OPCODE_BRANCH } }
-
-/**
- * Branch to absolute PC if ALU result is zero, immediate address.
- *
- * Address imm_pc is expressed in 32-bit words.
- */
-#define I_BXZI(imm_pc) { .bx = { \
-    .dreg = 0, \
-    .addr = imm_pc, \
-    .unused = 0, \
-    .reg = 0, \
-    .type = BX_JUMP_TYPE_ZERO, \
-    .sub_opcode = SUB_OPCODE_BX, \
-    .opcode = OPCODE_BRANCH } }
-
-/**
- * Branch to absolute PC if ALU overflow, address in register
- *
- * reg_pc is the register which contains address to jump to.
- * Address is expressed in 32-bit words.
- */
-#define I_BXFR(reg_pc) { .bx = { \
-    .dreg = reg_pc, \
-    .addr = 0, \
-    .unused = 0, \
-    .reg = 1, \
-    .type = BX_JUMP_TYPE_OVF, \
-    .sub_opcode = SUB_OPCODE_BX, \
-    .opcode = OPCODE_BRANCH } }
-
-/**
- * Branch to absolute PC if ALU overflow, immediate address
- *
- * Address imm_pc is expressed in 32-bit words.
- */
-#define I_BXFI(imm_pc) { .bx = { \
-    .dreg = 0, \
-    .addr = imm_pc, \
-    .unused = 0, \
-    .reg = 0, \
-    .type = BX_JUMP_TYPE_OVF, \
-    .sub_opcode = SUB_OPCODE_BX, \
-    .opcode = OPCODE_BRANCH } }
-
-
-/**
- * Addition: dest = src1 + src2
- */
-#define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src1, \
-    .treg = reg_src2, \
-    .unused = 0, \
-    .sel = ALU_SEL_ADD, \
-    .sub_opcode = SUB_OPCODE_ALU_REG, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Subtraction: dest = src1 - src2
- */
-#define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src1, \
-    .treg = reg_src2, \
-    .unused = 0, \
-    .sel = ALU_SEL_SUB, \
-    .sub_opcode = SUB_OPCODE_ALU_REG, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Logical AND: dest = src1 & src2
- */
-#define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src1, \
-    .treg = reg_src2, \
-    .unused = 0, \
-    .sel = ALU_SEL_AND, \
-    .sub_opcode = SUB_OPCODE_ALU_REG, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Logical OR: dest = src1 | src2
- */
-#define I_ORR(reg_dest, reg_src1, reg_src2)  { .alu_reg = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src1, \
-    .treg = reg_src2, \
-    .unused = 0, \
-    .sel = ALU_SEL_OR, \
-    .sub_opcode = SUB_OPCODE_ALU_REG, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Copy: dest = src
- */
-#define I_MOVR(reg_dest, reg_src) { .alu_reg = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src, \
-    .treg = 0, \
-    .unused = 0, \
-    .sel = ALU_SEL_MOV, \
-    .sub_opcode = SUB_OPCODE_ALU_REG, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Logical shift left: dest = src << shift
- */
-#define I_LSHR(reg_dest, reg_src, reg_shift)  { .alu_reg = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src, \
-    .treg = reg_shift, \
-    .unused = 0, \
-    .sel = ALU_SEL_LSH, \
-    .sub_opcode = SUB_OPCODE_ALU_REG, \
-    .opcode = OPCODE_ALU } }
-
-
-/**
- * Logical shift right: dest = src >> shift
- */
-#define I_RSHR(reg_dest, reg_src, reg_shift)  { .alu_reg = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src, \
-    .treg = reg_shift, \
-    .unused = 0, \
-    .sel = ALU_SEL_RSH, \
-    .sub_opcode = SUB_OPCODE_ALU_REG, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Add register and an immediate value: dest = src1 + imm
- */
-#define I_ADDI(reg_dest, reg_src, imm_) { .alu_imm = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src, \
-    .imm = imm_, \
-    .unused = 0, \
-    .sel = ALU_SEL_ADD, \
-    .sub_opcode = SUB_OPCODE_ALU_IMM, \
-    .opcode = OPCODE_ALU } }
-
-
-/**
- *  Subtract register and an immediate value: dest = src - imm
- */
-#define I_SUBI(reg_dest, reg_src, imm_) { .alu_imm = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src, \
-    .imm = imm_, \
-    .unused = 0, \
-    .sel = ALU_SEL_SUB, \
-    .sub_opcode = SUB_OPCODE_ALU_IMM, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Logical AND register and an immediate value: dest = src & imm
- */
-#define I_ANDI(reg_dest, reg_src, imm_) { .alu_imm = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src, \
-    .imm = imm_, \
-    .unused = 0, \
-    .sel = ALU_SEL_AND, \
-    .sub_opcode = SUB_OPCODE_ALU_IMM, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Logical OR register and an immediate value: dest = src | imm
- */
-#define I_ORI(reg_dest, reg_src, imm_) { .alu_imm = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src, \
-    .imm = imm_, \
-    .unused = 0, \
-    .sel = ALU_SEL_OR, \
-    .sub_opcode = SUB_OPCODE_ALU_IMM, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Copy an immediate value into register: dest = imm
- */
-#define I_MOVI(reg_dest, imm_) { .alu_imm = { \
-    .dreg = reg_dest, \
-    .sreg = 0, \
-    .imm = imm_, \
-    .unused = 0, \
-    .sel = ALU_SEL_MOV, \
-    .sub_opcode = SUB_OPCODE_ALU_IMM, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Logical shift left register value by an immediate: dest = src << imm
- */
-#define I_LSHI(reg_dest, reg_src, imm_) { .alu_imm = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src, \
-    .imm = imm_, \
-    .unused = 0, \
-    .sel = ALU_SEL_LSH, \
-    .sub_opcode = SUB_OPCODE_ALU_IMM, \
-    .opcode = OPCODE_ALU } }
-
-
-/**
- * Logical shift right register value by an immediate: dest = val >> imm
- */
-#define I_RSHI(reg_dest, reg_src, imm_) { .alu_imm = { \
-    .dreg = reg_dest, \
-    .sreg = reg_src, \
-    .imm = imm_, \
-    .unused = 0, \
-    .sel = ALU_SEL_RSH, \
-    .sub_opcode = SUB_OPCODE_ALU_IMM, \
-    .opcode = OPCODE_ALU } }
-
-/**
- * Define a label with number label_num.
- *
- * This is a macro which doesn't generate a real instruction.
- * The token generated by this macro is removed by ulp_process_macros_and_load
- * function. Label defined using this macro can be used in branch macros defined
- * below.
- */
-#define M_LABEL(label_num) { .macro = { \
-    .label = label_num, \
-    .unused = 0, \
-    .sub_opcode = SUB_OPCODE_MACRO_LABEL, \
-    .opcode = OPCODE_MACRO } }
-
-/**
- * Token macro used by M_B and M_BX macros. Not to be used directly.
- */
-#define M_BRANCH(label_num) { .macro = { \
-    .label = label_num, \
-    .unused = 0, \
-    .sub_opcode = SUB_OPCODE_MACRO_BRANCH, \
-    .opcode = OPCODE_MACRO } }
-
-/**
- * Macro: branch to label label_num if R0 is less than immediate value.
- *
- * This macro generates two ulp_insn_t values separated by a comma, and should
- * be used when defining contents of ulp_insn_t arrays. First value is not a
- * real instruction; it is a token which is removed by ulp_process_macros_and_load
- * function.
- */
-#define M_BL(label_num, imm_value) \
-    M_BRANCH(label_num), \
-    I_BL(0, imm_value)
-
-/**
- * Macro: branch to label label_num if R0 is greater or equal than immediate value
- *
- * This macro generates two ulp_insn_t values separated by a comma, and should
- * be used when defining contents of ulp_insn_t arrays. First value is not a
- * real instruction; it is a token which is removed by ulp_process_macros_and_load
- * function.
- */
-#define M_BGE(label_num, imm_value) \
-    M_BRANCH(label_num), \
-    I_BGE(0, imm_value)
-
-/**
- * Macro: unconditional branch to label
- *
- * This macro generates two ulp_insn_t values separated by a comma, and should
- * be used when defining contents of ulp_insn_t arrays. First value is not a
- * real instruction; it is a token which is removed by ulp_process_macros_and_load
- * function.
- */
-#define M_BX(label_num) \
-    M_BRANCH(label_num), \
-    I_BXI(0)
-
-/**
- * Macro: branch to label if ALU result is zero
- *
- * This macro generates two ulp_insn_t values separated by a comma, and should
- * be used when defining contents of ulp_insn_t arrays. First value is not a
- * real instruction; it is a token which is removed by ulp_process_macros_and_load
- * function.
- */
-#define M_BXZ(label_num) \
-    M_BRANCH(label_num), \
-    I_BXZI(0)
-
-/**
- * Macro: branch to label if ALU overflow
- *
- * This macro generates two ulp_insn_t values separated by a comma, and should
- * be used when defining contents of ulp_insn_t arrays. First value is not a
- * real instruction; it is a token which is removed by ulp_process_macros_and_load
- * function.
- */
-#define M_BXF(label_num) \
-    M_BRANCH(label_num), \
-    I_BXFI(0)
-
-
-
-#define RTC_SLOW_MEM ((uint32_t*) 0x50000000)       /*!< RTC slow memory, 8k size */
-
-/**
- * @brief Resolve all macro references in a program and load it into RTC memory
- * @param load_addr  address where the program should be loaded, expressed in 32-bit words
- * @param program  ulp_insn_t array with the program
- * @param psize  size of the program, expressed in 32-bit words
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NO_MEM if auxiliary temporary structure can not be allocated
- *      - one of ESP_ERR_ULP_xxx if program is not valid or can not be loaded
- */
-esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* program, size_t* psize);
-
-/**
- * @brief Load ULP program binary into RTC memory
- *
- * ULP program binary should have the following format (all values little-endian):
- *
- * 1. MAGIC, (value 0x00706c75, 4 bytes)
- * 2. TEXT_OFFSET, offset of .text section from binary start (2 bytes)
- * 3. TEXT_SIZE, size of .text section (2 bytes)
- * 4. DATA_SIZE, size of .data section (2 bytes)
- * 5. BSS_SIZE, size of .bss section (2 bytes)
- * 6. (TEXT_OFFSET - 12) bytes of arbitrary data (will not be loaded into RTC memory)
- * 7. .text section
- * 8. .data section
- *
- * Linker script in components/ulp/ld/esp32.ulp.ld produces ELF files which
- * correspond to this format. This linker script produces binaries with load_addr == 0.
- *
- * @param load_addr address where the program should be loaded, expressed in 32-bit words
- * @param program_binary pointer to program binary
- * @param program_size size of the program binary
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if load_addr is out of range
- *      - ESP_ERR_INVALID_SIZE if program_size doesn't match (TEXT_OFFSET + TEXT_SIZE + DATA_SIZE)
- *      - ESP_ERR_NOT_SUPPORTED if the magic number is incorrect
- */
-esp_err_t ulp_load_binary(uint32_t load_addr, const uint8_t* program_binary, size_t program_size);
-
-/**
- * @brief Run the program loaded into RTC memory
- * @param entry_point entry point, expressed in 32-bit words
- * @return  ESP_OK on success
- */
-esp_err_t ulp_run(uint32_t entry_point);
-
-/**
- * @brief Set one of ULP wakeup period values
- *
- * ULP coprocessor starts running the program when the wakeup timer counts up
- * to a given value (called period). There are 5 period values which can be
- * programmed into SENS_ULP_CP_SLEEP_CYCx_REG registers, x = 0..4.
- * By default, wakeup timer will use the period set into SENS_ULP_CP_SLEEP_CYC0_REG,
- * i.e. period number 0. ULP program code can use SLEEP instruction to select
- * which of the SENS_ULP_CP_SLEEP_CYCx_REG should be used for subsequent wakeups.
- *
- * However, please note that SLEEP instruction issued (from ULP program) while the system
- * is in deep sleep mode does not have effect, and sleep cycle count 0 is used.
- *
- * @param period_index wakeup period setting number (0 - 4)
- * @param period_us wakeup period, us
- * @note  The ULP FSM requires two clock cycles to wakeup before being able to run the program.
- *        Then additional 16 cycles are reserved after wakeup waiting until the 8M clock is stable.
- *        The FSM also requires two more clock cycles to go to sleep after the program execution is halted.
- *        The minimum wakeup period that may be set up for the ULP
- *        is equal to the total number of cycles spent on the above internal tasks.
- *        For a default configuration of the ULP running at 150kHz it makes about 133us.
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if period_index is out of range
- */
-esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/unity/unity.h b/tools/sdk/include/unity/unity.h
deleted file mode 100644
index a0c301d25a2..00000000000
--- a/tools/sdk/include/unity/unity.h
+++ /dev/null
@@ -1,503 +0,0 @@
-/* ==========================================
-    Unity Project - A Test Framework for C
-    Copyright (c) 2007-14 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-========================================== */
-
-#ifndef UNITY_FRAMEWORK_H
-#define UNITY_FRAMEWORK_H
-#define UNITY
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "unity_internals.h"
-
-/*-------------------------------------------------------
- * Test Setup / Teardown
- *-------------------------------------------------------*/
-
-/* These functions are intended to be called before and after each test. */
-void setUp(void);
-void tearDown(void);
-
-/* These functions are intended to be called at the beginning and end of an
- * entire test suite.  suiteTearDown() is passed the number of tests that
- * failed, and its return value becomes the exit code of main(). */
-void suiteSetUp(void);
-int suiteTearDown(int num_failures);
-
-/* If the compiler supports it, the following block provides stub
- * implementations of the above functions as weak symbols.  Note that on
- * some platforms (MinGW for example), weak function implementations need
- * to be in the same translation unit they are called from.  This can be
- * achieved by defining UNITY_INCLUDE_SETUP_STUBS before including unity.h. */
-#ifdef UNITY_INCLUDE_SETUP_STUBS
-  #ifdef UNITY_WEAK_ATTRIBUTE
-    UNITY_WEAK_ATTRIBUTE void setUp(void) { }
-    UNITY_WEAK_ATTRIBUTE void tearDown(void) { }
-    UNITY_WEAK_ATTRIBUTE void suiteSetUp(void) { }
-    UNITY_WEAK_ATTRIBUTE int suiteTearDown(int num_failures) { return num_failures; }
-  #elif defined(UNITY_WEAK_PRAGMA)
-    #pragma weak setUp
-    void setUp(void) { }
-    #pragma weak tearDown
-    void tearDown(void) { }
-    #pragma weak suiteSetUp
-    void suiteSetUp(void) { }
-    #pragma weak suiteTearDown
-    int suiteTearDown(int num_failures) { return num_failures; }
-  #endif
-#endif
-
-/*-------------------------------------------------------
- * Configuration Options
- *-------------------------------------------------------
- * All options described below should be passed as a compiler flag to all files using Unity. If you must add #defines, place them BEFORE the #include above.
-
- * Integers/longs/pointers
- *     - Unity attempts to automatically discover your integer sizes
- *       - define UNITY_EXCLUDE_STDINT_H to stop attempting to look in <stdint.h>
- *       - define UNITY_EXCLUDE_LIMITS_H to stop attempting to look in <limits.h>
- *     - If you cannot use the automatic methods above, you can force Unity by using these options:
- *       - define UNITY_SUPPORT_64
- *       - set UNITY_INT_WIDTH
- *       - set UNITY_LONG_WIDTH
- *       - set UNITY_POINTER_WIDTH
-
- * Floats
- *     - define UNITY_EXCLUDE_FLOAT to disallow floating point comparisons
- *     - define UNITY_FLOAT_PRECISION to specify the precision to use when doing TEST_ASSERT_EQUAL_FLOAT
- *     - define UNITY_FLOAT_TYPE to specify doubles instead of single precision floats
- *     - define UNITY_INCLUDE_DOUBLE to allow double floating point comparisons
- *     - define UNITY_EXCLUDE_DOUBLE to disallow double floating point comparisons (default)
- *     - define UNITY_DOUBLE_PRECISION to specify the precision to use when doing TEST_ASSERT_EQUAL_DOUBLE
- *     - define UNITY_DOUBLE_TYPE to specify something other than double
- *     - define UNITY_EXCLUDE_FLOAT_PRINT to trim binary size, won't print floating point values in errors
-
- * Output
- *     - by default, Unity prints to standard out with putchar.  define UNITY_OUTPUT_CHAR(a) with a different function if desired
- *     - define UNITY_DIFFERENTIATE_FINAL_FAIL to print FAILED (vs. FAIL) at test end summary - for automated search for failure
-
- * Optimization
- *     - by default, line numbers are stored in unsigned shorts.  Define UNITY_LINE_TYPE with a different type if your files are huge
- *     - by default, test and failure counters are unsigned shorts.  Define UNITY_COUNTER_TYPE with a different type if you want to save space or have more than 65535 Tests.
-
- * Test Cases
- *     - define UNITY_SUPPORT_TEST_CASES to include the TEST_CASE macro, though really it's mostly about the runner generator script
-
- * Parameterized Tests
- *     - you'll want to create a define of TEST_CASE(...) which basically evaluates to nothing
-
- * Tests with Arguments
- *     - you'll want to define UNITY_USE_COMMAND_LINE_ARGS if you have the test runner passing arguments to Unity
-
- *-------------------------------------------------------
- * Basic Fail and Ignore
- *-------------------------------------------------------*/
-
-#define TEST_FAIL_MESSAGE(message)                                                                 UNITY_TEST_FAIL(__LINE__, (message))
-#define TEST_FAIL()                                                                                UNITY_TEST_FAIL(__LINE__, NULL)
-#define TEST_IGNORE_MESSAGE(message)                                                               UNITY_TEST_IGNORE(__LINE__, (message))
-#define TEST_IGNORE()                                                                              UNITY_TEST_IGNORE(__LINE__, NULL)
-#define TEST_ONLY()
-
-/* It is not necessary for you to call PASS. A PASS condition is assumed if nothing fails.
- * This method allows you to abort a test immediately with a PASS state, ignoring the remainder of the test. */
-#define TEST_PASS()                                                                                TEST_ABORT()
-
-/* This macro does nothing, but it is useful for build tools (like Ceedling) to make use of this to figure out
- * which files should be linked to in order to perform a test. Use it like TEST_FILE("sandwiches.c") */
-#define TEST_FILE(a)
-
-/*-------------------------------------------------------
- * Test Asserts (simple)
- *-------------------------------------------------------*/
-
-/* Boolean */
-#define TEST_ASSERT(condition)                                                                     UNITY_TEST_ASSERT(       (condition), __LINE__, " Expression Evaluated To FALSE")
-#define TEST_ASSERT_TRUE(condition)                                                                UNITY_TEST_ASSERT(       (condition), __LINE__, " Expected TRUE Was FALSE")
-#define TEST_ASSERT_UNLESS(condition)                                                              UNITY_TEST_ASSERT(      !(condition), __LINE__, " Expression Evaluated To TRUE")
-#define TEST_ASSERT_FALSE(condition)                                                               UNITY_TEST_ASSERT(      !(condition), __LINE__, " Expected FALSE Was TRUE")
-#define TEST_ASSERT_NULL(pointer)                                                                  UNITY_TEST_ASSERT_NULL(    (pointer), __LINE__, " Expected NULL")
-#define TEST_ASSERT_NOT_NULL(pointer)                                                              UNITY_TEST_ASSERT_NOT_NULL((pointer), __LINE__, " Expected Non-NULL")
-
-/* Integers (of all sizes) */
-#define TEST_ASSERT_EQUAL_INT(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT8(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_INT8((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT16(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_INT16((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT32(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_INT32((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT64(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_INT64((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL(expected, actual)                                                        UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_NOT_EQUAL(expected, actual)                                                    UNITY_TEST_ASSERT(((expected) !=  (actual)), __LINE__, " Expected Not-Equal")
-#define TEST_ASSERT_EQUAL_UINT(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_UINT( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT8(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_UINT8( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT16(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT16( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT32(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT32( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT64(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_UINT64( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX8(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_HEX8( (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX16(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX16((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX32(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX64(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX64((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS(mask, expected, actual)                                                   UNITY_TEST_ASSERT_BITS((mask), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS_HIGH(mask, actual)                                                        UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(-1), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS_LOW(mask, actual)                                                         UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(0), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BIT_HIGH(bit, actual)                                                          UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(-1), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BIT_LOW(bit, actual)                                                           UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(0), (actual), __LINE__, NULL)
-
-/* Integer Greater Than/ Less Than (of all sizes) */
-#define TEST_ASSERT_GREATER_THAN(threshold, actual)                                                UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT(threshold, actual)                                            UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT8(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT16(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT32(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_INT64(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT8(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT16(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT32(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual)                                         UNITY_TEST_ASSERT_GREATER_THAN_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX8(threshold, actual)                                           UNITY_TEST_ASSERT_GREATER_THAN_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX16(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX32(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual)                                          UNITY_TEST_ASSERT_GREATER_THAN_HEX64((threshold), (actual), __LINE__, NULL)
-
-#define TEST_ASSERT_LESS_THAN(threshold, actual)                                                   UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT(threshold, actual)                                               UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT8(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT16(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT32(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_INT64(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT8(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT16(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT32(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_UINT64(threshold, actual)                                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX8(threshold, actual)                                              UNITY_TEST_ASSERT_SMALLER_THAN_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX16(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX32(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_THAN_HEX64(threshold, actual)                                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX64((threshold), (actual), __LINE__, NULL)
-
-#define TEST_ASSERT_GREATER_OR_EQUAL(threshold, actual)                                            UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT(threshold, actual)                                        UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT8(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT16(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT32(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT64(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT8(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT16(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT32(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT64(threshold, actual)                                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX8(threshold, actual)                                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX16(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX32(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX64(threshold, actual)                                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, NULL)
-
-#define TEST_ASSERT_LESS_OR_EQUAL(threshold, actual)                                               UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT(threshold, actual)                                           UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT8(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT16(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT32(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_INT64(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT8(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT16(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT32(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT64(threshold, actual)                                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX8(threshold, actual)                                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX16(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX32(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, NULL)
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX64(threshold, actual)                                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, NULL)
-
-/* Integer Ranges (of all sizes) */
-#define TEST_ASSERT_INT_WITHIN(delta, expected, actual)                                            UNITY_TEST_ASSERT_INT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT8_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_INT8_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT16_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_INT16_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT32_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_INT32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_INT64_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_INT64_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_UINT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT8_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_UINT8_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT16_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT16_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT32_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_UINT64_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_UINT64_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX_WITHIN(delta, expected, actual)                                            UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX8_WITHIN(delta, expected, actual)                                           UNITY_TEST_ASSERT_HEX8_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX16_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_HEX16_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX32_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_HEX64_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_HEX64_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-
-/* Structs and Strings */
-#define TEST_ASSERT_EQUAL_PTR(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_PTR((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_STRING(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_STRING((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_STRING_LEN(expected, actual, len)                                        UNITY_TEST_ASSERT_EQUAL_STRING_LEN((expected), (actual), (len), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_MEMORY(expected, actual, len)                                            UNITY_TEST_ASSERT_EQUAL_MEMORY((expected), (actual), (len), __LINE__, NULL)
-
-/* Arrays */
-#define TEST_ASSERT_EQUAL_INT_ARRAY(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EQUAL_INT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT8_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_INT8_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT16_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_INT16_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT32_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_INT32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_INT64_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT8_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_UINT8_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT16_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT16_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT32_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_UINT64_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX_ARRAY(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX8_ARRAY(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EQUAL_HEX8_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX16_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_HEX16_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX32_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_HEX64_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_PTR_ARRAY(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EQUAL_PTR_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_STRING_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_STRING_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_MEMORY_ARRAY(expected, actual, len, num_elements)                        UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((expected), (actual), (len), (num_elements), __LINE__, NULL)
-
-/* Arrays Compared To Single Value */
-#define TEST_ASSERT_EACH_EQUAL_INT(expected, actual, num_elements)                                 UNITY_TEST_ASSERT_EACH_EQUAL_INT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT8(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_INT8((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT16(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_INT16((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT32(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_INT32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_INT64(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_INT64((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_UINT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT8(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_UINT8((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT16(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT16((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT32(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_UINT64(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_UINT64((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX(expected, actual, num_elements)                                 UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX8(expected, actual, num_elements)                                UNITY_TEST_ASSERT_EACH_EQUAL_HEX8((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX16(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_HEX16((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX32(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_HEX64(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_HEX64((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_PTR(expected, actual, num_elements)                                 UNITY_TEST_ASSERT_EACH_EQUAL_PTR((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_STRING(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_STRING((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_MEMORY(expected, actual, len, num_elements)                         UNITY_TEST_ASSERT_EACH_EQUAL_MEMORY((expected), (actual), (len), (num_elements), __LINE__, NULL)
-
-/* Floating Point (If Enabled) */
-#define TEST_ASSERT_FLOAT_WITHIN(delta, expected, actual)                                          UNITY_TEST_ASSERT_FLOAT_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_FLOAT(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_FLOAT((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_FLOAT_ARRAY(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_FLOAT(expected, actual, num_elements)                               UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_INF(actual)                                                           UNITY_TEST_ASSERT_FLOAT_IS_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NEG_INF(actual)                                                       UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NAN(actual)                                                           UNITY_TEST_ASSERT_FLOAT_IS_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_DETERMINATE(actual)                                                   UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_INF(actual)                                                       UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_NEG_INF(actual)                                                   UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_NAN(actual)                                                       UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE(actual)                                               UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE((actual), __LINE__, NULL)
-
-/* Double (If Enabled) */
-#define TEST_ASSERT_DOUBLE_WITHIN(delta, expected, actual)                                         UNITY_TEST_ASSERT_DOUBLE_WITHIN((delta), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_DOUBLE(expected, actual)                                                 UNITY_TEST_ASSERT_EQUAL_DOUBLE((expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_EQUAL_DOUBLE_ARRAY(expected, actual, num_elements)                             UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_EACH_EQUAL_DOUBLE(expected, actual, num_elements)                              UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE((expected), (actual), (num_elements), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_INF(actual)                                                          UNITY_TEST_ASSERT_DOUBLE_IS_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NEG_INF(actual)                                                      UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NAN(actual)                                                          UNITY_TEST_ASSERT_DOUBLE_IS_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_DETERMINATE(actual)                                                  UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_INF(actual)                                                      UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF(actual)                                                  UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_NAN(actual)                                                      UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN((actual), __LINE__, NULL)
-#define TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual)                                              UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE((actual), __LINE__, NULL)
-
-/*-------------------------------------------------------
- * Test Asserts (with additional messages)
- *-------------------------------------------------------*/
-
-/* Boolean */
-#define TEST_ASSERT_MESSAGE(condition, message)                                                    UNITY_TEST_ASSERT(       (condition), __LINE__, (message))
-#define TEST_ASSERT_TRUE_MESSAGE(condition, message)                                               UNITY_TEST_ASSERT(       (condition), __LINE__, (message))
-#define TEST_ASSERT_UNLESS_MESSAGE(condition, message)                                             UNITY_TEST_ASSERT(      !(condition), __LINE__, (message))
-#define TEST_ASSERT_FALSE_MESSAGE(condition, message)                                              UNITY_TEST_ASSERT(      !(condition), __LINE__, (message))
-#define TEST_ASSERT_NULL_MESSAGE(pointer, message)                                                 UNITY_TEST_ASSERT_NULL(    (pointer), __LINE__, (message))
-#define TEST_ASSERT_NOT_NULL_MESSAGE(pointer, message)                                             UNITY_TEST_ASSERT_NOT_NULL((pointer), __LINE__, (message))
-
-/* Integers (of all sizes) */
-#define TEST_ASSERT_EQUAL_INT_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT8_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_INT8((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT16_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_INT16((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT32_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_INT32((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT64_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_INT64((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_MESSAGE(expected, actual, message)                                       UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_NOT_EQUAL_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT(((expected) !=  (actual)), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_UINT( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT8_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_UINT8( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT16_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT16( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT32_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT32( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT64_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_UINT64( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX8_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_HEX8( (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX16_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_HEX16((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX32_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_HEX32((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX64_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_HEX64((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_BITS_MESSAGE(mask, expected, actual, message)                                  UNITY_TEST_ASSERT_BITS((mask), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_BITS_HIGH_MESSAGE(mask, actual, message)                                       UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(-1), (actual), __LINE__, (message))
-#define TEST_ASSERT_BITS_LOW_MESSAGE(mask, actual, message)                                        UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(0), (actual), __LINE__, (message))
-#define TEST_ASSERT_BIT_HIGH_MESSAGE(bit, actual, message)                                         UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(-1), (actual), __LINE__, (message))
-#define TEST_ASSERT_BIT_LOW_MESSAGE(bit, actual, message)                                          UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(0), (actual), __LINE__, (message))
-
-/* Integer Greater Than/ Less Than (of all sizes) */
-#define TEST_ASSERT_GREATER_THAN_MESSAGE(threshold, actual, message)                               UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT8_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT16_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT32_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_INT64_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT8_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT16_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT32_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_UINT64_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_GREATER_THAN_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX8_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_GREATER_THAN_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX16_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX32_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_THAN_HEX64_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_GREATER_THAN_HEX64((threshold), (actual), __LINE__, (message))
-
-#define TEST_ASSERT_LESS_THAN_MESSAGE(threshold, actual, message)                                  UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT_MESSAGE(threshold, actual, message)                              UNITY_TEST_ASSERT_SMALLER_THAN_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT8_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT16_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT32_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_INT64_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT8_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT16_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT32_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_UINT64_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_SMALLER_THAN_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX8_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_SMALLER_THAN_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX16_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX32_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_THAN_HEX64_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_SMALLER_THAN_HEX64((threshold), (actual), __LINE__, (message))
-
-#define TEST_ASSERT_GREATER_OR_EQUAL_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT8_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT16_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT32_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_INT64_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT8_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT16_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT32_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_UINT64_MESSAGE(threshold, actual, message)                    UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX8_MESSAGE(threshold, actual, message)                      UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX16_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX32_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_GREATER_OR_EQUAL_HEX64_MESSAGE(threshold, actual, message)                     UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, (message))
-
-#define TEST_ASSERT_LESS_OR_EQUAL_MESSAGE(threshold, actual, message)                              UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT_MESSAGE(threshold, actual, message)                          UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT8_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT16_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT32_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_INT64_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT8_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT16_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT32_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_UINT64_MESSAGE(threshold, actual, message)                       UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX8_MESSAGE(threshold, actual, message)                         UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX8((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX16_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX16((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX32_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX32((threshold), (actual), __LINE__, (message))
-#define TEST_ASSERT_LESS_OR_EQUAL_HEX64_MESSAGE(threshold, actual, message)                        UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64((threshold), (actual), __LINE__, (message))
-
-/* Integer Ranges (of all sizes) */
-#define TEST_ASSERT_INT_WITHIN_MESSAGE(delta, expected, actual, message)                           UNITY_TEST_ASSERT_INT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT8_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_INT8_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT16_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_INT16_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT32_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_INT32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_INT64_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_INT64_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_UINT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT8_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_UINT8_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT16_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT16_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT32_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_UINT64_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_UINT64_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX_WITHIN_MESSAGE(delta, expected, actual, message)                           UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX8_WITHIN_MESSAGE(delta, expected, actual, message)                          UNITY_TEST_ASSERT_HEX8_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX16_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_HEX16_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX32_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_HEX32_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_HEX64_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_HEX64_WITHIN((delta), (expected), (actual), __LINE__, (message))
-
-/* Structs and Strings */
-#define TEST_ASSERT_EQUAL_PTR_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_PTR((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_STRING_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_STRING((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_STRING_LEN_MESSAGE(expected, actual, len, message)                       UNITY_TEST_ASSERT_EQUAL_STRING_LEN((expected), (actual), (len), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_MEMORY_MESSAGE(expected, actual, len, message)                           UNITY_TEST_ASSERT_EQUAL_MEMORY((expected), (actual), (len), __LINE__, (message))
-
-/* Arrays */
-#define TEST_ASSERT_EQUAL_INT_ARRAY_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EQUAL_INT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT8_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_INT8_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT16_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_INT16_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT32_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_INT32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_INT64_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT8_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_UINT8_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT16_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT16_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT32_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_UINT64_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX_ARRAY_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX8_ARRAY_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EQUAL_HEX8_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX16_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_HEX16_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX32_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_HEX64_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_PTR_ARRAY_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EQUAL_PTR_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_STRING_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_STRING_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_MEMORY_ARRAY_MESSAGE(expected, actual, len, num_elements, message)       UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((expected), (actual), (len), (num_elements), __LINE__, (message))
-
-/* Arrays Compared To Single Value*/
-#define TEST_ASSERT_EACH_EQUAL_INT_MESSAGE(expected, actual, num_elements, message)                UNITY_TEST_ASSERT_EACH_EQUAL_INT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT8_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_INT8((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT16_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_INT16((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT32_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_INT32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_INT64_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_INT64((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_UINT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT8_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_UINT8((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT16_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT16((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT32_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_UINT64_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_UINT64((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX_MESSAGE(expected, actual, num_elements, message)                UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX8_MESSAGE(expected, actual, num_elements, message)               UNITY_TEST_ASSERT_EACH_EQUAL_HEX8((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX16_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_HEX16((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX32_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_HEX32((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_HEX64_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_HEX64((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_PTR_MESSAGE(expected, actual, num_elements, message)                UNITY_TEST_ASSERT_EACH_EQUAL_PTR((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_STRING_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_STRING((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_MEMORY_MESSAGE(expected, actual, len, num_elements, message)        UNITY_TEST_ASSERT_EACH_EQUAL_MEMORY((expected), (actual), (len), (num_elements), __LINE__, (message))
-
-/* Floating Point (If Enabled) */
-#define TEST_ASSERT_FLOAT_WITHIN_MESSAGE(delta, expected, actual, message)                         UNITY_TEST_ASSERT_FLOAT_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_FLOAT_MESSAGE(expected, actual, message)                                 UNITY_TEST_ASSERT_EQUAL_FLOAT((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_FLOAT_ARRAY_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_FLOAT_MESSAGE(expected, actual, num_elements, message)              UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_INF_MESSAGE(actual, message)                                          UNITY_TEST_ASSERT_FLOAT_IS_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NEG_INF_MESSAGE(actual, message)                                      UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NAN_MESSAGE(actual, message)                                          UNITY_TEST_ASSERT_FLOAT_IS_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_DETERMINATE_MESSAGE(actual, message)                                  UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_INF_MESSAGE(actual, message)                                      UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_NEG_INF_MESSAGE(actual, message)                                  UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_NAN_MESSAGE(actual, message)                                      UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE_MESSAGE(actual, message)                              UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE((actual), __LINE__, (message))
-
-/* Double (If Enabled) */
-#define TEST_ASSERT_DOUBLE_WITHIN_MESSAGE(delta, expected, actual, message)                        UNITY_TEST_ASSERT_DOUBLE_WITHIN((delta), (expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_DOUBLE_MESSAGE(expected, actual, message)                                UNITY_TEST_ASSERT_EQUAL_DOUBLE((expected), (actual), __LINE__, (message))
-#define TEST_ASSERT_EQUAL_DOUBLE_ARRAY_MESSAGE(expected, actual, num_elements, message)            UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_EACH_EQUAL_DOUBLE_MESSAGE(expected, actual, num_elements, message)             UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE((expected), (actual), (num_elements), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_INF_MESSAGE(actual, message)                                         UNITY_TEST_ASSERT_DOUBLE_IS_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NEG_INF_MESSAGE(actual, message)                                     UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NAN_MESSAGE(actual, message)                                         UNITY_TEST_ASSERT_DOUBLE_IS_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_DETERMINATE_MESSAGE(actual, message)                                 UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_INF_MESSAGE(actual, message)                                     UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF_MESSAGE(actual, message)                                 UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_NAN_MESSAGE(actual, message)                                     UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN((actual), __LINE__, (message))
-#define TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE_MESSAGE(actual, message)                             UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE((actual), __LINE__, (message))
-
-/* end of UNITY_FRAMEWORK_H */
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/tools/sdk/include/unity/unity_config.h b/tools/sdk/include/unity/unity_config.h
deleted file mode 100644
index b23a5fe1298..00000000000
--- a/tools/sdk/include/unity/unity_config.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef UNITY_CONFIG_H
-#define UNITY_CONFIG_H
-
-// This file gets included from unity.h via unity_internals.h
-// It is inside #ifdef __cplusplus / extern "C" block, so we can
-// only use C features here
-
-#include <esp_err.h>
-#include <stddef.h>
-#include "sdkconfig.h"
-
-#ifdef CONFIG_UNITY_ENABLE_FLOAT
-#define UNITY_INCLUDE_FLOAT
-#else
-#define UNITY_EXCLUDE_FLOAT
-#endif //CONFIG_UNITY_ENABLE_FLOAT
-
-#ifdef CONFIG_UNITY_ENABLE_DOUBLE
-#define UNITY_INCLUDE_DOUBLE
-#else
-#define UNITY_EXCLUDE_DOUBLE
-#endif //CONFIG_UNITY_ENABLE_DOUBLE
-
-#ifdef CONFIG_UNITY_ENABLE_COLOR
-#define UNITY_OUTPUT_COLOR
-#endif
-
-#define UNITY_EXCLUDE_TIME_H
-
-void unity_flush(void);
-void unity_putc(int c);
-void unity_gets(char* dst, size_t len);
-void unity_exec_time_start(void);
-void unity_exec_time_stop(void);
-uint32_t unity_exec_time_get_ms(void);
-
-#define UNITY_OUTPUT_CHAR(a)    unity_putc(a)
-#define UNITY_OUTPUT_FLUSH()    unity_flush()
-#define UNITY_EXEC_TIME_START() unity_exec_time_start()
-#define UNITY_EXEC_TIME_STOP()  unity_exec_time_stop()
-#define UNITY_EXEC_TIME_MS()    unity_exec_time_get_ms()
-
-#ifdef CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER
-
-#include "unity_test_runner.h"
-
-#endif //CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER
-
-// shorthand to check esp_err_t return code
-#define TEST_ESP_OK(rc) TEST_ASSERT_EQUAL_HEX32(ESP_OK, rc)
-#define TEST_ESP_ERR(err, rc) TEST_ASSERT_EQUAL_HEX32(err, rc)
-
-#endif //UNITY_CONFIG_H
diff --git a/tools/sdk/include/unity/unity_internals.h b/tools/sdk/include/unity/unity_internals.h
deleted file mode 100644
index 7249fc7991a..00000000000
--- a/tools/sdk/include/unity/unity_internals.h
+++ /dev/null
@@ -1,928 +0,0 @@
-/* ==========================================
-    Unity Project - A Test Framework for C
-    Copyright (c) 2007-14 Mike Karlesky, Mark VanderVoord, Greg Williams
-    [Released under MIT License. Please refer to license.txt for details]
-========================================== */
-
-#ifndef UNITY_INTERNALS_H
-#define UNITY_INTERNALS_H
-
-#ifdef UNITY_INCLUDE_CONFIG_H
-#include "unity_config.h"
-#endif
-
-#ifndef UNITY_EXCLUDE_SETJMP_H
-#include <setjmp.h>
-#endif
-
-#ifndef UNITY_EXCLUDE_MATH_H
-#include <math.h>
-#endif
-
-#ifndef UNITY_EXCLUDE_STDDEF_H
-#include <stddef.h>
-#endif
-
-/* Unity Attempts to Auto-Detect Integer Types
- * Attempt 1: UINT_MAX, ULONG_MAX in <limits.h>, or default to 32 bits
- * Attempt 2: UINTPTR_MAX in <stdint.h>, or default to same size as long
- * The user may override any of these derived constants:
- * UNITY_INT_WIDTH, UNITY_LONG_WIDTH, UNITY_POINTER_WIDTH */
-#ifndef UNITY_EXCLUDE_STDINT_H
-#include <stdint.h>
-#endif
-
-#ifndef UNITY_EXCLUDE_LIMITS_H
-#include <limits.h>
-#endif
-
-#ifndef UNITY_EXCLUDE_TIME_H
-#include <time.h>
-#endif
-
-/*-------------------------------------------------------
- * Guess Widths If Not Specified
- *-------------------------------------------------------*/
-
-/* Determine the size of an int, if not already specified.
- * We cannot use sizeof(int), because it is not yet defined
- * at this stage in the translation of the C program.
- * Therefore, infer it from UINT_MAX if possible. */
-#ifndef UNITY_INT_WIDTH
-  #ifdef UINT_MAX
-    #if (UINT_MAX == 0xFFFF)
-      #define UNITY_INT_WIDTH (16)
-    #elif (UINT_MAX == 0xFFFFFFFF)
-      #define UNITY_INT_WIDTH (32)
-    #elif (UINT_MAX == 0xFFFFFFFFFFFFFFFF)
-      #define UNITY_INT_WIDTH (64)
-    #endif
-  #else /* Set to default */
-    #define UNITY_INT_WIDTH (32)
-  #endif /* UINT_MAX */
-#endif
-
-/* Determine the size of a long, if not already specified. */
-#ifndef UNITY_LONG_WIDTH
-  #ifdef ULONG_MAX
-    #if (ULONG_MAX == 0xFFFF)
-      #define UNITY_LONG_WIDTH (16)
-    #elif (ULONG_MAX == 0xFFFFFFFF)
-      #define UNITY_LONG_WIDTH (32)
-    #elif (ULONG_MAX == 0xFFFFFFFFFFFFFFFF)
-      #define UNITY_LONG_WIDTH (64)
-    #endif
-  #else /* Set to default */
-    #define UNITY_LONG_WIDTH (32)
-  #endif /* ULONG_MAX */
-#endif
-
-/* Determine the size of a pointer, if not already specified. */
-#ifndef UNITY_POINTER_WIDTH
-  #ifdef UINTPTR_MAX
-    #if (UINTPTR_MAX <= 0xFFFF)
-      #define UNITY_POINTER_WIDTH (16)
-    #elif (UINTPTR_MAX <= 0xFFFFFFFF)
-      #define UNITY_POINTER_WIDTH (32)
-    #elif (UINTPTR_MAX <= 0xFFFFFFFFFFFFFFFF)
-      #define UNITY_POINTER_WIDTH (64)
-    #endif
-  #else /* Set to default */
-    #define UNITY_POINTER_WIDTH UNITY_LONG_WIDTH
-  #endif /* UINTPTR_MAX */
-#endif
-
-/*-------------------------------------------------------
- * Int Support (Define types based on detected sizes)
- *-------------------------------------------------------*/
-
-#if (UNITY_INT_WIDTH == 32)
-    typedef unsigned char   UNITY_UINT8;
-    typedef unsigned short  UNITY_UINT16;
-    typedef unsigned int    UNITY_UINT32;
-    typedef signed char     UNITY_INT8;
-    typedef signed short    UNITY_INT16;
-    typedef signed int      UNITY_INT32;
-#elif (UNITY_INT_WIDTH == 16)
-    typedef unsigned char   UNITY_UINT8;
-    typedef unsigned int    UNITY_UINT16;
-    typedef unsigned long   UNITY_UINT32;
-    typedef signed char     UNITY_INT8;
-    typedef signed int      UNITY_INT16;
-    typedef signed long     UNITY_INT32;
-#else
-    #error Invalid UNITY_INT_WIDTH specified! (16 or 32 are supported)
-#endif
-
-/*-------------------------------------------------------
- * 64-bit Support
- *-------------------------------------------------------*/
-
-#ifndef UNITY_SUPPORT_64
-  #if UNITY_LONG_WIDTH == 64 || UNITY_POINTER_WIDTH == 64
-    #define UNITY_SUPPORT_64
-  #endif
-#endif
-
-#ifndef UNITY_SUPPORT_64
-    /* No 64-bit Support */
-    typedef UNITY_UINT32 UNITY_UINT;
-    typedef UNITY_INT32 UNITY_INT;
-#else
-
-    /* 64-bit Support */
-  #if (UNITY_LONG_WIDTH == 32)
-    typedef unsigned long long UNITY_UINT64;
-    typedef signed long long   UNITY_INT64;
-  #elif (UNITY_LONG_WIDTH == 64)
-    typedef unsigned long      UNITY_UINT64;
-    typedef signed long        UNITY_INT64;
-  #else
-    #error Invalid UNITY_LONG_WIDTH specified! (32 or 64 are supported)
-  #endif
-    typedef UNITY_UINT64 UNITY_UINT;
-    typedef UNITY_INT64 UNITY_INT;
-
-#endif
-
-/*-------------------------------------------------------
- * Pointer Support
- *-------------------------------------------------------*/
-
-#if (UNITY_POINTER_WIDTH == 32)
-#define UNITY_PTR_TO_INT UNITY_INT32
-#define UNITY_DISPLAY_STYLE_POINTER UNITY_DISPLAY_STYLE_HEX32
-#elif (UNITY_POINTER_WIDTH == 64)
-#define UNITY_PTR_TO_INT UNITY_INT64
-#define UNITY_DISPLAY_STYLE_POINTER UNITY_DISPLAY_STYLE_HEX64
-#elif (UNITY_POINTER_WIDTH == 16)
-#define UNITY_PTR_TO_INT UNITY_INT16
-#define UNITY_DISPLAY_STYLE_POINTER UNITY_DISPLAY_STYLE_HEX16
-#else
-    #error Invalid UNITY_POINTER_WIDTH specified! (16, 32 or 64 are supported)
-#endif
-
-#ifndef UNITY_PTR_ATTRIBUTE
-#define UNITY_PTR_ATTRIBUTE
-#endif
-
-#ifndef UNITY_INTERNAL_PTR
-#define UNITY_INTERNAL_PTR UNITY_PTR_ATTRIBUTE const void*
-#endif
-
-/*-------------------------------------------------------
- * Float Support
- *-------------------------------------------------------*/
-
-#ifdef UNITY_EXCLUDE_FLOAT
-
-/* No Floating Point Support */
-#ifndef UNITY_EXCLUDE_DOUBLE
-#define UNITY_EXCLUDE_DOUBLE /* Remove double when excluding float support */
-#endif
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-#define UNITY_EXCLUDE_FLOAT_PRINT
-#endif
-
-#else
-
-/* Floating Point Support */
-#ifndef UNITY_FLOAT_PRECISION
-#define UNITY_FLOAT_PRECISION (0.00001f)
-#endif
-#ifndef UNITY_FLOAT_TYPE
-#define UNITY_FLOAT_TYPE float
-#endif
-typedef UNITY_FLOAT_TYPE UNITY_FLOAT;
-
-/* isinf & isnan macros should be provided by math.h */
-#ifndef isinf
-/* The value of Inf - Inf is NaN */
-#define isinf(n) (isnan((n) - (n)) && !isnan(n))
-#endif
-
-#ifndef isnan
-/* NaN is the only floating point value that does NOT equal itself.
- * Therefore if n != n, then it is NaN. */
-#define isnan(n) ((n != n) ? 1 : 0)
-#endif
-
-#endif
-
-/*-------------------------------------------------------
- * Double Float Support
- *-------------------------------------------------------*/
-
-/* unlike float, we DON'T include by default */
-#if defined(UNITY_EXCLUDE_DOUBLE) || !defined(UNITY_INCLUDE_DOUBLE)
-
-  /* No Floating Point Support */
-  #ifndef UNITY_EXCLUDE_DOUBLE
-  #define UNITY_EXCLUDE_DOUBLE
-  #else
-    #undef UNITY_INCLUDE_DOUBLE
-  #endif
-
-  #ifndef UNITY_EXCLUDE_FLOAT
-    #ifndef UNITY_DOUBLE_TYPE
-    #define UNITY_DOUBLE_TYPE double
-    #endif
-  typedef UNITY_FLOAT UNITY_DOUBLE;
-  /* For parameter in UnityPrintFloat(UNITY_DOUBLE), which aliases to double or float */
-  #endif
-
-#else
-
-  /* Double Floating Point Support */
-  #ifndef UNITY_DOUBLE_PRECISION
-  #define UNITY_DOUBLE_PRECISION (1e-12)
-  #endif
-
-  #ifndef UNITY_DOUBLE_TYPE
-  #define UNITY_DOUBLE_TYPE double
-  #endif
-  typedef UNITY_DOUBLE_TYPE UNITY_DOUBLE;
-
-#endif
-
-/*-------------------------------------------------------
- * Output Method: stdout (DEFAULT)
- *-------------------------------------------------------*/
-#ifndef UNITY_OUTPUT_CHAR
-  /* Default to using putchar, which is defined in stdio.h */
-  #include <stdio.h>
-  #define UNITY_OUTPUT_CHAR(a) (void)putchar(a)
-#else
-  /* If defined as something else, make sure we declare it here so it's ready for use */
-  #ifdef UNITY_OUTPUT_CHAR_HEADER_DECLARATION
-    extern void UNITY_OUTPUT_CHAR_HEADER_DECLARATION;
-  #endif
-#endif
-
-#ifndef UNITY_OUTPUT_FLUSH
-  #ifdef UNITY_USE_FLUSH_STDOUT
-    /* We want to use the stdout flush utility */
-    #include <stdio.h>
-    #define UNITY_OUTPUT_FLUSH() (void)fflush(stdout)
-  #else
-    /* We've specified nothing, therefore flush should just be ignored */
-    #define UNITY_OUTPUT_FLUSH()
-  #endif
-#else
-  /* If defined as something else, make sure we declare it here so it's ready for use */
-  #ifdef UNITY_OUTPUT_FLUSH_HEADER_DECLARATION
-    extern void UNITY_OUTPUT_FLUSH_HEADER_DECLARATION;
-  #endif
-#endif
-
-#ifndef UNITY_OUTPUT_FLUSH
-#define UNITY_FLUSH_CALL()
-#else
-#define UNITY_FLUSH_CALL() UNITY_OUTPUT_FLUSH()
-#endif
-
-#ifndef UNITY_PRINT_EOL
-#define UNITY_PRINT_EOL()    UNITY_OUTPUT_CHAR('\n')
-#endif
-
-#ifndef UNITY_OUTPUT_START
-#define UNITY_OUTPUT_START()
-#endif
-
-#ifndef UNITY_OUTPUT_COMPLETE
-#define UNITY_OUTPUT_COMPLETE()
-#endif
-
-#ifndef UNITY_EXEC_TIME_RESET
-#ifdef UNITY_INCLUDE_EXEC_TIME
-#define UNITY_EXEC_TIME_RESET()\
-    Unity.CurrentTestStartTime = 0;\
-    Unity.CurrentTestStopTime = 0;
-#else
-#define UNITY_EXEC_TIME_RESET()
-#endif
-#endif
-
-#ifndef UNITY_EXEC_TIME_START
-#ifdef UNITY_INCLUDE_EXEC_TIME
-#define UNITY_EXEC_TIME_START() Unity.CurrentTestStartTime = UNITY_CLOCK_MS();
-#else
-#define UNITY_EXEC_TIME_START()
-#endif
-#endif
-
-#ifndef UNITY_EXEC_TIME_STOP
-#ifdef UNITY_INCLUDE_EXEC_TIME
-#define UNITY_EXEC_TIME_STOP() Unity.CurrentTestStopTime = UNITY_CLOCK_MS();
-#else
-#define UNITY_EXEC_TIME_STOP()
-#endif
-#endif
-
-#ifndef UNITY_PRINT_EXEC_TIME
-#ifdef UNITY_INCLUDE_EXEC_TIME
-#define UNITY_PRINT_EXEC_TIME() \
-	UnityPrint(" (");\
-	UNITY_COUNTER_TYPE execTimeMs = (Unity.CurrentTestStopTime - Unity.CurrentTestStartTime);\
-    UnityPrintNumberUnsigned(execTimeMs);\
-    UnityPrint(" ms)");
-#else
-#define UNITY_PRINT_EXEC_TIME()
-#endif
-#endif
-
-/*-------------------------------------------------------
- * Footprint
- *-------------------------------------------------------*/
-
-#ifndef UNITY_LINE_TYPE
-#define UNITY_LINE_TYPE UNITY_UINT
-#endif
-
-#ifndef UNITY_COUNTER_TYPE
-#define UNITY_COUNTER_TYPE UNITY_UINT
-#endif
-
-/*-------------------------------------------------------
- * Language Features Available
- *-------------------------------------------------------*/
-#if !defined(UNITY_WEAK_ATTRIBUTE) && !defined(UNITY_WEAK_PRAGMA)
-#   if defined(__GNUC__) || defined(__ghs__) /* __GNUC__ includes clang */
-#       if !(defined(__WIN32__) && defined(__clang__)) && !defined(__TMS470__)
-#           define UNITY_WEAK_ATTRIBUTE __attribute__((weak))
-#       endif
-#   endif
-#endif
-
-#ifdef UNITY_NO_WEAK
-#   undef UNITY_WEAK_ATTRIBUTE
-#   undef UNITY_WEAK_PRAGMA
-#endif
-
-
-/*-------------------------------------------------------
- * Internal Structs Needed
- *-------------------------------------------------------*/
-
-typedef void (*UnityTestFunction)(void);
-
-#define UNITY_DISPLAY_RANGE_INT  (0x10)
-#define UNITY_DISPLAY_RANGE_UINT (0x20)
-#define UNITY_DISPLAY_RANGE_HEX  (0x40)
-
-typedef enum
-{
-UNITY_DISPLAY_STYLE_INT = sizeof(int)+ UNITY_DISPLAY_RANGE_INT,
-    UNITY_DISPLAY_STYLE_INT8     = 1 + UNITY_DISPLAY_RANGE_INT,
-    UNITY_DISPLAY_STYLE_INT16    = 2 + UNITY_DISPLAY_RANGE_INT,
-    UNITY_DISPLAY_STYLE_INT32    = 4 + UNITY_DISPLAY_RANGE_INT,
-#ifdef UNITY_SUPPORT_64
-    UNITY_DISPLAY_STYLE_INT64    = 8 + UNITY_DISPLAY_RANGE_INT,
-#endif
-
-UNITY_DISPLAY_STYLE_UINT = sizeof(unsigned) + UNITY_DISPLAY_RANGE_UINT,
-    UNITY_DISPLAY_STYLE_UINT8    = 1 + UNITY_DISPLAY_RANGE_UINT,
-    UNITY_DISPLAY_STYLE_UINT16   = 2 + UNITY_DISPLAY_RANGE_UINT,
-    UNITY_DISPLAY_STYLE_UINT32   = 4 + UNITY_DISPLAY_RANGE_UINT,
-#ifdef UNITY_SUPPORT_64
-    UNITY_DISPLAY_STYLE_UINT64   = 8 + UNITY_DISPLAY_RANGE_UINT,
-#endif
-
-    UNITY_DISPLAY_STYLE_HEX8     = 1 + UNITY_DISPLAY_RANGE_HEX,
-    UNITY_DISPLAY_STYLE_HEX16    = 2 + UNITY_DISPLAY_RANGE_HEX,
-    UNITY_DISPLAY_STYLE_HEX32    = 4 + UNITY_DISPLAY_RANGE_HEX,
-#ifdef UNITY_SUPPORT_64
-    UNITY_DISPLAY_STYLE_HEX64    = 8 + UNITY_DISPLAY_RANGE_HEX,
-#endif
-
-    UNITY_DISPLAY_STYLE_UNKNOWN
-} UNITY_DISPLAY_STYLE_T;
-
-typedef enum
-{
-    UNITY_EQUAL_TO         = 1,
-    UNITY_GREATER_THAN     = 2,
-    UNITY_GREATER_OR_EQUAL = 2 + UNITY_EQUAL_TO,
-    UNITY_SMALLER_THAN     = 4,
-    UNITY_SMALLER_OR_EQUAL = 4 + UNITY_EQUAL_TO
-} UNITY_COMPARISON_T;
-
-#ifndef UNITY_EXCLUDE_FLOAT
-typedef enum UNITY_FLOAT_TRAIT
-{
-    UNITY_FLOAT_IS_NOT_INF       = 0,
-    UNITY_FLOAT_IS_INF,
-    UNITY_FLOAT_IS_NOT_NEG_INF,
-    UNITY_FLOAT_IS_NEG_INF,
-    UNITY_FLOAT_IS_NOT_NAN,
-    UNITY_FLOAT_IS_NAN,
-    UNITY_FLOAT_IS_NOT_DET,
-    UNITY_FLOAT_IS_DET,
-    UNITY_FLOAT_INVALID_TRAIT
-} UNITY_FLOAT_TRAIT_T;
-#endif
-
-typedef enum
-{
-    UNITY_ARRAY_TO_VAL = 0,
-    UNITY_ARRAY_TO_ARRAY
-} UNITY_FLAGS_T;
-
-struct UNITY_STORAGE_T
-{
-    const char* TestFile;
-    const char* CurrentTestName;
-#ifndef UNITY_EXCLUDE_DETAILS
-    const char* CurrentDetail1;
-    const char* CurrentDetail2;
-#endif
-    UNITY_LINE_TYPE CurrentTestLineNumber;
-    UNITY_COUNTER_TYPE NumberOfTests;
-    UNITY_COUNTER_TYPE TestFailures;
-    UNITY_COUNTER_TYPE TestIgnores;
-    UNITY_COUNTER_TYPE CurrentTestFailed;
-    UNITY_COUNTER_TYPE CurrentTestIgnored;
-#ifdef UNITY_INCLUDE_EXEC_TIME
-    UNITY_COUNTER_TYPE CurrentTestStartTime;
-    UNITY_COUNTER_TYPE CurrentTestStopTime;
-#endif
-#ifndef UNITY_EXCLUDE_SETJMP_H
-    jmp_buf AbortFrame;
-#endif
-};
-
-extern struct UNITY_STORAGE_T Unity;
-
-/*-------------------------------------------------------
- * Test Suite Management
- *-------------------------------------------------------*/
-
-void UnityBegin(const char* filename);
-int  UnityEnd(void);
-void UnityConcludeTest(void);
-void UnityDefaultTestRun(UnityTestFunction Func, const char* FuncName, const int FuncLineNum);
-
-/*-------------------------------------------------------
- * Details Support
- *-------------------------------------------------------*/
-
-#ifdef UNITY_EXCLUDE_DETAILS
-#define UNITY_CLR_DETAILS()
-#define UNITY_SET_DETAIL(d1)
-#define UNITY_SET_DETAILS(d1,d2)
-#else
-#define UNITY_CLR_DETAILS()      { Unity.CurrentDetail1 = 0;   Unity.CurrentDetail2 = 0;  }
-#define UNITY_SET_DETAIL(d1)     { Unity.CurrentDetail1 = (d1);  Unity.CurrentDetail2 = 0;  }
-#define UNITY_SET_DETAILS(d1,d2) { Unity.CurrentDetail1 = (d1);  Unity.CurrentDetail2 = (d2); }
-
-#ifndef UNITY_DETAIL1_NAME
-#define UNITY_DETAIL1_NAME "Function"
-#endif
-
-#ifndef UNITY_DETAIL2_NAME
-#define UNITY_DETAIL2_NAME "Argument"
-#endif
-#endif
-
-/*-------------------------------------------------------
- * Test Output
- *-------------------------------------------------------*/
-
-void UnityPrint(const char* string);
-void UnityPrintLen(const char* string, const UNITY_UINT32 length);
-void UnityPrintMask(const UNITY_UINT mask, const UNITY_UINT number);
-void UnityPrintNumberByStyle(const UNITY_INT number, const UNITY_DISPLAY_STYLE_T style);
-void UnityPrintNumber(const UNITY_INT number_to_print);
-void UnityPrintNumberUnsigned(const UNITY_UINT number);
-void UnityPrintNumberHex(const UNITY_UINT number, const char nibbles_to_print);
-
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-void UnityPrintFloat(const UNITY_DOUBLE input_number);
-#endif
-
-/*-------------------------------------------------------
- * Test Assertion Functions
- *-------------------------------------------------------
- *  Use the macros below this section instead of calling
- *  these directly. The macros have a consistent naming
- *  convention and will pull in file and line information
- *  for you. */
-
-void UnityAssertEqualNumber(const UNITY_INT expected,
-                            const UNITY_INT actual,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber,
-                            const UNITY_DISPLAY_STYLE_T style);
-
-void UnityAssertGreaterOrLessOrEqualNumber(const UNITY_INT threshold,
-                                           const UNITY_INT actual,
-                                           const UNITY_COMPARISON_T compare,
-                                           const char *msg,
-                                           const UNITY_LINE_TYPE lineNumber,
-                                           const UNITY_DISPLAY_STYLE_T style);
-
-void UnityAssertEqualIntArray(UNITY_INTERNAL_PTR expected,
-                              UNITY_INTERNAL_PTR actual,
-                              const UNITY_UINT32 num_elements,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_DISPLAY_STYLE_T style,
-                              const UNITY_FLAGS_T flags);
-
-void UnityAssertBits(const UNITY_INT mask,
-                     const UNITY_INT expected,
-                     const UNITY_INT actual,
-                     const char* msg,
-                     const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualString(const char* expected,
-                            const char* actual,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualStringLen(const char* expected,
-                            const char* actual,
-                            const UNITY_UINT32 length,
-                            const char* msg,
-                            const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualStringArray( UNITY_INTERNAL_PTR expected,
-                                  const char** actual,
-                                  const UNITY_UINT32 num_elements,
-                                  const char* msg,
-                                  const UNITY_LINE_TYPE lineNumber,
-                                  const UNITY_FLAGS_T flags);
-
-void UnityAssertEqualMemory( UNITY_INTERNAL_PTR expected,
-                             UNITY_INTERNAL_PTR actual,
-                             const UNITY_UINT32 length,
-                             const UNITY_UINT32 num_elements,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber,
-                             const UNITY_FLAGS_T flags);
-
-void UnityAssertNumbersWithin(const UNITY_UINT delta,
-                              const UNITY_INT expected,
-                              const UNITY_INT actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_DISPLAY_STYLE_T style);
-
-void UnityFail(const char* msg, const UNITY_LINE_TYPE line);
-
-void UnityIgnore(const char* msg, const UNITY_LINE_TYPE line);
-
-#ifndef UNITY_EXCLUDE_FLOAT
-void UnityAssertFloatsWithin(const UNITY_FLOAT delta,
-                             const UNITY_FLOAT expected,
-                             const UNITY_FLOAT actual,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualFloatArray(UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* expected,
-                                UNITY_PTR_ATTRIBUTE const UNITY_FLOAT* actual,
-                                const UNITY_UINT32 num_elements,
-                                const char* msg,
-                                const UNITY_LINE_TYPE lineNumber,
-                                const UNITY_FLAGS_T flags);
-
-void UnityAssertFloatSpecial(const UNITY_FLOAT actual,
-                             const char* msg,
-                             const UNITY_LINE_TYPE lineNumber,
-                             const UNITY_FLOAT_TRAIT_T style);
-#endif
-
-#ifndef UNITY_EXCLUDE_DOUBLE
-void UnityAssertDoublesWithin(const UNITY_DOUBLE delta,
-                              const UNITY_DOUBLE expected,
-                              const UNITY_DOUBLE actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber);
-
-void UnityAssertEqualDoubleArray(UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* expected,
-                                 UNITY_PTR_ATTRIBUTE const UNITY_DOUBLE* actual,
-                                 const UNITY_UINT32 num_elements,
-                                 const char* msg,
-                                 const UNITY_LINE_TYPE lineNumber,
-                                 const UNITY_FLAGS_T flags);
-
-void UnityAssertDoubleSpecial(const UNITY_DOUBLE actual,
-                              const char* msg,
-                              const UNITY_LINE_TYPE lineNumber,
-                              const UNITY_FLOAT_TRAIT_T style);
-#endif
-
-/*-------------------------------------------------------
- * Helpers
- *-------------------------------------------------------*/
-
-UNITY_INTERNAL_PTR UnityNumToPtr(const UNITY_INT num, const UNITY_UINT8 size);
-#ifndef UNITY_EXCLUDE_FLOAT
-UNITY_INTERNAL_PTR UnityFloatToPtr(const float num);
-#endif
-#ifndef UNITY_EXCLUDE_DOUBLE
-UNITY_INTERNAL_PTR UnityDoubleToPtr(const double num);
-#endif
-
-/*-------------------------------------------------------
- * Error Strings We Might Need
- *-------------------------------------------------------*/
-
-extern const char UnityStrErrFloat[];
-extern const char UnityStrErrDouble[];
-extern const char UnityStrErr64[];
-
-/*-------------------------------------------------------
- * Test Running Macros
- *-------------------------------------------------------*/
-
-#ifndef UNITY_EXCLUDE_SETJMP_H
-#define TEST_PROTECT() (setjmp(Unity.AbortFrame) == 0)
-#define TEST_ABORT() longjmp(Unity.AbortFrame, 1)
-#else
-#define TEST_PROTECT() 1
-#define TEST_ABORT() return
-#endif
-
-#ifndef UNITY_EXCLUDE_TIME_H
-#define UNITY_CLOCK_MS() (UNITY_COUNTER_TYPE)((clock() * 1000) / CLOCKS_PER_SEC)
-#else
-#define UNITY_CLOCK_MS()
-#endif
-
-/* This tricky series of macros gives us an optional line argument to treat it as RUN_TEST(func, num=__LINE__) */
-#ifndef RUN_TEST
-#ifdef __STDC_VERSION__
-#if __STDC_VERSION__ >= 199901L
-#define RUN_TEST(...) UnityDefaultTestRun(RUN_TEST_FIRST(__VA_ARGS__), RUN_TEST_SECOND(__VA_ARGS__))
-#define RUN_TEST_FIRST(...) RUN_TEST_FIRST_HELPER(__VA_ARGS__, throwaway)
-#define RUN_TEST_FIRST_HELPER(first, ...) (first), #first
-#define RUN_TEST_SECOND(...) RUN_TEST_SECOND_HELPER(__VA_ARGS__, __LINE__, throwaway)
-#define RUN_TEST_SECOND_HELPER(first, second, ...) (second)
-#endif
-#endif
-#endif
-
-/* If we can't do the tricky version, we'll just have to require them to always include the line number */
-#ifndef RUN_TEST
-#ifdef CMOCK
-#define RUN_TEST(func, num) UnityDefaultTestRun(func, #func, num)
-#else
-#define RUN_TEST(func) UnityDefaultTestRun(func, #func, __LINE__)
-#endif
-#endif
-
-#define TEST_LINE_NUM (Unity.CurrentTestLineNumber)
-#define TEST_IS_IGNORED (Unity.CurrentTestIgnored)
-#define UNITY_NEW_TEST(a) \
-    Unity.CurrentTestName = (a); \
-    Unity.CurrentTestLineNumber = (UNITY_LINE_TYPE)(__LINE__); \
-    Unity.NumberOfTests++;
-
-#ifndef UNITY_BEGIN
-#define UNITY_BEGIN() UnityBegin(__FILE__)
-#endif
-
-#ifndef UNITY_END
-#define UNITY_END() UnityEnd()
-#endif
-
-/*-----------------------------------------------
- * Command Line Argument Support
- *-----------------------------------------------*/
-
-#ifdef UNITY_USE_COMMAND_LINE_ARGS
-int UnityParseOptions(int argc, char** argv);
-int UnityTestMatches(void);
-#endif
-
-/*-------------------------------------------------------
- * Basic Fail and Ignore
- *-------------------------------------------------------*/
-
-#define UNITY_TEST_FAIL(line, message)   UnityFail(   (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_IGNORE(line, message) UnityIgnore( (message), (UNITY_LINE_TYPE)(line))
-
-/*-------------------------------------------------------
- * Test Asserts
- *-------------------------------------------------------*/
-
-#define UNITY_TEST_ASSERT(condition, line, message)                                              if (condition) {} else {UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), (message));}
-#define UNITY_TEST_ASSERT_NULL(pointer, line, message)                                           UNITY_TEST_ASSERT(((pointer) == NULL),  (UNITY_LINE_TYPE)(line), (message))
-#define UNITY_TEST_ASSERT_NOT_NULL(pointer, line, message)                                       UNITY_TEST_ASSERT(((pointer) != NULL),  (UNITY_LINE_TYPE)(line), (message))
-
-#define UNITY_TEST_ASSERT_EQUAL_INT(expected, actual, line, message)                             UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_EQUAL_INT8(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_EQUAL_INT16(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT16)(expected), (UNITY_INT)(UNITY_INT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_EQUAL_INT32(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT32)(expected), (UNITY_INT)(UNITY_INT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_EQUAL_UINT(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_EQUAL_UINT8(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_UINT8 )(expected), (UNITY_INT)(UNITY_UINT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_EQUAL_UINT16(expected, actual, line, message)                          UnityAssertEqualNumber((UNITY_INT)(UNITY_UINT16)(expected), (UNITY_INT)(UNITY_UINT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_EQUAL_UINT32(expected, actual, line, message)                          UnityAssertEqualNumber((UNITY_INT)(UNITY_UINT32)(expected), (UNITY_INT)(UNITY_UINT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_EQUAL_HEX8(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_EQUAL_HEX16(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT16)(expected), (UNITY_INT)(UNITY_INT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_EQUAL_HEX32(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(UNITY_INT32)(expected), (UNITY_INT)(UNITY_INT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-#define UNITY_TEST_ASSERT_BITS(mask, expected, actual, line, message)                            UnityAssertBits((UNITY_INT)(mask), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line))
-
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT8(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT16(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT32(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT8(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT16(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT32(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX32(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT(threshold, actual, line, message)                 UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT8(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT16(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT32(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT(threshold, actual, line, message)                 UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold), (UNITY_INT)(UNITY_INT32)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT8(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT16(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT32(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX8(threshold, actual, line, message)                UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX16(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX32(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_INT_WITHIN(delta, expected, actual, line, message)                     UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
-#define UNITY_TEST_ASSERT_INT8_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
-#define UNITY_TEST_ASSERT_INT16_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT16)(delta), (UNITY_INT)(UNITY_INT16)(expected), (UNITY_INT)(UNITY_INT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
-#define UNITY_TEST_ASSERT_INT32_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT32)(delta), (UNITY_INT)(UNITY_INT32)(expected), (UNITY_INT)(UNITY_INT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
-#define UNITY_TEST_ASSERT_UINT_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
-#define UNITY_TEST_ASSERT_UINT8_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
-#define UNITY_TEST_ASSERT_UINT16_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((UNITY_UINT16)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
-#define UNITY_TEST_ASSERT_UINT32_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((UNITY_UINT32)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
-#define UNITY_TEST_ASSERT_HEX8_WITHIN(delta, expected, actual, line, message)                    UnityAssertNumbersWithin((UNITY_UINT8 )(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
-#define UNITY_TEST_ASSERT_HEX16_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT16)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT16)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
-#define UNITY_TEST_ASSERT_HEX32_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((UNITY_UINT32)(delta), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(expected), (UNITY_INT)(UNITY_UINT)(UNITY_UINT32)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
-
-#define UNITY_TEST_ASSERT_EQUAL_PTR(expected, actual, line, message)                             UnityAssertEqualNumber((UNITY_PTR_TO_INT)(expected), (UNITY_PTR_TO_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_POINTER)
-#define UNITY_TEST_ASSERT_EQUAL_STRING(expected, actual, line, message)                          UnityAssertEqualString((const char*)(expected), (const char*)(actual), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_STRING_LEN(expected, actual, len, line, message)                 UnityAssertEqualStringLen((const char*)(expected), (const char*)(actual), (UNITY_UINT32)(len), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_MEMORY(expected, actual, len, line, message)                     UnityAssertEqualMemory((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(len), 1, (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-
-#define UNITY_TEST_ASSERT_EQUAL_INT_ARRAY(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT,     UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_INT8_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8,    UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_INT16_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_INT32_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT,    UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT8_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT16_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT32_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX8_ARRAY(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8,    UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX16_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX32_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32,   UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_PTR_ARRAY(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_POINTER, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_STRING_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualStringArray((UNITY_INTERNAL_PTR)(expected), (const char**)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY(expected, actual, len, num_elements, line, message) UnityAssertEqualMemory((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(len), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT(expected, actual, num_elements, line, message)          UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)              (expected), sizeof(int)),  (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT,     UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT8(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT8  )(expected), 1),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8,    UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT16(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT16 )(expected), 2),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT32(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT32 )(expected), 4),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)              (expected), sizeof(unsigned int)), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT,    UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT8(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT8 )(expected), 1),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT16(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT16)(expected), 2),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT32(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT32)(expected), 4),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX8(expected, actual, num_elements, line, message)         UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT8  )(expected), 1),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8,    UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX16(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT16 )(expected), 2),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX32(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT32 )(expected), 4),            (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32,   UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_PTR(expected, actual, num_elements, line, message)          UnityAssertEqualIntArray(UnityNumToPtr((UNITY_PTR_TO_INT)       (expected), sizeof(int*)), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_POINTER, UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_STRING(expected, actual, num_elements, line, message)       UnityAssertEqualStringArray((UNITY_INTERNAL_PTR)(expected), (const char**)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_MEMORY(expected, actual, len, num_elements, line, message)  UnityAssertEqualMemory((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(len), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-
-#ifdef UNITY_SUPPORT_64
-#define UNITY_TEST_ASSERT_EQUAL_INT64(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64(expected, actual, line, message)                          UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64(expected, actual, line, message)                           UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray((UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64,  UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_INT64(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT64)expected, 8), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_UINT64(expected, actual, num_elements, line, message)       UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_UINT64)expected, 8), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64, UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_HEX64(expected, actual, num_elements, line, message)        UnityAssertEqualIntArray(UnityNumToPtr((UNITY_INT)(UNITY_INT64)expected, 8), (UNITY_INTERNAL_PTR)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64,  UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_INT64_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_UINT64_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_HEX64_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT64(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64(threshold, actual, line, message)              UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64(threshold, actual, line, message)               UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_SMALLER_OR_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
-#else
-#define UNITY_TEST_ASSERT_EQUAL_INT64(expected, actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64(expected, actual, line, message)                          UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64(expected, actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_INT64_ARRAY(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_UINT64_ARRAY(expected, actual, num_elements, line, message)      UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_EQUAL_HEX64_ARRAY(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_INT64_WITHIN(delta, expected, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_UINT64_WITHIN(delta, expected, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_HEX64_WITHIN(delta, expected, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_INT64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_INT64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_UINT64(threshold, actual, line, message)              UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_GREATER_OR_EQUAL_HEX64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_INT64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_UINT64(threshold, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_THAN_HEX64(threshold, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_INT64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_UINT64(threshold, actual, line, message)              UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#define UNITY_TEST_ASSERT_SMALLER_OR_EQUAL_HEX64(threshold, actual, line, message)               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErr64)
-#endif
-
-#ifdef UNITY_EXCLUDE_FLOAT
-#define UNITY_TEST_ASSERT_FLOAT_WITHIN(delta, expected, actual, line, message)                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT(expected, actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT(expected, actual, num_elements, line, message)        UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_INF(actual, line, message)                                    UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF(actual, line, message)                                UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NAN(actual, line, message)                                    UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE(actual, line, message)                            UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF(actual, line, message)                                UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF(actual, line, message)                            UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN(actual, line, message)                                UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE(actual, line, message)                        UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrFloat)
-#else
-#define UNITY_TEST_ASSERT_FLOAT_WITHIN(delta, expected, actual, line, message)                   UnityAssertFloatsWithin((UNITY_FLOAT)(delta), (UNITY_FLOAT)(expected), (UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line))
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT(expected, actual, line, message)                           UNITY_TEST_ASSERT_FLOAT_WITHIN((UNITY_FLOAT)(expected) * (UNITY_FLOAT)UNITY_FLOAT_PRECISION, (UNITY_FLOAT)(expected), (UNITY_FLOAT)(actual), (UNITY_LINE_TYPE)(line), (message))
-#define UNITY_TEST_ASSERT_EQUAL_FLOAT_ARRAY(expected, actual, num_elements, line, message)       UnityAssertEqualFloatArray((UNITY_FLOAT*)(expected), (UNITY_FLOAT*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_FLOAT(expected, actual, num_elements, line, message)        UnityAssertEqualFloatArray(UnityFloatToPtr(expected), (UNITY_FLOAT*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)(line), UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_FLOAT_IS_INF(actual, line, message)                                    UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NEG_INF(actual, line, message)                                UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NEG_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NAN(actual, line, message)                                    UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NAN)
-#define UNITY_TEST_ASSERT_FLOAT_IS_DETERMINATE(actual, line, message)                            UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_DET)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_INF(actual, line, message)                                UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NEG_INF(actual, line, message)                            UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NEG_INF)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_NAN(actual, line, message)                                UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NAN)
-#define UNITY_TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE(actual, line, message)                        UnityAssertFloatSpecial((UNITY_FLOAT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_DET)
-#endif
-
-#ifdef UNITY_EXCLUDE_DOUBLE
-#define UNITY_TEST_ASSERT_DOUBLE_WITHIN(delta, expected, actual, line, message)                  UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE(expected, actual, line, message)                          UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY(expected, actual, num_elements, line, message)      UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE(expected, actual, num_elements, line, message)       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_INF(actual, line, message)                                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF(actual, line, message)                               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NAN(actual, line, message)                                   UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE(actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF(actual, line, message)                               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF(actual, line, message)                           UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN(actual, line, message)                               UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual, line, message)                       UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), UnityStrErrDouble)
-#else
-#define UNITY_TEST_ASSERT_DOUBLE_WITHIN(delta, expected, actual, line, message)                  UnityAssertDoublesWithin((UNITY_DOUBLE)(delta), (UNITY_DOUBLE)(expected), (UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)line)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE(expected, actual, line, message)                          UNITY_TEST_ASSERT_DOUBLE_WITHIN((UNITY_DOUBLE)(expected) * (UNITY_DOUBLE)UNITY_DOUBLE_PRECISION, (UNITY_DOUBLE)expected, (UNITY_DOUBLE)actual, (UNITY_LINE_TYPE)(line), message)
-#define UNITY_TEST_ASSERT_EQUAL_DOUBLE_ARRAY(expected, actual, num_elements, line, message)      UnityAssertEqualDoubleArray((UNITY_DOUBLE*)(expected), (UNITY_DOUBLE*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)line, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_EACH_EQUAL_DOUBLE(expected, actual, num_elements, line, message)       UnityAssertEqualDoubleArray(UnityDoubleToPtr(expected), (UNITY_DOUBLE*)(actual), (UNITY_UINT32)(num_elements), (message), (UNITY_LINE_TYPE)line, UNITY_ARRAY_TO_VAL)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_INF(actual, line, message)                                   UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NEG_INF(actual, line, message)                               UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NEG_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NAN(actual, line, message)                                   UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NAN)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_DETERMINATE(actual, line, message)                           UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_DET)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_INF(actual, line, message)                               UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF(actual, line, message)                           UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NEG_INF)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_NAN(actual, line, message)                               UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_NAN)
-#define UNITY_TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE(actual, line, message)                       UnityAssertDoubleSpecial((UNITY_DOUBLE)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_FLOAT_IS_NOT_DET)
-#endif
-
-/* End of UNITY_INTERNALS_H */
-#endif
diff --git a/tools/sdk/include/unity/unity_test_runner.h b/tools/sdk/include/unity/unity_test_runner.h
deleted file mode 100644
index 8f41eb83d7a..00000000000
--- a/tools/sdk/include/unity/unity_test_runner.h
+++ /dev/null
@@ -1,174 +0,0 @@
-// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include <stdint.h>
-#include <stdbool.h>
-
-// This file gets included from unity.h via unity_internals.h via unity_config.h
-// It is inside #ifdef __cplusplus / extern "C" block, so we can
-// only use C features here
-
-// Define helpers to register test cases from multiple files
-#define UNITY_EXPAND2(a, b) a ## b
-#define UNITY_EXPAND(a, b) UNITY_EXPAND2(a, b)
-#define UNITY_TEST_UID(what) UNITY_EXPAND(what, __LINE__)
-
-#define UNITY_TEST_REG_HELPER reg_helper ## UNITY_TEST_UID
-#define UNITY_TEST_DESC_UID desc ## UNITY_TEST_UID
-
-
-// get count of __VA_ARGS__
-#define PP_NARG(...) \
-         PP_NARG_(__VA_ARGS__,PP_RSEQ_N())
-#define PP_NARG_(...) \
-         PP_ARG_N(__VA_ARGS__)
-#define PP_ARG_N( \
-          _1, _2, _3, _4, _5, _6, _7, _8, _9, N, ...) N
-#define PP_RSEQ_N() 9,8,7,6,5,4,3,2,1,0
-
-// support max 5 test func now
-#define FN_NAME_SET_1(a)                {#a}
-#define FN_NAME_SET_2(a, b)             {#a, #b}
-#define FN_NAME_SET_3(a, b, c)          {#a, #b, #c}
-#define FN_NAME_SET_4(a, b, c, d)       {#a, #b, #c, #d}
-#define FN_NAME_SET_5(a, b, c, d, e)    {#a, #b, #c, #d, #e}
-
-#define FN_NAME_SET2(n) FN_NAME_SET_##n
-#define FN_NAME_SET(n, ...) FN_NAME_SET2(n)(__VA_ARGS__)
-
-#define UNITY_TEST_FN_SET(...)  \
-    static test_func UNITY_TEST_UID(test_functions)[] = {__VA_ARGS__}; \
-    static const char* UNITY_TEST_UID(test_fn_name)[] = FN_NAME_SET(PP_NARG(__VA_ARGS__), __VA_ARGS__)
-
-
-typedef void (* test_func)(void);
-
-typedef struct test_desc_t
-{
-    const char* name;
-    const char* desc;
-    test_func* fn;
-    const char* file;
-    int line;
-    uint8_t test_fn_count;
-    const char ** test_fn_name;
-    struct test_desc_t* next;
-} test_desc_t;
-
-void unity_testcase_register(test_desc_t* desc);
-
-
-/*  Test case macro, a-la CATCH framework.
-    First argument is a free-form description,
-    second argument is (by convention) a list of identifiers, each one in square brackets.
-    Identifiers are used to group related tests, or tests with specific properties.
-    Use like:
-
-    TEST_CASE("Frobnicator forbnicates", "[frobnicator][rom]")
-    {
-        // test goes here
-    }
-*/
-
-#define TEST_CASE(name_, desc_) \
-    static void UNITY_TEST_UID(test_func_) (void); \
-    static void __attribute__((constructor)) UNITY_TEST_UID(test_reg_helper_) () \
-    { \
-        static test_func test_fn_[] = {&UNITY_TEST_UID(test_func_)}; \
-        static test_desc_t UNITY_TEST_UID(test_desc_) = { \
-            .name = name_, \
-            .desc = desc_, \
-            .fn = test_fn_, \
-            .file = __FILE__, \
-            .line = __LINE__, \
-            .test_fn_count = 1, \
-            .test_fn_name = NULL, \
-            .next = NULL \
-        }; \
-        unity_testcase_register( & UNITY_TEST_UID(test_desc_) ); \
-    }\
-    static void UNITY_TEST_UID(test_func_) (void)
-
-
-/*
- * Multiple stages test cases will handle the case that test steps are separated by DUT reset.
- * e.g: we want to verify some function after SW reset, WDT reset or deep sleep reset.
- *
- * First argument is a free-form description,
- * second argument is (by convention) a list of identifiers, each one in square brackets.
- * subsequent arguments are names test functions separated by reset.
- * e.g:
- * TEST_CASE_MULTIPLE_STAGES("run light sleep after deep sleep","[sleep]", goto_deepsleep, light_sleep_after_deep_sleep_wakeup);
- * */
-
-#define TEST_CASE_MULTIPLE_STAGES(name_, desc_, ...) \
-    UNITY_TEST_FN_SET(__VA_ARGS__); \
-    static void __attribute__((constructor)) UNITY_TEST_UID(test_reg_helper_) () \
-    { \
-        static test_desc_t UNITY_TEST_UID(test_desc_) = { \
-            .name = name_, \
-            .desc = desc_"[multi_stage]", \
-            .fn = UNITY_TEST_UID(test_functions), \
-            .file = __FILE__, \
-            .line = __LINE__, \
-            .test_fn_count = PP_NARG(__VA_ARGS__), \
-            .test_fn_name = UNITY_TEST_UID(test_fn_name), \
-            .next = NULL \
-        }; \
-        unity_testcase_register( & UNITY_TEST_UID(test_desc_) ); \
-    }
-
-/*
- * First argument is a free-form description,
- * second argument is (by convention) a list of identifiers, each one in square brackets.
- * subsequent arguments are names of test functions for different DUTs
- * e.g:
- * TEST_CASE_MULTIPLE_DEVICES("master and slave spi","[spi][test_env=UT_T2_1]", master_test, slave_test);
- * */
-
-#define TEST_CASE_MULTIPLE_DEVICES(name_, desc_, ...) \
-    UNITY_TEST_FN_SET(__VA_ARGS__); \
-    static void __attribute__((constructor)) UNITY_TEST_UID(test_reg_helper_) () \
-    { \
-        static test_desc_t UNITY_TEST_UID(test_desc_) = { \
-            .name = name_, \
-            .desc = desc_"[multi_device]", \
-            .fn = UNITY_TEST_UID(test_functions), \
-            .file = __FILE__, \
-            .line = __LINE__, \
-            .test_fn_count = PP_NARG(__VA_ARGS__), \
-            .test_fn_name = UNITY_TEST_UID(test_fn_name), \
-            .next = NULL \
-        }; \
-        unity_testcase_register( & UNITY_TEST_UID(test_desc_) ); \
-    }
-
-/**
- * Note: initialization of test_desc_t fields above has to be done exactly
- * in the same order as the fields are declared in the structure.
- * Otherwise the initializer will not be valid in C++ (which doesn't
- * support designated initializers). G++ can parse the syntax, but
- * field names are treated as annotations and don't affect initialization
- * order. Also make sure all the fields are initialized.
- */
-
-void unity_run_test_by_name(const char *name);
-
-void unity_run_tests_by_tag(const char *tag, bool invert);
-
-void unity_run_all_tests();
-
-void unity_run_menu();
-
diff --git a/tools/sdk/include/vfs/esp_vfs.h b/tools/sdk/include/vfs/esp_vfs.h
deleted file mode 100644
index 35527d4f841..00000000000
--- a/tools/sdk/include/vfs/esp_vfs.h
+++ /dev/null
@@ -1,411 +0,0 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef __ESP_VFS_H__
-#define __ESP_VFS_H__
-
-#include <stdint.h>
-#include <stddef.h>
-#include <stdarg.h>
-#include <unistd.h>
-#include <utime.h>
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-#include "esp_err.h"
-#include <sys/types.h>
-#include <sys/reent.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-#include <sys/termios.h>
-#include <sys/poll.h>
-#include <dirent.h>
-#include <string.h>
-#include "sdkconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef _SYS_TYPES_FD_SET
-#error "VFS should be used with FD_SETSIZE and FD_SET from sys/types.h"
-#endif
-
-/**
- * Maximum number of (global) file descriptors.
- */
-#define MAX_FDS         FD_SETSIZE /* for compatibility with fd_set and select() */
-
-/**
- * Maximum length of path prefix (not including zero terminator)
- */
-#define ESP_VFS_PATH_MAX 15
-
-/**
- * Default value of flags member in esp_vfs_t structure.
- */
-#define ESP_VFS_FLAG_DEFAULT        0
-
-/**
- * Flag which indicates that FS needs extra context pointer in syscalls.
- */
-#define ESP_VFS_FLAG_CONTEXT_PTR    1
-
-/*
- * @brief VFS identificator used for esp_vfs_register_with_id()
- */
-typedef int esp_vfs_id_t;
-
-/**
- * @brief VFS definition structure
- *
- * This structure should be filled with pointers to corresponding
- * FS driver functions.
- *
- * VFS component will translate all FDs so that the filesystem implementation
- * sees them starting at zero. The caller sees a global FD which is prefixed
- * with an pre-filesystem-implementation.
- *
- * Some FS implementations expect some state (e.g. pointer to some structure)
- * to be passed in as a first argument. For these implementations,
- * populate the members of this structure which have _p suffix, set
- * flags member to ESP_VFS_FLAG_CONTEXT_PTR and provide the context pointer
- * to esp_vfs_register function.
- * If the implementation doesn't use this extra argument, populate the
- * members without _p suffix and set flags member to ESP_VFS_FLAG_DEFAULT.
- *
- * If the FS driver doesn't provide some of the functions, set corresponding
- * members to NULL.
- */
-typedef struct
-{
-    int flags;      /*!< ESP_VFS_FLAG_CONTEXT_PTR or ESP_VFS_FLAG_DEFAULT */
-    union {
-        ssize_t (*write_p)(void* p, int fd, const void * data, size_t size);
-        ssize_t (*write)(int fd, const void * data, size_t size);
-    };
-    union {
-        off_t (*lseek_p)(void* p, int fd, off_t size, int mode);
-        off_t (*lseek)(int fd, off_t size, int mode);
-    };
-    union {
-        ssize_t (*read_p)(void* ctx, int fd, void * dst, size_t size);
-        ssize_t (*read)(int fd, void * dst, size_t size);
-    };
-    union {
-        int (*open_p)(void* ctx, const char * path, int flags, int mode);
-        int (*open)(const char * path, int flags, int mode);
-    };
-    union {
-        int (*close_p)(void* ctx, int fd);
-        int (*close)(int fd);
-    };
-    union {
-        int (*fstat_p)(void* ctx, int fd, struct stat * st);
-        int (*fstat)(int fd, struct stat * st);
-    };
-    union {
-        int (*stat_p)(void* ctx, const char * path, struct stat * st);
-        int (*stat)(const char * path, struct stat * st);
-    };
-    union {
-        int (*link_p)(void* ctx, const char* n1, const char* n2);
-        int (*link)(const char* n1, const char* n2);
-    };
-    union {
-        int (*unlink_p)(void* ctx, const char *path);
-        int (*unlink)(const char *path);
-    };
-    union {
-        int (*rename_p)(void* ctx, const char *src, const char *dst);
-        int (*rename)(const char *src, const char *dst);
-    };
-    union {
-        DIR* (*opendir_p)(void* ctx, const char* name);
-        DIR* (*opendir)(const char* name);
-    };
-    union {
-        struct dirent* (*readdir_p)(void* ctx, DIR* pdir);
-        struct dirent* (*readdir)(DIR* pdir);
-    };
-    union {
-        int (*readdir_r_p)(void* ctx, DIR* pdir, struct dirent* entry, struct dirent** out_dirent);
-        int (*readdir_r)(DIR* pdir, struct dirent* entry, struct dirent** out_dirent);
-    };
-    union {
-        long (*telldir_p)(void* ctx, DIR* pdir);
-        long (*telldir)(DIR* pdir);
-    };
-    union {
-        void (*seekdir_p)(void* ctx, DIR* pdir, long offset);
-        void (*seekdir)(DIR* pdir, long offset);
-    };
-    union {
-        int (*closedir_p)(void* ctx, DIR* pdir);
-        int (*closedir)(DIR* pdir);
-    };
-    union {
-        int (*mkdir_p)(void* ctx, const char* name, mode_t mode);
-        int (*mkdir)(const char* name, mode_t mode);
-    };
-    union {
-        int (*rmdir_p)(void* ctx, const char* name);
-        int (*rmdir)(const char* name);
-    };
-    union {
-        int (*fcntl_p)(void* ctx, int fd, int cmd, va_list args);
-        int (*fcntl)(int fd, int cmd, va_list args);
-    };
-    union {
-        int (*ioctl_p)(void* ctx, int fd, int cmd, va_list args);
-        int (*ioctl)(int fd, int cmd, va_list args);
-    };
-    union {
-        int (*fsync_p)(void* ctx, int fd);
-        int (*fsync)(int fd);
-    };
-    union {
-        int (*access_p)(void* ctx, const char *path, int amode);
-        int (*access)(const char *path, int amode);
-    };
-    union {
-        int (*truncate_p)(void* ctx, const char *path, off_t length);
-        int (*truncate)(const char *path, off_t length);
-    };
-    union {
-        int (*utime_p)(void* ctx, const char *path, const struct utimbuf *times);
-        int (*utime)(const char *path, const struct utimbuf *times);
-    };
-#ifdef CONFIG_SUPPORT_TERMIOS
-    union {
-        int (*tcsetattr_p)(void *ctx, int fd, int optional_actions, const struct termios *p);
-        int (*tcsetattr)(int fd, int optional_actions, const struct termios *p);
-    };
-    union {
-        int (*tcgetattr_p)(void *ctx, int fd, struct termios *p);
-        int (*tcgetattr)(int fd, struct termios *p);
-    };
-    union {
-        int (*tcdrain_p)(void *ctx, int fd);
-        int (*tcdrain)(int fd);
-    };
-    union {
-        int (*tcflush_p)(void *ctx, int fd, int select);
-        int (*tcflush)(int fd, int select);
-    };
-    union {
-        int (*tcflow_p)(void *ctx, int fd, int action);
-        int (*tcflow)(int fd, int action);
-    };
-    union {
-        pid_t (*tcgetsid_p)(void *ctx, int fd);
-        pid_t (*tcgetsid)(int fd);
-    };
-    union {
-        int (*tcsendbreak_p)(void *ctx, int fd, int duration);
-        int (*tcsendbreak)(int fd, int duration);
-    };
-#endif // CONFIG_SUPPORT_TERMIOS
-
-    /** start_select is called for setting up synchronous I/O multiplexing of the desired file descriptors in the given VFS */
-    esp_err_t (*start_select)(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, SemaphoreHandle_t *signal_sem);
-    /** socket select function for socket FDs with the functionality of POSIX select(); this should be set only for the socket VFS */
-    int (*socket_select)(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds, struct timeval *timeout);
-    /** called by VFS to interrupt the socket_select call when select is activated from a non-socket VFS driver; set only for the socket driver */
-    void (*stop_socket_select)();
-    /** stop_socket_select which can be called from ISR; set only for the socket driver */
-    void (*stop_socket_select_isr)(BaseType_t *woken);
-    /** end_select is called to stop the I/O multiplexing and deinitialize the environment created by start_select for the given VFS */
-    void* (*get_socket_select_semaphore)();
-    /** get_socket_select_semaphore returns semaphore allocated in the socket driver; set only for the socket driver */
-    void (*end_select)();
-} esp_vfs_t;
-
-
-/**
- * Register a virtual filesystem for given path prefix.
- *
- * @param base_path  file path prefix associated with the filesystem.
- *                   Must be a zero-terminated C string, up to ESP_VFS_PATH_MAX
- *                   characters long, and at least 2 characters long.
- *                   Name must start with a "/" and must not end with "/".
- *                   For example, "/data" or "/dev/spi" are valid.
- *                   These VFSes would then be called to handle file paths such as
- *                   "/data/myfile.txt" or "/dev/spi/0".
- * @param vfs  Pointer to esp_vfs_t, a structure which maps syscalls to
- *             the filesystem driver functions. VFS component doesn't
- *             assume ownership of this pointer.
- * @param ctx  If vfs->flags has ESP_VFS_FLAG_CONTEXT_PTR set, a pointer
- *             which should be passed to VFS functions. Otherwise, NULL.
- *
- * @return  ESP_OK if successful, ESP_ERR_NO_MEM if too many VFSes are
- *          registered.
- */
-esp_err_t esp_vfs_register(const char* base_path, const esp_vfs_t* vfs, void* ctx);
-
-
-/**
- * Special case function for registering a VFS that uses a method other than
- * open() to open new file descriptors from the interval <min_fd; max_fd).
- *
- * This is a special-purpose function intended for registering LWIP sockets to VFS.
- *
- * @param vfs Pointer to esp_vfs_t. Meaning is the same as for esp_vfs_register().
- * @param ctx Pointer to context structure. Meaning is the same as for esp_vfs_register().
- * @param min_fd The smallest file descriptor this VFS will use.
- * @param max_fd Upper boundary for file descriptors this VFS will use (the biggest file descriptor plus one).
- *
- * @return  ESP_OK if successful, ESP_ERR_NO_MEM if too many VFSes are
- *          registered, ESP_ERR_INVALID_ARG if the file descriptor boundaries
- *          are incorrect.
- */
-esp_err_t esp_vfs_register_fd_range(const esp_vfs_t *vfs, void *ctx, int min_fd, int max_fd);
-
-/**
- * Special case function for registering a VFS that uses a method other than
- * open() to open new file descriptors. In comparison with
- * esp_vfs_register_fd_range, this function doesn't pre-registers an interval
- * of file descriptors. File descriptors can be registered later, by using
- * esp_vfs_register_fd.
- *
- * @param vfs Pointer to esp_vfs_t. Meaning is the same as for esp_vfs_register().
- * @param ctx Pointer to context structure. Meaning is the same as for esp_vfs_register().
- * @param vfs_id Here will be written the VFS ID which can be passed to
- *               esp_vfs_register_fd for registering file descriptors.
- *
- * @return  ESP_OK if successful, ESP_ERR_NO_MEM if too many VFSes are
- *          registered, ESP_ERR_INVALID_ARG if the file descriptor boundaries
- *          are incorrect.
- */
-esp_err_t esp_vfs_register_with_id(const esp_vfs_t *vfs, void *ctx, esp_vfs_id_t *vfs_id);
-
-/**
- * Unregister a virtual filesystem for given path prefix
- *
- * @param base_path  file prefix previously used in esp_vfs_register call
- * @return ESP_OK if successful, ESP_ERR_INVALID_STATE if VFS for given prefix
- *         hasn't been registered
- */
-esp_err_t esp_vfs_unregister(const char* base_path);
-
-/**
- * Special function for registering another file descriptor for a VFS registered
- * by esp_vfs_register_with_id.
- *
- * @param vfs_id VFS identificator returned by esp_vfs_register_with_id.
- * @param fd The registered file descriptor will be written to this address.
- *
- * @return  ESP_OK if the registration is successful,
- *          ESP_ERR_NO_MEM if too many file descriptors are registered,
- *          ESP_ERR_INVALID_ARG if the arguments are incorrect.
- */
-esp_err_t esp_vfs_register_fd(esp_vfs_id_t vfs_id, int *fd);
-
-/**
- * Special function for unregistering a file descriptor belonging to a VFS
- * registered by esp_vfs_register_with_id.
- *
- * @param vfs_id VFS identificator returned by esp_vfs_register_with_id.
- * @param fd File descriptor which should be unregistered.
- *
- * @return  ESP_OK if the registration is successful,
- *          ESP_ERR_INVALID_ARG if the arguments are incorrect.
- */
-esp_err_t esp_vfs_unregister_fd(esp_vfs_id_t vfs_id, int fd);
-
-/**
- * These functions are to be used in newlib syscall table. They will be called by
- * newlib when it needs to use any of the syscalls.
- */
-/**@{*/
-ssize_t esp_vfs_write(struct _reent *r, int fd, const void * data, size_t size);
-off_t esp_vfs_lseek(struct _reent *r, int fd, off_t size, int mode);
-ssize_t esp_vfs_read(struct _reent *r, int fd, void * dst, size_t size);
-int esp_vfs_open(struct _reent *r, const char * path, int flags, int mode);
-int esp_vfs_close(struct _reent *r, int fd);
-int esp_vfs_fstat(struct _reent *r, int fd, struct stat * st);
-int esp_vfs_stat(struct _reent *r, const char * path, struct stat * st);
-int esp_vfs_link(struct _reent *r, const char* n1, const char* n2);
-int esp_vfs_unlink(struct _reent *r, const char *path);
-int esp_vfs_rename(struct _reent *r, const char *src, const char *dst);
-int esp_vfs_utime(const char *path, const struct utimbuf *times);
-/**@}*/
-
-/**
- * @brief Synchronous I/O multiplexing which implements the functionality of POSIX select() for VFS
- * @param nfds      Specifies the range of descriptors which should be checked.
- *                  The first nfds descriptors will be checked in each set.
- * @param readfds   If not NULL, then points to a descriptor set that on input
- *                  specifies which descriptors should be checked for being
- *                  ready to read, and on output indicates which descriptors
- *                  are ready to read.
- * @param writefds  If not NULL, then points to a descriptor set that on input
- *                  specifies which descriptors should be checked for being
- *                  ready to write, and on output indicates which descriptors
- *                  are ready to write.
- * @param errorfds  If not NULL, then points to a descriptor set that on input
- *                  specifies which descriptors should be checked for error
- *                  conditions, and on output indicates which descriptors
- *                  have error conditions.
- * @param timeout   If not NULL, then points to timeval structure which
- *                  specifies the time period after which the functions should
- *                  time-out and return. If it is NULL, then the function will
- *                  not time-out.
- *
- * @return      The number of descriptors set in the descriptor sets, or -1
- *              when an error (specified by errno) have occurred.
- */
-int esp_vfs_select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds, struct timeval *timeout);
-
-/**
- * @brief Notification from a VFS driver about a read/write/error condition
- *
- * This function is called when the VFS driver detects a read/write/error
- * condition as it was requested by the previous call to start_select.
- *
- * @param signal_sem semaphore handle which was passed to the driver by the start_select call
- */
-void esp_vfs_select_triggered(SemaphoreHandle_t *signal_sem);
-
-/**
- * @brief Notification from a VFS driver about a read/write/error condition (ISR version)
- *
- * This function is called when the VFS driver detects a read/write/error
- * condition as it was requested by the previous call to start_select.
- *
- * @param signal_sem semaphore handle which was passed to the driver by the start_select call
- * @param woken is set to pdTRUE if the function wakes up a task with higher priority
- */
-void esp_vfs_select_triggered_isr(SemaphoreHandle_t *signal_sem, BaseType_t *woken);
-
-/**
- * @brief Implements the VFS layer for synchronous I/O multiplexing by poll()
- *
- * The implementation is based on esp_vfs_select. The parameters and return values are compatible with POSIX poll().
- *
- * @param fds         Pointer to the array containing file descriptors and events poll() should consider.
- * @param nfds        Number of items in the array fds.
- * @param timeout     Poll() should wait at least timeout milliseconds. If the value is 0 then it should return
- *                    immediately. If the value is -1 then it should wait (block) until the event occurs.
- *
- * @return            A positive return value indicates the number of file descriptors that have been selected. The 0
- *                    return value indicates a timed-out poll. -1 is return on failure and errno is set accordingly.
- *
- */
-int esp_vfs_poll(struct pollfd *fds, nfds_t nfds, int timeout);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif //__ESP_VFS_H__
diff --git a/tools/sdk/include/vfs/esp_vfs_dev.h b/tools/sdk/include/vfs/esp_vfs_dev.h
deleted file mode 100644
index 637f1449ff8..00000000000
--- a/tools/sdk/include/vfs/esp_vfs_dev.h
+++ /dev/null
@@ -1,127 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "esp_vfs.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Line ending settings
- */
-typedef enum {
-    ESP_LINE_ENDINGS_CRLF,//!< CR + LF
-    ESP_LINE_ENDINGS_CR,  //!< CR
-    ESP_LINE_ENDINGS_LF,  //!< LF
-} esp_line_endings_t;
-
-/**
- * @brief add /dev/uart virtual filesystem driver
- *
- * This function is called from startup code to enable serial output
- */
-void esp_vfs_dev_uart_register();
-
-/**
- * @brief Set the line endings expected to be received on UART
- *
- * This specifies the conversion between line endings received on UART and
- * newlines ('\n', LF) passed into stdin:
- *
- * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF
- * - ESP_LINE_ENDINGS_CR: convert CR to LF
- * - ESP_LINE_ENDINGS_LF: no modification
- *
- * @note this function is not thread safe w.r.t. reading from UART
- *
- * @param mode line endings expected on UART
- */
-void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode);
-
-/**
- * @brief Set the line endings to sent to UART
- *
- * This specifies the conversion between newlines ('\n', LF) on stdout and line
- * endings sent over UART:
- *
- * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF
- * - ESP_LINE_ENDINGS_CR: convert LF to CR
- * - ESP_LINE_ENDINGS_LF: no modification
- *
- * @note this function is not thread safe w.r.t. writing to UART
- *
- * @param mode line endings to send to UART
- */
-void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode);
-
-/**
- * @brief Set the line endings expected to be received on specified UART
- *
- * This specifies the conversion between line endings received on UART and
- * newlines ('\n', LF) passed into stdin:
- *
- * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF
- * - ESP_LINE_ENDINGS_CR: convert CR to LF
- * - ESP_LINE_ENDINGS_LF: no modification
- *
- * @note this function is not thread safe w.r.t. reading from UART
- *
- * @param uart_num the UART number
- * @param mode line endings to send to UART
- * @return  0 if successed, or -1
- *              when an error (specified by errno) have occurred.
- */
-int esp_vfs_dev_uart_port_set_rx_line_endings(int uart_num, esp_line_endings_t mode);
-
-/**
- * @brief Set the line endings to sent to specified UART
- *
- * This specifies the conversion between newlines ('\n', LF) on stdout and line
- * endings sent over UART:
- *
- * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF
- * - ESP_LINE_ENDINGS_CR: convert LF to CR
- * - ESP_LINE_ENDINGS_LF: no modification
- *
- * @note this function is not thread safe w.r.t. writing to UART
- *
- * @param uart_num the UART number
- * @param mode line endings to send to UART
-  * @return  0 if successed, or -1
- *              when an error (specified by errno) have occurred.
- */
-int esp_vfs_dev_uart_port_set_tx_line_endings(int uart_num, esp_line_endings_t mode);
-
-/**
- * @brief set VFS to use simple functions for reading and writing UART
- * Read is non-blocking, write is busy waiting until TX FIFO has enough space.
- * These functions are used by default.
- * @param uart_num UART peripheral number
- */
-void esp_vfs_dev_uart_use_nonblocking(int uart_num);
-
-/**
- * @brief set VFS to use UART driver for reading and writing
- * @note application must configure UART driver before calling these functions
- * With these functions, read and write are blocking and interrupt-driven.
- * @param uart_num UART peripheral number
- */
-void esp_vfs_dev_uart_use_driver(int uart_num);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/vfs/sys/dirent.h b/tools/sdk/include/vfs/sys/dirent.h
deleted file mode 100644
index 57b5be5eea3..00000000000
--- a/tools/sdk/include/vfs/sys/dirent.h
+++ /dev/null
@@ -1,55 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <stddef.h>
-#include <stdint.h>
-
-/**
- * This header file provides POSIX-compatible definitions of directory
- * access functions and related data types.
- * See http://pubs.opengroup.org/onlinepubs/7908799/xsh/dirent.h.html
- * for reference.
- */
-
-/**
- * @brief Opaque directory structure
- */
-typedef struct {
-    uint16_t dd_vfs_idx; /*!< VFS index, not to be used by applications */
-    uint16_t dd_rsv;     /*!< field reserved for future extension */
-    /* remaining fields are defined by VFS implementation */
-} DIR;
-
-/**
- * @brief Directory entry structure
- */
-struct dirent {
-    int d_ino;          /*!< file number */
-    uint8_t d_type;     /*!< not defined in POSIX, but present in BSD and Linux */
-#define DT_UNKNOWN  0
-#define DT_REG      1
-#define DT_DIR      2
-    char d_name[256];   /*!< zero-terminated file name */
-};
-
-DIR* opendir(const char* name);
-struct dirent* readdir(DIR* pdir);
-long telldir(DIR* pdir);
-void seekdir(DIR* pdir, long loc);
-void rewinddir(DIR* pdir);
-int closedir(DIR* pdir);
-int readdir_r(DIR* pdir, struct dirent* entry, struct dirent** out_dirent);
-
diff --git a/tools/sdk/include/vfs/sys/ioctl.h b/tools/sdk/include/vfs/sys/ioctl.h
deleted file mode 100644
index 90cbb47d663..00000000000
--- a/tools/sdk/include/vfs/sys/ioctl.h
+++ /dev/null
@@ -1,25 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int ioctl(int fd, int request, ...);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/wear_levelling/wear_levelling.h b/tools/sdk/include/wear_levelling/wear_levelling.h
deleted file mode 100644
index 137b13f1d19..00000000000
--- a/tools/sdk/include/wear_levelling/wear_levelling.h
+++ /dev/null
@@ -1,136 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _wear_levelling_H_
-#define _wear_levelling_H_
-
-#include "esp_log.h"
-#include "esp_partition.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-* @brief wear levelling handle
-*/
-typedef int32_t wl_handle_t;
-
-#define WL_INVALID_HANDLE -1
-
-/**
-* @brief Mount WL for defined partition
-*
-* @param partition that will be used for access
-* @param out_handle handle of the WL instance
-*
-* @return
-*       - ESP_OK, if the allocation was successfully;
-*       - ESP_ERR_INVALID_ARG, if WL allocation was unsuccessful;
-*       - ESP_ERR_NO_MEM, if there was no memory to allocate WL components;
-*/
-esp_err_t wl_mount(const esp_partition_t *partition, wl_handle_t *out_handle);
-
-/**
-* @brief Unmount WL for defined partition
-*
-* @param handle WL partition handle
-*
-* @return
-*       - ESP_OK, if the operation completed successfully;
-*       - or one of error codes from lower-level flash driver.
-*/
-esp_err_t wl_unmount(wl_handle_t handle);
-
-/**
-* @brief Erase part of the WL storage
-*
-* @param handle WL handle that are related to the partition
-* @param start_addr Address where erase operation should start. Must be aligned
-*                   to the result of function wl_sector_size(...).
-* @param size Size of the range which should be erased, in bytes.
-*                   Must be divisible by result of function wl_sector_size(...)..
-*
-* @return
-*       - ESP_OK, if the range was erased successfully;
-*       - ESP_ERR_INVALID_ARG, if iterator or dst are NULL;
-*       - ESP_ERR_INVALID_SIZE, if erase would go out of bounds of the partition;
-*       - or one of error codes from lower-level flash driver.
-*/
-esp_err_t wl_erase_range(wl_handle_t handle, size_t start_addr, size_t size);
-
-/**
-* @brief Write data to the WL storage
-*
-* Before writing data to flash, corresponding region of flash needs to be erased.
-* This can be done using wl_erase_range function.
-*
-* @param handle WL handle that are related to the partition
-* @param dest_addr Address where the data should be written, relative to the
-*                   beginning of the partition.
-* @param src Pointer to the source buffer.  Pointer must be non-NULL and
-*            buffer must be at least 'size' bytes long.
-* @param size Size of data to be written, in bytes.
-*
-* @note Prior to writing to WL storage, make sure it has been erased with
-*       wl_erase_range call.
-*
-* @return
-*       - ESP_OK, if data was written successfully;
-*       - ESP_ERR_INVALID_ARG, if dst_offset exceeds partition size;
-*       - ESP_ERR_INVALID_SIZE, if write would go out of bounds of the partition;
-*       - or one of error codes from lower-level flash driver.
-*/
-esp_err_t wl_write(wl_handle_t handle, size_t dest_addr, const void *src, size_t size);
-
-/**
-* @brief Read data from the WL storage
-*
-* @param handle WL module instance that was initialized before
-* @param dest Pointer to the buffer where data should be stored.
-*            Pointer must be non-NULL and buffer must be at least 'size' bytes long.
-* @param src_addr Address of the data to be read, relative to the
-*                   beginning of the partition.
-* @param size Size of data to be read, in bytes.
-*
-* @return
-*       - ESP_OK, if data was read successfully;
-*       - ESP_ERR_INVALID_ARG, if src_offset exceeds partition size;
-*       - ESP_ERR_INVALID_SIZE, if read would go out of bounds of the partition;
-*       - or one of error codes from lower-level flash driver.
-*/
-esp_err_t wl_read(wl_handle_t handle, size_t src_addr, void *dest, size_t size);
-
-/**
-* @brief Get size of the WL storage
-*
-* @param handle WL module handle that was initialized before
-* @return usable size, in bytes
-*/
-size_t wl_size(wl_handle_t handle);
-
-/**
-* @brief Get sector size of the WL instance
-*
-* @param handle WL module handle that was initialized before
-* @return sector size, in bytes
-*/
-size_t wl_sector_size(wl_handle_t handle);
-
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif // _wear_levelling_H_
diff --git a/tools/sdk/include/wifi_provisioning/wifi_provisioning/manager.h b/tools/sdk/include/wifi_provisioning/wifi_provisioning/manager.h
deleted file mode 100644
index 6b535604d4c..00000000000
--- a/tools/sdk/include/wifi_provisioning/wifi_provisioning/manager.h
+++ /dev/null
@@ -1,553 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <esp_event_loop.h>
-#include <protocomm.h>
-
-#include "wifi_provisioning/wifi_config.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   Events generated by manager
- *
- * These events are generated in order of declaration and, for the
- * stretch of time between initialization and de-initialization of
- * the manager, each event is signaled only once
- */
-typedef enum {
-    /**
-     * Emitted when the manager is initialized
-     */
-    WIFI_PROV_INIT,
-
-    /**
-     * Indicates that provisioning has started
-     */
-    WIFI_PROV_START,
-
-    /**
-     * Emitted when Wi-Fi AP credentials are received via `protocomm`
-     * endpoint `wifi_config`. The event data in this case is a pointer
-     * to the corresponding `wifi_sta_config_t` structure
-     */
-    WIFI_PROV_CRED_RECV,
-
-    /**
-     * Emitted when device fails to connect to the AP of which the
-     * credentials were received earlier on event `WIFI_PROV_CRED_RECV`.
-     * The event data in this case is a pointer to the disconnection
-     * reason code with type `wifi_prov_sta_fail_reason_t`
-     */
-    WIFI_PROV_CRED_FAIL,
-
-    /**
-     * Emitted when device successfully connects to the AP of which the
-     * credentials were received earlier on event `WIFI_PROV_CRED_RECV`
-     */
-    WIFI_PROV_CRED_SUCCESS,
-
-    /**
-     * Signals that provisioning service has stopped
-     */
-    WIFI_PROV_END,
-
-    /**
-     * Signals that manager has been de-initialized
-     */
-    WIFI_PROV_DEINIT,
-} wifi_prov_cb_event_t;
-
-typedef void (*wifi_prov_cb_func_t)(void *user_data, wifi_prov_cb_event_t event, void *event_data);
-
-/**
- * @brief   Event handler that is used by the manager while
- *          provisioning service is active
- */
-typedef struct {
-    /**
-     * Callback function to be executed on provisioning events
-     */
-    wifi_prov_cb_func_t event_cb;
-
-    /**
-     * User context data to pass as parameter to callback function
-     */
-    void *user_data;
-} wifi_prov_event_handler_t;
-
-/**
- * @brief Event handler can be set to none if not used
- */
-#define WIFI_PROV_EVENT_HANDLER_NONE { \
-    .event_cb  = NULL,                 \
-    .user_data = NULL                  \
-}
-
-/**
- * @brief   Structure for specifying the provisioning scheme to be
- *          followed by the manager
- *
- * @note    Ready to use schemes are available:
- *              - wifi_prov_scheme_ble     : for provisioning over BLE transport + GATT server
- *              - wifi_prov_scheme_softap  : for provisioning over SoftAP transport + HTTP server
- *              - wifi_prov_scheme_console : for provisioning over Serial UART transport + Console (for debugging)
- */
-typedef struct wifi_prov_scheme {
-    /**
-     * Function which is to be called by the manager when it is to
-     * start the provisioning service associated with a protocomm instance
-     * and a scheme specific configuration
-     */
-    esp_err_t (*prov_start) (protocomm_t *pc, void *config);
-
-    /**
-     * Function which is to be called by the manager to stop the
-     * provisioning service previously associated with a protocomm instance
-     */
-    esp_err_t (*prov_stop) (protocomm_t *pc);
-
-    /**
-     * Function which is to be called by the manager to generate
-     * a new configuration for the provisioning service, that is
-     * to be passed to prov_start()
-     */
-    void *(*new_config) (void);
-
-    /**
-     * Function which is to be called by the manager to delete a
-     * configuration generated using new_config()
-     */
-    void (*delete_config) (void *config);
-
-    /**
-     * Function which is to be called by the manager to set the
-     * service name and key values in the configuration structure
-     */
-    esp_err_t (*set_config_service) (void *config, const char *service_name, const char *service_key);
-
-    /**
-     * Function which is to be called by the manager to set a protocomm endpoint
-     * with an identifying name and UUID in the configuration structure
-     */
-    esp_err_t (*set_config_endpoint) (void *config, const char *endpoint_name, uint16_t uuid);
-
-    /**
-     * Sets mode of operation of Wi-Fi during provisioning
-     * This is set to :
-     * - WIFI_MODE_APSTA for SoftAP transport
-     * - WIFI_MODE_STA for BLE transport
-     */
-    wifi_mode_t wifi_mode;
-} wifi_prov_scheme_t;
-
-/**
- * @brief   Structure for specifying the manager configuration
- */
-typedef struct {
-    /**
-     * Provisioning scheme to use. Following schemes are already available:
-     *     - wifi_prov_scheme_ble     : for provisioning over BLE transport + GATT server
-     *     - wifi_prov_scheme_softap  : for provisioning over SoftAP transport + HTTP server + mDNS (optional)
-     *     - wifi_prov_scheme_console : for provisioning over Serial UART transport + Console (for debugging)
-     */
-    wifi_prov_scheme_t scheme;
-
-    /**
-     * Event handler required by the scheme for incorporating scheme specific
-     * behavior while provisioning manager is running. Various options may be
-     * provided by the scheme for setting this field. Use WIFI_PROV_EVENT_HANDLER_NONE
-     * when not used. When using scheme wifi_prov_scheme_ble, the following
-     * options are available:
-     *     - WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BTDM
-     *     - WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BLE
-     *     - WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BT
-     */
-    wifi_prov_event_handler_t scheme_event_handler;
-
-    /**
-     * Event handler that can be set for the purpose of incorporating application
-     * specific behavior. Use WIFI_PROV_EVENT_HANDLER_NONE when not used.
-     */
-    wifi_prov_event_handler_t app_event_handler;
-} wifi_prov_mgr_config_t;
-
-/**
- * @brief   Security modes supported by the Provisioning Manager.
- *
- * These are same as the security modes provided by protocomm
- */
-typedef enum wifi_prov_security {
-    /**
-     * No security (plain-text communication)
-     */
-    WIFI_PROV_SECURITY_0 = 0,
-
-    /**
-     * This secure communication mode consists of
-     *   X25519 key exchange
-     * + proof of possession (pop) based authentication
-     * + AES-CTR encryption
-     */
-    WIFI_PROV_SECURITY_1
-} wifi_prov_security_t;
-
-/**
- * @brief   Initialize provisioning manager instance
- *
- * Configures the manager and allocates internal resources
- *
- * Configuration specifies the provisioning scheme (transport)
- * and event handlers
- *
- * Event WIFI_PROV_INIT is emitted right after initialization
- * is complete
- *
- * @param[in] config Configuration structure
- *
- * @return
- *  - ESP_OK      : Success
- *  - ESP_FAIL    : Fail
- */
-esp_err_t wifi_prov_mgr_init(wifi_prov_mgr_config_t config);
-
-/**
- * @brief   Stop provisioning (if running) and release
- *          resource used by the manager
- *
- * Event WIFI_PROV_DEINIT is emitted right after de-initialization
- * is finished
- *
- * If provisioning service is  still active when this API is called,
- * it first stops the service, hence emitting WIFI_PROV_END, and
- * then performs the de-initialization
- */
-void wifi_prov_mgr_deinit(void);
-
-/**
- * @brief   Checks if device is provisioned
- *
- * This checks if Wi-Fi credentials are present on the NVS
- *
- * The Wi-Fi credentials are assumed to be kept in the same
- * NVS namespace as used by esp_wifi component
- *
- * If one were to call esp_wifi_set_config() directly instead
- * of going through the provisioning process, this function will
- * still yield true (i.e. device will be found to be provisioned)
- *
- * @note    Calling wifi_prov_mgr_start_provisioning() automatically
- *          resets the provision state, irrespective of what the
- *          state was prior to making the call.
- *
- * @param[out] provisioned  True if provisioned, else false
- *
- * @return
- *  - ESP_OK      : Retrieved provision state successfully
- *  - ESP_FAIL    : Wi-Fi not initialized
- *  - ESP_ERR_INVALID_ARG   : Null argument supplied
- *  - ESP_ERR_INVALID_STATE : Manager not initialized
- */
-esp_err_t wifi_prov_mgr_is_provisioned(bool *provisioned);
-
-/**
- * @brief   Start provisioning service
- *
- * This starts the provisioning service according to the scheme
- * configured at the time of initialization. For scheme :
- * - wifi_prov_scheme_ble : This starts protocomm_ble, which internally initializes
- *                          BLE transport and starts GATT server for handling
- *                          provisioning requests
- * - wifi_prov_scheme_softap : This activates SoftAP mode of Wi-Fi and starts
- *                          protocomm_httpd, which internally starts an HTTP
- *                          server for handling provisioning requests (If mDNS is
- *                          active it also starts advertising service with type
- *                          _esp_wifi_prov._tcp)
- *
- * Event WIFI_PROV_START is emitted right after provisioning starts without failure
- *
- * @note   This API will start provisioning service even if device is found to be
- *         already provisioned, i.e. wifi_prov_mgr_is_provisioned() yields true
- *
- * @param[in] security      Specify which protocomm security scheme to use :
- *                              - WIFI_PROV_SECURITY_0 : For no security
- *                              - WIFI_PROV_SECURITY_1 : x25519 secure handshake for session
- *                                establishment followed by AES-CTR encryption of provisioning messages
- * @param[in] pop           Pointer to proof of possession string (NULL if not needed). This
- *                          is relevant only for protocomm security 1, in which case it is used
- *                          for authenticating secure session
- * @param[in] service_name  Unique name of the service. This translates to:
- *                              - Wi-Fi SSID when provisioning mode is softAP
- *                              - Device name when provisioning mode is BLE
- * @param[in] service_key   Key required by client to access the service (NULL if not needed).
- *                          This translates to:
- *                              - Wi-Fi password when provisioning mode is softAP
- *                              - ignored when provisioning mode is BLE
- *
- * @return
- *  - ESP_OK      : Provisioning started successfully
- *  - ESP_FAIL    : Failed to start provisioning service
- *  - ESP_ERR_INVALID_STATE : Provisioning manager not initialized or already started
- */
-esp_err_t wifi_prov_mgr_start_provisioning(wifi_prov_security_t security, const char *pop,
-                                           const char *service_name, const char *service_key);
-
-/**
- * @brief   Stop provisioning service
- *
- * If provisioning service is active, this API will initiate a process to stop
- * the service and return. Once the service actually stops, the event WIFI_PROV_END
- * will be emitted.
- *
- * If wifi_prov_mgr_deinit() is called without calling this API first, it will
- * automatically stop the provisioning service and emit the WIFI_PROV_END, followed
- * by WIFI_PROV_DEINIT, before returning.
- *
- * This API will generally be used along with wifi_prov_mgr_disable_auto_stop()
- * in the scenario when the main application has registered its own endpoints,
- * and wishes that the provisioning service is stopped only when some protocomm
- * command from the client side application is received.
- *
- * Calling this API inside an endpoint handler, with sufficient cleanup_delay,
- * will allow the response / acknowledgment to be sent successfully before the
- * underlying protocomm service is stopped.
- *
- * Cleaup_delay is set when calling wifi_prov_mgr_disable_auto_stop().
- * If not specified, it defaults to 1000ms.
- *
- * For straightforward cases, using this API is usually not necessary as
- * provisioning is stopped automatically once WIFI_PROV_CRED_SUCCESS is emitted.
- * Stopping is delayed (maximum 30 seconds) thus allowing the client side
- * application to query for Wi-Fi state, i.e. after receiving the first query
- * and sending `Wi-Fi state connected` response the service is stopped immediately.
- */
-void wifi_prov_mgr_stop_provisioning(void);
-
-/**
- * @brief   Wait for provisioning service to finish
- *
- * Calling this API will block until provisioning service is stopped
- * i.e. till event WIFI_PROV_END is emitted.
- *
- * This will not block if provisioning is not started or not initialized.
- */
-void wifi_prov_mgr_wait(void);
-
-/**
- * @brief   Disable auto stopping of provisioning service upon completion
- *
- * By default, once provisioning is complete, the provisioning service is automatically
- * stopped, and all endpoints (along with those registered by main application) are
- * deactivated.
- *
- * This API is useful in the case when main application wishes to close provisioning service
- * only after it receives some protocomm command from the client side app. For example, after
- * connecting to Wi-Fi, the device may want to connect to the cloud, and only once that is
- * successfully, the device is said to be fully configured. But, then it is upto the main
- * application to explicitly call wifi_prov_mgr_stop_provisioning() later when the device is
- * fully configured and the provisioning service is no longer required.
- *
- * @note    This must be called before executing wifi_prov_mgr_start_provisioning()
- *
- * @param[in] cleanup_delay Sets the delay after which the actual cleanup of transport related
- *                          resources is done after a call to wifi_prov_mgr_stop_provisioning()
- *                          returns. Minimum allowed value is 100ms. If not specified, this will
- *                          default to 1000ms.
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_ERR_INVALID_STATE : Manager not initialized or
- *                            provisioning service already started
- */
-esp_err_t wifi_prov_mgr_disable_auto_stop(uint32_t cleanup_delay);
-
-/**
- * @brief   Set application version and capabilities in the JSON data returned by
- *          proto-ver endpoint
- *
- * This function can be called multiple times, to specify information about the various
- * application specific services running on the device, identified by unique labels.
- *
- * The provisioning service itself registers an entry in the JSON data, by the label "prov",
- * containing only provisioning service version and capabilities. Application services should
- * use a label other than "prov" so as not to overwrite this.
- *
- * @note    This must be called before executing wifi_prov_mgr_start_provisioning()
- *
- * @param[in] label   String indicating the application name.
- *
- * @param[in] version String indicating the application version.
- *                    There is no constraint on format.
- *
- * @param[in] capabilities  Array of strings with capabilities.
- *                          These could be used by the client side app to know
- *                          the application registered endpoint capabilities
- *
- * @param[in] total_capabilities  Size of capabilities array
- *
- * @return
- *  - ESP_OK : Success
- *  - ESP_ERR_INVALID_STATE : Manager not initialized or
- *                            provisioning service already started
- *  - ESP_ERR_NO_MEM : Failed to allocate memory for version string
- *  - ESP_ERR_INVALID_ARG : Null argument
- */
-esp_err_t wifi_prov_mgr_set_app_info(const char *label, const char *version,
-                                     const char**capabilities, size_t total_capabilities);
-
-/**
- * @brief   Create an additional endpoint and allocate internal resources for it
- *
- * This API is to be called by the application if it wants to create an additional
- * endpoint. All additional endpoints will be assigned UUIDs starting from 0xFF54
- * and so on in the order of execution.
- *
- * protocomm handler for the created endpoint is to be registered later using
- * wifi_prov_mgr_endpoint_register() after provisioning has started.
- *
- * @note    This API can only be called BEFORE provisioning is started
- *
- * @note    Additional endpoints can be used for configuring client provided
- *          parameters other than Wi-Fi credentials, that are necessary for the
- *          main application and hence must be set prior to starting the application
- *
- * @note    After session establishment, the additional endpoints must be targeted
- *          first by the client side application before sending Wi-Fi configuration,
- *          because once Wi-Fi configuration finishes the provisioning service is
- *          stopped and hence all endpoints are unregistered
- *
- * @param[in] ep_name  unique name of the endpoint
- *
- * @return
- *  - ESP_OK      : Success
- *  - ESP_FAIL    : Failure
- */
-esp_err_t wifi_prov_mgr_endpoint_create(const char *ep_name);
-
-/**
- * @brief   Register a handler for the previously created endpoint
- *
- * This API can be called by the application to register a protocomm handler
- * to any endpoint that was created using wifi_prov_mgr_endpoint_create().
- *
- * @note    This API can only be called AFTER provisioning has started
- *
- * @note    Additional endpoints can be used for configuring client provided
- *          parameters other than Wi-Fi credentials, that are necessary for the
- *          main application and hence must be set prior to starting the application
- *
- * @note    After session establishment, the additional endpoints must be targeted
- *          first by the client side application before sending Wi-Fi configuration,
- *          because once Wi-Fi configuration finishes the provisioning service is
- *          stopped and hence all endpoints are unregistered
- *
- * @param[in] ep_name   Name of the endpoint
- * @param[in] handler   Endpoint handler function
- * @param[in] user_ctx  User data
- *
- * @return
- *  - ESP_OK      : Success
- *  - ESP_FAIL    : Failure
- */
-esp_err_t wifi_prov_mgr_endpoint_register(const char *ep_name,
-                                          protocomm_req_handler_t handler,
-                                          void *user_ctx);
-
-/**
- * @brief   Unregister the handler for an endpoint
- *
- * This API can be called if the application wants to selectively
- * unregister the handler of an endpoint while the provisioning
- * is still in progress.
- *
- * All the endpoint handlers are unregistered automatically when
- * the provisioning stops.
- *
- * @param[in] ep_name  Name of the endpoint
- */
-void wifi_prov_mgr_endpoint_unregister(const char *ep_name);
-
-/**
- * @brief   Event handler for provisioning manager
- *
- * This is called from the main event handler and controls the
- * provisioning manager's internal state machine depending on
- * incoming Wi-Fi events
- *
- * @param[in] ctx   Event context data
- * @param[in] event Event info
- *
- * @return
- *  - ESP_OK       : Event handled successfully
- *  - ESP_ERR_FAIL : This event cannot be handled
- */
-esp_err_t wifi_prov_mgr_event_handler(void *ctx, system_event_t *event);
-
-/**
- * @brief   Get state of Wi-Fi Station during provisioning
- *
- * @param[out] state    Pointer to wifi_prov_sta_state_t
- *                      variable to be filled
- *
- * @return
- *  - ESP_OK    : Successfully retrieved Wi-Fi state
- *  - ESP_FAIL  : Provisioning app not running
- */
-esp_err_t wifi_prov_mgr_get_wifi_state(wifi_prov_sta_state_t *state);
-
-/**
- * @brief   Get reason code in case of Wi-Fi station
- *          disconnection during provisioning
- *
-* @param[out] reason    Pointer to wifi_prov_sta_fail_reason_t
-*                       variable to be filled
- *
- * @return
- *  - ESP_OK    : Successfully retrieved Wi-Fi disconnect reason
- *  - ESP_FAIL  : Provisioning app not running
- */
-esp_err_t wifi_prov_mgr_get_wifi_disconnect_reason(wifi_prov_sta_fail_reason_t *reason);
-
-/**
- * @brief   Runs Wi-Fi as Station with the supplied configuration
- *
- * Configures the Wi-Fi station mode to connect to the AP with
- * SSID and password specified in config structure and sets
- * Wi-Fi to run as station.
- *
- * This is automatically called by provisioning service upon
- * receiving new credentials.
- *
- * If credentials are to be supplied to the manager via a
- * different mode other than through protocomm, then this
- * API needs to be called.
- *
- * Event WIFI_PROV_CRED_RECV is emitted after credentials have
- * been applied and Wi-Fi station started
- *
- * @param[in] wifi_cfg  Pointer to Wi-Fi configuration structure
- *
- * @return
- *  - ESP_OK      : Wi-Fi configured and started successfully
- *  - ESP_FAIL    : Failed to set configuration
- */
-esp_err_t wifi_prov_mgr_configure_sta(wifi_config_t *wifi_cfg);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/wifi_provisioning/wifi_provisioning/scheme_ble.h b/tools/sdk/include/wifi_provisioning/wifi_provisioning/scheme_ble.h
deleted file mode 100644
index ed30d818155..00000000000
--- a/tools/sdk/include/wifi_provisioning/wifi_provisioning/scheme_ble.h
+++ /dev/null
@@ -1,82 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <protocomm.h>
-#include <protocomm_ble.h>
-
-#include "wifi_provisioning/manager.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   Scheme that can be used by manager for provisioning
- *          over BLE transport with GATT server
- */
-extern const wifi_prov_scheme_t wifi_prov_scheme_ble;
-
-/* This scheme specific event handler is to be used when application
- * doesn't require BT and BLE after provisioning has finished */
-#define WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BTDM {    \
-    .event_cb  = wifi_prov_scheme_ble_event_cb_free_btdm, \
-    .user_data = NULL                                     \
-}
-
-/* This scheme specific event handler is to be used when application
- * doesn't require BLE to be active after provisioning has finished */
-#define WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BLE {    \
-    .event_cb  = wifi_prov_scheme_ble_event_cb_free_ble, \
-    .user_data = NULL                                    \
-}
-
-/* This scheme specific event handler is to be used when application
- * doesn't require BT to be active after provisioning has finished */
-#define WIFI_PROV_SCHEME_BLE_EVENT_HANDLER_FREE_BT {    \
-    .event_cb  = wifi_prov_scheme_ble_event_cb_free_bt, \
-    .user_data = NULL                                   \
-}
-
-void wifi_prov_scheme_ble_event_cb_free_btdm(void *user_data, wifi_prov_cb_event_t event, void *event_data);
-void wifi_prov_scheme_ble_event_cb_free_ble (void *user_data, wifi_prov_cb_event_t event, void *event_data);
-void wifi_prov_scheme_ble_event_cb_free_bt  (void *user_data, wifi_prov_cb_event_t event, void *event_data);
-
-/**
- * @brief   Set the 128 bit GATT service UUID used for provisioning
- *
- * This API is used to override the default 128 bit provisioning
- * service UUID, which is 0000ffff-0000-1000-8000-00805f9b34fb.
- *
- * This must be called before starting provisioning, i.e. before
- * making a call to wifi_prov_mgr_start_provisioning(), otherwise
- * the default UUID will be used.
- *
- * @note    The data being pointed to by the argument must be valid
- *          atleast till provisioning is started. Upon start, the
- *          manager will store an internal copy of this UUID, and
- *          this data can be freed or invalidated afterwords.
- *
- * @param[in] uuid128  A custom 128 bit UUID
- *
- * @return
- *  - ESP_OK              : Success
- *  - ESP_ERR_INVALID_ARG : Null argument
- */
-esp_err_t wifi_prov_scheme_ble_set_service_uuid(uint8_t *uuid128);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/wifi_provisioning/wifi_provisioning/scheme_console.h b/tools/sdk/include/wifi_provisioning/wifi_provisioning/scheme_console.h
deleted file mode 100644
index 760fe3243a5..00000000000
--- a/tools/sdk/include/wifi_provisioning/wifi_provisioning/scheme_console.h
+++ /dev/null
@@ -1,34 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <protocomm.h>
-#include <protocomm_console.h>
-
-#include "wifi_provisioning/manager.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   Scheme that can be used by manager for provisioning
- *          over console (Serial UART)
- */
-extern const wifi_prov_scheme_t wifi_prov_scheme_console;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/wifi_provisioning/wifi_provisioning/scheme_softap.h b/tools/sdk/include/wifi_provisioning/wifi_provisioning/scheme_softap.h
deleted file mode 100644
index eda48be0f7e..00000000000
--- a/tools/sdk/include/wifi_provisioning/wifi_provisioning/scheme_softap.h
+++ /dev/null
@@ -1,47 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include <protocomm.h>
-#include <protocomm_httpd.h>
-
-#include "wifi_provisioning/manager.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   Scheme that can be used by manager for provisioning
- *          over SoftAP transport with HTTP server
- */
-extern const wifi_prov_scheme_t wifi_prov_scheme_softap;
-
-/**
- *
- * @brief Provide HTTPD Server handle externally.
- *
- * Useful in cases wherein applications need the webserver for some
- * different operations, and do not want the wifi provisioning component
- * to start/stop a new instance.
- *
- * @note This API should be called before wifi_prov_mgr_start_provisioning()
- *
- * @param[in] handle Handle to HTTPD server instance
- */
-void wifi_prov_scheme_softap_set_httpd_handle(void *handle);
-#ifdef __cplusplus
-}
-#endif
diff --git a/tools/sdk/include/wifi_provisioning/wifi_provisioning/wifi_config.h b/tools/sdk/include/wifi_provisioning/wifi_provisioning/wifi_config.h
deleted file mode 100644
index 2fa64448d49..00000000000
--- a/tools/sdk/include/wifi_provisioning/wifi_provisioning/wifi_config.h
+++ /dev/null
@@ -1,144 +0,0 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _WIFI_PROV_CONFIG_H_
-#define _WIFI_PROV_CONFIG_H_
-
-#include <lwip/inet.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   WiFi STA status for conveying back to the provisioning master
- */
-typedef enum {
-    WIFI_PROV_STA_CONNECTING,
-    WIFI_PROV_STA_CONNECTED,
-    WIFI_PROV_STA_DISCONNECTED
-} wifi_prov_sta_state_t;
-
-/**
- * @brief   WiFi STA connection fail reason
- */
-typedef enum {
-    WIFI_PROV_STA_AUTH_ERROR,
-    WIFI_PROV_STA_AP_NOT_FOUND
-} wifi_prov_sta_fail_reason_t;
-
-/**
- * @brief   WiFi STA connected status information
- */
-typedef struct {
-    /**
-     * IP Address received by station
-     */
-    char    ip_addr[IP4ADDR_STRLEN_MAX];
-
-    char    bssid[6];   /*!< BSSID of the AP to which connection was estalished */
-    char    ssid[33];   /*!< SSID of the to which connection was estalished */
-    uint8_t channel;    /*!< Channel of the AP */
-    uint8_t auth_mode;  /*!< Authorization mode of the AP */
-} wifi_prov_sta_conn_info_t;
-
-/**
- * @brief   WiFi status data to be sent in response to `get_status` request from master
- */
-typedef struct {
-    wifi_prov_sta_state_t wifi_state;    /*!< WiFi state of the station */
-    union {
-        /**
-         * Reason for disconnection (valid only when `wifi_state` is `WIFI_STATION_DISCONNECTED`)
-         */
-        wifi_prov_sta_fail_reason_t fail_reason;
-
-        /**
-         * Connection information (valid only when `wifi_state` is `WIFI_STATION_CONNECTED`)
-         */
-        wifi_prov_sta_conn_info_t   conn_info;
-    };
-} wifi_prov_config_get_data_t;
-
-/**
- * @brief   WiFi config data received by slave during `set_config` request from master
- */
-typedef struct {
-    char    ssid[33];       /*!< SSID of the AP to which the slave is to be connected */
-    char    password[64];   /*!< Password of the AP */
-    char    bssid[6];       /*!< BSSID of the AP */
-    uint8_t channel;        /*!< Channel of the AP */
-} wifi_prov_config_set_data_t;
-
-/**
- * @brief   Type of context data passed to each get/set/apply handler
- *           function set in `wifi_prov_config_handlers` structure.
- *
- * This is passed as an opaque pointer, thereby allowing it be defined
- * later in application code as per requirements.
- */
-typedef struct wifi_prov_ctx wifi_prov_ctx_t;
-
-/**
- * @brief   Internal handlers for receiving and responding to protocomm
- *          requests from master
- *
- * This is to be passed as priv_data for protocomm request handler
- * (refer to `wifi_prov_config_data_handler()`) when calling `protocomm_add_endpoint()`.
- */
-typedef struct wifi_prov_config_handlers {
-    /**
-     * Handler function called when connection status
-     * of the slave (in WiFi station mode) is requested
-     */
-    esp_err_t (*get_status_handler)(wifi_prov_config_get_data_t *resp_data,
-                                    wifi_prov_ctx_t **ctx);
-
-    /**
-     * Handler function called when WiFi connection configuration
-     * (eg. AP SSID, password, etc.) of the slave (in WiFi station mode)
-     * is to be set to user provided values
-     */
-    esp_err_t (*set_config_handler)(const wifi_prov_config_set_data_t *req_data,
-                                    wifi_prov_ctx_t **ctx);
-
-    /**
-     * Handler function for applying the configuration that was set in
-     * `set_config_handler`. After applying the station may get connected to
-     * the AP or may fail to connect. The slave must be ready to convey the
-     * updated connection status information when `get_status_handler` is
-     * invoked again by the master.
-     */
-    esp_err_t (*apply_config_handler)(wifi_prov_ctx_t **ctx);
-
-    /**
-     * Context pointer to be passed to above handler functions upon invocation
-     */
-    wifi_prov_ctx_t *ctx;
-} wifi_prov_config_handlers_t;
-
-/**
- * @brief   Handler for receiving and responding to requests from master
- *
- * This is to be registered as the `wifi_config` endpoint handler
- * (protocomm `protocomm_req_handler_t`) using `protocomm_add_endpoint()`
- */
-esp_err_t wifi_prov_config_data_handler(uint32_t session_id, const uint8_t *inbuf, ssize_t inlen,
-                                        uint8_t **outbuf, ssize_t *outlen, void *priv_data);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/wifi_provisioning/wifi_provisioning/wifi_scan.h b/tools/sdk/include/wifi_provisioning/wifi_provisioning/wifi_scan.h
deleted file mode 100644
index a4ebb7e5700..00000000000
--- a/tools/sdk/include/wifi_provisioning/wifi_provisioning/wifi_scan.h
+++ /dev/null
@@ -1,166 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#ifndef _PROV_WIFI_SCAN_H_
-#define _PROV_WIFI_SCAN_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <esp_wifi.h>
-
-#define WIFI_SSID_LEN  sizeof(((wifi_ap_record_t *)0)->ssid)
-#define WIFI_BSSID_LEN sizeof(((wifi_ap_record_t *)0)->bssid)
-
-/**
- * @brief   Type of context data passed to each get/set/apply handler
- *           function set in `wifi_prov_scan_handlers` structure.
- *
- * This is passed as an opaque pointer, thereby allowing it be defined
- * later in application code as per requirements.
- */
-typedef struct wifi_prov_scan_ctx wifi_prov_scan_ctx_t;
-
-/**
- * @brief   Structure of entries in the scan results list
- */
-typedef struct {
-    /**
-     * SSID of Wi-Fi AP
-     */
-    char ssid[WIFI_SSID_LEN];
-
-    /**
-     * BSSID of Wi-Fi AP
-     */
-    char bssid[WIFI_BSSID_LEN];
-
-    /**
-     * Wi-Fi channel number
-     */
-    uint8_t channel;
-
-    /**
-     * Signal strength
-     */
-    int rssi;
-
-    /**
-     * Wi-Fi security mode
-     */
-    uint8_t auth;
-} wifi_prov_scan_result_t;
-
-/**
- * @brief   Internal handlers for receiving and responding to protocomm
- *          requests from client
- *
- * This is to be passed as priv_data for protocomm request handler
- * (refer to `wifi_prov_scan_handler()`) when calling `protocomm_add_endpoint()`.
- */
-typedef struct wifi_prov_scan_handlers {
-    /**
-     * Handler function called when scan start command is received
-     * with various scan parameters :
-     *
-     * blocking (input) - If true, the function should return only
-     * when the scanning is finished
-     *
-     * passive (input) - If true, scan is to be started in passive
-     * mode (this may be slower) instead of active mode
-     *
-     * group_channels (input) - This specifies whether to scan
-     * all channels in one go (when zero) or perform scanning of
-     * channels in groups, with 120ms delay between scanning of
-     * consecutive groups, and the value of this parameter sets the
-     * number of channels in each group. This is useful when transport
-     * mode is SoftAP, where scanning all channels in one go may not
-     * give the Wi-Fi driver enough time to send out beacons, and
-     * hence may cause disconnection with any connected stations.
-     * When scanning in groups, the manager will wait for atleast
-     * 120ms after completing scan on a group of channels, and thus
-     * allow the driver to send out the beacons. For example, given
-     * that the total number of Wi-Fi channels is 14, then setting
-     * group_channels to 4, will create 5 groups, with each group
-     * having 3 channels, except the last one which will have
-     * 14 % 3 = 2 channels. So, when scan is started, the first 3
-     * channels will be scanned, followed by a 120ms delay, and then
-     * the next 3 channels, and so on, until all the 14 channels have
-     * been scanned. One may need to adjust this parameter as having
-     * only few channels in a group may slow down the overall scan
-     * time, while having too many may again cause disconnection.
-     * Usually a value of 4 should work for most cases. Note that
-     * for any other mode of transport, e.g. BLE, this can be safely
-     * set to 0, and hence achieve the fastest overall scanning time.
-     *
-     * period_ms (input) - Scan parameter specifying how long to
-     * wait on each channel (in milli-seconds)
-     */
-    esp_err_t (*scan_start)(bool blocking, bool passive,
-                            uint8_t group_channels, uint32_t period_ms,
-                            wifi_prov_scan_ctx_t **ctx);
-
-    /**
-     * Handler function called when scan status is requested. Status
-     * is given the parameters :
-     *
-     * scan_finished (output) - When scan has finished this returns true
-     *
-     * result_count (output) - This gives the total number of results
-     * obtained till now. If scan is yet happening this number will
-     * keep on updating
-     */
-    esp_err_t (*scan_status)(bool *scan_finished,
-                             uint16_t *result_count,
-                             wifi_prov_scan_ctx_t **ctx);
-
-    /**
-     * Handler function called when scan result is requested. Parameters :
-     *
-     * scan_result - For fetching scan results. This can be called even
-     * if scan is still on going
-     *
-     * start_index (input) - Starting index from where to fetch the
-     * entries from the results list
-     *
-     * count (input) - Number of entries to fetch from the starting index
-     *
-     * entries (output) - List of entries returned. Each entry consists
-     * of ssid, channel and rssi information
-     */
-    esp_err_t (*scan_result)(uint16_t result_index,
-                             wifi_prov_scan_result_t *result,
-                             wifi_prov_scan_ctx_t **ctx);
-
-    /**
-     * Context pointer to be passed to above handler functions upon invocation
-     */
-    wifi_prov_scan_ctx_t *ctx;
-} wifi_prov_scan_handlers_t;
-
-/**
- * @brief   Handler for sending on demand Wi-Fi scan results
- *
- * This is to be registered as the `prov-scan` endpoint handler
- * (protocomm `protocomm_req_handler_t`) using `protocomm_add_endpoint()`
- */
-esp_err_t wifi_prov_scan_handler(uint32_t session_id, const uint8_t *inbuf, ssize_t inlen,
-                                 uint8_t **outbuf, ssize_t *outlen, void *priv_data);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/tools/sdk/include/wpa_supplicant/byteswap.h b/tools/sdk/include/wpa_supplicant/byteswap.h
deleted file mode 100644
index 1a8bb8fd158..00000000000
--- a/tools/sdk/include/wpa_supplicant/byteswap.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2010 Espressif System
- */
-
-#ifndef BYTESWAP_H
-#define BYTESWAP_H
-
-/* Swap bytes in 16 bit value.  */
-#ifdef __GNUC__
-# define __bswap_16(x) \
-    (__extension__							      \
-     ({ unsigned short int __bsx = (x);					      \
-        ((((__bsx) >> 8) & 0xff) | (((__bsx) & 0xff) << 8)); }))
-#else
-static INLINE unsigned short int
-__bswap_16 (unsigned short int __bsx)
-{
-  return ((((__bsx) >> 8) & 0xff) | (((__bsx) & 0xff) << 8));
-}
-#endif
-
-/* Swap bytes in 32 bit value.  */
-#ifdef __GNUC__
-# define __bswap_32(x) \
-    (__extension__							      \
-     ({ unsigned int __bsx = (x);					      \
-        ((((__bsx) & 0xff000000) >> 24) | (((__bsx) & 0x00ff0000) >>  8) |    \
-	 (((__bsx) & 0x0000ff00) <<  8) | (((__bsx) & 0x000000ff) << 24)); }))
-#else
-static INLINE unsigned int
-__bswap_32 (unsigned int __bsx)
-{
-  return ((((__bsx) & 0xff000000) >> 24) | (((__bsx) & 0x00ff0000) >>  8) |
-	  (((__bsx) & 0x0000ff00) <<  8) | (((__bsx) & 0x000000ff) << 24));
-}
-#endif
-
-#if defined __GNUC__ && __GNUC__ >= 2
-/* Swap bytes in 64 bit value.  */
-# define __bswap_constant_64(x) \
-     ((((x) & 0xff00000000000000ull) >> 56)				      \
-      | (((x) & 0x00ff000000000000ull) >> 40)				      \
-      | (((x) & 0x0000ff0000000000ull) >> 24)				      \
-      | (((x) & 0x000000ff00000000ull) >> 8)				      \
-      | (((x) & 0x00000000ff000000ull) << 8)				      \
-      | (((x) & 0x0000000000ff0000ull) << 24)				      \
-      | (((x) & 0x000000000000ff00ull) << 40)				      \
-      | (((x) & 0x00000000000000ffull) << 56))
-
-# define __bswap_64(x) \
-     (__extension__							      \
-      ({ union { __extension__ unsigned long long int __ll;		      \
-		 unsigned int __l[2]; } __w, __r;			      \
-         if (__builtin_constant_p (x))					      \
-	   __r.__ll = __bswap_constant_64 (x);				      \
-	 else								      \
-	   {								      \
-	     __w.__ll = (x);						      \
-	     __r.__l[0] = __bswap_32 (__w.__l[1]);			      \
-	     __r.__l[1] = __bswap_32 (__w.__l[0]);			      \
-	   }								      \
-	 __r.__ll; }))
-#endif
-
-#endif /* BYTESWAP_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/aes.h b/tools/sdk/include/wpa_supplicant/crypto/aes.h
deleted file mode 100644
index ba384a9dae3..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/aes.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * AES functions
- * Copyright (c) 2003-2006, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef AES_H
-#define AES_H
-
-#define AES_BLOCK_SIZE 16
-
-void * aes_encrypt_init(const u8 *key, size_t len);
-void aes_encrypt(void *ctx, const u8 *plain, u8 *crypt);
-void aes_encrypt_deinit(void *ctx);
-void * aes_decrypt_init(const u8 *key, size_t len);
-void aes_decrypt(void *ctx, const u8 *crypt, u8 *plain);
-void aes_decrypt_deinit(void *ctx);
-
-#endif /* AES_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/aes_i.h b/tools/sdk/include/wpa_supplicant/crypto/aes_i.h
deleted file mode 100644
index 1063422a810..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/aes_i.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * AES (Rijndael) cipher
- * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef AES_I_H
-#define AES_I_H
-
-#include "aes.h"
-
-/* #define FULL_UNROLL */
-#define AES_SMALL_TABLES
-
-extern const u32 Te0[256];
-extern const u32 Te1[256];
-extern const u32 Te2[256];
-extern const u32 Te3[256];
-extern const u32 Te4[256];
-extern const u32 Td0[256];
-extern const u32 Td1[256];
-extern const u32 Td2[256];
-extern const u32 Td3[256];
-extern const u32 Td4[256];
-extern const u32 rcon[10];
-extern const u8 Td4s[256];
-extern const u8 rcons[10];
-
-#ifndef AES_SMALL_TABLES
-
-#define RCON(i) rcon[(i)]
-
-#define TE0(i) Te0[((i) >> 24) & 0xff]
-#define TE1(i) Te1[((i) >> 16) & 0xff]
-#define TE2(i) Te2[((i) >> 8) & 0xff]
-#define TE3(i) Te3[(i) & 0xff]
-#define TE41(i) (Te4[((i) >> 24) & 0xff] & 0xff000000)
-#define TE42(i) (Te4[((i) >> 16) & 0xff] & 0x00ff0000)
-#define TE43(i) (Te4[((i) >> 8) & 0xff] & 0x0000ff00)
-#define TE44(i) (Te4[(i) & 0xff] & 0x000000ff)
-#define TE421(i) (Te4[((i) >> 16) & 0xff] & 0xff000000)
-#define TE432(i) (Te4[((i) >> 8) & 0xff] & 0x00ff0000)
-#define TE443(i) (Te4[(i) & 0xff] & 0x0000ff00)
-#define TE414(i) (Te4[((i) >> 24) & 0xff] & 0x000000ff)
-#define TE411(i) (Te4[((i) >> 24) & 0xff] & 0xff000000)
-#define TE422(i) (Te4[((i) >> 16) & 0xff] & 0x00ff0000)
-#define TE433(i) (Te4[((i) >> 8) & 0xff] & 0x0000ff00)
-#define TE444(i) (Te4[(i) & 0xff] & 0x000000ff)
-#define TE4(i) (Te4[(i)] & 0x000000ff)
-
-#define TD0(i) Td0[((i) >> 24) & 0xff]
-#define TD1(i) Td1[((i) >> 16) & 0xff]
-#define TD2(i) Td2[((i) >> 8) & 0xff]
-#define TD3(i) Td3[(i) & 0xff]
-#define TD41(i) (Td4[((i) >> 24) & 0xff] & 0xff000000)
-#define TD42(i) (Td4[((i) >> 16) & 0xff] & 0x00ff0000)
-#define TD43(i) (Td4[((i) >> 8) & 0xff] & 0x0000ff00)
-#define TD44(i) (Td4[(i) & 0xff] & 0x000000ff)
-#define TD0_(i) Td0[(i) & 0xff]
-#define TD1_(i) Td1[(i) & 0xff]
-#define TD2_(i) Td2[(i) & 0xff]
-#define TD3_(i) Td3[(i) & 0xff]
-
-#else /* AES_SMALL_TABLES */
-
-#define RCON(i) (rcons[(i)] << 24)
-
-static inline u32 rotr(u32 val, int bits)
-{
-	return (val >> bits) | (val << (32 - bits));
-}
-
-#define TE0(i) Te0[((i) >> 24) & 0xff]
-#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)
-#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)
-#define TE3(i) rotr(Te0[(i) & 0xff], 24)
-#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)
-#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)
-#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)
-#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)
-#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000)
-#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000)
-#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00)
-#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff)
-#define TE411(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)
-#define TE422(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)
-#define TE433(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)
-#define TE444(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)
-#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff)
-
-#define TD0(i) Td0[((i) >> 24) & 0xff]
-#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)
-#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)
-#define TD3(i) rotr(Td0[(i) & 0xff], 24)
-#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24)
-#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16)
-#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8)
-#define TD44(i) (Td4s[(i) & 0xff])
-#define TD0_(i) Td0[(i) & 0xff]
-#define TD1_(i) rotr(Td0[(i) & 0xff], 8)
-#define TD2_(i) rotr(Td0[(i) & 0xff], 16)
-#define TD3_(i) rotr(Td0[(i) & 0xff], 24)
-
-#endif /* AES_SMALL_TABLES */
-
-#ifdef _MSC_VER
-#define SWAP(x) (_lrotl(x, 8) & 0x00ff00ff | _lrotr(x, 8) & 0xff00ff00)
-#define GETU32(p) SWAP(*((u32 *)(p)))
-#define PUTU32(ct, st) { *((u32 *)(ct)) = SWAP((st)); }
-#else
-#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \
-((u32)(pt)[2] <<  8) ^ ((u32)(pt)[3]))
-#define PUTU32(ct, st) { \
-(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \
-(ct)[2] = (u8)((st) >>  8); (ct)[3] = (u8)(st); }
-#endif
-
-#define AES_PRIV_SIZE (4 * 4 * 15 + 4)
-#define AES_PRIV_NR_POS (4 * 15)
-
-int rijndaelKeySetupEnc(u32 rk[], const u8 cipherKey[], int keyBits);
-
-#endif /* AES_I_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/aes_wrap.h b/tools/sdk/include/wpa_supplicant/crypto/aes_wrap.h
deleted file mode 100644
index 933031e4bad..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/aes_wrap.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * AES-based functions
- *
- * - AES Key Wrap Algorithm (128-bit KEK) (RFC3394)
- * - One-Key CBC MAC (OMAC1) hash with AES-128
- * - AES-128 CTR mode encryption
- * - AES-128 EAX mode encryption/decryption
- * - AES-128 CBC
- *
- * Copyright (c) 2003-2007, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef AES_WRAP_H
-#define AES_WRAP_H
-
-int __must_check aes_wrap(const u8 *kek, int n, const u8 *plain, u8 *cipher);
-int __must_check aes_unwrap(const u8 *kek, int n, const u8 *cipher, u8 *plain);
-int __must_check omac1_aes_128_vector(const u8 *key, size_t num_elem,
-				      const u8 *addr[], const size_t *len,
-				      u8 *mac);
-int __must_check omac1_aes_128(const u8 *key, const u8 *data, size_t data_len,
-			       u8 *mac);
-int __must_check aes_128_encrypt_block(const u8 *key, const u8 *in, u8 *out);
-int __must_check aes_128_ctr_encrypt(const u8 *key, const u8 *nonce,
-				     u8 *data, size_t data_len);
-int __must_check aes_128_eax_encrypt(const u8 *key,
-				     const u8 *nonce, size_t nonce_len,
-				     const u8 *hdr, size_t hdr_len,
-				     u8 *data, size_t data_len, u8 *tag);
-int __must_check aes_128_eax_decrypt(const u8 *key,
-				     const u8 *nonce, size_t nonce_len,
-				     const u8 *hdr, size_t hdr_len,
-				     u8 *data, size_t data_len, const u8 *tag);
-int __must_check aes_128_cbc_encrypt(const u8 *key, const u8 *iv, u8 *data,
-				     size_t data_len);
-int __must_check aes_128_cbc_decrypt(const u8 *key, const u8 *iv, u8 *data,
-				     size_t data_len);
-int __must_check fast_aes_wrap(const uint8_t *kek, int n, const uint8_t *plain, uint8_t *cipher);
-int __must_check fast_aes_unwrap(const uint8_t *kek, int n, const uint8_t *cipher, uint8_t *plain);
-int __must_check fast_aes_128_cbc_encrypt(const uint8_t *key, const uint8_t *iv, uint8_t *data,
-				          size_t data_len);
-int __must_check fast_aes_128_cbc_decrypt(const uint8_t *key, const uint8_t *iv, uint8_t *data,
-				          size_t data_len);
-#endif /* AES_WRAP_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/base64.h b/tools/sdk/include/wpa_supplicant/crypto/base64.h
deleted file mode 100644
index b87a1682f8d..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/base64.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Base64 encoding/decoding (RFC1341)
- * Copyright (c) 2005, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef BASE64_H
-#define BASE64_H
-
-unsigned char * base64_encode(const unsigned char *src, size_t len,
-			      size_t *out_len);
-unsigned char * base64_decode(const unsigned char *src, size_t len,
-			      size_t *out_len);
-
-#endif /* BASE64_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/common.h b/tools/sdk/include/wpa_supplicant/crypto/common.h
deleted file mode 100644
index 319b861e45d..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/common.h
+++ /dev/null
@@ -1,481 +0,0 @@
-/*
- * wpa_supplicant/hostapd / common helper functions, etc.
- * Copyright (c) 2002-2007, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef COMMON_H
-#define COMMON_H
-
-#include "os.h"
-
-#if defined(__XTENSA__)
-#include <machine/endian.h>
-#define __BYTE_ORDER     BYTE_ORDER
-#define __LITTLE_ENDIAN  LITTLE_ENDIAN
-#define __BIG_ENDIAN     BIG_ENDIAN
-#endif /*__XTENSA__*/
-
-#if defined(__linux__) || defined(__GLIBC__)
-#include <endian.h>
-#include <byteswap.h>
-#endif /* __linux__ */
-
-#if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || \
-    defined(__OpenBSD__)
-#include <sys/types.h>
-#include <sys/endian.h>
-#define __BYTE_ORDER	_BYTE_ORDER
-#define	__LITTLE_ENDIAN	_LITTLE_ENDIAN
-#define	__BIG_ENDIAN	_BIG_ENDIAN
-#ifdef __OpenBSD__
-#define bswap_16 swap16
-#define bswap_32 swap32
-#define bswap_64 swap64
-#else /* __OpenBSD__ */
-#define bswap_16 bswap16
-#define bswap_32 bswap32
-#define bswap_64 bswap64
-#endif /* __OpenBSD__ */
-#endif /* defined(__FreeBSD__) || defined(__NetBSD__) ||
-	* defined(__DragonFly__) || defined(__OpenBSD__) */
-
-#ifdef __APPLE__
-#include <sys/types.h>
-#include <machine/endian.h>
-#define __BYTE_ORDER	_BYTE_ORDER
-#define __LITTLE_ENDIAN	_LITTLE_ENDIAN
-#define __BIG_ENDIAN	_BIG_ENDIAN
-static inline unsigned short bswap_16(unsigned short v)
-{
-	return ((v & 0xff) << 8) | (v >> 8);
-}
-
-static inline unsigned int bswap_32(unsigned int v)
-{
-	return ((v & 0xff) << 24) | ((v & 0xff00) << 8) |
-		((v & 0xff0000) >> 8) | (v >> 24);
-}
-#endif /* __APPLE__ */
-
-#ifdef CONFIG_TI_COMPILER
-#define __BIG_ENDIAN 4321
-#define __LITTLE_ENDIAN 1234
-#ifdef __big_endian__
-#define __BYTE_ORDER __BIG_ENDIAN
-#else
-#define __BYTE_ORDER __LITTLE_ENDIAN
-#endif
-#endif /* CONFIG_TI_COMPILER */
-
-#ifdef __SYMBIAN32__
-#define __BIG_ENDIAN 4321
-#define __LITTLE_ENDIAN 1234
-#define __BYTE_ORDER __LITTLE_ENDIAN
-#endif /* __SYMBIAN32__ */
-
-#ifdef CONFIG_NATIVE_WINDOWS
-#include <winsock.h>
-
-typedef int socklen_t;
-
-#ifndef MSG_DONTWAIT
-#define MSG_DONTWAIT 0 /* not supported */
-#endif
-
-#endif /* CONFIG_NATIVE_WINDOWS */
-
-#ifdef _MSC_VER
-#define inline __inline
-
-#undef vsnprintf
-#define vsnprintf _vsnprintf
-#undef close
-#define close closesocket
-#endif /* _MSC_VER */
-
-
-/* Define platform specific integer types */
-
-#ifdef _MSC_VER
-typedef UINT64 u64;
-typedef UINT32 u32;
-typedef UINT16 u16;
-typedef UINT8 u8;
-typedef INT64 s64;
-typedef INT32 s32;
-typedef INT16 s16;
-typedef INT8 s8;
-#define WPA_TYPES_DEFINED
-#endif /* _MSC_VER */
-
-#ifdef __vxworks
-typedef unsigned long long u64;
-typedef UINT32 u32;
-typedef UINT16 u16;
-typedef UINT8 u8;
-typedef long long s64;
-typedef INT32 s32;
-typedef INT16 s16;
-typedef INT8 s8;
-#define WPA_TYPES_DEFINED
-#endif /* __vxworks */
-
-#ifdef CONFIG_TI_COMPILER
-#ifdef _LLONG_AVAILABLE
-typedef unsigned long long u64;
-#else
-/*
- * TODO: 64-bit variable not available. Using long as a workaround to test the
- * build, but this will likely not work for all operations.
- */
-typedef unsigned long u64;
-#endif
-typedef unsigned int u32;
-typedef unsigned short u16;
-typedef unsigned char u8;
-#define WPA_TYPES_DEFINED
-#endif /* CONFIG_TI_COMPILER */
-
-#ifdef __SYMBIAN32__
-#define __REMOVE_PLATSEC_DIAGNOSTICS__
-#include <e32def.h>
-typedef TUint64 u64;
-typedef TUint32 u32;
-typedef TUint16 u16;
-typedef TUint8 u8;
-#define WPA_TYPES_DEFINED
-#endif /* __SYMBIAN32__ */
-
-#ifndef WPA_TYPES_DEFINED
-#ifdef CONFIG_USE_INTTYPES_H
-#include <inttypes.h>
-#else
-#include <stdint.h>
-#endif
-
-typedef uint64_t u64;
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-typedef int64_t s64;
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-#define WPA_TYPES_DEFINED
-#endif /* !WPA_TYPES_DEFINED */
-
-
-/* Define platform specific byte swapping macros */
-
-#if defined(__CYGWIN__) || defined(CONFIG_NATIVE_WINDOWS)
-
-static inline unsigned short wpa_swap_16(unsigned short v)
-{
-	return ((v & 0xff) << 8) | (v >> 8);
-}
-
-static inline unsigned int wpa_swap_32(unsigned int v)
-{
-	return ((v & 0xff) << 24) | ((v & 0xff00) << 8) |
-		((v & 0xff0000) >> 8) | (v >> 24);
-}
-
-#define le_to_host16(n) (n)
-#define host_to_le16(n) (n)
-#define be_to_host16(n) wpa_swap_16(n)
-#define host_to_be16(n) wpa_swap_16(n)
-#define le_to_host32(n) (n)
-#define be_to_host32(n) wpa_swap_32(n)
-#define host_to_be32(n) wpa_swap_32(n)
-
-#define WPA_BYTE_SWAP_DEFINED
-
-#endif /* __CYGWIN__ || CONFIG_NATIVE_WINDOWS */
-
-
-#ifndef WPA_BYTE_SWAP_DEFINED
-
-#ifndef __BYTE_ORDER
-#ifndef __LITTLE_ENDIAN
-#ifndef __BIG_ENDIAN
-#define __LITTLE_ENDIAN 1234
-#define __BIG_ENDIAN 4321
-#if defined(sparc)
-#define __BYTE_ORDER __BIG_ENDIAN
-#endif
-#endif /* __BIG_ENDIAN */
-#endif /* __LITTLE_ENDIAN */
-#endif /* __BYTE_ORDER */
-
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-#define le_to_host16(n) ((__force u16) (le16) (n))
-#define host_to_le16(n) ((__force le16) (u16) (n))
-#define be_to_host16(n) bswap_16((__force u16) (be16) (n))
-#define host_to_be16(n) ((__force be16) bswap_16((n)))
-#define le_to_host32(n) ((__force u32) (le32) (n))
-#define host_to_le32(n) ((__force le32) (u32) (n))
-#define be_to_host32(n) bswap_32((__force u32) (be32) (n))
-#define host_to_be32(n) ((__force be32) bswap_32((n)))
-#define le_to_host64(n) ((__force u64) (le64) (n))
-#define host_to_le64(n) ((__force le64) (u64) (n))
-#define be_to_host64(n) bswap_64((__force u64) (be64) (n))
-#define host_to_be64(n) ((__force be64) bswap_64((n)))
-#elif __BYTE_ORDER == __BIG_ENDIAN
-#define le_to_host16(n) bswap_16(n)
-#define host_to_le16(n) bswap_16(n)
-#define be_to_host16(n) (n)
-#define host_to_be16(n) (n)
-#define le_to_host32(n) bswap_32(n)
-#define be_to_host32(n) (n)
-#define host_to_be32(n) (n)
-#define le_to_host64(n) bswap_64(n)
-#define host_to_le64(n) bswap_64(n)
-#define be_to_host64(n) (n)
-#define host_to_be64(n) (n)
-#ifndef WORDS_BIGENDIAN
-#define WORDS_BIGENDIAN
-#endif
-#else
-#error Could not determine CPU byte order
-#endif
-
-#define WPA_BYTE_SWAP_DEFINED
-#endif /* !WPA_BYTE_SWAP_DEFINED */
-
-
-/* Macros for handling unaligned memory accesses */
-
-#define WPA_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
-#define WPA_PUT_BE16(a, val)			\
-	do {					\
-		(a)[0] = ((u16) (val)) >> 8;	\
-		(a)[1] = ((u16) (val)) & 0xff;	\
-	} while (0)
-
-#define WPA_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))
-#define WPA_PUT_LE16(a, val)			\
-	do {					\
-		(a)[1] = ((u16) (val)) >> 8;	\
-		(a)[0] = ((u16) (val)) & 0xff;	\
-	} while (0)
-
-#define WPA_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
-			 ((u32) (a)[2]))
-#define WPA_PUT_BE24(a, val)					\
-	do {							\
-		(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-		(a)[2] = (u8) (((u32) (val)) & 0xff);		\
-	} while (0)
-
-#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
-			 (((u32) (a)[2]) << 8) | ((u32) (a)[3]))
-#define WPA_PUT_BE32(a, val)					\
-	do {							\
-		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
-		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
-	} while (0)
-
-#define WPA_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
-			 (((u32) (a)[1]) << 8) | ((u32) (a)[0]))
-#define WPA_PUT_LE32(a, val)					\
-	do {							\
-		(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
-		(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-		(a)[0] = (u8) (((u32) (val)) & 0xff);		\
-	} while (0)
-
-#define WPA_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
-			 (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
-			 (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
-			 (((u64) (a)[6]) << 8) | ((u64) (a)[7]))
-#define WPA_PUT_BE64(a, val)				\
-	do {						\
-		(a)[0] = (u8) (((u64) (val)) >> 56);	\
-		(a)[1] = (u8) (((u64) (val)) >> 48);	\
-		(a)[2] = (u8) (((u64) (val)) >> 40);	\
-		(a)[3] = (u8) (((u64) (val)) >> 32);	\
-		(a)[4] = (u8) (((u64) (val)) >> 24);	\
-		(a)[5] = (u8) (((u64) (val)) >> 16);	\
-		(a)[6] = (u8) (((u64) (val)) >> 8);	\
-		(a)[7] = (u8) (((u64) (val)) & 0xff);	\
-	} while (0)
-
-#define WPA_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \
-			 (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \
-			 (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \
-			 (((u64) (a)[1]) << 8) | ((u64) (a)[0]))
-
-
-#ifndef ETH_ALEN
-#define ETH_ALEN 6
-#endif
-#ifndef IFNAMSIZ
-#define IFNAMSIZ 16
-#endif
-#ifndef ETH_P_ALL
-#define ETH_P_ALL 0x0003
-#endif
-#ifndef ETH_P_PAE
-#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
-#endif /* ETH_P_PAE */
-#ifndef ETH_P_EAPOL
-#define ETH_P_EAPOL ETH_P_PAE
-#endif /* ETH_P_EAPOL */
-#ifndef ETH_P_RSN_PREAUTH
-#define ETH_P_RSN_PREAUTH 0x88c7
-#endif /* ETH_P_RSN_PREAUTH */
-#ifndef ETH_P_RRB
-#define ETH_P_RRB 0x890D
-#endif /* ETH_P_RRB */
-
-
-#ifdef __GNUC__
-#define PRINTF_FORMAT(a,b) __attribute__ ((format (printf, (a), (b))))
-#define STRUCT_PACKED __attribute__ ((packed))
-#else
-#define PRINTF_FORMAT(a,b)
-#define STRUCT_PACKED
-#endif
-
-#ifdef CONFIG_ANSI_C_EXTRA
-
-#if !defined(_MSC_VER) || _MSC_VER < 1400
-/* snprintf - used in number of places; sprintf() is _not_ a good replacement
- * due to possible buffer overflow; see, e.g.,
- * http://www.ijs.si/software/snprintf/ for portable implementation of
- * snprintf. */
-int snprintf(char *str, size_t size, const char *format, ...);
-
-/* vsnprintf - only used for wpa_msg() in wpa_supplicant.c */
-int vsnprintf(char *str, size_t size, const char *format, va_list ap);
-#endif /* !defined(_MSC_VER) || _MSC_VER < 1400 */
-
-/* getopt - only used in main.c */
-int getopt(int argc, char *const argv[], const char *optstring);
-extern char *optarg;
-extern int optind;
-
-#ifndef CONFIG_NO_SOCKLEN_T_TYPEDEF
-#ifndef __socklen_t_defined
-typedef int socklen_t;
-#endif
-#endif
-
-/* inline - define as __inline or just define it to be empty, if needed */
-#ifdef CONFIG_NO_INLINE
-#define inline
-#else
-#define inline __inline
-#endif
-
-#ifndef __func__
-#define __func__ "__func__ not defined"
-#endif
-
-#ifndef bswap_16
-#define bswap_16(a) ((((u16) (a) << 8) & 0xff00) | (((u16) (a) >> 8) & 0xff))
-#endif
-
-#ifndef bswap_32
-#define bswap_32(a) ((((u32) (a) << 24) & 0xff000000) | \
-		     (((u32) (a) << 8) & 0xff0000) | \
-     		     (((u32) (a) >> 8) & 0xff00) | \
-     		     (((u32) (a) >> 24) & 0xff))
-#endif
-
-#ifndef MSG_DONTWAIT
-#define MSG_DONTWAIT 0
-#endif
-
-#ifdef _WIN32_WCE
-void perror(const char *s);
-#endif /* _WIN32_WCE */
-
-#endif /* CONFIG_ANSI_C_EXTRA */
-
-#ifndef MAC2STR
-#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
-#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
-#endif
-
-#ifndef BIT
-#define BIT(x) (1 << (x))
-#endif
-
-/*
- * Definitions for sparse validation
- * (http://kernel.org/pub/linux/kernel/people/josh/sparse/)
- */
-#ifdef __CHECKER__
-#define __force __attribute__((force))
-#define __bitwise __attribute__((bitwise))
-#else
-#define __force
-#define __bitwise
-#endif
-
-typedef u16 __bitwise be16;
-typedef u16 __bitwise le16;
-typedef u32 __bitwise be32;
-typedef u32 __bitwise le32;
-typedef u64 __bitwise be64;
-typedef u64 __bitwise le64;
-
-#ifndef __must_check
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
-#define __must_check __attribute__((__warn_unused_result__))
-#else
-#define __must_check
-#endif /* __GNUC__ */
-#endif /* __must_check */
-
-int hwaddr_aton(const char *txt, u8 *addr);
-int hwaddr_aton2(const char *txt, u8 *addr);
-int hexstr2bin(const char *hex, u8 *buf, size_t len);
-void inc_byte_array(u8 *counter, size_t len);
-void wpa_get_ntp_timestamp(u8 *buf);
-int wpa_snprintf_hex(char *buf, size_t buf_size, const u8 *data, size_t len);
-int wpa_snprintf_hex_uppercase(char *buf, size_t buf_size, const u8 *data,
-			       size_t len);
-
-#ifdef CONFIG_NATIVE_WINDOWS
-void wpa_unicode2ascii_inplace(TCHAR *str);
-TCHAR * wpa_strdup_tchar(const char *str);
-#else /* CONFIG_NATIVE_WINDOWS */
-#define wpa_unicode2ascii_inplace(s) do { } while (0)
-#define wpa_strdup_tchar(s) strdup((s))
-#endif /* CONFIG_NATIVE_WINDOWS */
-
-const char * wpa_ssid_txt(const u8 *ssid, size_t ssid_len);
-
-static inline int is_zero_ether_addr(const u8 *a)
-{
-	return !(a[0] | a[1] | a[2] | a[3] | a[4] | a[5]);
-}
-
-/*
- * gcc 4.4 ends up generating strict-aliasing warnings about some very common
- * networking socket uses that do not really result in a real problem and
- * cannot be easily avoided with union-based type-punning due to struct
- * definitions including another struct in system header files. To avoid having
- * to fully disable strict-aliasing warnings, provide a mechanism to hide the
- * typecast from aliasing for now. A cleaner solution will hopefully be found
- * in the future to handle these cases.
- */
-void * __hide_aliasing_typecast(void *foo);
-#define aliasing_hide_typecast(a,t) (t *) __hide_aliasing_typecast((a))
-
-#endif /* COMMON_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/crypto.h b/tools/sdk/include/wpa_supplicant/crypto/crypto.h
deleted file mode 100644
index f6b7b2f2c49..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/crypto.h
+++ /dev/null
@@ -1,968 +0,0 @@
-/*
- * WPA Supplicant / wrapper functions for crypto libraries
- * Copyright (c) 2004-2009, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- *
- * This file defines the cryptographic functions that need to be implemented
- * for wpa_supplicant and hostapd. When TLS is not used, internal
- * implementation of MD5, SHA1, and AES is used and no external libraries are
- * required. When TLS is enabled (e.g., by enabling EAP-TLS or EAP-PEAP), the
- * crypto library used by the TLS implementation is expected to be used for
- * non-TLS needs, too, in order to save space by not implementing these
- * functions twice.
- *
- * Wrapper code for using each crypto library is in its own file (crypto*.c)
- * and one of these files is build and linked in to provide the functions
- * defined here.
- */
-
-#ifndef CRYPTO_H
-#define CRYPTO_H
-
-#include "common.h"
-
-/**
- * md4_vector - MD4 hash for data vector
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash
- * Returns: 0 on success, -1 on failure
- */
-int md4_vector(size_t num_elem, const u8 *addr[], const size_t *len, u8 *mac);
-
-/**
- * md5_vector - MD5 hash for data vector
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash
- * Returns: 0 on success, -1 on failure
- */
-int md5_vector(size_t num_elem, const u8 *addr[], const size_t *len, u8 *mac);
-
-#ifdef CONFIG_FIPS
-/**
- * md5_vector_non_fips_allow - MD5 hash for data vector (non-FIPS use allowed)
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash
- * Returns: 0 on success, -1 on failure
- */
-int md5_vector_non_fips_allow(size_t num_elem, const u8 *addr[],
-			      const size_t *len, u8 *mac);
-#else /* CONFIG_FIPS */
-#define md5_vector_non_fips_allow md5_vector
-#endif /* CONFIG_FIPS */
-
-
-/**
- * sha1_vector - SHA-1 hash for data vector
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash
- * Returns: 0 on success, -1 on failure
- */
-int sha1_vector(size_t num_elem, const u8 *addr[], const size_t *len,
-		u8 *mac);
-
-/**
- * fips186_2-prf - NIST FIPS Publication 186-2 change notice 1 PRF
- * @seed: Seed/key for the PRF
- * @seed_len: Seed length in bytes
- * @x: Buffer for PRF output
- * @xlen: Output length in bytes
- * Returns: 0 on success, -1 on failure
- *
- * This function implements random number generation specified in NIST FIPS
- * Publication 186-2 for EAP-SIM. This PRF uses a function that is similar to
- * SHA-1, but has different message padding.
- */
-int __must_check fips186_2_prf(const u8 *seed, size_t seed_len, u8 *x,
-			       size_t xlen);
-
-/**
- * sha256_vector - SHA256 hash for data vector
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash
- * Returns: 0 on success, -1 on failure
- */
-int sha256_vector(size_t num_elem, const u8 *addr[], const size_t *len,
-		  u8 *mac);
-
-/**
- * fast_sha256_vector - fast SHA256 hash for data vector
- * @num_elem: Number of elements in the data vector
- * @addr: Pointers to the data areas
- * @len: Lengths of the data blocks
- * @mac: Buffer for the hash
- * Returns: 0 on success, -1 on failure
- */
-int fast_sha256_vector(size_t num_elem, const uint8_t *addr[], const size_t *len,
-		       uint8_t *mac);
-
-/**
- * des_encrypt - Encrypt one block with DES
- * @clear: 8 octets (in)
- * @key: 7 octets (in) (no parity bits included)
- * @cypher: 8 octets (out)
- */
-void des_encrypt(const u8 *clear, const u8 *key, u8 *cypher);
-
-/**
- * aes_encrypt_init - Initialize AES for encryption
- * @key: Encryption key
- * @len: Key length in bytes (usually 16, i.e., 128 bits)
- * Returns: Pointer to context data or %NULL on failure
- */
-void * aes_encrypt_init(const u8 *key, size_t len);
-
-/**
- * aes_encrypt - Encrypt one AES block
- * @ctx: Context pointer from aes_encrypt_init()
- * @plain: Plaintext data to be encrypted (16 bytes)
- * @crypt: Buffer for the encrypted data (16 bytes)
- */
-void aes_encrypt(void *ctx, const u8 *plain, u8 *crypt);
-
-/**
- * aes_encrypt_deinit - Deinitialize AES encryption
- * @ctx: Context pointer from aes_encrypt_init()
- */
-void aes_encrypt_deinit(void *ctx);
-
-/**
- * aes_decrypt_init - Initialize AES for decryption
- * @key: Decryption key
- * @len: Key length in bytes (usually 16, i.e., 128 bits)
- * Returns: Pointer to context data or %NULL on failure
- */
-void * aes_decrypt_init(const u8 *key, size_t len);
-
-/**
- * aes_decrypt - Decrypt one AES block
- * @ctx: Context pointer from aes_encrypt_init()
- * @crypt: Encrypted data (16 bytes)
- * @plain: Buffer for the decrypted data (16 bytes)
- */
-void aes_decrypt(void *ctx, const u8 *crypt, u8 *plain);
-
-/**
- * aes_decrypt_deinit - Deinitialize AES decryption
- * @ctx: Context pointer from aes_encrypt_init()
- */
-void aes_decrypt_deinit(void *ctx);
-
-
-enum crypto_hash_alg {
-        CRYPTO_HASH_ALG_MD5, CRYPTO_HASH_ALG_SHA1,
-        CRYPTO_HASH_ALG_HMAC_MD5, CRYPTO_HASH_ALG_HMAC_SHA1,
-        CRYPTO_HASH_ALG_SHA256, CRYPTO_HASH_ALG_HMAC_SHA256
-};
-
-struct crypto_hash;
-
-/**
- * crypto_hash_init - Initialize hash/HMAC function
- * @alg: Hash algorithm
- * @key: Key for keyed hash (e.g., HMAC) or %NULL if not needed
- * @key_len: Length of the key in bytes
- * Returns: Pointer to hash context to use with other hash functions or %NULL
- * on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-struct crypto_hash * crypto_hash_init(enum crypto_hash_alg alg, const u8 *key,
-				      size_t key_len);
-
-/**
- * fast_crypto_hash_init - Initialize hash/HMAC function
- * @alg: Hash algorithm
- * @key: Key for keyed hash (e.g., HMAC) or %NULL if not needed
- * @key_len: Length of the key in bytes
- * Returns: Pointer to hash context to use with other hash functions or %NULL
- * on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-struct crypto_hash * fast_crypto_hash_init(enum crypto_hash_alg alg, const uint8_t *key,
-				                size_t key_len);
-
-/**
- * crypto_hash_update - Add data to hash calculation
- * @ctx: Context pointer from crypto_hash_init()
- * @data: Data buffer to add
- * @len: Length of the buffer
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-void crypto_hash_update(struct crypto_hash *ctx, const u8 *data, size_t len);
-
-/**
- * fast_crypto_hash_update - Add data to hash calculation
- * @ctx: Context pointer from crypto_hash_init()
- * @data: Data buffer to add
- * @len: Length of the buffer
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-void fast_crypto_hash_update(struct crypto_hash *ctx, const uint8_t *data, size_t len);
-
-/**
- * crypto_hash_finish - Complete hash calculation
- * @ctx: Context pointer from crypto_hash_init()
- * @hash: Buffer for hash value or %NULL if caller is just freeing the hash
- * context
- * @len: Pointer to length of the buffer or %NULL if caller is just freeing the
- * hash context; on return, this is set to the actual length of the hash value
- * Returns: 0 on success, -1 if buffer is too small (len set to needed length),
- * or -2 on other failures (including failed crypto_hash_update() operations)
- *
- * This function calculates the hash value and frees the context buffer that
- * was used for hash calculation.
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int crypto_hash_finish(struct crypto_hash *ctx, u8 *hash, size_t *len);
-
-/**
- * fast_crypto_hash_finish - Complete hash calculation
- * @ctx: Context pointer from crypto_hash_init()
- * @hash: Buffer for hash value or %NULL if caller is just freeing the hash
- * context
- * @len: Pointer to length of the buffer or %NULL if caller is just freeing the
- * hash context; on return, this is set to the actual length of the hash value
- * Returns: 0 on success, -1 if buffer is too small (len set to needed length),
- * or -2 on other failures (including failed crypto_hash_update() operations)
- *
- * This function calculates the hash value and frees the context buffer that
- * was used for hash calculation.
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int fast_crypto_hash_finish(struct crypto_hash *ctx, uint8_t *hash, size_t *len);
-
-
-enum crypto_cipher_alg {
-	CRYPTO_CIPHER_NULL = 0, CRYPTO_CIPHER_ALG_AES, CRYPTO_CIPHER_ALG_3DES,
-	CRYPTO_CIPHER_ALG_DES, CRYPTO_CIPHER_ALG_RC2, CRYPTO_CIPHER_ALG_RC4
-};
-
-struct crypto_cipher;
-
-/**
- * crypto_cipher_init - Initialize block/stream cipher function
- * @alg: Cipher algorithm
- * @iv: Initialization vector for block ciphers or %NULL for stream ciphers
- * @key: Cipher key
- * @key_len: Length of key in bytes
- * Returns: Pointer to cipher context to use with other cipher functions or
- * %NULL on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-struct crypto_cipher * crypto_cipher_init(enum crypto_cipher_alg alg,
-					  const u8 *iv, const u8 *key,
-					  size_t key_len);
-
-/**
- * fast_crypto_cipher_init - Initialize block/stream cipher function
- * @alg: Cipher algorithm
- * @iv: Initialization vector for block ciphers or %NULL for stream ciphers
- * @key: Cipher key
- * @key_len: Length of key in bytes
- * Returns: Pointer to cipher context to use with other cipher functions or
- * %NULL on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-struct crypto_cipher * fast_crypto_cipher_init(enum crypto_cipher_alg alg,
-					            const uint8_t *iv, const uint8_t *key,
-					            size_t key_len);
-/**
- * crypto_cipher_encrypt - Cipher encrypt
- * @ctx: Context pointer from crypto_cipher_init()
- * @plain: Plaintext to cipher
- * @crypt: Resulting ciphertext
- * @len: Length of the plaintext
- * Returns: 0 on success, -1 on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check crypto_cipher_encrypt(struct crypto_cipher *ctx,
-				       const u8 *plain, u8 *crypt, size_t len);
-
-/**
- * fast_crypto_cipher_encrypt - Cipher encrypt
- * @ctx: Context pointer from crypto_cipher_init()
- * @plain: Plaintext to cipher
- * @crypt: Resulting ciphertext
- * @len: Length of the plaintext
- * Returns: 0 on success, -1 on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check fast_crypto_cipher_encrypt(struct crypto_cipher *ctx,
-				            const uint8_t *plain, uint8_t *crypt, size_t len);
-
-/**
- * crypto_cipher_decrypt - Cipher decrypt
- * @ctx: Context pointer from crypto_cipher_init()
- * @crypt: Ciphertext to decrypt
- * @plain: Resulting plaintext
- * @len: Length of the cipher text
- * Returns: 0 on success, -1 on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check crypto_cipher_decrypt(struct crypto_cipher *ctx,
-				       const u8 *crypt, u8 *plain, size_t len);
-
-/**
- * fast_crypto_cipher_decrypt - Cipher decrypt
- * @ctx: Context pointer from crypto_cipher_init()
- * @crypt: Ciphertext to decrypt
- * @plain: Resulting plaintext
- * @len: Length of the cipher text
- * Returns: 0 on success, -1 on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check fast_crypto_cipher_decrypt(struct crypto_cipher *ctx,
-				            const uint8_t *crypt, uint8_t *plain, size_t len);
-
-/**
- * crypto_cipher_decrypt - Free cipher context
- * @ctx: Context pointer from crypto_cipher_init()
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-void crypto_cipher_deinit(struct crypto_cipher *ctx);
-
-/**
- * fast_crypto_cipher_decrypt - Free cipher context
- * @ctx: Context pointer from crypto_cipher_init()
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-void fast_crypto_cipher_deinit(struct crypto_cipher *ctx);
-
-struct crypto_public_key;
-struct crypto_private_key;
-
-/**
- * crypto_public_key_import - Import an RSA public key
- * @key: Key buffer (DER encoded RSA public key)
- * @len: Key buffer length in bytes
- * Returns: Pointer to the public key or %NULL on failure
- *
- * This function can just return %NULL if the crypto library supports X.509
- * parsing. In that case, crypto_public_key_from_cert() is used to import the
- * public key from a certificate.
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-struct crypto_public_key * crypto_public_key_import(const u8 *key, size_t len);
-
-/**
- * crypto_private_key_import - Import an RSA private key
- * @key: Key buffer (DER encoded RSA private key)
- * @len: Key buffer length in bytes
- * @passwd: Key encryption password or %NULL if key is not encrypted
- * Returns: Pointer to the private key or %NULL on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-struct crypto_private_key * crypto_private_key_import(const u8 *key,
-						      size_t len,
-						      const char *passwd);
-
-/**
- * crypto_public_key_from_cert - Import an RSA public key from a certificate
- * @buf: DER encoded X.509 certificate
- * @len: Certificate buffer length in bytes
- * Returns: Pointer to public key or %NULL on failure
- *
- * This function can just return %NULL if the crypto library does not support
- * X.509 parsing. In that case, internal code will be used to parse the
- * certificate and public key is imported using crypto_public_key_import().
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-struct crypto_public_key * crypto_public_key_from_cert(const u8 *buf,
-						       size_t len);
-
-/**
- * crypto_public_key_encrypt_pkcs1_v15 - Public key encryption (PKCS #1 v1.5)
- * @key: Public key
- * @in: Plaintext buffer
- * @inlen: Length of plaintext buffer in bytes
- * @out: Output buffer for encrypted data
- * @outlen: Length of output buffer in bytes; set to used length on success
- * Returns: 0 on success, -1 on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check crypto_public_key_encrypt_pkcs1_v15(
-	struct crypto_public_key *key, const u8 *in, size_t inlen,
-	u8 *out, size_t *outlen);
-
-/**
- * crypto_private_key_decrypt_pkcs1_v15 - Private key decryption (PKCS #1 v1.5)
- * @key: Private key
- * @in: Encrypted buffer
- * @inlen: Length of encrypted buffer in bytes
- * @out: Output buffer for encrypted data
- * @outlen: Length of output buffer in bytes; set to used length on success
- * Returns: 0 on success, -1 on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check crypto_private_key_decrypt_pkcs1_v15(
-	struct crypto_private_key *key, const u8 *in, size_t inlen,
-	u8 *out, size_t *outlen);
-
-/**
- * crypto_private_key_sign_pkcs1 - Sign with private key (PKCS #1)
- * @key: Private key from crypto_private_key_import()
- * @in: Plaintext buffer
- * @inlen: Length of plaintext buffer in bytes
- * @out: Output buffer for encrypted (signed) data
- * @outlen: Length of output buffer in bytes; set to used length on success
- * Returns: 0 on success, -1 on failure
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check crypto_private_key_sign_pkcs1(struct crypto_private_key *key,
-					       const u8 *in, size_t inlen,
-					       u8 *out, size_t *outlen);
-
-/**
- * crypto_public_key_free - Free public key
- * @key: Public key
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-void crypto_public_key_free(struct crypto_public_key *key);
-
-/**
- * crypto_private_key_free - Free private key
- * @key: Private key from crypto_private_key_import()
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-void crypto_private_key_free(struct crypto_private_key *key);
-
-/**
- * crypto_public_key_decrypt_pkcs1 - Decrypt PKCS #1 signature
- * @key: Public key
- * @crypt: Encrypted signature data (using the private key)
- * @crypt_len: Encrypted signature data length
- * @plain: Buffer for plaintext (at least crypt_len bytes)
- * @plain_len: Plaintext length (max buffer size on input, real len on output);
- * Returns: 0 on success, -1 on failure
- */
-int __must_check crypto_public_key_decrypt_pkcs1(
-	struct crypto_public_key *key, const u8 *crypt, size_t crypt_len,
-	u8 *plain, size_t *plain_len);
-
-/**
- * crypto_global_init - Initialize crypto wrapper
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check crypto_global_init(void);
-
-/**
- * crypto_global_deinit - Deinitialize crypto wrapper
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-void crypto_global_deinit(void);
-
-/**
- * crypto_mod_exp - Modular exponentiation of large integers
- * @base: Base integer (big endian byte array)
- * @base_len: Length of base integer in bytes
- * @power: Power integer (big endian byte array)
- * @power_len: Length of power integer in bytes
- * @modulus: Modulus integer (big endian byte array)
- * @modulus_len: Length of modulus integer in bytes
- * @result: Buffer for the result
- * @result_len: Result length (max buffer size on input, real len on output)
- * Returns: 0 on success, -1 on failure
- *
- * This function calculates result = base ^ power mod modulus. modules_len is
- * used as the maximum size of modulus buffer. It is set to the used size on
- * success.
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check crypto_mod_exp(const u8 *base, size_t base_len,
-				const u8 *power, size_t power_len,
-				const u8 *modulus, size_t modulus_len,
-				u8 *result, size_t *result_len);
-
-/**
- * fast_crypto_mod_exp - Modular exponentiation of large integers
- * @base: Base integer (big endian byte array)
- * @base_len: Length of base integer in bytes
- * @power: Power integer (big endian byte array)
- * @power_len: Length of power integer in bytes
- * @modulus: Modulus integer (big endian byte array)
- * @modulus_len: Length of modulus integer in bytes
- * @result: Buffer for the result
- * @result_len: Result length (max buffer size on input, real len on output)
- * Returns: 0 on success, -1 on failure
- *
- * This function calculates result = base ^ power mod modulus. modules_len is
- * used as the maximum size of modulus buffer. It is set to the used size on
- * success.
- *
- * This function is only used with internal TLSv1 implementation
- * (CONFIG_TLS=internal). If that is not used, the crypto wrapper does not need
- * to implement this.
- */
-int __must_check fast_crypto_mod_exp(const uint8_t *base, size_t base_len,
-				     const uint8_t *power, size_t power_len,
-				     const uint8_t *modulus, size_t modulus_len,
-				     uint8_t *result, size_t *result_len);
-
-/**
- * rc4_skip - XOR RC4 stream to given data with skip-stream-start
- * @key: RC4 key
- * @keylen: RC4 key length
- * @skip: number of bytes to skip from the beginning of the RC4 stream
- * @data: data to be XOR'ed with RC4 stream
- * @data_len: buf length
- * Returns: 0 on success, -1 on failure
- *
- * Generate RC4 pseudo random stream for the given key, skip beginning of the
- * stream, and XOR the end result with the data buffer to perform RC4
- * encryption/decryption.
- */
-int rc4_skip(const u8 *key, size_t keylen, size_t skip,
-	     u8 *data, size_t data_len);
-
-
-/**
- * crypto_get_random - Generate cryptographically strong pseudy-random bytes
- * @buf: Buffer for data
- * @len: Number of bytes to generate
- * Returns: 0 on success, -1 on failure
- *
- * If the PRNG does not have enough entropy to ensure unpredictable byte
- * sequence, this functions must return -1.
- */
-int crypto_get_random(void *buf, size_t len);
-
-
-/**
- * struct crypto_bignum - bignum
- *
- * Internal data structure for bignum implementation. The contents is specific
- * to the used crypto library.
- */
-struct crypto_bignum;
-
-/**
- * crypto_bignum_init - Allocate memory for bignum
- * Returns: Pointer to allocated bignum or %NULL on failure
- */
-struct crypto_bignum * crypto_bignum_init(void);
-
-/**
- * crypto_bignum_init_set - Allocate memory for bignum and set the value
- * @buf: Buffer with unsigned binary value
- * @len: Length of buf in octets
- * Returns: Pointer to allocated bignum or %NULL on failure
- */
-struct crypto_bignum * crypto_bignum_init_set(const u8 *buf, size_t len);
-
-/**
- * crypto_bignum_deinit - Free bignum
- * @n: Bignum from crypto_bignum_init() or crypto_bignum_init_set()
- * @clear: Whether to clear the value from memory
- */
-void crypto_bignum_deinit(struct crypto_bignum *n, int clear);
-
-/**
- * crypto_bignum_to_bin - Set binary buffer to unsigned bignum
- * @a: Bignum
- * @buf: Buffer for the binary number
- * @len: Length of @buf in octets
- * @padlen: Length in octets to pad the result to or 0 to indicate no padding
- * Returns: Number of octets written on success, -1 on failure
- */
-int crypto_bignum_to_bin(const struct crypto_bignum *a,
-        u8 *buf, size_t buflen, size_t padlen);
-
-/**
- * crypto_bignum_add - c = a + b
- * @a: Bignum
- * @b: Bignum
- * @c: Bignum; used to store the result of a + b
- * Returns: 0 on success, -1 on failure
- */
-int crypto_bignum_add(const struct crypto_bignum *a,
-        const struct crypto_bignum *b,
-        struct crypto_bignum *c);
-
-/**
- * crypto_bignum_mod - c = a % b
- * @a: Bignum
- * @b: Bignum
- * @c: Bignum; used to store the result of a % b
- * Returns: 0 on success, -1 on failure
- */
-int crypto_bignum_mod(const struct crypto_bignum *a,
-        const struct crypto_bignum *b,
-        struct crypto_bignum *c);
-
-/**
- * crypto_bignum_exptmod - Modular exponentiation: d = a^b (mod c)
- * @a: Bignum; base
- * @b: Bignum; exponent
- * @c: Bignum; modulus
- * @d: Bignum; used to store the result of a^b (mod c)
- * Returns: 0 on success, -1 on failure
- */
-int crypto_bignum_exptmod(const struct crypto_bignum *a,
-        const struct crypto_bignum *b,
-        const struct crypto_bignum *c,
-        struct crypto_bignum *d);
-
-/**
- * crypto_bignum_inverse - Inverse a bignum so that a * c = 1 (mod b)
- * @a: Bignum
- * @b: Bignum
- * @c: Bignum; used to store the result
- * Returns: 0 on success, -1 on failure
- */
-int crypto_bignum_inverse(const struct crypto_bignum *a,
-        const struct crypto_bignum *b,
-        struct crypto_bignum *c);
-
-/**
- * crypto_bignum_sub - c = a - b
- * @a: Bignum
- * @b: Bignum
- * @c: Bignum; used to store the result of a - b
- * Returns: 0 on success, -1 on failure
- */
-int crypto_bignum_sub(const struct crypto_bignum *a,
-        const struct crypto_bignum *b,
-        struct crypto_bignum *c);
-
-/**
- * crypto_bignum_div - c = a / b
- * @a: Bignum
- * @b: Bignum
- * @c: Bignum; used to store the result of a / b
- * Returns: 0 on success, -1 on failure
- */
-int crypto_bignum_div(const struct crypto_bignum *a,
-        const struct crypto_bignum *b,
-        struct crypto_bignum *c);
-
-/**
- * crypto_bignum_mulmod - d = a * b (mod c)
- * @a: Bignum
- * @b: Bignum
- * @c: Bignum
- * @d: Bignum; used to store the result of (a * b) % c
- * Returns: 0 on success, -1 on failure
- */
-int crypto_bignum_mulmod(const struct crypto_bignum *a,
-        const struct crypto_bignum *b,
-        const struct crypto_bignum *c,
-        struct crypto_bignum *d);
-
-/**
- * crypto_bignum_cmp - Compare two bignums
- * @a: Bignum
- * @b: Bignum
- * Returns: -1 if a < b, 0 if a == b, or 1 if a > b
- */
-int crypto_bignum_cmp(const struct crypto_bignum *a,
-        const struct crypto_bignum *b);
-
-/**
- * crypto_bignum_bits - Get size of a bignum in bits
- * @a: Bignum
- * Returns: Number of bits in the bignum
- */
-int crypto_bignum_bits(const struct crypto_bignum *a);
-
-/**
- * crypto_bignum_is_zero - Is the given bignum zero
- * @a: Bignum
- * Returns: 1 if @a is zero or 0 if not
- */
-int crypto_bignum_is_zero(const struct crypto_bignum *a);
-
-/**
- * crypto_bignum_is_one - Is the given bignum one
- * @a: Bignum
- * Returns: 1 if @a is one or 0 if not
- */
-int crypto_bignum_is_one(const struct crypto_bignum *a);
-
-/**
- * crypto_bignum_legendre - Compute the Legendre symbol (a/p)
- * @a: Bignum
- * @p: Bignum
- * Returns: Legendre symbol -1,0,1 on success; -2 on calculation failure
- */
-int crypto_bignum_legendre(const struct crypto_bignum *a,
-        const struct crypto_bignum *p);
-
-
-/**
- * struct crypto_ec - Elliptic curve context
- *
- * Internal data structure for EC implementation. The contents is specific
- * to the used crypto library.
- */
-struct crypto_ec;
-
-/**
- * crypto_ec_init - Initialize elliptic curve context
- * @group: Identifying number for the ECC group (IANA "Group Description"
- *  attribute registrty for RFC 2409)
- * Returns: Pointer to EC context or %NULL on failure
- */
-struct crypto_ec * crypto_ec_init(int group);
-
-/**
- * crypto_ec_deinit - Deinitialize elliptic curve context
- * @e: EC context from crypto_ec_init()
- */
-void crypto_ec_deinit(struct crypto_ec *e);
-
-/**
- * crypto_ec_prime_len - Get length of the prime in octets
- * @e: EC context from crypto_ec_init()
- * Returns: Length of the prime defining the group
- */
-size_t crypto_ec_prime_len(struct crypto_ec *e);
-
-/**
- * crypto_ec_prime_len_bits - Get length of the prime in bits
- * @e: EC context from crypto_ec_init()
- * Returns: Length of the prime defining the group in bits
- */
-size_t crypto_ec_prime_len_bits(struct crypto_ec *e);
-
-/**
- * crypto_ec_get_prime - Get prime defining an EC group
- * @e: EC context from crypto_ec_init()
- * Returns: Prime (bignum) defining the group
- */
-const struct crypto_bignum * crypto_ec_get_prime(struct crypto_ec *e);
-
-/**
- * crypto_ec_get_order - Get order of an EC group
- * @e: EC context from crypto_ec_init()
- * Returns: Order (bignum) of the group
- */
-const struct crypto_bignum * crypto_ec_get_order(struct crypto_ec *e);
-
-/**
- * struct crypto_ec_point - Elliptic curve point
- *
- * Internal data structure for EC implementation to represent a point. The
- * contents is specific to the used crypto library.
- */
-struct crypto_ec_point;
-
-/**
- * crypto_ec_point_init - Initialize data for an EC point
- * @e: EC context from crypto_ec_init()
- * Returns: Pointer to EC point data or %NULL on failure
- */
-struct crypto_ec_point * crypto_ec_point_init(struct crypto_ec *e);
-
-/**
- * crypto_ec_point_deinit - Deinitialize EC point data
- * @p: EC point data from crypto_ec_point_init()
- * @clear: Whether to clear the EC point value from memory
- */
-void crypto_ec_point_deinit(struct crypto_ec_point *p, int clear);
-
-/**
- * crypto_ec_point_to_bin - Write EC point value as binary data
- * @e: EC context from crypto_ec_init()
- * @p: EC point data from crypto_ec_point_init()
- * @x: Buffer for writing the binary data for x coordinate or %NULL if not used
- * @y: Buffer for writing the binary data for y coordinate or %NULL if not used
- * Returns: 0 on success, -1 on failure
- *
- * This function can be used to write an EC point as binary data in a format
- * that has the x and y coordinates in big endian byte order fields padded to
- * the length of the prime defining the group.
- */
-int crypto_ec_point_to_bin(struct crypto_ec *e,
-        const struct crypto_ec_point *point, u8 *x, u8 *y);
-
-/**
- * crypto_ec_point_from_bin - Create EC point from binary data
- * @e: EC context from crypto_ec_init()
- * @val: Binary data to read the EC point from
- * Returns: Pointer to EC point data or %NULL on failure
- *
- * This function readers x and y coordinates of the EC point from the provided
- * buffer assuming the values are in big endian byte order with fields padded to
- * the length of the prime defining the group.
- */
-struct crypto_ec_point * crypto_ec_point_from_bin(struct crypto_ec *e,
-        const u8 *val);
-
-/**
- * crypto_bignum_add - c = a + b
- * @e: EC context from crypto_ec_init()
- * @a: Bignum
- * @b: Bignum
- * @c: Bignum; used to store the result of a + b
- * Returns: 0 on success, -1 on failure
- */
-int crypto_ec_point_add(struct crypto_ec *e, const struct crypto_ec_point *a,
-        const struct crypto_ec_point *b,
-        struct crypto_ec_point *c);
-
-/**
- * crypto_bignum_mul - res = b * p
- * @e: EC context from crypto_ec_init()
- * @p: EC point
- * @b: Bignum
- * @res: EC point; used to store the result of b * p
- * Returns: 0 on success, -1 on failure
- */
-int crypto_ec_point_mul(struct crypto_ec *e, const struct crypto_ec_point *p,
-        const struct crypto_bignum *b,
-        struct crypto_ec_point *res);
-
-/**
- * crypto_ec_point_invert - Compute inverse of an EC point
- * @e: EC context from crypto_ec_init()
- * @p: EC point to invert (and result of the operation)
- * Returns: 0 on success, -1 on failure
- */
-int crypto_ec_point_invert(struct crypto_ec *e, struct crypto_ec_point *p);
-
-/**
- * crypto_ec_point_solve_y_coord - Solve y coordinate for an x coordinate
- * @e: EC context from crypto_ec_init()
- * @p: EC point to use for the returning the result
- * @x: x coordinate
- * @y_bit: y-bit (0 or 1) for selecting the y value to use
- * Returns: 0 on success, -1 on failure
- */
-int crypto_ec_point_solve_y_coord(struct crypto_ec *e,
-        struct crypto_ec_point *p,
-        const struct crypto_bignum *x, int y_bit);
-
-/**
- * crypto_ec_point_compute_y_sqr - Compute y^2 = x^3 + ax + b
- * @e: EC context from crypto_ec_init()
- * @x: x coordinate
- * Returns: y^2 on success, %NULL failure
- */
-struct crypto_bignum *
-crypto_ec_point_compute_y_sqr(struct crypto_ec *e,
-        const struct crypto_bignum *x);
-
-/**
- * crypto_ec_point_is_at_infinity - Check whether EC point is neutral element
- * @e: EC context from crypto_ec_init()
- * @p: EC point
- * Returns: 1 if the specified EC point is the neutral element of the group or
- *   0 if not
- */
-int crypto_ec_point_is_at_infinity(struct crypto_ec *e,
-        const struct crypto_ec_point *p);
-
-/**
- * crypto_ec_point_is_on_curve - Check whether EC point is on curve
- * @e: EC context from crypto_ec_init()
- * @p: EC point
- * Returns: 1 if the specified EC point is on the curve or 0 if not
- */
-int crypto_ec_point_is_on_curve(struct crypto_ec *e,
-        const struct crypto_ec_point *p);
-
-/**
- * crypto_ec_point_cmp - Compare two EC points
- * @e: EC context from crypto_ec_init()
- * @a: EC point
- * @b: EC point
- * Returns: 0 on equal, non-zero otherwise
- */
-int crypto_ec_point_cmp(const struct crypto_ec *e,
-        const struct crypto_ec_point *a,
-        const struct crypto_ec_point *b);
-
-
-#endif /* CRYPTO_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/dh_group5.h b/tools/sdk/include/wpa_supplicant/crypto/dh_group5.h
deleted file mode 100644
index f92c1115d5e..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/dh_group5.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Diffie-Hellman group 5 operations
- * Copyright (c) 2009, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef DH_GROUP5_H
-#define DH_GROUP5_H
-
-#include "wpa/wpabuf.h"
-
-void * dh5_init(struct wpabuf **priv, struct wpabuf **publ);
-struct wpabuf * dh5_derive_shared(void *ctx, const struct wpabuf *peer_public,
-				  const struct wpabuf *own_private);
-void dh5_free(void *ctx);
-
-#endif /* DH_GROUP5_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/dh_groups.h b/tools/sdk/include/wpa_supplicant/crypto/dh_groups.h
deleted file mode 100644
index 5c61539b700..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/dh_groups.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Diffie-Hellman groups
- * Copyright (c) 2007, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef DH_GROUPS_H
-#define DH_GROUPS_H
-
-struct dh_group {
-	int id;
-	const u8 *generator;
-	size_t generator_len;
-	const u8 *prime;
-	size_t prime_len;
-};
-
-const struct dh_group * dh_groups_get(int id);
-struct wpabuf * dh_init(const struct dh_group *dh, struct wpabuf **priv);
-struct wpabuf * dh_derive_shared(const struct wpabuf *peer_public,
-				 const struct wpabuf *own_private,
-				 const struct dh_group *dh);
-
-#endif /* DH_GROUPS_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/includes.h b/tools/sdk/include/wpa_supplicant/crypto/includes.h
deleted file mode 100644
index dbc65759b0d..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/includes.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * wpa_supplicant/hostapd - Default include files
- * Copyright (c) 2005-2006, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- *
- * This header file is included into all C files so that commonly used header
- * files can be selected with OS specific ifdef blocks in one place instead of
- * having to have OS/C library specific selection in many files.
- */
-
-#ifndef INCLUDES_H
-#define INCLUDES_H
-
-/* Include possible build time configuration before including anything else */
-//#include "build_config.h"  //don't need anymore
-#ifndef __ets__
-#include <stdlib.h>
-#include <stdio.h>
-#include <stdarg.h>
-#include <string.h>
-#ifndef _WIN32_WCE
-#ifndef CONFIG_TI_COMPILER
-#include <signal.h>
-#include <sys/types.h>
-#endif /* CONFIG_TI_COMPILER */
-#include <errno.h>
-#endif /* _WIN32_WCE */
-#include <ctype.h>
-#include <time.h>
-
-#ifndef CONFIG_TI_COMPILER
-#ifndef _MSC_VER
-#include <unistd.h>
-#endif /* _MSC_VER */
-#endif /* CONFIG_TI_COMPILER */
-
-#ifndef CONFIG_NATIVE_WINDOWS
-#ifndef CONFIG_TI_COMPILER
-//#include <sys/socket.h>
-//#include <netinet/in.h>
-//#include <arpa/inet.h>
-#ifndef __vxworks
-#ifndef __SYMBIAN32__
-//#include <sys/uio.h>
-#endif /* __SYMBIAN32__ */
-#include <sys/time.h>
-#endif /* __vxworks */
-#endif /* CONFIG_TI_COMPILER */
-#endif /* CONFIG_NATIVE_WINDOWS */
-
-#else
-
-#include "rom/ets_sys.h"
-
-#endif /* !__ets__ */
-
-#endif /* INCLUDES_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/md5.h b/tools/sdk/include/wpa_supplicant/crypto/md5.h
deleted file mode 100644
index 6de3a5b5f1b..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/md5.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * MD5 hash implementation and interface functions
- * Copyright (c) 2003-2009, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef MD5_H
-#define MD5_H
-
-#define MD5_MAC_LEN 16
-
-int hmac_md5_vector(const uint8_t *key, size_t key_len, size_t num_elem,
-		    const uint8_t *addr[], const size_t *len, uint8_t *mac);
-int hmac_md5(const uint8_t *key, size_t key_len, const uint8_t *data, size_t data_len,
-	     uint8_t *mac);
-#ifdef CONFIG_FIPS
-int hmac_md5_vector_non_fips_allow(const uint8_t *key, size_t key_len,
-				   size_t num_elem, const uint8_t *addr[],
-				   const size_t *len, uint8_t *mac);
-int hmac_md5_non_fips_allow(const uint8_t *key, size_t key_len, const uint8_t *data,
-			    size_t data_len, uint8_t *mac);
-#else /* CONFIG_FIPS */
-#define hmac_md5_vector_non_fips_allow hmac_md5_vector
-#define hmac_md5_non_fips_allow hmac_md5
-#endif /* CONFIG_FIPS */
-
-#endif /* MD5_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/md5_i.h b/tools/sdk/include/wpa_supplicant/crypto/md5_i.h
deleted file mode 100644
index b7f6596052a..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/md5_i.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * MD5 internal definitions
- * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef MD5_I_H
-#define MD5_I_H
-
-struct MD5Context {
-	u32 buf[4];
-	u32 bits[2];
-	u8 in[64];
-};
-
-void MD5Init(struct MD5Context *context);
-void MD5Update(struct MD5Context *context, unsigned char const *buf,
-	       unsigned len);
-void MD5Final(unsigned char digest[16], struct MD5Context *context);
-
-#endif /* MD5_I_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/ms_funcs.h b/tools/sdk/include/wpa_supplicant/crypto/ms_funcs.h
deleted file mode 100644
index dadb7d93215..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/ms_funcs.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * WPA Supplicant / shared MSCHAPV2 helper functions
- *
- *
- */
-
-#ifndef MS_FUNCS_H
-#define MS_FUNCS_H
-
-int generate_nt_response(const u8 *auth_challenge, const u8 *peer_challenge,
-			 const u8 *username, size_t username_len,
-			 const u8 *password, size_t password_len,
-			 u8 *response);
-
-int generate_nt_response_pwhash(const u8 *auth_challenge,
-				const u8 *peer_challenge,
-				const u8 *username, size_t username_len,
-				const u8 *password_hash,
-				u8 *response);
-int generate_authenticator_response(const u8 *password, size_t password_len,
-				    const u8 *peer_challenge,
-				    const u8 *auth_challenge,
-				    const u8 *username, size_t username_len,
-				    const u8 *nt_response, u8 *response);
-int generate_authenticator_response_pwhash(
-	const u8 *password_hash,
-	const u8 *peer_challenge, const u8 *auth_challenge,
-	const u8 *username, size_t username_len,
-	const u8 *nt_response, u8 *response);
-int nt_challenge_response(const u8 *challenge, const u8 *password,
-			  size_t password_len, u8 *response);
-
-void challenge_response(const u8 *challenge, const u8 *password_hash,
-			u8 *response);
-int nt_password_hash(const u8 *password, size_t password_len,
-		     u8 *password_hash);
-int hash_nt_password_hash(const u8 *password_hash, u8 *password_hash_hash);
-int get_master_key(const u8 *password_hash_hash, const u8 *nt_response,
-		   u8 *master_key);
-int get_asymetric_start_key(const u8 *master_key, u8 *session_key,
-			    size_t session_key_len, int is_send,
-			    int is_server);
-int encrypt_pw_block_with_password_hash(
-	const u8 *password, size_t password_len,
-	const u8 *password_hash, u8 *pw_block);
-int __must_check encry_pw_block_with_password_hash(
-	const u8 *password, size_t password_len,
-	const u8 *password_hash, u8 *pw_block);
-int __must_check new_password_encrypted_with_old_nt_password_hash(
-	const u8 *new_password, size_t new_password_len,
-	const u8 *old_password, size_t old_password_len,
-	u8 *encrypted_pw_block);
-void nt_password_hash_encrypted_with_block(const u8 *password_hash,
-					   const u8 *block, u8 *cypher);
-int old_nt_password_hash_encrypted_with_new_nt_password_hash(
-	const u8 *new_password, size_t new_password_len,
-	const u8 *old_password, size_t old_password_len,
-	u8 *encrypted_password_hash);
-
-#endif /* MS_FUNCS_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/random.h b/tools/sdk/include/wpa_supplicant/crypto/random.h
deleted file mode 100644
index cbfa8773fdb..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/random.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Random number generator
- * Copyright (c) 2010-2011, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef RANDOM_H
-#define RANDOM_H
-
-#define CONFIG_NO_RANDOM_POOL
-
-#ifdef CONFIG_NO_RANDOM_POOL
-#define random_init(e) do { } while (0)
-#define random_deinit() do { } while (0)
-#define random_add_randomness(b, l) do { } while (0)
-#define random_get_bytes(b, l) os_get_random((b), (l))
-#define random_pool_ready() 1
-#define random_mark_pool_ready() do { } while (0)
-#else /* CONFIG_NO_RANDOM_POOL */
-void random_init(const char *entropy_file);
-void random_deinit(void);
-void random_add_randomness(const void *buf, size_t len);
-int random_get_bytes(void *buf, size_t len);
-#endif /* CONFIG_NO_RANDOM_POOL */
-
-#endif /* RANDOM_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/sha1.h b/tools/sdk/include/wpa_supplicant/crypto/sha1.h
deleted file mode 100644
index 65e3958fc68..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/sha1.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * SHA1 hash implementation and interface functions
- * Copyright (c) 2003-2009, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef SHA1_H
-#define SHA1_H
-
-#define SHA1_MAC_LEN 20
-
-int hmac_sha1_vector(const uint8_t *key, size_t key_len, size_t num_elem,
-		     const uint8_t *addr[], const size_t *len, uint8_t *mac);
-int hmac_sha1(const uint8_t *key, size_t key_len, const uint8_t *data, size_t data_len,
-	       uint8_t *mac);
-int sha1_prf(const uint8_t *key, size_t key_len, const char *label,
-	     const uint8_t *data, size_t data_len, uint8_t *buf, size_t buf_len);
-int sha1_t_prf(const uint8_t *key, size_t key_len, const char *label,
-	       const uint8_t *seed, size_t seed_len, uint8_t *buf, size_t buf_len);
-//int __must_check tls_prf(const uint8_t *secret, size_t secret_len,
-//			 const char *label, const uint8_t *seed, size_t seed_len,
-//			 uint8_t *out, size_t outlen);
-int pbkdf2_sha1(const char *passphrase, const char *ssid, size_t ssid_len,
-		int iterations, uint8_t *buf, size_t buflen);
-#endif /* SHA1_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/sha1_i.h b/tools/sdk/include/wpa_supplicant/crypto/sha1_i.h
deleted file mode 100644
index ec2f82f75b9..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/sha1_i.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * SHA1 internal definitions
- * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef SHA1_I_H
-#define SHA1_I_H
-
-struct SHA1Context {
-	u32 state[5];
-	u32 count[2];
-	unsigned char buffer[64];
-};
-
-void SHA1Init(struct SHA1Context *context);
-void SHA1Update(struct SHA1Context *context, const void *data, u32 len);
-void SHA1Final(unsigned char digest[20], struct SHA1Context *context);
-void SHA1Transform(u32 state[5], const unsigned char buffer[64]);
-
-#endif /* SHA1_I_H */
diff --git a/tools/sdk/include/wpa_supplicant/crypto/sha256.h b/tools/sdk/include/wpa_supplicant/crypto/sha256.h
deleted file mode 100644
index 8025a29de37..00000000000
--- a/tools/sdk/include/wpa_supplicant/crypto/sha256.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * SHA256 hash implementation and interface functions
- * Copyright (c) 2003-2006, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef SHA256_H
-#define SHA256_H
-
-#define SHA256_MAC_LEN 32
-
-void hmac_sha256_vector(const u8 *key, size_t key_len, size_t num_elem,
-		      const u8 *addr[], const size_t *len, u8 *mac);
-void hmac_sha256(const u8 *key, size_t key_len, const u8 *data,
-		 size_t data_len, u8 *mac);
-void sha256_prf(const u8 *key, size_t key_len, const char *label,
-	      const u8 *data, size_t data_len, u8 *buf, size_t buf_len);
-
-void fast_hmac_sha256_vector(const uint8_t *key, size_t key_len, size_t num_elem,
-		             const uint8_t *addr[], const size_t *len, uint8_t *mac);
-void fast_hmac_sha256(const uint8_t *key, size_t key_len, const uint8_t *data,
-		      size_t data_len, uint8_t *mac);
-void fast_sha256_prf(const uint8_t *key, size_t key_len, const char *label,
-	             const uint8_t *data, size_t data_len, uint8_t *buf, size_t buf_len);
-#endif /* SHA256_H */
diff --git a/tools/sdk/include/wpa_supplicant/endian.h b/tools/sdk/include/wpa_supplicant/endian.h
deleted file mode 100644
index 1e2453f1645..00000000000
--- a/tools/sdk/include/wpa_supplicant/endian.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*-
- * Copyright (c) 2002 Thomas Moestl <tmm@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _ENDIAN_H_
-#define _ENDIAN_H_
-
-#include <stdint.h>
-#include "byteswap.h"
-
-#ifndef BIG_ENDIAN
-#define BIG_ENDIAN 4321
-#endif
-#ifndef LITTLE_ENDIAN
-#define LITTLE_ENDIAN 1234
-#endif
-
-#ifndef BYTE_ORDER
-#ifdef __IEEE_LITTLE_ENDIAN
-#define BYTE_ORDER LITTLE_ENDIAN
-#else
-#define BYTE_ORDER BIG_ENDIAN
-#endif
-#endif
-
-#define _UINT8_T_DECLARED
-#ifndef _UINT8_T_DECLARED
-typedef	__uint8_t	uint8_t;
-#define	_UINT8_T_DECLARED
-#endif
-
-#define _UINT16_T_DECLARED
-#ifndef _UINT16_T_DECLARED
-typedef	__uint16_t	uint16_t;
-#define	_UINT16_T_DECLARED
-#endif
- 
-#define _UINT32_T_DECLARED
-#ifndef _UINT32_T_DECLARED
-typedef	__uint32_t	uint32_t;
-#define	_UINT32_T_DECLARED
-#endif
- 
-#define _UINT64_T_DECLARED
-#ifndef _UINT64_T_DECLARED
-typedef	__uint64_t	uint64_t;
-#define	_UINT64_T_DECLARED
-#endif
- 
-/*
- * General byte order swapping functions.
- */
-#define	bswap16(x)	__bswap16(x)
-#define	bswap32(x)	__bswap32(x)
-#define	bswap64(x)	__bswap64(x)
-
-/*
- * Host to big endian, host to little endian, big endian to host, and little
- * endian to host byte order functions as detailed in byteorder(9).
- */
-#if 1 //BYTE_ORDER == _LITTLE_ENDIAN
-#define __bswap16     __bswap_16
-#define __bswap32     __bswap_32
-#define	htobe16(x)	bswap16((x))
-#define	htobe32(x)	bswap32((x))
-#define	htobe64(x)	bswap64((x))
-#define	htole16(x)	((uint16_t)(x))
-#define	htole32(x)	((uint32_t)(x))
-#define	htole64(x)	((uint64_t)(x))
-
-#define	be16toh(x)	bswap16((x))
-#define	be32toh(x)	bswap32((x))
-#define	be64toh(x)	bswap64((x))
-#define	le16toh(x)	((uint16_t)(x))
-#define	le32toh(x)	((uint32_t)(x))
-#define	le64toh(x)	((uint64_t)(x))
-
-#ifndef htons
-#define htons htobe16
-#endif //htons
-
-#else /* _BYTE_ORDER != _LITTLE_ENDIAN */
-#define	htobe16(x)	((uint16_t)(x))
-#define	htobe32(x)	((uint32_t)(x))
-#define	htobe64(x)	((uint64_t)(x))
-#define	htole16(x)	bswap16((x))
-#define	htole32(x)	bswap32((x))
-#define	htole64(x)	bswap64((x))
-
-#define	be16toh(x)	((uint16_t)(x))
-#define	be32toh(x)	((uint32_t)(x))
-#define	be64toh(x)	((uint64_t)(x))
-#define	le16toh(x)	bswap16((x))
-#define	le32toh(x)	bswap32((x))
-#define	le64toh(x)	bswap64((x))
-#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */
-
-/* Alignment-agnostic encode/decode bytestream to/from little/big endian. */
-#define INLINE                  __inline__
-
-static INLINE uint16_t
-be16dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return ((p[0] << 8) | p[1]);
-}
-
-static INLINE uint32_t
-be32dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (((unsigned)p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]);
-}
-
-static INLINE uint64_t
-be64dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (((uint64_t)be32dec(p) << 32) | be32dec(p + 4));
-}
-
-static INLINE uint16_t
-le16dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return ((p[1] << 8) | p[0]);
-}
-
-static INLINE uint32_t
-le32dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (((unsigned)p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
-}
-
-static INLINE uint64_t
-le64dec(const void *pp)
-{
-	uint8_t const *p = (uint8_t const *)pp;
-
-	return (((uint64_t)le32dec(p + 4) << 32) | le32dec(p));
-}
-
-static INLINE void
-be16enc(void *pp, uint16_t u)
-{
-	uint8_t *p = (uint8_t *)pp;
-
-	p[0] = (u >> 8) & 0xff;
-	p[1] = u & 0xff;
-}
-
-static INLINE void
-be32enc(void *pp, uint32_t u)
-{
-	uint8_t *p = (uint8_t *)pp;
-
-	p[0] = (u >> 24) & 0xff;
-	p[1] = (u >> 16) & 0xff;
-	p[2] = (u >> 8) & 0xff;
-	p[3] = u & 0xff;
-}
-
-static INLINE void
-be64enc(void *pp, uint64_t u)
-{
-	uint8_t *p = (uint8_t *)pp;
-
-	be32enc(p, (uint32_t)(u >> 32));
-	be32enc(p + 4, (uint32_t)(u & 0xffffffffU));
-}
-
-static INLINE void
-le16enc(void *pp, uint16_t u)
-{
-	uint8_t *p = (uint8_t *)pp;
-
-	p[0] = u & 0xff;
-	p[1] = (u >> 8) & 0xff;
-}
-
-static INLINE void
-le32enc(void *pp, uint32_t u)
-{
-	uint8_t *p = (uint8_t *)pp;
-
-	p[0] = u & 0xff;
-	p[1] = (u >> 8) & 0xff;
-	p[2] = (u >> 16) & 0xff;
-	p[3] = (u >> 24) & 0xff;
-}
-
-static INLINE void
-le64enc(void *pp, uint64_t u)
-{
-	uint8_t *p = (uint8_t *)pp;
-
-	le32enc(p, (uint32_t)(u & 0xffffffffU));
-	le32enc(p + 4, (uint32_t)(u >> 32));
-}
-
-#endif	/* _ENDIAN_H_ */
diff --git a/tools/sdk/include/wpa_supplicant/os.h b/tools/sdk/include/wpa_supplicant/os.h
deleted file mode 100644
index 0028c21e9cb..00000000000
--- a/tools/sdk/include/wpa_supplicant/os.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * OS specific functions
- * Copyright (c) 2005-2009, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef OS_H
-#define OS_H
-#include "esp_types.h"
-#include <string.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include "esp_err.h"
-#include "rom/ets_sys.h"
-
-typedef long os_time_t;
-
-/**
- * os_sleep - Sleep (sec, usec)
- * @sec: Number of seconds to sleep
- * @usec: Number of microseconds to sleep
- */
-void os_sleep(os_time_t sec, os_time_t usec);
-
-struct os_time {
-	os_time_t sec;
-	os_time_t usec;
-};
-
-/**
- * os_get_time - Get current time (sec, usec)
- * @t: Pointer to buffer for the time
- * Returns: 0 on success, -1 on failure
- */
-int os_get_time(struct os_time *t);
-
-
-/* Helper macros for handling struct os_time */
-
-#define os_time_before(a, b) \
-	((a)->sec < (b)->sec || \
-	 ((a)->sec == (b)->sec && (a)->usec < (b)->usec))
-
-#define os_time_sub(a, b, res) do { \
-	(res)->sec = (a)->sec - (b)->sec; \
-	(res)->usec = (a)->usec - (b)->usec; \
-	if ((res)->usec < 0) { \
-		(res)->sec--; \
-		(res)->usec += 1000000; \
-	} \
-} while (0)
-
-/**
- * os_mktime - Convert broken-down time into seconds since 1970-01-01
- * @year: Four digit year
- * @month: Month (1 .. 12)
- * @day: Day of month (1 .. 31)
- * @hour: Hour (0 .. 23)
- * @min: Minute (0 .. 59)
- * @sec: Second (0 .. 60)
- * @t: Buffer for returning calendar time representation (seconds since
- * 1970-01-01 00:00:00)
- * Returns: 0 on success, -1 on failure
- *
- * Note: The result is in seconds from Epoch, i.e., in UTC, not in local time
- * which is used by POSIX mktime().
- */
-int os_mktime(int year, int month, int day, int hour, int min, int sec,
-	      os_time_t *t);
-
-
-/**
- * os_daemonize - Run in the background (detach from the controlling terminal)
- * @pid_file: File name to write the process ID to or %NULL to skip this
- * Returns: 0 on success, -1 on failure
- */
-int os_daemonize(const char *pid_file);
-
-/**
- * os_daemonize_terminate - Stop running in the background (remove pid file)
- * @pid_file: File name to write the process ID to or %NULL to skip this
- */
-void os_daemonize_terminate(const char *pid_file);
-
-/**
- * os_get_random - Get cryptographically strong pseudo random data
- * @buf: Buffer for pseudo random data
- * @len: Length of the buffer
- * Returns: 0 on success, -1 on failure
- */
-int os_get_random(unsigned char *buf, size_t len);
-
-/**
- * os_random - Get pseudo random value (not necessarily very strong)
- * Returns: Pseudo random value
- */
-unsigned long os_random(void);
-
-/**
- * os_rel2abs_path - Get an absolute path for a file
- * @rel_path: Relative path to a file
- * Returns: Absolute path for the file or %NULL on failure
- *
- * This function tries to convert a relative path of a file to an absolute path
- * in order for the file to be found even if current working directory has
- * changed. The returned value is allocated and caller is responsible for
- * freeing it. It is acceptable to just return the same path in an allocated
- * buffer, e.g., return strdup(rel_path). This function is only used to find
- * configuration files when os_daemonize() may have changed the current working
- * directory and relative path would be pointing to a different location.
- */
-char * os_rel2abs_path(const char *rel_path);
-
-/**
- * os_program_init - Program initialization (called at start)
- * Returns: 0 on success, -1 on failure
- *
- * This function is called when a programs starts. If there are any OS specific
- * processing that is needed, it can be placed here. It is also acceptable to
- * just return 0 if not special processing is needed.
- */
-int os_program_init(void);
-
-/**
- * os_program_deinit - Program deinitialization (called just before exit)
- *
- * This function is called just before a program exists. If there are any OS
- * specific processing, e.g., freeing resourced allocated in os_program_init(),
- * it should be done here. It is also acceptable for this function to do
- * nothing.
- */
-void os_program_deinit(void);
-
-/**
- * os_setenv - Set environment variable
- * @name: Name of the variable
- * @value: Value to set to the variable
- * @overwrite: Whether existing variable should be overwritten
- * Returns: 0 on success, -1 on error
- *
- * This function is only used for wpa_cli action scripts. OS wrapper does not
- * need to implement this if such functionality is not needed.
- */
-int os_setenv(const char *name, const char *value, int overwrite);
-
-/**
- * os_unsetenv - Delete environent variable
- * @name: Name of the variable
- * Returns: 0 on success, -1 on error
- *
- * This function is only used for wpa_cli action scripts. OS wrapper does not
- * need to implement this if such functionality is not needed.
- */
-int os_unsetenv(const char *name);
-
-/**
- * os_readfile - Read a file to an allocated memory buffer
- * @name: Name of the file to read
- * @len: For returning the length of the allocated buffer
- * Returns: Pointer to the allocated buffer or %NULL on failure
- *
- * This function allocates memory and reads the given file to this buffer. Both
- * binary and text files can be read with this function. The caller is
- * responsible for freeing the returned buffer with os_free().
- */
-char * os_readfile(const char *name, size_t *len);
-
-/*
- * The following functions are wrapper for standard ANSI C or POSIX functions.
- * By default, they are just defined to use the standard function name and no
- * os_*.c implementation is needed for them. This avoids extra function calls
- * by allowing the C pre-processor take care of the function name mapping.
- *
- * If the target system uses a C library that does not provide these functions,
- * build_config.h can be used to define the wrappers to use a different
- * function name. This can be done on function-by-function basis since the
- * defines here are only used if build_config.h does not define the os_* name.
- * If needed, os_*.c file can be used to implement the functions that are not
- * included in the C library on the target system. Alternatively,
- * OS_NO_C_LIB_DEFINES can be defined to skip all defines here in which case
- * these functions need to be implemented in os_*.c file for the target system.
- */
- 
-#ifndef os_malloc
-#define os_malloc(s) malloc((s))
-#endif
-#ifndef os_realloc
-#define os_realloc(p, s) realloc((p), (s))
-#endif
-#ifndef os_zalloc
-#define os_zalloc(s) calloc(1, (s))
-#endif
-#ifndef os_free
-#define os_free(p) free((p))
-#endif
-
-#ifndef os_bzero
-#define os_bzero(s, n) bzero(s, n)
-#endif 
-
-
-#ifndef os_strdup
-#ifdef _MSC_VER
-#define os_strdup(s) _strdup(s)
-#else
-#define os_strdup(s) strdup(s)
-#endif
-#endif
-char * ets_strdup(const char *s);
-
-#ifndef os_memcpy
-#define os_memcpy(d, s, n) memcpy((d), (s), (n))
-#endif
-#ifndef os_memmove
-#define os_memmove(d, s, n) memmove((d), (s), (n))
-#endif
-#ifndef os_memset
-#define os_memset(s, c, n) memset(s, c, n)
-#endif
-#ifndef os_memcmp
-#define os_memcmp(s1, s2, n) memcmp((s1), (s2), (n))
-#endif
-
-#ifndef os_strlen
-#define os_strlen(s) strlen(s)
-#endif
-#ifndef os_strcasecmp
-#ifdef _MSC_VER
-#define os_strcasecmp(s1, s2) _stricmp((s1), (s2))
-#else
-#define os_strcasecmp(s1, s2) strcasecmp((s1), (s2))
-#endif
-#endif
-#ifndef os_strncasecmp
-#ifdef _MSC_VER
-#define os_strncasecmp(s1, s2, n) _strnicmp((s1), (s2), (n))
-#else
-#define os_strncasecmp(s1, s2, n) strncasecmp((s1), (s2), (n))
-#endif
-#endif
-#ifndef os_strchr
-#define os_strchr(s, c) strchr((s), (c))
-#endif
-#ifndef os_strcmp
-#define os_strcmp(s1, s2) strcmp((s1), (s2))
-#endif
-#ifndef os_strncmp
-#define os_strncmp(s1, s2, n) strncmp((s1), (s2), (n))
-#endif
-#ifndef os_strncpy
-#define os_strncpy(d, s, n) strncpy((d), (s), (n))
-#endif
-#ifndef os_strrchr
-//hard cold
-#define os_strrchr(s, c)  NULL
-#endif
-#ifndef os_strstr
-#define os_strstr(h, n) strstr((h), (n))
-#endif
-
-#ifndef os_snprintf
-#ifdef _MSC_VER
-#define os_snprintf _snprintf
-#else
-#define os_snprintf snprintf
-#endif
-#endif
-
-/**
- * os_strlcpy - Copy a string with size bound and NUL-termination
- * @dest: Destination
- * @src: Source
- * @siz: Size of the target buffer
- * Returns: Total length of the target string (length of src) (not including
- * NUL-termination)
- *
- * This function matches in behavior with the strlcpy(3) function in OpenBSD.
- */
-size_t os_strlcpy(char *dest, const char *src, size_t siz);
-
-
-
-#endif /* OS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/ap_config.h b/tools/sdk/include/wpa_supplicant/wpa/ap_config.h
deleted file mode 100644
index 761becb4844..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/ap_config.h
+++ /dev/null
@@ -1,544 +0,0 @@
-/*
- * hostapd / Configuration definitions and helpers functions
- * Copyright (c) 2003-2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef HOSTAPD_CONFIG_H
-#define HOSTAPD_CONFIG_H
-
-#include "wpa/defs.h"
-//#include "ip_addr.h"
-#include "wpa/wpa_common.h"
-//#include "common/ieee802_11_common.h"
-//#include "wps/wps.h"
-
-#define MAX_STA_COUNT 4
-#define MAX_VLAN_ID 4094
-
-typedef u8 macaddr[ETH_ALEN];
-
-struct mac_acl_entry {
-	macaddr addr;
-	int vlan_id;
-};
-
-struct hostapd_radius_servers;
-struct ft_remote_r0kh;
-struct ft_remote_r1kh;
-
-#define HOSTAPD_MAX_SSID_LEN 32
-
-#define NUM_WEP_KEYS 4
-struct hostapd_wep_keys {
-	u8 idx;
-	u8 *key[NUM_WEP_KEYS];
-	size_t len[NUM_WEP_KEYS];
-	int keys_set;
-	size_t default_len; /* key length used for dynamic key generation */
-};
-
-typedef enum hostap_security_policy {
-	SECURITY_PLAINTEXT = 0,
-	SECURITY_STATIC_WEP = 1,
-	SECURITY_IEEE_802_1X = 2,
-	SECURITY_WPA_PSK = 3,
-	SECURITY_WPA = 4
-} secpolicy;
-
-struct hostapd_ssid {
-	u8 ssid[HOSTAPD_MAX_SSID_LEN];
-	size_t ssid_len;
-	unsigned int ssid_set:1;
-	unsigned int utf8_ssid:1;
-
-//	char vlan[IFNAMSIZ + 1];
-//	secpolicy security_policy;
-
-	struct hostapd_wpa_psk *wpa_psk;
-	char *wpa_passphrase;
-//	char *wpa_psk_file;
-
-	struct hostapd_wep_keys wep;
-
-#if 0
-#define DYNAMIC_VLAN_DISABLED 0
-#define DYNAMIC_VLAN_OPTIONAL 1
-#define DYNAMIC_VLAN_REQUIRED 2
-	int dynamic_vlan;
-#define DYNAMIC_VLAN_NAMING_WITHOUT_DEVICE 0
-#define DYNAMIC_VLAN_NAMING_WITH_DEVICE 1
-#define DYNAMIC_VLAN_NAMING_END 2
-	int vlan_naming;
-#ifdef CONFIG_FULL_DYNAMIC_VLAN
-	char *vlan_tagged_interface;
-#endif /* CONFIG_FULL_DYNAMIC_VLAN */
-	struct hostapd_wep_keys **dyn_vlan_keys;
-	size_t max_dyn_vlan_keys;
-#endif
-};
-
-#if 0
-#define VLAN_ID_WILDCARD -1
-
-struct hostapd_vlan {
-	struct hostapd_vlan *next;
-	int vlan_id; /* VLAN ID or -1 (VLAN_ID_WILDCARD) for wildcard entry */
-	char ifname[IFNAMSIZ + 1];
-	int dynamic_vlan;
-#ifdef CONFIG_FULL_DYNAMIC_VLAN
-
-#define DVLAN_CLEAN_BR 	0x1
-#define DVLAN_CLEAN_VLAN	0x2
-#define DVLAN_CLEAN_VLAN_PORT	0x4
-#define DVLAN_CLEAN_WLAN_PORT	0x8
-	int clean;
-#endif /* CONFIG_FULL_DYNAMIC_VLAN */
-};
-#endif
-
-#define PMK_LEN 32
-struct hostapd_sta_wpa_psk_short {
-	struct hostapd_sta_wpa_psk_short *next;
-	u8 psk[PMK_LEN];
-};
-
-struct hostapd_wpa_psk {
-	struct hostapd_wpa_psk *next;
-	int group;
-	u8 psk[PMK_LEN];
-	u8 addr[ETH_ALEN];
-};
-
-#if 0
-struct hostapd_eap_user {
-	struct hostapd_eap_user *next;
-	u8 *identity;
-	size_t identity_len;
-	struct {
-		int vendor;
-		u32 method;
-	} methods[EAP_MAX_METHODS];
-	u8 *password;
-	size_t password_len;
-	int phase2;
-	int force_version;
-	unsigned int wildcard_prefix:1;
-	unsigned int password_hash:1; /* whether password is hashed with
-				       * nt_password_hash() */
-	int ttls_auth; /* EAP_TTLS_AUTH_* bitfield */
-};
-
-struct hostapd_radius_attr {
-	u8 type;
-	struct wpabuf *val;
-	struct hostapd_radius_attr *next;
-};
-
-
-#define NUM_TX_QUEUES 4
-
-struct hostapd_tx_queue_params {
-	int aifs;
-	int cwmin;
-	int cwmax;
-	int burst; /* maximum burst time in 0.1 ms, i.e., 10 = 1 ms */
-};
-
-
-#define MAX_ROAMING_CONSORTIUM_LEN 15
-
-struct hostapd_roaming_consortium {
-	u8 len;
-	u8 oi[MAX_ROAMING_CONSORTIUM_LEN];
-};
-
-struct hostapd_lang_string {
-	u8 lang[3];
-	u8 name_len;
-	u8 name[252];
-};
-
-#define MAX_NAI_REALMS 10
-#define MAX_NAI_REALMLEN 255
-#define MAX_NAI_EAP_METHODS 5
-#define MAX_NAI_AUTH_TYPES 4
-struct hostapd_nai_realm_data {
-	u8 encoding;
-	char realm_buf[MAX_NAI_REALMLEN + 1];
-	char *realm[MAX_NAI_REALMS];
-	u8 eap_method_count;
-	struct hostapd_nai_realm_eap {
-		u8 eap_method;
-		u8 num_auths;
-		u8 auth_id[MAX_NAI_AUTH_TYPES];
-		u8 auth_val[MAX_NAI_AUTH_TYPES];
-	} eap_method[MAX_NAI_EAP_METHODS];
-};
-#endif
-
-/**
- * struct hostapd_bss_config - Per-BSS configuration
- */
-struct hostapd_bss_config {
-//	char iface[IFNAMSIZ + 1];
-//	char bridge[IFNAMSIZ + 1];
-//	char wds_bridge[IFNAMSIZ + 1];
-
-//	enum hostapd_logger_level logger_syslog_level, logger_stdout_level;
-
-//	unsigned int logger_syslog; /* module bitfield */
-//	unsigned int logger_stdout; /* module bitfield */
-
-//	char *dump_log_name; /* file name for state dump (SIGUSR1) */
-
-	int max_num_sta; /* maximum number of STAs in station table */
-
-	int dtim_period;
-
-	int ieee802_1x; /* use IEEE 802.1X */
-	int eapol_version;
-//	int eap_server; /* Use internal EAP server instead of external
-//			 * RADIUS server */
-//	struct hostapd_eap_user *eap_user;
-//	char *eap_user_sqlite;
-//	char *eap_sim_db;
-//	struct hostapd_ip_addr own_ip_addr;
-//	char *nas_identifier;
-//	struct hostapd_radius_servers *radius;
-//	int acct_interim_interval;
-//	int radius_request_cui;
-//	struct hostapd_radius_attr *radius_auth_req_attr;
-//	struct hostapd_radius_attr *radius_acct_req_attr;
-//	int radius_das_port;
-//	unsigned int radius_das_time_window;
-//	int radius_das_require_event_timestamp;
-//	struct hostapd_ip_addr radius_das_client_addr;
-//	u8 *radius_das_shared_secret;
-//	size_t radius_das_shared_secret_len;
-
-	struct hostapd_ssid ssid;
-
-//	char *eap_req_id_text; /* optional displayable message sent with
-//				* EAP Request-Identity */
-//	size_t eap_req_id_text_len;
-//	int eapol_key_index_workaround;
-
-//	size_t default_wep_key_len;
-//	int individual_wep_key_len;
-	int wep_rekeying_period;
-	int broadcast_key_idx_min, broadcast_key_idx_max;
-//	int eap_reauth_period;
-
-//	int ieee802_11f; /* use IEEE 802.11f (IAPP) */
-//	char iapp_iface[IFNAMSIZ + 1]; /* interface used with IAPP broadcast
-//					* frames */
-
-	enum {
-		ACCEPT_UNLESS_DENIED = 0,
-		DENY_UNLESS_ACCEPTED = 1,
-		USE_EXTERNAL_RADIUS_AUTH = 2
-	} macaddr_acl;
-//	struct mac_acl_entry *accept_mac;
-//	int num_accept_mac;
-//	struct mac_acl_entry *deny_mac;
-//	int num_deny_mac;
-//	int wds_sta;
-//	int isolate;
-
-	int auth_algs; /* bitfield of allowed IEEE 802.11 authentication
-			* algorithms, WPA_AUTH_ALG_{OPEN,SHARED,LEAP} */
-
-	int wpa; /* bitfield of WPA_PROTO_WPA, WPA_PROTO_RSN */
-	int wpa_key_mgmt;
-#ifdef CONFIG_IEEE80211W
-	enum mfp_options ieee80211w;
-	/* dot11AssociationSAQueryMaximumTimeout (in TUs) */
-	unsigned int assoc_sa_query_max_timeout;
-	/* dot11AssociationSAQueryRetryTimeout (in TUs) */
-	int assoc_sa_query_retry_timeout;
-#endif /* CONFIG_IEEE80211W */
-	enum {
-		PSK_RADIUS_IGNORED = 0,
-		PSK_RADIUS_ACCEPTED = 1,
-		PSK_RADIUS_REQUIRED = 2
-	} wpa_psk_radius;
-	int wpa_pairwise;
-	int wpa_group;
-	int wpa_group_rekey;
-	int wpa_strict_rekey;
-	int wpa_gmk_rekey;
-	int wpa_ptk_rekey;
-	int rsn_pairwise;
-	int rsn_preauth;
-	char *rsn_preauth_interfaces;
-	int peerkey;
-
-#ifdef CONFIG_IEEE80211R
-	/* IEEE 802.11r - Fast BSS Transition */
-	u8 mobility_domain[MOBILITY_DOMAIN_ID_LEN];
-	u8 r1_key_holder[FT_R1KH_ID_LEN];
-	u32 r0_key_lifetime;
-	u32 reassociation_deadline;
-	struct ft_remote_r0kh *r0kh_list;
-	struct ft_remote_r1kh *r1kh_list;
-	int pmk_r1_push;
-	int ft_over_ds;
-#endif /* CONFIG_IEEE80211R */
-
-//	char *ctrl_interface; /* directory for UNIX domain sockets */
-#ifndef CONFIG_NATIVE_WINDOWS
-//	gid_t ctrl_interface_gid;
-#endif /* CONFIG_NATIVE_WINDOWS */
-//	int ctrl_interface_gid_set;
-
-//	char *ca_cert;
-//	char *server_cert;
-//	char *private_key;
-//	char *private_key_passwd;
-//	int check_crl;
-//	char *dh_file;
-//	u8 *pac_opaque_encr_key;
-//	u8 *eap_fast_a_id;
-//	size_t eap_fast_a_id_len;
-//	char *eap_fast_a_id_info;
-//	int eap_fast_prov;
-//	int pac_key_lifetime;
-//	int pac_key_refresh_time;
-//	int eap_sim_aka_result_ind;
-//	int tnc;
-//	int fragment_size;
-//	u16 pwd_group;
-
-//	char *radius_server_clients;
-//	int radius_server_auth_port;
-//	int radius_server_ipv6;
-
-//	char *test_socket; /* UNIX domain socket path for driver_test */
-
-//	int use_pae_group_addr; /* Whether to send EAPOL frames to PAE group
-//				 * address instead of individual address
-//				 * (for driver_wired.c).
-//				 */
-
-	int ap_max_inactivity;
-	int ignore_broadcast_ssid;
-
-	int wmm_enabled;
-	int wmm_uapsd;
-
-//	struct hostapd_vlan *vlan, *vlan_tail;
-
-	macaddr bssid;
-
-	/*
-	 * Maximum listen interval that STAs can use when associating with this
-	 * BSS. If a STA tries to use larger value, the association will be
-	 * denied with status code 51.
-	 */
-	u16 max_listen_interval;
-
-//	int disable_pmksa_caching;
-//	int okc; /* Opportunistic Key Caching */
-
-//	int wps_state;
-#ifdef CONFIG_WPS
-	int ap_setup_locked;
-	u8 uuid[16];
-	char *wps_pin_requests;
-	char *device_name;
-	char *manufacturer;
-	char *model_name;
-	char *model_number;
-	char *serial_number;
-	u8 device_type[WPS_DEV_TYPE_LEN];
-	char *config_methods;
-	u8 os_version[4];
-	char *ap_pin;
-	int skip_cred_build;
-	u8 *extra_cred;
-	size_t extra_cred_len;
-	int wps_cred_processing;
-	u8 *ap_settings;
-	size_t ap_settings_len;
-	char *upnp_iface;
-	char *friendly_name;
-	char *manufacturer_url;
-	char *model_description;
-	char *model_url;
-	char *upc;
-	struct wpabuf *wps_vendor_ext[MAX_WPS_VENDOR_EXTENSIONS];
-	int wps_nfc_dev_pw_id;
-	struct wpabuf *wps_nfc_dh_pubkey;
-	struct wpabuf *wps_nfc_dh_privkey;
-	struct wpabuf *wps_nfc_dev_pw;
-#endif /* CONFIG_WPS */
-//	int pbc_in_m1;
-
-#define P2P_ENABLED BIT(0)
-#define P2P_GROUP_OWNER BIT(1)
-#define P2P_GROUP_FORMATION BIT(2)
-#define P2P_MANAGE BIT(3)
-#define P2P_ALLOW_CROSS_CONNECTION BIT(4)
-//	int p2p;
-
-//	int disassoc_low_ack;
-//	int skip_inactivity_poll;
-
-#define TDLS_PROHIBIT BIT(0)
-#define TDLS_PROHIBIT_CHAN_SWITCH BIT(1)
-//	int tdls;
-//	int disable_11n;
-//	int disable_11ac;
-
-	/* IEEE 802.11v */
-//	int time_advertisement;
-//	char *time_zone;
-//	int wnm_sleep_mode;
-//	int bss_transition;
-
-	/* IEEE 802.11u - Interworking */
-//	int interworking;
-//	int access_network_type;
-//	int internet;
-//	int asra;
-//	int esr;
-//	int uesa;
-//	int venue_info_set;
-//	u8 venue_group;
-//	u8 venue_type;
-//	u8 hessid[ETH_ALEN];
-
-	/* IEEE 802.11u - Roaming Consortium list */
-//	unsigned int roaming_consortium_count;
-//	struct hostapd_roaming_consortium *roaming_consortium;
-
-	/* IEEE 802.11u - Venue Name duples */
-//	unsigned int venue_name_count;
-//	struct hostapd_lang_string *venue_name;
-
-	/* IEEE 802.11u - Network Authentication Type */
-//	u8 *network_auth_type;
-//	size_t network_auth_type_len;
-
-	/* IEEE 802.11u - IP Address Type Availability */
-//	u8 ipaddr_type_availability;
-//	u8 ipaddr_type_configured;
-
-	/* IEEE 802.11u - 3GPP Cellular Network */
-//	u8 *anqp_3gpp_cell_net;
-//	size_t anqp_3gpp_cell_net_len;
-
-	/* IEEE 802.11u - Domain Name */
-//	u8 *domain_name;
-//	size_t domain_name_len;
-
-//	unsigned int nai_realm_count;
-//	struct hostapd_nai_realm_data *nai_realm_data;
-
-//	u16 gas_comeback_delay;
-//	int gas_frag_limit;
-
-#ifdef CONFIG_HS20
-	int hs20;
-	int disable_dgaf;
-	unsigned int hs20_oper_friendly_name_count;
-	struct hostapd_lang_string *hs20_oper_friendly_name;
-	u8 *hs20_wan_metrics;
-	u8 *hs20_connection_capability;
-	size_t hs20_connection_capability_len;
-	u8 *hs20_operating_class;
-	u8 hs20_operating_class_len;
-#endif /* CONFIG_HS20 */
-
-//	u8 wps_rf_bands; /* RF bands for WPS (WPS_RF_*) */
-
-#ifdef CONFIG_RADIUS_TEST
-	char *dump_msk_file;
-#endif /* CONFIG_RADIUS_TEST */
-
-//	struct wpabuf *vendor_elements;
-};
-
-
-/**
- * struct hostapd_config - Per-radio interface configuration
- */
-struct hostapd_config {
-	struct hostapd_bss_config *bss, *last_bss;
-	size_t num_bss;
-
-	u16 beacon_int;
-	int rts_threshold;
-	int fragm_threshold;
-	u8 send_probe_response;
-	u8 channel;
-	enum hostapd_hw_mode hw_mode; /* HOSTAPD_MODE_IEEE80211A, .. */
-	enum {
-		LONG_PREAMBLE = 0,
-		SHORT_PREAMBLE = 1
-	} preamble;
-
-	int *supported_rates;
-	int *basic_rates;
-
-	const struct wpa_driver_ops *driver;
-
-	int ap_table_max_size;
-	int ap_table_expiration_time;
-
-	char country[3]; /* first two octets: country code as described in
-			  * ISO/IEC 3166-1. Third octet:
-			  * ' ' (ascii 32): all environments
-			  * 'O': Outdoor environemnt only
-			  * 'I': Indoor environment only
-			  */
-
-	int ieee80211d;
-
-//	struct hostapd_tx_queue_params tx_queue[NUM_TX_QUEUES];
-
-	/*
-	 * WMM AC parameters, in same order as 802.1D, i.e.
-	 * 0 = BE (best effort)
-	 * 1 = BK (background)
-	 * 2 = VI (video)
-	 * 3 = VO (voice)
-	 */
-//	struct hostapd_wmm_ac_params wmm_ac_params[4];
-
-	int ht_op_mode_fixed;
-	u16 ht_capab;
-	int ieee80211n;
-	int secondary_channel;
-	int require_ht;
-	u32 vht_capab;
-	int ieee80211ac;
-	int require_vht;
-	u8 vht_oper_chwidth;
-	u8 vht_oper_centr_freq_seg0_idx;
-	u8 vht_oper_centr_freq_seg1_idx;
-};
-
-
-int hostapd_mac_comp(const void *a, const void *b);
-int hostapd_mac_comp_empty(const void *a);
-struct hostapd_config * hostapd_config_defaults(void);
-void hostapd_config_defaults_bss(struct hostapd_bss_config *bss);
-void hostapd_config_free(struct hostapd_config *conf);
-int hostapd_maclist_found(struct mac_acl_entry *list, int num_entries,
-			  const u8 *addr, int *vlan_id);
-int hostapd_rate_found(int *list, int rate);
-int hostapd_wep_key_cmp(struct hostapd_wep_keys *a,
-			struct hostapd_wep_keys *b);
-const u8 * hostapd_get_psk(const struct hostapd_bss_config *conf,
-			   const u8 *addr, const u8 *prev_psk);
-int hostapd_setup_wpa_psk(struct hostapd_bss_config *conf);
-//const char * hostapd_get_vlan_id_ifname(struct hostapd_vlan *vlan,
-//					int vlan_id);
-//struct hostapd_radius_attr *
-//hostapd_config_get_radius_attr(struct hostapd_radius_attr *attr, u8 type);
-
-#endif /* HOSTAPD_CONFIG_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/common.h b/tools/sdk/include/wpa_supplicant/wpa/common.h
deleted file mode 100644
index 2e6012f8686..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/common.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * wpa_supplicant/hostapd / common helper functions, etc.
- * Copyright (c) 2002-2007, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef COMMON_H
-#define COMMON_H
-
-#if defined(__ets__)
-#endif /* ets */
-#include "os.h"
-
-/* Define platform specific variable type macros */
-#if defined(ESP_PLATFORM)
-#include <stdint.h>
-typedef uint64_t u64;
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-typedef int64_t s64;
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-#endif /*ESP_PLATFORM*/
-
-#if defined(__XTENSA__)
-#include <machine/endian.h>
-#define __BYTE_ORDER     BYTE_ORDER
-#define __LITTLE_ENDIAN  LITTLE_ENDIAN
-#define __BIG_ENDIAN     BIG_ENDIAN
-#endif /*__XTENSA__*/
-
-#if defined(__linux__) || defined(__GLIBC__) || defined(__ets__)
-#include <endian.h>
-#include <byteswap.h>
-#endif /* __linux__ */
-
-/* Define platform specific byte swapping macros */
-
-#if defined(__CYGWIN__) || defined(CONFIG_NATIVE_WINDOWS)
-
-static inline unsigned short wpa_swap_16(unsigned short v)
-{
-	return ((v & 0xff) << 8) | (v >> 8);
-}
-
-static inline unsigned int wpa_swap_32(unsigned int v)
-{
-	return ((v & 0xff) << 24) | ((v & 0xff00) << 8) |
-		((v & 0xff0000) >> 8) | (v >> 24);
-}
-
-#define le_to_host16(n) (n)
-#define host_to_le16(n) (n)
-#define be_to_host16(n) wpa_swap_16(n)
-#define host_to_be16(n) wpa_swap_16(n)
-#define le_to_host32(n) (n)
-#define be_to_host32(n) wpa_swap_32(n)
-#define host_to_be32(n) wpa_swap_32(n)
-
-#define WPA_BYTE_SWAP_DEFINED
-
-#endif /* __CYGWIN__ || CONFIG_NATIVE_WINDOWS */
-
-
-#ifndef WPA_BYTE_SWAP_DEFINED
-
-#ifndef __BYTE_ORDER
-#ifndef __LITTLE_ENDIAN
-#ifndef __BIG_ENDIAN
-#define __LITTLE_ENDIAN 1234
-#define __BIG_ENDIAN 4321
-#if defined(sparc)
-#define __BYTE_ORDER __BIG_ENDIAN
-#endif
-#endif /* __BIG_ENDIAN */
-#endif /* __LITTLE_ENDIAN */
-#endif /* __BYTE_ORDER */
-
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-#define le_to_host16(n) ((__force u16) (le16) (n))
-#define host_to_le16(n) ((__force le16) (u16) (n))
-#define be_to_host16(n) __bswap_16((__force u16) (be16) (n))
-#define host_to_be16(n) ((__force be16) __bswap_16((n)))
-#define le_to_host32(n) ((__force u32) (le32) (n))
-#define host_to_le32(n) ((__force le32) (u32) (n))
-#define be_to_host32(n) __bswap_32((__force u32) (be32) (n))
-#define host_to_be32(n) ((__force be32) __bswap_32((n)))
-#define le_to_host64(n) ((__force u64) (le64) (n))
-#define host_to_le64(n) ((__force le64) (u64) (n))
-#define be_to_host64(n) __bswap_64((__force u64) (be64) (n))
-#define host_to_be64(n) ((__force be64) bswap_64((n)))
-#elif __BYTE_ORDER == __BIG_ENDIAN
-#define le_to_host16(n) __bswap_16(n)
-#define host_to_le16(n) __bswap_16(n)
-#define be_to_host16(n) (n)
-#define host_to_be16(n) (n)
-#define le_to_host32(n) __bswap_32(n)
-#define be_to_host32(n) (n)
-#define host_to_be32(n) (n)
-#define le_to_host64(n) __bswap_64(n)
-#define host_to_le64(n) __bswap_64(n)
-#define be_to_host64(n) (n)
-#define host_to_be64(n) (n)
-#ifndef WORDS_BIGENDIAN
-#define WORDS_BIGENDIAN
-#endif
-#else
-#error Could not determine CPU byte order
-#endif
-
-#define WPA_BYTE_SWAP_DEFINED
-#endif /* !WPA_BYTE_SWAP_DEFINED */
-
-
-/* Macros for handling unaligned memory accesses */
-
-#define WPA_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
-#define WPA_PUT_BE16(a, val)			\
-	do {					\
-		(a)[0] = ((u16) (val)) >> 8;	\
-		(a)[1] = ((u16) (val)) & 0xff;	\
-	} while (0)
-
-#define WPA_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))
-#define WPA_PUT_LE16(a, val)			\
-	do {					\
-		(a)[1] = ((u16) (val)) >> 8;	\
-		(a)[0] = ((u16) (val)) & 0xff;	\
-	} while (0)
-
-#define WPA_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
-			 ((u32) (a)[2]))
-#define WPA_PUT_BE24(a, val)					\
-	do {							\
-		(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-		(a)[2] = (u8) (((u32) (val)) & 0xff);		\
-	} while (0)
-
-#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
-			 (((u32) (a)[2]) << 8) | ((u32) (a)[3]))
-#define WPA_PUT_BE32(a, val)					\
-	do {							\
-		(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
-		(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-		(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-		(a)[3] = (u8) (((u32) (val)) & 0xff);		\
-	} while (0)
-
-#define WPA_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
-			 (((u32) (a)[1]) << 8) | ((u32) (a)[0]))
-#define WPA_PUT_LE32(a, val)					\
-	do {							\
-		(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff);	\
-		(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff);	\
-		(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff);	\
-		(a)[0] = (u8) (((u32) (val)) & 0xff);		\
-	} while (0)
-
-#define WPA_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
-			 (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
-			 (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
-			 (((u64) (a)[6]) << 8) | ((u64) (a)[7]))
-#define WPA_PUT_BE64(a, val)				\
-	do {						\
-		(a)[0] = (u8) (((u64) (val)) >> 56);	\
-		(a)[1] = (u8) (((u64) (val)) >> 48);	\
-		(a)[2] = (u8) (((u64) (val)) >> 40);	\
-		(a)[3] = (u8) (((u64) (val)) >> 32);	\
-		(a)[4] = (u8) (((u64) (val)) >> 24);	\
-		(a)[5] = (u8) (((u64) (val)) >> 16);	\
-		(a)[6] = (u8) (((u64) (val)) >> 8);	\
-		(a)[7] = (u8) (((u64) (val)) & 0xff);	\
-	} while (0)
-
-#define WPA_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \
-			 (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \
-			 (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \
-			 (((u64) (a)[1]) << 8) | ((u64) (a)[0]))
-
-
-#ifndef ETH_ALEN
-#define ETH_ALEN 6
-#endif
-//#ifndef IFNAMSIZ
-//#define IFNAMSIZ 16
-//#endif
-#ifndef ETH_P_ALL
-#define ETH_P_ALL 0x0003
-#endif
-#ifndef ETH_P_PAE
-#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */
-#endif /* ETH_P_PAE */
-#ifndef ETH_P_EAPOL
-#define ETH_P_EAPOL ETH_P_PAE
-#endif /* ETH_P_EAPOL */
-#ifndef ETH_P_RSN_PREAUTH
-#define ETH_P_RSN_PREAUTH 0x88c7
-#endif /* ETH_P_RSN_PREAUTH */
-#ifndef ETH_P_RRB
-#define ETH_P_RRB 0x890D
-#endif /* ETH_P_RRB */
-
-
-#ifdef __GNUC__
-#define PRINTF_FORMAT(a,b) __attribute__ ((format (printf, (a), (b))))
-#define STRUCT_PACKED __attribute__ ((packed))
-#else
-#define PRINTF_FORMAT(a,b)
-#define STRUCT_PACKED
-#endif
-
-#ifdef CONFIG_ANSI_C_EXTRA
-
-/* inline - define as __inline or just define it to be empty, if needed */
-#ifdef CONFIG_NO_INLINE
-#define inline
-#else
-#define inline __inline
-#endif
-
-#ifndef __func__
-#define __func__ "__func__ not defined"
-#endif
-
-#ifndef bswap_16
-#define bswap_16(a) ((((u16) (a) << 8) & 0xff00) | (((u16) (a) >> 8) & 0xff))
-#endif
-
-#ifndef bswap_32
-#define bswap_32(a) ((((u32) (a) << 24) & 0xff000000) | \
-		     (((u32) (a) << 8) & 0xff0000) | \
-     		     (((u32) (a) >> 8) & 0xff00) | \
-     		     (((u32) (a) >> 24) & 0xff))
-#endif
-
-#ifndef MSG_DONTWAIT
-#define MSG_DONTWAIT 0
-#endif
-
-#ifdef _WIN32_WCE
-void perror(const char *s);
-#endif /* _WIN32_WCE */
-
-#endif /* CONFIG_ANSI_C_EXTRA */
-
-#ifndef MAC2STR
-#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
-#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
-#endif
-
-#ifndef BIT
-#define BIT(x) (1 << (x))
-#endif
-
-/*
- * Definitions for sparse validation
- * (http://kernel.org/pub/linux/kernel/people/josh/sparse/)
- */
-#ifdef __CHECKER__
-#define __force __attribute__((force))
-#define __bitwise __attribute__((bitwise))
-#else
-#define __force
-#define __bitwise
-#endif
-
-typedef u16 __bitwise be16;
-typedef u16 __bitwise le16;
-typedef u32 __bitwise be32;
-typedef u32 __bitwise le32;
-typedef u64 __bitwise be64;
-typedef u64 __bitwise le64;
-
-#ifndef __must_check
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
-#define __must_check __attribute__((__warn_unused_result__))
-#else
-#define __must_check
-#endif /* __GNUC__ */
-#endif /* __must_check */
-
-int hwaddr_aton(const char *txt, u8 *addr);
-int hwaddr_aton2(const char *txt, u8 *addr);
-int hexstr2bin(const char *hex, u8 *buf, size_t len);
-void inc_byte_array(u8 *counter, size_t len);
-void wpa_get_ntp_timestamp(u8 *buf);
-int wpa_snprintf_hex(char *buf, size_t buf_size, const u8 *data, size_t len);
-int wpa_snprintf_hex_uppercase(char *buf, size_t buf_size, const u8 *data,
-			       size_t len);
-
-#ifdef CONFIG_NATIVE_WINDOWS
-void wpa_unicode2ascii_inplace(TCHAR *str);
-TCHAR * wpa_strdup_tchar(const char *str);
-#else /* CONFIG_NATIVE_WINDOWS */
-#define wpa_unicode2ascii_inplace(s) do { } while (0)
-#define wpa_strdup_tchar(s) strdup((s))
-#endif /* CONFIG_NATIVE_WINDOWS */
-
-const char * wpa_ssid_txt(const u8 *ssid, size_t ssid_len);
-char * wpa_config_parse_string(const char *value, size_t *len);
-
-static inline int is_zero_ether_addr(const u8 *a)
-{
-	return !(a[0] | a[1] | a[2] | a[3] | a[4] | a[5]);
-}
-
-extern const struct eth_addr ethbroadcast;
-#define broadcast_ether_addr &ethbroadcast
-
-#include "wpabuf.h"
-#include "wpa_debug.h"
-
-
-/*
- * gcc 4.4 ends up generating strict-aliasing warnings about some very common
- * networking socket uses that do not really result in a real problem and
- * cannot be easily avoided with union-based type-punning due to struct
- * definitions including another struct in system header files. To avoid having
- * to fully disable strict-aliasing warnings, provide a mechanism to hide the
- * typecast from aliasing for now. A cleaner solution will hopefully be found
- * in the future to handle these cases.
- */
-void * __hide_aliasing_typecast(void *foo);
-#define aliasing_hide_typecast(a,t) (t *) __hide_aliasing_typecast((a))
-
-#endif /* COMMON_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/defs.h b/tools/sdk/include/wpa_supplicant/wpa/defs.h
deleted file mode 100644
index f019cee9927..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/defs.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * WPA Supplicant - Common definitions
- * Copyright (c) 2004-2008, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef DEFS_H
-#define DEFS_H
-
-#ifdef FALSE
-#undef FALSE
-#endif
-#ifdef TRUE
-#undef TRUE
-#endif
-typedef enum { FALSE = 0, TRUE = 1 } Boolean;
-
-/*
-#define WPA_CIPHER_NONE BIT(0)
-#define WPA_CIPHER_WEP40 BIT(1)
-#define WPA_CIPHER_WEP104 BIT(2)
-#define WPA_CIPHER_TKIP BIT(3)
-#define WPA_CIPHER_CCMP BIT(4)
-#ifdef CONFIG_IEEE80211W
-#define WPA_CIPHER_AES_128_CMAC BIT(5)
-#endif 
-*/
-
-/*
- * NB: these values are ordered carefully; there are lots of
- * of implications in any reordering.  Beware that 4 is used
- * only to indicate h/w TKIP MIC support in driver capabilities;
- * there is no separate cipher support (it's rolled into the
- * TKIP cipher support).
- */
-#define	IEEE80211_CIPHER_NONE		0	/* pseudo value */
-#define	IEEE80211_CIPHER_TKIP		1
-#define	IEEE80211_CIPHER_AES_OCB	2
-#define	IEEE80211_CIPHER_AES_CCM	3
-#define	IEEE80211_CIPHER_TKIPMIC	4	/* TKIP MIC capability */
-#define	IEEE80211_CIPHER_CKIP		5
-#define	IEEE80211_CIPHER_WEP		6
-#define	IEEE80211_CIPHER_WEP40		7
-#define	IEEE80211_CIPHER_WEP104		8
-
-
-#define	IEEE80211_CIPHER_MAX		(IEEE80211_CIPHER_NONE+2)
-
-/* capability bits in ic_cryptocaps/iv_cryptocaps */
-#define	IEEE80211_CRYPTO_NONE		(1<<IEEE80211_CIPHER_NONE)
-#define	IEEE80211_CRYPTO_WEP		(1<<IEEE80211_CIPHER_WEP)
-#define	IEEE80211_CRYPTO_WEP40		(1<<IEEE80211_CIPHER_WEP40)
-#define	IEEE80211_CRYPTO_WEP104	(1<<IEEE80211_CIPHER_WEP104)
-#define	IEEE80211_CRYPTO_TKIP		(1<<IEEE80211_CIPHER_TKIP)
-#define	IEEE80211_CRYPTO_AES_OCB	(1<<IEEE80211_CIPHER_AES_OCB)
-#define	IEEE80211_CRYPTO_AES_CCM	(1<<IEEE80211_CIPHER_AES_CCM)
-#define	IEEE80211_CRYPTO_TKIPMIC	(1<<IEEE80211_CIPHER_TKIPMIC)
-#define	IEEE80211_CRYPTO_CKIP		(1<<IEEE80211_CIPHER_CKIP)
-
-#define WPA_CIPHER_NONE                     IEEE80211_CRYPTO_NONE
-#define WPA_CIPHER_WEP40                    IEEE80211_CRYPTO_WEP40
-#define WPA_CIPHER_WEP104                  IEEE80211_CRYPTO_WEP104
-#define WPA_CIPHER_TKIP                       IEEE80211_CRYPTO_TKIP
-#define WPA_CIPHER_CCMP                     IEEE80211_CRYPTO_AES_CCM
-#ifdef CONFIG_IEEE80211W
-#define WPA_CIPHER_AES_128_CMAC    IEEE80211_CRYPTO_AES_OCB
-#endif /* CONFIG_IEEE80211W */
-#define WPA_CIPHER_GCMP BIT(6)
-
-#define WPA_KEY_MGMT_IEEE8021X BIT(0)
-#define WPA_KEY_MGMT_PSK BIT(1)
-#define WPA_KEY_MGMT_NONE BIT(2)
-#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
-#define WPA_KEY_MGMT_WPA_NONE BIT(4)
-#define WPA_KEY_MGMT_FT_IEEE8021X BIT(5)
-#define WPA_KEY_MGMT_FT_PSK BIT(6)
-#define WPA_KEY_MGMT_IEEE8021X_SHA256 BIT(7)
-#define WPA_KEY_MGMT_PSK_SHA256 BIT(8)
-#define WPA_KEY_MGMT_WPS BIT(9)
-#define WPA_KEY_MGMT_CCKM BIT(14)
-
-static inline int wpa_key_mgmt_wpa_ieee8021x(int akm)
-{
-	return !!(akm & (WPA_KEY_MGMT_IEEE8021X |
-			 WPA_KEY_MGMT_FT_IEEE8021X |
-			 WPA_KEY_MGMT_CCKM |
-			 WPA_KEY_MGMT_IEEE8021X_SHA256));
-}
-
-static inline int wpa_key_mgmt_wpa_psk(int akm)
-{
-	return akm == WPA_KEY_MGMT_PSK ||
-		akm == WPA_KEY_MGMT_FT_PSK ||
-		akm == WPA_KEY_MGMT_PSK_SHA256;
-}
-
-static inline int wpa_key_mgmt_ft(int akm)
-{
-	return akm == WPA_KEY_MGMT_FT_PSK ||
-		akm == WPA_KEY_MGMT_FT_IEEE8021X;
-}
-
-static inline int wpa_key_mgmt_sha256(int akm)
-{
-	return akm == WPA_KEY_MGMT_PSK_SHA256 ||
-		akm == WPA_KEY_MGMT_IEEE8021X_SHA256;
-}
-
-
-#define WPA_PROTO_WPA BIT(0)
-#define WPA_PROTO_RSN BIT(1)
-
-#define WPA_AUTH_ALG_OPEN BIT(0)
-#define WPA_AUTH_ALG_SHARED BIT(1)
-#define WPA_AUTH_ALG_LEAP BIT(2)
-#define WPA_AUTH_ALG_FT BIT(3)
-
-
-enum ieee80211_key_alg {
-	ALG_WEP,
-	ALG_TKIP,
-	ALG_CCMP,
-	ALG_AES_CMAC,
-};
-
-enum wpa_alg {
-	WPA_ALG_NONE =0,
-	WPA_ALG_WEP40 = 1,
-	WPA_ALG_TKIP = 2,
-	WPA_ALG_CCMP = 3,
-	WPA_ALG_WAPI = 4,
-	WPA_ALG_WEP104 = 5,
-	WPA_ALG_WEP,
-	WPA_ALG_IGTK,
-	WPA_ALG_PMK,
-	WPA_ALG_GCMP
-};
-
-/**
- * enum wpa_cipher - Cipher suites
- */
-enum wpa_cipher {
-	CIPHER_NONE,
-	CIPHER_WEP40,
-	CIPHER_TKIP,
-	CIPHER_CCMP,
-	CIPHER_WEP104
-};
-
-/**
- * enum wpa_key_mgmt - Key management suites
- */
-enum wpa_key_mgmt {
-	KEY_MGMT_802_1X,
-	KEY_MGMT_PSK,
-	KEY_MGMT_NONE,
-	KEY_MGMT_802_1X_NO_WPA,
-	KEY_MGMT_WPA_NONE,
-	KEY_MGMT_FT_802_1X,
-	KEY_MGMT_FT_PSK,
-	KEY_MGMT_802_1X_SHA256,
-	KEY_MGMT_PSK_SHA256,
-	KEY_MGMT_WPS
-};
-
-/**
- * enum wpa_states - wpa_supplicant state
- *
- * These enumeration values are used to indicate the current wpa_supplicant
- * state (wpa_s->wpa_state). The current state can be retrieved with
- * wpa_supplicant_get_state() function and the state can be changed by calling
- * wpa_supplicant_set_state(). In WPA state machine (wpa.c and preauth.c), the
- * wrapper functions wpa_sm_get_state() and wpa_sm_set_state() should be used
- * to access the state variable.
- */
-enum wpa_states {
-	/**
-	 * WPA_DISCONNECTED - Disconnected state
-	 *
-	 * This state indicates that client is not associated, but is likely to
-	 * start looking for an access point. This state is entered when a
-	 * connection is lost.
-	 */
-	WPA_DISCONNECTED,
-
-	/**
-	 * WPA_INACTIVE - Inactive state (wpa_supplicant disabled)
-	 *
-	 * This state is entered if there are no enabled networks in the
-	 * configuration. wpa_supplicant is not trying to associate with a new
-	 * network and external interaction (e.g., ctrl_iface call to add or
-	 * enable a network) is needed to start association.
-	 */
-	WPA_INACTIVE,
-
-	/**
-	 * WPA_SCANNING - Scanning for a network
-	 *
-	 * This state is entered when wpa_supplicant starts scanning for a
-	 * network.
-	 */
-	WPA_SCANNING,
-
-	/**
-	 * WPA_AUTHENTICATING - Trying to authenticate with a BSS/SSID
-	 *
-	 * This state is entered when wpa_supplicant has found a suitable BSS
-	 * to authenticate with and the driver is configured to try to
-	 * authenticate with this BSS. This state is used only with drivers
-	 * that use wpa_supplicant as the SME.
-	 */
-	WPA_AUTHENTICATING,
-
-	/**
-	 * WPA_ASSOCIATING - Trying to associate with a BSS/SSID
-	 *
-	 * This state is entered when wpa_supplicant has found a suitable BSS
-	 * to associate with and the driver is configured to try to associate
-	 * with this BSS in ap_scan=1 mode. When using ap_scan=2 mode, this
-	 * state is entered when the driver is configured to try to associate
-	 * with a network using the configured SSID and security policy.
-	 */
-	WPA_ASSOCIATING,
-
-	/**
-	 * WPA_ASSOCIATED - Association completed
-	 *
-	 * This state is entered when the driver reports that association has
-	 * been successfully completed with an AP. If IEEE 802.1X is used
-	 * (with or without WPA/WPA2), wpa_supplicant remains in this state
-	 * until the IEEE 802.1X/EAPOL authentication has been completed.
-	 */
-	WPA_ASSOCIATED,
-
-	/**
-	 * WPA_4WAY_HANDSHAKE - WPA 4-Way Key Handshake in progress
-	 *
-	 * This state is entered when WPA/WPA2 4-Way Handshake is started. In
-	 * case of WPA-PSK, this happens when receiving the first EAPOL-Key
-	 * frame after association. In case of WPA-EAP, this state is entered
-	 * when the IEEE 802.1X/EAPOL authentication has been completed.
-	 */
-	WPA_FIRST_HALF_4WAY_HANDSHAKE,
-
-	WPA_LAST_HALF_4WAY_HANDSHAKE,
-
-	/**
-	 * WPA_GROUP_HANDSHAKE - WPA Group Key Handshake in progress
-	 *
-	 * This state is entered when 4-Way Key Handshake has been completed
-	 * (i.e., when the supplicant sends out message 4/4) and when Group
-	 * Key rekeying is started by the AP (i.e., when supplicant receives
-	 * message 1/2).
-	 */
-	WPA_GROUP_HANDSHAKE,
-
-	/**
-	 * WPA_COMPLETED - All authentication completed
-	 *
-	 * This state is entered when the full authentication process is
-	 * completed. In case of WPA2, this happens when the 4-Way Handshake is
-	 * successfully completed. With WPA, this state is entered after the
-	 * Group Key Handshake; with IEEE 802.1X (non-WPA) connection is
-	 * completed after dynamic keys are received (or if not used, after
-	 * the EAP authentication has been completed). With static WEP keys and
-	 * plaintext connections, this state is entered when an association
-	 * has been completed.
-	 *
-	 * This state indicates that the supplicant has completed its
-	 * processing for the association phase and that data connection is
-	 * fully configured.
-	 */
-	WPA_COMPLETED,
-
-	WPA_MIC_FAILURE,                         // first mic_error event occur
-
-	WPA_TKIP_COUNTERMEASURES  //in countermeasure period that stop connect with ap in 60 sec
-};
-
-#define MLME_SETPROTECTION_PROTECT_TYPE_NONE 0
-#define MLME_SETPROTECTION_PROTECT_TYPE_RX 1
-#define MLME_SETPROTECTION_PROTECT_TYPE_TX 2
-#define MLME_SETPROTECTION_PROTECT_TYPE_RX_TX 3
-
-#define MLME_SETPROTECTION_KEY_TYPE_GROUP 0
-#define MLME_SETPROTECTION_KEY_TYPE_PAIRWISE 1
-
-/**
- * enum hostapd_hw_mode - Hardware mode
- */
-enum hostapd_hw_mode {
-	HOSTAPD_MODE_IEEE80211B,
-	HOSTAPD_MODE_IEEE80211G,
-	HOSTAPD_MODE_IEEE80211A,
-	HOSTAPD_MODE_IEEE80211AD,
-	NUM_HOSTAPD_MODES
-};
-
-#endif /* DEFS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/eapol_common.h b/tools/sdk/include/wpa_supplicant/wpa/eapol_common.h
deleted file mode 100644
index 6a40ac33b3f..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/eapol_common.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * EAPOL definitions shared between hostapd and wpa_supplicant
- * Copyright (c) 2002-2007, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef EAPOL_COMMON_H
-#define EAPOL_COMMON_H
-
-/* IEEE Std 802.1X-2004 */
-
-struct ieee802_1x_hdr {
-	u8 version;
-	u8 type;
-	be16 length;
-	/* followed by length octets of data */
-} STRUCT_PACKED;
-
-
-#define EAPOL_VERSION 2
-
-enum { IEEE802_1X_TYPE_EAP_PACKET = 0,
-       IEEE802_1X_TYPE_EAPOL_START = 1,
-       IEEE802_1X_TYPE_EAPOL_LOGOFF = 2,
-       IEEE802_1X_TYPE_EAPOL_KEY = 3,
-       IEEE802_1X_TYPE_EAPOL_ENCAPSULATED_ASF_ALERT = 4
-};
-
-enum { EAPOL_KEY_TYPE_RC4 = 1, EAPOL_KEY_TYPE_RSN = 2,
-       EAPOL_KEY_TYPE_WPA = 254 };
-
-#define IEEE8021X_REPLAY_COUNTER_LEN 8
-#define IEEE8021X_KEY_SIGN_LEN 16
-#define IEEE8021X_KEY_IV_LEN 16
-
-#define IEEE8021X_KEY_INDEX_FLAG 0x80
-#define IEEE8021X_KEY_INDEX_MASK 0x03
-
-struct ieee802_1x_eapol_key {
-	u8 type;
-	/* Note: key_length is unaligned */
-	u8 key_length[2];
-	/* does not repeat within the life of the keying material used to
-	 * encrypt the Key field; 64-bit NTP timestamp MAY be used here */
-	u8 replay_counter[IEEE8021X_REPLAY_COUNTER_LEN];
-	u8 key_iv[IEEE8021X_KEY_IV_LEN]; /* cryptographically random number */
-	u8 key_index; /* key flag in the most significant bit:
-		       * 0 = broadcast (default key),
-		       * 1 = unicast (key mapping key); key index is in the
-		       * 7 least significant bits */
-	/* HMAC-MD5 message integrity check computed with MS-MPPE-Send-Key as
-	 * the key */
-	u8 key_signature[IEEE8021X_KEY_SIGN_LEN];
-
-	/* followed by key: if packet body length = 44 + key length, then the
-	 * key field (of key_length bytes) contains the key in encrypted form;
-	 * if packet body length = 44, key field is absent and key_length
-	 * represents the number of least significant octets from
-	 * MS-MPPE-Send-Key attribute to be used as the keying material;
-	 * RC4 key used in encryption = Key-IV + MS-MPPE-Recv-Key */
-} STRUCT_PACKED;
-
-#endif /* EAPOL_COMMON_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/hostapd.h b/tools/sdk/include/wpa_supplicant/wpa/hostapd.h
deleted file mode 100644
index 1d52659a224..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/hostapd.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * hostapd / Initialization and configuration
- * Copyright (c) 2002-2009, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef HOSTAPD_H
-#define HOSTAPD_H
-
-#include "wpa/defs.h"
-#include "wpa/ap_config.h"
-
-struct wpa_driver_ops;
-struct wpa_ctrl_dst;
-struct radius_server_data;
-struct upnp_wps_device_sm;
-struct hostapd_data;
-struct sta_info;
-struct hostap_sta_driver_data;
-struct ieee80211_ht_capabilities;
-struct full_dynamic_vlan;
-enum wps_event;
-union wps_event_data;
-
-struct hostapd_iface;
-
-struct hapd_interfaces {
-	int (*reload_config)(struct hostapd_iface *iface);
-	struct hostapd_config * (*config_read_cb)(const char *config_fname);
-	int (*ctrl_iface_init)(struct hostapd_data *hapd);
-	void (*ctrl_iface_deinit)(struct hostapd_data *hapd);
-	int (*for_each_interface)(struct hapd_interfaces *interfaces,
-				  int (*cb)(struct hostapd_iface *iface,
-					    void *ctx), void *ctx);
-	int (*driver_init)(struct hostapd_iface *iface);
-
-	size_t count;
-	int global_ctrl_sock;
-	char *global_iface_path;
-	char *global_iface_name;
-	struct hostapd_iface **iface;
-};
-
-
-struct hostapd_probereq_cb {
-	int (*cb)(void *ctx, const u8 *sa, const u8 *da, const u8 *bssid,
-		  const u8 *ie, size_t ie_len, int ssi_signal);
-	void *ctx;
-};
-
-#define HOSTAPD_RATE_BASIC 0x00000001
-
-struct hostapd_rate_data {
-	int rate; /* rate in 100 kbps */
-	int flags; /* HOSTAPD_RATE_ flags */
-};
-
-struct hostapd_frame_info {
-	u32 channel;
-	u32 datarate;
-	int ssi_signal; /* dBm */
-};
-
-
-/**
- * struct hostapd_data - hostapd per-BSS data structure
- */
-struct hostapd_data {
-//	struct hostapd_iface *iface;
-	struct hostapd_config *iconf;
-	struct hostapd_bss_config *conf;
-	int interface_added; /* virtual interface added for this BSS */
-
-	u8 own_addr[ETH_ALEN];
-
-	int num_sta; /* number of entries in sta_list */
-//	struct sta_info *sta_list; /* STA info list head */
-//#define STA_HASH_SIZE 256
-//#define STA_HASH(sta) (sta[5])
-//	struct sta_info *sta_hash[STA_HASH_SIZE];
-
-//	/*
-//	 * Bitfield for indicating which AIDs are allocated. Only AID values
-//	 * 1-2007 are used and as such, the bit at index 0 corresponds to AID
-//	 * 1.
-//	 */
-//#define AID_WORDS ((2008 + 31) / 32)
-//	u32 sta_aid[AID_WORDS];
-
-//	const struct wpa_driver_ops *driver;
-//	void *drv_priv;
-
-//	void (*new_assoc_sta_cb)(struct hostapd_data *hapd,
-//				 struct sta_info *sta, int reassoc);
-
-//	void *msg_ctx; /* ctx for wpa_msg() calls */
-//	void *msg_ctx_parent; /* parent interface ctx for wpa_msg() calls */
-
-//	struct radius_client_data *radius;
-//	u32 acct_session_id_hi, acct_session_id_lo;
-//	struct radius_das_data *radius_das;
-
-//	struct iapp_data *iapp;
-
-//	struct hostapd_cached_radius_acl *acl_cache;
-//	struct hostapd_acl_query_data *acl_queries;
-
-	struct wpa_authenticator *wpa_auth;
-//	struct eapol_authenticator *eapol_auth;
-
-//	struct rsn_preauth_interface *preauth_iface;
-//	time_t michael_mic_failure;
-//	int michael_mic_failures;
-//	int tkip_countermeasures;
-
-//	int ctrl_sock;
-//	struct wpa_ctrl_dst *ctrl_dst;
-
-//	void *ssl_ctx;
-//	void *eap_sim_db_priv;
-//	struct radius_server_data *radius_srv;
-
-//	int parameter_set_count;
-
-	/* Time Advertisement */
-//	u8 time_update_counter;
-//	struct wpabuf *time_adv;
-
-#ifdef CONFIG_FULL_DYNAMIC_VLAN
-	struct full_dynamic_vlan *full_dynamic_vlan;
-#endif /* CONFIG_FULL_DYNAMIC_VLAN */
-
-//	struct l2_packet_data *l2;
-//	struct wps_context *wps;
-
-//	int beacon_set_done;
-//	struct wpabuf *wps_beacon_ie;
-//	struct wpabuf *wps_probe_resp_ie;
-#ifdef CONFIG_WPS
-	unsigned int ap_pin_failures;
-	unsigned int ap_pin_failures_consecutive;
-	struct upnp_wps_device_sm *wps_upnp;
-	unsigned int ap_pin_lockout_time;
-#endif /* CONFIG_WPS */
-
-//	struct hostapd_probereq_cb *probereq_cb;
-//	size_t num_probereq_cb;
-
-//	void (*public_action_cb)(void *ctx, const u8 *buf, size_t len,
-//				 int freq);
-//	void *public_action_cb_ctx;
-
-//	int (*vendor_action_cb)(void *ctx, const u8 *buf, size_t len,
-//				int freq);
-//	void *vendor_action_cb_ctx;
-
-//	void (*wps_reg_success_cb)(void *ctx, const u8 *mac_addr,
-//				   const u8 *uuid_e);
-//	void *wps_reg_success_cb_ctx;
-
-//	void (*wps_event_cb)(void *ctx, enum wps_event event,
-//			     union wps_event_data *data);
-//	void *wps_event_cb_ctx;
-
-//	void (*sta_authorized_cb)(void *ctx, const u8 *mac_addr,
-//				  int authorized, const u8 *p2p_dev_addr);
-//	void *sta_authorized_cb_ctx;
-
-//	void (*setup_complete_cb)(void *ctx);
-//	void *setup_complete_cb_ctx;
-
-#ifdef CONFIG_P2P
-	struct p2p_data *p2p;
-	struct p2p_group *p2p_group;
-	struct wpabuf *p2p_beacon_ie;
-	struct wpabuf *p2p_probe_resp_ie;
-
-	/* Number of non-P2P association stations */
-	int num_sta_no_p2p;
-
-	/* Periodic NoA (used only when no non-P2P clients in the group) */
-	int noa_enabled;
-	int noa_start;
-	int noa_duration;
-#endif /* CONFIG_P2P */
-#ifdef CONFIG_INTERWORKING
-	size_t gas_frag_limit;
-#endif /* CONFIG_INTERWORKING */
-
-#ifdef CONFIG_SQLITE
-	struct hostapd_eap_user tmp_eap_user;
-#endif /* CONFIG_SQLITE */
-};
-
-#if 0
-/**
- * struct hostapd_iface - hostapd per-interface data structure
- */
-struct hostapd_iface {
-	struct hapd_interfaces *interfaces;
-	void *owner;
-	char *config_fname;
-	struct hostapd_config *conf;
-
-	size_t num_bss;
-	struct hostapd_data **bss;
-
-	int num_ap; /* number of entries in ap_list */
-	struct ap_info *ap_list; /* AP info list head */
-	struct ap_info *ap_hash[STA_HASH_SIZE];
-	struct ap_info *ap_iter_list;
-
-	unsigned int drv_flags;
-
-	/*
-	 * A bitmap of supported protocols for probe response offload. See
-	 * struct wpa_driver_capa in driver.h
-	 */
-	unsigned int probe_resp_offloads;
-
-	struct hostapd_hw_modes *hw_features;
-	int num_hw_features;
-	struct hostapd_hw_modes *current_mode;
-	/* Rates that are currently used (i.e., filtered copy of
-	 * current_mode->channels */
-	int num_rates;
-	struct hostapd_rate_data *current_rates;
-	int *basic_rates;
-	int freq;
-
-	u16 hw_flags;
-
-	/* Number of associated Non-ERP stations (i.e., stations using 802.11b
-	 * in 802.11g BSS) */
-	int num_sta_non_erp;
-
-	/* Number of associated stations that do not support Short Slot Time */
-	int num_sta_no_short_slot_time;
-
-	/* Number of associated stations that do not support Short Preamble */
-	int num_sta_no_short_preamble;
-
-	int olbc; /* Overlapping Legacy BSS Condition */
-
-	/* Number of HT associated stations that do not support greenfield */
-	int num_sta_ht_no_gf;
-
-	/* Number of associated non-HT stations */
-	int num_sta_no_ht;
-
-	/* Number of HT associated stations 20 MHz */
-	int num_sta_ht_20mhz;
-
-	/* Overlapping BSS information */
-	int olbc_ht;
-
-	u16 ht_op_mode;
-	void (*scan_cb)(struct hostapd_iface *iface);
-};
-#endif
-
-#if 0
-/* hostapd.c */
-int hostapd_for_each_interface(struct hapd_interfaces *interfaces,
-			       int (*cb)(struct hostapd_iface *iface,
-					 void *ctx), void *ctx);
-int hostapd_reload_config(struct hostapd_iface *iface);
-struct hostapd_data *
-hostapd_alloc_bss_data(struct hostapd_iface *hapd_iface,
-		       struct hostapd_config *conf,
-		       struct hostapd_bss_config *bss);
-int hostapd_setup_interface(struct hostapd_iface *iface);
-int hostapd_setup_interface_complete(struct hostapd_iface *iface, int err);
-void hostapd_interface_deinit(struct hostapd_iface *iface);
-void hostapd_interface_free(struct hostapd_iface *iface);
-void hostapd_new_assoc_sta(struct hostapd_data *hapd, struct sta_info *sta,
-			   int reassoc);
-void hostapd_interface_deinit_free(struct hostapd_iface *iface);
-int hostapd_enable_iface(struct hostapd_iface *hapd_iface);
-int hostapd_reload_iface(struct hostapd_iface *hapd_iface);
-int hostapd_disable_iface(struct hostapd_iface *hapd_iface);
-int hostapd_add_iface(struct hapd_interfaces *ifaces, char *buf);
-int hostapd_remove_iface(struct hapd_interfaces *ifaces, char *buf);
-
-/* utils.c */
-int hostapd_register_probereq_cb(struct hostapd_data *hapd,
-				 int (*cb)(void *ctx, const u8 *sa,
-					   const u8 *da, const u8 *bssid,
-					   const u8 *ie, size_t ie_len,
-					   int ssi_signal),
-				 void *ctx);
-void hostapd_prune_associations(struct hostapd_data *hapd, const u8 *addr);
-
-/* drv_callbacks.c (TODO: move to somewhere else?) */
-int hostapd_notif_assoc(struct hostapd_data *hapd, const u8 *addr,
-			const u8 *ie, size_t ielen, int reassoc);
-void hostapd_notif_disassoc(struct hostapd_data *hapd, const u8 *addr);
-void hostapd_event_sta_low_ack(struct hostapd_data *hapd, const u8 *addr);
-int hostapd_probe_req_rx(struct hostapd_data *hapd, const u8 *sa, const u8 *da,
-			 const u8 *bssid, const u8 *ie, size_t ie_len,
-			 int ssi_signal);
-void hostapd_event_ch_switch(struct hostapd_data *hapd, int freq, int ht,
-			     int offset);
-
-const struct hostapd_eap_user *
-hostapd_get_eap_user(struct hostapd_data *hapd, const u8 *identity,
-		     size_t identity_len, int phase2);
-#endif
-
-#endif /* HOSTAPD_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/ieee80211_crypto.h b/tools/sdk/include/wpa_supplicant/wpa/ieee80211_crypto.h
deleted file mode 100644
index be0fb9aa12a..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/ieee80211_crypto.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/*-
- * Copyright (c) 2001 Atsushi Onoe
- * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-/*
- * copyright (c) 2010-2011  Espressif System
- */
-#ifndef _NET80211_IEEE80211_CRYPTO_H_
-#define _NET80211_IEEE80211_CRYPTO_H_
-
-//#include "pp/esf_buf.h"
-
-/*
- * 802.11 protocol crypto-related definitions.
- */
-#define	IEEE80211_KEYBUF_SIZE	16
-#define	IEEE80211_MICBUF_SIZE	(8+8)	/* space for both tx+rx keys */
-
-/*
- * Old WEP-style key.  Deprecated.
- */
-
-#if 0
-struct ieee80211_rsnparms {
-	uint8_t		rsn_mcastcipher;	/* mcast/group cipher */
-	uint8_t		rsn_mcastkeylen;	/* mcast key length */
-	uint8_t		rsn_ucastcipher;	/* selected unicast cipher */
-	uint8_t		rsn_ucastkeylen;	/* unicast key length */
-	uint8_t		rsn_keymgmt;		/* selected key mgmt algo */
-	uint16_t	rsn_caps;		/* capabilities */
-};
-#endif //0000
-
-/*
- * Template for a supported cipher.  Ciphers register with the
- * crypto code and are typically loaded as separate modules
- * (the null cipher is always present).
- * XXX may need refcnts
- */
-
-/*
- * Crypto key state.  There is sufficient room for all supported
- * ciphers (see below).  The underlying ciphers are handled
- * separately through loadable cipher modules that register with
- * the generic crypto support.  A key has a reference to an instance
- * of the cipher; any per-key state is hung off wk_private by the
- * cipher when it is attached.  Ciphers are automatically called
- * to detach and cleanup any such state when the key is deleted.
- *
- * The generic crypto support handles encap/decap of cipher-related
- * frame contents for both hardware- and software-based implementations.
- * A key requiring software crypto support is automatically flagged and
- * the cipher is expected to honor this and do the necessary work.
- * Ciphers such as TKIP may also support mixed hardware/software
- * encrypt/decrypt and MIC processing.
- */
-typedef uint16_t ieee80211_keyix;	/* h/w key index */
-
-struct ieee80211_key {
-	uint8_t		wk_keylen;	/* key length in bytes */
-	uint8_t		wk_pad;
-	uint16_t	wk_flags;
-#define	IEEE80211_KEY_XMIT	0x0001	/* key used for xmit */
-#define	IEEE80211_KEY_RECV	0x0002	/* key used for recv */
-#define	IEEE80211_KEY_GROUP	0x0004	/* key used for WPA group operation */
-#define	IEEE80211_KEY_SWENCRYPT	0x0010	/* host-based encrypt */
-#define	IEEE80211_KEY_SWDECRYPT	0x0020	/* host-based decrypt */
-#define	IEEE80211_KEY_SWENMIC	0x0040	/* host-based enmic */
-#define	IEEE80211_KEY_SWDEMIC	0x0080	/* host-based demic */
-#define	IEEE80211_KEY_DEVKEY	0x0100	/* device key request completed */
-#define	IEEE80211_KEY_CIPHER0	0x1000	/* cipher-specific action 0 */
-#define	IEEE80211_KEY_CIPHER1	0x2000	/* cipher-specific action 1 */
-#define IEEE80211_KEY_EMPTY     0x0000
-	ieee80211_keyix	wk_keyix;	/* h/w key index */
-	ieee80211_keyix	wk_rxkeyix;	/* optional h/w rx key index */
-	uint8_t		wk_key[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE];
-#define	wk_txmic	wk_key+IEEE80211_KEYBUF_SIZE+0	/* XXX can't () right */
-#define	wk_rxmic	wk_key+IEEE80211_KEYBUF_SIZE+8	/* XXX can't () right */
-					/* key receive sequence counter */
-	uint64_t	wk_keyrsc[IEEE80211_TID_SIZE];
-	uint64_t	wk_keytsc;	/* key transmit sequence counter */
-	const struct ieee80211_cipher *wk_cipher;
-	//void		*wk_private;	/* private cipher state */
-	//uint8_t		wk_macaddr[IEEE80211_ADDR_LEN]; //JLU: no need ...
-};
-#define	IEEE80211_KEY_COMMON 		/* common flags passed in by apps */\
-	(IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV | IEEE80211_KEY_GROUP)
-#define	IEEE80211_KEY_DEVICE		/* flags owned by device driver */\
-	(IEEE80211_KEY_DEVKEY|IEEE80211_KEY_CIPHER0|IEEE80211_KEY_CIPHER1)
-
-#define	IEEE80211_KEY_SWCRYPT \
-	(IEEE80211_KEY_SWENCRYPT | IEEE80211_KEY_SWDECRYPT)
-#define	IEEE80211_KEY_SWMIC	(IEEE80211_KEY_SWENMIC | IEEE80211_KEY_SWDEMIC)
-
-//#define	IEEE80211_KEYIX_NONE	((ieee80211_keyix) -1)
-
-/*
- * NB: these values are ordered carefully; there are lots of
- * of implications in any reordering.  Beware that 4 is used
- * only to indicate h/w TKIP MIC support in driver capabilities;
- * there is no separate cipher support (it's rolled into the
- * TKIP cipher support).
- */
-#define	IEEE80211_CIPHER_NONE		0	/* pseudo value */
-#define	IEEE80211_CIPHER_TKIP		1
-#define	IEEE80211_CIPHER_AES_OCB	2
-#define	IEEE80211_CIPHER_AES_CCM	3
-#define	IEEE80211_CIPHER_TKIPMIC	4	/* TKIP MIC capability */
-#define	IEEE80211_CIPHER_CKIP		5
-#define	IEEE80211_CIPHER_WEP		6
-#define	IEEE80211_CIPHER_WEP40		7
-#define	IEEE80211_CIPHER_WEP104		8
-
-
-#define	IEEE80211_CIPHER_MAX		(IEEE80211_CIPHER_NONE+2)
-
-/* capability bits in ic_cryptocaps/iv_cryptocaps */
-#define	IEEE80211_CRYPTO_NONE		(1<<IEEE80211_CIPHER_NONE)
-#define	IEEE80211_CRYPTO_WEP		(1<<IEEE80211_CIPHER_WEP)
-#define	IEEE80211_CRYPTO_WEP40		(1<<IEEE80211_CIPHER_WEP40)
-#define	IEEE80211_CRYPTO_WEP104	(1<<IEEE80211_CIPHER_WEP104)
-#define	IEEE80211_CRYPTO_TKIP		(1<<IEEE80211_CIPHER_TKIP)
-#define	IEEE80211_CRYPTO_AES_OCB	(1<<IEEE80211_CIPHER_AES_OCB)
-#define	IEEE80211_CRYPTO_AES_CCM	(1<<IEEE80211_CIPHER_AES_CCM)
-#define	IEEE80211_CRYPTO_TKIPMIC	(1<<IEEE80211_CIPHER_TKIPMIC)
-#define	IEEE80211_CRYPTO_CKIP		(1<<IEEE80211_CIPHER_CKIP)
-
-struct ieee80211_cipher {
-	u_int	ic_cipher;		/* IEEE80211_CIPHER_* */
-	u_int	ic_header;		/* size of privacy header (bytes) */
-	u_int	ic_trailer;		/* size of privacy trailer (bytes) */
-	u_int	ic_miclen;		/* size of mic trailer (bytes) */
-//	int	(*ic_setkey)(struct ieee80211_key *);
-	int	(*ic_encap)(struct ieee80211_key *, esf_buf_t *, uint8_t);
-	int	(*ic_decap)(struct ieee80211_key *, esf_buf_t *, int);
-#ifdef EAGLE_SW_MIC
-	int	(*ic_enmic)(struct ieee80211_key *, esf_buf_t *, int);
-	int	(*ic_demic)(struct ieee80211_key *, esf_buf_t *, int);
-#endif /* EAGLE_SW_CRYPTO */
-};
-
-struct ieee80211com;
-struct ieee80211_conn;
-
-#define	IEEE80211_KEY_UNDEFINED(k) \
-	((k)->wk_cipher == &ieee80211_cipher_none)
-
-struct ieee80211_key *ieee80211_crypto_encap(struct ieee80211_conn *,
-		esf_buf *);
-
-struct ieee80211_key *ieee80211_crypto_decap(struct ieee80211_conn *,
-		esf_buf *, int);
-
-#if 0 //H/W MIC
-/*
- * Check and remove any MIC.
- */
-static INLINE int
-ieee80211_crypto_demic(struct ieee80211vap *vap, struct ieee80211_key *k,
-	esf_buf *m, int force)
-{
-	const struct ieee80211_cipher *cip = k->wk_cipher;
-	return (cip->ic_miclen > 0 ? cip->ic_demic(k, m, force) : 1);
-}
-
-/*
- * Add any MIC.
- */
-static INLINE int
-ieee80211_crypto_enmic(struct ieee80211vap *vap,
-	struct ieee80211_key *k, esf_buf *m, int force)
-{
-	const struct ieee80211_cipher *cip = k->wk_cipher;
-	return (cip->ic_miclen > 0 ? cip->ic_enmic(k, m, force) : 1);
-}
-#endif //0000
-
-/* 
- * Setup crypto support for a device/shared instance.
- */
-void ieee80211_crypto_attach(struct ieee80211com *ic);
-
-/* 
- * Reset key state to an unused state.  The crypto
- * key allocation mechanism insures other state (e.g.
- * key data) is properly setup before a key is used.
- */
-static inline void
-ieee80211_crypto_resetkey(struct ieee80211_key *k)
-{
-	k->wk_cipher = NULL;
-	k->wk_flags = IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV;
-}
-
-/*
- * Crypt-related notification methods.
- */
-//void	ieee80211_notify_replay_failure(const struct ieee80211_frame *, const struct ieee80211_key *,
-//		uint64_t rsc, int tid);
-//void	ieee80211_notify_michael_failure(const struct ieee80211_frame *, u_int keyix);
-
-#endif /* _NET80211_IEEE80211_CRYPTO_H_ */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/ieee802_11_defs.h b/tools/sdk/include/wpa_supplicant/wpa/ieee802_11_defs.h
deleted file mode 100644
index 4881e39a01a..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/ieee802_11_defs.h
+++ /dev/null
@@ -1,607 +0,0 @@
-/*
- * IEEE 802.11 Frame type definitions
- * Copyright (c) 2002-2009, Jouni Malinen <j@w1.fi>
- * Copyright (c) 2007-2008 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef IEEE802_11_DEFS_H
-#define IEEE802_11_DEFS_H
-
-/* IEEE 802.11 defines */
-
-#define WLAN_FC_PVER		0x0003
-#define WLAN_FC_TODS		0x0100
-#define WLAN_FC_FROMDS		0x0200
-#define WLAN_FC_MOREFRAG	0x0400
-#define WLAN_FC_RETRY		0x0800
-#define WLAN_FC_PWRMGT		0x1000
-#define WLAN_FC_MOREDATA	0x2000
-#define WLAN_FC_ISWEP		0x4000
-#define WLAN_FC_ORDER		0x8000
-
-#define WLAN_FC_GET_TYPE(fc)	(((fc) & 0x000c) >> 2)
-#define WLAN_FC_GET_STYPE(fc)	(((fc) & 0x00f0) >> 4)
-
-#define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
-#define WLAN_GET_SEQ_SEQ(seq) \
-	(((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
-
-#define WLAN_FC_TYPE_MGMT		0
-#define WLAN_FC_TYPE_CTRL		1
-#define WLAN_FC_TYPE_DATA		2
-
-/* management */
-#define WLAN_FC_STYPE_ASSOC_REQ		0
-#define WLAN_FC_STYPE_ASSOC_RESP	1
-#define WLAN_FC_STYPE_REASSOC_REQ	2
-#define WLAN_FC_STYPE_REASSOC_RESP	3
-#define WLAN_FC_STYPE_PROBE_REQ		4
-#define WLAN_FC_STYPE_PROBE_RESP	5
-#define WLAN_FC_STYPE_BEACON		8
-#define WLAN_FC_STYPE_ATIM		9
-#define WLAN_FC_STYPE_DISASSOC		10
-#define WLAN_FC_STYPE_AUTH		11
-#define WLAN_FC_STYPE_DEAUTH		12
-#define WLAN_FC_STYPE_ACTION		13
-
-/* control */
-#define WLAN_FC_STYPE_PSPOLL		10
-#define WLAN_FC_STYPE_RTS		11
-#define WLAN_FC_STYPE_CTS		12
-#define WLAN_FC_STYPE_ACK		13
-#define WLAN_FC_STYPE_CFEND		14
-#define WLAN_FC_STYPE_CFENDACK		15
-
-/* data */
-#define WLAN_FC_STYPE_DATA		0
-#define WLAN_FC_STYPE_DATA_CFACK	1
-#define WLAN_FC_STYPE_DATA_CFPOLL	2
-#define WLAN_FC_STYPE_DATA_CFACKPOLL	3
-#define WLAN_FC_STYPE_NULLFUNC		4
-#define WLAN_FC_STYPE_CFACK		5
-#define WLAN_FC_STYPE_CFPOLL		6
-#define WLAN_FC_STYPE_CFACKPOLL		7
-#define WLAN_FC_STYPE_QOS_DATA		8
-
-/* Authentication algorithms */
-#define WLAN_AUTH_OPEN			0
-#define WLAN_AUTH_SHARED_KEY		1
-#define WLAN_AUTH_FT			2
-#define WLAN_AUTH_LEAP			128
-
-#define WLAN_AUTH_CHALLENGE_LEN 128
-
-#define WLAN_CAPABILITY_ESS BIT(0)
-#define WLAN_CAPABILITY_IBSS BIT(1)
-#define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
-#define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3)
-#define WLAN_CAPABILITY_PRIVACY BIT(4)
-#define WLAN_CAPABILITY_SHORT_PREAMBLE BIT(5)
-#define WLAN_CAPABILITY_PBCC BIT(6)
-#define WLAN_CAPABILITY_CHANNEL_AGILITY BIT(7)
-#define WLAN_CAPABILITY_SPECTRUM_MGMT BIT(8)
-#define WLAN_CAPABILITY_SHORT_SLOT_TIME BIT(10)
-#define WLAN_CAPABILITY_DSSS_OFDM BIT(13)
-
-/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */
-#define WLAN_STATUS_SUCCESS 0
-#define WLAN_STATUS_UNSPECIFIED_FAILURE 1
-#define WLAN_STATUS_CAPS_UNSUPPORTED 10
-#define WLAN_STATUS_REASSOC_NO_ASSOC 11
-#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12
-#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13
-#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14
-#define WLAN_STATUS_CHALLENGE_FAIL 15
-#define WLAN_STATUS_AUTH_TIMEOUT 16
-#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17
-#define WLAN_STATUS_ASSOC_DENIED_RATES 18
-/* IEEE 802.11b */
-#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19
-#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20
-#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21
-/* IEEE 802.11h */
-#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22
-#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23
-#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24
-/* IEEE 802.11g */
-#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25
-#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26
-#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27
-#define WLAN_STATUS_R0KH_UNREACHABLE 28
-/* IEEE 802.11w */
-#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30
-#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31
-#define WLAN_STATUS_UNSPECIFIED_QOS_FAILURE 32
-#define WLAN_STATUS_REQUEST_DECLINED 37
-#define WLAN_STATUS_INVALID_PARAMETERS 38
-/* IEEE 802.11i */
-#define WLAN_STATUS_INVALID_IE 40
-#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41
-#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42
-#define WLAN_STATUS_AKMP_NOT_VALID 43
-#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44
-#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45
-#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46
-#define WLAN_STATUS_TS_NOT_CREATED 47
-#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48
-#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49
-#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50
-#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51
-/* IEEE 802.11r */
-#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52
-#define WLAN_STATUS_INVALID_PMKID 53
-#define WLAN_STATUS_INVALID_MDIE 54
-#define WLAN_STATUS_INVALID_FTIE 55
-
-/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */
-#define WLAN_REASON_UNSPECIFIED 1
-#define WLAN_REASON_PREV_AUTH_NOT_VALID 2
-#define WLAN_REASON_DEAUTH_LEAVING 3
-#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4
-#define WLAN_REASON_DISASSOC_AP_BUSY 5
-#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6
-#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7
-#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8
-#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9
-/* IEEE 802.11h */
-#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10
-#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11
-/* IEEE 802.11i */
-#define WLAN_REASON_INVALID_IE 13
-#define WLAN_REASON_MICHAEL_MIC_FAILURE 14
-#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15
-#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16
-#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17
-#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18
-#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19
-#define WLAN_REASON_AKMP_NOT_VALID 20
-#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21
-#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22
-#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23
-#define WLAN_REASON_CIPHER_SUITE_REJECTED 24
-
-
-/* Information Element IDs */
-#define WLAN_EID_SSID 0
-#define WLAN_EID_SUPP_RATES 1
-#define WLAN_EID_FH_PARAMS 2
-#define WLAN_EID_DS_PARAMS 3
-#define WLAN_EID_CF_PARAMS 4
-#define WLAN_EID_TIM 5
-#define WLAN_EID_IBSS_PARAMS 6
-#define WLAN_EID_COUNTRY 7
-#define WLAN_EID_CHALLENGE 16
-/* EIDs defined by IEEE 802.11h - START */
-#define WLAN_EID_PWR_CONSTRAINT 32
-#define WLAN_EID_PWR_CAPABILITY 33
-#define WLAN_EID_TPC_REQUEST 34
-#define WLAN_EID_TPC_REPORT 35
-#define WLAN_EID_SUPPORTED_CHANNELS 36
-#define WLAN_EID_CHANNEL_SWITCH 37
-#define WLAN_EID_MEASURE_REQUEST 38
-#define WLAN_EID_MEASURE_REPORT 39
-#define WLAN_EID_QUITE 40
-#define WLAN_EID_IBSS_DFS 41
-/* EIDs defined by IEEE 802.11h - END */
-#define WLAN_EID_ERP_INFO 42
-#define WLAN_EID_HT_CAP 45
-#define WLAN_EID_RSN 48
-#define WLAN_EID_EXT_SUPP_RATES 50
-#define WLAN_EID_MOBILITY_DOMAIN 54
-#define WLAN_EID_FAST_BSS_TRANSITION 55
-#define WLAN_EID_TIMEOUT_INTERVAL 56
-#define WLAN_EID_RIC_DATA 57
-#define WLAN_EID_HT_OPERATION 61
-#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62
-#define WLAN_EID_20_40_BSS_COEXISTENCE 72
-#define WLAN_EID_20_40_BSS_INTOLERANT 73
-#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74
-#define WLAN_EID_MMIE 76
-#define WLAN_EID_VENDOR_SPECIFIC 221
-
-
-/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */
-#define WLAN_ACTION_SPECTRUM_MGMT 0
-#define WLAN_ACTION_QOS 1
-#define WLAN_ACTION_DLS 2
-#define WLAN_ACTION_BLOCK_ACK 3
-#define WLAN_ACTION_PUBLIC 4
-#define WLAN_ACTION_RADIO_MEASUREMENT 5
-#define WLAN_ACTION_FT 6
-#define WLAN_ACTION_HT 7
-#define WLAN_ACTION_SA_QUERY 8
-#define WLAN_ACTION_WMM 17 /* WMM Specification 1.1 */
-
-/* SA Query Action frame (IEEE 802.11w/D8.0, 7.4.9) */
-#define WLAN_SA_QUERY_REQUEST 0
-#define WLAN_SA_QUERY_RESPONSE 1
-
-#define WLAN_SA_QUERY_TR_ID_LEN 2
-
-/* Timeout Interval Type */
-#define WLAN_TIMEOUT_REASSOC_DEADLINE 1
-#define WLAN_TIMEOUT_KEY_LIFETIME 2
-#define WLAN_TIMEOUT_ASSOC_COMEBACK 3
-
-
-#ifdef _MSC_VER
-#pragma pack(push, 1)
-#endif /* _MSC_VER */
-
-struct ieee80211_hdr {
-	le16 frame_control;
-	le16 duration_id;
-	u8 addr1[6];
-	u8 addr2[6];
-	u8 addr3[6];
-	le16 seq_ctrl;
-	/* followed by 'u8 addr4[6];' if ToDS and FromDS is set in data frame
-	 */
-} STRUCT_PACKED;
-
-#define IEEE80211_DA_FROMDS addr1
-#define IEEE80211_BSSID_FROMDS addr2
-#define IEEE80211_SA_FROMDS addr3
-
-#define IEEE80211_HDRLEN (sizeof(struct ieee80211_hdr))
-
-#define IEEE80211_FC(type, stype) host_to_le16((type << 2) | (stype << 4))
-
-struct ieee80211_mgmt {
-	le16 frame_control;
-	le16 duration;
-	u8 da[6];
-	u8 sa[6];
-	u8 bssid[6];
-	le16 seq_ctrl;
-	union {
-		struct {
-			le16 auth_alg;
-			le16 auth_transaction;
-			le16 status_code;
-			/* possibly followed by Challenge text */
-			u8 variable[0];
-		} STRUCT_PACKED auth;
-		struct {
-			le16 reason_code;
-		} STRUCT_PACKED deauth;
-		struct {
-			le16 capab_info;
-			le16 listen_interval;
-			/* followed by SSID and Supported rates */
-			u8 variable[0];
-		} STRUCT_PACKED assoc_req;
-		struct {
-			le16 capab_info;
-			le16 status_code;
-			le16 aid;
-			/* followed by Supported rates */
-			u8 variable[0];
-		} STRUCT_PACKED assoc_resp, reassoc_resp;
-		struct {
-			le16 capab_info;
-			le16 listen_interval;
-			u8 current_ap[6];
-			/* followed by SSID and Supported rates */
-			u8 variable[0];
-		} STRUCT_PACKED reassoc_req;
-		struct {
-			le16 reason_code;
-		} STRUCT_PACKED disassoc;
-		struct {
-			u8 timestamp[8];
-			le16 beacon_int;
-			le16 capab_info;
-			/* followed by some of SSID, Supported rates,
-			 * FH Params, DS Params, CF Params, IBSS Params, TIM */
-			u8 variable[0];
-		} STRUCT_PACKED beacon;
-		struct {
-			/* only variable items: SSID, Supported rates */
-			u8 variable[0];
-		} STRUCT_PACKED probe_req;
-		struct {
-			u8 timestamp[8];
-			le16 beacon_int;
-			le16 capab_info;
-			/* followed by some of SSID, Supported rates,
-			 * FH Params, DS Params, CF Params, IBSS Params */
-			u8 variable[0];
-		} STRUCT_PACKED probe_resp;
-		struct {
-			u8 category;
-			union {
-				struct {
-					u8 action_code;
-					u8 dialog_token;
-					u8 status_code;
-					u8 variable[0];
-				} STRUCT_PACKED wmm_action;
-				struct{
-					u8 action_code;
-					u8 element_id;
-					u8 length;
-					u8 switch_mode;
-					u8 new_chan;
-					u8 switch_count;
-				} STRUCT_PACKED chan_switch;
-				struct {
-					u8 action;
-					u8 sta_addr[ETH_ALEN];
-					u8 target_ap_addr[ETH_ALEN];
-					u8 variable[0]; /* FT Request */
-				} STRUCT_PACKED ft_action_req;
-				struct {
-					u8 action;
-					u8 sta_addr[ETH_ALEN];
-					u8 target_ap_addr[ETH_ALEN];
-					le16 status_code;
-					u8 variable[0]; /* FT Request */
-				} STRUCT_PACKED ft_action_resp;
-				struct {
-					u8 action;
-					u8 trans_id[WLAN_SA_QUERY_TR_ID_LEN];
-				} STRUCT_PACKED sa_query_req;
-				struct {
-					u8 action; /* */
-					u8 trans_id[WLAN_SA_QUERY_TR_ID_LEN];
-				} STRUCT_PACKED sa_query_resp;
-			} u;
-		} STRUCT_PACKED action;
-	} u;
-} STRUCT_PACKED;
-
-
-struct ieee80211_ht_capabilities {
-	le16 ht_capabilities_info;
-	u8 a_mpdu_params;
-	u8 supported_mcs_set[16];
-	le16 ht_extended_capabilities;
-	le32 tx_bf_capability_info;
-	u8 asel_capabilities;
-} STRUCT_PACKED;
-
-
-struct ieee80211_ht_operation {
-	u8 control_chan;
-	u8 ht_param;
-	le16 operation_mode;
-	le16 stbc_param;
-	u8 basic_set[16];
-} STRUCT_PACKED;
-
-#ifdef _MSC_VER
-#pragma pack(pop)
-#endif /* _MSC_VER */
-
-#define ERP_INFO_NON_ERP_PRESENT BIT(0)
-#define ERP_INFO_USE_PROTECTION BIT(1)
-#define ERP_INFO_BARKER_PREAMBLE_MODE BIT(2)
-
-
-#define HT_CAP_INFO_LDPC_CODING_CAP		((u16) BIT(0))
-#define HT_CAP_INFO_SUPP_CHANNEL_WIDTH_SET	((u16) BIT(1))
-#define HT_CAP_INFO_SMPS_MASK			((u16) (BIT(2) | BIT(3)))
-#define HT_CAP_INFO_SMPS_STATIC			((u16) 0)
-#define HT_CAP_INFO_SMPS_DYNAMIC		((u16) BIT(2))
-#define HT_CAP_INFO_SMPS_DISABLED		((u16) (BIT(2) | BIT(3)))
-#define HT_CAP_INFO_GREEN_FIELD			((u16) BIT(4))
-#define HT_CAP_INFO_SHORT_GI20MHZ		((u16) BIT(5))
-#define HT_CAP_INFO_SHORT_GI40MHZ		((u16) BIT(6))
-#define HT_CAP_INFO_TX_STBC			((u16) BIT(7))
-#define HT_CAP_INFO_RX_STBC_MASK		((u16) (BIT(8) | BIT(9)))
-#define HT_CAP_INFO_RX_STBC_1			((u16) BIT(8))
-#define HT_CAP_INFO_RX_STBC_12			((u16) BIT(9))
-#define HT_CAP_INFO_RX_STBC_123			((u16) (BIT(8) | BIT(9)))
-#define HT_CAP_INFO_DELAYED_BA			((u16) BIT(10))
-#define HT_CAP_INFO_MAX_AMSDU_SIZE		((u16) BIT(11))
-#define HT_CAP_INFO_DSSS_CCK40MHZ		((u16) BIT(12))
-#define HT_CAP_INFO_PSMP_SUPP			((u16) BIT(13))
-#define HT_CAP_INFO_40MHZ_INTOLERANT		((u16) BIT(14))
-#define HT_CAP_INFO_LSIG_TXOP_PROTECT_SUPPORT	((u16) BIT(15))
-
-
-#define EXT_HT_CAP_INFO_PCO			((u16) BIT(0))
-#define EXT_HT_CAP_INFO_TRANS_TIME_OFFSET	1
-#define EXT_HT_CAP_INFO_MCS_FEEDBACK_OFFSET	8
-#define EXT_HT_CAP_INFO_HTC_SUPPORTED		((u16) BIT(10))
-#define EXT_HT_CAP_INFO_RD_RESPONDER		((u16) BIT(11))
-
-
-#define TX_BEAMFORM_CAP_TXBF_CAP ((u32) BIT(0))
-#define TX_BEAMFORM_CAP_RX_STAGGERED_SOUNDING_CAP ((u32) BIT(1))
-#define TX_BEAMFORM_CAP_TX_STAGGERED_SOUNDING_CAP ((u32) BIT(2))
-#define TX_BEAMFORM_CAP_RX_ZLF_CAP ((u32) BIT(3))
-#define TX_BEAMFORM_CAP_TX_ZLF_CAP ((u32) BIT(4))
-#define TX_BEAMFORM_CAP_IMPLICIT_ZLF_CAP ((u32) BIT(5))
-#define TX_BEAMFORM_CAP_CALIB_OFFSET 6
-#define TX_BEAMFORM_CAP_EXPLICIT_CSI_TXBF_CAP ((u32) BIT(8))
-#define TX_BEAMFORM_CAP_EXPLICIT_UNCOMPR_STEERING_MATRIX_CAP ((u32) BIT(9))
-#define TX_BEAMFORM_CAP_EXPLICIT_BF_CSI_FEEDBACK_CAP ((u32) BIT(10))
-#define TX_BEAMFORM_CAP_EXPLICIT_BF_CSI_FEEDBACK_OFFSET 11
-#define TX_BEAMFORM_CAP_EXPLICIT_UNCOMPR_STEERING_MATRIX_FEEDBACK_OFFSET 13
-#define TX_BEAMFORM_CAP_EXPLICIT_COMPRESSED_STEERING_MATRIX_FEEDBACK_OFFSET 15
-#define TX_BEAMFORM_CAP_MINIMAL_GROUPING_OFFSET 17
-#define TX_BEAMFORM_CAP_CSI_NUM_BEAMFORMER_ANT_OFFSET 19
-#define TX_BEAMFORM_CAP_UNCOMPRESSED_STEERING_MATRIX_BEAMFORMER_ANT_OFFSET 21
-#define TX_BEAMFORM_CAP_COMPRESSED_STEERING_MATRIX_BEAMFORMER_ANT_OFFSET 23
-#define TX_BEAMFORM_CAP_SCI_MAX_OF_ROWS_BEANFORMER_SUPPORTED_OFFSET 25
-
-
-#define ASEL_CAPABILITY_ASEL_CAPABLE ((u8) BIT(0))
-#define ASEL_CAPABILITY_EXPLICIT_CSI_FEEDBACK_BASED_TX_AS_CAP ((u8) BIT(1))
-#define ASEL_CAPABILITY_ANT_INDICES_FEEDBACK_BASED_TX_AS_CAP ((u8) BIT(2))
-#define ASEL_CAPABILITY_EXPLICIT_CSI_FEEDBACK_CAP ((u8) BIT(3))
-#define ASEL_CAPABILITY_ANT_INDICES_FEEDBACK_CAP ((u8) BIT(4))
-#define ASEL_CAPABILITY_RX_AS_CAP ((u8) BIT(5))
-#define ASEL_CAPABILITY_TX_SOUND_PPDUS_CAP ((u8) BIT(6))
-
-#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK	((u8) BIT(0) | BIT(1))
-#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE		((u8) BIT(0))
-#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW		((u8) BIT(0) | BIT(1))
-#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH		((u8) BIT(2))
-#define HT_INFO_HT_PARAM_RIFS_MODE			((u8) BIT(3))
-#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY		((u8) BIT(4))
-#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY	((u8) BIT(5))
-
-
-#define OP_MODE_PURE                    0
-#define OP_MODE_MAY_BE_LEGACY_STAS      1
-#define OP_MODE_20MHZ_HT_STA_ASSOCED    2
-#define OP_MODE_MIXED                   3
-
-#define HT_INFO_OPERATION_MODE_OP_MODE_MASK	\
-		((le16) (0x0001 | 0x0002))
-#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET		0
-#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT	((u8) BIT(2))
-#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT	((u8) BIT(3))
-#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT	((u8) BIT(4))
-
-#define HT_INFO_STBC_PARAM_DUAL_BEACON			((u16) BIT(6))
-#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT		((u16) BIT(7))
-#define HT_INFO_STBC_PARAM_SECONDARY_BCN		((u16) BIT(8))
-#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED	((u16) BIT(9))
-#define HT_INFO_STBC_PARAM_PCO_ACTIVE			((u16) BIT(10))
-#define HT_INFO_STBC_PARAM_PCO_PHASE			((u16) BIT(11))
-
-
-#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs)
-				* 00:50:F2 */
-#define WPA_IE_VENDOR_TYPE 0x0050f201
-#define WPS_IE_VENDOR_TYPE 0x0050f204
-
-#define WMM_OUI_TYPE 2
-#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
-#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
-#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
-#define WMM_VERSION 1
-
-#define WMM_ACTION_CODE_ADDTS_REQ 0
-#define WMM_ACTION_CODE_ADDTS_RESP 1
-#define WMM_ACTION_CODE_DELTS 2
-
-#define WMM_ADDTS_STATUS_ADMISSION_ACCEPTED 0
-#define WMM_ADDTS_STATUS_INVALID_PARAMETERS 1
-/* 2 - Reserved */
-#define WMM_ADDTS_STATUS_REFUSED 3
-/* 4-255 - Reserved */
-
-/* WMM TSPEC Direction Field Values */
-#define WMM_TSPEC_DIRECTION_UPLINK 0
-#define WMM_TSPEC_DIRECTION_DOWNLINK 1
-/* 2 - Reserved */
-#define WMM_TSPEC_DIRECTION_BI_DIRECTIONAL 3
-
-/*
- * WMM Information Element (used in (Re)Association Request frames; may also be
- * used in Beacon frames)
- */
-struct wmm_information_element {
-	/* Element ID: 221 (0xdd); Length: 7 */
-	/* required fields for WMM version 1 */
-	u8 oui[3]; /* 00:50:f2 */
-	u8 oui_type; /* 2 */
-	u8 oui_subtype; /* 0 */
-	u8 version; /* 1 for WMM version 1.0 */
-	u8 qos_info; /* AP/STA specific QoS info */
-
-} STRUCT_PACKED;
-
-#define WMM_AC_AIFSN_MASK 0x0f
-#define WMM_AC_AIFNS_SHIFT 0
-#define WMM_AC_ACM 0x10
-#define WMM_AC_ACI_MASK 0x60
-#define WMM_AC_ACI_SHIFT 5
-
-#define WMM_AC_ECWMIN_MASK 0x0f
-#define WMM_AC_ECWMIN_SHIFT 0
-#define WMM_AC_ECWMAX_MASK 0xf0
-#define WMM_AC_ECWMAX_SHIFT 4
-
-struct wmm_ac_parameter {
-	u8 aci_aifsn; /* AIFSN, ACM, ACI */
-	u8 cw; /* ECWmin, ECWmax (CW = 2^ECW - 1) */
-	le16 txop_limit;
-}  STRUCT_PACKED;
-
-/*
- * WMM Parameter Element (used in Beacon, Probe Response, and (Re)Association
- * Response frmaes)
- */
-struct wmm_parameter_element {
-	/* Element ID: 221 (0xdd); Length: 24 */
-	/* required fields for WMM version 1 */
-	u8 oui[3]; /* 00:50:f2 */
-	u8 oui_type; /* 2 */
-	u8 oui_subtype; /* 1 */
-	u8 version; /* 1 for WMM version 1.0 */
-	u8 qos_info; /* AP/STA specif QoS info */
-	u8 reserved; /* 0 */
-	struct wmm_ac_parameter ac[4]; /* AC_BE, AC_BK, AC_VI, AC_VO */
-
-} STRUCT_PACKED;
-
-/* WMM TSPEC Element */
-struct wmm_tspec_element {
-	u8 eid; /* 221 = 0xdd */
-	u8 length; /* 6 + 55 = 61 */
-	u8 oui[3]; /* 00:50:f2 */
-	u8 oui_type; /* 2 */
-	u8 oui_subtype; /* 2 */
-	u8 version; /* 1 */
-	/* WMM TSPEC body (55 octets): */
-	u8 ts_info[3];
-	le16 nominal_msdu_size;
-	le16 maximum_msdu_size;
-	le32 minimum_service_interval;
-	le32 maximum_service_interval;
-	le32 inactivity_interval;
-	le32 suspension_interval;
-	le32 service_start_time;
-	le32 minimum_data_rate;
-	le32 mean_data_rate;
-	le32 peak_data_rate;
-	le32 maximum_burst_size;
-	le32 delay_bound;
-	le32 minimum_phy_rate;
-	le16 surplus_bandwidth_allowance;
-	le16 medium_time;
-} STRUCT_PACKED;
-
-
-/* Access Categories / ACI to AC coding */
-enum {
-	WMM_AC_BE = 0 /* Best Effort */,
-	WMM_AC_BK = 1 /* Background */,
-	WMM_AC_VI = 2 /* Video */,
-	WMM_AC_VO = 3 /* Voice */
-};
-
-
-#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */
-
-#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */
-
-/* cipher suite selectors */
-#define WLAN_CIPHER_SUITE_USE_GROUP	0x000FAC00
-#define WLAN_CIPHER_SUITE_WEP40		0x000FAC01
-#define WLAN_CIPHER_SUITE_TKIP		0x000FAC02
-/* reserved: 				0x000FAC03 */
-#define WLAN_CIPHER_SUITE_CCMP		0x000FAC04
-#define WLAN_CIPHER_SUITE_WEP104	0x000FAC05
-#define WLAN_CIPHER_SUITE_AES_CMAC	0x000FAC06
-
-/* AKM suite selectors */
-#define WLAN_AKM_SUITE_8021X		0x000FAC01
-#define WLAN_AKM_SUITE_PSK		0x000FAC02
-
-#endif /* IEEE802_11_DEFS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/ieee802_1x.h b/tools/sdk/include/wpa_supplicant/wpa/ieee802_1x.h
deleted file mode 100644
index e10ff7b3109..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/ieee802_1x.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * hostapd / IEEE 802.1X-2004 Authenticator
- * Copyright (c) 2002-2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef IEEE802_1X_H
-#define IEEE802_1X_H
-
-struct hostapd_data;
-struct sta_info;
-struct eapol_state_machine;
-struct hostapd_config;
-struct hostapd_bss_config;
-struct hostapd_radius_attr;
-struct radius_msg;
-
-
-void ieee802_1x_receive(struct hostapd_data *hapd, const u8 *sa, const u8 *buf,
-			size_t len);
-
-#if 0
-void ieee802_1x_new_station(struct hostapd_data *hapd, struct sta_info *sta);
-void ieee802_1x_free_station(struct sta_info *sta);
-
-void ieee802_1x_tx_key(struct hostapd_data *hapd, struct sta_info *sta);
-void ieee802_1x_abort_auth(struct hostapd_data *hapd, struct sta_info *sta);
-void ieee802_1x_set_sta_authorized(struct hostapd_data *hapd,
-				   struct sta_info *sta, int authorized);
-void ieee802_1x_dump_state(FILE *f, const char *prefix, struct sta_info *sta);
-int ieee802_1x_init(struct hostapd_data *hapd);
-void ieee802_1x_deinit(struct hostapd_data *hapd);
-int ieee802_1x_tx_status(struct hostapd_data *hapd, struct sta_info *sta,
-			 const u8 *buf, size_t len, int ack);
-int ieee802_1x_eapol_tx_status(struct hostapd_data *hapd, struct sta_info *sta,
-			       const u8 *data, int len, int ack);
-u8 * ieee802_1x_get_identity(struct eapol_state_machine *sm, size_t *len);
-u8 * ieee802_1x_get_radius_class(struct eapol_state_machine *sm, size_t *len,
-				 int idx);
-struct wpabuf * ieee802_1x_get_radius_cui(struct eapol_state_machine *sm);
-const u8 * ieee802_1x_get_key(struct eapol_state_machine *sm, size_t *len);
-void ieee802_1x_notify_port_enabled(struct eapol_state_machine *sm,
-				    int enabled);
-void ieee802_1x_notify_port_valid(struct eapol_state_machine *sm,
-				  int valid);
-void ieee802_1x_notify_pre_auth(struct eapol_state_machine *sm, int pre_auth);
-int ieee802_1x_get_mib(struct hostapd_data *hapd, char *buf, size_t buflen);
-int ieee802_1x_get_mib_sta(struct hostapd_data *hapd, struct sta_info *sta,
-			   char *buf, size_t buflen);
-void hostapd_get_ntp_timestamp(u8 *buf);
-char *eap_type_text(u8 type);
-
-const char *radius_mode_txt(struct hostapd_data *hapd);
-int radius_sta_rate(struct hostapd_data *hapd, struct sta_info *sta);
-
-int add_common_radius_attr(struct hostapd_data *hapd,
-			   struct hostapd_radius_attr *req_attr,
-			   struct sta_info *sta,
-			   struct radius_msg *msg);
-#endif
-
-#endif /* IEEE802_1X_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/includes.h b/tools/sdk/include/wpa_supplicant/wpa/includes.h
deleted file mode 100644
index 993bc49941e..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/includes.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * wpa_supplicant/hostapd - Default include files
- * Copyright (c) 2005-2006, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- *
- * This header file is included into all C files so that commonly used header
- * files can be selected with OS specific ifdef blocks in one place instead of
- * having to have OS/C library specific selection in many files.
- */
-
-#ifndef INCLUDES_H
-#define INCLUDES_H
-
-/* Include possible build time configuration before including anything else */
-//#include "build_config.h"  //don't need anymore
-
-//#include <stdlib.h>
-//#include <stdio.h>
-//#include <string.h>
-//#include <ctype.h>
-//#include <time.h>
-
-#endif /* INCLUDES_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/list.h b/tools/sdk/include/wpa_supplicant/wpa/list.h
deleted file mode 100644
index a67a04966c6..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/list.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Doubly-linked list
- * Copyright (c) 2009, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef LIST_H
-#define LIST_H
-
-#include <stddef.h>
-
-/**
- * struct dl_list - Doubly-linked list
- */
-struct dl_list {
-	struct dl_list *next;
-	struct dl_list *prev;
-};
-
-static inline void dl_list_init(struct dl_list *list)
-{
-	list->next = list;
-	list->prev = list;
-}
-
-static inline void dl_list_add(struct dl_list *list, struct dl_list *item)
-{
-	item->next = list->next;
-	item->prev = list;
-	list->next->prev = item;
-	list->next = item;
-}
-
-static inline void dl_list_add_tail(struct dl_list *list, struct dl_list *item)
-{
-	dl_list_add(list->prev, item);
-}
-
-static inline void dl_list_del(struct dl_list *item)
-{
-	item->next->prev = item->prev;
-	item->prev->next = item->next;
-	item->next = NULL;
-	item->prev = NULL;
-}
-
-static inline int dl_list_empty(struct dl_list *list)
-{
-	return list->next == list;
-}
-
-static inline unsigned int dl_list_len(struct dl_list *list)
-{
-	struct dl_list *item;
-	int count = 0;
-	for (item = list->next; item != list; item = item->next)
-		count++;
-	return count;
-}
-
-#ifndef offsetof
-#define offsetof(type, member) ((long) &((type *) 0)->member)
-#endif
-
-#define dl_list_entry(item, type, member) \
-	((type *) ((char *) item - offsetof(type, member)))
-
-#define dl_list_first(list, type, member) \
-	(dl_list_empty((list)) ? NULL : \
-	 dl_list_entry((list)->next, type, member))
-
-#define dl_list_last(list, type, member) \
-	(dl_list_empty((list)) ? NULL : \
-	 dl_list_entry((list)->prev, type, member))
-
-#define dl_list_for_each(item, list, type, member) \
-	for (item = dl_list_entry((list)->next, type, member); \
-	     &item->member != (list); \
-	     item = dl_list_entry(item->member.next, type, member))
-
-#define dl_list_for_each_safe(item, n, list, type, member) \
-	for (item = dl_list_entry((list)->next, type, member), \
-		     n = dl_list_entry(item->member.next, type, member); \
-	     &item->member != (list); \
-	     item = n, n = dl_list_entry(n->member.next, type, member))
-
-#define dl_list_for_each_reverse(item, list, type, member) \
-	for (item = dl_list_entry((list)->prev, type, member); \
-	     &item->member != (list); \
-	     item = dl_list_entry(item->member.prev, type, member))
-
-#define DEFINE_DL_LIST(name) \
-	struct dl_list name = { &(name), &(name) }
-
-#endif /* LIST_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/sta_info.h b/tools/sdk/include/wpa_supplicant/wpa/sta_info.h
deleted file mode 100644
index 44874a2ff99..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/sta_info.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * hostapd / Station table
- * Copyright (c) 2002-2011, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef STA_INFO_H
-#define STA_INFO_H
-
-/* STA flags */
-#define WLAN_STA_AUTH BIT(0)
-#define WLAN_STA_ASSOC BIT(1)
-#define WLAN_STA_PS BIT(2)
-#define WLAN_STA_TIM BIT(3)
-#define WLAN_STA_PERM BIT(4)
-#define WLAN_STA_AUTHORIZED BIT(5)
-#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */
-#define WLAN_STA_SHORT_PREAMBLE BIT(7)
-#define WLAN_STA_PREAUTH BIT(8)
-#define WLAN_STA_WMM BIT(9)
-#define WLAN_STA_MFP BIT(10)
-#define WLAN_STA_HT BIT(11)
-#define WLAN_STA_WPS BIT(12)
-#define WLAN_STA_MAYBE_WPS BIT(13)
-#define WLAN_STA_WDS BIT(14)
-#define WLAN_STA_ASSOC_REQ_OK BIT(15)
-#define WLAN_STA_WPS2 BIT(16)
-#define WLAN_STA_GAS BIT(17)
-#define WLAN_STA_VHT BIT(18)
-#define WLAN_STA_PENDING_DISASSOC_CB BIT(29)
-#define WLAN_STA_PENDING_DEAUTH_CB BIT(30)
-#define WLAN_STA_NONERP BIT(31)
-
-/* Maximum number of supported rates (from both Supported Rates and Extended
- * Supported Rates IEs). */
-#define WLAN_SUPP_RATES_MAX 32
-
-
-struct sta_info {
-	struct sta_info *next; /* next entry in sta list */
-	struct sta_info *hnext; /* next entry in hash table list */
-	u8 addr[6];
-	u16 aid; /* STA's unique AID (1 .. 2007) or 0 if not yet assigned */
-	u32 flags; /* Bitfield of WLAN_STA_* */
-	u16 capability;
-	u16 listen_interval; /* or beacon_int for APs */
-	u8 supported_rates[WLAN_SUPP_RATES_MAX];
-	int supported_rates_len;
-//	u8 qosinfo; /* Valid when WLAN_STA_WMM is set */
-
-//	unsigned int nonerp_set:1;
-//	unsigned int no_short_slot_time_set:1;
-//	unsigned int no_short_preamble_set:1;
-//	unsigned int no_ht_gf_set:1;
-//	unsigned int no_ht_set:1;
-//	unsigned int ht_20mhz_set:1;
-//	unsigned int no_p2p_set:1;
-
-	u16 auth_alg;
-//	u8 previous_ap[6];
-
-	enum {
-		STA_NULLFUNC = 0, STA_DISASSOC, STA_DEAUTH, STA_REMOVE
-	} timeout_next;
-
-//	u16 deauth_reason;
-//	u16 disassoc_reason;
-
-	/* IEEE 802.1X related data */
-//	struct eapol_state_machine *eapol_sm;
-
-	/* IEEE 802.11f (IAPP) related data */
-//	struct ieee80211_mgmt *last_assoc_req;
-
-//	u32 acct_session_id_hi;
-//	u32 acct_session_id_lo;
-//	time_t acct_session_start;
-//	int acct_session_started;
-//	int acct_terminate_cause; /* Acct-Terminate-Cause */
-//	int acct_interim_interval; /* Acct-Interim-Interval */
-
-//	unsigned long last_rx_bytes;
-//	unsigned long last_tx_bytes;
-//	u32 acct_input_gigawords; /* Acct-Input-Gigawords */
-//	u32 acct_output_gigawords; /* Acct-Output-Gigawords */
-
-//	u8 *challenge; /* IEEE 802.11 Shared Key Authentication Challenge */
-
-	struct wpa_state_machine *wpa_sm;
-//	struct rsn_preauth_interface *preauth_iface;
-
-	struct hostapd_ssid *ssid; /* SSID selection based on (Re)AssocReq */
-//	struct hostapd_ssid *ssid_probe; /* SSID selection based on ProbeReq */
-
-//	int vlan_id;
-	 /* PSKs from RADIUS authentication server */
-//	struct hostapd_sta_wpa_psk_short *psk;
-
-//	char *identity; /* User-Name from RADIUS */
-//	char *radius_cui; /* Chargeable-User-Identity from RADIUS */
-
-//	struct ieee80211_ht_capabilities *ht_capabilities;
-//	struct ieee80211_vht_capabilities *vht_capabilities;
-
-#ifdef CONFIG_IEEE80211W
-	int sa_query_count; /* number of pending SA Query requests;
-			     * 0 = no SA Query in progress */
-	int sa_query_timed_out;
-	u8 *sa_query_trans_id; /* buffer of WLAN_SA_QUERY_TR_ID_LEN *
-				* sa_query_count octets of pending SA Query
-				* transaction identifiers */
-	struct os_time sa_query_start;
-#endif /* CONFIG_IEEE80211W */
-
-#ifdef CONFIG_INTERWORKING
-#define GAS_DIALOG_MAX 8 /* Max concurrent dialog number */
-	struct gas_dialog_info *gas_dialog;
-	u8 gas_dialog_next;
-#endif /* CONFIG_INTERWORKING */
-
-//	struct wpabuf *wps_ie; /* WPS IE from (Re)Association Request */
-//	struct wpabuf *p2p_ie; /* P2P IE from (Re)Association Request */
-//	struct wpabuf *hs20_ie; /* HS 2.0 IE from (Re)Association Request */
-
-//	struct os_time connected_time;
-
-#ifdef CONFIG_SAE
-	enum { SAE_INIT, SAE_COMMIT, SAE_CONFIRM } sae_state;
-	u16 sae_send_confirm;
-#endif /* CONFIG_SAE */
-};
-
-
-/* Default value for maximum station inactivity. After AP_MAX_INACTIVITY has
- * passed since last received frame from the station, a nullfunc data frame is
- * sent to the station. If this frame is not acknowledged and no other frames
- * have been received, the station will be disassociated after
- * AP_DISASSOC_DELAY seconds. Similarly, the station will be deauthenticated
- * after AP_DEAUTH_DELAY seconds has passed after disassociation. */
-#define AP_MAX_INACTIVITY (5 * 60)
-#define AP_DISASSOC_DELAY (1)
-#define AP_DEAUTH_DELAY (1)
-/* Number of seconds to keep STA entry with Authenticated flag after it has
- * been disassociated. */
-#define AP_MAX_INACTIVITY_AFTER_DISASSOC (1 * 30)
-/* Number of seconds to keep STA entry after it has been deauthenticated. */
-#define AP_MAX_INACTIVITY_AFTER_DEAUTH (1 * 5)
-
-
-struct hostapd_data;
-
-int ap_for_each_sta(struct hostapd_data *hapd,
-		    int (*cb)(struct hostapd_data *hapd, struct sta_info *sta,
-			      void *ctx),
-		    void *ctx);
-struct sta_info * ap_get_sta(struct hostapd_data *hapd, const u8 *sta);
-void ap_sta_hash_add(struct hostapd_data *hapd, struct sta_info *sta);
-void ap_free_sta(struct hostapd_data *hapd, struct sta_info *sta);
-void hostapd_free_stas(struct hostapd_data *hapd);
-void ap_handle_timer(void *eloop_ctx, void *timeout_ctx);
-void ap_sta_session_timeout(struct hostapd_data *hapd, struct sta_info *sta,
-			    u32 session_timeout);
-void ap_sta_no_session_timeout(struct hostapd_data *hapd,
-			       struct sta_info *sta);
-struct sta_info * ap_sta_add(struct hostapd_data *hapd, const u8 *addr);
-void ap_sta_disassociate(struct hostapd_data *hapd, struct sta_info *sta,
-			 u16 reason);
-void ap_sta_deauthenticate(struct hostapd_data *hapd, struct sta_info *sta,
-			   u16 reason);
-#ifdef CONFIG_WPS
-int ap_sta_wps_cancel(struct hostapd_data *hapd,
-		      struct sta_info *sta, void *ctx);
-#endif /* CONFIG_WPS */
-int ap_sta_bind_vlan(struct hostapd_data *hapd, struct sta_info *sta,
-		     int old_vlanid);
-void ap_sta_start_sa_query(struct hostapd_data *hapd, struct sta_info *sta);
-void ap_sta_stop_sa_query(struct hostapd_data *hapd, struct sta_info *sta);
-int ap_check_sa_query_timeout(struct hostapd_data *hapd, struct sta_info *sta);
-void ap_sta_disconnect(struct hostapd_data *hapd, struct sta_info *sta,
-		       const u8 *addr, u16 reason);
-
-void ap_sta_set_authorized(struct hostapd_data *hapd,
-			   struct sta_info *sta, int authorized);
-static inline int ap_sta_is_authorized(struct sta_info *sta)
-{
-	return sta->flags & WLAN_STA_AUTHORIZED;
-}
-
-void ap_sta_deauth_cb(struct hostapd_data *hapd, struct sta_info *sta);
-void ap_sta_disassoc_cb(struct hostapd_data *hapd, struct sta_info *sta);
-
-#endif /* STA_INFO_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/state_machine.h b/tools/sdk/include/wpa_supplicant/wpa/state_machine.h
deleted file mode 100644
index ce8c51e7700..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/state_machine.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * wpa_supplicant/hostapd - State machine definitions
- * Copyright (c) 2002-2005, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- *
- * This file includes a set of pre-processor macros that can be used to
- * implement a state machine. In addition to including this header file, each
- * file implementing a state machine must define STATE_MACHINE_DATA to be the
- * data structure including state variables (enum machine_state,
- * Boolean changed), and STATE_MACHINE_DEBUG_PREFIX to be a string that is used
- * as a prefix for all debug messages. If SM_ENTRY_MA macro is used to define
- * a group of state machines with shared data structure, STATE_MACHINE_ADDR
- * needs to be defined to point to the MAC address used in debug output.
- * SM_ENTRY_M macro can be used to define similar group of state machines
- * without this additional debug info.
- */
-
-#ifndef STATE_MACHINE_H
-#define STATE_MACHINE_H
-
-/**
- * SM_STATE - Declaration of a state machine function
- * @machine: State machine name
- * @state: State machine state
- *
- * This macro is used to declare a state machine function. It is used in place
- * of a C function definition to declare functions to be run when the state is
- * entered by calling SM_ENTER or SM_ENTER_GLOBAL.
- */
-#define SM_STATE(machine, state) \
-static void ICACHE_FLASH_ATTR sm_ ## machine ## _ ## state ## _Enter(STATE_MACHINE_DATA *sm, \
-	int global)
-
-/**
- * SM_ENTRY - State machine function entry point
- * @machine: State machine name
- * @state: State machine state
- *
- * This macro is used inside each state machine function declared with
- * SM_STATE. SM_ENTRY should be in the beginning of the function body, but
- * after declaration of possible local variables. This macro prints debug
- * information about state transition and update the state machine state.
- */
-#define SM_ENTRY(machine, state) \
-if (!global || sm->machine ## _state != machine ## _ ## state) { \
-	sm->changed = TRUE; \
-	wpa_printf(MSG_DEBUG, STATE_MACHINE_DEBUG_PREFIX ": " #machine \
-		   " entering state " #state); \
-} \
-sm->machine ## _state = machine ## _ ## state;
-
-/**
- * SM_ENTRY_M - State machine function entry point for state machine group
- * @machine: State machine name
- * @_state: State machine state
- * @data: State variable prefix (full variable: prefix_state)
- *
- * This macro is like SM_ENTRY, but for state machine groups that use a shared
- * data structure for more than one state machine. Both machine and prefix
- * parameters are set to "sub-state machine" name. prefix is used to allow more
- * than one state variable to be stored in the same data structure.
- */
-#define SM_ENTRY_M(machine, _state, data) \
-if (!global || sm->data ## _ ## state != machine ## _ ## _state) { \
-	sm->changed = TRUE; \
-	wpa_printf(MSG_DEBUG, STATE_MACHINE_DEBUG_PREFIX ": " \
-		   #machine " entering state " #_state); \
-} \
-sm->data ## _ ## state = machine ## _ ## _state;
-
-/**
- * SM_ENTRY_MA - State machine function entry point for state machine group
- * @machine: State machine name
- * @_state: State machine state
- * @data: State variable prefix (full variable: prefix_state)
- *
- * This macro is like SM_ENTRY_M, but a MAC address is included in debug
- * output. STATE_MACHINE_ADDR has to be defined to point to the MAC address to
- * be included in debug.
- */
-#define SM_ENTRY_MA(machine, _state, data) \
-if (!global || sm->data ## _ ## state != machine ## _ ## _state) { \
-	sm->changed = TRUE; \
-	wpa_printf(MSG_DEBUG, STATE_MACHINE_DEBUG_PREFIX ": " MACSTR " " \
-		   #machine " entering state " #_state"\n", \
-		   MAC2STR(STATE_MACHINE_ADDR)); \
-} \
-sm->data ## _ ## state = machine ## _ ## _state;
-
-/**
- * SM_ENTER - Enter a new state machine state
- * @machine: State machine name
- * @state: State machine state
- *
- * This macro expands to a function call to a state machine function defined
- * with SM_STATE macro. SM_ENTER is used in a state machine step function to
- * move the state machine to a new state.
- */
-#define SM_ENTER(machine, state) \
-sm_ ## machine ## _ ## state ## _Enter(sm, 0)
-
-/**
- * SM_ENTER_GLOBAL - Enter a new state machine state based on global rule
- * @machine: State machine name
- * @state: State machine state
- *
- * This macro is like SM_ENTER, but this is used when entering a new state
- * based on a global (not specific to any particular state) rule. A separate
- * macro is used to avoid unwanted debug message floods when the same global
- * rule is forcing a state machine to remain in on state.
- */
-#define SM_ENTER_GLOBAL(machine, state) \
-sm_ ## machine ## _ ## state ## _Enter(sm, 1)
-
-/**
- * SM_STEP - Declaration of a state machine step function
- * @machine: State machine name
- *
- * This macro is used to declare a state machine step function. It is used in
- * place of a C function definition to declare a function that is used to move
- * state machine to a new state based on state variables. This function uses
- * SM_ENTER and SM_ENTER_GLOBAL macros to enter new state.
- */
-#define SM_STEP(machine) \
-static void ICACHE_FLASH_ATTR sm_ ## machine ## _Step(STATE_MACHINE_DATA *sm)
-
-/**
- * SM_STEP_RUN - Call the state machine step function
- * @machine: State machine name
- *
- * This macro expands to a function call to a state machine step function
- * defined with SM_STEP macro.
- */
-#define SM_STEP_RUN(machine) sm_ ## machine ## _Step(sm)
-
-#endif /* STATE_MACHINE_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpa.h b/tools/sdk/include/wpa_supplicant/wpa/wpa.h
deleted file mode 100644
index 9d50bb1ba57..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpa.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * wpa_supplicant - WPA definitions
- * Copyright (c) 2003-2007, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef WPA_H
-#define WPA_H
-
-#include "rom/ets_sys.h"
-#include "common.h"
-#include "wpa/defs.h"
-#include "wpa/wpa_common.h"
-
-
-#define WPA_SM_STATE(_sm) ((_sm)->wpa_state)
-
-struct wpa_sm;
-
-int wpa_sm_rx_eapol(u8 *src_addr, u8 *buf, u32 len);
-
-#define WPA_ASSERT  ASSERT
-
-struct install_key {
-    int mic_errors_seen; /* Michael MIC errors with the current PTK */
-    int keys_cleared;
-    enum wpa_alg alg;
-    u8 addr[ETH_ALEN];
-    int key_idx;
-    int set_tx;
-    u8 seq[10];
-    u8 key[32];
-};
-
-/**
- * struct wpa_sm - Internal WPA state machine data
- */
-struct wpa_sm {
-    u8 pmk[PMK_LEN];
-    size_t pmk_len;
-
-    struct wpa_ptk ptk, tptk;
-    int ptk_set, tptk_set;
-    u8 snonce[WPA_NONCE_LEN];
-    u8 anonce[WPA_NONCE_LEN]; /* ANonce from the last 1/4 msg */
-    int renew_snonce;
-    u8 rx_replay_counter[WPA_REPLAY_COUNTER_LEN];
-    int rx_replay_counter_set;
-    u8 request_counter[WPA_REPLAY_COUNTER_LEN];
-
-    unsigned int pairwise_cipher;
-    unsigned int group_cipher;
-    unsigned int key_mgmt;
-    unsigned int mgmt_group_cipher;
-
-    int rsn_enabled; /* Whether RSN is enabled in configuration */
-
-    int countermeasures; /*TKIP countermeasures state flag, 1:in countermeasures state*/
-    ETSTimer  cm_timer;
-
-    u8 *assoc_wpa_ie; /* Own WPA/RSN IE from (Re)AssocReq */
-    size_t assoc_wpa_ie_len;
-
-    u8 eapol_version;
-
-    int wpa_ptk_rekey;
-    u8 own_addr[ETH_ALEN];
-
-    u8 bssid[ETH_ALEN];
-
-    unsigned int proto;
-    enum wpa_states wpa_state;
-
-    u8 *ap_wpa_ie, *ap_rsn_ie;
-    size_t ap_wpa_ie_len, ap_rsn_ie_len;
-
-    struct install_key install_ptk;
-    struct install_key install_gtk;
-    int  key_entry_valid;   //present current avaliable entry for bssid, for pairkey:0,5,10,15,20, gtk: pairkey_no+i (i:1~4)
-
-    struct pbuf *pb;
-
-    void (* sendto) (struct pbuf *pb);
-    void (*config_assoc_ie) (u8 proto, u8 *assoc_buf, u32 assoc_wpa_ie_len);
-    void (*install_ppkey) (enum wpa_alg alg, u8 *addr, int key_idx, int set_tx,
-               u8 *seq, unsigned int seq_len, u8 *key, unsigned int key_len, int key_entry_valid);
-    void (*wpa_deauthenticate)(u8 reason_code);
-    void (*wpa_neg_complete)();
-    struct wpa_gtk_data gd; //used for calllback save param
-    u16 key_info; 	//used for txcallback param    
-};
-
-struct l2_ethhdr {
-    u8 h_dest[ETH_ALEN];
-    u8 h_source[ETH_ALEN];
-    be16 h_proto;
-} STRUCT_PACKED;
-
-/**
- * set_key - Configure encryption key
- * @ifname: Interface name (for multi-SSID/VLAN support)
- * @priv: private driver interface data
- * @alg: encryption algorithm (%WPA_ALG_NONE, %WPA_ALG_WEP,
- *	%WPA_ALG_TKIP, %WPA_ALG_CCMP, %WPA_ALG_IGTK, %WPA_ALG_PMK);
- *	%WPA_ALG_NONE clears the key.
- * @addr: address of the peer STA or ff:ff:ff:ff:ff:ff for
- *	broadcast/default keys
- * @key_idx: key index (0..3), usually 0 for unicast keys; 0..4095 for
- *	IGTK
- * @set_tx: configure this key as the default Tx key (only used when
- *	driver does not support separate unicast/individual key
- * @seq: sequence number/packet number, seq_len octets, the next
- *	packet number to be used for in replay protection; configured
- *	for Rx keys (in most cases, this is only used with broadcast
- *	keys and set to zero for unicast keys)
- * @seq_len: length of the seq, depends on the algorithm:
- *	TKIP: 6 octets, CCMP: 6 octets, IGTK: 6 octets
- * @key: key buffer; TKIP: 16-byte temporal key, 8-byte Tx Mic key,
- *	8-byte Rx Mic Key
- * @key_len: length of the key buffer in octets (WEP: 5 or 13,
- *	TKIP: 32, CCMP: 16, IGTK: 16)
- *
- * Returns: 0 on success, -1 on failure
- *
- * Configure the given key for the kernel driver. If the driver
- * supports separate individual keys (4 default keys + 1 individual),
- * addr can be used to determine whether the key is default or
- * individual. If only 4 keys are supported, the default key with key
- * index 0 is used as the individual key. STA must be configured to use
- * it as the default Tx key (set_tx is set) and accept Rx for all the
- * key indexes. In most cases, WPA uses only key indexes 1 and 2 for
- * broadcast keys, so key index 0 is available for this kind of
- * configuration.
- *
- * Please note that TKIP keys include separate TX and RX MIC keys and
- * some drivers may expect them in different order than wpa_supplicant
- * is using. If the TX/RX keys are swapped, all TKIP encrypted packets
- * will tricker Michael MIC errors. This can be fixed by changing the
- * order of MIC keys by swapping te bytes 16..23 and 24..31 of the key
- * in driver_*.c set_key() implementation, see driver_ndis.c for an
- * example on how this can be done.
- */
-
-
-/**
- * send_eapol - Optional function for sending EAPOL packets
- * @priv: private driver interface data
- * @dest: Destination MAC address
- * @proto: Ethertype
- * @data: EAPOL packet starting with IEEE 802.1X header
- * @data_len: Size of the EAPOL packet
- *
- * Returns: 0 on success, -1 on failure
- *
- * This optional function can be used to override l2_packet operations
- * with driver specific functionality. If this function pointer is set,
- * l2_packet module is not used at all and the driver interface code is
- * responsible for receiving and sending all EAPOL packets. The
- * received EAPOL packets are sent to core code with EVENT_EAPOL_RX
- * event. The driver interface is required to implement get_mac_addr()
- * handler if send_eapol() is used.
- */
-
-#define KEYENTRY_TABLE_MAP(key_entry_valid)  ((key_entry_valid)%5) 
-
-void wpa_sm_set_state(enum wpa_states state);
-
-char * dup_binstr(const void *src, size_t len);
-
-#endif /* WPA_H */
-
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpa_auth.h b/tools/sdk/include/wpa_supplicant/wpa/wpa_auth.h
deleted file mode 100644
index c7299234944..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpa_auth.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * hostapd - IEEE 802.11i-2004 / WPA Authenticator
- * Copyright (c) 2004-2007, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef WPA_AUTH_H
-#define WPA_AUTH_H
-
-#include "wpa/defs.h"
-#include "wpa/eapol_common.h"
-#include "wpa/wpa_common.h"
-
-#ifdef _MSC_VER
-#pragma pack(push, 1)
-#endif /* _MSC_VER */
-
-/* IEEE Std 802.11r-2008, 11A.10.3 - Remote request/response frame definition
- */
-struct ft_rrb_frame {
-	u8 frame_type; /* RSN_REMOTE_FRAME_TYPE_FT_RRB */
-	u8 packet_type; /* FT_PACKET_REQUEST/FT_PACKET_RESPONSE */
-	le16 action_length; /* little endian length of action_frame */
-	u8 ap_address[ETH_ALEN];
-	/*
-	 * Followed by action_length bytes of FT Action frame (from Category
-	 * field to the end of Action Frame body.
-	 */
-} STRUCT_PACKED;
-
-#define RSN_REMOTE_FRAME_TYPE_FT_RRB 1
-
-#define FT_PACKET_REQUEST 0
-#define FT_PACKET_RESPONSE 1
-/* Vendor-specific types for R0KH-R1KH protocol; not defined in 802.11r */
-#define FT_PACKET_R0KH_R1KH_PULL 200
-#define FT_PACKET_R0KH_R1KH_RESP 201
-#define FT_PACKET_R0KH_R1KH_PUSH 202
-
-#define FT_R0KH_R1KH_PULL_DATA_LEN 44
-#define FT_R0KH_R1KH_RESP_DATA_LEN 76
-#define FT_R0KH_R1KH_PUSH_DATA_LEN 88
-
-struct ft_r0kh_r1kh_pull_frame {
-	u8 frame_type; /* RSN_REMOTE_FRAME_TYPE_FT_RRB */
-	u8 packet_type; /* FT_PACKET_R0KH_R1KH_PULL */
-	le16 data_length; /* little endian length of data (44) */
-	u8 ap_address[ETH_ALEN];
-
-	u8 nonce[16];
-	u8 pmk_r0_name[WPA_PMK_NAME_LEN];
-	u8 r1kh_id[FT_R1KH_ID_LEN];
-	u8 s1kh_id[ETH_ALEN];
-	u8 pad[4]; /* 8-octet boundary for AES key wrap */
-	u8 key_wrap_extra[8];
-} STRUCT_PACKED;
-
-struct ft_r0kh_r1kh_resp_frame {
-	u8 frame_type; /* RSN_REMOTE_FRAME_TYPE_FT_RRB */
-	u8 packet_type; /* FT_PACKET_R0KH_R1KH_RESP */
-	le16 data_length; /* little endian length of data (76) */
-	u8 ap_address[ETH_ALEN];
-
-	u8 nonce[16]; /* copied from pull */
-	u8 r1kh_id[FT_R1KH_ID_LEN]; /* copied from pull */
-	u8 s1kh_id[ETH_ALEN]; /* copied from pull */
-	u8 pmk_r1[PMK_LEN];
-	u8 pmk_r1_name[WPA_PMK_NAME_LEN];
-	le16 pairwise;
-	u8 pad[2]; /* 8-octet boundary for AES key wrap */
-	u8 key_wrap_extra[8];
-} STRUCT_PACKED;
-
-struct ft_r0kh_r1kh_push_frame {
-	u8 frame_type; /* RSN_REMOTE_FRAME_TYPE_FT_RRB */
-	u8 packet_type; /* FT_PACKET_R0KH_R1KH_PUSH */
-	le16 data_length; /* little endian length of data (88) */
-	u8 ap_address[ETH_ALEN];
-
-	/* Encrypted with AES key-wrap */
-	u8 timestamp[4]; /* current time in seconds since unix epoch, little
-			  * endian */
-	u8 r1kh_id[FT_R1KH_ID_LEN];
-	u8 s1kh_id[ETH_ALEN];
-	u8 pmk_r0_name[WPA_PMK_NAME_LEN];
-	u8 pmk_r1[PMK_LEN];
-	u8 pmk_r1_name[WPA_PMK_NAME_LEN];
-	le16 pairwise;
-	u8 pad[6]; /* 8-octet boundary for AES key wrap */
-	u8 key_wrap_extra[8];
-} STRUCT_PACKED;
-
-#ifdef _MSC_VER
-#pragma pack(pop)
-#endif /* _MSC_VER */
-
-
-/* per STA state machine data */
-
-struct wpa_authenticator;
-struct wpa_state_machine;
-struct rsn_pmksa_cache_entry;
-struct eapol_state_machine;
-
-
-struct ft_remote_r0kh {
-	struct ft_remote_r0kh *next;
-	u8 addr[ETH_ALEN];
-	u8 id[FT_R0KH_ID_MAX_LEN];
-	size_t id_len;
-	u8 key[16];
-};
-
-
-struct ft_remote_r1kh {
-	struct ft_remote_r1kh *next;
-	u8 addr[ETH_ALEN];
-	u8 id[FT_R1KH_ID_LEN];
-	u8 key[16];
-};
-
-
-struct wpa_auth_config {
-	int wpa;
-	int wpa_key_mgmt;
-	int wpa_pairwise;
-	int wpa_group;
-	int wpa_group_rekey;
-	int wpa_strict_rekey;
-	int wpa_gmk_rekey;
-	int wpa_ptk_rekey;
-	int rsn_pairwise;
-	int rsn_preauth;
-	int eapol_version;
-	int peerkey;
-	int wmm_enabled;
-	int wmm_uapsd;
-	int disable_pmksa_caching;
-	int okc;
-	int tx_status;
-#ifdef CONFIG_IEEE80211W
-	enum mfp_options ieee80211w;
-#endif /* CONFIG_IEEE80211W */
-#ifdef CONFIG_IEEE80211R
-#define SSID_LEN 32
-	u8 ssid[SSID_LEN];
-	size_t ssid_len;
-	u8 mobility_domain[MOBILITY_DOMAIN_ID_LEN];
-	u8 r0_key_holder[FT_R0KH_ID_MAX_LEN];
-	size_t r0_key_holder_len;
-	u8 r1_key_holder[FT_R1KH_ID_LEN];
-	u32 r0_key_lifetime;
-	u32 reassociation_deadline;
-	struct ft_remote_r0kh *r0kh_list;
-	struct ft_remote_r1kh *r1kh_list;
-	int pmk_r1_push;
-	int ft_over_ds;
-#endif /* CONFIG_IEEE80211R */
-	int disable_gtk;
-	int ap_mlme;
-};
-
-typedef enum {
-	LOGGER_DEBUG, LOGGER_INFO, LOGGER_WARNING
-} logger_level;
-
-typedef enum {
-	WPA_EAPOL_portEnabled, WPA_EAPOL_portValid, WPA_EAPOL_authorized,
-	WPA_EAPOL_portControl_Auto, WPA_EAPOL_keyRun, WPA_EAPOL_keyAvailable,
-	WPA_EAPOL_keyDone, WPA_EAPOL_inc_EapolFramesTx
-} wpa_eapol_variable;
-
-struct wpa_auth_callbacks {
-	void *ctx;
-	void (*logger)(void *ctx, const u8 *addr, logger_level level,
-		       const char *txt);
-	void (*disconnect)(void *ctx, const u8 *addr, u16 reason);
-	int (*mic_failure_report)(void *ctx, const u8 *addr);
-	void (*set_eapol)(void *ctx, const u8 *addr, wpa_eapol_variable var,
-			  int value);
-	int (*get_eapol)(void *ctx, const u8 *addr, wpa_eapol_variable var);
-	const u8 * (*get_psk)(void *ctx, const u8 *addr, const u8 *prev_psk);
-	int (*get_msk)(void *ctx, const u8 *addr, u8 *msk, size_t *len);
-	int (*set_key)(void *ctx, int vlan_id, enum wpa_alg alg,
-		       const u8 *addr, int idx, u8 *key, size_t key_len);
-	int (*get_seqnum)(void *ctx, const u8 *addr, int idx, u8 *seq);
-	int (*send_eapol)(void *ctx, const u8 *addr, const u8 *data,
-			  size_t data_len, int encrypt);
-	int (*for_each_sta)(void *ctx, int (*cb)(struct wpa_state_machine *sm,
-						 void *ctx), void *cb_ctx);
-	int (*for_each_auth)(void *ctx, int (*cb)(struct wpa_authenticator *a,
-						  void *ctx), void *cb_ctx);
-	int (*send_ether)(void *ctx, const u8 *dst, u16 proto, const u8 *data,
-			  size_t data_len);
-#ifdef CONFIG_IEEE80211R
-	struct wpa_state_machine * (*add_sta)(void *ctx, const u8 *sta_addr);
-	int (*send_ft_action)(void *ctx, const u8 *dst,
-			      const u8 *data, size_t data_len);
-	int (*add_tspec)(void *ctx, const u8 *sta_addr, u8 *tspec_ie,
-                         size_t tspec_ielen);
-#endif /* CONFIG_IEEE80211R */
-};
-
-struct wpa_authenticator * wpa_init(const u8 *addr,
-				    struct wpa_auth_config *conf,
-				    struct wpa_auth_callbacks *cb);
-int wpa_init_keys(struct wpa_authenticator *wpa_auth);
-void wpa_deinit(struct wpa_authenticator *wpa_auth);
-int wpa_reconfig(struct wpa_authenticator *wpa_auth,
-		 struct wpa_auth_config *conf);
-
-enum {
-	WPA_IE_OK, WPA_INVALID_IE, WPA_INVALID_GROUP, WPA_INVALID_PAIRWISE,
-	WPA_INVALID_AKMP, WPA_NOT_ENABLED, WPA_ALLOC_FAIL,
-	WPA_MGMT_FRAME_PROTECTION_VIOLATION, WPA_INVALID_MGMT_GROUP_CIPHER,
-	WPA_INVALID_MDIE, WPA_INVALID_PROTO
-};
-	
-int wpa_validate_wpa_ie(struct wpa_authenticator *wpa_auth,
-			struct wpa_state_machine *sm,
-			const u8 *wpa_ie, size_t wpa_ie_len/*,
-			const u8 *mdie, size_t mdie_len*/);
-int wpa_auth_uses_mfp(struct wpa_state_machine *sm);
-struct wpa_state_machine *
-wpa_auth_sta_init(struct wpa_authenticator *wpa_auth, const u8 *addr);
-int wpa_auth_sta_associated(struct wpa_authenticator *wpa_auth,
-			    struct wpa_state_machine *sm);
-void wpa_auth_sta_no_wpa(struct wpa_state_machine *sm);
-void wpa_auth_sta_deinit(struct wpa_state_machine *sm);
-void wpa_receive(struct wpa_authenticator *wpa_auth,
-		 struct wpa_state_machine *sm,
-		 u8 *data, size_t data_len);
-typedef enum {
-	WPA_AUTH, WPA_ASSOC, WPA_DISASSOC, WPA_DEAUTH, WPA_REAUTH,
-	WPA_REAUTH_EAPOL, WPA_ASSOC_FT
-} wpa_event;
-void wpa_remove_ptk(struct wpa_state_machine *sm);
-int wpa_auth_sm_event(struct wpa_state_machine *sm, wpa_event event);
-void wpa_auth_sm_notify(struct wpa_state_machine *sm);
-void wpa_gtk_rekey(struct wpa_authenticator *wpa_auth);
-int wpa_get_mib(struct wpa_authenticator *wpa_auth, char *buf, size_t buflen);
-int wpa_get_mib_sta(struct wpa_state_machine *sm, char *buf, size_t buflen);
-void wpa_auth_countermeasures_start(struct wpa_authenticator *wpa_auth);
-int wpa_auth_pairwise_set(struct wpa_state_machine *sm);
-int wpa_auth_get_pairwise(struct wpa_state_machine *sm);
-int wpa_auth_sta_key_mgmt(struct wpa_state_machine *sm);
-int wpa_auth_sta_wpa_version(struct wpa_state_machine *sm);
-int wpa_auth_sta_clear_pmksa(struct wpa_state_machine *sm,
-			     struct rsn_pmksa_cache_entry *entry);
-struct rsn_pmksa_cache_entry *
-wpa_auth_sta_get_pmksa(struct wpa_state_machine *sm);
-void wpa_auth_sta_local_mic_failure_report(struct wpa_state_machine *sm);
-const u8 * wpa_auth_get_wpa_ie(struct wpa_authenticator *wpa_auth,
-			       size_t *len);
-int wpa_auth_pmksa_add(struct wpa_state_machine *sm, const u8 *pmk,
-		       int session_timeout, struct eapol_state_machine *eapol);
-int wpa_auth_pmksa_add_preauth(struct wpa_authenticator *wpa_auth,
-			       const u8 *pmk, size_t len, const u8 *sta_addr,
-			       int session_timeout,
-			       struct eapol_state_machine *eapol);
-int wpa_auth_sta_set_vlan(struct wpa_state_machine *sm, int vlan_id);
-void wpa_auth_eapol_key_tx_status(struct wpa_authenticator *wpa_auth,
-				  struct wpa_state_machine *sm, int ack);
-
-#ifdef CONFIG_IEEE80211R
-u8 * wpa_sm_write_assoc_resp_ies(struct wpa_state_machine *sm, u8 *pos,
-				 size_t max_len, int auth_alg,
-				 const u8 *req_ies, size_t req_ies_len);
-void wpa_ft_process_auth(struct wpa_state_machine *sm, const u8 *bssid,
-			 u16 auth_transaction, const u8 *ies, size_t ies_len,
-			 void (*cb)(void *ctx, const u8 *dst, const u8 *bssid,
-				    u16 auth_transaction, u16 resp,
-				    const u8 *ies, size_t ies_len),
-			 void *ctx);
-u16 wpa_ft_validate_reassoc(struct wpa_state_machine *sm, const u8 *ies,
-			    size_t ies_len);
-int wpa_ft_action_rx(struct wpa_state_machine *sm, const u8 *data, size_t len);
-int wpa_ft_rrb_rx(struct wpa_authenticator *wpa_auth, const u8 *src_addr,
-		  const u8 *data, size_t data_len);
-void wpa_ft_push_pmk_r1(struct wpa_authenticator *wpa_auth, const u8 *addr);
-#endif /* CONFIG_IEEE80211R */
-
-void wpa_wnmsleep_rekey_gtk(struct wpa_state_machine *sm);
-void wpa_set_wnmsleep(struct wpa_state_machine *sm, int flag);
-int wpa_wnmsleep_gtk_subelem(struct wpa_state_machine *sm, u8 *pos);
-int wpa_wnmsleep_igtk_subelem(struct wpa_state_machine *sm, u8 *pos);
-
-int wpa_auth_uses_sae(struct wpa_state_machine *sm);
-
-#endif /* WPA_AUTH_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpa_auth_i.h b/tools/sdk/include/wpa_supplicant/wpa/wpa_auth_i.h
deleted file mode 100644
index 53ad8ea941d..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpa_auth_i.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * hostapd - IEEE 802.11i-2004 / WPA Authenticator: Internal definitions
- * Copyright (c) 2004-2007, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef WPA_AUTH_I_H
-#define WPA_AUTH_I_H
-
-/* max(dot11RSNAConfigGroupUpdateCount,dot11RSNAConfigPairwiseUpdateCount) */
-#define RSNA_MAX_EAPOL_RETRIES 4
-
-struct wpa_group;
-
-struct wpa_stsl_negotiation {
-	struct wpa_stsl_negotiation *next;
-	u8 initiator[ETH_ALEN];
-	u8 peer[ETH_ALEN];
-};
-
-
-struct wpa_state_machine {
-	struct wpa_authenticator *wpa_auth;
-	struct wpa_group *group;
-
-	u8 addr[ETH_ALEN];
-
-	enum {
-		WPA_PTK_INITIALIZE, WPA_PTK_DISCONNECT, WPA_PTK_DISCONNECTED,
-		WPA_PTK_AUTHENTICATION, WPA_PTK_AUTHENTICATION2,
-		WPA_PTK_INITPMK, WPA_PTK_INITPSK, WPA_PTK_PTKSTART,
-		WPA_PTK_PTKCALCNEGOTIATING, WPA_PTK_PTKCALCNEGOTIATING2,
-		WPA_PTK_PTKINITNEGOTIATING, WPA_PTK_PTKINITDONE
-	} wpa_ptk_state;
-
-	enum {
-		WPA_PTK_GROUP_IDLE = 0,
-		WPA_PTK_GROUP_REKEYNEGOTIATING,
-		WPA_PTK_GROUP_REKEYESTABLISHED,
-		WPA_PTK_GROUP_KEYERROR
-	} wpa_ptk_group_state;
-
-	Boolean Init;
-	Boolean DeauthenticationRequest;
-	Boolean AuthenticationRequest;
-	Boolean ReAuthenticationRequest;
-	Boolean Disconnect;
-	int TimeoutCtr;
-	int GTimeoutCtr;
-	Boolean TimeoutEvt;
-	Boolean EAPOLKeyReceived;
-	Boolean EAPOLKeyPairwise;
-	Boolean EAPOLKeyRequest;
-	Boolean MICVerified;
-	Boolean GUpdateStationKeys;
-	u8 ANonce[WPA_NONCE_LEN];
-	u8 SNonce[WPA_NONCE_LEN];
-	u8 PMK[PMK_LEN];
-	struct wpa_ptk PTK;
-	Boolean PTK_valid;
-	Boolean pairwise_set;
-	int keycount;
-	Boolean Pair;
-	struct wpa_key_replay_counter {
-		u8 counter[WPA_REPLAY_COUNTER_LEN];
-		Boolean valid;
-	} key_replay[RSNA_MAX_EAPOL_RETRIES],
-		prev_key_replay[RSNA_MAX_EAPOL_RETRIES];
-	Boolean PInitAKeys; /* WPA only, not in IEEE 802.11i */
-	Boolean PTKRequest; /* not in IEEE 802.11i state machine */
-	Boolean has_GTK;
-	Boolean PtkGroupInit; /* init request for PTK Group state machine */
-
-	u8 *last_rx_eapol_key; /* starting from IEEE 802.1X header */
-	size_t last_rx_eapol_key_len;
-
-	unsigned int changed:1;
-	unsigned int in_step_loop:1;
-	unsigned int pending_deinit:1;
-	unsigned int started:1;
-	unsigned int mgmt_frame_prot:1;
-	unsigned int rx_eapol_key_secure:1;
-	unsigned int update_snonce:1;
-#ifdef CONFIG_IEEE80211R
-	unsigned int ft_completed:1;
-	unsigned int pmk_r1_name_valid:1;
-#endif /* CONFIG_IEEE80211R */
-	unsigned int is_wnmsleep:1;
-
-	u8 req_replay_counter[WPA_REPLAY_COUNTER_LEN];
-	int req_replay_counter_used;
-
-	u8 *wpa_ie;
-	size_t wpa_ie_len;
-
-	enum {
-		WPA_VERSION_NO_WPA = 0 /* WPA not used */,
-		WPA_VERSION_WPA = 1 /* WPA / IEEE 802.11i/D3.0 */,
-		WPA_VERSION_WPA2 = 2 /* WPA2 / IEEE 802.11i */
-	} wpa;
-	int pairwise; /* Pairwise cipher suite, WPA_CIPHER_* */
-	int wpa_key_mgmt; /* the selected WPA_KEY_MGMT_* */
-//	struct rsn_pmksa_cache_entry *pmksa;
-
-//	u32 dot11RSNAStatsTKIPLocalMICFailures;
-//	u32 dot11RSNAStatsTKIPRemoteMICFailures;
-
-#ifdef CONFIG_IEEE80211R
-	u8 xxkey[PMK_LEN]; /* PSK or the second 256 bits of MSK */
-	size_t xxkey_len;
-	u8 pmk_r1_name[WPA_PMK_NAME_LEN]; /* PMKR1Name derived from FT Auth
-					   * Request */
-	u8 r0kh_id[FT_R0KH_ID_MAX_LEN]; /* R0KH-ID from FT Auth Request */
-	size_t r0kh_id_len;
-	u8 sup_pmk_r1_name[WPA_PMK_NAME_LEN]; /* PMKR1Name from EAPOL-Key
-					       * message 2/4 */
-	u8 *assoc_resp_ftie;
-#endif /* CONFIG_IEEE80211R */
-
-	int pending_1_of_4_timeout;
-};
-
-
-/* per group key state machine data */
-struct wpa_group {
-	struct wpa_group *next;
-	int vlan_id;
-
-	Boolean GInit;
-	int GKeyDoneStations;
-	Boolean GTKReKey;
-	int GTK_len;
-	int GN, GM;
-	Boolean GTKAuthenticator;
-	u8 Counter[WPA_NONCE_LEN];
-
-	enum {
-		WPA_GROUP_GTK_INIT = 0,
-		WPA_GROUP_SETKEYS, WPA_GROUP_SETKEYSDONE
-	} wpa_group_state;
-
-	u8 GMK[WPA_GMK_LEN];
-	u8 GTK[2][WPA_GTK_MAX_LEN];
-	u8 GNonce[WPA_NONCE_LEN];
-	Boolean changed;
-	Boolean first_sta_seen;
-	Boolean reject_4way_hs_for_entropy;
-#ifdef CONFIG_IEEE80211W
-	u8 IGTK[2][WPA_IGTK_LEN];
-	int GN_igtk, GM_igtk;
-#endif /* CONFIG_IEEE80211W */
-};
-
-
-struct wpa_ft_pmk_cache;
-
-/* per authenticator data */
-struct wpa_authenticator {
-	struct wpa_group *group;
-
-//	unsigned int dot11RSNAStatsTKIPRemoteMICFailures;
-//	u32 dot11RSNAAuthenticationSuiteSelected;
-//	u32 dot11RSNAPairwiseCipherSelected;
-//	u32 dot11RSNAGroupCipherSelected;
-//	u8 dot11RSNAPMKIDUsed[PMKID_LEN];
-//	u32 dot11RSNAAuthenticationSuiteRequested; /* FIX: update */
-//	u32 dot11RSNAPairwiseCipherRequested; /* FIX: update */
-//	u32 dot11RSNAGroupCipherRequested; /* FIX: update */
-//	unsigned int dot11RSNATKIPCounterMeasuresInvoked;
-//	unsigned int dot11RSNA4WayHandshakeFailures;
-
-//	struct wpa_stsl_negotiation *stsl_negotiations;
-
-	struct wpa_auth_config conf;
-//	struct wpa_auth_callbacks cb;
-
-	u8 *wpa_ie;
-	size_t wpa_ie_len;
-
-	u8 addr[ETH_ALEN];
-
-//	struct rsn_pmksa_cache *pmksa;
-//	struct wpa_ft_pmk_cache *ft_pmk_cache;
-};
-
-
-int wpa_write_rsn_ie(struct wpa_auth_config *conf, u8 *buf, size_t len,
-		     const u8 *pmkid);
-#if 0
-void wpa_auth_logger(struct wpa_authenticator *wpa_auth, const u8 *addr,
-		     logger_level level, const char *txt);
-void wpa_auth_vlogger(struct wpa_authenticator *wpa_auth, const u8 *addr,
-		      logger_level level, const char *fmt, ...);
-#endif
-void __wpa_send_eapol(struct wpa_authenticator *wpa_auth,
-		      struct wpa_state_machine *sm, int key_info,
-		      const u8 *key_rsc, const u8 *nonce,
-		      const u8 *kde, size_t kde_len,
-		      int keyidx, int encr, int force_version);
-int wpa_auth_for_each_sta(struct wpa_authenticator *wpa_auth,
-			  int (*cb)(struct wpa_state_machine *sm, void *ctx),
-			  void *cb_ctx);
-int wpa_auth_for_each_auth(struct wpa_authenticator *wpa_auth,
-			   int (*cb)(struct wpa_authenticator *a, void *ctx),
-			   void *cb_ctx);
-
-#ifdef CONFIG_PEERKEY
-int wpa_stsl_remove(struct wpa_authenticator *wpa_auth,
-		    struct wpa_stsl_negotiation *neg);
-void wpa_smk_error(struct wpa_authenticator *wpa_auth,
-		   struct wpa_state_machine *sm, struct wpa_eapol_key *key);
-void wpa_smk_m1(struct wpa_authenticator *wpa_auth,
-		struct wpa_state_machine *sm, struct wpa_eapol_key *key);
-void wpa_smk_m3(struct wpa_authenticator *wpa_auth,
-		struct wpa_state_machine *sm, struct wpa_eapol_key *key);
-#endif /* CONFIG_PEERKEY */
-
-#ifdef CONFIG_IEEE80211R
-int wpa_write_mdie(struct wpa_auth_config *conf, u8 *buf, size_t len);
-int wpa_write_ftie(struct wpa_auth_config *conf, const u8 *r0kh_id,
-		   size_t r0kh_id_len,
-		   const u8 *anonce, const u8 *snonce,
-		   u8 *buf, size_t len, const u8 *subelem,
-		   size_t subelem_len);
-int wpa_auth_derive_ptk_ft(struct wpa_state_machine *sm, const u8 *pmk,
-			   struct wpa_ptk *ptk, size_t ptk_len);
-struct wpa_ft_pmk_cache * wpa_ft_pmk_cache_init(void);
-void wpa_ft_pmk_cache_deinit(struct wpa_ft_pmk_cache *cache);
-void wpa_ft_install_ptk(struct wpa_state_machine *sm);
-#endif /* CONFIG_IEEE80211R */
-
-#endif /* WPA_AUTH_I_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpa_auth_ie.h b/tools/sdk/include/wpa_supplicant/wpa/wpa_auth_ie.h
deleted file mode 100644
index 4999139510e..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpa_auth_ie.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * hostapd - WPA/RSN IE and KDE definitions
- * Copyright (c) 2004-2007, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef WPA_AUTH_IE_H
-#define WPA_AUTH_IE_H
-
-struct wpa_eapol_ie_parse {
-	const u8 *wpa_ie;
-	size_t wpa_ie_len;
-	const u8 *rsn_ie;
-	size_t rsn_ie_len;
-	const u8 *pmkid;
-	const u8 *gtk;
-	size_t gtk_len;
-	const u8 *mac_addr;
-	size_t mac_addr_len;
-#ifdef CONFIG_PEERKEY
-	const u8 *smk;
-	size_t smk_len;
-	const u8 *nonce;
-	size_t nonce_len;
-	const u8 *lifetime;
-	size_t lifetime_len;
-	const u8 *error;
-	size_t error_len;
-#endif /* CONFIG_PEERKEY */
-#ifdef CONFIG_IEEE80211W
-	const u8 *igtk;
-	size_t igtk_len;
-#endif /* CONFIG_IEEE80211W */
-#ifdef CONFIG_IEEE80211R
-	const u8 *mdie;
-	size_t mdie_len;
-	const u8 *ftie;
-	size_t ftie_len;
-#endif /* CONFIG_IEEE80211R */
-};
-
-int wpa_parse_kde_ies(const u8 *buf, size_t len,
-		      struct wpa_eapol_ie_parse *ie);
-u8 * wpa_add_kde(u8 *pos, u32 kde, const u8 *data, size_t data_len,
-		 const u8 *data2, size_t data2_len);
-int wpa_auth_gen_wpa_ie(struct wpa_authenticator *wpa_auth);
-
-#endif /* WPA_AUTH_IE_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpa_common.h b/tools/sdk/include/wpa_supplicant/wpa/wpa_common.h
deleted file mode 100644
index 480cf0e27e6..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpa_common.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- * WPA definitions shared between hostapd and wpa_supplicant
- * Copyright (c) 2002-2008, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#include "os.h"
-#ifndef WPA_COMMON_H
-#define WPA_COMMON_H
-
-#define WPA_MAX_SSID_LEN 32
-
-/* IEEE 802.11i */
-#define PMKID_LEN 16
-#define PMK_LEN 32
-#define WPA_REPLAY_COUNTER_LEN 8
-#define WPA_NONCE_LEN 32
-#define WPA_KEY_RSC_LEN 8
-#define WPA_GMK_LEN 32
-#define WPA_GTK_MAX_LEN 32
-
-#define WPA_SELECTOR_LEN 4
-#define WPA_VERSION 1
-#define RSN_SELECTOR_LEN 4
-#define RSN_VERSION 1
-
-#define RSN_SELECTOR(a, b, c, d) \
-	((((u32) (a)) << 24) | (((u32) (b)) << 16) | (((u32) (c)) << 8) | \
-	 (u32) (d))
-
-#define WPA_AUTH_KEY_MGMT_NONE RSN_SELECTOR(0x00, 0x50, 0xf2, 0)
-#define WPA_AUTH_KEY_MGMT_UNSPEC_802_1X RSN_SELECTOR(0x00, 0x50, 0xf2, 1)
-#define WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X RSN_SELECTOR(0x00, 0x50, 0xf2, 2)
-#define WPA_CIPHER_SUITE_NONE RSN_SELECTOR(0x00, 0x50, 0xf2, 0)
-#define WPA_CIPHER_SUITE_WEP40 RSN_SELECTOR(0x00, 0x50, 0xf2, 1)
-#define WPA_CIPHER_SUITE_TKIP RSN_SELECTOR(0x00, 0x50, 0xf2, 2)
-#if 0
-#define WPA_CIPHER_SUITE_WRAP RSN_SELECTOR(0x00, 0x50, 0xf2, 3)
-#endif
-#define WPA_CIPHER_SUITE_CCMP RSN_SELECTOR(0x00, 0x50, 0xf2, 4)
-#define WPA_CIPHER_SUITE_WEP104 RSN_SELECTOR(0x00, 0x50, 0xf2, 5)
-
-
-#define RSN_AUTH_KEY_MGMT_UNSPEC_802_1X RSN_SELECTOR(0x00, 0x0f, 0xac, 1)
-#define RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X RSN_SELECTOR(0x00, 0x0f, 0xac, 2)
-#ifdef CONFIG_IEEE80211R
-#define RSN_AUTH_KEY_MGMT_FT_802_1X RSN_SELECTOR(0x00, 0x0f, 0xac, 3)
-#define RSN_AUTH_KEY_MGMT_FT_PSK RSN_SELECTOR(0x00, 0x0f, 0xac, 4)
-#endif /* CONFIG_IEEE80211R */
-#define RSN_AUTH_KEY_MGMT_802_1X_SHA256 RSN_SELECTOR(0x00, 0x0f, 0xac, 5)
-#define RSN_AUTH_KEY_MGMT_PSK_SHA256 RSN_SELECTOR(0x00, 0x0f, 0xac, 6)
-
-#define RSN_CIPHER_SUITE_NONE RSN_SELECTOR(0x00, 0x0f, 0xac, 0)
-#define RSN_CIPHER_SUITE_WEP40 RSN_SELECTOR(0x00, 0x0f, 0xac, 1)
-#define RSN_CIPHER_SUITE_TKIP RSN_SELECTOR(0x00, 0x0f, 0xac, 2)
-#if 0
-#define RSN_CIPHER_SUITE_WRAP RSN_SELECTOR(0x00, 0x0f, 0xac, 3)
-#endif
-#define RSN_CIPHER_SUITE_CCMP RSN_SELECTOR(0x00, 0x0f, 0xac, 4)
-#define RSN_CIPHER_SUITE_WEP104 RSN_SELECTOR(0x00, 0x0f, 0xac, 5)
-#ifdef CONFIG_IEEE80211W
-#define RSN_CIPHER_SUITE_AES_128_CMAC RSN_SELECTOR(0x00, 0x0f, 0xac, 6)
-#endif /* CONFIG_IEEE80211W */
-#define RSN_CIPHER_SUITE_NO_GROUP_ADDRESSED RSN_SELECTOR(0x00, 0x0f, 0xac, 7)
-#define RSN_CIPHER_SUITE_GCMP RSN_SELECTOR(0x00, 0x0f, 0xac, 8)
-
-/* EAPOL-Key Key Data Encapsulation
- * GroupKey and PeerKey require encryption, otherwise, encryption is optional.
- */
-#define RSN_KEY_DATA_GROUPKEY RSN_SELECTOR(0x00, 0x0f, 0xac, 1)
-#if 0
-#define RSN_KEY_DATA_STAKEY RSN_SELECTOR(0x00, 0x0f, 0xac, 2)
-#endif
-#define RSN_KEY_DATA_MAC_ADDR RSN_SELECTOR(0x00, 0x0f, 0xac, 3)
-#define RSN_KEY_DATA_PMKID RSN_SELECTOR(0x00, 0x0f, 0xac, 4)
-#ifdef CONFIG_PEERKEY
-#define RSN_KEY_DATA_SMK RSN_SELECTOR(0x00, 0x0f, 0xac, 5)
-#define RSN_KEY_DATA_NONCE RSN_SELECTOR(0x00, 0x0f, 0xac, 6)
-#define RSN_KEY_DATA_LIFETIME RSN_SELECTOR(0x00, 0x0f, 0xac, 7)
-#define RSN_KEY_DATA_ERROR RSN_SELECTOR(0x00, 0x0f, 0xac, 8)
-#endif /* CONFIG_PEERKEY */
-#ifdef CONFIG_IEEE80211W
-#define RSN_KEY_DATA_IGTK RSN_SELECTOR(0x00, 0x0f, 0xac, 9)
-#endif /* CONFIG_IEEE80211W */
-
-#define WPA_OUI_TYPE RSN_SELECTOR(0x00, 0x50, 0xf2, 1)
-
-#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
-#define RSN_SELECTOR_GET(a) WPA_GET_BE32((const u8 *) (a))
-
-#define RSN_NUM_REPLAY_COUNTERS_1 0
-#define RSN_NUM_REPLAY_COUNTERS_2 1
-#define RSN_NUM_REPLAY_COUNTERS_4 2
-#define RSN_NUM_REPLAY_COUNTERS_16 3
-
-#ifdef _MSC_VER
-#pragma pack(push, 1)
-#endif /* _MSC_VER */
-
-#ifdef CONFIG_IEEE80211W
-#define WPA_IGTK_LEN 16
-#endif /* CONFIG_IEEE80211W */
-
-
-/* IEEE 802.11, 7.3.2.25.3 RSN Capabilities */
-#define WPA_CAPABILITY_PREAUTH BIT(0)
-#define WPA_CAPABILITY_NO_PAIRWISE BIT(1)
-/* B2-B3: PTKSA Replay Counter */
-/* B4-B5: GTKSA Replay Counter */
-#define WPA_CAPABILITY_MFPR BIT(6)
-#define WPA_CAPABILITY_MFPC BIT(7)
-#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
-
-
-/* IEEE 802.11r */
-#define MOBILITY_DOMAIN_ID_LEN 2
-#define FT_R0KH_ID_MAX_LEN 48
-#define FT_R1KH_ID_LEN 6
-#define WPA_PMK_NAME_LEN 16
-
-
-/* IEEE 802.11, 8.5.2 EAPOL-Key frames */
-#define WPA_KEY_INFO_TYPE_MASK ((u16) (BIT(0) | BIT(1) | BIT(2)))
-#define WPA_KEY_INFO_TYPE_HMAC_MD5_RC4 BIT(0)
-#define WPA_KEY_INFO_TYPE_HMAC_SHA1_AES BIT(1)
-#define WPA_KEY_INFO_TYPE_AES_128_CMAC 3
-#define WPA_KEY_INFO_KEY_TYPE BIT(3) /* 1 = Pairwise, 0 = Group key */
-/* bit4..5 is used in WPA, but is reserved in IEEE 802.11i/RSN */
-#define WPA_KEY_INFO_KEY_INDEX_MASK (BIT(4) | BIT(5))
-#define WPA_KEY_INFO_KEY_INDEX_SHIFT 4
-#define WPA_KEY_INFO_INSTALL BIT(6) /* pairwise */
-#define WPA_KEY_INFO_TXRX BIT(6) /* group */
-#define WPA_KEY_INFO_ACK BIT(7)
-#define WPA_KEY_INFO_MIC BIT(8)
-#define WPA_KEY_INFO_SECURE BIT(9)
-#define WPA_KEY_INFO_ERROR BIT(10)
-#define WPA_KEY_INFO_REQUEST BIT(11)
-#define WPA_KEY_INFO_ENCR_KEY_DATA BIT(12) /* IEEE 802.11i/RSN only */
-#define WPA_KEY_INFO_SMK_MESSAGE BIT(13)
-
-
-struct wpa_eapol_key {
-	u8 type;
-	/* Note: key_info, key_length, and key_data_length are unaligned */
-	u8 key_info[2]; /* big endian */
-	u8 key_length[2]; /* big endian */
-	u8 replay_counter[WPA_REPLAY_COUNTER_LEN];
-	u8 key_nonce[WPA_NONCE_LEN];
-	u8 key_iv[16];
-	u8 key_rsc[WPA_KEY_RSC_LEN];
-	u8 key_id[8]; /* Reserved in IEEE 802.11i/RSN */
-	u8 key_mic[16];
-	u8 key_data_length[2]; /* big endian */
-	/* followed by key_data_length bytes of key_data */
-} STRUCT_PACKED;
-
-/**
- * struct wpa_ptk - WPA Pairwise Transient Key
- * IEEE Std 802.11i-2004 - 8.5.1.2 Pairwise key hierarchy
- */
-struct wpa_ptk {
-	u8 kck[16]; /* EAPOL-Key Key Confirmation Key (KCK) */
-	u8 kek[16]; /* EAPOL-Key Key Encryption Key (KEK) */
-	u8 tk1[16]; /* Temporal Key 1 (TK1) */
-	union {
-		u8 tk2[16]; /* Temporal Key 2 (TK2) */
-		struct {
-			u8 tx_mic_key[8];
-			u8 rx_mic_key[8];
-		} auth;
-	} u;
-} STRUCT_PACKED;
-
-struct wpa_gtk_data {
-	enum wpa_alg alg;
-	int tx, key_rsc_len, keyidx;
-	u8 gtk[32];
-	int gtk_len;
-};
-
-
-/* WPA IE version 1
- * 00-50-f2:1 (OUI:OUI type)
- * 0x01 0x00 (version; little endian)
- * (all following fields are optional:)
- * Group Suite Selector (4 octets) (default: TKIP)
- * Pairwise Suite Count (2 octets, little endian) (default: 1)
- * Pairwise Suite List (4 * n octets) (default: TKIP)
- * Authenticated Key Management Suite Count (2 octets, little endian)
- *    (default: 1)
- * Authenticated Key Management Suite List (4 * n octets)
- *    (default: unspec 802.1X)
- * WPA Capabilities (2 octets, little endian) (default: 0)
- */
-
-struct wpa_ie_hdr {
-	u8 elem_id;
-	u8 len;
-	u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
-	u8 version[2]; /* little endian */
-} STRUCT_PACKED;
-
-
-/* 1/4: PMKID
- * 2/4: RSN IE
- * 3/4: one or two RSN IEs + GTK IE (encrypted)
- * 4/4: empty
- * 1/2: GTK IE (encrypted)
- * 2/2: empty
- */
-
-/* RSN IE version 1
- * 0x01 0x00 (version; little endian)
- * (all following fields are optional:)
- * Group Suite Selector (4 octets) (default: CCMP)
- * Pairwise Suite Count (2 octets, little endian) (default: 1)
- * Pairwise Suite List (4 * n octets) (default: CCMP)
- * Authenticated Key Management Suite Count (2 octets, little endian)
- *    (default: 1)
- * Authenticated Key Management Suite List (4 * n octets)
- *    (default: unspec 802.1X)
- * RSN Capabilities (2 octets, little endian) (default: 0)
- * PMKID Count (2 octets) (default: 0)
- * PMKID List (16 * n octets)
- * Management Group Cipher Suite (4 octets) (default: AES-128-CMAC)
- */
-
-struct rsn_ie_hdr {
-	u8 elem_id; /* WLAN_EID_RSN */
-	u8 len;
-	u8 version[2]; /* little endian */
-} STRUCT_PACKED;
-
-
-#ifdef CONFIG_PEERKEY
-enum {
-	STK_MUI_4WAY_STA_AP = 1,
-	STK_MUI_4WAY_STAT_STA = 2,
-	STK_MUI_GTK = 3,
-	STK_MUI_SMK = 4
-};
-
-enum {
-	STK_ERR_STA_NR = 1,
-	STK_ERR_STA_NRSN = 2,
-	STK_ERR_CPHR_NS = 3,
-	STK_ERR_NO_STSL = 4
-};
-#endif /* CONFIG_PEERKEY */
-
-struct rsn_error_kde {
-	be16 mui;
-	be16 error_type;
-} STRUCT_PACKED;
-
-#ifdef CONFIG_IEEE80211W
-struct wpa_igtk_kde {
-	u8 keyid[2];
-	u8 pn[6];
-	u8 igtk[WPA_IGTK_LEN];
-} STRUCT_PACKED;
-#endif /* CONFIG_IEEE80211W */
-
-#ifdef CONFIG_IEEE80211R
-struct rsn_mdie {
-	u8 mobility_domain[MOBILITY_DOMAIN_ID_LEN];
-	u8 ft_capab;
-} STRUCT_PACKED;
-
-#define RSN_FT_CAPAB_FT_OVER_DS BIT(0)
-#define RSN_FT_CAPAB_FT_RESOURCE_REQ_SUPP BIT(1)
-
-struct rsn_ftie {
-	u8 mic_control[2];
-	u8 mic[16];
-	u8 anonce[WPA_NONCE_LEN];
-	u8 snonce[WPA_NONCE_LEN];
-	/* followed by optional parameters */
-} STRUCT_PACKED;
-
-#define FTIE_SUBELEM_R1KH_ID 1
-#define FTIE_SUBELEM_GTK 2
-#define FTIE_SUBELEM_R0KH_ID 3
-#define FTIE_SUBELEM_IGTK 4
-
-struct rsn_rdie {
-	u8 id;
-	u8 descr_count;
-	le16 status_code;
-} STRUCT_PACKED;
-
-#endif /* CONFIG_IEEE80211R */
-
-struct wpa_ie_data {
-	int proto;
-	int pairwise_cipher;
-	int group_cipher;
-	int key_mgmt;
-	int capabilities;
-	size_t num_pmkid;
-	const u8 *pmkid;
-	int mgmt_group_cipher;
-};
-
-const char * wpa_cipher_txt(int cipher);
-
-int wpa_parse_wpa_ie_rsn(const u8 *rsn_ie, size_t rsn_ie_len,
-			 struct wpa_ie_data *data);
-
-int wpa_eapol_key_mic(const u8 *key, int ver, const u8 *buf, size_t len,
-		      u8 *mic);
-int wpa_compare_rsn_ie(int ft_initial_assoc,
-		       const u8 *ie1, size_t ie1len,
-		       const u8 *ie2, size_t ie2len);
-
-void wpa_pmk_to_ptk(const u8 *pmk, size_t pmk_len, const char *label,
-		    const u8 *addr1, const u8 *addr2,
-		    const u8 *nonce1, const u8 *nonce2,
-		    u8 *ptk, size_t ptk_len, int use_sha256);
-
-void rsn_pmkid(const u8 *pmk, size_t pmk_len, const u8 *aa, const u8 *spa,
-	       u8 *pmkid, int use_sha256);
-
-#endif /* WPA_COMMON_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpa_debug.h b/tools/sdk/include/wpa_supplicant/wpa/wpa_debug.h
deleted file mode 100644
index 10fe928c3eb..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpa_debug.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * wpa_supplicant/hostapd / Debug prints
- * Copyright (c) 2002-2007, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef WPA_DEBUG_H
-#define WPA_DEBUG_H
-
-#include "wpabuf.h"
-#include "esp_log.h"
-
-#ifdef ESPRESSIF_USE
-
-#define TAG "wpa"
-
-#define MSG_ERROR ESP_LOG_ERROR
-#define MSG_WARNING ESP_LOG_WARN
-#define MSG_INFO ESP_LOG_INFO
-#define MSG_DEBUG ESP_LOG_DEBUG
-#define MSG_MSGDUMP ESP_LOG_VERBOSE
-
-#else 
-enum { MSG_MSGDUMP, MSG_DEBUG, MSG_INFO, MSG_WARNING, MSG_ERROR };
-#endif
-
-/** EAP authentication completed successfully */
-#define WPA_EVENT_EAP_SUCCESS "CTRL-EVENT-EAP-SUCCESS "
-
-int wpa_debug_open_file(const char *path);
-void wpa_debug_close_file(void);
-
-/**
- * wpa_debug_printf_timestamp - Print timestamp for debug output
- *
- * This function prints a timestamp in seconds_from_1970.microsoconds
- * format if debug output has been configured to include timestamps in debug
- * messages.
- */
-void wpa_debug_print_timestamp(void);
-
-/**
- * wpa_printf - conditional printf
- * @level: priority level (MSG_*) of the message
- * @fmt: printf format string, followed by optional arguments
- *
- * This function is used to print conditional debugging and error messages. The
- * output may be directed to stdout, stderr, and/or syslog based on
- * configuration.
- *
- * Note: New line '\n' is added to the end of the text when printing to stdout.
- */
-#define  DEBUG_PRINT
-#define   MSG_PRINT
-
-/**
- * wpa_hexdump - conditional hex dump
- * @level: priority level (MSG_*) of the message
- * @title: title of for the message
- * @buf: data buffer to be dumped
- * @len: length of the buf
- *
- * This function is used to print conditional debugging and error messages. The
- * output may be directed to stdout, stderr, and/or syslog based on
- * configuration. The contents of buf is printed out has hex dump.
- */
-#ifdef DEBUG_PRINT
-#define wpa_printf(level,fmt, args...) ESP_LOG_LEVEL_LOCAL(level, TAG, fmt, ##args)
-
-static inline void wpa_hexdump_ascii(int level, const char *title, const u8 *buf, size_t len)
-{
-
-}
-
-static inline void wpa_hexdump_ascii_key(int level, const char *title, const u8 *buf, size_t len)
-{
-}
-
-
-void wpa_hexdump(int level, const char *title, const u8 *buf, size_t len);
-
-static inline void wpa_hexdump_buf(int level, const char *title,
-				   const struct wpabuf *buf)
-{
-	wpa_hexdump(level, title, wpabuf_head(buf), wpabuf_len(buf));
-}
-
-/**
- * wpa_hexdump_key - conditional hex dump, hide keys
- * @level: priority level (MSG_*) of the message
- * @title: title of for the message
- * @buf: data buffer to be dumped
- * @len: length of the buf
- *
- * This function is used to print conditional debugging and error messages. The
- * output may be directed to stdout, stderr, and/or syslog based on
- * configuration. The contents of buf is printed out has hex dump. This works
- * like wpa_hexdump(), but by default, does not include secret keys (passwords,
- * etc.) in debug output.
- */
-void wpa_hexdump_key(int level, const char *title, const u8 *buf, size_t len);
-
-
-static inline void wpa_hexdump_buf_key(int level, const char *title,
-				       const struct wpabuf *buf)
-{
-	wpa_hexdump_key(level, title, wpabuf_head(buf), wpabuf_len(buf));
-}
-
-/**
- * wpa_hexdump_ascii - conditional hex dump
- * @level: priority level (MSG_*) of the message
- * @title: title of for the message
- * @buf: data buffer to be dumped
- * @len: length of the buf
- *
- * This function is used to print conditional debugging and error messages. The
- * output may be directed to stdout, stderr, and/or syslog based on
- * configuration. The contents of buf is printed out has hex dump with both
- * the hex numbers and ASCII characters (for printable range) are shown. 16
- * bytes per line will be shown.
- */
-void wpa_hexdump_ascii(int level, const char *title, const u8 *buf,
-		       size_t len);
-
-/**
- * wpa_hexdump_ascii_key - conditional hex dump, hide keys
- * @level: priority level (MSG_*) of the message
- * @title: title of for the message
- * @buf: data buffer to be dumped
- * @len: length of the buf
- *
- * This function is used to print conditional debugging and error messages. The
- * output may be directed to stdout, stderr, and/or syslog based on
- * configuration. The contents of buf is printed out has hex dump with both
- * the hex numbers and ASCII characters (for printable range) are shown. 16
- * bytes per line will be shown. This works like wpa_hexdump_ascii(), but by
- * default, does not include secret keys (passwords, etc.) in debug output.
- */
-void wpa_hexdump_ascii_key(int level, const char *title, const u8 *buf,
-			   size_t len);
-#else
-#define wpa_printf(level,fmt, args...)
-#define wpa_hexdump(...)
-#define wpa_hexdump_buf(...)
-#define wpa_hexdump_key(...)
-#define wpa_hexdump_buf_key(...)
-#define wpa_hexdump_ascii(...)
-#define wpa_hexdump_ascii_key(...)
-#endif
-
-#define wpa_auth_logger
-#define wpa_auth_vlogger
-
-/**
- * wpa_msg - Conditional printf for default target and ctrl_iface monitors
- * @ctx: Pointer to context data; this is the ctx variable registered
- *	with struct wpa_driver_ops::init()
- * @level: priority level (MSG_*) of the message
- * @fmt: printf format string, followed by optional arguments
- *
- * This function is used to print conditional debugging and error messages. The
- * output may be directed to stdout, stderr, and/or syslog based on
- * configuration. This function is like wpa_printf(), but it also sends the
- * same message to all attached ctrl_iface monitors.
- *
- * Note: New line '\n' is added to the end of the text when printing to stdout.
- */
-void wpa_msg(void *ctx, int level, const char *fmt, ...) PRINTF_FORMAT(3, 4);
-
-/**
- * wpa_msg_ctrl - Conditional printf for ctrl_iface monitors
- * @ctx: Pointer to context data; this is the ctx variable registered
- *	with struct wpa_driver_ops::init()
- * @level: priority level (MSG_*) of the message
- * @fmt: printf format string, followed by optional arguments
- *
- * This function is used to print conditional debugging and error messages.
- * This function is like wpa_msg(), but it sends the output only to the
- * attached ctrl_iface monitors. In other words, it can be used for frequent
- * events that do not need to be sent to syslog.
- */
-void wpa_msg_ctrl(void *ctx, int level, const char *fmt, ...)
-PRINTF_FORMAT(3, 4);
-
-typedef void (*wpa_msg_cb_func)(void *ctx, int level, const char *txt,
-				size_t len);
-
-typedef void (*eloop_timeout_handler)(void *eloop_data, void *user_ctx);
-
-int eloop_cancel_timeout(eloop_timeout_handler handler,
-			 void *eloop_data, void *user_data);
-
-int eloop_register_timeout(unsigned int secs, unsigned int usecs,
-			   eloop_timeout_handler handler,
-			   void *eloop_data, void *user_data);
-
-
-#endif /* WPA_DEBUG_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpa_i.h b/tools/sdk/include/wpa_supplicant/wpa/wpa_i.h
deleted file mode 100644
index a43c33d332b..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpa_i.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Internal WPA/RSN supplicant state machine definitions
- * Copyright (c) 2004-2010, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef WPA_I_H
-#define WPA_I_H
-
-/**
- * set_key - Configure encryption key
- * @ifname: Interface name (for multi-SSID/VLAN support)
- * @priv: private driver interface data
- * @alg: encryption algorithm (%WPA_ALG_NONE, %WPA_ALG_WEP,
- *	%WPA_ALG_TKIP, %WPA_ALG_CCMP, %WPA_ALG_IGTK, %WPA_ALG_PMK);
- *	%WPA_ALG_NONE clears the key.
- * @addr: address of the peer STA or ff:ff:ff:ff:ff:ff for
- *	broadcast/default keys
- * @key_idx: key index (0..3), usually 0 for unicast keys; 0..4095 for
- *	IGTK
- * @set_tx: configure this key as the default Tx key (only used when
- *	driver does not support separate unicast/individual key
- * @seq: sequence number/packet number, seq_len octets, the next
- *	packet number to be used for in replay protection; configured
- *	for Rx keys (in most cases, this is only used with broadcast
- *	keys and set to zero for unicast keys)
- * @seq_len: length of the seq, depends on the algorithm:
- *	TKIP: 6 octets, CCMP: 6 octets, IGTK: 6 octets
- * @key: key buffer; TKIP: 16-byte temporal key, 8-byte Tx Mic key,
- *	8-byte Rx Mic Key
- * @key_len: length of the key buffer in octets (WEP: 5 or 13,
- *	TKIP: 32, CCMP: 16, IGTK: 16)
- *
- * Returns: 0 on success, -1 on failure
- *
- * Configure the given key for the kernel driver. If the driver
- * supports separate individual keys (4 default keys + 1 individual),
- * addr can be used to determine whether the key is default or
- * individual. If only 4 keys are supported, the default key with key
- * index 0 is used as the individual key. STA must be configured to use
- * it as the default Tx key (set_tx is set) and accept Rx for all the
- * key indexes. In most cases, WPA uses only key indexes 1 and 2 for
- * broadcast keys, so key index 0 is available for this kind of
- * configuration.
- *
- * Please note that TKIP keys include separate TX and RX MIC keys and
- * some drivers may expect them in different order than wpa_supplicant
- * is using. If the TX/RX keys are swapped, all TKIP encrypted packets
- * will tricker Michael MIC errors. This can be fixed by changing the
- * order of MIC keys by swapping te bytes 16..23 and 24..31 of the key
- * in driver_*.c set_key() implementation, see driver_ndis.c for an
- * example on how this can be done.
- */
-
-typedef void (* WPA_SEND_FUNC)(struct pbuf *pb);
-
-typedef void (* WPA_SET_ASSOC_IE)(uint8 proto, u8 *assoc_buf, u32 assoc_wpa_ie_len);
-
-typedef void (*WPA_INSTALL_KEY) (enum wpa_alg alg, uint8 *addr, int key_idx, int set_tx,
-               uint8 *seq, size_t seq_len, uint8 *key, size_t key_len, int key_entry_valid);
-
-typedef void (*WPA_DEAUTH)(uint8 reason_code);
-
-typedef void (*WPA_NEG_COMPLETE)();
-
-void wpa_register(char * payload, WPA_SEND_FUNC snd_func, \
-                                                      WPA_SET_ASSOC_IE set_assoc_ie_func, \
-                                                      WPA_INSTALL_KEY ppinstallkey, \
-                                                      WPA_DEAUTH wpa_deauth, \
-                                                      WPA_NEG_COMPLETE wpa_neg_complete);
-
-#include "pp/esf_buf.h"
-void eapol_txcb(esf_buf_t *eb);
-
-void wpa_set_profile(uint32 wpa_proto);
-
-void wpa_set_bss(char *macddr, char * bssid, uint8 pairwise_cipher, uint8 group_cipher, char *passphrase, u8 *ssid, size_t ssid_len);
-
-int wpa_sm_rx_eapol(u8 *src_addr, u8 *buf, u32 len);
-#endif /* WPA_I_H */
-
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpa_ie.h b/tools/sdk/include/wpa_supplicant/wpa/wpa_ie.h
deleted file mode 100644
index 94518d84578..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpa_ie.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * wpa_supplicant - WPA/RSN IE and KDE definitions
- * Copyright (c) 2004-2007, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef WPA_IE_H
-#define WPA_IE_H
-
-struct wpa_eapol_ie_parse {
-	const u8 *wpa_ie;
-	size_t wpa_ie_len;
-	const u8 *rsn_ie;
-	size_t rsn_ie_len;
-	const u8 *pmkid;
-	const u8 *gtk;
-	size_t gtk_len;
-	const u8 *mac_addr;
-	size_t mac_addr_len;
-#ifdef CONFIG_PEERKEY
-	const u8 *smk;
-	size_t smk_len;
-	const u8 *nonce;
-	size_t nonce_len;
-	const u8 *lifetime;
-	size_t lifetime_len;
-	const u8 *error;
-	size_t error_len;
-#endif /* CONFIG_PEERKEY */
-#ifdef CONFIG_IEEE80211W
-	const u8 *igtk;
-	size_t igtk_len;
-#endif /* CONFIG_IEEE80211W */
-#ifdef CONFIG_IEEE80211R
-	const u8 *mdie;
-	size_t mdie_len;
-	const u8 *ftie;
-	size_t ftie_len;
-	const u8 *reassoc_deadline;
-	const u8 *key_lifetime;
-#endif /* CONFIG_IEEE80211R */
-};
-
-int wpa_supplicant_parse_ies(const u8 *buf, size_t len,
-			     struct wpa_eapol_ie_parse *ie);
-int wpa_gen_wpa_ie(struct wpa_sm *sm, u8 *wpa_ie, size_t wpa_ie_len);
-
-#endif /* WPA_IE_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpabuf.h b/tools/sdk/include/wpa_supplicant/wpa/wpabuf.h
deleted file mode 100644
index cccfcc80ef1..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpabuf.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Dynamic data buffer
- * Copyright (c) 2007-2009, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef WPABUF_H
-#define WPABUF_H
-
-/*
- * Internal data structure for wpabuf. Please do not touch this directly from
- * elsewhere. This is only defined in header file to allow inline functions
- * from this file to access data.
- */
-struct wpabuf {
-	size_t size; /* total size of the allocated buffer */
-	size_t used; /* length of data in the buffer */
-	u8 *ext_data; /* pointer to external data; NULL if data follows
-		       * struct wpabuf */
-	/* optionally followed by the allocated buffer */
-};
-
-
-int wpabuf_resize(struct wpabuf **buf, size_t add_len);
-struct wpabuf * wpabuf_alloc(size_t len);
-struct wpabuf * wpabuf_alloc_ext_data(u8 *data, size_t len);
-struct wpabuf * wpabuf_alloc_copy(const void *data, size_t len);
-struct wpabuf * wpabuf_dup(const struct wpabuf *src);
-void wpabuf_free(struct wpabuf *buf);
-void * wpabuf_put(struct wpabuf *buf, size_t len);
-struct wpabuf * wpabuf_concat(struct wpabuf *a, struct wpabuf *b);
-struct wpabuf * wpabuf_zeropad(struct wpabuf *buf, size_t len);
-void wpabuf_printf(struct wpabuf *buf, char *fmt, ...) PRINTF_FORMAT(2, 3);
-
-
-/**
- * wpabuf_size - Get the currently allocated size of a wpabuf buffer
- * @buf: wpabuf buffer
- * Returns: Currently allocated size of the buffer
- */
-static inline size_t wpabuf_size(const struct wpabuf *buf)
-{
-	return buf->size;
-}
-
-/**
- * wpabuf_len - Get the current length of a wpabuf buffer data
- * @buf: wpabuf buffer
- * Returns: Currently used length of the buffer
- */
-static inline size_t wpabuf_len(const struct wpabuf *buf)
-{
-	return buf->used;
-}
-
-/**
- * wpabuf_tailroom - Get size of available tail room in the end of the buffer
- * @buf: wpabuf buffer
- * Returns: Tail room (in bytes) of available space in the end of the buffer
- */
-static inline size_t wpabuf_tailroom(const struct wpabuf *buf)
-{
-	return buf->size - buf->used;
-}
-
-/**
- * wpabuf_head - Get pointer to the head of the buffer data
- * @buf: wpabuf buffer
- * Returns: Pointer to the head of the buffer data
- */
-static inline const void * wpabuf_head(const struct wpabuf *buf)
-{
-	if (buf->ext_data)
-		return buf->ext_data;
-	return buf + 1;
-}
-
-static inline const u8 * wpabuf_head_u8(const struct wpabuf *buf)
-{
-	return wpabuf_head(buf);
-}
-
-/**
- * wpabuf_mhead - Get modifiable pointer to the head of the buffer data
- * @buf: wpabuf buffer
- * Returns: Pointer to the head of the buffer data
- */
-static inline void * wpabuf_mhead(struct wpabuf *buf)
-{
-	if (buf->ext_data)
-		return buf->ext_data;
-	return buf + 1;
-}
-
-static inline u8 * wpabuf_mhead_u8(struct wpabuf *buf)
-{
-	return wpabuf_mhead(buf);
-}
-
-static inline void wpabuf_put_u8(struct wpabuf *buf, u8 data)
-{
-	u8 *pos = wpabuf_put(buf, 1);
-	*pos = data;
-}
-
-static inline void wpabuf_put_le16(struct wpabuf *buf, u16 data)
-{
-	u8 *pos = wpabuf_put(buf, 2);
-	WPA_PUT_LE16(pos, data);
-}
-
-static inline void wpabuf_put_le32(struct wpabuf *buf, u32 data)
-{
-	u8 *pos = wpabuf_put(buf, 4);
-	WPA_PUT_LE32(pos, data);
-}
-
-static inline void wpabuf_put_be16(struct wpabuf *buf, u16 data)
-{
-	u8 *pos = wpabuf_put(buf, 2);
-	WPA_PUT_BE16(pos, data);
-}
-
-static inline void wpabuf_put_be24(struct wpabuf *buf, u32 data)
-{
-	u8 *pos = wpabuf_put(buf, 3);
-	WPA_PUT_BE24(pos, data);
-}
-
-static inline void wpabuf_put_be32(struct wpabuf *buf, u32 data)
-{
-	u8 *pos = wpabuf_put(buf, 4);
-	WPA_PUT_BE32(pos, data);
-}
-
-static inline void wpabuf_put_data(struct wpabuf *buf, const void *data,
-				   size_t len)
-{
-	if (data)
-		os_memcpy(wpabuf_put(buf, len), data, len);
-}
-
-static inline void wpabuf_put_buf(struct wpabuf *dst,
-				  const struct wpabuf *src)
-{
-	wpabuf_put_data(dst, wpabuf_head(src), wpabuf_len(src));
-}
-
-static inline void wpabuf_set(struct wpabuf *buf, const void *data, size_t len)
-{
-	buf->ext_data = (u8 *) data;
-	buf->size = buf->used = len;
-}
-
-static inline void wpabuf_put_str(struct wpabuf *dst, const char *str)
-{
-	wpabuf_put_data(dst, str, os_strlen(str));
-}
-
-#endif /* WPABUF_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa/wpas_glue.h b/tools/sdk/include/wpa_supplicant/wpa/wpas_glue.h
deleted file mode 100644
index 7e254a2d7d1..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa/wpas_glue.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * WPA Supplicant - Glue code to setup EAPOL and RSN modules
- * Copyright (c) 2003-2008, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef WPAS_GLUE_H
-#define WPAS_GLUE_H
-
-u8 * wpa_sm_alloc_eapol(struct wpa_sm *sm, u8 type,
-				      const void *data, u16 data_len,
-				      size_t *msg_len, void **data_pos);
-
-int wpa_sm_mlme_setprotection(struct wpa_sm *sm, const u8 *addr,
-					    int protect_type, int key_type);
-
-void wpa_sm_deauthenticate(struct wpa_sm *sm, uint8 reason_code);
-
-void wpa_sm_disassociate(struct wpa_sm *sm, int reason_code);
-
-int wpa_sm_get_beacon_ie(struct wpa_sm *sm);
-
-#endif /* WPAS_GLUE_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap.h
deleted file mode 100644
index 9e1c3efa94f..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * EAP peer state machine functions (RFC 4137)
- * Copyright (c) 2004-2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_H
-#define EAP_H
-
-#include "wpa/defs.h"
-#include "wpa2/eap_peer/eap_defs.h"
-
-struct eap_sm;
-
-struct eap_method_type {
-	int vendor;
-	EapType method;
-};
-
-u8 *g_wpa_anonymous_identity;
-int g_wpa_anonymous_identity_len;
-u8 *g_wpa_username;
-int g_wpa_username_len;
-const u8 *g_wpa_client_cert;
-int g_wpa_client_cert_len;
-const u8 *g_wpa_private_key;
-int g_wpa_private_key_len;
-const u8 *g_wpa_private_key_passwd;
-int g_wpa_private_key_passwd_len;
-
-const u8 *g_wpa_ca_cert;
-int g_wpa_ca_cert_len;
-
-u8 *g_wpa_password;
-int g_wpa_password_len;
-
-u8 *g_wpa_new_password;
-int g_wpa_new_password_len;
-
-const u8 * eap_get_eapKeyData(struct eap_sm *sm, size_t *len);
-void eap_deinit_prev_method(struct eap_sm *sm, const char *txt);
-struct wpabuf * eap_sm_build_nak(struct eap_sm *sm, EapType type, u8 id);
-int eap_peer_blob_init(struct eap_sm *sm);
-void eap_peer_blob_deinit(struct eap_sm *sm);
-int eap_peer_config_init(
-	struct eap_sm *sm, u8 *private_key_passwd,
-	int private_key_passwd_len);
-void eap_peer_config_deinit(struct eap_sm *sm);
-void eap_sm_abort(struct eap_sm *sm);
-int eap_peer_register_methods(void);
-
-#endif /* EAP_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_common.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_common.h
deleted file mode 100644
index 38c57100584..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_common.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * EAP common peer/server definitions
- * Copyright (c) 2004-2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_COMMON_H
-#define EAP_COMMON_H
-
-#include "wpa/wpabuf.h"
-
-int eap_hdr_len_valid(const struct wpabuf *msg, size_t min_payload);
-const u8 * eap_hdr_validate(int vendor, EapType eap_type,
-			    const struct wpabuf *msg, size_t *plen);
-struct wpabuf * eap_msg_alloc(int vendor, EapType type, size_t payload_len,
-			      u8 code, u8 identifier);
-void eap_update_len(struct wpabuf *msg);
-u8 eap_get_id(const struct wpabuf *msg);
-EapType eap_get_type(const struct wpabuf *msg);
-
-#endif /* EAP_COMMON_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_config.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_config.h
deleted file mode 100644
index f95dcda3a12..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_config.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * EAP peer configuration data
- * Copyright (c) 2003-2013, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_CONFIG_H
-#define EAP_CONFIG_H
-
-/**
- * struct eap_peer_config - EAP peer configuration/credentials
- */
-struct eap_peer_config {
-	/**
-	 * identity - EAP Identity
-	 *
-	 * This field is used to set the real user identity or NAI (for
-	 * EAP-PSK/PAX/SAKE/GPSK).
-	 */
-	u8 *identity;
-
-	/**
-	 * identity_len - EAP Identity length
-	 */
-	size_t identity_len;
-
-	u8 *anonymous_identity;
-
-	size_t anonymous_identity_len;
-
-	/**
-	 * password - Password string for EAP
-	 *
-	 * This field can include either the plaintext password (default
-	 * option) or a NtPasswordHash (16-byte MD4 hash of the unicode
-	 * presentation of the password) if flags field has
-	 * EAP_CONFIG_FLAGS_PASSWORD_NTHASH bit set to 1. NtPasswordHash can
-	 * only be used with authentication mechanism that use this hash as the
-	 * starting point for operation: MSCHAP and MSCHAPv2 (EAP-MSCHAPv2,
-	 * EAP-TTLS/MSCHAPv2, EAP-TTLS/MSCHAP, LEAP).
-	 *
-	 * In addition, this field is used to configure a pre-shared key for
-	 * EAP-PSK/PAX/SAKE/GPSK. The length of the PSK must be 16 for EAP-PSK
-	 * and EAP-PAX and 32 for EAP-SAKE. EAP-GPSK can use a variable length
-	 * PSK.
-	 */
-	u8 *password;
-
-	/**
-	 * password_len - Length of password field
-	 */
-	size_t password_len;
-
-	/**
-	 * ca_cert - File path to CA certificate file (PEM/DER)
-	 *
-	 * This file can have one or more trusted CA certificates. If ca_cert
-	 * and ca_path are not included, server certificate will not be
-	 * verified. This is insecure and a trusted CA certificate should
-	 * always be configured when using EAP-TLS/TTLS/PEAP. Full path to the
-	 * file should be used since working directory may change when
-	 * wpa_supplicant is run in the background.
-	 *
-	 * Alternatively, a named configuration blob can be used by setting
-	 * this to blob://blob_name.
-	 *
-	 * Alternatively, this can be used to only perform matching of the
-	 * server certificate (SHA-256 hash of the DER encoded X.509
-	 * certificate). In this case, the possible CA certificates in the
-	 * server certificate chain are ignored and only the server certificate
-	 * is verified. This is configured with the following format:
-	 * hash:://server/sha256/cert_hash_in_hex
-	 * For example: "hash://server/sha256/
-	 * 5a1bc1296205e6fdbe3979728efe3920798885c1c4590b5f90f43222d239ca6a"
-	 *
-	 * On Windows, trusted CA certificates can be loaded from the system
-	 * certificate store by setting this to cert_store://name, e.g.,
-	 * ca_cert="cert_store://CA" or ca_cert="cert_store://ROOT".
-	 * Note that when running wpa_supplicant as an application, the user
-	 * certificate store (My user account) is used, whereas computer store
-	 * (Computer account) is used when running wpasvc as a service.
-	 */
-	u8 *ca_cert;
-
-	/**
-	 * ca_path - Directory path for CA certificate files (PEM)
-	 *
-	 * This path may contain multiple CA certificates in OpenSSL format.
-	 * Common use for this is to point to system trusted CA list which is
-	 * often installed into directory like /etc/ssl/certs. If configured,
-	 * these certificates are added to the list of trusted CAs. ca_cert
-	 * may also be included in that case, but it is not required.
-	 */
-	u8 *ca_path;
-
-	/**
-	 * client_cert - File path to client certificate file (PEM/DER)
-	 *
-	 * This field is used with EAP method that use TLS authentication.
-	 * Usually, this is only configured for EAP-TLS, even though this could
-	 * in theory be used with EAP-TTLS and EAP-PEAP, too. Full path to the
-	 * file should be used since working directory may change when
-	 * wpa_supplicant is run in the background.
-	 *
-	 * Alternatively, a named configuration blob can be used by setting
-	 * this to blob://blob_name.
-	 */
-	u8 *client_cert;
-
-	/**
-	 * private_key - File path to client private key file (PEM/DER/PFX)
-	 *
-	 * When PKCS#12/PFX file (.p12/.pfx) is used, client_cert should be
-	 * commented out. Both the private key and certificate will be read
-	 * from the PKCS#12 file in this case. Full path to the file should be
-	 * used since working directory may change when wpa_supplicant is run
-	 * in the background.
-	 *
-	 * Windows certificate store can be used by leaving client_cert out and
-	 * configuring private_key in one of the following formats:
-	 *
-	 * cert://substring_to_match
-	 *
-	 * hash://certificate_thumbprint_in_hex
-	 *
-	 * For example: private_key="hash://63093aa9c47f56ae88334c7b65a4"
-	 *
-	 * Note that when running wpa_supplicant as an application, the user
-	 * certificate store (My user account) is used, whereas computer store
-	 * (Computer account) is used when running wpasvc as a service.
-	 *
-	 * Alternatively, a named configuration blob can be used by setting
-	 * this to blob://blob_name.
-	 */
-	u8 *private_key;
-
-	/**
-	 * private_key_passwd - Password for private key file
-	 *
-	 * If left out, this will be asked through control interface.
-	 */
-	u8 *private_key_passwd;
-
-	/**
-	 * Phase 2
-	 */
-	u8 *ca_cert2;
-
-	u8 *ca_path2;
-
-	u8 *client_cert2;
-
-	u8 *private_key2;
-
-	u8 *private_key2_password;
-
-	/**
-	 * eap_methods - Allowed EAP methods
-	 */
-	struct eap_method_type *eap_methods;
-
-
-	char *phase1;
-
-	char *phase2;
-
-	/**
-	 * pin - PIN for USIM, GSM SIM, and smartcards
-	 *
-	 * This field is used to configure PIN for SIM and smartcards for
-	 * EAP-SIM and EAP-AKA. In addition, this is used with EAP-TLS if a
-	 * smartcard is used for private key operations.
-	 *
-	 * If left out, this will be asked through control interface.
-	 */
-	char *pin;
-
-	int mschapv2_retry;
-	u8 *new_password;
-	size_t new_password_len;
-
-	/**
-	 * fragment_size - Maximum EAP fragment size in bytes (default 1398)
-	 *
-	 * This value limits the fragment size for EAP methods that support
-	 * fragmentation (e.g., EAP-TLS and EAP-PEAP). This value should be set
-	 * small enough to make the EAP messages fit in MTU of the network
-	 * interface used for EAPOL. The default value is suitable for most
-	 * cases.
-	 */
-	int fragment_size;
-
-#define EAP_CONFIG_FLAGS_PASSWORD_NTHASH BIT(0)
-#define EAP_CONFIG_FLAGS_EXT_PASSWORD BIT(1)
-	/**
-	 * flags - Network configuration flags (bitfield)
-	 *
-	 * This variable is used for internal flags to describe further details
-	 * for the network parameters.
-	 * bit 0 = password is represented as a 16-byte NtPasswordHash value
-	 *         instead of plaintext password
-	 * bit 1 = password is stored in external storage; the value in the
-	 *         password field is the name of that external entry
-	 */
-	u32 flags;
-
-	/**
-	 * ocsp - Whether to use/require OCSP to check server certificate
-	 *
-	 * 0 = do not use OCSP stapling (TLS certificate status extension)
-	 * 1 = try to use OCSP stapling, but not require response
-	 * 2 = require valid OCSP stapling response
-	 */
-	int ocsp;
-};
-
-
-/**
- * struct wpa_config_blob - Named configuration blob
- *
- * This data structure is used to provide storage for binary objects to store
- * abstract information like certificates and private keys inlined with the
- * configuration data.
- */
-struct wpa_config_blob {
-	/**
-	 * name - Blob name
-	 */
-	char *name;
-
-	/**
-	 * data - Pointer to binary data
-	 */
-	const u8 *data;
-
-	/**
-	 * len - Length of binary data
-	 */
-	size_t len;
-
-	/**
-	 * next - Pointer to next blob in the configuration
-	 */
-	struct wpa_config_blob *next;
-};
-
-#endif /* EAP_CONFIG_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_defs.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_defs.h
deleted file mode 100644
index 10995d3868e..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_defs.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * EAP server/peer: Shared EAP definitions
- * Copyright (c) 2004-2007, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_DEFS_H
-#define EAP_DEFS_H
-
-/* RFC 3748 - Extensible Authentication Protocol (EAP) */
-
-#ifdef _MSC_VER
-#pragma pack(push, 1)
-#endif /* _MSC_VER */
-
-struct eap_hdr {
-	u8 code;
-	u8 identifier;
-	be16 length; /* including code and identifier; network byte order */
-	/* followed by length-4 octets of data */
-} STRUCT_PACKED;
-
-
-#ifdef _MSC_VER
-#pragma pack(pop)
-#endif /* _MSC_VER */
-
-enum { EAP_CODE_REQUEST = 1, EAP_CODE_RESPONSE = 2, EAP_CODE_SUCCESS = 3,
-       EAP_CODE_FAILURE = 4 };
-
-/* EAP Request and Response data begins with one octet Type. Success and
- * Failure do not have additional data. */
-
-/*
- * EAP Method Types as allocated by IANA:
- * http://www.iana.org/assignments/eap-numbers
- */
-typedef enum {
-	EAP_TYPE_NONE = 0,
-	EAP_TYPE_IDENTITY = 1 /* RFC 3748 */,
-	EAP_TYPE_NOTIFICATION = 2 /* RFC 3748 */,
-	EAP_TYPE_NAK = 3 /* Response only, RFC 3748 */,
-	EAP_TYPE_MD5 = 4, /* RFC 3748 */
-	EAP_TYPE_OTP = 5 /* RFC 3748 */,
-	EAP_TYPE_GTC = 6, /* RFC 3748 */
-	EAP_TYPE_TLS = 13 /* RFC 2716 */,
-	EAP_TYPE_LEAP = 17 /* Cisco proprietary */,
-	EAP_TYPE_SIM = 18 /* RFC 4186 */,
-	EAP_TYPE_TTLS = 21 /* RFC 5281 */,
-	EAP_TYPE_AKA = 23 /* RFC 4187 */,
-	EAP_TYPE_PEAP = 25 /* draft-josefsson-pppext-eap-tls-eap-06.txt */,
-	EAP_TYPE_MSCHAPV2 = 26 /* draft-kamath-pppext-eap-mschapv2-00.txt */,
-	EAP_TYPE_TLV = 33 /* draft-josefsson-pppext-eap-tls-eap-07.txt */,
-	EAP_TYPE_TNC = 38 /* TNC IF-T v1.0-r3; note: tentative assignment;
-			   * type 38 has previously been allocated for
-			   * EAP-HTTP Digest, (funk.com) */,
-	EAP_TYPE_FAST = 43 /* RFC 4851 */,
-	EAP_TYPE_PAX = 46 /* RFC 4746 */,
-	EAP_TYPE_PSK = 47 /* RFC 4764 */,
-	EAP_TYPE_SAKE = 48 /* RFC 4763 */,
-	EAP_TYPE_IKEV2 = 49 /* RFC 5106 */,
-	EAP_TYPE_AKA_PRIME = 50 /* RFC 5448 */,
-	EAP_TYPE_GPSK = 51 /* RFC 5433 */,
-	EAP_TYPE_PWD = 52 /* RFC 5931 */,
-	EAP_TYPE_EKE = 53 /* RFC 6124 */,
-	EAP_TYPE_EXPANDED = 254 /* RFC 3748 */
-} EapType;
-
-
-/* SMI Network Management Private Enterprise Code for vendor specific types */
-enum {
-	EAP_VENDOR_IETF = 0,
-	EAP_VENDOR_MICROSOFT = 0x000137 /* Microsoft */,
-	EAP_VENDOR_WFA = 0x00372A /* Wi-Fi Alliance */,
-	EAP_VENDOR_HOSTAP = 39068 /* hostapd/wpa_supplicant project */
-};
-
-struct eap_expand {
-    u8 vendor_id[3];
-    be32 vendor_type;
-    u8 opcode;
-} STRUCT_PACKED;
-
-#define EAP_VENDOR_UNAUTH_TLS EAP_VENDOR_HOSTAP
-#define EAP_VENDOR_TYPE_UNAUTH_TLS 1
-
-#define EAP_MSK_LEN 64
-#define EAP_EMSK_LEN 64
-
-#endif /* EAP_DEFS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_i.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_i.h
deleted file mode 100644
index 99a47a7a11e..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_i.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * EAP peer state machines internal structures (RFC 4137)
- * Copyright (c) 2004-2007, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_I_H
-#define EAP_I_H
-
-#include "wpa/wpabuf.h"
-#include "eap.h"
-#include "eap_common.h"
-#include "eap_config.h"
-#include "esp_wpa2.h"
-
-/* RFC 4137 - EAP Peer state machine */
-
-typedef enum {
-	DECISION_FAIL, DECISION_COND_SUCC, DECISION_UNCOND_SUCC
-} EapDecision;
-
-typedef enum {
-	METHOD_NONE, METHOD_INIT, METHOD_CONT, METHOD_MAY_CONT, METHOD_DONE
-} EapMethodState;
-
-/**
- * struct eap_method_ret - EAP return values from struct eap_method::process()
- *
- * These structure contains OUT variables for the interface between peer state
- * machine and methods (RFC 4137, Sect. 4.2). eapRespData will be returned as
- * the return value of struct eap_method::process() so it is not included in
- * this structure.
- */
-struct eap_method_ret {
-	/**
-	 * ignore - Whether method decided to drop the current packed (OUT)
-	 */
-	Boolean ignore;
-
-	/**
-	 * methodState - Method-specific state (IN/OUT)
-	 */
-	EapMethodState methodState;
-
-	/**
-	 * decision - Authentication decision (OUT)
-	 */
-	EapDecision decision;
-
-	/**
-	 * allowNotifications - Whether method allows notifications (OUT)
-	 */
-	Boolean allowNotifications;
-};
-
-struct eap_sm;
-
-struct eap_method {
-	/**
-	 * vendor -EAP Vendor-ID
-	 */
-	int vendor;
-
-	/**
-	 * method - EAP type number
-	 */
-	EapType method;	
-
-	/**
-	 * name - Name of the method (e.g., "TLS")
-	 */
-	const char *name;
-
-	struct eap_method *next;
-
-	void * (*init)(struct eap_sm *sm);
-	void (*deinit)(struct eap_sm *sm, void *priv);
-	struct wpabuf * (*process)(struct eap_sm *sm, void *priv,
-				   struct eap_method_ret *ret,
-				   const struct wpabuf *reqData);
-	bool (*isKeyAvailable)(struct eap_sm *sm, void *priv);
-	u8 * (*getKey)(struct eap_sm *sm, void *priv, size_t *len);
-	int (*get_status)(struct eap_sm *sm, void *priv, char *buf,
-			  size_t buflen, int verbose);
-	const u8 * (*get_identity)(struct eap_sm *sm, void *priv, size_t *len);
-	void (*free)(struct eap_method *method);
-	bool (*has_reauth_data)(struct eap_sm *sm, void *priv);
-	void (*deinit_for_reauth)(struct eap_sm *sm, void *priv);
-	void * (*init_for_reauth)(struct eap_sm *sm, void *priv);
-	u8 * (*getSessionId)(struct eap_sm *sm, void *priv, size_t *len);
-};
-
-#define CLIENT_CERT_NAME	"CLC"
-#define CA_CERT_NAME		"CAC"
-#define PRIVATE_KEY_NAME	"PVK"
-#define BLOB_NAME_LEN		3
-#define BLOB_NUM		3
-
-
-enum SIG_WPA2 {
-	    SIG_WPA2_START = 0,
-	    SIG_WPA2_RX,
-	    SIG_WPA2_TASK_DEL,
-	    SIG_WPA2_MAX,
-	};
-
-/**
- * struct eap_sm - EAP state machine data
- */
-struct eap_sm {
-	void *eap_method_priv;
-
-	void *ssl_ctx;
-
-	unsigned int workaround;
-/////////////////////////////////////////////////
-        struct pbuf *outbuf;
-	struct wpa_config_blob blob[BLOB_NUM];
-	struct eap_peer_config config;
-	u8 current_identifier;
-	u8 ownaddr[ETH_ALEN];
-#ifdef USE_WPA2_TASK
-    	u8 wpa2_sig_cnt[SIG_WPA2_MAX];
-#endif
-	u8 finish_state;
-
-	int init_phase2;
-	bool peap_done;
-
-	u8 *eapKeyData;
-	size_t eapKeyDataLen;
-	struct wpabuf *lastRespData;
-	const struct eap_method *m;
-};
-
-wpa2_crypto_funcs_t wpa2_crypto_funcs;
-
-const u8 * eap_get_config_identity(struct eap_sm *sm, size_t *len);
-const u8 * eap_get_config_password(struct eap_sm *sm, size_t *len);
-const u8 * eap_get_config_password2(struct eap_sm *sm, size_t *len, int *hash);
-const u8 * eap_get_config_new_password(struct eap_sm *sm, size_t *len);
-struct eap_peer_config * eap_get_config(struct eap_sm *sm);
-const struct wpa_config_blob * eap_get_config_blob(struct eap_sm *sm, const char *name);
-bool wifi_sta_get_enterprise_disable_time_check(void);
-
-struct wpabuf * eap_sm_build_identity_resp(struct eap_sm *sm, u8 id, int encrypted);
-
-#endif /* EAP_I_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_methods.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_methods.h
deleted file mode 100644
index 7d518dec2ce..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_methods.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * EAP peer: Method registration
- * Copyright (c) 2004-2007, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_METHODS_H
-#define EAP_METHODS_H
-
-#include "eap_defs.h"
-#include "eap_config.h"
-
-const struct eap_method * eap_peer_get_eap_method(int vendor, EapType method);
-const struct eap_method * eap_peer_get_methods(size_t *count);
-
-u32 eap_get_phase2_type(const char *name, int *vendor);
-struct eap_method_type * eap_get_phase2_types(struct eap_peer_config *config,
-					      size_t *count);
-
-struct eap_method * eap_peer_method_alloc(int verdor, EapType method,
-					  const char *name);
-
-void eap_peer_method_free(struct eap_method *method);
-int eap_peer_method_register(struct eap_method *method);
-
-void eap_peer_unregister_methods(void);
-
-//int eap_peer_md5_register(void);
-int eap_peer_tls_register(void);
-int eap_peer_peap_register(void);
-int eap_peer_ttls_register(void);
-int eap_peer_mschapv2_register(void);
-
-void eap_peer_unregister_methods(void);
-int eap_peer_register_methods(void);
-
-#endif /* EAP_METHODS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_peap_common.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_peap_common.h
deleted file mode 100644
index 7aad0dff781..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_peap_common.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * EAP-PEAP common routines
- * Copyright (c) 2008-2011, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_PEAP_COMMON_H
-#define EAP_PEAP_COMMON_H
-
-int peap_prfplus(int version, const u8 *key, size_t key_len,
-		 const char *label, const u8 *seed, size_t seed_len,
-		 u8 *buf, size_t buf_len);
-
-#endif /* EAP_PEAP_COMMON_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_tls.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_tls.h
deleted file mode 100644
index a8a386f22c7..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_tls.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * EAP peer: EAP-TLS/PEAP/TTLS/FAST common functions
- * Copyright (c) 2004-2009, 2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_TLS_H
-#define EAP_TLS_H
-
-#include "eap_i.h"
-#include "eap_common.h" 
-#include "eap.h" 
-#include "wpa/wpabuf.h" 
-
-void * eap_tls_init(struct eap_sm *sm);
-void eap_tls_deinit(struct eap_sm *sm, void *priv);
-struct wpabuf * eap_tls_process(struct eap_sm *sm, void *priv,
-                                       struct eap_method_ret *ret,
-                                       const struct wpabuf *reqData);
-
-u8 * eap_tls_getKey(struct eap_sm *sm, void *priv, size_t *len);
-
-#endif /* EAP_TLS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_tls_common.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_tls_common.h
deleted file mode 100644
index 1a5e0f89e4e..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_tls_common.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * EAP peer: EAP-TLS/PEAP/TTLS/FAST common functions
- * Copyright (c) 2004-2009, 2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_TLS_COMMON_H
-#define EAP_TLS_COMMON_H
-
-/**
- * struct eap_ssl_data - TLS data for EAP methods
- */
-struct eap_ssl_data {
-	/**
-	 * conn - TLS connection context data from tls_connection_init()
-	 */
-	struct tls_connection *conn;
-
-	/**
-	 * tls_out - TLS message to be sent out in fragments
-	 */
-	struct wpabuf *tls_out;
-
-	/**
-	 * tls_out_pos - The current position in the outgoing TLS message
-	 */
-	size_t tls_out_pos;
-
-	/**
-	 * tls_out_limit - Maximum fragment size for outgoing TLS messages
-	 */
-	size_t tls_out_limit;
-
-	/**
-	 * tls_in - Received TLS message buffer for re-assembly
-	 */
-	struct wpabuf *tls_in;
-
-	/**
-	 * tls_in_left - Number of remaining bytes in the incoming TLS message
-	 */
-	size_t tls_in_left;
-
-	/**
-	 * tls_in_total - Total number of bytes in the incoming TLS message
-	 */
-	size_t tls_in_total;
-
-	/**
-	 * phase2 - Whether this TLS connection is used in EAP phase 2 (tunnel)
-	 */
-	int phase2;
-
-	/**
-	 * include_tls_length - Whether the TLS length field is included even
-	 * if the TLS data is not fragmented
-	 */
-	int include_tls_length;
-
-	/**
-	 * eap - EAP state machine allocated with eap_peer_sm_init()
-	 */
-	struct eap_sm *eap;
-
-	/**
-	 * ssl_ctx - TLS library context to use for the connection
-	 */
-	void *ssl_ctx;
-
-	/**
-	 * eap_type - EAP method used in Phase 1 (EAP_TYPE_TLS/PEAP/TTLS/FAST)
-	 */
-	u8 eap_type;
-};
-
-
-/* EAP TLS Flags */
-#define EAP_TLS_FLAGS_LENGTH_INCLUDED 0x80
-#define EAP_TLS_FLAGS_MORE_FRAGMENTS 0x40
-#define EAP_TLS_FLAGS_START 0x20
-#define EAP_TLS_VERSION_MASK 0x07
-
- /* could be up to 128 bytes, but only the first 64 bytes are used */
-#define EAP_TLS_KEY_LEN 64
-
-/* dummy type used as a flag for UNAUTH-TLS */
-#define EAP_UNAUTH_TLS_TYPE 255
-
-
-int eap_peer_tls_ssl_init(struct eap_sm *sm, struct eap_ssl_data *data,
-			  struct eap_peer_config *config, u8 eap_type);
-void eap_peer_tls_ssl_deinit(struct eap_sm *sm, struct eap_ssl_data *data);
-u8 * eap_peer_tls_derive_key(struct eap_sm *sm, struct eap_ssl_data *data,
-			     const char *label, size_t len);
-u8 * eap_peer_tls_derive_session_id(struct eap_sm *sm,
-				    struct eap_ssl_data *data, u8 eap_type,
-				    size_t *len);
-int eap_peer_tls_process_helper(struct eap_sm *sm, struct eap_ssl_data *data,
-				EapType eap_type, int peap_version,
-				u8 id, const u8 *in_data, size_t in_len,
-				struct wpabuf **out_data);
-struct wpabuf * eap_peer_tls_build_ack(u8 id, EapType eap_type,
-				       int peap_version);
-int eap_peer_tls_reauth_init(struct eap_sm *sm, struct eap_ssl_data *data);
-int eap_peer_tls_status(struct eap_sm *sm, struct eap_ssl_data *data,
-			char *buf, size_t buflen, int verbose);
-const u8 * eap_peer_tls_process_init(struct eap_sm *sm,
-				     struct eap_ssl_data *data,
-				     EapType eap_type,
-				     struct eap_method_ret *ret,
-				     const struct wpabuf *reqData,
-				     size_t *len, u8 *flags);
-void eap_peer_tls_reset_input(struct eap_ssl_data *data);
-void eap_peer_tls_reset_output(struct eap_ssl_data *data);
-int eap_peer_tls_decrypt(struct eap_sm *sm, struct eap_ssl_data *data,
-			 const struct wpabuf *in_data,
-			 struct wpabuf **in_decrypted);
-int eap_peer_tls_encrypt(struct eap_sm *sm, struct eap_ssl_data *data,
-			 EapType eap_type, int peap_version, u8 id,
-			 const struct wpabuf *in_data,
-			 struct wpabuf **out_data);
-int eap_peer_select_phase2_methods(struct eap_peer_config *config,
-				   const char *prefix,
-				   struct eap_method_type **types,
-				   size_t *num_types);
-int eap_peer_tls_phase2_nak(struct eap_method_type *types, size_t num_types,
-			    struct eap_hdr *hdr, struct wpabuf **resp);
-
-#endif /* EAP_TLS_COMMON_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_tlv_common.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_tlv_common.h
deleted file mode 100644
index 3286055ab7b..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_tlv_common.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * EAP-TLV definitions (draft-josefsson-pppext-eap-tls-eap-10.txt)
- * Copyright (c) 2004-2008, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_TLV_COMMON_H
-#define EAP_TLV_COMMON_H
-
-/* EAP-TLV TLVs (draft-josefsson-ppext-eap-tls-eap-10.txt) */
-#define EAP_TLV_RESULT_TLV 3 /* Acknowledged Result */
-#define EAP_TLV_NAK_TLV 4
-#define EAP_TLV_ERROR_CODE_TLV 5
-#define EAP_TLV_CONNECTION_BINDING_TLV 6
-#define EAP_TLV_VENDOR_SPECIFIC_TLV 7
-#define EAP_TLV_URI_TLV 8
-#define EAP_TLV_EAP_PAYLOAD_TLV 9
-#define EAP_TLV_INTERMEDIATE_RESULT_TLV 10
-#define EAP_TLV_PAC_TLV 11 /* RFC 5422, Section 4.2 */
-#define EAP_TLV_CRYPTO_BINDING_TLV 12
-#define EAP_TLV_CALLING_STATION_ID_TLV 13
-#define EAP_TLV_CALLED_STATION_ID_TLV 14
-#define EAP_TLV_NAS_PORT_TYPE_TLV 15
-#define EAP_TLV_SERVER_IDENTIFIER_TLV 16
-#define EAP_TLV_IDENTITY_TYPE_TLV 17
-#define EAP_TLV_SERVER_TRUSTED_ROOT_TLV 18
-#define EAP_TLV_REQUEST_ACTION_TLV 19
-#define EAP_TLV_PKCS7_TLV 20
-
-#define EAP_TLV_RESULT_SUCCESS 1
-#define EAP_TLV_RESULT_FAILURE 2
-
-#define EAP_TLV_TYPE_MANDATORY 0x8000
-#define EAP_TLV_TYPE_MASK 0x3fff
-
-#ifdef _MSC_VER
-#pragma pack(push, 1)
-#endif /* _MSC_VER */
-
-struct eap_tlv_hdr {
-	be16 tlv_type;
-	be16 length;
-} STRUCT_PACKED;
-
-struct eap_tlv_nak_tlv {
-	be16 tlv_type;
-	be16 length;
-	be32 vendor_id;
-	be16 nak_type;
-} STRUCT_PACKED;
-
-struct eap_tlv_result_tlv {
-	be16 tlv_type;
-	be16 length;
-	be16 status;
-} STRUCT_PACKED;
-
-/* RFC 4851, Section 4.2.7 - Intermediate-Result TLV */
-struct eap_tlv_intermediate_result_tlv {
-	be16 tlv_type;
-	be16 length;
-	be16 status;
-	/* Followed by optional TLVs */
-} STRUCT_PACKED;
-
-/* RFC 4851, Section 4.2.8 - Crypto-Binding TLV */
-struct eap_tlv_crypto_binding_tlv {
-	be16 tlv_type;
-	be16 length;
-	u8 reserved;
-	u8 version;
-	u8 received_version;
-	u8 subtype;
-	u8 nonce[32];
-	u8 compound_mac[20];
-} STRUCT_PACKED;
-
-struct eap_tlv_pac_ack_tlv {
-	be16 tlv_type;
-	be16 length;
-	be16 pac_type;
-	be16 pac_len;
-	be16 result;
-} STRUCT_PACKED;
-
-/* RFC 4851, Section 4.2.9 - Request-Action TLV */
-struct eap_tlv_request_action_tlv {
-	be16 tlv_type;
-	be16 length;
-	be16 action;
-} STRUCT_PACKED;
-
-/* RFC 5422, Section 4.2.6 - PAC-Type TLV */
-struct eap_tlv_pac_type_tlv {
-	be16 tlv_type; /* PAC_TYPE_PAC_TYPE */
-	be16 length;
-	be16 pac_type;
-} STRUCT_PACKED;
-
-#ifdef _MSC_VER
-#pragma pack(pop)
-#endif /* _MSC_VER */
-
-#define EAP_TLV_CRYPTO_BINDING_SUBTYPE_REQUEST 0
-#define EAP_TLV_CRYPTO_BINDING_SUBTYPE_RESPONSE 1
-
-#define EAP_TLV_ACTION_PROCESS_TLV 1
-#define EAP_TLV_ACTION_NEGOTIATE_EAP 2
-
-#endif /* EAP_TLV_COMMON_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_ttls.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_ttls.h
deleted file mode 100644
index 17901d42db1..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/eap_ttls.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * EAP server/peer: EAP-TTLS (RFC 5281)
- * Copyright (c) 2004-2007, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EAP_TTLS_H
-#define EAP_TTLS_H
-
-struct ttls_avp {
-	be32 avp_code;
-	be32 avp_length; /* 8-bit flags, 24-bit length;
-			  * length includes AVP header */
-	/* optional 32-bit Vendor-ID */
-	/* Data */
-};
-
-struct ttls_avp_vendor {
-	be32 avp_code;
-	be32 avp_length; /* 8-bit flags, 24-bit length;
-			  * length includes AVP header */
-	be32 vendor_id;
-	/* Data */
-};
-
-#define AVP_FLAGS_VENDOR 0x80
-#define AVP_FLAGS_MANDATORY 0x40
-
-#define AVP_PAD(start, pos) \
-do { \
-	int __pad; \
-	__pad = (4 - (((pos) - (start)) & 3)) & 3; \
-	os_memset((pos), 0, __pad); \
-	pos += __pad; \
-} while (0)
-
-
-/* RFC 2865 */
-#define RADIUS_ATTR_USER_NAME 1
-#define RADIUS_ATTR_USER_PASSWORD 2
-#define RADIUS_ATTR_CHAP_PASSWORD 3
-#define RADIUS_ATTR_REPLY_MESSAGE 18
-#define RADIUS_ATTR_CHAP_CHALLENGE 60
-#define RADIUS_ATTR_EAP_MESSAGE 79
-
-/* RFC 2548 */
-#define RADIUS_VENDOR_ID_MICROSOFT 311
-#define RADIUS_ATTR_MS_CHAP_RESPONSE 1
-#define RADIUS_ATTR_MS_CHAP_ERROR 2
-#define RADIUS_ATTR_MS_CHAP_NT_ENC_PW 6
-#define RADIUS_ATTR_MS_CHAP_CHALLENGE 11
-#define RADIUS_ATTR_MS_CHAP2_RESPONSE 25
-#define RADIUS_ATTR_MS_CHAP2_SUCCESS 26
-#define RADIUS_ATTR_MS_CHAP2_CPW 27
-
-#define EAP_TTLS_MSCHAPV2_CHALLENGE_LEN 16
-#define EAP_TTLS_MSCHAPV2_RESPONSE_LEN 50
-#define EAP_TTLS_MSCHAP_CHALLENGE_LEN 8
-#define EAP_TTLS_MSCHAP_RESPONSE_LEN 50
-#define EAP_TTLS_CHAP_CHALLENGE_LEN 16
-#define EAP_TTLS_CHAP_PASSWORD_LEN 16
-
-#endif /* EAP_TTLS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/mschapv2.h b/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/mschapv2.h
deleted file mode 100644
index ef750819ffe..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/eap_peer/mschapv2.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * MSCHAPV2
- */
-
-
-#ifndef MSCHAPV2_H
-#define MSCHAPV2_H
-
-#define MSCHAPV2_CHAL_LEN		16
-#define MSCHAPV2_NT_RESPONSE_LEN	24
-#define MSCHAPV2_AUTH_RESPONSE_LEN	20
-#define MSCHAPV2_MASTER_KEY_LEN		16
-
-const u8 * mschapv2_remove_domain(const u8 *username, size_t *len);
-int mschapv2_derive_response(const u8 *username, size_t username_len,
-			     const u8 *password, size_t password_len,
-			     int pwhash,
-			     const u8 *auth_challenge,
-			     const u8 *peer_challenge,
-			     u8 *nt_response, u8 *auth_response,
-			     u8 *master_key);
-int mschapv2_verify_auth_response(const u8 *auth_response,
-				  const u8 *buf, size_t buf_len);
-#endif /* MSCHAPV2_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/asn1.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/asn1.h
deleted file mode 100644
index 6342c4cc79f..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/asn1.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * ASN.1 DER parsing
- * Copyright (c) 2006, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef ASN1_H
-#define ASN1_H
-
-#define ASN1_TAG_EOC		0x00 /* not used with DER */
-#define ASN1_TAG_BOOLEAN	0x01
-#define ASN1_TAG_INTEGER	0x02
-#define ASN1_TAG_BITSTRING	0x03
-#define ASN1_TAG_OCTETSTRING	0x04
-#define ASN1_TAG_NULL		0x05
-#define ASN1_TAG_OID		0x06
-#define ASN1_TAG_OBJECT_DESCRIPTOR	0x07 /* not yet parsed */
-#define ASN1_TAG_EXTERNAL	0x08 /* not yet parsed */
-#define ASN1_TAG_REAL		0x09 /* not yet parsed */
-#define ASN1_TAG_ENUMERATED	0x0A /* not yet parsed */
-#define ASN1_TAG_UTF8STRING	0x0C /* not yet parsed */
-#define ANS1_TAG_RELATIVE_OID	0x0D
-#define ASN1_TAG_SEQUENCE	0x10 /* shall be constructed */
-#define ASN1_TAG_SET		0x11
-#define ASN1_TAG_NUMERICSTRING	0x12 /* not yet parsed */
-#define ASN1_TAG_PRINTABLESTRING	0x13
-#define ASN1_TAG_TG1STRING	0x14 /* not yet parsed */
-#define ASN1_TAG_VIDEOTEXSTRING	0x15 /* not yet parsed */
-#define ASN1_TAG_IA5STRING	0x16
-#define ASN1_TAG_UTCTIME	0x17
-#define ASN1_TAG_GENERALIZEDTIME	0x18 /* not yet parsed */
-#define ASN1_TAG_GRAPHICSTRING	0x19 /* not yet parsed */
-#define ASN1_TAG_VISIBLESTRING	0x1A
-#define ASN1_TAG_GENERALSTRING	0x1B /* not yet parsed */
-#define ASN1_TAG_UNIVERSALSTRING	0x1C /* not yet parsed */
-#define ASN1_TAG_BMPSTRING	0x1D /* not yet parsed */
-
-#define ASN1_CLASS_UNIVERSAL		0
-#define ASN1_CLASS_APPLICATION		1
-#define ASN1_CLASS_CONTEXT_SPECIFIC	2
-#define ASN1_CLASS_PRIVATE		3
-
-
-struct asn1_hdr {
-	const u8 *payload;
-	u8 identifier, class, constructed;
-	unsigned int tag, length;
-};
-
-#define ASN1_MAX_OID_LEN 20
-struct asn1_oid {
-	unsigned long oid[ASN1_MAX_OID_LEN];
-	size_t len;
-};
-
-
-int asn1_get_next(const u8 *buf, size_t len, struct asn1_hdr *hdr);
-int asn1_parse_oid(const u8 *buf, size_t len, struct asn1_oid *oid);
-int asn1_get_oid(const u8 *buf, size_t len, struct asn1_oid *oid,
-		 const u8 **next);
-void asn1_oid_to_str(struct asn1_oid *oid, char *buf, size_t len);
-unsigned long asn1_bit_string_to_long(const u8 *buf, size_t len);
-
-#endif /* ASN1_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/bignum.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/bignum.h
deleted file mode 100644
index f25e26783a0..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/bignum.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Big number math
- * Copyright (c) 2006, Jouni Malinen <j@w1.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Alternatively, this software may be distributed under the terms of BSD
- * license.
- *
- * See README and COPYING for more details.
- */
-
-#ifndef BIGNUM_H
-#define BIGNUM_H
-
-struct bignum;
-
-struct bignum * bignum_init(void);
-void bignum_deinit(struct bignum *n);
-size_t bignum_get_unsigned_bin_len(struct bignum *n);
-int bignum_get_unsigned_bin(const struct bignum *n, u8 *buf, size_t *len);
-int bignum_set_unsigned_bin(struct bignum *n, const u8 *buf, size_t len);
-int bignum_cmp(const struct bignum *a, const struct bignum *b);
-int bignum_cmp_d(const struct bignum *a, unsigned long b);
-int bignum_add(const struct bignum *a, const struct bignum *b,
-	       struct bignum *c);
-int bignum_sub(const struct bignum *a, const struct bignum *b,
-	       struct bignum *c);
-int bignum_mul(const struct bignum *a, const struct bignum *b,
-	       struct bignum *c);
-int bignum_mulmod(const struct bignum *a, const struct bignum *b,
-		  const struct bignum *c, struct bignum *d);
-int bignum_exptmod(const struct bignum *a, const struct bignum *b,
-		   const struct bignum *c, struct bignum *d);
-
-#endif /* BIGNUM_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/libtommath.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/libtommath.h
deleted file mode 100644
index 9be311e86a6..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/libtommath.h
+++ /dev/null
@@ -1,3441 +0,0 @@
-/*
- * Minimal code for RSA support from LibTomMath 0.41
- * http://libtom.org/
- * http://libtom.org/files/ltm-0.41.tar.bz2
- * This library was released in public domain by Tom St Denis.
- *
- * The combination in this file may not use all of the optimized algorithms
- * from LibTomMath and may be considerable slower than the LibTomMath with its
- * default settings. The main purpose of having this version here is to make it
- * easier to build bignum.c wrapper without having to install and build an
- * external library.
- *
- * If CONFIG_INTERNAL_LIBTOMMATH is defined, bignum.c includes this
- * libtommath.c file instead of using the external LibTomMath library.
- */
-#include "os.h"
-#include "stdarg.h"
-
-#ifdef MEMLEAK_DEBUG
-static const char mem_debug_file[] ICACHE_RODATA_ATTR = __FILE__;
-#endif
-
-#ifndef CHAR_BIT
-#define CHAR_BIT 8
-#endif
-
-#define BN_MP_INVMOD_C
-#define BN_S_MP_EXPTMOD_C /* Note: #undef in tommath_superclass.h; this would
-			   * require BN_MP_EXPTMOD_FAST_C instead */
-#define BN_S_MP_MUL_DIGS_C
-#define BN_MP_INVMOD_SLOW_C
-#define BN_S_MP_SQR_C
-#define BN_S_MP_MUL_HIGH_DIGS_C /* Note: #undef in tommath_superclass.h; this
-				 * would require other than mp_reduce */
-
-#ifdef LTM_FAST
-
-/* Use faster div at the cost of about 1 kB */
-#define BN_MP_MUL_D_C
-
-/* Include faster exptmod (Montgomery) at the cost of about 2.5 kB in code */
-#define BN_MP_EXPTMOD_FAST_C
-#define BN_MP_MONTGOMERY_SETUP_C
-#define BN_FAST_MP_MONTGOMERY_REDUCE_C
-#define BN_MP_MONTGOMERY_CALC_NORMALIZATION_C
-#define BN_MP_MUL_2_C
-
-/* Include faster sqr at the cost of about 0.5 kB in code */
-#define BN_FAST_S_MP_SQR_C
-
-#else /* LTM_FAST */
-
-#define BN_MP_DIV_SMALL
-#define BN_MP_INIT_MULTI_C
-#define BN_MP_CLEAR_MULTI_C
-#define BN_MP_ABS_C
-#endif /* LTM_FAST */
-
-/* Current uses do not require support for negative exponent in exptmod, so we
- * can save about 1.5 kB in leaving out invmod. */
-#define LTM_NO_NEG_EXP
-
-/* from tommath.h */
-
-#ifndef MIN
-   #define MIN(x,y) ((x)<(y)?(x):(y))
-#endif
-
-#ifndef MAX
-   #define MAX(x,y) ((x)>(y)?(x):(y))
-#endif
-
-#define  OPT_CAST(x) (x *)
-
-typedef unsigned long mp_digit;
-typedef u64 mp_word;
-
-#define DIGIT_BIT          28
-#define MP_28BIT
-
-
-#define XMALLOC  os_malloc
-#define XFREE    os_free
-#define XREALLOC os_realloc
-
-
-#define MP_MASK          ((((mp_digit)1)<<((mp_digit)DIGIT_BIT))-((mp_digit)1))
-
-#define MP_LT        -1   /* less than */
-#define MP_EQ         0   /* equal to */
-#define MP_GT         1   /* greater than */
-
-#define MP_ZPOS       0   /* positive integer */
-#define MP_NEG        1   /* negative */
-
-#define MP_OKAY       0   /* ok result */
-#define MP_MEM        -2  /* out of mem */
-#define MP_VAL        -3  /* invalid input */
-
-#define MP_YES        1   /* yes response */
-#define MP_NO         0   /* no response */
-
-typedef int           mp_err;
-
-/* define this to use lower memory usage routines (exptmods mostly) */
-#define MP_LOW_MEM
-
-/* default precision */
-#ifndef MP_PREC
-   #ifndef MP_LOW_MEM
-      #define MP_PREC                 32     /* default digits of precision */
-   #else
-      #define MP_PREC                 8      /* default digits of precision */
-   #endif   
-#endif
-
-/* size of comba arrays, should be at least 2 * 2**(BITS_PER_WORD - BITS_PER_DIGIT*2) */
-#define MP_WARRAY               (1 << (sizeof(mp_word) * CHAR_BIT - 2 * DIGIT_BIT + 1))
-
-/* the infamous mp_int structure */
-typedef struct  {
-    int used, alloc, sign;
-    mp_digit *dp;
-} mp_int;
-
-
-/* ---> Basic Manipulations <--- */
-#define mp_iszero(a) (((a)->used == 0) ? MP_YES : MP_NO)
-#define mp_iseven(a) (((a)->used > 0 && (((a)->dp[0] & 1) == 0)) ? MP_YES : MP_NO)
-#define mp_isodd(a)  (((a)->used > 0 && (((a)->dp[0] & 1) == 1)) ? MP_YES : MP_NO)
-
-
-/* prototypes for copied functions */
-#define s_mp_mul(a, b, c) s_mp_mul_digs(a, b, c, (a)->used + (b)->used + 1)
-static int s_mp_exptmod(mp_int * G, mp_int * X, mp_int * P, mp_int * Y, int redmode);
-static int s_mp_mul_digs (mp_int * a, mp_int * b, mp_int * c, int digs);
-static int s_mp_sqr(mp_int * a, mp_int * b);
-static int s_mp_mul_high_digs(mp_int * a, mp_int * b, mp_int * c, int digs);
-
-static int fast_s_mp_mul_digs (mp_int * a, mp_int * b, mp_int * c, int digs);
-
-#ifdef BN_MP_INIT_MULTI_C
-static int mp_init_multi(mp_int *mp, ...);
-#endif
-#ifdef BN_MP_CLEAR_MULTI_C
-static void mp_clear_multi(mp_int *mp, ...);
-#endif
-static int mp_lshd(mp_int * a, int b);
-static void mp_set(mp_int * a, mp_digit b);
-static void mp_clamp(mp_int * a);
-static void mp_exch(mp_int * a, mp_int * b);
-static void mp_rshd(mp_int * a, int b);
-static void mp_zero(mp_int * a);
-static int mp_mod_2d(mp_int * a, int b, mp_int * c);
-static int mp_div_2d(mp_int * a, int b, mp_int * c, mp_int * d);
-static int mp_init_copy(mp_int * a, mp_int * b);
-static int mp_mul_2d(mp_int * a, int b, mp_int * c);
-#ifndef LTM_NO_NEG_EXP
-static int mp_div_2(mp_int * a, mp_int * b);
-static int mp_invmod(mp_int * a, mp_int * b, mp_int * c);
-static int mp_invmod_slow(mp_int * a, mp_int * b, mp_int * c);
-#endif /* LTM_NO_NEG_EXP */
-static int mp_copy(mp_int * a, mp_int * b);
-static int mp_count_bits(mp_int * a);
-static int mp_div(mp_int * a, mp_int * b, mp_int * c, mp_int * d);
-static int mp_mod(mp_int * a, mp_int * b, mp_int * c);
-static int mp_grow(mp_int * a, int size);
-static int mp_cmp_mag(mp_int * a, mp_int * b);
-#ifdef BN_MP_ABS_C
-static int mp_abs(mp_int * a, mp_int * b);
-#endif
-static int mp_sqr(mp_int * a, mp_int * b);
-static int mp_reduce_2k_l(mp_int *a, mp_int *n, mp_int *d);
-static int mp_reduce_2k_setup_l(mp_int *a, mp_int *d);
-static int mp_2expt(mp_int * a, int b);
-static int mp_reduce_setup(mp_int * a, mp_int * b);
-static int mp_reduce(mp_int * x, mp_int * m, mp_int * mu);
-static int mp_init_size(mp_int * a, int size);
-#ifdef BN_MP_EXPTMOD_FAST_C
-static int mp_exptmod_fast (mp_int * G, mp_int * X, mp_int * P, mp_int * Y, int redmode);
-#endif /* BN_MP_EXPTMOD_FAST_C */
-#ifdef BN_FAST_S_MP_SQR_C
-static int fast_s_mp_sqr (mp_int * a, mp_int * b);
-#endif /* BN_FAST_S_MP_SQR_C */
-#ifdef BN_MP_MUL_D_C
-static int mp_mul_d (mp_int * a, mp_digit b, mp_int * c);
-#endif /* BN_MP_MUL_D_C */
-
-
-
-/* functions from bn_<func name>.c */
-
-
-/* reverse an array, used for radix code */
-static void
-bn_reverse (unsigned char *s, int len)
-{
-  int     ix, iy;
-  unsigned char t;
-
-  ix = 0;
-  iy = len - 1;
-  while (ix < iy) {
-    t     = s[ix];
-    s[ix] = s[iy];
-    s[iy] = t;
-    ++ix;
-    --iy;
-  }
-}
-
-
-/* low level addition, based on HAC pp.594, Algorithm 14.7 */
-static int
-s_mp_add (mp_int * a, mp_int * b, mp_int * c)
-{
-  mp_int *x;
-  int     olduse, res, min, max;
-
-  /* find sizes, we let |a| <= |b| which means we have to sort
-   * them.  "x" will point to the input with the most digits
-   */
-  if (a->used > b->used) {
-    min = b->used;
-    max = a->used;
-    x = a;
-  } else {
-    min = a->used;
-    max = b->used;
-    x = b;
-  }
-
-  /* init result */
-  if (c->alloc < max + 1) {
-    if ((res = mp_grow (c, max + 1)) != MP_OKAY) {
-      return res;
-    }
-  }
-
-  /* get old used digit count and set new one */
-  olduse = c->used;
-  c->used = max + 1;
-
-  {
-    register mp_digit u, *tmpa, *tmpb, *tmpc;
-    register int i;
-
-    /* alias for digit pointers */
-
-    /* first input */
-    tmpa = a->dp;
-
-    /* second input */
-    tmpb = b->dp;
-
-    /* destination */
-    tmpc = c->dp;
-
-    /* zero the carry */
-    u = 0;
-    for (i = 0; i < min; i++) {
-      /* Compute the sum at one digit, T[i] = A[i] + B[i] + U */
-      *tmpc = *tmpa++ + *tmpb++ + u;
-
-      /* U = carry bit of T[i] */
-      u = *tmpc >> ((mp_digit)DIGIT_BIT);
-
-      /* take away carry bit from T[i] */
-      *tmpc++ &= MP_MASK;
-    }
-
-    /* now copy higher words if any, that is in A+B 
-     * if A or B has more digits add those in 
-     */
-    if (min != max) {
-      for (; i < max; i++) {
-        /* T[i] = X[i] + U */
-        *tmpc = x->dp[i] + u;
-
-        /* U = carry bit of T[i] */
-        u = *tmpc >> ((mp_digit)DIGIT_BIT);
-
-        /* take away carry bit from T[i] */
-        *tmpc++ &= MP_MASK;
-      }
-    }
-
-    /* add carry */
-    *tmpc++ = u;
-
-    /* clear digits above oldused */
-    for (i = c->used; i < olduse; i++) {
-      *tmpc++ = 0;
-    }
-  }
-
-  mp_clamp (c);
-  return MP_OKAY;
-}
-
-
-/* low level subtraction (assumes |a| > |b|), HAC pp.595 Algorithm 14.9 */
-static int
-s_mp_sub (mp_int * a, mp_int * b, mp_int * c)
-{
-  int     olduse, res, min, max;
-
-  /* find sizes */
-  min = b->used;
-  max = a->used;
-
-  /* init result */
-  if (c->alloc < max) {
-    if ((res = mp_grow (c, max)) != MP_OKAY) {
-      return res;
-    }
-  }
-  olduse = c->used;
-  c->used = max;
-
-  {
-    register mp_digit u, *tmpa, *tmpb, *tmpc;
-    register int i;
-
-    /* alias for digit pointers */
-    tmpa = a->dp;
-    tmpb = b->dp;
-    tmpc = c->dp;
-
-    /* set carry to zero */
-    u = 0;
-    for (i = 0; i < min; i++) {
-      /* T[i] = A[i] - B[i] - U */
-      *tmpc = *tmpa++ - *tmpb++ - u;
-
-      /* U = carry bit of T[i]
-       * Note this saves performing an AND operation since
-       * if a carry does occur it will propagate all the way to the
-       * MSB.  As a result a single shift is enough to get the carry
-       */
-      u = *tmpc >> ((mp_digit)(CHAR_BIT * sizeof (mp_digit) - 1));
-
-      /* Clear carry from T[i] */
-      *tmpc++ &= MP_MASK;
-    }
-
-    /* now copy higher words if any, e.g. if A has more digits than B  */
-    for (; i < max; i++) {
-      /* T[i] = A[i] - U */
-      *tmpc = *tmpa++ - u;
-
-      /* U = carry bit of T[i] */
-      u = *tmpc >> ((mp_digit)(CHAR_BIT * sizeof (mp_digit) - 1));
-
-      /* Clear carry from T[i] */
-      *tmpc++ &= MP_MASK;
-    }
-
-    /* clear digits above used (since we may not have grown result above) */
-    for (i = c->used; i < olduse; i++) {
-      *tmpc++ = 0;
-    }
-  }
-
-  mp_clamp (c);
-  return MP_OKAY;
-}
-
-
-/* init a new mp_int */
-static int
-mp_init (mp_int * a)
-{
-  int i;
-
-  /* allocate memory required and clear it */
-  a->dp = OPT_CAST(mp_digit) XMALLOC (sizeof (mp_digit) * MP_PREC);
-  if (a->dp == NULL) {
-    return MP_MEM;
-  }
-
-  /* set the digits to zero */
-  for (i = 0; i < MP_PREC; i++) {
-      a->dp[i] = 0;
-  }
-
-  /* set the used to zero, allocated digits to the default precision
-   * and sign to positive */
-  a->used  = 0;
-  a->alloc = MP_PREC;
-  a->sign  = MP_ZPOS;
-
-  return MP_OKAY;
-}
-
-
-/* clear one (frees)  */
-static void
-mp_clear (mp_int * a)
-{
-  int i;
-
-  /* only do anything if a hasn't been freed previously */
-  if (a->dp != NULL) {
-    /* first zero the digits */
-    for (i = 0; i < a->used; i++) {
-        a->dp[i] = 0;
-    }
-
-    /* free ram */
-    XFREE(a->dp);
-
-    /* reset members to make debugging easier */
-    a->dp    = NULL;
-    a->alloc = a->used = 0;
-    a->sign  = MP_ZPOS;
-  }
-}
-
-
-/* high level addition (handles signs) */
-static int
-mp_add (mp_int * a, mp_int * b, mp_int * c)
-{
-  int     sa, sb, res;
-
-  /* get sign of both inputs */
-  sa = a->sign;
-  sb = b->sign;
-
-  /* handle two cases, not four */
-  if (sa == sb) {
-    /* both positive or both negative */
-    /* add their magnitudes, copy the sign */
-    c->sign = sa;
-    res = s_mp_add (a, b, c);
-  } else {
-    /* one positive, the other negative */
-    /* subtract the one with the greater magnitude from */
-    /* the one of the lesser magnitude.  The result gets */
-    /* the sign of the one with the greater magnitude. */
-    if (mp_cmp_mag (a, b) == MP_LT) {
-      c->sign = sb;
-      res = s_mp_sub (b, a, c);
-    } else {
-      c->sign = sa;
-      res = s_mp_sub (a, b, c);
-    }
-  }
-  return res;
-}
-
-
-/* high level subtraction (handles signs) */
-static int
-mp_sub (mp_int * a, mp_int * b, mp_int * c)
-{
-  int     sa, sb, res;
-
-  sa = a->sign;
-  sb = b->sign;
-
-  if (sa != sb) {
-    /* subtract a negative from a positive, OR */
-    /* subtract a positive from a negative. */
-    /* In either case, ADD their magnitudes, */
-    /* and use the sign of the first number. */
-    c->sign = sa;
-    res = s_mp_add (a, b, c);
-  } else {
-    /* subtract a positive from a positive, OR */
-    /* subtract a negative from a negative. */
-    /* First, take the difference between their */
-    /* magnitudes, then... */
-    if (mp_cmp_mag (a, b) != MP_LT) {
-      /* Copy the sign from the first */
-      c->sign = sa;
-      /* The first has a larger or equal magnitude */
-      res = s_mp_sub (a, b, c);
-    } else {
-      /* The result has the *opposite* sign from */
-      /* the first number. */
-      c->sign = (sa == MP_ZPOS) ? MP_NEG : MP_ZPOS;
-      /* The second has a larger magnitude */
-      res = s_mp_sub (b, a, c);
-    }
-  }
-  return res;
-}
-
-
-/* high level multiplication (handles sign) */
-static int
-mp_mul (mp_int * a, mp_int * b, mp_int * c)
-{
-  int     res, neg;
-  neg = (a->sign == b->sign) ? MP_ZPOS : MP_NEG;
-
-  /* use Toom-Cook? */
-#ifdef BN_MP_TOOM_MUL_C
-  if (MIN (a->used, b->used) >= TOOM_MUL_CUTOFF) {
-    res = mp_toom_mul(a, b, c);
-  } else 
-#endif
-#ifdef BN_MP_KARATSUBA_MUL_C
-  /* use Karatsuba? */
-  if (MIN (a->used, b->used) >= KARATSUBA_MUL_CUTOFF) {
-    res = mp_karatsuba_mul (a, b, c);
-  } else 
-#endif
-  {
-    /* can we use the fast multiplier?
-     *
-     * The fast multiplier can be used if the output will 
-     * have less than MP_WARRAY digits and the number of 
-     * digits won't affect carry propagation
-     */
-#ifdef BN_FAST_S_MP_MUL_DIGS_C
-    int     digs = a->used + b->used + 1;
-
-    if ((digs < MP_WARRAY) &&
-        MIN(a->used, b->used) <= 
-        (1 << ((CHAR_BIT * sizeof (mp_word)) - (2 * DIGIT_BIT)))) {
-      res = fast_s_mp_mul_digs (a, b, c, digs);
-    } else 
-#endif
-#ifdef BN_S_MP_MUL_DIGS_C
-      res = s_mp_mul (a, b, c); /* uses s_mp_mul_digs */
-#else
-#error mp_mul could fail
-      res = MP_VAL;
-#endif
-
-  }
-  c->sign = (c->used > 0) ? neg : MP_ZPOS;
-  return res;
-}
-
-
-/* d = a * b (mod c) */
-static int
-mp_mulmod (mp_int * a, mp_int * b, mp_int * c, mp_int * d)
-{
-  int     res;
-  mp_int  t;
-
-  if ((res = mp_init (&t)) != MP_OKAY) {
-    return res;
-  }
-
-  if ((res = mp_mul (a, b, &t)) != MP_OKAY) {
-    mp_clear (&t);
-    return res;
-  }
-  res = mp_mod (&t, c, d);
-  mp_clear (&t);
-  return res;
-}
-
-
-/* c = a mod b, 0 <= c < b */
-static int
-mp_mod (mp_int * a, mp_int * b, mp_int * c)
-{
-  mp_int  t;
-  int     res;
-
-  if ((res = mp_init (&t)) != MP_OKAY) {
-    return res;
-  }
-
-  if ((res = mp_div (a, b, NULL, &t)) != MP_OKAY) {
-    mp_clear (&t);
-    return res;
-  }
-
-  if (t.sign != b->sign) {
-    res = mp_add (b, &t, c);
-  } else {
-    res = MP_OKAY;
-    mp_exch (&t, c);
-  }
-
-  mp_clear (&t);
-  return res;
-}
-
-
-/* this is a shell function that calls either the normal or Montgomery
- * exptmod functions.  Originally the call to the montgomery code was
- * embedded in the normal function but that wasted a lot of stack space
- * for nothing (since 99% of the time the Montgomery code would be called)
- */
-static int
-mp_exptmod (mp_int * G, mp_int * X, mp_int * P, mp_int * Y)
-{
-#if defined(BN_MP_DR_IS_MODULUS_C)||defined(BN_MP_REDUCE_IS_2K_C)||defined(BN_MP_EXPTMOD_FAST_C)
-  int dr = 0;
-#endif
-
-  /* modulus P must be positive */
-  if (P->sign == MP_NEG) {
-     return MP_VAL;
-  }
-
-  /* if exponent X is negative we have to recurse */
-  if (X->sign == MP_NEG) {
-#ifdef LTM_NO_NEG_EXP
-        return MP_VAL;
-#else /* LTM_NO_NEG_EXP */
-#ifdef BN_MP_INVMOD_C
-     mp_int tmpG, tmpX;
-     int err;
-
-     /* first compute 1/G mod P */
-     if ((err = mp_init(&tmpG)) != MP_OKAY) {
-        return err;
-     }
-     if ((err = mp_invmod(G, P, &tmpG)) != MP_OKAY) {
-        mp_clear(&tmpG);
-        return err;
-     }
-
-     /* now get |X| */
-     if ((err = mp_init(&tmpX)) != MP_OKAY) {
-        mp_clear(&tmpG);
-        return err;
-     }
-     if ((err = mp_abs(X, &tmpX)) != MP_OKAY) {
-        mp_clear_multi(&tmpG, &tmpX, NULL);
-        return err;
-     }
-
-     /* and now compute (1/G)**|X| instead of G**X [X < 0] */
-     err = mp_exptmod(&tmpG, &tmpX, P, Y);
-     mp_clear_multi(&tmpG, &tmpX, NULL);
-     return err;
-#else 
-#error mp_exptmod would always fail
-     /* no invmod */
-     return MP_VAL;
-#endif
-#endif /* LTM_NO_NEG_EXP */
-  }
-
-/* modified diminished radix reduction */
-#if defined(BN_MP_REDUCE_IS_2K_L_C) && defined(BN_MP_REDUCE_2K_L_C) && defined(BN_S_MP_EXPTMOD_C)
-  if (mp_reduce_is_2k_l(P) == MP_YES) {
-     return s_mp_exptmod(G, X, P, Y, 1);
-  }
-#endif
-
-#ifdef BN_MP_DR_IS_MODULUS_C
-  /* is it a DR modulus? */
-  dr = mp_dr_is_modulus(P);
-#endif
-
-#ifdef BN_MP_REDUCE_IS_2K_C
-  /* if not, is it a unrestricted DR modulus? */
-  if (dr == 0) {
-     dr = mp_reduce_is_2k(P) << 1;
-  }
-#endif
-    
-  /* if the modulus is odd or dr != 0 use the montgomery method */
-#ifdef BN_MP_EXPTMOD_FAST_C
-  if (mp_isodd (P) == 1 || dr !=  0) {
-    return mp_exptmod_fast (G, X, P, Y, dr);
-  } else {
-#endif
-#ifdef BN_S_MP_EXPTMOD_C
-    /* otherwise use the generic Barrett reduction technique */
-    return s_mp_exptmod (G, X, P, Y, 0);
-#else
-#error mp_exptmod could fail
-    /* no exptmod for evens */
-    return MP_VAL;
-#endif
-#ifdef BN_MP_EXPTMOD_FAST_C
-  }
-#endif
-}
-
-
-/* compare two ints (signed)*/
-static int
-mp_cmp (mp_int * a, mp_int * b)
-{
-  /* compare based on sign */
-  if (a->sign != b->sign) {
-     if (a->sign == MP_NEG) {
-        return MP_LT;
-     } else {
-        return MP_GT;
-     }
-  }
-  
-  /* compare digits */
-  if (a->sign == MP_NEG) {
-     /* if negative compare opposite direction */
-     return mp_cmp_mag(b, a);
-  } else {
-     return mp_cmp_mag(a, b);
-  }
-}
-
-
-/* compare a digit */
-static int
-mp_cmp_d(mp_int * a, mp_digit b)
-{
-  /* compare based on sign */
-  if (a->sign == MP_NEG) {
-    return MP_LT;
-  }
-
-  /* compare based on magnitude */
-  if (a->used > 1) {
-    return MP_GT;
-  }
-
-  /* compare the only digit of a to b */
-  if (a->dp[0] > b) {
-    return MP_GT;
-  } else if (a->dp[0] < b) {
-    return MP_LT;
-  } else {
-    return MP_EQ;
-  }
-}
-
-
-#ifndef LTM_NO_NEG_EXP
-/* hac 14.61, pp608 */
-static int
-mp_invmod (mp_int * a, mp_int * b, mp_int * c)
-{
-  /* b cannot be negative */
-  if (b->sign == MP_NEG || mp_iszero(b) == 1) {
-    return MP_VAL;
-  }
-
-#ifdef BN_FAST_MP_INVMOD_C
-  /* if the modulus is odd we can use a faster routine instead */
-  if (mp_isodd (b) == 1) {
-    return fast_mp_invmod (a, b, c);
-  }
-#endif
-
-#ifdef BN_MP_INVMOD_SLOW_C
-  return mp_invmod_slow(a, b, c);
-#endif
-
-#ifndef BN_FAST_MP_INVMOD_C
-#ifndef BN_MP_INVMOD_SLOW_C
-#error mp_invmod would always fail
-#endif
-#endif
-  return MP_VAL;
-}
-#endif /* LTM_NO_NEG_EXP */
-
-
-/* get the size for an unsigned equivalent */
-static int
-mp_unsigned_bin_size (mp_int * a)
-{
-  int     size = mp_count_bits (a);
-  return (size / 8 + ((size & 7) != 0 ? 1 : 0));
-}
-
-
-#ifndef LTM_NO_NEG_EXP
-/* hac 14.61, pp608 */
-static int
-mp_invmod_slow (mp_int * a, mp_int * b, mp_int * c)
-{
-  mp_int  x, y, u, v, A, B, C, D;
-  int     res;
-
-  /* b cannot be negative */
-  if (b->sign == MP_NEG || mp_iszero(b) == 1) {
-    return MP_VAL;
-  }
-
-  /* init temps */
-  if ((res = mp_init_multi(&x, &y, &u, &v, 
-                           &A, &B, &C, &D, NULL)) != MP_OKAY) {
-     return res;
-  }
-
-  /* x = a, y = b */
-  if ((res = mp_mod(a, b, &x)) != MP_OKAY) {
-      goto LBL_ERR;
-  }
-  if ((res = mp_copy (b, &y)) != MP_OKAY) {
-    goto LBL_ERR;
-  }
-
-  /* 2. [modified] if x,y are both even then return an error! */
-  if (mp_iseven (&x) == 1 && mp_iseven (&y) == 1) {
-    res = MP_VAL;
-    goto LBL_ERR;
-  }
-
-  /* 3. u=x, v=y, A=1, B=0, C=0,D=1 */
-  if ((res = mp_copy (&x, &u)) != MP_OKAY) {
-    goto LBL_ERR;
-  }
-  if ((res = mp_copy (&y, &v)) != MP_OKAY) {
-    goto LBL_ERR;
-  }
-  mp_set (&A, 1);
-  mp_set (&D, 1);
-
-top:
-  /* 4.  while u is even do */
-  while (mp_iseven (&u) == 1) {
-    /* 4.1 u = u/2 */
-    if ((res = mp_div_2 (&u, &u)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-    /* 4.2 if A or B is odd then */
-    if (mp_isodd (&A) == 1 || mp_isodd (&B) == 1) {
-      /* A = (A+y)/2, B = (B-x)/2 */
-      if ((res = mp_add (&A, &y, &A)) != MP_OKAY) {
-         goto LBL_ERR;
-      }
-      if ((res = mp_sub (&B, &x, &B)) != MP_OKAY) {
-         goto LBL_ERR;
-      }
-    }
-    /* A = A/2, B = B/2 */
-    if ((res = mp_div_2 (&A, &A)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-    if ((res = mp_div_2 (&B, &B)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-  }
-
-  /* 5.  while v is even do */
-  while (mp_iseven (&v) == 1) {
-    /* 5.1 v = v/2 */
-    if ((res = mp_div_2 (&v, &v)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-    /* 5.2 if C or D is odd then */
-    if (mp_isodd (&C) == 1 || mp_isodd (&D) == 1) {
-      /* C = (C+y)/2, D = (D-x)/2 */
-      if ((res = mp_add (&C, &y, &C)) != MP_OKAY) {
-         goto LBL_ERR;
-      }
-      if ((res = mp_sub (&D, &x, &D)) != MP_OKAY) {
-         goto LBL_ERR;
-      }
-    }
-    /* C = C/2, D = D/2 */
-    if ((res = mp_div_2 (&C, &C)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-    if ((res = mp_div_2 (&D, &D)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-  }
-
-  /* 6.  if u >= v then */
-  if (mp_cmp (&u, &v) != MP_LT) {
-    /* u = u - v, A = A - C, B = B - D */
-    if ((res = mp_sub (&u, &v, &u)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-
-    if ((res = mp_sub (&A, &C, &A)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-
-    if ((res = mp_sub (&B, &D, &B)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-  } else {
-    /* v - v - u, C = C - A, D = D - B */
-    if ((res = mp_sub (&v, &u, &v)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-
-    if ((res = mp_sub (&C, &A, &C)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-
-    if ((res = mp_sub (&D, &B, &D)) != MP_OKAY) {
-      goto LBL_ERR;
-    }
-  }
-
-  /* if not zero goto step 4 */
-  if (mp_iszero (&u) == 0)
-    goto top;
-
-  /* now a = C, b = D, gcd == g*v */
-
-  /* if v != 1 then there is no inverse */
-  if (mp_cmp_d (&v, 1) != MP_EQ) {
-    res = MP_VAL;
-    goto LBL_ERR;
-  }
-
-  /* if its too low */
-  while (mp_cmp_d(&C, 0) == MP_LT) {
-      if ((res = mp_add(&C, b, &C)) != MP_OKAY) {
-         goto LBL_ERR;
-      }
-  }
-  
-  /* too big */
-  while (mp_cmp_mag(&C, b) != MP_LT) {
-      if ((res = mp_sub(&C, b, &C)) != MP_OKAY) {
-         goto LBL_ERR;
-      }
-  }
-  
-  /* C is now the inverse */
-  mp_exch (&C, c);
-  res = MP_OKAY;
-LBL_ERR:mp_clear_multi (&x, &y, &u, &v, &A, &B, &C, &D, NULL);
-  return res;
-}
-#endif /* LTM_NO_NEG_EXP */
-
-
-/* compare maginitude of two ints (unsigned) */
-static int
-mp_cmp_mag (mp_int * a, mp_int * b)
-{
-  int     n;
-  mp_digit *tmpa, *tmpb;
-
-  /* compare based on # of non-zero digits */
-  if (a->used > b->used) {
-    return MP_GT;
-  }
-  
-  if (a->used < b->used) {
-    return MP_LT;
-  }
-
-  /* alias for a */
-  tmpa = a->dp + (a->used - 1);
-
-  /* alias for b */
-  tmpb = b->dp + (a->used - 1);
-
-  /* compare based on digits  */
-  for (n = 0; n < a->used; ++n, --tmpa, --tmpb) {
-    if (*tmpa > *tmpb) {
-      return MP_GT;
-    }
-
-    if (*tmpa < *tmpb) {
-      return MP_LT;
-    }
-  }
-  return MP_EQ;
-}
-
-
-/* reads a unsigned char array, assumes the msb is stored first [big endian] */
-static int
-mp_read_unsigned_bin (mp_int * a, const unsigned char *b, int c)
-{
-  int     res;
-
-  /* make sure there are at least two digits */
-  if (a->alloc < 2) {
-     if ((res = mp_grow(a, 2)) != MP_OKAY) {
-        return res;
-     }
-  }
-
-  /* zero the int */
-  mp_zero (a);
-
-  /* read the bytes in */
-  while (c-- > 0) {
-    if ((res = mp_mul_2d (a, 8, a)) != MP_OKAY) {
-      return res;
-    }
-
-#ifndef MP_8BIT
-      a->dp[0] |= *b++;
-      a->used += 1;
-#else
-      a->dp[0] = (*b & MP_MASK);
-      a->dp[1] |= ((*b++ >> 7U) & 1);
-      a->used += 2;
-#endif
-  }
-  mp_clamp (a);
-  return MP_OKAY;
-}
-
-
-/* store in unsigned [big endian] format */
-static int
-mp_to_unsigned_bin (mp_int * a, unsigned char *b)
-{
-  int     x, res;
-  mp_int  t;
-
-  if ((res = mp_init_copy (&t, a)) != MP_OKAY) {
-    return res;
-  }
-
-  x = 0;
-  while (mp_iszero (&t) == 0) {
-#ifndef MP_8BIT
-      b[x++] = (unsigned char) (t.dp[0] & 255);
-#else
-      b[x++] = (unsigned char) (t.dp[0] | ((t.dp[1] & 0x01) << 7));
-#endif
-    if ((res = mp_div_2d (&t, 8, &t, NULL)) != MP_OKAY) {
-      mp_clear (&t);
-      return res;
-    }
-  }
-  bn_reverse (b, x);
-  mp_clear (&t);
-  return MP_OKAY;
-}
-
-
-/* shift right by a certain bit count (store quotient in c, optional remainder in d) */
-static int
-mp_div_2d (mp_int * a, int b, mp_int * c, mp_int * d)
-{
-  mp_digit D, r, rr;
-  int     x, res;
-  mp_int  t;
-
-
-  /* if the shift count is <= 0 then we do no work */
-  if (b <= 0) {
-    res = mp_copy (a, c);
-    if (d != NULL) {
-      mp_zero (d);
-    }
-    return res;
-  }
-
-  if ((res = mp_init (&t)) != MP_OKAY) {
-    return res;
-  }
-
-  /* get the remainder */
-  if (d != NULL) {
-    if ((res = mp_mod_2d (a, b, &t)) != MP_OKAY) {
-      mp_clear (&t);
-      return res;
-    }
-  }
-
-  /* copy */
-  if ((res = mp_copy (a, c)) != MP_OKAY) {
-    mp_clear (&t);
-    return res;
-  }
-
-  /* shift by as many digits in the bit count */
-  if (b >= (int)DIGIT_BIT) {
-    mp_rshd (c, b / DIGIT_BIT);
-  }
-
-  /* shift any bit count < DIGIT_BIT */
-  D = (mp_digit) (b % DIGIT_BIT);
-  if (D != 0) {
-    register mp_digit *tmpc, mask, shift;
-
-    /* mask */
-    mask = (((mp_digit)1) << D) - 1;
-
-    /* shift for lsb */
-    shift = DIGIT_BIT - D;
-
-    /* alias */
-    tmpc = c->dp + (c->used - 1);
-
-    /* carry */
-    r = 0;
-    for (x = c->used - 1; x >= 0; x--) {
-      /* get the lower  bits of this word in a temp */
-      rr = *tmpc & mask;
-
-      /* shift the current word and mix in the carry bits from the previous word */
-      *tmpc = (*tmpc >> D) | (r << shift);
-      --tmpc;
-
-      /* set the carry to the carry bits of the current word found above */
-      r = rr;
-    }
-  }
-  mp_clamp (c);
-  if (d != NULL) {
-    mp_exch (&t, d);
-  }
-  mp_clear (&t);
-  return MP_OKAY;
-}
-
-
-static int
-mp_init_copy (mp_int * a, mp_int * b)
-{
-  int     res;
-
-  if ((res = mp_init (a)) != MP_OKAY) {
-    return res;
-  }
-  return mp_copy (b, a);
-}
-
-
-/* set to zero */
-static void
-mp_zero (mp_int * a)
-{
-  int       n;
-  mp_digit *tmp;
-
-  a->sign = MP_ZPOS;
-  a->used = 0;
-
-  tmp = a->dp;
-  for (n = 0; n < a->alloc; n++) {
-     *tmp++ = 0;
-  }
-}
-
-
-/* copy, b = a */
-static int
-mp_copy (mp_int * a, mp_int * b)
-{
-  int     res, n;
-
-  /* if dst == src do nothing */
-  if (a == b) {
-    return MP_OKAY;
-  }
-
-  /* grow dest */
-  if (b->alloc < a->used) {
-     if ((res = mp_grow (b, a->used)) != MP_OKAY) {
-        return res;
-     }
-  }
-
-  /* zero b and copy the parameters over */
-  {
-    register mp_digit *tmpa, *tmpb;
-
-    /* pointer aliases */
-
-    /* source */
-    tmpa = a->dp;
-
-    /* destination */
-    tmpb = b->dp;
-
-    /* copy all the digits */
-    for (n = 0; n < a->used; n++) {
-      *tmpb++ = *tmpa++;
-    }
-
-    /* clear high digits */
-    for (; n < b->used; n++) {
-      *tmpb++ = 0;
-    }
-  }
-
-  /* copy used count and sign */
-  b->used = a->used;
-  b->sign = a->sign;
-  return MP_OKAY;
-}
-
-
-/* shift right a certain amount of digits */
-static void
-mp_rshd (mp_int * a, int b)
-{
-  int     x;
-
-  /* if b <= 0 then ignore it */
-  if (b <= 0) {
-    return;
-  }
-
-  /* if b > used then simply zero it and return */
-  if (a->used <= b) {
-    mp_zero (a);
-    return;
-  }
-
-  {
-    register mp_digit *bottom, *top;
-
-    /* shift the digits down */
-
-    /* bottom */
-    bottom = a->dp;
-
-    /* top [offset into digits] */
-    top = a->dp + b;
-
-    /* this is implemented as a sliding window where 
-     * the window is b-digits long and digits from 
-     * the top of the window are copied to the bottom
-     *
-     * e.g.
-
-     b-2 | b-1 | b0 | b1 | b2 | ... | bb |   ---->
-                 /\                   |      ---->
-                  \-------------------/      ---->
-     */
-    for (x = 0; x < (a->used - b); x++) {
-      *bottom++ = *top++;
-    }
-
-    /* zero the top digits */
-    for (; x < a->used; x++) {
-      *bottom++ = 0;
-    }
-  }
-  
-  /* remove excess digits */
-  a->used -= b;
-}
-
-
-/* swap the elements of two integers, for cases where you can't simply swap the 
- * mp_int pointers around
- */
-static void
-mp_exch (mp_int * a, mp_int * b)
-{
-  mp_int  t;
-
-  t  = *a;
-  *a = *b;
-  *b = t;
-}
-
-
-/* trim unused digits 
- *
- * This is used to ensure that leading zero digits are
- * trimed and the leading "used" digit will be non-zero
- * Typically very fast.  Also fixes the sign if there
- * are no more leading digits
- */
-static void
-mp_clamp (mp_int * a)
-{
-  /* decrease used while the most significant digit is
-   * zero.
-   */
-  while (a->used > 0 && a->dp[a->used - 1] == 0) {
-    --(a->used);
-  }
-
-  /* reset the sign flag if used == 0 */
-  if (a->used == 0) {
-    a->sign = MP_ZPOS;
-  }
-}
-
-
-/* grow as required */
-static int
-mp_grow (mp_int * a, int size)
-{
-  int     i;
-  mp_digit *tmp;
-
-  /* if the alloc size is smaller alloc more ram */
-  if (a->alloc < size) {
-    /* ensure there are always at least MP_PREC digits extra on top */
-    size += (MP_PREC * 2) - (size % MP_PREC);
-
-    /* reallocate the array a->dp
-     *
-     * We store the return in a temporary variable
-     * in case the operation failed we don't want
-     * to overwrite the dp member of a.
-     */
-    tmp = OPT_CAST(mp_digit) XREALLOC (a->dp, sizeof (mp_digit) * size);
-    if (tmp == NULL) {
-      /* reallocation failed but "a" is still valid [can be freed] */
-      return MP_MEM;
-    }
-
-    /* reallocation succeeded so set a->dp */
-    a->dp = tmp;
-
-    /* zero excess digits */
-    i        = a->alloc;
-    a->alloc = size;
-    for (; i < a->alloc; i++) {
-      a->dp[i] = 0;
-    }
-  }
-  return MP_OKAY;
-}
-
-
-#ifdef BN_MP_ABS_C
-/* b = |a| 
- *
- * Simple function copies the input and fixes the sign to positive
- */
-static int
-mp_abs (mp_int * a, mp_int * b)
-{
-  int     res;
-
-  /* copy a to b */
-  if (a != b) {
-     if ((res = mp_copy (a, b)) != MP_OKAY) {
-       return res;
-     }
-  }
-
-  /* force the sign of b to positive */
-  b->sign = MP_ZPOS;
-
-  return MP_OKAY;
-}
-#endif
-
-
-/* set to a digit */
-static void
-mp_set (mp_int * a, mp_digit b)
-{
-  mp_zero (a);
-  a->dp[0] = b & MP_MASK;
-  a->used  = (a->dp[0] != 0) ? 1 : 0;
-}
-
-
-#ifndef LTM_NO_NEG_EXP
-/* b = a/2 */
-static int
-mp_div_2(mp_int * a, mp_int * b)
-{
-  int     x, res, oldused;
-
-  /* copy */
-  if (b->alloc < a->used) {
-    if ((res = mp_grow (b, a->used)) != MP_OKAY) {
-      return res;
-    }
-  }
-
-  oldused = b->used;
-  b->used = a->used;
-  {
-    register mp_digit r, rr, *tmpa, *tmpb;
-
-    /* source alias */
-    tmpa = a->dp + b->used - 1;
-
-    /* dest alias */
-    tmpb = b->dp + b->used - 1;
-
-    /* carry */
-    r = 0;
-    for (x = b->used - 1; x >= 0; x--) {
-      /* get the carry for the next iteration */
-      rr = *tmpa & 1;
-
-      /* shift the current digit, add in carry and store */
-      *tmpb-- = (*tmpa-- >> 1) | (r << (DIGIT_BIT - 1));
-
-      /* forward carry to next iteration */
-      r = rr;
-    }
-
-    /* zero excess digits */
-    tmpb = b->dp + b->used;
-    for (x = b->used; x < oldused; x++) {
-      *tmpb++ = 0;
-    }
-  }
-  b->sign = a->sign;
-  mp_clamp (b);
-  return MP_OKAY;
-}
-#endif /* LTM_NO_NEG_EXP */
-
-
-/* shift left by a certain bit count */
-static int
-mp_mul_2d (mp_int * a, int b, mp_int * c)
-{
-  mp_digit d;
-  int      res;
-
-  /* copy */
-  if (a != c) {
-     if ((res = mp_copy (a, c)) != MP_OKAY) {
-       return res;
-     }
-  }
-
-  if (c->alloc < (int)(c->used + b/DIGIT_BIT + 1)) {
-     if ((res = mp_grow (c, c->used + b / DIGIT_BIT + 1)) != MP_OKAY) {
-       return res;
-     }
-  }
-
-  /* shift by as many digits in the bit count */
-  if (b >= (int)DIGIT_BIT) {
-    if ((res = mp_lshd (c, b / DIGIT_BIT)) != MP_OKAY) {
-      return res;
-    }
-  }
-
-  /* shift any bit count < DIGIT_BIT */
-  d = (mp_digit) (b % DIGIT_BIT);
-  if (d != 0) {
-    register mp_digit *tmpc, shift, mask, r, rr;
-    register int x;
-
-    /* bitmask for carries */
-    mask = (((mp_digit)1) << d) - 1;
-
-    /* shift for msbs */
-    shift = DIGIT_BIT - d;
-
-    /* alias */
-    tmpc = c->dp;
-
-    /* carry */
-    r    = 0;
-    for (x = 0; x < c->used; x++) {
-      /* get the higher bits of the current word */
-      rr = (*tmpc >> shift) & mask;
-
-      /* shift the current word and OR in the carry */
-      *tmpc = ((*tmpc << d) | r) & MP_MASK;
-      ++tmpc;
-
-      /* set the carry to the carry bits of the current word */
-      r = rr;
-    }
-    
-    /* set final carry */
-    if (r != 0) {
-       c->dp[(c->used)++] = r;
-    }
-  }
-  mp_clamp (c);
-  return MP_OKAY;
-}
-
-
-#ifdef BN_MP_INIT_MULTI_C
-static int
-mp_init_multi(mp_int *mp, ...) 
-{
-    mp_err res = MP_OKAY;      /* Assume ok until proven otherwise */
-    int n = 0;                 /* Number of ok inits */
-    mp_int* cur_arg = mp;
-    va_list args;
-
-    va_start(args, mp);        /* init args to next argument from caller */
-    while (cur_arg != NULL) {
-        if (mp_init(cur_arg) != MP_OKAY) {
-            /* Oops - error! Back-track and mp_clear what we already
-               succeeded in init-ing, then return error.
-            */
-            va_list clean_args;
-            
-            /* end the current list */
-            va_end(args);
-            
-            /* now start cleaning up */            
-            cur_arg = mp;
-            va_start(clean_args, mp);
-            while (n--) {
-                mp_clear(cur_arg);
-                cur_arg = va_arg(clean_args, mp_int*);
-            }
-            va_end(clean_args);
-            res = MP_MEM;
-            break;
-        }
-        n++;
-        cur_arg = va_arg(args, mp_int*);
-    }
-    va_end(args);
-    return res;                /* Assumed ok, if error flagged above. */
-}
-#endif
-
-
-#ifdef BN_MP_CLEAR_MULTI_C
-static void
-mp_clear_multi(mp_int *mp, ...) 
-{
-    mp_int* next_mp = mp;
-    va_list args;
-    va_start(args, mp);
-    while (next_mp != NULL) {
-        mp_clear(next_mp);
-        next_mp = va_arg(args, mp_int*);
-    }
-    va_end(args);
-}
-#endif
-
-
-/* shift left a certain amount of digits */
-static int
-mp_lshd (mp_int * a, int b)
-{
-  int     x, res;
-
-  /* if its less than zero return */
-  if (b <= 0) {
-    return MP_OKAY;
-  }
-
-  /* grow to fit the new digits */
-  if (a->alloc < a->used + b) {
-     if ((res = mp_grow (a, a->used + b)) != MP_OKAY) {
-       return res;
-     }
-  }
-
-  {
-    register mp_digit *top, *bottom;
-
-    /* increment the used by the shift amount then copy upwards */
-    a->used += b;
-
-    /* top */
-    top = a->dp + a->used - 1;
-
-    /* base */
-    bottom = a->dp + a->used - 1 - b;
-
-    /* much like mp_rshd this is implemented using a sliding window
-     * except the window goes the otherway around.  Copying from
-     * the bottom to the top.  see bn_mp_rshd.c for more info.
-     */
-    for (x = a->used - 1; x >= b; x--) {
-      *top-- = *bottom--;
-    }
-
-    /* zero the lower digits */
-    top = a->dp;
-    for (x = 0; x < b; x++) {
-      *top++ = 0;
-    }
-  }
-  return MP_OKAY;
-}
-
-
-/* returns the number of bits in an int */
-static int
-mp_count_bits (mp_int * a)
-{
-  int     r;
-  mp_digit q;
-
-  /* shortcut */
-  if (a->used == 0) {
-    return 0;
-  }
-
-  /* get number of digits and add that */
-  r = (a->used - 1) * DIGIT_BIT;
-  
-  /* take the last digit and count the bits in it */
-  q = a->dp[a->used - 1];
-  while (q > ((mp_digit) 0)) {
-    ++r;
-    q >>= ((mp_digit) 1);
-  }
-  return r;
-}
-
-
-/* calc a value mod 2**b */
-static int
-mp_mod_2d (mp_int * a, int b, mp_int * c)
-{
-  int     x, res;
-
-  /* if b is <= 0 then zero the int */
-  if (b <= 0) {
-    mp_zero (c);
-    return MP_OKAY;
-  }
-
-  /* if the modulus is larger than the value than return */
-  if (b >= (int) (a->used * DIGIT_BIT)) {
-    res = mp_copy (a, c);
-    return res;
-  }
-
-  /* copy */
-  if ((res = mp_copy (a, c)) != MP_OKAY) {
-    return res;
-  }
-
-  /* zero digits above the last digit of the modulus */
-  for (x = (b / DIGIT_BIT) + ((b % DIGIT_BIT) == 0 ? 0 : 1); x < c->used; x++) {
-    c->dp[x] = 0;
-  }
-  /* clear the digit that is not completely outside/inside the modulus */
-  c->dp[b / DIGIT_BIT] &=
-    (mp_digit) ((((mp_digit) 1) << (((mp_digit) b) % DIGIT_BIT)) - ((mp_digit) 1));
-  mp_clamp (c);
-  return MP_OKAY;
-}
-
-
-#ifdef BN_MP_DIV_SMALL
-
-/* slower bit-bang division... also smaller */
-static int
-mp_div(mp_int * a, mp_int * b, mp_int * c, mp_int * d)
-{
-   mp_int ta, tb, tq, q;
-   int    res, n, n2;
-
-  /* is divisor zero ? */
-  if (mp_iszero (b) == 1) {
-    return MP_VAL;
-  }
-
-  /* if a < b then q=0, r = a */
-  if (mp_cmp_mag (a, b) == MP_LT) {
-    if (d != NULL) {
-      res = mp_copy (a, d);
-    } else {
-      res = MP_OKAY;
-    }
-    if (c != NULL) {
-      mp_zero (c);
-    }
-    return res;
-  }
-	
-  /* init our temps */
-  if ((res = mp_init_multi(&ta, &tb, &tq, &q, NULL) != MP_OKAY)) {
-     return res;
-  }
-
-
-  mp_set(&tq, 1);
-  n = mp_count_bits(a) - mp_count_bits(b);
-  if (((res = mp_abs(a, &ta)) != MP_OKAY) ||
-      ((res = mp_abs(b, &tb)) != MP_OKAY) || 
-      ((res = mp_mul_2d(&tb, n, &tb)) != MP_OKAY) ||
-      ((res = mp_mul_2d(&tq, n, &tq)) != MP_OKAY)) {
-      goto LBL_ERR;
-  }
-
-  while (n-- >= 0) {
-     if (mp_cmp(&tb, &ta) != MP_GT) {
-        if (((res = mp_sub(&ta, &tb, &ta)) != MP_OKAY) ||
-            ((res = mp_add(&q, &tq, &q)) != MP_OKAY)) {
-           goto LBL_ERR;
-        }
-     }
-     if (((res = mp_div_2d(&tb, 1, &tb, NULL)) != MP_OKAY) ||
-         ((res = mp_div_2d(&tq, 1, &tq, NULL)) != MP_OKAY)) {
-           goto LBL_ERR;
-     }
-  }
-
-  /* now q == quotient and ta == remainder */
-  n  = a->sign;
-  n2 = (a->sign == b->sign ? MP_ZPOS : MP_NEG);
-  if (c != NULL) {
-     mp_exch(c, &q);
-     c->sign  = (mp_iszero(c) == MP_YES) ? MP_ZPOS : n2;
-  }
-  if (d != NULL) {
-     mp_exch(d, &ta);
-     d->sign = (mp_iszero(d) == MP_YES) ? MP_ZPOS : n;
-  }
-LBL_ERR:
-   mp_clear_multi(&ta, &tb, &tq, &q, NULL);
-   return res;
-}
-
-#else
-
-/* integer signed division. 
- * c*b + d == a [e.g. a/b, c=quotient, d=remainder]
- * HAC pp.598 Algorithm 14.20
- *
- * Note that the description in HAC is horribly 
- * incomplete.  For example, it doesn't consider 
- * the case where digits are removed from 'x' in 
- * the inner loop.  It also doesn't consider the 
- * case that y has fewer than three digits, etc..
- *
- * The overall algorithm is as described as 
- * 14.20 from HAC but fixed to treat these cases.
-*/
-static int
-mp_div (mp_int * a, mp_int * b, mp_int * c, mp_int * d)
-{
-  mp_int  q, x, y, t1, t2;
-  int     res, n, t, i, norm, neg;
-
-  /* is divisor zero ? */
-  if (mp_iszero (b) == 1) {
-    return MP_VAL;
-  }
-
-  /* if a < b then q=0, r = a */
-  if (mp_cmp_mag (a, b) == MP_LT) {
-    if (d != NULL) {
-      res = mp_copy (a, d);
-    } else {
-      res = MP_OKAY;
-    }
-    if (c != NULL) {
-      mp_zero (c);
-    }
-    return res;
-  }
-
-  if ((res = mp_init_size (&q, a->used + 2)) != MP_OKAY) {
-    return res;
-  }
-  q.used = a->used + 2;
-
-  if ((res = mp_init (&t1)) != MP_OKAY) {
-    goto LBL_Q;
-  }
-
-  if ((res = mp_init (&t2)) != MP_OKAY) {
-    goto LBL_T1;
-  }
-
-  if ((res = mp_init_copy (&x, a)) != MP_OKAY) {
-    goto LBL_T2;
-  }
-
-  if ((res = mp_init_copy (&y, b)) != MP_OKAY) {
-    goto LBL_X;
-  }
-
-  /* fix the sign */
-  neg = (a->sign == b->sign) ? MP_ZPOS : MP_NEG;
-  x.sign = y.sign = MP_ZPOS;
-
-  /* normalize both x and y, ensure that y >= b/2, [b == 2**DIGIT_BIT] */
-  norm = mp_count_bits(&y) % DIGIT_BIT;
-  if (norm < (int)(DIGIT_BIT-1)) {
-     norm = (DIGIT_BIT-1) - norm;
-     if ((res = mp_mul_2d (&x, norm, &x)) != MP_OKAY) {
-       goto LBL_Y;
-     }
-     if ((res = mp_mul_2d (&y, norm, &y)) != MP_OKAY) {
-       goto LBL_Y;
-     }
-  } else {
-     norm = 0;
-  }
-
-  /* note hac does 0 based, so if used==5 then its 0,1,2,3,4, e.g. use 4 */
-  n = x.used - 1;
-  t = y.used - 1;
-
-  /* while (x >= y*b**n-t) do { q[n-t] += 1; x -= y*b**{n-t} } */
-  if ((res = mp_lshd (&y, n - t)) != MP_OKAY) { /* y = y*b**{n-t} */
-    goto LBL_Y;
-  }
-
-  while (mp_cmp (&x, &y) != MP_LT) {
-    ++(q.dp[n - t]);
-    if ((res = mp_sub (&x, &y, &x)) != MP_OKAY) {
-      goto LBL_Y;
-    }
-  }
-
-  /* reset y by shifting it back down */
-  mp_rshd (&y, n - t);
-
-  /* step 3. for i from n down to (t + 1) */
-  for (i = n; i >= (t + 1); i--) {
-    if (i > x.used) {
-      continue;
-    }
-
-    /* step 3.1 if xi == yt then set q{i-t-1} to b-1, 
-     * otherwise set q{i-t-1} to (xi*b + x{i-1})/yt */
-    if (x.dp[i] == y.dp[t]) {
-      q.dp[i - t - 1] = ((((mp_digit)1) << DIGIT_BIT) - 1);
-    } else {
-      mp_word tmp;
-      tmp = ((mp_word) x.dp[i]) << ((mp_word) DIGIT_BIT);
-      tmp |= ((mp_word) x.dp[i - 1]);
-      tmp /= ((mp_word) y.dp[t]);
-      if (tmp > (mp_word) MP_MASK)
-        tmp = MP_MASK;
-      q.dp[i - t - 1] = (mp_digit) (tmp & (mp_word) (MP_MASK));
-    }
-
-    /* while (q{i-t-1} * (yt * b + y{t-1})) > 
-             xi * b**2 + xi-1 * b + xi-2 
-     
-       do q{i-t-1} -= 1; 
-    */
-    q.dp[i - t - 1] = (q.dp[i - t - 1] + 1) & MP_MASK;
-    do {
-      q.dp[i - t - 1] = (q.dp[i - t - 1] - 1) & MP_MASK;
-
-      /* find left hand */
-      mp_zero (&t1);
-      t1.dp[0] = (t - 1 < 0) ? 0 : y.dp[t - 1];
-      t1.dp[1] = y.dp[t];
-      t1.used = 2;
-      if ((res = mp_mul_d (&t1, q.dp[i - t - 1], &t1)) != MP_OKAY) {
-        goto LBL_Y;
-      }
-
-      /* find right hand */
-      t2.dp[0] = (i - 2 < 0) ? 0 : x.dp[i - 2];
-      t2.dp[1] = (i - 1 < 0) ? 0 : x.dp[i - 1];
-      t2.dp[2] = x.dp[i];
-      t2.used = 3;
-    } while (mp_cmp_mag(&t1, &t2) == MP_GT);
-
-    /* step 3.3 x = x - q{i-t-1} * y * b**{i-t-1} */
-    if ((res = mp_mul_d (&y, q.dp[i - t - 1], &t1)) != MP_OKAY) {
-      goto LBL_Y;
-    }
-
-    if ((res = mp_lshd (&t1, i - t - 1)) != MP_OKAY) {
-      goto LBL_Y;
-    }
-
-    if ((res = mp_sub (&x, &t1, &x)) != MP_OKAY) {
-      goto LBL_Y;
-    }
-
-    /* if x < 0 then { x = x + y*b**{i-t-1}; q{i-t-1} -= 1; } */
-    if (x.sign == MP_NEG) {
-      if ((res = mp_copy (&y, &t1)) != MP_OKAY) {
-        goto LBL_Y;
-      }
-      if ((res = mp_lshd (&t1, i - t - 1)) != MP_OKAY) {
-        goto LBL_Y;
-      }
-      if ((res = mp_add (&x, &t1, &x)) != MP_OKAY) {
-        goto LBL_Y;
-      }
-
-      q.dp[i - t - 1] = (q.dp[i - t - 1] - 1UL) & MP_MASK;
-    }
-  }
-
-  /* now q is the quotient and x is the remainder 
-   * [which we have to normalize] 
-   */
-  
-  /* get sign before writing to c */
-  x.sign = x.used == 0 ? MP_ZPOS : a->sign;
-
-  if (c != NULL) {
-    mp_clamp (&q);
-    mp_exch (&q, c);
-    c->sign = neg;
-  }
-
-  if (d != NULL) {
-    mp_div_2d (&x, norm, &x, NULL);
-    mp_exch (&x, d);
-  }
-
-  res = MP_OKAY;
-
-LBL_Y:mp_clear (&y);
-LBL_X:mp_clear (&x);
-LBL_T2:mp_clear (&t2);
-LBL_T1:mp_clear (&t1);
-LBL_Q:mp_clear (&q);
-  return res;
-}
-
-#endif
-
-
-#ifdef MP_LOW_MEM
-   #define TAB_SIZE 32
-#else
-   #define TAB_SIZE 256
-#endif
-
-static int
-s_mp_exptmod (mp_int * G, mp_int * X, mp_int * P, mp_int * Y, int redmode)
-{
-  mp_int  M[TAB_SIZE], res, mu;
-  mp_digit buf;
-  int     err, bitbuf, bitcpy, bitcnt, mode, digidx, x, y, winsize;
-  int (*redux)(mp_int*,mp_int*,mp_int*);
-
-  /* find window size */
-  x = mp_count_bits (X);
-  if (x <= 7) {
-    winsize = 2;
-  } else if (x <= 36) {
-    winsize = 3;
-  } else if (x <= 140) {
-    winsize = 4;
-  } else if (x <= 450) {
-    winsize = 5;
-  } else if (x <= 1303) {
-    winsize = 6;
-  } else if (x <= 3529) {
-    winsize = 7;
-  } else {
-    winsize = 8;
-  }
-
-#ifdef MP_LOW_MEM
-    if (winsize > 5) {
-       winsize = 5;
-    }
-#endif
-
-  /* init M array */
-  /* init first cell */
-  if ((err = mp_init(&M[1])) != MP_OKAY) {
-     return err; 
-  }
-
-  /* now init the second half of the array */
-  for (x = 1<<(winsize-1); x < (1 << winsize); x++) {
-    if ((err = mp_init(&M[x])) != MP_OKAY) {
-      for (y = 1<<(winsize-1); y < x; y++) {
-        mp_clear (&M[y]);
-      }
-      mp_clear(&M[1]);
-      return err;
-    }
-  }
-
-  /* create mu, used for Barrett reduction */
-  if ((err = mp_init (&mu)) != MP_OKAY) {
-    goto LBL_M;
-  }
-  
-  if (redmode == 0) {
-     if ((err = mp_reduce_setup (&mu, P)) != MP_OKAY) {
-        goto LBL_MU;
-     }
-     redux = mp_reduce;
-  } else {
-     if ((err = mp_reduce_2k_setup_l (P, &mu)) != MP_OKAY) {
-        goto LBL_MU;
-     }
-     redux = mp_reduce_2k_l;
-  }    
-
-  /* create M table
-   *
-   * The M table contains powers of the base, 
-   * e.g. M[x] = G**x mod P
-   *
-   * The first half of the table is not 
-   * computed though accept for M[0] and M[1]
-   */
-  if ((err = mp_mod (G, P, &M[1])) != MP_OKAY) {
-    goto LBL_MU;
-  }
-
-  /* compute the value at M[1<<(winsize-1)] by squaring 
-   * M[1] (winsize-1) times 
-   */
-  if ((err = mp_copy (&M[1], &M[1 << (winsize - 1)])) != MP_OKAY) {
-    goto LBL_MU;
-  }
-
-  for (x = 0; x < (winsize - 1); x++) {
-    /* square it */
-    if ((err = mp_sqr (&M[1 << (winsize - 1)], 
-                       &M[1 << (winsize - 1)])) != MP_OKAY) {
-      goto LBL_MU;
-    }
-
-    /* reduce modulo P */
-    if ((err = redux (&M[1 << (winsize - 1)], P, &mu)) != MP_OKAY) {
-      goto LBL_MU;
-    }
-  }
-
-  /* create upper table, that is M[x] = M[x-1] * M[1] (mod P)
-   * for x = (2**(winsize - 1) + 1) to (2**winsize - 1)
-   */
-  for (x = (1 << (winsize - 1)) + 1; x < (1 << winsize); x++) {
-    if ((err = mp_mul (&M[x - 1], &M[1], &M[x])) != MP_OKAY) {
-      goto LBL_MU;
-    }
-    if ((err = redux (&M[x], P, &mu)) != MP_OKAY) {
-      goto LBL_MU;
-    }
-  }
-
-  /* setup result */
-  if ((err = mp_init (&res)) != MP_OKAY) {
-    goto LBL_MU;
-  }
-  mp_set (&res, 1);
-
-  /* set initial mode and bit cnt */
-  mode   = 0;
-  bitcnt = 1;
-  buf    = 0;
-  digidx = X->used - 1;
-  bitcpy = 0;
-  bitbuf = 0;
-
-  for (;;) {
-    /* grab next digit as required */
-    if (--bitcnt == 0) {
-      /* if digidx == -1 we are out of digits */
-      if (digidx == -1) {
-        break;
-      }
-      /* read next digit and reset the bitcnt */
-      buf    = X->dp[digidx--];
-      bitcnt = (int) DIGIT_BIT;
-    }
-
-    /* grab the next msb from the exponent */
-    y     = (buf >> (mp_digit)(DIGIT_BIT - 1)) & 1;
-    buf <<= (mp_digit)1;
-
-    /* if the bit is zero and mode == 0 then we ignore it
-     * These represent the leading zero bits before the first 1 bit
-     * in the exponent.  Technically this opt is not required but it
-     * does lower the # of trivial squaring/reductions used
-     */
-    if (mode == 0 && y == 0) {
-      continue;
-    }
-
-    /* if the bit is zero and mode == 1 then we square */
-    if (mode == 1 && y == 0) {
-      if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-      if ((err = redux (&res, P, &mu)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-      continue;
-    }
-
-    /* else we add it to the window */
-    bitbuf |= (y << (winsize - ++bitcpy));
-    mode    = 2;
-
-    if (bitcpy == winsize) {
-      /* ok window is filled so square as required and multiply  */
-      /* square first */
-      for (x = 0; x < winsize; x++) {
-        if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
-          goto LBL_RES;
-        }
-        if ((err = redux (&res, P, &mu)) != MP_OKAY) {
-          goto LBL_RES;
-        }
-      }
-
-      /* then multiply */
-      if ((err = mp_mul (&res, &M[bitbuf], &res)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-      if ((err = redux (&res, P, &mu)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-
-      /* empty window and reset */
-      bitcpy = 0;
-      bitbuf = 0;
-      mode   = 1;
-    }
-  }
-
-  /* if bits remain then square/multiply */
-  if (mode == 2 && bitcpy > 0) {
-    /* square then multiply if the bit is set */
-    for (x = 0; x < bitcpy; x++) {
-      if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-      if ((err = redux (&res, P, &mu)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-
-      bitbuf <<= 1;
-      if ((bitbuf & (1 << winsize)) != 0) {
-        /* then multiply */
-        if ((err = mp_mul (&res, &M[1], &res)) != MP_OKAY) {
-          goto LBL_RES;
-        }
-        if ((err = redux (&res, P, &mu)) != MP_OKAY) {
-          goto LBL_RES;
-        }
-      }
-    }
-  }
-
-  mp_exch (&res, Y);
-  err = MP_OKAY;
-LBL_RES:mp_clear (&res);
-LBL_MU:mp_clear (&mu);
-LBL_M:
-  mp_clear(&M[1]);
-  for (x = 1<<(winsize-1); x < (1 << winsize); x++) {
-    mp_clear (&M[x]);
-  }
-  return err;
-}
-
-
-/* computes b = a*a */
-static int
-mp_sqr (mp_int * a, mp_int * b)
-{
-  int     res;
-
-#ifdef BN_MP_TOOM_SQR_C
-  /* use Toom-Cook? */
-  if (a->used >= TOOM_SQR_CUTOFF) {
-    res = mp_toom_sqr(a, b);
-  /* Karatsuba? */
-  } else 
-#endif
-#ifdef BN_MP_KARATSUBA_SQR_C
-if (a->used >= KARATSUBA_SQR_CUTOFF) {
-    res = mp_karatsuba_sqr (a, b);
-  } else 
-#endif
-  {
-#ifdef BN_FAST_S_MP_SQR_C
-    /* can we use the fast comba multiplier? */
-    if ((a->used * 2 + 1) < MP_WARRAY && 
-         a->used < 
-         (1 << (sizeof(mp_word) * CHAR_BIT - 2*DIGIT_BIT - 1))) {
-      res = fast_s_mp_sqr (a, b);
-    } else
-#endif
-#ifdef BN_S_MP_SQR_C
-      res = s_mp_sqr (a, b);
-#else
-#error mp_sqr could fail
-      res = MP_VAL;
-#endif
-  }
-  b->sign = MP_ZPOS;
-  return res;
-}
-
-
-/* reduces a modulo n where n is of the form 2**p - d 
-   This differs from reduce_2k since "d" can be larger
-   than a single digit.
-*/
-static int
-mp_reduce_2k_l(mp_int *a, mp_int *n, mp_int *d)
-{
-   mp_int q;
-   int    p, res;
-   
-   if ((res = mp_init(&q)) != MP_OKAY) {
-      return res;
-   }
-   
-   p = mp_count_bits(n);    
-top:
-   /* q = a/2**p, a = a mod 2**p */
-   if ((res = mp_div_2d(a, p, &q, a)) != MP_OKAY) {
-      goto ERR;
-   }
-   
-   /* q = q * d */
-   if ((res = mp_mul(&q, d, &q)) != MP_OKAY) { 
-      goto ERR;
-   }
-   
-   /* a = a + q */
-   if ((res = s_mp_add(a, &q, a)) != MP_OKAY) {
-      goto ERR;
-   }
-   
-   if (mp_cmp_mag(a, n) != MP_LT) {
-      s_mp_sub(a, n, a);
-      goto top;
-   }
-   
-ERR:
-   mp_clear(&q);
-   return res;
-}
-
-
-/* determines the setup value */
-static int
-mp_reduce_2k_setup_l(mp_int *a, mp_int *d)
-{
-   int    res;
-   mp_int tmp;
-   
-   if ((res = mp_init(&tmp)) != MP_OKAY) {
-      return res;
-   }
-   
-   if ((res = mp_2expt(&tmp, mp_count_bits(a))) != MP_OKAY) {
-      goto ERR;
-   }
-   
-   if ((res = s_mp_sub(&tmp, a, d)) != MP_OKAY) {
-      goto ERR;
-   }
-   
-ERR:
-   mp_clear(&tmp);
-   return res;
-}
-
-
-/* computes a = 2**b 
- *
- * Simple algorithm which zeroes the int, grows it then just sets one bit
- * as required.
- */
-static int
-mp_2expt (mp_int * a, int b)
-{
-  int     res;
-
-  /* zero a as per default */
-  mp_zero (a);
-
-  /* grow a to accommodate the single bit */
-  if ((res = mp_grow (a, b / DIGIT_BIT + 1)) != MP_OKAY) {
-    return res;
-  }
-
-  /* set the used count of where the bit will go */
-  a->used = b / DIGIT_BIT + 1;
-
-  /* put the single bit in its place */
-  a->dp[b / DIGIT_BIT] = ((mp_digit)1) << (b % DIGIT_BIT);
-
-  return MP_OKAY;
-}
-
-
-/* pre-calculate the value required for Barrett reduction
- * For a given modulus "b" it calulates the value required in "a"
- */
-static int
-mp_reduce_setup (mp_int * a, mp_int * b)
-{
-  int     res;
-  
-  if ((res = mp_2expt (a, b->used * 2 * DIGIT_BIT)) != MP_OKAY) {
-    return res;
-  }
-  return mp_div (a, b, a, NULL);
-}
-
-
-/* reduces x mod m, assumes 0 < x < m**2, mu is 
- * precomputed via mp_reduce_setup.
- * From HAC pp.604 Algorithm 14.42
- */
-static int
-mp_reduce (mp_int * x, mp_int * m, mp_int * mu)
-{
-  mp_int  q;
-  int     res, um = m->used;
-
-  /* q = x */
-  if ((res = mp_init_copy (&q, x)) != MP_OKAY) {
-    return res;
-  }
-
-  /* q1 = x / b**(k-1)  */
-  mp_rshd (&q, um - 1);         
-
-  /* according to HAC this optimization is ok */
-  if (((unsigned long) um) > (((mp_digit)1) << (DIGIT_BIT - 1))) {
-    if ((res = mp_mul (&q, mu, &q)) != MP_OKAY) {
-      goto CLEANUP;
-    }
-  } else {
-#ifdef BN_S_MP_MUL_HIGH_DIGS_C
-    if ((res = s_mp_mul_high_digs (&q, mu, &q, um)) != MP_OKAY) {
-      goto CLEANUP;
-    }
-#elif defined(BN_FAST_S_MP_MUL_HIGH_DIGS_C)
-    if ((res = fast_s_mp_mul_high_digs (&q, mu, &q, um)) != MP_OKAY) {
-      goto CLEANUP;
-    }
-#else 
-    { 
-#error mp_reduce would always fail
-      res = MP_VAL;
-      goto CLEANUP;
-    }
-#endif
-  }
-
-  /* q3 = q2 / b**(k+1) */
-  mp_rshd (&q, um + 1);         
-
-  /* x = x mod b**(k+1), quick (no division) */
-  if ((res = mp_mod_2d (x, DIGIT_BIT * (um + 1), x)) != MP_OKAY) {
-    goto CLEANUP;
-  }
-
-  /* q = q * m mod b**(k+1), quick (no division) */
-  if ((res = s_mp_mul_digs (&q, m, &q, um + 1)) != MP_OKAY) {
-    goto CLEANUP;
-  }
-
-  /* x = x - q */
-  if ((res = mp_sub (x, &q, x)) != MP_OKAY) {
-    goto CLEANUP;
-  }
-
-  /* If x < 0, add b**(k+1) to it */
-  if (mp_cmp_d (x, 0) == MP_LT) {
-    mp_set (&q, 1);
-    if ((res = mp_lshd (&q, um + 1)) != MP_OKAY) {
-      goto CLEANUP;
-    }
-    if ((res = mp_add (x, &q, x)) != MP_OKAY) {
-      goto CLEANUP;
-    }
-  }
-
-  /* Back off if it's too big */
-  while (mp_cmp (x, m) != MP_LT) {
-    if ((res = s_mp_sub (x, m, x)) != MP_OKAY) {
-      goto CLEANUP;
-    }
-  }
-  
-CLEANUP:
-  mp_clear (&q);
-
-  return res;
-}
-
-
-/* multiplies |a| * |b| and only computes up to digs digits of result
- * HAC pp. 595, Algorithm 14.12  Modified so you can control how 
- * many digits of output are created.
- */
-static int
-s_mp_mul_digs (mp_int * a, mp_int * b, mp_int * c, int digs)
-{
-  mp_int  t;
-  int     res, pa, pb, ix, iy;
-  mp_digit u;
-  mp_word r;
-  mp_digit tmpx, *tmpt, *tmpy;
-
-  /* can we use the fast multiplier? */
-  if (((digs) < MP_WARRAY) &&
-      MIN (a->used, b->used) < 
-          (1 << ((CHAR_BIT * sizeof (mp_word)) - (2 * DIGIT_BIT)))) {
-    return fast_s_mp_mul_digs (a, b, c, digs);
-  }
-
-  if ((res = mp_init_size (&t, digs)) != MP_OKAY) {
-    return res;
-  }
-  t.used = digs;
-
-  /* compute the digits of the product directly */
-  pa = a->used;
-  for (ix = 0; ix < pa; ix++) {
-    /* set the carry to zero */
-    u = 0;
-
-    /* limit ourselves to making digs digits of output */
-    pb = MIN (b->used, digs - ix);
-
-    /* setup some aliases */
-    /* copy of the digit from a used within the nested loop */
-    tmpx = a->dp[ix];
-    
-    /* an alias for the destination shifted ix places */
-    tmpt = t.dp + ix;
-    
-    /* an alias for the digits of b */
-    tmpy = b->dp;
-
-    /* compute the columns of the output and propagate the carry */
-    for (iy = 0; iy < pb; iy++) {
-      /* compute the column as a mp_word */
-      r       = ((mp_word)*tmpt) +
-                ((mp_word)tmpx) * ((mp_word)*tmpy++) +
-                ((mp_word) u);
-
-      /* the new column is the lower part of the result */
-      *tmpt++ = (mp_digit) (r & ((mp_word) MP_MASK));
-
-      /* get the carry word from the result */
-      u       = (mp_digit) (r >> ((mp_word) DIGIT_BIT));
-    }
-    /* set carry if it is placed below digs */
-    if (ix + iy < digs) {
-      *tmpt = u;
-    }
-  }
-
-  mp_clamp (&t);
-  mp_exch (&t, c);
-
-  mp_clear (&t);
-  return MP_OKAY;
-}
-
-
-/* Fast (comba) multiplier
- *
- * This is the fast column-array [comba] multiplier.  It is 
- * designed to compute the columns of the product first 
- * then handle the carries afterwards.  This has the effect 
- * of making the nested loops that compute the columns very
- * simple and schedulable on super-scalar processors.
- *
- * This has been modified to produce a variable number of 
- * digits of output so if say only a half-product is required 
- * you don't have to compute the upper half (a feature 
- * required for fast Barrett reduction).
- *
- * Based on Algorithm 14.12 on pp.595 of HAC.
- *
- */
-static int
-fast_s_mp_mul_digs (mp_int * a, mp_int * b, mp_int * c, int digs)
-{
-  int     olduse, res, pa, ix, iz;
-  mp_digit W[MP_WARRAY];
-  register mp_word  _W;
-
-  /* grow the destination as required */
-  if (c->alloc < digs) {
-    if ((res = mp_grow (c, digs)) != MP_OKAY) {
-      return res;
-    }
-  }
-
-  /* number of output digits to produce */
-  pa = MIN(digs, a->used + b->used);
-
-  /* clear the carry */
-  _W = 0;
-  for (ix = 0; ix < pa; ix++) { 
-      int      tx, ty;
-      int      iy;
-      mp_digit *tmpx, *tmpy;
-
-      /* get offsets into the two bignums */
-      ty = MIN(b->used-1, ix);
-      tx = ix - ty;
-
-      /* setup temp aliases */
-      tmpx = a->dp + tx;
-      tmpy = b->dp + ty;
-
-      /* this is the number of times the loop will iterrate, essentially 
-         while (tx++ < a->used && ty-- >= 0) { ... }
-       */
-      iy = MIN(a->used-tx, ty+1);
-
-      /* execute loop */
-      for (iz = 0; iz < iy; ++iz) {
-         _W += ((mp_word)*tmpx++)*((mp_word)*tmpy--);
-
-      }
-
-      /* store term */
-      W[ix] = ((mp_digit)_W) & MP_MASK;
-
-      /* make next carry */
-      _W = _W >> ((mp_word)DIGIT_BIT);
- }
-
-  /* setup dest */
-  olduse  = c->used;
-  c->used = pa;
-
-  {
-    register mp_digit *tmpc;
-    tmpc = c->dp;
-    for (ix = 0; ix < pa+1; ix++) {
-      /* now extract the previous digit [below the carry] */
-      *tmpc++ = W[ix];
-    }
-
-    /* clear unused digits [that existed in the old copy of c] */
-    for (; ix < olduse; ix++) {
-      *tmpc++ = 0;
-    }
-  }
-  mp_clamp (c);
-  return MP_OKAY;
-}
-
-
-/* init an mp_init for a given size */
-static int
-mp_init_size (mp_int * a, int size)
-{
-  int x;
-
-  /* pad size so there are always extra digits */
-  size += (MP_PREC * 2) - (size % MP_PREC);	
-  
-  /* alloc mem */
-  a->dp = OPT_CAST(mp_digit) XMALLOC (sizeof (mp_digit) * size);
-  if (a->dp == NULL) {
-    return MP_MEM;
-  }
-
-  /* set the members */
-  a->used  = 0;
-  a->alloc = size;
-  a->sign  = MP_ZPOS;
-
-  /* zero the digits */
-  for (x = 0; x < size; x++) {
-      a->dp[x] = 0;
-  }
-
-  return MP_OKAY;
-}
-
-
-/* low level squaring, b = a*a, HAC pp.596-597, Algorithm 14.16 */
-static int
-s_mp_sqr (mp_int * a, mp_int * b)
-{
-  mp_int  t;
-  int     res, ix, iy, pa;
-  mp_word r;
-  mp_digit u, tmpx, *tmpt;
-
-  pa = a->used;
-  if ((res = mp_init_size (&t, 2*pa + 1)) != MP_OKAY) {
-    return res;
-  }
-
-  /* default used is maximum possible size */
-  t.used = 2*pa + 1;
-
-  for (ix = 0; ix < pa; ix++) {
-    /* first calculate the digit at 2*ix */
-    /* calculate double precision result */
-    r = ((mp_word) t.dp[2*ix]) +
-        ((mp_word)a->dp[ix])*((mp_word)a->dp[ix]);
-
-    /* store lower part in result */
-    t.dp[ix+ix] = (mp_digit) (r & ((mp_word) MP_MASK));
-
-    /* get the carry */
-    u           = (mp_digit)(r >> ((mp_word) DIGIT_BIT));
-
-    /* left hand side of A[ix] * A[iy] */
-    tmpx        = a->dp[ix];
-
-    /* alias for where to store the results */
-    tmpt        = t.dp + (2*ix + 1);
-    
-    for (iy = ix + 1; iy < pa; iy++) {
-      /* first calculate the product */
-      r       = ((mp_word)tmpx) * ((mp_word)a->dp[iy]);
-
-      /* now calculate the double precision result, note we use
-       * addition instead of *2 since it's easier to optimize
-       */
-      r       = ((mp_word) *tmpt) + r + r + ((mp_word) u);
-
-      /* store lower part */
-      *tmpt++ = (mp_digit) (r & ((mp_word) MP_MASK));
-
-      /* get carry */
-      u       = (mp_digit)(r >> ((mp_word) DIGIT_BIT));
-    }
-    /* propagate upwards */
-    while (u != ((mp_digit) 0)) {
-      r       = ((mp_word) *tmpt) + ((mp_word) u);
-      *tmpt++ = (mp_digit) (r & ((mp_word) MP_MASK));
-      u       = (mp_digit)(r >> ((mp_word) DIGIT_BIT));
-    }
-  }
-
-  mp_clamp (&t);
-  mp_exch (&t, b);
-  mp_clear (&t);
-  return MP_OKAY;
-}
-
-
-/* multiplies |a| * |b| and does not compute the lower digs digits
- * [meant to get the higher part of the product]
- */
-static int
-s_mp_mul_high_digs (mp_int * a, mp_int * b, mp_int * c, int digs)
-{
-  mp_int  t;
-  int     res, pa, pb, ix, iy;
-  mp_digit u;
-  mp_word r;
-  mp_digit tmpx, *tmpt, *tmpy;
-
-  /* can we use the fast multiplier? */
-#ifdef BN_FAST_S_MP_MUL_HIGH_DIGS_C
-  if (((a->used + b->used + 1) < MP_WARRAY)
-      && MIN (a->used, b->used) < (1 << ((CHAR_BIT * sizeof (mp_word)) - (2 * DIGIT_BIT)))) {
-    return fast_s_mp_mul_high_digs (a, b, c, digs);
-  }
-#endif
-
-  if ((res = mp_init_size (&t, a->used + b->used + 1)) != MP_OKAY) {
-    return res;
-  }
-  t.used = a->used + b->used + 1;
-
-  pa = a->used;
-  pb = b->used;
-  for (ix = 0; ix < pa; ix++) {
-    /* clear the carry */
-    u = 0;
-
-    /* left hand side of A[ix] * B[iy] */
-    tmpx = a->dp[ix];
-
-    /* alias to the address of where the digits will be stored */
-    tmpt = &(t.dp[digs]);
-
-    /* alias for where to read the right hand side from */
-    tmpy = b->dp + (digs - ix);
-
-    for (iy = digs - ix; iy < pb; iy++) {
-      /* calculate the double precision result */
-      r       = ((mp_word)*tmpt) +
-                ((mp_word)tmpx) * ((mp_word)*tmpy++) +
-                ((mp_word) u);
-
-      /* get the lower part */
-      *tmpt++ = (mp_digit) (r & ((mp_word) MP_MASK));
-
-      /* carry the carry */
-      u       = (mp_digit) (r >> ((mp_word) DIGIT_BIT));
-    }
-    *tmpt = u;
-  }
-  mp_clamp (&t);
-  mp_exch (&t, c);
-  mp_clear (&t);
-  return MP_OKAY;
-}
-
-
-#ifdef BN_MP_MONTGOMERY_SETUP_C
-/* setups the montgomery reduction stuff */
-static int
-mp_montgomery_setup (mp_int * n, mp_digit * rho)
-{
-  mp_digit x, b;
-
-/* fast inversion mod 2**k
- *
- * Based on the fact that
- *
- * XA = 1 (mod 2**n)  =>  (X(2-XA)) A = 1 (mod 2**2n)
- *                    =>  2*X*A - X*X*A*A = 1
- *                    =>  2*(1) - (1)     = 1
- */
-  b = n->dp[0];
-
-  if ((b & 1) == 0) {
-    return MP_VAL;
-  }
-
-  x = (((b + 2) & 4) << 1) + b; /* here x*a==1 mod 2**4 */
-  x *= 2 - b * x;               /* here x*a==1 mod 2**8 */
-#if !defined(MP_8BIT)
-  x *= 2 - b * x;               /* here x*a==1 mod 2**16 */
-#endif
-#if defined(MP_64BIT) || !(defined(MP_8BIT) || defined(MP_16BIT))
-  x *= 2 - b * x;               /* here x*a==1 mod 2**32 */
-#endif
-#ifdef MP_64BIT
-  x *= 2 - b * x;               /* here x*a==1 mod 2**64 */
-#endif
-
-  /* rho = -1/m mod b */
-  *rho = (unsigned long)(((mp_word)1 << ((mp_word) DIGIT_BIT)) - x) & MP_MASK;
-
-  return MP_OKAY;
-}
-#endif
-
-
-#ifdef BN_FAST_MP_MONTGOMERY_REDUCE_C
-/* computes xR**-1 == x (mod N) via Montgomery Reduction
- *
- * This is an optimized implementation of montgomery_reduce
- * which uses the comba method to quickly calculate the columns of the
- * reduction.
- *
- * Based on Algorithm 14.32 on pp.601 of HAC.
-*/
-int
-fast_mp_montgomery_reduce (mp_int * x, mp_int * n, mp_digit rho)
-{
-  int     ix, res, olduse;
-  mp_word W[MP_WARRAY];
-
-  /* get old used count */
-  olduse = x->used;
-
-  /* grow a as required */
-  if (x->alloc < n->used + 1) {
-    if ((res = mp_grow (x, n->used + 1)) != MP_OKAY) {
-      return res;
-    }
-  }
-
-  /* first we have to get the digits of the input into
-   * an array of double precision words W[...]
-   */
-  {
-    register mp_word *_W;
-    register mp_digit *tmpx;
-
-    /* alias for the W[] array */
-    _W   = W;
-
-    /* alias for the digits of  x*/
-    tmpx = x->dp;
-
-    /* copy the digits of a into W[0..a->used-1] */
-    for (ix = 0; ix < x->used; ix++) {
-      *_W++ = *tmpx++;
-    }
-
-    /* zero the high words of W[a->used..m->used*2] */
-    for (; ix < n->used * 2 + 1; ix++) {
-      *_W++ = 0;
-    }
-  }
-
-  /* now we proceed to zero successive digits
-   * from the least significant upwards
-   */
-  for (ix = 0; ix < n->used; ix++) {
-    /* mu = ai * m' mod b
-     *
-     * We avoid a double precision multiplication (which isn't required)
-     * by casting the value down to a mp_digit.  Note this requires
-     * that W[ix-1] have  the carry cleared (see after the inner loop)
-     */
-    register mp_digit mu;
-    mu = (mp_digit) (((W[ix] & MP_MASK) * rho) & MP_MASK);
-
-    /* a = a + mu * m * b**i
-     *
-     * This is computed in place and on the fly.  The multiplication
-     * by b**i is handled by offseting which columns the results
-     * are added to.
-     *
-     * Note the comba method normally doesn't handle carries in the
-     * inner loop In this case we fix the carry from the previous
-     * column since the Montgomery reduction requires digits of the
-     * result (so far) [see above] to work.  This is
-     * handled by fixing up one carry after the inner loop.  The
-     * carry fixups are done in order so after these loops the
-     * first m->used words of W[] have the carries fixed
-     */
-    {
-      register int iy;
-      register mp_digit *tmpn;
-      register mp_word *_W;
-
-      /* alias for the digits of the modulus */
-      tmpn = n->dp;
-
-      /* Alias for the columns set by an offset of ix */
-      _W = W + ix;
-
-      /* inner loop */
-      for (iy = 0; iy < n->used; iy++) {
-          *_W++ += ((mp_word)mu) * ((mp_word)*tmpn++);
-      }
-    }
-
-    /* now fix carry for next digit, W[ix+1] */
-    W[ix + 1] += W[ix] >> ((mp_word) DIGIT_BIT);
-  }
-
-  /* now we have to propagate the carries and
-   * shift the words downward [all those least
-   * significant digits we zeroed].
-   */
-  {
-    register mp_digit *tmpx;
-    register mp_word *_W, *_W1;
-
-    /* nox fix rest of carries */
-
-    /* alias for current word */
-    _W1 = W + ix;
-
-    /* alias for next word, where the carry goes */
-    _W = W + ++ix;
-
-    for (; ix <= n->used * 2 + 1; ix++) {
-      *_W++ += *_W1++ >> ((mp_word) DIGIT_BIT);
-    }
-
-    /* copy out, A = A/b**n
-     *
-     * The result is A/b**n but instead of converting from an
-     * array of mp_word to mp_digit than calling mp_rshd
-     * we just copy them in the right order
-     */
-
-    /* alias for destination word */
-    tmpx = x->dp;
-
-    /* alias for shifted double precision result */
-    _W = W + n->used;
-
-    for (ix = 0; ix < n->used + 1; ix++) {
-      *tmpx++ = (mp_digit)(*_W++ & ((mp_word) MP_MASK));
-    }
-
-    /* zero oldused digits, if the input a was larger than
-     * m->used+1 we'll have to clear the digits
-     */
-    for (; ix < olduse; ix++) {
-      *tmpx++ = 0;
-    }
-  }
-
-  /* set the max used and clamp */
-  x->used = n->used + 1;
-  mp_clamp (x);
-
-  /* if A >= m then A = A - m */
-  if (mp_cmp_mag (x, n) != MP_LT) {
-    return s_mp_sub (x, n, x);
-  }
-  return MP_OKAY;
-}
-#endif
-
-
-#ifdef BN_MP_MUL_2_C
-/* b = a*2 */
-static int
-mp_mul_2(mp_int * a, mp_int * b)
-{
-  int     x, res, oldused;
-
-  /* grow to accommodate result */
-  if (b->alloc < a->used + 1) {
-    if ((res = mp_grow (b, a->used + 1)) != MP_OKAY) {
-      return res;
-    }
-  }
-
-  oldused = b->used;
-  b->used = a->used;
-
-  {
-    register mp_digit r, rr, *tmpa, *tmpb;
-
-    /* alias for source */
-    tmpa = a->dp;
-    
-    /* alias for dest */
-    tmpb = b->dp;
-
-    /* carry */
-    r = 0;
-    for (x = 0; x < a->used; x++) {
-    
-      /* get what will be the *next* carry bit from the 
-       * MSB of the current digit 
-       */
-      rr = *tmpa >> ((mp_digit)(DIGIT_BIT - 1));
-      
-      /* now shift up this digit, add in the carry [from the previous] */
-      *tmpb++ = ((*tmpa++ << ((mp_digit)1)) | r) & MP_MASK;
-      
-      /* copy the carry that would be from the source 
-       * digit into the next iteration 
-       */
-      r = rr;
-    }
-
-    /* new leading digit? */
-    if (r != 0) {
-      /* add a MSB which is always 1 at this point */
-      *tmpb = 1;
-      ++(b->used);
-    }
-
-    /* now zero any excess digits on the destination 
-     * that we didn't write to 
-     */
-    tmpb = b->dp + b->used;
-    for (x = b->used; x < oldused; x++) {
-      *tmpb++ = 0;
-    }
-  }
-  b->sign = a->sign;
-  return MP_OKAY;
-}
-#endif
-
-
-#ifdef BN_MP_MONTGOMERY_CALC_NORMALIZATION_C
-/*
- * shifts with subtractions when the result is greater than b.
- *
- * The method is slightly modified to shift B unconditionally up to just under
- * the leading bit of b.  This saves a lot of multiple precision shifting.
- */
-static int
-mp_montgomery_calc_normalization (mp_int * a, mp_int * b)
-{
-  int     x, bits, res;
-
-  /* how many bits of last digit does b use */
-  bits = mp_count_bits (b) % DIGIT_BIT;
-
-  if (b->used > 1) {
-     if ((res = mp_2expt (a, (b->used - 1) * DIGIT_BIT + bits - 1)) != MP_OKAY) {
-        return res;
-     }
-  } else {
-     mp_set(a, 1);
-     bits = 1;
-  }
-
-
-  /* now compute C = A * B mod b */
-  for (x = bits - 1; x < (int)DIGIT_BIT; x++) {
-    if ((res = mp_mul_2 (a, a)) != MP_OKAY) {
-      return res;
-    }
-    if (mp_cmp_mag (a, b) != MP_LT) {
-      if ((res = s_mp_sub (a, b, a)) != MP_OKAY) {
-        return res;
-      }
-    }
-  }
-
-  return MP_OKAY;
-}
-#endif
-
-
-#ifdef BN_MP_EXPTMOD_FAST_C
-/* computes Y == G**X mod P, HAC pp.616, Algorithm 14.85
- *
- * Uses a left-to-right k-ary sliding window to compute the modular exponentiation.
- * The value of k changes based on the size of the exponent.
- *
- * Uses Montgomery or Diminished Radix reduction [whichever appropriate]
- */
-
-static int
-mp_exptmod_fast (mp_int * G, mp_int * X, mp_int * P, mp_int * Y, int redmode)
-{
-  mp_int  M[TAB_SIZE], res;
-  mp_digit buf, mp;
-  int     err, bitbuf, bitcpy, bitcnt, mode, digidx, x, y, winsize;
-
-  /* use a pointer to the reduction algorithm.  This allows us to use
-   * one of many reduction algorithms without modding the guts of
-   * the code with if statements everywhere.
-   */
-  int     (*redux)(mp_int*,mp_int*,mp_digit);
-
-  /* find window size */
-  x = mp_count_bits (X);
-  if (x <= 7) {
-    winsize = 2;
-  } else if (x <= 36) {
-    winsize = 3;
-  } else if (x <= 140) {
-    winsize = 4;
-  } else if (x <= 450) {
-    winsize = 5;
-  } else if (x <= 1303) {
-    winsize = 6;
-  } else if (x <= 3529) {
-    winsize = 7;
-  } else {
-    winsize = 8;
-  }
-
-#ifdef MP_LOW_MEM
-  if (winsize > 5) {
-     winsize = 5;
-  }
-#endif
-
-  /* init M array */
-  /* init first cell */
-  if ((err = mp_init(&M[1])) != MP_OKAY) {
-     return err;
-  }
-
-  /* now init the second half of the array */
-  for (x = 1<<(winsize-1); x < (1 << winsize); x++) {
-    if ((err = mp_init(&M[x])) != MP_OKAY) {
-      for (y = 1<<(winsize-1); y < x; y++) {
-        mp_clear (&M[y]);
-      }
-      mp_clear(&M[1]);
-      return err;
-    }
-  }
-
-  /* determine and setup reduction code */
-  if (redmode == 0) {
-#ifdef BN_MP_MONTGOMERY_SETUP_C     
-     /* now setup montgomery  */
-     if ((err = mp_montgomery_setup (P, &mp)) != MP_OKAY) {
-        goto LBL_M;
-     }
-#else
-     err = MP_VAL;
-     goto LBL_M;
-#endif
-
-     /* automatically pick the comba one if available (saves quite a few calls/ifs) */
-#ifdef BN_FAST_MP_MONTGOMERY_REDUCE_C
-     if (((P->used * 2 + 1) < MP_WARRAY) &&
-          P->used < (1 << ((CHAR_BIT * sizeof (mp_word)) - (2 * DIGIT_BIT)))) {
-        redux = fast_mp_montgomery_reduce;
-     } else 
-#endif
-     {
-#ifdef BN_MP_MONTGOMERY_REDUCE_C
-        /* use slower baseline Montgomery method */
-        redux = mp_montgomery_reduce;
-#else
-        err = MP_VAL;
-        goto LBL_M;
-#endif
-     }
-  } else if (redmode == 1) {
-#if defined(BN_MP_DR_SETUP_C) && defined(BN_MP_DR_REDUCE_C)
-     /* setup DR reduction for moduli of the form B**k - b */
-     mp_dr_setup(P, &mp);
-     redux = mp_dr_reduce;
-#else
-     err = MP_VAL;
-     goto LBL_M;
-#endif
-  } else {
-#if defined(BN_MP_REDUCE_2K_SETUP_C) && defined(BN_MP_REDUCE_2K_C)
-     /* setup DR reduction for moduli of the form 2**k - b */
-     if ((err = mp_reduce_2k_setup(P, &mp)) != MP_OKAY) {
-        goto LBL_M;
-     }
-     redux = mp_reduce_2k;
-#else
-     err = MP_VAL;
-     goto LBL_M;
-#endif
-  }
-
-  /* setup result */
-  if ((err = mp_init (&res)) != MP_OKAY) {
-    goto LBL_M;
-  }
-
-  /* create M table
-   *
-
-   *
-   * The first half of the table is not computed though accept for M[0] and M[1]
-   */
-
-  if (redmode == 0) {
-#ifdef BN_MP_MONTGOMERY_CALC_NORMALIZATION_C
-     /* now we need R mod m */
-     if ((err = mp_montgomery_calc_normalization (&res, P)) != MP_OKAY) {
-       goto LBL_RES;
-     }
-#else 
-     err = MP_VAL;
-     goto LBL_RES;
-#endif
-
-     /* now set M[1] to G * R mod m */
-     if ((err = mp_mulmod (G, &res, P, &M[1])) != MP_OKAY) {
-       goto LBL_RES;
-     }
-  } else {
-     mp_set(&res, 1);
-     if ((err = mp_mod(G, P, &M[1])) != MP_OKAY) {
-        goto LBL_RES;
-     }
-  }
-
-  /* compute the value at M[1<<(winsize-1)] by squaring M[1] (winsize-1) times */
-  if ((err = mp_copy (&M[1], &M[1 << (winsize - 1)])) != MP_OKAY) {
-    goto LBL_RES;
-  }
-
-  for (x = 0; x < (winsize - 1); x++) {
-    if ((err = mp_sqr (&M[1 << (winsize - 1)], &M[1 << (winsize - 1)])) != MP_OKAY) {
-      goto LBL_RES;
-    }
-    if ((err = redux (&M[1 << (winsize - 1)], P, mp)) != MP_OKAY) {
-      goto LBL_RES;
-    }
-  }
-
-  /* create upper table */
-  for (x = (1 << (winsize - 1)) + 1; x < (1 << winsize); x++) {
-    if ((err = mp_mul (&M[x - 1], &M[1], &M[x])) != MP_OKAY) {
-      goto LBL_RES;
-    }
-    if ((err = redux (&M[x], P, mp)) != MP_OKAY) {
-      goto LBL_RES;
-    }
-  }
-
-  /* set initial mode and bit cnt */
-  mode   = 0;
-  bitcnt = 1;
-  buf    = 0;
-  digidx = X->used - 1;
-  bitcpy = 0;
-  bitbuf = 0;
-
-  for (;;) {
-    /* grab next digit as required */
-    if (--bitcnt == 0) {
-      /* if digidx == -1 we are out of digits so break */
-      if (digidx == -1) {
-        break;
-      }
-      /* read next digit and reset bitcnt */
-      buf    = X->dp[digidx--];
-      bitcnt = (int)DIGIT_BIT;
-    }
-
-    /* grab the next msb from the exponent */
-    y     = (mp_digit)(buf >> (DIGIT_BIT - 1)) & 1;
-    buf <<= (mp_digit)1;
-
-    /* if the bit is zero and mode == 0 then we ignore it
-     * These represent the leading zero bits before the first 1 bit
-     * in the exponent.  Technically this opt is not required but it
-     * does lower the # of trivial squaring/reductions used
-     */
-    if (mode == 0 && y == 0) {
-      continue;
-    }
-
-    /* if the bit is zero and mode == 1 then we square */
-    if (mode == 1 && y == 0) {
-      if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-      if ((err = redux (&res, P, mp)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-      continue;
-    }
-
-    /* else we add it to the window */
-    bitbuf |= (y << (winsize - ++bitcpy));
-    mode    = 2;
-
-    if (bitcpy == winsize) {
-      /* ok window is filled so square as required and multiply  */
-      /* square first */
-      for (x = 0; x < winsize; x++) {
-        if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
-          goto LBL_RES;
-        }
-        if ((err = redux (&res, P, mp)) != MP_OKAY) {
-          goto LBL_RES;
-        }
-      }
-
-      /* then multiply */
-      if ((err = mp_mul (&res, &M[bitbuf], &res)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-      if ((err = redux (&res, P, mp)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-
-      /* empty window and reset */
-      bitcpy = 0;
-      bitbuf = 0;
-      mode   = 1;
-    }
-  }
-
-  /* if bits remain then square/multiply */
-  if (mode == 2 && bitcpy > 0) {
-    /* square then multiply if the bit is set */
-    for (x = 0; x < bitcpy; x++) {
-      if ((err = mp_sqr (&res, &res)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-      if ((err = redux (&res, P, mp)) != MP_OKAY) {
-        goto LBL_RES;
-      }
-
-      /* get next bit of the window */
-      bitbuf <<= 1;
-      if ((bitbuf & (1 << winsize)) != 0) {
-        /* then multiply */
-        if ((err = mp_mul (&res, &M[1], &res)) != MP_OKAY) {
-          goto LBL_RES;
-        }
-        if ((err = redux (&res, P, mp)) != MP_OKAY) {
-          goto LBL_RES;
-        }
-      }
-    }
-  }
-
-  if (redmode == 0) {
-     /* fixup result if Montgomery reduction is used
-      * recall that any value in a Montgomery system is
-      * actually multiplied by R mod n.  So we have
-      * to reduce one more time to cancel out the factor
-      * of R.
-      */
-     if ((err = redux(&res, P, mp)) != MP_OKAY) {
-       goto LBL_RES;
-     }
-  }
-
-  /* swap res with Y */
-  mp_exch (&res, Y);
-  err = MP_OKAY;
-LBL_RES:mp_clear (&res);
-LBL_M:
-  mp_clear(&M[1]);
-  for (x = 1<<(winsize-1); x < (1 << winsize); x++) {
-    mp_clear (&M[x]);
-  }
-  return err;
-}
-#endif
-
-
-#ifdef BN_FAST_S_MP_SQR_C
-/* the jist of squaring...
- * you do like mult except the offset of the tmpx [one that 
- * starts closer to zero] can't equal the offset of tmpy.  
- * So basically you set up iy like before then you min it with
- * (ty-tx) so that it never happens.  You double all those 
- * you add in the inner loop
-
-After that loop you do the squares and add them in.
-*/
-
-static int
-fast_s_mp_sqr (mp_int * a, mp_int * b)
-{
-  int       olduse, res, pa, ix, iz;
-  mp_digit   W[MP_WARRAY], *tmpx;
-  mp_word   W1;
-
-  /* grow the destination as required */
-  pa = a->used + a->used;
-  if (b->alloc < pa) {
-    if ((res = mp_grow (b, pa)) != MP_OKAY) {
-      return res;
-    }
-  }
-
-  /* number of output digits to produce */
-  W1 = 0;
-  for (ix = 0; ix < pa; ix++) { 
-      int      tx, ty, iy;
-      mp_word  _W;
-      mp_digit *tmpy;
-
-      /* clear counter */
-      _W = 0;
-
-      /* get offsets into the two bignums */
-      ty = MIN(a->used-1, ix);
-      tx = ix - ty;
-
-      /* setup temp aliases */
-      tmpx = a->dp + tx;
-      tmpy = a->dp + ty;
-
-      /* this is the number of times the loop will iterrate, essentially
-         while (tx++ < a->used && ty-- >= 0) { ... }
-       */
-      iy = MIN(a->used-tx, ty+1);
-
-      /* now for squaring tx can never equal ty 
-       * we halve the distance since they approach at a rate of 2x
-       * and we have to round because odd cases need to be executed
-       */
-      iy = MIN(iy, (ty-tx+1)>>1);
-
-      /* execute loop */
-      for (iz = 0; iz < iy; iz++) {
-         _W += ((mp_word)*tmpx++)*((mp_word)*tmpy--);
-      }
-
-      /* double the inner product and add carry */
-      _W = _W + _W + W1;
-
-      /* even columns have the square term in them */
-      if ((ix&1) == 0) {
-         _W += ((mp_word)a->dp[ix>>1])*((mp_word)a->dp[ix>>1]);
-      }
-
-      /* store it */
-      W[ix] = (mp_digit)(_W & MP_MASK);
-
-      /* make next carry */
-      W1 = _W >> ((mp_word)DIGIT_BIT);
-  }
-
-  /* setup dest */
-  olduse  = b->used;
-  b->used = a->used+a->used;
-
-  {
-    mp_digit *tmpb;
-    tmpb = b->dp;
-    for (ix = 0; ix < pa; ix++) {
-      *tmpb++ = W[ix] & MP_MASK;
-    }
-
-    /* clear unused digits [that existed in the old copy of c] */
-    for (; ix < olduse; ix++) {
-      *tmpb++ = 0;
-    }
-  }
-  mp_clamp (b);
-  return MP_OKAY;
-}
-#endif
-
-
-#ifdef BN_MP_MUL_D_C
-/* multiply by a digit */
-static int
-mp_mul_d (mp_int * a, mp_digit b, mp_int * c)
-{
-  mp_digit u, *tmpa, *tmpc;
-  mp_word  r;
-  int      ix, res, olduse;
-
-  /* make sure c is big enough to hold a*b */
-  if (c->alloc < a->used + 1) {
-    if ((res = mp_grow (c, a->used + 1)) != MP_OKAY) {
-      return res;
-    }
-  }
-
-  /* get the original destinations used count */
-  olduse = c->used;
-
-  /* set the sign */
-  c->sign = a->sign;
-
-  /* alias for a->dp [source] */
-  tmpa = a->dp;
-
-  /* alias for c->dp [dest] */
-  tmpc = c->dp;
-
-  /* zero carry */
-  u = 0;
-
-  /* compute columns */
-  for (ix = 0; ix < a->used; ix++) {
-    /* compute product and carry sum for this term */
-    r       = ((mp_word) u) + ((mp_word)*tmpa++) * ((mp_word)b);
-
-    /* mask off higher bits to get a single digit */
-    *tmpc++ = (mp_digit) (r & ((mp_word) MP_MASK));
-
-    /* send carry into next iteration */
-    u       = (mp_digit) (r >> ((mp_word) DIGIT_BIT));
-  }
-
-  /* store final carry [if any] and increment ix offset  */
-  *tmpc++ = u;
-  ++ix;
-
-  /* now zero digits above the top */
-  while (ix++ < olduse) {
-     *tmpc++ = 0;
-  }
-
-  /* set used count */
-  c->used = a->used + 1;
-  mp_clamp(c);
-
-  return MP_OKAY;
-}
-#endif
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/pkcs1.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/pkcs1.h
deleted file mode 100644
index ed64defaafe..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/pkcs1.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * PKCS #1 (RSA Encryption)
- * Copyright (c) 2006-2009, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef PKCS1_H
-#define PKCS1_H
-
-int pkcs1_encrypt(int block_type, struct crypto_rsa_key *key,
-		  int use_private, const u8 *in, size_t inlen,
-		  u8 *out, size_t *outlen);
-int pkcs1_v15_private_key_decrypt(struct crypto_rsa_key *key,
-				  const u8 *in, size_t inlen,
-				  u8 *out, size_t *outlen);
-int pkcs1_decrypt_public_key(struct crypto_rsa_key *key,
-			     const u8 *crypt, size_t crypt_len,
-			     u8 *plain, size_t *plain_len);
-
-#endif /* PKCS1_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/pkcs5.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/pkcs5.h
deleted file mode 100644
index 20ddadc4572..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/pkcs5.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * PKCS #5 (Password-based Encryption)
- * Copyright (c) 2009, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef PKCS5_H
-#define PKCS5_H
-
-u8 * pkcs5_decrypt(const u8 *enc_alg, size_t enc_alg_len,
-		   const u8 *enc_data, size_t enc_data_len,
-		   const char *passwd, size_t *data_len);
-
-#endif /* PKCS5_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/pkcs8.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/pkcs8.h
deleted file mode 100644
index bebf840ba75..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/pkcs8.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * PKCS #8 (Private-key information syntax)
- * Copyright (c) 2006-2009, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef PKCS8_H
-#define PKCS8_H
-
-struct crypto_private_key * pkcs8_key_import(const u8 *buf, size_t len);
-struct crypto_private_key *
-pkcs8_enc_key_import(const u8 *buf, size_t len, const char *passwd);
-
-#endif /* PKCS8_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/rsa.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/rsa.h
deleted file mode 100644
index c236a9df444..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/rsa.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * RSA
- * Copyright (c) 2006, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef RSA_H
-#define RSA_H
-
-struct crypto_rsa_key;
-
-struct crypto_rsa_key *
-crypto_rsa_import_public_key(const u8 *buf, size_t len);
-struct crypto_rsa_key *
-crypto_rsa_import_private_key(const u8 *buf, size_t len);
-size_t crypto_rsa_get_modulus_len(struct crypto_rsa_key *key);
-int crypto_rsa_exptmod(const u8 *in, size_t inlen, u8 *out, size_t *outlen,
-		       struct crypto_rsa_key *key, int use_private);
-void crypto_rsa_free(struct crypto_rsa_key *key);
-
-#endif /* RSA_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/tls.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/tls.h
deleted file mode 100644
index 983999b51d6..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/tls.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * SSL/TLS interface definition
- * Copyright (c) 2004-2013, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef TLS_H
-#define TLS_H
-
-struct tls_connection;
-
-struct tls_keys {
-	const u8 *master_key; /* TLS master secret */
-	size_t master_key_len;
-	const u8 *client_random;
-	size_t client_random_len;
-	const u8 *server_random;
-	size_t server_random_len;
-};
-
-enum tls_event {
-	TLS_CERT_CHAIN_SUCCESS,
-	TLS_CERT_CHAIN_FAILURE,
-	TLS_PEER_CERTIFICATE,
-	TLS_ALERT
-};
-
-/*
- * Note: These are used as identifier with external programs and as such, the
- * values must not be changed.
- */
-enum tls_fail_reason {
-	TLS_FAIL_UNSPECIFIED = 0,
-	TLS_FAIL_UNTRUSTED = 1,
-	TLS_FAIL_REVOKED = 2,
-	TLS_FAIL_NOT_YET_VALID = 3,
-	TLS_FAIL_EXPIRED = 4,
-	TLS_FAIL_SUBJECT_MISMATCH = 5,
-	TLS_FAIL_ALTSUBJECT_MISMATCH = 6,
-	TLS_FAIL_BAD_CERTIFICATE = 7,
-	TLS_FAIL_SERVER_CHAIN_PROBE = 8
-};
-
-union tls_event_data {
-	struct {
-		int depth;
-		const char *subject;
-		enum tls_fail_reason reason;
-		const char *reason_txt;
-		const struct wpabuf *cert;
-	} cert_fail;
-
-	struct {
-		int depth;
-		const char *subject;
-		const struct wpabuf *cert;
-		const u8 *hash;
-		size_t hash_len;
-	} peer_cert;
-
-	struct {
-		int is_local;
-		const char *type;
-		const char *description;
-	} alert;
-};
-
-struct tls_config {
-	const char *opensc_engine_path;
-	const char *pkcs11_engine_path;
-	const char *pkcs11_module_path;
-	int fips_mode;
-	int cert_in_cb;
-
-	void (*event_cb)(void *ctx, enum tls_event ev,
-			 union tls_event_data *data);
-	void *cb_ctx;
-};
-
-#define TLS_CONN_ALLOW_SIGN_RSA_MD5 BIT(0)
-#define TLS_CONN_DISABLE_TIME_CHECKS BIT(1)
-#define TLS_CONN_DISABLE_SESSION_TICKET BIT(2)
-#define TLS_CONN_REQUEST_OCSP BIT(3)
-#define TLS_CONN_REQUIRE_OCSP BIT(4)
-
-/**
- * struct tls_connection_params - Parameters for TLS connection
- * @ca_cert: File or reference name for CA X.509 certificate in PEM or DER
- * format
- * @ca_cert_blob: ca_cert as inlined data or %NULL if not used
- * @ca_cert_blob_len: ca_cert_blob length
- * @ca_path: Path to CA certificates (OpenSSL specific)
- * @subject_match: String to match in the subject of the peer certificate or
- * %NULL to allow all subjects
- * @altsubject_match: String to match in the alternative subject of the peer
- * certificate or %NULL to allow all alternative subjects
- * @client_cert: File or reference name for client X.509 certificate in PEM or
- * DER format
- * @client_cert_blob: client_cert as inlined data or %NULL if not used
- * @client_cert_blob_len: client_cert_blob length
- * @private_key: File or reference name for client private key in PEM or DER
- * format (traditional format (RSA PRIVATE KEY) or PKCS#8 (PRIVATE KEY)
- * @private_key_blob: private_key as inlined data or %NULL if not used
- * @private_key_blob_len: private_key_blob length
- * @private_key_passwd: Passphrase for decrypted private key, %NULL if no
- * passphrase is used.
- * @dh_file: File name for DH/DSA data in PEM format, or %NULL if not used
- * @dh_blob: dh_file as inlined data or %NULL if not used
- * @dh_blob_len: dh_blob length
- * @engine: 1 = use engine (e.g., a smartcard) for private key operations
- * (this is OpenSSL specific for now)
- * @engine_id: engine id string (this is OpenSSL specific for now)
- * @ppin: pointer to the pin variable in the configuration
- * (this is OpenSSL specific for now)
- * @key_id: the private key's id when using engine (this is OpenSSL
- * specific for now)
- * @cert_id: the certificate's id when using engine
- * @ca_cert_id: the CA certificate's id when using engine
- * @flags: Parameter options (TLS_CONN_*)
- * @ocsp_stapling_response: DER encoded file with cached OCSP stapling response
- *	or %NULL if OCSP is not enabled
- *
- * TLS connection parameters to be configured with tls_connection_set_params()
- * and tls_global_set_params().
- *
- * Certificates and private key can be configured either as a reference name
- * (file path or reference to certificate store) or by providing the same data
- * as a pointer to the data in memory. Only one option will be used for each
- * field.
- */
-struct tls_connection_params {
-	const char *ca_cert;
-	const u8 *ca_cert_blob;
-	size_t ca_cert_blob_len;
-	const char *ca_path;
-	const char *subject_match;
-	const char *altsubject_match;
-	const char *client_cert;
-	const u8 *client_cert_blob;
-	size_t client_cert_blob_len;
-	const char *private_key;
-	const u8 *private_key_blob;
-	size_t private_key_blob_len;
-	const char *private_key_passwd;
-	const char *dh_file;
-	const u8 *dh_blob;
-	size_t dh_blob_len;
-
-	/* OpenSSL specific variables */
-	int engine;
-	const char *engine_id;
-	const char *pin;
-	const char *key_id;
-	const char *cert_id;
-	const char *ca_cert_id;
-
-	unsigned int flags;
-	const char *ocsp_stapling_response;
-};
-
-
-/**
- * tls_init - Initialize TLS library
- * @conf: Configuration data for TLS library
- * Returns: Context data to be used as tls_ctx in calls to other functions,
- * or %NULL on failure.
- *
- * Called once during program startup and once for each RSN pre-authentication
- * session. In other words, there can be two concurrent TLS contexts. If global
- * library initialization is needed (i.e., one that is shared between both
- * authentication types), the TLS library wrapper should maintain a reference
- * counter and do global initialization only when moving from 0 to 1 reference.
- */
-void * tls_init(void);
-
-/**
- * tls_deinit - Deinitialize TLS library
- * @tls_ctx: TLS context data from tls_init()
- *
- * Called once during program shutdown and once for each RSN pre-authentication
- * session. If global library deinitialization is needed (i.e., one that is
- * shared between both authentication types), the TLS library wrapper should
- * maintain a reference counter and do global deinitialization only when moving
- * from 1 to 0 references.
- */
-void tls_deinit(void *tls_ctx);
-
-/**
- * tls_get_errors - Process pending errors
- * @tls_ctx: TLS context data from tls_init()
- * Returns: Number of found error, 0 if no errors detected.
- *
- * Process all pending TLS errors.
- */
-int tls_get_errors(void *tls_ctx);
-
-/**
- * tls_connection_init - Initialize a new TLS connection
- * @tls_ctx: TLS context data from tls_init()
- * Returns: Connection context data, conn for other function calls
- */
-struct tls_connection * tls_connection_init(void *tls_ctx);
-
-/**
- * tls_connection_deinit - Free TLS connection data
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- *
- * Release all resources allocated for TLS connection.
- */
-void tls_connection_deinit(void *tls_ctx, struct tls_connection *conn);
-
-/**
- * tls_connection_established - Has the TLS connection been completed?
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * Returns: 1 if TLS connection has been completed, 0 if not.
- */
-int tls_connection_established(void *tls_ctx, struct tls_connection *conn);
-
-/**
- * tls_connection_shutdown - Shutdown TLS connection
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * Returns: 0 on success, -1 on failure
- *
- * Shutdown current TLS connection without releasing all resources. New
- * connection can be started by using the same conn without having to call
- * tls_connection_init() or setting certificates etc. again. The new
- * connection should try to use session resumption.
- */
-int tls_connection_shutdown(void *tls_ctx, struct tls_connection *conn);
-
-enum {
-	TLS_SET_PARAMS_ENGINE_PRV_VERIFY_FAILED = -3,
-	TLS_SET_PARAMS_ENGINE_PRV_INIT_FAILED = -2
-};
-
-/**
- * tls_connection_set_params - Set TLS connection parameters
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @params: Connection parameters
- * Returns: 0 on success, -1 on failure,
- * TLS_SET_PARAMS_ENGINE_PRV_INIT_FAILED (-2) on possible PIN error causing
- * PKCS#11 engine failure, or
- * TLS_SET_PARAMS_ENGINE_PRV_VERIFY_FAILED (-3) on failure to verify the
- * PKCS#11 engine private key.
- */
-int __must_check
-tls_connection_set_params(void *tls_ctx, struct tls_connection *conn,
-			  const struct tls_connection_params *params);
-
-/**
- * tls_global_set_params - Set TLS parameters for all TLS connection
- * @tls_ctx: TLS context data from tls_init()
- * @params: Global TLS parameters
- * Returns: 0 on success, -1 on failure,
- * TLS_SET_PARAMS_ENGINE_PRV_INIT_FAILED (-2) on possible PIN error causing
- * PKCS#11 engine failure, or
- * TLS_SET_PARAMS_ENGINE_PRV_VERIFY_FAILED (-3) on failure to verify the
- * PKCS#11 engine private key.
- */
-int __must_check tls_global_set_params(
-	void *tls_ctx, const struct tls_connection_params *params);
-
-/**
- * tls_global_set_verify - Set global certificate verification options
- * @tls_ctx: TLS context data from tls_init()
- * @check_crl: 0 = do not verify CRLs, 1 = verify CRL for the user certificate,
- * 2 = verify CRL for all certificates
- * Returns: 0 on success, -1 on failure
- */
-int __must_check tls_global_set_verify(void *tls_ctx, int check_crl);
-
-/**
- * tls_connection_set_verify - Set certificate verification options
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @verify_peer: 1 = verify peer certificate
- * Returns: 0 on success, -1 on failure
- */
-int __must_check tls_connection_set_verify(void *tls_ctx,
-					   struct tls_connection *conn,
-					   int verify_peer);
-
-/**
- * tls_connection_get_keys - Get master key and random data from TLS connection
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @keys: Structure of key/random data (filled on success)
- * Returns: 0 on success, -1 on failure
- */
-int __must_check tls_connection_get_keys(void *tls_ctx,
-					 struct tls_connection *conn,
-					 struct tls_keys *keys);
-
-/**
- * tls_connection_prf - Use TLS-PRF to derive keying material
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @label: Label (e.g., description of the key) for PRF
- * @server_random_first: seed is 0 = client_random|server_random,
- * 1 = server_random|client_random
- * @out: Buffer for output data from TLS-PRF
- * @out_len: Length of the output buffer
- * Returns: 0 on success, -1 on failure
- *
- * This function is optional to implement if tls_connection_get_keys() provides
- * access to master secret and server/client random values. If these values are
- * not exported from the TLS library, tls_connection_prf() is required so that
- * further keying material can be derived from the master secret. If not
- * implemented, the function will still need to be defined, but it can just
- * return -1. Example implementation of this function is in tls_prf_sha1_md5()
- * when it is called with seed set to client_random|server_random (or
- * server_random|client_random).
- */
-int __must_check  tls_connection_prf(void *tls_ctx,
-				     struct tls_connection *conn,
-				     const char *label,
-				     int server_random_first,
-				     u8 *out, size_t out_len);
-
-/**
- * tls_connection_handshake - Process TLS handshake (client side)
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @in_data: Input data from TLS server
- * @appl_data: Pointer to application data pointer, or %NULL if dropped
- * Returns: Output data, %NULL on failure
- *
- * The caller is responsible for freeing the returned output data. If the final
- * handshake message includes application data, this is decrypted and
- * appl_data (if not %NULL) is set to point this data. The caller is
- * responsible for freeing appl_data.
- *
- * This function is used during TLS handshake. The first call is done with
- * in_data == %NULL and the library is expected to return ClientHello packet.
- * This packet is then send to the server and a response from server is given
- * to TLS library by calling this function again with in_data pointing to the
- * TLS message from the server.
- *
- * If the TLS handshake fails, this function may return %NULL. However, if the
- * TLS library has a TLS alert to send out, that should be returned as the
- * output data. In this case, tls_connection_get_failed() must return failure
- * (> 0).
- *
- * tls_connection_established() should return 1 once the TLS handshake has been
- * completed successfully.
- */
-struct wpabuf * tls_connection_handshake(void *tls_ctx,
-					 struct tls_connection *conn,
-					 const struct wpabuf *in_data,
-					 struct wpabuf **appl_data);
-
-struct wpabuf * tls_connection_handshake2(void *tls_ctx,
-					  struct tls_connection *conn,
-					  const struct wpabuf *in_data,
-					  struct wpabuf **appl_data,
-					  int *more_data_needed);
-
-/**
- * tls_connection_server_handshake - Process TLS handshake (server side)
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @in_data: Input data from TLS peer
- * @appl_data: Pointer to application data pointer, or %NULL if dropped
- * Returns: Output data, %NULL on failure
- *
- * The caller is responsible for freeing the returned output data.
- */
-struct wpabuf * tls_connection_server_handshake(void *tls_ctx,
-						struct tls_connection *conn,
-						const struct wpabuf *in_data,
-						struct wpabuf **appl_data);
-
-/**
- * tls_connection_encrypt - Encrypt data into TLS tunnel
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @in_data: Plaintext data to be encrypted
- * Returns: Encrypted TLS data or %NULL on failure
- *
- * This function is used after TLS handshake has been completed successfully to
- * send data in the encrypted tunnel. The caller is responsible for freeing the
- * returned output data.
- */
-struct wpabuf * tls_connection_encrypt(void *tls_ctx,
-				       struct tls_connection *conn,
-				       const struct wpabuf *in_data);
-
-/**
- * tls_connection_decrypt - Decrypt data from TLS tunnel
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @in_data: Encrypted TLS data
- * Returns: Decrypted TLS data or %NULL on failure
- *
- * This function is used after TLS handshake has been completed successfully to
- * receive data from the encrypted tunnel. The caller is responsible for
- * freeing the returned output data.
- */
-struct wpabuf * tls_connection_decrypt(void *tls_ctx,
-				       struct tls_connection *conn,
-				       const struct wpabuf *in_data);
-
-struct wpabuf * tls_connection_decrypt2(void *tls_ctx,
-					struct tls_connection *conn,
-					const struct wpabuf *in_data,
-					int *more_data_needed);
-
-/**
- * tls_connection_resumed - Was session resumption used
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * Returns: 1 if current session used session resumption, 0 if not
- */
-int tls_connection_resumed(void *tls_ctx, struct tls_connection *conn);
-
-enum {
-	TLS_CIPHER_NONE,
-	TLS_CIPHER_RC4_SHA /* 0x0005 */,
-	TLS_CIPHER_AES128_SHA /* 0x002f */,
-	TLS_CIPHER_RSA_DHE_AES128_SHA /* 0x0031 */,
-	TLS_CIPHER_ANON_DH_AES128_SHA /* 0x0034 */
-};
-
-/**
- * tls_connection_set_cipher_list - Configure acceptable cipher suites
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @ciphers: Zero (TLS_CIPHER_NONE) terminated list of allowed ciphers
- * (TLS_CIPHER_*).
- * Returns: 0 on success, -1 on failure
- */
-int __must_check tls_connection_set_cipher_list(void *tls_ctx,
-						struct tls_connection *conn,
-						u8 *ciphers);
-
-/**
- * tls_get_cipher - Get current cipher name
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @buf: Buffer for the cipher name
- * @buflen: buf size
- * Returns: 0 on success, -1 on failure
- *
- * Get the name of the currently used cipher.
- */
-int __must_check tls_get_cipher(void *tls_ctx, struct tls_connection *conn,
-				char *buf, size_t buflen);
-
-/**
- * tls_connection_enable_workaround - Enable TLS workaround options
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * Returns: 0 on success, -1 on failure
- *
- * This function is used to enable connection-specific workaround options for
- * buffer SSL/TLS implementations.
- */
-int __must_check tls_connection_enable_workaround(void *tls_ctx,
-						  struct tls_connection *conn);
-
-/**
- * tls_connection_client_hello_ext - Set TLS extension for ClientHello
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * @ext_type: Extension type
- * @data: Extension payload (%NULL to remove extension)
- * @data_len: Extension payload length
- * Returns: 0 on success, -1 on failure
- */
-int __must_check tls_connection_client_hello_ext(void *tls_ctx,
-						 struct tls_connection *conn,
-						 int ext_type, const u8 *data,
-						 size_t data_len);
-
-/**
- * tls_connection_get_failed - Get connection failure status
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- *
- * Returns >0 if connection has failed, 0 if not.
- */
-int tls_connection_get_failed(void *tls_ctx, struct tls_connection *conn);
-
-/**
- * tls_connection_get_read_alerts - Get connection read alert status
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * Returns: Number of times a fatal read (remote end reported error) has
- * happened during this connection.
- */
-int tls_connection_get_read_alerts(void *tls_ctx, struct tls_connection *conn);
-
-/**
- * tls_connection_get_write_alerts - Get connection write alert status
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * Returns: Number of times a fatal write (locally detected error) has happened
- * during this connection.
- */
-int tls_connection_get_write_alerts(void *tls_ctx,
-				    struct tls_connection *conn);
-
-/**
- * tls_connection_get_keyblock_size - Get TLS key_block size
- * @tls_ctx: TLS context data from tls_init()
- * @conn: Connection context data from tls_connection_init()
- * Returns: Size of the key_block for the negotiated cipher suite or -1 on
- * failure
- */
-int tls_connection_get_keyblock_size(void *tls_ctx,
-				     struct tls_connection *conn);
-
-/**
- * tls_capabilities - Get supported TLS capabilities
- * @tls_ctx: TLS context data from tls_init()
- * Returns: Bit field of supported TLS capabilities (TLS_CAPABILITY_*)
- */
-unsigned int tls_capabilities(void *tls_ctx);
-
-typedef int (*tls_session_ticket_cb)
-(void *ctx, const u8 *ticket, size_t len, const u8 *client_random,
- const u8 *server_random, u8 *master_secret);
-
-int __must_check  tls_connection_set_session_ticket_cb(
-	void *tls_ctx, struct tls_connection *conn,
-	tls_session_ticket_cb cb, void *ctx);
-
-int tls_prf_sha1_md5(const u8 *secret, size_t secret_len, const char *label,
-             const u8 *seed, size_t seed_len, u8 *out, size_t outlen);
-
-#endif /* TLS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_client.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_client.h
deleted file mode 100644
index 8ec85f1a919..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_client.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * TLS v1.0/v1.1/v1.2 client (RFC 2246, RFC 4346, RFC 5246)
- * Copyright (c) 2006-2011, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef TLSV1_CLIENT_H
-#define TLSV1_CLIENT_H
-
-#include "tlsv1_cred.h"
-
-struct tlsv1_client;
-
-int tlsv1_client_global_init(void);
-void tlsv1_client_global_deinit(void);
-struct tlsv1_client * tlsv1_client_init(void);
-void tlsv1_client_deinit(struct tlsv1_client *conn);
-int tlsv1_client_established(struct tlsv1_client *conn);
-int tlsv1_client_prf(struct tlsv1_client *conn, const char *label,
-		     int server_random_first, u8 *out, size_t out_len);
-u8 * tlsv1_client_handshake(struct tlsv1_client *conn,
-			    const u8 *in_data, size_t in_len,
-			    size_t *out_len, u8 **appl_data,
-			    size_t *appl_data_len, int *need_more_data);
-int tlsv1_client_encrypt(struct tlsv1_client *conn,
-			 const u8 *in_data, size_t in_len,
-			 u8 *out_data, size_t out_len);
-struct wpabuf * tlsv1_client_decrypt(struct tlsv1_client *conn,
-				     const u8 *in_data, size_t in_len,
-				     int *need_more_data);
-int tlsv1_client_get_cipher(struct tlsv1_client *conn, char *buf,
-			    size_t buflen);
-int tlsv1_client_shutdown(struct tlsv1_client *conn);
-int tlsv1_client_resumed(struct tlsv1_client *conn);
-int tlsv1_client_hello_ext(struct tlsv1_client *conn, int ext_type,
-			   const u8 *data, size_t data_len);
-int tlsv1_client_get_keys(struct tlsv1_client *conn, struct tls_keys *keys);
-int tlsv1_client_get_keyblock_size(struct tlsv1_client *conn);
-int tlsv1_client_set_cipher_list(struct tlsv1_client *conn, u8 *ciphers);
-int tlsv1_client_set_cred(struct tlsv1_client *conn,
-			  struct tlsv1_credentials *cred);
-void tlsv1_client_set_time_checks(struct tlsv1_client *conn, int enabled);
-
-typedef int (*tlsv1_client_session_ticket_cb)
-(void *ctx, const u8 *ticket, size_t len, const u8 *client_random,
- const u8 *server_random, u8 *master_secret);
-
-void tlsv1_client_set_session_ticket_cb(struct tlsv1_client *conn,
-					tlsv1_client_session_ticket_cb cb,
-					void *ctx);
-
-#endif /* TLSV1_CLIENT_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_client_i.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_client_i.h
deleted file mode 100644
index 55fdcf8d043..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_client_i.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * TLSv1 client - internal structures
- * Copyright (c) 2006-2011, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef TLSV1_CLIENT_I_H
-#define TLSV1_CLIENT_I_H
-
-struct tlsv1_client {
-	enum {
-		CLIENT_HELLO, SERVER_HELLO, SERVER_CERTIFICATE,
-		SERVER_KEY_EXCHANGE, SERVER_CERTIFICATE_REQUEST,
-		SERVER_HELLO_DONE, CLIENT_KEY_EXCHANGE, CHANGE_CIPHER_SPEC,
-		SERVER_CHANGE_CIPHER_SPEC, SERVER_FINISHED, ACK_FINISHED,
-		ESTABLISHED, FAILED
-	} state;
-
-	struct tlsv1_record_layer rl;
-
-	u8 session_id[TLS_SESSION_ID_MAX_LEN];
-	size_t session_id_len;
-	u8 client_random[TLS_RANDOM_LEN];
-	u8 server_random[TLS_RANDOM_LEN];
-	u8 master_secret[TLS_MASTER_SECRET_LEN];
-
-	u8 alert_level;
-	u8 alert_description;
-
-	unsigned int certificate_requested:1;
-	unsigned int session_resumed:1;
-	unsigned int session_ticket_included:1;
-	unsigned int use_session_ticket:1;
-	unsigned int disable_time_checks:1;
-
-	struct crypto_public_key *server_rsa_key;
-
-	struct tls_verify_hash verify;
-
-#define MAX_CIPHER_COUNT 30
-	u16 cipher_suites[MAX_CIPHER_COUNT];
-	size_t num_cipher_suites;
-
-	u16 prev_cipher_suite;
-
-	u8 *client_hello_ext;
-	size_t client_hello_ext_len;
-
-	/* The prime modulus used for Diffie-Hellman */
-	u8 *dh_p;
-	size_t dh_p_len;
-	/* The generator used for Diffie-Hellman */
-	u8 *dh_g;
-	size_t dh_g_len;
-	/* The server's Diffie-Hellman public value */
-	u8 *dh_ys;
-	size_t dh_ys_len;
-
-	struct tlsv1_credentials *cred;
-
-	tlsv1_client_session_ticket_cb session_ticket_cb;
-	void *session_ticket_cb_ctx;
-
-	struct wpabuf *partial_input;
-};
-
-
-void tls_alert(struct tlsv1_client *conn, u8 level, u8 description);
-void tlsv1_client_free_dh(struct tlsv1_client *conn);
-int tls_derive_pre_master_secret(u8 *pre_master_secret);
-int tls_derive_keys(struct tlsv1_client *conn,
-		    const u8 *pre_master_secret, size_t pre_master_secret_len);
-u8 * tls_send_client_hello(struct tlsv1_client *conn, size_t *out_len);
-u8 * tlsv1_client_send_alert(struct tlsv1_client *conn, u8 level,
-			     u8 description, size_t *out_len);
-u8 * tlsv1_client_handshake_write(struct tlsv1_client *conn, size_t *out_len,
-				  int no_appl_data);
-int tlsv1_client_process_handshake(struct tlsv1_client *conn, u8 ct,
-				   const u8 *buf, size_t *len,
-				   u8 **out_data, size_t *out_len);
-
-#endif /* TLSV1_CLIENT_I_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_common.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_common.h
deleted file mode 100644
index f28c0cdc479..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_common.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * TLSv1 common definitions
- * Copyright (c) 2006-2011, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef TLSV1_COMMON_H
-#define TLSV1_COMMON_H
-
-#include "crypto/crypto.h"
-
-#define TLS_VERSION_1 0x0301 /* TLSv1 */
-#define TLS_VERSION_1_1 0x0302 /* TLSv1.1 */
-#define TLS_VERSION_1_2 0x0303 /* TLSv1.2 */
-#ifdef CONFIG_TLSV12
-#define TLS_VERSION TLS_VERSION_1_2
-#else /* CONFIG_TLSV12 */
-#ifdef CONFIG_TLSV11
-#define TLS_VERSION TLS_VERSION_1_1
-#else /* CONFIG_TLSV11 */
-#define TLS_VERSION TLS_VERSION_1
-#endif /* CONFIG_TLSV11 */
-#endif /* CONFIG_TLSV12 */
-#define TLS_RANDOM_LEN 32
-#define TLS_PRE_MASTER_SECRET_LEN 48
-#define TLS_MASTER_SECRET_LEN 48
-#define TLS_SESSION_ID_MAX_LEN 32
-#define TLS_VERIFY_DATA_LEN 12
-
-/* HandshakeType */
-enum {
-	TLS_HANDSHAKE_TYPE_HELLO_REQUEST = 0,
-	TLS_HANDSHAKE_TYPE_CLIENT_HELLO = 1,
-	TLS_HANDSHAKE_TYPE_SERVER_HELLO = 2,
-	TLS_HANDSHAKE_TYPE_NEW_SESSION_TICKET = 4 /* RFC 4507 */,
-	TLS_HANDSHAKE_TYPE_CERTIFICATE = 11,
-	TLS_HANDSHAKE_TYPE_SERVER_KEY_EXCHANGE = 12,
-	TLS_HANDSHAKE_TYPE_CERTIFICATE_REQUEST = 13,
-	TLS_HANDSHAKE_TYPE_SERVER_HELLO_DONE = 14,
-	TLS_HANDSHAKE_TYPE_CERTIFICATE_VERIFY = 15,
-	TLS_HANDSHAKE_TYPE_CLIENT_KEY_EXCHANGE = 16,
-	TLS_HANDSHAKE_TYPE_FINISHED = 20,
-	TLS_HANDSHAKE_TYPE_CERTIFICATE_URL = 21 /* RFC 4366 */,
-	TLS_HANDSHAKE_TYPE_CERTIFICATE_STATUS = 22 /* RFC 4366 */
-};
-
-/* CipherSuite */
-#define TLS_NULL_WITH_NULL_NULL			0x0000 /* RFC 2246 */
-#define TLS_RSA_WITH_NULL_MD5			0x0001 /* RFC 2246 */
-#define TLS_RSA_WITH_NULL_SHA			0x0002 /* RFC 2246 */
-#define TLS_RSA_EXPORT_WITH_RC4_40_MD5		0x0003 /* RFC 2246 */
-#define TLS_RSA_WITH_RC4_128_MD5		0x0004 /* RFC 2246 */
-#define TLS_RSA_WITH_RC4_128_SHA		0x0005 /* RFC 2246 */
-#define TLS_RSA_EXPORT_WITH_RC2_CBC_40_MD5	0x0006 /* RFC 2246 */
-#define TLS_RSA_WITH_IDEA_CBC_SHA		0x0007 /* RFC 2246 */
-#define TLS_RSA_EXPORT_WITH_DES40_CBC_SHA	0x0008 /* RFC 2246 */
-#define TLS_RSA_WITH_DES_CBC_SHA		0x0009 /* RFC 2246 */
-#define TLS_RSA_WITH_3DES_EDE_CBC_SHA		0x000A /* RFC 2246 */
-#define TLS_DH_DSS_EXPORT_WITH_DES40_CBC_SHA	0x000B /* RFC 2246 */
-#define TLS_DH_DSS_WITH_DES_CBC_SHA		0x000C /* RFC 2246 */
-#define TLS_DH_DSS_WITH_3DES_EDE_CBC_SHA	0x000D /* RFC 2246 */
-#define TLS_DH_RSA_EXPORT_WITH_DES40_CBC_SHA	0x000E /* RFC 2246 */
-#define TLS_DH_RSA_WITH_DES_CBC_SHA		0x000F /* RFC 2246 */
-#define TLS_DH_RSA_WITH_3DES_EDE_CBC_SHA	0x0010 /* RFC 2246 */
-#define TLS_DHE_DSS_EXPORT_WITH_DES40_CBC_SHA	0x0011 /* RFC 2246 */
-#define TLS_DHE_DSS_WITH_DES_CBC_SHA		0x0012 /* RFC 2246 */
-#define TLS_DHE_DSS_WITH_3DES_EDE_CBC_SHA	0x0013 /* RFC 2246 */
-#define TLS_DHE_RSA_EXPORT_WITH_DES40_CBC_SHA	0x0014 /* RFC 2246 */
-#define TLS_DHE_RSA_WITH_DES_CBC_SHA		0x0015 /* RFC 2246 */
-#define TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA	0x0016 /* RFC 2246 */
-#define TLS_DH_anon_EXPORT_WITH_RC4_40_MD5	0x0017 /* RFC 2246 */
-#define TLS_DH_anon_WITH_RC4_128_MD5		0x0018 /* RFC 2246 */
-#define TLS_DH_anon_EXPORT_WITH_DES40_CBC_SHA	0x0019 /* RFC 2246 */
-#define TLS_DH_anon_WITH_DES_CBC_SHA		0x001A /* RFC 2246 */
-#define TLS_DH_anon_WITH_3DES_EDE_CBC_SHA	0x001B /* RFC 2246 */
-#define TLS_RSA_WITH_AES_128_CBC_SHA		0x002F /* RFC 3268 */
-#define TLS_DH_DSS_WITH_AES_128_CBC_SHA		0x0030 /* RFC 3268 */
-#define TLS_DH_RSA_WITH_AES_128_CBC_SHA		0x0031 /* RFC 3268 */
-#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA	0x0032 /* RFC 3268 */
-#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA	0x0033 /* RFC 3268 */
-#define TLS_DH_anon_WITH_AES_128_CBC_SHA	0x0034 /* RFC 3268 */
-#define TLS_RSA_WITH_AES_256_CBC_SHA		0x0035 /* RFC 3268 */
-#define TLS_DH_DSS_WITH_AES_256_CBC_SHA		0x0036 /* RFC 3268 */
-#define TLS_DH_RSA_WITH_AES_256_CBC_SHA		0x0037 /* RFC 3268 */
-#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA	0x0038 /* RFC 3268 */
-#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA	0x0039 /* RFC 3268 */
-#define TLS_DH_anon_WITH_AES_256_CBC_SHA	0x003A /* RFC 3268 */
-#define TLS_RSA_WITH_NULL_SHA256		0x003B /* RFC 5246 */
-#define TLS_RSA_WITH_AES_128_CBC_SHA256		0x003C /* RFC 5246 */
-#define TLS_RSA_WITH_AES_256_CBC_SHA256		0x003D /* RFC 5246 */
-#define TLS_DH_DSS_WITH_AES_128_CBC_SHA256	0x003E /* RFC 5246 */
-#define TLS_DH_RSA_WITH_AES_128_CBC_SHA256	0x003F /* RFC 5246 */
-#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA256	0x0040 /* RFC 5246 */
-#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA256	0x0067 /* RFC 5246 */
-#define TLS_DH_DSS_WITH_AES_256_CBC_SHA256	0x0068 /* RFC 5246 */
-#define TLS_DH_RSA_WITH_AES_256_CBC_SHA256	0x0069 /* RFC 5246 */
-#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA256	0x006A /* RFC 5246 */
-#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA256	0x006B /* RFC 5246 */
-#define TLS_DH_anon_WITH_AES_128_CBC_SHA256	0x006C /* RFC 5246 */
-#define TLS_DH_anon_WITH_AES_256_CBC_SHA256	0x006D /* RFC 5246 */
-
-/* CompressionMethod */
-#define TLS_COMPRESSION_NULL 0
-
-/* HashAlgorithm */
-enum {
-	TLS_HASH_ALG_NONE = 0,
-	TLS_HASH_ALG_MD5 = 1,
-	TLS_HASH_ALG_SHA1 = 2,
-	TLS_HASH_ALG_SHA224 = 3,
-	TLS_HASH_ALG_SHA256 = 4,
-	TLS_HASH_ALG_SHA384 = 5,
-	TLS_HASH_ALG_SHA512 = 6
-};
-
-/* SignatureAlgorithm */
-enum {
-	TLS_SIGN_ALG_ANONYMOUS = 0,
-	TLS_SIGN_ALG_RSA = 1,
-	TLS_SIGN_ALG_DSA = 2,
-	TLS_SIGN_ALG_ECDSA = 3,
-};
-
-/* AlertLevel */
-#define TLS_ALERT_LEVEL_WARNING 1
-#define TLS_ALERT_LEVEL_FATAL 2
-
-/* AlertDescription */
-#define TLS_ALERT_CLOSE_NOTIFY			0
-#define TLS_ALERT_UNEXPECTED_MESSAGE		10
-#define TLS_ALERT_BAD_RECORD_MAC		20
-#define TLS_ALERT_DECRYPTION_FAILED		21
-#define TLS_ALERT_RECORD_OVERFLOW		22
-#define TLS_ALERT_DECOMPRESSION_FAILURE		30
-#define TLS_ALERT_HANDSHAKE_FAILURE		40
-#define TLS_ALERT_BAD_CERTIFICATE		42
-#define TLS_ALERT_UNSUPPORTED_CERTIFICATE	43
-#define TLS_ALERT_CERTIFICATE_REVOKED		44
-#define TLS_ALERT_CERTIFICATE_EXPIRED		45
-#define TLS_ALERT_CERTIFICATE_UNKNOWN		46
-#define TLS_ALERT_ILLEGAL_PARAMETER		47
-#define TLS_ALERT_UNKNOWN_CA			48
-#define TLS_ALERT_ACCESS_DENIED			49
-#define TLS_ALERT_DECODE_ERROR			50
-#define TLS_ALERT_DECRYPT_ERROR			51
-#define TLS_ALERT_EXPORT_RESTRICTION		60
-#define TLS_ALERT_PROTOCOL_VERSION		70
-#define TLS_ALERT_INSUFFICIENT_SECURITY		71
-#define TLS_ALERT_INTERNAL_ERROR		80
-#define TLS_ALERT_USER_CANCELED			90
-#define TLS_ALERT_NO_RENEGOTIATION		100
-#define TLS_ALERT_UNSUPPORTED_EXTENSION		110 /* RFC 4366 */
-#define TLS_ALERT_CERTIFICATE_UNOBTAINABLE	111 /* RFC 4366 */
-#define TLS_ALERT_UNRECOGNIZED_NAME		112 /* RFC 4366 */
-#define TLS_ALERT_BAD_CERTIFICATE_STATUS_RESPONSE	113 /* RFC 4366 */
-#define TLS_ALERT_BAD_CERTIFICATE_HASH_VALUE	114 /* RFC 4366 */
-
-/* ChangeCipherSpec */
-enum {
-	TLS_CHANGE_CIPHER_SPEC = 1
-};
-
-/* TLS Extensions */
-#define TLS_EXT_SERVER_NAME			0 /* RFC 4366 */
-#define TLS_EXT_MAX_FRAGMENT_LENGTH		1 /* RFC 4366 */
-#define TLS_EXT_CLIENT_CERTIFICATE_URL		2 /* RFC 4366 */
-#define TLS_EXT_TRUSTED_CA_KEYS			3 /* RFC 4366 */
-#define TLS_EXT_TRUNCATED_HMAC			4 /* RFC 4366 */
-#define TLS_EXT_STATUS_REQUEST			5 /* RFC 4366 */
-#define TLS_EXT_SESSION_TICKET			35 /* RFC 4507 */
-
-#define TLS_EXT_PAC_OPAQUE TLS_EXT_SESSION_TICKET /* EAP-FAST terminology */
-
-
-typedef enum {
-	TLS_KEY_X_NULL,
-	TLS_KEY_X_RSA,
-	TLS_KEY_X_RSA_EXPORT,
-	TLS_KEY_X_DH_DSS_EXPORT,
-	TLS_KEY_X_DH_DSS,
-	TLS_KEY_X_DH_RSA_EXPORT,
-	TLS_KEY_X_DH_RSA,
-	TLS_KEY_X_DHE_DSS_EXPORT,
-	TLS_KEY_X_DHE_DSS,
-	TLS_KEY_X_DHE_RSA_EXPORT,
-	TLS_KEY_X_DHE_RSA,
-	TLS_KEY_X_DH_anon_EXPORT,
-	TLS_KEY_X_DH_anon
-} tls_key_exchange;
-
-typedef enum {
-	TLS_CIPHER_NULL,
-	TLS_CIPHER_RC4_40,
-	TLS_CIPHER_RC4_128,
-	TLS_CIPHER_RC2_CBC_40,
-	TLS_CIPHER_IDEA_CBC,
-	TLS_CIPHER_DES40_CBC,
-	TLS_CIPHER_DES_CBC,
-	TLS_CIPHER_3DES_EDE_CBC,
-	TLS_CIPHER_AES_128_CBC,
-	TLS_CIPHER_AES_256_CBC
-} tls_cipher;
-
-typedef enum {
-	TLS_HASH_NULL,
-	TLS_HASH_MD5,
-	TLS_HASH_SHA,
-	TLS_HASH_SHA256
-} tls_hash;
-
-struct tls_cipher_suite {
-	u16 suite;
-	tls_key_exchange key_exchange;
-	tls_cipher cipher;
-	tls_hash hash;
-};
-
-typedef enum {
-	TLS_CIPHER_STREAM,
-	TLS_CIPHER_BLOCK
-} tls_cipher_type;
-
-struct tls_cipher_data {
-	tls_cipher cipher;
-	tls_cipher_type type;
-	size_t key_material;
-	size_t expanded_key_material;
-	size_t block_size; /* also iv_size */
-	enum crypto_cipher_alg alg;
-};
-
-
-struct tls_verify_hash {
-	struct crypto_hash *md5_client;
-	struct crypto_hash *sha1_client;
-	struct crypto_hash *sha256_client;
-	struct crypto_hash *md5_server;
-	struct crypto_hash *sha1_server;
-	struct crypto_hash *sha256_server;
-	struct crypto_hash *md5_cert;
-	struct crypto_hash *sha1_cert;
-	struct crypto_hash *sha256_cert;
-};
-
-
-const struct tls_cipher_suite * tls_get_cipher_suite(u16 suite);
-const struct tls_cipher_data * tls_get_cipher_data(tls_cipher cipher);
-int tls_server_key_exchange_allowed(tls_cipher cipher);
-int tls_parse_cert(const u8 *buf, size_t len, struct crypto_public_key **pk);
-int tls_verify_hash_init(struct tls_verify_hash *verify);
-void tls_verify_hash_add(struct tls_verify_hash *verify, const u8 *buf,
-			 size_t len);
-void tls_verify_hash_free(struct tls_verify_hash *verify);
-int tls_version_ok(u16 ver);
-const char * tls_version_str(u16 ver);
-int tls_prf(u16 ver, const u8 *secret, size_t secret_len, const char *label,
-	    const u8 *seed, size_t seed_len, u8 *out, size_t outlen);
-
-#endif /* TLSV1_COMMON_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_cred.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_cred.h
deleted file mode 100644
index 68fbdc92300..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_cred.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * TLSv1 credentials
- * Copyright (c) 2006-2007, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef TLSV1_CRED_H
-#define TLSV1_CRED_H
-
-struct tlsv1_credentials {
-	struct x509_certificate *trusted_certs;
-	struct x509_certificate *cert;
-	struct crypto_private_key *key;
-
-	/* Diffie-Hellman parameters */
-	u8 *dh_p; /* prime */
-	size_t dh_p_len;
-	u8 *dh_g; /* generator */
-	size_t dh_g_len;
-};
-
-
-struct tlsv1_credentials * tlsv1_cred_alloc(void);
-void tlsv1_cred_free(struct tlsv1_credentials *cred);
-int tlsv1_set_ca_cert(struct tlsv1_credentials *cred, const char *cert,
-		      const u8 *cert_blob, size_t cert_blob_len,
-		      const char *path);
-int tlsv1_set_cert(struct tlsv1_credentials *cred, const char *cert,
-		   const u8 *cert_blob, size_t cert_blob_len);
-int tlsv1_set_private_key(struct tlsv1_credentials *cred,
-			  const char *private_key,
-			  const char *private_key_passwd,
-			  const u8 *private_key_blob,
-			  size_t private_key_blob_len);
-int tlsv1_set_dhparams(struct tlsv1_credentials *cred, const char *dh_file,
-		       const u8 *dh_blob, size_t dh_blob_len);
-
-#endif /* TLSV1_CRED_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_record.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_record.h
deleted file mode 100644
index 48abcb0d25c..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_record.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * TLSv1 Record Protocol
- * Copyright (c) 2006-2011, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef TLSV1_RECORD_H
-#define TLSV1_RECORD_H
-
-#include "crypto/crypto.h"
-
-#define TLS_MAX_WRITE_MAC_SECRET_LEN 32
-#define TLS_MAX_WRITE_KEY_LEN 32
-#define TLS_MAX_IV_LEN 16
-#define TLS_MAX_KEY_BLOCK_LEN (2 * (TLS_MAX_WRITE_MAC_SECRET_LEN + \
-				    TLS_MAX_WRITE_KEY_LEN + TLS_MAX_IV_LEN))
-
-#define TLS_SEQ_NUM_LEN 8
-#define TLS_RECORD_HEADER_LEN 5
-
-/* ContentType */
-enum {
-	TLS_CONTENT_TYPE_CHANGE_CIPHER_SPEC = 20,
-	TLS_CONTENT_TYPE_ALERT = 21,
-	TLS_CONTENT_TYPE_HANDSHAKE = 22,
-	TLS_CONTENT_TYPE_APPLICATION_DATA = 23
-};
-
-struct tlsv1_record_layer {
-	u16 tls_version;
-
-	u8 write_mac_secret[TLS_MAX_WRITE_MAC_SECRET_LEN];
-	u8 read_mac_secret[TLS_MAX_WRITE_MAC_SECRET_LEN];
-	u8 write_key[TLS_MAX_WRITE_KEY_LEN];
-	u8 read_key[TLS_MAX_WRITE_KEY_LEN];
-	u8 write_iv[TLS_MAX_IV_LEN];
-	u8 read_iv[TLS_MAX_IV_LEN];
-
-	size_t hash_size;
-	size_t key_material_len;
-	size_t iv_size; /* also block_size */
-
-	enum crypto_hash_alg hash_alg;
-	enum crypto_cipher_alg cipher_alg;
-
-	u8 write_seq_num[TLS_SEQ_NUM_LEN];
-	u8 read_seq_num[TLS_SEQ_NUM_LEN];
-
-	u16 cipher_suite;
-	u16 write_cipher_suite;
-	u16 read_cipher_suite;
-
-	struct crypto_cipher *write_cbc;
-	struct crypto_cipher *read_cbc;
-};
-
-
-int tlsv1_record_set_cipher_suite(struct tlsv1_record_layer *rl,
-				  u16 cipher_suite);
-int tlsv1_record_change_write_cipher(struct tlsv1_record_layer *rl);
-int tlsv1_record_change_read_cipher(struct tlsv1_record_layer *rl);
-int tlsv1_record_send(struct tlsv1_record_layer *rl, u8 content_type, u8 *buf,
-		      size_t buf_size, const u8 *payload, size_t payload_len,
-		      size_t *out_len);
-int tlsv1_record_receive(struct tlsv1_record_layer *rl,
-			 const u8 *in_data, size_t in_len,
-			 u8 *out_data, size_t *out_len, u8 *alert);
-
-#endif /* TLSV1_RECORD_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_server.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_server.h
deleted file mode 100644
index a18c69e37c1..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_server.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * TLS v1.0/v1.1/v1.2 server (RFC 2246, RFC 4346, RFC 5246)
- * Copyright (c) 2006-2011, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef TLSV1_SERVER_H
-#define TLSV1_SERVER_H
-
-#include "tlsv1_cred.h"
-
-struct tlsv1_server;
-
-int tlsv1_server_global_init(void);
-void tlsv1_server_global_deinit(void);
-struct tlsv1_server * tlsv1_server_init(struct tlsv1_credentials *cred);
-void tlsv1_server_deinit(struct tlsv1_server *conn);
-int tlsv1_server_established(struct tlsv1_server *conn);
-int tlsv1_server_prf(struct tlsv1_server *conn, const char *label,
-		     int server_random_first, u8 *out, size_t out_len);
-u8 * tlsv1_server_handshake(struct tlsv1_server *conn,
-			    const u8 *in_data, size_t in_len, size_t *out_len);
-int tlsv1_server_encrypt(struct tlsv1_server *conn,
-			 const u8 *in_data, size_t in_len,
-			 u8 *out_data, size_t out_len);
-int tlsv1_server_decrypt(struct tlsv1_server *conn,
-			 const u8 *in_data, size_t in_len,
-			 u8 *out_data, size_t out_len);
-int tlsv1_server_get_cipher(struct tlsv1_server *conn, char *buf,
-			    size_t buflen);
-int tlsv1_server_shutdown(struct tlsv1_server *conn);
-int tlsv1_server_resumed(struct tlsv1_server *conn);
-int tlsv1_server_get_keys(struct tlsv1_server *conn, struct tls_keys *keys);
-int tlsv1_server_get_keyblock_size(struct tlsv1_server *conn);
-int tlsv1_server_set_cipher_list(struct tlsv1_server *conn, u8 *ciphers);
-int tlsv1_server_set_verify(struct tlsv1_server *conn, int verify_peer);
-
-typedef int (*tlsv1_server_session_ticket_cb)
-(void *ctx, const u8 *ticket, size_t len, const u8 *client_random,
- const u8 *server_random, u8 *master_secret);
-
-void tlsv1_server_set_session_ticket_cb(struct tlsv1_server *conn,
-					tlsv1_server_session_ticket_cb cb,
-					void *ctx);
-
-#endif /* TLSV1_SERVER_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_server_i.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_server_i.h
deleted file mode 100644
index 1f61533a5aa..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/tlsv1_server_i.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * TLSv1 server - internal structures
- * Copyright (c) 2006-2007, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef TLSV1_SERVER_I_H
-#define TLSV1_SERVER_I_H
-
-struct tlsv1_server {
-	enum {
-		CLIENT_HELLO, SERVER_HELLO, SERVER_CERTIFICATE,
-		SERVER_KEY_EXCHANGE, SERVER_CERTIFICATE_REQUEST,
-		SERVER_HELLO_DONE, CLIENT_CERTIFICATE, CLIENT_KEY_EXCHANGE,
-		CERTIFICATE_VERIFY, CHANGE_CIPHER_SPEC, CLIENT_FINISHED,
-		SERVER_CHANGE_CIPHER_SPEC, SERVER_FINISHED,
-		ESTABLISHED, FAILED
-	} state;
-
-	struct tlsv1_record_layer rl;
-
-	u8 session_id[TLS_SESSION_ID_MAX_LEN];
-	size_t session_id_len;
-	u8 client_random[TLS_RANDOM_LEN];
-	u8 server_random[TLS_RANDOM_LEN];
-	u8 master_secret[TLS_MASTER_SECRET_LEN];
-
-	u8 alert_level;
-	u8 alert_description;
-
-	struct crypto_public_key *client_rsa_key;
-
-	struct tls_verify_hash verify;
-
-#define MAX_CIPHER_COUNT 30
-	u16 cipher_suites[MAX_CIPHER_COUNT];
-	size_t num_cipher_suites;
-
-	u16 cipher_suite;
-
-	struct tlsv1_credentials *cred;
-
-	int verify_peer;
-	u16 client_version;
-
-	u8 *session_ticket;
-	size_t session_ticket_len;
-
-	tlsv1_server_session_ticket_cb session_ticket_cb;
-	void *session_ticket_cb_ctx;
-
-	int use_session_ticket;
-
-	u8 *dh_secret;
-	size_t dh_secret_len;
-};
-
-
-void tlsv1_server_alert(struct tlsv1_server *conn, u8 level, u8 description);
-int tlsv1_server_derive_keys(struct tlsv1_server *conn,
-			     const u8 *pre_master_secret,
-			     size_t pre_master_secret_len);
-u8 * tlsv1_server_handshake_write(struct tlsv1_server *conn, size_t *out_len);
-u8 * tlsv1_server_send_alert(struct tlsv1_server *conn, u8 level,
-			     u8 description, size_t *out_len);
-int tlsv1_server_process_handshake(struct tlsv1_server *conn, u8 ct,
-				   const u8 *buf, size_t *len);
-
-#endif /* TLSV1_SERVER_I_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/tls/x509v3.h b/tools/sdk/include/wpa_supplicant/wpa2/tls/x509v3.h
deleted file mode 100644
index 91a35baf92b..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/tls/x509v3.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * X.509v3 certificate parsing and processing
- * Copyright (c) 2006-2011, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef X509V3_H
-#define X509V3_H
-
-#include "asn1.h"
-
-struct x509_algorithm_identifier {
-	struct asn1_oid oid;
-};
-
-struct x509_name_attr {
-	enum x509_name_attr_type {
-		X509_NAME_ATTR_NOT_USED,
-		X509_NAME_ATTR_DC,
-		X509_NAME_ATTR_CN,
-		X509_NAME_ATTR_C,
-		X509_NAME_ATTR_L,
-		X509_NAME_ATTR_ST,
-		X509_NAME_ATTR_O,
-		X509_NAME_ATTR_OU
-	} type;
-	char *value;
-};
-
-#define X509_MAX_NAME_ATTRIBUTES 20
-
-struct x509_name {
-	struct x509_name_attr attr[X509_MAX_NAME_ATTRIBUTES];
-	size_t num_attr;
-	char *email; /* emailAddress */
-
-	/* from alternative name extension */
-	char *alt_email; /* rfc822Name */
-	char *dns; /* dNSName */
-	char *uri; /* uniformResourceIdentifier */
-	u8 *ip; /* iPAddress */
-	size_t ip_len; /* IPv4: 4, IPv6: 16 */
-	struct asn1_oid rid; /* registeredID */
-};
-
-struct x509_certificate {
-	struct x509_certificate *next;
-	enum { X509_CERT_V1 = 0, X509_CERT_V2 = 1, X509_CERT_V3 = 2 } version;
-	unsigned long serial_number;
-	struct x509_algorithm_identifier signature;
-	struct x509_name issuer;
-	struct x509_name subject;
-	os_time_t not_before;
-	os_time_t not_after;
-	struct x509_algorithm_identifier public_key_alg;
-	u8 *public_key;
-	size_t public_key_len;
-	struct x509_algorithm_identifier signature_alg;
-	u8 *sign_value;
-	size_t sign_value_len;
-
-	/* Extensions */
-	unsigned int extensions_present;
-#define X509_EXT_BASIC_CONSTRAINTS		(1 << 0)
-#define X509_EXT_PATH_LEN_CONSTRAINT		(1 << 1)
-#define X509_EXT_KEY_USAGE			(1 << 2)
-#define X509_EXT_SUBJECT_ALT_NAME		(1 << 3)
-#define X509_EXT_ISSUER_ALT_NAME		(1 << 4)
-
-	/* BasicConstraints */
-	int ca; /* cA */
-	unsigned long path_len_constraint; /* pathLenConstraint */
-
-	/* KeyUsage */
-	unsigned long key_usage;
-#define X509_KEY_USAGE_DIGITAL_SIGNATURE	(1 << 0)
-#define X509_KEY_USAGE_NON_REPUDIATION		(1 << 1)
-#define X509_KEY_USAGE_KEY_ENCIPHERMENT		(1 << 2)
-#define X509_KEY_USAGE_DATA_ENCIPHERMENT	(1 << 3)
-#define X509_KEY_USAGE_KEY_AGREEMENT		(1 << 4)
-#define X509_KEY_USAGE_KEY_CERT_SIGN		(1 << 5)
-#define X509_KEY_USAGE_CRL_SIGN			(1 << 6)
-#define X509_KEY_USAGE_ENCIPHER_ONLY		(1 << 7)
-#define X509_KEY_USAGE_DECIPHER_ONLY		(1 << 8)
-
-	/*
-	 * The DER format certificate follows struct x509_certificate. These
-	 * pointers point to that buffer.
-	 */
-	const u8 *cert_start;
-	size_t cert_len;
-	const u8 *tbs_cert_start;
-	size_t tbs_cert_len;
-};
-
-enum {
-	X509_VALIDATE_OK,
-	X509_VALIDATE_BAD_CERTIFICATE,
-	X509_VALIDATE_UNSUPPORTED_CERTIFICATE,
-	X509_VALIDATE_CERTIFICATE_REVOKED,
-	X509_VALIDATE_CERTIFICATE_EXPIRED,
-	X509_VALIDATE_CERTIFICATE_UNKNOWN,
-	X509_VALIDATE_UNKNOWN_CA
-};
-
-void x509_certificate_free(struct x509_certificate *cert);
-struct x509_certificate * x509_certificate_parse(const u8 *buf, size_t len);
-void x509_name_string(struct x509_name *name, char *buf, size_t len);
-int x509_name_compare(struct x509_name *a, struct x509_name *b);
-void x509_certificate_chain_free(struct x509_certificate *cert);
-int x509_certificate_check_signature(struct x509_certificate *issuer,
-				     struct x509_certificate *cert);
-int x509_certificate_chain_validate(struct x509_certificate *trusted,
-				    struct x509_certificate *chain,
-				    int *reason, int disable_time_checks);
-struct x509_certificate *
-x509_certificate_get_subject(struct x509_certificate *chain,
-			     struct x509_name *name);
-int x509_certificate_self_signed(struct x509_certificate *cert);
-
-#endif /* X509V3_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/utils/base64.h b/tools/sdk/include/wpa_supplicant/wpa2/utils/base64.h
deleted file mode 100644
index aa21fd0fc1b..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/utils/base64.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Base64 encoding/decoding (RFC1341)
- * Copyright (c) 2005, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef BASE64_H
-#define BASE64_H
-
-unsigned char * base64_encode(const unsigned char *src, size_t len,
-			      size_t *out_len);
-unsigned char * base64_decode(const unsigned char *src, size_t len,
-			      size_t *out_len);
-
-#endif /* BASE64_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/utils/ext_password.h b/tools/sdk/include/wpa_supplicant/wpa2/utils/ext_password.h
deleted file mode 100644
index dfe8e6f0e70..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/utils/ext_password.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * External password backend
- * Copyright (c) 2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EXT_PASSWORD_H
-#define EXT_PASSWORD_H
-
-struct ext_password_data;
-
-#ifdef CONFIG_EXT_PASSWORD
-
-struct ext_password_data * ext_password_init(const char *backend,
-					     const char *params);
-void ext_password_deinit(struct ext_password_data *data);
-
-struct wpabuf * ext_password_get(struct ext_password_data *data,
-				 const char *name);
-void ext_password_free(struct wpabuf *pw);
-
-#else /* CONFIG_EXT_PASSWORD */
-
-#define ext_password_init(b, p)
-#define ext_password_deinit(d)
-#define ext_password_get(d, n)
-#define ext_password_free(p)
-
-#endif /* CONFIG_EXT_PASSWORD */
-
-#endif /* EXT_PASSWORD_H */
diff --git a/tools/sdk/include/wpa_supplicant/wpa2/utils/ext_password_i.h b/tools/sdk/include/wpa_supplicant/wpa2/utils/ext_password_i.h
deleted file mode 100644
index 043e7312c62..00000000000
--- a/tools/sdk/include/wpa_supplicant/wpa2/utils/ext_password_i.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * External password backend - internal definitions
- * Copyright (c) 2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef EXT_PASSWORD_I_H
-#define EXT_PASSWORD_I_H
-
-#include "ext_password.h"
-
-struct ext_password_backend {
-	const char *name;
-	void * (*init)(const char *params);
-	void (*deinit)(void *ctx);
-	struct wpabuf * (*get)(void *ctx, const char *name);
-};
-
-struct wpabuf * ext_password_alloc(size_t len);
-
-#endif /* EXT_PASSWORD_I_H */
diff --git a/tools/sdk/include/wpa_supplicant/wps/utils/uuid.h b/tools/sdk/include/wpa_supplicant/wps/utils/uuid.h
deleted file mode 100644
index 5e860cbc593..00000000000
--- a/tools/sdk/include/wpa_supplicant/wps/utils/uuid.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Universally Unique IDentifier (UUID)
- * Copyright (c) 2008, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef UUID_H
-#define UUID_H
-
-#define UUID_LEN 16
-
-int uuid_str2bin(const char *str, u8 *bin);
-int uuid_bin2str(const u8 *bin, char *str, size_t max_len);
-int is_nil_uuid(const u8 *uuid);
-
-#endif /* UUID_H */
diff --git a/tools/sdk/include/wpa_supplicant/wps/wps.h b/tools/sdk/include/wpa_supplicant/wps/wps.h
deleted file mode 100644
index 31092cbb836..00000000000
--- a/tools/sdk/include/wpa_supplicant/wps/wps.h
+++ /dev/null
@@ -1,1065 +0,0 @@
-/*
- * Wi-Fi Protected Setup
- * Copyright (c) 2007-2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef WPS_H
-#define WPS_H
-
-#include "rom/ets_sys.h"
-#include "wps_defs.h"
-#include "esp_wifi_types.h"
-
-/**
- * enum wsc_op_code - EAP-WSC OP-Code values
- */
-enum wsc_op_code {
-	WSC_UPnP = 0 /* No OP Code in UPnP transport */,
-	WSC_Start = 0x01,
-	WSC_ACK = 0x02,
-	WSC_NACK = 0x03,
-	WSC_MSG = 0x04,
-	WSC_Done = 0x05,
-	WSC_FRAG_ACK = 0x06
-};
-
-struct wps_registrar;
-//struct upnp_wps_device_sm;
-struct wps_er;
-struct wps_parse_attr;
-
-/**
- * struct wps_credential - WPS Credential
- * @ssid: SSID
- * @ssid_len: Length of SSID
- * @auth_type: Authentication Type (WPS_WIFI_AUTH_OPEN, .. flags)
- * @encr_type: Encryption Type (WPS_ENCR_NONE, .. flags)
- * @key_idx: Key index
- * @key: Key
- * @key_len: Key length in octets
- * @mac_addr: MAC address of the Credential receiver
- * @cred_attr: Unparsed Credential attribute data (used only in cred_cb());
- *	this may be %NULL, if not used
- * @cred_attr_len: Length of cred_attr in octets
- * @ap_channel: AP channel
- */
-struct wps_credential {
-	u8 ssid[32];
-	size_t ssid_len;
-	u16 auth_type;
-	u16 encr_type;
-	u8 key_idx;
-	u8 key[64];
-	size_t key_len;
-	u8 mac_addr[ETH_ALEN];
-	const u8 *cred_attr;
-	size_t cred_attr_len;
-	u16 ap_channel;
-};
-
-#define WPS_DEV_TYPE_LEN 8
-#define WPS_DEV_TYPE_BUFSIZE 21
-#define WPS_SEC_DEV_TYPE_MAX_LEN 128
-/* maximum number of advertised WPS vendor extension attributes */
-#define MAX_WPS_VENDOR_EXTENSIONS 10
-/* maximum size of WPS Vendor extension attribute */
-#define WPS_MAX_VENDOR_EXT_LEN 1024
-/* maximum number of parsed WPS vendor extension attributes */
-#define MAX_WPS_PARSE_VENDOR_EXT 10
-
-/**
- * struct wps_device_data - WPS Device Data
- * @mac_addr: Device MAC address
- * @device_name: Device Name (0..32 octets encoded in UTF-8)
- * @manufacturer: Manufacturer (0..64 octets encoded in UTF-8)
- * @model_name: Model Name (0..32 octets encoded in UTF-8)
- * @model_number: Model Number (0..32 octets encoded in UTF-8)
- * @serial_number: Serial Number (0..32 octets encoded in UTF-8)
- * @pri_dev_type: Primary Device Type
- * @sec_dev_type: Array of secondary device types
- * @num_sec_dev_type: Number of secondary device types
- * @os_version: OS Version
- * @rf_bands: RF bands (WPS_RF_24GHZ, WPS_RF_50GHZ flags)
- * @p2p: Whether the device is a P2P device
- */
-struct wps_device_data {
-	u8 mac_addr[ETH_ALEN];
-	char *device_name;
-	char *manufacturer;
-	char *model_name;
-	char *model_number;
-	char *serial_number;
-	u8 pri_dev_type[WPS_DEV_TYPE_LEN];
-#define WPS_SEC_DEVICE_TYPES 5
-	u8 sec_dev_type[WPS_SEC_DEVICE_TYPES][WPS_DEV_TYPE_LEN];
-	u8 num_sec_dev_types;
-	u32 os_version;
-	u8 rf_bands;
-	u16 config_methods;
-	struct wpabuf *vendor_ext_m1;
-	struct wpabuf *vendor_ext[MAX_WPS_VENDOR_EXTENSIONS];
-
-	int p2p;
-};
-
-/**
- * struct wps_config - WPS configuration for a single registration protocol run
- */
-struct wps_config {
-	/**
-	 * wps - Pointer to long term WPS context
-	 */
-	struct wps_context *wps;
-
-	/**
-	 * registrar - Whether this end is a Registrar
-	 */
-	int registrar;
-
-	/**
-	 * pin - Enrollee Device Password (%NULL for Registrar or PBC)
-	 */
-	const u8 *pin;
-
-	/**
-	 * pin_len - Length on pin in octets
-	 */
-	size_t pin_len;
-
-	/**
-	 * pbc - Whether this is protocol run uses PBC
-	 */
-	int pbc;
-
-	/**
-	 * assoc_wps_ie: (Re)AssocReq WPS IE (in AP; %NULL if not AP)
-	 */
-	const struct wpabuf *assoc_wps_ie;
-
-	/**
-	 * new_ap_settings - New AP settings (%NULL if not used)
-	 *
-	 * This parameter provides new AP settings when using a wireless
-	 * stations as a Registrar to configure the AP. %NULL means that AP
-	 * will not be reconfigured, i.e., the station will only learn the
-	 * current AP settings by using AP PIN.
-	 */
-	const struct wps_credential *new_ap_settings;
-
-	/**
-	 * peer_addr: MAC address of the peer in AP; %NULL if not AP
-	 */
-	const u8 *peer_addr;
-
-	/**
-	 * use_psk_key - Use PSK format key in Credential
-	 *
-	 * Force PSK format to be used instead of ASCII passphrase when
-	 * building Credential for an Enrollee. The PSK value is set in
-	 * struct wpa_context::psk.
-	 */
-	int use_psk_key;
-
-	/**
-	 * dev_pw_id - Device Password ID for Enrollee when PIN is used
-	 */
-	u16 dev_pw_id;
-
-	/**
-	 * p2p_dev_addr - P2P Device Address from (Re)Association Request
-	 *
-	 * On AP/GO, this is set to the P2P Device Address of the associating
-	 * P2P client if a P2P IE is included in the (Re)Association Request
-	 * frame and the P2P Device Address is included. Otherwise, this is set
-	 * to %NULL to indicate the station does not have a P2P Device Address.
-	 */
-	const u8 *p2p_dev_addr;
-
-	/**
-	 * pbc_in_m1 - Do not remove PushButton config method in M1 (AP)
-	 *
-	 * This can be used to enable a workaround to allow Windows 7 to use
-	 * PBC with the AP.
-	 */
-	int pbc_in_m1;
-};
-
-/* Bssid of the discard AP which is discarded for not select reg or other reason */
-struct discard_ap_list_t{
-	u8 bssid[6];
-};
-
-//struct wps_data * wps_init(const struct wps_config *cfg);
-struct wps_data * wps_init(void);
-
-//void wps_deinit(struct wps_data *data);
-void wps_deinit(void);
-
-/**
- * enum wps_process_res - WPS message processing result
- */
-enum wps_process_res {
-	/**
-	 * WPS_DONE - Processing done
-	 */
-	WPS_DONE,
-
-	/**
-	 * WPS_CONTINUE - Processing continues
-	 */
-	WPS_CONTINUE,
-
-	/**
-	 * WPS_FAILURE - Processing failed
-	 */
-	WPS_FAILURE,
-
-	/**
-	 * WPS_PENDING - Processing continues, but waiting for an external
-	 *	event (e.g., UPnP message from an external Registrar)
-	 */
-	WPS_PENDING,
-	WPS_IGNORE,     /* snake, ignore the re-packge */
-
-	WPS_FRAGMENT    /* Tim, send wsc fragment ack */
-};
-enum wps_process_res wps_process_msg(struct wps_data *wps,
-				     enum wsc_op_code op_code,
-				     const struct wpabuf *msg);
-
-struct wpabuf * wps_get_msg(struct wps_data *wps, enum wsc_op_code *op_code);
-
-int wps_is_selected_pbc_registrar(const struct wpabuf *msg, u8 *bssid);
-int wps_is_selected_pin_registrar(const struct wpabuf *msg, u8 *bssid);
-int wps_ap_priority_compar(const struct wpabuf *wps_a,
-			   const struct wpabuf *wps_b);
-int wps_is_addr_authorized(const struct wpabuf *msg, const u8 *addr,
-			   int ver1_compat);
-const u8 * wps_get_uuid_e(const struct wpabuf *msg);
-int wps_is_20(const struct wpabuf *msg);
-
-struct wpabuf * wps_build_assoc_req_ie(enum wps_request_type req_type);
-struct wpabuf * wps_build_assoc_resp_ie(void);
-struct wpabuf * wps_build_probe_req_ie(u16 pw_id, struct wps_device_data *dev,
-				       const u8 *uuid,
-				       enum wps_request_type req_type,
-				       unsigned int num_req_dev_types,
-				       const u8 *req_dev_types);
-
-
-/**
- * struct wps_registrar_config - WPS Registrar configuration
- */
-struct wps_registrar_config {
-	/**
-	 * new_psk_cb - Callback for new PSK
-	 * @ctx: Higher layer context data (cb_ctx)
-	 * @mac_addr: MAC address of the Enrollee
-	 * @psk: The new PSK
-	 * @psk_len: The length of psk in octets
-	 * Returns: 0 on success, -1 on failure
-	 *
-	 * This callback is called when a new per-device PSK is provisioned.
-	 */
-	int (*new_psk_cb)(void *ctx, const u8 *mac_addr, const u8 *psk,
-			  size_t psk_len);
-
-	/**
-	 * set_ie_cb - Callback for WPS IE changes
-	 * @ctx: Higher layer context data (cb_ctx)
-	 * @beacon_ie: WPS IE for Beacon
-	 * @probe_resp_ie: WPS IE for Probe Response
-	 * Returns: 0 on success, -1 on failure
-	 *
-	 * This callback is called whenever the WPS IE in Beacon or Probe
-	 * Response frames needs to be changed (AP only). Callee is responsible
-	 * for freeing the buffers.
-	 */
-	int (*set_ie_cb)(void *ctx, struct wpabuf *beacon_ie,
-			 struct wpabuf *probe_resp_ie);
-
-	/**
-	 * pin_needed_cb - Callback for requesting a PIN
-	 * @ctx: Higher layer context data (cb_ctx)
-	 * @uuid_e: UUID-E of the unknown Enrollee
-	 * @dev: Device Data from the unknown Enrollee
-	 *
-	 * This callback is called whenever an unknown Enrollee requests to use
-	 * PIN method and a matching PIN (Device Password) is not found in
-	 * Registrar data.
-	 */
-	void (*pin_needed_cb)(void *ctx, const u8 *uuid_e,
-			      const struct wps_device_data *dev);
-
-	/**
-	 * reg_success_cb - Callback for reporting successful registration
-	 * @ctx: Higher layer context data (cb_ctx)
-	 * @mac_addr: MAC address of the Enrollee
-	 * @uuid_e: UUID-E of the Enrollee
-	 * @dev_pw: Device Password (PIN) used during registration
-	 * @dev_pw_len: Length of dev_pw in octets
-	 *
-	 * This callback is called whenever an Enrollee completes registration
-	 * successfully.
-	 */
-	void (*reg_success_cb)(void *ctx, const u8 *mac_addr,
-			       const u8 *uuid_e, const u8 *dev_pw,
-			       size_t dev_pw_len);
-
-	/**
-	 * set_sel_reg_cb - Callback for reporting selected registrar changes
-	 * @ctx: Higher layer context data (cb_ctx)
-	 * @sel_reg: Whether the Registrar is selected
-	 * @dev_passwd_id: Device Password ID to indicate with method or
-	 *	specific password the Registrar intends to use
-	 * @sel_reg_config_methods: Bit field of active config methods
-	 *
-	 * This callback is called whenever the Selected Registrar state
-	 * changes (e.g., a new PIN becomes available or PBC is invoked). This
-	 * callback is only used by External Registrar implementation;
-	 * set_ie_cb() is used by AP implementation in similar caes, but it
-	 * provides the full WPS IE data instead of just the minimal Registrar
-	 * state information.
-	 */
-	void (*set_sel_reg_cb)(void *ctx, int sel_reg, u16 dev_passwd_id,
-			       u16 sel_reg_config_methods);
-
-	/**
-	 * enrollee_seen_cb - Callback for reporting Enrollee based on ProbeReq
-	 * @ctx: Higher layer context data (cb_ctx)
-	 * @addr: MAC address of the Enrollee
-	 * @uuid_e: UUID of the Enrollee
-	 * @pri_dev_type: Primary device type
-	 * @config_methods: Config Methods
-	 * @dev_password_id: Device Password ID
-	 * @request_type: Request Type
-	 * @dev_name: Device Name (if available)
-	 */
-	void (*enrollee_seen_cb)(void *ctx, const u8 *addr, const u8 *uuid_e,
-				 const u8 *pri_dev_type, u16 config_methods,
-				 u16 dev_password_id, u8 request_type,
-				 const char *dev_name);
-
-	/**
-	 * cb_ctx: Higher layer context data for Registrar callbacks
-	 */
-	void *cb_ctx;
-
-	/**
-	 * skip_cred_build: Do not build credential
-	 *
-	 * This option can be used to disable internal code that builds
-	 * Credential attribute into M8 based on the current network
-	 * configuration and Enrollee capabilities. The extra_cred data will
-	 * then be used as the Credential(s).
-	 */
-	int skip_cred_build;
-
-	/**
-	 * extra_cred: Additional Credential attribute(s)
-	 *
-	 * This optional data (set to %NULL to disable) can be used to add
-	 * Credential attribute(s) for other networks into M8. If
-	 * skip_cred_build is set, this will also override the automatically
-	 * generated Credential attribute.
-	 */
-	const u8 *extra_cred;
-
-	/**
-	 * extra_cred_len: Length of extra_cred in octets
-	 */
-	size_t extra_cred_len;
-
-	/**
-	 * disable_auto_conf - Disable auto-configuration on first registration
-	 *
-	 * By default, the AP that is started in not configured state will
-	 * generate a random PSK and move to configured state when the first
-	 * registration protocol run is completed successfully. This option can
-	 * be used to disable this functionality and leave it up to an external
-	 * program to take care of configuration. This requires the extra_cred
-	 * to be set with a suitable Credential and skip_cred_build being used.
-	 */
-	int disable_auto_conf;
-
-	/**
-	 * static_wep_only - Whether the BSS supports only static WEP
-	 */
-	int static_wep_only;
-
-	/**
-	 * dualband - Whether this is a concurrent dualband AP
-	 */
-	int dualband;
-};
-
-
-/**
- * enum wps_event - WPS event types
- */
-enum wps_event {
-	/**
-	 * WPS_EV_M2D - M2D received (Registrar did not know us)
-	 */
-	WPS_EV_M2D,
-
-	/**
-	 * WPS_EV_FAIL - Registration failed
-	 */
-	WPS_EV_FAIL,
-
-	/**
-	 * WPS_EV_SUCCESS - Registration succeeded
-	 */
-	WPS_EV_SUCCESS,
-
-	/**
-	 * WPS_EV_PWD_AUTH_FAIL - Password authentication failed
-	 */
-	WPS_EV_PWD_AUTH_FAIL,
-
-	/**
-	 * WPS_EV_PBC_OVERLAP - PBC session overlap detected
-	 */
-	WPS_EV_PBC_OVERLAP,
-
-	/**
-	 * WPS_EV_PBC_TIMEOUT - PBC walktime expired before protocol run start
-	 */
-	WPS_EV_PBC_TIMEOUT,
-
-	/**
-	 * WPS_EV_ER_AP_ADD - ER: AP added
-	 */
-	WPS_EV_ER_AP_ADD,
-
-	/**
-	 * WPS_EV_ER_AP_REMOVE - ER: AP removed
-	 */
-	WPS_EV_ER_AP_REMOVE,
-
-	/**
-	 * WPS_EV_ER_ENROLLEE_ADD - ER: Enrollee added
-	 */
-	WPS_EV_ER_ENROLLEE_ADD,
-
-	/**
-	 * WPS_EV_ER_ENROLLEE_REMOVE - ER: Enrollee removed
-	 */
-	WPS_EV_ER_ENROLLEE_REMOVE,
-
-	/**
-	 * WPS_EV_ER_AP_SETTINGS - ER: AP Settings learned
-	 */
-	WPS_EV_ER_AP_SETTINGS,
-
-	/**
-	 * WPS_EV_ER_SET_SELECTED_REGISTRAR - ER: SetSelectedRegistrar event
-	 */
-	WPS_EV_ER_SET_SELECTED_REGISTRAR,
-
-	/**
-	 * WPS_EV_AP_PIN_SUCCESS - External Registrar used correct AP PIN
-	 */
-	WPS_EV_AP_PIN_SUCCESS
-};
-
-/**
- * union wps_event_data - WPS event data
- */
-union wps_event_data {
-	/**
-	 * struct wps_event_m2d - M2D event data
-	 */
-	struct wps_event_m2d {
-		u16 config_methods;
-		const u8 *manufacturer;
-		size_t manufacturer_len;
-		const u8 *model_name;
-		size_t model_name_len;
-		const u8 *model_number;
-		size_t model_number_len;
-		const u8 *serial_number;
-		size_t serial_number_len;
-		const u8 *dev_name;
-		size_t dev_name_len;
-		const u8 *primary_dev_type; /* 8 octets */
-		u16 config_error;
-		u16 dev_password_id;
-	} m2d;
-
-	/**
-	 * struct wps_event_fail - Registration failure information
-	 * @msg: enum wps_msg_type
-	 */
-	struct wps_event_fail {
-		int msg;
-		u16 config_error;
-		u16 error_indication;
-	} fail;
-
-	struct wps_event_pwd_auth_fail {
-		int enrollee;
-		int part;
-	} pwd_auth_fail;
-
-	struct wps_event_er_ap {
-		const u8 *uuid;
-		const u8 *mac_addr;
-		const char *friendly_name;
-		const char *manufacturer;
-		const char *manufacturer_url;
-		const char *model_description;
-		const char *model_name;
-		const char *model_number;
-		const char *model_url;
-		const char *serial_number;
-		const char *upc;
-		const u8 *pri_dev_type;
-		u8 wps_state;
-	} ap;
-
-	struct wps_event_er_enrollee {
-		const u8 *uuid;
-		const u8 *mac_addr;
-		int m1_received;
-		u16 config_methods;
-		u16 dev_passwd_id;
-		const u8 *pri_dev_type;
-		const char *dev_name;
-		const char *manufacturer;
-		const char *model_name;
-		const char *model_number;
-		const char *serial_number;
-	} enrollee;
-
-	struct wps_event_er_ap_settings {
-		const u8 *uuid;
-		const struct wps_credential *cred;
-	} ap_settings;
-
-	struct wps_event_er_set_selected_registrar {
-		const u8 *uuid;
-		int sel_reg;
-		u16 dev_passwd_id;
-		u16 sel_reg_config_methods;
-		enum {
-			WPS_ER_SET_SEL_REG_START,
-			WPS_ER_SET_SEL_REG_DONE,
-			WPS_ER_SET_SEL_REG_FAILED
-		} state;
-	} set_sel_reg;
-};
-#ifdef CONFIG_WPS_UPNP
-/**
- * struct upnp_pending_message - Pending PutWLANResponse messages
- * @next: Pointer to next pending message or %NULL
- * @addr: NewWLANEventMAC
- * @msg: NewMessage
- * @type: Message Type
- */
-struct upnp_pending_message {
-	struct upnp_pending_message *next;
-	u8 addr[ETH_ALEN];
-	struct wpabuf *msg;
-	enum wps_msg_type type;
-};
-void wps_free_pending_msgs(struct upnp_pending_message *msgs);
-#endif
-/**
- * struct wps_context - Long term WPS context data
- *
- * This data is stored at the higher layer Authenticator or Supplicant data
- * structures and it is maintained over multiple registration protocol runs.
- */
-struct wps_context {
-	/**
-	 * ap - Whether the local end is an access point
-	 */
-	int ap;
-
-	/**
-	 * registrar - Pointer to WPS registrar data from wps_registrar_init()
-	 */
-	struct wps_registrar *registrar;
-
-	/**
-	 * wps_state - Current WPS state
-	 */
-	enum wps_state wps_state;
-
-	/**
-	 * ap_setup_locked - Whether AP setup is locked (only used at AP)
-	 */
-	int ap_setup_locked;
-
-	/**
-	 * uuid - Own UUID
-	 */
-	u8 uuid[16];
-
-	/**
-	 * ssid - SSID
-	 *
-	 * This SSID is used by the Registrar to fill in information for
-	 * Credentials. In addition, AP uses it when acting as an Enrollee to
-	 * notify Registrar of the current configuration.
-	 */
-	u8 ssid[32];
-
-	/**
-	 * ssid_len - Length of ssid in octets
-	 */
-	size_t ssid_len;
-
-	/**
-	 * dev - Own WPS device data
-	 */
-	struct wps_device_data dev;
-
-	/**
-	 * dh_ctx - Context data for Diffie-Hellman operation
-	 */
-	void *dh_ctx;
-
-	/**
-	 * dh_privkey - Diffie-Hellman private key
-	 */
-	struct wpabuf *dh_privkey;
-
-	/**
-	 * dh_pubkey_oob - Diffie-Hellman public key
-	 */
-	struct wpabuf *dh_pubkey;
-
-	/**
-	 * config_methods - Enabled configuration methods
-	 *
-	 * Bit field of WPS_CONFIG_*
-	 */
-	u16 config_methods;
-
-	/**
-	 * encr_types - Enabled encryption types (bit field of WPS_ENCR_*)
-	 */
-	u16 encr_types;
-
-	/**
-	 * auth_types - Authentication types (bit field of WPS_AUTH_*)
-	 */
-	u16 auth_types;
-
-	/**
-	 * network_key - The current Network Key (PSK) or %NULL to generate new
-	 *
-	 * If %NULL, Registrar will generate per-device PSK. In addition, AP
-	 * uses this when acting as an Enrollee to notify Registrar of the
-	 * current configuration.
-	 *
-	 * When using WPA/WPA2-Person, this key can be either the ASCII
-	 * passphrase (8..63 characters) or the 32-octet PSK (64 hex
-	 * characters). When this is set to the ASCII passphrase, the PSK can
-	 * be provided in the psk buffer and used per-Enrollee to control which
-	 * key type is included in the Credential (e.g., to reduce calculation
-	 * need on low-powered devices by provisioning PSK while still allowing
-	 * other devices to get the passphrase).
-	 */
-	u8 *network_key;
-
-	/**
-	 * network_key_len - Length of network_key in octets
-	 */
-	size_t network_key_len;
-
-	/**
-	 * psk - The current network PSK
-	 *
-	 * This optional value can be used to provide the current PSK if
-	 * network_key is set to the ASCII passphrase.
-	 */
-	u8 psk[32];
-
-	/**
-	 * psk_set - Whether psk value is set
-	 */
-	int psk_set;
-
-	/**
-	 * ap_settings - AP Settings override for M7 (only used at AP)
-	 *
-	 * If %NULL, AP Settings attributes will be generated based on the
-	 * current network configuration.
-	 */
-	u8 *ap_settings;
-
-	/**
-	 * ap_settings_len - Length of ap_settings in octets
-	 */
-	size_t ap_settings_len;
-
-	/**
-	 * friendly_name - Friendly Name (required for UPnP)
-	 */
-	char *friendly_name;
-
-	/**
-	 * manufacturer_url - Manufacturer URL (optional for UPnP)
-	 */
-	char *manufacturer_url;
-
-	/**
-	 * model_description - Model Description (recommended for UPnP)
-	 */
-	char *model_description;
-
-	/**
-	 * model_url - Model URL (optional for UPnP)
-	 */
-	char *model_url;
-
-	/**
-	 * upc - Universal Product Code (optional for UPnP)
-	 */
-	char *upc;
-
-	/**
-	 * cred_cb - Callback to notify that new Credentials were received
-	 * @ctx: Higher layer context data (cb_ctx)
-	 * @cred: The received Credential
-	 * Return: 0 on success, -1 on failure
-	 */
-	int (*cred_cb)(void *ctx, const struct wps_credential *cred);
-
-	/**
-	 * event_cb - Event callback (state information about progress)
-	 * @ctx: Higher layer context data (cb_ctx)
-	 * @event: Event type
-	 * @data: Event data
-	 */
-	void (*event_cb)(void *ctx, enum wps_event event,
-			 union wps_event_data *data);
-
-	/**
-	 * cb_ctx: Higher layer context data for callbacks
-	 */
-	void *cb_ctx;
-
-	//struct upnp_wps_device_sm *wps_upnp;
-
-	/* Pending messages from UPnP PutWLANResponse */
-	//struct upnp_pending_message *upnp_msgs;
-#ifdef CONFIG_WPS_NFC
-
-	u16 ap_nfc_dev_pw_id;
-	struct wpabuf *ap_nfc_dh_pubkey;
-	struct wpabuf *ap_nfc_dh_privkey;
-	struct wpabuf *ap_nfc_dev_pw;
-#endif
-};
-
-struct wps_registrar *
-wps_registrar_init(struct wps_context *wps,
-		   const struct wps_registrar_config *cfg);
-void wps_registrar_deinit(struct wps_registrar *reg);
-#ifdef CONFIG_WPS_PIN
-
-int wps_registrar_add_pin(struct wps_registrar *reg, const u8 *addr,
-			  const u8 *uuid, const u8 *pin, size_t pin_len,
-			  int timeout);
-int wps_registrar_invalidate_pin(struct wps_registrar *reg, const u8 *uuid);
-int wps_registrar_unlock_pin(struct wps_registrar *reg, const u8 *uuid);
-#endif
-int wps_registrar_wps_cancel(struct wps_registrar *reg);
-
-int wps_registrar_button_pushed(struct wps_registrar *reg,
-				const u8 *p2p_dev_addr);
-void wps_registrar_complete(struct wps_registrar *registrar, const u8 *uuid_e,
-			    const u8 *dev_pw, size_t dev_pw_len);
-void wps_registrar_probe_req_rx(struct wps_registrar *reg, const u8 *addr,
-				const struct wpabuf *wps_data,
-				int p2p_wildcard);
-int wps_registrar_update_ie(struct wps_registrar *reg);
-int wps_registrar_get_info(struct wps_registrar *reg, const u8 *addr,
-			   char *buf, size_t buflen);
-int wps_registrar_config_ap(struct wps_registrar *reg,
-			    struct wps_credential *cred);
-#ifdef CONFIG_WPS_NFC
-
-int wps_registrar_add_nfc_pw_token(struct wps_registrar *reg,
-				   const u8 *pubkey_hash, u16 pw_id,
-				   const u8 *dev_pw, size_t dev_pw_len);
-int wps_registrar_add_nfc_password_token(struct wps_registrar *reg,
-					 const u8 *oob_dev_pw,
-					 size_t oob_dev_pw_len);
-#endif
-int wps_build_credential_wrap(struct wpabuf *msg,
-			      const struct wps_credential *cred);
-#ifdef CONFIG_WPS_PIN
-
-unsigned int wps_pin_checksum(unsigned int pin);
-unsigned int wps_pin_valid(unsigned int pin);
-int wps_pin_str_valid(const char *pin);
-#endif
-unsigned int wps_generate_pin(void);
-
-#ifdef CONFIG_WPS_OOB
-
-struct wpabuf * wps_get_oob_cred(struct wps_context *wps);
-int wps_oob_use_cred(struct wps_context *wps, struct wps_parse_attr *attr);
-#endif
-int wps_attr_text(struct wpabuf *data, char *buf, char *end);
-
-struct wps_er * wps_er_init(struct wps_context *wps, const char *ifname,
-			    const char *filter);
-void wps_er_refresh(struct wps_er *er);
-void wps_er_deinit(struct wps_er *er, void (*cb)(void *ctx), void *ctx);
-void wps_er_set_sel_reg(struct wps_er *er, int sel_reg, u16 dev_passwd_id,
-			u16 sel_reg_config_methods);
-int wps_er_pbc(struct wps_er *er, const u8 *uuid);
-int wps_er_learn(struct wps_er *er, const u8 *uuid, const u8 *pin,
-		 size_t pin_len);
-int wps_er_set_config(struct wps_er *er, const u8 *uuid,
-		      const struct wps_credential *cred);
-int wps_er_config(struct wps_er *er, const u8 *uuid, const u8 *pin,
-		  size_t pin_len, const struct wps_credential *cred);
-#ifdef CONFIG_WPS_NFC
-
-struct wpabuf * wps_er_nfc_config_token(struct wps_er *er, const u8 *uuid);
-
-#endif
-
-int wps_dev_type_str2bin(const char *str, u8 dev_type[WPS_DEV_TYPE_LEN]);
-char * wps_dev_type_bin2str(const u8 dev_type[WPS_DEV_TYPE_LEN], char *buf,
-			    size_t buf_len);
-void uuid_gen_mac_addr(const u8 *mac_addr, u8 *uuid);
-u16 wps_config_methods_str2bin(const char *str);
-
-#ifdef CONFIG_WPS_NFC
-
-struct wpabuf * wps_build_nfc_pw_token(u16 dev_pw_id,
-				       const struct wpabuf *pubkey,
-				       const struct wpabuf *dev_pw);
-struct wpabuf * wps_nfc_token_gen(int ndef, int *id, struct wpabuf **pubkey,
-				  struct wpabuf **privkey,
-				  struct wpabuf **dev_pw);
-#endif
-
-/* ndef.c */
-struct wpabuf * ndef_parse_wifi(const struct wpabuf *buf);
-struct wpabuf * ndef_build_wifi(const struct wpabuf *buf);
-struct wpabuf * ndef_build_wifi_hr(void);
-
-#ifdef CONFIG_WPS_STRICT
-int wps_validate_beacon(const struct wpabuf *wps_ie);
-int wps_validate_beacon_probe_resp(const struct wpabuf *wps_ie, int probe,
-				   const u8 *addr);
-int wps_validate_probe_req(const struct wpabuf *wps_ie, const u8 *addr);
-int wps_validate_assoc_req(const struct wpabuf *wps_ie);
-int wps_validate_assoc_resp(const struct wpabuf *wps_ie);
-int wps_validate_m1(const struct wpabuf *tlvs);
-int wps_validate_m2(const struct wpabuf *tlvs);
-int wps_validate_m2d(const struct wpabuf *tlvs);
-int wps_validate_m3(const struct wpabuf *tlvs);
-int wps_validate_m4(const struct wpabuf *tlvs);
-int wps_validate_m4_encr(const struct wpabuf *tlvs, int wps2);
-int wps_validate_m5(const struct wpabuf *tlvs);
-int wps_validate_m5_encr(const struct wpabuf *tlvs, int wps2);
-int wps_validate_m6(const struct wpabuf *tlvs);
-int wps_validate_m6_encr(const struct wpabuf *tlvs, int wps2);
-int wps_validate_m7(const struct wpabuf *tlvs);
-int wps_validate_m7_encr(const struct wpabuf *tlvs, int ap, int wps2);
-int wps_validate_m8(const struct wpabuf *tlvs);
-int wps_validate_m8_encr(const struct wpabuf *tlvs, int ap, int wps2);
-int wps_validate_wsc_ack(const struct wpabuf *tlvs);
-int wps_validate_wsc_nack(const struct wpabuf *tlvs);
-int wps_validate_wsc_done(const struct wpabuf *tlvs);
-int wps_validate_upnp_set_selected_registrar(const struct wpabuf *tlvs);
-#else /* CONFIG_WPS_STRICT */
-static inline int wps_validate_beacon(const struct wpabuf *wps_ie){
-	return 0;
-}
-
-static inline int wps_validate_beacon_probe_resp(const struct wpabuf *wps_ie,
-						 int probe, const u8 *addr)
-{
-	return 0;
-}
-
-static inline int wps_validate_probe_req(const struct wpabuf *wps_ie,
-					 const u8 *addr)
-{
-	return 0;
-}
-
-static inline int wps_validate_assoc_req(const struct wpabuf *wps_ie)
-{
-	return 0;
-}
-
-static inline int wps_validate_assoc_resp(const struct wpabuf *wps_ie)
-{
-	return 0;
-}
-
-static inline int wps_validate_m1(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_m2(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_m2d(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_m3(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_m4(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_m4_encr(const struct wpabuf *tlvs, int wps2)
-{
-	return 0;
-}
-
-static inline int wps_validate_m5(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_m5_encr(const struct wpabuf *tlvs, int wps2)
-{
-	return 0;
-}
-
-static inline int wps_validate_m6(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_m6_encr(const struct wpabuf *tlvs, int wps2)
-{
-	return 0;
-}
-
-static inline int wps_validate_m7(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_m7_encr(const struct wpabuf *tlvs, int ap,
-				       int wps2)
-{
-	return 0;
-}
-
-static inline int wps_validate_m8(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_m8_encr(const struct wpabuf *tlvs, int ap,
-				       int wps2)
-{
-	return 0;
-}
-
-static inline int wps_validate_wsc_ack(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_wsc_nack(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_wsc_done(const struct wpabuf *tlvs)
-{
-	return 0;
-}
-
-static inline int wps_validate_upnp_set_selected_registrar(
-	const struct wpabuf *tlvs)
-{
-	return 0;
-}
-#endif /* CONFIG_WPS_STRICT */
-
-enum wps_cb_status {
-	WPS_CB_ST_SUCCESS = 0,
-	WPS_CB_ST_FAILED,
-	WPS_CB_ST_TIMEOUT,
-	WPS_CB_ST_WEP,
-	WPS_CB_ST_SCAN_ERR,
-};
-
-typedef void (*wps_st_cb_t)(int status);
-
-#ifdef USE_WPS_TASK
-#define SIG_WPS_START	2
-#define	SIG_WPS_RX	3
-#define	SIG_WPS_NUM	9
-#endif
-
-#define WPS_EAP_EXT_VENDOR_TYPE "WFA-SimpleConfig-Enrollee-1-0"
-#define WPS_OUTBUF_SIZE 500
-struct wps_sm {
-    struct wps_config *wps_cfg;
-    struct wps_context *wps_ctx;
-    struct wps_data *wps;
-    char identity[32];
-    u8 identity_len;
-    u8 ownaddr[ETH_ALEN];
-    u8 bssid[ETH_ALEN];
-    u8 ssid[32];
-    u8 ssid_len;
-    struct wps_device_data *dev;
-    u8 uuid[16];
-    u8 eapol_version;
-    char key[64];
-    u8 key_len;
-    ETSTimer wps_timeout_timer;
-    ETSTimer wps_msg_timeout_timer;
-    ETSTimer wps_scan_timer;
-    ETSTimer wps_success_cb_timer;
-    ETSTimer wps_eapol_start_timer;
-    wps_st_cb_t st_cb;
-    u8 current_identifier;
-    bool is_wps_scan;
-    u8 channel;
-    u8 scan_cnt;
-#ifdef USE_WPS_TASK
-    u8 wps_sig_cnt[SIG_WPS_NUM];
-#endif
-    u8 discover_ssid_cnt;
-    bool ignore_sel_reg;
-    struct discard_ap_list_t dis_ap_list[WPS_MAX_DIS_AP_NUM];
-    u8 discard_ap_cnt;
-    wifi_sta_config_t config;
-};
-
-#define    IEEE80211_CAPINFO_PRIVACY        0x0010
-
-struct wps_sm *wps_sm_get(void);
-int wps_ssid_save(u8 *ssid, u8 ssid_len);
-int wps_key_save(char *key, u8 key_len);
-int wps_station_wps_register_cb(wps_st_cb_t cb);
-int wps_station_wps_unregister_cb(void); 
-int wps_start_pending(void);
-int wps_sm_rx_eapol(u8 *src_addr, u8 *buf, u32 len);
-
-int wps_dev_deinit(struct wps_device_data *dev);
-#endif /* WPS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wps/wps_attr_parse.h b/tools/sdk/include/wpa_supplicant/wps/wps_attr_parse.h
deleted file mode 100644
index 86061aea062..00000000000
--- a/tools/sdk/include/wpa_supplicant/wps/wps_attr_parse.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Wi-Fi Protected Setup - attribute parsing
- * Copyright (c) 2008-2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef WPS_ATTR_PARSE_H
-#define WPS_ATTR_PARSE_H
-
-#include "wps/wps.h"
-
-struct wps_parse_attr {
-	/* fixed length fields */
-	const u8 *version; /* 1 octet */
-	const u8 *version2; /* 1 octet */
-	const u8 *msg_type; /* 1 octet */
-	const u8 *enrollee_nonce; /* WPS_NONCE_LEN (16) octets */
-	const u8 *registrar_nonce; /* WPS_NONCE_LEN (16) octets */
-	const u8 *uuid_r; /* WPS_UUID_LEN (16) octets */
-	const u8 *uuid_e; /* WPS_UUID_LEN (16) octets */
-	const u8 *auth_type_flags; /* 2 octets */
-	const u8 *encr_type_flags; /* 2 octets */
-	const u8 *conn_type_flags; /* 1 octet */
-	const u8 *config_methods; /* 2 octets */
-	const u8 *sel_reg_config_methods; /* 2 octets */
-	const u8 *primary_dev_type; /* 8 octets */
-	const u8 *rf_bands; /* 1 octet */
-	const u8 *assoc_state; /* 2 octets */
-	const u8 *config_error; /* 2 octets */
-	const u8 *dev_password_id; /* 2 octets */
-	const u8 *os_version; /* 4 octets */
-	const u8 *wps_state; /* 1 octet */
-	const u8 *authenticator; /* WPS_AUTHENTICATOR_LEN (8) octets */
-	const u8 *r_hash1; /* WPS_HASH_LEN (32) octets */
-	const u8 *r_hash2; /* WPS_HASH_LEN (32) octets */
-	const u8 *e_hash1; /* WPS_HASH_LEN (32) octets */
-	const u8 *e_hash2; /* WPS_HASH_LEN (32) octets */
-	const u8 *r_snonce1; /* WPS_SECRET_NONCE_LEN (16) octets */
-	const u8 *r_snonce2; /* WPS_SECRET_NONCE_LEN (16) octets */
-	const u8 *e_snonce1; /* WPS_SECRET_NONCE_LEN (16) octets */
-	const u8 *e_snonce2; /* WPS_SECRET_NONCE_LEN (16) octets */
-	const u8 *key_wrap_auth; /* WPS_KWA_LEN (8) octets */
-	const u8 *auth_type; /* 2 octets */
-	const u8 *encr_type; /* 2 octets */
-	const u8 *network_idx; /* 1 octet */
-	const u8 *network_key_idx; /* 1 octet */
-	const u8 *mac_addr; /* ETH_ALEN (6) octets */
-	const u8 *key_prov_auto; /* 1 octet (Bool) */
-	const u8 *dot1x_enabled; /* 1 octet (Bool) */
-	const u8 *selected_registrar; /* 1 octet (Bool) */
-	const u8 *request_type; /* 1 octet */
-	const u8 *response_type; /* 1 octet */
-	const u8 *ap_setup_locked; /* 1 octet */
-	const u8 *settings_delay_time; /* 1 octet */
-	const u8 *network_key_shareable; /* 1 octet (Bool) */
-	const u8 *request_to_enroll; /* 1 octet (Bool) */
-	const u8 *ap_channel; /* 2 octets */
-
-	/* variable length fields */
-	const u8 *manufacturer;
-	size_t manufacturer_len;
-	const u8 *model_name;
-	size_t model_name_len;
-	const u8 *model_number;
-	size_t model_number_len;
-	const u8 *serial_number;
-	size_t serial_number_len;
-	const u8 *dev_name;
-	size_t dev_name_len;
-	const u8 *public_key;
-	size_t public_key_len;
-	const u8 *encr_settings;
-	size_t encr_settings_len;
-	const u8 *ssid; /* <= 32 octets */
-	size_t ssid_len;
-	const u8 *network_key; /* <= 64 octets */
-	size_t network_key_len;
-	const u8 *eap_type; /* <= 8 octets */
-	size_t eap_type_len;
-	const u8 *eap_identity; /* <= 64 octets */
-	size_t eap_identity_len;
-	const u8 *authorized_macs; /* <= 30 octets */
-	size_t authorized_macs_len;
-	const u8 *sec_dev_type_list; /* <= 128 octets */
-	size_t sec_dev_type_list_len;
-	const u8 *oob_dev_password; /* 38..54 octets */
-	size_t oob_dev_password_len;
-
-	/* attributes that can occur multiple times */
-#define MAX_CRED_COUNT 10
-	const u8 *cred[MAX_CRED_COUNT];
-	size_t cred_len[MAX_CRED_COUNT];
-	size_t num_cred;
-
-#define MAX_REQ_DEV_TYPE_COUNT 10
-	const u8 *req_dev_type[MAX_REQ_DEV_TYPE_COUNT];
-	size_t num_req_dev_type;
-
-	const u8 *vendor_ext[MAX_WPS_PARSE_VENDOR_EXT];
-	size_t vendor_ext_len[MAX_WPS_PARSE_VENDOR_EXT];
-	size_t num_vendor_ext;
-};
-
-int wps_parse_msg(const struct wpabuf *msg, struct wps_parse_attr *attr);
-
-#endif /* WPS_ATTR_PARSE_H */
diff --git a/tools/sdk/include/wpa_supplicant/wps/wps_defs.h b/tools/sdk/include/wpa_supplicant/wps/wps_defs.h
deleted file mode 100644
index d100202da6e..00000000000
--- a/tools/sdk/include/wpa_supplicant/wps/wps_defs.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * Wi-Fi Protected Setup - message definitions
- * Copyright (c) 2008, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef WPS_DEFS_H
-#define WPS_DEFS_H
-
-#ifdef CONFIG_WPS_TESTING
-
-extern int wps_version_number;
-extern int wps_testing_dummy_cred;
-#define WPS_VERSION wps_version_number
-
-#else /* CONFIG_WPS_TESTING */
-
-#ifdef CONFIG_WPS2
-#define WPS_VERSION 0x20
-#else /* CONFIG_WPS2 */
-#define WPS_VERSION 0x10
-#endif /* CONFIG_WPS2 */
-
-#endif /* CONFIG_WPS_TESTING */
-
-#define CONFIG_WPS_STRICT
-
-/* Diffie-Hellman 1536-bit MODP Group; RFC 3526, Group 5 */
-#define WPS_DH_GROUP 5
-
-#define WPS_UUID_LEN 16
-#define WPS_NONCE_LEN 16
-#define WPS_AUTHENTICATOR_LEN 8
-#define WPS_AUTHKEY_LEN 32
-#define WPS_KEYWRAPKEY_LEN 16
-#define WPS_EMSK_LEN 32
-#define WPS_PSK_LEN 16
-#define WPS_SECRET_NONCE_LEN 16
-#define WPS_HASH_LEN 32
-#define WPS_KWA_LEN 8
-#define WPS_MGMTAUTHKEY_LEN 32
-#define WPS_MGMTENCKEY_LEN 16
-#define WPS_MGMT_KEY_ID_LEN 16
-#define WPS_OOB_DEVICE_PASSWORD_MIN_LEN 16
-#define WPS_OOB_DEVICE_PASSWORD_LEN 32
-#define WPS_OOB_PUBKEY_HASH_LEN 20
-
-/* Attribute Types */
-enum wps_attribute {
-	ATTR_AP_CHANNEL = 0x1001,
-	ATTR_ASSOC_STATE = 0x1002,
-	ATTR_AUTH_TYPE = 0x1003,
-	ATTR_AUTH_TYPE_FLAGS = 0x1004,
-	ATTR_AUTHENTICATOR = 0x1005,
-	ATTR_CONFIG_METHODS = 0x1008,
-	ATTR_CONFIG_ERROR = 0x1009,
-	ATTR_CONFIRM_URL4 = 0x100a,
-	ATTR_CONFIRM_URL6 = 0x100b,
-	ATTR_CONN_TYPE = 0x100c,
-	ATTR_CONN_TYPE_FLAGS = 0x100d,
-	ATTR_CRED = 0x100e,
-	ATTR_ENCR_TYPE = 0x100f,
-	ATTR_ENCR_TYPE_FLAGS = 0x1010,
-	ATTR_DEV_NAME = 0x1011,
-	ATTR_DEV_PASSWORD_ID = 0x1012,
-	ATTR_E_HASH1 = 0x1014,
-	ATTR_E_HASH2 = 0x1015,
-	ATTR_E_SNONCE1 = 0x1016,
-	ATTR_E_SNONCE2 = 0x1017,
-	ATTR_ENCR_SETTINGS = 0x1018,
-	ATTR_ENROLLEE_NONCE = 0x101a,
-	ATTR_FEATURE_ID = 0x101b,
-	ATTR_IDENTITY = 0x101c,
-	ATTR_IDENTITY_PROOF = 0x101d,
-	ATTR_KEY_WRAP_AUTH = 0x101e,
-	ATTR_KEY_ID = 0x101f,
-	ATTR_MAC_ADDR = 0x1020,
-	ATTR_MANUFACTURER = 0x1021,
-	ATTR_MSG_TYPE = 0x1022,
-	ATTR_MODEL_NAME = 0x1023,
-	ATTR_MODEL_NUMBER = 0x1024,
-	ATTR_NETWORK_INDEX = 0x1026,
-	ATTR_NETWORK_KEY = 0x1027,
-	ATTR_NETWORK_KEY_INDEX = 0x1028,
-	ATTR_NEW_DEVICE_NAME = 0x1029,
-	ATTR_NEW_PASSWORD = 0x102a,
-	ATTR_OOB_DEVICE_PASSWORD = 0x102c,
-	ATTR_OS_VERSION = 0x102d,
-	ATTR_POWER_LEVEL = 0x102f,
-	ATTR_PSK_CURRENT = 0x1030,
-	ATTR_PSK_MAX = 0x1031,
-	ATTR_PUBLIC_KEY = 0x1032,
-	ATTR_RADIO_ENABLE = 0x1033,
-	ATTR_REBOOT = 0x1034,
-	ATTR_REGISTRAR_CURRENT = 0x1035,
-	ATTR_REGISTRAR_ESTABLISHED = 0x1036,
-	ATTR_REGISTRAR_LIST = 0x1037,
-	ATTR_REGISTRAR_MAX = 0x1038,
-	ATTR_REGISTRAR_NONCE = 0x1039,
-	ATTR_REQUEST_TYPE = 0x103a,
-	ATTR_RESPONSE_TYPE = 0x103b,
-	ATTR_RF_BANDS = 0x103c,
-	ATTR_R_HASH1 = 0x103d,
-	ATTR_R_HASH2 = 0x103e,
-	ATTR_R_SNONCE1 = 0x103f,
-	ATTR_R_SNONCE2 = 0x1040,
-	ATTR_SELECTED_REGISTRAR = 0x1041,
-	ATTR_SERIAL_NUMBER = 0x1042,
-	ATTR_WPS_STATE = 0x1044,
-	ATTR_SSID = 0x1045,
-	ATTR_TOTAL_NETWORKS = 0x1046,
-	ATTR_UUID_E = 0x1047,
-	ATTR_UUID_R = 0x1048,
-	ATTR_VENDOR_EXT = 0x1049,
-	ATTR_VERSION = 0x104a,
-	ATTR_X509_CERT_REQ = 0x104b,
-	ATTR_X509_CERT = 0x104c,
-	ATTR_EAP_IDENTITY = 0x104d,
-	ATTR_MSG_COUNTER = 0x104e,
-	ATTR_PUBKEY_HASH = 0x104f,
-	ATTR_REKEY_KEY = 0x1050,
-	ATTR_KEY_LIFETIME = 0x1051,
-	ATTR_PERMITTED_CFG_METHODS = 0x1052,
-	ATTR_SELECTED_REGISTRAR_CONFIG_METHODS = 0x1053,
-	ATTR_PRIMARY_DEV_TYPE = 0x1054,
-	ATTR_SECONDARY_DEV_TYPE_LIST = 0x1055,
-	ATTR_PORTABLE_DEV = 0x1056,
-	ATTR_AP_SETUP_LOCKED = 0x1057,
-	ATTR_APPLICATION_EXT = 0x1058,
-	ATTR_EAP_TYPE = 0x1059,
-	ATTR_IV = 0x1060,
-	ATTR_KEY_PROVIDED_AUTO = 0x1061,
-	ATTR_802_1X_ENABLED = 0x1062,
-	ATTR_APPSESSIONKEY = 0x1063,
-	ATTR_WEPTRANSMITKEY = 0x1064,
-	ATTR_REQUESTED_DEV_TYPE = 0x106a,
-	ATTR_EXTENSIBILITY_TEST = 0x10fa /* _NOT_ defined in the spec */
-};
-
-#define WPS_VENDOR_ID_WFA 14122
-
-/* WFA Vendor Extension subelements */
-enum {
-	WFA_ELEM_VERSION2 = 0x00,
-	WFA_ELEM_AUTHORIZEDMACS = 0x01,
-	WFA_ELEM_NETWORK_KEY_SHAREABLE = 0x02,
-	WFA_ELEM_REQUEST_TO_ENROLL = 0x03,
-	WFA_ELEM_SETTINGS_DELAY_TIME = 0x04
-};
-
-/* Device Password ID */
-enum wps_dev_password_id {
-	DEV_PW_DEFAULT = 0x0000,
-	DEV_PW_USER_SPECIFIED = 0x0001,
-	DEV_PW_MACHINE_SPECIFIED = 0x0002,
-	DEV_PW_REKEY = 0x0003,
-	DEV_PW_PUSHBUTTON = 0x0004,
-	DEV_PW_REGISTRAR_SPECIFIED = 0x0005
-};
-
-/* WPS message flag */
-enum wps_msg_flag {
-	WPS_MSG_FLAG_MORE = 0x01,
-	WPS_MSG_FLAG_LEN = 0x02
-};
-
-/* Message Type */
-enum wps_msg_type {
-	WPS_Beacon = 0x01,
-	WPS_ProbeRequest = 0x02,
-	WPS_ProbeResponse = 0x03,
-	WPS_M1 = 0x04,
-	WPS_M2 = 0x05,
-	WPS_M2D = 0x06,
-	WPS_M3 = 0x07,
-	WPS_M4 = 0x08,
-	WPS_M5 = 0x09,
-	WPS_M6 = 0x0a,
-	WPS_M7 = 0x0b,
-	WPS_M8 = 0x0c,
-	WPS_WSC_ACK = 0x0d,
-	WPS_WSC_NACK = 0x0e,
-	WPS_WSC_DONE = 0x0f
-};
-
-/* Authentication Type Flags */
-#define WPS_WIFI_AUTH_OPEN 0x0001
-#define WPS_AUTH_WPAPSK 0x0002
-#define WPS_AUTH_SHARED 0x0004
-#define WPS_AUTH_WPA 0x0008
-#define WPS_AUTH_WPA2 0x0010
-#define WPS_AUTH_WPA2PSK 0x0020
-#define WPS_AUTH_TYPES (WPS_WIFI_AUTH_OPEN | WPS_AUTH_WPAPSK | WPS_AUTH_SHARED | \
-			WPS_AUTH_WPA | WPS_AUTH_WPA2 | WPS_AUTH_WPA2PSK)
-
-/* Encryption Type Flags */
-#define WPS_ENCR_NONE 0x0001
-#define WPS_ENCR_WEP 0x0002
-#define WPS_ENCR_TKIP 0x0004
-#define WPS_ENCR_AES 0x0008
-#define WPS_ENCR_TYPES (WPS_ENCR_NONE | WPS_ENCR_WEP | WPS_ENCR_TKIP | \
-			WPS_ENCR_AES)
-
-/* Configuration Error */
-enum wps_config_error {
-	WPS_CFG_NO_ERROR = 0,
-	WPS_CFG_OOB_IFACE_READ_ERROR = 1,
-	WPS_CFG_DECRYPTION_CRC_FAILURE = 2,
-	WPS_CFG_24_CHAN_NOT_SUPPORTED = 3,
-	WPS_CFG_50_CHAN_NOT_SUPPORTED = 4,
-	WPS_CFG_SIGNAL_TOO_WEAK = 5,
-	WPS_CFG_NETWORK_AUTH_FAILURE = 6,
-	WPS_CFG_NETWORK_ASSOC_FAILURE = 7,
-	WPS_CFG_NO_DHCP_RESPONSE = 8,
-	WPS_CFG_FAILED_DHCP_CONFIG = 9,
-	WPS_CFG_IP_ADDR_CONFLICT = 10,
-	WPS_CFG_NO_CONN_TO_REGISTRAR = 11,
-	WPS_CFG_MULTIPLE_PBC_DETECTED = 12,
-	WPS_CFG_ROGUE_SUSPECTED = 13,
-	WPS_CFG_DEVICE_BUSY = 14,
-	WPS_CFG_SETUP_LOCKED = 15,
-	WPS_CFG_MSG_TIMEOUT = 16,
-	WPS_CFG_REG_SESS_TIMEOUT = 17,
-	WPS_CFG_DEV_PASSWORD_AUTH_FAILURE = 18
-};
-
-/* Vendor specific Error Indication for WPS event messages */
-enum wps_error_indication {
-	WPS_EI_NO_ERROR,
-	WPS_EI_SECURITY_TKIP_ONLY_PROHIBITED,
-	WPS_EI_SECURITY_WEP_PROHIBITED,
-	NUM_WPS_EI_VALUES
-};
-
-/* RF Bands */
-#define WPS_RF_24GHZ 0x01
-#define WPS_RF_50GHZ 0x02
-
-/* Config Methods */
-#define WPS_CONFIG_USBA 0x0001
-#define WPS_CONFIG_ETHERNET 0x0002
-#define WPS_CONFIG_LABEL 0x0004
-#define WPS_CONFIG_DISPLAY 0x0008
-#define WPS_CONFIG_EXT_NFC_TOKEN 0x0010
-#define WPS_CONFIG_INT_NFC_TOKEN 0x0020
-#define WPS_CONFIG_NFC_INTERFACE 0x0040
-#define WPS_CONFIG_PUSHBUTTON 0x0080
-#define WPS_CONFIG_KEYPAD 0x0100
-#ifdef CONFIG_WPS2
-#define WPS_CONFIG_VIRT_PUSHBUTTON 0x0280
-#define WPS_CONFIG_PHY_PUSHBUTTON 0x0480
-#define WPS_CONFIG_VIRT_DISPLAY 0x2008
-#define WPS_CONFIG_PHY_DISPLAY 0x4008
-#endif /* CONFIG_WPS2 */
-
-/* Connection Type Flags */
-#define WPS_CONN_ESS 0x01
-#define WPS_CONN_IBSS 0x02
-
-/* Wi-Fi Protected Setup State */
-enum wps_state {
-	WPS_STATE_NOT_CONFIGURED = 1,
-	WPS_STATE_CONFIGURED = 2
-};
-
-/* Association State */
-enum wps_assoc_state {
-	WPS_ASSOC_NOT_ASSOC = 0,
-	WPS_ASSOC_CONN_SUCCESS = 1,
-	WPS_ASSOC_CFG_FAILURE = 2,
-	WPS_ASSOC_FAILURE = 3,
-	WPS_ASSOC_IP_FAILURE = 4
-};
-
-
-#define WPS_DEV_OUI_WFA 0x0050f204
-
-enum wps_dev_categ {
-	WPS_DEV_COMPUTER = 1,
-	WPS_DEV_INPUT = 2,
-	WPS_DEV_PRINTER = 3,
-	WPS_DEV_CAMERA = 4,
-	WPS_DEV_STORAGE = 5,
-	WPS_DEV_NETWORK_INFRA = 6,
-	WPS_DEV_DISPLAY = 7,
-	WPS_DEV_MULTIMEDIA = 8,
-	WPS_DEV_GAMING = 9,
-	WPS_DEV_PHONE = 10
-};
-
-enum wps_dev_subcateg {
-	WPS_DEV_COMPUTER_PC = 1,
-	WPS_DEV_COMPUTER_SERVER = 2,
-	WPS_DEV_COMPUTER_MEDIA_CENTER = 3,
-	WPS_DEV_PRINTER_PRINTER = 1,
-	WPS_DEV_PRINTER_SCANNER = 2,
-	WPS_DEV_CAMERA_DIGITAL_STILL_CAMERA = 1,
-	WPS_DEV_STORAGE_NAS = 1,
-	WPS_DEV_NETWORK_INFRA_AP = 1,
-	WPS_DEV_NETWORK_INFRA_ROUTER = 2,
-	WPS_DEV_NETWORK_INFRA_SWITCH = 3,
-	WPS_DEV_DISPLAY_TV = 1,
-	WPS_DEV_DISPLAY_PICTURE_FRAME = 2,
-	WPS_DEV_DISPLAY_PROJECTOR = 3,
-	WPS_DEV_MULTIMEDIA_DAR = 1,
-	WPS_DEV_MULTIMEDIA_PVR = 2,
-	WPS_DEV_MULTIMEDIA_MCX = 3,
-	WPS_DEV_GAMING_XBOX = 1,
-	WPS_DEV_GAMING_XBOX360 = 2,
-	WPS_DEV_GAMING_PLAYSTATION = 3,
-	WPS_DEV_PHONE_WINDOWS_MOBILE = 1
-};
-
-
-/* Request Type */
-enum wps_request_type {
-	WPS_REQ_ENROLLEE_INFO = 0,
-	WPS_REQ_ENROLLEE = 1,
-	WPS_REQ_REGISTRAR = 2,
-	WPS_REQ_WLAN_MANAGER_REGISTRAR = 3
-};
-
-/* Response Type */
-enum wps_response_type {
-	WPS_RESP_ENROLLEE_INFO = 0,
-	WPS_RESP_ENROLLEE = 1,
-	WPS_RESP_REGISTRAR = 2,
-	WPS_RESP_AP = 3
-};
-
-/* Walk Time for push button configuration (in seconds) */
-#define WPS_PBC_WALK_TIME 120
-
-#define WPS_MAX_AUTHORIZED_MACS 5
-
-#define WPS_IGNORE_SEL_REG_MAX_CNT	4
-
-#define WPS_MAX_DIS_AP_NUM	10
-
-#endif /* WPS_DEFS_H */
diff --git a/tools/sdk/include/wpa_supplicant/wps/wps_dev_attr.h b/tools/sdk/include/wpa_supplicant/wps/wps_dev_attr.h
deleted file mode 100644
index 200c9c45adc..00000000000
--- a/tools/sdk/include/wpa_supplicant/wps/wps_dev_attr.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Wi-Fi Protected Setup - device attributes
- * Copyright (c) 2008, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef WPS_DEV_ATTR_H
-#define WPS_DEV_ATTR_H
-
-struct wps_parse_attr;
-
-int wps_build_manufacturer(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_build_model_name(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_build_model_number(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_build_dev_name(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_build_device_attrs(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_build_os_version(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_build_vendor_ext_m1(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_build_rf_bands(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_build_primary_dev_type(struct wps_device_data *dev,
-			       struct wpabuf *msg);
-int wps_build_secondary_dev_type(struct wps_device_data *dev,
-				 struct wpabuf *msg);
-int wps_build_dev_name(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_process_device_attrs(struct wps_device_data *dev,
-			     struct wps_parse_attr *attr);
-int wps_process_os_version(struct wps_device_data *dev, const u8 *ver);
-int wps_process_rf_bands(struct wps_device_data *dev, const u8 *bands);
-void wps_device_data_dup(struct wps_device_data *dst,
-			 const struct wps_device_data *src);
-void wps_device_data_free(struct wps_device_data *dev);
-int wps_build_vendor_ext(struct wps_device_data *dev, struct wpabuf *msg);
-int wps_build_req_dev_type(struct wps_device_data *dev, struct wpabuf *msg,
-			   unsigned int num_req_dev_types,
-			   const u8 *req_dev_types);
-
-#endif /* WPS_DEV_ATTR_H */
diff --git a/tools/sdk/include/wpa_supplicant/wps/wps_i.h b/tools/sdk/include/wpa_supplicant/wps/wps_i.h
deleted file mode 100644
index c20d5ef917c..00000000000
--- a/tools/sdk/include/wpa_supplicant/wps/wps_i.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * Wi-Fi Protected Setup - internal definitions
- * Copyright (c) 2008-2012, Jouni Malinen <j@w1.fi>
- *
- * This software may be distributed under the terms of the BSD license.
- * See README for more details.
- */
-
-#ifndef WPS_I_H
-#define WPS_I_H
-
-#include "wps.h"
-#include "wps_attr_parse.h"
-#include "esp_wifi_crypto_types.h"
-
-#ifdef CONFIG_WPS_NFC
-struct wps_nfc_pw_token;
-#endif
-/**
- * struct wps_data - WPS registration protocol data
- *
- * This data is stored at the EAP-WSC server/peer method and it is kept for a
- * single registration protocol run.
- */
-struct wps_data {
-	/**
-	 * wps - Pointer to long term WPS context
-	 */
-	struct wps_context *wps;
-
-	/**
-	 * registrar - Whether this end is a Registrar
-	 */
-	int registrar;
-
-	/**
-	 * er - Whether the local end is an external registrar
-	 */
-	int er;
-
-	enum {
-		/* Enrollee states */
-		SEND_M1, RECV_M2, SEND_M3, RECV_M4, SEND_M5, RECV_M6, SEND_M7,
-		RECV_M8, RECEIVED_M2D, WPS_MSG_DONE, RECV_ACK, WPS_FINISHED,
-		SEND_WSC_NACK,
-
-		/* Registrar states */
-		RECV_M1, SEND_M2, RECV_M3, SEND_M4, RECV_M5, SEND_M6,
-		RECV_M7, SEND_M8, RECV_DONE, SEND_M2D, RECV_M2D_ACK
-	} state;
-
-	u8 uuid_e[WPS_UUID_LEN];
-	u8 uuid_r[WPS_UUID_LEN];
-	u8 mac_addr_e[ETH_ALEN];
-	u8 nonce_e[WPS_NONCE_LEN];
-	u8 nonce_r[WPS_NONCE_LEN];
-	u8 psk1[WPS_PSK_LEN];
-	u8 psk2[WPS_PSK_LEN];
-	u8 snonce[2 * WPS_SECRET_NONCE_LEN];
-	u8 peer_hash1[WPS_HASH_LEN];
-	u8 peer_hash2[WPS_HASH_LEN];
-
-	struct wpabuf *dh_privkey;
-	struct wpabuf *dh_pubkey_e;
-	struct wpabuf *dh_pubkey_r;
-	u8 authkey[WPS_AUTHKEY_LEN];
-	u8 keywrapkey[WPS_KEYWRAPKEY_LEN];
-	u8 emsk[WPS_EMSK_LEN];
-
-	struct wpabuf *last_msg;
-
-	u8 *dev_password;
-	size_t dev_password_len;
-	u16 dev_pw_id;
-	int pbc;
-
-	/**
-	 * request_type - Request Type attribute from (Re)AssocReq
-	 */
-	u8 request_type;
-
-	/**
-	 * encr_type - Available encryption types
-	 */
-	u16 encr_type;
-
-	/**
-	 * auth_type - Available authentication types
-	 */
-	u16 auth_type;
-
-	u8 *new_psk;
-	size_t new_psk_len;
-
-	int wps_pin_revealed;
-	struct wps_credential cred;
-
-	struct wps_device_data peer_dev;
-
-	/**
-	 * config_error - Configuration Error value to be used in NACK
-	 */
-	u16 config_error;
-	u16 error_indication;
-
-	int ext_reg;
-	int int_reg;
-
-	struct wps_credential *new_ap_settings;
-
-	void *dh_ctx;
-
-	void (*ap_settings_cb)(void *ctx, const struct wps_credential *cred);
-	void *ap_settings_cb_ctx;
-
-	struct wps_credential *use_cred;
-
-	int use_psk_key;
-	u8 p2p_dev_addr[ETH_ALEN]; /* P2P Device Address of the client or
-				    * 00:00:00:00:00:00 if not a P2p client */
-	int pbc_in_m1;
-#ifdef CONFIG_WPS_NFC
-	struct wps_nfc_pw_token *nfc_pw_token;
-#endif
-};
-
-wps_crypto_funcs_t wps_crypto_funcs;
-
-/* wps_common.c */
-void wps_kdf(const u8 *key, const u8 *label_prefix, size_t label_prefix_len,
-	     const char *label, u8 *res, size_t res_len);
-int wps_derive_keys(struct wps_data *wps);
-void wps_derive_psk(struct wps_data *wps, const u8 *dev_passwd,
-		    size_t dev_passwd_len);
-struct wpabuf * wps_decrypt_encr_settings(struct wps_data *wps, const u8 *encr,
-					  size_t encr_len);
-void wps_fail_event(struct wps_context *wps, enum wps_msg_type msg,
-		    u16 config_error, u16 error_indication);
-void wps_success_event(struct wps_context *wps);
-void wps_pwd_auth_fail_event(struct wps_context *wps, int enrollee, int part);
-void wps_pbc_overlap_event(struct wps_context *wps);
-void wps_pbc_timeout_event(struct wps_context *wps);
-
-struct wpabuf * wps_build_wsc_ack(struct wps_data *wps);
-struct wpabuf * wps_build_wsc_nack(struct wps_data *wps);
-
-typedef enum wps_calc_key_mode {
-	WPS_CALC_KEY_NORMAL = 0,
-	WPS_CALC_KEY_NO_CALC,
-	WPS_CALC_KEY_PRE_CALC,
-	WPS_CALC_KEY_MAX,
-} wps_key_mode_t;
-
-/* wps_attr_build.c */
-int wps_build_public_key(struct wps_data *wps, struct wpabuf *msg, wps_key_mode_t mode);
-int wps_build_req_type(struct wpabuf *msg, enum wps_request_type type);
-int wps_build_resp_type(struct wpabuf *msg, enum wps_response_type type);
-int wps_build_config_methods(struct wpabuf *msg, u16 methods);
-int wps_build_uuid_e(struct wpabuf *msg, const u8 *uuid);
-int wps_build_dev_password_id(struct wpabuf *msg, u16 id);
-int wps_build_config_error(struct wpabuf *msg, u16 err);
-int wps_build_authenticator(struct wps_data *wps, struct wpabuf *msg);
-int wps_build_key_wrap_auth(struct wps_data *wps, struct wpabuf *msg);
-int wps_build_encr_settings(struct wps_data *wps, struct wpabuf *msg,
-			    struct wpabuf *plain);
-int wps_build_version(struct wpabuf *msg);
-int wps_build_wfa_ext(struct wpabuf *msg, int req_to_enroll,
-		      const u8 *auth_macs, size_t auth_macs_count);
-int wps_build_msg_type(struct wpabuf *msg, enum wps_msg_type msg_type);
-int wps_build_enrollee_nonce(struct wps_data *wps, struct wpabuf *msg);
-int wps_build_registrar_nonce(struct wps_data *wps, struct wpabuf *msg);
-int wps_build_auth_type_flags(struct wps_data *wps, struct wpabuf *msg);
-int wps_build_encr_type_flags(struct wps_data *wps, struct wpabuf *msg);
-int wps_build_conn_type_flags(struct wps_data *wps, struct wpabuf *msg);
-int wps_build_assoc_state(struct wps_data *wps, struct wpabuf *msg);
-int wps_build_oob_dev_pw(struct wpabuf *msg, u16 dev_pw_id,
-			 const struct wpabuf *pubkey, const u8 *dev_pw,
-			 size_t dev_pw_len);
-struct wpabuf * wps_ie_encapsulate(struct wpabuf *data);
-
-/* wps_attr_process.c */
-int wps_process_authenticator(struct wps_data *wps, const u8 *authenticator,
-			      const struct wpabuf *msg);
-int wps_process_key_wrap_auth(struct wps_data *wps, struct wpabuf *msg,
-			      const u8 *key_wrap_auth);
-int wps_process_cred(struct wps_parse_attr *attr,
-		     struct wps_credential *cred);
-int wps_process_ap_settings(struct wps_parse_attr *attr,
-			    struct wps_credential *cred);
-
-/* wps_enrollee.c */
-struct wpabuf * wps_enrollee_get_msg(struct wps_data *wps,
-				     enum wsc_op_code *op_code);
-enum wps_process_res wps_enrollee_process_msg(struct wps_data *wps,
-					      enum wsc_op_code op_code,
-					      const struct wpabuf *msg);
-
-/* wps_registrar.c */
-struct wpabuf * wps_registrar_get_msg(struct wps_data *wps,
-				      enum wsc_op_code *op_code);
-enum wps_process_res wps_registrar_process_msg(struct wps_data *wps,
-					       enum wsc_op_code op_code,
-					       const struct wpabuf *msg);
-int wps_build_cred(struct wps_data *wps, struct wpabuf *msg);
-int wps_device_store(struct wps_registrar *reg,
-		     struct wps_device_data *dev, const u8 *uuid);
-void wps_registrar_selected_registrar_changed(struct wps_registrar *reg);
-const u8 * wps_authorized_macs(struct wps_registrar *reg, size_t *count);
-int wps_registrar_pbc_overlap(struct wps_registrar *reg,
-			      const u8 *addr, const u8 *uuid_e);
-#ifdef CONFIG_WPS_NFC
-
-void wps_registrar_remove_nfc_pw_token(struct wps_registrar *reg,
-				       struct wps_nfc_pw_token *token);
-#endif
-
-#endif /* WPS_I_H */
diff --git a/tools/sdk/include/xtensa-debug-module/eri.h b/tools/sdk/include/xtensa-debug-module/eri.h
deleted file mode 100644
index 33e4dd09180..00000000000
--- a/tools/sdk/include/xtensa-debug-module/eri.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef ERI_H
-#define ERI_H
-
-#include <stdint.h>
-
-/*
- The ERI is a bus internal to each Xtensa core. It connects, amongst others, to the debug interface, where it
- allows reading/writing the same registers as available over JTAG.
-*/
-
-
-/**
- * @brief  Perform an ERI read
- * @param  addr : ERI register to read from
- *
- * @return Value read
- */
-uint32_t eri_read(int addr);
-
-
-/**
- * @brief  Perform an ERI write
- * @param  addr : ERI register to write to
- * @param  data : Value to write
- *
- * @return Value read
- */
-void eri_write(int addr, uint32_t data);
-
-
-#endif
\ No newline at end of file
diff --git a/tools/sdk/include/xtensa-debug-module/trax.h b/tools/sdk/include/xtensa-debug-module/trax.h
deleted file mode 100644
index c1b3608eb81..00000000000
--- a/tools/sdk/include/xtensa-debug-module/trax.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#include "soc/dport_reg.h"
-#include "sdkconfig.h"
-#include "esp_err.h"
-#include "eri.h"
-#include "xtensa-debug-module.h"
-
-
-typedef enum {
-    TRAX_DOWNCOUNT_WORDS,
-    TRAX_DOWNCOUNT_INSTRUCTIONS
-} trax_downcount_unit_t;
-
-typedef enum {
-    TRAX_ENA_NONE = 0,
-    TRAX_ENA_PRO,
-    TRAX_ENA_APP,
-    TRAX_ENA_PRO_APP,
-    TRAX_ENA_PRO_APP_SWAP
-} trax_ena_select_t;
-
-
-/**
- * @brief  Enable the trax memory blocks to be used as Trax memory.
- *
- * @param  pro_cpu_enable : true if Trax needs to be enabled for the pro CPU
- * @param  app_cpu_enable : true if Trax needs to be enabled for the pro CPU
- * @param  swap_regions : Normally, the pro CPU writes to Trax mem block 0 while
- *                        the app cpu writes to block 1. Setting this to true
- *                        inverts this.
- *
- * @return esp_err_t. Fails with ESP_ERR_NO_MEM if Trax enable is requested for 2 CPUs 
- *                    but memmap only has room for 1, or if Trax memmap is disabled 
- *                    entirely.
- */
-int trax_enable(trax_ena_select_t ena);
-
-/**
- * @brief  Start a Trax trace on the current CPU
- *
- * @param  units_until_stop : Set the units of the delay that gets passed to
- *              trax_trigger_traceend_after_delay. One of TRAX_DOWNCOUNT_WORDS
- *              or TRAX_DOWNCOUNT_INSTRUCTIONS.
- *
- * @return esp_err_t. Fails with ESP_ERR_NO_MEM if Trax is disabled.
- */
-int trax_start_trace(trax_downcount_unit_t units_until_stop);
-
-
-/**
- * @brief  Trigger a Trax trace stop after the indicated delay. If this is called
- *         before and the previous delay hasn't ended yet, this will overwrite
- *         that delay with the new value. The delay will always start at the time
- *         the function is called.
- *
- * @param  delay : The delay to stop the trace in, in the unit indicated to 
- *              trax_start_trace. Note: the trace memory has 4K words available.
- *
- * @return esp_err_t
- */
-int trax_trigger_traceend_after_delay(int delay);
-
-
diff --git a/tools/sdk/include/xtensa-debug-module/xtensa-debug-module.h b/tools/sdk/include/xtensa-debug-module/xtensa-debug-module.h
deleted file mode 100644
index 61b21825314..00000000000
--- a/tools/sdk/include/xtensa-debug-module/xtensa-debug-module.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef XTENSA_DEBUG_MODULE_H
-#define XTENSA_DEBUG_MODULE_H
-
-/*
-ERI registers / OCD offsets and field definitions
-*/
-
-#define ERI_DEBUG_OFFSET 0x100000
-
-#define ERI_TRAX_OFFSET         (ERI_DEBUG_OFFSET+0)
-#define ERI_PERFMON_OFFSET      (ERI_DEBUG_OFFSET+0x1000)
-#define ERI_OCDREG_OFFSET       (ERI_DEBUG_OFFSET+0x2000)
-#define ERI_MISCDBG_OFFSET      (ERI_DEBUG_OFFSET+0x3000)
-#define ERI_CORESIGHT_OFFSET    (ERI_DEBUG_OFFSET+0x3F00)
-
-#define ERI_TRAX_TRAXID         (ERI_TRAX_OFFSET+0x00)
-#define ERI_TRAX_TRAXCTRL       (ERI_TRAX_OFFSET+0x04)
-#define ERI_TRAX_TRAXSTAT       (ERI_TRAX_OFFSET+0x08)
-#define ERI_TRAX_TRAXDATA       (ERI_TRAX_OFFSET+0x0C)
-#define ERI_TRAX_TRAXADDR       (ERI_TRAX_OFFSET+0x10)
-#define ERI_TRAX_TRIGGERPC      (ERI_TRAX_OFFSET+0x14)
-#define ERI_TRAX_PCMATCHCTRL    (ERI_TRAX_OFFSET+0x18)
-#define ERI_TRAX_DELAYCNT       (ERI_TRAX_OFFSET+0x1C)
-#define ERI_TRAX_MEMADDRSTART   (ERI_TRAX_OFFSET+0x20)
-#define ERI_TRAX_MEMADDREND     (ERI_TRAX_OFFSET+0x24)
-
-#define TRAXCTRL_TREN           (1<<0)  //Trace enable. Tracing starts on 0->1
-#define TRAXCTRL_TRSTP          (1<<1)  //Trace Stop. Make 1 to stop trace.
-#define TRAXCTRL_PCMEN          (1<<2)  //PC match enable
-#define TRAXCTRL_PTIEN          (1<<4)  //Processor-trigger enable
-#define TRAXCTRL_CTIEN          (1<<5)  //Cross-trigger enable
-#define TRAXCTRL_TMEN           (1<<7)  //Tracemem Enable. Always set.
-#define TRAXCTRL_CNTU           (1<<9)  //Post-stop-trigger countdown units; selects when DelayCount-- happens.
-                                        //0 - every 32-bit word written to tracemem, 1 - every cpu instruction
-#define TRAXCTRL_TSEN           (1<<11) //Undocumented/deprecated?
-#define TRAXCTRL_SMPER_SHIFT    12      //Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg
-#define TRAXCTRL_SMPER_MASK     0x7     //Synchronization message period
-#define TRAXCTRL_PTOWT          (1<<16) //Processor Trigger Out (OCD halt) enabled when stop triggered
-#define TRAXCTRL_PTOWS          (1<<17) //Processor Trigger Out (OCD halt) enabled when trace stop completes
-#define TRAXCTRL_CTOWT          (1<<20) //Cross-trigger Out enabled when stop triggered
-#define TRAXCTRL_CTOWS          (1<<21) //Cross-trigger Out enabled when trace stop completes
-#define TRAXCTRL_ITCTO          (1<<22) //Integration mode: cross-trigger output
-#define TRAXCTRL_ITCTIA         (1<<23) //Integration mode: cross-trigger ack
-#define TRAXCTRL_ITATV          (1<<24) //replaces ATID when in integration mode: ATVALID output
-#define TRAXCTRL_ATID_MASK      0x7F    //ARB source ID
-#define TRAXCTRL_ATID_SHIFT     24
-#define TRAXCTRL_ATEN           (1<<31) //ATB interface enable
-
-#define TRAXSTAT_TRACT          (1<<0)  //Trace active flag.
-#define TRAXSTAT_TRIG           (1<<1)  //Trace stop trigger. Clears on TREN 1->0
-#define TRAXSTAT_PCMTG          (1<<2)  //Stop trigger caused by PC match. Clears on TREN 1->0
-#define TRAXSTAT_PJTR           (1<<3)  //JTAG transaction result. 1=err in preceding jtag transaction.
-#define TRAXSTAT_PTITG          (1<<4)  //Stop trigger caused by Processor Trigger Input. Clears on TREN 1->0
-#define TRAXSTAT_CTITG          (1<<5)  //Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0
-#define TRAXSTAT_MEMSZ_SHIFT    8       //Traceram size inducator. Usable trace ram is 2^MEMSZ bytes.
-#define TRAXSTAT_MEMSZ_MASK     0x1F
-#define TRAXSTAT_PTO            (1<<16) //Processor Trigger Output: current value
-#define TRAXSTAT_CTO            (1<<17) //Cross-Trigger Output: current value
-#define TRAXSTAT_ITCTOA         (1<<22) //Cross-Trigger Out Ack: current value
-#define TRAXSTAT_ITCTI          (1<<23) //Cross-Trigger Input: current value
-#define TRAXSTAT_ITATR          (1<<24) //ATREADY Input: current value
-
-#define TRAXADDR_TADDR_SHIFT    0       //Trax memory address, in 32-bit words.
-#define TRAXADDR_TADDR_MASK     0x1FFFFF //Actually is only as big as the trace buffer size max addr.
-#define TRAXADDR_TWRAP_SHIFT    21      //Amount of times TADDR has overflown
-#define TRAXADDR_TWRAP_MASK     0x3FF
-#define TRAXADDR_TWSAT          (1<<31) //1 if TWRAP has overflown, clear by disabling tren.
-
-#define PCMATCHCTRL_PCML_SHIFT  0       //Amount of lower bits to ignore in pc trigger register
-#define PCMATCHCTRL_PCML_MASK   0x1F 
-#define PCMATCHCTRL_PCMS        (1<<31) //PC Match Sense, 0 - match when procs PC is in-range, 1 - match when
-                                        //out-of-range
-
-
-#endif
\ No newline at end of file
diff --git a/tools/sdk/ld/esp32.extram.bss.ld b/tools/sdk/ld/esp32.extram.bss.ld
deleted file mode 100644
index 582f6eb6ea2..00000000000
--- a/tools/sdk/ld/esp32.extram.bss.ld
+++ /dev/null
@@ -1,18 +0,0 @@
-/* This section is only included if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
-   is set, to link some sections to BSS in PSRAM */
-
-SECTIONS
-{
-   /* external memory bss, from any global variable with EXT_RAM_ATTR attribute*/
-  .ext_ram.bss (NOLOAD) :
-  {
-    _ext_ram_bss_start = ABSOLUTE(.);
-    *(.ext_ram.bss*)
-    *libnet80211.a:(.dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)
-    *libpp.a:(.dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)
-    *liblwip.a:(.dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)
-    *libbt.a:(EXCLUDE_FILE (libbtdm_app.a) .dynsbss .sbss .sbss.* .gnu.linkonce.sb.* .scommon .sbss2.* .gnu.linkonce.sb2.* .dynbss .bss .bss.* .share.mem .gnu.linkonce.b.* COMMON)
-    . = ALIGN(4);
-    _ext_ram_bss_end = ABSOLUTE(.);
-  } > extern_ram_seg
-}
diff --git a/tools/sdk/ld/esp32.ld b/tools/sdk/ld/esp32.ld
deleted file mode 100644
index 11873b9d357..00000000000
--- a/tools/sdk/ld/esp32.ld
+++ /dev/null
@@ -1,92 +0,0 @@
-/* ESP32 Linker Script Memory Layout
-
-   This file describes the memory layout (memory blocks) as virtual
-   memory addresses.
-
-   esp32.project.ld contains output sections to link compiler output
-   into these memory blocks.
-
-   ***
-
-   This linker script is passed through the C preprocessor to include
-   configuration options.
-
-   Please use preprocessor features sparingly! Restrict
-   to simple macros with numeric values, and/or #if/#endif blocks.
-*/
-#include "sdkconfig.h"
-
-/* If BT is not built at all */
-#ifndef CONFIG_BT_RESERVE_DRAM
-#define CONFIG_BT_RESERVE_DRAM 0
-#endif
-
-MEMORY
-{
-  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
-  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
-  are connected to the data port of the CPU and eg allow bytewise access. */
-
-  /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
-  iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000
-
-  /* Even though the segment name is iram, it is actually mapped to flash
-  */
-  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000-0x18
-
-  /*
-    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
-    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
-    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
-  */
-
-
-  /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
-
-     Enabling Bluetooth & Trace Memory features in menuconfig will decrease
-     the amount of RAM available.
-
-     Note: Length of this section *should* be 0x50000, and this extra DRAM is available
-     in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
-     additional static memory temporarily cannot be used.
-  */
-  dram0_0_seg (RW) :                 org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,
-                                     len = 0x2c200 - CONFIG_BT_RESERVE_DRAM
-
-  /* Flash mapped constant data */
-  drom0_0_seg (R) :                  org = 0x3F400018, len = 0x400000-0x18
-
-  /* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
-
-  /* RTC fast memory (executable). Persists over deep sleep.
-   */
-  rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000
-  
-  /* RTC fast memory (same block as above), viewed from data bus */
-  rtc_data_seg(RW) :                 org = 0x3ff80000, len = 0x2000
-
-  /* RTC slow memory (data accessible). Persists over deep sleep.
-
-     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
-  */
-  rtc_slow_seg(RW)  :                org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
-                                     len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
-
-  /* external memory ,including data and text */
-  extern_ram_seg(RWX)  :             org = 0x3F800000,
-                                     len = 0x400000
-}
-
-/* Heap ends at top of dram0_0_seg */
-_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;
-
-_data_seg_org = ORIGIN(rtc_data_seg);
-
-/* The lines below define location alias for .rtc.data section based on Kconfig option. 
-   When the option is not defined then use slow memory segment 
-   else the data will be placed in fast memory segment */ 
-#ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM
-REGION_ALIAS("rtc_data_location", rtc_slow_seg );
-#else
-REGION_ALIAS("rtc_data_location", rtc_data_seg );
-#endif
diff --git a/tools/sdk/ld/esp32.peripherals.ld b/tools/sdk/ld/esp32.peripherals.ld
deleted file mode 100644
index 2dce0e0fcf7..00000000000
--- a/tools/sdk/ld/esp32.peripherals.ld
+++ /dev/null
@@ -1,32 +0,0 @@
-PROVIDE ( UART0 = 0x3ff40000 );
-PROVIDE ( SPI1 = 0x3ff42000 );
-PROVIDE ( SPI0 = 0x3ff43000 );
-PROVIDE ( GPIO = 0x3ff44000 );
-PROVIDE ( SIGMADELTA = 0x3ff44f00 );
-PROVIDE ( RTCCNTL = 0x3ff48000 );
-PROVIDE ( RTCIO = 0x3ff48400 );
-PROVIDE ( SENS = 0x3ff48800 );
-PROVIDE ( HINF = 0x3ff4B000 );
-PROVIDE ( UHCI1 = 0x3ff4C000 );
-PROVIDE ( I2S0 = 0x3ff4F000 );
-PROVIDE ( UART1 = 0x3ff50000 );
-PROVIDE ( I2C0 = 0x3ff53000 );
-PROVIDE ( UHCI0 = 0x3ff54000 );
-PROVIDE ( HOST = 0x3ff55000 );
-PROVIDE ( RMT = 0x3ff56000 );
-PROVIDE ( RMTMEM = 0x3ff56800 );
-PROVIDE ( PCNT = 0x3ff57000 );
-PROVIDE ( SLC = 0x3ff58000 );
-PROVIDE ( LEDC = 0x3ff59000 );
-PROVIDE ( MCPWM0 = 0x3ff5E000 );
-PROVIDE ( TIMERG0 = 0x3ff5F000 );
-PROVIDE ( TIMERG1 = 0x3ff60000 );
-PROVIDE ( SPI2 = 0x3ff64000 );
-PROVIDE ( SPI3 = 0x3ff65000 );
-PROVIDE ( SYSCON = 0x3ff66000 );
-PROVIDE ( I2C1 = 0x3ff67000 );
-PROVIDE ( SDMMC = 0x3ff68000 );
-PROVIDE ( CAN = 0x3ff6B000 );
-PROVIDE ( MCPWM1 = 0x3ff6C000 );
-PROVIDE ( I2S1 = 0x3ff6D000 );
-PROVIDE ( UART2 = 0x3ff6E000 );
diff --git a/tools/sdk/ld/esp32.project.ld b/tools/sdk/ld/esp32.project.ld
deleted file mode 100644
index 1d3f69734ea..00000000000
--- a/tools/sdk/ld/esp32.project.ld
+++ /dev/null
@@ -1,618 +0,0 @@
-/* Automatically generated file; DO NOT EDIT */
-/* Espressif IoT Development Framework Linker Script */
-/* Generated from: /Users/ficeto/Desktop/ESP32/ESP32/esp-idf-public/components/esp32/ld/esp32.project.ld.in */
-
-/*  Default entry point:  */
-ENTRY(call_start_cpu0);
-
-SECTIONS
-{
-  /* RTC fast memory holds RTC wake stub code,
-     including from any source file named rtc_wake_stub*.c
-  */
-  .rtc.text :
-  {
-    . = ALIGN(4);
-
-    *( .rtc.literal  .rtc.text  .rtc.text.*)
-
-    *rtc_wake_stub*.*(.literal .text .literal.* .text.*)
-    _rtc_text_end = ABSOLUTE(.);
-  } > rtc_iram_seg
-  
-  /*
-    This section is required to skip rtc.text area because rtc_iram_seg and 
-    rtc_data_seg are reflect the same address space on different buses.
-  */
-  .rtc.dummy :
-  {
-    _rtc_dummy_start = ABSOLUTE(.);
-    _rtc_fast_start = ABSOLUTE(.);
-    . = SIZEOF(.rtc.text);
-    _rtc_dummy_end = ABSOLUTE(.);
-  } > rtc_data_seg
-
-  /* This section located in RTC FAST Memory area. 
-     It holds data marked with RTC_FAST_ATTR attribute. 
-     See the file "esp_attr.h" for more information.
-  */
-  .rtc.force_fast :
-  {
-    . = ALIGN(4);
-    _rtc_force_fast_start = ABSOLUTE(.);
-    *(.rtc.force_fast .rtc.force_fast.*)
-    . = ALIGN(4) ;
-    _rtc_force_fast_end = ABSOLUTE(.);
-  } > rtc_data_seg
-
-  /* RTC data section holds RTC wake stub
-     data/rodata, including from any source file
-     named rtc_wake_stub*.c and the data marked with
-     RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
-     The memory location of the data is dependent on 
-     CONFIG_ESP32_RTCDATA_IN_FAST_MEM option.
-  */
-  .rtc.data :
-  {
-    _rtc_data_start = ABSOLUTE(.);
-
-    *( .rtc.data  .rtc.data.*  .rtc.rodata  .rtc.rodata.*)
-
-    *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*)
-    _rtc_data_end = ABSOLUTE(.);
-  } > rtc_data_location
-
-  /* RTC bss, from any source file named rtc_wake_stub*.c */
-  .rtc.bss (NOLOAD) :
-  {
-    _rtc_bss_start = ABSOLUTE(.);
-    *rtc_wake_stub*.*(.bss .bss.*)
-    *rtc_wake_stub*.*(COMMON)
-
-    *( .rtc.bss)
-
-    _rtc_bss_end = ABSOLUTE(.);
-  } > rtc_data_location
-
-  /* This section holds data that should not be initialized at power up 
-     and will be retained during deep sleep.
-     User data marked with RTC_NOINIT_ATTR will be placed
-     into this section. See the file "esp_attr.h" for more information. 
-	 The memory location of the data is dependent on 
-     CONFIG_ESP32_RTCDATA_IN_FAST_MEM option.
-  */
-  .rtc_noinit (NOLOAD):
-  {
-    . = ALIGN(4);
-    _rtc_noinit_start = ABSOLUTE(.);
-    *(.rtc_noinit .rtc_noinit.*)
-    . = ALIGN(4) ;
-    _rtc_noinit_end = ABSOLUTE(.);
-  } > rtc_data_location
-
-  /* This section located in RTC SLOW Memory area. 
-     It holds data marked with RTC_SLOW_ATTR attribute. 
-     See the file "esp_attr.h" for more information.
-  */
-  .rtc.force_slow :
-  {
-    . = ALIGN(4);
-    _rtc_force_slow_start = ABSOLUTE(.);
-    *(.rtc.force_slow .rtc.force_slow.*)
-    . = ALIGN(4) ;
-    _rtc_force_slow_end = ABSOLUTE(.);
-  } > rtc_slow_seg
-
-  /* Get size of rtc slow data based on rtc_data_location alias */
-  _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) 
-                        ? (_rtc_force_slow_end - _rtc_data_start) 
-                        : (_rtc_force_slow_end - _rtc_force_slow_start);
-
-  _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) 
-                        ? (_rtc_force_fast_end - _rtc_fast_start) 
-                        : (_rtc_noinit_end - _rtc_fast_start);
-  
-  ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
-          "RTC_SLOW segment data does not fit.")
-          
-  ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
-          "RTC_FAST segment data does not fit.")
-
-  /* Send .iram0 code to iram */
-  .iram0.vectors :
-  {
-    _iram_start = ABSOLUTE(.);
-    /* Vectors go to IRAM */
-    _init_start = ABSOLUTE(.);
-    /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
-    . = 0x0;
-    KEEP(*(.WindowVectors.text));
-    . = 0x180;
-    KEEP(*(.Level2InterruptVector.text));
-    . = 0x1c0;
-    KEEP(*(.Level3InterruptVector.text));
-    . = 0x200;
-    KEEP(*(.Level4InterruptVector.text));
-    . = 0x240;
-    KEEP(*(.Level5InterruptVector.text));
-    . = 0x280;
-    KEEP(*(.DebugExceptionVector.text));
-    . = 0x2c0;
-    KEEP(*(.NMIExceptionVector.text));
-    . = 0x300;
-    KEEP(*(.KernelExceptionVector.text));
-    . = 0x340;
-    KEEP(*(.UserExceptionVector.text));
-    . = 0x3C0;
-    KEEP(*(.DoubleExceptionVector.text));
-    . = 0x400;
-    *(.*Vector.literal)
-
-    *(.UserEnter.literal);
-    *(.UserEnter.text);
-    . = ALIGN (16);
-    *(.entry.text)
-    *(.init.literal)
-    *(.init)
-    _init_end = ABSOLUTE(.);
-  } > iram0_0_seg
-
-  .iram0.text :
-  {
-    /* Code marked as runnning out of IRAM */
-    _iram_text_start = ABSOLUTE(.);
-
-    *( .iram1  .iram1.*)
-    *libapp_trace.a:( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:creat.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:isatty.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-abs.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-asctime.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-asctime_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-atoi.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-atol.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-bzero.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-close.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-creat.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-ctime.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-ctime_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-ctype_.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-div.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-environ.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-envlock.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-fclose.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-fflush.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-findfp.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-fputwc.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-fvwrite.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-fwalk.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-getenv_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-gettzinfo.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-gmtime.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-gmtime_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-impure.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-isalnum.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-isalpha.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-isascii.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-isblank.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-iscntrl.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-isdigit.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-isgraph.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-islower.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-isprint.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-ispunct.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-isspace.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-isupper.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-itoa.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-labs.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-lcltime.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-lcltime_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-ldiv.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-longjmp.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-makebuf.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-memccpy.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-memchr.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-memcmp.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-memcpy.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-memmove.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-memrchr.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-memset.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-mktime.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-month_lengths.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-open.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-quorem.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-raise.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-rand.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-rand_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-read.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-refill.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-rshift.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-s_fpclassify.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-sbrk.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-sccl.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-setjmp.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-sf_nan.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-srand.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-stdio.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strcasecmp.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strcasestr.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strcat.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strchr.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strcmp.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strcoll.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strcpy.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strcspn.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strdup.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strdup_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strftime.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strlcat.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strlcpy.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strlen.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strlwr.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strncasecmp.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strncat.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strncmp.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strncpy.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strndup.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strndup_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strnlen.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strptime.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strrchr.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strsep.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strspn.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strstr.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strtok_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strtol.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strtoul.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-strupr.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-sysclose.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-sysopen.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-sysread.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-syssbrk.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-system.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-systimes.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-syswrite.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-time.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-timelocal.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-toascii.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-tolower.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-toupper.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-tzcalc_limits.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-tzlock.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-tzset.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-tzset_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-tzvars.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-ungetc.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-utoa.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-wbuf.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-wcrtomb.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-wctomb_r.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lib_a-wsetup.*( .literal  .literal.*  .text  .text.*)
-    *libc-psram-workaround.a:lock.*( .literal  .literal.*  .text  .text.*)
-    *libesp32.a:panic.*( .literal  .literal.*  .text  .text.*)
-    *libesp_ringbuf.a:( .literal  .literal.*  .text  .text.*)
-    *libespcoredump.a:core_dump_common.*( .literal  .literal.*  .text  .text.*)
-    *libespcoredump.a:core_dump_flash.*( .literal  .literal.*  .text  .text.*)
-    *libespcoredump.a:core_dump_port.*( .literal  .literal.*  .text  .text.*)
-    *libespcoredump.a:core_dump_uart.*( .literal  .literal.*  .text  .text.*)
-    *libfreertos.a:( .literal  .literal.*  .text  .text.*)
-    *libgcc.a:lib2funcs.*( .literal  .literal.*  .text  .text.*)
-    *libgcov.a:( .literal  .literal.*  .text  .text.*)
-    *libhal.a:( .literal  .literal.*  .text  .text.*)
-    *libheap.a:multi_heap.*( .literal  .literal.*  .text  .text.*)
-    *libheap.a:multi_heap_poisoning.*( .literal  .literal.*  .text  .text.*)
-    *librtc.a:( .literal  .literal.*  .text  .text.*)
-    *libsoc.a:cpu_util.*( .literal  .literal.*  .text  .text.*)
-    *libsoc.a:rtc_clk.*( .literal  .literal.*  .text  .text.*)
-    *libsoc.a:rtc_clk_init.*( .literal  .literal.*  .text  .text.*)
-    *libsoc.a:rtc_init.*( .literal  .literal.*  .text  .text.*)
-    *libsoc.a:rtc_periph.*( .literal  .literal.*  .text  .text.*)
-    *libsoc.a:rtc_pm.*( .literal  .literal.*  .text  .text.*)
-    *libsoc.a:rtc_sleep.*( .literal  .literal.*  .text  .text.*)
-    *libsoc.a:rtc_time.*( .literal  .literal.*  .text  .text.*)
-    *libsoc.a:rtc_wdt.*( .literal  .literal.*  .text  .text.*)
-    *libspi_flash.a:spi_flash_rom_patch.*( .literal  .literal.*  .text  .text.*)
-    *libxtensa-debug-module.a:eri.*( .literal  .literal.*  .text  .text.*)
-
-    _iram_text_end = ABSOLUTE(.);
-    _iram_end = ABSOLUTE(.);
-  } > iram0_0_seg
-
-  ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
-          "IRAM0 segment data does not fit.")
-
-  .dram0.data :
-  {
-    _data_start = ABSOLUTE(.);
-    _bt_data_start = ABSOLUTE(.);
-    *libbt.a:(.data .data.*)
-    . = ALIGN (4);
-    _bt_data_end = ABSOLUTE(.);
-    _btdm_data_start = ABSOLUTE(.);
-    *libbtdm_app.a:(.data .data.*)
-    . = ALIGN (4);
-    _btdm_data_end = ABSOLUTE(.);
-    *(.gnu.linkonce.d.*)
-    *(.data1)
-    *(.sdata)
-    *(.sdata.*)
-    *(.gnu.linkonce.s.*)
-    *(.sdata2)
-    *(.sdata2.*)
-    *(.gnu.linkonce.s2.*)
-    *(.jcr)
-
-    *( .data  .data.*  .dram1  .dram1.*)
-    *libapp_trace.a:( .rodata  .rodata.*)
-    *libc-psram-workaround.a:creat.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:isatty.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-abs.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-asctime.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-asctime_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-atoi.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-atol.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-bzero.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-close.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-creat.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-ctime.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-ctime_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-ctype_.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-div.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-environ.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-envlock.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-fclose.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-fflush.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-findfp.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-fputwc.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-fvwrite.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-fwalk.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-getenv_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-gettzinfo.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-gmtime.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-gmtime_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-impure.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-isalnum.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-isalpha.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-isascii.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-isblank.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-iscntrl.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-isdigit.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-isgraph.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-islower.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-isprint.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-ispunct.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-isspace.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-isupper.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-itoa.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-labs.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-lcltime.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-lcltime_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-ldiv.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-longjmp.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-makebuf.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-memccpy.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-memchr.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-memcmp.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-memcpy.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-memmove.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-memrchr.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-memset.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-mktime.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-month_lengths.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-open.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-quorem.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-raise.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-rand.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-rand_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-read.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-refill.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-rshift.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-s_fpclassify.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-sbrk.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-sccl.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-setjmp.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-sf_nan.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-srand.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-stdio.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strcasecmp.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strcasestr.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strcat.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strchr.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strcmp.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strcoll.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strcpy.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strcspn.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strdup.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strdup_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strftime.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strlcat.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strlcpy.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strlen.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strlwr.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strncasecmp.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strncat.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strncmp.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strncpy.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strndup.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strndup_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strnlen.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strptime.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strrchr.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strsep.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strspn.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strstr.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strtok_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strtol.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strtoul.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-strupr.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-sysclose.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-sysopen.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-sysread.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-syssbrk.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-system.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-systimes.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-syswrite.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-time.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-timelocal.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-toascii.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-tolower.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-toupper.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-tzcalc_limits.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-tzlock.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-tzset.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-tzset_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-tzvars.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-ungetc.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-utoa.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-wbuf.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-wcrtomb.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-wctomb_r.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lib_a-wsetup.*( .rodata  .rodata.*)
-    *libc-psram-workaround.a:lock.*( .rodata  .rodata.*)
-    *libesp32.a:panic.*( .rodata  .rodata.*)
-    *libgcov.a:( .rodata  .rodata.*)
-    *libheap.a:multi_heap.*( .rodata  .rodata.*)
-    *libheap.a:multi_heap_poisoning.*( .rodata  .rodata.*)
-    *libphy.a:( .rodata  .rodata.*)
-    *libsoc.a:rtc_clk.*( .rodata  .rodata.*)
-
-    _data_end = ABSOLUTE(.);
-    . = ALIGN(4);
-  } > dram0_0_seg
-
-  /*This section holds data that should not be initialized at power up.
-    The section located in Internal SRAM memory region. The macro _NOINIT
-    can be used as attribute to place data into this section.
-    See the esp_attr.h file for more information.
-  */
-  .noinit (NOLOAD):
-  {
-    . = ALIGN(4);
-    _noinit_start = ABSOLUTE(.);
-    *(.noinit .noinit.*) 
-    . = ALIGN(4) ;
-    _noinit_end = ABSOLUTE(.);
-  } > dram0_0_seg
-
-  /* Shared RAM */
-  .dram0.bss (NOLOAD) :
-  {
-    . = ALIGN (8);
-    _bss_start = ABSOLUTE(.);
-    *(.ext_ram.bss*)
-    _bt_bss_start = ABSOLUTE(.);
-    *libbt.a:(.bss .bss.* COMMON)
-    . = ALIGN (4);
-    _bt_bss_end = ABSOLUTE(.);
-    _btdm_bss_start = ABSOLUTE(.);
-    *libbtdm_app.a:(.bss .bss.* COMMON)
-    . = ALIGN (4);
-    _btdm_bss_end = ABSOLUTE(.);
-
-    *( .bss  .bss.*  COMMON)
-
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.share.mem)
-    *(.gnu.linkonce.b.*)
-
-    . = ALIGN (8);
-    _bss_end = ABSOLUTE(.);
-    /* The heap starts right after end of this section */
-    _heap_start = ABSOLUTE(.);
-  } > dram0_0_seg
-
-  ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),
-          "DRAM segment data does not fit.")
-          
-  .flash.rodata :
-  {
-    _rodata_start = ABSOLUTE(.);
-
-    *(.rodata_desc .rodata_desc.*)               /* Should be the first.  App version info.        DO NOT PUT ANYTHING BEFORE IT! */
-    *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */
-
-    *(EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libphy.a *libsoc.a:rtc_clk.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-atol.* *libgcov.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .rodata EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libphy.a *libsoc.a:rtc_clk.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-atol.* *libgcov.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .rodata.*)
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*libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-atol.* *libfreertos.a *libgcov.a *libxtensa-debug-module.a:eri.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .literal EXCLUDE_FILE(*libspi_flash.a:spi_flash_rom_patch.* *libesp_ringbuf.a *libhal.a *libapp_trace.a *libesp32.a:panic.* *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libespcoredump.a:core_dump_uart.* *librtc.a *libgcc.a:lib2funcs.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_sleep.* *libsoc.a:cpu_util.* *libsoc.a:rtc_init.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-atol.* *libfreertos.a *libgcov.a *libxtensa-debug-module.a:eri.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .literal.* EXCLUDE_FILE(*libspi_flash.a:spi_flash_rom_patch.* *libesp_ringbuf.a *libhal.a *libapp_trace.a *libesp32.a:panic.* *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libespcoredump.a:core_dump_uart.* *librtc.a *libgcc.a:lib2funcs.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_sleep.* *libsoc.a:cpu_util.* *libsoc.a:rtc_init.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-atol.* *libfreertos.a *libgcov.a *libxtensa-debug-module.a:eri.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .text EXCLUDE_FILE(*libspi_flash.a:spi_flash_rom_patch.* *libesp_ringbuf.a *libhal.a *libapp_trace.a *libesp32.a:panic.* *libespcoredump.a:core_dump_port.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_flash.* *libespcoredump.a:core_dump_uart.* *librtc.a *libgcc.a:lib2funcs.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_sleep.* *libsoc.a:cpu_util.* *libsoc.a:rtc_init.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-strftime.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-atol.* *libfreertos.a *libgcov.a *libxtensa-debug-module.a:eri.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .text.*  .wifi0iram  .wifi0iram.*  .wifirxiram  .wifirxiram.*)
-
-    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
-    *(.fini.literal)
-    *(.fini)
-    *(.gnu.version)
-    _text_end = ABSOLUTE(.);
-    _etext = .;
-
-    /* Similar to _iram_start, this symbol goes here so it is
-       resolved by addr2line in preference to the first symbol in
-       the flash.text segment.
-    */
-    _flash_cache_start = ABSOLUTE(0);
-  } >iram0_2_seg
-}
diff --git a/tools/sdk/ld/esp32.rom.ld b/tools/sdk/ld/esp32.rom.ld
deleted file mode 100644
index eefa8c5b431..00000000000
--- a/tools/sdk/ld/esp32.rom.ld
+++ /dev/null
@@ -1,1635 +0,0 @@
-/*
-ESP32 ROM address table
-Generated for ROM with MD5sum:
-ab8282ae908fe9e7a63fb2a4ac2df013  ../../rom_image/prorom.elf
-*/
-PROVIDE ( Add2SelfBigHex256 = 0x40015b7c );
-PROVIDE ( AddBigHex256 = 0x40015b28 );
-PROVIDE ( AddBigHexModP256 = 0x40015c98 );
-PROVIDE ( AddP256 = 0x40015c74 );
-PROVIDE ( AddPdiv2_256 = 0x40015ce0 );
-PROVIDE ( app_gpio_arg = 0x3ffe003c );
-PROVIDE ( app_gpio_handler = 0x3ffe0040 );
-PROVIDE ( BasePoint_x_256 = 0x3ff97488 );
-PROVIDE ( BasePoint_y_256 = 0x3ff97468 );
-PROVIDE ( bigHexInversion256 = 0x400168f0 );
-PROVIDE ( bigHexP256 = 0x3ff973bc );
-PROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c );
-PROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 );
-PROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 );
-PROVIDE ( btdm_r_data_init = 0x4001002c );
-PROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 );
-PROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 );
-PROVIDE ( btdm_r_ip_func_p_set = 0x40019afc );
-PROVIDE ( btdm_r_modules_func_p_get = 0x4005427c );
-PROVIDE ( btdm_r_modules_func_p_set = 0x40054270 );
-PROVIDE ( btdm_r_plf_func_p_set = 0x40054288 );
-PROVIDE ( bt_util_buf_env = 0x3ffb8bd4 );
-PROVIDE ( cache_flash_mmu_set_rom = 0x400095e0 );
-PROVIDE ( Cache_Flush_rom = 0x40009a14 );
-PROVIDE ( Cache_Read_Disable_rom = 0x40009ab8 );
-PROVIDE ( Cache_Read_Enable_rom = 0x40009a84 );
-PROVIDE ( Cache_Read_Init_rom = 0x40009950 );
-PROVIDE ( cache_sram_mmu_set_rom = 0x400097f4 );
-/* This is static function, but can be used, not generated by script*/
-PROVIDE ( calc_rtc_memory_crc = 0x40008170 );
-PROVIDE ( calloc = 0x4000bee4 );
-PROVIDE ( __clear_cache = 0x40063860 );
-PROVIDE ( _close_r = 0x4000bd3c );
-PROVIDE ( co_default_bdaddr = 0x3ffae704 );
-PROVIDE ( co_null_bdaddr = 0x3ffb80e0 );
-PROVIDE ( co_sca2ppm = 0x3ff971e8 );
-PROVIDE ( crc16_be = 0x4005d09c );
-PROVIDE ( crc16_le = 0x4005d05c );
-PROVIDE ( crc32_be = 0x4005d024 );
-PROVIDE ( crc32_le = 0x4005cfec );
-PROVIDE ( crc8_be = 0x4005d114 );
-PROVIDE ( crc8_le = 0x4005d0e0 );
-PROVIDE ( _ctype_ = 0x3ff96354 );
-PROVIDE ( __ctype_ptr__ = 0x3ff96350 );
-PROVIDE ( _data_end_rom = 0x4000d5c8 );
-PROVIDE ( _data_end_btdm_rom = 0x4000d4f8 );
-PROVIDE ( _data_start_rom = 0x4000d4f8 );
-PROVIDE ( _data_start_btdm_rom = 0x4000d4f4 );
-PROVIDE ( _data_start_btdm = 0x3ffae6e0);
-PROVIDE ( _data_end_btdm = 0x3ffaff10);
-PROVIDE ( _bss_start_btdm = 0x3ffb8000);
-PROVIDE ( _bss_end_btdm = 0x3ffbff70);
-PROVIDE ( _daylight = 0x3ffae0a4 );
-PROVIDE ( dbg_default_handler = 0x3ff97218 );
-PROVIDE ( dbg_default_state = 0x3ff97220 );
-PROVIDE ( dbg_state = 0x3ffb8d5d );
-PROVIDE ( DebugE256PublicKey_x = 0x3ff97428 );
-PROVIDE ( DebugE256PublicKey_y = 0x3ff97408 );
-PROVIDE ( DebugE256SecretKey = 0x3ff973e8 );
-PROVIDE ( debug_timer = 0x3ffe042c );
-PROVIDE ( debug_timerfn = 0x3ffe0430 );
-PROVIDE ( dh_group14_generator = 0x3ff9ac60 );
-PROVIDE ( dh_group14_prime = 0x3ff9ab60 );
-PROVIDE ( dh_group15_generator = 0x3ff9ab5f );
-PROVIDE ( dh_group15_prime = 0x3ff9a9df );
-PROVIDE ( dh_group16_generator = 0x3ff9a9de );
-PROVIDE ( dh_group16_prime = 0x3ff9a7de );
-PROVIDE ( dh_group17_generator = 0x3ff9a7dd );
-PROVIDE ( dh_group17_prime = 0x3ff9a4dd );
-PROVIDE ( dh_group18_generator = 0x3ff9a4dc );
-PROVIDE ( dh_group18_prime = 0x3ff9a0dc );
-PROVIDE ( dh_group1_generator = 0x3ff9ae03 );
-PROVIDE ( dh_group1_prime = 0x3ff9ada3 );
-PROVIDE ( dh_group2_generator = 0x3ff9ada2 );
-PROVIDE ( dh_group2_prime = 0x3ff9ad22 );
-PROVIDE ( dh_group5_generator = 0x3ff9ad21 );
-PROVIDE ( dh_group5_prime = 0x3ff9ac61 );
-PROVIDE ( g_rom_spiflash_dummy_len_plus = 0x3ffae290 );
-PROVIDE ( ecc_env = 0x3ffb8d60 );
-PROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 );
-PROVIDE ( em_buf_env = 0x3ffb8d74 );
-PROVIDE ( environ = 0x3ffae0b4 );
-PROVIDE ( esp_crc8 = 0x4005d144 );
-PROVIDE ( _etext = 0x4000d66c );
-PROVIDE ( ets_readySet_ = 0x3ffe01f0 );
-PROVIDE ( ets_startup_callback = 0x3ffe0404 );
-PROVIDE ( rwip_coex_cfg = 0x3ff9914c );
-PROVIDE ( rwip_priority = 0x3ff99159 );
-PROVIDE ( exc_cause_table = 0x3ff991d0 );
-PROVIDE ( _exit_r = 0x4000bd28 );
-PROVIDE ( free = 0x4000beb8 );
-PROVIDE ( _fstat_r = 0x4000bccc );
-PROVIDE ( __gcc_bcmp = 0x40064a70 );
-PROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 );
-PROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 );
-PROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c );
-PROVIDE ( _global_impure_ptr = 0x3ffae0b0 );
-PROVIDE ( g_phyFuns_instance = 0x3ffae0c4 );
-PROVIDE ( g_rom_flashchip = 0x3ffae270 );
-PROVIDE ( gTxMsg = 0x3ffe0050 );
-PROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 );
-PROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 );
-PROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c );
-PROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 );
-PROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 );
-PROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c );
-PROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 );
-PROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 );
-PROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 );
-PROVIDE ( hci_command_handler = 0x4004c928 );
-PROVIDE ( hci_env = 0x3ffb9350 );
-PROVIDE ( rwip_env = 0x3ffb8bcc );
-PROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c );
-PROVIDE ( hci_evt_desc_tab = 0x3ff9751c );
-PROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 );
-PROVIDE ( hci_fc_env = 0x3ffb9340 );
-PROVIDE ( jd_decomp = 0x400613e8 );
-PROVIDE ( jd_prepare = 0x40060fa8 );
-PROVIDE ( ke_env = 0x3ffb93cc );
-PROVIDE ( ke_handler_search = 0x4001a430 );
-PROVIDE ( ke_task_env = 0x3ffb81d4 );
-PROVIDE ( lb_default_handler = 0x3ff982b8 );
-PROVIDE ( lb_default_state_tab_p_get = 0x4001c198 );
-PROVIDE ( lb_env = 0x3ffb9424 );
-PROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c );
-PROVIDE ( lb_state = 0x3ffb94e8 );
-PROVIDE ( lc_default_handler = 0x3ff98648 );
-PROVIDE ( lc_default_state_tab_p_get = 0x4002f494 );
-PROVIDE ( lc_env = 0x3ffb94ec );
-PROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 );
-PROVIDE ( lc_state = 0x3ffb9508 );
-PROVIDE ( ld_acl_br_sizes = 0x3ff98a2a );
-PROVIDE ( ld_acl_br_types = 0x3ff98a36 );
-PROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 );
-PROVIDE ( ld_acl_edr_types = 0x3ff98a22 );
-PROVIDE ( ld_env = 0x3ffb9510 );
-PROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c );
-PROVIDE ( ld_sched_params = 0x3ffb96c0 );
-PROVIDE ( ld_sync_train_channels = 0x3ff98a3c );
-PROVIDE ( _link_r = 0x4000bc9c );
-PROVIDE ( llc_default_handler = 0x3ff98b3c );
-PROVIDE ( llc_default_state_tab_p_get = 0x40046058 );
-PROVIDE ( llc_env = 0x3ffb96d0 );
-PROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 );
-PROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 );
-PROVIDE ( llc_hci_command_handler = 0x40042360 );
-PROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 );
-PROVIDE ( llc_state = 0x3ffb96f8 );
-PROVIDE ( lldesc_build_chain = 0x4000a850 );
-PROVIDE ( lldesc_num2link = 0x4000a948 );
-PROVIDE ( lldesc_set_owner = 0x4000a974 );
-PROVIDE ( lld_evt_deferred_elt_push = 0x400466b4 );
-PROVIDE ( lld_evt_deferred_elt_pop = 0x400466dc );
-PROVIDE ( lld_evt_winsize_change = 0x40046730 );
-PROVIDE ( lld_evt_rxwin_compute = 0x400467c8 );
-PROVIDE ( lld_evt_slave_time_compute = 0x40046818 );
-PROVIDE ( lld_evt_env = 0x3ffb9704 );
-PROVIDE ( lld_evt_elt_wait_get = 0x400468e4 );
-PROVIDE ( lld_evt_get_next_free_slot = 0x4004692c );
-PROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 );
-PROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 );
-PROVIDE ( lld_pdu_tx_flush_list = 0x4004a760 );
-PROVIDE ( lld_pdu_pack = 0x4004ab14 );
-PROVIDE ( LLM_AA_CT1 = 0x3ff98d8a );
-PROVIDE ( LLM_AA_CT2 = 0x3ff98d88 );
-PROVIDE ( llm_default_handler = 0x3ff98d80 );
-PROVIDE ( llm_default_state_tab_p_get = 0x4004e718 );
-PROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 );
-PROVIDE ( llm_le_env = 0x3ffb976c );
-PROVIDE ( llm_local_cmds = 0x3ff98d38 );
-PROVIDE ( llm_local_data_len_values = 0x3ff98d1c );
-PROVIDE ( llm_local_le_feats = 0x3ff98d30 );
-PROVIDE ( llm_local_le_states = 0x3ff98d28 );
-PROVIDE ( llm_state = 0x3ffb985c );
-PROVIDE ( lm_default_handler = 0x3ff990e0 );
-PROVIDE ( lm_default_state_tab_p_get = 0x40054268 );
-PROVIDE ( lm_env = 0x3ffb9860 );
-PROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c );
-PROVIDE ( lm_local_supp_feats = 0x3ff990ee );
-PROVIDE ( lm_n_page_tab = 0x3ff990e8 );
-PROVIDE ( lmp_desc_tab = 0x3ff96e6c );
-PROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c );
-PROVIDE ( lm_state = 0x3ffb9a1c );
-PROVIDE ( _lseek_r = 0x4000bd8c );
-PROVIDE ( malloc = 0x4000bea0 );
-PROVIDE ( maxSecretKey_256 = 0x3ff97448 );
-PROVIDE ( __mb_cur_max = 0x3ff96530 );
-PROVIDE ( mmu_init = 0x400095a4 );
-PROVIDE ( __month_lengths = 0x3ff9609c );
-PROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 );
-PROVIDE ( MultiplyBigHexModP256 = 0x400160b8 );
-PROVIDE ( MultiplyByU32ModP256 = 0x40015fdc );
-PROVIDE ( multofup = 0x4000ab8c );
-PROVIDE ( mz_adler32 = 0x4005edbc );
-PROVIDE ( mz_crc32 = 0x4005ee88 );
-PROVIDE ( mz_free = 0x4005eed4 );
-PROVIDE ( notEqual256 = 0x40015b04 );
-PROVIDE ( one_bits = 0x3ff971f8 );
-PROVIDE ( _open_r = 0x4000bd54 );
-PROVIDE ( phy_get_romfuncs = 0x40004100 );
-PROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 );
-PROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c );
-PROVIDE ( r_btdm_option_data = 0x3ffae6e0 );
-PROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 );
-PROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 );
-PROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 );
-PROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 );
-PROVIDE ( r_bt_util_buf_init = 0x400100e4 );
-PROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 );
-PROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec );
-PROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 );
-PROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 );
-PROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 );
-PROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c );
-PROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec );
-PROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 );
-PROVIDE ( r_co_bdaddr_compare = 0x40014324 );
-PROVIDE ( r_co_bytes_to_string = 0x400142e4 );
-PROVIDE ( r_co_list_check_size_available = 0x400142c4 );
-PROVIDE ( r_co_list_extract = 0x4001404c );
-PROVIDE ( r_co_list_extract_after = 0x40014118 );
-PROVIDE ( r_co_list_find = 0x4001419c );
-PROVIDE ( r_co_list_init = 0x40013f14 );
-PROVIDE ( r_co_list_insert_after = 0x40014254 );
-PROVIDE ( r_co_list_insert_before = 0x40014200 );
-PROVIDE ( r_co_list_merge = 0x400141bc );
-PROVIDE ( r_co_list_pool_init = 0x40013f30 );
-PROVIDE ( r_co_list_pop_front = 0x40014028 );
-PROVIDE ( r_co_list_push_back = 0x40013fb8 );
-PROVIDE ( r_co_list_push_front = 0x40013ff4 );
-PROVIDE ( r_co_list_size = 0x400142ac );
-PROVIDE ( r_co_nb_good_channels = 0x40014360 );
-PROVIDE ( r_co_slot_to_duration = 0x40014348 );
-PROVIDE ( r_dbg_init = 0x40014394 );
-PROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 );
-PROVIDE ( r_dbg_swdiag_init = 0x40014470 );
-PROVIDE ( r_dbg_swdiag_read = 0x400144a4 );
-PROVIDE ( r_dbg_swdiag_write = 0x400144d0 );
-PROVIDE ( r_E1 = 0x400108e8 );
-PROVIDE ( r_E21 = 0x40010968 );
-PROVIDE ( r_E22 = 0x400109b4 );
-PROVIDE ( r_E3 = 0x40010a58 );
-PROVIDE ( lm_n192_mod_mul = 0x40011dc0 );
-PROVIDE ( lm_n192_mod_add = 0x40011e9c );
-PROVIDE ( lm_n192_mod_sub = 0x40011eec );
-PROVIDE ( r_ea_alarm_clear = 0x40015ab4 );
-PROVIDE ( r_ea_alarm_set = 0x40015a10 );
-PROVIDE ( _read_r = 0x4000bda8 );
-PROVIDE ( r_ea_elt_cancel = 0x400150d0 );
-PROVIDE ( r_ea_elt_create = 0x40015264 );
-PROVIDE ( r_ea_elt_insert = 0x400152a8 );
-PROVIDE ( r_ea_elt_remove = 0x400154f0 );
-PROVIDE ( r_ea_finetimer_isr = 0x400155d4 );
-PROVIDE ( r_ea_init = 0x40015228 );
-PROVIDE ( r_ea_interval_create = 0x4001555c );
-PROVIDE ( r_ea_interval_delete = 0x400155a8 );
-PROVIDE ( r_ea_interval_duration_req = 0x4001597c );
-PROVIDE ( r_ea_interval_insert = 0x4001557c );
-PROVIDE ( r_ea_interval_remove = 0x40015590 );
-PROVIDE ( ea_conflict_check = 0x40014e9c );
-PROVIDE ( ea_prog_timer = 0x40014f88 );
-PROVIDE ( realloc = 0x4000becc );
-PROVIDE ( r_ea_offset_req = 0x40015748 );
-PROVIDE ( r_ea_sleep_check = 0x40015928 );
-PROVIDE ( r_ea_sw_isr = 0x40015724 );
-PROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 );
-PROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 );
-PROVIDE ( r_ecc_abort_key256_generation = 0x40017070 );
-PROVIDE ( r_ecc_generate_key256 = 0x40016e00 );
-PROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 );
-PROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 );
-PROVIDE ( r_ecc_get_debug_Keys = 0x40017224 );
-PROVIDE ( r_ecc_init = 0x40016dbc );
-PROVIDE ( ecc_point_multiplication_uint8_256 = 0x40016804);
-PROVIDE ( RecvBuff = 0x3ffe009c );
-PROVIDE ( r_em_buf_init = 0x4001729c );
-PROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 );
-PROVIDE ( r_em_buf_rx_free = 0x400173c4 );
-PROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 );
-PROVIDE ( r_em_buf_tx_free = 0x4001741c );
-PROVIDE ( _rename_r = 0x4000bc28 );
-PROVIDE ( r_F1_256 = 0x400133e4 );
-PROVIDE ( r_F2_256 = 0x40013568 );
-PROVIDE ( r_F3_256 = 0x40013664 );
-PROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c );
-PROVIDE ( r_G_256 = 0x40013470 );
-PROVIDE ( r_H3 = 0x40013760 );
-PROVIDE ( r_H4 = 0x40013830 );
-PROVIDE ( r_h4tl_init = 0x40017878 );
-PROVIDE ( r_h4tl_start = 0x40017924 );
-PROVIDE ( r_h4tl_stop = 0x40017934 );
-PROVIDE ( r_h4tl_write = 0x400178d0 );
-PROVIDE ( r_H5 = 0x400138dc );
-PROVIDE ( r_hashConcat = 0x40013a38 );
-PROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c );
-PROVIDE ( r_hci_acl_tx_data_received = 0x40019654 );
-PROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 );
-PROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac );
-PROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c );
-PROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 );
-PROVIDE ( r_hci_cmd_received = 0x400192f8 );
-PROVIDE ( r_hci_evt_filter_add = 0x40018a64 );
-PROVIDE ( r_hci_evt_mask_set = 0x400189e4 );
-PROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 );
-PROVIDE ( r_hci_fc_acl_en = 0x400179d8 );
-PROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c );
-PROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 );
-PROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 );
-PROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c );
-PROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 );
-PROVIDE ( r_hci_fc_init = 0x40017974 );
-PROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 );
-PROVIDE ( r_hci_fc_sync_en = 0x40017a30 );
-PROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 );
-PROVIDE ( r_hci_init = 0x40018538 );
-PROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 );
-PROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 );
-PROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 );
-PROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 );
-PROVIDE ( r_hci_reset = 0x4001856c );
-PROVIDE ( r_hci_send_2_host = 0x400185bc );
-PROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 );
-PROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 );
-PROVIDE ( r_hci_tl_init = 0x40019290 );
-PROVIDE ( r_hci_tl_send = 0x40019228 );
-PROVIDE ( r_hci_util_pack = 0x40019874 );
-PROVIDE ( r_hci_util_unpack = 0x40019998 );
-PROVIDE ( r_hci_voice_settings_get = 0x40018bdc );
-PROVIDE ( r_hci_voice_settings_set = 0x40018be8 );
-PROVIDE ( r_HMAC = 0x40013968 );
-PROVIDE ( r_import_rf_phy_func = 0x3ffb8354 );
-PROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 );
-PROVIDE ( r_ip_funcs = 0x3ffae710 );
-PROVIDE ( r_ip_funcs_p = 0x3ffae70c );
-PROVIDE ( r_ke_check_malloc = 0x40019de0 );
-PROVIDE ( r_ke_event_callback_set = 0x40019ba8 );
-PROVIDE ( r_ke_event_clear = 0x40019c2c );
-PROVIDE ( r_ke_event_flush = 0x40019ccc );
-PROVIDE ( r_ke_event_get = 0x40019c78 );
-PROVIDE ( r_ke_event_get_all = 0x40019cc0 );
-PROVIDE ( r_ke_event_init = 0x40019b90 );
-PROVIDE ( r_ke_event_schedule = 0x40019cdc );
-PROVIDE ( r_ke_event_set = 0x40019be0 );
-PROVIDE ( r_ke_flush = 0x4001a374 );
-PROVIDE ( r_ke_free = 0x4001a014 );
-PROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 );
-PROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 );
-PROVIDE ( r_ke_init = 0x4001a318 );
-PROVIDE ( r_ke_is_free = 0x4001a184 );
-PROVIDE ( r_ke_malloc = 0x40019eb4 );
-PROVIDE ( r_ke_mem_init = 0x40019d3c );
-PROVIDE ( r_ke_mem_is_empty = 0x40019d8c );
-PROVIDE ( r_ke_msg_alloc = 0x4001a1e0 );
-PROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 );
-PROVIDE ( r_ke_msg_discard = 0x4001a850 );
-PROVIDE ( r_ke_msg_forward = 0x4001a290 );
-PROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac );
-PROVIDE ( r_ke_msg_free = 0x4001a2cc );
-PROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 );
-PROVIDE ( r_ke_msg_save = 0x4001a858 );
-PROVIDE ( r_ke_msg_send = 0x4001a234 );
-PROVIDE ( r_ke_msg_send_basic = 0x4001a26c );
-PROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec );
-PROVIDE ( r_ke_queue_extract = 0x40055fd0 );
-PROVIDE ( r_ke_queue_insert = 0x40056020 );
-PROVIDE ( r_ke_sleep_check = 0x4001a3d8 );
-PROVIDE ( r_ke_state_get = 0x4001a7d8 );
-PROVIDE ( r_ke_state_set = 0x4001a6fc );
-PROVIDE ( r_ke_stats_get = 0x4001a3f0 );
-PROVIDE ( r_ke_task_check = 0x4001a8a4 );
-PROVIDE ( r_ke_task_create = 0x4001a674 );
-PROVIDE ( r_ke_task_delete = 0x4001a6c0 );
-PROVIDE ( r_ke_task_init = 0x4001a650 );
-PROVIDE ( r_ke_task_msg_flush = 0x4001a860 );
-PROVIDE ( r_ke_timer_active = 0x4001ac08 );
-PROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 );
-PROVIDE ( r_ke_timer_clear = 0x4001ab90 );
-PROVIDE ( r_ke_timer_init = 0x4001aa9c );
-PROVIDE ( r_ke_timer_set = 0x4001aac0 );
-PROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 );
-PROVIDE ( r_KPrimC = 0x40010ad4 );
-PROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 );
-PROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 );
-PROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 );
-PROVIDE ( r_lb_init = 0x4001acd4 );
-PROVIDE ( r_lb_mst_key = 0x4001afc0 );
-PROVIDE ( r_lb_mst_key_cmp = 0x4001af74 );
-PROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 );
-PROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 );
-PROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c );
-PROVIDE ( r_lb_reset = 0x4001ad38 );
-PROVIDE ( r_lb_send_lmp = 0x4001adbc );
-PROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c );
-PROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 );
-PROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 );
-PROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 );
-PROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c );
-PROVIDE ( r_lc_afh_set = 0x4001cc74 );
-PROVIDE ( r_lc_afh_start = 0x4001d240 );
-PROVIDE ( r_lc_auth_cmp = 0x4001cd54 );
-PROVIDE ( r_lc_calc_link_key = 0x4001ce7c );
-PROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 );
-PROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc );
-PROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac );
-PROVIDE ( r_lc_chk_to = 0x4001d2a8 );
-PROVIDE ( r_lc_cmd_stat_send = 0x4001c914 );
-PROVIDE ( r_lc_comb_key_svr = 0x4001d30c );
-PROVIDE ( r_lc_con_cmp = 0x4001d44c );
-PROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc );
-PROVIDE ( r_lc_conn_seq_done = 0x40021334 );
-PROVIDE ( r_lc_detach = 0x4002037c );
-PROVIDE ( r_lc_dhkey = 0x4001d564 );
-PROVIDE ( r_lc_enc_cmp = 0x4001d8bc );
-PROVIDE ( r_lc_enc_key_refresh = 0x4001d720 );
-PROVIDE ( r_lc_end_chk_colli = 0x4001d858 );
-PROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 );
-PROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 );
-PROVIDE ( r_lc_epr_change_lk = 0x4001db38 );
-PROVIDE ( r_lc_epr_cmp = 0x4001da88 );
-PROVIDE ( r_lc_epr_resp = 0x4001e0b4 );
-PROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 );
-PROVIDE ( r_lc_ext_feat = 0x40020d6c );
-PROVIDE ( r_lc_feat = 0x40020984 );
-PROVIDE ( r_lc_hl_connect = 0x400209e8 );
-PROVIDE ( r_lc_init = 0x4001c948 );
-PROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 );
-PROVIDE ( r_lc_initiator_epr = 0x4001e064 );
-PROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 );
-PROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 );
-PROVIDE ( r_lc_key_exch_end = 0x4001e140 );
-PROVIDE ( r_lc_legacy_pair = 0x4001e1c0 );
-PROVIDE ( r_lc_local_switch = 0x4001e22c );
-PROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 );
-PROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 );
-PROVIDE ( r_lc_loc_auth = 0x40020ecc );
-PROVIDE ( r_lc_locepr_lkref = 0x4001d648 );
-PROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 );
-PROVIDE ( r_lc_loc_sniff = 0x40020a6c );
-PROVIDE ( r_lc_max_slot_mgt = 0x4001e410 );
-PROVIDE ( r_lc_mst_key = 0x4001e7c0 );
-PROVIDE ( r_lc_mst_qos_done = 0x4001ea80 );
-PROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 );
-PROVIDE ( r_lc_mutual_auth_end = 0x4001e670 );
-PROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 );
-PROVIDE ( r_lc_packet_type = 0x40021038 );
-PROVIDE ( r_lc_pair = 0x40020ddc );
-PROVIDE ( r_lc_pairing_cont = 0x4001eafc );
-PROVIDE ( r_lc_passkey_comm = 0x4001ed20 );
-PROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 );
-PROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec );
-PROVIDE ( r_lc_ptt = 0x4001ee2c );
-PROVIDE ( r_lc_ptt_cmp = 0x4001eeec );
-PROVIDE ( r_lc_qos_setup = 0x4001ef50 );
-PROVIDE ( r_lc_rd_rem_name = 0x4001efd0 );
-PROVIDE ( r_lc_release = 0x4001f8a8 );
-PROVIDE ( r_lc_rem_enc = 0x4001f124 );
-PROVIDE ( r_lc_rem_name_cont = 0x4001f290 );
-PROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 );
-PROVIDE ( r_lc_rem_sniff = 0x40020ca4 );
-PROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 );
-PROVIDE ( r_lc_rem_switch = 0x4001f070 );
-PROVIDE ( r_lc_rem_trans_mode = 0x4001f314 );
-PROVIDE ( r_lc_rem_unsniff = 0x400207a0 );
-PROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c );
-PROVIDE ( r_lc_reset = 0x4001c99c );
-PROVIDE ( r_lc_resp_auth = 0x4001f518 );
-PROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 );
-PROVIDE ( r_lc_resp_num_comp = 0x40020074 );
-PROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 );
-PROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c );
-PROVIDE ( r_lc_resp_pair = 0x400208a4 );
-PROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 );
-PROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c );
-PROVIDE ( r_lc_restart_enc = 0x4001f8ec );
-PROVIDE ( r_lc_restart_enc_cont = 0x4001f940 );
-PROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 );
-PROVIDE ( r_lc_restore_to = 0x4001f9e0 );
-PROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 );
-PROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 );
-PROVIDE ( r_lc_rsw_done = 0x4001db94 );
-PROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 );
-PROVIDE ( r_lc_sco_detach = 0x40021e40 );
-PROVIDE ( r_lc_sco_host_accept = 0x40022118 );
-PROVIDE ( r_lc_sco_host_reject = 0x400222b8 );
-PROVIDE ( r_lc_sco_host_request = 0x40021f4c );
-PROVIDE ( r_lc_sco_host_request_disc = 0x4002235c );
-PROVIDE ( r_lc_sco_init = 0x40021dc8 );
-PROVIDE ( r_lc_sco_peer_accept = 0x40022780 );
-PROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 );
-PROVIDE ( r_lc_sco_peer_reject = 0x40022824 );
-PROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c );
-PROVIDE ( r_lc_sco_peer_request = 0x4002240c );
-PROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec );
-PROVIDE ( r_lc_sco_release = 0x40021eec );
-PROVIDE ( r_lc_sco_reset = 0x40021dfc );
-PROVIDE ( r_lc_sco_timeout = 0x40022bd4 );
-PROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec );
-PROVIDE ( r_lc_semi_key_cmp = 0x40020294 );
-PROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c );
-PROVIDE ( r_lc_send_enc_mode = 0x40020220 );
-PROVIDE ( r_lc_send_lmp = 0x4001c1a8 );
-PROVIDE ( r_lc_send_pdu_acc = 0x4001c21c );
-PROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 );
-PROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 );
-PROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 );
-PROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c );
-PROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 );
-PROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 );
-PROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 );
-PROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 );
-PROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 );
-PROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 );
-PROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 );
-PROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec );
-PROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 );
-PROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 );
-PROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c );
-PROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c );
-PROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 );
-PROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec );
-PROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c );
-PROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 );
-PROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 );
-PROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 );
-PROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 );
-PROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 );
-PROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c );
-PROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 );
-PROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 );
-PROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 );
-PROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 );
-PROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 );
-PROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 );
-PROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 );
-PROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 );
-PROVIDE ( r_lc_send_pdu_sres = 0x4001c548 );
-PROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc );
-PROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 );
-PROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 );
-PROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 );
-PROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc );
-PROVIDE ( r_lc_sniff_init = 0x40022cac );
-PROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 );
-PROVIDE ( r_lc_sniff_reset = 0x40022cc8 );
-PROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 );
-PROVIDE ( r_lc_sniff_sub_mode = 0x400204fc );
-PROVIDE ( r_lc_sp_end = 0x400213a8 );
-PROVIDE ( r_lc_sp_fail = 0x40020470 );
-PROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc );
-PROVIDE ( r_lc_ssr_nego = 0x4002125c );
-PROVIDE ( r_lc_start = 0x4001ca28 );
-PROVIDE ( r_lc_start_enc = 0x4001fb28 );
-PROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c );
-PROVIDE ( r_lc_start_key_exch = 0x4001fe10 );
-PROVIDE ( r_lc_start_lmp_to = 0x4001fae8 );
-PROVIDE ( r_lc_start_oob = 0x4001fffc );
-PROVIDE ( r_lc_start_passkey = 0x4001feac );
-PROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 );
-PROVIDE ( r_lc_stop_afh_report = 0x40020184 );
-PROVIDE ( r_lc_stop_enc = 0x40020110 );
-PROVIDE ( r_lc_switch_cmp = 0x40020448 );
-PROVIDE ( r_lc_unit_key_svr = 0x400206d8 );
-PROVIDE ( r_lc_unsniff = 0x40020c50 );
-PROVIDE ( r_lc_unsniff_cmp = 0x40020810 );
-PROVIDE ( r_lc_unsniff_cont = 0x40020750 );
-PROVIDE ( r_lc_upd_to = 0x4002065c );
-PROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 );
-PROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac );
-PROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 );
-PROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c );
-PROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 );
-PROVIDE ( r_lc_version = 0x40020a30 );
-PROVIDE ( lc_set_encap_pdu_data_p192 = 0x4002e4c8 );
-PROVIDE ( lc_set_encap_pdu_data_p256 = 0x4002e454 );
-PROVIDE ( lm_get_auth_method = 0x40023420);
-PROVIDE ( lmp_accepted_ext_handler = 0x40027290 );
-PROVIDE ( lmp_not_accepted_ext_handler = 0x40029c54 );
-PROVIDE ( lmp_clk_adj_handler = 0x40027468 );
-PROVIDE ( lmp_clk_adj_ack_handler = 0x400274f4 );
-PROVIDE ( lm_get_auth_method = 0x40023420);
-PROVIDE ( lmp_accepted_ext_handler = 0x40027290 );
-PROVIDE ( lmp_not_accepted_ext_handler = 0x40029c54 );
-PROVIDE ( lmp_clk_adj_handler = 0x40027468 );
-PROVIDE ( lmp_clk_adj_ack_handler = 0x400274f4 );
-PROVIDE ( lmp_clk_adj_req_handler = 0x4002751c );
-PROVIDE ( lmp_feats_res_ext_handler = 0x4002cac4 );
-PROVIDE ( lmp_feats_req_ext_handler = 0x4002ccb0 );
-PROVIDE ( lmp_pkt_type_tbl_req_handler = 0x40027574 );
-PROVIDE ( lmp_esco_link_req_handler = 0x40027610 );
-PROVIDE ( lmp_rmv_esco_link_req_handler = 0x400276e8 );
-PROVIDE ( lmp_ch_class_req_handler = 0x40027730 );
-PROVIDE ( lmp_ch_class_handler = 0x4002ca18 );
-PROVIDE ( lmp_ssr_req_handler = 0x4002780c );
-PROVIDE ( lmp_ssr_res_handler = 0x40027900 );
-PROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );
-PROVIDE ( lmp_pause_enc_req_handler = 0x4002df90 );
-PROVIDE ( lmp_resume_enc_req_handler = 0x4002e084 );
-PROVIDE ( lmp_num_comparison_fail_handler = 0x40027a74 );
-PROVIDE ( lmp_passkey_fail_handler = 0x40027aec );
-PROVIDE ( lmp_keypress_notif_handler = 0x4002c5c8 );
-PROVIDE ( lmp_pwr_ctrl_req_handler = 0x400263bc );
-PROVIDE ( lmp_pwr_ctrl_res_handler = 0x40026480 );
-PROVIDE ( lmp_auto_rate_handler = 0x40026548 );
-PROVIDE ( lmp_pref_rate_handler = 0x4002657c );
-PROVIDE ( lmp_name_req_handler = 0x40025050 );
-PROVIDE ( lmp_name_res_handler = 0x400250bc );
-PROVIDE ( lmp_not_accepted_handler = 0x400251d0 );
-PROVIDE ( lmp_accepted_handler = 0x4002e894 );
-PROVIDE ( lmp_clk_off_req_handler = 0x40025a44 );
-PROVIDE ( lmp_clk_off_res_handler = 0x40025ab8 );
-PROVIDE ( lmp_detach_handler = 0x40025b74 );
-PROVIDE ( lmp_tempkey_handler = 0x4002b6b0 );
-PROVIDE ( lmp_temprand_handler = 0x4002b74c );
-PROVIDE ( lmp_sres_handler = 0x4002b840 );
-PROVIDE ( lmp_aurand_handler = 0x4002bda0 );
-PROVIDE ( lmp_unitkey_handler = 0x4002c13c );
-PROVIDE ( lmp_combkey_handler = 0x4002c234 );
-PROVIDE ( lmp_inrand_handler = 0x4002c414 );
-PROVIDE ( lmp_oob_fail_handler = 0x40027b84 );
-PROVIDE ( lmp_ping_req_handler = 0x40027c08 );
-PROVIDE ( lmp_ping_res_handler = 0x40027c5c );
-PROVIDE ( lmp_enc_mode_req_handler = 0x40025c60 );
-PROVIDE ( lmp_enc_key_size_req_handler = 0x40025e54 );
-PROVIDE ( lmp_switch_req_handler = 0x40025f84 );
-PROVIDE ( lmp_start_enc_req_handler = 0x4002e124 );
-PROVIDE ( lmp_stop_enc_req_handler = 0x4002de30 );
-PROVIDE ( lmp_sniff_req_handler = 0x400260c8 );
-PROVIDE ( lmp_unsniff_req_handler = 0x400261e0 );
-PROVIDE ( lmp_incr_pwr_req_handler = 0x4002629c );
-PROVIDE ( lmp_decr_pwr_req_handler = 0x400262f8 );
-PROVIDE ( lmp_max_pwr_handler = 0x40026354 );
-PROVIDE ( lmp_min_pwr_handler = 0x40026388 );
-PROVIDE ( lmp_ver_req_handler = 0x400265f0 );
-PROVIDE ( lmp_ver_res_handler = 0x40026670 );
-PROVIDE ( lmp_qos_handler = 0x40026790 );
-PROVIDE ( lmp_qos_req_handler = 0x40026844 );
-PROVIDE ( lmp_sco_link_req_handler = 0x40026930 );
-PROVIDE ( lmp_rmv_sco_link_req_handler = 0x40026a10 );
-PROVIDE ( lmp_max_slot_handler = 0x40026a54 );
-PROVIDE ( lmp_max_slot_req_handler = 0x40026aac );
-PROVIDE ( lmp_timing_accu_req_handler = 0x40026b54 );
-PROVIDE ( lmp_timing_accu_res_handler = 0x40026bcc );
-PROVIDE ( lmp_setup_cmp_handler = 0x40026c84 );
-PROVIDE ( lmp_feats_res_handler = 0x4002b548 );
-PROVIDE ( lmp_feats_req_handler = 0x4002b620 );
-PROVIDE ( lmp_host_con_req_handler = 0x4002b3d8 );
-PROVIDE ( lmp_use_semi_perm_key_handler = 0x4002b4c4 );
-PROVIDE ( lmp_slot_off_handler = 0x40026cc8 );
-PROVIDE ( lmp_page_mode_req_handler = 0x40026d0c );
-PROVIDE ( lmp_page_scan_mode_req_handler = 0x40026d4c );
-PROVIDE ( lmp_supv_to_handler = 0x40026d94 );
-PROVIDE ( lmp_test_activate_handler = 0x40026e7c );
-PROVIDE ( lmp_test_ctrl_handler = 0x40026ee4 );
-PROVIDE ( lmp_enc_key_size_mask_req_handler = 0x40027038 );
-PROVIDE ( lmp_enc_key_size_mask_res_handler = 0x400270a4 );
-PROVIDE ( lmp_set_afh_handler = 0x4002b2e4 );
-PROVIDE ( lmp_encaps_hdr_handler = 0x40027120 );
-PROVIDE ( lmp_encaps_payl_handler = 0x4002e590 );
-PROVIDE ( lmp_sp_nb_handler = 0x4002acf0 );
-PROVIDE ( lmp_sp_cfm_handler = 0x4002b170 );
-PROVIDE ( lmp_dhkey_chk_handler = 0x4002ab48 );
-PROVIDE ( lmp_pause_enc_aes_req_handler = 0x400279a4 );
-PROVIDE ( lmp_io_cap_res_handler = 0x4002c670 );
-PROVIDE ( lmp_io_cap_req_handler = 0x4002c7a4 );
-PROVIDE ( lc_cmd_cmp_bd_addr_send = 0x4002cec4 );
-PROVIDE ( ld_acl_tx_packet_type_select = 0x4002fb40 );
-PROVIDE ( ld_acl_sched = 0x40033268 );
-PROVIDE ( ld_acl_sniff_sched = 0x4003340c );
-PROVIDE ( ld_acl_rx = 0x4003274c );
-PROVIDE ( ld_acl_tx = 0x4002ffdc );
-PROVIDE ( ld_acl_rx_sync = 0x4002fbec );
-PROVIDE ( ld_acl_rx_sync2 = 0x4002fd8c );
-PROVIDE ( ld_acl_rx_no_sync = 0x4002fe78 );
-PROVIDE ( ld_acl_clk_isr = 0x40030cf8 );
-PROVIDE ( ld_acl_rsw_frm_cbk = 0x40033bb0 );
-PROVIDE ( ld_sco_modify = 0x40031778 );
-PROVIDE ( lm_cmd_cmp_send = 0x40051838 );
-PROVIDE ( ld_sco_frm_cbk = 0x400349dc );
-PROVIDE ( ld_acl_sniff_frm_cbk = 0x4003482c );
-PROVIDE ( ld_inq_end = 0x4003ab48 );
-PROVIDE ( ld_inq_sched = 0x4003aba4 );
-PROVIDE ( ld_inq_frm_cbk = 0x4003ae4c );
-PROVIDE ( ld_pscan_frm_cbk = 0x4003ebe4 );
-PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 );
-PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 );
-PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 );
-PROVIDE ( r_ld_acl_afh_set = 0x40036b60 );
-PROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 );
-PROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 );
-PROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 );
-PROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 );
-PROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 );
-PROVIDE ( r_ld_acl_clk_set = 0x40036950 );
-PROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 );
-PROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 );
-PROVIDE ( r_ld_acl_data_flush = 0x400357bc );
-PROVIDE ( r_ld_acl_data_tx = 0x4003544c );
-PROVIDE ( r_ld_acl_edr_set = 0x4003678c );
-PROVIDE ( r_ld_acl_enc_key_load = 0x40036404 );
-PROVIDE ( r_ld_acl_flow_off = 0x40035400 );
-PROVIDE ( r_ld_acl_flow_on = 0x4003541c );
-PROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c );
-PROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 );
-PROVIDE ( r_ld_acl_init = 0x40034d08 );
-PROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 );
-PROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 );
-PROVIDE ( r_ld_acl_lsto_get = 0x400366b4 );
-PROVIDE ( r_ld_acl_lsto_set = 0x400366f8 );
-PROVIDE ( r_ld_acl_reset = 0x40034d24 );
-PROVIDE ( r_ld_acl_role_get = 0x40036b30 );
-PROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 );
-PROVIDE ( r_ld_acl_rsw_req = 0x40035e74 );
-PROVIDE ( r_ld_acl_rx_enc = 0x40036344 );
-PROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 );
-PROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 );
-PROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c );
-PROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 );
-PROVIDE ( r_ld_acl_sniff = 0x4003617c );
-PROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 );
-PROVIDE ( r_ld_acl_ssr_set = 0x40036274 );
-PROVIDE ( r_ld_acl_start = 0x40034ddc );
-PROVIDE ( r_ld_acl_stop = 0x4003532c );
-PROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 );
-PROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c );
-PROVIDE ( r_ld_acl_t_poll_get = 0x40036024 );
-PROVIDE ( r_ld_acl_t_poll_set = 0x40036068 );
-PROVIDE ( r_ld_acl_tx_enc = 0x400362f8 );
-PROVIDE ( ld_acl_frm_cbk = 0x40034414 );
-PROVIDE ( ld_acl_rsw_end = 0x40032bc0 );
-PROVIDE ( ld_acl_end = 0x40033140 );
-PROVIDE ( ld_acl_resched = 0x40033814 );
-PROVIDE ( ld_acl_test_mode_update = 0x40032050 );
-PROVIDE ( r_ld_acl_unsniff = 0x400361e0 );
-PROVIDE ( r_ld_active_check = 0x4003cac4 );
-PROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec );
-PROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c );
-PROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 );
-PROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc );
-PROVIDE ( r_ld_bcst_acl_start = 0x4003882c );
-PROVIDE ( r_ld_bcst_afh_update = 0x40038f3c );
-PROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c );
-PROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 );
-PROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 );
-PROVIDE ( r_ld_bd_addr_get = 0x4003ca20 );
-PROVIDE ( r_ld_channel_assess = 0x4003c184 );
-PROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 );
-PROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 );
-PROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 );
-PROVIDE ( r_ld_csb_rx_init = 0x40039690 );
-PROVIDE ( r_ld_csb_rx_reset = 0x4003969c );
-PROVIDE ( r_ld_csb_rx_start = 0x4003972c );
-PROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 );
-PROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc );
-PROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c );
-PROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 );
-PROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 );
-PROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 );
-PROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 );
-PROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 );
-PROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 );
-PROVIDE ( r_ld_fm_frame_isr = 0x4003a82c );
-PROVIDE ( r_ld_fm_init = 0x4003a760 );
-PROVIDE ( r_ld_fm_prog_check = 0x4003ab28 );
-PROVIDE ( r_ld_fm_prog_disable = 0x4003a984 );
-PROVIDE ( r_ld_fm_prog_enable = 0x4003a944 );
-PROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 );
-PROVIDE ( r_ld_fm_reset = 0x4003a794 );
-PROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 );
-PROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 );
-PROVIDE ( r_ld_init = 0x4003c294 );
-PROVIDE ( r_ld_inq_init = 0x4003b15c );
-PROVIDE ( r_ld_inq_reset = 0x4003b168 );
-PROVIDE ( r_ld_inq_start = 0x4003b1f0 );
-PROVIDE ( r_ld_inq_stop = 0x4003b4f0 );
-PROVIDE ( r_ld_iscan_eir_get = 0x4003c118 );
-PROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 );
-PROVIDE ( r_ld_iscan_init = 0x4003b9f0 );
-PROVIDE ( r_ld_iscan_reset = 0x4003ba14 );
-PROVIDE ( r_ld_iscan_restart = 0x4003ba44 );
-PROVIDE ( r_ld_iscan_start = 0x4003bb28 );
-PROVIDE ( r_ld_iscan_stop = 0x4003bf1c );
-PROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 );
-PROVIDE ( r_ld_page_init = 0x4003d808 );
-PROVIDE ( r_ld_page_reset = 0x4003d814 );
-PROVIDE ( r_ld_page_start = 0x4003d848 );
-PROVIDE ( r_ld_page_stop = 0x4003da54 );
-PROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 );
-PROVIDE ( r_ld_pca_init = 0x4003deb4 );
-PROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac );
-PROVIDE ( r_ld_pca_local_config = 0x4003df6c );
-PROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 );
-PROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 );
-PROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 );
-PROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 );
-PROVIDE ( r_ld_pca_reset = 0x4003df0c );
-PROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 );
-PROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 );
-PROVIDE ( r_ld_pscan_init = 0x4003f474 );
-PROVIDE ( r_ld_pscan_reset = 0x4003f498 );
-PROVIDE ( r_ld_pscan_restart = 0x4003f4b8 );
-PROVIDE ( r_ld_pscan_start = 0x4003f514 );
-PROVIDE ( r_ld_pscan_stop = 0x4003f618 );
-PROVIDE ( r_ld_read_clock = 0x4003c9e4 );
-PROVIDE ( r_ld_reset = 0x4003c714 );
-PROVIDE ( r_ld_sched_acl_add = 0x4003f978 );
-PROVIDE ( r_ld_sched_acl_remove = 0x4003f99c );
-PROVIDE ( r_ld_sched_compute = 0x4003f6f8 );
-PROVIDE ( r_ld_sched_init = 0x4003f7ac );
-PROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 );
-PROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 );
-PROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 );
-PROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 );
-PROVIDE ( r_ld_sched_page_add = 0x4003f910 );
-PROVIDE ( r_ld_sched_page_remove = 0x4003f938 );
-PROVIDE ( r_ld_sched_pscan_add = 0x4003f828 );
-PROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 );
-PROVIDE ( r_ld_sched_reset = 0x4003f7d4 );
-PROVIDE ( r_ld_sched_sco_add = 0x4003fa4c );
-PROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c );
-PROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 );
-PROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c );
-PROVIDE ( r_ld_sched_sscan_add = 0x4003f868 );
-PROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 );
-PROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 );
-PROVIDE ( r_ld_sco_data_tx = 0x40037ee8 );
-PROVIDE ( r_ld_sco_start = 0x40037110 );
-PROVIDE ( r_ld_sco_stop = 0x40037c40 );
-PROVIDE ( r_ld_sco_update = 0x40037a74 );
-PROVIDE ( r_ld_sscan_activated = 0x4004031c );
-PROVIDE ( r_ld_sscan_init = 0x400402f0 );
-PROVIDE ( r_ld_sscan_reset = 0x400402fc );
-PROVIDE ( r_ld_sscan_start = 0x40040384 );
-PROVIDE ( r_ld_strain_init = 0x400409f4 );
-PROVIDE ( r_ld_strain_reset = 0x40040a00 );
-PROVIDE ( r_ld_strain_start = 0x40040a8c );
-PROVIDE ( r_ld_strain_stop = 0x40040df0 );
-PROVIDE ( r_ld_timing_accuracy_get = 0x4003caac );
-PROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c );
-PROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 );
-PROVIDE ( r_ld_util_bch_create = 0x40040fcc );
-PROVIDE ( r_ld_util_fhs_pk = 0x400411c8 );
-PROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 );
-PROVIDE ( r_ld_util_stp_pk = 0x400413f4 );
-PROVIDE ( r_ld_util_stp_unpk = 0x40041324 );
-PROVIDE ( r_ld_version_get = 0x4003ca6c );
-PROVIDE ( r_ld_wlcoex_set = 0x4003caf8 );
-PROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 );
-PROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c );
-PROVIDE ( r_llc_ch_assess_local = 0x40041494 );
-PROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 );
-PROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 );
-PROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac );
-PROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 );
-PROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c );
-PROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 );
-PROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c );
-PROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 );
-PROVIDE ( r_llc_con_update_complete_send = 0x40044d68 );
-PROVIDE ( r_llc_con_update_finished = 0x4004518c );
-PROVIDE ( r_llc_con_update_ind = 0x40045038 );
-PROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 );
-PROVIDE ( r_llc_end_evt_defer = 0x40046330 );
-PROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c );
-PROVIDE ( r_llc_init = 0x40044778 );
-PROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 );
-PROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 );
-PROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc );
-PROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 );
-PROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 );
-PROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 );
-PROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 );
-PROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 );
-PROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 );
-PROVIDE ( r_llc_llcp_get_autorize = 0x4004475c );
-PROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 );
-PROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac );
-PROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 );
-PROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 );
-PROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c );
-PROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 );
-PROVIDE ( r_llc_llcp_recv_handler = 0x40044678 );
-PROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c );
-PROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c );
-PROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 );
-PROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 );
-PROVIDE ( r_llc_llcp_tester_send = 0x400445e4 );
-PROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 );
-PROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c );
-PROVIDE ( r_llc_lsto_con_update = 0x40045098 );
-PROVIDE ( r_llc_ltk_req_send = 0x40044dc0 );
-PROVIDE ( r_llc_map_update_finished = 0x40045260 );
-PROVIDE ( r_llc_map_update_ind = 0x400450f0 );
-PROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc );
-PROVIDE ( r_llc_pdu_defer = 0x40046528 );
-PROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac );
-PROVIDE ( r_llc_reset = 0x400447b8 );
-PROVIDE ( r_llc_start = 0x400447f4 );
-PROVIDE ( r_llc_stop = 0x400449ac );
-PROVIDE ( r_llc_util_bw_mgt = 0x4004629c );
-PROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 );
-PROVIDE ( r_llc_util_dicon_procedure = 0x40046130 );
-PROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 );
-PROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 );
-PROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 );
-PROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 );
-PROVIDE ( r_llc_util_update_channel_map = 0x400461ac );
-PROVIDE ( r_llc_version_rd_event_send = 0x40044e60 );
-PROVIDE ( r_lld_adv_start = 0x40048b38 );
-PROVIDE ( r_lld_adv_stop = 0x40048ea0 );
-PROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 );
-PROVIDE ( r_lld_con_param_req = 0x40049f0c );
-PROVIDE ( r_lld_con_param_rsp = 0x40049e00 );
-PROVIDE ( r_lld_con_start = 0x400491f8 );
-PROVIDE ( r_lld_con_stop = 0x40049fdc );
-PROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc );
-PROVIDE ( r_lld_con_update_ind = 0x4004a30c );
-PROVIDE ( r_lld_con_update_req = 0x40049b60 );
-PROVIDE ( r_lld_core_reset = 0x40048a9c );
-PROVIDE ( r_lld_crypt_isr = 0x4004a324 );
-PROVIDE ( r_lld_evt_adv_create = 0x400481f4 );
-PROVIDE ( r_lld_evt_canceled = 0x400485c8 );
-PROVIDE ( r_lld_evt_channel_next = 0x40046aac );
-PROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc );
-PROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 );
-PROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c );
-PROVIDE ( r_lld_evt_drift_compute = 0x40047670 );
-PROVIDE ( r_lld_evt_elt_delete = 0x40047538 );
-PROVIDE ( r_lld_evt_elt_insert = 0x400474c8 );
-PROVIDE ( r_lld_evt_end = 0x400483e8 );
-PROVIDE ( r_lld_evt_end_isr = 0x4004862c );
-PROVIDE ( r_lld_evt_init = 0x40046b3c );
-PROVIDE ( r_lld_evt_init_evt = 0x40046cd0 );
-PROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 );
-PROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 );
-PROVIDE ( r_lld_evt_prevent_stop = 0x40047adc );
-PROVIDE ( r_lld_evt_restart = 0x40046d50 );
-PROVIDE ( r_lld_evt_rx = 0x40048578 );
-PROVIDE ( r_lld_evt_rx_isr = 0x40048678 );
-PROVIDE ( r_lld_evt_scan_create = 0x40047ae8 );
-PROVIDE ( r_lld_evt_schedule = 0x40047908 );
-PROVIDE ( r_lld_evt_schedule_next = 0x400477dc );
-PROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 );
-PROVIDE ( r_lld_evt_slave_update = 0x40048138 );
-PROVIDE ( r_lld_evt_update_create = 0x40047cd8 );
-PROVIDE ( r_lld_get_mode = 0x40049ff8 );
-PROVIDE ( r_lld_init = 0x4004873c );
-PROVIDE ( r_lld_move_to_master = 0x400499e0 );
-PROVIDE ( r_lld_move_to_slave = 0x4004a024 );
-PROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 );
-PROVIDE ( r_lld_pdu_check = 0x4004ac34 );
-PROVIDE ( r_lld_pdu_data_send = 0x4004b018 );
-PROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc );
-PROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 );
-PROVIDE ( r_lld_pdu_send_packet = 0x4004b774 );
-PROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 );
-PROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 );
-PROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 );
-PROVIDE ( r_lld_pdu_tx_push = 0x4004b080 );
-PROVIDE ( r_lld_ral_renew_req = 0x4004a73c );
-PROVIDE ( r_lld_scan_start = 0x40048ee0 );
-PROVIDE ( r_lld_scan_stop = 0x40049190 );
-PROVIDE ( r_lld_test_mode_rx = 0x4004a540 );
-PROVIDE ( r_lld_test_mode_tx = 0x4004a350 );
-PROVIDE ( r_lld_test_stop = 0x4004a710 );
-PROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc );
-PROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c );
-PROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 );
-PROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 );
-PROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 );
-PROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 );
-PROVIDE ( r_lld_util_flush_list = 0x4004bbd8 );
-PROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 );
-PROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac );
-PROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 );
-PROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 );
-PROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 );
-PROVIDE ( r_lld_util_instant_get = 0x4004b890 );
-PROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc );
-PROVIDE ( r_lld_util_priority_set = 0x4004bd10 );
-PROVIDE ( r_lld_util_priority_update = 0x4004bd78 );
-PROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 );
-PROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 );
-PROVIDE ( r_lld_wlcoex_set = 0x4004bd98 );
-PROVIDE ( r_llm_ble_ready = 0x4004cc34 );
-PROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 );
-PROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 );
-PROVIDE ( r_llm_con_req_ind = 0x4004cc54 );
-PROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 );
-PROVIDE ( r_llm_create_con = 0x4004de78 );
-PROVIDE ( r_llm_encryption_done = 0x4004dff8 );
-PROVIDE ( r_llm_encryption_start = 0x4004e128 );
-PROVIDE ( r_llm_end_evt_defer = 0x4004eb6c );
-PROVIDE ( r_llm_init = 0x4004c9f8 );
-PROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 );
-PROVIDE ( r_llm_pdu_defer = 0x4004ec48 );
-PROVIDE ( r_llm_ral_clear = 0x4004e1fc );
-PROVIDE ( r_llm_ral_dev_add = 0x4004e23c );
-PROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc );
-PROVIDE ( r_llm_ral_get_rpa = 0x4004e400 );
-PROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 );
-PROVIDE ( r_llm_ral_update = 0x4004e4f8 );
-PROVIDE ( r_llm_set_adv_data = 0x4004d960 );
-PROVIDE ( r_llm_set_adv_en = 0x4004d7ec );
-PROVIDE ( r_llm_set_adv_param = 0x4004d5f4 );
-PROVIDE ( r_llm_set_scan_en = 0x4004db64 );
-PROVIDE ( r_llm_set_scan_param = 0x4004dac8 );
-PROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 );
-PROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 );
-PROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc );
-PROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc );
-PROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 );
-PROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 );
-PROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 );
-PROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 );
-PROVIDE ( r_llm_util_bl_add = 0x4004e9ac );
-PROVIDE ( r_llm_util_bl_check = 0x4004e930 );
-PROVIDE ( r_llm_util_bl_rem = 0x4004ea70 );
-PROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 );
-PROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 );
-PROVIDE ( r_llm_util_check_map_validity = 0x4004e800 );
-PROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 );
-PROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 );
-PROVIDE ( r_llm_util_set_public_addr = 0x4004e89c );
-PROVIDE ( r_llm_wl_clr = 0x4004dc54 );
-PROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 );
-PROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 );
-PROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc );
-PROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 );
-PROVIDE ( r_lm_acl_disc = 0x4004f148 );
-PROVIDE ( r_LM_AddSniff = 0x40022d20 );
-PROVIDE ( r_lm_add_sync = 0x40051358 );
-PROVIDE ( r_lm_afh_activate_timer = 0x4004f444 );
-PROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 );
-PROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 );
-PROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c );
-PROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 );
-PROVIDE ( r_lm_check_active_sync = 0x40051334 );
-PROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c );
-PROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 );
-PROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c );
-PROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 );
-PROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 );
-PROVIDE ( r_LM_ComputePacketType = 0x4002f554 );
-PROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac );
-PROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 );
-PROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 );
-PROVIDE ( r_lm_dhkey_calc_init = 0x40013234 );
-PROVIDE ( r_lm_dhkey_compare = 0x400132d8 );
-PROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec );
-PROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 );
-PROVIDE ( r_lm_f1 = 0x40012bb8 );
-PROVIDE ( r_lm_f2 = 0x40012cfc );
-PROVIDE ( r_lm_f3 = 0x40013050 );
-PROVIDE ( r_lm_g = 0x40012f90 );
-PROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c );
-PROVIDE ( r_lm_get_auth_en = 0x4004f1ac );
-PROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c );
-PROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 );
-PROVIDE ( r_LM_GetFeature = 0x4002f924 );
-PROVIDE ( r_LM_GetLinkTimeout = 0x400233ec );
-PROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 );
-PROVIDE ( r_lm_get_loopback_mode = 0x4004f248 );
-PROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c );
-PROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 );
-PROVIDE ( r_LM_GetMasterKey = 0x4001b260 );
-PROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 );
-PROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 );
-PROVIDE ( r_lm_get_nb_acl = 0x4004ef9c );
-PROVIDE ( r_lm_get_nb_sync_link = 0x4005179c );
-PROVIDE ( r_lm_get_nonce = 0x400131c4 );
-PROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 );
-PROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 );
-PROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 );
-PROVIDE ( r_LM_GetPINType = 0x4004f1e8 );
-PROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 );
-PROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 );
-PROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 );
-PROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 );
-PROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 );
-PROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 );
-PROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c );
-PROVIDE ( r_lm_get_sp_en = 0x4004f1c0 );
-PROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 );
-PROVIDE ( r_lm_get_synchdl = 0x4005175c );
-PROVIDE ( r_lm_get_sync_param = 0x400503b4 );
-PROVIDE ( r_lm_init = 0x4004ed34 );
-PROVIDE ( r_lm_init_sync = 0x400512d8 );
-PROVIDE ( r_lm_is_acl_con = 0x4004f47c );
-PROVIDE ( r_lm_is_acl_con_role = 0x4004f49c );
-PROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 );
-PROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 );
-PROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 );
-PROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 );
-PROVIDE ( r_lm_look_for_sync = 0x40051774 );
-PROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c );
-PROVIDE ( r_lm_lt_addr_free = 0x4004ef74 );
-PROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 );
-PROVIDE ( r_LM_MakeCof = 0x4002f84c );
-PROVIDE ( r_LM_MakeRandVec = 0x400112d8 );
-PROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 );
-PROVIDE ( r_LM_MaxSlot = 0x4002f694 );
-PROVIDE ( r_lm_modif_sync = 0x40051578 );
-PROVIDE ( r_lm_n_is_zero = 0x40012170 );
-PROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 );
-PROVIDE ( r_lm_oob_f1 = 0x40012e54 );
-PROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 );
-PROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 );
-PROVIDE ( nvds_null_read = 0x400542a0 );
-PROVIDE ( nvds_null_write = 0x400542a8 );
-PROVIDE ( nvds_null_erase = 0x400542b0 );
-PROVIDE ( nvds_read = 0x400542c4 );
-PROVIDE ( nvds_write = 0x400542fc );
-PROVIDE ( nvds_erase = 0x40054334 );
-PROVIDE ( nvds_init_memory = 0x40054358 );
-PROVIDE ( r_lmp_pack = 0x4001135c );
-PROVIDE ( r_lmp_unpack = 0x4001149c );
-PROVIDE ( r_lm_read_features = 0x4004f0d8 );
-PROVIDE ( r_LM_RemoveSniff = 0x40023124 );
-PROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 );
-PROVIDE ( r_lm_remove_sync = 0x400517c8 );
-PROVIDE ( r_lm_reset_sync = 0x40051304 );
-PROVIDE ( r_lm_role_switch_finished = 0x4004f028 );
-PROVIDE ( r_lm_role_switch_start = 0x4004efe0 );
-PROVIDE ( r_lm_sco_nego_end = 0x40051828 );
-PROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 );
-PROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 );
-PROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc );
-PROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 );
-PROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 );
-PROVIDE ( r_lm_sp_n_one = 0x400123a4 );
-PROVIDE ( r_lm_sp_p192_add = 0x40012828 );
-PROVIDE ( r_lm_sp_p192_dbl = 0x4001268c );
-PROVIDE ( r_lm_sp_p192_invert = 0x40012b6c );
-PROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 );
-PROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 );
-PROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 );
-PROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 );
-PROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 );
-PROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 );
-PROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 );
-PROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 );
-PROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 );
-PROVIDE ( r_modules_funcs = 0x3ffafd6c );
-PROVIDE ( r_modules_funcs_p = 0x3ffafd68 );
-PROVIDE ( r_nvds_del = 0x400544c4 );
-PROVIDE ( r_nvds_get = 0x40054488 );
-PROVIDE ( r_nvds_init = 0x40054410 );
-PROVIDE ( r_nvds_lock = 0x400544fc );
-PROVIDE ( r_nvds_put = 0x40054534 );
-PROVIDE ( rom_abs_temp = 0x400054f0 );
-PROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c );
-PROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac );
-PROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 );
-PROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 );
-PROVIDE ( rom_bb_wdg_test_en = 0x40003b70 );
-PROVIDE ( rom_cbw2040_cfg = 0x400040b0 );
-PROVIDE ( rom_check_noise_floor = 0x40003c78 );
-PROVIDE ( rom_chip_i2c_readReg = 0x40004110 );
-PROVIDE ( rom_chip_i2c_writeReg = 0x40004168 );
-PROVIDE ( rom_chip_v7_bt_init = 0x40004d8c );
-PROVIDE ( rom_chip_v7_rx_init = 0x40004cec );
-PROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 );
-PROVIDE ( rom_chip_v7_tx_init = 0x40004d18 );
-PROVIDE ( rom_clk_force_on_vit = 0x40003710 );
-PROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 );
-PROVIDE ( rom_dc_iq_est = 0x400055c8 );
-PROVIDE ( rom_disable_agc = 0x40002fa4 );
-PROVIDE ( rom_enable_agc = 0x40002fcc );
-PROVIDE ( rom_en_pwdet = 0x4000506c );
-PROVIDE ( rom_gen_rx_gain_table = 0x40003e3c );
-PROVIDE ( rom_get_data_sat = 0x4000312c );
-PROVIDE ( rom_get_fm_sar_dout = 0x40005204 );
-PROVIDE ( rom_get_power_db = 0x40005fc8 );
-PROVIDE ( rom_get_pwctrl_correct = 0x400065d4 );
-PROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc );
-PROVIDE ( rom_get_rf_gain_qdb = 0x40006290 );
-PROVIDE ( rom_get_sar_dout = 0x40006564 );
-PROVIDE ( rom_i2c_readReg = 0x40004148 );
-PROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 );
-PROVIDE ( rom_i2c_writeReg = 0x400041a4 );
-PROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc );
-PROVIDE ( rom_index_to_txbbgain = 0x40004df8 );
-PROVIDE ( rom_iq_est_disable = 0x40005590 );
-PROVIDE ( rom_iq_est_enable = 0x40005514 );
-PROVIDE ( rom_linear_to_db = 0x40005f64 );
-PROVIDE ( rom_loopback_mode_en = 0x400030f8 );
-PROVIDE ( rom_meas_tone_pwr_db = 0x40006004 );
-PROVIDE ( rom_mhz2ieee = 0x4000404c );
-PROVIDE ( rom_noise_floor_auto_set = 0x40003bdc );
-PROVIDE ( rom_pbus_debugmode = 0x40004458 );
-PROVIDE ( rom_pbus_force_mode = 0x40004270 );
-PROVIDE ( rom_pbus_force_test = 0x400043c0 );
-PROVIDE ( rom_pbus_rd = 0x40004414 );
-PROVIDE ( rom_pbus_rd_addr = 0x40004334 );
-PROVIDE ( rom_pbus_rd_shift = 0x40004374 );
-PROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 );
-PROVIDE ( rom_pbus_set_dco = 0x40004638 );
-PROVIDE ( rom_pbus_set_rxgain = 0x40004480 );
-PROVIDE ( rom_pbus_workmode = 0x4000446c );
-PROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 );
-PROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c );
-PROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 );
-PROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 );
-PROVIDE ( rom_phy_disable_agc = 0x40002f6c );
-PROVIDE ( rom_phy_disable_cca = 0x40003000 );
-PROVIDE ( rom_phy_enable_agc = 0x40002f88 );
-PROVIDE ( rom_phy_enable_cca = 0x4000302c );
-PROVIDE ( rom_phy_freq_correct = 0x40004b44 );
-PROVIDE ( rom_phyFuns = 0x3ffae0c0 );
-PROVIDE ( rom_phy_get_noisefloor = 0x40003c2c );
-PROVIDE ( rom_phy_get_vdd33 = 0x4000642c );
-PROVIDE ( rom_pow_usr = 0x40003044 );
-PROVIDE ( rom_read_sar_dout = 0x400051c0 );
-PROVIDE ( rom_restart_cal = 0x400046e0 );
-PROVIDE ( rom_rfcal_pwrctrl = 0x40006058 );
-PROVIDE ( rom_rfcal_rxiq = 0x40005b4c );
-PROVIDE ( rom_rfcal_txcap = 0x40005dec );
-PROVIDE ( rom_rfpll_reset = 0x40004680 );
-PROVIDE ( rom_rfpll_set_freq = 0x400047f8 );
-PROVIDE ( rom_rtc_mem_backup = 0x40003db4 );
-PROVIDE ( rom_rtc_mem_recovery = 0x40003df4 );
-PROVIDE ( rom_rx_gain_force = 0x4000351c );
-PROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 );
-PROVIDE ( rom_rxiq_get_mis = 0x400058e4 );
-PROVIDE ( rom_rxiq_set_reg = 0x40005a00 );
-PROVIDE ( rom_set_cal_rxdc = 0x400030b8 );
-PROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 );
-PROVIDE ( rom_set_channel_freq = 0x40004880 );
-PROVIDE ( rom_set_loopback_gain = 0x40003060 );
-PROVIDE ( rom_set_noise_floor = 0x40003d48 );
-PROVIDE ( rom_set_pbus_mem = 0x400031a4 );
-PROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 );
-PROVIDE ( rom_set_rxclk_en = 0x40003594 );
-PROVIDE ( rom_set_txcap_reg = 0x40005d50 );
-PROVIDE ( rom_set_txclk_en = 0x40003564 );
-PROVIDE ( rom_spur_coef_cfg = 0x40003ac8 );
-PROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 );
-PROVIDE ( rom_start_tx_tone = 0x400036b4 );
-PROVIDE ( rom_start_tx_tone_step = 0x400035d0 );
-PROVIDE ( rom_stop_tx_tone = 0x40003f98 );
-PROVIDE ( _rom_store = 0x4000d66c );
-PROVIDE ( _rom_store_table = 0x4000d4f8 );
-PROVIDE ( rom_target_power_add_backoff = 0x40006268 );
-PROVIDE ( rom_tx_atten_set_interp = 0x400061cc );
-PROVIDE ( rom_txbbgain_to_index = 0x40004dc0 );
-PROVIDE ( rom_txcal_work_mode = 0x4000510c );
-PROVIDE ( rom_txdc_cal_init = 0x40004e10 );
-PROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 );
-PROVIDE ( rom_txiq_cover = 0x4000538c );
-PROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc );
-PROVIDE ( rom_txiq_set_reg = 0x40005154 );
-PROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c );
-PROVIDE ( rom_txtone_linear_pwr = 0x40005290 );
-PROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 );
-PROVIDE ( rom_write_gain_mem = 0x4000348c );
-PROVIDE ( rom_write_rfpll_sdm = 0x40004740 );
-PROVIDE ( roundup2 = 0x4000ab7c );
-PROVIDE ( r_plf_funcs_p = 0x3ffb8360 );
-PROVIDE ( r_rf_rw_bt_init = 0x40054868 );
-PROVIDE ( r_rf_rw_init = 0x40054b0c );
-PROVIDE ( r_rf_rw_le_init = 0x400549d0 );
-PROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c );
-PROVIDE ( r_rwble_init = 0x40054bf4 );
-PROVIDE ( r_rwble_isr = 0x40054e08 );
-PROVIDE ( r_rwble_reset = 0x40054ce8 );
-PROVIDE ( r_rwble_sleep_check = 0x40054d78 );
-PROVIDE ( r_rwble_version = 0x40054dac );
-PROVIDE ( r_rwbt_init = 0x40055160 );
-PROVIDE ( r_rwbt_isr = 0x40055248 );
-PROVIDE ( r_rwbt_reset = 0x400551bc );
-PROVIDE ( r_rwbt_sleep_check = 0x4005577c );
-PROVIDE ( r_rwbt_sleep_enter = 0x400557a4 );
-PROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc );
-PROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc );
-PROVIDE ( r_rwbt_version = 0x4005520c );
-PROVIDE ( r_rwip_assert_err = 0x40055f88 );
-PROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc );
-PROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c );
-PROVIDE ( r_rwip_init = 0x4005595c );
-PROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 );
-PROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 );
-PROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 );
-PROVIDE ( r_rwip_reset = 0x40055ab8 );
-PROVIDE ( r_rwip_schedule = 0x40055b38 );
-PROVIDE ( r_rwip_sleep = 0x40055b5c );
-PROVIDE ( r_rwip_sleep_enable = 0x40055f30 );
-PROVIDE ( r_rwip_version = 0x40055b20 );
-PROVIDE ( r_rwip_wakeup = 0x40055dc4 );
-PROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c );
-PROVIDE ( r_rwip_wakeup_end = 0x40055e18 );
-PROVIDE ( r_rwip_wlcoex_set = 0x40055f60 );
-PROVIDE ( r_SHA_256 = 0x40013a90 );
-PROVIDE ( rwip_coex_cfg = 0x3ff9914c );
-PROVIDE ( rwip_priority = 0x3ff99159 );
-PROVIDE ( rwip_rf = 0x3ffbdb28 );
-PROVIDE ( rwip_rf_p_get = 0x400558f4 );
-PROVIDE ( r_XorKey = 0x400112c0 );
-PROVIDE ( __sf_fake_stderr = 0x3ff96458 );
-PROVIDE ( __sf_fake_stdin = 0x3ff96498 );
-PROVIDE ( __sf_fake_stdout = 0x3ff96478 );
-PROVIDE ( sha_blk_bits = 0x3ff99290 );
-PROVIDE ( sha_blk_bits_bytes = 0x3ff99288 );
-PROVIDE ( sha_blk_hash_bytes = 0x3ff9928c );
-PROVIDE ( sig_matrix = 0x3ffae293 );
-PROVIDE ( sip_after_tx_complete = 0x4000b358 );
-PROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c );
-PROVIDE ( sip_get_ptr = 0x4000b34c );
-PROVIDE ( sip_get_state = 0x4000ae2c );
-PROVIDE ( sip_init_attach = 0x4000ae58 );
-PROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 );
-PROVIDE ( sip_install_rx_data_cb = 0x4000ae20 );
-PROVIDE ( sip_is_active = 0x4000b3c0 );
-PROVIDE ( sip_post_init = 0x4000aed8 );
-PROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc );
-PROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c );
-PROVIDE ( sip_send = 0x4000af54 );
-PROVIDE ( sip_to_host_chain_append = 0x4000aef8 );
-PROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 );
-PROVIDE ( slc_add_credits = 0x4000baf4 );
-PROVIDE ( slc_enable = 0x4000b64c );
-PROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 );
-PROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 );
-PROVIDE ( slc_has_pkt_to_host = 0x4000b5fc );
-PROVIDE ( slc_init_attach = 0x4000b918 );
-PROVIDE ( slc_init_credit = 0x4000badc );
-PROVIDE ( slc_reattach = 0x4000b62c );
-PROVIDE ( slc_send_to_host_chain = 0x4000b6a0 );
-PROVIDE ( slc_set_host_io_max_window = 0x4000b89c );
-PROVIDE ( slc_to_host_chain_recycle = 0x4000b758 );
-PROVIDE ( specialModP256 = 0x4001600c );
-PROVIDE ( __stack = 0x3ffe3f20 );
-PROVIDE ( __stack_app = 0x3ffe7e30 );
-PROVIDE ( _stack_sentry = 0x3ffe1320 );
-PROVIDE ( _stack_sentry_app = 0x3ffe5230 );
-PROVIDE ( _start = 0x40000704 );
-PROVIDE ( start_tb_console = 0x4005a980 );
-PROVIDE ( _stat_r = 0x4000bcb4 );
-PROVIDE ( _stext = 0x40000560 );
-PROVIDE ( SubtractBigHex256 = 0x40015bcc );
-PROVIDE ( SubtractBigHexMod256 = 0x40015e8c );
-PROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c );
-PROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 );
-PROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 );
-PROVIDE ( sw_to_hw = 0x3ffb8d40 );
-PROVIDE ( syscall_table_ptr_app = 0x3ffae020 );
-PROVIDE ( syscall_table_ptr_pro = 0x3ffae024 );
-PROVIDE ( tdefl_compress = 0x400600bc );
-PROVIDE ( tdefl_compress_buffer = 0x400607f4 );
-PROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 );
-PROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 );
-PROVIDE ( tdefl_get_adler32 = 0x400608d8 );
-PROVIDE ( tdefl_get_prev_return_status = 0x400608d0 );
-PROVIDE ( tdefl_init = 0x40060810 );
-PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c );
-PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 );
-PROVIDE ( _timezone = 0x3ffae0a0 );
-PROVIDE ( tinfl_decompress = 0x4005ef30 );
-PROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 );
-PROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 );
-PROVIDE ( _tzname = 0x3ffae030 );
-PROVIDE ( UartDev = 0x3ffe019c );
-PROVIDE ( _unlink_r = 0x4000bc84 );
-PROVIDE ( user_code_start = 0x3ffe0400 );
-PROVIDE ( veryBigHexP256 = 0x3ff9736c );
-PROVIDE ( __wctomb = 0x3ff96540 );
-PROVIDE ( _write_r = 0x4000bd70 );
-PROVIDE ( xthal_bcopy = 0x4000c098 );
-PROVIDE ( xthal_copy123 = 0x4000c124 );
-PROVIDE ( xthal_get_ccompare = 0x4000c078 );
-PROVIDE ( xthal_get_ccount = 0x4000c050 );
-PROVIDE ( xthal_get_interrupt = 0x4000c1e4 );
-PROVIDE ( xthal_get_intread = 0x4000c1e4 );
-PROVIDE ( Xthal_intlevel = 0x3ff9c2b4 );
-PROVIDE ( xthal_memcpy = 0x4000c0bc );
-PROVIDE ( xthal_set_ccompare = 0x4000c058 );
-PROVIDE ( xthal_set_intclear = 0x4000c1ec );
-PROVIDE ( _xtos_set_intlevel = 0x4000bfdc );
-PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );
-PROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );
-PROVIDE ( esp_rom_spiflash_config_param = 0x40063238 );
-PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );
-PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 );
-PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 );
-PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );
-PROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc );
-PROVIDE ( esp_rom_spiflash_attach = 0x40062a6c );
-PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 );
-PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );
-
-PROVIDE ( hci_le_rd_rem_used_feats_cmd_handler = 0x400417b4 );
-PROVIDE ( llcp_length_req_handler = 0x40043808 );
-PROVIDE ( llcp_unknown_rsp_handler = 0x40043ba8 );
-PROVIDE ( llcp_channel_map_req_handler = 0x4004291c );
-PROVIDE ( llcp_con_up_req_handler = 0x400426f0 );
-
-/*
-These functions are xtos-related (or call xtos-related functions) and do not play well
-with multicore FreeRTOS. Where needed, we provide alternatives that are multicore
-compatible. These functions also use a chunk of static RAM, by not using them we can
-allocate that RAM for general use.
-*/
-/*
-PROVIDE ( _DebugExceptionVector = 0x40000280 );
-PROVIDE ( _DoubleExceptionVector = 0x400003c0 );
-PROVIDE ( _KernelExceptionVector = 0x40000300 );
-PROVIDE ( _GeneralException = 0x40000e14 );
-PROVIDE ( _ResetHandler = 0x40000450 );
-PROVIDE ( _ResetVector = 0x40000400 );
-PROVIDE ( _UserExceptionVector = 0x40000340 );
-PROVIDE ( _NMIExceptionVector = 0x400002c0 );
-PROVIDE ( _WindowOverflow12 = 0x40000100 );
-PROVIDE ( _WindowOverflow4 = 0x40000000 );
-PROVIDE ( _WindowOverflow8 = 0x40000080 );
-PROVIDE ( _WindowUnderflow12 = 0x40000140 );
-PROVIDE ( _WindowUnderflow4 = 0x40000040 );
-PROVIDE ( _WindowUnderflow8 = 0x400000c0 );
-PROVIDE ( _Level2FromVector = 0x40000954 );
-PROVIDE ( _Level3FromVector = 0x40000a28 );
-PROVIDE ( _Level4FromVector = 0x40000af8 );
-PROVIDE ( _Level5FromVector = 0x40000c68 );
-PROVIDE ( _Level2Vector = 0x40000180 );
-PROVIDE ( _Level3Vector = 0x400001c0 );
-PROVIDE ( _Level4Vector = 0x40000200 );
-PROVIDE ( _Level5Vector = 0x40000240 );
-PROVIDE ( _LevelOneInterrupt = 0x40000835 );
-PROVIDE ( _SyscallException = 0x400007cf );
-PROVIDE ( _xtos_alloca_handler = 0x40000010 );
-PROVIDE ( _xtos_cause3_handler = 0x40000dd8 );
-PROVIDE ( _xtos_c_handler_table = 0x3ffe0548 );
-PROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 );
-PROVIDE ( _xtos_enabled = 0x3ffe0650 );
-PROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 );
-PROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 );
-PROVIDE ( _xtos_interrupt_table = 0x3ffe0658 );
-PROVIDE ( _xtos_ints_off = 0x4000bfac );
-PROVIDE ( _xtos_ints_on = 0x4000bf88 );
-PROVIDE ( _xtos_intstruct = 0x3ffe0650 );
-PROVIDE ( _xtos_l1int_handler = 0x40000814 );
-PROVIDE ( _xtos_p_none = 0x4000bfd4 );
-PROVIDE ( _xtos_restore_intlevel = 0x40000928 );
-PROVIDE ( _xtos_return_from_exc = 0x4000c034 );
-PROVIDE ( _xtos_set_exception_handler = 0x4000074c );
-PROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 );
-PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 );
-PROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 );
-PROVIDE ( _xtos_set_vpri = 0x40000934 );
-PROVIDE ( _xtos_syscall_handler = 0x40000790 );
-PROVIDE ( _xtos_unhandled_exception = 0x4000c024 );
-PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c );
-PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 );
-PROVIDE ( ets_intr_count = 0x3ffe03fc );
-*/
-
-/* These functions are part of the UART downloader but also contain general UART functions. */
-PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 );
-PROVIDE ( FilePacketSendReqMsgProc = 0x40008860 );
-PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 );
-PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c );
-PROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 );
-PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 );
-PROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec );
-PROVIDE ( MemDwnLdStartMsgProc = 0x40008948 );
-PROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc );
-PROVIDE ( MemPacketSendReqMsgProc = 0x40008978 );
-PROVIDE ( uart_baudrate_detect = 0x40009034 );
-PROVIDE ( uart_buff_switch = 0x400093c0 );
-PROVIDE ( UartConnCheck = 0x40008738 );
-PROVIDE ( UartConnectProc = 0x40008a04 );
-PROVIDE ( UartDwnLdProc = 0x40008ce8 );
-PROVIDE ( UartRegReadProc = 0x40008a58 );
-PROVIDE ( UartRegWriteProc = 0x40008a14 );
-PROVIDE ( UartSetBaudProc = 0x40008aac );
-PROVIDE ( UartSpiAttachProc = 0x40008a6c );
-PROVIDE ( UartSpiReadProc = 0x40008a80 );
-PROVIDE ( VerifyFlashMd5Proc = 0x40008c44 );
-PROVIDE ( GetUartDevice = 0x40009598 );
-PROVIDE ( RcvMsg = 0x4000954c );
-PROVIDE ( SendMsg = 0x40009384 );
-PROVIDE ( UartGetCmdLn = 0x40009564 );
-PROVIDE ( UartRxString = 0x400092fc );
-PROVIDE ( Uart_Init = 0x40009120 );
-PROVIDE ( recv_packet = 0x40009424 );
-PROVIDE ( send_packet = 0x40009340 );
-PROVIDE ( uartAttach = 0x40008fd0 );
-PROVIDE ( uart_div_modify = 0x400090cc );
-PROVIDE ( uart_rx_intr_handler = 0x40008f4c );
-PROVIDE ( uart_rx_one_char = 0x400092d0 );
-PROVIDE ( uart_rx_one_char_block = 0x400092a4 );
-PROVIDE ( uart_rx_readbuff = 0x40009394 );
-PROVIDE ( uart_tx_flush = 0x40009258 );
-PROVIDE ( uart_tx_one_char = 0x40009200 );
-PROVIDE ( uart_tx_one_char2 = 0x4000922c );
-PROVIDE ( uart_tx_switch = 0x40009028 );
-
-
-/*
-These functions are part of the ROM GPIO driver. We do not use them; the provided esp-idf functions
-replace them and this way we can re-use the fixed RAM addresses these routines need.
-*/
-/* <-- So you don't read over it: This comment disables the next lines.
-PROVIDE ( gpio_init = 0x40009c20 );
-PROVIDE ( gpio_intr_ack = 0x40009dd4 );
-PROVIDE ( gpio_intr_ack_high = 0x40009e1c );
-PROVIDE ( gpio_intr_handler_register = 0x40009e6c );
-PROVIDE ( gpio_intr_pending = 0x40009cec );
-PROVIDE ( gpio_intr_pending_high = 0x40009cf8 );
-PROVIDE ( gpio_pending_mask = 0x3ffe0038 );
-PROVIDE ( gpio_pending_mask_high = 0x3ffe0044 );
-PROVIDE ( gpio_pin_intr_state_set = 0x40009d04 );
-PROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 );
-PROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c );
-PROVIDE ( gpio_register_get = 0x40009cbc );
-PROVIDE ( gpio_register_set = 0x40009bbc );
-*/
-/* These are still part of that driver, but have been verified not to use static RAM, so they can be used. */
-PROVIDE ( gpio_output_set = 0x40009b24 );
-PROVIDE ( gpio_output_set_high = 0x40009b5c );
-PROVIDE ( gpio_input_get = 0x40009b88 );
-PROVIDE ( gpio_input_get_high = 0x40009b9c );
-PROVIDE ( gpio_matrix_in = 0x40009edc );
-PROVIDE ( gpio_matrix_out = 0x40009f0c );
-PROVIDE ( gpio_pad_select_gpio = 0x40009fdc );
-PROVIDE ( gpio_pad_set_drv = 0x4000a11c );
-PROVIDE ( gpio_pad_pulldown = 0x4000a348 );
-PROVIDE ( gpio_pad_pullup = 0x4000a22c );
-PROVIDE ( gpio_pad_hold = 0x4000a734 );
-PROVIDE ( gpio_pad_unhold = 0x4000a484 );
-
-/*
-These functions are part of the non-os kernel (etsc).
-*/
-PROVIDE ( ets_aes_crypt = 0x4005c9b8 );
-PROVIDE ( ets_aes_disable = 0x4005c8f8 );
-PROVIDE ( ets_aes_enable = 0x4005c8cc );
-PROVIDE ( ets_aes_set_endian = 0x4005c928 );
-PROVIDE ( ets_aes_setkey_dec = 0x4005c994 );
-PROVIDE ( ets_aes_setkey_enc = 0x4005c97c );
-PROVIDE ( ets_bigint_disable = 0x4005c4e0 );
-PROVIDE ( ets_bigint_enable = 0x4005c498 );
-PROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 );
-PROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 );
-PROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 );
-PROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c );
-PROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 );
-PROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc );
-PROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 );
-PROVIDE ( ets_bigint_mult_prepare = 0x4005c630 );
-PROVIDE ( ets_bigint_wait_finish = 0x4005c520 );
-PROVIDE ( ets_post = 0x4000673c );
-PROVIDE ( ets_run = 0x400066bc );
-PROVIDE ( ets_set_idle_cb = 0x40006674 );
-PROVIDE ( ets_task = 0x40006688 );
-PROVIDE ( ets_efuse_get_8M_clock = 0x40008710 );
-PROVIDE ( ets_efuse_get_spiconfig = 0x40008658 );
-PROVIDE ( ets_efuse_program_op = 0x40008628 );
-PROVIDE ( ets_efuse_read_op = 0x40008600 );
-PROVIDE ( ets_intr_lock = 0x400067b0 );
-PROVIDE ( ets_intr_unlock = 0x400067c4 );
-PROVIDE ( ets_isr_attach = 0x400067ec );
-PROVIDE ( ets_waiti0 = 0x400067d8 );
-PROVIDE ( intr_matrix_set = 0x4000681c );
-PROVIDE ( check_pos = 0x400068b8 );
-PROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c );
-PROVIDE ( ets_set_startup_callback = 0x4000688c );
-PROVIDE ( ets_set_user_start = 0x4000687c );
-PROVIDE ( ets_unpack_flash_code = 0x40007018 );
-PROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c );
-PROVIDE ( rom_main = 0x400076c4 );
-PROVIDE ( ets_write_char_uart = 0x40007cf8 );
-PROVIDE ( ets_install_putc1 = 0x40007d18 );
-PROVIDE ( ets_install_putc2 = 0x40007d38 );
-PROVIDE ( ets_install_uart_printf = 0x40007d28 );
-PROVIDE ( ets_printf = 0x40007d54 );
-PROVIDE ( rtc_boot_control = 0x4000821c );
-PROVIDE ( rtc_get_reset_reason = 0x400081d4 );
-PROVIDE ( rtc_get_wakeup_cause = 0x400081f4 );
-PROVIDE ( rtc_select_apb_bridge = 0x40008288 );
-PROVIDE ( set_rtc_memory_crc = 0x40008208 );
-PROVIDE ( software_reset = 0x4000824c );
-PROVIDE ( software_reset_cpu = 0x40008264 );
-PROVIDE ( ets_secure_boot_check = 0x4005cb40 );
-PROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 );
-PROVIDE ( ets_secure_boot_check_start = 0x4005cbcc );
-PROVIDE ( ets_secure_boot_finish = 0x4005ca84 );
-PROVIDE ( ets_secure_boot_hash = 0x4005cad4 );
-PROVIDE ( ets_secure_boot_obtain = 0x4005cb14 );
-PROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 );
-PROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 );
-PROVIDE ( ets_secure_boot_start = 0x4005ca34 );
-PROVIDE ( ets_sha_disable = 0x4005c0a8 );
-PROVIDE ( ets_sha_enable = 0x4005c07c );
-PROVIDE ( ets_sha_finish = 0x4005c104 );
-PROVIDE ( ets_sha_init = 0x4005c0d4 );
-PROVIDE ( ets_sha_update = 0x4005c2a0 );
-PROVIDE ( ets_delay_us = 0x40008534 );
-PROVIDE ( ets_get_cpu_frequency = 0x4000855c );
-PROVIDE ( ets_get_detected_xtal_freq = 0x40008588 );
-PROVIDE ( ets_get_xtal_scale = 0x4000856c );
-PROVIDE ( ets_update_cpu_frequency_rom = 0x40008550 );  /* Updates g_ticks_per_us on the current CPU only; not on the other core */
-
-/* Following are static data, but can be used, not generated by script <<<<< btdm data */
-PROVIDE ( hci_tl_env = 0x3ffb8154 );
-PROVIDE ( ld_acl_env = 0x3ffb8258 );
-PROVIDE ( ea_env = 0x3ffb80ec );
-PROVIDE ( lc_sco_data_path_config = 0x3ffb81f8 );
-PROVIDE ( lc_sco_env = 0x3ffb81fc );
-PROVIDE ( ld_active_ch_map = 0x3ffb8334 );
-PROVIDE ( ld_bcst_acl_env = 0x3ffb8274 );
-PROVIDE ( ld_csb_rx_env = 0x3ffb8278 );
-PROVIDE ( ld_csb_tx_env = 0x3ffb827c );
-PROVIDE ( ld_env = 0x3ffb9510 );
-PROVIDE ( ld_fm_env = 0x3ffb8284 );
-PROVIDE ( ld_inq_env = 0x3ffb82e4 );
-PROVIDE ( ld_iscan_env = 0x3ffb82e8 );
-PROVIDE ( ld_page_env = 0x3ffb82f0 );
-PROVIDE ( ld_pca_env = 0x3ffb82f4 );
-PROVIDE ( ld_pscan_env = 0x3ffb8308 );
-PROVIDE ( ld_sched_env = 0x3ffb830c );
-PROVIDE ( ld_sched_params = 0x3ffb96c0 );
-PROVIDE ( ld_sco_env = 0x3ffb824c );
-PROVIDE ( ld_sscan_env = 0x3ffb832c );
-PROVIDE ( ld_strain_env = 0x3ffb8330 );
-PROVIDE ( LM_Sniff = 0x3ffb8230 );
-PROVIDE ( LM_SniffSubRate = 0x3ffb8214 );
-PROVIDE ( prbs_64bytes = 0x3ff98992 );
-PROVIDE ( nvds_env = 0x3ffb8364 );
-PROVIDE ( nvds_magic_number = 0x3ff9912a );
-PROVIDE ( TASK_DESC_LLD = 0x3ff98b58 );
-/* Above are static data, but can be used, not generated by script >>>>> btdm data */
-
diff --git a/tools/sdk/ld/esp32.rom.libgcc.ld b/tools/sdk/ld/esp32.rom.libgcc.ld
deleted file mode 100644
index 51448b33272..00000000000
--- a/tools/sdk/ld/esp32.rom.libgcc.ld
+++ /dev/null
@@ -1,91 +0,0 @@
-__absvdi2 = 0x4006387c;
-__absvsi2 = 0x40063868;
-__adddf3 = 0x40002590;
-__addsf3 = 0x400020e8;
-__addvdi3 = 0x40002cbc;
-__addvsi3 = 0x40002c98;
-__ashldi3 = 0x4000c818;
-__ashrdi3 = 0x4000c830;
-__bswapdi2 = 0x40064b08;
-__bswapsi2 = 0x40064ae0;
-__clrsbdi2 = 0x40064b7c;
-__clrsbsi2 = 0x40064b64;
-__clzdi2 = 0x4000ca50;
-__clzsi2 = 0x4000c7e8;
-__cmpdi2 = 0x40063820;
-__ctzdi2 = 0x4000ca64;
-__ctzsi2 = 0x4000c7f0;
-__divdc3 = 0x400645a4;
-__divdf3 = 0x40002954;
-__divdi3 = 0x4000ca84;
-__divsc3 = 0x4006429c;
-__divsf3 = 0x4000234c;
-__divsi3 = 0x4000c7b8;
-__eqdf2 = 0x400636a8;
-__eqsf2 = 0x40063374;
-__extendsfdf2 = 0x40002c34;
-__ffsdi2 = 0x4000ca2c;
-__ffssi2 = 0x4000c804;
-__fixdfdi = 0x40002ac4;
-__fixdfsi = 0x40002a78;
-__fixsfdi = 0x4000244c;
-__fixsfsi = 0x4000240c;
-__fixunsdfsi = 0x40002b30;
-__fixunssfdi = 0x40002504;
-__fixunssfsi = 0x400024ac;
-__floatdidf = 0x4000c988;
-__floatdisf = 0x4000c8c0;
-__floatsidf = 0x4000c944;
-__floatsisf = 0x4000c870;
-__floatundidf = 0x4000c978;
-__floatundisf = 0x4000c8b0;
-__floatunsidf = 0x4000c938;
-__floatunsisf = 0x4000c864;
-__gedf2 = 0x40063768;
-__gesf2 = 0x4006340c;
-__gtdf2 = 0x400636dc;
-__gtsf2 = 0x400633a0;
-__ledf2 = 0x40063704;
-__lesf2 = 0x400633c0;
-__lshrdi3 = 0x4000c84c;
-__ltdf2 = 0x40063790;
-__ltsf2 = 0x4006342c;
-__moddi3 = 0x4000cd4c;
-__modsi3 = 0x4000c7c0;
-__muldc3 = 0x40063c90;
-__muldf3 = 0x4006358c;
-__muldi3 = 0x4000c9fc;
-__mulsc3 = 0x40063944;
-__mulsf3 = 0x400632c8;
-__mulsi3 = 0x4000c7b0;
-__mulvdi3 = 0x40002d78;
-__mulvsi3 = 0x40002d60;
-__nedf2 = 0x400636a8;
-__negdf2 = 0x400634a0;
-__negdi2 = 0x4000ca14;
-__negsf2 = 0x400020c0;
-__negvdi2 = 0x40002e98;
-__negvsi2 = 0x40002e78;
-__nesf2 = 0x40063374;
-__nsau_data = 0x3ff96544;
-__paritysi2 = 0x40002f3c;
-__popcount_tab = 0x3ff96544;
-__popcountdi2 = 0x40002ef8;
-__popcountsi2 = 0x40002ed0;
-__powidf2 = 0x400638e4;
-__powisf2 = 0x4006389c;
-__subdf3 = 0x400026e4;
-__subsf3 = 0x400021d0;
-__subvdi3 = 0x40002d20;
-__subvsi3 = 0x40002cf8;
-__truncdfsf2 = 0x40002b90;
-__ucmpdi2 = 0x40063840;
-__udiv_w_sdiv = 0x40064bec;
-__udivdi3 = 0x4000cff8;
-__udivmoddi4 = 0x40064bf4;
-__udivsi3 = 0x4000c7c8;
-__umoddi3 = 0x4000d280;
-__umodsi3 = 0x4000c7d0;
-__umulsidi3 = 0x4000c7d8;
-__unorddf2 = 0x400637f4;
-__unordsf2 = 0x40063478;
diff --git a/tools/sdk/ld/esp32.rom.nanofmt.ld b/tools/sdk/ld/esp32.rom.nanofmt.ld
deleted file mode 100644
index ae843dff2fb..00000000000
--- a/tools/sdk/ld/esp32.rom.nanofmt.ld
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
-	Address table for printf/scanf family of functions in ESP32 ROM.
-	These functions are compiled with newlib "nano" format option.
-	As such, they don's support 64-bit integer formats.
-	Floating point formats are supported by setting _printf_float and
-	_scanf_float entries in syscall table. This is done automatically
-	by startup code.
-
-	Generated for ROM with MD5sum:
-	ab8282ae908fe9e7a63fb2a4ac2df013  eagle.pro.rom.out
-*/
-
-PROVIDE ( asiprintf = 0x40056d9c );
-PROVIDE ( _asiprintf_r = 0x40056d4c );
-PROVIDE ( asniprintf = 0x40056cd8 );
-PROVIDE ( _asniprintf_r = 0x40056c64 );
-PROVIDE ( asnprintf = 0x40056cd8 );
-PROVIDE ( _asnprintf_r = 0x40056c64 );
-PROVIDE ( asprintf = 0x40056d9c );
-PROVIDE ( _asprintf_r = 0x40056d4c );
-PROVIDE ( fiprintf = 0x40056efc );
-PROVIDE ( _fiprintf_r = 0x40056ed8 );
-PROVIDE ( fiscanf = 0x40058884 );
-PROVIDE ( _fiscanf_r = 0x400588b4 );
-PROVIDE ( fprintf = 0x40056efc );
-PROVIDE ( _fprintf_r = 0x40056ed8 );
-PROVIDE ( iprintf = 0x40056978 );
-PROVIDE ( _iprintf_r = 0x40056944 );
-PROVIDE ( printf = 0x40056978 );
-PROVIDE ( _printf_common = 0x40057338 );
-PROVIDE ( _printf_float = 0x4000befc );
-PROVIDE ( _printf_i = 0x40057404 );
-PROVIDE ( _printf_r = 0x40056944 );
-PROVIDE ( siprintf = 0x40056c08 );
-PROVIDE ( _siprintf_r = 0x40056bbc );
-PROVIDE ( sniprintf = 0x40056b4c );
-PROVIDE ( _sniprintf_r = 0x40056ae4 );
-PROVIDE ( snprintf = 0x40056b4c );
-PROVIDE ( _snprintf_r = 0x40056ae4 );
-PROVIDE ( sprintf = 0x40056c08 );
-PROVIDE ( _sprintf_r = 0x40056bbc );
-PROVIDE ( __sprint_r = 0x400577e4 );
-PROVIDE ( _svfiprintf_r = 0x40057100 );
-PROVIDE ( __svfiscanf_r = 0x40057b08 );
-PROVIDE ( _svfprintf_r = 0x40057100 );
-PROVIDE ( __svfscanf = 0x40057f04 );
-PROVIDE ( __svfscanf_r = 0x40057b08 );
-PROVIDE ( vasiprintf = 0x40056eb8 );
-PROVIDE ( _vasiprintf_r = 0x40056e80 );
-PROVIDE ( vasniprintf = 0x40056e58 );
-PROVIDE ( _vasniprintf_r = 0x40056df8 );
-PROVIDE ( vasnprintf = 0x40056e58 );
-PROVIDE ( _vasnprintf_r = 0x40056df8 );
-PROVIDE ( vasprintf = 0x40056eb8 );
-PROVIDE ( _vasprintf_r = 0x40056e80 );
-PROVIDE ( vfiprintf = 0x40057ae8 );
-PROVIDE ( _vfiprintf_r = 0x40057850 );
-PROVIDE ( vfiscanf = 0x40057eb8 );
-PROVIDE ( _vfiscanf_r = 0x40057f24 );
-PROVIDE ( vfprintf = 0x40057ae8 );
-PROVIDE ( _vfprintf_r = 0x40057850 );
-PROVIDE ( vfscanf = 0x40057eb8 );
-PROVIDE ( _vfscanf_r = 0x40057f24 );
-PROVIDE ( viprintf = 0x400569b4 );
-PROVIDE ( _viprintf_r = 0x400569e4 );
-PROVIDE ( viscanf = 0x40058698 );
-PROVIDE ( _viscanf_r = 0x400586c8 );
-PROVIDE ( vprintf = 0x400569b4 );
-PROVIDE ( _vprintf_r = 0x400569e4 );
-PROVIDE ( vscanf = 0x40058698 );
-PROVIDE ( _vscanf_r = 0x400586c8 );
-PROVIDE ( vsiprintf = 0x40056ac4 );
-PROVIDE ( _vsiprintf_r = 0x40056a90 );
-PROVIDE ( vsiscanf = 0x40058740 );
-PROVIDE ( _vsiscanf_r = 0x400586f8 );
-PROVIDE ( vsniprintf = 0x40056a68 );
-PROVIDE ( _vsniprintf_r = 0x40056a14 );
-PROVIDE ( vsnprintf = 0x40056a68 );
-PROVIDE ( _vsnprintf_r = 0x40056a14 );
-PROVIDE ( vsprintf = 0x40056ac4 );
-PROVIDE ( _vsprintf_r = 0x40056a90 );
-PROVIDE ( vsscanf = 0x40058740 );
-PROVIDE ( _vsscanf_r = 0x400586f8 );
-PROVIDE ( fscanf = 0x40058884 );
-PROVIDE ( _fscanf_r = 0x400588b4 );
-PROVIDE ( iscanf = 0x40058760 );
-PROVIDE ( _iscanf_r = 0x4005879c );
-PROVIDE ( scanf = 0x40058760 );
-PROVIDE ( _scanf_chars = 0x40058384 );
-PROVIDE ( _scanf_float = 0x4000bf18 );
-PROVIDE ( _scanf_i = 0x4005845c );
-PROVIDE ( _scanf_r = 0x4005879c );
-PROVIDE ( siscanf = 0x400587d0 );
-PROVIDE ( _siscanf_r = 0x40058830 );
-PROVIDE ( sscanf = 0x400587d0 );
-PROVIDE ( _sscanf_r = 0x40058830 );
-PROVIDE ( __ssvfiscanf_r = 0x4005802c );
-PROVIDE ( __ssvfscanf_r = 0x4005802c );
-
-
diff --git a/tools/sdk/ld/esp32.rom.redefined.ld b/tools/sdk/ld/esp32.rom.redefined.ld
deleted file mode 100644
index c229640a20e..00000000000
--- a/tools/sdk/ld/esp32.rom.redefined.ld
+++ /dev/null
@@ -1,60 +0,0 @@
-/* 
-   ROM Functions defined in this file are not used in ESP-IDF as is,
-   and different definitions for functions with the same names are provided.
-   This file is not used when linking ESP-IDF and is intended for reference only
-*/
-  
-PROVIDE ( abort = 0x4000bba4 );
-PROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c );
-PROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 );
-PROVIDE ( aes_unwrap = 0x4005ccf0 );
-PROVIDE ( base64_decode = 0x4005ced8 );
-PROVIDE ( base64_encode = 0x4005cdbc );
-PROVIDE ( ets_isr_mask = 0x400067fc );
-PROVIDE ( ets_isr_unmask = 0x40006808 );
-PROVIDE ( ets_timer_arm = 0x40008368 );
-PROVIDE ( ets_timer_arm_us = 0x400083ac );
-PROVIDE ( ets_timer_disarm = 0x400083ec );
-PROVIDE ( ets_timer_done = 0x40008428 );
-PROVIDE ( ets_timer_init = 0x400084e8 );
-PROVIDE ( ets_timer_handler_isr = 0x40008454 );
-PROVIDE ( ets_timer_setfn = 0x40008350 );
-PROVIDE ( _free_r = 0x4000bbcc );
-PROVIDE ( _getpid_r = 0x4000bcfc );
-PROVIDE ( __getreent = 0x4000be8c );
-PROVIDE ( _gettimeofday_r = 0x4000bc58 );
-PROVIDE ( hmac_md5 = 0x4005d264 );
-PROVIDE ( hmac_md5_vector = 0x4005d17c );
-PROVIDE ( hmac_sha1 = 0x40060acc );
-PROVIDE ( hmac_sha1_vector = 0x400609e4 );
-PROVIDE ( hmac_sha256 = 0x40060d58 );
-PROVIDE ( hmac_sha256_vector = 0x40060c84 );
-PROVIDE ( _kill_r = 0x4000bd10 );
-PROVIDE ( _lock_acquire = 0x4000be14 );
-PROVIDE ( _lock_acquire_recursive = 0x4000be28 );
-PROVIDE ( _lock_close = 0x4000bdec );
-PROVIDE ( _lock_close_recursive = 0x4000be00 );
-PROVIDE ( _lock_init = 0x4000bdc4 );
-PROVIDE ( _lock_init_recursive = 0x4000bdd8 );
-PROVIDE ( _lock_release = 0x4000be64 );
-PROVIDE ( _lock_release_recursive = 0x4000be78 );
-PROVIDE ( _lock_try_acquire = 0x4000be3c );
-PROVIDE ( _lock_try_acquire_recursive = 0x4000be50 );
-PROVIDE ( _malloc_r = 0x4000bbb4 );
-PROVIDE ( MD5Final = 0x4005db1c );
-PROVIDE ( MD5Init = 0x4005da7c );
-PROVIDE ( MD5Update = 0x4005da9c );
-PROVIDE ( md5_vector = 0x4005db80 );
-PROVIDE ( pbkdf2_sha1 = 0x40060ba4 );
-PROVIDE ( rc4_skip = 0x40060928 );
-PROVIDE ( _raise_r = 0x4000bc70 );
-PROVIDE ( _realloc_r = 0x4000bbe0 );
-PROVIDE ( _sbrk_r = 0x4000bce4 );
-PROVIDE ( sha1_prf = 0x40060ae8 );
-PROVIDE ( sha1_vector = 0x40060b64 );
-PROVIDE ( sha256_prf = 0x40060d70 );
-PROVIDE ( sha256_vector = 0x40060e08 );
-PROVIDE ( _system_r = 0x4000bc10 );
-PROVIDE ( _times_r = 0x4000bc40 );
-PROVIDE ( uart_tx_wait_idle = 0x40009278 );
-
diff --git a/tools/sdk/ld/esp32.rom.spiflash.ld b/tools/sdk/ld/esp32.rom.spiflash.ld
deleted file mode 100644
index 709b3581144..00000000000
--- a/tools/sdk/ld/esp32.rom.spiflash.ld
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
-	Address table for SPI driver functions in ESP32 ROM.
-	These functions are only linked from ROM when SPI_FLASH_ROM_DRIVER_PATCH is not set in configuration.
-*/
-
-PROVIDE ( esp_rom_spiflash_write_encrypted = 0x40062e78 );
-PROVIDE ( esp_rom_spiflash_erase_area = 0x400631ac );
-PROVIDE ( esp_rom_spiflash_erase_block = 0x40062c4c );
-PROVIDE ( esp_rom_spiflash_erase_chip = 0x40062c14 );
-PROVIDE ( esp_rom_spiflash_erase_sector = 0x40062ccc );
-PROVIDE ( esp_rom_spiflash_lock = 0x400628f0 );
-PROVIDE ( esp_rom_spiflash_read = 0x40062ed8 );
-PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062b64 ); /* SPIMasterReadModeCnfig */
-PROVIDE ( esp_rom_spiflash_read_status = 0x4006226c );
-PROVIDE ( esp_rom_spiflash_read_statushigh = 0x40062448 );
-PROVIDE ( esp_rom_spiflash_write = 0x40062d50 );
-PROVIDE ( esp_rom_spiflash_enable_write = 0x40062320 );
-PROVIDE ( esp_rom_spiflash_write_status = 0x400622f0 );
-
-/* always using patched versions of these functions 
-PROVIDE ( esp_rom_spiflash_wait_idle = 0x400622c0 );
-PROVIDE ( esp_rom_spiflash_unlock = 0x400????? );
-*/
diff --git a/tools/sdk/ld/esp32.rom.spiram_incompatible_fns.ld b/tools/sdk/ld/esp32.rom.spiram_incompatible_fns.ld
deleted file mode 100644
index 17a38d35573..00000000000
--- a/tools/sdk/ld/esp32.rom.spiram_incompatible_fns.ld
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- If the spiram compiler workaround is active, these functions from ROM cannot be used. If the workaround is not
- active (e.g. because the system does not use SPI RAM) then these functions are okay to use.
-*/
-PROVIDE ( abs = 0x40056340 );
-PROVIDE ( __ascii_wctomb = 0x40058ef0 );
-PROVIDE ( asctime = 0x40059588 );
-PROVIDE ( asctime_r = 0x40000ec8 );
-PROVIDE ( atoi = 0x400566c4 );
-PROVIDE ( _atoi_r = 0x400566d4 );
-PROVIDE ( atol = 0x400566ec );
-PROVIDE ( _atol_r = 0x400566fc );
-PROVIDE ( bzero = 0x4000c1f4 );
-PROVIDE ( _cleanup = 0x40001df8 );
-PROVIDE ( _cleanup_r = 0x40001d48 );
-PROVIDE ( close = 0x40001778 );
-PROVIDE ( creat = 0x40000e8c );
-PROVIDE ( ctime = 0x400595b0 );
-PROVIDE ( ctime_r = 0x400595c4 );
-PROVIDE ( div = 0x40056348 );
-PROVIDE ( __dummy_lock = 0x4000c728 );
-PROVIDE ( __dummy_lock_try = 0x4000c730 );
-PROVIDE ( __env_lock = 0x40001fd4 );
-PROVIDE ( __env_unlock = 0x40001fe0 );
-PROVIDE ( fclose = 0x400020ac );
-PROVIDE ( _fclose_r = 0x40001fec );
-PROVIDE ( fflush = 0x40059394 );
-PROVIDE ( _fflush_r = 0x40059320 );
-PROVIDE ( _findenv_r = 0x40001f44 );
-PROVIDE ( __fp_lock_all = 0x40001f1c );
-PROVIDE ( __fp_unlock_all = 0x40001f30 );
-PROVIDE ( fputwc = 0x40058ea8 );
-PROVIDE ( __fputwc = 0x40058da0 );
-PROVIDE ( _fputwc_r = 0x40058e4c );
-PROVIDE ( _fwalk = 0x4000c738 );
-PROVIDE ( _fwalk_reent = 0x4000c770 );
-PROVIDE ( __get_current_time_locale = 0x40001834 );
-PROVIDE ( _getenv_r = 0x40001fbc );
-PROVIDE ( __gettzinfo = 0x40001fcc );
-PROVIDE ( gmtime = 0x40059848 );
-PROVIDE ( gmtime_r = 0x40059868 );
-PROVIDE ( isalnum = 0x40000f04 );
-PROVIDE ( isalpha = 0x40000f18 );
-PROVIDE ( isascii = 0x4000c20c );
-PROVIDE ( _isatty_r = 0x40000ea0 );
-PROVIDE ( isblank = 0x40000f2c );
-PROVIDE ( iscntrl = 0x40000f50 );
-PROVIDE ( isdigit = 0x40000f64 );
-PROVIDE ( isgraph = 0x40000f94 );
-PROVIDE ( islower = 0x40000f78 );
-PROVIDE ( isprint = 0x40000fa8 );
-PROVIDE ( ispunct = 0x40000fc0 );
-PROVIDE ( isspace = 0x40000fd4 );
-PROVIDE ( isupper = 0x40000fe8 );
-PROVIDE ( itoa = 0x400566b4 );
-PROVIDE ( __itoa = 0x40056678 );
-PROVIDE ( labs = 0x40056370 );
-PROVIDE ( ldiv = 0x40056378 );
-PROVIDE ( __locale_charset = 0x40059540 );
-PROVIDE ( __locale_cjk_lang = 0x40059558 );
-PROVIDE ( localeconv = 0x4005957c );
-PROVIDE ( _localeconv_r = 0x40059560 );
-PROVIDE ( __locale_mb_cur_max = 0x40059548 );
-PROVIDE ( __locale_msgcharset = 0x40059550 );
-PROVIDE ( localtime = 0x400595dc );
-PROVIDE ( localtime_r = 0x400595fc );
-PROVIDE ( longjmp = 0x400562cc );
-PROVIDE ( memccpy = 0x4000c220 );
-PROVIDE ( memchr = 0x4000c244 );
-PROVIDE ( memcmp = 0x4000c260 );
-PROVIDE ( memcpy = 0x4000c2c8 );
-PROVIDE ( memmove = 0x4000c3c0 );
-PROVIDE ( memrchr = 0x4000c400 );
-PROVIDE ( memset = 0x4000c44c );
-PROVIDE ( mktime = 0x4005a5e8 );
-PROVIDE ( open = 0x4000178c );
-PROVIDE ( qsort = 0x40056424 );
-PROVIDE ( rand = 0x40001058 );
-PROVIDE ( rand_r = 0x400010d4 );
-PROVIDE ( read = 0x400017dc );
-PROVIDE ( sbrk = 0x400017f4 );
-PROVIDE ( __sccl = 0x4000c498 );
-PROVIDE ( __sclose = 0x400011b8 );
-PROVIDE ( __seofread = 0x40001148 );
-PROVIDE ( setjmp = 0x40056268 );
-PROVIDE ( setlocale = 0x40059568 );
-PROVIDE ( _setlocale_r = 0x4005950c );
-PROVIDE ( __sflush_r = 0x400591e0 );
-PROVIDE ( __sfmoreglue = 0x40001dc8 );
-PROVIDE ( __sfp = 0x40001e90 );
-PROVIDE ( __sfp_lock_acquire = 0x40001e08 );
-PROVIDE ( __sfp_lock_release = 0x40001e14 );
-PROVIDE ( __sfputs_r = 0x40057790 );
-PROVIDE ( __sfvwrite_r = 0x4005893c );
-PROVIDE ( __sinit = 0x40001e38 );
-PROVIDE ( __sinit_lock_acquire = 0x40001e20 );
-PROVIDE ( __sinit_lock_release = 0x40001e2c );
-PROVIDE ( __smakebuf_r = 0x40059108 );
-PROVIDE ( srand = 0x40001004 );
-PROVIDE ( __sread = 0x40001118 );
-PROVIDE ( __srefill_r = 0x400593d4 );
-PROVIDE ( __sseek = 0x40001184 );
-PROVIDE ( __ssprint_r = 0x40056ff8 );
-PROVIDE ( __ssputs_r = 0x40056f2c );
-PROVIDE ( __ssrefill_r = 0x40057fec );
-PROVIDE ( strcasecmp = 0x400011cc );
-PROVIDE ( strcasestr = 0x40001210 );
-PROVIDE ( strcat = 0x4000c518 );
-PROVIDE ( strchr = 0x4000c53c );
-PROVIDE ( strcmp = 0x40001274 );
-PROVIDE ( strcoll = 0x40001398 );
-PROVIDE ( strcpy = 0x400013ac );
-PROVIDE ( strcspn = 0x4000c558 );
-PROVIDE ( strdup = 0x4000143c );
-PROVIDE ( _strdup_r = 0x40001450 );
-PROVIDE ( strftime = 0x40059ab4 );
-PROVIDE ( strlcat = 0x40001470 );
-PROVIDE ( strlcpy = 0x4000c584 );
-PROVIDE ( strlen = 0x400014c0 );
-PROVIDE ( strlwr = 0x40001524 );
-PROVIDE ( strncasecmp = 0x40001550 );
-PROVIDE ( strncat = 0x4000c5c4 );
-PROVIDE ( strncmp = 0x4000c5f4 );
-PROVIDE ( strncpy = 0x400015d4 );
-PROVIDE ( strndup = 0x400016b0 );
-PROVIDE ( _strndup_r = 0x400016c4 );
-PROVIDE ( strnlen = 0x4000c628 );
-PROVIDE ( strrchr = 0x40001708 );
-PROVIDE ( strsep = 0x40001734 );
-PROVIDE ( strspn = 0x4000c648 );
-PROVIDE ( strstr = 0x4000c674 );
-PROVIDE ( __strtok_r = 0x4000c6a8 );
-PROVIDE ( strtok_r = 0x4000c70c );
-PROVIDE ( strtol = 0x4005681c );
-PROVIDE ( _strtol_r = 0x40056714 );
-PROVIDE ( strtoul = 0x4005692c );
-PROVIDE ( _strtoul_r = 0x40056834 );
-PROVIDE ( strupr = 0x4000174c );
-PROVIDE ( __submore = 0x40058f3c );
-PROVIDE ( _sungetc_r = 0x40057f6c );
-PROVIDE ( __swbuf = 0x40058cb4 );
-PROVIDE ( __swbuf_r = 0x40058bec );
-PROVIDE ( __swrite = 0x40001150 );
-PROVIDE ( __swsetup_r = 0x40058cc8 );
-PROVIDE ( time = 0x40001844 );
-PROVIDE ( __time_load_locale = 0x4000183c );
-PROVIDE ( times = 0x40001808 );
-PROVIDE ( toascii = 0x4000c720 );
-PROVIDE ( tolower = 0x40001868 );
-PROVIDE ( toupper = 0x40001884 );
-PROVIDE ( __tzcalc_limits = 0x400018a0 );
-PROVIDE ( __tz_lock = 0x40001a04 );
-PROVIDE ( tzset = 0x40001a1c );
-PROVIDE ( _tzset_r = 0x40001a28 );
-PROVIDE ( __tz_unlock = 0x40001a10 );
-PROVIDE ( ungetc = 0x400590f4 );
-PROVIDE ( _ungetc_r = 0x40058fa0 );
-PROVIDE ( utoa = 0x40056258 );
-PROVIDE ( __utoa = 0x400561f0 );
-PROVIDE ( wcrtomb = 0x40058920 );
-PROVIDE ( _wcrtomb_r = 0x400588d8 );
-PROVIDE ( _wctomb_r = 0x40058f14 );
-PROVIDE ( write = 0x4000181c );
diff --git a/tools/sdk/ld/esp32_out.ld b/tools/sdk/ld/esp32_out.ld
deleted file mode 100644
index 21c516fc8c3..00000000000
--- a/tools/sdk/ld/esp32_out.ld
+++ /dev/null
@@ -1,74 +0,0 @@
-/* ESP32 Linker Script Memory Layout
-
-   This file describes the memory layout (memory blocks) as virtual
-   memory addresses.
-
-   esp32.project.ld contains output sections to link compiler output
-   into these memory blocks.
-
-   ***
-
-   This linker script is passed through the C preprocessor to include
-   configuration options.
-
-   Please use preprocessor features sparingly! Restrict
-   to simple macros with numeric values, and/or #if/#endif blocks.
-*/
-/*
- *
- * Automatically generated file; DO NOT EDIT.
- * Espressif IoT Development Framework Configuration
- *
- */
-/* If BT is not built at all */
-MEMORY
-{
-  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
-  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
-  are connected to the data port of the CPU and eg allow bytewise access. */
-  /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
-  iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
-  /* Even though the segment name is iram, it is actually mapped to flash
-  */
-  iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
-  /*
-    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
-    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
-    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
-  */
-  /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
-
-     Enabling Bluetooth & Trace Memory features in menuconfig will decrease
-     the amount of RAM available.
-
-     Note: Length of this section *should* be 0x50000, and this extra DRAM is available
-     in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
-     additional static memory temporarily cannot be used.
-  */
-  dram0_0_seg (RW) : org = 0x3FFB0000 + 0xdb5c,
-                                     len = 0x2c200 - 0xdb5c
-  /* Flash mapped constant data */
-  drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
-  /* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
-  /* RTC fast memory (executable). Persists over deep sleep.
-   */
-  rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
-  /* RTC fast memory (same block as above), viewed from data bus */
-  rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000
-  /* RTC slow memory (data accessible). Persists over deep sleep.
-
-     Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
-  */
-  rtc_slow_seg(RW) : org = 0x50000000 + 512,
-                                     len = 0x1000 - 512
-  /* external memory ,including data and text */
-  extern_ram_seg(RWX) : org = 0x3F800000,
-                                     len = 0x400000
-}
-/* Heap ends at top of dram0_0_seg */
-_heap_end = 0x40000000 - 0x0;
-_data_seg_org = ORIGIN(rtc_data_seg);
-/* The lines below define location alias for .rtc.data section based on Kconfig option. 
-   When the option is not defined then use slow memory segment 
-   else the data will be placed in fast memory segment */
-REGION_ALIAS("rtc_data_location", rtc_slow_seg );
diff --git a/tools/sdk/lib/libapp_trace.a b/tools/sdk/lib/libapp_trace.a
deleted file mode 100644
index 4b5d0207cf2..00000000000
Binary files a/tools/sdk/lib/libapp_trace.a and /dev/null differ
diff --git a/tools/sdk/lib/libapp_update.a b/tools/sdk/lib/libapp_update.a
deleted file mode 100644
index 5f2a2b39ae3..00000000000
Binary files a/tools/sdk/lib/libapp_update.a and /dev/null differ
diff --git a/tools/sdk/lib/libasio.a b/tools/sdk/lib/libasio.a
deleted file mode 100644
index 74263fbaf98..00000000000
Binary files a/tools/sdk/lib/libasio.a and /dev/null differ
diff --git a/tools/sdk/lib/libbootloader_support.a b/tools/sdk/lib/libbootloader_support.a
deleted file mode 100644
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diff --git a/tools/sdk/sdkconfig b/tools/sdk/sdkconfig
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--- a/tools/sdk/sdkconfig
+++ /dev/null
@@ -1,953 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# Espressif IoT Development Framework Configuration
-#
-CONFIG_IDF_TARGET="esp32"
-CONFIG_IDF_FIRMWARE_CHIP_ID=0x0000
-
-#
-# SDK tool configuration
-#
-CONFIG_TOOLPREFIX="xtensa-esp32-elf-"
-CONFIG_PYTHON="python"
-CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y
-
-#
-# Application manager
-#
-CONFIG_APP_COMPILE_TIME_DATE=y
-CONFIG_APP_EXCLUDE_PROJECT_VER_VAR=
-CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR=
-CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
-
-#
-# Arduino Configuration
-#
-CONFIG_ENABLE_ARDUINO_DEPENDS=y
-CONFIG_AUTOSTART_ARDUINO=y
-CONFIG_ARDUINO_RUN_CORE0=
-CONFIG_ARDUINO_RUN_CORE1=y
-CONFIG_ARDUINO_RUN_NO_AFFINITY=
-CONFIG_ARDUINO_RUNNING_CORE=1
-CONFIG_ARDUINO_EVENT_RUN_CORE0=
-CONFIG_ARDUINO_EVENT_RUN_CORE1=y
-CONFIG_ARDUINO_EVENT_RUN_NO_AFFINITY=
-CONFIG_ARDUINO_EVENT_RUNNING_CORE=1
-CONFIG_ARDUINO_UDP_RUN_CORE0=
-CONFIG_ARDUINO_UDP_RUN_CORE1=y
-CONFIG_ARDUINO_UDP_RUN_NO_AFFINITY=
-CONFIG_ARDUINO_UDP_TASK_PRIORITY=3
-CONFIG_ARDUINO_UDP_RUNNING_CORE=1
-CONFIG_DISABLE_HAL_LOCKS=
-
-#
-# Debug Log Configuration
-#
-CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_NONE=
-CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_ERROR=y
-CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_WARN=
-CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_INFO=
-CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_DEBUG=
-CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_VERBOSE=
-CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL=1
-CONFIG_ARDUHAL_LOG_COLORS=
-CONFIG_ARDUHAL_ESP_LOG=y
-CONFIG_ARDUHAL_PARTITION_SCHEME_DEFAULT=y
-CONFIG_ARDUHAL_PARTITION_SCHEME_MINIMAL=
-CONFIG_ARDUHAL_PARTITION_SCHEME_NO_OTA=
-CONFIG_ARDUHAL_PARTITION_SCHEME_HUGE_APP=
-CONFIG_ARDUHAL_PARTITION_SCHEME_MIN_SPIFFS=
-CONFIG_ARDUHAL_PARTITION_SCHEME="default"
-CONFIG_AUTOCONNECT_WIFI=
-CONFIG_ARDUINO_SELECTIVE_COMPILATION=
-
-#
-# Bootloader config
-#
-CONFIG_LOG_BOOTLOADER_LEVEL_NONE=y
-CONFIG_LOG_BOOTLOADER_LEVEL_ERROR=
-CONFIG_LOG_BOOTLOADER_LEVEL_WARN=
-CONFIG_LOG_BOOTLOADER_LEVEL_INFO=
-CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG=
-CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE=
-CONFIG_LOG_BOOTLOADER_LEVEL=0
-CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V=
-CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y
-CONFIG_BOOTLOADER_FACTORY_RESET=
-CONFIG_BOOTLOADER_APP_TEST=
-CONFIG_BOOTLOADER_WDT_ENABLE=y
-CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE=
-CONFIG_BOOTLOADER_WDT_TIME_MS=9000
-CONFIG_APP_ROLLBACK_ENABLE=
-
-#
-# Security features
-#
-CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT=
-CONFIG_SECURE_BOOT_ENABLED=
-CONFIG_FLASH_ENCRYPTION_ENABLED=
-
-#
-# Serial flasher config
-#
-CONFIG_ESPTOOLPY_PORT="/dev/cu.usbserial-DO00EAB0"
-CONFIG_ESPTOOLPY_BAUD_115200B=
-CONFIG_ESPTOOLPY_BAUD_230400B=
-CONFIG_ESPTOOLPY_BAUD_921600B=y
-CONFIG_ESPTOOLPY_BAUD_2MB=
-CONFIG_ESPTOOLPY_BAUD_OTHER=
-CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
-CONFIG_ESPTOOLPY_BAUD=921600
-CONFIG_ESPTOOLPY_COMPRESSED=y
-CONFIG_FLASHMODE_QIO=
-CONFIG_FLASHMODE_QOUT=
-CONFIG_FLASHMODE_DIO=y
-CONFIG_FLASHMODE_DOUT=
-CONFIG_ESPTOOLPY_FLASHMODE="dio"
-CONFIG_ESPTOOLPY_FLASHFREQ_80M=
-CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
-CONFIG_ESPTOOLPY_FLASHFREQ_26M=
-CONFIG_ESPTOOLPY_FLASHFREQ_20M=
-CONFIG_ESPTOOLPY_FLASHFREQ="40m"
-CONFIG_ESPTOOLPY_FLASHSIZE_1MB=
-CONFIG_ESPTOOLPY_FLASHSIZE_2MB=
-CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
-CONFIG_ESPTOOLPY_FLASHSIZE_8MB=
-CONFIG_ESPTOOLPY_FLASHSIZE_16MB=
-CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
-CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
-CONFIG_ESPTOOLPY_BEFORE_RESET=y
-CONFIG_ESPTOOLPY_BEFORE_NORESET=
-CONFIG_ESPTOOLPY_BEFORE="default_reset"
-CONFIG_ESPTOOLPY_AFTER_RESET=y
-CONFIG_ESPTOOLPY_AFTER_NORESET=
-CONFIG_ESPTOOLPY_AFTER="hard_reset"
-CONFIG_MONITOR_BAUD_9600B=
-CONFIG_MONITOR_BAUD_57600B=
-CONFIG_MONITOR_BAUD_115200B=y
-CONFIG_MONITOR_BAUD_230400B=
-CONFIG_MONITOR_BAUD_921600B=
-CONFIG_MONITOR_BAUD_2MB=
-CONFIG_MONITOR_BAUD_OTHER=
-CONFIG_MONITOR_BAUD_OTHER_VAL=115200
-CONFIG_MONITOR_BAUD=115200
-
-#
-# Partition Table
-#
-CONFIG_PARTITION_TABLE_SINGLE_APP=y
-CONFIG_PARTITION_TABLE_TWO_OTA=
-CONFIG_PARTITION_TABLE_CUSTOM=
-CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
-CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv"
-CONFIG_PARTITION_TABLE_OFFSET=0x8000
-CONFIG_PARTITION_TABLE_MD5=y
-
-#
-# Compiler options
-#
-CONFIG_OPTIMIZATION_LEVEL_DEBUG=y
-CONFIG_OPTIMIZATION_LEVEL_RELEASE=
-CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
-CONFIG_OPTIMIZATION_ASSERTIONS_SILENT=
-CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED=
-CONFIG_CXX_EXCEPTIONS=y
-CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE=0
-CONFIG_STACK_CHECK_NONE=
-CONFIG_STACK_CHECK_NORM=y
-CONFIG_STACK_CHECK_STRONG=
-CONFIG_STACK_CHECK_ALL=
-CONFIG_STACK_CHECK=y
-CONFIG_WARN_WRITE_STRINGS=y
-CONFIG_DISABLE_GCC8_WARNINGS=
-
-#
-# Component config
-#
-
-#
-# Application Level Tracing
-#
-CONFIG_ESP32_APPTRACE_DEST_TRAX=
-CONFIG_ESP32_APPTRACE_DEST_NONE=y
-CONFIG_ESP32_APPTRACE_ENABLE=
-CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
-CONFIG_AWS_IOT_SDK=
-
-#
-# Bluetooth
-#
-CONFIG_BT_ENABLED=y
-
-#
-# Bluetooth controller
-#
-CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY=
-CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY=
-CONFIG_BTDM_CONTROLLER_MODE_BTDM=y
-CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN=3
-CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN=2
-CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN=0
-CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=0
-CONFIG_BTDM_CTRL_AUTO_LATENCY=
-CONFIG_BTDM_CTRL_AUTO_LATENCY_EFF=
-CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT=y
-CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF=y
-CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=3
-CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=2
-CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0
-CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_0=y
-CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_1=
-CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0
-CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI=y
-CONFIG_BTDM_CONTROLLER_HCI_MODE_UART_H4=
-
-#
-# MODEM SLEEP Options
-#
-CONFIG_BTDM_CONTROLLER_MODEM_SLEEP=y
-CONFIG_BTDM_MODEM_SLEEP_MODE_ORIG=y
-CONFIG_BTDM_MODEM_SLEEP_MODE_EVED=
-CONFIG_BTDM_LPCLK_SEL_MAIN_XTAL=y
-CONFIG_BLE_SCAN_DUPLICATE=y
-CONFIG_SCAN_DUPLICATE_BY_DEVICE_ADDR=y
-CONFIG_SCAN_DUPLICATE_BY_ADV_DATA=
-CONFIG_SCAN_DUPLICATE_BY_ADV_DATA_AND_DEVICE_ADDR=
-CONFIG_SCAN_DUPLICATE_TYPE=0
-CONFIG_DUPLICATE_SCAN_CACHE_SIZE=20
-CONFIG_BLE_MESH_SCAN_DUPLICATE_EN=
-CONFIG_BTDM_CONTROLLER_FULL_SCAN_SUPPORTED=y
-CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED=y
-CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM=100
-CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD=20
-CONFIG_BTDM_COEX_BT_OPTIONS=
-CONFIG_BLUEDROID_ENABLED=y
-CONFIG_BLUEDROID_PINNED_TO_CORE_0=y
-CONFIG_BLUEDROID_PINNED_TO_CORE_1=
-CONFIG_BLUEDROID_PINNED_TO_CORE=0
-CONFIG_BTC_TASK_STACK_SIZE=8192
-CONFIG_BTU_TASK_STACK_SIZE=4096
-CONFIG_BLUEDROID_MEM_DEBUG=
-CONFIG_CLASSIC_BT_ENABLED=y
-CONFIG_A2DP_ENABLE=y
-CONFIG_A2DP_SINK_TASK_STACK_SIZE=2048
-CONFIG_A2DP_SOURCE_TASK_STACK_SIZE=2048
-CONFIG_BT_SPP_ENABLED=y
-CONFIG_HFP_ENABLE=y
-CONFIG_HFP_CLIENT_ENABLE=y
-CONFIG_HFP_AUDIO_DATA_PATH_PCM=y
-CONFIG_HFP_AUDIO_DATA_PATH_HCI=
-CONFIG_BT_SSP_ENABLED=y
-CONFIG_GATTS_ENABLE=y
-CONFIG_GATTS_SEND_SERVICE_CHANGE_MANUAL=
-CONFIG_GATTS_SEND_SERVICE_CHANGE_AUTO=y
-CONFIG_GATTS_SEND_SERVICE_CHANGE_MODE=0
-CONFIG_GATTC_ENABLE=y
-CONFIG_GATTC_CACHE_NVS_FLASH=
-CONFIG_BLE_SMP_ENABLE=y
-CONFIG_SMP_SLAVE_CON_PARAMS_UPD_ENABLE=
-CONFIG_BT_STACK_NO_LOG=y
-CONFIG_BT_ACL_CONNECTIONS=4
-CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST=y
-CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY=y
-CONFIG_BLE_HOST_QUEUE_CONGESTION_CHECK=
-CONFIG_SMP_ENABLE=y
-CONFIG_BLE_ACTIVE_SCAN_REPORT_ADV_SCAN_RSP_INDIVIDUALLY=
-CONFIG_BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT=30
-CONFIG_BT_RESERVE_DRAM=0xdb5c
-CONFIG_BLE_MESH=
-
-#
-# Driver configurations
-#
-
-#
-# ADC configuration
-#
-CONFIG_ADC_FORCE_XPD_FSM=
-CONFIG_ADC2_DISABLE_DAC=y
-
-#
-# SPI configuration
-#
-CONFIG_SPI_MASTER_IN_IRAM=
-CONFIG_SPI_MASTER_ISR_IN_IRAM=y
-CONFIG_SPI_SLAVE_IN_IRAM=
-CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
-
-#
-# eFuse Bit Manager
-#
-CONFIG_EFUSE_CUSTOM_TABLE=
-CONFIG_EFUSE_VIRTUAL=
-CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE=
-CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y
-CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT=
-CONFIG_EFUSE_MAX_BLK_LEN=192
-CONFIG_C_IMPL=
-CONFIG_XTENSA_IMPL=y
-
-#
-# ESP-FACE Configuration
-#
-CONFIG_MTMN_LITE_QUANT=y
-CONFIG_MTMN_LITE_FLOAT=
-CONFIG_MTMN_HEAVY_QUANT=
-CONFIG_FRMN=
-CONFIG_MFN56_1X=y
-CONFIG_MFN56_2X=
-CONFIG_MFN56_3X=
-CONFIG_MFN56_4X=
-
-#
-# Object Detection
-#
-CONFIG_DETECT_WITH_LANDMARK=
-
-#
-# Pose Estimation
-#
-CONFIG_HD_NANO1=y
-CONFIG_HD_LITE1=
-CONFIG_HP_NANO1=y
-CONFIG_HP_LITE1=
-
-#
-# ESP32-specific
-#
-CONFIG_IDF_TARGET_ESP32=y
-CONFIG_ESP32_ECO3_CACHE_LOCK_FIX=y
-CONFIG_ESP32_REV_MIN_0=y
-CONFIG_ESP32_REV_MIN_1=
-CONFIG_ESP32_REV_MIN_2=
-CONFIG_ESP32_REV_MIN_3=
-CONFIG_ESP32_REV_MIN=0
-CONFIG_ESP32_DPORT_WORKAROUND=y
-CONFIG_ESP32_DEFAULT_CPU_FREQ_80=
-CONFIG_ESP32_DEFAULT_CPU_FREQ_160=
-CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
-CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
-CONFIG_SPIRAM_SUPPORT=y
-
-#
-# SPI RAM config
-#
-CONFIG_SPIRAM_BOOT_INIT=
-CONFIG_SPIRAM_USE_MEMMAP=
-CONFIG_SPIRAM_USE_CAPS_ALLOC=y
-CONFIG_SPIRAM_USE_MALLOC=
-CONFIG_SPIRAM_TYPE_AUTO=y
-CONFIG_SPIRAM_TYPE_ESPPSRAM32=
-CONFIG_SPIRAM_TYPE_ESPPSRAM64=
-CONFIG_SPIRAM_SIZE=-1
-CONFIG_SPIRAM_SPEED_40M=y
-CONFIG_SPIRAM_CACHE_WORKAROUND=y
-CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
-CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
-CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST=
-CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=
-
-#
-# PSRAM clock and cs IO for ESP32-DOWD
-#
-CONFIG_D0WD_PSRAM_CLK_IO=17
-CONFIG_D0WD_PSRAM_CS_IO=16
-
-#
-# PSRAM clock and cs IO for ESP32-D2WD
-#
-CONFIG_D2WD_PSRAM_CLK_IO=9
-CONFIG_D2WD_PSRAM_CS_IO=10
-
-#
-# PSRAM clock and cs IO for ESP32-PICO
-#
-CONFIG_PICO_PSRAM_CS_IO=10
-CONFIG_SPIRAM_SPIWP_SD3_PIN=7
-CONFIG_SPIRAM_2T_MODE=
-CONFIG_MEMMAP_TRACEMEM=
-CONFIG_MEMMAP_TRACEMEM_TWOBANKS=
-CONFIG_ESP32_TRAX=
-CONFIG_TRACEMEM_RESERVE_DRAM=0x0
-CONFIG_TWO_UNIVERSAL_MAC_ADDRESS=
-CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y
-CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4
-CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
-CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2048
-CONFIG_MAIN_TASK_STACK_SIZE=4096
-CONFIG_IPC_TASK_STACK_SIZE=1024
-CONFIG_TIMER_TASK_STACK_SIZE=4096
-CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
-CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF=
-CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR=
-CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF=
-CONFIG_NEWLIB_STDIN_LINE_ENDING_LF=
-CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
-CONFIG_NEWLIB_NANO_FORMAT=
-CONFIG_CONSOLE_UART_DEFAULT=y
-CONFIG_CONSOLE_UART_CUSTOM=
-CONFIG_CONSOLE_UART_NONE=
-CONFIG_CONSOLE_UART_NUM=0
-CONFIG_CONSOLE_UART_BAUDRATE=115200
-CONFIG_ULP_COPROC_ENABLED=y
-CONFIG_ULP_COPROC_RESERVE_MEM=512
-CONFIG_ESP32_PANIC_PRINT_HALT=
-CONFIG_ESP32_PANIC_PRINT_REBOOT=y
-CONFIG_ESP32_PANIC_SILENT_REBOOT=
-CONFIG_ESP32_PANIC_GDBSTUB=
-CONFIG_ESP32_DEBUG_OCDAWARE=y
-CONFIG_ESP32_DEBUG_STUBS_ENABLE=y
-CONFIG_INT_WDT=y
-CONFIG_INT_WDT_TIMEOUT_MS=300
-CONFIG_INT_WDT_CHECK_CPU1=y
-CONFIG_TASK_WDT=y
-CONFIG_TASK_WDT_PANIC=y
-CONFIG_TASK_WDT_TIMEOUT_S=5
-CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
-CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=
-CONFIG_BROWNOUT_DET=y
-CONFIG_BROWNOUT_DET_LVL_SEL_0=y
-CONFIG_BROWNOUT_DET_LVL_SEL_1=
-CONFIG_BROWNOUT_DET_LVL_SEL_2=
-CONFIG_BROWNOUT_DET_LVL_SEL_3=
-CONFIG_BROWNOUT_DET_LVL_SEL_4=
-CONFIG_BROWNOUT_DET_LVL_SEL_5=
-CONFIG_BROWNOUT_DET_LVL_SEL_6=
-CONFIG_BROWNOUT_DET_LVL_SEL_7=
-CONFIG_BROWNOUT_DET_LVL=0
-CONFIG_REDUCE_PHY_TX_POWER=y
-CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
-CONFIG_ESP32_TIME_SYSCALL_USE_RTC=
-CONFIG_ESP32_TIME_SYSCALL_USE_FRC1=
-CONFIG_ESP32_TIME_SYSCALL_USE_NONE=
-CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
-CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL=
-CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC=
-CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256=
-CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
-CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
-CONFIG_ESP32_XTAL_FREQ_40=
-CONFIG_ESP32_XTAL_FREQ_26=
-CONFIG_ESP32_XTAL_FREQ_AUTO=y
-CONFIG_ESP32_XTAL_FREQ=0
-CONFIG_DISABLE_BASIC_ROM_CONSOLE=
-CONFIG_ESP_TIMER_PROFILING=
-CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS=
-CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
-CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
-
-#
-# Wi-Fi
-#
-CONFIG_SW_COEXIST_ENABLE=y
-CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=16
-CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=
-CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
-CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
-CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32
-CONFIG_ESP32_WIFI_CSI_ENABLED=
-CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
-CONFIG_ESP32_WIFI_TX_BA_WIN=6
-CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
-CONFIG_ESP32_WIFI_RX_BA_WIN=16
-CONFIG_ESP32_WIFI_NVS_ENABLED=y
-CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
-CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1=
-CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
-CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
-CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE=
-CONFIG_ESP32_WIFI_IRAM_OPT=
-CONFIG_ESP32_WIFI_RX_IRAM_OPT=
-
-#
-# PHY
-#
-CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
-CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION=
-CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
-CONFIG_ESP32_PHY_MAX_TX_POWER=20
-
-#
-# Power Management
-#
-CONFIG_PM_ENABLE=
-
-#
-# Camera configuration
-#
-CONFIG_OV7670_SUPPORT=y
-CONFIG_OV7725_SUPPORT=y
-CONFIG_NT99141_SUPPORT=y
-CONFIG_OV2640_SUPPORT=y
-CONFIG_OV3660_SUPPORT=y
-CONFIG_OV5640_SUPPORT=y
-CONFIG_SCCB_HARDWARE_I2C_PORT0=
-CONFIG_SCCB_HARDWARE_I2C_PORT1=y
-CONFIG_CAMERA_CORE0=
-CONFIG_CAMERA_CORE1=y
-CONFIG_CAMERA_NO_AFFINITY=
-
-#
-# ADC-Calibration
-#
-CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
-CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
-CONFIG_ADC_CAL_LUT_ENABLE=y
-
-#
-# Event Loop Library
-#
-CONFIG_EVENT_LOOP_PROFILING=
-
-#
-# ESP HTTP client
-#
-CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y
-CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH=
-
-#
-# HTTP Server
-#
-CONFIG_HTTPD_MAX_REQ_HDR_LEN=512
-CONFIG_HTTPD_MAX_URI_LEN=512
-CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
-CONFIG_HTTPD_PURGE_BUF_LEN=32
-CONFIG_HTTPD_LOG_PURGE_DATA=
-
-#
-# ESP HTTPS OTA
-#
-CONFIG_OTA_ALLOW_HTTP=
-
-#
-# Core dump
-#
-CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=
-CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=
-CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
-CONFIG_ESP32_ENABLE_COREDUMP=
-
-#
-# Ethernet
-#
-CONFIG_DMA_RX_BUF_NUM=10
-CONFIG_DMA_TX_BUF_NUM=10
-CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y
-CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000
-CONFIG_EMAC_TASK_PRIORITY=20
-CONFIG_EMAC_TASK_STACK_SIZE=3072
-
-#
-# FAT Filesystem support
-#
-CONFIG_FATFS_CODEPAGE_DYNAMIC=
-CONFIG_FATFS_CODEPAGE_437=
-CONFIG_FATFS_CODEPAGE_720=
-CONFIG_FATFS_CODEPAGE_737=
-CONFIG_FATFS_CODEPAGE_771=
-CONFIG_FATFS_CODEPAGE_775=
-CONFIG_FATFS_CODEPAGE_850=y
-CONFIG_FATFS_CODEPAGE_852=
-CONFIG_FATFS_CODEPAGE_855=
-CONFIG_FATFS_CODEPAGE_857=
-CONFIG_FATFS_CODEPAGE_860=
-CONFIG_FATFS_CODEPAGE_861=
-CONFIG_FATFS_CODEPAGE_862=
-CONFIG_FATFS_CODEPAGE_863=
-CONFIG_FATFS_CODEPAGE_864=
-CONFIG_FATFS_CODEPAGE_865=
-CONFIG_FATFS_CODEPAGE_866=
-CONFIG_FATFS_CODEPAGE_869=
-CONFIG_FATFS_CODEPAGE_932=
-CONFIG_FATFS_CODEPAGE_936=
-CONFIG_FATFS_CODEPAGE_949=
-CONFIG_FATFS_CODEPAGE_950=
-CONFIG_FATFS_CODEPAGE=850
-CONFIG_FATFS_LFN_NONE=
-CONFIG_FATFS_LFN_HEAP=
-CONFIG_FATFS_LFN_STACK=y
-CONFIG_FATFS_MAX_LFN=255
-CONFIG_FATFS_API_ENCODING_ANSI_OEM=y
-CONFIG_FATFS_API_ENCODING_UTF_16=
-CONFIG_FATFS_API_ENCODING_UTF_8=
-CONFIG_FATFS_FS_LOCK=0
-CONFIG_FATFS_TIMEOUT_MS=10000
-CONFIG_FATFS_PER_FILE_CACHE=y
-CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y
-
-#
-# Modbus configuration
-#
-CONFIG_MB_QUEUE_LENGTH=20
-CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048
-CONFIG_MB_SERIAL_BUF_SIZE=256
-CONFIG_MB_SERIAL_TASK_PRIO=10
-CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=
-CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_MB_CONTROLLER_STACK_SIZE=4096
-CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
-CONFIG_MB_TIMER_PORT_ENABLED=y
-CONFIG_MB_TIMER_GROUP=0
-CONFIG_MB_TIMER_INDEX=0
-
-#
-# FreeRTOS
-#
-CONFIG_FREERTOS_UNICORE=
-CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
-CONFIG_FREERTOS_CORETIMER_0=y
-CONFIG_FREERTOS_CORETIMER_1=
-CONFIG_FREERTOS_HZ=1000
-CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=
-CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE=
-CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL=
-CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
-CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y
-CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
-CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
-CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
-CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE=
-CONFIG_FREERTOS_ASSERT_DISABLE=
-CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1024
-CONFIG_FREERTOS_ISR_STACKSIZE=1536
-CONFIG_FREERTOS_LEGACY_HOOKS=
-CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
-CONFIG_SUPPORT_STATIC_ALLOCATION=
-CONFIG_TIMER_TASK_PRIORITY=1
-CONFIG_TIMER_TASK_STACK_DEPTH=2048
-CONFIG_TIMER_QUEUE_LENGTH=10
-CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
-CONFIG_FREERTOS_USE_TRACE_FACILITY=
-CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=
-CONFIG_FREERTOS_DEBUG_INTERNALS=
-CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
-CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
-CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=
-
-#
-# Heap memory debugging
-#
-CONFIG_HEAP_POISONING_DISABLED=
-CONFIG_HEAP_POISONING_LIGHT=y
-CONFIG_HEAP_POISONING_COMPREHENSIVE=
-CONFIG_HEAP_TRACING=
-CONFIG_HEAP_TASK_TRACKING=
-
-#
-# libsodium
-#
-CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y
-
-#
-# Log output
-#
-CONFIG_LOG_DEFAULT_LEVEL_NONE=
-CONFIG_LOG_DEFAULT_LEVEL_ERROR=y
-CONFIG_LOG_DEFAULT_LEVEL_WARN=
-CONFIG_LOG_DEFAULT_LEVEL_INFO=
-CONFIG_LOG_DEFAULT_LEVEL_DEBUG=
-CONFIG_LOG_DEFAULT_LEVEL_VERBOSE=
-CONFIG_LOG_DEFAULT_LEVEL=1
-CONFIG_LOG_COLORS=
-
-#
-# LWIP
-#
-CONFIG_L2_TO_L3_COPY=
-CONFIG_ETHARP_SUPPORT_VLAN=
-CONFIG_LWIP_IRAM_OPTIMIZATION=
-CONFIG_LWIP_MAX_SOCKETS=10
-CONFIG_LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS=y
-CONFIG_USE_ONLY_LWIP_SELECT=
-CONFIG_LWIP_SO_LINGER=
-CONFIG_LWIP_SO_REUSE=y
-CONFIG_LWIP_SO_REUSE_RXTOALL=y
-CONFIG_LWIP_SO_RCVBUF=y
-CONFIG_LWIP_IP4_FRAG=y
-CONFIG_LWIP_IP6_FRAG=y
-CONFIG_LWIP_IP4_REASSEMBLY=
-CONFIG_LWIP_IP6_REASSEMBLY=
-CONFIG_LWIP_STATS=
-CONFIG_LWIP_ETHARP_TRUST_IP_MAC=y
-CONFIG_ESP_GRATUITOUS_ARP=y
-CONFIG_GARP_TMR_INTERVAL=60
-CONFIG_TCPIP_RECVMBOX_SIZE=32
-CONFIG_LWIP_DHCP_DOES_ARP_CHECK=
-CONFIG_LWIP_DHCP_RESTORE_LAST_IP=y
-
-#
-# DHCP server
-#
-CONFIG_LWIP_DHCPS_LEASE_UNIT=60
-CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
-CONFIG_LWIP_AUTOIP=
-CONFIG_LWIP_IPV6_AUTOCONFIG=
-CONFIG_LWIP_NETIF_LOOPBACK=y
-CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8
-
-#
-# TCP
-#
-CONFIG_LWIP_TCP_ISN_HOOK=y
-CONFIG_LWIP_MAX_ACTIVE_TCP=16
-CONFIG_LWIP_MAX_LISTENING_TCP=16
-CONFIG_TCP_MAXRTX=12
-CONFIG_TCP_SYNMAXRTX=6
-CONFIG_TCP_MSS=1436
-CONFIG_TCP_MSL=60000
-CONFIG_TCP_SND_BUF_DEFAULT=5744
-CONFIG_TCP_WND_DEFAULT=5744
-CONFIG_TCP_RECVMBOX_SIZE=6
-CONFIG_TCP_QUEUE_OOSEQ=y
-CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES=
-CONFIG_TCP_OVERSIZE_MSS=y
-CONFIG_TCP_OVERSIZE_QUARTER_MSS=
-CONFIG_TCP_OVERSIZE_DISABLE=
-CONFIG_LWIP_TCP_RTO_TIME=3000
-
-#
-# UDP
-#
-CONFIG_LWIP_MAX_UDP_PCBS=16
-CONFIG_UDP_RECVMBOX_SIZE=6
-CONFIG_TCPIP_TASK_STACK_SIZE=2560
-CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=
-CONFIG_TCPIP_TASK_AFFINITY_CPU0=y
-CONFIG_TCPIP_TASK_AFFINITY_CPU1=
-CONFIG_TCPIP_TASK_AFFINITY=0x0
-CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3
-CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5
-CONFIG_PPP_SUPPORT=y
-CONFIG_PPP_NOTIFY_PHASE_SUPPORT=
-CONFIG_PPP_PAP_SUPPORT=y
-CONFIG_PPP_CHAP_SUPPORT=y
-CONFIG_PPP_MSCHAP_SUPPORT=y
-CONFIG_PPP_MPPE_SUPPORT=y
-CONFIG_PPP_DEBUG_ON=
-
-#
-# ICMP
-#
-CONFIG_LWIP_MULTICAST_PING=
-CONFIG_LWIP_BROADCAST_PING=
-
-#
-# LWIP RAW API
-#
-CONFIG_LWIP_MAX_RAW_PCBS=16
-
-#
-# SNTP
-#
-CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1
-CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
-CONFIG_LWIP_ESP_LWIP_ASSERT=y
-
-#
-# mbedTLS
-#
-CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y
-CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC=
-CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=
-CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC=
-CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384
-CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=
-CONFIG_MBEDTLS_DEBUG=
-CONFIG_MBEDTLS_ECP_RESTARTABLE=
-CONFIG_MBEDTLS_CMAC_C=
-CONFIG_MBEDTLS_HARDWARE_AES=y
-CONFIG_MBEDTLS_HARDWARE_MPI=
-CONFIG_MBEDTLS_HARDWARE_SHA=
-CONFIG_MBEDTLS_HAVE_TIME=y
-CONFIG_MBEDTLS_HAVE_TIME_DATE=
-CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y
-CONFIG_MBEDTLS_TLS_SERVER_ONLY=
-CONFIG_MBEDTLS_TLS_CLIENT_ONLY=
-CONFIG_MBEDTLS_TLS_DISABLED=
-CONFIG_MBEDTLS_TLS_SERVER=y
-CONFIG_MBEDTLS_TLS_CLIENT=y
-CONFIG_MBEDTLS_TLS_ENABLED=y
-
-#
-# TLS Key Exchange Methods
-#
-CONFIG_MBEDTLS_PSK_MODES=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
-CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
-CONFIG_MBEDTLS_SSL_PROTO_SSL3=
-CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
-CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
-CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
-CONFIG_MBEDTLS_SSL_PROTO_DTLS=
-CONFIG_MBEDTLS_SSL_ALPN=y
-CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y
-
-#
-# Symmetric Ciphers
-#
-CONFIG_MBEDTLS_AES_C=y
-CONFIG_MBEDTLS_CAMELLIA_C=
-CONFIG_MBEDTLS_DES_C=
-CONFIG_MBEDTLS_RC4_DISABLED=y
-CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT=
-CONFIG_MBEDTLS_RC4_ENABLED=
-CONFIG_MBEDTLS_BLOWFISH_C=
-CONFIG_MBEDTLS_XTEA_C=
-CONFIG_MBEDTLS_CCM_C=y
-CONFIG_MBEDTLS_GCM_C=y
-CONFIG_MBEDTLS_RIPEMD160_C=
-
-#
-# Certificates
-#
-CONFIG_MBEDTLS_PEM_PARSE_C=y
-CONFIG_MBEDTLS_PEM_WRITE_C=y
-CONFIG_MBEDTLS_X509_CRL_PARSE_C=y
-CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
-CONFIG_MBEDTLS_ECP_C=y
-CONFIG_MBEDTLS_ECDH_C=y
-CONFIG_MBEDTLS_ECDSA_C=y
-CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y
-CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
-
-#
-# mDNS
-#
-CONFIG_MDNS_MAX_SERVICES=10
-
-#
-# ESP-MQTT Configurations
-#
-CONFIG_MQTT_PROTOCOL_311=y
-CONFIG_MQTT_TRANSPORT_SSL=y
-CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
-CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
-CONFIG_MQTT_USE_CUSTOM_CONFIG=
-CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED=
-CONFIG_MQTT_CUSTOM_OUTBOX=
-
-#
-# NVS
-#
-
-#
-# OpenSSL
-#
-CONFIG_OPENSSL_DEBUG=
-CONFIG_OPENSSL_ASSERT_DO_NOTHING=y
-CONFIG_OPENSSL_ASSERT_EXIT=
-
-#
-# PThreads
-#
-CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
-CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=2048
-CONFIG_PTHREAD_STACK_MIN=768
-CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y
-CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0=
-CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1=
-CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
-CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
-
-#
-# SPI Flash driver
-#
-CONFIG_SPI_FLASH_VERIFY_WRITE=
-CONFIG_SPI_FLASH_ENABLE_COUNTERS=
-CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
-CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
-CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS=
-CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED=
-CONFIG_SPI_FLASH_YIELD_DURING_ERASE=
-
-#
-# SPIFFS Configuration
-#
-CONFIG_SPIFFS_MAX_PARTITIONS=3
-
-#
-# SPIFFS Cache Configuration
-#
-CONFIG_SPIFFS_CACHE=y
-CONFIG_SPIFFS_CACHE_WR=y
-CONFIG_SPIFFS_CACHE_STATS=
-CONFIG_SPIFFS_PAGE_CHECK=y
-CONFIG_SPIFFS_GC_MAX_RUNS=10
-CONFIG_SPIFFS_GC_STATS=
-CONFIG_SPIFFS_PAGE_SIZE=256
-CONFIG_SPIFFS_OBJ_NAME_LEN=32
-CONFIG_SPIFFS_USE_MAGIC=y
-CONFIG_SPIFFS_USE_MAGIC_LENGTH=y
-CONFIG_SPIFFS_META_LENGTH=4
-CONFIG_SPIFFS_USE_MTIME=y
-
-#
-# Debug Configuration
-#
-CONFIG_SPIFFS_DBG=
-CONFIG_SPIFFS_API_DBG=
-CONFIG_SPIFFS_GC_DBG=
-CONFIG_SPIFFS_CACHE_DBG=
-CONFIG_SPIFFS_CHECK_DBG=
-CONFIG_SPIFFS_TEST_VISUALISATION=
-
-#
-# TCP/IP Adapter
-#
-CONFIG_IP_LOST_TIMER_INTERVAL=120
-CONFIG_TCPIP_LWIP=y
-
-#
-# Unity unit testing library
-#
-CONFIG_UNITY_ENABLE_FLOAT=y
-CONFIG_UNITY_ENABLE_DOUBLE=y
-CONFIG_UNITY_ENABLE_COLOR=
-CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
-CONFIG_UNITY_ENABLE_FIXTURE=
-
-#
-# Virtual file system
-#
-CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
-CONFIG_SUPPORT_TERMIOS=y
-
-#
-# Wear Levelling
-#
-CONFIG_WL_SECTOR_SIZE_512=
-CONFIG_WL_SECTOR_SIZE_4096=y
-CONFIG_WL_SECTOR_SIZE=4096
-
-#
-# Wi-Fi Provisioning Manager
-#
-CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
-
-#
-# Supplicant
-#
-CONFIG_WPA_WPS_WARS=
diff --git a/variants/AirM2M_CORE_ESP32C3/pins_arduino.h b/variants/AirM2M_CORE_ESP32C3/pins_arduino.h
new file mode 100644
index 00000000000..ea40027c9e7
--- /dev/null
+++ b/variants/AirM2M_CORE_ESP32C3/pins_arduino.h
@@ -0,0 +1,30 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 12;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t LED_BUILTIN_AUX = 13;
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 5;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 3;
+static const uint8_t MISO = 10;
+static const uint8_t SCK = 2;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/AirM2M_CORE_ESP32C3/variant.cpp b/variants/AirM2M_CORE_ESP32C3/variant.cpp
new file mode 100644
index 00000000000..01bd641f5b9
--- /dev/null
+++ b/variants/AirM2M_CORE_ESP32C3/variant.cpp
@@ -0,0 +1,9 @@
+#include "Arduino.h"
+
+extern "C" void initVariant(void) {
+  // Stop LEDs floating
+  pinMode(LED_BUILTIN, OUTPUT);
+  digitalWrite(LED_BUILTIN, LOW);
+  pinMode(LED_BUILTIN_AUX, OUTPUT);
+  digitalWrite(LED_BUILTIN_AUX, LOW);
+}
diff --git a/variants/Aventen_S3_Sync/pins_arduino.h b/variants/Aventen_S3_Sync/pins_arduino.h
new file mode 100644
index 00000000000..bc7eee314e2
--- /dev/null
+++ b/variants/Aventen_S3_Sync/pins_arduino.h
@@ -0,0 +1,62 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303a
+#define USB_PID          0x1001
+#define USB_MANUFACTURER "Aventen"
+#define USB_PRODUCT      "Aventen S3 Sync"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 2;
+static const uint8_t SCL = 3;
+static const uint8_t SCL_1 = 21;
+static const uint8_t SDA_1 = 20;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t ALS = 17;
+static const uint8_t RGB_DI = 38;
+static const uint8_t RF_SW = 37;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+static const uint8_t T15 = 15;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Bee_Data_Logger/pins_arduino.h b/variants/Bee_Data_Logger/pins_arduino.h
new file mode 100644
index 00000000000..1114ff0bdd3
--- /dev/null
+++ b/variants/Bee_Data_Logger/pins_arduino.h
@@ -0,0 +1,77 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x815C
+#define USB_MANUFACTURER "Smart Bee Designs"
+#define USB_PRODUCT      "Bee Data Logger"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 37;
+static const uint8_t SCL = 36;
+
+static const uint8_t SS = 47;
+static const uint8_t MOSI = 46;
+static const uint8_t MISO = 45;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 48;
+
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+static const uint8_t A7 = 7;
+static const uint8_t A8 = 8;
+static const uint8_t A9 = 9;
+
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 4;
+static const uint8_t D5 = 5;
+static const uint8_t D6 = 6;
+static const uint8_t D7 = 7;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D38 = 38;
+static const uint8_t D39 = 39;
+static const uint8_t D41 = 41;
+static const uint8_t D42 = 42;
+static const uint8_t D43 = 43;
+static const uint8_t D44 = 44;
+
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t BOOT_BTN = 0;
+static const uint8_t VBAT_VOLTAGE = 1;
+static const uint8_t VBUS_SENSE = 2;
+static const uint8_t LDO2 = 34;
+static const uint8_t RGB_DATA = 40;
+static const uint8_t RGB_PWR = 34;
+
+#define PIN_RGB_LED RGB_DATA
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Bee_Motion/pins_arduino.h b/variants/Bee_Motion/pins_arduino.h
new file mode 100644
index 00000000000..a2d6616552e
--- /dev/null
+++ b/variants/Bee_Motion/pins_arduino.h
@@ -0,0 +1,53 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303A
+#define USB_PID          0x810D
+#define USB_MANUFACTURER "Smart Bee Designs"
+#define USB_PRODUCT      "Bee Motion S3"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 36;
+static const uint8_t SCL = 37;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 16;
+static const uint8_t MISO = 38;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 15;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+
+static const uint8_t T1 = 1;
+static const uint8_t T3 = 3;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T14 = 14;
+
+static const uint8_t BOOT_BTN = 0;
+static const uint8_t PIR = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Bee_Motion_Mini/pins_arduino.h b/variants/Bee_Motion_Mini/pins_arduino.h
new file mode 100644
index 00000000000..376125c2bf6
--- /dev/null
+++ b/variants/Bee_Motion_Mini/pins_arduino.h
@@ -0,0 +1,27 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t BOOT_BTN = 9;
+static const uint8_t PIR = 5;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Bee_Motion_S3/pins_arduino.h b/variants/Bee_Motion_S3/pins_arduino.h
new file mode 100644
index 00000000000..45f73b56ba0
--- /dev/null
+++ b/variants/Bee_Motion_S3/pins_arduino.h
@@ -0,0 +1,85 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x8113
+#define USB_MANUFACTURER "Smart Bee Designs"
+#define USB_PRODUCT      "Bee Motion S3"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 37;
+static const uint8_t SCL = 36;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 15;
+static const uint8_t MISO = 16;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 17;
+
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+static const uint8_t A7 = 7;
+static const uint8_t A8 = 8;
+static const uint8_t A9 = 9;
+static const uint8_t A10 = 10;
+static const uint8_t A11 = 11;
+static const uint8_t A12 = 12;
+static const uint8_t A13 = 13;
+static const uint8_t A14 = 14;
+static const uint8_t A15 = 15;
+
+static const uint8_t D5 = 5;
+static const uint8_t D6 = 6;
+static const uint8_t D7 = 7;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D10 = 10;
+static const uint8_t D11 = 11;
+static const uint8_t D12 = 12;
+static const uint8_t D14 = 14;
+static const uint8_t D15 = 15;
+static const uint8_t D16 = 16;
+static const uint8_t D17 = 17;
+static const uint8_t D35 = 35;
+static const uint8_t D36 = 36;
+static const uint8_t D37 = 37;
+static const uint8_t D43 = 43;
+static const uint8_t D44 = 44;
+
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t BOOT_BTN = 0;
+static const uint8_t VBAT_VOLTAGE = 1;
+static const uint8_t VBUS_SENSE = 2;
+static const uint8_t PIR = 4;
+static const uint8_t LIGHT = 3;
+static const uint8_t LDO2 = 34;
+static const uint8_t RGB_DATA = 40;
+static const uint8_t RGB_PWR = 34;
+
+#define PIN_RGB_LED RGB_DATA
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Bee_S3/pins_arduino.h b/variants/Bee_S3/pins_arduino.h
new file mode 100644
index 00000000000..9e76fff803e
--- /dev/null
+++ b/variants/Bee_S3/pins_arduino.h
@@ -0,0 +1,74 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x8110
+#define USB_MANUFACTURER "Smart Bee Designs"
+#define USB_PRODUCT      "BeeS3"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 37;
+static const uint8_t SCL = 36;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 38;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 38;
+static const uint8_t SCK = 39;
+
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+static const uint8_t A7 = 7;
+static const uint8_t A8 = 8;
+static const uint8_t A9 = 9;
+static const uint8_t A10 = 10;
+
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 4;
+static const uint8_t D5 = 5;
+static const uint8_t D6 = 6;
+static const uint8_t D7 = 7;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D10 = 10;
+static const uint8_t D35 = 35;
+static const uint8_t D36 = 36;
+static const uint8_t D37 = 37;
+static const uint8_t D38 = 38;
+static const uint8_t D39 = 39;
+static const uint8_t D43 = 43;
+static const uint8_t D44 = 44;
+
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+
+static const uint8_t VBAT_VOLTAGE = 1;
+
+static const uint8_t RGB_DATA = 48;
+static const uint8_t RGB_PWR = 34;
+
+#define PIN_RGB_LED RGB_DATA
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/BharatPi-A7672S-4G/pins_arduino.h b/variants/BharatPi-A7672S-4G/pins_arduino.h
new file mode 100644
index 00000000000..bf1fab09ddc
--- /dev/null
+++ b/variants/BharatPi-A7672S-4G/pins_arduino.h
@@ -0,0 +1,31 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t A0 = 14;
+static const uint8_t A1 = 13;
+static const uint8_t A2 = 12;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 2;
+static const uint8_t A5 = 0;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t TX_4G = 17;
+static const uint8_t RX_4G = 16;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/BharatPi-LoRa/pins_arduino.h b/variants/BharatPi-LoRa/pins_arduino.h
new file mode 100644
index 00000000000..a42e5834a3a
--- /dev/null
+++ b/variants/BharatPi-LoRa/pins_arduino.h
@@ -0,0 +1,35 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t A0 = 14;
+static const uint8_t A1 = 13;
+static const uint8_t A2 = 12;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 2;
+static const uint8_t A5 = 0;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t TX2 = 17;
+static const uint8_t RX2 = 16;
+
+static const uint8_t LORA_SS = 4;
+static const uint8_t RST = 14;
+static const uint8_t DIO0 = 2;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/BharatPi-Node-Wifi/pins_arduino.h b/variants/BharatPi-Node-Wifi/pins_arduino.h
new file mode 100644
index 00000000000..3b151289f44
--- /dev/null
+++ b/variants/BharatPi-Node-Wifi/pins_arduino.h
@@ -0,0 +1,35 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SAFFRON_LED = 12;
+static const uint8_t WHITE_LED = 2;
+static const uint8_t GREEN_LED = 13;
+
+static const uint8_t A0 = 14;
+static const uint8_t A1 = 13;
+static const uint8_t A2 = 12;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 2;
+static const uint8_t A5 = 0;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t TX2 = 17;
+static const uint8_t RX2 = 16;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/ET-Board/pins_arduino.h b/variants/ET-Board/pins_arduino.h
new file mode 100644
index 00000000000..ec2c1f42903
--- /dev/null
+++ b/variants/ET-Board/pins_arduino.h
@@ -0,0 +1,42 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 5;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 34;
+static const uint8_t RX = 35;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 29;
+static const uint8_t MOSI = 37;
+static const uint8_t MISO = 31;
+static const uint8_t SCK = 30;
+
+static const uint8_t A0 = 36;  // BUILTIN_Potentiometer
+static const uint8_t A1 = 39;  // BUILTIN_CDS
+static const uint8_t A2 = 32;  // BUILTIN_temperature
+static const uint8_t A3 = 33;  // Analog Input
+static const uint8_t A4 = 34;  // Analog Input
+static const uint8_t A5 = 35;  // Analog Input
+static const uint8_t A6 = 25;  // Analog Input
+static const uint8_t A7 = 26;  // Analog Input
+
+static const uint8_t D2 = 27;  // BUILTIN_LED_Red
+static const uint8_t D3 = 14;  // BUILTIN_LED_Blue
+static const uint8_t D4 = 12;  // BUILTIN_LED_Green
+static const uint8_t D5 = 13;  // BUILTIN_LED_Yellow
+static const uint8_t D6 = 15;  // BUILTIN_BUTTON_Red
+static const uint8_t D7 = 16;  // BUILTIN_BUTTON_Blue
+static const uint8_t D8 = 17;  // BUILTIN_BUTTON_Green
+static const uint8_t D9 = 4;   // BUILTIN_BUTTON_Yellow
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Edgebox-ESP-100/pins_arduino.h b/variants/Edgebox-ESP-100/pins_arduino.h
new file mode 100644
index 00000000000..d2f54a89383
--- /dev/null
+++ b/variants/Edgebox-ESP-100/pins_arduino.h
@@ -0,0 +1,59 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+//Programming and Debugging Port
+static const uint8_t TXD = 43;
+static const uint8_t RXD = 44;
+static const uint8_t RST = 0;
+
+//I2C
+static const uint8_t SDA = 20;
+static const uint8_t SCL = 19;
+
+//I2C INT fro RTC PCF8563
+static const uint8_t I2C_INT = 9;
+
+//SPI BUS for W5500 Ethernet Port Driver
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 12;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 13;
+static const uint8_t ETH_INT = 14;
+static const uint8_t ETH_RST = 15;
+
+//A7670G
+static const uint8_t LTE_PWR_EN = 16;
+static const uint8_t LTE_PWR_KEY = 21;
+static const uint8_t LTE_TXD = 48;
+static const uint8_t LTE_RXD = 47;
+
+//RS485
+static const uint8_t RS485_TXD = 17;
+static const uint8_t RS485_RXD = 18;
+static const uint8_t RS485_RTS = 8;
+
+//CAN BUS
+static const uint8_t CAN_TXD = 1;
+static const uint8_t CAN_RXD = 2;
+
+//BUZZER
+static const uint8_t BUZZER = 45;
+
+static const uint8_t DO0 = 40;
+static const uint8_t DO1 = 39;
+static const uint8_t DO2 = 38;
+static const uint8_t DO3 = 37;
+static const uint8_t DO4 = 36;
+static const uint8_t DO5 = 35;
+
+static const uint8_t DI0 = 4;
+static const uint8_t DI1 = 5;
+static const uint8_t DI2 = 6;
+static const uint8_t DI3 = 7;
+
+static const uint8_t AO0 = 42;
+static const uint8_t AO1 = 41;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Geekble_ESP32C3/pins_arduino.h b/variants/Geekble_ESP32C3/pins_arduino.h
new file mode 100644
index 00000000000..660313ce849
--- /dev/null
+++ b/variants/Geekble_ESP32C3/pins_arduino.h
@@ -0,0 +1,32 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 10;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SW_BUILTIN = 9;
+#define BUILTIN_SW SW_BUILTIN  // backward compatibility
+#define SW_BUILTIN SW_BUILTIN  // allow testing #ifdef SW_BUILTIN
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 5;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+//static const uint8_t A5 = 5;  // ADC1 no longer supported
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Geekble_Nano_ESP32S3/pins_arduino.h b/variants/Geekble_Nano_ESP32S3/pins_arduino.h
new file mode 100644
index 00000000000..657c0d5d51b
--- /dev/null
+++ b/variants/Geekble_Nano_ESP32S3/pins_arduino.h
@@ -0,0 +1,74 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303a
+#define USB_PID          0x82C5
+#define USB_MANUFACTURER "Geekble"
+#define USB_PRODUCT      "Geekble nano ESP32-S3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t D0 = 44;  // also RX
+static const uint8_t D1 = 43;  // also TX
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 6;  // also CTS
+static const uint8_t D4 = 7;  // also DSR
+static const uint8_t D5 = 8;
+static const uint8_t D6 = 9;
+static const uint8_t D7 = 10;
+static const uint8_t D8 = 17;
+static const uint8_t D9 = 18;
+static const uint8_t D10 = 21;  // also SS
+static const uint8_t D11 = 38;  // also MOSI
+static const uint8_t D12 = 47;  // also MISO
+static const uint8_t D13 = 48;  // also SCK, LED_BUILTIN
+
+static const uint8_t A0 = 1;  // also DTR
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 11;  // also SDA
+static const uint8_t A5 = 12;  // also SCL
+static const uint8_t A6 = 13;
+static const uint8_t A7 = 14;
+
+// alternate pin functions
+
+static const uint8_t LED_BUILTIN = D13;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SW_BUILTIN = 0;
+
+static const uint8_t TX = D1;
+static const uint8_t RX = D0;
+static const uint8_t RTS = 45;
+static const uint8_t CTS = D3;
+static const uint8_t DTR = A0;
+static const uint8_t DSR = D4;
+
+static const uint8_t SS = D10;
+static const uint8_t MOSI = D11;
+static const uint8_t MISO = D12;
+static const uint8_t SCK = D13;
+
+static const uint8_t SDA = A4;
+static const uint8_t SCL = A5;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#define PIN_I2S_SCK    D7
+#define PIN_I2S_FS     D8
+#define PIN_I2S_SD     D9
+#define PIN_I2S_SD_OUT D9  // same as bidir
+#define PIN_I2S_SD_IN  D10
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Microduino-esp32/pins_arduino.h b/variants/Microduino-esp32/pins_arduino.h
index 35861423e8e..7d7c22f8818 100644
--- a/variants/Microduino-esp32/pins_arduino.h
+++ b/variants/Microduino-esp32/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        22
-#define NUM_ANALOG_INPUTS       12
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = -1;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 #define MTDO 15
 #define MTDI 12
@@ -23,16 +15,17 @@ static const uint8_t LED_BUILTIN = -1;
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
-static const uint8_t SDA = 22;//23;
-static const uint8_t SCL = 21;//19;
+static const uint8_t SDA = 22;  //23;
+static const uint8_t SCL = 21;  //19;
 
+#define WIRE1_PIN_DEFINED 1  // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin)
 static const uint8_t SDA1 = 12;
 static const uint8_t SCL1 = 13;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 12;
 static const uint8_t A1 = 13;
@@ -52,12 +45,12 @@ static const uint8_t D0 = 3;
 static const uint8_t D1 = 1;
 static const uint8_t D2 = 16;
 static const uint8_t D3 = 17;
-static const uint8_t D4 = 32;//ADC1_CH4
-static const uint8_t D5 = 33;//ADC1_CH5
-static const uint8_t D6 = 25;//ADC2_CH8 DAC_1
-static const uint8_t D7 = 26;//ADC2_CH9 DAC_2
-static const uint8_t D8 = 27;//ADC2_CH7
-static const uint8_t D9 = 14;//ADC2_CH6
+static const uint8_t D4 = 32;  //ADC1_CH4
+static const uint8_t D5 = 33;  //ADC1_CH5
+static const uint8_t D6 = 25;  //ADC2_CH8 DAC_1
+static const uint8_t D7 = 26;  //ADC2_CH9 DAC_2
+static const uint8_t D8 = 27;  //ADC2_CH7
+static const uint8_t D9 = 14;  //ADC2_CH6
 static const uint8_t D10 = 5;
 static const uint8_t D11 = 23;
 static const uint8_t D12 = 19;
@@ -71,7 +64,6 @@ static const uint8_t D19 = 21;
 static const uint8_t D20 = 38;
 static const uint8_t D21 = 37;
 
-
 static const uint8_t T0 = 4;
 static const uint8_t T1 = 0;
 static const uint8_t T2 = 2;
diff --git a/variants/Nebula_S3/pins_arduino.h b/variants/Nebula_S3/pins_arduino.h
new file mode 100644
index 00000000000..cc18cda1394
--- /dev/null
+++ b/variants/Nebula_S3/pins_arduino.h
@@ -0,0 +1,57 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 45;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 12;
+static const uint8_t SCL = 13;
+
+static const uint8_t SDA1 = 2;
+static const uint8_t SCL1 = 1;
+
+static const uint8_t SS = 41;
+static const uint8_t MOSI = 40;
+static const uint8_t MISO = 39;
+static const uint8_t SCK = 38;
+
+static const uint8_t D0 = 1;
+static const uint8_t D1 = 2;
+static const uint8_t D2 = 44;
+static const uint8_t D3 = 43;
+static const uint8_t D4 = 42;
+static const uint8_t D5 = 41;
+static const uint8_t D6 = 40;
+static const uint8_t D7 = 39;
+static const uint8_t D8 = 38;
+static const uint8_t D9 = 27;
+static const uint8_t D10 = 45;
+static const uint8_t D11 = 4;
+static const uint8_t D12 = 5;
+static const uint8_t D13 = 6;
+static const uint8_t D14 = 7;
+static const uint8_t D15 = 15;
+static const uint8_t D16 = 16;
+static const uint8_t D17 = 17;
+static const uint8_t D18 = 18;
+
+static const uint8_t A0 = 4;
+static const uint8_t A1 = 5;
+static const uint8_t A2 = 6;
+static const uint8_t A3 = 7;
+static const uint8_t A4 = 1;
+static const uint8_t A5 = 2;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Pcbcupid_GLYPH_C3/pins_arduino.h b/variants/Pcbcupid_GLYPH_C3/pins_arduino.h
new file mode 100644
index 00000000000..653c2c48828
--- /dev/null
+++ b/variants/Pcbcupid_GLYPH_C3/pins_arduino.h
@@ -0,0 +1,43 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = 1;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+//MSR Used in on-board battery measurement
+static const uint8_t BAT_MEASURE = 0;
+#define MSR BAT_MEASURE
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 5;
+
+static const uint8_t SS = 3;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 7;
+static const uint8_t SCK = 10;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+
+static const uint8_t D0 = 0;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 2;
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 4;
+static const uint8_t D5 = 5;
+static const uint8_t D6 = 6;
+static const uint8_t D7 = 7;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D10 = 10;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Pcbcupid_GLYPH_C6/pins_arduino.h b/variants/Pcbcupid_GLYPH_C6/pins_arduino.h
new file mode 100644
index 00000000000..f06fb151244
--- /dev/null
+++ b/variants/Pcbcupid_GLYPH_C6/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = 14;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+//MSR Used in on-board battery measurement
+static const uint8_t BAT_MEASURE = 0;
+#define MSR BAT_MEASURE
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 5;
+
+static const uint8_t SS = 20;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 23;
+static const uint8_t SCK = 21;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+
+static const uint8_t D0 = 0;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 2;
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 4;
+static const uint8_t D5 = 5;
+static const uint8_t D6 = 6;
+static const uint8_t D7 = 7;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D14 = 14;
+static const uint8_t D15 = 15;
+static const uint8_t D16 = 16;
+static const uint8_t D17 = 17;
+static const uint8_t D18 = 18;
+static const uint8_t D19 = 19;
+static const uint8_t D20 = 20;
+static const uint8_t D21 = 21;
+static const uint8_t D22 = 22;
+static const uint8_t D23 = 23;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/Pcbcupid_GLYPH_H2/pins_arduino.h b/variants/Pcbcupid_GLYPH_H2/pins_arduino.h
new file mode 100644
index 00000000000..20a385a9817
--- /dev/null
+++ b/variants/Pcbcupid_GLYPH_H2/pins_arduino.h
@@ -0,0 +1,44 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = 0;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+//MSR Used in on-board battery measurement
+static const uint8_t BAT_MEASURE = 1;
+#define MSR BAT_MEASURE
+
+static const uint8_t TX = 24;
+static const uint8_t RX = 23;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 5;
+
+static const uint8_t SS = 3;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 25;
+static const uint8_t SCK = 11;
+
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+
+static const uint8_t D0 = 0;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 2;
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 4;
+static const uint8_t D5 = 5;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D10 = 10;
+static const uint8_t D11 = 11;
+static const uint8_t D12 = 12;
+static const uint8_t D13 = 13;
+static const uint8_t D14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/S_ODI_Ultra_v1/pins_arduino.h b/variants/S_ODI_Ultra_v1/pins_arduino.h
index a1a968ed5c3..430ae8bd860 100644
--- a/variants/S_ODI_Ultra_v1/pins_arduino.h
+++ b/variants/S_ODI_Ultra_v1/pins_arduino.h
@@ -3,19 +3,11 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
 static const uint8_t LED_BUILTINB = 4;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-#define BUILTIN_LED2  LED_BUILTINB
+#define BUILTIN_LED  LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN  LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+#define BUILTIN_LED2 LED_BUILTINB
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -61,4 +53,4 @@ static const uint8_t DAC2 = 26;
 
 #endif /* Pins_Arduino_h */
 
-/* compitable with SPELEC S.ODI Ultra v1.0 (based on ESP32 Series)*/
+/* compatible with SPELEC S.ODI Ultra v1.0 (based on ESP32 Series)*/
diff --git a/variants/VALTRACK_V4_MFW_ESP32_C3/pins_arduino.h b/variants/VALTRACK_V4_MFW_ESP32_C3/pins_arduino.h
new file mode 100644
index 00000000000..564c9fec495
--- /dev/null
+++ b/variants/VALTRACK_V4_MFW_ESP32_C3/pins_arduino.h
@@ -0,0 +1,48 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t TX1 = 0;
+static const uint8_t RX1 = 1;
+
+static const uint8_t SDA = 5;
+static const uint8_t SCL = 6;
+
+static const uint8_t SS = 20;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 9;
+static const uint8_t SCK = 8;
+
+static const uint8_t A0 = 2;
+static const uint8_t A1 = 3;
+static const uint8_t A2 = 4;
+static const uint8_t A3 = 5;
+
+static const uint8_t D0 = 2;
+static const uint8_t D1 = 3;
+static const uint8_t D2 = 4;
+static const uint8_t D3 = 5;
+static const uint8_t D4 = 6;
+static const uint8_t D5 = 7;
+static const uint8_t D6 = 21;
+static const uint8_t D7 = 20;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D10 = 10;
+
+static const uint8_t GPIO_IIC_DATA = 5;
+static const uint8_t GPIO_IIC_CLOCK = 6;
+static const uint8_t GPIO_PWRKEY = 7;
+static const uint8_t GPIO_GSM_ENABLE = 10;
+static const uint8_t GPIO_TPS_ENABLE = 4;
+static const uint8_t GPIO_INT1 = 3;
+static const uint8_t GPIO_ANALOG_IN = 2;
+static const uint8_t GPIO_SOS = 9;
+static const uint8_t GPIO_CHG_IN = 4;
+static const uint8_t GPIO_LED_SIGNAL = 8;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/VALTRACK_V4_VTS_ESP32_C3/pins_arduino.h b/variants/VALTRACK_V4_VTS_ESP32_C3/pins_arduino.h
new file mode 100644
index 00000000000..564c9fec495
--- /dev/null
+++ b/variants/VALTRACK_V4_VTS_ESP32_C3/pins_arduino.h
@@ -0,0 +1,48 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t TX1 = 0;
+static const uint8_t RX1 = 1;
+
+static const uint8_t SDA = 5;
+static const uint8_t SCL = 6;
+
+static const uint8_t SS = 20;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 9;
+static const uint8_t SCK = 8;
+
+static const uint8_t A0 = 2;
+static const uint8_t A1 = 3;
+static const uint8_t A2 = 4;
+static const uint8_t A3 = 5;
+
+static const uint8_t D0 = 2;
+static const uint8_t D1 = 3;
+static const uint8_t D2 = 4;
+static const uint8_t D3 = 5;
+static const uint8_t D4 = 6;
+static const uint8_t D5 = 7;
+static const uint8_t D6 = 21;
+static const uint8_t D7 = 20;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D10 = 10;
+
+static const uint8_t GPIO_IIC_DATA = 5;
+static const uint8_t GPIO_IIC_CLOCK = 6;
+static const uint8_t GPIO_PWRKEY = 7;
+static const uint8_t GPIO_GSM_ENABLE = 10;
+static const uint8_t GPIO_TPS_ENABLE = 4;
+static const uint8_t GPIO_INT1 = 3;
+static const uint8_t GPIO_ANALOG_IN = 2;
+static const uint8_t GPIO_SOS = 9;
+static const uint8_t GPIO_CHG_IN = 4;
+static const uint8_t GPIO_LED_SIGNAL = 8;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/ViraLink-G0.1/pins_arduino.h b/variants/ViraLink-G0.1/pins_arduino.h
new file mode 100644
index 00000000000..7e11a91ce18
--- /dev/null
+++ b/variants/ViraLink-G0.1/pins_arduino.h
@@ -0,0 +1,46 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 5;
+#define BUILTIN_LED LED_BUILTIN
+#define LED_BUILTIN LED_BUILTIN
+
+static const uint8_t RESET_KEY = 0;
+
+static const uint8_t RS485_TX = 32;
+static const uint8_t RS485_RX = 35;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 16;
+
+static const uint8_t BUZZER = 12;
+static const uint8_t RELAY1_PIN = 2;
+static const uint8_t RELAY2_PIN = 13;
+static const uint8_t RELAY3_PIN = 14;
+static const uint8_t RELAY4_PIN = 33;
+
+static const uint8_t Wiegand1_D0 = 15;
+static const uint8_t Wiegand1_D1 = 34;
+
+static const uint8_t Wiegand2_D0 = 39;
+static const uint8_t Wiegand2_D1 = 36;
+
+static const uint8_t ETH_CLK_OUT = 17;
+
+static const uint8_t EMAC_MDIO = 18;
+static const uint8_t EMAC_TXD0 = 19;
+static const uint8_t EMAC_TX_EN = 21;
+static const uint8_t EMAC_TXD1 = 22;
+static const uint8_t EMAC_MDC = 23;
+static const uint8_t EMAC_RXD0 = 25;
+static const uint8_t EMAC_RXD1 = 26;
+static const uint8_t EMAC_RXD_DV = 27;
+
+static const uint8_t SS = -1;
+static const uint8_t MOSI = -1;
+static const uint8_t SCK = -1;
+static const uint8_t MISO = -1;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/ViraLink-G1.1/pins_arduino.h b/variants/ViraLink-G1.1/pins_arduino.h
new file mode 100644
index 00000000000..e509b0d0e79
--- /dev/null
+++ b/variants/ViraLink-G1.1/pins_arduino.h
@@ -0,0 +1,50 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t RESET_KEY = 0;
+
+static const uint8_t RF433 = 5;
+
+static const uint8_t RS485_TX = 32;
+static const uint8_t RS485_RX = 35;
+
+static const uint8_t GSM1_TX = 15;
+static const uint8_t GSM1_RX = 34;
+
+static const uint8_t GSM2_TX = 32;
+static const uint8_t GSM2_RX = 35;
+
+static const uint8_t GSM_PWR = 33;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 16;
+
+static const uint8_t EXT1 = 12;
+static const uint8_t EXT2 = 13;
+static const uint8_t PCF1_INT = 14;
+
+static const uint8_t Wiegand1_D0 = 15;
+static const uint8_t Wiegand1_D1 = 34;
+
+static const uint8_t Wiegand2_D0 = 39;
+static const uint8_t Wiegand2_D1 = 36;
+
+static const uint8_t ETH_CLK_OUT = 17;
+
+static const uint8_t EMAC_MDIO = 18;
+static const uint8_t EMAC_TXD0 = 19;
+static const uint8_t EMAC_TX_EN = 21;
+static const uint8_t EMAC_TXD1 = 22;
+static const uint8_t EMAC_MDC = 23;
+static const uint8_t EMAC_RXD0 = 25;
+static const uint8_t EMAC_RXD1 = 26;
+static const uint8_t EMAC_RXD_DV = 27;
+
+static const uint8_t SS = -1;
+static const uint8_t MOSI = -1;
+static const uint8_t SCK = -1;
+static const uint8_t MISO = -1;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/XIAO_ESP32C3/pins_arduino.h b/variants/XIAO_ESP32C3/pins_arduino.h
new file mode 100644
index 00000000000..061e743f523
--- /dev/null
+++ b/variants/XIAO_ESP32C3/pins_arduino.h
@@ -0,0 +1,33 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 6;
+static const uint8_t SCL = 7;
+
+static const uint8_t SS = 20;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 9;
+static const uint8_t SCK = 8;
+
+static const uint8_t A0 = 2;
+static const uint8_t A1 = 3;
+static const uint8_t A2 = 4;
+
+static const uint8_t D0 = 2;
+static const uint8_t D1 = 3;
+static const uint8_t D2 = 4;
+static const uint8_t D3 = 5;
+static const uint8_t D4 = 6;
+static const uint8_t D5 = 7;
+static const uint8_t D6 = 21;
+static const uint8_t D7 = 20;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D10 = 10;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/XIAO_ESP32C6/pins_arduino.h b/variants/XIAO_ESP32C6/pins_arduino.h
new file mode 100644
index 00000000000..c90a3394237
--- /dev/null
+++ b/variants/XIAO_ESP32C6/pins_arduino.h
@@ -0,0 +1,47 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x2886
+#define USB_PID          0x0048
+#define USB_MANUFACTURER "Seeed Studio"
+#define USB_PRODUCT      "XIAO ESP32-C6"
+#define USB_SERIAL       ""
+
+static const uint8_t LED_BUILTIN = 15;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 22;
+static const uint8_t SCL = 23;
+
+static const uint8_t SS = 21;
+static const uint8_t MOSI = 18;
+static const uint8_t MISO = 20;
+static const uint8_t SCK = 19;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+
+static const uint8_t D0 = 0;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 2;
+static const uint8_t D3 = 21;
+static const uint8_t D4 = 22;
+static const uint8_t D5 = 23;
+static const uint8_t D6 = 16;
+static const uint8_t D7 = 17;
+static const uint8_t D8 = 19;
+static const uint8_t D9 = 20;
+static const uint8_t D10 = 18;
+
+static const uint8_t WIFI_ENABLE = 3;
+static const uint8_t WIFI_ANT_CONFIG = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/XIAO_ESP32C6/variant.cpp b/variants/XIAO_ESP32C6/variant.cpp
new file mode 100644
index 00000000000..07bd8489c72
--- /dev/null
+++ b/variants/XIAO_ESP32C6/variant.cpp
@@ -0,0 +1,21 @@
+/*
+*By setting the WIFI_ENABLE and WIFI_ANT_CONFIG pins,
+*
+*the XIAO_ESP32C6 will turn on the on-board antenna by default after power-on
+*
+*https://wiki.seeedstudio.com/xiao_esp32c6_getting_started/
+*/
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+void initVariant(void) {
+  pinMode(WIFI_ENABLE, OUTPUT);
+  digitalWrite(WIFI_ENABLE, LOW);  //turn on this function
+
+  pinMode(WIFI_ANT_CONFIG, OUTPUT);
+  digitalWrite(WIFI_ANT_CONFIG, LOW);  //use built-in antenna, set HIGH to use external antenna
+}
+}
diff --git a/variants/XIAO_ESP32S3/bootloader-tinyuf2.bin b/variants/XIAO_ESP32S3/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..b11e5b236f0
Binary files /dev/null and b/variants/XIAO_ESP32S3/bootloader-tinyuf2.bin differ
diff --git a/variants/XIAO_ESP32S3/partitions-8MB.csv b/variants/XIAO_ESP32S3/partitions-8MB.csv
new file mode 100644
index 00000000000..4026378b6fb
--- /dev/null
+++ b/variants/XIAO_ESP32S3/partitions-8MB.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/variants/XIAO_ESP32S3/pins_arduino.h b/variants/XIAO_ESP32S3/pins_arduino.h
new file mode 100644
index 00000000000..b019fd2d747
--- /dev/null
+++ b/variants/XIAO_ESP32S3/pins_arduino.h
@@ -0,0 +1,56 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x2886
+#define USB_PID 0x0056
+
+static const uint8_t LED_BUILTIN = 21;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 5;
+static const uint8_t SCL = 6;
+
+static const uint8_t SS = 44;
+static const uint8_t MOSI = 9;
+static const uint8_t MISO = 8;
+static const uint8_t SCK = 7;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A8 = 7;
+static const uint8_t A9 = 8;
+static const uint8_t A10 = 9;
+
+static const uint8_t D0 = 1;
+static const uint8_t D1 = 2;
+static const uint8_t D2 = 3;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 5;
+static const uint8_t D5 = 6;
+static const uint8_t D6 = 43;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 7;
+static const uint8_t D9 = 8;
+static const uint8_t D10 = 9;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/XIAO_ESP32S3/tinyuf2.bin b/variants/XIAO_ESP32S3/tinyuf2.bin
new file mode 100644
index 00000000000..86d981f8019
Binary files /dev/null and b/variants/XIAO_ESP32S3/tinyuf2.bin differ
diff --git a/variants/XIAO_ESP32S3_Plus/bootloader-tinyuf2.bin b/variants/XIAO_ESP32S3_Plus/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..b11e5b236f0
Binary files /dev/null and b/variants/XIAO_ESP32S3_Plus/bootloader-tinyuf2.bin differ
diff --git a/variants/XIAO_ESP32S3_Plus/partitions-8MB.csv b/variants/XIAO_ESP32S3_Plus/partitions-8MB.csv
new file mode 100644
index 00000000000..4026378b6fb
--- /dev/null
+++ b/variants/XIAO_ESP32S3_Plus/partitions-8MB.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/variants/XIAO_ESP32S3_Plus/pins_arduino.h b/variants/XIAO_ESP32S3_Plus/pins_arduino.h
new file mode 100644
index 00000000000..fb887287e35
--- /dev/null
+++ b/variants/XIAO_ESP32S3_Plus/pins_arduino.h
@@ -0,0 +1,90 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x2886
+#define USB_PID 0x0056
+
+static const uint8_t LED_BUILTIN = 21;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t TX1 = 42;
+static const uint8_t RX1 = 41;
+
+static const uint8_t SDA = 5;
+static const uint8_t SCL = 6;
+
+static const uint8_t SS = 44;
+static const uint8_t MOSI = 9;
+static const uint8_t MISO = 8;
+static const uint8_t SCK = 7;
+
+static const uint8_t MOSI1 = 11;
+static const uint8_t MISO1 = 12;
+static const uint8_t SCK1 = 13;
+
+static const uint8_t I2S_SCK = 39;
+static const uint8_t I2S_SD = 38;
+static const uint8_t I2S_WS = 40;
+
+static const uint8_t MTCK = 39;
+static const uint8_t MTDO = 40;
+static const uint8_t MTDI = 41;
+static const uint8_t MTMS = 42;
+
+static const uint8_t DVP_Y8 = 11;
+static const uint8_t DVP_YP = 12;
+static const uint8_t DVP_PCLK = 13;
+static const uint8_t DVP_VSYNC = 38;
+static const uint8_t CAM_SCL = 39;
+static const uint8_t CAM_SDA = 40;
+static const uint8_t XMCLK = 10;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A8 = 7;
+static const uint8_t A9 = 8;
+static const uint8_t A10 = 9;
+static const uint8_t ADC_BAT = 10;
+
+static const uint8_t D0 = 1;
+static const uint8_t D1 = 2;
+static const uint8_t D2 = 3;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 5;
+static const uint8_t D5 = 6;
+static const uint8_t D6 = 43;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 7;
+static const uint8_t D9 = 8;
+static const uint8_t D10 = 9;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 39;
+static const uint8_t D13 = 40;
+static const uint8_t D14 = 41;
+static const uint8_t D15 = 42;
+static const uint8_t D16 = 10;
+static const uint8_t D17 = 13;
+static const uint8_t D18 = 12;
+static const uint8_t D19 = 11;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/XIAO_ESP32S3_Plus/tinyuf2.bin b/variants/XIAO_ESP32S3_Plus/tinyuf2.bin
new file mode 100644
index 00000000000..86d981f8019
Binary files /dev/null and b/variants/XIAO_ESP32S3_Plus/tinyuf2.bin differ
diff --git a/variants/adafruit_camera_esp32s3/bootloader-tinyuf2.bin b/variants/adafruit_camera_esp32s3/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..ef4e3bf6fd1
Binary files /dev/null and b/variants/adafruit_camera_esp32s3/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_camera_esp32s3/pins_arduino.h b/variants/adafruit_camera_esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..447204f7345
--- /dev/null
+++ b/variants/adafruit_camera_esp32s3/pins_arduino.h
@@ -0,0 +1,82 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x8117
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Camera ESP32-S3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t PIN_NEOPIXEL = 1;
+static const uint8_t NEOPIXEL_PIN = 1;
+
+//By making LED_BUILTIN have the same value of RGB_BUILTIN
+//NeoPixel LED can also be used as LED_BUILTIN with digitalMode() + digitalWrite()
+static const uint8_t LED_BUILTIN = PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TFT_BACKLIGHT = 45;
+static const uint8_t TFT_DC = 40;
+static const uint8_t TFT_CS = 39;
+static const uint8_t TFT_RESET = 38;
+static const uint8_t TFT_RST = 38;
+
+static const uint8_t SD_CS = 48;
+static const uint8_t SD_CHIP_SELECT = 48;
+static const uint8_t SPEAKER = 46;
+
+static const uint8_t SCL = 33;
+static const uint8_t SDA = 34;
+
+static const uint8_t SS = 48;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 17;
+static const uint8_t A1 = 18;
+static const uint8_t BATT_MONITOR = 4;
+static const uint8_t SHUTTER_BUTTON = 0;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#define AWEXP_SPKR_SD      0
+#define AWEXP_BUTTON_SEL   1
+#define AWEXP_SD_DET       8
+#define AWEXP_SD_PWR       9
+#define AWEXP_BUTTON_OK    11
+#define AWEXP_BUTTON_RIGHT 12
+#define AWEXP_BUTTON_UP    13
+#define AWEXP_BUTTON_LEFT  14
+#define AWEXP_BUTTON_DOWN  15
+
+#define RESET_GPIO_NUM 47
+#define PWDN_GPIO_NUM  21
+#define XCLK_GPIO_NUM  8
+#define SIOD_GPIO_NUM  SDA
+#define SIOC_GPIO_NUM  SCL
+
+#define Y9_GPIO_NUM    7
+#define Y8_GPIO_NUM    9
+#define Y7_GPIO_NUM    10
+#define Y6_GPIO_NUM    12
+#define Y5_GPIO_NUM    14
+#define Y4_GPIO_NUM    16
+#define Y3_GPIO_NUM    15
+#define Y2_GPIO_NUM    13
+#define VSYNC_GPIO_NUM 5
+#define HREF_GPIO_NUM  6
+#define PCLK_GPIO_NUM  11
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_camera_esp32s3/tinyuf2.bin b/variants/adafruit_camera_esp32s3/tinyuf2.bin
new file mode 100644
index 00000000000..5eb3429b516
Binary files /dev/null and b/variants/adafruit_camera_esp32s3/tinyuf2.bin differ
diff --git a/variants/adafruit_camera_esp32s3/variant.cpp b/variants/adafruit_camera_esp32s3/variant.cpp
new file mode 100644
index 00000000000..4655d30d46c
--- /dev/null
+++ b/variants/adafruit_camera_esp32s3/variant.cpp
@@ -0,0 +1,43 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  pinMode(TFT_BACKLIGHT, OUTPUT);
+  digitalWrite(TFT_BACKLIGHT, LOW);
+  pinMode(SD_CS, OUTPUT);
+  digitalWrite(SD_CS, HIGH);
+  pinMode(TFT_CS, OUTPUT);
+  digitalWrite(TFT_CS, HIGH);
+  pinMode(TFT_RESET, OUTPUT);
+  digitalWrite(TFT_RESET, LOW);
+  delay(1);
+  digitalWrite(TFT_RESET, HIGH);
+}
+}
diff --git a/variants/adafruit_feather_esp32_v2/pins_arduino.h b/variants/adafruit_feather_esp32_v2/pins_arduino.h
new file mode 100644
index 00000000000..f4af72aa98b
--- /dev/null
+++ b/variants/adafruit_feather_esp32_v2/pins_arduino.h
@@ -0,0 +1,70 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t TX = 8;
+static const uint8_t RX = 7;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 22;
+static const uint8_t SCL = 20;
+
+static const uint8_t SS = 33;
+static const uint8_t MOSI = 19;
+static const uint8_t MISO = 21;
+static const uint8_t SCK = 5;
+
+// mapping to match other feathers and also in order
+static const uint8_t A0 = 26;
+static const uint8_t A1 = 25;
+static const uint8_t A2 = 34;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 36;
+static const uint8_t A5 = 4;
+static const uint8_t A6 = 14;
+static const uint8_t A7 = 32;
+static const uint8_t A8 = 15;
+static const uint8_t A9 = 33;
+static const uint8_t A10 = 27;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 35;
+
+// vbat measure
+#define BATT_MONITOR 35
+
+// internal switch
+#define BUTTON 38
+
+// User LED
+static const uint8_t LED_BUILTIN = 13;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+// Neopixel
+#define PIN_NEOPIXEL 0
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+// Neopixel & I2C power
+#define NEOPIXEL_I2C_POWER 2
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_feather_esp32_v2/variant.cpp b/variants/adafruit_feather_esp32_v2/variant.cpp
new file mode 100644
index 00000000000..576afb6b228
--- /dev/null
+++ b/variants/adafruit_feather_esp32_v2/variant.cpp
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels & I2C
+  pinMode(NEOPIXEL_I2C_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_I2C_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_feather_esp32c6/pins_arduino.h b/variants/adafruit_feather_esp32c6/pins_arduino.h
new file mode 100644
index 00000000000..c4ae4bab3fe
--- /dev/null
+++ b/variants/adafruit_feather_esp32c6/pins_arduino.h
@@ -0,0 +1,38 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_NEOPIXEL 9
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = 15;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_I2C_POWER     20  // I2C power pin
+#define PIN_NEOPIXEL_I2C_POWER 20  // I2C power pin
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 19;
+static const uint8_t SCL = 18;
+
+static const uint8_t SS = 0;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 23;
+static const uint8_t SCK = 21;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 4;
+static const uint8_t A2 = 6;
+static const uint8_t A3 = 5;
+static const uint8_t A4 = 3;
+static const uint8_t A5 = 2;
+static const uint8_t A6 = 0;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_feather_esp32c6/variant.cpp b/variants/adafruit_feather_esp32c6/variant.cpp
new file mode 100644
index 00000000000..576afb6b228
--- /dev/null
+++ b/variants/adafruit_feather_esp32c6/variant.cpp
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels & I2C
+  pinMode(NEOPIXEL_I2C_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_I2C_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_feather_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s2/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..0c49080d571
Binary files /dev/null and b/variants/adafruit_feather_esp32s2/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s2/pins_arduino.h b/variants/adafruit_feather_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..72ab65a8d33
--- /dev/null
+++ b/variants/adafruit_feather_esp32s2/pins_arduino.h
@@ -0,0 +1,62 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x80EB
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Feather ESP32-S2"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 33
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    21    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+#define I2C_POWER         7     // I2C power pin
+#define PIN_I2C_POWER     7     // I2C power pin
+
+static const uint8_t SDA = 3;
+static const uint8_t SCL = 4;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 16;
+static const uint8_t A3 = 15;
+static const uint8_t A4 = 14;
+static const uint8_t A5 = 8;
+
+static const uint8_t TX = 39;
+static const uint8_t RX = 38;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_feather_esp32s2/tinyuf2.bin b/variants/adafruit_feather_esp32s2/tinyuf2.bin
new file mode 100644
index 00000000000..40a8f04f924
Binary files /dev/null and b/variants/adafruit_feather_esp32s2/tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s2/variant.cpp b/variants/adafruit_feather_esp32s2/variant.cpp
new file mode 100644
index 00000000000..56d9ea06e4c
--- /dev/null
+++ b/variants/adafruit_feather_esp32s2/variant.cpp
@@ -0,0 +1,44 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels.
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+
+  // turn on the I2C power by setting pin to opposite of 'rest state'
+  pinMode(PIN_I2C_POWER, INPUT);
+  delay(1);
+  bool polarity = digitalRead(PIN_I2C_POWER);
+  pinMode(PIN_I2C_POWER, OUTPUT);
+  digitalWrite(PIN_I2C_POWER, !polarity);
+}
+}
diff --git a/variants/adafruit_feather_esp32s2_reversetft/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s2_reversetft/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..e4d6a498eb1
Binary files /dev/null and b/variants/adafruit_feather_esp32s2_reversetft/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s2_reversetft/pins_arduino.h b/variants/adafruit_feather_esp32s2_reversetft/pins_arduino.h
new file mode 100644
index 00000000000..92902cc1622
--- /dev/null
+++ b/variants/adafruit_feather_esp32s2_reversetft/pins_arduino.h
@@ -0,0 +1,66 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x80ED
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Feather ESP32-S2 Reverse TFT"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 33
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    21    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+
+#define TFT_I2C_POWER 7
+#define TFT_CS        42
+#define TFT_RST       41
+#define TFT_DC        40
+#define TFT_BACKLITE  45
+
+static const uint8_t SDA = 3;
+static const uint8_t SCL = 4;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 16;
+static const uint8_t A3 = 15;
+static const uint8_t A4 = 14;
+static const uint8_t A5 = 8;
+
+static const uint8_t TX = 39;
+static const uint8_t RX = 38;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_feather_esp32s2_reversetft/tinyuf2.bin b/variants/adafruit_feather_esp32s2_reversetft/tinyuf2.bin
new file mode 100644
index 00000000000..ff6eb115dba
Binary files /dev/null and b/variants/adafruit_feather_esp32s2_reversetft/tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s2_reversetft/variant.cpp b/variants/adafruit_feather_esp32s2_reversetft/variant.cpp
new file mode 100644
index 00000000000..403faaa8404
--- /dev/null
+++ b/variants/adafruit_feather_esp32s2_reversetft/variant.cpp
@@ -0,0 +1,39 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has power control pins, and we must set them to output and high
+  // in order to enable the NeoPixels, TFT & I2C
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+  pinMode(TFT_I2C_POWER, OUTPUT);
+  digitalWrite(TFT_I2C_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_feather_esp32s2_tft/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s2_tft/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..aa7cb519661
Binary files /dev/null and b/variants/adafruit_feather_esp32s2_tft/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s2_tft/pins_arduino.h b/variants/adafruit_feather_esp32s2_tft/pins_arduino.h
new file mode 100644
index 00000000000..8c3059acb6e
--- /dev/null
+++ b/variants/adafruit_feather_esp32s2_tft/pins_arduino.h
@@ -0,0 +1,68 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x810F
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Feather ESP32-S2 TFT"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 33
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    34    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+
+#define TFT_I2C_POWER 21
+#define TFT_CS        7
+#define TFT_RST       40
+#define TFT_DC        39
+#define TFT_BACKLITE  45
+
+static const uint8_t SDA = 42;
+static const uint8_t SCL = 41;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 16;
+static const uint8_t A3 = 15;
+static const uint8_t A4 = 14;
+static const uint8_t A5 = 8;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 2;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_feather_esp32s2_tft/tinyuf2.bin b/variants/adafruit_feather_esp32s2_tft/tinyuf2.bin
new file mode 100644
index 00000000000..b8334f98220
Binary files /dev/null and b/variants/adafruit_feather_esp32s2_tft/tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s2_tft/variant.cpp b/variants/adafruit_feather_esp32s2_tft/variant.cpp
new file mode 100644
index 00000000000..403faaa8404
--- /dev/null
+++ b/variants/adafruit_feather_esp32s2_tft/variant.cpp
@@ -0,0 +1,39 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has power control pins, and we must set them to output and high
+  // in order to enable the NeoPixels, TFT & I2C
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+  pinMode(TFT_I2C_POWER, OUTPUT);
+  digitalWrite(TFT_I2C_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_feather_esp32s3/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s3/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..8a04549dad5
Binary files /dev/null and b/variants/adafruit_feather_esp32s3/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s3/pins_arduino.h b/variants/adafruit_feather_esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..991a57c9eba
--- /dev/null
+++ b/variants/adafruit_feather_esp32s3/pins_arduino.h
@@ -0,0 +1,70 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x811B
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Feather ESP32-S3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 33
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    21    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+#define I2C_POWER         7     // I2C power pin
+#define PIN_I2C_POWER     7     // I2C power pin
+
+static const uint8_t TX = 39;
+static const uint8_t RX = 38;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 3;
+static const uint8_t SCL = 4;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 16;
+static const uint8_t A3 = 15;
+static const uint8_t A4 = 14;
+static const uint8_t A5 = 8;
+static const uint8_t A6 = 3;
+static const uint8_t A7 = 4;
+static const uint8_t A8 = 5;
+static const uint8_t A9 = 6;
+static const uint8_t A10 = 9;
+static const uint8_t A11 = 10;
+static const uint8_t A12 = 11;
+static const uint8_t A13 = 12;
+static const uint8_t A14 = 13;
+
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_feather_esp32s3/tinyuf2.bin b/variants/adafruit_feather_esp32s3/tinyuf2.bin
new file mode 100644
index 00000000000..d76bd75c297
Binary files /dev/null and b/variants/adafruit_feather_esp32s3/tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s3/variant.cpp b/variants/adafruit_feather_esp32s3/variant.cpp
new file mode 100644
index 00000000000..e431b7c5778
--- /dev/null
+++ b/variants/adafruit_feather_esp32s3/variant.cpp
@@ -0,0 +1,41 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels.
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+
+  // turn on the I2C power by setting LDO enable pin 'high'
+  pinMode(PIN_I2C_POWER, OUTPUT);
+  digitalWrite(PIN_I2C_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_feather_esp32s3_nopsram/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s3_nopsram/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..9cca9d28a05
Binary files /dev/null and b/variants/adafruit_feather_esp32s3_nopsram/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s3_nopsram/pins_arduino.h b/variants/adafruit_feather_esp32s3_nopsram/pins_arduino.h
new file mode 100644
index 00000000000..34fe2ebae2c
--- /dev/null
+++ b/variants/adafruit_feather_esp32s3_nopsram/pins_arduino.h
@@ -0,0 +1,70 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x8113
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Feather ESP32-S3 No PSRAM"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 33
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    21    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+#define I2C_POWER         7     // I2C power pin
+#define PIN_I2C_POWER     7     // I2C power pin
+
+static const uint8_t TX = 39;
+static const uint8_t RX = 38;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 3;
+static const uint8_t SCL = 4;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 16;
+static const uint8_t A3 = 15;
+static const uint8_t A4 = 14;
+static const uint8_t A5 = 8;
+static const uint8_t A6 = 3;
+static const uint8_t A7 = 4;
+static const uint8_t A8 = 5;
+static const uint8_t A9 = 6;
+static const uint8_t A10 = 9;
+static const uint8_t A11 = 10;
+static const uint8_t A12 = 11;
+static const uint8_t A13 = 12;
+static const uint8_t A14 = 13;
+
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_feather_esp32s3_nopsram/tinyuf2.bin b/variants/adafruit_feather_esp32s3_nopsram/tinyuf2.bin
new file mode 100644
index 00000000000..c345a5b8ce5
Binary files /dev/null and b/variants/adafruit_feather_esp32s3_nopsram/tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s3_nopsram/variant.cpp b/variants/adafruit_feather_esp32s3_nopsram/variant.cpp
new file mode 100644
index 00000000000..e431b7c5778
--- /dev/null
+++ b/variants/adafruit_feather_esp32s3_nopsram/variant.cpp
@@ -0,0 +1,41 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels.
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+
+  // turn on the I2C power by setting LDO enable pin 'high'
+  pinMode(PIN_I2C_POWER, OUTPUT);
+  digitalWrite(PIN_I2C_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_feather_esp32s3_reversetft/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s3_reversetft/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..4e92bba7a71
Binary files /dev/null and b/variants/adafruit_feather_esp32s3_reversetft/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s3_reversetft/pins_arduino.h b/variants/adafruit_feather_esp32s3_reversetft/pins_arduino.h
new file mode 100644
index 00000000000..ea955ff54f5
--- /dev/null
+++ b/variants/adafruit_feather_esp32s3_reversetft/pins_arduino.h
@@ -0,0 +1,66 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x8123
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Feather ESP32-S3 Reverse TFT"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 33
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    21    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+
+#define TFT_I2C_POWER 7
+#define TFT_CS        42
+#define TFT_RST       41
+#define TFT_DC        40
+#define TFT_BACKLITE  45
+
+static const uint8_t SDA = 3;
+static const uint8_t SCL = 4;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 16;
+static const uint8_t A3 = 15;
+static const uint8_t A4 = 14;
+static const uint8_t A5 = 8;
+
+static const uint8_t TX = 39;
+static const uint8_t RX = 38;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_feather_esp32s3_reversetft/tinyuf2.bin b/variants/adafruit_feather_esp32s3_reversetft/tinyuf2.bin
new file mode 100644
index 00000000000..70f80cf1dd3
Binary files /dev/null and b/variants/adafruit_feather_esp32s3_reversetft/tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s3_reversetft/variant.cpp b/variants/adafruit_feather_esp32s3_reversetft/variant.cpp
new file mode 100644
index 00000000000..403faaa8404
--- /dev/null
+++ b/variants/adafruit_feather_esp32s3_reversetft/variant.cpp
@@ -0,0 +1,39 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has power control pins, and we must set them to output and high
+  // in order to enable the NeoPixels, TFT & I2C
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+  pinMode(TFT_I2C_POWER, OUTPUT);
+  digitalWrite(TFT_I2C_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_feather_esp32s3_tft/bootloader-tinyuf2.bin b/variants/adafruit_feather_esp32s3_tft/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..2babca98301
Binary files /dev/null and b/variants/adafruit_feather_esp32s3_tft/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s3_tft/pins_arduino.h b/variants/adafruit_feather_esp32s3_tft/pins_arduino.h
new file mode 100644
index 00000000000..3e007c7706d
--- /dev/null
+++ b/variants/adafruit_feather_esp32s3_tft/pins_arduino.h
@@ -0,0 +1,68 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x811D
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Feather ESP32-S3 TFT"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 33
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    34    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+
+#define TFT_I2C_POWER 21
+#define TFT_CS        7
+#define TFT_RST       40
+#define TFT_DC        39
+#define TFT_BACKLITE  45
+
+static const uint8_t SDA = 42;
+static const uint8_t SCL = 41;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 16;
+static const uint8_t A3 = 15;
+static const uint8_t A4 = 14;
+static const uint8_t A5 = 8;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 2;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_feather_esp32s3_tft/tinyuf2.bin b/variants/adafruit_feather_esp32s3_tft/tinyuf2.bin
new file mode 100644
index 00000000000..1f2b1d66157
Binary files /dev/null and b/variants/adafruit_feather_esp32s3_tft/tinyuf2.bin differ
diff --git a/variants/adafruit_feather_esp32s3_tft/variant.cpp b/variants/adafruit_feather_esp32s3_tft/variant.cpp
new file mode 100644
index 00000000000..403faaa8404
--- /dev/null
+++ b/variants/adafruit_feather_esp32s3_tft/variant.cpp
@@ -0,0 +1,39 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has power control pins, and we must set them to output and high
+  // in order to enable the NeoPixels, TFT & I2C
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+  pinMode(TFT_I2C_POWER, OUTPUT);
+  digitalWrite(TFT_I2C_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_funhouse_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_funhouse_esp32s2/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..7e153e6b117
Binary files /dev/null and b/variants/adafruit_funhouse_esp32s2/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_funhouse_esp32s2/pins_arduino.h b/variants/adafruit_funhouse_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..741193eef09
--- /dev/null
+++ b/variants/adafruit_funhouse_esp32s2/pins_arduino.h
@@ -0,0 +1,65 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x239A
+#define USB_PID          0x80F9
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Funhouse ESP32-S2"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+#define LED_BUILTIN 37
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+#define PIN_BUTTON1 3
+#define PIN_BUTTON2 4
+#define PIN_BUTTON3 5
+#define PIN_BUTTON4 0  // BOOT0 switch
+
+static const uint8_t PIN_DOTSTAR_DATA = 14;
+static const uint8_t PIN_DOTSTAR_CLOCK = 15;
+
+static const uint8_t TFT_BACKLIGHT = 21;
+static const uint8_t TFT_DC = 39;
+static const uint8_t TFT_CS = 40;
+static const uint8_t TFT_RESET = 41;
+
+static const uint8_t SPEAKER = 42;
+static const uint8_t BUTTON_DOWN = PIN_BUTTON1;
+static const uint8_t BUTTON_SELECT = PIN_BUTTON2;
+static const uint8_t BUTTON_UP = PIN_BUTTON3;
+static const uint8_t SENSOR_PIR = 16;
+static const uint8_t SENSOR_LIGHT = 18;
+
+static const uint8_t SDA = 34;
+static const uint8_t SCL = 33;
+
+static const uint8_t SS = 40;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 17;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 1;
+static const uint8_t A3 = 18;  // light sensor
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_funhouse_esp32s2/tinyuf2.bin b/variants/adafruit_funhouse_esp32s2/tinyuf2.bin
new file mode 100644
index 00000000000..4cf847944f7
Binary files /dev/null and b/variants/adafruit_funhouse_esp32s2/tinyuf2.bin differ
diff --git a/variants/adafruit_funhouse_esp32s2/variant.cpp b/variants/adafruit_funhouse_esp32s2/variant.cpp
new file mode 100644
index 00000000000..971bf530d58
--- /dev/null
+++ b/variants/adafruit_funhouse_esp32s2/variant.cpp
@@ -0,0 +1,32 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {}
+}
diff --git a/variants/adafruit_itsybitsy_esp32/pins_arduino.h b/variants/adafruit_itsybitsy_esp32/pins_arduino.h
new file mode 100644
index 00000000000..801dc15da57
--- /dev/null
+++ b/variants/adafruit_itsybitsy_esp32/pins_arduino.h
@@ -0,0 +1,56 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// User LED
+static const uint8_t LED_BUILTIN = 13;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+// Neopixel
+static const uint8_t PIN_NEOPIXEL = 0;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t NEOPIXEL_POWER = 2;
+
+static const uint8_t TX = 20;
+static const uint8_t RX = 8;
+
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 15;
+static const uint8_t SCL = 27;
+
+static const uint8_t SS = 32;
+static const uint8_t MOSI = 21;
+static const uint8_t MISO = 22;
+static const uint8_t SCK = 19;
+
+static const uint8_t A0 = 25;
+static const uint8_t A1 = 26;
+static const uint8_t A2 = 4;
+static const uint8_t A3 = 38;
+static const uint8_t A4 = 37;
+static const uint8_t A5 = 36;
+
+// internal switch
+static const uint8_t BUTTON = 35;
+
+static const uint8_t T0 = 4;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_itsybitsy_esp32/variant.cpp b/variants/adafruit_itsybitsy_esp32/variant.cpp
new file mode 100644
index 00000000000..7809ec26f46
--- /dev/null
+++ b/variants/adafruit_itsybitsy_esp32/variant.cpp
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels.
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_magtag29_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_magtag29_esp32s2/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..eec06c84fa2
Binary files /dev/null and b/variants/adafruit_magtag29_esp32s2/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_magtag29_esp32s2/pins_arduino.h b/variants/adafruit_magtag29_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..197f2e4c1aa
--- /dev/null
+++ b/variants/adafruit_magtag29_esp32s2/pins_arduino.h
@@ -0,0 +1,88 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x80E5
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "EPD MagTag 2.9\" ESP32-S2"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 1  // D1
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM      4    // number of neopixels
+#define NEOPIXEL_POWER    21   // power pin
+#define NEOPIXEL_POWER_ON LOW  // power pin state when on
+
+#define PIN_BUTTON1 15
+#define PIN_BUTTON2 14
+#define PIN_BUTTON3 12
+#define PIN_BUTTON4 11
+#define PIN_BUTTON5 0  // BOOT0 switch
+
+static const uint8_t EPD_BUSY = 5;
+static const uint8_t EPD_RESET = 6;
+static const uint8_t EPD_DC = 7;
+static const uint8_t EPD_CS = 8;
+
+static const uint8_t ACCEL_IRQ = 9;
+
+static const uint8_t BUTTON_A = PIN_BUTTON1;
+static const uint8_t BUTTON_B = PIN_BUTTON2;
+static const uint8_t BUTTON_C = PIN_BUTTON3;
+static const uint8_t BUTTON_D = PIN_BUTTON4;
+
+static const uint8_t LIGHT_SENSOR = 3;
+static const uint8_t BATT_MONITOR = 4;
+static const uint8_t SPEAKER_SHUTDOWN = 16;
+
+static const uint8_t SDA = 33;
+static const uint8_t SCL = 34;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t A0 = 17;
+static const uint8_t A1 = 18;
+static const uint8_t A2 = 1;
+static const uint8_t A3 = 2;
+static const uint8_t A4 = 3;
+static const uint8_t A5 = 4;
+static const uint8_t A6 = 5;
+static const uint8_t A7 = 6;
+static const uint8_t A8 = 7;
+static const uint8_t A9 = 8;
+static const uint8_t A10 = 9;
+static const uint8_t A11 = 10;
+static const uint8_t A12 = 11;
+static const uint8_t A13 = 12;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 14;
+static const uint8_t A16 = 15;
+static const uint8_t A17 = 16;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T10 = 10;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_magtag29_esp32s2/tinyuf2.bin b/variants/adafruit_magtag29_esp32s2/tinyuf2.bin
new file mode 100644
index 00000000000..7a70be3ef32
Binary files /dev/null and b/variants/adafruit_magtag29_esp32s2/tinyuf2.bin differ
diff --git a/variants/adafruit_magtag29_esp32s2/variant.cpp b/variants/adafruit_magtag29_esp32s2/variant.cpp
new file mode 100644
index 00000000000..971bf530d58
--- /dev/null
+++ b/variants/adafruit_magtag29_esp32s2/variant.cpp
@@ -0,0 +1,32 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {}
+}
diff --git a/variants/adafruit_matrixportal_esp32s3/bootloader-tinyuf2.bin b/variants/adafruit_matrixportal_esp32s3/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..6f062fea2fe
Binary files /dev/null and b/variants/adafruit_matrixportal_esp32s3/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_matrixportal_esp32s3/pins_arduino.h b/variants/adafruit_matrixportal_esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..9843c54c1cd
--- /dev/null
+++ b/variants/adafruit_matrixportal_esp32s3/pins_arduino.h
@@ -0,0 +1,56 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x8125
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "MatrixPortal ESP32-S3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+#define PIN_NEOPIXEL 4
+#define NEOPIXEL_PIN 4
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM    1
+#define PIN_LIGHTSENSOR A5
+
+#define PIN_BUTTON_UP   6
+#define PIN_BUTTON_DOWN 7
+
+static const uint8_t TX = 18;
+static const uint8_t RX = 8;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 16;
+static const uint8_t SCL = 17;
+
+static const uint8_t SS = -1;
+static const uint8_t MOSI = -1;
+static const uint8_t SCK = -1;
+static const uint8_t MISO = -1;
+
+static const uint8_t A0 = 12;
+static const uint8_t A1 = 3;
+static const uint8_t A2 = 9;
+static const uint8_t A3 = 10;
+static const uint8_t A4 = 11;
+static const uint8_t A5 = 5;  // Light
+
+static const uint8_t T3 = 3;  // Touch pin IDs map directly
+static const uint8_t T8 = 8;  // to underlying GPIO numbers NOT
+static const uint8_t T9 = 9;  // the analog numbers on board silk
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_matrixportal_esp32s3/tinyuf2.bin b/variants/adafruit_matrixportal_esp32s3/tinyuf2.bin
new file mode 100644
index 00000000000..16f7054546b
Binary files /dev/null and b/variants/adafruit_matrixportal_esp32s3/tinyuf2.bin differ
diff --git a/variants/adafruit_metro_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_metro_esp32s2/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..1a98daf73f7
Binary files /dev/null and b/variants/adafruit_metro_esp32s2/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_metro_esp32s2/pins_arduino.h b/variants/adafruit_metro_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..cef937d3662
--- /dev/null
+++ b/variants/adafruit_metro_esp32s2/pins_arduino.h
@@ -0,0 +1,78 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x80DF
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Metro ESP32-S2"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+#define LED_BUILTIN 42
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 45
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM 1
+
+#define PIN_BUTTON1 0  // BOOT0 switch
+
+static const uint8_t TX = 5;
+static const uint8_t RX = 6;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 33;
+static const uint8_t SCL = 34;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 17;
+static const uint8_t A1 = 18;
+static const uint8_t A2 = 1;
+static const uint8_t A3 = 2;
+static const uint8_t A4 = 3;
+static const uint8_t A5 = 4;
+static const uint8_t A6 = 5;
+static const uint8_t A7 = 6;
+static const uint8_t A8 = 7;
+static const uint8_t A9 = 8;
+static const uint8_t A10 = 9;
+static const uint8_t A11 = 10;
+static const uint8_t A12 = 11;
+static const uint8_t A13 = 12;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 14;
+static const uint8_t A16 = 15;
+static const uint8_t A17 = 16;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_metro_esp32s2/tinyuf2.bin b/variants/adafruit_metro_esp32s2/tinyuf2.bin
new file mode 100644
index 00000000000..6763a41df29
Binary files /dev/null and b/variants/adafruit_metro_esp32s2/tinyuf2.bin differ
diff --git a/variants/adafruit_metro_esp32s2/variant.cpp b/variants/adafruit_metro_esp32s2/variant.cpp
new file mode 100644
index 00000000000..971bf530d58
--- /dev/null
+++ b/variants/adafruit_metro_esp32s2/variant.cpp
@@ -0,0 +1,32 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {}
+}
diff --git a/variants/adafruit_metro_esp32s3/bootloader-tinyuf2.bin b/variants/adafruit_metro_esp32s3/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..03cc2bfe4cf
Binary files /dev/null and b/variants/adafruit_metro_esp32s3/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_metro_esp32s3/pins_arduino.h b/variants/adafruit_metro_esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..9e2cff7e651
--- /dev/null
+++ b/variants/adafruit_metro_esp32s3/pins_arduino.h
@@ -0,0 +1,76 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x8145
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Metro ESP32-S3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// Neopixel
+#define PIN_NEOPIXEL 46
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM 1
+
+#define PIN_BUTTON1 0  // BOOT0 switch
+
+static const uint8_t TX = 40;
+static const uint8_t RX = 41;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 47;
+static const uint8_t SCL = 48;
+
+static const uint8_t SS = 45;
+static const uint8_t MOSI = 42;
+static const uint8_t SCK = 39;
+static const uint8_t MISO = 21;
+
+static const uint8_t A0 = 14;
+static const uint8_t A1 = 15;
+static const uint8_t A2 = 16;
+static const uint8_t A3 = 17;
+static const uint8_t A4 = 18;
+static const uint8_t A5 = 1;
+
+static const uint8_t A6 = 40;
+static const uint8_t A7 = 41;
+static const uint8_t A8 = 2;
+static const uint8_t A9 = 3;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 5;
+static const uint8_t A12 = 6;
+static const uint8_t A13 = 7;
+static const uint8_t A14 = 8;
+static const uint8_t A15 = 9;
+static const uint8_t A16 = 10;
+static const uint8_t A17 = 11;
+static const uint8_t A18 = 12;
+static const uint8_t A19 = 13;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_metro_esp32s3/tinyuf2.bin b/variants/adafruit_metro_esp32s3/tinyuf2.bin
new file mode 100644
index 00000000000..d0eaed3f7cf
Binary files /dev/null and b/variants/adafruit_metro_esp32s3/tinyuf2.bin differ
diff --git a/variants/adafruit_metro_esp32s3/variant.cpp b/variants/adafruit_metro_esp32s3/variant.cpp
new file mode 100644
index 00000000000..7adcc6f401c
--- /dev/null
+++ b/variants/adafruit_metro_esp32s3/variant.cpp
@@ -0,0 +1,36 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // default SD_CS to input pullup (we cannot have built in pullup since its
+  // a strapping pin!)
+  pinMode(SS, INPUT_PULLUP);
+}
+}
diff --git a/variants/adafruit_qtpy_esp32/pins_arduino.h b/variants/adafruit_qtpy_esp32/pins_arduino.h
new file mode 100644
index 00000000000..b422377d981
--- /dev/null
+++ b/variants/adafruit_qtpy_esp32/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// Neopixel
+#define PIN_NEOPIXEL 5
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_POWER 8
+
+static const uint8_t TX = 32;
+static const uint8_t RX = 7;
+
+#define TX1 32
+#define RX1 7
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 33;
+
+#define WIRE1_PIN_DEFINED 1  // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin)
+static const uint8_t SDA1 = 22;
+static const uint8_t SCL1 = 19;
+
+static const uint8_t SS = 27;
+static const uint8_t MOSI = 13;
+static const uint8_t MISO = 12;
+static const uint8_t SCK = 14;
+
+static const uint8_t A0 = 26;
+static const uint8_t A1 = 25;
+static const uint8_t A2 = 27;
+static const uint8_t A3 = 15;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 32;
+static const uint8_t A7 = 7;
+static const uint8_t A8 = 14;
+static const uint8_t A9 = 12;
+static const uint8_t A10 = 13;
+
+static const uint8_t BUTTON = 0;
+
+static const uint8_t T0 = 4;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_qtpy_esp32/variant.cpp b/variants/adafruit_qtpy_esp32/variant.cpp
new file mode 100644
index 00000000000..7809ec26f46
--- /dev/null
+++ b/variants/adafruit_qtpy_esp32/variant.cpp
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels.
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_qtpy_esp32c3/pins_arduino.h b/variants/adafruit_qtpy_esp32c3/pins_arduino.h
new file mode 100644
index 00000000000..92d2591a806
--- /dev/null
+++ b/variants/adafruit_qtpy_esp32c3/pins_arduino.h
@@ -0,0 +1,37 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define BUTTON 9
+
+// Neopixel
+#define PIN_NEOPIXEL 2
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 5;
+static const uint8_t SCL = 6;
+
+static const uint8_t SS = 6;
+static const uint8_t MOSI = 7;
+static const uint8_t MISO = 8;
+static const uint8_t SCK = 10;
+
+static const uint8_t A0 = 4;
+static const uint8_t A1 = 3;
+static const uint8_t A2 = 1;
+static const uint8_t A3 = 0;
+static const uint8_t A4 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_qtpy_esp32s2/bootloader-tinyuf2.bin b/variants/adafruit_qtpy_esp32s2/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..f34e2710bd9
Binary files /dev/null and b/variants/adafruit_qtpy_esp32s2/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_qtpy_esp32s2/pins_arduino.h b/variants/adafruit_qtpy_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..3baf0808db1
--- /dev/null
+++ b/variants/adafruit_qtpy_esp32s2/pins_arduino.h
@@ -0,0 +1,61 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x8111
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "QT Py ESP32-S2"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// Neopixel
+#define PIN_NEOPIXEL 39
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    38    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+
+static const uint8_t SDA = 7;
+static const uint8_t SCL = 6;
+
+#define WIRE1_PIN_DEFINED 1  // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin)
+static const uint8_t SDA1 = 41;
+static const uint8_t SCL1 = 40;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 9;
+static const uint8_t A3 = 8;
+static const uint8_t A4 = 7;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 5;
+static const uint8_t A7 = 16;
+
+static const uint8_t TX = 5;
+static const uint8_t RX = 16;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_qtpy_esp32s2/tinyuf2.bin b/variants/adafruit_qtpy_esp32s2/tinyuf2.bin
new file mode 100644
index 00000000000..008c8a1f9c4
Binary files /dev/null and b/variants/adafruit_qtpy_esp32s2/tinyuf2.bin differ
diff --git a/variants/adafruit_qtpy_esp32s2/variant.cpp b/variants/adafruit_qtpy_esp32s2/variant.cpp
new file mode 100644
index 00000000000..7809ec26f46
--- /dev/null
+++ b/variants/adafruit_qtpy_esp32s2/variant.cpp
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels.
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_qtpy_esp32s3_n4r2/bootloader-tinyuf2.bin b/variants/adafruit_qtpy_esp32s3_n4r2/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..301ccf6088c
Binary files /dev/null and b/variants/adafruit_qtpy_esp32s3_n4r2/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_qtpy_esp32s3_n4r2/pins_arduino.h b/variants/adafruit_qtpy_esp32s3_n4r2/pins_arduino.h
new file mode 100644
index 00000000000..1202ad1caca
--- /dev/null
+++ b/variants/adafruit_qtpy_esp32s3_n4r2/pins_arduino.h
@@ -0,0 +1,57 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x8143
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "QT Py ESP32-S3 (4MB Flash 2MB PSRAM)"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+#define PIN_NEOPIXEL      39
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    38    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 5;
+static const uint8_t RX = 16;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 7;
+static const uint8_t SCL = 6;
+
+#define WIRE1_PIN_DEFINED 1  // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin)
+static const uint8_t SDA1 = 41;
+static const uint8_t SCL1 = 40;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 9;
+static const uint8_t A3 = 8;
+static const uint8_t A4 = 7;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 5;
+static const uint8_t A7 = 16;
+
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_qtpy_esp32s3_n4r2/tinyuf2.bin b/variants/adafruit_qtpy_esp32s3_n4r2/tinyuf2.bin
new file mode 100644
index 00000000000..887fd31be65
Binary files /dev/null and b/variants/adafruit_qtpy_esp32s3_n4r2/tinyuf2.bin differ
diff --git a/variants/adafruit_qtpy_esp32s3_n4r2/variant.cpp b/variants/adafruit_qtpy_esp32s3_n4r2/variant.cpp
new file mode 100644
index 00000000000..7809ec26f46
--- /dev/null
+++ b/variants/adafruit_qtpy_esp32s3_n4r2/variant.cpp
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels.
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_qtpy_esp32s3_nopsram/bootloader-tinyuf2.bin b/variants/adafruit_qtpy_esp32s3_nopsram/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..ff0868213e8
Binary files /dev/null and b/variants/adafruit_qtpy_esp32s3_nopsram/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_qtpy_esp32s3_nopsram/pins_arduino.h b/variants/adafruit_qtpy_esp32s3_nopsram/pins_arduino.h
new file mode 100644
index 00000000000..55b4f4355a9
--- /dev/null
+++ b/variants/adafruit_qtpy_esp32s3_nopsram/pins_arduino.h
@@ -0,0 +1,57 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x8119
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "QT Py ESP32-S3 No PSRAM"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+#define PIN_NEOPIXEL      39
+#define NEOPIXEL_NUM      1     // number of neopixels
+#define NEOPIXEL_POWER    38    // power pin
+#define NEOPIXEL_POWER_ON HIGH  // power pin state when on
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_NEOPIXEL;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 5;
+static const uint8_t RX = 16;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 7;
+static const uint8_t SCL = 6;
+
+#define WIRE1_PIN_DEFINED 1  // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin)
+static const uint8_t SDA1 = 41;
+static const uint8_t SCL1 = 40;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 9;
+static const uint8_t A3 = 8;
+static const uint8_t A4 = 7;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 5;
+static const uint8_t A7 = 16;
+
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_qtpy_esp32s3_nopsram/tinyuf2.bin b/variants/adafruit_qtpy_esp32s3_nopsram/tinyuf2.bin
new file mode 100644
index 00000000000..5dfee90e6e5
Binary files /dev/null and b/variants/adafruit_qtpy_esp32s3_nopsram/tinyuf2.bin differ
diff --git a/variants/adafruit_qtpy_esp32s3_nopsram/variant.cpp b/variants/adafruit_qtpy_esp32s3_nopsram/variant.cpp
new file mode 100644
index 00000000000..7809ec26f46
--- /dev/null
+++ b/variants/adafruit_qtpy_esp32s3_nopsram/variant.cpp
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the NeoPixels.
+  pinMode(NEOPIXEL_POWER, OUTPUT);
+  digitalWrite(NEOPIXEL_POWER, HIGH);
+}
+}
diff --git a/variants/adafruit_qualia_s3_rgb666/bootloader-tinyuf2.bin b/variants/adafruit_qualia_s3_rgb666/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..0d437a3e3a3
Binary files /dev/null and b/variants/adafruit_qualia_s3_rgb666/bootloader-tinyuf2.bin differ
diff --git a/variants/adafruit_qualia_s3_rgb666/pins_arduino.h b/variants/adafruit_qualia_s3_rgb666/pins_arduino.h
new file mode 100644
index 00000000000..da1ed3c0c17
--- /dev/null
+++ b/variants/adafruit_qualia_s3_rgb666/pins_arduino.h
@@ -0,0 +1,66 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x239A
+#define USB_PID 0x8147
+
+#define USB_MANUFACTURER "Adafruit"
+#define USB_PRODUCT      "Qualia ESP32-S3 RGB666"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t PCA_TFT_SCK = 0;
+static const uint8_t PCA_TFT_CS = 1;
+static const uint8_t PCA_TFT_RESET = 2;
+static const uint8_t PCA_CPT_IRQ = 3;
+static const uint8_t PCA_TFT_BACKLIGHT = 4;
+static const uint8_t PCA_BUTTON_UP = 5;
+static const uint8_t PCA_BUTTON_DOWN = 6;
+static const uint8_t PCA_TFT_MOSI = 7;
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 18;
+
+static const uint8_t SS = 15;
+static const uint8_t MOSI = 7;
+static const uint8_t MISO = 6;
+static const uint8_t SCK = 5;
+
+static const uint8_t A0 = 17;
+static const uint8_t A1 = 16;
+
+static const uint8_t T3 = 3;  // Touch pin IDs map directly
+static const uint8_t T8 = 8;  // to underlying GPIO numbers NOT
+static const uint8_t T9 = 9;  // the analog numbers on board silk
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+
+static const uint8_t TFT_R1 = 11;
+static const uint8_t TFT_R2 = 10;
+static const uint8_t TFT_R3 = 9;
+static const uint8_t TFT_R4 = 46;
+static const uint8_t TFT_R5 = 3;
+static const uint8_t TFT_G0 = 48;
+static const uint8_t TFT_G1 = 47;
+static const uint8_t TFT_G2 = 21;
+static const uint8_t TFT_G3 = 14;
+static const uint8_t TFT_G4 = 13;
+static const uint8_t TFT_G5 = 12;
+static const uint8_t TFT_B1 = 40;
+static const uint8_t TFT_B2 = 39;
+static const uint8_t TFT_B3 = 38;
+static const uint8_t TFT_B4 = 0;
+static const uint8_t TFT_B5 = 45;
+static const uint8_t TFT_PCLK = 1;
+static const uint8_t TFT_DE = 2;
+static const uint8_t TFT_HSYNC = 41;
+static const uint8_t TFT_VSYNC = 42;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_qualia_s3_rgb666/tinyuf2.bin b/variants/adafruit_qualia_s3_rgb666/tinyuf2.bin
new file mode 100644
index 00000000000..ed8e9df4bcd
Binary files /dev/null and b/variants/adafruit_qualia_s3_rgb666/tinyuf2.bin differ
diff --git a/variants/adafruit_qualia_s3_rgb666/variant.cpp b/variants/adafruit_qualia_s3_rgb666/variant.cpp
new file mode 100644
index 00000000000..4b76e26411e
--- /dev/null
+++ b/variants/adafruit_qualia_s3_rgb666/variant.cpp
@@ -0,0 +1,35 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // default SD_CS to input pullup
+  pinMode(SS, INPUT_PULLUP);
+}
+}
diff --git a/variants/adafruit_sparklemotion_esp32/pins_arduino.h b/variants/adafruit_sparklemotion_esp32/pins_arduino.h
new file mode 100644
index 00000000000..99043a9758c
--- /dev/null
+++ b/variants/adafruit_sparklemotion_esp32/pins_arduino.h
@@ -0,0 +1,42 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// User LED
+static const uint8_t LED_BUILTIN = 4;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+// Neopixel
+static const uint8_t PIN_NEOPIXEL = 2;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 9;
+static const uint8_t RX = 10;
+
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 14;
+static const uint8_t SCL = 13;
+
+static const uint8_t SS = 23;
+static const uint8_t MOSI = 9;
+static const uint8_t MISO = 10;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 27;
+
+// internal switch
+static const uint8_t BUTTON = 0;
+
+static const uint8_t T0 = 27;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/adafruit_sparklemotionmini_esp32/pins_arduino.h b/variants/adafruit_sparklemotionmini_esp32/pins_arduino.h
new file mode 100644
index 00000000000..2af307de209
--- /dev/null
+++ b/variants/adafruit_sparklemotionmini_esp32/pins_arduino.h
@@ -0,0 +1,42 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// User LED
+static const uint8_t LED_BUILTIN = 12;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+// Neopixel
+static const uint8_t PIN_NEOPIXEL = 18;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_NEOPIXEL + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 25;
+static const uint8_t RX = 26;
+
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 19;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 14;
+static const uint8_t MOSI = 25;
+static const uint8_t MISO = 26;
+static const uint8_t SCK = 27;
+
+static const uint8_t A0 = 13;
+
+// internal switch
+static const uint8_t BUTTON = 0;
+
+static const uint8_t T0 = 13;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/alfredo-nou3/pins_arduino.h b/variants/alfredo-nou3/pins_arduino.h
new file mode 100644
index 00000000000..8b5a7d51b9f
--- /dev/null
+++ b/variants/alfredo-nou3/pins_arduino.h
@@ -0,0 +1,28 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#define USB_VID          0xAFD0
+#define USB_PID          0x0003
+#define USB_MANUFACTURER "Alfredo"
+#define USB_PRODUCT      "NoU3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 45
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+//static const uint8_t TX = 39;
+//static const uint8_t RX = 40;
+//#define TX1 TX
+//#define RX1 RX
+
+static const uint8_t SDA = -1;
+static const uint8_t SCL = -1;
+
+static const uint8_t SS = -1;
+static const uint8_t MOSI = -1;
+static const uint8_t SCK = -1;
+static const uint8_t MISO = -1;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/alksesp32/pins_arduino.h b/variants/alksesp32/pins_arduino.h
index f170b852632..95238aae6e4 100644
--- a/variants/alksesp32/pins_arduino.h
+++ b/variants/alksesp32/pins_arduino.h
@@ -3,19 +3,11 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-#define ALKSESP32 // tell library to not map pins again
+#define ALKSESP32  // tell library to not map pins again
 
 static const uint8_t LED_BUILTIN = 23;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -75,10 +67,10 @@ static const uint8_t S5 = 21;
 static const uint8_t SDA = 27;
 static const uint8_t SCL = 14;
 
-static const uint8_t SS    = 19;
-static const uint8_t MOSI  = 21;
-static const uint8_t MISO  = 22;
-static const uint8_t SCK   = 23;
+static const uint8_t SS = 19;
+static const uint8_t MOSI = 21;
+static const uint8_t MISO = 22;
+static const uint8_t SCK = 23;
 
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
diff --git a/variants/arduino_nano_nora/dfu_callbacks.cpp b/variants/arduino_nano_nora/dfu_callbacks.cpp
new file mode 100644
index 00000000000..fa7d57da7d9
--- /dev/null
+++ b/variants/arduino_nano_nora/dfu_callbacks.cpp
@@ -0,0 +1,105 @@
+#include "Arduino.h"
+
+#include <esp32-hal-tinyusb.h>
+#include <esp_system.h>
+
+// defines an "Update" object accessed only by this translation unit
+// (also, the object requires MD5Builder internally)
+namespace {
+// ignore '{anonymous}::MD5Builder::...() defined but not used' warnings
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-function"
+#include "../../libraries/Update/src/Updater.cpp"
+#include "../../cores/esp32/HEXBuilder.cpp"
+#include "../../cores/esp32/MD5Builder.cpp"
+#pragma GCC diagnostic pop
+}  // namespace
+
+#define ALT_COUNT 1
+
+//--------------------------------------------------------------------+
+// DFU callbacks
+// Note: alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
+//--------------------------------------------------------------------+
+
+uint16_t load_dfu_ota_descriptor(uint8_t *dst, uint8_t *itf) {
+#define DFU_ATTRS (DFU_ATTR_CAN_DOWNLOAD | DFU_ATTR_CAN_UPLOAD | DFU_ATTR_MANIFESTATION_TOLERANT)
+
+  uint8_t str_index = tinyusb_add_string_descriptor("Arduino DFU");
+  uint8_t descriptor[TUD_DFU_DESC_LEN(ALT_COUNT)] = {
+    // Interface number, string index, attributes, detach timeout, transfer size */
+    TUD_DFU_DESCRIPTOR(*itf, ALT_COUNT, str_index, DFU_ATTRS, 100, CFG_TUD_DFU_XFER_BUFSIZE),
+  };
+  *itf += 1;
+  memcpy(dst, descriptor, TUD_DFU_DESC_LEN(ALT_COUNT));
+  return TUD_DFU_DESC_LEN(ALT_COUNT);
+}
+
+// Invoked right before tud_dfu_download_cb() (state=DFU_DNBUSY) or tud_dfu_manifest_cb() (state=DFU_MANIFEST)
+// Application return timeout in milliseconds (bwPollTimeout) for the next download/manifest operation.
+// During this period, USB host won't try to communicate with us.
+uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state) {
+  if (state == DFU_DNBUSY) {
+    // longest delay for Flash writing
+    return 10;
+  } else if (state == DFU_MANIFEST) {
+    // time for esp32_ota_set_boot_partition to check final image
+    return 100;
+  }
+
+  return 0;
+}
+
+// Invoked when received DFU_DNLOAD (wLength>0) following by DFU_GETSTATUS (state=DFU_DNBUSY) requests
+// This callback could be returned before flashing op is complete (async).
+// Once finished flashing, application must call tud_dfu_finish_flashing()
+void tud_dfu_download_cb(uint8_t alt, uint16_t block_num, uint8_t const *data, uint16_t length) {
+  if (!Update.isRunning()) {
+    // this is the first data block, start update if possible
+    if (!Update.begin()) {
+      tud_dfu_finish_flashing(DFU_STATUS_ERR_TARGET);
+      return;
+    }
+  }
+
+  // write a block of data to Flash
+  // XXX: Update API is needlessly non-const
+  size_t written = Update.write(const_cast<uint8_t *>(data), length);
+  tud_dfu_finish_flashing((written == length) ? DFU_STATUS_OK : DFU_STATUS_ERR_WRITE);
+}
+
+// Invoked when download process is complete, received DFU_DNLOAD (wLength=0) following by DFU_GETSTATUS (state=Manifest)
+// Application can do checksum, or actual flashing if buffered entire image previously.
+// Once finished flashing, application must call tud_dfu_finish_flashing()
+void tud_dfu_manifest_cb(uint8_t alt) {
+  (void)alt;
+  bool ok = Update.end(true);
+
+  // flashing op for manifest is complete
+  tud_dfu_finish_flashing(ok ? DFU_STATUS_OK : DFU_STATUS_ERR_VERIFY);
+}
+
+// Invoked when received DFU_UPLOAD request
+// Application must populate data with up to length bytes and
+// Return the number of written bytes
+uint16_t tud_dfu_upload_cb(uint8_t alt, uint16_t block_num, uint8_t *data, uint16_t length) {
+  (void)alt;
+  (void)block_num;
+  (void)data;
+  (void)length;
+
+  // not implemented
+  return 0;
+}
+
+// Invoked when the Host has terminated a download or upload transfer
+void tud_dfu_abort_cb(uint8_t alt) {
+  (void)alt;
+  // ignore
+}
+
+// Invoked when a DFU_DETACH request is received
+void tud_dfu_detach_cb(void) {
+  // done, reboot
+  esp_restart();
+}
diff --git a/variants/arduino_nano_nora/double_tap.c b/variants/arduino_nano_nora/double_tap.c
new file mode 100644
index 00000000000..e371be60422
--- /dev/null
+++ b/variants/arduino_nano_nora/double_tap.c
@@ -0,0 +1,69 @@
+#include <string.h>
+
+#include <esp_system.h>
+#include <esp32s3/rom/cache.h>
+#include <esp_heap_caps.h>
+
+#include "double_tap.h"
+
+#define NUM_TOKENS 3
+static const uint32_t MAGIC_TOKENS[NUM_TOKENS] = {
+  0xf01681de,
+  0xbd729b29,
+  0xd359be7a,
+};
+
+static void *magic_area;
+static uint32_t backup_area[NUM_TOKENS];
+
+#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0)
+// Current IDF does not map external RAM to a fixed address.
+// The actual VMA depends on other enabled devices, so the precise
+// location must be discovered.
+#include <esp_psram.h>
+#include <esp_private/esp_psram_extram.h>
+static uintptr_t get_extram_data_high(void) {
+  // get a pointer into SRAM area (only the address is useful)
+  void *psram_ptr = heap_caps_malloc(16, MALLOC_CAP_SPIRAM);
+  heap_caps_free(psram_ptr);
+
+  // keep moving backwards until leaving PSRAM area
+  uintptr_t psram_base_addr = (uintptr_t)psram_ptr;
+  psram_base_addr &= ~(CONFIG_MMU_PAGE_SIZE - 1);  // align to start of page
+  while (esp_psram_check_ptr_addr((void *)psram_base_addr)) {
+    psram_base_addr -= CONFIG_MMU_PAGE_SIZE;
+  }
+
+  // offset is one page from start of PSRAM
+  return psram_base_addr + CONFIG_MMU_PAGE_SIZE + esp_psram_get_size();
+}
+#else
+#include <soc/soc.h>
+#define get_extram_data_high() ((uintptr_t)SOC_EXTRAM_DATA_HIGH)
+#endif
+
+void double_tap_init(void) {
+  // magic location block ends 0x20 bytes from end of PSRAM
+  magic_area = (void *)(get_extram_data_high() - 0x20 - sizeof(MAGIC_TOKENS));
+}
+
+void double_tap_mark() {
+  memcpy(backup_area, magic_area, sizeof(MAGIC_TOKENS));
+  memcpy(magic_area, MAGIC_TOKENS, sizeof(MAGIC_TOKENS));
+  Cache_WriteBack_Addr((uintptr_t)magic_area, sizeof(MAGIC_TOKENS));
+}
+
+void double_tap_invalidate() {
+  if (memcmp(backup_area, MAGIC_TOKENS, sizeof(MAGIC_TOKENS))) {
+    // different contents: restore backup
+    memcpy(magic_area, backup_area, sizeof(MAGIC_TOKENS));
+  } else {
+    // clear memory
+    memset(magic_area, 0, sizeof(MAGIC_TOKENS));
+  }
+  Cache_WriteBack_Addr((uintptr_t)magic_area, sizeof(MAGIC_TOKENS));
+}
+
+bool double_tap_check_match() {
+  return (memcmp(magic_area, MAGIC_TOKENS, sizeof(MAGIC_TOKENS)) == 0);
+}
diff --git a/variants/arduino_nano_nora/double_tap.h b/variants/arduino_nano_nora/double_tap.h
new file mode 100644
index 00000000000..e797f4f64fd
--- /dev/null
+++ b/variants/arduino_nano_nora/double_tap.h
@@ -0,0 +1,20 @@
+#ifndef __DOUBLE_TAP_H__
+#define __DOUBLE_TAP_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void double_tap_init(void);
+void double_tap_mark(void);
+void double_tap_invalidate(void);
+bool double_tap_check_match(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DOUBLE_TAP_H__ */
diff --git a/variants/arduino_nano_nora/extra/nora_recovery/README.md b/variants/arduino_nano_nora/extra/nora_recovery/README.md
new file mode 100644
index 00000000000..786027dc6e3
--- /dev/null
+++ b/variants/arduino_nano_nora/extra/nora_recovery/README.md
@@ -0,0 +1,49 @@
+
+# Arduino Nano Nora Recovery Sketch
+
+This sketch implements the DFU recovery mode logic, called by all sketches
+when a double tap on the RESET button is detected. It should not be uploaded
+as any other sketch; instead, this should be compiled and then flashed in
+the module's `factory` partition.
+
+## Compilation
+
+The binary can be compiled with the Arduino 2.x IDE or CLI using the
+`nano_nora` variant. In particular, using the CLI the resulting binary
+can be exported to the `build` directory with the `-e` switch to
+`arduino-cli compile`.
+
+## Automatic installation
+
+By replacing the binary in the current folder, automatic installation
+can be performed by running the "Upload with Programmer" action on any
+sketch in the Arduino 2.x IDE or CLI. In particular, using the CLI the
+binary can be installed via the command:
+
+```
+arduino-cli compile -u --programmer esptool
+```
+
+## Manual installation
+
+Once compiled, the binary can also be installed on a board using `esptool.py`
+with the following command:
+
+```
+esptool.py --chip esp32s3 --port "/dev/ttyACM0" --baud 921600  --before default_reset --after hard_reset write_flash  -z --flash_mode dio --flash_freq 80m --flash_size 16MB 0xF70000 "nora_recovery.ino.bin"
+```
+
+where:
+- `esptool.py` is located in your core's install path under `tools/esptool_py`;
+- `/dev/ttyACM0` is the serial port exposed by the board to be used;
+- `0xF70000` is the factory partition address (make sure it matches the
+  offset in the variant's `{build.partitions}` file);
+- `nora_recovery.ino.bin` is the compiled sketch image.
+
+Due to a BSP issue, the first call to `esptool.py` will enter the hardware
+bootloader for programming, but fail with an "Input/output error". This is
+a known issue; calling the program again with the same arguments will now
+work correctly.
+
+Once flashing is complete, a power cycle (or RESET button tap) is required
+to leave the `esptool.py` flashing mode and load user sketches.
diff --git a/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino b/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino
new file mode 100644
index 00000000000..fbaa340af6d
--- /dev/null
+++ b/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino
@@ -0,0 +1,100 @@
+#include "USB.h"
+
+#define USB_TIMEOUT_MS 15000
+#define POLL_DELAY_MS  60
+#define FADESTEP       8
+
+void pulse_led() {
+  static uint32_t pulse_width = 0;
+  static uint8_t dir = 0;
+
+  if (dir) {
+    pulse_width -= FADESTEP;
+    if (pulse_width < FADESTEP) {
+      dir = 0U;
+      pulse_width = FADESTEP;
+    }
+  } else {
+    pulse_width += FADESTEP;
+    if (pulse_width > 255) {
+      dir = 1U;
+      pulse_width = 255;
+    }
+  }
+
+  analogWrite(LED_GREEN, pulse_width);
+}
+
+#include <esp_ota_ops.h>
+#include <esp_partition.h>
+#include <esp_flash_partitions.h>
+#include <esp_image_format.h>
+const esp_partition_t *find_previous_firmware() {
+  extern bool _recovery_active;
+  if (!_recovery_active) {
+    // user flashed this recovery sketch to an OTA partition
+    // stay here and wait for a proper firmware
+    return NULL;
+  }
+
+  // booting from factory partition, look for a valid OTA image
+  esp_partition_iterator_t it = esp_partition_find(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, NULL);
+  for (; it != NULL; it = esp_partition_next(it)) {
+    const esp_partition_t *part = esp_partition_get(it);
+    if (part->subtype != ESP_PARTITION_SUBTYPE_APP_FACTORY) {
+      esp_partition_pos_t candidate = {part->address, part->size};
+      esp_image_metadata_t meta;
+      if (esp_image_verify(ESP_IMAGE_VERIFY_SILENT, &candidate, &meta) == ESP_OK) {
+        // found, use it
+        return part;
+      }
+    }
+  }
+
+  return NULL;
+}
+
+const esp_partition_t *user_part = NULL;
+
+void setup() {
+  user_part = find_previous_firmware();
+  if (user_part) {
+    esp_ota_set_boot_partition(user_part);
+  }
+
+  extern bool _recovery_marker_found;
+  if (!_recovery_marker_found && user_part) {
+    // recovery marker not found, probable cold start
+    // try starting previous firmware immediately
+    esp_restart();
+  }
+
+  // recovery marker found, or nothing else to load
+  printf("Recovery firmware started, waiting for USB\r\n");
+}
+
+void loop() {
+  static int elapsed_ms = 0;
+
+  pulse_led();
+  delay(POLL_DELAY_MS);
+  if (USB) {
+    // wait indefinitely for DFU to complete
+    elapsed_ms = 0;
+  } else {
+    // wait for USB connection
+    elapsed_ms += POLL_DELAY_MS;
+  }
+
+  if (elapsed_ms > USB_TIMEOUT_MS) {
+    elapsed_ms = 0;
+    // timed out, try loading previous firmware
+    if (user_part) {
+      // there was a valid FW image, load it
+      analogWrite(LED_GREEN, 255);
+      printf("Leaving recovery firmware\r\n");
+      delay(200);
+      esp_restart();  // does not return
+    }
+  }
+}
diff --git a/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino.bin b/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino.bin
new file mode 100644
index 00000000000..ee5e7d5452e
Binary files /dev/null and b/variants/arduino_nano_nora/extra/nora_recovery/nora_recovery.ino.bin differ
diff --git a/variants/arduino_nano_nora/io_pin_remap.cpp b/variants/arduino_nano_nora/io_pin_remap.cpp
new file mode 100644
index 00000000000..f615f572905
--- /dev/null
+++ b/variants/arduino_nano_nora/io_pin_remap.cpp
@@ -0,0 +1,73 @@
+#if defined(BOARD_HAS_PIN_REMAP) && !defined(ARDUINO_CORE_BUILD)
+// -DARDUINO_CORE_BUILD must be set for core files only, to avoid extra
+// remapping steps that would create all sorts of issues in the core.
+// Removing -DBOARD_HAS_PIN_REMAP at least does correctly restore the
+// use of GPIO numbers in the API.
+#error This build system is not supported. Please rebuild without BOARD_HAS_PIN_REMAP.
+#endif
+
+#if !defined(BOARD_HAS_PIN_REMAP)
+// This board uses pin mapping but the build system has disabled it
+#warning The build system forces the Arduino API to use GPIO numbers on a board that has custom pin mapping.
+#elif defined(BOARD_USES_HW_GPIO_NUMBERS)
+// The user has chosen to disable pin mapping.
+#warning The Arduino API will use GPIO numbers for this build.
+#endif
+
+#include "Arduino.h"
+
+// NOTE: This must match with the remapped pin sequence in pins_arduino.h
+static const int8_t TO_GPIO_NUMBER[] = {
+  44,  // [ 0] D0, RX
+  43,  // [ 1] D1, TX
+  5,   // [ 2] D2
+  6,   // [ 3] D3, CTS
+  7,   // [ 4] D4, DSR
+  8,   // [ 5] D5
+  9,   // [ 6] D6
+  10,  // [ 7] D7
+  17,  // [ 8] D8
+  18,  // [ 9] D9
+  21,  // [10] D10, SS
+  38,  // [11] D11, MOSI
+  47,  // [12] D12, MISO
+  48,  // [13] D13, SCK, LED_BUILTIN
+  46,  // [14] LED_RED
+  0,   // [15] LED_GREEN
+  45,  // [16] LED_BLUE, RTS
+  1,   // [17] A0, DTR
+  2,   // [18] A1
+  3,   // [19] A2
+  4,   // [20] A3
+  11,  // [21] A4, SDA
+  12,  // [22] A5, SCL
+  13,  // [23] A6
+  14,  // [24] A7
+};
+
+#if defined(BOARD_HAS_PIN_REMAP) && !defined(BOARD_USES_HW_GPIO_NUMBERS)
+
+int8_t digitalPinToGPIONumber(int8_t digitalPin) {
+  if ((digitalPin < 0) || (digitalPin >= NUM_DIGITAL_PINS)) {
+    return -1;
+  }
+  return TO_GPIO_NUMBER[digitalPin];
+}
+
+int8_t gpioNumberToDigitalPin(int8_t gpioNumber) {
+  if (gpioNumber < 0) {
+    return -1;
+  }
+
+  // slow linear table lookup
+  for (int8_t digitalPin = 0; digitalPin < NUM_DIGITAL_PINS; ++digitalPin) {
+    if (TO_GPIO_NUMBER[digitalPin] == gpioNumber) {
+      return digitalPin;
+    }
+  }
+
+  // not found
+  return -1;
+}
+
+#endif
diff --git a/variants/arduino_nano_nora/pins_arduino.h b/variants/arduino_nano_nora/pins_arduino.h
new file mode 100644
index 00000000000..2772d6f15da
--- /dev/null
+++ b/variants/arduino_nano_nora/pins_arduino.h
@@ -0,0 +1,114 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x2341
+#define USB_PID 0x0070
+
+#ifndef __cplusplus
+#define constexpr const
+#endif
+
+// primary pin names
+
+#if defined(BOARD_HAS_PIN_REMAP) && !defined(BOARD_USES_HW_GPIO_NUMBERS)
+
+// Arduino style definitions (API uses Dx)
+
+static constexpr uint8_t D0 = 0;  // also RX
+static constexpr uint8_t D1 = 1;  // also TX
+static constexpr uint8_t D2 = 2;
+static constexpr uint8_t D3 = 3;  // also CTS
+static constexpr uint8_t D4 = 4;  // also DSR
+static constexpr uint8_t D5 = 5;
+static constexpr uint8_t D6 = 6;
+static constexpr uint8_t D7 = 7;
+static constexpr uint8_t D8 = 8;
+static constexpr uint8_t D9 = 9;
+static constexpr uint8_t D10 = 10;  // also SS
+static constexpr uint8_t D11 = 11;  // also MOSI
+static constexpr uint8_t D12 = 12;  // also MISO
+static constexpr uint8_t D13 = 13;  // also SCK, LED_BUILTIN
+static constexpr uint8_t LED_RED = 14;
+static constexpr uint8_t LED_GREEN = 15;
+static constexpr uint8_t LED_BLUE = 16;  // also RTS
+
+static constexpr uint8_t A0 = 17;  // also DTR
+static constexpr uint8_t A1 = 18;
+static constexpr uint8_t A2 = 19;
+static constexpr uint8_t A3 = 20;
+static constexpr uint8_t A4 = 21;  // also SDA
+static constexpr uint8_t A5 = 22;  // also SCL
+static constexpr uint8_t A6 = 23;
+static constexpr uint8_t A7 = 24;
+
+#else
+
+// ESP32-style definitions (API uses GPIOx)
+
+static constexpr uint8_t D0 = 44;  // also RX
+static constexpr uint8_t D1 = 43;  // also TX
+static constexpr uint8_t D2 = 5;
+static constexpr uint8_t D3 = 6;  // also CTS
+static constexpr uint8_t D4 = 7;  // also DSR
+static constexpr uint8_t D5 = 8;
+static constexpr uint8_t D6 = 9;
+static constexpr uint8_t D7 = 10;
+static constexpr uint8_t D8 = 17;
+static constexpr uint8_t D9 = 18;
+static constexpr uint8_t D10 = 21;  // also SS
+static constexpr uint8_t D11 = 38;  // also MOSI
+static constexpr uint8_t D12 = 47;  // also MISO
+static constexpr uint8_t D13 = 48;  // also SCK, LED_BUILTIN
+static constexpr uint8_t LED_RED = 46;
+static constexpr uint8_t LED_GREEN = 0;
+static constexpr uint8_t LED_BLUE = 45;  // also RTS
+
+static constexpr uint8_t A0 = 1;  // also DTR
+static constexpr uint8_t A1 = 2;
+static constexpr uint8_t A2 = 3;
+static constexpr uint8_t A3 = 4;
+static constexpr uint8_t A4 = 11;  // also SDA
+static constexpr uint8_t A5 = 12;  // also SCL
+static constexpr uint8_t A6 = 13;
+static constexpr uint8_t A7 = 14;
+
+#endif
+
+// Aliases
+
+static constexpr uint8_t LEDR = LED_RED;
+static constexpr uint8_t LEDG = LED_GREEN;
+static constexpr uint8_t LEDB = LED_BLUE;
+
+// alternate pin functions
+
+static constexpr uint8_t LED_BUILTIN = D13;
+
+static constexpr uint8_t TX = D1;
+static constexpr uint8_t RX = D0;
+static constexpr uint8_t RTS = LED_BLUE;
+static constexpr uint8_t CTS = D3;
+static constexpr uint8_t DTR = A0;
+static constexpr uint8_t DSR = D4;
+
+static constexpr uint8_t SS = D10;
+static constexpr uint8_t MOSI = D11;
+static constexpr uint8_t MISO = D12;
+static constexpr uint8_t SCK = D13;
+
+static constexpr uint8_t SDA = A4;
+static constexpr uint8_t SCL = A5;
+
+#define PIN_I2S_SCK    D7
+#define PIN_I2S_FS     D8
+#define PIN_I2S_SD     D9
+#define PIN_I2S_SD_OUT D9  // same as bidir
+#define PIN_I2S_SD_IN  D10
+
+#ifndef __cplusplus
+#undef constexpr
+#endif
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/arduino_nano_nora/variant.cpp b/variants/arduino_nano_nora/variant.cpp
new file mode 100644
index 00000000000..df28d0dd10e
--- /dev/null
+++ b/variants/arduino_nano_nora/variant.cpp
@@ -0,0 +1,101 @@
+// Enable pin remapping in this file, so pin constants are meaningful
+#undef ARDUINO_CORE_BUILD
+
+#include "Arduino.h"
+
+#include "double_tap.h"
+
+#include <esp_system.h>
+#include <esp_ota_ops.h>
+#include <esp_partition.h>
+
+extern "C" {
+void initVariant() {
+  // nothing to do
+}
+}
+
+// global, accessible from recovery sketch
+bool _recovery_marker_found;  // double tap detected
+bool _recovery_active;        // running from factory partition
+
+#define DELAY_US 10000
+#define FADESTEP 8
+static void rgb_pulse_delay(void) {
+  //                Bv   R^  G  x
+  int widths[4] = {192, 64, 0, 0};
+  int dec_led = 0;
+
+  // initialize RGB signals from weak pinstraps
+  pinMode(LED_RED, OUTPUT);
+  pinMode(LED_GREEN, OUTPUT);
+  pinMode(LED_BLUE, OUTPUT);
+  while (dec_led < 3) {
+    widths[dec_led] -= FADESTEP;
+    widths[dec_led + 1] += FADESTEP;
+    if (widths[dec_led] <= 0) {
+      widths[dec_led] = 0;
+      dec_led = dec_led + 1;
+      widths[dec_led] = 255;
+    }
+
+    analogWrite(LED_RED, 255 - widths[1]);
+    analogWrite(LED_GREEN, 255 - widths[2]);
+    analogWrite(LED_BLUE, 255 - widths[0]);
+    delayMicroseconds(DELAY_US);
+  }
+
+  // reset pins to digital HIGH before leaving
+  digitalWrite(LED_RED, HIGH);
+  digitalWrite(LED_GREEN, HIGH);
+  digitalWrite(LED_BLUE, HIGH);
+}
+
+static void NANO_ESP32_enter_bootloader(void) {
+  if (!_recovery_active) {
+    // check for valid partition scheme
+    const esp_partition_t *ota_part = esp_ota_get_next_update_partition(NULL);
+    const esp_partition_t *fact_part = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_APP_FACTORY, NULL);
+    if (ota_part && fact_part) {
+      // set tokens so the recovery FW will find them
+      double_tap_mark();
+      // invalidate other OTA image
+      esp_partition_erase_range(ota_part, 0, 4096);
+      // activate factory partition
+      esp_ota_set_boot_partition(fact_part);
+    }
+  }
+
+  esp_restart();
+}
+
+static void boot_double_tap_logic() {
+  const esp_partition_t *part = esp_ota_get_running_partition();
+  _recovery_active = (part->subtype == ESP_PARTITION_SUBTYPE_APP_FACTORY);
+
+  double_tap_init();
+
+  _recovery_marker_found = double_tap_check_match();
+  if (_recovery_marker_found && !_recovery_active) {
+    // double tap detected in user application, reboot to factory
+    NANO_ESP32_enter_bootloader();
+  }
+
+  // delay with mark set then proceed
+  // - for normal startup, to detect first double tap
+  // - in recovery mode, to ignore several short presses
+  double_tap_mark();
+  rgb_pulse_delay();
+  double_tap_invalidate();
+}
+
+namespace {
+class DoubleTap {
+public:
+  DoubleTap() {
+    boot_double_tap_logic();
+  }
+};
+
+DoubleTap dt __attribute__((init_priority(101)));
+}  // namespace
diff --git a/variants/aslcanx2/default_8MB_ffat.csv b/variants/aslcanx2/default_8MB_ffat.csv
new file mode 100644
index 00000000000..2791bf7912e
--- /dev/null
+++ b/variants/aslcanx2/default_8MB_ffat.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0x330000,
+app1,     app,  ota_1,   0x340000,0x330000,
+ffat,     data, fat,     0x670000,0x180000,
+coredump, data, coredump,0x7F0000,0x10000,
diff --git a/variants/aslcanx2/pins_arduino.h b/variants/aslcanx2/pins_arduino.h
new file mode 100644
index 00000000000..eb876a09708
--- /dev/null
+++ b/variants/aslcanx2/pins_arduino.h
@@ -0,0 +1,65 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x16D0
+#define USB_PID 0x07F2
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN
+
+static const uint8_t CAN1_RX = 6;
+static const uint8_t CAN1_TX = 7;
+
+static const uint8_t SS = -1;
+static const uint8_t CS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/atd147_s3/pins_arduino.h b/variants/atd147_s3/pins_arduino.h
new file mode 100644
index 00000000000..873ca211a0b
--- /dev/null
+++ b/variants/atd147_s3/pins_arduino.h
@@ -0,0 +1,67 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+#define LCD_CS  SS
+#define LCD_SCK SCK
+#define LCD_SDA MOSI
+static const uint8_t LCD_DC = 21;
+static const uint8_t LCD_RES = 14;
+
+static const uint8_t BTN_A = 4;
+static const uint8_t BTN_B = 5;
+static const uint8_t BTN_C = 45;
+#define KEY_BUILTIN BTN_A
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/atd35s3/pins_arduino.h b/variants/atd35s3/pins_arduino.h
new file mode 100644
index 00000000000..c973693b71c
--- /dev/null
+++ b/variants/atd35s3/pins_arduino.h
@@ -0,0 +1,78 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+// LCD pin
+#define LCD_CS  SS
+#define LCD_SCK SCK
+#define LCD_SDA MOSI
+static const uint8_t LCD_DC = 21;
+static const uint8_t LCD_RES = 14;
+static const uint8_t LCD_BL = 3;
+
+// MicroSD Card pin
+static const uint8_t SD_CS = 18;
+static const uint8_t SD_CD = 17;
+
+static const uint8_t BTN_A = 4;
+#define KEY_BUILTIN BTN_A
+
+static const uint8_t LED_BUILTIN = 5;
+
+// DAC pin
+static const uint8_t DAC_DIN = 47;
+static const uint8_t DAC_BCLK = 48;
+static const uint8_t DAC_WS = 45;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/atmegazero_esp32s2/bootloader-tinyuf2.bin b/variants/atmegazero_esp32s2/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..d52b958ec96
Binary files /dev/null and b/variants/atmegazero_esp32s2/bootloader-tinyuf2.bin differ
diff --git a/variants/atmegazero_esp32s2/partitions-16MB-tinyuf2.csv b/variants/atmegazero_esp32s2/partitions-16MB-tinyuf2.csv
new file mode 100644
index 00000000000..003418ceac2
--- /dev/null
+++ b/variants/atmegazero_esp32s2/partitions-16MB-tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  11968K,
diff --git a/variants/atmegazero_esp32s2/pins_arduino.h b/variants/atmegazero_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..dda442c20e2
--- /dev/null
+++ b/variants/atmegazero_esp32s2/pins_arduino.h
@@ -0,0 +1,60 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x800A
+#define USB_MANUFACTURER "ATMegaZero"
+#define USB_PRODUCT      "ATMZ-ESP32S2"
+#define USB_SERIAL       ""
+
+static const uint8_t RGB_LED_PIN = 40;
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = (RGB_LED_PIN + SOC_GPIO_PIN_COUNT);
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t PD5 = 0;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 38;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 17;
+static const uint8_t A1 = 18;
+static const uint8_t A2 = 13;
+static const uint8_t A3 = 12;
+static const uint8_t A4 = 6;
+static const uint8_t A5 = 3;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/atmegazero_esp32s2/tinyuf2.bin b/variants/atmegazero_esp32s2/tinyuf2.bin
new file mode 100644
index 00000000000..6e78e5431d7
Binary files /dev/null and b/variants/atmegazero_esp32s2/tinyuf2.bin differ
diff --git a/variants/bpi-bit/pins_arduino.h b/variants/bpi-bit/pins_arduino.h
index 2a317a9abf9..42a820a0b26 100644
--- a/variants/bpi-bit/pins_arduino.h
+++ b/variants/bpi-bit/pins_arduino.h
@@ -2,22 +2,22 @@
 #define Pins_Arduino_h
 
 #include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS 40
-#define NUM_ANALOG_INPUTS 16
-
-#define analogInputToDigitalPin(p) (((p) < 20) ? (esp32_adc2gpio[(p)]) : -1)
-#define digitalPinToInterrupt(p) (((p) < 40) ? (p) : -1)
-#define digitalPinHasPWM(p) (p < 34)
+#include "soc/soc_caps.h"
 
 static const uint8_t BUZZER = 25;
 
 static const uint8_t BUTTON_A = 35;
 static const uint8_t BUTTON_B = 27;
 
+// RGB LED Matrix 5 x 5
 static const uint8_t RGB_LED = 4;
 
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+#define LED_BUILTIN (RGB_LED + SOC_GPIO_PIN_COUNT)  // Just a single LED in the Matrix
+#define BUILTIN_LED LED_BUILTIN                     // backward compatibility
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
 static const uint8_t LIGHT_SENSOR1 = 36;
 static const uint8_t LIGHT_SENSOR2 = 39;
 
diff --git a/variants/bpi_leaf_s3/pins_arduino.h b/variants/bpi_leaf_s3/pins_arduino.h
new file mode 100644
index 00000000000..3a22a46bfc1
--- /dev/null
+++ b/variants/bpi_leaf_s3/pins_arduino.h
@@ -0,0 +1,72 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303a
+#define USB_PID          0x80df
+#define USB_MANUFACTURER "Banana Pi"
+#define USB_PRODUCT      "BPI-Leaf-S3"
+#define USB_SERIAL       ""
+
+// Some boards have too low voltage on this pin (board design bug)
+// Use different pin with 3V and connect with 48
+// and change this setup for the chosen pin (for example 38)
+#define PIN_RGB_LED 48
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 25
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 15;
+static const uint8_t SCL = 16;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/cezerio_dev_esp32c6/pins_arduino.h b/variants/cezerio_dev_esp32c6/pins_arduino.h
new file mode 100644
index 00000000000..3ffc59aee6f
--- /dev/null
+++ b/variants/cezerio_dev_esp32c6/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x1001
+#define USB_MANUFACTURER "RFtek Electronics"
+#define USB_PRODUCT      "cezerio dev ESP32C6"
+#define USB_SERIAL       ""
+
+#define PIN_RGB_LED 3
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGBLED         LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t BUT_BUILTIN = 9;
+#define BUILTIN_BUT BUT_BUILTIN  // backward compatibility
+#define BUT_BUILTIN BUT_BUILTIN  // allow testing #ifdef BUT_BUILTIN
+#define BOOT        BUT_BUILTIN
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 7;
+
+static const uint8_t SS = 14;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 23;
+static const uint8_t SCK = 21;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+
+static const uint8_t MATRIX = 18;
+
+static const uint8_t IMUSD = 8;
+static const uint8_t IMUSC = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/cezerio_mini_dev_esp32c6/pins_arduino.h b/variants/cezerio_mini_dev_esp32c6/pins_arduino.h
new file mode 100644
index 00000000000..e7ef94e5a64
--- /dev/null
+++ b/variants/cezerio_mini_dev_esp32c6/pins_arduino.h
@@ -0,0 +1,47 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x1001
+#define USB_MANUFACTURER "RFtek Electronics"
+#define USB_PRODUCT      "cezerio mini dev ESP32C6"
+#define USB_SERIAL       ""
+
+#define PIN_RGB_LED 20
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGBLED         LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t BUT_BUILTIN = 9;
+#define BUILTIN_BUT BUT_BUILTIN  // backward compatibility
+#define BUT_BUILTIN BUT_BUILTIN  // allow testing #ifdef BUT_BUILTIN
+#define BOOT        BUT_BUILTIN
+
+static const uint8_t TX = 7;
+static const uint8_t RX = 14;
+
+static const uint8_t SDA = 23;
+static const uint8_t SCL = 22;
+
+static const uint8_t MOSI = 19;
+static const uint8_t MISO = 21;
+static const uint8_t SCK = 18;
+static const uint8_t SS = 17;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A6 = 6;
+
+static const uint8_t MATRIX = 4;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/ch_denky/pins_arduino.h b/variants/ch_denky/pins_arduino.h
new file mode 100644
index 00000000000..11792a15af3
--- /dev/null
+++ b/variants/ch_denky/pins_arduino.h
@@ -0,0 +1,70 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+// Specific CH2i (Charles Hallard) Boards
+// 1st Revision Denky with ESP WROOM32 + LoRa RN2483 module
+#if defined(ARDUINO_DENKY_WROOM32)
+#define PUSH_BUTTON    0
+#define TIC_ENABLE_PIN 4
+#define TIC_RX_PIN     33
+#define LORA_TX_PIN    26
+#define LORA_RX_PIN    27
+#define LORA_RESET     14
+#define RGB_LED_PIN    25
+
+// 2nd Utra Small version with ESP Pico-D4-V3-02
+#elif defined(ARDUINO_DENKY_PICOV3)
+// RGB Led Pins
+#define LED_RED_PIN 27
+#define LED_GRN_PIN 26
+#define LED_BLU_PIN 25
+
+// Teleinfo RXD pin is connected to ESP32-PICO-V3-02 GPIO8
+#define TIC_RX_PIN  8
+#endif
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/circuitart_zero_s3/bootloader_tinyuf2.bin b/variants/circuitart_zero_s3/bootloader_tinyuf2.bin
new file mode 100644
index 00000000000..901005128d9
Binary files /dev/null and b/variants/circuitart_zero_s3/bootloader_tinyuf2.bin differ
diff --git a/variants/circuitart_zero_s3/partitions_tinyuf2.csv b/variants/circuitart_zero_s3/partitions_tinyuf2.csv
new file mode 100644
index 00000000000..55f6c2b8d76
--- /dev/null
+++ b/variants/circuitart_zero_s3/partitions_tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    app,  ota_0,   0x10000,  2048K,
+ota_1,    app,  ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  11968K,
diff --git a/variants/circuitart_zero_s3/pins_arduino.h b/variants/circuitart_zero_s3/pins_arduino.h
new file mode 100644
index 00000000000..adf38ca672f
--- /dev/null
+++ b/variants/circuitart_zero_s3/pins_arduino.h
@@ -0,0 +1,137 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303A
+#define USB_PID          0x80DB
+#define USB_MANUFACTURER "CircuitART"
+#define USB_PRODUCT      "ZeroS3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 46
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// RGB LED
+#define PIN_RGB_LED 47
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() and digitalWrite() for blinking
+#define RGB_BUILTIN    (PIN_RGB_LED + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+#define RGBLED_NUM     1  // number of RGB LEDs
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t TFT_DC = 5;
+static const uint8_t TFT_CS = 39;
+static const uint8_t TFT_RST = 40;
+static const uint8_t TFT_RESET = 40;
+
+static const uint8_t SD_CS = 42;
+static const uint8_t SD_CHIP_SELECT = 42;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+static const uint8_t TX0 = 43;
+static const uint8_t RX0 = 44;
+
+static const uint8_t TX1 = 40;
+static const uint8_t RX2 = 41;
+
+static const uint8_t SDA = 33;
+static const uint8_t SCL = 34;
+
+static const uint8_t SS = 39;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+static const uint8_t T15 = 15;
+
+static const uint8_t D0 = 0;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 2;
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 4;
+static const uint8_t D5 = 5;
+static const uint8_t D6 = 6;
+static const uint8_t D7 = 7;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D10 = 10;
+static const uint8_t D11 = 11;
+static const uint8_t D12 = 12;
+static const uint8_t D13 = 13;
+static const uint8_t D14 = 14;
+static const uint8_t D15 = 15;
+static const uint8_t D16 = 16;
+static const uint8_t D17 = 17;
+static const uint8_t D18 = 18;
+static const uint8_t D33 = 33;
+static const uint8_t D34 = 34;
+static const uint8_t D35 = 35;
+static const uint8_t D36 = 36;
+static const uint8_t D37 = 37;
+static const uint8_t D38 = 38;
+static const uint8_t D39 = 39;
+static const uint8_t D40 = 40;
+static const uint8_t D41 = 41;
+
+// Camera
+#define TFT_CAM_POWER 21
+
+#define PWDN_GPIO_NUM  -1  // connected through expander
+#define RESET_GPIO_NUM -1  // connected through expander
+#define XCLK_GPIO_NUM  15
+#define SIOD_GPIO_NUM  SDA
+#define SIOC_GPIO_NUM  SCL
+
+#define Y9_GPIO_NUM    14  //16
+#define Y8_GPIO_NUM    13  //14
+#define Y7_GPIO_NUM    11  //13
+#define Y6_GPIO_NUM    10
+#define Y5_GPIO_NUM    9  //8
+#define Y4_GPIO_NUM    8  //6
+#define Y3_GPIO_NUM    7
+#define Y2_GPIO_NUM    6  //9
+#define VSYNC_GPIO_NUM 38
+#define HREF_GPIO_NUM  48
+#define PCLK_GPIO_NUM  16  //11
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/circuitart_zero_s3/tinyuf2.bin b/variants/circuitart_zero_s3/tinyuf2.bin
new file mode 100644
index 00000000000..5c4db2984c7
Binary files /dev/null and b/variants/circuitart_zero_s3/tinyuf2.bin differ
diff --git a/variants/cnrs_aw2eth/pins_arduino.h b/variants/cnrs_aw2eth/pins_arduino.h
new file mode 100644
index 00000000000..11b4ba8e38a
--- /dev/null
+++ b/variants/cnrs_aw2eth/pins_arduino.h
@@ -0,0 +1,48 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 9;
+static const uint8_t SCL = 10;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 14;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/codecell/pins_arduino.h b/variants/codecell/pins_arduino.h
new file mode 100644
index 00000000000..b4b0f0bd2dd
--- /dev/null
+++ b/variants/codecell/pins_arduino.h
@@ -0,0 +1,25 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/connaxio_espoir/pins_arduino.h b/variants/connaxio_espoir/pins_arduino.h
new file mode 100644
index 00000000000..2a6a47e3645
--- /dev/null
+++ b/variants/connaxio_espoir/pins_arduino.h
@@ -0,0 +1,77 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+/* variant: Espoir
+ * vendor: Connaxio
+ * url: https://www.connaxio.com/electronics/espoir/
+ */
+
+#include <stdint.h>
+
+/* USB UART */
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+/* mikroBUS UART */
+static const uint8_t TX1 = 10;
+static const uint8_t RX1 = 9;
+
+/* mikroBUS I2C */
+static const uint8_t SDA = 23;
+static const uint8_t SCL = 18;
+
+/* mikroBUS SPI */
+static const uint8_t SS = 15;
+static const uint8_t MOSI = 13;
+static const uint8_t MISO = 12;
+static const uint8_t SCK = 14;
+
+/* Default analog pins */
+static const uint8_t A0 = 36;
+static const uint8_t A1 = 37;
+static const uint8_t A2 = 38;
+static const uint8_t A3 = 39;
+static const uint8_t A6 = 34;
+
+/* Alternative analog pins */
+static const uint8_t A10 = 4;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+
+/* Touch pins */
+static const uint8_t T0 = 4;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+
+/* Other pin names */
+static const uint8_t AN = 36;
+static const uint8_t RST = 5;
+static const uint8_t PWM = 2;
+static const uint8_t INT = 4;
+static const uint8_t CS = 15;
+static const uint8_t SDO = 13;
+static const uint8_t SDI = 12;
+
+/* Ethernet interface */
+static const uint8_t ETH_INT = 35;
+#define ETH_PHY_ADDR  0
+#define ETH_PHY_POWER -1
+#define ETH_PHY_MDC   32
+#define ETH_PHY_MDIO  33
+#define ETH_PHY_TYPE  ETH_PHY_KSZ8081
+#define ETH_CLK_MODE  ETH_CLOCK_GPIO0_IN
+
+/* USB interface */
+#define USB_VID          0x10C4  // Silabs's VID
+#define USB_PID          0x8D9A  // Espoir's PID, requires Silab USB PHY
+#define USB_MANUFACTURER "Connaxio"
+#define USB_PRODUCT      "Espoir"
+#define USB_SERIAL       ""
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/crabik_slot_esp32_s3/pins_arduino.h b/variants/crabik_slot_esp32_s3/pins_arduino.h
new file mode 100644
index 00000000000..0f18a900877
--- /dev/null
+++ b/variants/crabik_slot_esp32_s3/pins_arduino.h
@@ -0,0 +1,80 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303a
+#define USB_PID          0x814D  // for user apps (https://github.com/espressif/usb-pids/pull/77)
+#define USB_MANUFACTURER "Crabik"
+#define USB_PRODUCT      "Slot ESP32-S3"
+#define USB_SERIAL       ""
+
+static const uint8_t LED_BUILTIN = 21;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t S1 = 1;
+static const uint8_t S2 = 12;
+static const uint8_t S3 = 2;
+static const uint8_t S4 = 11;
+static const uint8_t S5 = 17;
+static const uint8_t S6 = 18;
+static const uint8_t S7 = 3;
+static const uint8_t S8 = 4;
+static const uint8_t S9 = 5;
+static const uint8_t S10 = 6;
+static const uint8_t S11 = 7;
+static const uint8_t S12 = 8;
+static const uint8_t S13 = 9;
+static const uint8_t S14 = 10;
+static const uint8_t S15 = 45;
+static const uint8_t S16 = 46;
+static const uint8_t S17 = 48;
+static const uint8_t S18 = 47;
+static const uint8_t S19 = 33;
+static const uint8_t S20 = 34;
+
+static const uint8_t TX = S12;
+static const uint8_t RX = S11;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 13;
+static const uint8_t SCL = 14;
+static const uint8_t D = SDA;
+static const uint8_t C = SCL;
+
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+static const uint8_t DO = MOSI;
+static const uint8_t DI = MISO;
+static const uint8_t CLK = SCK;
+static const uint8_t CS1 = S5;
+static const uint8_t CS2 = S6;
+static const uint8_t SS = CS1;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+
+static const uint8_t USB_DN = 19;
+static const uint8_t USB_DP = 20;
+
+static const uint8_t BOOT_BTN = 0;
+static const uint8_t USER_LED = LED_BUILTIN;
+
+static const uint8_t EN_TROYKA = 15;
+
+static const uint8_t LIPO_ALERT = 16;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/cyobot_v2_esp32s3/pins_arduino.h b/variants/cyobot_v2_esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..45f0968ef2a
--- /dev/null
+++ b/variants/cyobot_v2_esp32s3/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_MANUFACTURER "CYOBot"
+#define USB_PRODUCT      "CYOBrain ESP32S3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t BUTTON0 = 4;
+static const uint8_t BUTTON1 = 38;
+static const uint8_t LED = 24;
+
+static const uint8_t BAT_MEAS = 6;
+static const uint8_t CHAR_DET = 23;
+
+static const uint8_t NEO_BASE = 7;
+static const uint8_t NEO_BRAIN = 15;
+
+static const uint8_t I2S0_MCLK = 16;
+static const uint8_t I2S0_DSDIN = 8;
+static const uint8_t I2S0_SCLK = 9;
+static const uint8_t I2S0_LRCK = 45;
+
+static const uint8_t SDA = 17;
+static const uint8_t SCL = 18;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 2;
+static const uint8_t MISO = 42;
+static const uint8_t SCK = 41;
+
+static const uint8_t ENCODER1_A = 39;
+static const uint8_t ENCODER1_B = 40;
+static const uint8_t ENCODER2_B = 19;
+static const uint8_t ENCODER2_A = 20;
+
+static const uint8_t UART1_RXD = 3;
+static const uint8_t UART1_TXD = 1;
+
+static const uint8_t GPIO46 = 46;
+static const uint8_t ESP_IO0 = 0;
+
+static const uint8_t SD_OUT = 10;
+static const uint8_t SD_SPI_MOSI = 11;
+static const uint8_t SD_SPI_CLK = 12;
+static const uint8_t SD_SPI_MISO = 13;
+static const uint8_t SD_SPI_CS = 14;
+
+static const uint8_t PA_CTRL = 25;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/cytron_maker_feather_aiot_s3/bootloader-tinyuf2.bin b/variants/cytron_maker_feather_aiot_s3/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..6e7ea8a275e
Binary files /dev/null and b/variants/cytron_maker_feather_aiot_s3/bootloader-tinyuf2.bin differ
diff --git a/variants/cytron_maker_feather_aiot_s3/partitions-8MB-tinyuf2.csv b/variants/cytron_maker_feather_aiot_s3/partitions-8MB-tinyuf2.csv
new file mode 100644
index 00000000000..4026378b6fb
--- /dev/null
+++ b/variants/cytron_maker_feather_aiot_s3/partitions-8MB-tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/variants/cytron_maker_feather_aiot_s3/pins_arduino.h b/variants/cytron_maker_feather_aiot_s3/pins_arduino.h
new file mode 100644
index 00000000000..9f7475294e8
--- /dev/null
+++ b/variants/cytron_maker_feather_aiot_s3/pins_arduino.h
@@ -0,0 +1,69 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x80F8
+#define USB_MANUFACTURER "Cytron"
+#define USB_PRODUCT      "Maker Feather AIoT S3"
+#define USB_SERIAL       ""
+
+static const uint8_t LED_BUILTIN = 2;                        // Status LED.
+#define BUILTIN_LED LED_BUILTIN                              // backward compatibility
+#define LED_BUILTIN LED_BUILTIN                              // allow testing #ifdef LED_BUILTIN
+static const uint8_t RGB_BUILTIN = SOC_GPIO_PIN_COUNT + 46;  // RGB LED.
+#define RGB_BUILTIN    RGB_BUILTIN                           // necessary to make digitalWrite/digitalMode find it
+#define RGB_BRIGHTNESS 64
+
+#define LED            LED_BUILTIN
+#define RGB            RGB_BUILTIN
+#define RGB_LED_PIN    RGB_BUILTIN
+#define RGB_BRIGHTNESS 65
+
+#define VP_EN  11  // V Peripheral Enable.
+#define BUZZER 12  // Piezo Buzzer.
+#define BOOT   0   // Boot Button.
+#define BUTTON 3   // User Button.
+
+#define VIN             13  // Vin Sense.
+#define VBATT           13
+#define VOLTAGE_MONITOR 13
+
+static const uint8_t TX = 15;
+static const uint8_t RX = 16;
+
+static const uint8_t SDA = 42;
+static const uint8_t SCL = 41;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 8;
+static const uint8_t SCK = 17;
+static const uint8_t MISO = 18;
+
+static const uint8_t A0 = 10;
+static const uint8_t A1 = 9;
+static const uint8_t A2 = 6;
+static const uint8_t A3 = 5;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 7;
+
+static const uint8_t A6 = 17;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 18;
+static const uint8_t A9 = 16;
+static const uint8_t A10 = 15;
+static const uint8_t A11 = 14;
+static const uint8_t A12 = 13;
+
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/cytron_maker_feather_aiot_s3/tinyuf2.bin b/variants/cytron_maker_feather_aiot_s3/tinyuf2.bin
new file mode 100644
index 00000000000..a43bff014da
Binary files /dev/null and b/variants/cytron_maker_feather_aiot_s3/tinyuf2.bin differ
diff --git a/variants/cytron_maker_feather_aiot_s3/variant.cpp b/variants/cytron_maker_feather_aiot_s3/variant.cpp
new file mode 100644
index 00000000000..9ac4da2732f
--- /dev/null
+++ b/variants/cytron_maker_feather_aiot_s3/variant.cpp
@@ -0,0 +1,36 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Wai Weng for Cytron Technologies
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // Turn on VPeripheral by default.
+  pinMode(VP_EN, OUTPUT);
+  digitalWrite(VP_EN, HIGH);
+}
+}
diff --git a/variants/d-duino-32/pins_arduino.h b/variants/d-duino-32/pins_arduino.h
index 19a1eb91a16..b14955417af 100644
--- a/variants/d-duino-32/pins_arduino.h
+++ b/variants/d-duino-32/pins_arduino.h
@@ -3,24 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 5;
 static const uint8_t SCL = 4;
 
-static const uint8_t SS    = 15;
-static const uint8_t MOSI  = 13;
-static const uint8_t MISO  = 12;
-static const uint8_t SCK   = 14;
+static const uint8_t SS = 15;
+static const uint8_t MOSI = 13;
+static const uint8_t MISO = 12;
+static const uint8_t SCK = 14;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/d1_mini32/pins_arduino.h b/variants/d1_mini32/pins_arduino.h
index 69982798610..826eff64104 100644
--- a/variants/d1_mini32/pins_arduino.h
+++ b/variants/d1_mini32/pins_arduino.h
@@ -5,30 +5,30 @@
 #include <../d32/d32_core.h>
 
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-static const uint8_t _VBAT = 35; // battery voltage
+#define BUILTIN_LED LED_BUILTIN   // backward compatibility
+#define LED_BUILTIN LED_BUILTIN   // allow testing #ifdef LED_BUILTIN
+static const uint8_t _VBAT = 35;  // battery voltage
 
-#define PIN_WIRE_SDA SDA // backward compatibility
-#define PIN_WIRE_SCL SCL // backward compatibility
+#define PIN_WIRE_SDA SDA  // backward compatibility
+#define PIN_WIRE_SCL SCL  // backward compatibility
 
-static const uint8_t D0   = 26;
-static const uint8_t D1   = 22;
-static const uint8_t D2   = 21;
-static const uint8_t D3   = 17;
-static const uint8_t D4   = 16;
-static const uint8_t D5   = 18;
-static const uint8_t D6   = 19;
-static const uint8_t D7   = 23;
-static const uint8_t D8   = 5;
-static const uint8_t RXD  = 3;
-static const uint8_t TXD  = 1;
+static const uint8_t D0 = 26;
+static const uint8_t D1 = 22;
+static const uint8_t D2 = 21;
+static const uint8_t D3 = 17;
+static const uint8_t D4 = 16;
+static const uint8_t D5 = 18;
+static const uint8_t D6 = 19;
+static const uint8_t D7 = 23;
+static const uint8_t D8 = 5;
+static const uint8_t RXD = 3;
+static const uint8_t TXD = 1;
 
-#define PIN_SPI_SS   SS   // backward compatibility
-#define PIN_SPI_MOSI MOSI // backward compatibility
-#define PIN_SPI_MISO MISO // backward compatibility
-#define PIN_SPI_SCK  SCK  // backward compatibility
+#define PIN_SPI_SS   SS    // backward compatibility
+#define PIN_SPI_MOSI MOSI  // backward compatibility
+#define PIN_SPI_MISO MISO  // backward compatibility
+#define PIN_SPI_SCK  SCK   // backward compatibility
 
-#define PIN_A0 A0 // backward compatibility
+#define PIN_A0 A0  // backward compatibility
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/d1_uno32/pins_arduino.h b/variants/d1_uno32/pins_arduino.h
new file mode 100644
index 00000000000..7eefc21a8c4
--- /dev/null
+++ b/variants/d1_uno32/pins_arduino.h
@@ -0,0 +1,55 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+// Board Pinmap: https://www.botnroll.com/en/esp/3639-wemos-d1-r32-w-esp32-uno-r3-pinout.html
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 2;
+static const uint8_t A1 = 4;
+static const uint8_t A2 = 35;
+static const uint8_t A3 = 34;
+static const uint8_t A4 = 36;
+static const uint8_t A5 = 39;
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+#define PIN_WIRE_SDA SDA  // backward compatibility
+#define PIN_WIRE_SCL SCL  // backward compatibility
+
+static const uint8_t D0 = 3;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 26;
+static const uint8_t D3 = 25;
+static const uint8_t D4 = 17;
+static const uint8_t D5 = 16;
+static const uint8_t D6 = 27;
+static const uint8_t D7 = 14;
+static const uint8_t D8 = 12;
+static const uint8_t D9 = 13;
+static const uint8_t D10 = 5;
+static const uint8_t D11 = 23;
+static const uint8_t D12 = 19;
+static const uint8_t D13 = 18;
+
+#define PIN_SPI_SS   SS    // backward compatibility
+#define PIN_SPI_MOSI MOSI  // backward compatibility
+#define PIN_SPI_MISO MISO  // backward compatibility
+#define PIN_SPI_SCK  SCK   // backward compatibility
+
+#define PIN_A0 A0  // backward compatibility
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/d32/d32_core.h b/variants/d32/d32_core.h
index 787d08c2006..3d637594602 100644
--- a/variants/d32/d32_core.h
+++ b/variants/d32/d32_core.h
@@ -1,24 +1,16 @@
 #ifndef _D32_CORE_H_
 #define _D32_CORE_H_
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -51,4 +43,4 @@ static const uint8_t T9 = 32;
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
 
-#endif
\ No newline at end of file
+#endif
diff --git a/variants/d32/pins_arduino.h b/variants/d32/pins_arduino.h
index 810eeae6de2..d5346c38acc 100644
--- a/variants/d32/pins_arduino.h
+++ b/variants/d32/pins_arduino.h
@@ -5,8 +5,8 @@
 #include <d32_core.h>
 
 static const uint8_t LED_BUILTIN = 5;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-static const uint8_t _VBAT = 35; // battery voltage
+#define BUILTIN_LED LED_BUILTIN   // backward compatibility
+#define LED_BUILTIN LED_BUILTIN   // allow testing #ifdef LED_BUILTIN
+static const uint8_t _VBAT = 35;  // battery voltage
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/d32_pro/pins_arduino.h b/variants/d32_pro/pins_arduino.h
index f19efb977ba..fd3c899ef11 100644
--- a/variants/d32_pro/pins_arduino.h
+++ b/variants/d32_pro/pins_arduino.h
@@ -5,18 +5,18 @@
 #include <../d32/d32_core.h>
 
 static const uint8_t LED_BUILTIN = 5;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-static const uint8_t _VBAT = 35; // battery voltage
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
+static const uint8_t _VBAT = 35;  // battery voltage
 
-#define TF_CS   4  // TF (Micro SD Card) CS pin
-#define TS_CS   12 // Touch Screen CS pin
-#define TFT_CS  14 // TFT CS pin
-#define TFT_LED 32 // TFT backlight control pin
-#define TFT_RST 33 // TFT reset pin
-#define TFT_DC  27 // TFT DC pin
+#define TF_CS   4   // TF (Micro SD Card) CS pin
+#define TS_CS   12  // Touch Screen CS pin
+#define TFT_CS  14  // TFT CS pin
+#define TFT_LED 32  // TFT backlight control pin
+#define TFT_RST 33  // TFT reset pin
+#define TFT_DC  27  // TFT DC pin
 
-#define SS      TF_CS
+#define SS TF_CS
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/deneyapkart/pins_arduino.h b/variants/deneyapkart/pins_arduino.h
new file mode 100644
index 00000000000..c03f1ebdec0
--- /dev/null
+++ b/variants/deneyapkart/pins_arduino.h
@@ -0,0 +1,89 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 4;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+#define LEDB        LED_BUILTIN
+#define LEDR        3
+#define LEDG        1
+
+static const uint8_t GPKEY = 0;
+#define KEY_BUILTIN GPKEY
+#define BUILTIN_KEY GPKEY
+#define BOOT        GPKEY
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 15;
+
+static const uint8_t SS = 21;
+static const uint8_t MOSI = 5;
+static const uint8_t MISO = 18;
+static const uint8_t SCK = 19;
+
+static const uint8_t A0 = 36;
+static const uint8_t A1 = 39;
+static const uint8_t A2 = 34;
+static const uint8_t A3 = 35;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+
+static const uint8_t T0 = 32;
+static const uint8_t T1 = 33;
+static const uint8_t T2 = 27;
+static const uint8_t T3 = 14;
+static const uint8_t T4 = 12;
+static const uint8_t T5 = 13;
+
+static const uint8_t D0 = 23;
+static const uint8_t D1 = 22;
+static const uint8_t D2 = 1;
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 21;
+static const uint8_t D5 = 19;
+static const uint8_t D6 = 18;
+static const uint8_t D7 = 5;
+static const uint8_t D8 = 0;
+static const uint8_t D9 = 2;
+static const uint8_t D10 = 4;
+static const uint8_t D11 = 15;
+static const uint8_t D12 = 13;
+static const uint8_t D13 = 12;
+static const uint8_t D14 = 14;
+static const uint8_t D15 = 27;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t PWM0 = 23;
+static const uint8_t PWM1 = 22;
+
+static const uint8_t CAMSD = 33;
+static const uint8_t CAMSC = 25;
+static const uint8_t CAMD2 = 19;
+static const uint8_t CAMD3 = 22;
+static const uint8_t CAMD4 = 23;
+static const uint8_t CAMD5 = 21;
+static const uint8_t CAMD6 = 18;
+static const uint8_t CAMD7 = 26;
+static const uint8_t CAMD8 = 35;
+static const uint8_t CAMD9 = 34;
+static const uint8_t CAMPC = 5;
+static const uint8_t CAMXC = 32;
+static const uint8_t CAMH = 39;
+static const uint8_t CAMV = 36;
+
+static const uint8_t MICD = 12;
+static const uint8_t MICC = 13;
+
+static const uint8_t IMUSD = 4;
+static const uint8_t IMUSC = 15;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/deneyapkart1A/pins_arduino.h b/variants/deneyapkart1A/pins_arduino.h
new file mode 100644
index 00000000000..b1f0c3f57b8
--- /dev/null
+++ b/variants/deneyapkart1A/pins_arduino.h
@@ -0,0 +1,89 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 13;  //D12
+#define BUILTIN_LED    LED_BUILTIN                           // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN                           // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGBLED         LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t GPKEY = 0;
+#define KEY_BUILTIN GPKEY
+#define BUILTIN_KEY GPKEY
+#define BOOT        GPKEY
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 15;
+
+static const uint8_t SS = 21;
+static const uint8_t MOSI = 5;
+static const uint8_t MISO = 18;
+static const uint8_t SCK = 19;
+
+static const uint8_t A0 = 36;
+static const uint8_t A1 = 39;
+static const uint8_t A2 = 34;
+static const uint8_t A3 = 35;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+
+static const uint8_t T0 = 32;
+static const uint8_t T1 = 33;
+static const uint8_t T2 = 27;
+static const uint8_t T3 = 14;
+static const uint8_t T4 = 12;
+static const uint8_t T5 = 13;
+
+static const uint8_t D0 = 23;
+static const uint8_t D1 = 22;
+static const uint8_t D2 = 1;
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 21;
+static const uint8_t D5 = 19;
+static const uint8_t D6 = 18;
+static const uint8_t D7 = 5;
+static const uint8_t D8 = 0;
+static const uint8_t D9 = 2;
+static const uint8_t D10 = 4;
+static const uint8_t D11 = 15;
+static const uint8_t D12 = 13;
+static const uint8_t D13 = 12;
+static const uint8_t D14 = 14;
+static const uint8_t D15 = 27;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t PWM0 = 23;
+static const uint8_t PWM1 = 22;
+
+static const uint8_t CAMSD = 33;
+static const uint8_t CAMSC = 25;
+static const uint8_t CAMD2 = 19;
+static const uint8_t CAMD3 = 22;
+static const uint8_t CAMD4 = 23;
+static const uint8_t CAMD5 = 21;
+static const uint8_t CAMD6 = 18;
+static const uint8_t CAMD7 = 26;
+static const uint8_t CAMD8 = 35;
+static const uint8_t CAMD9 = 34;
+static const uint8_t CAMPC = 5;
+static const uint8_t CAMXC = 32;
+static const uint8_t CAMH = 39;
+static const uint8_t CAMV = 36;
+
+static const uint8_t SDMI = 2;
+static const uint8_t SDMO = 14;
+static const uint8_t SDCS = 12;
+static const uint8_t SDCK = 27;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/deneyapkart1Av2/pins_arduino.h b/variants/deneyapkart1Av2/pins_arduino.h
new file mode 100644
index 00000000000..141367aa4c4
--- /dev/null
+++ b/variants/deneyapkart1Av2/pins_arduino.h
@@ -0,0 +1,106 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x8147
+#define USB_MANUFACTURER "Turkish Technology Team Foundation (T3)"
+#define USB_PRODUCT      "DENEYAP KART 1A v2"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48;  //D9
+#define BUILTIN_LED    LED_BUILTIN                           // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN                           // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGBLED         LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t GPKEY = 0;
+#define KEY_BUILTIN GPKEY
+#define BUILTIN_KEY GPKEY
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 47;
+static const uint8_t SCL = 21;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 39;
+static const uint8_t MISO = 40;
+static const uint8_t SCK = 41;
+
+static const uint8_t A0 = 4;
+static const uint8_t A1 = 5;
+static const uint8_t A2 = 6;
+static const uint8_t A3 = 7;
+static const uint8_t A4 = 15;
+static const uint8_t A5 = 16;
+static const uint8_t A6 = 17;
+static const uint8_t A7 = 18;
+static const uint8_t A8 = 9;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 5;
+static const uint8_t T2 = 6;
+static const uint8_t T3 = 7;
+static const uint8_t T4 = 8;
+static const uint8_t T5 = 3;
+static const uint8_t T6 = 10;
+static const uint8_t T7 = 1;
+static const uint8_t T8 = 2;
+
+static const uint8_t D0 = 1;
+static const uint8_t D1 = 2;
+static const uint8_t D2 = 43;
+static const uint8_t D3 = 44;
+static const uint8_t D4 = 42;
+static const uint8_t D5 = 41;
+static const uint8_t D6 = 40;
+static const uint8_t D7 = 39;
+static const uint8_t D8 = 38;
+static const uint8_t D9 = 48;
+static const uint8_t D10 = 47;
+static const uint8_t D11 = 21;
+static const uint8_t D12 = 10;
+static const uint8_t D13 = 3;
+static const uint8_t D14 = 8;
+static const uint8_t D15 = 0;
+static const uint8_t D16 = 13;
+static const uint8_t D17 = 12;
+static const uint8_t D18 = 11;
+static const uint8_t D19 = 14;
+
+static const uint8_t PWM0 = 15;
+static const uint8_t PWM1 = 16;
+static const uint8_t PWM2 = 17;
+static const uint8_t PWM3 = 18;
+static const uint8_t PWM4 = 38;
+
+static const uint8_t CAMSD = 4;
+static const uint8_t CAMSC = 5;
+static const uint8_t CAMD2 = 41;
+static const uint8_t CAMD3 = 2;
+static const uint8_t CAMD4 = 1;
+static const uint8_t CAMD5 = 42;
+static const uint8_t CAMD6 = 40;
+static const uint8_t CAMD7 = 38;
+static const uint8_t CAMD8 = 17;
+static const uint8_t CAMD9 = 15;
+static const uint8_t CAMPC = 39;
+static const uint8_t CAMXC = 16;
+static const uint8_t CAMH = 7;
+static const uint8_t CAMV = 6;
+
+static const uint8_t SDMI = 14;
+static const uint8_t SDMO = 12;
+static const uint8_t SDCS = 11;
+static const uint8_t SDCK = 13;
+
+static const uint8_t BAT = 9;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/deneyapkartg/pins_arduino.h b/variants/deneyapkartg/pins_arduino.h
new file mode 100644
index 00000000000..f9d9048976e
--- /dev/null
+++ b/variants/deneyapkartg/pins_arduino.h
@@ -0,0 +1,57 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x814A
+#define USB_MANUFACTURER "Turkish Technology Team Foundation (T3)"
+#define USB_PRODUCT      "DENEYAP KART G"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 10;  //D3
+#define BUILTIN_LED    LED_BUILTIN                           // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN                           // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGBLED         LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t GPKEY = 9;
+#define KEY_BUILTIN GPKEY
+#define BUILTIN_KEY GPKEY
+#define BT          GPKEY
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 2;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+
+static const uint8_t D0 = 20;
+static const uint8_t D1 = 21;
+static const uint8_t D2 = 9;
+static const uint8_t D3 = 10;
+static const uint8_t D4 = 8;
+static const uint8_t D5 = 7;
+static const uint8_t D6 = 2;
+
+static const uint8_t PWM0 = 0;
+static const uint8_t PWM1 = 1;
+static const uint8_t PWM2 = 3;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/deneyapmini/pins_arduino.h b/variants/deneyapmini/pins_arduino.h
new file mode 100644
index 00000000000..ee6ec693a81
--- /dev/null
+++ b/variants/deneyapmini/pins_arduino.h
@@ -0,0 +1,88 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303A
+#define USB_PID          0x8141
+#define USB_MANUFACTURER "Turkish Technology Team Foundation (T3)"
+#define USB_PRODUCT      "DENEYAP MINI"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t LED_BUILTIN = 35;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+#define LEDB        LED_BUILTIN
+#define LEDR        34
+#define LEDG        33
+
+static const uint8_t GPKEY = 0;
+#define KEY_BUILTIN GPKEY
+#define BUILTIN_KEY GPKEY
+#define BT          GPKEY
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 36;
+static const uint8_t SCL = 37;
+
+static const uint8_t SS = 21;
+static const uint8_t MOSI = 40;
+static const uint8_t MISO = 39;
+static const uint8_t SCK = 38;
+
+static const uint8_t A0 = 8;
+static const uint8_t A1 = 9;
+static const uint8_t A2 = 10;
+static const uint8_t A3 = 11;
+static const uint8_t A4 = 12;
+static const uint8_t A5 = 13;
+static const uint8_t A6 = 16;
+
+static const uint8_t T0 = 8;
+static const uint8_t T1 = 9;
+static const uint8_t T2 = 10;
+static const uint8_t T3 = 11;
+static const uint8_t T4 = 12;
+static const uint8_t T5 = 13;
+
+static const uint8_t D0 = 44;
+static const uint8_t D1 = 43;
+static const uint8_t D2 = 42;
+static const uint8_t D3 = 41;
+static const uint8_t D4 = 40;
+static const uint8_t D5 = 39;
+static const uint8_t D6 = 38;
+static const uint8_t D7 = 37;
+static const uint8_t D8 = 36;
+static const uint8_t D9 = 26;
+static const uint8_t D10 = 21;
+static const uint8_t D11 = 18;
+static const uint8_t D12 = 17;
+static const uint8_t D13 = 0;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 33;
+static const uint8_t D16 = 34;
+
+static const uint8_t PWM0 = 42;
+static const uint8_t PWM1 = 41;
+
+static const uint8_t DAC0 = 17;
+static const uint8_t DAC1 = 18;
+
+/*
+#define SD SDA
+#define SC SCL
+
+#define MO MOSI
+#define MI MISO
+#define MC SCK
+
+#define DA0 DAC0
+#define DA1 DAC1
+*/
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/deneyapminiv2/pins_arduino.h b/variants/deneyapminiv2/pins_arduino.h
new file mode 100644
index 00000000000..009ca10abb1
--- /dev/null
+++ b/variants/deneyapminiv2/pins_arduino.h
@@ -0,0 +1,88 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x8144
+#define USB_MANUFACTURER "Turkish Technology Team Foundation (T3)"
+#define USB_PRODUCT      "DENEYAP MINI v2"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 33;  //D14
+#define BUILTIN_LED    LED_BUILTIN                           // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN                           // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGBLED         LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t GPKEY = 0;
+#define KEY_BUILTIN GPKEY
+#define BUILTIN_KEY GPKEY
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 36;
+static const uint8_t SCL = 37;
+
+static const uint8_t SS = 21;
+static const uint8_t MOSI = 40;
+static const uint8_t MISO = 39;
+static const uint8_t SCK = 38;
+
+static const uint8_t A0 = 7;
+static const uint8_t A1 = 8;
+static const uint8_t A2 = 9;
+static const uint8_t A3 = 10;
+static const uint8_t A4 = 11;
+static const uint8_t A5 = 12;
+static const uint8_t A6 = 13;
+static const uint8_t A7 = 16;
+
+static const uint8_t T0 = 7;
+static const uint8_t T1 = 8;
+static const uint8_t T2 = 9;
+static const uint8_t T3 = 10;
+static const uint8_t T4 = 11;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 13;
+
+static const uint8_t D0 = 44;
+static const uint8_t D1 = 43;
+static const uint8_t D2 = 42;
+static const uint8_t D3 = 41;
+static const uint8_t D4 = 40;
+static const uint8_t D5 = 39;
+static const uint8_t D6 = 38;
+static const uint8_t D7 = 37;
+static const uint8_t D8 = 36;
+static const uint8_t D9 = 26;
+static const uint8_t D10 = 21;
+static const uint8_t D11 = 18;
+static const uint8_t D12 = 17;
+static const uint8_t D13 = 0;
+static const uint8_t D14 = 33;
+
+static const uint8_t PWM0 = 42;
+static const uint8_t PWM1 = 41;
+
+static const uint8_t DAC0 = 17;
+static const uint8_t DAC1 = 18;
+
+/*
+#define SD SDA
+#define SC SCL
+
+#define MO MOSI
+#define MI MISO
+#define MC SCK
+
+#define DA0 DAC0
+#define DA1 DAC1
+*/
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/department_of_alchemy_minimain_esp32s2/bootloader-tinyuf2.bin b/variants/department_of_alchemy_minimain_esp32s2/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..59fe0a4b196
Binary files /dev/null and b/variants/department_of_alchemy_minimain_esp32s2/bootloader-tinyuf2.bin differ
diff --git a/variants/department_of_alchemy_minimain_esp32s2/partitions-4MB-tinyuf2.csv b/variants/department_of_alchemy_minimain_esp32s2/partitions-4MB-tinyuf2.csv
new file mode 100644
index 00000000000..164ba0d5965
--- /dev/null
+++ b/variants/department_of_alchemy_minimain_esp32s2/partitions-4MB-tinyuf2.csv
@@ -0,0 +1,11 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,          0x8000, 4K
+
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  1408K,
+ota_1,    0,    ota_1,  0x170000,  1408K,
+uf2,      app,  factory,0x2d0000,  256K,
+ffat,     data, fat,    0x310000,  960K,
diff --git a/variants/department_of_alchemy_minimain_esp32s2/pins_arduino.h b/variants/department_of_alchemy_minimain_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..7f053b3f600
--- /dev/null
+++ b/variants/department_of_alchemy_minimain_esp32s2/pins_arduino.h
@@ -0,0 +1,63 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303a
+#define USB_PID          0x80FF
+#define USB_MANUFACTURER "Department of Alchemy"
+#define USB_PRODUCT      "MiniMain ESP32-S2"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+// RGB LED
+#define PIN_RGB_LED 33
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWritee() for blinking
+#define RGB_BUILTIN    (PIN_RGB_LED + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+#define RGBLED_NUM         1     // number of RGB LEDs
+#define RGBLED_POWER       21    // power pin
+#define RGBLED_POWER_ON    HIGH  // power pin state when on
+#define PIN_SERVO          2     // servo pin
+#define PIN_ISOLATED_INPUT 40    // optocoupled input
+
+static const uint8_t SDA = 3;
+static const uint8_t SCL = 4;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 18;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 16;
+static const uint8_t A3 = 15;
+static const uint8_t A4 = 14;
+static const uint8_t A5 = 8;
+
+static const uint8_t TX = 39;
+static const uint8_t RX = 38;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t T2 = 2;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/department_of_alchemy_minimain_esp32s2/tinyuf2.bin b/variants/department_of_alchemy_minimain_esp32s2/tinyuf2.bin
new file mode 100644
index 00000000000..5ab2d2d4921
Binary files /dev/null and b/variants/department_of_alchemy_minimain_esp32s2/tinyuf2.bin differ
diff --git a/variants/department_of_alchemy_minimain_esp32s2/variant.cpp b/variants/department_of_alchemy_minimain_esp32s2/variant.cpp
new file mode 100644
index 00000000000..ee4eaa8df2b
--- /dev/null
+++ b/variants/department_of_alchemy_minimain_esp32s2/variant.cpp
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // This board has a power control pin, and we must set it to output and high
+  // in order to enable the RGB LEDs.
+  pinMode(RGBLED_POWER, OUTPUT);
+  digitalWrite(RGBLED_POWER, HIGH);
+}
+}
diff --git a/variants/dfrobot_beetle_esp32c3/pins_arduino.h b/variants/dfrobot_beetle_esp32c3/pins_arduino.h
new file mode 100644
index 00000000000..49fd71e938c
--- /dev/null
+++ b/variants/dfrobot_beetle_esp32c3/pins_arduino.h
@@ -0,0 +1,51 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x3343
+#define USB_PID          0x8364
+#define USB_MANUFACTURER "DFRobot"
+#define USB_PRODUCT      "Beetle ESP32-C3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t LED_BUILTIN = 10;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#define GDI_DISPLAY_FPC_INTERFACE
+#ifdef GDI_DISPLAY_FPC_INTERFACE
+
+#define GDI_BLK      LED_BUILTIN
+#define GDI_SPI_SCLK SCK
+#define GDI_SPI_MOSI MOSI
+#define GDI_SPI_MISO MISO
+#define GDI_DC       A1
+#define GDI_RES      A2
+#define GDI_CS       SS
+#define GDI_SDCS     A0
+#define GDI_TCS      A3
+#define GDI_SCL      SCL
+#define GDI_SDA      SDA
+
+#endif
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/dfrobot_beetle_esp32c6/pins_arduino.h b/variants/dfrobot_beetle_esp32c6/pins_arduino.h
new file mode 100644
index 00000000000..fb3c1a703e2
--- /dev/null
+++ b/variants/dfrobot_beetle_esp32c6/pins_arduino.h
@@ -0,0 +1,22 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t LED_BUILTIN = 15;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 19;
+static const uint8_t SCL = 20;
+
+static const uint8_t SS = 4;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 21;
+static const uint8_t SCK = 23;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/dfrobot_firebeetle2_esp32c6/pins_arduino.h b/variants/dfrobot_firebeetle2_esp32c6/pins_arduino.h
new file mode 100644
index 00000000000..57f7b605c56
--- /dev/null
+++ b/variants/dfrobot_firebeetle2_esp32c6/pins_arduino.h
@@ -0,0 +1,56 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t LED_BUILTIN = 15;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 19;
+static const uint8_t SCL = 20;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 21;
+static const uint8_t SCK = 23;
+
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+
+static const uint8_t D2 = 8;
+static const uint8_t D3 = 14;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 18;
+static const uint8_t D9 = 9;
+static const uint8_t D11 = 7;
+static const uint8_t D12 = 6;
+static const uint8_t D13 = 15;
+
+#define GDI_DISPLAY_FPC_INTERFACE
+#ifdef GDI_DISPLAY_FPC_INTERFACE
+
+#define GDI_BLK      D13
+#define GDI_SPI_SCLK SCK
+#define GDI_SPI_MOSI MOSI
+#define GDI_SPI_MISO MISO
+#define GDI_DC       D2
+#define GDI_RES      D3
+#define GDI_CS       D6  //LCD_CS
+#define GDI_SDCS     D7
+#define GDI_FCS      -1
+#define GDI_TCS      D12
+#define GDI_SCL      SCL
+#define GDI_SDA      SDA
+#define GDI_INT      D11
+#define GDI_BUSY_TE  -1
+
+#endif
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/dfrobot_firebeetle2_esp32e/pins_arduino.h b/variants/dfrobot_firebeetle2_esp32e/pins_arduino.h
new file mode 100644
index 00000000000..3048c5f6a12
--- /dev/null
+++ b/variants/dfrobot_firebeetle2_esp32e/pins_arduino.h
@@ -0,0 +1,70 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+typedef unsigned char uint8_t;
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+static const uint8_t TX2 = 17;
+static const uint8_t RX2 = 16;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t D0 = 3;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 25;
+static const uint8_t D3 = 26;
+static const uint8_t D4 = 27;
+static const uint8_t D5 = 0;
+static const uint8_t D6 = 14;
+static const uint8_t D7 = 13;
+static const uint8_t D8 = 5;
+static const uint8_t D9 = 2;
+static const uint8_t D10 = 17;
+static const uint8_t D11 = 16;
+static const uint8_t D12 = 4;
+static const uint8_t D13 = 12;
+
+static const uint8_t A0 = 36;
+static const uint8_t A1 = 39;
+static const uint8_t A2 = 34;
+static const uint8_t A3 = 35;
+static const uint8_t A4 = 15;
+static const uint8_t A5 = 35;
+static const uint8_t A6 = 4;
+static const uint8_t A7 = 0;
+static const uint8_t A8 = 2;
+static const uint8_t A9 = 13;
+static const uint8_t A10 = 12;
+static const uint8_t A11 = 14;
+static const uint8_t A12 = 27;
+static const uint8_t A13 = 25;
+static const uint8_t A14 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/dfrobot_firebeetle2_esp32s3/pins_arduino.h b/variants/dfrobot_firebeetle2_esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..76a2e9a29d4
--- /dev/null
+++ b/variants/dfrobot_firebeetle2_esp32s3/pins_arduino.h
@@ -0,0 +1,81 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x3343
+#define USB_PID          0x83CF
+#define USB_MANUFACTURER "DFRobot"
+#define USB_PRODUCT      "FireBeetle 2 ESP32-S3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 1;
+static const uint8_t SCL = 2;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 15;
+static const uint8_t MISO = 16;
+static const uint8_t SCK = 17;
+
+static const uint8_t A0 = 4;
+static const uint8_t A1 = 5;
+static const uint8_t A2 = 6;
+static const uint8_t A3 = 8;
+static const uint8_t A4 = 10;
+static const uint8_t A5 = 11;
+
+static const uint8_t D2 = 3;
+static const uint8_t D3 = 38;
+static const uint8_t D5 = 7;
+static const uint8_t D6 = 18;
+static const uint8_t D7 = 9;
+static const uint8_t D9 = 0;
+static const uint8_t D10 = 14;
+static const uint8_t D11 = 13;
+static const uint8_t D12 = 12;
+static const uint8_t D13 = 21;
+static const uint8_t D14 = 47;
+
+static const uint8_t LED_BUILTIN = D13;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#define GDI_DISPLAY_FPC_INTERFACE
+#ifdef GDI_DISPLAY_FPC_INTERFACE
+
+#define GDI_BLK      21
+#define GDI_SPI_SCLK SCK
+#define GDI_SPI_MOSI MOSI
+#define GDI_SPI_MISO MISO
+#define GDI_DC       3
+#define GDI_RES      38
+#define GDI_CS       18
+#define GDI_SDCS     9
+#define GDI_FCS      7
+#define GDI_TCS      12
+#define GDI_SCL      SCL
+#define GDI_SDA      SDA
+#define GDI_INT      13
+#define GDI_BUSY_TE  14
+
+#endif
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/dfrobot_romeo_esp32s3/pins_arduino.h b/variants/dfrobot_romeo_esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..3eb3f56d48d
--- /dev/null
+++ b/variants/dfrobot_romeo_esp32s3/pins_arduino.h
@@ -0,0 +1,73 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 1;
+static const uint8_t SCL = 2;
+
+static const uint8_t MOSI = 15;
+static const uint8_t MISO = 16;
+static const uint8_t SCK = 17;
+static const uint8_t SS = 18;
+
+#define GDI_DISPLAY_FPC_INTERFACE
+#ifdef GDI_DISPLAY_FPC_INTERFACE
+
+#define GDI_BLK      21
+#define GDI_SPI_SCLK SCK
+#define GDI_SPI_MOSI MOSI
+#define GDI_SPI_MISO MISO
+#define GDI_DC       3
+#define GDI_RES      38
+#define GDI_CS       18
+#define GDI_SDCS     0
+#define GDI_FCS      7
+#define GDI_TCS      12
+#define GDI_SCL      SCL
+#define GDI_SDA      SDA
+#define GDI_INT      13
+#define GDI_BUSY_TE  14
+
+#endif /* GDI_DISPLAY_FPC_INTERFACE */
+
+// CAM
+#define CAM_DVP_INTERFACE
+#ifdef CAM_DVP_INTERFACE
+
+#define CAM_D5    4
+#define CAM_PCLK  5
+#define CAM_VSYNC 6
+#define CAM_D6    7
+#define CAM_D7    8
+#define CAM_D8    46
+#define CAM_D9    48
+#define CAM_XMCLK 45
+#define CAM_D2    39
+#define CAM_D3    40
+#define CAM_D4    41
+#define CAM_HREF  42
+#define CAM_SCL   SCL
+#define CAM_SDA   SDA
+
+#endif /* CAM_DVP_INTERFACE */
+
+// Motor
+#define MOTOR_INTERFACE
+#ifdef MOTOR_INTERFACE
+
+#define M1_EN 12
+#define M1_PH 13
+#define M2_EN 14
+#define M2_PH 21
+#define M3_EN 9
+#define M3_PH 10
+#define M4_EN 47
+#define M4_PH 11
+
+#endif
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/doitESP32devkitV1/pins_arduino.h b/variants/doitESP32devkitV1/pins_arduino.h
index 44aff01baf9..8e1d00416d1 100644
--- a/variants/doitESP32devkitV1/pins_arduino.h
+++ b/variants/doitESP32devkitV1/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -21,10 +13,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/doitESPduino32/pins_Arduino.h b/variants/doitESPduino32/pins_Arduino.h
deleted file mode 100644
index 6fd9d57a5ca..00000000000
--- a/variants/doitESPduino32/pins_Arduino.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-
-
-static const uint8_t SDA = 21;
-static const uint8_t SCL = 22;
-
-//SPI
-static const uint8_t IO5    = 5; //SS
-static const uint8_t IO23  = 23; //MOSI
-static const uint8_t IO19  = 19; //MISO
-static const uint8_t IO18   = 18; //SCK
-
-//ANALOG
-static const uint8_t IO36 = 36;
-static const uint8_t IO39 = 39;
-static const uint8_t IO4 = 4;
-static const uint8_t IO2 = 2;
-static const uint8_t IO35 = 35;
-//ANALOG+
-static const uint8_t IO15 = 15;
-static const uint8_t IO33 = 33;
-static const uint8_t IO32 = 32;
-static const uint8_t IO0 = 0;
-
-//DIGITAL
-static const uint8_t IO13 = 13;
-static const uint8_t IO12 = 12;
-static const uint8_t IO14 = 14;
-static const uint8_t IO27 = 27;
-static const uint8_t IO16 = 16;
-static const uint8_t IO17 = 17;
-static const uint8_t IO25 = 25;
-static const uint8_t IO26 = 26;
-static const uint8_t TX0 = 1;
-static const uint8_t RX0 = 3;
-//TFlash(uSD)
-static const uint8_t SD2 = 9;
-static const uint8_t SD3 = 10;
-static const uint8_t CMD = 11;
-static const uint8_t CLK = 6;
-static const uint8_t SD0 = 7;
-static const uint8_t SD1 = 8;
-
-// ESP-WROOM-32 does not have GPIO 14, 20(NC), 24, 28, 29, 30, 31, 36, 37, 38, 40+
-// All pins should be PWM capable. The board is a clone of WeMos D1 R32.
-
-#endif /* Pins_Arduino_h */
diff --git a/variants/doitESPduino32/pins_arduino.h b/variants/doitESPduino32/pins_arduino.h
new file mode 100644
index 00000000000..ff6f071229a
--- /dev/null
+++ b/variants/doitESPduino32/pins_arduino.h
@@ -0,0 +1,94 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+//SPI
+static const uint8_t IO5 = 5;    //SS
+static const uint8_t IO23 = 23;  //MOSI
+static const uint8_t IO19 = 19;  //MISO
+static const uint8_t IO18 = 18;  //SCK
+
+static const uint8_t SS = IO5;
+static const uint8_t MOSI = IO23;
+static const uint8_t MISO = IO19;
+static const uint8_t SCK = IO18;
+
+//ANALOG
+static const uint8_t IO36 = 36;
+static const uint8_t IO39 = 39;
+static const uint8_t IO4 = 4;
+static const uint8_t IO2 = 2;
+static const uint8_t IO35 = 35;
+//ANALOG+
+static const uint8_t IO15 = 15;
+static const uint8_t IO33 = 33;
+static const uint8_t IO32 = 32;
+static const uint8_t IO0 = 0;
+
+//DIGITAL
+static const uint8_t IO13 = 13;
+static const uint8_t IO12 = 12;
+static const uint8_t IO14 = 14;
+static const uint8_t IO27 = 27;
+static const uint8_t IO16 = 16;
+static const uint8_t IO17 = 17;
+static const uint8_t IO25 = 25;
+static const uint8_t IO26 = 26;
+static const uint8_t TX0 = 1;
+static const uint8_t RX0 = 3;
+//TFlash(uSD)
+static const uint8_t SD2 = 9;
+static const uint8_t SD3 = 10;
+static const uint8_t CMD = 11;
+static const uint8_t CLK = 6;
+static const uint8_t SD0 = 7;
+static const uint8_t SD1 = 8;
+
+//Arduino Uno backward compatibility
+static const uint8_t A0 = 2;
+static const uint8_t A1 = 4;
+static const uint8_t A2 = 35;
+static const uint8_t A3 = 34;
+static const uint8_t A4 = 36;
+static const uint8_t A5 = 39;
+
+static const uint8_t D0 = 3;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 26;
+static const uint8_t D3 = 25;
+static const uint8_t D4 = 17;
+static const uint8_t D5 = 16;
+static const uint8_t D6 = 27;
+static const uint8_t D7 = 14;
+static const uint8_t D8 = 12;
+static const uint8_t D9 = 13;
+static const uint8_t D10 = 5;
+static const uint8_t D11 = 23;
+static const uint8_t D12 = 19;
+static const uint8_t D13 = 18;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+#define PIN_WIRE_SDA SDA  // backward compatibility
+#define PIN_WIRE_SCL SCL  // backward compatibility
+
+#define PIN_SPI_SS   SS    // backward compatibility
+#define PIN_SPI_MOSI MOSI  // backward compatibility
+#define PIN_SPI_MISO MISO  // backward compatibility
+#define PIN_SPI_SCK  SCK   // backward compatibility
+
+#define PIN_A0 A0  // backward compatibility
+
+// ESP-WROOM-32 does not have GPIO 14, 20(NC), 24, 28, 29, 30, 31, 36, 37, 38, 40+
+// All pins should be PWM capable. The board is a clone of WeMos D1 R32.
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/dpu_esp32/pins_arduino.h b/variants/dpu_esp32/pins_arduino.h
new file mode 100644
index 00000000000..adc8ebd8b43
--- /dev/null
+++ b/variants/dpu_esp32/pins_arduino.h
@@ -0,0 +1,56 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 5;
+
+static const uint8_t MOSI = 13;
+static const uint8_t MISO = 12;
+static const uint8_t SCK = 14;
+static const uint8_t SS = 15;
+
+static const uint8_t TP_RST = 21;
+static const uint8_t TP_INT = 19;
+static const uint8_t TFT_BL = 18;
+static const uint8_t TFT_CS = 15;
+static const uint8_t TFT_DC = 27;
+static const uint8_t TFT_RST = 32;
+static const uint8_t SD_CS = 23;
+static const uint8_t SD_CD = 22;
+#endif /* Pins_Arduino_h */
diff --git a/variants/elecrow_crowpanel_7/pins_arduino.h b/variants/elecrow_crowpanel_7/pins_arduino.h
new file mode 100644
index 00000000000..6b55d35defd
--- /dev/null
+++ b/variants/elecrow_crowpanel_7/pins_arduino.h
@@ -0,0 +1,65 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x1a86
+#define USB_PID 0x7523
+
+// Some boards have too low voltage on this pin (board design bug)
+// Use different pin with 3V and connect with 48
+// and change this setup for the chosen pin (for example 38)
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 37;
+static const uint8_t RX = 40;
+
+static const uint8_t TXD2 = 17;
+static const uint8_t RXD2 = 18;
+
+static const uint8_t SDA = 19;
+static const uint8_t SCL = 20;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t G0 = 0;
+static const uint8_t G1 = 1;
+static const uint8_t G2 = 2;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G6 = 6;
+static const uint8_t G7 = 7;
+static const uint8_t G8 = 8;
+static const uint8_t G9 = 9;
+static const uint8_t G11 = 11;
+static const uint8_t G12 = 12;
+static const uint8_t G13 = 13;
+static const uint8_t G14 = 14;
+static const uint8_t G17 = 17;
+static const uint8_t G18 = 18;
+static const uint8_t G19 = 19;
+static const uint8_t G20 = 20;
+static const uint8_t G21 = 21;
+static const uint8_t G33 = 33;
+static const uint8_t G34 = 34;
+static const uint8_t G35 = 35;
+static const uint8_t G36 = 36;
+static const uint8_t G37 = 37;
+static const uint8_t G38 = 38;
+static const uint8_t G45 = 45;
+static const uint8_t G46 = 46;
+static const uint8_t G47 = 47;
+static const uint8_t G48 = 48;
+
+static const uint8_t ADC = 38;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32-devkit-lipo/pins_arduino.h b/variants/esp32-devkit-lipo/pins_arduino.h
index a405e764c6a..44dfe7cec8d 100644
--- a/variants/esp32-devkit-lipo/pins_arduino.h
+++ b/variants/esp32-devkit-lipo/pins_arduino.h
@@ -3,30 +3,22 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
-#define TX1 33	// Ext1 pin 8
-#define RX1 25	// Ext1 pin 9
+#define TX1 33  // Ext1 pin 8
+#define RX1 25  // Ext1 pin 9
 
-#define TX2 19	// Ext2 pin 8
-#define RX2 18	// Ext2 pin 9
+#define TX2 19  // Ext2 pin 8
+#define RX2 18  // Ext2 pin 9
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/esp32-evb/pins_arduino.h b/variants/esp32-evb/pins_arduino.h
index 15fa98e2496..7a980667535 100644
--- a/variants/esp32-evb/pins_arduino.h
+++ b/variants/esp32-evb/pins_arduino.h
@@ -3,15 +3,6 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-
 static const uint8_t KEY_BUILTIN = 34;
 
 static const uint8_t TX = 1;
@@ -23,11 +14,12 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 13;
 static const uint8_t SCL = 16;
 
-static const uint8_t SS    = 17;
-static const uint8_t MOSI  = 2;
-static const uint8_t MISO  = 15;
-static const uint8_t SCK   = 14;
+static const uint8_t SS = 17;
+static const uint8_t MOSI = 2;
+static const uint8_t MISO = 15;
+static const uint8_t SCK = 14;
 
 #define BOARD_HAS_1BIT_SDMMC
+#define BOARD_MAX_SDMMC_FREQ SDMMC_FREQ_DEFAULT
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/esp32-gateway/pins_arduino.h b/variants/esp32-gateway/pins_arduino.h
index 8e4216cdd9d..64f7ad000c5 100644
--- a/variants/esp32-gateway/pins_arduino.h
+++ b/variants/esp32-gateway/pins_arduino.h
@@ -3,32 +3,28 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-#if	ARDUINO_ESP32_GATEWAY >= 'D'
-#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT
+#if defined(ARDUINO_ESP32_GATEWAY_E) || defined(ARDUINO_ESP32_GATEWAY_F)
+#define ETH_PHY_TYPE  ETH_PHY_LAN8720
+#define ETH_PHY_ADDR  0
+#define ETH_PHY_MDC   23
+#define ETH_PHY_MDIO  18
 #define ETH_PHY_POWER 5
+#define ETH_CLK_MODE  ETH_CLOCK_GPIO17_OUT
 #endif
 
 static const uint8_t LED_BUILTIN = 33;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 34;
 
-static const uint8_t SCL = 16; // This is extention pin 11
-static const uint8_t SDA = 32; // This is extention pin 13
+static const uint8_t SCL = 16;  // This is extension pin 11
+static const uint8_t SDA = 32;  // This is extension pin 13
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -40,7 +36,7 @@ static const uint8_t A7 = 35;
 
 static const uint8_t T9 = 32;
 
-#if	ARDUINO_ESP32_GATEWAY >= 'F'
+#if defined(ARDUINO_ESP32_GATEWAY_F)
 #define BOARD_HAS_1BIT_SDMMC
 #endif
 
diff --git a/variants/esp32-gateway/variant.cpp b/variants/esp32-gateway/variant.cpp
new file mode 100644
index 00000000000..045cc145979
--- /dev/null
+++ b/variants/esp32-gateway/variant.cpp
@@ -0,0 +1,35 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2024 Olimex Ltd (support@olimex.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+#include "driver/gpio.h"
+
+extern "C" {
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // Change the drive strength of the digital output num 17 from the default value 20mA to 5mA
+  gpio_set_drive_capability((gpio_num_t)GPIO_NUM_17, GPIO_DRIVE_CAP_0);
+}
+}
diff --git a/variants/esp32-poe-iso/pins_arduino.h b/variants/esp32-poe-iso/pins_arduino.h
index 1ab04a7578b..7a6f59eac5c 100644
--- a/variants/esp32-poe-iso/pins_arduino.h
+++ b/variants/esp32-poe-iso/pins_arduino.h
@@ -3,16 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT
+#define ETH_PHY_TYPE  ETH_PHY_LAN8720
+#define ETH_PHY_ADDR  0
+#define ETH_PHY_MDC   23
+#define ETH_PHY_MDIO  18
 #define ETH_PHY_POWER 12
+#if defined BOARD_HAS_PSRAM  // when PSRAM is enabled pins 16 and 17 are used for the PSRAM and alternative pins are used for respectively I2C SCL and Ethernet Clock GPIO
+#define ETH_CLK_MODE ETH_CLOCK_GPIO0_OUT
+#else
+#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT
+#endif
 
 static const uint8_t KEY_BUILTIN = 34;
 
@@ -22,16 +22,20 @@ static const uint8_t RX = 3;
 #define TX1 4
 #define RX1 36
 
-#define TX2 33	// ext2 pin 5
-#define RX2 35	// ext2 pin 3
+#define TX2 33  // ext2 pin 5
+#define RX2 35  // ext2 pin 3
 
 static const uint8_t SDA = 13;
+#if defined BOARD_HAS_PSRAM  // when PSRAM is enabled pins 16 and 17 are used for the PSRAM and alternative pins are used for respectively I2C SCL and Ethernet Clock GPIO
+static const uint8_t SCL = 33;
+#else
 static const uint8_t SCL = 16;
+#endif
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 2;
-static const uint8_t MISO  = 15;
-static const uint8_t SCK   = 14;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 2;
+static const uint8_t MISO = 15;
+static const uint8_t SCK = 14;
 
 #define BOARD_HAS_1BIT_SDMMC
 
diff --git a/variants/esp32-poe/pins_arduino.h b/variants/esp32-poe/pins_arduino.h
index 1ab04a7578b..7a6f59eac5c 100644
--- a/variants/esp32-poe/pins_arduino.h
+++ b/variants/esp32-poe/pins_arduino.h
@@ -3,16 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT
+#define ETH_PHY_TYPE  ETH_PHY_LAN8720
+#define ETH_PHY_ADDR  0
+#define ETH_PHY_MDC   23
+#define ETH_PHY_MDIO  18
 #define ETH_PHY_POWER 12
+#if defined BOARD_HAS_PSRAM  // when PSRAM is enabled pins 16 and 17 are used for the PSRAM and alternative pins are used for respectively I2C SCL and Ethernet Clock GPIO
+#define ETH_CLK_MODE ETH_CLOCK_GPIO0_OUT
+#else
+#define ETH_CLK_MODE ETH_CLOCK_GPIO17_OUT
+#endif
 
 static const uint8_t KEY_BUILTIN = 34;
 
@@ -22,16 +22,20 @@ static const uint8_t RX = 3;
 #define TX1 4
 #define RX1 36
 
-#define TX2 33	// ext2 pin 5
-#define RX2 35	// ext2 pin 3
+#define TX2 33  // ext2 pin 5
+#define RX2 35  // ext2 pin 3
 
 static const uint8_t SDA = 13;
+#if defined BOARD_HAS_PSRAM  // when PSRAM is enabled pins 16 and 17 are used for the PSRAM and alternative pins are used for respectively I2C SCL and Ethernet Clock GPIO
+static const uint8_t SCL = 33;
+#else
 static const uint8_t SCL = 16;
+#endif
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 2;
-static const uint8_t MISO  = 15;
-static const uint8_t SCK   = 14;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 2;
+static const uint8_t MISO = 15;
+static const uint8_t SCK = 14;
 
 #define BOARD_HAS_1BIT_SDMMC
 
diff --git a/variants/esp32-sbc-fabgl/pins_arduino.h b/variants/esp32-sbc-fabgl/pins_arduino.h
new file mode 100644
index 00000000000..3663de76cd4
--- /dev/null
+++ b/variants/esp32-sbc-fabgl/pins_arduino.h
@@ -0,0 +1,48 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32-trueverit-iot-driver-mkii/pins_arduino.h b/variants/esp32-trueverit-iot-driver-mkii/pins_arduino.h
new file mode 100644
index 00000000000..12d35f71bfd
--- /dev/null
+++ b/variants/esp32-trueverit-iot-driver-mkii/pins_arduino.h
@@ -0,0 +1,45 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 18;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+#define TX1 12
+#define RX1 13
+#define TX2 33
+#define RX2 39
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SCL = 4;
+static const uint8_t SDA = 15;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 32;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+
+static const uint8_t T0 = 4;
+static const uint8_t T2 = 2;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+#define ETH_PHY_ADDR  1
+#define ETH_PHY_POWER 2
+#define ETH_PHY_MDC   16
+#define ETH_PHY_MDIO  14
+#define ETH_PHY_TYPE  ETH_PHY_DP83848
+#define ETH_CLK_MODE  ETH_CLOCK_GPIO17_OUT
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32-trueverit-iot-driver-mkiii/pins_arduino.h b/variants/esp32-trueverit-iot-driver-mkiii/pins_arduino.h
new file mode 100644
index 00000000000..4be9c7fe69a
--- /dev/null
+++ b/variants/esp32-trueverit-iot-driver-mkiii/pins_arduino.h
@@ -0,0 +1,45 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 18;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+#define TX1 12
+#define RX1 13
+#define TX2 33
+#define RX2 39
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SCL = 4;
+static const uint8_t SDA = 15;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 32;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+
+static const uint8_t T0 = 4;
+static const uint8_t T2 = 2;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+#define ETH_PHY_ADDR  0
+#define ETH_PHY_POWER 2
+#define ETH_PHY_MDC   16
+#define ETH_PHY_MDIO  14
+#define ETH_PHY_TYPE  ETH_PHY_RTL8201
+#define ETH_CLK_MODE  ETH_CLOCK_GPIO17_OUT
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32-trueverit-iot-driver/pins_arduino.h b/variants/esp32-trueverit-iot-driver/pins_arduino.h
new file mode 100644
index 00000000000..2f1edcf77c6
--- /dev/null
+++ b/variants/esp32-trueverit-iot-driver/pins_arduino.h
@@ -0,0 +1,45 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 18;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+#define TX1 12
+#define RX1 13
+#define TX2 33
+#define RX2 39
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SCL = 4;
+static const uint8_t SDA = 15;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 32;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+
+static const uint8_t T0 = 4;
+static const uint8_t T2 = 2;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+#define ETH_PHY_ADDR  0
+#define ETH_PHY_POWER -1
+#define ETH_PHY_MDC   16
+#define ETH_PHY_MDIO  14
+#define ETH_PHY_TYPE  ETH_PHY_LAN8720
+#define ETH_CLK_MODE  ETH_CLOCK_GPIO17_OUT
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32/pins_arduino.h b/variants/esp32/pins_arduino.h
index d50715e5c91..3663de76cd4 100644
--- a/variants/esp32/pins_arduino.h
+++ b/variants/esp32/pins_arduino.h
@@ -3,24 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/esp320/pins_arduino.h b/variants/esp320/pins_arduino.h
index ebb18ad3949..cb9152a7aa8 100644
--- a/variants/esp320/pins_arduino.h
+++ b/variants/esp320/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 11
-#define NUM_DIGITAL_PINS        12
-#define NUM_ANALOG_INPUTS       5
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 5;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -21,9 +13,9 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 2;
 static const uint8_t SCL = 14;
 
-static const uint8_t SS    = 15;
-static const uint8_t MOSI  = 13;
-static const uint8_t MISO  = 12;
-static const uint8_t SCK   = 14;
+static const uint8_t SS = 15;
+static const uint8_t MOSI = 13;
+static const uint8_t MISO = 12;
+static const uint8_t SCK = 14;
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/esp32_s3r8n16/gen4esp32_16MBapp.csv b/variants/esp32_s3r8n16/gen4esp32_16MBapp.csv
new file mode 100644
index 00000000000..d3b9316c255
--- /dev/null
+++ b/variants/esp32_s3r8n16/gen4esp32_16MBapp.csv
@@ -0,0 +1,5 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0xFE0000,
+coredump,    data,coredump, 0xFF0000, 0x10000,
diff --git a/variants/esp32_s3r8n16/gen4esp32_2MBapp_2MBota_12MBspiffs.csv b/variants/esp32_s3r8n16/gen4esp32_2MBapp_2MBota_12MBspiffs.csv
new file mode 100644
index 00000000000..431c235007d
--- /dev/null
+++ b/variants/esp32_s3r8n16/gen4esp32_2MBapp_2MBota_12MBspiffs.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000,0x200000,
+app1,     app,  ota_1, 0x210000,0x200000,
+spiffs,   data, spiffs, 0x410000,0xBE0000,
+coredump, data, coredump,0xFF0000,0x10000,
diff --git a/variants/esp32_s3r8n16/gen4esp32_4MBapp_4MBota_7MBspiffs.csv b/variants/esp32_s3r8n16/gen4esp32_4MBapp_4MBota_7MBspiffs.csv
new file mode 100644
index 00000000000..a0483430726
--- /dev/null
+++ b/variants/esp32_s3r8n16/gen4esp32_4MBapp_4MBota_7MBspiffs.csv
@@ -0,0 +1,7 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000, 0x480000,
+app1,     app,  ota_1,   0x490000,0x480000,
+spiffs,   data, spiffs,  0x910000,0x6E0000,
+coredump, data, coredump,0xFF0000,0x10000,
diff --git a/variants/esp32_s3r8n16/gen4esp32_8MBapp_8MBota.csv b/variants/esp32_s3r8n16/gen4esp32_8MBapp_8MBota.csv
new file mode 100644
index 00000000000..840a2f0d10e
--- /dev/null
+++ b/variants/esp32_s3r8n16/gen4esp32_8MBapp_8MBota.csv
@@ -0,0 +1,6 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x9000,  0x5000,
+otadata,  data, ota,     0xe000,  0x2000,
+app0,     app,  ota_0,   0x10000,0x7F0000,
+app1,     app,  ota_1, 0x800000,0x7F0000,
+coredump,   data,coredump, 0xFF0000,  0x10000,
diff --git a/variants/esp32_s3r8n16/pins_arduino.h b/variants/esp32_s3r8n16/pins_arduino.h
new file mode 100644
index 00000000000..ca2dda0c5c9
--- /dev/null
+++ b/variants/esp32_s3r8n16/pins_arduino.h
@@ -0,0 +1,23 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303a
+#define USB_PID          0x1001
+#define USB_MANUFACTURER "4D Systems Pty Ltd"
+#define USB_PRODUCT      "4D Systems gen4-ESP32 16MB Modules (ESP32-S3R8n16)"
+//#define USB_CLASS 2
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 17;
+static const uint8_t SCL = 18;
+
+static const uint8_t SS = -1;    // Modified elsewhere
+static const uint8_t MOSI = -1;  // Modified elsewhere
+static const uint8_t MISO = -1;  // Modified elsewhere
+static const uint8_t SCK = -1;   // Modified elsewhere
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32c2/pins_arduino.h b/variants/esp32c2/pins_arduino.h
new file mode 100644
index 00000000000..70024ead09c
--- /dev/null
+++ b/variants/esp32c2/pins_arduino.h
@@ -0,0 +1,28 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 13;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 20;
+static const uint8_t RX = 19;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32c3-devkit-lipo/pins_arduino.h b/variants/esp32c3-devkit-lipo/pins_arduino.h
new file mode 100644
index 00000000000..5459b893f27
--- /dev/null
+++ b/variants/esp32c3-devkit-lipo/pins_arduino.h
@@ -0,0 +1,38 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t LED_BUILTIN = 8;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t BUT_BUILTIN = 9;
+#define BUILTIN_BUT BUT_BUILTIN  // backward compatibility
+#define BUT_BUILTIN BUT_BUILTIN  // allow testing #ifdef BUT_BUILTIN
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+// define I2C pins
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+// define SPI pins
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+// external power sense - disabled by default - check the schematic
+//static const uint8_t PWR_SENSE = 4;
+// battery measurement - disabled by default - check the schematic
+//static const uint8_t BAT_SENSE = 3;
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32c3/pins_arduino.h b/variants/esp32c3/pins_arduino.h
new file mode 100644
index 00000000000..179ce636ea5
--- /dev/null
+++ b/variants/esp32c3/pins_arduino.h
@@ -0,0 +1,34 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_RGB_LED 8
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32c6-evb/pins_arduino.h b/variants/esp32c6-evb/pins_arduino.h
new file mode 100644
index 00000000000..a0b0d805ae7
--- /dev/null
+++ b/variants/esp32c6-evb/pins_arduino.h
@@ -0,0 +1,49 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t LED_BUILTIN = 8;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t BUT_BUILTIN = 9;
+#define BUILTIN_BUT BUT_BUILTIN  // backward compatibility
+#define BUT_BUILTIN BUT_BUILTIN  // allow testing #ifdef BUT_BUILTIN
+
+#define REL1 10
+#define REL2 11
+#define REL3 22
+#define REL4 23
+
+#define DIN1 1
+#define DIN2 2
+#define DIN3 3
+#define DIN4 15
+
+// available at UEXT and pUEXT +
+static const uint8_t TX1 = 5;
+static const uint8_t RX1 = 4;
+
+static const uint8_t SDA = 6;
+static const uint8_t SCL = 7;
+
+static const uint8_t SS = 21;
+static const uint8_t MOSI = 18;
+static const uint8_t MISO = 20;
+static const uint8_t SCK = 19;
+// available at UEXT and pUEXT -
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32c6/pins_arduino.h b/variants/esp32c6/pins_arduino.h
new file mode 100644
index 00000000000..348db9f907e
--- /dev/null
+++ b/variants/esp32c6/pins_arduino.h
@@ -0,0 +1,40 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_RGB_LED 8
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 23;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 19;
+static const uint8_t MISO = 20;
+static const uint8_t SCK = 21;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+
+// LP I2C Pins are fixed on ESP32-C6
+#define WIRE1_PIN_DEFINED
+static const uint8_t SDA1 = 6;
+static const uint8_t SCL1 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32da/pins_arduino.h b/variants/esp32da/pins_arduino.h
new file mode 100644
index 00000000000..212cb93a7e9
--- /dev/null
+++ b/variants/esp32da/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#define BOARD_HAS_DUAL_ANTENNA
+static const uint8_t ANT1 = 2;
+static const uint8_t ANT2 = 25;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32h2-devkit-lipo/pins_arduino.h b/variants/esp32h2-devkit-lipo/pins_arduino.h
new file mode 100644
index 00000000000..bb15be3e871
--- /dev/null
+++ b/variants/esp32h2-devkit-lipo/pins_arduino.h
@@ -0,0 +1,35 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_RGB_LED 8
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t KEY_BUILTIN = 9;
+
+static const uint8_t TX = 24;
+static const uint8_t RX = 23;
+
+static const uint8_t SDA = 12;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 0;
+static const uint8_t MOSI = 25;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 10;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32h2/pins_arduino.h b/variants/esp32h2/pins_arduino.h
new file mode 100644
index 00000000000..108d874699b
--- /dev/null
+++ b/variants/esp32h2/pins_arduino.h
@@ -0,0 +1,33 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_RGB_LED 8
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 24;
+static const uint8_t RX = 23;
+
+static const uint8_t SDA = 12;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 0;
+static const uint8_t MOSI = 25;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 10;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32micromod/pins_arduino.h b/variants/esp32micromod/pins_arduino.h
new file mode 100644
index 00000000000..ea74895edb2
--- /dev/null
+++ b/variants/esp32micromod/pins_arduino.h
@@ -0,0 +1,66 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+#define TX1 17
+#define RX1 16
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+static const uint8_t I2C_INT = 4;
+
+#define WIRE1_PIN_DEFINED 1  // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin)
+static const uint8_t SDA1 = 26;
+static const uint8_t SCL1 = 25;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 34;
+static const uint8_t A1 = 35;
+static const uint8_t BATT_VIN = 39;
+
+static const uint8_t PWM0 = 13;
+static const uint8_t PWM1 = 12;
+
+static const uint8_t D0 = 14;
+static const uint8_t D1 = 27;
+
+static const uint8_t G0 = 15;
+static const uint8_t G1 = 25;
+static const uint8_t G2 = 26;
+static const uint8_t G3 = 17;
+static const uint8_t G4 = 16;
+static const uint8_t G5 = 32;
+static const uint8_t G6 = 33;
+
+static const uint8_t AUD_OUT = 17;
+static const uint8_t AUD_IN = 16;
+static const uint8_t AUD_LRCLK = 25;
+static const uint8_t AUD_BCLK = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32p4/pins_arduino.h b/variants/esp32p4/pins_arduino.h
new file mode 100644
index 00000000000..cbb1e871ae5
--- /dev/null
+++ b/variants/esp32p4/pins_arduino.h
@@ -0,0 +1,85 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BOOT_MODE 35
+// BOOT_MODE2 36 pullup
+
+static const uint8_t TX = 37;
+static const uint8_t RX = 38;
+
+static const uint8_t SDA = 7;
+static const uint8_t SCL = 8;
+
+// Use GPIOs 36 or lower on the P4 DevKit to avoid LDO power issues with high numbered GPIOs.
+static const uint8_t SS = 26;
+static const uint8_t MOSI = 32;
+static const uint8_t MISO = 33;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 16;
+static const uint8_t A1 = 17;
+static const uint8_t A2 = 18;
+static const uint8_t A3 = 19;
+static const uint8_t A4 = 20;
+static const uint8_t A5 = 21;
+static const uint8_t A6 = 22;
+static const uint8_t A7 = 23;
+static const uint8_t A8 = 49;
+static const uint8_t A9 = 50;
+static const uint8_t A10 = 51;
+static const uint8_t A11 = 52;
+static const uint8_t A12 = 53;
+static const uint8_t A13 = 54;
+
+static const uint8_t T0 = 2;
+static const uint8_t T1 = 3;
+static const uint8_t T2 = 4;
+static const uint8_t T3 = 5;
+static const uint8_t T4 = 6;
+static const uint8_t T5 = 7;
+static const uint8_t T6 = 8;
+static const uint8_t T7 = 9;
+static const uint8_t T8 = 10;
+static const uint8_t T9 = 11;
+static const uint8_t T10 = 12;
+static const uint8_t T11 = 13;
+static const uint8_t T12 = 14;
+static const uint8_t T13 = 15;
+
+/* ESP32-P4 EV Function board specific definitions */
+//ETH
+#define ETH_PHY_TYPE    ETH_PHY_TLK110
+#define ETH_PHY_ADDR    1
+#define ETH_PHY_MDC     31
+#define ETH_PHY_MDIO    52
+#define ETH_PHY_POWER   51
+#define ETH_RMII_TX_EN  49
+#define ETH_RMII_TX0    34
+#define ETH_RMII_TX1    35
+#define ETH_RMII_RX0    29
+#define ETH_RMII_RX1_EN 30
+#define ETH_RMII_CRS_DV 28
+#define ETH_RMII_CLK    50
+#define ETH_CLK_MODE    EMAC_CLK_EXT_IN
+
+//SDMMC
+#define BOARD_HAS_SDMMC
+#define BOARD_SDMMC_SLOT           0
+#define BOARD_SDMMC_POWER_CHANNEL  4
+#define BOARD_SDMMC_POWER_PIN      45
+#define BOARD_SDMMC_POWER_ON_LEVEL LOW
+
+//WIFI - ESP32C6
+#define BOARD_HAS_SDIO_ESP_HOSTED
+#define BOARD_SDIO_ESP_HOSTED_CLK   18
+#define BOARD_SDIO_ESP_HOSTED_CMD   19
+#define BOARD_SDIO_ESP_HOSTED_D0    14
+#define BOARD_SDIO_ESP_HOSTED_D1    15
+#define BOARD_SDIO_ESP_HOSTED_D2    16
+#define BOARD_SDIO_ESP_HOSTED_D3    17
+#define BOARD_SDIO_ESP_HOSTED_RESET 54
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s2-devkit-lipo-usb/pins_arduino.h b/variants/esp32s2-devkit-lipo-usb/pins_arduino.h
new file mode 100644
index 00000000000..6dba09dbe43
--- /dev/null
+++ b/variants/esp32s2-devkit-lipo-usb/pins_arduino.h
@@ -0,0 +1,70 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_RGB_LED    18
+#define RGB_BUILTIN    PIN_RGB_LED
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t BUT_BUILTIN = 0;
+#define BUILTIN_BUT BUT_BUILTIN  // backward compatibility
+#define BUT_BUILTIN BUT_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+// external power sense - disabled by default - check the schematic
+//static const uint8_t PWR_SENSE = 7;
+// battery measurement - disabled by default - check the schematic
+//static const uint8_t BAT_SENSE = 8;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s2-devkit-lipo/pins_arduino.h b/variants/esp32s2-devkit-lipo/pins_arduino.h
new file mode 100644
index 00000000000..98116754f5a
--- /dev/null
+++ b/variants/esp32s2-devkit-lipo/pins_arduino.h
@@ -0,0 +1,72 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_RGB_LED    18
+#define RGB_BUILTIN    PIN_RGB_LED
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t BUT_BUILTIN = 0;
+#define BUILTIN_BUT BUT_BUILTIN  // backward compatibility
+#define BUT_BUILTIN BUT_BUILTIN  // allow testing #ifdef BUT_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// define I2C pins
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+// define SPI pins
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+// external power sense - disabled by default - check the schematic
+//static const uint8_t PWR_SENSE = 7;
+// battery measurement - disabled by default - check the schematic
+//static const uint8_t BAT_SENSE = 8;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s2/pins_arduino.h b/variants/esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..27391ef22ab
--- /dev/null
+++ b/variants/esp32s2/pins_arduino.h
@@ -0,0 +1,69 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// GPIO pin for Saola-1 & DevKitM-1 = 18
+#define PIN_RGB_LED 18
+// GPIO pin for Kaluga = 45
+//#define PIN_RGB_LED 45
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s2thing_plus/pins_arduino.h b/variants/esp32s2thing_plus/pins_arduino.h
new file mode 100644
index 00000000000..a0520dc8929
--- /dev/null
+++ b/variants/esp32s2thing_plus/pins_arduino.h
@@ -0,0 +1,70 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x1B4F
+#define USB_PID          0x0027
+#define USB_MANUFACTURER "SparkFun"
+#define USB_PRODUCT      "ESP32-S2 Thing Plus"
+#define USB_SERIAL       ""
+
+static const uint8_t LED_BUILTIN = 13;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+#define TX1 34
+#define RX1 33
+
+static const uint8_t SDA = 1;
+static const uint8_t SCL = 2;
+
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 17;
+static const uint8_t A1 = 18;
+static const uint8_t A2 = 14;
+static const uint8_t A3 = 9;
+static const uint8_t A4 = 7;
+static const uint8_t A5 = 5;
+
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s2usb/pins_arduino.h b/variants/esp32s2usb/pins_arduino.h
new file mode 100644
index 00000000000..4d31e12dcc6
--- /dev/null
+++ b/variants/esp32s2usb/pins_arduino.h
@@ -0,0 +1,72 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// Default USB Settings
+#define USB_VID            0x303A
+#define USB_PID            0x0003
+#define USB_MANUFACTURER   "Espressif Systems"
+#define USB_PRODUCT        "ESP32-S2-USB"
+#define USB_SERIAL         "0"
+#define USB_WEBUSB_ENABLED false
+#define USB_WEBUSB_URL     "https://docs.espressif.com/projects/arduino-esp32/en/latest/_static/webusb.html"
+
+// Default USB FirmwareMSC Settings
+#define USB_FW_MSC_VENDOR_ID        "ESP32-S2"      //max 8 chars
+#define USB_FW_MSC_PRODUCT_ID       "Firmware MSC"  //max 16 chars
+#define USB_FW_MSC_PRODUCT_REVISION "1.23"          //max 4 chars
+#define USB_FW_MSC_VOLUME_NAME      "S2-Firmware"   //max 11 chars
+#define USB_FW_MSC_SERIAL_NUMBER    0x00000000
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s3-devkit-lipo/pins_arduino.h b/variants/esp32s3-devkit-lipo/pins_arduino.h
new file mode 100644
index 00000000000..3e1ae6f2381
--- /dev/null
+++ b/variants/esp32s3-devkit-lipo/pins_arduino.h
@@ -0,0 +1,75 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = 38;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t BUT_BUILTIN = 0;
+#define BUILTIN_BUT BUT_BUILTIN  // backward compatibility
+#define BUT_BUILTIN BUT_BUILTIN  // allow testing #ifdef BUT_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// available at pUEXT +
+static const uint8_t TX1 = 17;
+static const uint8_t RX1 = 18;
+
+static const uint8_t SDA = 48;
+static const uint8_t SCL = 47;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+// available at pUEXT -
+
+// external power sense
+static const uint8_t PWR_SENSE = 5;
+// battery measurement
+static const uint8_t BAT_SENSE = 6;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s3/pins_arduino.h b/variants/esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..623d684e20f
--- /dev/null
+++ b/variants/esp32s3/pins_arduino.h
@@ -0,0 +1,69 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+// Some boards have too low voltage on this pin (board design bug)
+// Use different pin with 3V and connect with 48
+// and change this setup for the chosen pin (for example 38)
+#define PIN_RGB_LED 48
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s3_powerfeather/pins_arduino.h b/variants/esp32s3_powerfeather/pins_arduino.h
new file mode 100644
index 00000000000..f5f3b20551e
--- /dev/null
+++ b/variants/esp32s3_powerfeather/pins_arduino.h
@@ -0,0 +1,55 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303A
+#define USB_PID          0x81BB
+#define USB_MANUFACTURER "PowerFeather"
+#define USB_PRODUCT      "ESP32-S3 PowerFeather"
+#define USB_SERIAL       ""
+
+static const uint8_t ALARM = 21;
+static const uint8_t INT = 5;
+
+static const uint8_t LED = 46;
+static const uint8_t BTN = 0;
+static const uint8_t EN = 7;
+
+static const uint8_t TX = 44;
+static const uint8_t RX = 42;
+static const uint8_t TX0 = 43;
+
+static const uint8_t SS = -1;
+static const uint8_t MISO = 41;
+static const uint8_t MOSI = 40;
+static const uint8_t SCK = 39;
+
+static const uint8_t SCL = 36;
+static const uint8_t SDA = 35;
+
+#define WIRE1_PIN_DEFINED 1
+static const uint8_t SCL1 = 48;
+static const uint8_t SDA1 = 47;
+
+static const uint8_t A0 = 10;
+static const uint8_t A1 = 9;
+static const uint8_t A2 = 8;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 2;
+static const uint8_t A5 = 1;
+
+static const uint8_t D5 = 15;
+static const uint8_t D6 = 16;
+static const uint8_t D7 = 37;
+static const uint8_t D8 = 6;
+static const uint8_t D9 = 17;
+static const uint8_t D10 = 18;
+static const uint8_t D11 = 45;
+static const uint8_t D12 = 12;
+static const uint8_t D13 = 11;
+
+#define LED_BUILTIN 46
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s3box/pins_arduino.h b/variants/esp32s3box/pins_arduino.h
new file mode 100644
index 00000000000..8fb0a8cd7d0
--- /dev/null
+++ b/variants/esp32s3box/pins_arduino.h
@@ -0,0 +1,61 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 41;
+static const uint8_t SCL = 40;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+// Wire1 for ES7210 MIC ADC, ES8311 I2S DAC, ICM-42607-P IMU and TT21100 Touch Panel
+#define I2C_SDA 8
+#define I2C_SCL 18
+
+#define ES7210_ADDR    0x40  //MIC ADC
+#define ES8311_ADDR    0x18  //I2S DAC
+#define ICM42607P_ADDR 0x68  //IMU
+#define TT21100_ADDR   0x24  //Touch Panel
+
+#define TFT_DC   4
+#define TFT_CS   5
+#define TFT_MOSI 6
+#define TFT_CLK  7
+#define TFT_MISO 0
+#define TFT_BL   45
+#define TFT_RST  48
+
+#define I2S_LRCK 47
+#define I2S_MCLK 2
+#define I2S_SCLK 17
+#define I2S_SDIN 16
+#define I2S_DOUT 15
+
+#define PA_PIN   46  //Audio Amp Power
+#define MUTE_PIN 1   //MUTE Button
+#define TS_IRQ   3   //Touch Screen IRQ
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s3camlcd/pins_arduino.h b/variants/esp32s3camlcd/pins_arduino.h
new file mode 100644
index 00000000000..ca734b96b3b
--- /dev/null
+++ b/variants/esp32s3camlcd/pins_arduino.h
@@ -0,0 +1,63 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 17;
+static const uint8_t SCL = 18;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+// Wire1 for Cam and TS
+#define I2C_SDA 17
+#define I2C_SCL 18
+
+#define PWDN_GPIO_NUM  -1
+#define RESET_GPIO_NUM -1
+#define XCLK_GPIO_NUM  40
+#define SIOD_GPIO_NUM  17
+#define SIOC_GPIO_NUM  18
+#define Y9_GPIO_NUM    39
+#define Y8_GPIO_NUM    41
+#define Y7_GPIO_NUM    42
+#define Y6_GPIO_NUM    12
+#define Y5_GPIO_NUM    3
+#define Y4_GPIO_NUM    14
+#define Y3_GPIO_NUM    47
+#define Y2_GPIO_NUM    13
+#define VSYNC_GPIO_NUM 21
+#define HREF_GPIO_NUM  38
+#define PCLK_GPIO_NUM  11
+
+#define TFT_FREQ   40000000
+#define TFT_BITS   8
+#define TFT_WIDTH  480
+#define TFT_HEIGHT 320
+#define TFT_WR     4
+#define TFT_DC     2
+#define TFT_D0     45
+#define TFT_D1     16
+#define TFT_D2     15
+#define TFT_D3     10
+#define TFT_D4     8
+#define TFT_D5     7
+#define TFT_D6     6
+#define TFT_D7     5
+
+#define SDMMC_CMD  20
+#define SDMMC_CLK  9
+#define SDMMC_DATA 19
+
+#define MIC_CLK  0
+#define MIC_DATA 1
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s3usbotg/pins_arduino.h b/variants/esp32s3usbotg/pins_arduino.h
new file mode 100644
index 00000000000..5b873e2d2f1
--- /dev/null
+++ b/variants/esp32s3usbotg/pins_arduino.h
@@ -0,0 +1,96 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 45;
+static const uint8_t SCL = 46;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+
+static const uint8_t T3 = 3;
+
+// SDCARD Slot
+#define BOARD_HAS_SDMMC
+#define SDMMC_D2             33  // SDMMC Data2
+#define SDMMC_D3             34  // SDMMC Data3 / SPI CS
+#define SDMMC_CMD            35  // SDMMC CMD   / SPI MOSI
+#define SDMMC_CLK            36  // SDMMC CLK   / SPI SCK
+#define SDMMC_D0             37  // SDMMC Data0 / SPI MISO
+#define SDMMC_D1             38  // SDMMC Data1
+#define BOARD_MAX_SDMMC_FREQ SDMMC_FREQ_DEFAULT
+
+// 240x240 LCD
+#define BOARD_HAS_SPI_LCD
+#define LCD_MODEL  ST7789
+#define LCD_WIDTH  240
+#define LCD_HEIGHT 240  // *RAM height is actually 320!
+#define LCD_MISO   -1   // LCD Does not use MISO.
+#define LCD_DC     4    // Used to switch data and command status.
+#define LCD_CS     5    // used to enable LCD, low level to enable.
+#define LCD_CLK    6    // LCD SPI Clock.
+#define LCD_MOSI   7    // LCD SPI MOSI.
+#define LCD_RST    8    // used to reset LCD, low level to reset.
+#define LCD_BL     9    // LCD backlight control.
+
+// Buttons
+#define BUTTON_OK   0   // OK button, low level when pressed.
+#define BUTTON_UP   10  // UP button, low level when pressed.
+#define BUTTON_DOWN 11  // Down button, low level when pressed.
+#define BUTTON_MENU 14  // Menu button, low level when pressed.
+
+// LEDs
+#define LED_GREEN  15  // the light is lit when set high level.
+#define LED_YELLOW 16  // the light is lit when set high level.
+
+// Board Controls
+#define DEV_VBUS_EN 12  // High level to enable DEV_VBUS power supply.
+#define BOOST_EN    13  // High level to enable Battery Boost circuit.
+#define LIMIT_EN    17  // Enable USB_HOST current limiting IC, high level enable.
+#define USB_HOST_EN \
+  18  // Used to switch the USB interface. When high level, the USB_HOST interface is enabled. When low level, the USB_DEV interface is enabled.
+
+// Board Sensors
+#define OVER_CURRENT 21  // Current overrun signal, high level means overrun.
+#define HOST_VOLTS   1   // USB_DEV voltage monitoring, ADC1 channel 0. actual_v = value_v * 3.7
+#define BAT_VOLTS    2   // Battery voltage monitoring, ADC1 channel 1. actual_v = value_v * 2
+
+// USB Port
+#define USB_DN 19  // USB D-
+#define USB_DP 20  // USB D+
+
+// Bottom header
+#define MTCK 39
+#define MTDO 40
+#define MTDI 41
+#define MTMS 42
+// #define FREE_6        3 // Idle, can be customized.
+// #define FREE_4       26 // Idle, can be customized.
+// #define FREE_1       45 // Idle, can be customized.
+// #define FREE_2       46 // Idle, can be customized.
+// #define FREE_5       47 // Idle, can be customized.
+// #define FREE_3       48 // Idle, can be customized.
+
+typedef enum {
+  USB_HOST_POWER_OFF,
+  USB_HOST_POWER_VBUS,
+  USB_HOST_POWER_BAT
+} UsbHostPower_t;
+void usbHostPower(UsbHostPower_t mode);
+void usbHostEnable(bool enable);
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32s3usbotg/variant.cpp b/variants/esp32s3usbotg/variant.cpp
new file mode 100644
index 00000000000..a8de800f90a
--- /dev/null
+++ b/variants/esp32s3usbotg/variant.cpp
@@ -0,0 +1,52 @@
+#include "Arduino.h"
+
+void usbHostPower(UsbHostPower_t mode) {
+  static UsbHostPower_t m = USB_HOST_POWER_OFF;
+  if (m == mode) {
+    return;
+  }
+  if (mode == USB_HOST_POWER_OFF) {
+    digitalWrite(LIMIT_EN, LOW);
+    if (m == USB_HOST_POWER_VBUS) {
+      digitalWrite(DEV_VBUS_EN, LOW);
+    } else if (m == USB_HOST_POWER_BAT) {
+      digitalWrite(BOOST_EN, LOW);
+    }
+  } else if (mode == USB_HOST_POWER_VBUS) {
+    if (m == USB_HOST_POWER_BAT) {
+      digitalWrite(BOOST_EN, LOW);
+    }
+    digitalWrite(DEV_VBUS_EN, HIGH);
+  } else if (mode == USB_HOST_POWER_BAT) {
+    if (m == USB_HOST_POWER_VBUS) {
+      digitalWrite(DEV_VBUS_EN, LOW);
+    }
+    digitalWrite(BOOST_EN, HIGH);
+  }
+  if (mode != USB_HOST_POWER_OFF) {
+    digitalWrite(LIMIT_EN, HIGH);
+  }
+  m = mode;
+}
+
+void usbHostEnable(bool enable) {
+  digitalWrite(USB_HOST_EN, enable);
+}
+
+extern "C" void initVariant(void) {
+  // Route USB to Device Side
+  pinMode(BOOST_EN, OUTPUT);
+  digitalWrite(BOOST_EN, LOW);
+  pinMode(LIMIT_EN, OUTPUT);
+  digitalWrite(LIMIT_EN, LOW);
+  pinMode(DEV_VBUS_EN, OUTPUT);
+  digitalWrite(DEV_VBUS_EN, LOW);
+  pinMode(USB_HOST_EN, OUTPUT);
+  digitalWrite(USB_HOST_EN, LOW);
+
+  // Turn Off LCD
+  pinMode(LCD_RST, OUTPUT);
+  digitalWrite(LCD_RST, LOW);
+  pinMode(LCD_BL, OUTPUT);
+  digitalWrite(LCD_BL, LOW);
+}
diff --git a/variants/esp32thing/pins_arduino.h b/variants/esp32thing/pins_arduino.h
index f0f8e69eafa..00abcdfb191 100644
--- a/variants/esp32thing/pins_arduino.h
+++ b/variants/esp32thing/pins_arduino.h
@@ -3,17 +3,11 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
+#define F_XTAL_MHZ 26  //SparkFun ESP32 Thing has 26MHz Crystal
 
 static const uint8_t LED_BUILTIN = 5;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -23,10 +17,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 2;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 2;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/esp32thing_plus/pins_arduino.h b/variants/esp32thing_plus/pins_arduino.h
index 6cdd2950b8a..0803c6780f0 100644
--- a/variants/esp32thing_plus/pins_arduino.h
+++ b/variants/esp32thing_plus/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 13;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 17;
 static const uint8_t RX = 16;
@@ -24,13 +16,13 @@ static const uint8_t RX = 16;
 static const uint8_t SDA = 23;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 33;
-static const uint8_t MOSI  = 18;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 5;
+static const uint8_t SS = 33;
+static const uint8_t MOSI = 18;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
 
 // mapping to match other feathers and also in order
-static const uint8_t A0 = 26; 
+static const uint8_t A0 = 26;
 static const uint8_t A1 = 25;
 static const uint8_t A2 = 34;
 static const uint8_t A3 = 39;
@@ -44,7 +36,6 @@ static const uint8_t A10 = 27;
 static const uint8_t A11 = 12;
 static const uint8_t A12 = 13;
 
-
 static const uint8_t T0 = 4;
 static const uint8_t T1 = 0;
 static const uint8_t T2 = 2;
diff --git a/variants/esp32thing_plus_c/pins_arduino.h b/variants/esp32thing_plus_c/pins_arduino.h
new file mode 100644
index 00000000000..ca7b6c65d45
--- /dev/null
+++ b/variants/esp32thing_plus_c/pins_arduino.h
@@ -0,0 +1,58 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t LED_BUILTIN = 13;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+static const uint8_t RGB_BUILTIN = SOC_GPIO_PIN_COUNT + 2;
+#define RGB_BUILTIN    RGB_BUILTIN  // necessary to make digitalWrite/digitalMode find it
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 17;
+static const uint8_t RX = 16;
+
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 15;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 26;
+static const uint8_t A1 = 25;
+static const uint8_t A2 = 34;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 36;
+static const uint8_t A5 = 35;
+static const uint8_t A6 = 14;
+static const uint8_t A7 = 32;
+static const uint8_t A8 = 15;
+static const uint8_t A9 = 33;
+static const uint8_t A10 = 27;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/esp32vn-iot-uno/pins_arduino.h b/variants/esp32vn-iot-uno/pins_arduino.h
index 0bdb52da4ec..167e649e5e3 100644
--- a/variants/esp32vn-iot-uno/pins_arduino.h
+++ b/variants/esp32vn-iot-uno/pins_arduino.h
@@ -3,24 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -46,7 +38,6 @@ static const uint8_t T5 = 12;
 static const uint8_t T6 = 14;
 static const uint8_t T7 = 27;
 
-
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
 
diff --git a/variants/esp_c3_m1_i_kit/pins_arduino.h b/variants/esp_c3_m1_i_kit/pins_arduino.h
new file mode 100644
index 00000000000..01ee56d4230
--- /dev/null
+++ b/variants/esp_c3_m1_i_kit/pins_arduino.h
@@ -0,0 +1,43 @@
+/*
+   For more information about this board:
+   https://docs.ai-thinker.com/_media/esp32/docs/nodemcu-esp-c3-m1-i-kit_v1.2.0_specification.pdf
+*/
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// User LEDs are also connected to USB D- and D+
+static const uint8_t LED_WARM = 18;
+static const uint8_t LED_COLD = 19;
+
+// RGB LED
+static const uint8_t LED_RED = 3;
+static const uint8_t LED_GREEN = 4;
+static const uint8_t LED_BLUE = 5;
+
+static const uint8_t LED_BUILTIN = LED_WARM;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+// Standard ESP32-C3 GPIOs
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/espea32/pins_arduino.h b/variants/espea32/pins_arduino.h
index 359defee34b..bc0d7a1f772 100644
--- a/variants/espea32/pins_arduino.h
+++ b/variants/espea32/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 5;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/espectro32/pins_arduino.h b/variants/espectro32/pins_arduino.h
index 43351c23a36..7f6dbb18e32 100644
--- a/variants/espectro32/pins_arduino.h
+++ b/variants/espectro32/pins_arduino.h
@@ -5,19 +5,11 @@
 
 #ifndef ESPECTRO32_VERSION
 #define ESPECTRO32_VERSION 1
-#endif 
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
+#endif
 
 static const uint8_t LED_BUILTIN = 15;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -26,10 +18,10 @@ static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
 static const uint8_t SD_SS = 33;
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/espino32/pins_arduino.h b/variants/espino32/pins_arduino.h
index 24f9ac51996..840fd863629 100644
--- a/variants/espino32/pins_arduino.h
+++ b/variants/espino32/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        38
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 16;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t BUILTIN_KEY = 0;
 
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/feather_esp32/pins_arduino.h b/variants/feather_esp32/pins_arduino.h
index 743d53c3cb2..523ea49f6ec 100644
--- a/variants/feather_esp32/pins_arduino.h
+++ b/variants/feather_esp32/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 13;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 17;
 static const uint8_t RX = 16;
@@ -24,13 +16,13 @@ static const uint8_t RX = 16;
 static const uint8_t SDA = 23;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 33;
-static const uint8_t MOSI  = 18;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 5;
+static const uint8_t SS = 33;
+static const uint8_t MOSI = 18;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
 
 // mapping to match other feathers and also in order
-static const uint8_t A0 = 26; 
+static const uint8_t A0 = 26;
 static const uint8_t A1 = 25;
 static const uint8_t A2 = 34;
 static const uint8_t A3 = 39;
@@ -45,14 +37,12 @@ static const uint8_t A11 = 12;
 static const uint8_t A12 = 13;
 
 // vbat measure
+static const uint8_t BATT_MONITOR = 35;
 static const uint8_t A13 = 35;
 //static const uint8_t Ax = 0; // not used/available
 //static const uint8_t Ax = 2; // not used/available
 
-
 static const uint8_t T0 = 4;
-static const uint8_t T1 = 0;
-static const uint8_t T2 = 2;
 static const uint8_t T3 = 15;
 static const uint8_t T4 = 13;
 static const uint8_t T5 = 12;
diff --git a/variants/firebeetle32/pins_arduino.h b/variants/firebeetle32/pins_arduino.h
index 8783987f5e7..60a35d603c1 100644
--- a/variants/firebeetle32/pins_arduino.h
+++ b/variants/firebeetle32/pins_arduino.h
@@ -3,21 +3,11 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 typedef unsigned char uint8_t;
 
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-
-
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -25,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t D0 = 3;
 static const uint8_t D1 = 1;
@@ -40,6 +30,7 @@ static const uint8_t D6 = 10;
 static const uint8_t D7 = 13;
 static const uint8_t D8 = 5;
 static const uint8_t D9 = 2;
+static const uint8_t D10 = 0;
 
 static const uint8_t A0 = 36;
 static const uint8_t A1 = 39;
@@ -57,20 +48,6 @@ static const uint8_t A12 = 27;
 static const uint8_t A13 = 25;
 static const uint8_t A14 = 26;
 
-
-
-static const uint8_t D0 = 3;
-static const uint8_t D1 = 1;
-static const uint8_t D2 = 25;
-static const uint8_t D3 = 26;
-static const uint8_t D4 = 27;
-static const uint8_t D5 = 9;
-static const uint8_t D6 = 10;
-static const uint8_t D7 = 13;
-static const uint8_t D8 = 5;
-static const uint8_t D9 = 2;
-static const uint8_t D10 = 0;
-
 static const uint8_t T0 = 4;
 static const uint8_t T1 = 0;
 static const uint8_t T2 = 2;
diff --git a/variants/fm-devkit/pins_arduino.h b/variants/fm-devkit/pins_arduino.h
index 2302dd9f67e..63a6d866390 100644
--- a/variants/fm-devkit/pins_arduino.h
+++ b/variants/fm-devkit/pins_arduino.h
@@ -1,53 +1,47 @@
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-static const uint8_t TX = 1;
-static const uint8_t RX = 3;
-
-// IO
-static const uint8_t LED_BUILTIN = 5;
-static const uint8_t SW1 = 4;
-static const uint8_t SW2 = 18;
-static const uint8_t SW3 = 19;
-static const uint8_t SW4 = 21;
-
-//I2S DAC
-static const uint8_t I2S_MCLK = 2;    // CLOCK must be an integer multiplier of SCLK
-static const uint8_t I2S_LRCLK = 25;  // LRCLK
-static const uint8_t I2S_SCLK = 26;   // SCLK - Fs (44100 Hz)
-static const uint8_t I2S_DOUT = 22;   // DATA
-
-//GPIO
-static const uint8_t D0 = 34; // GPI - Input Only
-static const uint8_t D1 = 35; // GPI - Input Only
-static const uint8_t D2 = 32; // GPO - Output Only
-static const uint8_t D3 = 33; // GPO - Output Only
-static const uint8_t D4 = 27;
-static const uint8_t D5 = 14;
-static const uint8_t D6 = 12;
-static const uint8_t D7 = 13;
-static const uint8_t D8 = 15;
-static const uint8_t D9 = 23;
-static const uint8_t D10 = 0;
-
-// I2C BUS, 2k2 hardware pull-ups
-static const uint8_t SDA = 16;
-static const uint8_t SCL = 17;
-
-// SPI - unused but you can create your own definition in your sketch
-static const int8_t SCK = -1;
-static const int8_t MISO = -1;
-static const int8_t MOSI = -1;
-static const int8_t SS = -1;
-
-#endif /* Pins_Arduino_h */
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+// IO
+static const uint8_t LED_BUILTIN = 5;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+static const uint8_t SW1 = 4;
+static const uint8_t SW2 = 18;
+static const uint8_t SW3 = 19;
+static const uint8_t SW4 = 21;
+
+//I2S DAC
+static const uint8_t I2S_MCLK = 2;    // CLOCK must be an integer multiplier of SCLK
+static const uint8_t I2S_LRCLK = 25;  // LRCLK
+static const uint8_t I2S_SCLK = 26;   // SCLK - Fs (44100 Hz)
+static const uint8_t I2S_DOUT = 22;   // DATA
+
+//GPIO
+static const uint8_t D0 = 34;  // GPI - Input Only
+static const uint8_t D1 = 35;  // GPI - Input Only
+static const uint8_t D2 = 32;  // GPO - Output Only
+static const uint8_t D3 = 33;  // GPO - Output Only
+static const uint8_t D4 = 27;
+static const uint8_t D5 = 14;
+static const uint8_t D6 = 12;
+static const uint8_t D7 = 13;
+static const uint8_t D8 = 15;
+static const uint8_t D9 = 23;
+static const uint8_t D10 = 0;
+
+// I2C BUS, 2k2 hardware pull-ups
+static const uint8_t SDA = 16;
+static const uint8_t SCL = 17;
+
+// SPI - unused but you can create your own definition in your sketch
+static const int8_t SCK = -1;
+static const int8_t MISO = -1;
+static const int8_t MOSI = -1;
+static const int8_t SS = -1;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/franzininho_wifi_esp32s2/pins_arduino.h b/variants/franzininho_wifi_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..b75fcc768d7
--- /dev/null
+++ b/variants/franzininho_wifi_esp32s2/pins_arduino.h
@@ -0,0 +1,73 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID            0x303A
+#define USB_PID            0x80A9
+#define USB_MANUFACTURER   "Franzininho"
+#define USB_PRODUCT        "Franzininho WIFI"
+#define USB_SERIAL         "0"
+#define USB_WEBUSB_ENABLED false
+
+static const uint8_t PIN_RGB_LED = 18;
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = (PIN_RGB_LED + SOC_GPIO_PIN_COUNT);
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/franzininho_wifi_msc_esp32s2/pins_arduino.h b/variants/franzininho_wifi_msc_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..db213cb97d4
--- /dev/null
+++ b/variants/franzininho_wifi_msc_esp32s2/pins_arduino.h
@@ -0,0 +1,80 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID            0x303A
+#define USB_PID            0x80A9
+#define USB_MANUFACTURER   "Franzininho"
+#define USB_PRODUCT        "Franzininho WIFI MSC"
+#define USB_SERIAL         "0"
+#define USB_WEBUSB_ENABLED false
+
+// Default USB FirmwareMSC Settings
+#define USB_FW_MSC_VENDOR_ID        "ESP32-S2"      //max 8 chars
+#define USB_FW_MSC_PRODUCT_ID       "Firmware MSC"  //max 16 chars
+#define USB_FW_MSC_PRODUCT_REVISION "1.23"          //max 4 chars
+#define USB_FW_MSC_VOLUME_NAME      "S2-Firmware"   //max 11 chars
+#define USB_FW_MSC_SERIAL_NUMBER    0x00000000
+
+static const uint8_t PIN_RGB_LED = 18;
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = (PIN_RGB_LED + SOC_GPIO_PIN_COUNT);
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/fri3d_2024_esp32s3/pins_arduino.h b/variants/fri3d_2024_esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..3cdba371f57
--- /dev/null
+++ b/variants/fri3d_2024_esp32s3/pins_arduino.h
@@ -0,0 +1,127 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = 21;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 9;
+static const uint8_t SCL = 18;
+
+static const uint8_t SS = 14;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 8;
+static const uint8_t SCK = 7;
+
+#define X_FRI3D_BADGE_2024   // General Define for use in sketches or lib files
+#define X_WS2812_NUM_LEDS 5  // Number of RBG LEDs
+
+#define PIN_I2C_SDA       SDA
+#define PIN_I2C_SCL       SCL
+#define PIN_WS2812        12
+#define X_WS2812_NUM_LEDS 5
+
+#define PIN_LED         21
+#define PIN_IR_RECEIVER 11
+#define PIN_BLASTER     10
+#define PIN_BUZZER      46
+#define PIN_BATTERY     13
+
+#define PIN_SDCARD_CS SS
+
+#define PIN_JOY_X 1
+#define PIN_JOY_Y 3
+
+#define PIN_A     39
+#define PIN_B     40
+#define PIN_X     38
+#define PIN_Y     41
+#define PIN_MENU  45
+#define PIN_START 0
+
+#define PIN_AUX 42  // Fri3d Badge 2024 Aux Pwr
+
+#define CHANNEL_BUZZER 0
+
+// Fri3d Badge 2024 Accelero Gyro
+#define X_ACCELERO_GYRO 21
+
+// I2S microphone on communicator addon
+#define I2S_MIC_CHANNEL          I2S_CHANNEL_FMT_ONLY_LEFT
+#define I2S_MIC_SERIAL_CLOCK     17  //serial clock SCLK: pin SCK
+#define I2S_MIC_LEFT_RIGHT_CLOCK 47  //left/right clock LRCK: pin WS
+#define I2S_MIC_SERIAL_DATA      15  //serial data DIN: pin SD
+
+// Fri3d Badge 2024 LCD
+// For using display with TFT_eSPI library
+#define USER_SETUP_LOADED
+#define SPI_FREQUENCY 80000000
+#define ST7789_DRIVER
+#define USE_HSPI_PORT
+
+#define TFT_RGB_ORDER TFT_BGR  //# swap red and blue byte order
+#define TFT_INVERSION_OFF
+#define TFT_WIDTH  296  //;setting these will init the eSPI lib with correct dimensions
+#define TFT_HEIGHT 240  //;setting these will init the eSPI lib with correct dimensions
+#define TFT_MISO   MISO
+#define TFT_MOSI   MOSI
+#define TFT_SCLK   SCK
+#define TFT_CS     5
+#define TFT_DC     4
+#define TFT_RST    48
+#define LOAD_GLCD  1
+#define LOAD_FONT2
+#define LOAD_FONT4
+#define LOAD_FONT6
+#define LOAD_FONT7
+#define LOAD_FONT8
+#define LOAD_GFXFF
+#define SMOOTH_FONT
+#define SPI_FREQUENCY 80000000
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/frog32/pins_arduino.h b/variants/frog32/pins_arduino.h
index d50715e5c91..3663de76cd4 100644
--- a/variants/frog32/pins_arduino.h
+++ b/variants/frog32/pins_arduino.h
@@ -3,24 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/gpy/pins_arduino.h b/variants/gpy/pins_arduino.h
index 71760e37693..93d3e5bfa1d 100644
--- a/variants/gpy/pins_arduino.h
+++ b/variants/gpy/pins_arduino.h
@@ -2,42 +2,40 @@
 #define Pins_Arduino_h
 
 #include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       18
-
-#define analogInputToDigitalPin(p)  (((p)<40)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
+#include "soc/soc_caps.h"
 
 // Sequans Monarch LTE Cat M1/NB1 modem
 // NOTE: The Pycom pinout as well as spec sheet block diagram / pin details
 // incorrectly list the LTE pins. The correct pins are defined in the source and CSV
 // at https://github.com/pycom/pycom-micropython-sigfox/tree/master/esp32/boards/GPY.
-#define LTE_CTS 18  // GPIO18 - Sequans modem CTS
-#define LTE_RTS 19  // GPIO19 - Sequans modem RTS (pull low to communicate)
-#define LTE_RX 23   // GPIO23 - Sequans modem RX
-#define LTE_TX 5    // GPIO5  - Sequans modem TX
-#define LTE_WAKE 27 // GPIO27 - Sequans modem wake-up interrupt
+#define LTE_CTS  18  // GPIO18 - Sequans modem CTS
+#define LTE_RTS  19  // GPIO19 - Sequans modem RTS (pull low to communicate)
+#define LTE_RX   23  // GPIO23 - Sequans modem RX
+#define LTE_TX   5   // GPIO5  - Sequans modem TX
+#define LTE_WAKE 27  // GPIO27 - Sequans modem wake-up interrupt
 #define LTE_BAUD 921600
 
-static const uint8_t LED_BUILTIN = 0; // ->2812 RGB !!!
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+// RGB LED
+#define PIN_RGB_LED 0  // ->2812 RGB !!!
+static const uint8_t LED_BUILTIN = PIN_RGB_LED + SOC_GPIO_PIN_COUNT;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
 
-#define ANT_SELECT 21   // GPIO21 - WiFi external / internal antenna switch
+#define ANT_SELECT 21  // GPIO21 - WiFi external / internal antenna switch
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 12;
 static const uint8_t SCL = 13;
- 
-static const uint8_t SS    = 17;
-static const uint8_t MOSI  = 22;
-static const uint8_t MISO  = 37;
-static const uint8_t SCK   = 13;
+
+static const uint8_t SS = 17;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 13;
 
 static const uint8_t A0 = 36;
 static const uint8_t A1 = 37;
diff --git a/variants/healthypi4/pins_arduino.h b/variants/healthypi4/pins_arduino.h
index 15f5b189b04..2b8707fdaeb 100644
--- a/variants/healthypi4/pins_arduino.h
+++ b/variants/healthypi4/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 15;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 17;
 
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 2;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 2;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -59,15 +51,15 @@ static const uint8_t T9 = 32;
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
 
-static const uint8_t ADS1292_DRDY_PIN   = 26;
-static const uint8_t ADS1292_CS_PIN     = 13;
-static const uint8_t ADS1292_START_PIN  = 14;
-static const uint8_t ADS1292_PWDN_PIN   = 27;
-static const uint8_t AFE4490_CS_PIN     = 21;
-static const uint8_t AFE4490_DRDY_PIN   = 39;
-static const uint8_t AFE4490_PWDN_PIN   = 4;
+static const uint8_t ADS1292_DRDY_PIN = 26;
+static const uint8_t ADS1292_CS_PIN = 13;
+static const uint8_t ADS1292_START_PIN = 14;
+static const uint8_t ADS1292_PWDN_PIN = 27;
+static const uint8_t AFE4490_CS_PIN = 21;
+static const uint8_t AFE4490_DRDY_PIN = 39;
+static const uint8_t AFE4490_PWDN_PIN = 4;
 
-static const uint8_t PUSH_BUTTON        = 17;
-static const uint8_t SLIDE_SWITCH       = 16;
+static const uint8_t PUSH_BUTTON = 17;
+static const uint8_t SLIDE_SWITCH = 16;
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/heltec_capsule_sensor_v3/partitions.csv b/variants/heltec_capsule_sensor_v3/partitions.csv
new file mode 100644
index 00000000000..b363a417de0
--- /dev/null
+++ b/variants/heltec_capsule_sensor_v3/partitions.csv
@@ -0,0 +1,10 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+nvs,      data, nvs,     0x009000, 0x005000,
+otadata,  data, ota,     0x00e000, 0x002000,
+app,      app,  ota_0,   0x010000, 0x250000,
+flashApp, app,  ota_1,   0x260000, 0x0A0000,
+spiffs,   data, spiffs,  0x300000, 0x100000,
+factory,  app,  factory, 0x400000, 0x100000,
+secondApp,app,  ota_2,   0x500000, 0x2D0000,
+key_data, 0x40, 0x00,    0x7D0000, 0x020000,
+coredump, data, coredump,0x7F0000,0x10000,
diff --git a/variants/heltec_capsule_sensor_v3/pins_arduino.h b/variants/heltec_capsule_sensor_v3/pins_arduino.h
new file mode 100644
index 00000000000..2a74e055599
--- /dev/null
+++ b/variants/heltec_capsule_sensor_v3/pins_arduino.h
@@ -0,0 +1,85 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define HELTEC_CAPSULE_SENSOR_V3 true
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+// Some boards have too low voltage on this pin (board design bug)
+// Use different pin with 3V and connect with 48
+// and change this setup for the chosen pin (for example 38)
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 41;
+static const uint8_t SCL = 42;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 21;
+static const uint8_t LED0 = 33;
+static const uint8_t LED1 = 34;
+static const uint8_t USER_BUTTON = 18;
+
+static const uint8_t GPS_RX_PIN = 5;
+static const uint8_t GPS_TX_PIN = 4;
+static const uint8_t GPS_RESET_PIN = 3;
+static const uint8_t GPS_PPS_PIN = 1;
+
+static const uint8_t ADC_BATTERY_PIN = 7;
+static const uint8_t ADC_BATTERY_CTRL_PIN = 36;
+
+static const uint8_t RST_LoRa = 12;
+static const uint8_t BUSY_LoRa = 13;
+static const uint8_t DIO0 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_ht_de01/pins_arduino.h b/variants/heltec_ht_de01/pins_arduino.h
new file mode 100644
index 00000000000..59692741e10
--- /dev/null
+++ b/variants/heltec_ht_de01/pins_arduino.h
@@ -0,0 +1,70 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define HT_DE01 true
+
+static const uint8_t LED_BUILTIN = 35;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 45;
+static const uint8_t LED = 18;
+static const uint8_t RST_EINK = 6;
+static const uint8_t BUSY_EINK = 7;
+static const uint8_t CLK_EINK = 3;
+static const uint8_t CS_EINK = 5;
+static const uint8_t DC_EINK = 4;
+static const uint8_t SDI_EINK = 2;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_vision_master_e290/pins_arduino.h b/variants/heltec_vision_master_e290/pins_arduino.h
new file mode 100644
index 00000000000..7940cdde702
--- /dev/null
+++ b/variants/heltec_vision_master_e290/pins_arduino.h
@@ -0,0 +1,72 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define Vision_Master_E290 true
+#define DISPLAY_HEIGHT     128
+#define DISPLAY_WIDTH      296
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 39;
+static const uint8_t SCL = 38;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 18;
+static const uint8_t Eink_SDI = 1;
+static const uint8_t Eink_CLK = 2;
+static const uint8_t Eink_CS = 3;
+static const uint8_t Eink_DC = 4;
+static const uint8_t Eink_RST = 5;
+static const uint8_t Eink_BUSY = 6;
+
+static const uint8_t RST_LoRa = 12;
+static const uint8_t BUSY_LoRa = 13;
+static const uint8_t DIO0 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_vision_master_e_213/pins_arduino.h b/variants/heltec_vision_master_e_213/pins_arduino.h
new file mode 100644
index 00000000000..003528f9cc0
--- /dev/null
+++ b/variants/heltec_vision_master_e_213/pins_arduino.h
@@ -0,0 +1,72 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define Vision_Master_E213 true
+#define DISPLAY_HEIGHT     122
+#define DISPLAY_WIDTH      250
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 39;
+static const uint8_t SCL = 38;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 18;
+static const uint8_t Eink_BUSY = 1;
+static const uint8_t Eink_DC = 2;
+static const uint8_t Eink_RST = 3;
+static const uint8_t Eink_CLK = 4;
+static const uint8_t Eink_CS = 5;
+static const uint8_t Eink_SDI = 6;
+
+static const uint8_t RST_LoRa = 12;
+static const uint8_t BUSY_LoRa = 13;
+static const uint8_t DIO0 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_vision_master_t190/pins_arduino.h b/variants/heltec_vision_master_t190/pins_arduino.h
new file mode 100644
index 00000000000..6c5fbf907e1
--- /dev/null
+++ b/variants/heltec_vision_master_t190/pins_arduino.h
@@ -0,0 +1,71 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define Vision_Master_T190 true
+#define DISPLAY_HEIGHT     170
+#define DISPLAY_WIDTH      320
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 2;
+static const uint8_t SCL = 1;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 5;
+static const uint8_t TFT_SCL = 38;
+static const uint8_t TFT_CS = 39;
+static const uint8_t TFT_RST = 40;
+static const uint8_t TFT_RS = 47;
+static const uint8_t TFT_SDA = 48;
+
+static const uint8_t RST_LoRa = 12;
+static const uint8_t BUSY_LoRa = 13;
+static const uint8_t DIO0 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wifi_kit_32/pins_arduino.h b/variants/heltec_wifi_kit_32/pins_arduino.h
index 1409535e823..0bac8faf7d6 100644
--- a/variants/heltec_wifi_kit_32/pins_arduino.h
+++ b/variants/heltec_wifi_kit_32/pins_arduino.h
@@ -3,21 +3,15 @@
 
 #include <stdint.h>
 
-#define WIFI_Kit_32	true
+#define WIFI_Kit_32    true
 #define DISPLAY_HEIGHT 64
 #define DISPLAY_WIDTH  128
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
+#define F_XTAL_MHZ 26
 
 static const uint8_t LED_BUILTIN = 25;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -27,10 +21,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A1 = 37;
@@ -67,7 +61,7 @@ static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
 
 static const uint8_t Vext = 21;
-static const uint8_t LED  = 25;
+static const uint8_t LED = 25;
 static const uint8_t RST_OLED = 16;
 static const uint8_t SCL_OLED = 15;
 static const uint8_t SDA_OLED = 4;
diff --git a/variants/heltec_wifi_kit_32_V3/pins_arduino.h b/variants/heltec_wifi_kit_32_V3/pins_arduino.h
new file mode 100644
index 00000000000..94c35573ace
--- /dev/null
+++ b/variants/heltec_wifi_kit_32_V3/pins_arduino.h
@@ -0,0 +1,71 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define WIFI_Kit_32_V3 true
+#define DISPLAY_HEIGHT 64
+#define DISPLAY_WIDTH  128
+
+static const uint8_t LED_BUILTIN = 35;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 36;
+static const uint8_t LED = 35;
+static const uint8_t RST_OLED = 21;
+static const uint8_t SCL_OLED = 18;
+static const uint8_t SDA_OLED = 17;
+
+static const uint8_t DIO0 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wifi_lora_32/pins_arduino.h b/variants/heltec_wifi_lora_32/pins_arduino.h
index b65e50becae..d4e78df4b23 100644
--- a/variants/heltec_wifi_lora_32/pins_arduino.h
+++ b/variants/heltec_wifi_lora_32/pins_arduino.h
@@ -3,21 +3,15 @@
 
 #include <stdint.h>
 
-#define WIFI_LoRa_32
+#define WIFI_LoRa_32   true
 #define DISPLAY_HEIGHT 64
 #define DISPLAY_WIDTH  128
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
+#define F_XTAL_MHZ 26
 
 static const uint8_t LED_BUILTIN = 25;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -27,10 +21,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 18;
-static const uint8_t MOSI  = 27;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 5;
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 27;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -63,8 +57,8 @@ static const uint8_t T9 = 32;
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
 
-static const uint8_t Vext  = 21;
-static const uint8_t LED  = 25;
+static const uint8_t Vext = 21;
+static const uint8_t LED = 25;
 static const uint8_t RST_OLED = 16;
 static const uint8_t SCL_OLED = 15;
 static const uint8_t SDA_OLED = 4;
@@ -73,5 +67,4 @@ static const uint8_t DIO0 = 26;
 static const uint8_t DIO1 = 33;
 static const uint8_t DIO2 = 32;
 
-
 #endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wifi_lora_32_V2/pins_arduino.h b/variants/heltec_wifi_lora_32_V2/pins_arduino.h
index 4d091dabec4..7ddca80cb3c 100644
--- a/variants/heltec_wifi_lora_32_V2/pins_arduino.h
+++ b/variants/heltec_wifi_lora_32_V2/pins_arduino.h
@@ -3,21 +3,13 @@
 
 #include <stdint.h>
 
-#define WIFI_LoRa_32_V2
-#define DISPLAY_HEIGHT 64
-#define DISPLAY_WIDTH  128
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
+#define WIFI_LoRa_32_V2 true
+#define DISPLAY_HEIGHT  64
+#define DISPLAY_WIDTH   128
 
 static const uint8_t LED_BUILTIN = 25;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -27,10 +19,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 18;
-static const uint8_t MOSI  = 27;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 5;
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 27;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -64,7 +56,7 @@ static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
 
 static const uint8_t Vext = 21;
-static const uint8_t LED  = 25;
+static const uint8_t LED = 25;
 static const uint8_t RST_OLED = 16;
 static const uint8_t SCL_OLED = 15;
 static const uint8_t SDA_OLED = 4;
@@ -73,5 +65,4 @@ static const uint8_t DIO0 = 26;
 static const uint8_t DIO1 = 35;
 static const uint8_t DIO2 = 34;
 
-
 #endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wifi_lora_32_V3/pins_arduino.h b/variants/heltec_wifi_lora_32_V3/pins_arduino.h
new file mode 100644
index 00000000000..031bc0e49db
--- /dev/null
+++ b/variants/heltec_wifi_lora_32_V3/pins_arduino.h
@@ -0,0 +1,74 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define WIFI_LoRa_32_V3 true
+#define DISPLAY_HEIGHT  64
+#define DISPLAY_WIDTH   128
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = 35;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 41;
+static const uint8_t SCL = 42;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 36;
+static const uint8_t LED = 35;
+static const uint8_t RST_OLED = 21;
+static const uint8_t SCL_OLED = 18;
+static const uint8_t SDA_OLED = 17;
+
+static const uint8_t RST_LoRa = 12;
+static const uint8_t BUSY_LoRa = 13;
+static const uint8_t DIO0 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wireless_bridge/pins_arduino.h b/variants/heltec_wireless_bridge/pins_arduino.h
new file mode 100644
index 00000000000..e5cbf324986
--- /dev/null
+++ b/variants/heltec_wireless_bridge/pins_arduino.h
@@ -0,0 +1,31 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define WIRELESS_BRIDGE true
+
+static const uint8_t LED_BUILTIN = 25;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 27;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
+
+static const uint8_t Vext = 21;
+static const uint8_t LED = 25;
+static const uint8_t BLE_LED = 25;
+static const uint8_t WIFI_LED = 23;
+static const uint8_t LoRa_LED = 22;
+static const uint8_t RST_LoRa = 14;
+static const uint8_t DIO0 = 26;
+static const uint8_t DIO1 = 35;
+static const uint8_t DIO2 = 34;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wireless_mini_shell/pins_arduino.h b/variants/heltec_wireless_mini_shell/pins_arduino.h
new file mode 100644
index 00000000000..05675eeb9e4
--- /dev/null
+++ b/variants/heltec_wireless_mini_shell/pins_arduino.h
@@ -0,0 +1,33 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define WIRELESS_MINI_SHELL true
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 8;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wireless_paper/pins_arduino.h b/variants/heltec_wireless_paper/pins_arduino.h
new file mode 100644
index 00000000000..727148b3350
--- /dev/null
+++ b/variants/heltec_wireless_paper/pins_arduino.h
@@ -0,0 +1,69 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define WIRELESS_PAPER true
+#define DISPLAY_HEIGHT 64
+#define DISPLAY_WIDTH  128
+
+static const uint8_t LED_BUILTIN = 35;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 45;
+static const uint8_t LED = 18;
+static const uint8_t RST_OLED = 21;
+static const uint8_t SCL_OLED = 18;
+static const uint8_t SDA_OLED = 17;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wireless_shell_v3/pins_arduino.h b/variants/heltec_wireless_shell_v3/pins_arduino.h
new file mode 100644
index 00000000000..72eccd04548
--- /dev/null
+++ b/variants/heltec_wireless_shell_v3/pins_arduino.h
@@ -0,0 +1,77 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+//#include "soc/soc_caps.h"
+
+#define HELTEC_WIRELESS_SHELL_V3 true
+#define DISPLAY_HEIGHT           0
+#define DISPLAY_WIDTH            0
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = 35;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+//static const uint8_t SDA = 41;
+//static const uint8_t SCL = 42;
+static const uint8_t SDA = 2;
+static const uint8_t SCL = 3;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 36;
+static const uint8_t LED = 35;
+static const uint8_t RST_OLED = 21;
+static const uint8_t SCL_OLED = 18;
+static const uint8_t SDA_OLED = 17;
+
+static const uint8_t RST_LoRa = 12;
+static const uint8_t BUSY_LoRa = 13;
+static const uint8_t DIO0 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wireless_stick/pins_arduino.h b/variants/heltec_wireless_stick/pins_arduino.h
index 11e028d9f1c..3bebf0706e6 100644
--- a/variants/heltec_wireless_stick/pins_arduino.h
+++ b/variants/heltec_wireless_stick/pins_arduino.h
@@ -3,21 +3,13 @@
 
 #include <stdint.h>
 
-#define Wireless_Stick
+#define Wireless_Stick true
 #define DISPLAY_HEIGHT 32
 #define DISPLAY_WIDTH  64
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 25;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -27,10 +19,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 18;
-static const uint8_t MOSI  = 27;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 5;
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 27;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -64,7 +56,7 @@ static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
 
 static const uint8_t Vext = 21;
-static const uint8_t LED  = 25;
+static const uint8_t LED = 25;
 static const uint8_t RST_OLED = 16;
 static const uint8_t SCL_OLED = 15;
 static const uint8_t SDA_OLED = 4;
diff --git a/variants/heltec_wireless_stick_V1/pins_arduino.h b/variants/heltec_wireless_stick_V1/pins_arduino.h
new file mode 100644
index 00000000000..5f9f85f9368
--- /dev/null
+++ b/variants/heltec_wireless_stick_V1/pins_arduino.h
@@ -0,0 +1,68 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define Wireless_Stick true
+#define DISPLAY_HEIGHT 32
+#define DISPLAY_WIDTH  64
+
+static const uint8_t LED_BUILTIN = 25;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 27;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t Vext = 21;
+static const uint8_t LED = 25;
+static const uint8_t RST_OLED = 16;
+static const uint8_t SCL_OLED = 15;
+static const uint8_t SDA_OLED = 4;
+static const uint8_t RST_LoRa = 14;
+static const uint8_t DIO0 = 26;
+static const uint8_t DIO1 = 33;
+static const uint8_t DIO2 = 32;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wireless_stick_lite/pins_arduino.h b/variants/heltec_wireless_stick_lite/pins_arduino.h
new file mode 100644
index 00000000000..f5b4a5f82be
--- /dev/null
+++ b/variants/heltec_wireless_stick_lite/pins_arduino.h
@@ -0,0 +1,65 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define Wireless_Stick_Lite true
+#define DISPLAY_HEIGHT      0
+#define DISPLAY_WIDTH       0
+
+static const uint8_t LED_BUILTIN = 25;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 27;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t Vext = 21;
+static const uint8_t LED = 25;
+static const uint8_t RST_LoRa = 14;
+static const uint8_t DIO0 = 26;
+static const uint8_t DIO1 = 35;
+static const uint8_t DIO2 = 34;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wireless_stick_lite_v3/pins_arduino.h b/variants/heltec_wireless_stick_lite_v3/pins_arduino.h
new file mode 100644
index 00000000000..8882fccd45c
--- /dev/null
+++ b/variants/heltec_wireless_stick_lite_v3/pins_arduino.h
@@ -0,0 +1,59 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define Wireless_Stick_Lite_V3 true
+#define DISPLAY_HEIGHT         0
+#define DISPLAY_WIDTH          0
+
+static const uint8_t LED_BUILTIN = 35;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 2;
+static const uint8_t SCL = 3;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 12;
+static const uint8_t A8 = 14;
+static const uint8_t A9 = 15;
+static const uint8_t A10 = 16;
+static const uint8_t A11 = 17;
+static const uint8_t A12 = 18;
+static const uint8_t A13 = 19;
+static const uint8_t A14 = 20;
+
+static const uint8_t T0 = 1;
+static const uint8_t T1 = 2;
+static const uint8_t T2 = 3;
+static const uint8_t T3 = 4;
+static const uint8_t T4 = 5;
+static const uint8_t T5 = 6;
+static const uint8_t T6 = 7;
+
+static const uint8_t Vext = 36;
+static const uint8_t LED = 35;
+static const uint8_t RST_OLED = 21;
+static const uint8_t SCL_OLED = 18;
+static const uint8_t SDA_OLED = 17;
+
+static const uint8_t RST_LoRa = 12;
+static const uint8_t BUSY_LoRa = 13;
+static const uint8_t DIO0 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wireless_stick_v3/pins_arduino.h b/variants/heltec_wireless_stick_v3/pins_arduino.h
new file mode 100644
index 00000000000..6a553950afc
--- /dev/null
+++ b/variants/heltec_wireless_stick_v3/pins_arduino.h
@@ -0,0 +1,81 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define WIRELESS_STICK_V3 true
+
+#define DISPLAY_HEIGHT 32
+#define DISPLAY_WIDTH  64
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+// Some boards have too low voltage on this pin (board design bug)
+// Use different pin with 3V and connect with 48
+// and change this setup for the chosen pin (for example 38)
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 41;
+static const uint8_t SCL = 42;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 36;
+static const uint8_t LED = 35;
+static const uint8_t RST_OLED = 21;
+static const uint8_t SCL_OLED = 18;
+static const uint8_t SDA_OLED = 17;
+
+static const uint8_t RST_LoRa = 12;
+static const uint8_t BUSY_LoRa = 13;
+static const uint8_t DIO0 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/heltec_wireless_tracker/pins_arduino.h b/variants/heltec_wireless_tracker/pins_arduino.h
new file mode 100644
index 00000000000..08c2ce2051b
--- /dev/null
+++ b/variants/heltec_wireless_tracker/pins_arduino.h
@@ -0,0 +1,71 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+// Some boards have too low voltage on this pin (board design bug)
+// Use different pin with 3V and connect with 48
+// and change this setup for the chosen pin (for example 38)
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 41;
+static const uint8_t SCL = 42;
+
+static const uint8_t SS = 8;
+static const uint8_t MOSI = 10;
+static const uint8_t MISO = 11;
+static const uint8_t SCK = 9;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t Vext = 3;
+static const uint8_t LED = 18;
+static const uint8_t RST_OLED = 39;
+static const uint8_t SCL_OLED = 41;
+static const uint8_t SDA_OLED = 42;
+#endif /* Pins_Arduino_h */
diff --git a/variants/honeylemon/pins_arduino.h b/variants/honeylemon/pins_arduino.h
index 04f62911883..567989a3c90 100644
--- a/variants/honeylemon/pins_arduino.h
+++ b/variants/honeylemon/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        38
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t BUILTIN_KEY = 0;
 
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/hornbill32dev/pins_arduino.h b/variants/hornbill32dev/pins_arduino.h
index a01aa4e42a3..0bd626ab7ef 100644
--- a/variants/hornbill32dev/pins_arduino.h
+++ b/variants/hornbill32dev/pins_arduino.h
@@ -3,40 +3,32 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 13;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
 static const uint8_t TX = 1;
-static const uint8_t RX = 3;  
-
-static const uint8_t SDA = 21;  
-static const uint8_t SCL = 22; 
-
-static const uint8_t SS    = 5; 
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18; 
-
-static const uint8_t A0 = 36; 
-static const uint8_t A3 = 39; 
-static const uint8_t A4 = 32; 
-static const uint8_t A5 = 33;  
-static const uint8_t A6 = 34;  
-static const uint8_t A7 = 35;  
-static const uint8_t A10 = 4;  
-static const uint8_t A11 = 0;  
-static const uint8_t A12 = 2;  
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
 static const uint8_t A13 = 15;
 static const uint8_t A14 = 13;
 static const uint8_t A15 = 12;
@@ -45,8 +37,8 @@ static const uint8_t A17 = 27;
 static const uint8_t A18 = 25;
 static const uint8_t A19 = 26;
 
-static const uint8_t T0 = 4;  
-static const uint8_t T1 = 0;  
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
 static const uint8_t T2 = 2;
 static const uint8_t T3 = 15;
 static const uint8_t T4 = 13;
@@ -56,7 +48,7 @@ static const uint8_t T7 = 27;
 static const uint8_t T8 = 33;
 static const uint8_t T9 = 32;
 
-static const uint8_t DAC1 = 25;  
-static const uint8_t DAC2 = 26;  
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/hornbill32minima/pins_arduino.h b/variants/hornbill32minima/pins_arduino.h
index d18c4dacd58..74ecf87cb6c 100644
--- a/variants/hornbill32minima/pins_arduino.h
+++ b/variants/hornbill32minima/pins_arduino.h
@@ -3,47 +3,31 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;  //taken out on pgm header
 static const uint8_t RX = 3;  //taken out on pgm header
 
 static const uint8_t SDA = 21;  //1
 static const uint8_t SCL = 22;  //2
 
-static const uint8_t SS    = 2; //3
-static const uint8_t MOSI  = 23; //4
-static const uint8_t MISO  = 19; //5	
-static const uint8_t SCK   = 18; //6
-
-
-
-static const uint8_t A6 = 34;  //7
-static const uint8_t A7 = 35;  //8 
-static const uint8_t A10 = 4;  //9
-static const uint8_t A11 = 0;  // taken out on pgm header
-static const uint8_t A12 = 2;  // with SPI SS
-static const uint8_t A13 = 15; //10
-static const uint8_t A14 = 13; //11
-
+static const uint8_t SS = 2;     //3
+static const uint8_t MOSI = 23;  //4
+static const uint8_t MISO = 19;  //5
+static const uint8_t SCK = 18;   //6
 
+static const uint8_t A6 = 34;   //7
+static const uint8_t A7 = 35;   //8
+static const uint8_t A10 = 4;   //9
+static const uint8_t A11 = 0;   // taken out on pgm header
+static const uint8_t A12 = 2;   // with SPI SS
+static const uint8_t A13 = 15;  //10
+static const uint8_t A14 = 13;  //11
 
 static const uint8_t DAC1 = 25;  //12
 static const uint8_t DAC2 = 26;  //13
 
-
-static const uint8_t T0 = 4;  //used
-static const uint8_t T1 = 0;  // taken out on pgm header
-static const uint8_t T2 = 2;  //used
-static const uint8_t T3 = 15; //used
-
-
-
+static const uint8_t T0 = 4;   //used
+static const uint8_t T1 = 0;   // taken out on pgm header
+static const uint8_t T2 = 2;   //used
+static const uint8_t T3 = 15;  //used
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/huidu_hd_wf2/pins_arduino.h b/variants/huidu_hd_wf2/pins_arduino.h
new file mode 100644
index 00000000000..6068e4d6371
--- /dev/null
+++ b/variants/huidu_hd_wf2/pins_arduino.h
@@ -0,0 +1,61 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// Huidu HD-WF2 - esp32-s3 HUB75 driver board
+// https://www.hdwell.com/Product/index46.html
+// https://github.com/mrcodetastic/ESP32-HUB75-MatrixPanel-DMA/discussions/667
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+#define WF2_X1_R1_PIN 2
+#define WF2_X1_R2_PIN 3
+#define WF2_X1_G1_PIN 6
+#define WF2_X1_G2_PIN 7
+#define WF2_X1_B1_PIN 10
+#define WF2_X1_B2_PIN 11
+#define WF2_X1_E_PIN  21
+
+#define WF2_X2_R1_PIN 4
+#define WF2_X2_R2_PIN 5
+#define WF2_X2_G1_PIN 8
+#define WF2_X2_G2_PIN 9
+#define WF2_X2_B1_PIN 12
+#define WF2_X2_B2_PIN 13
+#define WF2_X2_E_PIN  -1  // Currently unknown, so X2 port will not work (yet) with 1/32 scan panels
+
+#define WF2_A_PIN   39
+#define WF2_B_PIN   38
+#define WF2_C_PIN   37
+#define WF2_D_PIN   36
+#define WF2_OE_PIN  35
+#define WF2_CLK_PIN 34
+#define WF2_LAT_PIN 33
+
+#define WF2_BUTTON_TEST    17  // Test key button on PCB, 1=normal, 0=pressed
+#define WF2_LED_RUN_PIN    40  // Status LED on PCB
+#define WF2_BM8563_I2C_SDA 41  // RTC BM8563 I2C port
+#define WF2_BM8563_I2C_SCL 42
+#define WF2_USB_DN_PIN     19  // USB D-
+#define WF2_USB_DP_PIN     20  // USB D+
+
+#define WF2_PCB1_PIN 45  // open pad on PCB
+#define WF2_PCB2_PIN 46  // open pad on PCB
+
+#define LED_BUILTIN WF2_LED_RUN_PIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = WF2_BM8563_I2C_SDA;
+static const uint8_t SCL = WF2_BM8563_I2C_SCL;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/huidu_hd_wf4/pins_arduino.h b/variants/huidu_hd_wf4/pins_arduino.h
new file mode 100644
index 00000000000..5b8667477bf
--- /dev/null
+++ b/variants/huidu_hd_wf4/pins_arduino.h
@@ -0,0 +1,111 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// Huidu HD-WF4 - esp32-s3 HUB75 driver board
+// https://www.hdwell.com/Product/index46.html
+// https://github.com/mrcodetastic/ESP32-HUB75-MatrixPanel-DMA/discussions/667
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+#define WF4_A_PIN   39
+#define WF4_B_PIN   38
+#define WF4_C_PIN   37
+#define WF4_D_PIN   36
+#define WF4_E_PIN   21
+#define WF4_OE_PIN  35
+#define WF4_CLK_PIN 34
+#define WF4_LAT_PIN 33
+
+// X1 HUB75
+#define WF4_X1_R1_PIN 2
+#define WF4_X1_R2_PIN 3
+#define WF4_X1_G1_PIN 6
+#define WF4_X1_G2_PIN 7
+#define WF4_X1_B1_PIN 10
+#define WF4_X1_B2_PIN 11
+#define WF4_X1_CS_PIN 45  // CS gpio must be set HIGH to enable X1 output
+
+// X2 HUB75
+#define WF4_X2_R1_PIN 4
+#define WF4_X2_R2_PIN 5
+#define WF4_X2_G1_PIN 8
+#define WF4_X2_G2_PIN 9
+#define WF4_X2_B1_PIN 12
+#define WF4_X2_B2_PIN 13
+#define WF4_X2_CS_PIN WF4_X1_CS_PIN  // CS gpio must be set HIGH to enable X2 output
+
+// X3 HUB75
+#define WF4_X3_R1_PIN 2
+#define WF4_X3_R2_PIN 3
+#define WF4_X3_G1_PIN 6
+#define WF4_X3_G2_PIN 7
+#define WF4_X3_B1_PIN 10
+#define WF4_X3_B2_PIN 11
+#define WF4_X3_CS_PIN 14  // CS gpio must be set HIGH to enable X3 output
+
+// X4 HUB75
+#define WF4_X4_R1_PIN 4
+#define WF4_X4_R2_PIN 5
+#define WF4_X4_G1_PIN 8
+#define WF4_X4_G2_PIN 9
+#define WF4_X4_B1_PIN 12
+#define WF4_X4_B2_PIN 13
+#define WF4_X4_CS_PIN WF4_X3_CS_PIN  // CS gpio must be set HIGH to enable X4 output
+
+// P1 is a UART connector
+#define WF4_P1_RX_PIN 44
+#define WF4_P1_TX_PIN 43
+
+// P2: PCB holes gpio/gnd
+#define WF4_P2_DATA_PIN 0  // GPIO0 boot
+
+// P5: temperature sensor connector
+#define WF4_P5_DATA_PIN 16
+
+// P7: VCC/GPIO holes on PCB
+#define WF4_P7_DATA_PIN 1
+
+// P11: IR connector
+#define WF4_P11_DATA_PIN 15
+
+// P12: two gpio's, Vcc, GND
+#define WF4_P12_DATA1_PIN 47
+#define WF4_P12_DATA2_PIN 18
+
+// S1 Button
+#define WF4_S1_DATA_PIN 17
+
+// S2-S3 PCB holes
+#define WF4_S2_DATA_PIN 48
+#define WF4_S3_DATA_PIN 26
+#define WF4_S4_DATA_PIN 46
+
+#define WF4_BUTTON_TEST    WF4_S1_PIN  // Test key button on PCB, 1=normal, 0=pressed
+#define WF4_LED_RUN_PIN    40          // Status LED on PCB
+#define WF4_BM8563_I2C_SDA 41          // RTC BM8563 I2C port
+#define WF4_BM8563_I2C_SCL 42
+#define WF4_USB_DN_PIN     19  // USB-A D-
+#define WF4_USB_DP_PIN     20  // USB-A D+
+
+#define LED_BUILTIN WF4_LED_RUN_PIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+static const uint8_t TX = WF4_P1_TX_PIN;
+static const uint8_t RX = WF4_P1_RX_PIN;
+
+static const uint8_t SDA = WF4_BM8563_I2C_SDA;
+static const uint8_t SCL = WF4_BM8563_I2C_SCL;
+
+// there is no dedicated SPI connector on board, but SPI could be accessed via PCB holes
+static const uint8_t SS = WF4_S2_DATA_PIN;
+static const uint8_t MOSI = WF4_S3_DATA_PIN;
+static const uint8_t MISO = WF4_S4_DATA_PIN;
+static const uint8_t SCK = WF4_P7_DATA_PIN;
+
+// touch pins are mostly busy with HUB75 ports
+static const uint8_t T1 = WF4_P7_DATA_PIN;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/imbrios-logsens-v1p1/pins_arduino.h b/variants/imbrios-logsens-v1p1/pins_arduino.h
index 8e90770cf10..bece598cf43 100644
--- a/variants/imbrios-logsens-v1p1/pins_arduino.h
+++ b/variants/imbrios-logsens-v1p1/pins_arduino.h
@@ -3,41 +3,34 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        9
-#define NUM_ANALOG_INPUTS       7
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 // Renaming few signals
-#define SPI_CLK	SCK			// IO14
-#define SPI_MISO	MISO			// IO12
-#define SPI_MOSI	MOSI			// IO13
-#define SPI_CS0	SS			// IO15, Default SPI CS: Extension Header, Pin_3
-#define SD_SPI_CS1	SPI_CS1		// SPI Chip Select: MicroSD Card
-#define LED_WIFI_LINK	LED1_BUILDIN		// LED6 on the LogSens V1.1 Board
-#define LED_WIFI_ACT	LED2_BUILDIN		// LED7 on the LogSens V1.1 Board\
+#define SPI_CLK       SCK           // IO14
+#define SPI_MISO      MISO          // IO12
+#define SPI_MOSI      MOSI          // IO13
+#define SPI_CS0       SS            // IO15, Default SPI CS: Extension Header, Pin_3
+#define SD_SPI_CS1    SPI_CS1       // SPI Chip Select: MicroSD Card
+#define LED_WIFI_LINK LED1_BUILDIN  // LED6 on the LogSens V1.1 Board
+#define LED_WIFI_ACT \
+  LED2_BUILDIN  // LED7 on the LogSens V1.1 Board\
 
 /* LED_BUILTIN is kept for compatibility reason; mapped to LED2 on the LogSens V1.1 Board */
 static const uint8_t LED_BUILTIN = 33;
-#define BUILTIN_LED  LED_BUILTIN 	// backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 /* UART0: Serial Port for Programming and Debugging on the LogSens V1.1 Board */
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 #ifdef BOARD_VARIANT_RS485
-/* UART2: Serial Port conencted to RS485 transceiver on the LogSens V1.1 Board */
+/* UART2: Serial Port connected to RS485 transceiver on the LogSens V1.1 Board */
 static const uint8_t UART2_TX = 17;
 static const uint8_t UART2_RX = 16;
 static const uint8_t UART2_RTS = 4;
 #endif /* BOARD_VARIANT_RS485 */
 
 #ifdef BOARD_VARIANT_CAN
-/* CAN Bus conencted to CAN transceiver on the LogSens V1.1 Board */
+/* CAN Bus connected to CAN transceiver on the LogSens V1.1 Board */
 static const uint8_t CAN_TX = 17;
 static const uint8_t CAN_RX = 16;
 static const uint8_t CAN_TXDE = 4;
@@ -48,24 +41,23 @@ static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
 /* SPI Bus: Shared between MicroSD Card (X6) and Expansion Header (X3) */
-static const uint8_t SS    = 15;		// SPI Chip Select - 0; Connected to Extension Header, Pin_3  on the LogSens V1.1 Board
-static const uint8_t MOSI  = 13;
-static const uint8_t MISO  = 12;
-static const uint8_t SCK   = 14;
+static const uint8_t SS = 15;  // SPI Chip Select - 0; Connected to Extension Header, Pin_3  on the LogSens V1.1 Board
+static const uint8_t MOSI = 13;
+static const uint8_t MISO = 12;
+static const uint8_t SCK = 14;
 
-static const uint8_t SPI_SS1  = 23;		// SPI Chip Select - 1; connected to MicroSD Card on the LogSens V1.1 Board
-  
-/* Software Controlled: IO, LEDs and Switches */
-static const uint8_t BUZZER_CTRL = 19;		// Signal connected to MOSFET gate pin to control conenctor (X8)
-static const uint8_t SD_CARD_DETECT = 35; 	// MicroSD Card (X6): Card Detect Signal
+static const uint8_t SS1 = 23;  // SPI Chip Select - 1; connected to MicroSD Card on the LogSens V1.1 Board
 
-static const uint8_t SW2_BUILDIN = 0;		// Tactile Switch-2 (SW2); ESP32 BOOT0 pin, Use it with care !!
-static const uint8_t SW3_BUILDIN = 36;		// Tactile Switch-3 (SW3) 
-static const uint8_t SW4_BUILDIN = 34;		// Tactile Switch-4 (SW4)
+/* Software Controlled: IO, LEDs and Switches */
+static const uint8_t BUZZER_CTRL = 19;     // Signal connected to MOSFET gate pin to control connector (X8)
+static const uint8_t SD_CARD_DETECT = 35;  // MicroSD Card (X6): Card Detect Signal
 
-static const uint8_t LED1_BUILDIN = 32;	// Connected to LogSens V1.1: LED6 		
-static const uint8_t LED2_BUILDIN = 33;	// Connected to LogSens V1.1: LED7
+static const uint8_t SW2_BUILDIN = 0;   // Tactile Switch-2 (SW2); ESP32 BOOT0 pin, Use it with care !!
+static const uint8_t SW3_BUILDIN = 36;  // Tactile Switch-3 (SW3)
+static const uint8_t SW4_BUILDIN = 34;  // Tactile Switch-4 (SW4)
 
+static const uint8_t LED1_BUILDIN = 32;  // Connected to LogSens V1.1: LED6
+static const uint8_t LED2_BUILDIN = 33;  // Connected to LogSens V1.1: LED7
 
 /* Analog Input Channels accessible on the LogSens V1.1 Board */
 //static const uint8_t A0 = 36;
diff --git a/variants/intorobot-fig/pins_arduino.h b/variants/intorobot-fig/pins_arduino.h
index a48f328d833..d6a13496a78 100644
--- a/variants/intorobot-fig/pins_arduino.h
+++ b/variants/intorobot-fig/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        7
-#define NUM_ANALOG_INPUTS       10
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 4;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t RGB_R_BUILTIN = 27;
 static const uint8_t RGB_G_BUILTIN = 21;
@@ -27,10 +19,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 23;
 static const uint8_t SCL = 19;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 16;
-static const uint8_t MISO  = 17;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 16;
+static const uint8_t MISO = 17;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A1 = 39;
diff --git a/variants/ioxesp32/pins_arduino.h b/variants/ioxesp32/pins_arduino.h
new file mode 100644
index 00000000000..bc0d7a1f772
--- /dev/null
+++ b/variants/ioxesp32/pins_arduino.h
@@ -0,0 +1,54 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 5;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/ioxesp32c6/pins_arduino.h b/variants/ioxesp32c6/pins_arduino.h
new file mode 100644
index 00000000000..bcd20119514
--- /dev/null
+++ b/variants/ioxesp32c6/pins_arduino.h
@@ -0,0 +1,35 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_RGB_LED 8
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 20;
+static const uint8_t SCK = 19;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/jczn_2432s028r/partitions_all_app_4MB.csv b/variants/jczn_2432s028r/partitions_all_app_4MB.csv
new file mode 100644
index 00000000000..25eeb8c7d47
--- /dev/null
+++ b/variants/jczn_2432s028r/partitions_all_app_4MB.csv
@@ -0,0 +1,3 @@
+# Name,    Type,  SubType,     Offset,      Size,  Flags
+nvs,       data,  nvs,         0x9000,    0x5000,
+factory,   app,   factory,    0x10000,  0x3F0000,
diff --git a/variants/jczn_2432s028r/partitions_otanofs_4MB.csv b/variants/jczn_2432s028r/partitions_otanofs_4MB.csv
new file mode 100644
index 00000000000..04240badb49
--- /dev/null
+++ b/variants/jczn_2432s028r/partitions_otanofs_4MB.csv
@@ -0,0 +1,6 @@
+#   Name, Type,  SubType,   Offset,      Size, Flags
+     nvs, data,      nvs,   0x9000,    0x5000,
+ otadata, data,      ota,   0xE000,    0x2000,
+    app0,  app,    ota_0,  0x10000,  0x1F0000,
+    app1,  app,    ota_1, 0x200000,  0x1F0000,
+coredump, data, coredump, 0x3F0000,   0x10000,
diff --git a/variants/jczn_2432s028r/pins_arduino.h b/variants/jczn_2432s028r/pins_arduino.h
new file mode 100644
index 00000000000..ba10d0f1fd4
--- /dev/null
+++ b/variants/jczn_2432s028r/pins_arduino.h
@@ -0,0 +1,91 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t D35 = 35;
+static const uint8_t D22 = 22;
+static const uint8_t D27 = 27;
+static const uint8_t D21 = 21;
+
+static const uint8_t A6 = 34;
+static const uint8_t A17 = 27;
+
+static const uint8_t T7 = 27;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+#define CYD_TP_IRQ     36
+#define CYD_TP_MOSI    32
+#define CYD_TP_MISO    39
+#define CYD_TP_CLK     25
+#define CYD_TP_CS      33
+#define CYD_TP_DIN     CYD_TP_MOSI
+#define CYD_TP_OUT     CYD_TP_MOSI
+#define CYD_TP_SPI_BUS VSPI
+
+#define CYD_TFT_DC      2
+#define CYD_TFT_MISO    12
+#define CYD_TFT_MOSI    13
+#define CYD_TFT_SCK     14
+#define CYD_TFT_CS      15
+#define CYD_TFT_RS      CYD_TFT_DC
+#define CYD_TFT_SDO     CYD_TFT_MISO
+#define CYD_TFT_SDI     CYD_TFT_MOSI
+#define CYD_TFT_SPI_BUS HSPI
+
+#define CYD_TFT_WIDTH     320
+#define CYD_TFT_HEIGHT    240
+#define CYD_SCREEN_WIDTH  CYD_TFT_WIDTH
+#define CYD_SCREEN_HEIGHT CYD_TFT_HEIGHT
+
+#define CYD_TFT_BL          21
+#define CYD_TFT_BL_ENABLE() ((pinMode(CYD_TFT_BL, OUTPUT)))
+#define CYD_TFT_BL_OFF()    (digitalWrite(CYD_TFT_BL, 0))
+#define CYD_TFT_BL_ON()     (digitalWrite(CYD_TFT_BL, 1))
+
+#define CYD_LED_RED   4
+#define CYD_LED_GREEN 16
+#define CYD_LED_BLUE  17
+
+#define CYD_AUDIO_OUT 26
+
+#define CYD_USER_BUTTON 0
+
+#define CYD_SD_SS      5
+#define CYD_SD_MOSI    23
+#define CYD_SD_MISO    19
+#define CYD_SD_SCK     18
+#define CYD_SD_SPI_BUS VSPI
+
+#define CYD_LDR 34
+
+#define CYD_LED_RED_OFF()   (digitalWrite(CYD_LED_RED, 1))
+#define CYD_LED_RED_ON()    (digitalWrite(CYD_LED_RED, 0))
+#define CYD_LED_GREEN_OFF() (digitalWrite(CYD_LED_GREEN, 1))
+#define CYD_LED_GREEN_ON()  (digitalWrite(CYD_LED_GREEN, 0))
+#define CYD_LED_BLUE_OFF()  (digitalWrite(CYD_LED_BLUE, 1))
+#define CYD_LED_BLUE_ON()   (digitalWrite(CYD_LED_BLUE, 0))
+#define CYD_LED_RGB_OFF() \
+  CYD_LED_RED_OFF();      \
+  CYD_LED_GREEN_OFF();    \
+  CYD_LED_BLUE_OFF()
+#define CYD_LED_RGB_ON() \
+  CYD_LED_RED_ON();      \
+  CYD_LED_GREEN_ON();    \
+  CYD_LED_BLUE_ON()
+#define CYD_LED_WHITE_OFF() CYD_LED_RGB_OFF()
+#define CYD_LED_WHITE_ON()  CYD_LED_RGB_ON()
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/jczn_2432s028r/variant.cpp b/variants/jczn_2432s028r/variant.cpp
new file mode 100644
index 00000000000..a56fc4c190e
--- /dev/null
+++ b/variants/jczn_2432s028r/variant.cpp
@@ -0,0 +1,13 @@
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  pinMode(CYD_LED_RED, OUTPUT);
+  pinMode(CYD_LED_GREEN, OUTPUT);
+  pinMode(CYD_LED_BLUE, OUTPUT);
+  CYD_LED_RGB_OFF();
+}
+}
diff --git a/variants/lilygo_t3_s3_lr1121/pins_arduino.h b/variants/lilygo_t3_s3_lr1121/pins_arduino.h
new file mode 100644
index 00000000000..70fc3502dab
--- /dev/null
+++ b/variants/lilygo_t3_s3_lr1121/pins_arduino.h
@@ -0,0 +1,67 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x820A
+
+static const uint8_t LED_BUILTIN = 37;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t BUTTON_1 = 0;
+static const uint8_t BAT_VOLT = 1;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 18;
+static const uint8_t SCL = 17;
+
+#define WIRE1_PIN_DEFINED  //QWIIC
+static const uint8_t SDA1 = 10;
+static const uint8_t SCL1 = 21;
+
+// SD Card SPI
+static const uint8_t SS = 13;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 2;
+static const uint8_t SCK = 14;
+
+#define LORA_SCK  5  // LR1121 SCK
+#define LORA_MISO 3  // LR1121 MISO
+#define LORA_MOSI 6  // LR1121 MOSI
+#define LORA_CS   7  // LR1121 CS
+#define LORA_RST  8  // LR1121 RST
+
+#define LORA_DIO9 36  // LR1121 DIO9
+#define LORA_BUSY 34  // LR1121 BUSY
+#define LORA_IRQ  LORA_DIO9
+
+// P1
+static const uint8_t PIN_42 = 45;
+static const uint8_t PIN_46 = 46;
+static const uint8_t PIN_45 = 45;
+static const uint8_t PIN_41 = 41;
+static const uint8_t PIN_40 = 40;
+static const uint8_t PIN_39 = 39;
+static const uint8_t PIN_43 = 43;
+static const uint8_t PIN_44 = 44;
+static const uint8_t PIN_38 = 38;
+
+// P2
+static const uint8_t PIN_37 = 37;
+static const uint8_t PIN_36 = 36;
+static const uint8_t PIN_0 = 0;
+static const uint8_t PIN_35 = 35;
+static const uint8_t PIN_34 = 34;
+static const uint8_t PIN_33 = 33;
+static const uint8_t PIN_47 = 47;
+static const uint8_t PIN_48 = 48;
+static const uint8_t PIN_12 = 12;
+static const uint8_t PIN_8 = 8;
+static const uint8_t PIN_15 = 15;
+static const uint8_t PIN_16 = 16;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_t3_s3_sx1262/pins_arduino.h b/variants/lilygo_t3_s3_sx1262/pins_arduino.h
new file mode 100644
index 00000000000..8fbf0b31066
--- /dev/null
+++ b/variants/lilygo_t3_s3_sx1262/pins_arduino.h
@@ -0,0 +1,67 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x820A
+
+static const uint8_t LED_BUILTIN = 37;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t BUTTON_1 = 0;
+static const uint8_t BAT_VOLT = 1;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 18;
+static const uint8_t SCL = 17;
+
+#define WIRE1_PIN_DEFINED  //QWIIC
+static const uint8_t SDA1 = 10;
+static const uint8_t SCL1 = 21;
+
+// SD Card SPI
+static const uint8_t SS = 13;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 2;
+static const uint8_t SCK = 14;
+
+#define LORA_SCK  5  // SX1262 SCK
+#define LORA_MISO 3  // SX1262 MISO
+#define LORA_MOSI 6  // SX1262 MOSI
+#define LORA_CS   7  // SX1262 CS
+#define LORA_RST  8  // SX1262 RST
+
+#define LORA_DIO1 33  //SX1262 DIO1
+#define LORA_BUSY 34
+#define LORA_IRQ  LORA_DIO1
+
+// P1
+static const uint8_t PIN_42 = 45;
+static const uint8_t PIN_46 = 46;
+static const uint8_t PIN_45 = 45;
+static const uint8_t PIN_41 = 41;
+static const uint8_t PIN_40 = 40;
+static const uint8_t PIN_39 = 39;
+static const uint8_t PIN_43 = 43;
+static const uint8_t PIN_44 = 44;
+static const uint8_t PIN_38 = 38;
+
+// P2
+static const uint8_t PIN_37 = 37;
+static const uint8_t PIN_36 = 36;
+static const uint8_t PIN_0 = 0;
+static const uint8_t PIN_35 = 35;
+static const uint8_t PIN_34 = 34;
+static const uint8_t PIN_33 = 33;
+static const uint8_t PIN_47 = 47;
+static const uint8_t PIN_48 = 48;
+static const uint8_t PIN_12 = 12;
+static const uint8_t PIN_8 = 8;
+static const uint8_t PIN_15 = 15;
+static const uint8_t PIN_16 = 16;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_t3_s3_sx127x/pins_arduino.h b/variants/lilygo_t3_s3_sx127x/pins_arduino.h
new file mode 100644
index 00000000000..1b3e0a99239
--- /dev/null
+++ b/variants/lilygo_t3_s3_sx127x/pins_arduino.h
@@ -0,0 +1,74 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x820A
+
+static const uint8_t LED_BUILTIN = 37;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t BUTTON_1 = 0;
+static const uint8_t BAT_VOLT = 1;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 18;
+static const uint8_t SCL = 17;
+
+#define WIRE1_PIN_DEFINED  //QWIIC
+static const uint8_t SDA1 = 10;
+static const uint8_t SCL1 = 21;
+
+// SD Card SPI
+static const uint8_t SS = 13;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 2;
+static const uint8_t SCK = 14;
+
+#define LORA_SCK  5  // SX1276/SX1278 SCK
+#define LORA_MISO 3  // SX1276/SX1278 MISO
+#define LORA_MOSI 6  // SX1276/SX1278 MOSI
+#define LORA_CS   7  // SX1276/SX1278 CS
+#define LORA_RST  8  // SX1276/SX1278 RST
+
+#define LORA_BUSY 33
+#define LORA_DIO0 9  //IRQ
+#define LORA_DIO1 33
+#define LORA_DIO2 34
+#define LORA_DIO3 21
+#define LORA_DIO4 10
+#define LORA_DIO5 36
+
+#define LORA_IRQ  LORA_DIO0
+#define LORA_BUSY LORA_DIO1
+
+// P1
+static const uint8_t PIN_42 = 45;
+static const uint8_t PIN_46 = 46;
+static const uint8_t PIN_45 = 45;
+static const uint8_t PIN_41 = 41;
+static const uint8_t PIN_40 = 40;
+static const uint8_t PIN_39 = 39;
+static const uint8_t PIN_43 = 43;
+static const uint8_t PIN_44 = 44;
+static const uint8_t PIN_38 = 38;
+
+// P2
+static const uint8_t PIN_37 = 37;
+static const uint8_t PIN_36 = 36;
+static const uint8_t PIN_0 = 0;
+static const uint8_t PIN_35 = 35;
+static const uint8_t PIN_34 = 34;
+static const uint8_t PIN_33 = 33;
+static const uint8_t PIN_47 = 47;
+static const uint8_t PIN_48 = 48;
+static const uint8_t PIN_12 = 12;
+static const uint8_t PIN_8 = 8;
+static const uint8_t PIN_15 = 15;
+static const uint8_t PIN_16 = 16;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_t3_s3_sx1280/pins_arduino.h b/variants/lilygo_t3_s3_sx1280/pins_arduino.h
new file mode 100644
index 00000000000..ba342f3b8e9
--- /dev/null
+++ b/variants/lilygo_t3_s3_sx1280/pins_arduino.h
@@ -0,0 +1,67 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x820A
+
+static const uint8_t LED_BUILTIN = 37;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t BUTTON_1 = 0;
+static const uint8_t BAT_VOLT = 1;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 18;
+static const uint8_t SCL = 17;
+
+#define WIRE1_PIN_DEFINED  //QWIIC
+static const uint8_t SDA1 = 10;
+static const uint8_t SCL1 = 21;
+
+// SD Card SPI
+static const uint8_t SS = 13;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 2;
+static const uint8_t SCK = 14;
+
+#define LORA_SCK  5  // SX1280 SCK
+#define LORA_MISO 3  // SX1280 MISO
+#define LORA_MOSI 6  // SX1280 MOSI
+#define LORA_CS   7  // SX1280 CS
+#define LORA_RST  8  // SX1280 RST
+
+#define LORA_DIO1 9   // SX1280 DIO1
+#define LORA_BUSY 36  // SX1280 BUSY
+#define LORA_IRQ  LORA_DIO1
+
+// P1
+static const uint8_t PIN_42 = 45;
+static const uint8_t PIN_46 = 46;
+static const uint8_t PIN_45 = 45;
+static const uint8_t PIN_41 = 41;
+static const uint8_t PIN_40 = 40;
+static const uint8_t PIN_39 = 39;
+static const uint8_t PIN_43 = 43;
+static const uint8_t PIN_44 = 44;
+static const uint8_t PIN_38 = 38;
+
+// P2
+static const uint8_t PIN_37 = 37;
+static const uint8_t PIN_36 = 36;
+static const uint8_t PIN_0 = 0;
+static const uint8_t PIN_35 = 35;
+static const uint8_t PIN_34 = 34;
+static const uint8_t PIN_33 = 33;
+static const uint8_t PIN_47 = 47;
+static const uint8_t PIN_48 = 48;
+static const uint8_t PIN_12 = 12;
+static const uint8_t PIN_8 = 8;
+static const uint8_t PIN_15 = 15;
+static const uint8_t PIN_16 = 16;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_t3_s3_sx1280pa/pins_arduino.h b/variants/lilygo_t3_s3_sx1280pa/pins_arduino.h
new file mode 100644
index 00000000000..03212754a69
--- /dev/null
+++ b/variants/lilygo_t3_s3_sx1280pa/pins_arduino.h
@@ -0,0 +1,66 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x820A
+
+static const uint8_t LED_BUILTIN = 37;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t BUTTON_1 = 0;
+static const uint8_t BAT_VOLT = 1;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 18;
+static const uint8_t SCL = 17;
+
+// SD Card SPI
+static const uint8_t SS = 13;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 2;
+static const uint8_t SCK = 14;
+
+#define LORA_SCK  5  // SX1280PA SCK
+#define LORA_MISO 3  // SX1280PA MISO
+#define LORA_MOSI 6  // SX1280PA MOSI
+#define LORA_CS   7  // SX1280PA CS
+#define LORA_RST  8  // SX1280PA RST
+
+#define LORA_DIO1 9   // SX1280 DIO1
+#define LORA_BUSY 36  // SX1280 BUSY
+#define LORA_IRQ  LORA_DIO1
+
+#define LORA_RX 21  // SX1280PA RX SWITCH
+#define LORA_TX 10  // SX1280PA TX SWITCH
+
+// P1
+static const uint8_t PIN_42 = 45;
+static const uint8_t PIN_46 = 46;
+static const uint8_t PIN_45 = 45;
+static const uint8_t PIN_41 = 41;
+static const uint8_t PIN_40 = 40;
+static const uint8_t PIN_39 = 39;
+static const uint8_t PIN_43 = 43;
+static const uint8_t PIN_44 = 44;
+static const uint8_t PIN_38 = 38;
+
+// P2
+static const uint8_t PIN_37 = 37;
+static const uint8_t PIN_36 = 36;
+static const uint8_t PIN_0 = 0;
+static const uint8_t PIN_35 = 35;
+static const uint8_t PIN_34 = 34;
+static const uint8_t PIN_33 = 33;
+static const uint8_t PIN_47 = 47;
+static const uint8_t PIN_48 = 48;
+static const uint8_t PIN_12 = 12;
+static const uint8_t PIN_8 = 8;
+static const uint8_t PIN_15 = 15;
+static const uint8_t PIN_16 = 16;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_t_display/pins_arduino.h b/variants/lilygo_t_display/pins_arduino.h
new file mode 100644
index 00000000000..1caeffdfa5f
--- /dev/null
+++ b/variants/lilygo_t_display/pins_arduino.h
@@ -0,0 +1,59 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x1A86
+#define USB_PID          0x55D4
+#define USB_MANUFACTURER "Lilygo"
+#define USB_PRODUCT      "T-Display"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t VBAT = 34;
+
+static const uint8_t RIGHT_BUTTON = 35;
+static const uint8_t LEFT_BUTTON = 0;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_t_display_s3/pins_arduino.h b/variants/lilygo_t_display_s3/pins_arduino.h
new file mode 100644
index 00000000000..8a179e67ef7
--- /dev/null
+++ b/variants/lilygo_t_display_s3/pins_arduino.h
@@ -0,0 +1,82 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t BUTTON_1 = 0;
+static const uint8_t BUTTON_2 = 14;
+static const uint8_t BAT_VOLT = 4;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 18;
+static const uint8_t SCL = 17;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t TP_RESET = 21;
+static const uint8_t TP_INIT = 16;
+
+// ST7789 IPS TFT 170x320
+static const uint8_t LCD_BL = 38;
+static const uint8_t LCD_D0 = 39;
+static const uint8_t LCD_D1 = 40;
+static const uint8_t LCD_D2 = 41;
+static const uint8_t LCD_D3 = 42;
+static const uint8_t LCD_D4 = 45;
+static const uint8_t LCD_D5 = 46;
+static const uint8_t LCD_D6 = 47;
+static const uint8_t LCD_D7 = 48;
+static const uint8_t LCD_WR = 8;
+static const uint8_t LCD_RD = 9;
+static const uint8_t LCD_DC = 7;
+static const uint8_t LCD_CS = 6;
+static const uint8_t LCD_RES = 5;
+static const uint8_t LCD_POWER_ON = 15;
+
+// P1
+static const uint8_t PIN_43 = 43;
+static const uint8_t PIN_44 = 44;
+static const uint8_t PIN_18 = 18;
+static const uint8_t PIN_17 = 17;
+static const uint8_t PIN_21 = 21;
+static const uint8_t PIN_16 = 16;
+
+// P2
+static const uint8_t PIN_1 = 1;
+static const uint8_t PIN_2 = 2;
+static const uint8_t PIN_3 = 3;
+static const uint8_t PIN_10 = 10;
+static const uint8_t PIN_11 = 11;
+static const uint8_t PIN_12 = 12;
+static const uint8_t PIN_13 = 13;
+
+// Analog
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+
+// Touch
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_t_eth_lite/pins_arduino.h b/variants/lilygo_t_eth_lite/pins_arduino.h
new file mode 100644
index 00000000000..cb8fed779d9
--- /dev/null
+++ b/variants/lilygo_t_eth_lite/pins_arduino.h
@@ -0,0 +1,50 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 15;
+static const uint8_t SCL = 16;
+
+static const uint8_t SS = 4;
+static const uint8_t MISO = 5;
+static const uint8_t MOSI = 6;
+static const uint8_t SCK = 7;
+static const uint8_t SD_SS = 42;
+
+// Analog
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+
+// Touch
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+
+// Ethernet
+#define ETH_PHY_TYPE     ETH_PHY_W5500
+#define ETH_PHY_ADDR     1
+#define ETH_PHY_CS       9
+#define ETH_PHY_IRQ      13
+#define ETH_PHY_RST      14
+#define ETH_PHY_SPI_HOST SPI2_HOST
+#define ETH_PHY_SPI_SCK  10
+#define ETH_PHY_SPI_MISO 11
+#define ETH_PHY_SPI_MOSI 12
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_tlora_pager/pins_arduino.h b/variants/lilygo_tlora_pager/pins_arduino.h
new file mode 100644
index 00000000000..a7e03c759bd
--- /dev/null
+++ b/variants/lilygo_tlora_pager/pins_arduino.h
@@ -0,0 +1,100 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#ifndef digitalPinToInterrupt
+#define digitalPinToInterrupt(p) (((p) < 48) ? (p) : -1)
+#endif
+
+#define USB_VID          0x303a
+#define USB_PID          0x82D4
+#define USB_MANUFACTURER "LILYGO"
+#define USB_PRODUCT      "T-LoRa-Pager"
+
+// ST7796
+#define DISP_WIDTH  (222)
+#define DISP_HEIGHT (480)
+#define SD_CS       (21)
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+//BHI260,PCF85063,BQ25896,DRV2605L,ES8311 share I2C Bus
+static const uint8_t SDA = 2;
+static const uint8_t SCL = 3;
+
+// Default sd cs pin
+static const uint8_t SS = SD_CS;
+static const uint8_t MOSI = 34;
+static const uint8_t MISO = 33;
+static const uint8_t SCK = 35;
+
+#define KB_INT       (6)
+#define KB_BACKLIGHT (46)
+
+// Rotary
+#define ROTARY_A (40)
+#define ROTARY_B (41)
+#define ROTARY_C (7)
+
+// Interrupt IO port
+#define RTC_INT    (1)
+#define NFC_INT    (5)
+#define SENSOR_INT (8)
+#define NFC_CS     (39)
+
+// ES8311
+#define I2S_WS    (18)
+#define I2S_SCK   (11)
+#define I2S_MCLK  (10)
+#define I2S_SDOUT (45)
+#define I2S_SDIN  (17)
+
+// GPS
+#define GPS_TX  (12)
+#define GPS_RX  (4)
+#define GPS_PPS (13)
+
+// LoRa, SD, ST25R3916 card share SPI bus
+#define LORA_SCK  (SCK)   // share spi bus
+#define LORA_MISO (MISO)  // share spi bus
+#define LORA_MOSI (MOSI)  // share spi bus
+#define LORA_CS   (36)
+#define LORA_RST  (47)
+#define LORA_BUSY (48)
+#define LORA_IRQ  (14)
+
+// SPI interface display
+#define DISP_MOSI (MOSI)
+#define DISP_MISO (MISO)
+#define DISP_SCK  (SCK)
+#define DISP_RST  (-1)
+#define DISP_CS   (38)
+#define DISP_DC   (37)
+#define DISP_BL   (42)
+
+// External expansion chip IO definition
+#define EXPANDS_DRV_EN   (0)
+#define EXPANDS_AMP_EN   (1)
+#define EXPANDS_KB_RST   (2)
+#define EXPANDS_LORA_EN  (3)
+#define EXPANDS_GPS_EN   (4)
+#define EXPANDS_NFC_EN   (5)
+#define EXPANDS_DISP_RST (6)
+#define EXPANDS_GPS_RST  (7)
+#define EXPANDS_KB_EN    (8)
+#define EXPANDS_GPIO_EN  (9)
+
+// Peripheral definition exists
+#define USING_AUDIO_CODEC
+#define USING_XL9555_EXPANDS
+#define USING_PPM_MANAGE
+#define USING_BQ_GAUGE
+#define USING_INPUT_DEV_ROTARY
+#define USING_INPUT_DEV_KEYBOARD
+#define USING_ST25R3916
+#define USING_BHI260_SENSOR
+#define HAS_SD_CARD_SOCKET
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_twatch_s3/pins_arduino.h b/variants/lilygo_twatch_s3/pins_arduino.h
new file mode 100644
index 00000000000..b184dc9ba17
--- /dev/null
+++ b/variants/lilygo_twatch_s3/pins_arduino.h
@@ -0,0 +1,76 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303a
+#define USB_PID          0x821B
+#define USB_MANUFACTURER "LILYGO"
+#define USB_PRODUCT      "T-Watch-S3"
+
+#define DISP_WIDTH  (240)
+#define DISP_HEIGHT (240)
+
+#define DISP_MOSI (13)
+#define DISP_MISO (-1)
+#define DISP_SCK  (18)
+#define DISP_RST  (-1)
+#define DISP_CS   (12)
+#define DISP_DC   (38)
+#define DISP_BL   (45)
+
+// touch screen
+#define TP_INT (16)
+#define TP_SDA (39)
+#define TP_SCL (40)
+
+// Interrupt IO port
+#define RTC_INT    (17)
+#define PMU_INT    (21)
+#define SENSOR_INT (14)
+
+// PDM microphone
+#define MIC_SCK (44)
+#define MIC_DAT (47)
+
+// MAX98357A
+#define I2S_BCLK (48)
+#define I2S_WCLK (15)
+#define I2S_DOUT (46)
+
+#define IR_SEND (2)
+
+// TX, RX pin connected to GPS
+static const uint8_t TX = 42;
+static const uint8_t RX = 41;
+
+//BHI260,PCF85063,AXP2101,DRV2605L,PN532 share I2C Bus
+static const uint8_t SDA = 10;
+static const uint8_t SCL = 11;
+
+// Default sd cs pin
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 1;
+static const uint8_t MISO = 4;
+static const uint8_t SCK = 3;
+
+// LoRa and SD card share SPI bus
+#define LORA_SCK  (SCK)   // share spi bus
+#define LORA_MISO (MISO)  // share spi bus
+#define LORA_MOSI (MOSI)  // share spi bus
+#define LORA_CS   (5)
+#define LORA_RST  (8)
+#define LORA_BUSY (7)
+#define LORA_IRQ  (9)
+
+#define GPS_TX (TX)
+#define GPS_RX (RX)
+
+// Peripheral definition exists
+#define USING_PCM_AMPLIFIER
+#define USING_PDM_MICROPHONE
+#define USING_PMU_MANAGE
+#define USING_INPUT_DEV_TOUCHPAD
+#define USING_IR_REMOTE
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lilygo_twatch_ultra/pins_arduino.h b/variants/lilygo_twatch_ultra/pins_arduino.h
new file mode 100644
index 00000000000..c90c1ba584e
--- /dev/null
+++ b/variants/lilygo_twatch_ultra/pins_arduino.h
@@ -0,0 +1,92 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#ifndef digitalPinToInterrupt
+#define digitalPinToInterrupt(p) (((p) < 48) ? (p) : -1)
+#endif
+
+#define USB_VID          0x303a
+#define USB_PID          0x8227
+#define USB_MANUFACTURER "LILYGO"
+#define USB_PRODUCT      "T-Watch-Ultra"
+
+#define DISP_WIDTH  502
+#define DISP_HEIGHT 410
+
+// QSPI interface display
+#define DISP_D0  (38)
+#define DISP_D1  (39)
+#define DISP_D2  (42)
+#define DISP_D3  (45)
+#define DISP_SCK (40)
+#define DISP_CS  (41)
+#define DISP_TE  (6)
+
+// Interrupt IO port
+#define TP_INT     (12)
+#define RTC_INT    (1)
+#define PMU_INT    (7)
+#define NFC_INT    (5)
+#define SENSOR_INT (8)
+#define NFC_CS     (4)
+
+// PDM microphone
+#define MIC_SCK (17)
+#define MIC_DAT (18)
+
+// MAX98357A
+#define I2S_BCLK (9)
+#define I2S_WCLK (10)
+#define I2S_DOUT (11)
+
+#define SD_CS (21)
+
+// TX, RX pin connected to GPS
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+//BHI260,PCF85063,AXP2101,DRV2605L,PN532 share I2C Bus
+static const uint8_t SDA = 2;
+static const uint8_t SCL = 3;
+
+// Default sd cs pin
+static const uint8_t SS = SD_CS;
+static const uint8_t MOSI = 34;
+static const uint8_t MISO = 33;
+static const uint8_t SCK = 35;
+
+#define GPS_TX  (TX)
+#define GPS_RX  (RX)
+#define GPS_PPS (13)
+
+#define TP_SDA (SDA)
+#define TP_SCL (SCL)
+
+// LoRa and SD card share SPI bus
+#define LORA_SCK  (SCK)   // share spi bus
+#define LORA_MISO (MISO)  // share spi bus
+#define LORA_MOSI (MOSI)  // share spi bus
+#define LORA_CS   (36)
+#define LORA_RST  (47)
+#define LORA_BUSY (48)
+#define LORA_IRQ  (14)
+
+// External expansion chip IO definition
+#define EXPANDS_DRV_EN    (6)
+#define EXPANDS_DISP_EN   (7)
+#define EXPANDS_TOUCH_RST (10)
+#define EXPANDS_DISP_RST  (11)
+
+// Peripheral definition exists
+#define USING_XL9555_EXPANDS
+#define USING_PCM_AMPLIFIER
+#define USING_PDM_MICROPHONE
+#define USING_PMU_MANAGE
+#define USING_INPUT_DEV_TOUCHPAD
+#define USING_ST25R3916
+#define USING_BHI260_SENSOR
+#define HAS_SD_CARD_SOCKET
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lionbit/pins_arduino.h b/variants/lionbit/pins_arduino.h
new file mode 100644
index 00000000000..5e1ee2373bc
--- /dev/null
+++ b/variants/lionbit/pins_arduino.h
@@ -0,0 +1,89 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 0;  // GPIO0, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1,EMAC_TX_CLK
+#define BUILTIN_LED LED_BUILTIN        // backward compatibility
+#define LED_BUILTIN LED_BUILTIN        // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SWITCH_A = 2;  //  GPIO2, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0,SD_DATA0
+static const uint8_t SWITCH_B = 4;  //  GPIO4, ADC2_CH0, TOUCH0, RTC_GPIO10, HSPIHD, HS2_DATA1,SD_DATA1, EMAC_TX_ER
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+/* LionBit pin setup */
+static const uint8_t D0 = 3;  //Rx GPIO3, U0RXD, CLK_OUT2
+static const uint8_t D1 = 1;  //TX GPIO1, U0TXD, CLK_OUT3, EMAC_RXD2
+//-------------------------------------------------------------------
+
+//Please do not use while using QIO SPI mode ; Use only DIO flash mode
+static const uint8_t D2 = 9;   //I/O   U1RX  GPIO9,  SD_DATA2, SPIHD, HS1_DATA2, U1RXD
+static const uint8_t D3 = 10;  //I/O  U1TX  GPIO10, SD_DATA3, SPIWP, HS1_DATA3, U1TXD
+//-------------------------------------------------------------------
+static const uint8_t U1RX = 9;   //I/O   U1RX
+static const uint8_t U1TX = 10;  //I/O  U1TX
+
+//Second Segment - Sector -01 (Voltage (*5v or 3.3V) can be selected by using D4-7 Jumper
+static const uint8_t D4 = 16;  //I/O   U2RX  GPIO16, HS1_DATA4, U2RXD, EMAC_CLK_OUT
+static const uint8_t D5 = 17;  //I/O   U2TX  GPIO17, HS1_DATA5, U2TXD, EMAC_CLK_OUT_180
+static const uint8_t D6 = 21;  //I/O   SDA GPIO21, VSPIHD, EMAC_TX_EN
+static const uint8_t D7 = 22;  //I/O   SCl GPIO22, VSPIWP, U0RTS, EMAC_TXD1
+
+//Second Segment - Sector -02 (Voltage (*5v or 3.3V) can be selected by using D8-11 Jumper
+static const uint8_t D8 = 5;  //I/O  GPIO5, VSPICS0, HS1_DATA6, EMAC_RX_CLK
+static const uint8_t D9 =
+  23;  //I/O GPIO23, VSPID, HS1_STROBE  **********************************************Don not use when display "ON or USE"*************************
+static const uint8_t D10 = 19;  //I/O GPIO19, VSPIQ, U0CTS, EMAC_TXD0
+static const uint8_t D11 =
+  18;  //I/O GPIO18, VSPICLK, HS1_DATA7 **********************************************Don not use when display "ON or USE"*************************
+
+// Analog to Digital Converter (Support 5V) ADC2 pins not recommended while using Wifi
+static const uint8_t A0 /*ADC2_CH3 */ = 12;  //MAX 5V,I/O GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI, HSPIQ, HS2_DATA2,SD_DATA2, EMAC_TXD3
+static const uint8_t A1 /*ADC1_CH0 */ = 14;  //MAX 5V,I/O GPIO14, ADC2_CH6, TOUCH6, RTC_GPIO16, MTMS, HSPICLK, HS2_CLK,SD_CLK, EMAC_TXD2
+static const uint8_t A2 /*ADC2_CH6 */ =
+  34;  //MAX 5V,GPIO34, ADC1_CH6, RTC_GPIO4 ***********************/////////////////////Connected LDR/////////////////////////////
+static const uint8_t A3 /*ADC1_CH7 */ = 35;  //MAX 5V,GPIO35, ADC1_CH7, RTC_GPIO5
+static const uint8_t A4 /*ADC2_CH5 */ = 15;  //MAX 5V,GPIO15, ADC2_CH3, TOUCH3, MTDO, HSPICS0, RTC_GPIO13, HS2_CMD,SD_CMD, EMAC_RXD3
+static const uint8_t A5 /*ADC2_CH4 */ = 13;  //MAX 5V,GPIO13, ADC2_CH4, TOUCH4, RTC_GPIO14, MTCK, HSPID, HS2_DATA3,SD_DATA3, EMAC_RX_ER
+                                             //-------------------------------------------------------------------
+
+//------------------Touch Sensors-------------------------------------------------
+static const uint8_t VP = 36;  //  GPIO36, ADC1_CH0, RTC_GPIO0
+static const uint8_t VN = 39;  //  GPIO39, ADC1_CH3, RTC_GPIO3
+
+static const uint8_t T0 = 36;
+static const uint8_t T1 = 39;
+
+static const uint8_t DAC1 = 25;  // I/O GPIO25, DAC_1, ADC2_CH8, RTC_GPIO6, EMAC_RXD0
+static const uint8_t DAC2 = 26;  // I/O GPIO26, DAC_2, ADC2_CH9, RTC_GPIO7, EMAC_RXD1
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+/* Hardware HSPI */
+static const uint8_t MOSI = 13;  // 13;
+static const uint8_t MISO = 12;  // 12;
+static const uint8_t SCK = 14;   // 14;
+static const uint8_t SS = 15;    // 15;
+
+/* Software VSPI [Note : D9 and D11 Do not use when display "ON or USE"]*/
+static const uint8_t VMOSI = 23;  //23 /*Do not use when display "ON or USE"*/
+static const uint8_t VMISO = 19;  // 19
+static const uint8_t VSCK = 18;   // 18 /*Do not use when display "ON or USE"*/
+static const uint8_t VSS = 5;     // 5
+
+// Inbuilt Display Unit 128*128 ST7735 Driver
+static const uint8_t RST = 33;      // - RESET GPIO33, XTAL_32K_N (32.768 kHz crystal oscillator output),ADC1_CH5, TOUCH8, RTC_GPIO8
+static const uint8_t CLK = 18;      // - (18) CLK  (D11) and  D9 pin will engaged when display "ON or USE"
+static const uint8_t CS = 27;       // - CS    GPIO27, ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV
+static const uint8_t DC = 32;       //- DC/A0 GPIO32, XTAL_32K_P (32.768 kHz crystal oscillator input), ADC1_CH4,TOUCH9, RTC_GPIO9
+static const uint8_t ST_MOSI = 23;  // - MOSI (D9) This D9 pin will engaged when display "ON or USE"
+
+static const uint8_t MTDO = 15;  // A4 JTAG SIGNAL -> TDO
+static const uint8_t MTDI = 12;  // A0 JTAG SIGNAL -> TDI
+static const uint8_t MTCK = 13;  // A5 JTAG SIGNAL -> TCK
+static const uint8_t MTMS = 14;  // A1 JTAG SIGNAL -> TMS
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lionbits3/pins_arduino.h b/variants/lionbits3/pins_arduino.h
new file mode 100644
index 00000000000..260b732b777
--- /dev/null
+++ b/variants/lionbits3/pins_arduino.h
@@ -0,0 +1,92 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 0;  //GPIO0,
+#define BUILTIN_LED LED_BUILTIN        // backward compatibility
+#define LED_BUILTIN LED_BUILTIN        // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SWITCH_A = 46;  //GPIO46,
+static const uint8_t SWITCH_B = 47;  //GPIO47,
+//Wifi and Bluetooth LEDs
+static const uint8_t WIFI_LED = 38;
+static const uint8_t BT_LED = 37;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+//-------------------------------------------------------------------
+static const uint8_t U1RX = 9;   //IO,GPIO9
+static const uint8_t U1TX = 10;  //IO,GPIO10
+/* LionBits3 pin setup */
+static const uint8_t D0 = 3;    //RX,GPIO3,MCPWM
+static const uint8_t D1 = 1;    //TX,GPIO1,ADC1_CH0,MCPWM
+static const uint8_t D2 = 9;    //IO,GPIO9,ADC1_CH8,TOUCH9,MCPWM
+static const uint8_t D3 = 10;   //IO,GPIO10,ADC1_CH9,TOUCH10,MCPWM
+static const uint8_t D4 = 11;   //IO,GPIO11,ADC2_CH0,TOUCH11,MCPWM
+static const uint8_t D5 = 12;   //IO,GPIO12,ADC2_CH1,TOUCH12,MCPWM
+static const uint8_t D6 = 13;   //IO,GPIO13,ADC2_CH2,TOUCH13,MCPWM
+static const uint8_t D7 = 14;   //IO,GPIO14,ADC2_CH3,TOUCH14,MCPWM
+static const uint8_t D8 = 15;   //IO,GPIO15,ADC2_CH4,MCPWM
+static const uint8_t D9 = 16;   //IO,GPIO16,ADC2_CH5,MCPWM
+static const uint8_t D10 = 17;  //IO,GPIO17,ADC2_CH6,MCPWM
+static const uint8_t D11 = 18;  //IO,GPIO18,ADC2_CH7,MCPWM
+static const uint8_t D12 = 8;   //IO,GPIO8,ADC1_CH7,MCPWM
+static const uint8_t D13 = 39;  //IO,GPIO39,MCPWM
+static const uint8_t D14 = 40;  //IO,GPIO40,MCPWM
+static const uint8_t D15 = 41;  //IO,GPIO41,MCPWM
+static const uint8_t D16 = 48;  //IO,GPIO48,MCPWM
+static const uint8_t D17 = 21;  //IO,GPIO21,MCPWM
+
+//Other pins.
+static const uint8_t BUZZER = 21;
+static const uint8_t LDR = 7;
+
+static const uint8_t RGBLED = 48;
+
+// Analog to Digital Converter (Support 5V) ADC2 pins not recommended while using Wifi
+static const uint8_t A0 = 2;   //IO,GPIO2,ADC1_CH1,TOUCH2,MCPWM
+static const uint8_t A1 = 1;   //IO,GPIO1,ADC1_CH0,TOUCH1,MCPWM
+static const uint8_t A2 = 3;   //IO,GPIO3,ADC1_CH2,TOUCH3,MCPWM
+static const uint8_t A3 = 4;   //IO,GPIO4,ADC1_CH3,TOUCH4,MCPWM
+static const uint8_t A4 = 5;   //IO,GPIO5,ADC1_CH4,TOUCH5,MCPWM
+static const uint8_t A5 = 6;   //IO,GPIO6,ADC1_CH5,TOUCH6,MCPWM
+static const uint8_t A6 = 7;   //IO,GPIO7,ADC1_CH6,TOUCH7,MCPWM
+static const uint8_t AD1 = 7;  //IO,GPIO7,ADC1_CH6,TOUCH7,MCPWM
+
+// Inbuilt Display Unit 128*128 ST7735 Driver New
+
+static const uint8_t SDA = 40;  //GPIO40;
+static const uint8_t SCL = 41;  //GPIO41;
+
+/* Hardware HSPI */
+static const uint8_t MOSI = 35;  //GPIO35;
+static const uint8_t MISO = 37;  //GPIO37;
+static const uint8_t SCK = 36;   //GPIO36;
+static const uint8_t SS = 34;    //GPIO34;
+static const uint8_t SDO = 35;   //GPIO35;
+static const uint8_t SDI = 37;   //GPIO37;
+//----------------------------------
+
+static const uint8_t TFT_RST = 38;   //GPIO38;
+static const uint8_t TFT_SCLK = 35;  //GPIO35;
+static const uint8_t TFT_CS = 42;    //GPIO42;
+static const uint8_t TFT_DC = 37;    //GPIO37;
+static const uint8_t TFT_MOSI = 36;  //GPIO36;
+
+static const uint8_t LCD_A0 = 37;          //GPIO37,
+static const uint8_t LCD_BACK_LIGHT = 45;  //GPIO45,
+static const uint8_t DAC1 = 21;            //GPIO21,
+//LCD additional pins
+
+//Adafruit 128*128 ST7735 Driver New
+static const uint8_t rst = 38;
+static const uint8_t sclk = 35;
+static const uint8_t cs = 42;
+static const uint8_t dc = 37;
+static const uint8_t mosi = 36;
+
+#define VP 36  //GPIO36,
+#define VN 39  //GPIO39,
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lolin32-lite/pins_arduino.h b/variants/lolin32-lite/pins_arduino.h
new file mode 100644
index 00000000000..140d06b8423
--- /dev/null
+++ b/variants/lolin32-lite/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t LED_BUILTIN = 22;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SDA = 19;
+static const uint8_t SCL = 23;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lolin32/pins_arduino.h b/variants/lolin32/pins_arduino.h
index 6be8fe24c7b..12ca95c4cab 100644
--- a/variants/lolin32/pins_arduino.h
+++ b/variants/lolin32/pins_arduino.h
@@ -3,19 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 5;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-
-
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -23,10 +13,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/lolin_c3_mini/pins_arduino.h b/variants/lolin_c3_mini/pins_arduino.h
new file mode 100644
index 00000000000..0236f02267d
--- /dev/null
+++ b/variants/lolin_c3_mini/pins_arduino.h
@@ -0,0 +1,36 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// based on https://www.wemos.cc/en/latest/c3/c3_mini.html
+// WS2812 RGB LED on pin 7
+#define PIN_RGB_LED 7
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 10;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 4;
+static const uint8_t MISO = 3;
+static const uint8_t SCK = 2;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lolin_c3_pico/pins_arduino.h b/variants/lolin_c3_pico/pins_arduino.h
new file mode 100644
index 00000000000..45087c3f9fc
--- /dev/null
+++ b/variants/lolin_c3_pico/pins_arduino.h
@@ -0,0 +1,40 @@
+// https://www.wemos.cc/en/latest/c3/c3_pico.html
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// based on https://www.wemos.cc/en/latest/c3/c3_pico.html
+// WS2812 RGB LED on pin 7
+#define PIN_RGB_LED 7
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 10;
+
+static const uint8_t VBAT = 3;
+
+static const uint8_t SCK = 1;
+static const uint8_t MISO = 0;
+static const uint8_t MOSI = 4;
+static const uint8_t SS = 5;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lolin_s2_mini/pins_arduino.h b/variants/lolin_s2_mini/pins_arduino.h
new file mode 100644
index 00000000000..50b821a64ab
--- /dev/null
+++ b/variants/lolin_s2_mini/pins_arduino.h
@@ -0,0 +1,74 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// Default USB Settings
+#define USB_VID          0x303a
+#define USB_PID          0x80C2
+#define USB_MANUFACTURER "WEMOS.CC"
+#define USB_PRODUCT      "LOLIN-S2-MINI"
+#define USB_SERIAL       "0"
+
+// Default USB FirmwareMSC Settings
+#define USB_FW_MSC_VENDOR_ID        "ESP32-S2"      //max 8 chars
+#define USB_FW_MSC_PRODUCT_ID       "Firmware MSC"  //max 16 chars
+#define USB_FW_MSC_PRODUCT_REVISION "1.23"          //max 4 chars
+#define USB_FW_MSC_VOLUME_NAME      "S2-Firmware"   //max 11 chars
+#define USB_FW_MSC_SERIAL_NUMBER    0x00000000
+
+static const uint8_t LED_BUILTIN = 15;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 39;
+static const uint8_t RX = 37;
+
+static const uint8_t SDA = 33;
+static const uint8_t SCL = 35;
+
+static const uint8_t SS = 12;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 9;
+static const uint8_t SCK = 7;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lolin_s2_pico/pins_arduino.h b/variants/lolin_s2_pico/pins_arduino.h
new file mode 100644
index 00000000000..d98528cf5f0
--- /dev/null
+++ b/variants/lolin_s2_pico/pins_arduino.h
@@ -0,0 +1,76 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// Default USB Settings
+#define USB_VID          0x303a
+#define USB_PID          0x80C5
+#define USB_MANUFACTURER "WEMOS.CC"
+#define USB_PRODUCT      "LOLIN-S2-PICO"
+#define USB_SERIAL       "0"
+
+// Default USB FirmwareMSC Settings
+#define USB_FW_MSC_VENDOR_ID        "ESP32-S2"      //max 8 chars
+#define USB_FW_MSC_PRODUCT_ID       "Firmware MSC"  //max 16 chars
+#define USB_FW_MSC_PRODUCT_REVISION "1.23"          //max 4 chars
+#define USB_FW_MSC_VOLUME_NAME      "S2-Firmware"   //max 11 chars
+#define USB_FW_MSC_SERIAL_NUMBER    0x00000000
+
+static const uint8_t LED_BUILTIN = 10;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 38;
+static const uint8_t RX = 33;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+static const uint8_t S2_PICO_OLED_RESET = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lolin_s3/pins_arduino.h b/variants/lolin_s3/pins_arduino.h
new file mode 100644
index 00000000000..0c23654ab9e
--- /dev/null
+++ b/variants/lolin_s3/pins_arduino.h
@@ -0,0 +1,61 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = 38 + SOC_GPIO_PIN_COUNT;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 42;
+static const uint8_t SCL = 41;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lolin_s3_mini/pins_arduino.h b/variants/lolin_s3_mini/pins_arduino.h
new file mode 100644
index 00000000000..361d3238960
--- /dev/null
+++ b/variants/lolin_s3_mini/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x8167
+
+static const uint8_t LED_BUILTIN = 47 + SOC_GPIO_PIN_COUNT;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+// This board has a builtin RGB LED that works with a different signal color order
+// Other order options can be found in https://github.com/espressif/arduino-esp32/blob/master/cores/esp32/esp32-hal-rgb-led.h
+#define RGB_BUILTIN_LED_COLOR_ORDER LED_COLOR_ORDER_RGB
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 35;
+static const uint8_t SCL = 36;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lolin_s3_mini_pro/pins_arduino.h b/variants/lolin_s3_mini_pro/pins_arduino.h
new file mode 100644
index 00000000000..1c5f6c26bd0
--- /dev/null
+++ b/variants/lolin_s3_mini_pro/pins_arduino.h
@@ -0,0 +1,77 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x8216
+
+static const uint8_t LED_BUILTIN = 8 + SOC_GPIO_PIN_COUNT;
+;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 5
+#define RGB_POWER      7  //RGB LED POWER PIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 12;
+static const uint8_t SCL = 11;
+
+static const uint8_t SS = 37;
+static const uint8_t MOSI = 38;
+static const uint8_t MISO = 39;
+static const uint8_t SCK = 40;
+
+//TFT
+static const uint8_t TFT_BL = 33;
+static const uint8_t TFT_DC = 36;
+static const uint8_t TFT_CS = 35;
+static const uint8_t TFT_RST = 34;
+
+//IR
+static const uint8_t PIN_IR = 9;
+
+//BUTTON
+static const uint8_t BUTTON_LEFT = 0;
+static const uint8_t BUTTON_OK = 47;
+static const uint8_t BUTTON_RIGHT = 48;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lolin_s3_mini_pro/variant.cpp b/variants/lolin_s3_mini_pro/variant.cpp
new file mode 100644
index 00000000000..72b340b27ad
--- /dev/null
+++ b/variants/lolin_s3_mini_pro/variant.cpp
@@ -0,0 +1,31 @@
+/*
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  // IR
+  pinMode(PIN_IR, OUTPUT);
+  digitalWrite(PIN_IR, LOW);
+  // RGB
+  pinMode(RGB_POWER, OUTPUT);
+  digitalWrite(RGB_POWER, LOW);
+  // BUTTON
+  pinMode(BUTTON_LEFT, INPUT_PULLUP);
+  pinMode(BUTTON_OK, INPUT_PULLUP);
+  pinMode(BUTTON_RIGHT, INPUT_PULLUP);
+  // TFT
+  pinMode(TFT_BL, OUTPUT);
+  digitalWrite(TFT_BL, LOW);
+  pinMode(TFT_CS, OUTPUT);
+  digitalWrite(TFT_CS, HIGH);
+  pinMode(TFT_RST, OUTPUT);
+  digitalWrite(TFT_RST, LOW);
+  delay(1);
+  digitalWrite(TFT_RST, HIGH);
+}
+}
diff --git a/variants/lolin_s3_pro/pins_arduino.h b/variants/lolin_s3_pro/pins_arduino.h
new file mode 100644
index 00000000000..7f2cd934521
--- /dev/null
+++ b/variants/lolin_s3_pro/pins_arduino.h
@@ -0,0 +1,69 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x8161
+
+static const uint8_t LED_BUILTIN = 38 + SOC_GPIO_PIN_COUNT;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 9;
+static const uint8_t SCL = 10;
+
+static const uint8_t SS = 0;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t TF_CS = 46;
+
+static const uint8_t TS_CS = 45;
+static const uint8_t TFT_CS = 48;
+static const uint8_t TFT_DC = 47;
+static const uint8_t TFT_RST = 21;
+static const uint8_t TFT_LED = 14;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/lopy/pins_arduino.h b/variants/lopy/pins_arduino.h
index 40db576c9b9..f7e2ee02476 100644
--- a/variants/lopy/pins_arduino.h
+++ b/variants/lopy/pins_arduino.h
@@ -2,42 +2,40 @@
 #define Pins_Arduino_h
 
 #include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       18
-
-#define analogInputToDigitalPin(p)  (((p)<40)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
+#include "soc/soc_caps.h"
 
 // SPI LoRa Radio
-#define LORA_SCK 5      // GPIO5  - SX1276 SCK
-#define LORA_MISO 19    // GPIO19 - SX1276 MISO
-#define LORA_MOSI 27    // GPIO27 - SX1276 MOSI
-#define LORA_CS 17      // GPIO17 - SX1276 CS
-#define LORA_RST 18     // GPIO18 - SX1276 RST
-#define LORA_IRQ 23     // GPIO23 - SX1276 IO0
-#define LORA_IO0 LORA_IRQ  // alias
-#define LORA_IO1 LORA_IRQ  // tied by diode to IO0
-#define LORA_IO2 LORA_IRQ  // tied by diode to IO0
+#define LORA_SCK  5         // GPIO5  - SX1276 SCK
+#define LORA_MISO 19        // GPIO19 - SX1276 MISO
+#define LORA_MOSI 27        // GPIO27 - SX1276 MOSI
+#define LORA_CS   17        // GPIO17 - SX1276 CS
+#define LORA_RST  18        // GPIO18 - SX1276 RST
+#define LORA_IRQ  23        // GPIO23 - SX1276 IO0
+#define LORA_IO0  LORA_IRQ  // alias
+#define LORA_IO1  LORA_IRQ  // tied by diode to IO0
+#define LORA_IO2  LORA_IRQ  // tied by diode to IO0
 
-static const uint8_t LED_BUILTIN = 0; // ->2812 RGB !!!
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+// RGB LED
+#define PIN_RGB_LED 0  // ->2812 RGB !!!
+static const uint8_t LED_BUILTIN = PIN_RGB_LED + SOC_GPIO_PIN_COUNT;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
 
-#define ANT_SELECT 16   // GPIO16 - External Antenna Switch
+#define ANT_SELECT 16  // GPIO16 - External Antenna Switch
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 12;
 static const uint8_t SCL = 13;
- 
-static const uint8_t SS    = 17;
-static const uint8_t MOSI  = 22;
-static const uint8_t MISO  = 37;
-static const uint8_t SCK   = 13;
+
+static const uint8_t SS = 17;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 13;
 
 static const uint8_t A0 = 36;
 static const uint8_t A1 = 37;
diff --git a/variants/lopy4/pins_arduino.h b/variants/lopy4/pins_arduino.h
index 3fb401a6e50..eb36b3008e6 100644
--- a/variants/lopy4/pins_arduino.h
+++ b/variants/lopy4/pins_arduino.h
@@ -2,42 +2,40 @@
 #define Pins_Arduino_h
 
 #include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       18
-
-#define analogInputToDigitalPin(p)  (((p)<40)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
+#include "soc/soc_caps.h"
 
 // SPI LoRa Radio
-#define LORA_SCK 5      // GPIO5  - SX1276 SCK
-#define LORA_MISO 19    // GPIO19 - SX1276 MISO
-#define LORA_MOSI 27    // GPIO27 - SX1276 MOSI
-#define LORA_CS 18      // GPIO18 - SX1276 CS
-#define LORA_IRQ 23     // GPIO23 - SX1276 IO0
-#define LORA_IO0 LORA_IRQ  // alias
-#define LORA_IO1 LORA_IRQ   // tied by diode to IO0
-#define LORA_IO2 LORA_IRQ   // tied by diode to IO0
-#define LORA_RST NOT_A_PIN
+#define LORA_SCK  5         // GPIO5  - SX1276 SCK
+#define LORA_MISO 19        // GPIO19 - SX1276 MISO
+#define LORA_MOSI 27        // GPIO27 - SX1276 MOSI
+#define LORA_CS   18        // GPIO18 - SX1276 CS
+#define LORA_IRQ  23        // GPIO23 - SX1276 IO0
+#define LORA_IO0  LORA_IRQ  // alias
+#define LORA_IO1  LORA_IRQ  // tied by diode to IO0
+#define LORA_IO2  LORA_IRQ  // tied by diode to IO0
+#define LORA_RST  NOT_A_PIN
 
-static const uint8_t LED_BUILTIN = 0; // ->2812 RGB !!!
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+// RGB LED
+#define PIN_RGB_LED 0  // ->2812 RGB !!!
+static const uint8_t LED_BUILTIN = PIN_RGB_LED + SOC_GPIO_PIN_COUNT;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
 
-#define ANT_SELECT 21   // GPIO21 - External Antenna Switch
+#define ANT_SELECT 21  // GPIO21 - External Antenna Switch
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 12;
 static const uint8_t SCL = 13;
- 
-static const uint8_t SS    = 18;
-static const uint8_t MOSI  = 22;
-static const uint8_t MISO  = 37;
-static const uint8_t SCK   = 13;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 13;
 
 static const uint8_t A0 = 36;
 static const uint8_t A1 = 37;
diff --git a/variants/m5stack_atom/pins_arduino.h b/variants/m5stack_atom/pins_arduino.h
index b899534a071..8a845658d5d 100644
--- a/variants/m5stack_atom/pins_arduino.h
+++ b/variants/m5stack_atom/pins_arduino.h
@@ -3,21 +3,12 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 26;
 static const uint8_t SCL = 32;
 
-
 static const uint8_t G12 = 12;
 static const uint8_t G19 = 19;
 static const uint8_t G21 = 21;
@@ -42,9 +33,9 @@ static const uint8_t DAC2 = 26;
 static const uint8_t ADC1 = 35;
 static const uint8_t ADC2 = 36;
 
-static const uint8_t SS    = 19;
-static const uint8_t MOSI  = 33;
-static const uint8_t MISO  = 23;
-static const uint8_t SCK   = 22;
+static const uint8_t SS = 19;
+static const uint8_t MOSI = 33;
+static const uint8_t MISO = 23;
+static const uint8_t SCK = 22;
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_atoms3/pins_arduino.h b/variants/m5stack_atoms3/pins_arduino.h
new file mode 100644
index 00000000000..9d2389cc98c
--- /dev/null
+++ b/variants/m5stack_atoms3/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+// Some boards have too low voltage on this pin (board design bug)
+// Use different pin with 3V and connect with 48
+// and change this setup for the chosen pin (for example 38)
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t TXD2 = 1;
+static const uint8_t RXD2 = 2;
+
+static const uint8_t SDA = 38;
+static const uint8_t SCL = 39;
+
+static const uint8_t SS = 15;
+static const uint8_t MOSI = 21;
+static const uint8_t MISO = -1;
+static const uint8_t SCK = 17;
+
+static const uint8_t G0 = 0;
+static const uint8_t G1 = 1;
+static const uint8_t G2 = 2;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G6 = 6;
+static const uint8_t G7 = 7;
+static const uint8_t G8 = 8;
+static const uint8_t G36 = 36;
+static const uint8_t G37 = 37;
+static const uint8_t G38 = 38;
+static const uint8_t G39 = 39;
+static const uint8_t G40 = 40;
+static const uint8_t G42 = 42;
+
+static const uint8_t ADC1 = 7;
+static const uint8_t ADC2 = 8;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_capsule/pins_arduino.h b/variants/m5stack_capsule/pins_arduino.h
new file mode 100644
index 00000000000..0209d2162fe
--- /dev/null
+++ b/variants/m5stack_capsule/pins_arduino.h
@@ -0,0 +1,51 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t TXD2 = 1;
+static const uint8_t RXD2 = 2;
+
+static const uint8_t SDA = 13;
+static const uint8_t SCL = 15;
+
+static const uint8_t SS = 11;
+static const uint8_t MOSI = 12;
+static const uint8_t MISO = 39;
+static const uint8_t SCK = 14;
+
+static const uint8_t G0 = 0;
+static const uint8_t G1 = 1;
+static const uint8_t G2 = 2;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G6 = 6;
+static const uint8_t G7 = 7;
+static const uint8_t G8 = 8;
+static const uint8_t G9 = 9;
+static const uint8_t G10 = 10;
+static const uint8_t G11 = 11;
+static const uint8_t G12 = 12;
+static const uint8_t G13 = 13;
+static const uint8_t G14 = 14;
+static const uint8_t G15 = 15;
+static const uint8_t G39 = 39;
+static const uint8_t G40 = 40;
+static const uint8_t G41 = 41;
+static const uint8_t G42 = 42;
+static const uint8_t G43 = 43;
+static const uint8_t G44 = 44;
+static const uint8_t G46 = 46;
+
+static const uint8_t ADC1 = 7;
+static const uint8_t ADC2 = 8;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_cardputer/pins_arduino.h b/variants/m5stack_cardputer/pins_arduino.h
new file mode 100644
index 00000000000..2c50f97c262
--- /dev/null
+++ b/variants/m5stack_cardputer/pins_arduino.h
@@ -0,0 +1,51 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t TXD2 = 1;
+static const uint8_t RXD2 = 2;
+
+static const uint8_t SDA = 13;
+static const uint8_t SCL = 15;
+
+static const uint8_t SS = 12;
+static const uint8_t MOSI = 14;
+static const uint8_t MISO = 39;
+static const uint8_t SCK = 40;
+
+static const uint8_t G0 = 0;
+static const uint8_t G1 = 1;
+static const uint8_t G2 = 2;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G6 = 6;
+static const uint8_t G7 = 7;
+static const uint8_t G8 = 8;
+static const uint8_t G9 = 9;
+static const uint8_t G10 = 10;
+static const uint8_t G11 = 11;
+static const uint8_t G12 = 12;
+static const uint8_t G13 = 13;
+static const uint8_t G14 = 14;
+static const uint8_t G15 = 15;
+static const uint8_t G39 = 39;
+static const uint8_t G40 = 40;
+static const uint8_t G41 = 41;
+static const uint8_t G42 = 42;
+static const uint8_t G43 = 43;
+static const uint8_t G44 = 44;
+static const uint8_t G46 = 46;
+
+static const uint8_t ADC1 = 7;
+static const uint8_t ADC2 = 8;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_core/pins_arduino.h b/variants/m5stack_core/pins_arduino.h
new file mode 100644
index 00000000000..cf807aab447
--- /dev/null
+++ b/variants/m5stack_core/pins_arduino.h
@@ -0,0 +1,47 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t TXD2 = 17;
+static const uint8_t RXD2 = 16;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t G23 = 23;
+static const uint8_t G19 = 19;
+static const uint8_t G18 = 18;
+static const uint8_t G3 = 3;
+static const uint8_t G16 = 16;
+static const uint8_t G21 = 21;
+static const uint8_t G2 = 2;
+static const uint8_t G12 = 12;
+static const uint8_t G15 = 15;
+static const uint8_t G35 = 35;
+static const uint8_t G36 = 36;
+static const uint8_t G25 = 25;
+static const uint8_t G26 = 26;
+static const uint8_t G1 = 1;
+static const uint8_t G17 = 17;
+static const uint8_t G22 = 22;
+static const uint8_t G5 = 5;
+static const uint8_t G13 = 13;
+static const uint8_t G0 = 0;
+static const uint8_t G34 = 34;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t ADC1 = 35;
+static const uint8_t ADC2 = 36;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_core2/pins_arduino.h b/variants/m5stack_core2/pins_arduino.h
index 20ffc5144be..a4bd6bb29a6 100644
--- a/variants/m5stack_core2/pins_arduino.h
+++ b/variants/m5stack_core2/pins_arduino.h
@@ -3,14 +3,6 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        20
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 #define TX2 14
 #define RX2 13
 
@@ -20,10 +12,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 32;
 static const uint8_t SCL = 33;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 38;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 38;
+static const uint8_t SCK = 18;
 
 static const uint8_t G23 = 23;
 static const uint8_t G38 = 38;
diff --git a/variants/m5stack_core_esp32/pins_arduino.h b/variants/m5stack_core_esp32/pins_arduino.h
deleted file mode 100644
index d2d87d4fa2d..00000000000
--- a/variants/m5stack_core_esp32/pins_arduino.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        20
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-static const uint8_t TX = 1;
-static const uint8_t RX = 3;
-
-static const uint8_t TXD2 = 17;
-static const uint8_t RXD2 = 16;
-
-static const uint8_t SDA = 21;
-static const uint8_t SCL = 22;
-
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
-
-static const uint8_t G23 = 23;
-static const uint8_t G19 = 19;
-static const uint8_t G18 = 18;
-static const uint8_t G3 = 3;
-static const uint8_t G16 = 16;
-static const uint8_t G21 = 21;
-static const uint8_t G2 = 2;
-static const uint8_t G12 = 12;
-static const uint8_t G15 = 15;
-static const uint8_t G35 = 35;
-static const uint8_t G36 = 36;
-static const uint8_t G25 = 25;
-static const uint8_t G26 = 26;
-static const uint8_t G1 = 1;
-static const uint8_t G17 = 17;
-static const uint8_t G22 = 22;
-static const uint8_t G5 = 5;
-static const uint8_t G13 = 13;
-static const uint8_t G0 = 0;
-static const uint8_t G34 = 34;
-
-static const uint8_t DAC1 = 25;
-static const uint8_t DAC2 = 26;
-
-static const uint8_t ADC1 = 35;
-static const uint8_t ADC2 = 36;
-
-#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_coreink/pins_arduino.h b/variants/m5stack_coreink/pins_arduino.h
index 6ef1bf4792a..5d6f3ea0b4a 100644
--- a/variants/m5stack_coreink/pins_arduino.h
+++ b/variants/m5stack_coreink/pins_arduino.h
@@ -3,14 +3,6 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 #define TX2 14
 #define RX2 13
 
@@ -20,10 +12,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 32;
 static const uint8_t SCL = 33;
 
-static const uint8_t SS    = 9;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 34;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 9;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 34;
+static const uint8_t SCK = 18;
 
 static const uint8_t G26 = 26;
 static const uint8_t G36 = 36;
diff --git a/variants/m5stack_cores3/pins_arduino.h b/variants/m5stack_cores3/pins_arduino.h
new file mode 100644
index 00000000000..301d833553f
--- /dev/null
+++ b/variants/m5stack_cores3/pins_arduino.h
@@ -0,0 +1,63 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+// Some boards have too low voltage on this pin (board design bug)
+// Use different pin with 3V and connect with 48
+// and change this setup for the chosen pin (for example 38)
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 48;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t TXD2 = 17;
+static const uint8_t RXD2 = 18;
+
+static const uint8_t SDA = 12;
+static const uint8_t SCL = 11;
+
+static const uint8_t SS = 15;
+static const uint8_t MOSI = 37;
+static const uint8_t MISO = 35;
+static const uint8_t SCK = 36;
+
+static const uint8_t G0 = 0;
+static const uint8_t G1 = 1;
+static const uint8_t G2 = 2;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G6 = 6;
+static const uint8_t G7 = 7;
+static const uint8_t G8 = 8;
+static const uint8_t G9 = 9;
+static const uint8_t G11 = 11;
+static const uint8_t G12 = 12;
+static const uint8_t G13 = 13;
+static const uint8_t G14 = 14;
+static const uint8_t G17 = 17;
+static const uint8_t G18 = 18;
+static const uint8_t G19 = 19;
+static const uint8_t G20 = 20;
+static const uint8_t G21 = 21;
+static const uint8_t G33 = 33;
+static const uint8_t G34 = 34;
+static const uint8_t G35 = 35;
+static const uint8_t G36 = 36;
+static const uint8_t G37 = 37;
+static const uint8_t G38 = 38;
+static const uint8_t G45 = 45;
+static const uint8_t G46 = 46;
+
+static const uint8_t ADC = 10;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_dial/pins_arduino.h b/variants/m5stack_dial/pins_arduino.h
new file mode 100644
index 00000000000..2c50f97c262
--- /dev/null
+++ b/variants/m5stack_dial/pins_arduino.h
@@ -0,0 +1,51 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t TXD2 = 1;
+static const uint8_t RXD2 = 2;
+
+static const uint8_t SDA = 13;
+static const uint8_t SCL = 15;
+
+static const uint8_t SS = 12;
+static const uint8_t MOSI = 14;
+static const uint8_t MISO = 39;
+static const uint8_t SCK = 40;
+
+static const uint8_t G0 = 0;
+static const uint8_t G1 = 1;
+static const uint8_t G2 = 2;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G6 = 6;
+static const uint8_t G7 = 7;
+static const uint8_t G8 = 8;
+static const uint8_t G9 = 9;
+static const uint8_t G10 = 10;
+static const uint8_t G11 = 11;
+static const uint8_t G12 = 12;
+static const uint8_t G13 = 13;
+static const uint8_t G14 = 14;
+static const uint8_t G15 = 15;
+static const uint8_t G39 = 39;
+static const uint8_t G40 = 40;
+static const uint8_t G41 = 41;
+static const uint8_t G42 = 42;
+static const uint8_t G43 = 43;
+static const uint8_t G44 = 44;
+static const uint8_t G46 = 46;
+
+static const uint8_t ADC1 = 7;
+static const uint8_t ADC2 = 8;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_dinmeter/pins_arduino.h b/variants/m5stack_dinmeter/pins_arduino.h
new file mode 100644
index 00000000000..2c50f97c262
--- /dev/null
+++ b/variants/m5stack_dinmeter/pins_arduino.h
@@ -0,0 +1,51 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t TXD2 = 1;
+static const uint8_t RXD2 = 2;
+
+static const uint8_t SDA = 13;
+static const uint8_t SCL = 15;
+
+static const uint8_t SS = 12;
+static const uint8_t MOSI = 14;
+static const uint8_t MISO = 39;
+static const uint8_t SCK = 40;
+
+static const uint8_t G0 = 0;
+static const uint8_t G1 = 1;
+static const uint8_t G2 = 2;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G6 = 6;
+static const uint8_t G7 = 7;
+static const uint8_t G8 = 8;
+static const uint8_t G9 = 9;
+static const uint8_t G10 = 10;
+static const uint8_t G11 = 11;
+static const uint8_t G12 = 12;
+static const uint8_t G13 = 13;
+static const uint8_t G14 = 14;
+static const uint8_t G15 = 15;
+static const uint8_t G39 = 39;
+static const uint8_t G40 = 40;
+static const uint8_t G41 = 41;
+static const uint8_t G42 = 42;
+static const uint8_t G43 = 43;
+static const uint8_t G44 = 44;
+static const uint8_t G46 = 46;
+
+static const uint8_t ADC1 = 7;
+static const uint8_t ADC2 = 8;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_fire/pins_arduino.h b/variants/m5stack_fire/pins_arduino.h
index 5912a1c35c6..2202e6bb4bc 100644
--- a/variants/m5stack_fire/pins_arduino.h
+++ b/variants/m5stack_fire/pins_arduino.h
@@ -3,24 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        20
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 4;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t G23 = 23;
 static const uint8_t G19 = 19;
diff --git a/variants/m5stack_nanoc6/pins_arduino.h b/variants/m5stack_nanoc6/pins_arduino.h
new file mode 100644
index 00000000000..8f16e0a2675
--- /dev/null
+++ b/variants/m5stack_nanoc6/pins_arduino.h
@@ -0,0 +1,45 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x1001
+#define USB_MANUFACTURER "M5Stack"
+#define USB_PRODUCT      "NanoC6"
+#define USB_SERIAL       ""
+
+static const uint8_t LED_BUILTIN = 7;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 2;
+static const uint8_t SCL = 1;
+
+static const uint8_t SS = 4;    // Not connected
+static const uint8_t MOSI = 5;  // Not connected
+static const uint8_t MISO = 6;  // Not connected
+static const uint8_t SCK = 8;   // Not connected
+
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 2;
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 7;
+static const uint8_t D5 = 8;
+static const uint8_t D6 = 9;
+
+static const uint8_t BLUE_LED_PIN = 7;
+static const uint8_t BTN_PIN = 9;
+static const uint8_t IR_TX_PIN = 3;
+static const uint8_t RGB_LED_PWR_PIN = 19;
+static const uint8_t RGB_LED_DATA_PIN = 20;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_paper/pins_arduino.h b/variants/m5stack_paper/pins_arduino.h
new file mode 100644
index 00000000000..02ccc73d933
--- /dev/null
+++ b/variants/m5stack_paper/pins_arduino.h
@@ -0,0 +1,48 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define TX2 14
+#define RX2 13
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 25;
+static const uint8_t SCL = 32;
+
+static const uint8_t SS = 15;
+static const uint8_t MOSI = 12;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 14;
+
+static const uint8_t G25 = 25;
+static const uint8_t G32 = 32;
+
+static const uint8_t G26 = 26;
+static const uint8_t G33 = 33;
+
+static const uint8_t G18 = 18;
+static const uint8_t G19 = 19;
+
+static const uint8_t G21 = 21;
+static const uint8_t G22 = 22;
+
+static const uint8_t G36 = 36;
+static const uint8_t G2 = 2;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G23 = 23;
+
+static const uint8_t G37 = 37;
+static const uint8_t G38 = 38;
+static const uint8_t G39 = 39;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t ADC1 = 35;
+static const uint8_t ADC2 = 36;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_poe_cam/pins_arduino.h b/variants/m5stack_poe_cam/pins_arduino.h
new file mode 100644
index 00000000000..9ae9b238731
--- /dev/null
+++ b/variants/m5stack_poe_cam/pins_arduino.h
@@ -0,0 +1,48 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 25;
+static const uint8_t SCL = 33;
+
+// Modified elsewhere
+static const uint8_t SS = -1;
+static const uint8_t MOSI = -1;
+static const uint8_t MISO = -1;
+static const uint8_t SCK = -1;
+
+static const uint8_t G23 = 23;
+static const uint8_t G25 = 25;
+static const uint8_t G27 = 27;
+static const uint8_t G22 = 22;
+static const uint8_t G26 = 26;
+static const uint8_t G21 = 21;
+static const uint8_t G32 = 32;
+static const uint8_t G35 = 35;
+static const uint8_t G34 = 34;
+static const uint8_t G5 = 5;
+static const uint8_t G39 = 39;
+static const uint8_t G18 = 18;
+static const uint8_t G36 = 36;
+static const uint8_t G19 = 19;
+static const uint8_t G15 = 15;
+
+static const uint8_t G2 = 2;
+static const uint8_t G33 = 33;
+
+static const uint8_t G13 = 13;
+static const uint8_t G4 = 4;
+
+static const uint8_t G0 = 0;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t ADC1 = 35;
+static const uint8_t ADC2 = 36;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_stamp_c3/pins_arduino.h b/variants/m5stack_stamp_c3/pins_arduino.h
new file mode 100644
index 00000000000..629fc1b41e6
--- /dev/null
+++ b/variants/m5stack_stamp_c3/pins_arduino.h
@@ -0,0 +1,24 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_stamp_pico/pins_arduino.h b/variants/m5stack_stamp_pico/pins_arduino.h
new file mode 100644
index 00000000000..37a17ffec4d
--- /dev/null
+++ b/variants/m5stack_stamp_pico/pins_arduino.h
@@ -0,0 +1,31 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 19;
+static const uint8_t MOSI = 26;
+static const uint8_t MISO = 36;
+static const uint8_t SCK = 18;
+
+static const uint8_t G26 = 26;
+static const uint8_t G36 = 36;
+static const uint8_t G18 = 18;
+static const uint8_t G19 = 19;
+static const uint8_t G21 = 21;
+static const uint8_t G22 = 22;
+static const uint8_t G25 = 25;
+static const uint8_t G1 = 1;
+static const uint8_t G3 = 3;
+static const uint8_t G0 = 0;
+
+static const uint8_t G32 = 32;
+static const uint8_t G33 = 33;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_stamp_s3/pins_arduino.h b/variants/m5stack_stamp_s3/pins_arduino.h
new file mode 100644
index 00000000000..595da52bf29
--- /dev/null
+++ b/variants/m5stack_stamp_s3/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t TXD2 = 1;
+static const uint8_t RXD2 = 2;
+
+static const uint8_t SDA = 13;
+static const uint8_t SCL = 15;
+
+// Modified elsewhere
+static const uint8_t SS = -1;
+static const uint8_t MOSI = -1;
+static const uint8_t MISO = -1;
+static const uint8_t SCK = -1;
+
+static const uint8_t G0 = 0;
+static const uint8_t G1 = 1;
+static const uint8_t G2 = 2;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G6 = 6;
+static const uint8_t G7 = 7;
+static const uint8_t G8 = 8;
+static const uint8_t G9 = 9;
+static const uint8_t G10 = 10;
+static const uint8_t G11 = 11;
+static const uint8_t G12 = 12;
+static const uint8_t G13 = 13;
+static const uint8_t G14 = 14;
+static const uint8_t G15 = 15;
+static const uint8_t G39 = 39;
+static const uint8_t G40 = 40;
+static const uint8_t G41 = 41;
+static const uint8_t G42 = 42;
+static const uint8_t G43 = 43;
+static const uint8_t G44 = 44;
+static const uint8_t G46 = 46;
+
+static const uint8_t ADC1 = 7;
+static const uint8_t ADC2 = 8;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_station/pins_arduino.h b/variants/m5stack_station/pins_arduino.h
new file mode 100644
index 00000000000..d8285fe88b6
--- /dev/null
+++ b/variants/m5stack_station/pins_arduino.h
@@ -0,0 +1,50 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t TXD1 = 14;
+static const uint8_t RXD1 = 13;
+
+static const uint8_t TXD2 = 17;
+static const uint8_t RXD2 = 16;
+
+static const uint8_t SDA = 32;
+static const uint8_t SCL = 33;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = -1;
+static const uint8_t SCK = 18;
+
+static const uint8_t G1 = 1;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G13 = 13;
+static const uint8_t G14 = 14;
+static const uint8_t G16 = 16;
+static const uint8_t G17 = 17;
+static const uint8_t G18 = 18;
+static const uint8_t G19 = 19;
+static const uint8_t G23 = 23;
+static const uint8_t G25 = 25;
+static const uint8_t G26 = 26;
+static const uint8_t G32 = 32;
+static const uint8_t G33 = 33;
+static const uint8_t G35 = 35;
+static const uint8_t G36 = 36;
+static const uint8_t G37 = 37;
+static const uint8_t G38 = 38;
+static const uint8_t G39 = 39;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t ADC1 = 35;
+static const uint8_t ADC2 = 36;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_stickc/pins_arduino.h b/variants/m5stack_stickc/pins_arduino.h
new file mode 100644
index 00000000000..1948afc96d7
--- /dev/null
+++ b/variants/m5stack_stickc/pins_arduino.h
@@ -0,0 +1,33 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 32;
+static const uint8_t SCL = 33;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 15;
+static const uint8_t MISO = 36;
+static const uint8_t SCK = 13;
+
+static const uint8_t G9 = 9;
+static const uint8_t G10 = 10;
+static const uint8_t G37 = 37;
+static const uint8_t G39 = 39;
+static const uint8_t G32 = 32;
+static const uint8_t G33 = 33;
+static const uint8_t G26 = 26;
+static const uint8_t G36 = 36;
+static const uint8_t G0 = 0;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t ADC1 = 35;
+static const uint8_t ADC2 = 36;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_stickc_plus/pins_arduino.h b/variants/m5stack_stickc_plus/pins_arduino.h
new file mode 100644
index 00000000000..1948afc96d7
--- /dev/null
+++ b/variants/m5stack_stickc_plus/pins_arduino.h
@@ -0,0 +1,33 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 32;
+static const uint8_t SCL = 33;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 15;
+static const uint8_t MISO = 36;
+static const uint8_t SCK = 13;
+
+static const uint8_t G9 = 9;
+static const uint8_t G10 = 10;
+static const uint8_t G37 = 37;
+static const uint8_t G39 = 39;
+static const uint8_t G32 = 32;
+static const uint8_t G33 = 33;
+static const uint8_t G26 = 26;
+static const uint8_t G36 = 36;
+static const uint8_t G0 = 0;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t ADC1 = 35;
+static const uint8_t ADC2 = 36;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_stickc_plus2/pins_arduino.h b/variants/m5stack_stickc_plus2/pins_arduino.h
new file mode 100644
index 00000000000..1948afc96d7
--- /dev/null
+++ b/variants/m5stack_stickc_plus2/pins_arduino.h
@@ -0,0 +1,33 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 32;
+static const uint8_t SCL = 33;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 15;
+static const uint8_t MISO = 36;
+static const uint8_t SCK = 13;
+
+static const uint8_t G9 = 9;
+static const uint8_t G10 = 10;
+static const uint8_t G37 = 37;
+static const uint8_t G39 = 39;
+static const uint8_t G32 = 32;
+static const uint8_t G33 = 33;
+static const uint8_t G26 = 26;
+static const uint8_t G36 = 36;
+static const uint8_t G0 = 0;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t ADC1 = 35;
+static const uint8_t ADC2 = 36;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_timer_cam/pins_arduino.h b/variants/m5stack_timer_cam/pins_arduino.h
index 64b442d452d..8c1196425b9 100644
--- a/variants/m5stack_timer_cam/pins_arduino.h
+++ b/variants/m5stack_timer_cam/pins_arduino.h
@@ -3,13 +3,8 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -17,6 +12,11 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 4;
 static const uint8_t SCL = 13;
 
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
 static const uint8_t G23 = 23;
 static const uint8_t G25 = 25;
 static const uint8_t G27 = 27;
diff --git a/variants/m5stack_tough/pins_arduino.h b/variants/m5stack_tough/pins_arduino.h
new file mode 100644
index 00000000000..f9d5b8c1a72
--- /dev/null
+++ b/variants/m5stack_tough/pins_arduino.h
@@ -0,0 +1,49 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 32;
+static const uint8_t SCL = 33;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 38;
+static const uint8_t SCK = 18;
+
+static const uint8_t G23 = 23;
+static const uint8_t G38 = 38;
+static const uint8_t G18 = 18;
+static const uint8_t G3 = 3;
+static const uint8_t G13 = 13;
+static const uint8_t G21 = 21;
+static const uint8_t G32 = 32;
+static const uint8_t G27 = 27;
+static const uint8_t G2 = 2;
+static const uint8_t G35 = 35;
+static const uint8_t G36 = 36;
+static const uint8_t G25 = 25;
+static const uint8_t G26 = 26;
+static const uint8_t G1 = 1;
+static const uint8_t G14 = 14;
+static const uint8_t G22 = 22;
+static const uint8_t G33 = 33;
+static const uint8_t G19 = 19;
+static const uint8_t G0 = 0;
+static const uint8_t G34 = 34;
+
+static const uint8_t G12 = 12;
+static const uint8_t G15 = 15;
+static const uint8_t G17 = 17;
+static const uint8_t G5 = 5;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t ADC1 = 35;
+static const uint8_t ADC2 = 36;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_unit_cam/pins_arduino.h b/variants/m5stack_unit_cam/pins_arduino.h
new file mode 100644
index 00000000000..453e1c41516
--- /dev/null
+++ b/variants/m5stack_unit_cam/pins_arduino.h
@@ -0,0 +1,50 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 4;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 17;
+static const uint8_t SCL = 16;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t G23 = 23;
+static const uint8_t G25 = 25;
+static const uint8_t G27 = 27;
+static const uint8_t G22 = 22;
+static const uint8_t G26 = 26;
+static const uint8_t G21 = 21;
+static const uint8_t G32 = 32;
+static const uint8_t G35 = 35;
+static const uint8_t G34 = 34;
+static const uint8_t G5 = 5;
+static const uint8_t G39 = 39;
+static const uint8_t G18 = 18;
+static const uint8_t G36 = 36;
+static const uint8_t G19 = 19;
+static const uint8_t G15 = 15;
+
+static const uint8_t G2 = 2;
+static const uint8_t G33 = 33;
+
+static const uint8_t G13 = 13;
+static const uint8_t G4 = 4;
+
+static const uint8_t G0 = 0;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t ADC1 = 35;
+static const uint8_t ADC2 = 36;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stack_unit_cams3/pins_arduino.h b/variants/m5stack_unit_cams3/pins_arduino.h
new file mode 100644
index 00000000000..595da52bf29
--- /dev/null
+++ b/variants/m5stack_unit_cams3/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t TXD2 = 1;
+static const uint8_t RXD2 = 2;
+
+static const uint8_t SDA = 13;
+static const uint8_t SCL = 15;
+
+// Modified elsewhere
+static const uint8_t SS = -1;
+static const uint8_t MOSI = -1;
+static const uint8_t MISO = -1;
+static const uint8_t SCK = -1;
+
+static const uint8_t G0 = 0;
+static const uint8_t G1 = 1;
+static const uint8_t G2 = 2;
+static const uint8_t G3 = 3;
+static const uint8_t G4 = 4;
+static const uint8_t G5 = 5;
+static const uint8_t G6 = 6;
+static const uint8_t G7 = 7;
+static const uint8_t G8 = 8;
+static const uint8_t G9 = 9;
+static const uint8_t G10 = 10;
+static const uint8_t G11 = 11;
+static const uint8_t G12 = 12;
+static const uint8_t G13 = 13;
+static const uint8_t G14 = 14;
+static const uint8_t G15 = 15;
+static const uint8_t G39 = 39;
+static const uint8_t G40 = 40;
+static const uint8_t G41 = 41;
+static const uint8_t G42 = 42;
+static const uint8_t G43 = 43;
+static const uint8_t G44 = 44;
+static const uint8_t G46 = 46;
+
+static const uint8_t ADC1 = 7;
+static const uint8_t ADC2 = 8;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/m5stick_c/pins_arduino.h b/variants/m5stick_c/pins_arduino.h
deleted file mode 100644
index 048d9b5e50b..00000000000
--- a/variants/m5stick_c/pins_arduino.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-static const uint8_t TX = 1;
-static const uint8_t RX = 3;
-
-static const uint8_t SDA = 32;
-static const uint8_t SCL = 33;
-
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 15;
-static const uint8_t MISO  = 36;
-static const uint8_t SCK   = 13;
-
-static const uint8_t G9 = 9;
-static const uint8_t G10 = 10;
-static const uint8_t G37 = 37;
-static const uint8_t G39 = 39;
-static const uint8_t G32 = 32;
-static const uint8_t G33 = 33;
-static const uint8_t G26 = 26;
-static const uint8_t G36 = 36;
-static const uint8_t G0 = 0;
-
-static const uint8_t DAC1 = 25;
-static const uint8_t DAC2 = 26;
-
-static const uint8_t ADC1 = 35;
-static const uint8_t ADC2 = 36;
-
-#endif /* Pins_Arduino_h */
diff --git a/variants/magicbit/pins_arduino.h b/variants/magicbit/pins_arduino.h
index 3073ade6100..093cfcc3da0 100644
--- a/variants/magicbit/pins_arduino.h
+++ b/variants/magicbit/pins_arduino.h
@@ -3,24 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -66,6 +58,9 @@ static const uint8_t MOTOR1A = 27;
 static const uint8_t MOTOR1B = 18;
 static const uint8_t MOTOR2A = 16;
 static const uint8_t MOTOR2B = 17;
-static const uint8_t LED_BUILTIN=16;
+
+static const uint8_t LED_BUILTIN = 16;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/makergo_c3_supermini/pins_arduino.h b/variants/makergo_c3_supermini/pins_arduino.h
new file mode 100644
index 00000000000..349e2481d9a
--- /dev/null
+++ b/variants/makergo_c3_supermini/pins_arduino.h
@@ -0,0 +1,33 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define TX1 0
+#define RX1 1
+
+static const uint8_t LED_BUILTIN = 8;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t BOOT_BUILTIN = 9;  // built-in boot button
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/metro_esp-32/pins_arduino.h b/variants/metro_esp-32/pins_arduino.h
index d2c737dc4ea..675ea79bd6e 100644
--- a/variants/metro_esp-32/pins_arduino.h
+++ b/variants/metro_esp-32/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -22,4 +14,9 @@ static const uint8_t SCL = 22;
 
 static const uint8_t ADR = 12;
 
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
 #endif /* Pins_Arduino_h */
diff --git a/variants/mgbot-iotik32a/pins_arduino.h b/variants/mgbot-iotik32a/pins_arduino.h
index 41345caeae4..10d1033b196 100644
--- a/variants/mgbot-iotik32a/pins_arduino.h
+++ b/variants/mgbot-iotik32a/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 4;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -28,10 +20,10 @@ static const uint8_t RX2 = 16;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/mgbot-iotik32b/pins_arduino.h b/variants/mgbot-iotik32b/pins_arduino.h
index e34f62713fc..05678e74a0a 100644
--- a/variants/mgbot-iotik32b/pins_arduino.h
+++ b/variants/mgbot-iotik32b/pins_arduino.h
@@ -3,21 +3,13 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 18;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 // IR receiver
 static const uint8_t IR = 27;
-#define IR_RECV IR
+#define IR_RECV  IR
 #define IR_INPUT IR
 
 static const uint8_t TX = 1;
@@ -33,10 +25,10 @@ static const uint8_t RX2 = 16;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/mhetesp32devkit/pins_arduino.h b/variants/mhetesp32devkit/pins_arduino.h
index ee2112b9fa6..8e1d00416d1 100644
--- a/variants/mhetesp32devkit/pins_arduino.h
+++ b/variants/mhetesp32devkit/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN 
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -21,10 +13,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/mhetesp32minikit/pins_arduino.h b/variants/mhetesp32minikit/pins_arduino.h
index ee2112b9fa6..8e1d00416d1 100644
--- a/variants/mhetesp32minikit/pins_arduino.h
+++ b/variants/mhetesp32minikit/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN 
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -21,10 +13,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/micro_s2/pins_arduino.h b/variants/micro_s2/pins_arduino.h
new file mode 100644
index 00000000000..422799478fc
--- /dev/null
+++ b/variants/micro_s2/pins_arduino.h
@@ -0,0 +1,75 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x239A
+#define USB_PID          0x80C5
+#define USB_MANUFACTURER "microDev"
+#define USB_PRODUCT      "microS2"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+static const uint8_t LED_BUILTIN = 21;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t PIXEL_BUILTIN = 33;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (PIXEL_BUILTIN + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t BUTTON_BUILTIN = 0;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/mpython/pins_arduino.h b/variants/mpython/pins_arduino.h
index 5ecb2a555a3..98994e68aab 100644
--- a/variants/mpython/pins_arduino.h
+++ b/variants/mpython/pins_arduino.h
@@ -3,24 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 23;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -53,7 +45,6 @@ static const uint8_t T9 = 32;
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
 
-
 static const uint8_t P0 = 33;
 static const uint8_t P1 = 32;
 static const uint8_t P2 = 35;
@@ -86,5 +77,4 @@ static const uint8_t SOUND = 36;
 static const uint8_t LIGHT = 39;
 static const uint8_t BUZZER = 16;
 
-
 #endif /* Pins_Arduino_h */
diff --git a/variants/namino_arancio/pins_arduino.h b/variants/namino_arancio/pins_arduino.h
new file mode 100644
index 00000000000..78000a477b0
--- /dev/null
+++ b/variants/namino_arancio/pins_arduino.h
@@ -0,0 +1,197 @@
+//
+// Copyright (c) 2023 Namino Team, version: 1.0.20 @ 2023-10-06
+//
+//
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+#define NAMINO_ARANCIO_BOARD
+
+/* Begin Pins on ESP32-S3-WROOM-1U-N4R8 */
+static const uint8_t GPIO4 = 4;
+static const uint8_t GPIO5 = 5;
+static const uint8_t GPIO6 = 6;
+static const uint8_t GPIO7 = 7;
+static const uint8_t GPIO15 = 15;
+static const uint8_t GPIO16 = 16;
+static const uint8_t GPIO17 = 17;
+static const uint8_t GPIO18 = 18;
+static const uint8_t GPIO8 = 8;
+static const uint8_t GPIO19 = 19;
+static const uint8_t GPIO20 = 20;
+static const uint8_t GPIO3 = 3;
+static const uint8_t GPIO46 = 46;
+static const uint8_t GPIO9 = 9;
+static const uint8_t GPIO10 = 10;
+static const uint8_t GPIO11 = 11;
+static const uint8_t GPIO12 = 12;
+static const uint8_t GPIO13 = 13;
+static const uint8_t GPIO14 = 14;
+static const uint8_t GPIO21 = 21;
+static const uint8_t GPIO47 = 47;
+static const uint8_t GPIO48 = 48;
+static const uint8_t GPIO45 = 45;
+static const uint8_t GPIO0 = 0;
+static const uint8_t GPIO35 = 35;
+static const uint8_t GPIO36 = 36;
+static const uint8_t GPIO37 = 37;
+static const uint8_t GPIO38 = 38;
+static const uint8_t GPIO39 = 39;
+static const uint8_t GPIO40 = 40;
+static const uint8_t GPIO41 = 41;
+static const uint8_t GPIO42 = 42;
+static const uint8_t GPIO44 = 44;
+static const uint8_t GPIO43 = 43;
+static const uint8_t GPIO2 = 2;
+static const uint8_t GPIO1 = 1;
+
+static const uint8_t RESET_ADD_ON = GPIO46;
+static const uint8_t SS = GPIO10;
+static const uint8_t MOSI = GPIO11;
+static const uint8_t MISO = GPIO13;
+static const uint8_t SCK = GPIO12;
+// SPI SD CARD
+static const uint8_t CS_SDCARD = GPIO2;
+// prog pins
+static const uint8_t BOOT_MODE = GPIO47;
+static const uint8_t ISP_TX = GPIO17;
+static const uint8_t ISP_RX = GPIO18;
+static const uint8_t NM_RESET = GPIO48;
+/* End Pins on ESP32-S3-WROOM-1U-N4R8 */
+
+/* Begin Analog Pins on ESP32-S3-WROOM-1U-N4R8 */
+static const uint8_t ADC1_CH3 = GPIO4;
+static const uint8_t ADC1_CH4 = GPIO5;
+static const uint8_t ADC1_CH5 = GPIO6;
+static const uint8_t ADC1_CH6 = GPIO7;
+static const uint8_t ADC2_CH4 = GPIO15;
+static const uint8_t ADC2_CH5 = GPIO16;
+static const uint8_t ADC2_CH6 = GPIO17;
+static const uint8_t ADC2_CH7 = GPIO18;
+static const uint8_t ADC1_CH7 = GPIO8;
+static const uint8_t ADC2_CH8 = GPIO19;
+static const uint8_t ADC2_CH9 = GPIO20;
+static const uint8_t ADC1_CH2 = GPIO3;
+static const uint8_t ADC1_CH8 = GPIO9;
+static const uint8_t ADC1_CH9 = GPIO10;
+static const uint8_t ADC2_CH0 = GPIO11;
+static const uint8_t ADC2_CH1 = GPIO12;
+static const uint8_t ADC2_CH2 = GPIO13;
+static const uint8_t ADC2_CH3 = GPIO14;
+static const uint8_t ADC1_CH1 = GPIO2;
+static const uint8_t ADC1_CH0 = GPIO1;
+/* End Analog Pins on ESP32-S3-WROOM-1U-N4R8 */
+
+/* Begin Touch Pins on ESP32-S3-WROOM-1U-N4R8 */
+static const uint8_t TOUCH4 = GPIO4;
+static const uint8_t TOUCH5 = GPIO5;
+static const uint8_t TOUCH6 = GPIO6;
+static const uint8_t TOUCH7 = GPIO7;
+static const uint8_t TOUCH8 = GPIO8;
+static const uint8_t TOUCH3 = GPIO3;
+static const uint8_t TOUCH9 = GPIO9;
+static const uint8_t TOUCH10 = GPIO10;
+static const uint8_t TOUCH11 = GPIO11;
+static const uint8_t TOUCH12 = GPIO12;
+static const uint8_t TOUCH13 = GPIO13;
+static const uint8_t TOUCH14 = GPIO14;
+static const uint8_t TOUCH2 = GPIO2;
+static const uint8_t TOUCH1 = GPIO1;
+/* End Touch Pins on ESP32-S3-WROOM-1U-N4R8 */
+
+static const uint8_t TX = GPIO17;
+static const uint8_t RX = GPIO18;
+
+static const uint8_t SDA = GPIO1;
+static const uint8_t SCL = GPIO0;
+static const uint8_t NAMINO_ARANCIO_I2C_SDA = SDA;
+static const uint8_t NAMINO_ARANCIO_I2C_SCL = SCL;
+static const uint8_t NM_I2C_SDA = SDA;
+static const uint8_t NM_I2C_SCL = SCL;
+
+static const uint8_t A0 = ADC1_CH0;
+static const uint8_t A1 = ADC1_CH1;
+static const uint8_t A2 = ADC1_CH2;
+static const uint8_t A3 = ADC1_CH3;
+static const uint8_t A4 = ADC1_CH4;
+static const uint8_t A5 = ADC1_CH5;
+static const uint8_t A6 = ADC1_CH6;
+static const uint8_t A7 = ADC1_CH7;
+static const uint8_t A8 = ADC2_CH0;
+static const uint8_t A9 = ADC2_CH1;
+static const uint8_t A10 = ADC2_CH2;
+static const uint8_t A11 = ADC2_CH3;
+static const uint8_t A12 = ADC2_CH4;
+static const uint8_t A13 = ADC2_CH5;
+static const uint8_t A14 = ADC2_CH6;
+static const uint8_t A15 = ADC2_CH7;
+
+static const uint8_t DAC1 = 0;
+static const uint8_t DAC2 = 0;
+
+/* Begin Arduino naming */
+static const uint8_t RESET_ARDUINO = GPIO46;
+static const uint8_t PC0 = GPIO3;
+static const uint8_t PC1 = GPIO4;
+static const uint8_t PC2 = GPIO5;
+static const uint8_t PC3 = GPIO6;
+static const uint8_t PC4 = GPIO7;
+static const uint8_t PC5 = GPIO8;
+static const uint8_t PB5 = GPIO35;
+static const uint8_t PB4 = GPIO36;
+static const uint8_t PB3 = GPIO37;
+static const uint8_t PB2 = GPIO38;
+static const uint8_t PB1 = GPIO39;
+static const uint8_t PB0 = GPIO40;
+static const uint8_t PD7 = GPIO41;
+static const uint8_t PD6 = GPIO42;
+static const uint8_t PD5 = GPIO21;
+static const uint8_t PD4 = GPIO16;
+static const uint8_t PD3 = GPIO14;
+static const uint8_t PD2 = GPIO9;
+static const uint8_t PD1 = GPIO17;
+static const uint8_t PD0 = GPIO18;
+/* End Arduino naming */
+
+/* Begin alternate naming */
+static const uint8_t J1_io0 = SCL;
+
+static const uint8_t J2_35 = PB5;
+static const uint8_t J2_36 = PB4;
+static const uint8_t J2_37 = PB3;
+static const uint8_t J2_38 = PB2;
+static const uint8_t J2_39 = PB1;
+static const uint8_t J2_40 = PB0;
+
+static const uint8_t J3_io8 = PD7;
+static const uint8_t J3_7 = PD6;
+static const uint8_t J3_21 = PD5;
+static const uint8_t J3_16 = PD4;
+static const uint8_t J3_14 = PD3;
+static const uint8_t J3_9 = PD2;
+static const uint8_t J3_17 = TX;
+static const uint8_t J3_18 = RX;
+
+static const uint8_t J4_cs_io2 = CS_SDCARD;
+static const uint8_t J4_sclk = SCK;
+static const uint8_t J4_mosi = MOSI;
+static const uint8_t J4_miso = MISO;
+
+static const uint8_t J9_io3 = PC0;
+static const uint8_t J9_4 = PC1;
+static const uint8_t J9_5 = PC2;
+static const uint8_t J9_6 = PC3;
+static const uint8_t J9_7 = PC4;
+static const uint8_t J9_8 = PC5;
+
+static const uint8_t J10_enc_A = 0;
+static const uint8_t J10_enc_B = 0;
+static const uint8_t J10_sw = 0;
+/* End alternate naming */
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/namino_bianco/pins_arduino.h b/variants/namino_bianco/pins_arduino.h
new file mode 100644
index 00000000000..48c94493582
--- /dev/null
+++ b/variants/namino_bianco/pins_arduino.h
@@ -0,0 +1,197 @@
+//
+// Copyright (c) 2023 Namino Team, bianco version: 1.0.1 @ 2023-10-06
+//
+//
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+#define NAMINO_BIANCO_BOARD
+
+/* Begin Pins on ESP32-S3-WROOM-1U-N4R8 */
+static const uint8_t GPIO4 = 4;
+static const uint8_t GPIO5 = 5;
+static const uint8_t GPIO6 = 6;
+static const uint8_t GPIO7 = 7;
+static const uint8_t GPIO15 = 15;
+static const uint8_t GPIO16 = 16;
+static const uint8_t GPIO17 = 17;
+static const uint8_t GPIO18 = 18;
+static const uint8_t GPIO8 = 8;
+static const uint8_t GPIO19 = 19;
+static const uint8_t GPIO20 = 20;
+static const uint8_t GPIO3 = 3;
+static const uint8_t GPIO46 = 46;
+static const uint8_t GPIO9 = 9;
+static const uint8_t GPIO10 = 10;
+static const uint8_t GPIO11 = 11;
+static const uint8_t GPIO12 = 12;
+static const uint8_t GPIO13 = 13;
+static const uint8_t GPIO14 = 14;
+static const uint8_t GPIO21 = 21;
+static const uint8_t GPIO47 = 47;
+static const uint8_t GPIO48 = 48;
+static const uint8_t GPIO45 = 45;
+static const uint8_t GPIO0 = 0;
+static const uint8_t GPIO35 = 35;
+static const uint8_t GPIO36 = 36;
+static const uint8_t GPIO37 = 37;
+static const uint8_t GPIO38 = 38;
+static const uint8_t GPIO39 = 39;
+static const uint8_t GPIO40 = 40;
+static const uint8_t GPIO41 = 41;
+static const uint8_t GPIO42 = 42;
+static const uint8_t GPIO44 = 44;
+static const uint8_t GPIO43 = 43;
+static const uint8_t GPIO2 = 2;
+static const uint8_t GPIO1 = 1;
+
+static const uint8_t SS = GPIO48;
+static const uint8_t MOSI = GPIO11;
+static const uint8_t MISO = GPIO13;
+static const uint8_t SCK = GPIO12;
+
+/* End Pins on ESP32-S3-WROOM-1U-N4R8 */
+
+/* Begin Analog Pins on ESP32-S3-WROOM-1U-N4R8 */
+static const uint8_t ADC1_CH3 = GPIO4;
+static const uint8_t ADC1_CH4 = GPIO5;
+static const uint8_t ADC1_CH5 = GPIO6;
+static const uint8_t ADC1_CH6 = GPIO7;
+static const uint8_t ADC2_CH4 = GPIO15;
+static const uint8_t ADC2_CH5 = GPIO16;
+static const uint8_t ADC2_CH6 = GPIO17;
+static const uint8_t ADC2_CH7 = GPIO18;
+static const uint8_t ADC1_CH7 = GPIO8;
+static const uint8_t ADC2_CH8 = GPIO19;
+static const uint8_t ADC2_CH9 = GPIO20;
+static const uint8_t ADC1_CH2 = GPIO3;
+static const uint8_t ADC1_CH8 = GPIO9;
+static const uint8_t ADC1_CH9 = GPIO10;
+static const uint8_t ADC2_CH0 = GPIO11;
+static const uint8_t ADC2_CH1 = GPIO12;
+static const uint8_t ADC2_CH2 = GPIO13;
+static const uint8_t ADC2_CH3 = GPIO14;
+static const uint8_t ADC1_CH1 = GPIO2;
+static const uint8_t ADC1_CH0 = GPIO1;
+/* End Analog Pins on ESP32-S3-WROOM-1U-N4R8 */
+
+/* Begin Touch Pins on ESP32-S3-WROOM-1U-N4R8 */
+static const uint8_t TOUCH4 = GPIO4;
+static const uint8_t TOUCH5 = GPIO5;
+static const uint8_t TOUCH6 = GPIO6;
+static const uint8_t TOUCH7 = GPIO7;
+static const uint8_t TOUCH8 = GPIO8;
+static const uint8_t TOUCH3 = GPIO3;
+static const uint8_t TOUCH9 = GPIO9;
+static const uint8_t TOUCH10 = GPIO10;
+static const uint8_t TOUCH11 = GPIO11;
+static const uint8_t TOUCH12 = GPIO12;
+static const uint8_t TOUCH13 = GPIO13;
+static const uint8_t TOUCH14 = GPIO14;
+static const uint8_t TOUCH2 = GPIO2;
+static const uint8_t TOUCH1 = GPIO1;
+/* End Touch Pins on ESP32-S3-WROOM-1U-N4R8 */
+
+static const uint8_t TX = GPIO17;
+static const uint8_t RX = GPIO18;
+
+static const uint8_t SDA = GPIO1;
+static const uint8_t SCL = GPIO2;
+static const uint8_t NM_I2C_SDA = SDA;
+static const uint8_t NM_I2C_SCL = SCL;
+
+static const uint8_t A0 = ADC1_CH2;
+static const uint8_t A1 = ADC1_CH3;
+static const uint8_t A2 = ADC1_CH4;
+static const uint8_t A3 = ADC1_CH5;
+static const uint8_t A4 = ADC1_CH6;
+static const uint8_t A5 = ADC2_CH4;
+static const uint8_t A6 = 0;
+static const uint8_t A7 = 0;
+static const uint8_t A8 = 0;
+static const uint8_t A9 = 0;
+static const uint8_t A10 = 0;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 0;
+static const uint8_t A13 = 0;
+static const uint8_t A14 = 0;
+static const uint8_t A15 = 0;
+
+static const uint8_t DAC1 = 0;
+static const uint8_t DAC2 = 0;
+
+/* Begin Arduino naming */
+static const uint8_t RESET_ARDUINO = 0;
+static const uint8_t PC0 = GPIO3;
+static const uint8_t PC1 = GPIO4;
+static const uint8_t PC2 = GPIO5;
+static const uint8_t PC3 = GPIO6;
+static const uint8_t PC4 = GPIO7;
+static const uint8_t PC5 = GPIO15;
+static const uint8_t PB5 = GPIO35;
+static const uint8_t PB4 = GPIO36;
+static const uint8_t PB3 = GPIO37;
+static const uint8_t PB2 = GPIO38;
+static const uint8_t PB1 = GPIO39;
+static const uint8_t PB0 = GPIO40;
+static const uint8_t PD7 = GPIO41;
+static const uint8_t PD6 = GPIO42;
+static const uint8_t PD5 = GPIO21;
+static const uint8_t PD4 = GPIO16;
+static const uint8_t PD3 = GPIO14;
+static const uint8_t PD2 = GPIO47;
+static const uint8_t PD1 = GPIO17;
+static const uint8_t PD0 = GPIO18;
+/* End Arduino naming */
+
+/* Begin alternate naming */
+static const uint8_t PB_SCL = SCL;
+static const uint8_t PB_SDA = SDA;
+static const uint8_t PB_35 = PB5;
+static const uint8_t PB_36 = PB4;
+static const uint8_t PB_37 = PB3;
+static const uint8_t PB_38 = PB2;
+static const uint8_t PB_39 = PB1;
+static const uint8_t PB_40 = PB0;
+
+static const uint8_t PD_io41 = PD7;
+static const uint8_t PD_42 = PD6;
+static const uint8_t PD_21 = PD5;
+static const uint8_t PD_16 = PD4;
+static const uint8_t PD_14 = PD3;
+static const uint8_t PD_47 = PD2;
+static const uint8_t PD_17 = TX;
+static const uint8_t PD_18 = RX;
+
+static const uint8_t PC_io3 = PC0;
+static const uint8_t PC_4 = PC1;
+static const uint8_t PC_5 = PC2;
+static const uint8_t PC_6 = PC3;
+static const uint8_t PC_7 = PC4;
+static const uint8_t PC_15 = PC5;
+
+static const uint8_t M1_3_AN = GPIO3;
+static const uint8_t M1_RST = 0;
+static const uint8_t M1_48_CS = SS;
+static const uint8_t M1_12_SCK = SCK;
+static const uint8_t M1_13_MISO = MISO;
+static const uint8_t M1_11_MOSI = MOSI;
+static const uint8_t M2_47_PWM = GPIO47;
+static const uint8_t M2_14_INT = GPIO14;
+static const uint8_t M2_18_RX = GPIO18;
+static const uint8_t M2_17_TX = GPIO17;
+static const uint8_t M2_2_SCL = SCL;
+static const uint8_t M2_1_SDA = SDA;
+
+static const uint8_t J3_SCL = SCL;
+static const uint8_t J3_SDA = SDA;
+
+/* End alternate naming */
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/namino_rosso/pins_arduino.h b/variants/namino_rosso/pins_arduino.h
new file mode 100644
index 00000000000..90508e90257
--- /dev/null
+++ b/variants/namino_rosso/pins_arduino.h
@@ -0,0 +1,197 @@
+//
+// Copyright (c) 2023 Namino Team, version: 1.0.20 @ 2023-10-06
+//
+//
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+#define NAMINO_ROSSO_BOARD
+
+/* Begin Pins on ESP32-S3-WROOM-1U-N4R8 */
+static const uint8_t GPIO4 = 4;
+static const uint8_t GPIO5 = 5;
+static const uint8_t GPIO6 = 6;
+static const uint8_t GPIO7 = 7;
+static const uint8_t GPIO15 = 15;
+static const uint8_t GPIO16 = 16;
+static const uint8_t GPIO17 = 17;
+static const uint8_t GPIO18 = 18;
+static const uint8_t GPIO8 = 8;
+static const uint8_t GPIO19 = 19;
+static const uint8_t GPIO20 = 20;
+static const uint8_t GPIO3 = 3;
+static const uint8_t GPIO46 = 46;
+static const uint8_t GPIO9 = 9;
+static const uint8_t GPIO10 = 10;
+static const uint8_t GPIO11 = 11;
+static const uint8_t GPIO12 = 12;
+static const uint8_t GPIO13 = 13;
+static const uint8_t GPIO14 = 14;
+static const uint8_t GPIO21 = 21;
+static const uint8_t GPIO47 = 47;
+static const uint8_t GPIO48 = 48;
+static const uint8_t GPIO45 = 45;
+static const uint8_t GPIO0 = 0;
+static const uint8_t GPIO35 = 35;
+static const uint8_t GPIO36 = 36;
+static const uint8_t GPIO37 = 37;
+static const uint8_t GPIO38 = 38;
+static const uint8_t GPIO39 = 39;
+static const uint8_t GPIO40 = 40;
+static const uint8_t GPIO41 = 41;
+static const uint8_t GPIO42 = 42;
+static const uint8_t GPIO44 = 44;
+static const uint8_t GPIO43 = 43;
+static const uint8_t GPIO2 = 2;
+static const uint8_t GPIO1 = 1;
+
+static const uint8_t RESET_ADD_ON = GPIO46;
+static const uint8_t SS = GPIO10;
+static const uint8_t MOSI = GPIO11;
+static const uint8_t MISO = GPIO13;
+static const uint8_t SCK = GPIO12;
+// SPI SD CARD
+static const uint8_t CS_SDCARD = GPIO2;
+// prog pins
+static const uint8_t BOOT_MODE = GPIO47;
+static const uint8_t ISP_TX = GPIO17;
+static const uint8_t ISP_RX = GPIO18;
+static const uint8_t NM_RESET = GPIO48;
+/* End Pins on ESP32-S3-WROOM-1U-N4R8 */
+
+/* Begin Analog Pins on ESP32-S3-WROOM-1U-N4R8 */
+static const uint8_t ADC1_CH3 = GPIO4;
+static const uint8_t ADC1_CH4 = GPIO5;
+static const uint8_t ADC1_CH5 = GPIO6;
+static const uint8_t ADC1_CH6 = GPIO7;
+static const uint8_t ADC2_CH4 = GPIO15;
+static const uint8_t ADC2_CH5 = GPIO16;
+static const uint8_t ADC2_CH6 = GPIO17;
+static const uint8_t ADC2_CH7 = GPIO18;
+static const uint8_t ADC1_CH7 = GPIO8;
+static const uint8_t ADC2_CH8 = GPIO19;
+static const uint8_t ADC2_CH9 = GPIO20;
+static const uint8_t ADC1_CH2 = GPIO3;
+static const uint8_t ADC1_CH8 = GPIO9;
+static const uint8_t ADC1_CH9 = GPIO10;
+static const uint8_t ADC2_CH0 = GPIO11;
+static const uint8_t ADC2_CH1 = GPIO12;
+static const uint8_t ADC2_CH2 = GPIO13;
+static const uint8_t ADC2_CH3 = GPIO14;
+static const uint8_t ADC1_CH1 = GPIO2;
+static const uint8_t ADC1_CH0 = GPIO1;
+/* End Analog Pins on ESP32-S3-WROOM-1U-N4R8 */
+
+/* Begin Touch Pins on ESP32-S3-WROOM-1U-N4R8 */
+static const uint8_t TOUCH4 = GPIO4;
+static const uint8_t TOUCH5 = GPIO5;
+static const uint8_t TOUCH6 = GPIO6;
+static const uint8_t TOUCH7 = GPIO7;
+static const uint8_t TOUCH8 = GPIO8;
+static const uint8_t TOUCH3 = GPIO3;
+static const uint8_t TOUCH9 = GPIO9;
+static const uint8_t TOUCH10 = GPIO10;
+static const uint8_t TOUCH11 = GPIO11;
+static const uint8_t TOUCH12 = GPIO12;
+static const uint8_t TOUCH13 = GPIO13;
+static const uint8_t TOUCH14 = GPIO14;
+static const uint8_t TOUCH2 = GPIO2;
+static const uint8_t TOUCH1 = GPIO1;
+/* End Touch Pins on ESP32-S3-WROOM-1U-N4R8 */
+
+static const uint8_t TX = GPIO17;
+static const uint8_t RX = GPIO18;
+
+static const uint8_t SDA = GPIO1;
+static const uint8_t SCL = GPIO0;
+static const uint8_t NAMINO_ARANCIO_I2C_SDA = SDA;
+static const uint8_t NAMINO_ARANCIO_I2C_SCL = SCL;
+static const uint8_t NM_I2C_SDA = SDA;
+static const uint8_t NM_I2C_SCL = SCL;
+
+static const uint8_t A0 = ADC1_CH0;
+static const uint8_t A1 = ADC1_CH1;
+static const uint8_t A2 = ADC1_CH2;
+static const uint8_t A3 = ADC1_CH3;
+static const uint8_t A4 = ADC1_CH4;
+static const uint8_t A5 = ADC1_CH5;
+static const uint8_t A6 = ADC1_CH6;
+static const uint8_t A7 = ADC1_CH7;
+static const uint8_t A8 = ADC2_CH0;
+static const uint8_t A9 = ADC2_CH1;
+static const uint8_t A10 = ADC2_CH2;
+static const uint8_t A11 = ADC2_CH3;
+static const uint8_t A12 = ADC2_CH4;
+static const uint8_t A13 = ADC2_CH5;
+static const uint8_t A14 = ADC2_CH6;
+static const uint8_t A15 = ADC2_CH7;
+
+static const uint8_t DAC1 = 0;
+static const uint8_t DAC2 = 0;
+
+/* Begin Arduino naming */
+static const uint8_t RESET_ARDUINO = GPIO46;
+static const uint8_t PC0 = GPIO3;
+static const uint8_t PC1 = GPIO4;
+static const uint8_t PC2 = GPIO5;
+static const uint8_t PC3 = GPIO6;
+static const uint8_t PC4 = GPIO7;
+static const uint8_t PC5 = GPIO8;
+static const uint8_t PB5 = GPIO35;
+static const uint8_t PB4 = GPIO36;
+static const uint8_t PB3 = GPIO37;
+static const uint8_t PB2 = GPIO38;
+static const uint8_t PB1 = GPIO39;
+static const uint8_t PB0 = GPIO40;
+static const uint8_t PD7 = GPIO41;
+static const uint8_t PD6 = GPIO42;
+static const uint8_t PD5 = GPIO21;
+static const uint8_t PD4 = GPIO16;
+static const uint8_t PD3 = GPIO14;
+static const uint8_t PD2 = GPIO9;
+static const uint8_t PD1 = GPIO17;
+static const uint8_t PD0 = GPIO18;
+/* End Arduino naming */
+
+/* Begin alternate naming */
+static const uint8_t J1_io0 = SCL;
+
+static const uint8_t J2_35 = PB5;
+static const uint8_t J2_36 = PB4;
+static const uint8_t J2_37 = PB3;
+static const uint8_t J2_38 = PB2;
+static const uint8_t J2_39 = PB1;
+static const uint8_t J2_40 = PB0;
+
+static const uint8_t J3_io8 = PD7;
+static const uint8_t J3_7 = PD6;
+static const uint8_t J3_21 = PD5;
+static const uint8_t J3_16 = PD4;
+static const uint8_t J3_14 = PD3;
+static const uint8_t J3_9 = PD2;
+static const uint8_t J3_17 = TX;
+static const uint8_t J3_18 = RX;
+
+static const uint8_t J4_cs_io2 = CS_SDCARD;
+static const uint8_t J4_sclk = SCK;
+static const uint8_t J4_mosi = MOSI;
+static const uint8_t J4_miso = MISO;
+
+static const uint8_t J9_io3 = PC0;
+static const uint8_t J9_4 = PC1;
+static const uint8_t J9_5 = PC2;
+static const uint8_t J9_6 = PC3;
+static const uint8_t J9_7 = PC4;
+static const uint8_t J9_8 = PC5;
+
+static const uint8_t J10_enc_A = 0;
+static const uint8_t J10_enc_B = 0;
+static const uint8_t J10_sw = 0;
+/* End alternate naming */
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/nano32/pins_arduino.h b/variants/nano32/pins_arduino.h
index 24f9ac51996..840fd863629 100644
--- a/variants/nano32/pins_arduino.h
+++ b/variants/nano32/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        38
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 16;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t BUILTIN_KEY = 0;
 
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/nina_w10/pins_arduino.h b/variants/nina_w10/pins_arduino.h
index f3ce937dd26..ea1c5ab681d 100644
--- a/variants/nina_w10/pins_arduino.h
+++ b/variants/nina_w10/pins_arduino.h
@@ -3,14 +3,6 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_GREEN = 33;
 static const uint8_t LED_RED = 23;
 static const uint8_t LED_BLUE = 21;
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 12;
 static const uint8_t SCL = 13;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/node32s/pins_arduino.h b/variants/node32s/pins_arduino.h
index df2223aa8ba..e7c7a87e2c6 100644
--- a/variants/node32s/pins_arduino.h
+++ b/variants/node32s/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/nodemcu-32s/pins_arduino.h b/variants/nodemcu-32s/pins_arduino.h
index df2223aa8ba..e7c7a87e2c6 100644
--- a/variants/nodemcu-32s/pins_arduino.h
+++ b/variants/nodemcu-32s/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/nologo_esp32c3_super_mini/pins_arduino.h b/variants/nologo_esp32c3_super_mini/pins_arduino.h
new file mode 100644
index 00000000000..fdcc730c1a0
--- /dev/null
+++ b/variants/nologo_esp32c3_super_mini/pins_arduino.h
@@ -0,0 +1,28 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 8;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/nologo_esp32s3_pico/pins_arduino.h b/variants/nologo_esp32s3_pico/pins_arduino.h
new file mode 100644
index 00000000000..52841688b1b
--- /dev/null
+++ b/variants/nologo_esp32s3_pico/pins_arduino.h
@@ -0,0 +1,37 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = 21;
+#define BUILTIN_LED    LED_BUILTIN
+#define LED_BUILTIN    LED_BUILTIN
+#define RGB_BUILTIN    SOC_GPIO_PIN_COUNT + LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+// SPI - unused but you can create your own definition in your sketch
+static const int8_t SCK = -1;
+static const int8_t MISO = -1;
+static const int8_t MOSI = -1;
+static const int8_t SS = -1;
+
+// I2C - unused but you can create your own definition in your sketch
+static const uint8_t SDA = -1;
+static const uint8_t SCL = -1;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/nora_w10/pins_arduino.h b/variants/nora_w10/pins_arduino.h
new file mode 100644
index 00000000000..a833fbb2440
--- /dev/null
+++ b/variants/nora_w10/pins_arduino.h
@@ -0,0 +1,84 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+// The pin assignments in this file are based on u-blox EVK-NORA-W1, a Arduino compatible board.
+// For your own module design you can freely chose the pins available on the module module pins
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+static const uint8_t RTS = 45;
+static const uint8_t CTS = 6;
+static const uint8_t DTR = 1;
+static const uint8_t DSR = 7;
+
+static const uint8_t SW1 = 46;
+static const uint8_t SW2 = 0;  // BOOT
+static const uint8_t SW3 = 47;
+static const uint8_t SW4 = 48;
+
+static const uint8_t LED_RED = 5;
+static const uint8_t LED_GREEN = 2;
+static const uint8_t LED_BLUE = 8;
+#define BUILTIN_LED LED_BLUE  // backward compatibility
+#define LED_BUILTIN LED_BLUE
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 11;
+static const uint8_t A1 = 12;
+static const uint8_t A2 = 13;
+static const uint8_t A3 = 5;
+static const uint8_t A4 = 15;
+static const uint8_t A5 = 16;
+
+static const uint8_t D0 = 44;  // RX0
+static const uint8_t D1 = 43;  // TX0
+static const uint8_t D2 = 46;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 14;
+static const uint8_t D7 = 10;
+
+static const uint8_t D8 = 33;
+static const uint8_t D9 = 38;
+static const uint8_t D10 = 34;  // SS
+static const uint8_t D11 = 35;  // MOSI
+static const uint8_t D12 = 37;  // MISO
+static const uint8_t D13 = 36;  // SCK
+static const uint8_t SDA1 = 21;
+static const uint8_t SCL1 = 0;
+
+static const uint8_t D14 = 45;  // RTS
+static const uint8_t D15 = 6;   // CTS
+static const uint8_t D16 = 1;   // DTR
+static const uint8_t D17 = 7;   // DSR
+static const uint8_t D18 = 47;
+static const uint8_t D19 = 48;
+static const uint8_t SDA = 18;
+static const uint8_t SCL = 17;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/odroid_esp32/pins_arduino.h b/variants/odroid_esp32/pins_arduino.h
index 36af935e159..f89dfff1bdd 100644
--- a/variants/odroid_esp32/pins_arduino.h
+++ b/variants/odroid_esp32/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -21,10 +13,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 15;
 static const uint8_t SCL = 4;
 
-static const uint8_t SS    = 22;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 22;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
diff --git a/variants/onehorse32dev/pins_arduino.h b/variants/onehorse32dev/pins_arduino.h
index ab100c11435..06364e54f8b 100644
--- a/variants/onehorse32dev/pins_arduino.h
+++ b/variants/onehorse32dev/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 5;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A1 = 37;
diff --git a/variants/openkb/pins_arduino.h b/variants/openkb/pins_arduino.h
index f187d251ee2..0ceccde0a7a 100644
--- a/variants/openkb/pins_arduino.h
+++ b/variants/openkb/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        38
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 16;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -21,10 +13,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -62,7 +54,6 @@ static const uint8_t LDR_PIN = 36;
 static const uint8_t SW1 = 16;
 static const uint8_t SW2 = 14;
 
-
 static const uint8_t BT_LED = 17;
 static const uint8_t WIFI_LED = 2;
 static const uint8_t NTP_LED = 15;
@@ -81,11 +72,12 @@ static const uint8_t OUTPUT2 = 27;
 static const uint8_t SDA0 = 21;
 static const uint8_t SCL0 = 22;
 
+#define WIRE1_PIN_DEFINED 1  // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin)
 static const uint8_t SDA1 = 4;
 static const uint8_t SCL1 = 5;
 
 static const uint8_t KB_GPIO18 = 18;
 static const uint8_t KB_GPIO19 = 19;
-static const uint8_t KB_GPIO23= 23;
+static const uint8_t KB_GPIO23 = 23;
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/oroca_edubot/pins_arduino.h b/variants/oroca_edubot/pins_arduino.h
index 331ccdbd24a..b9129485beb 100644
--- a/variants/oroca_edubot/pins_arduino.h
+++ b/variants/oroca_edubot/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 13;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 17;
 static const uint8_t RX = 16;
@@ -21,18 +13,17 @@ static const uint8_t RX = 16;
 static const uint8_t SDA = 23;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 2;
-static const uint8_t MOSI  = 18;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 5;
+static const uint8_t SS = 2;
+static const uint8_t MOSI = 18;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
 
-
-static const uint8_t A0 = 34; 
+static const uint8_t A0 = 34;
 static const uint8_t A1 = 39;
 static const uint8_t A2 = 36;
 static const uint8_t A3 = 33;
 
-static const uint8_t D0 = 4; 
+static const uint8_t D0 = 4;
 static const uint8_t D1 = 16;
 static const uint8_t D2 = 17;
 static const uint8_t D3 = 22;
@@ -45,7 +36,6 @@ static const uint8_t D8 = 33;
 // vbat measure
 static const uint8_t VBAT = 35;
 
-
 static const uint8_t T0 = 4;
 static const uint8_t T1 = 0;
 static const uint8_t T2 = 2;
diff --git a/variants/pico32/pins_arduino.h b/variants/pico32/pins_arduino.h
index d50715e5c91..3663de76cd4 100644
--- a/variants/pico32/pins_arduino.h
+++ b/variants/pico32/pins_arduino.h
@@ -3,24 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/piranha_esp-32/pins_arduino.h b/variants/piranha_esp-32/pins_arduino.h
index 3e74d0ad69e..57616dac637 100644
--- a/variants/piranha_esp-32/pins_arduino.h
+++ b/variants/piranha_esp-32/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -23,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A11 = 0;
 static const uint8_t A13 = 15;
diff --git a/variants/pocket_32/pins_arduino.h b/variants/pocket_32/pins_arduino.h
index a36a6bb91d7..9c904d04226 100644
--- a/variants/pocket_32/pins_arduino.h
+++ b/variants/pocket_32/pins_arduino.h
@@ -3,19 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 16;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-
-
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -23,10 +13,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/quantum/pins_arduino.h b/variants/quantum/pins_arduino.h
index d50715e5c91..3663de76cd4 100644
--- a/variants/quantum/pins_arduino.h
+++ b/variants/quantum/pins_arduino.h
@@ -3,24 +3,16 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/redpill_esp32s3/pins_arduino.h b/variants/redpill_esp32s3/pins_arduino.h
new file mode 100644
index 00000000000..21ad8b66bf9
--- /dev/null
+++ b/variants/redpill_esp32s3/pins_arduino.h
@@ -0,0 +1,63 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID 0x303A
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + 3;
+#define BUILTIN_LED    LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN    LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 15;
+static const uint8_t MOSI = 16;
+static const uint8_t MISO = 17;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/redpill_esp32s3/tinyuf2.bin b/variants/redpill_esp32s3/tinyuf2.bin
new file mode 100644
index 00000000000..3b10b6f1fc8
Binary files /dev/null and b/variants/redpill_esp32s3/tinyuf2.bin differ
diff --git a/variants/roboheart_hercules/pins_arduino.h b/variants/roboheart_hercules/pins_arduino.h
new file mode 100644
index 00000000000..aaa91f75799
--- /dev/null
+++ b/variants/roboheart_hercules/pins_arduino.h
@@ -0,0 +1,95 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// Motor driver pins
+#define MOTOR_A_IN1 25  //  PHASE/IN1
+#define MOTOR_A_IN2 26  //  ENABLE/IN2
+
+#define MOTOR_B_IN1 27  //  PHASE/IN1
+#define MOTOR_B_IN2 32  //  ENABLE/IN2
+
+#define MOTOR_C_IN1 33  //  PHASE/IN1
+#define MOTOR_C_IN2 4   //  ENABLE/IN2
+
+#define SLEEP_MOTOR_ABC 2  //  nSLEEP
+
+#define LED_ROBOHEART 13             // Built in LED
+#define BUILTIN_LED   LED_ROBOHEART  // backward compatibility
+#define LED_BUILTIN   LED_ROBOHEART
+
+#define BUTTON_ROBOHEART 0  // Button
+
+// I2C IMU sensor
+#define IMU_SDA 21
+#define IMU_SCL 22
+
+#define RXD1 16
+#define TXD1 17
+
+// GSM Vela connector board pins
+#define GSM_PWRKEY  12
+#define GSM_DTR     13
+#define GSM_CTS     15
+#define GSM_RTS     14
+#define GSM_TX      TXD1
+#define GSM_RX      RXD1
+#define BATTERY_PIN 36  // Battery ADC pin
+
+static const uint8_t TX = 35;
+static const uint8_t RX = 34;
+
+static const uint8_t TXD2 = 17;
+static const uint8_t RXD2 = 16;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t G23 = 23;
+static const uint8_t G19 = 19;
+static const uint8_t G18 = 18;
+static const uint8_t G3 = 3;
+static const uint8_t G16 = 16;
+static const uint8_t G21 = 21;
+static const uint8_t G2 = 2;
+static const uint8_t G12 = 12;
+static const uint8_t G15 = 15;
+static const uint8_t G35 = 35;
+static const uint8_t G36 = 36;
+static const uint8_t G25 = 25;
+static const uint8_t G26 = 26;
+static const uint8_t G1 = 1;
+static const uint8_t G17 = 17;
+static const uint8_t G22 = 22;
+static const uint8_t G5 = 5;
+static const uint8_t G13 = 13;
+static const uint8_t G0 = 0;
+static const uint8_t G34 = 34;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/sensebox_mcu_esp32s2/bootloader-tinyuf2.bin b/variants/sensebox_mcu_esp32s2/bootloader-tinyuf2.bin
new file mode 100644
index 00000000000..3e0f1f360a3
Binary files /dev/null and b/variants/sensebox_mcu_esp32s2/bootloader-tinyuf2.bin differ
diff --git a/variants/sensebox_mcu_esp32s2/partitions-4MB-tinyuf2.csv b/variants/sensebox_mcu_esp32s2/partitions-4MB-tinyuf2.csv
new file mode 100644
index 00000000000..164ba0d5965
--- /dev/null
+++ b/variants/sensebox_mcu_esp32s2/partitions-4MB-tinyuf2.csv
@@ -0,0 +1,11 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,          0x8000, 4K
+
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  1408K,
+ota_1,    0,    ota_1,  0x170000,  1408K,
+uf2,      app,  factory,0x2d0000,  256K,
+ffat,     data, fat,    0x310000,  960K,
diff --git a/variants/sensebox_mcu_esp32s2/pins_arduino.h b/variants/sensebox_mcu_esp32s2/pins_arduino.h
new file mode 100644
index 00000000000..62acb6a13f4
--- /dev/null
+++ b/variants/sensebox_mcu_esp32s2/pins_arduino.h
@@ -0,0 +1,133 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303A
+#define USB_PID          0x81B8
+#define USB_MANUFACTURER "senseBox"
+#define USB_PRODUCT      "MCU-S2 ESP32S2"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// Default USB FirmwareMSC Settings
+#define USB_FW_MSC_VENDOR_ID        "senseBox"        // max 8 chars
+#define USB_FW_MSC_PRODUCT_ID       "MCU-S2 ESP32S2"  // max 16 chars
+#define USB_FW_MSC_PRODUCT_REVISION "1.00"            // max 4 chars
+#define USB_FW_MSC_VOLUME_NAME      "senseBox"        // max 11 chars
+#define USB_FW_MSC_SERIAL_NUMBER    0x00000000
+
+#define PIN_RGB_LED 1  // RGB LED
+#define RGBLED_PIN  1  // RGB LED
+#define RGBLED_NUM  1  // number of RGB LEDs
+
+// Default I2C QWIIC-Ports
+static const uint8_t SDA = 39;
+static const uint8_t SCL = 40;
+#define PIN_QWIIC_SDA 39
+#define PIN_QWIIC_SCL 40
+
+// Secondary I2C MPU6050
+#define WIRE1_PIN_DEFINED 1  // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin)
+static const uint8_t SCL1 = 42;
+static const uint8_t SDA1 = 45;
+#define PIN_I2C_SCL 42
+#define PIN_I2C_SDA 45
+#define PIN_I2C_INT 46
+
+// SPI
+static const uint8_t SS = 42;
+static const uint8_t MOSI = 35;
+static const uint8_t SCK = 36;
+static const uint8_t MISO = 37;
+
+// XBEE Pins
+#define PIN_XBEE_ENABLE 41
+#define PIN_XBEE_INT    33
+#define PIN_XBEE_CS     34
+#define PIN_XBEE_MOSI   35
+#define PIN_XBEE_SCLK   36
+#define PIN_XBEE_MISO   37
+#define PIN_XBEE_RESET  38
+#define PIN_XBEE_TXD    17
+#define PIN_XBEE_RXD    18
+
+// Alias XB1
+#define PIN_XB1_ENABLE 41
+#define PIN_XB1_INT    33
+#define PIN_XB1_CS     34
+#define PIN_XB1_MOSI   35
+#define PIN_XB1_SCLK   36
+#define PIN_XB1_MISO   37
+#define PIN_XB1_RESET  38
+#define PIN_XB1_TXD    17
+#define PIN_XB1_RXD    18
+
+// IO Pins
+#define PIN_LED   1
+#define PIN_IO2   2
+#define PIN_IO3   3
+#define PIN_IO4   4
+#define PIN_IO5   5
+#define PIN_IO6   6
+#define PIN_IO7   7
+#define IO_ENABLE 8
+
+static const uint8_t A2 = PIN_IO2;
+static const uint8_t A3 = PIN_IO3;
+static const uint8_t A4 = PIN_IO4;
+static const uint8_t A5 = PIN_IO5;
+static const uint8_t A6 = PIN_IO6;
+static const uint8_t A7 = PIN_IO7;
+
+static const uint8_t D2 = PIN_IO2;
+static const uint8_t D3 = PIN_IO3;
+static const uint8_t D4 = PIN_IO4;
+static const uint8_t D5 = PIN_IO5;
+static const uint8_t D6 = PIN_IO6;
+static const uint8_t D7 = PIN_IO7;
+
+// UART Port
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+#define PIN_UART_TXD    43
+#define PIN_UART_RXD    44
+#define PIN_UART_ENABLE 26
+
+// UART XBee
+static const uint8_t TX1 = 17;
+static const uint8_t RX1 = 18;
+
+// PD-Sensor
+#define PD_SENSE      14
+#define PD_ENABLE     21
+#define PIN_PD_ENABLE 21
+
+// SD-Card
+#define VSPI_MISO 13
+#define VSPI_MOSI 11
+#define VSPI_SCLK 12
+#define VSPI_SS   10
+#define SD_ENABLE 9
+
+#define PIN_SD_ENABLE 9
+#define PIN_SD_CS     10
+#define PIN_SD_MOSI   11
+#define PIN_SD_SCLK   12
+#define PIN_SD_MISO   13
+
+// USB
+#define PIN_USB_DM 19
+#define PIN_USB_DP 20
+
+// Touch Pins
+static const uint8_t T2 = PIN_IO2;
+static const uint8_t T3 = PIN_IO3;
+static const uint8_t T4 = PIN_IO4;
+static const uint8_t T5 = PIN_IO5;
+static const uint8_t T6 = PIN_IO6;
+static const uint8_t T7 = PIN_IO7;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/sensebox_mcu_esp32s2/tinyuf2.bin b/variants/sensebox_mcu_esp32s2/tinyuf2.bin
new file mode 100644
index 00000000000..bdc4d839ed7
Binary files /dev/null and b/variants/sensebox_mcu_esp32s2/tinyuf2.bin differ
diff --git a/variants/sensebox_mcu_esp32s2/variant.cpp b/variants/sensebox_mcu_esp32s2/variant.cpp
new file mode 100644
index 00000000000..0c58ef2cbe2
--- /dev/null
+++ b/variants/sensebox_mcu_esp32s2/variant.cpp
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "esp32-hal-gpio.h"
+#include "pins_arduino.h"
+
+extern "C" {
+
+// Initialize variant/board, called before setup()
+void initVariant(void) {
+  //enable IO Pins by default
+  pinMode(IO_ENABLE, OUTPUT);
+  digitalWrite(IO_ENABLE, LOW);
+
+  //reset RGB
+  pinMode(PIN_RGB_LED, OUTPUT);
+  digitalWrite(PIN_RGB_LED, LOW);
+
+  //enable XBEE by default
+  pinMode(PIN_XB1_ENABLE, OUTPUT);
+  digitalWrite(PIN_XB1_ENABLE, LOW);
+
+  //enable UART by default
+  pinMode(PIN_UART_ENABLE, OUTPUT);
+  digitalWrite(PIN_UART_ENABLE, LOW);
+
+  //enable PD-Sensor by default
+  pinMode(PD_ENABLE, OUTPUT);
+  digitalWrite(PD_ENABLE, HIGH);
+}
+}
diff --git a/variants/sonoff_dualr3/pins_arduino.h b/variants/sonoff_dualr3/pins_arduino.h
new file mode 100644
index 00000000000..e7d6c6c1555
--- /dev/null
+++ b/variants/sonoff_dualr3/pins_arduino.h
@@ -0,0 +1,19 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t BUTTON = 0;
+static const uint8_t LED_LINK = 13;
+static const uint8_t RELAY_2 = 14;
+static const uint8_t RELAY_1 = 27;
+static const uint8_t SWITCH_2 = 33;
+static const uint8_t SWITCH_1 = 32;
+
+static const uint8_t CSE7761_TX = 25;
+static const uint8_t CSE7761_RX = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/sparkfun_esp32_iot_redboard/pins_arduino.h b/variants/sparkfun_esp32_iot_redboard/pins_arduino.h
new file mode 100644
index 00000000000..f6226fdf286
--- /dev/null
+++ b/variants/sparkfun_esp32_iot_redboard/pins_arduino.h
@@ -0,0 +1,58 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+static const uint8_t LED_BUILTIN = 18;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+#define RGB_LED_PIN 2  //WS2812 LED
+static const uint8_t RGB_BUILTIN = (SOC_GPIO_PIN_COUNT + RGB_LED_PIN);
+#define RGB_BUILTIN    RGB_BUILTIN  // necessary to make digitalWrite/digitalMode find it
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/sparkfun_esp32c6_qwiic_pocket/pins_arduino.h b/variants/sparkfun_esp32c6_qwiic_pocket/pins_arduino.h
new file mode 100644
index 00000000000..ca021a1426e
--- /dev/null
+++ b/variants/sparkfun_esp32c6_qwiic_pocket/pins_arduino.h
@@ -0,0 +1,31 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = 23;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 6;
+static const uint8_t SCL = 7;
+
+static const uint8_t SS = 2;
+static const uint8_t MOSI = 3;
+static const uint8_t MISO = 4;
+static const uint8_t SCK = 5;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/sparkfun_esp32c6_thing_plus/pins_arduino.h b/variants/sparkfun_esp32c6_thing_plus/pins_arduino.h
new file mode 100644
index 00000000000..61c939a32a9
--- /dev/null
+++ b/variants/sparkfun_esp32c6_thing_plus/pins_arduino.h
@@ -0,0 +1,35 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_RGB_LED 23
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 6;
+static const uint8_t SCL = 7;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 20;
+static const uint8_t MISO = 21;
+static const uint8_t SCK = 19;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/sparkfun_esp32s3_thing_plus/pins_arduino.h b/variants/sparkfun_esp32s3_thing_plus/pins_arduino.h
new file mode 100644
index 00000000000..7c5e0c1f570
--- /dev/null
+++ b/variants/sparkfun_esp32s3_thing_plus/pins_arduino.h
@@ -0,0 +1,61 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+//#define USB_VID          0x303A
+//#define USB_PID          0x1001
+//#define USB_MANUFACTURER "Sparkfun"
+//#define USB_PRODUCT      "ESP32-S3 Thing Plus"
+#define USB_SERIAL ""
+
+#define LED_PIN     46  //Pin 46 on Thing Plus C S3 is connected to WS2812 LED
+#define COLOR_ORDER GRB
+#define CHIPSET     WS2812
+#define NUM_LEDS    1
+#define BRIGHTNESS  25
+#define LED_BUILTIN LED_PIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+static const uint8_t LED = LED_PIN;
+static const uint8_t STAT_LED = 0;
+static const uint8_t BTN = 0;
+static const uint8_t Q_EN = 45;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SS = 10;
+static const uint8_t MISO = 13;  //POCI
+static const uint8_t MOSI = 11;  //PICO
+static const uint8_t SCK = 12;
+
+static const uint8_t SCL = 9;
+static const uint8_t SDA = 8;
+
+static const uint8_t A0 = 10;
+static const uint8_t A1 = 14;
+static const uint8_t A2 = 15;
+static const uint8_t A3 = 16;
+static const uint8_t A4 = 17;
+static const uint8_t A5 = 18;
+
+static const uint8_t GPIO0 = 21;
+static const uint8_t GPIO1 = 7;
+static const uint8_t GPIO2 = 6;
+static const uint8_t GPIO3 = 5;
+static const uint8_t GPIO4 = 4;
+static const uint8_t GPIO5 = 2;
+static const uint8_t GPIO6 = 1;
+
+static const uint8_t FREEBIE = 42;
+
+static const uint8_t SDIO_DET = 48;
+static const uint8_t SDIO0 = 39;
+static const uint8_t SDIO1 = 40;
+static const uint8_t SDIO2 = 47;
+static const uint8_t SDIO3 = 33;
+static const uint8_t SDIO_CLK = 38;
+static const uint8_t SDIO_CMD = 34;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/sparkfun_lora_gateway_1-channel/pins_arduino.h b/variants/sparkfun_lora_gateway_1-channel/pins_arduino.h
old mode 100755
new mode 100644
index 0d45940f576..589b72e5baa
--- a/variants/sparkfun_lora_gateway_1-channel/pins_arduino.h
+++ b/variants/sparkfun_lora_gateway_1-channel/pins_arduino.h
@@ -1,58 +1,52 @@
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-static const int LED_BUILTIN = 17;
-
-static const uint8_t TX = 1;
-static const uint8_t RX = 3;
-
-static const uint8_t SDA = 21;
-static const uint8_t SCL = 22;
-
-static const uint8_t SS    = 16;
-static const uint8_t MOSI  = 13;
-static const uint8_t MISO  = 12;
-static const uint8_t SCK   = 14;
-
-static const uint8_t A0 = 36;
-static const uint8_t A3 = 39;
-static const uint8_t A4 = 32;
-static const uint8_t A5 = 33;
-static const uint8_t A6 = 34;
-static const uint8_t A7 = 35;
-static const uint8_t A10 = 4;
-static const uint8_t A11 = 0;
-static const uint8_t A12 = 2;
-static const uint8_t A13 = 15;
-static const uint8_t A14 = 13;
-static const uint8_t A15 = 12;
-static const uint8_t A16 = 14;
-static const uint8_t A17 = 27;
-static const uint8_t A18 = 25;
-static const uint8_t A19 = 26;
-
-static const uint8_t T0 = 4;
-static const uint8_t T1 = 0;
-static const uint8_t T2 = 2;
-static const uint8_t T3 = 15;
-static const uint8_t T4 = 13;
-static const uint8_t T5 = 12;
-static const uint8_t T6 = 14;
-static const uint8_t T7 = 27;
-static const uint8_t T8 = 33;
-static const uint8_t T9 = 32;
-
-static const uint8_t DAC1 = 25;
-static const uint8_t DAC2 = 26;
-
-#endif /* Pins_Arduino_h */
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const int LED_BUILTIN = 17;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 16;
+static const uint8_t MOSI = 13;
+static const uint8_t MISO = 12;
+static const uint8_t SCK = 14;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/sparkfun_pro_micro_esp32c3/pins_arduino.h b/variants/sparkfun_pro_micro_esp32c3/pins_arduino.h
new file mode 100644
index 00000000000..4ad646fc064
--- /dev/null
+++ b/variants/sparkfun_pro_micro_esp32c3/pins_arduino.h
@@ -0,0 +1,48 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x1B4F
+#define USB_PID          0x0035
+#define USB_MANUFACTURER "SparkFun"
+#define USB_PRODUCT      "SparkFun_Pro_Micro-ESP32C3"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+static const uint8_t LED_BUILTIN = 10;
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+
+static const uint8_t D0 = 0;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 2;
+static const uint8_t D3 = 3;
+static const uint8_t D4 = 4;
+static const uint8_t D5 = 5;
+static const uint8_t D6 = 6;
+static const uint8_t D7 = 7;
+static const uint8_t D8 = 8;
+static const uint8_t D9 = 9;
+static const uint8_t D10 = 10;
+
+static const uint8_t SDA = 5;
+static const uint8_t SCL = 6;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 3;
+static const uint8_t MISO = 1;
+static const uint8_t SCK = 0;
+
+static const uint8_t PIN_I2S_SCK = 6;      // Frame clock, no bit clock
+static const uint8_t PIN_I2S_SD_DOUT = 7;  // data out
+static const uint8_t PIN_I2S_SD_IN = 5;    // data in
+static const uint8_t PIN_I2S_FS = 10;      // frame select
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/tamc_termod_s3/pins_arduino.h b/variants/tamc_termod_s3/pins_arduino.h
new file mode 100644
index 00000000000..3d846c9b111
--- /dev/null
+++ b/variants/tamc_termod_s3/pins_arduino.h
@@ -0,0 +1,101 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+// This board has no NeoLED or any User LED
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t BAT_LV = 1;
+static const uint8_t CHG = 2;
+static const uint8_t TFT_CS = 10;
+static const uint8_t TFT_DC = 18;
+static const uint8_t TFT_RST = 14;
+static const uint8_t TFT_BCKL = 48;  // TFT Backlight is enabled by soldering JP2 together
+static const uint8_t SD_CS = 21;
+static const uint8_t SD_CD = 47;  // uSD Card Detect is enabled by soldering JP1 together.
+
+#define DISPLAY_PORTRAIT       2
+#define DISPLAY_LANDSCAPE      3
+#define DISPLAY_PORTRAIT_FLIP  0
+#define DISPLAY_LANDSCAPE_FLIP 1
+
+#define DISPLAY_WIDTH  240
+#define DISPLAY_HEIGHT 320
+
+/**
+ * Get battery voltage in volts
+ * @return          Battery voltage in volts
+ */
+float getBatteryVoltage();
+/**
+ * Get battery level in percent
+ * @return          Battery level in percent(0-100)
+ */
+float getBatteryCapacity();
+/**
+ * Get battery charge state
+ * @return          Battery charge state(true=charging, false=not charging)
+ */
+bool getChargingState();
+/**
+ * Set on charge start callback
+ * @param func  On charge start Callback function
+ */
+void setOnChargeStart(void (*func)());
+/**
+ * Set on charge end callback
+ * @param func  On charge end Callback function
+ */
+void setOnChargeEnd(void (*func)());
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/tamc_termod_s3/variant.cpp b/variants/tamc_termod_s3/variant.cpp
new file mode 100644
index 00000000000..8079bdbba8d
--- /dev/null
+++ b/variants/tamc_termod_s3/variant.cpp
@@ -0,0 +1,42 @@
+#include "Arduino.h"
+
+float getBatteryVoltage() {
+  int analogVolt = analogReadMilliVolts(1);
+  float voltage = analogVolt / 1000.0;
+  voltage = voltage * (100.0 + 200.0) / 200.0;
+  return voltage;
+}
+
+float getBatteryCapacity() {
+  float voltage = getBatteryVoltage();
+  float capacity = (voltage - 3.3) / (4.2 - 3.3) * 100.0;
+  capacity = constrain(capacity, 0, 100);
+  return capacity;
+}
+
+bool getChargingState() {
+  return !digitalRead(CHG);
+}
+
+void (*__onChargeStart__)();
+void (*__onChargeEnd__)();
+void setOnChargeStart(void (*func)()) {
+  __onChargeStart__ = func;
+}
+void setOnChargeEnd(void (*func)()) {
+  __onChargeEnd__ = func;
+}
+
+void ARDUINO_ISR_ATTR chargeIsr() {
+  if (getChargingState()) {
+    __onChargeStart__();
+  } else {
+    __onChargeEnd__();
+  }
+}
+
+extern "C" void initVariant(void) {
+  pinMode(CHG, INPUT_PULLUP);
+  attachInterrupt(CHG, chargeIsr, CHANGE);
+  analogReadResolution(12);
+}
diff --git a/variants/tbeam/pins_arduino.h b/variants/tbeam/pins_arduino.h
index ba4f9adea8b..4be8494c350 100644
--- a/variants/tbeam/pins_arduino.h
+++ b/variants/tbeam/pins_arduino.h
@@ -3,41 +3,33 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        20
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 // SPI LoRa Radio
-#define LORA_SCK 5      // GPIO5  - SX1276 SCK
-#define LORA_MISO 19    // GPIO19 - SX1276 MISO
-#define LORA_MOSI 27    // GPIO27 - SX1276 MOSI
-#define LORA_CS 18      // GPIO18 - SX1276 CS
-#define LORA_RST 23     // GPIO23 - SX1276 RST
-#define LORA_IRQ 26     // GPIO26 - SX1276 IO0
-#define LORA_IO0 LORA_IRQ  // alias
-#define LORA_IO1 33     // GPIO33 - SX1276 IO1 -> wired on pcb AND connected to header pin LORA1
-#define LORA_IO2 32     // GPIO32 - SX1276 IO2 -> wired on pcb AND connected to header pin LORA2
+#define LORA_SCK  5         // GPIO5  - SX1276 SCK
+#define LORA_MISO 19        // GPIO19 - SX1276 MISO
+#define LORA_MOSI 27        // GPIO27 - SX1276 MOSI
+#define LORA_CS   18        // GPIO18 - SX1276 CS
+#define LORA_RST  23        // GPIO23 - SX1276 RST
+#define LORA_IRQ  26        // GPIO26 - SX1276 IO0
+#define LORA_IO0  LORA_IRQ  // alias
+#define LORA_IO1  33        // GPIO33 - SX1276 IO1 -> wired on pcb AND connected to header pin LORA1
+#define LORA_IO2  32        // GPIO32 - SX1276 IO2 -> wired on pcb AND connected to header pin LORA2
 
 static const uint8_t KEY_BUILTIN = 39;
 
 static const uint8_t LED_BUILTIN = 14;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
- 
-static const uint8_t SS    = 18;
-static const uint8_t MOSI  = 27;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 5;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 27;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/thingpulse_epulse_feather/pins_arduino.h b/variants/thingpulse_epulse_feather/pins_arduino.h
new file mode 100644
index 00000000000..62855db018f
--- /dev/null
+++ b/variants/thingpulse_epulse_feather/pins_arduino.h
@@ -0,0 +1,53 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = -1;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SDA = 23;
+static const uint8_t SCL = 22;
+
+static const uint8_t MOSI = 18;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
+static const uint8_t SS = -1;
+
+// mapping to match other feathers and also in order
+static const uint8_t A0 = 26;
+static const uint8_t A1 = 25;
+static const uint8_t A2 = 34;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 36;
+static const uint8_t A5 = 4;
+static const uint8_t A6 = 14;
+static const uint8_t A7 = 32;
+static const uint8_t A8 = 15;
+static const uint8_t A9 = 33;
+static const uint8_t A10 = 27;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+
+// vbat measure
+static const uint8_t BATT_MONITOR = 35;  // Note: voltage divider 2.2M/4.7M
+static const uint8_t A13 = 35;
+//static const uint8_t Ax = 0; // not used/available
+//static const uint8_t Ax = 2; // not used/available? GPIO02 is available!
+
+// touch inputs
+static const uint8_t T0 = 4;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/thingpulse_epulse_feather_c6/pins_arduino.h b/variants/thingpulse_epulse_feather_c6/pins_arduino.h
new file mode 100644
index 00000000000..55afea91565
--- /dev/null
+++ b/variants/thingpulse_epulse_feather_c6/pins_arduino.h
@@ -0,0 +1,35 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define PIN_RGB_LED 8
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 23;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 19;
+static const uint8_t MISO = 20;
+static const uint8_t SCK = 21;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 6;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/tinypico/pins_arduino.h b/variants/tinypico/pins_arduino.h
deleted file mode 100644
index 617cd9bf92c..00000000000
--- a/variants/tinypico/pins_arduino.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-static const uint8_t TX = 1;
-static const uint8_t RX = 3;
-
-static const uint8_t SDA = 21;
-static const uint8_t SCL = 22;
-
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
-
-static const uint8_t A0 = 36;
-static const uint8_t A3 = 39;
-static const uint8_t A4 = 32;
-static const uint8_t A5 = 33;
-static const uint8_t A6 = 34;
-static const uint8_t A7 = 35;
-static const uint8_t A10 = 4;
-static const uint8_t A11 = 0;
-static const uint8_t A12 = 2;
-static const uint8_t A13 = 15;
-static const uint8_t A14 = 13;
-static const uint8_t A15 = 12;
-static const uint8_t A16 = 14;
-static const uint8_t A17 = 27;
-static const uint8_t A18 = 25;
-static const uint8_t A19 = 26;
-
-static const uint8_t T0 = 4;
-static const uint8_t T1 = 0;
-static const uint8_t T2 = 2;
-static const uint8_t T3 = 15;
-static const uint8_t T4 = 13;
-static const uint8_t T5 = 12;
-static const uint8_t T6 = 14;
-static const uint8_t T7 = 27;
-static const uint8_t T8 = 33;
-static const uint8_t T9 = 32;
-
-static const uint8_t DAC1 = 25;
-static const uint8_t DAC2 = 26;
-
-static const uint8_t APA_POWER = 13;
-static const uint8_t APA_DATA = 2;
-static const uint8_t APA_CLK = 12;
-
-#endif /* Pins_Arduino_h */
diff --git a/variants/ttgo-lora32-v1/pins_arduino.h b/variants/ttgo-lora32-v1/pins_arduino.h
index c365f240b40..85bfe5fda5d 100644
--- a/variants/ttgo-lora32-v1/pins_arduino.h
+++ b/variants/ttgo-lora32-v1/pins_arduino.h
@@ -1,78 +1,70 @@
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-// I2C OLED Display works with SSD1306 driver
-#define OLED_SDA 4
-#define OLED_SCL 15
-#define OLED_RST 16
-
-// SPI LoRa Radio
-#define LORA_SCK 5        // GPIO5 - SX1276 SCK
-#define LORA_MISO 19     // GPIO19 - SX1276 MISO
-#define LORA_MOSI 27    // GPIO27 - SX1276 MOSI
-#define LORA_CS 18     // GPIO18 - SX1276 CS
-#define LORA_RST 14   // GPIO14 - SX1276 RST
-#define LORA_IRQ 26  // GPIO26 - SX1276 IRQ (interrupt request)
-
-static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-
-static const uint8_t KEY_BUILTIN = 0;
-
-static const uint8_t TX = 1;
-static const uint8_t RX = 3;
-
-static const uint8_t SDA = 21;
-static const uint8_t SCL = 22;
-
-static const uint8_t SS    = 18;
-static const uint8_t MOSI  = 27;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 5;
-
-static const uint8_t A0 = 36;
-static const uint8_t A1 = 37;
-static const uint8_t A2 = 38;
-static const uint8_t A3 = 39;
-static const uint8_t A4 = 32;
-static const uint8_t A5 = 33;
-static const uint8_t A6 = 34;
-static const uint8_t A7 = 35;
-
-static const uint8_t A10 = 4;
-static const uint8_t A11 = 0;
-static const uint8_t A12 = 2;
-static const uint8_t A13 = 15;
-static const uint8_t A14 = 13;
-static const uint8_t A15 = 12;
-static const uint8_t A16 = 14;
-static const uint8_t A17 = 27;
-static const uint8_t A18 = 25;
-static const uint8_t A19 = 26;
-
-static const uint8_t T0 = 4;
-static const uint8_t T1 = 0;
-static const uint8_t T2 = 2;
-static const uint8_t T3 = 15;
-static const uint8_t T4 = 13;
-static const uint8_t T5 = 12;
-static const uint8_t T6 = 14;
-static const uint8_t T7 = 27;
-static const uint8_t T8 = 33;
-static const uint8_t T9 = 32;
-
-static const uint8_t DAC1 = 25;
-static const uint8_t DAC2 = 26;
-
-#endif /* Pins_Arduino_h */
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+// I2C OLED Display works with SSD1306 driver
+#define OLED_SDA 4
+#define OLED_SCL 15
+#define OLED_RST 16
+
+// SPI LoRa Radio
+#define LORA_SCK  5   // GPIO5 - SX1276 SCK
+#define LORA_MISO 19  // GPIO19 - SX1276 MISO
+#define LORA_MOSI 27  // GPIO27 - SX1276 MOSI
+#define LORA_CS   18  // GPIO18 - SX1276 CS
+#define LORA_RST  14  // GPIO14 - SX1276 RST
+#define LORA_IRQ  26  // GPIO26 - SX1276 IRQ (interrupt request)
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 27;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
+
+static const uint8_t A0 = 36;
+static const uint8_t A1 = 37;
+static const uint8_t A2 = 38;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/ttgo-lora32-v2/pins_arduino.h b/variants/ttgo-lora32-v2/pins_arduino.h
index 416034e7efa..7e29ee950d3 100644
--- a/variants/ttgo-lora32-v2/pins_arduino.h
+++ b/variants/ttgo-lora32-v2/pins_arduino.h
@@ -3,26 +3,18 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 // I2C OLED Display works with SSD1306 driver
-#define OLED_SDA    21
-#define OLED_SCL    22
-#define OLED_RST    16
+#define OLED_SDA 21
+#define OLED_SCL 22
+#define OLED_RST 16
 
 // SPI LoRa Radio
-#define LORA_SCK    5   // GPIO5 - SX1276 SCK
-#define LORA_MISO   19  // GPIO19 - SX1276 MISO
-#define LORA_MOSI   27  // GPIO27 - SX1276 MOSI
-#define LORA_CS     18  // GPIO18 - SX1276 CS
-#define LORA_RST    12  // GPIO14 - SX1276 RST
-#define LORA_IRQ    26  // GPIO26 - SX1276 IRQ (interrupt request)
+#define LORA_SCK  5   // GPIO5 - SX1276 SCK
+#define LORA_MISO 19  // GPIO19 - SX1276 MISO
+#define LORA_MOSI 27  // GPIO27 - SX1276 MOSI
+#define LORA_CS   18  // GPIO18 - SX1276 CS
+#define LORA_RST  12  // GPIO14 - SX1276 RST
+#define LORA_IRQ  26  // GPIO26 - SX1276 IRQ (interrupt request)
 
 // SD card
 #define SD_SCK  14
@@ -30,52 +22,52 @@
 #define SD_MOSI 15
 #define SD_CS   13
 
-static const uint8_t LED_BUILTIN =  22;
-#define BUILTIN_LED  LED_BUILTIN    // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+static const uint8_t LED_BUILTIN = 22;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
-static const uint8_t KEY_BUILTIN =  0;
+static const uint8_t KEY_BUILTIN = 0;
 
-static const uint8_t TX =   1;
-static const uint8_t RX =   3;
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
 
-static const uint8_t SDA =  21;
-static const uint8_t SCL =  22;
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
 
-static const uint8_t SS =   18;
+static const uint8_t SS = 18;
 static const uint8_t MOSI = 27;
 static const uint8_t MISO = 19;
-static const uint8_t SCK =  5;
+static const uint8_t SCK = 5;
 
-static const uint8_t A0 =   36;
-static const uint8_t A1 =   37;
-static const uint8_t A2 =   38;
-static const uint8_t A3 =   39;
-static const uint8_t A4 =   32;
-static const uint8_t A5 =   33;
-static const uint8_t A6 =   34;
-static const uint8_t A7 =   35;
-static const uint8_t A10 =  4;
-static const uint8_t A11 =  0;
-static const uint8_t A12 =  2;
-static const uint8_t A13 =  15;
-static const uint8_t A14 =  13;
-static const uint8_t A15 =  12;
-static const uint8_t A16 =  14;
-static const uint8_t A17 =  27;
-static const uint8_t A18 =  25;
-static const uint8_t A19 =  26;
+static const uint8_t A0 = 36;
+static const uint8_t A1 = 37;
+static const uint8_t A2 = 38;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
 
-static const uint8_t T0 =   4;
-static const uint8_t T1 =   0;
-static const uint8_t T2 =   2;
-static const uint8_t T3 =   15;
-static const uint8_t T4 =   13;
-static const uint8_t T5 =   12;
-static const uint8_t T6 =   14;
-static const uint8_t T7 =   27;
-static const uint8_t T8 =   33;
-static const uint8_t T9 =   32;
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
 
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
diff --git a/variants/ttgo-lora32-v21new/pins_arduino.h b/variants/ttgo-lora32-v21new/pins_arduino.h
index 931ff29839a..06bb27ecccf 100644
--- a/variants/ttgo-lora32-v21new/pins_arduino.h
+++ b/variants/ttgo-lora32-v21new/pins_arduino.h
@@ -9,28 +9,20 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 // I2C OLED Display works with SSD1306 driver
-#define OLED_SDA    21
-#define OLED_SCL    22
-#define OLED_RST    16
+#define OLED_SDA 21
+#define OLED_SCL 22
+#define OLED_RST 16
 
 // SPI LoRa Radio
-#define LORA_SCK    5   // GPIO5 - SX1276 SCK
-#define LORA_MISO   19  // GPIO19 - SX1276 MISO
-#define LORA_MOSI   27  // GPIO27 - SX1276 MOSI
-#define LORA_CS     18  // GPIO18 - SX1276 CS
-#define LORA_RST    12  // GPIO14 - SX1276 RST
-#define LORA_IRQ    26  // GPIO26 - SX1276 IRQ (interrupt request)
-#define LORA_D1     33  // GPIO33 - SX1276 IO1 (for LMIC Arduino library)
-#define LORA_D2     32 // GPIO32 - SX1276 IO2
+#define LORA_SCK  5   // GPIO5 - SX1276 SCK
+#define LORA_MISO 19  // GPIO19 - SX1276 MISO
+#define LORA_MOSI 27  // GPIO27 - SX1276 MOSI
+#define LORA_CS   18  // GPIO18 - SX1276 CS
+#define LORA_RST  23  // GPIO23 - SX1276 RST
+#define LORA_IRQ  26  // GPIO26 - SX1276 IRQ (interrupt request)
+#define LORA_D1   33  // GPIO33 - SX1276 IO1 (for LMIC Arduino library)
+#define LORA_D2   32  // GPIO32 - SX1276 IO2
 
 // SD card
 #define SD_SCK  14
@@ -38,52 +30,52 @@
 #define SD_MOSI 15
 #define SD_CS   13
 
-static const uint8_t LED_BUILTIN = 25  ;
-#define BUILTIN_LED  LED_BUILTIN    // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+static const uint8_t LED_BUILTIN = 25;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
-static const uint8_t KEY_BUILTIN =  0;
+static const uint8_t KEY_BUILTIN = 0;
 
-static const uint8_t TX =   1;
-static const uint8_t RX =   3;
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
 
-static const uint8_t SDA =  21;
-static const uint8_t SCL =  22;
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
 
-static const uint8_t SS =   18;
+static const uint8_t SS = 18;
 static const uint8_t MOSI = 27;
 static const uint8_t MISO = 19;
-static const uint8_t SCK =  5;
-
-static const uint8_t A0 =   36;
-static const uint8_t A1 =   37;
-static const uint8_t A2 =   38;
-static const uint8_t A3 =   39;
-static const uint8_t A4 =   32;
-static const uint8_t A5 =   33;
-static const uint8_t A6 =   34;
-static const uint8_t A7 =   35;
-static const uint8_t A10 =  4; 
-static const uint8_t A11 =  0;
-static const uint8_t A12 =  2;
-static const uint8_t A13 =  15;
-static const uint8_t A14 =  13;
-static const uint8_t A15 =  12;
-static const uint8_t A16 =  14;
-static const uint8_t A17 =  27;
-static const uint8_t A18 =  25;
-static const uint8_t A19 =  26;
-
-static const uint8_t T0 =   4;
-static const uint8_t T1 =   0;
-static const uint8_t T2 =   2;
-static const uint8_t T3 =   15;
-static const uint8_t T4 =   13;
-static const uint8_t T5 =   12;
-static const uint8_t T6 =   14;
-static const uint8_t T7 =   27;
-static const uint8_t T8 =   33;
-static const uint8_t T9 =   32;
+static const uint8_t SCK = 5;
+
+static const uint8_t A0 = 36;
+static const uint8_t A1 = 37;
+static const uint8_t A2 = 38;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
 
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
diff --git a/variants/ttgo-t-oi-plus/pins_arduino.h b/variants/ttgo-t-oi-plus/pins_arduino.h
new file mode 100644
index 00000000000..5738ce0277d
--- /dev/null
+++ b/variants/ttgo-t-oi-plus/pins_arduino.h
@@ -0,0 +1,27 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 3;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 19;
+static const uint8_t SCL = 18;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 4;
+static const uint8_t A3 = 5;
+
+static const uint8_t BAT_ADC_PIN = 2;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/ttgo-t1/pins_arduino.h b/variants/ttgo-t1/pins_arduino.h
index fa20c5f9698..b8da3464e81 100644
--- a/variants/ttgo-t1/pins_arduino.h
+++ b/variants/ttgo-t1/pins_arduino.h
@@ -3,20 +3,12 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
 
 static const uint8_t LED_BUILTIN = 22;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t SDA = 21;
 // Despite the many diagrams from TTGO showing SCL on pin 22, due to the on-board LED
@@ -24,10 +16,10 @@ static const uint8_t SDA = 21;
 static const uint8_t SCL = 23;
 
 // These are the settings used for the on-board SD card slot
-static const uint8_t SS    = 13;
-static const uint8_t MOSI  = 15;
-static const uint8_t MISO  = 2;
-static const uint8_t SCK   = 14;
+static const uint8_t SS = 13;
+static const uint8_t MOSI = 15;
+static const uint8_t MISO = 2;
+static const uint8_t SCK = 14;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/ttgo-t7-v13-mini32/pins_arduino.h b/variants/ttgo-t7-v13-mini32/pins_arduino.h
new file mode 100644
index 00000000000..23a98d70d5e
--- /dev/null
+++ b/variants/ttgo-t7-v13-mini32/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t LED_BUILTIN = 22;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/ttgo-t7-v14-mini32/pins_arduino.h b/variants/ttgo-t7-v14-mini32/pins_arduino.h
new file mode 100644
index 00000000000..f3ebba9f354
--- /dev/null
+++ b/variants/ttgo-t7-v14-mini32/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t LED_BUILTIN = 19;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/turta_iot_node/pins_arduino.h b/variants/turta_iot_node/pins_arduino.h
index 4e1ae60fe05..e5fbc40b04c 100644
--- a/variants/turta_iot_node/pins_arduino.h
+++ b/variants/turta_iot_node/pins_arduino.h
@@ -3,18 +3,10 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 20
-#define NUM_DIGITAL_PINS        21
-#define NUM_ANALOG_INPUTS       9
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 // LED
 static const uint8_t LED_BUILTIN = 13;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 // UART
 static const uint8_t TX = 10;
@@ -25,13 +17,13 @@ static const uint8_t SDA = 23;
 static const uint8_t SCL = 22;
 
 // SPI
-static const uint8_t SS    = 21;
-static const uint8_t MOSI  = 18;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 5;
+static const uint8_t SS = 21;
+static const uint8_t MOSI = 18;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 5;
 
 // Analog Inputs
-static const uint8_t A0 = 4; 
+static const uint8_t A0 = 4;
 static const uint8_t A1 = 25;
 static const uint8_t A2 = 26;
 static const uint8_t A3 = 27;
diff --git a/variants/twatch/pins_arduino.h b/variants/twatch/pins_arduino.h
index f4b4fc52333..1d69ae5b5b5 100644
--- a/variants/twatch/pins_arduino.h
+++ b/variants/twatch/pins_arduino.h
@@ -3,36 +3,31 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        20
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 // touch screen
-#define TP_SDA              23
-#define TP_SCL              32
-#define TP_INT              38
+#define TP_SDA 23
+#define TP_SCL 32
+#define TP_INT 38
 
 // Interrupt IO port
-#define RTC_INT             37
-#define APX20X_INT          35
-#define BMA42X_INT1         39
+#define RTC_INT     37
+#define APX20X_INT  35
+#define BMA42X_INT1 39
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
 
 //Serial1 Already assigned to GPS LORA
-#define TX1                 33
-#define RX1                 34
+#define TX1 33
+#define RX1 34
 
 // Already assigned to BMA423 PCF8563 and external extensions
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 // SPI has been configured as an SD card slot and must be removed when downloading
-static const uint8_t SS    = 13;
-static const uint8_t MOSI  = 15;
-static const uint8_t MISO  = 2;
-static const uint8_t SCK   = 14;
+static const uint8_t SS = 13;
+static const uint8_t MOSI = 15;
+static const uint8_t MISO = 2;
+static const uint8_t SCK = 14;
 // Externally programmable IO
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
diff --git a/variants/uPesy_edu_esp32/pins_arduino.h b/variants/uPesy_edu_esp32/pins_arduino.h
new file mode 100644
index 00000000000..c3349d94843
--- /dev/null
+++ b/variants/uPesy_edu_esp32/pins_arduino.h
@@ -0,0 +1,53 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 33;
+static const uint8_t A1 = 32;
+static const uint8_t A2 = 35;
+static const uint8_t A3 = 34;
+static const uint8_t A4 = 36;
+static const uint8_t A5 = 39;
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN
+
+#define PIN_WIRE_SDA SDA  // backward compatibility
+#define PIN_WIRE_SCL SCL  // backward compatibility
+
+static const uint8_t D0 = 3;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 26;
+static const uint8_t D3 = 25;
+static const uint8_t D4 = 17;
+static const uint8_t D5 = 16;
+static const uint8_t D6 = 27;
+static const uint8_t D7 = 14;
+static const uint8_t D8 = 12;
+static const uint8_t D9 = 13;
+static const uint8_t D10 = 5;
+static const uint8_t D11 = 23;
+static const uint8_t D12 = 19;
+static const uint8_t D13 = 18;
+
+#define PIN_SPI_SS   SS    // backward compatibility
+#define PIN_SPI_MOSI MOSI  // backward compatibility
+#define PIN_SPI_MISO MISO  // backward compatibility
+#define PIN_SPI_SCK  SCK   // backward compatibility
+
+#define PIN_A0 A0  // backward compatibility
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/uPesy_esp32_wroom_devkit/pins_arduino.h b/variants/uPesy_esp32_wroom_devkit/pins_arduino.h
new file mode 100644
index 00000000000..8e1d00416d1
--- /dev/null
+++ b/variants/uPesy_esp32_wroom_devkit/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/uPesy_esp32_wrover_devkit/pins_arduino.h b/variants/uPesy_esp32_wrover_devkit/pins_arduino.h
new file mode 100644
index 00000000000..8e1d00416d1
--- /dev/null
+++ b/variants/uPesy_esp32_wrover_devkit/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/uPesy_esp32c3_basic/pins_arduino.h b/variants/uPesy_esp32c3_basic/pins_arduino.h
new file mode 100644
index 00000000000..7536acec2c8
--- /dev/null
+++ b/variants/uPesy_esp32c3_basic/pins_arduino.h
@@ -0,0 +1,32 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303A
+#define USB_PID          0x8195
+#define USB_MANUFACTURER "uPesy Electronics"
+#define USB_PRODUCT      "uPesy ESP32C3 Basic"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 3;
+static const uint8_t SCL = 10;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+static const uint8_t VBAT_SENSE = 0;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/uPesy_esp32c3_mini/pins_arduino.h b/variants/uPesy_esp32c3_mini/pins_arduino.h
new file mode 100644
index 00000000000..71029338133
--- /dev/null
+++ b/variants/uPesy_esp32c3_mini/pins_arduino.h
@@ -0,0 +1,31 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303A
+#define USB_PID          0x819B
+#define USB_MANUFACTURER "uPesy Electronics"
+#define USB_PRODUCT      "uPesy ESP32C3 Mini"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 3;
+static const uint8_t SCL = 10;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+static const uint8_t VBAT_SENSE = 0;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/uPesy_esp32s3_basic/pins_arduino.h b/variants/uPesy_esp32s3_basic/pins_arduino.h
new file mode 100644
index 00000000000..85d9c2ccb00
--- /dev/null
+++ b/variants/uPesy_esp32s3_basic/pins_arduino.h
@@ -0,0 +1,79 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x8192
+#define USB_MANUFACTURER "uPesy Electronics"
+#define USB_PRODUCT      "uPesy ESP32S3 Basic"
+#define USB_SERIAL       ""
+
+static const uint8_t RGB_DATA = 38;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+static const uint8_t TX0 = 43;
+static const uint8_t RX0 = 44;
+
+static const uint8_t TX1 = 17;
+static const uint8_t RX1 = 18;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t MTMS = 42;
+static const uint8_t MTDI = 41;
+static const uint8_t MTDO = 40;
+static const uint8_t MTCK = 39;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_bling/bootloader_tinyuf2.bin b/variants/um_bling/bootloader_tinyuf2.bin
new file mode 100644
index 00000000000..847c813304e
Binary files /dev/null and b/variants/um_bling/bootloader_tinyuf2.bin differ
diff --git a/variants/um_bling/partitions_tinyuf2.csv b/variants/um_bling/partitions_tinyuf2.csv
new file mode 100644
index 00000000000..4026378b6fb
--- /dev/null
+++ b/variants/um_bling/partitions_tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/variants/um_bling/pins_arduino.h b/variants/um_bling/pins_arduino.h
new file mode 100644
index 00000000000..590eec5efea
--- /dev/null
+++ b/variants/um_bling/pins_arduino.h
@@ -0,0 +1,80 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x817F
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "BLING!"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 21;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t SD_CS = 21;
+static const uint8_t SD_DETECT = 38;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+static const uint8_t BUTTON_A = 11;
+static const uint8_t BUTTON_B = 10;
+static const uint8_t BUTTON_C = 33;
+static const uint8_t BUTTON_D = 34;
+
+static const uint8_t VBAT_SENSE = 17;
+static const uint8_t VBUS_SENSE = 16;
+
+static const uint8_t I2S_MIC_SEL = 39;
+static const uint8_t I2S_MIC_WS = 40;
+static const uint8_t I2S_MIC_DATA = 41;
+static const uint8_t I2S_MIC_BCLK = 42;
+
+static const uint8_t I2S_AMP_SD = 4;
+static const uint8_t I2S_AMP_DATA = 3;
+static const uint8_t I2S_AMP_BCLK = 2;
+static const uint8_t I2S_AMP_WS = 1;
+
+static const uint8_t RTC_INT = 7;
+
+static const uint8_t RGB_DATA = 18;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = RGB_BUILTIN;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t RGB_PWR = 6;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_bling/tinyuf2.bin b/variants/um_bling/tinyuf2.bin
new file mode 100644
index 00000000000..c5ef0c3807b
Binary files /dev/null and b/variants/um_bling/tinyuf2.bin differ
diff --git a/variants/um_feathers2/pins_arduino.h b/variants/um_feathers2/pins_arduino.h
new file mode 100644
index 00000000000..c108c491a3f
--- /dev/null
+++ b/variants/um_feathers2/pins_arduino.h
@@ -0,0 +1,69 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x239A
+#define USB_PID          0x80AB
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "FeatherS2"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+static const uint8_t LDO_2_POWER = 21;
+
+static const uint8_t APA_DATA = 40;
+static const uint8_t APA_CLK = 45;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_feathers2neo/pins_arduino.h b/variants/um_feathers2neo/pins_arduino.h
new file mode 100644
index 00000000000..92c9cd1a099
--- /dev/null
+++ b/variants/um_feathers2neo/pins_arduino.h
@@ -0,0 +1,70 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x239A
+#define USB_PID          0x80B4
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "FeatherS2 Neo"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 17;
+static const uint8_t A1 = 18;
+static const uint8_t A2 = 14;
+static const uint8_t A3 = 12;
+static const uint8_t A4 = 6;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 1;
+static const uint8_t A7 = 3;
+static const uint8_t A8 = 7;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+
+static const uint8_t T1 = 1;
+static const uint8_t T3 = 3;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+static const uint8_t NEOPIXEL_MATRIX_DATA = 21;
+static const uint8_t NEOPIXEL_MATRIX_PWR = 4;
+
+static const uint8_t NEOPIXEL_DATA = 40;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (NEOPIXEL_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = RGB_BUILTIN;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t NEOPIXEL_PWR = 39;
+
+static const uint8_t VBAT_SENSE = 2;
+static const uint8_t VBUS_SENSE = 34;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_feathers3/bootloader_tinyuf2.bin b/variants/um_feathers3/bootloader_tinyuf2.bin
new file mode 100644
index 00000000000..5a2cde3f57a
Binary files /dev/null and b/variants/um_feathers3/bootloader_tinyuf2.bin differ
diff --git a/variants/um_feathers3/partitions_tinyuf2.csv b/variants/um_feathers3/partitions_tinyuf2.csv
new file mode 100644
index 00000000000..003418ceac2
--- /dev/null
+++ b/variants/um_feathers3/partitions_tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  11968K,
diff --git a/variants/um_feathers3/pins_arduino.h b/variants/um_feathers3/pins_arduino.h
new file mode 100644
index 00000000000..1c81339c88e
--- /dev/null
+++ b/variants/um_feathers3/pins_arduino.h
@@ -0,0 +1,72 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x80D6
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "FeatherS3"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+#define WIRE1_PIN_DEFINED 1  // See Wire.cpp at bool TwoWire::initPins(int sdaPin, int sclPin)
+static const uint8_t SDA1 = 16;
+static const uint8_t SCL1 = 15;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+
+static const uint8_t T1 = 1;
+static const uint8_t T3 = 3;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T14 = 14;
+
+static const uint8_t VBAT_SENSE = 2;
+static const uint8_t VBUS_SENSE = 34;
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+static const uint8_t RGB_DATA = 40;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t RGB_PWR = 39;
+static const uint8_t LDO2 = 39;
+static const uint8_t LED = 13;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_feathers3/tinyuf2.bin b/variants/um_feathers3/tinyuf2.bin
new file mode 100644
index 00000000000..178044761cd
Binary files /dev/null and b/variants/um_feathers3/tinyuf2.bin differ
diff --git a/variants/um_feathers3neo/pins_arduino.h b/variants/um_feathers3neo/pins_arduino.h
new file mode 100644
index 00000000000..94d546d22c2
--- /dev/null
+++ b/variants/um_feathers3neo/pins_arduino.h
@@ -0,0 +1,69 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x81FB
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "FeatherS3 Neo"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 17;
+static const uint8_t A1 = 18;
+static const uint8_t A2 = 14;
+static const uint8_t A3 = 12;
+static const uint8_t A4 = 6;
+static const uint8_t A5 = 5;
+static const uint8_t A6 = 1;
+static const uint8_t A7 = 3;
+static const uint8_t A8 = 7;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 8;
+static const uint8_t A12 = 9;
+
+static const uint8_t T1 = 1;
+static const uint8_t T3 = 3;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T14 = 14;
+
+static const uint8_t VBAT_SENSE = 2;
+static const uint8_t VBUS_SENSE = 15;
+
+// User LED
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+static const uint8_t RGB_DATA = 40;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+
+static const uint8_t RGB_PWR = 39;
+static const uint8_t RGB_MATRIX_PWR = 39;
+static const uint8_t RGB_MATRIX_DATA = 16;
+static const uint8_t LED = 13;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_nanos3/bootloader_tinyuf2.bin b/variants/um_nanos3/bootloader_tinyuf2.bin
new file mode 100644
index 00000000000..e89596f423d
Binary files /dev/null and b/variants/um_nanos3/bootloader_tinyuf2.bin differ
diff --git a/variants/um_nanos3/partitions_tinyuf2.csv b/variants/um_nanos3/partitions_tinyuf2.csv
new file mode 100644
index 00000000000..4026378b6fb
--- /dev/null
+++ b/variants/um_nanos3/partitions_tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/variants/um_nanos3/pins_arduino.h b/variants/um_nanos3/pins_arduino.h
new file mode 100644
index 00000000000..66aef214c47
--- /dev/null
+++ b/variants/um_nanos3/pins_arduino.h
@@ -0,0 +1,57 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x8179
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "Nanos3"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+static const uint8_t RGB_DATA = 41;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = RGB_BUILTIN;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t RGB_PWR = 42;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_nanos3/tinyuf2.bin b/variants/um_nanos3/tinyuf2.bin
new file mode 100644
index 00000000000..b2723dcf3b9
Binary files /dev/null and b/variants/um_nanos3/tinyuf2.bin differ
diff --git a/variants/um_omgs3/bootloader_tinyuf2.bin b/variants/um_omgs3/bootloader_tinyuf2.bin
new file mode 100644
index 00000000000..84bab25be27
Binary files /dev/null and b/variants/um_omgs3/bootloader_tinyuf2.bin differ
diff --git a/variants/um_omgs3/partitions_tinyuf2.csv b/variants/um_omgs3/partitions_tinyuf2.csv
new file mode 100644
index 00000000000..4026378b6fb
--- /dev/null
+++ b/variants/um_omgs3/partitions_tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/variants/um_omgs3/pins_arduino.h b/variants/um_omgs3/pins_arduino.h
new file mode 100644
index 00000000000..81164c48efe
--- /dev/null
+++ b/variants/um_omgs3/pins_arduino.h
@@ -0,0 +1,59 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x8224
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "OMGS3"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 3;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SDO = 6;
+static const uint8_t SDI = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+static const uint8_t VBUS_SENSE = 33;
+
+static const uint8_t RGB_DATA = 35;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = RGB_BUILTIN;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t RGB_PWR = 34;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_omgs3/tinyuf2.bin b/variants/um_omgs3/tinyuf2.bin
new file mode 100644
index 00000000000..fccd2906393
Binary files /dev/null and b/variants/um_omgs3/tinyuf2.bin differ
diff --git a/variants/um_pros3/bootloader_tinyuf2.bin b/variants/um_pros3/bootloader_tinyuf2.bin
new file mode 100644
index 00000000000..e92ef2b566a
Binary files /dev/null and b/variants/um_pros3/bootloader_tinyuf2.bin differ
diff --git a/variants/um_pros3/partitions_tinyuf2.csv b/variants/um_pros3/partitions_tinyuf2.csv
new file mode 100644
index 00000000000..003418ceac2
--- /dev/null
+++ b/variants/um_pros3/partitions_tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  11968K,
diff --git a/variants/um_pros3/pins_arduino.h b/variants/um_pros3/pins_arduino.h
new file mode 100644
index 00000000000..4b9bc8de6aa
--- /dev/null
+++ b/variants/um_pros3/pins_arduino.h
@@ -0,0 +1,69 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x80D3
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "ProS3"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t VBAT_SENSE = 10;
+static const uint8_t VBUS_SENSE = 33;
+
+static const uint8_t RGB_DATA = 18;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = RGB_BUILTIN;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t RGB_PWR = 17;
+static const uint8_t LDO2 = 17;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_pros3/tinyuf2.bin b/variants/um_pros3/tinyuf2.bin
new file mode 100644
index 00000000000..1e8ee8ca70f
Binary files /dev/null and b/variants/um_pros3/tinyuf2.bin differ
diff --git a/variants/um_tinyc6/pins_arduino.h b/variants/um_tinyc6/pins_arduino.h
new file mode 100644
index 00000000000..6505e1ed50e
--- /dev/null
+++ b/variants/um_tinyc6/pins_arduino.h
@@ -0,0 +1,60 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x1001
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "TinyC6"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 16;
+static const uint8_t RX = 17;
+
+static const uint8_t SDA = 6;
+static const uint8_t SCL = 7;
+
+static const uint8_t SS = 18;
+static const uint8_t MOSI = 21;
+static const uint8_t MISO = 20;
+static const uint8_t SDO = 21;
+static const uint8_t SDI = 20;
+static const uint8_t SCK = 19;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+static const uint8_t VBAT_SENSE = 4;
+static const uint8_t VBUS_SENSE = 10;
+
+static const uint8_t RGB_DATA = 23;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = RGB_BUILTIN;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t RGB_PWR = 22;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_tinypico/pins_arduino.h b/variants/um_tinypico/pins_arduino.h
new file mode 100644
index 00000000000..ce7f6dd2767
--- /dev/null
+++ b/variants/um_tinypico/pins_arduino.h
@@ -0,0 +1,54 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SDO = 23;
+static const uint8_t SDI = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 36;
+static const uint8_t A3 = 39;
+static const uint8_t A4 = 32;
+static const uint8_t A5 = 33;
+static const uint8_t A6 = 34;
+static const uint8_t A7 = 35;
+static const uint8_t A10 = 4;
+static const uint8_t A11 = 0;
+static const uint8_t A12 = 2;
+static const uint8_t A13 = 15;
+static const uint8_t A14 = 13;
+static const uint8_t A15 = 12;
+static const uint8_t A16 = 14;
+static const uint8_t A17 = 27;
+static const uint8_t A18 = 25;
+static const uint8_t A19 = 26;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+static const uint8_t APA_POWER = 13;
+static const uint8_t APA_DATA = 2;
+static const uint8_t APA_CLK = 12;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_tinys2/pins_arduino.h b/variants/um_tinys2/pins_arduino.h
new file mode 100644
index 00000000000..2a6e03aa078
--- /dev/null
+++ b/variants/um_tinys2/pins_arduino.h
@@ -0,0 +1,79 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x8001
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "TinyS2"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 14;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+static const uint8_t DAC1 = 17;
+static const uint8_t DAC2 = 18;
+
+static const uint8_t VBAT_SENSE = 3;
+static const uint8_t VBUS_SENSE = 21;
+
+static const uint8_t RGB_DATA = 1;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = RGB_BUILTIN;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t RGB_PWR = 2;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_tinys3/bootloader_tinyuf2.bin b/variants/um_tinys3/bootloader_tinyuf2.bin
new file mode 100644
index 00000000000..e89596f423d
Binary files /dev/null and b/variants/um_tinys3/bootloader_tinyuf2.bin differ
diff --git a/variants/um_tinys3/partitions_tinyuf2.csv b/variants/um_tinys3/partitions_tinyuf2.csv
new file mode 100644
index 00000000000..4026378b6fb
--- /dev/null
+++ b/variants/um_tinys3/partitions_tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/variants/um_tinys3/pins_arduino.h b/variants/um_tinys3/pins_arduino.h
new file mode 100644
index 00000000000..24742781dce
--- /dev/null
+++ b/variants/um_tinys3/pins_arduino.h
@@ -0,0 +1,60 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+#define USB_VID          0x303A
+#define USB_PID          0x80D0
+#define USB_MANUFACTURER "Unexpected Maker"
+#define USB_PRODUCT      "TinyS3"
+#define USB_SERIAL       ""
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 34;
+static const uint8_t MOSI = 35;
+static const uint8_t MISO = 37;
+static const uint8_t SDO = 35;
+static const uint8_t SDI = 37;
+static const uint8_t SCK = 36;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+
+static const uint8_t VBAT_SENSE = 10;
+static const uint8_t VBUS_SENSE = 33;
+
+static const uint8_t RGB_DATA = 18;
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    (RGB_DATA + SOC_GPIO_PIN_COUNT)
+#define RGB_BRIGHTNESS 64
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = RGB_BUILTIN;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t RGB_PWR = 17;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/um_tinys3/tinyuf2.bin b/variants/um_tinys3/tinyuf2.bin
new file mode 100644
index 00000000000..b2723dcf3b9
Binary files /dev/null and b/variants/um_tinys3/tinyuf2.bin differ
diff --git a/variants/unphone8/pins_arduino.h b/variants/unphone8/pins_arduino.h
new file mode 100644
index 00000000000..0fcd7d1e5a7
--- /dev/null
+++ b/variants/unphone8/pins_arduino.h
@@ -0,0 +1,59 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x16D0
+#define USB_PID 0x1178
+
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+static const uint8_t TX = 37;
+static const uint8_t RX = 36;
+
+static const uint8_t SDA = 1;
+static const uint8_t SCL = 2;
+
+static const uint8_t SS = 3;
+static const uint8_t MOSI = 39;
+static const uint8_t MISO = 40;
+static const uint8_t SCK = 38;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 8;
+static const uint8_t A3 = 9;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 14;
+static const uint8_t A7 = 7;
+static const uint8_t A8 = 15;
+static const uint8_t A9 = 33;
+static const uint8_t A10 = 27;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 2;
+static const uint8_t T2 = 8;
+static const uint8_t T3 = 9;
+static const uint8_t T4 = 5;
+static const uint8_t T5 = 6;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 15;
+static const uint8_t T9 = 33;
+static const uint8_t T10 = 27;
+static const uint8_t T11 = 12;
+static const uint8_t T12 = 13;
+static const uint8_t T13 = 14;
+static const uint8_t T14 = 15;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/unphone9/pins_arduino.h b/variants/unphone9/pins_arduino.h
new file mode 100644
index 00000000000..983feb2a556
--- /dev/null
+++ b/variants/unphone9/pins_arduino.h
@@ -0,0 +1,69 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x16D0
+#define USB_PID 0x1178
+
+#define LED_BUILTIN 13
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 3;
+static const uint8_t SCL = 4;
+
+static const uint8_t SS = 13;
+static const uint8_t MOSI = 40;
+static const uint8_t MISO = 41;
+static const uint8_t SCK = 39;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 8;
+static const uint8_t A3 = 9;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 14;
+static const uint8_t A7 = 7;
+static const uint8_t A8 = 15;
+static const uint8_t A9 = 33;
+static const uint8_t A10 = 27;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 2;
+static const uint8_t T2 = 8;
+static const uint8_t T3 = 9;
+static const uint8_t T4 = 5;
+static const uint8_t T5 = 6;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 15;
+static const uint8_t T9 = 33;
+static const uint8_t T10 = 27;
+static const uint8_t T11 = 12;
+static const uint8_t T12 = 13;
+static const uint8_t T13 = 14;
+static const uint8_t T14 = 15;
+
+static const uint8_t D5 = 14;
+static const uint8_t D6 = 7;
+static const uint8_t D9 = 15;
+static const uint8_t D10 = 16;
+static const uint8_t D11 = 17;
+static const uint8_t D12 = 12;
+static const uint8_t D13 = 13;
+static const uint8_t D21 = 47;
+#define UNPHONE_D_PINS_MAPPED
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/vintlabsdevkitv1/pins_arduino.h b/variants/vintlabsdevkitv1/pins_arduino.h
index feddfd95c71..ddffe2d072e 100644
--- a/variants/vintlabsdevkitv1/pins_arduino.h
+++ b/variants/vintlabsdevkitv1/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -21,10 +13,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
@@ -57,7 +49,7 @@ static const uint8_t T9 = 32;
 static const uint8_t DAC1 = 25;
 static const uint8_t DAC2 = 26;
 
-// PWM Driver pins for PWM Driver board 
+// PWM Driver pins for PWM Driver board
 static const uint8_t PWM0 = 12;
 static const uint8_t PWM1 = 13;
 static const uint8_t PWM2 = 14;
diff --git a/variants/walter/pins_arduino.h b/variants/walter/pins_arduino.h
new file mode 100644
index 00000000000..53076e7b48e
--- /dev/null
+++ b/variants/walter/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303a
+#define USB_PID          0x1001
+#define USB_MANUFACTURER "DPTechnics"
+#define USB_PRODUCT      "Walter"
+#define USB_SERIAL       ""
+
+#define MODEM_TX    48  // Sequans modem UART0 TX
+#define MODEM_RX    14  // Sequans modem UART0 RX
+#define MODEM_CTS   47  // Sequans modem UART0 CTS
+#define MODEM_RTS   19  // Sequans modem UART0 RTS
+#define MODEM_RESET 45  // Sequans modem reset signal
+#define MODEM_WAKE  46  // Sequans modem wake signal
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/watchy/pins_arduino.h b/variants/watchy/pins_arduino.h
new file mode 100644
index 00000000000..c126b27aa06
--- /dev/null
+++ b/variants/watchy/pins_arduino.h
@@ -0,0 +1,52 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 21;
+static const uint8_t SCL = 22;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t MENU_BTN_PIN = 26;
+static const uint8_t BACK_BTN_PIN = 25;
+static const uint8_t DOWN_BTN_PIN = 4;
+static const uint8_t DISPLAY_CS = 5;
+static const uint8_t DISPLAY_RES = 9;
+static const uint8_t DISPLAY_DC = 10;
+static const uint8_t DISPLAY_BUSY = 19;
+static const uint8_t ACC_INT_1_PIN = 14;
+static const uint8_t ACC_INT_2_PIN = 12;
+static const uint8_t VIB_MOTOR_PIN = 13;
+static const uint8_t RTC_INT_PIN = 27;
+
+#if defined(ARDUINO_WATCHY_V10)
+static const uint8_t UP_BTN_PIN = 32;
+static const uint8_t BATT_ADC_PIN = 33;
+#define UP_BTN_MASK GPIO_SEL_32
+#define RTC_TYPE    1  //DS3231
+#elif defined(ARDUINO_WATCHY_V15)
+static const uint8_t UP_BTN_PIN = 32;
+static const uint8_t BATT_ADC_PIN = 35;
+#define UP_BTN_MASK GPIO_SEL_32
+#define RTC_TYPE    2  //PCF8563
+#elif defined(ARDUINO_WATCHY_V20)
+static const uint8_t UP_BTN_PIN = 35;
+static const uint8_t BATT_ADC_PIN = 34;
+#define UP_BTN_MASK GPIO_SEL_35
+#define RTC_TYPE    2  //PCF8563
+#endif
+
+#define MENU_BTN_MASK GPIO_SEL_26
+#define BACK_BTN_MASK GPIO_SEL_25
+#define DOWN_BTN_MASK GPIO_SEL_4
+#define ACC_INT_MASK  GPIO_SEL_14
+#define BTN_PIN_MASK  MENU_BTN_MASK | BACK_BTN_MASK | UP_BTN_MASK | DOWN_BTN_MASK
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_lcd_146/pins_arduino.h b/variants/waveshare_esp32_s3_lcd_146/pins_arduino.h
new file mode 100644
index 00000000000..2539f207bd0
--- /dev/null
+++ b/variants/waveshare_esp32_s3_lcd_146/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8258
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-1.46"
+#define USB_SERIAL       ""
+
+// I2C pins
+static const uint8_t SCL = 10;
+static const uint8_t SDA = 11;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_lcd_147/pins_arduino.h b/variants/waveshare_esp32_s3_lcd_147/pins_arduino.h
new file mode 100644
index 00000000000..b79a970c1ef
--- /dev/null
+++ b/variants/waveshare_esp32_s3_lcd_147/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x828A
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-LCD-1.47"
+#define USB_SERIAL       ""
+
+#define PIN_RGB_LED 38
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_lcd_169/pins_arduino.h b/variants/waveshare_esp32_s3_lcd_169/pins_arduino.h
new file mode 100644
index 00000000000..54663a6810a
--- /dev/null
+++ b/variants/waveshare_esp32_s3_lcd_169/pins_arduino.h
@@ -0,0 +1,102 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8221
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-LCD-1.69"
+#define USB_SERIAL       ""
+
+// display for ST7789V2
+#define WS_LCD_DC  4
+#define WS_LCD_CS  5
+#define WS_LCD_SCL 6
+#define WS_LCD_SDA 7
+#define WS_LCD_RST 8
+#define WS_LCD_BL  15
+
+// Onboard RTC for PCF85063
+#define WS_RTC_SCL     10
+#define WS_RTC_SDA     11
+#define WS_RTC_ADDRESS 0x51
+#define WS_RTC_INT     41
+
+// Onboard  QMI8658 IMU
+#define WS_QMI8658_SDA     11
+#define WS_QMI8658_SCL     10
+#define WS_QMI8658_ADDRESS 0x6B
+#define WS_QMI8658_INT1    38
+
+// Onboard Electric buzzer & Custom buttons
+// GPIO and PSRAM conflict, need to pay attention when using
+#define WS_BUZZ    33  // Please pull down the level when using
+#define WS_SYS_OUT 36
+#define WS_SYS_EN  35
+
+// Partial voltage measurement method
+#define WS_BAT_ADC 1
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 11;
+static const uint8_t SCL = 10;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO17 = 17;
+static const uint8_t OUTPUT_IO18 = 18;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_lcd_185/pins_arduino.h b/variants/waveshare_esp32_s3_lcd_185/pins_arduino.h
new file mode 100644
index 00000000000..f8542f014e7
--- /dev/null
+++ b/variants/waveshare_esp32_s3_lcd_185/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8290
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-LCD-1.85"
+#define USB_SERIAL       ""
+
+// I2C pins
+static const uint8_t SCL = 10;
+static const uint8_t SDA = 11;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_relay_6ch/pins_arduino.h b/variants/waveshare_esp32_s3_relay_6ch/pins_arduino.h
new file mode 100644
index 00000000000..f389f5e1358
--- /dev/null
+++ b/variants/waveshare_esp32_s3_relay_6ch/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8273
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Relay-6CH"
+#define USB_SERIAL       ""
+
+#define PIN_RGB_LED 38
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_amoled_143/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_143/pins_arduino.h
new file mode 100644
index 00000000000..ed6df1d3a2c
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_amoled_143/pins_arduino.h
@@ -0,0 +1,49 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x824A
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-AMOLED-1.43"
+#define USB_SERIAL       ""
+
+// display QSPI SPI2
+#define QSPI_CS       9
+#define QSPI_SCK      10
+#define QSPI_D0       11
+#define QSPI_D1       12
+#define QSPI_D2       13
+#define QSPI_D3       14
+#define AMOLED_RESET  21
+#define AMOLED_TE     -1
+#define AMOLED_PWR_EN -1
+// Touch I2C
+#define TP_SCL 48
+#define TP_SDA 47
+#define TP_RST -1
+#define TP_INT -1
+
+// RTC
+#define RTC_INT 15
+// Partial voltage measurement method
+#define BAT_ADC 4
+// Onboard  QMI8658 IMU
+#define QMI_INT1 8
+
+static const uint8_t SDA = 47;
+static const uint8_t SCL = 48;
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+//esp32s3-PSFlash   SPI1/SPI0
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+#endif                           /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_amoled_164/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_164/pins_arduino.h
new file mode 100644
index 00000000000..ce17a49972a
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_amoled_164/pins_arduino.h
@@ -0,0 +1,55 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8249
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-AMOLED-1.64"
+#define USB_SERIAL       ""
+
+// display QSPI SPI2
+#define QSPI_CS       9
+#define QSPI_SCK      10
+#define QSPI_D0       11
+#define QSPI_D1       12
+#define QSPI_D2       13
+#define QSPI_D3       14
+#define AMOLED_RESET  21
+#define AMOLED_TE     -1
+#define AMOLED_PWR_EN -1
+
+// Touch I2C
+#define TP_SCL 48
+#define TP_SDA 47
+#define TP_RST -1
+#define TP_INT -1
+
+//key
+#define KEY_0 0
+//ADC
+#define BAT_ADC 4
+
+//SD_CARD
+#define SD_CS   38
+#define SD_MOSI 39
+#define SD_MISO 40
+#define SD_SCLK 41
+
+static const uint8_t SDA = 47;
+static const uint8_t SCL = 48;
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+//esp32s3-PSFlash   SPI1/SPI0
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+#endif                           /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_amoled_18/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_18/pins_arduino.h
new file mode 100644
index 00000000000..de8bcaec2d9
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_amoled_18/pins_arduino.h
@@ -0,0 +1,87 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8255
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-AMOLED-1.8"
+#define USB_SERIAL       ""
+
+// display for SH8601
+#define WS_LCD_CS    12
+#define WS_QSPI_SIO0 4
+#define WS_QSPI_SI1  5
+#define WS_QSPI_SI2  6
+#define WS_QSPI_SI3  7
+#define WS_QSPI_SCL  11
+
+// Touch for FT3168
+#define WS_TP_INT 21
+
+// Onboard Electric buzzer & Custom buttons
+// GPIO and PSRAM conflict, need to pay attention when using
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 14;
+static const uint8_t SCL = 15;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO17 = 17;
+static const uint8_t OUTPUT_IO18 = 18;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_amoled_191/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_191/pins_arduino.h
new file mode 100644
index 00000000000..7e882a7ef46
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_amoled_191/pins_arduino.h
@@ -0,0 +1,57 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x824B
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-AMOLED-1.91"
+#define USB_SERIAL       ""
+
+// display QSPI SPI2
+#define QSPI_CS       6
+#define QSPI_SCK      47
+#define QSPI_D0       18
+#define QSPI_D1       7
+#define QSPI_D2       48
+#define QSPI_D3       5
+#define AMOLED_RESET  17
+#define AMOLED_TE     -1
+#define AMOLED_PWR_EN -1
+// Touch I2C
+#define TP_SCL 39
+#define TP_SDA 40
+#define TP_RST -1
+#define TP_INT -1
+
+// Partial voltage measurement method
+#define BAT_ADC 1
+// Onboard  QMI8658 IMU
+#define QMI_INT1 45
+#define QMI_INT1 46
+
+//SD
+#define SD_CS   9
+#define SD_MISO 8
+#define SD_MOSI 42
+#define SD_CLK  47
+
+//i2c
+
+static const uint8_t SDA = 40;
+static const uint8_t SCL = 39;
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+//esp32s3-PSFlash   SPI1/SPI0
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+#endif                           /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_amoled_241/pins_arduino.h b/variants/waveshare_esp32_s3_touch_amoled_241/pins_arduino.h
new file mode 100644
index 00000000000..cb6c5f40ac1
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_amoled_241/pins_arduino.h
@@ -0,0 +1,60 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8242
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-AMOLED-2.41"
+#define USB_SERIAL       ""
+
+// display QSPI SPI2
+#define QSPI_CS       9
+#define QSPI_SCK      10
+#define QSPI_D0       11
+#define QSPI_D1       12
+#define QSPI_D2       13
+#define QSPI_D3       14
+#define AMOLED_RESET  21
+#define AMOLED_TE     -1
+#define AMOLED_PWR_EN -1
+
+// Touch I2C
+#define TP_SCL 48
+#define TP_SDA 47
+#define TP_RST -1
+#define TP_INT -1
+
+// Onboard RTC for PCF85063
+#define RTC_SCL     48
+#define RTC_SDA     47
+#define RTC_ADDRESS 0x51
+#define RTC_INT     -1
+
+// Onboard  QMI8658 IMU
+#define QMI8658_SDA     47
+#define QMI8658_SCL     48
+#define QMI8658_ADDRESS 0x6b
+#define QMI8658_INT1    -1
+
+// Partial voltage measurement method
+#define BAT_ADC 17
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 47;
+static const uint8_t SCL = 48;
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+//esp32s3-PSFlash   SPI1/SPI0
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+#endif                           /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_146/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_146/pins_arduino.h
new file mode 100644
index 00000000000..1c14bfe6714
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_146/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8287
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-1.85-Box"
+#define USB_SERIAL       ""
+
+// I2C pins
+static const uint8_t SCL = 10;
+static const uint8_t SDA = 11;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_169/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_169/pins_arduino.h
new file mode 100644
index 00000000000..8d1562f4cd7
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_169/pins_arduino.h
@@ -0,0 +1,108 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x821e
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-1.69"
+#define USB_SERIAL       ""
+
+// display for ST7789V2
+#define WS_LCD_DC  4
+#define WS_LCD_CS  5
+#define WS_LCD_SCL 6
+#define WS_LCD_SDA 7
+#define WS_LCD_RST 8
+#define WS_LCD_BL  15
+
+// Touch for CST816T
+#define WS_TP_SCL 10
+#define WS_TP_SDA 11
+#define WS_TP_RST 13
+#define WS_TP_INT 14
+
+// Onboard RTC for PCF85063
+#define WS_RTC_SCL     10
+#define WS_RTC_SDA     11
+#define WS_RTC_ADDRESS 0x51
+#define WS_RTC_INT     41
+
+// Onboard  QMI8658 IMU
+#define WS_QMI8658_SDA     11
+#define WS_QMI8658_SCL     10
+#define WS_QMI8658_ADDRESS 0x6B
+#define WS_QMI8658_INT1    38
+
+// Onboard Electric buzzer & Custom buttons
+// GPIO and PSRAM conflict, need to pay attention when using
+#define WS_BUZZ    33  // Please pull down the level when using
+#define WS_SYS_OUT 36
+#define WS_SYS_EN  35
+
+// Partial voltage measurement method
+#define WS_BAT_ADC 1
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 11;
+static const uint8_t SCL = 10;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO17 = 17;
+static const uint8_t OUTPUT_IO18 = 18;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_185/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_185/pins_arduino.h
new file mode 100644
index 00000000000..863590e321a
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_185/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8290
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-1.85"
+#define USB_SERIAL       ""
+
+// I2C pins
+static const uint8_t SCL = 10;
+static const uint8_t SDA = 11;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_185_box/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_185_box/pins_arduino.h
new file mode 100644
index 00000000000..438da04025a
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_185_box/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x825B
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-2.1"
+#define USB_SERIAL       ""
+
+// I2C pins
+static const uint8_t SCL = 7;
+static const uint8_t SDA = 15;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_21/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_21/pins_arduino.h
new file mode 100644
index 00000000000..a6c76a7ff34
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_21/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x825E
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-2.8"
+#define USB_SERIAL       ""
+
+// I2C pins
+static const uint8_t SCL = 10;
+static const uint8_t SDA = 11;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_28/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_28/pins_arduino.h
new file mode 100644
index 00000000000..a6c76a7ff34
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_28/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x825E
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-2.8"
+#define USB_SERIAL       ""
+
+// I2C pins
+static const uint8_t SCL = 10;
+static const uint8_t SDA = 11;
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+static const uint8_t A18 = 19;
+static const uint8_t A19 = 20;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_4/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_4/pins_arduino.h
new file mode 100644
index 00000000000..f4a08ea7945
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_4/pins_arduino.h
@@ -0,0 +1,73 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x823D
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-4"
+#define USB_SERIAL       ""
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = -1;
+static const uint8_t SCL = -1;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO17 = 17;
+static const uint8_t OUTPUT_IO18 = 18;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_43/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_43/pins_arduino.h
new file mode 100644
index 00000000000..9b60b50e0c1
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_43/pins_arduino.h
@@ -0,0 +1,116 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x822E
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-4.3"
+#define USB_SERIAL       ""
+
+// display for ST7262
+#define WS_LCD_B3 14
+#define WS_LCD_B4 38
+#define WS_LCD_B5 18
+#define WS_LCD_B6 17
+#define WS_LCD_B7 10
+
+#define WS_LCD_G2 39
+#define WS_LCD_G3 0
+#define WS_LCD_G4 45
+#define WS_LCD_G5 48
+#define WS_LCD_G6 47
+#define WS_LCD_G7 21
+
+#define WS_LCD_R3 1
+#define WS_LCD_R4 2
+#define WS_LCD_R5 42
+#define WS_LCD_R6 41
+#define WS_LCD_R7 40
+
+#define WS_LCD_VSYNC 3
+#define WS_LCD_HSYNC 46
+#define WS_LCD_PCLK  7
+#define WS_LCD_DE    5
+
+// Touch for gt911
+#define WS_TP_SDA 8
+#define WS_TP_SCL 9
+#define WS_TP_RST -1
+#define WS_TP_INT 4
+
+//RS485
+#define WS_RS485_RXD 16
+#define WS_RS485_TXD 15
+
+//CAN
+#define WS_CAN_RXD 19
+#define WS_CAN_TXD 20
+
+//Onboard CH422G IO expander
+#define WS_CH422G_SDA 8
+#define WS_CH422G_SCL 9
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 11;
+static const uint8_t SCL = 10;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO17 = 17;
+static const uint8_t OUTPUT_IO18 = 18;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_43b/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_43b/pins_arduino.h
new file mode 100644
index 00000000000..f3bcb406d4c
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_43b/pins_arduino.h
@@ -0,0 +1,116 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8231
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-4.3B"
+#define USB_SERIAL       ""
+
+// display for ST7262
+#define WS_LCD_B3 14
+#define WS_LCD_B4 38
+#define WS_LCD_B5 18
+#define WS_LCD_B6 17
+#define WS_LCD_B7 10
+
+#define WS_LCD_G2 39
+#define WS_LCD_G3 0
+#define WS_LCD_G4 45
+#define WS_LCD_G5 48
+#define WS_LCD_G6 47
+#define WS_LCD_G7 21
+
+#define WS_LCD_R3 1
+#define WS_LCD_R4 2
+#define WS_LCD_R5 42
+#define WS_LCD_R6 41
+#define WS_LCD_R7 40
+
+#define WS_LCD_VSYNC 3
+#define WS_LCD_HSYNC 46
+#define WS_LCD_PCLK  7
+#define WS_LCD_DE    5
+
+// Touch for gt911
+#define WS_TP_SDA 8
+#define WS_TP_SCL 9
+#define WS_TP_RST -1
+#define WS_TP_INT 4
+
+//RS485
+#define WS_RS485_RXD 43
+#define WS_RS485_TXD 44
+
+//CAN
+#define WS_CAN_RXD 15
+#define WS_CAN_TXD 16
+
+//Onboard CH422G IO expander
+#define WS_CH422G_SDA 8
+#define WS_CH422G_SCL 9
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 11;
+static const uint8_t SCL = 10;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO17 = 17;
+static const uint8_t OUTPUT_IO18 = 18;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_5/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_5/pins_arduino.h
new file mode 100644
index 00000000000..135dc0d0895
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_5/pins_arduino.h
@@ -0,0 +1,116 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8237
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-5"
+#define USB_SERIAL       ""
+
+// display for ST7262
+#define WS_LCD_B3 14
+#define WS_LCD_B4 38
+#define WS_LCD_B5 18
+#define WS_LCD_B6 17
+#define WS_LCD_B7 10
+
+#define WS_LCD_G2 39
+#define WS_LCD_G3 0
+#define WS_LCD_G4 45
+#define WS_LCD_G5 48
+#define WS_LCD_G6 47
+#define WS_LCD_G7 21
+
+#define WS_LCD_R3 1
+#define WS_LCD_R4 2
+#define WS_LCD_R5 42
+#define WS_LCD_R6 41
+#define WS_LCD_R7 40
+
+#define WS_LCD_VSYNC 3
+#define WS_LCD_HSYNC 46
+#define WS_LCD_PCLK  7
+#define WS_LCD_DE    5
+
+// Touch for gt911
+#define WS_TP_SDA 8
+#define WS_TP_SCL 9
+#define WS_TP_RST -1
+#define WS_TP_INT 4
+
+//RS485
+#define WS_RS485_RXD 43
+#define WS_RS485_TXD 44
+
+//CAN
+#define WS_CAN_RXD 15
+#define WS_CAN_TXD 16
+
+//Onboard CH422G IO expander
+#define WS_CH422G_SDA 8
+#define WS_CH422G_SCL 9
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 11;
+static const uint8_t SCL = 10;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO17 = 17;
+static const uint8_t OUTPUT_IO18 = 18;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_5b/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_5b/pins_arduino.h
new file mode 100644
index 00000000000..e8829608a26
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_5b/pins_arduino.h
@@ -0,0 +1,116 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x823A
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-5B"
+#define USB_SERIAL       ""
+
+// display for ST7262
+#define WS_LCD_B3 14
+#define WS_LCD_B4 38
+#define WS_LCD_B5 18
+#define WS_LCD_B6 17
+#define WS_LCD_B7 10
+
+#define WS_LCD_G2 39
+#define WS_LCD_G3 0
+#define WS_LCD_G4 45
+#define WS_LCD_G5 48
+#define WS_LCD_G6 47
+#define WS_LCD_G7 21
+
+#define WS_LCD_R3 1
+#define WS_LCD_R4 2
+#define WS_LCD_R5 42
+#define WS_LCD_R6 41
+#define WS_LCD_R7 40
+
+#define WS_LCD_VSYNC 3
+#define WS_LCD_HSYNC 46
+#define WS_LCD_PCLK  7
+#define WS_LCD_DE    5
+
+// Touch for gt911
+#define WS_TP_SDA 8
+#define WS_TP_SCL 9
+#define WS_TP_RST -1
+#define WS_TP_INT 4
+
+//RS485
+#define WS_RS485_RXD 43
+#define WS_RS485_TXD 44
+
+//CAN
+#define WS_CAN_RXD 15
+#define WS_CAN_TXD 16
+
+//Onboard CH422G IO expander
+#define WS_CH422G_SDA 8
+#define WS_CH422G_SCL 9
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 11;
+static const uint8_t SCL = 10;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO17 = 17;
+static const uint8_t OUTPUT_IO18 = 18;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_touch_lcd_7/pins_arduino.h b/variants/waveshare_esp32_s3_touch_lcd_7/pins_arduino.h
new file mode 100644
index 00000000000..357edf78c34
--- /dev/null
+++ b/variants/waveshare_esp32_s3_touch_lcd_7/pins_arduino.h
@@ -0,0 +1,116 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x8234
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Touch-LCD-7"
+#define USB_SERIAL       ""
+
+// display for ST7262
+#define WS_LCD_B3 14
+#define WS_LCD_B4 38
+#define WS_LCD_B5 18
+#define WS_LCD_B6 17
+#define WS_LCD_B7 10
+
+#define WS_LCD_G2 39
+#define WS_LCD_G3 0
+#define WS_LCD_G4 45
+#define WS_LCD_G5 48
+#define WS_LCD_G6 47
+#define WS_LCD_G7 21
+
+#define WS_LCD_R3 1
+#define WS_LCD_R4 2
+#define WS_LCD_R5 42
+#define WS_LCD_R6 41
+#define WS_LCD_R7 40
+
+#define WS_LCD_VSYNC 3
+#define WS_LCD_HSYNC 46
+#define WS_LCD_PCLK  7
+#define WS_LCD_DE    5
+
+// Touch for gt911
+#define WS_TP_SDA 8
+#define WS_TP_SCL 9
+#define WS_TP_RST -1
+#define WS_TP_INT 4
+
+//RS485
+#define WS_RS485_RXD 16
+#define WS_RS485_TXD 15
+
+//CAN
+#define WS_CAN_RXD 19
+#define WS_CAN_TXD 20
+
+//Onboard CH422G IO expander
+#define WS_CH422G_SDA 8
+#define WS_CH422G_SCL 9
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 11;
+static const uint8_t SCL = 10;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO17 = 17;
+static const uint8_t OUTPUT_IO18 = 18;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32_s3_zero/pins_arduino.h b/variants/waveshare_esp32_s3_zero/pins_arduino.h
new file mode 100644
index 00000000000..0d73bee16d0
--- /dev/null
+++ b/variants/waveshare_esp32_s3_zero/pins_arduino.h
@@ -0,0 +1,81 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x303a
+#define USB_PID          0x822B
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Zero"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+// Partial voltage measurement method
+#define WS_RGB 21
+
+// Mapping based on the ESP32S3 data sheet - alternate for OUTPUT
+static const uint8_t OUTPUT_IO1 = 1;
+static const uint8_t OUTPUT_IO2 = 2;
+static const uint8_t OUTPUT_IO3 = 3;
+static const uint8_t OUTPUT_IO4 = 4;
+static const uint8_t OUTPUT_IO5 = 5;
+static const uint8_t OUTPUT_IO6 = 6;
+static const uint8_t OUTPUT_IO7 = 7;
+static const uint8_t OUTPUT_IO8 = 8;
+static const uint8_t OUTPUT_IO9 = 9;
+static const uint8_t OUTPUT_IO10 = 10;
+static const uint8_t OUTPUT_IO11 = 11;
+static const uint8_t OUTPUT_IO12 = 12;
+static const uint8_t OUTPUT_IO13 = 13;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = -1;
+static const uint8_t SCL = -1;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/waveshare_esp32s3_touch_lcd_128/pins_arduino.h b/variants/waveshare_esp32s3_touch_lcd_128/pins_arduino.h
new file mode 100644
index 00000000000..02228eb5697
--- /dev/null
+++ b/variants/waveshare_esp32s3_touch_lcd_128/pins_arduino.h
@@ -0,0 +1,37 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID          0x1A86
+#define USB_PID          0x55D3
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3 Touch LCD 1.28"
+#define USB_SERIAL       ""  // Empty string for MAC address
+
+#define LCD_BACKLIGHT 2
+#define LCD_DC        8
+#define LCD_RST       14
+
+#define TP_INT 5
+#define TP_RST 13
+
+#define IMU_INT1 4
+#define IMU_INT2 3
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+#define TX1 TX
+#define RX1 RX
+
+static const uint8_t SCL = 7;
+static const uint8_t SDA = 6;
+
+static const uint8_t SS = 9;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 12;
+static const uint8_t SCK = 10;
+
+static const uint8_t A0 = 1;  // Connected through voltage divider to battery pin
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/weact_studio_esp32c3/pins_arduino.h b/variants/weact_studio_esp32c3/pins_arduino.h
new file mode 100644
index 00000000000..fdcc730c1a0
--- /dev/null
+++ b/variants/weact_studio_esp32c3/pins_arduino.h
@@ -0,0 +1,28 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 8;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 6;
+static const uint8_t MISO = 5;
+static const uint8_t SCK = 4;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/wesp32/pins_arduino.h b/variants/wesp32/pins_arduino.h
index c3790504155..ad1ee1d225e 100644
--- a/variants/wesp32/pins_arduino.h
+++ b/variants/wesp32/pins_arduino.h
@@ -3,18 +3,10 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-#define TX1   12
-#define RX1   13
-#define TX2   33
-#define RX2   39
+#define TX1 12
+#define RX1 13
+#define TX2 33
+#define RX2 39
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -22,10 +14,10 @@ static const uint8_t RX = 3;
 static const uint8_t SCL = 4;
 static const uint8_t SDA = 15;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 32;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 32;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A3 = 39;
diff --git a/variants/widora-air/pins_arduino.h b/variants/widora-air/pins_arduino.h
index 52ecdd554e8..2240bbeeae2 100644
--- a/variants/widora-air/pins_arduino.h
+++ b/variants/widora-air/pins_arduino.h
@@ -3,18 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        7
-#define NUM_ANALOG_INPUTS       10
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 25;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t KEY_BUILTIN = 0;
 
@@ -24,10 +15,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 23;
 static const uint8_t SCL = 19;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 16;
-static const uint8_t MISO  = 17;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 16;
+static const uint8_t MISO = 17;
+static const uint8_t SCK = 18;
 
 static const uint8_t A0 = 36;
 static const uint8_t A1 = 39;
diff --git a/variants/wifiduino32/pins_arduino.h b/variants/wifiduino32/pins_arduino.h
index 63c04ff9eee..5334a5c354f 100644
--- a/variants/wifiduino32/pins_arduino.h
+++ b/variants/wifiduino32/pins_arduino.h
@@ -1,68 +1,59 @@
-#ifndef Pins_Arduino_h
-#define Pins_Arduino_h
-
-#include <stdint.h>
-
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-static const uint8_t LED_BUILTIN = 2;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-
-static const uint8_t KEY_BUILTIN = 0;
-
-static const uint8_t TX = 1;
-static const uint8_t RX = 3;
-
-static const uint8_t SDA = 5;
-static const uint8_t SCL = 16;
-
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
-
-static const uint8_t A0 = 27;
-static const uint8_t A1 = 14;
-static const uint8_t A2 = 12;
-static const uint8_t A3 = 35;
-static const uint8_t A4 = 13;
-static const uint8_t A5 = 4;
-
-
-static const uint8_t D0 = 3;
-static const uint8_t D1 = 1;
-static const uint8_t D2 = 17;
-static const uint8_t D3 = 15;
-static const uint8_t D4 = 32;
-static const uint8_t D5 = 33;
-static const uint8_t D6 = 25;
-static const uint8_t D7 = 26;
-static const uint8_t D8 = 23;
-static const uint8_t D9 = 22;
-static const uint8_t D10 = 21;
-static const uint8_t D11 = 19;
-static const uint8_t D12 = 18;
-static const uint8_t D13 = 2;
-
-static const uint8_t T0 = 4;
-static const uint8_t T1 = 0;
-static const uint8_t T2 = 2;
-static const uint8_t T3 = 15;
-static const uint8_t T4 = 13;
-static const uint8_t T5 = 12;
-static const uint8_t T6 = 14;
-static const uint8_t T7 = 27;
-static const uint8_t T8 = 33;
-static const uint8_t T9 = 32;
-
-static const uint8_t DAC1 = 25;
-static const uint8_t DAC2 = 26;
-
-#endif /* Pins_Arduino_h */
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 2;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t KEY_BUILTIN = 0;
+
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+static const uint8_t SDA = 5;
+static const uint8_t SCL = 16;
+
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
+
+static const uint8_t A0 = 27;
+static const uint8_t A1 = 14;
+static const uint8_t A2 = 12;
+static const uint8_t A3 = 35;
+static const uint8_t A4 = 13;
+static const uint8_t A5 = 4;
+
+static const uint8_t D0 = 3;
+static const uint8_t D1 = 1;
+static const uint8_t D2 = 17;
+static const uint8_t D3 = 15;
+static const uint8_t D4 = 32;
+static const uint8_t D5 = 33;
+static const uint8_t D6 = 25;
+static const uint8_t D7 = 26;
+static const uint8_t D8 = 23;
+static const uint8_t D9 = 22;
+static const uint8_t D10 = 21;
+static const uint8_t D11 = 19;
+static const uint8_t D12 = 18;
+static const uint8_t D13 = 2;
+
+static const uint8_t T0 = 4;
+static const uint8_t T1 = 0;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 15;
+static const uint8_t T4 = 13;
+static const uint8_t T5 = 12;
+static const uint8_t T6 = 14;
+static const uint8_t T7 = 27;
+static const uint8_t T8 = 33;
+static const uint8_t T9 = 32;
+
+static const uint8_t DAC1 = 25;
+static const uint8_t DAC2 = 26;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/wifiduino32s3/pins_arduino.h b/variants/wifiduino32s3/pins_arduino.h
new file mode 100644
index 00000000000..d26e415910e
--- /dev/null
+++ b/variants/wifiduino32s3/pins_arduino.h
@@ -0,0 +1,44 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+// No USER LED or NeoLED
+
+static const uint8_t TX = 45;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 5;
+
+static const uint8_t SS = 46;
+static const uint8_t MOSI = 3;
+static const uint8_t MISO = 20;
+static const uint8_t SCK = 19;
+
+static const uint8_t A0 = 7;
+static const uint8_t A1 = 6;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 1;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+static const uint8_t D0 = 44;
+static const uint8_t D1 = 45;
+static const uint8_t D2 = 42;
+static const uint8_t D3 = 41;
+static const uint8_t D4 = 0;
+static const uint8_t D5 = 45;
+static const uint8_t D6 = 48;
+static const uint8_t D7 = 47;
+static const uint8_t D8 = 21;
+static const uint8_t D9 = 14;
+static const uint8_t D10 = 46;
+static const uint8_t D11 = 3;
+static const uint8_t D12 = 20;
+static const uint8_t D13 = 19;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/wifiduinov2/pins_arduino.h b/variants/wifiduinov2/pins_arduino.h
new file mode 100644
index 00000000000..916de50e642
--- /dev/null
+++ b/variants/wifiduinov2/pins_arduino.h
@@ -0,0 +1,43 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 13;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 21;
+static const uint8_t RX = 20;
+
+static const uint8_t SDA = 4;
+static const uint8_t SCL = 5;
+
+static const uint8_t SS = 7;
+static const uint8_t MOSI = 3;
+static const uint8_t MISO = 10;
+static const uint8_t SCK = 2;
+
+static const uint8_t A0 = 0;
+static const uint8_t A1 = 1;
+static const uint8_t A2 = 2;
+static const uint8_t A3 = 3;
+static const uint8_t A4 = 4;
+static const uint8_t A5 = 5;
+
+static const uint8_t D0 = 20;
+static const uint8_t D1 = 21;
+static const uint8_t D2 = 9;
+static const uint8_t D3 = 13;
+static const uint8_t D4 = 12;
+static const uint8_t D5 = 11;
+static const uint8_t D6 = 6;
+static const uint8_t D7 = 18;
+static const uint8_t D8 = 19;
+static const uint8_t D9 = 8;
+static const uint8_t D10 = 7;
+static const uint8_t D11 = 3;
+static const uint8_t D12 = 10;
+static const uint8_t D13 = 2;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/wipy3/pins_arduino.h b/variants/wipy3/pins_arduino.h
index c8d9888eb9f..a9fda1ecaa3 100644
--- a/variants/wipy3/pins_arduino.h
+++ b/variants/wipy3/pins_arduino.h
@@ -2,20 +2,19 @@
 #define Pins_Arduino_h
 
 #include <stdint.h>
+#include "soc/soc_caps.h"
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       18
+// RGB LED
+#define PIN_RGB_LED 0  // ->2812 RGB !!!
+// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino
+static const uint8_t LED_BUILTIN = (PIN_RGB_LED + SOC_GPIO_PIN_COUNT);
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite()
+#define RGB_BUILTIN    LED_BUILTIN
+#define RGB_BRIGHTNESS 64
 
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
-static const uint8_t LED_BUILTIN = 0; // ->2812 RGB !!!
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
-
-#define ANT_SELECT 21   // GPIO21 - External Antenna Switch
+#define ANT_SELECT 21  // GPIO21 - External Antenna Switch
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -23,10 +22,10 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 12;
 static const uint8_t SCL = 13;
 
-static const uint8_t SS    = 2;
-static const uint8_t MOSI  = 22;
-static const uint8_t MISO  = 37;
-static const uint8_t SCK   = 13;
+static const uint8_t SS = 2;
+static const uint8_t MOSI = 22;
+static const uint8_t MISO = 37;
+static const uint8_t SCK = 13;
 
 static const uint8_t A0 = 36;
 static const uint8_t A1 = 37;
diff --git a/variants/ws_esp32_s3_matrix/partitions_all_app_4MB.csv b/variants/ws_esp32_s3_matrix/partitions_all_app_4MB.csv
new file mode 100755
index 00000000000..25eeb8c7d47
--- /dev/null
+++ b/variants/ws_esp32_s3_matrix/partitions_all_app_4MB.csv
@@ -0,0 +1,3 @@
+# Name,    Type,  SubType,     Offset,      Size,  Flags
+nvs,       data,  nvs,         0x9000,    0x5000,
+factory,   app,   factory,    0x10000,  0x3F0000,
diff --git a/variants/ws_esp32_s3_matrix/partitions_otanofs_4MB.csv b/variants/ws_esp32_s3_matrix/partitions_otanofs_4MB.csv
new file mode 100755
index 00000000000..04240badb49
--- /dev/null
+++ b/variants/ws_esp32_s3_matrix/partitions_otanofs_4MB.csv
@@ -0,0 +1,6 @@
+#   Name, Type,  SubType,   Offset,      Size, Flags
+     nvs, data,      nvs,   0x9000,    0x5000,
+ otadata, data,      ota,   0xE000,    0x2000,
+    app0,  app,    ota_0,  0x10000,  0x1F0000,
+    app1,  app,    ota_1, 0x200000,  0x1F0000,
+coredump, data, coredump, 0x3F0000,   0x10000,
diff --git a/variants/ws_esp32_s3_matrix/pins_arduino.h b/variants/ws_esp32_s3_matrix/pins_arduino.h
new file mode 100644
index 00000000000..ab067055c8e
--- /dev/null
+++ b/variants/ws_esp32_s3_matrix/pins_arduino.h
@@ -0,0 +1,77 @@
+
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+#include "soc/soc_caps.h"
+
+// BN: ESP32 Family Device
+#define USB_VID 0x303a
+#define USB_PID 0x1001
+
+#define USB_MANUFACTURER "Waveshare"
+#define USB_PRODUCT      "ESP32-S3-Matrix"
+#define USB_SERIAL       ""
+
+// Onboard 8 x 8 Matrix panel
+#define WS_MATRIX_DIN 14
+
+// Onboard  QMI8658 IMU
+#define WS_IMU_SDA     11
+#define WS_IMU_SCL     12
+#define WS_IMU_ADDRESS 0x6B
+#define WS_IMU_INT1    10
+#define WS_IMU_INT2    13
+
+// UART0 pins
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+// Def for I2C that shares the IMU I2C pins
+static const uint8_t SDA = 11;
+static const uint8_t SCL = 12;
+
+// Mapping based on the ESP32S3 data sheet - alternate for SPI2
+static const uint8_t SS = 34;    // FSPICS0
+static const uint8_t MOSI = 35;  // FSPID
+static const uint8_t MISO = 37;  // FSPIQ
+static const uint8_t SCK = 36;   // FSPICLK
+
+// Analog capable pins on the header
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+
+// GPIO capable pins on the header
+static const uint8_t D0 = 7;
+static const uint8_t D1 = 6;
+static const uint8_t D2 = 5;
+static const uint8_t D3 = 4;
+static const uint8_t D4 = 3;
+static const uint8_t D5 = 2;
+static const uint8_t D6 = 1;
+static const uint8_t D7 = 44;
+static const uint8_t D8 = 43;
+static const uint8_t D9 = 40;
+static const uint8_t D10 = 39;
+static const uint8_t D11 = 38;
+static const uint8_t D12 = 37;
+static const uint8_t D13 = 36;
+static const uint8_t D14 = 35;
+static const uint8_t D15 = 34;
+static const uint8_t D16 = 33;
+
+// Touch input capable pins on the header
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/wt32-eth01/pins_arduino.h b/variants/wt32-eth01/pins_arduino.h
new file mode 100644
index 00000000000..f5fb7041613
--- /dev/null
+++ b/variants/wt32-eth01/pins_arduino.h
@@ -0,0 +1,57 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+/**
+ * Variant: WT32-ETH01
+ * Vendor: Wireless-Tag
+ * Url: http://www.wireless-tag.com/portfolio/wt32-eth01/
+ */
+
+#include <stdint.h>
+
+// interface to Ethernet PHY (LAN8720A)
+#define ETH_PHY_ADDR  1
+#define ETH_PHY_POWER 16
+#define ETH_PHY_MDC   23
+#define ETH_PHY_MDIO  18
+#define ETH_PHY_TYPE  ETH_PHY_LAN8720
+#define ETH_CLK_MODE  ETH_CLOCK_GPIO0_IN
+
+// general purpose IO pins
+static const uint8_t IO0 = 0;
+static const uint8_t IO1 = 1;  // TXD0 / TX0 pin
+static const uint8_t IO2 = 2;
+static const uint8_t IO3 = 3;  // RXD0 / RX0 pin
+static const uint8_t IO4 = 4;
+static const uint8_t IO5 = 5;  // RXD2 / RXD pin
+static const uint8_t IO12 = 12;
+static const uint8_t IO14 = 14;
+static const uint8_t IO15 = 15;
+static const uint8_t IO17 = 17;  // TXD2 / TXD pin
+static const uint8_t IO32 = 32;  // CFG pin
+static const uint8_t IO33 = 33;  // 485_EN pin
+
+// input-only pins
+static const uint8_t IO35 = 35;
+static const uint8_t IO36 = 36;
+static const uint8_t IO39 = 39;
+
+// UART interfaces
+static const uint8_t TXD0 = 1, TX0 = 1;
+static const uint8_t RXD0 = 3, RX0 = 3;
+static const uint8_t TXD2 = 17, TXD = 17;
+static const uint8_t RXD2 = 5, RXD = 5;
+static const uint8_t TX = 1;
+static const uint8_t RX = 3;
+
+//SPI VSPI default pins
+static const uint8_t SS = -1;
+static const uint8_t MOSI = 14;
+static const uint8_t MISO = 15;
+static const uint8_t SCK = 12;
+
+//I2C default pins
+static const uint8_t SDA = 33;
+static const uint8_t SCL = 32;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/wt32-sc01-plus/bootloader_tinyuf2.bin b/variants/wt32-sc01-plus/bootloader_tinyuf2.bin
new file mode 100644
index 00000000000..e89596f423d
Binary files /dev/null and b/variants/wt32-sc01-plus/bootloader_tinyuf2.bin differ
diff --git a/variants/wt32-sc01-plus/partitions_tinyuf2.csv b/variants/wt32-sc01-plus/partitions_tinyuf2.csv
new file mode 100644
index 00000000000..4026378b6fb
--- /dev/null
+++ b/variants/wt32-sc01-plus/partitions_tinyuf2.csv
@@ -0,0 +1,10 @@
+# ESP-IDF Partition Table
+# Name,   Type, SubType, Offset,  Size, Flags
+# bootloader.bin,,          0x1000, 32K
+# partition table,,         0x8000, 4K
+nvs,      data, nvs,      0x9000,  20K,
+otadata,  data, ota,      0xe000,  8K,
+ota_0,    0,    ota_0,   0x10000,  2048K,
+ota_1,    0,    ota_1,  0x210000,  2048K,
+uf2,      app,  factory,0x410000,  256K,
+ffat,     data, fat,    0x450000,  3776K,
diff --git a/variants/wt32-sc01-plus/pins_arduino.h b/variants/wt32-sc01-plus/pins_arduino.h
new file mode 100644
index 00000000000..ef418d9f485
--- /dev/null
+++ b/variants/wt32-sc01-plus/pins_arduino.h
@@ -0,0 +1,64 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+/**
+ * Variant: WT32-SC01 PLUS
+ * Vendor: Wireless-Tag
+ * Url: http://www.wireless-tag.com/portfolio/wt32-eth01/
+ */
+
+#include <stdint.h>
+
+#define USB_VID          0x303A
+#define USB_PID          0x80D0
+#define USB_MANUFACTURER "PANLEE"
+#define USB_PRODUCT      "SC01PLUS"
+#define USB_SERIAL       ""
+//GENERAL I/O
+static const uint8_t BOOT_0 = 0;
+static const uint8_t IO1 = 10;
+static const uint8_t IO2 = 11;
+static const uint8_t IO3 = 12;
+static const uint8_t IO4 = 13;
+static const uint8_t IO5 = 14;
+static const uint8_t IO6 = 21;
+//RS485
+static const uint8_t TX = 42;
+static const uint8_t RX = 1;
+static const uint8_t RTS = 2;
+//TOUCHSCREEN
+static const uint8_t BL_PWM = 45;    //BACKLIGHT PWM
+static const uint8_t LCD_RESET = 4;  //LCD RESET, MULTIPLEXED WITH TOUCH RESET
+static const uint8_t LCD_RS = 0;     //COMMAND/DATA
+static const uint8_t LCD_WR = 47;    //WRITE CLOCK
+static const uint8_t LCD_TE = 48;    //FRAME SYNC
+static const uint8_t LCD_DB0 = 9;
+static const uint8_t LCD_DB1 = 46;
+static const uint8_t LCD_DB2 = 3;
+static const uint8_t LCD_DB3 = 8;
+static const uint8_t LCD_DB4 = 18;
+static const uint8_t LCD_DB5 = 17;
+static const uint8_t LCD_DB6 = 16;
+static const uint8_t LCD_DB7 = 15;
+
+//SPEAKER
+static const uint8_t LRCK = 35;
+static const uint8_t BCLK = 36;
+static const uint8_t DOUT = 37;
+
+//TOUCHSCREEN DIGITIZER
+static const uint8_t TP_INT = 7;
+static const uint8_t SDA = 6;
+static const uint8_t SCL = 5;
+static const uint8_t RST = 4;
+//MICRO SD CARD
+static const uint8_t SD_CS = 41;
+static const uint8_t SD_DI = 40;  //MOSI
+static const uint8_t SD_DO = 38;  //MISO
+static const uint8_t SD_CLK = 39;
+static const uint8_t SS = 41;
+static const uint8_t MOSI = 40;
+static const uint8_t MISO = 38;
+static const uint8_t SCK = 39;
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/wt32-sc01-plus/tinyuf2.bin b/variants/wt32-sc01-plus/tinyuf2.bin
new file mode 100644
index 00000000000..b2723dcf3b9
Binary files /dev/null and b/variants/wt32-sc01-plus/tinyuf2.bin differ
diff --git a/variants/xinabox/pins_arduino.h b/variants/xinabox/pins_arduino.h
index 3a1763f23ad..eeabcd7858a 100644
--- a/variants/xinabox/pins_arduino.h
+++ b/variants/xinabox/pins_arduino.h
@@ -3,17 +3,9 @@
 
 #include <stdint.h>
 
-#define EXTERNAL_NUM_INTERRUPTS 16
-#define NUM_DIGITAL_PINS        40
-#define NUM_ANALOG_INPUTS       16
-
-#define analogInputToDigitalPin(p)  (((p)<20)?(esp32_adc2gpio[(p)]):-1)
-#define digitalPinToInterrupt(p)    (((p)<40)?(p):-1)
-#define digitalPinHasPWM(p)         (p < 34)
-
 static const uint8_t LED_BUILTIN = 27;
-#define BUILTIN_LED  LED_BUILTIN // backward compatibility
-#define LED_BUILTIN LED_BUILTIN
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
 
 static const uint8_t TX = 1;
 static const uint8_t RX = 3;
@@ -21,9 +13,9 @@ static const uint8_t RX = 3;
 static const uint8_t SDA = 21;
 static const uint8_t SCL = 22;
 
-static const uint8_t SS    = 5;
-static const uint8_t MOSI  = 23;
-static const uint8_t MISO  = 19;
-static const uint8_t SCK   = 18;
+static const uint8_t SS = 5;
+static const uint8_t MOSI = 23;
+static const uint8_t MISO = 19;
+static const uint8_t SCK = 18;
 
 #endif /* Pins_Arduino_h */
diff --git a/variants/yb_esp32s3_amp_v2/pins_arduino.h b/variants/yb_esp32s3_amp_v2/pins_arduino.h
new file mode 100644
index 00000000000..34d454f5f5e
--- /dev/null
+++ b/variants/yb_esp32s3_amp_v2/pins_arduino.h
@@ -0,0 +1,57 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+static const uint8_t LED_BUILTIN = 47;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+//I2S for onboard MAX98357A only
+static const uint8_t I2S_BCLK = 5;
+static const uint8_t I2S_LRCLK = 6;
+static const uint8_t I2S_DOUT = 7;
+
+// SPI for onboard microSD only
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+// SPI2 for public usage
+static const uint8_t SS2 = 38;
+static const uint8_t MOSI2 = 39;
+static const uint8_t MISO2 = 41;
+static const uint8_t SCK2 = 40;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 8;
+static const uint8_t A5 = 9;
+static const uint8_t A6 = 10;
+static const uint8_t A7 = 14;
+static const uint8_t A8 = 15;
+static const uint8_t A9 = 16;
+static const uint8_t A10 = 17;
+static const uint8_t A11 = 18;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T14 = 14;
+
+#define PIN_DAC_MUTE 47  // only if solder bridge "DAC_MUTE" is closed
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/yb_esp32s3_amp_v3/pins_arduino.h b/variants/yb_esp32s3_amp_v3/pins_arduino.h
new file mode 100644
index 00000000000..0b6ff0f29a1
--- /dev/null
+++ b/variants/yb_esp32s3_amp_v3/pins_arduino.h
@@ -0,0 +1,60 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303A
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = 47;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+//I2S for onboard MAX98357A only
+static const uint8_t I2S_BCLK = 5;
+static const uint8_t I2S_LRCLK = 6;
+static const uint8_t I2S_DOUT = 7;
+
+// SPI for onboard microSD only
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+// SPI2 for public usage
+static const uint8_t SS2 = 38;
+static const uint8_t MOSI2 = 39;
+static const uint8_t MISO2 = 41;
+static const uint8_t SCK2 = 40;
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 8;
+static const uint8_t A5 = 9;
+static const uint8_t A6 = 10;
+static const uint8_t A7 = 14;
+static const uint8_t A8 = 15;
+static const uint8_t A9 = 16;
+static const uint8_t A10 = 17;
+static const uint8_t A11 = 18;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T14 = 14;
+
+#define PIN_DAC_MUTE 47  // only if solder bridge "DAC_MUTE" is closed
+
+#endif /* Pins_Arduino_h */
diff --git a/variants/yb_esp32s3_eth/pins_arduino.h b/variants/yb_esp32s3_eth/pins_arduino.h
new file mode 100644
index 00000000000..77fcf6923fc
--- /dev/null
+++ b/variants/yb_esp32s3_eth/pins_arduino.h
@@ -0,0 +1,63 @@
+#ifndef Pins_Arduino_h
+#define Pins_Arduino_h
+
+#include <stdint.h>
+
+#define USB_VID 0x303A
+#define USB_PID 0x1001
+
+static const uint8_t LED_BUILTIN = 47;
+#define BUILTIN_LED LED_BUILTIN  // backward compatibility
+#define LED_BUILTIN LED_BUILTIN  // allow testing #ifdef LED_BUILTIN
+
+static const uint8_t TX = 43;
+static const uint8_t RX = 44;
+
+static const uint8_t SDA = 8;
+static const uint8_t SCL = 9;
+
+static const uint8_t SS = 10;
+static const uint8_t MOSI = 11;
+static const uint8_t MISO = 13;
+static const uint8_t SCK = 12;
+
+// Definitions for onboard WIZnet W5500 ethernet controller chip
+static const uint8_t W5500_SS = 14;   // W5500 chip select
+static const uint8_t W5500_INT = 18;  // available only if solder bridge "INT" is closed (default open)
+static const uint8_t W5500_RST = 21;  // set GPIO21 to INPUT (high impedance) if RST signal is unused
+
+static const uint8_t A0 = 1;
+static const uint8_t A1 = 2;
+static const uint8_t A2 = 3;
+static const uint8_t A3 = 4;
+static const uint8_t A4 = 5;
+static const uint8_t A5 = 6;
+static const uint8_t A6 = 7;
+static const uint8_t A7 = 8;
+static const uint8_t A8 = 9;
+static const uint8_t A9 = 10;
+static const uint8_t A10 = 11;
+static const uint8_t A11 = 12;
+static const uint8_t A12 = 13;
+static const uint8_t A13 = 14;
+static const uint8_t A14 = 15;
+static const uint8_t A15 = 16;
+static const uint8_t A16 = 17;
+static const uint8_t A17 = 18;
+
+static const uint8_t T1 = 1;
+static const uint8_t T2 = 2;
+static const uint8_t T3 = 3;
+static const uint8_t T4 = 4;
+static const uint8_t T5 = 5;
+static const uint8_t T6 = 6;
+static const uint8_t T7 = 7;
+static const uint8_t T8 = 8;
+static const uint8_t T9 = 9;
+static const uint8_t T10 = 10;
+static const uint8_t T11 = 11;
+static const uint8_t T12 = 12;
+static const uint8_t T13 = 13;
+static const uint8_t T14 = 14;
+
+#endif /* Pins_Arduino_h */